added boot script files to repository

2616 files changed, 514134 insertions, 0 deletions

diff --git a/u-boot/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/u-boot/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
new file mode 100644
index 0000000..d64ad1b
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2005-2009
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include "asm/m5282.h"
+#include <bmp_layout.h>
+#include <status_led.h>
+#include <bus_vcxk.h>
+
+/*---------------------------------------------------------------------------*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long display_width;
+unsigned long display_height;
+
+/*---------------------------------------------------------------------------*/
+
+int checkboard (void)
+{
+	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
+#if (CONFIG_SYS_TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
+	puts ("       Boot from Internal FLASH\n");
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	int size, i;
+
+	size = 0;
+	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
+			| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
+#ifdef CONFIG_SYS_SDRAM_BASE0
+
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
+			| MCFSDRAMC_DACR_CASL (1)
+			| MCFSDRAMC_DACR_CBM (3)
+			| MCFSDRAMC_DACR_PS_16;
+
+	MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+	for (i = 0; i < 2000; i++)
+		asm (" nop");
+	mbar_writeLong (MCFSDRAMC_DACR0,
+			mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+			| MCFSDRAMC_DACR_CASL (1)
+			| MCFSDRAMC_DACR_CBM (3)
+			| MCFSDRAMC_DACR_PS_16;
+
+	MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
+
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
+
+	for (i = 0; i < 2000; i++)
+		asm (" nop");
+
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+#endif
+	return size;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef	CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+#ifndef CONFIG_VIDEO
+	vcxk_init(16, 16);
+#endif
+	return 1;
+}
+
+#if defined(CONFIG_VIDEO)
+
+/*
+ ****h* EB+CPU5282-T1/drv_video_init
+ * FUNCTION
+ ***
+ */
+
+int drv_video_init(void)
+{
+	char *s;
+	unsigned long splash;
+
+	printf("Init Video as ");
+
+	if ((s = getenv("displaywidth")) != NULL)
+		display_width = simple_strtoul(s, NULL, 10);
+	else
+		display_width = 256;
+
+	if ((s = getenv("displayheight")) != NULL)
+		display_height = simple_strtoul(s, NULL, 10);
+	else
+		display_height = 256;
+
+	printf("%lu x %lu pixel matrix\n", display_width, display_height);
+
+	MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
+	MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
+
+	vcxk_init(display_width, display_height);
+
+#ifdef CONFIG_SPLASH_SCREEN
+	if ((s = getenv("splashimage")) != NULL) {
+		debug("use splashimage: %s\n", s);
+		splash = simple_strtoul(s, NULL, 16);
+		debug("use splashimage: %x\n", splash);
+		vcxk_acknowledge_wait();
+		video_display_bitmap(splash, 0, 0);
+	}
+#endif
+	return 0;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CONFIG_VIDEO
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = 0;
+	ulong side;
+	ulong bright;
+
+	switch (argc) {
+	case 3:
+		side = simple_strtoul(argv[1], NULL, 10);
+		bright = simple_strtoul(argv[2], NULL, 10);
+		if ((side >= 0) && (side <= 3) &&
+			(bright >= 0) && (bright <= 1000)) {
+			vcxk_setbrightness(side, bright);
+			rcode = 0;
+		} else {
+			printf("parameters out of range\n");
+			printf("Usage:\n%s\n", cmdtp->usage);
+			rcode = 1;
+		}
+		break;
+	default:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+	bright,	3,	0,	do_brightness,
+	"sets the display brightness\n",
+	" <side> <0..1000>\n        side: 0/3=both; 1=first; 2=second\n"
+);
+
+#endif
+
+/* EOF EB+MCF-EV123.c */
diff --git a/u-boot/board/BuS/EB+MCF-EV123/Makefile b/u-boot/board/BuS/EB+MCF-EV123/Makefile
new file mode 100644
index 0000000..0f14699
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o cfm_flash.o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/BuS/EB+MCF-EV123/cfm_flash.c b/u-boot/board/BuS/EB+MCF-EV123/cfm_flash.c
new file mode 100644
index 0000000..fe03b17
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/cfm_flash.c
@@ -0,0 +1,212 @@
+/*
+ * Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5282.h>
+#include  "cfm_flash.h"
+
+#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
+
+#if (CONFIG_SYS_CLK>20000000)
+	#define CFM_CLK  (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
+#else
+	#define CFM_CLK  ((long) CONFIG_SYS_CLK / 400000 + 1)
+#endif
+
+#define cmf_backdoor_address(addr)	(((addr) & 0x0007FFFF) | 0x04000000 | \
+					 (CONFIG_SYS_MBAR & 0xC0000000))
+
+void cfm_flash_print_info (flash_info_t * info)
+{
+	printf ("Freescale: ");
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
+		printf ("MCF5281 internal FLASH\n");
+		break;
+	case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
+		printf ("MCF5282 internal FLASH\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+}
+
+void cfm_flash_init (flash_info_t * info)
+{
+	int sector;
+	ulong protection;
+	MCFCFM_MCR = 0;
+	MCFCFM_CLKD = CFM_CLK;
+	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
+		CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CONFIG_SYS_CLK);
+	MCFCFM_SACC = 0;
+	MCFCFM_DACC = 0;
+
+	if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
+		puts("CFM backdoor access is enabled\n");
+	if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
+		puts("CFM securety is enabled\n");
+
+	#ifdef CONFIG_M5281
+		info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
+				 (FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
+		info->size = 256*1024;
+		info->sector_count = 16;
+	#else
+		info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
+				 (FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
+		info->size = 512*1024;
+		info->sector_count = 32;
+	#endif
+	protection = MCFCFM_PROT;
+	for (sector = 0; sector < info->sector_count; sector++)
+	{
+		if (sector == 0)
+		{
+			info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
+		}
+		else
+		{
+			info->start[sector] = info->start[sector-1] + 0x04000;
+		}
+		info->protect[sector] = protection & 1;
+		protection >>= 1;
+	}
+}
+
+int cfm_flash_readycheck(int checkblank)
+{
+	int	rc;
+	unsigned char state;
+
+	rc	= ERR_OK;
+	while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
+	state = MCFCFM_USTAT;
+	if (state & MCFCFM_USTAT_ACCERR)
+	{
+		debug ("%s(): CFM access error",__FUNCTION__);
+		rc = ERR_PROG_ERROR;
+	}
+	if (state & MCFCFM_USTAT_PVIOL)
+	{
+		debug ("%s(): CFM protection violation",__FUNCTION__);
+		rc = ERR_PROTECTED;
+	}
+	if (checkblank)
+	{
+		if (!(state & MCFCFM_USTAT_BLANK))
+		{
+			debug ("%s(): CFM erras error",__FUNCTION__);
+			rc = ERR_NOT_ERASED;
+		}
+	}
+	MCFCFM_USTAT = state & 0x34; /* reset state */
+	return rc;
+}
+
+/* Erase 16KiB = 8 2KiB pages */
+
+int cfm_flash_erase_sector (flash_info_t * info, int sector)
+{
+	ulong address;
+	int page;
+	int rc;
+	rc= ERR_OK;
+	address = cmf_backdoor_address(info->start[sector]);
+	for (page=0; (page<8) && (rc==ERR_OK); page++)
+	{
+		*(volatile __u32*) address = 0;
+		MCFCFM_CMD = MCFCFM_CMD_PGERS;
+		MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+		rc = cfm_flash_readycheck(0);
+		if (rc==ERR_OK)
+		{
+			*(volatile __u32*) address = 0;
+			MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
+			MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+			rc = cfm_flash_readycheck(1);
+		}
+		address += 0x800;
+	}
+	return rc;
+}
+
+int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+	ulong dest, data;
+
+	rc = ERR_OK;
+	if (addr & 3)
+	{
+		debug ("Byte and Word alignment not supported\n");
+		rc = ERR_ALIGN;
+	}
+	if (cnt & 3)
+	{
+		debug ("Byte and Word transfer not supported\n");
+		rc = ERR_ALIGN;
+	}
+	dest = cmf_backdoor_address(addr);
+	while ((cnt>=4) && (rc == ERR_OK))
+	{
+		data = *((volatile u32 *) src);
+		*(volatile u32*) dest = data;
+		MCFCFM_CMD = MCFCFM_CMD_PGM;
+		MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+		rc = cfm_flash_readycheck(0);
+		if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
+		src +=4;
+		dest +=4;
+		addr +=4;
+		cnt -=4;
+	}
+	return rc;
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+
+int cfm_flash_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+
+	rc= ERR_OK;
+	if (prot)
+	{
+		MCFCFM_PROT |= (1<<sector);
+		info->protect[sector]=1;
+	}
+	else
+	{
+		MCFCFM_PROT &= ~(1<<sector);
+		info->protect[sector]=0;
+	}
+	return rc;
+}
+
+#endif
+
+#endif
diff --git a/u-boot/board/BuS/EB+MCF-EV123/cfm_flash.h b/u-boot/board/BuS/EB+MCF-EV123/cfm_flash.h
new file mode 100644
index 0000000..ed4e794
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/cfm_flash.h
@@ -0,0 +1,40 @@
+/*
+ * Basic Flash Driver for Freescale MCF 5282 internal FLASH
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CFM_FLASH_H_
+#define __CFM_FLASH_H_
+
+#define	FREESCALE_MANUFACT 0xFACFFACF
+#define	FREESCALE_ID_MCF5281 0x5281
+#define	FREESCALE_ID_MCF5282 0x5282
+
+extern void cfm_flash_print_info (flash_info_t * info);
+extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
+extern void cfm_flash_init (flash_info_t * info);
+extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
+#endif
+
+#endif
diff --git a/u-boot/board/BuS/EB+MCF-EV123/config.mk b/u-boot/board/BuS/EB+MCF-EV123/config.mk
new file mode 100644
index 0000000..50185ae
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0xFE000000
+endif
diff --git a/u-boot/board/BuS/EB+MCF-EV123/flash.c b/u-boot/board/BuS/EB+MCF-EV123/flash.c
new file mode 100644
index 0000000..3c36367
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/flash.c
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * Based On
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include  "cfm_flash.h"
+
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV160B & FLASH_TYPEMASK):
+			printf ("AM29LV160B (16Bit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			break;
+		}
+		break;
+	case FREESCALE_MANUFACT & FLASH_VENDMASK:
+		cfm_flash_print_info (info);
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	puts ("  Size: ");
+	if ((info->size >> 20) > 0)
+	{
+		printf ("%ld MiB",info->size >> 20);
+	}
+	else
+	{
+		printf ("%ld KiB",info->size >> 10);
+	}
+	printf (" in %d Sectors\n", info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0) {
+			printf ("\n    ");
+		}
+		printf ("%02d: %08lX%s  ", i,info->start[i],
+			info->protect[i] ? " P" : "  ");
+	}
+	printf ("\n\n");
+}
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		switch (i)
+		{
+		case 1:
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV160B & FLASH_TYPEMASK);
+			flash_info[i].size = FLASH_BANK_SIZE;
+			flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+			memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+			flashbase = PHYS_FLASH_1;
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				if (j == 0) {
+					/* 1st is 16 KiB */
+					flash_info[i].start[j] = flashbase;
+				}
+				if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + 0x2000 * (j - 1);
+				}
+				if (j == 3) {
+					/* 4th is 32 KiB */
+					flash_info[i].start[j] = flashbase + 0x8000;
+				}
+				if ((j >= 4) && (j <= 34)) {
+					/* rest is 256 KiB */
+					flash_info[i].start[j] =
+						flashbase + 0x10000 + 0x10000 * (j - 4);
+				}
+			}
+			break;
+		case 0:
+			cfm_flash_init (&flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+		}
+
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
+
+	return size;
+}
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
+
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define ERR_READY -1
+
+int amd_flash_erase_sector(flash_info_t * info, int sector)
+{
+	int state;
+	ulong result;
+
+	volatile u16 *addr =
+				(volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	*addr = CMD_ERASE_CONFIRM;
+
+	/* wait until flash is ready */
+	state = 0;
+	set_timer (0);
+
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+			state = ERR_TIMOUT;
+		}
+
+		if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
+			state = ERR_READY;
+	}
+	while (!state);
+	if (state == ERR_READY)
+		state = ERR_OK;
+
+	MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+	return state;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int iflag, cflag;
+	int sector;
+	int rc;
+
+	rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		rc = ERR_UNKNOWN_FLASH_TYPE;
+	} /* (info->flash_id == FLASH_UNKNOWN) */
+
+	if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
+	{
+		rc = ERR_INVAL;
+	}
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
+
+		if (info->protect[sector])
+		{
+			putc('P'); /*  protected sector will not erase */
+		}
+		else
+		{
+			/* erase on unprotected sector */
+			puts("E\b");
+			switch (info->flash_id & FLASH_VENDMASK)
+			{
+			case (AMD_MANUFACT & FLASH_VENDMASK):
+				rc = amd_flash_erase_sector(info,sector);
+				break;
+			case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+				rc = cfm_flash_erase_sector(info,sector);
+				break;
+			default:
+				return ERR_UNKNOWN_FLASH_VENDOR;
+			}
+			putc('.');
+		}
+	}
+	if (rc!=ERR_OK)
+	{
+		printf ("\n   ");
+		flash_perror (rc);
+	}
+	else
+	{
+		printf (" done\n");
+	}
+
+	udelay (10000);	/* allow flash to settle - wait 10 ms */
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
+{
+	volatile u16 *addr;
+	ulong result;
+	int cflag, iflag;
+	int state;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	addr = (volatile u16 *) dest;
+
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	state = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				state = ERR_TIMOUT;
+		}
+		if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
+			state = ERR_READY;
+
+	} while (!state);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (state == ERR_READY)
+		state = ERR_OK;
+	if ((*addr != data) && (state != ERR_TIMOUT))
+		state = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return state;
+}
+
+int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+	ulong dest;
+	u16 data;
+
+	rc = ERR_OK;
+	if (addr & 1)
+	{
+		debug ("Byte alignment not supported\n");
+		rc = ERR_ALIGN;
+	}
+	if (cnt & 1)
+	{
+		debug ("Byte transfer not supported\n");
+		rc = ERR_ALIGN;
+	}
+
+	dest = addr;
+	while ((cnt>=2) && (rc == ERR_OK))
+	{
+		data = *((volatile u16 *) src);
+		rc=amd_write_word (info,dest,data);
+		src +=2;
+		dest +=2;
+		cnt -=2;
+	}
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case (AMD_MANUFACT & FLASH_VENDMASK):
+			rc = amd_flash_write_buff(info,src,addr,cnt);
+			break;
+		case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+			rc = cfm_flash_write_buff(info,src,addr,cnt);
+			break;
+		default:
+			rc = ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	return rc;
+
+}
+int amd_flash_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+	rc= ERR_OK;
+	if (prot)
+	{
+		info->protect[sector]=1;
+	}
+	else
+	{
+		info->protect[sector]=0;
+	}
+	return rc;
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+
+int flash_real_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case (AMD_MANUFACT & FLASH_VENDMASK):
+			rc = amd_flash_protect(info,sector,prot);
+			break;
+		case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+			rc = cfm_flash_protect(info,sector,prot);
+			break;
+		default:
+			rc = ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	return rc;
+}
+
+#endif
diff --git a/u-boot/board/BuS/EB+MCF-EV123/textbase.mk b/u-boot/board/BuS/EB+MCF-EV123/textbase.mk
new file mode 100644
index 0000000..b97c034
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/textbase.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0xFFE00000
diff --git a/u-boot/board/BuS/EB+MCF-EV123/u-boot.lds b/u-boot/board/BuS/EB+MCF-EV123/u-boot.lds
new file mode 100644
index 0000000..0fa633a
--- /dev/null
+++ b/u-boot/board/BuS/EB+MCF-EV123/u-boot.lds
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/string.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o	(.text)
+    lib/zlib.o	(.text)
+
+/*    . = env_offset; */
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+    .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/BuS/eb_cpux9k2/Makefile b/u-boot/board/BuS/eb_cpux9k2/Makefile
new file mode 100644
index 0000000..f45836f
--- /dev/null
+++ b/u-boot/board/BuS/eb_cpux9k2/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cpux9k2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/BuS/eb_cpux9k2/cpux9k2.c b/u-boot/board/BuS/eb_cpux9k2/cpux9k2.c
new file mode 100644
index 0000000..fe62a0f
--- /dev/null
+++ b/u-boot/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_mc.h>
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_VIDEO
+#include <bus_vcxk.h>
+
+extern unsigned long display_width;
+extern unsigned long display_height;
+#endif
+
+#ifdef CONFIG_CMD_NAND
+void cpux9k2_nand_hw_init(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	at91_pio_t *pio	= (at91_pio_t *) AT91_PIO_BASE;
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* Correct IRDA resistor problem / Set PA23_TXD in Output */
+	writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+
+	gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_STATUS_LED
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+#ifdef CONFIG_CMD_NAND
+	cpux9k2_nand_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+
+int misc_init_r(void)
+{
+	uchar	mac[8];
+	uchar	tm;
+	uchar	midx;
+	uchar	macn6, macn7;
+
+#ifdef CONFIG_NET_MULTI
+	if (getenv("ethaddr") == NULL) {
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
+				CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				(uchar *) &mac, sizeof(mac)) != 0) {
+			puts("Error reading MAC from EEPROM\n");
+		} else {
+			tm = 0;
+			macn6 = 0;
+			macn7 = 0xFF;
+			for (midx = 0; midx < 6; midx++) {
+				if ((mac[midx] != 0) && (mac[midx] != 0xFF))
+					tm++;
+				macn6 += mac[midx];
+				macn7 ^= mac[midx];
+			}
+			if ((macn6 != mac[6]) || (macn7 != mac[7]))
+				tm = 0;
+			if (tm)
+				eth_setenv_enetaddr("ethaddr", mac);
+			 else
+				puts("Error: invalid MAC at EEPROM\n");
+		}
+	}
+#endif
+	gd->jt[XF_do_reset] = (void *) do_reset;
+
+#ifdef CONFIG_STATUS_LED
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+	udelay(10000);
+	eth_init(gd->bd);
+}
+#endif
+
+/*
+ * DRAM initialisations
+ */
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/*
+ * Ethernet initialisations
+ */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, (u32) AT91_EMAC_BASE);
+	return rc;
+}
+#endif
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if defined(CONFIG_CMD_NAND)
+
+#define	MASK_ALE	(1 << 22)	/* our ALE is AD22 */
+#define	MASK_CLE	(1 << 21)	/* our CLE is AD21 */
+
+void cpux9k2_nand_hw_init(void)
+{
+	unsigned long csr;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+
+	/* Setup Smart Media, fitst enable the address range of CS3 */
+	writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
+
+	/* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
+	csr =	AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
+		AT91_SMC_CSR_NWS(3) |
+		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
+		AT91_SMC_CSR_WSEN;
+	writel(csr, &mc->smc.csr[3]);
+
+	writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr);
+	writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE,
+		&pio->pioc.pdr);
+
+	/* Configure PC2 as input (signal Nand READY ) */
+	writel(AT91_PMX_CA_BFAVD, &pio->pioc.per);
+	writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
+	writel(AT91_PMX_CA_BFCK, &pio->pioc.codr);
+
+	/* PIOC clock enabling */
+	writel(1 << AT91_ID_PIOC, &pmc->pcer);
+}
+
+static void board_nand_hwcontrol(struct mtd_info *mtd,
+	int cmd, unsigned int ctrl)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		if ((ctrl & NAND_NCE))
+			writel(1, &pio->pioc.codr);
+		else
+			writel(1, &pio->pioc.sodr);
+
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int board_nand_dev_ready(struct mtd_info *mtd)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	cpux9k2_nand_hw_init();
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = board_nand_hwcontrol;
+	nand->dev_ready = board_nand_dev_ready;
+	nand->chip_delay = 20;
+	return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * drv_video_init
+ * FUNCTION: initialize VCxK device
+ */
+
+int drv_video_init(void)
+{
+#ifdef CONFIG_SPLASH_SCREEN
+	unsigned long splash;
+#endif
+	char *s;
+	unsigned long csr;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+
+	printf("Init Video as ");
+	s = getenv("displaywidth");
+	if (s != NULL)
+		display_width = simple_strtoul(s, NULL, 10);
+	else
+		display_width = 256;
+	s = getenv("displayheight");
+	if (s != NULL)
+		display_height = simple_strtoul(s, NULL, 10);
+	else
+		display_height = 256;
+	printf("%ld x %ld pixel matrix\n", display_width, display_height);
+
+	/* RWH = 7 | RWS =7  | TDF = 15 | NWS = 0x7F */
+	csr =	AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
+		AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
+		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
+	writel(csr, &mc->smc.csr[2]);
+	writel(1 << AT91_ID_PIOB, &pmc->pcer);
+
+	vcxk_init(display_width, display_height);
+#ifdef CONFIG_SPLASH_SCREEN
+	s = getenv("splashimage");
+	if (s != NULL) {
+		splash = simple_strtoul(s, NULL, 16);
+		printf("use splashimage: %lx\n", splash);
+		video_display_bitmap(splash, 0, 0);
+	}
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+
+void i2c_init_board(void)
+{
+	u32 pin;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	writel(1 << AT91_ID_PIOA, &pmc->pcer);
+	pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+	writel(pin, &pio->pioa.idr);
+	writel(pin, &pio->pioa.pudr);
+	writel(pin, &pio->pioa.per);
+	writel(pin, &pio->pioa.oer);
+	writel(pin, &pio->pioa.sodr);
+}
+
+#endif
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_STATUS_LED
+
+void __led_toggle(led_id_t mask)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	if (readl(&pio->piod.odsr) & mask)
+		writel(mask, &pio->piod.codr);
+	else
+		writel(mask, &pio->piod.codr);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	writel(1 << AT91_ID_PIOD, &pmc->pcer);	/* Enable PIOB clock */
+	/* Disable peripherals on LEDs */
+	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
+	/* Enable pins as outputs */
+	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
+	/* Turn all LEDs OFF */
+	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
+
+	__led_set(mask, state);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	if (state == STATUS_LED_ON)
+		writel(mask, &pio->piod.codr);
+	else
+		writel(mask, &pio->piod.sodr);
+}
+
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = 0;
+	ulong side;
+	ulong bright;
+
+	switch (argc) {
+	case 3:
+		side = simple_strtoul(argv[1], NULL, 10);
+		bright = simple_strtoul(argv[2], NULL, 10);
+		if ((side >= 0) && (side <= 3) &&
+				(bright >= 0) && (bright <= 1000)) {
+			vcxk_setbrightness(side, bright);
+			rcode = 0;
+		} else {
+			printf("parameters out of range\n");
+			printf("Usage:\n%s\n", cmdtp->usage);
+			rcode = 1;
+		}
+		break;
+	default:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+	bright,	3,	0,	do_brightness,
+	"bright  - sets the display brightness\n",
+	" <side> <0..1000>\n        side: 0/3=both; 1=first; 2=second\n"
+);
+
+/* EOF cpu9k2.c */
diff --git a/u-boot/board/LEOX/elpt860/Makefile b/u-boot/board/LEOX/elpt860/Makefile
new file mode 100644
index 0000000..96727cb
--- /dev/null
+++ b/u-boot/board/LEOX/elpt860/Makefile
@@ -0,0 +1,55 @@
+
+#######################################################################
+#
+# Copyright (C) 2000, 2001, 2002, 2003
+# The LEOX team <team@leox.org>, http://www.leox.org
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# LEOX.org is about the development of free hardware and software resources
+#   for system on chip.
+#
+# Description: U-Boot port on the LEOX's ELPT860 CPU board
+# ~~~~~~~~~~~
+#
+#######################################################################
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#######################################################################
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/LEOX/elpt860/README.LEOX b/u-boot/board/LEOX/elpt860/README.LEOX
new file mode 100644
index 0000000..e8ab867
--- /dev/null
+++ b/u-boot/board/LEOX/elpt860/README.LEOX
@@ -0,0 +1,424 @@
+=============================================================================
+
+	     U-Boot port on the LEOX's ELPT860 CPU board
+	     -------------------------------------------
+
+LEOX.org is about the development of free hardware and software resources
+	 for system on chip.
+
+For more information, contact The LEOX team <team@leox.org>
+
+References:
+~~~~~~~~~~
+    1) Get the last stable release from denx.de:
+	   o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
+    2) Get the current CVS snapshot:
+	   o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
+	   o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
+
+=============================================================================
+
+The ELPT860 CPU board has the following features:
+
+Processor:	- MPC860T @ 50MHz
+		- PowerPC Core
+		- 65 MIPS
+		- Caches: D->4KB, I->4KB
+		- CPM: 4 SCCs, 2 SMCs
+		- Ethernet 10/100
+		- SPI, I2C, PCMCIA, Parallel
+
+CPU board:	- DRAM:   16 MB
+		- FLASH: 512 KB + (2 * 4 MB)
+		- NVRAM: 128 KB
+		- 1 Serial link
+		- 2 Ethernet 10 BaseT Channels
+
+On power-up the processor jumps to the address of 0x02000100
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0x02001000.  The environment space is located in NVRAM separately from
+U-Boot, at the address of 0x03000000.
+
+=============================================================================
+
+			U-Boot test results
+
+=============================================================================
+
+
+##################################################
+# Operation on the serial console (SMC1)
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: help
+askenv  - get environment variables from stdin
+base    - print or set address offset
+bdinfo  - print Board Info structure
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+cmp     - memory compare
+coninfo - print console devices and informations
+cp      - memory copy
+crc32   - checksum calculation
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+iminfo  - print header information for application image
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loop    - infinite loop on address range
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+source  - run script from memory
+tftpboot- boot image via network using TFTP protocol
+	       and env variables ipaddr and serverip
+version - print monitor version
+?       - alias for 'help'
+
+##################################################
+# Environment Variables (CONFIG_ENV_IS_IN_NVRAM)
+##############################
+
+LEOX_elpt860: printenv
+bootdelay=5
+loads_echo=1
+baudrate=9600
+stdin=serial
+stdout=serial
+stderr=serial
+ethaddr=00:03:ca:00:64:df
+ipaddr=192.168.0.30
+netmask=255.255.255.0
+serverip=192.168.0.1
+nfsserverip=192.168.0.1
+preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
+gatewayip=192.168.0.1
+ramargs=setenv bootargs root=/dev/ram rw
+rootargs=setenv rootpath /tftp/${ipaddr}
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
+addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
+ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
+nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
+bootcmd=run ramboot
+clocks_in_mhz=1
+
+Environment size: 730/16380 bytes
+
+##################################################
+# Flash Memory Information
+##############################
+
+LEOX_elpt860: flinfo
+
+Bank # 1: AMD AM29F040   (4 Mbits)
+  Size: 512 KB in 8 Sectors
+  Sector Start Addresses:
+    02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000
+    02050000      02060000      02070000
+
+##################################################
+# Board Information Structure
+##############################
+
+LEOX_elpt860: bdinfo
+memstart    = 0x00000000
+memsize     = 0x01000000
+flashstart  = 0x02000000
+flashsize   = 0x00080000
+flashoffset = 0x00030000
+sramstart   = 0x00000000
+sramsize    = 0x00000000
+immr_base   = 0xFF000000
+bootflags   = 0x00000001
+intfreq     =     50 MHz
+busfreq     =     50 MHz
+ethaddr     = 00:03:ca:00:64:df
+IP addr     = 192.168.0.30
+baudrate    =   9600 bps
+
+##################################################
+# Image Download and run over serial port
+#    hello_world (S-Record image)
+#    ===> 1) Enter "loads" command into U-Boot monitor
+#    ===> 2) From TeraTerm's bar menu, Select 'File/Send file...'
+#            Then select 'hello_world.srec' with the file browser
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: loads
+## Ready for S-Record download ...
+S804040004F3050154000501709905014C000501388D
+## First Load Addr = 0x00040000
+## Last  Load Addr = 0x0005018B
+## Total Size      = 0x0001018C = 65932 Bytes
+## Start Addr      = 0x00040004
+LEOX_elpt860: go 40004 This is a test !!!
+## Starting application at 0x00040004 ...
+Hello World
+argc = 6
+argv[0] = "40004"
+argv[1] = "This"
+argv[2] = "is"
+argv[3] = "a"
+argv[4] = "test"
+argv[5] = "!!!"
+argv[6] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+
+##################################################
+# Image download and run over ethernet interface
+#    Linux-2.4.4 (uImage) + Root filesystem mounted over NFS
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: run nfsboot
+ARP broadcast 1
+TFTP from server 192.168.0.1; our IP address is 192.168.0.30
+Filename '/home/leox/uImage'.
+Load address: 0x400000
+Loading: #################################################################
+	 #############################
+done
+Bytes transferred = 477294 (7486e hex)
+## Booting image at 00400000 ...
+   Image Name:   Linux-2.4.4
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    477230 Bytes = 466 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
+On node 0 totalpages: 4096
+zone(0): 4096 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0:
+rtsched version <20010618.1050.24>
+Decrementer Frequency: 3125000
+Warning: real time clock seems stuck!
+Calibrating delay loop... 49.76 BogoMIPS
+Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem)
+Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
+Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
+Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
+POSIX conformance testing by UNIFIX
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Starting kswapd v1.8
+CPM UART driver version 0.03
+ttyS0 on SMC1 at 0x0280, BRG1
+block: queued sectors max/low 9701kB/3233kB, 64 slots per queue
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 1024 bind 1024)
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+Looking up port of RPC 100003/2 on 192.168.0.1
+Looking up port of RPC 100005/2 on 192.168.0.1
+VFS: Mounted root (nfs filesystem).
+Freeing unused kernel memory: 44k init
+INIT: version 2.78 booting
+		Welcome to DENX Embedded Linux Environment
+		Press 'I' to enter interactive startup.
+Mounting proc filesystem:  [  OK  ]
+Configuring kernel parameters:  [  OK  ]
+Cannot access the Hardware Clock via any known method.
+Use the --debug option to see the details of our search for an access method.
+Setting clock : Wed Dec 31 19:00:11 EST 1969 [  OK  ]
+Activating swap partitions:  [  OK  ]
+Setting hostname 192.168.0.30:  [  OK  ]
+Finding module dependencies:
+[  OK  ]
+Checking filesystems
+Checking all file systems.
+[  OK  ]
+Mounting local filesystems:  [  OK  ]
+Enabling swap space:  [  OK  ]
+INIT: Entering runlevel: 3
+Entering non-interactive startup
+Starting system logger: [  OK  ]
+Starting kernel logger: [  OK  ]
+Starting xinetd: [  OK  ]
+
+192 login: root
+Last login: Wed Dec 31 19:00:41 on ttyS0
+bash-2.04#
+
+##################################################
+# Image download and run over ethernet interface
+#    Linux-2.4.4 + Root filesystem mounted from RAM (pMulti)
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: run ramboot
+ARP broadcast 1
+TFTP from server 192.168.0.1; our IP address is 192.168.0.30
+Filename '/home/leox/pMulti'.
+Load address: 0x400000
+Loading: #################################################################
+	 #################################################################
+	 #################################################################
+	 #################################################################
+	 #################################################################
+	 ########################################################
+done
+Bytes transferred = 1947816 (1db8a8 hex)
+## Booting image at 00400000 ...
+   Image Name:   linux-2.4.4-2002-03-21 Multiboot
+   Image Type:   PowerPC Linux Multi-File Image (gzip compressed)
+   Data Size:    1947752 Bytes = 1902 kB = 1 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Contents:
+   Image 0:   477230 Bytes = 466 kB = 0 MB
+   Image 1:  1470508 Bytes = 1436 kB = 1 MB
+   Verifying Checksum ... OK
+   Uncompressing Multi-File Image ... OK
+   Loading Ramdisk to 00e44000, end 00fab02c ... OK
+Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
+On node 0 totalpages: 4096
+zone(0): 4096 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/ram rw
+rtsched version <20010618.1050.24>
+Decrementer Frequency: 3125000
+Warning: real time clock seems stuck!
+Calibrating delay loop... 49.76 BogoMIPS
+Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem)
+Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
+Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
+Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
+POSIX conformance testing by UNIFIX
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Starting kswapd v1.8
+CPM UART driver version 0.03
+ttyS0 on SMC1 at 0x0280, BRG1
+block: queued sectors max/low 8741kB/2913kB, 64 slots per queue
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
+RAMDISK: Compressed image found at block 0
+Freeing initrd memory: 1436k freed
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 1024 bind 1024)
+IP-Config: Incomplete network configuration information.
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 44k iné
+init started:  BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname
+Configuring lo...
+Configuring eth0...
+Configuring Gateway...
+
+Please press Enter to activate this console.
+
+ELPT860 login: root
+Password:
+Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
+
+					      a8888b.
+					     d888888b.
+					     8P"YP"Y88
+     _      _                                8|o||o|88
+    | |    |_|                               8'    .88
+    | |     _ ____  _   _  _  _              8`._.' Y8.
+    | |    | |  _ \| | | |\ \/ /            d/      `8b.
+    | |___ | | | | | |_| |/    \          .dP   .     Y8b.
+    |_____||_|_| |_|\____|\_/\_/         d8:'   "   `::88b.
+					d8"           `Y88b
+				       :8P     '       :888
+					8a.    :      _a88P
+				      ._/"Yaa_ :    .| 88P|
+				      \    YP"      `| 8P  `.
+				      /     \._____.d|    .'
+				      `--..__)888888P`._.'
+login[21]: root login  on `ttyS0'
+
+
+
+BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash)
+Enter 'help' for a list of built-in commands.
+
+root@ELPT860:~ #
diff --git a/u-boot/board/LEOX/elpt860/elpt860.c b/u-boot/board/LEOX/elpt860/elpt860.c
new file mode 100644
index 0000000..905df92
--- /dev/null
+++ b/u-boot/board/LEOX/elpt860/elpt860.c
@@ -0,0 +1,348 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+** Note 1: In this file, you have to provide the following functions:
+** ------
+**              int             board_early_init_f(void)
+**              int             checkboard(void)
+**              phys_size_t     initdram(int board_type)
+** called from 'board_init_f()' into 'common/board.c'
+**
+**              void            reset_phy(void)
+** called from 'board_init_r()' into 'common/board.c'
+*/
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint init_sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+	0xFFFFFC04,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
+};
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xFF0FFC00,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
+	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
+	_NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
+	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
+};
+
+/* ------------------------------------------------------------------------- */
+
+#define CONFIG_SYS_PC4    0x0800
+
+#define CONFIG_SYS_DS1    CONFIG_SYS_PC4
+
+/*
+ * Very early board init code (fpga boot, etc.)
+ */
+int board_early_init_f (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/*
+	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
+	 */
+	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
+
+	return (0);		/* success */
+}
+
+/*
+ * Check Board Identity:
+ *
+ * Test ELPT860 ID string
+ *
+ * Return 1 if no second DRAM bank, otherwise returns 0
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	if (!s || strncmp (s, "ELPT860", 7))
+		printf ("### No HW ID - assuming ELPT860\n");
+
+	return (0);		/* success */
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+
+	/*
+	 * This sequence initializes SDRAM chips on ELPT860 board
+	 */
+	upmconfig (UPMA, (uint *) init_sdram_table,
+		   sizeof (init_sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = 0x0200;
+	memctl->memc_mamr = 0x18002111;
+
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
+			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
+			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns       */
+		size_b0 = size9;
+		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+	} else {		/* back to 8 columns                      */
+
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size_b0 < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	{
+		unsigned long reg;
+
+		/* adjust refresh rate depending on SDRAM type, one bank */
+		reg = memctl->memc_mptpr;
+		reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+		memctl->memc_mptpr = reg;
+	}
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int
+dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define CONFIG_SYS_PA1     0x4000
+#define CONFIG_SYS_PA2     0x2000
+
+#define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
+
+void reset_phy (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/*
+	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+	 *                                          and no AUI loopback
+	 */
+	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
+}
diff --git a/u-boot/board/LEOX/elpt860/flash.c b/u-boot/board/LEOX/elpt860/flash.c
new file mode 100644
index 0000000..9a75aad
--- /dev/null
+++ b/u-boot/board/LEOX/elpt860/flash.c
@@ -0,0 +1,615 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+** Note 1: In this file, you have to provide the following variable:
+** ------
+**              flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
+** 'flash_info_t' structure is defined into 'include/flash.h'
+** and defined as extern into 'common/cmd_flash.c'
+**
+** Note 2: In this file, you have to provide the following functions:
+** ------
+**              unsigned long   flash_init(void)
+** called from 'board_init_r()' into 'common/board.c'
+**
+**              void            flash_print_info(flash_info_t *info)
+** called from 'do_flinfo()' into 'common/cmd_flash.c'
+**
+**              int             flash_erase(flash_info_t *info,
+**                                          int           s_first,
+**                                          int           s_last)
+** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c'
+**
+**              int             write_buff (flash_info_t *info,
+**                                          uchar        *src,
+**                                          ulong         addr,
+**                                          ulong         cnt)
+** called from 'flash_write()' into 'common/cmd_flash.c'
+*/
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+#ifndef	CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Internal Functions
+ */
+static void   flash_get_offsets (ulong base, flash_info_t *info);
+static ulong  flash_get_size (volatile unsigned char *addr, flash_info_t *info);
+
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  unsigned long         size_b0;
+  int i;
+
+  /* Init: no FLASHes known */
+  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+    {
+      flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+  /* Static FLASH Bank configuration here - FIXME XXX */
+
+  size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
+			    &flash_info[0]);
+
+  if ( flash_info[0].flash_id == FLASH_UNKNOWN )
+    {
+      printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	      size_b0, size_b0<<20);
+    }
+
+  /* Remap FLASH according to real size */
+  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
+
+  /* Re-do sizing to get full correct info */
+  size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
+			    &flash_info[0]);
+
+  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+  /* monitor protection ON by default */
+  flash_protect (FLAG_PROTECT_SET,
+		 CONFIG_SYS_MONITOR_BASE,
+		 CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
+		 &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+  /* ENV protection ON by default */
+  flash_protect(FLAG_PROTECT_SET,
+		CONFIG_ENV_ADDR,
+		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1,
+		&flash_info[0]);
+#endif
+
+  flash_info[0].size = size_b0;
+
+  return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets (ulong          base,
+		   flash_info_t  *info)
+{
+  int i;
+
+#define SECTOR_64KB    0x00010000
+
+  /* set up sector start adress table */
+  for (i = 0; i < info->sector_count; i++)
+    {
+      info->start[i] = base + (i * SECTOR_64KB);
+    }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+  int i;
+
+  if ( info->flash_id == FLASH_UNKNOWN )
+    {
+      printf ("missing or unknown FLASH type\n");
+      return;
+    }
+
+  switch ( info->flash_id & FLASH_VENDMASK )
+    {
+    case FLASH_MAN_AMD:	printf ("AMD ");		break;
+    case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+    case FLASH_MAN_STM: printf ("STM (Thomson) ");      break;
+    default:		printf ("Unknown Vendor ");	break;
+    }
+
+  switch ( info->flash_id & FLASH_TYPEMASK )
+    {
+    case FLASH_AM040:   printf ("AM29F040   (4 Mbits)\n");
+      break;
+    default:	        printf ("Unknown Chip Type\n");
+      break;
+    }
+
+  printf ("  Size: %ld KB in %d Sectors\n",
+	  info->size >> 10, info->sector_count);
+
+  printf ("  Sector Start Addresses:");
+  for (i=0; i<info->sector_count; ++i)
+    {
+      if ((i % 5) == 0)
+	printf ("\n   ");
+      printf (" %08lX%s",
+	      info->start[i],
+	      info->protect[i] ? " (RO)" : "     "
+	      );
+    }
+  printf ("\n");
+
+  return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong
+flash_get_size (volatile unsigned char *addr,
+		flash_info_t           *info)
+{
+  short i;
+  uchar value;
+  ulong base = (ulong)addr;
+
+  /* Write auto select command: read Manufacturer ID */
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0x90;
+
+  value = addr[0];
+
+  switch ( value )
+    {
+      /*    case AMD_MANUFACT: */
+    case 0x01:
+      info->flash_id = FLASH_MAN_AMD;
+      break;
+      /*    case FUJ_MANUFACT: */
+    case 0x04:
+      info->flash_id = FLASH_MAN_FUJ;
+      break;
+      /*    case STM_MANUFACT: */
+    case 0x20:
+      info->flash_id = FLASH_MAN_STM;
+      break;
+
+    default:
+      info->flash_id = FLASH_UNKNOWN;
+      info->sector_count = 0;
+      info->size = 0;
+      return (0);			/* no or unknown flash	*/
+    }
+
+  value = addr[1];			/* device ID		*/
+
+  switch ( value )
+    {
+    case STM_ID_F040B:
+    case AMD_ID_F040B:
+      info->flash_id += FLASH_AM040;    /* 4 Mbits = 512k * 8  */
+      info->sector_count = 8;
+      info->size = 0x00080000;
+      break;
+
+    default:
+      info->flash_id = FLASH_UNKNOWN;
+      return (0);			/* => no or unknown flash */
+    }
+
+  /* set up sector start adress table */
+  for (i = 0; i < info->sector_count; i++)
+    {
+      info->start[i] = base + (i * 0x00010000);
+    }
+
+  /* check for protected sectors */
+  for (i = 0; i < info->sector_count; i++)
+    {
+      /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+      /* D0 = 1 if protected */
+      addr = (volatile unsigned char *)(info->start[i]);
+      info->protect[i] = addr[2] & 1;
+    }
+
+  /*
+   * Prevent writes to uninitialized FLASH.
+   */
+  if ( info->flash_id != FLASH_UNKNOWN )
+    {
+      addr = (volatile unsigned char *)info->start[0];
+
+      *addr = 0xF0;	/* reset bank */
+    }
+
+  return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase (flash_info_t  *info,
+	     int            s_first,
+	     int            s_last)
+{
+  volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+  int flag, prot, sect, l_sect;
+  ulong start, now, last;
+
+  if ( (s_first < 0) || (s_first > s_last) )
+    {
+      if ( info->flash_id == FLASH_UNKNOWN )
+	{
+	  printf ("- missing\n");
+	}
+      else
+	{
+	  printf ("- no sectors to erase\n");
+	}
+      return ( 1 );
+    }
+
+  if ( (info->flash_id == FLASH_UNKNOWN) ||
+       (info->flash_id > FLASH_AMD_COMP) )
+    {
+      printf ("Can't erase unknown flash type %08lx - aborted\n",
+	      info->flash_id);
+      return ( 1 );
+    }
+
+  prot = 0;
+  for (sect=s_first; sect<=s_last; ++sect)
+    {
+      if ( info->protect[sect] )
+	{
+	  prot++;
+	}
+    }
+
+  if ( prot )
+    {
+      printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    }
+  else
+    {
+      printf ("\n");
+    }
+
+  l_sect = -1;
+
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0x80;
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+
+  /* Start erase on unprotected sectors */
+  for (sect = s_first; sect<=s_last; sect++)
+    {
+      if (info->protect[sect] == 0)    /* not protected */
+	{
+	  addr = (volatile unsigned char *)(info->start[sect]);
+	  addr[0] = 0x30;
+	  l_sect = sect;
+	}
+    }
+
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* wait at least 80us - let's wait 1 ms */
+  udelay (1000);
+
+  /*
+   * We wait for the last triggered sector
+   */
+  if ( l_sect < 0 )
+    goto DONE;
+
+  start = get_timer (0);
+  last  = start;
+  addr = (volatile unsigned char *)(info->start[l_sect]);
+  while ( (addr[0] & 0x80) != 0x80 )
+    {
+      if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
+	{
+	  printf ("Timeout\n");
+	  return ( 1 );
+	}
+      /* show that we're waiting */
+      if ( (now - last) > 1000 )     /* every second */
+	{
+	  putc ('.');
+	  last = now;
+	}
+    }
+
+DONE:
+  /* reset to read mode */
+  addr = (volatile unsigned char *)info->start[0];
+  addr[0] = 0xF0;	/* reset bank */
+
+  printf (" done\n");
+
+  return ( 0 );
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int
+write_buff (flash_info_t  *info,
+	    uchar         *src,
+	    ulong          addr,
+	    ulong          cnt)
+{
+  ulong cp, wp, data;
+  uchar bdata;
+  int i, l, rc;
+
+  if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 )
+    {
+      /* Width of the data bus: 8 bits */
+
+      wp = addr;
+
+      while ( cnt )
+	{
+	  bdata = *src++;
+
+	  if ( (rc = write_byte(info, wp, bdata)) != 0 )
+	    {
+	      return (rc);
+	    }
+
+	  ++wp;
+	  --cnt;
+	}
+
+      return ( 0 );
+    }
+  else
+    {
+      /* Width of the data bus: 32 bits */
+
+      wp = (addr & ~3);	/* get lower word aligned address */
+
+      /*
+       * handle unaligned start bytes
+       */
+      if ( (l = addr - wp) != 0 )
+	{
+	  data = 0;
+	  for (i=0, cp=wp; i<l; ++i, ++cp)
+	    {
+	      data = (data << 8) | (*(uchar *)cp);
+	    }
+	  for (; i<4 && cnt>0; ++i)
+	    {
+	      data = (data << 8) | *src++;
+	      --cnt;
+	      ++cp;
+	    }
+	  for (; cnt==0 && i<4; ++i, ++cp)
+	    {
+	      data = (data << 8) | (*(uchar *)cp);
+	    }
+
+	  if ( (rc = write_word(info, wp, data)) != 0 )
+	    {
+	      return (rc);
+	    }
+	  wp += 4;
+	}
+
+      /*
+       * handle word aligned part
+       */
+      while ( cnt >= 4 )
+	{
+	  data = 0;
+	  for (i=0; i<4; ++i)
+	    {
+	      data = (data << 8) | *src++;
+	    }
+	  if ( (rc = write_word(info, wp, data)) != 0 )
+	    {
+	      return (rc);
+	    }
+	  wp  += 4;
+	  cnt -= 4;
+	}
+
+      if ( cnt == 0 )
+	{
+	  return (0);
+	}
+
+      /*
+       * handle unaligned tail bytes
+       */
+      data = 0;
+      for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
+	{
+	  data = (data << 8) | *src++;
+	  --cnt;
+	}
+      for (; i<4; ++i, ++cp)
+	{
+	  data = (data << 8) | (*(uchar *)cp);
+	}
+
+      return (write_word(info, wp, data));
+    }
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word (flash_info_t  *info,
+	    ulong          dest,
+	    ulong          data)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  ulong start;
+  int flag;
+
+  /* Check if Flash is (sufficiently) erased */
+  if ( (*((vu_long *)dest) & data) != data )
+    {
+      return (2);
+    }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00A000A0;
+
+  *((vu_long *)dest) = data;
+
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
+    {
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
+	{
+	  return (1);
+	}
+    }
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_byte (flash_info_t  *info,
+	    ulong          dest,
+	    uchar          data)
+{
+  volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+  ulong  start;
+  int    flag;
+
+  /* Check if Flash is (sufficiently) erased */
+  if ( (*((volatile unsigned char *)dest) & data) != data )
+    {
+      return (2);
+    }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0xA0;
+
+  *((volatile unsigned char *)dest) = data;
+
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
+    {
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
+	{
+	  return (1);
+	}
+    }
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/LEOX/elpt860/u-boot.lds b/u-boot/board/LEOX/elpt860/u-boot.lds
new file mode 100644
index 0000000..9077e69
--- /dev/null
+++ b/u-boot/board/LEOX/elpt860/u-boot.lds
@@ -0,0 +1,114 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    common/libcommon.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    board/LEOX/elpt860/libelpt860.o	(.text*)
+    arch/powerpc/lib/libpowerpc.o	(.text*)
+/*    drivers/rtc/librtc.o		(.text*)	*/
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/LEOX/elpt860/u-boot.lds.debug b/u-boot/board/LEOX/elpt860/u-boot.lds.debug
new file mode 100644
index 0000000..287fc20
--- /dev/null
+++ b/u-boot/board/LEOX/elpt860/u-boot.lds.debug
@@ -0,0 +1,139 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/LaCie/edminiv2/Makefile b/u-boot/board/LaCie/edminiv2/Makefile
new file mode 100644
index 0000000..f733389
--- /dev/null
+++ b/u-boot/board/LaCie/edminiv2/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= edminiv2.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/LaCie/edminiv2/config.mk b/u-boot/board/LaCie/edminiv2/config.mk
new file mode 100644
index 0000000..2ffd125
--- /dev/null
+++ b/u-boot/board/LaCie/edminiv2/config.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# TEXT_BASE must equal the intended FLASH location of u-boot.
+CONFIG_SYS_TEXT_BASE = 0xfff90000
diff --git a/u-boot/board/LaCie/edminiv2/edminiv2.c b/u-boot/board/LaCie/edminiv2/edminiv2.c
new file mode 100644
index 0000000..bb388ed
--- /dev/null
+++ b/u-boot/board/LaCie/edminiv2/edminiv2.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+	int sect;
+
+	if (base != CONFIG_SYS_FLASH_BASE)
+		return 0;
+
+	info->size = 0;
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	/* set each sector's start address and size based */
+	for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+		info->start[sect] = base+info->size;
+		info->size += sectsz[sect];
+	}
+	/* This flash must be accessed in 8-bits mode, no buffer. */
+	info->flash_id = 0x01000000;
+	info->portwidth = FLASH_CFI_8BIT;
+	info->chipwidth = FLASH_CFI_BY8;
+	info->buffer_size = 0;
+	/* timings are derived from the Macronix datasheet. */
+	info->erase_blk_tout = 1000;
+	info->write_tout = 10;
+	info->buffer_write_tout = 300;
+	/* Commands and addresses are for AMD mode 8-bit access. */
+	info->vendor = CFI_CMDSET_AMD_LEGACY;
+	info->cmd_reset = 0xF0;
+	info->interface = FLASH_CFI_X8;
+	info->legacy_unlock = 0;
+	info->ext_addr = 0;
+	info->addr_unlock1 = 0x00000aaa;
+	info->addr_unlock2 = 0x00000555;
+	/* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
+	info->manufacturer_id = 0x22;
+	info->device_id = 0xBA;
+	info->device_id2 = 0;
+	info->cfi_version = 0x3133;
+	info->cfi_offset = 0x0000;
+	info->name = "MX29LV400CB";
+
+	return 1;
+}
+#endif				/* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+	/* arch number of board */
+	gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+	/* boot parameter start at 256th byte of RAM base */
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/u-boot/board/LaCie/edminiv2/edminiv2.h b/u-boot/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..88e62b2
--- /dev/null
+++ b/u-boot/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_BASE_H
+#define __EDMINIV2_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __EDMINIV2_BASE_H */
diff --git a/u-boot/board/Marvell/aspenite/Makefile b/u-boot/board/Marvell/aspenite/Makefile
new file mode 100644
index 0000000..cb1b65f
--- /dev/null
+++ b/u-boot/board/Marvell/aspenite/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)lib$(BOARD).o
+
+COBJS	:= aspenite.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/aspenite/aspenite.c b/u-boot/board/Marvell/aspenite/aspenite.c
new file mode 100644
index 0000000..046ffd6
--- /dev/null
+++ b/u-boot/board/Marvell/aspenite/aspenite.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART1 */
+		MFP107_UART1_RXD,
+		MFP108_UART1_TXD,
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	return 0;
+}
diff --git a/u-boot/board/Marvell/common/bootseq.txt b/u-boot/board/Marvell/common/bootseq.txt
new file mode 100644
index 0000000..e4fefb3
--- /dev/null
+++ b/u-boot/board/Marvell/common/bootseq.txt
@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+    b boot_cold
+
+start_warm:
+    b boot_warm
+
+
+boot_cold:
+boot_warm:
+    clear bats
+    init l2 (if enabled)
+    init altivec (if enabled)
+    invalidate l2 (if enabled)
+    setup bats (from defines in config_EVB)
+    enable_addr_trans: (if MMU enabled)
+	enable MSR_IR and MSR_DR
+    jump to in_flash
+
+in_flash:
+    enable l1 dcache
+    gal_low_init: (board/evb64260/sdram_init.S)
+	config SDRAM (CFG, TIMING, DECODE)
+	init scratch regs (810 + 814)
+
+	detect DIMM0 (bank 0 only)
+	config SDRAM_PARA0 to 256/512Mbit
+	bl sdram_op_mode
+	detect bank0 width
+	    write scratch reg 810
+	config SDRAM_PARA0 with results
+	config SDRAM_PARA1 with results
+
+	detect DIMM1 (bank 2 only)
+	config SDRAM_PARA2 to 256/512Mbit
+	detect bank2 width
+	    write scratch reg 814
+	config SDRAM_PARA2 with results
+	config SDRAM_PARA3 with results
+
+	setup device bus timings/width
+	setup boot device timings/width
+
+	setup CPU_CONF (0x0)
+	setup cpu master control register 0x160
+	setup PCI0 TIMEOUT
+	setup PCI1 TIMEOUT
+	setup PCI0 BAR
+	setup PCI1 BAR
+
+	setup MPP control 0-3
+	setup GPP level control
+	setup Serial ports multiplex
+
+    setup stack pointer (r1)
+    setup GOT
+    call cpu_init_f
+	debug leds
+    board_init_f: (common/board.c)
+	board_early_init_f:
+	    remap gt regs?
+	    map PCI mem/io
+	    map device space
+	    clear out interupts
+	init_timebase
+	env_init
+	serial_init
+	console_init_f
+	display_options
+	initdram: (board/evb64260/evb64260.c)
+	    detect memory
+	    for each bank:
+		dram_size()
+		setup PCI slave memory mappings
+		setup SCS
+	setup monitor
+	alloc board info struct
+	init bd struct
+	relocate_code: (cpu/mpc7xxx/start.S)
+	    copy,got,clearbss
+	    board_init_r(bd, dest_addr) (common/board.c)
+		setup bd function pointers
+		trap_init
+		flash_init: (board/evb64260/flash.c)
+		setup bd flash info
+		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+		    nothing
+		mem_malloc_init
+		malloc_bin_reloc
+		spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
+		env_relocated
+		misc_init_r(bd): (board/evb64260/evb64260.c)
+		    mpsc_init2
diff --git a/u-boot/board/Marvell/common/ecctest.c b/u-boot/board/Marvell/common/ecctest.c
new file mode 100644
index 0000000..e22b113
--- /dev/null
+++ b/u-boot/board/Marvell/common/ecctest.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef ECC_TEST
+static inline void ecc_off (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
+}
+
+static inline void ecc_on (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
+}
+
+static int putshex (const char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
+	}
+	return 0;
+}
+
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/Marvell/common/flash.c b/u-boot/board/Marvell/common/flash.c
new file mode 100644
index 0000000..21eae0e
--- /dev/null
+++ b/u-boot/board/Marvell/common/flash.c
@@ -0,0 +1,1072 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * flash.c - flash support for the 512k, 8bit boot flash
+	and the 8MB 32bit extra flash on the DB64360
+ *           most of this file was based on the existing U-Boot
+ *           flash drivers.
+ *
+ * written or collected and sometimes rewritten by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/memory.h"
+#include "intel_flash.h"
+
+#define FLASH_ROM       0xFFFD	/* unknown flash type                   */
+#define FLASH_RAM       0xFFFE	/* unknown flash type                   */
+#define FLASH_MAN_UNKNOWN 0xFFFF0000
+
+/* #define DEBUG */
+
+/* Intel flash commands */
+int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
+int write_word_intel (bank_addr_t addr, bank_word_t value);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (int portwidth, vu_long * addr,
+			     flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long size_b0 = 0, size_b1 = 0;
+	unsigned long base, flash_size;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* the boot flash */
+	base = CONFIG_SYS_FLASH_BASE;
+	size_b0 =
+		flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
+				&flash_info[0]);
+
+	printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
+	}
+
+	base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
+/*	base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		unsigned long size =
+			flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
+					(vu_long *) base, &flash_info[i]);
+
+		printf ("[%ldMB@%lx] ", size >> 20, base);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			if (i == 1) {
+				printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20);
+			}
+			break;
+		}
+		size_b1 += size;
+		base += size;
+	}
+
+	flash_size = size_b0 + size_b1;
+	return flash_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	int sector_size;
+
+	if (!info->sector_count)
+		return;
+
+	/* set up sector start address table */
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+	case FLASH_28F128J3A:
+	case FLASH_28F640J3A:
+	case FLASH_RAM:
+		/* this chip has uniformly spaced sectors */
+		sector_size = info->size / info->sector_count;
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sector_size);
+		break;
+	default:
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type    */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		} else {
+			/* set sector offsets for top boot block type               */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A (64 Mbit)\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A (128 Mbit)\n");
+		break;
+	case FLASH_ROM:
+		printf ("ROM\n");
+		break;
+	case FLASH_RAM:
+		printf ("RAM\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if ((info->size >> 20) > 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+	} else {
+		printf ("  Size: %ld kB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static inline void flash_cmd (int width, volatile unsigned char *addr,
+			      int offset, unsigned char cmd)
+{
+	/* supports 1x8, 1x16, and 2x16 */
+	/* 2x8 and 4x8 are not supported */
+	if (width == 4) {
+		/* assuming chips are in 16 bit mode */
+		/* 2x16 */
+		unsigned long cmd32 = (cmd << 16) | cmd;
+
+		*(volatile unsigned long *) (addr + offset * 2) = cmd32;
+	} else {
+		/* 1x16 or 1x8 */
+		*(volatile unsigned char *) (addr + offset) = cmd;
+	}
+}
+
+static ulong
+flash_get_size (int portwidth, vu_long * addr, flash_info_t * info)
+{
+	short i;
+	volatile unsigned char *caddr = (unsigned char *) addr;
+	volatile unsigned short *saddr = (unsigned short *) addr;
+	volatile unsigned long *laddr = (unsigned long *) addr;
+	char old[2], save;
+	ulong id = 0, manu = 0, base = (ulong) addr;
+
+#ifdef DEBUG
+	printf ("%s: enter\n", __FUNCTION__);
+#endif
+	info->portwidth = portwidth;
+
+	save = *caddr;
+
+	flash_cmd (portwidth, caddr, 0, 0xf0);
+	flash_cmd (portwidth, caddr, 0, 0xf0);
+
+	udelay (10);
+
+	old[0] = caddr[0];
+	old[1] = caddr[1];
+
+
+	if (old[0] != 0xf0) {
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		udelay (10);
+
+		if (*caddr == 0xf0) {
+			/* this area is ROM */
+			*caddr = save;
+			info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+			info->sector_count = 8;
+			info->size = 0x80000;
+			flash_get_offsets (base, info);
+			return info->size;
+		}
+	} else {
+		*caddr = 0;
+
+		udelay (10);
+
+		if (*caddr == 0) {
+			/* this area is RAM */
+			*caddr = save;
+			info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
+			info->sector_count = 8;
+			info->size = 0x80000;
+			flash_get_offsets (base, info);
+			return info->size;
+		}
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		udelay (10);
+	}
+
+	/* Write auto select command: read Manufacturer ID */
+	flash_cmd (portwidth, caddr, 0x555, 0xAA);
+	flash_cmd (portwidth, caddr, 0x2AA, 0x55);
+	flash_cmd (portwidth, caddr, 0x555, 0x90);
+
+	udelay (10);
+
+	if ((caddr[0] == old[0]) && (caddr[1] == old[1])) {
+
+		/* this area is ROM */
+		info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		flash_get_offsets (base, info);
+		return info->size;
+#ifdef DEBUG
+	} else {
+		printf ("%px%d: %02x:%02x -> %02x:%02x\n",
+			caddr, portwidth, old[0], old[1], caddr[0], caddr[1]);
+#endif
+	}
+
+	switch (portwidth) {
+	case 1:
+		manu = caddr[0];
+		manu |= manu << 16;
+		id = caddr[1];
+		break;
+	case 2:
+		manu = saddr[0];
+		manu |= manu << 16;
+		id = saddr[1];
+		id |= id << 16;
+		break;
+	case 4:
+		manu = laddr[0];
+		id = laddr[1];
+		break;
+	}
+
+#ifdef DEBUG
+	flash_cmd (portwidth, caddr, 0, 0xf0);
+
+	printf ("\n%08lx:%08lx:%08lx\n", base, manu, id);
+	printf ("%08lx %08lx %08lx %08lx\n",
+		laddr[0], laddr[1], laddr[2], laddr[3]);
+#endif
+
+	switch (manu) {
+	case STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (id) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		info->chipwidth = 1;
+		break;		/* => 1 MB      */
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		info->chipwidth = 1;
+		break;		/* => 1 MB      */
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		info->chipwidth = 1;
+		break;		/* => 2 MB      */
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		info->chipwidth = 1;
+		break;		/* => 2 MB      */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		info->chipwidth = 1;
+		break;		/* => 4 MB      */
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		info->chipwidth = 1;
+		break;		/* => 4 MB      */
+#if 0				/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB      */
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB      */
+#endif
+	case AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		info->chipwidth = 1;
+		break;		/* => 512 kB    */
+
+	case INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 128 * 1024 * 64;	/* 128kbytes x 64 blocks */
+		info->chipwidth = 2;
+		if (portwidth == 4)
+			info->size *= 2;	/* 2x16 */
+		break;
+
+	case INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 128 * 1024 * 128;	/* 128kbytes x 128 blocks */
+		info->chipwidth = 2;
+		if (portwidth == 4)
+			info->size *= 2;	/* 2x16 */
+		break;
+
+	default:
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		printf ("Unknown id %lx:[%lx]\n", manu, id);
+		info->flash_id = FLASH_UNKNOWN;
+		info->chipwidth = 1;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets (base, info);
+
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0)=0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *) (info->start[i]);
+		saddr = (volatile unsigned short *) (info->start[i]);
+		laddr = (volatile unsigned long *) (info->start[i]);
+		if (portwidth == 1)
+			info->protect[i] = caddr[2] & 1;
+		else if (portwidth == 2)
+			info->protect[i] = saddr[2] & 1;
+		else
+			info->protect[i] = laddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (volatile unsigned char *) info->start[0];
+
+		flash_cmd (portwidth, caddr, 0, 0xF0);	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (uchar *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+/* modified to support 2x16 Intel flash */
+/* Note that the code will not exit on a flash erasure error or timeout */
+/* but will print and error message and continue processing sectors */
+/* until they are all erased. */
+/* 10-16-2002 P. Marchese */
+	ulong mask;
+	int timeout;
+
+	if (info->portwidth == 4)
+/*		{
+		printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
+		return 1;
+		}*/
+	{
+		/* make sure it's Intel flash */
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+			/* yup! it's an Intel flash */
+			/* is it 16-bits wide? */
+			if (info->chipwidth == 2) {
+				/* yup! it's 16-bits wide */
+				/* are there any sectors to process? */
+				if ((s_first < 0) || (s_first > s_last)) {
+					printf ("Error:  There are no sectors to erase\n");
+					printf ("Either sector %d is less than zero\n", s_first);
+					printf ("or sector %d is greater than sector %d\n", s_first, s_last);
+					return 1;
+				}
+				/* check for protected sectors */
+				prot = 0;
+				for (sect = s_first; sect <= s_last; ++sect)
+					if (info->protect[sect])
+						prot++;
+				/* if variable "prot" is nonzero, there are protected sectors */
+				if (prot)
+					printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+				/* reset the flash */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* Disable interrupts which might cause a timeout here */
+				flag = disable_interrupts ();
+				/* Clear the status register */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_CLR_STAT);
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* Start erase on unprotected sectors */
+				for (sect = s_first; sect <= s_last; sect++) {
+					/* is the sector unprotected? */
+					if (info->protect[sect] == 0) {	/* not protected */
+						/* issue the single block erase command, 0x20 */
+						flash_cmd (info->portwidth,
+							   (volatile unsigned
+							    char *) info->
+							   start[sect], 0,
+							   CHIP_CMD_ERASE1);
+						/* issue the erase confirm command, 0xD0 */
+						flash_cmd (info->portwidth,
+							   (volatile unsigned
+							    char *) info->
+							   start[sect], 0,
+							   CHIP_CMD_ERASE2);
+						l_sect = sect;
+						/* re-enable interrupts if necessary */
+						if (flag)
+							enable_interrupts ();
+						/* poll for erasure completion */
+						/* put flash into read status mode by writing 0x70 to it */
+						flash_cmd (info->portwidth,
+							   addr, 0,
+							   CHIP_CMD_RD_STAT);
+						/* setup the status register mask */
+						mask = CHIP_STAT_RDY |
+							(CHIP_STAT_RDY << 16);
+						/* init. the timeout counter */
+						start = get_timer (0);
+						/* keep looping while the flash is not ready */
+						/* exit the loop by timing out or the flash */
+						/* becomes ready again */
+						timeout = 0;
+						while ((*
+							(volatile unsigned
+							 long *) info->
+							start[sect] & mask) !=
+						       mask) {
+							/* has the timeout limit been reached? */
+							if (get_timer (start)
+							    >
+							    CONFIG_SYS_FLASH_ERASE_TOUT)
+							{
+								/* timeout limit reached */
+								printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
+								printf ("Continuing with next sector\n");
+								timeout = 1;
+								goto timed_out_error;
+							}
+							/* put flash into read status mode by writing 0x70 to it */
+							flash_cmd (info->
+								   portwidth,
+								   addr, 0,
+								   CHIP_CMD_RD_STAT);
+						}
+						/* did we timeout? */
+					      timed_out_error:if (timeout == 0)
+						{
+							/* didn't timeout, so check the status register */
+							/* create the status mask to check for errors */
+							mask = CHIP_STAT_ECLBS;
+							mask = mask | (mask <<
+								       16);
+							/* put flash into read status mode by writing 0x70 to it */
+							flash_cmd (info->
+								   portwidth,
+								   addr, 0,
+								   CHIP_CMD_RD_STAT);
+							/* are there any errors? */
+							if ((*
+							     (volatile
+							      unsigned long *)
+							     info->
+							     start[sect] &
+							     mask) != 0) {
+								/* We got an erasure error */
+								printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]);
+								printf ("Continuing with next sector\n");
+								/* reset the flash */
+								flash_cmd
+									(info->
+									 portwidth,
+									 addr,
+									 0,
+									 CHIP_CMD_RST);
+							}
+						}
+						/* erasure completed without errors */
+						/* reset the flash */
+						flash_cmd (info->portwidth,
+							   addr, 0,
+							   CHIP_CMD_RST);
+					}	/* end if not protected */
+				}	/* end for loop */
+				printf ("Flash erasure done\n");
+				return 0;
+			} else {
+				/* The Intel flash is not 16-bit wide */
+				/* print and error message and return */
+				/* NOTE: you can add routines here to handle other size flash */
+				printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
+				printf ("The erasure code only handles Intel 16-bit wide flash memory\n");
+				return 1;
+			}
+		} else {
+			/* Not Intel flash so return an error as a write timeout */
+			/* NOTE: if it's another type flash, stick its routine here */
+			printf ("Error: The flash device is not Intel type\n");
+			printf ("The erasure code only supports Intel flash in a 32-bit port width\n");
+			return 1;
+		}
+	}
+
+	/* end 32-bit wide flash code */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
+		return 1;	/* Rom can not be erased */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {	/* RAM just copy 0s to RAM */
+		for (sect = s_first; sect <= s_last; sect++) {
+			int sector_size = info->size / info->sector_count;
+
+			addr = (uchar *) (info->start[sect]);
+			memset ((void *) addr, 0, sector_size);
+		}
+		return 0;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {	/* Intel works spezial */
+		return flash_erase_intel (info,
+					  (unsigned short) s_first,
+					  (unsigned short) s_last);
+	}
+#if 0
+	if ((info->flash_id == FLASH_UNKNOWN) ||	/* Flash is unknown to PPCBoot */
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+#endif
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	flash_cmd (info->portwidth, addr, 0x555, 0xAA);	/* start erase routine */
+	flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
+	flash_cmd (info->portwidth, addr, 0x555, 0x80);
+	flash_cmd (info->portwidth, addr, 0x555, 0xAA);
+	flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (uchar *) (info->start[sect]);
+			flash_cmd (info->portwidth, addr, 0, 0x30);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (volatile unsigned char *) (info->start[l_sect]);
+	/* broken for 2x16: TODO */
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *) info->start[0];
+	flash_cmd (info->portwidth, addr, 0, 0xf0);
+	flash_cmd (info->portwidth, addr, 0, 0xf0);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+/* broken for 2x16: TODO */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+/* Commented out since the below code should work for 32-bit(2x 16 flash) */
+/* 10-16-2002 P. Marchese */
+/*	if(info->portwidth==4) return 1; */
+/*	if(info->portwidth==4) {
+		printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
+		return 1;
+		}*/
+
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
+		return 0;
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+		memcpy ((void *) addr, src, cnt);
+		return 0;
+	}
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+/* broken for 2x16: TODO */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (uchar *) (info->start[0]);
+	ulong start;
+	int flag, i;
+	ulong mask;
+
+/* modified so that it handles 32-bit(2x16 Intel flash programming */
+/* 10-16-2002 P. Marchese */
+
+	if (info->portwidth == 4)
+/*		{
+		printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
+		return 1;
+		}*/
+	{
+		/* make sure it's Intel flash */
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+			/* yup! it's an Intel flash */
+			/* is it 16-bits wide? */
+			if (info->chipwidth == 2) {
+				/* yup! it's 16-bits wide */
+				/* so we know how to program it */
+				/* reset the flash */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* Disable interrupts which might cause a timeout here */
+				flag = disable_interrupts ();
+				/* Clear the status register */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_CLR_STAT);
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* 1st cycle of word/byte program */
+				/* write 0x40 to the location to program */
+				flash_cmd (info->portwidth, (uchar *) dest, 0,
+					   CHIP_CMD_PROG);
+				/* 2nd cycle of word/byte program */
+				/* write the data to the destination address */
+				*(ulong *) dest = data;
+				/* re-enable interrupts if necessary */
+				if (flag)
+					enable_interrupts ();
+				/* setup the status register mask */
+				mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16);
+				/* put flash into read status mode by writing 0x70 to it */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RD_STAT);
+				/* init. the timeout counter */
+				start = get_timer (0);
+				/* keep looping while the flash is not ready */
+				/* exit the loop by timing out or the flash */
+				/* becomes ready again */
+/* 11-13-2002 Paul Marchese */
+/* modified while loop conditional statement */
+/* because we were always timing out.  */
+/* there is a type mismatch, "addr[0]" */
+/* returns a byte but "mask" is a 32-bit value */
+				while ((*(volatile unsigned long *) info->
+					start[0] & mask) != mask)
+/* original code */
+/* while (addr[0] & mask) != mask) */
+				{
+					/* has the timeout limit been reached? */
+					if (get_timer (start) >
+					    CONFIG_SYS_FLASH_WRITE_TOUT) {
+						/* timeout limit reached */
+						printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
+						/* reset the flash */
+						flash_cmd (info->portwidth,
+							   addr, 0,
+							   CHIP_CMD_RST);
+						return (1);
+					}
+					/* put flash into read status mode by writing 0x70 to it */
+					flash_cmd (info->portwidth, addr, 0,
+						   CHIP_CMD_RD_STAT);
+				}
+				/* flash is ready, so check the status */
+				/* create the status mask to check for errors */
+				mask = CHIP_STAT_DPS | CHIP_STAT_VPPS |
+					CHIP_STAT_PSLBS;
+				mask = mask | (mask << 16);
+				/* put flash into read status mode by writing 0x70 to it */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RD_STAT);
+				/* are there any errors? */
+				if ((addr[0] & mask) != 0) {
+					/* We got a one of the following errors: */
+					/* Voltage range, Device protect, or programming */
+					/* return the error as a device timeout */
+					/* put flash into read status mode by writing 0x70 to it */
+					flash_cmd (info->portwidth, addr, 0,
+						   CHIP_CMD_RD_STAT);
+					printf ("Flash programming error at address 0x%08lx\n", dest);
+					printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]);
+					/* reset the flash */
+					flash_cmd (info->portwidth, addr, 0,
+						   CHIP_CMD_RST);
+					return 1;
+				}
+				/* write completed without errors */
+				/* reset the flash */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				return 0;
+			} else {
+				/* it's not 16-bits wide, so return an error as a write timeout */
+				/* NOTE: you can add routines here to handle other size flash */
+				printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
+				printf ("The write code only handles Intel 16-bit wide flash memory\n");
+				return 1;
+			}
+		} else {
+			/* not Intel flash so return an error as a write timeout */
+			/* NOTE: if it's another type flash, stick its routine here */
+			printf ("Error: The flash device is not Intel type\n");
+			printf ("The code only supports Intel flash in a 32-bit port width\n");
+			return 1;
+		}
+	}
+
+	/* end of 32-bit flash code */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
+		return 1;
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+		*(unsigned long *) dest = data;
+		return 0;
+	}
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		unsigned short low = data & 0xffff;
+		unsigned short hi = (data >> 16) & 0xffff;
+		int ret = write_word_intel ((bank_addr_t) dest, hi);
+
+		if (!ret)
+			ret = write_word_intel ((bank_addr_t) (dest + 2),
+						low);
+
+		return ret;
+	}
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	addr[0x555] = 0xAA;
+	addr[0x2AA] = 0x55;
+	addr[0x555] = 0x20;
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *) &data;
+
+		addr[0] = 0xA0;
+		*(((char *) dest) + i) = data_ch[i];
+		udelay (10);	/* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	addr[0] = 0x90;
+	addr[0] = 0x00;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/Marvell/common/i2c.c b/u-boot/board/Marvell/common/i2c.c
new file mode 100644
index 0000000..8d87b2d
--- /dev/null
+++ b/u-boot/board/Marvell/common/i2c.c
@@ -0,0 +1,537 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include <i2c.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/core.h"
+
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+#undef	DEBUG_I2C
+/*#define DEBUG_I2C*/
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CONFIG_SYS_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	GT_REG_READ (I2C_CONTROL, &control);
+}
+
+static uchar i2c_start (void)
+{				/* DB64360 checked -> ok */
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+/* gtI2cGenerateStartBit() */
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+
+	count = 0;
+	while ((status & 0xff) != 0x08) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+
+	udelay (I2C_DELAY);
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY * 5);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	while ((status & 0xff) != 0x58) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* 11-14-2002 Paul Marchese */
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* 11-14-2002 Paul Marchese */
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
+	/* set the interrupt bit in the control register */
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+int
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	/* set the i2c frequency again */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* 11-14-2002 Paul Marchese */
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+}
+
+/* 11-14-2002 Paul Marchese */
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+int
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* 11-14-2002 Paul Marchese */
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
diff --git a/u-boot/board/Marvell/common/i2c.h b/u-boot/board/Marvell/common/i2c.h
new file mode 100644
index 0000000..b669ff0
--- /dev/null
+++ b/u-boot/board/Marvell/common/i2c.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/u-boot/board/Marvell/common/intel_flash.c b/u-boot/board/Marvell/common/intel_flash.c
new file mode 100644
index 0000000..42b3ee1
--- /dev/null
+++ b/u-boot/board/Marvell/common/intel_flash.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/memory.h"
+#include "intel_flash.h"
+
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+static void bank_reset (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, eaddrw;
+
+	addrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf ("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long) addrw);
+#endif
+		*addrw = BANK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void bank_erase_init (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
+	printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
+	printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
+	printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
+	printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
+	printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
+	printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
+#endif
+
+	saddrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
+
+#ifdef FLASH_DEBUG
+	printf ("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long) saddrw, (unsigned long) eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf ("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long) addrw);
+#endif
+		*addrw = BANK_CMD_ERASE1;
+		*addrw = BANK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+}
+
+static int bank_erase_poll (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		bank_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf ("  checking status at addr "
+			"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
+#endif
+		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & BANK_STAT_ERR) != 0) {
+			printf (" failed on sector %d "
+				"(stat = 0x%08x) at "
+				"address 0x%p\n", sect, stat, addrw);
+			*addrw = BANK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+int write_word_intel (bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf ("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+      done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+
+#ifdef FLASH_DEBUG
+	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info (info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init (info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer (start);
+
+			do {
+				now = get_timer (start);
+
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll (info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset (info, sect);
+		}
+	}
+	return haderr;
+}
diff --git a/u-boot/board/Marvell/common/intel_flash.h b/u-boot/board/Marvell/common/intel_flash.h
new file mode 100644
index 0000000..bd8941e
--- /dev/null
+++ b/u-boot/board/Marvell/common/intel_flash.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
+#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
+#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
+#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST		0xFF		/* reset flash */
+#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
+#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define CHIP_CMD_PROG		0x40		/* program word command */
+#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
+#define CHIP_STAT_VPPS		0x08		/* VPP Status */
+#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
+#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
+#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS		128
+#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
+#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS		CHIP_NBLOCKS
+#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS		1		/* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o)	((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/u-boot/board/Marvell/common/memory.c b/u-boot/board/Marvell/common/memory.c
new file mode 100644
index 0000000..45353af
--- /dev/null
+++ b/u-boot/board/Marvell/common/memory.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright - Galileo technology.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * written or collected and sometimes rewritten by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ */
+
+
+#include <common.h>
+#include "../include/core.h"
+#include "../include/memory.h"
+
+/*******************************************************************************
+* memoryGetBankBaseAddress - Returns the base address of a memory bank.
+* DESCRIPTION:
+*       This function returns the base address of one of the SDRAM’s memory
+*       banks. There are 4 memory banks and each one represents one DIMM side.
+* INPUT:
+*       MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit Memory bank base address.
+*******************************************************************************/
+static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
+{
+	switch (bank) {
+	case BANK0:
+		return SCS_0_LOW_DECODE_ADDRESS;
+	case BANK1:
+		return SCS_1_LOW_DECODE_ADDRESS;
+	case BANK2:
+		return SCS_2_LOW_DECODE_ADDRESS;
+	case BANK3:
+		return SCS_3_LOW_DECODE_ADDRESS;
+
+	}
+	return SCS_0_LOW_DECODE_ADDRESS;	/* default value */
+}
+
+unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
+{
+	unsigned int base;
+	unsigned int regOffset = memoryGetBankRegOffset (bank);
+
+	GT_REG_READ (regOffset, &base);
+	base = base << 16;	/* MV6436x */
+	return base;
+}
+
+/*******************************************************************************
+* memoryGetDeviceBaseAddress - Returns the base address of a device.
+* DESCRIPTION:
+*       This function returns the base address of a device on the system. There
+*       are 5 possible devices (0 - 4 and one boot device) as defined in
+*       gtMemory.h. Each of the device parameters is maped to one of the CS
+*       (Devices chip selects) base address register.
+* INPUT:
+*       device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit Device base address.
+*
+*******************************************************************************/
+static unsigned int memoryGetDeviceRegOffset (DEVICE device)
+{
+	switch (device) {
+	case DEVICE0:
+		return CS_0_LOW_DECODE_ADDRESS;
+	case DEVICE1:
+		return CS_1_LOW_DECODE_ADDRESS;
+	case DEVICE2:
+		return CS_2_LOW_DECODE_ADDRESS;
+	case DEVICE3:
+		return CS_3_LOW_DECODE_ADDRESS;
+	case BOOT_DEVICE:
+		return BOOTCS_LOW_DECODE_ADDRESS;
+	}
+	return CS_0_LOW_DECODE_ADDRESS;	/* default value */
+}
+
+unsigned int memoryGetDeviceBaseAddress (DEVICE device)
+{
+	unsigned int regBase;
+	unsigned int regOffset = memoryGetDeviceRegOffset (device);
+
+	GT_REG_READ (regOffset, &regBase);
+
+	regBase = regBase << 16;	/* MV6436x */
+	return regBase;
+}
+
+/*******************************************************************************
+* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
+* DESCRIPTION:
+*       This function returns the base address of a PCI window. There are 5
+*       possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
+*       interface as defined in gtMemory.h, used by the CPU's address decoding
+*       mechanism.
+*	New in MV6436x
+* INPUT:
+*       pciWindow - Selects one of the PCI windows as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit PCI window base address.
+*******************************************************************************/
+unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
+{
+	unsigned int baseAddrReg, base;
+
+	switch (pciWindow) {
+	case PCI_0_IO:
+		baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR;  */
+		break;
+	case PCI_0_MEM0:
+		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
+		break;
+	case PCI_0_MEM1:
+		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
+		break;
+	case PCI_0_MEM2:
+		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR;  */
+		break;
+	case PCI_0_MEM3:
+		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR;  */
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR;  */
+		break;
+	case PCI_1_MEM0:
+		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
+		break;
+	case PCI_1_MEM1:
+		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
+		break;
+	case PCI_1_MEM2:
+		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
+		break;
+	case PCI_1_MEM3:
+		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		return 0xffffffff;
+	}
+	GT_REG_READ (baseAddrReg, &base);
+	return (base << 16);
+}
+
+/*******************************************************************************
+* memoryGetBankSize - Returns the size of a memory bank.
+* DESCRIPTION:
+*       This function returns the size of memory bank as described in
+*       'gtMemoryGetBankBaseAddress' function.
+* INPUT:
+*       bank - Selects one of the four banks as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit size memory bank size or 0 for a closed or non populated bank.
+*
+*******************************************************************************/
+unsigned int memoryGetBankSize (MEMORY_BANK bank)
+{
+	unsigned int sizeReg, size;
+	MEMORY_WINDOW window;
+
+	switch (bank) {
+	case BANK0:
+		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/* CS_0_SIZE; */
+		window = CS_0_WINDOW;
+		break;
+	case BANK1:
+		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/* CS_1_SIZE; */
+		window = CS_1_WINDOW;
+		break;
+	case BANK2:
+		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/* CS_2_SIZE; */
+		window = CS_2_WINDOW;
+		break;
+	case BANK3:
+		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/* CS_3_SIZE; */
+		window = CS_3_WINDOW;
+		break;
+	default:
+		return 0;
+		break;
+	}
+	/* If the window is closed, a size of 0 is returned */
+	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
+		return 0;
+	GT_REG_READ (sizeReg, &size);
+	size = ((size << 16) | 0xffff) + 1;
+	return size;
+}
+
+/*******************************************************************************
+* memoryGetDeviceSize - Returns the size of a device memory space.
+* DESCRIPTION:
+*       This function returns the memory space size of a given device.
+* INPUT:
+*       device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit size of a device memory space.
+*******************************************************************************/
+unsigned int memoryGetDeviceSize (DEVICE device)
+{
+	unsigned int sizeReg, size;
+	MEMORY_WINDOW window;
+
+	switch (device) {
+	case DEVICE0:
+		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
+		window = DEVCS_0_WINDOW;
+		break;
+	case DEVICE1:
+		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
+		window = DEVCS_1_WINDOW;
+		break;
+	case DEVICE2:
+		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
+		window = DEVCS_2_WINDOW;
+		break;
+	case DEVICE3:
+		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
+		window = DEVCS_3_WINDOW;
+		break;
+	case BOOT_DEVICE:
+		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
+		window = BOOT_CS_WINDOW;
+		break;
+	default:
+		return 0;
+		break;
+	}
+	/* If the window is closed, a size of 0 is returned */
+	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
+		return 0;
+	GT_REG_READ (sizeReg, &size);
+	size = ((size << 16) | 0xffff) + 1;
+	return size;
+}
+
+/*******************************************************************************
+* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
+* DESCRIPTION:
+*       This function returns the size of a PCI window.
+* INPUT:
+*       pciWindow - Selects one of the PCI memory windows as defined in
+*       Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit size of a PCI memory window.
+*******************************************************************************/
+unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
+{
+	unsigned int sizeReg, size;
+
+	switch (pciWindow) {
+	case PCI_0_IO:
+		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
+		break;
+	case PCI_0_MEM0:
+		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
+		break;
+	case PCI_0_MEM1:
+		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
+		break;
+	case PCI_0_MEM2:
+		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
+		break;
+	case PCI_0_MEM3:
+		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
+		break;
+	case PCI_1_MEM0:
+		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
+		break;
+	case PCI_1_MEM1:
+		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE;  */
+		break;
+	case PCI_1_MEM2:
+		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE;  */
+		break;
+	case PCI_1_MEM3:
+		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		return 0x0;
+	}
+	/* If the memory window is disabled, retrun size = 0 */
+	if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
+	    == MEM_WINDOW_DISABLED)
+		return 0;
+	GT_REG_READ (sizeReg, &size);
+	size = ((size << 16) | 0xffff) + 1;
+	return size;
+}
+
+/*******************************************************************************
+* memoryGetDeviceWidth - Returns the width of a given device.
+* DESCRIPTION:
+*       The MV's device interface supports up to 32 Bit wide devices. A device
+*       can have a  1, 2, 4 or 8 Bytes data width. This function returns the
+*       width of a device as defined by the user or the operating system.
+* INPUT:
+*       device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
+*******************************************************************************/
+unsigned int memoryGetDeviceWidth (DEVICE device)
+{
+	unsigned int width;
+	unsigned int regValue;
+
+	GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, &regValue);
+	width = (regValue & (BIT20 | BIT21)) >> 20;
+	return (BIT0 << width);
+}
+
+/*******************************************************************************
+* memoryMapBank - Set new base address and size for one of the memory
+*                         banks.
+*
+* DESCRIPTION:
+*       The CPU interface address decoding map consists of 21 address windows
+*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+*       space. Each address window is defined by two registers - base and size.
+*       The CPU address is compared with the values in the various CPU windows
+*       until a match is found and the address is than targeted to that window.
+*       This function sets new base and size for one the memory banks
+*       (CS0 - CS3). It is the programmer`s responsibility to make sure that
+*       there are no conflicts with other memory spaces. When two memory spaces
+*       overlap, the MV’s behavior is not defined .If a bank needs to be closed,
+*       set the ’bankLength’ parameter size to 0x0.
+*
+* INPUT:
+*       bank      - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
+*       bankBase  - The memory bank base address.
+*       bankLength  - The memory bank size. This function will decrement the
+*                   'bankLength' parameter by one and then check if the size is
+*                   valid. A valid size must be programed from LSB to MSB as
+*                   sequence of ‘1’s followed by sequence of ‘0’s.
+*                   To close a memory window simply set the size to 0.
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+* OUTPUT:
+*       None.
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
+*
+*******************************************************************************/
+
+bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
+		    unsigned int bankLength)
+{
+	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
+
+/*    PCI_INTERNAL_BAR pciBAR; */
+
+	switch (bank) {
+	case BANK0:
+		baseReg = SCS_0_LOW_DECODE_ADDRESS;	/*CS_0_BASE_ADDR; */
+		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/*CS_0_SIZE; */
+/*        pciBAR = PCI_CS0_BAR; */
+		break;
+	case BANK1:
+		baseReg = SCS_1_LOW_DECODE_ADDRESS;	/*CS_1_BASE_ADDR; */
+		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/*CS_1_SIZE; */
+		/*        pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
+		break;
+	case BANK2:
+		baseReg = SCS_2_LOW_DECODE_ADDRESS;	/*CS_2_BASE_ADDR; */
+		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/*CS_2_SIZE; */
+/*        pciBAR = PCI_CS2_BAR;*/
+		break;
+	case BANK3:
+		baseReg = SCS_3_LOW_DECODE_ADDRESS;	/*CS_3_BASE_ADDR; */
+		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/*CS_3_SIZE; */
+/*        pciBAR = PCI_CS3_BAR; */
+		break;
+	default:
+		return false;
+	}
+	/* If the size is 0, the window will be disabled */
+	if (bankLength == 0) {
+		MemoryDisableWindow (CS_0_WINDOW << bank);
+		/* Disable the BAR from the PCI slave side */
+/*        gtPci0DisableInternalBAR(pciBAR); */
+/*        gtPci1DisableInternalBAR(pciBAR); */
+		return true;
+	}
+	/* The base address must be aligned to the size */
+	if ((bankBase % bankLength) != 0) {
+		return false;
+	}
+	if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
+		newBase = bankBase >> 16;
+		newSize = bankLength >> 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = newSize - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid	 */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+#ifdef DEBUG
+		{
+			unsigned int oldBase, oldSize;
+
+			GT_REG_READ (baseReg, &oldBase);
+			GT_REG_READ (sizeReg + 8, &oldSize);
+
+			printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
+				bank, oldBase, oldSize, newBase, newSize);
+		}
+#endif
+		/* writing the new values */
+		GT_REG_WRITE (baseReg, newBase);
+		GT_REG_WRITE (sizeReg, newSize - 1);
+		/* Enable back the window */
+		MemoryEnableWindow (CS_0_WINDOW << bank);
+		/* Enable the BAR from the PCI slave side */
+/*        gtPci0EnableInternalBAR(pciBAR); */
+/*        gtPci1EnableInternalBAR(pciBAR); */
+		return true;
+	}
+	return false;
+}
+
+
+/*******************************************************************************
+* memoryMapDeviceSpace - Set new base address and size for one of the device
+*                           windows.
+*
+* DESCRIPTION:
+*       The CPU interface address decoding map consists of 21 address windows
+*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+*       space. Each address window is defined by two registers - base and size.
+*       The CPU address is compared with the values in the various CPU windows
+*       until a match is found and the address is than targeted to that window.
+*       This function sets new base and size for one the device windows
+*       (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
+*       that there are no conflicts with other memory spaces. When two memory
+*       spaces overlap, the MV’s behavior is not defined .If a device window
+*       needs to be closed, set the 'deviceLength' parameter size to 0x0.
+*
+* INPUT:
+*       device           - One of the device windows (DEV_CS0-DEV_CS3) as
+*                          defined in gtMemory.h.
+*       deviceBase - The device window base address.
+*       deviceLength - The device window size. This function will decrement
+*                          the 'deviceLength' parameter by one and then
+*                          check if the size is valid. A valid size must be
+*                          programed from LSB to MSB as sequence of ‘1’s
+*                          followed by sequence of ‘0’s.
+*                          To close a memory window simply set the size to 0.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
+*
+*******************************************************************************/
+
+bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
+			   unsigned int deviceLength)
+{
+	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
+
+/*    PCI_INTERNAL_BAR pciBAR;*/
+
+	switch (device) {
+	case DEVICE0:
+		baseReg = CS_0_LOW_DECODE_ADDRESS;	/*DEV_CS0_BASE_ADDR; */
+		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
+/*        pciBAR = PCI_DEV_CS0_BAR; */
+		break;
+	case DEVICE1:
+		baseReg = CS_1_LOW_DECODE_ADDRESS;	/*DEV_CS1_BASE_ADDR; */
+		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
+/*        pciBAR = PCI_DEV_CS1_BAR; */
+		break;
+	case DEVICE2:
+		baseReg = CS_2_LOW_DECODE_ADDRESS;	/*DEV_CS2_BASE_ADDR; */
+		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
+/*        pciBAR = PCI_DEV_CS2_BAR; */
+		break;
+	case DEVICE3:
+		baseReg = CS_3_LOW_DECODE_ADDRESS;	/*DEV_CS3_BASE_ADDR; */
+		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
+/*        pciBAR = PCI_DEV_CS3_BAR; */
+		break;
+	case BOOT_DEVICE:
+		baseReg = BOOTCS_LOW_DECODE_ADDRESS;	/*BOOTCS_BASE_ADDR; */
+		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
+/*        pciBAR = PCI_BOOT_CS_BAR; */
+		break;
+	default:
+		return false;
+	}
+	if (deviceLength == 0) {
+		MemoryDisableWindow (DEVCS_0_WINDOW << device);
+		/* Disable the BAR from the PCI slave side */
+/*        gtPci0DisableInternalBAR(pciBAR); */
+/*        gtPci1DisableInternalBAR(pciBAR); */
+		return true;
+	}
+	/* The base address must be aligned to the size */
+	if ((deviceBase % deviceLength) != 0) {
+		return false;
+	}
+	if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
+		newBase = deviceBase >> 16;
+		newSize = deviceLength >> 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = newSize - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid       */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+		/* writing the new values */
+		GT_REG_WRITE (baseReg, newBase);
+		GT_REG_WRITE (sizeReg, newSize - 1);
+		MemoryEnableWindow (DEVCS_0_WINDOW << device);
+		/* Enable the BAR from the PCI slave side */
+/*        gtPci0EnableInternalBAR(pciBAR); */
+/*        gtPci1EnableInternalBAR(pciBAR); */
+		return true;
+	}
+	return false;
+}
+
+/*******************************************************************************
+* MemorySetPciWindow - Set new base address and size for one of the PCI
+*                        windows.
+*
+* DESCRIPTION:
+*       The CPU interface address decoding map consists of 21 address windows
+*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+*       space. Each address window is defined by two registers - base and size.
+*       The CPU address is compared with the values in the various CPU windows
+*       until a match is found and the address is than targeted to that window.
+*       This function sets new base and size for one the PCI windows
+*       (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
+*       that there are no conflicts with other memory spaces. When two memory
+*       spaces overlap, the MV’s behavior is not defined .If a PCI window
+*       needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
+*
+* INPUT:
+*       pciWindow     - One of the PCI windows as defined in gtMemory.h.
+*       pciWindowBase - The PCI window base address.
+*       pciWindowSize - The PCI window size. This function will decrement the
+*                       'pciWindowSize' parameter by one and then check if the
+*                       size is valid. A valid size must be programed from LSB
+*                       to MSB as sequence of ‘1’s followed by sequence of ‘0’s.
+*                       To close a memory window simply set the size to 0.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+*******************************************************************************/
+bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+			 unsigned int pciWindowSize)
+{
+	unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
+
+	switch (pciWindow) {
+	case PCI_0_IO:
+		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR; */
+		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
+		break;
+	case PCI_0_MEM0:
+		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
+		break;
+	case PCI_0_MEM1:
+		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
+		break;
+	case PCI_0_MEM2:
+		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
+		break;
+	case PCI_0_MEM3:
+		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR; */
+		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
+		break;
+	case PCI_1_MEM0:
+		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
+		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
+		break;
+	case PCI_1_MEM1:
+		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
+		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE; */
+		break;
+	case PCI_1_MEM2:
+		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
+		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE; */
+		break;
+	case PCI_1_MEM3:
+		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
+		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		return false;
+	}
+	if (pciWindowSize == 0) {
+		MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
+		return true;
+	}
+	/* The base address must be aligned to the size */
+	if ((pciWindowBase % pciWindowSize) != 0) {
+		return false;
+	}
+	if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
+		pciWindowBase >>= 16;
+		pciWindowSize >>= 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = pciWindowSize - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid       */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+		GT_REG_WRITE (sizeReg, pciWindowSize - 1);
+		GT_REG_READ (baseAddrReg, &currentLow);
+		pciWindowBase =
+			(pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
+		GT_REG_WRITE (baseAddrReg, pciWindowBase);
+		MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
+		return true;
+	}
+	return false;
+}
+
+/*******************************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internal
+*                                  registers memory space.
+*
+* DESCRIPTION:
+*       This function set new base address for the internal register’s memory
+*       space (the size is fixed and cannot be modified). The function does not
+*       handle overlapping with other memory spaces, it is the programer's
+*       responsibility to ensure that overlapping does not occur.
+*       When two memory spaces overlap, the MV’s behavior is not defined.
+*
+* INPUT:
+*       internalRegBase - new base address for the internal register’s memory
+*                         space.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*        true on success, false on failure
+*
+*******************************************************************************/
+/********************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internals
+*                                   registers.
+*
+* INPUTS:  unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
+{
+	unsigned int currentValue;
+	unsigned int internalValue = internalRegBase;
+
+	internalRegBase = (internalRegBase >> 16);
+	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
+	internalRegBase = (currentValue & 0xff000000) | internalRegBase;
+	GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
+	/* initializing also the global variable 'internalRegBaseAddr' */
+/*    gtInternalRegBaseAddr = internalValue; */
+	INTERNAL_REG_BASE_ADDR = internalValue;
+	return true;
+}
+
+/*******************************************************************************
+* memoryGetInternalRegistersSpace - Returns the internal registers Base
+*                                     address.
+*
+* DESCRIPTION:
+*       This function returns the base address of  the internal register’s
+*       memory space .
+*
+* INPUT:
+*       None.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       32 bit base address of the internal register’s memory space.
+*
+*******************************************************************************/
+unsigned int memoryGetInternalRegistersSpace (void)
+{
+	unsigned int currentValue = 0;
+
+	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
+	return ((currentValue & 0x000fffff) << 16);
+}
+
+/*******************************************************************************
+* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
+*
+* DESCRIPTION:
+*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
+*       funcnion return the SRAM's base address.
+* INPUT:
+*       None.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit SRAM's base address.
+*
+*******************************************************************************/
+unsigned int memoryGetInternalSramBaseAddr (void)
+{
+	return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
+}
+
+/*******************************************************************************
+* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
+*
+* DESCRIPTION:
+*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
+*       function sets a new base address to the SRAM .
+* INPUT:
+*       sramBaseAddress - The SRAM's base address.
+* OUTPUT:
+*       None.
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
+{
+	GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
+}
+
+/*******************************************************************************
+* memorySetProtectRegion - Set protection mode for one of the 8 regions.
+*
+* DESCRIPTION:
+*       The CPU interface supports configurable access protection. This includes
+*       up to eight address ranges defined to a different protection type :
+*       whether the address range is cacheable or not, whether it is writable or
+*       not , and whether it is accessible or not. A Low and High registers
+*       define each window while the minimum address range of each window is
+*       1Mbyte. An address driven by the CPU, in addition to the address
+*       decoding and remapping process, is compared against the eight Access
+*       Protection Low/High registers , if an address matches one of the windows
+*       , the MV device checks the transaction type against the protection bits
+*       defined in CPU Access Protection register, to determine if the access is
+*       allowed. This function set a protection mode to one of the 8 possible
+*       regions.
+*      NOTE:
+*       The CPU address windows are restricted to a size of  2 power n and the
+*       start address must be aligned to the window size. For example, if using
+*       a 16 MB window, the start address bits [23:0] must be 0.The MV's
+*       internal registers space is not protected, even if the access protection
+*       windows contain this space.
+*
+* INPUT:
+*       region - selects which region to be configured. The values defined in
+*                gtMemory.h:
+*
+*                 - MEM_REGION0
+*                 - MEM_REGION1
+*                 - etc.
+*
+*       memAccess - Allows or forbids access (read or write ) to the region. The
+*                   values defined in gtMemory.h:
+*
+*                    - MEM_ACCESS_ALLOWED
+*                    - MEM_ACCESS_FORBIDEN
+*
+*       memWrite - CPU write protection to the region. The values defined in
+*                  gtMemory.h:
+*
+*                   - MEM_WRITE_ALLOWED
+*                   - MEM_WRITE_FORBIDEN
+*
+*       cacheProtection - Defines whether caching the region is allowed or not.
+*                         The values defined in gtMemory.h:
+*
+*                          - MEM_CACHE_ALLOWED
+*                          - MEM_CACHE_FORBIDEN
+*
+*       baseAddress - the region's base Address.
+*       regionSize  - The region's size. This function will decrement the
+*                     'regionSize' parameter by one and then check if the size
+*                     is valid. A valid size must be programed from LSB to MSB
+*                     as sequence of ‘1’s followed by sequence of ‘0’s.
+*                     To close a memory window simply set the size to 0.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+*******************************************************************************/
+bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
+			     MEMORY_ACCESS memAccess,
+			     MEMORY_ACCESS_WRITE memWrite,
+			     MEMORY_CACHE_PROTECT cacheProtection,
+			     unsigned int baseAddress, unsigned int size)
+{
+	unsigned int dataForReg, temp, rShift;
+
+	if (size == 0) {
+		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
+			      0x0);
+		return true;
+	}
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size >= MINIMUM_ACCESS_WIN_SIZE) {
+		baseAddress = ((baseAddress >> 16) & 0xfffff);
+		dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
+			((memWrite << 21) & BIT21) | ((cacheProtection << 22)
+						      & BIT22) | BIT31;
+		GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
+			      dataForReg);
+		size >>= 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = size - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid       */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
+			      size - 1);
+		return true;
+	}
+	return false;
+}
+
+/*******************************************************************************
+* gtMemoryDisableProtectRegion - Disable a protected window.
+*
+* DESCRIPTION:
+*       This function disable a protected window set by
+*       'gtMemorySetProtectRegion' function.
+*
+* INPUT:
+*       window - one of the 4 windows ( defined in gtMemory.h ).
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
+{
+	RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
+			BIT31);
+}
+
+/*******************************************************************************
+* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
+*
+* DESCRIPTION:
+*       In addition to the address decoding mechanism, the CPU has an address
+*       remapping mechanism to be used by every PCI decoding window. Each PCI
+*       window can be remaped to a desired address target according to the remap
+*       value within the remap register. The address remapping is useful when a
+*       CPU address range must be reallocated to a different location on the
+*       PCI bus. Also, it enables CPU access to a PCI agent located above the
+*       4Gbyte space. On system boot, each of the PCI memory spaces is maped to
+*       a defualt value (see CPU interface section in the MV spec for the
+*       default values). The remap mechanism does not always produce the desired
+*       address on the PCI bus because of the remap mechanism way of working
+*       (to fully understand why, please see the 'Address Remapping' section in
+*       the MV's spec). Therefor, this function sets a desired remap value to
+*       one of the PCI memory windows and return the effective address that
+*       should be used when exiting the PCI memory window. You should ALWAYS use
+*       the returned value by this function when remapping a PCI window and
+*       exiting it. If for example the base address of PCI0 memory 0 is
+*       0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
+*       the function will return the value of 0x91000000 that MUST
+*       be used to exit this memory window in order to achive the deisred
+*       remapping.
+*
+* INPUT:
+*       memoryWindow   - One of the PCI memory windows as defined in Memory.h
+*       remapValueLow  - The low remap value.
+*       remapValueHigh - The high remap value.
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       The effective base address to exit the PCI, or 0xffffffff if one of the
+*       parameters is erroneous or the effective base address is higher the top
+*       decode value.
+*
+*******************************************************************************/
+unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
+				     unsigned int remapValueHigh,
+				     unsigned int remapValueLow)
+{
+	unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
+	unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
+	unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
+
+	/* Initializing the base and size variables of the PCI
+	   memory windows */
+	switch (memoryWindow) {
+	case PCI_0_IO:
+		pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_IO_SIZE;
+		remapRegLow = PCI_0_IO_ADDR_REMAP;
+		remapRegHigh = PCI_0_IO_ADDR_REMAP;
+		break;
+	case PCI_0_MEM0:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
+		remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
+		break;
+	case PCI_0_MEM1:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
+		remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
+		break;
+	case PCI_0_MEM2:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
+		remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
+		break;
+	case PCI_0_MEM3:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
+		remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_IO_SIZE;
+		remapRegLow = PCI_1_IO_ADDR_REMAP;
+		remapRegHigh = PCI_1_IO_ADDR_REMAP;
+		break;
+	case PCI_1_MEM0:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
+		remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
+		break;
+	case PCI_1_MEM1:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
+		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
+		break;
+	case PCI_1_MEM2:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
+		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
+		break;
+	case PCI_1_MEM3:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
+		remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		/* Retrun an invalid effective base address */
+		return 0xffffffff;
+	}
+	/* Writing the remap value to the remap regisers */
+	GT_REG_WRITE (remapRegHigh, remapValueHigh);
+	GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
+	/* Reading the values from the base address and size registers */
+	baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
+	windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
+	/* Start calculating the effective Base Address */
+	effectiveBaseAddress = baseAddrValue << 16;
+	/* The effective base address will be combined from the chopped (if any)
+	   remap value (according to the size value and remap mechanism) and the
+	   window's base address */
+	effectiveBaseAddress |=
+		(((windowSizeValue << 16) | 0xffff) & remapValueLow);
+	/* If the effectiveBaseAddress exceed the window boundaries return an
+	   invalid value. */
+	if (effectiveBaseAddress >
+	    ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
+		return 0xffffffff;
+	return effectiveBaseAddress;
+}
+
+/********************************************************************
+* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
+*                            supports Cache Coherency.
+*
+*
+* Inputs: SNOOP_REGION region - One of the four regions.
+*         SNOOP_TYPE snoopType - There is four optional Types:
+*                               1. No Snoop.
+*                               2. Snoop to WT region.
+*                               3. Snoop to WB region.
+*                               4. Snoop & Invalidate to WB region.
+*         unsigned int baseAddress - Base Address of this region.
+*         unsigned int topAddress - Top Address of this region.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+/* evb6260 code */
+#if 0
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength)
+{
+    unsigned int snoopXbaseAddress;
+    unsigned int snoopXtopAddress;
+    unsigned int data;
+    unsigned int snoopHigh = baseAddress + regionLength;
+
+    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
+	return false;
+    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
+    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
+				 if(regionLength == 0) /* closing the region */
+    {
+	GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
+	GT_REG_WRITE(snoopXtopAddress,0);
+	return true;
+    }
+    baseAddress = baseAddress & 0xffff0000;
+    data = (baseAddress >> 16) | snoopType << 16;
+    GT_REG_WRITE(snoopXbaseAddress,data);
+    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
+    return true;
+}
+#endif
+
+/********************************************************************
+* memoryRemapAddress - This fubction used for address remapping.
+*
+*
+* Inputs: regOffset: remap register
+*         remapValue :
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*
+* Not needed function To_do !!!!
+*********************************************************************/
+bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
+{
+	unsigned int valueForReg;
+
+	valueForReg = (remapValue & 0xfff00000) >> 20;
+	GT_REG_WRITE (remapReg, valueForReg);
+	return true;
+}
+
+/*******************************************************************************
+* memoryGetDeviceParam - Extract the device parameters from the device bank
+*                          parameters register.
+*
+* DESCRIPTION:
+*       To allow interfacing with very slow devices and fast synchronous SRAMs,
+*       each device can be programed to different timing parameters. Each bank
+*       has its own parameters register. Bank width can be programmed to 8, 16,
+*       or 32-bits. Bank timing parameters can be programmed to support
+*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
+*       Controllers). The MV allows you to set timing parameters and width for
+*       each device through parameters register .
+*       This function extracts the parameters described from the Device Bank
+*       parameters register and fills the given 'deviceParam' (defined in
+*       gtMemory.h) structure with the read data.
+*
+* INPUT:
+*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
+*                      Memory.h).For details about each structure field please
+*                      see the device timing parameter section in the MV
+*                      datasheet.
+*       deviceNum  -   Select on of the five device banks (defined in
+*                      Memory.h) :
+*
+*                       - DEVICE0
+*                       - DEVICE1
+*                       - DEVICE2
+*                       - etc.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       false if one of the parameters is erroneous,true otherwise.
+*
+*******************************************************************************/
+/********************************************************************
+* memoryGetDeviceParam - This function used for getting device parameters from
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+
+bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
+{
+	unsigned int valueOfReg;
+	unsigned int calcData;
+
+	if (deviceNum > 4)
+		return false;
+	GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
+	calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
+	deviceParam->turnOff = calcData;	/* Turn Off */
+
+	calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
+	deviceParam->acc2First = calcData;	/* Access To First */
+
+	calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
+	deviceParam->acc2Next = calcData;	/* Access To Next */
+
+	calcData =
+		((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
+	deviceParam->ale2Wr = calcData;	/* Ale To Write */
+
+	calcData = ((0x1c000 & valueOfReg) >> 14) +
+		((BIT26 & valueOfReg) >> 23);
+	deviceParam->wrLow = calcData;	/* Write Active */
+
+	calcData = ((0xe0000 & valueOfReg) >> 17) +
+		((BIT27 & valueOfReg) >> 24);
+	deviceParam->wrHigh = calcData;	/* Write High */
+
+	calcData = ((0x300000 & valueOfReg) >> 20);
+	deviceParam->deviceWidth = (BIT0 << calcData);	/* In bytes */
+	calcData = ((0x30000000 & valueOfReg) >> 28);
+	deviceParam->badrSkew = calcData;	/* Cycles gap between BAdr
+						   toggle to read data sample. */
+	calcData = ((0x40000000 & valueOfReg) >> 30);
+	deviceParam->DPEn = calcData;	/*  Data Parity enable  */
+	return true;
+}
+
+/*******************************************************************************
+* memorySetDeviceParam - Set new parameters for a device.
+*
+*
+* DESCRIPTION:
+*       To allow interfacing with very slow devices and fast synchronous SRAMs,
+*       each device can be programed to different timing parameters. Each bank
+*       has its own parameters register. Bank width can be programmed to 8, 16,
+*       or 32-bits. Bank timing parameters can be programmed to support
+*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
+*       Controllers). The MV allows you to set timing parameters and width for
+*       each device through parameters register. This function set new
+*       parameters to a device Bank from the delivered structure 'deviceParam'
+*       (defined in gtMemory.h). The structure must be initialized with data
+*       prior to the use of these function.
+*
+* INPUT:
+*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
+*                      Memory.h).For details about each structure field please
+*                      see the device timing parameter section in the MV
+*                      datasheet.
+*       deviceNum  -   Select on of the five device banks (defined in
+*                      Memory.h) :
+*
+*                       - DEVICE0
+*                       - DEVICE1
+*                       - DEVICE2
+*                       - etc.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       false if one of the parameters is erroneous,true otherwise.
+*
+*******************************************************************************/
+/********************************************************************
+* memorySetDeviceParam - This function used for setting device parameters to
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
+{
+	unsigned int valueForReg;
+
+	if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
+	    (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
+	    (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
+	    (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
+		return false;
+	}
+	valueForReg = (((deviceParam->turnOff) & 0x7) |
+		       (((deviceParam->turnOff) & 0x8) << 19) |
+		       (((deviceParam->acc2First) & 0xf) << 3) |
+		       (((deviceParam->acc2First) & 0x10) << 19) |
+		       (((deviceParam->acc2Next) & 0xf) << 7) |
+		       (((deviceParam->acc2Next) & 0x10) << 20) |
+		       (((deviceParam->ale2Wr) & 0x7) << 11) |
+		       (((deviceParam->ale2Wr) & 0xf) << 22) |
+		       (((deviceParam->wrLow) & 0x7) << 14) |
+		       (((deviceParam->wrLow) & 0xf) << 23) |
+		       (((deviceParam->wrHigh) & 0x7) << 17) |
+		       (((deviceParam->wrHigh) & 0xf) << 24) |
+		       (((deviceParam->badrSkew) & 0x3) << 28) |
+		       (((deviceParam->DPEn) & 0x1) << 30));
+
+	/* insert the device width: */
+	switch (deviceParam->deviceWidth) {
+	case 1:
+		valueForReg = valueForReg | _8BIT;
+		break;
+	case 2:
+		valueForReg = valueForReg | _16BIT;
+		break;
+	case 4:
+		valueForReg = valueForReg | _32BIT;
+		break;
+	default:
+		valueForReg = valueForReg | _8BIT;
+		break;
+	}
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
+	return true;
+}
+
+/*******************************************************************************
+* MemoryDisableWindow - Disable a memory space by the disable bit.
+* DESCRIPTION:
+*       This function disables one of the 21 availiable windows dedicated for
+*       the CPU decoding mechanism. Its possible to combine several windows with
+*       the OR command.
+* INPUT:
+*       window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+*       None.
+* RETURN:
+*       None.
+*******************************************************************************/
+void MemoryDisableWindow (MEMORY_WINDOW window)
+{
+	SET_REG_BITS (BASE_ADDR_ENABLE, window);
+}
+
+/*******************************************************************************
+* MemoryEnableWindow - Enable a memory space that was disabled by
+*                       'MemoryDisableWindow'.
+* DESCRIPTION:
+*       This function enables one of the 21 availiable windows dedicated for the
+*       CPU decoding mechanism. Its possible to combine several windows with the
+*       OR command.
+* INPUT:
+*       window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+*       None.
+* RETURN:
+*       None.
+*******************************************************************************/
+void MemoryEnableWindow (MEMORY_WINDOW window)
+{
+	RESET_REG_BITS (BASE_ADDR_ENABLE, window);
+}
+
+/*******************************************************************************
+* MemoryGetMemWindowStatus - This function check whether the memory window is
+*                              disabled or not.
+* DESCRIPTION:
+*       This function checks if the given memory window is closed .
+* INPUT:
+*       window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+*       None.
+* RETURN:
+*       True for a closed window, false otherwise .
+*******************************************************************************/
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
+{
+	if (GTREGREAD (BASE_ADDR_ENABLE) & window)
+		return MEM_WINDOW_DISABLED;
+	return MEM_WINDOW_ENABLED;
+}
diff --git a/u-boot/board/Marvell/common/misc.S b/u-boot/board/Marvell/common/misc.S
new file mode 100644
index 0000000..b3a0898
--- /dev/null
+++ b/u-boot/board/Marvell/common/misc.S
@@ -0,0 +1,235 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CONFIG_SYS_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+	stw	r21, 0x0(r18)
+/*	  stw	  r18, 0x0(r18) */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+	stw	r21, 0x0(r18)
+/*	  stw	  r18, 0x0(r18) */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+	stw	r18, 0x0(r18)
+	sync
+	blr
diff --git a/u-boot/board/Marvell/common/ns16550.c b/u-boot/board/Marvell/common/ns16550.c
new file mode 100644
index 0000000..7839b68
--- /dev/null
+++ b/u-boot/board/Marvell/common/ns16550.c
@@ -0,0 +1,66 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
+ *
+ * further modified by Josh Huber <huber@mclx.com> to support
+ * the DUART on the Galileo Eval board. (db64360)
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+#ifdef ZUMA_NTL
+/* no 16550 device */
+#else
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
+	(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
+};
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
+{
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
+
+	/* Clear & enable FIFOs */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+	return (com_port);
+}
+
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
+{
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
+
+	/* Clear & enable FIFOs */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+}
+
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
+{
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
+}
+
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
+{
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
+}
+
+int NS16550_tstc (volatile struct NS16550 *com_port)
+{
+	return ((com_port->lsr & LSR_DR) != 0);
+}
+#endif
diff --git a/u-boot/board/Marvell/common/ns16550.h b/u-boot/board/Marvell/common/ns16550.h
new file mode 100644
index 0000000..0a2951b
--- /dev/null
+++ b/u-boot/board/Marvell/common/ns16550.h
@@ -0,0 +1,102 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * further modified to support the DUART in the Galileo eval board
+ * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ */
+
+#ifndef __NS16550_H__
+#define __NS16550_H__
+
+/* the padding is necessary because on the galileo board the UART is
+   wired in with the 3 address lines shifted over by 2 bits */
+struct NS16550
+{
+	unsigned char rbr;  /* 0 = 0-3*/
+	int pad1:24;
+
+	unsigned char ier;  /* 1 = 4-7*/
+	int pad2:24;
+
+	unsigned char fcr;  /* 2 = 8-b*/
+	int pad3:24;
+
+	unsigned char lcr;  /* 3 = c-f*/
+	int pad4:24;
+
+	unsigned char mcr;  /* 4 = 10-13*/
+	int pad5:24;
+
+	unsigned char lsr;  /* 5 = 14-17*/
+	int pad6:24;
+
+	unsigned char msr;  /* 6 =18-1b*/
+	int pad7:24;
+
+	unsigned char scr;  /* 7 =1c-1f*/
+	int pad8:24;
+} __attribute__ ((packed));
+
+/* aliases */
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+#define FCR_FIFO_EN     0x01    /*fifo enable*/
+#define FCR_RXSR        0x02    /*reciever soft reset*/
+#define FCR_TXSR        0x04    /*transmitter soft reset*/
+
+
+#define MCR_DTR         0x01
+#define MCR_RTS         0x02
+#define MCR_DMA_EN      0x04
+#define MCR_TX_DFR      0x08
+
+
+#define LCR_WLS_MSK 0x03    /* character length slect mask*/
+#define LCR_WLS_5   0x00    /* 5 bit character length */
+#define LCR_WLS_6   0x01    /* 6 bit character length */
+#define LCR_WLS_7   0x02    /* 7 bit character length */
+#define LCR_WLS_8   0x03    /* 8 bit character length */
+#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08    /* Parity eneble*/
+#define LCR_EPS     0x10    /* Even Parity Select*/
+#define LCR_STKP    0x20    /* Stick Parity*/
+#define LCR_SBRK    0x40    /* Set Break*/
+#define LCR_BKSE    0x80    /* Bank select enable*/
+
+#define LSR_DR      0x01    /* Data ready */
+#define LSR_OE      0x02    /* Overrun */
+#define LSR_PE      0x04    /* Parity error */
+#define LSR_FE      0x08    /* Framing error */
+#define LSR_BI      0x10    /* Break */
+#define LSR_THRE    0x20    /* Xmit holding register empty */
+#define LSR_TEMT    0x40    /* Xmitter empty */
+#define LSR_ERR     0x80    /* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1     0x03
+
+
+#define COM1 0x03F8
+#define COM2 0x02F8
+
+volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
+void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc(volatile struct NS16550 *com_port);
+int NS16550_tstc(volatile struct NS16550 *com_port);
+void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+
+typedef struct NS16550 *NS16550_t;
+
+extern const NS16550_t COM_PORTS[];
+
+#endif
diff --git a/u-boot/board/Marvell/common/serial.c b/u-boot/board/Marvell/common/serial.c
new file mode 100644
index 0000000..3e7f406
--- /dev/null
+++ b/u-boot/board/Marvell/common/serial.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../include/memory.h"
+#include "serial.h"
+
+#ifdef CONFIG_DB64360
+#include "../db64360/mpsc.h"
+#endif
+
+#ifdef CONFIG_DB64460
+#include "../db64460/mpsc.h"
+#endif
+
+#include "ns16550.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_MPSC
+
+
+int serial_init (void)
+{
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+	int clock_divisor = 230400 / gd->baudrate;
+#endif
+
+	mpsc_init (gd->baudrate);
+
+	/* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CONFIG_SYS_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else  /* ! CONFIG_MPSC */
+
+int serial_init (void)
+{
+	int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	(void) NS16550_init (0, clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	(void) NS16550_init (1, clock_divisor);
+#endif
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
+
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+	int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/u-boot/board/Marvell/common/serial.h b/u-boot/board/Marvell/common/serial.h
new file mode 100644
index 0000000..c7fc8c1
--- /dev/null
+++ b/u-boot/board/Marvell/common/serial.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/u-boot/board/Marvell/db64360/64360.h b/u-boot/board/Marvell/db64360/64360.h
new file mode 100644
index 0000000..a65e23b
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/64360.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64360.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */
diff --git a/u-boot/board/Marvell/db64360/Makefile b/u-boot/board/Marvell/db64360/Makefile
new file mode 100644
index 0000000..036d255
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	= ../common/misc.o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
+	  sdram_init.o ../common/intel_flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/db64360/db64360.c b/u-boot/board/Marvell/db64360/db64360.c
new file mode 100644
index 0000000..35b695e
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/db64360.c
@@ -0,0 +1,937 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ */
+
+/*
+ * db64360.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+#include <netdev.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CONFIG_SYS_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
+		sram_boot = 1;
+	if (!sram_boot)
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
+
+
+	/* configure device timing */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
+	if (!sram_boot)
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+#endif
+
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+#endif
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+#endif
+
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CONFIG_SYS_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CONFIG_SYS_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
+	}
+	display_mem_map ();
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+	volatile int *addr = 0;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x08000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x0c000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x14000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x18000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x1c000);
+			break;
+		}
+	}
+
+	dummy = *addr;
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- EXT SRAM (actual - 1M)\n");
+		else if (i == 1)
+			printf ("\t- RTC\n");
+		else if (i == 2)
+			printf ("\t- UART\n");
+		else
+			printf ("\t- LARGE FLASH\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CONFIG_SYS_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
+
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
+
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+/*    rundata = 1; */
+/*    runaddress = 0; */
+/*    runwalk = 0; */
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+	}
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
+/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+
+	icache_disable ();
+	dcache_disable ();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/Marvell/db64360/eth.h b/u-boot/board/Marvell/db64360/eth.h
new file mode 100644
index 0000000..aab32d2
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/u-boot/board/Marvell/db64360/mpsc.c b/u-boot/board/Marvell/db64360/mpsc.c
new file mode 100644
index 0000000..7ad6ae8
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/mpsc.c
@@ -0,0 +1,1017 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../include/memory.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64360 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/u-boot/board/Marvell/db64360/mpsc.h b/u-boot/board/Marvell/db64360/mpsc.h
new file mode 100644
index 0000000..4b537ea
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/u-boot/board/Marvell/db64360/mv_eth.c b/u-boot/board/Marvell/db64360/mv_eth.c
new file mode 100644
index 0000000..30304b0
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/mv_eth.c
@@ -0,0 +1,3184 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64360_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64360_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64360_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64360_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64360 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64360_eth_real_open (struct eth_device *eth);
+static int mv64360_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64360_eth_update_stat (struct eth_device *dev);
+bool db64360_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64360_eth_receive (struct eth_device *dev);
+
+int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64360_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64360_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64360_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64360_eth
+ *
+ **********************************************************************/
+int db64360_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64360_eth_start (dev));
+}
+
+int db64360_eth_poll (struct eth_device *dev)
+{
+	return mv64360_eth_receive (dev);
+}
+
+int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64360_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64360_eth_disable (struct eth_device *dev)
+{
+	mv64360_eth_stop (dev);
+}
+
+
+void mv6436x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64360_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64360_eth_transmit;
+		dev->recv = (void *) db64360_eth_poll;
+
+		ethernet_private = calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *) ethernet_private;
+
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private = calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64360_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64360_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64360_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64360_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64360_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64360_eth_open (struct eth_device *dev)
+{
+	return (mv64360_eth_real_open (dev));
+}
+
+/* Helper function for mv64360_eth_open */
+static int mv64360_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status, phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64360_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64360_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64360_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64360_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64360_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64360_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64360_eth_stop */
+
+static int mv64360_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64360_eth_free_tx_rings (dev);
+	mv64360_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64360_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64360_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64360_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64360_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64360_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64360_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64360_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64360_eth_start (struct eth_device *dev)
+{
+	return (mv64360_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ *	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/u-boot/board/Marvell/db64360/mv_eth.h b/u-boot/board/Marvell/db64360/mv_eth.h
new file mode 100644
index 0000000..142910b
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/mv_eth.h
@@ -0,0 +1,843 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64360_ETH_H__
+#define __DB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include <asm/errno.h>
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64360_TX_QUEUE_NUM 1
+#define MV64360_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#else
+#define MV64360_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#else
+#define MV64360_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64360_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64360_TX_BUFFER_SIZE 1600
+#endif
+
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64360_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+
+int mv64360_eth_init (struct eth_device *dev);
+int mv64360_eth_stop (struct eth_device *dev);
+int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64360_eth0_poll(); */
+
+int mv64360_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64360_ETH_ */
diff --git a/u-boot/board/Marvell/db64360/mv_regs.h b/u-boot/board/Marvell/db64360/mv_regs.h
new file mode 100644
index 0000000..0d6370b
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/mv_regs.h
@@ -0,0 +1,1124 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64360r.h - GT-64360 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64360
+
+/* Supported by the Atlantis */
+#define MV64360_INCLUDE_PCI_1
+#define MV64360_INCLUDE_PCI_0_ARBITER
+#define MV64360_INCLUDE_PCI_1_ARBITER
+#define MV64360_INCLUDE_SNOOP_SUPPORT
+#define MV64360_INCLUDE_P2P
+#define MV64360_INCLUDE_ETH_PORT_2
+#define MV64360_INCLUDE_CPU_MAPPING
+#define MV64360_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64360_CS_0_BASE_ADDR					    0x008
+#define MV64360_CS_0_SIZE					    0x010
+#define MV64360_CS_1_BASE_ADDR					    0x208
+#define MV64360_CS_1_SIZE					    0x210
+#define MV64360_CS_2_BASE_ADDR					    0x018
+#define MV64360_CS_2_SIZE					    0x020
+#define MV64360_CS_3_BASE_ADDR					    0x218
+#define MV64360_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64360_PCI_0_IO_SIZE					    0x050
+#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64360_PCI_1_IO_SIZE					    0x098
+#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64360_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64360_CPU_CONFIG					    0x000
+#define MV64360_CPU_MODE					    0x120
+#define MV64360_CPU_MASTER_CONTROL				    0x160
+#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64360_SMP_WHO_AM_I					    0x200
+#define MV64360_SMP_CPU0_DOORBELL				    0x214
+#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64360_SMP_CPU1_DOORBELL				    0x224
+#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64360_SMP_SEMAPHOR0					    0x244
+#define MV64360_SMP_SEMAPHOR1					    0x24c
+#define MV64360_SMP_SEMAPHOR2					    0x254
+#define MV64360_SMP_SEMAPHOR3					    0x25c
+#define MV64360_SMP_SEMAPHOR4					    0x264
+#define MV64360_SMP_SEMAPHOR5					    0x26c
+#define MV64360_SMP_SEMAPHOR6					    0x274
+#define MV64360_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64360_CPU_ERROR_DATA_LOW				    0x128
+#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64360_CPU_ERROR_PARITY				    0x138
+#define MV64360_CPU_ERROR_CAUSE					    0x140
+#define MV64360_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64360_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64360_SRAM_CONFIG					    0x380
+#define MV64360_SRAM_TEST_MODE					    0X3F4
+#define MV64360_SRAM_ERROR_CAUSE				    0x388
+#define MV64360_SRAM_ERROR_ADDR					    0x390
+#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64360_SDRAM_CONFIG					    0x1400
+#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64360_SDRAM_OPERATION					    0x1418
+#define MV64360_SDRAM_MODE					    0x141c
+#define MV64360_EXTENDED_DRAM_MODE				    0x1420
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64360_SDRAM_ERROR_ADDR				    0x1450
+#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64360_SDRAM_ECC_CONTROL				    0x1454
+#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64360_DFCDL_CONFIG0					    0x1480
+#define MV64360_DFCDL_CONFIG1					    0x1484
+#define MV64360_DLL_WRITE					    0x1488
+#define MV64360_DLL_READ					    0x148c
+#define MV64360_SRAM_ADDR					    0x1490
+#define MV64360_SRAM_DATA0					    0x1494
+#define MV64360_SRAM_DATA1					    0x1498
+#define MV64360_SRAM_DATA2					    0x149c
+#define MV64360_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64360_DUNIT_DEBUG_LOW					    0x1460
+#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64360_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64360_DEVICE_ERROR_DATA				    0x4dc
+#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64360_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64360_PCI_0_COMMAND					    0xc00
+#define MV64360_PCI_1_COMMAND					    0xc80
+#define MV64360_PCI_0_MODE					    0xd00
+#define MV64360_PCI_1_MODE					    0xd80
+#define MV64360_PCI_0_RETRY					    0xc04
+#define MV64360_PCI_1_RETRY					    0xc84
+#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_SERR_MASK					    0xc28
+#define MV64360_PCI_1_SERR_MASK					    0xca8
+#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_MMASK					    0X1D24
+#define MV64360_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64360_PCI_VPD_ADDR					    0x048
+#define MV64360_PCI_VPD_DATA					    0x04c
+#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64360_PCI_X_COMMAND					    0x060
+#define MV64360_PCI_X_STATUS					    0x064
+#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64360_ETH_PHY_ADDR_REG				    0x2000
+#define MV64360_ETH_SMI_REG					    0x2004
+#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64360_ETH_BAR_0					    0x2200
+#define MV64360_ETH_BAR_1					    0x2208
+#define MV64360_ETH_BAR_2					    0x2210
+#define MV64360_ETH_BAR_3					    0x2218
+#define MV64360_ETH_BAR_4					    0x2220
+#define MV64360_ETH_BAR_5					    0x2228
+#define MV64360_ETH_SIZE_REG_0					    0x2204
+#define MV64360_ETH_SIZE_REG_1					    0x220c
+#define MV64360_ETH_SIZE_REG_2					    0x2214
+#define MV64360_ETH_SIZE_REG_3					    0x221c
+#define MV64360_ETH_SIZE_REG_4					    0x2224
+#define MV64360_ETH_SIZE_REG_5					    0x222c
+#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64360_CUNIT_SIZE0					    0xf204
+#define MV64360_CUNIT_SIZE1					    0xf20c
+#define MV64360_CUNIT_SIZE2					    0xf214
+#define MV64360_CUNIT_SIZE3					    0xf21c
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64360_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64360_CUNIT_CONFIG_REG				    0xb40c
+#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64360_CUNIT_DEBUG_LOW					    0xf340
+#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64360_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64360_MPSC_ROUTING_REG				    0xb400
+#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64360_SDMA_CAUSE_REG					    0xb800
+#define MV64360_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64360_SDMA_SRAM_TARGET				    0x0003
+#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64360_PCI_0_TARGET					    0x0003
+#define MV64360_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64360_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64360_BRG_CAUSE_REG					    0xb834
+#define MV64360_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64360_DMA_SIZE_REG0					    0xa04
+#define MV64360_DMA_SIZE_REG1					    0xa0c
+#define MV64360_DMA_SIZE_REG2					    0xa14
+#define MV64360_DMA_SIZE_REG3					    0xa1c
+#define MV64360_DMA_SIZE_REG4					    0xa24
+#define MV64360_DMA_SIZE_REG5					    0xa2c
+#define MV64360_DMA_SIZE_REG6					    0xa34
+#define MV64360_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64360_DMA_ARBITER_CONTROL				    0x860
+#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64360_DMA_ERROR_ADDR					    0x8c8
+#define MV64360_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64360_DMA_DEBUG_LOW					    0x8e0
+#define MV64360_DMA_DEBUG_HIGH					    0x8e4
+#define MV64360_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64360_TIMER_COUNTER0					    0x850
+#define MV64360_TIMER_COUNTER1					    0x854
+#define MV64360_TIMER_COUNTER2					    0x858
+#define MV64360_TIMER_COUNTER3					    0x85C
+#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64360_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64360_I2C_SLAVE_ADDR					    0xc000
+#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64360_I2C_DATA					    0xc004
+#define MV64360_I2C_CONTROL					    0xc008
+#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64360_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_GPP_IO_CONTROL					    0xf100
+#define MV64360_GPP_LEVEL_CONTROL				    0xf110
+#define MV64360_GPP_VALUE					    0xf104
+#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64360_GPP_VALUE_SET					    0xf118
+#define MV64360_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_MPP_CONTROL0					    0xf000
+#define MV64360_MPP_CONTROL1					    0xf004
+#define MV64360_MPP_CONTROL2					    0xf008
+#define MV64360_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64360_SERIAL_INIT_CONTROL				    0xf328
+#define MV64360_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64360rh */
diff --git a/u-boot/board/Marvell/db64360/pci.c b/u-boot/board/Marvell/db64360/pci.c
new file mode 100644
index 0000000..4998095
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/pci.c
@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#include <pci.h>
+
+#include "../include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
diff --git a/u-boot/board/Marvell/db64360/sdram_init.c b/u-boot/board/Marvell/db64360/sdram_init.c
new file mode 100644
index 0000000..d52d3f0
--- /dev/null
+++ b/u-boot/board/Marvell/db64360/sdram_init.c
@@ -0,0 +1,1984 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64360 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ ************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../common/i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+#define MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit (void);	/* setup delay line of Mv64360 */
+int mvDmaIsChannelActive (int);
+int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
+int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB	   (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
+
+typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+	SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+} VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
+		4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
+		32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD { SD_CL_1 =
+		1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
+		SD_FAULT } MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;	/* ECC , PARITY.. */
+	unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;	/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;	/* measured in ns */
+
+	int addrAndCommandHoldTime;	/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;	/* (measured in ns/100) */
+	int dataInputSetupTime; /* LoP left of point (measured in ns) */
+	int dataInputHoldTime;	/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+	unsigned int clockToDataOut_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;	/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;		/* DRAM size in n*64Mbit */
+	uchar slot;		/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];	/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+	uchar manufactura[8];	/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];	/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];	/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;	/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;	/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;	/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;	/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	unsigned long spd_checksum;
+
+#ifdef ZUMA_NTL
+	/* zero all the values */
+	memset (info, 0, sizeof (*info));
+
+/*
+	if (!slot) {
+	    info->slot = 0;
+	    info->banks = 1;
+	    info->registered = 0;
+		    info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
+/*	    info->tpar = 3;
+	    info->tras_clocks = 5;
+	    info->burst_len = 4;
+*/
+#ifdef CONFIG_MV64360_ECC
+	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+	dimmInfo->errorCheckType = 2;
+/*	    info->ecc = 2;*/
+#endif
+}
+
+return 0;
+
+#else
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 1, data, 128);
+
+	DP (puts ("after i2c read\n"));
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+/* find Manufactura of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by:		%s\n",
+		dimmInfo->manufactura);
+
+/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is:		%s\n",
+		dimmInfo->modul_id);
+
+/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is:		%s\n",
+		dimmInfo->vendor_data);
+
+/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is:			%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is:		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	spd_checksum = 0;
+
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2: /* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				DP (printf
+				    ("Dram_type in slot %d is:			SDRAM\n",
+				     dimmInfo->slot));
+			if (dimmInfo->memoryType == 1)
+				DP (printf
+				    ("Dram_type in slot %d is:			DDRAM\n",
+				     dimmInfo->slot));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3: /* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			DP (printf
+			    ("Module Number of row addresses:		%d\n",
+			     dimmInfo->numOfRowAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4: /* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			DP (printf
+			    ("Module Number of col addresses:		%d\n",
+			     dimmInfo->numOfColAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5: /* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			DP (printf
+			    ("Number of Banks on Mod. :					%d\n",
+			     dimmInfo->numOfModuleBanks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6: /* Data Width */
+			dimmInfo->dataWidth = data[i];
+			DP (printf
+			    ("Module Data Width:				%d\n",
+			     dimmInfo->dataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8: /* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				DP (printf
+				    ("Module is						TTL_5V_TOLERANT\n"));
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				DP (printf
+				    ("Module is						LVTTL\n"));
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				DP (printf
+				    ("Module is						TTL_5V_TOLERANT\n"));
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				DP (printf
+				    ("Module is						HSTL_1_5V\n"));
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				DP (printf
+				    ("Module is						SSTL_2_5V\n"));
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				DP (printf
+				    ("Module is						VOLTAGE_UNKNOWN\n"));
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9: /* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			DP (printf ("Clock To Data Out:					%d.%2d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+/*#ifdef CONFIG_ECC */
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			DP (printf
+			    ("Error Check Type (0=NONE):			%d\n",
+			     dimmInfo->errorCheckType));
+			break;
+/* #endif */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			DP (printf
+			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			DP (printf
+			    ("Sdram Width:					%d\n",
+			     dimmInfo->sdramWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			DP (printf
+			    ("Error Check Data Width:			%d\n",
+			     dimmInfo->errorCheckDataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			DP (printf
+			    ("Minimum Clock Delay:				%d\n",
+			     dimmInfo->minClkDelay));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8	  |  4	 |   2	|   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Burst Length Supported:			"));
+			if (dimmInfo->burstLengthSupported & 0x01)
+				DP (printf ("1, "));
+			if (dimmInfo->burstLengthSupported & 0x02)
+				DP (printf ("2, "));
+			if (dimmInfo->burstLengthSupported & 0x04)
+				DP (printf ("4, "));
+			if (dimmInfo->burstLengthSupported & 0x08)
+				DP (printf ("8, "));
+			DP (printf (" Bit \n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			DP (printf
+			    ("Number Of Banks On Each Chip:			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	| TBD  | 3.5  |	  3  | 2.5  |  2   | 1.5  |   1	 *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	|  7   |  6   |	 5   |	4   |  3   |   2  |   1	 *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Suported Cas Latencies: (CL)			"));
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						DP (printf
+						    ("%d,			",
+						     k + 1));
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					DP (printf ("1, "));
+				if (dimmInfo->suportedCasLatencies & 2)
+					DP (printf ("1.5, "));
+				if (dimmInfo->suportedCasLatencies & 4)
+					DP (printf ("2, "));
+				if (dimmInfo->suportedCasLatencies & 8)
+					DP (printf ("2.5, "));
+				if (dimmInfo->suportedCasLatencies & 16)
+					DP (printf ("3, "));
+				if (dimmInfo->suportedCasLatencies & 32)
+					DP (printf ("3.5, "));
+
+			}
+			DP (printf ("\n"));
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				3.5 clk's\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				3 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				2.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				2 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				1.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+
+						/* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
+						   lower then our SDRAM cycle count, we won't be able to support this CAL
+						   and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     <
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 <
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								dimmInfo->
+								maxClSupported_DDR
+								>> 1;
+							DP (printf
+							    ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
+						}
+						/* ronen - checkif the Dimm frequency compared to the Sysclock. */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     >
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 >
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							printf ("*********************************************************\n");
+							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
+							printf ("*********************************************************\n");
+							hang ();
+						}
+
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
+						DP (printf
+						    ("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD));
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+#ifdef DEBUG
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Buffered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Buffered Address/Control Input:		No \n"));
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Registered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Registered Address/Control Input:		No \n"));
+
+			if (dimmInfo->onCardPLL == 1)
+				DP (printf
+				    (" - On-Card PLL (clock):				Yes \n"));
+			else
+				DP (printf
+				    (" - On-Card PLL (clock):				No \n"));
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				Yes \n"));
+			else
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				No \n"));
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				DP (printf
+				    (" - Registered DQMB Inputs:			Yes \n"));
+			else
+				DP (printf
+				    (" - Registered DQMB Inputs:			No \n"));
+
+			if (dimmInfo->differentialClockInput == 1)
+				DP (printf
+				    (" - Differential Clock Input:			Yes \n"));
+			else
+				DP (printf
+				    (" - Differential Clock Input:			No \n"));
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				DP (printf
+				    (" - redundant Row Addressing:			Yes \n"));
+			else
+				DP (printf
+				    (" - redundant Row Addressing:			No \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+#ifdef DEBUG
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				DP (printf
+				    (" - Early Ras Precharge:			Yes \n"));
+			else
+				DP (printf
+				    (" -  Early Ras Precharge:			No \n"));
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				DP (printf
+				    (" - AutoPreCharge:				Yes \n"));
+			else
+				DP (printf
+				    (" -  AutoPreCharge:				No \n"));
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				DP (printf
+				    (" - Precharge All:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Precharge All:				No \n"));
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				DP (printf
+				    (" - Write 1/ReadBurst:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Write 1/ReadBurst:				No \n"));
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				DP (printf
+				    (" - lower VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    ("	- lower VCC tolerance:			10 Percent \n"));
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				DP (printf
+				    (" - upper VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    (" -  upper VCC tolerance:			10 Percent \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (2nd CL value):			%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (3rd CL value):			%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100));
+			DP (printf
+			    ("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trrd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trcd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks));
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			DP (printf
+			    ("Module Bank Density:				%d\n",
+			     dimmInfo->moduleBankDensity));
+#ifdef DEBUG
+			DP (printf
+			    ("*** Offered Densities (more than 1 = Multisize-Module): "));
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					DP (printf ("4MB, "));
+				if (dimmInfo->moduleBankDensity & 2)
+					DP (printf ("8MB, "));
+				if (dimmInfo->moduleBankDensity & 4)
+					DP (printf ("16MB, "));
+				if (dimmInfo->moduleBankDensity & 8)
+					DP (printf ("32MB, "));
+				if (dimmInfo->moduleBankDensity & 16)
+					DP (printf ("64MB, "));
+				if (dimmInfo->moduleBankDensity & 32)
+					DP (printf ("128MB, "));
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					DP (printf ("ERROR, "));
+					hang ();
+				}
+			}
+			DP (printf ("\n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Setup Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Hold Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Setup Time [ns]:			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Hold Time [ns]:			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices -
+			 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
+			 dimmInfo->numberOfDevices / 8);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
+	dimmInfo->drb_size = (uchar) tmp;
+	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 3) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 3;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 2;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		hang ();
+		return 0;
+	}
+
+	return true;
+
+#endif
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp, check;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	int i;
+
+	/* added 8/21/2003 P. Marchese */
+	unsigned int sdram_config_reg;
+
+	/* added 10/10/2003 P. Marchese */
+	ulong sdram_chip_size;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	DP (printf ("Delay line set done\n"));
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM configuration */
+/* added 8/21/2003 P. Marchese */
+/* code allows usage of registered DIMMS */
+
+	/* figure out the memory refresh internal */
+	switch (info->RefreshInterval) {
+	case 0x0:
+	case 0x80:		/* refresh period is 15.625 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
+					/ (float) 1000000.0);
+		break;
+	case 0x1:
+	case 0x81:		/* refresh period is 3.9 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x2:
+	case 0x82:		/* refresh period is 7.8 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x3:
+	case 0x83:		/* refresh period is 31.3 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x4:
+	case 0x84:		/* refresh period is 62.5 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x5:
+	case 0x85:		/* refresh period is 125 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	default:		/* refresh period undefined */
+		printf ("DRAM refresh period is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+	DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
+
+	/* make sure the refresh value is only 14 bits */
+	if (sdram_config_reg > 0x1fff)
+		sdram_config_reg = 0x1fff;
+	DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
+
+	/* we want physical bank interleaving and */
+	/* virtual bank interleaving enabled so do nothing */
+	/* since these bits need to be zero to enable the interleaving */
+
+	/*  registered DRAM ? */
+	if (info->registeredAddrAndControlInputs == 1) {
+		/* it's registered DRAM, so set the reg. DRAM bit */
+		sdram_config_reg = sdram_config_reg | BIT17;
+		DP (printf ("Enabling registered DRAM bit\n"));
+	}
+	/* turn on DRAM ECC? */
+#ifdef CONFIG_MV64360_ECC
+	if (info->errorCheckType == 0x2) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg = sdram_config_reg | BIT18;
+		DP (printf ("Enabling ECC\n"));
+	}
+#endif
+	/* set the data DQS pin configuration */
+	switch (info->sdramWidth) {
+	case 0x4:		/* memory is x4 */
+		sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
+		DP (printf ("Data DQS pins set for 16 pins\n"));
+		break;
+	case 0x8:		/* memory is x8 or x16 */
+	case 0x10:
+		sdram_config_reg = sdram_config_reg | BIT21;
+		DP (printf ("Data DQS pins set for 8 pins\n"));
+		break;
+	case 0x20:		/* memory is x32 */
+		/* both bits are cleared for x32 so nothing to do */
+		DP (printf ("Data DQS pins set for 2 pins\n"));
+		break;
+	default:		/* memory width unsupported */
+		printf ("DRAM chip width is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+
+	/* perform read buffer assignments */
+	/* we are going to use the Power-up defaults */
+	/* bit 26 = CPU = buffer 1 */
+	/* bit 27 = PCI bus #0 = buffer 0 */
+	/* bit 28 = PCI bus #1 = buffer 0 */
+	/* bit 29 = MPSC = buffer 0 */
+	/* bit 30 = IDMA = buffer 0 */
+	/* bit 31 = Gigabit = buffer 0 */
+	sdram_config_reg = sdram_config_reg | BIT26;
+	/*  sdram_config_reg = sdram_config_reg | 0x58000000; */
+	/* sdram_config_reg = sdram_config_reg & 0xffffff00;  */
+
+	/* write the value into the SDRAM configuration register */
+	GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
+	DP (printf
+	    ("OOOOOOOOO sdram_conf 0x1400: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM open pages control keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	DP (printf
+	    ("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+	else
+		DP (printf
+		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+
+	/* SDRAM set CAS Latency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		printf ("### SD-RAM not supported !!!\n");
+		printf ("Aborting!!!\n");
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+		/* Calculate the settings for SDRAM mode and Dunit control low registers */
+		/* Values set according to technical bulletin TB-92 rev. c */
+	case DDR:
+		DP (printf ("### SET-CL for DDR-RAM\n"));
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x05110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x2C1107F2;
+				else
+					tmp_dunit_control_low = 0x3C1107d2;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2_5:
+			tmp_sdram_mode = 0x62;	/* CL=2.5 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x25110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
+					printf ("Aborting!!!\n");
+					hang ();
+				} else
+					tmp_dunit_control_low = 0x1B1107d2;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2:
+			tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x04110051;
+				else
+					tmp_dunit_control_low = 0x03110051;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
+					printf ("Aborting!!!\n");
+					hang ();
+				} else
+					tmp_dunit_control_low = 0x3B1107d2;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_1_5:
+			tmp_sdram_mode = 0x52;	/* CL=1.5 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x24110051;
+				else
+					tmp_dunit_control_low = 0x23110051;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
+					printf ("Aborting!!!\n");
+					hang ();
+				} else
+					tmp_dunit_control_low = 0x1A1107d2;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}		/* end DDR switch */
+		break;
+	}			/* end CL switch */
+
+	/* Write results of CL detection procedure */
+	/* set SDRAM mode reg. 0x141c */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+	}
+
+/*------------------------------------------------------------------------------ */
+
+	/* bank parameters */
+	/* SDRAM address decode register 0x1410 */
+	/* program this with the default value */
+	tmp = 0x02;		/* power-up default address select decoding value */
+
+	DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+/* figure out the DRAM chip size */
+	sdram_chip_size =
+		(1 << (info->numOfRowAddresses + info->numOfColAddresses));
+	sdram_chip_size *= info->sdramWidth;
+	sdram_chip_size *= 4;
+	DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
+	/* divide sdram chip size by 64 Mbits */
+	sdram_chip_size = sdram_chip_size / 0x4000000;
+	switch (sdram_chip_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		printf ("RAM-Device_size is unsupported\n");
+		hang ();
+	}
+
+	/* SDRAM address control */
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+	DP (printf
+	    ("setting up sdram address control (0x1410) with: %08lx \n",
+	     tmp));
+
+/* ------------------------------------------------------------------------------ */
+/* same settings for registerd & non-registerd DDR SDRAM */
+	DP (printf
+	    ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
+	     0x11511220));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		DP (printf
+		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs));
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV64360 */
+	tmp |= (1 << 26);
+	DP (printf
+	    ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+	DP (printf
+	    ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM timing To_do: */
+/* ------------------------------------------------------------------------------ */
+
+	DP (printf
+	    ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
+	     0x9));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
+
+	DP (printf
+	    ("setting up sdram address pads control (0x14c0) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
+
+	DP (printf
+	  indent: Standard input:1450: Warning:old style assignment ambiguity in "=*".	Assuming "= *"
+
+indent: Standard input:1451: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+  ("setting up sdram data pads control (0x14c4) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
+
+/* ------------------------------------------------------------------------------ */
+
+	/* set the SDRAM configuration for each bank */
+
+/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		i = info->slot;
+		DP (printf
+		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+
+		/* set SDRAM mode */ /* To_do check it */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			DP (printf
+			    ("Found %08x  at Address %08x (failure)\n",
+			     (unsigned int) val, (unsigned int) addr));
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+phys_size_t initdram (int board_type)
+{
+	int s0 = 0, s1 = 0;
+	int checkbank[4] = {[0 ... 3] = 0 };
+	ulong realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int nhr, bank_no;
+	ulong dest, memSpaceAttr;
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0 () & (1 << 16);
+
+	if (nhr) {
+		printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		s0 = check_dimm (0, &dimmInfo1);
+
+		/* DIMM1 */
+		s1 = check_dimm (1, &dimmInfo2);
+
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
+
+		/* ronen check correct set of DIMMS */
+		if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
+			if (dimmInfo1.errorCheckType !=
+			    dimmInfo2.errorCheckType)
+				printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
+			if (dimmInfo1.maxClSupported_DDR !=
+			    dimmInfo2.maxClSupported_DDR)
+				printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
+			if (dimmInfo1.registeredAddrAndControlInputs !=
+			    dimmInfo2.registeredAddrAndControlInputs)
+				printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
+		}
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
+			printf ("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
+			printf ("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0 (get_hid0 () | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB / 4;
+	if (dimmInfo1.numOfModuleBanks > 0) {
+		checkbank[0] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 1) {
+		checkbank[1] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+	printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
+
+	if (dimmInfo2.numOfModuleBanks > 0) {
+		checkbank[2] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 1) {
+		checkbank[3] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
+
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (!checkbank[bank_no])
+			continue;
+
+		/* ronen - realsize = dram_size((long int *)total, check); */
+		if (bank_no == 0 || bank_no == 1) {
+			if (checkbank[1] == 1)
+				realsize = dimmInfo1.size / 2;
+			else
+				realsize = dimmInfo1.size;
+		}
+		if (bank_no == 2 || bank_no == 3) {
+			if (checkbank[3] == 1)
+				realsize = dimmInfo2.size / 2;
+			else
+				realsize = dimmInfo2.size;
+		}
+		memory_map_bank (bank_no, total, realsize);
+
+		/* ronen - initialize the DRAM for ECC */
+#ifdef CONFIG_MV64360_ECC
+		if ((dimmInfo1.errorCheckType != 0) &&
+		    ((dimmInfo2.errorCheckType != 0)
+		     || (dimmInfo2.numOfModuleBanks == 0))) {
+			printf ("ECC Initialization of Bank %d:", bank_no);
+			memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
+					     realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mvDmaTransfer (0, total, dest, _8M,
+					       BIT8 /*DMA_DTL_128BYTES */  |
+					       BIT3 /*DMA_HOLD_SOURCE_ADDR */
+					       |
+					       BIT11
+					       /*DMA_BLOCK_TRANSFER_MODE */ );
+				while (mvDmaIsChannelActive (0));
+			}
+			printf (" PASS\n");
+		}
+#endif
+
+		total += realsize;
+	}
+
+	/* ronen- add DRAM conf prints */
+	switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
+	case 0x2:
+		printf ("CAS Latency = 2");
+		break;
+	case 0x3:
+		printf ("CAS Latency = 3");
+		break;
+	case 0x5:
+		printf ("CAS Latency = 1.5");
+		break;
+	case 0x6:
+		printf ("CAS Latency = 2.5");
+		break;
+	}
+	printf (" tRP = %d tRAS = %d tRCD=%d\n",
+		((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	if (total > _256M)
+		printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
+	else
+		printf ("Total SDRAM memory is ");
+	/* (cause all the 4 BATS are taken) */
+	return (total);
+}
+
+
+/* ronen- add Idma functions for usage of the ecc dram init. */
+/*******************************************************************************
+* mvDmaIsChannelActive - Checks if a engine is busy.
+********************************************************************************/
+int mvDmaIsChannelActive (int engine)
+{
+	ulong data;
+
+	data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14 /*activity status */ ) {
+		return 1;
+	}
+	return 0;
+}
+
+/*******************************************************************************
+* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
+*			map.
+*******************************************************************************/
+int mvDmaSetMemorySpace (ulong memSpace,
+			 ulong memSpaceTarget,
+			 ulong memSpaceAttr, ulong baseAddress, ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return 0;
+	}
+	if (size >= 0x10000 /*64K */ ) {
+		size &= 0xffff0000;
+		baseAddress = (baseAddress & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
+			      (temp & ~(BIT0 << memSpace)));
+		return 1;
+	}
+	return 0;
+}
+
+
+/*******************************************************************************
+* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
+*		  DMA channels.
+********************************************************************************/
+int mvDmaTransfer (int engine, ulong sourceAddr,
+		   ulong destAddr, ulong numOfBytes, ulong command)
+{
+	ulong engOffReg = 0;	/* Engine Offset Register */
+
+	if (numOfBytes > 0xffff) {
+		command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
+	}
+	command = command | ((command >> 6) & 0x7);
+	engOffReg = engine * 4;
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
+		      numOfBytes);
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
+		      sourceAddr);
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
+		      destAddr);
+	command =
+		command | BIT12 /*DMA_CHANNEL_ENABLE */	 | BIT9
+		/*DMA_NON_CHAIN_MODE */ ;
+	/* Activate DMA engine By writting to mvDmaControlRegister */
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command);
+	return 1;
+}
+
+/****************************************************************************************
+ *				SDRAM INIT						*
+ *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+ *		  This procedure fits only the Atlantis					*
+ *											*
+ ***************************************************************************************/
+
+
+/****************************************************************************************
+ *				DFCDL initialize MV643xx Design Considerations		*
+ *											*
+ ***************************************************************************************/
+int set_dfcdlInit (void)
+{
+	int i;
+	unsigned int dfcdl_word = 0x391;	/*   0x14f;  ronen new dfcdl */
+
+	for (i = 0; i < 64; i++) {
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
+/*	dfcdl_word += 0x41;  - ronen new dfcdl */
+	}
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+	return (0);
+}
diff --git a/u-boot/board/Marvell/db64460/64460.h b/u-boot/board/Marvell/db64460/64460.h
new file mode 100644
index 0000000..8bb0ebf
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/64460.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64460.
+ */
+
+#ifndef __64460_H__
+#define __64460_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64460_H__ */
diff --git a/u-boot/board/Marvell/db64460/Makefile b/u-boot/board/Marvell/db64460/Makefile
new file mode 100644
index 0000000..036d255
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	= ../common/misc.o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
+	  sdram_init.o ../common/intel_flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/db64460/db64460.c b/u-boot/board/Marvell/db64460/db64460.c
new file mode 100644
index 0000000..14e6355
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/db64460.c
@@ -0,0 +1,937 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
+ */
+
+/*
+ * db64460.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+#include <netdev.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CONFIG_SYS_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64460 P.399 */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6446x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6446x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
+		sram_boot = 1;
+	if (!sram_boot)
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
+
+
+	/* configure device timing */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
+	if (!sram_boot)
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+#endif
+
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+#endif
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+#endif
+
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CONFIG_SYS_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CONFIG_SYS_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
+	}
+	display_mem_map ();
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+	volatile int *addr = 0;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x08000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x0c000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x14000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x18000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
+					0x1c000);
+			break;
+		}
+	}
+
+	dummy = *addr;
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- EXT SRAM (actual - 1M)\n");
+		else if (i == 1)
+			printf ("\t- RTC\n");
+		else if (i == 2)
+			printf ("\t- UART\n");
+		else
+			printf ("\t- LARGE FLASH\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CONFIG_SYS_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
+
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
+
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+/*    rundata = 1; */
+/*    runaddress = 0; */
+/*    runwalk = 0; */
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+	}
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
+
+/* Relocate MV64460 internal regs */
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+
+	icache_disable ();
+	dcache_disable ();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/Marvell/db64460/eth.h b/u-boot/board/Marvell/db64460/eth.h
new file mode 100644
index 0000000..6c3b2e0
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/eth.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64460_ETH_H__
+#define __EVB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+int db64460_eth0_poll(void);
+int db64460_eth0_transmit(unsigned int s, volatile char *p);
+void db64460_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+#endif /* __EVB64460_ETH_H__ */
diff --git a/u-boot/board/Marvell/db64460/mpsc.c b/u-boot/board/Marvell/db64460/mpsc.c
new file mode 100644
index 0000000..303a636
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/mpsc.c
@@ -0,0 +1,1017 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../include/memory.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64460 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/u-boot/board/Marvell/db64460/mpsc.h b/u-boot/board/Marvell/db64460/mpsc.h
new file mode 100644
index 0000000..b8462cb
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/u-boot/board/Marvell/db64460/mv_eth.c b/u-boot/board/Marvell/db64460/mv_eth.c
new file mode 100644
index 0000000..cd9d5a4
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/mv_eth.c
@@ -0,0 +1,3183 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64460_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64460_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64460_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64460_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64460 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64460_eth_real_open (struct eth_device *eth);
+static int mv64460_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64460_eth_update_stat (struct eth_device *dev);
+bool db64460_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64460_eth_receive (struct eth_device *dev);
+
+int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64460_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64460_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64460_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64460_eth
+ *
+ **********************************************************************/
+int db64460_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64460_eth_start (dev));
+}
+
+int db64460_eth_poll (struct eth_device *dev)
+{
+	return mv64460_eth_receive (dev);
+}
+
+int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64460_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64460_eth_disable (struct eth_device *dev)
+{
+	mv64460_eth_stop (dev);
+}
+
+
+void mv6446x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64460_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64460_eth_transmit;
+		dev->recv = (void *) db64460_eth_poll;
+
+		ethernet_private = calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *)ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private = calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64460_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64460_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64460_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64460_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64460_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64460_eth_open (struct eth_device *dev)
+{
+	return (mv64460_eth_real_open (dev));
+}
+
+/* Helper function for mv64460_eth_open */
+static int mv64460_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status, phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64460_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64460_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64460_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64460_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64460_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64460_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64460_eth_stop */
+
+static int mv64460_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64460_eth_free_tx_rings (dev);
+	mv64460_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64460_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64460_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64460_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64460_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64460_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64460_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64460_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64460_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64460_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64460_eth_start (struct eth_device *dev)
+{
+	return (mv64460_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64460_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ *	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/u-boot/board/Marvell/db64460/mv_eth.h b/u-boot/board/Marvell/db64460/mv_eth.h
new file mode 100644
index 0000000..cbe751a
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/mv_eth.h
@@ -0,0 +1,840 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64460_ETH_H__
+#define __DB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include <asm/errno.h>
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64460_TX_QUEUE_NUM 1
+#define MV64460_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#else
+#define MV64460_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#else
+#define MV64460_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64460_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64460_TX_BUFFER_SIZE 1600
+#endif
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64460_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+int mv64460_eth_init (struct eth_device *dev);
+int mv64460_eth_stop (struct eth_device *dev);
+int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64460_eth0_poll(); */
+
+int mv64460_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64460_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64460_ETH_ */
diff --git a/u-boot/board/Marvell/db64460/mv_regs.h b/u-boot/board/Marvell/db64460/mv_regs.h
new file mode 100644
index 0000000..fb50bb6
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/mv_regs.h
@@ -0,0 +1,1124 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64460r.h - GT-64460 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64460
+
+/* Supported by the Atlantis */
+#define MV64460_INCLUDE_PCI_1
+#define MV64460_INCLUDE_PCI_0_ARBITER
+#define MV64460_INCLUDE_PCI_1_ARBITER
+#define MV64460_INCLUDE_SNOOP_SUPPORT
+#define MV64460_INCLUDE_P2P
+#define MV64460_INCLUDE_ETH_PORT_2
+#define MV64460_INCLUDE_CPU_MAPPING
+#define MV64460_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64460_CS_0_BASE_ADDR					    0x008
+#define MV64460_CS_0_SIZE					    0x010
+#define MV64460_CS_1_BASE_ADDR					    0x208
+#define MV64460_CS_1_SIZE					    0x210
+#define MV64460_CS_2_BASE_ADDR					    0x018
+#define MV64460_CS_2_SIZE					    0x020
+#define MV64460_CS_3_BASE_ADDR					    0x218
+#define MV64460_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64460_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64460_PCI_0_IO_SIZE					    0x050
+#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64460_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64460_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64460_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64460_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64460_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64460_PCI_1_IO_SIZE					    0x098
+#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64460_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64460_CPU_CONFIG					    0x000
+#define MV64460_CPU_MODE					    0x120
+#define MV64460_CPU_MASTER_CONTROL				    0x160
+#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64460_SMP_WHO_AM_I					    0x200
+#define MV64460_SMP_CPU0_DOORBELL				    0x214
+#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64460_SMP_CPU1_DOORBELL				    0x224
+#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64460_SMP_SEMAPHOR0					    0x244
+#define MV64460_SMP_SEMAPHOR1					    0x24c
+#define MV64460_SMP_SEMAPHOR2					    0x254
+#define MV64460_SMP_SEMAPHOR3					    0x25c
+#define MV64460_SMP_SEMAPHOR4					    0x264
+#define MV64460_SMP_SEMAPHOR5					    0x26c
+#define MV64460_SMP_SEMAPHOR6					    0x274
+#define MV64460_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64460_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64460_CPU_ERROR_DATA_LOW				    0x128
+#define MV64460_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64460_CPU_ERROR_PARITY				    0x138
+#define MV64460_CPU_ERROR_CAUSE					    0x140
+#define MV64460_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64460_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64460_SRAM_CONFIG					    0x380
+#define MV64460_SRAM_TEST_MODE					    0X3F4
+#define MV64460_SRAM_ERROR_CAUSE				    0x388
+#define MV64460_SRAM_ERROR_ADDR					    0x390
+#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64460_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64460_SDRAM_CONFIG					    0x1400
+#define MV64460_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64460_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64460_SDRAM_OPERATION					    0x1418
+#define MV64460_SDRAM_MODE					    0x141c
+#define MV64460_EXTENDED_DRAM_MODE				    0x1420
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64460_SDRAM_ERROR_ADDR				    0x1450
+#define MV64460_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64460_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64460_SDRAM_ECC_CONTROL				    0x1454
+#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64460_DFCDL_CONFIG0					    0x1480
+#define MV64460_DFCDL_CONFIG1					    0x1484
+#define MV64460_DLL_WRITE					    0x1488
+#define MV64460_DLL_READ					    0x148c
+#define MV64460_SRAM_ADDR					    0x1490
+#define MV64460_SRAM_DATA0					    0x1494
+#define MV64460_SRAM_DATA1					    0x1498
+#define MV64460_SRAM_DATA2					    0x149c
+#define MV64460_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64460_DUNIT_DEBUG_LOW					    0x1460
+#define MV64460_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64460_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64460_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64460_DEVICE_ERROR_DATA				    0x4dc
+#define MV64460_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64460_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64460_PCI_0_COMMAND					    0xc00
+#define MV64460_PCI_1_COMMAND					    0xc80
+#define MV64460_PCI_0_MODE					    0xd00
+#define MV64460_PCI_1_MODE					    0xd80
+#define MV64460_PCI_0_RETRY					    0xc04
+#define MV64460_PCI_1_RETRY					    0xc84
+#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64460_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64460_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64460_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_SERR_MASK					    0xc28
+#define MV64460_PCI_1_SERR_MASK					    0xca8
+#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64460_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64460_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_MMASK					    0X1D24
+#define MV64460_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64460_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64460_PCI_VPD_ADDR					    0x048
+#define MV64460_PCI_VPD_DATA					    0x04c
+#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64460_PCI_X_COMMAND					    0x060
+#define MV64460_PCI_X_STATUS					    0x064
+#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64460_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64460_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64460_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64460_ETH_PHY_ADDR_REG				    0x2000
+#define MV64460_ETH_SMI_REG					    0x2004
+#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64460_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64460_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64460_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64460_ETH_BAR_0					    0x2200
+#define MV64460_ETH_BAR_1					    0x2208
+#define MV64460_ETH_BAR_2					    0x2210
+#define MV64460_ETH_BAR_3					    0x2218
+#define MV64460_ETH_BAR_4					    0x2220
+#define MV64460_ETH_BAR_5					    0x2228
+#define MV64460_ETH_SIZE_REG_0					    0x2204
+#define MV64460_ETH_SIZE_REG_1					    0x220c
+#define MV64460_ETH_SIZE_REG_2					    0x2214
+#define MV64460_ETH_SIZE_REG_3					    0x221c
+#define MV64460_ETH_SIZE_REG_4					    0x2224
+#define MV64460_ETH_SIZE_REG_5					    0x222c
+#define MV64460_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64460_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64460_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64460_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64460_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64460_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64460_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64460_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64460_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64460_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64460_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64460_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64460_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64460_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64460_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64460_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64460_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64460_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64460_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64460_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64460_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64460_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64460_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64460_CUNIT_SIZE0					    0xf204
+#define MV64460_CUNIT_SIZE1					    0xf20c
+#define MV64460_CUNIT_SIZE2					    0xf214
+#define MV64460_CUNIT_SIZE3					    0xf21c
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64460_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64460_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64460_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64460_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64460_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64460_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64460_CUNIT_CONFIG_REG				    0xb40c
+#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64460_CUNIT_DEBUG_LOW					    0xf340
+#define MV64460_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64460_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64460_MPSC_ROUTING_REG				    0xb400
+#define MV64460_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64460_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64460_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64460_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64460_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64460_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64460_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64460_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64460_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64460_SDMA_CAUSE_REG					    0xb800
+#define MV64460_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64460_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64460_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64460_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64460_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64460_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64460_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64460_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64460_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64460_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64460_SDMA_SRAM_TARGET				    0x0003
+#define MV64460_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64460_PCI_0_TARGET					    0x0003
+#define MV64460_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64460_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64460_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64460_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64460_BRG_CAUSE_REG					    0xb834
+#define MV64460_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64460_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64460_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64460_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64460_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64460_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64460_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64460_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64460_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64460_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64460_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64460_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64460_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64460_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64460_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64460_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64460_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64460_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64460_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64460_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64460_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64460_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64460_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64460_DMA_SIZE_REG0					    0xa04
+#define MV64460_DMA_SIZE_REG1					    0xa0c
+#define MV64460_DMA_SIZE_REG2					    0xa14
+#define MV64460_DMA_SIZE_REG3					    0xa1c
+#define MV64460_DMA_SIZE_REG4					    0xa24
+#define MV64460_DMA_SIZE_REG5					    0xa2c
+#define MV64460_DMA_SIZE_REG6					    0xa34
+#define MV64460_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64460_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64460_DMA_ARBITER_CONTROL				    0x860
+#define MV64460_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64460_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64460_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64460_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64460_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64460_DMA_ERROR_ADDR					    0x8c8
+#define MV64460_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64460_DMA_DEBUG_LOW					    0x8e0
+#define MV64460_DMA_DEBUG_HIGH					    0x8e4
+#define MV64460_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64460_TIMER_COUNTER0					    0x850
+#define MV64460_TIMER_COUNTER1					    0x854
+#define MV64460_TIMER_COUNTER2					    0x858
+#define MV64460_TIMER_COUNTER3					    0x85C
+#define MV64460_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64460_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64460_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64460_I2C_SLAVE_ADDR					    0xc000
+#define MV64460_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64460_I2C_DATA					    0xc004
+#define MV64460_I2C_CONTROL					    0xc008
+#define MV64460_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64460_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_GPP_IO_CONTROL					    0xf100
+#define MV64460_GPP_LEVEL_CONTROL				    0xf110
+#define MV64460_GPP_VALUE					    0xf104
+#define MV64460_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64460_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64460_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64460_GPP_VALUE_SET					    0xf118
+#define MV64460_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64460_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64460_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64460_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64460_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64460_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64460_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64460_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64460_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64460_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64460_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64460_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_MPP_CONTROL0					    0xf000
+#define MV64460_MPP_CONTROL1					    0xf004
+#define MV64460_MPP_CONTROL2					    0xf008
+#define MV64460_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64460_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64460_SERIAL_INIT_CONTROL				    0xf328
+#define MV64460_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64460rh */
diff --git a/u-boot/board/Marvell/db64460/pci.c b/u-boot/board/Marvell/db64460/pci.c
new file mode 100644
index 0000000..4998095
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/pci.c
@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#include <pci.h>
+
+#include "../include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
diff --git a/u-boot/board/Marvell/db64460/sdram_init.c b/u-boot/board/Marvell/db64460/sdram_init.c
new file mode 100644
index 0000000..e328d8f
--- /dev/null
+++ b/u-boot/board/Marvell/db64460/sdram_init.c
@@ -0,0 +1,1985 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64460 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+  ************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../common/i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit (void);	/* setup delay line of Mv64460 */
+int mvDmaIsChannelActive (int);
+int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
+int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB         (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
+
+typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+	SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+} VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
+		4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
+		32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD { SD_CL_1 =
+		1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
+		SD_FAULT } MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;	/* ECC , PARITY.. */
+	unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;	/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;	/* measured in ns */
+
+	int addrAndCommandHoldTime;	/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;	/* (measured in ns/100) */
+	int dataInputSetupTime;	/* LoP left of point (measured in ns) */
+	int dataInputHoldTime;	/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+	unsigned int clockToDataOut_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;	/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;		/* DRAM size in n*64Mbit */
+	uchar slot;		/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];	/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+	uchar manufactura[8];	/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];	/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];	/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;	/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;	/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;	/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;	/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	unsigned long spd_checksum;
+
+#ifdef ZUMA_NTL
+	/* zero all the values */
+	memset (info, 0, sizeof (*info));
+
+/*
+	if (!slot) {
+	    info->slot = 0;
+	    info->banks = 1;
+	    info->registered = 0;
+		    info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
+/*	    info->tpar = 3;
+	    info->tras_clocks = 5;
+	    info->burst_len = 4;
+*/
+#ifdef CONFIG_MV64460_ECC
+	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+	dimmInfo->errorCheckType = 2;
+/*	    info->ecc = 2;*/
+#endif
+}
+
+return 0;
+
+#else
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 1, data, 128);
+
+	DP (puts ("after i2c read\n"));
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+/* find Manufactura of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by: 		%s\n",
+		dimmInfo->manufactura);
+
+/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is: 		%s\n",
+		dimmInfo->modul_id);
+
+/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is: 		%s\n",
+		dimmInfo->vendor_data);
+
+/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is: 		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is: 	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is: 		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	spd_checksum = 0;
+
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2:	/* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				DP (printf
+				    ("Dram_type in slot %d is: 			SDRAM\n",
+				     dimmInfo->slot));
+			if (dimmInfo->memoryType == 1)
+				DP (printf
+				    ("Dram_type in slot %d is: 			DDRAM\n",
+				     dimmInfo->slot));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3:	/* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			DP (printf
+			    ("Module Number of row addresses: 		%d\n",
+			     dimmInfo->numOfRowAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4:	/* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			DP (printf
+			    ("Module Number of col addresses: 		%d\n",
+			     dimmInfo->numOfColAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5:	/* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			DP (printf
+			    ("Number of Banks on Mod. : 				%d\n",
+			     dimmInfo->numOfModuleBanks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6:	/* Data Width */
+			dimmInfo->dataWidth = data[i];
+			DP (printf
+			    ("Module Data Width: 				%d\n",
+			     dimmInfo->dataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8:	/* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				DP (printf
+				    ("Module is 					LVTTL\n"));
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				DP (printf
+				    ("Module is 					HSTL_1_5V\n"));
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				DP (printf
+				    ("Module is 					SSTL_2_5V\n"));
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				DP (printf
+				    ("Module is 					VOLTAGE_UNKNOWN\n"));
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9:	/* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At Max CasLatancy: 		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			DP (printf ("Clock To Data Out: 				%d.%2d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+/*#ifdef CONFIG_ECC */
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			DP (printf
+			    ("Error Check Type (0=NONE): 			%d\n",
+			     dimmInfo->errorCheckType));
+			break;
+/* #endif */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			DP (printf
+			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			DP (printf
+			    ("Sdram Width: 					%d\n",
+			     dimmInfo->sdramWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			DP (printf
+			    ("Error Check Data Width: 			%d\n",
+			     dimmInfo->errorCheckDataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			DP (printf
+			    ("Minimum Clock Delay: 				%d\n",
+			     dimmInfo->minClkDelay));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8   |  4   |   2  |   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Burst Length Supported: 			"));
+			if (dimmInfo->burstLengthSupported & 0x01)
+				DP (printf ("1, "));
+			if (dimmInfo->burstLengthSupported & 0x02)
+				DP (printf ("2, "));
+			if (dimmInfo->burstLengthSupported & 0x04)
+				DP (printf ("4, "));
+			if (dimmInfo->burstLengthSupported & 0x08)
+				DP (printf ("8, "));
+			DP (printf (" Bit \n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			DP (printf
+			    ("Number Of Banks On Each Chip: 			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Suported Cas Latencies: (CL) 			"));
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						DP (printf
+						    ("%d, 			",
+						     k + 1));
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					DP (printf ("1, "));
+				if (dimmInfo->suportedCasLatencies & 2)
+					DP (printf ("1.5, "));
+				if (dimmInfo->suportedCasLatencies & 4)
+					DP (printf ("2, "));
+				if (dimmInfo->suportedCasLatencies & 8)
+					DP (printf ("2.5, "));
+				if (dimmInfo->suportedCasLatencies & 16)
+					DP (printf ("3, "));
+				if (dimmInfo->suportedCasLatencies & 32)
+					DP (printf ("3.5, "));
+
+			}
+			DP (printf ("\n"));
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3.5 clk's\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			1.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+
+						/* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
+						   lower then our SDRAM cycle count, we won't be able to support this CAL
+						   and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     <
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 <
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								dimmInfo->
+								maxClSupported_DDR
+								>> 1;
+							DP (printf
+							    ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
+						}
+						/* ronen - checkif the Dimm frequency compared to the Sysclock. */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     >
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 >
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							printf ("*********************************************************\n");
+							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
+							printf ("*********************************************************\n");
+							hang ();
+						}
+
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): 	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded                   */
+						DP (printf
+						    ("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD));
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+#ifdef DEBUG
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Buffered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Buffered Address/Control Input:		No \n"));
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Registered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Registered Address/Control Input:		No \n"));
+
+			if (dimmInfo->onCardPLL == 1)
+				DP (printf
+				    (" - On-Card PLL (clock):				Yes \n"));
+			else
+				DP (printf
+				    (" - On-Card PLL (clock):				No \n"));
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				Yes \n"));
+			else
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				No \n"));
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				DP (printf
+				    (" - Registered DQMB Inputs:			Yes \n"));
+			else
+				DP (printf
+				    (" - Registered DQMB Inputs:			No \n"));
+
+			if (dimmInfo->differentialClockInput == 1)
+				DP (printf
+				    (" - Differential Clock Input:			Yes \n"));
+			else
+				DP (printf
+				    (" - Differential Clock Input:			No \n"));
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				DP (printf
+				    (" - redundant Row Addressing:			Yes \n"));
+			else
+				DP (printf
+				    (" - redundant Row Addressing:			No \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+#ifdef DEBUG
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				DP (printf
+				    (" - Early Ras Precharge:			Yes \n"));
+			else
+				DP (printf
+				    (" -  Early Ras Precharge:			No \n"));
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				DP (printf
+				    (" - AutoPreCharge:				Yes \n"));
+			else
+				DP (printf
+				    (" -  AutoPreCharge:				No \n"));
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				DP (printf
+				    (" - Precharge All:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Precharge All:				No \n"));
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				DP (printf
+				    (" - Write 1/ReadBurst:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Write 1/ReadBurst:				No \n"));
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				DP (printf
+				    (" - lower VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    ("  - lower VCC tolerance:			10 Percent \n"));
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				DP (printf
+				    (" - upper VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    (" -  upper VCC tolerance:			10 Percent \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100));
+			DP (printf
+			    ("Minimum Row Precharge Time [ns]: 		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trrd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Row Active -To- Row Active Delay [ns]: 	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trcd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras-To-Cas Delay [ns]: 			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras Pulse Width [ns]: 			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks));
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			DP (printf
+			    ("Module Bank Density: 				%d\n",
+			     dimmInfo->moduleBankDensity));
+#ifdef DEBUG
+			DP (printf
+			    ("*** Offered Densities (more than 1 = Multisize-Module): "));
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					DP (printf ("4MB, "));
+				if (dimmInfo->moduleBankDensity & 2)
+					DP (printf ("8MB, "));
+				if (dimmInfo->moduleBankDensity & 4)
+					DP (printf ("16MB, "));
+				if (dimmInfo->moduleBankDensity & 8)
+					DP (printf ("32MB, "));
+				if (dimmInfo->moduleBankDensity & 16)
+					DP (printf ("64MB, "));
+				if (dimmInfo->moduleBankDensity & 32)
+					DP (printf ("128MB, "));
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					DP (printf ("ERROR, "));
+					hang ();
+				}
+			}
+			DP (printf ("\n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Setup Time [ns]: 		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Hold Time [ns]: 		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Setup Time [ns]: 			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Hold Time [ns]: 			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices -
+			 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
+			 dimmInfo->numberOfDevices / 8);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)       */
+	dimmInfo->drb_size = (uchar) tmp;
+	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 3) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 3;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 2;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		hang ();
+		return 0;
+	}
+
+	return true;
+#endif
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp, check;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	int i;
+
+	/* added 8/21/2003 P. Marchese */
+	unsigned int sdram_config_reg;
+
+	/* added 10/10/2003 P. Marchese */
+	ulong sdram_chip_size;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	DP (printf ("Delay line set done\n"));
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM configuration */
+/* added 8/21/2003 P. Marchese */
+/* code allows usage of registered DIMMS */
+
+	/* figure out the memory refresh internal */
+	switch (info->RefreshInterval) {
+	case 0x0:
+	case 0x80:		/* refresh period is 15.625 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
+					/ (float) 1000000.0);
+		break;
+	case 0x1:
+	case 0x81:		/* refresh period is 3.9 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x2:
+	case 0x82:		/* refresh period is 7.8 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x3:
+	case 0x83:		/* refresh period is 31.3 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x4:
+	case 0x84:		/* refresh period is 62.5 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	case 0x5:
+	case 0x85:		/* refresh period is 125 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
+					(float) 1000000.0);
+		break;
+	default:		/* refresh period undefined */
+		printf ("DRAM refresh period is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+	DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
+
+	/* make sure the refresh value is only 14 bits */
+	if (sdram_config_reg > 0x1fff)
+		sdram_config_reg = 0x1fff;
+	DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
+
+	/* we want physical bank interleaving and */
+	/* virtual bank interleaving enabled so do nothing */
+	/* since these bits need to be zero to enable the interleaving */
+
+	/*  registered DRAM ? */
+	if (info->registeredAddrAndControlInputs == 1) {
+		/* it's registered DRAM, so set the reg. DRAM bit */
+		sdram_config_reg = sdram_config_reg | BIT17;
+		DP (printf ("Enabling registered DRAM bit\n"));
+	}
+	/* turn on DRAM ECC? */
+#ifdef CONFIG_MV64460_ECC
+	if (info->errorCheckType == 0x2) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg = sdram_config_reg | BIT18;
+		DP (printf ("Enabling ECC\n"));
+	}
+#endif
+	/* set the data DQS pin configuration */
+	switch (info->sdramWidth) {
+	case 0x4:		/* memory is x4 */
+		sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
+		DP (printf ("Data DQS pins set for 16 pins\n"));
+		break;
+	case 0x8:		/* memory is x8 or x16 */
+	case 0x10:
+		sdram_config_reg = sdram_config_reg | BIT21;
+		DP (printf ("Data DQS pins set for 8 pins\n"));
+		break;
+	case 0x20:		/* memory is x32 */
+		/* both bits are cleared for x32 so nothing to do */
+		DP (printf ("Data DQS pins set for 2 pins\n"));
+		break;
+	default:		/* memory width unsupported */
+		printf ("DRAM chip width is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+
+	/*ronen db64460 */
+	/* perform read buffer assignments */
+	/* we are going to use the Power-up defaults */
+	/* bit 27 = PCI bus #0 = buffer 0 */
+	/* bit 28 = PCI bus #1 = buffer 0 */
+	/* bit 29 = MPSC = buffer 0 */
+	/* bit 30 = IDMA = buffer 0 */
+	/* bit 31 = Gigabit = buffer 0 */
+	sdram_config_reg = sdram_config_reg | 0x58000000;
+	sdram_config_reg = sdram_config_reg & 0xffffff00;
+	/* bit 14 FBSplit = FCRAM controller bsplit enable. */
+	/* bit 15 vw = FCRAM Variable write length enable.   */
+	/* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
+	sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
+
+	/* write the value into the SDRAM configuration register */
+	GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
+	DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM open pages control keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	DP (printf
+	    ("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+	else
+		DP (printf
+		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+
+	/* SDRAM set CAS Latency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		printf ("### SD-RAM not supported !!!\n");
+		printf ("Aborting!!!\n");
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+		/* Calculate the settings for SDRAM mode and Dunit control low registers */
+		/* Values set according to technical bulletin TB-92 rev. c */
+	case DDR:
+		DP (printf ("### SET-CL for DDR-RAM\n"));
+		/* ronen db64460 - change the tmp_dunit_control_low setting!!! */
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x05110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0xC5000540;
+				else
+					tmp_dunit_control_low = 0xC4000540;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2_5:
+			tmp_sdram_mode = 0x62;	/* CL=2.5 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x25110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0xC5000540;
+					/* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
+					/* printf("Aborting!!!\n");1 */
+					/* hang();1 */
+				} else
+					tmp_dunit_control_low = 0xC4000540;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2:
+			tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x04110051;
+				else
+					tmp_dunit_control_low = 0x03110051;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					/*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
+					/*printf("Aborting!!!\n");1 */
+					/*hang();1 */
+					tmp_dunit_control_low = 0xC4000540;
+				} else
+					tmp_dunit_control_low = 0xC3000540;;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_1_5:
+			tmp_sdram_mode = 0x52;	/* CL=1.5 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x24110051;
+				else
+					tmp_dunit_control_low = 0x23110051;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					/*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
+					/*printf("Aborting!!!\n");1 */
+					/*hang();1 */
+					tmp_dunit_control_low = 0xC4000540;
+				} else
+					tmp_dunit_control_low = 0xC3000540;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}		/* end DDR switch */
+		break;
+	}			/* end CL switch */
+
+	/* Write results of CL detection procedure */
+	/* set SDRAM mode reg. 0x141c */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+	}
+
+/*------------------------------------------------------------------------------ */
+
+	/* bank parameters */
+	/* SDRAM address decode register 0x1410 */
+	/* program this with the default value */
+	tmp = 0x02;		/* power-up default address select decoding value */
+
+	DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+/* figure out the DRAM chip size */
+	sdram_chip_size =
+		(1 << (info->numOfRowAddresses + info->numOfColAddresses));
+	sdram_chip_size *= info->sdramWidth;
+	sdram_chip_size *= 4;
+	DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
+	/* divide sdram chip size by 64 Mbits */
+	sdram_chip_size = sdram_chip_size / 0x4000000;
+	switch (sdram_chip_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		printf ("RAM-Device_size is unsupported\n");
+		hang ();
+	}
+
+	/* SDRAM address control */
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+	DP (printf
+	    ("setting up sdram address control (0x1410) with: %08lx \n",
+	     tmp));
+
+/* ------------------------------------------------------------------------------ */
+/* same settings for registerd & non-registerd DDR SDRAM */
+	DP (printf
+	    ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
+	     0x01501220));
+	/*ronen db64460 */
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		DP (printf
+		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs));
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+indent: Standard input:1465: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+4460 */
+	tmp |= (1 << 26);
+	DP (printf
+	    ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+	DP (printf
+	    ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM timing To_do: */
+/* ------------------------------------------------------------------------------ */
+	/* ronen db64460 */
+	DP (printf
+	    ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
+	     0xc));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
+
+	DP (printf
+	    ("setting up sdram address pads control (0x14c0) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
+
+	DP (printf
+	    ("setting up sdram data pads control (0x14c4) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
+
+/* ------------------------------------------------------------------------------ */
+
+	/* set the SDRAM configuration for each bank */
+
+/*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		i = info->slot;
+		DP (printf
+		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+
+		/* set SDRAM mode */ /* To_do check it */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			DP (printf
+			    ("Found %08x  at Address %08x (failure)\n",
+			     (unsigned int) val, (unsigned int) addr));
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+phys_size_t initdram (int board_type)
+{
+	int s0 = 0, s1 = 0;
+	int checkbank[4] = {[0 ... 3] = 0 };
+	ulong realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int nhr, bank_no;
+	ulong dest, memSpaceAttr;
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0 () & (1 << 16);
+
+	if (nhr) {
+		printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		s0 = check_dimm (0, &dimmInfo1);
+
+		/* DIMM1 */
+		s1 = check_dimm (1, &dimmInfo2);
+
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
+
+		/* ronen check correct set of DIMMS */
+		if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
+			if (dimmInfo1.errorCheckType !=
+			    dimmInfo2.errorCheckType)
+				printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
+			if (dimmInfo1.maxClSupported_DDR !=
+			    dimmInfo2.maxClSupported_DDR)
+				printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
+			if (dimmInfo1.registeredAddrAndControlInputs !=
+			    dimmInfo2.registeredAddrAndControlInputs)
+				printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
+		}
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
+			printf ("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
+			printf ("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0 (get_hid0 () | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB / 4;
+	if (dimmInfo1.numOfModuleBanks > 0) {
+		checkbank[0] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 1) {
+		checkbank[1] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+	printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
+
+	if (dimmInfo2.numOfModuleBanks > 0) {
+		checkbank[2] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 1) {
+		checkbank[3] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
+
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (!checkbank[bank_no])
+			continue;
+
+		/* ronen - realsize = dram_size((long int *)total, check); */
+		if (bank_no == 0 || bank_no == 1) {
+			if (checkbank[1] == 1)
+				realsize = dimmInfo1.size / 2;
+			else
+				realsize = dimmInfo1.size;
+		}
+		if (bank_no == 2 || bank_no == 3) {
+			if (checkbank[3] == 1)
+				realsize = dimmInfo2.size / 2;
+			else
+				realsize = dimmInfo2.size;
+		}
+		memory_map_bank (bank_no, total, realsize);
+
+		/* ronen - initialize the DRAM for ECC */
+#ifdef CONFIG_MV64460_ECC
+		if ((dimmInfo1.errorCheckType != 0) &&
+		    ((dimmInfo2.errorCheckType != 0)
+		     || (dimmInfo2.numOfModuleBanks == 0))) {
+			printf ("ECC Initialization of Bank %d:", bank_no);
+			memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
+					     realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mvDmaTransfer (0, total, dest, _8M,
+					       BIT8 /*DMA_DTL_128BYTES */  |
+					       BIT3 /*DMA_HOLD_SOURCE_ADDR */
+					       |
+					       BIT11
+					       /*DMA_BLOCK_TRANSFER_MODE */ );
+				while (mvDmaIsChannelActive (0));
+			}
+			printf (" PASS\n");
+		}
+#endif
+
+		total += realsize;
+	}
+
+	/* ronen */
+	switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
+	case 0x2:
+		printf ("CAS Latency = 2");
+		break;
+	case 0x3:
+		printf ("CAS Latency = 3");
+		break;
+	case 0x5:
+		printf ("CAS Latency = 1.5");
+		break;
+	case 0x6:
+		printf ("CAS Latency = 2.5");
+		break;
+	}
+	printf (" tRP = %d tRAS = %d tRCD=%d\n",
+		((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	if (total > _256M)
+		printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
+	else
+		printf ("Total SDRAM memory is ");
+	/* (cause all the 4 BATS are taken) */
+	return (total);
+}
+
+
+/* ronen- add Idma functions for usage of the ecc dram init. */
+/*******************************************************************************
+* mvDmaIsChannelActive - Checks if a engine is busy.
+********************************************************************************/
+int mvDmaIsChannelActive (int engine)
+{
+	ulong data;
+
+	data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14 /*activity status */ ) {
+		return 1;
+	}
+	return 0;
+}
+
+/*******************************************************************************
+* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
+*                       map.
+*******************************************************************************/
+int mvDmaSetMemorySpace (ulong memSpace,
+			 ulong memSpaceTarget,
+			 ulong memSpaceAttr, ulong baseAddress, ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return 0;
+	}
+	if (size >= 0x10000 /*64K */ ) {
+		size &= 0xffff0000;
+		baseAddress = (baseAddress & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
+			      (temp & ~(BIT0 << memSpace)));
+		return 1;
+	}
+	return 0;
+}
+
+
+/*******************************************************************************
+* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
+*                 DMA channels.
+********************************************************************************/
+int mvDmaTransfer (int engine, ulong sourceAddr,
+		   ulong destAddr, ulong numOfBytes, ulong command)
+{
+	ulong engOffReg = 0;	/* Engine Offset Register */
+
+	if (numOfBytes > 0xffff) {
+		command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
+	}
+	command = command | ((command >> 6) & 0x7);
+	engOffReg = engine * 4;
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
+		      numOfBytes);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
+		      sourceAddr);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
+		      destAddr);
+	command =
+		command | BIT12 /*DMA_CHANNEL_ENABLE */  | BIT9
+		/*DMA_NON_CHAIN_MODE */ ;
+	/* Activate DMA engine By writting to mvDmaControlRegister */
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
+	return 1;
+}
+
+/****************************************************************************************
+ *			       SDRAM INIT						*
+ *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+ *		 This procedure fits only the Atlantis					*
+ *											*
+ ***************************************************************************************/
+
+
+/****************************************************************************************
+ *			       DFCDL initialize MV643xx Design Considerations		*
+ *											*
+ ***************************************************************************************/
+int set_dfcdlInit (void)
+{
+	/*ronen the dfcdl init are done by the I2C */
+	return (0);
+}
diff --git a/u-boot/board/Marvell/dkb/Makefile b/u-boot/board/Marvell/dkb/Makefile
new file mode 100644
index 0000000..2fafdb3
--- /dev/null
+++ b/u-boot/board/Marvell/dkb/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)lib$(BOARD).o
+
+COBJS	:= dkb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/dkb/dkb.c b/u-boot/board/Marvell/dkb/dkb.c
new file mode 100644
index 0000000..72a2d2a
--- /dev/null
+++ b/u-boot/board/Marvell/dkb/dkb.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART2 */
+		MFP47_UART2_RXD,
+		MFP48_UART2_TXD,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
+	return 0;
+}
diff --git a/u-boot/board/Marvell/guruplug/Makefile b/u-boot/board/Marvell/guruplug/Makefile
new file mode 100644
index 0000000..ff7e9d7
--- /dev/null
+++ b/u-boot/board/Marvell/guruplug/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= guruplug.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/guruplug/guruplug.c b/u-boot/board/Marvell/guruplug/guruplug.c
new file mode 100644
index 0000000..1f0e67a
--- /dev/null
+++ b/u-boot/board/Marvell/guruplug/guruplug.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "guruplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(GURUPLUG_OE_VAL_LOW,
+			GURUPLUG_OE_VAL_HIGH,
+			GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,	/* GPIO_RST */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GE1_8,
+		MPP29_GE1_9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GE1_15,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_TDM_SPI_SCK,
+		MPP41_TDM_SPI_MISO,
+		MPP42_TDM_SPI_MOSI,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO, 	/* M_RLED */
+		MPP47_GPIO,	/* M_GLED */
+		MPP48_GPIO,	/* B_RLED */
+		MPP49_GPIO,	/* B_GLED */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1121_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
+	reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
+	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1121 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+	/* configure and initialize both PHY's */
+	mv_phy_88e1121_init("egiga0");
+	mv_phy_88e1121_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/u-boot/board/Marvell/guruplug/guruplug.h b/u-boot/board/Marvell/guruplug/guruplug.h
new file mode 100644
index 0000000..5bc16b4
--- /dev/null
+++ b/u-boot/board/Marvell/guruplug/guruplug.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __GURUPLUG_H
+#define __GURUPLUG_H
+
+#define GURUPLUG_OE_LOW		(~(0))
+#define GURUPLUG_OE_HIGH	(~(0))
+#define GURUPLUG_OE_VAL_LOW	0
+#define GURUPLUG_OE_VAL_HIGH	(0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1121_MAC_CTRL2_REG		21
+#define MV88E1121_PGADR_REG		22
+#define MV88E1121_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1121_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __GURUPLUG_H */
diff --git a/u-boot/board/Marvell/guruplug/kwbimage.cfg b/u-boot/board/Marvell/guruplug/kwbimage.cfg
new file mode 100644
index 0000000..2afd927
--- /dev/null
+++ b/u-boot/board/Marvell/guruplug/kwbimage.cfg
@@ -0,0 +1,162 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   01, Cs0width=x8
+# bit3-2:   10, Cs0size=1Gb
+# bit5-4:   01, Cs1width=x8
+# bit7-6:   10, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/Marvell/include/core.h b/u-boot/board/Marvell/include/core.h
new file mode 100644
index 0000000..c413439
--- /dev/null
+++ b/u-boot/board/Marvell/include/core.h
@@ -0,0 +1,241 @@
+/* Core.h - Basic core logic functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This header file contains simple read/write macros for addressing
+the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
+space). The macros take care of Big/Little endian conversions.
+*/
+
+#ifndef __INCcoreh
+#define __INCcoreh
+
+#include "mv_gen_reg.h"
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/****************************************/
+/*	    GENERAL Definitions			*/
+/****************************************/
+
+#define NO_BIT		0x00000000
+#define BIT0		0x00000001
+#define BIT1		0x00000002
+#define BIT2		0x00000004
+#define BIT3		0x00000008
+#define BIT4		0x00000010
+#define BIT5		0x00000020
+#define BIT6		0x00000040
+#define BIT7		0x00000080
+#define BIT8		0x00000100
+#define BIT9		0x00000200
+#define BIT10		0x00000400
+#define BIT11		0x00000800
+#define BIT12		0x00001000
+#define BIT13		0x00002000
+#define BIT14		0x00004000
+#define BIT15		0x00008000
+#define BIT16		0x00010000
+#define BIT17		0x00020000
+#define BIT18		0x00040000
+#define BIT19		0x00080000
+#define BIT20		0x00100000
+#define BIT21		0x00200000
+#define BIT22		0x00400000
+#define BIT23		0x00800000
+#define BIT24		0x01000000
+#define BIT25		0x02000000
+#define BIT26		0x04000000
+#define BIT27		0x08000000
+#define BIT28		0x10000000
+#define BIT29		0x20000000
+#define BIT30		0x40000000
+#define BIT31		0x80000000
+
+#define _1K		0x00000400
+#define _2K		0x00000800
+#define _4K		0x00001000
+#define _8K		0x00002000
+#define _16K		0x00004000
+#define _32K		0x00008000
+#define _64K		0x00010000
+#define _128K		0x00020000
+#define _256K		0x00040000
+#define _512K		0x00080000
+
+#define _1M		0x00100000
+#define _2M		0x00200000
+#define _3M		0x00300000
+#define _4M		0x00400000
+#define _5M		0x00500000
+#define _6M		0x00600000
+#define _7M		0x00700000
+#define _8M		0x00800000
+#define _9M		0x00900000
+#define _10M		0x00a00000
+#define _11M		0x00b00000
+#define _12M		0x00c00000
+#define _13M		0x00d00000
+#define _14M		0x00e00000
+#define _15M		0x00f00000
+#define _16M		0x01000000
+
+#define _32M		0x02000000
+#define _64M		0x04000000
+#define _128M		0x08000000
+#define _256M		0x10000000
+#define _512M		0x20000000
+
+#define _1G		0x40000000
+#define _2G		0x80000000
+
+#ifndef	BOOL_WAS_DEFINED
+#define BOOL_WAS_DEFINED
+typedef enum _bool{false,true} bool;
+#endif
+
+/* Little to Big endian conversion macros */
+
+#ifdef LE /* Little Endian */
+#define SHORT_SWAP(X) (X)
+#define WORD_SWAP(X) (X)
+#define LONG_SWAP(X) ((l64)(X))
+
+#else	 /* Big Endian */
+#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
+
+#define WORD_SWAP(X) (((X)&0xff)<<24)+	    \
+		    (((X)&0xff00)<<8)+	    \
+		    (((X)&0xff0000)>>8)+    \
+		    (((X)&0xff000000)>>24)
+
+#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+		\
+			    (((X)&0xff00ULL)<<40)+		\
+			    (((X)&0xff0000ULL)<<24)+		\
+			    (((X)&0xff000000ULL)<<8)+		\
+			    (((X)&0xff00000000ULL)>>8)+		\
+			    (((X)&0xff0000000000ULL)>>24)+	\
+			    (((X)&0xff000000000000ULL)>>40)+	\
+			    (((X)&0xff00000000000000ULL)>>56))
+
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* Those two definitions were defined to be compatible with MIPS */
+#define NONE_CACHEABLE		0x00000000
+#define CACHEABLE			0x00000000
+
+/* 750 cache line */
+#define CACHE_LINE_SIZE 32
+#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
+#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
+
+/* Read/Write to/from GT`s internal registers */
+#define GT_REG_READ(offset, pData)					    \
+*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |			    \
+		INTERNAL_REG_BASE_ADDR | (offset))) ) ;						     \
+*pData = WORD_SWAP(*pData)
+
+#define GTREGREAD(offset)						    \
+	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |	     \
+		   INTERNAL_REG_BASE_ADDR | (offset))) ))
+
+#define GT_REG_WRITE(offset, data)					    \
+*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =		    \
+		    WORD_SWAP(data)
+
+/* Write 32/16/8 bit */
+#define WRITE_CHAR(address, data)					    \
+	*((unsigned char *)(address)) = data
+#define WRITE_SHORT(address, data)					    \
+	*((unsigned short *)(address)) = data
+#define WRITE_WORD(address, data)					    \
+	*((unsigned int *)(address)) = data
+
+#define GT_WRITE_CHAR(address, data)	 WRITE_CHAR(address, data)
+
+/* Write 32/16/8 bit NonCacheable */
+/*
+#define GT_WRITE_CHAR(address, data)					       \
+	(*((unsigned char *)NONE_CACHEABLE(address))) = data
+#define GT_WRITE_SHORT(address, data)					       \
+	(*((unsigned short *)NONE_CACHEABLE(address))) = data
+#define GT_WRITE_WORD(address, data)					       \
+	(*((unsigned int *)NONE_CACHEABLE(address))) = data
+*/
+ /*#define GT_WRITE_CHAR(address, data)	  ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
+
+ /*#define GT_WRITE_SHORT(address, data)   ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
+
+ /*#define GT_WRITE_WORD(address, data)	 ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
+
+
+/* Read 32/16/8 bits - returns data in variable. */
+#define READ_CHAR(address, pData)					    \
+	*pData = *((volatile unsigned char *)(address))
+
+#define READ_SHORT(address, pData)					    \
+	*pData = *((volatile unsigned short *)(address))
+
+#define READ_WORD(address, pData)					    \
+	*pData = *((volatile unsigned int *)(address))
+
+/* Read 32/16/8 bit - returns data direct. */
+#define READCHAR(address)						    \
+	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
+
+#define READSHORT(address)						    \
+	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
+
+#define READWORD(address)						    \
+	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
+
+/* Those two Macros were defined to be compatible with MIPS */
+#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
+#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
+
+/*  SET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+#define SET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
+	regOffset) |= (unsigned int)WORD_SWAP(bits)
+
+/*  RESET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '0' in register 0x840 while the other bits stays as is. */
+#define RESET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
+	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
+/* gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+ /*#define GT_SET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
+ /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
+#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
+/* gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
+   logic '0' in register 0x840 while the other bits stays as is. */
+ /*#define GT_RESET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) |  (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
+#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
+
+
+#define DEBUG_LED0_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
+#define DEBUG_LED1_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
+#define DEBUG_LED2_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
+#define DEBUG_LED0_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
+#define DEBUG_LED1_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
+#define DEBUG_LED2_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
+
+#endif /* __INCcoreh */
diff --git a/u-boot/board/Marvell/include/memory.h b/u-boot/board/Marvell/include/memory.h
new file mode 100644
index 0000000..0947b6e
--- /dev/null
+++ b/u-boot/board/Marvell/include/memory.h
@@ -0,0 +1,173 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY	0xffffffff
+#define PARITY_SUPPORT	0x40000000
+#define MINIMUM_MEM_BANK_SIZE		0x10000
+#define MINIMUM_DEVICE_WINDOW_SIZE	0x10000
+#define MINIMUM_PCI_WINDOW_SIZE		0x10000
+#define MINIMUM_ACCESS_WIN_SIZE		0x10000
+
+#define _8BIT		0x00000000
+#define _16BIT		0x00100000
+#define _32BIT		0x00200000
+#define _64BIT		0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{						/* boundary values  */
+    unsigned int    turnOff;			/* 0x0 - 0xf	    */
+    unsigned int    acc2First;			/* 0x0 - 0x1f	    */
+    unsigned int    acc2Next;		/* 0x0 - 0x1f	    */
+    unsigned int    ale2Wr;			/* 0x0 - 0xf	    */
+    unsigned int    wrLow;			/* 0x0 - 0xf	    */
+    unsigned int    wrHigh;			/* 0x0 - 0xf	    */
+    unsigned int    badrSkew;		/* 0x0 - 0x2	   */
+    unsigned int    DPEn;			/* 0x0 - 0x1	   */
+    unsigned int    deviceWidth;	/* in Bytes  */
+} DEVICE_PARAM;
+
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,	\
+				   MEM_REGION3,MEM_REGION4,MEM_REGION5,	      \
+				   MEM_REGION6,MEM_REGION7}		      \
+				   MEMORY_PROTECT_REGION;*/
+/* There are four possible windows that can be defined as protected */
+typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
+				  MEM_WINDOW3
+				 } MEMORY_PROTECT_WINDOW;
+/* When defining a protected window , this paramter indicates whether it
+   is accessible or not */
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}	      \
+			    MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}	      \
+			   MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}	      \
+				  MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}	      \
+			       MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,	      \
+				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}	      \
+				 MEMORY_SNOOP_REGION;
+
+/* There are 21 memory windows dedicated for the varios interfaces (PCI,
+   devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
+   address decoding mechanism. */
+typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
+			    CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
+			    DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
+			    DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
+			    BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
+			    PCI_0_MEM0_WINDOW = BIT10,
+			    PCI_0_MEM1_WINDOW = BIT11,
+			    PCI_0_MEM2_WINDOW = BIT12,
+			    PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
+			    PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
+			    PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
+			    INTEGRATED_SRAM_WINDOW = BIT19,
+			    INTERNAL_SPACE_WINDOW = BIT20,
+			    ALL_WINDOWS = 0X1FFFFF
+			   } MEMORY_WINDOW;
+
+typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
+				 } MEMORY_WINDOW_STATUS;
+
+
+typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
+#ifdef INCLUDE_PCI_1
+			  ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
+#endif /* INCLUDE_PCI_1 */
+			  } PCI_MEM_WINDOW;
+
+
+/* -------------------------------------------------------------------------------------------------*/
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+/* New at MV6436x */
+unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+/* New at MV6436x */
+unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+/* Set a new base and size for one of the memory banks (CS0 - CS3) */
+bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
+			   unsigned int bankSize);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+
+/* Returns the integrated SRAM Base Address. */
+unsigned int memoryGetInternalSramBaseAddr(void);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Set new base address for the integrated SRAM. */
+void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Delete a protection feature to a given space. */
+void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Writes a new remap value to the remap register */
+unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
+				      unsigned int remapValueHigh,
+				      unsigned int remapValueLow);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
+			      MEMORY_ACCESS gtMemoryAccess,
+			      MEMORY_ACCESS_WRITE gtMemoryWrite,
+			      MEMORY_CACHE_PROTECT cacheProtection,
+			      unsigned int baseAddress,
+			      unsigned int size);
+
+/* Configurate the protection feature to a given space. */
+/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memoryAccess,
+			    MEMORY_ACCESS_WRITE memoryWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength); */
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+/* Set a new base and size for one of the PCI windows. */
+bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+			  unsigned int pciWindowSize);
+
+/* Disable or enable one of the 21 windows dedicated for the CPU's
+   address decoding mechanism */
+void MemoryDisableWindow(MEMORY_WINDOW window);
+void MemoryEnableWindow (MEMORY_WINDOW window);
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
+#endif	/* __INCmemoryh */
diff --git a/u-boot/board/Marvell/include/mv_gen_reg.h b/u-boot/board/Marvell/include/mv_gen_reg.h
new file mode 100644
index 0000000..5e4f076
--- /dev/null
+++ b/u-boot/board/Marvell/include/mv_gen_reg.h
@@ -0,0 +1,2288 @@
+/* mv_gen_reg.h - Internal registers definition file */
+/* Copyright - Galileo technology. */
+
+
+/*******************************************************************************
+*		    Copyright 2002, GALILEO TECHNOLOGY, LTD.		       *
+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.		       *
+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE	       *
+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
+*									       *
+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
+* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
+********************************************************************************
+* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_gen_regh
+#define __INCmv_gen_regh
+
+
+/* Supported by the Atlantis */
+#define INCLUDE_PCI_1
+#define INCLUDE_PCI_0_ARBITER
+#define INCLUDE_PCI_1_ARBITER
+#define INCLUDE_SNOOP_SUPPORT
+#define INCLUDE_P2P
+#define INCLUDE_ETH_PORT_2
+#define INCLUDE_CPU_MAPPING
+#define INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+
+/****************************************/
+/* Processor Address Space				*/
+/****************************************/
+/* DDR SDRAM BAR and size registers */
+
+/* Sdram's BAR'S */
+#define SCS_0_LOW_DECODE_ADDRESS			0x008
+#define SCS_0_HIGH_DECODE_ADDRESS			0x010
+#define SCS_1_LOW_DECODE_ADDRESS			0x208
+#define SCS_1_HIGH_DECODE_ADDRESS			0x210
+#define SCS_2_LOW_DECODE_ADDRESS			0x018
+#define SCS_2_HIGH_DECODE_ADDRESS			0x020
+#define SCS_3_LOW_DECODE_ADDRESS			0x218
+#define SCS_3_HIGH_DECODE_ADDRESS			0x220
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+#define CS_0_BASE_ADDR			SCS_0_LOW_DECODE_ADDRESS
+#define CS_0_SIZE			SCS_0_HIGH_DECODE_ADDRESS
+#define CS_1_BASE_ADDR		SCS_1_LOW_DECODE_ADDRESS
+#define CS_1_SIZE			SCS_1_HIGH_DECODE_ADDRESS
+#define CS_2_BASE_ADDR		SCS_2_LOW_DECODE_ADDRESS
+#define CS_2_SIZE			SCS_2_HIGH_DECODE_ADDRESS
+#define CS_3_BASE_ADDR		SCS_3_LOW_DECODE_ADDRESS
+#define CS_3_SIZE			SCS_3_HIGH_DECODE_ADDRESS
+
+/* Devices BAR'S */
+#define CS_0_LOW_DECODE_ADDRESS			0x028
+#define CS_0_HIGH_DECODE_ADDRESS			0x030
+#define CS_1_LOW_DECODE_ADDRESS			0x228
+#define CS_1_HIGH_DECODE_ADDRESS			0x230
+#define CS_2_LOW_DECODE_ADDRESS			0x248
+#define CS_2_HIGH_DECODE_ADDRESS			0x250
+#define CS_3_LOW_DECODE_ADDRESS			0x038
+#define CS_3_HIGH_DECODE_ADDRESS			0x040
+#define BOOTCS_LOW_DECODE_ADDRESS			0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS			0x240
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+/* Devices BAR and size registers */
+
+#define DEV_CS0_BASE_ADDR	CS_0_LOW_DECODE_ADDRESS
+#define DEV_CS0_SIZE			CS_0_HIGH_DECODE_ADDRESS
+#define DEV_CS1_BASE_ADDR	CS_1_LOW_DECODE_ADDRESS
+#define DEV_CS1_SIZE		CS_1_HIGH_DECODE_ADDRESS
+#define DEV_CS2_BASE_ADDR	CS_2_LOW_DECODE_ADDRESS
+#define DEV_CS2_SIZE			CS_2_HIGH_DECODE_ADDRESS
+#define DEV_CS3_BASE_ADDR		CS_3_LOW_DECODE_ADDRESS
+#define DEV_CS3_SIZE		CS_3_HIGH_DECODE_ADDRESS
+#define BOOTCS_BASE_ADDR	BOOTCS_LOW_DECODE_ADDRESS
+#define BOOTCS_SIZE		BOOTCS_HIGH_DECODE_ADDRESS
+
+/* PCI 0 BAR and size registers	 old names of evb64260*/
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS		0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS		0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS		0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS		0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+#define PCI_0_IO_BASE_ADDR						0x048
+#define PCI_0_IO_SIZE							0x050
+#define PCI_0_MEMORY0_BASE_ADDR					0x058
+#define PCI_0_MEMORY0_SIZE						0x060
+#define PCI_0_MEMORY1_BASE_ADDR					0x080
+#define PCI_0_MEMORY1_SIZE						0x088
+#define PCI_0_MEMORY2_BASE_ADDR					0x258
+#define PCI_0_MEMORY2_SIZE						0x260
+#define PCI_0_MEMORY3_BASE_ADDR					0x280
+#define PCI_0_MEMORY3_SIZE						0x288
+
+/* PCI 1 BAR and size registers	 old names of evb64260*/
+#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS		0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS		0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS		0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS		0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+#define PCI_1_IO_BASE_ADDR						0x090
+#define PCI_1_IO_SIZE							0x098
+#define PCI_1_MEMORY0_BASE_ADDR					0x0a0
+#define PCI_1_MEMORY0_SIZE						0x0a8
+#define PCI_1_MEMORY1_BASE_ADDR					0x0b0
+#define PCI_1_MEMORY1_SIZE						0x0b8
+#define PCI_1_MEMORY2_BASE_ADDR					0x2a0
+#define PCI_1_MEMORY2_SIZE						0x2a8
+#define PCI_1_MEMORY3_BASE_ADDR					0x2b0
+#define PCI_1_MEMORY3_SIZE						0x2b8
+
+/* internal registers space base address */
+#define INTERNAL_SPACE_DECODE				0x068
+#define INTERNAL_SPACE_BASE_ADDR				INTERNAL_SPACE_DECODE
+
+/* SRAM base address */
+#define INTEGRATED_SRAM_BASE_ADDR				0x268
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define BASE_ADDR_ENABLE						0x278
+
+
+#define CPU_0_LOW_DECODE_ADDRESS				0x290
+#define CPU_0_HIGH_DECODE_ADDRESS				0x298
+#define CPU_1_LOW_DECODE_ADDRESS				0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS				0x2c8
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+/*****************************************************************************************/
+      /* PCI 0 */
+/* old fashion evb 64260 */
+#define PCI_0I_O_ADDRESS_REMAP				0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP		0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP		0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP		0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP		0x338
+
+#define PCI_0_IO_ADDR_REMAP						PCI_0I_O_ADDRESS_REMAP
+#define PCI_0_MEMORY0_LOW_ADDR_REMAP				PCI_0MEMORY0_ADDRESS_REMAP
+#define PCI_0_MEMORY0_HIGH_ADDR_REMAP				PCI_0MEMORY0_HIGH_ADDRESS_REMAP
+#define PCI_0_MEMORY1_LOW_ADDR_REMAP				PCI_0MEMORY1_ADDRESS_REMAP
+#define PCI_0_MEMORY1_HIGH_ADDR_REMAP				PCI_0MEMORY1_HIGH_ADDRESS_REMAP
+#define PCI_0_MEMORY2_LOW_ADDR_REMAP				PCI_0MEMORY2_ADDRESS_REMAP
+#define PCI_0_MEMORY2_HIGH_ADDR_REMAP				PCI_0MEMORY2_HIGH_ADDRESS_REMAP
+#define PCI_0_MEMORY3_LOW_ADDR_REMAP				PCI_0MEMORY3_ADDRESS_REMAP
+#define PCI_0_MEMORY3_HIGH_ADDR_REMAP				PCI_0MEMORY3_HIGH_ADDRESS_REMAP
+
+       /* PCI 1 */
+/* old fashion evb 64260 */
+#define PCI_1I_O_ADDRESS_REMAP				0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP		0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP		0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP		0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP		0x358
+
+#define PCI_1_IO_ADDR_REMAP						PCI_1I_O_ADDRESS_REMAP
+#define PCI_1_MEMORY0_LOW_ADDR_REMAP				PCI_1MEMORY0_ADDRESS_REMAP
+#define PCI_1_MEMORY0_HIGH_ADDR_REMAP				PCI_1MEMORY0_HIGH_ADDRESS_REMAP
+#define PCI_1_MEMORY1_LOW_ADDR_REMAP				PCI_1MEMORY1_ADDRESS_REMAP
+#define PCI_1_MEMORY1_HIGH_ADDR_REMAP				PCI_1MEMORY1_HIGH_ADDRESS_REMAP
+#define PCI_1_MEMORY2_LOW_ADDR_REMAP				PCI_1MEMORY2_ADDRESS_REMAP
+#define PCI_1_MEMORY2_HIGH_ADDR_REMAP				PCI_1MEMORY2_HIGH_ADDRESS_REMAP
+#define PCI_1_MEMORY3_LOW_ADDR_REMAP				PCI_1MEMORY3_ADDRESS_REMAP
+#define PCI_1_MEMORY3_HIGH_ADDR_REMAP				PCI_1MEMORY3_HIGH_ADDRESS_REMAP
+
+/* old fashion evb 64260 */
+#define CPU_PCI_0_HEADERS_RETARGET_CONTROL			0x3b0
+#define CPU_PCI_0_HEADERS_RETARGET_BASE				0x3b8
+#define CPU_PCI_1_HEADERS_RETARGET_CONTROL			0x3c0
+#define CPU_PCI_1_HEADERS_RETARGET_BASE				0x3c8
+#define CPU_GE_HEADERS_RETARGET_CONTROL				0x3d0
+#define CPU_GE_HEADERS_RETARGET_BASE				0x3d8
+
+/* MV64360 and MV64460 no changes needed*/
+/*****************************************************************************************/
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+/* CPU MASTER CONTROL REGISTER */
+#define CPU_CONFIGURATION				0x000
+#define CPU_MASTER_CONTROL				0x160
+
+#define CPU_CONFIG							0x000
+#define CPU_MODE							0x120
+#define CPU_MASTER_CONTROL						0x160
+/* new in MV64360 and MV64460 */
+#define CPU_CROSS_BAR_CONTROL_LOW				0x150
+#define CPU_CROSS_BAR_CONTROL_HIGH				0x158
+#define CPU_CROSS_BAR_TIMEOUT					0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define SMP_WHO_AM_I							0x200
+#define SMP_CPU0_DOORBELL						0x214
+#define SMP_CPU0_DOORBELL_CLEAR					0x21C
+#define SMP_CPU1_DOORBELL						0x224
+#define SMP_CPU1_DOORBELL_CLEAR					0x22C
+#define SMP_CPU0_DOORBELL_MASK					0x234
+#define SMP_CPU1_DOORBELL_MASK					0x23C
+#define SMP_SEMAPHOR0							0x244
+#define SMP_SEMAPHOR1							0x24c
+#define SMP_SEMAPHOR2							0x254
+#define SMP_SEMAPHOR3							0x25c
+#define SMP_SEMAPHOR4							0x264
+#define SMP_SEMAPHOR5							0x26c
+#define SMP_SEMAPHOR6							0x274
+#define SMP_SEMAPHOR7							0x27c
+
+
+/****************************************/
+/* CPU Sync Barrier				*/
+/****************************************/
+#define CPU_0_SYNC_BARRIER_TRIGGER				0x0c0
+#define CPU_0_SYNC_BARRIER_VIRTUAL				0x0c8
+#define CPU_1_SYNC_BARRIER_TRIGGER				0x0d0
+#define CPU_1_SYNC_BARRIER_VIRTUAL				0x0d8
+
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define CPU_LOW_PROTECT_ADDRESS_0			    0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0			    0x188
+#define CPU_LOW_PROTECT_ADDRESS_1			    0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1			    0x198
+#define CPU_LOW_PROTECT_ADDRESS_2			    0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2			    0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3			    0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3			    0x1b8
+/*#define CPU_LOW_PROTECT_ADDRESS_4			      0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4			    0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5			    0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5			    0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6			    0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6			    0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7			    0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7			    0x1f8
+*/
+
+#define CPU_PROTECT_WINDOW_0_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
+#define CPU_PROTECT_WINDOW_0_SIZE			    CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */
+#define CPU_PROTECT_WINDOW_1_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */
+#define CPU_PROTECT_WINDOW_1_SIZE			    CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */
+#define CPU_PROTECT_WINDOW_2_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */
+#define CPU_PROTECT_WINDOW_2_SIZE			    CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */
+#define CPU_PROTECT_WINDOW_3_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */
+#define CPU_PROTECT_WINDOW_3_SIZE			    CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */
+
+
+/****************************************/
+/*	    Snoop Control			*/
+/****************************************/
+
+/*#define SNOOP_BASE_ADDRESS_0				      0x380
+#define SNOOP_TOP_ADDRESS_0				    0x388
+#define SNOOP_BASE_ADDRESS_1				    0x390
+#define SNOOP_TOP_ADDRESS_1				    0x398
+#define SNOOP_BASE_ADDRESS_2				    0x3a0
+#define SNOOP_TOP_ADDRESS_2				    0x3a8
+#define SNOOP_BASE_ADDRESS_3				    0x3b0
+#define SNOOP_TOP_ADDRESS_3				    0x3b8
+*/
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define SRAM_CONFIG						0x380
+#define SRAM_TEST_MODE						0x3F4
+#define SRAM_ERROR_CAUSE					0x388
+#define SRAM_ERROR_ADDR						0x390
+#define SRAM_ERROR_ADDR_HIGH					0x3F8
+#define SRAM_ERROR_DATA_LOW					0x398
+#define SRAM_ERROR_DATA_HIGH					0x3a0
+#define SRAM_ERROR_DATA_PARITY					0x3a8
+
+/****************************************/
+/*	    CPU Error Report			*/
+/****************************************/
+
+#define CPU_ERROR_ADDRESS_LOW		0x070
+#define CPU_ERROR_ADDRESS_HIGH		0x078
+#define CPU_ERROR_DATA_LOW					0x128
+#define CPU_ERROR_DATA_HIGH					0x130
+#define CPU_ERROR_PARITY					0x138
+#define CPU_ERROR_CAUSE						0x140
+#define CPU_ERROR_MASK						0x148
+
+#define CPU_ERROR_ADDR_LOW					CPU_ERROR_ADDRESS_LOW  /* 0x0701 */
+#define CPU_ERROR_ADDR_HIGH					CPU_ERROR_ADDRESS_HIGH	/* 0x0781 */
+
+/****************************************/
+/*	    Pslave Debug			*/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define X_0_ADDRESS						0x360
+#define X_0_COMMAND_ID						0x368
+#define X_1_ADDRESS						0x370
+#define X_1_COMMAND_ID						0x378
+ /*#define WRITE_DATA_LOW					0x3c01 */
+ /*#define WRITE_DATA_HIGH					0x3c81 */
+ /*#define WRITE_BYTE_ENABLE					0x3e01 */
+ /*#define READ_DATA_LOW					0x3d01 */
+ /*#define READ_DATA_HIGH					0x3d81 */
+ /*#define READ_ID						0x3e81 */
+
+#define PUNIT_SLAVE_DEBUG_LOW					X_0_ADDRESS  /* 0x3601 */
+#define PUNIT_SLAVE_DEBUG_HIGH					X_0_COMMAND_ID	/* 0x3681 */
+#define PUNIT_MASTER_DEBUG_LOW					X_1_ADDRESS  /* 0x3701 */
+#define PUNIT_MASTER_DEBUG_HIGH				   X_1_COMMAND_ID  /* 0x3781 */
+#define PUNIT_MMASK						0x3e4
+
+
+/****************************************/
+/* SDRAM and Device Address Space		*/
+/****************************************/
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+#define SDRAM_CONFIG						0x1400	/* MV64260 0x448 some changes*/
+#define D_UNIT_CONTROL_LOW					0x1404	/* NEW in MV64360 and MV64460 */
+#define D_UNIT_CONTROL_HIGH					0x1424	/* NEW in MV64360 and MV64460 */
+#define SDRAM_TIMING_CONTROL_LOW			0x1408	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
+#define SDRAM_TIMING_CONTROL_HIGH			0x140c	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
+#define SDRAM_ADDR_CONTROL				    0x1410	/* MV64260 0x47c some changes*/
+#define SDRAM_OPEN_PAGES_CONTROL			0x1414	/* NEW in MV64360 and MV64460 */
+#define SDRAM_OPERATION						0x1418	/* MV64260 0x474 some changes*/
+#define SDRAM_MODE						0x141c	/* NEW in MV64360 and MV64460 */
+#define EXTENDED_DRAM_MODE					0x1420	/* NEW in MV64360 and MV64460 */
+#define SDRAM_CROSS_BAR_CONTROL_LOW			0x1430	/* MV64260 0x4a8 NO changes*/
+#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x1434	/* MV64260 0x4ac NO changes*/
+#define SDRAM_CROSS_BAR_TIMEOUT				0x1438	/* MV64260 0x4b0 NO changes*/
+#define SDRAM_ADDR_CTRL_PADS_CALIBRATION	0x14c0	/* what is this ??? */
+#define SDRAM_DATA_PADS_CALIBRATION			0x14c4	/* what is this ??? */
+/****************************************/
+/* SDRAM Configuration MV64260			*/
+/****************************************/
+ /*#define SDRAM_CONFIGURATION			0x4481 */
+ /*#define SDRAM_OPERATION_MODE			0x4741 */
+ /*#define SDRAM_ADDRESS_DECODE		0x47c1 */
+ /*#define SDRAM_UMA_CONTROL			0x4a4	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_CROSS_BAR_CONTROL_LOW	0x4a81 */
+ /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
+ /*#define SDRAM_CROSS_BAR_TIMEOUT		0x4b01 */
+ /*#define SDRAM_TIMING				0x4b41 */
+
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+#define SDRAM_ERROR_DATA_LOW				0x1444	/* MV64260 0x484 NO changes*/
+#define SDRAM_ERROR_DATA_HIGH					0x1440	/* MV64260 0x480 NO changes*/
+#define SDRAM_ERROR_ADDR					0x1450	/* MV64260 0x490 NO changes*/
+#define SDRAM_RECEIVED_ECC					0x1448	/* MV64260 0x488 NO changes*/
+#define SDRAM_CALCULATED_ECC					0x144c	/* MV64260 0x48c NO changes*/
+#define SDRAM_ECC_CONTROL					0x1454	/* MV64260 0x494 NO changes*/
+#define SDRAM_ECC_ERROR_COUNTER				0x1458	/* MV64260 0x498 NO changes*/
+#define SDRAM_MMASK					0x1B40	/* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
+/****************************************/
+/* SDRAM Error Report MV64260			*/
+/****************************************/
+ /*#define SDRAM_ERROR_DATA_LOW					0x4841 */
+ /*#define SDRAM_ERROR_DATA_HIGH				0x4801 */
+ /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS		0x4901 */
+ /*#define SDRAM_RECEIVED_ECC				       0x4881 */
+ /*#define SDRAM_CALCULATED_ECC					0x48c1 */
+ /*#define SDRAM_ECC_CONTROL					0x4941 */
+ /*#define SDRAM_ECC_ERROR_COUNTER			0x4981 */
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+#define DFCDL_CONFIG0						0x1480
+#define DFCDL_CONFIG1						0x1484
+#define DLL_WRITE						0x1488
+#define DLL_READ						0x148c
+#define SRAM_ADDR						0x1490
+#define SRAM_DATA0						0x1494
+#define SRAM_DATA1						0x1498
+#define SRAM_DATA2						0x149c
+#define DFCL_PROBE						0x14a0
+
+
+/****************************************/
+/* SDRAM Parameters only in MV64260			*/
+/****************************************/
+
+ /*#define SDRAM_BANK0PARAMETERS				0x44C	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_BANK1PARAMETERS				0x450	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_BANK2PARAMETERS				0x454	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_BANK3PARAMETERS				0x458	eliminated in MV64360 and MV64460 */
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define DUNIT_DEBUG_LOW						0x1460
+#define DUNIT_DEBUG_HIGH					0x1464
+#define DUNIT_MMASK						0x1b40
+
+/****************************************/
+/* SDunit Debug (for internal use)	*/
+/****************************************/
+
+#define X0_ADDRESS					    0x500
+#define X0_COMMAND_AND_ID				    0x504
+#define X0_WRITE_DATA_LOW				    0x508
+#define X0_WRITE_DATA_HIGH				    0x50c
+#define X0_WRITE_BYTE_ENABLE				    0x518
+#define X0_READ_DATA_LOW				    0x510
+#define X0_READ_DATA_HIGH				    0x514
+#define X0_READ_ID					    0x51c
+#define X1_ADDRESS					    0x520
+#define X1_COMMAND_AND_ID				    0x524
+#define X1_WRITE_DATA_LOW				    0x528
+#define X1_WRITE_DATA_HIGH				    0x52c
+#define X1_WRITE_BYTE_ENABLE				    0x538
+#define X1_READ_DATA_LOW				    0x530
+#define X1_READ_DATA_HIGH				    0x534
+#define X1_READ_ID					    0x53c
+#define X0_SNOOP_ADDRESS				    0x540
+#define X0_SNOOP_COMMAND				    0x544
+#define X1_SNOOP_ADDRESS				    0x548
+#define X1_SNOOP_COMMAND				    0x54c
+
+/****************************************/
+/* Device Parameters					*/
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS				0x45c
+#define DEVICE_BANK1PARAMETERS				0x460
+#define DEVICE_BANK2PARAMETERS				0x464
+#define DEVICE_BANK3PARAMETERS				0x468
+#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
+#define DEVICE_CONTROL							0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW				0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH				0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT				0x4c4
+
+/****************************************/
+/* Device Parameters					*/
+/****************************************/
+
+#define DEVICE_BANK0_PARAMETERS			DEVICE_BANK0PARAMETERS	/* 0x45c1 */
+#define DEVICE_BANK1_PARAMETERS			DEVICE_BANK1PARAMETERS	/* 0x4601 */
+#define DEVICE_BANK2_PARAMETERS			DEVICE_BANK2PARAMETERS	/* 0x4641 */
+#define DEVICE_BANK3_PARAMETERS			DEVICE_BANK3PARAMETERS	/* 0x4681 */
+/*#define DEVICE_BOOT_BANK_PARAMETERS			 0x46c1 */
+#define DEVICE_INTERFACE_CONTROL				DEVICE_CONTROL	/* 0x4c01 */
+#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		DEVICE_CROSS_BAR_CONTROL_LOW  /* 0x4c81 */
+#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		DEVICE_CROSS_BAR_CONTROL_HIGH  /* 0x4cc1 */
+#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT			DEVICE_CROSS_BAR_TIMEOUT  /* 0x4c41 */
+
+
+/****************************************/
+/* Device Interrupt					*/
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE						0x4d0
+#define DEVICE_INTERRUPT_MASK						0x4d4
+#define DEVICE_ERROR_ADDRESS						0x4d8
+ /*#define DEVICE_INTERRUPT_CAUSE				0x4d01 */
+ /*#define DEVICE_INTERRUPT_MASK				0x4d41 */
+#define DEVICE_ERROR_ADDR				DEVICE_ERROR_ADDRESS  /*0x4d81 */
+#define DEVICE_ERROR_DATA				0x4dc
+#define DEVICE_ERROR_PARITY					0x4e0
+
+/****************************************/
+/* Device debug registers			*/
+/****************************************/
+
+#define DEVICE_DEBUG_LOW					0x4e4
+#define DEVICE_DEBUG_HIGH				0x4e8
+#define RUNIT_MMASK							0x4f0
+
+/****************************************/
+/* DMA Record							*/
+/****************************************/
+
+ /*#define CHANNEL4_DMA_BYTE_COUNT			0x9001 */
+ /*#define CHANNEL5_DMA_BYTE_COUNT			0x9041 */
+ /*#define CHANNEL6_DMA_BYTE_COUNT			0x9081 */
+ /*#define CHANNEL7_DMA_BYTE_COUNT			0x90C1 */
+ /*#define CHANNEL4_DMA_SOURCE_ADDRESS		0x9101 */
+ /*#define CHANNEL5_DMA_SOURCE_ADDRESS		0x9141 */
+ /*#define CHANNEL6_DMA_SOURCE_ADDRESS		0x9181 */
+ /*#define CHANNEL7_DMA_SOURCE_ADDRESS		0x91C1 */
+ /*#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x9201 */
+ /*#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x9241 */
+ /*#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x9281 */
+ /*#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C1 */
+ /*#define CHANNEL4NEXT_RECORD_POINTER			0x9301 */
+ /*#define CHANNEL5NEXT_RECORD_POINTER			0x9341 */
+ /*#define CHANNEL6NEXT_RECORD_POINTER			0x9381 */
+ /*#define CHANNEL7NEXT_RECORD_POINTER			0x93C1 */
+ /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x9701 */
+ /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x9741 */
+ /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x9781 */
+ /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C1 */
+ /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8901 */
+ /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8941 */
+ /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8981 */
+ /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x89c1 */
+ /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9901 */
+ /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9941 */
+ /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9981 */
+ /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x99c1 */
+ /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a01 */
+ /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a41 */
+ /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a81 */
+ /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8ac1 */
+ /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a01 */
+ /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a41 */
+ /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a81 */
+ /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9ac1 */
+ /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b01 */
+ /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b41 */
+ /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b81 */
+ /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc1 */
+ /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b01 */
+ /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b41 */
+ /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b81 */
+ /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc1 */
+
+/****************************************/
+/* DMA Channel Control					*/
+/****************************************/
+
+#define CHANNEL0CONTROL					0x840
+#define CHANNEL0CONTROL_HIGH				0x880
+#define CHANNEL1CONTROL					0x844
+#define CHANNEL1CONTROL_HIGH				0x884
+#define CHANNEL2CONTROL					0x848
+#define CHANNEL2CONTROL_HIGH				0x888
+#define CHANNEL3CONTROL					0x84C
+#define CHANNEL3CONTROL_HIGH				0x88C
+
+#define DMA_CHANNEL0_CONTROL				CHANNEL0CONTROL	 /*0x8401 */
+#define DMA_CHANNEL0_CONTROL_HIGH			CHANNEL0CONTROL_HIGH  /*0x8801 */
+#define DMA_CHANNEL1_CONTROL				CHANNEL1CONTROL	 /* 0x8441 */
+#define DMA_CHANNEL1_CONTROL_HIGH			CHANNEL1CONTROL_HIGH  /*0x8841 */
+#define DMA_CHANNEL2_CONTROL				CHANNEL2CONTROL	 /*0x8481 */
+#define DMA_CHANNEL2_CONTROL_HIGH			CHANNEL2CONTROL_HIGH  /*0x8881 */
+#define DMA_CHANNEL3_CONTROL				CHANNEL3CONTROL	 /*0x84C1 */
+#define DMA_CHANNEL3_CONTROL_HIGH			CHANNEL3CONTROL_HIGH  /*0x88C1 */
+
+ /*#define CHANNEL4CONTROL				0x9401 */
+ /*#define CHANNEL4CONTROL_HIGH				0x9801 */
+ /*#define CHANNEL5CONTROL				0x9441 */
+ /*#define CHANNEL5CONTROL_HIGH				0x9841 */
+ /*#define CHANNEL6CONTROL				0x9481 */
+ /*#define CHANNEL6CONTROL_HIGH				0x9881 */
+ /*#define CHANNEL7CONTROL				0x94C1 */
+ /*#define CHANNEL7CONTROL_HIGH				0x98C1 */
+
+
+/****************************************/
+/* DMA Arbiter							*/
+/****************************************/
+
+ /*#define ARBITER_CONTROL_0_3				0x8601 */
+#define ARBITER_CONTROL_4_7				0x960
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define DMA_CHANNEL0_BYTE_COUNT					CHANNEL0_DMA_BYTE_COUNT	 /*0x8001 */
+#define DMA_CHANNEL1_BYTE_COUNT					CHANNEL1_DMA_BYTE_COUNT	 /*0x8041 */
+#define DMA_CHANNEL2_BYTE_COUNT					CHANNEL2_DMA_BYTE_COUNT	 /*0x8081 */
+#define DMA_CHANNEL3_BYTE_COUNT					CHANNEL3_DMA_BYTE_COUNT	 /*0x80C1 */
+#define DMA_CHANNEL0_SOURCE_ADDR				CHANNEL0_DMA_SOURCE_ADDRESS  /*0x8101 */
+#define DMA_CHANNEL1_SOURCE_ADDR				CHANNEL1_DMA_SOURCE_ADDRESS  /*0x8141 */
+#define DMA_CHANNEL2_SOURCE_ADDR				CHANNEL2_DMA_SOURCE_ADDRESS  /*0x8181 */
+#define DMA_CHANNEL3_SOURCE_ADDR				CHANNEL3_DMA_SOURCE_ADDRESS  /*0x81c1 */
+#define DMA_CHANNEL0_DESTINATION_ADDR				CHANNEL0_DMA_DESTINATION_ADDRESS  /*0x8201 */
+#define DMA_CHANNEL1_DESTINATION_ADDR				CHANNEL1_DMA_DESTINATION_ADDRESS  /*0x8241 */
+#define DMA_CHANNEL2_DESTINATION_ADDR				CHANNEL2_DMA_DESTINATION_ADDRESS  /*0x8281 */
+#define DMA_CHANNEL3_DESTINATION_ADDR				CHANNEL3_DMA_DESTINATION_ADDRESS  /*0x82C1 */
+#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		CHANNEL0NEXT_RECORD_POINTER  /*0x8301 */
+#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		CHANNEL1NEXT_RECORD_POINTER  /*0x8341 */
+#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		CHANNEL2NEXT_RECORD_POINTER  /*0x8381 */
+#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		CHANNEL3NEXT_RECORD_POINTER  /*0x83C1 */
+#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		CHANNEL0CURRENT_DESCRIPTOR_POINTER  /*0x8701 */
+#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		CHANNEL1CURRENT_DESCRIPTOR_POINTER  /*0x8741 */
+#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		CHANNEL2CURRENT_DESCRIPTOR_POINTER  /*0x8781 */
+#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		CHANNEL3CURRENT_DESCRIPTOR_POINTER  /*0x87C1 */
+
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
+#define CHANNEL0NEXT_RECORD_POINTER			0x830
+#define CHANNEL1NEXT_RECORD_POINTER			0x834
+#define CHANNEL2NEXT_RECORD_POINTER			0x838
+#define CHANNEL3NEXT_RECORD_POINTER			0x83C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
+#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
+#define CHANNEL0_DMA_BYTE_COUNT			0x800
+#define CHANNEL1_DMA_BYTE_COUNT			0x804
+#define CHANNEL2_DMA_BYTE_COUNT			0x808
+#define CHANNEL3_DMA_BYTE_COUNT			0x80C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define DMA_BASE_ADDR_REG0						0xa00
+#define DMA_BASE_ADDR_REG1						0xa08
+#define DMA_BASE_ADDR_REG2						0xa10
+#define DMA_BASE_ADDR_REG3						0xa18
+#define DMA_BASE_ADDR_REG4						0xa20
+#define DMA_BASE_ADDR_REG5						0xa28
+#define DMA_BASE_ADDR_REG6						0xa30
+#define DMA_BASE_ADDR_REG7						0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define DMA_SIZE_REG0							0xa04
+#define DMA_SIZE_REG1							0xa0c
+#define DMA_SIZE_REG2							0xa14
+#define DMA_SIZE_REG3							0xa1c
+#define DMA_SIZE_REG4							0xa24
+#define DMA_SIZE_REG5							0xa2c
+#define DMA_SIZE_REG6							0xa34
+#define DMA_SIZE_REG7							0xa3C
+
+    /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define DMA_HIGH_ADDR_REMAP_REG0				0xa60
+#define DMA_HIGH_ADDR_REMAP_REG1				0xa64
+#define DMA_HIGH_ADDR_REMAP_REG2				0xa68
+#define DMA_HIGH_ADDR_REMAP_REG3				0xa6C
+#define DMA_BASE_ADDR_ENABLE_REG				0xa80
+#define DMA_CHANNEL0_ACCESS_PROTECTION_REG		0xa70
+#define DMA_CHANNEL1_ACCESS_PROTECTION_REG		   0xa74
+#define DMA_CHANNEL2_ACCESS_PROTECTION_REG		   0xa78
+#define DMA_CHANNEL3_ACCESS_PROTECTION_REG		   0xa7c
+#define DMA_ARBITER_CONTROL						0x860
+#define DMA_CROSS_BAR_TIMEOUT					0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+ /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL			0x3e01 */
+ /*#define CPU_IDMA_HEADERS_RETARGET_BASE			 0x3e81 */
+
+#define DMA_HEADERS_RETARGET_CONTROL			0xa84
+#define DMA_HEADERS_RETARGET_BASE			0xa88
+
+/****************************************/
+/* DMA Interrupt						*/
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE			0x8c0
+#define CHANELS0_3_INTERRUPT_MASK			0x8c4
+#define CHANELS0_3_ERROR_ADDRESS			0x8c8
+#define CHANELS0_3_ERROR_SELECT				0x8cc
+ /*#define CHANELS4_7_INTERRUPT_CAUSE			0x9c01 */
+ /*#define CHANELS4_7_INTERRUPT_MASK			0x9c41 */
+ /*#define CHANELS4_7_ERROR_ADDRESS			0x9c81 */
+ /*#define CHANELS4_7_ERROR_SELECT			0x9cc1 */
+
+#define DMA_INTERRUPT_CAUSE_REG				CHANELS0_3_INTERRUPT_CAUSE  /*0x8c01 */
+#define DMA_INTERRUPT_CAUSE_MASK			CHANELS0_3_INTERRUPT_MASK  /*0x8c41 */
+#define DMA_ERROR_ADDR						CHANELS0_3_ERROR_ADDRESS  /*0x8c81 */
+#define DMA_ERROR_SELECT					CHANELS0_3_ERROR_SELECT	 /*0x8cc1 */
+
+
+/****************************************/
+/* DMA Debug (for internal use)		*/
+/****************************************/
+
+#define DMA_X0_ADDRESS						0x8e0
+#define DMA_X0_COMMAND_AND_ID				0x8e4
+ /*#define DMA_X0_WRITE_DATA_LOW				0x8e81 */
+ /*#define DMA_X0_WRITE_DATA_HIGH				0x8ec1 */
+ /*#define DMA_X0_WRITE_BYTE_ENABLE				0x8f81 */
+ /*#define DMA_X0_READ_DATA_LOW					0x8f01 */
+ /*#define DMA_X0_READ_DATA_HIGH				0x8f41 */
+ /*#define DMA_X0_READ_ID					0x8fc1 */
+ /*#define DMA_X1_ADDRESS					0x9e01 */
+ /*#define DMA_X1_COMMAND_AND_ID			0x9e41 */
+ /*#define DMA_X1_WRITE_DATA_LOW				0x9e81 */
+ /*#define DMA_X1_WRITE_DATA_HIGH				0x9ec1 */
+ /*#define DMA_X1_WRITE_BYTE_ENABLE				0x9f81 */
+ /*#define DMA_X1_READ_DATA_LOW					0x9f01 */
+ /*#define DMA_X1_READ_DATA_HIGH				0x9f41 */
+ /*#define DMA_X1_READ_ID					0x9fc1 */
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define DMA_DEBUG_LOW						DMA_X0_ADDRESS	/* 0x8e01 */
+#define DMA_DEBUG_HIGH						DMA_X0_COMMAND_AND_ID  /*0x8e41 */
+#define DMA_SPARE						0xA8C
+
+
+/****************************************/
+/* Timer_Counter						*/
+/****************************************/
+
+#define TIMER_COUNTER0					0x850
+#define TIMER_COUNTER1					0x854
+#define TIMER_COUNTER2					0x858
+#define TIMER_COUNTER3					0x85C
+#define TIMER_COUNTER_0_3_CONTROL			0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK		0x86c
+ /*#define TIMER_COUNTER4					0x9501 */
+ /*#define TIMER_COUNTER5					0x9541 */
+ /*#define TIMER_COUNTER6					0x9581 */
+ /*#define TIMER_COUNTER7					0x95C1 */
+ /*#define TIMER_COUNTER_4_7_CONTROL			0x9641 */
+ /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x9681 */
+ /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK			0x96c1 */
+
+/****************************************/
+/* PCI Slave Address Decoding		*/
+/****************************************/
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+#define PCI_0_CS_0_BANK_SIZE					PCI_0SCS_0_BANK_SIZE  /*0xc081 */
+#define PCI_1_CS_0_BANK_SIZE					PCI_1SCS_0_BANK_SIZE  /* 0xc881 */
+#define PCI_0_CS_1_BANK_SIZE					PCI_0SCS_1_BANK_SIZE  /*0xd081 */
+#define PCI_1_CS_1_BANK_SIZE					PCI_1SCS_1_BANK_SIZE  /* 0xd881 */
+#define PCI_0_CS_2_BANK_SIZE					PCI_0SCS_2_BANK_SIZE  /*0xc0c1 */
+#define PCI_1_CS_2_BANK_SIZE					PCI_1SCS_2_BANK_SIZE  /*0xc8c1 */
+#define PCI_0_CS_3_BANK_SIZE					PCI_0SCS_3_BANK_SIZE  /*0xd0c1 */
+#define PCI_1_CS_3_BANK_SIZE					PCI_1SCS_3_BANK_SIZE  /*0xd8c1 */
+#define PCI_0_DEVCS_0_BANK_SIZE					PCI_0CS_0_BANK_SIZE  /*0xc101 */
+#define PCI_1_DEVCS_0_BANK_SIZE				    PCI_1CS_0_BANK_SIZE	 /*0xc901 */
+#define PCI_0_DEVCS_1_BANK_SIZE				    PCI_0CS_1_BANK_SIZE	 /*0xd101 */
+#define PCI_1_DEVCS_1_BANK_SIZE				    PCI_1CS_1_BANK_SIZE	 /* 0xd901 */
+#define PCI_0_DEVCS_2_BANK_SIZE				    PCI_0CS_2_BANK_SIZE	 /* 0xd181 */
+#define PCI_1_DEVCS_2_BANK_SIZE				    PCI_1CS_2_BANK_SIZE	 /*0xd981 */
+#define PCI_0_DEVCS_3_BANK_SIZE				    PCI_0CS_3_BANK_SIZE	 /* 0xc141 */
+#define PCI_1_DEVCS_3_BANK_SIZE				    PCI_1CS_3_BANK_SIZE	 /*0xc941 */
+#define PCI_0_DEVCS_BOOT_BANK_SIZE			PCI_0CS_BOOT_BANK_SIZE	/*0xd141 */
+#define PCI_1_DEVCS_BOOT_BANK_SIZE			PCI_1CS_BOOT_BANK_SIZE	/* 0xd941 */
+#define PCI_0_P2P_MEM0_BAR_SIZE				    PCI_0P2P_MEM0_BAR_SIZE  /*0xd1c1 */
+#define PCI_1_P2P_MEM0_BAR_SIZE				    PCI_1P2P_MEM0_BAR_SIZE  /*0xd9c1 */
+#define PCI_0_P2P_MEM1_BAR_SIZE				    PCI_0P2P_MEM1_BAR_SIZE  /*0xd201 */
+#define PCI_1_P2P_MEM1_BAR_SIZE				    PCI_1P2P_MEM1_BAR_SIZE  /*0xda01 */
+#define PCI_0_P2P_I_O_BAR_SIZE					PCI_0P2P_I_O_BAR_SIZE  /*0xd241 */
+#define PCI_1_P2P_I_O_BAR_SIZE					PCI_1P2P_I_O_BAR_SIZE  /*0xda41 */
+#define PCI_0_CPU_BAR_SIZE					PCI_0CPU_BAR_SIZE  /*0xd281 */
+#define PCI_1_CPU_BAR_SIZE					PCI_1CPU_BAR_SIZE  /*0xda81 */
+#define PCI_0_INTERNAL_SRAM_BAR_SIZE			PCI_0DAC_SCS_0_BANK_SIZE  /*0xe001 */
+#define PCI_1_INTERNAL_SRAM_BAR_SIZE			PCI_1DAC_SCS_0_BANK_SIZE  /*0xe801 */
+#define PCI_0_EXPANSION_ROM_BAR_SIZE			PCI_0EXPANSION_ROM_BAR_SIZE  /*0xd2c1 */
+#define PCI_1_EXPANSION_ROM_BAR_SIZE		       PCI_1EXPANSION_ROM_BAR_SIZE  /*0xd9c1 */
+#define PCI_0_BASE_ADDR_REG_ENABLE			PCI_0BASE_ADDRESS_REGISTERS_ENABLE  /*0xc3c1 */
+#define PCI_1_BASE_ADDR_REG_ENABLE			PCI_1BASE_ADDRESS_REGISTERS_ENABLE  /*0xcbc1 */
+#define PCI_0_CS_0_BASE_ADDR_REMAP		PCI_0SCS_0_BASE_ADDRESS_REMAP  /*0xc481 */
+#define PCI_1_CS_0_BASE_ADDR_REMAP		PCI_1SCS_0_BASE_ADDRESS_REMAP  /*0xcc81 */
+#define PCI_0_CS_1_BASE_ADDR_REMAP		PCI_0SCS_1_BASE_ADDRESS_REMAP  /*0xd481 */
+#define PCI_1_CS_1_BASE_ADDR_REMAP		PCI_1SCS_1_BASE_ADDRESS_REMAP  /*0xdc81 */
+#define PCI_0_CS_2_BASE_ADDR_REMAP		PCI_0SCS_2_BASE_ADDRESS_REMAP  /*0xc4c1 */
+#define PCI_1_CS_2_BASE_ADDR_REMAP		PCI_1SCS_2_BASE_ADDRESS_REMAP  /*0xccc1 */
+#define PCI_0_CS_3_BASE_ADDR_REMAP		PCI_0SCS_3_BASE_ADDRESS_REMAP  /*0xd4c1 */
+#define PCI_1_CS_3_BASE_ADDR_REMAP		PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */
+#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP
+#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP
+#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP
+#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP
+#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP
+#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP
+#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP
+#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP
+#define PCI_0_DEVCS_0_BASE_ADDR_REMAP		PCI_0CS_0_BASE_ADDRESS_REMAP  /*0xc501 */
+#define PCI_1_DEVCS_0_BASE_ADDR_REMAP		PCI_1CS_0_BASE_ADDRESS_REMAP  /*0xcd01 */
+#define PCI_0_DEVCS_1_BASE_ADDR_REMAP		PCI_0CS_1_BASE_ADDRESS_REMAP  /*0xd501 */
+#define PCI_1_DEVCS_1_BASE_ADDR_REMAP		PCI_1CS_1_BASE_ADDRESS_REMAP  /*0xdd01 */
+#define PCI_0_DEVCS_2_BASE_ADDR_REMAP		PCI_0CS_2_BASE_ADDRESS_REMAP  /*0xd581 */
+#define PCI_1_DEVCS_2_BASE_ADDR_REMAP		PCI_1CS_2_BASE_ADDRESS_REMAP  /*0xdd81 */
+#define PCI_0_DEVCS_3_BASE_ADDR_REMAP			PCI_0CS_3_BASE_ADDRESS_REMAP  /*0xc541 */
+#define PCI_1_DEVCS_3_BASE_ADDR_REMAP			PCI_1CS_3_BASE_ADDRESS_REMAP  /*0xcd41 */
+#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	 /*0xd541 */
+#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	 /*0xdd41 */
+#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xd5c1 */
+#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xddc1 */
+#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xd601 */
+#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xde01 */
+#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW	PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xd641 */
+#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW	PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xde41 */
+#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH	PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xd681 */
+#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH	PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xde81 */
+#define PCI_0_P2P_I_O_BASE_ADDR_REMAP			PCI_0P2P_I_O_BASE_ADDRESS_REMAP	 /*0xd6c1 */
+#define PCI_1_P2P_I_O_BASE_ADDR_REMAP			PCI_1P2P_I_O_BASE_ADDRESS_REMAP	 /*0xdec 1 */
+#define PCI_0_CPU_BASE_ADDR_REMAP_LOW			PCI_0CPU_BASE_ADDRESS_REMAP  /*0xd701 */
+#define PCI_1_CPU_BASE_ADDR_REMAP_LOW			PCI_1CPU_BASE_ADDRESS_REMAP  /*0xdf01 */
+#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH			0xd74
+#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH			0xdf4
+#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		  PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP  /*0xf001 */
+#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		  0xf80
+#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		   PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xf381 */
+#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		   PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xfb81 */
+#define PCI_0_ADDR_DECODE_CONTROL				PCI_0ADDRESS_DECODE_CONTROL  /*0xd3c1 */
+#define PCI_1_ADDR_DECODE_CONTROL				PCI_1ADDRESS_DECODE_CONTROL  /*0xdbc1 */
+#define PCI_0_HEADERS_RETARGET_CONTROL			0xF40
+#define PCI_1_HEADERS_RETARGET_CONTROL				0xFc0
+#define PCI_0_HEADERS_RETARGET_BASE				0xF44
+#define PCI_1_HEADERS_RETARGET_BASE				0xFc4
+#define PCI_0_HEADERS_RETARGET_HIGH				0xF48
+#define PCI_1_HEADERS_RETARGET_HIGH				0xFc8
+
+#define PCI_0SCS_0_BANK_SIZE				0xc08
+#define PCI_1SCS_0_BANK_SIZE				0xc88
+#define PCI_0SCS_1_BANK_SIZE				0xd08
+#define PCI_1SCS_1_BANK_SIZE				0xd88
+#define PCI_0SCS_2_BANK_SIZE				0xc0c
+#define PCI_1SCS_2_BANK_SIZE				0xc8c
+#define PCI_0SCS_3_BANK_SIZE				0xd0c
+#define PCI_1SCS_3_BANK_SIZE				0xd8c
+#define PCI_0CS_0_BANK_SIZE				0xc10
+#define PCI_1CS_0_BANK_SIZE				0xc90
+#define PCI_0CS_1_BANK_SIZE				0xd10
+#define PCI_1CS_1_BANK_SIZE				0xd90
+#define PCI_0CS_2_BANK_SIZE				0xd18
+#define PCI_1CS_2_BANK_SIZE				0xd98
+#define PCI_0CS_3_BANK_SIZE				0xc14
+#define PCI_1CS_3_BANK_SIZE				0xc94
+#define PCI_0CS_BOOT_BANK_SIZE				0xd14
+#define PCI_1CS_BOOT_BANK_SIZE				0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE						0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE						0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE						0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE						0xda0
+#define PCI_0P2P_I_O_BAR_SIZE						0xd24
+#define PCI_1P2P_I_O_BAR_SIZE						0xda4
+#define PCI_0CPU_BAR_SIZE						0xd28
+#define PCI_1CPU_BAR_SIZE						0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE				0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE				0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE				0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE				0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE				0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE				0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE				0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE				0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE					0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE					0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE					0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE					0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE					0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE					0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE					0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE					0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE				0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE				0xea0
+
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE				0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE				0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE				0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE				0xea8
+#define PCI_0DAC_CPU_BAR_SIZE						0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE						0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE				0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE				0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE		0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE		0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP			0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP			0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW		  0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		  0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		  0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW		 0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW		 0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		 0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		 0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP				0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP				0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP				0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP				0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP			0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP			0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP			0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP			0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP			0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP			0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP			0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP			0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP			0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP			0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP			0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP			0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP			0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP			0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP			0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP			0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP			0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP		    0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW     0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP				0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP				0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP			0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP			0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL				0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL				0xdbc
+
+/****************************************/
+/* PCI Control				*/
+/****************************************/
+
+#define PCI_0COMMAND										0xc00
+#define PCI_1COMMAND										0xc80
+#define PCI_0MODE					    0xd00
+#define PCI_1MODE					    0xd80
+#define PCI_0TIMEOUT_RETRY									0xc04
+#define PCI_1TIMEOUT_RETRY									0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER			    0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MSI_0TRIGGER_TIMER				    0xc38
+#define MSI_1TRIGGER_TIMER				    0xcb8
+#define PCI_0ARBITER_CONTROL				    0x1d00
+#define PCI_1ARBITER_CONTROL				    0x1d80
+/* changing untill here */
+#define PCI_0CROSS_BAR_CONTROL_LOW			     0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH			     0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT				     0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	     0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	     0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER		     0x1d10
+#define PCI_0P2P_CONFIGURATION				     0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW			     0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH			     0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0			     0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW			     0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH			     0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1			     0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW			     0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH			     0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2			     0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW			     0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH			     0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3			     0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW			     0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH			     0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4			     0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW			     0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH			     0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5			     0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW			     0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH			     0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6			     0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW			     0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH			     0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7			     0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW			     0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH			     0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT				     0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	     0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	     0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER		     0x1d90
+#define PCI_1P2P_CONFIGURATION				     0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW			     0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH			     0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0			     0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW			     0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH			     0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1			     0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW			     0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH			     0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2			     0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW			     0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH			     0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3			     0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW			     0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH			     0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4			     0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW			     0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH			     0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5			     0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW			     0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH			     0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6			     0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW			     0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH			     0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7			     0x1ef8
+
+/****************************************/
+/* PCI Snoop Control			*/
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW			     0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH			     0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0			     0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW			     0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH		     0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1			     0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW			     0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH		     0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2			     0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW			     0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH		     0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3			     0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW			     0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH			     0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0			     0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW			     0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH		     0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1			     0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW			     0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH		     0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2			     0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW			     0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH		     0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3			     0x1fb8
+
+/****************************************/
+/* PCI Configuration Address		*/
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS							0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER		0xcfc
+#define PCI_1CONFIGURATION_ADDRESS							0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER		0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xcb4
+
+/****************************************/
+/* PCI Error Report			*/
+/****************************************/
+
+#define PCI_0SERR_MASK										 0xc28
+#define PCI_0ERROR_ADDRESS_LOW				     0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH				     0x1d44
+#define PCI_0ERROR_DATA_LOW				     0x1d48
+#define PCI_0ERROR_DATA_HIGH				     0x1d4c
+#define PCI_0ERROR_COMMAND				     0x1d50
+#define PCI_0ERROR_CAUSE				     0x1d58
+#define PCI_0ERROR_MASK					     0x1d5c
+#define PCI_1SERR_MASK										 0xca8
+#define PCI_1ERROR_ADDRESS_LOW				     0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH				     0x1dc4
+#define PCI_1ERROR_DATA_LOW				     0x1dc8
+#define PCI_1ERROR_DATA_HIGH				     0x1dcc
+#define PCI_1ERROR_COMMAND				     0x1dd0
+#define PCI_1ERROR_CAUSE				     0x1dd8
+#define PCI_1ERROR_MASK					     0x1ddc
+
+
+/****************************************/
+/* Lslave Debug	 (for internal use)	*/
+/****************************************/
+
+#define L_SLAVE_X0_ADDRESS				    0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID			    0x1d24
+#define L_SLAVE_X1_ADDRESS				    0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID			    0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW				    0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH				    0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE			    0x1d60
+#define L_SLAVE_READ_DATA_LOW				    0x1d38
+#define L_SLAVE_READ_DATA_HIGH				    0x1d3c
+#define L_SLAVE_READ_ID					    0x1d64
+
+/****************************************/
+/* PCI Configuration Function 0		*/
+/****************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID							0x000
+#define PCI_STATUS_AND_COMMAND								0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID					0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
+#define PCI_SCS_0_BASE_ADDRESS							0x010
+#define PCI_SCS_1_BASE_ADDRESS							    0x014
+#define PCI_SCS_2_BASE_ADDRESS							    0x018
+#define PCI_SCS_3_BASE_ADDRESS							0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID			0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER				0x030
+#define PCI_CAPABILTY_LIST_POINTER			    0x034
+#define PCI_INTERRUPT_PIN_AND_LINE						    0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define PCI_VPD_ADDRESS					    0x048
+#define PCI_VPD_DATA					    0x04c
+#define PCI_MSI_MESSAGE_CONTROL				    0x050
+#define PCI_MSI_MESSAGE_ADDRESS				    0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS			    0x058
+#define PCI_MSI_MESSAGE_DATA				    0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY		    0x058
+
+/****************************************/
+/* PCI Configuration Function 1		*/
+/****************************************/
+
+#define PCI_CS_0_BASE_ADDRESS							0x110
+#define PCI_CS_1_BASE_ADDRESS							    0x114
+#define PCI_CS_2_BASE_ADDRESS							    0x118
+#define PCI_CS_3_BASE_ADDRESS							0x11c
+#define PCI_BOOTCS_BASE_ADDRESS				    0x120
+
+/****************************************/
+/* PCI Configuration Function 2		*/
+/****************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDRESS						0x210
+ /*#define PCI_P2P_MEM1_BASE_ADDRESS							0x2141 */
+#define PCI_P2P_I_O_BASE_ADDRESS							0x218
+ /*#define PCI_CPU_BASE_ADDRESS							    0x21c1 */
+
+/****************************************/
+/* PCI Configuration Function 4		*/
+/****************************************/
+
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW						0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH					    0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW					    0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH					    0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW		    0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH		    0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5		*/
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW						0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH					    0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW					    0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH					    0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW		    0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH		    0x524
+
+
+/****************************************/
+/* PCI Configuration Function 6		*/
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW						0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH					    0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW					    0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH					    0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW				0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH				0x624
+
+/****************************************/
+/* PCI Configuration Function 7		*/
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW						0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH					    0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW					    0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH				    0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW				0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH				0x724
+
+/****************************** MV64360 and MV64460 PCI ***************************/
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define PCI_0_DLL_STATUS_AND_COMMAND				0x1d20
+#define PCI_1_DLL_STATUS_AND_COMMAND				0x1da0
+#define PCI_0_MPP_PADS_DRIVE_CONTROL				0x1d1C
+#define PCI_1_MPP_PADS_DRIVE_CONTROL				0x1d9C
+#define PCI_0_COMMAND					0xc00
+#define PCI_1_COMMAND					0xc80
+#define PCI_0_MODE							0xd00
+#define PCI_1_MODE							0xd80
+#define PCI_0_RETRY						0xc04
+#define PCI_1_RETRY						0xc84
+#define PCI_0_READ_BUFFER_DISCARD_TIMER				0xd04
+#define PCI_1_READ_BUFFER_DISCARD_TIMER				0xd84
+#define PCI_0_MSI_TRIGGER_TIMER						0xc38
+#define PCI_1_MSI_TRIGGER_TIMER						0xcb8
+#define PCI_0_ARBITER_CONTROL						0x1d00
+#define PCI_1_ARBITER_CONTROL						0x1d80
+#define PCI_0_CROSS_BAR_CONTROL_LOW				0x1d08
+#define PCI_1_CROSS_BAR_CONTROL_LOW				0x1d88
+#define PCI_0_CROSS_BAR_CONTROL_HIGH				0x1d0c
+#define PCI_1_CROSS_BAR_CONTROL_HIGH				0x1d8c
+#define PCI_0_CROSS_BAR_TIMEOUT					0x1d04
+#define PCI_1_CROSS_BAR_TIMEOUT					0x1d84
+#define PCI_0_SYNC_BARRIER_TRIGGER_REG				0x1D18
+#define PCI_1_SYNC_BARRIER_TRIGGER_REG				0x1D98
+#define PCI_0_SYNC_BARRIER_VIRTUAL_REG				0x1d10
+#define PCI_1_SYNC_BARRIER_VIRTUAL_REG				0x1d90
+#define PCI_0_P2P_CONFIG						0x1d14
+#define PCI_1_P2P_CONFIG						0x1d94
+
+#define PCI_0_ACCESS_CONTROL_BASE_0_LOW				0x1e00
+#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH			0x1e04
+#define PCI_0_ACCESS_CONTROL_SIZE_0				0x1e08
+#define PCI_0_ACCESS_CONTROL_BASE_1_LOW				0x1e10
+#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH			0x1e14
+#define PCI_0_ACCESS_CONTROL_SIZE_1				0x1e18
+#define PCI_0_ACCESS_CONTROL_BASE_2_LOW				0x1e20
+#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH			0x1e24
+#define PCI_0_ACCESS_CONTROL_SIZE_2				0x1e28
+#define PCI_0_ACCESS_CONTROL_BASE_3_LOW				0x1e30
+#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH			0x1e34
+#define PCI_0_ACCESS_CONTROL_SIZE_3				0x1e38
+#define PCI_0_ACCESS_CONTROL_BASE_4_LOW				0x1e40
+#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH			0x1e44
+#define PCI_0_ACCESS_CONTROL_SIZE_4				0x1e48
+#define PCI_0_ACCESS_CONTROL_BASE_5_LOW				0x1e50
+#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH			0x1e54
+#define PCI_0_ACCESS_CONTROL_SIZE_5				0x1e58
+
+#define PCI_1_ACCESS_CONTROL_BASE_0_LOW				0x1e80
+#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH			0x1e84
+#define PCI_1_ACCESS_CONTROL_SIZE_0				0x1e88
+#define PCI_1_ACCESS_CONTROL_BASE_1_LOW				0x1e90
+#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH			0x1e94
+#define PCI_1_ACCESS_CONTROL_SIZE_1				0x1e98
+#define PCI_1_ACCESS_CONTROL_BASE_2_LOW				0x1ea0
+#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH			0x1ea4
+#define PCI_1_ACCESS_CONTROL_SIZE_2				0x1ea8
+#define PCI_1_ACCESS_CONTROL_BASE_3_LOW				0x1eb0
+#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH			0x1eb4
+#define PCI_1_ACCESS_CONTROL_SIZE_3				0x1eb8
+#define PCI_1_ACCESS_CONTROL_BASE_4_LOW				0x1ec0
+#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH			0x1ec4
+#define PCI_1_ACCESS_CONTROL_SIZE_4				0x1ec8
+#define PCI_1_ACCESS_CONTROL_BASE_5_LOW				0x1ed0
+#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH			0x1ed4
+#define PCI_1_ACCESS_CONTROL_SIZE_5				0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define PCI_0_CONFIG_ADDR				0xcf8
+#define PCI_0_CONFIG_DATA_VIRTUAL_REG				0xcfc
+#define PCI_1_CONFIG_ADDR				0xc78
+#define PCI_1_CONFIG_DATA_VIRTUAL_REG				0xc7c
+#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
+#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define PCI_0_SERR_MASK					0xc28
+#define PCI_1_SERR_MASK					0xca8
+#define PCI_0_ERROR_ADDR_LOW						0x1d40
+#define PCI_1_ERROR_ADDR_LOW						0x1dc0
+#define PCI_0_ERROR_ADDR_HIGH						0x1d44
+#define PCI_1_ERROR_ADDR_HIGH						0x1dc4
+#define PCI_0_ERROR_ATTRIBUTE						0x1d48
+#define PCI_1_ERROR_ATTRIBUTE						0x1dc8
+#define PCI_0_ERROR_COMMAND						0x1d50
+#define PCI_1_ERROR_COMMAND						0x1dd0
+#define PCI_0_ERROR_CAUSE						0x1d58
+#define PCI_1_ERROR_CAUSE						0x1dd8
+#define PCI_0_ERROR_MASK						0x1d5c
+#define PCI_1_ERROR_MASK						0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define PCI_0_MMASK							0X1D24
+#define PCI_1_MMASK							0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID			0x000
+#define PCI_STATUS_AND_COMMAND			0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID			0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
+
+#define PCI_SCS_0_BASE_ADDR_LOW				0x010
+#define PCI_SCS_0_BASE_ADDR_HIGH			0x014
+#define PCI_SCS_1_BASE_ADDR_LOW				0x018
+#define PCI_SCS_1_BASE_ADDR_HIGH			0x01C
+#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW    0x020
+#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH   0x024
+ /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02c1 */
+#define PCI_EXPANSION_ROM_BASE_ADDR_REG		0x030
+#define PCI_CAPABILTY_LIST_POINTER				0x034
+#define PCI_INTERRUPT_PIN_AND_LINE			0x03C
+       /* capability list */
+#define PCI_POWER_MANAGEMENT_CAPABILITY				0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	     0x044
+#define PCI_VPD_ADDR							0x048
+#define PCI_VPD_DATA							0x04c
+#define PCI_MSI_MESSAGE_CONTROL					0x050
+#define PCI_MSI_MESSAGE_ADDR						0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDR				0x058
+#define PCI_MSI_MESSAGE_DATA						0x05c
+#define PCI_X_COMMAND							0x060
+#define PCI_X_STATUS							0x064
+#define PCI_COMPACT_PCI_HOT_SWAP				0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define PCI_SCS_2_BASE_ADDR_LOW				0x110
+#define PCI_SCS_2_BASE_ADDR_HIGH			0x114
+#define PCI_SCS_3_BASE_ADDR_LOW				0x118
+#define PCI_SCS_3_BASE_ADDR_HIGH			0x11c
+#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW					0x120
+#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH				0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define PCI_DEVCS_0_BASE_ADDR_LOW			0x210
+#define PCI_DEVCS_0_BASE_ADDR_HIGH			0x214
+#define PCI_DEVCS_1_BASE_ADDR_LOW			0x218
+#define PCI_DEVCS_1_BASE_ADDR_HIGH				0x21c
+#define PCI_DEVCS_2_BASE_ADDR_LOW			0x220
+#define PCI_DEVCS_2_BASE_ADDR_HIGH				0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define PCI_DEVCS_3_BASE_ADDR_LOW			0x310
+#define PCI_DEVCS_3_BASE_ADDR_HIGH			0x314
+#define PCI_BOOT_CS_BASE_ADDR_LOW			0x318
+#define PCI_BOOT_CS_BASE_ADDR_HIGH				0x31c
+#define PCI_CPU_BASE_ADDR_LOW				0x220
+#define PCI_CPU_BASE_ADDR_HIGH				0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDR_LOW			0x410
+#define PCI_P2P_MEM0_BASE_ADDR_HIGH			0x414
+#define PCI_P2P_MEM1_BASE_ADDR_LOW			0x418
+#define PCI_P2P_MEM1_BASE_ADDR_HIGH			0x41c
+#define PCI_P2P_I_O_BASE_ADDR						0x420
+#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		  0x424
+
+/****************************** MV64360 and MV64460 PCI End ***************************/
+/****************************************/
+/* I20 Support registers				*/
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE		0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE		0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE				0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE			0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C7C
+
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE			0x010
+#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE				0x014
+#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE				0x018
+#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE				0x01C
+#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE				0x020
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE		0x024
+#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE			0x028
+#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE				0x02C
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE		0x030
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE		0x034
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE		0x040
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE		0x044
+#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE			0x050
+#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE			0x054
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE		0x060
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE		0x064
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE		0x068
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE		0x06C
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE		0x070
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE		0x074
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE		0x0F8
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE		0x0FC
+
+#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE			0x090
+#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE				0x094
+#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE				0x098
+#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE				0x09C
+#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE				0x0A0
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE		0x0A4
+#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE			0x0A8
+#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE				0x0AC
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE		0x0B0
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE		0x0B4
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE		0x0C0
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE		0x0C4
+#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE			0x0D0
+#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE			0x0D4
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE		0x0E0
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE		0x0E4
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE		0x0E8
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE		0x0EC
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE		0x0F0
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE		0x0F4
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE		0x078
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE		0x07C
+
+#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE			0x1C10
+#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE				0x1C14
+#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE				0x1C18
+#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE				0x1C1C
+#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE				0x1C20
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE			0x1C24
+#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE			0x1C28
+#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE				0x1C2C
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE		0x1C30
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE		0x1C34
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE		0x1C40
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE		0x1C44
+#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE				0x1C50
+#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE				0x1C54
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE		0x1C60
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE		0x1C64
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE		0x1C68
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE		0x1C6C
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE		0x1C70
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE		0x1C74
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE		0x1CF8
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE		0x1CFC
+#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE			0x1C90
+#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE				0x1C94
+#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE				0x1C98
+#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE				0x1C9C
+#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE				0x1CA0
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE			0x1CA4
+#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE			0x1CA8
+#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE				0x1CAC
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE		0x1CB0
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE		0x1CB4
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE		0x1CC0
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE		0x1CC4
+#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE				0x1CD0
+#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE				0x1CD4
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE		0x1CE0
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE		0x1CE4
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE		0x1CE8
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE		0x1CEC
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE		0x1CF0
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE		0x1CF4
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE		0x1C78
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE		0x1C7C
+
+
+/****************************************/
+/* Communication Unit Registers		*/
+/****************************************/
+/*
+#define ETHERNET_0_ADDRESS_CONTROL_LOW						0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH			    0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW			    0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH			    0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW			    0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH			    0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf258
+ */
+#define MPSC_0_ADDRESS_CONTROL_LOW			    0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH			    0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		    0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		    0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW			    0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH			    0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		    0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		    0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf2d4
+ /*#define SERIAL_INIT_PCI_HIGH_ADDRESS			       0xf3201 */
+#define COMM_UNIT_ARBITER_CONTROL			    0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT			    0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE			    0xf310
+#define COMM_UNIT_INTERRUPT_MASK			    0xf314
+#define COMM_UNIT_ERROR_ADDRESS				    0xf314
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+ /*#define SERIAL_INIT_LAST_DATA					0xf3241 */
+ /*#define SERIAL_INIT_STATUS_AND_CONTROL			0xf3281 */
+#define SERIAL_INIT_LAST_DATA						0xf324
+#define SERIAL_INIT_CONTROL						0xf328
+#define SERIAL_INIT_STATUS						0xf32c
+
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define ETH_PHY_ADDR_REG			0x2000
+#define ETH_SMI_REG					0x2004
+#define ETH_UNIT_DEFAULT_ADDR_REG		0x2008
+#define ETH_UNIT_DEFAULTID_REG			0x200c
+#define ETH_UNIT_INTERRUPT_CAUSE_REG	0x2080
+#define ETH_UNIT_INTERRUPT_MASK_REG	0x2084
+#define ETH_UNIT_INTERNAL_USE_REG		0x24fc
+#define ETH_UNIT_ERROR_ADDR_REG			0x2094
+#define ETH_BAR_0					0x2200
+#define ETH_BAR_1					0x2208
+#define ETH_BAR_2					0x2210
+#define ETH_BAR_3					0x2218
+#define ETH_BAR_4					0x2220
+#define ETH_BAR_5					0x2228
+#define ETH_SIZE_REG_0				0x2204
+#define ETH_SIZE_REG_1				0x220c
+#define ETH_SIZE_REG_2				0x2214
+#define ETH_SIZE_REG_3				0x221c
+#define ETH_SIZE_REG_4				0x2224
+#define ETH_SIZE_REG_5					0x222c
+#define ETH_HEADERS_RETARGET_BASE_REG			0x2230
+#define ETH_HEADERS_RETARGET_CONTROL_REG	0x2234
+#define ETH_HIGH_ADDR_REMAP_REG_0		0x2280
+#define ETH_HIGH_ADDR_REMAP_REG_1		0x2284
+#define ETH_HIGH_ADDR_REMAP_REG_2		0x2288
+#define ETH_HIGH_ADDR_REMAP_REG_3			0x228c
+#define ETH_BASE_ADDR_ENABLE_REG			0x2290
+#define ETH_ACCESS_PROTECTION_REG(port)			(0x2294 + (port<<2))
+#define ETH_MIB_COUNTERS_BASE(port)			(0x3000 + (port<<7))
+#define ETH_PORT_CONFIG_REG(port)				(0x2400 + (port<<10))
+#define ETH_PORT_CONFIG_EXTEND_REG(port)		(0x2404 + (port<<10))
+#define ETH_MII_SERIAL_PARAMETRS_REG(port)		(0x2408 + (port<<10))
+#define ETH_GMII_SERIAL_PARAMETRS_REG(port)		(0x240c + (port<<10))
+#define ETH_VLAN_ETHERTYPE_REG(port)			(0x2410 + (port<<10))
+#define ETH_MAC_ADDR_LOW(port)					(0x2414 + (port<<10))
+#define ETH_MAC_ADDR_HIGH(port)					(0x2418 + (port<<10))
+#define ETH_SDMA_CONFIG_REG(port)				(0x241c + (port<<10))
+#define ETH_DSCP_0(port)					(0x2420 + (port<<10))
+#define ETH_DSCP_1(port)					(0x2424 + (port<<10))
+#define ETH_DSCP_2(port)					(0x2428 + (port<<10))
+#define ETH_DSCP_3(port)					(0x242c + (port<<10))
+#define ETH_DSCP_4(port)					(0x2430 + (port<<10))
+#define ETH_DSCP_5(port)					(0x2434 + (port<<10))
+#define ETH_DSCP_6(port)					(0x2438 + (port<<10))
+#define ETH_PORT_SERIAL_CONTROL_REG(port)		(0x243c + (port<<10))
+#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		(0x2440 + (port<<10))
+#define ETH_PORT_STATUS_REG(port)				(0x2444 + (port<<10))
+#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)	(0x2448 + (port<<10))
+#define ETH_TX_QUEUE_FIXED_PRIORITY(port)		(0x244c + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)		(0x2450 + (port<<10))
+#define ETH_MAXIMUM_TRANSMIT_UNIT(port)				(0x2458 + (port<<10))
+#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)		(0x245c + (port<<10))
+#define ETH_INTERRUPT_CAUSE_REG(port)				(0x2460 + (port<<10))
+#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)			(0x2464 + (port<<10))
+#define ETH_INTERRUPT_MASK_REG(port)				(0x2468 + (port<<10))
+#define ETH_INTERRUPT_EXTEND_MASK_REG(port)			(0x246c + (port<<10))
+#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)			(0x2470 + (port<<10))
+#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)			(0x2474 + (port<<10))
+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)			(0x247c + (port<<10))
+#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)			(0x2484 + (port<<10)
+#define ETH_PORT_DEBUG_0_REG(port)					(0x248c + (port<<10))
+#define ETH_PORT_DEBUG_1_REG(port)					(0x2490 + (port<<10))
+#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)			(0x2494 + (port<<10))
+#define ETH_INTERNAL_USE_REG(port)					(0x24fc + (port<<10))
+#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)			(0x2680 + (port<<10))
+#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)			(0x2684 + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)			(0x260c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)			(0x261c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)			(0x262c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)			(0x263c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)			(0x264c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)			(0x265c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)			(0x266c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)			(0x267c + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)			(0x26c0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)			(0x26c4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)			(0x26c8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)			(0x26cc + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)			(0x26d0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)			(0x26d4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)			(0x26d8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)			(0x26dc + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)			(0x2700 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)			(0x2710 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)			(0x2720 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)			(0x2730 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)			(0x2740 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)			(0x2750 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)			(0x2760 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)			(0x2770 + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)		(0x2704 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)		(0x2714 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)		(0x2724 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)		(0x2734 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)		(0x2744 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)		(0x2754 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)		(0x2764 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)		(0x2774 + (port<<10))
+#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)			(0x2708 + (port<<10))
+#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)			(0x2718 + (port<<10))
+#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)			(0x2728 + (port<<10))
+#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)			(0x2738 + (port<<10))
+#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)			(0x2748 + (port<<10))
+#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)			(0x2758 + (port<<10))
+#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)			(0x2768 + (port<<10))
+#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)			(0x2778 + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)			(0x2780 + (port<<10))
+#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)	(0x3400 + (port<<10))
+#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)		(0x3500 + (port<<10))
+#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)			(0x3600 + (port<<10))
+
+/****************************************/
+/* Cunit Debug	(for internal use)     */
+/****************************************/
+
+#define CUNIT_ADDRESS					    0xf340
+#define CUNIT_COMMAND_AND_ID				    0xf344
+#define CUNIT_WRITE_DATA_LOW				    0xf348
+#define CUNIT_WRITE_DATA_HIGH				    0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE				    0xf358
+#define CUNIT_READ_DATA_LOW				    0xf350
+#define CUNIT_READ_DATA_HIGH				    0xf354
+#define CUNIT_READ_ID					    0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers		*/
+/****************************************/
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define ETH_PHY_ADDR_REG				0x2000
+#define ETH_SMI_REG						0x2004
+#define ETH_UNIT_DEFAULT_ADDR_REG			0x2008
+#define ETH_UNIT_DEFAULTID_REG				0x200c
+#define ETH_UNIT_INTERRUPT_CAUSE_REG			0x2080
+#define ETH_UNIT_INTERRUPT_MASK_REG		0x2084
+#define ETH_UNIT_INTERNAL_USE_REG			0x24fc
+#define ETH_UNIT_ERROR_ADDR_REG				0x2094
+#define ETH_BAR_0						0x2200
+#define ETH_BAR_1						0x2208
+#define ETH_BAR_2						0x2210
+#define ETH_BAR_3						0x2218
+#define ETH_BAR_4						0x2220
+#define ETH_BAR_5						0x2228
+#define ETH_SIZE_REG_0						0x2204
+#define ETH_SIZE_REG_1						0x220c
+#define ETH_SIZE_REG_2						0x2214
+#define ETH_SIZE_REG_3						0x221c
+#define ETH_SIZE_REG_4						0x2224
+#define ETH_SIZE_REG_5						0x222c
+#define ETH_HEADERS_RETARGET_BASE_REG			0x2230
+#define ETH_HEADERS_RETARGET_CONTROL_REG	0x2234
+#define ETH_HIGH_ADDR_REMAP_REG_0			0x2280
+#define ETH_HIGH_ADDR_REMAP_REG_1		0x2284
+#define ETH_HIGH_ADDR_REMAP_REG_2		0x2288
+#define ETH_HIGH_ADDR_REMAP_REG_3			0x228c
+#define ETH_BASE_ADDR_ENABLE_REG			0x2290
+#define ETH_ACCESS_PROTECTION_REG(port)			(0x2294 + (port<<2))
+#define ETH_MIB_COUNTERS_BASE(port)			(0x3000 + (port<<7))
+#define ETH_PORT_CONFIG_REG(port)			(0x2400 + (port<<10))
+#define ETH_PORT_CONFIG_EXTEND_REG(port)		(0x2404 + (port<<10))
+#define ETH_MII_SERIAL_PARAMETRS_REG(port)		(0x2408 + (port<<10))
+#define ETH_GMII_SERIAL_PARAMETRS_REG(port)		(0x240c + (port<<10))
+#define ETH_VLAN_ETHERTYPE_REG(port)			(0x2410 + (port<<10))
+#define ETH_MAC_ADDR_LOW(port)					(0x2414 + (port<<10))
+#define ETH_MAC_ADDR_HIGH(port)					(0x2418 + (port<<10))
+#define ETH_SDMA_CONFIG_REG(port)			(0x241c + (port<<10))
+#define ETH_DSCP_0(port)					(0x2420 + (port<<10))
+#define ETH_DSCP_1(port)					(0x2424 + (port<<10))
+#define ETH_DSCP_2(port)					(0x2428 + (port<<10))
+#define ETH_DSCP_3(port)					(0x242c + (port<<10))
+#define ETH_DSCP_4(port)					(0x2430 + (port<<10))
+#define ETH_DSCP_5(port)					(0x2434 + (port<<10))
+#define ETH_DSCP_6(port)					(0x2438 + (port<<10))
+#define ETH_PORT_SERIAL_CONTROL_REG(port)	(0x243c + (port<<10))
+#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		(0x2440 + (port<<10))
+#define ETH_PORT_STATUS_REG(port)				(0x2444 + (port<<10))
+#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)	(0x2448 + (port<<10))
+#define ETH_TX_QUEUE_FIXED_PRIORITY(port)		(0x244c + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define ETH_MAXIMUM_TRANSMIT_UNIT(port)			(0x2458 + (port<<10))
+#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define ETH_INTERRUPT_CAUSE_REG(port)			(0x2460 + (port<<10))
+#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		(0x2464 + (port<<10))
+#define ETH_INTERRUPT_MASK_REG(port)			(0x2468 + (port<<10))
+#define ETH_INTERRUPT_EXTEND_MASK_REG(port)		(0x246c + (port<<10))
+#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)	(0x2470 + (port<<10))
+#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)	(0x2474 + (port<<10))
+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		(0x247c + (port<<10))
+#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)	(0x2484 + (port<<10)
+#define ETH_PORT_DEBUG_0_REG(port)				(0x248c + (port<<10))
+#define ETH_PORT_DEBUG_1_REG(port)				(0x2490 + (port<<10))
+#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)	(0x2494 + (port<<10))
+#define ETH_INTERNAL_USE_REG(port)				(0x24fc + (port<<10))
+#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)	(0x2680 + (port<<10))
+#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)		(0x2684 + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		(0x260c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)	(0x261c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		(0x262c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		(0x263c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		(0x264c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		(0x265c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		(0x266c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		(0x267c + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)	(0x26c0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)	(0x26c4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)	(0x26c8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		(0x26cc + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		(0x26d0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		(0x26d4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		(0x26d8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		(0x26dc + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		(0x2708 + (port<<10))
+#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		(0x2718 + (port<<10))
+#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		(0x2728 + (port<<10))
+#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		(0x2738 + (port<<10))
+#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		(0x2748 + (port<<10))
+#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		(0x2758 + (port<<10))
+#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		(0x2768 + (port<<10))
+#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		(0x2778 + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		(0x2780 + (port<<10))
+#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		(0x3600 + (port<<10))
+
+
+/* Ethernet GT64260 */
+/*
+#define ETHERNET_PHY_ADDRESS_REGISTER					0x2000
+#define ETHERNET_SMI_REGISTER							0x2010
+*/
+/* Ethernet 0 */
+/*
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER				0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER		0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER					0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER					0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER				0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER				0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER			0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER					0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER				0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER				0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0				0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1				0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2				0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3				0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0		0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1		0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2		0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3		0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0		0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1		0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE					0x2500
+*/
+/* Ethernet 1 */
+/*
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER				0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER		0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER					0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER					0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER				0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER				0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER			0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER					0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER				0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER				0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0				0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1				0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2				0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3				0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0		0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1		0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2		0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3		0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0		0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1		0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE					0x2900
+*/
+/* Ethernet 2 */
+/*
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER				0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER		0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER					0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER					0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER				0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER				0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER			0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER					0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER				0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER				0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0				0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1				0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2				0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3				0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0		0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1		0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2		0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3		0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0		0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1		0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE					0x2d00
+*/
+
+/****************************************/
+/* SDMA Registers			*/
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER			0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER				0x4000
+#define CHANNEL0_COMMAND_REGISTER				0x4008
+#define CHANNEL0_RX_CMD_STATUS					0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES		    0x4804
+#define CHANNEL0_RX_BUFFER_POINTER				0x4808
+#define CHANNEL0_RX_NEXT_POINTER				0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER		0x4810
+#define CHANNEL0_TX_CMD_STATUS					0x4C00
+#define CHANNEL0_TX_PACKET_SIZE					0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER				0x4C08
+#define CHANNEL0_TX_NEXT_POINTER				0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER		0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER			0x4c14
+/*
+#define CHANNEL1_CONFIGURATION_REGISTER				0x5000
+#define CHANNEL1_COMMAND_REGISTER				0x5008
+#define CHANNEL1_RX_CMD_STATUS					0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES		    0x5804
+#define CHANNEL1_RX_BUFFER_POINTER				0x5808
+#define CHANNEL1_RX_NEXT_POINTER				0x580c
+#define CHANNEL1_TX_CMD_STATUS					0x5C00
+#define CHANNEL1_TX_PACKET_SIZE					0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER				0x5C08
+#define CHANNEL1_TX_NEXT_POINTER				0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER		0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER		0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER			0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER				0x6000
+#define CHANNEL2_COMMAND_REGISTER				0x6008
+#define CHANNEL2_RX_CMD_STATUS					0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES		    0x6804
+#define CHANNEL2_RX_BUFFER_POINTER				0x6808
+#define CHANNEL2_RX_NEXT_POINTER				0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_TX_CMD_STATUS					0x6C00
+#define CHANNEL2_TX_PACKET_SIZE					0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER				0x6C08
+#define CHANNEL2_TX_NEXT_POINTER				0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER			0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER			0x6c14
+*/
+/* SDMA Interrupt */
+/*
+#define SDMA_CAUSE							0xb820
+#define SDMA_MASK							0xb8a0
+*/
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define SDMA_CONFIG_REG(channel)					(0x4000 + (channel<<13))
+#define SDMA_COMMAND_REG(channel)					(0x4008 + (channel<<13))
+#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)		(0x4810 + (channel<<13))
+#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define SDMA_CAUSE_REG							0xb800
+#define SDMA_MASK_REG							0xb880
+
+/****************************************/
+/* Baude Rate Generators Registers	*/
+/****************************************/
+
+/* BRG 0 */
+#define BRG0_CONFIGURATION_REGISTER		0xb200
+#define BRG0_BAUDE_TUNING_REGISTER			 0xb204
+
+/* BRG 1 */
+#define BRG1_CONFIGURATION_REGISTER			0xb208
+#define BRG1_BAUDE_TUNING_REGISTER			 0xb20c
+
+/* BRG 2 */
+#define BRG2_CONFIGURATION_REGISTER			0xb210
+#define BRG2_BAUDE_TUNING_REGISTER			 0xb214
+
+/* BRG Interrupts */
+#define BRG_CAUSE_REGISTER					0xb834
+#define BRG_MASK_REGISTER					0xb8b4
+#define BRG_CONFIG_REG(brg)					(0xb200 + (brg<<3))
+#define BRG_BAUDE_TUNING_REG(brg)				(0xb208 + (brg<<3))
+#define BRG_CAUSE_REG						BRG_CAUSE_REGISTER  /*0xb8341 */
+#define BRG_MASK_REG						BRG_MASK_REGISTER  /*0xb8b41 */
+
+/* MISC */
+
+#define MAIN_ROUTING_REGISTER						0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER				0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER				0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	0xb40c
+
+/****************************************/
+/*	   Watchdog registers			*/
+/****************************************/
+#define WATCHDOG_CONFIGURATION_REGISTER			0xb410
+#define WATCHDOG_VALUE_REGISTER					0xb414
+#define WATCHDOG_CONFIG_REG					WATCHDOG_CONFIGURATION_REGISTER	 /*0xb4101 */
+#define WATCHDOG_VALUE_REG						WATCHDOG_VALUE_REGISTER	 /*0xb4141 */
+
+
+/****************************************/
+/* Flex TDM Registers			*/
+/****************************************/
+
+/* FTDM Port */
+
+#define FLEXTDM_TRANSMIT_READ_POINTER			    0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER			    0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER			    0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER		    0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER		    0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER		    0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER		    0xa818
+
+/* FTDM Interrupts */
+
+#define FTDM_CAUSE_REGISTER				    0xb830
+#define FTDM_MASK_REGISTER				    0xb8b0
+
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define GPP_IO_CONTROL						0xf100
+#define GPP_LEVEL_CONTROL					0xf110
+#define GPP_VALUE						0xf104
+#define GPP_INTERRUPT_CAUSE					0xf108
+#define GPP_INTERRUPT_MASK					0xf10c
+#define GPP_INTERRUPT_MASK0					GPP_INTERRUPT_MASK  /* 0xf10c1 */
+#define GPP_INTERRUPT_MASK1					0xf114
+#define GPP_VALUE_SET						0xf118
+#define GPP_VALUE_CLEAR						0xf11c
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+#define MPP_CONTROL0						0xf000
+#define MPP_CONTROL1						0xf004
+#define MPP_CONTROL2						0xf008
+#define MPP_CONTROL3						0xf00c
+#define DEBUG_PORT_MULTIPLEX					0xf014
+ /*#define SERIAL_PORT_MULTIPLEX			       0xf0101 */
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts							*/
+/****************************************/
+/****************************************/
+/* Interrupts (checked I.A. 14.10.02)				*/
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER			0x004  /* gt64260: 0xc181 */
+#define HIGH_INTERRUPT_CAUSE_REGISTER			0x00c  /* gt64260: 0xc681 */
+#define CPU_INTERRUPT_MASK_REGISTER_LOW		0x014  /* gt64260: 0xc1c1 */
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH		0x01c  /* gt64260: 0xc6c1 */
+#define CPU_SELECT_CAUSE_REGISTER			0x024  /* gt64260: 0xc701 */
+#define CPU_INTERRUPT_1_MASK_REGISTER_LOW		0x034  /* new in the MV64360 and MV64460 */
+#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH		0x03c  /* new in the MV64360 and MV64460 */
+#define CPU_SELECT_1_CAUSE_REGISTER			0x044  /* new in the MV64360 and MV64460 */
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW	0x054  /* gt64260: 0xc241 */
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c  /* gt64260: 0xc641 */
+#define PCI_0SELECT_CAUSE						0x064  /* gt64260: 0xc741 */
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	0x074  /* gt64260: 0xca41 */
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c  /* gt64260: 0xce41 */
+#define PCI_1SELECT_CAUSE						0x084  /* gt64260: 0xcf41 */
+/*#define CPU_INT_0_MASK						0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */
+/*#define CPU_INT_1_MASK						0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */
+/*#define CPU_INT_2_MASK						0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */
+/*#define CPU_INT_3_MASK						0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */
+
+#define MAIN_INTERRUPT_CAUSE_LOW				LOW_INTERRUPT_CAUSE_REGISTER  /* 0x0041 */
+#define MAIN_INTERRUPT_CAUSE_HIGH				HIGH_INTERRUPT_CAUSE_REGISTER  /* 0x00c1 */
+#define CPU_INTERRUPT0_MASK_LOW				CPU_INTERRUPT_MASK_REGISTER_LOW	 /* 0x0141 */
+#define CPU_INTERRUPT0_MASK_HIGH			CPU_INTERRUPT_MASK_REGISTER_HIGH  /*0x01c1 */
+#define CPU_INTERRUPT0_SELECT_CAUSE			CPU_SELECT_CAUSE_REGISTER  /* 0x0241 */
+#define CPU_INTERRUPT1_MASK_LOW				CPU_INTERRUPT_1_MASK_REGISTER_LOW  /* 0x0341 */
+#define CPU_INTERRUPT1_MASK_HIGH			CPU_INTERRUPT_1_MASK_REGISTER_HIGH  /* 0x03c1 */
+#define CPU_INTERRUPT1_SELECT_CAUSE			CPU_SELECT_1_CAUSE_REGISTER  /* 0x0441 */
+#define INTERRUPT0_MASK_0_LOW				PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */
+#define INTERRUPT0_MASK_0_HIGH					PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH	 /* 0x05c1 */
+#define INTERRUPT0_SELECT_CAUSE				PCI_0SELECT_CAUSE  /* 0x0641 */
+#define INTERRUPT1_MASK_0_LOW					PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	/* 0x0741 */
+#define INTERRUPT1_MASK_0_HIGH					PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH	 /* 0x07c1 */
+#define INTERRUPT1_SELECT_CAUSE				PCI_1SELECT_CAUSE  /* 0x0841 */
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define I2C_SLAVE_ADDRESS					0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS			0xc040
+#define I2C_DATA						0xc004
+#define I2C_CONTROL						0xc008
+#define I2C_STATUS_BAUDE_RATE					0xc00C
+#define I2C_SOFT_RESET						0xc01c
+#define I2C_SLAVE_ADDR						I2C_SLAVE_ADDRESS  /* 0xc0001 */
+#define I2C_EXTENDED_SLAVE_ADDR					I2C_EXTENDED_SLAVE_ADDRESS  /*0xc0101 */
+
+/****************************************/
+/* MPSC Registers			*/
+/****************************************/
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MPSC_ROUTING_REG					0xb400
+#define MPSC_RX_CLOCK_ROUTING_REG			0xb404
+#define MPSC_TX_CLOCK_ROUTING_REG			0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MPSC_CAUSE_REG(port)					(0xb804 + (port<<3))
+#define MPSC_MASK_REG(port)					(0xb884 + (port<<3))
+
+#define MPSC_MAIN_CONFIG_LOW(port)			(0x8000 + (port<<12))
+#define MPSC_MAIN_CONFIG_HIGH(port)			(0x8004 + (port<<12))
+#define MPSC_PROTOCOL_CONFIG(port)			(0x8008 + (port<<12))
+#define MPSC_CHANNEL_REG1(port)					(0x800c + (port<<12))
+#define MPSC_CHANNEL_REG2(port)					(0x8010 + (port<<12))
+#define MPSC_CHANNEL_REG3(port)					(0x8014 + (port<<12))
+#define MPSC_CHANNEL_REG4(port)					(0x8018 + (port<<12))
+#define MPSC_CHANNEL_REG5(port)					(0x801c + (port<<12))
+#define MPSC_CHANNEL_REG6(port)					(0x8020 + (port<<12))
+#define MPSC_CHANNEL_REG7(port)					(0x8024 + (port<<12))
+#define MPSC_CHANNEL_REG8(port)					(0x8028 + (port<<12))
+#define MPSC_CHANNEL_REG9(port)					(0x802c + (port<<12))
+#define MPSC_CHANNEL_REG10(port)				(0x8030 + (port<<12))
+
+
+/* MPSC0  */
+
+#define MPSC0_MAIN_CONFIGURATION_LOW			    0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH			    0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION			    0x8008
+#define CHANNEL0_REGISTER1				    0x800c
+#define CHANNEL0_REGISTER2				    0x8010
+#define CHANNEL0_REGISTER3				    0x8014
+#define CHANNEL0_REGISTER4				    0x8018
+#define CHANNEL0_REGISTER5				    0x801c
+#define CHANNEL0_REGISTER6				    0x8020
+#define CHANNEL0_REGISTER7				    0x8024
+#define CHANNEL0_REGISTER8				    0x8028
+#define CHANNEL0_REGISTER9				    0x802c
+#define CHANNEL0_REGISTER10				    0x8030
+#define CHANNEL0_REGISTER11				    0x8034
+
+/* MPSC1  */
+
+#define MPSC1_MAIN_CONFIGURATION_LOW			    0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH			    0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION			    0x8848
+#define CHANNEL1_REGISTER1				    0x884c
+#define CHANNEL1_REGISTER2				    0x8850
+#define CHANNEL1_REGISTER3				    0x8854
+#define CHANNEL1_REGISTER4				    0x8858
+#define CHANNEL1_REGISTER5				    0x885c
+#define CHANNEL1_REGISTER6				    0x8860
+#define CHANNEL1_REGISTER7				    0x8864
+#define CHANNEL1_REGISTER8				    0x8868
+#define CHANNEL1_REGISTER9				    0x886c
+#define CHANNEL1_REGISTER10				    0x8870
+#define CHANNEL1_REGISTER11				    0x8874
+
+/* MPSC2  */
+
+#define MPSC2_MAIN_CONFIGURATION_LOW			    0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH			    0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION			    0x9048
+#define CHANNEL2_REGISTER1				    0x904c
+#define CHANNEL2_REGISTER2				    0x9050
+#define CHANNEL2_REGISTER3				    0x9054
+#define CHANNEL2_REGISTER4				    0x9058
+#define CHANNEL2_REGISTER5				    0x905c
+#define CHANNEL2_REGISTER6				    0x9060
+#define CHANNEL2_REGISTER7				    0x9064
+#define CHANNEL2_REGISTER8				    0x9068
+#define CHANNEL2_REGISTER9				    0x906c
+#define CHANNEL2_REGISTER10				    0x9070
+#define CHANNEL2_REGISTER11				    0x9074
+
+/* MPSCs Interupts  */
+
+#define MPSC0_CAUSE						0xb824
+#define MPSC0_MASK						0xb8a4
+#define MPSC1_CAUSE						0xb828
+#define MPSC1_MASK						0xb8a8
+#define MPSC2_CAUSE						0xb82c
+#define MPSC2_MASK						 0xb8ac
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define CUNIT_BASE_ADDR_REG0					0xf200
+#define CUNIT_BASE_ADDR_REG1					0xf208
+#define CUNIT_BASE_ADDR_REG2					0xf210
+#define CUNIT_BASE_ADDR_REG3					0xf218
+#define CUNIT_SIZE0						0xf204
+#define CUNIT_SIZE1						0xf20c
+#define CUNIT_SIZE2						0xf214
+#define CUNIT_SIZE3						0xf21c
+#define CUNIT_HIGH_ADDR_REMAP_REG0			0xf240
+#define CUNIT_HIGH_ADDR_REMAP_REG1			0xf244
+#define CUNIT_BASE_ADDR_ENABLE_REG			0xf250
+#define MPSC0_ACCESS_PROTECTION_REG			0xf254
+#define MPSC1_ACCESS_PROTECTION_REG			0xf258
+#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG	0xf25C
+
+	/*  Error Report Registers  */
+
+#define CUNIT_INTERRUPT_CAUSE_REG			0xf310
+#define CUNIT_INTERRUPT_MASK_REG			0xf314
+#define CUNIT_ERROR_ADDR					0xf318
+
+	/*  Cunit Control Registers */
+
+#define CUNIT_ARBITER_CONTROL_REG			0xf300
+#define CUNIT_CONFIG_REG					0xb40c
+#define CUNIT_CRROSBAR_TIMEOUT_REG			0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define CUNIT_DEBUG_LOW						0xf340
+#define CUNIT_DEBUG_HIGH					0xf344
+#define CUNIT_MMASK						0xf380
+
+#endif /* __INCmv_gen_regh */
diff --git a/u-boot/board/Marvell/include/pci.h b/u-boot/board/Marvell/include/pci.h
new file mode 100644
index 0000000..167248d
--- /dev/null
+++ b/u-boot/board/Marvell/include/pci.h
@@ -0,0 +1,293 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include"core.h"
+#include"memory.h"
+
+/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
+#define PCI_MAX_DEVICES 22
+
+
+/* Macros */
+
+/* The next Macros configurate the initiator board (SELF) or any any agent on
+   the PCI to become: MASTER, response to MEMORY transactions , response to
+   IO transactions or TWO both MEMORY_IO transactions. Those configuration
+   are for both PCI0 and PCI1. */
+
+#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host,		       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
+
+#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |		     \
+	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host,	      \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &		     \
+	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define		MASTER_ENABLE			BIT2
+#define		MEMORY_ENABLE			BIT1
+#define		I_O_ENABLE			BIT0
+#define	    SELF		    32
+
+/* Agent on the PCI bus may have up to 6 BARS. */
+#define	    BAR0		    0x10
+#define	    BAR1		    0x14
+#define	    BAR2		    0x18
+#define	    BAR3		    0x1c
+#define	    BAR4		    0x20
+#define	    BAR5		    0x24
+#define		BAR_SEL_MEM_IO			BIT0
+#define		BAR_MEM_TYPE_32_BIT		NO_BIT
+#define		BAR_MEM_TYPE_BELOW_1M		       BIT1
+#define		BAR_MEM_TYPE_64_BIT			      BIT2
+#define		BAR_MEM_TYPE_RESERVED		      (BIT1 | BIT2)
+#define		BAR_MEM_TYPE_MASK		      (BIT1 | BIT2)
+#define		BAR_PREFETCHABLE				      BIT3
+#define		BAR_CONFIG_MASK			(BIT0 | BIT1 | BIT2 | BIT3)
+
+/* Defines for the access regions. */
+#define	    PREFETCH_ENABLE		    BIT12
+#define	    PREFETCH_DISABLE		    NO_BIT
+#define	    DELAYED_READ_ENABLE		    BIT13
+/* #define     CACHING_ENABLE		       BIT14 */
+/* aggressive prefetch: PCI slave prefetch two burst in advance*/
+#define	    AGGRESSIVE_PREFETCH		     BIT16
+/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define	    READ_LINE_AGGRESSIVE_PREFETCH   BIT17
+/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define	    READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
+#define	    MAX_BURST_4			    NO_BIT
+#define	    MAX_BURST_8			    BIT20  /* Bits[21:20] = 01 */
+#define	    MAX_BURST_16		    BIT21  /* Bits[21:20] = 10 */
+#define	    PCI_BYTE_SWAP		    NO_BIT /* Bits[25:24] = 00 */
+#define	    PCI_NO_SWAP			    BIT24  /* Bits[25:24] = 01 */
+#define	    PCI_BYTE_AND_WORD_SWAP	    BIT25  /* Bits[25:24] = 10 */
+#define	    PCI_WORD_SWAP		   (BIT24 | BIT25) /* Bits[25:24] = 11 */
+#define	    PCI_ACCESS_PROTECT		    BIT28
+#define	    PCI_WRITE_PROTECT		    BIT29
+
+/* typedefs */
+
+typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
+				REGION6,REGION7} PCI_ACCESS_REGIONS;
+
+typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
+typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
+
+typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
+			    PCI_SNOOP_TYPE;
+typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
+			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
+			      PCI_SNOOP_REGION;
+
+typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
+typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
+			 PCI_REGION2,PCI_REGION3,
+			 PCI_IO}
+			 PCI_REGION;
+
+/*ronen 7/Dec/03 */
+typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
+			       PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
+			       PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
+			       PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
+			       PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
+			       PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
+			       PCI_LAST_BAR} PCI_INTERNAL_BAR;
+
+typedef struct pciBar {
+    unsigned int detectBase;
+    unsigned int base;
+    unsigned int size;
+    unsigned int type;
+} PCI_BAR;
+
+typedef struct pciDevice {
+    PCI_HOST	     host;
+    char	    type[40];
+    unsigned int    deviceNum;
+    unsigned int    venID;
+    unsigned int    deviceID;
+    PCI_BAR bar[6];
+} PCI_DEVICE;
+
+typedef struct pciSelfBars {
+    unsigned int    SCS0Base;
+    unsigned int    SCS0Size;
+    unsigned int    SCS1Base;
+    unsigned int    SCS1Size;
+    unsigned int    SCS2Base;
+    unsigned int    SCS2Size;
+    unsigned int    SCS3Base;
+    unsigned int    SCS3Size;
+    unsigned int    internalMemBase;
+    unsigned int    internalIOBase;
+    unsigned int    CS0Base;
+    unsigned int    CS0Size;
+    unsigned int    CS1Base;
+    unsigned int    CS1Size;
+    unsigned int    CS2Base;
+    unsigned int    CS2Size;
+    unsigned int    CS3Base;
+    unsigned int    CS3Size;
+    unsigned int    CSBootBase;
+    unsigned int    CSBootSize;
+    unsigned int    P2PMem0Base;
+    unsigned int    P2PMem0Size;
+    unsigned int    P2PMem1Base;
+    unsigned int    P2PMem1Size;
+    unsigned int    P2PIOBase;
+    unsigned int    P2PIOSize;
+    unsigned int    CPUBase;
+    unsigned int    CPUSize;
+} PCI_SELF_BARS;
+
+/* read/write configuration registers on local PCI bus. */
+void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
+		       unsigned int pciDevNum, unsigned int data);
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum);
+
+/* read/write configuration registers on another PCI bus. */
+void pciOverBridgeWriteConfigReg(PCI_HOST host,
+				 unsigned int regOffset,
+				 unsigned int pciDevNum,
+				 unsigned int busNum,unsigned int data);
+unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
+					unsigned int regOffset,
+					unsigned int pciDevNum,
+					unsigned int busNum);
+
+/* Performs full scane on both PCI and returns all detail possible on the
+   agents which exist on the bus. */
+void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
+		    unsigned int numberOfElment);
+
+/*	Master`s memory space	*/
+bool pciMapSpace(PCI_HOST host, PCI_REGION region,
+		unsigned int remapBase,
+		unsigned int deviceBase,
+		unsigned int deviceLength);
+unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
+unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
+
+/*	Slave`s memory space   */
+void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
+		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
+
+#if 0 /* GARBAGE routines - dont use till they get cleaned up */
+void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
+void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
+void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
+void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
+void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
+			       unsigned int pci0Dev0Length);
+void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
+			       unsigned int pci1Dev0Length);
+void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
+			       unsigned int pci0Dev1Length);
+void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
+			       unsigned int pci1Dev1Length);
+void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
+			       unsigned int pci0Dev2Length);
+void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
+			       unsigned int pci1Dev2Length);
+void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
+			       unsigned int pci0Dev3Length);
+void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
+			       unsigned int pci1Dev3Length);
+void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
+				  unsigned int pci0DevBootLength);
+void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
+				  unsigned int pci1DevBootLength);
+void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
+			 unsigned int pci0P2pMem0Length);
+void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
+			 unsigned int pci1P2pMem0Length);
+void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
+			 unsigned int pci0P2pMem1Length);
+void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
+			 unsigned int pci1P2pMem1Length);
+void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
+		       unsigned int pci0P2pIoLength);
+void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
+		       unsigned int pci1P2pIoLength);
+
+void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
+void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
+#endif
+
+/* PCI region options */
+
+bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
+	unsigned int features, unsigned int baseAddress,
+	unsigned int regionLength);
+
+void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
+
+/* PCI arbiter */
+
+bool pciArbiterEnable(PCI_HOST host);
+bool pciArbiterDisable(PCI_HOST host);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5);
+bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+
+/* PCI-to-PCI (P2P) */
+
+bool pciP2PConfig(PCI_HOST host,
+		  unsigned int SecondBusLow,unsigned int SecondBusHigh,
+		  unsigned int busNum,unsigned int devNum);
+/* PCI Cache-coherency */
+
+bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+
+PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
+
+#endif /* __INCpcih */
diff --git a/u-boot/board/Marvell/mv88f6281gtw_ge/Makefile b/u-boot/board/Marvell/mv88f6281gtw_ge/Makefile
new file mode 100644
index 0000000..2443101
--- /dev/null
+++ b/u-boot/board/Marvell/mv88f6281gtw_ge/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mv88f6281gtw_ge.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/u-boot/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
new file mode 100644
index 0000000..ec2513f
--- /dev/null
+++ b/u-boot/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
@@ -0,0 +1,165 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000a00	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202433D	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x0000002A	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000046	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010001	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E811	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/u-boot/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
new file mode 100644
index 0000000..80fd20b
--- /dev/null
+++ b/u-boot/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -0,0 +1,134 @@
+/*
+ * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "mv88f6281gtw_ge.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
+			MV88F6281GTW_GE_OE_VAL_HIGH,
+			MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_GPIO,
+		MPP5_GPO,
+		MPP6_SYSRST_OUTn,
+		MPP7_SPI_SCn,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_GPIO,
+		MPP14_GPIO,
+		MPP15_GPIO,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_GPO,
+		MPP19_GPO,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+void reset_phy(void)
+{
+	/* configure and initialize switch */
+	struct mv88e61xx_config swcfg = {
+		.name = "egiga0",
+		.vlancfg = MV88E61XX_VLANCFG_ROUTER,
+		.rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+		.led_init = MV88E61XX_LED_INIT_EN,
+		.mdip = MV88E61XX_MDIP_REVERSE,
+		.portstate = MV88E61XX_PORTSTT_FORWARDING,
+		.cpuport = (1 << 5),
+		.ports_enabled = 0x3f
+	};
+
+	mv88e61xx_switch_initialize(&swcfg);
+}
+#endif /* CONFIG_MV88E61XX_SWITCH */
diff --git a/u-boot/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h b/u-boot/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
new file mode 100644
index 0000000..65b925d
--- /dev/null
+++ b/u-boot/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MV88F6281GTW_GE_H
+#define __MV88F6281GTW_GE_H
+
+#define MV88F6281GTW_GE_OE_LOW		(~((1 << 7) | (1 << 12) \
+					  |(1 << 20) | (1 << 21)))	/*enable GLED,RLED */
+#define MV88F6281GTW_GE_OE_HIGH		(~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \
+					  |(1 << 13)|(1 << 16)|(1 << 17)))
+#define MV88F6281GTW_GE_OE_VAL_LOW	(1 << 20)	/*make GLED on */
+#define MV88F6281GTW_GE_OE_VAL_HIGH	((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17))
+
+
+#endif /* __MV88F6281GTW_GE_H */
diff --git a/u-boot/board/Marvell/openrd_base/Makefile b/u-boot/board/Marvell/openrd_base/Makefile
new file mode 100644
index 0000000..d6d0ed3
--- /dev/null
+++ b/u-boot/board/Marvell/openrd_base/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= openrd_base.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/openrd_base/kwbimage.cfg b/u-boot/board/Marvell/openrd_base/kwbimage.cfg
new file mode 100644
index 0000000..757eb28
--- /dev/null
+++ b/u-boot/board/Marvell/openrd_base/kwbimage.cfg
@@ -0,0 +1,168 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strength reduced
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
+# bit3-0:   0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4:   0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+
+DATA 0xFFD0149C 0x0000E40f	# CPU ODT Control
+# bit3-0:    1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10:    01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12:    10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14:        1, M_STARTBURST_IN ODT: Enabled
+# bit15:        1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/Marvell/openrd_base/openrd_base.c b/u-boot/board/Marvell/openrd_base/openrd_base.c
new file mode 100644
index 0000000..10109c1
--- /dev/null
+++ b/u-boot/board/Marvell/openrd_base/openrd_base.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.c:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "openrd_base.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(OPENRD_OE_VAL_LOW,
+			OPENRD_OE_VAL_HIGH,
+			OPENRD_OE_LOW, OPENRD_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD, /* Alt UART1_TXD */
+		MPP14_SD_D0,  /* Alt UART1_RXD */
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,   /* UART1 / SD sel */
+		MPP35_TDM_CH0_TX_QL,
+		MPP36_TDM_SPI_CS1,
+		MPP37_TDM_CH2_TX_QL,
+		MPP38_TDM_CH2_RX_QL,
+		MPP39_AUDIO_I2SBCLK,
+		MPP40_AUDIO_I2SDO,
+		MPP41_AUDIO_I2SLRC,
+		MPP42_AUDIO_I2SMCLK,
+		MPP43_AUDIO_I2SDI,
+		MPP44_AUDIO_EXTCLK,
+		MPP45_TDM_PCLK,
+		MPP46_TDM_FS,
+		MPP47_TDM_DRX,
+		MPP48_TDM_DTX,
+		MPP49_TDM_CH0_RX_QL,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/u-boot/board/Marvell/openrd_base/openrd_base.h b/u-boot/board/Marvell/openrd_base/openrd_base.h
new file mode 100644
index 0000000..f3daf17
--- /dev/null
+++ b/u-boot/board/Marvell/openrd_base/openrd_base.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __OPENRD_BASE_H
+#define __OPENRD_BASE_H
+
+#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
+#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
+#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __OPENRD_BASE_H */
diff --git a/u-boot/board/Marvell/rd6281a/Makefile b/u-boot/board/Marvell/rd6281a/Makefile
new file mode 100644
index 0000000..e730e37
--- /dev/null
+++ b/u-boot/board/Marvell/rd6281a/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= rd6281a.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/rd6281a/kwbimage.cfg b/u-boot/board/Marvell/rd6281a/kwbimage.cfg
new file mode 100644
index 0000000..0d12dd9
--- /dev/null
+++ b/u-boot/board/Marvell/rd6281a/kwbimage.cfg
@@ -0,0 +1,167 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000099	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    1,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    0,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
+# bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/Marvell/rd6281a/rd6281a.c b/u-boot/board/Marvell/rd6281a/rd6281a.c
new file mode 100644
index 0000000..ecdea82
--- /dev/null
+++ b/u-boot/board/Marvell/rd6281a/rd6281a.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "rd6281a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(RD6281A_OE_VAL_LOW,
+			RD6281A_OE_VAL_HIGH,
+			RD6281A_OE_LOW, RD6281A_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GPIO,
+		MPP36_AUDIO_SPDIFI,
+		MPP37_AUDIO_SPDIFO,
+		MPP38_GPIO,
+		MPP39_TDM_SPI_CS0,
+		MPP40_TDM_SPI_SCK,
+		MPP41_TDM_SPI_MISO,
+		MPP42_TDM_SPI_MOSI,
+		MPP43_TDM_CODEC_INTn,
+		MPP44_GPIO,
+		MPP45_TDM_PCLK,
+		MPP46_TDM_FS,
+		MPP47_TDM_DRX,
+		MPP48_TDM_DTX,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+void mv_phy_88e1116_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	if (miiphy_read (name, devadr, MII_BMCR, &reg) != 0) {
+		printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
+		return;
+	}
+	if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
+		printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
+		return;
+	}
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+	/* configure and initialize switch */
+	struct mv88e61xx_config swcfg = {
+		.name = "egiga0",
+		.vlancfg = MV88E61XX_VLANCFG_ROUTER,
+		.rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+		.led_init = MV88E61XX_LED_INIT_EN,
+		.portstate = MV88E61XX_PORTSTT_FORWARDING,
+		.cpuport = (1 << 5),
+		.ports_enabled = 0x3f,
+	};
+
+	mv88e61xx_switch_initialize(&swcfg);
+
+	/* configure and initialize PHY */
+	mv_phy_88e1116_init("egiga1");
+}
diff --git a/u-boot/board/Marvell/rd6281a/rd6281a.h b/u-boot/board/Marvell/rd6281a/rd6281a.h
new file mode 100644
index 0000000..c978bef
--- /dev/null
+++ b/u-boot/board/Marvell/rd6281a/rd6281a.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __RD6281A_H
+#define __RD6281A_H
+
+#define RD6281A_OE_LOW			(~(1 << 7))
+#define RD6281A_OE_HIGH			(~(1 << 2 | 1 << 12))
+#define RD6281A_OE_VAL_LOW		(0)
+#define RD6281A_OE_VAL_HIGH		(1 << 12)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __RD6281A_H */
diff --git a/u-boot/board/Marvell/sheevaplug/Makefile b/u-boot/board/Marvell/sheevaplug/Makefile
new file mode 100644
index 0000000..d2286fa
--- /dev/null
+++ b/u-boot/board/Marvell/sheevaplug/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sheevaplug.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Marvell/sheevaplug/kwbimage.cfg b/u-boot/board/Marvell/sheevaplug/kwbimage.cfg
new file mode 100644
index 0000000..3b9c53f
--- /dev/null
+++ b/u-boot/board/Marvell/sheevaplug/kwbimage.cfg
@@ -0,0 +1,162 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/Marvell/sheevaplug/sheevaplug.c b/u-boot/board/Marvell/sheevaplug/sheevaplug.c
new file mode 100644
index 0000000..d7dc80c
--- /dev/null
+++ b/u-boot/board/Marvell/sheevaplug/sheevaplug.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "sheevaplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
+			SHEEVAPLUG_OE_VAL_HIGH,
+			SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/u-boot/board/Marvell/sheevaplug/sheevaplug.h b/u-boot/board/Marvell/sheevaplug/sheevaplug.h
new file mode 100644
index 0000000..3ed5b7f
--- /dev/null
+++ b/u-boot/board/Marvell/sheevaplug/sheevaplug.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __SHEEVAPLUG_H
+#define __SHEEVAPLUG_H
+
+#define SHEEVAPLUG_OE_LOW		(~(0))
+#define SHEEVAPLUG_OE_HIGH		(~(0))
+#define SHEEVAPLUG_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __SHEEVAPLUG_H */
diff --git a/u-boot/board/RPXClassic/Makefile b/u-boot/board/RPXClassic/Makefile
new file mode 100644
index 0000000..554a865
--- /dev/null
+++ b/u-boot/board/RPXClassic/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o eccx.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/RPXClassic/RPXClassic.c b/u-boot/board/RPXClassic/RPXClassic.c
new file mode 100644
index 0000000..c3d5385
--- /dev/null
+++ b/u-boot/board/RPXClassic/RPXClassic.c
@@ -0,0 +1,276 @@
+/*
+ * (C)	Copyright 2001
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ * U-Boot port on RPXClassic LF (CLLF_BW31) board
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <config.h>
+#include <mpc8xx.h>
+#include <net.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static unsigned char aschex_to_byte (unsigned char *cp);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
+	0x0CFFCC00, 0x33FFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXClassic\n");
+	return (0);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+static void board_get_enetaddr(uchar *enet)
+{
+	int i;
+	char buff[256], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x54, 0, 1, (uchar *)buff, 128);
+	i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
+
+	/* Retrieve MAC address in buffer (key EA)		*/
+	for (cp = buff;;) {
+		if (cp[0] == 'E' && cp[1] == 'A') {
+			cp += 3;
+			/* Read MAC address			*/
+			for (i = 0; i < 6; i++, cp += 2) {
+				enet[i] = aschex_to_byte ((unsigned char *)cp);
+			}
+		}
+		/* Scan to the end of the record		*/
+		while ((*cp != '\n') && (*cp != (char)0xff)) {
+			cp++;
+		}
+		/* If the next character is a \n, 0 or ff, we are done.	*/
+		cp++;
+		if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
+			break;
+	}
+
+#ifdef CONFIG_FEC_ENET
+	/* The MAC address is the same as normal ethernet except the 3rd byte	 */
+	/* (See the E.P. Planet Core Overview manual		*/
+	enet[3] |= 0x80;
+#endif
+
+	printf("MAC address = %pM\n", enet);
+}
+
+int misc_init_r(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
+
+void rpxclassic_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+
+#ifdef CONFIG_FEC_ENET
+
+	/* Validate the fast ethernet tranceiver                             */
+	*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
+	*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
+	*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
+	*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
+#endif
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size10;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_mar = 0x00000000;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size
+	 * try 10 column mode
+	 */
+
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
+						SDRAM_MAX_SIZE);
+
+	return (size10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+/*-----------------------------------------------------------------------------
+ * aschex_to_byte --
+ *-----------------------------------------------------------------------------
+ */
+static unsigned char aschex_to_byte (unsigned char *cp)
+{
+	u_char byte, c;
+
+	c = *cp++;
+
+	if ((c >= 'A') && (c <= 'F')) {
+		c -= 'A';
+		c += 10;
+	} else if ((c >= 'a') && (c <= 'f')) {
+		c -= 'a';
+		c += 10;
+	} else {
+		c -= '0';
+	}
+
+	byte = c * 16;
+
+	c = *cp;
+
+	if ((c >= 'A') && (c <= 'F')) {
+		c -= 'A';
+		c += 10;
+	} else if ((c >= 'a') && (c <= 'f')) {
+		c -= 'a';
+		c += 10;
+	} else {
+		c -= '0';
+	}
+
+	byte += c;
+
+	return (byte);
+}
diff --git a/u-boot/board/RPXClassic/eccx.c b/u-boot/board/RPXClassic/eccx.c
new file mode 100644
index 0000000..e1f3f9d
--- /dev/null
+++ b/u-boot/board/RPXClassic/eccx.c
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Video support for the ECCX daughter board                                 */
+
+
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_VIDEO_SED13806
+#include <sed13806.h>
+
+
+/* Screen configurations: the initialization of the SD13806 depends on
+   screen and on display mode. We handle only 8bpp and 16 bpp modes          */
+
+/* ECCX board is supplied with a NEC NL6448BC20 screen                       */
+#ifdef CONFIG_NEC_NL6448BC20
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SED13806_8BPP
+static const S1D_REGS init_regs [] =
+{
+    {0x0001,0x00},   /* Miscellaneous Register */
+    {0x01FC,0x00},   /* Display Mode Register */
+    {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
+    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+    {0x0008,0xe5},   /* General IO Pins Control Register 0 */
+    {0x0009,0x1f},   /* General IO Pins Control Register 1 */
+    {0x0010,0x02},   /* Memory Clock Configuration Register */
+    {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
+    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+    {0x0021,0x04},   /* DRAM Refresh Rate Register */
+    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
+    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
+    {0x0020,0x80},   /* Memory Configuration Register */
+    {0x0030,0x25},   /* Panel Type Register */
+    {0x0031,0x00},   /* MOD Rate Register */
+    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
+    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+    {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+    {0x0040,0x03},   /* LCD Display Mode Register */
+    {0x0041,0x02},   /* LCD Miscellaneous Register */
+    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
+    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
+    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
+    {0x0046,0x40},   /* LCD Memory Address Offset Register 0 */
+    {0x0047,0x01},   /* LCD Memory Address Offset Register 1 */
+    {0x0048,0x00},   /* LCD Pixel Panning Register */
+    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+    {0x005B,0x00},   /* TV Output Control Register */
+    {0x0060,0x03},   /* CRT/TV Display Mode Register */
+    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+    {0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+    {0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+    {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
+    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+    {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
+    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+    {0x0100,0x00},   /* BitBlt Control Register 0 */
+    {0x0101,0x00},   /* BitBlt Control Register 1 */
+    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+    {0x0103,0x00},   /* BitBlt Operation Register */
+    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+    {0x0110,0x00},   /* BitBlt Width Register 0 */
+    {0x0111,0x00},   /* BitBlt Width Register 1 */
+    {0x0112,0x00},   /* BitBlt Height Register 0 */
+    {0x0113,0x00},   /* BitBlt Height Register 1 */
+    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
+    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
+    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+    {0x01E0,0x00},   /* Look-Up Table Mode Register */
+    {0x01E2,0x00},   /* Look-Up Table Address Register */
+    {0x01E4,0x00},   /* Look-Up Table Data Register */
+    {0x01F0,0x10},   /* Power Save Configuration Register */
+    {0x01F1,0x00},   /* Power Save Status Register */
+    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+    {0x01FC,0x01},   /* Display Mode Register */
+    {0, 0}
+};
+#endif /* CONFIG_VIDEO_SED13806_8BPP */
+
+#ifdef CONFIG_VIDEO_SED13806_16BPP
+
+static const S1D_REGS init_regs [] =
+{
+    {0x0001,0x00},   /* Miscellaneous Register */
+    {0x01FC,0x00},   /* Display Mode Register */
+    {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
+    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+    {0x0008,0xe5},   /* General IO Pins Control Register 0 */
+    {0x0009,0x1f},   /* General IO Pins Control Register 1 */
+    {0x0010,0x02},   /* Memory Clock Configuration Register */
+    {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
+    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+    {0x0021,0x04},   /* DRAM Refresh Rate Register */
+    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
+    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
+    {0x0020,0x80},   /* Memory Configuration Register */
+    {0x0030,0x25},   /* Panel Type Register */
+    {0x0031,0x00},   /* MOD Rate Register */
+    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
+    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+    {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+    {0x0040,0x05},   /* LCD Display Mode Register */
+    {0x0041,0x02},   /* LCD Miscellaneous Register */
+    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
+    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
+    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
+    {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+    {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+    {0x0048,0x00},   /* LCD Pixel Panning Register */
+    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+    {0x005B,0x00},   /* TV Output Control Register */
+    {0x0060,0x05},   /* CRT/TV Display Mode Register */
+    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+    {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+    {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+    {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
+    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+    {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
+    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+    {0x0100,0x00},   /* BitBlt Control Register 0 */
+    {0x0101,0x00},   /* BitBlt Control Register 1 */
+    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+    {0x0103,0x00},   /* BitBlt Operation Register */
+    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+    {0x0110,0x00},   /* BitBlt Width Register 0 */
+    {0x0111,0x00},   /* BitBlt Width Register 1 */
+    {0x0112,0x00},   /* BitBlt Height Register 0 */
+    {0x0113,0x00},   /* BitBlt Height Register 1 */
+    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
+    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
+    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+    {0x01E0,0x01},   /* Look-Up Table Mode Register */
+    {0x01E2,0x00},   /* Look-Up Table Address Register */
+    {0x01E4,0x00},   /* Look-Up Table Data Register */
+    {0x01F0,0x10},   /* Power Save Configuration Register */
+    {0x01F1,0x00},   /* Power Save Status Register */
+    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+    {0x01FC,0x01},   /* Display Mode Register */
+    {0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SED13806_16BPP */
+#endif /* CONFIG_NEC_NL6448BC20 */
+
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+
+/*-----------------------------------------------------------------------------
+ * video_get_info_str -- setup a board string: type, speed, etc.
+ * line_number= location to place info string beside logo
+ * info= buffer for info string
+ *-----------------------------------------------------------------------------
+ */
+void video_get_info_str (int line_number, char *info)
+{
+    if (line_number == 1) {
+	strcpy (info, " RPXClassic board");
+    }
+    else {
+	info [0] = '\0';
+    }
+
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_video_init -- init de l'EPSON, config du CS
+ *-----------------------------------------------------------------------------
+ */
+unsigned int board_video_init (void)
+{
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    /* Program ECCX registers                                                */
+    *(ECCX_CSR12) |= ECCX_860;
+    *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
+    *(ECCX_CSR8) |= ECCX_ENEPSON;
+
+    memctl->memc_or2 = SED13806_OR;
+    memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
+
+    return (SED13806_REG_ADDR);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_validate_screen --
+ *-----------------------------------------------------------------------------
+ */
+void board_validate_screen (unsigned int base)
+{
+    /* Activate the panel bias power                                         */
+    *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
+}
+/*-----------------------------------------------------------------------------
+ * board_get_regs --
+ *-----------------------------------------------------------------------------
+ */
+const S1D_REGS *board_get_regs (void)
+{
+    return (init_regs);
+}
+/*-----------------------------------------------------------------------------
+ * board_get_width --
+ *-----------------------------------------------------------------------------
+ */
+int board_get_width (void)
+{
+    return (DISPLAY_WIDTH);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_get_height --
+ *-----------------------------------------------------------------------------
+ */
+int board_get_height (void)
+{
+    return (DISPLAY_HEIGHT);
+}
+
+#endif /* CONFIG_VIDEO_SED13806 */
diff --git a/u-boot/board/RPXClassic/flash.c b/u-boot/board/RPXClassic/flash.c
new file mode 100644
index 0000000..f07d960
--- /dev/null
+++ b/u-boot/board/RPXClassic/flash.c
@@ -0,0 +1,447 @@
+/*
+ * (C)  Copyright 2001
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ * U-Boot port on RPXClassic LF (CLLF_BW31) board
+ *
+ * RPXClassic uses Am29DL323B flash memory with 2 banks
+ *
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:
+	    printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
+	    break;
+	default:
+	    printf ("Unknown Chip Type\n");
+	    break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Reset flash componeny                                             */
+	addr [0] = 0xf0f0f0f0;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0xAAAAAAAA ;
+	addr[0x555] = 0x55555555 ;
+	addr[0xAAA] = 0x90909090 ;
+
+	value = addr[0] ;
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_DL323B & 0x00FF00FF):
+	    info->flash_id += FLASH_AMDL323B;
+	    info->sector_count = 71;
+	    info->size = 0x01000000;            /* 16 Mb                     */
+
+	    break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	/* set sector offsets for bottom boot block type	*/
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00008000;
+	info->start[2] = base + 0x00010000;
+	info->start[3] = base + 0x00018000;
+	info->start[4] = base + 0x00020000;
+	info->start[5] = base + 0x00028000;
+	info->start[6] = base + 0x00030000;
+	info->start[7] = base + 0x00038000;
+	for (i = 8; i < info->sector_count; i++) {
+	    info->start[i] = base + ((i-7) * 0x00040000) ;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < 23; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr = (volatile unsigned long *)(info->start[i]);
+	    info->protect[i] = addr[4] & 1 ;
+	}
+	/* Check for protected sectors in the 2nd bank                       */
+	addr[0x100AAA] = 0xAAAAAAAA ;
+	addr[0x100555] = 0x55555555 ;
+	addr[0x100AAA] = 0x90909090 ;
+
+	for (i = 23; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr = (volatile unsigned long *)(info->start[i]);
+	    info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank 1                      */
+		addr = (volatile unsigned long *)info->start[23];
+
+		*addr = 0xF0F0F0F0;	/* reset bank 2                      */
+
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/RPXClassic/u-boot.lds b/u-boot/board/RPXClassic/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/RPXClassic/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RPXClassic/u-boot.lds.debug b/u-boot/board/RPXClassic/u-boot.lds.debug
new file mode 100644
index 0000000..c218905
--- /dev/null
+++ b/u-boot/board/RPXClassic/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RPXlite/Makefile b/u-boot/board/RPXlite/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/RPXlite/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/RPXlite/RPXlite.c b/u-boot/board/RPXlite/RPXlite.c
new file mode 100644
index 0000000..dca53a4
--- /dev/null
+++ b/u-boot/board/RPXlite/RPXlite.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * DRAM related UPMA register values are modified.
+ * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
+	0x3FBFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
+	0x3FBFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
+	0x3FFFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
+	0x0CFFCC00, 0x33FFCC27,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
+	0x3FFFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size10;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_mar = 0x00000000;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size
+	 * try 10 column mode
+	 */
+
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
+			    SDRAM_MAX_SIZE);
+
+	return (size10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
diff --git a/u-boot/board/RPXlite/flash.c b/u-boot/board/RPXlite/flash.c
new file mode 100644
index 0000000..788fcdf
--- /dev/null
+++ b/u-boot/board/RPXlite/flash.c
@@ -0,0 +1,524 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ *	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+/*	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR; */
+/*	volatile memctl8xx_t *memctl = &immap->im_memctl; */
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+/*
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+*/
+	/* Remap FLASH according to real size */
+/*%%%
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+%%%*/
+	/* Re-do sizing to get full correct info */
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/*%%% Size doubled by yooth */
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/*%%% sector start address modified */
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/RPXlite/u-boot.lds b/u-boot/board/RPXlite/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/RPXlite/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RPXlite/u-boot.lds.debug b/u-boot/board/RPXlite/u-boot.lds.debug
new file mode 100644
index 0000000..c218905
--- /dev/null
+++ b/u-boot/board/RPXlite/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RPXlite_dw/Makefile b/u-boot/board/RPXlite_dw/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/RPXlite_dw/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/RPXlite_dw/README b/u-boot/board/RPXlite_dw/README
new file mode 100644
index 0000000..14296b2
--- /dev/null
+++ b/u-boot/board/RPXlite_dw/README
@@ -0,0 +1,161 @@
+
+After following the step of Yoo. Jonghoon and Wolfgang Denk,
+I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
+
+There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW.
+
+Board(in U-Boot)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
+RPXlite				RPXlite CW		850	16MB	4MB
+RPXlite_DW		RPXlite DW(EP 823 H1 DW)	823e	64MB	16MB
+
+This fireware is specially coded for EmbeddedPlanet Co. Software Development
+Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
+
+It has the following three features:
+
+1. 64MHz/48MHz system frequence setting options.
+The default setting is 48MHz.To get a 64MHz u-boot,just add
+'64' in make command,like
+
+make distclean
+make RPXlite_DW_64_config
+make all
+
+2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM
+
+The default environment parameter is stored in FLASH because it is a common choice for
+environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
+didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
+home.Because of the possibility of using two firewares on this board,I didn't
+'disturb' EEPROM.To get NVRAM support,you may use the following build command:
+
+make distclean
+make RPXlite_DW_NVRAM_config
+make all
+
+3. LCD panel support
+
+To support the Platform better,I added LCD panel(NL6448BC20-08) function.
+For the convenience of debug, CONFIG_PERBOOT was supported. So you just
+perss ENTER if you want to get a serial console in boot downcounting.
+Then you can switch to LCD and serial console freely just typing
+'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
+
+To get a LCD support u-boot,you can do the following:
+
+make distclean
+make RPXlite_DW_LCD_config
+make all
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The basic make commands could be:
+
+make RPXlite_DW_config
+make RPXlite_DW_64_config
+make RPXlite_DW_LCD_config
+make RPXlite_DW_NVRAM_config
+
+BTW,you can combine the above features together and get a workable u-boot to meet your need.
+For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
+
+make RPXlite_DW_NVRAM_64_LCD_config
+make all
+
+So other combining make commands could be:
+
+make RPXlite_DW_NVRAM_64_config
+make RPXlite_DW_NVRAM_LCD_config
+make RPXlite_DW_64_LCD_config
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The boot process by "make RPXlite_DW_config" could be:
+
+U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
+
+CPU:   PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
+Board: RPXlite_DW
+DRAM:  64 MB
+FLASH: 16 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+u-boot>
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A word on the U-Boot enviroment variable setting and usage :
+
+In the beginning, you could just need very simple defult environment variable setting,
+like[include/configs/RPXlite.h] :
+
+#define CONFIG_BOOTCOMMAND                                                      \
+	"bootp; "                                                               \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+	"bootm"
+
+This is enough for kernel NFS test. But as debug process goes on, you would expect
+to save some time on environment variable setting and u-boot/kernel updating.
+So the default environment variable setting would become more complicated. Just like
+the one I did in include/configs/RPXlite_DW.h.
+
+Two u-boot commands, ku and uu, should be careful to use. They were designed to update
+kernel and u-boot image file respectively. You must tftp your image to default address
+'100000' and then use them correctly. Yeah, you can create your own command to do this
+job. :-) The example u-boot image updating process could be :
+
+u-boot>t 100000 RPXlite_DW_LCD.bin
+Using SCC ETHERNET device
+TFTP from server 172.16.115.6; our IP address is 172.16.115.7
+Filename 'RPXlite_DW_LCD.bin'.
+Load address: 0x100000
+Loading: #############################
+done
+Bytes transferred = 144700 (2353c hex)
+u-boot>run uu
+Un-Protect Flash Sectors 0-4 in Bank # 1
+Erase Flash Sectors 0-4 in Bank # 1
+.... done
+Copy to Flash... done
+ff000000: 27051956 552d426f 6f742031 2e312e32    '..VU-Boot 1.1.2
+ff000010: 20284175 67203239 20323030 34202d20     (Aug 29 2004 -
+ff000020: 31353a32 303a3238 29000000 00000000    15:20:28).......
+ff000030: 00000000 00000000 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: 00000000 00000000 00000000 00000000    ................
+ff000090: 00000000 00000000 00000000 00000000    ................
+ff0000a0: 00000000 00000000 00000000 00000000    ................
+ff0000b0: 00000000 00000000 00000000 00000000    ................
+ff0000c0: 00000000 00000000 00000000 00000000    ................
+ff0000d0: 00000000 00000000 00000000 00000000    ................
+ff0000e0: 00000000 00000000 00000000 00000000    ................
+ff0000f0: 00000000 00000000 00000000 00000000    ................
+u-boot updating finished
+u-boot>
+
+Also for environment updating, 'run eu' could let you erase OLD default environment variable
+and then use the working u-boot environment setting.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Finally, if you want to keep the serial port to possible debug on spot for deployment, you
+just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string
+defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot.
+
+I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
+I would particually thank Wolfgang Denk for his nice help.
+
+Enjoy,
+
+Sam Song, samsongshu@yahoo.com.cn
+Institute of Electrical Machinery and Controls
+Shanghai University
+
+Oct. 11, 2004
diff --git a/u-boot/board/RPXlite_dw/RPXlite_dw.c b/u-boot/board/RPXlite_dw/RPXlite_dw.c
new file mode 100644
index 0000000..364a316
--- /dev/null
+++ b/u-boot/board/RPXlite_dw/RPXlite_dw.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2004
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Sam Song
+ * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
+ * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
+ * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+static long int dram_size (long int, long int *, long int);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
+	_NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+	/* INIT sequence RAM WORDS
+	 * SDRAM Initialization (offset 0x36 in UPMA RAM)
+	 * The above definition uses the remaining space
+	 * to establish an initialization sequence,
+	 * which is executed by a RUN command.
+	 * The sequence is COMMAND INHIBIT(NOP),Precharge,
+	 * Load Mode Register,NOP,Auto Refresh.
+	 */
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite_DW\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
+
+	memctl->memc_mar  = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*Disable Periodic timer A. */
+
+	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
+
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	/*Enable Periodic timer A */
+
+	udelay (1000);
+
+	 /* Check Bank 0 Memory Size
+	  * try 9 column mode
+	  */
+
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+
+	udelay (1000);
+
+	return (size9);
+}
+
+void rpxlite_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
diff --git a/u-boot/board/RPXlite_dw/flash.c b/u-boot/board/RPXlite_dw/flash.c
new file mode 100644
index 0000000..91788af
--- /dev/null
+++ b/u-boot/board/RPXlite_dw/flash.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ *	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+/* Yes,Yoo.They do use other FLASH for the board.
+ *
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-Boot port on RPXlite DW version board
+ *
+ * By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
+ * The total FLASH has 16MB(4x4MB).
+ * I just made some necessary changes on the basis of Wolfgang and Yoo's job.
+ *
+ * June 8, 2004 */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions   vu_long : volatile unsigned long IN include/common.h
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* If Monitor is in the cope of FLASH,then
+	 * protect this area by default in case for
+	 * other occupation. [SAM] */
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+	flash_info[0].size = size_b0;
+	return (size_b0);
+}
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000);
+		}
+	} else {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL323B:    printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
+				break;
+	/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM]  */
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:			/* AMD_MANUFACT =0x00010001 in flash.h */
+		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;			/* device ID		*/
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/* Size doubled by yooth */
+		break;				/* => 4 MB		 */
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_DL323B & 0x00FF00FF):
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;                          /* => 16 MB(4x4MB)  */
+	/* AMD_ID_DL323B= 0x22532253  FLASH_AMDL323B= 0x0013
+	 * AMD_ID_DL323B could be found in <flash.h>.[SAM]
+	 * So we could get : flash_id = 0x00000013.
+	 * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+	/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
+	 * it means bottom boot flash. GOOD IDEA! [SAM]
+	 */
+
+	/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		/* info->protect[i] = addr[4] & 1 ; */
+		/* Mask it for disorder FLASH protection **[Sam]** */
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/RPXlite_dw/u-boot.lds b/u-boot/board/RPXlite_dw/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/RPXlite_dw/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RPXlite_dw/u-boot.lds.debug b/u-boot/board/RPXlite_dw/u-boot.lds.debug
new file mode 100644
index 0000000..a78d0b7
--- /dev/null
+++ b/u-boot/board/RPXlite_dw/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RRvision/Makefile b/u-boot/board/RRvision/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/RRvision/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/RRvision/RRvision.c b/u-boot/board/RRvision/RRvision.c
new file mode 100644
index 0000000..9d016c5
--- /dev/null
+++ b/u-boot/board/RRvision/RRvision.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Always return 1 (no second DRAM bank).
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board: RRvision ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long reg;
+	long int size8, size9;
+	long int size = 0;
+
+	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 the SDRAM bank 2 at physical address 0.
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size = size9;
+/*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {			/* back to 8 columns            */
+		size = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/*
+	 * No bank 1
+	 *
+	 * invalidate bank
+	 */
+	memctl->memc_br3 = 0;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/u-boot/board/RRvision/flash.c b/u-boot/board/RRvision/flash.c
new file mode 100644
index 0000000..fdbe928
--- /dev/null
+++ b/u-boot/board/RRvision/flash.c
@@ -0,0 +1,522 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	puts ("AMD ");			break;
+	case FLASH_MAN_FUJ:	puts ("FUJITSU ");		break;
+	default:		puts ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	puts ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	puts ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	puts ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	puts ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		puts ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	puts ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			puts ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	puts ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	switch (value) {
+	case AMD_ID_LV400B:
+	case AMD_ID_LV800B:
+	case AMD_ID_LV160B:
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+		break;
+	case AMD_ID_LV400T:
+	case AMD_ID_LV800T:
+	case AMD_ID_LV160T:
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+		break;
+	case AMD_ID_LV320B:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The first 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < 8)
+				?  2 * ( 8 << 10)
+				:  2 * (64 << 10);
+		}
+		break;
+	case AMD_ID_LV320T:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The last 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < (info->sector_count - 8))
+				?  2 * (64 << 10)
+				:  2 * ( 8 << 10);
+		}
+		break;
+	default:
+		return (0);
+		break;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			puts ("- missing\n");
+		} else {
+			puts ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		puts ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			puts ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	puts (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/RRvision/u-boot.lds b/u-boot/board/RRvision/u-boot.lds
new file mode 100644
index 0000000..5232e20
--- /dev/null
+++ b/u-boot/board/RRvision/u-boot.lds
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    . = env_offset;
+    common/env_embedded.o	(.ppcenv)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/RRvision/video_ad7179.h b/u-boot/board/RRvision/video_ad7179.h
new file mode 100644
index 0000000..f146738
--- /dev/null
+++ b/u-boot/board/RRvision/video_ad7179.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7179"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz	*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder	*/
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#else
+#error "NTSC mode is not supported"
+#endif
+
+static unsigned char video_encoder_data[] = {
+				0x05, /* Mode Register 0 */
+				0x11, /* Mode Register 1 */
+				0x20, /* Mode Register 2 */
+				0x0C, /* Mode Register 3 */
+				0x01, /* Mode Register 4 */
+				0x00, /* Reserved */
+				0x00, /* Reserved */
+				0x04, /* Timing Register 0 */
+				0x00, /* Timing Register 1 */
+				0xCB, /* Subcarrier Frequency Register 0 */
+				0x0A, /* Subcarrier Frequency Register 1 */
+				0x09, /* Subcarrier Frequency Register 2 */
+				0x2A, /* Subcarrier Frequency Register 3 */
+				0x00, /* Subcarrier Phase */
+				0x00, /* Closed Captioning Ext Reg 0 */
+				0x00, /* Closed Captioning Ext Reg 1 */
+				0x00, /* Closed Captioning Reg 0 */
+				0x00, /* Closed Captioning Reg 1 */
+				0x00, /* Pedestal Control Reg 0 */
+				0x00, /* Pedestal Control Reg 1 */
+				0x00, /* Pedestal Control Reg 2 */
+				0x00, /* Pedestal Control Reg 3 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00  /* Teletext Req. Control Reg */
+} ;
diff --git a/u-boot/board/Seagate/dockstar/Makefile b/u-boot/board/Seagate/dockstar/Makefile
new file mode 100644
index 0000000..bfcc6d9
--- /dev/null
+++ b/u-boot/board/Seagate/dockstar/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= dockstar.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/Seagate/dockstar/dockstar.c b/u-boot/board/Seagate/dockstar/dockstar.c
new file mode 100644
index 0000000..cab3a83
--- /dev/null
+++ b/u-boot/board/Seagate/dockstar/dockstar.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "dockstar.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
+			DOCKSTAR_OE_VAL_HIGH,
+			DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED	(1 << 14)
+#define ORANGE_LED	(1 << 15)
+#define BOTH_LEDS	(GREEN_LED | ORANGE_LED)
+#define NEITHER_LED	0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+	struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE;
+	u32 oe = readl(&r->oe) | BOTH_LEDS;
+	writel(oe & ~leds, &r->oe);	/* active low */
+	u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
+	writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case 15:		/* booting Linux */
+		set_leds(BOTH_LEDS, NEITHER_LED);
+		break;
+	case 64:		/* Ethernet initialization */
+		set_leds(GREEN_LED, GREEN_LED);
+		break;
+	default:
+		if (val < 0)	/* error */
+			set_leds(ORANGE_LED, ORANGE_LED);
+		break;
+	}
+}
diff --git a/u-boot/board/Seagate/dockstar/dockstar.h b/u-boot/board/Seagate/dockstar/dockstar.h
new file mode 100644
index 0000000..a2efe87
--- /dev/null
+++ b/u-boot/board/Seagate/dockstar/dockstar.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DOCKSTAR_H
+#define __DOCKSTAR_H
+
+#define DOCKSTAR_OE_LOW		(~(0))
+#define DOCKSTAR_OE_HIGH		(~(0))
+#define DOCKSTAR_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
+#define DOCKSTAR_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __DOCKSTAR_H */
diff --git a/u-boot/board/Seagate/dockstar/kwbimage.cfg b/u-boot/board/Seagate/dockstar/kwbimage.cfg
new file mode 100644
index 0000000..98b514d
--- /dev/null
+++ b/u-boot/board/Seagate/dockstar/kwbimage.cfg
@@ -0,0 +1,165 @@
+#
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/a3000/Makefile b/u-boot/board/a3000/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/a3000/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/a3000/README b/u-boot/board/a3000/README
new file mode 100644
index 0000000..f0e92c5
--- /dev/null
+++ b/u-boot/board/a3000/README
@@ -0,0 +1,17 @@
+U-Boot for Artis SBC-A3000
+---------------------------
+
+Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB)
+or 28F064J3A (8MB) chips.
+
+In board's notation, bank 0 is the one at the address of 0xFF000000.
+bank 1 is the one at the address of 0xFF800000
+
+On power-up the processor jumps to the address of 0xFFF00100, the last
+megabyte of the bank 0 of flash.
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0xFFF00000.  The environment space is located in flash separately from
+U-Boot, at the address of 0xFFFE0000.
+
+There is a National ns83815 10/100M ethernet controller on-board.
diff --git a/u-boot/board/a3000/a3000.c b/u-boot/board/a3000/a3000.c
new file mode 100644
index 0000000..ce2cf28
--- /dev/null
+++ b/u-boot/board/a3000/a3000.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * Modified during 2003 by
+ * Ken Chou, kchou@ieee.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <netdev.h>
+
+int checkboard (void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+
+}
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_a3000_config_table[] = {
+	/* vendor, device, class */
+	/* bus, dev, func */
+	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
+	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	/* dp83815 eth0 divice */
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x14, PCI_ANY_ID,		/* PCI slot1 */
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x15, PCI_ANY_ID,		/* PCI slot2 */
+	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
+				       PCI_ENET2_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x16, PCI_ANY_ID,		/* PCI slot3 */
+	  pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
+				       PCI_ENET3_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_a3000_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/a3000/flash.c b/u-boot/board/a3000/flash.c
new file mode 100644
index 0000000..b671ce7
--- /dev/null
+++ b/u-boot/board/a3000/flash.c
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc824x.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+
+/*---------------------------------------------------------------------*/
+#define DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, uchar *dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#define BS(b)     (b)
+#define BYTEME(x) ((x) & 0xFF)
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS;
+	unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+	{
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		DEBUGF("Get flash bank %d @ 0x%08lx\n", i, flash_banks[i]);
+/*
+		size_b[i] = flash_get_size((vu_char *)flash_banks[i], &flash_info[i]);
+*/
+		size_b[i] = flash_get_size((vu_char *) 0xff800000 , &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN)
+		{
+			printf ("## Unknown FLASH on Bank %d: "
+				"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+				i, flash_info[i].flash_id,
+				size_b[i], size_b[i]<<20);
+		}
+		else
+		{
+			DEBUGF("## Flash bank %d at 0x%08lx sizes: 0x%08lx \n",
+				i, flash_banks[i], size_b[i]);
+
+			flash_get_offsets (flash_banks[i], &flash_info[i]);
+			flash_info[i].size = size_b[i];
+		}
+	}
+
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN);
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE);
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	size = 0;
+	DEBUGF("## Final Flash bank sizes: ");
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+	{
+		DEBUGF("%08lx ", size_b[i]);
+		size += size_b[i];
+	}
+	DEBUGF("\n");
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:
+		    for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 0x00020000;		/* 128k per bank */
+		    }
+		    return;
+
+		default:
+		    printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
+		    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+			printf ("28F320J3A (32Mbit = 128K x 32)\n");
+			break;
+	case FLASH_28F640J3A:
+			printf ("28F640J3A (64Mbit = 128K x 64)\n");
+			break;
+	case FLASH_28F128J3A:
+			printf ("28F128J3A (128Mbit = 128K x 128)\n");
+			break;
+	default:
+			printf ("Unknown Chip Type\n");
+			break;
+	}
+
+#if 1
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+#endif
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+	vu_char manuf, device;
+
+	addr[0] = BS(0x90);
+	manuf = BS(addr[0]);
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf);
+
+	switch (manuf) {
+	case BYTEME(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case BYTEME(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case BYTEME(SST_MANUFACT):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case BYTEME(STM_MANUFACT):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case BYTEME(INTEL_MANUFACT):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = BS(0xFF);		/* restore read mode, (yes, BS is a NOP) */
+		return 0;			/* no or unknown flash	*/
+	}
+
+	device = BS(addr[2]);			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device);
+
+	switch (device) {
+	case BYTEME(INTEL_ID_28F320J3A):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* =>  4 MB		*/
+
+	case BYTEME(INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case BYTEME(INTEL_ID_28F128J3A):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = BS(0xFF);		/* restore read mode (yes, a NOP) */
+		return 0;			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = BS(0xFF);		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_char *addr = (vu_char *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = BS(0x50);	/* clear status register */
+			*addr = BS(0x20);	/* erase setup */
+			*addr = BS(0xD0);	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = BS(0xB0); /* suspend erase	  */
+					*addr = BS(0xFF); /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = BS(0xFF);	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	1	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	uchar *wp = (uchar *)addr;
+	int rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	while (cnt > 0) {
+		if ((rc = write_data(info, wp, *src)) != 0) {
+			return rc;
+		}
+		wp++;
+		src++;
+		cnt--;
+	}
+
+	return cnt;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, uchar *dest, uchar data)
+{
+	vu_char *addr = (vu_char *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((BS(*addr) & data) != data) {
+		return 2;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = BS(0x40);		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	start = get_timer (0);
+
+	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = BS(0xFF);	/* restore read mode */
+			return 1;
+		}
+	}
+
+	*addr = BS(0xFF);	/* restore read mode */
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/a4m072/Makefile b/u-boot/board/a4m072/Makefile
new file mode 100644
index 0000000..d3c31d6
--- /dev/null
+++ b/u-boot/board/a4m072/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/a4m072/a4m072.c b/u-boot/board/a4m072/a4m072.c
new file mode 100644
index 0000000..09a5a51
--- /dev/null
+++ b/u-boot/board/a4m072/a4m072.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <netdev.h>
+#include <led-display.h>
+#include <linux/err.h>
+
+#include "mt46v32m16.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: A4M072\n");
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	if ((rv = cpu_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize FEC.\n");
+
+	if ((rv = pci_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Initialize EEPROM write-protect GPIO pin.
+ */
+int misc_init_r(void)
+{
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	/* Enable GPIO pin */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
+	/* Set direction, output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
+	/* De-assert write enable */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+#endif
+	return 0;
+}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access */
+			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access */
+			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+						   CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+#endif
+
+#ifdef CONFIG_CMD_DISPLAY
+#define DISPLAY_BUF_SIZE	2
+static u8 display_buf[DISPLAY_BUF_SIZE];
+static u8 display_putc_pos;
+static u8 display_out_pos;
+
+void display_set(int cmd) {
+
+	if (cmd & DISPLAY_CLEAR) {
+		display_buf[0] = display_buf[1] = 0;
+	}
+
+	if (cmd & DISPLAY_HOME) {
+		display_putc_pos = 0;
+	}
+}
+
+#define SEG_A    (1<<0)
+#define SEG_B    (1<<1)
+#define SEG_C    (1<<2)
+#define SEG_D    (1<<3)
+#define SEG_E    (1<<4)
+#define SEG_F    (1<<5)
+#define SEG_G    (1<<6)
+#define SEG_P    (1<<7)
+#define SEG__    0
+
+/*
+ * +- A -+
+ * |     |
+ * F     B
+ * |     |
+ * +- G -+
+ * |     |
+ * E     C
+ * |     |
+ * +- D -+  P
+ *
+ * 0..9		index 0..9
+ * A..Z		index 10..35
+ * -		index 36
+ * _		index 37
+ * .		index 38
+ */
+
+#define SYMBOL_DASH		(36)
+#define SYMBOL_UNDERLINE	(37)
+#define SYMBOL_DOT		(38)
+
+static u8 display_char2seg7_tbl[]=
+{
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* 0 */
+	SEG_B | SEG_C,						/* 1 */
+	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* 2 */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_G,			/* 3 */
+	SEG_B | SEG_C | SEG_F | SEG_G,				/* 4 */
+	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* 5 */
+	SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,		/* 6 */
+	SEG_A | SEG_B | SEG_C,					/* 7 */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,	/* 8 */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* 9 */
+	SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,		/* A */
+	SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,			/* b */
+	SEG_A | SEG_D | SEG_E | SEG_F,				/* C */
+	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
+	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
+	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
+	0,					/* g - not displayed */
+	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
+	SEG_B | SEG_C,						/* I */
+	0,					/* J - not displayed */
+	0,					/* K - not displayed */
+	SEG_D | SEG_E | SEG_F,					/* L */
+	0,					/* m - not displayed */
+	0,					/* n - not displayed */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
+	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
+	0,					/* q - not displayed */
+	0,					/* r - not displayed */
+	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
+	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
+	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
+	0,					/* V - not displayed */
+	0,					/* w - not displayed */
+	0,					/* X - not displayed */
+	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
+	0,					/* Z - not displayed */
+	SEG_G,							/* - */
+	SEG_D,							/* _ */
+	SEG_P							/* . */
+};
+
+/* Convert char to the LED segments representation */
+static u8 display_char2seg7(char c)
+{
+	u8 val = 0;
+
+	if (c >= '0' && c <= '9')
+		c -= '0';
+	else if (c >= 'a' && c <= 'z')
+		c -= 'a' - 10;
+	else if (c >= 'A' && c <= 'Z')
+		c -= 'A' - 10;
+	else if (c == '-')
+		c = SYMBOL_DASH;
+	else if (c == '_')
+		c = SYMBOL_UNDERLINE;
+	else if (c == '.')
+		c = SYMBOL_DOT;
+	else
+		c = ' ';	/* display unsupported symbols as space */
+
+	if (c != ' ')
+		val = display_char2seg7_tbl[(int)c];
+
+	return val;
+}
+
+int display_putc(char c)
+{
+	if (display_putc_pos >= DISPLAY_BUF_SIZE)
+		return -1;
+
+	display_buf[display_putc_pos++] = display_char2seg7(c);
+	/* one-symbol message should be steady */
+	if (display_putc_pos == 1)
+		display_buf[display_putc_pos] = display_char2seg7(c);
+
+	return c;
+}
+
+/*
+ * Flush current symbol to the LED display hardware
+ */
+static inline void display_flush(void)
+{
+	u32 val = display_buf[display_out_pos];
+
+	val |= (val << 8) | (val << 16) | (val << 24);
+	out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
+}
+
+/*
+ * Output contents of the software display buffer to the LED display every 0.5s
+ */
+void board_show_activity(ulong timestamp)
+{
+	static ulong last;
+	static u8 once;
+
+	if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
+		display_flush();
+		display_out_pos ^= 1;
+		last = timestamp;
+		once = 1;
+	}
+}
+
+/*
+ * Empty fake function
+ */
+void show_activity(int arg)
+{
+}
+#endif
+#if defined (CONFIG_SHOW_BOOT_PROGRESS)
+static int a4m072_status2code(int status, char *buf)
+{
+	char c = 0;
+
+	if (((status > 0) && (status <= 8)) ||
+				((status >= 100) && (status <= 108)) ||
+				((status < 0) && (status >= -9)) ||
+				(status == -100) || (status == -101) ||
+				((status <= -103) && (status >= -113))) {
+		c = '5';
+	} else if (((status >= 9) && (status <= 14)) ||
+			((status >= 120) && (status <= 123)) ||
+			((status >= 125) && (status <= 129)) ||
+			((status >= -13) && (status <= -10)) ||
+			(status == -120) || (status == -122) ||
+			((status <= -124) && (status >= -127)) ||
+			(status == -129)) {
+		c = '8';
+	} else if (status == 15) {
+		c = '9';
+	} else if ((status <= -30) && (status >= -32)) {
+		c = 'A';
+	} else if (((status <= -35) && (status >= -40)) ||
+			((status <= -42) && (status >= -51)) ||
+			((status <= -53) && (status >= -58)) ||
+			(status == -64) ||
+			((status <= -80) && (status >= -83)) ||
+			(status == -130) || (status == -140) ||
+			(status == -150)) {
+		c = 'B';
+	}
+
+	if (c == 0)
+		return -EINVAL;
+
+	buf[0] = (status < 0) ? '-' : c;
+	buf[1] = c;
+
+	return 0;
+}
+
+void show_boot_progress(int status)
+{
+	char buf[2];
+
+	if (a4m072_status2code(status, buf) < 0)
+		return;
+
+	display_putc(buf[0]);
+	display_putc(buf[1]);
+	display_set(DISPLAY_HOME);
+	display_out_pos = 0;	/* reset output position */
+
+	/* we want to flush status 15 now */
+	if (status == 15)
+		display_flush();
+}
+#endif
diff --git a/u-boot/board/a4m072/mt46v32m16.h b/u-boot/board/a4m072/mt46v32m16.h
new file mode 100644
index 0000000..d7561fb
--- /dev/null
+++ b/u-boot/board/a4m072/mt46v32m16.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40010000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/u-boot/board/actux1/Makefile b/u-boot/board/actux1/Makefile
new file mode 100644
index 0000000..31e044b
--- /dev/null
+++ b/u-boot/board/actux1/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= actux1.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/actux1/actux1.c b/u-boot/board/actux1/actux1.c
new file mode 100644
index 0000000..e73aff8
--- /dev/null
+++ b/u-boot/board/actux1/actux1.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+#include <asm/io.h>
+#include <miiphy.h>
+
+#include "actux1_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+
+	/* Setup GPIO's for PCI INTA */
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
+
+	/* Setup GPIO's for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
+	*IXP425_GPIO_GPCLKR = 0x011001FF;
+
+	/* CS5: Debug port */
+	*IXP425_EXP_CS5 = 0x9d520003;
+	/* CS6: HwRel */
+	*IXP425_EXP_CS6 = 0x81860001;
+	/* CS7: LEDs */
+	*IXP425_EXP_CS7 = 0x80900003;
+
+	udelay (533);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+
+	ACTUX1_LED1 (2);
+	ACTUX1_LED2 (2);
+	ACTUX1_LED3 (0);
+	ACTUX1_LED4 (0);
+	ACTUX1_LED5 (0);
+	ACTUX1_LED6 (0);
+	ACTUX1_LED7 (0);
+
+	ACTUX1_HS (ACTUX1_HS_DCD);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board: AcTux-1 rev.");
+	putc (ACTUX1_BOARDREL + 'A' - 1);
+
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * 0 = reserved
+ * 1 = Rev. A
+ * 2 = Rev. B
+ *************************************************************************/
+u32 get_board_rev (void)
+{
+	return ACTUX1_BOARDREL;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+extern struct pci_controller hose;
+extern void pci_ixp_init (struct pci_controller *hose);
+
+void pci_init_board (void)
+{
+	extern void pci_ixp_init (struct pci_controller *hose);
+	pci_ixp_init (&hose);
+}
+#endif
+
+void reset_phy (void)
+{
+	u16 id1, id2;
+
+	/* initialize the PHY */
+	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+
+	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
+	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
+
+	id2 &= 0xFFF0;		/* mask out revision bits */
+
+	if (id1 == 0x13 && id2 == 0x78e0) {
+		/*
+		 * LXT971/LXT972 PHY: set LED outputs:
+		 * LED1(green) = Link/ACT,
+		 * LED2 (unused) = LINK,
+		 * LED3(red) = Coll
+		 */
+		miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
+	} else if (id1 == 0x143 && id2 == 0xbc30) {
+		/* BCM5241: default values are OK */
+	} else
+		printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
+}
diff --git a/u-boot/board/actux1/actux1_hw.h b/u-boot/board/actux1/actux1_hw.h
new file mode 100644
index 0000000..fe454c5
--- /dev/null
+++ b/u-boot/board/actux1/actux1_hw.h
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * hardware register definitions for the AcTux-1 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ACTUX1_HW_H
+#define _ACTUX1_HW_H
+
+/* 0 = LED off,1 = green, 2 = red, 3 = orange */
+#define ACTUX1_LED1(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
+#define ACTUX1_LED2(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
+#define ACTUX1_LED3(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
+#define ACTUX1_LED4(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
+#define ACTUX1_LED5(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
+#define ACTUX1_LED6(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
+#define ACTUX1_LED7(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
+#define ACTUX1_HS(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
+#define ACTUX1_HS_DCD	0x01
+#define ACTUX1_HS_DSR	0x02
+
+#define ACTUX1_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
+#define ACTUX1_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
+
+/* GPIO settings */
+#define CONFIG_SYS_GPIO_PCI1_INTA		2
+#define CONFIG_SYS_GPIO_PCI2_INTA		3
+#define CONFIG_SYS_GPIO_I2C_SDA		4
+#define CONFIG_SYS_GPIO_I2C_SCL		5
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
+
+#endif
diff --git a/u-boot/board/actux1/config.mk b/u-boot/board/actux1/config.mk
new file mode 100644
index 0000000..88634f7
--- /dev/null
+++ b/u-boot/board/actux1/config.mk
@@ -0,0 +1,6 @@
+CONFIG_SYS_TEXT_BASE = 0x00e00000
+
+# include NPE ethernet driver
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/u-boot/board/actux1/u-boot.lds b/u-boot/board/actux1/u-boot.lds
new file mode 100644
index 0000000..5c1ece7
--- /dev/null
+++ b/u-boot/board/actux1/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH (arm)
+ENTRY (_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN (4);
+	.text : {
+		arch/arm/cpu/ixp/start.o(.text)
+		lib/string.o(.text)
+		lib/vsprintf.o(.text)
+		arch/arm/lib/board.o(.text)
+		common/dlmalloc.o(.text)
+		arch/arm/cpu/ixp/cpu.o(.text)
+		. = env_offset;
+		common/env_embedded.o(.ppcenv)
+		* (.text)
+	}
+
+	. = ALIGN (4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN (4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN (4);
+	.got : {
+		*(.got)
+	}
+	. =.;
+	__u_boot_cmd_start =.;
+	.u_boot_cmd : {
+		*(.u_boot_cmd)
+	}
+	__u_boot_cmd_end =.;
+
+	. = ALIGN (4);
+	__bss_start =.;
+	.bss (NOLOAD): {
+		*(.bss)
+		. = ALIGN(4);
+	}
+	_end =.;
+}
diff --git a/u-boot/board/actux2/Makefile b/u-boot/board/actux2/Makefile
new file mode 100644
index 0000000..b026d94
--- /dev/null
+++ b/u-boot/board/actux2/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= actux2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/actux2/actux2.c b/u-boot/board/actux2/actux2.c
new file mode 100644
index 0000000..d6aaad6
--- /dev/null
+++ b/u-boot/board/actux2/actux2.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+#include <asm/io.h>
+
+#include <miiphy.h>
+
+#include "actux2_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+
+	/* Setup GPIO's for Interrupt inputs */
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+
+	/* Setup GPIO's for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
+	*IXP425_GPIO_GPCLKR = 0x011001FF;
+
+	/* CS1: IPAC-X */
+	*IXP425_EXP_CS1 = 0x94d10013;
+	/* CS5: Debug port */
+	*IXP425_EXP_CS5 = 0x9d520003;
+	/* CS6: HW release register */
+	*IXP425_EXP_CS6 = 0x81860001;
+	/* CS7: LEDs */
+	*IXP425_EXP_CS7 = 0x80900003;
+
+	udelay (533);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
+
+	ACTUX2_LED1 (1);
+	ACTUX2_LED2 (0);
+	ACTUX2_LED3 (0);
+	ACTUX2_LED4 (0);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board: AcTux-2 rev.");
+	putc (ACTUX2_BOARDREL + 'A' - 1);
+
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * 0 = reserved
+ * 1 = Rev. A
+ * 2 = Rev. B
+ *************************************************************************/
+u32 get_board_rev (void)
+{
+	return ACTUX2_BOARDREL;
+}
+
+void reset_phy (void)
+{
+	/* init IcPlus IP175C ethernet switch to native IP175C mode */
+	miiphy_write ("NPE0", 29, 31, 0x175C);
+}
diff --git a/u-boot/board/actux2/actux2_hw.h b/u-boot/board/actux2/actux2_hw.h
new file mode 100644
index 0000000..0f5ebcb
--- /dev/null
+++ b/u-boot/board/actux2/actux2_hw.h
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * hardware register definitions for the AcTux-2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ACTUX2_HW_H
+#define _ACTUX2_HW_H
+
+/* 0 = LED off,1 = green, 2 = red, 3 = orange */
+#define ACTUX2_LED1(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
+#define ACTUX2_LED2(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
+#define ACTUX2_LED3(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
+#define ACTUX2_LED4(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
+
+#define ACTUX2_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
+#define ACTUX2_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
+#define ACTUX2_OPTION	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_UNUSED4		4
+#define CONFIG_SYS_GPIO_UNUSED5		5
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_IPAC_INT		8
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
+
+#endif
diff --git a/u-boot/board/actux2/config.mk b/u-boot/board/actux2/config.mk
new file mode 100644
index 0000000..88634f7
--- /dev/null
+++ b/u-boot/board/actux2/config.mk
@@ -0,0 +1,6 @@
+CONFIG_SYS_TEXT_BASE = 0x00e00000
+
+# include NPE ethernet driver
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/u-boot/board/actux2/u-boot.lds b/u-boot/board/actux2/u-boot.lds
new file mode 100644
index 0000000..707c027
--- /dev/null
+++ b/u-boot/board/actux2/u-boot.lds
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH (arm)
+ENTRY (_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN (4);
+	.text : {
+		arch/arm/cpu/ixp/start.o(.text)
+		lib/string.o(.text)
+		lib/vsprintf.o(.text)
+		arch/arm/lib/board.o(.text)
+		common/dlmalloc.o(.text)
+		arch/arm/cpu/ixp/cpu.o(.text)
+
+		. = env_offset;
+		common/env_embedded.o (.ppcenv)
+
+		* (.text)
+	}
+
+	. = ALIGN (4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN (4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN (4);
+	.got : {
+		*(.got)
+	}
+
+	. =.;
+	__u_boot_cmd_start =.;
+	.u_boot_cmd : {
+		*(.u_boot_cmd)
+	}
+	__u_boot_cmd_end =.;
+
+	. = ALIGN (4);
+	__bss_start =.;
+	.bss (NOLOAD): {
+		*(.bss)
+		. = ALIGN(4);
+	}
+	_end =.;
+}
diff --git a/u-boot/board/actux3/Makefile b/u-boot/board/actux3/Makefile
new file mode 100644
index 0000000..97317fb
--- /dev/null
+++ b/u-boot/board/actux3/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= actux3.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/actux3/actux3.c b/u-boot/board/actux3/actux3.c
new file mode 100644
index 0000000..63bf365
--- /dev/null
+++ b/u-boot/board/actux3/actux3.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+#include <asm/io.h>
+
+#include <miiphy.h>
+
+#include "actux3_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
+
+	/*
+	 * Setup GPIO's for Interrupt inputs
+	 */
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+
+	/*
+	 * Setup GPIO's for 33MHz clock output
+	 */
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
+	*IXP425_GPIO_GPCLKR = 0x011001FF;
+
+	/* CS1: IPAC-X */
+	*IXP425_EXP_CS1 = 0x94d10013;
+	/* CS5: Debug port */
+	*IXP425_EXP_CS5 = 0x9d520003;
+	/* CS6: Release/Option register */
+	*IXP425_EXP_CS6 = 0x81860001;
+	/* CS7: LEDs */
+	*IXP425_EXP_CS7 = 0x80900003;
+
+	udelay (533);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
+
+	ACTUX3_LED1_RT (1);
+	ACTUX3_LED1_GN (0);
+	ACTUX3_LED2_RT (0);
+	ACTUX3_LED2_GN (0);
+	ACTUX3_LED3_RT (0);
+	ACTUX3_LED3_GN (0);
+	ACTUX3_LED4_GN (0);
+	ACTUX3_LED5_RT (0);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board: AcTux-3 rev.");
+	putc (ACTUX3_BOARDREL + 'A' - 1);
+
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * 0 = reserved
+ * 1 = Rev. A
+ * 2 = Rev. B
+ *************************************************************************/
+u32 get_board_rev (void)
+{
+	return ACTUX3_BOARDREL;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+void reset_phy (void)
+{
+	int i;
+
+	/* initialize the PHY */
+	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+
+	/* all LED outputs = Link/Act */
+	miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
+
+	/*
+	 * The Marvell 88E6060 switch comes up with all ports disabled.
+	 * set all ethernet switch ports to forwarding state
+	*/
+	for (i = 1; i <= 5; i++)
+		miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
+
+}
diff --git a/u-boot/board/actux3/actux3_hw.h b/u-boot/board/actux3/actux3_hw.h
new file mode 100644
index 0000000..c3c0cfc
--- /dev/null
+++ b/u-boot/board/actux3/actux3_hw.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * hardware register definitions for the AcTux-3 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ACTUX3_HW_H
+#define _ACTUX3_HW_H
+
+/* 0 = LED off,1 = ON */
+#define ACTUX3_LED1_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
+#define ACTUX3_LED1_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
+#define ACTUX3_LED2_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
+#define ACTUX3_LED2_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
+#define ACTUX3_LED3_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
+#define ACTUX3_LED3_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
+#define ACTUX3_LED4_GN(a)	writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
+#define ACTUX3_LED5_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
+
+#define ACTUX3_DBG_PORT		IXP425_EXP_BUS_CS5_BASE_PHYS
+#define ACTUX3_BOARDREL		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
+#define ACTUX3_OPTION		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
+
+/* GPIO settings */
+#define CONFIG_SYS_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_LED6_RT		4	/* Out */
+#define CONFIG_SYS_GPIO_LED6_GN		5	/* Out */
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
+
+#endif
diff --git a/u-boot/board/actux3/config.mk b/u-boot/board/actux3/config.mk
new file mode 100644
index 0000000..88634f7
--- /dev/null
+++ b/u-boot/board/actux3/config.mk
@@ -0,0 +1,6 @@
+CONFIG_SYS_TEXT_BASE = 0x00e00000
+
+# include NPE ethernet driver
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/u-boot/board/actux3/u-boot.lds b/u-boot/board/actux3/u-boot.lds
new file mode 100644
index 0000000..497ab97
--- /dev/null
+++ b/u-boot/board/actux3/u-boot.lds
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH (arm)
+ENTRY (_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN (4);
+	.text : {
+		arch/arm/cpu/ixp/start.o (.text)
+		lib/string.o (.text)
+		lib/vsprintf.o (.text)
+		arch/arm/lib/board.o (.text)
+		common/dlmalloc.o (.text)
+		arch/arm/cpu/ixp/cpu.o (.text)
+
+		. = env_offset;
+		common/env_embedded.o (.ppcenv)
+
+		* (.text)
+	}
+
+	. = ALIGN (4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN (4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN (4);
+	.got : {
+		*(.got)
+	}
+
+	. =.;
+	__u_boot_cmd_start =.;
+	.u_boot_cmd : {
+		*(.u_boot_cmd)
+	}
+	__u_boot_cmd_end =.;
+
+	. = ALIGN (4);
+	__bss_start =.;
+	.bss (NOLOAD): {
+		*(.bss)
+		. = ALIGN(4);
+	}
+	_end =.;
+}
diff --git a/u-boot/board/actux4/Makefile b/u-boot/board/actux4/Makefile
new file mode 100644
index 0000000..c631a5b
--- /dev/null
+++ b/u-boot/board/actux4/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= actux4.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/actux4/actux4.c b/u-boot/board/actux4/actux4.c
new file mode 100644
index 0000000..f373b58
--- /dev/null
+++ b/u-boot/board/actux4/actux4.c
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+
+#include <miiphy.h>
+
+#include "actux4_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
+
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+
+	/* led not populated on board*/
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
+
+	/* middle LED */
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
+
+	/* right LED */
+	/* weak pulldown = LED weak on */
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
+
+	/* Setup GPIO's for Interrupt inputs */
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
+
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
+
+	/* Setup GPIO's for 33MHz clock output */
+	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+
+	*IXP425_EXP_CS1 = 0xbd113c42;
+
+	udelay (10000);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	udelay (10000);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	udelay (10000);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+
+	return 0;
+}
+
+/* Check Board Identity */
+int checkboard (void)
+{
+	puts ("Board: AcTux-4\n");
+	return (0);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
+ * Flash 1 is an Intel *16 flash using the CFI driver.
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = 1;
+		info->chipwidth = 1;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/u-boot/board/actux4/actux4_hw.h b/u-boot/board/actux4/actux4_hw.h
new file mode 100644
index 0000000..afd1c06
--- /dev/null
+++ b/u-boot/board/actux4/actux4_hw.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * hardware register definitions for the AcTux-4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ACTUX4_HW_H
+#define _ACTUX4_HW_H
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPIO_USBINTA		0
+#define CONFIG_SYS_GPIO_USBINTB		1
+#define CONFIG_SYS_GPIO_USBINTC		2
+#define CONFIG_SYS_GPIO_nPWRON			3	/* Out */
+#define CONFIG_SYS_GPIO_I2C_SCL		4
+#define CONFIG_SYS_GPIO_I2C_SDA		5
+#define CONFIG_SYS_GPIO_PCI_INTB		6
+#define CONFIG_SYS_GPIO_BUTTON1		7
+#define CONFIG_SYS_GPIO_LED1			8	/* Out */
+#define CONFIG_SYS_GPIO_RTCINT			9
+#define CONFIG_SYS_GPIO_LED2			10	/* Out */
+#define CONFIG_SYS_GPIO_PCI_INTA		11
+#define CONFIG_SYS_GPIO_IORST			12	/* Out */
+#define CONFIG_SYS_GPIO_LED3			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
+
+#endif
diff --git a/u-boot/board/actux4/config.mk b/u-boot/board/actux4/config.mk
new file mode 100644
index 0000000..9cb838b
--- /dev/null
+++ b/u-boot/board/actux4/config.mk
@@ -0,0 +1,4 @@
+CONFIG_SYS_TEXT_BASE = 0x00e00000
+
+# include NPE ethernet driver
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
diff --git a/u-boot/board/adder/Makefile b/u-boot/board/adder/Makefile
new file mode 100644
index 0000000..70205f1
--- /dev/null
+++ b/u-boot/board/adder/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/adder/adder.c b/u-boot/board/adder/adder.c
new file mode 100644
index 0000000..87791de
--- /dev/null
+++ b/u-boot/board/adder/adder.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#if defined(CONFIG_OF_LIBFDT)
+	#include <libfdt.h>
+#endif
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
+ *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+phys_size_t initdram (int board_type)
+{
+	long int msize;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
+	udelay(200);
+
+	/* Run precharge from location 0x15 */
+	memctl->memc_mar = 0x0;
+	memctl->memc_mcr = 0x80002115;
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002830;
+	udelay(200);
+
+	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mar = 0x88;
+	memctl->memc_mcr = 0x80002116;
+	udelay(200);
+
+	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
+	memctl->memc_or1  |= ~(msize - 1);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+	puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+	puts("II\n");
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+}
+#endif
diff --git a/u-boot/board/adder/u-boot.lds b/u-boot/board/adder/u-boot.lds
new file mode 100644
index 0000000..26c9a22
--- /dev/null
+++ b/u-boot/board/adder/u-boot.lds
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text          :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/u-boot/board/afeb9260/Makefile b/u-boot/board/afeb9260/Makefile
new file mode 100644
index 0000000..895412d
--- /dev/null
+++ b/u-boot/board/afeb9260/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= afeb9260.o
+COBJS-y	+= partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/afeb9260/afeb9260.c b/u-boot/board/afeb9260/afeb9260.c
new file mode 100644
index 0000000..3c37557
--- /dev/null
+++ b/u-boot/board/afeb9260/afeb9260.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <netdev.h>
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void afeb9260_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 |
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#ifdef CONFIG_MACB
+static void afeb9260_macb_hw_init(void)
+{
+	unsigned long rstc;
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (rstc) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	afeb9260_nand_hw_init();
+#endif
+	at91_spi0_hw_init((1 << 0) | (1 << 1));
+#ifdef CONFIG_MACB
+	afeb9260_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/afeb9260/config.mk b/u-boot/board/afeb9260/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/u-boot/board/afeb9260/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/u-boot/board/afeb9260/partition.c b/u-boot/board/afeb9260/partition.c
new file mode 100644
index 0000000..be08f29
--- /dev/null
+++ b/u-boot/board/afeb9260/partition.c
@@ -0,0 +1,36 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
diff --git a/u-boot/board/alaska/Makefile b/u-boot/board/alaska/Makefile
new file mode 100644
index 0000000..d8aace2
--- /dev/null
+++ b/u-boot/board/alaska/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/alaska/alaska.c b/u-boot/board/alaska/alaska.c
new file mode 100644
index 0000000..89c1abd
--- /dev/null
+++ b/u-boot/board/alaska/alaska.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+void setupBat (ulong size)
+{
+	ulong batu, batl;
+	int blocksize = 0;
+
+	/* Flash 0 */
+#if defined (CONFIG_SYS_AMD_BOOT)
+	batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
+#else
+	batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
+#endif
+	batl = CONFIG_SYS_FLASH0_BASE | 0x22;
+	write_bat (IBAT0, batu, batl);
+	write_bat (DBAT0, batu, batl);
+
+	/* Flash 1 */
+#if defined (CONFIG_SYS_AMD_BOOT)
+	batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
+#else
+	batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
+#endif
+	batl = CONFIG_SYS_FLASH1_BASE | 0x22;
+	write_bat (IBAT1, batu, batl);
+	write_bat (DBAT1, batu, batl);
+
+	/* CPLD */
+	batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_CPLD_BASE | 0x22;
+	write_bat (IBAT2, 0, 0);
+	write_bat (DBAT2, batu, batl);
+
+	/* FPGA */
+	batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_FPGA_BASE | 0x22;
+	write_bat (IBAT3, 0, 0);
+	write_bat (DBAT3, batu, batl);
+
+	/* MBAR - Data only */
+	batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_MBAR | 0x22;
+	mtspr (IBAT4L, 0);
+	mtspr (IBAT4U, 0);
+	mtspr (DBAT4L, batl);
+	mtspr (DBAT4U, batu);
+
+	/* MBAR - SRAM */
+	batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_SRAM_BASE | 0x42;
+	mtspr (IBAT5L, batl);
+	mtspr (IBAT5U, batu);
+	mtspr (DBAT5L, batl);
+	mtspr (DBAT5U, batu);
+
+	if (size <= 0x800000)	/* 8MB */
+		blocksize = BATU_BL_8M;
+	else if (size <= 0x1000000)	/* 16MB */
+		blocksize = BATU_BL_16M;
+	else if (size <= 0x2000000)	/* 32MB */
+		blocksize = BATU_BL_32M;
+	else if (size <= 0x4000000)	/* 64MB */
+		blocksize = BATU_BL_64M;
+	else if (size <= 0x8000000)	/* 128MB */
+		blocksize = BATU_BL_128M;
+	else if (size <= 0x10000000)	/* 256MB */
+		blocksize = BATU_BL_256M;
+
+	/* Memory */
+	batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_SDRAM_BASE | 0x42;
+	mtspr (IBAT6L, batl);
+	mtspr (IBAT6U, batu);
+	mtspr (DBAT6L, batl);
+	mtspr (DBAT6U, batu);
+
+	/* memory size is less than 256MB */
+	if (size <= 0x10000000) {
+		/* Nothing */
+		batu = 0;
+		batl = 0;
+	} else {
+		size -= 0x10000000;
+		if (size <= 0x800000)	/* 8MB */
+			blocksize = BATU_BL_8M;
+		else if (size <= 0x1000000)	/* 16MB */
+			blocksize = BATU_BL_16M;
+		else if (size <= 0x2000000)	/* 32MB */
+			blocksize = BATU_BL_32M;
+		else if (size <= 0x4000000)	/* 64MB */
+			blocksize = BATU_BL_64M;
+		else if (size <= 0x8000000)	/* 128MB */
+			blocksize = BATU_BL_128M;
+		else if (size <= 0x10000000)	/* 256MB */
+			blocksize = BATU_BL_256M;
+
+		batu = (CONFIG_SYS_SDRAM_BASE +
+			0x10000000) | blocksize | BPP_RW | BPP_RX;
+		batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
+	}
+
+	mtspr (IBAT7L, batl);
+	mtspr (IBAT7U, batu);
+	mtspr (DBAT7L, batl);
+	mtspr (DBAT7U, batu);
+}
+
+phys_size_t initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+
+/* if iCache ad dCache is defined */
+#if defined(CONFIG_CMD_CACHE)
+/*    setupBat(size);*/
+#endif
+
+	return size;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Alaska MPC8220 Evaluation Board\n");
+
+	return 0;
+}
diff --git a/u-boot/board/alaska/flash.c b/u-boot/board/alaska/flash.c
new file mode 100644
index 0000000..aed3b6f
--- /dev/null
+++ b/u-boot/board/alaska/flash.c
@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH8
+
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+
+#define SWAP(x)         (x)
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT    0x89
+#define INTEL_ALT       0xB0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM   0x10
+#define INTEL_ERASE     0x20
+#define INTEL_CLEAR     0x50
+#define INTEL_LOCKBIT   0x60
+#define INTEL_PROTECT   0x01
+#define INTEL_STATUS    0x70
+#define INTEL_READID    0x90
+#define INTEL_CONFIRM   0xD0
+#define INTEL_RESET     0xFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED  0x80
+#define INTEL_OK        0x80
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x0555
+#define FLASH_CYCLE2    0x02aa
+
+#define WR_BLOCK        0x20
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static int write_data_block (flash_info_t * info, ulong src, ulong dest);
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+static unsigned char same_chip_banks (int bank1, int bank2);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	ulong fsize = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		memset (&flash_info[i], 0, sizeof (flash_info_t));
+
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
+					&flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
+					&flash_info[i]);
+			fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
+			flash_get_offsets (fsize, &flash_info[i]);
+			break;
+		case 2:
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
+					&flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
+			break;
+		case 3:
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
+					&flash_info[i]);
+			fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
+			flash_get_offsets (fsize, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+
+		/* get the h/w and s/w protection status in sync */
+		flash_sync_real_protect(&flash_info[i]);
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if defined (CONFIG_SYS_AMD_BOOT)
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[2]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_INTEL_BASE,
+		       CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[3]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_AMD_BASE,
+		       CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV1_ADDR,
+		       CONFIG_ENV1_ADDR + CONFIG_ENV1_SIZE - 1, &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[3]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_AM040:
+		printf ("AMD29F040B\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	FPWV value;
+	static int amd = 0;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	__asm__ ("sync");
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	__asm__ ("sync");
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD */
+	__asm__ ("sync");
+
+	udelay (100);
+
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		value = addr[1];
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		value = addr[2];
+		break;
+
+	default:
+		printf ("unknown\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;	/* => 16 MB     */
+		break;
+
+	case (FPW) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		if (amd == 0) {
+			info->sector_count = 7;
+			info->size = 0x00070000;	/* => 448 KB     */
+			amd = 1;
+		} else {
+			/* for Environment settings */
+			info->sector_count = 1;
+			info->size = PHYS_AMD_SECT_SIZE;	/* => 64 KB     */
+			amd = 0;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	if (value == (FPW) INTEL_ID_28F128J3A)
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+	else
+		addr[0] = (FPW) 0x00F000F0;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	case FLASH_AM040:
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 4 for 8-bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 4;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
+
+
+/*
+ * Checks if "bank1" and "bank2" are on the same chip.  Returns 1 if they
+ * are and 0 otherwise.
+ */
+static unsigned char same_chip_banks (int bank1, int bank2)
+{
+	unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
+		{1, 1, 0, 0},
+		{1, 1, 0, 0},
+		{0, 0, 1, 1},
+		{0, 0, 1, 1}
+	};
+	return same_chip[bank1][bank2];
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0, intel = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		type = (info->flash_id & FLASH_VENDMASK);
+		if ((type != FLASH_MAN_AMD)) {
+			printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+			return 1;
+		}
+	}
+
+	if (type == FLASH_MAN_INTEL)
+		intel = 1;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer (0);
+
+			if (intel) {
+				*addr = (FPW) 0x00500050;	/* clear status register */
+				*addr = (FPW) 0x00200020;	/* erase setup */
+				*addr = (FPW) 0x00D000D0;	/* erase confirm */
+			} else {
+				FPWV *base;	/* first address in bank */
+
+				base = (FPWV *) (CONFIG_SYS_AMD_BASE);
+				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+				base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+				*addr = (FPW) 0x00300030;	/* erase sector */
+			}
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					if (intel) {
+						*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+						*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					} else
+						*addr = (FPW) 0x00F000F0;	/* reset to read mode */
+
+					rcode = 1;
+					break;
+				}
+			}
+
+			if (intel) {
+				*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+				*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+			} else
+				*addr = (FPW) 0x00F000F0;	/* reset to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+	    {
+		FPW data = 0;	/* 16 or 32 bit word, matches flash bus width */
+		int bytes;	/* number of bytes to program in current word */
+		int left;	/* number of bytes left to program */
+		int i, res;
+
+		for (left = cnt, res = 0;
+		     left > 0 && res == 0;
+		     addr += sizeof (data), left -=
+		     sizeof (data) - bytes) {
+
+			bytes = addr & (sizeof (data) - 1);
+			addr &= ~(sizeof (data) - 1);
+
+			/* combine source and destination data so can program
+			 * an entire word of 16 or 32 bits
+			 */
+			for (i = 0; i < sizeof (data); i++) {
+				data <<= 8;
+				if (i < bytes || i - bytes >= left)
+					data += *((uchar *) addr + i);
+				else
+					data += *src++;
+			}
+
+			res = write_word_amd (info, (FPWV *) addr,
+					      data);
+		}
+		return res;
+	    }		/* case FLASH_MAN_AMD */
+
+	case FLASH_MAN_INTEL:
+	    {
+		ulong cp, wp;
+		FPW data;
+		int count, i, l, rc, port_width;
+
+		/* get lower word aligned address */
+		wp = addr;
+		port_width = 1;
+
+		/*
+		 * handle unaligned start bytes
+		 */
+		if ((l = addr - wp) != 0) {
+			data = 0;
+			for (i = 0, cp = wp; i < l; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+
+			for (; i < port_width && cnt > 0; ++i) {
+				data = (data << 8) | *src++;
+				--cnt;
+				++cp;
+			}
+
+			for (; cnt == 0 && i < port_width; ++i, ++cp)
+				data = (data << 8) | (*(uchar *) cp);
+
+			if ((rc =
+			     write_data (info, wp, SWAP (data))) != 0)
+				return (rc);
+			wp += port_width;
+		}
+
+		if (cnt > WR_BLOCK) {
+			/*
+			 * handle word aligned part
+			 */
+			count = 0;
+			while (cnt >= WR_BLOCK) {
+
+				if ((rc =
+				     write_data_block (info,
+						       (ulong) src,
+						       wp)) != 0)
+					return (rc);
+
+				wp += WR_BLOCK;
+				src += WR_BLOCK;
+				cnt -= WR_BLOCK;
+
+				if (count++ > 0x800) {
+					spin_wheel ();
+					count = 0;
+				}
+			}
+		}
+
+		if (cnt < WR_BLOCK) {
+			/*
+			 * handle word aligned part
+			 */
+			count = 0;
+			while (cnt >= port_width) {
+				data = 0;
+				for (i = 0; i < port_width; ++i)
+					data = (data << 8) | *src++;
+
+				if ((rc =
+				     write_data (info, wp,
+						 SWAP (data))) != 0)
+					return (rc);
+
+				wp += port_width;
+				cnt -= port_width;
+				if (count++ > 0x800) {
+					spin_wheel ();
+					count = 0;
+				}
+			}
+		}
+
+		if (cnt == 0)
+			return (0);
+
+		/*
+		 * handle unaligned tail bytes
+		 */
+		data = 0;
+		for (i = 0, cp = wp; i < port_width && cnt > 0;
+		     ++i, ++cp) {
+			data = (data << 8) | *src++;
+			--cnt;
+		}
+
+		for (; i < port_width; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		return (write_data (info, wp, SWAP (data)));
+	    }		/* case FLASH_MAN_INTEL */
+
+	}			/* switch */
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong)addr, (ulong)*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data_block (flash_info_t * info, ulong src, ulong dest)
+{
+	FPWV *srcaddr = (FPWV *) src;
+	FPWV *dstaddr = (FPWV *) dest;
+	ulong start;
+	int flag, i;
+
+	/* Check if Flash is (sufficiently) erased */
+	for (i = 0; i < WR_BLOCK; i++)
+		if ((*dstaddr++ & 0xff) != 0xff) {
+			printf ("not erased at %08lx (%lx)\n",
+				(ulong)dstaddr, (ulong)*dstaddr);
+			return (2);
+		}
+
+	dstaddr = (FPWV *) dest;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*dstaddr = (FPW) 0x00e800e8;	/* write block setup */
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*dstaddr = (FPW) 0x001f001f;	/* write 32 to buffer */
+	for (i = 0; i < WR_BLOCK; i++)
+		*dstaddr++ = *srcaddr++;
+
+	dstaddr -= 1;
+	*dstaddr = (FPW) 0x00d000d0;	/* write 32 to buffer */
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CONFIG_SYS_AMD_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	ulong start;
+	int i, j;
+	int curr_bank;
+	int bank;
+	int rc = 0;
+	FPWV *addr = (FPWV *) (info->start[sector]);
+	int flag = disable_interrupts ();
+
+	/*
+	 * 29F040B AMD flash does not support software protection/unprotection,
+	 * the only way to protect the AMD flash is marked it as prot bit.
+	 * This flash only support hardware protection, by supply or not supply
+	 * 12vpp to the flash
+	 */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		info->protect[sector] = prot;
+
+		return 0;
+	}
+
+	*addr = INTEL_CLEAR;	/* Clear status register    */
+	if (prot) {		/* Set sector lock bit      */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
+		*addr = INTEL_PROTECT;	/* set                      */
+	} else {		/* Clear sector lock bit    */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
+		*addr = INTEL_CONFIRM;	/* clear                    */
+	}
+
+	start = get_timer (0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+			printf ("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
+			(uint) addr, (uint) * addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot) {
+		/*
+		 * re-locking must be done for all banks that belong on one
+		 * FLASH chip, as all the sectors on the chip were unlocked
+		 * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
+		 * that banks never span chips, in particular chips which
+		 * support h/w protection differently).
+		 */
+
+		/* find the current bank number */
+		curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
+		for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
+			if (&flash_info[j] == info) {
+				curr_bank = j;
+			}
+		}
+		if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
+			printf("Error: can't determine bank number!\n");
+		}
+
+		for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
+			if (!same_chip_banks(curr_bank, bank)) {
+				continue;
+			}
+			info = &flash_info[bank];
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i]) {
+					start = get_timer (0);
+					addr = (FPWV *) (info->start[i]);
+					*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
+					*addr = INTEL_PROTECT;	/* set              */
+					while ((*addr & INTEL_FINISHED) !=
+					       INTEL_FINISHED) {
+						if (get_timer (start) >
+						    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+							printf ("Flash lock bit operation timed out\n");
+							rc = 1;
+							break;
+						}
+					}
+				}
+			}
+		}
+
+		/*
+		 * get the s/w sector protection status in sync with the h/w,
+		 * in case something went wrong during the re-locking.
+		 */
+		flash_sync_real_protect(info); /* resets flash to read  mode */
+	}
+
+	if (flag)
+		enable_interrupts ();
+
+	*addr = INTEL_RESET;	/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/u-boot/board/altera/common/AMDLV065D.c b/u-boot/board/altera/common/AMDLV065D.c
new file mode 100644
index 0000000..7a1b4d3
--- /dev/null
+++ b/u-boot/board/altera/common/AMDLV065D.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#if defined(CONFIG_NIOS)
+#include <nios.h>
+#else
+#include <asm/io.h>
+#endif
+
+#define SECTSZ		(64 * 1024)
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = CONFIG_SYS_FLASH_SIZE;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CONFIG_SYS_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+		fli->protect[i] = 1;
+	}
+
+	return (CONFIG_SYS_FLASH_SIZE);
+}
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	int erased;
+	unsigned long *addr;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		erased = 1;
+		addr = (unsigned long *) info->start[i];
+		for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+			if ( readl(addr++) != (unsigned long)-1) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	unsigned char *addr = (unsigned char *) info->start[0];
+	unsigned char *addr2;
+	int prot, sect;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (unsigned char *) info->start[sect];
+			writeb (0xaa, addr);
+			writeb (0x55, addr);
+			writeb (0x80, addr);
+			writeb (0xaa, addr);
+			writeb (0x55, addr);
+			writeb (0x30, addr2);
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait.
+			 */
+			start = get_timer (0);
+			while ( readb (addr2) != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+		}
+	}
+	printf ("\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((readb (dst) & b) != b) {
+			printf ("%02x : %02x\n", readb (dst), b);
+			return (2);
+		}
+
+		writeb (0xaa, cmd);
+		writeb (0x55, cmd);
+		writeb (0xa0, cmd);
+		writeb (b, dst);
+
+		/* Verify write */
+		start = get_timer (0);
+		while (readb (dst) != b) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/altera/common/cfide.c b/u-boot/board/altera/common/cfide.c
new file mode 100644
index 0000000..40d6a12
--- /dev/null
+++ b/u-boot/board/altera/common/cfide.c
@@ -0,0 +1,33 @@
+/*
+ * Altera CF drvier
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE)
+/* ide_set_reset for Altera CF interface */
+#define ALTERA_CF_CTL_STATUS			0
+#define ALTERA_CF_IDE_CTL			4
+#define ALTERA_CF_CTL_STATUS_PRESENT_MSK	(0x1)
+#define ALTERA_CF_CTL_STATUS_POWER_MSK		(0x2)
+#define ALTERA_CF_CTL_STATUS_RESET_MSK		(0x4)
+#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK	(0x8)
+#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK		(0x1)
+
+void ide_set_reset(int idereset)
+{
+	int i;
+	writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
+	       ALTERA_CF_CTL_STATUS_POWER_MSK,
+	       CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
+	/* wait 500 ms for power to stabilize */
+	for (i = 0; i < 500; i++)
+		udelay(1000);
+}
+#endif
diff --git a/u-boot/board/altera/common/epled.c b/u-boot/board/altera/common/epled.c
new file mode 100644
index 0000000..d019735
--- /dev/null
+++ b/u-boot/board/altera/common/epled.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+#include <status_led.h>
+
+/* The LED port is configured as output only, so we
+ * must track the state manually.
+ */
+static led_id_t val = 0;
+
+void __led_init (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (val, &pio->data);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (val, &pio->data);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+
+	val ^= mask;
+	writel (val, &pio->data);
+}
diff --git a/u-boot/board/altera/common/flash.c b/u-boot/board/altera/common/flash.c
new file mode 100644
index 0000000..83bb7c2
--- /dev/null
+++ b/u-boot/board/altera/common/flash.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	unsigned long size;
+	int erased;
+	volatile unsigned char *flash;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned char *) info->start[i];
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s", info->start[i], erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int prot, sect;
+	unsigned oldpri;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
+	/* NOTE: disabling interrupts on Nios can be very bad since it
+	 * also disables the LO_LIMIT exception. It's better here to
+	 * set the interrupt priority to 3 & restore it when we're done.
+	 */
+	oldpri = ipri (3);
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr = 0x80;
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr2 = 0x30;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+			oldpri = ipri (3); /* disallow non important irqs again */
+		}
+	}
+
+	printf ("\n");
+
+	/* Restore interrupt priority */
+	ipri (oldpri);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	unsigned oldpri;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((*dst & b) != b) {
+			printf ("%02x : %02x\n", *dst, b);
+			return (2);
+		}
+
+		/* Disable interrupts other than window underflow
+		 * (interrupt priority 2)
+		 */
+		oldpri = ipri (3);
+		*cmd = 0xaa;
+		*cmd = 0x55;
+		*cmd = 0xa0;
+		*dst = b;
+
+		/* Verify write */
+		start = get_timer (0);
+		while (*dst != b) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				ipri (oldpri);
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+		ipri (oldpri);
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/altera/common/sevenseg.c b/u-boot/board/altera/common/sevenseg.c
new file mode 100644
index 0000000..c53cec1
--- /dev/null
+++ b/u-boot/board/altera/common/sevenseg.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * common/sevenseg.c
+ *
+ * NIOS PIO based seven segment led support functions
+ */
+
+#include <common.h>
+#include <nios-io.h>
+
+#ifdef	CONFIG_SEVENSEG
+
+#define SEVENDEG_MASK_DP	((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+#if (SEVENSEG_ACTIVE == 0)
+static unsigned int sevenseg_portval = ~0;
+#else
+static unsigned int sevenseg_portval = 0;
+#endif
+#endif
+
+static int sevenseg_init_done = 0;
+
+static inline void __sevenseg_set_masked (unsigned int mask, int value)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+#if (SEVENSEG_ACTIVE == 0)
+	if (value)
+		sevenseg_portval &= ~mask;
+	else
+		sevenseg_portval |= mask;
+#else
+	if (value)
+		sevenseg_portval |= mask;
+	else
+		sevenseg_portval &= ~mask;
+#endif
+
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+#if (SEVENSEG_ACTIVE == 0)
+	if (value)
+		piop->data &= ~mask;
+	else
+		piop->data |= mask;
+#else
+	if (value)
+		piop->data |= mask;
+	else
+		piop->data &= ~mask;
+#endif
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_toggle_masked (unsigned int mask)
+{
+	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+	sevenseg_portval ^= mask;
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+	piop->data ^= mask;
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_set (unsigned int value)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+#if (SEVENSEG_ACTIVE == 0)
+	sevenseg_portval = (sevenseg_portval &   SEVENDEG_MASK_DP)
+		         | ((~value)         & (~SEVENDEG_MASK_DP));
+#else
+	sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
+		         | (value);
+#endif
+
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+#if (SEVENSEG_ACTIVE == 0)
+	piop->data = (piop->data &   SEVENDEG_MASK_DP)
+		   | ((~value)   & (~SEVENDEG_MASK_DP));
+#else
+	piop->data = (piop->data & SEVENDEG_MASK_DP)
+		   | (value);
+#endif
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_init (void)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+	__sevenseg_set(0);
+
+#ifndef	SEVENSEG_WRONLY	/* setup direction */
+
+	piop->direction |= mask;
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+
+void sevenseg_set(int value)
+{
+	unsigned char	digits[] = {
+		SEVENSEG_DIGITS_0,
+		SEVENSEG_DIGITS_1,
+		SEVENSEG_DIGITS_2,
+		SEVENSEG_DIGITS_3,
+		SEVENSEG_DIGITS_4,
+		SEVENSEG_DIGITS_5,
+		SEVENSEG_DIGITS_6,
+		SEVENSEG_DIGITS_7,
+		SEVENSEG_DIGITS_8,
+		SEVENSEG_DIGITS_9,
+		SEVENSEG_DIGITS_A,
+		SEVENSEG_DIGITS_B,
+		SEVENSEG_DIGITS_C,
+		SEVENSEG_DIGITS_D,
+		SEVENSEG_DIGITS_E,
+		SEVENSEG_DIGITS_F
+	};
+
+	if (!sevenseg_init_done) {
+		__sevenseg_init();
+		sevenseg_init_done++;
+	}
+
+	switch (value & SEVENSEG_MASK_CTRL) {
+
+		case SEVENSEG_RAW:
+			__sevenseg_set( (
+				(digits[((value & SEVENSEG_MASK_VAL) >>  4)] << 8) |
+				digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_OFF:
+			__sevenseg_set(0);
+			__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_SET_DPL:
+			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_SET_DPH:
+			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_RES_DPL:
+			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_RES_DPH:
+			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_TOG_DPL:
+			__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_TOG_DPH:
+			__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_LO:
+		case SEVENSEG_HI:
+		case SEVENSEG_STR:
+		default:
+			break;
+	}
+}
+
+#endif	/* CONFIG_SEVENSEG */
diff --git a/u-boot/board/altera/common/sevenseg.h b/u-boot/board/altera/common/sevenseg.h
new file mode 100644
index 0000000..cbfd2e7
--- /dev/null
+++ b/u-boot/board/altera/common/sevenseg.h
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * common/sevenseg.h
+ *
+ * NIOS PIO based seven segment led support functions
+ */
+
+#ifndef __DK1S10_SEVENSEG_H__
+#define __DK1S10_SEVENSEG_H__
+
+#ifdef	CONFIG_SEVENSEG
+
+/*
+ *  15                    8 7      0
+ * |-----------------------|--------|
+ * |   controll value      |  value |
+ * ----------------------------------
+ */
+#define	SEVENSEG_RAW		(int)(0)	/* write out byte value (hex) */
+#define	SEVENSEG_OFF		(int)( 1 << 8)	/* display switch off */
+#define	SEVENSEG_SET_DPL	(int)( 2 << 8)	/* set dp low  nibble */
+#define	SEVENSEG_SET_DPH	(int)( 3 << 8)	/* set dp high nibble */
+#define	SEVENSEG_RES_DPL	(int)( 4 << 8)	/* reset dp low  nibble */
+#define	SEVENSEG_RES_DPH	(int)( 5 << 8)	/* reset dp high nibble */
+#define	SEVENSEG_TOG_DPL	(int)( 6 << 8)	/* toggle dp low  nibble */
+#define	SEVENSEG_TOG_DPH	(int)( 7 << 8)	/* toggle dp high nibble */
+#define	SEVENSEG_LO		(int)( 8 << 8)	/* write out low nibble only */
+#define	SEVENSEG_HI		(int)( 9 << 8)	/* write out high nibble only */
+#define	SEVENSEG_STR		(int)(10 << 8)	/* write out a string */
+
+#define	SEVENSEG_MASK_VAL	(0xff)		/* only used by SEVENSEG_RAW */
+#define	SEVENSEG_MASK_CTRL	(~SEVENSEG_MASK_VAL)
+
+#ifdef	SEVENSEG_DIGIT_HI_LO_EQUAL
+
+#define	SEVENSEG_DIGITS_0	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	)
+#define	SEVENSEG_DIGITS_1	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	)
+#define	SEVENSEG_DIGITS_2	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_3	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_4	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_5	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_6	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_7	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	)
+#define	SEVENSEG_DIGITS_8	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_9	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_A	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_B	(	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_C	(	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_D	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_E	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_F	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+
+#else	/* !SEVENSEG_DIGIT_HI_LO_EQUAL */
+#error SEVENSEG: different pin asssignments not supported
+#endif
+
+void sevenseg_set(int value);
+
+#endif	/* CONFIG_SEVENSEG */
+
+#endif	/* __DK1S10_SEVENSEG_H__ */
diff --git a/u-boot/board/altera/nios2-generic/Makefile b/u-boot/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..6386352
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/Makefile
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_GPIO) += gpio.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y	:= text_base.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/altera/nios2-generic/config.mk b/u-boot/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..95e75af
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
diff --git a/u-boot/board/altera/nios2-generic/custom_fpga.h b/u-boot/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..f7f3853
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is generated by sopc-create-config-files.
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from std_1c20.sopc */
+
+/* cpu.data_master is a altera_nios2 */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_RESET_ADDR 0x00000000
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
+#define CONFIG_SYS_ICACHE_SIZE 4096
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_SIZE 2048
+#define CONFIG_SYS_DCACHELINE_SIZE 4
+
+/* sdram.s1 is a altera_avalon_new_sdram_controller */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000
+
+/* uart1.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BASE 0x82120840
+#define CONFIG_SYS_UART_FREQ 50000000
+#define CONFIG_SYS_UART_BAUD 115200
+
+/* lan91c111.s1 is a altera_avalon_lan91c111 */
+#define CONFIG_SMC91111_BASE 0x82110300
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+
+/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */
+#define EPCS_CONTROLLER_REG_BASE 0x82100200
+#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE }
+#define CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
+
+/* led_pio.s1 is a altera_avalon_pio */
+#define LED_PIO_BASE 0x82120870
+#define LED_PIO_WIDTH 8
+
+/* high_res_timer.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_BASE 0x82120820
+#define CONFIG_SYS_TIMER_IRQ 3
+#define CONFIG_SYS_TIMER_FREQ 50000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
+#define CONFIG_SYS_SRAM_BASE 0x02000000
+#define CONFIG_SYS_SRAM_SIZE 0x00100000
+
+/* sysid.control_slave is a altera_avalon_sysid */
+#define CONFIG_SYS_SYSID_BASE 0x821208b8
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/u-boot/board/altera/nios2-generic/gpio.c b/u-boot/board/altera/nios2-generic/gpio.c
new file mode 100644
index 0000000..4a30564
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/gpio.c
@@ -0,0 +1,71 @@
+/*
+ * board gpio driver
+ *
+ * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
+ * Licensed under the GPL-2 or later.
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_GPIO_BASE
+
+#define ALTERA_PIO_BASE LED_PIO_BASE
+#define ALTERA_PIO_WIDTH LED_PIO_WIDTH
+#define ALTERA_PIO_DATA (ALTERA_PIO_BASE + 0)
+#define ALTERA_PIO_DIR (ALTERA_PIO_BASE + 4)
+static u32 pio_data_reg;
+static u32 pio_dir_reg;
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+	return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+	u32 mask = 1 << gpio;
+	writel(pio_dir_reg &= ~mask, ALTERA_PIO_DIR);
+	return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+	u32 mask = 1 << gpio;
+	if (value)
+		pio_data_reg |= mask;
+	else
+		pio_data_reg &= ~mask;
+	writel(pio_data_reg, ALTERA_PIO_DATA);
+	writel(pio_dir_reg |= mask, ALTERA_PIO_DIR);
+	return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+	u32 mask = 1 << gpio;
+	if (pio_dir_reg & mask)
+		return (pio_data_reg & mask) ? 1 : 0;
+	else
+		return (readl(ALTERA_PIO_DATA) & mask) ? 1 : 0;
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+	u32 mask = 1 << gpio;
+	if (value)
+		pio_data_reg |= mask;
+	else
+		pio_data_reg &= ~mask;
+	writel(pio_data_reg, ALTERA_PIO_DATA);
+}
+
+int gpio_is_valid(int number)
+{
+	return ((unsigned)number) < ALTERA_PIO_WIDTH;
+}
+#endif
diff --git a/u-boot/board/altera/nios2-generic/nios2-generic.c b/u-boot/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..89848cf
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+	text_base_hook();
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+	rc += altera_tse_initialize(0,
+				    CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
+#endif
+#ifdef CONFIG_ETHOC
+	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/altera/nios2-generic/text_base.S b/u-boot/board/altera/nios2-generic/text_base.S
new file mode 100644
index 0000000..f236db1
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/text_base.S
@@ -0,0 +1,21 @@
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+	.text
+	/* text base used in link script u-boot.lds */
+	.global text_base
+	.equ text_base,CONFIG_SYS_MONITOR_BASE
+	/* dummy func to let linker include this file */
+	.global text_base_hook
+text_base_hook:
+	ret
+#endif
diff --git a/u-boot/board/altera/nios2-generic/u-boot.lds b/u-boot/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..d4be077
--- /dev/null
+++ b/u-boot/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = text_base;
+	.text :
+	{
+	  arch/nios2/cpu/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/u-boot/board/amcc/acadia/Makefile b/u-boot/board/amcc/acadia/Makefile
new file mode 100644
index 0000000..b277287
--- /dev/null
+++ b/u-boot/board/amcc/acadia/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o cmd_acadia.o memory.o pll.o
+SOBJS	=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/acadia/acadia.c b/u-boot/board/amcc/acadia/acadia.c
new file mode 100644
index 0000000..4825611
--- /dev/null
+++ b/u-boot/board/amcc/acadia/acadia.c
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+static void acadia_gpio_init(void)
+{
+	/*
+	 * GPIO0 setup (select GPIO or alternate function)
+	 */
+	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select */
+	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select */
+	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select */
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);  /* enable output driver for outputs */
+
+	/*
+	 * Ultra (405EZ) was nice enough to add another GPIO controller
+	 */
+	out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH);	/* output select */
+	out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
+	out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H);	/* input select */
+	out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
+	out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH);	/* three-state select */
+	out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
+	out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR);  /* enable output driver for outputs */
+}
+
+int board_early_init_f(void)
+{
+	unsigned int reg;
+
+#if !defined(CONFIG_NAND_U_BOOT)
+	/* don't reinit PLL when booting via I2C bootstrap option */
+	mfsdr(SDR0_PINSTP, reg);
+	if (reg != 0xf0000000)
+		board_pll_init_f();
+#endif
+
+	acadia_gpio_init();
+
+	/* Configure 405EZ for NAND usage */
+	mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
+	mfsdr(SDR0_ULTRA0, reg);
+	reg &= ~SDR_ULTRA0_CSN_MASK;
+	reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
+		SDR_ULTRA0_NDGPIOBP |
+		SDR_ULTRA0_EBCRDYEN |
+		SDR_ULTRA0_NFSRSTEN;
+	mtsdr(SDR0_ULTRA0, reg);
+
+	/* USB Host core needs this bit set */
+	mfsdr(SDR0_ULTRA1, reg);
+	mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
+
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000010);
+	mtdcr(UIC0PR, 0xFE7FFFF0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000010);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int misc_init_f(void)
+{
+	/* Set EPLD to take PHY out of reset */
+	out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
+	udelay(100000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u8 rev;
+
+	rev = in8(CONFIG_SYS_CPLD_BASE + 0);
+	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
diff --git a/u-boot/board/amcc/acadia/cmd_acadia.c b/u-boot/board/amcc/acadia/cmd_acadia.c
new file mode 100644
index 0000000..6936e51
--- /dev/null
+++ b/u-boot/board/amcc/acadia/cmd_acadia.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+static u8 boot_267_nor[] = {
+	0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
+	0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00
+};
+
+static u8 boot_267_nand[] = {
+	0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
+	0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00
+};
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u8 chip;
+	u8 *buf;
+	int cpu_freq;
+
+	if (argc < 3)
+		return cmd_usage(cmdtp);
+
+	cpu_freq = simple_strtol(argv[1], NULL, 10);
+	if (cpu_freq != 267) {
+		printf("Unsupported cpu-frequency - only 267 supported\n");
+		return 1;
+	}
+
+	/* use 0x50 as I2C EEPROM address for now */
+	chip = 0x50;
+
+	if ((strcmp(argv[2], "nor") != 0) &&
+	    (strcmp(argv[2], "nand") != 0)) {
+		printf("Unsupported boot-device - only nor|nand support\n");
+		return 1;
+	}
+
+	if (strcmp(argv[2], "nand") == 0) {
+		switch (cpu_freq) {
+		case 267:
+			buf = boot_267_nand;
+			break;
+		default:
+			break;
+		}
+	} else {
+		switch (cpu_freq) {
+		case 267:
+			buf = boot_267_nor;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (i2c_write(chip, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", chip);
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+	if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
+		printf("Error2 writing to EEPROM at address 0x%x\n", chip);
+
+	printf("Done\n");
+	printf("Please power-cycle the board for the changes to take effect\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootstrap,	3,	0,	do_bootstrap,
+	"program the I2C bootstrap EEPROM",
+	"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM"
+);
diff --git a/u-boot/board/amcc/acadia/config.mk b/u-boot/board/amcc/acadia/config.mk
new file mode 100644
index 0000000..2f2787f
--- /dev/null
+++ b/u-boot/board/amcc/acadia/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2007-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 405EZ Reference Platform (Acadia) board
+#
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
diff --git a/u-boot/board/amcc/acadia/memory.c b/u-boot/board/amcc/acadia/memory.c
new file mode 100644
index 0000000..703a668
--- /dev/null
+++ b/u-boot/board/amcc/acadia/memory.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern void board_pll_init_f(void);
+
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+static void cram_bcr_write(u32 wr_val)
+{
+	wr_val <<= 2;
+
+	/* set CRAM_CRE to 1 */
+	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
+
+	/* Write BCR to CRAM on CS1 */
+	out32(wr_val + 0x00200000, 0);
+	debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
+
+	/* Write BCR to CRAM on CS2 */
+	out32(wr_val + 0x02200000, 0);
+	debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
+
+	sync();
+	eieio();
+
+	/* set CRAM_CRE back to 0 (normal operation) */
+	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
+
+	return;
+}
+#endif
+
+phys_size_t initdram(int board_type)
+{
+#if defined(CONFIG_NAND_SPL)
+	u32 reg;
+
+	/* don't reinit PLL when booting via I2C bootstrap option */
+	mfsdr(SDR0_PINSTP, reg);
+	if (reg != 0xf0000000)
+		board_pll_init_f();
+#endif
+
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	int i;
+	u32 val;
+
+	/* 1. EBC need to program READY, CLK, ADV for ASync mode */
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+
+	/* 2. EBC in Async mode */
+	mtebc(PB1AP, 0x078F1EC0);
+	mtebc(PB2AP, 0x078F1EC0);
+	mtebc(PB1CR, 0x000BC000);
+	mtebc(PB2CR, 0x020BC000);
+
+	/* 3. Set CRAM in Sync mode */
+	cram_bcr_write(0x7012);		/* CRAM burst setting */
+
+	/* 4. EBC in Sync mode */
+	mtebc(PB1AP, 0x9C0201C0);
+	mtebc(PB2AP, 0x9C0201C0);
+
+	/* Set GPIO pins back to alternate function */
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+
+	/* Config EBC to use RDY */
+	mfsdr(SDR0_ULTRA0, val);
+	mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
+
+	/* Wait a short while, since for NAND booting this is too fast */
+	for (i=0; i<200000; i++)
+		;
+#endif
+
+	return (CONFIG_SYS_MBYTES_RAM << 20);
+}
diff --git a/u-boot/board/amcc/acadia/pll.c b/u-boot/board/amcc/acadia/pll.c
new file mode 100644
index 0000000..6327d6c
--- /dev/null
+++ b/u-boot/board/amcc/acadia/pll.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  200.0     |   4 (0x02)|
+	 * | PLB   |  133.3     |   6 (0x06)|
+	 * | OPB   |   66.6     |  12 (0x0C)|
+	 * | EBC   |   66.6     |  12 (0x0C)|
+	 * | SPI   |   66.6     |  12 (0x0C)|
+	 * | UART0 |   10.0     |  40 (0x28)|
+	 * | UART1 |   10.0     |  40 (0x28)|
+	 * | DAC   |    2.0     | 200 (0xC8)|
+	 * | ADC   |    2.0     | 200 (0xC8)|
+	 * | PWM   |  100.0     |   4 (0x04)|
+	 * | EMAC  |   25.0     |  16 (0x10)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(CPR0_PLLC, 0x0000033c);
+	mtcpr(CPR0_PLLD, 0x0c010200);
+	mtcpr(CPR0_PRIMAD, 0x04060c0c);
+	mtcpr(CPR0_PERD0, 0x000c0000);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPR0_CLKUPD, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  266.64    |   3       |
+	 * | PLB   |  159.98    |   5 (0x05)|
+	 * | OPB   |   79.99    |  10 (0x0A)|
+	 * | EBC   |   79.99    |  10 (0x0A)|
+	 * | SPI   |   79.99    |  10 (0x0A)|
+	 * | UART0 |   28.57    |   7 (0x07)|
+	 * | UART1 |   28.57    |   7 (0x07)|
+	 * | DAC   |   28.57    |   7 (0xA7)|
+	 * | ADC   |    4       |  50 (0x32)|
+	 * | PWM   |   28.57    |   7 (0x07)|
+	 * | EMAC  |    4       |  50 (0x32)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(CPR0_PLLC, 0x20000238);
+	mtcpr(CPR0_PLLD, 0x03010400);
+	mtcpr(CPR0_PRIMAD, 0x03050a0a);
+	mtcpr(CPR0_PERC0, 0x00000000);
+	mtcpr(CPR0_PERD0, 0x070a0707);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPR0_PERD1, 0x07323200);
+	mtcpr(CPR0_CLKUP, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  333.33    |   2       |
+	 * | PLB   |  166.66    |   4 (0x04)|
+	 * | OPB   |   83.33    |   8 (0x08)|
+	 * | EBC   |   83.33    |   8 (0x08)|
+	 * | SPI   |   83.33    |   8 (0x08)|
+	 * | UART0 |   16.66    |   5 (0x05)|
+	 * | UART1 |   16.66    |   5 (0x05)|
+	 * | DAC   |   ????     | 166 (0xA6)|
+	 * | ADC   |   ????     | 166 (0xA6)|
+	 * | PWM   |   41.66    |   3 (0x03)|
+	 * | EMAC  |   ????     |   3 (0x03)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(CPR0_PLLC, 0x0000033C);
+	mtcpr(CPR0_PLLD, 0x0a010000);
+	mtcpr(CPR0_PRIMAD, 0x02040808);
+	mtcpr(CPR0_PERD0, 0x02080505);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPR0_PERD1, 0xA6A60300);
+	mtcpr(CPR0_CLKUP, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------
+	 * | CLK   | FREQ (MHz) |
+	 * ----------------------
+	 * | CPU   |  100.00    |
+	 * | PLB   |  100.00    |
+	 * | OPB   |   12.00    |
+	 * | EBC   |   49.00    |
+	 * ----------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(CPR0_PLLC, 0x000003BC);
+	mtcpr(CPR0_PLLD, 0x06060600);
+	mtcpr(CPR0_PRIMAD, 0x02020004);
+	mtcpr(CPR0_PERD0, 0x04002828);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPR0_PERD1, 0xC8C81600);
+	mtcpr(CPR0_CLKUP, 0x40000000);
+}
+#endif				/* CPU_<speed>_405EZ */
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk(void)
+{
+	unsigned long cpr_plld;
+	unsigned long cpr_primad;
+	unsigned long primad_cpudv;
+	unsigned long pllFbkDiv;
+	unsigned long freqProcessor;
+
+	/*
+	 * Read PLL Mode registers
+	 */
+	mfcpr(CPR0_PLLD, cpr_plld);
+
+	/*
+	 * Read CPR_PRIMAD register
+	 */
+	mfcpr(CPR0_PRIMAD, cpr_primad);
+
+	/*
+	 * Determine CPU clock frequency
+	 */
+	primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+	if (primad_cpudv == 0)
+		primad_cpudv = 16;
+
+	/*
+	 * Determine FBK_DIV.
+	 */
+	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+	if (pllFbkDiv == 0)
+		pllFbkDiv = 256;
+
+	freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
+
+	return (freqProcessor);
+}
+#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/u-boot/board/amcc/acadia/u-boot-nand.lds b/u-boot/board/amcc/acadia/u-boot-nand.lds
new file mode 100644
index 0000000..c2a04c7
--- /dev/null
+++ b/u-boot/board/amcc/acadia/u-boot-nand.lds
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/env_embedded.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/amcc/bamboo/Makefile b/u-boot/board/amcc/bamboo/Makefile
new file mode 100644
index 0000000..2e7dc39
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/bamboo/bamboo.c b/u-boot/board/amcc/bamboo/bamboo.c
new file mode 100644
index 0000000..d4205e0
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/bamboo.c
@@ -0,0 +1,1928 @@
+/*
+ * (C) Copyright 2005-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <spd_sdram.h>
+#include <asm/ppc440.h>
+#include "bamboo.h"
+
+void ext_bus_cntlr_init(void);
+void configure_ppc440ep_pins(void);
+int is_nand_selected(void);
+
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+/*************************************************************************
+ *
+ * Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ *	13 row add bits, 10 column add bits (but 12 row used only).
+ *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ *	12 row add bits, 10 column add bits.
+ *	Prepare a subset (only the used ones) of SPD data
+ *
+ *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ *	the corresponding bank is divided by 2 due to number of Row addresses
+ *	12 in the ECC module
+ *
+ *  Assumes:	64 MB, ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+const unsigned char cfg_simulate_spd_eeprom[128] = {
+	0x80,    /* number of SPD bytes used: 128 */
+	0x08,    /*  total number bytes in SPD device = 256 */
+	0x07,    /* DDR ram */
+#ifdef CONFIG_DDR_ECC
+	0x0C,    /* num Row Addr: 12 */
+#else
+	0x0D,    /* num Row Addr: 13 */
+#endif
+	0x09,    /* numColAddr: 9  */
+	0x01,    /* numBanks: 1 */
+	0x20,    /* Module data width: 32 bits */
+	0x00,    /* Module data width continued: +0 */
+	0x04,    /* 2.5 Volt */
+	0x75,    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+	0x00,    /* SDRAM Access from clock */
+#ifdef CONFIG_DDR_ECC
+	0x02,    /* ECC ON : 02 OFF : 00 */
+#else
+	0x00,    /* ECC ON : 02 OFF : 00 */
+#endif
+	0x82,    /* refresh Rate Type: Normal (7.8us) + Self refresh */
+	0,
+	0,
+	0x01,    /* wcsbc = 1 */
+	0,
+	0,
+	0x0C,    /* casBit (2,2.5) */
+	0,
+	0,
+	0x00,    /* not registered: 0  registered : 0x02*/
+	0,
+	0xA0,    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+	0,
+	0x00,    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+	0,
+	0x50,    /* tRpNs = 20 ns  */
+	0,
+	0x50,    /* tRcdNs = 20 ns */
+	45,      /* tRasNs */
+#ifdef CONFIG_DDR_ECC
+	0x08,    /* bankSizeID: 32MB */
+#else
+	0x10,    /* bankSizeID: 64MB */
+#endif
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0
+};
+#endif
+
+#if 0
+{	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
+    {
+	/* GPIO Core 0 */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0	-> EBC_ADDR(7)	    DMA_REQ(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1	-> EBC_ADDR(6)	    DMA_ACK(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2	-> EBC_ADDR(5)	    DMA_EOT/TC(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3	-> EBC_ADDR(4)	    DMA_REQ(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4	-> EBC_ADDR(3)	    DMA_ACK(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6	-> EBC_CS_N(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7	-> EBC_CS_N(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8	-> EBC_CS_N(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9	 -> EBC_CS_N(4) */
+	{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->		    USB2D_RXVALID */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ	    USB2D_RXERROR */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->		    USB2D_TXVALID */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA	    USB2D_PAD_SUSPNDM */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK	    USB2D_XCVRSELECT */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
+    },
+    {
+	/* GPIO Core 1 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0	-> USB2D_OPMODE0 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1	-> USB2D_OPMODE1 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2	-> UART0_DCD_N	    UART1_DSR_CTS_N   UART2_SOUT */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3	-> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4	-> UART0_8PIN_CTS_N		      UART3_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5	-> UART0_RTS_N */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6	-> UART0_DTR_N	    UART1_SOUT */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7	-> UART0_RI_N	    UART1_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8	-> UIC_IRQ(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9	-> UIC_IRQ(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)	    DMA_ACK(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)	    DMA_EOT/TC(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)	    DMA_REQ(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)	    DMA_ACK(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)	    DMA_EOT/TC(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \	   Can be unselected thru TraceSelect Bit */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /	      in PowerPC440EP Chip */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
+    }
+};
+#endif
+
+/*----------------------------------------------------------------------------+
+  | EBC Devices Characteristics
+  |   Peripheral Bank Access Parameters	      -	  EBC0_BnAP
+  |   Peripheral Bank Configuration Register  -	  EBC0_BnCR
+  +----------------------------------------------------------------------------*/
+/* Small Flash */
+#define EBC0_BNAP_SMALL_FLASH				\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(6)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(1)			|	\
+	EBC0_BNAP_WBN_ENCODE(1)			|	\
+	EBC0_BNAP_WBF_ENCODE(3)			|	\
+	EBC0_BNAP_TH_ENCODE(1)			|	\
+	EBC0_BNAP_RE_ENABLED			|	\
+	EBC0_BNAP_SOR_DELAYED			|	\
+	EBC0_BNAP_BEM_WRITEONLY			|	\
+	EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_SMALL_FLASH_CS0			\
+	EBC0_BNCR_BAS_ENCODE(0xFFF00000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_8BIT
+
+#define EBC0_BNCR_SMALL_FLASH_CS4			\
+	EBC0_BNCR_BAS_ENCODE(0x87F00000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_8BIT
+
+/* Large Flash or SRAM */
+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM			\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(8)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(1)			|	\
+	EBC0_BNAP_WBN_ENCODE(1)			|	\
+	EBC0_BNAP_WBF_ENCODE(1)			|	\
+	EBC0_BNAP_TH_ENCODE(2)			|	\
+	EBC0_BNAP_SOR_DELAYED			|	\
+	EBC0_BNAP_BEM_RW			|	\
+	EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0		\
+	EBC0_BNCR_BAS_ENCODE(0xFF800000)	|	\
+	EBC0_BNCR_BS_8MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_16BIT
+
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4		\
+	EBC0_BNCR_BAS_ENCODE(0x87800000)	|	\
+	EBC0_BNCR_BS_8MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_16BIT
+
+/* NVRAM - FPGA */
+#define EBC0_BNAP_NVRAM_FPGA				\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(9)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(1)			|	\
+	EBC0_BNAP_WBN_ENCODE(1)			|	\
+	EBC0_BNAP_WBF_ENCODE(0)			|	\
+	EBC0_BNAP_TH_ENCODE(2)			|	\
+	EBC0_BNAP_RE_ENABLED			|	\
+	EBC0_BNAP_SOR_DELAYED			|	\
+	EBC0_BNAP_BEM_WRITEONLY			|	\
+	EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_NVRAM_FPGA_CS5			\
+	EBC0_BNCR_BAS_ENCODE(0x80000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_8BIT
+
+/* Nand Flash */
+#define EBC0_BNAP_NAND_FLASH				\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(3)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(0)			|	\
+	EBC0_BNAP_WBN_ENCODE(0)			|	\
+	EBC0_BNAP_WBF_ENCODE(0)			|	\
+	EBC0_BNAP_TH_ENCODE(1)			|	\
+	EBC0_BNAP_RE_ENABLED			|	\
+	EBC0_BNAP_SOR_NOT_DELAYED		|	\
+	EBC0_BNAP_BEM_RW			|	\
+	EBC0_BNAP_PEN_DISABLED
+
+
+#define EBC0_BNCR_NAND_FLASH_CS0	0xB8400000
+
+/* NAND0 */
+#define EBC0_BNCR_NAND_FLASH_CS1			\
+	EBC0_BNCR_BAS_ENCODE(0x90000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_32BIT
+/* NAND1 - Bank2 */
+#define EBC0_BNCR_NAND_FLASH_CS2			\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_32BIT
+
+/* NAND1 - Bank3 */
+#define EBC0_BNCR_NAND_FLASH_CS3			\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
+	EBC0_BNCR_BW_32BIT
+
+int board_early_init_f(void)
+{
+	ext_bus_cntlr_init();
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	out32(GPIO0_OSRL,  0x00000400);
+	out32(GPIO0_OSRH,  0x00000000);
+	out32(GPIO0_TSRL,  0x00000400);
+	out32(GPIO0_TSRH,  0x00000000);
+	out32(GPIO0_ISR1L, 0x00000000);
+	out32(GPIO0_ISR1H, 0x00000000);
+	out32(GPIO0_ISR2L, 0x00000000);
+	out32(GPIO0_ISR2H, 0x00000000);
+	out32(GPIO0_ISR3L, 0x00000000);
+	out32(GPIO0_ISR3H, 0x00000000);
+
+	out32(GPIO1_OSRL,  0x0C380000);
+	out32(GPIO1_OSRH,  0x00000000);
+	out32(GPIO1_TSRL,  0x0C380000);
+	out32(GPIO1_TSRH,  0x00000000);
+	out32(GPIO1_ISR1L, 0x0FC30000);
+	out32(GPIO1_ISR1H, 0x00000000);
+	out32(GPIO1_ISR2L, 0x0C010000);
+	out32(GPIO1_ISR2H, 0x00000000);
+	out32(GPIO1_ISR3L, 0x01400000);
+	out32(GPIO1_ISR3H, 0x00000000);
+
+	configure_ppc440ep_pins();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+	long dram_size;
+
+	dram_size = spd_sdram();
+
+	return dram_size;
+#else
+	return CONFIG_SYS_MBYTES_SDRAM << 20;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+  | is_powerpc440ep_pass1.
+  +----------------------------------------------------------------------------*/
+int is_powerpc440ep_pass1(void)
+{
+	unsigned long pvr;
+
+	pvr = get_pvr();
+
+	if (pvr == PVR_POWERPC_440EP_PASS1)
+		return TRUE;
+	else if (pvr == PVR_POWERPC_440EP_PASS2)
+		return FALSE;
+	else {
+		printf("brdutil error 3\n");
+		for (;;)
+			;
+	}
+
+	return(FALSE);
+}
+
+/*----------------------------------------------------------------------------+
+  | is_nand_selected.
+  +----------------------------------------------------------------------------*/
+int is_nand_selected(void)
+{
+#ifdef CONFIG_BAMBOO_NAND
+	return TRUE;
+#else
+	return FALSE;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+  | config_on_ebc_cs4_is_small_flash => from EPLD
+  +----------------------------------------------------------------------------*/
+unsigned char config_on_ebc_cs4_is_small_flash(void)
+{
+	/* Not implemented yet => returns constant value */
+	return TRUE;
+}
+
+/*----------------------------------------------------------------------------+
+  | Ext_bus_cntlr_init.
+  | Initialize the external bus controller
+  +----------------------------------------------------------------------------*/
+void ext_bus_cntlr_init(void)
+{
+	unsigned long sdr0_pstrp0, sdr0_sdstp1;
+	unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
+	int	      computed_boot_device = BOOT_DEVICE_UNKNOWN;
+	unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
+	unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
+	unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
+	unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
+	unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
+
+
+	/*-------------------------------------------------------------------------+
+	  |
+	  |  PART 1 : Initialize EBC Bank 5
+	  |  ==============================
+	  | Bank5 is always associated to the NVRAM/EPLD.
+	  | It has to be initialized prior to other banks settings computation since
+	  | some board registers values may be needed
+	  |
+	  +-------------------------------------------------------------------------*/
+	/* NVRAM - FPGA */
+	mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
+	mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
+
+	/*-------------------------------------------------------------------------+
+	  |
+	  |  PART 2 : Determine which boot device was selected
+	  |  =========================================
+	  |
+	  |  Read Pin Strap Register in PPC440EP
+	  |  In case of boot from IIC, read Serial Device Strap Register1
+	  |
+	  |  Result can either be :
+	  |   - Boot from EBC 8bits    => SMALL FLASH
+	  |   - Boot from EBC 16bits   => Large Flash or SRAM
+	  |   - Boot from NAND Flash
+	  |   - Boot from PCI
+	  |
+	  +-------------------------------------------------------------------------*/
+	/* Read Pin Strap Register in PPC440EP */
+	mfsdr(SDR0_PINSTP, sdr0_pstrp0);
+	bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+	/*-------------------------------------------------------------------------+
+	  |  PPC440EP Pass1
+	  +-------------------------------------------------------------------------*/
+	if (is_powerpc440ep_pass1() == TRUE) {
+		switch(bootstrap_settings) {
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+			/* Boot from Small Flash */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+			/* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
+			/* Boot from PCI */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+			/* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
+			/* Boot from Nand Flash */
+			computed_boot_device = BOOT_FROM_NAND_FLASH0;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+			/* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
+			/* Boot from Small Flash */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+			/* Read Serial Device Strap Register1 in PPC440EP */
+			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
+			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+			switch(boot_selection) {
+			case SDR0_SDSTP1_BOOT_SEL_EBC:
+				switch(ebc_boot_size) {
+				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+					break;
+				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+					computed_boot_device = BOOT_FROM_SMALL_FLASH;
+					break;
+				}
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_PCI:
+				computed_boot_device = BOOT_FROM_PCI;
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_NDFC:
+				computed_boot_device = BOOT_FROM_NAND_FLASH0;
+				break;
+			}
+			break;
+		}
+	}
+
+	/*-------------------------------------------------------------------------+
+	  |  PPC440EP Pass2
+	  +-------------------------------------------------------------------------*/
+	else {
+		switch(bootstrap_settings) {
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+			/* Boot from Small Flash */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+			/* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
+			/* Boot from PCI */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+			/* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
+			/* Boot from Nand Flash */
+			computed_boot_device = BOOT_FROM_NAND_FLASH0;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+			/* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
+			/* Boot from Large Flash or SRAM */
+			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+			/* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
+			/* Boot from Large Flash or SRAM */
+			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
+			/* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
+			/* Boot from PCI */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+			/* Default Strap Settings 5-7 */
+			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+			/* Read Serial Device Strap Register1 in PPC440EP */
+			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
+			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+			switch(boot_selection) {
+			case SDR0_SDSTP1_BOOT_SEL_EBC:
+				switch(ebc_boot_size) {
+				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+					break;
+				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+					computed_boot_device = BOOT_FROM_SMALL_FLASH;
+					break;
+				}
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_PCI:
+				computed_boot_device = BOOT_FROM_PCI;
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_NDFC:
+				computed_boot_device = BOOT_FROM_NAND_FLASH0;
+				break;
+			}
+			break;
+		}
+	}
+
+	/*-------------------------------------------------------------------------+
+	  |
+	  |  PART 3 : Compute EBC settings depending on selected boot device
+	  |  ======   ======================================================
+	  |
+	  | Resulting EBC init will be among following configurations :
+	  |
+	  |  - Boot from EBC 8bits => boot from SMALL FLASH selected
+	  |	       EBC-CS0	   = Small Flash
+	  |	       EBC-CS1,2,3 = NAND Flash or
+	  |			    Exp.Slot depending on Soft Config
+	  |	       EBC-CS4	   = SRAM/Large Flash or
+	  |			    Large Flash/SRAM depending on jumpers
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
+	  |	       EBC-CS0	   = SRAM/Large Flash or
+	  |			     Large Flash/SRAM depending on jumpers
+	  |	       EBC-CS1,2,3 = NAND Flash or
+	  |			     Exp.Slot depending on Software Configuration
+	  |	       EBC-CS4	   = Small Flash
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  |  - Boot from NAND Flash
+	  |	       EBC-CS0	   = NAND Flash0
+	  |	       EBC-CS1,2,3 = NAND Flash1
+	  |	       EBC-CS4	   = SRAM/Large Flash or
+	  |			     Large Flash/SRAM depending on jumpers
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  |    - Boot from PCI
+	  |	       EBC-CS0	   = ...
+	  |	       EBC-CS1,2,3 = NAND Flash or
+	  |			     Exp.Slot depending on Software Configuration
+	  |	       EBC-CS4	   = SRAM/Large Flash or
+	  |			     Large Flash/SRAM or
+	  |			     Small Flash depending on jumpers
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  +-------------------------------------------------------------------------*/
+
+	switch(computed_boot_device) {
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_SMALL_FLASH:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
+		ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
+		if ((is_nand_selected()) == TRUE) {
+			/* NAND Flash */
+			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+			ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		} else {
+			/* Expansion Slot */
+			ebc0_cs1_bnap_value = 0;
+			ebc0_cs1_bncr_value = 0;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		}
+		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+		ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
+		if ((is_nand_selected()) == TRUE) {
+			/* NAND Flash */
+			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		} else {
+			/* Expansion Slot */
+			ebc0_cs1_bnap_value = 0;
+			ebc0_cs1_bncr_value = 0;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		}
+		ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+		ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_NAND_FLASH0:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
+		ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+
+		ebc0_cs1_bnap_value = 0;
+		ebc0_cs1_bncr_value = 0;
+		ebc0_cs2_bnap_value = 0;
+		ebc0_cs2_bncr_value = 0;
+		ebc0_cs3_bnap_value = 0;
+		ebc0_cs3_bncr_value = 0;
+
+		/* Large Flash or SRAM */
+		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_PCI:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = 0;
+		ebc0_cs0_bncr_value = 0;
+
+		if ((is_nand_selected()) == TRUE) {
+			/* NAND Flash */
+			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		} else {
+			/* Expansion Slot */
+			ebc0_cs1_bnap_value = 0;
+			ebc0_cs1_bncr_value = 0;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		}
+
+		if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
+			/* Small Flash */
+			ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+			ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+		} else {
+			/* Large Flash or SRAM */
+			ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+			ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+		}
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_DEVICE_UNKNOWN:
+		/*------------------------------------------------------------------------- */
+		/* Error */
+		break;
+
+	}
+
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN	   |
+	      EBC0_CFG_PTD_ENABLED	  |
+	      EBC0_CFG_RTC_2048PERCLK	  |
+	      EBC0_CFG_EMPL_LOW		  |
+	      EBC0_CFG_EMPH_LOW		  |
+	      EBC0_CFG_CSTC_DRIVEN	  |
+	      EBC0_CFG_BPF_ONEDW	  |
+	      EBC0_CFG_EMS_8BIT		  |
+	      EBC0_CFG_PME_DISABLED	  |
+	      EBC0_CFG_PMT_ENCODE(0)	  );
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC Bank 0-4
+	  +-------------------------------------------------------------------------*/
+	/* EBC Bank0 */
+	mtebc(PB0AP, ebc0_cs0_bnap_value);
+	mtebc(PB0CR, ebc0_cs0_bncr_value);
+	/* EBC Bank1 */
+	mtebc(PB1AP, ebc0_cs1_bnap_value);
+	mtebc(PB1CR, ebc0_cs1_bncr_value);
+	/* EBC Bank2 */
+	mtebc(PB2AP, ebc0_cs2_bnap_value);
+	mtebc(PB2CR, ebc0_cs2_bncr_value);
+	/* EBC Bank3 */
+	mtebc(PB3AP, ebc0_cs3_bnap_value);
+	mtebc(PB3CR, ebc0_cs3_bncr_value);
+	/* EBC Bank4 */
+	mtebc(PB4AP, ebc0_cs4_bnap_value);
+	mtebc(PB4CR, ebc0_cs4_bncr_value);
+
+	return;
+}
+
+
+/*----------------------------------------------------------------------------+
+  | get_uart_configuration.
+  +----------------------------------------------------------------------------*/
+uart_config_nb_t get_uart_configuration(void)
+{
+	return (L4);
+}
+
+/*----------------------------------------------------------------------------+
+  | set_phy_configuration_through_fpga => to EPLD
+  +----------------------------------------------------------------------------*/
+void set_phy_configuration_through_fpga(zmii_config_t config)
+{
+
+	unsigned long fpga_selection_reg;
+
+	fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
+
+	switch(config)
+	{
+	case ZMII_CONFIGURATION_IS_MII:
+		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
+		break;
+	case ZMII_CONFIGURATION_IS_RMII:
+		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
+		break;
+	case ZMII_CONFIGURATION_IS_SMII:
+		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
+		break;
+	case ZMII_CONFIGURATION_UNKNOWN:
+	default:
+		break;
+	}
+	out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
+
+}
+
+/*----------------------------------------------------------------------------+
+  | scp_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void scp_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | iic1_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void iic1_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_a_b_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_a_b_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_a_b_unselect_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_a_b_unselect_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_c_d_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_c_d_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_c_d_unselect_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_c_d_unselect_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | usb2_device_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void usb2_device_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_1_reg;
+
+	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
+	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | usb2_device_reset_through_fpga.
+  +----------------------------------------------------------------------------*/
+void usb2_device_reset_through_fpga(void)
+{
+	/* Perform soft Reset pulse */
+	unsigned long fpga_reset_reg;
+	int i;
+
+	fpga_reset_reg = in8(FPGA_RESET_REG);
+	out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
+	for (i=0; i<500; i++)
+		udelay(1000);
+	out8(FPGA_RESET_REG,fpga_reset_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | usb2_host_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void usb2_host_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_1_reg;
+
+	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
+	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | ndfc_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void ndfc_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_1_reg;
+
+	fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
+	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
+	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
+	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | uart_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void uart_selection_in_fpga(uart_config_nb_t uart_config)
+{
+	/* FPGA register */
+	unsigned char	fpga_selection_3_reg;
+
+	/* Read FPGA Reagister */
+	fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
+
+	switch (uart_config)
+	{
+	case L1:
+		/* ----------------------------------------------------------------------- */
+		/* L1 configuration:	UART0 = 8 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+		break;
+
+	case L2:
+		/* ----------------------------------------------------------------------- */
+		/* L2 configuration:	UART0 = 4 pins */
+		/*			UART1 = 4 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+		break;
+
+	case L3:
+		/* ----------------------------------------------------------------------- */
+		/* L3 configuration:	UART0 = 4 pins */
+		/*			UART1 = 2 pins */
+		/*			UART2 = 2 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+		break;
+
+	case L4:
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+		break;
+
+	default:
+		/* Unsupported UART configuration number */
+		for (;;)
+			;
+		break;
+
+	}
+}
+
+
+/*----------------------------------------------------------------------------+
+  | init_default_gpio
+  +----------------------------------------------------------------------------*/
+void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	int i;
+
+	/* Init GPIO0 */
+	for(i=0; i<GPIO_MAX; i++)
+	{
+		gpio_tab[GPIO0][i].add	  = GPIO0_BASE;
+		gpio_tab[GPIO0][i].in_out = GPIO_DIS;
+		gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
+	}
+
+	/* Init GPIO1 */
+	for(i=0; i<GPIO_MAX; i++)
+	{
+		gpio_tab[GPIO1][i].add	  = GPIO1_BASE;
+		gpio_tab[GPIO1][i].in_out = GPIO_DIS;
+		gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
+	}
+
+	/* EBC_CS_N(5) - GPIO0_10 */
+	gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
+	gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
+
+	/* EBC_CS_N(4) - GPIO0_9 */
+	gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
+	gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_uart_ios
+  +------------------------------------------------------------------------------
+  |
+  | Set UART Configuration in PowerPC440EP
+  |
+  | +---------------------------------------------------------------------+
+  | | Configuartion   |	  Connector   | Nb of pins | Pins   | Associated  |
+  | |	 Number	      |	  Port Name   |	 available | naming |	CORE	  |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |	  L1	      |	  Port_A      |	    8	   | UART   | UART core 0 |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |	  L2	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
+  | |	 (L2D)	      |	  Port_B      |	    4	   | UART2  | UART core 1 |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |	  L3	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
+  | |	 (L3D)	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
+  | |		      |	  Port_C      |	    2	   | UART3  | UART core 2 |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |		      |	  Port_A      |	    2	   | UART1  | UART core 0 |
+  | |	  L4	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
+  | |	 (L4D)	      |	  Port_C      |	    2	   | UART3  | UART core 2 |
+  | |		      |	  Port_D      |	    2	   | UART4  | UART core 3 |
+  | +-----------------+---------------+------------+--------+-------------+
+  |
+  |  Involved GPIOs
+  |
+  | +------------------------------------------------------------------------------+
+  | |  GPIO   |	  Aternate 1	 | I/O |  Alternate 2	 | I/O | Alternate 3 | I/O |
+  | +---------+------------------+-----+-----------------+-----+-------------+-----+
+  | | GPIO1_2 | UART0_DCD_N	 |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |	O  |
+  | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |	I  |
+  | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA		 |  NA | UART3_SIN   |	I  |
+  | | GPIO1_5 | UART0_RTS_N	 |  O  | NA		 |  NA | UART3_SOUT  |	O  |
+  | | GPIO1_6 | UART0_DTR_N	 |  O  | UART1_SOUT	 |  O  | NA	     |	NA |
+  | | GPIO1_7 | UART0_RI_N	 |  I  | UART1_SIN	 |  I  | NA	     |	NA |
+  | +------------------------------------------------------------------------------+
+  |
+  |
+  +----------------------------------------------------------------------------*/
+
+void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	switch (uart_config)
+	{
+	case L1:
+		/* ----------------------------------------------------------------------- */
+		/* L1 configuration:	UART0 = 8 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_IN;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_IN;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
+
+		break;
+
+	case L2:
+		/* ----------------------------------------------------------------------- */
+		/* L2 configuration:	UART0 = 4 pins */
+		/*			UART1 = 4 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_IN;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+		break;
+
+	case L3:
+		/* ----------------------------------------------------------------------- */
+		/* L3 configuration:	UART0 = 4 pins */
+		/*			UART1 = 2 pins */
+		/*			UART2 = 2 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_IN;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+		break;
+
+	case L4:
+		/* ----------------------------------------------------------------------- */
+		/* L4 configuration:	UART0 = 2 pins */
+		/*			UART1 = 2 pins */
+		/*			UART2 = 2 pins */
+		/*			UART3 = 2 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_IN;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+		break;
+
+	default:
+		/* Unsupported UART configuration number */
+		printf("ERROR - Unsupported UART configuration number.\n\n");
+		for (;;)
+			;
+		break;
+
+	}
+
+	/* Set input Selection Register on Alt_Receive for UART Input Core */
+	out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
+	out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
+	out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
+}
+
+/*----------------------------------------------------------------------------+
+  | update_ndfc_ios(void).
+  +----------------------------------------------------------------------------*/
+void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	/* Update GPIO Configuration Table */
+	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */
+	gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(2) */
+	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+
+#if 0
+	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(3) */
+	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+  | update_zii_ios(void).
+  +----------------------------------------------------------------------------*/
+void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	/* Update GPIO Configuration Table */
+	gpio_tab[GPIO0][12].in_out = GPIO_IN;	    /* ZII_p0Rxd(0) */
+	gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][13].in_out = GPIO_IN;	    /* ZII_p0Rxd(1) */
+	gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][14].in_out = GPIO_IN;	    /* ZII_p0Rxd(2) */
+	gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][15].in_out = GPIO_IN;	    /* ZII_p0Rxd(3) */
+	gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][16].in_out = GPIO_OUT;	    /* ZII_p0Txd(0) */
+	gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][17].in_out = GPIO_OUT;	    /* ZII_p0Txd(1) */
+	gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][18].in_out = GPIO_OUT;	    /* ZII_p0Txd(2) */
+	gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][19].in_out = GPIO_OUT;	    /* ZII_p0Txd(3) */
+	gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][20].in_out = GPIO_IN;	    /* ZII_p0Rx_er */
+	gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][21].in_out = GPIO_IN;	    /* ZII_p0Rx_dv */
+	gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][22].in_out = GPIO_IN;	    /* ZII_p0Crs */
+	gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][23].in_out = GPIO_OUT;	    /* ZII_p0Tx_er */
+	gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][24].in_out = GPIO_OUT;	    /* ZII_p0Tx_en */
+	gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][25].in_out = GPIO_IN;	    /* ZII_p0Col */
+	gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | update_uic_0_3_irq_ios().
+  +----------------------------------------------------------------------------*/
+void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO1][8].in_out = GPIO_IN;	    /* UIC_IRQ(0) */
+	gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][9].in_out = GPIO_IN;	    /* UIC_IRQ(1) */
+	gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][10].in_out = GPIO_IN;	    /* UIC_IRQ(2) */
+	gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][11].in_out = GPIO_IN;	    /* UIC_IRQ(3) */
+	gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_uic_4_9_irq_ios().
+  +----------------------------------------------------------------------------*/
+void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO1][12].in_out = GPIO_IN;	    /* UIC_IRQ(4) */
+	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][13].in_out = GPIO_IN;	    /* UIC_IRQ(6) */
+	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* UIC_IRQ(7) */
+	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][15].in_out = GPIO_IN;	    /* UIC_IRQ(8) */
+	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][16].in_out = GPIO_IN;	    /* UIC_IRQ(9) */
+	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_dma_a_b_ios().
+  +----------------------------------------------------------------------------*/
+void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO1][12].in_out = GPIO_OUT;	    /* DMA_ACK(1) */
+	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][13].in_out = GPIO_BI;	    /* DMA_EOT/TC(1) */
+	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* DMA_REQ(0) */
+	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][15].in_out = GPIO_OUT;	    /* DMA_ACK(0) */
+	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][16].in_out = GPIO_BI;	    /* DMA_EOT/TC(0) */
+	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_dma_c_d_ios().
+  +----------------------------------------------------------------------------*/
+void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO0][0].in_out = GPIO_IN;	    /* DMA_REQ(2) */
+	gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][1].in_out = GPIO_OUT;	    /* DMA_ACK(2) */
+	gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][2].in_out = GPIO_BI;	    /* DMA_EOT/TC(2) */
+	gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][3].in_out = GPIO_IN;	    /* DMA_REQ(3) */
+	gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][4].in_out = GPIO_OUT;	    /* DMA_ACK(3) */
+	gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][5].in_out = GPIO_BI;	    /* DMA_EOT/TC(3) */
+	gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | update_ebc_master_ios().
+  +----------------------------------------------------------------------------*/
+void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* EXT_EBC_REQ */
+	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
+	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* EBC_EXT_ACK */
+	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* EBC_EXR_BUSREQ */
+	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_usb2_device_ios().
+  +----------------------------------------------------------------------------*/
+void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO0][26].in_out = GPIO_IN;	    /* USB2D_RXVALID */
+	gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* USB2D_RXERROR */
+	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][28].in_out = GPIO_OUT;	    /* USB2D_TXVALID */
+	gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* USB2D_PAD_SUSPNDM */
+	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* USB2D_XCVRSELECT */
+	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* USB2D_TERMSELECT */
+	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][0].in_out = GPIO_OUT;	    /* USB2D_OPMODE0 */
+	gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][1].in_out = GPIO_OUT;	    /* USB2D_OPMODE1 */
+	gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | update_pci_patch_ios().
+  +----------------------------------------------------------------------------*/
+void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
+	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  |   set_chip_gpio_configuration(unsigned char gpio_core,
+  |                               gpio_param_s (*gpio_tab)[GPIO_MAX])
+  |   Put the core impacted by clock modification and sharing in reset.
+  |   Config the select registers to resolve the sharing depending of the config.
+  |   Configure the GPIO registers.
+  |
+  +----------------------------------------------------------------------------*/
+void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+	unsigned char i=0, j=0, reg_offset = 0;
+	unsigned long gpio_reg, gpio_core_add;
+
+	/* GPIO config of the GPIOs 0 to 31 */
+	for (i=0; i<GPIO_MAX; i++, j++)
+	{
+		if (i == GPIO_MAX/2)
+		{
+			reg_offset = 4;
+			j = i-16;
+		}
+
+		gpio_core_add = gpio_tab[gpio_core][i].add;
+
+		if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
+		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+		{
+			switch (gpio_tab[gpio_core][i].alt_nb)
+			{
+			case GPIO_SEL:
+				break;
+
+			case GPIO_ALT1:
+				gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+				out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+				break;
+
+			case GPIO_ALT2:
+				gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+				out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+				break;
+
+			case GPIO_ALT3:
+				gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+				out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			}
+		}
+		if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
+		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+		{
+
+			switch (gpio_tab[gpio_core][i].alt_nb)
+			{
+			case GPIO_SEL:
+				break;
+			case GPIO_ALT1:
+				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			case GPIO_ALT2:
+				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			case GPIO_ALT3:
+				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			}
+		}
+	}
+}
+
+/*----------------------------------------------------------------------------+
+  | force_bup_core_selection.
+  +----------------------------------------------------------------------------*/
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
+{
+	/* Pointer invalid */
+	if (core_select_P == NULL)
+	{
+		printf("Configuration invalid pointer 1\n");
+		for (;;)
+			;
+	}
+
+	/* L4 Selection */
+	*(core_select_P+UART_CORE0)	       = CORE_SELECTED;
+	*(core_select_P+UART_CORE1)	       = CORE_SELECTED;
+	*(core_select_P+UART_CORE2)	       = CORE_SELECTED;
+	*(core_select_P+UART_CORE3)	       = CORE_SELECTED;
+
+	/* RMII Selection */
+	*(core_select_P+RMII_SEL)		= CORE_SELECTED;
+
+	/* External Interrupt 0-9 selection */
+	*(core_select_P+UIC_0_3)		= CORE_SELECTED;
+	*(core_select_P+UIC_4_9)		= CORE_SELECTED;
+
+	*(core_select_P+SCP_CORE)	        = CORE_SELECTED;
+	*(core_select_P+DMA_CHANNEL_CD)		= CORE_SELECTED;
+	*(core_select_P+PACKET_REJ_FUNC_AVAIL)	= CORE_SELECTED;
+	*(core_select_P+USB1_DEVICE)		= CORE_SELECTED;
+
+	if (is_nand_selected()) {
+		*(core_select_P+NAND_FLASH)	= CORE_SELECTED;
+	}
+
+	*config_val_P = CONFIG_IS_VALID;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | configure_ppc440ep_pins.
+  +----------------------------------------------------------------------------*/
+void configure_ppc440ep_pins(void)
+{
+	uart_config_nb_t uart_configuration;
+	config_validity_t config_val = CONFIG_IS_INVALID;
+
+	/* Create Core Selection Table */
+	core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
+		{
+			CORE_NOT_SELECTED,	/* IIC_CORE, */
+			CORE_NOT_SELECTED,	/* SPC_CORE, */
+			CORE_NOT_SELECTED,	/* DMA_CHANNEL_AB, */
+			CORE_NOT_SELECTED,	/* UIC_4_9, */
+			CORE_NOT_SELECTED,	/* USB2_HOST, */
+			CORE_NOT_SELECTED,	/* DMA_CHANNEL_CD, */
+			CORE_NOT_SELECTED,	/* USB2_DEVICE, */
+			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_AVAIL, */
+			CORE_NOT_SELECTED,	/* USB1_DEVICE, */
+			CORE_NOT_SELECTED,	/* EBC_MASTER, */
+			CORE_NOT_SELECTED,	/* NAND_FLASH, */
+			CORE_NOT_SELECTED,	/* UART_CORE0, */
+			CORE_NOT_SELECTED,	/* UART_CORE1, */
+			CORE_NOT_SELECTED,	/* UART_CORE2, */
+			CORE_NOT_SELECTED,	/* UART_CORE3, */
+			CORE_NOT_SELECTED,	/* MII_SEL, */
+			CORE_NOT_SELECTED,	/* RMII_SEL, */
+			CORE_NOT_SELECTED,	/* SMII_SEL, */
+			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_EN */
+			CORE_NOT_SELECTED,	/* UIC_0_3 */
+			CORE_NOT_SELECTED,	/* USB1_HOST */
+			CORE_NOT_SELECTED	/* PCI_PATCH */
+		};
+
+	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
+
+	/* Table Default Initialisation + FPGA Access */
+	init_default_gpio(gpio_tab);
+	set_chip_gpio_configuration(GPIO0, gpio_tab);
+	set_chip_gpio_configuration(GPIO1, gpio_tab);
+
+	/* Update Table */
+	force_bup_core_selection(ppc440ep_core_selection, &config_val);
+#if 0 /* test-only */
+	/* If we are running PIBS 1, force known configuration */
+	update_core_selection_table(ppc440ep_core_selection, &config_val);
+#endif
+
+	/*----------------------------------------------------------------------------+
+	  | SDR + ios table update + fpga initialization
+	  +----------------------------------------------------------------------------*/
+	unsigned long sdr0_pfc1	    = 0;
+	unsigned long sdr0_usb0	    = 0;
+	unsigned long sdr0_mfr	    = 0;
+
+	/* PCI Always selected */
+
+	/* I2C Selection */
+	if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+		iic1_selection_in_fpga();
+	}
+
+	/* SCP Selection */
+	if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+		scp_selection_in_fpga();
+	}
+
+	/* UIC 0:3 Selection */
+	if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
+	{
+		update_uic_0_3_irq_ios(gpio_tab);
+		dma_a_b_unselect_in_fpga();
+	}
+
+	/* UIC 4:9 Selection */
+	if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
+		update_uic_4_9_irq_ios(gpio_tab);
+	}
+
+	/* DMA AB Selection */
+	if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
+		update_dma_a_b_ios(gpio_tab);
+		dma_a_b_selection_in_fpga();
+	}
+
+	/* DMA CD Selection */
+	if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
+	{
+		update_dma_c_d_ios(gpio_tab);
+		dma_c_d_selection_in_fpga();
+	}
+
+	/* EBC Master Selection */
+	if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+		update_ebc_master_ios(gpio_tab);
+	}
+
+	/* PCI Patch Enable */
+	if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+		update_pci_patch_ios(gpio_tab);
+	}
+
+	/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
+	if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
+	{
+		/* Not Implemented in PowerPC 440EP Pass1-Pass2 */
+		printf("Invalid configuration => USB2 Host selected\n");
+		for (;;)
+			;
+		/*usb2_host_selection_in_fpga(); */
+	}
+
+	/* USB2.0 Device Selection */
+	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+	{
+		update_usb2_device_ios(gpio_tab);
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
+
+		mfsdr(SDR0_USB0, sdr0_usb0);
+		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
+		mtsdr(SDR0_USB0, sdr0_usb0);
+
+		usb2_device_selection_in_fpga();
+	}
+
+	/* USB1.1 Device Selection */
+	if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
+	{
+		mfsdr(SDR0_USB0, sdr0_usb0);
+		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
+		mtsdr(SDR0_USB0, sdr0_usb0);
+	}
+
+	/* USB1.1 Host Selection */
+	if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
+	{
+		mfsdr(SDR0_USB0, sdr0_usb0);
+		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
+		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
+		mtsdr(SDR0_USB0, sdr0_usb0);
+	}
+
+	/* NAND Flash Selection */
+	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
+	{
+		update_ndfc_ios(gpio_tab);
+
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
+		      SDR0_CUST0_NDFC_ENABLE	|
+		      SDR0_CUST0_NDFC_BW_8_BIT	|
+		      SDR0_CUST0_NDFC_ARE_MASK	|
+		      SDR0_CUST0_CHIPSELGAT_EN1 |
+		      SDR0_CUST0_CHIPSELGAT_EN2);
+#else
+		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
+		      SDR0_CUST0_NDFC_ENABLE	|
+		      SDR0_CUST0_NDFC_BW_8_BIT	|
+		      SDR0_CUST0_NDFC_ARE_MASK	|
+		      SDR0_CUST0_CHIPSELGAT_EN0 |
+		      SDR0_CUST0_CHIPSELGAT_EN2);
+#endif
+
+		ndfc_selection_in_fpga();
+	}
+	else
+	{
+		/* Set Mux on EMAC */
+		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
+	}
+
+	/* MII Selection */
+	if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
+	{
+		update_zii_ios(gpio_tab);
+		mfsdr(SDR0_MFR, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
+		mtsdr(SDR0_MFR, sdr0_mfr);
+
+		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
+	}
+
+	/* RMII Selection */
+	if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
+	{
+		update_zii_ios(gpio_tab);
+		mfsdr(SDR0_MFR, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+		mtsdr(SDR0_MFR, sdr0_mfr);
+
+		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
+	}
+
+	/* SMII Selection */
+	if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
+	{
+		update_zii_ios(gpio_tab);
+		mfsdr(SDR0_MFR, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
+		mtsdr(SDR0_MFR, sdr0_mfr);
+
+		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
+	}
+
+	/* UART Selection */
+	uart_configuration = get_uart_configuration();
+	switch (uart_configuration)
+	{
+	case L1:	 /* L1 Selection */
+		/* UART0 8 pins Only */
+		/*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;	  /* Chip Pb */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
+		break;
+	case L2:	 /* L2 Selection */
+		/* UART0 and UART1 4 pins */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		break;
+	case L3:	 /* L3 Selection */
+		/* UART0 4 pins, UART1 and UART2 2 pins */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		break;
+	case L4:	 /* L4 Selection */
+		/* UART0, UART1, UART2 and UART3 2 pins */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		break;
+	}
+	update_uart_ios(uart_configuration, gpio_tab);
+
+	/* UART Selection in all cases */
+	uart_selection_in_fpga(uart_configuration);
+
+	/* Packet Reject Function Available */
+	if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
+	{
+		/* Set UPR Bit in SDR0_PFC1 Register */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
+	}
+
+	/* Packet Reject Function Enable */
+	if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
+	{
+		mfsdr(SDR0_MFR, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+		mtsdr(SDR0_MFR, sdr0_mfr);
+	}
+
+	/* Perform effective access to hardware */
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+	set_chip_gpio_configuration(GPIO0, gpio_tab);
+	set_chip_gpio_configuration(GPIO1, gpio_tab);
+
+	/* USB2.0 Device Reset must be done after GPIO setting */
+	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+		usb2_device_reset_through_fpga();
+
+}
diff --git a/u-boot/board/amcc/bamboo/bamboo.h b/u-boot/board/amcc/bamboo/bamboo.h
new file mode 100644
index 0000000..f2b78a9
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/bamboo.h
@@ -0,0 +1,367 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*----------------------------------------------------------------------------+
+  | FPGA registers and bit definitions
+  +----------------------------------------------------------------------------*/
+/*
+ * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
+ * TLB initialization makes it correspond to logical address 0x80001FF0.
+ * => Done init_chip.s in bootlib
+ */
+#define FPGA_BASE_ADDR	0x80002000
+
+/*----------------------------------------------------------------------------+
+  | Board Jumpers Setting Register
+  |   Board Settings provided by jumpers
+  +----------------------------------------------------------------------------*/
+#define FPGA_SETTING_REG	    (FPGA_BASE_ADDR+0x3)
+/* Boot from small flash */
+#define	    FPGA_SET_REG_BOOT_SMALL_FLASH	    0x80
+/* Operational Flash versus SRAM position in Memory Map */
+#define	    FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK	    0x40
+#define	     FPGA_SET_REG_OP_CODE_FLASH_ABOVE	     0x40
+#define	     FPGA_SET_REG_SRAM_ABOVE		     0x00
+/* Boot From NAND Flash */
+#define	    FPGA_SET_REG_BOOT_NAND_FLASH_MASK	    0x40
+#define	    FPGA_SET_REG_BOOT_NAND_FLASH_SELECT	     0x00
+/* On Board PCI Arbiter Select */
+#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK   0x10
+#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL	    0x00
+
+/*----------------------------------------------------------------------------+
+  | Functions Selection Register 1
+  +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_1_REG	    (FPGA_BASE_ADDR+0x4)
+#define	    FPGA_SEL_1_REG_PHY_MASK	    0xE0
+#define	    FPGA_SEL_1_REG_MII		    0x80
+#define	    FPGA_SEL_1_REG_RMII		    0x40
+#define	    FPGA_SEL_1_REG_SMII		    0x20
+#define	    FPGA_SEL_1_REG_USB2_DEV_SEL	    0x10	   /* USB2 Device Selection */
+#define	    FPGA_SEL_1_REG_USB2_HOST_SEL    0x08	   /* USB2 Host Selection */
+#define	    FPGA_SEL_1_REG_NF_SELEC_MASK    0x07	   /* NF Selection Mask */
+#define	    FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04	   /* NF0 Selected by NF_CS1 */
+#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02	   /* NF1 Selected by NF_CS2 */
+#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01	   /* NF1 Selected by NF_CS3 */
+
+/*----------------------------------------------------------------------------+
+  | Functions Selection Register 2
+  +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_2_REG	    (FPGA_BASE_ADDR+0x5)
+#define	    FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80	   /* IIC1 / SCP Selection */
+#define	    FPGA_SEL2_REG_SEL_FRAM	    0x80	   /* FRAM on IIC1 bus selected - SCP Select */
+#define	    FPGA_SEL2_REG_SEL_SCP	    0x80	   /* Identical to SCP Selection */
+#define	    FPGA_SEL2_REG_SEL_IIC1	    0x00	   /* IIC1 Selection - Default Value */
+#define	    FPGA_SEL2_REG_SEL_DMA_A_B	    0x40	   /* DMA A & B channels selected */
+#define	    FPGA_SEL2_REG_SEL_DMA_C_D	    0x20	   /* DMA C & D channels selected */
+#define	    FPGA_SEL2_REG_DMA_EOT_TC_3_SEL  0x10	   /* 0 = EOT - input to 440EP */
+							   /* 1 = TC - output from 440EP */
+#define	    FPGA_SEL2_REG_DMA_EOT_TC_2_SEL  0x08	   /* 0 = EOT (input to 440EP) */
+							   /* 1 = TC (output from 440EP) */
+#define	    FPGA_SEL2_REG_SEL_GPIO_1	    0x04	   /* EBC_GPIO & USB2_GPIO selected */
+#define	    FPGA_SEL2_REG_SEL_GPIO_2	    0x02	   /* Ether._GPIO & UART_GPIO selected */
+#define	    FPGA_SEL2_REG_SEL_GPIO_3	    0x01	   /* DMA_GPIO & Trace_GPIO selected */
+
+/*----------------------------------------------------------------------------+
+  | Functions Selection Register 3
+  +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_3_REG	    (FPGA_BASE_ADDR+0x6)
+#define	    FPGA_SEL3_REG_EXP_SLOT_EN		    0x80    /* Expansion Slot enabled */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG_MASK	    0x70
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG1	    0x40    /* one 8_pin UART */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG2	    0x20    /* two 4_pin UARTs */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG3	    0x10    /* one 4_pin & two 2_pin UARTs */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG4	    0x08    /* four 2_pin UARTs */
+#define	    FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART   0x00    /* DTR/DSR mode for 4_pin_UART */
+#define	    FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART   0x04    /* RTS/CTS mode for 4_pin_UART */
+
+/*----------------------------------------------------------------------------+
+  | Soft Reset Register
+  +----------------------------------------------------------------------------*/
+#define FPGA_RESET_REG		    (FPGA_BASE_ADDR+0x7)
+#define	    FPGA_RESET_REG_RESET_USB20_DEV	    0x80    /* Hard Reset of the GT3200 */
+#define	    FPGA_RESET_REG_RESET_DISPLAY	    0x40    /* Hard Reset on Display Device */
+#define	    FPGA_RESET_REG_STATUS_LED_0		    0x08    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_1		    0x04    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_2		    0x02    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_3		    0x01    /* 1 = Led On */
+
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+#define	  SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_8BIT  0x00000000    /* EBC  8 Bits */
+
+#define	  SDR0_SDSTP1_BOOT_SEL_MASK    0x00001800   /* Boot device Selection Mask */
+#define	  SDR0_SDSTP1_BOOT_SEL_EBC     0x00000000     /* EBC */
+#define	  SDR0_SDSTP1_BOOT_SEL_PCI     0x00000800     /* PCI */
+#define	  SDR0_SDSTP1_BOOT_SEL_NDFC    0x00001000     /* NDFC */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0		     0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000  /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000  /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000  /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000  /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000  /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000  /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000  /* Default strap settings 7 */
+
+/*----------------------------------------------------------------------------+
+| EBC Configuration Register - EBC0_CFG
++----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED	    0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK	    0x38000000
+#define EBC0_CFG_RTC_16PERCLK	    0x00000000
+#define EBC0_CFG_RTC_32PERCLK	    0x08000000
+#define EBC0_CFG_RTC_64PERCLK	    0x10000000
+#define EBC0_CFG_RTC_128PERCLK	    0x18000000
+#define EBC0_CFG_RTC_256PERCLK	    0x20000000
+#define EBC0_CFG_RTC_512PERCLK	    0x28000000
+#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
+#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW	    0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
+#define EBC0_CFG_EMPL_HIGH	    0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW	    0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
+#define EBC0_CFG_EMPH_HIGH	    0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW	    0x00000000
+#define EBC0_CFG_BPF_TWODW	    0x00100000
+#define EBC0_CFG_BPF_FOURDW	    0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT	    0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED	    0x00000000
+#define EBC0_CFG_PME_ENABLED	    0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Configuration Register - EBC0_BnCR
++----------------------------------------------------------------------------*/
+/* BAS - Base Address Select */
+#define EBC0_BNCR_BAS_ENCODE(n)		((((unsigned long)(n))&0xFFF00000)<<0)
+/* BS - Bank Size */
+#define EBC0_BNCR_BS_MASK	0x000E0000
+#define EBC0_BNCR_BS_1MB	0x00000000
+#define EBC0_BNCR_BS_2MB	0x00020000
+#define EBC0_BNCR_BS_4MB	0x00040000
+#define EBC0_BNCR_BS_8MB	0x00060000
+#define EBC0_BNCR_BS_16MB	0x00080000
+#define EBC0_BNCR_BS_32MB	0x000A0000
+#define EBC0_BNCR_BS_64MB	0x000C0000
+#define EBC0_BNCR_BS_128MB	0x000E0000
+/* BU - Bank Usage */
+#define EBC0_BNCR_BU_MASK	0x00018000
+#define EBC0_BNCR_BU_RO		    0x00008000
+#define EBC0_BNCR_BU_WO		    0x00010000
+#define EBC0_BNCR_BU_RW		0x00018000
+/* BW - Bus Width */
+#define EBC0_BNCR_BW_MASK	0x00006000
+#define EBC0_BNCR_BW_8BIT	0x00000000
+#define EBC0_BNCR_BW_16BIT	0x00002000
+#define EBC0_BNCR_BW_32BIT	0x00004000
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Access Parameters - EBC0_BnAP
++----------------------------------------------------------------------------*/
+/* Burst Mode Enable */
+#define EBC0_BNAP_BME_ENABLED	    0x80000000
+#define EBC0_BNAP_BME_DISABLED	    0x00000000
+/* Transfert Wait */
+#define EBC0_BNAP_TWT_ENCODE(n)	    ((((unsigned long)(n))&0xFF)<<23)	/* Bits 1:8 */
+/* Chip Select On Timing */
+#define EBC0_BNAP_CSN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<18)	/* Bits 12:13 */
+/* Output Enable On Timing */
+#define EBC0_BNAP_OEN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<16)	/* Bits 14:15 */
+/* Write Back Enable On Timing */
+#define EBC0_BNAP_WBN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<14)	/* Bits 16:17 */
+/* Write Back Enable Off Timing */
+#define EBC0_BNAP_WBF_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<12)	/* Bits 18:19 */
+/* Transfert Hold */
+#define EBC0_BNAP_TH_ENCODE(n)	    ((((unsigned long)(n))&0x7)<<9)	/* Bits 20:22 */
+/* PerReady Enable */
+#define EBC0_BNAP_RE_ENABLED	    0x00000100
+#define EBC0_BNAP_RE_DISABLED	    0x00000000
+/* Sample On Ready */
+#define EBC0_BNAP_SOR_DELAYED	    0x00000000
+#define EBC0_BNAP_SOR_NOT_DELAYED   0x00000080
+/* Byte Enable Mode */
+#define EBC0_BNAP_BEM_WRITEONLY	    0x00000000
+#define EBC0_BNAP_BEM_RW	    0x00000040
+/* Parity Enable */
+#define EBC0_BNAP_PEN_DISABLED	    0x00000000
+#define EBC0_BNAP_PEN_ENABLED	    0x00000020
+
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+/* */
+#define BOOT_FROM_SMALL_FLASH		0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
+#define BOOT_FROM_NAND_FLASH0		0x02
+#define BOOT_FROM_PCI			0x03
+#define BOOT_DEVICE_UNKNOWN		0x04
+
+
+#define	 PVR_POWERPC_440EP_PASS1    0x42221850
+#define	 PVR_POWERPC_440EP_PASS2    0x422218D3
+
+#define TRUE 1
+#define FALSE 0
+
+#define GPIO0		0
+#define GPIO1		1
+
+/*#define MAX_SELECTION_NB	CORE_NB */
+#define MAX_CORE_SELECT_NB	22
+
+/*----------------------------------------------------------------------------+
+  | PPC440EP GPIOs addresses.
+  +----------------------------------------------------------------------------*/
+#define GPIO0_REAL	 0xEF600B00
+
+#define GPIO1_REAL	 0xEF600C00
+
+/* Offsets */
+#define GPIOx_OR    0x00	/* GPIO Output Register */
+#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
+#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
+#define GPIOx_IR    0x1C	/* GPIO Input Register */
+#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
+#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
+#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
+#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
+
+/* GPIO0 */
+#define GPIO0_IS1L	(GPIO0_BASE+GPIOx_IS1L)
+#define GPIO0_IS1H	(GPIO0_BASE+GPIOx_IS1H)
+#define GPIO0_IS2L	(GPIO0_BASE+GPIOx_IS2L)
+#define GPIO0_IS2H	(GPIO0_BASE+GPIOx_IS2H)
+#define GPIO0_IS3L	(GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS3H	(GPIO0_BASE+GPIOx_IS3L)
+
+/* GPIO1 */
+#define GPIO1_IS1L	(GPIO1_BASE+GPIOx_IS1L)
+#define GPIO1_IS1H	(GPIO1_BASE+GPIOx_IS1H)
+#define GPIO1_IS2L	(GPIO1_BASE+GPIOx_IS2L)
+#define GPIO1_IS2H	(GPIO1_BASE+GPIOx_IS2H)
+#define GPIO1_IS3L	(GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS3H	(GPIO1_BASE+GPIOx_IS3L)
+
+#define GPIO_OS(x)	(x+GPIOx_OSL)	 /* GPIO Output Register High or Low */
+#define GPIO_TS(x)	(x+GPIOx_TSL)	 /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)	(x+GPIOx_IS1L)	 /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)	(x+GPIOx_IS2L)	 /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)	(x+GPIOx_IS3L)	 /* GPIO Input register3 High or Low */
+
+
+/*----------------------------------------------------------------------------+
+  |			XX     XX
+  |
+  | XXXXXX   XXX XX    XXX    XXX
+  |    XX    XX X XX	XX     XX
+  |   XX     XX X XX	XX     XX
+  |  XX	     XX	  XX	XX     XX
+  | XXXXXX   XXX  XXX  XXXX   XXXX
+  +----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+  | Defines
+  +----------------------------------------------------------------------------*/
+typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
+			   ZMII_CONFIGURATION_IS_MII,
+			   ZMII_CONFIGURATION_IS_RMII,
+			   ZMII_CONFIGURATION_IS_SMII
+} zmii_config_t;
+
+/*----------------------------------------------------------------------------+
+  | Declare Configuration values
+  +----------------------------------------------------------------------------*/
+typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
+typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
+typedef enum config_list {  IIC_CORE,
+			    SCP_CORE,
+			    DMA_CHANNEL_AB,
+			    UIC_4_9,
+			    USB2_HOST,
+			    DMA_CHANNEL_CD,
+			    USB2_DEVICE,
+			    PACKET_REJ_FUNC_AVAIL,
+			    USB1_DEVICE,
+			    EBC_MASTER,
+			    NAND_FLASH,
+			    UART_CORE0,
+			    UART_CORE1,
+			    UART_CORE2,
+			    UART_CORE3,
+			    MII_SEL,
+			    RMII_SEL,
+			    SMII_SEL,
+			    PACKET_REJ_FUNC_EN,
+			    UIC_0_3,
+			    USB1_HOST,
+			    PCI_PATCH,
+			    CORE_NB
+} core_list_t;
+
+typedef enum block3_value { B3_V1,  B3_V2,  B3_V3,  B3_V4,  B3_V5,
+			    B3_V6,  B3_V7,  B3_V8,  B3_V9,  B3_V10,
+			    B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
+			    B3_V16, B3_VALUE_UNKNOWN
+} block3_value_t;
+
+typedef enum config_validity { CONFIG_IS_VALID,
+			       CONFIG_IS_INVALID
+} config_validity_t;
diff --git a/u-boot/board/amcc/bamboo/config.mk b/u-boot/board/amcc/bamboo/config.mk
new file mode 100644
index 0000000..7ca16a0
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
diff --git a/u-boot/board/amcc/bamboo/flash.c b/u-boot/board/amcc/bamboo/flash.c
new file mode 100644
index 0000000..07d185f
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/flash.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include "bamboo.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
+	{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash  */
+	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
+	{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
+	{0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+	unsigned long val;
+	unsigned long ebc_boot_size;
+	unsigned long boot_selection;
+
+	mfsdr(SDR0_PINSTP, val);
+	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
+
+	if ((index == 5) || (index == 7)) {
+		/*
+		 * Boot Settings in IIC EEprom address 0xA8 or 0xA4
+		 * Read Serial Device Strap Register1 in PPC440EP
+		 */
+		mfsdr(SDR0_SDSTP1, val);
+		boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+		ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+		switch(boot_selection) {
+		case SDR0_SDSTP1_BOOT_SEL_EBC:
+			switch(ebc_boot_size) {
+			case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+				index = 3;
+				break;
+			case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+				index = 0;
+				break;
+			}
+			break;
+
+		case SDR0_SDSTP1_BOOT_SEL_PCI:
+			index = 1;
+			break;
+
+		case SDR0_SDSTP1_BOOT_SEL_NDFC:
+			index = 2;
+			break;
+		}
+	} else if (index == 0) {
+		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
+			index = 8; /* sram below op code flash -> new index 8 */
+		}
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0)
+			continue;
+
+		DEBUGF("Detection bank %d...\n", i);
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/u-boot/board/amcc/bamboo/init.S b/u-boot/board/amcc/bamboo/init.S
new file mode 100644
index 0000000..3d9989d
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/init.S
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+#ifndef CONFIG_NAND_SPL
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
+#else
+	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
+#endif
+
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+
+	/* PCI base & peripherals */
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
+	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
+
+	/* PCI */
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
+
+	/* USB 2.0 Device */
+	tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
+#define TLB02	TLB2(AC_RWX | SA_IG)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/u-boot/board/amcc/bamboo/u-boot-nand.lds b/u-boot/board/amcc/bamboo/u-boot-nand.lds
new file mode 100644
index 0000000..c34bb62
--- /dev/null
+++ b/u-boot/board/amcc/bamboo/u-boot-nand.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
+    board/amcc/bamboo/init.o		(.text*)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/env_embedded.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/amcc/bluestone/Makefile b/u-boot/board/amcc/bluestone/Makefile
new file mode 100644
index 0000000..642eda0
--- /dev/null
+++ b/u-boot/board/amcc/bluestone/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri <tmarri@apm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+SOBJS	:= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/bluestone/bluestone.c b/u-boot/board/amcc/bluestone/bluestone.c
new file mode 100644
index 0000000..fe8929c
--- /dev/null
+++ b/u-boot/board/amcc/bluestone/bluestone.c
@@ -0,0 +1,111 @@
+/*
+ * Bluestone board support
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/apm821xx.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx-gpio.h>
+
+int board_early_init_f(void)
+{
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * UART0: 2 pins
+	 */
+	mtsdr(SDR0_PFC1, 0x0000000);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Bluestone Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
diff --git a/u-boot/board/amcc/bluestone/config.mk b/u-boot/board/amcc/bluestone/config.mk
new file mode 100644
index 0000000..d5d66eb
--- /dev/null
+++ b/u-boot/board/amcc/bluestone/config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri <tmarri@apm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Applied Micro APM821XX Evaluation board.
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/bluestone/init.S b/u-boot/board/amcc/bluestone/init.S
new file mode 100644
index 0000000..4b90c8d
--- /dev/null
+++ b/u-boot/board/amcc/bluestone/init.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/* TLB 0 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+	4, AC_RWX | SA_G)
+
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+			0, AC_RWX | SA_G)
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
+			AC_RWX | SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
+			CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/bubinga/Makefile b/u-boot/board/amcc/bubinga/Makefile
new file mode 100644
index 0000000..9f63df1
--- /dev/null
+++ b/u-boot/board/amcc/bubinga/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/bubinga/bubinga.c b/u-boot/board/amcc/bubinga/bubinga.c
new file mode 100644
index 0000000..49eadb9
--- /dev/null
+++ b/u-boot/board/amcc/bubinga/bubinga.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+long int spd_sdram(void);
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000010);
+	mtdcr(UIC0PR, 0xFFFF7FF0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000010);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 * and enable the internal PCI arbiter if selected
+	 */
+	if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
+		mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+	else
+		mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/* -------------------------------------------------------------------------
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+   ------------------------------------------------------------------------- */
+phys_size_t initdram(int board_type)
+{
+	long int ret;
+
+	ret = spd_sdram();
+	return ret;
+}
diff --git a/u-boot/board/amcc/bubinga/flash.c b/u-boot/board/amcc/bubinga/flash.c
new file mode 100644
index 0000000..4850fe1
--- /dev/null
+++ b/u-boot/board/amcc/bubinga/flash.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[0]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+#endif
+
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	}
+
+	/* 2 banks */
+	else {
+		size_b1 =
+		    flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+				   &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr(EBC0_CFGADDR, PB0CR);
+			pbcr = mfdcr(EBC0_CFGDATA);
+			mtdcr(EBC0_CFGADDR, PB0CR);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 |
+			    (((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr(EBC0_CFGDATA, pbcr);
+			/*          printf("PB1CR = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr(EBC0_CFGADDR, PB1CR);
+			pbcr = mfdcr(EBC0_CFGDATA);
+			mtdcr(EBC0_CFGADDR, PB1CR);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 |
+			    (((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr(EBC0_CFGDATA, pbcr);
+			/*            printf("PB0CR = %x\n", pbcr); */
+		}
+
+		size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+		flash_get_offsets(base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
+				    base_b0 + size_b0 - 1, &flash_info[0]);
+		/* Also protect sector containing initial power-up instruction */
+		/* (flash_protect() checks address range - other call ignored) */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+			    flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+			flash_get_offsets(base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void)flash_protect(FLAG_PROTECT_SET,
+					    base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN,
+					    base_b1 + size_b1 - 1,
+					    &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+					    base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
+					    base_b0 + size_b0 - 1,
+					    &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
diff --git a/u-boot/board/amcc/canyonlands/Makefile b/u-boot/board/amcc/canyonlands/Makefile
new file mode 100644
index 0000000..4d87ea9
--- /dev/null
+++ b/u-boot/board/amcc/canyonlands/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	:= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/canyonlands/canyonlands.c b/u-boot/board/amcc/canyonlands/canyonlands.c
new file mode 100644
index 0000000..80e2739
--- /dev/null
+++ b/u-boot/board/amcc/canyonlands/canyonlands.c
@@ -0,0 +1,534 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/errno.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_bcsr {
+	u8	board_id;
+	u8	cpld_rev;
+	u8	led_user;
+	u8	board_status;
+	u8	reset_ctrl;
+	u8	flash_ctrl;
+	u8	eth_ctrl;
+	u8	usb_ctrl;
+	u8	irq_ctrl;
+};
+
+#define BOARD_CANYONLANDS_PCIE	1
+#define BOARD_CANYONLANDS_SATA	2
+#define BOARD_GLACIER		3
+#define BOARD_ARCHES		4
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+#if defined(CONFIG_ARCHES)
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
+}
+#else
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+#endif
+
+#if defined(CONFIG_ARCHES)
+/*
+ * FPGA read/write helper macros
+ */
+static inline int board_fpga_read(int offset)
+{
+	int data;
+
+	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
+
+	return data;
+}
+
+static inline void board_fpga_write(int offset, int data)
+{
+	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
+}
+
+/*
+ * CPLD read/write helper macros
+ */
+static inline int board_cpld_read(int offset)
+{
+	int data;
+
+	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
+
+	return data;
+}
+
+static inline void board_cpld_write(int offset, int data)
+{
+	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
+}
+#else
+static int pvr_460ex(void)
+{
+	u32 pvr = get_pvr();
+
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
+	    (pvr == PVR_460EX_RB))
+		return 1;
+
+	return 0;
+}
+#endif	/* defined(CONFIG_ARCHES) */
+
+int board_early_init_f(void)
+{
+#if !defined(CONFIG_ARCHES)
+	u32 sdr0_cust0;
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+
+#endif
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+#if !defined(CONFIG_ARCHES)
+	/* SDR Setting - enable NDFC */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+#endif
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * UART0: 4 pins
+	 */
+	mtsdr(SDR0_PFC1, 0x00040000);
+
+	/* Enable PCI host functionality in SDR0_PCI0 */
+	mtsdr(SDR0_PCI0, 0xe0000000);
+
+#if !defined(CONFIG_ARCHES)
+	/* Enable ethernet and take out of reset */
+	out_8(&bcsr_data->eth_ctrl, 0) ;
+
+	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
+	out_8(&bcsr_data->flash_ctrl, 0) ;
+	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+	u8 val;
+
+	/* Enable USB host & USB-OTG */
+	val = in_8(&bcsr_data->usb_ctrl);
+	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+	out_8(&bcsr_data->usb_ctrl, val);
+
+	/*
+	 * Configure USB-STP pins as alternate and not GPIO
+	 * It seems to be neccessary to configure the STP pins as GPIO
+	 * input at powerup (perhaps while USB reset is asserted). So
+	 * we configure those pins to their "real" function now.
+	 */
+	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+	u8 val;
+
+	/* Disable USB host & USB-OTG */
+	val = in_8(&bcsr_data->usb_ctrl);
+	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+	out_8(&bcsr_data->usb_ctrl, val);
+
+	/* Reconfigure USB-STP pins as input */
+	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+
+	return 0;
+}
+
+int usb_board_init_fail(void)
+{
+	return usb_board_stop();
+}
+#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
+
+#if !defined(CONFIG_ARCHES)
+static void canyonlands_sata_init(int board_type)
+{
+	u32 reg;
+
+	if (board_type == BOARD_CANYONLANDS_SATA) {
+		/* Put SATA in reset */
+		SDR_WRITE(SDR0_SRST1, 0x00020001);
+
+		/* Set the phy for SATA, not PCI-E port 0 */
+		reg = SDR_READ(PESDR0_PHY_CTL_RST);
+		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
+		reg = SDR_READ(PESDR0_L0CLK);
+		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
+		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
+		SDR_WRITE(PESDR0_L0DRV, 0x00000104);
+
+		/* Bring SATA out of reset */
+		SDR_WRITE(SDR0_SRST1, 0x00000000);
+	}
+}
+#endif	/* !defined(CONFIG_ARCHES) */
+
+int get_cpu_num(void)
+{
+	int cpu = NA_OR_UNKNOWN_CPU;
+
+#if defined(CONFIG_ARCHES)
+	int cpu_num;
+
+	cpu_num = board_fpga_read(0x3);
+
+	/* sanity check; assume cpu numbering starts and increments from 0 */
+	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
+		cpu = cpu_num;
+#endif
+
+	return cpu;
+}
+
+#if !defined(CONFIG_ARCHES)
+int checkboard(void)
+{
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+	char *s = getenv("serial#");
+
+	if (pvr_460ex()) {
+		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
+		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
+			gd->board_type = BOARD_CANYONLANDS_PCIE;
+		else
+			gd->board_type = BOARD_CANYONLANDS_SATA;
+	} else {
+		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
+		gd->board_type = BOARD_GLACIER;
+	}
+
+	switch (gd->board_type) {
+	case BOARD_CANYONLANDS_PCIE:
+	case BOARD_GLACIER:
+		puts(", 2*PCIe");
+		break;
+
+	case BOARD_CANYONLANDS_SATA:
+		puts(", 1*PCIe/1*SATA");
+		break;
+	}
+
+	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	canyonlands_sata_init(gd->board_type);
+
+	return (0);
+}
+
+#else	/* defined(CONFIG_ARCHES) */
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
+	printf("       Revision %02x.%02x ",
+				board_fpga_read(0x0), board_fpga_read(0x1));
+
+	gd->board_type = BOARD_ARCHES;
+
+	/* Only CPU0 has access to CPLD registers */
+	if (get_cpu_num() == 0) {
+		u8 cfg_sw = board_cpld_read(0x1);
+		printf("(FPGA=%02x, CPLD=%02x)\n",
+				board_fpga_read(0x2), board_cpld_read(0x0));
+		printf("       Configuration Switch %d%d%d%d\n",
+				((cfg_sw >> 3) & 0x01),
+				((cfg_sw >> 2) & 0x01),
+				((cfg_sw >> 1) & 0x01),
+				((cfg_sw >> 0) & 0x01));
+	} else
+		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
+
+
+	if (s != NULL)
+		printf("       Serial# %s\n", s);
+
+	return 0;
+}
+#endif	/* !defined(CONFIG_ARCHES) */
+
+#if defined(CONFIG_PCI)
+int board_pcie_first(void)
+{
+	/*
+	 * Canyonlands with SATA enabled has only one PCIe slot
+	 * (2nd one).
+	 */
+	if (gd->board_type == BOARD_CANYONLANDS_SATA)
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_PCI */
+
+int board_early_init_r (void)
+{
+	/*
+	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+	 * boot EBC mapping only supports a maximum of 16MBytes
+	 * (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfc00.0000 -> 4.cc00.0000
+	 */
+
+	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+#else
+	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+#endif
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
+		    TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+#if !defined(CONFIG_ARCHES)
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+	u32 eth_cfg;
+	u8 val;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	/* disable SGMII mode */
+	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+		     SDR0_ETH_CFG_SGMII1_ENABLE |
+		     SDR0_ETH_CFG_SGMII0_ENABLE);
+	/* Set the for 2 RGMII mode */
+	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+	if (pvr_460ex())
+		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	else
+		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	/*
+	 * RTC/M41T62:
+	 * Disable square wave output: Batterie will be drained
+	 * quickly, when this output is not disabled
+	 */
+	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
+	val &= ~0x40;
+	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
+
+	return 0;
+}
+
+#else	/* defined(CONFIG_ARCHES) */
+
+int misc_init_r(void)
+{
+	u32 eth_cfg = 0;
+	u32 eth_pll;
+	u32 reg;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+
+	/* enable SGMII mode */
+	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
+			SDR0_ETH_CFG_SGMII1_ENABLE |
+			SDR0_ETH_CFG_SGMII2_ENABLE);
+
+	/* Set EMAC for MDIO */
+	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
+
+	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
+	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/* reset all SGMII interfaces */
+	mfsdr(SDR0_SRST1,   reg);
+	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
+	mtsdr(SDR0_SRST1, reg);
+	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
+	mtsdr(SDR0_SRST1,   0x00000000);
+
+	do {
+		mfsdr(SDR0_ETH_PLL, eth_pll);
+	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
+
+	return 0;
+}
+#endif	/* !defined(CONFIG_ARCHES) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	__ft_board_setup(blob, bd);
+
+	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
+		/*
+		 * When SATA is selected we need to disable the first PCIe
+		 * node in the device tree, so that Linux doesn't initialize
+		 * it.
+		 */
+		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+				     "disabled", sizeof("disabled"), 1);
+	}
+
+	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
+		/*
+		 * When PCIe is selected we need to disable the SATA
+		 * node in the device tree, so that Linux doesn't initialize
+		 * it.
+		 */
+		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+				     "disabled", sizeof("disabled"), 1);
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/amcc/canyonlands/chip_config.c b/u-boot/board/amcc/canyonlands/chip_config.c
new file mode 100644
index 0000000..5ad78b8
--- /dev/null
+++ b/u-boot/board/amcc/canyonlands/chip_config.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+#if !defined(CONFIG_ARCHES)
+	{
+		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+#endif
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/amcc/canyonlands/config.mk b/u-boot/board/amcc/canyonlands/config.mk
new file mode 100644
index 0000000..abf2a26
--- /dev/null
+++ b/u-boot/board/amcc/canyonlands/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2008-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
diff --git a/u-boot/board/amcc/canyonlands/init.S b/u-boot/board/amcc/canyonlands/init.S
new file mode 100644
index 0000000..8b7bfce
--- /dev/null
+++ b/u-boot/board/amcc/canyonlands/init.S
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I
+	 */
+#ifndef CONFIG_NAND_SPL
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
+#else
+	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
+	tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
+#endif
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+
+	/* PCIe UTL register */
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
+
+#if !defined(CONFIG_ARCHES)
+	/* TLB-entry for NAND */
+	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
+
+	/* TLB-entry for CPLD */
+	tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
+#else
+	/* TLB-entry for FPGA */
+	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
+#endif
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
+
+	/* AHB: Internal USB Peripherals (USB, SATA) */
+	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
+
+#if defined(CONFIG_RAPIDIO)
+	/* TLB-entries for RapidIO (SRIO) */
+	tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
+					0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
+					0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
+					0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K,  0x00100000,
+					0x4, AC_RW | SA_IG)
+#endif
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
+#define TLB02	TLB2(AC_RWX | SA_IG)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/u-boot/board/amcc/canyonlands/u-boot-nand.lds b/u-boot/board/amcc/canyonlands/u-boot-nand.lds
new file mode 100644
index 0000000..534d6dd
--- /dev/null
+++ b/u-boot/board/amcc/canyonlands/u-boot-nand.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/amcc/canyonlands/init.o	(.text*)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x20000);
+    common/env_embedded.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x80000);
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/amcc/common/flash.c b/u-boot/board/amcc/common/flash.c
new file mode 100644
index 0000000..8f23375
--- /dev/null
+++ b/u-boot/board/amcc/common/flash.c
@@ -0,0 +1,956 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_MX:
+		printf ("MACRONIX ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMD016:
+		printf("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM033C:
+		printf("AM29LV033C (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_STMW320DT:
+		printf ("M29W320DT (32 M, top sector)\n");
+		break;
+	case FLASH_MXLV320T:
+		printf ("MXLV320T (32 Mbit, top sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1) {
+		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+	} else {
+		return flash_get_size_1(addr, info);
+	}
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;		/* => 512 KiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;		/* => 512 KiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;		/* => 512 KiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;	/* => 2 MiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;	/* => 4 MiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 512 KiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 512 KiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MiB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MiB */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	int n;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID */
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MiB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MiB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = 0x00400000;  break;	/* => 4 MiB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
+		info->flash_id += FLASH_MXLV320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;	/* => 4 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n=0; n<2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+		info->start[i--] = base + info->size - 0x00010000;
+
+		for (; i >= 0; i--)
+			info->start[i] = base + i * 0x00010000;
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000a000;
+			info->start[6] = base + 0x0000c000;
+			info->start[7] = base + 0x0000e000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + ((i-7) * 0x00010000);
+			}
+		} else {
+			/* set sector offsets for top boot block type */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000a000;
+			info->start[i--] = base + info->size - 0x0000c000;
+			info->start[i--] = base + info->size - 0x0000e000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
diff --git a/u-boot/board/amcc/ebony/Makefile b/u-boot/board/amcc/ebony/Makefile
new file mode 100644
index 0000000..b5d0fe5
--- /dev/null
+++ b/u-boot/board/amcc/ebony/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/ebony/config.mk b/u-boot/board/amcc/ebony/config.mk
new file mode 100644
index 0000000..9eac8b9
--- /dev/null
+++ b/u-boot/board/amcc/ebony/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/ebony/ebony.c b/u-boot/board/amcc/ebony/ebony.c
new file mode 100644
index 0000000..923dbca
--- /dev/null
+++ b/u-boot/board/amcc/ebony/ebony.c
@@ -0,0 +1,166 @@
+/*
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+long int fixed_sdram(void);
+
+int board_early_init_f(void)
+{
+	uint reg;
+	unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
+	unsigned char status;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	reg = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
+
+	mtebc(PB1AP, 0x02815480);	/* NVRAM/RTC */
+	mtebc(PB1CR, 0x48018000);	/* BA=0x480 1MB R/W 8-bit */
+	mtebc(PB7AP, 0x01015280);	/* FPGA registers */
+	mtebc(PB7CR, 0x48318000);	/* BA=0x483 1MB R/W 8-bit */
+
+	/* read FPGA_REG0  and set the bus controller */
+	status = *fpga_base;
+	if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
+		mtebc(PB0AP, 0x9b015480);	/* FLASH/SRAM */
+		mtebc(PB0CR, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+		mtebc(PB2AP, 0x9b015480);	/* 4MB FLASH */
+		mtebc(PB2CR, 0xff858000);	/* BAS=0xff8 4MB R/W 8-bit */
+	} else {
+		mtebc(PB0AP, 0x9b015480);	/* 4MB FLASH */
+		mtebc(PB0CR, 0xffc58000);	/* BAS=0xffc 4MB R/W 8-bit */
+
+		/* set CS2 if FLASH_ONBD_N == 0 */
+		if (!(status & FLASH_ONBD_N)) {
+			mtebc(PB2AP, 0x9b015480);	/* FLASH/SRAM */
+			mtebc(PB2CR, 0xff818000);	/* BAS=0xff8 4MB R/W 8-bit */
+		}
+	}
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+phys_size_t initdram(int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram();
+#else
+	dram_size = fixed_sdram();
+#endif
+	return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    128 MB, non-ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram(void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram(SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(SDRAM0_WDDCTR, 0x00000000);	/* wrcp=0 dcd=0                 */
+	mtsdram(SDRAM0_CLKTR, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(SDRAM0_TR0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3                       */
+	mtsdram(SDRAM0_TR1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram(SDRAM0_RTR, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	udelay(400);		/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram(SDRAM0_CFG0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
+	for (;;) {
+		mfsdram(SDRAM0_MCSTS, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB                           */
+}
+#endif				/* !defined(CONFIG_SPD_EEPROM) */
diff --git a/u-boot/board/amcc/ebony/flash.c b/u-boot/board/amcc/ebony/flash.c
new file mode 100644
index 0000000..df7716c
--- /dev/null
+++ b/u-boot/board/amcc/ebony/flash.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+
+#define     BOOT_SMALL_FLASH_VAL    4
+#define     FLASH_ONBD_N_VAL        2
+#define     FLASH_SRAM_SEL_VAL      1
+
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{0xffc00000, 0xffe00000, 0xff880000},	/* 0:000: configuraton 3 */
+	{0xffc00000, 0xffe00000, 0xff800000},	/* 1:001: configuraton 4 */
+	{0xffc00000, 0xffe00000, 0x00000000},	/* 2:010: configuraton 7 */
+	{0xffc00000, 0xffe00000, 0x00000000},	/* 3:011: configuraton 8 */
+	{0xff800000, 0xffa00000, 0xfff80000},	/* 4:100: configuraton 1 */
+	{0xff800000, 0xffa00000, 0xfff00000},	/* 5:101: configuraton 2 */
+	{0xffc00000, 0xffe00000, 0x00000000},	/* 6:110: configuraton 5 */
+	{0xffc00000, 0xffe00000, 0x00000000}	/* 7:111: configuraton 6 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+	u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
+
+	if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
+		/*
+		 * cs0: small flash (512KiB)
+		 * cs2: 2 * big flash (2 * 2MiB)
+		 */
+		if (cs == 0)
+			return flash_info[2].size;
+		if (cs == 2)
+			return flash_info[0].size + flash_info[1].size;
+	} else {
+		/*
+		 * cs0: 2 * big flash (2 * 2MiB)
+		 * cs2: small flash (512KiB)
+		 */
+		if (cs == 0)
+			return flash_info[0].size + flash_info[1].size;
+		if (cs == 2)
+			return flash_info[2].size;
+	}
+
+	return 0;
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	/* check the bitmap of switch status */
+	if (switch_status & BOOT_SMALL_FLASH) {
+		index += BOOT_SMALL_FLASH_VAL;
+	}
+	if (switch_status & FLASH_ONBD_N) {
+		index += FLASH_ONBD_N_VAL;
+	}
+	if (switch_status & FLASH_SRAM_SEL) {
+		index += FLASH_SRAM_SEL_VAL;
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *)
+					   flash_addr_table[index][i],
+					   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[2]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/u-boot/board/amcc/ebony/init.S b/u-boot/board/amcc/ebony/init.S
new file mode 100644
index 0000000..08a0d11
--- /dev/null
+++ b/u-boot/board/amcc/ebony/init.S
@@ -0,0 +1,58 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/katmai/Makefile b/u-boot/board/amcc/katmai/Makefile
new file mode 100644
index 0000000..466b190
--- /dev/null
+++ b/u-boot/board/amcc/katmai/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/katmai/chip_config.c b/u-boot/board/amcc/katmai/chip_config.c
new file mode 100644
index 0000000..efaf378
--- /dev/null
+++ b/u-boot/board/amcc/katmai/chip_config.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"400-133","CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"500-166","CPU: 500 PLB: 166 OPB:  83 EBC:  83",
+		{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"533-133","CPU: 533 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"667-133","CPU: 667 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"667-166","CPU: 667 PLB: 166 OPB:  83 EBC:  83",
+		{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"800-160","CPU: 800 PLB: 160 OPB:  53 EBC:  17",
+		{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/amcc/katmai/config.mk b/u-boot/board/amcc/katmai/config.mk
new file mode 100644
index 0000000..f5dfbaf
--- /dev/null
+++ b/u-boot/board/amcc/katmai/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440SPe Evaluation (Katmai) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/katmai/init.S b/u-boot/board/amcc/katmai/init.S
new file mode 100644
index 0000000..4a42f1f
--- /dev/null
+++ b/u-boot/board/amcc/katmai/init.S
@@ -0,0 +1,119 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+	.globl tlbtabA
+tlbtabA:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
+	tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+	.globl tlbtabB
+tlbtabB:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/katmai/katmai.c b/u-boot/board/amcc/katmai/katmai.c
new file mode 100644
index 0000000..7301cd5
--- /dev/null
+++ b/u-boot/board/amcc/katmai/katmai.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2007-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+	unsigned long mfr;
+
+	/*----------------------------------------------------------------------+
+	 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
+	 *-----------------------------------------------------------------------+
+	 *-----------------------------------------------------------------------+
+	 * Interrupt | Source                            | Pol.  | Sensi.| Crit. |
+	 *-----------+-----------------------------------+-------+-------+-------+
+	 * IRQ 00    | UART0                             | High  | Level | Non   |
+	 * IRQ 01    | UART1                             | High  | Level | Non   |
+	 * IRQ 02    | IIC0                              | High  | Level | Non   |
+	 * IRQ 03    | IIC1                              | High  | Level | Non   |
+	 * IRQ 04    | PCI0X0 MSG IN                     | High  | Level | Non   |
+	 * IRQ 05    | PCI0X0 CMD Write                  | High  | Level | Non   |
+	 * IRQ 06    | PCI0X0 Power Mgt                  | High  | Level | Non   |
+	 * IRQ 07    | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
+	 * IRQ 08    | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
+	 * IRQ 09    | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
+	 * IRQ 10    | UIC2 Non-critical Int.            | NA    | NA    | Non   |
+	 * IRQ 11    | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
+	 * IRQ 12    | PCI Express MSI Level 0           | Rising| Edge  | Non   |
+	 * IRQ 13    | PCI Express MSI Level 1           | Rising| Edge  | Non   |
+	 * IRQ 14    | PCI Express MSI Level 2           | Rising| Edge  | Non   |
+	 * IRQ 15    | PCI Express MSI Level 3           | Rising| Edge  | Non   |
+	 * IRQ 16    | UIC3 Non-critical Int.            | NA    | NA    | Non   |
+	 * IRQ 17    | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
+	 * IRQ 18    | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
+	 * IRQ 19    | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	 * IRQ 20    | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	 * IRQ 21    | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	 * IRQ 22    | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	 * IRQ 23    | I2O Inbound Doorbell              | High  | Level | Non   |
+	 * IRQ 24    | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
+	 * IRQ 25    | I2O Region 0 LL PLB Write         | High  | Level | Non   |
+	 * IRQ 26    | I2O Region 1 LL PLB Write         | High  | Level | Non   |
+	 * IRQ 27    | I2O Region 0 HB PLB Write         | High  | Level | Non   |
+	 * IRQ 28    | I2O Region 1 HB PLB Write         | High  | Level | Non   |
+	 * IRQ 29    | GPT Down Count Timer              | Rising| Edge  | Non   |
+	 * IRQ 30    | UIC1 Non-critical Int.            | NA    | NA    | Non   |
+	 * IRQ 31    | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
+	 *------------------------------------------------------------------------
+	 * IRQ 32    | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 33    | MAL Serr                          | High  | Level | Non   |
+	 * IRQ 34    | MAL Txde                          | High  | Level | Non   |
+	 * IRQ 35    | MAL Rxde                          | High  | Level | Non   |
+	 * IRQ 36    | DMC CE or DMC UE                  | High  | Level | Non   |
+	 * IRQ 37    | EBC or UART2                      | High  |Lvl Edg| Non   |
+	 * IRQ 38    | MAL TX EOB                        | High  | Level | Non   |
+	 * IRQ 39    | MAL RX EOB                        | High  | Level | Non   |
+	 * IRQ 40    | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
+	 * IRQ 41    | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
+	 * IRQ 42    | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
+	 * IRQ 43    | L2 Cache                          | Risin | Edge  | Non   |
+	 * IRQ 44    | GPT Compare Timer 0               | Risin | Edge  | Non   |
+	 * IRQ 45    | GPT Compare Timer 1               | Risin | Edge  | Non   |
+	 * IRQ 46    | GPT Compare Timer 2               | Risin | Edge  | Non   |
+	 * IRQ 47    | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	 * IRQ 48    | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	 * IRQ 49    | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
+	 * IRQ 50    | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 51    | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 52    | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 53    | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 54    | DMA Error                         | High  | Level | Non   |
+	 * IRQ 55    | DMA I2O Error                     | High  | Level | Non   |
+	 * IRQ 56    | Serial ROM                        | High  | Level | Non   |
+	 * IRQ 57    | PCIX0 Error                       | High  | Edge  | Non   |
+	 * IRQ 58    | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 59    | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 60    | EMAC0 Interrupt                   | High  | Level | Non   |
+	 * IRQ 61    | EMAC0 Wake-up                     | High  | Level | Non   |
+	 * IRQ 62    | Reserved                          | High  | Level | Non   |
+	 * IRQ 63    | XOR                               | High  | Level | Non   |
+	 *-----------------------------------------------------------------------
+	 * IRQ 64    | PE0 AL                            | High  | Level | Non   |
+	 * IRQ 65    | PE0 VPD Access                    | Risin | Edge  | Non   |
+	 * IRQ 66    | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	 * IRQ 67    | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	 * IRQ 68    | PE0 TCR                           | High  | Level | Non   |
+	 * IRQ 69    | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	 * IRQ 70    | PE0 DCR Error                     | High  | Level | Non   |
+	 * IRQ 71    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 72    | PE1 AL                            | High  | Level | Non   |
+	 * IRQ 73    | PE1 VPD Access                    | Risin | Edge  | Non   |
+	 * IRQ 74    | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	 * IRQ 75    | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	 * IRQ 76    | PE1 TCR                           | High  | Level | Non   |
+	 * IRQ 77    | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	 * IRQ 78    | PE1 DCR Error                     | High  | Level | Non   |
+	 * IRQ 79    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 80    | PE2 AL                            | High  | Level | Non   |
+	 * IRQ 81    | PE2 VPD Access                    | Risin | Edge  | Non   |
+	 * IRQ 82    | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	 * IRQ 83    | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	 * IRQ 84    | PE2 TCR                           | High  | Level | Non   |
+	 * IRQ 85    | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	 * IRQ 86    | PE2 DCR Error                     | High  | Level | Non   |
+	 * IRQ 87    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 88    | External IRQ(5)                   | Progr | Progr | Non   |
+	 * IRQ 89    | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	 * IRQ 90    | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 91    | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 92    | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 93    | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 94    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 95    | Reserved                          | N/A   | N/A   | Non   |
+	 *-----------------------------------------------------------------------
+	 * IRQ 96    | PE0 INTA                          | High  | Level | Non   |
+	 * IRQ 97    | PE0 INTB                          | High  | Level | Non   |
+	 * IRQ 98    | PE0 INTC                          | High  | Level | Non   |
+	 * IRQ 99    | PE0 INTD                          | High  | Level | Non   |
+	 * IRQ 100   | PE1 INTA                          | High  | Level | Non   |
+	 * IRQ 101   | PE1 INTB                          | High  | Level | Non   |
+	 * IRQ 102   | PE1 INTC                          | High  | Level | Non   |
+	 * IRQ 103   | PE1 INTD                          | High  | Level | Non   |
+	 * IRQ 104   | PE2 INTA                          | High  | Level | Non   |
+	 * IRQ 105   | PE2 INTB                          | High  | Level | Non   |
+	 * IRQ 106   | PE2 INTC                          | High  | Level | Non   |
+	 * IRQ 107   | PE2 INTD                          | Risin | Edge  | Non   |
+	 * IRQ 108   | PCI Express MSI Level 4           | Risin | Edge  | Non   |
+	 * IRQ 109   | PCI Express MSI Level 5           | Risin | Edge  | Non   |
+	 * IRQ 110   | PCI Express MSI Level 6           | Risin | Edge  | Non   |
+	 * IRQ 111   | PCI Express MSI Level 7           | Risin | Edge  | Non   |
+	 * IRQ 116   | PCI Express MSI Level 12          | Risin | Edge  | Non   |
+	 * IRQ 112   | PCI Express MSI Level 8           | Risin | Edge  | Non   |
+	 * IRQ 113   | PCI Express MSI Level 9           | Risin | Edge  | Non   |
+	 * IRQ 114   | PCI Express MSI Level 10          | Risin | Edge  | Non   |
+	 * IRQ 115   | PCI Express MSI Level 11          | Risin | Edge  | Non   |
+	 * IRQ 117   | PCI Express MSI Level 13          | Risin | Edge  | Non   |
+	 * IRQ 118   | PCI Express MSI Level 14          | Risin | Edge  | Non   |
+	 * IRQ 119   | PCI Express MSI Level 15          | Risin | Edge  | Non   |
+	 * IRQ 120   | PCI Express MSI Level 16          | Risin | Edge  | Non   |
+	 * IRQ 121   | PCI Express MSI Level 17          | Risin | Edge  | Non   |
+	 * IRQ 122   | PCI Express MSI Level 18          | Risin | Edge  | Non   |
+	 * IRQ 123   | PCI Express MSI Level 19          | Risin | Edge  | Non   |
+	 * IRQ 124   | PCI Express MSI Level 20          | Risin | Edge  | Non   |
+	 * IRQ 125   | PCI Express MSI Level 21          | Risin | Edge  | Non   |
+	 * IRQ 126   | PCI Express MSI Level 22          | Risin | Edge  | Non   |
+	 * IRQ 127   | PCI Express MSI Level 23          | Risin | Edge  | Non   |
+	 *-----------+-----------------------------------+-------+-------+-------+ */
+	/*-------------------------------------------------------------------------+
+	 * Put UICs in PowerPC440SPemode.
+	 * Initialise UIC registers.  Clear all interrupts.  Disable all interrupts.
+	 * Set critical interrupt values.  Set interrupt polarities.  Set interrupt
+	 * trigger levels.  Make bit 0 High  priority.  Clear all interrupts again.
+	 *------------------------------------------------------------------------*/
+	mtdcr (UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC3CR, 0x00000000);	/* Set Critical / Non Critical interrupts: */
+	mtdcr (UIC3PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr (UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC3SR, 0x00000000);	/* clear all  interrupts*/
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all  interrupts*/
+
+
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (UIC2PR, 0xebebebff);	/* Set Interrupt Polarities*/
+	mtdcr (UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts*/
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels*/
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts*/
+
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all interrupts excepted cascade    to be checked */
+	mtdcr (UIC0CR, 0x00104001);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (UIC0PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr (UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts*/
+
+	mfsdr(SDR0_MFR, mfr);
+	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
+	mtsdr(SDR0_MFR, mfr);
+
+	mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
+
+	out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
+	out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Katmai - AMCC 440SPe Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+
+#if defined(CONFIG_PCI)
+int board_pcie_card_present(int port)
+{
+	u32 val;
+
+	val = in32(GPIO0_IR);
+	switch (port) {
+	case 0:
+		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
+	case 1:
+		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
+	case 2:
+		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
+	default:
+		return 0;
+	}
+}
+#endif	/* defined(CONFIG_PCI) */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/amcc/kilauea/Makefile b/u-boot/board/amcc/kilauea/Makefile
new file mode 100644
index 0000000..726c3ce
--- /dev/null
+++ b/u-boot/board/amcc/kilauea/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/kilauea/chip_config.c b/u-boot/board/amcc/kilauea/chip_config.c
new file mode 100644
index 0000000..919ec7f
--- /dev/null
+++ b/u-boot/board/amcc/kilauea/chip_config.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"333-nor","NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  83",
+		{
+			0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-nor", "NOR  CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-nor", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
+		{
+			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-nand", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
+		{
+			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nand", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"666-nor", "NOR  CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+		{
+			0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/amcc/kilauea/config.mk b/u-boot/board/amcc/kilauea/config.mk
new file mode 100644
index 0000000..4ae3ea9
--- /dev/null
+++ b/u-boot/board/amcc/kilauea/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2007-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
diff --git a/u-boot/board/amcc/kilauea/kilauea.c b/u-boot/board/amcc/kilauea/kilauea.c
new file mode 100644
index 0000000..bd6550c
--- /dev/null
+++ b/u-boot/board/amcc/kilauea/kilauea.c
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static int board_cpld_version(void)
+{
+	u32 cpld;
+
+	cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+	if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+		/*
+		 * Magic not found -> "old" CPLD revision which needs
+		 * the "old" EBC configuration
+		 */
+		mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+		      EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+		      EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+		      EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+		      EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+		      EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+		      EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+		/*
+		 * Return 0 for "old" CPLD version
+		 */
+		return 0;
+	}
+
+	/*
+	 * Magic found -> "new" CPLD revision which needs no new
+	 * EBC configuration
+	 */
+	return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
+}
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+	u32 val;
+
+	/*--------------------------------------------------------------------+
+	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+	 +--------------------------------------------------------------------+
+	+---------------------------------------------------------------------+
+	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+	+---------+-----------------------------------+-------+-------+-------+
+	| IRQ 00  | UART0                             | High  | Level | Non   |
+	| IRQ 01  | UART1                             | High  | Level | Non   |
+	| IRQ 02  | IIC0                              | High  | Level | Non   |
+	| IRQ 03  | TBD                               | High  | Level | Non   |
+	| IRQ 04  | TBD                               | High  | Level | Non   |
+	| IRQ 05  | EBM                               | High  | Level | Non   |
+	| IRQ 06  | BGI                               | High  | Level | Non   |
+	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
+	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
+	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
+	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
+	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
+	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
+	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
+	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
+	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
+	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
+	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
+	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
+	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
+	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
+	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
+	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
+	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
+	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
+	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
+	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
+	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
+	|----------------------------------------------------------------------
+	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
+	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
+	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
+	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
+	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
+	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
+	| IRQ 38  | NDFC                              | High  | Level | Non   |
+	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
+	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
+	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
+	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
+	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
+	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
+	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
+	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
+	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
+	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
+	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
+	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
+	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
+	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
+	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
+	|----------------------------------------------------------------------
+	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
+	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
+	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
+	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
+	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
+	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
+	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
+	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
+	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
+	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
+	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
+	|---------------------------------------------------------------------
+	+---------+-----------------------------------+-------+-------+------*/
+	/*--------------------------------------------------------------------+
+	 | Initialise UIC registers.  Clear all interrupts.  Disable all
+	 | interrupts.
+	 | Set critical interrupt values.  Set interrupt polarities.  Set
+	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 | interrupts again.
+	 +-------------------------------------------------------------------*/
+
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
+					/* Except cascade UIC0 and UIC1 */
+	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
+	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
+
+	/*
+	 * Note: Some cores are still in reset when the chip starts, so
+	 * take them out of reset
+	 */
+	mtsdr(SDR0_SRST, 0);
+
+	/* Configure 405EX for NAND usage */
+	val = SDR0_CUST0_MUX_NDFC_SEL |
+		SDR0_CUST0_NDFC_ENABLE |
+		SDR0_CUST0_NDFC_BW_8_BIT |
+		SDR0_CUST0_NRB_BUSY |
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+	mtsdr(SDR0_CUST0, val);
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * -> Enable USB
+	 */
+	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+	mtsdr(SDR0_PFC1, val);
+
+	/*
+	 * The CPLD version detection has to be the first access to
+	 * the CPLD, so we need to make this access this early and
+	 * save the CPLD version for later.
+	 */
+	gd->board_type = board_cpld_version();
+
+	/*
+	 * Configure FPGA register with PCIe reset
+	 */
+	out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4);	/* assert PCIe reset */
+	mdelay(50);
+	out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7);	/* deassert PCIe reset */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      -CONFIG_SYS_MONITOR_LEN,
+		      0xffffffff,
+		      &flash_info[0]);
+#endif
+
+	return 0;
+}
+
+static int is_405exr(void)
+{
+	u32 pvr = get_pvr();
+
+	if (pvr & 0x00000004)
+		return 0;		/* bit 2 set -> 405EX */
+
+	return 1;			/* bit 2 cleared -> 405EXr */
+}
+
+int board_emac_count(void)
+{
+	/*
+	 * 405EXr only has one EMAC interface, 405EX has two
+	 */
+	if (is_405exr())
+		return 1;
+	else
+		return 2;
+}
+
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
+{
+	/*
+	 * 405EXr only has one EMAC interface, 405EX has two
+	 */
+	if (is_405exr())
+		return 1 - 1;
+	else
+		return 2 - 1;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	if (is_405exr())
+		printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
+	else
+		printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	printf(" (CPLD rev. %ld)\n", gd->board_type);
+
+	return (0);
+}
diff --git a/u-boot/board/amcc/kilauea/u-boot-nand.lds b/u-boot/board/amcc/kilauea/u-boot-nand.lds
new file mode 100644
index 0000000..c2a04c7
--- /dev/null
+++ b/u-boot/board/amcc/kilauea/u-boot-nand.lds
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/env_embedded.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/amcc/luan/Makefile b/u-boot/board/amcc/luan/Makefile
new file mode 100644
index 0000000..b5d0fe5
--- /dev/null
+++ b/u-boot/board/amcc/luan/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/luan/config.mk b/u-boot/board/amcc/luan/config.mk
new file mode 100644
index 0000000..9eac8b9
--- /dev/null
+++ b/u-boot/board/amcc/luan/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/luan/epld.h b/u-boot/board/amcc/luan/epld.h
new file mode 100644
index 0000000..569d78c
--- /dev/null
+++ b/u-boot/board/amcc/luan/epld.h
@@ -0,0 +1,85 @@
+#define EPLD0_FSEL_FB2		0x80
+#define EPLD0_BOOT_SMALL_FLASH	0x40	/* 0 boot from large flash, 1 from small flash */
+#define EPLD0_RAW_CARD_BIT0	0x20	/* raw card EC level */
+#define EPLD0_RAW_CARD_BIT1	0x10
+#define EPLD0_RAW_CARD_BIT2	0x08
+#define EPLD0_EXT_ARB_SEL_N	0x04	/* 0 select on-board ext PCI-X, 1 internal arbiter */
+#define EPLD0_FLASH_ONBRD_N	0x02	/* 0 small flash/SRAM active, 1 block access */
+#define EPLD0_FLASH_SRAM_SEL_N	0x01	/* 0 SRAM at mem top, 1 small flash at mem top */
+
+#define EPLD1_CLK_CNTL0		0x80	/* FSEL-FB1 of MPC9772 */
+#define EPLD1_PCIL0_CNTL1	0x40	/* S*0 of 9531 */
+#define EPLD1_PCIL0_CNTL2	0x20	/* S*1 of 9531 */
+#define EPLD1_CLK_CNTL3		0x10	/* FSEL-B1 of MPC9772 */
+#define EPLD1_CLK_CNTL4		0x08	/* FSEL-B0 of MPC9772 */
+#define EPLD1_MASTER_CLOCK6	0x04	/* clock source select 6 */
+#define EPLD1_MASTER_CLOCK7	0x02	/* clock source select 7 */
+#define EPLD1_MASTER_CLOCK8	0x01	/* clock source select 8 */
+
+#define EPLD2_ETH_MODE_10	0x80	/* Ethernet mode 10   (default = 1) */
+#define EPLD2_ETH_MODE_100	0x40	/* Ethernet mode 100  (default = 1) */
+#define EPLD2_ETH_MODE_1000	0x20	/* Ethernet mode 1000 (default = 1) */
+#define EPLD2_ETH_DUPLEX_MODE	0x10	/* Ethernet force full duplex mode */
+#define EPLD2_RESET_ETH_N	0x08	/* Ethernet reset (default = 1) */
+#define EPLD2_ETH_AUTO_NEGO	0x04	/* Ethernet auto negotiation */
+#define EPLD2_DEFAULT_UART_N	0x01	/* 0 select DSR DTR for UART1 */
+
+#define EPLD3_STATUS_LED4	0x08	/* status LED 8 (1 = LED on) */
+#define EPLD3_STATUS_LED3	0x04	/* status LED 4 (1 = LED on) */
+#define EPLD3_STATUS_LED2	0x02	/* status LED 2 (1 = LED on) */
+#define EPLD3_STATUS_LED1	0x01	/* status LED 1 (1 = LED on) */
+
+#define EPLD4_PCIL0_VTH1	0x80	/* PCI-X 0 VTH1 status */
+#define EPLD4_PCIL0_VTH2	0x40	/* PCI-X 0 VTH2 status */
+#define EPLD4_PCIL0_VTH3	0x20	/* PCI-X 0 VTH3 status */
+#define EPLD4_PCIL0_VTH4	0x10	/* PCI-X 0 VTH4 status */
+#define EPLD4_PCIX1_VTH1	0x08	/* PCI-X 1 VTH1 status */
+#define EPLD4_PCIX1_VTH2	0x04	/* PCI-X 1 VTH2 status */
+#define EPLD4_PCIX1_VTH3	0x02	/* PCI-X 1 VTH3 status */
+#define EPLD4_PCIX1_VTH4	0x01	/* PCI-X 1 VTH4 status */
+
+#define EPLD5_PCIL0_INT0	0x80	/* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIL0_INT1	0x40	/* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIL0_INT2	0x20	/* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIL0_INT3	0x10	/* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIX1_INT0	0x08	/* PCIX1 INT0 status, write 0 to reset */
+#define EPLD5_PCIX1_INT1	0x04	/* PCIX1 INT1 status, write 0 to reset */
+#define EPLD5_PCIX1_INT2	0x02	/* PCIX1 INT2 status, write 0 to reset */
+#define EPLD5_PCIX1_INT3	0x01	/* PCIX1 INT3 status, write 0 to reset */
+
+#define EPLD6_PCIL0_RESET_CTL	0x80	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIX1_RESET_CTL	0x40	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_ETH_INT_MODE	0x20	/* 0=IRQ5 recv's external eth int */
+#define EPLD6_PCIX2_RESET_CTL	0x10	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCI1_CLKCNTL1	0x80	/* PCI1 clock control S*0 of 9531 */
+#define EPLD6_PCI1_CLKCNTL2	0x40	/* PCI1 clock control S*1 of 9531 */
+#define EPLD6_PCI2_CLKCNTL1	0x20	/* PCI2 clock control S*0 of 9531 */
+#define EPLD6_PCI2_CLKCNTL2	0x10	/* PCI2 clock control S*1 of 9531 */
+
+#define EPLD7_VTH1		0x80	/* PCI2 VTH1 status */
+#define EPLD7_VTH2		0x40	/* PCI2 VTH2 status */
+#define EPLD7_VTH3		0x20	/* PCI2 VTH3 status */
+#define EPLD7_VTH4		0x10	/* PCI2 VTH4 status */
+#define EPLD7_INTA_MODE		0x80	/* see S5 on SW2 for details */
+#define EPLD7_PCI_INT_MODE_N	0x40	/* see S1 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_GPIO	0x20	/* see S2 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_INT	0x10	/* see S3 on SW2 for details */
+
+
+typedef struct {
+    unsigned char  status;		/* misc status */
+    unsigned char  clock;		/* clock status, PCI-X clock control */
+    unsigned char  ethuart;		/* Ethernet, UART status */
+    unsigned char  leds;		/* LED register */
+    unsigned char  vth01;		/* PCI0, PCI1 VTH register */
+    unsigned char  pciints;		/* PCI0, PCI1 interrupts */
+    unsigned char  pci2;		/* PCI2 interrupts, clock control */
+    unsigned char  vth2;		/* PCI2 VTH register */
+    unsigned char  filler1[4096-8];
+    unsigned char  gpio00;		/* GPIO bits  0-7 */
+    unsigned char  gpio08;		/* GPIO bits  8-15 */
+    unsigned char  gpio16;		/* GPIO bits 16-23 */
+    unsigned char  gpio24;		/* GPIO bits 24-31 */
+    unsigned char  filler2[4096-4];
+    unsigned char  version;		/* EPLD version */
+} epld_t;
diff --git a/u-boot/board/amcc/luan/flash.c b/u-boot/board/amcc/luan/flash.c
new file mode 100644
index 0000000..8088509
--- /dev/null
+++ b/u-boot/board/amcc/luan/flash.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{0xff900000, 0xff980000, 0xffc00000},	/* 0:000: configuraton 3 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *)
+					   flash_addr_table[index][i],
+					   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[2]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/u-boot/board/amcc/luan/init.S b/u-boot/board/amcc/luan/init.S
new file mode 100644
index 0000000..7cca319
--- /dev/null
+++ b/u-boot/board/amcc/luan/init.S
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
+
+	tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
+	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
+	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
+	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
+	tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	/* internal ram (l2 cache) */
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
+
+	/* peripherals at f0000000 */
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
+
+	/* PCI */
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/luan/luan.c b/u-boot/board/amcc/luan/luan.c
new file mode 100644
index 0000000..b2595a8
--- /dev/null
+++ b/u-boot/board/amcc/luan/luan.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2005
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-isram.h>
+#include <spd_sdram.h>
+#include "epld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*************************************************************************
+ *  int board_early_init_f()
+ *
+ ************************************************************************/
+int board_early_init_f(void)
+{
+	u32 mfr;
+
+	mtebc( PB0AP,  0x03800000 );	/* set chip selects */
+	mtebc( PB0CR,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+	mtebc( PB1AP,  0x03800000 );
+	mtebc( PB1CR,  0xff018000 );	/* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+	mtebc( PB2AP,  0x03800000 );
+	mtebc( PB2CR,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+
+	mtdcr( UIC1SR, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( UIC1ER, 0x00000000 );	/* disable all interrupts */
+	mtdcr( UIC1CR, 0x00000000 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( UIC1PR, 0x7fff83ff );	/* Set Interrupt Polarities */
+	mtdcr( UIC1TR, 0x001f8000 );	/* Set Interrupt Trigger Levels */
+	mtdcr( UIC1VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( UIC1SR, 0x00000000 );	/* clear all interrupts */
+	mtdcr( UIC1SR, 0xffffffff );
+
+	mtdcr( UIC0SR, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( UIC0ER, 0x00000000 );	/* disable all interrupts excepted cascade */
+	mtdcr( UIC0CR, 0x00000001 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( UIC0PR, 0xffffffff );	/* Set Interrupt Polarities */
+	mtdcr( UIC0TR, 0x01000004 );	/* Set Interrupt Trigger Levels */
+	mtdcr( UIC0VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( UIC0SR, 0x00000000 );	/* clear all interrupts */
+	mtdcr( UIC0SR, 0xffffffff );
+
+	mfsdr(SDR0_MFR, mfr);
+	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
+	mtsdr(SDR0_MFR, mfr);
+
+	return  0;
+}
+
+
+/*************************************************************************
+ *  int misc_init_r()
+ *
+ ************************************************************************/
+int misc_init_r(void)
+{
+	volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
+
+	/* set modes of operation */
+	x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+		EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+	/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+	x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+	/* put Ethernet+PHY in reset */
+	x->ethuart &= ~EPLD2_RESET_ETH_N;
+	udelay(10000);
+	/* take Ethernet+PHY out of reset */
+	x->ethuart |= EPLD2_RESET_ETH_N;
+
+	return  0;
+}
+
+
+/*************************************************************************
+ *  int checkboard()
+ *
+ ************************************************************************/
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Luan - AMCC PPC440SP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return  0;
+}
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+}
+#endif
+
+
+/*************************************************************************
+ *  int on_off()
+ *
+ ************************************************************************/
+static int on_off( const char *s )
+{
+	if (strcmp(s, "on") == 0) {
+		return  1;
+	} else if (strcmp(s, "off") == 0) {
+		return  0;
+	}
+	return  -1;
+}
+
+
+/*************************************************************************
+ *  void l2cache_disable()
+ *
+ ************************************************************************/
+static void l2cache_disable(void)
+{
+	mtdcr( L2_CACHE_CFG, 0 );
+}
+
+
+/*************************************************************************
+ *  void l2cache_enable()
+ *
+ ************************************************************************/
+static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
+{
+	mtdcr( L2_CACHE_CFG, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
+
+	mtdcr( L2_CACHE_ADDR, 0 );		/* set L2_ADDR with all zeros */
+
+	mtdcr( L2_CACHE_CMD, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
+
+	while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
+
+	mtdcr( L2_CACHE_CMD, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
+
+	mtdcr( L2_CACHE_CMD, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
+
+	mtdcr( L2_CACHE_SNP0, 0 );		/* snoop registers */
+	mtdcr( L2_CACHE_SNP1, 0 );
+
+	__asm__ volatile ("sync");		/* msync */
+
+	mtdcr( L2_CACHE_CFG, 0xe0000000 );	/* inst and data use L2 */
+
+	__asm__ volatile ("sync");
+}
+
+
+/*************************************************************************
+ *  int l2cache_status()
+ *
+ ************************************************************************/
+static int l2cache_status(void)
+{
+	return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
+}
+
+
+/*************************************************************************
+ *  int do_l2cache()
+ *
+ ************************************************************************/
+int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
+{
+	switch (argc) {
+	case 2:			/* on / off	*/
+		switch (on_off(argv[1])) {
+		case 0:	l2cache_disable();
+			break;
+		case 1:	l2cache_enable();
+			break;
+		}
+		/* FALL TROUGH */
+	case 1:			/* get status */
+		printf ("L2 Cache is %s\n",
+			l2cache_status() ? "ON" : "OFF");
+		return 0;
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return  0;
+}
+
+
+U_BOOT_CMD(
+	l2cache,   2,   1,     do_l2cache,
+	"enable or disable L2 cache",
+	"[on, off]\n"
+	"    - enable or disable L2 cache"
+);
diff --git a/u-boot/board/amcc/makalu/Makefile b/u-boot/board/amcc/makalu/Makefile
new file mode 100644
index 0000000..e10fadb
--- /dev/null
+++ b/u-boot/board/amcc/makalu/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o cmd_pll.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/makalu/cmd_pll.c b/u-boot/board/amcc/makalu/cmd_pll.c
new file mode 100644
index 0000000..7f75ad7
--- /dev/null
+++ b/u-boot/board/amcc/makalu/cmd_pll.c
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * ehnus: change pll frequency.
+ * Wed Sep  5 11:45:17 CST 2007
+ * hsun@udtech.com.cn
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <i2c.h>
+
+#ifdef CONFIG_CMD_EEPROM
+
+#define EEPROM_CONF_OFFSET		0
+#define EEPROM_TEST_OFFSET		16
+#define EEPROM_SDSTP_PARAM		16
+
+#define PLL_NAME_MAX			12
+#define BUF_STEP			8
+
+/* eeprom_wirtes 8Byte per op. */
+#define EEPROM_ALTER_FREQ(freq)						\
+	do {								\
+		int __i;						\
+		for (__i = 0; __i < 2; __i++)				\
+			eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR,		\
+				      EEPROM_CONF_OFFSET + __i*BUF_STEP, \
+				      pll_select[freq],			\
+				      BUF_STEP + __i*BUF_STEP);		\
+	} while (0)
+
+#define PDEBUG
+#ifdef	PDEBUG
+#define PLL_DEBUG	pll_debug(EEPROM_CONF_OFFSET)
+#else
+#define PLL_DEBUG
+#endif
+
+typedef enum {
+	PLL_ebc20,
+	PLL_333,
+	PLL_4001,
+	PLL_4002,
+	PLL_533,
+	PLL_600,
+	PLL_666,	/* For now, kilauea can't support */
+	RCONF,
+	WTEST,
+	PLL_TOTAL
+} pll_freq_t;
+
+static const char
+pll_name[][PLL_NAME_MAX] = {
+	"PLL_ebc20",
+	"PLL_333",
+	"PLL_400@1",
+	"PLL_400@2",
+	"PLL_533",
+	"PLL_600",
+	"PLL_666",
+	"RCONF",
+	"WTEST",
+	""
+};
+
+/*
+ * ehnus:
+ */
+static uchar
+pll_select[][EEPROM_SDSTP_PARAM] = {
+	/* 0: CPU 333MHz EBC 20MHz, for test only */
+	{
+		0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 0: 333 */
+	{
+		0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 1: 400_266 */
+	{
+		0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 2: 400 */
+	{
+		0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 3: 533 */
+	{
+		0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 4: 600 */
+	{
+		0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 5: 666 */
+	{
+		0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	{}
+};
+
+static uchar
+testbuf[EEPROM_SDSTP_PARAM] = {
+	0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+	0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+};
+
+static void
+pll_debug(int off)
+{
+	int i;
+	uchar buffer[EEPROM_SDSTP_PARAM];
+
+	memset(buffer, 0, sizeof(buffer));
+	eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
+		    buffer, EEPROM_SDSTP_PARAM);
+
+	printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
+	for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
+		printf("%02x ", buffer[i]);
+	printf("\n");
+}
+
+static void
+test_write(void)
+{
+	printf("Debug: test eeprom_write ... ");
+
+	/*
+	 * Write twice, 8 bytes per write
+	 */
+	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+		      testbuf, 8);
+	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+		      testbuf, 16);
+	printf("done\n");
+
+	pll_debug(EEPROM_TEST_OFFSET);
+}
+
+int
+do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char c = '\0';
+	pll_freq_t pll_freq;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
+		if (!strcmp(pll_name[pll_freq], argv[1]))
+			break;
+	}
+
+	switch (pll_freq) {
+	case PLL_ebc20:
+	case PLL_333:
+	case PLL_4001:
+	case PLL_4002:
+	case PLL_533:
+	case PLL_600:
+		EEPROM_ALTER_FREQ(pll_freq);
+		break;
+
+	case PLL_666:		/* not support */
+		printf("Choose this option will result in a boot failure."
+		       "\nContinue? (Y/N): ");
+
+		c = getc(); putc('\n');
+
+		if ((c == 'y') || (c == 'Y')) {
+			EEPROM_ALTER_FREQ(pll_freq);
+			break;
+		}
+		goto ret;
+
+	case RCONF:
+		pll_debug(EEPROM_CONF_OFFSET);
+		goto ret;
+	case WTEST:
+		printf("DEBUG: write test\n");
+		test_write();
+		goto ret;
+
+	default:
+		printf("Invalid options\n\n");
+		return cmd_usage(cmdtp);
+	}
+
+	printf("PLL set to %s, "
+	       "reset the board to take effect\n", pll_name[pll_freq]);
+
+	PLL_DEBUG;
+ret:
+	return 0;
+}
+
+U_BOOT_CMD(
+	pllalter, CONFIG_SYS_MAXARGS, 1,        do_pll_alter,
+	"change pll frequence",
+	"pllalter <selection>      - change pll frequence \n\n\
+	** New freq take effect after reset. ** \n\
+	----------------------------------------------\n\
+	PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	Same as PLL_333	\n\
+	\t	except          \n\
+	\t	EBC: 20 MHz     \n\
+	----------------------------------------------\n\
+	PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 666 MHz  \n\
+	\t	CPU: 333 MHz  \n\
+	\t	PLB: 166 MHz  \n\
+	\t	OPB: 83 MHz   \n\
+	\t	DDR: 83 MHz   \n\
+	------------------------------------------------\n\
+	PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 800 MHz  \n\
+	\t	CPU: 400 MHz  \n\
+	\t	PLB: 133 MHz  \n\
+	\t	OPB: 66  MHz  \n\
+	\t	DDR: 133 MHz  \n\
+	------------------------------------------------\n\
+	PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 800 MHz  \n\
+	\t	CPU: 400 MHz  \n\
+	\t	PLB: 200 MHz  \n\
+	\t	OPB: 100 MHz  \n\
+	\t	DDR: 200 MHz  \n\
+	----------------------------------------------\n\
+	PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 1066 MHz  \n\
+	\t	CPU: 533  MHz  \n\
+	\t	PLB: 177  MHz  \n\
+	\t	OPB: 88   MHz  \n\
+	\t	DDR: 177  MHz  \n\
+	----------------------------------------------\n\
+	PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 1200 MHz  \n\
+	\t	CPU: 600  MHz  \n\
+	\t	PLB: 200  MHz  \n\
+	\t	OPB: 100  MHz  \n\
+	\t	DDR: 200  MHz  \n\
+	----------------------------------------------\n\
+	PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 1333 MHz  \n\
+	\t	CPU: 666  MHz  \n\
+	\t	PLB: 166  MHz  \n\
+	\t	OPB: 83   MHz  \n\
+	\t	DDR: 166  MHz  \n\
+	-----------------------------------------------\n\
+	RCONF: Read current eeprom configuration.      \n\
+	-----------------------------------------------\n\
+	WTEST: Test EEPROM write with predefined values\n\
+	-----------------------------------------------"
+);
+
+#endif	/* CONFIG_CMD_EEPROM */
diff --git a/u-boot/board/amcc/makalu/init.S b/u-boot/board/amcc/makalu/init.S
new file mode 100644
index 0000000..4d0f460
--- /dev/null
+++ b/u-boot/board/amcc/makalu/init.S
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Originally based on code provided from Senao and AMCC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.globl  ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	blr
diff --git a/u-boot/board/amcc/makalu/makalu.c b/u-boot/board/amcc/makalu/makalu.c
new file mode 100644
index 0000000..483df66
--- /dev/null
+++ b/u-boot/board/amcc/makalu/makalu.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <asm/errno.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+	u32 val;
+
+	/*--------------------------------------------------------------------+
+	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+	 +--------------------------------------------------------------------+
+	+---------------------------------------------------------------------+
+	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+	+---------+-----------------------------------+-------+-------+-------+
+	| IRQ 00  | UART0                             | High  | Level | Non   |
+	| IRQ 01  | UART1                             | High  | Level | Non   |
+	| IRQ 02  | IIC0                              | High  | Level | Non   |
+	| IRQ 03  | TBD                               | High  | Level | Non   |
+	| IRQ 04  | TBD                               | High  | Level | Non   |
+	| IRQ 05  | EBM                               | High  | Level | Non   |
+	| IRQ 06  | BGI                               | High  | Level | Non   |
+	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
+	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
+	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
+	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
+	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
+	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
+	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
+	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
+	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
+	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
+	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
+	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
+	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
+	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
+	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
+	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
+	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
+	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
+	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
+	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
+	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
+	|----------------------------------------------------------------------
+	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
+	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
+	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
+	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
+	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
+	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
+	| IRQ 38  | NDFC                              | High  | Level | Non   |
+	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
+	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
+	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
+	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
+	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
+	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
+	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
+	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
+	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
+	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
+	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
+	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
+	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
+	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
+	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
+	|----------------------------------------------------------------------
+	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
+	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
+	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
+	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
+	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
+	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
+	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
+	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
+	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
+	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
+	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
+	|---------------------------------------------------------------------
+	+---------+-----------------------------------+-------+-------+------*/
+	/*--------------------------------------------------------------------+
+	 | Initialise UIC registers.  Clear all interrupts.  Disable all
+	 | interrupts.
+	 | Set critical interrupt values.  Set interrupt polarities.  Set
+	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 | interrupts again.
+	 +-------------------------------------------------------------------*/
+
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
+					/* Except cascade UIC0 and UIC1 */
+	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
+	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
+
+	/*
+	 * Note: Some cores are still in reset when the chip starts, so
+	 * take them out of reset
+	 */
+	mtsdr(SDR0_SRST, 0);
+
+	/* Reset PCIe slots */
+	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
+	udelay(100);
+	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * -> Enable USB
+	 */
+	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+	mtsdr(SDR0_PFC1, val);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      -CONFIG_SYS_MONITOR_LEN,
+		      0xffffffff,
+		      &flash_info[0]);
+#endif
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
diff --git a/u-boot/board/amcc/ocotea/Makefile b/u-boot/board/amcc/ocotea/Makefile
new file mode 100644
index 0000000..b5d0fe5
--- /dev/null
+++ b/u-boot/board/amcc/ocotea/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/ocotea/config.mk b/u-boot/board/amcc/ocotea/config.mk
new file mode 100644
index 0000000..75634ad
--- /dev/null
+++ b/u-boot/board/amcc/ocotea/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440GX Reference Platform (Ocotea) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/ocotea/flash.c b/u-boot/board/amcc/ocotea/flash.c
new file mode 100644
index 0000000..fbc552b
--- /dev/null
+++ b/u-boot/board/amcc/ocotea/flash.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define     BOOT_SMALL_FLASH        0x40	/* 01000000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+
+#define     BOOT_SMALL_FLASH_VAL    4
+#define     FLASH_ONBD_N_VAL        2
+#define     FLASH_SRAM_SEL_VAL      1
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
+	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
+	{0xFFF00000, 0xFFF80000, 0xFF800000},	/* 5:101: configuraton 1 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 6:110: configuraton 6 */
+	{0x00000000, 0x00000000, 0x00000000}	/* 7:111: configuraton 5 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	/* check the bitmap of switch status */
+	if (switch_status & BOOT_SMALL_FLASH) {
+		index += BOOT_SMALL_FLASH_VAL;
+	}
+	if (switch_status & FLASH_ONBD_N) {
+		index += FLASH_ONBD_N_VAL;
+	}
+	if (switch_status & FLASH_SRAM_SEL) {
+		index += FLASH_SRAM_SEL_VAL;
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] =
+		    flash_get_size((vu_long *) flash_addr_table[index][i],
+				   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf
+			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			     i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/u-boot/board/amcc/ocotea/init.S b/u-boot/board/amcc/ocotea/init.S
new file mode 100644
index 0000000..39f5a02
--- /dev/null
+++ b/u-boot/board/amcc/ocotea/init.S
@@ -0,0 +1,58 @@
+/*
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/ocotea/ocotea.c b/u-boot/board/amcc/ocotea/ocotea.c
new file mode 100644
index 0000000..bbb5331
--- /dev/null
+++ b/u-boot/board/amcc/ocotea/ocotea.c
@@ -0,0 +1,402 @@
+/*
+ *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include "ocotea.h"
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <asm/ppc4xx-emac.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+void fpga_init (void);
+
+int board_early_init_f (void)
+{
+	unsigned long mfr;
+	unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned long cs0_base;
+	unsigned long cs0_size;
+	unsigned long cs0_twt;
+	unsigned long cs2_base;
+	unsigned long cs2_size;
+	unsigned long cs2_twt;
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	if (switch_status & 0x40) {
+		cs0_base = 0xFFE00000;
+		cs0_size = EBC_BXCR_BS_2MB;
+		cs0_twt = 8;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_4MB;
+		cs2_twt = 10;
+	} else {
+		cs0_base = 0xFFC00000;
+		cs0_size = EBC_BXCR_BS_4MB;
+		cs0_twt = 10;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_2MB;
+		cs2_twt = 8;
+	}
+
+	/*-------------------------------------------------------------------------+
+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
+	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | 4 MB FLASH. Initialize bank 2 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
+	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC0SR, 0xfc000000); /* clear all */
+	mtdcr (UIC0ER, 0x00000000); /* disable all */
+	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000); /* */
+	mtdcr (UIC0TR, 0x00000000); /* */
+	mtdcr (UIC0VR, 0x00000001); /* */
+	mfsdr (SDR0_MFR, mfr);
+	mfr &= ~SDR0_MFR_ECS_MASK;
+/*	mtsdr(SDR0_MFR, mfr); */
+	fpga_init();
+
+	return 0;
+}
+
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    128 MB, non-ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram (SDRAM0_SLIO, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */
+	mtsdram (SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram (SDRAM0_WDDCTR, 0x00000000);	/* wrcp=0 dcd=0                 */
+	mtsdram (SDRAM0_CLKTR, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (SDRAM0_TR0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3                       */
+	mtsdram (SDRAM0_TR1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (SDRAM0_RTR, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram (SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (SDRAM0_CFG0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
+	for (;;) {
+		mfsdram (SDRAM0_MCSTS, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB                           */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+void fpga_init(void)
+{
+	unsigned long group;
+	unsigned long sdr0_pfc0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_cust0;
+	unsigned long pvr;
+
+	mfsdr (SDR0_PFC0, sdr0_pfc0);
+	mfsdr (SDR0_PFC1, sdr0_pfc1);
+	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
+	pvr = get_pvr ();
+
+	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
+	if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
+		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+		out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+		     FPGA_REG2_EXT_INTFACE_ENABLE);
+		mtsdr (SDR0_PFC0, sdr0_pfc0);
+		mtsdr (SDR0_PFC1, sdr0_pfc1);
+	} else {
+		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
+		switch (group)
+		{
+		case 0:
+		case 1:
+		case 2:
+			/* CPU trace A */
+			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+			     FPGA_REG2_EXT_INTFACE_ENABLE);
+			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+			mtsdr (SDR0_PFC0, sdr0_pfc0);
+			mtsdr (SDR0_PFC1, sdr0_pfc1);
+			break;
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			/* CPU trace B - Over EBMI */
+			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
+			mtsdr (SDR0_PFC0, sdr0_pfc0);
+			mtsdr (SDR0_PFC1, sdr0_pfc1);
+			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+			     FPGA_REG2_EXT_INTFACE_DISABLE);
+			break;
+		}
+	}
+
+	/* Initialize the ethernet specific functions in the fpga */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
+	    ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
+	     (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+			     FPGA_REG3_ENET_GROUP7);
+		}
+		else
+		{
+			if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
+			{
+				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+				     FPGA_REG3_ENET_GROUP7);
+			}
+			else
+			{
+				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+				     FPGA_REG3_ENET_GROUP8);
+			}
+		}
+	}
+	else
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+			     FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+		}
+		else
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+			     FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+		}
+	}
+	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
+	     FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
+	     FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
+
+	/* reset the gigabyte phy if necessary */
+	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
+			udelay(10000);
+			out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
+		}
+		else
+		{
+			out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
+			udelay(10000);
+			out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
+		}
+	}
+
+	/*
+	 * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
+	 */
+	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
+		out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
+		udelay(10000);
+		out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
+	}
+
+	/* Turn off the LED's */
+	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
+	     FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
+	     FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
+
+	return;
+}
diff --git a/u-boot/board/amcc/ocotea/ocotea.h b/u-boot/board/amcc/ocotea/ocotea.h
new file mode 100644
index 0000000..400852a
--- /dev/null
+++ b/u-boot/board/amcc/ocotea/ocotea.h
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Board specific FPGA stuff ... */
+#define FPGA_REG0                       (CONFIG_SYS_FPGA_BASE + 0x00)
+#define   FPGA_REG0_SSCG_MASK             0x80
+#define   FPGA_REG0_SSCG_DISABLE          0x00
+#define   FPGA_REG0_SSCG_ENABLE           0x80
+#define   FPGA_REG0_BOOT_MASK             0x40
+#define   FPGA_REG0_BOOT_LARGE_FLASH      0x00
+#define   FPGA_REG0_BOOT_SMALL_FLASH      0x40
+#define   FPGA_REG0_ECLS_MASK             0x38  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_0                0x20  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_1                0x10  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_2                0x08  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER1             0x00  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER3             0x08  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER4             0x10  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER5             0x18  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER2             0x20  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER6             0x28  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER7             0x30  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER8             0x38  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ARBITER_MASK          0x04
+#define   FPGA_REG0_ARBITER_EXT           0x00
+#define   FPGA_REG0_ARBITER_INT           0x04
+#define   FPGA_REG0_ONBOARD_FLASH_MASK    0x02
+#define   FPGA_REG0_ONBOARD_FLASH_ENABLE  0x00
+#define   FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
+#define   FPGA_REG0_FLASH                 0x01
+#define FPGA_REG1                       (CONFIG_SYS_FPGA_BASE + 0x01)
+#define   FPGA_REG1_9772_FSELFBX_MASK     0x80
+#define   FPGA_REG1_9772_FSELFBX_6        0x00
+#define   FPGA_REG1_9772_FSELFBX_10       0x80
+#define   FPGA_REG1_9531_SX_MASK          0x60
+#define   FPGA_REG1_9531_SX_33MHZ         0x00
+#define   FPGA_REG1_9531_SX_100MHZ        0x20
+#define   FPGA_REG1_9531_SX_66MHZ         0x40
+#define   FPGA_REG1_9531_SX_133MHZ        0x60
+#define   FPGA_REG1_9772_FSELBX_MASK      0x18
+#define   FPGA_REG1_9772_FSELBX_4         0x00
+#define   FPGA_REG1_9772_FSELBX_6         0x08
+#define   FPGA_REG1_9772_FSELBX_8         0x10
+#define   FPGA_REG1_9772_FSELBX_10        0x18
+#define   FPGA_REG1_SOURCE_MASK           0x07
+#define   FPGA_REG1_SOURCE_TC             0x00
+#define   FPGA_REG1_SOURCE_66MHZ          0x01
+#define   FPGA_REG1_SOURCE_50MHZ          0x02
+#define   FPGA_REG1_SOURCE_33MHZ          0x03
+#define   FPGA_REG1_SOURCE_25MHZ          0x04
+#define   FPGA_REG1_SOURCE_SSDIV1         0x05
+#define   FPGA_REG1_SOURCE_SSDIV2         0x06
+#define   FPGA_REG1_SOURCE_SSDIV4         0x07
+#define FPGA_REG2                       (CONFIG_SYS_FPGA_BASE + 0x02)
+#define   FPGA_REG2_TC0                   0x80
+#define   FPGA_REG2_TC1                   0x40
+#define   FPGA_REG2_TC2                   0x20
+#define   FPGA_REG2_TC3                   0x10
+#define   FPGA_REG2_GIGABIT_RESET_DISABLE 0x08   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG2_EXT_INTFACE_MASK      0x04
+#define   FPGA_REG2_EXT_INTFACE_ENABLE    0x00
+#define   FPGA_REG2_EXT_INTFACE_DISABLE   0x04
+#define   FPGA_REG2_SMII_RESET_DISABLE    0x02   /*Use on Ocotea pass 3 boards*/
+#define   FPGA_REG2_DEFAULT_UART1_N       0x01
+#define FPGA_REG3                       (CONFIG_SYS_FPGA_BASE + 0x03)
+#define   FPGA_REG3_GIGABIT_RESET_DISABLE 0x80   /*Use on Ocotea pass 1 boards*/
+#define   FPGA_REG3_ENET_MASK1            0x70   /*Use on Ocotea pass 1 boards*/
+#define   FPGA_REG3_ENET_MASK2            0xF0   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG3_ENET_GROUP0           0x00
+#define   FPGA_REG3_ENET_GROUP1           0x10
+#define   FPGA_REG3_ENET_GROUP2           0x20
+#define   FPGA_REG3_ENET_GROUP3           0x30
+#define   FPGA_REG3_ENET_GROUP4           0x40
+#define   FPGA_REG3_ENET_GROUP5           0x50
+#define   FPGA_REG3_ENET_GROUP6           0x60
+#define   FPGA_REG3_ENET_GROUP7           0x70
+#define   FPGA_REG3_ENET_GROUP8           0x80   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
+#define   FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
+#define   FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
+#define   FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
+#define   FPGA_REG3_STAT_MASK             0x0F
+#define   FPGA_REG3_STAT_LED8_ENAB        0x08
+#define   FPGA_REG3_STAT_LED4_ENAB        0x04
+#define   FPGA_REG3_STAT_LED2_ENAB        0x02
+#define   FPGA_REG3_STAT_LED1_ENAB        0x01
+#define   FPGA_REG3_STAT_LED8_DISAB       0x00
+#define   FPGA_REG3_STAT_LED4_DISAB       0x00
+#define   FPGA_REG3_STAT_LED2_DISAB       0x00
+#define   FPGA_REG3_STAT_LED1_DISAB       0x00
+#define FPGA_REG4                       (CONFIG_SYS_FPGA_BASE + 0x04)
+#define   FPGA_REG4_GPHY_MODE10           0x80
+#define   FPGA_REG4_GPHY_MODE100          0x40
+#define   FPGA_REG4_GPHY_MODE1000         0x20
+#define   FPGA_REG4_GPHY_FRC_DPLX         0x10
+#define   FPGA_REG4_GPHY_ANEG_DIS         0x08
+#define   FPGA_REG4_CONNECT_PHYS          0x04
+
+
+#define   SDR0_CUST0_ENET3_MASK         0x00000080
+#define   SDR0_CUST0_ENET3_COPPER       0x00000000
+#define   SDR0_CUST0_ENET3_FIBER        0x00000080
+#define   SDR0_CUST0_RGMII3_MASK        0x00000070
+#define   SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+#define   SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+#define   SDR0_CUST0_RGMII3_DISAB       0x00000000
+#define   SDR0_CUST0_RGMII3_RTBI        0x00000040
+#define   SDR0_CUST0_RGMII3_RGMII       0x00000050
+#define   SDR0_CUST0_RGMII3_TBI         0x00000060
+#define   SDR0_CUST0_RGMII3_GMII        0x00000070
+#define   SDR0_CUST0_ENET2_MASK         0x00000008
+#define   SDR0_CUST0_ENET2_COPPER       0x00000000
+#define   SDR0_CUST0_ENET2_FIBER        0x00000008
+#define   SDR0_CUST0_RGMII2_MASK        0x00000007
+#define   SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define   SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+#define   SDR0_CUST0_RGMII2_DISAB       0x00000000
+#define   SDR0_CUST0_RGMII2_RTBI        0x00000004
+#define   SDR0_CUST0_RGMII2_RGMII       0x00000005
+#define   SDR0_CUST0_RGMII2_TBI         0x00000006
+#define   SDR0_CUST0_RGMII2_GMII        0x00000007
diff --git a/u-boot/board/amcc/redwood/Makefile b/u-boot/board/amcc/redwood/Makefile
new file mode 100644
index 0000000..8759001
--- /dev/null
+++ b/u-boot/board/amcc/redwood/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/redwood/config.mk b/u-boot/board/amcc/redwood/config.mk
new file mode 100644
index 0000000..f10d812
--- /dev/null
+++ b/u-boot/board/amcc/redwood/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 460SX Reference Platform (redwood) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/redwood/init.S b/u-boot/board/amcc/redwood/init.S
new file mode 100644
index 0000000..47f700b
--- /dev/null
+++ b/u-boot/board/amcc/redwood/init.S
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	/* Although 512 KB, map 256k at a time */
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
+
+	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+
+	/*
+	 * Peripheral base
+	 */
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/redwood/redwood.c b/u-boot/board/amcc/redwood/redwood.c
new file mode 100644
index 0000000..bb7565e
--- /dev/null
+++ b/u-boot/board/amcc/redwood/redwood.c
@@ -0,0 +1,456 @@
+/*
+ * This is the main board level file for the Redwood AMCC board.
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include "redwood.h"
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+int compare_to_true(char *str);
+char *remove_l_w_space(char *in_str);
+char *remove_t_w_space(char *in_str);
+int get_console_port(void);
+
+static void early_init_EBC(void);
+static int bootdevice_selected(void);
+static void early_reinit_EBC(int);
+static void early_init_UIC(void);
+
+/*
+ * Define Boot devices
+ */
+#define BOOT_FROM_8BIT_SRAM			0x00
+#define BOOT_FROM_16BIT_SRAM			0x01
+#define BOOT_FROM_32BIT_SRAM			0x02
+#define BOOT_FROM_8BIT_NAND			0x03
+#define BOOT_FROM_16BIT_NOR			0x04
+#define BOOT_DEVICE_UNKNOWN			0xff
+
+/*
+ * EBC Devices Characteristics
+ *   Peripheral Bank Access Parameters       -   EBC_BxAP
+ *   Peripheral Bank Configuration Register  -   EBC_BxCR
+ */
+
+/*
+ * 8 bit width SRAM
+ * BU Value
+ * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_8BIT_SRAM					\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXAP_16BIT_SRAM	EBC_BXAP_8BIT_SRAM
+#define EBC_BXAP_32BIT_SRAM	EBC_BXAP_8BIT_SRAM
+
+/*
+ * NAND flash
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NAND						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+/*
+ * NOR flash
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NOR						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(11) |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1)  |	\
+	EBC_BXAP_WBN_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(1)  |	\
+	EBC_BXAP_TH_ENCODE(1)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_RW         |	\
+	EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_8BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_32BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_NAND_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_16BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS1						\
+	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NAND_CS1						\
+	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_NAND_CS2						\
+	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SRAM_CS2						\
+	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2					\
+	EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_FPGA_CS3						\
+	EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+/*****************************************************************************
+ * UBOOT initiated board specific function calls
+ ****************************************************************************/
+
+int board_early_init_f(void)
+{
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*
+	 * Initialise EBC
+	 */
+	early_init_EBC();
+
+	/*
+	 * Determine which boot device was selected
+	 */
+	computed_boot_device = bootdevice_selected();
+
+	/*
+	 * Reinit EBC based on selected boot device
+	 */
+	early_reinit_EBC(computed_boot_device);
+
+	/*
+	 * Setup for UIC on 460SX redwood board
+	 */
+	early_init_UIC();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Redwood - AMCC 460SX Reference Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+static void early_init_EBC(void)
+{
+	/*
+	 * Initialize EBC CONFIG -
+	 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+	 * default value :
+	 *      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+	 */
+	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_16PERCLK |
+	      EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_OEO_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
+
+	/*
+	 * PART 1 : Initialize EBC Bank 3
+	 * ==============================
+	 * Bank1 is always associated to the EPLD.
+	 * It has to be initialized prior to other banks settings computation
+	 * since some board registers values may be needed to determine the
+	 * boot type
+	 */
+	mtebc(PB1AP, EBC_BXAP_FPGA);
+	mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
+
+}
+
+static int bootdevice_selected(void)
+{
+	unsigned long sdr0_pinstp;
+	unsigned long bootstrap_settings;
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*
+	 *  Determine which boot device was selected
+	 *  =================================================
+	 *
+	 *  Read Pin Strap Register in PPC460SX
+	 *  Result can either be :
+	 *   - Boot strap = boot from EBC 8bits     => Small Flash
+	 *   - Boot strap = boot from PCI
+	 *   - Boot strap = IIC
+	 *  In case of boot from IIC, read Serial Device Strap Register1
+	 *
+	 *  Result can either be :
+	 *   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
+	 *   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
+	 *   - Boot from PCI
+	 */
+
+	/* Read Pin Strap Register in PPC460SX */
+	mfsdr(SDR0_PINSTP, sdr0_pinstp);
+	bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+	switch (bootstrap_settings) {
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+		/*
+		 * Boot from SRAM, 8bit width
+		 */
+		computed_boot_device = BOOT_FROM_8BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+		/*
+		 * Boot from SRAM, 32bit width
+		 */
+		computed_boot_device = BOOT_FROM_32BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+		/*
+		 * Boot from NAND, 8bit width
+		 */
+		computed_boot_device = BOOT_FROM_8BIT_NAND;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+		/*
+		 * Boot from SRAM, 16bit width
+		 * Boot setting in IIC EEPROM 0x50
+		 */
+		computed_boot_device = BOOT_FROM_16BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
+		/*
+		 * Boot from NOR, 16bit width
+		 * Boot setting in IIC EEPROM 0x54
+		 */
+		computed_boot_device = BOOT_FROM_16BIT_NOR;
+		break;
+	default:
+		/* should not be */
+		computed_boot_device = BOOT_DEVICE_UNKNOWN;
+		break;
+	}
+
+	return computed_boot_device;
+}
+
+static void early_reinit_EBC(int computed_boot_device)
+{
+	/*
+	 *  Compute EBC settings depending on selected boot device
+	 *  ======================================================
+	 *
+	 * Resulting EBC init will be among following configurations :
+	 *
+	 *  - Boot from EBC 8bits => boot from Small Flash selected
+	 *            EBC-CS0     = Small Flash
+	 *            EBC-CS2     = Large Flash and SRAM
+	 *
+	 *  - Boot from EBC 16bits => boot from Large Flash or SRAM
+	 *            EBC-CS0     = Large Flash or SRAM
+	 *            EBC-CS2     = Small Flash
+	 *
+	 *  - Boot from PCI
+	 *            EBC-CS0     = not initialized to avoid address contention
+	 *            EBC-CS2     = same as boot from Small Flash selected
+	 */
+
+	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+	unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
+	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+	switch (computed_boot_device) {
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_8BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_16BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_32BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_16BIT_NOR:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_8BIT_NAND:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	default:
+		/*-------------------------------------------------------------------*/
+		/* BOOT_DEVICE_UNKNOWN */
+		break;
+	}
+
+	mtebc(PB0AP, ebc0_cs0_bxap_value);
+	mtebc(PB0CR, ebc0_cs0_bxcr_value);
+	mtebc(PB1AP, ebc0_cs1_bxap_value);
+	mtebc(PB1CR, ebc0_cs1_bxcr_value);
+	mtebc(PB2AP, ebc0_cs2_bxap_value);
+	mtebc(PB2CR, ebc0_cs2_bxcr_value);
+}
+
+static void early_init_UIC(void)
+{
+	/*
+	 * Initialise UIC registers.  Clear all interrupts.  Disable all
+	 * interrupts.
+	 * Set critical interrupt values.  Set interrupt polarities.  Set
+	 * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 * interrupts again.
+	 */
+	mtdcr(UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC3CR, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(UIC3PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all  interrupts */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC2CR, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(UIC2PR, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr(UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC1CR, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC1TR, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all interrupts excepted
+					 * cascade to be checked */
+	mtdcr(UIC0CR, 0x00104001);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(UIC0PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC0TR, 0x000f003c);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all interrupts */
+
+}
diff --git a/u-boot/board/amcc/redwood/redwood.h b/u-boot/board/amcc/redwood/redwood.h
new file mode 100644
index 0000000..89b87e6
--- /dev/null
+++ b/u-boot/board/amcc/redwood/redwood.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REDWOOD_H_
+#define __REDWOOD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+/* Pin Straps Reg */
+#define SDR0_PSTRP0			0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000	/* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000	/* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000	/* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000	/* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000	/* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000	/* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000	/* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000	/* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000	/* Default strap settings 7 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* __REDWOOD_H_ */
diff --git a/u-boot/board/amcc/sequoia/Makefile b/u-boot/board/amcc/sequoia/Makefile
new file mode 100644
index 0000000..efe2065
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	= $(BOARD).o sdram.o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/sequoia/chip_config.c b/u-boot/board/amcc/sequoia/chip_config.c
new file mode 100644
index 0000000..036de9f
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/chip_config.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"333-133-nor", "NOR  CPU: 333 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"333-166-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"333-166-nand", "NAND CPU: 333 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-160-nor", "NOR  CPU: 400 PLB: 160 OPB:  80 EBC:  53",
+		{
+			0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"416-166-nor", "NOR  CPU: 416 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"416-166-nand", "NAND CPU: 416 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"500-166-nor", "NOR  CPU: 500 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"500-166-nand", "NAND CPU: 500 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-133-nor", "NOR  CPU: 533 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667-133-nor", "NOR  CPU: 667 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667-166-nor", "NOR  CPU: 667 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667-166-nand", "NAND CPU: 667 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/amcc/sequoia/config.mk b/u-boot/board/amcc/sequoia/config.mk
new file mode 100644
index 0000000..73efe72
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
diff --git a/u-boot/board/amcc/sequoia/init.S b/u-boot/board/amcc/sequoia/init.S
new file mode 100644
index 0000000..419ef4f
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/init.S
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ */
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/* vxWorks needs this as first entry for the Machine Check interrupt */
+	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
+
+	/*
+	 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
+	 * entry is already configured for SDRAM via the JTAG debugger and mustn't
+	 * be re-initialized by this RAM-booting U-Boot version.
+	 */
+#ifndef CONFIG_SYS_RAMBOOT
+	/* TLB-entry for DDR SDRAM (Up to 2GB) */
+#ifdef CONFIG_4xx_DCACHE
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
+#else
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
+#endif
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/* TLB-entry for EBC */
+	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
+
+	/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+#ifndef CONFIG_NAND_SPL
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+#else
+	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
+#endif
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+	/* TLB-entry for NAND */
+	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
+
+	/*TLB-entry PCI registers*/
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	/* TLB-entry PCI IO Space - from sr@denx.de */
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
+#define TLB02	TLB2(AC_RWX | SA_IG)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/u-boot/board/amcc/sequoia/sdram.c b/u-boot/board/amcc/sequoia/sdram.c
new file mode 100644
index 0000000..5c01def
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/sdram.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc440.h>
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+
+#if defined(CONFIG_NAND_SPL)
+/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val)	133333333
+#endif
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
+    defined(CONFIG_NAND_SPL)
+	ulong speed = get_bus_freq(0);
+
+	mtsdram(DDR0_02, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030602);
+	mtsdram(DDR0_04, 0x0A020200);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0102C812);
+	mtsdram(DDR0_07, 0x000D0100);
+	mtsdram(DDR0_08, 0x02430001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000100);
+	mtsdram(DDR0_11, 0x0027C800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x19000000);
+	mtsdram(DDR0_18, 0x19191919);
+	mtsdram(DDR0_19, 0x19191919);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+	mtsdram(DDR0_22, 0x00267F0B);
+	mtsdram(DDR0_23, 0x00000000);
+	mtsdram(DDR0_24, 0x01010002);
+	if (speed > 133333334)
+		mtsdram(DDR0_26, 0x5B26050C);
+	else
+		mtsdram(DDR0_26, 0x5B260408);
+	mtsdram(DDR0_27, 0x0000682B);
+	mtsdram(DDR0_28, 0x00000000);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000006);
+	mtsdram(DDR0_43, 0x030A0200);
+	mtsdram(DDR0_44, 0x00000003);
+	mtsdram(DDR0_02, 0x00000001);
+
+	denali_wait_for_dlllock();
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+#ifdef CONFIG_DDR_DATA_EYE
+	/* -----------------------------------------------------------+
+	 * Perform data eye search if requested.
+	 * ----------------------------------------------------------*/
+	denali_core_search_data_eye();
+#endif
+
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+}
diff --git a/u-boot/board/amcc/sequoia/sequoia.c b/u-boot/board/amcc/sequoia/sequoia.c
new file mode 100644
index 0000000..b518aa7
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/sequoia.c
@@ -0,0 +1,426 @@
+/*
+ * (C) Copyright 2006-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#endif
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+ulong flash_get_size(ulong base, int banknum);
+
+static inline u32 get_async_pci_freq(void)
+{
+	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+		CONFIG_SYS_BCSR5_PCI66EN)
+		return 66666666;
+	else
+		return 33333333;
+}
+
+int board_early_init_f(void)
+{
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	/* Check and reconfigure the PCI sync clock if necessary */
+	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
+	/* 50MHz tmrclk */
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
+
+	/* clear write protects */
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
+
+	/* enable Ethernet */
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
+
+	/* enable USB device */
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
+
+	/* select Ethernet (and optionally IIC1) pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
+	/* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
+
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_4;
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* PCI arbiter enabled */
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+#if !defined(CONFIG_SYS_NO_FLASH)
+	uint pbcr;
+	int size_val = 0;
+#endif
+#ifdef CONFIG_440EPX
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	char *act = getenv("usbact");
+#endif
+	u32 reg;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+	/* Re-do flash sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+    defined(CONFIG_SYS_RAMBOOT)
+	mtdcr(EBC0_CFGADDR, PB3CR);
+#else
+	mtdcr(EBC0_CFGADDR, PB0CR);
+#endif
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+    defined(CONFIG_SYS_RAMBOOT)
+	mtdcr(EBC0_CFGADDR, PB3CR);
+#else
+	mtdcr(EBC0_CFGADDR, PB0CR);
+#endif
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+#endif
+#endif /* CONFIG_SYS_NO_FLASH */
+
+	/*
+	 * USB suff...
+	 */
+#ifdef CONFIG_440EPX
+	if (act == NULL || strcmp(act, "hostdev") == 0) {
+		/* SDR Setting */
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+		/*
+		 * An 8-bit/60MHz interface is the only possible alternative
+		 * when connecting the Device to the PHY
+		 */
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+		/*
+		 * To enable the USB 2.0 Device function
+		 * through the UTMI interface
+		 */
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
+
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		/*clear resets*/
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	} else if (strcmp(act, "dev") == 0) {
+		/*-------------------PATCH-------------------------------*/
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x672c6000);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000080);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60206000);
+
+		*(unsigned int *)(0xe0000350) = 0x00000001;
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60306000);
+		/*-------------------PATCH-------------------------------*/
+
+		/* SDR Setting */
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+		/* clear resets */
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Device(int phy)\n");
+	}
+#endif /* CONFIG_440EPX */
+
+	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
+	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+	mtsdr(SDR0_SRST1, reg);
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u8 rev;
+	u32 clock = get_async_pci_freq();
+
+#ifdef CONFIG_440EPX
+	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+#else
+	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
+#endif
+
+	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	/*
+	 * Reconfiguration of the PCI sync clock is already done,
+	 * now check again if everything is in range:
+	 */
+	if (ppc4xx_pci_sync_clock_config(clock)) {
+		printf("ERROR: PCI clocking incorrect (async=%d "
+		       "sync=%ld)!\n", clock, get_PCI_freq());
+	}
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
+}
+#endif
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+/*
+ * On NAND-booting sequoia, we need to patch the chips select numbers
+ * in the dtb (CS0 - NAND, CS3 - NOR)
+ */
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+	int len;
+	int nodeoffset;
+	struct fdt_property *prop;
+	u32 *reg;
+	char path[32];
+
+	/* First do common fdt setup */
+	__ft_board_setup(blob, bd);
+
+	/* And now configure NOR chip select to 3 instead of 0 */
+	strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
+	nodeoffset = fdt_path_offset(blob, path);
+	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+	if (prop == NULL) {
+		printf("Unable to update NOR chip select for NAND booting\n");
+		return;
+	}
+	reg = (u32 *)&prop->data[0];
+	reg[0] = 3;
+	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+	if (rc) {
+		printf("Unable to update property NOR mappings, err=%s\n",
+		       fdt_strerror(rc));
+		return;
+	}
+
+	/* And now configure NAND chip select to 0 instead of 3 */
+	strcpy(path, "/plb/opb/ebc/ndfc@3,0");
+	nodeoffset = fdt_path_offset(blob, path);
+	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+	if (prop == NULL) {
+		printf("Unable to update NDFC chip select for NAND booting\n");
+		return;
+	}
+	reg = (u32 *)&prop->data[0];
+	reg[0] = 0;
+	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+	if (rc) {
+		printf("Unable to update property NDFC mappings, err=%s\n",
+		       fdt_strerror(rc));
+		return;
+	}
+}
+#endif /* CONFIG_NAND_U_BOOT */
diff --git a/u-boot/board/amcc/sequoia/u-boot-nand.lds b/u-boot/board/amcc/sequoia/u-boot-nand.lds
new file mode 100644
index 0000000..f3855c4
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/u-boot-nand.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/amcc/sequoia/init.o	(.text*)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/env_embedded.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/amcc/sequoia/u-boot-ram.lds b/u-boot/board/amcc/sequoia/u-boot-ram.lds
new file mode 100644
index 0000000..ba76a77
--- /dev/null
+++ b/u-boot/board/amcc/sequoia/u-boot-ram.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
+    board/amcc/sequoia/init.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/amcc/taihu/Makefile b/u-boot/board/amcc/taihu/Makefile
new file mode 100644
index 0000000..9b2e7e4
--- /dev/null
+++ b/u-boot/board/amcc/taihu/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o lcd.o update.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/taihu/flash.c b/u-boot/board/amcc/taihu/flash.c
new file mode 100644
index 0000000..e9fbbb1
--- /dev/null
+++ b/u-boot/board/amcc/taihu/flash.c
@@ -0,0 +1,1085 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char
+#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa)
+#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555)
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef FLASH_BASE1_PRELIM
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1=0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 << 20);
+	}
+
+	if (size_b0) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[0]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+#endif
+		/* Also protect sector containing initial power-up instruction */
+		/* (flash_protect() checks address range - other call ignored) */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+
+		flash_info[0].size = size_b0;
+	}
+#ifdef FLASH_BASE1_PRELIM
+	size_b1 =
+	    flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2;
+
+	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+		       size_b1, size_b1 << 20);
+	}
+
+	if (size_b1) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
+		flash_info[1].size = size_b1;
+	}
+#endif
+	return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000*2);
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000*2);
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
+
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMD016:
+		printf("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM033C:
+		printf("AM29LV033C (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMLV128U:
+		printf("AM29LV128U (128 Mbit * 2, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_STMW320DT:
+		printf ("M29W320DT (32 M, top sector)\n");
+		break;
+	case FLASH_S29GL128N:
+		printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef FLASH_BASE1_PRELIM
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	if ((ulong)addr == FLASH_BASE1_PRELIM) {
+		return flash_get_size_2(addr, info);
+	} else {
+		return flash_get_size_1(addr, info);
+	}
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return 0;	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return 0;	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+	else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000 * 2);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return info->size;
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return 0;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef FLASH_BASE1_PRELIM
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return 2;
+	}
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CONFIG_SYS_FLASH_CHAR_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+	addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+	addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+	udelay(1000);
+
+	value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return 0;		/* no or unknown flash */
+	}
+
+	value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2];	/* device ID */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;			/* => 2 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;			/* => 4 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;			/* => 0.5 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;			/* => 0.5 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;			/* => 1 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;			/* => 1 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;			/* => 2 MB */
+
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;			/* => 2 MB */
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
+		if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
+				&& (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
+			info->flash_id += FLASH_AMLV128U;
+			info->sector_count = 256;
+			info->size = 0x01000000;
+		} else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
+				&& (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
+			info->flash_id += FLASH_S29GL128N;
+			info->sector_count = 128;
+			info->size = 0x01000000;
+		}
+		else
+			info->flash_id = FLASH_UNKNOWN;
+		break;			/* => 2 MB */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return 0;		/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00020000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0;
+	return info->size;
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) { /* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return 2;
+	}
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+		addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+		addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+#endif /* FLASH_BASE1_PRELIM */
diff --git a/u-boot/board/amcc/taihu/lcd.c b/u-boot/board/amcc/taihu/lcd.c
new file mode 100644
index 0000000..15cfcb0
--- /dev/null
+++ b/u-boot/board/amcc/taihu/lcd.c
@@ -0,0 +1,253 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#define LCD_CMD_ADDR	0x50100002
+#define LCD_DATA_ADDR	0x50100003
+#define LCD_BLK_CTRL	CPLD_REG1_ADDR
+
+static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
+static int addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+	out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
+}
+
+static void lcd_putc(int val)
+{
+	int i = 100;
+	char addr;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	addr = in_8((u8 *) LCD_CMD_ADDR);
+	udelay(50);
+	if ((addr != 0) && (addr % 0x10 == 0)) {
+		addr_flag ^= 0x40;
+		out_8((u8 *) LCD_CMD_ADDR, addr_flag);
+	}
+
+	udelay(50);
+	out_8((u8 *) LCD_DATA_ADDR, val);
+	udelay(50);
+}
+
+static void lcd_puts(char *s)
+{
+	char *p = s;
+	int i = 100;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	while (*p)
+		lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+	int i = 100;
+	char *p = amcc_logo;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	out_8((u8 *) LCD_CMD_ADDR, 0x80);
+	while (*p)
+		lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+	puts("LCD: ");
+	out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
+	udelay(50);
+	out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
+	udelay(50);
+	out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
+	udelay(2000);
+	out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
+	udelay(50);
+	lcd_bl_ctrl(0x02);		/* set backlight on */
+	lcd_put_logo();
+	puts("ready\n");
+
+	return 0;
+}
+
+static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	out_8((u8 *) LCD_CMD_ADDR, 0x01);
+	udelay(2000);
+
+	return 0;
+}
+
+static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	lcd_puts(argv[1]);
+
+	return 0;
+}
+
+static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	lcd_putc((char)argv[1][0]);
+
+	return 0;
+}
+
+static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong count;
+	ulong dir;
+	char cur_addr;
+
+	if (argc < 3)
+		return cmd_usage(cmdtp);
+
+	count = simple_strtoul(argv[1], NULL, 16);
+	if (count > 31) {
+		printf("unable to shift > 0x20\n");
+		count = 0;
+	}
+
+	dir = simple_strtoul(argv[2], NULL, 16);
+	cur_addr = in_8((u8 *) LCD_CMD_ADDR);
+	udelay(50);
+
+	if (dir == 0x0) {
+		if (addr_flag == 0x80) {
+			if (count >= (cur_addr & 0xf)) {
+				out_8((u8 *) LCD_CMD_ADDR, 0x80);
+				udelay(50);
+				count = 0;
+			}
+		} else {
+			if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+				out_8((u8 *) LCD_CMD_ADDR, 0x80);
+				addr_flag = 0x80;
+				udelay(50);
+				count = 0x0;
+			} else if (count >= ( cur_addr & 0xf)) {
+				count -= cur_addr & 0xf ;
+				out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
+				addr_flag = 0x80;
+				udelay(50);
+			}
+		}
+	} else {
+		if (addr_flag == 0x80) {
+			if (count >= (0x1f - (cur_addr & 0xf))) {
+				count = 0x0;
+				addr_flag = 0xc0;
+				out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
+				udelay(50);
+			} else if ((count + (cur_addr & 0xf ))>=  0x0f) {
+				count = count + (cur_addr & 0xf) - 0x0f;
+				addr_flag = 0xc0;
+				out_8((u8 *) LCD_CMD_ADDR, 0xc0);
+				udelay(50);
+			}
+		} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
+			count = 0x0;
+			out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
+			udelay(50);
+		}
+	}
+	while (count--) {
+		if (dir == 0)
+			out_8((u8 *) LCD_CMD_ADDR, 0x10);
+		else
+			out_8((u8 *) LCD_CMD_ADDR, 0x14);
+		udelay(50);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lcd_cls, 1, 1, do_lcd_clear,
+	"lcd clear display",
+	""
+);
+
+U_BOOT_CMD(
+	lcd_puts, 2, 1, do_lcd_puts,
+	"display string on lcd",
+	"<string> - <string> to be displayed"
+);
+
+U_BOOT_CMD(
+	lcd_putc, 2, 1, do_lcd_putc,
+	"display char on lcd",
+	"<char> - <char> to be displayed"
+);
+
+U_BOOT_CMD(
+	lcd_cur, 3, 1, do_lcd_cur,
+	"shift cursor on lcd",
+	"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
+	" <count> - 0..31\n"
+	" <dir>   - 0=backward 1=forward"
+);
diff --git a/u-boot/board/amcc/taihu/taihu.c b/u-boot/board/amcc/taihu/taihu.c
new file mode 100644
index 0000000..87c9403
--- /dev/null
+++ b/u-boot/board/amcc/taihu/taihu.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <netdev.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern int lcd_init(void);
+
+/*
+ * board_early_init_f
+ */
+int board_early_init_f(void)
+{
+	lcd_init();
+
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);	/* memory bank 3 (CPLD_LCM) initialization */
+	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
+
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 * and enable the internal PCI arbiter
+	 */
+	mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
+{
+	char stat;
+	int i;
+
+	stat = in_8((u8 *) CPLD_REG0_ADDR);
+	printf("SW2 status: ");
+	for (i=0; i<4; i++) /* 4-position */
+		printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
+	printf("\n");
+	return 0;
+}
+
+U_BOOT_CMD (
+	sw2_stat, 1, 1, do_sw_stat,
+	"show status of switch 2",
+	""
+);
+
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
+{
+	int led_no;
+
+	if (argc != 3)
+		return cmd_usage(cmd_tp);
+
+	led_no = simple_strtoul(argv[1], NULL, 16);
+	if (led_no != 1 && led_no != 2)
+		return cmd_usage(cmd_tp);
+
+	if (strcmp(argv[2],"off") == 0x0) {
+		if (led_no == 1)
+			gpio_write_bit(30, 1);
+		else
+			gpio_write_bit(31, 1);
+	} else if (strcmp(argv[2],"on") == 0x0) {
+		if (led_no == 1)
+			gpio_write_bit(30, 0);
+		else
+			gpio_write_bit(31, 0);
+	} else {
+		return cmd_usage(cmd_tp);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	led_ctl, 3, 1, do_led_ctl,
+	"make led 1 or 2  on or off",
+	"<led_no> <on/off>	-  make led <led_no> on/off,\n"
+	"\tled_no is 1 or 2"
+);
+
+#define SPI_CS_GPIO0	0
+#define SPI_SCLK_GPIO14	14
+#define SPI_DIN_GPIO15	15
+#define SPI_DOUT_GPIO16	16
+
+void spi_scl(int bit)
+{
+	gpio_write_bit(SPI_SCLK_GPIO14, bit);
+}
+
+void spi_sda(int bit)
+{
+	gpio_write_bit(SPI_DOUT_GPIO16, bit);
+}
+
+unsigned char spi_read(void)
+{
+	return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio_write_bit(SPI_CS_GPIO0, 1);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio_write_bit(SPI_CS_GPIO0, 0);
+}
+
+#ifdef CONFIG_PCI
+static unsigned char int_lines[32] = {
+	29, 30, 27, 28, 29, 30, 25, 27,
+	29, 30, 27, 28, 29, 30, 27, 28,
+	29, 30, 27, 28, 29, 30, 27, 28,
+	29, 30, 27, 28, 29, 30, 27, 28};
+
+static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+	hose->fixup_irq = taihu_pci_fixup_irq;
+	return 1;
+}
+#endif /* CONFIG_PCI */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/amcc/taihu/update.c b/u-boot/board/amcc/taihu/update.c
new file mode 100644
index 0000000..b87eac4
--- /dev/null
+++ b/u-boot/board/amcc/taihu/update.c
@@ -0,0 +1,132 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#define PCI_M66EN 0x10
+
+static uchar buf_33[] =
+{
+	0xb5,	/* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+	0x80,	/* 0x01~0x03:ptm1ms =0x80000001 */
+	0x00,
+	0x00,
+	0x00,	/* 0x04~0x06:ptm1la = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x07~0x09:ptm2ma = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x0a~0x0c:ptm2la = 0x00000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x0d~0x0e:vendor id 0x1014*/
+	0x14,
+	0x00,	/* 0x0f~0x10:device id 0x0000*/
+	0x00,
+	0x00,	/* 0x11:revision 0x00 */
+	0x00,	/* 0x12~0x14:class 0x000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x15~0x16:subsystem vendor id */
+	0xe8,
+	0x00,	/* 0x17~0x18:subsystem device id */
+	0x00,
+	0x61,	/* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+	0x68,	/* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+	0x2d,	/* 0x1b: fwdvb=0b101,fwdva=0b101 */
+	0x82,	/* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+	0xbe,	/* 0x1d: tun[24-31]=0xbe */
+	0x00,
+	0x00
+};
+
+static uchar buf_66[] =
+{
+	0xb5,	/* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+	0x80,	/* 0x01~0x03:ptm1ms =0x80000001 */
+	0x00,
+	0x00,
+	0x00,	/* 0x04~0x06:ptm1la = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x07~0x09:ptm2ma = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x0a~0x0c:ptm2la = 0x00000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x0d~0x0e:vendor id 0x1014*/
+	0x14,
+	0x00,	/* 0x0f~0x10:device id 0x0000*/
+	0x00,
+	0x00,	/* 0x11:revision 0x00 */
+	0x00,	/* 0x12~0x14:class 0x000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x15~0x16:subsystem vendor id */
+	0xe8,
+	0x00,	/* 0x17~0x18:subsystem device id */
+	0x00,
+	0x61,	/* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+	0x68,	/* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+	0x2d,	/* 0x1b: fwdvb=0b101,fwdva=0b101 */
+	0x82,	/* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+	0xbe,	/* 0x1d: tun[24-31]=0xbe */
+	0x00,
+	0x00
+};
+
+static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong len = 0x20;
+	uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR;
+	uchar *pbuf;
+	uchar base;
+	int i;
+
+	if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
+		pbuf = buf_33;
+		base = 0x00;
+	} else {
+		pbuf = buf_66;
+		base = 0x40;
+	}
+
+	for (i = 0; i< len; i++, base++) {
+		if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
+			printf("i2c_write fail\n");
+			return 1;
+		}
+		udelay(11000);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	update_boot_eeprom, 1, 1, update_boot_eeprom,
+	"update boot eeprom content",
+	""
+);
diff --git a/u-boot/board/amcc/taishan/Makefile b/u-boot/board/amcc/taishan/Makefile
new file mode 100644
index 0000000..099cf9d
--- /dev/null
+++ b/u-boot/board/amcc/taishan/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o lcd.o update.o showinfo.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/taishan/config.mk b/u-boot/board/amcc/taishan/config.mk
new file mode 100644
index 0000000..3d18a38
--- /dev/null
+++ b/u-boot/board/amcc/taishan/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440GX Reference Platform (Taishan) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/taishan/init.S b/u-boot/board/amcc/taishan/init.S
new file mode 100644
index 0000000..6d47851
--- /dev/null
+++ b/u-boot/board/amcc/taishan/init.S
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+	tlbtab_end
diff --git a/u-boot/board/amcc/taishan/lcd.c b/u-boot/board/amcc/taishan/lcd.c
new file mode 100644
index 0000000..7f7730a
--- /dev/null
+++ b/u-boot/board/amcc/taishan/lcd.c
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_TAISHAN
+
+#define LCD_DELAY_NORMAL_US	100
+#define LCD_DELAY_NORMAL_MS	2
+#define LCD_CMD_ADDR		((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE))
+#define LCD_DATA_ADDR		((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1))
+#define LCD_BLK_CTRL		((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2))
+
+#define mdelay(t)	({unsigned long msec=(t); while (msec--) { udelay(1000);}})
+
+static int g_lcd_init_b = 0;
+static char *amcc_logo = "  AMCC TAISHAN  440GX EvalBoard";
+static char addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+	char cpld_val;
+
+	cpld_val = *LCD_BLK_CTRL;
+	*LCD_BLK_CTRL = val | cpld_val;
+}
+
+static void lcd_putc(char val)
+{
+	int i = 100;
+	char addr;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	addr = *LCD_CMD_ADDR;
+	udelay(LCD_DELAY_NORMAL_US);
+	if ((addr != 0) && (addr % 0x10 == 0)) {
+		addr_flag ^= 0x40;
+		*LCD_CMD_ADDR = addr_flag;
+	}
+
+	udelay(LCD_DELAY_NORMAL_US);
+	*LCD_DATA_ADDR = val;
+	udelay(LCD_DELAY_NORMAL_US);
+}
+
+static void lcd_puts(char *s)
+{
+	char *p = s;
+	int i = 100;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	while (*p)
+		lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+	int i = 100;
+	char *p = amcc_logo;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	*LCD_CMD_ADDR = 0x80;
+	while (*p)
+		lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+	if (g_lcd_init_b == 0) {
+		puts("LCD: ");
+		mdelay(100);	/* Waiting for the LCD initialize */
+
+		*LCD_CMD_ADDR = 0x38;	/*set function:8-bit,2-line,5x7 font type */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		*LCD_CMD_ADDR = 0x0f;	/*set display on,cursor on,blink on */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		*LCD_CMD_ADDR = 0x01;	/*display clear */
+		mdelay(LCD_DELAY_NORMAL_MS);
+
+		*LCD_CMD_ADDR = 0x06;	/*set entry */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		lcd_bl_ctrl(0x02);
+		lcd_put_logo();
+
+		puts("  ready\n");
+		g_lcd_init_b = 1;
+	}
+
+	return 0;
+}
+
+static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	lcd_init();
+	return 0;
+}
+
+static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	*LCD_CMD_ADDR = 0x01;
+	mdelay(LCD_DELAY_NORMAL_MS);
+	return 0;
+}
+static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	lcd_puts(argv[1]);
+	return 0;
+}
+static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	lcd_putc((char)argv[1][0]);
+	return 0;
+}
+static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong count;
+	ulong dir;
+	char cur_addr;
+
+	if (argc < 3)
+		return cmd_usage(cmdtp);
+
+	count = simple_strtoul(argv[1], NULL, 16);
+	if (count > 31) {
+		printf("unable to shift > 0x20\n");
+		count = 0;
+	}
+
+	dir = simple_strtoul(argv[2], NULL, 16);
+	cur_addr = *LCD_CMD_ADDR;
+	udelay(LCD_DELAY_NORMAL_US);
+	if (dir == 0x0) {
+		if (addr_flag == 0x80) {
+			if (count >= (cur_addr & 0xf)) {
+				*LCD_CMD_ADDR = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+				count = 0;
+			}
+		} else {
+			if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+				*LCD_CMD_ADDR = 0x80;
+				addr_flag = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+				count = 0x0;
+			} else if (count >= (cur_addr & 0xf)) {
+				count -= cur_addr & 0xf;
+				*LCD_CMD_ADDR = 0x80 | 0xf;
+				addr_flag = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+			}
+		}
+	} else {
+		if (addr_flag == 0x80) {
+			if (count >= (0x1f - (cur_addr & 0xf))) {
+				count = 0x0;
+				addr_flag = 0xc0;
+				*LCD_CMD_ADDR = 0xc0 | 0xf;
+				udelay(LCD_DELAY_NORMAL_US);
+			} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+				count = count + (cur_addr & 0xf) - 0x0f;
+				addr_flag = 0xc0;
+				*LCD_CMD_ADDR = 0xc0;
+				udelay(LCD_DELAY_NORMAL_US);
+			}
+		} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+			count = 0x0;
+			*LCD_CMD_ADDR = 0xc0 | 0xf;
+			udelay(LCD_DELAY_NORMAL_US);
+		}
+	}
+
+	while (count--) {
+		if (dir == 0) {
+			*LCD_CMD_ADDR = 0x10;
+		} else {
+			*LCD_CMD_ADDR = 0x14;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", "");
+U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", "");
+U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
+	   "display string on lcd",
+	   "<string> - <string> to be displayed");
+U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
+	   "display char on lcd",
+	   "<char> - <char> to be displayed");
+U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
+	   "shift cursor on lcd",
+	   "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
+	   " <count> - 0~31\n" " <dir> - 0,backward; 1, forward");
+
+#if 0 /* test-only */
+void set_phy_loopback_mode(void)
+{
+	char devemac2[32];
+	char devemac3[32];
+
+	sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+	sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+#if 0
+	unsigned short reg_short;
+
+	miiphy_read(devemac2, 0x1, 1, &reg_short);
+	if (reg_short & 0x04) {
+		/*
+		 * printf("EMAC2 link up,do nothing\n");
+		 */
+	} else {
+		udelay(1000);
+		miiphy_write(devemac2, 0x1, 0, 0x6000);
+		udelay(1000);
+		miiphy_read(devemac2, 0x1, 0, &reg_short);
+		if (reg_short != 0x6000) {
+			printf
+			    ("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
+			     reg_short);
+		}
+	}
+
+	miiphy_read(devemac3, 0x3, 1, &reg_short);
+	if (reg_short & 0x04) {
+		/*
+		 * printf("EMAC3 link up,do nothing\n");
+		 */
+	} else {
+		udelay(1000);
+		miiphy_write(devemac3, 0x3, 0, 0x6000);
+		udelay(1000);
+		miiphy_read(devemac3, 0x3, 0, &reg_short);
+		if (reg_short != 0x6000) {
+			printf
+			    ("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
+			     reg_short);
+		}
+	}
+#else
+	/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
+	udelay(1000);
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
+	udelay(1000);
+#endif	/* 0 */
+}
+
+void set_phy_normal_mode(void)
+{
+	char devemac2[32];
+	char devemac3[32];
+	unsigned short reg_short;
+
+	sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+	sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+	/* Set phy of EMAC2 */
+	miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, &reg_short);
+	reg_short &= ~(0x7);
+	reg_short |= 0x6;	/* RGMII DLL Delay */
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
+
+	miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, &reg_short);
+	reg_short &= ~(0x40);
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
+
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
+
+	/* Set phy of EMAC3 */
+	miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, &reg_short);
+	reg_short &= ~(0x7);
+	reg_short |= 0x6;	/* RGMII DLL Delay */
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
+
+	miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, &reg_short);
+	reg_short &= ~(0x40);
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
+
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
+}
+#endif	/* 0 - test only */
+
+static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	volatile unsigned int *GpioOr =
+		(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
+	*GpioOr |= 0x00300000;
+	return 0;
+}
+
+static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	volatile unsigned int *GpioOr =
+		(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
+	*GpioOr &= ~0x00300000;
+	return 0;
+}
+
+U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
+	   "led test light on", "");
+
+U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
+	   "led test light off", "");
+#endif
diff --git a/u-boot/board/amcc/taishan/showinfo.c b/u-boot/board/amcc/taishan/showinfo.c
new file mode 100644
index 0000000..587fe74
--- /dev/null
+++ b/u-boot/board/amcc/taishan/showinfo.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+void show_reset_reg(void)
+{
+	unsigned long reg;
+
+	/* read clock regsiter */
+	printf("===== Display reset and initialize register Start =========\n");
+	mfcpr(CPR0_PLLC,reg);
+	printf("cpr_pllc   = %#010lx\n",reg);
+
+	mfcpr(CPR0_PLLD,reg);
+	printf("cpr_plld   = %#010lx\n",reg);
+
+	mfcpr(CPR0_PRIMAD0,reg);
+	printf("cpr_primad = %#010lx\n",reg);
+
+	mfcpr(CPR0_PRIMBD0,reg);
+	printf("cpr_primbd = %#010lx\n",reg);
+
+	mfcpr(CPR0_OPBD0,reg);
+	printf("cpr_opbd   = %#010lx\n",reg);
+
+	mfcpr(CPR0_PERD,reg);
+	printf("cpr_perd   = %#010lx\n",reg);
+
+	mfcpr(CPR0_MALD,reg);
+	printf("cpr_mald   = %#010lx\n",reg);
+
+	/* read sdr register */
+	mfsdr(SDR0_EBC,reg);
+	printf("SDR0_EBC    = %#010lx\n",reg);
+
+	mfsdr(SDR0_CP440,reg);
+	printf("SDR0_CP440  = %#010lx\n",reg);
+
+	mfsdr(SDR0_XCR,reg);
+	printf("SDR0_XCR    = %#010lx\n",reg);
+
+	mfsdr(SDR0_XPLLC,reg);
+	printf("SDR0_XPLLC  = %#010lx\n",reg);
+
+	mfsdr(SDR0_XPLLD,reg);
+	printf("SDR0_XPLLD  = %#010lx\n",reg);
+
+	mfsdr(SDR0_PFC0,reg);
+	printf("SDR0_PFC0   = %#010lx\n",reg);
+
+	mfsdr(SDR0_PFC1,reg);
+	printf("SDR0_PFC1   = %#010lx\n",reg);
+
+	mfsdr(SDR0_CUST0,reg);
+	printf("SDR0_CUST0  = %#010lx\n",reg);
+
+	mfsdr(SDR0_CUST1,reg);
+	printf("SDR0_CUST1  = %#010lx\n",reg);
+
+	mfsdr(SDR0_UART0,reg);
+	printf("SDR0_UART0  = %#010lx\n",reg);
+
+	mfsdr(SDR0_UART1,reg);
+	printf("SDR0_UART1  = %#010lx\n",reg);
+
+	printf("===== Display reset and initialize register End   =========\n");
+}
+
+void show_xbridge_info(void)
+{
+	unsigned long reg;
+
+	printf("PCI-X chip control registers\n");
+	mfsdr(SDR0_XCR, reg);
+	printf("SDR0_XCR    = %#010lx\n", reg);
+
+	mfsdr(SDR0_XPLLC, reg);
+	printf("SDR0_XPLLC  = %#010lx\n", reg);
+
+	mfsdr(SDR0_XPLLD, reg);
+	printf("SDR0_XPLLD  = %#010lx\n", reg);
+
+	printf("PCI-X Bridge Configure registers\n");
+	printf("PCIL0_VENDID            = %#06x\n", in16r(PCIL0_VENDID));
+	printf("PCIL0_DEVID             = %#06x\n", in16r(PCIL0_DEVID));
+	printf("PCIL0_CMD               = %#06x\n", in16r(PCIL0_CMD));
+	printf("PCIL0_STATUS            = %#06x\n", in16r(PCIL0_STATUS));
+	printf("PCIL0_REVID             = %#04x\n", in8(PCIL0_REVID));
+	printf("PCIL0_CACHELS           = %#04x\n", in8(PCIL0_CACHELS));
+	printf("PCIL0_LATTIM            = %#04x\n", in8(PCIL0_LATTIM));
+	printf("PCIL0_HDTYPE            = %#04x\n", in8(PCIL0_HDTYPE));
+	printf("PCIL0_BIST              = %#04x\n", in8(PCIL0_BIST));
+
+	printf("PCIL0_BAR0              = %#010lx\n", in32r(PCIL0_BAR0));
+	printf("PCIL0_BAR1              = %#010lx\n", in32r(PCIL0_BAR1));
+	printf("PCIL0_BAR2              = %#010lx\n", in32r(PCIL0_BAR2));
+	printf("PCIL0_BAR3              = %#010lx\n", in32r(PCIL0_BAR3));
+	printf("PCIL0_BAR4              = %#010lx\n", in32r(PCIL0_BAR4));
+	printf("PCIL0_BAR5              = %#010lx\n", in32r(PCIL0_BAR5));
+
+	printf("PCIL0_CISPTR            = %#010lx\n", in32r(PCIL0_CISPTR));
+	printf("PCIL0_SBSSYSVID         = %#010x\n", in16r(PCIL0_SBSYSVID));
+	printf("PCIL0_SBSSYSID          = %#010x\n", in16r(PCIL0_SBSYSID));
+	printf("PCIL0_EROMBA            = %#010lx\n", in32r(PCIL0_EROMBA));
+	printf("PCIL0_CAP               = %#04x\n", in8(PCIL0_CAP));
+	printf("PCIL0_INTLN             = %#04x\n", in8(PCIL0_INTLN));
+	printf("PCIL0_INTPN             = %#04x\n", in8(PCIL0_INTPN));
+	printf("PCIL0_MINGNT            = %#04x\n", in8(PCIL0_MINGNT));
+	printf("PCIL0_MAXLTNCY          = %#04x\n", in8(PCIL0_MAXLTNCY));
+
+	printf("PCIL0_BRDGOPT1          = %#010lx\n", in32r(PCIL0_BRDGOPT1));
+	printf("PCIL0_BRDGOPT2          = %#010lx\n", in32r(PCIL0_BRDGOPT2));
+
+	printf("PCIL0_POM0LAL           = %#010lx\n", in32r(PCIL0_POM0LAL));
+	printf("PCIL0_POM0LAH           = %#010lx\n", in32r(PCIL0_POM0LAH));
+	printf("PCIL0_POM0SA            = %#010lx\n", in32r(PCIL0_POM0SA));
+	printf("PCIL0_POM0PCILAL        = %#010lx\n", in32r(PCIL0_POM0PCIAL));
+	printf("PCIL0_POM0PCILAH        = %#010lx\n", in32r(PCIL0_POM0PCIAH));
+	printf("PCIL0_POM1LAL           = %#010lx\n", in32r(PCIL0_POM1LAL));
+	printf("PCIL0_POM1LAH           = %#010lx\n", in32r(PCIL0_POM1LAH));
+	printf("PCIL0_POM1SA            = %#010lx\n", in32r(PCIL0_POM1SA));
+	printf("PCIL0_POM1PCILAL        = %#010lx\n", in32r(PCIL0_POM1PCIAL));
+	printf("PCIL0_POM1PCILAH        = %#010lx\n", in32r(PCIL0_POM1PCIAH));
+	printf("PCIL0_POM2SA            = %#010lx\n", in32r(PCIL0_POM2SA));
+
+	printf("PCIL0_PIM0SA            = %#010lx\n", in32r(PCIL0_PIM0SA));
+	printf("PCIL0_PIM0LAL           = %#010lx\n", in32r(PCIL0_PIM0LAL));
+	printf("PCIL0_PIM0LAH           = %#010lx\n", in32r(PCIL0_PIM0LAH));
+	printf("PCIL0_PIM1SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+	printf("PCIL0_PIM1LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+	printf("PCIL0_PIM1LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+	printf("PCIL0_PIM2SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+	printf("PCIL0_PIM2LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+	printf("PCIL0_PIM2LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+
+	printf("PCIL0_XSTS              = %#010lx\n", in32r(PCIL0_STS));
+}
+
+int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	show_xbridge_info();
+	return 0;
+}
+
+U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
+	   "Show PCIX bridge info", "");
+
+#define TAISHAN_PCI_DEV_ID0 0x800
+#define TAISHAN_PCI_DEV_ID1 0x1000
+
+void show_pcix_device_info(void)
+{
+	int ii;
+	int dev;
+	u8 capp;
+	u8 xcapid;
+	u16 status;
+	u16 xcommand;
+	u32 xstatus;
+
+	for (ii = 0; ii < 2; ii++) {
+		if (ii == 0)
+			dev = TAISHAN_PCI_DEV_ID0;
+		else
+			dev = TAISHAN_PCI_DEV_ID1;
+
+		pci_read_config_word(dev, PCI_STATUS, &status);
+		if (status & PCI_STATUS_CAP_LIST) {
+			pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
+
+			pci_read_config_byte(dev, (int)(capp), &xcapid);
+			if (xcapid == 0x07) {
+				pci_read_config_word(dev, (int)(capp + 2),
+						     &xcommand);
+				pci_read_config_dword(dev, (int)(capp + 4),
+						      &xstatus);
+				printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
+				       (ii + 1), xcommand, xstatus);
+			} else {
+				printf("BUS0 dev%d PCI-X CAP ID error,"
+				       "CAP=%#04x,XCAPID=%#04x\n",
+				       (ii + 1), capp, xcapid);
+			}
+		} else {
+			printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
+			       ii + 1);
+		}
+	}
+
+}
+
+int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
+			     char * const argv[])
+{
+	show_pcix_device_info();
+	return 0;
+}
+
+U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
+	   "Show PCIX Device info", "");
+
+extern void show_reset_reg(void);
+
+int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	show_reset_reg();
+	return 0;
+}
+
+U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
+	   "Show Reset REG info", "");
diff --git a/u-boot/board/amcc/taishan/taishan.c b/u-boot/board/amcc/taishan/taishan.c
new file mode 100644
index 0000000..2957a77
--- /dev/null
+++ b/u-boot/board/amcc/taishan/taishan.c
@@ -0,0 +1,216 @@
+/*
+ *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <asm/ppc4xx-emac.h>
+#include <netdev.h>
+
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
+void show_reset_reg(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int lcd_init(void);
+
+int board_early_init_f (void)
+{
+	unsigned long reg;
+	volatile unsigned int *GpioOdr;
+	volatile unsigned int *GpioTcr;
+	volatile unsigned int *GpioOr;
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*-------------------------------------------------------------------------+
+	  | 64MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
+	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | LCM. Initialize bank 2 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | TMP. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | Connector 4~7. Initialize bank 3~ 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(PB4AP,0);
+	mtebc(PB4CR,0);
+	mtebc(PB5AP,0);
+	mtebc(PB5CR,0);
+	mtebc(PB6AP,0);
+	mtebc(PB6CR,0);
+	mtebc(PB7AP,0);
+	mtebc(PB7CR,0);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all */
+	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000);	/* */
+	mtdcr (UIC0TR, 0x00000000);	/* */
+	mtdcr (UIC0VR, 0x00000001);	/* */
+
+	/* Enable two GPIO 10~11 and TraceA signal */
+	mfsdr(SDR0_PFC0,reg);
+	reg |= 0x00300000;
+	mtsdr(SDR0_PFC0,reg);
+
+	mfsdr(SDR0_PFC1,reg);
+	reg |= 0x00100000;
+	mtsdr(SDR0_PFC1,reg);
+
+	/* Set GPIO 10 and 11 as output */
+	GpioOdr	= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
+	GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
+	GpioOr  = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
+
+	*GpioOdr &= ~(0x00300000);
+	*GpioTcr |= 0x00300000;
+	*GpioOr  |= 0x00300000;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	lcd_init();
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
+	show_reset_reg();
+#endif
+
+	return (0);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/amcc/taishan/update.c b/u-boot/board/amcc/taishan/update.c
new file mode 100644
index 0000000..3f063a0
--- /dev/null
+++ b/u-boot/board/amcc/taishan/update.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#if defined(CONFIG_TAISHAN)
+
+const uchar bootstrap_buf[16] = {
+	0x86,
+	0x78,
+	0xc1,
+	0xa6,
+	0x09,
+	0x67,
+	0x04,
+	0x63,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00
+};
+
+static int update_boot_eeprom(void)
+{
+	ulong len = 0x10;
+	uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR;
+	uchar *pbuf = (uchar *)bootstrap_buf;
+	int ii, jj;
+
+	for (ii = 0; ii < len; ii++) {
+		if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
+			printf("i2c_write failed\n");
+			return -1;
+		}
+
+		/* wait 10ms */
+		for (jj = 0; jj < 10; jj++)
+			udelay(1000);
+	}
+	return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	return update_boot_eeprom();
+}
+
+U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+	   "update bootstrap eeprom content", "");
+#endif
diff --git a/u-boot/board/amcc/walnut/Makefile b/u-boot/board/amcc/walnut/Makefile
new file mode 100644
index 0000000..9f63df1
--- /dev/null
+++ b/u-boot/board/amcc/walnut/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/walnut/flash.c b/u-boot/board/amcc/walnut/flash.c
new file mode 100644
index 0000000..f72e278
--- /dev/null
+++ b/u-boot/board/amcc/walnut/flash.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[0]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+#endif
+
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	} else {
+		/* 2 banks */
+		size_b1 =
+		    flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+				   &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr(EBC0_CFGADDR, PB0CR);
+			pbcr = mfdcr(EBC0_CFGDATA);
+			mtdcr(EBC0_CFGADDR, PB0CR);
+			base_b1 = -size_b1;
+			pbcr =
+			    (pbcr & 0x0001ffff) | base_b1 |
+			    (((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr(EBC0_CFGDATA, pbcr);
+			/*          printf("PB1CR = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr(EBC0_CFGADDR, PB1CR);
+			pbcr = mfdcr(EBC0_CFGDATA);
+			mtdcr(EBC0_CFGADDR, PB1CR);
+			base_b0 = base_b1 - size_b0;
+			pbcr =
+			    (pbcr & 0x0001ffff) | base_b0 |
+			    (((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr(EBC0_CFGDATA, pbcr);
+			/*            printf("PB0CR = %x\n", pbcr); */
+		}
+
+		size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+		flash_get_offsets(base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    base_b0 + size_b0 - monitor_flash_len,
+				    base_b0 + size_b0 - 1, &flash_info[0]);
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+			    flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+			flash_get_offsets(base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void)flash_protect(FLAG_PROTECT_SET,
+					    base_b1 + size_b1 -
+					    monitor_flash_len,
+					    base_b1 + size_b1 - 1,
+					    &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+					    base_b0 + size_b0 -
+					    monitor_flash_len,
+					    base_b0 + size_b0 - 1,
+					    &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
diff --git a/u-boot/board/amcc/walnut/walnut.c b/u-boot/board/amcc/walnut/walnut.c
new file mode 100644
index 0000000..4f29932
--- /dev/null
+++ b/u-boot/board/amcc/walnut/walnut.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+	/*-------------------------------------------------------------------------+
+	  | Interrupt controller setup for the Walnut/Sycamore board.
+	  | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+	  |       IRQ 16    405GP internally generated; active low; level sensitive
+	  |       IRQ 17-24 RESERVED
+	  |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+	  |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+	  |       IRQ 27 (EXT IRQ 2) Not Used
+	  |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+	  |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	  |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+	  |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+	  | Note for Walnut board:
+	  |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+	  |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+	  |       interrupt. The FPGA must be read to determine which device
+	  |       caused the interrupt. The default setting of the FPGA clears
+	  |
+	  +-------------------------------------------------------------------------*/
+
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/* set UART1 control to select CTS/RTS */
+#define FPGA_BRDC       0xF0300004
+	*(volatile char *)(FPGA_BRDC) |= 0x1;
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	uint pvr = get_pvr();
+
+	if (pvr == PVR_405GPR_RB) {
+		puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
+	} else {
+		puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
+	}
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/*
+ * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * the necessary info for SDRAM controller configuration
+ */
+phys_size_t initdram(int board_type)
+{
+	return spd_sdram();
+}
diff --git a/u-boot/board/amcc/yosemite/Makefile b/u-boot/board/amcc/yosemite/Makefile
new file mode 100644
index 0000000..5b0ffc2
--- /dev/null
+++ b/u-boot/board/amcc/yosemite/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/yosemite/config.mk b/u-boot/board/amcc/yosemite/config.mk
new file mode 100644
index 0000000..9eac8b9
--- /dev/null
+++ b/u-boot/board/amcc/yosemite/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/yosemite/init.S b/u-boot/board/amcc/yosemite/init.S
new file mode 100644
index 0000000..d23cdc7
--- /dev/null
+++ b/u-boot/board/amcc/yosemite/init.S
@@ -0,0 +1,66 @@
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
+
+    /* PCI */
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
+
+    /* USB 2.0 Device */
+    tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
+
+    tlbtab_end
diff --git a/u-boot/board/amcc/yosemite/yosemite.c b/u-boot/board/amcc/yosemite/yosemite.c
new file mode 100644
index 0000000..aaeab6f
--- /dev/null
+++ b/u-boot/board/amcc/yosemite/yosemite.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static inline u32 get_async_pci_freq(void)
+{
+	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+		CONFIG_SYS_BCSR5_PCI66EN)
+		return 66666666;
+	else
+		return 33333333;
+}
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	reg = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	/*CPLD cs */
+	/*setup Address lines for flash size 64Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
+
+	/*setup emac */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+	/*UART1 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+	/* external interrupts IRQ0...3 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+#ifdef CONFIG_440EP
+	/*setup USB 2.0 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+#endif
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
+	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
+
+	/* Check and reconfigure the PCI sync clock if necessary */
+	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
+	/*clear tmrclk divisor */
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
+
+	/*enable ethernet */
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
+
+#ifdef CONFIG_440EP
+	/*enable usb 1.1 fs device and remove usb 2.0 reset */
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
+#endif
+
+	/*get rid of flash write protect */
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	uint pbcr;
+	int size_val = 0;
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u8 rev;
+	u32 clock = get_async_pci_freq();
+
+#ifdef CONFIG_440EP
+	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+#else
+	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+#endif
+
+	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	/*
+	 * Reconfiguration of the PCI sync clock is already done,
+	 * now check again if everything is in range:
+	 */
+	if (ppc4xx_pci_sync_clock_config(clock)) {
+		printf("ERROR: PCI clocking incorrect (async=%d "
+		       "sync=%ld)!\n", clock, get_PCI_freq());
+	}
+
+	return (0);
+}
+
+/*************************************************************************
+ *  initdram -- doesn't use serial presence detect.
+ *
+ *  Assumes:    256 MB, ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+	int i;
+	int j, k;
+	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
+	int first_good = -1, last_bad = 0x1ff;
+
+	unsigned long test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	/* go through all possible SDRAM0_TR1[RDCT] values */
+	for (i=0; i<=0x1ff; i++) {
+		/* set the current value for TR1 */
+		mtsdram(SDRAM0_TR1, (0x80800800 | i));
+
+		/* write values */
+		for (j=0; j<NUM_TRIES; j++) {
+			ram_pointer[j] = test[j];
+
+			/* clear any cache at ram location */
+			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+		}
+
+		/* read values back */
+		for (j=0; j<NUM_TRIES; j++) {
+			for (k=0; k<NUM_READS; k++) {
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+				if (ram_pointer[j] != test[j])
+					break;
+			}
+
+			/* read error */
+			if (k != NUM_READS) {
+				break;
+			}
+		}
+
+		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
+		if (j == NUM_TRIES) {
+			if (first_good == -1)
+				first_good = i;		/* found beginning of window */
+		} else { /* bad read */
+			/* if we have not had a good read then don't care */
+			if(first_good != -1) {
+				/* first failure after a good read */
+				last_bad = i-1;
+				break;
+			}
+		}
+	}
+
+	/* return the current value for TR1 */
+	*tr1_value = (first_good + last_bad) / 2;
+}
+
+phys_size_t initdram(int board)
+{
+	register uint reg;
+	int tr1_bank1, tr1_bank2;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram(SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(SDRAM0_CLKTR, 0x40000000);	/* ?? */
+	mtsdram(SDRAM0_WDDCTR, 0x40000000);	/* ?? */
+
+	/*clear this first, if the DDR is enabled by a debugger
+	  then you can not make changes. */
+	mtsdram(SDRAM0_CFG0, 0x00000000);	/* Disable EEC */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(SDRAM0_B1CR, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
+
+	mtsdram(SDRAM0_TR0, 0x410a4012);	/* ?? */
+	mtsdram(SDRAM0_RTR, 0x04080000);	/* ?? */
+	mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	mtsdram(SDRAM0_CFG0, 0x30000000);	/* Disable EEC */
+	udelay(400);		/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram(SDRAM0_CFG0, 0x80000000);	/* Enable */
+
+	for (;;) {
+		mfsdram(SDRAM0_MCSTS, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	sdram_tr1_set(0x00000000, &tr1_bank1);
+	sdram_tr1_set(0x08000000, &tr1_bank2);
+	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
+
+	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
+}
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
+
+void board_reset(void)
+{
+	/* give reset to BCSR */
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
+}
diff --git a/u-boot/board/amcc/yucca/Makefile b/u-boot/board/amcc/yucca/Makefile
new file mode 100644
index 0000000..d9fb713
--- /dev/null
+++ b/u-boot/board/amcc/yucca/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o cmd_yucca.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amcc/yucca/cmd_yucca.c b/u-boot/board/amcc/yucca/cmd_yucca.c
new file mode 100644
index 0000000..e9cd333
--- /dev/null
+++ b/u-boot/board/amcc/yucca/cmd_yucca.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for evb440spe
+ */
+
+#include <common.h>
+#include <command.h>
+#include "yucca.h"
+#include <i2c.h>
+#include <asm/byteorder.h>
+
+extern void print_evb440spe_info(void);
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
+		int flag, int argc, char * const argv[]);
+
+/* ------------------------------------------------------------------------- */
+int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return setBootStrapClock (cmdtp, 1, flag, argc, argv);
+}
+
+/* ------------------------------------------------------------------------- */
+/* Modify memory.
+ *
+ * Syntax:
+ *	evb440spe wrclk prom0,prom1
+ */
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
+		int argc, char * const argv[])
+{
+	uchar	chip;
+	ulong	data;
+	int	nbytes;
+	extern char console_buffer[];
+
+	char sysClock[4];
+	char cpuClock[4];
+	char plbClock[4];
+	char pcixClock[4];
+
+	if (argc < 3)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[2], "prom0") == 0)
+		chip = IIC0_BOOTPROM_ADDR;
+	else
+		chip = IIC0_ALT_BOOTPROM_ADDR;
+
+	do {
+		printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if ((strcmp(console_buffer, "33") != 0) &
+				(strcmp(console_buffer, "66") != 0))
+			nbytes=0;
+
+		strcpy(sysClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	do {
+		if (strcmp(sysClock, "66") == 0) {
+			printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n");
+		} else {
+#ifdef	CONFIG_STRESS
+			printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n");
+#else
+			printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
+#endif
+		}
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if (strcmp(sysClock, "66") == 0) {
+			if ((strcmp(console_buffer, "400") != 0) &
+					(strcmp(console_buffer, "533") != 0)
+#ifdef	CONFIG_STRESS
+					& (strcmp(console_buffer, "667") != 0)
+#endif
+			   ) {
+				nbytes = 0;
+			}
+		} else {
+			if ((strcmp(console_buffer, "400") != 0) &
+					(strcmp(console_buffer, "500") != 0) &
+					(strcmp(console_buffer, "533") != 0)
+#ifdef	CONFIG_STRESS
+					& (strcmp(console_buffer, "667") != 0)
+#endif
+			   ) {
+				nbytes = 0;
+			}
+		}
+
+		strcpy(cpuClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	if (strcmp(cpuClock, "500") == 0){
+		strcpy(plbClock, "166");
+	} else if (strcmp(cpuClock, "533") == 0){
+		strcpy(plbClock, "133");
+	} else {
+		do {
+			if (strcmp(cpuClock, "400") == 0)
+				printf("enter plb clock frequency 100, 133 MHz or quit to abort\n");
+
+#ifdef	CONFIG_STRESS
+			if (strcmp(cpuClock, "667") == 0)
+				printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
+
+#endif
+			nbytes = readline (" ? ");
+
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+
+			if (strcmp(cpuClock, "400") == 0) {
+				if ((strcmp(console_buffer, "100") != 0) &
+						(strcmp(console_buffer, "133") != 0))
+					nbytes = 0;
+			}
+#ifdef	CONFIG_STRESS
+			if (strcmp(cpuClock, "667") == 0) {
+				if ((strcmp(console_buffer, "133") != 0) &
+						(strcmp(console_buffer, "166") != 0))
+					nbytes = 0;
+			}
+#endif
+			strcpy(plbClock, console_buffer);
+
+		} while (nbytes == 0);
+	}
+
+	do {
+		printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if ((strcmp(console_buffer, "33") != 0) &
+				(strcmp(console_buffer, "66") != 0) &
+				(strcmp(console_buffer, "100") != 0) &
+				(strcmp(console_buffer, "133") != 0)) {
+			nbytes = 0;
+		}
+		strcpy(pcixClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	printf("\nsys clk   = %s MHz\n", sysClock);
+	printf("cpu clk   = %s MHz\n", cpuClock);
+	printf("plb clk   = %s MHz\n", plbClock);
+	printf("Pci-X clk = %s MHz\n", pcixClock);
+
+	do {
+		printf("\npress [y] to write I2C bootstrap \n");
+		printf("or [n] to abort.  \n");
+		printf("Don't forget to set board switches \n");
+		printf("according to your choice before re-starting \n");
+		printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+
+		nbytes = readline (" ? ");
+		if (strcmp(console_buffer, "n") == 0)
+			return 0;
+
+	} while (nbytes == 0);
+
+	if (strcmp(sysClock, "33") == 0) {
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "100") == 0))
+			data = 0x8678c206;
+
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x8678c2c6;
+
+		if ((strcmp(cpuClock, "500") == 0))
+			data = 0x8778f2c6;
+
+		if ((strcmp(cpuClock, "533") == 0))
+			data = 0x87790252;
+
+#ifdef	CONFIG_STRESS
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x87794256;
+
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "166") == 0))
+			data = 0x87794206;
+
+#endif
+	}
+	if (strcmp(sysClock, "66") == 0) {
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "100") == 0))
+			data = 0x84706206;
+
+		if ((strcmp(cpuClock, "400") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x847062c6;
+
+		if ((strcmp(cpuClock, "533") == 0))
+			data = 0x85708206;
+
+#ifdef	CONFIG_STRESS
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "133") == 0))
+			data = 0x8570a256;
+
+		if ((strcmp(cpuClock, "667") == 0) &
+				(strcmp(plbClock, "166") == 0))
+			data = 0x8570a206;
+
+#endif
+	}
+
+#ifdef	DEBUG
+	printf(" pin strap0 to write in i2c  = %x\n", data);
+#endif	/* DEBUG */
+
+	if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
+		printf("Error writing strap0 in %s\n", argv[2]);
+
+	if (strcmp(pcixClock, "33") == 0)
+		data = 0x00000701;
+
+	if (strcmp(pcixClock, "66") == 0)
+		data = 0x00000601;
+
+	if (strcmp(pcixClock, "100") == 0)
+		data = 0x00000501;
+
+	if (strcmp(pcixClock, "133") == 0)
+		data = 0x00000401;
+
+	if (strcmp(plbClock, "166") == 0)
+		data = data | 0x05950000;
+	else
+		data = data | 0x05A50000;
+
+#ifdef	DEBUG
+	printf(" pin strap1 to write in i2c  = %x\n", data);
+#endif	/* DEBUG */
+
+	udelay(1000);
+	if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
+		printf("Error writing strap1 in %s\n", argv[2]);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	evb440spe,	3,	1,	do_evb440spe,
+	"program the serial device strap",
+	"wrclk [prom0|prom1] - program the serial device strap"
+);
diff --git a/u-boot/board/amcc/yucca/config.mk b/u-boot/board/amcc/yucca/config.mk
new file mode 100644
index 0000000..179df64
--- /dev/null
+++ b/u-boot/board/amcc/yucca/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440SPe Reference Platform (yucca) board
+#
+
+ifeq ($(ramsym),1)
+CONFIG_SYS_TEXT_BASE = 0x07FD0000
+else
+CONFIG_SYS_TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/amcc/yucca/flash.c b/u-boot/board/amcc/yucca/flash.c
new file mode 100644
index 0000000..20b6af9
--- /dev/null
+++ b/u-boot/board/amcc/yucca/flash.c
@@ -0,0 +1,1055 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include "yucca.h"
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
+	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
+	{0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+	{0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
+	{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
+	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf("AMD ");
+			break;
+		case FLASH_MAN_STM:
+			printf("STM ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf("FUJITSU ");
+			break;
+		case FLASH_MAN_SST:
+			printf("SST ");
+			break;
+		case FLASH_MAN_MX:
+			printf("MIXC ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			printf("AM29F040 (512 Kbit, uniform sector size)\n");
+			break;
+		case FLASH_AM400B:
+			printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM400T:
+			printf("AM29LV400T (4 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AM800B:
+			printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM800T:
+			printf("AM29LV800T (8 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AMD016:
+			printf("AM29F016D (16 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_AM160B:
+			printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM160T:
+			printf("AM29LV160T (16 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AM320B:
+			printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM320T:
+			printf("AM29LV320T (32 Mbit, top boot sector)\n");
+			break;
+		case FLASH_AM033C:
+			printf("AM29LV033C (32 Mbit, top boot sector)\n");
+			break;
+		case FLASH_SST800A:
+			printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_SST160A:
+			printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_STMW320DT:
+			printf ("M29W320DT (32 M, top sector)\n");
+			break;
+		case FLASH_MXLV320T:
+			printf ("MXLV320T (32 Mbit, top sector)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1)
+		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+	else
+		return flash_get_size_1(addr, info);
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+			info->flash_id = FLASH_MAN_SST;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x0080000;	/* => 512 ko */
+			break;
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x0080000;	/* => 512 ko */
+			break;
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x0080000;	/* => 512 ko */
+			break;
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
+			info->flash_id += FLASH_AMD016;
+			info->sector_count = 32;
+			info->size = 0x00200000;
+			break;		/* => 2 MB              */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
+			info->flash_id += FLASH_AMDLV033C;
+			info->sector_count = 64;
+			info->size = 0x00400000;
+			break;		/* => 4 MB              */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00080000;
+			break;		/* => 0.5 MB            */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00080000;
+			break;		/* => 0.5 MB            */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00100000;
+			break;		/* => 1 MB              */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00100000;
+			break;		/* => 1 MB              */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00200000;
+			break;		/* => 2 MB              */
+
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00200000;
+			break;		/* => 2 MB              */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < 4; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i)
+			data = (data << 8) | *src++;
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *) cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i, flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	int n;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+			info->flash_id = FLASH_MAN_SST;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
+			info->flash_id = FLASH_MAN_MX;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
+			info->flash_id += FLASH_STMW320DT;
+			info->sector_count = 67;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
+			info->flash_id += FLASH_MXLV320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+			((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n = 0; n < 2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+		info->start[i--] = base + info->size - 0x00010000;
+
+		for (; i >= 0; i--)
+			info->start[i] = base + i * 0x00010000;
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+
+			for (i = 4; i < info->sector_count; i++)
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+
+			for (; i >= 0; i--)
+				info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!",	prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+	unsigned long val;
+	unsigned long ebc_boot_size;
+	unsigned long boot_selection;
+
+	mfsdr(sdr_pstrp0, val);
+	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28;
+
+	if ((index == 0xc) || (index == 8)) {
+		/*
+		 * Boot Settings in IIC EEprom address 0xA8 or 0xA0
+		 * Read Serial Device Strap Register1 in PPC440SPe
+		 */
+		mfsdr(SDR0_SDSTP1, val);
+		boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+		ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+		switch(boot_selection) {
+			case SDR0_SDSTP1_BOOT_SEL_EBC:
+				switch(ebc_boot_size) {
+					case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+						index = 3;
+						break;
+					case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+						index = 0;
+						break;
+				}
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_PCI:
+				index = 1;
+				break;
+
+		}
+	} /*else if (index == 0) {*/
+/*		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
+/*			index = 8;*/ /* sram below op code flash -> new index 8*/
+/*	}*/
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0)
+			continue;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/u-boot/board/amcc/yucca/init.S b/u-boot/board/amcc/yucca/init.S
new file mode 100644
index 0000000..c63002b
--- /dev/null
+++ b/u-boot/board/amcc/yucca/init.S
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+	.globl tlbtabA
+tlbtabA:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
+
+	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
+	tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+	.globl tlbtabB
+tlbtabB:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
+
+	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/amcc/yucca/yucca.c b/u-boot/board/amcc/yucca/yucca.c
new file mode 100644
index 0000000..b128e46
--- /dev/null
+++ b/u-boot/board/amcc/yucca/yucca.c
@@ -0,0 +1,732 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Port to AMCC-440SPE Evaluation Board SOP - April 2005
+ *
+ * PCIe supporting routines derived from Linux 440SPe PCIe driver.
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+
+#include "yucca.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fpga_init (void);
+
+#define DEBUG_ENV
+#ifdef DEBUG_ENV
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+#define FALSE	0
+#define TRUE	1
+
+int board_early_init_f (void)
+{
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+#define BOOT_FROM_SMALL_FLASH		0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
+#define BOOT_FROM_PCI			0x02
+#define BOOT_DEVICE_UNKNOWN		0x03
+
+/*----------------------------------------------------------------------------+
+| EBC Devices Characteristics
+|   Peripheral Bank Access Parameters       -   EBC_BxAP
+|   Peripheral Bank Configuration Register  -   EBC_BxCR
++----------------------------------------------------------------------------*/
+
+/*
+ * Small Flash and FRAM
+ * BU Value
+ * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_SMALL_FLASH		EBC_BXAP_BME_DISABLED	| \
+					EBC_BXAP_TWT_ENCODE(7)	| \
+					EBC_BXAP_BCE_DISABLE	| \
+					EBC_BXAP_BCT_2TRANS	| \
+					EBC_BXAP_CSN_ENCODE(0)	| \
+					EBC_BXAP_OEN_ENCODE(0)	| \
+					EBC_BXAP_WBN_ENCODE(0)	| \
+					EBC_BXAP_WBF_ENCODE(0)	| \
+					EBC_BXAP_TH_ENCODE(0)	| \
+					EBC_BXAP_RE_DISABLED	| \
+					EBC_BXAP_SOR_DELAYED	| \
+					EBC_BXAP_BEM_WRITEONLY	| \
+					EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_SMALL_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SMALL_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xe7000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_8BIT
+
+/*
+ * Large Flash and SRAM
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_LARGE_FLASH		EBC_BXAP_BME_DISABLED	| \
+					EBC_BXAP_TWT_ENCODE(7)	| \
+					EBC_BXAP_BCE_DISABLE	| \
+					EBC_BXAP_BCT_2TRANS	| \
+					EBC_BXAP_CSN_ENCODE(0)	| \
+					EBC_BXAP_OEN_ENCODE(0)	| \
+					EBC_BXAP_WBN_ENCODE(0)	| \
+					EBC_BXAP_WBF_ENCODE(0)	| \
+					EBC_BXAP_TH_ENCODE(0)	| \
+					EBC_BXAP_RE_DISABLED	| \
+					EBC_BXAP_SOR_DELAYED	| \
+					EBC_BXAP_BEM_WRITEONLY	| \
+					EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_LARGE_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xE7000000)	| \
+					EBC_BXCR_BS_16MB		| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_16BIT
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA			EBC_BXAP_BME_DISABLED	| \
+					EBC_BXAP_TWT_ENCODE(11)	| \
+					EBC_BXAP_BCE_DISABLE	| \
+					EBC_BXAP_BCT_2TRANS	| \
+					EBC_BXAP_CSN_ENCODE(10)	| \
+					EBC_BXAP_OEN_ENCODE(1)	| \
+					EBC_BXAP_WBN_ENCODE(1)	| \
+					EBC_BXAP_WBF_ENCODE(1)	| \
+					EBC_BXAP_TH_ENCODE(1)	| \
+					EBC_BXAP_RE_DISABLED	| \
+					EBC_BXAP_SOR_DELAYED	| \
+					EBC_BXAP_BEM_RW		| \
+					EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_FPGA_CS1		EBC_BXCR_BAS_ENCODE(0xe2000000)	| \
+					EBC_BXCR_BS_1MB			| \
+					EBC_BXCR_BU_RW			| \
+					EBC_BXCR_BW_16BIT
+
+	 unsigned long mfr;
+	/*
+	 * Define Variables for EBC initialization depending on BOOTSTRAP option
+	 */
+	unsigned long sdr0_pinstp, sdr0_sdstp1 ;
+	unsigned long bootstrap_settings, ebc_data_width, boot_selection;
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*-------------------------------------------------------------------+
+	 | Initialize EBC CONFIG -
+	 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+	 | default value :
+	 |	0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+	 |
+	 +-------------------------------------------------------------------*/
+	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+			EBC_CFG_PTD_ENABLE |
+			EBC_CFG_RTC_16PERCLK |
+			EBC_CFG_ATC_PREVIOUS |
+			EBC_CFG_DTC_PREVIOUS |
+			EBC_CFG_CTC_PREVIOUS |
+			EBC_CFG_OEO_PREVIOUS |
+			EBC_CFG_EMC_DEFAULT |
+			EBC_CFG_PME_DISABLE |
+			EBC_CFG_PR_16);
+
+	/*-------------------------------------------------------------------+
+	 |
+	 |  PART 1 : Initialize EBC Bank 1
+	 |  ==============================
+	 | Bank1 is always associated to the EPLD.
+	 | It has to be initialized prior to other banks settings computation
+	 | since some board registers values may be needed to determine the
+	 | boot type
+	 |
+	 +-------------------------------------------------------------------*/
+	mtebc(PB1AP, EBC_BXAP_FPGA);
+	mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
+
+	/*-------------------------------------------------------------------+
+	 |
+	 |  PART 2 : Determine which boot device was selected
+	 |  =================================================
+	 |
+	 |  Read Pin Strap Register in PPC440SPe
+	 |  Result can either be :
+	 |   - Boot strap = boot from EBC 8bits     => Small Flash
+	 |   - Boot strap = boot from PCI
+	 |   - Boot strap = IIC
+	 |  In case of boot from IIC, read Serial Device Strap Register1
+	 |
+	 |  Result can either be :
+	 |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
+	 |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
+	 |   - Boot from PCI
+	 |
+	 +-------------------------------------------------------------------*/
+	/* Read Pin Strap Register in PPC440SP */
+	mfsdr(SDR0_PINSTP, sdr0_pinstp);
+	bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
+
+	switch (bootstrap_settings) {
+		case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
+			/*
+			 * Strapping Option A
+			 * Boot from EBC - 8 bits , Small Flash
+			 */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+		case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
+			/*
+			 * Strappping Option B
+			 * Boot from PCI
+			 */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+		case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
+		case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
+			/*
+			 * Strapping Option C or D
+			 * Boot Settings in IIC EEprom address 0x50 or 0x54
+			 * Read Serial Device Strap Register1 in PPC440SPe
+			 */
+			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
+			boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
+			ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
+
+			switch (boot_selection) {
+				case SDR0_SDSTP1_ERPN_EBC:
+					switch (ebc_data_width) {
+						case SDR0_SDSTP1_EBCW_16_BITS:
+							computed_boot_device =
+								BOOT_FROM_LARGE_FLASH_OR_SRAM;
+							break;
+						case SDR0_SDSTP1_EBCW_8_BITS :
+							computed_boot_device = BOOT_FROM_SMALL_FLASH;
+							break;
+					}
+					break;
+
+				case SDR0_SDSTP1_ERPN_PCI:
+					computed_boot_device = BOOT_FROM_PCI;
+					break;
+				default:
+					/* should not occure */
+					computed_boot_device = BOOT_DEVICE_UNKNOWN;
+			}
+			break;
+		default:
+			/* should not be */
+			computed_boot_device = BOOT_DEVICE_UNKNOWN;
+			break;
+	}
+
+	/*-------------------------------------------------------------------+
+	 |
+	 |  PART 3 : Compute EBC settings depending on selected boot device
+	 |  ======   ======================================================
+	 |
+	 | Resulting EBC init will be among following configurations :
+	 |
+	 |  - Boot from EBC 8bits => boot from Small Flash selected
+	 |            EBC-CS0     = Small Flash
+	 |            EBC-CS2     = Large Flash and SRAM
+	 |
+	 |  - Boot from EBC 16bits => boot from Large Flash or SRAM
+	 |            EBC-CS0     = Large Flash or SRAM
+	 |            EBC-CS2     = Small Flash
+	 |
+	 |  - Boot from PCI
+	 |            EBC-CS0     = not initialized to avoid address contention
+	 |            EBC-CS2     = same as boot from Small Flash selected
+	 |
+	 +-------------------------------------------------------------------*/
+	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+	switch (computed_boot_device) {
+		/*-------------------------------------------------------------------*/
+		case BOOT_FROM_PCI:
+		/*-------------------------------------------------------------------*/
+			/*
+			 * By Default CS2 is affected to LARGE Flash
+			 * do not initialize SMALL FLASH to avoid address contention
+			 * Large Flash
+			 */
+			ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
+			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+			break;
+
+		/*-------------------------------------------------------------------*/
+		case BOOT_FROM_SMALL_FLASH:
+		/*-------------------------------------------------------------------*/
+			ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
+			ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
+
+			/*
+			 * Large Flash or SRAM
+			 */
+			/* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
+			ebc0_cs2_bxap_value = 0x048ff240;
+			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+			break;
+
+		/*-------------------------------------------------------------------*/
+		case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+		/*-------------------------------------------------------------------*/
+			ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
+			ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
+
+			/* Small flash */
+			ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
+			ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
+			break;
+
+		/*-------------------------------------------------------------------*/
+		default:
+		/*-------------------------------------------------------------------*/
+			/* BOOT_DEVICE_UNKNOWN */
+			break;
+	}
+
+	mtebc(PB0AP, ebc0_cs0_bxap_value);
+	mtebc(PB0CR, ebc0_cs0_bxcr_value);
+	mtebc(PB2AP, ebc0_cs2_bxap_value);
+	mtebc(PB2CR, ebc0_cs2_bxcr_value);
+
+	/*--------------------------------------------------------------------+
+	 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
+	 +--------------------------------------------------------------------+
+	+---------------------------------------------------------------------+
+	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+	+---------+-----------------------------------+-------+-------+-------+
+	| IRQ 00  | UART0                             | High  | Level | Non   |
+	| IRQ 01  | UART1                             | High  | Level | Non   |
+	| IRQ 02  | IIC0                              | High  | Level | Non   |
+	| IRQ 03  | IIC1                              | High  | Level | Non   |
+	| IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
+	| IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
+	| IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
+	| IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
+	| IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
+	| IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
+	| IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
+	| IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
+	| IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
+	| IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
+	| IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
+	| IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
+	| IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
+	| IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
+	| IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
+	| IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	| IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	| IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	| IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	| IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
+	| IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
+	| IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
+	| IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
+	| IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
+	| IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
+	| IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
+	| IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
+	| IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
+	|----------------------------------------------------------------------
+	| IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 33  | MAL Serr                          | High  | Level | Non   |
+	| IRQ 34  | MAL Txde                          | High  | Level | Non   |
+	| IRQ 35  | MAL Rxde                          | High  | Level | Non   |
+	| IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
+	| IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
+	| IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
+	| IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
+	| IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
+	| IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
+	| IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
+	| IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
+	| IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
+	| IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
+	| IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
+	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	| IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 54  | DMA Error                         | High  | Level | Non   |
+	| IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
+	| IRQ 56  | Serial ROM                        | High  | Level | Non   |
+	| IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
+	| IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
+	| IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
+	| IRQ 62  | Reserved                          | High  | Level | Non   |
+	| IRQ 63  | XOR                               | High  | Level | Non   |
+	|----------------------------------------------------------------------
+	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
+	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
+	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
+	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
+	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
+	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
+	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
+	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
+	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
+	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
+	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
+	|---------------------------------------------------------------------
+	| IRQ 96  | PE0 INTA                          | High  | Level | Non   |
+	| IRQ 97  | PE0 INTB                          | High  | Level | Non   |
+	| IRQ 98  | PE0 INTC                          | High  | Level | Non   |
+	| IRQ 99  | PE0 INTD                          | High  | Level | Non   |
+	| IRQ 100 | PE1 INTA                          | High  | Level | Non   |
+	| IRQ 101 | PE1 INTB                          | High  | Level | Non   |
+	| IRQ 102 | PE1 INTC                          | High  | Level | Non   |
+	| IRQ 103 | PE1 INTD                          | High  | Level | Non   |
+	| IRQ 104 | PE2 INTA                          | High  | Level | Non   |
+	| IRQ 105 | PE2 INTB                          | High  | Level | Non   |
+	| IRQ 106 | PE2 INTC                          | High  | Level | Non   |
+	| IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
+	| IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
+	| IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
+	| IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
+	| IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
+	| IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
+	| IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
+	| IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
+	| IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
+	| IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
+	| IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
+	| IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
+	| IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
+	| IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
+	| IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
+	| IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
+	| IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
+	| IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
+	| IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
+	| IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
+	| IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
+	+---------+-----------------------------------+-------+-------+------*/
+	/*--------------------------------------------------------------------+
+	 | Put UICs in PowerPC440SPemode.
+	 | Initialise UIC registers.  Clear all interrupts.  Disable all
+	 | interrupts.
+	 | Set critical interrupt values.  Set interrupt polarities.  Set
+	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 | interrupts again.
+	 +-------------------------------------------------------------------*/
+	mtdcr (UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC3CR, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (UIC3PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (UIC3SR, 0x00000000);	/* clear all  interrupts */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all  interrupts */
+
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (UIC2PR, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr (UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all interrupts excepted
+					 * cascade to be checked */
+	mtdcr (UIC0CR, 0x00104001);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr (UIC0PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
+					 * priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
+
+	mfsdr(SDR0_MFR, mfr);
+	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
+	mtsdr(SDR0_MFR, mfr);
+
+	fpga_init();
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Yucca - AMCC 440SPe Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+	if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+		return 1;
+	else
+		return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_WRDTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+	return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_CLKTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+	return default_val;
+}
+
+#if defined(CONFIG_PCI)
+int board_pcie_card_present(int port)
+{
+	u16 reg;
+
+	reg = in_be16((u16 *)FPGA_REG1C);
+	switch(port) {
+	case 0:
+		return !(reg & FPGA_REG1C_PE0_PRSNT);
+	case 1:
+		return !(reg & FPGA_REG1C_PE1_PRSNT);
+	case 2:
+		return !(reg & FPGA_REG1C_PE2_PRSNT);
+	default:
+		return 0;
+	}
+}
+
+/*
+ * For the given slot, set endpoint mode, send power to the slot,
+ * turn on the green LED and turn off the yellow LED, enable the
+ * clock. In endpoint mode reset bit is read only.
+ */
+void board_pcie_setup_port(int port, int rootpoint)
+{
+	u16 power, clock, green_led, yellow_led,
+		reset_off, rp, ep;
+
+	switch (port) {
+	case 0:
+		rp = FPGA_REG1C_PE0_ROOTPOINT;
+		ep = 0;
+		break;
+	case 1:
+		rp = 0;
+		ep = FPGA_REG1C_PE1_ENDPOINT;
+		break;
+	case 2:
+		rp = 0;
+		ep = FPGA_REG1C_PE2_ENDPOINT;
+		break;
+
+	default:
+		return;
+	}
+
+	power = FPGA_REG1A_PWRON_ENCODE(port);
+	green_led = FPGA_REG1A_GLED_ENCODE(port);
+	clock = FPGA_REG1A_REFCLK_ENCODE(port);
+	yellow_led = FPGA_REG1A_YLED_ENCODE(port);
+	reset_off = FPGA_REG1C_PERST_ENCODE(port);
+
+	out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
+		 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
+
+	out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
+		 (rp | in_be16((u16 *)FPGA_REG1C)));
+
+	if (rootpoint) {
+		/*
+		 * Leave device in reset for a while after powering on the
+		 * slot to give it a chance to initialize.
+		 */
+		udelay(250 * 1000);
+
+		out_be16((u16 *)FPGA_REG1C,
+			 reset_off | in_be16((u16 *)FPGA_REG1C));
+	}
+}
+#endif	/* defined(CONFIG_PCI) */
+
+int misc_init_f (void)
+{
+	uint reg;
+
+	out16(FPGA_REG10, (in16(FPGA_REG10) &
+			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
+				FPGA_REG10_10MHZ_ENABLE |
+				FPGA_REG10_100MHZ_ENABLE |
+				FPGA_REG10_GIGABIT_ENABLE |
+				FPGA_REG10_FULL_DUPLEX );
+
+	udelay(10000);	/* wait 10ms */
+
+	out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
+
+	/* minimal init for PCIe */
+	/* pci express 0 Endpoint Mode */
+	mfsdr(SDRN_PESDR_DLPSET(0), reg);
+	reg &= (~0x00400000);
+	mtsdr(SDRN_PESDR_DLPSET(0), reg);
+	/* pci express 1 Rootpoint  Mode */
+	mfsdr(SDRN_PESDR_DLPSET(1), reg);
+	reg |= 0x00400000;
+	mtsdr(SDRN_PESDR_DLPSET(1), reg);
+	/* pci express 2 Rootpoint  Mode */
+	mfsdr(SDRN_PESDR_DLPSET(2), reg);
+	reg |= 0x00400000;
+	mtsdr(SDRN_PESDR_DLPSET(2), reg);
+
+	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
+				~FPGA_REG1C_PE0_ROOTPOINT &
+				~FPGA_REG1C_PE1_ENDPOINT  &
+				~FPGA_REG1C_PE2_ENDPOINT));
+
+	return 0;
+}
+
+void fpga_init(void)
+{
+	/*
+	 * by default sdram access is disabled by fpga
+	 */
+	out16(FPGA_REG10, (in16 (FPGA_REG10) |
+				FPGA_REG10_SDRAM_ENABLE |
+				FPGA_REG10_ENABLE_DISPLAY ));
+
+	return;
+}
+
+/*---------------------------------------------------------------------------+
+ | onboard_pci_arbiter_selected => from EPLD
+ +---------------------------------------------------------------------------*/
+int onboard_pci_arbiter_selected(int core_pci)
+{
+#if 0
+	unsigned long onboard_pci_arbiter_sel;
+
+	onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
+
+	if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
+		return (BOARD_OPTION_SELECTED);
+	else
+#endif
+	return (BOARD_OPTION_NOT_SELECTED);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/amcc/yucca/yucca.h b/u-boot/board/amcc/yucca/yucca.h
new file mode 100644
index 0000000..4d13021
--- /dev/null
+++ b/u-boot/board/amcc/yucca/yucca.h
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __YUCCA_H_
+#define __YUCCA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+
+#define TMR_FREQ_EXT		25000000
+#define BOARD_UART_CLOCK	11059200
+
+#define BOARD_OPTION_SELECTED		1
+#define BOARD_OPTION_NOT_SELECTED	0
+
+#define ENGINEERING_CLOCK_CHECKING "clk_chk"
+#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
+
+#define ENGINEERING_CLOCK_CHECKING_DATA	1
+#define ENGINEERING_EXTERNAL_CLOCK_DATA	2
+
+/* ethernet definition */
+#define MAX_ENETMODE_PARM	3
+#define ENETMODE_NEG		0
+#define ENETMODE_SPEED		1
+#define ENETMODE_DUPLEX		2
+
+#define ENETMODE_AUTONEG	0
+#define ENETMODE_NO_AUTONEG	1
+#define ENETMODE_10		2
+#define ENETMODE_100		3
+#define ENETMODE_1000		4
+#define ENETMODE_HALF		5
+#define ENETMODE_FULL		6
+
+#define NUM_TLB_ENTRIES          64
+
+/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
+#define MICRON_SPD_JEDEC_ID 0x2c
+
+/*----------------------------------------------------------------------------+
+| TLB specific defines.
++----------------------------------------------------------------------------*/
+#define TLB_256MB_ALIGN_MASK	0xF0000000
+#define TLB_16MB_ALIGN_MASK	0xFF000000
+#define TLB_1MB_ALIGN_MASK	0xFFF00000
+#define TLB_256KB_ALIGN_MASK	0xFFFC0000
+#define TLB_64KB_ALIGN_MASK	0xFFFF0000
+#define TLB_16KB_ALIGN_MASK	0xFFFFC000
+#define TLB_4KB_ALIGN_MASK	0xFFFFF000
+#define TLB_1KB_ALIGN_MASK	0xFFFFFC00
+#define TLB_256MB_SIZE		0x10000000
+#define TLB_16MB_SIZE		0x01000000
+#define TLB_1MB_SIZE		0x00100000
+#define TLB_256KB_SIZE		0x00040000
+#define TLB_64KB_SIZE		0x00010000
+#define TLB_16KB_SIZE		0x00004000
+#define TLB_4KB_SIZE		0x00001000
+#define TLB_1KB_SIZE		0x00000400
+
+#define TLB_WORD0_EPN_MASK	0xFFFFFC00
+#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_V_MASK	0x00000200
+#define TLB_WORD0_V_ENABLE	0x00000200
+#define TLB_WORD0_V_DISABLE	0x00000000
+#define TLB_WORD0_TS_MASK	0x00000100
+#define TLB_WORD0_TS_1		0x00000100
+#define TLB_WORD0_TS_0		0x00000000
+#define TLB_WORD0_SIZE_MASK	0x000000F0
+#define TLB_WORD0_SIZE_1KB	0x00000000
+#define TLB_WORD0_SIZE_4KB	0x00000010
+#define TLB_WORD0_SIZE_16KB	0x00000020
+#define TLB_WORD0_SIZE_64KB	0x00000030
+#define TLB_WORD0_SIZE_256KB	0x00000040
+#define TLB_WORD0_SIZE_1MB	0x00000050
+#define TLB_WORD0_SIZE_16MB	0x00000070
+#define TLB_WORD0_SIZE_256MB	0x00000090
+#define TLB_WORD0_TPAR_MASK	0x0000000F
+#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD1_RPN_MASK	0xFFFFFC00
+#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_PAR1_MASK	0x00000300
+#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define TLB_WORD1_PAR1_0	0x00000000
+#define TLB_WORD1_PAR1_1	0x00000100
+#define TLB_WORD1_PAR1_2	0x00000200
+#define TLB_WORD1_PAR1_3	0x00000300
+#define TLB_WORD1_ERPN_MASK	0x0000000F
+#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD2_PAR2_MASK	0xC0000000
+#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+#define TLB_WORD2_PAR2_0	0x00000000
+#define TLB_WORD2_PAR2_1	0x40000000
+#define TLB_WORD2_PAR2_2	0x80000000
+#define TLB_WORD2_PAR2_3	0xC0000000
+#define TLB_WORD2_U0_MASK	0x00008000
+#define TLB_WORD2_U0_ENABLE	0x00008000
+#define TLB_WORD2_U0_DISABLE	0x00000000
+#define TLB_WORD2_U1_MASK	0x00004000
+#define TLB_WORD2_U1_ENABLE	0x00004000
+#define TLB_WORD2_U1_DISABLE	0x00000000
+#define TLB_WORD2_U2_MASK	0x00002000
+#define TLB_WORD2_U2_ENABLE	0x00002000
+#define TLB_WORD2_U2_DISABLE	0x00000000
+#define TLB_WORD2_U3_MASK	0x00001000
+#define TLB_WORD2_U3_ENABLE	0x00001000
+#define TLB_WORD2_U3_DISABLE	0x00000000
+#define TLB_WORD2_W_MASK	0x00000800
+#define TLB_WORD2_W_ENABLE	0x00000800
+#define TLB_WORD2_W_DISABLE	0x00000000
+#define TLB_WORD2_I_MASK	0x00000400
+#define TLB_WORD2_I_ENABLE	0x00000400
+#define TLB_WORD2_I_DISABLE	0x00000000
+#define TLB_WORD2_M_MASK	0x00000200
+#define TLB_WORD2_M_ENABLE	0x00000200
+#define TLB_WORD2_M_DISABLE	0x00000000
+#define TLB_WORD2_G_MASK	0x00000100
+#define TLB_WORD2_G_ENABLE	0x00000100
+#define TLB_WORD2_G_DISABLE	0x00000000
+#define TLB_WORD2_E_MASK	0x00000080
+#define TLB_WORD2_E_ENABLE	0x00000080
+#define TLB_WORD2_E_DISABLE	0x00000000
+#define TLB_WORD2_UX_MASK	0x00000020
+#define TLB_WORD2_UX_ENABLE	0x00000020
+#define TLB_WORD2_UX_DISABLE	0x00000000
+#define TLB_WORD2_UW_MASK	0x00000010
+#define TLB_WORD2_UW_ENABLE	0x00000010
+#define TLB_WORD2_UW_DISABLE	0x00000000
+#define TLB_WORD2_UR_MASK	0x00000008
+#define TLB_WORD2_UR_ENABLE	0x00000008
+#define TLB_WORD2_UR_DISABLE	0x00000000
+#define TLB_WORD2_SX_MASK	0x00000004
+#define TLB_WORD2_SX_ENABLE	0x00000004
+#define TLB_WORD2_SX_DISABLE	0x00000000
+#define TLB_WORD2_SW_MASK	0x00000002
+#define TLB_WORD2_SW_ENABLE	0x00000002
+#define TLB_WORD2_SW_DISABLE	0x00000000
+#define TLB_WORD2_SR_MASK	0x00000001
+#define TLB_WORD2_SR_ENABLE	0x00000001
+#define TLB_WORD2_SR_DISABLE	0x00000000
+
+/*----------------------------------------------------------------------------+
+| Board specific defines.
++----------------------------------------------------------------------------*/
+#define NONCACHE_MEMORY_SIZE     (64*1024)
+#define NONCACHE_AREA0_ENDOFFSET (64*1024)
+#define NONCACHE_AREA1_ENDOFFSET (32*1024)
+
+#define FLASH_SECTORSIZE	0x00010000
+
+/* SDRAM MICRON */
+#define SDRAM_MICRON		0x2C
+
+#define SDRAM_TRUE		1
+#define SDRAM_FALSE		0
+#define SDRAM_DDR1		1
+#define SDRAM_DDR2		2
+#define SDRAM_NONE		0
+#define MAXDIMMS		2		/* Changes le 12/01/05 pour 1.6 */
+#define MAXRANKS		4		/* Changes le 12/01/05 pour 1.6 */
+#define MAXBANKSPERDIMM		2
+#define MAXRANKSPERDIMM		2
+#define MAXBXCF			4		/* Changes le 12/01/05 pour 1.6 */
+#define MAXSDRAMMEMORY		0xFFFFFFFF	/* 4GB */
+#define ERROR_STR_LENGTH	256
+#define MAX_SPD_BYTES		256		/* Max number of bytes on the DIMM's SPD EEPROM */
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define sdr_pstrp0	0x0040
+
+#define	SDR0_SDSTP1_EBC_ROM_BS_MASK	0x00000080 /* EBC Boot bus width Mask */
+#define	SDR0_SDSTP1_EBC_ROM_BS_16BIT	0x00000080 /* EBC 16 Bits */
+#define	SDR0_SDSTP1_EBC_ROM_BS_8BIT	0x00000000 /* EBC  8 Bits */
+
+#define	SDR0_SDSTP1_BOOT_SEL_MASK	0x00080000 /* Boot device Selection Mask */
+#define	SDR0_SDSTP1_BOOT_SEL_EBC	0x00000000 /* EBC */
+#define	SDR0_SDSTP1_BOOT_SEL_PCI	0x00080000 /* PCI */
+
+#define	SDR0_SDSTP1_EBC_SIZE_MASK	0x00000060 /* Boot rom size Mask */
+#define	SDR0_SDSTP1_BOOT_SIZE_16MB	0x00000060 /* 16 MB */
+#define	SDR0_SDSTP1_BOOT_SIZE_8MB	0x00000040 /*  8 MB */
+#define	SDR0_SDSTP1_BOOT_SIZE_4MB	0x00000020 /*  4 MB */
+#define	SDR0_SDSTP1_BOOT_SIZE_2MB	0x00000000 /*  2 MB */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0			0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000  /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000  /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000  /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000  /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000  /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000  /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000  /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000  /* Default strap settings 7 */
+
+/* fpgareg - defines are in include/config/YUCCA.h */
+
+#define SDR0_CUST0_ENET3_MASK		0x00000080
+#define SDR0_CUST0_ENET3_COPPER		0x00000000
+#define SDR0_CUST0_ENET3_FIBER		0x00000080
+#define SDR0_CUST0_RGMII3_MASK		0x00000070
+#define SDR0_CUST0_RGMII3_ENCODE(n)	((((unsigned long)(n))&0x7)<<4)
+#define SDR0_CUST0_RGMII3_DECODE(n)	((((unsigned long)(n))>>4)&0x07)
+#define SDR0_CUST0_RGMII3_DISAB		0x00000000
+#define SDR0_CUST0_RGMII3_RTBI		0x00000040
+#define SDR0_CUST0_RGMII3_RGMII		0x00000050
+#define SDR0_CUST0_RGMII3_TBI		0x00000060
+#define SDR0_CUST0_RGMII3_GMII		0x00000070
+#define SDR0_CUST0_ENET2_MASK		0x00000008
+#define SDR0_CUST0_ENET2_COPPER		0x00000000
+#define SDR0_CUST0_ENET2_FIBER		0x00000008
+#define SDR0_CUST0_RGMII2_MASK		0x00000007
+#define SDR0_CUST0_RGMII2_ENCODE(n)	((((unsigned long)(n))&0x7)<<0)
+#define SDR0_CUST0_RGMII2_DECODE(n)	((((unsigned long)(n))>>0)&0x07)
+#define SDR0_CUST0_RGMII2_DISAB		0x00000000
+#define SDR0_CUST0_RGMII2_RTBI		0x00000004
+#define SDR0_CUST0_RGMII2_RGMII		0x00000005
+#define SDR0_CUST0_RGMII2_TBI		0x00000006
+#define SDR0_CUST0_RGMII2_GMII		0x00000007
+
+#define ONE_MILLION			1000000
+#define ONE_BILLION			1000000000
+
+/*----------------------------------------------------------------------------+
+|                               X
+|                              XX
+| XX  XXX   XXXXX   XX XXX    XXXXX
+| XX  XX        X    XXX XX    XX
+| XX  XX   XXXXXX    XX        XX
+| XX  XX   X   XX    XX        XX XX
+|  XXX XX  XXXXX X  XXXX        XXX
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+| Declare Configuration values
++----------------------------------------------------------------------------*/
+
+typedef enum config_selection {
+	CONFIG_NOT_SELECTED,
+	CONFIG_SELECTED
+} config_selection_t;
+
+typedef enum config_list {
+	UART2_IN_SERVICE_MODE,
+	CPU_TRACE_MODE,
+	UART1_CTS_RTS,
+	CONFIG_NB
+} config_list_t;
+
+#define MAX_CONFIG_SELECT_NB			3
+
+#define BOARD_INFO_UART2_IN_SERVICE_MODE	1
+#define BOARD_INFO_CPU_TRACE_MODE		2
+#define BOARD_INFO_UART1_CTS_RTS_MODE		4
+
+void force_bup_config_selection(config_selection_t *confgi_select_P);
+void update_config_selection_table(config_selection_t *config_select_P);
+void display_config_selection(config_selection_t *config_select_P);
+
+/*----------------------------------------------------------------------------+
+|                     XX
+|
+|   XXXX    XX XXX   XXX     XXXX
+|  XX        XX  XX   XX    XX  XX
+|  XX  XXX   XX  XX   XX    XX  XX
+|  XX  XX    XXXXX    XX    XX  XX
+|   XXXX     XX      XXXX    XXXX
+|           XXXX
+|
+|
+|
+| +------------------------------------------------------------------+
+| |  GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
+| +----------------------+------------------+-----+------------+-----+
+| |                      |                  |     |            |     |
+| | GPIO0_0              | PCIX0REQ2_N      | I/O |  TRCCLK    |     |
+| | GPIO0_1              | PCIX0REQ3_N      | I/O |  TRCBS0    |     |
+| | GPIO0_2              | PCIX0GNT2_N      | I/O |  TRCBS1    |     |
+| | GPIO0_3              | PCIX0GNT3_N      | I/O |  TRCBS2    |     |
+| | GPIO0_4              | PCIX1REQ2_N      | I/O |  TRCES0    |     |
+| | GPIO0_5              | PCIX1REQ3_N      | I/O |  TRCES1    |     |
+| | GPIO0_6              | PCIX1GNT2_N      | I/O |  TRCES2    | NA  |
+| | GPIO0_7              | PCIX1GNT3_N      | I/O |  TRCES3    | NA  |
+| | GPIO0_8              | PERREADY         |  I  |  TRCES4    | NA  |
+| | GPIO0_9              | PERCS1_N         |  O  |  TRCTS0    | NA  |
+| | GPIO0_10             | PERCS2_N         |  O  |  TRCTS1    | NA  |
+| | GPIO0_11             | IRQ0             |  I  |  TRCTS2    | NA  |
+| | GPIO0_12             | IRQ1             |  I  |  TRCTS3    | NA  |
+| | GPIO0_13             | IRQ2             |  I  |  TRCTS4    | NA  |
+| | GPIO0_14             | IRQ3             |  I  |  TRCTS5    | NA  |
+| | GPIO0_15             | IRQ4             |  I  |  TRCTS6    | NA  |
+| | GPIO0_16             | IRQ5             |  I  |  UART2RX   |  I  |
+| | GPIO0_17             | PERBE0_N         |  O  |  UART2TX   |  O  |
+| | GPIO0_18             | PCI0GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_19             | PCI0GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_20             | PCI0REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_21             | PCI0REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_22             | PCI1GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_23             | PCI1GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_24             | PCI1REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_25             | PCI1REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_26             | PCI2GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_27             | PCI2GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_28             | PCI2REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_29             | PCI2REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_30             | UART1RX          |  I  |  NA        | NA  |
+| | GPIO0_31             | UART1TX          |  O  |  NA        | NA  |
+| |                      |                  |     |            |     |
+| +----------------------+------------------+-----+------------+-----+
+|
++----------------------------------------------------------------------------*/
+
+unsigned long auto_calc_speed(void);
+/*----------------------------------------------------------------------------+
+| Prototypes
++----------------------------------------------------------------------------*/
+void print_evb440spe_info(void);
+
+int onboard_pci_arbiter_selected(int core_pci);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __YUCCA_H_ */
diff --git a/u-boot/board/amirix/ap1000/Makefile b/u-boot/board/amirix/ap1000/Makefile
new file mode 100644
index 0000000..fe7a6a2
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o serial.o pci.o powerspan.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/amirix/ap1000/ap1000.c b/u-boot/board/amirix/ap1000/ap1000.c
new file mode 100644
index 0000000..c8dd99e
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/ap1000.c
@@ -0,0 +1,705 @@
+/*
+ * amirix.c: ppcboot platform support for AMIRIX board
+ *
+ * Copyright 2002 Mind NV
+ * Copyright 2003 AMIRIX Systems Inc.
+ *
+ * http://www.mind.be/
+ * http://www.amirix.com/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *          Frank Smith (smith@amirix.com)
+ *
+ * Derived from : Other platform support files in this tree, ml2
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/processor.h>
+
+#include "powerspan.h"
+#include "ap1000.h"
+
+int board_pre_init (void)
+{
+	return 0;
+}
+
+/** serial number and platform display at startup */
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+	char *e;
+
+	/* After a loadace command, the SystemAce control register is left in a wonky state. */
+	/* this code did not work in board_pre_init */
+	unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+
+	p[SYSACE_CTRLREG0] = 0x0;
+
+	/* add platform and device to banner */
+	switch (get_device ()) {
+	case AP1xx_AP107_TARGET:
+		puts (AP1xx_AP107_TARGET_STR);
+		break;
+	case AP1xx_AP120_TARGET:
+		puts (AP1xx_AP120_TARGET_STR);
+		break;
+	case AP1xx_AP130_TARGET:
+		puts (AP1xx_AP130_TARGET_STR);
+		break;
+	case AP1xx_AP1070_TARGET:
+		puts (AP1xx_AP1070_TARGET_STR);
+		break;
+	case AP1xx_AP1100_TARGET:
+		puts (AP1xx_AP1100_TARGET_STR);
+		break;
+	default:
+		puts (AP1xx_UNKNOWN_STR);
+		break;
+	}
+	puts (AP1xx_TARGET_STR);
+	puts (" with ");
+
+	switch (get_platform ()) {
+	case AP100_BASELINE_PLATFORM:
+	case AP1000_BASELINE_PLATFORM:
+		puts (AP1xx_BASELINE_PLATFORM_STR);
+		break;
+	case AP1xx_QUADGE_PLATFORM:
+		puts (AP1xx_QUADGE_PLATFORM_STR);
+		break;
+	case AP1xx_MGT_REF_PLATFORM:
+		puts (AP1xx_MGT_REF_PLATFORM_STR);
+		break;
+	case AP1xx_STANDARD_PLATFORM:
+		puts (AP1xx_STANDARD_PLATFORM_STR);
+		break;
+	case AP1xx_DUAL_PLATFORM:
+		puts (AP1xx_DUAL_PLATFORM_STR);
+		break;
+	case AP1xx_BASE_SRAM_PLATFORM:
+		puts (AP1xx_BASE_SRAM_PLATFORM_STR);
+		break;
+	case AP1xx_PCI_PCB_TESTPLATFORM:
+	case AP1000_PCI_PCB_TESTPLATFORM:
+		puts (AP1xx_PCI_PCB_TESTPLATFORM_STR);
+		break;
+	case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:
+		puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR);
+		break;
+	case AP1xx_SFP_MEZZ_TESTPLATFORM:
+		puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR);
+		break;
+	default:
+		puts (AP1xx_UNKNOWN_STR);
+		break;
+	}
+
+	if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) {
+		puts (AP1xx_TESTPLATFORM_STR);
+	} else {
+		puts (AP1xx_PLATFORM_STR);
+	}
+
+	putc ('\n');
+
+	puts ("Serial#: ");
+
+	if (!s) {
+		printf ("### No HW ID - assuming AMIRIX");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+	char *s = getenv ("dramsize");
+
+	if (s != NULL) {
+		if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
+			s += 2;
+		}
+		return (long int)simple_strtoul (s, NULL, 16);
+	} else {
+		/* give all 64 MB */
+		return 64 * 1024 * 1024;
+	}
+}
+
+unsigned int get_platform (void)
+{
+	unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+
+	return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
+}
+
+unsigned int get_device (void)
+{
+	unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+
+	return (*revision_reg_ptr & AP1xx_TARGET_MASK);
+}
+
+#if 0				/* loadace is not working; it appears to be a hardware issue with the system ace. */
+/*
+   This function loads FPGA configurations from the SystemACE CompactFlash
+*/
+int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+	int cfg;
+
+	if ((p[SYSACE_STATREG0] & 0x10) == 0) {
+		p[SYSACE_CTRLREG0] = 0x80;
+		printf ("\nNo CompactFlash Detected\n\n");
+		p[SYSACE_CTRLREG0] = 0x00;
+		return 1;
+	}
+
+	/* reset configuration controller: |  0x80 */
+	/* select cpflash                  & ~0x40 */
+	/* cfg start                       |  0x20 */
+	/* wait for cfgstart               & ~0x10 */
+	/* force cfgmode:                  |  0x08 */
+	/* do no force cfgaddr:            & ~0x04 */
+	/* clear mpulock:                  & ~0x02 */
+	/* do not force lock request       & ~0x01 */
+
+	p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08;
+	p[SYSACE_CTRLREG1] = 0x00;
+
+	/* force config address if arg2 exists */
+	if (argc == 2) {
+		cfg = simple_strtoul (argv[1], NULL, 10);
+
+		if (cfg > 7) {
+			printf ("\nInvalid Configuration\n\n");
+			p[SYSACE_CTRLREG0] = 0x00;
+			return 1;
+		}
+		/* Set config address */
+		p[SYSACE_CTRLREG1] = (cfg << 5);
+		/* force cfgaddr */
+		p[SYSACE_CTRLREG0] |= 0x04;
+
+	} else {
+		cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5;
+	}
+
+	/* release configuration controller */
+	printf ("\nLoading V2PRO with config %d...\n", cfg);
+	p[SYSACE_CTRLREG0] &= ~0x80;
+
+
+	while ((p[SYSACE_STATREG1] & 0x01) == 0) {
+
+		if (p[SYSACE_ERRREG0] & 0x80) {
+			/* attempting to load an invalid configuration makes the cpflash */
+			/* appear to be removed. Reset here to avoid that problem */
+			p[SYSACE_CTRLREG0] = 0x80;
+			printf ("\nConfiguration %d Read Error\n\n", cfg);
+			p[SYSACE_CTRLREG0] = 0x00;
+			return 1;
+		}
+	}
+
+	p[SYSACE_CTRLREG0] |= 0x20;
+
+	return 0;
+}
+#endif
+
+/** Console command to display and set the software reconfigure byte
+  * <pre>
+  * swconfig        - display the current value of the software reconfigure byte
+  * swconfig [#]    - change the software reconfigure byte to #
+  * </pre>
+  * @param  *cmdtp  [IN] as passed by run_command (ignored)
+  * @param  flag    [IN] as passed by run_command (ignored)
+  * @param  argc    [IN] as passed by run_command if 1, display, if 2 change
+  * @param  *argv[] [IN] contains the parameters to use
+  * @return
+  * <pre>
+  *      0 if passed
+  *     -1 if failed
+  * </pre>
+  */
+int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned char *sector_buffer = NULL;
+	unsigned char input_char;
+	int write_result;
+	unsigned int input_uint;
+
+	/* display value if no argument */
+	if (argc < 2) {
+		printf ("Software configuration byte is currently: 0x%02x\n",
+			*((unsigned char *) (SW_BYTE_SECTOR_ADDR +
+					     SW_BYTE_SECTOR_OFFSET)));
+		return 0;
+	} else if (argc > 3) {
+		printf ("Too many arguments\n");
+		return -1;
+	}
+
+	/* if 3 arguments, 3rd argument is the address to use */
+	if (argc == 3) {
+		input_uint = simple_strtoul (argv[1], NULL, 16);
+		sector_buffer = (unsigned char *) input_uint;
+	} else {
+		sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR;
+	}
+
+	input_char = simple_strtoul (argv[1], NULL, 0);
+	if ((input_char & ~SW_BYTE_MASK) != 0) {
+		printf ("Input of 0x%02x will be masked to 0x%02x\n",
+			input_char, (input_char & SW_BYTE_MASK));
+		input_char = input_char & SW_BYTE_MASK;
+	}
+
+	memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR,
+		SW_BYTE_SECTOR_SIZE);
+	sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char;
+
+
+	printf ("Erasing Flash...");
+	if (flash_sect_erase
+	    (SW_BYTE_SECTOR_ADDR,
+	     (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) {
+		return -1;
+	}
+
+	printf ("Writing to Flash... ");
+	write_result =
+		flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR,
+			     SW_BYTE_SECTOR_SIZE);
+	if (write_result != 0) {
+		flash_perror (write_result);
+		return -1;
+	} else {
+		printf ("done\n");
+		printf ("Software configuration byte is now: 0x%02x\n",
+			*((unsigned char *) (SW_BYTE_SECTOR_ADDR +
+					     SW_BYTE_SECTOR_OFFSET)));
+	}
+
+	return 0;
+}
+
+#define ONE_SECOND 1000000
+
+int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	int pause_time;
+	unsigned int delay_time;
+	int break_loop = 0;
+
+	/* display value if no argument */
+	if (argc < 2) {
+		pause_time = 1;
+	}
+
+	else if (argc > 2) {
+		printf ("Too many arguments\n");
+		return -1;
+	} else {
+		pause_time = simple_strtoul (argv[1], NULL, 0);
+	}
+
+	printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time);
+	delay_time = pause_time * ONE_SECOND;
+	while (break_loop == 0) {
+		udelay (delay_time);
+		if (serial_tstc () != 0) {
+			break_loop = 1;
+			/* eat user key presses */
+			while (serial_tstc () != 0) {
+				serial_getc ();
+			}
+		}
+	}
+
+	return 0;
+}
+
+int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n",
+		*((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
+	udelay (1000);
+	*((unsigned char *) AP1000_CPLD_BASE) = 1;
+
+	return 0;
+}
+
+#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125)
+#define TEMP_BUSY_BIT   0x80
+#define TEMP_LHIGH_BIT  0x40
+#define TEMP_LLOW_BIT   0x20
+#define TEMP_EHIGH_BIT  0x10
+#define TEMP_ELOW_BIT   0x08
+#define TEMP_OPEN_BIT   0x04
+#define TEMP_ETHERM_BIT 0x02
+#define TEMP_LTHERM_BIT 0x01
+
+int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd;
+	int ret_val = 0;
+	unsigned char temp_byte;
+	int temp;
+	int temp_low;
+	int low;
+	int low_low;
+	int high;
+	int high_low;
+	int therm;
+	unsigned char user_data[4] = { 0 };
+	int user_data_count = 0;
+	int ii;
+
+	if (argc > 1) {
+		cmd = argv[1][0];
+	} else {
+		cmd = 's';	/* default to status */
+	}
+
+	user_data_count = argc - 2;
+	for (ii = 0; ii < user_data_count; ii++) {
+		user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0);
+	}
+	switch (cmd) {
+	case 's':
+		if (I2CAccess
+		    (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Status    : 0x%02x  ", temp_byte);
+		if (temp_byte & TEMP_BUSY_BIT)
+			printf ("BUSY ");
+
+		if (temp_byte & TEMP_LHIGH_BIT)
+			printf ("LHIGH ");
+
+		if (temp_byte & TEMP_LLOW_BIT)
+			printf ("LLOW ");
+
+		if (temp_byte & TEMP_EHIGH_BIT)
+			printf ("EHIGH ");
+
+		if (temp_byte & TEMP_ELOW_BIT)
+			printf ("ELOW ");
+
+		if (temp_byte & TEMP_OPEN_BIT)
+			printf ("OPEN ");
+
+		if (temp_byte & TEMP_ETHERM_BIT)
+			printf ("ETHERM ");
+
+		if (temp_byte & TEMP_LTHERM_BIT)
+			printf ("LTHERM");
+
+		printf ("\n");
+
+		if (I2CAccess
+		    (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Config    : 0x%02x  ", temp_byte);
+
+		if (I2CAccess
+		    (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			printf ("\n");
+			goto fail;
+		}
+		printf ("Conversion: 0x%02x\n", temp_byte);
+		if (I2CAccess
+		    (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Cons Alert: 0x%02x  ", temp_byte);
+
+		if (I2CAccess
+		    (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			printf ("\n");
+			goto fail;
+		}
+		printf ("Therm Hyst: %d\n", temp_byte);
+
+		if (I2CAccess
+		    (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		temp = temp_byte;
+		if (I2CAccess
+		    (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		low = temp_byte;
+		if (I2CAccess
+		    (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		high = temp_byte;
+		if (I2CAccess
+		    (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		therm = temp_byte;
+		printf ("Local Temp: %2d     Low: %2d     High: %2d     THERM: %2d\n", temp, low, high, therm);
+
+		if (I2CAccess
+		    (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		temp = temp_byte;
+		if (I2CAccess
+		    (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		temp_low = temp_byte;
+		if (I2CAccess
+		    (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		low = temp_byte;
+		if (I2CAccess
+		    (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		low_low = temp_byte;
+		if (I2CAccess
+		    (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		high = temp_byte;
+		if (I2CAccess
+		    (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		high_low = temp_byte;
+		if (I2CAccess
+		    (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		therm = temp_byte;
+		if (I2CAccess
+		    (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Ext Temp  : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte);
+		break;
+	case 'l':		/* alter local limits : low, high, therm */
+		if (argc < 3) {
+			goto usage;
+		}
+
+		/* low */
+		if (I2CAccess
+		    (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &user_data[0], I2C_WRITE) != 0) {
+			goto fail;
+		}
+
+		if (user_data_count > 1) {
+			/* high */
+			if (I2CAccess
+			    (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+			     &user_data[1], I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 2) {
+			/* therm */
+			if (I2CAccess
+			    (0x20, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[2],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+		break;
+	case 'e':		/* alter external limits: low, high, therm, offset */
+		if (argc < 3) {
+			goto usage;
+		}
+
+		/* low */
+		if (I2CAccess
+		    (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &user_data[0], I2C_WRITE) != 0) {
+			goto fail;
+		}
+
+		if (user_data_count > 1) {
+			/* high */
+			if (I2CAccess
+			    (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+			     &user_data[1], I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 2) {
+			/* therm */
+			if (I2CAccess
+			    (0x19, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[2],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 3) {
+			/* offset */
+			if (I2CAccess
+			    (0x11, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[3],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+		break;
+	case 'c':		/* alter config settings: config, conv, cons alert, therm hyst */
+		if (argc < 3) {
+			goto usage;
+		}
+
+		/* config */
+		if (I2CAccess
+		    (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &user_data[0], I2C_WRITE) != 0) {
+			goto fail;
+		}
+
+		if (user_data_count > 1) {
+			/* conversion */
+			if (I2CAccess
+			    (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+			     &user_data[1], I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 2) {
+			/* cons alert */
+			if (I2CAccess
+			    (0x22, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[2],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 3) {
+			/* therm hyst */
+			if (I2CAccess
+			    (0x21, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[3],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+		break;
+	default:
+		goto usage;
+	}
+
+	goto done;
+fail:
+	printf ("Access to sensor failed\n");
+	ret_val = -1;
+	goto done;
+usage:
+	printf ("Usage:\n%s\n", cmdtp->help);
+
+done:
+	return ret_val;
+}
+
+U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
+	    "interact with the temperature sensor",
+	    "temp [s]\n"
+	    "        - Show status.\n"
+	    "temp l LOW [HIGH] [THERM]\n"
+	    "        - Set local limits.\n"
+	    "temp e LOW [HIGH] [THERM] [OFFSET]\n"
+	    "        - Set external limits.\n"
+	    "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n"
+	    "        - Set config options.\n"
+	    "\n"
+	    "All values can be decimal or hex (hex preceded with 0x).\n"
+	    "Only whole numbers are supported for external limits.");
+
+#if 0
+U_BOOT_CMD (loadace, 2, 0, do_loadace,
+	    "load fpga configuration from System ACE compact flash",
+	    "N\n"
+	    "    - Load configuration N (0-7) from System ACE compact flash\n"
+	    "loadace\n" "    - loads default configuration");
+#endif
+
+U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
+	    "display or modify the software configuration byte",
+	    "N [ADDRESS]\n"
+	    "    - set software configuration byte to N, optionally use ADDRESS as\n"
+	    "      location of buffer for flash copy\n"
+	    "swconfig\n" "    - display software configuration byte");
+
+U_BOOT_CMD (pause, 2, 0, do_pause,
+	    "sleep processor until any key is pressed with poll time of N seconds",
+	    "N\n"
+	    "    - sleep processor until any key is pressed with poll time of N seconds\n"
+	    "pause\n"
+	    "    - sleep processor until any key is pressed with poll time of 1 second");
+
+U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
+	    "trigger a board reconfigure to the software selected configuration",
+	    "\n"
+	    "    - trigger a board reconfigure to the software selected configuration");
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/amirix/ap1000/ap1000.h b/u-boot/board/amirix/ap1000/ap1000.h
new file mode 100644
index 0000000..118c4d1
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/ap1000.h
@@ -0,0 +1,173 @@
+/*
+ * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
+ *
+ * Author : James MacAulay
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#ifndef __AP1000_H
+#define __AP1000_H
+
+/*
+ *  Revision Register stuff
+ */
+#define AP1xx_FPGA_REV_ADDR 0x29000000
+
+#define AP1xx_PLATFORM_MASK	 0xFF000000
+#define AP100_BASELINE_PLATFORM	 0x01000000
+#define AP1xx_QUADGE_PLATFORM	 0x02000000
+#define AP1xx_MGT_REF_PLATFORM	 0x03000000
+#define AP1xx_STANDARD_PLATFORM	 0x04000000
+#define AP1xx_DUAL_PLATFORM	 0x05000000
+#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
+
+#define AP1000_BASELINE_PLATFORM 0x21000000
+
+#define AP1xx_TESTPLATFORM_MASK		0xC0000000
+#define AP1xx_PCI_PCB_TESTPLATFORM	0xC0000000
+#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
+#define AP1xx_SFP_MEZZ_TESTPLATFORM	0xC2000000
+
+#define AP1000_PCI_PCB_TESTPLATFORM	 0xC3000000
+
+#define AP1xx_TARGET_MASK  0x00FF0000
+#define AP1xx_AP107_TARGET 0x00010000
+#define AP1xx_AP120_TARGET 0x00020000
+#define AP1xx_AP130_TARGET 0x00030000
+#define AP1xx_AP1070_TARGET 0x00040000
+#define AP1xx_AP1100_TARGET 0x00050000
+
+#define AP1xx_UNKNOWN_STR "Unknown"
+
+#define AP1xx_PLATFORM_STR	     " Platform"
+#define AP1xx_BASELINE_PLATFORM_STR  "Baseline"
+#define AP1xx_QUADGE_PLATFORM_STR    "Quad GE"
+#define AP1xx_MGT_REF_PLATFORM_STR   "MGT Reference"
+#define AP1xx_STANDARD_PLATFORM_STR  "Standard"
+#define AP1xx_DUAL_PLATFORM_STR	     "Dual"
+#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
+
+#define AP1xx_TESTPLATFORM_STR		    " Test Platform"
+#define AP1xx_PCI_PCB_TESTPLATFORM_STR	    "Base"
+#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
+#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR	    "SFP Mezzanine"
+
+#define AP1xx_TARGET_STR       " Board"
+#define AP1xx_AP107_TARGET_STR "AP107"
+#define AP1xx_AP120_TARGET_STR "AP120"
+#define AP1xx_AP130_TARGET_STR "AP130"
+
+#define AP1xx_AP1070_TARGET_STR "AP1070"
+#define AP1xx_AP1100_TARGET_STR "AP1100"
+
+/*
+ *  Flash Stuff
+ */
+#define AP1xx_PROGRAM_FLASH_INDEX   0
+#define AP1xx_CONFIG_FLASH_INDEX    1
+
+/*
+ *  System Ace Stuff
+ */
+#define AP1000_SYSACE_REGBASE  0x28000000
+
+#define SYSACE_STATREG0 0x04 /* 7:0 */
+#define SYSACE_STATREG1 0x05 /* 15:8 */
+#define SYSACE_STATREG2 0x06 /* 23:16 */
+#define SYSACE_STATREG3 0x07 /* 31:24 */
+
+#define SYSACE_ERRREG0 0x08 /* 7:0 */
+#define SYSACE_ERRREG1 0x09 /* 15:8 */
+#define SYSACE_ERRREG2 0x0a /* 23:16 */
+#define SYSACE_ERRREG3 0x0b /* 31:24 */
+
+#define SYSACE_CTRLREG0 0x18 /* 7:0 */
+#define SYSACE_CTRLREG1 0x19 /* 15:8 */
+#define SYSACE_CTRLREG2 0x1A /* 23:16 */
+#define SYSACE_CTRLREG3 0x1B /* 31:24 */
+
+/*
+ *  Software reconfig thing
+ */
+#define SW_BYTE_SECTOR_ADDR	0x24FE0000
+#define SW_BYTE_SECTOR_OFFSET	0x0001FFFF
+#define SW_BYTE_SECTOR_SIZE	0x00020000
+#define SW_BYTE_MASK		0x00000003
+
+#define DEFAULT_TEMP_ADDR	0x00100000
+
+#define AP1000_CPLD_BASE	0x26000000
+
+/* PowerSpan II Stuff */
+#define PSII_SYNC() asm("eieio")
+#define PSPAN_BASEADDR 0x30000000
+#define EEPROM_DEFAULT { 0x01,	     /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */  \
+			0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
+			0x0,	     /* Byte 4 - Powerspan reserved  - start of short load */ \
+			0x0F,	     /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
+			0x0E,	     /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
+			0x00, 0x00,  /* Byte 7,8 - PCI-1 Subsystem ID - */ \
+			0x00, 0x00,  /* Byte 9,10 - PCI-1 Subsystem Vendor Id -	 */ \
+			0x00,	     /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
+			0x1F,	     /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
+			0xBA,	     /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
+			0xA0,	     /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
+			0x00,	     /* Byte 15 - Vital Product Data Disabled. */ \
+			0x88,	     /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1	*/ \
+			0x40,	     /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
+			0x00,	     /* Byte 18 - I2O disabled */ \
+			0x00,	     /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
+			0x00,0x00,   /* Bytes 20,21 - PCI 2 Subsystem Id */ \
+			0x00,0x00,   /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
+			0x0C,	     /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
+			0xBB,	     /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1  - 128 Meg (program/config flash) */ \
+			0x00,	     /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
+			0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
+			/* Long Load Information */ \
+			0x82,0x60,   /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
+			0x10,0xE3,   /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
+			0x06,	     /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
+			0x80,	     /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
+			0x00,	     /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
+			0x01,	     /* Byte 39 - Power span revision 1. */ \
+			0x6E,	     /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
+			0x40,	     /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
+			0x22,	     /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
+			0x00,0x00,   /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
+			0x0E,	     /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
+			0x2c,00,00,  /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
+			0x30,00,00,  /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
+			0x82,0x60,   /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
+			0x10,0xE3,   /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
+			0x06,	     /* Byte 56 - PCI-2 Class Base - Bridge device */ \
+			0x80,	     /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
+			0x00,	     /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
+			0x01,	     /* Byte 59 - PCI-2 class revision	1 */ \
+			0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
+
+
+#define EEPROM_LENGTH	64  /* Long Load */
+
+#define I2C_SENSOR_DEV	    0x9
+#define I2C_SENSOR_CHIP_SEL 0x4
+
+/*
+ *  Board Functions
+ */
+void set_eat_machine_checks(int a_flag);
+int get_eat_machine_checks(void);
+unsigned int get_platform(void);
+unsigned int get_device(void);
+void* memcpyb(void * dest,const void *src,size_t count);
+int process_bootflag(ulong bootflag);
+void user_led_on(void);
+void user_led_off(void);
+
+#endif	/* __COMMON_H_ */
diff --git a/u-boot/board/amirix/ap1000/flash.c b/u-boot/board/amirix/ap1000/flash.c
new file mode 100644
index 0000000..1e742e5
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/flash.c
@@ -0,0 +1,903 @@
+/**
+ * @file flash.c
+ */
+
+/*
+ * (C) Copyright 2003
+ * AMIRIX Systems Inc.
+ *
+ * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c
+ *
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI           0x98
+#define FLASH_CMD_READ_ID       0x90
+#define FLASH_CMD_RESET         0xff
+#define FLASH_CMD_BLOCK_ERASE       0x20
+#define FLASH_CMD_ERASE_CONFIRM     0xD0
+#define FLASH_CMD_WRITE         0x40
+#define FLASH_CMD_PROTECT       0x60
+#define FLASH_CMD_PROTECT_SET       0x01
+#define FLASH_CMD_PROTECT_CLEAR     0xD0
+#define FLASH_CMD_CLEAR_STATUS      0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE       0x80
+#define FLASH_STATUS_ESS        0x40
+#define FLASH_STATUS_ECLBS      0x20
+#define FLASH_STATUS_PSLBS      0x10
+#define FLASH_STATUS_VPENS      0x08
+#define FLASH_STATUS_PSS        0x04
+#define FLASH_STATUS_DPS        0x02
+#define FLASH_STATUS_R          0x01
+#define FLASH_STATUS_PROTECT        0x01
+
+#define FLASH_OFFSET_CFI        0x55
+#define FLASH_OFFSET_CFI_RESP       0x10
+#define FLASH_OFFSET_WTOUT      0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT      0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT      0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT      0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE       0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS  0x2C
+#define FLASH_OFFSET_ERASE_REGIONS  0x2D
+#define FLASH_OFFSET_PROTECT        0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI           0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char *cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
+			     uchar cmd);
+static int flash_isequal (flash_info_t * info, int sect, uchar offset,
+			  uchar cmd);
+static int flash_isset (flash_info_t * info, int sect, uchar offset,
+			uchar cmd);
+static int flash_detect_cfi (flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+				cfiword_t cword);
+static int flash_full_status_check (flash_info_t * info, ulong sector,
+				    ulong tout, char *prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+				  int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+uchar *flash_make_addr (flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->chipwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+uchar flash_read_uchar (flash_info_t * info, uchar offset)
+{
+	if (info->portwidth == FLASH_CFI_8BIT) {
+		volatile uchar *cp;
+		uchar c;
+
+		cp = flash_make_addr (info, 0, offset);
+		c = *cp;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n",
+			offset, (unsigned int) cp, c);
+#endif
+		return (c);
+
+	} else if (info->portwidth == FLASH_CFI_16BIT) {
+		volatile ushort *sp;
+		ushort s;
+		uchar c;
+
+		sp = (ushort *) flash_make_addr (info, 0, offset);
+		s = *sp;
+		c = (uchar) s;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c);
+#endif
+		return (c);
+
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset)
+{
+	if (info->portwidth == FLASH_CFI_8BIT) {
+		volatile uchar *cp;
+		uchar c0, c1;
+		ushort s;
+
+		cp = flash_make_addr (info, 0, offset);
+		c1 = cp[2];
+		c0 = cp[0];
+		s = c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s);
+#endif
+		return (s);
+
+	} else if (info->portwidth == FLASH_CFI_16BIT) {
+		volatile ushort *sp;
+		ushort s;
+		uchar c0, c1;
+
+		sp = (ushort *) flash_make_addr (info, 0, offset);
+		s = *sp;
+		c1 = (uchar) sp[1];
+		c0 = (uchar) sp[0];
+		s = c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s);
+#endif
+		return (s);
+
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long (flash_info_t * info, int sect, uchar offset)
+{
+	if (info->portwidth == FLASH_CFI_8BIT) {
+		volatile uchar *cp;
+		uchar c0, c1, c2, c3;
+		ulong l;
+
+		cp = flash_make_addr (info, 0, offset);
+		c3 = cp[6];
+		c2 = cp[4];
+		c1 = cp[2];
+		c0 = cp[0];
+		l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l);
+#endif
+		return (l);
+
+	} else if (info->portwidth == FLASH_CFI_16BIT) {
+		volatile ushort *sp;
+		uchar c0, c1, c2, c3;
+		ulong l;
+
+		sp = (ushort *) flash_make_addr (info, 0, offset);
+		c3 = (uchar) sp[3];
+		c2 = (uchar) sp[2];
+		c1 = (uchar) sp[1];
+		c0 = (uchar) sp[0];
+		l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l);
+#endif
+		return (l);
+
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+
+	size = 0;
+
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+	flash_info[0].portwidth = FLASH_CFI_16BIT;
+	flash_info[0].chipwidth = FLASH_CFI_16BIT;
+	size += flash_info[0].size = flash_get_size (CONFIG_SYS_PROGFLASH_BASE, 0);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
+	};
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].portwidth = FLASH_CFI_8BIT;
+	flash_info[1].chipwidth = FLASH_CFI_16BIT;
+	size += flash_info[1].size = flash_get_size (CONFIG_SYS_CONFFLASH_BASE, 1);
+	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
+	};
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			flash_write_cmd (info, sect, 0,
+					 FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd (info, sect, 0,
+					 FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd (info, sect, 0,
+					 FLASH_CMD_ERASE_CONFIRM);
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf (".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf ("CFI conformant FLASH (x%d device in x%d mode)",
+		(info->chipwidth << 3), (info->portwidth << 3));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i], info->protect[i] ? " (RO)" : " ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte (info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte (info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte (info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while (cnt >= info->portwidth) {
+		i = info->buffer_size > cnt ? cnt : info->buffer_size;
+		if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	/* handle the aligned part */
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte (info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte (info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte (info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword (info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check (info, sector, info->erase_blk_tout,
+				      prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			int i;
+
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect (info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check (flash_info_t * info, ulong sector, ulong tout,
+			       char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer (start) > info->erase_blk_tout) {
+			printf ("Flash %s timeout at address %lx\n", prompt,
+				info->start[sector]);
+			flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check (flash_info_t * info, ulong sector,
+				    ulong tout, char *prompt)
+{
+	int retcode;
+
+	retcode = flash_status_check (info, sector, tout, prompt);
+	if ((retcode == ERR_OK)
+	    && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf ("Flash %s error at address %lx\n", prompt,
+			info->start[sector]);
+		if (flash_isset
+		    (info, sector, 0,
+		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+			printf ("Command Sequence Error.\n");
+		} else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
+			printf ("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf ("Locking Error\n");
+		}
+		if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
+			printf ("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
+			printf ("Vpp Low Error.\n");
+	}
+	flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+{
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	/*int i; */
+	uchar *cp = (uchar *) cmdbuf;
+
+	/* for(i=0; i< info->portwidth; i++) */
+	/*  *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */
+	if (info->portwidth == FLASH_CFI_8BIT
+	    && info->chipwidth == FLASH_CFI_16BIT) {
+		cp[0] = cmd;
+	} else if (info->portwidth == FLASH_CFI_16BIT
+		   && info->chipwidth == FLASH_CFI_16BIT) {
+		cp[0] = '\0';
+		cp[1] = cmd;
+	};
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
+			     uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+
+	addr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal (flash_info_t * info, int sect, uchar offset,
+			  uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset (flash_info_t * info, int sect, uchar offset,
+			uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi (flash_info_t * info)
+{
+
+#if 0
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
+					 FLASH_CMD_CFI);
+			if (flash_isequal
+			    (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal (info, 0,
+					      FLASH_OFFSET_CFI_RESP + 1, 'R')
+			    && flash_isequal (info, 0,
+					      FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+#endif
+	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+	flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+	if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
+	    flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+	    flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
+		return 1;
+	} else {
+		return 0;
+	};
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+
+	if (flash_detect_cfi (info)) {
+#ifdef DEBUG_FLASH
+		printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
+#endif
+		size_ratio = 1;	/* info->portwidth / info->chipwidth; */
+		num_erase_regions =
+			flash_read_uchar (info,
+					  FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf ("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long (info, 0,
+					       FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_count = (tmp & 0xffff) + 1;
+			tmp >>= 16;
+			erase_region_size =
+				(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] =
+					flash_isset (info, sect_cnt,
+						     FLASH_OFFSET_PROTECT,
+						     FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+			(1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
+			size_ratio;
+		info->buffer_size =
+			(1 <<
+			 flash_read_ushort (info, 0,
+					    FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+			(tmp *
+			 (1 <<
+			  flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+			(tmp *
+			 (1 <<
+			  flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+			(tmp *
+			 (1 <<
+			  flash_read_uchar (info,
+					    FLASH_OFFSET_WMAX_TOUT))) / 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+				cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr (info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	return flash_full_status_check (info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector (flash_info_t * info, ulong addr)
+{
+	int sector;
+
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+				  int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector (info, dest);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode =
+	     flash_status_check (info, sector, info->buffer_write_tout,
+				 "write to buffer")) == ERR_OK) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd (info, sector, 0,
+				 FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+			flash_full_status_check (info, sector,
+						 info->buffer_write_tout,
+						 "buffer write");
+	}
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/u-boot/board/amirix/ap1000/init.S b/u-boot/board/amirix/ap1000/init.S
new file mode 100644
index 0000000..eac7cd3
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/init.S
@@ -0,0 +1,30 @@
+/*
+ * init.S: Stubs for ppcboot initialization
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	blr
diff --git a/u-boot/board/amirix/ap1000/pci.c b/u-boot/board/amirix/ap1000/pci.c
new file mode 100644
index 0000000..d021164
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/pci.c
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2003
+ * AMIRIX Systems Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+#define PCI_MEM_82559ER_CSR_BASE    0x30200000
+#define PCI_IO_82559ER_CSR_BASE     0x40000200
+
+/** AP1100 specific values */
+#define PSII_BASE                   0x30000000	  /**< PowerSpan II dual bridge local bus register address */
+#define PSII_CONFIG_ADDR            0x30000290	  /**< PowerSpan II Configuration Cycle Address configuration register */
+#define PSII_CONFIG_DATA            0x30000294	  /**< PowerSpan II Configuration Cycle Data register. */
+#define PSII_CONFIG_DEST_PCI2       0x01000000	  /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
+#define PSII_PCI_MEM_BASE           0x30200000	  /**< Local Bus address for start of PCI memory space on PCI2 bus. */
+#define PSII_PCI_MEM_SIZE           0x1BE00000	  /**< PCI Memory space about 510 Meg. */
+#define AP1000_SYS_MEM_START        0x00000000	  /**< System memory starts at 0. */
+#define AP1000_SYS_MEM_SIZE         0x08000000	  /**< System memory is 128 Meg. */
+
+/* static int G_verbosity_level = 1; */
+#define G_verbosity_level 1
+
+void write1 (unsigned long addr, unsigned char val)
+{
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
+			val);
+	*p = val;
+	asm ("eieio");
+}
+
+unsigned char read1 (unsigned long addr)
+{
+	unsigned char val;
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("read1: addr=%08x ", (unsigned int) addr);
+	val = *p;
+	asm ("eieio");
+	if (G_verbosity_level > 1)
+		printf ("val=%08x\n", val);
+	return val;
+}
+
+void write2 (unsigned long addr, unsigned short val)
+{
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
+			(unsigned int) addr, val,
+			((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
+
+	*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	asm ("eieio");
+}
+
+unsigned short read2 (unsigned long addr)
+{
+	unsigned short val;
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("read2: addr=%08x ", (unsigned int) addr);
+	val = *p;
+	val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	asm ("eieio");
+	if (G_verbosity_level > 1)
+		printf ("*p=%04x -> val=%04x\n",
+			((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
+	return val;
+}
+
+void write4 (unsigned long addr, unsigned long val)
+{
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
+			(unsigned int) addr, (unsigned int) val,
+			(unsigned int) (((val & 0xFF000000) >> 24) |
+					((val & 0x000000FF) << 24) |
+					((val & 0x00FF0000) >> 8) |
+					((val & 0x0000FF00) << 8)));
+
+	*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	asm ("eieio");
+}
+
+unsigned long read4 (unsigned long addr)
+{
+	unsigned long val;
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("read4: addr=%08x", (unsigned int) addr);
+
+	val = *p;
+	val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	asm ("eieio");
+
+	if (G_verbosity_level > 1)
+		printf ("*p=%04x -> val=%04x\n",
+			(unsigned int) (((val & 0xFF000000) >> 24) |
+					((val & 0x000000FF) << 24) |
+					((val & 0x00FF0000) >> 8) |
+					((val & 0x0000FF00) << 8)),
+			(unsigned int) val);
+	return val;
+}
+
+void write4be (unsigned long addr, unsigned long val)
+{
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
+			(unsigned int) val);
+	*p = val;
+	asm ("eieio");
+}
+
+/** One byte configuration write on PSII.
+ *  Currently fixes destination PCI bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Address of location for received byte.
+ *  @return Always Zero.
+ */
+static int psII_read_config_byte (struct pci_controller *hose,
+				  pci_dev_t dev, int reg, u8 * val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	*val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
+	return (0);
+}
+
+/** One byte configuration write on PSII.
+ *  Currently fixes destination bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Output byte.
+ *  @return Always Zero.
+ */
+static int psII_write_config_byte (struct pci_controller *hose,
+				   pci_dev_t dev, int reg, u8 val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
+
+	return (0);
+}
+
+/** One word (16 bit) configuration read on PSII.
+ *  Currently fixes destination PCI bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Address of location for received word.
+ *  @return Always Zero.
+ */
+static int psII_read_config_word (struct pci_controller *hose,
+				  pci_dev_t dev, int reg, u16 * val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	*val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
+	return (0);
+}
+
+/** One word (16 bit) configuration write on PSII.
+ *  Currently fixes destination bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Output word.
+ *  @return Always Zero.
+ */
+static int psII_write_config_word (struct pci_controller *hose,
+				   pci_dev_t dev, int reg, u16 val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
+
+	return (0);
+}
+
+/** One DWord (32 bit) configuration read on PSII.
+ *  Currently fixes destination PCI bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Address of location for received byte.
+ *  @return Always Zero.
+ */
+static int psII_read_config_dword (struct pci_controller *hose,
+				   pci_dev_t dev, int reg, u32 * val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	*val = read4 (PSII_CONFIG_DATA);
+	return (0);
+}
+
+/** One DWord (32 bit) configuration write on PSII.
+ *  Currently fixes destination bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Output Dword.
+ *  @return Always Zero.
+ */
+static int psII_write_config_dword (struct pci_controller *hose,
+				    pci_dev_t dev, int reg, u32 val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	write4 (PSII_CONFIG_DATA, (unsigned long) val);
+
+	return (0);
+}
+
+static struct pci_config_table ap1000_config_table[] = {
+#ifdef CONFIG_AP1000
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_BUS (CONFIG_SYS_ETH_DEV_FN), PCI_DEV (CONFIG_SYS_ETH_DEV_FN),
+	 PCI_FUNC (CONFIG_SYS_ETH_DEV_FN),
+	 pci_cfgfunc_config_device,
+	 {CONFIG_SYS_ETH_IOBASE, CONFIG_SYS_ETH_MEMBASE,
+	  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+#endif
+	{}
+};
+
+static struct pci_controller psII_hose = {
+      config_table:ap1000_config_table,
+};
+
+void pci_init_board (void)
+{
+	struct pci_controller *hose = &psII_hose;
+
+	/*
+	 * Register the hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System memory space */
+	pci_set_region (hose->regions + 0,
+			AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
+			AP1000_SYS_MEM_SIZE,
+			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* PCI Memory space */
+	pci_set_region (hose->regions + 1,
+			PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
+			PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+	/* No IO Memory space  - for now */
+
+	pci_set_ops (hose,
+		     psII_read_config_byte,
+		     psII_read_config_word,
+		     psII_read_config_dword,
+		     psII_write_config_byte,
+		     psII_write_config_word, psII_write_config_dword);
+
+	hose->region_count = 2;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+}
diff --git a/u-boot/board/amirix/ap1000/powerspan.c b/u-boot/board/amirix/ap1000/powerspan.c
new file mode 100644
index 0000000..55451b1
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/powerspan.c
@@ -0,0 +1,750 @@
+/**
+ * @file powerspan.c Source file for PowerSpan II code.
+ */
+
+/*
+ * (C) Copyright 2005
+ * AMIRIX Systems Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include "powerspan.h"
+#define tolower(x) x
+#include "ap1000.h"
+
+#ifdef INCLUDE_PCI
+
+/** Write one byte with byte swapping.
+  * @param  addr [IN] the address to write to
+  * @param  val  [IN] the value to write
+  */
+void write1 (unsigned long addr, unsigned char val)
+{
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("write1: addr=%08x val=%02x\n", addr, val);
+	}
+#endif
+	*p = val;
+	PSII_SYNC ();
+}
+
+/** Read one byte with byte swapping.
+  * @param  addr  [IN] the address to read from
+  * @return the value at addr
+  */
+unsigned char read1 (unsigned long addr)
+{
+	unsigned char val;
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+	val = *p;
+	PSII_SYNC ();
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("read1: addr=%08x val=%02x\n", addr, val);
+	}
+#endif
+	return val;
+}
+
+/** Write one 2-byte word with byte swapping.
+  * @param  addr  [IN] the address to write to
+  * @param  val   [IN] the value to write
+  */
+void write2 (unsigned long addr, unsigned short val)
+{
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val,
+			((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
+	}
+#endif
+	*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	PSII_SYNC ();
+}
+
+/** Read one 2-byte word with byte swapping.
+  * @param  addr  [IN] the address to read from
+  * @return the value at addr
+  */
+unsigned short read2 (unsigned long addr)
+{
+	unsigned short val;
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+	val = *p;
+	val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	PSII_SYNC ();
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
+			val);
+	}
+#endif
+	return val;
+}
+
+/** Write one 4-byte word with byte swapping.
+  * @param  addr  [IN] the address to write to
+  * @param  val   [IN] the value to write
+  */
+void write4 (unsigned long addr, unsigned long val)
+{
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
+			((val & 0xFF000000) >> 24) |
+			((val & 0x000000FF) << 24) |
+			((val & 0x00FF0000) >>  8) |
+			((val & 0x0000FF00) <<  8));
+	}
+#endif
+	*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	PSII_SYNC ();
+}
+
+/** Read one 4-byte word with byte swapping.
+  * @param  addr  [IN] the address to read from
+  * @return the value at addr
+  */
+unsigned long read4 (unsigned long addr)
+{
+	unsigned long val;
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	val = *p;
+	val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	PSII_SYNC ();
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
+			val);
+	}
+#endif
+	return val;
+}
+
+int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
+		   unsigned long *val)
+{
+	unsigned int conAdrVal;
+	unsigned int conDataReg = REG_CONFIG_DATA;
+	unsigned int status;
+	int ret_val = 0;
+
+
+	/* DEST bit hardcoded to 1: local pci is PCI-2 */
+	/* TYPE bit is hardcoded to 1: all config cycles are local */
+	conAdrVal = (1 << 24)
+		| ((bus & 0xFF) << 16)
+		| ((dev & 0xFF) << 11)
+		| ((fn & 0x07) << 8)
+		| (reg & 0xFC);
+
+	/* clear any pending master aborts */
+	write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+
+	/* Load the conAdrVal value first, then read from pb_conf_data */
+	write4 (REG_CONFIG_ADDRESS, conAdrVal);
+	PSII_SYNC ();
+
+
+	/* Note: documentation does not match the pspan library code */
+	/* Note: *pData comes back as -1 if device is not present */
+	switch (width) {
+	case 4:
+		*(unsigned int *) val = read4 (conDataReg);
+		break;
+	case 2:
+		*(unsigned short *) val = read2 (conDataReg);
+		break;
+	case 1:
+		*(unsigned char *) val = read1 (conDataReg);
+		break;
+	default:
+		ret_val = ILLEGAL_REG_OFFSET;
+		break;
+	}
+	PSII_SYNC ();
+
+	/* clear any pending master aborts */
+	status = read4 (REG_P1_CSR);
+	if (status & CLEAR_MASTER_ABORT) {
+		ret_val = NO_DEVICE_FOUND;
+		write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+	}
+
+	return ret_val;
+}
+
+
+int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
+		    unsigned long val)
+{
+	unsigned int conAdrVal;
+	unsigned int conDataReg = REG_CONFIG_DATA;
+	unsigned int status;
+	int ret_val = 0;
+
+
+	/* DEST bit hardcoded to 1: local pci is PCI-2 */
+	/* TYPE bit is hardcoded to 1: all config cycles are local */
+	conAdrVal = (1 << 24)
+		| ((bus & 0xFF) << 16)
+		| ((dev & 0xFF) << 11)
+		| ((fn & 0x07) << 8)
+		| (reg & 0xFC);
+
+	/* clear any pending master aborts */
+	write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+
+	/* Load the conAdrVal value first, then read from pb_conf_data */
+	write4 (REG_CONFIG_ADDRESS, conAdrVal);
+	PSII_SYNC ();
+
+
+	/* Note: documentation does not match the pspan library code */
+	/* Note: *pData comes back as -1 if device is not present */
+	switch (width) {
+	case 4:
+		write4 (conDataReg, val);
+		break;
+	case 2:
+		write2 (conDataReg, val);
+		break;
+	case 1:
+		write1 (conDataReg, val);
+		break;
+	default:
+		ret_val = ILLEGAL_REG_OFFSET;
+		break;
+	}
+	PSII_SYNC ();
+
+	/* clear any pending master aborts */
+	status = read4 (REG_P1_CSR);
+	if (status & CLEAR_MASTER_ABORT) {
+		ret_val = NO_DEVICE_FOUND;
+		write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+	}
+
+	return ret_val;
+}
+
+
+int pci_read_config_byte (int bus, int dev, int fn, int reg,
+			  unsigned char *val)
+{
+	unsigned long read_val;
+	int ret_val;
+
+	ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val);
+	*val = read_val & 0xFF;
+
+	return ret_val;
+}
+
+int pci_write_config_byte (int bus, int dev, int fn, int reg,
+			   unsigned char val)
+{
+	return PCIWriteConfig (bus, dev, fn, reg, 1, val);
+}
+
+int pci_read_config_word (int bus, int dev, int fn, int reg,
+			  unsigned short *val)
+{
+	unsigned long read_val;
+	int ret_val;
+
+	ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val);
+	*val = read_val & 0xFFFF;
+
+	return ret_val;
+}
+
+int pci_write_config_word (int bus, int dev, int fn, int reg,
+			   unsigned short val)
+{
+	return PCIWriteConfig (bus, dev, fn, reg, 2, val);
+}
+
+int pci_read_config_dword (int bus, int dev, int fn, int reg,
+			   unsigned long *val)
+{
+	return PCIReadConfig (bus, dev, fn, reg, 4, val);
+}
+
+int pci_write_config_dword (int bus, int dev, int fn, int reg,
+			    unsigned long val)
+{
+	return PCIWriteConfig (bus, dev, fn, reg, 4, val);
+}
+
+#endif /* INCLUDE_PCI */
+
+int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
+	       unsigned char theChipSel, unsigned char *theValue, int RWFlag)
+{
+	int ret_val = 0;
+	unsigned int reg_value;
+
+	reg_value = PowerSpanRead (REG_I2C_CSR);
+
+	if (reg_value & I2C_CSR_ACT) {
+		printf ("Error: I2C busy\n");
+		ret_val = I2C_BUSY;
+	} else {
+		reg_value = ((theI2CAddress & 0xFF) << 24)
+			| ((theDevCode & 0x0F) << 12)
+			| ((theChipSel & 0x07) << 9)
+			| I2C_CSR_ERR;
+		if (RWFlag == I2C_WRITE) {
+			reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16);
+		}
+
+		PowerSpanWrite (REG_I2C_CSR, reg_value);
+		udelay (1);
+
+		do {
+			reg_value = PowerSpanRead (REG_I2C_CSR);
+
+			if ((reg_value & I2C_CSR_ACT) == 0) {
+				if (reg_value & I2C_CSR_ERR) {
+					ret_val = I2C_ERR;
+				} else {
+					*theValue =
+						(reg_value & I2C_CSR_DATA) >>
+						16;
+				}
+			}
+		} while (reg_value & I2C_CSR_ACT);
+	}
+
+	return ret_val;
+}
+
+int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
+{
+	return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
+			  theValue, I2C_READ);
+}
+
+int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
+{
+	return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
+			  &theValue, I2C_WRITE);
+}
+
+int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd;
+	int ret_val = 0;
+	unsigned int address = 0;
+	unsigned char value = 1;
+	unsigned char read_value;
+	int ii;
+	int error = 0;
+	unsigned char *mem_ptr;
+	unsigned char default_eeprom[] = EEPROM_DEFAULT;
+
+	if (argc < 2) {
+		goto usage;
+	}
+
+	cmd = argv[1][0];
+	if (argc > 2) {
+		address = simple_strtoul (argv[2], NULL, 16);
+		if (argc > 3) {
+			value = simple_strtoul (argv[3], NULL, 16) & 0xFF;
+		}
+	}
+
+	switch (cmd) {
+	case 'r':
+		if (address > 256) {
+			printf ("Illegal Address\n");
+			goto usage;
+		}
+		printf ("@0x%x: ", address);
+		for (ii = 0; ii < value; ii++) {
+			if (EEPROMRead (address + ii, &read_value) !=
+			    0) {
+				printf ("Read Error\n");
+			} else {
+				printf ("0x%02x ", read_value);
+			}
+
+			if (((ii + 1) % 16) == 0) {
+				printf ("\n");
+			}
+		}
+		printf ("\n");
+		break;
+	case 'w':
+		if (address > 256) {
+			printf ("Illegal Address\n");
+			goto usage;
+		}
+		if (argc < 4) {
+			goto usage;
+		}
+		if (EEPROMWrite (address, value) != 0) {
+			printf ("Write Error\n");
+		}
+		break;
+	case 'g':
+		if (argc != 3) {
+			goto usage;
+		}
+		mem_ptr = (unsigned char *) address;
+		for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+		     ii++) {
+			if (EEPROMRead (ii, &read_value) != 0) {
+				printf ("Read Error\n");
+				error = 1;
+			} else {
+				*mem_ptr = read_value;
+				mem_ptr++;
+			}
+		}
+		break;
+	case 'p':
+		if (argc != 3) {
+			goto usage;
+		}
+		mem_ptr = (unsigned char *) address;
+		for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+		     ii++) {
+			if (EEPROMWrite (ii, *mem_ptr) != 0) {
+				printf ("Write Error\n");
+				error = 1;
+			}
+
+			mem_ptr++;
+		}
+		break;
+	case 'd':
+		if (argc != 2) {
+			goto usage;
+		}
+		for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+		     ii++) {
+			if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
+				printf ("Write Error\n");
+				error = 1;
+			}
+		}
+		break;
+	default:
+		goto usage;
+	}
+
+	goto done;
+      usage:
+	printf ("Usage:\n%s\n", cmdtp->help);
+
+      done:
+	return ret_val;
+
+}
+
+U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
+	    "read/write/copy to/from the PowerSpan II eeprom",
+	    "eeprom r OFF [NUM]\n"
+	    "    - read NUM words starting at OFF\n"
+	    "eeprom w OFF VAL\n"
+	    "    - write word VAL at offset OFF\n"
+	    "eeprom g ADD\n"
+	    "    - store contents of eeprom at address ADD\n"
+	    "eeprom p ADD\n"
+	    "    - put data stored at address ADD into the eeprom\n"
+	    "eeprom d\n" "    - return eeprom to default contents");
+
+unsigned int PowerSpanRead (unsigned int theOffset)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+	unsigned int ret_val;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanRead: offset=%08x ", theOffset);
+	}
+#endif
+	ret_val = *ptr;
+	PSII_SYNC ();
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("value=%08x\n", ret_val);
+	}
+#endif
+
+	return ret_val;
+}
+
+void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
+			theValue);
+	}
+#endif
+	*ptr = theValue;
+	PSII_SYNC ();
+}
+
+/**
+ * Sets the indicated bits in the indicated register.
+ * @param theOffset [IN] the register to access.
+ * @param theMask   [IN] bits set in theMask will be set in the register.
+ */
+void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+	unsigned int register_value;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
+			theOffset, theMask);
+	}
+#endif
+	register_value = *ptr;
+	PSII_SYNC ();
+
+	register_value |= theMask;
+	*ptr = register_value;
+	PSII_SYNC ();
+}
+
+/**
+ * Clears the indicated bits in the indicated register.
+ * @param theOffset [IN] the register to access.
+ * @param theMask   [IN] bits set in theMask will be cleared in the register.
+ */
+void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+	unsigned int register_value;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
+			theOffset, theMask);
+	}
+#endif
+	register_value = *ptr;
+	PSII_SYNC ();
+
+	register_value &= ~theMask;
+	*ptr = register_value;
+	PSII_SYNC ();
+}
+
+/**
+ * Configures a slave image on the local bus, based on the parameters and some hardcoded system values.
+ * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus.  Thus, they
+ *  are outgoing from the standpoint of the local bus.
+ * @param theImageIndex    [IN] the PowerSpan II image to set (assumed to be 0-7).
+ * @param theBlockSize     [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]).
+ * @param theMemIOFlag     [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
+ * @param theEndianness    [IN] the endian bits for the image (already shifted, use defines).
+ * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
+ * @param thePCIBaseAddr   [IN] the PCI address for the image (assumed to be valid with provided block size).
+ */
+int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
+		   int theMemIOFlag, int theEndianness,
+		   unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
+{
+	unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
+	unsigned int reg_value = 0;
+
+	/* Make sure that the Slave Image is disabled */
+	PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
+			    PB_SLAVE_CSR_IMG_EN);
+
+	/* Setup the mask required for requested PB Slave Image configuration */
+	reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
+	if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) {
+		reg_value |= PB_SLAVE_CSR_MEM_IO;
+	}
+
+	/* hardcoding the following:
+	   TA_EN = 1
+	   MD_EN = 0
+	   MODE  = 0
+	   PRKEEP = 0
+	   RD_AMT = 0
+	 */
+	PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value);
+
+	/* these values are not checked by software */
+	PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr);
+	PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
+
+	/* Enable the Slave Image */
+	PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
+			  PB_SLAVE_CSR_IMG_EN);
+
+	return 0;
+}
+
+/**
+ * Configures a target image on the local bus, based on the parameters and some hardcoded system values.
+ * Target Images are used when the PowerSpan II is acting as a target for an access.  Thus, they
+ *  are incoming from the standpoint of the local bus.
+ * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI
+ *  base address will not be updated; makes sense given that the hosts own memory should be mapped to
+ *  PCI address 0x00000000.
+ * @param theImageIndex    [IN] the PowerSpan II image to set.
+ * @param theBlockSize     [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]).
+ * @param theMemIOFlag     [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
+ * @param theEndianness    [IN] the endian bits for the image (already shifted, use defines).
+ * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
+ * @param thePCIBaseAddr   [IN] the PCI address for the image (assumed to be valid with provided block size).
+ */
+int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
+		    int theMemIOFlag, int theEndianness,
+		    unsigned int theLocalBaseAddr,
+		    unsigned int thePCIBaseAddr)
+{
+	unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
+	unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
+	unsigned int reg_value = 0;
+
+	/* Make sure that the Slave Image is disabled */
+	PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
+			    PB_SLAVE_CSR_IMG_EN);
+
+	/* Setup the mask required for requested PB Slave Image configuration */
+	reg_value =
+		PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
+		PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
+	if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
+		reg_value |= PX_TGT_MEM_IO;
+	}
+
+	/* hardcoding the following:
+	   TA_EN = 1
+	   BAR_EN = 1
+	   MD_EN = 0
+	   MODE  = 0
+	   DEST  = 0
+	   RTT = 01010
+	   GBL = 0
+	   CI = 0
+	   WTT = 00010
+	   PRKEEP = 0
+	   MRA = 0
+	   RD_AMT = 0
+	 */
+	PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
+
+	PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
+			theLocalBaseAddr);
+
+	if (thePCIBaseAddr != (unsigned int) NULL) {
+		PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
+				thePCIBaseAddr);
+	}
+
+	/* Enable the Slave Image */
+	PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
+			  PB_SLAVE_CSR_IMG_EN);
+
+	return 0;
+}
+
+int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd;
+	int ret_val = 1;
+	unsigned int image_index;
+	unsigned int block_size;
+	unsigned int mem_io;
+	unsigned int local_addr;
+	unsigned int pci_addr;
+	int endianness;
+
+	if (argc != 8) {
+		goto usage;
+	}
+
+	cmd = argv[1][0];
+	image_index = simple_strtoul (argv[2], NULL, 16);
+	block_size = simple_strtoul (argv[3], NULL, 16);
+	mem_io = simple_strtoul (argv[4], NULL, 16);
+	endianness = argv[5][0];
+	local_addr = simple_strtoul (argv[6], NULL, 16);
+	pci_addr = simple_strtoul (argv[7], NULL, 16);
+
+
+	switch (cmd) {
+	case 'i':
+		if (tolower (endianness) == 'b') {
+			endianness = PX_TGT_CSR_BIG_END;
+		} else if (tolower (endianness) == 'l') {
+			endianness = PX_TGT_CSR_TRUE_LEND;
+		} else {
+			goto usage;
+		}
+		SetTargetImage (image_index, block_size, mem_io,
+				endianness, local_addr, pci_addr);
+		break;
+	case 'o':
+		if (tolower (endianness) == 'b') {
+			endianness = PB_SLAVE_CSR_BIG_END;
+		} else if (tolower (endianness) == 'l') {
+			endianness = PB_SLAVE_CSR_TRUE_LEND;
+		} else {
+			goto usage;
+		}
+		SetSlaveImage (image_index, block_size, mem_io,
+			       endianness, local_addr, pci_addr);
+		break;
+	default:
+		goto usage;
+	}
+
+	goto done;
+usage:
+	printf ("Usage:\n%s\n", cmdtp->help);
+
+done:
+	return ret_val;
+}
diff --git a/u-boot/board/amirix/ap1000/powerspan.h b/u-boot/board/amirix/ap1000/powerspan.h
new file mode 100644
index 0000000..4e9a8c1
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/powerspan.h
@@ -0,0 +1,170 @@
+/**
+ * @file powerspan.h Header file for PowerSpan II code.
+ */
+
+/*
+ * (C) Copyright 2005
+ * AMIRIX Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef POWERSPAN_H
+#define POWERSPAN_H
+
+#define CLEAR_MASTER_ABORT 0xdeadbeef
+#define NO_DEVICE_FOUND     -1
+#define ILLEGAL_REG_OFFSET  -2
+#define I2C_BUSY            -3
+#define I2C_ERR             -4
+
+#define REG_P1_CSR          0x004
+#define REGS_P1_BST         0x018
+#define REG_P1_ERR_CSR      0x150
+#define REG_P1_MISC_CSR     0x160
+#define REGS_P1_TGT_CSR     0x100
+#define REGS_P1_TGT_TADDR   0x104
+#define REGS_PB_SLAVE_CSR   0x200
+#define REGS_PB_SLAVE_TADDR 0x204
+#define REGS_PB_SLAVE_BADDR 0x208
+#define REG_CONFIG_ADDRESS  0x290
+#define REG_CONFIG_DATA     0x294
+#define REG_PB_ERR_CSR      0x2B0
+#define REG_PB_MISC_CSR     0x2C0
+#define REG_MISC_CSR        0x400
+#define REG_I2C_CSR         0x408
+#define REG_RESET_CSR       0x40C
+#define REG_ISR0            0x410
+#define REG_ISR1            0x414
+#define REG_IER0            0x418
+#define REG_MBOX_MAP        0x420
+#define REG_HW_MAP          0x42C
+#define REG_IDR             0x444
+
+#define CSR_MEMORY_SPACE_ENABLE 0x00000002
+#define CSR_PCI_MASTER_ENABLE   0x00000004
+
+#define P1_BST_OFF  0x04
+
+#define PX_ERR_ERR_STATUS   0x01000000
+
+#define PX_MISC_CSR_MAX_RETRY_MASK  0x00000F00
+#define PX_MISC_CSR_MAX_RETRY       0x00000F00
+#define PX_MISC_REG_BAR_ENABLE      0x00008000
+#define PB_MISC_TEA_ENABLE          0x00000010
+#define PB_MISC_MAC_TEA             0x00000040
+
+#define P1_TGT_IMAGE_OFF    0x010
+#define PX_TGT_CSR_IMG_EN   0x80000000
+#define PX_TGT_CSR_TA_EN    0x40000000
+#define PX_TGT_CSR_BAR_EN   0x20000000
+#define PX_TGT_CSR_MD_EN    0x10000000
+#define PX_TGT_CSR_MODE     0x00800000
+#define PX_TGT_CSR_DEST     0x00400000
+#define PX_TGT_CSR_MEM_IO   0x00200000
+#define PX_TGT_CSR_GBL      0x00080000
+#define PX_TGT_CSR_CL       0x00040000
+#define PX_TGT_CSR_PRKEEP   0x00000080
+
+#define PX_TGT_CSR_BS_MASK      0x0F000000
+#define PX_TGT_MEM_IO           0x00200000
+#define PX_TGT_CSR_RTT_MASK     0x001F0000
+#define PX_TGT_CSR_RTT_READ     0x000A0000
+#define PX_TGT_CSR_WTT_MASK     0x00001F00
+#define PX_TGT_CSR_WTT_WFLUSH   0x00000200
+#define PX_TGT_CSR_END_MASK     0x00000060
+#define PX_TGT_CSR_BIG_END      0x00000040
+#define PX_TGT_CSR_TRUE_LEND    0x00000060
+#define PX_TGT_CSR_RDAMT_MASK   0x00000007
+
+#define PX_TGT_CSR_BS_64MB  0xa
+#define PX_TGT_CSR_BS_16MB  0x8
+
+#define PX_TGT_USE_MEM_IO   1
+#define PX_TGT_NOT_MEM_IO   0
+
+#define PB_SLAVE_IMAGE_OFF  0x010
+#define PB_SLAVE_CSR_IMG_EN 0x80000000
+#define PB_SLAVE_CSR_TA_EN  0x40000000
+#define PB_SLAVE_CSR_MD_EN  0x20000000
+#define PB_SLAVE_CSR_MODE   0x00800000
+#define PB_SLAVE_CSR_DEST   0x00400000
+#define PB_SLAVE_CSR_MEM_IO 0x00200000
+#define PB_SLAVE_CSR_PRKEEP 0x00000080
+
+#define PB_SLAVE_CSR_BS_MASK    0x1F000000
+#define PB_SLAVE_CSR_END_MASK   0x00000060
+#define PB_SLAVE_CSR_BIG_END    0x00000040
+#define PB_SLAVE_CSR_TRUE_LEND  0x00000060
+#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
+
+#define PB_SLAVE_USE_MEM_IO 1
+#define PB_SLAVE_NOT_MEM_IO 0
+
+
+#define MISC_CSR_PCI1_LOCK  0x00000080
+
+#define I2C_CSR_ADDR      0xFF000000  /* Specifies I2C Device Address to be Accessed */
+#define I2C_CSR_DATA      0x00FF0000  /* Specifies the Required Data for a Write */
+#define I2C_CSR_DEV_CODE  0x0000F000  /* Device Select. I2C 4-bit Device Code */
+#define I2C_CSR_CS        0x00000E00  /* Chip Select */
+#define I2C_CSR_RW        0x00000100  /* Read/Write */
+#define I2C_CSR_ACT       0x00000080  /* I2C Interface Active */
+#define I2C_CSR_ERR       0x00000040  /* Error */
+
+#define I2C_EEPROM_DEV      0xa
+#define I2C_EEPROM_CHIP_SEL 0
+
+#define I2C_READ    0
+#define I2C_WRITE   1
+
+#define RESET_CSR_EEPROM_LOAD 0x00000010
+
+#define ISR_CLEAR_ALL   0xFFFFFFFF
+
+#define IER0_DMA_INTS_EN    0x0F000000
+#define IER0_PCI_1_EN       0x00400000
+#define IER0_HW_INTS_EN     0x003F0000
+#define IER0_MB_INTS_EN     0x000000FF
+#define IER0_DEFAULT        (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
+
+#define MBOX_MAP_TO_INT4    0xCCCCCCCC
+
+#define HW_MAP_HW4_TO_INT4  0x000C0000
+
+#define IDR_PCI_A_OUT   0x40000000
+#define IDR_MBOX_OUT    0x10000000
+
+
+int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
+int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
+int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
+int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
+int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
+int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
+
+unsigned int PowerSpanRead(unsigned int theOffset);
+void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
+
+int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
+
+int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
+int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
+
+int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
+int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
+
+#endif
diff --git a/u-boot/board/amirix/ap1000/serial.c b/u-boot/board/amirix/ap1000/serial.c
new file mode 100644
index 0000000..87003be
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/serial.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2002
+ * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <config.h>
+
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) CONFIG_SYS_NS16550_COM1, (NS16550_t) CONFIG_SYS_NS16550_COM2 };
+
+#undef CONFIG_SYS_DUART_CHAN
+#define CONFIG_SYS_DUART_CHAN gComPort
+static int gComPort = 0;
+
+int serial_init (void)
+{
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+	(void) NS16550_init (COM_PORTS[0], clock_divisor);
+	gComPort = 0;
+
+	return 0;
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n') {
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
+	}
+
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/u-boot/board/amirix/ap1000/u-boot.lds b/u-boot/board/amirix/ap1000/u-boot.lds
new file mode 100644
index 0000000..356d019
--- /dev/null
+++ b/u-boot/board/amirix/ap1000/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/amirix/ap1000/init.o		(.text)
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/apollon/Makefile b/u-boot/board/apollon/Makefile
new file mode 100644
index 0000000..ce41efc
--- /dev/null
+++ b/u-boot/board/apollon/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= apollon.o mem.o sys_info.o
+SOBJS	:= lowlevel_init.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/apollon/apollon.c b/u-boot/board/apollon/apollon.c
new file mode 100644
index 0000000..4768f58
--- /dev/null
+++ b/u-boot/board/apollon/apollon.c
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics.
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <asm/mach-types.h>
+
+void wait_for_command_complete(unsigned int wd_base);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define write_config_reg(reg, value)					\
+do {									\
+	writeb(value, reg);						\
+} while (0)
+
+#define mask_config_reg(reg, mask)					\
+do {									\
+	char value = readb(reg) & ~(mask);				\
+	writeb(value, reg);						\
+} while (0)
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+	__asm__("1:\n" "subs %0, %1, #1\n"
+		  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+	gpmc_init();		/* in SRAM or SDRM, finish GPMC */
+
+	gd->bd->bi_arch_number = 919;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with sram stack.
+ **********************************************************/
+void s_init(void)
+{
+	watchdog_init();
+	set_muxconf_regs();
+	delay(100);
+
+	peripheral_enable();
+	icache_enable();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r(void)
+{
+	return (0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
+	 * The ROM takes care of the secure one. Of the 3 GP ones,
+	 * 1 can reset us directly, the other 2 only generate MPU interrupts.
+	 */
+	__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+	wait_for_command_complete(WD2_BASE);
+	__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+
+#define MPU_WD_CLOCKED 1
+#if MPU_WD_CLOCKED
+	/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
+	__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
+	wait_for_command_complete(WD3_BASE);
+	__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
+
+	__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
+	wait_for_command_complete(WD4_BASE);
+	__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
+#endif
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+	int pending = 1;
+	do {
+		pending = __raw_readl(wd_base + WWPS);
+	} while (pending);
+}
+
+/*******************************************************************
+ * Routine:board_eth_init
+ * Description: take the Ethernet controller out of reset and wait
+ *		   for the EEPROM load to complete.
+ ******************************************************************/
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	int cnt = 20;
+
+	__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2);	/*protect->gpio74 */
+
+	__raw_writew(0x0, LAN_RESET_REGISTER);
+	do {
+		__raw_writew(0x1, LAN_RESET_REGISTER);
+		udelay(100);
+		if (cnt == 0)
+			goto eth_reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+	cnt = 20;
+
+	do {
+		__raw_writew(0x0, LAN_RESET_REGISTER);
+		udelay(100);
+		if (cnt == 0)
+			goto eth_reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+	udelay(1000);
+
+	mask_config_reg(ETH_CONTROL_REG, 0x01);
+	udelay(1000);
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+eth_reset_err_out:
+#endif
+	return rc;
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init(void)
+{
+	unsigned int size0 = 0, size1 = 0;
+	u32 mtype, btype, rev = 0, cpu = 0;
+#define NOT_EARLY 0
+
+	btype = get_board_type();
+	mtype = get_mem_type();
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+
+	display_board_info(btype);
+
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+		/* init other chip select */
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
+	}
+
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
+	gd->bd->bi_dram[1].size = size1;
+#endif
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ *              specific to the hardware
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+	muxSetupSDRC();
+	muxSetupGPMC();
+	muxSetupUsb0();		/* USB Device */
+	muxSetupUsbHost();	/* USB Host */
+	muxSetupUART1();
+	muxSetupLCD();
+	muxSetupMMCSD();
+	muxSetupTouchScreen();
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void peripheral_enable(void)
+{
+	unsigned int v, if_clks = 0, func_clks = 0;
+
+	/* Enable GP2 timer. */
+	if_clks |= BIT4 | BIT3;
+	func_clks |= BIT4 | BIT3;
+	/* Sys_clk input OMAP2420_GPT2 */
+	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
+	__raw_writel(v, CM_CLKSEL2_CORE);
+	__raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CONFIG_SYS_NS16550
+	/* Enable UART1 clock */
+	func_clks |= BIT21;
+	if_clks |= BIT21;
+#endif
+	/* Interface clocks on */
+	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
+	__raw_writel(v, CM_ICLKEN1_CORE);
+	/* Functional Clocks on */
+	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
+	__raw_writel(v, CM_FCLKEN1_CORE);
+	delay(1000);
+
+#ifndef KERNEL_UPDATED
+	{
+#define V1 0xffffffff
+#define V2 0x00000007
+
+		__raw_writel(V1, CM_FCLKEN1_CORE);
+		__raw_writel(V2, CM_FCLKEN2_CORE);
+		__raw_writel(V1, CM_ICLKEN1_CORE);
+		__raw_writel(V1, CM_ICLKEN2_CORE);
+	}
+#endif
+}
+
+/****************************************
+ * Routine: muxSetupUsb0   (ostboot)
+ * Description: Setup usb muxing
+ *****************************************/
+void muxSetupUsb0(void)
+{
+	mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
+}
+
+/****************************************
+ * Routine: muxSetupUSBHost   (ostboot)
+ * Description: Setup USB Host muxing
+ *****************************************/
+void muxSetupUsbHost(void)
+{
+	/* V19 */
+	write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
+	/* W20 */
+	write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
+	/* N14 */
+	write_config_reg(CONTROL_PADCONF_GPIO69, 3);
+	/* P15 */
+	write_config_reg(CONTROL_PADCONF_GPIO70, 3);
+	/* L18 */
+	write_config_reg(CONTROL_PADCONF_GPIO102, 3);
+	/* L19 */
+	write_config_reg(CONTROL_PADCONF_GPIO103, 3);
+	/* K15 */
+	write_config_reg(CONTROL_PADCONF_GPIO104, 3);
+	/* K14 */
+	write_config_reg(CONTROL_PADCONF_GPIO105, 3);
+}
+
+/****************************************
+ * Routine: muxSetupUART1  (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+void muxSetupUART1(void)
+{
+	/* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
+	/* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
+	/* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
+	/* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
+}
+
+/****************************************
+ * Routine: muxSetupLCD   (ostboot)
+ * Description: Setup lcd muxing
+ *****************************************/
+void muxSetupLCD(void)
+{
+	/* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
+	/* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
+	/* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
+	/* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
+	/* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
+	/* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
+	/* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
+	/* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
+	/* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
+	/* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
+	/* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
+	/* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
+	/* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
+	/* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
+	/* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
+	/* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
+	/* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
+	/* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
+	/* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
+	/* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
+	/* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
+	/* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
+}
+
+/****************************************
+ * Routine: muxSetupMMCSD (ostboot)
+ * Description: set up MMC muxing
+ *****************************************/
+void muxSetupMMCSD(void)
+{
+	/* SDMMC_CLKI pin configuration,  PIN = H15, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
+	/* SDMMC_CLKO pin configuration,  PIN = G19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
+	/* SDMMC_CMD pin configuration,   PIN = H18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
+	/* SDMMC_DAT0 pin configuration,  PIN = F20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
+	/* SDMMC_DAT1 pin configuration,  PIN = H14, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
+	/* SDMMC_DAT2 pin configuration,  PIN = E19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
+	/* SDMMC_DAT3 pin configuration,  PIN = D19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
+	/* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
+	/* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
+	/* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
+	/* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
+	/* SDMMC_CDIR pin configuration,  PIN = G18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
+}
+
+/******************************************
+ * Routine: muxSetupTouchScreen (ostboot)
+ * Description:  Set up touch screen muxing
+ *******************************************/
+void muxSetupTouchScreen(void)
+{
+	/* SPI1_CLK pin configuration,  PIN = U18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
+	/* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
+	/* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
+	/* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
+#define CONTROL_PADCONF_GPIO85	CONTROL_PADCONF_SPI1_NCS1
+	/* PEN_IRQ pin configuration,   PIN = N15, Mode = 3, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_GPIO85, 3);
+}
+
+/***************************************************************
+ * Routine: muxSetupGPMC (ostboot)
+ * Description: Configures balls which cam up in protected mode
+ ***************************************************************/
+void muxSetupGPMC(void)
+{
+	/* gpmc_io_dir, MCR */
+	volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
+	*MCR = 0x19000000;
+
+	/* NOR FLASH CS0 */
+	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
+	write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
+	/* MPDB(Multi Port Debug Port) CS1 */
+	/* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
+	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
+	/* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
+	/* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
+	/* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
+	/* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
+	/* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
+}
+
+/****************************************************************
+ * Routine: muxSetupSDRC  (ostboot)
+ * Description: Configures balls which come up in protected mode
+ ****************************************************************/
+void muxSetupSDRC(void)
+{
+	/* It's set by IPL */
+}
diff --git a/u-boot/board/apollon/config.mk b/u-boot/board/apollon/config.mk
new file mode 100644
index 0000000..66005d4
--- /dev/null
+++ b/u-boot/board/apollon/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2005-2007
+# Samsung Electronics
+#
+# Samsung December board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# December has 1 bank of 128MB mDDR-SDRAM on CS0
+# December has 1 bank of  00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x83e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+#CONFIG_SYS_TEXT_BASE = 0x40270000
+
+# Handy to get symbols to debug ROM version.
+#CONFIG_SYS_TEXT_BASE = 0x0
+#CONFIG_SYS_TEXT_BASE = 0x08000000
diff --git a/u-boot/board/apollon/lowlevel_init.S b/u-boot/board/apollon/lowlevel_init.S
new file mode 100644
index 0000000..f066fe4
--- /dev/null
+++ b/u-boot/board/apollon/lowlevel_init.S
@@ -0,0 +1,337 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include "mem.h"
+
+#define APOLLON_CS0_BASE	0x00000000
+
+#ifdef PRCM_CONFIG_I
+#define SDRC_ACTIM_CTRLA_0_VAL	0x7BA35907
+#define SDRC_ACTIM_CTRLB_0_VAL	0x00000013
+#define SDRC_RFR_CTRL_0_VAL	0x00044C01
+#elif defined(PRCM_CONFIG_II)
+#define SDRC_ACTIM_CTRLA_0_VAL	0x4A59B485
+#define SDRC_ACTIM_CTRLB_0_VAL	0x0000000C
+#define SDRC_RFR_CTRL_0_VAL	0x00030001
+#endif
+
+#define SDRAM_BASE_ADDRESS	0x80008000
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef CONFIG_SYS_NOR_BOOT
+	/* Check running in SDRAM */
+	mov	r0, pc, lsr #28
+	cmp	r0, #8
+	beq	prcm_setup
+
+flash_setup:
+	/* In Flash */
+	ldr	r0, =WD2_BASE
+	ldr	r1, =WD_UNLOCK1
+	str	r1, [r0, #WSPR]
+
+	ldr	r1, =WD_UNLOCK2
+	str	r1, [r0, #WSPR]
+
+	/* Pin muxing for SDRC */
+	mov	r1, #0x00
+	ldr	r0, =0x480000A1		/* ball C12, mode 0 */
+	strb	r1, [r0]
+
+	ldr	r0, =0x48000032		/* ball D11, mode 0 */
+	strb	r1, [r0]
+
+	ldr	r0, =0x480000A3		/* ball B13, mode 0 */
+	strb	r1, [r0]
+
+	/* SDRC setting */
+	ldr	r0, =OMAP2420_SDRC_BASE
+	ldr	r1, =0x00000010
+	str	r1, [r0, #0x10]
+
+	ldr	r1, =0x00000100
+	str	r1, [r0, #0x44]
+
+	/* SDRC CS0 configuration */
+	ldr	r1, =0x00d04011
+	str	r1, [r0, #0x80]
+
+	ldr	r1, =SDRC_ACTIM_CTRLA_0_VAL
+	str	r1, [r0, #0x9C]
+
+	ldr	r1, =SDRC_ACTIM_CTRLB_0_VAL
+	str	r1, [r0, #0xA0]
+
+	ldr	r1, =SDRC_RFR_CTRL_0_VAL
+	str	r1, [r0, #0xA4]
+
+	ldr	r1, =0x00000041
+	str	r1, [r0, #0x70]
+
+	/* Manual command sequence */
+	ldr	r1, =0x00000007
+	str	r1, [r0, #0xA8]
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0xA8]
+
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xA8]
+
+	ldr	r1, =0x00000002
+	str	r1, [r0, #0xA8]
+	str	r1, [r0, #0xA8]
+
+	/*
+	 * CS0 SDRC Mode register
+	 *   Burst length = 4 - DDR memory
+	 *   Serial mode
+	 *   CAS latency = 3
+	 */
+	ldr	r1, =0x00000032
+	str	r1, [r0, #0x84]
+
+	/* Note: You MUST set EMR values */
+	/* EMR1 & EMR2 */
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x88]
+	str	r1, [r0, #0x8C]
+
+#ifdef OLD_SDRC_DLLA_CTRL
+	/* SDRC_DLLA_CTRL */
+	ldr	r1, =0x00007306
+	str	r1, [r0, #0x60]
+
+	ldr	r1, =0x00007303
+	str	r1, [r0, #0x60]
+#else
+	/* SDRC_DLLA_CTRL */
+	ldr	r1, =0x00000506
+	str	r1, [r0, #0x60]
+
+	ldr	r1, =0x00000503
+	str	r1, [r0, #0x60]
+#endif
+
+#ifdef __BROKEN_FEATURE__
+	/* SDRC_DLLB_CTRL */
+	ldr	r1, =0x00000506
+	str	r1, [r0, #0x68]
+
+	ldr	r1, =0x00000503
+	str	r1, [r0, #0x68]
+#endif
+
+	/* little delay after init */
+	mov	r2, #0x1800
+1:
+	subs	r2, r2, #0x1
+	bne	1b
+
+	/* Setup base address */
+	ldr	r0, =0x00000000		/* NOR address */
+	ldr	r1, =SDRAM_BASE_ADDRESS	/* SDRAM address */
+	ldr	r2, =0x20000		/* Size: 128KB */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}
+	stmia	r1!, {r3-r10}
+	cmp	r0, r2
+	ble	copy_loop
+
+	ldr	r1, =SDRAM_BASE_ADDRESS
+	mov	lr, pc
+	mov	pc, r1
+#endif
+
+prcm_setup:
+	ldr	r0, =OMAP2420_CM_BASE
+	ldr	r1, [r0, #0x544]	/* CLKSEL2_PLL */
+	bic	r1, r1, #0x03
+	orr	r1, r1, #0x02
+	str	r1, [r0, #0x544]
+
+	ldr	r1, [r0, #0x500]
+	bic	r1, r1, #0x03
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x500]
+
+	ldr	r1, [r0, #0x140]
+	bic	r1, r1, #0x1f
+	orr	r1, r1, #0x02
+	str	r1, [r0, #0x140]
+
+#ifdef PRCM_CONFIG_I
+	ldr	r1, =0x000003C3
+#else
+	ldr	r1, =0x00000343
+#endif
+	str	r1, [r0, #0x840]
+
+	ldr	r1, =0x00000002
+	str	r1, [r0, #0x340]
+
+	ldr	r1, =CM_CLKSEL1_CORE
+#ifdef PRCM_CONFIG_I
+	ldr	r2, =0x08300C44
+#else
+	ldr	r2, =0x04600C26
+#endif
+	str	r2, [r1]
+
+	ldr	r0, =OMAP2420_CM_BASE
+	ldr	r1, [r0, #0x084]
+	and	r1, r1, #0x01
+	cmp	r1, #0x01
+	bne	clkvalid
+
+	b	.
+
+clkvalid:
+	mov	r1, #0x01
+	str	r1, [r0, #0x080]
+
+waitvalid:
+	ldr	r1, [r0, #0x084]
+	and	r1, r1, #0x01
+	cmp	r1, #0x00
+	bne	waitvalid
+
+	ldr	r0, =CM_CLKSEL1_PLL
+#ifdef PRCM_CONFIG_I
+	ldr	r1, =0x01837100
+#else
+	ldr	r1, =0x01832100
+#endif
+	str	r1, [r0]
+
+	ldr	r0, =PRCM_CLKCFG_CTRL
+	mov	r1, #0x01
+	str	r1, [r0]
+	mov	r6, #0x50
+loop1:
+	subs	r6, r6, #0x01
+	cmp	r6, #0x01
+	bne	loop1
+
+	ldr	r0, =CM_CLKEN_PLL
+	mov	r1, #0x0f
+	str	r1, [r0]
+
+	mov	r6, #0x100
+loop2:
+	subs	r6, r6, #0x01
+	cmp	r6, #0x01
+	bne	loop2
+
+	ldr	r0, =0x48008200
+	ldr	r1, =0xbfffffff
+	str	r1, [r0]
+
+	ldr	r0, =0x48008210
+	ldr	r1, =0xfffffff9
+	str	r1, [r0]
+
+	ldr	r0, =0x4806a004
+	ldr	r1, =0x00
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a020
+	ldr	r1, =0x07
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a00c
+	ldr	r1, =0x83
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a000
+	ldr	r1, =0x1a
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a004
+	ldr	r1, =0x00
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a00c
+	ldr	r1, =0x03
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a010
+	ldr	r1, =0x03
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a008
+	ldr	r1, =0x04
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a020
+	ldr	r1, =0x00
+	strb	r1, [r0]
+
+#if 0
+	ldr	r0, =0x4806a000
+	mov	r1, #'u'
+	strb	r1, [r0]
+#endif
+
+#if 0
+	/* LED0 OFF */
+	ldr	r3, =0x480000E5
+	mov	r4, #0x0b
+	strb	r4, [r3]
+#endif
+
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* map interrupt controller */
+	ldr	r0,	VAL_INTH_SETUP
+	mcr	p15, 0, r0, c15, c2, 4
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+VAL_INTH_SETUP:
+	.word PERIFERAL_PORT_BASE
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
diff --git a/u-boot/board/apollon/mem.c b/u-boot/board/apollon/mem.c
new file mode 100644
index 0000000..36bf6e9
--- /dev/null
+++ b/u-boot/board/apollon/mem.c
@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+#include "mem.h"
+
+/************************************************************
+ * sdelay() - simple spin loop.  Will be constant time as
+ *  its generally used in 12MHz bypass conditions only.  This
+ *  is necessary until timers are accessible.
+ *
+ *  not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+	__asm__("1:\n" "subs %0, %1, #1\n"
+		  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/********************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * (config II default).
+ *   -- called from SRAM, or Flash (using temp SRAM stack).
+ ********************************************************************/
+void prcm_init(void) { }
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontigious support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(SDRC_CS0_OSET);
+	size /= SZ_32M;		/* find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in gussing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+	u32 val1, val2;
+	u32 pattern = 0x12345678;
+
+	/* clear pos A */
+	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
+	/* pattern to pos B */
+	__raw_writel(pattern, OMAP2420_SDRC_CS0);
+	/* remove pattern off the bus */
+	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
+	/* get pos A value */
+	val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
+	val2 = __raw_readl(OMAP2420_SDRC_CS0);	/* get val2 */
+
+	/* see if pos A value changed */
+	if ((val1 != 0) || (val2 != pattern))
+		return (0);
+	else
+		return (1);
+}
+
+/********************************************************
+ *  sdrc_init() - init the sdrc chip selects CS0 and CS1
+ *  - early init routines, called from flash or
+ *  SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+#define EARLY_INIT 1
+	/* only init up first bank here */
+	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *  -called from low level code with stack only.
+ *  -code sets up SDRAM timing and muxing for 2422 or 2420.
+ *  -optimal settings can be placed here, or redone after i2c
+ *      inspection of board info
+ *
+ *  This is a bit ugly, but should handle all memory moduels
+ *   used with the APOLLON. The first time though this code from s_init()
+ *   we configure the first chip select.  Later on we come back and
+ *   will configure the 2nd chip select if it exists.
+ *
+ **************************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	u32 mux = 0, mtype, mwidth, rev, tval;
+
+	rev = get_cpu_rev();
+	if (rev == CPU_2420_2422_ES1)
+		tval = 1;
+	else
+		tval = 0;	/* disable bit switched meaning */
+
+	/* global settings */
+	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
+	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
+	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);	/* timeout disable */
+#ifdef CONFIG_SYS_NAND_BOOT
+	/* set nWP, disable limited addr */
+	__raw_writel(0x001, GPMC_CONFIG);
+#else
+	/* set nWP, disable limited addr */
+	__raw_writel(0x111, GPMC_CONFIG);
+#endif
+
+	/* discover bus connection from sysboot */
+	if (is_gpmc_muxed() == GPMC_MUXED)
+		mux = BIT9;
+	mtype = get_gpmc0_type();
+	mwidth = get_gpmc0_width();
+
+	/* setup cs0 */
+	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
+	sdelay(1000);
+
+#ifdef CONFIG_SYS_NOR_BOOT
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
+#else
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
+		     GPMC_CONFIG1_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
+#endif
+	sdelay(2000);
+
+	/* setup cs1 */
+	__raw_writel(0, GPMC_CONFIG7_1);	/* disable any mapping */
+	sdelay(1000);
+
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
+	sdelay(2000);
+
+	/* setup cs2 */
+	__raw_writel(0x0, GPMC_CONFIG7_2);	/* disable current map */
+	sdelay(1000);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
+		     GPMC_CONFIG1_2);
+	/* It's same as cs 0 */
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
+#ifdef CONFIG_SYS_NOR_BOOT
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
+#else
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
+#endif
+
+#ifndef CONFIG_SYS_NOR_BOOT
+	/* setup cs3 */
+	__raw_writel(0, GPMC_CONFIG7_3);	/* disable any mapping */
+	sdelay(1000);
+
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
+#endif
+
+#ifndef ASYNC_NOR
+	__raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
+	__raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
+	__raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
+#endif
+	sdelay(2000);
+}
diff --git a/u-boot/board/apollon/mem.h b/u-boot/board/apollon/mem.h
new file mode 100644
index 0000000..09c4ea4
--- /dev/null
+++ b/u-boot/board/apollon/mem.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _APOLLON_OMAP24XX_MEM_H_
+#define _APOLLON_OMAP24XX_MEM_H_
+
+/* Slower full frequency range default timings for x32 operation*/
+#define APOLLON_2420_SDRC_SHARING		0x00000100
+#define APOLLON_2420_SDRC_MDCFG_0_DDR		0x00d04011
+#define APOLLON_2420_SDRC_MR_0_DDR		0x00000032
+
+/* optimized timings good for current shipping parts */
+#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz	0x4A59B485
+#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz	0x0000000C
+
+#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz	0x7BA35907
+#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz	0x00000013
+
+#define APOLLON_242X_SDRC_RFR_CTRL_100MHz	0x00030001
+#define APOLLON_242X_SDRC_RFR_CTRL_166MHz	0x00044C01
+
+#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz	0x00007306
+#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz	0x00000506
+
+#ifdef PRCM_CONFIG_I
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
+#define APOLLON_2420_SDRC_RFR_CTRL	APOLLON_242X_SDRC_RFR_CTRL_166MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL	APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
+#elif PRCM_CONFIG_II
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
+#define APOLLON_2420_SDRC_RFR_CTRL	APOLLON_242X_SDRC_RFR_CTRL_100MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL	APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
+#endif
+
+/* GPMC settings */
+#ifdef PRCM_CONFIG_I		/* L3 at 165MHz */
+/* CS0: OneNAND */
+# define APOLLON_24XX_GPMC_CONFIG1_0	0x00000001
+# define APOLLON_24XX_GPMC_CONFIG2_0	0x000c1000
+# define APOLLON_24XX_GPMC_CONFIG3_0	0x00030400
+# define APOLLON_24XX_GPMC_CONFIG4_0	0x0b841006
+# define APOLLON_24XX_GPMC_CONFIG5_0	0x020f0c11
+# define APOLLON_24XX_GPMC_CONFIG6_0	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000e40|(APOLLON_CS0_BASE >> 24))
+
+/* CS1: Ethernet */
+# define APOLLON_24XX_GPMC_CONFIG1_1	0x00011203
+# define APOLLON_24XX_GPMC_CONFIG2_1	0x001F1F01
+# define APOLLON_24XX_GPMC_CONFIG3_1	0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1	0x1C0b1C0a
+# define APOLLON_24XX_GPMC_CONFIG5_1	0x041F1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
+
+/* CS2: OneNAND */
+/* It's same as CS0 */
+# define APOLLON_24XX_GPMC_CONFIG7_2	(0x00000e40|(APOLLON_CS2_BASE >> 24))
+
+/* CS3: NOR */
+#ifdef ASYNC_NOR
+# define APOLLON_24XX_GPMC_CONFIG1_3	0x00021201
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00121601
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00040401
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x12061605
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x01151317
+#else
+# define SYNC_NOR_VALUE			0x24aaa
+# define APOLLON_24XX_GPMC_CONFIG1_3	0xe5011211
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00090b01
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00020201
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x09030b03
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x010a0a0c
+#endif /* ASYNC_NOR */
+# define APOLLON_24XX_GPMC_CONFIG6_3	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_3	(0x00000e40|(APOLLON_CS3_BASE >> 24))
+#endif /* endif PRCM_CONFIG_I */
+
+#ifdef PRCM_CONFIG_II		/* L3 at 100MHz */
+/* CS0: OneNAND */
+# define APOLLON_24XX_GPMC_CONFIG1_0	0x00000001
+# define APOLLON_24XX_GPMC_CONFIG2_0	0x00081080
+# define APOLLON_24XX_GPMC_CONFIG3_0	0x00030300
+# define APOLLON_24XX_GPMC_CONFIG4_0	0x08041004
+# define APOLLON_24XX_GPMC_CONFIG5_0	0x020b0910
+# define APOLLON_24XX_GPMC_CONFIG6_0	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000C40|(APOLLON_CS0_BASE >> 24))
+
+/* CS1: ethernet */
+# define APOLLON_24XX_GPMC_CONFIG1_1	0x00401203
+# define APOLLON_24XX_GPMC_CONFIG2_1	0x001F1F01
+# define APOLLON_24XX_GPMC_CONFIG3_1	0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1	0x1C091C09
+# define APOLLON_24XX_GPMC_CONFIG5_1	0x041F1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
+
+/* CS2: OneNAND */
+/* It's same as CS0 */
+# define APOLLON_24XX_GPMC_CONFIG7_2	(0x00000e40|(APOLLON_CS2_BASE >> 24))
+
+/* CS3: NOR */
+#define ASYNC_NOR
+#ifdef ASYNC_NOR
+# define APOLLON_24XX_GPMC_CONFIG1_3	0x00021201
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00121601
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00040401
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x12061605
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x01151317
+#else
+# define SYNC_NOR_VALUE			0x24aaa
+# define APOLLON_24XX_GPMC_CONFIG1_3	0xe1001202
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00151501
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00050501
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x0e070e07
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x01131F1F
+#endif /* ASYNC_NOR */
+# define APOLLON_24XX_GPMC_CONFIG6_3	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_3	(0x00000C40|(APOLLON_CS3_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III		/* L3 at 133MHz */
+# ifdef CONFIG_SYS_NAND_BOOT
+#  define APOLLON_24XX_GPMC_CONFIG1_0   0x0
+#  define APOLLON_24XX_GPMC_CONFIG2_0   0x00141400
+#  define APOLLON_24XX_GPMC_CONFIG3_0   0x00141400
+#  define APOLLON_24XX_GPMC_CONFIG4_0   0x0F010F01
+#  define APOLLON_24XX_GPMC_CONFIG5_0   0x010C1414
+#  define APOLLON_24XX_GPMC_CONFIG6_0   0x00000A80
+# else /* NOR boot */
+#  define APOLLON_24XX_GPMC_CONFIG1_0   0x3
+#  define APOLLON_24XX_GPMC_CONFIG2_0   0x00151501
+#  define APOLLON_24XX_GPMC_CONFIG3_0   0x00060602
+#  define APOLLON_24XX_GPMC_CONFIG4_0   0x10081008
+#  define APOLLON_24XX_GPMC_CONFIG5_0   0x01131F1F
+#  define APOLLON_24XX_GPMC_CONFIG6_0   0x000004c4
+# endif	/* endif CONFIG_SYS_NAND_BOOT */
+# define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000C40|(APOLLON_CS0_BASE >> 24))
+# define APOLLON_24XX_GPMC_CONFIG1_1	0x00011000
+# define APOLLON_24XX_GPMC_CONFIG2_1	0x001f1f01
+# define APOLLON_24XX_GPMC_CONFIG3_1	0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1	0x1C091C09
+# define APOLLON_24XX_GPMC_CONFIG5_1	0x041f1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
+#endif /* endif CONFIG_SYS_PRCM_III */
+
+#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
diff --git a/u-boot/board/apollon/sys_info.c b/u-boot/board/apollon/sys_info.c
new file mode 100644
index 0000000..26ac9a2
--- /dev/null
+++ b/u-boot/board/apollon/sys_info.c
@@ -0,0 +1,403 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>	/* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+	u32 p;
+	p = __raw_readl(PRODUCTION_ID);	/* get production ID */
+	return ((p & CPU_242X_PID_MASK) >> 16);
+}
+
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ *   (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+	u32 v;
+
+	switch (get_prod_id()) {
+	case 1:;		/* 2420 */
+	case 2:
+		return (CPU_2420);
+		break;		/* 2420 pop */
+	case 4:
+		return (CPU_2422);
+		break;
+	case 8:
+		return (CPU_2423);
+		break;
+	default:
+		break;		/* early 2420/2422's unmarked */
+	}
+
+	v = __raw_readl(TAP_IDCODE_REG);
+	v &= CPU_24XX_ID_MASK;
+	/* currently 2420 and 2422 have same id */
+	if (v == CPU_2420_CHIPID) {
+		if (is_gpmc_muxed() == GPMC_MUXED)	/* if mux'ed */
+			return (CPU_2420);
+		else
+			return (CPU_2422);
+	} else
+		return (CPU_2420);	/* don't know, say 2420 */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 v;
+	v = __raw_readl(TAP_IDCODE_REG);
+	v = v >> 28;
+	return (v + 1);		/* currently 2422 and 2420 match up */
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
+	if (*burst == H4_2420_SDRC_MR_0_SDR)
+		return (1);
+	return (0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+	u32 cpu, sdr = is_mem_sdr();
+
+	cpu = get_cpu_type();
+	if (cpu == CPU_2422 || cpu == CPU_2423)
+		return (DDR_STACKED);
+
+	if (get_prod_id() == 0x2)
+		return (XDR_POP);
+
+	if (get_board_type() == BOARD_H4_MENELAUS)
+		if (sdr)
+			return (SDR_DISCRETE);
+		else
+			return (DDR_COMBO);
+	else if (sdr)		/* SDP + SDR kit */
+		return (SDR_DISCRETE);
+	else
+		return (DDR_DISCRETE);	/* origional SDP */
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+	size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;	/* get ram size field */
+	size &= 0x2FF;		/* remove unwanted bits */
+	size *= SZ_2M;		/* find size in MB */
+	return (size);
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
+ *      when they are available we can get info from there.  This should
+ *      be correct of all known boards up until today.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+	return (BOARD_H4_SDP);
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings (dip switch on h4)
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return (0x00000FFF & __raw_readl(CONTROL_STATUS));
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = __raw_readl(GPMC_CONFIG7_0);
+	b &= 0x1F;		/* keep base [5:0] */
+	b = b << 24;		/* ret 0x0b000000 */
+	return (b);
+}
+
+/*****************************************************************
+ *  is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+	u32 mux;
+	mux = get_sysboot_value();
+	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+		return (GPMC_MUXED);	/* NAND Boot mode */
+	if (mux & BIT1)		/* if mux'ed */
+		return (GPMC_MUXED);
+	else
+		return (GPMC_NONMUXED);
+}
+
+/************************************************************************
+ *  get_gpmc0_type() - read sysboot lines to see type of memory attached
+ ************************************************************************/
+u32 get_gpmc0_type(void)
+{
+	u32 type;
+	type = get_sysboot_value();
+	if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
+		return (TYPE_NAND);
+	else
+		return (TYPE_NOR);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	u32 width;
+	width = get_sysboot_value();
+	if ((width & 0xF) == (BIT3 | BIT2))
+		return (WIDTH_8BIT);
+	else
+		return (WIDTH_16BIT);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ *   volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+	u32 i = 0, val;
+	do {
+		++i;
+		val = __raw_readl(read_addr) & read_bit_mask;
+		if (val == match_value)
+			return (1);
+		if (i == bound)
+			return (0);
+	} while (1);
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char cpu_2420[] = "2420";	/* cpu type */
+	char cpu_2422[] = "2422";
+	char cpu_2423[] = "2423";
+	char db_men[] = "Menelaus";	/* board type */
+	char db_ip[] = "IP";
+	char mem_sdr[] = "mSDR";	/* memory type */
+	char mem_ddr[] = "mDDR";
+	char t_tst[] = "TST";	/* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+
+	char *cpu_s, *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if (is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	if (cpu == CPU_2423)
+		cpu_s = cpu_2423;
+	else if (cpu == CPU_2422)
+		cpu_s = cpu_2422;
+	else
+		cpu_s = cpu_2420;
+
+	if (btype == BOARD_H4_MENELAUS)
+		db_s = db_men;
+	else
+		db_s = db_ip;
+
+	switch (sec) {
+	case TST_DEVICE:
+		sec_s = t_tst;
+		break;
+	case EMU_DEVICE:
+		sec_s = t_emu;
+		break;
+	case HS_DEVICE:
+		sec_s = t_hs;
+		break;
+	case GP_DEVICE:
+		sec_s = t_gp;
+		break;
+	default:
+		sec_s = unk;
+	}
+
+	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
+	printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ *          0 = 242x IP platform (first 2xx boards)
+ *          1 = 242x Menelaus platfrom.
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	u32 btype = get_board_type();
+
+	if (btype == BOARD_H4_MENELAUS)
+		rev = 1;
+	return (rev);
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32 val;
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return (val);
+}
+
+/********************************************************
+ *  get_base2(); get 2upper addr of current execution
+ *******************************************************/
+u32 get_base2(void)
+{
+	u32 val;
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xFF000000;
+	val >>= 24;
+	return (val);
+}
+
+/********************************************************
+ *  running_in_flash() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+	if (get_base() < 4)
+		return (1);	/* in flash */
+	return (0);		/* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sram() - tell if currently running in
+ *   sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+	if (get_base() == 4)
+		return (1);	/* in SRAM */
+	return (0);		/* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sdram() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return (1);	/* in sdram */
+	return (0);		/* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ *  running_from_internal_boot() - am I a signed NOR image.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+	u32 v, base;
+
+	v = get_sysboot_value() & BIT3;
+	base = get_base2();
+	/* if running at mask rom flash address and
+	 * sysboot3 says this was an internal boot
+	 */
+	if ((base == 0x08) && v)
+		return (1);
+	else
+		return (0);
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
+	return (mode >>= 8);
+}
diff --git a/u-boot/board/armadillo/Makefile b/u-boot/board/armadillo/Makefile
new file mode 100644
index 0000000..3b52452
--- /dev/null
+++ b/u-boot/board/armadillo/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= armadillo.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/armadillo/armadillo.c b/u-boot/board/armadillo/armadillo.c
new file mode 100644
index 0000000..a825144
--- /dev/null
+++ b/u-boot/board/armadillo/armadillo.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <clps7111.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number MACH_TYPE_ARMADILLO - not official*/
+	gd->bd->bi_arch_number = 83;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/armadillo/config.mk b/u-boot/board/armadillo/config.mk
new file mode 100644
index 0000000..ecb8b74
--- /dev/null
+++ b/u-boot/board/armadillo/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+CONFIG_SYS_TEXT_BASE = 0xc0f80000
diff --git a/u-boot/board/armadillo/flash.c b/u-boot/board/armadillo/flash.c
new file mode 100644
index 0000000..cdbbfd0
--- /dev/null
+++ b/u-boot/board/armadillo/flash.c
@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Flash driver for armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x400000
+
+/*value used by hermit is 0x200*/
+/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/
+#define MAIN_SECT_SIZE  0x10000
+
+#define UNALIGNED_MASK (3)
+#define FL_WORD(addr) (*(volatile unsigned short*)(addr))
+#define FLASH_TIMEOUT 20000000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK);
+		/*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] =
+				flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FUJ_MANUFACT & FLASH_VENDMASK):
+		printf ("Fujitsu: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+/*
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+		printf ("28F128J3 (128Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+*/
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+/*
+Done:	;
+*/
+}
+
+/*
+ *  * Loop until both write state machines complete.
+ *   */
+static unsigned short flash_status_wait (unsigned long addr,
+					 unsigned short value)
+{
+	unsigned short status;
+	long timeout = FLASH_TIMEOUT;
+
+	while (((status = (FL_WORD (addr))) != value) && timeout > 0) {
+		timeout--;
+	}
+	return status;
+}
+
+/*
+ * Loop until the Write State machine is ready, then do a full error
+ * check.  Clear status and leave the flash in Read Array mode; return
+ * 0 for no error, -1 for error.
+ */
+static int flash_status_full_check (unsigned long addr, unsigned short value1,
+				    unsigned short value2)
+{
+	unsigned short status1, status2;
+
+	status1 = flash_status_wait (addr, value1);
+	status2 = flash_status_wait (addr + 2, value2);
+	return (status1 != value1 || status2 != value2) ? -1 : 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+	unsigned long base;
+	unsigned long addr;
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FUJ_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	printf ("Erasing %d sectors starting at sector %2d.\n"
+		"This make take some time ... ",
+		s_last - s_first, sect);
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		/* ARM simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			addr = sect * MAIN_SECT_SIZE;
+			addr &= ~(unsigned long) UNALIGNED_MASK;	/* word align */
+			base = addr & 0xF0000000;
+
+			FL_WORD (base + (0x555 << 1)) = 0xAA;
+			FL_WORD (base + (0x2AA << 1)) = 0x55;
+			FL_WORD (base + (0x555 << 1)) = 0x80;
+			FL_WORD (base + (0x555 << 1)) = 0xAA;
+			FL_WORD (base + (0x2AA << 1)) = 0x55;
+			FL_WORD (addr) = 0x30;
+			if (flash_status_full_check (addr, 0xFFFF, 0xFFFF))
+				return ERR_PROTECTED;
+		}
+	}
+	printf ("\nDone.\n");
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	int flag;
+	unsigned long base;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((FL_WORD (dest) & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	base = dest & 0xF0000000;
+	FL_WORD (base + (0x555 << 1)) = 0xAA;
+	FL_WORD (base + (0x2AA << 1)) = 0x55;
+	FL_WORD (base + (0x555 << 1)) = 0xA0;
+	FL_WORD (dest) = data;
+	/*printf("writing 0x%p = 0x%x\n",dest,data); */
+	if (flash_status_wait (dest, data) != data)
+		return ERR_PROG_ERROR;
+
+	if (flag)
+		enable_interrupts ();
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+	printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src);
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		printf ("\nDone.\n");
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/armadillo/lowlevel_init.S b/u-boot/board/armadillo/lowlevel_init.S
new file mode 100644
index 0000000..e7d373d
--- /dev/null
+++ b/u-boot/board/armadillo/lowlevel_init.S
@@ -0,0 +1,66 @@
+/*
+ * Initialization stuff - taken from hermit
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+/* setting up the memory */
+#define	SRAM_START	0x60000000
+#define	SRAM_SIZE	0x0000c000
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r0, #0x70		/* 32-bit code + data, MMU mandatory */
+	mcr	p15, 0, r0, c1, c0, 0	/* MMU init */
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	r0, #0x80000000		/* I/O base */
+
+	mov	r1, #0x6		/* CLKCTL_73 in SYSCON3 */
+	add	r2, r0, #0x2200		/* address of SYSCON3 in r2 */
+	str	r1, [r2]		/* set clock speed to 73.728 MHz */
+
+	mov	r1, #0x81		/* 64KHz DRAM refresh period */
+	str	r1, [r0, #0x200]	/* set DRFPR */
+
+	mov	r1, #0x500		/* permanent enable, 16bits wide */
+	add	r1, r1, #0x42		/* 128Mbit, CAS lat = 2 SDRAM */
+	add	r2, r0, #0x2300		/* load address in r2 */
+	str	r1, [r2]
+
+	mov	r1, #0x100		/* SDRAM refresh rate */
+	add	r2, r0, #0x2340		/* load address in r2 */
+	str	r1, [r2]
+
+	mov	sp, #SRAM_START		/* init stack pointer */
+	add	sp, sp, #SRAM_SIZE
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/armltd/integrator/Makefile b/u-boot/board/armltd/integrator/Makefile
new file mode 100644
index 0000000..c452631
--- /dev/null
+++ b/u-boot/board/armltd/integrator/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS-y	:= lowlevel_init.o
+
+COBJS-y	:= integrator.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-y += timer.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+COBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(COBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(COBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/armltd/integrator/config.mk b/u-boot/board/armltd/integrator/config.mk
new file mode 100644
index 0000000..8b57af1
--- /dev/null
+++ b/u-boot/board/armltd/integrator/config.mk
@@ -0,0 +1,5 @@
+#
+# image should be loaded at 0x01000000
+#
+
+CONFIG_SYS_TEXT_BASE = 0x01000000
diff --git a/u-boot/board/armltd/integrator/integrator.c b/u-boot/board/armltd/integrator/integrator.c
new file mode 100644
index 0000000..9bb56b5
--- /dev/null
+++ b/u-boot/board/armltd/integrator/integrator.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of Integrator Board */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+#else
+	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	gd->flags = 0;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#endif
+
+	icache_enable ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PCI
+	pci_init();
+#endif
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+	{
+extern void dram_query(void);
+	unsigned long cm_reg_sdram;
+	unsigned long sdram_shift;
+
+	dram_query();	/* Assembler accesses to CM registers */
+			/* Queries the SPD values	      */
+
+	/* Obtain the SDRAM size from the CM SDRAM register */
+
+	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+	/*   Register	      SDRAM size
+	 *
+	 *   0xXXXXXXbbb000bb	 16 MB
+	 *   0xXXXXXXbbb001bb	 32 MB
+	 *   0xXXXXXXbbb010bb	 64 MB
+	 *   0xXXXXXXbbb011bb	128 MB
+	 *   0xXXXXXXbbb100bb	256 MB
+	 *
+	 */
+	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
+
+	}
+#endif /* CM_SPD_DETECT */
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	rc += pci_eth_init(bis);
+	return rc;
+}
+#endif
diff --git a/u-boot/board/armltd/integrator/lowlevel_init.S b/u-boot/board/armltd/integrator/lowlevel_init.S
new file mode 100644
index 0000000..ab9589c
--- /dev/null
+++ b/u-boot/board/armltd/integrator/lowlevel_init.S
@@ -0,0 +1,213 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+	/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+	mov	r0, #CM_BASE
+	ldr	r1,[r0,#OS_CTRL]
+	orr	r1,r1,#CMMASK_RESET
+	str	r1,[r0,#OS_CTRL]
+
+reset_failed:
+	b	reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	/* If U-Boot has been run after the ARM boot monitor
+	 * then all the necessary actions have been done
+	 * otherwise we are running from user flash mapped to 0x00000000
+	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+	 * Changes to the (possibly soft) reset defaults of the processor
+	 * itself should be performed in cpu/arm<>/start.S
+	 * This function affects only the core module or board settings
+	 */
+
+#ifdef CONFIG_CM_INIT
+	/* CM has an initialization register
+	 * - bits in it are wired into test-chip pins to force
+	 *   reset defaults
+	 * - may need to change its contents for U-Boot
+	 */
+
+	/* set the desired CM specific value */
+	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+	orr	r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+     !defined (CONFIG_CM940T)
+
+#ifdef	CONFIG_CM_MULTIPLE_SSRAM
+	/* set simple mapping			*/
+	and	r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
+
+#ifdef	CONFIG_CM_TCRAM
+	/* disable TCRAM			*/
+	and	r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM		*/
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+     defined (CONFIG_CM1136JF_S)
+
+	and	r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+	orr	r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+	/* read CM_INIT		 */
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_INIT]
+	/* check against desired bit setting */
+	and	r3,r1,r2
+	cmp	r3,r2
+	beq	init_reg_OK
+
+	/* lock for change */
+	mov	r3, #CMVAL_LOCK1
+	add	r3,r3,#CMVAL_LOCK2
+	str	r3, [r0, #OS_LOCK]
+	/* set desired value */
+	orr	r1,r1,r2
+	/* write & relock CM_INIT */
+	str	r1, [r0, #OS_INIT]
+	mov	r1, #CMVAL_UNLOCK
+	str	r1, [r0, #OS_LOCK]
+
+	/* soft reset so new values used */
+	b	reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+	mov	pc, lr
+
+#ifdef	CONFIG_CM_SPD_DETECT
+	/* Fast memory is available for the DRAM data
+	 * - ensure it has been transferred, then summarize the data
+	 *   into a CM register
+	 */
+.globl dram_query
+dram_query:
+	stmfd	r13!,{r4-r6,lr}
+	/* set up SDRAM info					*/
+	/* - based on example code from the CM User Guide */
+	mov	r0, #CM_BASE
+
+readspdbit:
+	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register	*/
+	and	r1, r1, #0x20		/* mask SPD bit (5)		*/
+	cmp	r1, #0x20		/* test if set			*/
+	bne	readspdbit
+
+setupsdram:
+	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
+	ldrb	r1, [r0, #3]		/* number of row address lines		*/
+	ldrb	r2, [r0, #4]		/* number of column address lines	*/
+	ldrb	r3, [r0, #5]		/* number of banks			*/
+	ldrb	r4, [r0, #31]		/* module bank density			*/
+	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
+	mov	r5, r5, ASL#2		/* size in MB				*/
+	mov	r0, #CM_BASE		/* reload for later code		*/
+	cmp	r5, #0x10		/* is it 16MB?				*/
+	bne	not16
+	mov	r6, #0x2		/* store size and CAS latency of 2	*/
+	b	writesize
+
+not16:
+	cmp	r5, #0x20		/* is it  32MB? */
+	bne	not32
+	mov	r6, #0x6
+	b	writesize
+
+not32:
+	cmp	r5, #0x40		/* is it  64MB? */
+	bne	not64
+	mov	r6, #0xa
+	b	writesize
+
+not64:
+	cmp	r5, #0x80		/* is it 128MB? */
+	bne	not128
+	mov	r6, #0xe
+	b	writesize
+
+not128:
+	/* if it is none of these sizes then it is either 256MB, or
+	 * there is no SDRAM fitted so default to 256MB
+	 */
+	mov	r6, #0x12
+
+writesize:
+	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
+	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
+	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
+	orr	r6, r6, r3		/* OR in size and CAS latency	 */
+	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
+
+#ifdef	CONFIG_CM_REMAP
+	/* CM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 */
+.globl cm_remap
+cm_remap:
+	stmfd	r13!,{r4-r10,lr}
+
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_CTRL]
+	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
+	str	r1, [r0, #OS_CTRL]
+
+	/* Now 0x00000000 is writeable, replace the vectors	*/
+	ldr	r0, =_start	/* r0 <- start of vectors	*/
+	ldr	r2, =_armboot_start	/* r2 <- past vectors	*/
+	sub	r1,r1,r1		/* destination 0x00000000	*/
+
+copy_vec:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
+	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
+	cmp	r0, r2			/* until source end address [r2]	*/
+	ble	copy_vec
+
+	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/u-boot/board/armltd/integrator/pci.c b/u-boot/board/armltd/integrator/pci.c
new file mode 100644
index 0000000..6ee2a85
--- /dev/null
+++ b/u-boot/board/armltd/integrator/pci.c
@@ -0,0 +1,396 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_integrator_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif /* CONFIG_PCI_PNP */
+
+/* V3 access routines */
+#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
+#define _V3Read16(o)	(*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
+
+#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
+#define _V3Read32(o)	(*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
+
+/* Compute address necessary to access PCI config space for the given */
+/* bus and device. */
+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({				\
+	unsigned int __address, __devicebit;						\
+	unsigned short __mapaddress;							\
+	unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */		\
+											\
+	if (__bus == 0) {								\
+		/* local bus segment so need a type 0 config cycle */			\
+		/* build the PCI configuration "address" with one-hot in A31-A11 */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__devfn & 0x07) << 8);					\
+		__address |= __offset & 0xFF;						\
+		__mapaddress = 0x000A;	/* 101=>config cycle, 0=>A1=A0=0 */		\
+		__devicebit = (1 << (__dev + 11));					\
+											\
+		if ((__devicebit & 0xFF000000) != 0) {					\
+			/* high order bits are handled by the MAP register */		\
+			__mapaddress |= (__devicebit >> 16);				\
+		} else {								\
+			/* low order bits handled directly in the address */		\
+			__address |= __devicebit;					\
+		}									\
+	} else {		/* bus !=0 */						\
+		/* not the local bus segment so need a type 1 config cycle */		\
+		/* A31-A24 are don't care (so clear to 0) */				\
+		__mapaddress = 0x000B;	/* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__bus & 0xFF) << 16);	/* bits 23..16 = bus number	*/  \
+		__address |= ((__dev & 0x1F) << 11);	/* bits 15..11 = device number	*/  \
+		__address |= ((__devfn & 0x07) << 8);	/* bits 10..8  = function number */ \
+		__address |= __offset & 0xFF;	/* bits	 7..0  = register number */	\
+	}										\
+	_V3Write16 (V3_LB_MAP1, __mapaddress);						\
+	__address;									\
+})
+
+/* _V3OpenConfigWindow - open V3 configuration window */
+#define _V3OpenConfigWindow() {								\
+	/* Set up base0 to see all 512Mbytes of memory space (not	     */		\
+	/* prefetchable), this frees up base1 for re-use by configuration*/		\
+	/* memory */									\
+											\
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+				     0x90 | V3_LB_BASE_M_ENABLE));			\
+	/* Set up base1 to point into configuration space, note that MAP1 */		\
+	/* register is set up by pciMakeConfigAddress(). */				\
+											\
+	_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |			\
+				     0x40 | V3_LB_BASE_M_ENABLE));			\
+}
+
+/* _V3CloseConfigWindow - close V3 configuration window */
+#define _V3CloseConfigWindow() {							\
+    /* Reassign base1 for use by prefetchable PCI memory */				\
+	_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
+					| 0x84 | V3_LB_BASE_M_ENABLE));			\
+	_V3Write16 (V3_LB_MAP1,								\
+	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
+											\
+	/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
+											\
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+			     0x80 | V3_LB_BASE_M_ENABLE));				\
+}
+
+static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned char *val)
+{
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							       PCI_FUNC (dev),
+							       offset);
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_read__word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short *val)
+{
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_read_dword (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned int *val)
+{
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	*val |= (*(volatile unsigned int *)
+		 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
+				     (offset + 2))) << 16;
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_write_byte (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned char val)
+{
+	_V3OpenConfigWindow ();
+	*(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							PCI_FUNC (dev),
+							offset) = val;
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_write_word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short val)
+{
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = val;
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_write_dword (struct pci_controller *hose,
+				       pci_dev_t dev, int offset,
+				       unsigned int val)
+{
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = (val & 0xFFFF);
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 (offset + 2)) = ((val >> 16) & 0xFFFF);
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+/******************************
+ * PCI initialisation
+ ******************************/
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+	volatile int i, j;
+	struct pci_controller *hose = &integrator_hose;
+
+	/* setting this register will take the V3 out of reset */
+
+	*(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
+
+	/* wait a few usecs to settle the device and the PCI bus */
+
+	for (i = 0; i < 100; i++)
+		j = i + 1;
+
+	/* Now write the Base I/O Address Word to V3_BASE + 0x6C */
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
+		(unsigned short) (V3_BASE >> 16);
+
+	do {
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
+			0x55;
+	} while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
+		 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
+						 4) != 0x55);
+
+	/* Make sure that V3 register access is not locked, if it is, unlock it */
+
+	if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
+	     V3_SYSTEM_M_LOCK)
+	    == V3_SYSTEM_M_LOCK)
+		*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
+
+	/* Ensure that the slave accesses from PCI are disabled while we */
+	/* setup windows */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
+		~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+
+	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
+		~V3_SYSTEM_M_RST_OUT;
+
+	/* Make all accesses from PCI space retry until we're ready for them */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
+		V3_PCI_CFG_M_RETRY_EN;
+
+	/* Set up any V3 PCI Configuration Registers that we absolutely have to */
+	/* LB_CFG controls Local Bus protocol. */
+	/* Enable LocalBus byte strobes for READ accesses too. */
+	/* set bit 7 BE_IMODE and bit 6 BE_OMODE */
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
+
+	/* PCI_CMD controls overall PCI operation. */
+	/* Enable PCI bus master. */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
+
+	/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
+		(INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
+					      V3_PCI_MAP_M_REG_EN |
+					      V3_PCI_MAP_M_ENABLE);
+
+	/* PCI_BASE0 is the PCI address of the start of the window */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
+		INTEGRATOR_BOOT_ROM_BASE;
+
+	/* PCI_MAP1 is LOCAL address of the start of the window */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
+		(INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
+						V3_PCI_MAP_M_REG_EN |
+						V3_PCI_MAP_M_ENABLE);
+
+	/* PCI_BASE1 is the PCI address of the start of the window */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
+		INTEGRATOR_HDR0_SDRAM_BASE;
+
+	/* Set up the windows from local bus memory into PCI configuration, */
+	/* I/O and Memory. */
+	/* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
+		((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
+
+	/* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+	/* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
+	/* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
+	/* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
+
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
+		INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
+		((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
+
+	/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
+		INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
+		(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
+
+	/* Allow accesses to PCI Configuration space */
+	/* and set up A1, A0 for type 1 config cycles */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
+		((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
+		 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
+		V3_PCI_CFG_M_AD_LOW0;
+
+	/* now we can allow in PCI MEMORY accesses */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
+		(*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
+		V3_COMMAND_M_MEM_EN;
+
+	/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
+	/* initialise and lock the V3 system register so that no one else */
+	/* can play with it */
+
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_RST_OUT;
+
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_LOCK;
+
+	/*
+	 * Register the hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System memory space */
+	pci_set_region (hose->regions + 0,
+			0x00000000, 0x40000000, 0x01000000,
+			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* PCI Memory - config space */
+	pci_set_region (hose->regions + 1,
+			0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
+
+	/* PCI V3 regs */
+	pci_set_region (hose->regions + 2,
+			0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 3,
+			0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
+
+	pci_set_ops (hose,
+		     pci_integrator_read_byte,
+		     pci_integrator_read__word,
+		     pci_integrator_read_dword,
+		     pci_integrator_write_byte,
+		     pci_integrator_write_word, pci_integrator_write_dword);
+
+	hose->region_count = 4;
+
+	pci_register_hose (hose);
+
+	pciauto_config_init (hose);
+	pciauto_config_device (hose, 0);
+
+	hose->last_busno = pci_hose_scan (hose);
+}
diff --git a/u-boot/board/armltd/integrator/split_by_variant.sh b/u-boot/board/armltd/integrator/split_by_variant.sh
new file mode 100755
index 0000000..d869dd2
--- /dev/null
+++ b/u-boot/board/armltd/integrator/split_by_variant.sh
@@ -0,0 +1,220 @@
+#!/bin/sh
+
+mkdir -p ${obj}include
+mkdir -p ${obj}board/armltd/integrator
+
+config_file=${obj}include/config.h
+
+if [ "$1" = "ap" ]
+then
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+cat > ${config_file} << _EOF
+/* Integrator configuration implied by Makefile target */
+#define CONFIG_INTEGRATOR /* Integrator board */
+#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */
+_EOF
+
+# ---------------------------------------------------------
+#	Set the core module defines according to Core Module
+# ---------------------------------------------------------
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$2" = "" ]
+then
+	echo "$0:: No parameters - using arm_intcm"
+else
+	case "$2" in
+	ap7_config)
+	cpu="arm_intcm"
+	variant="unported core module CM7TDMI"
+	;;
+
+	ap966)
+	cpu="arm_intcm"
+	variant="unported core module CM966E-S"
+	;;
+
+	ap922_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T"
+	;;
+
+	integratorap_config	|	\
+	ap_config)
+	cpu="arm_intcm"
+	variant="unspecified core module"
+	;;
+
+	ap720t_config)
+	cpu="arm720t"
+	echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \
+		>> ${config_file}
+	variant="Core module CM720T"
+	;;
+
+	ap922_XA10_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T_XA10"
+	echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
+		>> ${config_file}
+	;;
+
+	ap920t_config)
+	cpu="arm920t"
+	variant="Core module CM920T"
+	echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
+		>> ${config_file}
+	;;
+
+	ap926ejs_config)
+	cpu="arm926ejs"
+	variant="Core module CM926EJ-S"
+	echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
+		>> ${config_file}
+	;;
+
+	ap946es_config)
+	cpu="arm946es"
+	variant="Core module CM946E-S"
+	echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
+		>> ${config_file}
+	;;
+
+	*)
+	echo "$0:: Unknown core module"
+	variant="unknown core module"
+	cpu="arm_intcm"
+	;;
+
+	esac
+fi
+
+case "$cpu" in
+	arm_intcm)
+	cat >> ${config_file} << _EOF
+/* Core module undefined/not ported */
+#define CONFIG_ARM_INTCM 1
+#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
+#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
+#undef CONFIG_CM_REMAP /* CM may not support remapping */
+#undef CONFIG_CM_INIT  /* CM may not have initialization reg */
+#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
+/* May not be processor without cache support */
+#define CONFIG_SYS_NO_ICACHE 1
+#define CONFIG_SYS_NO_DCACHE 1
+_EOF
+	;;
+
+	arm720t)
+	cat >> ${config_file} << _EOF
+/* May not be processor without cache support */
+#define CONFIG_SYS_NO_ICACHE 1
+#define CONFIG_SYS_NO_DCACHE 1
+_EOF
+	;;
+esac
+
+else
+
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+cat >> ${config_file} << _EOF
+/* Integrator configuration implied by Makefile target */
+#define CONFIG_INTEGRATOR /* Integrator board */
+#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP   */
+_EOF
+
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$2" = "" ]
+then
+	echo "$0:: No parameters - using arm_intcm"
+else
+	case "$2" in
+	ap966)
+	cpu="arm_intcm"
+	variant="unported core module CM966E-S"
+	;;
+
+	ap922_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T"
+	;;
+
+	integratorcp_config	|	\
+	cp_config)
+	cpu="arm_intcm"
+	variant="unspecified core module"
+	;;
+
+	cp922_XA10_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T_XA10"
+	echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
+		>> ${config_file}
+	;;
+
+	cp920t_config)
+	cpu="arm920t"
+	variant="Core module CM920T"
+	echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
+		>> ${config_file}
+	;;
+
+	cp926ejs_config)
+	cpu="arm926ejs"
+	variant="Core module CM926EJ-S"
+	echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
+		>> ${config_file}
+	;;
+
+
+	cp946es_config)
+	cpu="arm946es"
+	variant="Core module CM946E-S"
+	echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
+		>> ${config_file}
+	;;
+
+	cp1136_config)
+	cpu="arm1136"
+	variant="Core module CM1136EJF-S"
+	echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \
+		>> ${config_file}
+	;;
+
+	*)
+	echo "$0:: Unknown core module"
+	variant="unknown core module"
+	cpu="arm_intcm"
+	;;
+
+	esac
+
+fi
+
+if [ "$cpu" = "arm_intcm" ]
+then
+	cat >> ${config_file} << _EOF
+/* Core module undefined/not ported */
+#define CONFIG_ARM_INTCM 1
+#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
+#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
+#undef CONFIG_CM_REMAP /* CM may not support remapping */
+#undef CONFIG_CM_INIT /* CM may not have initialization reg */
+#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
+_EOF
+fi
+
+fi # ap
+
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+$MKCONFIG -a -n "${2%%_config}" integrator$1 arm $cpu integrator armltd
+echo "Variant: $variant with core $cpu"
diff --git a/u-boot/board/armltd/integrator/timer.c b/u-boot/board/armltd/integrator/timer.c
new file mode 100644
index 0000000..7562ffa
--- /dev/null
+++ b/u-boot/board/armltd/integrator/timer.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+#define DIV_CLOCK_INIT	1
+#define TIMER_LOAD_VAL	0xFFFFFFFFL
+#else
+#define DIV_CLOCK_INIT	256
+#define TIMER_LOAD_VAL	0x0000FFFFL
+#endif
+/* The Integrator/CP timer1 is clocked at 1MHz
+ * can be divided by 16 or 256
+ * and can be set up as a 32-bit timer
+ */
+/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
+/* Keep total timer count to avoid losing decrements < div_timer */
+static unsigned long long total_count = 0;
+static unsigned long long lastdec;	 /* Timer reading at last call	   */
+/* Divisor applied to timer clock */
+static unsigned long long div_clock = DIV_CLOCK_INIT;
+static unsigned long long div_timer = 1; /* Divisor to convert timer reading
+					  * change to U-Boot ticks
+					  */
+/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
+static ulong timestamp;		/* U-Boot ticks since startup */
+
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
+
+/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
+ *  - unless otherwise stated
+ */
+
+/* starts up a counter
+ * - the Integrator/CP timer can be set up to issue an interrupt */
+int timer_init (void)
+{
+	/* Load timer with initial value */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	/* Set timer to be
+	 *	enabled		 1
+	 *	periodic	 1
+	 *	no interrupts	 0
+	 *	X		 0
+	 *	divider 1	00 == less rounding error
+	 *	32 bit		 1
+	 *	wrapping	 0
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+#else
+	/* Set timer to be
+	 *	enabled		 1
+	 *	free-running	 0
+	 *	XX		00
+	 *	divider 256	10
+	 *	XX		00
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+#endif
+
+	/* init the timestamp */
+	total_count = 0ULL;
+	reset_timer_masked();
+
+	div_timer = CONFIG_SYS_HZ_CLOCK;
+	do_div(div_timer, CONFIG_SYS_HZ);
+	do_div(div_timer, div_clock);
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base_ticks)
+{
+	return get_timer_masked () - base_ticks;
+}
+
+void set_timer (ulong ticks)
+{
+	timestamp   = ticks;
+	total_count = ticks * div_timer;
+}
+
+/* delay usec useconds */
+void __udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* Convert to U-Boot ticks */
+	tmo  = usec * CONFIG_SYS_HZ;
+	tmo /= (1000000L);
+
+	tmp  = get_timer_masked();	/* get current timestamp */
+	tmo += tmp;			/* form target timestamp */
+
+	while (get_timer_masked () < tmo) {/* loop till event */
+		/*NOP*/;
+	}
+}
+
+void reset_timer_masked (void)
+{
+	/* capure current decrementer value    */
+	lastdec	  = READ_TIMER;
+	/* start "advancing" time stamp from 0 */
+	timestamp = 0L;
+}
+
+/* converts the timer reading to U-Boot ticks	       */
+/* the timestamp is the number of ticks since reset    */
+ulong get_timer_masked (void)
+{
+	/* get current count */
+	unsigned long long now = READ_TIMER;
+
+	if(now > lastdec) {
+		/* Must have wrapped */
+		total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+	} else {
+		total_count += lastdec - now;
+	}
+	lastdec	= now;
+
+	/* Reuse "now" */
+	now = total_count;
+	do_div(now, div_timer);
+	timestamp = now;
+
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk (void)
+{
+	unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+
+	do_div(tmp, div_clock);
+
+	return tmp;
+}
diff --git a/u-boot/board/armltd/versatile/Makefile b/u-boot/board/armltd/versatile/Makefile
new file mode 100644
index 0000000..3470328
--- /dev/null
+++ b/u-boot/board/armltd/versatile/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= versatile.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/armltd/versatile/config.mk b/u-boot/board/armltd/versatile/config.mk
new file mode 100644
index 0000000..8b57af1
--- /dev/null
+++ b/u-boot/board/armltd/versatile/config.mk
@@ -0,0 +1,5 @@
+#
+# image should be loaded at 0x01000000
+#
+
+CONFIG_SYS_TEXT_BASE = 0x01000000
diff --git a/u-boot/board/armltd/versatile/lowlevel_init.S b/u-boot/board/armltd/versatile/lowlevel_init.S
new file mode 100644
index 0000000..bdfce2d
--- /dev/null
+++ b/u-boot/board/armltd/versatile/lowlevel_init.S
@@ -0,0 +1,34 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* All done by Versatile's boot monitor! */
+	mov pc, lr
diff --git a/u-boot/board/armltd/versatile/split_by_variant.sh b/u-boot/board/armltd/versatile/split_by_variant.sh
new file mode 100755
index 0000000..475e5a3
--- /dev/null
+++ b/u-boot/board/armltd/versatile/split_by_variant.sh
@@ -0,0 +1,42 @@
+#!/bin/sh
+# ---------------------------------------------------------
+#  Set the core module defines according to Core Module
+# ---------------------------------------------------------
+# ---------------------------------------------------------
+# Set up the Versatile type define
+# ---------------------------------------------------------
+
+mkdir -p ${obj}include
+variant=PB926EJ-S
+if [ "$1" = "" ]
+then
+	echo "$0:: No parameters - using versatilepb_config"
+	echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
+	variant=PB926EJ-S
+else
+	case "$1" in
+	versatilepb_config	|	\
+	versatile_config)
+	echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
+	;;
+
+	versatileab_config)
+	echo "#define CONFIG_ARCH_VERSATILE_AB" > ${obj}include/config.h
+	variant=AB926EJ-S
+	;;
+
+
+	*)
+	echo "$0:: Unrecognised config - using versatilepb_config"
+	echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
+	variant=PB926EJ-S
+	;;
+
+	esac
+
+fi
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+$MKCONFIG -a versatile arm arm926ejs versatile armltd versatile
+echo "Variant:: $variant"
diff --git a/u-boot/board/armltd/versatile/versatile.c b/u-boot/board/armltd/versatile/versatile.c
new file mode 100644
index 0000000..6e836dd
--- /dev/null
+++ b/u-boot/board/armltd/versatile/versatile.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+    printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/*
+	 * set clock frequency:
+	 *	VERSATILE_REFCLK is 32KHz
+	 *	VERSATILE_TIMCLK is 1MHz
+	 */
+	*(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
+	  ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
+	   (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
+
+	/* arch number of Versatile Board */
+	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	gd->flags = 0;
+
+	icache_enable ();
+
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/armltd/vexpress/Makefile b/u-boot/board/armltd/vexpress/Makefile
new file mode 100644
index 0000000..49c4b81
--- /dev/null
+++ b/u-boot/board/armltd/vexpress/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ca9x4_ct_vxp.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/armltd/vexpress/ca9x4_ct_vxp.c b/u-boot/board/armltd/vexpress/ca9x4_ct_vxp.c
new file mode 100644
index 0000000..ce1be1e
--- /dev/null
+++ b/u-boot/board/armltd/vexpress/ca9x4_ct_vxp.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/systimer.h>
+#include <asm/arch/sysctrl.h>
+#include <asm/arch/wdt.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
+
+static void flash__init(void);
+static void vexpress_timer_init(void);
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(ulong loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+	gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
+	gd->flags = 0;
+
+	icache_enable();
+	flash__init();
+	vexpress_timer_init();
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+static void flash__init(void)
+{
+	/* Setup the sytem control register to allow writing to flash */
+	writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
+	       &sysctrl_base->scflashctrl);
+}
+
+int dram_init(void)
+{
+	gd->ram_size =
+		get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size =
+			get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size =
+			get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+/*
+ * Start timer:
+ *    Setup a 32 bit timer, running at 1KHz
+ *    Versatile Express Motherboard provides 1 MHz timer
+ */
+static void vexpress_timer_init(void)
+{
+	/*
+	 * Set clock frequency in system controller:
+	 *   VEXPRESS_REFCLK is 32KHz
+	 *   VEXPRESS_TIMCLK is 1MHz
+	 */
+	writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
+	       SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
+	       readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
+
+	/*
+	 * Set Timer0 to be:
+	 *   Enabled, free running, no interrupt, 32-bit, wrapping
+	 */
+	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+	writel(SYSTIMER_EN | SYSTIMER_32BIT | \
+	       readl(&systimer_base->timer0control), \
+	       &systimer_base->timer0control);
+
+	reset_timer_masked();
+}
+
+/* Use the ARM Watchdog System to cause reset */
+void reset_cpu(ulong addr)
+{
+	writeb(WDT_EN, &wdt_base->wdogcontrol);
+	writel(WDT_RESET_LOAD, &wdt_base->wdogload);
+	while (1)
+		;
+}
+
+/*
+ * Delay x useconds AND perserve advance timstamp value
+ *     assumes timer is ticking at 1 msec
+ */
+void __udelay(ulong usec)
+{
+	ulong tmo, tmp;
+
+	tmo = usec / 1000;
+	tmp = get_timer(0);	/* get current timestamp */
+
+	/*
+	 * If setting this forward will roll time stamp	then
+	 * reset "advancing" timestamp to 0 and set lastdec value
+	 * otherwise set the advancing stamp to the wake up time
+	 */
+	if ((tmo + tmp + 1) < tmp)
+		reset_timer_masked();
+	else
+		tmo += tmp;
+
+	while (get_timer_masked() < tmo)
+		; /* loop till wakeup event */
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+	lastdec = readl(&systimer_base->timer0value) / 1000;
+	timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = readl(&systimer_base->timer0value) / 1000;
+
+	if (lastdec >= now) {	/* normal mode (non roll) */
+		timestamp += lastdec - now;
+	} else {		/* count down timer overflowed */
+		/*
+		 * nts = ts + ld - now
+		 * ts = old stamp, ld = time before passing through - 1
+		 * now = amount of time after passing though - 1
+		 * nts = new "advancing time stamp"
+		 */
+		timestamp += lastdec + SYSTIMER_RELOAD - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void lowlevel_init(void)
+{
+}
+
+ulong get_board_rev(void){
+	return readl((u32 *)SYS_ID);
+}
diff --git a/u-boot/board/armltd/vexpress/config.mk b/u-boot/board/armltd/vexpress/config.mk
new file mode 100644
index 0000000..36395f2
--- /dev/null
+++ b/u-boot/board/armltd/vexpress/config.mk
@@ -0,0 +1,22 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Linux-Kernel is expected to be at 0x60008000
+#
+CONFIG_SYS_TEXT_BASE = 0x60800000
diff --git a/u-boot/board/assabet/Makefile b/u-boot/board/assabet/Makefile
new file mode 100644
index 0000000..b3cf4aa
--- /dev/null
+++ b/u-boot/board/assabet/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2004 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= assabet.o
+SOBJS	:= setup.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/assabet/assabet.c b/u-boot/board/assabet/assabet.c
new file mode 100644
index 0000000..753c8d2
--- /dev/null
+++ b/u-boot/board/assabet/assabet.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <SA-1100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Board dependent initialisation
+ */
+
+#define ECOR			0x8000
+#define ECOR_RESET		0x80
+#define ECOR_LEVEL_IRQ		0x40
+#define ECOR_WR_ATTRIB		0x04
+#define ECOR_ENABLE		0x01
+
+#define ECSR			0x8002
+#define ECSR_IOIS8		0x20
+#define ECSR_PWRDWN		0x04
+#define ECSR_INT		0x02
+#define SMC_IO_SHIFT		2
+#define NCR_0			(*((volatile u_char *)(0x100000a0)))
+#define NCR_ENET_OSC_EN		(1<<3)
+
+static inline u8
+readb(volatile u8 * p)
+{
+	return *p;
+}
+
+static inline void
+writeb(u8 v, volatile u8 * p)
+{
+	*p = v;
+}
+
+static void
+smc_init(void)
+{
+	u8 ecor;
+	u8 ecsr;
+	volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
+
+	NCR_0 |= NCR_ENET_OSC_EN;
+	udelay(100);
+
+	ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
+	writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
+	udelay(100);
+
+	/*
+	 * The device will ignore all writes to the enable bit while
+	 * reset is asserted, even if the reset bit is cleared in the
+	 * same write.  Must clear reset first, then enable the device.
+	 */
+	writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
+	writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
+
+	/*
+	 * Set the appropriate byte/word mode.
+	 */
+	ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
+	ecsr |= ECSR_IOIS8;
+	writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
+	udelay(100);
+}
+
+static void
+neponset_init(void)
+{
+	smc_init();
+}
+
+int
+board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	neponset_init();
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/assabet/config.mk b/u-boot/board/assabet/config.mk
new file mode 100644
index 0000000..d9866a0
--- /dev/null
+++ b/u-boot/board/assabet/config.mk
@@ -0,0 +1,7 @@
+#
+# SA-1110 based Intel Assabet board
+#
+# The Intel Assabet 1 bank of 32 MiB SDRAM
+#
+
+CONFIG_SYS_TEXT_BASE = 0xc1f00000
diff --git a/u-boot/board/assabet/setup.S b/u-boot/board/assabet/setup.S
new file mode 100644
index 0000000..56ea0dd
--- /dev/null
+++ b/u-boot/board/assabet/setup.S
@@ -0,0 +1,136 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04
+#define MDCAS01		0x08
+#define MDCAS02		0x0C
+#define MSC0		0x10
+#define MSC1		0x14
+#define MECR		0x18
+#define MDREFR		0x1C
+#define MDCAS20		0x20
+#define MDCAS21		0x24
+#define MDCAS22		0x28
+#define MSC2		0x2C
+#define SMCNFG		0x30
+
+#define ASSABET_BCR		(0x12000000)
+#define ASSABET_BCR_DB1110	(0x00a07490 | (0<<16) | (0<<17))
+#define ASSABET_SCR_nNEPONSET	(1 << 9)
+#define NEPONSET_LEDS		(0x10000010)
+
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+mdcnfg:		.long	0x72547254
+mdcas00:	.long	0xaaaaaa7f
+mdcas01:	.long	0xaaaaaaaa
+mdcas02:	.long	0xaaaaaaaa
+msc0:		.long	0x4b384370
+msc1:		.long	0x22212419
+mecr:		.long	0x994a994a
+mdrefr:		.long	0x04340327
+mdcas20:	.long	0xaaaaaa7f
+mdcas21:	.long	0xaaaaaaaa
+mdcas22:	.long	0xaaaaaaaa
+msc2:		.long	0x42196669
+smcnfg:		.long	0x00000000
+
+BCR:		.long	ASSABET_BCR
+BCR_DB1110:	.long	ASSABET_BCR_DB1110
+LEDS:		.long	NEPONSET_LEDS
+
+
+	.globl lowlevel_init
+lowlevel_init:
+
+	/* Setting up the memory and stuff */
+
+	ldr	r0, MEM_BASE
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+	ldr	r1, mdrefr
+	str	r1, [r0, #MDREFR]
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Load something to activate bank */
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r3, [r2]
+.endr
+
+	/* Enable SDRAM */
+	orr	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	ldr	r1, BCR
+	ldr	r2, BCR_DB1110
+	str	r2, [r1]
+
+	ldr	r1, LEDS
+	mov	r0, #0x3
+	str	r0, [r1]
+
+	/* All done... */
+	mov	pc, lr
diff --git a/u-boot/board/astro/mcf5373l/Makefile b/u-boot/board/astro/mcf5373l/Makefile
new file mode 100644
index 0000000..d44a260
--- /dev/null
+++ b/u-boot/board/astro/mcf5373l/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o fpga.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/astro/mcf5373l/astro.h b/u-boot/board/astro/mcf5373l/astro.h
new file mode 100644
index 0000000..b55a6f7
--- /dev/null
+++ b/u-boot/board/astro/mcf5373l/astro.h
@@ -0,0 +1,44 @@
+#ifndef __ASTRO_H__
+#define __ASTRO_H__
+
+/* in mcf5373l.c */
+int rs_serial_init(int port, int baud);
+void astro_put_char(char ch);
+int astro_is_char(void);
+int astro_get_char(void);
+
+/* in fpga.c */
+int astro5373l_altera_load(void);
+int astro5373l_xilinx_load(void);
+
+/* data structures used for communication (update.c) */
+typedef struct card_id {
+	char card_type;
+	char hardware_version;
+	char software_version;
+	char software_subversion;	/* " ","a".."z" */
+	char fpga_version_altera;
+	char fpga_version_xilinx;
+} card_id_t;
+
+typedef struct {
+	unsigned char mode;
+	unsigned char deviation;
+	unsigned short freq;
+} __attribute__ ((packed)) output_params_t;
+
+typedef struct {
+	unsigned short satfreq;
+	unsigned char satdatallg;
+	unsigned short symbolrate;
+	unsigned char viterbirate;
+	unsigned char symbolrate_l;
+	output_params_t output_params;
+	unsigned char reserve;
+	unsigned char card_error;
+	unsigned short dummy_ts_id;
+	unsigned char dummy_pat_ver;
+	unsigned char dummy_sdt_ver;
+} __attribute__ ((packed)) parameters_t;
+
+#endif /* __ASTRO_H__ */
diff --git a/u-boot/board/astro/mcf5373l/fpga.c b/u-boot/board/astro/mcf5373l/fpga.c
new file mode 100644
index 0000000..467461b
--- /dev/null
+++ b/u-boot/board/astro/mcf5373l/fpga.c
@@ -0,0 +1,425 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
+ * w.wegner@astro-kom.de
+ *
+ * based on the files by
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ * and
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
+
+#include <common.h>
+#include <watchdog.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int altera_pre_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+
+	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
+	writeb(0xFE, &gpiop->pclrr_timer);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int altera_config_fn(int assert_config, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_config)
+		writeb(0x04, &gpiop->ppd_uart);
+	else
+		writeb(0xFB, &gpiop->pclrr_uart);
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int altera_status_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x08)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int altera_done_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x20)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/*
+ * writes the complete buffer to the FPGA
+ * writing the complete buffer in one function is much faster,
+ * then calling it for every bit
+ */
+int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	while (bytecount < len) {
+		val = data[bytecount++];
+		i = 8;
+		do {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x01)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val >>= 1;
+			i--;
+		} while (i > 0);
+
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int altera_abort_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	writeb(0x20, &gpiop->ppd_qspi);
+	writeb(0x08, &gpiop->ppd_uart);
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int altera_post_fn(int cookie)
+{
+	return altera_abort_fn(cookie);
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	altera_pre_fn,
+	altera_config_fn,
+	altera_status_fn,
+	altera_done_fn,
+	altera_write_fn,
+	altera_abort_fn,
+	altera_post_fn
+};
+
+Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+	{Altera_CYC2,
+	 passive_serial,
+	 85903,
+	 (void *)&altera_fns,
+	 NULL,
+	 0}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_altera_load(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		altera_fns.pre = altera_pre_fn;
+		altera_fns.config = altera_config_fn;
+		altera_fns.status = altera_status_fn;
+		altera_fns.done = altera_done_fn;
+		altera_fns.write = altera_write_fn;
+		altera_fns.abort = altera_abort_fn;
+		altera_fns.post = altera_post_fn;
+		altera_fpga[i].iface_fns = (void *)&altera_fns;
+		fpga_add(fpga_altera, &altera_fpga[i]);
+	}
+	return 1;
+}
+
+/* Set the FPGA's PROG_B line to the specified level */
+int xilinx_pgm_fn(int assert, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert)
+		writeb(0xFB, &gpiop->pclrr_uart);
+	else
+		writeb(0x04, &gpiop->ppd_uart);
+	return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int xilinx_init_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
+}
+
+/* Test the state of the active-high FPGA DONE pin */
+int xilinx_done_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
+}
+
+/* Abort an FPGA operation */
+int xilinx_abort_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	/* ensure all SPI peripherals and FPGAs are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x01, &gpiop->ppd_timer);
+	writeb(0x38, &gpiop->ppd_qspi);
+	return FPGA_FAIL;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int xilinx_pre_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+	writeb(0x01, &gpiop->ppd_timer);
+
+	/* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
+	writeb(0xF7, &gpiop->pclrr_uart);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return 0;
+}
+
+/*
+ * FPGA post configuration function. Should perform a test if FPGA is running.
+ */
+int xilinx_post_config_fn(int cookie)
+{
+	int rc = 0;
+
+	/*
+	 * no test yet
+	 */
+	return rc;
+}
+
+int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_clk)
+		writeb(0x04, &gpiop->ppd_qspi);
+	else
+		writeb(0xFB, &gpiop->pclrr_qspi);
+	return assert_clk;
+}
+
+int xilinx_wr_fn(int assert_write, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_write)
+		writeb(0x01, &gpiop->ppd_qspi);
+	else
+		writeb(0xFE, &gpiop->pclrr_qspi);
+	return assert_write;
+}
+
+int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	for (bytecount = 0; bytecount < len; bytecount++) {
+		val = *(data++);
+		for (i = 8; i > 0; i--) {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x80)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val <<= 1;
+		}
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/*
+ * Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+	xilinx_pre_config_fn,
+	xilinx_pgm_fn,
+	xilinx_clk_fn,
+	xilinx_init_fn,
+	xilinx_done_fn,
+	xilinx_wr_fn,
+	0,
+	xilinx_fastwr_fn
+};
+
+Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+	{Xilinx_Spartan3,
+	 slave_serial,
+	 XILINX_XC3S4000_SIZE,
+	 (void *)&xilinx_fns,
+	 0}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_xilinx_load(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		xilinx_fns.pre = xilinx_pre_config_fn;
+		xilinx_fns.pgm = xilinx_pgm_fn;
+		xilinx_fns.clk = xilinx_clk_fn;
+		xilinx_fns.init = xilinx_init_fn;
+		xilinx_fns.done = xilinx_done_fn;
+		xilinx_fns.wr = xilinx_wr_fn;
+		xilinx_fns.bwr = xilinx_fastwr_fn;
+		xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
+		fpga_add(fpga_xilinx, &xilinx_fpga[i]);
+	}
+	return 1;
+}
diff --git a/u-boot/board/astro/mcf5373l/mcf5373l.c b/u-boot/board/astro/mcf5373l/mcf5373l.c
new file mode 100644
index 0000000..3c09a21
--- /dev/null
+++ b/u-boot/board/astro/mcf5373l/mcf5373l.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+
+/* needed for astro bus: */
+#include <asm/uart.h>
+#include "astro.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void uart_port_conf(void);
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("ASTRO MCF5373L (Urmel) Board\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
+
+	/*
+	 * GPIO configuration for bus should be set correctly from reset,
+	 * so we do not care! First, set up address space: at this point,
+	 * we should be running from internal SRAM;
+	 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+	 * and do not care where it is
+	 */
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+			&sdp->cs0);
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+			&sdp->cs1);
+	/*
+	 * I am not sure from the data sheet, but it seems burst length
+	 * has to be 8 for the 16 bit data bus we use;
+	 * so these values are for BL = 8
+	 */
+	__raw_writel(0x33211530, &sdp->cfg1);
+	__raw_writel(0x56570000, &sdp->cfg2);
+	/* send PrechargeALL, REF and IREF remain cleared! */
+	__raw_writel(0xE1462C02, &sdp->ctrl);
+	udelay(1);
+	/* refresh SDRAM twice */
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	udelay(1);
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	/* init MR  */
+	__raw_writel(0x008D0000, &sdp->mode);
+	/* initialize EMR */
+	__raw_writel(0x80010000, &sdp->mode);
+	/* wait until DLL is locked */
+	udelay(1);
+	/*
+	 * enable automatic refresh, lock mode register,
+	 * clear iref and ipall
+	 */
+	__raw_writel(0x71462C00, &sdp->ctrl);
+	/* Dummy write to start SDRAM */
+	writel(0, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+	/*
+	 * for get_ram_size() to work, both CS areas have to be
+	 * configured, i.e. CS1 has to be explicitely disabled, else
+	 * probing for memory will cause the SDRAM bus to hang!
+	 * (Do not rely on the SDCS register(s) being set to 0x00000000
+	 * during reset as stated in the data sheet.)
+	 */
+	return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+}
+
+#define UART_BASE MMAP_UART0
+int rs_serial_init(int port, int baud)
+{
+	uart_t *uart;
+	u32 counter;
+
+	switch (port) {
+	case 0:
+		uart = (uart_t *)(MMAP_UART0);
+		break;
+	case 1:
+		uart = (uart_t *)(MMAP_UART1);
+		break;
+	case 2:
+		uart = (uart_t *)(MMAP_UART2);
+		break;
+	default:
+		uart = (uart_t *)(MMAP_UART0);
+	}
+
+	uart_port_conf();
+
+	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+	writeb(UART_UCR_RESET_MR, &uart->ucr);
+	__asm__ ("nop");
+
+	writeb(0, &uart->uimr);
+
+	/* write to CSR: RX/TX baud rate from timers */
+	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
+
+	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
+
+	/* Setting up BaudRate */
+	counter = (u32) (gd->bus_clk / (baud));
+	counter >>= 5;
+
+	/* write to CTUR: divide counter upper byte */
+	writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
+	/* write to CTLR: divide counter lower byte */
+	writeb((u8) (counter & 0x00ff), &uart->ubg2);
+
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+
+	return 0;
+}
+
+void astro_put_char(char ch)
+{
+	uart_t *uart;
+	unsigned long timer;
+
+	uart = (uart_t *)(MMAP_UART0);
+	/*
+	 * Wait for last character to go. Timeout of 6ms should
+	 * be enough for our lowest baud rate of 2400.
+	 */
+	timer = get_timer(0);
+	while (get_timer(timer) < 6) {
+		if (readb(&uart->usr) & UART_USR_TXRDY)
+			break;
+	}
+	writeb(ch, &uart->utb);
+
+	return;
+}
+
+int astro_is_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	return readb(&uart->usr) & UART_USR_RXRDY;
+}
+
+int astro_get_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
+	return readb(&uart->urb);
+}
+
+int misc_init_r(void)
+{
+	int retval = 0;
+
+	puts("Configure Xilinx FPGA...");
+	retval = astro5373l_xilinx_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	puts("Configure Altera FPGA...");
+	retval = astro5373l_altera_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	return retval;
+}
diff --git a/u-boot/board/astro/mcf5373l/u-boot.lds b/u-boot/board/astro/mcf5373l/u-boot.lds
new file mode 100644
index 0000000..167a0a3
--- /dev/null
+++ b/u-boot/board/astro/mcf5373l/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf532x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+/*    *(.fixup)*/
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/atc/Makefile b/u-boot/board/atc/Makefile
new file mode 100644
index 0000000..bbfb28c
--- /dev/null
+++ b/u-boot/board/atc/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ti113x.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atc/atc.c b/u-boot/board/atc/atc.c
new file mode 100644
index 0000000..936c031
--- /dev/null
+++ b/u-boot/board/atc/atc.c
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+#if 1
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+#else
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+#endif
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+#if 0
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+#else
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* PC15 */
+#endif
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+#if 0
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+#else
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* PD4 */
+#endif
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/*
+ * UPMB initialization table
+ */
+#define	_NOT_USED_	0xFFFFFFFF
+
+static const uint rtc_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
+	0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
+	0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: ATC\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
+	memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM;
+
+	return (0);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 8 * 1024 * 1024;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/u-boot/board/atc/flash.c b/u-boot/board/atc/flash.c
new file mode 100644
index 0000000..fd76723
--- /dev/null
+++ b/u-boot/board/atc/flash.c
@@ -0,0 +1,663 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+#if 0
+		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
+#else
+		ulong flashbase = CONFIG_SYS_FLASH_BASE;
+#endif
+
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+	*dest = (FPW)0x00400040;	/* program setup		*/
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00B000B0;	/* Suspend program	*/
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW)0x00100010))
+		res = 1;	/* write failed, time out error is close enough	*/
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+	return (res);
+}
diff --git a/u-boot/board/atc/ti113x.c b/u-boot/board/atc/ti113x.c
new file mode 100644
index 0000000..ff871f6
--- /dev/null
+++ b/u-boot/board/atc/ti113x.c
@@ -0,0 +1,637 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ *
+ * Lots of code copied from:
+ *
+ * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
+ * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
+ * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_I82365
+
+#include <command.h>
+#include <pci.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#include <pcmcia/ss.h>
+#include <pcmcia/i82365.h>
+#include <pcmcia/yenta.h>
+#include <pcmcia/ti113x.h>
+
+static struct pci_device_id supported[] = {
+	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
+	{0, 0}
+};
+
+#define CYCLE_TIME	120
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev);
+#endif
+
+typedef struct socket_info_t {
+	pci_dev_t	dev;
+	u_short		bcr;
+	u_char		pci_lat, cb_lat, sub_bus, cache;
+	u_int		cb_phys;
+
+	socket_cap_t	cap;
+	u_short		type;
+	u_int		flags;
+	ti113x_state_t	state;
+} socket_info_t;
+
+static socket_info_t socket;
+static socket_state_t state;
+static struct pccard_mem_map mem;
+static struct pccard_io_map io;
+
+/*====================================================================*/
+
+/* Some PCI shortcuts */
+
+static int pci_readb (socket_info_t * s, int r, u_char * v)
+{
+	return pci_read_config_byte (s->dev, r, v);
+}
+static int pci_writeb (socket_info_t * s, int r, u_char v)
+{
+	return pci_write_config_byte (s->dev, r, v);
+}
+static int pci_readw (socket_info_t * s, int r, u_short * v)
+{
+	return pci_read_config_word (s->dev, r, v);
+}
+static int pci_writew (socket_info_t * s, int r, u_short v)
+{
+	return pci_write_config_word (s->dev, r, v);
+}
+static int pci_readl (socket_info_t * s, int r, u_int * v)
+{
+	return pci_read_config_dword (s->dev, r, v);
+}
+static int pci_writel (socket_info_t * s, int r, u_int v)
+{
+	return pci_write_config_dword (s->dev, r, v);
+}
+
+/*====================================================================*/
+
+#define cb_readb(s, r)		readb((s)->cb_phys + (r))
+#define cb_readl(s, r)		readl((s)->cb_phys + (r))
+#define cb_writeb(s, r, v)	writeb(v, (s)->cb_phys + (r))
+#define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))
+
+static u_char i365_get (socket_info_t * s, u_short reg)
+{
+	return cb_readb (s, 0x0800 + reg);
+}
+
+static void i365_set (socket_info_t * s, u_short reg, u_char data)
+{
+	cb_writeb (s, 0x0800 + reg, data);
+}
+
+static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
+{
+	i365_set (s, reg, i365_get (s, reg) | mask);
+}
+
+static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
+{
+	i365_set (s, reg, i365_get (s, reg) & ~mask);
+}
+
+#if 0	/* not used */
+static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
+{
+	u_char d = i365_get (s, reg);
+
+	i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
+}
+
+static u_short i365_get_pair (socket_info_t * s, u_short reg)
+{
+	return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
+}
+#endif	/* not used */
+
+static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
+{
+	i365_set (s, reg, data & 0xff);
+	i365_set (s, reg + 1, data >> 8);
+}
+
+/*======================================================================
+
+    Code to save and restore global state information for TI 1130 and
+    TI 1131 controllers, and to set and report global configuration
+    options.
+
+======================================================================*/
+
+static void ti113x_get_state (socket_info_t * s)
+{
+	ti113x_state_t *p = &s->state;
+
+	pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
+	pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
+	pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
+	pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
+	pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
+}
+
+static void ti113x_set_state (socket_info_t * s)
+{
+	ti113x_state_t *p = &s->state;
+
+	pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
+	pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
+	pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
+	pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
+	pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
+	pci_writel (s, TI12XX_IRQMUX, p->irqmux);
+	i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
+	i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
+}
+
+static u_int ti113x_set_opts (socket_info_t * s)
+{
+	ti113x_state_t *p = &s->state;
+	u_int mask = 0xffff;
+
+	p->cardctl &= ~TI113X_CCR_ZVENABLE;
+	p->cardctl |= TI113X_CCR_SPKROUTEN;
+
+	return mask;
+}
+
+/*======================================================================
+
+    Routines to handle common CardBus options
+
+======================================================================*/
+
+/* Default settings for PCI command configuration register */
+#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
+		  PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
+
+static void cb_get_state (socket_info_t * s)
+{
+	pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
+	pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
+	pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
+	pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
+	pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
+	pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
+}
+
+static void cb_set_state (socket_info_t * s)
+{
+	pci_writel (s, CB_LEGACY_MODE_BASE, 0);
+	pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
+	pci_writew (s, PCI_COMMAND, CMD_DFLT);
+	pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
+	pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
+	pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
+	pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
+	pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
+	pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
+}
+
+static void cb_set_opts (socket_info_t * s)
+{
+	if (s->cache == 0)
+		s->cache = 8;
+	if (s->pci_lat == 0)
+		s->pci_lat = 0xa8;
+	if (s->cb_lat == 0)
+		s->cb_lat = 0xb0;
+}
+
+/*======================================================================
+
+    Power control for Cardbus controllers: used both for 16-bit and
+    Cardbus cards.
+
+======================================================================*/
+
+static int cb_set_power (socket_info_t * s, socket_state_t * state)
+{
+	u_int reg = 0;
+
+	/* restart card voltage detection if it seems appropriate */
+	if ((state->Vcc == 0) && (state->Vpp == 0) &&
+	   !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
+		cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
+	switch (state->Vcc) {
+	case 0:
+		reg = 0;
+		break;
+	case 33:
+		reg = CB_SC_VCC_3V;
+		break;
+	case 50:
+		reg = CB_SC_VCC_5V;
+		break;
+	default:
+		return -1;
+	}
+	switch (state->Vpp) {
+	case 0:
+		break;
+	case 33:
+		reg |= CB_SC_VPP_3V;
+		break;
+	case 50:
+		reg |= CB_SC_VPP_5V;
+		break;
+	case 120:
+		reg |= CB_SC_VPP_12V;
+		break;
+	default:
+		return -1;
+	}
+	if (reg != cb_readl (s, CB_SOCKET_CONTROL))
+		cb_writel (s, CB_SOCKET_CONTROL, reg);
+
+	return 0;
+}
+
+/*======================================================================
+
+    Generic routines to get and set controller options
+
+======================================================================*/
+
+static void get_bridge_state (socket_info_t * s)
+{
+	ti113x_get_state (s);
+	cb_get_state (s);
+}
+
+static void set_bridge_state (socket_info_t * s)
+{
+	cb_set_state (s);
+	i365_set (s, I365_GBLCTL, 0x00);
+	i365_set (s, I365_GENCTL, 0x00);
+	ti113x_set_state (s);
+}
+
+static void set_bridge_opts (socket_info_t * s)
+{
+	ti113x_set_opts (s);
+	cb_set_opts (s);
+}
+
+/*====================================================================*/
+#define PD67_EXT_INDEX		0x2e	/* Extension index */
+#define PD67_EXT_DATA		0x2f	/* Extension data */
+#define PD67_EXD_VS1(s)		(0x01 << ((s)<<1))
+
+#define pd67_ext_get(s, r) \
+    (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
+
+static int i365_get_status (socket_info_t * s, u_int * value)
+{
+	u_int status;
+
+	status = i365_get (s, I365_IDENT);
+	status = i365_get (s, I365_STATUS);
+	*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
+	if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
+		*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
+	} else {
+		*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
+		*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
+	}
+	*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
+	*value |= (status & I365_CS_READY) ? SS_READY : 0;
+	*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
+
+	status = cb_readl (s, CB_SOCKET_STATE);
+	*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
+	*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
+	*value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
+	*value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
+	/* For now, ignore cards with unsupported voltage keys */
+	if (*value & SS_XVCARD)
+		*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
+
+	return 0;
+}	/* i365_get_status */
+
+static int i365_set_socket (socket_info_t * s, socket_state_t * state)
+{
+	u_char reg;
+
+	set_bridge_state (s);
+
+	/* IO card, RESET flag */
+	reg = 0;
+	reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
+	reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
+	i365_set (s, I365_INTCTL, reg);
+
+	reg = I365_PWR_NORESET;
+	if (state->flags & SS_PWR_AUTO)
+		reg |= I365_PWR_AUTO;
+	if (state->flags & SS_OUTPUT_ENA)
+		reg |= I365_PWR_OUT;
+
+	cb_set_power (s, state);
+	reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
+
+	if (reg != i365_get (s, I365_POWER))
+		i365_set (s, I365_POWER, reg);
+
+	return 0;
+}	/* i365_set_socket */
+
+/*====================================================================*/
+
+static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
+{
+	u_short base, i;
+	u_char map;
+
+	debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
+		mem->map, mem->flags, mem->speed,
+		mem->sys_start, mem->sys_stop, mem->card_start);
+
+	map = mem->map;
+	if ((map > 4) ||
+	    (mem->card_start > 0x3ffffff) ||
+	    (mem->sys_start > mem->sys_stop) ||
+	    (mem->speed > 1000)) {
+		return -1;
+	}
+
+	/* Turn off the window before changing anything */
+	if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
+		i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
+
+	/* Take care of high byte, for PCI controllers */
+	i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
+
+	base = I365_MEM (map);
+	i = (mem->sys_start >> 12) & 0x0fff;
+	if (mem->flags & MAP_16BIT)
+		i |= I365_MEM_16BIT;
+	if (mem->flags & MAP_0WS)
+		i |= I365_MEM_0WS;
+	i365_set_pair (s, base + I365_W_START, i);
+
+	i = (mem->sys_stop >> 12) & 0x0fff;
+	switch (mem->speed / CYCLE_TIME) {
+	case 0:
+		break;
+	case 1:
+		i |= I365_MEM_WS0;
+		break;
+	case 2:
+		i |= I365_MEM_WS1;
+		break;
+	default:
+		i |= I365_MEM_WS1 | I365_MEM_WS0;
+		break;
+	}
+	i365_set_pair (s, base + I365_W_STOP, i);
+
+	i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
+	if (mem->flags & MAP_WRPROT)
+		i |= I365_MEM_WRPROT;
+	if (mem->flags & MAP_ATTRIB)
+		i |= I365_MEM_REG;
+	i365_set_pair (s, base + I365_W_OFF, i);
+
+	/* Turn on the window if necessary */
+	if (mem->flags & MAP_ACTIVE)
+		i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
+	return 0;
+}	/* i365_set_mem_map */
+
+static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
+{
+	u_char map, ioctl;
+
+	map = io->map;
+	/* comment out: comparison is always false due to limited range of data type */
+	if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
+	    (io->stop < io->start))
+		return -1;
+	/* Turn off the window before changing anything */
+	if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
+		i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
+	i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
+	i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
+	ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
+	if (io->speed)
+		ioctl |= I365_IOCTL_WAIT (map);
+	if (io->flags & MAP_0WS)
+		ioctl |= I365_IOCTL_0WS (map);
+	if (io->flags & MAP_16BIT)
+		ioctl |= I365_IOCTL_16BIT (map);
+	if (io->flags & MAP_AUTOSZ)
+		ioctl |= I365_IOCTL_IOCS16 (map);
+	i365_set (s, I365_IOCTL, ioctl);
+	/* Turn on the window if necessary */
+	if (io->flags & MAP_ACTIVE)
+		i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
+	return 0;
+}	/* i365_set_io_map */
+
+/*====================================================================*/
+
+static int i82365_init (void)
+{
+	u_int val;
+	int i;
+
+	if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
+		/* Controller not found */
+		return 1;
+	}
+	debug ("i82365 Device Found!\n");
+
+	pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
+	socket.cb_phys &= ~0xf;
+
+	get_bridge_state (&socket);
+	set_bridge_opts (&socket);
+
+	i = i365_get_status (&socket, &val);
+
+	if (val & SS_DETECT) {
+		if (val & SS_3VCARD) {
+			state.Vcc = state.Vpp = 33;
+			puts (" 3.3V card found: ");
+		} else if (!(val & SS_XVCARD)) {
+			state.Vcc = state.Vpp = 50;
+			puts (" 5.0V card found: ");
+		} else {
+			puts ("i82365: unsupported voltage key\n");
+			state.Vcc = state.Vpp = 0;
+		}
+	} else {
+		/* No card inserted */
+		puts ("No card\n");
+		return 1;
+	}
+
+	state.flags = SS_IOCARD | SS_OUTPUT_ENA;
+	state.csc_mask = 0;
+	state.io_irq = 0;
+
+	i365_set_socket (&socket, &state);
+
+	for (i = 500; i; i--) {
+		if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
+			break;
+		udelay (1000);
+	}
+
+	if (i == 0) {
+		/* PC Card not ready for data transfer */
+		puts ("i82365 PC Card not ready for data transfer\n");
+		return 1;
+	}
+	debug (" PC Card ready for data transfer: ");
+
+	mem.map = 0;
+	mem.flags = MAP_ATTRIB | MAP_ACTIVE;
+	mem.speed = 300;
+	mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
+	mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
+	mem.card_start = 0;
+	i365_set_mem_map (&socket, &mem);
+
+	io.map = 0;
+	io.flags = MAP_AUTOSZ | MAP_ACTIVE;
+	io.speed = 0;
+	io.start = 0x0100;
+	io.stop = 0x010F;
+	i365_set_io_map (&socket, &io);
+
+#ifdef DEBUG
+	i82365_dump_regions (socket.dev);
+#endif
+
+	return 0;
+}
+
+static void i82365_exit (void)
+{
+	io.map = 0;
+	io.flags = 0;
+	io.speed = 0;
+	io.start = 0;
+	io.stop = 0x1;
+
+	i365_set_io_map (&socket, &io);
+
+	mem.map = 0;
+	mem.flags = 0;
+	mem.speed = 0;
+	mem.sys_start = 0;
+	mem.sys_stop = 0x1000;
+	mem.card_start = 0;
+
+	i365_set_mem_map (&socket, &mem);
+
+	socket.state.sysctl &= 0xFFFF00FF;
+
+	state.Vcc = state.Vpp = 0;
+
+	i365_set_socket (&socket, &state);
+}
+
+int pcmcia_on (void)
+{
+	u_int rc;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	rc = i82365_init();
+	if (rc)
+		goto exit;
+
+	rc = check_ide_device(0);
+	if (rc == 0)
+		goto exit;
+
+	i82365_exit();
+
+exit:
+	return rc;
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	i82365_exit();
+
+	return 0;
+}
+#endif
+
+/*======================================================================
+
+    Debug stuff
+
+======================================================================*/
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev)
+{
+	u_int tmp[2];
+	u_int *mem = (void *) socket.cb_phys;
+	u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
+	u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
+
+	pci_read_config_dword (dev, 0x00, tmp + 0);
+	pci_read_config_dword (dev, 0x80, tmp + 1);
+
+	printf ("PCI CONF: %08X ... %08X\n",
+		tmp[0], tmp[1]);
+	printf ("PCI MEM:  ... %08X ... %08X\n",
+		mem[0x8 / 4], mem[0x800 / 4]);
+	printf ("CIS:      ...%c%c%c%c%c%c%c%c...\n",
+		cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
+		cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
+	printf ("CIS CONF: %02X %02X %02X ...\n",
+		cis[0x200], cis[0x202], cis[0x204]);
+	printf ("IDE:      %02X %02X %02X %02X %02X %02X %02X %02X\n",
+		ide[0], ide[1], ide[2], ide[3],
+		ide[4], ide[5], ide[6], ide[7]);
+}
+#endif	/* DEBUG */
+
+#endif /* CONFIG_I82365 */
diff --git a/u-boot/board/atmel/at91cap9adk/Makefile b/u-boot/board/atmel/at91cap9adk/Makefile
new file mode 100644
index 0000000..2eec0ce
--- /dev/null
+++ b/u-boot/board/atmel/at91cap9adk/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= at91cap9adk.o
+COBJS-y	+= led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91cap9adk/at91cap9adk.c b/u-boot/board/atmel/at91cap9adk/at91cap9adk.c
new file mode 100644
index 0000000..2ab8bc2
--- /dev/null
+++ b/u-boot/board/atmel/at91cap9adk/at91cap9adk.c
@@ -0,0 +1,352 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+#define MP_BLOCK_3_BASE	0xFDF00000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void at91cap9_slowclock_hw_init(void)
+{
+	/*
+	 * On AT91CAP9 revC CPUs, the slow clock can be based on an
+	 * internal impreciseRC oscillator or an external 32kHz oscillator.
+	 * Switch to the latter.
+	 */
+#define ARCH_ID_AT91CAP9_REVB	0x399
+#define ARCH_ID_AT91CAP9_REVC	0x601
+	if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
+		unsigned i, tmp = at91_sys_read(AT91_SCKCR);
+		if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
+			timer_init();
+			tmp |= AT91CAP9_SCKCR_OSC32EN;
+			at91_sys_write(AT91_SCKCR, tmp);
+			for (i = 0; i < 1200; i++)
+				udelay(1000);
+			tmp |= AT91CAP9_SCKCR_OSCSEL_32;
+			at91_sys_write(AT91_SCKCR, tmp);
+			udelay(200);
+			tmp &= ~AT91CAP9_SCKCR_RCEN;
+			at91_sys_write(AT91_SCKCR, tmp);
+		}
+	}
+}
+
+static void at91cap9_nor_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Ensure EBI supply is 3.3V */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
+	/* Configure SMC CS0 for parallel flash */
+	at91_sys_write(AT91_SMC_SETUP(0),
+		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
+		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
+	at91_sys_write(AT91_SMC_PULSE(0),
+		       AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
+		       AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
+	at91_sys_write(AT91_SMC_CYCLE(0),
+		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+	at91_sys_write(AT91_SMC_MODE(0),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
+		       AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
+}
+
+#ifdef CONFIG_CMD_NAND
+static void at91cap9_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
+		       AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(1));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
+
+	/* RDY/BSY is not connected */
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91cap9_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PB22) => PHY normal mode (not Test mode)
+	 *	ERX0 (PB25) => PHY ADDR0
+	 *	ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PB22) |
+	       pin_to_mask(AT91_PIN_PB25) |
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PB22) |
+	       pin_to_mask(AT91_PIN_PB25) |
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_macb_hw_init();
+
+	/* Unlock EMAC, 3 0 2 1 sequence */
+#define MP_MAC_KEY0	0x5969cb2a
+#define MP_MAC_KEY1	0xb4a1872e
+#define MP_MAC_KEY2	0x05683fbc
+#define MP_MAC_KEY3	0x3634fba4
+#define UNLOCK_MAC	0x00000008
+	writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
+	writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
+	writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
+	writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
+	writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_NEW
+static void at91cap9_uhp_hw_init(void)
+{
+	/* Unlock USB OHCI, 3 2 0 1 sequence */
+#define MP_OHCI_KEY0	0x896c11ca
+#define MP_OHCI_KEY1	0x68ebca21
+#define MP_OHCI_KEY2	0x4823efbc
+#define MP_OHCI_KEY3	0x8651aae4
+#define UNLOCK_OHCI	0x00000010
+	writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
+	writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
+	writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
+	writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
+	writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91CAP9_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PC0, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PC0, 1);  /* power down */
+}
+
+static void at91cap9_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
+	at91_set_A_periph(AT91_PIN_PC25, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
+
+	gd->fb_base = 0;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91CAP9ADK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+	at91cap9_slowclock_hw_init();
+	at91cap9_nor_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91cap9_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	at91cap9_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91cap9_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91cap9_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/atmel/at91cap9adk/config.mk b/u-boot/board/atmel/at91cap9adk/config.mk
new file mode 100644
index 0000000..797da0e
--- /dev/null
+++ b/u-boot/board/atmel/at91cap9adk/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x73000000
diff --git a/u-boot/board/atmel/at91cap9adk/led.c b/u-boot/board/atmel/at91cap9adk/led.c
new file mode 100644
index 0000000..14aea99
--- /dev/null
+++ b/u-boot/board/atmel/at91cap9adk/led.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 0);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+}
diff --git a/u-boot/board/atmel/at91cap9adk/partition.c b/u-boot/board/atmel/at91cap9adk/partition.c
new file mode 100644
index 0000000..7e1d46f
--- /dev/null
+++ b/u-boot/board/atmel/at91cap9adk/partition.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
diff --git a/u-boot/board/atmel/at91rm9200dk/Makefile b/u-boot/board/atmel/at91rm9200dk/Makefile
new file mode 100644
index 0000000..bc3dbc6
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += flash.o
+COBJS-y += led.o
+ifdef CONFIG_HAS_DATAFLASH
+COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
+COBJS-y += partition.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91rm9200dk/at91rm9200dk.c b/u-boot/board/atmel/at91rm9200dk/at91rm9200dk.c
new file mode 100644
index 0000000..49b5fe3
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/at91rm9200dk.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <netdev.h>
+#include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_DRIVER_ETHER)
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of AT91RM9200DK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+void board_reset (void)
+{
+	AT91PS_PIO pio = AT91C_BASE_PIOA;
+
+	/* Clear PA19 to trigger the hard reset */
+	writel(0x00080000, pio->PIO_CODR);
+	writel(0x00080000, pio->PIO_OER);
+	writel(0x00080000, pio->PIO_PER);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif
+#endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if defined(CONFIG_CMD_NAND)
+extern ulong nand_probe (ulong physadr);
+
+#define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
+void nand_init (void)
+{
+	/* Setup Smart Media, fitst enable the address range of CS3 */
+	*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
+	/* set the bus interface characteristics based on
+	   tDS Data Set up Time 30 - ns
+	   tDH Data Hold Time 20 - ns
+	   tALS ALE Set up Time 20 - ns
+	   16ns at 60 MHz ~= 3  */
+/*memory mapping structures */
+#define SM_ID_RWH	(5 << 28)
+#define SM_RWH		(1 << 28)
+#define SM_RWS		(0 << 24)
+#define SM_TDF		(1 << 8)
+#define SM_NWS		(3)
+	AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
+		AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
+		SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
+
+	/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
+	*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+		AT91C_PC3_BFBAA_SMWE;
+	*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+		AT91C_PC3_BFBAA_SMWE;
+
+	/* Configure PC2 as input (signal READY of the SmartMedia) */
+	*AT91C_PIOC_PER = AT91C_PC2_BFAVD;	/* enable direct output enable */
+	*AT91C_PIOC_ODR = AT91C_PC2_BFAVD;	/* disable output */
+
+	/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
+	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
+
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
+		printf ("  No SmartMedia card inserted\n");
+#ifdef DEBUG
+	printf ("  SmartMedia card inserted\n");
+
+	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
+#endif
+	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
+}
+#endif
diff --git a/u-boot/board/atmel/at91rm9200dk/config.mk b/u-boot/board/atmel/at91rm9200dk/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/u-boot/board/atmel/at91rm9200dk/flash.c b/u-boot/board/atmel/at91rm9200dk/flash.c
new file mode 100644
index 0000000..902c3c4
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/flash.c
@@ -0,0 +1,502 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef
+{
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgAT49BV16x4[] =
+{
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{  2, 32*1024 },	/*   2 * 32 kBytes sectors */
+	{ 30, 64*1024 },	/*  30 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV16x4A[] =
+{
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 31, 64*1024 },	/*  31 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV6416[] =
+{
+	{   8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
+};
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/* AT49BV1614A Codes */
+#define FLASH_CODE1		0xAA
+#define FLASH_CODE2		0x55
+#define ID_IN_CODE		0x90
+#define ID_OUT_CODE		0xF0
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+#define CMD_SECTOR_UNLOCK	0x0070
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00005555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00002AAA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+void flash_identification (flash_info_t * info)
+{
+	volatile u16 manuf_code, device_code, add_device_code;
+
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_IN_CODE;
+
+	manuf_code = *(volatile u16 *) CONFIG_SYS_FLASH_BASE;
+	device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + 2);
+	add_device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + (3 << 1));
+
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_OUT_CODE;
+
+	/* Vendor type */
+	info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
+	printf ("Atmel: ");
+
+	if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+		if ((add_device_code & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
+			info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
+			printf ("AT49BV1614A (16Mbit)\n");
+		} else {				/* AT49BV1614 Flash */
+			info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+			printf ("AT49BV1614 (16Mbit)\n");
+		}
+
+	} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+		info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+		printf ("AT49BV6416 (64Mbit)\n");
+	}
+}
+
+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+	int i, nb_sectors = 0;
+
+	for (i=0; i<nb_blocks; i++){
+		nb_sectors += pOrgDef[i].sector_number;
+	}
+
+	return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+	volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	*addr = CMD_SECTOR_UNLOCK;
+}
+
+
+ulong flash_init (void)
+{
+	int i, j, k;
+	unsigned int flash_nb_blocks, sector;
+	unsigned int start_address;
+	OrgDef *pOrgDef;
+
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_identification (&flash_info[i]);
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+			pOrgDef = OrgAT49BV16x4;
+			flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)){	/* AT49BV1614A Flash */
+
+			pOrgDef = OrgAT49BV16x4A;
+			flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			pOrgDef = OrgAT49BV6416;
+			flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
+		} else {
+			flash_nb_blocks = 0;
+			pOrgDef = OrgAT49BV16x4;
+		}
+
+		flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
+		memset (flash_info[i].protect, 0, flash_info[i].sector_count);
+
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+
+		sector = 0;
+		start_address = flashbase;
+		flash_info[i].size = 0;
+
+		for (j = 0; j < flash_nb_blocks; j++) {
+			for (k = 0; k < pOrgDef[j].sector_number; k++) {
+				flash_info[i].start[sector++] = start_address;
+				start_address += pOrgDef[j].sector_size;
+				flash_info[i].size += pOrgDef[j].sector_size;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			/* Unlock all sectors at reset */
+			for (j=0; j<flash_info[i].sector_count; j++){
+				flash_unlock_sector(&flash_info[i], j);
+			}
+		}
+	}
+
+	/* Protect binary boot image */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + CONFIG_SYS_BOOT_SIZE - 1, &flash_info[0]);
+
+	/* Protect environment variables */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	/* Protect U-Boot gzipped image */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_U_BOOT_BASE,
+		       CONFIG_SYS_U_BOOT_BASE + CONFIG_SYS_U_BOOT_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (ATM_MANUFACT & FLASH_VENDMASK):
+		printf ("Atmel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (ATM_ID_BV1614 & FLASH_TYPEMASK):
+		printf ("AT49BV1614 (16Mbit)\n");
+		break;
+	case (ATM_ID_BV1614A & FLASH_TYPEMASK):
+		printf ("AT49BV1614A (16Mbit)\n");
+		break;
+	case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+		printf ("AT49BV6416 (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(ATM_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr = (volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {			/* it was protected */
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	};
+
+	if ((int) src & 1) {
+		printf ("unaligned source not supported\n");
+		return ERR_ALIGN;
+	};
+
+	wp = addr;
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) <<
+										   8);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	};
+
+	return ERR_OK;
+}
diff --git a/u-boot/board/atmel/at91rm9200dk/led.c b/u-boot/board/atmel/at91rm9200dk/led.c
new file mode 100644
index 0000000..47a3bfc
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/led.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+
+#define	GREEN_LED	AT91C_PIO_PB0
+#define	YELLOW_LED	AT91C_PIO_PB1
+#define	RED_LED	AT91C_PIO_PB2
+
+void	green_LED_on(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_CODR		= GREEN_LED;
+}
+
+void	 yellow_LED_on(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_CODR		= YELLOW_LED;
+}
+
+void	 red_LED_on(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_CODR		= RED_LED;
+}
+
+void	green_LED_off(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_SODR		= GREEN_LED;
+}
+
+void	yellow_LED_off(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_SODR		= YELLOW_LED;
+}
+
+void	red_LED_off(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_SODR		= RED_LED;
+}
+
+
+void coloured_LED_init (void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	AT91PS_PMC	PMC	= AT91C_BASE_PMC;
+	PMC->PMC_PCER		= (1 << AT91C_ID_PIOB);	/* Enable PIOB clock */
+	/* Disable peripherals on LEDs */
+	PIOB->PIO_PER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+	/* Enable pins as outputs */
+	PIOB->PIO_OER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+	/* Turn all LEDs OFF */
+	PIOB->PIO_SODR		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+}
diff --git a/u-boot/board/atmel/at91rm9200dk/mux.c b/u-boot/board/atmel/at91rm9200dk/mux.c
new file mode 100644
index 0000000..a00563e
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/mux.c
@@ -0,0 +1,29 @@
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+int AT91F_GetMuxStatus(void) {
+	AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */
+	AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */
+
+
+	if(AT91C_BASE_PIOB->PIO_ODSR & CONFIG_SYS_DATAFLASH_MMC_PIO)
+		return 1;
+
+	return 0;
+}
+
+void AT91F_SelectMMC(void) {
+	AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */
+	AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */
+	/* Set Output */
+	AT91C_BASE_PIOB->PIO_SODR = CONFIG_SYS_DATAFLASH_MMC_PIO;
+}
+
+void AT91F_SelectSPI(void) {
+	AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */
+	AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */
+	/* Clear Output */
+	AT91C_BASE_PIOB->PIO_CODR = CONFIG_SYS_DATAFLASH_MMC_PIO;
+}
diff --git a/u-boot/board/atmel/at91rm9200dk/partition.c b/u-boot/board/atmel/at91rm9200dk/partition.c
new file mode 100644
index 0000000..c739b11
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200dk/partition.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
diff --git a/u-boot/board/atmel/at91rm9200ek/Makefile b/u-boot/board/atmel/at91rm9200ek/Makefile
new file mode 100644
index 0000000..f64e595
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200ek/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += led.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c b/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c
new file mode 100644
index 0000000..d242583
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * derived from previous work
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+int board_init(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+
+	/*
+	 * Correct IRDA resistor problem
+	 * Set PA23_TXD in Output
+	 */
+	writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+
+	/* arch number of AT91RM9200EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	return at91emac_register(bis, (u32) AT91_EMAC_BASE);
+}
+#endif
diff --git a/u-boot/board/atmel/at91rm9200ek/led.c b/u-boot/board/atmel/at91rm9200ek/led.c
new file mode 100644
index 0000000..8d512e0
--- /dev/null
+++ b/u-boot/board/atmel/at91rm9200ek/led.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
+
+/* bit mask in PIO port B */
+#define	GREEN_LED	(1<<0)
+#define	YELLOW_LED	(1<<1)
+#define	RED_LED		(1<<2)
+
+void	green_LED_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	writel(GREEN_LED, &pio->piob.codr);
+}
+
+void	 yellow_LED_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	writel(YELLOW_LED, &pio->piob.codr);
+}
+
+void	 red_LED_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	writel(RED_LED, &pio->piob.codr);
+}
+
+void	green_LED_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	writel(GREEN_LED, &pio->piob.sodr);
+}
+
+void	yellow_LED_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	writel(YELLOW_LED, &pio->piob.sodr);
+}
+
+void	red_LED_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	writel(RED_LED, &pio->piob.sodr);
+}
+
+void coloured_LED_init (void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+
+	/* Enable PIOB clock */
+	writel(1 << AT91_ID_PIOB, &pmc->pcer);
+
+	/* Disable peripherals on LEDs */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
+	/* Enable pins as outputs */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
+	/* Turn all LEDs OFF */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
+}
diff --git a/u-boot/board/atmel/at91sam9260ek/Makefile b/u-boot/board/atmel/at91sam9260ek/Makefile
new file mode 100644
index 0000000..1fd8529
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9260ek/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= at91sam9260ek.o
+COBJS-y	+= led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c b/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c
new file mode 100644
index 0000000..64c6d17
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9260ek_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9260ek_macb_hw_init(void)
+{
+	unsigned long rstc;
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (rstc) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+#ifdef CONFIG_AT91SAM9G20EK
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
+#else
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9260ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init((1 << 0) | (1 << 1));
+#endif
+#ifdef CONFIG_MACB
+	at91sam9260ek_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/atmel/at91sam9260ek/config.mk b/u-boot/board/atmel/at91sam9260ek/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9260ek/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/atmel/at91sam9260ek/led.c b/u-boot/board/atmel/at91sam9260ek/led.c
new file mode 100644
index 0000000..2424d27
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9260ek/led.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/u-boot/board/atmel/at91sam9260ek/partition.c b/u-boot/board/atmel/at91sam9260ek/partition.c
new file mode 100644
index 0000000..2629c67
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9260ek/partition.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
diff --git a/u-boot/board/atmel/at91sam9261ek/Makefile b/u-boot/board/atmel/at91sam9261ek/Makefile
new file mode 100644
index 0000000..9d20ba0
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9261ek/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += at91sam9261ek.o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c b/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c
new file mode 100644
index 0000000..de5cfae
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9261ek_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+#ifdef CONFIG_AT91SAM9G10EK
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+#else
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+#endif
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+static void at91sam9261ek_dm9000_hw_init(void)
+{
+	/* Configure SMC CS2 for DM9000 */
+#ifdef CONFIG_AT91SAM9G10EK
+	at91_sys_write(AT91_SMC_SETUP(2),
+		       AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(2),
+		       AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) |
+		       AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8));
+	at91_sys_write(AT91_SMC_CYCLE(2),
+		       AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20));
+	at91_sys_write(AT91_SMC_MODE(2),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
+		       AT91_SMC_TDF_(1));
+#else
+	at91_sys_write(AT91_SMC_SETUP(2),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(2),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
+	at91_sys_write(AT91_SMC_CYCLE(2),
+		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+	at91_sys_write(AT91_SMC_MODE(2),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
+		       AT91_SMC_TDF_(1));
+#endif
+
+	/* Configure Reset signal as output */
+	at91_set_gpio_output(AT91_PIN_PC10, 0);
+
+	/* Configure Interrupt pin as input, no pull-up */
+	at91_set_gpio_input(AT91_PIN_PC11, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9261_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
+}
+
+static void at91sam9261ek_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+
+#ifdef CONFIG_AT91SAM9G10EK
+	gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE;
+#else
+	gd->fb_base = AT91SAM9261_SRAM_BASE;
+#endif
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+#ifdef CONFIG_AT91SAM9G10EK
+	/* arch number of AT91SAM9G10EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
+#else
+	/* arch number of AT91SAM9261EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9261ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	at91sam9261ek_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9261ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/atmel/at91sam9261ek/config.mk b/u-boot/board/atmel/at91sam9261ek/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9261ek/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/atmel/at91sam9261ek/led.c b/u-boot/board/atmel/at91sam9261ek/led.c
new file mode 100644
index 0000000..5d1c5f2
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9261ek/led.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/u-boot/board/atmel/at91sam9261ek/partition.c b/u-boot/board/atmel/at91sam9261ek/partition.c
new file mode 100644
index 0000000..c739b11
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9261ek/partition.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
diff --git a/u-boot/board/atmel/at91sam9263ek/Makefile b/u-boot/board/atmel/at91sam9263ek/Makefile
new file mode 100644
index 0000000..e43326e
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9263ek/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += at91sam9263ek.o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c b/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c
new file mode 100644
index 0000000..91efc07
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -0,0 +1,297 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9263ek_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Enable CS3 */
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_MODE_DBW_8 |
+#endif
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
+		&pmc->pcer);
+
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9263ek_macb_hw_init(void)
+{
+	unsigned long 	erstl;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIO_BASE;
+	at91_rstc_t	*rstc	= (at91_rstc_t *) AT91_RSTC_BASE;
+	/* Enable clock */
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PC25) => PHY normal mode (not Test mode)
+	 * 	ERX0 (PE25) => PHY ADDR0
+	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+
+	writel(1 << 25, &pio->pioc.pudr);
+	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
+
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+	/* Need to reset PHY -> 500ms reset */
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+	/* Wait for end hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	/* Re-enable pull-up */
+	writel(1 << 25, &pio->pioc.puer);
+	writel((1 << 25) | (1 <<26), &pio->pioe.puer);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
+}
+
+static void at91sam9263ek_lcd_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
+	gd->fb_base = AT91SAM9263_SRAM0_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+#ifndef CONFIG_SYS_NO_FLASH
+extern flash_info_t flash_info[];
+#endif
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+#ifndef CONFIG_SYS_NO_FLASH
+	ulong flash_size;
+#endif
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+#ifndef CONFIG_SYS_NO_FLASH
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+#endif
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
+		dram_size >> 20,
+		nand_size >> 20 );
+#ifndef CONFIG_SYS_NO_FLASH
+	lcd_printf (",\n  %ld MB NOR",
+		flash_size >> 20);
+#endif
+	lcd_puts ("\n");
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9263EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9263ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_set_pio_output(AT91_PIO_PORTE, 20, 1);	/* select spi0 clock */
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	at91sam9263ek_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9263ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/atmel/at91sam9263ek/config.mk b/u-boot/board/atmel/at91sam9263ek/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9263ek/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/atmel/at91sam9263ek/led.c b/u-boot/board/atmel/at91sam9263ek/led.c
new file mode 100644
index 0000000..fa1f05b
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9263ek/led.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
+		&pmc->pcer);
+
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/u-boot/board/atmel/at91sam9263ek/partition.c b/u-boot/board/atmel/at91sam9263ek/partition.c
new file mode 100644
index 0000000..7e1d46f
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9263ek/partition.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
diff --git a/u-boot/board/atmel/at91sam9m10g45ek/Makefile b/u-boot/board/atmel/at91sam9m10g45ek/Makefile
new file mode 100644
index 0000000..7aa2521
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9m10g45ek/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += at91sam9m10g45ek.o
+COBJS-y += led.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
new file mode 100644
index 0000000..f92b20f
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -0,0 +1,340 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9m10g45ek_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(3));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void at91sam9m10g45ek_usb_hw_init(void)
+{
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9m10g45ek_macb_hw_init(void)
+{
+	unsigned long rstc;
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA15) => PHY normal mode (not Test mode)
+	 * 	ERX0 (PA12) => PHY ADDR0
+	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	rstc = at91_sys_read(AT91_RSTC_MR);
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (rstc) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	vl_col:		480,
+	vl_row:		272,
+	vl_clk:		9000000,
+	vl_sync:	ATMEL_LCDC_INVLINE_NORMAL |
+			ATMEL_LCDC_INVFRAME_NORMAL,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	45,
+	vl_left_margin:	1,
+	vl_right_margin:1,
+	vl_vsync_len:	1,
+	vl_upper_margin:40,
+	vl_lower_margin:1,
+	mmio:		AT91SAM9G45_LCDC_BASE,
+};
+
+
+void lcd_enable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
+}
+
+static void at91sam9m10g45ek_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+
+	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9M10G45EK-Board */
+#ifdef CONFIG_AT91SAM9M10G45EK
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
+#elif defined CONFIG_AT91SAM9G45EKES
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	at91sam9m10g45ek_usb_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+	at91sam9m10g45ek_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+	at91sam9m10g45ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch(slave->cs) {
+		case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 0);
+			break;
+		case 0:
+		default:
+			at91_set_gpio_output(AT91_PIN_PB3, 0);
+			break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch(slave->cs) {
+		case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 1);
+			break;
+		case 0:
+		default:
+			at91_set_gpio_output(AT91_PIN_PB3, 1);
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/u-boot/board/atmel/at91sam9m10g45ek/config.mk b/u-boot/board/atmel/at91sam9m10g45ek/config.mk
new file mode 100644
index 0000000..9d3c5ae
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9m10g45ek/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x73f00000
diff --git a/u-boot/board/atmel/at91sam9m10g45ek/led.c b/u-boot/board/atmel/at91sam9m10g45ek/led.c
new file mode 100644
index 0000000..ff59a2d
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9m10g45ek/led.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/u-boot/board/atmel/at91sam9rlek/Makefile b/u-boot/board/atmel/at91sam9rlek/Makefile
new file mode 100644
index 0000000..234aeb6
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9rlek/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += at91sam9rlek.o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c b/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c
new file mode 100644
index 0000000..e374917
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91sam9rl_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9rlek_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9RL_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+}
+static void at91sam9rlek_lcd_hw_init(void)
+{
+	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
+	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDCC */
+	at91_set_B_periph(AT91_PIN_PC9, 0);	/* LCDD3 */
+	at91_set_B_periph(AT91_PIN_PC10, 0);	/* LCDD4 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* LCDD5 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD6 */
+	at91_set_B_periph(AT91_PIN_PC13, 0);	/* LCDD7 */
+	at91_set_B_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_B_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
+	at91_set_B_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_B_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
+
+	gd->fb_base = 0;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9RLEK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9rlek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_LCD
+	at91sam9rlek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
diff --git a/u-boot/board/atmel/at91sam9rlek/config.mk b/u-boot/board/atmel/at91sam9rlek/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9rlek/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/atmel/at91sam9rlek/led.c b/u-boot/board/atmel/at91sam9rlek/led.c
new file mode 100644
index 0000000..9634cc0
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9rlek/led.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/u-boot/board/atmel/at91sam9rlek/partition.c b/u-boot/board/atmel/at91sam9rlek/partition.c
new file mode 100644
index 0000000..7e1d46f
--- /dev/null
+++ b/u-boot/board/atmel/at91sam9rlek/partition.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
diff --git a/u-boot/board/atmel/atngw100/Makefile b/u-boot/board/atmel/atngw100/Makefile
new file mode 100644
index 0000000..7fbd20d
--- /dev/null
+++ b/u-boot/board/atmel/atngw100/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/atngw100/atngw100.c b/u-boot/board/atmel/atngw100/atngw100.c
new file mode 100644
index 0000000..49bc03e
--- /dev/null
+++ b/u-boot/board/atmel/atngw100/atngw100.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_16BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = uncached(EBI_SDRAM_BASE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	gd->bd->bi_phy_id[1] = 0x03;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/u-boot/board/atmel/atngw100/config.mk b/u-boot/board/atmel/atngw100/config.mk
new file mode 100644
index 0000000..ea76d05
--- /dev/null
+++ b/u-boot/board/atmel/atngw100/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE		= 0x00000000
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
diff --git a/u-boot/board/atmel/atngw100/u-boot.lds b/u-boot/board/atmel/atngw100/u-boot.lds
new file mode 100644
index 0000000..a7243f2
--- /dev/null
+++ b/u-boot/board/atmel/atngw100/u-boot.lds
@@ -0,0 +1,72 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/u-boot/board/atmel/atstk1000/Makefile b/u-boot/board/atmel/atstk1000/Makefile
new file mode 100644
index 0000000..ae47396
--- /dev/null
+++ b/u-boot/board/atmel/atstk1000/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB			:= $(obj)lib$(BOARD).o
+
+COBJS-y			+= $(BOARD).o
+COBJS-y			+= flash.o
+
+SRCS			:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS			:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/atmel/atstk1000/atstk1000.c b/u-boot/board/atmel/atstk1000/atstk1000.c
new file mode 100644
index 0000000..8b1e1b5
--- /dev/null
+++ b/u-boot/board/atmel/atstk1000/atstk1000.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+#if defined(CONFIG_ATSTK1006)
+	/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 2,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 4,
+	.txsr		= 7,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+#else
+	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
+#ifdef CONFIG_ATSTK1004
+	.data_bits	= SDRAM_DATA_16BIT,
+#else
+	.data_bits	= SDRAM_DATA_32BIT,
+#endif
+#ifdef CONFIG_ATSTK1000_16MB_SDRAM
+	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
+	.row_bits	= 12,
+#else
+	.row_bits	= 11,
+#endif
+	.col_bits	= 8,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 15.6 us */
+	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+#endif
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = uncached(EBI_SDRAM_BASE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x10;
+	gd->bd->bi_phy_id[1] = 0x11;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/atmel/atstk1000/config.mk b/u-boot/board/atmel/atstk1000/config.mk
new file mode 100644
index 0000000..8c03b77
--- /dev/null
+++ b/u-boot/board/atmel/atstk1000/config.mk
@@ -0,0 +1,4 @@
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
+CONFIG_SYS_TEXT_BASE		= 0x00000000
+LDSCRIPT		= $(src)board/atmel/atstk1000/u-boot.lds
diff --git a/u-boot/board/atmel/atstk1000/flash.c b/u-boot/board/atmel/atstk1000/flash.c
new file mode 100644
index 0000000..0ba06dd
--- /dev/null
+++ b/u-boot/board/atmel/atstk1000/flash.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATSTK1000_EXT_FLASH
+#include <asm/arch/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void flash_identify(uint16_t *flash, flash_info_t *info)
+{
+	unsigned long flags;
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+
+	writew(0xaa, flash + 0x555);
+	writew(0x55, flash + 0xaaa);
+	writew(0x90, flash + 0x555);
+	info->flash_id = readl(flash);
+	writew(0xff, flash);
+
+	readw(flash);
+
+	if (flags)
+		enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long addr;
+	unsigned int i;
+
+	flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+	flash_info[0].sector_count = 135;
+
+	flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
+
+	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+		flash_info[0].start[i] = addr;
+	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+		flash_info[0].start[i] = addr;
+
+	return CONFIG_SYS_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
+	       info->flash_id >> 16, info->flash_id & 0xffff);
+	printf("Size: %ld MB in %d sectors\n",
+	       info->size >> 10, info->sector_count);
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long flags;
+	unsigned long start_time;
+	uint16_t *fb, *sb;
+	unsigned int i;
+	int ret;
+	uint16_t status;
+
+	if ((s_first < 0) || (s_first > s_last)
+	    || (s_last >= info->sector_count)) {
+		puts("Error: first and/or last sector out of range\n");
+		return ERR_INVAL;
+	}
+
+	for (i = s_first; i < s_last; i++)
+		if (info->protect[i]) {
+			printf("Error: sector %d is protected\n", i);
+			return ERR_PROTECTED;
+		}
+
+	fb = (uint16_t *)uncached(info->start[0]);
+
+	dcache_flush_unlocked();
+
+	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+		printf("Erasing sector %3d...", i);
+
+		sb = (uint16_t *)uncached(info->start[i]);
+
+		flags = disable_interrupts();
+
+		start_time = get_timer(0);
+
+		/* Unlock sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x70, sb);
+
+		/* Erase sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x80, fb + 0x555);
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x30, sb);
+
+		/* Wait for completion */
+		ret = ERR_OK;
+		do {
+			/* TODO: Timeout */
+			status = readw(sb);
+		} while ((status != 0xffff) && !(status & 0x28));
+
+		writew(0xf0, fb);
+
+		/*
+		 * Make sure the command actually makes it to the bus
+		 * before we re-enable interrupts.
+		 */
+		readw(fb);
+
+		if (flags)
+			enable_interrupts();
+
+		if (status != 0xffff) {
+			printf("Flash erase error at address 0x%p: 0x%02x\n",
+			       sb, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (ctrlc())
+		printf("User interrupt!\n");
+
+	return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, uchar *src,
+			   ulong addr, ulong count)
+{
+	unsigned long flags;
+	uint16_t *base, *p, *s, *end;
+	uint16_t word, status, status1;
+	int ret = ERR_OK;
+
+	if (addr < info->start[0]
+	    || (addr + count) > (info->start[0] + info->size)
+	    || (addr + count) < addr) {
+		puts("Error: invalid address range\n");
+		return ERR_INVAL;
+	}
+
+	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+		puts("Error: misaligned source, destination or count\n");
+		return ERR_ALIGN;
+	}
+
+	base = (uint16_t *)uncached(info->start[0]);
+	end = (uint16_t *)uncached(addr + count);
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+	sync_write_buffer();
+
+	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+	     p < end && !ctrlc(); p++, s++) {
+		word = *s;
+
+		writew(0xaa, base + 0x555);
+		writew(0x55, base + 0xaaa);
+		writew(0xa0, base + 0x555);
+		writew(word, p);
+
+		sync_write_buffer();
+
+		/* Wait for completion */
+		status1 = readw(p);
+		do {
+			/* TODO: Timeout */
+			status = status1;
+			status1 = readw(p);
+		} while (((status ^ status1) & 0x40)	/* toggled */
+			 && !(status1 & 0x28));		/* error bits */
+
+		/*
+		 * We'll need to check once again for toggle bit
+		 * because the toggle bit may stop toggling as I/O5
+		 * changes to "1" (ref at49bv642.pdf p9)
+		 */
+		status1 = readw(p);
+		status = readw(p);
+		if ((status ^ status1) & 0x40) {
+			printf("Flash write error at address 0x%p: "
+			       "0x%02x != 0x%02x\n",
+			       p, status,word);
+			ret = ERR_PROG_ERROR;
+			writew(0xf0, base);
+			readw(base);
+			break;
+		}
+
+		writew(0xf0, base);
+		readw(base);
+	}
+
+	if (flags)
+		enable_interrupts();
+
+	return ret;
+}
+
+#endif /* CONFIG_ATSTK1000_EXT_FLASH */
diff --git a/u-boot/board/atmel/atstk1000/u-boot.lds b/u-boot/board/atmel/atstk1000/u-boot.lds
new file mode 100644
index 0000000..86ef939
--- /dev/null
+++ b/u-boot/board/atmel/atstk1000/u-boot.lds
@@ -0,0 +1,72 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss (NOLOAD) : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/u-boot/board/avnet/fx12mm/.gitignore b/u-boot/board/avnet/fx12mm/.gitignore
new file mode 100644
index 0000000..b644f59
--- /dev/null
+++ b/u-boot/board/avnet/fx12mm/.gitignore
@@ -0,0 +1 @@
+config.tmp
diff --git a/u-boot/board/avnet/fx12mm/Makefile b/u-boot/board/avnet/fx12mm/Makefile
new file mode 100644
index 0000000..f943781
--- /dev/null
+++ b/u-boot/board/avnet/fx12mm/Makefile
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+COBJS	+= $(BOARD).o
+
+include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile
diff --git a/u-boot/board/avnet/fx12mm/config.mk b/u-boot/board/avnet/fx12mm/config.mk
new file mode 100644
index 0000000..78dde62
--- /dev/null
+++ b/u-boot/board/avnet/fx12mm/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
diff --git a/u-boot/board/avnet/fx12mm/fx12mm.c b/u-boot/board/avnet/fx12mm/fx12mm.c
new file mode 100644
index 0000000..e671a7b
--- /dev/null
+++ b/u-boot/board/avnet/fx12mm/fx12mm.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Author: Xilinx Inc.
+ *
+ * Modified by:
+ *  Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	char tmp[64];
+	char *s, *e;
+	int i = getenv_f("serial", tmp, sizeof(tmp));
+
+	if (i < 0) {
+		printf("Avnet Virtex4 FX12 with no serial #");
+	} else {
+		for (e = tmp; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+		printf("Avnet Virtex4 FX12 Minimodul # ");
+		for (s = tmp; s < e; ++s)
+			putc(*s);
+	}
+	putc('\n');
+	return 0;
+}
diff --git a/u-boot/board/avnet/fx12mm/xparameters.h b/u-boot/board/avnet/fx12mm/xparameters.h
new file mode 100644
index 0000000..4410f19
--- /dev/null
+++ b/u-boot/board/avnet/fx12mm/xparameters.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * CAUTION: This file is based on the xparameters.h automatically
+ * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
+ */
+
+#ifndef __XPARAMETER_H__
+#define __XPARAMETER_H__
+
+/* RS232 */
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
+
+
+/* INT_C */
+#define XPAR_XPS_INTC_0_DEVICE_ID 0
+#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
+
+/* CPU core clock */
+#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
+#define XPAR_PLB_CLOCK_FREQ_HZ  100000000
+
+/* RAM */
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+
+/* FLASH */
+#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
+
+#endif
diff --git a/u-boot/board/avnet/v5fx30teval/.gitignore b/u-boot/board/avnet/v5fx30teval/.gitignore
new file mode 100644
index 0000000..f6418a0
--- /dev/null
+++ b/u-boot/board/avnet/v5fx30teval/.gitignore
@@ -0,0 +1 @@
+/config.tmp
diff --git a/u-boot/board/avnet/v5fx30teval/Makefile b/u-boot/board/avnet/v5fx30teval/Makefile
new file mode 100644
index 0000000..de23f29
--- /dev/null
+++ b/u-boot/board/avnet/v5fx30teval/Makefile
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+COBJS	+= $(BOARD).o
+
+include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile
diff --git a/u-boot/board/avnet/v5fx30teval/config.mk b/u-boot/board/avnet/v5fx30teval/config.mk
new file mode 100644
index 0000000..78dde62
--- /dev/null
+++ b/u-boot/board/avnet/v5fx30teval/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
diff --git a/u-boot/board/avnet/v5fx30teval/v5fx30teval.c b/u-boot/board/avnet/v5fx30teval/v5fx30teval.c
new file mode 100644
index 0000000..14a1d5d
--- /dev/null
+++ b/u-boot/board/avnet/v5fx30teval/v5fx30teval.c
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+
+int checkboard(void)
+{
+	puts("Avnet Virtex 5 FX30 Evaluation Board\n");
+	return 0;
+}
diff --git a/u-boot/board/avnet/v5fx30teval/xparameters.h b/u-boot/board/avnet/v5fx30teval/xparameters.h
new file mode 100644
index 0000000..bb657fc
--- /dev/null
+++ b/u-boot/board/avnet/v5fx30teval/xparameters.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_INTC_0_BASEADDR		0x81800000
+#define XPAR_UARTLITE_0_BASEADDR	0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xFF000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
+#define XPAR_UARTLITE_0_BAUDRATE	9600
+
+#endif
diff --git a/u-boot/board/balloon3/Makefile b/u-boot/board/balloon3/Makefile
new file mode 100644
index 0000000..29e7915
--- /dev/null
+++ b/u-boot/board/balloon3/Makefile
@@ -0,0 +1,47 @@
+#
+# Balloon3 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= balloon3.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/balloon3/balloon3.c b/u-boot/board/balloon3/balloon3.c
new file mode 100644
index 0000000..26e34e9
--- /dev/null
+++ b/u-boot/board/balloon3/balloon3.c
@@ -0,0 +1,238 @@
+/*
+ * Balloon3 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <spartan3.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void balloon3_init_fpga(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of vpac270 */
+	gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* Init the FPGA */
+	balloon3_init_fpga();
+
+	return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+	return &serial_stuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef	CONFIG_CMD_USB
+int usb_board_init(void)
+{
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+void usb_board_init_fail(void)
+{
+	return;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#if defined(CONFIG_FPGA)
+/* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
+int fpga_pgm_fn(int nassert, int nflush, int cookie)
+{
+	if (nassert)
+		writel(0x80, GPCR3);
+	else
+		writel(0x80, GPSR3);
+	if (nflush)
+		writel(0x100, GPCR3);
+	else
+		writel(0x100, GPSR3);
+	return nassert;
+}
+
+/* Check GPIO83 -- INITB */
+int fpga_init_fn(int cookie)
+{
+	return !(readl(GPLR2) & 0x80000);
+}
+
+/* Check GPIO84 -- BUSY */
+int fpga_busy_fn(int cookie)
+{
+	return !(readl(GPLR2) & 0x100000);
+}
+
+/* Check GPIO111 -- DONE */
+int fpga_done_fn(int cookie)
+{
+	return readl(GPLR3) & 0x8000;
+}
+
+/* Configure GPIO104 as GPIO and deassert it */
+int fpga_pre_config_fn(int cookie)
+{
+	writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
+	writel(0x100, GPCR3);
+	return 0;
+}
+
+/* Configure GPIO104 as nSKTSEL */
+int fpga_post_config_fn(int cookie)
+{
+	writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
+	return 0;
+}
+
+/* Toggle RDnWR */
+int fpga_wr_fn(int nassert_write, int flush, int cookie)
+{
+	udelay(1000);
+
+	if (nassert_write)
+		writel(0x100, GPCR3);
+	else
+		writel(0x100, GPSR3);
+
+	return nassert_write;
+}
+
+/* Write program to the FPGA */
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+	writeb(data, 0x10f00000);
+	return 0;
+}
+
+/* Toggle Clock pin -- NO-OP */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	return assert_clk;
+}
+
+/* Toggle ChipSelect pin -- NO-OP */
+int fpga_cs_fn(int assert_clk, int flush, int cookie)
+{
+	return assert_clk;
+}
+
+Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_init_fn,
+	NULL,	/* err */
+	fpga_done_fn,
+	fpga_clk_fn,
+	fpga_cs_fn,
+	fpga_wr_fn,
+	NULL,	/* rdata */
+	fpga_wdata_fn,
+	fpga_busy_fn,
+	NULL,	/* abort */
+	fpga_post_config_fn,
+};
+
+Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+			(void *)&balloon3_fpga_fns, 0);
+
+/* Initialize the FPGA */
+void balloon3_init_fpga(void)
+{
+	fpga_init();
+	fpga_add(fpga_xilinx, &fpga);
+}
+#else
+void balloon3_init_fpga(void) {}
+#endif /* CONFIG_FPGA */
diff --git a/u-boot/board/bc3450/Makefile b/u-boot/board/bc3450/Makefile
new file mode 100644
index 0000000..53aa651
--- /dev/null
+++ b/u-boot/board/bc3450/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o cmd_bc3450.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bc3450/bc3450.c b/u-boot/board/bc3450/bc3450.c
new file mode 100644
index 0000000..97fb5a4
--- /dev/null
+++ b/u-boot/board/bc3450/bc3450.c
@@ -0,0 +1,602 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2006
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_RTC_MPC5200
+#include <rtc.h>
+#endif
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize;
+}
+
+int checkboard (void)
+{
+#if defined (CONFIG_TQM5200)
+	puts ("Board: TQM5200 (TQ-Components GmbH)\n");
+#endif
+
+#if defined (CONFIG_BC3450)
+	puts ("Dev:   GERSYS BC3450\n");
+#endif
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;		/* clear RO	   */
+}
+
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+}
+#endif
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+	struct mpc5xxx_gpio *gpio;
+
+	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+	/*
+	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+	 * CODEC or UART mode. Consumer IrDA should still be possible.
+	 */
+	gpio->port_config &= ~(0x07000000);
+	gpio->port_config |=   0x03000000;
+
+	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+	gpio->simple_gpioe |= 0x20000000;
+
+	/* Configure GPIO_IRDA_1 as input */
+	gpio->simple_ddr &= ~(0x20000000);
+
+	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_RTC_MPC5200
+	struct rtc_time t;
+
+	/* set to Wed Dec 31 19:00:00 1969 */
+	t.tm_sec = t.tm_min = 0;
+	t.tm_hour = 19;
+	t.tm_mday = 31;
+	t.tm_mon = 12;
+	t.tm_year = 1969;
+	t.tm_wday = 3;
+
+	rtc_set(&t);
+#endif /* CONFIG_RTC_MPC5200 */
+
+#ifdef CONFIG_PS2MULT
+	ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+	return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+
+int last_stage_init (void)
+{
+	/*
+	 * auto scan for really existing devices and re-set chip select
+	 * configuration.
+	 */
+	u16 save, tmp;
+	int restore;
+
+	/*
+	 * Check for SRAM and SRAM size
+	 */
+
+	/* save original SRAM content  */
+	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
+	restore = 1;
+
+	/* write test pattern to SRAM */
+	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in SRAM detection\n");
+
+	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
+		/* no SRAM at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
+		/* make sure that we access a mirrored address */
+		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
+		__asm__ volatile ("sync");
+		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
+			/* SRAM size = 512 kByte */
+			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
+								0x80000);
+			__asm__ volatile ("sync");
+			puts ("SRAM:  512 kB\n");
+		}
+		else
+			puts ("!! possible error in SRAM detection\n");
+	} else {
+		puts ("SRAM:  1 MB\n");
+	}
+	/* restore origianl SRAM content  */
+	if (restore) {
+		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
+		__asm__ volatile ("sync");
+	}
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+		/* no grafic controller at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else {
+		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
+	}
+	/* restore origianl FB content	*/
+	if (restore) {
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define DISPLAY_WIDTH	640
+#define DISPLAY_HEIGHT	480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
+	/* FP only */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x01013106},
+	{0x80004, 0xc428bb17},
+	{0x80000, 0x03013106},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a028b},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e9},
+	{0x80200, 0x00010200},
+	{0x80000, 0x0f013106},
+#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
+	/* CRT only */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x10090a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x10090a01},
+	{0x00054, 0x0},
+	{0x80200, 0x00010000},
+	{0x80204, 0x0},
+	{0x80208, 0x0A000A00},
+	{0x8020C, 0x02fa027f},
+	{0x80210, 0x004a028b},
+	{0x80214, 0x020c01df},
+	{0x80218, 0x000201e9},
+	{0x80200, 0x00013306},
+#else	/* panel + CRT */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x0f013106},
+	{0x80004, 0xc428bb17},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a028b},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e9},
+	{0x80200, 0x00010000},
+#endif
+	{0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+#if defined (CONFIG_TQM5200)
+	    strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#else
+#error No supported board selected
+#endif /* CONFIG_TQM5200 */
+
+#if defined (CONFIG_BC3450)
+	} else if (line_number == 2) {
+	    strcpy (info, " Dev:   GERSYS BC3450");
+#endif /* CONFIG_BC3450 */
+	}
+	else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+	u16 save, tmp;
+	int restore, ret;
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+		/* no grafic controller found */
+		restore = 0;
+		ret = 0;
+	} else {
+	    ret = SM501_MMIO_BASE;
+	}
+
+	if (restore) {
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+	return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/bc3450/cmd_bc3450.c b/u-boot/board/bc3450/cmd_bc3450.c
new file mode 100644
index 0000000..a9e4902
--- /dev/null
+++ b/u-boot/board/bc3450/cmd_bc3450.c
@@ -0,0 +1,828 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+/*
+ * BC3450 specific commands
+ */
+#if defined(CONFIG_CMD_BSP)
+
+#undef DEBUG
+#ifdef DEBUG
+# define dprintf(fmt,args...)	printf(fmt, ##args)
+#else
+# define dprintf(fmt,args...)
+#endif
+
+/*
+ * Definitions for DS1620 chip
+ */
+#define THERM_START_CONVERT	0xee
+#define THERM_RESET		0xaf
+#define THERM_READ_CONFIG	0xac
+#define THERM_READ_TEMP		0xaa
+#define THERM_READ_TL		0xa2
+#define THERM_READ_TH		0xa1
+#define THERM_WRITE_CONFIG	0x0c
+#define THERM_WRITE_TL		0x02
+#define THERM_WRITE_TH		0x01
+
+#define CONFIG_SYS_CPU			2
+#define CONFIG_SYS_1SHOT		1
+#define CONFIG_SYS_STANDALONE		0
+
+struct therm {
+	int hi;
+	int lo;
+};
+
+/*
+ * SM501 Register
+ */
+#define SM501_GPIO_CTRL_LOW		0x00000008UL	/* gpio pins 0..31  */
+#define SM501_GPIO_CTRL_HIGH		0x0000000CUL	/* gpio pins 32..63 */
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_LOW		0x00010000UL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+#define SM501_CRT_DISPLAY_CONTROL	0x00080200UL
+
+/* SM501 CRT Display Control Bits */
+#define SM501_CDC_SEL			(1 << 9)
+#define SM501_CDC_TE			(1 << 8)
+#define SM501_CDC_E			(1 << 2)
+
+/* SM501 Panel Display Control Bits */
+#define SM501_PDC_FPEN			(1 << 27)
+#define SM501_PDC_BIAS			(1 << 26)
+#define SM501_PDC_DATA			(1 << 25)
+#define SM501_PDC_VDDEN			(1 << 24)
+
+/* SM501 GPIO Data LOW Bits */
+#define SM501_GPIO24			0x01000000
+#define SM501_GPIO25			0x02000000
+#define SM501_GPIO26			0x04000000
+#define SM501_GPIO27			0x08000000
+#define SM501_GPIO28			0x10000000
+#define SM501_GPIO29			0x20000000
+#define SM501_GPIO30			0x40000000
+#define SM501_GPIO31			0x80000000
+
+/* SM501 GPIO Data HIGH Bits */
+#define SM501_GPIO46			0x00004000
+#define SM501_GPIO47			0x00008000
+#define SM501_GPIO48			0x00010000
+#define SM501_GPIO49			0x00020000
+#define SM501_GPIO50			0x00040000
+#define SM501_GPIO51			0x00080000
+
+/* BC3450 GPIOs @ SM501 Data LOW */
+#define DIP				(SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
+#define DS1620_DQ			SM501_GPIO29	/* I/O             */
+#define DS1620_CLK			SM501_GPIO30	/* High active O/P */
+#define DS1620_RES			SM501_GPIO31	/* Low active O/P  */
+/* BC3450 GPIOs @ SM501 Data HIGH */
+#define BUZZER				SM501_GPIO47	/* Low active O/P  */
+#define DS1620_TLOW			SM501_GPIO48	/* High active I/P */
+#define PWR_OFF				SM501_GPIO49	/* Low active O/P  */
+#define FP_DATA_TRI			SM501_GPIO50	/* High active O/P */
+
+
+/*
+ * Initialise GPIO on SM501
+ *
+ * This function may be called from several other functions.
+ * Yet, the initialisation sequence is executed only the first
+ * time the function is called.
+ */
+int sm501_gpio_init (void)
+{
+	static int init_done = 0;
+
+	if (init_done) {
+/*	dprintf("sm501_gpio_init: nothing to be done.\n"); */
+		return 1;
+	}
+
+	/* enable SM501 GPIO control (in both power modes) */
+	*(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	*(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+
+	/* set up default O/Ps */
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+		~(DS1620_RES | DS1620_CLK);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+		~(FP_DATA_TRI);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
+		(BUZZER | PWR_OFF);
+
+	/* configure directions for SM501 GPIO pins */
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
+		~(0x3F << 14);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
+		~(DIP | DS1620_DQ);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |=
+		(DS1620_RES | DS1620_CLK);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
+		~DS1620_TLOW;
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |=
+		(PWR_OFF | BUZZER | FP_DATA_TRI);
+
+	init_done = 1;
+/*  dprintf("sm501_gpio_init: done.\n"); */
+	return 0;
+}
+
+
+/*
+ * dip - read Config Inputs
+ *
+ * read and prints the dip switch
+ * and/or external config inputs (4bits) 0...0x0F
+ */
+int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	vu_long rc = 0;
+
+	sm501_gpio_init ();
+
+	/* read dip switch */
+	rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+	rc = ~rc;
+	rc &= DIP;
+	rc = (int) (rc >> 24);
+
+	/* plausibility check */
+	if (rc > 0x0F)
+		return -1;
+
+	printf ("0x%lx\n", rc);
+	return 0;
+}
+
+U_BOOT_CMD (dip, 1, 1, cmd_dip,
+	    "read dip switch and config inputs",
+	    "\n"
+	    "     - prints the state of the dip switch and/or\n"
+	    "       external configuration inputs as hex value.\n"
+	    "     - \"Config 1\" is the LSB");
+
+
+/*
+ * buz - turns Buzzer on/off
+ */
+#ifdef CONFIG_BC3450_BUZZER
+static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2) {
+		printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+		return 1;
+	}
+
+	sm501_gpio_init ();
+
+	if (strncmp (argv[1], "on", 2) == 0) {
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+			~(BUZZER);
+		return 0;
+	} else if (strncmp (argv[1], "off", 3) == 0) {
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
+			BUZZER;
+		return 0;
+	}
+	printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+	return 1;
+}
+
+U_BOOT_CMD (buz, 2, 1, cmd_buz,
+	    "turns buzzer on/off",
+	    "\n" "buz <on/off>\n" "     - turns the buzzer on or off");
+#endif /* CONFIG_BC3450_BUZZER */
+
+
+/*
+ * fp - front panel commands
+ */
+static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	sm501_gpio_init ();
+
+	if (strncmp (argv[1], "on", 2) == 0) {
+		/* turn on VDD first */
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
+		udelay (1000);
+		/* then put data on */
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
+		/* wait some time and enable backlight */
+		udelay (1000);
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+		udelay (1000);
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+		return 0;
+	} else if (strncmp (argv[1], "off", 3) == 0) {
+		/* turn off the backlight first */
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+		udelay (1000);
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+		udelay (200000);
+		/* wait some time, then remove data */
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
+		udelay (1000);
+		/* and remove VDD last */
+		*(vu_long *) (SM501_MMIO_BASE +
+			      SM501_PANEL_DISPLAY_CONTROL) &=
+			~SM501_PDC_VDDEN;
+		return 0;
+	} else if (strncmp (argv[1], "bl", 2) == 0) {
+		/* turn on/off backlight only */
+		if (strncmp (argv[2], "on", 2) == 0) {
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_PANEL_DISPLAY_CONTROL) |=
+				SM501_PDC_BIAS;
+			udelay (1000);
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_PANEL_DISPLAY_CONTROL) |=
+				SM501_PDC_FPEN;
+			return 0;
+		} else if (strncmp (argv[2], "off", 3) == 0) {
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_PANEL_DISPLAY_CONTROL) &=
+				~SM501_PDC_FPEN;
+			udelay (1000);
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_PANEL_DISPLAY_CONTROL) &=
+				~SM501_PDC_BIAS;
+			return 0;
+		}
+	}
+#ifdef CONFIG_BC3450_CRT
+	else if (strncmp (argv[1], "crt", 3) == 0) {
+		/* enables/disables the crt output (debug only) */
+		if (strncmp (argv[2], "on", 2) == 0) {
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_CRT_DISPLAY_CONTROL) |=
+				(SM501_CDC_TE | SM501_CDC_E);
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_CRT_DISPLAY_CONTROL) &=
+				~SM501_CDC_SEL;
+			return 0;
+		} else if (strncmp (argv[2], "off", 3) == 0) {
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_CRT_DISPLAY_CONTROL) &=
+				~(SM501_CDC_TE | SM501_CDC_E);
+			*(vu_long *) (SM501_MMIO_BASE +
+				      SM501_CRT_DISPLAY_CONTROL) |=
+				SM501_CDC_SEL;
+			return 0;
+		}
+	}
+#endif /* CONFIG_BC3450_CRT */
+	printf ("Usage:%s\n", cmdtp->help);
+	return 1;
+}
+
+U_BOOT_CMD (fp, 3, 1, cmd_fp,
+	    "front panes access functions",
+	    "\n"
+	    "fp bl <on/off>\n"
+	    "     - turns the CCFL backlight of the display on/off\n"
+	    "fp <on/off>\n" "     - turns the whole display on/off"
+#ifdef CONFIG_BC3450_CRT
+	    "\n"
+	    "fp crt <on/off>\n"
+	    "     - enables/disables the crt output (debug only)"
+#endif /* CONFIG_BC3450_CRT */
+	);
+
+/*
+ * temp - DS1620 thermometer
+ */
+/* GERSYS BC3450 specific functions */
+static inline void bc_ds1620_set_clk (int clk)
+{
+	if (clk)
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
+			DS1620_CLK;
+	else
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+			~DS1620_CLK;
+}
+
+static inline void bc_ds1620_set_data (int dat)
+{
+	if (dat)
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
+			DS1620_DQ;
+	else
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+			~DS1620_DQ;
+}
+
+static inline int bc_ds1620_get_data (void)
+{
+	vu_long rc;
+
+	rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+	rc &= DS1620_DQ;
+	if (rc != 0)
+		rc = 1;
+	return (int) rc;
+}
+
+static inline void bc_ds1620_set_data_dir (int dir)
+{
+	if (dir)		/* in */
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
+	else			/* out */
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
+}
+
+static inline void bc_ds1620_set_reset (int res)
+{
+	if (res)
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
+	else
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
+}
+
+/* hardware independent functions */
+static void ds1620_send_bits (int nr, int value)
+{
+	int i;
+
+	for (i = 0; i < nr; i++) {
+		bc_ds1620_set_data (value & 1);
+		bc_ds1620_set_clk (0);
+		udelay (1);
+		bc_ds1620_set_clk (1);
+		udelay (1);
+
+		value >>= 1;
+	}
+}
+
+static unsigned int ds1620_recv_bits (int nr)
+{
+	unsigned int value = 0, mask = 1;
+	int i;
+
+	bc_ds1620_set_data (0);
+
+	for (i = 0; i < nr; i++) {
+		bc_ds1620_set_clk (0);
+		udelay (1);
+
+		if (bc_ds1620_get_data ())
+			value |= mask;
+
+		mask <<= 1;
+
+		bc_ds1620_set_clk (1);
+		udelay (1);
+	}
+
+	return value;
+}
+
+static void ds1620_out (int cmd, int bits, int value)
+{
+	bc_ds1620_set_clk (1);
+	bc_ds1620_set_data_dir (0);
+
+	bc_ds1620_set_reset (0);
+	udelay (1);
+	bc_ds1620_set_reset (1);
+
+	udelay (1);
+
+	ds1620_send_bits (8, cmd);
+	if (bits)
+		ds1620_send_bits (bits, value);
+
+	udelay (1);
+
+	/* go stand alone */
+	bc_ds1620_set_data_dir (1);
+	bc_ds1620_set_reset (0);
+	bc_ds1620_set_clk (0);
+
+	udelay (10000);
+}
+
+static unsigned int ds1620_in (int cmd, int bits)
+{
+	unsigned int value;
+
+	bc_ds1620_set_clk (1);
+	bc_ds1620_set_data_dir (0);
+
+	bc_ds1620_set_reset (0);
+	udelay (1);
+	bc_ds1620_set_reset (1);
+
+	udelay (1);
+
+	ds1620_send_bits (8, cmd);
+
+	bc_ds1620_set_data_dir (1);
+	value = ds1620_recv_bits (bits);
+
+	/* go stand alone */
+	bc_ds1620_set_data_dir (1);
+	bc_ds1620_set_reset (0);
+	bc_ds1620_set_clk (0);
+
+	return value;
+}
+
+static int cvt_9_to_int (unsigned int val)
+{
+	if (val & 0x100)
+		val |= 0xfffffe00;
+
+	return val;
+}
+
+/* set thermostate thresholds */
+static void ds1620_write_state (struct therm *therm)
+{
+	ds1620_out (THERM_WRITE_TL, 9, therm->lo);
+	ds1620_out (THERM_WRITE_TH, 9, therm->hi);
+	ds1620_out (THERM_START_CONVERT, 0, 0);
+}
+
+static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	struct therm therm;
+
+	sm501_gpio_init ();
+
+	/* print temperature */
+	if (argc == 1) {
+		i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
+		printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
+		return 0;
+	}
+
+	/* set to default operation */
+	if (strncmp (argv[1], "set", 3) == 0) {
+		if (strncmp (argv[2], "default", 3) == 0) {
+			therm.hi = +88;
+			therm.lo = -20;
+			therm.hi <<= 1;
+			therm.lo <<= 1;
+			ds1620_write_state (&therm);
+			ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
+			return 0;
+		}
+	}
+
+	printf ("Usage:%s\n", cmdtp->help);
+	return 1;
+}
+
+U_BOOT_CMD (temp, 3, 1, cmd_temp,
+	    "print current temperature",
+	    "\n" "temp\n" "     - print current temperature");
+
+#ifdef CONFIG_BC3450_CAN
+/*
+ * Initialise CAN interface
+ *
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init (void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
+
+	/* GPIO configuration of the CAN pins is done in BC3450.h */
+
+	if (!init_done) {
+		/* init CAN 1 */
+		can1->canctl1 |= 0x80;	/* CAN enable */
+		udelay (100);
+
+		i = 0;
+		can1->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can1->canctl1 & 0x02)) {
+			udelay (10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not enter sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		i = 0;
+		can1->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can1->canctl1 & 0x01)) {
+			udelay (10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can1->canctl1 = 0x80;
+		can1->canctl1 |= 0x40;
+		can1->canbtr0 = 0x0F;
+		can1->canbtr1 = 0x7F;
+		can1->canidac &= ~(0x30);
+		can1->canidar1 = 0x00;
+		can1->canidar3 = 0x00;
+		can1->canidar5 = 0x00;
+		can1->canidar7 = 0x00;
+		can1->canidmr0 = 0xFF;
+		can1->canidmr1 = 0xFF;
+		can1->canidmr2 = 0xFF;
+		can1->canidmr3 = 0xFF;
+		can1->canidmr4 = 0xFF;
+		can1->canidmr5 = 0xFF;
+		can1->canidmr6 = 0xFF;
+		can1->canidmr7 = 0xFF;
+
+		i = 0;
+		can1->canctl0 &= ~(0x01);	/* leave init mode */
+		can1->canctl0 &= ~(0x02);
+		/* wait until init and sleep mode left */
+		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+			udelay (10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+
+		/* init CAN 2 */
+		can2->canctl1 |= 0x80;	/* CAN enable */
+		udelay (100);
+
+		i = 0;
+		can2->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can2->canctl1 & 0x02)) {
+			udelay (10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		i = 0;
+		can2->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can2->canctl1 & 0x01)) {
+			udelay (10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can2->canctl1 = 0x80;
+		can2->canctl1 |= 0x40;
+		can2->canbtr0 = 0x0F;
+		can2->canbtr1 = 0x7F;
+		can2->canidac &= ~(0x30);
+		can2->canidar1 = 0x00;
+		can2->canidar3 = 0x00;
+		can2->canidar5 = 0x00;
+		can2->canidar7 = 0x00;
+		can2->canidmr0 = 0xFF;
+		can2->canidmr1 = 0xFF;
+		can2->canidmr2 = 0xFF;
+		can2->canidmr3 = 0xFF;
+		can2->canidmr4 = 0xFF;
+		can2->canidmr5 = 0xFF;
+		can2->canidmr6 = 0xFF;
+		can2->canidmr7 = 0xFF;
+		can2->canctl0 &= ~(0x01);	/* leave init mode */
+		can2->canctl0 &= ~(0x02);
+
+		i = 0;
+		/* wait until init mode left */
+		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+			udelay (10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		init_done = 1;
+	}
+	return 0;
+}
+
+/*
+ * Do CAN test
+ * by sending message between CAN1 and CAN2
+ *
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can (char * const argv[])
+{
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
+
+	/* send a message on CAN1 */
+	can1->cantbsel = 0x01;
+	can1->cantxfg.idr[0] = 0x55;
+	can1->cantxfg.idr[1] = 0x00;
+	can1->cantxfg.idr[1] &= ~0x8;
+	can1->cantxfg.idr[1] &= ~0x10;
+	can1->cantxfg.dsr[0] = 0xCC;
+	can1->cantxfg.dlr = 1;
+	can1->cantxfg.tbpr = 0;
+	can1->cantflg = 0x01;
+
+	i = 0;
+	while ((can1->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 send timeout, "
+				"can not send message!\n", __FUNCTION__);
+			return 1;
+		}
+		udelay (1000);
+	}
+	udelay (1000);
+
+	i = 0;
+	while (!(can2->canrflg & 0x01)) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 receive timeout, "
+				"no message received!\n", __FUNCTION__);
+			return 1;
+		}
+		udelay (1000);
+	}
+
+	if (can2->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN2 receive error, "
+			"data mismatch!\n", __FUNCTION__);
+		return 1;
+	}
+
+	/* send a message on CAN2 */
+	can2->cantbsel = 0x01;
+	can2->cantxfg.idr[0] = 0x55;
+	can2->cantxfg.idr[1] = 0x00;
+	can2->cantxfg.idr[1] &= ~0x8;
+	can2->cantxfg.idr[1] &= ~0x10;
+	can2->cantxfg.dsr[0] = 0xCC;
+	can2->cantxfg.dlr = 1;
+	can2->cantxfg.tbpr = 0;
+	can2->cantflg = 0x01;
+
+	i = 0;
+	while ((can2->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 send error, "
+				"can not send message!\n", __FUNCTION__);
+			return 1;
+		}
+		udelay (1000);
+	}
+	udelay (1000);
+
+	i = 0;
+	while (!(can1->canrflg & 0x01)) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 receive timeout, "
+				"no message received!\n", __FUNCTION__);
+			return 1;
+		}
+		udelay (1000);
+	}
+
+	if (can1->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN1 receive error 0x%02x\n",
+			__FUNCTION__, (can1->canrxfg.dsr[0]));
+		return 1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BC3450_CAN */
+
+/*
+ * test - BC3450 HW test routines
+ */
+int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_BC3450_CAN
+	int rcode;
+
+	can_init ();
+#endif /* CONFIG_BC3450_CAN */
+
+	sm501_gpio_init ();
+
+	if (argc != 2) {
+		printf ("Usage:%s\n", cmdtp->help);
+		return 1;
+	}
+
+	if (strncmp (argv[1], "unit-off", 8) == 0) {
+		printf ("waiting 2 seconds...\n");
+		udelay (2000000);
+		*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+			~PWR_OFF;
+		return 0;
+	}
+#ifdef CONFIG_BC3450_CAN
+	else if (strncmp (argv[1], "can", 2) == 0) {
+		rcode = do_can (argv);
+		if (simple_strtoul (argv[2], NULL, 10) == 2) {
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+		}
+		return rcode;
+	}
+#endif /* CONFIG_BC3450_CAN */
+
+	printf ("Usage:%s\n", cmdtp->help);
+	return 1;
+}
+
+U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
+#ifdef CONFIG_BC3450_CAN
+	"test can\n"
+	"     - connect CAN1 (X8) with CAN2 (X9) for this test\n"
+#endif /* CONFIG_BC3450_CAN */
+	"test unit-off\n"
+	"     - turns off the BC3450 unit\n"
+	"       WARNING: Unsaved environment variables will be lost!"
+);
+#endif
diff --git a/u-boot/board/bc3450/mt48lc16m16a2-75.h b/u-boot/board/bc3450/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..48b4321
--- /dev/null
+++ b/u-boot/board/bc3450/mt48lc16m16a2-75.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/u-boot/board/bct-brettl2/Makefile b/u-boot/board/bct-brettl2/Makefile
new file mode 100644
index 0000000..b268815
--- /dev/null
+++ b/u-boot/board/bct-brettl2/Makefile
@@ -0,0 +1,51 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o cled.o
+COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/bct-brettl2/bct-brettl2.c b/u-boot/board/bct-brettl2/bct-brettl2.c
new file mode 100644
index 0000000..de5b9ff
--- /dev/null
+++ b/u-boot/board/bct-brettl2/bct-brettl2.c
@@ -0,0 +1,123 @@
+/*
+ * U-boot - main board file for BCT brettl2
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/gpio.h>
+#include <asm/net.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+
+#include "../cm-bf537e/gpio_cfi_flash.h"
+#include "smsc9303.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: bct-brettl2 board\n");
+	printf("       Support: http://www.bct-electronic.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int retry = 3;
+	int ret;
+
+	ret = bfin_EMAC_initialize(bis);
+
+	uchar enetaddr[6];
+	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		printf("setting MAC %pM\n", enetaddr);
+	}
+	puts("       ");
+
+	puts("initialize SMSC LAN9303i ethernet switch\n");
+
+	while (retry-- > 0) {
+		if (init_smsc9303i_mii())
+			return ret;
+	}
+
+	return ret;
+}
+#endif
+
+static void init_tlv320aic31(void)
+{
+	puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
+	peripheral_request(P_TMR0, "tlv320aic31 clock");
+	bfin_write_TIMER0_CONFIG(0x020d);
+	bfin_write_TIMER0_PERIOD(0x0008);
+	bfin_write_TIMER0_WIDTH(0x0008/2);
+	bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
+	SSYNC();
+	udelay(10000);
+
+	puts("       resetting tlv320aic31\n");
+
+	gpio_request(GPIO_PF2, "tlv320aic31");
+	gpio_direction_output(GPIO_PF2, 0);
+	udelay(10000);
+	gpio_direction_output(GPIO_PF2, 1);
+	udelay(10000);
+	gpio_free(GPIO_PF2);
+}
+
+static void init_mute_pin(void)
+{
+	printf("       unmute class D amplifier\n");
+
+	gpio_request(GPIO_PF5, "mute");
+	gpio_direction_output(GPIO_PF5, 1);
+	gpio_free(GPIO_PF5);
+}
+
+/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
+static void turn_leds_off(void)
+{
+	printf("       turn LEDs off\n");
+
+	gpio_request(GPIO_PF6, "led");
+	gpio_direction_output(GPIO_PF6, 0);
+	gpio_free(GPIO_PF6);
+
+	gpio_request(GPIO_PF15, "led");
+	gpio_direction_output(GPIO_PF15, 0);
+	gpio_free(GPIO_PF15);
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+	init_tlv320aic31();
+	init_mute_pin();
+	turn_leds_off();
+
+	return 0;
+}
diff --git a/u-boot/board/bct-brettl2/cled.c b/u-boot/board/bct-brettl2/cled.c
new file mode 100644
index 0000000..dcb91bd
--- /dev/null
+++ b/u-boot/board/bct-brettl2/cled.c
@@ -0,0 +1,32 @@
+/*
+ * cled.c - control color led
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+
+int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr = 0x20000000 + 0x200000; /* AMS2 */
+	uchar data;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	data = simple_strtoul(argv[1], NULL, 10);
+	outb(data, addr);
+
+	printf("cled, write %02x\n", data);
+
+	return 0;
+}
+
+U_BOOT_CMD(cled, 2, 0, do_cled,
+	"set/clear color LED",
+	"");
diff --git a/u-boot/board/bct-brettl2/config.mk b/u-boot/board/bct-brettl2/config.mk
new file mode 100644
index 0000000..0c02d44
--- /dev/null
+++ b/u-boot/board/bct-brettl2/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf536-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bct-brettl2/gpio_cfi_flash.c b/u-boot/board/bct-brettl2/gpio_cfi_flash.c
new file mode 100644
index 0000000..b385c7f
--- /dev/null
+++ b/u-boot/board/bct-brettl2/gpio_cfi_flash.c
@@ -0,0 +1,4 @@
+#define GPIO_PIN_1 GPIO_PG5
+#define GPIO_PIN_2 GPIO_PG6
+#define GPIO_PIN_3 GPIO_PG7
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/u-boot/board/bct-brettl2/smsc9303.c b/u-boot/board/bct-brettl2/smsc9303.c
new file mode 100644
index 0000000..15eea7a
--- /dev/null
+++ b/u-boot/board/bct-brettl2/smsc9303.c
@@ -0,0 +1,176 @@
+/*
+ * smsc9303.c - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <miiphy.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
+{
+	const char *devname = miiphy_get_current_dev();
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_write(devname, addr, reg, data) != 0)
+	    return 0;
+
+	return 1;
+}
+
+static int smc9303i_write_reg(unsigned short reg, unsigned int data)
+{
+	const char *devname = miiphy_get_current_dev();
+	unsigned char mii_addr = 0x10 | (reg >> 6);
+	unsigned char mii_reg = (reg & 0x3c) >> 1;
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
+	    return 0;
+
+	if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
+	    return 0;
+
+	return 1;
+}
+
+static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
+{
+	const char *devname = miiphy_get_current_dev();
+	unsigned char mii_addr = 0x10 | (reg >> 6);
+	unsigned char mii_reg = (reg & 0x3c) >> 1;
+	unsigned short tmp1, tmp2;
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
+	    return 0;
+
+	if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
+	    return 0;
+
+	*data = (tmp2 << 16) | tmp1;
+
+	return 1;
+}
+
+#if 0
+static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
+{
+	const char *devname = miiphy_get_current_dev();
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_read(devname, addr, reg, data) != 0)
+	    return 0;
+
+	return 1;
+}
+#endif
+
+typedef struct {
+	unsigned short reg;
+	unsigned int value;
+} smsc9303i_config_entry1_t;
+
+static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
+{
+	{0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
+	{0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
+	{0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
+};
+
+typedef struct
+{
+	unsigned char addr;
+	unsigned char reg;
+	unsigned short value;
+} smsc9303i_config_entry2_t;
+
+static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
+{
+	{0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
+	{0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
+	{0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
+
+	{0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
+	{0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
+	{0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
+
+	{0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
+	{0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
+	{0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
+
+	{0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
+	{0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
+	{0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
+	{0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
+	{0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
+	{0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
+	{0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
+	{0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
+	{0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
+};
+
+int init_smsc9303i_mii(void)
+{
+	unsigned int data;
+	unsigned int i;
+
+	printf("       reset SMSC LAN9303i\n");
+
+	gpio_request(GPIO_PG10, "smsc9303");
+	gpio_direction_output(GPIO_PG10, 0);
+	udelay(10000);
+	gpio_direction_output(GPIO_PG10, 1);
+	udelay(10000);
+
+	gpio_free(GPIO_PG10);
+
+#if defined(CONFIG_MII_INIT)
+	mii_init();
+#endif
+
+	printf("       write SMSC LAN9303i configuration\n");
+
+	if (!smc9303i_read_reg(0x50, &data))
+		return 0;
+
+	if ((data >> 16) != 0x9303)	{
+		/* chip id not found */
+		printf("       error identifying SMSC LAN9303i\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
+		const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
+
+		if (!smc9303i_write_reg(entry->reg, entry->value)) {
+			printf("       error writing SMSC LAN9303i configuration\n");
+			return 0;
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
+		const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
+
+		if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
+			printf("       error writing SMSC LAN9303i configuration\n");
+			return 0;
+		}
+	}
+
+	return 1;
+}
diff --git a/u-boot/board/bct-brettl2/smsc9303.h b/u-boot/board/bct-brettl2/smsc9303.h
new file mode 100644
index 0000000..a4ba40e
--- /dev/null
+++ b/u-boot/board/bct-brettl2/smsc9303.h
@@ -0,0 +1,9 @@
+/*
+ * smsc9303.h - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+int init_smsc9303i_mii(void);
diff --git a/u-boot/board/bf518f-ezbrd/Makefile b/u-boot/board/bf518f-ezbrd/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf518f-ezbrd/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf518f-ezbrd/bf518f-ezbrd.c b/u-boot/board/bf518f-ezbrd/bf518f-ezbrd.c
new file mode 100644
index 0000000..ff1ac4c
--- /dev/null
+++ b/u-boot/board/bf518f-ezbrd/bf518f-ezbrd.c
@@ -0,0 +1,162 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/otp.h>
+#include <asm/sdh.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF518F EZ-Board board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	bool valid_mac = false;
+
+#if 0
+	/* the MAC is stored in OTP memory page 0xDF */
+	uint32_t ret;
+	uint64_t otp_mac;
+
+	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+	if (!(ret & OTP_MASTER_ERROR)) {
+		uchar *otp_mac_p = (uchar *)&otp_mac;
+
+		for (ret = 0; ret < 6; ++ret)
+			mac_addr[ret] = otp_mac_p[5 - ret];
+
+		if (is_valid_ether_addr(mac_addr))
+			valid_mac = true;
+	}
+#endif
+
+	if (!valid_mac) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(mac_addr);
+	}
+
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+#define KSZ_MAX_HZ    5000000
+
+#define KSZ_WRITE     0x02
+#define KSZ_READ      0x03
+
+#define KSZ_REG_CHID  0x00	/* Register 0: Chip ID0 */
+#define KSZ_REG_STPID 0x01	/* Register 1: Chip ID1 / Start Switch */
+#define KSZ_REG_GC9   0x0b	/* Register 11: Global Control 9 */
+#define KSZ_REG_P3C0  0x30	/* Register 48: Port 3 Control 0 */
+
+static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
+			     uchar data, uchar result[3])
+{
+	unsigned char dout[3] = { dir, reg, data, };
+	return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
+{
+	unsigned char din[3];
+	return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
+}
+
+static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
+{
+	int ret;
+	unsigned char din[3];
+	ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
+	return ret ? ret : din[2];
+}
+
+static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+{
+	return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
+}
+
+static int ksz8893m_reset(struct spi_slave *slave)
+{
+	int ret = 0;
+
+	/* Disable STPID mode */
+	ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
+
+	/* Disable VLAN tag insert on Port3 */
+	ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
+
+	/* Start switch */
+	ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
+
+	return ret;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	static bool switch_is_alive = false, phy_is_ksz = true;
+	int ret;
+
+	if (!switch_is_alive) {
+		struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
+		if (slave) {
+			if (!spi_claim_bus(slave)) {
+				phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
+				ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
+				switch_is_alive = (ret == 0);
+				spi_release_bus(slave);
+			}
+			spi_free_slave(slave);
+		}
+	}
+
+	if (switch_is_alive)
+		return bfin_EMAC_initialize(bis);
+	else
+		return -1;
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* connect async banks by default */
+	const unsigned short pins[] = {
+		P_AMS2, P_AMS3, 0,
+	};
+	return peripheral_request_list(pins, "async");
+}
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+	return bfin_mmc_init(bis);
+}
+#endif
diff --git a/u-boot/board/bf518f-ezbrd/config.mk b/u-boot/board/bf518f-ezbrd/config.mk
new file mode 100644
index 0000000..9a54dbf
--- /dev/null
+++ b/u-boot/board/bf518f-ezbrd/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf518-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf526-ezbrd/Makefile b/u-boot/board/bf526-ezbrd/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf526-ezbrd/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf526-ezbrd/bf526-ezbrd.c b/u-boot/board/bf526-ezbrd/bf526-ezbrd.c
new file mode 100644
index 0000000..52d82cd
--- /dev/null
+++ b/u-boot/board/bf526-ezbrd/bf526-ezbrd.c
@@ -0,0 +1,70 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF526 EZ-Board board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	bool valid_mac = false;
+
+	/* the MAC is stored in OTP memory page 0xDF */
+	uint32_t ret;
+	uint64_t otp_mac;
+
+	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+	if (!(ret & OTP_MASTER_ERROR)) {
+		uchar *otp_mac_p = (uchar *)&otp_mac;
+
+		for (ret = 0; ret < 6; ++ret)
+			mac_addr[ret] = otp_mac_p[5 - ret];
+
+		if (is_valid_ether_addr(mac_addr))
+			valid_mac = true;
+	}
+
+	if (!valid_mac) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(mac_addr);
+	}
+
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/bf526-ezbrd/config.mk b/u-boot/board/bf526-ezbrd/config.mk
new file mode 100644
index 0000000..46c09ea
--- /dev/null
+++ b/u-boot/board/bf526-ezbrd/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf526-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf527-ad7160-eval/Makefile b/u-boot/board/bf527-ad7160-eval/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf527-ad7160-eval/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/u-boot/board/bf527-ad7160-eval/bf527-ad7160-eval.c
new file mode 100644
index 0000000..ea405b6
--- /dev/null
+++ b/u-boot/board/bf527-ad7160-eval/bf527-ad7160-eval.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+	printf("Board: ADI BF527 AD7160-EVAL board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/* CLKIN Buffer Output Enable */
+	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+	return 0;
+}
diff --git a/u-boot/board/bf527-ad7160-eval/config.mk b/u-boot/board/bf527-ad7160-eval/config.mk
new file mode 100644
index 0000000..a6c272a
--- /dev/null
+++ b/u-boot/board/bf527-ad7160-eval/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.2
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf527-ezkit/Makefile b/u-boot/board/bf527-ezkit/Makefile
new file mode 100644
index 0000000..98a8121
--- /dev/null
+++ b/u-boot/board/bf527-ezkit/Makefile
@@ -0,0 +1,55 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_VIDEO)      += video.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf527-ezkit/bf527-ezkit.c b/u-boot/board/bf527-ezkit/bf527-ezkit.c
new file mode 100644
index 0000000..211cf24
--- /dev/null
+++ b/u-boot/board/bf527-ezkit/bf527-ezkit.c
@@ -0,0 +1,82 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF527 EZ-Kit board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	bool valid_mac = false;
+
+	/* the MAC is stored in OTP memory page 0xDF */
+	uint32_t ret;
+	uint64_t otp_mac;
+
+	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+	if (!(ret & OTP_MASTER_ERROR)) {
+		uchar *otp_mac_p = (uchar *)&otp_mac;
+
+		for (ret = 0; ret < 6; ++ret)
+			mac_addr[ret] = otp_mac_p[5 - ret];
+
+		if (is_valid_ether_addr(mac_addr))
+			valid_mac = true;
+	}
+
+	if (!valid_mac) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(mac_addr);
+	}
+
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_BLACKFIN
+void board_musb_init(void)
+{
+	/*
+	 * BF527 EZ-KITs require PG13 to be high for HOST mode
+	 */
+	gpio_request(GPIO_PG13, "musb-vbus");
+	gpio_direction_output(GPIO_PG13, 1);
+}
+#endif
diff --git a/u-boot/board/bf527-ezkit/config.mk b/u-boot/board/bf527-ezkit/config.mk
new file mode 100644
index 0000000..790fe99
--- /dev/null
+++ b/u-boot/board/bf527-ezkit/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf527-ezkit/video.c b/u-boot/board/bf527-ezkit/video.c
new file mode 100644
index 0000000..ca5e9b0
--- /dev/null
+++ b/u-boot/board/bf527-ezkit/video.c
@@ -0,0 +1,449 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/dma.h>
+#include <spi.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#include <asm/mach-common/bits/ppi.h>
+#include <asm/mach-common/bits/timer.h>
+
+#define LCD_X_RES		320	/* Horizontal Resolution */
+#define LCD_Y_RES		240	/* Vertical Resolution */
+#define DMA_BUS_SIZE		16
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
+
+#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
+    !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
+# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+#endif
+
+/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
+ * small Programmable Logic Device (CPLD)
+ * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
+ */
+
+#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+#include <asm/bfin_logo_rgb565_230x230.h>
+#define LCD_BPP		16	/* Bit Per Pixel */
+#define CLOCKS_PPIX	2	/* Clocks per pixel */
+#define CPLD_DELAY	3	/* RGB565 pipeline delay */
+#endif
+
+#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
+#include <asm/bfin_logo_230x230.h>
+#define LCD_BPP		24	/* Bit Per Pixel */
+#define CLOCKS_PPIX	3	/* Clocks per pixel */
+#define CPLD_DELAY	5	/* RGB888 pipeline delay */
+#endif
+
+/*
+ * HS and VS timing parameters (all in number of PPI clk ticks)
+ */
+
+#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
+#define H_PERIOD	(336 * CLOCKS_PPIX)		/* HS period */
+#define H_PULSE		(2 * CLOCKS_PPIX)		/* HS pulse width */
+#define H_START		(7 * CLOCKS_PPIX + CPLD_DELAY)	/* first valid pixel */
+
+#define U_LINE		4				/* Blanking Lines */
+
+#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
+#define V_PULSE		(2 * CLOCKS_PPIX)		/* VS pulse width (1-5 H_PERIODs) */
+#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */
+
+#define ACTIVE_VIDEO_MEM_OFFSET	((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
+
+/*
+ * LCD Modes
+ */
+#define LQ035_RL	(0 << 8)	/* Right -> Left Scan */
+#define LQ035_LR	(1 << 8)	/* Left -> Right Scan */
+#define LQ035_TB	(1 << 9)	/* Top -> Botton Scan */
+#define LQ035_BT	(0 << 9)	/* Botton -> Top Scan */
+#define LQ035_BGR	(1 << 11)	/* Use BGR format */
+#define LQ035_RGB	(0 << 11)	/* Use RGB format */
+#define LQ035_NORM	(1 << 13)	/* Reversal */
+#define LQ035_REV	(0 << 13)	/* Reversal */
+
+#define LQ035_INDEX			0x74
+#define LQ035_DATA			0x76
+
+#define LQ035_DRIVER_OUTPUT_CTL		0x1
+#define LQ035_SHUT_CTL			0x11
+
+#define LQ035_DRIVER_OUTPUT_MASK	(LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
+#define LQ035_DRIVER_OUTPUT_DEFAULT	(0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
+
+#define LQ035_SHUT			(1 << 0)	/* Shutdown */
+#define LQ035_ON			(0 << 0)	/* Shutdown */
+
+#ifndef CONFIG_LQ035Q1_LCD_MODE
+#define CONFIG_LQ035Q1_LCD_MODE		(LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
+#endif
+
+#else /* t350mcqb */
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_BPP		24	/* Bit Per Pixel */
+#define CLOCKS_PPIX	3	/* Clocks per pixel */
+
+/* HS and VS timing parameters (all in number of PPI clk ticks) */
+#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
+#define H_PERIOD	(408 * CLOCKS_PPIX)		/* HS period */
+#define H_PULSE		90				/* HS pulse width */
+#define H_START		204				/* first valid pixel */
+
+#define U_LINE		1				/* Blanking Lines */
+
+#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
+#define V_PULSE		(3 * H_PERIOD)			/* VS pulse width (1-5 H_PERIODs) */
+#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */
+
+#define ACTIVE_VIDEO_MEM_OFFSET	(U_LINE * H_ACTPIX)
+#endif
+
+#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
+#define DMA_SIZE16		2
+
+#define PPI_TX_MODE		0x2
+#define PPI_XFER_TYPE_11	0xC
+#define PPI_PORT_CFG_01		0x10
+#define PPI_PACK_EN		0x80
+#define PPI_POLS_1		0x8000
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+static struct spi_slave *slave;
+static int lq035q1_control(unsigned char reg, unsigned short value)
+{
+	int ret;
+	u8 regs[3] = {LQ035_INDEX, 0, 0};
+	u8 data[3] = {LQ035_DATA, 0, 0};
+	u8 dummy[3];
+
+	regs[2] = reg;
+	data[1] = value >> 8;
+	data[2] = value & 0xFF;
+
+	if (!slave) {
+		/* FIXME: Verify the max SCK rate */
+		slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
+				CONFIG_LQ035Q1_SPI_CS, 20000000,
+				SPI_MODE_3);
+		if (!slave)
+			return -1;
+	}
+
+	if (spi_claim_bus(slave))
+		return -1;
+
+	ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+	ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	spi_release_bus(slave);
+
+	return ret;
+}
+#endif
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+}
+
+void DisablePPI(void)
+{
+	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
+}
+
+void Init_Ports(void)
+{
+	const unsigned short pins[] = {
+		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
+	};
+	peripheral_request_list(pins, "lcd");
+}
+
+void Init_PPI(void)
+{
+
+	bfin_write_PPI_DELAY(H_START);
+	bfin_write_PPI_COUNT(H_ACTPIX - 1);
+	bfin_write_PPI_FRAME(V_LINES);
+
+	/* PPI control, to be replaced with definitions */
+	bfin_write_PPI_CONTROL(
+			PPI_TX_MODE		|	/* output mode , PORT_DIR */
+			PPI_XFER_TYPE_11	|	/* sync mode XFR_TYPE */
+			PPI_PORT_CFG_01		|	/* two frame sync PORT_CFG */
+			PPI_PACK_EN		|	/* packing enabled PACK_EN */
+			PPI_POLS_1			/* faling edge syncs POLS */
+	);
+}
+
+void Init_DMA(void *dst)
+{
+	bfin_write_DMA0_START_ADDR(dst);
+
+	/* X count */
+	bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
+	bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
+
+	/* Y count */
+	bfin_write_DMA0_Y_COUNT(V_LINES);
+	bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
+
+	/* DMA Config */
+	bfin_write_DMA0_CONFIG(
+		WDSIZE_16	|	/* 16 bit DMA */
+		DMA2D 		|	/* 2D DMA */
+		FLOW_AUTO		/* autobuffer mode */
+	);
+}
+
+void EnableDMA(void)
+{
+	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
+}
+
+void DisableDMA(void)
+{
+	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
+}
+
+/* Init TIMER0 as Frame Sync 1 generator */
+void InitTIMER0(void)
+{
+	bfin_write_TIMER_DISABLE(TIMDIS0);			/* disable Timer */
+	SSYNC();
+	bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0);	/* clear status */
+	SSYNC();
+
+	bfin_write_TIMER0_PERIOD(H_PERIOD);
+	SSYNC();
+	bfin_write_TIMER0_WIDTH(H_PULSE);
+	SSYNC();
+
+	bfin_write_TIMER0_CONFIG(
+				PWM_OUT |
+				PERIOD_CNT   |
+				TIN_SEL      |
+				CLK_SEL      |
+				EMU_RUN
+	);
+	SSYNC();
+}
+
+void EnableTIMER0(void)
+{
+	bfin_write_TIMER_ENABLE(TIMEN0);
+	SSYNC();
+}
+
+void DisableTIMER0(void)
+{
+	bfin_write_TIMER_DISABLE(TIMDIS0);
+	SSYNC();
+}
+
+
+void InitTIMER1(void)
+{
+	bfin_write_TIMER_DISABLE(TIMDIS1);			/* disable Timer */
+	SSYNC();
+	bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1);	/* clear status */
+	SSYNC();
+
+	bfin_write_TIMER1_PERIOD(V_PERIOD);
+	SSYNC();
+	bfin_write_TIMER1_WIDTH(V_PULSE);
+	SSYNC();
+
+	bfin_write_TIMER1_CONFIG(
+				PWM_OUT |
+				PERIOD_CNT   |
+				TIN_SEL      |
+				CLK_SEL      |
+				EMU_RUN
+	);
+	SSYNC();
+}
+
+void EnableTIMER1(void)
+{
+	bfin_write_TIMER_ENABLE(TIMEN1);
+	SSYNC();
+}
+
+void DisableTIMER1(void)
+{
+	bfin_write_TIMER_DISABLE(TIMDIS1);
+	SSYNC();
+}
+
+void EnableTIMER12(void)
+{
+	bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
+	SSYNC();
+}
+
+int video_init(void *dst)
+{
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+	lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
+	lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
+		LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
+#endif
+	Init_Ports();
+	Init_DMA(dst);
+	EnableDMA();
+	InitTIMER0();
+	InitTIMER1();
+	Init_PPI();
+	EnablePPI();
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+	EnableTIMER12();
+#else
+	/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
+	EnableTIMER1();
+	/* Add Some Delay ... */
+	SSYNC();
+	SSYNC();
+	SSYNC();
+	SSYNC();
+
+	/* now start frame sync 1 */
+	EnableTIMER0();
+#endif
+
+	return 0;
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+	if (dcache_status())
+		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
+
+	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+	/* Setup destination start address */
+	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
+	/* Setup destination xcount */
+	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+	/* Setup destination xmodify */
+	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+	/* Setup destination ycount */
+	bfin_write_MDMA_D0_Y_COUNT(logo->height);
+	/* Setup destination ymodify */
+	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
+
+
+	/* Setup Source start address */
+	bfin_write_MDMA_S0_START_ADDR(logo->data);
+	/* Setup Source xcount */
+	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+	/* Setup Source xmodify */
+	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+	/* Setup Source ycount */
+	bfin_write_MDMA_S0_Y_COUNT(logo->height);
+	/* Setup Source ymodify */
+	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+
+	/* Enable source DMA */
+	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+	SSYNC();
+	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);
+
+	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
+
+	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+}
+
+void video_stop(void)
+{
+	DisablePPI();
+	DisableDMA();
+	DisableTIMER0();
+	DisableTIMER1();
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+	lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
+#endif
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+	int error, devices = 1;
+	struct stdio_dev videodev;
+
+	u8 *dst;
+	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+	dst = malloc(fbmem_size);
+
+	if (dst == NULL) {
+		printf("Failed to alloc FB memory\n");
+		return -1;
+	}
+
+#ifdef EASYLOGO_ENABLE_GZIP
+	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+		puts("Failed to decompress logo\n");
+		free(dst);
+		return -1;
+	}
+	bfin_logo.data = data;
+#endif
+
+	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+			(LCD_X_RES - bfin_logo.width) / 2,
+			(LCD_Y_RES - bfin_logo.height) / 2);
+
+	video_init(dst);		/* Video initialization */
+
+	memset(&videodev, 0, sizeof(videodev));
+
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
+	videodev.putc = video_putc;	/* 'putc' function */
+	videodev.puts = video_puts;	/* 'puts' function */
+
+	error = stdio_register(&videodev);
+
+	return (error == 0) ? devices : error;
+}
diff --git a/u-boot/board/bf527-sdp/Makefile b/u-boot/board/bf527-sdp/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf527-sdp/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf527-sdp/bf527-sdp.c b/u-boot/board/bf527-sdp/bf527-sdp.c
new file mode 100644
index 0000000..504869d
--- /dev/null
+++ b/u-boot/board/bf527-sdp/bf527-sdp.c
@@ -0,0 +1,32 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+	printf("Board: ADI BF527 SDP board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+
+	/* Enable access to parallel flash */
+	gpio_request(GPIO_PG0, "parallel-flash");
+	gpio_direction_output(GPIO_PG0, 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/* CLKIN Buffer Output Enable */
+	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+
+	return 0;
+}
diff --git a/u-boot/board/bf527-sdp/config.mk b/u-boot/board/bf527-sdp/config.mk
new file mode 100644
index 0000000..7cb935a
--- /dev/null
+++ b/u-boot/board/bf527-sdp/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.2
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf533-ezkit/Makefile b/u-boot/board/bf533-ezkit/Makefile
new file mode 100644
index 0000000..dfc1724
--- /dev/null
+++ b/u-boot/board/bf533-ezkit/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf533-ezkit/bf533-ezkit.c b/u-boot/board/bf533-ezkit/bf533-ezkit.c
new file mode 100644
index 0000000..b1aa7b7
--- /dev/null
+++ b/u-boot/board/bf533-ezkit/bf533-ezkit.c
@@ -0,0 +1,60 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include "psd4256.h"
+#include "flash-defines.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF533 EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* Set direction bits for Video en/decoder reset as output      */
+	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) =
+	    PSDA_VDEC_RST | PSDA_VENC_RST;
+	/* Deactivate Video en/decoder reset lines                      */
+	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) =
+	    PSDA_VDEC_RST | PSDA_VENC_RST;
+
+	return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/u-boot/board/bf533-ezkit/config.mk b/u-boot/board/bf533-ezkit/config.mk
new file mode 100644
index 0000000..a0d1749
--- /dev/null
+++ b/u-boot/board/bf533-ezkit/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf533-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf533-ezkit/flash-defines.h b/u-boot/board/bf533-ezkit/flash-defines.h
new file mode 100644
index 0000000..eb0af94
--- /dev/null
+++ b/u-boot/board/bf533-ezkit/flash-defines.h
@@ -0,0 +1,124 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
+#define TRUE			0x1
+#define FALSE			0x0
+#define BUFFER_SIZE		0x80000
+#define NO_COMMAND		0
+#define GET_CODES		1
+#define RESET			2
+#define WRITE			3
+#define FILL			4
+#define ERASE_ALL		5
+#define ERASE_SECT		6
+#define READ			7
+#define GET_SECTNUM		8
+#define FLASH_START_L		0x0000
+#define FLASH_START_H		0x2000
+#define FLASH_TOT_SECT		40
+#define FLASH_SIZE		0x220000
+#define FLASH_MAN_ST		2
+#define CONFIG_SYS_FLASH0_BASE		0x20000000
+#define CONFIG_SYS_FLASH1_BASE		0x20200000
+#define RESET_VAL		0xF0
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int, unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, uchar *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+
+#define WRITESEQ1		0x0AAA
+#define WRITESEQ2		0x0554
+#define WRITESEQ3		0x0AAA
+#define WRITESEQ4		0x0AAA
+#define WRITESEQ5		0x0554
+#define WRITESEQ6		0x0AAA
+#define WRITEDATA1		0xaa
+#define WRITEDATA2		0x55
+#define WRITEDATA3		0x80
+#define WRITEDATA4		0xaa
+#define WRITEDATA5		0x55
+#define WRITEDATA6		0x10
+#define PriFlashABegin		0
+#define SecFlashABegin		32
+#define SecFlashBBegin		36
+#define PriFlashAOff		0x0
+#define PriFlashBOff		0x100000
+#define SecFlashAOff		0x200000
+#define SecFlashBOff		0x280000
+#define INVALIDLOCNSTART	0x20270000
+#define INVALIDLOCNEND		0x20280000
+#define BlockEraseVal		0x30
+#define UNLOCKDATA1		0xaa
+#define UNLOCKDATA2		0x55
+#define UNLOCKDATA3		0xa0
+#define GETCODEDATA1		0xaa
+#define GETCODEDATA2		0x55
+#define GETCODEDATA3		0x90
+#define SecFlashASec1Off	0x200000
+#define SecFlashASec2Off	0x204000
+#define SecFlashASec3Off	0x206000
+#define SecFlashASec4Off	0x208000
+#define SecFlashAEndOff		0x210000
+#define SecFlashBSec1Off	0x280000
+#define SecFlashBSec2Off	0x284000
+#define SecFlashBSec3Off	0x286000
+#define SecFlashBSec4Off	0x288000
+#define SecFlashBEndOff		0x290000
+
+#define SECT32			32
+#define SECT33			33
+#define SECT34			34
+#define SECT35			35
+#define SECT36			36
+#define SECT37			37
+#define SECT38			38
+#define SECT39			39
+
+#define FLASH_SUCCESS	0
+#define FLASH_FAIL	-1
+
+#endif
diff --git a/u-boot/board/bf533-ezkit/flash.c b/u-boot/board/bf533-ezkit/flash.c
new file mode 100644
index 0000000..ab808d8
--- /dev/null
+++ b/u-boot/board/bf533-ezkit/flash.c
@@ -0,0 +1,489 @@
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <asm/io.h>
+#include "flash-defines.h"
+
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+void flash_reset(void)
+{
+	reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
+{
+	int id = 0, i = 0;
+	static int FlagDev = 1;
+
+	id = get_codes();
+	if (FlagDev) {
+#ifdef DEBUG
+		printf("Device ID of the Flash is %x\n", id);
+#endif
+		FlagDev = 0;
+	}
+	info->flash_id = id;
+
+	switch (bank_flag) {
+	case 0:
+		for (i = PriFlashABegin; i < SecFlashABegin; i++)
+			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+		info->size = 0x200000;
+		info->sector_count = 32;
+		break;
+	case 1:
+		info->start[0] = baseaddr + SecFlashASec1Off;
+		info->start[1] = baseaddr + SecFlashASec2Off;
+		info->start[2] = baseaddr + SecFlashASec3Off;
+		info->start[3] = baseaddr + SecFlashASec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	case 2:
+		info->start[0] = baseaddr + SecFlashBSec1Off;
+		info->start[1] = baseaddr + SecFlashBSec2Off;
+		info->start[2] = baseaddr + SecFlashBSec3Off;
+		info->start[3] = baseaddr + SecFlashBSec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	}
+	return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1, size_b2;
+	int i;
+
+	size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+	printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
+	printf("Memory Map for the Flash\n");
+	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+	printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+	printf("Please type command flinfo for information on Sectors \n");
+#endif
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0);
+	size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1);
+	size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 >> 20);
+	}
+
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE,
+			    (flash_info[0].start[2] - 1), &flash_info[0]);
+
+	return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id) {
+	case FLASH_PSD4256GV:
+		printf("ST Microelectronics ");
+		break;
+	default:
+		printf("Unknown Vendor: (0x%08lX) ", info->flash_id);
+		break;
+	}
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int cnt = 0, i;
+	int prot, sect;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	cnt = s_last - s_first + 1;
+
+	if (cnt == FLASH_TOT_SECT) {
+		printf("Erasing flash, Please Wait \n");
+		if (erase_flash() < 0) {
+			printf("Erasing flash failed \n");
+			return FLASH_FAIL;
+		}
+	} else {
+		printf("Erasing Flash locations, Please Wait\n");
+		for (i = s_first; i <= s_last; i++) {
+			if (info->protect[i] == 0) {	/* not protected */
+				if (erase_block_flash(i, info->start[i]) < 0) {
+					printf("Error Sector erasing \n");
+					return FLASH_FAIL;
+				}
+			}
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int ret;
+	int d;
+	if (addr % 2) {
+		read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d);
+		d = (int)((d & 0x00FF) | (*src++ << 8));
+		ret = write_data(addr - 1, 2, (uchar *) & d);
+		if (ret == FLASH_FAIL)
+			return ERR_NOT_ERASED;
+		ret = write_data(addr + 1, cnt - 1, src);
+	} else
+		ret = write_data(addr, cnt, src);
+	if (ret == FLASH_FAIL)
+		return ERR_NOT_ERASED;
+	return FLASH_SUCCESS;
+}
+
+int write_data(long lStart, long lCount, uchar * pnData)
+{
+	long i = 0;
+	unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE;
+	int d;
+	int nSector = 0;
+	int flag = 0;
+
+	if (lCount % 2) {
+		flag = 1;
+		lCount = lCount - 1;
+	}
+
+	for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &d);
+		if (d != 0xffff) {
+			printf
+			    ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
+			     ulOffset);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		d = (int)(pnData[i] | pnData[i + 1] << 8);
+		write_flash(ulOffset, d);
+		if (poll_toggle_bit(ulOffset) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+		if ((i > 0) && (!(i % AFP_SectorSize2)))
+			printf(".");
+	}
+	if (flag) {
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &d);
+		if (d != 0xffff) {
+			printf
+			    ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
+			     ulOffset);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		d = (int)(pnData[i] | (d & 0xFF00));
+		write_flash(ulOffset, d);
+		if (poll_toggle_bit(ulOffset) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	long ulOffset = ulStart;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nHi, nLow;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+			    && (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset, &nLow);
+			ulOffset += (lStride * 2);
+			read_flash(ulOffset, &nHi);
+			ulOffset += (lStride * 2);
+			pnData[i] = (nHi << 16) | nLow;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+		    && (ulOffset < INVALIDLOCNEND))
+			return FLASH_FAIL;
+
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &pnData[i]);
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+	long addr;
+
+	addr = (CONFIG_SYS_FLASH_BASE + nOffset);
+	SSYNC();
+	*(unsigned volatile short *)addr = nValue;
+	SSYNC();
+	if (poll_toggle_bit(nOffset) < 0)
+		return FLASH_FAIL;
+	return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+	int nValue = 0x0;
+	long addr = (CONFIG_SYS_FLASH_BASE + nOffset);
+
+	if (nOffset != 0x2)
+		reset_flash();
+	SSYNC();
+	nValue = *(volatile unsigned short *)addr;
+	SSYNC();
+	*pnValue = nValue;
+	return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+	unsigned int u1, u2;
+	unsigned long timeout = 0xFFFFFFFF;
+	volatile unsigned long *FB =
+	    (volatile unsigned long *)(0x20000000 + lOffset);
+	while (1) {
+		if (timeout < 0)
+			break;
+		u1 = *(volatile unsigned short *)FB;
+		u2 = *(volatile unsigned short *)FB;
+		if ((u1 & 0x0040) == (u2 & 0x0040))
+			return FLASH_SUCCESS;
+		if ((u2 & 0x0020) == 0x0000)
+			continue;
+		u1 = *(volatile unsigned short *)FB;
+		if ((u2 & 0x0040) == (u1 & 0x0040))
+			return FLASH_SUCCESS;
+		else {
+			reset_flash();
+			return FLASH_FAIL;
+		}
+		timeout--;
+	}
+	printf("Time out occured \n");
+	if (timeout < 0)
+		return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+	write_flash(WRITESEQ1, RESET_VAL);
+	/* Wait for 10 micro seconds */
+	udelay(10);
+}
+
+int erase_flash(void)
+{
+	write_flash(WRITESEQ1, WRITEDATA1);
+	write_flash(WRITESEQ2, WRITEDATA2);
+	write_flash(WRITESEQ3, WRITEDATA3);
+	write_flash(WRITESEQ4, WRITEDATA4);
+	write_flash(WRITESEQ5, WRITEDATA5);
+	write_flash(WRITESEQ6, WRITEDATA6);
+
+	if (poll_toggle_bit(0x0000) < 0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+	if (poll_toggle_bit(SecFlashASec1Off) < 0)
+		return FLASH_FAIL;
+
+	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if (poll_toggle_bit(PriFlashBOff) < 0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if (poll_toggle_bit(SecFlashBOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+	long ulSectorOff = 0x0;
+
+	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+		return FALSE;
+
+	ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
+
+	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+	write_flash(ulSectorOff, BlockEraseVal);
+
+	if (poll_toggle_bit(ulSectorOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+	unsigned long ulOffsetAddr = ulOffset;
+	ulOffsetAddr &= 0xFFFF0000;
+
+	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+	int dev_id = 0;
+
+	write_flash(WRITESEQ1, GETCODEDATA1);
+	write_flash(WRITESEQ2, GETCODEDATA2);
+	write_flash(WRITESEQ3, GETCODEDATA3);
+
+	read_flash(0x0002, &dev_id);
+	dev_id &= 0x00FF;
+
+	reset_flash();
+
+	return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+
+	if (ulOffset >= SecFlashAOff) {
+		if ((ulOffset < SecFlashASec1Off)
+		    && (ulOffset < SecFlashASec2Off)) {
+			nSector = SECT32;
+		} else if ((ulOffset >= SecFlashASec2Off)
+			   && (ulOffset < SecFlashASec3Off)) {
+			nSector = SECT33;
+		} else if ((ulOffset >= SecFlashASec3Off)
+			   && (ulOffset < SecFlashASec4Off)) {
+			nSector = SECT34;
+		} else if ((ulOffset >= SecFlashASec4Off)
+			   && (ulOffset < SecFlashAEndOff)) {
+			nSector = SECT35;
+		}
+	} else if (ulOffset >= SecFlashBOff) {
+		if ((ulOffset < SecFlashBSec1Off)
+		    && (ulOffset < SecFlashBSec2Off)) {
+			nSector = SECT36;
+		}
+		if ((ulOffset < SecFlashBSec2Off)
+		    && (ulOffset < SecFlashBSec3Off)) {
+			nSector = SECT37;
+		}
+		if ((ulOffset < SecFlashBSec3Off)
+		    && (ulOffset < SecFlashBSec4Off)) {
+			nSector = SECT38;
+		}
+		if ((ulOffset < SecFlashBSec4Off)
+		    && (ulOffset < SecFlashBEndOff)) {
+			nSector = SECT39;
+		}
+	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+		nSector = ulOffset & 0xffff0000;
+		nSector = ulOffset >> 16;
+		nSector = nSector & 0x000ff;
+	}
+
+	if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+		*pnSector = nSector;
+	}
+}
diff --git a/u-boot/board/bf533-ezkit/psd4256.h b/u-boot/board/bf533-ezkit/psd4256.h
new file mode 100644
index 0000000..9b381d2
--- /dev/null
+++ b/u-boot/board/bf533-ezkit/psd4256.h
@@ -0,0 +1,67 @@
+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
+ * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTA_DIN	0x070000
+#define	PSD_PORTA_DOUT	0x070004
+#define	PSD_PORTA_DIR	0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
+ * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTB_DIN	0x070001
+#define	PSD_PORTB_DOUT	0x070005
+#define	PSD_PORTB_DIR	0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define	PSDA_PPICLK1	0x20	/* PPI Clock select bit 1               */
+#define	PSDA_PPICLK0	0x10	/* PPI Clock select bit 0               */
+#define	PSDA_VDEC_RST	0x08	/* Video decoder reset, 0 = RESET       */
+#define	PSDA_VENC_RST	0x04	/* Video encoder reset, 0 = RESET       */
+#define	PSDA_CODEC_RST	0x01	/* Codec reset, 0 = RESET               */
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define	PSDA_LED9	0x20	/* LED 9, 1 = LED ON                    */
+#define	PSDA_LED8	0x10	/* LED 8, 1 = LED ON                    */
+#define	PSDA_LED7	0x08	/* LED 7, 1 = LED ON                    */
+#define	PSDA_LED6	0x04	/* LED 6, 1 = LED ON                    */
+#define	PSDA_LED5	0x02	/* LED 5, 1 = LED ON                    */
+#define	PSDA_LED4	0x01	/* LED 4, 1 = LED ON                    */
diff --git a/u-boot/board/bf533-stamp/Makefile b/u-boot/board/bf533-stamp/Makefile
new file mode 100644
index 0000000..ce3ff42
--- /dev/null
+++ b/u-boot/board/bf533-stamp/Makefile
@@ -0,0 +1,56 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_STAMP_CF) += ide-cf.o
+COBJS-$(CONFIG_VIDEO) += video.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf533-stamp/bf533-stamp.c b/u-boot/board/bf533-stamp/bf533-stamp.c
new file mode 100644
index 0000000..935aad2
--- /dev/null
+++ b/u-boot/board/bf533-stamp/bf533-stamp.c
@@ -0,0 +1,135 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF533 Stamp board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+/* PF0 and PF1 are used to switch between the ethernet and flash:
+ *         PF0  PF1
+ *  flash:  0    0
+ *  ether:  1    0
+ */
+void swap_to(int device_id)
+{
+	gpio_request(GPIO_PF0, "eth_flash_swap");
+	gpio_request(GPIO_PF1, "eth_flash_swap");
+	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
+	gpio_direction_output(GPIO_PF1, 0);
+	SSYNC();
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_STAMP_CF
+	cf_ide_init();
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON  1
+
+static int gpio_setup;
+
+static void stamp_led_set(int LED1, int LED2, int LED3)
+{
+	if (!gpio_setup) {
+		gpio_request(GPIO_PF2, "boot_progress");
+		gpio_request(GPIO_PF3, "boot_progress");
+		gpio_request(GPIO_PF4, "boot_progress");
+		gpio_direction_output(GPIO_PF2, LED1);
+		gpio_direction_output(GPIO_PF3, LED2);
+		gpio_direction_output(GPIO_PF4, LED3);
+		gpio_setup = 1;
+	} else {
+		gpio_set_value(GPIO_PF2, LED1);
+		gpio_set_value(GPIO_PF3, LED2);
+		gpio_set_value(GPIO_PF4, LED3);
+	}
+}
+
+void show_boot_progress(int status)
+{
+	switch (status) {
+	case 1:
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+		break;
+	case 2:
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+		break;
+	case 3:
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+		break;
+	case 4:
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+		break;
+	case 5:
+	case 6:
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+		break;
+	case 7:
+	case 8:
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+		break;
+	case 9:
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
+		break;
+	default:
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+		break;
+	}
+}
+#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/u-boot/board/bf533-stamp/config.mk b/u-boot/board/bf533-stamp/config.mk
new file mode 100644
index 0000000..a0d1749
--- /dev/null
+++ b/u-boot/board/bf533-stamp/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf533-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf533-stamp/ide-cf.c b/u-boot/board/bf533-stamp/ide-cf.c
new file mode 100644
index 0000000..3e4080e
--- /dev/null
+++ b/u-boot/board/bf533-stamp/ide-cf.c
@@ -0,0 +1,98 @@
+/*
+ * CF IDE addon card code
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+void cf_outb(unsigned char val, volatile unsigned char *addr)
+{
+	/* "ETHERNET" means the expansion memory banks */
+	swap_to(ETHERNET);
+
+	*addr = val;
+	SSYNC();
+
+	swap_to(FLASH);
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+	unsigned char c;
+
+	swap_to(ETHERNET);
+
+	c = *addr;
+	SSYNC();
+
+	swap_to(FLASH);
+
+	return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+	int i;
+
+	swap_to(ETHERNET);
+
+	for (i = 0; i < words; i++) {
+		*(sect_buf + i) = *addr;
+		SSYNC();
+	}
+
+	swap_to(FLASH);
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+	int i;
+
+	swap_to(ETHERNET);
+
+	for (i = 0; i < words; i++) {
+		*addr = *(sect_buf + i);
+		SSYNC();
+	}
+
+	swap_to(FLASH);
+}
+
+/* Definitions used in  Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS	0x0000
+#define FIO_POLAR_CF_BITS	0x0000
+#define FIO_EDGE_BITS		0x1E0
+#define FIO_POLAR_BITS		0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS	0x00000060
+
+void cf_ide_init(void)
+{
+	int i, cf_stat;
+
+	/* Check whether CF card is inserted */
+	bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS);
+	bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS);
+	for (i = 0; i < 0x300; i++)
+		asm volatile("nop;");
+
+	cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS;
+
+	bfin_write_FIO_EDGE(FIO_EDGE_BITS);
+	bfin_write_FIO_POLAR(FIO_POLAR_BITS);
+
+	if (!cf_stat) {
+		for (i = 0; i < 0x3000; i++)
+			asm volatile("nop;");
+
+		ide_init();
+	}
+}
diff --git a/u-boot/board/bf533-stamp/video.c b/u-boot/board/bf533-stamp/video.c
new file mode 100644
index 0000000..75b8adc
--- /dev/null
+++ b/u-boot/board/bf533-stamp/video.c
@@ -0,0 +1,171 @@
+/*
+ * BF533-STAMP splash driver
+ *
+ * Copyright (c) 2006-2008 Analog Devices Inc.
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#define DMA_SIZE16	2
+
+#include <asm/mach-common/bits/ppi.h>
+
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE  720 * 240 */
+#define VERTICAL	2
+#define HORIZONTAL	4
+
+int is_vblank_line(const int line)
+{
+	/*
+	 *  This array contains a single bit for each line in
+	 *  an NTSC frame.
+	 */
+	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+		return true;
+
+	return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+	const int NTSC_frames = 1;
+	const int NTSC_lines = 525;
+	char *dest = base_address;
+	int frame_num, line_num;
+
+	for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+		for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+			unsigned int code;
+			int offset = 0;
+			int i;
+
+			if (is_vblank_line(line_num))
+				offset++;
+
+			if (line_num > 266 || line_num < 3)
+				offset += 2;
+
+			/* Output EAV code */
+			code = system_code_map[offset].eav;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output horizontal blanking */
+			for (i = 0; i < 67 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+
+			/* Output SAV */
+			code = system_code_map[offset].sav;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output empty horizontal data */
+			for (i = 0; i < 360 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+		}
+	}
+
+	return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+	int *OddPtr32;
+	int OddLine;
+	int *EvenPtr32;
+	int EvenLine;
+	int i;
+	int *data;
+	int m, n;
+
+	/* fill odd and even frames */
+	for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+		OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+		EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+		for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+			*OddPtr32 = Value;
+			*EvenPtr32 = Value;
+		}
+	}
+
+	for (m = 0; m < VERTICAL; m++) {
+		data = (int *)u_boot_logo.data;
+		for (OddLine = (22 + m), EvenLine = (285 + m);
+		     OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+		     OddLine += VERTICAL, EvenLine += VERTICAL) {
+			OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+			EvenPtr32 =
+			    (int *)((Frame + ((EvenLine) * 1716)) + 276);
+			for (i = 0; i < u_boot_logo.width / 2; i++) {
+				/* enlarge one pixel to m x n */
+				for (n = 0; n < HORIZONTAL; n++) {
+					*OddPtr32++ = *data;
+					*EvenPtr32++ = *data;
+				}
+				data++;
+			}
+		}
+	}
+}
+
+static void video_init(char *NTSCFrame)
+{
+	NTSC_framebuffer_init(NTSCFrame);
+	fill_frame(NTSCFrame, BLUE);
+
+	bfin_write_PPI_CONTROL(0x0082);
+	bfin_write_PPI_FRAME(0x020D);
+
+	bfin_write_DMA0_START_ADDR(NTSCFrame);
+	bfin_write_DMA0_X_COUNT(0x035A);
+	bfin_write_DMA0_X_MODIFY(0x0002);
+	bfin_write_DMA0_Y_COUNT(0x020D);
+	bfin_write_DMA0_Y_MODIFY(0x0002);
+	bfin_write_DMA0_CONFIG(0x1015);
+	bfin_write_PPI_CONTROL(0x0083);
+}
+
+void video_stop(void)
+{
+	bfin_write_PPI_CONTROL(0);
+	bfin_write_DMA0_CONFIG(0);
+}
+
+int drv_video_init(void)
+{
+	struct stdio_dev videodev;
+
+	video_init((void *)NTSC_FRAME_ADDR);
+
+	memset(&videodev, 0, sizeof(videodev));
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;
+	videodev.flags = DEV_FLAGS_SYSTEM;
+
+	return stdio_register(&videodev);
+}
diff --git a/u-boot/board/bf533-stamp/video.h b/u-boot/board/bf533-stamp/video.h
new file mode 100644
index 0000000..80837e2
--- /dev/null
+++ b/u-boot/board/bf533-stamp/video.h
@@ -0,0 +1,25 @@
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK   (0x01800180)	/* black pixel pattern   */
+#define BLUE    (0x296E29F0)	/* blue pixel pattern    */
+#define RED     (0x51F0515A)	/* red pixel pattern     */
+#define MAGENTA (0x6ADE6ACA)	/* magenta pixel pattern */
+#define GREEN   (0x91229136)	/* green pixel pattern   */
+#define CYAN    (0xAA10AAA6)	/* cyan pixel pattern    */
+#define YELLOW  (0xD292D210)	/* yellow pixel pattern  */
+#define WHITE   (0xFE80FE80)	/* white pixel pattern   */
+
+#define true	1
+#define false	0
+
+typedef struct {
+	unsigned int sav;
+	unsigned int eav;
+} system_code_type;
+
+const system_code_type system_code_map[] = {
+	{ 0xFF000080, 0xFF00009D },
+	{ 0xFF0000AB, 0xFF0000B6 },
+	{ 0xFF0000C7, 0xFF0000DA },
+	{ 0xFF0000EC, 0xFF0000F1 },
+};
diff --git a/u-boot/board/bf537-minotaur/Makefile b/u-boot/board/bf537-minotaur/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf537-minotaur/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf537-minotaur/bf537-minotaur.c b/u-boot/board/bf537-minotaur/bf537-minotaur.c
new file mode 100644
index 0000000..920429c
--- /dev/null
+++ b/u-boot/board/bf537-minotaur/bf537-minotaur.c
@@ -0,0 +1,49 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: CSP BF537 Minotaur board\n");
+	printf("       Support: http://www.camsig.co.uk/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/bf537-minotaur/config.mk b/u-boot/board/bf537-minotaur/config.mk
new file mode 100644
index 0000000..de02635
--- /dev/null
+++ b/u-boot/board/bf537-minotaur/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART       := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf537-pnav/Makefile b/u-boot/board/bf537-pnav/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf537-pnav/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf537-pnav/bf537-pnav.c b/u-boot/board/bf537-pnav/bf537-pnav.c
new file mode 100644
index 0000000..c512528
--- /dev/null
+++ b/u-boot/board/bf537-pnav/bf537-pnav.c
@@ -0,0 +1,49 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF537 PNAV board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/bf537-pnav/config.mk b/u-boot/board/bf537-pnav/config.mk
new file mode 100644
index 0000000..e29d87f
--- /dev/null
+++ b/u-boot/board/bf537-pnav/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf537-srv1/Makefile b/u-boot/board/bf537-srv1/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf537-srv1/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf537-srv1/bf537-srv1.c b/u-boot/board/bf537-srv1/bf537-srv1.c
new file mode 100644
index 0000000..04d3891
--- /dev/null
+++ b/u-boot/board/bf537-srv1/bf537-srv1.c
@@ -0,0 +1,49 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Surveyor SRV1 board\n");
+	printf("       Support: http://www.surveyor.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/bf537-srv1/config.mk b/u-boot/board/bf537-srv1/config.mk
new file mode 100644
index 0000000..de02635
--- /dev/null
+++ b/u-boot/board/bf537-srv1/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART       := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf537-stamp/Makefile b/u-boot/board/bf537-stamp/Makefile
new file mode 100644
index 0000000..2b9328b
--- /dev/null
+++ b/u-boot/board/bf537-stamp/Makefile
@@ -0,0 +1,56 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_BFIN_IDE)   += ide-cf.o
+COBJS-$(CONFIG_HAS_POST)   += post.o post-memory.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf537-stamp/bf537-stamp.c b/u-boot/board/bf537-stamp/bf537-stamp.c
new file mode 100644
index 0000000..ec888d4
--- /dev/null
+++ b/u-boot/board/bf537-stamp/bf537-stamp.c
@@ -0,0 +1,106 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <net.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF537 stamp board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+void board_reset(void)
+{
+	/* workaround for weak pull ups on ssel */
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+		bfin_reset_boot_spi_cs(GPIO_PF10);
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+#ifdef CONFIG_SYS_NO_FLASH
+# define USE_MAC_IN_FLASH 0
+#else
+# define USE_MAC_IN_FLASH 1
+#endif
+	bool valid_mac = false;
+
+	if (USE_MAC_IN_FLASH) {
+		/* we cram the MAC in the last flash sector */
+		uchar *board_mac_addr = (uchar *)0x203F0000;
+		if (is_valid_ether_addr(board_mac_addr)) {
+			memcpy(mac_addr, board_mac_addr, 6);
+			valid_mac = true;
+		}
+	}
+
+	if (!valid_mac) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(mac_addr);
+	}
+
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* we use the last sector for the MAC address / POST LDR */
+	extern flash_info_t flash_info[];
+	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
+#endif
+
+#ifdef CONFIG_BFIN_IDE
+	cf_ide_init();
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/bf537-stamp/config.mk b/u-boot/board/bf537-stamp/config.mk
new file mode 100644
index 0000000..6694f06
--- /dev/null
+++ b/u-boot/board/bf537-stamp/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf537-stamp/ide-cf.c b/u-boot/board/bf537-stamp/ide-cf.c
new file mode 100644
index 0000000..5a3720d
--- /dev/null
+++ b/u-boot/board/bf537-stamp/ide-cf.c
@@ -0,0 +1,66 @@
+/*
+ * CF IDE addon card code
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+
+void cf_outb(unsigned char val, volatile unsigned char *addr)
+{
+	*(addr) = val;
+	SSYNC();
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+	volatile unsigned char c;
+
+	c = *(addr);
+	SSYNC();
+
+	return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+	int i;
+
+	for (i = 0; i < words; i++)
+		*(sect_buf + i) = *(addr);
+	SSYNC();
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+	int i;
+
+	for (i = 0; i < words; i++)
+		*(addr) = *(sect_buf + i);
+	SSYNC();
+}
+
+void cf_ide_init(void)
+{
+#if defined(CONFIG_BFIN_TRUE_IDE)
+	/* Enable ATASEL when in True IDE mode */
+	printf("Using CF True IDE Mode\n");
+	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
+	udelay(1000);
+#elif defined(CONFIG_BFIN_CF_IDE)
+	/* Disable ATASEL when we're in Common Memory Mode */
+	printf("Using CF Common Memory Mode\n");
+	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
+	udelay(1000);
+#elif defined(CONFIG_BFIN_HDD_IDE)
+	printf("Using HDD IDE Mode\n");
+#endif
+	ide_init();
+}
diff --git a/u-boot/board/bf537-stamp/post-memory.c b/u-boot/board/bf537-stamp/post-memory.c
new file mode 100644
index 0000000..49022dc
--- /dev/null
+++ b/u-boot/board/bf537-stamp/post-memory.c
@@ -0,0 +1,318 @@
+#include <common.h>
+#include <asm/io.h>
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#define CLKIN 25000000
+#define PATTERN1 0x5A5A5A5A
+#define PATTERN2 0xAAAAAAAA
+
+#define CCLK_NUM	4
+#define SCLK_NUM	3
+
+void post_out_buff(char *buff);
+int post_key_pressed(void);
+void post_init_pll(int mult, int div);
+int post_init_sdram(int sclk);
+void post_init_uart(int sclk);
+
+const int pll[CCLK_NUM][SCLK_NUM][2] = {
+	{ {20, 4}, {20, 5}, {20, 10} },	/* CCLK = 500M */
+	{ {16, 4}, {16, 5}, {16, 8} },	/* CCLK = 400M */
+	{ {8, 2}, {8, 4}, {8, 5} },	/* CCLK = 200M */
+	{ {4, 1}, {4, 2}, {4, 4} }	/* CCLK = 100M */
+};
+const char *const log[CCLK_NUM][SCLK_NUM] = {
+	{"CCLK-500MHz SCLK-125MHz:    Writing...\0",
+	 "CCLK-500MHz SCLK-100MHz:    Writing...\0",
+	 "CCLK-500MHz SCLK- 50MHz:    Writing...\0",},
+	{"CCLK-400MHz SCLK-100MHz:    Writing...\0",
+	 "CCLK-400MHz SCLK- 80MHz:    Writing...\0",
+	 "CCLK-400MHz SCLK- 50MHz:    Writing...\0",},
+	{"CCLK-200MHz SCLK-100MHz:    Writing...\0",
+	 "CCLK-200MHz SCLK- 50MHz:    Writing...\0",
+	 "CCLK-200MHz SCLK- 40MHz:    Writing...\0",},
+	{"CCLK-100MHz SCLK-100MHz:    Writing...\0",
+	 "CCLK-100MHz SCLK- 50MHz:    Writing...\0",
+	 "CCLK-100MHz SCLK- 25MHz:    Writing...\0",},
+};
+
+int memory_post_test(int flags)
+{
+	int addr;
+	int m, n;
+	int sclk, sclk_temp;
+	int ret = 1;
+
+	sclk_temp = CLKIN / 1000000;
+	sclk_temp = sclk_temp * CONFIG_VCO_MULT;
+	for (sclk = 0; sclk_temp > 0; sclk++)
+		sclk_temp -= CONFIG_SCLK_DIV;
+	sclk = sclk * 1000000;
+	post_init_uart(sclk);
+	if (post_key_pressed() == 0)
+		return 0;
+
+	for (m = 0; m < CCLK_NUM; m++) {
+		for (n = 0; n < SCLK_NUM; n++) {
+			/* Calculate the sclk */
+			sclk_temp = CLKIN / 1000000;
+			sclk_temp = sclk_temp * pll[m][n][0];
+			for (sclk = 0; sclk_temp > 0; sclk++)
+				sclk_temp -= pll[m][n][1];
+			sclk = sclk * 1000000;
+
+			post_init_pll(pll[m][n][0], pll[m][n][1]);
+			post_init_sdram(sclk);
+			post_init_uart(sclk);
+			post_out_buff("\n\r\0");
+			post_out_buff(log[m][n]);
+			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
+				*(unsigned long *)addr = PATTERN1;
+			post_out_buff("Reading...\0");
+			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
+				if ((*(unsigned long *)addr) != PATTERN1) {
+					post_out_buff("Error\n\r\0");
+					ret = 0;
+				}
+			}
+			post_out_buff("OK\n\r\0");
+		}
+	}
+	if (ret)
+		post_out_buff("memory POST passed\n\r\0");
+	else
+		post_out_buff("memory POST failed\n\r\0");
+
+	post_out_buff("\n\r\n\r\0");
+	return 1;
+}
+
+void post_init_uart(int sclk)
+{
+	int divisor;
+
+	for (divisor = 0; sclk > 0; divisor++)
+		sclk -= 57600 * 16;
+
+	bfin_write_PORTF_FER(0x000F);
+	bfin_write_PORTH_FER(0xFFFF);
+
+	bfin_write_UART_GCTL(0x00);
+	bfin_write_UART_LCR(0x83);
+	SSYNC();
+	bfin_write_UART_DLL(divisor & 0xFF);
+	SSYNC();
+	bfin_write_UART_DLH((divisor >> 8) & 0xFF);
+	SSYNC();
+	bfin_write_UART_LCR(0x03);
+	SSYNC();
+	bfin_write_UART_GCTL(0x01);
+	SSYNC();
+}
+
+void post_out_buff(char *buff)
+{
+
+	int i = 0;
+	for (i = 0; i < 0x80000; i++)
+		;
+	i = 0;
+	while ((buff[i] != '\0') && (i != 100)) {
+		while (!(bfin_read_pUART_LSR() & 0x20)) ;
+		bfin_write_UART_THR(buff[i]);
+		SSYNC();
+		i++;
+	}
+	for (i = 0; i < 0x80000; i++)
+		;
+}
+
+/* Using sw10-PF5 as the hotkey */
+#define KEY_LOOP 0x80000
+#define KEY_DELAY 0x80
+int post_key_pressed(void)
+{
+	int i, n;
+	unsigned short value;
+
+	bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5);
+	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5);
+	bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5);
+	SSYNC();
+
+	post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
+	for (i = 0; i < KEY_LOOP; i++) {
+		value = bfin_read_PORTFIO() & PF5;
+		if (bfin_read_UART0_RBR() == 0x0D) {
+			value = 0;
+			goto key_pressed;
+		}
+		if (value != 0)
+			goto key_pressed;
+		for (n = 0; n < KEY_DELAY; n++)
+			asm("nop");
+	}
+	post_out_buff("\b2\0");
+
+	for (i = 0; i < KEY_LOOP; i++) {
+		value = bfin_read_PORTFIO() & PF5;
+		if (bfin_read_UART0_RBR() == 0x0D) {
+			value = 0;
+			goto key_pressed;
+		}
+		if (value != 0)
+			goto key_pressed;
+		for (n = 0; n < KEY_DELAY; n++)
+			asm("nop");
+	}
+	post_out_buff("\b1\0");
+
+	for (i = 0; i < KEY_LOOP; i++) {
+		value = bfin_read_PORTFIO() & PF5;
+		if (bfin_read_UART0_RBR() == 0x0D) {
+			value = 0;
+			goto key_pressed;
+		}
+		if (value != 0)
+			goto key_pressed;
+		for (n = 0; n < KEY_DELAY; n++)
+			asm("nop");
+	}
+      key_pressed:
+	post_out_buff("\b0");
+	post_out_buff("\n\r\0");
+	if (value == 0)
+		return 0;
+	post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
+	return 1;
+}
+
+void post_init_pll(int mult, int div)
+{
+
+	bfin_write_SIC_IWR(0x01);
+	bfin_write_PLL_CTL((mult << 9));
+	bfin_write_PLL_DIV(div);
+	asm("CLI R2;");
+	asm("IDLE;");
+	asm("STI R2;");
+	while (!(bfin_read_PLL_STAT() & 0x20)) ;
+}
+
+int post_init_sdram(int sclk)
+{
+	int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
+	    SDRAM_tWR;
+	int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
+	    mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
+
+	if ((sclk > 119402985)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_7;
+		SDRAM_tRAS_num = 7;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 104477612) && (sclk <= 119402985)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_6;
+		SDRAM_tRAS_num = 6;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 89552239) && (sclk <= 104477612)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_5;
+		SDRAM_tRAS_num = 5;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 74626866) && (sclk <= 89552239)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_4;
+		SDRAM_tRAS_num = 4;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 66666667) && (sclk <= 74626866)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_3;
+		SDRAM_tRAS_num = 3;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 59701493) && (sclk <= 66666667)) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_4;
+		SDRAM_tRAS_num = 4;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 44776119) && (sclk <= 59701493)) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_3;
+		SDRAM_tRAS_num = 3;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 29850746) && (sclk <= 44776119)) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_2;
+		SDRAM_tRAS_num = 2;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else if (sclk <= 29850746) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_1;
+		SDRAM_tRAS_num = 1;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_1;
+		SDRAM_tRAS_num = 1;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	}
+	/*SDRAM INFORMATION: */
+	SDRAM_Tref = 64;	/* Refresh period in milliseconds */
+	SDRAM_NRA = 4096;	/* Number of row addresses in SDRAM */
+	SDRAM_CL = CL_3;	/* 2 */
+
+	SDRAM_SIZE = EBSZ_64;
+	SDRAM_WIDTH = EBCAW_10;
+
+	mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
+
+	/* Equation from section 17 (p17-46) of BF533 HRM */
+	mem_SDRRC =
+	    (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
+	    (SDRAM_tRAS_num + SDRAM_tRP_num);
+
+	/* Enable SCLK Out */
+	mem_SDGCTL =
+	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
+	     | PSS);
+
+	SSYNC();
+
+	bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
+	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
+	bfin_write_EBIU_SDRRC(mem_SDRRC);
+
+	/* SDRAM Memory Bank Control Register */
+	bfin_write_EBIU_SDBCTL(mem_SDBCTL);
+
+	/* SDRAM Memory Global Control Register */
+	bfin_write_EBIU_SDGCTL(mem_SDGCTL);
+	SSYNC();
+	return mem_SDRRC;
+}
+
+#endif				/* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
diff --git a/u-boot/board/bf537-stamp/post.c b/u-boot/board/bf537-stamp/post.c
new file mode 100644
index 0000000..60eed5f
--- /dev/null
+++ b/u-boot/board/bf537-stamp/post.c
@@ -0,0 +1,174 @@
+/*
+ * BF537-STAMP POST code
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+	int delay = 3;
+	int i;
+	unsigned short value;
+
+	gpio_request(GPIO_PF5, "post");
+	gpio_direction_input(GPIO_PF5);
+
+	printf("########Press SW10 to enter Memory POST########: %2d ", delay);
+	while (delay--) {
+		for (i = 0; i < 100; i++) {
+			value = gpio_get_value(GPIO_PF5);
+			if (value != 0) {
+				break;
+			}
+			udelay(10000);
+		}
+		printf("\b\b\b%2d ", delay);
+	}
+	printf("\b\b\b 0");
+	printf("\n");
+	if (value == 0)
+		return 0;
+	else {
+		printf("Hotkey has been pressed, Enter POST . . . . . .\n");
+		return 1;
+	}
+
+	gpio_free(GPIO_PF5);
+}
+
+int uart_post_test(int flags)
+{
+	return 0;
+}
+
+#define BLOCK_SIZE 0x10000
+#define VERIFY_ADDR 0x2000000
+extern int erase_block_flash(int);
+extern int write_data(long lStart, long lCount, uchar * pnData);
+int flash_post_test(int flags)
+{
+	unsigned short *pbuf, *temp;
+	int offset, n, i;
+	int value = 0;
+	int result = 0;
+	printf("\n");
+	pbuf = (unsigned short *)VERIFY_ADDR;
+	temp = pbuf;
+	for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
+		offset = (n - 7) * BLOCK_SIZE;
+		printf("--------Erase   block:%2d..", n);
+		erase_block_flash(n);
+		printf("OK\r");
+		printf("--------Program block:%2d...", n);
+		write_data(CONFIG_SYS_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
+		printf("OK\r");
+		printf("--------Verify  block:%2d...", n);
+		for (i = 0; i < BLOCK_SIZE; i += 2) {
+			if (*(unsigned short *)(CONFIG_SYS_FLASH_BASE + offset + i) !=
+			    *temp++) {
+				value = 1;
+				result = 1;
+			}
+		}
+		if (value)
+			printf("failed\n");
+		else
+			printf("OK		%3d%%\r",
+			       (int)(
+				     (n + 1 -
+				      FLASH_START_POST_BLOCK) *
+				     100 / (FLASH_END_POST_BLOCK -
+					    FLASH_START_POST_BLOCK)));
+
+		temp = pbuf;
+		value = 0;
+	}
+	printf("\n");
+	if (result)
+		return -1;
+	else
+		return 0;
+}
+
+/****************************************************
+ * LED1 ---- PF6	LED2 ---- PF7		    *
+ * LED3 ---- PF8	LED4 ---- PF9		    *
+ * LED5 ---- PF10	LED6 ---- PF11		    *
+ ****************************************************/
+int led_post_test(int flags)
+{
+	unsigned int leds[] = {
+		GPIO_PF6, GPIO_PF7, GPIO_PF8,
+		GPIO_PF9, GPIO_PF10, GPIO_PF11,
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(leds); ++i) {
+		gpio_request(leds[i], "post");
+		gpio_direction_output(leds[i], 0);
+
+		printf("LED%i on", i + 1);
+		gpio_set_value(leds[i], 1);
+		udelay(1000000);
+		printf("\b\b\b\b\b\b\b");
+
+		gpio_free(leds[i]);
+	}
+
+	return 0;
+}
+
+/************************************************
+ *  SW10 ---- PF5	SW11 ---- PF4		*
+ *  SW12 ---- PF3	SW13 ---- PF2		*
+ ************************************************/
+int button_post_test(int flags)
+{
+	unsigned int buttons[] = {
+		GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5,
+	};
+	unsigned int sws[] = { 13, 12, 11, 10, };
+	int i, delay = 5;
+	unsigned short value = 0;
+	int result = 0;
+
+	for (i = 0; i < ARRAY_SIZE(buttons); ++i) {
+		gpio_request(buttons[i], "post");
+		gpio_direction_input(buttons[i]);
+
+		delay = 5;
+		printf("\n--------Press SW%i: %2d ", sws[i], delay);
+		while (delay--) {
+			for (i = 0; i < 100; i++) {
+				value = gpio_get_value(buttons[i]);
+				if (value != 0)
+					break;
+				udelay(10000);
+			}
+			printf("\b\b\b%2d ", delay);
+		}
+		if (value != 0)
+			puts("\b\bOK");
+		else {
+			result = -1;
+			puts("\b\bfailed");
+		}
+
+		gpio_free(buttons[i]);
+	}
+
+	puts("\n");
+
+	return result;
+}
diff --git a/u-boot/board/bf538f-ezkit/Makefile b/u-boot/board/bf538f-ezkit/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/bf538f-ezkit/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf538f-ezkit/bf538f-ezkit.c b/u-boot/board/bf538f-ezkit/bf538f-ezkit.c
new file mode 100644
index 0000000..49d30e7
--- /dev/null
+++ b/u-boot/board/bf538f-ezkit/bf538f-ezkit.c
@@ -0,0 +1,28 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF538F EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/u-boot/board/bf538f-ezkit/config.mk b/u-boot/board/bf538f-ezkit/config.mk
new file mode 100644
index 0000000..4ab1397
--- /dev/null
+++ b/u-boot/board/bf538f-ezkit/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf538-0.4
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf548-ezkit/Makefile b/u-boot/board/bf548-ezkit/Makefile
new file mode 100644
index 0000000..98a8121
--- /dev/null
+++ b/u-boot/board/bf548-ezkit/Makefile
@@ -0,0 +1,55 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_VIDEO)      += video.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf548-ezkit/bf548-ezkit.c b/u-boot/board/bf548-ezkit/bf548-ezkit.c
new file mode 100644
index 0000000..cb9ee86
--- /dev/null
+++ b/u-boot/board/bf548-ezkit/bf548-ezkit.c
@@ -0,0 +1,64 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/sdh.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF548 EZ-Kit board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* Set async addr lines as peripheral */
+	const unsigned short pins[] = {
+		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+		P_A21, P_A22, P_A23, P_A24, 0
+	};
+	return peripheral_request_list(pins, "async");
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+	return bfin_mmc_init(bis);
+}
+#endif
+
+#ifdef CONFIG_USB_BLACKFIN
+void board_musb_init(void)
+{
+	/*
+	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
+	 * and OTG host modes, while rev 1.1 and greater require PE7 to
+	 * be low for device mode and high for host mode.  We set it high
+	 * here because we are in host mode.
+	 */
+	gpio_request(GPIO_PE7, "musb-vbus");
+	gpio_direction_output(GPIO_PE7, 1);
+}
+#endif
diff --git a/u-boot/board/bf548-ezkit/config.mk b/u-boot/board/bf548-ezkit/config.mk
new file mode 100644
index 0000000..9aa1761
--- /dev/null
+++ b/u-boot/board/bf548-ezkit/config.mk
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf548-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
+LDR_FLAGS-BFIN_BOOT_NAND       := --dma 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf548-ezkit/video.c b/u-boot/board/bf548-ezkit/video.c
new file mode 100644
index 0000000..9bcf935
--- /dev/null
+++ b/u-boot/board/bf548-ezkit/video.c
@@ -0,0 +1,333 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#define DMA_SIZE16	2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_X_RES		480	/*Horizontal Resolution */
+#define LCD_Y_RES		272	/* Vertical Resolution */
+
+#define LCD_BPP			24	/* Bit Per Pixel */
+#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
+#define	DMA_BUS_SIZE		32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/* 	-- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency 	1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period 		TH - 525 - Clock
+ * Pulse width 		THp - 41 - Clock
+ * Horizontal period 	THd - 480 - Clock
+ * Back porch 		THb - 2 - Clock
+ * Front porch 		THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period 		TV - 286 - Line
+ * Pulse width 		TVp - 10 - Line
+ * Vertical period 	TVd - 272 - Line
+ * Back porch 		TVb - 2 - Line
+ * Front porch 		TVf - 2 - Line
+ */
+
+#define	LCD_CLK         	(8*1000*1000)	/* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT		LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT		LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE		525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME		286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL		41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL		EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY		43
+
+/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB		(EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF		(EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY		12
+
+#define EPPI_CLIP		0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL		(0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+	u32 sclk = get_sclk();
+
+	/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+	return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+	u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+	bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+	bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+	bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+	bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+	bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+	bfin_write_EPPI0_FRAME(EPPI_FRAME);
+	bfin_write_EPPI0_LINE(EPPI_LINE);
+
+	bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+	bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+	bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+	bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+	bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+		bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+					 RGB_FMT_EN);
+#else
+		bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+					 ~RGB_FMT_EN);
+#endif
+
+}
+
+#define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+
+#if defined(CONFIG_DEB_DMA_URGENT)
+	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
+#endif
+
+	bfin_write_DMA12_START_ADDR(dst);
+
+	/* X count */
+	bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
+	bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
+
+	/* Y count */
+	bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
+	bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
+
+	/* DMA Config */
+	bfin_write_DMA12_CONFIG(
+		WDSIZE_32	|	/* 32 bit DMA */
+		DMA2D 		|	/* 2D DMA */
+		FLOW_AUTO		/* autobuffer mode */
+	);
+}
+
+void Init_Ports(void)
+{
+	const unsigned short pins[] = {
+		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
+#if !defined(CONFIG_VIDEO_RGB666)
+		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+		P_PPI0_D23,
+#endif
+		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+	};
+	peripheral_request_list(pins, "lcd");
+
+	gpio_request(GPIO_PE3, "lcd-disp");
+	gpio_direction_output(GPIO_PE3, 1);
+}
+
+void EnableDMA(void)
+{
+	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
+}
+
+void DisableDMA(void)
+{
+	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+	Init_Ports();
+	Init_DMA(dst);
+	EnableDMA();
+	Init_PPI();
+	EnablePPI();
+
+	return 0;
+}
+
+void video_stop(void)
+{
+	DisablePPI();
+	DisableDMA();
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+	if (dcache_status())
+		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
+
+	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+	/* Setup destination start address */
+	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
+	/* Setup destination xcount */
+	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+	/* Setup destination xmodify */
+	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+	/* Setup destination ycount */
+	bfin_write_MDMA_D0_Y_COUNT(logo->height);
+	/* Setup destination ymodify */
+	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
+
+
+	/* Setup Source start address */
+	bfin_write_MDMA_S0_START_ADDR(logo->data);
+	/* Setup Source xcount */
+	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+	/* Setup Source xmodify */
+	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+	/* Setup Source ycount */
+	bfin_write_MDMA_S0_Y_COUNT(logo->height);
+	/* Setup Source ymodify */
+	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+
+	/* Enable source DMA */
+	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+	SSYNC();
+	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);
+
+	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
+
+	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+	int error, devices = 1;
+	struct stdio_dev videodev;
+
+	u8 *dst;
+	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+	dst = malloc(fbmem_size);
+
+	if (dst == NULL) {
+		printf("Failed to alloc FB memory\n");
+		return -1;
+	}
+
+#ifdef EASYLOGO_ENABLE_GZIP
+	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+		puts("Failed to decompress logo\n");
+		free(dst);
+		return -1;
+	}
+	bfin_logo.data = data;
+#endif
+
+	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+			(LCD_X_RES - bfin_logo.width) / 2,
+			(LCD_Y_RES - bfin_logo.height) / 2);
+
+	video_init(dst);		/* Video initialization */
+
+	memset(&videodev, 0, sizeof(videodev));
+
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
+	videodev.putc = video_putc;	/* 'putc' function */
+	videodev.puts = video_puts;	/* 'puts' function */
+
+	error = stdio_register(&videodev);
+
+	return (error == 0) ? devices : error;
+}
diff --git a/u-boot/board/bf561-acvilon/Makefile b/u-boot/board/bf561-acvilon/Makefile
new file mode 100644
index 0000000..9259d6e
--- /dev/null
+++ b/u-boot/board/bf561-acvilon/Makefile
@@ -0,0 +1,56 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf561-acvilon/bf561-acvilon.c b/u-boot/board/bf561-acvilon/bf561-acvilon.c
new file mode 100644
index 0000000..483758e
--- /dev/null
+++ b/u-boot/board/bf561-acvilon/bf561-acvilon.c
@@ -0,0 +1,51 @@
+/*
+ * File:         board/bf561-acvilon/bf561-acvilon.c
+ * Based on:     board/bf561-ezkit/bf561-ezkit.c
+ * Author:
+ *
+ * Created:      2009-06-23
+ * Description:  Acvilon System On Module board file
+ *
+ * Modified:
+ *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ *               Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ *               (C) Copyright 2000-2004
+ *               Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Bugs:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board:  CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
+	printf("       Support: http://www.niistt.ru/\n");
+	return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
diff --git a/u-boot/board/bf561-acvilon/config.mk b/u-boot/board/bf561-acvilon/config.mk
new file mode 100644
index 0000000..5c88114
--- /dev/null
+++ b/u-boot/board/bf561-acvilon/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.5
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bf561-ezkit/Makefile b/u-boot/board/bf561-ezkit/Makefile
new file mode 100644
index 0000000..0d17676
--- /dev/null
+++ b/u-boot/board/bf561-ezkit/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bf561-ezkit/bf561-ezkit.c b/u-boot/board/bf561-ezkit/bf561-ezkit.c
new file mode 100644
index 0000000..b2411b6
--- /dev/null
+++ b/u-boot/board/bf561-ezkit/bf561-ezkit.c
@@ -0,0 +1,46 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF561 EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/u-boot/board/bf561-ezkit/config.mk b/u-boot/board/bf561-ezkit/config.mk
new file mode 100644
index 0000000..19cdefc
--- /dev/null
+++ b/u-boot/board/bf561-ezkit/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/blackstamp/Makefile b/u-boot/board/blackstamp/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/blackstamp/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/blackstamp/blackstamp.c b/u-boot/board/blackstamp/blackstamp.c
new file mode 100644
index 0000000..06d004a
--- /dev/null
+++ b/u-boot/board/blackstamp/blackstamp.c
@@ -0,0 +1,41 @@
+/*
+ * U-boot - blackstamp.c BlackStamp board specific routines
+ * Most code stolen from boards/bf533-stamp/bf533-stamp.c
+ * Edited to the BlackStamp by Ben Matthews for UR LLE
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: BlackStamp\n");
+	printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n");
+	return 0;
+}
+
+#ifdef SHARED_RESOURCES
+void swap_to(int device_id)
+{
+	gpio_request(GPIO_PF0, "eth_flash_swap");
+	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
+	SSYNC();
+}
+#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/u-boot/board/blackstamp/config.mk b/u-boot/board/blackstamp/config.mk
new file mode 100644
index 0000000..0ca3c90
--- /dev/null
+++ b/u-boot/board/blackstamp/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf532-0.5
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/blackvme/Makefile b/u-boot/board/blackvme/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/blackvme/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/blackvme/blackvme.c b/u-boot/board/blackvme/blackvme.c
new file mode 100644
index 0000000..eccdaf3
--- /dev/null
+++ b/u-boot/board/blackvme/blackvme.c
@@ -0,0 +1,31 @@
+/* U-boot - blackvme.c  board specific routines
+ * (c) Wojtek Skulski 2010 info@skutek.com
+ * Board info: http://www.skutek.com
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+	printf("Board: BlackVME\n");
+	printf("Support: http://www.skutek.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AX88180
+/*
+ * The ax88180 driver had to be patched to work around a bug
+ * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
+ */
+int board_eth_init(bd_t *bis)
+{
+	return ax88180_initialize(bis);
+}
+#endif	/* CONFIG_DRIVER_AX88180 */
diff --git a/u-boot/board/blackvme/config.mk b/u-boot/board/blackvme/config.mk
new file mode 100644
index 0000000..4d6e0ba
--- /dev/null
+++ b/u-boot/board/blackvme/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.5
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/bmw/Makefile b/u-boot/board/bmw/Makefile
new file mode 100644
index 0000000..4f88efa
--- /dev/null
+++ b/u-boot/board/bmw/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
+
+SOBJS	= early_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/bmw/README b/u-boot/board/bmw/README
new file mode 100644
index 0000000..1fbef79
--- /dev/null
+++ b/u-boot/board/bmw/README
@@ -0,0 +1,331 @@
+Broadcom 95xx BMW CPCI Platform
+
+Overview
+=========
+BMW is an MPC8245 system controller featuring:
+* 3U CPCI Form Factor
+* BCM5703 Gigabit Ethernet
+* M48T59Y NVRAM
+* 16MB DOC
+* DIP Socket for Socketed DOC up to 1GB
+* 64MB SDRAM
+* LCD Display
+* Configurable Jumper options for 66,85, and 100Mhz memory bus
+
+
+BMW System Address Map
+======================
+BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual
+(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found
+onboard the processor module are listed briefly below:
+
+0x00000000 - 0x40000000 - 64MB SDRAM SIMM
+			  (Unregistered PC-100 SDRAM DIMM Module)
+
+0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
+			  TSOP 16MB (MD2211-D16-V3)
+
+0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
+			  DIP32 (Socketed 16MB - 1GB ) *
+			  NOTE: this is not populated on all systems.
+
+0x7c000000 - 0x7c000000 - Reset Register
+			  (Write 0 to reset)
+
+0x7c000001 - 0x7c000001 - System LED
+			  (Clear Bit 7 to turn on, set to shut off)
+
+0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
+			  (Clear bit 7 to reset, set to assert IRQ3)
+
+0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
+			  (Clear bit 7 to make R/W, set to make R/O)
+
+0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
+			  5x7 Dot Matrix Alphanumeric Display
+			  (Each byte sets the appropriate character)
+
+0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
+			  NVRAM Memory Region
+
+0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
+			  Realtime Clock Registers
+
+0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
+			  (AMD AM29F040, ST 29W040B)
+
+0xFFF00100 -              System Reset Vector
+
+
+IO/MMU (BAT) Configuration
+======================
+The following Block-Address-Translation (BAT) configuration
+is recommended to access all I/O devices.
+
+#define CONFIG_SYS_IBAT0L  (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+
+Interrupt Mappings
+======================
+BMW uses MPC8245 discrete mode interrupts. With the following
+hardwired mappings:
+
+BCM5701 10/100/1000 Ethernet		IRQ1
+CompactPCI Interrupt A			IRQ2
+RTC/Watchdog Interrupt			IRQ3
+Internal NS16552 UART			IRQ4
+
+
+Jumper Settings
+======================
+
+BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus.
+A jumper (X) is a 0 bit.
+
+Hence 66= 10110
+      85= 11000
+     100= 10000
+
+Jumper Settings for various Speeds
+=======================
+J1 J2 J3 J4 J5
+    X        X    66Mhz
+=======================
+J1 J2 J3 J4 J5
+       X  X  X    85Mhz
+=======================
+J1 J2 J3 J4 J5
+    X  X  X  X   100Mhz
+=======================
+
+Obviously, 100Mhz memory bus is recommended for optimum performance.
+
+
+U-Boot
+===============
+Broadcom BMW board is supported under config_BWM option.
+Supported features:
+
+- NVRAM setenv/getenv (used by Linux Kernel for configuration variables)
+- BCM570x TFTP file transfer support
+- LCD Display Support
+- DOC Support - (underway)
+
+
+U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
+
+CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
+Built: Aug  6 2002 at 17:44:37
+Local Bus at 66 MHz
+DRAM:  64 MB
+FLASH: 4095 MB
+In:    serial
+Out:   serial
+Err:   serial
+DOC:   No DiskOnChip found
+Hit any key to stop autoboot:  0
+=>printenv
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+hostname=switch-2
+bootcmd=tftp 100000 vmlinux.img;bootm
+gateway=10.16.64.1
+ethaddr=00:00:10:18:10:10
+nfsroot=172.16.40.111:/boot/root-fs
+filesize=5ec8c
+netmask=255.255.240.0
+ipaddr=172.16.40.114
+serverip=172.16.40.111
+root=/dev/nfs
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 315/8172 bytes
+=>boot
+
+
+DevTools
+========
+ELDK
+	DENX Embedded Linux Development Kit
+
+ROM Emulator
+	Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
+	Grammar Engine PL32E 32Pin PLCC Emulation cables
+	Grammar Engine 3VA8CON (3Volt adapter with Short cables)
+	Grammar Engine FPNET PromICE Ethernet Adapters
+
+ICE
+	WRS/EST VisionICE-II (PPC8240)
+
+
+=>reset
+
+
+U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
+
+CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
+Built: Aug  6 2002 at 17:44:37
+Local Bus at 66 MHz
+DRAM:  64 MB
+FLASH: 4095 MB
+In:    serial
+Out:   serial
+Err:   serial
+DOC:   No DiskOnChip found
+Hit any key to stop autoboot:  0
+
+Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000
+BCM570x PCI Memory base address @0x80100000
+eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF
+eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010
+eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found
+eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON
+ARP broadcast 1
+TFTP from server 172.16.40.111; our IP address is 172.16.40.114
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: #################################################################
+	 ####################################T #############################
+	 ######################
+done
+Bytes transferred = 777199 (bdbef hex)
+
+eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline.
+## Booting image at 00100000 ...
+   Image Name:   vmlinux.bin.gz
+   Created:      2002-08-06   6:30:13 UTC
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    777135 Bytes = 758 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb
+Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002
+CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000
+U-Boot Environment: 0xc01b08f0
+IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10>
+cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e
+NOTICE: mounting root file system via NFS
+IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111
+On node 0 totalpages: 16384
+zone(0): 16384 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111
+root_dev_setup:/dev/nfs or 00:ff
+time_init: decrementer frequency = 16.501145 MHz
+Calibrating delay loop... 175.71 BogoMIPS
+Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem)
+Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
+Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
+Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
+Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd
+devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au)
+devfs: devfs_debug: 0x0
+devfs: boot_options: 0x1
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+pty: 256 Unix98 ptys configured
+Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
+Testing ttyS0 (0xf7f51500, 0xf7f51500)...
+Testing ttyS1 (0xfc004600, 0xfc004600)...
+ttyS00 at 0xf7f51500 (irq = 24) is a ST16650
+ttyS01 at 0xfc004600 (irq = 25) is a 16550A
+Real Time Clock Driver v1.10e
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: loaded (max 8 devices)
+TFFS 5.1.1 Flash disk driver for DiskOnChip
+Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd.
+DOC device(s) found: 1
+fl_init: registered device at major: 100
+fl_geninit: registered device at major: 100
+Partition check:
+ fla: p1
+partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB
+partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB
+partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
+partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
+Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02)
+eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010
+eth0: Broadcom BCM5701 Integrated Copper transceiver found
+eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON
+bond0 registered without MII link monitoring, in bonding mode.
+rtc: unable to get misc minor
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP, IGMP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 4096 bind 4096)
+bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex
+IP-Config: Gateway not on directly connected network.
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com>
+All bugs added by David S. Miller <davem@redhat.com>
+Looking up port of RPC 100003/2 on 172.16.40.111
+Looking up port of RPC 100005/1 on 172.16.40.111
+VFS: Mounted root (nfs filesystem).
+Mounted devfs on /dev
+Freeing unused kernel memory: 100k init
+INIT: version 2.78 booting
+Mounting local filesystems...
+not mounted anything
+Setting up symlinks in /dev...done.
+Setting up extra devices in /dev...done.
+Starting devfsd...Started device management daemon for /dev
+INIT: Entering runlevel: 2
+Starting internet superserver: inetd.
+
+
+Welcome to Linux/PPC
+MPC8245/BMW
+
+
+switch-2 login: root
+Password:
+PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
+Last login: Thu Nov 25 11:51:14 1920 on console
+
+
+Welcome to Linux/PPC
+MPC8245/BMW
+
+
+login[49]: ROOT LOGIN on `console'
+
+root@switch-2:~# cat /proc/cpuinfo
+cpu             : 82xx
+revision        : 16.20 (pvr 8081 1014)
+bogomips        : 175.71
+vendor          : Broadcom
+machine         : BMW/MPC8245
+root@switch-2:~#
diff --git a/u-boot/board/bmw/bmw.c b/u-boot/board/bmw/bmw.c
new file mode 100644
index 0000000..5ba6c09
--- /dev/null
+++ b/u-boot/board/bmw/bmw.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002
+ * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <net.h>
+#include <timestamp.h>
+#include <dtt.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <linux/mtd/doc2000.h>
+
+#include "bmw.h"
+#include "m48t59y.h"
+#include <pci.h>
+
+
+int checkboard(void)
+{
+    ulong busfreq  = get_bus_freq(0);
+    char  buf[32];
+
+    puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
+    printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
+    /* printf("MPLD:  Revision %d\n", SYS_REVID_GET()); */
+    printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+    return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+    return 64*1024*1024;
+}
+
+
+void
+get_tod(void)
+{
+    int year, month, day, hour, minute, second;
+
+    m48_tod_get(&year,
+		&month,
+		&day,
+		&hour,
+		&minute,
+		&second);
+
+    printf("  Current date/time: %d/%d/%d %d:%d:%d \n",
+	   month, day, year, hour, minute, second);
+
+}
+
+/*
+ * EPIC, PCI, and I/O devices.
+ * Initialize Mousse Platform, probe for PCI devices,
+ * Query configuration parameters if not set.
+ */
+int misc_init_f (void)
+{
+#if 0
+    m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
+    printf("RTC:   M48T589 TOD/NVRAM (%d) bytes\n",
+	   TOD_NVRAM_SIZE);
+    get_tod();
+#endif
+
+    sys_led_msg("BOOT");
+    return 0;
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+struct pci_controller hose;
+
+void pci_init_board (void)
+{
+    pci_mpc824x_init(&hose);
+    /* pci_dev_init(0); */
+}
+
+/*
+ * Write characters to LCD display.
+ * Note that the bytes for the first character is the last address.
+ */
+void
+sys_led_msg(char* msg)
+{
+    LED_REG(0) = msg[3];
+    LED_REG(1) = msg[2];
+    LED_REG(2) = msg[1];
+    LED_REG(3) = msg[0];
+}
+
+#ifdef CONFIG_CMD_DOC
+/*
+ * Map onboard TSOP-16MB DOC FLASH chip.
+ */
+void doc_init (void)
+{
+    doc_probe(DOC_BASE_ADDR);
+}
+#endif
+
+#define NV_ADDR	((volatile unsigned char *) CONFIG_ENV_ADDR)
+
+/* Read from NVRAM */
+void*
+nvram_read(void *dest, const long src, size_t count)
+{
+    int i;
+    volatile unsigned char* d = (unsigned char*)dest;
+    volatile unsigned char* s = (unsigned char*)src;
+
+    for( i = 0; i < count;i++)
+	d[i] = s[i];
+
+    return dest;
+}
+
+/* Write to NVRAM */
+void
+nvram_write(long dest, const void *src, size_t count)
+{
+    int i;
+    volatile unsigned char* d = (unsigned char*)dest;
+    volatile unsigned char* s = (unsigned char*)src;
+
+    SYS_TOD_UNPROTECT();
+
+    for( i = 0; i < count;i++)
+	d[i] = s[i];
+
+    SYS_TOD_PROTECT();
+}
diff --git a/u-boot/board/bmw/bmw.h b/u-boot/board/bmw/bmw.h
new file mode 100644
index 0000000..dd97569
--- /dev/null
+++ b/u-boot/board/bmw/bmw.h
@@ -0,0 +1,86 @@
+/*
+ * BMW/MPC8245 Board definitions.
+ * For more info, see http://www.vooha.com/
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BMW_H
+#define __BMW_H
+
+/* System addresses */
+
+#define PCI_SPECIAL_BASE	0xfe000000
+#define PCI_SPECIAL_SIZE	0x01000000
+
+#define EUMBBAR_VAL		0x80500000	/* Location of EUMB region */
+#define EUMBSIZE		0x00100000	/* Size of EUMB region */
+
+/* Extended ROM space devices */
+#define DOC_BASE_ADDR           0xff000000      /* Onboard DOC TSOP 16MB */
+#define DOC2_BASE_ADDR          0x70000000      /* DIP32 socket -> 1GB */
+#define XROM_BASE_ADDR          0x7c000000      /* RCS2 (PAL / Satellite IO) */
+#define PLD_REG_BASE		XROM_BASE_ADDR
+#define LED_REG_BASE		(XROM_BASE_ADDR | 0x2000)
+#define TOD_BASE		(XROM_BASE_ADDR | 0x4000)
+#define LED_REG(x)              (*(volatile unsigned char *) \
+				  (LED_REG_BASE + (x)))
+#define XROM_DEV_SIZE		0x00006000
+
+#define ENET_DEV_BASE		0x80000000
+
+#define PLD_REG(off)		(*(volatile unsigned char *)\
+				  (PLD_REG_BASE + (off)))
+
+#define PLD_REVID_B1		0x7f	/* Fix me */
+#define PLD_REVID_B2		0x01	/* Fix me */
+
+#define SYS_HARD_RESET()	{ for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
+#define SYS_REVID_GET()		((int) PLD_REG(0) & 0x7f)
+#define SYS_LED_OFF()		(PLD_REG(1) |= 0x80)
+#define SYS_LED_ON()		(PLD_REG(1) &= ~0x80)
+#define SYS_WATCHDOG_IRQ3()	(PLD_REG(2) |= 0x80)
+#define SYS_WATCHDOG_RESET()	(PLD_REG(2) &= ~0x80)
+#define SYS_TOD_PROTECT()	(PLD_REG(3) |= 0x80)
+#define SYS_TOD_UNPROTECT()	(PLD_REG(3) &= ~0x80)
+
+#define	TOD_REG_BASE		(TOD_BASE | 0x1ff0)
+#define	TOD_NVRAM_BASE		TOD_BASE
+#define	TOD_NVRAM_SIZE		0x1ff0
+#define	TOD_NVRAM_LIMIT		(TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
+#define RTC(r)		        (TOD_BASE + r)
+
+/* Onboard BCM570x device */
+#define	PCI_ENET_IOADDR		0x80000000
+#define	PCI_ENET_MEMADDR	0x80000000
+
+
+#ifndef __ASSEMBLY__
+/* C Function prototypes */
+void sys_led_msg(char* msg);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __BMW_H */
diff --git a/u-boot/board/bmw/config.mk b/u-boot/board/bmw/config.mk
new file mode 100644
index 0000000..a1a44e5
--- /dev/null
+++ b/u-boot/board/bmw/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# BMW board
+#
+
+# NOTE: The flags below affect how the BCM570x driver is compiled
+PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
+		     -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256
diff --git a/u-boot/board/bmw/early_init.S b/u-boot/board/bmw/early_init.S
new file mode 100644
index 0000000..63c29d5
--- /dev/null
+++ b/u-boot/board/bmw/early_init.S
@@ -0,0 +1,1170 @@
+#include <ppc_asm.tmpl>
+#include <mpc824x.h>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
+
+
+/*
+ * Initialize the MMU using BAT entries and hardwired TLB
+ * This obviates the need for any code in cpu_init_f which
+ * configures the BAT registers.
+*/
+#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
+	.global	iommu_setup
+	/* Initialize IO/MMU mappings via BAT method Ch. 7,
+	 * PPC Programming Reference
+	 */
+iommu_setup:
+
+/* initialize the BAT registers (SPRs 528 - 543 */
+#define	mtibat0u(x)	mtspr	528,(x)			/* SPR 528 (IBAT0U) */
+#define mtibat0l(x)	mtspr	529,(x)			/* SPR 529 (IBAT0L) */
+#define mtibat1u(x)	mtspr	530,(x)			/* SPR 530 (IBAT1U) */
+#define mtibat1l(x)	mtspr	531,(x)			/* SPR 531 (IBAT1L) */
+#define mtibat2u(x)	mtspr	532,(x)			/* SPR 532 (IBAT2U) */
+#define mtibat2l(x)	mtspr	533,(x)			/* SPR 533 (IBAT2L) */
+#define mtibat3u(x)	mtspr	534,(x)			/* SPR 534 (IBAT3U) */
+#define mtibat3l(x)	mtspr	535,(x)			/* SPR 535 (IBAT3L) */
+#define mtdbat0u(x)	mtspr	536,(x)			/* SPR 536 (DBAT0U) */
+#define mtdbat0l(x)	mtspr	537,(x)			/* SPR 537 (DBAT0L) */
+#define mtdbat1u(x)	mtspr	538,(x)			/* SPR 538 (DBAT1U) */
+#define mtdbat1l(x)	mtspr	539,(x)			/* SPR 539 (DBAT1L) */
+#define mtdbat2u(x)	mtspr	540,(x)			/* SPR 540 (DBAT2U) */
+#define mtdbat2l(x)	mtspr	541,(x)			/* SPR 541 (DBAT2L) */
+#define mtdbat3u(x)	mtspr	542,(x)			/* SPR 542 (DBAT3U) */
+#define mtdbat3l(x)	mtspr	543,(x)			/* SPR 543 (DBAT3L) */
+
+
+/* PowerPC processors do not necessarily initialize the BAT
+   registers on power-up or reset.  So they are in an unknown
+   state.  Before programming the BATs for the first time, all
+   BAT registers MUST have their Vs and Vp bits cleared in the
+   upper BAT half in order to avoid possibly having 2 BATs
+   valid and mapping the same memory region.
+
+   The reason for this is that, even with address translation
+   disabled, multiple BAT hits for an address are treated as
+   programming errors and can cause unpredictable results.
+
+   It is up to the software to make sure it never has 2 IBAT
+   mappings or 2 DBAT mappings that are valid for the same
+   addresses.  It is not necessary to perform this code
+   sequence every time the BATs are programmed, only when
+   there is a possibility that there may be overlapping BAT
+   entries.
+
+   When programming the BATs in non-reset scenarios, even if
+   you are sure that your new mapping will not temporarily
+   create overlapping regions, it is still a wise idea to
+   invalidate a BAT entry by setting its upper BAT register to
+   all 0's before programming it.  This will avoid having a
+   BAT marked valid that is in an unknown or transient state
+*/
+
+	addis   r5,0,0x0000
+	mtibat0u(r5)
+	mtibat0l(r5)
+	mtibat1u(r5)
+	mtibat1l(r5)
+	mtibat2u(r5)
+	mtibat2l(r5)
+	mtibat3u(r5)
+	mtibat3l(r5)
+	mtdbat0u(r5)
+	mtdbat0l(r5)
+	mtdbat1u(r5)
+	mtdbat1l(r5)
+	mtdbat2u(r5)
+	mtdbat2l(r5)
+	mtdbat3u(r5)
+	mtdbat3l(r5)
+	isync
+
+/*
+ *  Set up I/D BAT0
+ */
+	lis     r4, CONFIG_SYS_DBAT0L@h
+	ori     r4, r4, CONFIG_SYS_DBAT0L@l
+	lis     r3, CONFIG_SYS_DBAT0U@h
+	ori     r3, r3, CONFIG_SYS_DBAT0U@l
+
+	mtdbat0l(r4)
+	isync
+	mtdbat0u(r3)
+	isync
+	sync
+
+	lis     r4, CONFIG_SYS_IBAT0L@h
+	ori     r4, r4, CONFIG_SYS_IBAT0L@l
+	lis     r3, CONFIG_SYS_IBAT0U@h
+	ori     r3, r3, CONFIG_SYS_IBAT0U@l
+
+	isync
+	mtibat0l(r4)
+	isync
+	mtibat0u(r3)
+	isync
+
+/*
+ *  Set up I/D BAT1
+ */
+	lis     r4, CONFIG_SYS_IBAT1L@h
+	ori     r4, r4, CONFIG_SYS_IBAT1L@l
+	lis     r3, CONFIG_SYS_IBAT1U@h
+	ori     r3, r3, CONFIG_SYS_IBAT1U@l
+
+	isync
+	mtibat1l(r4)
+	isync
+	mtibat1u(r3)
+	isync
+	mtdbat1l(r4)
+	isync
+	mtdbat1u(r3)
+	isync
+	sync
+
+/*
+ *  Set up I/D BAT2
+ */
+	lis     r4, CONFIG_SYS_IBAT2L@h
+	ori     r4, r4, CONFIG_SYS_IBAT2L@l
+	lis     r3, CONFIG_SYS_IBAT2U@h
+	ori     r3, r3, CONFIG_SYS_IBAT2U@l
+
+	isync
+	mtibat2l(r4)
+	isync
+	mtibat2u(r3)
+	isync
+	mtdbat2l(r4)
+	isync
+	mtdbat2u(r3)
+	isync
+	sync
+
+/*
+ *  Setup I/D BAT3
+ */
+	lis     r4, CONFIG_SYS_IBAT3L@h
+	ori     r4, r4, CONFIG_SYS_IBAT3L@l
+	lis     r3, CONFIG_SYS_IBAT3U@h
+	ori     r3, r3, CONFIG_SYS_IBAT3U@l
+
+	isync
+	mtibat3l(r4)
+	isync
+	mtibat3u(r3)
+	isync
+	mtdbat3l(r4)
+	isync
+	mtdbat3u(r3)
+	isync
+	sync
+
+
+/*
+ *  Invalidate all 64 TLB's
+ */
+	lis     r3, 0
+	mtctr   r3
+	lis     r5, 4
+
+tlblp:
+	tlbie   r3
+	sync
+	addi    r3, r3, 0x1000
+	cmplw   r3, r5
+	blt     tlblp
+
+	sync
+
+/*
+ *  Enable Data Translation
+ */
+	lis	r4, MEMORY_MGMT_MSR_BITS@h
+	ori	r4, r4, MEMORY_MGMT_MSR_BITS@l
+	mfmsr	r3
+	or	r3, r4, r3
+	mtmsr	r3
+	isync
+	sync
+
+	blr
+
+
+#ifdef USE_V2_INIT
+/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
+/* Macro for hiadjust and lo */
+#define HIADJ(arg)	arg@ha
+#define HI(arg)		arg@h
+#define LO(arg)		arg@l
+
+#undef LOADPTR
+#define	LOADPTR(reg,const32) \
+	  addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
+
+.globl  early_init_f
+
+early_init_f:
+/* MPC8245/BMW CPCI System Init
+ * Jimmy Blair, Broadcom Corp, 2002.
+ */
+	mflr    r11
+	/* Zero-out registers */
+
+	addis	r0,r0,0
+	mtspr	SPRG0,r0
+	mtspr	SPRG1,r0
+	mtspr	SPRG2,r0
+	mtspr	SPRG3,r0
+
+	/* Set MPU/MSR to a known state. Turn on FP */
+
+	LOADPTR (r3, MSR_FP)
+	sync
+	mtmsr	r3
+	isync
+
+	/* Init the floating point control/status register */
+
+	mtfsfi	7,0x0
+	mtfsfi	6,0x0
+	mtfsfi	5,0x0
+	mtfsfi	4,0x0
+	mtfsfi	3,0x0
+	mtfsfi	2,0x0
+	mtfsfi	1,0x0
+	mtfsfi	0,0x0
+	isync
+
+	/* Set MPU/MSR to a known state. Turn off FP */
+
+#if 1	/* Turn off floating point (remove to keep FP on) */
+	andi.	r3, r3, 0
+	sync
+	mtmsr	r3
+	isync
+#endif
+
+	/* Init the Segment registers */
+
+	andi.	r3, r3, 0
+	isync
+	mtsr	0,r3
+	isync
+	mtsr	1,r3
+	isync
+	mtsr	2,r3
+	isync
+	mtsr	3,r3
+	isync
+	mtsr	4,r3
+	isync
+	mtsr	5,r3
+	isync
+	mtsr	6,r3
+	isync
+	mtsr	7,r3
+	isync
+	mtsr	8,r3
+	isync
+	mtsr	9,r3
+	isync
+	mtsr	10,r3
+	isync
+	mtsr	11,r3
+	isync
+	mtsr	12,r3
+	isync
+	mtsr	13,r3
+	isync
+	mtsr	14,r3
+	isync
+	mtsr	15,r3
+	isync
+
+	/* Turn off data and instruction cache control bits */
+
+	mfspr	r3, HID0
+	isync
+	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */
+	sync
+	isync
+	mtspr	HID0, r4		/* HID0 = r4 */
+	isync
+
+	/* Get cpu type */
+
+	mfspr	r28, PVR
+	rlwinm	r28, r28, 16, 16, 31
+
+	/* invalidate the MPU's data/instruction caches */
+
+	lis	r3, 0x0
+	cmpli	0, 0, r28, CPU_TYPE_603
+	beq	cpuIs603
+	cmpli	0, 0, r28, CPU_TYPE_603E
+	beq	cpuIs603
+	cmpli	0, 0, r28, CPU_TYPE_603P
+	beq	cpuIs603
+	cmpli	0, 0, r28, CPU_TYPE_604R
+	bne	cpuNot604R
+
+cpuIs604R:
+	lis	r3, 0x0
+	mtspr	HID0, r3		/* disable the caches */
+	isync
+	ori	r4, r4, 0x0002		/* disable BTAC by setting bit 30 */
+
+cpuNot604R:
+	ori	r3, r3, (HID0_ICFI |HID0_DCI)
+
+cpuIs603:
+	ori	r3, r3, (HID0_ICE | HID0_DCE)
+	or	r4, r4, r3		/* set bits */
+	sync
+	isync
+	mtspr	HID0, r4		/* HID0 = r4 */
+	andc	r4, r4, r3		/* clear bits */
+	isync
+	cmpli	0, 0, r28, CPU_TYPE_604
+	beq	cpuIs604
+	cmpli	0, 0, r28, CPU_TYPE_604E
+	beq	cpuIs604
+	cmpli	0, 0, r28, CPU_TYPE_604R
+	beq	cpuIs604
+	mtspr	HID0, r4
+	isync
+
+#ifdef USER_I_CACHE_ENABLE
+	b	instCacheOn603
+#else
+	b	cacheEnableDone
+#endif
+
+cpuIs604:
+	LOADPTR (r5, 0x1000)		/* loop count, 0x1000 */
+	mtspr	CTR, r5
+loopDelay:
+	nop
+	bdnz	loopDelay
+	isync
+	mtspr	HID0, r4
+	isync
+
+	/* turn the Instruction cache ON for faster FLASH ROM boots */
+
+#ifdef USER_I_CACHE_ENABLE
+
+	ori	r4, r4, (HID0_ICE | HID0_ICFI)
+	isync				/* Synchronize for ICE enable */
+	b	writeReg4
+instCacheOn603:
+	ori	r4, r4, (HID0_ICE | HID0_ICFI)
+	rlwinm	r3, r4, 0, 21, 19	/* clear the ICFI bit */
+
+	/*
+	 * The setting of the instruction cache enable (ICE) bit must be
+	 * preceded by an isync instruction to prevent the cache from being
+	 * enabled or disabled while an instruction access is in progress.
+	 */
+	isync
+writeReg4:
+	mtspr	HID0, r4		/* Enable Instr Cache & Inval cache */
+	cmpli	0, 0, r28, CPU_TYPE_604
+	beq	cacheEnableDone
+	cmpli	0, 0, r28, CPU_TYPE_604E
+	beq	cacheEnableDone
+
+	mtspr	HID0, r3		/* using 2 consec instructions */
+					/* PPC603 recommendation */
+#endif
+cacheEnableDone:
+
+	/* Detect map A or B */
+
+	addis	r5,r0, HI(CHRP_REG_ADDR)
+	addis	r6,r0, HI(CHRP_REG_DATA)
+	LOADPTR (r7, KAHLUA_ID)		/* Kahlua PCI controller ID */
+	LOADPTR (r8, BMC_BASE)
+
+	stwbrx	r8,0,(r5)
+	lwbrx	r3,0,(r6)		/* Store read value to r3 */
+	cmp	0,0,r3,r7
+	beq	cr0, X4_KAHLUA_START
+
+	/* It's not an 8240, is it an 8245? */
+
+	LOADPTR (r7, KAHLUA2_ID)	/* Kahlua PCI controller ID */
+	cmp	0,0,r3,r7
+	beq	cr0, X4_KAHLUA_START
+
+	/* Save the PCI controller type in r7 */
+	mr	r7, r3
+
+	LOADPTR (r5, PREP_REG_ADDR)
+	LOADPTR (r6, PREP_REG_DATA)
+
+X4_KAHLUA_START:
+	/* MPC8245 changes begin here */
+	LOADPTR (r3, MPC107_PCI_CMD)	/* PCI command reg */
+	stwbrx	r3,0,r5
+	li	r4, 6			/* Command register value */
+	sthbrx	r4, 0, r6
+
+	LOADPTR (r3, MPC107_PCI_STAT)	/* PCI status reg */
+	stwbrx	r3,0,r5
+	li	r4, -1			/* Write-to-clear all bits */
+	li	r3, 2			/* PCI_STATUS is at +2 offset */
+	sthbrx	r4, r3, r6
+
+	/*-------PROC_INT1_ADR */
+
+	LOADPTR (r3, PROC_INT1_ADR)	/* Processor I/F Config 1 reg. */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xff141b98)
+	stwbrx	r4,0,r6
+
+	/*-------PROC_INT2_ADR */
+
+	LOADPTR (r3, PROC_INT2_ADR)	/* Processor I/F Config 2 reg. */
+	stwbrx	r3,0,r5
+	lis	r4, 0x2000		/* Flush PCI config writes */
+	stwbrx	r4,0,r6
+
+	LOADPTR (r9, KAHLUA2_ID)
+	cmpl	0, 0, r7, r9
+	bne     L1not8245
+
+	/* MIOCR1 -- turn on bit for DLL delay */
+
+	LOADPTR (r3, MIOCR1_ADR_X)
+	stwbrx	r3,0,r5
+	li      r4, 0x04
+	stb	r4, MIOCR1_SHIFT(r6)
+
+	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
+	/* SDRAM_CLK_DEL (0x77)*/
+
+	LOADPTR (r3, MIOCR2_ADR_X)
+	stwbrx	r3,0,r5
+	li      r4, 0x10
+	stb	r4, MIOCR2_SHIFT(r6)
+
+	/* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
+
+	LOADPTR (r3, PMCR2_ADR_X)
+	stwbrx	r3,0,r5
+	li      r4, 0x20
+	stb	r4, PMCR2_SHIFT(r6)
+
+	/* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
+
+	LOADPTR (r3, EUMBBAR)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, CONFIG_SYS_EUMB_ADDR)
+	stwbrx	r4,0,r6
+
+L1not8245:
+
+	/* Toggle the DLL reset bit in AMBOR */
+
+	LOADPTR (r3, AMBOR)
+	stwbrx	r3,0,r5
+	lbz	r4, 0(r6)
+
+	andi.   r4, r4, 0xdf
+	stb	r4, 0(r6)		/* Clear DLL_RESET */
+	sync
+
+	ori     r4, r4, 0x20		/* Set DLL_RESET */
+	stb	r4, 0(r6)
+	sync
+
+	andi.   r4, r4, 0xdf
+	stb	r4, 0(r6)		/* Clear DLL_RESET */
+
+
+	/* Enable RCS2, use supplied timings */
+	LOADPTR (r3, ERCR1)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x80408000)
+	stwbrx	r4,0,r6
+
+	/* Disable RCS3 parameters */
+	LOADPTR (r3, ERCR2)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000000)
+	stwbrx	r4,0,r6
+
+	/* RCS3 at 0x70000000, 64KBytes */
+	LOADPTR (r3, ERCR2)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000004)
+	stwbrx	r4,0,r6
+
+	/*-------MCCR1 */
+
+#ifdef INCLUDE_ECC
+#define MC_ECC				1
+#else /* INCLUDE_ECC */
+#define MC_ECC				0
+#endif /* INCLUDE_ECC */
+
+#define MC1_ROMNAL			8		/* 0-15 */
+#define MC1_ROMFAL			11		/* 0-31 */
+#define MC1_DBUS_SIZE			0		/* 0-3, read only */
+#define MC1_BURST			0		/* 0-1 */
+#define MC1_MEMGO			0		/* 0-1 */
+#define MC1_SREN			1		/* 0-1 */
+#define MC1_RAM_TYPE			0		/* 0-1 */
+#define MC1_PCKEN			MC_ECC		/* 0-1 */
+#define MC1_BANKBITS			0x5555		/* 2 bits/bank 7-0 */
+
+	LOADPTR (r3, MEM_CONT1_ADR)	/* Set MCCR1 (F0) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
+		MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
+		MC1_MEMGO << 19 | MC1_SREN << 18 | \
+		MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
+	li	r3, MC1_BANKBITS
+	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
+	bne     BankBitsAdd
+	cmpli   0, 0, r3, 0x5555
+	beq     K2BankBitsHack		/* On 8245, 5555 ==> 0 */
+BankBitsAdd:
+	ori	r4, r3, 0
+K2BankBitsHack:
+	stwbrx	r4, 0, r6
+
+	/*------- MCCR2 */
+
+#define MC2_TS_WAIT_TIMER		0		/* 0-7 */
+#define MC2_ASRISE			8		/* 0-15 */
+#define MC2_ASFALL			4		/* 0-15 */
+#define MC2_INLINE_PAR_NOT_ECC		0		/* 0-1 */
+#define MC2_WRITE_PARITY_CHK_EN		MC_ECC		/* 0-1 */
+#define MC2_INLRD_PARECC_CHK_EN		MC_ECC		/* 0-1 */
+#define MC2_ECC_EN			0		/* 0-1 */
+#define MC2_EDO				0		/* 0-1 */
+/*
+*  N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
+*  May need to be decreased for 100 MHz
+*/
+#define MC2_REFINT			0x3a5		/* 0-0x3fff */
+#define MC2_RSV_PG			0		/* 0-1 */
+#define MC2_RMW_PAR			MC_ECC		/* 0-1 */
+
+	LOADPTR (r3, MEM_CONT2_ADR)	/* Set MCCR2 (F4) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
+		MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
+		MC2_WRITE_PARITY_CHK_EN << 19 | \
+		MC2_INLRD_PARECC_CHK_EN << 18 | \
+		MC2_ECC_EN << 17 | MC2_EDO << 16 | \
+		MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
+	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
+	bne     notK2
+	/* clear Kahlua2 reserved bits */
+	LOADPTR (r3, 0xfffcffff)
+	and	r4, r4, r3
+notK2:
+	stwbrx	r4,0,r6
+
+	/*------- MCCR3 */
+
+#define MC_BSTOPRE			0x079		/* 0-0x7ff */
+
+#define MC3_BSTOPRE_U			(MC_BSTOPRE >> 4 & 0xf)
+#define MC3_REFREC			8		/* 0-15 */
+#define MC3_RDLAT			(4+MC_ECC)	/* 0-15 */
+#define MC3_CPX				0		/* 0-1 */
+#define MC3_RAS6P			0		/* 0-15 */
+#define MC3_CAS5			0		/* 0-7 */
+#define MC3_CP4				0		/* 0-7 */
+#define MC3_CAS3			0		/* 0-7 */
+#define MC3_RCD2			0		/* 0-7 */
+#define MC3_RP1				0		/* 0-7 */
+
+	LOADPTR (r3, MEM_CONT3_ADR)	/* Set MCCR3 (F8) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
+		MC3_RDLAT << 20 | MC3_CPX << 19 | \
+		MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
+		MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
+	cmpl	0, 0, r7, r9              /* Check for Kahlua2 */
+	bne     notK2b
+	/* clear Kahlua2 reserved bits */
+	LOADPTR (r3, 0xff000000)
+	and	r4, r4, r3
+notK2b:
+	stwbrx	r4,0,r6
+
+	/*------- MCCR4 */
+
+#define MC4_PRETOACT			3		/* 0-15 */
+#define MC4_ACTOPRE			5		/* 0-15 */
+#define MC4_WMODE			0		/* 0-1 */
+#define MC4_INLINE			MC_ECC		/* 0-1 */
+#define MC4_REGISTERED			(1-MC_ECC)	/* 0-1 */
+#define MC4_BSTOPRE_UU			(MC_BSTOPRE >> 8 & 3)
+#define MC4_REGDIMM			0		/* 0-1 */
+#define MC4_SDMODE_CAS			2		/* 0-7 */
+#define MC4_DBUS_RCS1			1		/* 0-1, 8-bit */
+#define MC4_SDMODE_WRAP			0		/* 0-1 */
+#define MC4_SDMODE_BURST		2		/* 0-7 */
+#define MC4_ACTORW			3		/* 0-15 */
+#define MC4_BSTOPRE_L			(MC_BSTOPRE & 0xf)
+
+	LOADPTR (r3, MEM_CONT4_ADR)	/* Set MCCR4 (FC) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
+		MC4_WMODE << 23 | MC4_INLINE << 22 | \
+		MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
+		MC4_DBUS_RCS1 << 17 | \
+		MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
+		MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
+		MC4_ACTORW << 4 | MC4_BSTOPRE_L)
+	cmpl	0, 0, r7, r9                /* Check for Kahlua 2 */
+	bne     notK2c
+	/* Turn on Kahlua2 extended ROM space */
+	LOADPTR (r3, 0x00200000)
+	or	r4, r4, r3
+notK2c:
+	stwbrx	r4,0,r6
+
+#ifdef INCLUDE_ECC
+	/*------- MEM_ERREN1 */
+
+	LOADPTR (r3, MEM_ERREN1_ADR)	/* Set MEM_ERREN1 (c0) */
+	stwbrx	r3,0,r5
+	lwbrx	r4,0,r6
+	ori	r4,r4,4			/* Set MEM_PERR_EN */
+	stwbrx	r4,0,r6
+#endif /* INCLUDE_ECC */
+
+	/*------- MSAR/MEAR */
+
+	LOADPTR (r3, MEM_START1_ADR)	/* Set MSAR1 (80) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xc0804000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, MEM_START2_ADR)	/* Set MSAR2 (84) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xc0804000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_START1_ADR)	/* Set MESAR1 (88) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_START2_ADR)	/* Set MESAR2 (8c) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x01010101)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, MEM_END1_ADR)	/* Set MEAR1 (90) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xffbf7f3f)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, MEM_END2_ADR)	/* Set MEAR2 (94) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xffbf7f3f)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_END1_ADR)	/* MEEAR1 (98) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_END2_ADR)	/* MEEAR2 (9c) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x01010101)
+	stwbrx	r4,0,r6
+
+	/*-------ODCR */
+
+	LOADPTR (r3, ODCR_ADR_X)	/* Set ODCR */
+	stwbrx	r3,0,r5
+
+	li	r4, 0x7f
+	stb	r4, ODCR_SHIFT(r6)	/* ODCR is at +3 offset */
+
+	/*-------MBEN */
+
+	LOADPTR (r3, MEM_EN_ADR)	/* Set MBEN (a0) */
+	stwbrx	r3,0,r5
+	li	r4, 0x01		/* Enable bank 0 */
+	stb	r4, 0(r6)		/* MBEN is at +0 offset */
+
+#if 0   /* Jimmy:  I think page made is broken */
+	/*-------PGMAX */
+
+	LOADPTR (r3, MPM_ADR_X)
+	stwbrx	r3,0,r5
+	li	r4, 0x32
+	stb	r4, MPM_SHIFT(r6)		/* PAGE_MODE is at +3 offset */
+#endif
+
+	/* Wait before initializing other registers */
+
+	lis	r4,0x0001
+	mtctr	r4
+
+KahluaX4wait200us:
+	bdnz	KahluaX4wait200us
+
+	/* Set MEMGO bit */
+
+	LOADPTR (r3, MEM_CONT1_ADR)	/* MCCR1 (F0) |= PGMAX */
+	stwbrx	r3,0,r5
+	lwbrx	r4,0,r6			/* old MCCR1 */
+	oris	r4,r4,0x0008		/* MEMGO=1 */
+	stwbrx	r4, 0, r6
+
+	/* Wait again */
+
+	addis	r4,r0,0x0002
+	ori	r4,r4,0xffff
+
+	mtctr	r4
+
+KahluaX4wait8ref:
+	bdnz	KahluaX4wait8ref
+
+	sync
+	eieio
+	mtlr    r11
+	blr
+
+#else /* USE_V2_INIT */
+
+
+/* U-Boot works, but memory will not run reliably for all address ranges.
+ * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
+ * initialized correctly. Could work if debugged.
+ */
+/* PCI Support routines */
+
+    .globl __pci_config_read_32
+__pci_config_read_32:
+    lis     r4, 0xfec0
+    stwbrx   r3, r0, r4
+    sync
+    lis     r4, 0xfee0
+    lwbrx   r3, 0, r4
+    blr
+    .globl __pci_config_read_16
+__pci_config_read_16:
+    lis     r4, 0xfec0
+    andi.    r5, r3, 2
+    stwbrx  r3, r0, r4
+    sync
+    oris     r4, r5, 0xfee0
+    lhbrx    r3, r0, r4
+    blr
+    .globl __pci_config_read_8
+__pci_config_read_8:
+    lis     r4, 0xfec0
+    andi.    r5, r3, 3
+    stwbrx  r3, r0, r4
+    sync
+    oris     r4, r5, 0xfee0
+    lbz      r3, 0(4)
+    blr
+    .globl __pci_config_write_32
+__pci_config_write_32:
+    lis     r5, 0xfec0
+    stwbrx   r3, r0, r5
+    sync
+    lis      r5, 0xfee0
+    stwbrx   r4, r0, r5
+    sync
+    blr
+    .globl __pci_config_write_16
+__pci_config_write_16:
+    lis     r5, 0xfec0
+    andi.    r6, r3, 2
+    stwbrx  r3, r0, 5
+    sync
+    oris     r5, r6, 0xfee0
+    sthbrx    r4, r0, r5
+    sync
+    blr
+    .globl __pci_config_write_8
+__pci_config_write_8:
+    lis      r5, 0xfec0
+    andi.    r6, r3, 3
+    stwbrx   r3, r0, r5
+    sync
+    oris      r5, r6, 0xfee0
+    stb       r4, 0(r5)
+    sync
+    blr
+    .globl  in_8
+in_8:
+    oris    r3, r3, 0xfe00
+    lbz     r3,0(r3)
+    blr
+    .globl  in_16
+in_16:
+    oris    r3, r3, 0xfe00
+    lhbrx   r3, 0, r3
+    blr
+    .globl in_16_ne
+in_16_ne:
+    oris    r3, r3, 0xfe00
+    lhzx    r3, 0, r3
+    blr
+    .globl  in_32
+in_32:
+    oris    r3, r3, 0xfe00
+    lwbrx   r3, 0, r3
+    blr
+    .globl  out_8
+out_8:
+    oris    r3, r3, 0xfe00
+    stb     r4, 0(r3)
+    eieio
+    blr
+    .globl  out_16
+out_16:
+    oris    r3, r3, 0xfe00
+    sthbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  out_16_ne
+out_16_ne:
+    oris    r3, r3, 0xfe00
+    sth     r4, 0(r3)
+    eieio
+    blr
+    .globl  out_32
+out_32:
+    oris    r3, r3, 0xfe00
+    stwbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  read_8
+read_8:
+    lbz     r3,0(r3)
+    blr
+    .globl  read_16
+read_16:
+    lhbrx   r3, 0, r3
+    blr
+    .globl  read_32
+read_32:
+    lwbrx   r3, 0, r3
+    blr
+    .globl  read_32_ne
+read_32_ne:
+    lwz     r3, 0(r3)
+    blr
+    .globl  write_8
+write_8:
+    stb     r4, 0(r3)
+    eieio
+    blr
+    .globl  write_16
+write_16:
+    sthbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  write_32
+write_32:
+    stwbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  write_32_ne
+write_32_ne:
+    stw     r4, 0(r3)
+    eieio
+    blr
+
+
+.globl  early_init_f
+
+early_init_f:
+	mflr    r11
+	lis     r10, 0x8000
+
+	/* PCI Latency Timer */
+	li      r4, 0x0d
+	ori     r3, r10, PLTR@l
+	bl      __pci_config_write_8
+
+	/* Cache Line Size */
+	li      r4, 0x08
+	ori     r3, r10, PCLSR@l
+	bl      __pci_config_write_8
+
+	/* PCI Cmd */
+	li      r4, 6
+	ori     r3, r10, PCICR@l
+	bl      __pci_config_write_16
+
+#if 1
+	/* PCI Stat */
+	ori     r3, r10, PCISR@l
+	bl      __pci_config_read_16
+	ori     r4, r4, 0xffff
+	ori     r3, r10, PCISR@l
+	bl      __pci_config_write_16
+#endif
+
+	/* PICR1 */
+	lis     r4, 0xff14
+	ori     r4, r4, 0x1b98
+	ori     r3, r10, PICR1@l
+	bl      __pci_config_write_32
+
+
+	/* PICR2 */
+	lis     r4, 0x0404
+	ori     r4, r4, 0x0004
+	ori     r3, r10, PICR2@l
+	bl      __pci_config_write_32
+
+	/* MIOCR1 */
+	li      r4, 0x04
+	ori     r3, r10, MIOCR1@l
+	bl      __pci_config_write_8
+
+	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
+	/* SDRAM_CLK_DEL (0x77)*/
+	li      r4, 0x10
+	ori     r3, r10, MIOCR2@l
+	bl      __pci_config_write_8
+
+	/* EUMBBAR */
+	lis     r4, 0xfc00
+	ori     r3, r10, EUMBBAR@l
+	bl      __pci_config_write_32
+
+	/* AMBOR */
+
+       /* Even if Address Map B is not being used (though it should),
+	* the memory DLL needs to be cleared/set/cleared before using memory.
+	*/
+
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_read_8	/* get Current bits */
+
+	andi.   r4, r4, 0xffdf
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Clear DLL_RESET */
+
+	ori    r4, r4, 0x0020
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Set DLL_RESET */
+
+	andi.   r4, r4, 0xffdf
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Clear DLL_RESET */
+
+	/* ERCR1 */
+	lis     r4, 0x8040		/* Enable RCS2, use supplied timings */
+	ori     r4, r4, 0x8000
+	ori     r3, r10, ERCR1@l
+	bl      __pci_config_write_32
+
+	/* ERCR2 */
+	lis     r4, 0x0000		/* Disable RCS3 parms */
+	ori     r4, r4, 0x0000
+	ori     r3, r10, ERCR2@l
+	bl      __pci_config_write_32
+
+	/* ERCR3 */
+	lis     r4, 0x0000		/* RCS3 at 0x70000000, 64K bytes */
+	ori     r4, r4, 0x0004
+	ori     r3, r10, ERCR2@l
+	bl      __pci_config_write_32
+
+	/* Preserve memgo bit */
+	/* MCCR1 */
+
+/*	lis     r4, 0x75a8		/  Safe Local ROM = 11+3 clocks */
+	lis     r4, 0x75a0              /* Safe Local ROM = 11+3 clocks */
+/*      lis     r4, 0x73a0              /  Fast Local ROM = 7+3 clocks */
+/*      oris    r4, r4, 0x0010          /  Burst ROM/Flash enable */
+/*      oris    r4, r4, 0x0004          /  Self-refresh enable */
+
+/*      ori     r4,r4,0xFFFF            /  16Mbit  2bank SDRAM */
+/*      ori     r4,r4,0xAAAA            /  256Mbit 4bank SDRAM (8245 only) */
+/*      ori     r4,r4,0x5555            /  64Mbit  2bank SDRAM */
+	ori     r4,r4,0x0000            /* 64Mbit  4bank SDRAM */
+
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_write_32
+
+	/* MCCR2 */
+
+	lis     r4,0x0000
+/*      oris    r4,r4,0x4000            /  TS_WAIT_TIMER = 3 clocks */
+	oris    r4,r4,0x1000            /* ASRISE = 8 clocks */
+	oris    r4,r4,0x0080            /* ASFALL = 8 clocks */
+/*      oris    r4,r4,0x0010            /  SDRAM Parity (else ECC) */
+/*      oris    r4,r4,0x0008            /  Write parity check */
+/*      oris    r4,r4,0x0004            /  SDRAM inline reads */
+
+
+/* Select a refresh rate; it needs to match the bus speed; if too */
+/* slow, data may be lost; if too fast, performance is lost.  We */
+/* use the fastest value so we run at all speeds. */
+/* Refresh = (15600ns/busclk) - (213 (see UM)). */
+
+/*      ori     r4,r4,0x1d2c            /  133 MHz mem bus        = 1867 */
+/*      ori     r4,r4,0x150c            /  100 MHz mem bus        = 1347 */
+/*      ori     r4,r4,0x10fc            /   83 MHz mem bus        = 1087 */
+/*      ori     r4,r4,0x0cc4            /   66 MHz mem bus        =  817 */
+	ori     r4,r4,0x04cc            /*  33 MHz mem bus (SAFE) =  307 */
+/*      ori     r4,r4,0x0002            /  Reserve a page */
+/*      ori     r4,r4,0x0001            /  RWM parity */
+
+	ori     r3, r10, MCCR2@l
+	bl      __pci_config_write_32
+
+
+	/* MCCR3 */
+	lis     r4,0x0000               /* BSTOPRE_M = 7 (see A/N) */
+	oris    r4,r4,0x0500            /* REFREC    = 8 clocks */
+	ori     r3, r10, MCCR3@l
+	bl      __pci_config_write_32
+
+	/* MCCR4 */                     /* Turn on registered buffer mode */
+	lis     r4, 0x2000              /* PRETOACT = 3 clocks */
+	oris    r4,r4,0x0400            /* ACTOPRE  = 5 clocks */
+/*      oris    r4,r4,0x0080            /  Enable 8-beat burst (32-bit bus) */
+/*      oris    r4,r4,0x0040            /  Enable Inline ECC/Parity */
+	oris    r4,r4,0x0020            /* EXTROM enabled */
+	oris    r4,r4,0x0010            /* Registered buffers */
+/*      oris    r4,r4,0x0000            /  BSTOPRE_U = 0 (see A/N) */
+	oris    r4,r4,0x0002            /* DBUS_SIZ[2] (8 bit on RCS1) */
+
+/*      ori     r4,r4,0x8000            /  Registered DIMMs */
+	ori     r4,r4,0x2000            /*CAS Latency (CL=3) (see RDLAT) */
+/*      ori     r4,r4,0x2000            /  CAS Latency (CL=2) (see RDLAT) */
+/*      ori     r4,r4,0x0300            /  Sequential wrap/8-beat burst */
+	ori     r4,r4,0x0200            /* Sequential wrap/4-beat burst */
+	ori     r4,r4,0x0030            /* ACTORW  = 3 clocks */
+	ori     r4,r4,0x0009            /* BSTOPRE_L = 9 (see A/N) */
+
+	ori     r3, r10, MCCR4@l
+	bl      __pci_config_write_32
+
+	/* MSAR1 */
+	lis     r4, 0xc0804000@h
+	ori     r4, r4, 0xc0804000@l
+	ori     r3, r10, MSAR1@l
+	bl      __pci_config_write_32
+
+	/* MSAR2 */
+	lis     r4, 0xc0804000@h
+	ori     r4, r4, 0xc0804000@l
+	ori     r3, r10, MSAR2@l
+	bl      __pci_config_write_32
+
+	/* MESAR1 */
+	lis     r4, 0x00000000@h
+	ori     r4, r4, 0x00000000@l
+	ori     r3, r10, EMSAR1@l
+	bl      __pci_config_write_32
+
+	/* MESAR2 */
+	lis     r4, 0x01010101@h
+	ori     r4, r4, 0x01010101@l
+	ori     r3, r10, EMSAR2@l
+	bl      __pci_config_write_32
+
+	/* MEAR1 */
+	lis     r4, 0xffbf7f3f@h
+	ori     r4, r4, 0xffbf7f3f@l
+	ori     r3, r10, MEAR1@l
+	bl      __pci_config_write_32
+
+	/* MEAR2 */
+	lis     r4, 0xffbf7f3f@h
+	ori     r4, r4, 0xffbf7f3f@l
+	ori     r3, r10, MEAR2@l
+	bl      __pci_config_write_32
+
+	/* MEEAR1 */
+	lis     r4, 0x00000000@h
+	ori     r4, r4, 0x00000000@l
+	ori     r3, r10, EMEAR1@l
+	bl      __pci_config_write_32
+
+	/* MEEAR2 */
+	lis     r4, 0x01010101@h
+	ori     r4, r4, 0x01010101@l
+	ori     r3, r10, EMEAR2@l
+	bl      __pci_config_write_32
+
+	/* ODCR */
+	li      r4, 0x7f
+	ori     r3, r10, ODCR@l
+	bl      __pci_config_write_8
+
+	/* MBER */
+	li      r4, 0x01
+	ori     r3, r10, MBER@l
+	bl      __pci_config_write_8
+
+	/* Page CTR aka PGMAX */
+	li      r4, 0x32
+	ori     r3, r10, 0x70
+	bl      __pci_config_write_8
+
+#if 0
+	/* CLK Drive */
+	ori     r4, r10, 0xfc01 /* Top bit will be ignored */
+	ori     r3, r10, 0x74
+	bl      __pci_config_write_16
+#endif
+
+	/* delay */
+	lis     r7, 1
+	mtctr   r7
+label1:	bdnz    label1
+
+	/* Set memgo bit */
+	/* MCCR1 */
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_read_32
+	lis	r7, 0x0008
+	or	r4, r3, r7
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_write_32
+
+	/* delay again */
+	lis     r7, 1
+	mtctr   r7
+label2:	bdnz    label2
+#if 0
+/* DEBUG: Infinite loop, write then read */
+loop:
+	lis     r7, 0xffff
+	mtctr   r7
+	li	r3, 0x5004
+	lis	r4, 0xa0a0
+	ori	r4, r4, 0x5050
+	bl write_32_ne
+	li	r3, 0x5004
+	bl read_32_ne
+	bdnz    loop
+#endif
+	mtlr    r11
+	blr
+#endif
diff --git a/u-boot/board/bmw/flash.c b/u-boot/board/bmw/flash.c
new file mode 100644
index 0000000..57ffe08
--- /dev/null
+++ b/u-boot/board/bmw/flash.c
@@ -0,0 +1,779 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+
+#if 0
+static void flash_get_offsets (ulong base, flash_info_t * info);
+#endif /* 0 */
+
+/*flash command address offsets*/
+
+#if 0
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+#else
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+#endif
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+#if 0
+static int byte_parity_odd (unsigned char x) __attribute__ ((const));
+#endif /* 0 */
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+	__attribute__ ((const));
+
+typedef struct {
+	FLASH_WORD_SIZE extval;
+	unsigned short intval;
+} map_entry;
+
+#if 0
+static int byte_parity_odd (unsigned char x)
+{
+	x ^= x >> 4;
+	x ^= x >> 2;
+	x ^= x >> 1;
+	return (x & 0x1) != 0;
+}
+#endif /* 0 */
+
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B, FLASH_AM040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for (p = &chip_map[0];
+	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+		if (p->extval == chip) {
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+
+	/* find vendor id */
+	for (p = &mfct_map[0];
+	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+		if (p->extval == mfct) {
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+
+	return result;
+}
+
+
+unsigned long flash_init (void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE *const flash =
+			(FLASH_WORD_SIZE *) base_address;
+#if 0
+		volatile FLASH_WORD_SIZE *addr2;
+#endif
+#if 0
+		/* write autoselect sequence */
+		flash[0x5555] = 0xaa;
+		flash[0x2aaa] = 0x55;
+		flash[0x5555] = 0x90;
+#else
+		flash[0xAAA << (3 * i)] = 0xaa;
+		flash[0x555 << (3 * i)] = 0x55;
+		flash[0xAAA << (3 * i)] = 0x90;
+#endif
+		__asm__ __volatile__ ("sync");
+
+#if 0
+		pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]);
+#else
+		pflinfo->flash_id =
+			flash_id (flash[0x0], flash[0x2 + 14 * i]);
+#endif
+
+		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			pflinfo->size = 0x00080000;
+			pflinfo->sector_count = 8;
+			for (j = 0; j < 8; j++) {
+				pflinfo->start[j] =
+					base_address + 0x00010000 * j;
+				pflinfo->protect[j] = flash[(j << 16) | 0x2];
+			}
+			break;
+		case FLASH_STM800AB:
+			pflinfo->size = 0x00100000;
+			pflinfo->sector_count = 19;
+			pflinfo->start[0] = base_address;
+			pflinfo->start[1] = base_address + 0x4000;
+			pflinfo->start[2] = base_address + 0x6000;
+			pflinfo->start[3] = base_address + 0x8000;
+			for (j = 1; j < 16; j++) {
+				pflinfo->start[j + 3] =
+					base_address + 0x00010000 * j;
+			}
+#if 0
+			/* check for protected sectors */
+			for (j = 0; j < pflinfo->sector_count; j++) {
+				/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+				/* D0 = 1 if protected */
+				addr2 = (volatile FLASH_WORD_SIZE
+					 *) (pflinfo->start[j]);
+				if (pflinfo->flash_id & FLASH_MAN_SST)
+					pflinfo->protect[j] = 0;
+				else
+					pflinfo->protect[j] = addr2[2] & 1;
+			}
+#endif
+			break;
+		}
+		/* Protect monitor and environment sectors
+		 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR,
+			       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+			       &flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__ ("sync");
+	}
+
+	return flash_info[0].size + flash_info[1].size;
+}
+
+#if 0
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+		"  Size: %lu KB in %d Sectors\n",
+		mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+		     (flash != (unsigned long *) info->start[i] + size)
+		     && erased; flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+			(i % 5) ? "" : "\n   ",
+			info->start[i],
+			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+#if 0
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	printf ("flash_get_size: \n");
+	/* Write auto select command: read Manufacturer ID */
+	eieio ();
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90;
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+	printf ("recognised manufacturer");
+
+	value = addr2[ADDR3];	/* device ID        */
+	debug ("\ndev_code=%x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB        */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB        */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB      */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;		/* => 1 MB      */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB      */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id,
+		info->sector_count, info->size);
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if (info->flash_id & FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+#endif
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
+								       start
+								       [sect]
+								       -
+								       info->
+								       start
+								       [0]) <<
+								      sh8b));
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+						       info->
+						       start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+				     info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/bmw/m48t59y.c b/u-boot/board/bmw/m48t59y.c
new file mode 100644
index 0000000..4e83b90
--- /dev/null
+++ b/u-boot/board/bmw/m48t59y.c
@@ -0,0 +1,324 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
+ * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
+ * registers which are used to set/get the internal date/time functions.
+ *
+ * This module implements Y2K compliance by taking full year numbers
+ * and translating back and forth from the TOD 2-digit year.
+ *
+ * NOTE: for proper interaction with an operating system, the TOD should
+ * be used to store Universal Coordinated Time (GMT) and timezone
+ * conversions should be used.
+ *
+ * Here is a diagram of the memory layout:
+ *
+ * +---------------------------------------------+ 0xffe0a000
+ * | Non-volatile memory                         | .
+ * |                                             | .
+ * | (8176 bytes of Non-volatile memory)         | .
+ * |                                             | .
+ * +---------------------------------------------+ 0xffe0bff0
+ * | Flags                                       |
+ * +---------------------------------------------+ 0xffe0bff1
+ * | Unused                                      |
+ * +---------------------------------------------+ 0xffe0bff2
+ * | Alarm Seconds                               |
+ * +---------------------------------------------+ 0xffe0bff3
+ * | Alarm Minutes                               |
+ * +---------------------------------------------+ 0xffe0bff4
+ * | Alarm Date                                  |
+ * +---------------------------------------------+ 0xffe0bff5
+ * | Interrupts                                  |
+ * +---------------------------------------------+ 0xffe0bff6
+ * | WatchDog                                    |
+ * +---------------------------------------------+ 0xffe0bff7
+ * | Calibration                                 |
+ * +---------------------------------------------+ 0xffe0bff8
+ * | Seconds                                     |
+ * +---------------------------------------------+ 0xffe0bff9
+ * | Minutes                                     |
+ * +---------------------------------------------+ 0xffe0bffa
+ * | Hours                                       |
+ * +---------------------------------------------+ 0xffe0bffb
+ * | Day                                         |
+ * +---------------------------------------------+ 0xffe0bffc
+ * | Date                                        |
+ * +---------------------------------------------+ 0xffe0bffd
+ * | Month                                       |
+ * +---------------------------------------------+ 0xffe0bffe
+ * | Year (2 digits only)                        |
+ * +---------------------------------------------+ 0xffe0bfff
+ */
+#include <common.h>
+#include <rtc.h>
+#include "bmw.h"
+
+/*
+ * Imported from mousse.h:
+ *
+ *   TOD_REG_BASE		Base of m48t59y TOD registers
+ *   SYS_TOD_UNPROTECT()	Disable NVRAM write protect
+ *   SYS_TOD_PROTECT()		Re-enable NVRAM write protect
+ */
+
+#define YEAR		0xf
+#define MONTH		0xe
+#define DAY		0xd
+#define DAY_OF_WEEK	0xc
+#define HOUR		0xb
+#define MINUTE		0xa
+#define SECOND		0x9
+#define CONTROL		0x8
+#define WATCH		0x7
+#define INTCTL		0x6
+#define WD_DATE		0x5
+#define WD_HOUR		0x4
+#define WD_MIN		0x3
+#define WD_SEC		0x2
+#define _UNUSED		0x1
+#define FLAGS		0x0
+
+#define M48_ADDR	((volatile unsigned char *) TOD_REG_BASE)
+
+int m48_tod_init(void)
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] = 0;
+    M48_ADDR[WATCH] = 0;
+    M48_ADDR[INTCTL] = 0;
+
+    /*
+     * If the oscillator is currently stopped (as on a new part shipped
+     * from the factory), start it running.
+     *
+     * Here is an example of the TOD bytes on a brand new M48T59Y part:
+     *		00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
+     */
+
+    if (M48_ADDR[SECOND] & 0x80)
+	M48_ADDR[SECOND] = 0;
+
+    /* Is battery low */
+    if ( M48_ADDR[FLAGS] & 0x10) {
+	 printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
+    }
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * m48_tod_set
+ */
+
+static int to_bcd(int value)
+{
+    return value / 10 * 16 + value % 10;
+}
+
+static int from_bcd(int value)
+{
+    return value / 16 * 10 + value % 16;
+}
+
+static int day_of_week(int y, int m, int d)	/* 0-6 ==> Sun-Sat */
+{
+    static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
+    y -= m < 3;
+    return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_set(int year,		/* 1980-2079 */
+		int month,		/* 01-12 */
+		int day,		/* 01-31 */
+		int hour,		/* 00-23 */
+		int minute,		/* 00-59 */
+		int second)		/* 00-59 */
+
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x80;	/* Set WRITE bit */
+
+    M48_ADDR[YEAR] = to_bcd(year % 100);
+    M48_ADDR[MONTH] = to_bcd(month);
+    M48_ADDR[DAY] = to_bcd(day);
+    M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
+    M48_ADDR[HOUR] = to_bcd(hour);
+    M48_ADDR[MINUTE] = to_bcd(minute);
+    M48_ADDR[SECOND] = to_bcd(second);
+
+    M48_ADDR[CONTROL] &= ~0x80;	/* Clear WRITE bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_get(int *year,		/* 1980-2079 */
+		int *month,		/* 01-12 */
+		int *day,		/* 01-31 */
+		int *hour,		/* 00-23 */
+		int *minute,		/* 00-59 */
+		int *second)		/* 00-59 */
+{
+    int y;
+
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x40;	/* Set READ bit */
+
+    y = from_bcd(M48_ADDR[YEAR]);
+    *year = y < 80 ? 2000 + y : 1900 + y;
+    *month = from_bcd(M48_ADDR[MONTH]);
+    *day = from_bcd(M48_ADDR[DAY]);
+    /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
+    *hour = from_bcd(M48_ADDR[HOUR]);
+    *minute = from_bcd(M48_ADDR[MINUTE]);
+    *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
+
+    M48_ADDR[CONTROL] &= ~0x40;	/* Clear READ bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+int m48_tod_get_second(void)
+{
+    return from_bcd(M48_ADDR[SECOND] & 0x7f);
+}
+
+/*
+ * Watchdog function
+ *
+ *  If usec is 0, the watchdog timer is disarmed.
+ *
+ *  If usec is non-zero, the watchdog timer is armed (or re-armed) for
+ *    approximately usec microseconds (if the exact requested usec is
+ *    not supported by the chip, the next higher available value is used).
+ *
+ *  Minimum watchdog timeout = 62500 usec
+ *  Maximum watchdog timeout = 124 sec (124000000 usec)
+ */
+
+void m48_watchdog_arm(int usec)
+{
+    int		mpy, res;
+
+    SYS_TOD_UNPROTECT();
+
+    if (usec == 0) {
+	res = 0;
+	mpy = 0;
+    } else if (usec < 2000000) {	/* Resolution: 1/16s if below 2s */
+	res = 0;
+	mpy = (usec + 62499) / 62500;
+    } else if (usec < 8000000) {	/* Resolution: 1/4s if below 8s */
+	res = 1;
+	mpy = (usec + 249999) / 250000;
+    } else if (usec < 32000000) {	/* Resolution: 1s if below 32s */
+	res = 2;
+	mpy = (usec + 999999) / 1000000;
+    } else {				/* Resolution: 4s up to 124s */
+	res = 3;
+	mpy = (usec + 3999999) / 4000000;
+	if (mpy > 31)
+	    mpy = 31;
+    }
+
+    M48_ADDR[WATCH] = (0x80 |		/* Steer to RST signal (IRQ = N/C) */
+		       mpy << 2 |
+		       res);
+
+    SYS_TOD_PROTECT();
+}
+
+/*
+ * U-Boot RTC support.
+ */
+int
+rtc_get( struct rtc_time *tmp )
+{
+	m48_tod_get(&tmp->tm_year,
+		    &tmp->tm_mon,
+		    &tmp->tm_mday,
+		    &tmp->tm_hour,
+		    &tmp->tm_min,
+		    &tmp->tm_sec);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+#ifdef RTC_DEBUG
+	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
+#endif
+
+	return 0;
+}
+
+int rtc_set( struct rtc_time *tmp )
+{
+	m48_tod_set(tmp->tm_year,		/* 1980-2079 */
+		    tmp->tm_mon,		/* 01-12 */
+		    tmp->tm_mday,              /* 01-31 */
+		    tmp->tm_hour,		/* 00-23 */
+		    tmp->tm_min,		/* 00-59 */
+		    tmp->tm_sec);		/* 00-59 */
+
+#ifdef RTC_DEBUG
+	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+	return 0;
+}
+
+void
+rtc_reset (void)
+{
+  m48_tod_init();
+}
diff --git a/u-boot/board/bmw/m48t59y.h b/u-boot/board/bmw/m48t59y.h
new file mode 100644
index 0000000..717300d
--- /dev/null
+++ b/u-boot/board/bmw/m48t59y.h
@@ -0,0 +1,57 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M48_T59_Y_H
+#define __M48_T59_Y_H
+
+/*
+ * M48 T59Y -Timekeeping Battery backed SRAM.
+ */
+
+int m48_tod_init(void);
+
+int m48_tod_set(int year,
+		int month,
+		int day,
+		int hour,
+		int minute,
+		int second);
+
+int m48_tod_get(int *year,
+		int *month,
+		int *day,
+		int *hour,
+		int *minute,
+		int *second);
+
+int m48_tod_get_second(void);
+
+void m48_watchdog_arm(int usec);
+
+#endif /*!__M48_T59_Y_H */
diff --git a/u-boot/board/bmw/ns16550.c b/u-boot/board/bmw/ns16550.c
new file mode 100644
index 0000000..be455bb
--- /dev/null
+++ b/u-boot/board/bmw/ns16550.c
@@ -0,0 +1,57 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+typedef struct NS16550 *NS16550_t;
+
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500),
+(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) };
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
+{
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+	return (com_port);
+}
+
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
+{
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+}
+
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
+{
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
+}
+
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
+{
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
+}
+
+int NS16550_tstc (volatile struct NS16550 *com_port)
+{
+	return ((com_port->lsr & LSR_DR) != 0);
+}
diff --git a/u-boot/board/bmw/ns16550.h b/u-boot/board/bmw/ns16550.h
new file mode 100644
index 0000000..8aa251d
--- /dev/null
+++ b/u-boot/board/bmw/ns16550.h
@@ -0,0 +1,79 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ * further modified to support the 8245 duart
+ * modifications (c) Paul Jimenez, Musenki, Inc. 2001.
+ */
+
+
+struct NS16550 {
+	unsigned char rbrthrdlb;	/* 0 */
+	unsigned char ierdmb;		/* 1 */
+	unsigned char iirfcrafr;	/* 2 */
+	unsigned char lcr;		/* 3 */
+	unsigned char mcr;		/* 4 */
+	unsigned char lsr;		/* 5 */
+	unsigned char msr;		/* 6 */
+	unsigned char scr;		/* 7 */
+	unsigned char reserved[2];	/* 8 & 9 */
+	unsigned char dsr;		/* 10 */
+	unsigned char dcr;		/* 11 */
+};
+
+
+#define rbr rbrthrdlb
+#define thr rbrthrdlb
+#define dll rbrthrdlb
+#define ier ierdmb
+#define dlm ierdmb
+#define iir iirfcrafr
+#define fcr iirfcrafr
+#define afr iirfcrafr
+
+#define FCR_FIFO_EN     0x01	/*fifo enable */
+#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_TXSR        0x04	/*transmitter soft reset */
+#define FCR_DMS		0x08	/* DMA Mode Select */
+
+#define MCR_RTS         0x02	/* Readyu to Send */
+#define MCR_LOOP	0x10	/* Local loopback mode enable */
+/* #define MCR_DTR         0x01    noton 8245 duart */
+/* #define MCR_DMA_EN      0x04    noton 8245 duart */
+/* #define MCR_TX_DFR      0x08    noton 8245 duart */
+
+#define LCR_WLS_MSK 0x03	/* character length slect mask */
+#define LCR_WLS_5   0x00	/* 5 bit character length */
+#define LCR_WLS_6   0x01	/* 6 bit character length */
+#define LCR_WLS_7   0x02	/* 7 bit character length */
+#define LCR_WLS_8   0x03	/* 8 bit character length */
+#define LCR_STB     0x04	/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08	/* Parity eneble */
+#define LCR_EPS     0x10	/* Even Parity Select */
+#define LCR_STKP    0x20	/* Stick Parity */
+#define LCR_SBRK    0x40	/* Set Break */
+#define LCR_BKSE    0x80	/* Bank select enable - aka DLAB on 8245 */
+
+#define LSR_DR      0x01	/* Data ready */
+#define LSR_OE      0x02	/* Overrun */
+#define LSR_PE      0x04	/* Parity error */
+#define LSR_FE      0x08	/* Framing error */
+#define LSR_BI      0x10	/* Break */
+#define LSR_THRE    0x20	/* Xmit holding register empty */
+#define LSR_TEMT    0x40	/* Xmitter empty */
+#define LSR_ERR     0x80	/* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1     0x03
+
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc (volatile struct NS16550 *com_port);
+int NS16550_tstc (volatile struct NS16550 *com_port);
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
diff --git a/u-boot/board/bmw/serial.c b/u-boot/board/bmw/serial.c
new file mode 100644
index 0000000..0c97f12
--- /dev/null
+++ b/u-boot/board/bmw/serial.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "ns16550.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_CONS_INDEX == 1
+static struct NS16550 *console =
+		(struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
+#elif CONFIG_CONS_INDEX == 2
+static struct NS16550 *console =
+		(struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
+#else
+#error no valid console defined
+#endif
+
+extern ulong get_bus_freq (ulong);
+
+int serial_init (void)
+{
+	int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
+
+	NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n') {
+		serial_putc ('\r');
+	}
+	NS16550_putc (console, c);
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+
+int serial_getc (void)
+{
+	return NS16550_getc (console);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (console);
+}
+
+void serial_setbrg (void)
+{
+	int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
+
+	NS16550_reinit (console, clock_divisor);
+}
diff --git a/u-boot/board/c2mon/Makefile b/u-boot/board/c2mon/Makefile
new file mode 100644
index 0000000..b49f26d
--- /dev/null
+++ b/u-boot/board/c2mon/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/c2mon/c2mon.c b/u-boot/board/c2mon/c2mon.c
new file mode 100644
index 0000000..717a64b
--- /dev/null
+++ b/u-boot/board/c2mon/c2mon.c
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char *s = (unsigned char *)getenv ("serial#");
+
+	puts ("Board: TTTech C2MON ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long reg;
+	long int size8, size9;
+	long int size = 0;
+
+	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 2 the SDRAM bank 2 at physical address 0.
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size = size9;
+/*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {			/* back to 8 columns            */
+		size = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/*
+	 * No bank 1
+	 *
+	 * invalidate bank
+	 */
+	memctl->memc_br3 = 0;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/u-boot/board/c2mon/flash.c b/u-boot/board/c2mon/flash.c
new file mode 100644
index 0000000..d33cb6c
--- /dev/null
+++ b/u-boot/board/c2mon/flash.c
@@ -0,0 +1,570 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/c2mon/pcmcia.c b/u-boot/board/c2mon/pcmcia.c
new file mode 100644
index 0000000..c833b20
--- /dev/null
+++ b/u-boot/board/c2mon/pcmcia.c
@@ -0,0 +1,284 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if	defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "C2MON"
+
+static void cfg_ports (void)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	ushort sreg;
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/*
+	* Configure Port C for TPS2211 PC-Card Power-Interface Switch
+	*
+	* Switch off all voltages, assert shutdown
+	*/
+	sreg = immap->im_ioport.iop_pcdat;
+	sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1);	/* VAVPP => Hi-Z */
+	sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1);	/* 3V and 5V off */
+	immap->im_ioport.iop_pcdat = sreg;
+
+	immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
+	immap->im_ioport.iop_pcdir |=   TPS2211_OUTPUTS;
+
+	debug ("Set Port C: PAR:     %04x DIR:     %04x DAT:     %04x\n",
+	       immap->im_ioport.iop_pcpar,
+	       immap->im_ioport.iop_pcdir,
+	       immap->im_ioport.iop_pcdat);
+
+	/*
+	* Configure Port B for TPS2211 PC-Card Power-Interface Switch
+	*
+	* Over-Current Input only
+	*/
+	cp->cp_pbpar &= ~(TPS2211_INPUTS);
+	cp->cp_pbdir &= ~(TPS2211_INPUTS);
+
+	debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
+	       cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, pipr, mask;
+	ushort sreg;
+	int i;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+	cfg_ports ();
+
+	/*
+	* Configure SIUMCR to enable PCMCIA port B
+	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	*/
+	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+	*/
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	pipr = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       pipr,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+	sreg = immap->im_ioport.iop_pcdat;
+	if ((pipr & mask) == mask) {
+		sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1 |	/* VAVPP => Hi-Z */
+				TPS2211_VCCD1);			/* 5V on	*/
+		sreg &= ~(TPS2211_VCCD0);			/* 3V off	*/
+		puts (" 5.0V card found: ");
+	} else {
+		sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1 |	/* VAVPP => Hi-Z */
+				TPS2211_VCCD0);			/* 3V on	*/
+		sreg &= ~(TPS2211_VCCD1);			/* 5V off	*/
+		puts (" 3.3V card found: ");
+	}
+
+	debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
+	       sreg,
+	       ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
+	       (!(sreg & TPS2211_VCCD0) &&  (sreg & TPS2211_VCCD1)) ? "on" : "off"
+	      );
+
+	immap->im_ioport.iop_pcdat = sreg;
+
+	/*  Wait 500 ms; use this to check for over-current */
+	for (i=0; i<5000; ++i) {
+		if ((cp->cp_pbdat & TPS2211_OC) == 0) {
+			printf ("   *** Overcurrent - Safety shutdown ***\n");
+			immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
+			return (1);
+		}
+		udelay (100);
+	}
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	/* ALl voltages off / Hi-Z */
+	immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
+			TPS2211_VCCD0 | TPS2211_VCCD1 );
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+	ushort sreg;
+
+	debug ("voltage_set: "
+			PCMCIA_BOARD_MSG
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	* Disable PCMCIA buffers (isolate the interface)
+	* and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Configure Port C pins for
+	* 5 Volts Enable and 3 Volts enable,
+	* Turn all power pins to Hi-Z
+	*/
+	debug ("PCMCIA power OFF\n");
+	cfg_ports ();	/* Enables switch, but all in Hi-Z */
+
+	sreg  = immap->im_ioport.iop_pcdat;
+	sreg |= TPS2211_VPPD0 | TPS2211_VPPD1;		/* VAVPP always Hi-Z */
+
+	switch(vcc) {
+		case  0:			break;	/* Switch off		*/
+		case 33: sreg |=  TPS2211_VCCD0;	/* Switch on 3.3V	*/
+		sreg &= ~TPS2211_VCCD1;
+		break;
+		case 50: sreg &= ~TPS2211_VCCD0;	/* Switch on 5.0V	*/
+		sreg |=  TPS2211_VCCD1;
+		break;
+		default:			goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+	       pcmp->pcmc_pipr,
+	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+	immap->im_ioport.iop_pcdat = sreg;
+
+#ifdef DEBUG
+{
+	char *s;
+
+	if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
+		s = "at 3.3V";
+	} else if (!(sreg & TPS2211_VCCD0) &&  (sreg & TPS2211_VCCD1)) {
+		s = "at 5.0V";
+	} else {
+		s = "down";
+	}
+	printf ("PCMCIA powered %s\n", s);
+}
+#endif
+
+done:
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/c2mon/u-boot.lds b/u-boot/board/c2mon/u-boot.lds
new file mode 100644
index 0000000..7a088c9
--- /dev/null
+++ b/u-boot/board/c2mon/u-boot.lds
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    net/libnet.o			(.text*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/c2mon/u-boot.lds.debug b/u-boot/board/c2mon/u-boot.lds.debug
new file mode 100644
index 0000000..99098bf
--- /dev/null
+++ b/u-boot/board/c2mon/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/calao/sbc35_a9g20/Makefile b/u-boot/board/calao/sbc35_a9g20/Makefile
new file mode 100644
index 0000000..cc4219d
--- /dev/null
+++ b/u-boot/board/calao/sbc35_a9g20/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= sbc35_a9g20.o
+COBJS-$(CONFIG_ATMEL_SPI)	+= spi.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/calao/sbc35_a9g20/config.mk b/u-boot/board/calao/sbc35_a9g20/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/calao/sbc35_a9g20/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/calao/sbc35_a9g20/sbc35_a9g20.c b/u-boot/board/calao/sbc35_a9g20/sbc35_a9g20.c
new file mode 100644
index 0000000..9df45c0
--- /dev/null
+++ b/u-boot/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void sbc35_a9g20_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void sbc35_a9g20_macb_hw_init(void)
+{
+	unsigned long rstc;
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (rstc) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+	sbc35_a9g20_nand_hw_init();
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4 | 1 << 5);
+#endif
+#ifdef CONFIG_MACB
+	sbc35_a9g20_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
+		return -1;
+
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/calao/sbc35_a9g20/spi.c b/u-boot/board/calao/sbc35_a9g20/spi.c
new file mode 100644
index 0000000..1057fa2
--- /dev/null
+++ b/u-boot/board/calao/sbc35_a9g20/spi.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+#define SBC_A9260_CS0_PIN	AT91_PIN_PA3
+#define SBC_A9260_CS1_PIN	AT91_PIN_PC11
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && (cs == 1 || cs == 0);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	if(slave->cs == 0)
+		at91_set_gpio_value(SBC_A9260_CS0_PIN, 0);
+	else if(slave->cs == 1)
+		at91_set_gpio_value(SBC_A9260_CS1_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	if(slave->cs == 0)
+		at91_set_gpio_value(SBC_A9260_CS0_PIN, 1);
+	else if(slave->cs == 1)
+		at91_set_gpio_value(SBC_A9260_CS1_PIN, 1);
+}
+
+void spi_init_f(void)
+{
+	/* everything done in board_init */
+}
diff --git a/u-boot/board/calao/tny_a9260/Makefile b/u-boot/board/calao/tny_a9260/Makefile
new file mode 100644
index 0000000..151a228
--- /dev/null
+++ b/u-boot/board/calao/tny_a9260/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= tny_a9260.o
+COBJS-$(CONFIG_ATMEL_SPI)	+= spi.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/calao/tny_a9260/config.mk b/u-boot/board/calao/tny_a9260/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/calao/tny_a9260/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/calao/tny_a9260/spi.c b/u-boot/board/calao/tny_a9260/spi.c
new file mode 100644
index 0000000..2db9f84
--- /dev/null
+++ b/u-boot/board/calao/tny_a9260/spi.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+#define TNY_A9260_CS_PIN	AT91_PIN_PC11
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_gpio_value(TNY_A9260_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_gpio_value(TNY_A9260_CS_PIN, 1);
+}
+
+void spi_init_f(void)
+{
+	/* everything done in board_init */
+}
diff --git a/u-boot/board/calao/tny_a9260/tny_a9260.c b/u-boot/board/calao/tny_a9260/tny_a9260.c
new file mode 100644
index 0000000..d51ca15
--- /dev/null
+++ b/u-boot/board/calao/tny_a9260/tny_a9260.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void tny_a9260_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+#if defined(CONFIG_TNY_A9260)
+	gd->bd->bi_arch_number = MACH_TYPE_TNY_A9260;
+#elif defined(CONFIG_TNY_A9G20)
+	gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+	tny_a9260_nand_hw_init();
+	at91_spi0_hw_init(1 << 5);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
+		return -1;
+
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
diff --git a/u-boot/board/canmb/Makefile b/u-boot/board/canmb/Makefile
new file mode 100644
index 0000000..0e2ec4b
--- /dev/null
+++ b/u-boot/board/canmb/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+#ifneq ($(OBJTREE),$(SRCTREE))
+#$(shell mkdir -p $(obj)../common)
+#endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+#../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/canmb/canmb.c b/u-boot/board/canmb/canmb.c
new file mode 100644
index 0000000..6c3d2ac
--- /dev/null
+++ b/u-boot/board/canmb/canmb.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
+	return 0;
+}
diff --git a/u-boot/board/canmb/mt48lc16m32s2-75.h b/u-boot/board/canmb/mt48lc16m32s2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/canmb/mt48lc16m32s2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/cerf250/Makefile b/u-boot/board/cerf250/Makefile
new file mode 100644
index 0000000..d824ffa
--- /dev/null
+++ b/u-boot/board/cerf250/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cerf250.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cerf250/cerf250.c b/u-boot/board/cerf250/cerf250.c
new file mode 100644
index 0000000..043afea
--- /dev/null
+++ b/u-boot/board/cerf250/cerf250.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of cerf PXA Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/cerf250/flash.c b/u-boot/board/cerf250/flash.c
new file mode 100644
index 0000000..a4b201e
--- /dev/null
+++ b/u-boot/board/cerf250/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/cm-bf527/Makefile b/u-boot/board/cm-bf527/Makefile
new file mode 100644
index 0000000..4d7bf14
--- /dev/null
+++ b/u-boot/board/cm-bf527/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm-bf527/cm-bf527.c b/u-boot/board/cm-bf527/cm-bf527.c
new file mode 100644
index 0000000..a5f70a4
--- /dev/null
+++ b/u-boot/board/cm-bf527/cm-bf527.c
@@ -0,0 +1,72 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+#include "../cm-bf537e/gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF527 board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	bool valid_mac = false;
+
+	/* the MAC is stored in OTP memory page 0xDF */
+	uint32_t ret;
+	uint64_t otp_mac;
+
+	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+	if (!(ret & OTP_MASTER_ERROR)) {
+		uchar *otp_mac_p = (uchar *)&otp_mac;
+
+		for (ret = 0; ret < 6; ++ret)
+			mac_addr[ret] = otp_mac_p[5 - ret];
+
+		if (is_valid_ether_addr(mac_addr))
+			valid_mac = true;
+	}
+
+	if (!valid_mac) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(mac_addr);
+	}
+
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+
+	return 0;
+}
diff --git a/u-boot/board/cm-bf527/config.mk b/u-boot/board/cm-bf527/config.mk
new file mode 100644
index 0000000..790fe99
--- /dev/null
+++ b/u-boot/board/cm-bf527/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/cm-bf527/gpio_cfi_flash.c b/u-boot/board/cm-bf527/gpio_cfi_flash.c
new file mode 100644
index 0000000..6e62fff
--- /dev/null
+++ b/u-boot/board/cm-bf527/gpio_cfi_flash.c
@@ -0,0 +1,3 @@
+#define GPIO_PIN_1 GPIO_PH9
+#define GPIO_PIN_2 GPIO_PG11
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/u-boot/board/cm-bf533/Makefile b/u-boot/board/cm-bf533/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/cm-bf533/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm-bf533/cm-bf533.c b/u-boot/board/cm-bf533/cm-bf533.c
new file mode 100644
index 0000000..a863195
--- /dev/null
+++ b/u-boot/board/cm-bf533/cm-bf533.c
@@ -0,0 +1,26 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF533 board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/u-boot/board/cm-bf533/config.mk b/u-boot/board/cm-bf533/config.mk
new file mode 100644
index 0000000..a0d1749
--- /dev/null
+++ b/u-boot/board/cm-bf533/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf533-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/cm-bf537e/Makefile b/u-boot/board/cm-bf537e/Makefile
new file mode 100644
index 0000000..4d7bf14
--- /dev/null
+++ b/u-boot/board/cm-bf537e/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm-bf537e/cm-bf537e.c b/u-boot/board/cm-bf537e/cm-bf537e.c
new file mode 100644
index 0000000..1e350dc
--- /dev/null
+++ b/u-boot/board/cm-bf537e/cm-bf537e.c
@@ -0,0 +1,52 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include "gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF537E board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+
+	return 0;
+}
diff --git a/u-boot/board/cm-bf537e/config.mk b/u-boot/board/cm-bf537e/config.mk
new file mode 100644
index 0000000..c5d45c7
--- /dev/null
+++ b/u-boot/board/cm-bf537e/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/cm-bf537e/gpio_cfi_flash.c b/u-boot/board/cm-bf537e/gpio_cfi_flash.c
new file mode 100644
index 0000000..1075cc4
--- /dev/null
+++ b/u-boot/board/cm-bf537e/gpio_cfi_flash.c
@@ -0,0 +1,81 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include "gpio_cfi_flash.h"
+
+/* Allow this driver to be shared among boards */
+#ifndef GPIO_PIN_1
+#define GPIO_PIN_1  GPIO_PF4
+#endif
+#define GPIO_MASK_1 (1 << 21)
+#ifndef GPIO_PIN_2
+#define GPIO_MASK_2 (0)
+#else
+#define GPIO_MASK_2 (1 << 22)
+#endif
+#ifndef GPIO_PIN_3
+#define GPIO_MASK_3 (0)
+#else
+#define GPIO_MASK_3 (1 << 23)
+#endif
+#define GPIO_MASK   (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3)
+
+void *gpio_cfi_flash_swizzle(void *vaddr)
+{
+	unsigned long addr = (unsigned long)vaddr;
+
+	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
+
+#ifdef GPIO_PIN_2
+	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
+#endif
+
+#ifdef GPIO_PIN_3
+	gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3);
+#endif
+
+	SSYNC();
+	udelay(1);
+
+	return (void *)(addr & ~GPIO_MASK);
+}
+
+#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
+#define __raw_readq(addr) *(volatile u64 *)addr
+
+#define MAKE_FLASH(size, sfx) \
+void flash_write##size(u##size value, void *addr) \
+{ \
+	__raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
+} \
+u##size flash_read##size(void *addr) \
+{ \
+	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
+}
+MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
+
+void gpio_cfi_flash_init(void)
+{
+	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+	gpio_direction_output(GPIO_PIN_1, 0);
+#ifdef GPIO_PIN_2
+	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+	gpio_direction_output(GPIO_PIN_2, 0);
+#endif
+#ifdef GPIO_PIN_3
+	gpio_request(GPIO_PIN_3, "gpio_cfi_flash");
+	gpio_direction_output(GPIO_PIN_3, 0);
+#endif
+}
diff --git a/u-boot/board/cm-bf537e/gpio_cfi_flash.h b/u-boot/board/cm-bf537e/gpio_cfi_flash.h
new file mode 100644
index 0000000..5211e97
--- /dev/null
+++ b/u-boot/board/cm-bf537e/gpio_cfi_flash.h
@@ -0,0 +1,10 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+void *gpio_cfi_flash_swizzle(void *vaddr);
+void gpio_cfi_flash_init(void);
diff --git a/u-boot/board/cm-bf537u/Makefile b/u-boot/board/cm-bf537u/Makefile
new file mode 100644
index 0000000..4d7bf14
--- /dev/null
+++ b/u-boot/board/cm-bf537u/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm-bf537u/cm-bf537u.c b/u-boot/board/cm-bf537u/cm-bf537u.c
new file mode 100644
index 0000000..4b7e864
--- /dev/null
+++ b/u-boot/board/cm-bf537u/cm-bf537u.c
@@ -0,0 +1,59 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include "../cm-bf537e/gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF537U board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+
+	return 0;
+}
diff --git a/u-boot/board/cm-bf537u/config.mk b/u-boot/board/cm-bf537u/config.mk
new file mode 100644
index 0000000..c5d45c7
--- /dev/null
+++ b/u-boot/board/cm-bf537u/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/cm-bf537u/gpio_cfi_flash.c b/u-boot/board/cm-bf537u/gpio_cfi_flash.c
new file mode 100644
index 0000000..ef5ea8b
--- /dev/null
+++ b/u-boot/board/cm-bf537u/gpio_cfi_flash.c
@@ -0,0 +1,2 @@
+#define GPIO_PIN_1 GPIO_PH0
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/u-boot/board/cm-bf548/Makefile b/u-boot/board/cm-bf548/Makefile
new file mode 100644
index 0000000..98a8121
--- /dev/null
+++ b/u-boot/board/cm-bf548/Makefile
@@ -0,0 +1,55 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_VIDEO)      += video.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm-bf548/cm-bf548.c b/u-boot/board/cm-bf548/cm-bf548.c
new file mode 100644
index 0000000..90ce4c3
--- /dev/null
+++ b/u-boot/board/cm-bf548/cm-bf548.c
@@ -0,0 +1,43 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF548 board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* Set async addr lines as peripheral */
+	const unsigned short pins[] = {
+		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+		P_A21, P_A22, P_A23, P_A24, 0
+	};
+	return peripheral_request_list(pins, "async");
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/cm-bf548/config.mk b/u-boot/board/cm-bf548/config.mk
new file mode 100644
index 0000000..da6aa52
--- /dev/null
+++ b/u-boot/board/cm-bf548/config.mk
@@ -0,0 +1,39 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf548-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/cm-bf548/video.c b/u-boot/board/cm-bf548/video.c
new file mode 100644
index 0000000..4703098
--- /dev/null
+++ b/u-boot/board/cm-bf548/video.c
@@ -0,0 +1,339 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#ifdef CONFIG_VIDEO
+
+#define DMA_SIZE16	2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_X_RES		480	/*Horizontal Resolution */
+#define LCD_Y_RES		272	/* Vertical Resolution */
+
+#define LCD_BPP			24	/* Bit Per Pixel */
+#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
+#define	DMA_BUS_SIZE		32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/* 	-- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency 	1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period 		TH - 525 - Clock
+ * Pulse width 		THp - 41 - Clock
+ * Horizontal period 	THd - 480 - Clock
+ * Back porch 		THb - 2 - Clock
+ * Front porch 		THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period 		TV - 286 - Line
+ * Pulse width 		TVp - 10 - Line
+ * Vertical period 	TVd - 272 - Line
+ * Back porch 		TVb - 2 - Line
+ * Front porch 		TVf - 2 - Line
+ */
+
+#define	LCD_CLK         	(8*1000*1000)	/* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT		LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT		LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE		525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME		286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL		41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL		EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY		43
+
+/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB		(EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF		(EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY		12
+
+#define EPPI_CLIP		0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL		(0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+	u32 sclk = get_sclk();
+
+	/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+	return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+	u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+	bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+	bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+	bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+	bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+	bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+	bfin_write_EPPI0_FRAME(EPPI_FRAME);
+	bfin_write_EPPI0_LINE(EPPI_LINE);
+
+	bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+	bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+	bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+	bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+	bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+	bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+				 RGB_FMT_EN);
+#else
+	bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+				 ~RGB_FMT_EN);
+#endif
+
+}
+
+#define               DEB2_URGENT  0x2000	/* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+#if defined(CONFIG_DEB_DMA_URGENT)
+	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
+#endif
+
+	bfin_write_DMA12_START_ADDR(dst);
+
+	/* X count */
+	bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
+	bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
+
+	/* Y count */
+	bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
+	bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
+
+	/* DMA Config */
+	bfin_write_DMA12_CONFIG(
+	    WDSIZE_32 |	/* 32 bit DMA */
+	    DMA2D |		/* 2D DMA */
+	    FLOW_AUTO		/* autobuffer mode */
+	);
+}
+
+void Init_Ports(void)
+{
+	const unsigned short pins[] = {
+		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
+#if !defined(CONFIG_VIDEO_RGB666)
+		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+		P_PPI0_D23,
+#endif
+		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+	};
+	peripheral_request_list(pins, "lcd");
+
+	gpio_request(GPIO_PE3, "lcd-disp");
+	gpio_direction_output(GPIO_PE3, 1);
+}
+
+void EnableDMA(void)
+{
+	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
+}
+
+void DisableDMA(void)
+{
+	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+	Init_Ports();
+	Init_DMA(dst);
+	EnableDMA();
+	Init_PPI();
+	EnablePPI();
+
+	return 0;
+}
+
+void video_stop(void)
+{
+	DisablePPI();
+	DisableDMA();
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+	if (dcache_status())
+		blackfin_dcache_flush_range(logo->data,
+					    logo->data + logo->size);
+
+	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+	/* Setup destination start address */
+	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+				      + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+	/* Setup destination xcount */
+	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+	/* Setup destination xmodify */
+	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+	/* Setup destination ycount */
+	bfin_write_MDMA_D0_Y_COUNT(logo->height);
+	/* Setup destination ymodify */
+	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
+				    DMA_SIZE16);
+
+	/* Setup Source start address */
+	bfin_write_MDMA_S0_START_ADDR(logo->data);
+	/* Setup Source xcount */
+	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+	/* Setup Source xmodify */
+	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+	/* Setup Source ycount */
+	bfin_write_MDMA_S0_Y_COUNT(logo->height);
+	/* Setup Source ymodify */
+	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+	/* Enable source DMA */
+	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+	SSYNC();
+	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
+
+	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
+				      | DMA_ERR);
+	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
+				      | DMA_ERR);
+
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+	int error, devices = 1;
+	struct stdio_dev videodev;
+
+	u8 *dst;
+	u32 fbmem_size =
+	    LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+	dst = malloc(fbmem_size);
+
+	if (dst == NULL) {
+		printf("Failed to alloc FB memory\n");
+		return -1;
+	}
+#ifdef EASYLOGO_ENABLE_GZIP
+	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+		puts("Failed to decompress logo\n");
+		free(dst);
+		return -1;
+	}
+	bfin_logo.data = data;
+#endif
+
+	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
+	       fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+		    (LCD_X_RES - bfin_logo.width) / 2,
+		    (LCD_Y_RES - bfin_logo.height) / 2);
+
+	video_init(dst);	/* Video initialization */
+
+	memset(&videodev, 0, sizeof(videodev));
+
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
+	videodev.putc = video_putc;	/* 'putc' function */
+	videodev.puts = video_puts;	/* 'puts' function */
+
+	error = stdio_register(&videodev);
+
+	return (error == 0) ? devices : error;
+}
+
+#endif
diff --git a/u-boot/board/cm-bf561/Makefile b/u-boot/board/cm-bf561/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/cm-bf561/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm-bf561/cm-bf561.c b/u-boot/board/cm-bf561/cm-bf561.c
new file mode 100644
index 0000000..5741f64
--- /dev/null
+++ b/u-boot/board/cm-bf561/cm-bf561.c
@@ -0,0 +1,26 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF561 core module\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
diff --git a/u-boot/board/cm-bf561/config.mk b/u-boot/board/cm-bf561/config.mk
new file mode 100644
index 0000000..19cdefc
--- /dev/null
+++ b/u-boot/board/cm-bf561/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/cm4008/Makefile b/u-boot/board/cm4008/Makefile
new file mode 100644
index 0000000..e9bae19
--- /dev/null
+++ b/u-boot/board/cm4008/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cm4008.o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm4008/cm4008.c b/u-boot/board/cm4008/cm4008.c
new file mode 100644
index 0000000..d34737c
--- /dev/null
+++ b/u-boot/board/cm4008/cm4008.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	/* arch number of CM4008 */
+	gd->bd->bi_arch_number = 624;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/u-boot/board/cm4008/config.mk b/u-boot/board/cm4008/config.mk
new file mode 100644
index 0000000..0d5923b
--- /dev/null
+++ b/u-boot/board/cm4008/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/u-boot/board/cm4008/flash.c b/u-boot/board/cm4008/flash.c
new file mode 100644
index 0000000..2e66872
--- /dev/null
+++ b/u-boot/board/cm4008/flash.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/cm41xx/Makefile b/u-boot/board/cm41xx/Makefile
new file mode 100644
index 0000000..e608fe8
--- /dev/null
+++ b/u-boot/board/cm41xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cm41xx.o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm41xx/cm41xx.c b/u-boot/board/cm41xx/cm41xx.c
new file mode 100644
index 0000000..02d05af
--- /dev/null
+++ b/u-boot/board/cm41xx/cm41xx.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	/* arch number of CM41xx */
+	gd->bd->bi_arch_number = 672;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/u-boot/board/cm41xx/config.mk b/u-boot/board/cm41xx/config.mk
new file mode 100644
index 0000000..0d5923b
--- /dev/null
+++ b/u-boot/board/cm41xx/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/u-boot/board/cm41xx/flash.c b/u-boot/board/cm41xx/flash.c
new file mode 100644
index 0000000..2e66872
--- /dev/null
+++ b/u-boot/board/cm41xx/flash.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/cm5200/Makefile b/u-boot/board/cm5200/Makefile
new file mode 100644
index 0000000..ac431a7
--- /dev/null
+++ b/u-boot/board/cm5200/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o cmd_cm5200.o fwupdate.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cm5200/cm5200.c b/u-boot/board/cm5200/cm5200.c
new file mode 100644
index 0000000..b25887b
--- /dev/null
+++ b/u-boot/board/cm5200/cm5200.c
@@ -0,0 +1,384 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Adapted to U-Boot 1.2 by:
+ *   Bartlomiej Sieka <tur@semihalf.com>:
+ *      - HW ID readout from EEPROM
+ *      - module detection
+ *   Grzegorz Bernacki <gjb@semihalf.com>:
+ *      - run-time SDRAM controller configuration
+ *      - LIBFDT support
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+
+#include "cm5200.h"
+#include "fwupdate.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static hw_id_t hw_id;
+
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
+						hi_addr_bit;
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
+						hi_addr_bit;
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+						hi_addr_bit;
+
+	/* auto refresh, second time */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+						hi_addr_bit;
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+
+/*
+ * Retrieve memory configuration for a given module. board_type is the index
+ * in hw_id_list[] corresponding to the module we are executing on; we return
+ * SDRAM controller settings approprate for this module.
+ */
+static mem_conf_t* get_mem_config(int board_type)
+{
+	switch(board_type){
+		case CM1_QA:
+			return memory_config[0];
+		case CM11_QA:
+		case CMU1_QA:
+			return memory_config[1];
+		default:
+			printf("ERROR: Unknown module, using a default SDRAM "
+				"configuration - things may not work!!!.\n");
+			return memory_config[0];
+	}
+}
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+	mem_conf_t *mem_conf;
+
+	mem_conf = get_mem_config(board_type);
+
+	/* configure SDRAM start/end for detection */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
+
+	sdram_start(0, mem_conf);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1, mem_conf);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0, mem_conf);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller.  Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
+	 * the MPC5200B User's Manual.
+	 */
+	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+	__asm__ volatile ("sync");
+
+	return dramsize;
+}
+
+
+/*
+ * Read module hardware identification data from the I2C EEPROM.
+ */
+static void read_hw_id(hw_id_t hw_id)
+{
+	int i;
+	for (i = 0; i < HW_ID_ELEM_COUNT; ++i)
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM,
+				hw_id_format[i].offset,
+				2,
+				(uchar *)&hw_id[i][0],
+				hw_id_format[i].length) != 0)
+			printf("ERROR: can't read HW ID from EEPROM\n");
+}
+
+
+/*
+ * Identify module we are running on, set gd->board_type to the index in
+ * hw_id_list[] corresponding to the module identifed, or to
+ * CM5200_UNKNOWN_MODULE if we can't identify the module.
+ */
+static void identify_module(hw_id_t hw_id)
+{
+	int i, j, element;
+	char match;
+	gd->board_type = CM5200_UNKNOWN_MODULE;
+	for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
+		match = 1;
+		for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
+			element = hw_id_identify[j];
+			if (strncmp(hw_id_list[i][element],
+					&hw_id[element][0],
+					hw_id_format[element].length) != 0) {
+				match = 0;
+				break;
+			}
+		}
+		if (match) {
+			gd->board_type = i;
+			break;
+		}
+	}
+}
+
+
+/*
+ * Compose string with module name.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_module_name(hw_id_t hw_id, char *buf)
+{
+	char tmp[MODULE_NAME_MAXLEN];
+	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+	strncat(buf, ".", 1);
+	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+	strncat(buf, " (", 2);
+	strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
+		hw_id_format[IDENTIFICATION_NUMBER].length);
+	sprintf(tmp, " / %u.%u)",
+		hw_id[MAJOR_SW_VERSION][0],
+		hw_id[MINOR_SW_VERSION][0]);
+	strcat(buf, tmp);
+}
+
+
+/*
+ * Compose string with hostname.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_hostname(hw_id_t hw_id, char *buf)
+{
+	char *p;
+	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+	strncat(buf, "_", 1);
+	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+	for (p = buf; *p; ++p)
+		*p = tolower(*p);
+
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * Update 'model' and 'memory' properties in the blob according to the module
+ * that we are running on.
+ */
+static void ft_blob_update(void *blob, bd_t *bd)
+{
+	int len, ret, nodeoffset = 0;
+	char module_name[MODULE_NAME_MAXLEN] = {0};
+
+	compose_module_name(hw_id, module_name);
+	len = strlen(module_name) + 1;
+
+	ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
+	if (ret < 0)
+	printf("ft_blob_update(): cannot set /model property err:%s\n",
+		fdt_strerror(ret));
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+
+/*
+ * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
+ * that we need to use local variable for readout, because global data is not
+ * writable yet (and we'll have to redo the readout later on).
+ */
+int checkboard(void)
+{
+	hw_id_t hw_id_tmp;
+	char module_name_tmp[MODULE_NAME_MAXLEN] = "";
+
+	/*
+	 * We need I2C to access HW ID data from EEPROM, so we call i2c_init()
+	 * here despite the fact that it will be called again later on. We
+	 * also use a little trick to silence I2C-related output.
+	 */
+	gd->flags |= GD_FLG_SILENT;
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	gd->flags &= ~GD_FLG_SILENT;
+
+	read_hw_id(hw_id_tmp);
+	identify_module(hw_id_tmp);	/* this sets gd->board_type */
+	compose_module_name(hw_id_tmp, module_name_tmp);
+
+	if (gd->board_type != CM5200_UNKNOWN_MODULE)
+		printf("Board: %s\n", module_name_tmp);
+	else
+		printf("Board: unrecognized cm5200 module (%s)\n",
+			module_name_tmp);
+
+	return 0;
+}
+
+
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection
+	 * process. Note that CS_BOOT cannot be cleared when executing in
+	 * flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+	/* Now that we can write to global data, read HW ID again. */
+	read_hw_id(hw_id);
+	return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	uchar buf[6];
+	char str[18];
+	char hostname[MODULE_NAME_MAXLEN];
+
+	/* Read ethaddr from EEPROM */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
+		sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
+			buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+		/* Check if MAC addr is owned by Schindler */
+		if (strstr(str, "00:06:C3") != str)
+			printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
+				" in EEPROM.\n", str);
+		else {
+			printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
+				str);
+			setenv("ethaddr", str);
+		}
+	} else {
+		printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
+			" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
+			CONFIG_MAC_OFFSET);
+	}
+#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
+	if (!getenv("ethaddr"))
+		printf(LOG_PREFIX "MAC address not set, networking is not "
+					"operational\n");
+
+	/* set the hostname appropriate to the module we're running on */
+	hostname[0] = 0x00;
+	compose_hostname(hw_id, hostname);
+	setenv("hostname", hostname);
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+#ifdef CONFIG_USB_STORAGE
+	cm5200_fwupdate();
+#endif /* CONFIG_USB_STORAGE */
+	return 0;
+}
+#endif /* CONFIG_LAST_STAGE_INIT */
+
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/cm5200/cm5200.h b/u-boot/board/cm5200/cm5200.h
new file mode 100644
index 0000000..b2ea5ce
--- /dev/null
+++ b/u-boot/board/cm5200/cm5200.h
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Bartlomiej Sieka <tur@semihalf.com>
+ * Author: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CM5200_H
+#define _CM5200_H
+
+
+/*
+ * Definitions and declarations for the modules of the cm5200 platform. Mostly
+ * related to reading the hardware identification data (HW ID) from the I2C
+ * EEPROM, detection of the particular module we are executing on, and
+ * appropriate SDRAM controller initialization.
+ */
+
+
+#define CM5200_UNKNOWN_MODULE	0xffffffff
+
+enum {
+	DEVICE_NAME,		/* 0 */
+	GENERATION,		/* 1 */
+	PCB_NAME,		/* 2 */
+	FORM,			/* 3 */
+	VERSION,		/* 4 */
+	IDENTIFICATION_NUMBER,	/* 5 */
+	MAJOR_SW_VERSION,	/* 6 */
+	MINOR_SW_VERSION,	/* 7 */
+	/* add new alements above this line */
+	HW_ID_ELEM_COUNT	/* count */
+};
+
+/*
+ * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
+ */
+
+#define DEVICE_NAME_OFFSET		0x02
+#define GENERATION_OFFSET		0x0b
+#define PCB_NAME_OFFSET			0x0c
+#define FORM_OFFSET			0x15
+#define VERSION_OFFSET			0x16
+#define IDENTIFICATION_NUMBER_OFFSET	0x19
+#define MAJOR_SW_VERSION_OFFSET		0x0480
+#define MINOR_SW_VERSION_OFFSET		0x0481
+
+
+#define DEVICE_NAME_LEN			0x09
+#define GENERATION_LEN			0x01
+#define PCB_NAME_LEN			0x09
+#define FORM_LEN			0x01
+#define VERSION_LEN			0x03
+#define IDENTIFICATION_NUMBER_LEN	0x09
+#define MAJOR_SW_VERSION_LEN		0x01
+#define MINOR_SW_VERSION_LEN		0x01
+
+#define HW_ID_ELEM_MAXLEN		0x09	/* MAX(XXX_LEN) */
+
+/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
+#define MODULE_NAME_MAXLEN		64
+
+
+/* storage for HW ID read from EEPROM */
+typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
+
+
+/* HW ID layout in EEPROM */
+static struct {
+	unsigned int offset;
+	unsigned int length;
+} hw_id_format[HW_ID_ELEM_COUNT] = {
+	{DEVICE_NAME_OFFSET,		DEVICE_NAME_LEN},
+	{GENERATION_OFFSET,		GENERATION_LEN},
+	{PCB_NAME_OFFSET,		PCB_NAME_LEN},
+	{FORM_OFFSET,			FORM_LEN},
+	{VERSION_OFFSET,		VERSION_LEN},
+	{IDENTIFICATION_NUMBER_OFFSET,	IDENTIFICATION_NUMBER_LEN},
+	{MAJOR_SW_VERSION_OFFSET,	MAJOR_SW_VERSION_LEN},
+	{MINOR_SW_VERSION_OFFSET,	MINOR_SW_VERSION_LEN},
+};
+
+
+/* HW ID data found in EEPROM on supported modules */
+static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+	"CM",		/* DEVICE_NAME */
+	"1",		/* GENERATION */
+	"CM1",		/* PCB_NAME */
+	"Q",		/* FORM */
+	"A",		/* VERSION */
+	"591881",	/* IDENTIFICATION_NUMBER */
+	"",		/* MAJOR_SW_VERSION */
+	"",		/* MINOR_SW_VERSION */
+};
+
+static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
+	"CM",		/* DEVICE_NAME */
+	"1",		/* GENERATION */
+	"CM11",		/* PCB_NAME */
+	"Q",		/* FORM */
+	"A",		/* VERSION */
+	"594200",	/* IDENTIFICATION_NUMBER */
+	"",		/* MAJOR_SW_VERSION */
+	"",		/* MINOR_SW_VERSION */
+};
+
+static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+	"CMU",		/* DEVICE_NAME */
+	"1",		/* GENERATION */
+	"CMU1",		/* PCB_NAME */
+	"Q",		/* FORM */
+	"A",		/* VERSION */
+	"594128",	/* IDENTIFICATION_NUMBER */
+	"",		/* MAJOR_SW_VERSION */
+	"",		/* MINOR_SW_VERSION */
+};
+
+
+/* list of known modules */
+static char **hw_id_list[] = {
+	cm1_qa_hw_id,
+	cm11_qa_hw_id,
+	cmu1_qa_hw_id,
+};
+
+/* indices to the above list - keep in sync */
+enum {
+	CM1_QA,
+	CM11_QA,
+	CMU1_QA,
+};
+
+
+/* identify modules based on these hw id elements */
+static int hw_id_identify[] = {
+	PCB_NAME,
+	FORM,
+	VERSION,
+};
+
+
+/* Registers' settings for SDRAM controller intialization */
+typedef struct {
+	ulong mode;
+	ulong control;
+	ulong config1;
+	ulong config2;
+} mem_conf_t;
+
+static mem_conf_t k4s561632E = {
+	0x00CD0000,      /* CASL 3, burst length 8 */
+	0x514F0000,
+	0xE2333900,
+	0x8EE70000
+};
+
+static mem_conf_t mt48lc32m16a2 = {
+	0x00CD0000,      /* CASL 3, burst length 8 */
+	0x514F0000,
+	0xD2322800,
+	0x8AD70000
+};
+
+static mem_conf_t* memory_config[] = {
+	&k4s561632E,
+	&mt48lc32m16a2
+};
+
+#endif /* _CM5200_H */
diff --git a/u-boot/board/cm5200/cmd_cm5200.c b/u-boot/board/cm5200/cmd_cm5200.c
new file mode 100644
index 0000000..df372d9
--- /dev/null
+++ b/u-boot/board/cm5200/cmd_cm5200.c
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
+ *
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <usb.h>
+
+#ifdef CONFIG_CMD_BSP
+
+static int do_i2c_test(char * const argv[])
+{
+	unsigned char temp, temp1;
+
+	printf("Starting I2C Test\n"
+		"Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n"
+		"Please press any key to start\n\n");
+	getc();
+
+	temp = 0xf0; /* set io 0-4 as output */
+	i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1);
+
+	printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n"
+		"Press any key to stop\n\n");
+
+	while (!tstc()) {
+		i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1);
+		temp1 = (temp >> 4) & 0x03;
+		temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */
+		temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */
+		temp = temp1;
+		i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1);
+	}
+	getc();
+
+	return 0;
+}
+
+static int do_usb_test(char * const argv[])
+{
+	int i;
+	static int usb_stor_curr_dev = -1; /* current device */
+
+	printf("Starting USB Test\n"
+		"Please insert USB Memmory Stick\n\n"
+		"Please press any key to start\n\n");
+	getc();
+
+	usb_stop();
+	printf("(Re)start USB...\n");
+	i = usb_init();
+#ifdef CONFIG_USB_STORAGE
+		/* try to recognize storage devices immediately */
+		if (i >= 0)
+			usb_stor_curr_dev = usb_stor_scan(1);
+#endif /* CONFIG_USB_STORAGE */
+	if (usb_stor_curr_dev >= 0)
+		printf("Found USB Storage Dev continue with Test...\n");
+	else {
+		printf("No USB Storage Device detected.. Stop Test\n");
+		return 1;
+	}
+
+	usb_stor_info();
+
+	printf("stopping USB..\n");
+	usb_stop();
+
+	return 0;
+}
+
+static int do_led_test(char * const argv[])
+{
+	int i = 0;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	printf("Starting LED Test\n"
+		"Please set Switch S500 all off\n\n"
+		"Please press any key to start\n\n");
+	getc();
+
+	/* configure timer 2-3 for simple GPIO output High */
+	gpt->gpt2.emsr |= 0x00000034;
+	gpt->gpt3.emsr |= 0x00000034;
+
+	(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
+	(*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
+	printf("Please press any key to stop\n\n");
+	while (!tstc()) {
+		if (i == 1) {
+			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
+			gpt->gpt2.emsr &= ~0x00000010;
+			gpt->gpt3.emsr &= ~0x00000010;
+		} else if (i == 2) {
+			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
+			gpt->gpt2.emsr &= ~0x00000010;
+			gpt->gpt3.emsr |= 0x00000010;
+		} else if (i >= 3) {
+			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
+			gpt->gpt3.emsr &= ~0x00000010;
+			gpt->gpt2.emsr |= 0x00000010;
+			i = 0;
+		}
+		i++;
+		udelay(200000);
+	}
+	getc();
+
+	(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
+	gpt->gpt2.emsr |= 0x00000010;
+	gpt->gpt3.emsr |= 0x00000010;
+
+	return 0;
+}
+
+static int do_rs232_test(char * const argv[])
+{
+	int error_status = 0;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	/* Configure PSC 2-3-6 as GPIO */
+	gpio->port_config &= 0xFF0FF80F;
+
+	switch (simple_strtoul(argv[2], NULL, 10)) {
+	case 1:
+		/* check RTS <-> CTS loop */
+		/* set rts to 0 */
+		printf("Uart 1 test: RX TX tested by using U-Boot\n"
+			"Please connect RTS with CTS on Uart1 plug\n\n"
+			"Press any key to start\n\n");
+		getc();
+
+		psc1->op1 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 0) {
+			error_status = 3;
+			printf("%s: failure at rs232_1, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		/* set rts to 1 */
+		psc1->op0 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 1) {
+			error_status = 3;
+			printf("%s: failure at rs232_1, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+		break;
+	case 2:
+		/* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
+		printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
+			"\nPress any key to start\n\n");
+		getc();
+
+		gpio->simple_gpioe &= ~(0x000000F0);
+		gpio->simple_gpioe |= 0x000000F0;
+		gpio->simple_ddr &= ~(0x000000F0);
+		gpio->simple_ddr |= 0x00000050;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |= (1 << 4);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
+			error_status = 2;
+			printf("%s: failure at rs232_2, rxd status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000020) >> 5);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 4);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_2, rxd status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000020) >> 5);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |= (1 << 6);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
+			error_status = 3;
+			printf("%s: failure at rs232_2, cts status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000080) >> 7);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 6);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_2, cts status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000080) >> 7);
+		}
+		break;
+	case 3:
+		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+		printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
+			"\nPress any key to start\n\n");
+		getc();
+
+		gpio->simple_gpioe &= ~(0x00000F00);
+		gpio->simple_gpioe |= 0x00000F00;
+
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |= 0x00000500;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |= (1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+			error_status = 2;
+			printf("%s: failure at rs232_3, rxd status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_3, rxd status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |= (1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+			error_status = 3;
+			printf("%s: failure at rs232_3, cts status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_3, cts status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+		break;
+	case 4:
+		/* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
+		printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
+			"\nPress any key to start\n\n");
+		getc();
+
+		gpio->simple_gpioe &= ~(0xF0000000);
+		gpio->simple_gpioe |= 0x30000000;
+
+		gpio->simple_ddr &= ~(0xf0000000);
+		gpio->simple_ddr |= 0x30000000;
+
+		(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
+		(*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |= (1 << 28);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
+				0x10000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_4, rxd status is %lu "
+				"(should be 1)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x10000000) >> 28);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 28);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
+				0x00000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_4, rxd status is %lu "
+				"(should be 0)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x10000000) >> 28);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |= (1 << 29);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
+				0x20000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_4, cts status is %lu "
+				"(should be 1)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x20000000) >> 29);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 29);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
+				0x00000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_4, cts status is %lu "
+				"(should be 0)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x20000000) >> 29);
+		}
+		break;
+	default:
+		printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+		error_status = 1;
+		break;
+	}
+	gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
+
+	return error_status;
+}
+
+static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = -1;
+
+	switch (argc) {
+	case 2:
+		if (strncmp(argv[1], "i2c", 3) == 0)
+			rcode = do_i2c_test(argv);
+		else if (strncmp(argv[1], "led", 3) == 0)
+			rcode = do_led_test(argv);
+		else if (strncmp(argv[1], "usb", 3) == 0)
+			rcode = do_usb_test(argv);
+		break;
+	case 3:
+		if (strncmp(argv[1], "rs232", 3) == 0)
+			rcode = do_rs232_test(argv);
+		break;
+	}
+
+	switch (rcode) {
+	case -1:
+		printf("Usage:\n"
+			"fkt { i2c | led | usb }\n"
+			"fkt rs232 number\n");
+		rcode = 1;
+		break;
+	case 0:
+		printf("Test passed\n");
+		break;
+	default:
+		printf("Test failed with code: %d\n", rcode);
+	}
+
+	return rcode;
+}
+
+U_BOOT_CMD(
+	fkt,	4,	1,	cmd_fkt,
+	"Function test routines",
+	"i2c\n"
+	"     - Test I2C communication\n"
+	"fkt led\n"
+	"     - Test LEDs\n"
+	"fkt rs232 number\n"
+	"     - Test RS232 (loopback plug(s) for RS232 required)\n"
+	"fkt usb\n"
+	"     - Test USB communication"
+);
+#endif /* CONFIG_CMD_BSP */
diff --git a/u-boot/board/cm5200/fwupdate.c b/u-boot/board/cm5200/fwupdate.c
new file mode 100644
index 0000000..9d4eadc
--- /dev/null
+++ b/u-boot/board/cm5200/fwupdate.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2007 Schindler Lift Inc.
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Michel Marti <mma@objectxp.com>
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
+ *   - code clean-up
+ *   - bugfix for overwriting bootargs by user
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <usb.h>
+#include <fat.h>
+
+#include "fwupdate.h"
+
+extern long do_fat_read(const char *, void *, unsigned long, int);
+extern int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
+
+static int load_rescue_image(ulong);
+
+void cm5200_fwupdate(void)
+{
+	cmd_tbl_t *bcmd;
+	char *rsargs;
+	char *tmp = NULL;
+	char ka[16];
+	char * const argv[3] = { "bootm", ka, NULL };
+
+	/* Check if rescue system is disabled... */
+	if (getenv("norescue")) {
+		printf(LOG_PREFIX "Rescue System disabled.\n");
+		return;
+	}
+
+	/* Check if we have a USB storage device and load image */
+	if (load_rescue_image(LOAD_ADDR))
+		return;
+
+	bcmd = find_cmd("bootm");
+	if (!bcmd)
+		return;
+
+	sprintf(ka, "%lx", (ulong)LOAD_ADDR);
+
+	/* prepare our bootargs */
+	rsargs = getenv("rs-args");
+	if (!rsargs)
+		rsargs = RS_BOOTARGS;
+	else {
+		tmp = malloc(strlen(rsargs+1));
+		if (!tmp) {
+			printf(LOG_PREFIX "Memory allocation failed\n");
+			return;
+		}
+		strcpy(tmp, rsargs);
+		rsargs = tmp;
+	}
+
+	setenv("bootargs", rsargs);
+
+	if (rsargs == tmp)
+		free(rsargs);
+
+	printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
+	do_bootm(bcmd, 0, 2, argv);
+}
+
+static int load_rescue_image(ulong addr)
+{
+	disk_partition_t info;
+	int devno;
+	int partno;
+	int i;
+	char fwdir[64];
+	char nxri[128];
+	char *tmp;
+	char dev[7];
+	char addr_str[16];
+	char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
+	block_dev_desc_t *stor_dev = NULL;
+	cmd_tbl_t *bcmd;
+
+	/* Get name of firmware directory */
+	tmp = getenv("fw-dir");
+
+	/* Copy it into fwdir */
+	strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
+	fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
+
+	printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
+		" storage...\n", fwdir);
+	usb_stop();
+	if (usb_init() != 0)
+		return 1;
+
+	/* Check for storage device */
+	if (usb_stor_scan(1) != 0) {
+		usb_stop();
+		return 1;
+	}
+
+	/* Detect storage device */
+	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
+		stor_dev = usb_stor_get_dev(devno);
+		if (stor_dev->type != DEV_TYPE_UNKNOWN)
+			break;
+	}
+	if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
+		printf(LOG_PREFIX "No valid storage device found...\n");
+		usb_stop();
+		return 1;
+	}
+
+	/* Detect partition */
+	for (partno = -1, i = 0; i < 6; i++) {
+		if (get_partition_info(stor_dev, i, &info) == 0) {
+			if (fat_register_device(stor_dev, i) == 0) {
+				/* Check if rescue image is present */
+				FW_DEBUG("Looking for firmware directory '%s'"
+					" on partition %d\n", fwdir, i);
+				if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) {
+					FW_DEBUG("No NX rescue image on "
+						"partition %d.\n", i);
+					partno = -2;
+				} else {
+					partno = i;
+					FW_DEBUG("Partition %d contains "
+						"firmware directory\n", partno);
+					break;
+				}
+			}
+		}
+	}
+
+	if (partno < 0) {
+		switch (partno) {
+		case -1:
+			printf(LOG_PREFIX "Error: No valid (FAT) partition "
+				"detected\n");
+			break;
+		case -2:
+			printf(LOG_PREFIX "Error: No NX rescue image on FAT "
+				"partition\n");
+			break;
+		default:
+			printf(LOG_PREFIX "Error: Failed with code %d\n",
+				partno);
+		}
+		usb_stop();
+		return 1;
+	}
+
+	/* Load the rescue image */
+	bcmd = find_cmd("fatload");
+	if (!bcmd) {
+		printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
+		usb_stop();
+		return 1;
+	}
+
+	tmp = getenv("nx-rescue-image");
+	sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
+	sprintf(dev, "%d:%d", devno, partno);
+	sprintf(addr_str, "%lx", addr);
+
+	FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
+		dev, addr_str, nxri);
+
+	if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
+		usb_stop();
+		return 1;
+	}
+
+	/* Stop USB */
+	usb_stop();
+	return 0;
+}
diff --git a/u-boot/board/cm5200/fwupdate.h b/u-boot/board/cm5200/fwupdate.h
new file mode 100644
index 0000000..3bbcbdc
--- /dev/null
+++ b/u-boot/board/cm5200/fwupdate.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007 Schindler Lift Inc.
+ *
+ * Author: Michel Marti <mma@objectxp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FW_UPDATE_H
+#define __FW_UPDATE_H
+
+/* Default prefix for output messages */
+#define LOG_PREFIX	"CM5200:"
+
+/* Extra debug macro */
+#ifdef CONFIG_FWUPDATE_DEBUG
+#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
+#else
+#define FW_DEBUG(fmt...)
+#endif
+
+/* Name of the directory holding firmware images */
+#define FW_DIR		"nx-fw"
+#define RESCUE_IMAGE	"nxrs.img"
+#define LOAD_ADDR	0x400000
+#define RS_BOOTARGS	"ramdisk_size=8192K"
+
+/* Main function for fwupdate */
+void cm5200_fwupdate(void);
+
+#endif /* __FW_UPDATE_H */
diff --git a/u-boot/board/cm5200/u-boot.lds b/u-boot/board/cm5200/u-boot.lds
new file mode 100644
index 0000000..2d8492e
--- /dev/null
+++ b/u-boot/board/cm5200/u-boot.lds
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.got1)
+    . = ALIGN(16);
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/cm_t35/Makefile b/u-boot/board/cm_t35/Makefile
new file mode 100644
index 0000000..862b8dc
--- /dev/null
+++ b/u-boot/board/cm_t35/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cm_t35.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/cm_t35/cm_t35.c b/u-boot/board/cm_t35/cm_t35.c
new file mode 100644
index 0000000..459df0b
--- /dev/null
+++ b/u-boot/board/cm_t35/cm_t35.c
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2010
+ * CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Derived from omap3evm and Beagle Board by
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <net.h>
+#include <i2c.h>
+#include <twl4030.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"CM-T35 board",
+	"NAND",
+};
+
+static u32 gpmc_net_config[GPMC_MAX_REG] = {
+	NET_GPMC_CONFIG1,
+	NET_GPMC_CONFIG2,
+	NET_GPMC_CONFIG3,
+	NET_GPMC_CONFIG4,
+	NET_GPMC_CONFIG5,
+	NET_GPMC_CONFIG6,
+	0
+};
+
+static u32 gpmc_nand_config[GPMC_MAX_REG] = {
+	SMNAND_GPMC_CONFIG1,
+	SMNAND_GPMC_CONFIG2,
+	SMNAND_GPMC_CONFIG3,
+	SMNAND_GPMC_CONFIG4,
+	SMNAND_GPMC_CONFIG5,
+	SMNAND_GPMC_CONFIG6,
+	0,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
+			      CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
+
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init I2C and display die ID
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	/* SDRC */
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)); /*SDRC_D0*/
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)); /*SDRC_D1*/
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)); /*SDRC_D2*/
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)); /*SDRC_D3*/
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)); /*SDRC_D4*/
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)); /*SDRC_D5*/
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)); /*SDRC_D6*/
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)); /*SDRC_D7*/
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)); /*SDRC_D8*/
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)); /*SDRC_D9*/
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)); /*SDRC_D10*/
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)); /*SDRC_D11*/
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)); /*SDRC_D12*/
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)); /*SDRC_D13*/
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)); /*SDRC_D14*/
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)); /*SDRC_D15*/
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)); /*SDRC_D16*/
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)); /*SDRC_D17*/
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)); /*SDRC_D18*/
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)); /*SDRC_D19*/
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)); /*SDRC_D20*/
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)); /*SDRC_D21*/
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)); /*SDRC_D22*/
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)); /*SDRC_D23*/
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)); /*SDRC_D24*/
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)); /*SDRC_D25*/
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)); /*SDRC_D26*/
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)); /*SDRC_D27*/
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)); /*SDRC_D28*/
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)); /*SDRC_D29*/
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)); /*SDRC_D30*/
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)); /*SDRC_D31*/
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)); /*GPMC_A1*/
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)); /*GPMC_A2*/
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)); /*GPMC_A3*/
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)); /*GPMC_A4*/
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)); /*GPMC_A5*/
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)); /*GPMC_A6*/
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)); /*GPMC_A7*/
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)); /*GPMC_A8*/
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)); /*GPMC_A9*/
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)); /*GPMC_A10*/
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)); /*GPMC_D0*/
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)); /*GPMC_D1*/
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)); /*GPMC_D2*/
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)); /*GPMC_D3*/
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)); /*GPMC_D4*/
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)); /*GPMC_D5*/
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)); /*GPMC_D6*/
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)); /*GPMC_D7*/
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)); /*GPMC_D8*/
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)); /*GPMC_D9*/
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)); /*GPMC_D10*/
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)); /*GPMC_D11*/
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)); /*GPMC_D12*/
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)); /*GPMC_D13*/
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)); /*GPMC_D14*/
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)); /*GPMC_D15*/
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/
+
+	/* SB-T35 Ethernet */
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/
+
+	/* CM-T35 Ethernet */
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
+	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTD | DIS | M4)); /*GPIO_59*/
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)); /*nADV_ALE*/
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)); /*nOE*/
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)); /*nWE*/
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)); /*nBE0_CLE*/
+	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTD | DIS | M4)); /*GPIO_61*/
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)); /*nWP*/
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)); /*WAIT0*/
+
+	/* DSS */
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
+
+	/* serial interface */
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)); /*UART3_RX*/
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)); /*UART3_TX*/
+
+	/* mUSB */
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)); /*HSUSB0_CLK*/
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)); /*HSUSB0_STP*/
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)); /*HSUSB0_DIR*/
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)); /*HSUSB0_NXT*/
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA0*/
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA1*/
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA2*/
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA3*/
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA4*/
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA5*/
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA6*/
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA7*/
+
+	/* I2C1 */
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)); /*I2C1_SDA*/
+
+	/* control and debug */
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)); /*SYS_32K*/
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)); /*SYS_CLKREQ*/
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)); /*SYS_nIRQ*/
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)); /*OFF_MODE*/
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)); /*CLKOUT1*/
+	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTD | DIS | M4)); /*green LED*/
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: setup_net_chip_gmpc
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip_gmpc(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
+			      CM_T35_SMC911X_BASE, GPMC_SIZE_16M);
+	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
+			      SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+/*
+ * Routine: reset_net_chip
+ * Description: reset the Ethernet controller via TPS65930 GPIO
+ */
+static void reset_net_chip(void)
+{
+	/* Set GPIO1 of TPS65930 as output */
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+			     TWL4030_BASEADD_GPIO+0x03);
+	/* Send a pulse on the GPIO pin */
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+			     TWL4030_BASEADD_GPIO+0x0C);
+	udelay(1);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+			     TWL4030_BASEADD_GPIO+0x09);
+	udelay(1);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+			     TWL4030_BASEADD_GPIO+0x0C);
+}
+#else
+static inline void reset_net_chip(void) {}
+#endif
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	int rc;
+
+	rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (rc)
+		return 0;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	rc = i2c_read(0x50, 0, 1, enetaddr, 6);
+	if (rc)
+		return rc;
+#endif
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0, rc1 = 0;
+
+#ifdef CONFIG_SMC911X
+	setup_net_chip_gmpc();
+	reset_net_chip();
+
+	rc1 = handle_mac_address();
+	if (rc1)
+		printf("CM-T35: No MAC address found\n");
+
+	rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE);
+	if (rc1 > 0)
+		rc++;
+
+	rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+	if (rc1 > 0)
+		rc++;
+#endif
+
+	return rc;
+}
diff --git a/u-boot/board/cmc_pu2/Makefile b/u-boot/board/cmc_pu2/Makefile
new file mode 100644
index 0000000..a60f2e9
--- /dev/null
+++ b/u-boot/board/cmc_pu2/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cmc_pu2.o flash.o load_sernum_ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cmc_pu2/cmc_pu2.c b/u-boot/board/cmc_pu2/cmc_pu2.c
new file mode 100644
index 0000000..0ac851c
--- /dev/null
+++ b/u-boot/board/cmc_pu2/cmc_pu2.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
+ * (2004) garyj@denx.de
+ *
+ * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mach-types.h>
+#include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+#include <netdev.h>
+#if defined(CONFIG_DRIVER_ETHER)
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#define CMC_HP_BASIC	1
+#define CMC_PU2		2
+#define CMC_BASIC	4
+
+int hw_detect (void);
+
+int board_init (void)
+{
+	AT91PS_PIO piob = AT91C_BASE_PIOB;
+	AT91PS_PIO pioc = AT91C_BASE_PIOC;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	/* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	/*
+	 * configure PC0-PC3 as input without pull ups, so RS485 driver enable
+	 * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated.
+	 */
+	pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+
+	/*
+	 * On CMC-PU2 board configure PB3-PB6 to input without pull ups to
+	 * clear the duo LEDs (the external pull downs assure a proper
+	 * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and
+	 * drive it high, to configure current measurement on AINx.
+	 */
+	if (hw_detect() & CMC_PU2) {
+		piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) {
+		piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+		piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+
+	/*
+	 * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in
+	 * the linuxarm kernel, yet.
+	 */
+	/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
+	gd->bd->bi_arch_number = 251;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+int checkboard (void)
+{
+	if (hw_detect() & CMC_PU2)
+		puts ("Board: CMC-PU2 (Rittal GmbH)\n");
+	else if (hw_detect() & CMC_BASIC)
+		puts ("Board: CMC-BASIC (Rittal GmbH)\n");
+	else if (hw_detect() & CMC_HP_BASIC)
+		puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n");
+	else
+		puts ("Board: unknown\n");
+	return 0;
+}
+
+int hw_detect (void)
+{
+	AT91PS_PIO pio = AT91C_BASE_PIOB;
+
+	/* PIOB clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+
+	/* configure PB12 as input without pull up */
+	pio->PIO_ODR = AT91C_PIO_PB12;
+	pio->PIO_PPUDR = AT91C_PIO_PB12;
+	pio->PIO_PER = AT91C_PIO_PB12;
+
+	/* configure PB13 as input without pull up */
+	pio->PIO_ODR = AT91C_PIO_PB13;
+	pio->PIO_PPUDR = AT91C_PIO_PB13;
+	pio->PIO_PER = AT91C_PIO_PB13;
+
+	/* read board identification pin */
+	if (pio->PIO_PDSR & AT91C_PIO_PB12)
+		return ((pio->PIO_PDSR & AT91C_PIO_PB13)
+			? CMC_PU2 : 0);
+	else
+		return ((pio->PIO_PDSR & AT91C_PIO_PB13)
+			? CMC_HP_BASIC : CMC_BASIC);
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif
+#endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/u-boot/board/cmc_pu2/config.mk b/u-boot/board/cmc_pu2/config.mk
new file mode 100644
index 0000000..cdb8a5f
--- /dev/null
+++ b/u-boot/board/cmc_pu2/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE = 0x20F00000
+## For testing: load at 0x20100000 and "go" at 0x201000A4
+#CONFIG_SYS_TEXT_BASE = 0x20100000
diff --git a/u-boot/board/cmc_pu2/flash.c b/u-boot/board/cmc_pu2/flash.c
new file mode 100644
index 0000000..d832e62
--- /dev/null
+++ b/u-boot/board/cmc_pu2/flash.c
@@ -0,0 +1,468 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
+ * garyj@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02AA
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_short *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+	/* Init: no FLASHes known */
+	memset(&flash_info[0], 0, sizeof(flash_info_t));
+
+	flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]);
+
+	size = flash_info[0].size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	vu_short *base = (vu_short *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = 0x00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = 0x00F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	info = NULL;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_S29GL064M:
+		printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	int i;
+	ushort value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command sequence */
+	addr[FLASH_CYCLE1] = 0x00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = 0x0055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = 0x0090;	/* selects Intel or AMD */
+
+	/* read Manufacturer ID */
+	udelay(100);
+	value = addr[0];
+	debug ("Manufacturer ID: %04X\n", value);
+
+	switch (value) {
+
+	case (AMD_MANUFACT & 0xFFFF):
+		debug ("Manufacturer: AMD (Spansion)\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (INTEL_MANUFACT & 0xFFFF):
+		debug ("Manufacturer: Intel (not supported yet)\n");
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		printf ("Unknown Manufacturer ID: %04X\n", value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		goto out;
+	}
+
+	value = addr[1];
+	debug ("Device ID: %04X\n", value);
+
+	switch (addr[1]) {
+
+	case (AMD_ID_MIRROR & 0xFFFF):
+		debug ("Mirror Bit flash: addr[14] = %08X  addr[15] = %08X\n",
+			addr[14], addr[15]);
+
+		switch(addr[14]) {
+		case (AMD_ID_GL064M_2 & 0xFFFF):
+			if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
+				printf ("Chip: S29GLxxxM -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+				info->sector_count = 0;
+				info->size = 0;
+			} else {
+				debug ("Chip: S29GL064M-R6\n");
+				info->flash_id += FLASH_S29GL064M;
+				info->sector_count = 128;
+				info->size = 0x00800000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] = base;
+					base += 0x10000;
+				}
+			}
+			break;	/* => 16 MB	*/
+		default:
+			printf ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+		}
+		break;
+
+	default:
+		printf ("Unknown Device ID: %04X\n", value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+out:
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short *)(info->start[0]);
+	int flag, prot, sect, ssect, l_sect;
+	ulong now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/*
+	 * Start erase on unprotected sectors.
+	 * Since the flash can erase multiple sectors with one command
+	 * we take advantage of that by doing the erase in chunks of
+	 * 3 sectors.
+	 */
+	for (sect = s_first; sect <= s_last; ) {
+		l_sect = -1;
+
+		addr[FLASH_CYCLE1] = 0x00AA;
+		addr[FLASH_CYCLE2] = 0x0055;
+		addr[FLASH_CYCLE1] = 0x0080;
+		addr[FLASH_CYCLE1] = 0x00AA;
+		addr[FLASH_CYCLE2] = 0x0055;
+
+		/* do the erase in chunks of at most 3 sectors */
+		for (ssect = 0; ssect < 3; ssect++) {
+			if ((sect + ssect) > s_last)
+				break;
+			if (info->protect[sect + ssect] == 0) {	/* not protected */
+				addr = (vu_short *)(info->start[sect + ssect]);
+				addr[0] = 0x0030;
+				l_sect = sect + ssect;
+			}
+		}
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		reset_timer_masked ();
+		last  = 0;
+		addr = (vu_short *)(info->start[l_sect]);
+		while ((addr[0] & 0x0080) != 0x0080) {
+			if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		addr = (vu_short *)info->start[0];
+		addr[0] = 0x00F0;	/* reset bank */
+		sect += ssect;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short *)info->start[0];
+	addr[0] = 0x00F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	};
+
+	if ((int) src & 1) {
+		printf ("unaligned source not supported\n");
+		return ERR_ALIGN;
+	};
+
+	wp = addr;
+
+	while (cnt >= 2) {
+		data = *((vu_short *)src);
+		if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
+printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (ERR_OK);
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8);
+		if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
+printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data)
+{
+	int flag;
+	vu_short *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (vu_short *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+	base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+	base[FLASH_CYCLE1] = 0x00A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	reset_timer_masked ();
+
+	/* data polling for D7 */
+	while ((*dest & 0x0080) != (data & 0x0080)) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = 0x00F0;	/* reset bank */
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/cmc_pu2/load_sernum_ethaddr.c b/u-boot/board/cmc_pu2/load_sernum_ethaddr.c
new file mode 100644
index 0000000..6f85dd9
--- /dev/null
+++ b/u-boot/board/cmc_pu2/load_sernum_ethaddr.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <net.h>
+
+#define I2C_CHIP	0x50	/* I2C bus address of onboard EEPROM */
+#define I2C_ALEN	1	/* length of EEPROM addresses in bytes */
+#define I2C_OFFSET	0x0	/* start address of manufacturere data block
+				 * in EEPROM */
+
+/* 64 Byte manufacturer data block in EEPROM */
+struct manufacturer_data {
+	unsigned int	serial_number;	/* serial number (0...999999) */
+	unsigned short	hardware;	/* hardware version (e.g. V1.02) */
+	unsigned short	manuf_date;	/* manufacture date (e.g. 25/02) */
+	unsigned char	name[20];	/* device name (in CHIP.INI) */
+	unsigned char	macadr[6];	/* MAC address */
+	signed char	a_kal[4];	/* calibration value for U */
+	signed char	i_kal[4];	/* calibration value for I */
+	unsigned char	reserve[18];	/* reserved */
+	unsigned short	save_nr;	/* save count */
+	unsigned short	chksum;		/* checksum */
+};
+
+
+int i2c_read (unsigned char chip, unsigned int addr, int alen,
+	      unsigned char *buffer, int len);
+
+/*-----------------------------------------------------------------------
+ * Process manufacturer data block in EEPROM:
+ *
+ * If we boot on a system fresh from factory, check if the manufacturer data
+ * in the EEPROM is valid and save some information it contains.
+ *
+ * CMC manufacturer data is defined as follows:
+ *
+ * - located in the onboard EEPROM
+ * - starts at offset 0x0
+ * - size 0x00000040
+ *
+ * Internal structure: see struct definition
+ */
+
+int misc_init_r(void)
+{
+	struct manufacturer_data data;
+	char  serial [9];
+	unsigned short chksum;
+	unsigned char *p;
+	unsigned short i;
+
+#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C)
+#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C)
+#endif
+	if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data,
+		     sizeof(data)) != 0) {
+		puts ("Error reading manufacturer data from EEPROM\n");
+		return -1;
+	}
+
+	/* check if manufacturer data block is valid  */
+	p = (unsigned char *)&data;
+	chksum = 0;
+	for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++)
+		chksum += *p++;
+
+	debug ("checksum of manufacturer data block: %#.4x\n", chksum);
+
+	if (chksum != data.chksum) {
+		puts ("Error: manufacturer data block has invalid checksum\n");
+		return -1;
+	}
+
+	/* copy serial number */
+	sprintf (serial, "%d", data.serial_number);
+
+	/* set serial# and ethaddr if not yet defined */
+	if (getenv("serial#") == NULL) {
+		setenv ("serial#", serial);
+	}
+
+	if (getenv("ethaddr") == NULL) {
+		eth_setenv_enetaddr("ethaddr", data.macadr);
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/cmi/Makefile b/u-boot/board/cmi/Makefile
new file mode 100644
index 0000000..c554ce2
--- /dev/null
+++ b/u-boot/board/cmi/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= flash.o cmi.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cmi/cmi.c b/u-boot/board/cmi/cmi.c
new file mode 100644
index 0000000..b78183e
--- /dev/null
+++ b/u-boot/board/cmi/cmi.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * File:		cmi.c
+ *
+ * Discription:		For generic board specific functions
+ *
+ */
+
+
+#include <common.h>
+#include <mpc5xx.h>
+
+#define SRAM_SIZE	1024000L	/* 1M RAM available*/
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+#  define SYM_CHAR "_"
+#else /* No leading character on symbols */
+#  define SYM_CHAR
+#endif
+
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+		asm (".globl " GEN_SYMNAME(name)); \
+		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+/*
+ * Check the board
+ */
+int checkboard(void)
+{
+    puts ("Board: ### No HW ID - assuming CMI board\n");
+    return (0);
+}
+
+/*
+ * Get RAM size.
+ */
+phys_size_t initdram(int board_type)
+{
+	return (SRAM_SIZE);		/* We currently have a static size adapted for cmi board. */
+}
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/u-boot/board/cmi/flash.c b/u-boot/board/cmi/flash.c
new file mode 100644
index 0000000..630c330
--- /dev/null
+++ b/u-boot/board/cmi/flash.c
@@ -0,0 +1,517 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * File:		flash.c
+ *
+ * Discription:		This Driver is for 28F320J3A, 28F640J3A and
+ *			28F128J3A Intel flashs working in 16 Bit mode.
+ *			They are single bank flashs.
+ *
+ *			Most of this code is taken from existing u-boot
+ *			source code.
+ */
+
+
+#include <common.h>
+#include <mpc5xx.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+#define	FLASH_ID_MASK			0xFFFF
+#define FLASH_BLOCK_SIZE		0x00010000
+#define FLASH_CMD_READ_ID		0x0090
+#define FLASH_CMD_RESET			0x00ff
+#define FLASH_CMD_BLOCK_ERASE		0x0020
+#define FLASH_CMD_ERASE_CONFIRM		0x00D0
+#define FLASH_CMD_CLEAR_STATUS		0x0050
+#define FLASH_CMD_SUSPEND_ERASE		0x00B0
+#define FLASH_CMD_WRITE			0x0040
+#define FLASH_CMD_PROTECT		0x0060
+#define FLASH_CMD_PROTECT_SET		0x0001
+#define FLASH_CMD_PROTECT_CLEAR		0x00D0
+#define FLASH_STATUS_DONE		0x0080
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*
+ * Local function prototypes
+ */
+static ulong	flash_get_size		(vu_short *addr, flash_info_t *info);
+static int	write_short		(flash_info_t *info, ulong dest, ushort data);
+static void	flash_get_offsets	(ulong base, flash_info_t *info);
+
+/*
+ * Initialize flash
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+#if 1
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+#endif
+	size_b0 = flash_get_size((vu_short *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	return size_b0;
+}
+
+/*
+ * Compute start adress of each sector (block)
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + i * FLASH_BLOCK_SIZE;
+	    }
+	    return;
+
+	default:
+	    printf ("Don't know sector offsets for flash type 0x%lx\n",
+		info->flash_id);
+	    return;
+	}
+}
+
+/*
+ * Print flash information
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320J3A (32Mbit) 16-Bit\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64Mbit) 16-Bit\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128J3A (128Mbit) 16-Bit\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * Get size of flash in bytes.
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	vu_short value;
+
+	/* Read Manufacturer ID */
+	addr[0] = FLASH_CMD_READ_ID;
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = FLASH_CMD_RESET;	/* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F320J3A  & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* =>  32 MBit		*/
+
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 64 MBit		*/
+
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 128 MBit		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = FLASH_CMD_RESET;	/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = FLASH_CMD_RESET;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*
+ * Erase unprotected sectors
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+#ifdef DEBUG
+			printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+			*addr = FLASH_CMD_CLEAR_STATUS;
+			*addr = FLASH_CMD_BLOCK_ERASE;
+			*addr = FLASH_CMD_ERASE_CONFIRM;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf("Flash erase timeout at address %lx\n", info->start[sect]);
+					*addr = FLASH_CMD_SUSPEND_ERASE;
+					*addr = FLASH_CMD_RESET;
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+			*addr = FLASH_CMD_RESET;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int i, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+
+	while (cnt >= 2) {
+		data = 0;
+		for (i=0; i<2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_short(info, wp, data));
+
+}
+
+/*
+ * Write 16 bit (short) to flash
+ */
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	if (!(info->flash_id & FLASH_VENDMASK)) {
+		return 4;
+	}
+	*addr = FLASH_CMD_ERASE_CONFIRM;
+	*addr = FLASH_CMD_WRITE;
+
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	/* wait for error or finish */
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * Protects a flash sector
+ */
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	vu_short *addr = (vu_short*)(info->start[sector]);
+	ulong start;
+
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
diff --git a/u-boot/board/cobra5272/Makefile b/u-boot/board/cobra5272/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/cobra5272/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cobra5272/bdm/cobra5272_uboot.gdb b/u-boot/board/cobra5272/bdm/cobra5272_uboot.gdb
new file mode 100644
index 0000000..61e778e
--- /dev/null
+++ b/u-boot/board/cobra5272/bdm/cobra5272_uboot.gdb
@@ -0,0 +1,169 @@
+#
+# GDB Init script for the Coldfire 5272 processor.
+#
+# The main purpose of this script is to configure the 
+# DRAM controller so code can be loaded.
+#
+# This file was changed to suite the senTec COBRA5272 board.
+# 
+
+define addresses
+
+set $mbar  = 0x10000001
+set $scr   = $mbar - 1 + 0x004
+set $spr   = $mbar - 1 + 0x006
+set $pmr   = $mbar - 1 + 0x008
+set $apmr  = $mbar - 1 + 0x00e
+set $dir   = $mbar - 1 + 0x010
+set $icr1  = $mbar - 1 + 0x020
+set $icr2  = $mbar - 1 + 0x024
+set $icr3  = $mbar - 1 + 0x028
+set $icr4  = $mbar - 1 + 0x02c
+set $isr   = $mbar - 1 + 0x030
+set $pitr  = $mbar - 1 + 0x034
+set $piwr  = $mbar - 1 + 0x038
+set $pivr  = $mbar - 1 + 0x03f
+set $csbr0 = $mbar - 1 + 0x040
+set $csor0 = $mbar - 1 + 0x044
+set $csbr1 = $mbar - 1 + 0x048
+set $csor1 = $mbar - 1 + 0x04c
+set $csbr2 = $mbar - 1 + 0x050
+set $csor2 = $mbar - 1 + 0x054
+set $csbr3 = $mbar - 1 + 0x058
+set $csor3 = $mbar - 1 + 0x05c
+set $csbr4 = $mbar - 1 + 0x060
+set $csor4 = $mbar - 1 + 0x064
+set $csbr5 = $mbar - 1 + 0x068
+set $csor5 = $mbar - 1 + 0x06c
+set $csbr6 = $mbar - 1 + 0x070
+set $csor6 = $mbar - 1 + 0x074
+set $csbr7 = $mbar - 1 + 0x078
+set $csor7 = $mbar - 1 + 0x07c
+set $pacnt = $mbar - 1 + 0x080
+set $paddr = $mbar - 1 + 0x084
+set $padat = $mbar - 1 + 0x086
+set $pbcnt = $mbar - 1 + 0x088
+set $pbddr = $mbar - 1 + 0x08c
+set $pbdat = $mbar - 1 + 0x08e
+set $pcddr = $mbar - 1 + 0x094
+set $pcdat = $mbar - 1 + 0x096
+set $pdcnt = $mbar - 1 + 0x098
+set $sdcr  = $mbar - 1 + 0x180
+set $sdtr  = $mbar - 1 + 0x184
+set $wrrr  = $mbar - 1 + 0x280
+set $wirr  = $mbar - 1 + 0x283
+set $wcr   = $mbar - 1 + 0x288
+set $wer   = $mbar - 1 + 0x28c
+
+end
+
+
+#
+# Setup system configuration
+#
+define setup-sys
+set *((unsigned short *) $scr) = 0x0003
+set *((unsigned short *) $spr) = 0xffff
+set *((unsigned char *) $pivr) = 0x4f
+end
+
+
+#
+# Setup Chip Selects (as per Motorola M5272C3 board)
+#
+define setup-cs
+
+# CS0 -- FLASH
+set *((unsigned long *) $csbr0) = 0xffe00201
+set *((unsigned long *) $csor0) = 0xffe00014
+
+# CS1 -- external bus test
+set *((unsigned long *) $csbr1) = 0x0
+set *((unsigned long *) $csor1) = 0x0
+
+# CS2 -- Optional FSRAM
+set *((unsigned long *) $csbr2) = 0x30000001
+set *((unsigned long *) $csor2) = 0xfff80000
+
+# CS3 -- not used
+set *((unsigned long *) $csbr3) = 0x0
+set *((unsigned long *) $csor3) = 0x0
+
+# CS4 --  not used
+set *((unsigned long *) $csbr4) = 0x0
+set *((unsigned long *) $csor4) = 0x0
+
+# CS5 -- PLI socket0
+set *((unsigned long *) $csbr5) = 0x0
+set *((unsigned long *) $csor5) = 0x0
+
+# CS6 -- PLI socket1
+set *((unsigned long *) $csbr6) = 0x0
+set *((unsigned long *) $csor6) = 0x0
+
+# CS7 -- SDRAM
+set *((unsigned long *) $csbr7) = 0x00000701
+set *((unsigned long *) $csor7) = 0xff00007c
+
+end
+
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+set *((unsigned long *) $sdtr) = 0x0000f539
+set *((unsigned long *) $sdcr) = 0x00004211
+
+# Dummy write to start SDRAM
+set *((unsigned long *) 0) = 0
+end
+
+
+#
+# Setup for GPIO pins
+#
+define setup-ppio
+
+# PORT A -- the LED's
+set *((unsigned long *) $pacnt) = 0x00000000
+# lower 8 bits for output:
+set *((unsigned short *) $paddr) = 0xff
+# LED's off:
+set *((unsigned short *) $padat) = 0xff
+
+# PORT B
+set *((unsigned long *) $pbcnt) = 0x55554155
+set *((unsigned short *) $pbddr) = 0x0000
+set *((unsigned short *) $pbdat) = 0x17ea
+
+# PORT C
+#set *((unsigned short *) $pcddr) = 0x0000
+#set *((unsigned short *) $pcdat) = 0x1898
+
+# PORT D
+set *((unsigned long *) $pdcnt) = 0x00000000
+
+end
+
+
+#
+#	Added for uClinux-coldfire target...
+#
+target bdm /dev/bdm
+
+addresses
+setup-sys
+setup-cs
+setup-dram
+setup-ppio
+set print pretty
+set print asm-demangle
+display/i $pc
+
+
+#
+load u-boot
+set $pc=0x20000
+c
diff --git a/u-boot/board/cobra5272/bdm/gdbinit.reset b/u-boot/board/cobra5272/bdm/gdbinit.reset
new file mode 100644
index 0000000..5f1e482
--- /dev/null
+++ b/u-boot/board/cobra5272/bdm/gdbinit.reset
@@ -0,0 +1,2 @@
+target bdm /dev/bdmcf0
+q
diff --git a/u-boot/board/cobra5272/bdm/load-cobra_uboot b/u-boot/board/cobra5272/bdm/load-cobra_uboot
new file mode 100644
index 0000000..933c7e7
--- /dev/null
+++ b/u-boot/board/cobra5272/bdm/load-cobra_uboot
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
+
diff --git a/u-boot/board/cobra5272/bdm/reset b/u-boot/board/cobra5272/bdm/reset
new file mode 100644
index 0000000..8bef00b
--- /dev/null
+++ b/u-boot/board/cobra5272/bdm/reset
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
+
diff --git a/u-boot/board/cobra5272/cobra5272.c b/u-boot/board/cobra5272/cobra5272.c
new file mode 100644
index 0000000..a62214c
--- /dev/null
+++ b/u-boot/board/cobra5272/cobra5272.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+
+int checkboard (void)
+{
+	puts ("Board: ");
+	puts ("senTec COBRA5272 Board\n");
+	return 0;
+};
+
+phys_size_t initdram (int board_type)
+{
+	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *) 0) = 0;
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/cobra5272/config.mk b/u-boot/board/cobra5272/config.mk
new file mode 100644
index 0000000..5b8c608
--- /dev/null
+++ b/u-boot/board/cobra5272/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/u-boot/board/cobra5272/flash.c b/u-boot/board/cobra5272/flash.c
new file mode 100644
index 0000000..33c9361
--- /dev/null
+++ b/u-boot/board/cobra5272/flash.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 224 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 10)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x40000 + 0x40000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/u-boot/board/cobra5272/u-boot.lds b/u-boot/board/cobra5272/u-boot.lds
new file mode 100644
index 0000000..ec0f5e9
--- /dev/null
+++ b/u-boot/board/cobra5272/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/cpu/mcf52x2/cpu_init.o	(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/cogent/Makefile b/u-boot/board/cogent/Makefile
new file mode 100644
index 0000000..334f03f
--- /dev/null
+++ b/u-boot/board/cogent/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cogent/README b/u-boot/board/cogent/README
new file mode 100644
index 0000000..4343f73
--- /dev/null
+++ b/u-boot/board/cogent/README
@@ -0,0 +1,118 @@
+Cogent Modular Architecture configuration
+-----------------------------------------
+
+As the name suggests, the Cogent platform is a modular system where
+you have a motherboard into which plugs a cpu module and one or more
+i/o modules. This provides very nice flexibility, but makes the
+configuration task somewhat harder.
+
+The possible Cogent motherboards are:
+
+Code		Config Variable		Description
+----		---------------		-----------
+
+CMA101		CONFIG_CMA101		32MB ram, 2 ser, 1 par, rtc, dipsw,
+					2x16 lcd, eth(?)
+CMA102		CONFIG_CMA102		32MB ram, 2 ser, 1 par, rtc, dipsw,
+					2x16 lcd
+CMA111		CONFIG_CMA111		32MB ram, 1MB flash, 4 ser, 1 par,
+					rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
+					10/100TP eth
+CMA120		CONFIG_CMA120		32MB ram, 1MB flash, 4 ser, 1 par,
+					rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
+					10/100TP eth, 2xPCMCIA, video/lcd-panel
+CMA150		CONFIG_CMA150		8MB ram, 1MB flash, 2 ser, 1 par, rtc,
+					ps/2 kbd/mse, 2x16 lcd
+
+The possible Cogent PowerPC CPU modules are:
+
+Code		Config Variable		Description
+----		---------------		-----------
+
+CMA278-603EV	CONFIG_CMA278_603EV	PPC603ev CPU, 66MHz clock, 512K EPROM,
+					JTAG/COP
+CMA278-603ER	CONFIG_CMA278_603ER	PPC603er CPU, 66MHz clock, 512K EPROM,
+					JTAG/COP
+CMA278-740	CONFIG_CMA278_740	PPC740 CPU, 66MHz clock, 512K EPROM,
+					JTAG/COP
+CMA280-509	CONFIG_CMA280_509	MPC505/509 CPU, 50MHz clock,
+					512K EPROM, BDM
+CMA282		CONFIG_CMA282		MPC8260 CPU, 66MHz clock, 512K EPROM,
+					JTAG, 16M RAM, 1 x ser (SMC2),
+					1 x 10baseT PHY (SCC4), 1 x 10/100 TP
+					PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1)
+CMA285		CONFIG_CMA285		MPC801 CPU, 33MHz clock, 512K EPROM,
+					BDM
+CMA286-21	CONFIG_CMA286_21	MPC821 CPU, 66MHz clock, 512K EPROM,
+					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
+					1 x 10baseT PHY (SCC2)
+CMA286-60-OLD	CONFIG_CMA286_60_OLD	MPC860 CPU, 33MHz clock, 128K EPROM,
+					BDM
+CMA286-60	CONFIG_CMA286_60	MPC860 CPU, 66MHz clock, 512K EPROM,
+					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
+					1 x 10baseT PHY (SCC2)
+CMA286-60P	CONFIG_CMA286_60P	MPC860P CPU, 66MHz clock, 512K EPROM,
+					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
+					1 x 10baseT PHY (SCC2)
+CMA287-23	CONFIG_CMA287_23	MPC823 CPU, 33MHz clock, 512K EPROM,
+					BDM
+CMA287-50	CONFIG_CMA287_50	MPC850 CPU, 33MHz clock, 512K EPROM,
+					BDM
+
+(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs,
+but we'll worry about those later).
+
+The possible Cogent CMA I/O Modules are:
+
+Code		Config Variable		Description
+----		---------------		-----------
+
+CMA302		CONFIG_CMA302		up to 16M flash, ps/2 keyboard/mouse
+CMA352		CONFIG_CMA352		CMAbus <=> PCI
+
+Currently supported:
+
+	Motherboards:	CMA102
+	CPU Modules:	CMA286-60-OLD
+	I/O Modules:	CMA302 I/O module
+
+To configure, perform the usual U-Boot configuration task of editing
+"include/config_cogent_mpc8xx.h" and reviewing all the options and
+settings in there. In particular, check the chip select values
+installed into the memory controller's various option and base
+registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and
+CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
+into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you
+want the serial console on motherboard serial port A or on one of the
+8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
+(NONE means use Cogent motherboard serial port A).
+
+Then edit the file "cogent/config.mk". Firstly, set CONFIG_SYS_TEXT_BASE to be
+the base address of the EPROM for the CPU module. This should be the
+same as the value selected for CONFIG_SYS_MONITOR_BASE in
+"include/config_cogent_*.h" (in fact, I have made this automatic via
+the -CONFIG_SYS_TEXT_BASE=... option in CPPFLAGS).
+
+Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS).
+
+$(CMA_MB) is the name of the directory that contains support for your
+motherboard. At this stage, only "cma10x" exists, which supports the
+CMA101 and CMA102 motherboards - but only selected devices, namely
+serial, lcd and dipsw.
+
+$(CMA_IOMS) is a list of zero or more directories that contain
+support for the i/o modules you have installed. At this stage, only
+"cma302" exists, which supports the CMA302 flash i/o module - but
+only the flash part, not the ps/2 keyboard and mouse interfaces.
+
+There should be a make variable for each of the above directories,
+which is the directory name with "_O" appended. This make variable is
+a list of object files to compile from that directory and include in
+the library.
+
+	e.g. cma10x_O = serial.o ...
+
+That's it. Good Luck.
+
+Murray.Jensen@cmst.csiro.au
+August 31, 2000.
diff --git a/u-boot/board/cogent/README.cma286 b/u-boot/board/cogent/README.cma286
new file mode 100644
index 0000000..0345fea
--- /dev/null
+++ b/u-boot/board/cogent/README.cma286
@@ -0,0 +1,69 @@
+CPU module revisions
+--------------------
+
+My cpu module has the model number "CMA286-60-990526-01". My motherboard
+has the model number "CMA102-32M-990526-01". These are both fairly old,
+and may not reflect current design. In particular, I can see from the
+Cogent web site that the CMA286 has been significantly redesigned - it
+now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports
+(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and
+also the EPROM is 512K.
+
+My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU
+clock is listed as 66MHz, whereas mine is 33.333MHz.
+
+Clocks
+------
+
+Quote from my "CMA286 MPC860/821 User's Manual":
+
+"When setting up the Periodic Interrupt Timer (PIT), be aware that the
+CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed
+a 25MHz clock directly into the MPC860/821. This mode sets the divisor
+for the PIT to be 512. In addition, the Time Base Register (TMB)
+divisor is set to 16."
+
+I interpreted this information to mean that EXTCLK is 25MHz and that at
+power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the
+source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the
+multiplication factor) to 1 (I assume this is what they mean by X1
+mode above). MF=1 means the cpus internal clock runs at the same
+rate as EXTCLK i.e. 25MHz.
+
+Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the
+System Clock and Reset Control register) is set in the cpu initialisation
+code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is
+forced to be 16. This results in TMBCLK=1562500.
+
+One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512,
+PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users
+Manual:
+
+"When used by the real-time clock (RTC), the PITRTCLK source is first
+divided as determined by RTDIV, and then divided in the RTC circuits by
+either 8192 or 9600. Therefore, in order for the RTC to count in
+seconds, the clock source must satisfy:
+
+	(EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1
+
+The RTC will operate with other frequencies, but it will not count in
+units of seconds."
+
+Therefore, the internal RTC of the MPC860 is not going to count in
+seconds, so we must use the motherboard RTC (if we need a RTC).
+
+I presume this means that they do not provide a fixed oscillator for
+OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM,
+RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since
+the CMA286-60 doesn't have this (at least mine doesn't) we can't use
+the code in get_gclk_freq().
+
+Finally, it appears that the internal clock in my CMA286-60 is actually
+33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and
+PITRTCLK=65103.515625 (bloody hell!).
+
+If anyone finds anything wrong with the stuff above, I would appreciate
+an email about it.
+
+Murray Jensen <Murray.Jensen@csiro.au>
+21-Aug-00
diff --git a/u-boot/board/cogent/config.mk b/u-boot/board/cogent/config.mk
new file mode 100644
index 0000000..78730db
--- /dev/null
+++ b/u-boot/board/cogent/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent Modular Architecture
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+
+LDSCRIPT := $(SRCTREE)/board/cogent/u-boot.lds
diff --git a/u-boot/board/cogent/dipsw.c b/u-boot/board/cogent/dipsw.c
new file mode 100644
index 0000000..d2027c9
--- /dev/null
+++ b/u-boot/board/cogent/dipsw.c
@@ -0,0 +1,50 @@
+#include <common.h>
+#include <board/cogent/dipsw.h>
+
+unsigned char
+dipsw_raw(void)
+{
+    return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val);
+}
+
+unsigned char
+dipsw_cooked(void)
+{
+    unsigned char val1, val2, mask1, mask2;
+
+    val1 = dipsw_raw();
+
+    /*
+     * we want to mirror the bits because the low bit is switch 1 and high
+     * bit is switch 8 and also invert them because 1=off and 0=on, according
+     * to manual.
+     *
+     * this makes the value more intuitive i.e.
+     * - left most, or high, or top, bit is left most switch (1);
+     * - right most, or low, or bottom, bit is right most switch (8)
+     * - a set bit means "on" and a clear bit means "off"
+     */
+
+    val2 = 0;
+    for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1)
+	if ((val1 & mask1) == 0)
+	    val2 |= mask2;
+
+    return (val2);
+}
+
+void
+dipsw_init(void)
+{
+    unsigned char val, mask;
+
+    val = dipsw_cooked();
+
+    printf("|");
+    for (mask = 1 << 7; mask > 0; mask >>= 1)
+	if (val & mask)
+	    printf("on |");
+	else
+	    printf("off|");
+    printf("\n");
+}
diff --git a/u-boot/board/cogent/dipsw.h b/u-boot/board/cogent/dipsw.h
new file mode 100644
index 0000000..4f52fd4
--- /dev/null
+++ b/u-boot/board/cogent/dipsw.h
@@ -0,0 +1,3 @@
+extern unsigned char dipsw_raw(void);
+extern unsigned char dipsw_cooked(void);
+extern void dipsw_init(void);
diff --git a/u-boot/board/cogent/flash.c b/u-boot/board/cogent/flash.c
new file mode 100644
index 0000000..e6c85b6
--- /dev/null
+++ b/u-boot/board/cogent/flash.c
@@ -0,0 +1,648 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <board/cogent/flash.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+
+#if defined(CONFIG_CMA302)
+
+/*
+ * probe for the existence of flash at address "addr"
+ * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id
+ */
+static int
+c302f_probe_word(c302f_addr_t addr)
+{
+	/* reset the flash */
+	*addr = C302F_BNK_CMD_RST;
+
+	/* check the manufacturer id */
+	*addr = C302F_BNK_CMD_RD_ID;
+	if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN)
+		return 1;
+
+	/* check the device id */
+	*addr = C302F_BNK_CMD_RD_ID;
+	if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV)
+		return 2;
+
+#ifdef FLASH_DEBUG
+	{
+		int i;
+
+		printf("\nMaster Lock Config = 0x%08lx\n",
+			*C302F_BNK_ADDR_CFGM(addr));
+		for (i = 0; i < C302F_BNK_NBLOCKS; i++)
+			printf("Block %2d Lock Config = 0x%08lx\n",
+				i, *C302F_BNK_ADDR_CFG(i, addr));
+	}
+#endif
+
+	/* reset the flash again */
+	*addr = C302F_BNK_CMD_RST;
+
+	return 0;
+}
+
+/*
+ * probe for Cogent CMA302 flash module at address "base" and store
+ * info for any found into flash_info entry "fip". Must find at least
+ * one bank.
+ */
+static void
+c302f_probe(flash_info_t *fip, c302f_addr_t base)
+{
+	c302f_addr_t addr, eaddr;
+	int nbanks;
+
+	fip->size = 0L;
+	fip->sector_count = 0;
+
+	addr = base;
+	eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS);
+	nbanks = 0;
+
+	while (addr < eaddr) {
+		c302f_addr_t addrw, eaddrw, addrb;
+		int i, osc, nsc;
+
+		addrw = addr;
+		eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
+
+		while (addrw < eaddrw)
+			if (c302f_probe_word(addrw++) != 0)
+				goto out;
+
+		/* bank exists - append info for this bank to *fip */
+		fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5;
+		fip->size += C302F_BNK_SIZE;
+		osc = fip->sector_count;
+		fip->sector_count += C302F_BNK_NBLOCKS;
+		if ((nsc = fip->sector_count) >= CONFIG_SYS_MAX_FLASH_SECT)
+			panic("Too many sectors in flash at address 0x%08lx\n",
+				(unsigned long)base);
+
+		addrb = addr;
+		for (i = osc; i < nsc; i++) {
+			fip->start[i] = (ulong)addrb;
+			fip->protect[i] = 0;
+			addrb = C302F_BNK_ADDR_NEXT_BLK(addrb);
+		}
+
+		addr = C302F_BNK_ADDR_NEXT_BNK(addr);
+		nbanks++;
+	}
+
+out:
+	if (nbanks == 0)
+		panic("ERROR: no flash found at address 0x%08lx\n",
+			(unsigned long)base);
+}
+
+static void
+c302f_reset(flash_info_t *info, int sect)
+{
+	c302f_addr_t addrw, eaddrw;
+
+	addrw = (c302f_addr_t)info->start[sect];
+	eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = C302F_BNK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void
+c302f_erase_init(flash_info_t *info, int sect)
+{
+	c302f_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG);
+	printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1);
+	printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2);
+	printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT);
+	printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST);
+	printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY);
+	printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR);
+#endif
+
+	saddrw = (c302f_addr_t)info->start[sect];
+	eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
+
+#ifdef FLASH_DEBUG
+	printf("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long)saddrw, (unsigned long)eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = C302F_BNK_CMD_ERASE1;
+		*addrw = C302F_BNK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+}
+
+static int
+c302f_erase_poll(flash_info_t *info, int sect)
+{
+	c302f_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (c302f_addr_t)info->start[sect];
+	eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		c302f_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf("  checking status at addr "
+			"0x%08lx [0x%08lx]\n",
+			(unsigned long)addrw, stat);
+#endif
+		if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & C302F_BNK_STAT_ERR) != 0) {
+			printf(" failed on sector %d "
+				"(stat = 0x%08lx) at "
+				"address 0x%08lx\n",
+				sect, stat,
+				(unsigned long)addrw);
+			*addrw = C302F_BNK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+static int
+c302f_write_word(c302f_addr_t addr, c302f_word_t value)
+{
+	c302f_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = C302F_BNK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY);
+
+	if ((stat & C302F_BNK_STAT_ERR) != 0) {
+		printf("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong)stat, (ulong)addr);
+		*addr = C302F_BNK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+done:
+	/* reset to read mode */
+	*addr = C302F_BNK_CMD_RST;
+
+	return (retval);
+}
+
+#endif	/* CONFIG_CMA302 */
+
+unsigned long
+flash_init(void)
+{
+	unsigned long total;
+	int i;
+	flash_info_t *fip;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	fip = &flash_info[0];
+	total = 0L;
+
+#if defined(CONFIG_CMA302)
+	c302f_probe(fip, (c302f_addr_t)CONFIG_SYS_FLASH_BASE);
+	total += fip->size;
+	fip++;
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+	/* not yet ...
+	cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE);
+	total += fip->size;
+	fip++;
+	*/
+#endif
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return total;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F008S5:	printf ("28F008S5\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" %2d - %08lX%s", i,
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+	void (*erase_init)(flash_info_t *, int);
+	int (*erase_poll)(flash_info_t *, int);
+	void (*reset)(flash_info_t *, int);
+	int rcode = 0;
+
+#ifdef FLASH_DEBUG
+	printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info(info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id) {
+
+#if defined(CONFIG_CMA302)
+	case FLASH_MAN_INTEL|FLASH_28F008S5:
+		erase_init = c302f_erase_init;
+		erase_poll = c302f_erase_poll;
+		reset = c302f_reset;
+		break;
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+	case FLASH_MAN_INTEL|FLASH_28F800_B:
+	case FLASH_MAN_AMD|FLASH_AM29F800B:
+		/* not yet ...
+		erase_init = cmbf_erase_init;
+		erase_poll = cmbf_erase_poll;
+		reset = cmbf_reset;
+		break;
+		*/
+#endif
+
+	default:
+		printf ("Flash type %08lx not supported - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sector%s will not be erased!\n",
+			prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			(*erase_init)(info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer(start);
+
+			do {
+				now = get_timer(start);
+
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) { /* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = (*erase_poll)(info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0) {
+		printf (" failed\n");
+	        rcode = 1;
+	}
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			(*reset)(info, sect);
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - write error
+ */
+
+int
+write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	ulong start, now, last;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	start = get_timer (0);
+	last = 0;
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+
+		/* show that we're waiting */
+		now = get_timer(start);
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - write error
+ */
+static int
+write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	int retval;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(ulong *)dest & data) != data) {
+		return (2);
+	}
+
+	switch (info->flash_id) {
+
+#if defined(CONFIG_CMA302)
+	case FLASH_MAN_INTEL|FLASH_28F008S5:
+		retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data);
+		break;
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+	case FLASH_MAN_INTEL|FLASH_28F800_B:
+	case FLASH_MAN_AMD|FLASH_AM29F800B:
+		/* not yet ...
+		retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data);
+		*/
+		retval = 3;
+		break;
+#endif
+
+	default:
+		printf ("Flash type %08lx not supported - aborted\n",
+			info->flash_id);
+		retval = 3;
+		break;
+	}
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/cogent/flash.h b/u-boot/board/cogent/flash.h
new file mode 100644
index 0000000..0b8d6aa
--- /dev/null
+++ b/u-boot/board/cogent/flash.h
@@ -0,0 +1,305 @@
+/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/
+
+/* register addresses, valid only following a I8S5_CMD_RD_ID command */
+#define I8S5_ADDR_MAN	0x00000	/* manufacturer's id */
+#define I8S5_ADDR_DEV	0x00001	/* device id */
+#define I8S5_ADDR_CFGM	0x00003	/* master lock configuration */
+#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */
+
+/* Commands */
+#define I8S5_CMD_RST	0xFF	/* reset flash */
+#define I8S5_CMD_RD_ID	0x90	/* read the id and lock bits */
+#define I8S5_CMD_RD_STAT 0x70	/* read the status register */
+#define I8S5_CMD_CLR_STAT 0x50	/* clear the staus register */
+#define I8S5_CMD_ERASE1	0x20	/* first word for block erase */
+#define I8S5_CMD_ERASE2	0xD0	/* second word for block erase */
+#define I8S5_CMD_PROG	0x40	/* program word command */
+#define I8S5_CMD_LOCK	0x60	/* first word for all lock commands */
+#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */
+#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */
+#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */
+
+/* status register bits */
+#define I8S5_STAT_DPS	0x02	/* Device Protect Status */
+#define I8S5_STAT_PSS	0x04	/* Program Suspend Status */
+#define I8S5_STAT_VPPS	0x08	/* VPP Status */
+#define I8S5_STAT_PSLBS	0x10	/* Program and Set Lock Bit Status */
+#define I8S5_STAT_ECLBS	0x20	/* Erase and Clear Lock Bit Status */
+#define I8S5_STAT_ESS	0x40	/* Erase Suspend Status */
+#define I8S5_STAT_RDY	0x80	/* Write State Machine Status, 1=rdy */
+
+#define I8S5_STAT_ERR	(I8S5_STAT_VPPS | I8S5_STAT_DPS | \
+			    I8S5_STAT_ECLBS | I8S5_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define I8S5_RD_ID_LOCK	0x01	/* Bit 0 of each byte */
+#define I8S5_RD_ID_MAN	0x89	/* Manufacturer code = 0x89 */
+#define I8S5_RD_ID_DEV	0xA6	/* Device code = 0xA6, 28F008S5 */
+
+/* dimensions */
+#define I8S5_NBLOCKS	16		/* a 28F008S5 consists of 16 blocks */
+#define I8S5_BLKSZ	(64*1024)	/* of 64Kbyte each */
+#define I8S5_SIZE	(I8S5_BLKSZ * I8S5_NBLOCKS)
+
+/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/
+
+/* register addresses, valid only following a I8S5_CMD_RD_ID command */
+#define I8B5_ADDR_MAN	0x00000	/* manufacturer's id */
+#define I8B5_ADDR_DEV	0x00001	/* device id */
+
+/* Commands */
+#define I8B5_CMD_RST	0xFF	/* reset flash */
+#define I8B5_CMD_RD_ID	0x90	/* read the id and lock bits */
+#define I8B5_CMD_RD_STAT 0x70	/* read the status register */
+#define I8B5_CMD_CLR_STAT 0x50	/* clear the staus register */
+#define I8B5_CMD_ERASE1	0x20	/* first word for block erase */
+#define I8B5_CMD_ERASE2	0xD0	/* second word for block erase */
+#define I8B5_CMD_PROG	0x40	/* program word command */
+
+/* status register bits */
+#define I8B5_STAT_VPPS	0x08	/* VPP Status */
+#define I8B5_STAT_DWS	0x10	/* Program and Set Lock Bit Status */
+#define I8B5_STAT_ES	0x20	/* Erase and Clear Lock Bit Status */
+#define I8B5_STAT_ESS	0x40	/* Erase Suspend Status */
+#define I8B5_STAT_RDY	0x80	/* Write State Machine Status, 1=rdy */
+
+#define I8B5_STAT_ERR	(I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES)
+
+/* ID Configuration */
+#define I8B5_RD_ID_MAN	0x89	/* Manufacturer code = 0x89 */
+#define I8B5_RD_ID_DEV1	0x889D	/* Device code = 0x889D, 28F800B5 */
+
+/* dimensions */
+#define I8B5_NBLOCKS	8		/* a 28F008S5 consists of 16 blocks */
+#define I8B5_BLKSZ	(128*1024)	/* of 64Kbyte each */
+#define I8B5_SIZE	(I8B5_BLKSZ * I8B5_NBLOCKS)
+
+/****************** DEFINES for Cogent CMA302 Flash **************************/
+
+/*
+ * Quoted from the CMA302 manual:
+ *
+ * Although the CMA302 supports 64-bit reads, all writes must be done with
+ * word size only. When programming the CMA302, the FLASH devices appear as 2
+ * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four
+ * 28F008S5 devices. The first bank is accessed when the word address is even,
+ * while the second bank is accessed when the word address is odd. This must
+ * be taken into account when programming the desired word. Also, when locking
+ * blocks, software must lock both banks. The CMA302 does not directly support
+ * byte writing.  Programming and/or erasing individual bytes is done with
+ * selective use of the Write Command.  By not placing the Write Command value
+ * on a particular byte lane, that byte will not be written with the following
+ * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are
+ * two 28F008S5 devices, one for each bank or every other word.
+ *
+ * End quote.
+ *
+ * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The
+ * chips are arranged on the CMA302 in multiples of two banks, each bank having
+ * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e.
+ * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3)
+ * going to each of the 4 chips and the word address selecting the bank, even
+ * being the low bank and odd the high bank. For 64bit reads, both banks are
+ * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5
+ * consists of 16 64Kbyte "block"s. Before programming a byte, the block that
+ * the byte resides within must be erased. So if you want to program contiguous
+ * memory locations, you must erase all 8 chips at the same time. i.e. the
+ * flash on the CMA302 can be viewed as a number of 512Kbyte blocks.
+ *
+ * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas
+ * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks.
+ */
+
+typedef unsigned long c302f_word_t;	/* 32 or 64 bit unsigned integer */
+typedef volatile c302f_word_t *c302f_addr_t;
+typedef unsigned long c302f_size_t;	/* want this big - at least 32 bit */
+
+/* layout of banks on cma302 board */
+#define C302F_BNK_WIDTH		8	/* each bank is 8 chips wide */
+#define C302F_BNK_WSHIFT	3	/* log base 2 of C302F_BNK_WIDTH */
+#define C302F_BNK_NBLOCKS	I8S5_NBLOCKS
+#define C302F_BNK_BLKSZ		(I8S5_BLKSZ * C302F_BNK_WIDTH)
+#define C302F_BNK_SIZE		(I8S5_SIZE * C302F_BNK_WIDTH)
+
+#define C302F_MAX_BANKS		2	/* up to 2 banks (8M each) on CMA302 */
+
+/* align addresses and sizes to bank boundaries */
+#define C302F_BNK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(C302F_BNK_WIDTH - 1)))
+#define C302F_BNK_SIZE_ALIGN(s)	((c302f_size_t)C302F_BNK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1)))
+
+/* align addresses and sizes to block boundaries */
+#define C302F_BLK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(C302F_BNK_BLKSZ - 1)))
+#define C302F_BLK_SIZE_ALIGN(s)	((c302f_size_t)C302F_BLK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1)))
+
+/* add a byte offset to a flash address */
+#define C302F_ADDR_ADD_BYTEOFF(a,o) \
+				(c302f_addr_t)((c302f_size_t)(a) + (o))
+
+/* get base address of bank b, given flash base address a */
+#define C302F_BNK_ADDR_BASE(a,b) \
+				C302F_ADDR_ADD_BYTEOFF((a), \
+				    (c302f_size_t)(b) * C302F_BNK_SIZE)
+
+/* adjust an address a (within a bank) to next word, block or bank */
+#define C302F_BNK_ADDR_NEXT_WORD(a) \
+				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH)
+#define C302F_BNK_ADDR_NEXT_BLK(a) \
+				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ)
+#define C302F_BNK_ADDR_NEXT_BNK(a) \
+				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define C302F_BNK_ADDR_I8S5REG(a,r) \
+				C302F_ADDR_ADD_BYTEOFF((a), \
+				    (r) << C302F_BNK_WSHIFT)
+
+/* make a bank representation for each chip address */
+
+#define C302F_BNK_ADDR_MAN(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN)
+#define C302F_BNK_ADDR_DEV(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV)
+#define C302F_BNK_ADDR_CFGM(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM)
+#define C302F_BNK_ADDR_CFG(b,a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the c302f_word_t type
+ */
+#define C302F_FILL_WORD(o)	(((unsigned long)(o) << 24) | \
+				    ((unsigned long)(o) << 16) | \
+				    ((unsigned long)(o) << 8) | \
+				    (unsigned long)(o))
+
+/* make a bank representation for each chip cmd/stat/rd value */
+
+/* Commands */
+#define C302F_BNK_CMD_RST	C302F_FILL_WORD(I8S5_CMD_RST)
+#define C302F_BNK_CMD_RD_ID	C302F_FILL_WORD(I8S5_CMD_RD_ID)
+#define C302F_BNK_CMD_RD_STAT	C302F_FILL_WORD(I8S5_CMD_RD_STAT)
+#define C302F_BNK_CMD_CLR_STAT	C302F_FILL_WORD(I8S5_CMD_CLR_STAT)
+#define C302F_BNK_CMD_ERASE1	C302F_FILL_WORD(I8S5_CMD_ERASE1)
+#define C302F_BNK_CMD_ERASE2	C302F_FILL_WORD(I8S5_CMD_ERASE2)
+#define C302F_BNK_CMD_PROG	C302F_FILL_WORD(I8S5_CMD_PROG)
+#define C302F_BNK_CMD_LOCK	C302F_FILL_WORD(I8S5_CMD_LOCK)
+#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK)
+#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR)
+#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define C302F_BNK_STAT_DPS	C302F_FILL_WORD(I8S5_STAT_DPS)
+#define C302F_BNK_STAT_PSS	C302F_FILL_WORD(I8S5_STAT_PSS)
+#define C302F_BNK_STAT_VPPS	C302F_FILL_WORD(I8S5_STAT_VPPS)
+#define C302F_BNK_STAT_PSLBS	C302F_FILL_WORD(I8S5_STAT_PSLBS)
+#define C302F_BNK_STAT_ECLBS	C302F_FILL_WORD(I8S5_STAT_ECLBS)
+#define C302F_BNK_STAT_ESS	C302F_FILL_WORD(I8S5_STAT_ESS)
+#define C302F_BNK_STAT_RDY	C302F_FILL_WORD(I8S5_STAT_RDY)
+
+#define C302F_BNK_STAT_ERR	C302F_FILL_WORD(I8S5_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define C302F_BNK_RD_ID_LOCK	C302F_FILL_WORD(I8S5_RD_ID_LOCK)
+#define C302F_BNK_RD_ID_MAN	C302F_FILL_WORD(I8S5_RD_ID_MAN)
+#define C302F_BNK_RD_ID_DEV	C302F_FILL_WORD(I8S5_RD_ID_DEV)
+
+/*************** DEFINES for Cogent Motherboard Flash ************************/
+
+typedef unsigned short cmbf_word_t;	/* 16 bit unsigned integer */
+typedef volatile cmbf_word_t *cmbf_addr_t;
+typedef unsigned long cmbf_size_t;	/* want this big - at least 32 bit */
+
+/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */
+#define CMBF_BNK_WIDTH		1	/* each bank is one chip wide */
+#define CMBF_BNK_WSHIFT	0	/* log base 2 of CMBF_BNK_WIDTH */
+#define CMBF_BNK_NBLOCKS	I8B5_NBLOCKS
+#define CMBF_BNK_BLKSZ		(I8B5_BLKSZ * CMBF_BNK_WIDTH)
+#define CMBF_BNK_SIZE		(I8B5_SIZE * CMBF_BNK_WIDTH)
+
+#define CMBF_MAX_BANKS		1	/* only 1 x 1Mbyte bank on cogent m/b */
+
+/* align addresses and sizes to bank boundaries */
+#define CMBF_BNK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(CMBF_BNK_WIDTH - 1)))
+#define CMBF_BNK_SIZE_ALIGN(s)	((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1)))
+
+/* align addresses and sizes to block boundaries */
+#define CMBF_BLK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(CMBF_BNK_BLKSZ - 1)))
+#define CMBF_BLK_SIZE_ALIGN(s)	((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1)))
+
+/* add a byte offset to a flash address */
+#define CMBF_ADDR_ADD_BYTEOFF(a,o) \
+				(c302f_addr_t)((c302f_size_t)(a) + (o))
+
+/* get base address of bank b, given flash base address a */
+#define CMBF_BNK_ADDR_BASE(a,b) \
+				CMBF_ADDR_ADD_BYTEOFF((a), \
+				    (c302f_size_t)(b) * CMBF_BNK_SIZE)
+
+/* adjust an address a (within a bank) to next word, block or bank */
+#define CMBF_BNK_ADDR_NEXT_WORD(a) \
+				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH)
+#define CMBF_BNK_ADDR_NEXT_BLK(a) \
+				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ)
+#define CMBF_BNK_ADDR_NEXT_BNK(a) \
+				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define CMBF_BNK_ADDR_I8B5REG(a,r) \
+				CMBF_ADDR_ADD_BYTEOFF((a), \
+				    (r) << CMBF_BNK_WSHIFT)
+
+/* make a bank representation for each chip address */
+
+#define CMBF_BNK_ADDR_MAN(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN)
+#define CMBF_BNK_ADDR_DEV(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV)
+#define CMBF_BNK_ADDR_CFGM(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM)
+#define CMBF_BNK_ADDR_CFG(b,a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the c302f_word_t type
+ */
+#define CMBF_FILL_WORD(o)	(((unsigned long)(o) << 24) | \
+				    ((unsigned long)(o) << 16) | \
+				    ((unsigned long)(o) << 8) | \
+				    (unsigned long)(o))
+
+/* make a bank representation for each chip cmd/stat/rd value */
+
+/* Commands */
+#define CMBF_BNK_CMD_RST	CMBF_FILL_WORD(I8B5_CMD_RST)
+#define CMBF_BNK_CMD_RD_ID	CMBF_FILL_WORD(I8B5_CMD_RD_ID)
+#define CMBF_BNK_CMD_RD_STAT	CMBF_FILL_WORD(I8B5_CMD_RD_STAT)
+#define CMBF_BNK_CMD_CLR_STAT	CMBF_FILL_WORD(I8B5_CMD_CLR_STAT)
+#define CMBF_BNK_CMD_ERASE1	CMBF_FILL_WORD(I8B5_CMD_ERASE1)
+#define CMBF_BNK_CMD_ERASE2	CMBF_FILL_WORD(I8B5_CMD_ERASE2)
+#define CMBF_BNK_CMD_PROG	CMBF_FILL_WORD(I8B5_CMD_PROG)
+#define CMBF_BNK_CMD_LOCK	CMBF_FILL_WORD(I8B5_CMD_LOCK)
+#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK)
+#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR)
+#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define CMBF_BNK_STAT_DPS	CMBF_FILL_WORD(I8B5_STAT_DPS)
+#define CMBF_BNK_STAT_PSS	CMBF_FILL_WORD(I8B5_STAT_PSS)
+#define CMBF_BNK_STAT_VPPS	CMBF_FILL_WORD(I8B5_STAT_VPPS)
+#define CMBF_BNK_STAT_PSLBS	CMBF_FILL_WORD(I8B5_STAT_PSLBS)
+#define CMBF_BNK_STAT_ECLBS	CMBF_FILL_WORD(I8B5_STAT_ECLBS)
+#define CMBF_BNK_STAT_ESS	CMBF_FILL_WORD(I8B5_STAT_ESS)
+#define CMBF_BNK_STAT_RDY	CMBF_FILL_WORD(I8B5_STAT_RDY)
+
+#define CMBF_BNK_STAT_ERR	CMBF_FILL_WORD(I8B5_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define CMBF_BNK_RD_ID_LOCK	CMBF_FILL_WORD(I8B5_RD_ID_LOCK)
+#define CMBF_BNK_RD_ID_MAN	CMBF_FILL_WORD(I8B5_RD_ID_MAN)
+#define CMBF_BNK_RD_ID_DEV	CMBF_FILL_WORD(I8B5_RD_ID_DEV)
diff --git a/u-boot/board/cogent/kbm.c b/u-boot/board/cogent/kbm.c
new file mode 100644
index 0000000..8496402
--- /dev/null
+++ b/u-boot/board/cogent/kbm.c
@@ -0,0 +1,3 @@
+/* keyboard/mouse not implemented yet */
+
+int cma_kbm_not_implemented = 1;
diff --git a/u-boot/board/cogent/kbm.h b/u-boot/board/cogent/kbm.h
new file mode 100644
index 0000000..7eb419c
--- /dev/null
+++ b/u-boot/board/cogent/kbm.h
@@ -0,0 +1,79 @@
+/* keyboard/mouse not implemented yet */
+
+extern int cma_kbm_not_implemented;
+
+/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/
+
+/*
+ * note the auxillary port is used to control the mouse
+ */
+
+/* 8542B Commands (Sent to the Command Port) */
+#define HT8542_CMD_SET_BYTE	0x60	/* Set the command byte */
+#define HT8542_CMD_GET_BYTE	0x20	/* Get the command byte */
+#define HT8542_CMD_KBD_OBUFF	0xD2	/* Write to HT8542 Kbd Output Buffer */
+#define HT8542_CMD_AUX_OBUFF	0xD3	/* Write to HT8542 Mse Output Buffer */
+#define HT8542_CMD_AUX_WRITE	0xD4	/* Write to Mouse Port */
+#define HT8542_CMD_AUX_OFF	0xA7	/* Disable Mouse Port */
+#define HT8542_CMD_AUX_ON	0xA8	/* Re-Enable Mouse Port */
+#define HT8542_CMD_AUX_TEST	0xA9	/* Test for the presence of a Mouse */
+#define HT8542_CMD_DIAG		0xAA	/* Start Diagnostics */
+#define HT8542_CMD_KBD_TEST	0xAB	/* Test for presence of a keyboard */
+#define HT8542_CMD_KBD_OFF	0xAD	/* Disable Kbd Port (use KBD_DAT_ON) */
+#define HT8542_CMD_KBD_ON	0xAE	/* Enable Kbd Port (use KBD_DAT_OFF) */
+
+/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */
+#define HT8542_CMD_BYTE_TRANS	0x40
+#define HT8542_CMD_BYTE_AUX_OFF	0x20	/* 1 = mse port disabled, 0 = enabled */
+#define HT8542_CMD_BYTE_KBD_OFF	0x10	/* 1 = kbd port disabled, 0 = enabled */
+#define HT8542_CMD_BYTE_OVER	0x08	/* 1 = override keyboard lock */
+#define HT8542_CMD_BYTE_RES	0x04	/* reserved */
+#define HT8542_CMD_BYTE_AUX_INT	0x02	/* 1 = enable mouse interrupt */
+#define HT8542_CMD_BYTE_KBD_INT	0x01	/* 1 = enable keyboard interrupt */
+
+/* Keyboard Commands (Sent to the Data Port) */
+#define KBD_CMD_LED		0xED	/* Set Keyboard LEDS with next byte */
+#define KBD_CMD_ECHO		0xEE	/* Echo - we get 0xFA, 0xEE back */
+#define KBD_CMD_MODE		0xF0	/* set scan code mode with next byte */
+#define KBD_CMD_ID		0xF2	/* get keyboard/mouse ID */
+#define KBD_CMD_RPT		0xF3	/* Set Repeat Rate and Delay 2nd Byte */
+#define KBD_CMD_ON		0xF4	/* Enable keyboard */
+#define KBD_CMD_OFF		0xF5	/* Disables Scanning, Resets to Def */
+#define KBD_CMD_DEF		0xF6	/* Reverts kbd to default settings */
+#define KBD_CMD_RST		0xFF	/* Reset - should get 0xFA, 0xAA back */
+
+/* Set LED second bit defines */
+#define KBD_CMD_LED_SCROLL	0x01	/* Set SCROLL LOCK LED on */
+#define KBD_CMD_LED_NUM		0x02	/* Set NUM LOCK LED on */
+#define KBD_CMD_LED_CAPS	0x04	/* Set CAPS LOCK LED on */
+
+/* Set Mode second byte defines */
+#define KBD_CMD_MODE_STAT	0x00	/* get current scan code mode */
+#define KBD_CMD_MODE_SCAN1	0x01	/* set mode to scan code 1 */
+#define KBD_CMD_MODE_SCAN2	0x02	/* set mode to scan code 2 */
+#define KBD_CMD_MODE_SCAN3	0x03	/* set mode to scan code 3 */
+
+/* Keyboard/Mouse ID Codes */
+#define KBD_CMD_ID_1ST		0xAB	/* 1st byte is 0xAB, 2nd is actual ID */
+#define KBD_CMD_ID_KBD		0x83	/* Keyboard */
+#define KBD_CMD_ID_MOUSE	0x00	/* Mouse */
+
+/* Keyboard Data Return Defines */
+#define KBD_STAT_OVER		0x00	/* Buffer Overrun */
+#define KBD_STAT_DIAG_OK	0x55	/* Internal Self Test OK */
+#define KBD_STAT_RST_OK		0xAA	/* Reset Complete */
+#define KBD_STAT_ECHO		0xEE	/* Echo Command Return */
+#define KBD_STAT_BRK		0xF0	/* Prefix for Break Key Code */
+#define KBD_STAT_ACK		0xFA	/* Received after all commands */
+#define KBD_STAT_DIAG_FAIL	0xFD	/* Internal Self Test Failed */
+#define KBD_STAT_RESEND		0xFE	/* Resend Last Command */
+
+/* HT8542B Status Register Bit Defines */
+#define HT8542_STAT_OBF		0x01	/* 1 = output buffer is full */
+#define HT8542_STAT_IBF		0x02	/* 1 = input buffer is full */
+#define HT8542_STAT_SYS		0x04	/* system flag - unused */
+#define HT8542_STAT_CMD		0x08	/* 1 = cmd in input buffer, 0 = data */
+#define HT8542_STAT_INH		0x10	/* 1 = Inhibit - unused */
+#define HT8542_STAT_TX		0x20	/* 1 = Transmit Timeout has occured */
+#define HT8542_STAT_RX		0x40	/* 1 = Receive Timeout has occured */
+#define HT8542_STAT_PERR	0x80	/* 1 = Parity Error from Keyboard */
diff --git a/u-boot/board/cogent/lcd.c b/u-boot/board/cogent/lcd.c
new file mode 100644
index 0000000..76f5ad1
--- /dev/null
+++ b/u-boot/board/cogent/lcd.c
@@ -0,0 +1,245 @@
+/* most of this is taken from the file */
+/* hal/powerpc/cogent/current/src/hal_diag.c in the */
+/* Cygnus eCos source. Here is the copyright notice: */
+/* */
+/*============================================================================= */
+/* */
+/*      hal_diag.c */
+/* */
+/*      HAL diagnostic output code */
+/* */
+/*============================================================================= */
+/*####COPYRIGHTBEGIN#### */
+/* */
+/* ------------------------------------------- */
+/* The contents of this file are subject to the Cygnus eCos Public License */
+/* Version 1.0 (the "License"); you may not use this file except in */
+/* compliance with the License.  You may obtain a copy of the License at */
+/* http://sourceware.cygnus.com/ecos */
+/* */
+/* Software distributed under the License is distributed on an "AS IS" */
+/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the */
+/* License for the specific language governing rights and limitations under */
+/* the License. */
+/* */
+/* The Original Code is eCos - Embedded Cygnus Operating System, released */
+/* September 30, 1998. */
+/* */
+/* The Initial Developer of the Original Code is Cygnus.  Portions created */
+/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved. */
+/* ------------------------------------------- */
+/* */
+/*####COPYRIGHTEND#### */
+/*============================================================================= */
+/*#####DESCRIPTIONBEGIN#### */
+/* */
+/* Author(s):    nickg, jskov */
+/* Contributors: nickg, jskov */
+/* Date:         1999-03-23 */
+/* Purpose:      HAL diagnostic output */
+/* Description:  Implementations of HAL diagnostic output support. */
+/* */
+/*####DESCRIPTIONEND#### */
+/* */
+/*============================================================================= */
+
+/*----------------------------------------------------------------------------- */
+/* Cogent board specific LCD code */
+
+#include <common.h>
+#include <stdarg.h>
+#include <board/cogent/lcd.h>
+
+static char lines[2][LCD_LINE_LENGTH+1];
+static int curline;
+static int linepos;
+static int heartbeat_active;
+/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */
+/* pad to the right with spaces if necessary */
+static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent  ";
+static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000";
+
+static inline unsigned char
+lcd_read_status(cma_mb_lcd *clp)
+{
+    /* read the Busy Status Register */
+    return (cma_mb_reg_read(&clp->lcd_bsr));
+}
+
+static inline void
+lcd_wait_not_busy(cma_mb_lcd *clp)
+{
+    /*
+     * wait for not busy
+     * Note: It seems that the LCD isn't quite ready to process commands
+     * when it clears the BUSY flag. Reading the status address an extra
+     * time seems to give it enough breathing room.
+     */
+
+    while (lcd_read_status(clp) & LCD_STAT_BUSY)
+	;
+
+    (void)lcd_read_status(clp);
+}
+
+static inline void
+lcd_write_command(cma_mb_lcd *clp, unsigned char cmd)
+{
+    lcd_wait_not_busy(clp);
+
+    /* write the Command Register */
+    cma_mb_reg_write(&clp->lcd_cmd, cmd);
+}
+
+static inline void
+lcd_write_data(cma_mb_lcd *clp, unsigned char data)
+{
+    lcd_wait_not_busy(clp);
+
+    /* write the Current Character Register */
+    cma_mb_reg_write(&clp->lcd_ccr, data);
+}
+
+static inline void
+lcd_dis(int addr, char *string)
+{
+    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
+    int pos, linelen;
+
+    linelen = LCD_LINE_LENGTH;
+    if (heartbeat_active && addr == LCD_LINE0)
+	linelen--;
+
+    lcd_write_command(clp, LCD_CMD_ADD + addr);
+    for (pos = 0; *string != '\0' && pos < linelen; pos++)
+	lcd_write_data(clp, *string++);
+}
+
+void
+lcd_init(void)
+{
+    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
+    int i;
+
+    /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */
+    lcd_write_command(clp, LCD_CMD_MODE);
+
+    /* turn the LCD display on */
+    lcd_write_command(clp, LCD_CMD_DON);
+
+    curline = 0;
+    linepos = 0;
+
+    for (i = 0; i < LCD_LINE_LENGTH; i++) {
+	lines[0][i] = init_line0[i];
+	lines[1][i] = init_line1[i];
+    }
+
+    lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0;
+
+    lcd_dis(LCD_LINE0, lines[0]);
+    lcd_dis(LCD_LINE1, lines[1]);
+
+    printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH);
+}
+
+void
+lcd_write_char(const char c)
+{
+    int i, linelen;
+
+    /* ignore CR */
+    if (c == '\r')
+	return;
+
+    linelen = LCD_LINE_LENGTH;
+    if (heartbeat_active && curline == 0)
+	linelen--;
+
+    if (c == '\n') {
+	lcd_dis(LCD_LINE0, &lines[curline^1][0]);
+	lcd_dis(LCD_LINE1, &lines[curline][0]);
+
+	/* Do a line feed */
+	curline ^= 1;
+	linelen = LCD_LINE_LENGTH;
+	if (heartbeat_active && curline == 0)
+	    linelen--;
+	linepos = 0;
+
+	for (i = 0; i < linelen; i++)
+	    lines[curline][i] = ' ';
+
+	return;
+    }
+
+    /* Only allow to be output if there is room on the LCD line */
+    if (linepos < linelen)
+	lines[curline][linepos++] = c;
+}
+
+void
+lcd_flush(void)
+{
+    lcd_dis(LCD_LINE1, &lines[curline][0]);
+}
+
+void
+lcd_write_string(const char *s)
+{
+    char *p;
+
+    for (p = (char *)s; *p != '\0'; p++)
+	lcd_write_char(*p);
+}
+
+void
+lcd_printf(const char *fmt, ...)
+{
+    va_list args;
+    char buf[CONFIG_SYS_PBSIZE];
+
+    va_start(args, fmt);
+    (void)vsprintf(buf, fmt, args);
+    va_end(args);
+
+    lcd_write_string(buf);
+}
+
+void
+lcd_heartbeat(void)
+{
+    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
+#if 0
+    static char rotchars[] = { '|', '/', '-', '\\' };
+#else
+    /* HD44780 Rom Code A00 has no backslash */
+    static char rotchars[] = { '|', '/', '-', '\315' };
+#endif
+    static int rotator_index = 0;
+
+    heartbeat_active = 1;
+
+    /* write the address */
+    lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1));
+
+    /* write the next char in the sequence */
+    lcd_write_data(clp, rotchars[rotator_index]);
+
+    if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
+	rotator_index = 0;
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timestamp)
+{
+#ifdef CONFIG_STATUS_LED
+	if ((timestamp % (CONFIG_SYS_HZ / 2) == 0)
+		lcd_heartbeat ();
+#endif
+}
+
+void show_activity(int arg)
+{
+}
+#endif
diff --git a/u-boot/board/cogent/lcd.h b/u-boot/board/cogent/lcd.h
new file mode 100644
index 0000000..9e6157e
--- /dev/null
+++ b/u-boot/board/cogent/lcd.h
@@ -0,0 +1,84 @@
+/* most of this is taken from the file */
+/* hal/powerpc/cogent/current/src/hal_diag.c in the */
+/* Cygnus eCos source. Here is the copyright notice: */
+/* */
+/*============================================================================= */
+/* */
+/*      hal_diag.c */
+/* */
+/*      HAL diagnostic output code */
+/* */
+/*============================================================================= */
+/*####COPYRIGHTBEGIN#### */
+/* */
+/* ------------------------------------------- */
+/* The contents of this file are subject to the Cygnus eCos Public License */
+/* Version 1.0 (the "License"); you may not use this file except in */
+/* compliance with the License.  You may obtain a copy of the License at */
+/* http://sourceware.cygnus.com/ecos */
+/* */
+/* Software distributed under the License is distributed on an "AS IS" */
+/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the */
+/* License for the specific language governing rights and limitations under */
+/* the License. */
+/* */
+/* The Original Code is eCos - Embedded Cygnus Operating System, released */
+/* September 30, 1998. */
+/* */
+/* The Initial Developer of the Original Code is Cygnus.  Portions created */
+/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved. */
+/* ------------------------------------------- */
+/* */
+/*####COPYRIGHTEND#### */
+/*============================================================================= */
+/*#####DESCRIPTIONBEGIN#### */
+/* */
+/* Author(s):    nickg, jskov */
+/* Contributors: nickg, jskov */
+/* Date:         1999-03-23 */
+/* Purpose:      HAL diagnostic output */
+/* Description:  Implementations of HAL diagnostic output support. */
+/* */
+/*####DESCRIPTIONEND#### */
+/* */
+/*============================================================================= */
+
+/* FEMA 162B 16 character x 2 line LCD */
+
+/* status register bit definitions */
+#define LCD_STAT_BUSY	0x80	/* 1 = display busy */
+#define LCD_STAT_ADD	0x7F	/* bits 0-6 return current display address */
+
+/* command register definitions */
+#define LCD_CMD_RST	0x01	/* clear entire display and reset display addr */
+#define LCD_CMD_HOME	0x02	/* reset display address and reset any shifting */
+#define LCD_CMD_ECL	0x04	/* move cursor left one pos on next data write */
+#define LCD_CMD_ESL	0x05	/* shift display left one pos on next data write */
+#define LCD_CMD_ECR	0x06	/* move cursor right one pos on next data write */
+#define LCD_CMD_ESR	0x07	/* shift disp right one pos on next data write */
+#define LCD_CMD_DOFF	0x08	/* display off, cursor off, blinking off */
+#define LCD_CMD_BL	0x09	/* blink character at current cursor position */
+#define LCD_CMD_CUR	0x0A	/* enable cursor on */
+#define LCD_CMD_DON	0x0C	/* turn display on */
+#define LCD_CMD_CL	0x10	/* move cursor left one position */
+#define LCD_CMD_SL	0x14	/* shift display left one position */
+#define LCD_CMD_CR	0x18	/* move cursor right one position */
+#define LCD_CMD_SR	0x1C	/* shift display right one position */
+#define LCD_CMD_MODE	0x38	/* sets 8 bits, 2 lines, 5x7 characters */
+#define LCD_CMD_ACG	0x40	/* bits 0-5 sets character generator address */
+#define LCD_CMD_ADD	0x80	/* bits 0-6 sets display data addr to line 1 + */
+
+/* LCD status values */
+#define LCD_OK		0x00
+#define LCD_ERR		0x01
+
+#define LCD_LINE0	0x00
+#define LCD_LINE1	0x40
+
+#define LCD_LINE_LENGTH	16
+
+extern void lcd_init(void);
+extern void lcd_write_char(const char);
+extern void lcd_flush(void);
+extern void lcd_write_string(const char *);
+extern void lcd_printf(const char *, ...);
diff --git a/u-boot/board/cogent/mb.c b/u-boot/board/cogent/mb.c
new file mode 100644
index 0000000..619aea3
--- /dev/null
+++ b/u-boot/board/cogent/mb.c
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <board/cogent/dipsw.h>
+#include <board/cogent/lcd.h>
+#include <board/cogent/rtc.h>
+#include <board/cogent/par.h>
+#include <board/cogent/pci.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_8260)
+
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A configuration */
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PA31 */ {0, 0, 0, 0, 0, 0},
+	 /* PA30 */ {0, 0, 0, 0, 0, 0},
+	 /* PA29 */ {0, 0, 0, 0, 0, 0},
+	 /* PA28 */ {0, 0, 0, 0, 0, 0},
+	 /* PA27 */ {0, 0, 0, 0, 0, 0},
+	 /* PA26 */ {0, 0, 0, 0, 0, 0},
+	 /* PA25 */ {0, 0, 0, 0, 0, 0},
+	 /* PA24 */ {0, 0, 0, 0, 0, 0},
+	 /* PA23 */ {0, 0, 0, 0, 0, 0},
+	 /* PA22 */ {0, 0, 0, 0, 0, 0},
+	 /* PA21 */ {0, 0, 0, 0, 0, 0},
+	 /* PA20 */ {0, 0, 0, 0, 0, 0},
+	 /* PA19 */ {0, 0, 0, 0, 0, 0},
+	 /* PA18 */ {0, 0, 0, 0, 0, 0},
+	 /* PA17 */ {0, 0, 0, 0, 0, 0},
+	 /* PA16 */ {0, 0, 0, 0, 0, 0},
+	 /* PA15 */ {0, 0, 0, 0, 0, 0},
+	 /* PA14 */ {0, 0, 0, 0, 0, 0},
+	 /* PA13 */ {0, 0, 0, 0, 0, 0},
+	 /* PA12 */ {0, 0, 0, 0, 0, 0},
+	 /* PA11 */ {0, 0, 0, 0, 0, 0},
+	 /* PA10 */ {0, 0, 0, 0, 0, 0},
+					/* PA9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC2 TXD */
+					/* PA8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC2 RXD */
+	 /* PA7  */ {0, 0, 0, 0, 0, 0},
+	 /* PA6  */ {0, 0, 0, 0, 0, 0},
+	 /* PA5  */ {0, 0, 0, 0, 0, 0},
+	 /* PA4  */ {0, 0, 0, 0, 0, 0},
+	 /* PA3  */ {0, 0, 0, 0, 0, 0},
+	 /* PA2  */ {0, 0, 0, 0, 0, 0},
+	 /* PA1  */ {0, 0, 0, 0, 0, 0},
+	 /* PA0  */ {0, 0, 0, 0, 0, 0}
+	 },
+
+
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PB31 */ {0, 0, 0, 0, 0, 0},
+	 /* PB30 */ {0, 0, 0, 0, 0, 0},
+	 /* PB29 */ {0, 0, 0, 0, 0, 0},
+	 /* PB28 */ {0, 0, 0, 0, 0, 0},
+	 /* PB27 */ {0, 0, 0, 0, 0, 0},
+	 /* PB26 */ {0, 0, 0, 0, 0, 0},
+	 /* PB25 */ {0, 0, 0, 0, 0, 0},
+	 /* PB24 */ {0, 0, 0, 0, 0, 0},
+	 /* PB23 */ {0, 0, 0, 0, 0, 0},
+	 /* PB22 */ {0, 0, 0, 0, 0, 0},
+	 /* PB21 */ {0, 0, 0, 0, 0, 0},
+	 /* PB20 */ {0, 0, 0, 0, 0, 0},
+	 /* PB19 */ {0, 0, 0, 0, 0, 0},
+	 /* PB18 */ {0, 0, 0, 0, 0, 0},
+	 /* PB17 */ {0, 0, 0, 0, 0, 0},
+	 /* PB16 */ {0, 0, 0, 0, 0, 0},
+	 /* PB15 */ {0, 0, 0, 0, 0, 0},
+	 /* PB14 */ {0, 0, 0, 0, 0, 0},
+	 /* PB13 */ {0, 0, 0, 0, 0, 0},
+	 /* PB12 */ {0, 0, 0, 0, 0, 0},
+	 /* PB11 */ {0, 0, 0, 0, 0, 0},
+	 /* PB10 */ {0, 0, 0, 0, 0, 0},
+	 /* PB9  */ {0, 0, 0, 0, 0, 0},
+	 /* PB8  */ {0, 0, 0, 0, 0, 0},
+	 /* PB7  */ {0, 0, 0, 0, 0, 0},
+	 /* PB6  */ {0, 0, 0, 0, 0, 0},
+	 /* PB5  */ {0, 0, 0, 0, 0, 0},
+	 /* PB4  */ {0, 0, 0, 0, 0, 0},
+					/* PB3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 },
+
+
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PC31 */ {0, 0, 0, 0, 0, 0},
+	 /* PC30 */ {0, 0, 0, 0, 0, 0},
+	 /* PC29 */ {0, 0, 0, 0, 0, 0},
+	 /* PC28 */ {0, 0, 0, 0, 0, 0},
+	 /* PC27 */ {0, 0, 0, 0, 0, 0},
+	 /* PC26 */ {0, 0, 0, 0, 0, 0},
+	 /* PC25 */ {0, 0, 0, 0, 0, 0},
+	 /* PC24 */ {0, 0, 0, 0, 0, 0},
+	 /* PC23 */ {0, 0, 0, 0, 0, 0},
+	 /* PC22 */ {0, 0, 0, 0, 0, 0},
+	 /* PC21 */ {0, 0, 0, 0, 0, 0},
+	 /* PC20 */ {0, 0, 0, 0, 0, 0},
+	 /* PC19 */ {0, 0, 0, 0, 0, 0},
+	 /* PC18 */ {0, 0, 0, 0, 0, 0},
+	 /* PC17 */ {0, 0, 0, 0, 0, 0},
+	 /* PC16 */ {0, 0, 0, 0, 0, 0},
+	 /* PC15 */ {0, 0, 0, 0, 0, 0},
+	 /* PC14 */ {0, 0, 0, 0, 0, 0},
+	 /* PC13 */ {0, 0, 0, 0, 0, 0},
+	 /* PC12 */ {0, 0, 0, 0, 0, 0},
+	 /* PC11 */ {0, 0, 0, 0, 0, 0},
+	 /* PC10 */ {0, 0, 0, 0, 0, 0},
+	 /* PC9  */ {0, 0, 0, 0, 0, 0},
+	 /* PC8  */ {0, 0, 0, 0, 0, 0},
+	 /* PC7  */ {0, 0, 0, 0, 0, 0},
+	 /* PC6  */ {0, 0, 0, 0, 0, 0},
+	 /* PC5  */ {0, 0, 0, 0, 0, 0},
+	 /* PC4  */ {0, 0, 0, 0, 0, 0},
+	 /* PC3  */ {0, 0, 0, 0, 0, 0},
+	 /* PC2  */ {0, 0, 0, 0, 0, 0},
+	 /* PC1  */ {0, 0, 0, 0, 0, 0},
+	 /* PC0  */ {0, 0, 0, 0, 0, 0}
+	 },
+
+
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PD31 */ {0, 0, 0, 0, 0, 0},
+	 /* PD30 */ {0, 0, 0, 0, 0, 0},
+	 /* PD29 */ {0, 0, 0, 0, 0, 0},
+	 /* PD28 */ {0, 0, 0, 0, 0, 0},
+	 /* PD27 */ {0, 0, 0, 0, 0, 0},
+	 /* PD26 */ {0, 0, 0, 0, 0, 0},
+	 /* PD25 */ {0, 0, 0, 0, 0, 0},
+	 /* PD24 */ {0, 0, 0, 0, 0, 0},
+	 /* PD23 */ {0, 0, 0, 0, 0, 0},
+	 /* PD22 */ {0, 0, 0, 0, 0, 0},
+	 /* PD21 */ {0, 0, 0, 0, 0, 0},
+	 /* PD20 */ {0, 0, 0, 0, 0, 0},
+	 /* PD19 */ {0, 0, 0, 0, 0, 0},
+	 /* PD18 */ {0, 0, 0, 0, 0, 0},
+	 /* PD17 */ {0, 0, 0, 0, 0, 0},
+	 /* PD16 */ {0, 0, 0, 0, 0, 0},
+					/* PD15 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SDA */
+					/* PD14 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SCL */
+	 /* PD13 */ {0, 0, 0, 0, 0, 0},
+	 /* PD12 */ {0, 0, 0, 0, 0, 0},
+	 /* PD11 */ {0, 0, 0, 0, 0, 0},
+	 /* PD10 */ {0, 0, 0, 0, 0, 0},
+					/* PD9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC1 TXD */
+					/* PD8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC1 RXD */
+	 /* PD7  */ {0, 0, 0, 0, 0, 0},
+	 /* PD6  */ {0, 0, 0, 0, 0, 0},
+	 /* PD5  */ {0, 0, 0, 0, 0, 0},
+	 /* PD4  */ {0, 0, 0, 0, 0, 0},
+					/* PD3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 }
+};
+
+#endif /* CONFIG_8260 */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
+	      COGENT_CPU_MODULE " CPU Module\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations while still
+ * running in flash
+ */
+
+int misc_init_f (void)
+{
+	printf ("DIPSW: ");
+	dipsw_init ();
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+#ifdef CONFIG_CMA111
+	return (32L * 1024L * 1024L);
+#else
+	unsigned char dipsw_val;
+	int dual, size0, size1;
+	long int memsize;
+
+	dipsw_val = dipsw_cooked ();
+
+	dual = dipsw_val & 0x01;
+	size0 = (dipsw_val & 0x08) >> 3;
+	size1 = (dipsw_val & 0x04) >> 2;
+
+	if (size0)
+		if (size1)
+			memsize = 16L * 1024L * 1024L;
+		else
+			memsize = 1L * 1024L * 1024L;
+	else if (size1)
+		memsize = 4L * 1024L * 1024L;
+	else {
+		printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
+		memsize = 16L * 1024L * 1024L;	/* shouldn't happen - guess 16M */
+	}
+
+	if (dual)
+		memsize *= 2L;
+
+	return (memsize);
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations after monitor
+ * has been relocated into ram
+ */
+
+int misc_init_r (void)
+{
+	printf ("LCD:   ");
+	lcd_init ();
+
+#if 0
+	printf ("RTC:   ");
+	rtc_init ();
+
+	printf ("PAR:   ");
+	par_init ();
+
+	printf ("KBM:   ");
+	kbm_init ();
+
+	printf ("PCI:   ");
+	pci_init ();
+#endif
+	return (0);
+}
diff --git a/u-boot/board/cogent/mb.h b/u-boot/board/cogent/mb.h
new file mode 100644
index 0000000..b3aba48
--- /dev/null
+++ b/u-boot/board/cogent/mb.h
@@ -0,0 +1,529 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * defines for Cogent Motherboards
+ */
+
+#ifndef _COGENT_MB_H
+#define _COGENT_MB_H
+
+/*
+ * Cogent Motherboard Address Map
+ *
+ * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
+ *
+ * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
+ * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
+ * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
+ * Most other motherboard devices have registers mapped into the area
+ * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
+ * is free for whatever.
+ *
+ * The location of the motherboard address space in the physical address space
+ * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
+ * module plugged into the motherboard and is configured above.
+ *
+ * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
+ * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
+ * 8 bit, or 1 byte, transfers can take place, so all the registers are
+ * only 8 bits wide. The exceptions are the motherboard flash, which uses
+ * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
+ *
+ * I/O registers within the mapped motherboard devices are 64 bit aligned
+ * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
+ * will be at byte 7 (the address + 7). For little endian addressing, the
+ * register will be at byte 0 (the address + 0). To learn the endianess
+ * we must include <endian.h>
+ *
+ * Take the CMA102 and CMA111 motherboards as examples...
+ *
+ * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
+ * CMABus slots are each mapped directly onto the three general I/O slots.
+ *
+ * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
+ * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
+ * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
+ * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
+ * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
+ * 0xA000000-0xDFFFFFF.
+ */
+
+#define CMA_MB_RAM_BASE		(CONFIG_SYS_CMA_MB_BASE+0x0000000)
+#define CMA_MB_RAM_SIZE		0x2000000	/* dip sws set actual size */
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
+#define CMA_MB_SLOT1_BASE	(CONFIG_SYS_CMA_MB_BASE+0x2000000)
+#define CMA_MB_SLOT1_SIZE	0x2000000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
+#define CMA_MB_SLOT2_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
+#define CMA_MB_SLOT2_SIZE	0x2000000
+#endif
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#define CMA_MB_STDPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
+#define CMA_MB_STDPCI_SIZE	0x1ff0000
+#define CMA_MB_V360EPC_BASE	(CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
+#define CMA_MB_V360EPC_SIZE	0x10000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
+#define CMA_MB_SLOT3_BASE	(CONFIG_SYS_CMA_MB_BASE+0x6000000)
+#define CMA_MB_SLOT3_SIZE	0x2000000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
+#define CMA_MB_EXTPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0xa000000)
+#define CMA_MB_EXTPCI_SIZE	0x4000000
+#endif
+
+#define CMA_MB_ROMLOW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
+#define CMA_MB_ROMLOW_SIZE	0x800000
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+#define CMA_MB_FLLOW_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
+#define CMA_MB_FLLOW_EXEC_SIZE	0x100000
+#define CMA_MB_FLLOW_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe400000)
+#define CMA_MB_FLLOW_RDWR_SIZE	0x400000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
+#define CMA_MB_RTC_BASE		(CONFIG_SYS_CMA_MB_BASE+0xe800000)
+#define CMA_MB_RTC_SIZE		0x4000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+#define CMA_MB_SERPAR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900000)
+#define   CMA_MB_SERIALB_BASE	  (CMA_MB_SERPAR_BASE+0x00)
+#define   CMA_MB_SERIALA_BASE	  (CMA_MB_SERPAR_BASE+0x40)
+#define   CMA_MB_PARALLEL_BASE	  (CMA_MB_SERPAR_BASE+0x80)
+#define CMA_MB_SERPAR_SIZE	0xa0
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
+#define CMA_MB_PKBM_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900100)
+#define CMA_MB_PKBM_SIZE	0x10
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
+#define CMA_MB_LCD_BASE		(CONFIG_SYS_CMA_MB_BASE+0xeb00000)
+#define CMA_MB_LCD_SIZE		0x10
+#endif
+
+#define CMA_MB_DIPSW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xec00000)
+#define CMA_MB_DIPSW_SIZE	0x10
+
+#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
+#define CMA_MB_SLOT1CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf100000)
+#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define   CMA_MB_SER2_BASE	  (CMA_MB_SLOT1CFG_BASE+0x80)
+#define     CMA_MB_SER2B_BASE	    (CMA_MB_SER2_BASE+0x00)
+#define     CMA_MB_SER2A_BASE	    (CMA_MB_SER2_BASE+0x40)
+#endif
+#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
+#define   CMA_MB_S1KBM_BASE	  (CMA_MB_SLOT1CFG_BASE+0x200)
+#endif
+#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
+#define   CMA_MB_IREQ1STAT_BASE	  (CMA_MB_SLOT1CFG_BASE+0x100)
+#define   CMA_MB_AKBM_BASE	  (CMA_MB_SLOT1CFG_BASE+0x200)
+#define   CMA_MB_IREQ1MASK_BASE	  (CMA_MB_SLOT1CFG_BASE+0x300)
+#endif
+#define CMA_MB_SLOT1CFG_SIZE	0x400
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
+#define CMA_MB_SLOT2CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
+#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
+#define   CMA_MB_S2KBM_BASE	  (CMA_MB_SLOT2CFG_BASE+0x200)
+#endif
+#define CMA_MB_SLOT2CFG_SIZE	0x400
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#define CMA_MB_PCICTL_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
+#define   CMA_MB_PCI_V3CTL_BASE	  (CMA_MB_PCICTL_BASE+0x100)
+#define   CMA_MB_PCI_IDSEL_BASE	  (CMA_MB_PCICTL_BASE+0x200)
+#define   CMA_MB_PCI_IMASK_BASE	  (CMA_MB_PCICTL_BASE+0x300)
+#define   CMA_MB_PCI_ISTAT_BASE	  (CMA_MB_PCICTL_BASE+0x400)
+#define   CMA_MB_PCI_MBID_BASE	  (CMA_MB_PCICTL_BASE+0x500)
+#define   CMA_MB_PCI_MBREV_BASE	  (CMA_MB_PCICTL_BASE+0x600)
+#define CMA_MB_PCICTL_SIZE	0x700
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
+#define CMA_MB_SLOT3CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf300000)
+#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
+#define   CMA_MB_S3KBM_BASE	  (CMA_MB_SLOT3CFG_BASE+0x200)
+#endif
+#define CMA_MB_SLOT3CFG_SIZE	0x400
+#endif
+
+#define CMA_MB_ROMHIGH_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
+#define CMA_MB_ROMHIGH_SIZE	0x800000
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+#define CMA_MB_FLHIGH_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
+#define CMA_MB_FLHIGH_EXEC_SIZE	0x100000
+#define CMA_MB_FLHIGH_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xfc00000)
+#define CMA_MB_FLHIGH_RDWR_SIZE	0x400000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+
+/* PCI Control Register bits */
+
+/* V360EPC Control register bits */
+#define CMA_MB_PCI_V3CTL_RESET	0x01
+#define CMA_MB_PCI_V3CTL_EXTADD	0x08
+
+/* PCI ID Select register bits */
+#define CMA_MB_PCI_IDSEL_SLOTA	0x01
+#define CMA_MB_PCI_IDSEL_SLOTB	0x02
+#define CMA_MB_PCI_IDSEL_GD82559 0x04
+#define CMA_MB_PCI_IDSEL_B69000	0x08
+#define CMA_MB_PCI_IDSEL_PD6832	0x10
+
+/* PCI Interrupt Mask/Status register bits */
+#define CMA_MB_PCI_IMS_INTA	0x01
+#define CMA_MB_PCI_IMS_INTB	0x02
+#define CMA_MB_PCI_IMS_INTC	0x04
+#define CMA_MB_PCI_IMS_INTD	0x08
+#define CMA_MB_PCI_IMS_CBINT	0x10
+#define CMA_MB_PCI_IMS_V3LINT	0x80
+
+#endif
+
+#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
+
+/*
+ * IREQ1 Interrupt Mask/Status register bits
+ * (Note: not available on CMA150 - must poll HT6542B interrupt register)
+ */
+
+#define IREQ1_MINT	0x01
+#define IREQ1_KINT	0x02
+#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define IREQ1_SINT2	0x04
+#define IREQ1_SINT3	0x08
+#endif
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef USE_HOSTCC
+#include <endian.h>		/* avoid using private kernel header files */
+#else
+#include <asm/byteorder.h>	/* use U-Boot provided headers */
+#endif
+
+/* a single CMA10x motherboard i/o register */
+typedef
+    struct {
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+	unsigned char value;
+#endif
+	unsigned char filler[7];
+#if __BYTE_ORDER == __BIG_ENDIAN
+	unsigned char value;
+#endif
+    }
+cma_mb_reg;
+
+extern __inline__ unsigned char
+cma_mb_reg_read(volatile cma_mb_reg *reg)
+{
+    unsigned char data = reg->value;
+    __asm__ __volatile__ ("eieio" : : : "memory");
+    return data;
+}
+
+extern __inline__ void
+cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
+{
+    reg->value = data;
+    __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
+
+/* MK48T02 RTC registers */
+typedef
+    struct {
+	cma_mb_reg sram[2040];/* Battery-Backed SRAM */
+	cma_mb_reg clk_ctl;	/* Clock Control Register */
+	cma_mb_reg clk_sec;	/* Clock Seconds Register */
+	cma_mb_reg clk_min;	/* Clock Minutes Register */
+	cma_mb_reg clk_hour;	/* Clock Hour Register */
+	cma_mb_reg clk_day;	/* Clock Day Register */
+	cma_mb_reg clk_date;	/* Clock Date Register */
+	cma_mb_reg clk_month;	/* Clock Month Register */
+	cma_mb_reg clk_year;	/* Clock Year Register */
+    }
+cma_mb_rtc;
+
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+
+/* ST16C522 Serial I/O */
+typedef
+    struct {
+	cma_mb_reg ser_rhr;	/* Receive Holding Register (R, DLAB=0) */
+	cma_mb_reg ser_ier;	/* Interrupt Enable Register (R/W, DLAB=0) */
+	cma_mb_reg ser_isr;	/* Interrupt Status Register (R) */
+	cma_mb_reg ser_lcr;	/* Line Control Register (R/W) */
+	cma_mb_reg ser_mcr;	/* Modem Control Register (R/W) */
+	cma_mb_reg ser_lsr;	/* Line Status Register (R) */
+	cma_mb_reg ser_msr;	/* Modem Status Register (R/W) */
+	cma_mb_reg ser_spr;	/* Scratch Pad Register (R/W) */
+    }
+cma_mb_serial;
+
+#define ser_thr	ser_rhr		/* Transmit Holding Register (W, DLAB=0) */
+#define ser_brl	ser_rhr		/* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
+#define ser_brh	ser_ier		/* Baud Rate Divisor High Byte (R/W, DLAB=1) */
+#define ser_fcr	ser_isr		/* FIFO Control Register (W) */
+#define ser_nop	ser_lsr		/* No Operation (W) */
+
+/* ST16C522 Parallel I/O */
+typedef
+    struct {
+	cma_mb_reg par_rdr;	/* Port Read Data Register (R) */
+	cma_mb_reg par_sr;	/* Status Register (R) */
+	cma_mb_reg par_cmd;	/* Command Register (R) */
+    }
+cma_mb_parallel;
+
+#define par_wdr	par_rdr		/* Port Write Data Register (W) */
+#define par_ios	par_sr		/* I/O Select Register (W) */
+#define par_ctl	par_cmd		/* Control Register (W) */
+
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
+
+/* HT6542B PS/2 Keyboard/Mouse Controller */
+typedef
+    struct {
+	cma_mb_reg kbm_rdr;	/* Read Data Register (R) */
+	cma_mb_reg kbm_sr;	/* Status Register (R) */
+    }
+cma_mb_kbm;
+
+#define kbm_wdr	kbm_rdr		/* Write Data Register (W) */
+#define kbm_cmd	kbm_sr		/* Command Register (W) */
+
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
+
+/* HD44780 LCD Display */
+typedef
+    struct {
+	cma_mb_reg lcd_ccr;	/* Current Character Register (R/W) */
+	cma_mb_reg lcd_bsr;	/* Busy Status Register (R) */
+    }
+cma_mb_lcd;
+
+#define lcd_cmd	lcd_bsr		/* Command Register (W) */
+
+#endif
+
+/* 8-Position Configuration Switch */
+typedef
+    struct {
+	cma_mb_reg dip_val;	/* Dip Switch value (R) */
+    }
+cma_mb_dipsw;
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+
+/* V360EPC PCI Bridge */
+typedef
+    struct {
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+	unsigned short v3_pci_vendor;		/* 0x00 */
+	unsigned short v3_pci_device;
+	unsigned short v3_pci_cmd;		/* 0x04 */
+	unsigned short v3_pci_stat;
+	unsigned long  v3_pci_cc_rev;		/* 0x08 */
+	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
+	unsigned long  v3_pci_io_base;		/* 0x10 */
+	unsigned long  v3_pci_base0;		/* 0x14 */
+	unsigned long  v3_pci_base1;		/* 0x18 */
+	unsigned long  reserved1[4];		/* 0x1c */
+	unsigned short v3_pci_sub_vendor;	/* 0x2c */
+	unsigned short v3_pci_sub_id;
+	unsigned long  v3_pci_rom;		/* 0x30 */
+	unsigned long  reserved2[2];		/* 0x34 */
+	unsigned long  v3_pci_bparam;		/* 0x3c */
+	unsigned long  v3_pci_map0;		/* 0x40 */
+	unsigned long  v3_pci_map1;		/* 0x44 */
+	unsigned long  v3_pci_int_stat;		/* 0x48 */
+	unsigned long  v3_pci_int_cfg;		/* 0x4c */
+	unsigned long  reserved3[1];		/* 0x50 */
+	unsigned long  v3_lb_base0;		/* 0x54 */
+	unsigned long  v3_lb_base1;		/* 0x58 */
+	unsigned short reserved4;		/* 0x5c */
+	unsigned short v3_lb_map0;
+	unsigned short reserved5;		/* 0x60 */
+	unsigned short v3_lb_map1;
+	unsigned short v3_lb_base2;		/* 0x64 */
+	unsigned short v3_lb_map2;
+	unsigned long  v3_lb_size;		/* 0x68 */
+	unsigned short reserved6;		/* 0x6c */
+	unsigned short v3_lb_io_base;
+	unsigned short v3_fifo_cfg;		/* 0x70 */
+	unsigned short v3_fifo_priority;
+	unsigned short v3_fifo_stat;		/* 0x74 */
+	unsigned char  v3_lb_istat;
+	unsigned char  v3_lb_imask;
+	unsigned short v3_system;		/* 0x78 */
+	unsigned short v3_lb_cfg;
+	unsigned short v3_pci_cfg;		/* 0x7c */
+	unsigned short reserved7;
+	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
+	unsigned long  v3_dma_local_addr0;	/* 0x84 */
+	unsigned long  v3_dma_length0:24;	/* 0x88 */
+	unsigned long  v3_dma_csr0:8;
+	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
+	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
+	unsigned long  v3_dma_local_addr1;	/* 0x94 */
+	unsigned long  v3_dma_length1:24;	/* 0x98 */
+	unsigned long  v3_dma_csr1:8;
+	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
+	unsigned long  v3_i20_mups[8];		/* 0xa0 */
+	unsigned char  v3_mail_data0;		/* 0xc0 */
+	unsigned char  v3_mail_data1;
+	unsigned char  v3_mail_data2;
+	unsigned char  v3_mail_data3;
+	unsigned char  v3_mail_data4;		/* 0xc4 */
+	unsigned char  v3_mail_data5;
+	unsigned char  v3_mail_data6;
+	unsigned char  v3_mail_data7;
+	unsigned char  v3_mail_data8;		/* 0xc8 */
+	unsigned char  v3_mail_data9;
+	unsigned char  v3_mail_data10;
+	unsigned char  v3_mail_data11;
+	unsigned char  v3_mail_data12;		/* 0xcc */
+	unsigned char  v3_mail_data13;
+	unsigned char  v3_mail_data14;
+	unsigned char  v3_mail_data15;
+	unsigned short v3_pci_mail_iewr;	/* 0xd0 */
+	unsigned short v3_pci_mail_ierd;
+	unsigned short v3_lb_mail_iewr;		/* 0xd4 */
+	unsigned short v3_lb_mail_ierd;
+	unsigned short v3_mail_wr_stat;		/* 0xd8 */
+	unsigned short v3_mail_rd_stat;
+	unsigned long  v3_qba_map;		/* 0xdc */
+	unsigned long  v3_dma_delay:8;		/* 0xe0 */
+	unsigned long  reserved8:24;
+	unsigned long  reserved9[7];		/* 0xe4 */
+#endif
+#if __BYTE_ORDER == __BIG_ENDIAN
+	unsigned short v3_pci_device;		/* 0x00 */
+	unsigned short v3_pci_vendor;
+	unsigned short v3_pci_stat;		/* 0x04 */
+	unsigned short v3_pci_cmd;
+	unsigned long  v3_pci_cc_rev;		/* 0x08 */
+	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
+	unsigned long  v3_pci_io_base;		/* 0x10 */
+	unsigned long  v3_pci_base0;		/* 0x14 */
+	unsigned long  v3_pci_base1;		/* 0x18 */
+	unsigned long  reserved1[4];		/* 0x1c */
+	unsigned short v3_pci_sub_id;		/* 0x2c */
+	unsigned short v3_pci_sub_vendor;
+	unsigned long  v3_pci_rom;		/* 0x30 */
+	unsigned long  reserved2[2];		/* 0x34 */
+	unsigned long  v3_pci_bparam;		/* 0x3c */
+	unsigned long  v3_pci_map0;		/* 0x40 */
+	unsigned long  v3_pci_map1;		/* 0x44 */
+	unsigned long  v3_pci_int_stat;		/* 0x48 */
+	unsigned long  v3_pci_int_cfg;		/* 0x4c */
+	unsigned long  reserved3;		/* 0x50 */
+	unsigned long  v3_lb_base0;		/* 0x54 */
+	unsigned long  v3_lb_base1;		/* 0x58 */
+	unsigned short v3_lb_map0;		/* 0x5c */
+	unsigned short reserved4;
+	unsigned short v3_lb_map1;		/* 0x60 */
+	unsigned short reserved5;
+	unsigned short v3_lb_map2;		/* 0x64 */
+	unsigned short v3_lb_base2;
+	unsigned long  v3_lb_size;		/* 0x68 */
+	unsigned short v3_lb_io_base;		/* 0x6c */
+	unsigned short reserved6;
+	unsigned short v3_fifo_priority;	/* 0x70 */
+	unsigned short v3_fifo_cfg;
+	unsigned char  v3_lb_imask;		/* 0x74 */
+	unsigned char  v3_lb_istat;
+	unsigned short v3_fifo_stat;
+	unsigned short v3_lb_cfg;		/* 0x78 */
+	unsigned short v3_system;
+	unsigned short reserved7;		/* 0x7c */
+	unsigned short v3_pci_cfg;
+	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
+	unsigned long  v3_dma_local_addr0;	/* 0x84 */
+	unsigned long  v3_dma_csr0:8;		/* 0x88 */
+	unsigned long  v3_dma_length0:24;
+	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
+	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
+	unsigned long  v3_dma_local_addr1;	/* 0x94 */
+	unsigned long  v3_dma_csr1:8;		/* 0x98 */
+	unsigned long  v3_dma_length1:24;
+	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
+	unsigned long  v3_i20_mups[8];		/* 0xa0 */
+	unsigned char  v3_mail_data3;		/* 0xc0 */
+	unsigned char  v3_mail_data2;
+	unsigned char  v3_mail_data1;
+	unsigned char  v3_mail_data0;
+	unsigned char  v3_mail_data7;		/* 0xc4 */
+	unsigned char  v3_mail_data6;
+	unsigned char  v3_mail_data5;
+	unsigned char  v3_mail_data4;
+	unsigned char  v3_mail_data11;		/* 0xc8 */
+	unsigned char  v3_mail_data10;
+	unsigned char  v3_mail_data9;
+	unsigned char  v3_mail_data8;
+	unsigned char  v3_mail_data15;		/* 0xcc */
+	unsigned char  v3_mail_data14;
+	unsigned char  v3_mail_data13;
+	unsigned char  v3_mail_data12;
+	unsigned short v3_pci_mail_ierd;	/* 0xd0 */
+	unsigned short v3_pci_mail_iewr;
+	unsigned short v3_lb_mail_ierd;		/* 0xd4 */
+	unsigned short v3_lb_mail_iewr;
+	unsigned short v3_mail_rd_stat;		/* 0xd8 */
+	unsigned short v3_mail_wr_stat;
+	unsigned long  v3_qba_map;		/* 0xdc */
+	unsigned long  reserved8:24;		/* 0xe0 */
+	unsigned long  v3_dma_delay:8;
+	unsigned long  reserved9[7];		/* 0xe4 */
+#endif
+    }						/* 0x100 */
+cma_mb_v360epc;
+
+#endif
+
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* _COGENT_MB_H */
diff --git a/u-boot/board/cogent/par.c b/u-boot/board/cogent/par.c
new file mode 100644
index 0000000..a03c0f1
--- /dev/null
+++ b/u-boot/board/cogent/par.c
@@ -0,0 +1,3 @@
+/* parallel not implemented yet */
+
+int cma_parallel_not_implemented = 1;
diff --git a/u-boot/board/cogent/par.h b/u-boot/board/cogent/par.h
new file mode 100644
index 0000000..664ae4a
--- /dev/null
+++ b/u-boot/board/cogent/par.h
@@ -0,0 +1,3 @@
+/* parallel not implemented yet */
+
+extern int cma_parallel_not_implemented;
diff --git a/u-boot/board/cogent/pci.c b/u-boot/board/cogent/pci.c
new file mode 100644
index 0000000..0a57c0c
--- /dev/null
+++ b/u-boot/board/cogent/pci.c
@@ -0,0 +1,3 @@
+/* pci not implemented yet */
+
+int cma_pci_not_implemented = 1;
diff --git a/u-boot/board/cogent/pci.h b/u-boot/board/cogent/pci.h
new file mode 100644
index 0000000..35aa354
--- /dev/null
+++ b/u-boot/board/cogent/pci.h
@@ -0,0 +1,3 @@
+/* pci not implemented yet */
+
+extern int cma_pci_not_implemented;
diff --git a/u-boot/board/cogent/rtc.c b/u-boot/board/cogent/rtc.c
new file mode 100644
index 0000000..ace9193
--- /dev/null
+++ b/u-boot/board/cogent/rtc.c
@@ -0,0 +1,3 @@
+/* rtc not implemented yet */
+
+int cma_rtc_not_implemented = 1;
diff --git a/u-boot/board/cogent/rtc.h b/u-boot/board/cogent/rtc.h
new file mode 100644
index 0000000..4b55bd2
--- /dev/null
+++ b/u-boot/board/cogent/rtc.h
@@ -0,0 +1,3 @@
+/* rtc not implemented yet */
+
+extern int cma_rtc_not_implemented;
diff --git a/u-boot/board/cogent/serial.c b/u-boot/board/cogent/serial.c
new file mode 100644
index 0000000..d9c27be
--- /dev/null
+++ b/u-boot/board/cogent/serial.c
@@ -0,0 +1,173 @@
+/*
+ * Simple serial driver for Cogent motherboard serial ports
+ * for use during boot
+ */
+
+#include <common.h>
+#include <board/cogent/serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+
+#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
+     (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
+
+#if CONFIG_CONS_INDEX == 1
+#define CMA_MB_SERIAL_BASE	CMA_MB_SERIALA_BASE
+#elif CONFIG_CONS_INDEX == 2
+#define CMA_MB_SERIAL_BASE	CMA_MB_SERIALB_BASE
+#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_SERIAL_BASE	CMA_MB_SER2A_BASE
+#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_SERIAL_BASE	CMA_MB_SER2B_BASE
+#else
+#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
+#endif
+
+int serial_init (void)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+
+	cma_mb_reg_write (&mbsp->ser_ier, 0x00);	/* turn off interrupts */
+	serial_setbrg ();
+	cma_mb_reg_write (&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
+	cma_mb_reg_write (&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
+	cma_mb_reg_write (&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
+
+	return (0);
+}
+
+void serial_setbrg (void)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+	unsigned int divisor;
+	unsigned char lcr;
+
+	if ((divisor = br_to_div (gd->baudrate)) == 0)
+		divisor = DEFDIV;
+
+	lcr = cma_mb_reg_read (&mbsp->ser_lcr);
+	cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80);	/* Access baud rate(set DLAB) */
+	cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+	cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+	cma_mb_reg_write (&mbsp->ser_lcr, lcr);	/* unset DLAB */
+}
+
+void serial_putc (const char c)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+
+	if (c == '\n')
+		serial_putc ('\r');
+
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
+
+	cma_mb_reg_write (&mbsp->ser_thr, c);
+}
+
+void serial_puts (const char *s)
+{
+	while (*s != '\0')
+		serial_putc (*s++);
+}
+
+int serial_getc (void)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
+
+	return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
+}
+
+int serial_tstc (void)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+
+	return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
+}
+
+#endif /* CONS_NONE */
+
+#if defined(CONFIG_CMD_KGDB) && \
+    defined(CONFIG_KGDB_NONE)
+
+#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
+#error Console and kgdb are on the same serial port - this is not supported
+#endif
+
+#if CONFIG_KGDB_INDEX == 1
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SERIALA_BASE
+#elif CONFIG_KGDB_INDEX == 2
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SERIALB_BASE
+#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SER2A_BASE
+#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SER2B_BASE
+#else
+#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
+#endif
+
+void kgdb_serial_init (void)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+	unsigned int divisor;
+
+	if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0)
+		divisor = DEFDIV;
+
+	cma_mb_reg_write (&mbsp->ser_ier, 0x00);	/* turn off interrupts */
+	cma_mb_reg_write (&mbsp->ser_lcr, 0x80);	/* Access baud rate(set DLAB) */
+	cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+	cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+	cma_mb_reg_write (&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
+	cma_mb_reg_write (&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
+	cma_mb_reg_write (&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
+
+	printf ("[on cma10x serial port B] ");
+}
+
+void putDebugChar (int c)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
+
+	cma_mb_reg_write (&mbsp->ser_thr, c & 0xff);
+}
+
+void putDebugStr (const char *str)
+{
+	while (*str != '\0') {
+		if (*str == '\n')
+			putDebugChar ('\r');
+		putDebugChar (*str++);
+	}
+}
+
+int getDebugChar (void)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
+
+	return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
+}
+
+void kgdb_interruptible (int yes)
+{
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+
+	if (yes == 1) {
+		printf ("kgdb: turning serial ints on\n");
+		cma_mb_reg_write (&mbsp->ser_ier, 0xf);
+	} else {
+		printf ("kgdb: turning serial ints off\n");
+		cma_mb_reg_write (&mbsp->ser_ier, 0x0);
+	}
+}
+
+#endif /* KGDB && KGDB_NONE */
+
+#endif /* CAPS & SERPAR */
diff --git a/u-boot/board/cogent/serial.h b/u-boot/board/cogent/serial.h
new file mode 100644
index 0000000..89962d8
--- /dev/null
+++ b/u-boot/board/cogent/serial.h
@@ -0,0 +1,15 @@
+/* Line Status Register bits */
+#define LSR_DR		0x01	/* Data ready */
+#define LSR_OE		0x02	/* Overrun */
+#define LSR_PE		0x04	/* Parity error */
+#define LSR_FE		0x08	/* Framing error */
+#define LSR_BI		0x10	/* Break */
+#define LSR_THRE	0x20	/* Xmit holding register empty */
+#define LSR_TEMT	0x40	/* Xmitter empty */
+#define LSR_ERR		0x80	/* Error */
+
+#define CLKRATE		3686400	/* cogent motherboard serial clk = 3.6864MHz */
+#define DEFDIV		1	/* default to 230400 bps */
+
+#define br_to_div(br)	(CLKRATE / (16 * (br)))
+#define div_to_br(div)	(CLKRATE / (16 * (div)))
diff --git a/u-boot/board/cogent/u-boot.lds b/u-boot/board/cogent/u-boot.lds
new file mode 100644
index 0000000..42ed142
--- /dev/null
+++ b/u-boot/board/cogent/u-boot.lds
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+#ifdef CONFIG_MPC8260
+    arch/powerpc/cpu/mpc8260/start.o	(.text*)
+#else
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+#endif
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/cogent/u-boot.lds.debug b/u-boot/board/cogent/u-boot.lds.debug
new file mode 100644
index 0000000..c218905
--- /dev/null
+++ b/u-boot/board/cogent/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/colibri_pxa270/Makefile b/u-boot/board/colibri_pxa270/Makefile
new file mode 100644
index 0000000..40b3a3d
--- /dev/null
+++ b/u-boot/board/colibri_pxa270/Makefile
@@ -0,0 +1,47 @@
+#
+# Toradex Colibri PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= colibri_pxa270.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/colibri_pxa270/colibri_pxa270.c b/u-boot/board/colibri_pxa270/colibri_pxa270.c
new file mode 100644
index 0000000..191fb33
--- /dev/null
+++ b/u-boot/board/colibri_pxa270/colibri_pxa270.c
@@ -0,0 +1,128 @@
+/*
+ * Toradex Colibri PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+struct serial_device *default_serial_console (void)
+{
+	return &serial_ffuart_device;
+}
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of vpac270 */
+	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef	CONFIG_CMD_USB
+int usb_board_init(void)
+{
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (UHCHR & UHCHR_FSBIR);
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+void usb_board_init_fail(void)
+{
+	return;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/cpc45/Makefile b/u-boot/board/cpc45/Makefile
new file mode 100644
index 0000000..5c6b78f
--- /dev/null
+++ b/u-boot/board/cpc45/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o plx9030.o pd67290.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cpc45/cpc45.c b/u-boot/board/cpc45/cpc45.c
new file mode 100644
index 0000000..1178822
--- /dev/null
+++ b/u-boot/board/cpc45/cpc45.c
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <i2c.h>
+#include <netdev.h>
+
+int sysControlDisplay(int digit, uchar ascii_code);
+extern void Plx9030Init(void);
+extern void SPD67290Init(void);
+
+	/* We have to clear the initial data area here. Couldn't have done it
+	 * earlier because DRAM had not been initialized.
+	 */
+int board_early_init_f(void)
+{
+
+	/* enable DUAL UART Mode on CPC45 */
+	*(uchar*)DUART_DCR |= 0x1;	/* set DCM bit */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+/*
+	char  revision = BOARD_REV;
+*/
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	puts ("CPC45  ");
+/*
+	printf("Revision %d ", revision);
+*/
+	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	int m, row, col, bank, i, ref;
+	unsigned long start, end;
+	uint32_t mccr1, mccr2;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+	unsigned int tmp;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (i2c_reg_read (0x50, 2) != 0x04)
+		return 0;	/* Memory type */
+
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	CONFIG_READ_WORD(MCCR2, mccr2);
+	mccr2 &= 0xffff0000;
+
+	start = CONFIG_SYS_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	switch(ref) {
+		case 0x00:
+		case 0x80:
+			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
+			break;
+		case 0x01:
+		case 0x81:
+			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
+			break;
+		case 0x02:
+		case 0x82:
+			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
+			break;
+		case 0x03:
+		case 0x83:
+			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
+			break;
+		case 0x04:
+		case 0x84:
+			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
+			break;
+		case 0x05:
+		case 0x85:
+			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
+			break;
+		default:
+			tmp = 0x512;
+			break;
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+static struct pci_config_table pci_cpc45_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
+				       PCI_PLX9030_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
+				       PCMCIA_IO_BASE,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
+#endif /*CONFIG_PCI_PNP*/
+	{ }
+};
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_cpc45_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+
+	/* init PCI_to_LOCAL Bus BRIDGE */
+	Plx9030Init();
+
+	/* Clear Display */
+	DISP_CWORD = 0x0;
+
+	sysControlDisplay(0,' ');
+	sysControlDisplay(1,'C');
+	sysControlDisplay(2,'P');
+	sysControlDisplay(3,'C');
+	sysControlDisplay(4,' ');
+	sysControlDisplay(5,'4');
+	sysControlDisplay(6,'5');
+	sysControlDisplay(7,' ');
+
+}
+
+/**************************************************************************
+*
+* sysControlDisplay - controls one of the Alphanum. Display digits.
+*
+* This routine will write an ASCII character to the display digit requested.
+*
+* SEE ALSO:
+*
+* RETURNS: NA
+*/
+
+int sysControlDisplay (int digit,	/* number of digit 0..7 */
+		       uchar ascii_code	/* ASCII code */
+		      )
+{
+	if ((digit < 0) || (digit > 7))
+		return (-1);
+
+	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
+
+	return (0);
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+
+#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init(void)
+{
+	u_int rc;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	rc = i82365_init();
+
+	return rc;
+}
+
+#endif
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	u_char  val;
+	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
+	val = readb(BCSR_BASE + 0x04);
+	if (status) {				/* led on */
+		val |= B_CTRL_LED0;
+	} else {
+		val &= ~B_CTRL_LED0;
+	}
+	writeb(val, BCSR_BASE + 0x04);
+}
+# endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/cpc45/flash.c b/u-boot/board/cpc45/flash.c
new file mode 100644
index 0000000..8fe7584
--- /dev/null
+++ b/u-boot/board/cpc45/flash.c
@@ -0,0 +1,522 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x40000
+#define PARAM_SECT_SIZE 0x8000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static int write_data (flash_info_t * info, ulong dest, ulong * data);
+static void write_via_fpu (vu_long * addr, ulong * data);
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);
+
+/*---------------------------------------------------------------------*/
+#undef	DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+	uchar tempChar;
+	vu_long *tmpaddr;
+
+	/* Enable flash writes on CPC45 */
+
+	tempChar = BOARD_CTRL;
+
+	tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+
+	tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+
+	BOARD_CTRL = tempChar;
+
+	__asm__ volatile ("sync\n eieio");
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0] = 0x00900090;
+
+		__asm__ volatile ("sync\n eieio");
+
+		udelay (100);
+
+		DEBUGF ("Flash bank # %d:\n"
+			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+			i,
+			(ulong) (&addr[0]), addr[0],
+			(ulong) (&addr[2]), addr[2]);
+
+
+		if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+		    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
+
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
+
+		} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
+			 && (addr[2] == addr[3])
+			 && (addr[2] == INTEL_ID_28F160C3T)) {
+
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160C3T & FLASH_TYPEMASK);
+
+		} else {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFFFFFFFF;
+			goto Done;
+		}
+
+		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+		addr[0] = 0xFFFFFFFF;
+
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j > 30) {
+				flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					(MAIN_SECT_SIZE * 31) + (j -
+								 31) *
+					PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					j * MAIN_SECT_SIZE;
+			}
+		}
+
+		/* unlock sectors, if 160C3T */
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			tmpaddr = (vu_long *) flash_info[i].start[j];
+
+			if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			    (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
+				tmpaddr[0] = 0x00600060;
+				tmpaddr[0] = 0x00D000D0;
+				tmpaddr[1] = 0x00600060;
+				tmpaddr[1] = 0x00D000D0;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+#endif
+
+Done:
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch ((i = info->flash_id & FLASH_VENDMASK)) {
+	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor 0x%04x ", i);
+		break;
+	}
+
+	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
+		printf ("28F160F3T (16Mbit)\n");
+		break;
+
+	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
+		printf ("28F160C3T (16Mbit)\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type 0x%04x\n", i);
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+		info - &flash_info[0], s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			DEBUGF ("Erase sect %d @ 0x%08lX\n",
+				sect, (ulong) addr);
+
+			/* Disable interrupts which might cause a timeout
+			 * here.
+			 */
+			flag = disable_interrupts ();
+
+			addr[0] = 0x00500050;	/* clear status register */
+			addr[0] = 0x00200020;	/* erase setup */
+			addr[0] = 0x00D000D0;	/* erase confirm */
+
+			addr[1] = 0x00500050;	/* clear status register */
+			addr[1] = 0x00200020;	/* erase setup */
+			addr[1] = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((addr[0] & 0x00800080) != 0x00800080) ||
+			       ((addr[1] & 0x00800080) != 0x00800080)) {
+				if ((now = get_timer (start)) >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					addr[0] = 0x00B000B0;	/* suspend erase */
+					addr[0] = 0x00FF00FF;	/* to read mode  */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			addr[0] = 0x00FF00FF;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	8	/* flash bus width in bytes */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, cp, msr;
+	int l, rc, i;
+	ulong data[2];
+	ulong *datah = &data[0];
+	ulong *datal = &data[1];
+
+	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+		addr, (ulong) src, cnt);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
+
+	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		*datah = *datal = 0;
+
+		for (i = 0, cp = wp; i < l; i++, cp++) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+					((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | (*(uchar *) cp);
+		}
+		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+			char tmp = *src++;
+
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+					((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | tmp;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+					((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datah << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
+			return (rc);
+		}
+
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		*datah = *(ulong *) src;
+		*datal = *(ulong *) (src + 4);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+		src += FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		set_msr (msr);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	*datah = *datal = 0;
+	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+		char tmp = *src++;
+
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
+		}
+
+		*datal = (*datal << 8) | tmp;
+		--cnt;
+	}
+
+	for (; i < FLASH_WIDTH; ++i, ++cp) {
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
+		}
+
+		*datal = (*datal << 8) | (*(uchar *) cp);
+	}
+
+	rc = write_data (info, wp, data);
+	set_msr (msr);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((addr[0] & data[0]) != data[0]) ||
+	    ((addr[1] & data[1]) != data[1])) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[0] = 0x00400040;	/* write setup */
+	write_via_fpu (addr, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((addr[0] & 0x00800080) != 0x00800080) ||
+	       ((addr[1] & 0x00800080) != 0x00800080)) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			addr[0] = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	addr[0] = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (vu_long * addr, ulong * data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+}
+
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+}
diff --git a/u-boot/board/cpc45/pd67290.c b/u-boot/board/cpc45/pd67290.c
new file mode 100644
index 0000000..0d8ef23
--- /dev/null
+++ b/u-boot/board/cpc45/pd67290.c
@@ -0,0 +1,818 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ *
+ * Lots of code copied from:
+ *
+ * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
+ * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
+ * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_I82365
+
+#include <command.h>
+#include <pci.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#include <pcmcia/ss.h>
+#include <pcmcia/i82365.h>
+#include <pcmcia/yenta.h>
+#include <pcmcia/cirrus.h>
+
+static struct pci_device_id supported[] = {
+	{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
+	{0, 0}
+};
+
+#define CYCLE_TIME	120
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev);
+#endif
+
+typedef struct socket_info_t {
+	pci_dev_t	dev;
+	u_short		bcr;
+	u_char		pci_lat, cb_lat, sub_bus, cache;
+	u_int		cb_phys;
+
+	socket_cap_t	cap;
+	u_short		type;
+	u_int		flags;
+	cirrus_state_t	c_state;
+} socket_info_t;
+
+/* These definitions must match the pcic table! */
+typedef enum pcic_id {
+	IS_PD6710, IS_PD672X, IS_VT83C469
+} pcic_id;
+
+typedef struct pcic_t {
+	char *name;
+} pcic_t;
+
+static pcic_t pcic[] = {
+	{" Cirrus PD6710: "},
+	{" Cirrus PD672x: "},
+	{" VIA VT83C469: "},
+};
+
+static socket_info_t socket;
+static socket_state_t state;
+static struct pccard_mem_map mem;
+static struct pccard_io_map io;
+
+/*====================================================================*/
+
+/* Some PCI shortcuts */
+
+static int pci_readb (socket_info_t * s, int r, u_char * v)
+{
+	return pci_read_config_byte (s->dev, r, v);
+}
+static int pci_writeb (socket_info_t * s, int r, u_char v)
+{
+	return pci_write_config_byte (s->dev, r, v);
+}
+static int pci_readw (socket_info_t * s, int r, u_short * v)
+{
+	return pci_read_config_word (s->dev, r, v);
+}
+static int pci_writew (socket_info_t * s, int r, u_short v)
+{
+	return pci_write_config_word (s->dev, r, v);
+}
+
+/*====================================================================*/
+
+#define cb_readb(s)		readb((s)->cb_phys + 1)
+#define cb_writeb(s, v)		writeb(v, (s)->cb_phys)
+#define cb_writeb2(s, v)	writeb(v, (s)->cb_phys + 1)
+#define cb_readl(s, r)		readl((s)->cb_phys + (r))
+#define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))
+
+
+static u_char i365_get (socket_info_t * s, u_short reg)
+{
+	u_char val;
+#ifdef CONFIG_PCMCIA_SLOT_A
+	int slot = 0;
+#else
+	int slot = 1;
+#endif
+
+	val = I365_REG (slot, reg);
+
+	cb_writeb (s, val);
+	val = cb_readb (s);
+
+	debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
+	return val;
+}
+
+static void i365_set (socket_info_t * s, u_short reg, u_char data)
+{
+#ifdef CONFIG_PCMCIA_SLOT_A
+	int slot = 0;
+#else
+	int slot = 1;
+#endif
+	u_char val;
+
+	val = I365_REG (slot, reg);
+
+	cb_writeb (s, val);
+	cb_writeb2 (s, data);
+
+	debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
+}
+
+static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
+{
+	i365_set (s, reg, i365_get (s, reg) | mask);
+}
+
+static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
+{
+	i365_set (s, reg, i365_get (s, reg) & ~mask);
+}
+
+#if 0	/* not used */
+static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
+{
+	u_char d = i365_get (s, reg);
+
+	i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
+}
+
+static u_short i365_get_pair (socket_info_t * s, u_short reg)
+{
+	return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
+}
+#endif	/* not used */
+
+static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
+{
+	i365_set (s, reg, data & 0xff);
+	i365_set (s, reg + 1, data >> 8);
+}
+
+/*======================================================================
+
+    Code to save and restore global state information for Cirrus
+    PD67xx controllers, and to set and report global configuration
+    options.
+
+======================================================================*/
+
+#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
+
+static void cirrus_get_state (socket_info_t * s)
+{
+	int i;
+	cirrus_state_t *p = &s->c_state;
+
+	p->misc1 = i365_get (s, PD67_MISC_CTL_1);
+	p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
+	p->misc2 = i365_get (s, PD67_MISC_CTL_2);
+	for (i = 0; i < 6; i++)
+		p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
+
+}
+
+static void cirrus_set_state (socket_info_t * s)
+{
+	int i;
+	u_char misc;
+	cirrus_state_t *p = &s->c_state;
+
+	misc = i365_get (s, PD67_MISC_CTL_2);
+	i365_set (s, PD67_MISC_CTL_2, p->misc2);
+	if (misc & PD67_MC2_SUSPEND)
+		udelay (50000);
+	misc = i365_get (s, PD67_MISC_CTL_1);
+	misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
+	i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
+	for (i = 0; i < 6; i++)
+		i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
+}
+
+static u_int cirrus_set_opts (socket_info_t * s)
+{
+	cirrus_state_t *p = &s->c_state;
+	u_int mask = 0xffff;
+#if DEBUG
+	char buf[200];
+
+	memset (buf, 0, 200);
+#endif
+
+	if (has_ring == -1)
+		has_ring = 1;
+	flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
+	flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
+#if DEBUG
+	if (p->misc2 & PD67_MC2_IRQ15_RI)
+		strcat (buf, " [ring]");
+	if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
+		strcat (buf, " [dyn mode]");
+	if (p->misc1 & PD67_MC1_INPACK_ENA)
+		strcat (buf, " [inpack]");
+#endif
+
+	if (p->misc2 & PD67_MC2_IRQ15_RI)
+		mask &= ~0x8000;
+	if (has_led > 0) {
+#if DEBUG
+		strcat (buf, " [led]");
+#endif
+		mask &= ~0x1000;
+	}
+	if (has_dma > 0) {
+#if DEBUG
+		strcat (buf, " [dma]");
+#endif
+		mask &= ~0x0600;
+		flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
+#if DEBUG
+		if (p->misc2 & PD67_MC2_FREQ_BYPASS)
+			strcat (buf, " [freq bypass]");
+#endif
+	}
+
+	if (setup_time >= 0)
+		p->timer[0] = p->timer[3] = setup_time;
+	if (cmd_time > 0) {
+		p->timer[1] = cmd_time;
+		p->timer[4] = cmd_time * 2 + 4;
+	}
+	if (p->timer[1] == 0) {
+		p->timer[1] = 6;
+		p->timer[4] = 16;
+		if (p->timer[0] == 0)
+			p->timer[0] = p->timer[3] = 1;
+	}
+	if (recov_time >= 0)
+		p->timer[2] = p->timer[5] = recov_time;
+
+	debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
+		buf,
+		p->timer[0], p->timer[1], p->timer[2],
+		p->timer[3], p->timer[4], p->timer[5]);
+
+	return mask;
+}
+
+/*======================================================================
+
+    Routines to handle common CardBus options
+
+======================================================================*/
+
+/* Default settings for PCI command configuration register */
+#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
+		  PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
+
+static void cb_get_state (socket_info_t * s)
+{
+	pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
+	pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
+	pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
+	pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
+	pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
+	pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
+}
+
+static void cb_set_state (socket_info_t * s)
+{
+	pci_writew (s, PCI_COMMAND, CMD_DFLT);
+	pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
+	pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
+	pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
+	pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
+	pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
+	pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
+}
+
+static void cb_set_opts (socket_info_t * s)
+{
+}
+
+/*======================================================================
+
+    Power control for Cardbus controllers: used both for 16-bit and
+    Cardbus cards.
+
+======================================================================*/
+
+static int cb_set_power (socket_info_t * s, socket_state_t * state)
+{
+	u_int reg = 0;
+
+	reg = I365_PWR_NORESET;
+	if (state->flags & SS_PWR_AUTO)
+		reg |= I365_PWR_AUTO;
+	if (state->flags & SS_OUTPUT_ENA)
+		reg |= I365_PWR_OUT;
+	if (state->Vpp != 0) {
+		if (state->Vpp == 120) {
+			reg |= I365_VPP1_12V;
+			puts (" 12V card found: ");
+		} else if (state->Vpp == state->Vcc) {
+			reg |= I365_VPP1_5V;
+		} else {
+			puts (" power not found: ");
+			return -1;
+		}
+	}
+	if (state->Vcc != 0) {
+		reg |= I365_VCC_5V;
+		if (state->Vcc == 33) {
+			puts (" 3.3V card found: ");
+			i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+		} else if (state->Vcc == 50) {
+			puts (" 5V card found: ");
+			i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+		} else {
+			puts (" power not found: ");
+			return -1;
+		}
+	}
+
+	if (reg != i365_get (s, I365_POWER)) {
+		reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
+		i365_set (s, I365_POWER, reg);
+	}
+
+	return 0;
+}
+
+/*======================================================================
+
+    Generic routines to get and set controller options
+
+======================================================================*/
+
+static void get_bridge_state (socket_info_t * s)
+{
+	cirrus_get_state (s);
+	cb_get_state (s);
+}
+
+static void set_bridge_state (socket_info_t * s)
+{
+	cb_set_state (s);
+	i365_set (s, I365_GBLCTL, 0x00);
+	i365_set (s, I365_GENCTL, 0x00);
+	cirrus_set_state (s);
+}
+
+static void set_bridge_opts (socket_info_t * s)
+{
+	cirrus_set_opts (s);
+	cb_set_opts (s);
+}
+
+/*====================================================================*/
+#define PD67_EXT_INDEX		0x2e	/* Extension index */
+#define PD67_EXT_DATA		0x2f	/* Extension data */
+#define PD67_EXD_VS1(s)		(0x01 << ((s)<<1))
+
+#define pd67_ext_get(s, r) \
+    (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
+
+static int i365_get_status (socket_info_t * s, u_int * value)
+{
+	u_int status;
+	u_char val;
+	u_char power, vcc, vpp;
+	u_int powerstate;
+
+	status = i365_get (s, I365_IDENT);
+	status = i365_get (s, I365_STATUS);
+	*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
+	if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
+		*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
+	} else {
+		*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
+		*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
+	}
+	*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
+	*value |= (status & I365_CS_READY) ? SS_READY : 0;
+	*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
+
+	/* Check for Cirrus CL-PD67xx chips */
+	i365_set (s, PD67_CHIP_INFO, 0);
+	val = i365_get (s, PD67_CHIP_INFO);
+	s->type = -1;
+	if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
+		val = i365_get (s, PD67_CHIP_INFO);
+		if ((val & PD67_INFO_CHIP_ID) == 0) {
+			s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
+			i365_set (s, PD67_EXT_INDEX, 0xe5);
+			if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
+				s->type = IS_VT83C469;
+		}
+	} else {
+		printf ("no Cirrus Chip found\n");
+		*value = 0;
+		return -1;
+	}
+
+	power = i365_get (s, I365_POWER);
+	state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
+	state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
+	vcc = power & I365_VCC_MASK;
+	vpp = power & I365_VPP1_MASK;
+	state.Vcc = state.Vpp = 0;
+	if((vcc== 0) || (vpp == 0)) {
+		/*
+		 * On the Cirrus we get the info which card voltage
+		 * we have in EXTERN DATA and write it to MISC_CTL1
+		 */
+		powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
+		if (powerstate & PD67_EXD_VS1(0)) {
+			/* 5V Card */
+			i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+		} else {
+			/* 3.3V Card */
+			i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+		}
+		i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
+		power = i365_get (s, I365_POWER);
+	}
+	if (power & I365_VCC_5V) {
+		state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
+	}
+
+	if (power == I365_VPP1_12V)
+		state.Vpp = 120;
+
+	/* IO card, RESET flags, IO interrupt */
+	power = i365_get (s, I365_INTCTL);
+	state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
+	if (power & I365_PC_IOCARD)
+		state.flags |= SS_IOCARD;
+	state.io_irq = power & I365_IRQ_MASK;
+
+	/* Card status change mask */
+	power = i365_get (s, I365_CSCINT);
+	state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
+	if (state.flags & SS_IOCARD)
+		state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
+	else {
+		state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
+		state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
+		state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
+	}
+	debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
+		"io_irq %d, csc_mask %#2.2x\n", state.flags,
+		state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
+
+	return 0;
+}	/* i365_get_status */
+
+static int i365_set_socket (socket_info_t * s, socket_state_t * state)
+{
+	u_char reg;
+
+	set_bridge_state (s);
+
+	/* IO card, RESET flag */
+	reg = 0;
+	reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
+	reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
+	i365_set (s, I365_INTCTL, reg);
+
+	cb_set_power (s, state);
+
+#if 0
+	/* Card status change interrupt mask */
+	reg = s->cs_irq << 4;
+	if (state->csc_mask & SS_DETECT)
+		reg |= I365_CSC_DETECT;
+	if (state->flags & SS_IOCARD) {
+		if (state->csc_mask & SS_STSCHG)
+			reg |= I365_CSC_STSCHG;
+	} else {
+		if (state->csc_mask & SS_BATDEAD)
+			reg |= I365_CSC_BVD1;
+		if (state->csc_mask & SS_BATWARN)
+			reg |= I365_CSC_BVD2;
+		if (state->csc_mask & SS_READY)
+			reg |= I365_CSC_READY;
+	}
+	i365_set (s, I365_CSCINT, reg);
+	i365_get (s, I365_CSC);
+#endif	/* 0 */
+
+	return 0;
+}	/* i365_set_socket */
+
+/*====================================================================*/
+
+static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
+{
+	u_short base, i;
+	u_char map;
+
+	debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
+		mem->map, mem->flags, mem->speed,
+		mem->sys_start, mem->sys_stop, mem->card_start);
+
+	map = mem->map;
+	if ((map > 4) ||
+	    (mem->card_start > 0x3ffffff) ||
+	    (mem->sys_start > mem->sys_stop) ||
+	    (mem->speed > 1000)) {
+		return -1;
+	}
+
+	/* Turn off the window before changing anything */
+	if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
+		i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
+
+	/* Take care of high byte, for PCI controllers */
+	i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
+
+	base = I365_MEM (map);
+	i = (mem->sys_start >> 12) & 0x0fff;
+	if (mem->flags & MAP_16BIT)
+		i |= I365_MEM_16BIT;
+	if (mem->flags & MAP_0WS)
+		i |= I365_MEM_0WS;
+	i365_set_pair (s, base + I365_W_START, i);
+
+	i = (mem->sys_stop >> 12) & 0x0fff;
+	switch (mem->speed / CYCLE_TIME) {
+	case 0:
+		break;
+	case 1:
+		i |= I365_MEM_WS0;
+		break;
+	case 2:
+		i |= I365_MEM_WS1;
+		break;
+	default:
+		i |= I365_MEM_WS1 | I365_MEM_WS0;
+		break;
+	}
+	i365_set_pair (s, base + I365_W_STOP, i);
+
+	i = 0;
+	if (mem->flags & MAP_WRPROT)
+		i |= I365_MEM_WRPROT;
+	if (mem->flags & MAP_ATTRIB)
+		i |= I365_MEM_REG;
+	i365_set_pair (s, base + I365_W_OFF, i);
+
+	/* set System Memory map Upper Adress */
+	i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
+	i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
+
+	/* Turn on the window if necessary */
+	if (mem->flags & MAP_ACTIVE)
+		i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
+	return 0;
+}	/* i365_set_mem_map */
+
+static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
+{
+	u_char map, ioctl;
+
+	map = io->map;
+	/* comment out: comparison is always false due to limited range of data type */
+	if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
+	    (io->stop < io->start))
+		return -1;
+	/* Turn off the window before changing anything */
+	if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
+		i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
+	i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
+	i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
+	ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
+	if (io->speed)
+		ioctl |= I365_IOCTL_WAIT (map);
+	if (io->flags & MAP_0WS)
+		ioctl |= I365_IOCTL_0WS (map);
+	if (io->flags & MAP_16BIT)
+		ioctl |= I365_IOCTL_16BIT (map);
+	if (io->flags & MAP_AUTOSZ)
+		ioctl |= I365_IOCTL_IOCS16 (map);
+	i365_set (s, I365_IOCTL, ioctl);
+	/* Turn on the window if necessary */
+	if (io->flags & MAP_ACTIVE)
+		i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
+	return 0;
+}	/* i365_set_io_map */
+
+/*====================================================================*/
+
+/*
+ * PCI_ADDR = (HOST_ADDR - 0xfe000000)
+ * see MPC 8245 Users Manual Adress Map B
+ */
+#define	HOST_TO_PCI(addr)	((addr) - 0xfe000000)
+#define	PCI_TO_HOST(addr)	((addr) + 0xfe000000)
+
+static int i82365_init (void)
+{
+	u_int val;
+	int i;
+
+	if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
+		/* Controller not found */
+		printf ("No PD67290 device found !!\n");
+		return 1;
+	}
+	debug ("i82365 Device Found!\n");
+
+	socket.cb_phys = PCMCIA_IO_BASE;
+
+	/* set base address */
+	pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0,
+		HOST_TO_PCI(socket.cb_phys));
+
+	/* enable mapped memory and IO addresses */
+	pci_write_config_dword (socket.dev,
+				PCI_COMMAND,
+				PCI_COMMAND_MEMORY |
+				PCI_COMMAND_IO | PCI_COMMAND_WAIT);
+
+	get_bridge_state (&socket);
+	set_bridge_opts (&socket);
+
+	i = i365_get_status (&socket, &val);
+
+	if (i > -1) {
+		puts (pcic[socket.type].name);
+	} else {
+		printf ("i82365: Controller not found.\n");
+		return 1;
+	}
+	if((val & SS_DETECT) != SS_DETECT){
+		puts ("No card\n");
+		return 1;
+	}
+
+	state.flags |= SS_OUTPUT_ENA;
+
+	i365_set_socket (&socket, &state);
+
+	for (i = 500; i; i--) {
+		if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
+			break;
+		udelay (1000);
+	}
+
+	if (i == 0) {
+		/* PC Card not ready for data transfer */
+		puts ("i82365 PC Card not ready for data transfer\n");
+		return 1;
+	}
+	debug (" PC Card ready for data transfer: ");
+
+	mem.map = 0;
+	mem.flags = MAP_ATTRIB | MAP_ACTIVE;
+	mem.speed = 300;
+	mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
+	mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
+	mem.card_start = 0;
+	i365_set_mem_map (&socket, &mem);
+
+	mem.map = 1;
+	mem.flags = MAP_ACTIVE;
+	mem.speed = 300;
+	mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
+	mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
+	mem.card_start = 0;
+	i365_set_mem_map (&socket, &mem);
+
+#ifdef DEBUG
+	i82365_dump_regions (socket.dev);
+#endif
+
+	return 0;
+}
+
+static void i82365_exit (void)
+{
+	io.map = 0;
+	io.flags = 0;
+	io.speed = 0;
+	io.start = 0;
+	io.stop = 0x1;
+
+	i365_set_io_map (&socket, &io);
+
+	mem.map = 0;
+	mem.flags = 0;
+	mem.speed = 0;
+	mem.sys_start = 0;
+	mem.sys_stop = 0x1000;
+	mem.card_start = 0;
+
+	i365_set_mem_map (&socket, &mem);
+
+	mem.map = 1;
+	mem.flags = 0;
+	mem.speed = 0;
+	mem.sys_start = 0;
+	mem.sys_stop = 0x1000;
+	mem.card_start = 0;
+
+	i365_set_mem_map (&socket, &mem);
+
+	state.Vcc = state.Vpp = 0;
+
+	i365_set_socket (&socket, &state);
+}
+
+int pcmcia_on (void)
+{
+	u_int rc;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	rc = i82365_init();
+	if (rc)
+		goto exit;
+
+	rc = check_ide_device(0);
+	if (rc == 0)
+		goto exit;
+
+	i82365_exit();
+
+exit:
+	return rc;
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	i82365_exit();
+
+	return 0;
+}
+#endif
+
+/*======================================================================
+
+    Debug stuff
+
+======================================================================*/
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev)
+{
+	u_int tmp[2];
+	u_int *mem = (void *) socket.cb_phys;
+	u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
+	u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
+
+	pci_read_config_dword (dev, 0x00, tmp + 0);
+	pci_read_config_dword (dev, 0x80, tmp + 1);
+
+	printf ("PCI CONF: %08X ... %08X\n",
+		tmp[0], tmp[1]);
+	printf ("PCI MEM:  ... %08X ... %08X\n",
+		mem[0x8 / 4], mem[0x800 / 4]);
+	printf ("CIS:      ...%c%c%c%c%c%c%c%c...\n",
+		cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
+		cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
+	printf ("CIS CONF: %02X %02X %02X ...\n",
+		cis[0x200], cis[0x202], cis[0x204]);
+	printf ("IDE:      %02X %02X %02X %02X %02X %02X %02X %02X\n",
+		ide[0], ide[1], ide[2], ide[3],
+		ide[4], ide[5], ide[6], ide[7]);
+}
+#endif	/* DEBUG */
+
+#endif /* CONFIG_I82365 */
diff --git a/u-boot/board/cpc45/plx9030.c b/u-boot/board/cpc45/plx9030.c
new file mode 100644
index 0000000..3711ccb
--- /dev/null
+++ b/u-boot/board/cpc45/plx9030.c
@@ -0,0 +1,173 @@
+/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
+/*
+ * (C) Copyright 2002-2003
+ * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *   Date       Modification                                      by
+ * -------      ----------------------------------------------    ---
+ * 30sep02      converted from VxWorks to LINUX                   wa
+*/
+
+
+/*
+DESCRIPTION
+
+This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
+It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
+registers (CS3) on CPC45.
+*/
+
+/* includes */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* imports */
+
+
+/* defines */
+#define	PLX9030_VENDOR_ID	0x10B5
+#define	PLX9030_DEVICE_ID	0x9030
+
+#undef PLX_DEBUG
+
+/* PLX9030 register offsets  */
+#define	P9030_LAS0RR	0x00
+#define	P9030_LAS1RR	0x04
+#define	P9030_LAS2RR	0x08
+#define	P9030_LAS3RR	0x0c
+#define	P9030_EROMRR	0x10
+#define	P9030_LAS0BA	0x14
+#define	P9030_LAS1BA	0x18
+#define	P9030_LAS2BA	0x1c
+#define	P9030_LAS3BA	0x20
+#define	P9030_EROMBA	0x24
+#define	P9030_LAS0BRD	0x28
+#define	P9030_LAS1BRD	0x2c
+#define	P9030_LAS2BRD	0x30
+#define	P9030_LAS3BRD	0x34
+#define	P9030_EROMBRD	0x38
+#define	P9030_CS0BASE	0x3C
+#define	P9030_CS1BASE	0x40
+#define	P9030_CS2BASE	0x44
+#define	P9030_CS3BASE	0x48
+#define	P9030_INTCSR	0x4c
+#define	P9030_CNTRL	0x50
+#define	P9030_GPIOC	0x54
+
+/* typedefs */
+
+
+/* locals */
+
+static struct pci_device_id supported[] = {
+	{ PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
+	{ }
+};
+
+/* forward declarations */
+void sysOutLong(ulong address, ulong value);
+
+
+/***************************************************************************
+*
+* Plx9030Init - init CS0..CS3 for CPC45
+*
+*
+* RETURNS: N/A
+*/
+
+void Plx9030Init (void)
+{
+    pci_dev_t   devno;
+    ulong	membaseCsr;	  /* base address of device memory space */
+    int		idx = 0;	  /* general index */
+
+
+    /* find plx9030 device */
+
+    if ((devno = pci_find_devices(supported, idx++)) < 0)
+    {
+	printf("No PLX9030 device found !!\n");
+	return;
+    }
+
+
+#ifdef PLX_DEBUG
+	printf("PLX 9030 device found ! devno = 0x%x\n",devno);
+#endif
+
+	membaseCsr   = PCI_PLX9030_MEMADDR;
+
+	/* set base address */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
+
+	/* enable mapped memory and IO addresses */
+	pci_write_config_dword(devno,
+			       PCI_COMMAND,
+			       PCI_COMMAND_MEMORY |
+			       PCI_COMMAND_MASTER);
+
+
+	/* configure GBIOC */
+	sysOutLong((membaseCsr + P9030_GPIOC),   0x00000FC0);		/* CS2/CS3 enable */
+
+	/* configure CS0 (SRAM) */
+	sysOutLong((membaseCsr + P9030_LAS0BA),  0x00000001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS0RR),  0x0FE00000);		/* 2 MByte */
+	sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);		/* enable 2 MByte */
+	/* remap CS0 (SRAM) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
+
+	/* configure CS1 (ST16552 / CHAN A) */
+	sysOutLong((membaseCsr + P9030_LAS1BA),  0x00400001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS1RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);		/* enable 256 Byte */
+	/* remap CS1 (ST16552 / CHAN A) */
+	/* remap CS1 (ST16552 / CHAN A) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
+
+	/* configure CS2 (ST16552 / CHAN B) */
+	sysOutLong((membaseCsr + P9030_LAS2BA),  0x00800001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS2RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);		/* enable 256 Byte */
+	/* remap CS2 (ST16552 / CHAN B) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
+
+	/* configure CS3 (BCSR) */
+	sysOutLong((membaseCsr + P9030_LAS3BA),  0x00C00001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS3RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80);		/* 9 wait states */
+	sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);		/* enable 256 Byte */
+	/* remap CS3 (DISPLAY and BCSR) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
+}
+
+void sysOutLong(ulong address, ulong value)
+{
+	*(ulong*)address = cpu_to_le32(value);
+}
diff --git a/u-boot/board/cpu86/Makefile b/u-boot/board/cpu86/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/cpu86/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cpu86/cpu86.c b/u-boot/board/cpu86/cpu86.c
new file mode 100644
index 0000000..bc7ebfe
--- /dev/null
+++ b/u-boot/board/cpu86/cpu86.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu86.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 32 * 1024 * 1024;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
diff --git a/u-boot/board/cpu86/cpu86.h b/u-boot/board/cpu86/cpu86.h
new file mode 100644
index 0000000..ca0c39f
--- /dev/null
+++ b/u-boot/board/cpu86/cpu86.h
@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU86__
+#define __BOARD_CPU86__
+
+#include <config.h>
+
+#define REG8(x)			(*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT		0x01
+#define CPU86_BCR_FWRE		0x02
+
+#endif /* __BOARD_CPU86__ */
diff --git a/u-boot/board/cpu86/flash.c b/u-boot/board/cpu86/flash.c
new file mode 100644
index 0000000..8135780
--- /dev/null
+++ b/u-boot/board/cpu86/flash.c
@@ -0,0 +1,615 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu86.h"
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write identify command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+	short i;
+	uchar vendor, devid;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x90;
+
+	udelay(1000);
+
+	vendor = addr[0];
+	devid = addr[1] & 0xff;
+
+	/* only support AMD */
+	if (vendor != 0x01) {
+		return 0;
+	}
+
+	vendor &= 0xf;
+	devid &= 0xff;
+
+	if (devid == AMD_ID_F040B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 8;
+		info->size         = info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F080B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 16;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F016D) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 32;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else {
+		printf ("## Unknown Flash Type: %02x\n", devid);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* sector base address */
+		info->start[i] = base + i * (info->size / info->sector_count);
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_char *)info->start[0];
+		addr[0] = 0xF0; /* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	unsigned long size_b1 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Disable flash protection */
+	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
+
+	if (size_b0 > 0 || size_b1 > 0) {
+
+		printf("(");
+
+		if (size_b0 > 0) {
+			puts ("Bank#1 - ");
+			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+		}
+
+		if (size_b1 > 0) {
+			puts ("Bank#2 - ");
+			print_size (size_b1, ") ");
+		}
+	}
+	else {
+		printf ("## No FLASH found.\n");
+		return 0;
+	}
+	/* protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
+	if (size_b1) {
+		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
+		 * but we shouldn't protect it.
+		 */
+
+		flash_protect  (FLAG_PROTECT_SET,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+		);
+	}
+#else
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+#endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
+	if (size_b1) {
+		flash_protect (FLAG_PROTECT_SET,
+				CONFIG_ENV_ADDR,
+				CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
+	}
+# else
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 Mbit, bottom sector)\n");
+		break;
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (info->size < 0x100000)
+		printf ("  Size: %ld KB in %d Sectors\n",
+				info->size >> 10, info->sector_count);
+	else
+		printf ("  Size: %ld MB in %d Sectors\n",
+				info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Check the type of erased flash
+	 */
+	if (info->flash_id >> 16 == 0x1) {
+		/* Erase AMD flash
+		 */
+		l_sect = -1;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+		addr[0x0555] = 0x80;
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect<=s_last; sect++) {
+			if (info->protect[sect] == 0) { /* not protected */
+				addr = (vu_char *)(info->start[sect]);
+				addr[0] = 0x30;
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto AMD_DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (vu_char *)(info->start[l_sect]);
+		while ((addr[0] & 0x80) != 0x80) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {      /* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+AMD_DONE:
+		/* reset to read mode */
+		addr = (volatile unsigned char *)info->start[0];
+		addr[0] = 0xF0;     /* reset bank */
+
+	} else {
+		/* Erase Intel flash
+		 */
+
+		/* Start erase on unprotected sectors
+		 */
+		for (sect = s_first; sect <= s_last; sect++) {
+			volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+			start = get_timer (0);
+			last = start;
+			if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+				flag = disable_interrupts ();
+
+				/* Erase the block
+				 */
+				addr[0] = 0x00200020;
+				addr[1] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				addr[1] = 0x00D000D0;
+
+				/* re-enable interrupts if necessary
+				 */
+				if (flag)
+					enable_interrupts ();
+
+				/* wait at least 80us - let's wait 1 ms
+				 */
+				udelay (1000);
+
+				last = start;
+				while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+						printf ("Timeout (erase suspended!)\n");
+						/* Suspend erase
+						 */
+						addr[0] = 0x00B000B0;
+						addr[1] = 0x00B000B0;
+						goto DONE;
+					}
+					/* show that we're waiting
+					 */
+					if ((now - last) > 1000) {	/* every second */
+						serial_putc ('.');
+						last = now;
+					}
+				}
+				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+					printf ("*** ERROR: erase failed!\n");
+					goto DONE;
+				}
+			}
+			/* Clear status register and reset to read mode
+			 */
+			addr[0] = 0x00500050;
+			addr[1] = 0x00500050;
+			addr[0] = 0x00FF00FF;
+			addr[1] = 0x00FF00FF;
+		}
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, rc, cc = cnt, res = 0;
+
+	if (info->flash_id >> 16 == 0x1) {
+
+		/* Write to AMD 8-bit flash
+		 */
+		while (cnt > 0) {
+			if ((rc = write_byte(info, addr, *src)) != 0) {
+				return (rc);
+			}
+			addr++;
+			src++;
+			cnt--;
+		}
+
+		return (0);
+	} else {
+
+		/* Write to Intel 64-bit flash
+		 */
+		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+			l = (addr & 3);
+			addr &= ~3;
+
+			for (i = 0; i < 4; i++) {
+				v = (v << 8) + (i < l || i - l >= cc ?
+					*((unsigned char *) addr + i) : *src++);
+			}
+
+			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/cpu87/Makefile b/u-boot/board/cpu87/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/cpu87/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cpu87/cpu87.c b/u-boot/board/cpu87/cpu87.c
new file mode 100644
index 0000000..057a34c
--- /dev/null
+++ b/u-boot/board/cpu87/cpu87.c
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu87.h"
+#include <pci.h>
+#include <netdev.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong size8, size9, size10;
+#endif
+	long psize;
+
+	psize = 32 * 1024 * 1024;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	psize = max(size8,max(size9,size10));
+
+	if (psize == size8) {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	} else if (psize == size9){
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:9COL) ");
+	} else
+		printf ("(60x:10COL) ");
+
+#endif	/* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/cpu87/cpu87.h b/u-boot/board/cpu87/cpu87.h
new file mode 100644
index 0000000..45cb853
--- /dev/null
+++ b/u-boot/board/cpu87/cpu87.h
@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU87__
+#define __BOARD_CPU87__
+
+#include <config.h>
+
+#define REG8(x)			(*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT		0x01
+#define CPU86_BCR_FWRE		0x02
+
+#endif /* __BOARD_CPU87__ */
diff --git a/u-boot/board/cpu87/flash.c b/u-boot/board/cpu87/flash.c
new file mode 100644
index 0000000..c35757b
--- /dev/null
+++ b/u-boot/board/cpu87/flash.c
@@ -0,0 +1,624 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu87.h"
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write identify command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+	short i;
+	uchar vendor, devid;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x90;
+
+	udelay(1000);
+
+	vendor = addr[0];
+	devid = addr[1] & 0xff;
+
+	/* only support AMD */
+	if (vendor != 0x01) {
+		return 0;
+	}
+
+	vendor &= 0xf;
+	devid &= 0xff;
+
+	if (devid == AMD_ID_F040B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 8;
+		info->size         = info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F080B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 16;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F016D) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 32;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else {
+		printf ("## Unknown Flash Type: %02x\n", devid);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* sector base address */
+		info->start[i] = base + i * (info->size / info->sector_count);
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_char *)info->start[0];
+		addr[0] = 0xF0; /* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	unsigned long size_b1 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Disable flash protection */
+	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
+
+	if (size_b0 > 0 || size_b1 > 0) {
+
+		printf("(");
+
+		if (size_b0 > 0) {
+			puts ("Bank#1 - ");
+			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+		}
+
+		if (size_b1 > 0) {
+			puts ("Bank#2 - ");
+			print_size (size_b1, ") ");
+		}
+	}
+	else {
+		printf ("## No FLASH found.\n");
+		return 0;
+	}
+	/* protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
+	if (size_b1) {
+		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
+		 * but we shouldn't protect it.
+		 */
+
+		flash_protect  (FLAG_PROTECT_SET,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+		);
+	}
+#else
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+#endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
+	if (size_b1) {
+		flash_protect (FLAG_PROTECT_SET,
+				CONFIG_ENV_ADDR,
+				CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
+	}
+# else
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (info->size < 0x100000)
+		printf ("  Size: %ld KB in %d Sectors\n",
+				info->size >> 10, info->sector_count);
+	else
+		printf ("  Size: %ld MB in %d Sectors\n",
+				info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Check the type of erased flash
+	 */
+	if (info->flash_id >> 16 == 0x1) {
+		/* Erase AMD flash
+		 */
+		l_sect = -1;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+		addr[0x0555] = 0x80;
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect<=s_last; sect++) {
+			if (info->protect[sect] == 0) { /* not protected */
+				addr = (vu_char *)(info->start[sect]);
+				addr[0] = 0x30;
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto AMD_DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (vu_char *)(info->start[l_sect]);
+		while ((addr[0] & 0x80) != 0x80) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {      /* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+AMD_DONE:
+		/* reset to read mode */
+		addr = (volatile unsigned char *)info->start[0];
+		addr[0] = 0xF0;     /* reset bank */
+
+	} else {
+		/* Erase Intel flash
+		 */
+
+		/* Start erase on unprotected sectors
+		 */
+		for (sect = s_first; sect <= s_last; sect++) {
+			volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+			start = get_timer (0);
+			last = start;
+			if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+				flag = disable_interrupts ();
+
+				/* Erase the block
+				 */
+				addr[0] = 0x00200020;
+				addr[1] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				addr[1] = 0x00D000D0;
+
+				/* re-enable interrupts if necessary
+				 */
+				if (flag)
+					enable_interrupts ();
+
+				/* wait at least 80us - let's wait 1 ms
+				 */
+				udelay (1000);
+
+				last = start;
+				while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+						printf ("Timeout (erase suspended!)\n");
+						/* Suspend erase
+						 */
+						addr[0] = 0x00B000B0;
+						addr[1] = 0x00B000B0;
+						goto DONE;
+					}
+					/* show that we're waiting
+					 */
+					if ((now - last) > 1000) {	/* every second */
+						serial_putc ('.');
+						last = now;
+					}
+				}
+				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+					printf ("*** ERROR: erase failed!\n");
+					goto DONE;
+				}
+			}
+			/* Clear status register and reset to read mode
+			 */
+			addr[0] = 0x00500050;
+			addr[1] = 0x00500050;
+			addr[0] = 0x00FF00FF;
+			addr[1] = 0x00FF00FF;
+		}
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, rc, cc = cnt, res = 0;
+
+	if (info->flash_id >> 16 == 0x1) {
+
+		/* Write to AMD 8-bit flash
+		 */
+		while (cnt > 0) {
+			if ((rc = write_byte(info, addr, *src)) != 0) {
+				return (rc);
+			}
+			addr++;
+			src++;
+			cnt--;
+		}
+
+		return (0);
+	} else {
+
+		/* Write to Intel 64-bit flash
+		 */
+		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+			l = (addr & 3);
+			addr &= ~3;
+
+			for (i = 0; i < 4; i++) {
+				v = (v << 8) + (i < l || i - l >= cc ?
+					*((unsigned char *) addr + i) : *src++);
+			}
+
+			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/cradle/Makefile b/u-boot/board/cradle/Makefile
new file mode 100644
index 0000000..18040c7
--- /dev/null
+++ b/u-boot/board/cradle/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cradle.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cradle/cradle.c b/u-boot/board/cradle/cradle.c
new file mode 100644
index 0000000..2bbf2d5
--- /dev/null
+++ b/u-boot/board/cradle/cradle.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+
+/* local prototypes */
+void set_led (int led, int color);
+void error_code_halt (int code);
+int init_sio (int led, unsigned long base);
+inline void cradle_outb (unsigned short val, unsigned long base,
+			 unsigned long reg);
+inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
+inline void sleep (int i);
+
+inline void
+/**********************************************************/
+sleep (int i)
+/**********************************************************/
+{
+	while (i--) {
+		udelay (1000000);
+	}
+}
+
+void
+/**********************************************************/
+error_code_halt (int code)
+/**********************************************************/
+{
+	while (1) {
+		led_code (code, RED);
+		sleep (1);
+		led_code (0, OFF);
+		sleep (1);
+	}
+}
+
+void
+/**********************************************************/
+led_code (int code, int color)
+/**********************************************************/
+{
+	int i;
+
+	code &= 0xf;		/* only 4 leds */
+
+	for (i = 0; i < 4; i++) {
+		if (code & (1 << i)) {
+			set_led (i, color);
+		} else {
+			set_led (i, OFF);
+		}
+	}
+}
+
+void
+/**********************************************************/
+set_led (int led, int color)
+/**********************************************************/
+{
+	int shift = led * 2;
+	unsigned long mask = 0x3 << shift;
+
+	writel(mask, GPCR2);	/* clear bits */
+	writel((color << shift), GPSR2);	/* set bits */
+	udelay (5000);
+}
+
+inline void
+/**********************************************************/
+cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
+/**********************************************************/
+{
+	*(volatile unsigned short *) (base + (reg * 2)) = val;
+}
+
+inline unsigned char
+/**********************************************************/
+cradle_inb (unsigned long base, unsigned long reg)
+/**********************************************************/
+{
+	unsigned short val;
+
+	val = *(volatile unsigned short *) (base + (reg * 2));
+	return (val & 0xff);
+}
+
+int
+/**********************************************************/
+init_sio (int led, unsigned long base)
+/**********************************************************/
+{
+	unsigned char val;
+
+	set_led (led, YELLOW);
+	val = cradle_inb (base, CRADLE_SIO_INDEX);
+	val = cradle_inb (base, CRADLE_SIO_INDEX);
+	if (val != 0) {
+		set_led (led, RED);
+		return -1;
+	}
+
+	/* map SCC2 to COM1 */
+	cradle_outb (0x01, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x00, base, CRADLE_SIO_DATA);
+
+	/* enable SCC2 extended regs */
+	cradle_outb (0x40, base, CRADLE_SIO_INDEX);
+	cradle_outb (0xa0, base, CRADLE_SIO_DATA);
+
+	/* enable SCC2 clock multiplier */
+	cradle_outb (0x51, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x04, base, CRADLE_SIO_DATA);
+
+	/* enable SCC2 */
+	cradle_outb (0x00, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x04, base, CRADLE_SIO_DATA);
+
+	/* map SCC2 DMA to channel 0 */
+	cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x09, base, CRADLE_SIO_DATA);
+
+	/* read ID from SIO to check operation */
+	cradle_outb (0xe4, base, 0x3f8 + 0x3);
+	val = cradle_inb (base, 0x3f8 + 0x0);
+	if ((val & 0xf0) != 0x20) {
+		set_led (led, RED);
+		/* disable SCC2 */
+		cradle_outb (0, base, CRADLE_SIO_INDEX);
+		cradle_outb (0, base, CRADLE_SIO_DATA);
+		return -1;
+	}
+	/* set back to bank 0 */
+	cradle_outb (0, base, 0x3f8 + 0x3);
+	set_led (led, GREEN);
+	return 0;
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_late_init (void)
+/**********************************************************/
+{
+	return (0);
+}
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	led_code (0xf, YELLOW);
+
+	/* arch number of HHP Cradle */
+	gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* Init SIOs to enable SCC2 */
+	udelay (100000);		/* delay makes it look neat */
+	init_sio (0, CRADLE_SIO1_PHYS);
+	udelay (100000);
+	init_sio (1, CRADLE_SIO2_PHYS);
+	udelay (100000);
+	init_sio (2, CRADLE_SIO3_PHYS);
+	udelay (100000);
+	set_led (3, GREEN);
+
+	return 1;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/cradle/flash.c b/u-boot/board/cradle/flash.c
new file mode 100644
index 0000000..b5635fb
--- /dev/null
+++ b/u-boot/board/cradle/flash.c
@@ -0,0 +1,359 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x400000
+#define MAIN_SECT_SIZE  0x20000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		case 1:
+			flashbase = PHYS_FLASH_2;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] =
+				flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i, j;
+
+	for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf ("28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf ("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			goto Done;
+			break;
+		}
+
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+		printf ("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) {
+				printf ("\n   ");
+			}
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while ((*addr & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			/* clear status register command */
+			*addr = 0x50;
+			/* reset to read mode */
+			*addr = 0xFF;
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* clear status register command */
+	*addr = 0x50;
+
+	/* program set-up command */
+	*addr = 0x40;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0xB0;
+			goto outahere;
+		}
+	}
+
+	if (val & 0x1A) {	/* check for error */
+		printf ("\nFlash write error %02x at address %08lx\n",
+			(int) val, (unsigned long) dest);
+		if (val & (1 << 3)) {
+			printf ("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if (val & (1 << 1)) {
+			printf ("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if (val & (1 << 4)) {
+			printf ("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+outahere:
+	/* read array command */
+	*addr = 0xFF;
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/cray/L1/L1.c b/u-boot/board/cray/L1/L1.c
new file mode 100644
index 0000000..d87b6ef
--- /dev/null
+++ b/u-boot/board/cray/L1/L1.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-i2c.h>
+#include <command.h>
+#include <rtc.h>
+#include <post.h>
+#include <net.h>
+#include <malloc.h>
+
+#define L1_MEMSIZE (32*1024*1024)
+
+/* the std. DHCP stufff */
+#define DHCP_ROUTER       3
+#define DHCP_NETMASK      1
+#define DHCP_BOOTFILE     67
+#define DHCP_ROOTPATH     17
+#define DHCP_HOSTNAME     12
+
+/* some extras used by CRAY
+ *
+ * on the server this looks like:
+ *
+ * option L1-initrd-image code 224 = string;
+ * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
+ */
+#define DHCP_L1_INITRD  224
+
+/* new, [better?] way via official vendor-extensions, defining an option
+ * space.
+ * on the server this looks like:
+ *
+ * option space CRAYL1;
+ * option CRAYL1.initrd     code 3 = string;
+ * ..etc...
+ */
+#define DHCP_VENDOR_SPECX   43
+#define DHCP_VX_INITRD       3
+#define DHCP_VX_BOOTCMD      4
+#define DHCP_VX_BOOTARGS     5
+#define DHCP_VX_ROOTDEV      6
+#define DHCP_VX_FROMFLASH    7
+#define DHCP_VX_BOOTSCRIPT   8
+#define DHCP_VX_RCFILE	     9
+#define DHCP_VX_MAGIC        10
+
+/* Things DHCP server can tellme about.  If there's no flash address, then
+ * they dont participate in 'update' to flash, and we force their values
+ * back to '0' every boot to be sure to get them fresh from DHCP.  Yes, I
+ * know this is a pain...
+ *
+ * If I get no bootfile, boot from flash.  If rootpath, use that.  If no
+ * rootpath use initrd in flash.
+ */
+typedef struct dhcp_item_s {
+	u8 dhcp_option;
+	u8 dhcp_vendor_option;
+	char *dhcpvalue;
+	char *envname;
+} dhcp_item_t;
+static dhcp_item_t Things[] = {
+	{DHCP_ROUTER, 0, NULL, "gateway"},
+	{DHCP_NETMASK, 0, NULL, "netmask"},
+	{DHCP_BOOTFILE, 0, NULL, "bootfile"},
+	{DHCP_ROOTPATH, 0, NULL, "rootpath"},
+	{DHCP_HOSTNAME, 0, NULL, "hostname"},
+	{DHCP_L1_INITRD, 0, NULL, "initrd"},
+/* and the other way.. */
+	{DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
+	{DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
+};
+
+#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
+
+extern char bootscript[];
+
+/* Here is the boot logic as HUSH script. Overridden by any TFP provided
+ * bootscript file.
+ */
+
+static void init_sdram (void);
+
+/* ------------------------------------------------------------------------- */
+int board_early_init_f (void)
+{
+	/* Running from ROM: global data is still READONLY */
+	init_sdram ();
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+int checkboard (void)
+{
+	return (0);
+}
+/* ------------------------------------------------------------------------- */
+
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+	char *s, *e;
+	image_header_t *hdr;
+	time_t timestamp;
+	struct rtc_time tm;
+	char bootcmd[32];
+
+	hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	timestamp = (time_t)image_get_time (hdr);
+	to_tm (timestamp, &tm);
+	printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d  %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
+
+#define FACTORY_SETTINGS 0xFFFC0000
+	if ((s = getenv ("ethaddr")) == NULL) {
+		e = (char *) (FACTORY_SETTINGS);
+		if (*(e + 0) != '0'
+			|| *(e + 1) != '0'
+			|| *(e + 2) != ':'
+			|| *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') {
+			printf ("No valid MAC address in flash location 0x3C0000!\n");
+		} else {
+			printf ("Factory MAC: %s\n", e);
+			setenv ("ethaddr", e);
+		}
+	}
+	sprintf (bootcmd,"source %X",(unsigned)bootscript);
+	setenv ("bootcmd", bootcmd);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+/* stubs so we can print dates w/o any nvram RTC.*/
+int rtc_get (struct rtc_time *tmp)
+{
+	return 0;
+}
+int rtc_set (struct rtc_time *tmp)
+{
+	return 0;
+}
+void rtc_reset (void)
+{
+	return;
+}
+
+/* ------------------------------------------------------------------------- */
+/*  Do sdram bank init in C so I can read it..no console to print to yet!
+ */
+static void init_sdram (void)
+{
+ unsigned long tmp;
+
+	/* write SDRAM bank 0 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	mtdcr (SDRAM0_CFGDATA, 0x00062001);
+
+/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.	*/
+/* To set the appropriate timings, we need to know the SDRAM speed.	*/
+/* We can use the PLB speed since the SDRAM speed is the same as	*/
+/* the PLB speed. The PLB speed is the FBK divider times the		*/
+/* 405GP reference clock, which on the L1 is 25MHz.			*/
+/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is	*/
+/* 150MHz; if FBK is 3, SDRAM is 150MHz.				*/
+
+	/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
+
+/* write SDRAM timing for 100MHz. */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	mtdcr (SDRAM0_CFGDATA, 0x0086400D);
+
+/* write SDRAM refresh interval register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	mtdcr (SDRAM0_CFGDATA, 0x05F00000);
+	udelay (200);
+
+/* sdram controller.*/
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	mtdcr (SDRAM0_CFGDATA, 0x90800000);
+	udelay (200);
+
+/* initially, disable ECC on all banks */
+	udelay (200);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	tmp &= 0xff0fffff;
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+	mtdcr (SDRAM0_CFGDATA, tmp);
+
+	return;
+}
+
+extern int memory_post_test (int flags);
+
+int testdram (void)
+{
+ unsigned long tmp;
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) L1_MEMSIZE;
+	uint *p;
+
+	if (getenv_f("booted",NULL,0) <= 0)
+	{
+		printf ("testdram..");
+	/*AA*/
+		for (p = pstart; p < pend; p++)
+			*p = 0xaaaaaaaa;
+		for (p = pstart; p < pend; p++) {
+			if (*p != 0xaaaaaaaa) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+						(uint) p, *p, 0xaaaaaaaa);
+				return 1;
+			}
+		}
+	/*55*/
+		for (p = pstart; p < pend; p++)
+			*p = 0x55555555;
+		for (p = pstart; p < pend; p++) {
+			if (*p != 0x55555555) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+						(uint) p, *p, 0x55555555);
+				return 1;
+			}
+		}
+	/*addr*/
+		for (p = pstart; p < pend; p++)
+			*p = (unsigned)p;
+		for (p = pstart; p < pend; p++) {
+			if (*p != (unsigned)p) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+						(uint) p, *p, (uint)p);
+				return 1;
+			}
+		}
+		printf ("Success. ");
+	}
+	printf ("Enable ECC..");
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	mtdcr (SDRAM0_CFGDATA, tmp);
+	udelay (600);
+	for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
+		;
+	udelay (400);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	tmp |= 0x00800000;
+	mtdcr (SDRAM0_CFGDATA, tmp);
+	udelay (400);
+	printf ("enabled.\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+static u8 *dhcp_env_update (u8 thing, u8 * pop)
+{
+	u8 i, oplen;
+
+	oplen = *(pop + 1);
+
+	if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) {
+		printf ("Whoops! failed to malloc space for DHCP thing %s\n",
+				Things[thing].envname);
+		return NULL;
+	}
+	for (i = 0; (i < oplen); i++)
+		if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ')
+			break;
+	*(Things[thing].dhcpvalue + i) = '\0';
+
+/* set env. */
+	if (Things[thing].envname)
+	{
+		setenv (Things[thing].envname, Things[thing].dhcpvalue);
+	}
+	return ((u8 *)(Things[thing].dhcpvalue));
+}
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+	u8 thing;
+
+/* ask for the things I want. */
+	*e++ = 55;					/* Parameter Request List */
+	*e++ = N_THINGS;
+	for (thing = 0; thing < N_THINGS; thing++)
+		*e++ = Things[thing].dhcp_option;
+	*e++ = 255;
+
+	return e;
+}
+
+/* ------------------------------------------------------------------------- */
+/* .. return NULL means it wasnt mine, non-null means I got it..*/
+u8 *dhcp_vendorex_proc (u8 * pop)
+{
+	u8 oplen, *sub_op, sub_oplen, *retval;
+	u8 thing = 0;
+
+	retval = NULL;
+	oplen = *(pop + 1);
+/* if pop is vender spec indicator, there are sub-options. */
+	if (*pop == DHCP_VENDOR_SPECX) {
+		for (sub_op = pop + 2;
+		     oplen && (sub_oplen = *(sub_op + 1));
+		     oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
+			for (thing = 0; thing < N_THINGS; thing++) {
+			    if (*sub_op == Things[thing].dhcp_vendor_option) {
+					if (!(retval = dhcp_env_update (thing, sub_op))) {
+						return NULL;
+					}
+			    }
+			}
+		}
+	} else {
+		for (thing = 0; thing < N_THINGS; thing++) {
+			if (*pop == Things[thing].dhcp_option)
+				if (!(retval = dhcp_env_update (thing, pop)))
+					return NULL;
+		}
+	}
+	return (pop);
+}
diff --git a/u-boot/board/cray/L1/L1.h b/u-boot/board/cray/L1/L1.h
new file mode 100644
index 0000000..c3a0b8f
--- /dev/null
+++ b/u-boot/board/cray/L1/L1.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip
+ *
+ *                          Start Address    Length
+ * +++++++++++++++++++++++++ 0xFFC0_0000     Start of Flash -----------------
+ * | Failsafe Linux Image  |	(1M)
+ * +=======================+ 0xFFD0_0000
+ * | (Reserved FlashFiles) |	(1M)
+ * +=======================+ 0xFFE0_0000
+ * | Failsafe RootFS       |	(1M)
+ * +=======================+ 0xFFF0_0000
+ * |                       |
+ * | U N U S E D           |
+ * |                       |
+ * +-----------------------+ 0xFFFD_0000	U-Boot image header (64 bytes)
+ * | environment settings  |	(64k)
+ * +-----------------------+ 0xFFFE_0000	U-Boot image header (64 bytes)
+ * | U-Boot                | 0xFFFE_0040    _start of U-Boot
+ * |                       | 0xFFFE_FFFC    reset vector - branch to _start
+ * +++++++++++++++++++++++++ 0xFFFF_FFFF     End of Flash -----------------
+ *****************************************************************************/
diff --git a/u-boot/board/cray/L1/Makefile b/u-boot/board/cray/L1/Makefile
new file mode 100644
index 0000000..d1a7a0b
--- /dev/null
+++ b/u-boot/board/cray/L1/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
+# built in the depend stage.  So... put bootscript.o here, not in OBJS
+$(LIB):	$(OBJS) $(SOBJS) $(obj)bootscript.o
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS) $(obj)bootscript.c \
+		$(obj)bootscript.image $(obj)bootscript.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+$(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o
+
+$(obj)bootscript.c: $(obj)bootscript.image
+	od -t x1 -v -A x $^ | awk -f x2c.awk > $@
+
+$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile
+	-$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cray/L1/bootscript.hush b/u-boot/board/cray/L1/bootscript.hush
new file mode 100644
index 0000000..f2f78ad
--- /dev/null
+++ b/u-boot/board/cray/L1/bootscript.hush
@@ -0,0 +1,117 @@
+# $Header$
+# hush bootscript for PPCBOOT on L1
+# note: all #s are in hex, do _NOT_ prefix it with 0x
+
+flash_rfs=ffc00000
+flash_krl=fff00000
+tftp_addr=100000
+tftp2_addr=1000000
+
+if printenv booted
+then
+	echo already booted before
+else
+	echo first boot in environment, create and save settings
+	setenv booted OK
+	saveenv
+fi
+
+setenv autoload no
+# clear out stale env stuff, so we get fresh from dhcp.
+for setting in initrd fromflash kernel rootfs rootpath
+do
+setenv $setting
+done
+
+dhcp
+
+# if host provides us with a different bootscript, us it.
+if printenv bootscript
+	then
+	tftp $tftp_addr $bootcript
+	if imi $tftp_addr
+	then
+		source $tftp_addr
+	fi
+fi
+
+# default base kernel arguments.
+setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
+
+# Have a kernel in flash?
+if imi $flash_krl
+then
+	echo ok kernel to boot from $flash_krl
+	setenv kernel $flash_krl
+else
+	echo no kernel to boot from $flash_krl, need tftp
+fi
+
+# Have a rootfs in flash? 
+echo test for SQUASHfs at $flash_rfs
+
+if imi $flash_rfs
+then
+	echo appears to be a good initrd image at base of flash OK
+	setenv rootfs $flash_rfs
+else
+	echo no image at base of flash, need nfsroot or initrd
+fi
+
+# I boot from flash if told to and I can.
+if printenv fromflash && printenv kernel && printenv rootfs
+then
+	echo booting entirely from flash
+	setenv bootargs root=/dev/ram0 rw $bootargs
+	bootm $kernel $rootfs
+	echo oh no failed so I try some other stuff
+fi
+
+# TFTP down a kernel
+if printenv bootfile
+then 
+	tftp $tftp_addr $bootfile
+	setenv kernel $tftp_addr
+	echo I will boot the TFTP kernel
+else
+	if printenv kernel
+	then
+		echo no bootfile specified, will use one from flash
+	else
+		setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
+		echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
+		tftp $tftp_addr $bootfile
+		setenv kernel $tftp_addr
+	fi
+fi
+
+# the rootfs.
+if printenv rootpath
+then
+	echo rootpath is $rootpath
+	if printenv initrd
+	then 
+		echo initrd is also specified, so use $initrd
+		tftp $tftp2_addr $initrd
+		setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
+		bootm $kernel $tftp2_addr
+	else
+		echo initrd is not specified, so use NFSROOT $rootpat
+		setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
+		bootm $kernel
+	fi
+else
+	echo we have no rootpath check for one in flash
+	if printenv rootfs
+	then
+		echo I will use the one in flash
+		setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+		bootm $kernel
+	else
+		setenv rootpath /export/crayl1
+		echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
+		setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+		bootm $kernel
+	fi
+fi
+reset
diff --git a/u-boot/board/cray/L1/flash.c b/u-boot/board/cray/L1/flash.c
new file mode 100644
index 0000000..a3d893e
--- /dev/null
+++ b/u-boot/board/cray/L1/flash.c
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Modified July 20, 2001
+ * Strip down to support ONLY the AMD29F032B.
+ * Dave Updegraff - Cray, Inc. dave@cray.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/* The flash chip we use... */
+#define AMD_ID_F032B	0x41	/* 29F032B ID  32 Mbit,64 64Kx8 sectors */
+#define FLASH_AM320B    0x0009
+
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Only one bank */
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
+	  {
+	    /* Setup offsets */
+	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+#if 0
+	    /* Monitor protection ON by default */
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				FLASH_BASE0_PRELIM,
+				FLASH_BASE0_PRELIM+monitor_flash_len-1,
+				&flash_info[0]);
+#endif
+	    size_b1 = 0 ;
+	    flash_info[0].size = size_b0;
+	  }
+
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[1];			/* device ID		*/
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_F032B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 64;
+		info->size = 0x0400000; /* => 4 MB */
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+	info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+    last  = start;
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return -1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    putc ('.');
+	    last = now;
+	}
+    }
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+		    printf("Erasing sector %p\n", addr2);
+
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    l_sect = sect;
+		    /*
+		     * Wait for each sector to complete, it's more
+		     * reliable.  According to AMD Spec, you must
+		     * issue all erase commands within a specified
+		     * timeout.  This has been seen to fail, especially
+		     * if printf()s are included (for debug)!!
+		     */
+		    wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/cray/L1/init.S b/u-boot/board/cray/L1/init.S
new file mode 100644
index 0000000..1662141
--- /dev/null
+++ b/u-boot/board/cray/L1/init.S
@@ -0,0 +1,140 @@
+/*------------------------------------------------------------------------------+ */
+/* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------------- */
+
+/*----------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*	Bank 0 - Flash and SRAM */
+/*	Bank 1 - NVRAM/RTC */
+/*	Bank 2 - Keyboard/Mouse controller */
+/*	Bank 3 - IR controller */
+/*	Bank 4 - not used */
+/*	Bank 5 - not used */
+/*	Bank 6 - not used */
+/*	Bank 7 - FPGA registers */
+/*-----------------------------------------------------------------------------#include <config.h> */
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
+/*	except for #1 which we use for DMA'ing to IOCA-like things, so the */
+/*	control registers to set that up are determined by what we've */
+/*	empirically discovered work there. */
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	/*------------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing */
+	    /* bank 0 timings. 200usec should be enough. */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*------------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+
+	/*---------------------------------------------------------------------- */
+	/* Peripheral Bank 0 (Flash) initialization */
+	/*---------------------------------------------------------------------- */
+		/* 0x7F8FFE80 slowest boot */
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,0x9B01
+	ori     r4,r4,0x5480
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,0xFFC5           /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   EBC0_CFGDATA,r4
+
+	blr
+
+	/*---------------------------------------------------------------------- */
+	/* Peripheral Bank 1 (NVRAM/RTC) initialization */
+		/* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
+		/* and we do DMA on it.  The ConfigurationRegister part is threfore */
+		/* almost arbitrary, except that our linux driver needs to know the */
+		/* address, but it can query, it.. */
+		/* */
+		/* The AccessParameter is CRITICAL, */
+		/* thouch, since it needs to agree with the electrical timings on the */
+		/* IOCA parallel interface.  That value is: 0x0185,4380 */
+		/* BurstModeEnable			BME=0 */
+		/* TransferWait				TWT=3 */
+		/* ChipSelectOnTiming		CSN=1 */
+		/* OutputEnableOnTimimg		OEN=1 */
+		/* WriteByteEnableOnTiming	WBN=1 */
+		/* WriteByteEnableOffTiming	WBF=0 */
+		/* TransferHold				TH=1 */
+		/* ReadyEnable				RE=1 */
+		/* SampleOnReady			SOR=1 */
+		/* ByteEnableMode			BEM=0 */
+		/* ParityEnable				PEN=0 */
+		/* all reserved bits=0 */
+	/*---------------------------------------------------------------------- */
+	/*---------------------------------------------------------------------- */
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,0x0185		/* hiword */
+	ori     r4,r4,0x4380	/* loword */
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB1CR
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,0xF001           /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   EBC0_CFGDATA,r4
+
+	blr
diff --git a/u-boot/board/cray/L1/patchme b/u-boot/board/cray/L1/patchme
new file mode 100644
index 0000000..e77ee7e
--- /dev/null
+++ b/u-boot/board/cray/L1/patchme
@@ -0,0 +1,30 @@
+# master confi.mk
+echo "CROSS_COMPILE = powerpc-linux-"	>>include/config.mk
+
+# patch the examples/Makefile to ignore return value from OBJCOPY
+sed  -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
+
+# add a built target for mkimage on the target architecture
+sed  -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
+
+cat <<EOF >>tools/makefile
+mkimage.ppc : mkimage.o.ppc crc32.o.ppc
+	powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
+	powerpc-linux-strip $@
+
+XFLAGS="-D__KERNEL__  -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
+mkimage.o.ppc: mkimage.c
+	powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+crc32.o.ppc: crc32.c
+	powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+EOF
+
+# make an image by default out of the u-boot image
+sed  -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
+cat <<EOF >>makefile
+u-boot.image:  u-boot.bin
+	tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
+
+EOF
diff --git a/u-boot/board/cray/L1/u-boot.lds.debug b/u-boot/board/cray/L1/u-boot.lds.debug
new file mode 100644
index 0000000..0e9cdcf
--- /dev/null
+++ b/u-boot/board/cray/L1/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/cray/L1/x2c.awk b/u-boot/board/cray/L1/x2c.awk
new file mode 100644
index 0000000..9235e6c
--- /dev/null
+++ b/u-boot/board/cray/L1/x2c.awk
@@ -0,0 +1,6 @@
+#!/bin/awk
+BEGIN { print "unsigned char bootscript[] = { \n"}
+{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
+  print ""
+}
+END { print "\n};\n" }
diff --git a/u-boot/board/csb226/Makefile b/u-boot/board/csb226/Makefile
new file mode 100644
index 0000000..b10c447
--- /dev/null
+++ b/u-boot/board/csb226/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= csb226.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/csb226/csb226.c b/u-boot/board/csb226/csb226.c
new file mode 100644
index 0000000..dd29e62
--- /dev/null
+++ b/u-boot/board/csb226/csb226.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
+ * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
+ * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+/**
+ * misc_init_r: - misc initialisation routines
+ */
+
+int misc_init_r(void)
+{
+#if 0
+	uchar *str;
+
+	/* determine if the software update key is pressed during startup */
+	/* not ported yet... */
+	if (GPLR0 & 0x00000800) {
+		printf("using bootcmd_normal (sw-update button not pressed)\n");
+		str = getenv("bootcmd_normal");
+	} else {
+		printf("using bootcmd_update (sw-update button pressed)\n");
+		str = getenv("bootcmd_update");
+	}
+
+	setenv("bootcmd",str);
+#endif
+	return 0;
+}
+
+
+/**
+ * board_init: - setup some data structures
+ *
+ * @return: 0 in case of success
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of CSB226 board */
+	gd->bd->bi_arch_number = MACH_TYPE_CSB226;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+/**
+ * csb226_set_led: - switch LEDs on or off
+ *
+ * @param led:   LED to switch (0,1,2)
+ * @param state: switch on (1) or off (0)
+ */
+
+void csb226_set_led(int led, int state)
+{
+	switch(led) {
+
+		case 0: if (state==1) {
+				writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
+			} else if (state==0) {
+				writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
+			}
+			break;
+
+		case 1: if (state==1) {
+				writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
+			} else if (state==0) {
+				writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
+			}
+			break;
+
+		case 2: if (state==1) {
+				writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
+			} else if (state==0) {
+				writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
+			}
+			break;
+	}
+
+	return;
+}
+
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	switch(status) {
+		case  1: csb226_set_led(0,1); break;
+		case  5: csb226_set_led(1,1); break;
+		case 15: csb226_set_led(2,1); break;
+	}
+
+	return;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/csb226/flash.c b/u-boot/board/csb226/flash.c
new file mode 100644
index 0000000..02ded1c
--- /dev/null
+++ b/u-boot/board/csb226/flash.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
+ * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+#define FLASH_BANK_SIZE 0x02000000
+#define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/**
+ * flash_init: - initialize data structures for flash chips
+ *
+ * @return: size of the flash
+ */
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+
+		switch (i) {
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+	return size;
+}
+
+
+/**
+ * flash_print_info: - print information about the flash situation
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i, j;
+
+	for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
+
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
+		}
+
+		printf("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+		printf("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) printf ("\n	");
+
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "	   ");
+		}
+		printf ("\n");
+		info++;
+	}
+}
+
+
+/**
+ * flash_erase: - erase flash sectors
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) prot++;
+	}
+
+	if (prot) return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) { /* not protected */
+			u32 * volatile addr = (u32 * volatile)(info->start[sect]);
+
+			/* erase sector:				    */
+			/* The strata flashs are aligned side by side on    */
+			/* the data bus, so we have to write the commands   */
+			/* to both chips here:				    */
+
+			*addr = 0x00200020;	/* erase setup */
+			*addr = 0x00D000D0;	/* erase confirm */
+
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = 0x00B000B0; /* suspend erase*/
+					*addr = 0x00FF00FF; /* read mode    */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+			*addr = 0x00500050; /* clear status register cmd.   */
+			*addr = 0x00FF00FF; /* reset to read mode	    */
+		}
+		printf("ok.\n");
+	}
+	if (ctrlc()) printf("User Interrupt!\n");
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked(10000);
+
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+/**
+ * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
+ */
+
+static int write_long (flash_info_t *info, ulong dest, ulong data)
+{
+	u32 * volatile addr = (u32 * volatile)dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* read array command - just for the case... */
+	*addr = 0x00FF00FF;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts();
+
+	/* clear status register command */
+	*addr = 0x00500050;
+
+	/* program set-up command */
+	*addr = 0x00400040;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while(((val = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0x00B000B0;
+			goto outahere;
+		}
+	}
+
+	/* check for errors */
+	if(val & 0x001A001A) {
+		printf("\nFlash write error %02x at address %08lx\n",
+			(int)val, (unsigned long)dest);
+		if(val & 0x00080008) {
+			printf("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if(val & 0x00020002) {
+			printf("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if(val & 0x00100010) {
+			printf("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr: where to copy to
+ * @param cnt:	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+/* "long" version, uses 32bit words */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ulong data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+
+		if ((rc = write_long(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((ulong*)src);
+		if ((rc = write_long(info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	return write_long(info, wp, data);
+}
diff --git a/u-boot/board/csb272/Makefile b/u-boot/board/csb272/Makefile
new file mode 100644
index 0000000..cfc8839
--- /dev/null
+++ b/u-boot/board/csb272/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+#COBJS	= $(BOARD).o flash.o
+#COBJS	= $(BOARD).o strataflash.o
+COBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/csb272/csb272.c b/u-boot/board/csb272/csb272.c
new file mode 100644
index 0000000..8b36127
--- /dev/null
+++ b/u-boot/board/csb272/csb272.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/ppc4xx-emac.h>
+
+void sdram_init(void);
+
+/*
+ * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
+ *
+ * CLKA output => Epson LCD Controller
+ * CLKB output => Not Connected
+ * CLKC output => Ethernet
+ * CLKD output => UART external clock
+ *
+ * Note: these values are obtained from device after init by micromonitor
+*/
+uchar pll_fs6377_regs[16] = {
+	0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
+	0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
+
+/*
+ * pll_init: Initialize AMIS IC FS6377-01 PLL
+ *
+ * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
+ *
+ */
+int pll_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	return  i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
+		(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
+}
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+	/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
+	(void) get_clocks();
+	pll_init();
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB272\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+phys_size_t initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in arch/powerpc/cpu/ppc4xx
+	 */
+	sdram_init();
+
+	tot_size = 0;
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+	/* AUTO neg */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+
+	/* LEDs     */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
+
+
+	return 0; /* success */
+}
diff --git a/u-boot/board/csb272/init.S b/u-boot/board/csb272/init.S
new file mode 100644
index 0000000..82c6fdb
--- /dev/null
+++ b/u-boot/board/csb272/init.S
@@ -0,0 +1,218 @@
+/******************************************************************************
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   EBC0_CFGADDR,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   EBC0_CFGDATA,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   SDRAM0_CFGADDR,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   SDRAM0_CFGDATA,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x007000c0)
+	mtdcr	CPC0_CR0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, CPC0_CR1
+	ori	r4, r4, 0x4000
+	mtdcr	CPC0_CR1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(EBC0_CFG, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(PB1AP, 0x02869200)*/
+	WDCR_EBC(PB1AP, 0x07869200)
+	WDCR_EBC(PB0CR, 0xfe0bc000)
+	/********************************************************************
+	 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
+	 *******************************************************************/
+	WDCR_EBC(PB1AP, 0x1f869200)
+	WDCR_EBC(PB1CR, 0xf0818000)
+	/********************************************************************
+	 * Memory Bank 2 (Epson S1D13506) initialization
+	 *******************************************************************/
+	WDCR_EBC(PB2AP, 0x05860300)
+	WDCR_EBC(PB2CR, 0xf045a000)
+	/********************************************************************
+	 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
+	 *******************************************************************/
+	WDCR_EBC(PB3AP, 0x0387d200)
+	WDCR_EBC(PB3CR, 0xf021c000)
+	/********************************************************************
+	 * Memory Bank 4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(PB4AP, 0)
+	WDCR_EBC(PB4CR, 0)
+	WDCR_EBC(PB5AP, 0)
+	WDCR_EBC(PB5CR, 0)
+	WDCR_EBC(PB6AP, 0)
+	WDCR_EBC(PB6CR, 0)
+	WDCR_EBC(PB7AP, 0)
+	WDCR_EBC(PB7CR, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
+	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(SDRAM0_TR, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
+	/* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(SDRAM0_CFG,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/u-boot/board/csb472/Makefile b/u-boot/board/csb472/Makefile
new file mode 100644
index 0000000..cfc8839
--- /dev/null
+++ b/u-boot/board/csb472/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+#COBJS	= $(BOARD).o flash.o
+#COBJS	= $(BOARD).o strataflash.o
+COBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/csb472/csb472.c b/u-boot/board/csb472/csb472.c
new file mode 100644
index 0000000..eac4408
--- /dev/null
+++ b/u-boot/board/csb472/csb472.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/ppc4xx-emac.h>
+
+void sdram_init(void);
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB472\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+phys_size_t initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in arch/powerpc/cpu/ppc4xx
+	 */
+	sdram_init();
+
+	tot_size = 0;
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+	/* AUTO neg */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+
+	/* LEDs     */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
+
+	return 0; /* success */
+}
diff --git a/u-boot/board/csb472/init.S b/u-boot/board/csb472/init.S
new file mode 100644
index 0000000..e00b5f5
--- /dev/null
+++ b/u-boot/board/csb472/init.S
@@ -0,0 +1,214 @@
+/******************************************************************************
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   EBC0_CFGADDR,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   EBC0_CFGDATA,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   SDRAM0_CFGADDR,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   SDRAM0_CFGDATA,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x00c01030)
+	mtdcr	CPC0_CR0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, CPC0_CR1
+	ori	r4, r4, 0x4000
+	mtdcr	CPC0_CR1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(EBC0_CFG, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(PB1AP, 0x03055200)*/
+	/*WDCR_EBC(PB1AP, 0x04055200)*/
+	WDCR_EBC(PB1AP, 0x08055200)
+	WDCR_EBC(PB0CR, 0xff87a000)
+	/********************************************************************
+	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(PB3AP, 0x07869200)*/
+	WDCR_EBC(PB3AP, 0x04055200)
+	WDCR_EBC(PB3CR, 0xf081c000)
+	/********************************************************************
+	 * Memory Bank 1,2,4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(PB1AP, 0)
+	WDCR_EBC(PB1CR, 0)
+	WDCR_EBC(PB2AP, 0)
+	WDCR_EBC(PB2CR, 0)
+	WDCR_EBC(PB4AP, 0)
+	WDCR_EBC(PB4CR, 0)
+	WDCR_EBC(PB5AP, 0)
+	WDCR_EBC(PB5CR, 0)
+	WDCR_EBC(PB6AP, 0)
+	WDCR_EBC(PB6CR, 0)
+	WDCR_EBC(PB7AP, 0)
+	WDCR_EBC(PB7CR, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
+	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(SDRAM0_TR, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
+	/* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(SDRAM0_CFG,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/u-boot/board/csb637/Makefile b/u-boot/board/csb637/Makefile
new file mode 100644
index 0000000..a5484ae
--- /dev/null
+++ b/u-boot/board/csb637/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= csb637.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/csb637/config.mk b/u-boot/board/csb637/config.mk
new file mode 100644
index 0000000..e2cc8a6
--- /dev/null
+++ b/u-boot/board/csb637/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23fc0000
diff --git a/u-boot/board/csb637/csb637.c b/u-boot/board/csb637/csb637.c
new file mode 100644
index 0000000..d7fdcc4
--- /dev/null
+++ b/u-boot/board/csb637/csb637.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <netdev.h>
+#include <asm/io.h>
+#if defined(CONFIG_DRIVER_ETHER)
+#include <at91rm9200_net.h>
+#include <bcm5221.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of CSB637-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_CSB637;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init		 = bcm5221_InitPhy;
+	p_phyops->IsPhyConnected = bcm5221_IsPhyConnected;
+	p_phyops->GetLinkSpeed	 = bcm5221_GetLinkSpeed;
+	p_phyops->AutoNegotiate	 = bcm5221_AutoNegotiate;
+}
+
+#endif
+#endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/u-boot/board/cu824/Makefile b/u-boot/board/cu824/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/cu824/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/cu824/README b/u-boot/board/cu824/README
new file mode 100644
index 0000000..cc0d207
--- /dev/null
+++ b/u-boot/board/cu824/README
@@ -0,0 +1,453 @@
+ppcboot for a CU824 board
+---------------------------
+
+CU824 has two banks of flash 8MB each. In board's notation, bank 0 is
+the one at the address of 0xFF800000 and bank 1 is the one at the
+address of 0xFF000000. On power-up the processor jumps to the address
+of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus,
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is not embedded in the U-Boot code
+and is located in flash separately from U-Boot, at the address of
+0xFF008000.
+
+
+U-Boot test results
+--------------------
+
+x.x Operation on all available serial consoles
+
+x.x.x CONFIG_CONS_INDEX 1
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>he
+go      - start application at address 'addr'
+run     - run commands in an environment variable
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+tftpboot- boot image via network using TFTP protocol
+	       and env variables ipaddr and serverip
+rarpboot- boot image via network using RARP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+loads   - load S-Record file over serial line
+loadb   - load binary file over serial line (kermit mode)
+md      - memory display
+mm      - memory modify (auto-incrementing)
+nm      - memory modify (constant address)
+mw      - memory write (fill)
+cp      - memory copy
+cmp     - memory compare
+crc32   - checksum calculation
+base    - print or set address offset
+printenv- print environment variables
+setenv  - set environment variables
+saveenv - save environment variables to persistent storage
+protect - enable or disable FLASH write protection
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+bdinfo  - print Board Info structure
+iminfo  - print header information for application image
+coninfo - print console devices and informations
+loop    - infinite loop on address range
+mtest   - simple RAM test
+icache  - enable or disable instruction cache
+dcache  - enable or disable data cache
+reset   - Perform RESET of the CPU
+echo    - echo args to console
+version - print monitor version
+help    - print online help
+?       - alias for 'help'
+=>
+
+
+x.x.x CONFIG_CONS_INDEX 2
+
+**** NOT TESTED ****
+
+x.x Flash Driver Operation
+
+x.x.x Erase Operation
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=>md ff000000
+ff000000: 27051956 70706362 6f6f7420 302e382e    '..Vppcboot 0.8.
+ff000010: 3320284d 61792031 31203230 3031202d    3 (May 11 2001 -
+ff000020: 2031343a 35373a30 33290000 00000000     14:57:03)......
+ff000030: 00000000 00000000 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: 00000000 00000000 00000000 00000000    ................
+ff000090: 00000000 00000000 00000000 00000000    ................
+ff0000a0: 00000000 00000000 00000000 00000000    ................
+ff0000b0: 00000000 00000000 00000000 00000000    ................
+ff0000c0: 00000000 00000000 00000000 00000000    ................
+ff0000d0: 00000000 00000000 00000000 00000000    ................
+ff0000e0: 00000000 00000000 00000000 00000000    ................
+ff0000f0: 00000000 00000000 00000000 00000000    ................
+=>erase ff000000 ff007fff
+Erase Flash from 0xff000000 to 0xff007fff
+ done
+Erased 1 sectors
+=>md ff000000
+ff000000: ffffffff ffffffff ffffffff ffffffff    ................
+ff000010: ffffffff ffffffff ffffffff ffffffff    ................
+ff000020: ffffffff ffffffff ffffffff ffffffff    ................
+ff000030: ffffffff ffffffff ffffffff ffffffff    ................
+ff000040: ffffffff ffffffff ffffffff ffffffff    ................
+ff000050: ffffffff ffffffff ffffffff ffffffff    ................
+ff000060: ffffffff ffffffff ffffffff ffffffff    ................
+ff000070: ffffffff ffffffff ffffffff ffffffff    ................
+ff000080: ffffffff ffffffff ffffffff ffffffff    ................
+ff000090: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000f0: ffffffff ffffffff ffffffff ffffffff    ................
+=>
+
+x.x.x Information
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=>
+=>flinfo
+
+Bank # 1: Intel: 28F160F3B (16Mbit)
+  Size: 8 MB in 39 Sectors
+  Sector Start Addresses:
+    FF000000      FF008000 (RO) FF010000      FF018000      FF020000
+    FF028000      FF030000      FF038000      FF040000      FF080000
+    FF0C0000      FF100000      FF140000      FF180000      FF1C0000
+    FF200000      FF240000      FF280000      FF2C0000      FF300000
+    FF340000      FF380000      FF3C0000      FF400000      FF440000
+    FF480000      FF4C0000      FF500000      FF540000      FF580000
+    FF5C0000      FF600000      FF640000      FF680000      FF6C0000
+    FF700000      FF740000      FF780000      FF7C0000
+
+Bank # 2: Intel: 28F160F3B (16Mbit)
+  Size: 8 MB in 39 Sectors
+  Sector Start Addresses:
+    FF800000      FF808000      FF810000      FF818000      FF820000
+    FF828000      FF830000      FF838000      FF840000      FF880000
+    FF8C0000      FF900000      FF940000      FF980000      FF9C0000
+    FFA00000      FFA40000      FFA80000      FFAC0000      FFB00000
+    FFB40000      FFB80000      FFBC0000      FFC00000      FFC40000
+    FFC80000      FFCC0000      FFD00000      FFD40000      FFD80000
+    FFDC0000      FFE00000      FFE40000      FFE80000      FFEC0000
+    FFF00000 (RO) FFF40000      FFF80000      FFFC0000
+=>
+
+x.x.x Flash Programming
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=>
+=>cp 0 ff000000 20
+Copy to Flash... done
+=>md 0
+00000000: 0ec08ce0 03f9800c 00000001 040c0000    ................
+00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00    ................
+00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0    ...X......4...4.
+00000030: 03fcd5bc 03fcdabc 00000000 00000000    ................
+00000040: 00000000 00000000 00000000 00000000    ................
+00000050: 00000000 00000000 00000000 00000000    ................
+00000060: 00000000 00000000 00000000 00000000    ................
+00000070: 00000000 00000000 00000000 00000000    ................
+00000080: 00000000 00000000 00000000 00000000    ................
+00000090: 00000000 00000000 00000000 00000000    ................
+000000a0: 00000000 00000000 00000000 00000000    ................
+000000b0: 00000000 00000000 00000000 00000000    ................
+000000c0: 00000000 00000000 00000000 00000000    ................
+000000d0: 00000000 00000000 00000000 00000000    ................
+000000e0: 00000000 00000000 00000000 00000000    ................
+000000f0: 00000000 00000000 00000000 00000000    ................
+=>md ff000000
+ff000000: 0ec08ce0 03f9800c 00000001 040c0000    ................
+ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00    ................
+ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0    ...X......4...4.
+ff000030: 03fcd5bc 03fcdabc 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: ffffffff ffffffff ffffffff ffffffff    ................
+ff000090: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000f0: ffffffff ffffffff ffffffff ffffffff    ................
+=>
+
+x.x.x Storage of environment variables in flash
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>printenv
+bootargs=
+bootcmd=bootm FE020000
+bootdelay=5
+baudrate=9600
+ipaddr=192.168.4.2
+serverip=192.168.4.1
+ethaddr=00:40:42:01:00:a0
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 167/32764 bytes
+=>setenv myvar 1234
+=>save_env
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=>reset
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>printenv
+bootargs=
+bootcmd=bootm FE020000
+bootdelay=5
+baudrate=9600
+ipaddr=192.168.4.2
+serverip=192.168.4.1
+ethaddr=00:40:42:01:00:a0
+myvar=1234
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 178/32764 bytes
+=>
+
+x.x Image Download and run over serial port
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>mw 40000 0 10000
+=>md 40000
+00040000: 00000000 00000000 00000000 00000000    ................
+00040010: 00000000 00000000 00000000 00000000    ................
+00040020: 00000000 00000000 00000000 00000000    ................
+00040030: 00000000 00000000 00000000 00000000    ................
+00040040: 00000000 00000000 00000000 00000000    ................
+00040050: 00000000 00000000 00000000 00000000    ................
+00040060: 00000000 00000000 00000000 00000000    ................
+00040070: 00000000 00000000 00000000 00000000    ................
+00040080: 00000000 00000000 00000000 00000000    ................
+00040090: 00000000 00000000 00000000 00000000    ................
+000400a0: 00000000 00000000 00000000 00000000    ................
+000400b0: 00000000 00000000 00000000 00000000    ................
+000400c0: 00000000 00000000 00000000 00000000    ................
+000400d0: 00000000 00000000 00000000 00000000    ................
+000400e0: 00000000 00000000 00000000 00000000    ................
+000400f0: 00000000 00000000 00000000 00000000    ................
+=>loads
+## Ready for S-Record download ...
+
+(Back at xpert.denx.de)
+[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0
+[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c
+Connecting to /dev/ttyS0, speed 9600.
+The escape character is Ctrl-\ (ASCII 28, FS)
+Type the escape character followed by C to get back,
+or followed by ? to see other options.
+md 40000
+00040000: 00018148 9421ffe0 7c0802a6 bf61000c    ...H.!..|....a..
+00040010: 90010024 48000005 7fc802a6 801effe8    ...$H...........
+00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378    ....|..x.?.8|.#x
+00040030: 807e8000 7cbd2b78 80090010 3b600000    .~..|.+x....;`..
+00040040: 7c0803a6 4e800021 813f0038 7f84e378    |...N..!.?.8...x
+00040050: 807e8004 80090010 7c0803a6 4e800021    .~......|...N..!
+00040060: 7c1be000 4181003c 80bd0000 813f0038    |...A..<.....?.8
+00040070: 3bbd0004 2c050000 40820008 80be8008    ;...,...@.......
+00040080: 80090010 7f64db78 807e800c 3b7b0001    .....d.x.~..;{..
+00040090: 7c0803a6 4e800021 7c1be000 4081ffcc    |...N..!|...@...
+000400a0: 813f0038 807e8010 80090010 7c0803a6    .?.8.~......|...
+000400b0: 4e800021 813f0038 80090004 7c0803a6    N..!.?.8....|...
+000400c0: 4e800021 2c030000 4182ffec 813f0038    N..!,...A....?.8
+000400d0: 80090000 7c0803a6 4e800021 813f0038    ....|...N..!.?.8
+000400e0: 807e8014 80090010 7c0803a6 4e800021    .~......|...N..!
+000400f0: 38600000 80010024 7c0803a6 bb61000c    8`.....$|....a..
+=>go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+=>
+
+x.x Image download and run over ethernet interface
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>mw 40000 0 10000
+=>md 40000
+00040000: 00000000 00000000 00000000 00000000    ................
+00040010: 00000000 00000000 00000000 00000000    ................
+00040020: 00000000 00000000 00000000 00000000    ................
+00040030: 00000000 00000000 00000000 00000000    ................
+00040040: 00000000 00000000 00000000 00000000    ................
+00040050: 00000000 00000000 00000000 00000000    ................
+00040060: 00000000 00000000 00000000 00000000    ................
+00040070: 00000000 00000000 00000000 00000000    ................
+00040080: 00000000 00000000 00000000 00000000    ................
+00040090: 00000000 00000000 00000000 00000000    ................
+000400a0: 00000000 00000000 00000000 00000000    ................
+000400b0: 00000000 00000000 00000000 00000000    ................
+000400c0: 00000000 00000000 00000000 00000000    ................
+000400d0: 00000000 00000000 00000000 00000000    ................
+000400e0: 00000000 00000000 00000000 00000000    ................
+000400f0: 00000000 00000000 00000000 00000000    ................
+=>tftpboot 40000 hello_world.bin
+ARP broadcast 1
+TFTP from server 192.168.4.1; our IP address is 192.168.4.2
+Filename 'hello_world.bin'.
+Load address: 0x40000
+Loading: #############
+done
+Bytes transferred = 65912 (10178 hex)
+=>md 40000
+00040000: 00018148 9421ffe0 7c0802a6 bf61000c    ...H.!..|....a..
+00040010: 90010024 48000005 7fc802a6 801effe8    ...$H...........
+00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378    ....|..x.?.8|.#x
+00040030: 807e8000 7cbd2b78 80090010 3b600000    .~..|.+x....;`..
+00040040: 7c0803a6 4e800021 813f0038 7f84e378    |...N..!.?.8...x
+00040050: 807e8004 80090010 7c0803a6 4e800021    .~......|...N..!
+00040060: 7c1be000 4181003c 80bd0000 813f0038    |...A..<.....?.8
+00040070: 3bbd0004 2c050000 40820008 80be8008    ;...,...@.......
+00040080: 80090010 7f64db78 807e800c 3b7b0001    .....d.x.~..;{..
+00040090: 7c0803a6 4e800021 7c1be000 4081ffcc    |...N..!|...@...
+000400a0: 813f0038 807e8010 80090010 7c0803a6    .?.8.~......|...
+000400b0: 4e800021 813f0038 80090004 7c0803a6    N..!.?.8....|...
+000400c0: 4e800021 2c030000 4182ffec 813f0038    N..!,...A....?.8
+000400d0: 80090000 7c0803a6 4e800021 813f0038    ....|...N..!.?.8
+000400e0: 807e8014 80090010 7c0803a6 4e800021    .~......|...N..!
+000400f0: 38600000 80010024 7c0803a6 bb61000c    8`.....$|....a..
+=>go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+=>
diff --git a/u-boot/board/cu824/cu824.c b/u-boot/board/cu824/cu824.c
new file mode 100644
index 0000000..720c56f
--- /dev/null
+++ b/u-boot/board/cu824/cu824.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2001-2006
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <pci.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOARD_REV_REG 0xFE80002B
+
+int checkboard (void)
+{
+	char  revision = *(volatile char *)(BOARD_REV_REG);
+	char  buf[32];
+
+	puts ("Board: CU824 ");
+	printf("Revision %d ", revision);
+	printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk));
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1,  mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/cu824/flash.c b/u-boot/board/cu824/flash.c
new file mode 100644
index 0000000..bd0f8d3
--- /dev/null
+++ b/u-boot/board/cu824/flash.c
@@ -0,0 +1,486 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x40000
+#define PARAM_SECT_SIZE 0x8000
+
+#define BOARD_CTRL_REG 0xFE800013
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static int write_data (flash_info_t *info, ulong dest, ulong *data);
+static void write_via_fpu(vu_long *addr, ulong *data);
+static __inline__ unsigned long get_msr(void);
+static __inline__ void set_msr(unsigned long msr);
+
+/*---------------------------------------------------------------------*/
+#undef	DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+    volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG);
+
+    DEBUGF("Write protect was: 0x%02X\n", *bcr);
+    *bcr &= 0x1;	/* FWPT must be 0  */
+    *bcr |= 0x6;	/* FWP0 = FWP1 = 1 */
+    DEBUGF("Write protect is:  0x%02X\n", *bcr);
+
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+	vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+	addr[0] = 0x00900090;
+
+	DEBUGF ("Flash bank # %d:\n"
+		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+		i,
+		(ulong)(&addr[0]), addr[0],
+		(ulong)(&addr[2]), addr[2]);
+
+	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B))
+	{
+	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				     (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
+	} else {
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+	    addr[0] = 0xFFFFFFFF;
+	    goto Done;
+	}
+
+	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+	addr[0] = 0xFFFFFFFF;
+
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+	for (j = 0; j < flash_info[i].sector_count; j++) {
+		if (j <= 7) {
+			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
+						 i * FLASH_BANK_SIZE +
+						 j * PARAM_SECT_SIZE;
+		} else {
+			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
+						 i * FLASH_BANK_SIZE +
+						 (j - 7)*MAIN_SECT_SIZE;
+		}
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
+    flash_protect(FLAG_PROTECT_SET,
+	      CONFIG_SYS_MONITOR_BASE,
+	      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+	      &flash_info[1]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+	      CONFIG_SYS_MONITOR_BASE,
+	      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+	      &flash_info[0]);
+#endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
+    flash_protect(FLAG_PROTECT_SET,
+	      CONFIG_ENV_ADDR,
+	      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+	      &flash_info[1]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+	      CONFIG_ENV_ADDR,
+	      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+	      &flash_info[0]);
+#endif
+#endif
+
+Done:
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch ((i = info->flash_id & FLASH_VENDMASK)) {
+	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor 0x%04x ", i);
+		break;
+	}
+
+	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+	case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
+		printf ("28F160F3B (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type 0x%04x\n", i);
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+		info - &flash_info[0], s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			DEBUGF ("Erase sect %d @ 0x%08lX\n",
+				sect, (ulong)addr);
+
+			/* Disable interrupts which might cause a timeout
+			 * here.
+			 */
+			flag = disable_interrupts();
+
+			addr[0] = 0x00500050;	/* clear status register */
+			addr[0] = 0x00200020;	/* erase setup */
+			addr[0] = 0x00D000D0;	/* erase confirm */
+
+			addr[1] = 0x00500050;	/* clear status register */
+			addr[1] = 0x00200020;	/* erase setup */
+			addr[1] = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((addr[0] & 0x00800080) != 0x00800080) ||
+			       ((addr[1] & 0x00800080) != 0x00800080) ) {
+				if ((now=get_timer(start)) >
+					   CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					addr[0] = 0x00B000B0; /* suspend erase */
+					addr[0] = 0x00FF00FF; /* to read mode  */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {  /* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			addr[0] = 0x00FF00FF;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	8	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, cp, msr;
+	int l, rc, i;
+	ulong data[2];
+	ulong *datah = &data[0];
+	ulong *datal = &data[1];
+
+	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+		addr, (ulong)src, cnt);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	msr = get_msr();
+	set_msr(msr | MSR_FP);
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		*datah = *datal = 0;
+
+		for (i = 0, cp = wp; i < l; i++, cp++) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+						((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | (*(uchar *)cp);
+		}
+		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+			char tmp;
+
+			tmp = *src;
+
+			src++;
+
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+						((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | tmp;
+
+			--cnt; ++cp;
+		}
+
+		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+						((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datah << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			set_msr(msr);
+			return (rc);
+		}
+
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		*datah = *(ulong *)src;
+		*datal = *(ulong *)(src + 4);
+		if ((rc = write_data(info, wp, data)) != 0) {
+			set_msr(msr);
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+		src += FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		set_msr(msr);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	*datah = *datal = 0;
+	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+		char tmp;
+
+		tmp = *src;
+
+		src++;
+
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | tmp;
+
+		--cnt;
+	}
+
+	for (; i < FLASH_WIDTH; ++i, ++cp) {
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | (*(uchar *)cp);
+	}
+
+	rc = write_data(info, wp, data);
+	set_msr(msr);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong *data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((addr[0] & data[0]) != data[0]) ||
+	    ((addr[1] & data[1]) != data[1]) ) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0] = 0x00400040;		/* write setup */
+	write_via_fpu(addr, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((addr[0] & 0x00800080) != 0x00800080) ||
+	       ((addr[1] & 0x00800080) != 0x00800080) ) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			addr[0] = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	addr[0] = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu(vu_long *addr, ulong *data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+}
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr(void)
+{
+    unsigned long msr;
+
+    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+    return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
diff --git a/u-boot/board/dave/B2/B2.c b/u-boot/board/dave/B2/B2.c
new file mode 100644
index 0000000..096ebbd
--- /dev/null
+++ b/u-boot/board/dave/B2/B2.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialization
+ */
+
+int board_init (void)
+{
+	u32 temp;
+
+	/* Configuration Port Control Register*/
+	/* Port A */
+	PCONA = 0x3ff;
+
+	/* Port B */
+	PCONB = 0xff;
+	PDATB = 0xFFFF;
+
+	/* Port C */
+	/*
+	PCONC = 0xff55ff15;
+	PDATC = 0x0;
+	PUPC = 0xffff;
+	*/
+
+	/* Port D */
+	/*
+	PCOND = 0xaaaa;
+	PUPD = 0xff;
+	*/
+
+	/* Port E */
+	PCONE = 0x0001aaa9;
+	PDATE = 0x0;
+	PUPE = 0xff;
+
+	/* Port F */
+	PCONF = 0x124955;
+	PDATF  = 0xff; /* B2-eth_reset tied high level */
+	/*
+	PUPF = 0x1e3;
+	*/
+
+	/* Port G */
+	PUPG = 0x1;
+	PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/
+
+	INTMSK = 0x03fffeff;
+	INTCON = 0x05;
+
+    /*
+	Configure chip ethernet interrupt as High level
+	Port G EINT 0-7 EINT0 -> CHIP ETHERNET
+    */
+	temp = EXTINT;
+	temp &= ~0x7;
+    temp |= 0x1; /*LEVEL_HIGH*/
+	EXTINT = temp;
+
+    /*
+	Reset SMSC LAN91C96 chip
+    */
+    temp= PCONF;
+    temp |= 0x00000040;
+    PCONF = temp;
+
+	/* Reset high */
+    temp = PDATF;
+    temp |= (1 << 3);
+    PDATF = temp;
+
+    /* Short delay */
+    for (temp=0;temp<10;temp++)
+    {
+		/* NOP */
+    }
+
+    /* Reset low */
+    temp = PDATF;
+    temp &= ~(1 << 3);
+    PDATF = temp;
+
+	/* arch number MACH_TYPE_MBA44B0 */
+	gd->bd->bi_arch_number = MACH_TYPE_S3C44B0;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0x0c000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/dave/B2/Makefile b/u-boot/board/dave/B2/Makefile
new file mode 100644
index 0000000..b981579
--- /dev/null
+++ b/u-boot/board/dave/B2/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= B2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/dave/B2/config.mk b/u-boot/board/dave/B2/config.mk
new file mode 100644
index 0000000..f7b686a
--- /dev/null
+++ b/u-boot/board/dave/B2/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x0C100000
+
+PLATFORM_CPPFLAGS += -Uarm
diff --git a/u-boot/board/dave/B2/flash.c b/u-boot/board/dave/B2/flash.c
new file mode 100644
index 0000000..bb892e6
--- /dev/null
+++ b/u-boot/board/dave/B2/flash.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+	return CONFIG_SYS_DUMMY_FLASH_SIZE;
+#else
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (0, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+#endif
+}
diff --git a/u-boot/board/dave/B2/lowlevel_init.S b/u-boot/board/dave/B2/lowlevel_init.S
new file mode 100644
index 0000000..2f3a364
--- /dev/null
+++ b/u-boot/board/dave/B2/lowlevel_init.S
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
+ * Modified By MATTO
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+/*
+ * Documentation:
+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
+ *     Advanced Developer's manual, December 1999
+ *
+ * Intel has a very hard to find SDRAM configurator on their web site:
+ *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
+ *
+ * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
+ * appears to be true, but it might be possible that somebody designs a
+ * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
+ *
+ * 04-10-2001:  SELETZ
+ * - separated memory config for multiple platform support
+ * - perform SA1110 Hardware Reset Procedure
+ *
+ */
+
+.equ    B0_Tacs,      0x0 /* 0clk */
+.equ    B0_Tcos,      0x0 /* 0clk */
+.equ    B0_Tacc,      0x4 /* 6clk */
+.equ    B0_Tcoh,      0x0 /* 0clk */
+.equ    B0_Tah,       0x0 /* 0clk */
+.equ    B0_Tacp,      0x0 /* 0clk */
+.equ    B0_PMC,       0x0 /* normal(1data) */
+/* Bank 1 parameter */
+.equ    B1_Tacs,      0x3 /* 4clk */
+.equ    B1_Tcos,      0x3 /* 4clk */
+.equ    B1_Tacc,      0x7 /* 14clkv */
+.equ    B1_Tcoh,      0x3 /* 4clk */
+.equ    B1_Tah,       0x3 /* 4clk */
+.equ    B1_Tacp,      0x3 /* 6clk */
+.equ    B1_PMC,       0x0 /* normal(1data) */
+
+/* Bank 2 parameter - LAN91C96 */
+.equ    B2_Tacs,      0x3 /* 4clk */
+.equ    B2_Tcos,      0x3 /* 4clk */
+.equ    B2_Tacc,      0x7 /* 14clk */
+.equ    B2_Tcoh,      0x3 /* 4clk */
+.equ    B2_Tah,       0x3 /* 4clk */
+.equ    B2_Tacp,      0x3 /* 6clk */
+.equ    B2_PMC,       0x0 /* normal(1data) */
+
+/* Bank 3 parameter */
+.equ    B3_Tacs,      0x3 /* 4clk */
+.equ    B3_Tcos,      0x3 /* 4clk */
+.equ    B3_Tacc,      0x7 /* 14clk */
+.equ    B3_Tcoh,      0x3 /* 4clk */
+.equ    B3_Tah,       0x3 /* 4clk */
+.equ    B3_Tacp,      0x3 /* 6clk */
+.equ    B3_PMC,       0x0 /* normal(1data) */
+
+/* Bank 4 parameter */
+.equ    B4_Tacs,      0x3 /* 4clk */
+.equ    B4_Tcos,      0x3 /* 4clk */
+.equ    B4_Tacc,      0x7 /* 14clk */
+.equ    B4_Tcoh,      0x3 /* 4clk */
+.equ    B4_Tah,       0x3 /* 4clk */
+.equ    B4_Tacp,      0x3 /* 6clk */
+.equ    B4_PMC,       0x0 /* normal(1data) */
+
+/* Bank 5 parameter */
+.equ    B5_Tacs,      0x3 /* 4clk */
+.equ    B5_Tcos,      0x3 /* 4clk */
+.equ    B5_Tacc,      0x7 /* 14clk */
+.equ    B5_Tcoh,      0x3 /* 4clk */
+.equ    B5_Tah,       0x3 /* 4clk */
+.equ    B5_Tacp,      0x3 /* 6clk */
+.equ    B5_PMC,       0x0 /* normal(1data) */
+
+/* Bank 6(if SROM) parameter */
+.equ    B6_Tacs,      0x3 /* 4clk */
+.equ    B6_Tcos,      0x3 /* 4clk */
+.equ    B6_Tacc,      0x7 /* 14clk */
+.equ    B6_Tcoh,      0x3 /* 4clk */
+.equ    B6_Tah,       0x3 /* 4clk */
+.equ    B6_Tacp,      0x3 /* 6clk */
+.equ    B6_PMC,       0x0 /* normal(1data) */
+
+/* Bank 7(if SROM) parameter */
+.equ    B7_Tacs,      0x3 /* 4clk */
+.equ    B7_Tcos,      0x3 /* 4clk */
+.equ    B7_Tacc,      0x7 /* 14clk */
+.equ    B7_Tcoh,      0x3 /* 4clk */
+.equ    B7_Tah,       0x3 /* 4clk */
+.equ    B7_Tacp,      0x3 /* 6clk */
+.equ    B7_PMC,       0x0 /* normal(1data) */
+
+/* Bank 6 parameter */
+.equ    B6_MT,        0x3 /* SDRAM */
+.equ    B6_Trcd,      0x0 /* 2clk */
+.equ    B6_SCAN,      0x0 /* 10bit */
+
+.equ    B7_MT,        0x3 /* SDRAM */
+.equ    B7_Trcd,      0x0 /* 2clk */
+.equ    B7_SCAN,      0x0 /* 10bit */
+
+
+/* REFRESH parameter */
+.equ    REFEN,        0x1 /* Refresh enable */
+.equ    TREFMD,       0x0 /* CBR(CAS before RAS)/Auto refresh */
+.equ    Trp,        0x0 /* 2clk */
+.equ    Trc,        0x3 /* 0x1=5clk 0x3=11clk*/
+.equ    Tchr,       0x0 /* 0x2=3clk 0x0=0clks  */
+.equ    REFCNT,       879
+
+MEMORY_CONFIG:
+  .long   0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
+  .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
+  .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
+  .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
+  .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
+  .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
+  .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
+  .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  /*GCS6*/
+  .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  /*GCS7*/
+  .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
+  .word 0x17      /*SCLK power down mode, BANKSIZE 16M/16M*/
+  .word 0x20      /*MRSR6 CL=2clk*/
+  .word 0x20      /*MRSR7*/
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+		the next instruction fail due memory relocation...
+		we'll find the right MEMORY_CONFIG address with the next 3 lines...
+	*/
+	/*ldr r0, =MEMORY_CONFIG*/
+	mov r0, pc
+	ldr r1, =(0x38+4)
+	sub r0, r0, r1
+
+	ldmia r0, {r1-r13}
+	ldr   r0, =0x01c80000
+	stmia r0, {r1-r13}
+	mov pc, lr
diff --git a/u-boot/board/dave/PPChameleonEVB/Makefile b/u-boot/board/dave/PPChameleonEVB/Makefile
new file mode 100644
index 0000000..5028510
--- /dev/null
+++ b/u-boot/board/dave/PPChameleonEVB/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/dave/PPChameleonEVB/PPChameleonEVB.c b/u-boot/board/dave/PPChameleonEVB/PPChameleonEVB.c
new file mode 100644
index 0000000..8e26996
--- /dev/null
+++ b/u-boot/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2003
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+	out32(GPIO0_OR, CONFIG_SYS_NAND0_CE);                 /* set initial outputs     */
+	out32(GPIO0_OR, CONFIG_SYS_NAND1_CE);                 /* set initial outputs     */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0)
+	 * IRQ 26 (EXT IRQ 1)
+	 * IRQ 27 (EXT IRQ 2)
+	 * IRQ 28 (EXT IRQ 3)
+	 * IRQ 29 (EXT IRQ 4)
+	 * IRQ 30 (EXT IRQ 5)
+	 * IRQ 31 (EXT IRQ 6)
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+#if 1 /* test-only */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+#else
+	mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
+#endif
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart = 0 - flash_info[0].size;
+	gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
+#if 0
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+	volatile unsigned char *duart0_mcr =
+		(unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr =
+		(unsigned char *)((ulong)DUART1_BA + 4);
+
+	bd_t *bd = gd->bd;
+	char *	tmp;                    /* Temporary char pointer      */
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long CPC0_CR0Reg;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+#endif
+
+#if 0
+	/*
+	 * Enable power on PS/2 interface
+	 */
+	*fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+#endif
+	return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PPChameleonEVB");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CFB_CONSOLE
+# ifdef CONFIG_CONSOLE_EXTRA_INFO
+# include <video_fb.h>
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	uint pvr = get_pvr ();
+
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		switch (pvr) {
+		case PVR_405EP_RB:
+			sprintf (info, " AMCC PowerPC 405EP Rev. B");
+			break;
+		default:
+			sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
+			break;
+		}
+		return;
+	case 2:
+		sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+# endif	/* CONFIG_CONSOLE_EXTRA_INFO */
+#endif	/* CONFIG_CFB_CONSOLE */
diff --git a/u-boot/board/dave/PPChameleonEVB/flash.c b/u-boot/board/dave/PPChameleonEVB/flash.c
new file mode 100644
index 0000000..2e1a9ab
--- /dev/null
+++ b/u-boot/board/dave/PPChameleonEVB/flash.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+	return CONFIG_SYS_DUMMY_FLASH_SIZE;
+#else
+	unsigned long size;
+	int i;
+	uint pbcr;
+	unsigned long base;
+	int size_val = 0;
+
+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+	debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+	/* Setup offsets */
+	flash_get_offsets (-size, &flash_info[0]);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base = -size;
+	switch (size) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+	flash_info[0].size  = size;
+
+	return (size);
+#endif
+}
diff --git a/u-boot/board/dave/PPChameleonEVB/fpgadata.c b/u-boot/board/dave/PPChameleonEVB/fpgadata.c
new file mode 100644
index 0000000..f5e30dd
--- /dev/null
+++ b/u-boot/board/dave/PPChameleonEVB/fpgadata.c
@@ -0,0 +1,1139 @@
+  0x1f,0x8b,0x08,0x08,0x80,0xb0,0xc0,0x3e,0x00,0x03,0x61,0x73,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x70,0x14,0x65,
+  0x9a,0xc7,0x9f,0xe9,0xee,0x24,0x9d,0x99,0x4e,0xa6,0x0d,0x84,0x42,0xe5,0x47,0xe7,
+  0xc7,0xba,0xa3,0x37,0x0c,0x63,0x82,0x9a,0x05,0x32,0x69,0x03,0x7f,0xe4,0x84,0x2d,
+  0xd9,0xbd,0xba,0xaa,0xdb,0x5a,0x6b,0x1d,0x5d,0xbc,0xe2,0xb6,0xd0,0xca,0xea,0x55,
+  0x1d,0x67,0x6d,0xdd,0xbd,0x24,0x39,0x08,0x07,0x2b,0x01,0xb9,0x23,0xee,0x51,0x5c,
+  0xf3,0x63,0xcb,0xa8,0xa9,0xad,0x11,0x76,0x0d,0x0a,0xa5,0x4d,0x2e,0x8b,0x21,0x44,
+  0xc8,0xb1,0xd6,0x6e,0x44,0x97,0x1d,0x34,0xab,0x23,0x72,0x18,0xd1,0x92,0x44,0x20,
+  0xb9,0xf7,0xed,0xee,0xf7,0xed,0x9f,0x33,0xc9,0x8e,0x7f,0xf8,0xe4,0x9d,0xd7,0xf6,
+  0x7d,0x9e,0x79,0xfb,0x79,0x3e,0xfd,0x7d,0xde,0x86,0xd2,0xe8,0xb8,0xf9,0x0f,0x40,
+  0xe8,0x31,0x90,0x1f,0x7b,0x66,0xc3,0xb2,0xe4,0x7d,0x8f,0xde,0xfb,0x68,0x32,0x99,
+  0x78,0xea,0xc7,0xeb,0xe1,0x71,0x88,0xd4,0x3d,0x73,0x5f,0xf2,0x89,0x7f,0xfc,0xe9,
+  0xbd,0xcb,0x96,0xc1,0x8f,0xf1,0x5f,0xc9,0x64,0xfd,0xd2,0xe4,0x7d,0x4b,0xef,0xad,
+  0x87,0xf5,0x50,0x7a,0x6f,0x72,0xf9,0xb2,0x65,0xcb,0x97,0x35,0xc0,0x13,0x10,0xaa,
+  0x3f,0x3c,0x8d,0x3f,0x2f,0xbf,0xf0,0xb7,0x7f,0x9f,0x04,0x14,0x02,0x80,0x92,0x64,
+  0x28,0x4d,0xfe,0x1d,0x49,0x86,0x94,0x10,0xa0,0xa6,0x25,0x49,0xd0,0xc9,0xdf,0x60,
+  0x7d,0x5f,0x9a,0x04,0xc5,0xf9,0x77,0x28,0x09,0x2a,0xac,0x03,0x75,0x07,0x54,0x24,
+  0x61,0xe6,0x8f,0x2a,0x20,0x6a,0xfe,0x85,0xf3,0xa7,0x87,0x50,0xde,0x59,0xf6,0xa7,
+  0xe9,0x9a,0x46,0x4d,0x6e,0x16,0xd7,0x0f,0xa9,0xc0,0xae,0x7f,0x61,0x56,0xd7,0xff,
+  0x9a,0x5e,0xff,0x2f,0x9d,0x0f,0x15,0xb3,0x98,0x0e,0x20,0xb0,0xf5,0x58,0xf3,0x11,
+  0xc4,0x20,0x0c,0x1c,0x02,0x0d,0x14,0x6c,0x78,0xaf,0x3f,0x40,0xad,0x93,0x45,0x53,
+  0x70,0x03,0x35,0x65,0xa3,0xa3,0xfc,0x3c,0x38,0x87,0x9a,0x40,0x9a,0xe0,0x53,0x30,
+  0x4d,0x46,0x8e,0xf1,0x57,0x4d,0x63,0x82,0x1f,0x87,0x56,0x6b,0x7e,0xff,0xfc,0x5f,
+  0xc1,0x71,0x94,0xc8,0x46,0xba,0x9a,0x13,0xdc,0x76,0x94,0x80,0xb2,0x4c,0x38,0x61,
+  0x8e,0x1c,0xe3,0xae,0x52,0x23,0x2b,0xd0,0x28,0x0e,0x0a,0x3b,0xe0,0x28,0xc4,0xf5,
+  0x88,0x1c,0xae,0x85,0x76,0x88,0x83,0x98,0xe4,0x24,0x73,0x24,0xc9,0x0d,0x53,0xa3,
+  0x1f,0x2f,0xd2,0xfc,0xe8,0xd0,0x0b,0xc7,0x21,0xa1,0x47,0xba,0xfb,0x13,0xb0,0x1d,
+  0x12,0x70,0x7b,0x92,0x8b,0x9b,0x23,0x19,0xee,0x0a,0x35,0xc6,0x05,0xba,0x9e,0xef,
+  0x55,0x5e,0x81,0x1b,0x90,0xd2,0xa3,0xfb,0xf8,0xa5,0xca,0x19,0x58,0x19,0x93,0x32,
+  0x35,0x71,0x73,0x24,0xc3,0x5f,0xa1,0xc6,0xc8,0x6a,0x3a,0x5f,0x0b,0x9d,0x80,0x69,
+  0x68,0xd2,0xa3,0x23,0xfc,0x4d,0x62,0x24,0xa3,0xe3,0xa6,0xa1,0x3b,0x8d,0x1c,0xa4,
+  0xe9,0x7a,0xe4,0x5e,0x7a,0xfd,0x8d,0xf0,0x19,0xa4,0xa0,0xdc,0x71,0x59,0x66,0x8c,
+  0x0b,0x74,0xfd,0xa3,0x45,0x71,0xd9,0x5c,0xff,0x3d,0x12,0xbc,0x8f,0xd7,0xdf,0xf9,
+  0x1b,0x7b,0xd9,0xcc,0xb8,0x86,0x77,0xbf,0x75,0x7d,0x61,0xad,0x19,0x04,0xc4,0x7d,
+  0xb7,0xe3,0x10,0x17,0xd7,0xee,0x74,0x84,0x85,0x19,0x13,0xf8,0x5e,0x31,0x3f,0xe3,
+  0xf0,0x23,0xe8,0x43,0x4b,0xb2,0x91,0x1f,0x84,0x53,0xf2,0x5e,0xb4,0xf4,0xc3,0xd2,
+  0x4d,0xdc,0x45,0x73,0x04,0x1b,0xc8,0x32,0x46,0xd9,0xf5,0x5b,0xc4,0xb5,0xf0,0x25,
+  0x5a,0xa9,0x47,0x77,0xf1,0x6b,0x95,0x8f,0x60,0x25,0x8a,0x26,0xf9,0x61,0xf8,0x12,
+  0xf0,0x48,0x03,0x7f,0x16,0x61,0x23,0x8b,0x47,0xce,0x73,0x74,0x3f,0xa8,0x0b,0x7b,
+  0xcd,0x20,0x7c,0x61,0x44,0xa3,0x51,0x2f,0x67,0x61,0xf9,0x82,0xbf,0xa2,0x5a,0xf1,
+  0x19,0x29,0xa6,0xf1,0x11,0x8b,0x7a,0xa5,0x1b,0x02,0x0e,0x02,0x8a,0xc4,0xe1,0x0c,
+  0x8e,0x8f,0xe4,0x89,0xcf,0xca,0x2c,0x1e,0x19,0x62,0xbf,0xef,0xe0,0xed,0xfb,0xa0,
+  0x0f,0x96,0xe8,0x91,0x75,0xdc,0x02,0xd8,0x8a,0x0d,0xb1,0x95,0xfb,0xc0,0x1c,0xa1,
+  0x06,0x1e,0xb9,0xc6,0xe2,0xa9,0xc0,0x7e,0xa1,0x0f,0x3d,0x99,0x8d,0xfc,0x1d,0xb7,
+  0xbc,0x7a,0x2b,0x8a,0x6b,0x2e,0x7f,0x0d,0x43,0xdc,0xc4,0xe9,0xec,0xfa,0x1b,0xe8,
+  0x7e,0xcb,0xe0,0x6d,0xd6,0x0e,0x92,0x7e,0xb7,0x2f,0x9e,0x78,0x07,0x9e,0x67,0xd7,
+  0xcf,0x56,0xe6,0xe0,0x1b,0x48,0xa1,0x68,0x96,0x5f,0x21,0x0c,0x71,0x4d,0x07,0xcb,
+  0x34,0xde,0x1a,0x31,0x0c,0x21,0x85,0xff,0x9f,0xfc,0x84,0x40,0xfd,0x6d,0x09,0x69,
+  0xa1,0x09,0xec,0x66,0x14,0xf1,0x97,0x14,0x6c,0xc8,0xe5,0x88,0xcf,0x82,0x35,0xc2,
+  0x8c,0xf3,0x40,0xf7,0xbf,0x28,0x1f,0x86,0x49,0x48,0xa9,0xd1,0x2e,0xfe,0x09,0x38,
+  0x0d,0x2b,0x55,0xa9,0x8b,0xaf,0xa5,0x23,0x63,0xd4,0xe8,0x67,0xf7,0x0b,0x12,0xd6,
+  0xc3,0xeb,0x90,0x50,0x23,0xbb,0xda,0x8a,0xdb,0x4a,0x21,0xb1,0x21,0xb6,0x8f,0xab,
+  0x35,0x47,0xba,0xb8,0x31,0x6a,0x64,0x41,0xb6,0xe6,0x37,0x14,0xb1,0x6f,0xd7,0xc3,
+  0x36,0x48,0xb4,0x88,0xf3,0x9c,0xf3,0x6f,0x37,0x8d,0x53,0x6c,0x3f,0xc4,0xe6,0x0a,
+  0xf0,0x2a,0xc4,0xd5,0x88,0xcc,0x09,0xe2,0x66,0x88,0x3f,0x34,0x1f,0x1b,0x74,0x64,
+  0x80,0x1a,0xfd,0x21,0xba,0x1f,0x36,0x95,0xa5,0xa9,0x53,0x69,0x18,0x84,0x94,0x28,
+  0xa1,0x88,0xe2,0xf3,0xf7,0x22,0x4f,0xf7,0x67,0x77,0xa5,0xe9,0xd4,0xc3,0x4f,0xb7,
+  0x7f,0x80,0x8d,0xa6,0x87,0xa2,0xbb,0xdb,0xc7,0x7c,0xfe,0x7e,0x5c,0x4c,0xef,0xc7,
+  0xf9,0x45,0xd6,0xe0,0x3a,0x7e,0x0f,0x8e,0x4f,0x53,0x4b,0xf9,0x3a,0xde,0x35,0xbf,
+  0x89,0x18,0xa7,0x58,0xfe,0x69,0x98,0x9f,0x85,0x63,0xf8,0xb6,0x8a,0xb4,0xb5,0x29,
+  0x30,0x2a,0x24,0xe6,0x85,0xdb,0x38,0x6b,0x04,0xd9,0xc6,0x59,0x16,0xcf,0x16,0xe8,
+  0x30,0x9d,0xda,0x1d,0xee,0x80,0xcd,0x5c,0x62,0x30,0x2c,0xb7,0x61,0x37,0x05,0xe2,
+  0x66,0x05,0xf3,0xf7,0x7c,0x88,0x5e,0xbf,0x5b,0x38,0x6c,0x46,0x6f,0x37,0x0e,0xe3,
+  0x0b,0xd8,0x08,0x3b,0xc2,0xce,0x8c,0x8f,0xd9,0x7e,0xd0,0x0c,0x7f,0x13,0x6a,0x74,
+  0x01,0xdf,0x81,0xd7,0x9f,0x4a,0x97,0x77,0xf1,0x7e,0x7f,0x73,0x2c,0x5f,0x0d,0x86,
+  0xac,0xfd,0xd0,0xcd,0x8f,0x55,0x63,0x63,0xc3,0xd2,0xa0,0xf9,0xdf,0xb0,0xfc,0x23,
+  0xca,0x1a,0x09,0x3b,0x44,0xb7,0xf0,0x9a,0x38,0x28,0x18,0xd1,0xd6,0x7c,0xf1,0x1f,
+  0x62,0xfb,0x39,0x56,0x14,0x83,0x37,0x20,0x81,0x22,0x63,0xdc,0xeb,0xf0,0x32,0x2c,
+  0xe9,0xe2,0x3f,0xe4,0x62,0x22,0x19,0xd9,0xae,0x71,0x39,0xf3,0x2b,0x8d,0x1b,0xb2,
+  0xf7,0x83,0xb0,0x56,0xa8,0x11,0xf0,0xdd,0x51,0xcb,0x89,0xd0,0x2e,0xc4,0xcf,0xe3,
+  0xdb,0x64,0x87,0xeb,0x7e,0x39,0x89,0x8d,0x21,0xb6,0xdf,0x90,0xfc,0x88,0x79,0xb7,
+  0x66,0xe7,0x65,0x62,0x2f,0xc2,0x12,0x15,0xdf,0x86,0x0b,0xd8,0xfd,0x2b,0x3f,0xc0,
+  0x19,0x46,0x8e,0xcd,0xef,0xec,0xfc,0x11,0x7c,0x82,0x1a,0xb3,0xd1,0x0d,0xdf,0xae,
+  0x80,0xb7,0xdb,0x1a,0xb5,0xe8,0x06,0x7e,0x3f,0x5c,0x47,0x0b,0xb3,0xd1,0x4d,0xfc,
+  0x45,0xf8,0xa7,0x8e,0x46,0x62,0x5c,0xae,0xa6,0xf3,0xc5,0x4a,0x9c,0x6f,0x43,0x38,
+  0x7b,0x68,0xd8,0xbb,0x1b,0xf0,0x2f,0x10,0xfd,0xb5,0x37,0xdf,0x2e,0xce,0xf0,0xfd,
+  0x6d,0x34,0x3e,0x20,0xbc,0xa9,0x4e,0xa3,0xd4,0x58,0x34,0x17,0x99,0x07,0x67,0x3a,
+  0x9a,0xc6,0xe2,0x37,0xad,0xfa,0xb5,0x73,0x82,0x9f,0x82,0xe9,0xb6,0xa6,0x4b,0xb8,
+  0x7e,0xe9,0x1a,0x8d,0xff,0xcb,0xf3,0xf7,0xc1,0x75,0x58,0x92,0x8b,0xa4,0x39,0xb9,
+  0x65,0x6b,0xe6,0xdb,0xab,0xc5,0x71,0x7b,0xfd,0x17,0xd5,0xbe,0x8a,0x38,0x31,0x2e,
+  0xb3,0xdf,0x17,0x60,0x5f,0x08,0x7f,0x3b,0x78,0x67,0x2b,0xd7,0x4a,0xf2,0xd5,0x40,
+  0x77,0xda,0xe1,0xaf,0x68,0x19,0x76,0xfe,0x51,0x84,0x1d,0xa5,0x35,0x46,0xf4,0xda,
+  0x1e,0x44,0x3c,0xd4,0x7e,0x3f,0x46,0x12,0xd1,0xd1,0xd0,0x46,0x23,0x9e,0x45,0x56,
+  0x60,0x07,0xd9,0xfe,0xec,0xa9,0x24,0x45,0x01,0x7b,0x27,0xf2,0x0f,0x92,0xfc,0x99,
+  0x5e,0x90,0xf9,0x2b,0x7f,0xfd,0xb2,0xd7,0x83,0x42,0xbd,0x82,0x31,0x78,0x60,0xce,
+  0x21,0x6c,0x2c,0x4a,0x47,0x83,0xea,0x51,0x96,0xdd,0x2f,0x55,0xb2,0x55,0xef,0xb2,
+  0x7c,0x12,0xce,0xe1,0x7c,0x2e,0x65,0xf9,0x95,0xac,0xde,0x85,0x2c,0x43,0x5f,0x4d,
+  0xd7,0x7f,0x40,0xd8,0x68,0x16,0x29,0x8d,0xab,0x41,0xaf,0x40,0xe2,0xf1,0x58,0x26,
+  0xec,0xaf,0xbf,0xd9,0x07,0xd9,0x7e,0x28,0x8a,0xc3,0x2b,0x64,0xb0,0x93,0xab,0x26,
+  0xf5,0x3a,0x1b,0xeb,0x36,0xea,0xf5,0x3d,0xee,0xf9,0x6c,0xbf,0x89,0x73,0x25,0x78,
+  0x5e,0x8e,0x0f,0x46,0xb4,0x62,0x80,0x43,0x62,0x5c,0x15,0x65,0x9b,0x07,0xde,0xd1,
+  0x28,0x0f,0xb0,0xfc,0x03,0x65,0x1b,0x43,0xb8,0xec,0x0e,0x62,0xa7,0x14,0x38,0xa3,
+  0xa4,0xc8,0xfa,0x49,0x7c,0x96,0xeb,0xe7,0x7e,0xc3,0xff,0x1f,0xc2,0xa1,0x7b,0x17,
+  0x7f,0xa5,0xb3,0xfc,0x73,0xb0,0xf2,0xa6,0x3c,0xad,0x34,0x0d,0x44,0x5a,0x31,0xb4,
+  0x4c,0x93,0xec,0xc1,0xea,0xd7,0x35,0x1c,0x1f,0x5a,0xdf,0x59,0xfe,0xd1,0xcb,0x18,
+  0xe4,0x5c,0x80,0x3f,0x75,0x19,0x06,0xde,0x36,0x28,0x75,0xe9,0x39,0xcb,0x70,0xf3,
+  0x0f,0x02,0x06,0x39,0x39,0x91,0xf8,0xeb,0xc4,0x9e,0x00,0xfe,0x11,0x8b,0x58,0xf5,
+  0xc9,0xc1,0xf3,0x8a,0xbb,0xac,0xb3,0xfb,0xab,0x9f,0xe5,0x1f,0xfd,0xb6,0x5e,0x1a,
+  0xb4,0xcb,0x24,0x9e,0xae,0x30,0x3a,0xf8,0x87,0xed,0xcf,0xb9,0xbd,0xf4,0x47,0x1f,
+  0xc2,0xbc,0xe1,0xd8,0x06,0x4e,0x50,0xd1,0x59,0x7e,0xb8,0x04,0x27,0x68,0x10,0x26,
+  0xb8,0x69,0x58,0xaa,0x07,0xf2,0xcf,0x84,0x4a,0xe7,0x33,0xfe,0xc9,0xe0,0x6a,0xf8,
+  0xbe,0x67,0x9b,0x05,0xf0,0xcf,0xa0,0xc0,0x76,0x4b,0x4e,0x7c,0xdf,0xbf,0x7e,0xce,
+  0xe2,0x1f,0xfa,0xf9,0xb0,0x68,0x2d,0x8d,0x86,0x0e,0xcf,0x43,0x40,0x7c,0xdc,0xfc,
+  0xf3,0x58,0x68,0x11,0xad,0xfe,0xdf,0xc0,0x5e,0xc3,0x28,0x36,0x30,0x20,0x17,0x71,
+  0x80,0x81,0x83,0x7f,0xa0,0x1c,0xbe,0xcc,0x18,0x90,0x73,0x12,0x7e,0x47,0x40,0xc8,
+  0xe2,0x9f,0x1c,0x35,0x3c,0xfc,0x53,0x69,0xc7,0x07,0xa6,0x65,0x16,0x96,0xd4,0x00,
+  0x21,0x22,0xcc,0x3f,0x29,0x02,0x42,0x36,0xff,0xf4,0x54,0x9e,0xc5,0xb7,0xad,0x01,
+  0x39,0xd9,0xfc,0xf1,0xb9,0x6c,0xe7,0xff,0xdb,0xf6,0xc1,0xdb,0x26,0xe4,0x8c,0x1a,
+  0xfc,0x13,0xf1,0xf1,0x4f,0x84,0xf0,0x0f,0xbd,0xbe,0x0e,0xfb,0x61,0xab,0x09,0x39,
+  0xd7,0x2c,0x7f,0xbd,0xfc,0x83,0x8d,0x71,0x96,0x7f,0x5a,0x30,0x4f,0xb6,0x9b,0x90,
+  0x33,0x8c,0xb6,0xdb,0x61,0x94,0x5c,0xf1,0xb4,0xf9,0x24,0x57,0xd4,0x53,0x31,0x04,
+  0x06,0xe4,0xbc,0x07,0x17,0x38,0x8a,0x3d,0xe0,0x36,0xec,0x7a,0xd4,0xa2,0x66,0x21,
+  0xe7,0xa9,0x3e,0xd4,0x28,0x09,0xe2,0x1f,0x30,0x8b,0x5a,0x84,0x54,0xb7,0xd3,0x70,
+  0xbf,0xb3,0xcc,0xd5,0x5b,0xa8,0xd0,0x35,0xa7,0x1f,0x7c,0xfc,0x43,0xaa,0xed,0x4b,
+  0x50,0xed,0x2c,0xbb,0x15,0x36,0xff,0xc8,0x34,0xff,0xcc,0x9f,0x6b,0xd3,0x0e,0xb7,
+  0x0d,0xee,0x72,0x95,0x69,0x66,0x9c,0x12,0xe8,0xef,0x2b,0x0a,0x8c,0x76,0xc6,0x60,
+  0x33,0xfe,0xbd,0x9d,0xd8,0x63,0xf3,0x0f,0xdb,0x9f,0xc7,0x44,0xca,0x3f,0xf5,0x59,
+  0x5c,0x88,0xef,0x77,0x3b,0x2e,0x5a,0xc6,0x59,0x8e,0xae,0xa7,0xbb,0x8c,0xf1,0xde,
+  0xbb,0xda,0x64,0xcc,0x5d,0xd6,0x03,0xf8,0xa7,0xbb,0xe8,0x2b,0x0a,0x39,0x7f,0xe6,
+  0x4e,0xc3,0x11,0xf7,0x7c,0x71,0x92,0x4b,0x79,0xf8,0x07,0x1c,0xb4,0xd3,0x09,0x07,
+  0x61,0x0d,0x2a,0xc8,0x3f,0x62,0xe5,0x80,0xf0,0x2a,0x47,0xfd,0x8d,0x29,0x5e,0x7f,
+  0x43,0x16,0xef,0x31,0x1e,0xab,0x3c,0xcc,0xa2,0xa7,0x6c,0x73,0xc6,0xbf,0xd4,0x15,
+  0x4f,0xba,0x1f,0x0e,0x56,0x92,0x41,0xb2,0xc8,0x92,0xdf,0xc2,0x49,0xa8,0x0b,0xf6,
+  0x37,0xd7,0x41,0xaf,0xdf,0x03,0x34,0x3e,0x35,0xfe,0x69,0xcc,0xb8,0x8c,0xe8,0xfd,
+  0x1b,0x93,0x4d,0xda,0x91,0x30,0x6f,0xc3,0x44,0x28,0x05,0x3b,0x83,0x78,0x7b,0xa8,
+  0x83,0xee,0x7f,0x45,0x30,0xf9,0x27,0x46,0x68,0xe7,0x4d,0x93,0x76,0x30,0xf6,0x70,
+  0xa6,0x31,0xdf,0xe2,0x9f,0x41,0x9b,0x7f,0xac,0xfc,0x23,0x06,0xa5,0x1d,0x66,0x0c,
+  0xb1,0xfc,0x53,0x15,0x32,0xaa,0x7f,0x56,0x6c,0xad,0xc0,0x77,0x6b,0x32,0xcf,0xfd,
+  0x3b,0xa8,0xb2,0xeb,0xc3,0x22,0x4c,0x3b,0x8d,0x59,0x89,0xd0,0xce,0x75,0xad,0xd1,
+  0xc4,0x1e,0x32,0xe2,0x34,0x86,0x58,0xfe,0x31,0xf8,0x87,0x3c,0x9d,0xe1,0xec,0xa1,
+  0x98,0xd9,0x23,0xe4,0xcf,0x27,0xfd,0x2c,0xff,0xa8,0x95,0x53,0xaa,0x55,0xbf,0xa6,
+  0xd2,0xe7,0xd0,0x0a,0x5a,0xbf,0xf0,0xc8,0xeb,0xf8,0xf9,0xfd,0x86,0xf9,0xd5,0x08,
+  0xdb,0x3f,0x3d,0x38,0xff,0x18,0x4e,0xb5,0x72,0x37,0xe1,0x77,0x98,0x67,0xec,0x65,
+  0xb3,0x7c,0xe2,0xe4,0x9f,0x17,0x60,0x1f,0x85,0x9c,0x0f,0x42,0xee,0x7c,0xf5,0xb4,
+  0xc1,0x3f,0x4f,0x9e,0xc4,0x23,0x59,0x96,0x7f,0xd2,0x02,0x0b,0xda,0x39,0x35,0x6f,
+  0x3e,0x1f,0x65,0xfb,0xb3,0xa1,0xa8,0x57,0xb4,0x9c,0xba,0xa5,0x9e,0x83,0x67,0x83,
+  0xf3,0xe7,0x90,0x60,0xd7,0x5f,0x3a,0xb8,0xca,0x8f,0x85,0x0e,0xfe,0xa1,0xeb,0xd9,
+  0x0c,0x8e,0xea,0xf6,0x27,0x77,0x99,0xab,0x71,0xf0,0x0f,0x5d,0xcf,0x49,0xca,0x3f,
+  0x99,0xea,0x2b,0x26,0xd8,0x04,0xd6,0x5f,0x9b,0x7f,0x2a,0xe9,0x7c,0x8c,0xcd,0x79,
+  0xeb,0xb5,0x83,0x7f,0x84,0x32,0x38,0x2a,0x5b,0xd1,0x38,0x84,0x0d,0xfa,0xbc,0x3f,
+  0x82,0x89,0x71,0x58,0x39,0xaa,0xc4,0x47,0xd7,0x38,0xf9,0x47,0x2f,0x7d,0x92,0xc4,
+  0x67,0x00,0x3b,0x75,0xc2,0x55,0x5f,0x46,0x0c,0x03,0xf3,0xcf,0x05,0x17,0xff,0x68,
+  0x0b,0xb1,0x77,0x4a,0xd3,0xa0,0xe9,0xa6,0xd2,0xe4,0xad,0xef,0x6a,0xca,0xc3,0x3f,
+  0x45,0x53,0x94,0x7f,0xbe,0x16,0xc7,0xd1,0x7d,0x9a,0x34,0x42,0xf5,0x1f,0x22,0x04,
+  0x9d,0xf3,0xea,0x3f,0xba,0x6c,0x41,0x4e,0x92,0xfb,0x18,0x3a,0x95,0x7b,0x50,0x67,
+  0xb6,0x22,0x4e,0xb1,0xe7,0x57,0xb0,0xdd,0xa7,0xff,0xd8,0xfc,0x33,0x86,0x93,0xe9,
+  0x5d,0xa8,0x34,0x79,0x87,0xe4,0x7c,0x42,0xf7,0xea,0x3f,0x95,0x8c,0x7f,0x3e,0x81,
+  0x4e,0x54,0xad,0x95,0xf6,0xd8,0xfc,0xd9,0x4b,0x23,0x6c,0xeb,0x3f,0x3a,0xd5,0x7f,
+  0x32,0x7f,0x73,0x0e,0xc6,0xf5,0xfb,0xb3,0x65,0xdd,0xed,0x8c,0x9f,0x0d,0x45,0x22,
+  0x8f,0xfe,0x33,0xde,0x7c,0x13,0x6f,0x8d,0x26,0x3d,0xe1,0x8c,0x0f,0x97,0x5f,0xff,
+  0xc9,0xe0,0xc7,0xf6,0x41,0x75,0xb9,0x26,0xa5,0x22,0x7e,0x3e,0x77,0xf0,0x4f,0xc8,
+  0x5c,0x6d,0xf9,0x09,0xfc,0xfc,0xd8,0xa9,0x28,0x7b,0x36,0x1c,0xb3,0xf5,0xab,0x61,
+  0xbf,0xfe,0x93,0xa5,0xfc,0xf3,0x00,0x7e,0x0c,0x47,0x10,0x43,0xe2,0x32,0x8e,0x29,
+  0x18,0x01,0xfc,0x93,0xc5,0xfc,0xf3,0x00,0xbe,0x49,0xc3,0x9b,0x9e,0x7e,0x40,0xed,
+  0x38,0x50,0x73,0xb8,0x65,0x82,0xdb,0x6f,0xdc,0xb6,0x7c,0x20,0xff,0x3c,0x24,0x4a,
+  0xa6,0xda,0x93,0xe4,0x05,0xd0,0xb5,0x06,0x41,0xaa,0xe3,0x77,0xd0,0x91,0xb3,0xd4,
+  0x70,0xf0,0x4f,0xd9,0x09,0xec,0x94,0x11,0x84,0x77,0xe1,0xa6,0xdc,0x24,0x44,0x5b,
+  0xf9,0x9f,0x99,0xb2,0x4f,0xc6,0x0e,0x94,0xcd,0x3f,0x2f,0x17,0x59,0x41,0x38,0x16,
+  0x11,0xa0,0x1a,0x8e,0xe8,0xf1,0xd7,0x22,0x09,0x1a,0xf6,0xb3,0xd4,0x70,0xe8,0x3f,
+  0xbb,0x8c,0xe7,0x29,0x92,0x46,0xe6,0xc2,0xef,0xa1,0x46,0x17,0xc7,0xdb,0x56,0xc2,
+  0x1f,0x68,0x62,0xd9,0x4a,0xf9,0x87,0xce,0x47,0xb0,0x9f,0x3a,0xf5,0x7d,0x65,0xef,
+  0xb6,0xaa,0x2a,0x0c,0x42,0x8b,0x0c,0x22,0x32,0xf2,0x95,0x65,0xd8,0xcf,0x5f,0x2d,
+  0x73,0x69,0xd0,0x9a,0x57,0xc3,0xee,0x74,0x35,0x32,0xf4,0x46,0x96,0x88,0xac,0xfd,
+  0xe6,0xd4,0x7f,0x7a,0x28,0xe4,0xfc,0x40,0xf8,0x7d,0x73,0xfd,0x9e,0x05,0x63,0x7c,
+  0x0c,0x86,0x2c,0xfe,0xe1,0x2c,0xc3,0xa1,0xff,0x80,0x55,0x74,0x3a,0xf8,0x03,0x44,
+  0xff,0x81,0x47,0x3b,0xda,0x0b,0xeb,0x3f,0x63,0xf0,0x29,0xad,0x6e,0x9f,0xd6,0xd4,
+  0xb5,0x0e,0xef,0x5a,0x5e,0x2b,0xce,0x42,0xff,0xd9,0xd3,0x36,0x26,0x6c,0x53,0xaa,
+  0x5b,0x36,0xec,0x8b,0xac,0x2f,0xa0,0xff,0xcc,0xa7,0xfa,0x4f,0x77,0xf1,0x98,0xf8,
+  0x0a,0xae,0xd7,0x2d,0x72,0xf3,0x61,0x3f,0xff,0x38,0xf2,0x0f,0xe5,0x9f,0xe6,0xe1,
+  0xd0,0x36,0x50,0x54,0xb1,0xae,0x6d,0x00,0x76,0xe5,0xd5,0x7f,0x1a,0xca,0xd2,0x98,
+  0xf7,0x12,0x10,0x05,0x9e,0x80,0x5f,0x1d,0x48,0x6d,0x35,0x7e,0xfd,0xc1,0xd6,0x7f,
+  0x46,0x17,0x5a,0x4e,0xed,0x6e,0xff,0x0a,0x6e,0xc5,0xde,0x7a,0x28,0x7a,0xbe,0x7d,
+  0xbd,0x36,0x0b,0xfd,0x67,0x17,0xde,0x6f,0xef,0x40,0xbd,0x2e,0x9d,0x6f,0x67,0xfa,
+  0xd8,0x57,0xd4,0xb0,0xf9,0x67,0x93,0x6c,0x41,0x0e,0xe0,0xb2,0x8e,0xef,0x2f,0xf1,
+  0x9e,0x2d,0x61,0x05,0x15,0xe0,0x9f,0x22,0xcb,0xa9,0x0a,0xc2,0x3f,0xa2,0xd6,0x2c,
+  0xca,0x6d,0x82,0xe2,0xe5,0x3d,0x5b,0xff,0x99,0x7f,0xdb,0x61,0x07,0x4f,0xaa,0xca,
+  0xea,0xb0,0xdc,0xec,0xd7,0xdf,0xbc,0xfa,0x8f,0xb5,0xc8,0xd3,0xea,0x91,0xa7,0x03,
+  0xf5,0x3d,0x5b,0xff,0xc9,0x51,0xfd,0x27,0xc3,0x8f,0xa1,0x49,0x31,0xd5,0x1c,0xfd,
+  0x45,0x41,0xfd,0x87,0xf2,0x0f,0x0e,0xb2,0x82,0xf3,0x4f,0x4a,0x8e,0x13,0x63,0x16,
+  0xfa,0xcf,0x2f,0x9b,0xbf,0x03,0x53,0xb0,0x74,0x77,0x4f,0x36,0x1c,0xa3,0xb2,0x4f,
+  0x90,0xfe,0x43,0xf3,0x4f,0x03,0x17,0x49,0x6f,0x23,0x20,0xd4,0x10,0xa0,0xcf,0xdb,
+  0xfa,0x8f,0x66,0xf0,0xcf,0x93,0x7a,0x64,0x23,0xb7,0x12,0xfa,0xc4,0x25,0x80,0xf3,
+  0xd5,0x02,0xdd,0xcb,0x3f,0xb6,0xfe,0xd3,0x23,0x9a,0xfc,0x13,0xfd,0x87,0xc8,0x1d,
+  0xf0,0x5b,0xd4,0x78,0x69,0xed,0x86,0x55,0x8b,0x74,0x2f,0xff,0x38,0xf4,0x9f,0x85,
+  0x56,0xbe,0x3d,0x18,0xca,0x09,0x37,0x30,0xef,0x2d,0xc5,0x69,0x16,0xe5,0xe7,0x1f,
+  0xf8,0xb7,0x29,0xf8,0x57,0x52,0xa4,0x72,0xf8,0xa6,0x7b,0xa7,0xab,0xfe,0x70,0x74,
+  0xb2,0x86,0x95,0x2d,0x86,0x46,0xb6,0xfe,0x43,0xf8,0xa7,0x4f,0xc3,0x8b,0x4c,0x57,
+  0x8c,0x70,0x3b,0xa1,0x4a,0x5a,0xf3,0x25,0xb7,0x80,0xe6,0x9f,0xb3,0xa8,0x0f,0xbe,
+  0x63,0xe8,0x3f,0x2c,0xfe,0x00,0x78,0xbe,0x82,0xbf,0x55,0xb9,0xff,0x85,0x2d,0xa1,
+  0xaa,0x93,0x3f,0x54,0xdb,0x1e,0xf1,0x3d,0xb8,0x39,0xf4,0x1f,0x9a,0x7f,0x80,0xd3,
+  0xe5,0x36,0x55,0x51,0x7e,0xb8,0x92,0x5b,0xeb,0x7c,0xb0,0x8d,0x79,0xf5,0x1f,0xcb,
+  0x5f,0x8d,0xd7,0xb9,0xc1,0x75,0x75,0xe9,0x48,0x27,0xff,0x33,0x23,0x6d,0x2e,0xce,
+  0xcc,0x09,0x78,0x7e,0xc4,0xfc,0x63,0xf2,0x92,0x8e,0x79,0xf8,0x1b,0x35,0x25,0x44,
+  0xb9,0x39,0xbd,0xbe,0x7a,0x94,0x65,0xeb,0x0f,0xc9,0x56,0xd2,0xce,0xcd,0x19,0x87,
+  0x0f,0x60,0x85,0x2e,0xe9,0x0e,0xfd,0x07,0xa6,0x05,0x8f,0xfe,0x83,0x28,0xff,0x74,
+  0x54,0x7c,0x04,0xe7,0x1f,0xac,0x56,0xd6,0xfe,0xbc,0x39,0x40,0xff,0x51,0x19,0xff,
+  0x90,0x7a,0x47,0x1e,0xea,0x7f,0x59,0xfc,0xa1,0xd2,0x2d,0xc6,0x3a,0xc4,0x0e,0xab,
+  0xde,0x85,0xf3,0xf0,0x0f,0xde,0x5d,0xca,0x46,0x23,0x3e,0xf0,0x0b,0x55,0x81,0x6d,
+  0x60,0xe6,0x67,0x22,0x83,0x0c,0xa7,0x8f,0xc2,0x46,0x9f,0xfe,0x03,0xc7,0x63,0xa4,
+  0xbf,0xc0,0x67,0x85,0x0b,0xea,0x72,0x7d,0x01,0xe2,0x17,0x30,0x7f,0xe9,0xc6,0xd0,
+  0x4b,0x9c,0xfc,0x43,0xea,0xd7,0xc3,0x3a,0x86,0x96,0x29,0x68,0x82,0x72,0xdd,0x2e,
+  0x5b,0x57,0x90,0x5f,0xff,0xb1,0xf9,0x67,0xaa,0x85,0x18,0xe5,0x13,0xfc,0x4d,0x64,
+  0xc9,0x3e,0xec,0x2b,0x87,0xfe,0x23,0x7f,0x4c,0x69,0xe7,0x0a,0x3a,0x8e,0xee,0x22,
+  0xc6,0xf4,0xec,0xf4,0x9f,0x61,0x44,0x8c,0x30,0x36,0x54,0x5f,0xff,0xcb,0xd6,0x7f,
+  0xf0,0xf3,0x97,0x23,0xda,0x77,0xcd,0xa4,0xff,0xa8,0x95,0x57,0x55,0xd7,0xaf,0x1f,
+  0xd8,0x9f,0x1a,0x61,0xfb,0x27,0x1b,0x7a,0xcd,0xa7,0xf6,0x04,0xe8,0x3f,0x41,0xfc,
+  0xe3,0xbf,0x6c,0x10,0xff,0xe0,0x7a,0xe4,0x5d,0xed,0xcd,0x02,0xfd,0xaf,0x6c,0xd1,
+  0xea,0xfc,0x8f,0x5d,0x01,0xfc,0x93,0x0e,0xcd,0xf3,0xa9,0x1f,0x7e,0xc3,0xd9,0xff,
+  0x12,0x28,0xe4,0x0c,0xbb,0x8c,0x6c,0x34,0x59,0x33,0x1c,0xc0,0x3f,0x0b,0x7f,0x4d,
+  0xd4,0x1e,0xbd,0x04,0xd3,0x8e,0x6a,0x81,0xd0,0x4d,0xd5,0x21,0x04,0x79,0xf8,0xa7,
+  0x07,0xd7,0x2f,0x6f,0x34,0xa6,0xf4,0x33,0x5e,0xfd,0x87,0xed,0x9f,0xc1,0xdb,0xf6,
+  0xf8,0x9e,0x16,0x87,0x15,0x6f,0x3e,0x71,0xea,0x3f,0xff,0x19,0xe0,0xe6,0x56,0xcf,
+  0x88,0x43,0xff,0x99,0x3b,0x10,0x10,0xc6,0x76,0xcf,0xc8,0x79,0xb6,0x3f,0x73,0x36,
+  0xff,0xd8,0xb2,0x0f,0xc5,0x1e,0x5b,0xff,0xf1,0xf3,0x4f,0xd0,0x63,0x78,0x1e,0xfe,
+  0xb1,0xd5,0x0c,0xcb,0x10,0x26,0x43,0x33,0xf2,0x4f,0x90,0x8c,0x53,0x88,0x7f,0x0a,
+  0xce,0x0f,0xe2,0x1f,0x87,0x0c,0xa2,0xe5,0xef,0x7f,0x35,0xd8,0xfd,0x2f,0xdb,0x4d,
+  0xe4,0x1d,0x39,0x6b,0xf7,0xbf,0xca,0x28,0xb4,0xcc,0x19,0xd3,0xde,0xcb,0xa7,0x6f,
+  0x04,0xf0,0x4f,0x17,0xff,0x67,0xc3,0xd8,0x19,0x34,0xff,0x14,0xbb,0x7f,0x1b,0x64,
+  0x06,0x39,0xba,0x85,0x3d,0xcd,0x97,0xd4,0x59,0xf0,0x4f,0x90,0xcc,0xe5,0xf0,0x37,
+  0x48,0xff,0x29,0x14,0x4f,0xba,0x1f,0xb4,0xca,0xf5,0xf9,0x65,0x1c,0xd3,0x58,0x8c,
+  0xf9,0xc7,0xd6,0x1f,0x42,0x87,0x67,0x9a,0x4f,0xf4,0x9f,0x20,0xfe,0xc9,0x9a,0x8d,
+  0x30,0x62,0x8c,0x7a,0xf9,0x87,0xed,0x7f,0xc6,0x3f,0x84,0x76,0xfe,0x1d,0x1b,0x51,
+  0x6a,0xcc,0xc0,0x3f,0xc9,0x62,0xc7,0x6d,0xe2,0x15,0x2e,0x86,0x04,0x56,0x5f,0x42,
+  0x76,0xb7,0x08,0x59,0xb7,0xed,0x59,0x1f,0x0f,0xe4,0xd8,0xf5,0x09,0xff,0xf4,0x59,
+  0xb4,0xa3,0xbc,0x4d,0xb1,0xe7,0x0f,0x5e,0xfe,0xb1,0xf5,0x9f,0x85,0x76,0xbe,0xed,
+  0x37,0xf3,0xb9,0x57,0xe8,0x70,0xf3,0x8f,0x59,0xbf,0xc6,0x8c,0x6a,0x75,0xae,0xcd,
+  0x90,0x7d,0x58,0xd9,0xba,0xca,0xf8,0xc7,0xa5,0xff,0xf4,0x91,0xfe,0x17,0xd1,0x7f,
+  0xb6,0x12,0x10,0x7a,0xd6,0x5e,0xf6,0x45,0x6a,0xb8,0xfa,0x5f,0x76,0xbe,0xda,0xaa,
+  0x98,0xb2,0x0f,0x1b,0x41,0xf9,0xf9,0x27,0x28,0xed,0x30,0x23,0x80,0x7f,0x70,0xbe,
+  0xe5,0xbc,0x69,0x33,0xa8,0xff,0x05,0x57,0xac,0x7a,0xb7,0x8a,0x14,0xfa,0x44,0xc0,
+  0xfc,0x9d,0x84,0x7f,0xe8,0xf5,0x09,0xff,0x9c,0x33,0x92,0xf6,0x1c,0xbb,0xcc,0xc9,
+  0xc4,0x58,0x8c,0x0d,0xd1,0xa7,0xff,0x6c,0x16,0xd6,0xba,0x65,0x9f,0x35,0x81,0x7a,
+  0x8e,0xcd,0x3f,0x45,0x71,0x26,0xfb,0x08,0xde,0x69,0xd4,0x68,0x76,0xf2,0x4f,0x1c,
+  0x0e,0x59,0xd1,0x10,0x8e,0x8a,0x76,0x58,0x06,0x18,0x21,0xac,0xf1,0xf2,0x0f,0x0e,
+  0xcb,0x69,0xe3,0xe9,0xdb,0x70,0xf3,0x88,0xa5,0xff,0x44,0xb0,0xbf,0x1a,0xe5,0x1f,
+  0x9e,0x4e,0x37,0xf4,0x1f,0xa2,0x17,0x91,0x6a,0x75,0x23,0x44,0x8e,0x6d,0xd4,0x50,
+  0xc7,0xed,0x08,0xe4,0x4a,0x02,0xf8,0xe7,0x26,0xd9,0x8d,0x8a,0xe4,0x68,0x7b,0x05,
+  0xf5,0xbf,0x64,0x06,0x39,0x53,0xc4,0x50,0x62,0x81,0xfd,0x2f,0x08,0xe2,0x1f,0x62,
+  0x00,0x7e,0xbe,0xf0,0xef,0x07,0x27,0xff,0xb8,0x69,0x53,0x15,0x8f,0xcd,0xb6,0xff,
+  0x65,0x9c,0x36,0xf1,0x9d,0x3f,0xc9,0xdf,0xff,0x32,0xa2,0x51,0x31,0xfb,0xfe,0xd7,
+  0x15,0x74,0x06,0xd5,0xc1,0xda,0x37,0x0a,0xeb,0x3f,0xac,0xff,0x55,0x3d,0xa5,0x6c,
+  0x87,0xea,0xe6,0xb2,0x13,0x01,0xe7,0x97,0xec,0xfe,0x57,0xd6,0xee,0x7f,0x9d,0x83,
+  0x76,0x01,0x32,0xf8,0x79,0xca,0xff,0xfc,0xe5,0xe4,0x9f,0x45,0x0e,0x0c,0x18,0xa8,
+  0x39,0x5c,0x4a,0xf4,0x10,0x1f,0xff,0x08,0x74,0xbf,0xb5,0x88,0xf8,0x6a,0xb4,0xed,
+  0xf5,0x3f,0x4a,0xd7,0xe6,0x1d,0xd5,0xbc,0x44,0x8f,0xfd,0xd8,0xfd,0xaf,0x62,0xba,
+  0x1e,0x75,0xa1,0x15,0x9f,0x0c,0xff,0x47,0x62,0x9c,0x8c,0xa6,0x03,0xe2,0x33,0xc2,
+  0xe2,0xdf,0x53,0x74,0x05,0x3e,0x42,0x75,0x64,0xfe,0x55,0x79,0x0d,0xac,0x44,0xd2,
+  0x31,0xa3,0x3f,0x6b,0x74,0xc4,0xd8,0xf9,0x1f,0x27,0xff,0x90,0xfc,0x59,0x45,0x92,
+  0xc6,0x1f,0xbb,0xf1,0x63,0x17,0x2a,0x6b,0xb5,0xfa,0xe9,0xec,0x20,0x90,0xe8,0xed,
+  0x7f,0xf5,0xa1,0x2a,0xe2,0xd4,0x59,0x78,0x11,0x2d,0x4d,0x8a,0x39,0xcb,0x5f,0xd1,
+  0x71,0xfe,0x67,0xdc,0xa3,0xff,0x28,0x38,0x68,0xd5,0xc4,0xd8,0x78,0xf2,0x6e,0x08,
+  0x4b,0x6e,0x85,0x5f,0x74,0xf3,0x0f,0x81,0x9c,0x23,0xb8,0x4c,0x94,0xe4,0xe0,0x32,
+  0x34,0x6a,0x52,0x96,0x8f,0x19,0xd8,0x13,0xa7,0xfc,0x13,0x77,0xf3,0x8f,0xa3,0x1e,
+  0x75,0xab,0x29,0x58,0xdc,0x31,0x6b,0xfe,0x81,0xc9,0x8a,0x94,0x2a,0x75,0xcf,0x19,
+  0x93,0x67,0xa1,0xff,0x18,0xd5,0x56,0xc5,0xfb,0xff,0x85,0xfe,0x82,0xfc,0x23,0xd4,
+  0xc2,0x4b,0xb4,0x5f,0x43,0xbe,0x15,0x83,0xeb,0x35,0xfd,0x88,0x60,0xf3,0x8f,0x56,
+  0x2f,0x24,0x1e,0x8b,0x15,0xee,0x7f,0x35,0x88,0x69,0xd6,0xef,0x43,0x66,0x23,0x66,
+  0x95,0xdf,0x5f,0x47,0xff,0x6b,0xa1,0xab,0x9a,0x37,0x91,0x83,0x3d,0x33,0xf1,0xcf,
+  0x2d,0x4b,0xed,0x41,0xb7,0xf0,0x7c,0xa9,0xd5,0xd0,0x4f,0x9a,0xf2,0x9d,0xff,0xb1,
+  0xf9,0xe7,0x92,0x61,0x7c,0x57,0xab,0x50,0x0a,0xf5,0xbf,0x2c,0xfe,0xd9,0x8e,0xbd,
+  0x5b,0xfd,0x2a,0x24,0xd2,0xa2,0xdc,0x1c,0x74,0xde,0x29,0x1f,0xff,0xb4,0x94,0x76,
+  0x05,0x9c,0xbf,0xb2,0xfb,0x5f,0xda,0x5c,0x0f,0xcf,0xc4,0x77,0x45,0x0a,0xe9,0x3f,
+  0x76,0xff,0x8b,0x7c,0x2b,0xe6,0xed,0x7f,0xd1,0xeb,0xfb,0xf8,0x47,0xda,0x12,0xa4,
+  0xff,0xd8,0xfd,0xaf,0x0e,0xcc,0x3f,0x21,0x02,0x39,0x15,0x37,0x76,0x3f,0x27,0x2e,
+  0x41,0x3d,0x1b,0xda,0x7a,0x18,0x11,0xc9,0x79,0xfb,0x5f,0xa4,0xff,0x8e,0xda,0x70,
+  0x34,0x44,0x25,0x48,0xff,0x51,0x3c,0xfd,0x2f,0x93,0x16,0xb6,0xc0,0x92,0x36,0x71,
+  0x9c,0xdb,0x57,0xa8,0xff,0x45,0xf5,0x9f,0x4d,0x7c,0x3f,0xbc,0x4d,0xea,0xcb,0x26,
+  0x7e,0x51,0xa1,0xfe,0x97,0xcd,0x3f,0x39,0x92,0x3d,0xd0,0xc3,0x41,0xf9,0xdc,0xd1,
+  0xff,0x2a,0xba,0xda,0x72,0x1d,0xd5,0x93,0x22,0xf5,0x06,0x5c,0xc4,0x86,0xf4,0xcf,
+  0x76,0xff,0x82,0xd4,0xaf,0x15,0xde,0xfe,0xd7,0x7e,0x5c,0x64,0x0f,0x90,0x45,0x8e,
+  0x76,0xec,0x44,0x77,0x6f,0x11,0x9f,0xa9,0x58,0xe0,0x5b,0xbf,0x93,0x37,0x88,0x77,
+  0xdf,0x32,0xe6,0x4b,0x27,0xa0,0xaa,0xab,0xb4,0xb5,0xda,0x35,0xff,0x6e,0xdd,0xdd,
+  0xff,0x32,0xf2,0x4f,0xad,0x01,0x39,0x70,0x00,0x62,0x9b,0x4b,0x83,0xf4,0x34,0xbb,
+  0xff,0x15,0x33,0xfa,0x17,0xaf,0x61,0xa7,0x4a,0x7a,0x8a,0xbe,0x80,0x24,0x2a,0x33,
+  0xf3,0x27,0xf3,0x77,0xb9,0xd9,0xff,0xb2,0xd7,0xd3,0x4b,0x07,0x3f,0x85,0xff,0xe2,
+  0x52,0x5d,0xe5,0xff,0x11,0x78,0xfe,0xc7,0xc9,0x3f,0xec,0xa1,0xfe,0xd6,0xe1,0x7a,
+  0x24,0x8d,0xbb,0xf4,0x9f,0x7c,0xfd,0xaf,0xd2,0x0c,0xf7,0x19,0x1c,0x4f,0x57,0x1f,
+  0x09,0x2f,0x0f,0x3a,0x7f,0xeb,0xe2,0x1f,0x6b,0xb0,0x27,0xfd,0x86,0x50,0xad,0x89,
+  0xc7,0x02,0xe6,0x7b,0xf4,0x1f,0x1c,0x84,0xd2,0x64,0xf3,0x20,0x1c,0x55,0x0e,0x6e,
+  0x7e,0xd6,0x3a,0x0f,0x3c,0x60,0xc6,0x87,0xf7,0x9e,0xff,0x91,0xe2,0xe8,0xc6,0x3a,
+  0x6b,0x3f,0x4c,0x40,0x1d,0x92,0x32,0x56,0x7c,0x22,0x8e,0x46,0x98,0x93,0x7f,0x6e,
+  0x19,0x4e,0x95,0x8d,0xf3,0xa3,0x30,0xa9,0x36,0x22,0xea,0xe6,0x20,0x35,0x86,0x02,
+  0xf8,0x27,0x65,0x62,0xb3,0xd9,0x2d,0x5d,0xe3,0xda,0x3f,0xf5,0xfe,0xfe,0xd7,0x0a,
+  0x02,0x39,0x47,0x2c,0xda,0x91,0x8e,0x71,0xae,0xf3,0xcf,0xd5,0xbe,0xfe,0x97,0x70,
+  0x34,0x14,0xd7,0xb7,0x3b,0x7e,0x7d,0xd7,0x7e,0x50,0xf2,0xf6,0xbf,0xcc,0xe8,0x89,
+  0x19,0x77,0x3c,0xab,0xf3,0xf5,0xbf,0xec,0x5f,0xdf,0xb5,0x7f,0xea,0xf2,0xf5,0xbf,
+  0xf2,0xe8,0x3f,0x6f,0xe5,0xed,0x7f,0xcd,0x4a,0xff,0x19,0x2d,0xf2,0xfc,0xfa,0x7c,
+  0xd2,0xc9,0x6f,0x47,0xbd,0xfa,0x4f,0xce,0xce,0x3f,0xb3,0xd2,0x7f,0xc6,0x43,0x8b,
+  0xcc,0x43,0xce,0xcf,0x92,0xea,0xaf,0x99,0xd8,0x23,0xe4,0xd7,0x7f,0xfe,0x5a,0x2c,
+  0x27,0x90,0x33,0x16,0x5d,0x4e,0x68,0x47,0x33,0x8e,0x3d,0x0f,0xfb,0x14,0x21,0xa7,
+  0xfe,0x63,0xf4,0xbf,0x06,0x02,0xe2,0x63,0xfa,0xeb,0xd3,0x7f,0xf0,0xa0,0xc9,0x3f,
+  0x56,0x34,0x1a,0x78,0x3f,0x1f,0xba,0xfa,0x5f,0xf0,0x16,0xdc,0xe7,0xca,0x36,0xfe,
+  0xfc,0xe3,0xea,0x7f,0xc9,0x6f,0x99,0xfc,0xc3,0xbc,0xf3,0xf3,0x9e,0xb7,0xff,0x55,
+  0xeb,0xea,0x1e,0xfa,0xf3,0x8f,0xb7,0xff,0x55,0xe7,0x54,0x7b,0x22,0x31,0x9f,0x22,
+  0x14,0xd0,0xff,0xb2,0xab,0xcf,0x9c,0xac,0x30,0x2b,0xfe,0xf1,0x97,0xc5,0xc2,0xfc,
+  0x53,0x40,0xd8,0xf1,0xe8,0x3f,0xa1,0x84,0xba,0xa6,0xe0,0xfc,0x20,0xfd,0x27,0x1c,
+  0x20,0x04,0x15,0xd4,0x7f,0xfc,0x65,0x37,0xa8,0xff,0x55,0xc6,0xfa,0x5f,0x05,0xf4,
+  0x0d,0x37,0xff,0x7c,0xea,0xfa,0x76,0x84,0x77,0xf0,0xa1,0x85,0x46,0xa7,0x38,0x67,
+  0xff,0x2b,0x67,0x9e,0x7f,0xf6,0x1f,0xfb,0xb1,0xf9,0x07,0x9c,0xfc,0x73,0xc0,0xec,
+  0x7f,0x51,0xef,0x2a,0x06,0xe4,0x02,0xfd,0x2f,0xcc,0x3f,0x2f,0xc1,0x53,0x33,0xe8,
+  0x3f,0xee,0xfe,0x17,0x5e,0xff,0x83,0x85,0xf5,0x9c,0x80,0xfe,0x97,0x43,0x1d,0x9a,
+  0xa9,0xff,0x95,0xef,0xbc,0x59,0xbe,0xfe,0xd7,0x4f,0x0c,0xc8,0x01,0xaa,0xf6,0x30,
+  0xc3,0xa9,0xff,0xb0,0xeb,0xb3,0xfc,0x23,0x14,0xc8,0x3f,0xde,0xfe,0x17,0xbe,0x49,
+  0x7f,0x5a,0xec,0x3f,0xf6,0x13,0xd4,0xff,0xea,0xf4,0xd0,0xce,0x7f,0x07,0x9d,0xff,
+  0xb9,0xac,0xb0,0xfe,0xd7,0xed,0xbd,0xe4,0x35,0x13,0x3d,0x10,0x7b,0x4c,0xa3,0x24,
+  0x53,0xd3,0xcf,0xe2,0xcf,0x59,0xcf,0xef,0x8b,0x27,0xf9,0x29,0xf5,0x2d,0xfb,0xfc,
+  0xaa,0xd5,0xff,0xba,0x8e,0x8e,0x8c,0x95,0xbb,0xf5,0x9f,0x1d,0x45,0x9f,0xe0,0x45,
+  0x6e,0x67,0xab,0x4d,0x52,0xe3,0x59,0xb8,0xb8,0xb9,0x4f,0xab,0x22,0xd2,0xd0,0xe5,
+  0x0e,0x7a,0x7d,0x40,0xfb,0xe0,0x45,0xcb,0x3b,0x89,0xb9,0xb9,0x17,0xa8,0x10,0xa4,
+  0x54,0x0d,0x86,0xbd,0xfa,0xcf,0xa1,0x42,0xf9,0x5c,0x31,0xf5,0x1f,0x16,0x9f,0x4a,
+  0xd3,0x5f,0xd2,0x9d,0x31,0xbc,0x33,0x1c,0xb7,0x0f,0xba,0x84,0x8e,0x90,0x8e,0x86,
+  0xab,0xff,0x65,0xce,0x2f,0x58,0x8f,0xdc,0xfd,0xaf,0xcf,0xf3,0xd4,0x3b,0xee,0x84,
+  0xcd,0x3f,0x74,0xfd,0xac,0xff,0x15,0x24,0xfb,0xe4,0xd1,0x7f,0xcc,0xc1,0x62,0xf2,
+  0x6d,0xf1,0xcc,0xe7,0x7f,0x24,0xeb,0xb4,0x0f,0xd1,0x7f,0xbc,0xf1,0x91,0xb1,0xd1,
+  0x7f,0xa7,0x57,0xff,0xb1,0xfd,0x95,0xb1,0xc1,0xce,0xc3,0x1f,0x99,0xd3,0x9b,0xbc,
+  0x61,0x1e,0x8d,0x76,0x9d,0xff,0x51,0x4c,0xa7,0xda,0xad,0xf3,0x3f,0xd7,0xda,0x2d,
+  0x7f,0x5f,0x25,0xff,0xa1,0x1a,0xd0,0xff,0xfa,0xdc,0xda,0x2d,0xf2,0x34,0x79,0xff,
+  0x6b,0xd4,0xde,0x3f,0x6f,0x06,0xf5,0xbf,0xae,0xc2,0x67,0x36,0xed,0x2c,0xcd,0xb6,
+  0x74,0xcf,0xf6,0xfc,0xb3,0x61,0x28,0xf3,0xe5,0x19,0xf4,0x1f,0x37,0xff,0x20,0xb1,
+  0x7b,0x86,0xfe,0x97,0xfb,0xd7,0xaf,0x8d,0xed,0x69,0x67,0x23,0x0c,0x5d,0x9c,0xfd,
+  0xaf,0x13,0xce,0xfd,0xd0,0x08,0xf4,0x45,0xb0,0x59,0xf4,0xbf,0xd2,0x37,0xe0,0x7e,
+  0xb1,0xcc,0xf7,0x3e,0x82,0xa7,0xff,0x45,0xf7,0x03,0x18,0xb4,0x06,0xe2,0xee,0x82,
+  0xef,0x7f,0x39,0xf4,0x9f,0xb3,0x98,0x87,0x6b,0x47,0x44,0x80,0xc2,0xfd,0xaf,0x45,
+  0xe6,0x69,0x67,0x83,0x7f,0x90,0x92,0x15,0xd7,0xce,0xd0,0xff,0x92,0xcc,0xd3,0xce,
+  0x98,0x7f,0xd0,0x97,0x68,0x99,0x2e,0xc1,0x8c,0xfc,0x83,0x83,0x30,0xb0,0x93,0xbc,
+  0xff,0x75,0x5d,0x4e,0x8d,0x3c,0x65,0xf6,0x4f,0x53,0x79,0xfb,0x5f,0x34,0x08,0x25,
+  0x1b,0x0d,0x1a,0x97,0xba,0x9c,0xf1,0x79,0xdf,0xdf,0xff,0xa2,0x4f,0x8b,0x46,0xfe,
+  0x8c,0xeb,0x9d,0xeb,0x66,0x3c,0xff,0x6c,0x3a,0x55,0x61,0xbc,0xf8,0xf6,0x61,0xcc,
+  0xd5,0x08,0xdb,0xeb,0xef,0x7f,0xf9,0xdf,0xf6,0xf2,0xc7,0xd3,0xdb,0xff,0x22,0x6d,
+  0x82,0x55,0x2d,0xf2,0x37,0xd0,0x88,0xa4,0xc7,0x9d,0xe7,0x9f,0x2f,0xe4,0xef,0x7f,
+  0x61,0xa3,0x41,0x4d,0xc9,0x0f,0x77,0xce,0x56,0xff,0xf9,0xb8,0xf3,0x34,0xa4,0x9a,
+  0xc5,0x00,0x10,0xe2,0xfc,0xfc,0xb3,0xbd,0x8b,0xfb,0x44,0xdc,0x96,0x36,0xf4,0x1c,
+  0x7f,0x47,0x26,0x4f,0xff,0x6b,0x1b,0x24,0x9a,0xc3,0x81,0x7a,0x45,0x70,0xff,0x6b,
+  0x33,0x24,0x1e,0x0a,0xcb,0x5c,0xc7,0xac,0xf8,0x67,0x55,0x4e,0x26,0xef,0x7f,0x3d,
+  0xa7,0x05,0x80,0x90,0xa3,0xff,0xc5,0xf4,0x9f,0x39,0x63,0xc5,0x93,0x78,0xb7,0x2c,
+  0x19,0x99,0x65,0xff,0x8b,0xfb,0x0a,0xd3,0x4e,0xbd,0x5a,0x36,0x12,0x00,0x8a,0x36,
+  0xff,0x38,0xf4,0x1f,0x62,0xdc,0x13,0x0a,0x23,0x3e,0x3d,0x03,0xff,0x58,0x4e,0xad,
+  0x0e,0xbd,0xca,0xa5,0xd7,0x95,0x9a,0xef,0xbb,0xd5,0x1a,0x20,0x24,0x90,0xaf,0xd6,
+  0xc8,0x15,0x41,0xfa,0x4f,0x31,0x89,0xde,0x4f,0xc8,0x8b,0x60,0xfe,0x8e,0xe4,0x29,
+  0x17,0xff,0x98,0xe7,0x9f,0xf9,0xf5,0x0b,0x26,0xa1,0xee,0x7b,0x65,0x72,0xc1,0xf3,
+  0x3f,0xbe,0xfe,0x97,0xe3,0x7d,0xb1,0x92,0x3c,0xfd,0x2f,0xab,0xdb,0xa5,0xc1,0x84,
+  0x72,0x3f,0x79,0xdf,0x70,0x56,0xe7,0x7f,0x34,0x6e,0xb2,0xe3,0x35,0xa8,0xea,0x12,
+  0x2f,0x71,0xa6,0xfe,0xb3,0x06,0xf3,0x8f,0x60,0x7e,0x55,0x11,0xd4,0xff,0xe2,0xda,
+  0xd1,0x11,0xbd,0x76,0x6f,0x38,0x48,0x7f,0xb6,0xcf,0x3f,0x3b,0xfa,0x5f,0x23,0xd0,
+  0x27,0x7e,0xeb,0xe4,0x1d,0xd9,0x36,0x9f,0xfe,0x03,0xee,0xfe,0x97,0x05,0x39,0xbb,
+  0xe1,0x6b,0xb4,0x4c,0x2b,0x0f,0xd2,0x7f,0x2e,0xd3,0xed,0xc6,0xf4,0x9f,0x12,0x5c,
+  0xc4,0xe5,0x6b,0xb0,0x7c,0xf3,0xcf,0x93,0x41,0xfa,0x8f,0xad,0xff,0x93,0xf7,0x97,
+  0xbb,0x8c,0x63,0x1b,0x53,0xd0,0x81,0x56,0xd4,0x2e,0x7c,0xcf,0xd0,0x7f,0xac,0x83,
+  0xd0,0x9f,0x9b,0xad,0x31,0x4f,0xff,0x0b,0x19,0x4e,0x8d,0x70,0x48,0xa9,0x92,0xa4,
+  0x67,0xf8,0x47,0x9c,0xeb,0x6f,0xcc,0xfa,0xfb,0x5f,0xca,0x12,0x3d,0x4c,0xfc,0xed,
+  0x08,0xc5,0x20,0x36,0x62,0x3c,0xaf,0xdd,0xcd,0xfc,0x1d,0xcc,0xd7,0xff,0xd2,0x45,
+  0x04,0x8a,0x22,0xde,0xcb,0xf9,0x9f,0x70,0xdd,0xfd,0xaf,0xe3,0xe6,0xb1,0x8d,0x2c,
+  0x4e,0x76,0x0d,0xf3,0xa4,0xff,0x67,0xef,0xfa,0x63,0xab,0xb8,0xb2,0xf3,0x7d,0xf3,
+  0xc6,0x30,0xb6,0x9f,0xed,0xb1,0x81,0x96,0x2c,0x04,0x06,0x03,0x5b,0x97,0xba,0xe0,
+  0xc5,0x88,0xb0,0x0e,0x31,0x83,0x49,0x54,0x16,0xa2,0x80,0x36,0x6d,0xb5,0x2b,0x45,
+  0x91,0x45,0xa8,0x8a,0x54,0xb6,0x62,0x7f,0xfc,0xe1,0x25,0xab,0xcd,0x80,0xc9,0xc6,
+  0x59,0xd3,0xae,0x93,0xcd,0x6a,0x89,0xb2,0xbb,0x7d,0x04,0x54,0x50,0x97,0x56,0x40,
+  0xd2,0x2c,0x34,0x28,0x79,0x10,0x4b,0x71,0x12,0x27,0x58,0xd9,0x54,0x9b,0x1f,0x94,
+  0x7d,0xd1,0xd2,0xc4,0x0d,0x0e,0x71,0x48,0x94,0x3a,0xc1,0xe0,0xce,0x9d,0xb9,0x3f,
+  0xe7,0x9e,0x7b,0x67,0x1c,0x36,0x9b,0x48,0x8d,0xff,0x3a,0x7a,0x1e,0x9e,0xe6,0x1e,
+  0xc6,0xf7,0x7e,0xf3,0x9d,0xef,0x7c,0x67,0x05,0xe9,0x6f,0x8a,0xd6,0x7b,0x1e,0xa8,
+  0x7f,0xd1,0x24,0xbc,0x8e,0xc6,0x56,0xb7,0xa3,0xda,0xc4,0x79,0xd4,0xa6,0xe5,0x7f,
+  0x2e,0xa2,0x71,0x74,0x3d,0xaa,0x19,0xcf,0x7f,0xcf,0xc0,0xff,0xec,0xe0,0xf8,0x27,
+  0xfc,0x6b,0x0a,0x96,0x7b,0x35,0x27,0x76,0x1a,0xf5,0x3f,0xfc,0x7d,0xbf,0x5c,0x3c,
+  0x56,0x5a,0xd4,0x52,0x79,0xd8,0x52,0x11,0x94,0xca,0xff,0x54,0x2f,0x9b,0x52,0x42,
+  0x87,0xdd,0x05,0xe8,0x2b,0xf1,0xfb,0x29,0x96,0xfd,0xc4,0x07,0xdf,0x40,0x52,0xff,
+  0x53,0xff,0xb8,0x43,0x40,0xdd,0x98,0xdf,0x86,0x7e,0x7e,0x38,0xbf,0x55,0xad,0xef,
+  0x70,0xfc,0x73,0x4d,0xb4,0xa8,0x53,0x75,0x17,0xf3,0x43,0x68,0xdc,0x5b,0x85,0xea,
+  0xb6,0xc9,0xe7,0x7b,0xfb,0x10,0xac,0xff,0xf9,0x50,0x84,0xcd,0x11,0x22,0x3a,0xc6,
+  0x18,0x21,0xa8,0xfe,0x75,0x98,0xa3,0x9d,0x91,0xa0,0x37,0x1d,0xff,0x2c,0x6d,0x18,
+  0xcc,0xb1,0xc7,0x80,0x20,0xe4,0xdd,0xe9,0xf8,0x27,0x7e,0x91,0x4f,0x0a,0xcb,0x25,
+  0xfc,0x93,0x53,0x61,0xf0,0x79,0x23,0xfe,0xb9,0x7a,0xfd,0x4f,0xb2,0xd1,0x49,0xc6,
+  0x3f,0x97,0x14,0xd8,0x9c,0xbc,0x7f,0x10,0xff,0x08,0xc7,0x74,0xb2,0xfe,0x0e,0xd7,
+  0xbf,0x5c,0x1a,0x38,0xf7,0x24,0x18,0x21,0x05,0xff,0x48,0x68,0x67,0x04,0xfd,0x1a,
+  0x97,0xbd,0x18,0x23,0x24,0xe1,0x9f,0xf0,0xfd,0xeb,0x1d,0xd2,0x1d,0x40,0x69,0x1f,
+  0xd2,0xf6,0x85,0xdf,0x50,0x26,0xdc,0xa8,0xb4,0x0a,0xe0,0x9f,0x63,0xd5,0x58,0x08,
+  0x17,0x65,0xe3,0x02,0x7a,0x0e,0xcd,0x91,0xf2,0x03,0xe1,0x1f,0x91,0xf6,0x31,0xe9,
+  0x7f,0x98,0xfe,0x79,0x8e,0x9d,0x49,0xff,0x03,0xd1,0x3e,0x99,0xf4,0x3f,0x02,0xed,
+  0x33,0x29,0xfd,0xcf,0xb4,0xf2,0x94,0xac,0xf5,0xaf,0x49,0xf1,0x3f,0x7f,0x38,0xfd,
+  0x4f,0x16,0xfc,0x83,0xe6,0xb3,0xd5,0x95,0xd0,0x98,0x95,0x8a,0x7f,0x38,0xff,0xd3,
+  0x7a,0xae,0x48,0xda,0xb8,0xc2,0x4f,0xf2,0x3a,0xfc,0xf3,0x00,0xa3,0x7d,0xa6,0x9d,
+  0xf3,0x15,0xfc,0x03,0xd5,0xbf,0x4c,0xfc,0x0f,0x58,0xff,0xa2,0xc2,0xef,0xfe,0xe0,
+  0xaa,0xf5,0x3f,0x90,0xfe,0xd9,0xc0,0xe7,0x28,0xf8,0x87,0xf3,0x45,0xff,0x94,0xae,
+  0xff,0x99,0x2c,0xff,0x13,0xd7,0xbf,0x2c,0x95,0xf6,0xd1,0xe8,0x7f,0x8c,0x7c,0x85,
+  0x0e,0xff,0x88,0x32,0x18,0x5f,0xe5,0x7f,0xe8,0xf7,0x63,0xfc,0x13,0xf5,0xbf,0x6f,
+  0xef,0xe6,0xb4,0x4f,0x51,0xc1,0x3f,0xa0,0xfe,0xc7,0xd6,0xf2,0x1b,0xb2,0xfe,0x07,
+  0xe3,0x9f,0xba,0xe3,0xdd,0x21,0xec,0xe9,0x4b,0x1c,0x64,0x08,0xd6,0xff,0x60,0xd9,
+  0xcf,0x47,0x74,0xff,0xe9,0xb2,0xe2,0x17,0x31,0xb8,0xfe,0xc5,0xf4,0x3f,0xdf,0xb2,
+  0x88,0xf0,0xfb,0x5b,0xc0,0xfb,0x1a,0x88,0x7f,0x54,0x18,0x09,0xe2,0x1f,0xc2,0x96,
+  0x8f,0xfe,0x1d,0xa3,0xcd,0x89,0xd0,0x45,0x10,0x3e,0x01,0xf8,0x67,0x14,0x48,0x8b,
+  0xa1,0xfe,0xb5,0x41,0x7f,0xde,0xd5,0x24,0xf0,0x8f,0xf3,0xf1,0xf8,0x1f,0xe3,0xf5,
+  0x2a,0xfe,0x69,0xd9,0x39,0x68,0xb7,0x46,0xc0,0x40,0xca,0x8f,0x9b,0xac,0x7f,0xd5,
+  0x84,0x68,0xc7,0x13,0xd7,0x7b,0xb4,0x3b,0xca,0xcf,0x4b,0x8c,0x08,0xaa,0x51,0xfa,
+  0xbf,0x24,0xb5,0x2a,0x16,0x4a,0xc5,0xfd,0xef,0x94,0x11,0x02,0xf0,0xcf,0xb3,0x35,
+  0x63,0xf9,0x76,0xcc,0xff,0x74,0x4a,0xfc,0x21,0xcc,0xff,0x3c,0x1e,0x2c,0x19,0x75,
+  0x48,0xd9,0xab,0x33,0x53,0xff,0xfb,0x62,0x54,0x49,0x9e,0x87,0xd5,0xe0,0xf3,0x90,
+  0xc0,0x3f,0xb9,0xc5,0x1d,0x3d,0xb8,0xdb,0x2b,0xcc,0xde,0x8d,0x4a,0x3e,0x4f,0x42,
+  0xfc,0xcf,0x4b,0x35,0xa4,0xec,0xd5,0x39,0x15,0x7a,0x1e,0x14,0xfc,0x53,0xae,0x1b,
+  0xad,0x8e,0x60,0x70,0x27,0xf8,0x60,0x28,0xf8,0xc7,0xbd,0x99,0x7c,0xdb,0x4d,0xa9,
+  0xfa,0x67,0xfc,0x3c,0x34,0x77,0x38,0x2d,0x28,0xea,0x76,0xff,0x0e,0xf8,0x3c,0x28,
+  0xf8,0xa7,0xb3,0x89,0x64,0x63,0x63,0xaa,0xfe,0x19,0xe3,0x9f,0xe6,0x2d,0x54,0xfd,
+  0xb2,0x85,0xc2,0x00,0x5d,0xff,0x7b,0x8c,0x7f,0x4e,0x16,0x08,0xfe,0xd9,0xa2,0xf4,
+  0xbf,0x27,0xf9,0x9f,0xc8,0xff,0x67,0x98,0x66,0xe3,0x46,0x1a,0xe0,0xfe,0xf7,0x11,
+  0x2d,0xff,0xb3,0x96,0xca,0xae,0x7c,0x9c,0x16,0xe7,0x4e,0x83,0xfe,0x39,0xda,0x4f,
+  0x3a,0x54,0xdb,0x1f,0x13,0xfe,0x69,0x8e,0xd4,0x3e,0xb9,0x70,0x75,0x9d,0x69,0xfd,
+  0xef,0x78,0xff,0xb1,0x38,0xed,0xe3,0x83,0xf9,0x4c,0xe2,0x9f,0x55,0x4c,0xed,0xb3,
+  0x13,0xee,0x7f,0xd7,0xe2,0x1f,0x97,0x1d,0x43,0x73,0x0d,0xf8,0x67,0xe5,0xe6,0xc2,
+  0x24,0xf1,0x0f,0x95,0xf1,0x7c,0x35,0x23,0xfe,0x71,0xe2,0x7e,0xf9,0xac,0xf8,0x67,
+  0x1d,0x28,0xfb,0xd1,0xe3,0x1f,0xa7,0x10,0xe4,0xf5,0x8d,0xff,0x0a,0xfe,0x91,0xd5,
+  0x3b,0xe7,0x92,0xc2,0xe6,0x35,0x49,0xfc,0xb3,0x6a,0x4b,0x21,0xa6,0x7d,0x6e,0xf0,
+  0xa1,0x44,0xdd,0x21,0xe1,0x1f,0x27,0x04,0x39,0x7d,0x4e,0x60,0x79,0x38,0x40,0x4e,
+  0x26,0xfc,0xb3,0xd1,0x21,0x36,0x47,0xab,0x2b,0x53,0xf5,0xcf,0x39,0x2c,0xfb,0x71,
+  0x28,0x8d,0x56,0x99,0x09,0xff,0x6c,0x6c,0x8e,0x68,0xbd,0xdc,0xca,0xce,0x3f,0xcf,
+  0x84,0x7f,0xc2,0x0f,0xab,0xa3,0xdf,0xae,0x9d,0x93,0x05,0xff,0xac,0xc4,0x6d,0x5f,
+  0x65,0xda,0x08,0x9f,0x8a,0x7f,0x30,0x6d,0xee,0x45,0x68,0x67,0xc9,0x03,0xeb,0x32,
+  0xe1,0x9f,0x32,0xfd,0x7b,0xd9,0x05,0xf2,0xa5,0x0a,0xfe,0x19,0xa2,0x7f,0xbf,0xa8,
+  0x0a,0xae,0x7f,0xd1,0xef,0x8f,0xf1,0xcf,0xca,0xce,0x66,0x8a,0x76,0x0a,0x60,0xfd,
+  0x4b,0x83,0x7f,0x72,0xe1,0xea,0x40,0xfc,0x63,0xd1,0xfc,0x10,0xfd,0x73,0xb9,0x40,
+  0xde,0xd6,0x3d,0xf0,0xfc,0x52,0xf4,0xcf,0xa5,0xa6,0x3b,0xf1,0xdd,0x06,0xcd,0x0e,
+  0x59,0x48,0x73,0xac,0xe8,0xd6,0xe1,0x1f,0x9f,0x5c,0xb6,0x44,0x5e,0x2f,0xac,0x7f,
+  0x6e,0xc5,0xcf,0x1b,0xd3,0xbb,0xa6,0xe1,0x1f,0xbc,0xde,0x95,0xfd,0x54,0x2d,0xe9,
+  0x81,0xfd,0x3b,0x12,0xfe,0x71,0xc4,0xdf,0xda,0x99,0xf0,0x4f,0xbb,0x5f,0x20,0xdb,
+  0x38,0x2a,0x40,0xe7,0x9d,0xca,0xff,0x34,0x11,0x3d,0x73,0x63,0x55,0xa2,0x11,0xa9,
+  0x0d,0xc0,0x3f,0xb9,0xc5,0xa5,0xb5,0xe4,0x74,0xf3,0x9c,0x6c,0xf8,0xc7,0x69,0x69,
+  0x88,0xb2,0xe1,0x56,0xc5,0xb2,0x1f,0xac,0x98,0x6a,0x60,0xfd,0x71,0x09,0xfc,0x83,
+  0xef,0x3f,0x5a,0xdd,0xbc,0x76,0x77,0x36,0xfe,0x5a,0x22,0xfb,0x11,0xf4,0xcf,0x12,
+  0xfe,0xc1,0xdb,0x4e,0xe4,0x5f,0xe7,0xdf,0x80,0x44,0xd9,0x0f,0x3e,0xbf,0xae,0x4f,
+  0xe0,0x9f,0x19,0xcc,0xff,0x87,0x1b,0x29,0xb8,0xa4,0x11,0x0c,0xc4,0x3f,0x7f,0x4f,
+  0x41,0xce,0xa0,0x45,0x68,0x9f,0x91,0xac,0xf5,0xaf,0x7d,0xf1,0xea,0x06,0x89,0x02,
+  0x0a,0xc4,0x3f,0x15,0x87,0xf4,0xb4,0x09,0xc4,0xff,0x54,0xe8,0x60,0xb0,0xf8,0x20,
+  0x19,0xf9,0x9f,0x35,0x46,0xfc,0x83,0x0e,0x71,0x7e,0x29,0x49,0xfb,0xe0,0x60,0xb9,
+  0xae,0xfe,0x45,0xee,0xbf,0x36,0x05,0xff,0xcc,0x60,0xfc,0xcf,0x08,0xe8,0xff,0xb3,
+  0x40,0xc1,0x3f,0x01,0x3d,0xfd,0x0b,0x98,0x06,0xa9,0x4a,0xeb,0xff,0xaa,0xa5,0xfa,
+  0xe7,0x17,0xd0,0xad,0xe8,0x7b,0x4a,0x23,0xd8,0x32,0xb0,0xfe,0x55,0x8a,0xdb,0xbe,
+  0x72,0x77,0x31,0xda,0x50,0x0a,0x64,0xfc,0xf3,0x1e,0xd5,0xff,0x40,0xf9,0x01,0xf1,
+  0xcf,0x3c,0x10,0xf6,0x34,0x68,0xf1,0xcf,0x42,0xb6,0xba,0xd7,0xd9,0x32,0x2b,0x0d,
+  0xfc,0x4f,0x94,0xb4,0x41,0x87,0x25,0x36,0x0d,0xff,0x3c,0x26,0x55,0xbb,0xd2,0xf1,
+  0x4f,0xdb,0xc7,0xea,0xff,0x22,0x42,0x17,0x0b,0x1b,0x01,0xb1,0xf3,0xae,0xd6,0xc0,
+  0xff,0xbc,0xc2,0x8d,0x80,0xb4,0xf8,0x27,0x17,0x1e,0xd3,0x56,0xf4,0x61,0x3f,0xae,
+  0x7f,0xb1,0x42,0x58,0x18,0x74,0x40,0xf8,0x27,0xd2,0x3f,0x6f,0xf5,0x67,0xe1,0xd3,
+  0x9f,0xb5,0xbd,0xef,0xd5,0xe3,0x9f,0x82,0xd0,0xff,0xc5,0xf0,0x0f,0x16,0xe2,0x4e,
+  0x4d,0xa9,0x7f,0xe5,0xcf,0x15,0x95,0xc0,0xa8,0x7f,0xfe,0x6f,0x3d,0x3e,0x84,0xf9,
+  0x9f,0x60,0x85,0x9e,0xff,0x61,0x7a,0x12,0xa8,0xff,0x0b,0xe8,0x77,0x33,0xf0,0x3f,
+  0x8d,0x26,0xff,0x1f,0x85,0xff,0x49,0xd1,0xff,0x5c,0x55,0xff,0x57,0x56,0xfe,0x27,
+  0x02,0x39,0x9b,0x32,0xf3,0x3f,0xe9,0xfa,0x43,0xb0,0xfe,0xa5,0xc2,0x00,0x0d,0xfe,
+  0xd1,0xd2,0x3e,0x10,0xfe,0xa9,0xa1,0xf8,0x67,0xcd,0xdb,0x7d,0x34,0xf0,0x53,0xfb,
+  0xbf,0xa2,0x63,0xcb,0x23,0xc1,0x44,0x0a,0xfe,0x79,0x84,0xb4,0x9d,0x46,0x77,0x5b,
+  0x0b,0xe1,0x37,0x4d,0xff,0x97,0x36,0x80,0xfb,0xbf,0x22,0x7d,0x4b,0x15,0x4f,0x63,
+  0x47,0x4a,0xff,0x57,0x6c,0x84,0xc8,0xf9,0x9f,0xbf,0x30,0xf1,0x3f,0x94,0x1d,0x02,
+  0xf1,0x12,0x58,0xff,0x1a,0x27,0xa7,0xff,0x34,0xda,0x11,0x96,0x52,0xff,0x8a,0x8d,
+  0x19,0xa3,0x20,0x69,0x04,0xa4,0xf2,0x3f,0xb3,0x84,0xfe,0x2f,0xb5,0x5e,0x23,0xe1,
+  0x1f,0x9f,0x90,0x3c,0xcf,0x8b,0xc0,0x40,0x56,0x08,0x4b,0xf8,0xc7,0x25,0x8b,0xba,
+  0x4c,0xab,0x7b,0xe3,0x28,0xd9,0x28,0x27,0xe0,0x9f,0xaf,0x48,0xb6,0x3f,0xd7,0x97,
+  0x36,0x40,0xe7,0x3b,0x50,0xff,0xc2,0xf8,0xf9,0xb7,0x89,0xc7,0x46,0xcb,0xff,0x48,
+  0x68,0x67,0x93,0xf8,0xc9,0xce,0x04,0xfe,0x69,0xaa,0x30,0xfc,0x59,0xf1,0xf5,0xea,
+  0xf5,0xcf,0x1a,0xfc,0x43,0xef,0x07,0xd9,0x69,0xfa,0xe4,0x93,0x38,0x3f,0xdc,0xdf,
+  0xd2,0xe5,0xe7,0xbb,0xa7,0xad,0x7f,0x0d,0x83,0xfd,0x5f,0x14,0xed,0x18,0xf9,0x1f,
+  0xee,0x7f,0x78,0xc1,0x23,0x81,0x5a,0x0f,0xe5,0xfd,0x5f,0x25,0xc6,0x07,0x8a,0xcf,
+  0x83,0x81,0xff,0x41,0xaa,0xfa,0xf7,0x76,0x19,0x18,0xc0,0xf5,0xaf,0x15,0xf9,0x41,
+  0xe7,0xbd,0xdc,0xb2,0x93,0x62,0xdb,0x3b,0xc4,0xff,0xcc,0x8e,0xf3,0x33,0x37,0xc2,
+  0x3f,0x98,0xf6,0x39,0x4c,0x69,0x1f,0xd0,0xff,0xc7,0x91,0xf1,0x67,0x9b,0x98,0x96,
+  0xf9,0x80,0xfe,0x79,0x38,0x07,0xec,0x27,0xb6,0x5e,0xff,0x8c,0x78,0xfd,0xcb,0xd0,
+  0xef,0x2f,0xea,0x9f,0xf9,0x7e,0x1e,0xd5,0x5b,0x99,0x9f,0x76,0xa5,0x84,0x7f,0xd8,
+  0xfd,0xd8,0x58,0x1d,0xc1,0xd0,0xce,0x76,0x18,0xff,0x7c,0xc8,0xf1,0x0f,0x3b,0x8f,
+  0xfe,0x04,0x9f,0x3e,0xdf,0x97,0xcf,0x23,0x1b,0xc0,0x3f,0xf4,0xbc,0x9b,0x86,0xf1,
+  0x8c,0x46,0x28,0xfb,0x14,0xc7,0x3f,0x88,0xd6,0xb3,0xf2,0x86,0x42,0x8c,0xdc,0xff,
+  0xc5,0xfc,0xfa,0x0c,0xf5,0x2f,0xba,0x5e,0xa1,0xfe,0xa5,0xca,0x7e,0xa0,0xfe,0xaf,
+  0x6b,0xc4,0xfe,0x77,0x4b,0x73,0xfe,0x9e,0x65,0xfd,0x5f,0xc7,0x6a,0xb2,0xe0,0x81,
+  0x37,0xb8,0x9e,0x07,0xf3,0x3f,0x76,0x94,0x9f,0xf7,0x13,0x97,0x0d,0x31,0xff,0x1f,
+  0x81,0xff,0x99,0x69,0xac,0x7f,0xb9,0x7a,0xff,0x67,0xba,0xba,0x59,0xd0,0x7a,0x05,
+  0xfd,0xf3,0x74,0x96,0xf6,0x91,0x4c,0xfa,0x67,0xdb,0xbc,0xde,0x1c,0xf6,0xb7,0x9c,
+  0x2f,0xe8,0x9f,0xdd,0xfd,0x0e,0x65,0xc3,0x3c,0xed,0x3f,0x04,0xfd,0x7f,0x32,0xe1,
+  0x1f,0x64,0x33,0xfd,0xcf,0x58,0x40,0x6d,0x0f,0xf1,0x27,0x3b,0x44,0xfc,0x33,0xe0,
+  0xd1,0xfd,0xc1,0xb9,0x9b,0xfd,0xbd,0x9c,0x34,0xe1,0x1f,0xfa,0x33,0xaf,0x5e,0xd4,
+  0xff,0x68,0xf0,0x40,0xc7,0x00,0xfd,0x7a,0xdc,0xff,0xe5,0x12,0x90,0xf3,0xa2,0x02,
+  0x7b,0x78,0xff,0x57,0x23,0xbd,0xde,0xe1,0x78,0xa0,0xac,0xdf,0xd8,0x4f,0xfd,0x80,
+  0xe6,0xa7,0xd3,0x66,0x22,0xd5,0xb3,0x91,0xed,0xcf,0x3d,0xa4,0x6d,0xf9,0x5c,0xdd,
+  0x77,0xf3,0x73,0xa8,0x11,0xd0,0x50,0xc0,0xf0,0x0f,0xfa,0x19,0xad,0xd6,0x0d,0xf9,
+  0xbf,0x11,0x6e,0x1b,0x2b,0x2a,0x67,0x5b,0x51,0x21,0xfe,0x9b,0x82,0xfe,0x39,0xe0,
+  0xf8,0x47,0xf5,0x6b,0x9d,0x4d,0x3f,0xe1,0xfd,0x5f,0xfe,0x74,0x26,0xea,0x50,0xfd,
+  0x6c,0x99,0xdf,0x9d,0xd0,0xff,0x55,0x21,0xac,0xb7,0x57,0x5e,0x66,0x75,0x33,0xed,
+  0x88,0xe7,0xff,0xbf,0x45,0x77,0x24,0x43,0x7e,0xf8,0xfd,0x08,0xf8,0xe7,0x3d,0xad,
+  0x10,0x5a,0x38,0x1f,0xb9,0xff,0xa1,0xf5,0x94,0x81,0x7f,0x60,0xff,0xbf,0x01,0x3f,
+  0xef,0xca,0xa2,0x10,0x5a,0x8b,0x7f,0x50,0x81,0xe7,0x47,0x94,0x25,0x0c,0x88,0x85,
+  0x30,0x01,0xff,0xcc,0x24,0x6a,0x9f,0x7f,0x4f,0xac,0xf7,0x59,0x0d,0xfe,0xa9,0x61,
+  0x8b,0x1a,0x4d,0x2c,0xf3,0x08,0x8c,0x7f,0xce,0x5a,0xe4,0x21,0x19,0xc7,0x6a,0xb1,
+  0x52,0xcd,0x18,0xc6,0x4b,0xc1,0xaa,0xd7,0x35,0xfc,0xcf,0xcc,0x0b,0xd4,0xe4,0xf0,
+  0x4c,0xe9,0x97,0xbb,0x96,0x8c,0x56,0x1f,0xeb,0x98,0xf0,0xcd,0xfc,0x0f,0x5d,0xa6,
+  0xb7,0x8f,0x08,0xbf,0x85,0xbf,0x2f,0x3b,0x89,0x7f,0x2a,0x0e,0xf1,0xb4,0xeb,0xfd,
+  0x27,0x39,0xfe,0x99,0xb1,0xd5,0x61,0x68,0xf0,0x7c,0x5c,0x0d,0xc4,0x69,0x99,0x23,
+  0x01,0x63,0xfe,0xff,0x2b,0xf4,0x7f,0x9d,0x89,0xfc,0x30,0x7b,0xa3,0xfc,0x58,0x26,
+  0xfc,0xc3,0xf4,0xe7,0xaf,0x91,0x36,0x28,0x3b,0x9a,0xf8,0xa0,0xa9,0x7f,0x15,0x82,
+  0x5e,0x6a,0xfb,0xd3,0x6b,0x2f,0x09,0x83,0x06,0xee,0xff,0x33,0x1d,0xc0,0x3f,0x98,
+  0x7f,0x8e,0xf9,0x8a,0x2c,0xfe,0xcf,0x9d,0xee,0xed,0x8a,0xfb,0x9f,0x80,0x07,0xae,
+  0x53,0xf5,0x3f,0x37,0xa3,0xdf,0x05,0xcb,0x62,0xb4,0x73,0xab,0x2b,0xc0,0x9e,0xa9,
+  0x2d,0xf3,0x5f,0x88,0x47,0x63,0x24,0xfd,0x9f,0x71,0xf6,0x28,0x3e,0x4c,0x36,0x82,
+  0x59,0x49,0xfc,0x13,0xbb,0xb3,0x96,0x6b,0x48,0xfe,0x07,0xc3,0xb4,0x5f,0x09,0xce,
+  0x47,0x2f,0x26,0xf3,0x19,0x23,0x94,0x9c,0x7f,0xb1,0xa4,0xe4,0x6c,0xb3,0xc6,0x8b,
+  0xf7,0xd8,0xcd,0xa7,0xc2,0xe0,0x79,0x5f,0xd5,0xff,0xd0,0xeb,0xbd,0x08,0xff,0x2c,
+  0x89,0xd8,0x9e,0xe0,0x00,0xe1,0xbb,0xa2,0x80,0xf1,0x3f,0xeb,0xe5,0xf9,0x17,0x02,
+  0xda,0xa1,0x46,0xd0,0x80,0xfe,0x87,0x5e,0x3f,0x4c,0xe6,0x5f,0x44,0x63,0x2f,0xde,
+  0x0a,0x83,0x5a,0x29,0x78,0x55,0xe9,0xff,0xca,0xed,0x8d,0xe6,0x5f,0xd4,0x46,0x32,
+  0x98,0x24,0xfe,0x31,0xce,0xbf,0xc0,0xf8,0x67,0xe5,0x6a,0xa1,0xbe,0x63,0xe1,0x60,
+  0x4e,0x18,0xe4,0x44,0xfe,0xe7,0x6f,0x11,0x9e,0xa7,0xb0,0x9e,0xd2,0x38,0x35,0xd2,
+  0xf9,0xfb,0xe5,0x24,0xfe,0x59,0x51,0xb1,0xd0,0x67,0xbf,0x7d,0x50,0xe9,0x7f,0x7f,
+  0x30,0x97,0xe8,0x7f,0x6f,0x72,0x6d,0xc6,0xf6,0x14,0xef,0x43,0xcd,0xeb,0x2a,0x21,
+  0x3e,0xe4,0x29,0x76,0xfd,0xb1,0x02,0x56,0x17,0xe3,0x45,0xcd,0x2f,0x07,0x2f,0x93,
+  0x42,0x18,0xf7,0xff,0xe9,0x4a,0xe2,0x9f,0x3d,0x02,0x1f,0x52,0xfc,0x1f,0xd9,0xef,
+  0xfa,0x56,0xf6,0xab,0x37,0x25,0xff,0xe7,0x57,0xe8,0xf5,0xcf,0x27,0x1b,0xc1,0x68,
+  0x20,0xf8,0xff,0xcc,0xc4,0xb6,0xcf,0x6d,0xb9,0xc8,0xff,0xe7,0x20,0x5a,0xec,0x62,
+  0xd8,0xe3,0x2b,0xf8,0x67,0x8a,0x88,0x7f,0x28,0xcd,0x55,0xdc,0x81,0x9a,0x6f,0xac,
+  0x76,0x1b,0xf1,0x32,0x9b,0x74,0xf8,0xc7,0xde,0x1f,0xa6,0x7d,0x51,0x4c,0xfb,0x68,
+  0xeb,0x89,0x6f,0x70,0xff,0x9f,0xbf,0xea,0x27,0xf7,0x3f,0xed,0x9c,0xfd,0x0c,0xb7,
+  0x75,0x6a,0x93,0xf1,0x8f,0xc7,0xf8,0xcf,0x88,0xff,0x89,0x7e,0xbb,0x99,0xe8,0x85,
+  0x72,0x9b,0x93,0xf8,0x67,0x1a,0xe7,0x1b,0x1d,0xb7,0xd8,0x49,0x69,0x37,0x6b,0x20,
+  0x0b,0xff,0xd3,0xe6,0xb0,0x6e,0x77,0x6c,0xfb,0xb3,0x1e,0xe2,0x7f,0xc4,0xfe,0xf7,
+  0x0d,0x44,0xff,0x13,0x1e,0x5b,0xdd,0x31,0x5f,0xa1,0x32,0x42,0x1c,0xff,0x04,0x0c,
+  0xff,0x4c,0x39,0xa3,0xfc,0xd9,0x02,0xf8,0xa7,0xc7,0xb9,0x3f,0xd6,0xff,0x84,0x68,
+  0xc7,0x7f,0x7a,0xc7,0x0d,0xe5,0x0d,0x5d,0x6b,0xcc,0xf8,0xa7,0x18,0xee,0x96,0xb1,
+  0x7a,0x70,0xf7,0xf5,0x48,0xd3,0x08,0x76,0x6a,0x0a,0x5d,0xaf,0x6f,0x1f,0x45,0xa7,
+  0xfb,0x62,0xff,0x1f,0xff,0xe9,0xbe,0xd6,0xf8,0x45,0x3e,0xc2,0x3f,0x5d,0x91,0x10,
+  0x3a,0x0a,0x5c,0x96,0xff,0x83,0x33,0xfb,0xd0,0xaf,0x8b,0x91,0xff,0x0f,0xf6,0x2f,
+  0x9a,0x57,0xaa,0xfe,0x2e,0xc5,0x3f,0xdb,0x22,0x85,0x46,0x18,0x7c,0xb3,0x63,0x91,
+  0xc0,0xff,0xf4,0xc5,0xb6,0x3f,0x98,0x2f,0xba,0x47,0x90,0x3d,0x4b,0x0a,0x46,0x4f,
+  0xf0,0x7f,0x0e,0x44,0xb7,0xd5,0x26,0x31,0x8d,0x1d,0xec,0xe8,0x9f,0x29,0xf4,0xbf,
+  0xf7,0xa0,0xe7,0x72,0x91,0x69,0xcf,0xf8,0x94,0xe7,0xd0,0x47,0xa2,0x8d,0x33,0x56,
+  0x54,0xc6,0x41,0x95,0xd0,0x0f,0x1b,0xc3,0x00,0x92,0x96,0xbf,0x4e,0xc3,0x3f,0x45,
+  0xf7,0xa2,0xe2,0x7e,0x73,0x26,0xe2,0x7f,0x6a,0x40,0xfc,0xb3,0xd7,0xde,0xe4,0xab,
+  0xc7,0x6e,0xf2,0x13,0x01,0xff,0xdc,0xe4,0x79,0xea,0xf5,0x06,0xfe,0x67,0x3a,0x42,
+  0xfb,0xd6,0x36,0x9f,0x8a,0xf0,0x00,0x15,0x06,0xe3,0x27,0x70,0x20,0x4e,0x94,0x9f,
+  0xc0,0x3f,0x41,0xb8,0xff,0x9c,0xef,0x8c,0x9a,0xbc,0xc6,0x83,0x58,0xff,0x13,0x2e,
+  0x33,0x3c,0xf1,0x4f,0x85,0x27,0xce,0xdb,0x6b,0x2f,0xf9,0x49,0xfc,0x53,0xd1,0xc7,
+  0xf5,0x51,0xbf,0xb5,0x56,0x9d,0x24,0x83,0x9c,0xe2,0xf3,0x2b,0xc0,0xa3,0x31,0x24,
+  0xfc,0x83,0x50,0xf8,0x1e,0xb8,0x37,0xdc,0x0e,0xa2,0x3e,0x10,0x5d,0x80,0xc4,0x1f,
+  0x1b,0x85,0x77,0xe7,0x87,0x3b,0xb0,0x21,0x10,0x7f,0x76,0xa1,0x79,0xc8,0xf1,0xc3,
+  0x1d,0xd2,0x10,0x5c,0xcd,0xf7,0x07,0xe1,0x7f,0xb6,0x83,0x2c,0x63,0x20,0xfc,0x98,
+  0x2f,0x8c,0x83,0xab,0xf9,0xfe,0xc9,0xfe,0x7c,0xc6,0xf2,0xef,0xe2,0x59,0x7e,0x83,
+  0xe8,0xdb,0x68,0x76,0xc9,0x10,0xd8,0x1f,0xfb,0xfb,0x3f,0xe1,0xfc,0xdb,0x6e,0x90,
+  0x21,0xe7,0x39,0x81,0x5f,0x9a,0xdc,0xcf,0xca,0x95,0x59,0xae,0xaa,0xab,0xfb,0x98,
+  0x5f,0xff,0x07,0xf8,0x59,0x35,0x31,0x31,0x51,0x4a,0x09,0xfe,0x3f,0x5f,0xff,0x19,
+  0xfb,0x7b,0xfc,0x7c,0x3f,0xfc,0x7c,0x3f,0xbc,0x8a,0xfc,0x7f,0xbe,0x1f,0xa6,0xfd,
+  0x7c,0xd6,0xf6,0x9f,0xcf,0xd6,0xf5,0xa2,0x3f,0x36,0x7e,0x9b,0x50,0x02,0x6d,0x7d,
+  0xb0,0x91,0x06,0x0d,0x46,0x7d,0x38,0xda,0x5d,0xaf,0xa3,0x9d,0x3b,0xc0,0xfa,0xa0,
+  0xa1,0x2c,0x08,0xf0,0x63,0x39,0xa1,0x7e,0x17,0x15,0x52,0xab,0xa1,0xf7,0x05,0x01,
+  0xff,0x27,0xfc,0x21,0x95,0x60,0xae,0xb6,0x3e,0xc8,0x02,0xb5,0x3f,0x11,0xaa,0x0f,
+  0xe6,0x13,0x65,0xc1,0x5e,0x9d,0x3f,0x64,0x8e,0xb1,0xc7,0x59,0xea,0x83,0xb4,0x3f,
+  0x6e,0xcc,0x22,0x83,0x62,0xb7,0xf3,0xb1,0xb0,0xa6,0xfa,0xe0,0xe1,0x78,0x2c,0x08,
+  0x6e,0x8b,0xbb,0x25,0xf6,0x87,0x5c,0x01,0xd6,0x07,0x05,0x7d,0x14,0x8a,0xdc,0x90,
+  0x04,0x59,0x38,0x50,0x1f,0x6c,0xb2,0x0f,0xa1,0xd7,0xe0,0xb2,0xa9,0x60,0x94,0x24,
+  0xf0,0x63,0xae,0x5e,0x6f,0xe0,0xce,0x36,0xd5,0x07,0xbf,0xa8,0xca,0xa2,0x58,0xa9,
+  0x54,0xac,0x0f,0xee,0xd6,0xa7,0xb1,0xa0,0xf2,0x63,0xd8,0x1f,0xe9,0x55,0xb4,0x1c,
+  0x2c,0x0b,0x72,0xa3,0x24,0xad,0x3f,0x52,0x06,0x7e,0x4c,0xa8,0xfe,0x7c,0x9d,0xd3,
+  0x20,0x8b,0x53,0xfb,0xe3,0x90,0x3a,0x16,0x4d,0xe0,0xc7,0xe8,0xf5,0x42,0x7d,0x70,
+  0x73,0xc4,0x8f,0xc9,0x7c,0xce,0x83,0x8a,0x3f,0x64,0xa6,0xfe,0x38,0xce,0x8f,0x75,
+  0x55,0x0a,0xf5,0x41,0x6a,0xcb,0xec,0xe8,0xeb,0x83,0x09,0x7f,0x48,0x1a,0x54,0xc8,
+  0x9f,0xbc,0x99,0xd0,0x87,0x83,0x65,0x32,0xc1,0x58,0xc0,0xd8,0x1f,0xd7,0xa8,0x04,
+  0x62,0x7d,0xb0,0x62,0x97,0x58,0x0f,0x6d,0x02,0xd6,0x5b,0x25,0xcd,0x87,0x9d,0x6e,
+  0x28,0xcb,0x02,0xf5,0xc1,0x87,0x45,0x7d,0xd4,0x71,0x46,0x8b,0x25,0xf5,0x51,0x0b,
+  0x58,0x7d,0x10,0xd4,0x47,0x1d,0x4f,0x04,0x52,0x7d,0x30,0xe2,0x63,0xe7,0x64,0xac,
+  0x0f,0x7a,0x15,0x89,0x69,0x20,0x75,0x29,0xfc,0x18,0x9e,0xa7,0x6c,0x6d,0x4d,0xd1,
+  0x6f,0x08,0xf5,0x41,0x24,0xe9,0xa3,0xbe,0x91,0x5a,0x1f,0xec,0x89,0xfd,0xb1,0x6b,
+  0xa3,0x69,0xb0,0x19,0xea,0x83,0xb3,0x13,0x7a,0x0f,0x50,0xff,0x23,0xf0,0x63,0x15,
+  0x4c,0xdf,0xfb,0x7d,0x3c,0x0d,0x56,0x3a,0xb6,0xd8,0xaf,0x86,0x18,0x3f,0xf6,0x2f,
+  0xf5,0xbf,0xe8,0x21,0x77,0x7b,0x1b,0xfa,0x69,0x31,0xf2,0x47,0x7a,0x21,0x20,0x46,
+  0x49,0x67,0xef,0x8e,0xad,0x9f,0x3a,0x24,0x7f,0xc8,0x1d,0x7c,0x75,0x1e,0xd3,0x83,
+  0x2d,0x94,0x84,0x61,0x49,0x7f,0xc8,0x34,0x3d,0x8c,0x50,0x1f,0x9c,0x7e,0x88,0xca,
+  0xa2,0xc2,0xd5,0x45,0x65,0x17,0x32,0x16,0xe4,0x47,0xc2,0x7a,0x9f,0x15,0xf8,0x31,
+  0xe1,0x18,0xd2,0xea,0x51,0xc5,0xfa,0xa0,0xf1,0xbc,0x7b,0x52,0xad,0x0f,0x36,0xeb,
+  0xc7,0x52,0x40,0xfc,0x98,0xa8,0x07,0x96,0x82,0xe7,0xf0,0x84,0x35,0x50,0x1f,0xfe,
+  0x63,0x5a,0x0f,0x7a,0xc4,0x61,0x63,0x41,0xc2,0xb4,0x2c,0x23,0xfe,0xd8,0x49,0x7d,
+  0x54,0xc0,0x57,0x57,0x6c,0xff,0x4f,0xdc,0x16,0x17,0x7e,0x32,0x67,0x88,0x04,0x8a,
+  0x3e,0xfc,0x72,0xfd,0x93,0xe8,0x8f,0xd9,0xf9,0x35,0x5c,0x77,0xb1,0x3b,0x1a,0x0b,
+  0xf2,0x6c,0xdd,0xc5,0x58,0xf1,0x92,0xa8,0x0f,0xde,0x2d,0x3e,0x2d,0xde,0xaa,0x73,
+  0xb5,0x66,0x7d,0x54,0xc9,0x11,0xd0,0xce,0x93,0x43,0xcd,0x25,0x07,0xea,0x8f,0x1b,
+  0x65,0xfb,0xf3,0x00,0xda,0x6d,0xe3,0x7e,0x25,0xf6,0xbf,0x5f,0xa5,0x04,0xe1,0xaf,
+  0x2e,0x72,0x7d,0xb8,0x2d,0xe9,0xa3,0x9a,0x4b,0xa0,0xde,0x9e,0xeb,0xc3,0xeb,0x93,
+  0xfa,0x70,0xf0,0xef,0xe5,0x1c,0xc3,0x4b,0xc5,0x7a,0xf1,0x79,0xc8,0xe9,0xf4,0x51,
+  0x6c,0xff,0x19,0x72,0x0f,0xf1,0x7e,0x84,0x77,0xc4,0xef,0xaf,0x85,0xf1,0xcf,0x4d,
+  0xc2,0xf3,0xf0,0x64,0xe4,0x6f,0xd9,0xc1,0xef,0xdf,0x25,0xc1,0x07,0xec,0x79,0x10,
+  0xf4,0x51,0x6a,0x5a,0x00,0xfc,0x33,0xea,0x72,0x7d,0x78,0x14,0x38,0xdb,0xa7,0xa8,
+  0x7a,0xa1,0x71,0x8e,0x7f,0x66,0xd6,0xa2,0xf7,0xdc,0x95,0xa5,0xd3,0x2d,0xd3,0x5e,
+  0x70,0x7e,0x17,0xa2,0x9d,0xda,0x36,0x6e,0x8b,0xfd,0x42,0xf8,0x6e,0x87,0xf1,0xcf,
+  0x1d,0x2f,0xb2,0xc7,0xcd,0x9f,0x7e,0x02,0x5d,0x62,0xfd,0x95,0x0e,0x4f,0x4b,0x7f,
+  0xdc,0xa1,0xa9,0xd4,0x07,0x05,0x7f,0x72,0xc0,0xa8,0x81,0x14,0x52,0x05,0x7d,0xb8,
+  0x23,0xe2,0x1f,0xdd,0x7c,0xc9,0x8b,0x0b,0xe8,0xf7,0x7b,0x92,0x3e,0xea,0x07,0x90,
+  0x3e,0x6a,0x7d,0x57,0x43,0x99,0xe1,0xd5,0x2d,0x76,0x8c,0x7f,0xf2,0xc6,0xfd,0x87,
+  0xeb,0xc3,0xcb,0xd3,0xb1,0x3e,0x7c,0x0e,0x2c,0x8b,0x02,0xfd,0x21,0x05,0xbd,0xca,
+  0x68,0x16,0x7d,0xf8,0x7e,0xa2,0xff,0x89,0xce,0x3b,0xcd,0xfc,0x50,0x11,0xff,0x2c,
+  0x70,0x85,0xd3,0xb6,0x11,0x3e,0x7f,0x85,0xfa,0xe0,0x4d,0x0b,0xec,0xf4,0xeb,0xb9,
+  0x3e,0xbc,0x69,0xba,0x88,0x7f,0x9a,0x8a,0x1a,0x7d,0x14,0xdb,0x7f,0xba,0xae,0xed,
+  0x74,0xe9,0x7c,0x58,0x7b,0xcc,0x5b,0x0a,0xcf,0x27,0xbd,0xc0,0xf6,0x9f,0x63,0x33,
+  0xf8,0x18,0x14,0x5c,0x38,0x5b,0x47,0x96,0xb9,0x3c,0x56,0x88,0x91,0x5f,0x7d,0xc0,
+  0xf6,0x9f,0x15,0x04,0xff,0xd4,0xe0,0x7a,0xd9,0x2b,0x68,0xe9,0xc6,0x5a,0x50,0x4f,
+  0xc5,0xf5,0x51,0x4e,0x31,0xf6,0x87,0x8c,0xf1,0x4f,0x23,0x72,0x82,0x06,0x05,0x11,
+  0x35,0x9c,0xe5,0xf8,0xc7,0x16,0xf5,0x51,0xbe,0xe7,0xff,0x50,0x5a,0xef,0x7d,0xc9,
+  0xfa,0xe0,0x1e,0x7b,0xbf,0x50,0x16,0xcc,0x3d,0xac,0xf1,0x1b,0x17,0xf4,0x51,0xfb,
+  0x39,0x7a,0xf9,0x30,0xd7,0xe0,0xff,0x02,0xb8,0xff,0x1c,0x9f,0x0f,0x3b,0x20,0xd6,
+  0x8b,0xdf,0xb5,0x71,0xf5,0x50,0xbd,0x7e,0xcd,0x47,0xcc,0x1f,0xdb,0x49,0xfa,0x03,
+  0xa4,0xcc,0x87,0x75,0xb8,0x3e,0x8a,0xb9,0x61,0x53,0xd8,0xd3,0x08,0xe0,0x1f,0xc7,
+  0x96,0xaa,0x81,0x8b,0x75,0xf8,0x87,0xfe,0xff,0x22,0x57,0xf8,0x6b,0xbd,0x4e,0x9a,
+  0xaf,0x2a,0xea,0xc3,0x99,0x3f,0xb6,0xb3,0xe7,0x76,0x09,0xed,0xbc,0x55,0x47,0xeb,
+  0x83,0x53,0xa5,0xf9,0x68,0xf4,0xeb,0x05,0x7d,0x94,0xa1,0xff,0x5d,0xd0,0x47,0xed,
+  0x7a,0x62,0x23,0xc7,0x3f,0x61,0x50,0xe0,0xc7,0xd6,0xb4,0x2b,0x0e,0x3d,0xbf,0xb8,
+  0x3e,0xca,0xd9,0x8d,0x37,0x0d,0x7a,0xb7,0x4b,0x4a,0x55,0x5f,0xe2,0xfd,0x71,0x83,
+  0xb1,0x50,0x53,0xd4,0x47,0x21,0xf4,0x33,0xfb,0x3a,0x71,0x75,0x60,0x63,0x6f,0x3f,
+  0xd7,0x47,0xd9,0xe2,0xfb,0x97,0xad,0xd1,0x87,0x8b,0xfa,0xa8,0x70,0x51,0x71,0x7d,
+  0x70,0xc4,0x7e,0x3c,0xdc,0x5d,0xc1,0xf9,0x0e,0xaf,0xf2,0xe7,0xad,0x5e,0xc9,0xcf,
+  0xb4,0x11,0x57,0x39,0xef,0xd8,0xfe,0x33,0xcf,0x3d,0xe1,0xb0,0xd3,0x0d,0xeb,0xa3,
+  0xaa,0xa1,0xf3,0x6e,0x94,0xdd,0xcf,0xde,0x4c,0xfe,0x90,0xe7,0xd8,0xfe,0x13,0x54,
+  0x28,0xd7,0x63,0x7d,0x54,0x4e,0x5b,0x1f,0x74,0x0b,0xbe,0x38,0x16,0xa4,0x14,0x0d,
+  0xa6,0x21,0xf3,0xbb,0x99,0x42,0x58,0xc0,0x3f,0x7b,0x88,0x3f,0xc0,0xe1,0xfc,0xdb,
+  0xf1,0xfb,0xf8,0x91,0x58,0xff,0xd3,0x4f,0x3e,0x89,0xf1,0x1e,0xc7,0x3f,0x33,0x70,
+  0x19,0x31,0x5e,0x5d,0x31,0xb6,0x05,0xc8,0xcb,0xfe,0xd8,0x49,0x7d,0x14,0x01,0xc9,
+  0x2f,0xcb,0xb6,0xea,0x5a,0xfc,0xb3,0x87,0x80,0x9c,0xfb,0xad,0x7f,0x53,0x60,0x0f,
+  0xc0,0xff,0x84,0xf8,0x27,0x5e,0x54,0x71,0xa7,0x81,0xdf,0xe0,0xfc,0x4f,0xd9,0x3e,
+  0x14,0x83,0x84,0xa2,0x65,0x10,0x8a,0x73,0xfe,0x67,0xf5,0x0c,0xa2,0x56,0x7a,0x00,
+  0xb0,0x65,0xe6,0xfd,0x71,0xaa,0x3f,0xf6,0x8b,0x39,0x83,0x3f,0x12,0xc7,0x3f,0xfd,
+  0x94,0xff,0x79,0xb4,0xda,0xf0,0x87,0x09,0xf8,0x63,0xb7,0x00,0xb6,0x5a,0x40,0x7f,
+  0x5c,0x89,0xed,0x3f,0x55,0x99,0xf8,0x9f,0x51,0xf7,0x76,0x85,0xfd,0x30,0xf7,0xc7,
+  0xdd,0x12,0x93,0x3c,0x27,0xf8,0x58,0x58,0xa3,0x3e,0x7c,0xc6,0x09,0xff,0x49,0x2e,
+  0x8b,0x12,0xfb,0x35,0x34,0xfc,0x0f,0x71,0xa3,0xea,0x33,0xe5,0x5f,0xe0,0x7f,0x66,
+  0x12,0xfc,0xb3,0x11,0xb0,0xc5,0xd6,0xe8,0xc3,0x0f,0x04,0x5c,0x06,0x9f,0xa6,0x0f,
+  0xa7,0xfa,0xa8,0xea,0x13,0x3f,0x34,0x34,0xfe,0x88,0xfc,0x4f,0xac,0x86,0xaa,0x7b,
+  0x2b,0xbf,0x85,0x0b,0xc5,0x71,0x30,0x17,0xd6,0x87,0xe7,0x8a,0x94,0xf6,0x31,0x08,
+  0x77,0x25,0xfc,0xe3,0xe2,0xb6,0xb8,0x0d,0xf7,0xe5,0x17,0x24,0x8c,0xa0,0x35,0xfa,
+  0x70,0xc2,0xff,0xec,0xc9,0x67,0xf2,0xc7,0x5e,0x51,0x21,0xf0,0x3f,0x19,0xfc,0x91,
+  0x38,0xfe,0x99,0x92,0xc9,0x1f,0xbb,0xab,0x86,0xcc,0x07,0x41,0xd5,0x9c,0x08,0xaa,
+  0xd4,0xfb,0x63,0x33,0x7d,0xd4,0x8b,0xdd,0x26,0x7d,0xb8,0xca,0xff,0x40,0xb6,0x90,
+  0x10,0xff,0x33,0x93,0x80,0x9c,0x2a,0x4b,0x1d,0x0b,0x02,0xf1,0x3f,0x68,0x17,0xd1,
+  0x83,0xdd,0x6f,0x3b,0xda,0xf5,0xca,0xf8,0x27,0x4a,0x5a,0xbd,0xc9,0x6f,0x5c,0xf2,
+  0xc7,0x8e,0x6d,0x9d,0xee,0x07,0xc6,0x82,0x00,0xfd,0x71,0x58,0x1f,0x75,0x5c,0x77,
+  0x19,0xa0,0x0f,0x77,0xa8,0x3e,0x7c,0x57,0xde,0x23,0x42,0xb5,0x8c,0xfd,0x71,0x56,
+  0x1c,0xf4,0xa6,0xf4,0xc7,0x71,0xfc,0x63,0xd8,0x7f,0xb8,0x3f,0x76,0xe0,0xde,0x96,
+  0xe1,0xef,0x97,0xfb,0x63,0xf7,0xf4,0xdc,0x9e,0x8b,0x40,0xce,0xd7,0xab,0x55,0x5b,
+  0x48,0x68,0x3e,0x2c,0xc5,0x3f,0x8f,0x19,0xf1,0x0f,0xef,0x8f,0xe3,0xfa,0xf0,0xf6,
+  0xb8,0xbf,0x29,0xd6,0x47,0xad,0x3a,0x47,0x83,0xb2,0x3c,0x1f,0x96,0xee,0x3f,0x2e,
+  0xbd,0xff,0x3b,0xe3,0xdb,0x2e,0xd3,0xa0,0x24,0xf7,0xc7,0x05,0xe4,0xfa,0xaf,0x55,
+  0xc9,0xeb,0x1d,0xd0,0xf4,0xc7,0x71,0xfc,0x23,0xe4,0xb3,0x35,0x91,0x4f,0xb1,0x3f,
+  0x8e,0x2d,0x8a,0xef,0x9f,0x05,0xce,0x08,0xa1,0x68,0x02,0x9a,0xe0,0x8f,0x9d,0x23,
+  0xf9,0xe9,0x4b,0xa6,0xe5,0xb4,0xc4,0xff,0xd0,0xfb,0x67,0xf8,0x67,0x08,0x18,0x0b,
+  0x02,0xea,0xa3,0x08,0x9e,0x69,0x61,0x63,0xd9,0x1b,0xd5,0xf3,0x0b,0xf4,0x47,0x32,
+  0x9c,0x77,0xa2,0x3e,0x8a,0xa4,0xe5,0x01,0x9a,0x9f,0xa5,0xb1,0x2d,0xb6,0x4e,0x1f,
+  0xfe,0x0f,0x5b,0xfd,0x68,0x51,0x7f,0x49,0xf3,0x73,0x8c,0xbc,0x68,0x8b,0x46,0x40,
+  0x25,0x11,0xff,0xf4,0xc9,0xab,0x7b,0x3f,0x4f,0x26,0xa6,0xbd,0x0b,0xe3,0x1f,0x15,
+  0xed,0x08,0x41,0xec,0x0f,0x79,0x87,0xae,0x3f,0xae,0x29,0x15,0xff,0x88,0xfe,0x00,
+  0xd3,0xc9,0xf4,0x5b,0xfa,0x49,0x43,0xb4,0xf0,0x78,0xbd,0xec,0x7e,0xea,0xf5,0xb0,
+  0xa7,0x01,0xe0,0x7f,0x10,0x30,0x1f,0x04,0xa8,0x7f,0x65,0xf0,0x87,0x9c,0x6b,0xf2,
+  0x47,0x2a,0x11,0xfd,0xf9,0x52,0xf9,0xfb,0xdd,0x3b,0x55,0x7d,0xb8,0xf0,0x18,0x9c,
+  0x8f,0xa7,0x99,0xa4,0xfb,0x23,0x91,0xb4,0xec,0x8b,0xdd,0xe3,0x59,0xc6,0x76,0xab,
+  0xf8,0x47,0x9a,0x8f,0x76,0x40,0x68,0x9c,0xe7,0xc1,0x2c,0x09,0xff,0xac,0x2d,0x38,
+  0x0c,0xed,0x9c,0x47,0x2d,0x49,0xfc,0x73,0x18,0xf6,0x47,0xa2,0x69,0x79,0xbc,0x44,
+  0xda,0xe2,0x88,0xe2,0x4e,0xf5,0x07,0x98,0x71,0x41,0x1c,0x6b,0xb8,0xbc,0xb4,0x41,
+  0x68,0x8b,0x83,0xfc,0x01,0xae,0x39,0xc1,0xdb,0x4c,0x7e,0xaa,0x31,0x0a,0x90,0xfc,
+  0x01,0x9e,0x10,0x65,0xf0,0xd0,0x7a,0xb1,0x3f,0x00,0xe3,0x7f,0xd6,0xda,0x82,0x1a,
+  0xfc,0xa1,0x44,0x3e,0x35,0xfe,0x00,0x82,0x1b,0x24,0x5c,0x08,0xfb,0x3d,0xcd,0x87,
+  0x25,0x34,0x48,0x0a,0xff,0x23,0xc1,0x18,0x81,0xcf,0xe9,0xcd,0xe2,0x0f,0xf9,0x45,
+  0xe9,0x98,0x8e,0x8f,0xf2,0x59,0x06,0x7f,0x48,0x2f,0x0d,0xff,0x48,0xf3,0x61,0x47,
+  0xd1,0x72,0x71,0x99,0x6b,0x00,0xfe,0x27,0xae,0x7f,0xd1,0xea,0x5e,0x93,0x4c,0x6b,
+  0x98,0xf0,0x8f,0x09,0x0f,0xdc,0xf1,0x86,0xa6,0xfe,0xe5,0x01,0xf8,0x27,0x67,0x98,
+  0x0f,0xeb,0x24,0xf0,0x8f,0x7d,0xf5,0xfe,0x90,0xc9,0xf9,0x68,0x3f,0x92,0xea,0x59,
+  0x44,0xef,0xcd,0xf9,0x1f,0x79,0x3e,0x9a,0xd6,0x1f,0x00,0x9e,0x8f,0x96,0xc5,0x1f,
+  0xc0,0x6e,0xd2,0xda,0x02,0x40,0xfc,0xcf,0x64,0xfd,0x01,0x3c,0xc8,0x1f,0x40,0xe9,
+  0x6f,0xe5,0xfc,0x8f,0x30,0x1f,0x2d,0x44,0x3b,0x43,0xe9,0xfe,0x00,0xd7,0x1e,0x12,
+  0xd8,0x8c,0xce,0x54,0xfc,0xe3,0x57,0x30,0xb5,0x06,0x9e,0x06,0xdb,0x9a,0xf6,0xfe,
+  0x4e,0xfc,0x91,0xca,0xc4,0x0d,0x29,0xdc,0x7f,0xb6,0x73,0x5b,0x92,0xc8,0x1f,0xa9,
+  0x0c,0xf9,0x03,0x9c,0x24,0xab,0x9b,0xa7,0xce,0x87,0x3d,0x29,0xf1,0x3f,0x72,0xfd,
+  0xcb,0xd6,0xec,0x3f,0xe2,0x7c,0x34,0xe1,0x7c,0x99,0x40,0x47,0xe1,0xf5,0x9e,0x85,
+  0xfc,0xb1,0x0d,0xc1,0xeb,0x3a,0x7f,0x00,0x4d,0xc0,0xf9,0x1f,0xc9,0x1f,0xe0,0x7c,
+  0x06,0x7f,0xc8,0x9c,0x70,0xbd,0xb6,0x9f,0x4b,0xe9,0x8f,0x1b,0x20,0xe7,0x1d,0xc6,
+  0x3f,0x3b,0xc5,0xfc,0xf8,0x49,0xfc,0xe3,0x44,0x6a,0x13,0xac,0x0f,0x1f,0x09,0xde,
+  0xa4,0xfa,0x70,0xba,0xde,0xdd,0x97,0x56,0x47,0xbf,0x2a,0x27,0xfd,0x91,0xb0,0x09,
+  0xf6,0xe5,0xb8,0x1f,0x50,0x68,0xeb,0x7e,0x1b,0x91,0xd1,0xb1,0x06,0xfc,0x53,0x33,
+  0x96,0x9b,0xa4,0x3f,0xc0,0xa4,0xe6,0x83,0x68,0xf8,0x1f,0x93,0x3f,0xf6,0x26,0x1c,
+  0xd4,0x4a,0x83,0x7a,0x27,0x8f,0x7f,0xe8,0xf3,0xc9,0xf1,0xcf,0x34,0xc3,0xf3,0x00,
+  0xcc,0x87,0x3d,0xa2,0x7e,0x2d,0x3f,0xe8,0x35,0xf8,0xc7,0xc0,0xff,0xd0,0x1f,0xd8,
+  0x1f,0x3b,0x83,0xfe,0xc7,0xd8,0x2f,0x2f,0xe9,0x7f,0x6c,0x99,0xed,0xb9,0x1e,0x07,
+  0x81,0x96,0xff,0xb9,0x56,0x87,0x0f,0x61,0xfe,0xe7,0xa0,0xd6,0x9f,0x4a,0x83,0x7f,
+  0xb8,0x3f,0x76,0x26,0x7f,0xc8,0x93,0x99,0xfc,0x01,0x24,0x7f,0x24,0x75,0xec,0x8e,
+  0x09,0xff,0xfc,0xe4,0x20,0x47,0x3b,0x98,0xf6,0xa9,0xfe,0x44,0xf1,0x8f,0x26,0xf8,
+  0xe4,0xfd,0xb1,0xe9,0x4f,0x46,0x7f,0x6c,0x76,0xfd,0x31,0x11,0xff,0x68,0x03,0xed,
+  0x7c,0xd8,0x38,0x70,0x92,0x9f,0x70,0xfc,0xb3,0x87,0xf1,0x3f,0x20,0x7f,0xf2,0x8c,
+  0x41,0xff,0x13,0xf3,0x3f,0x75,0x22,0xfe,0xb1,0x7a,0x0c,0xf3,0x41,0xa0,0x85,0xef,
+  0x30,0xe0,0x9f,0x38,0xb1,0x55,0x52,0x3e,0xef,0x4d,0xe2,0x9f,0x87,0xeb,0xd9,0xdd,
+  0xc6,0xf7,0x5f,0x2d,0xdc,0x7f,0x3f,0xbd,0xff,0x49,0xfb,0x23,0x31,0xfc,0xb3,0x88,
+  0xe3,0x1f,0xc3,0x7c,0x3a,0x61,0x3e,0x2c,0xe5,0x7f,0xbc,0x88,0xcf,0x94,0x0b,0x61,
+  0x63,0x06,0xfc,0xe3,0x02,0xfc,0xcf,0x00,0xc3,0x3f,0x6c,0x3e,0x2c,0xf3,0x47,0xda,
+  0x68,0xb1,0xb1,0x1a,0x2c,0x78,0x99,0x06,0x03,0x37,0xd2,0xef,0x67,0xfe,0x48,0x5f,
+  0x63,0x63,0x41,0xa6,0x31,0xd8,0xf3,0x2a,0xd3,0xff,0xb0,0xf9,0xd4,0xcc,0x1f,0xd2,
+  0x05,0xb6,0x91,0x61,0x86,0x7f,0xf8,0xfb,0x11,0x3d,0xbf,0xd8,0x58,0xab,0xe3,0xfc,
+  0xd8,0xfa,0x88,0xe9,0x7f,0x14,0x7f,0xc8,0xf0,0xfe,0xc9,0x6e,0xb3,0x22,0x0c,0x1e,
+  0x49,0xdc,0x3f,0xe0,0x8f,0xc4,0xae,0x17,0xf0,0x0f,0xbb,0x9e,0xeb,0x6d,0xa8,0x3f,
+  0x52,0xde,0x25,0x69,0x5c,0x13,0x0f,0xaa,0x96,0xf3,0xc9,0xf1,0xcf,0x16,0x8a,0x7f,
+  0x28,0x9f,0xf3,0x34,0xb4,0xde,0x67,0xb3,0xe1,0x1f,0x76,0x3d,0xd7,0x07,0x96,0x28,
+  0xfe,0x19,0x82,0x8e,0x39,0x83,0x3f,0x12,0x34,0x96,0x7d,0x98,0xeb,0x7f,0x14,0xfe,
+  0x07,0x1a,0x83,0x35,0x0c,0xe0,0x9f,0xa4,0xde,0x03,0x1b,0x65,0x2b,0xf9,0x11,0xfa,
+  0xe3,0x6a,0xb6,0x26,0xf8,0xae,0x47,0x70,0xb0,0x51,0x5e,0xaf,0xe2,0x0f,0x29,0x2c,
+  0xf3,0x22,0xb0,0x5e,0x8e,0x7f,0x4e,0x55,0x5c,0xb1,0x27,0x76,0x24,0x68,0x9f,0x8d,
+  0x0c,0xff,0xbc,0x13,0x57,0x54,0x85,0xfa,0xd7,0x4c,0x15,0xed,0x0c,0x06,0xf1,0xc4,
+  0x90,0x9d,0x23,0x91,0x75,0x40,0xd5,0x31,0x6b,0x54,0xad,0x7f,0xa9,0xc7,0xd0,0x52,
+  0x6b,0xb0,0xb8,0x2f,0xcc,0x4f,0xa5,0x41,0xff,0x43,0x82,0x87,0xc2,0x20,0xc4,0x3f,
+  0xb1,0xf1,0x54,0x95,0x88,0x7f,0x56,0x9b,0xf1,0x0f,0x2e,0xcd,0x14,0x0e,0xe7,0xdf,
+  0xe7,0xfa,0x1f,0x95,0xff,0x81,0xfc,0xa3,0x14,0xfe,0xa7,0x46,0xfa,0xda,0xd7,0x48,
+  0xe1,0x95,0x52,0x1f,0xdf,0x61,0xf8,0xa7,0x14,0x3d,0x0f,0xb5,0xba,0x7e,0xc9,0xde,
+  0x24,0xff,0x33,0x60,0x43,0xf8,0x47,0xe8,0x30,0x8d,0x2a,0xf2,0x5d,0x50,0xfd,0x4b,
+  0x80,0x01,0x49,0xc7,0x00,0x41,0xff,0xe3,0xdc,0xac,0xa0,0x9d,0x41,0x3c,0x1f,0xa4,
+  0x14,0x0d,0x0a,0x79,0x2a,0x0e,0xbe,0x2a,0xf9,0x03,0x18,0xf1,0x4f,0xcc,0xff,0xfc,
+  0x33,0xcd,0x0f,0xd6,0xff,0xbc,0x17,0xc8,0xb4,0xd8,0x85,0xb8,0x22,0x86,0x27,0x86,
+  0xbc,0xa6,0xe0,0x1f,0x57,0xf5,0x87,0x1c,0x8f,0x19,0xa1,0x51,0xce,0xa8,0x27,0xf5,
+  0x3f,0xf3,0x12,0xeb,0x3d,0x40,0x2b,0x80,0x64,0x3e,0x1a,0xdf,0x7f,0xb6,0x60,0xfd,
+  0xb3,0x95,0x7c,0xed,0xea,0x4e,0x30,0xd2,0x82,0xfe,0xa7,0x1e,0x83,0x9c,0xa3,0x09,
+  0xda,0xe7,0x2d,0x3a,0x31,0x04,0xf0,0x07,0xc8,0xf2,0x3e,0xae,0xf1,0x07,0x48,0x04,
+  0x16,0x0b,0x54,0xfc,0x53,0x6b,0xc2,0x33,0x8d,0x60,0xfd,0x2b,0xd3,0x7c,0x10,0x5a,
+  0xff,0xaa,0x32,0xe3,0x1f,0xa9,0xfe,0x95,0x01,0xff,0x28,0xf5,0x2f,0x49,0xc6,0x73,
+  0x38,0xae,0x10,0x75,0x33,0xa3,0xc8,0x0f,0x24,0xfe,0xe7,0x72,0x22,0x3f,0x9b,0x37,
+  0x46,0x1d,0xf7,0x0f,0xe4,0x59,0xea,0xc4,0xfa,0x57,0x51,0x2d,0x7b,0x05,0x11,0xec,
+  0xd9,0x69,0x79,0x45,0xf2,0x89,0x4e,0xff,0x43,0x06,0xa5,0x05,0x44,0xf6,0xb3,0x8b,
+  0x0e,0x0a,0xb9,0x5f,0xa9,0x7f,0xe5,0x55,0xd8,0xe3,0x12,0x44,0x94,0xef,0xeb,0x30,
+  0xfb,0x43,0x6e,0xa6,0x8e,0x07,0xec,0xfe,0x0f,0x4a,0xf5,0xaf,0x74,0xfc,0x03,0xd4,
+  0xbf,0x12,0x69,0x6f,0x93,0x14,0xe9,0x62,0xfd,0xeb,0x60,0x92,0xf6,0x89,0xe6,0xc3,
+  0xb6,0xc5,0x9f,0x60,0xc7,0x80,0x3a,0x4d,0xfd,0x6b,0x30,0x9a,0x4e,0xbe,0x1e,0x1b,
+  0xfb,0x3f,0x42,0x1b,0xdb,0x7f,0x9c,0xe4,0x7f,0x58,0xfd,0x6b,0x9b,0x4c,0x83,0xe0,
+  0xc6,0xf9,0x29,0xb8,0xe3,0x3e,0xe1,0x0f,0xd9,0xd3,0x43,0xf5,0x3f,0x16,0xa7,0x7d,
+  0xfc,0x5f,0x05,0x5f,0x2e,0xd7,0x6d,0xcf,0x5f,0xf1,0x7e,0x13,0x5c,0xab,0xe8,0x7f,
+  0xea,0x93,0xdb,0x38,0xf1,0x87,0x7c,0x34,0x3f,0x52,0xc2,0xc1,0x2d,0x52,0xfd,0x6b,
+  0xd7,0x13,0xae,0x5a,0xb6,0x88,0xe6,0x5b,0x8d,0x77,0x5f,0x41,0xa7,0x77,0x44,0xa3,
+  0x63,0x05,0x7f,0xc8,0x99,0xcc,0x1f,0x52,0xb0,0xa5,0x65,0x8c,0xf4,0x3d,0xd9,0xfc,
+  0x21,0x0f,0x24,0xae,0x2f,0x79,0x34,0xff,0x9e,0x0d,0x9d,0x77,0xdd,0x72,0xd0,0x28,
+  0xd7,0xbf,0x1e,0x4f,0xac,0x77,0x9c,0x4e,0x8c,0x65,0x46,0x88,0x82,0x1e,0x3b,0x77,
+  0x08,0xdd,0x09,0x9f,0x77,0xa3,0xf9,0x11,0x4b,0xc1,0x3f,0xf3,0x0c,0xfa,0xe7,0x79,
+  0x80,0x3f,0xa4,0x59,0xff,0x93,0x63,0x78,0x06,0xa8,0x7f,0x41,0xef,0xfb,0xbf,0x04,
+  0xeb,0x5f,0x2e,0xfc,0x5a,0xba,0x09,0xaa,0x7f,0x61,0xfc,0xe3,0xcb,0xeb,0x3d,0x43,
+  0xd7,0x7b,0x06,0x9d,0xcf,0xc5,0xfe,0x87,0x6c,0xff,0xd9,0x3b,0x23,0x95,0xef,0x3a,
+  0x9d,0xa9,0xfe,0xe5,0xd5,0xae,0xcd,0x7f,0x80,0x4e,0xa3,0xd6,0x4c,0xfc,0x0f,0x5a,
+  0x5c,0x76,0xfa,0x76,0xe2,0x8d,0xa2,0xb1,0xa4,0xf2,0x3f,0xb9,0x58,0xe6,0x2d,0x09,
+  0xed,0x50,0x95,0x17,0xa6,0xa5,0x1b,0x1d,0x4c,0xe5,0x7f,0x48,0xe0,0x84,0x69,0xb4,
+  0xee,0x45,0x8b,0x64,0xfe,0xc7,0x07,0x9e,0x9f,0x28,0xc0,0x0e,0x36,0x83,0xe8,0x39,
+  0xef,0x0b,0xf8,0x93,0x4c,0xf3,0xd1,0x42,0x84,0xec,0x5d,0x2e,0x5e,0xa7,0xab,0x7f,
+  0x4d,0x95,0xbe,0x7f,0x29,0xaa,0x7b,0x38,0x3c,0x1f,0x2f,0xb9,0x4b,0x15,0xfe,0x07,
+  0x9c,0x2f,0xb3,0x0c,0x07,0x7f,0x8a,0x8e,0x0f,0x2d,0x87,0xea,0x5f,0xea,0xf3,0xe0,
+  0xa1,0x6a,0xdb,0xaa,0x40,0xff,0xe1,0x37,0x65,0xe3,0x7f,0x16,0xbe,0x5e,0xfd,0x72,
+  0xd5,0x1f,0xa1,0xc7,0x00,0xfe,0x87,0xc0,0x1e,0x6b,0x90,0x07,0x97,0x50,0x4b,0xae,
+  0xce,0xcb,0xa3,0xdc,0x25,0xb4,0x22,0x9d,0xff,0x61,0xfd,0x5f,0x17,0xd1,0x84,0x7b,
+  0x9d,0x66,0x3e,0x9a,0xd0,0x1f,0x87,0x3f,0x59,0x89,0xf3,0xdf,0x8c,0x47,0xcf,0x97,
+  0x0b,0x2b,0xaa,0x17,0x65,0xe0,0x7f,0x1c,0xac,0x28,0x38,0x8a,0xf6,0x61,0x85,0xe1,
+  0x52,0x68,0x3e,0x9a,0xb4,0xde,0x25,0x5e,0xd5,0xb0,0xf5,0x05,0x0f,0x57,0xc4,0x9c,
+  0x2e,0xab,0x25,0xe1,0x8f,0x2d,0xe5,0x33,0x1a,0x3b,0xb8,0x15,0x3b,0xd2,0x57,0x21,
+  0x6c,0x9d,0xed,0xb4,0x58,0x0d,0xd0,0x7c,0xb4,0x04,0xed,0x53,0xeb,0x85,0xff,0xbf,
+  0x57,0xd0,0x72,0x3c,0x3a,0xa4,0x0d,0xe6,0x7f,0xba,0xe4,0x83,0xa9,0x7a,0x14,0x8d,
+  0xfa,0x6d,0x99,0xf8,0x1f,0x3f,0x52,0xfc,0x2e,0x40,0x1f,0xee,0x6d,0xcc,0xc4,0xff,
+  0x04,0xcd,0x7e,0x3c,0xb1,0xa2,0xb3,0x31,0x1b,0xff,0xb3,0xc8,0xaf,0x1c,0xb2,0x96,
+  0x55,0x44,0x13,0x4e,0xe1,0xfa,0x57,0x87,0x54,0x06,0x5a,0xe2,0x3b,0x43,0xd6,0x74,
+  0x74,0xa4,0x69,0x8b,0xa1,0xfe,0x25,0x9d,0xbf,0x35,0x41,0xbe,0xc5,0x1e,0xf3,0xda,
+  0xf4,0xfe,0xd8,0x42,0x80,0x0b,0x61,0x0d,0xbd,0x23,0xc5,0x89,0xa6,0xc7,0xd6,0xa5,
+  0xd5,0xbf,0xa6,0x2e,0x88,0x11,0xd1,0x4b,0xf9,0x97,0xfc,0xcb,0xa8,0xf5,0x46,0xec,
+  0x8f,0xa4,0x9b,0x0f,0x8b,0x83,0x7c,0x67,0x5c,0x08,0xdb,0x89,0x3f,0x71,0x1a,0xb5,
+  0xfc,0x0f,0x09,0xfa,0x70,0x23,0x98,0xd3,0xec,0xf7,0x36,0x58,0xfd,0xc1,0x11,0xd7,
+  0x4b,0xaf,0x7f,0x6d,0x16,0x11,0x51,0x63,0xaa,0x3f,0xb6,0xc5,0x10,0x0e,0x76,0xfc,
+  0x3e,0x9a,0x99,0xff,0x79,0x10,0x07,0x4e,0x7b,0x47,0x5d,0x8a,0x3f,0xb6,0x55,0x8e,
+  0x15,0xe9,0x3d,0x79,0x0f,0x95,0x36,0x2e,0x45,0xcd,0x1a,0xfd,0x0f,0xc5,0x3f,0x53,
+  0x48,0x30,0x6c,0xb5,0xa1,0x7f,0x0c,0x7e,0x55,0x74,0xca,0x46,0x7f,0xec,0xc3,0x0d,
+  0x83,0x05,0x1c,0xcc,0xfa,0x92,0x55,0xeb,0x77,0x97,0xbc,0x6d,0x95,0x9e,0xec,0x8f,
+  0xed,0x68,0x68,0xdb,0xb1,0xaa,0x36,0xf4,0x13,0xb4,0x70,0x53,0x65,0xa7,0xc6,0x1f,
+  0x5b,0x01,0x42,0xd8,0xbf,0xb1,0xb5,0xb3,0x66,0x0b,0x30,0x1f,0x16,0x38,0xdf,0x5b,
+  0xf2,0xc3,0x16,0x56,0xd0,0xd5,0x16,0x13,0xf3,0x61,0x27,0x82,0xb9,0xd2,0xf9,0x15,
+  0x0b,0xa1,0xeb,0x86,0xf3,0xed,0x21,0xfe,0x69,0x2d,0x17,0x86,0xf3,0x48,0xe5,0x7f,
+  0xd4,0xfb,0x1f,0xb5,0x56,0xf8,0x77,0xa3,0x3f,0x2b,0x39,0x9d,0xd6,0x22,0x09,0xff,
+  0x1c,0x80,0xaf,0xef,0xb4,0x6e,0x43,0xd8,0x61,0x29,0xbc,0x1e,0x81,0xfe,0xd8,0x34,
+  0xc0,0x78,0xb2,0x79,0x2c,0x0c,0xd6,0xa1,0x1d,0x41,0x53,0xc9,0xf1,0x2c,0x47,0xf2,
+  0xc7,0x96,0xe6,0xdd,0x57,0x93,0xf9,0x17,0xe5,0x10,0xff,0xff,0xcd,0xce,0x81,0x9e,
+  0x46,0xbc,0xff,0x2c,0x4a,0xe7,0x7f,0xfa,0x31,0xde,0x0e,0xde,0xf5,0xdb,0xfb,0xe6,
+  0x16,0xf3,0x5a,0x7f,0x6c,0x12,0xfc,0x17,0x16,0x42,0x0f,0x75,0x2f,0x0b,0xf1,0xd5,
+  0xb7,0x0f,0x16,0xca,0xf3,0xb5,0xfe,0xd8,0x24,0xb8,0x17,0x07,0x7d,0xd6,0xc2,0xe0,
+  0xde,0xf2,0xf2,0x3e,0xa7,0x98,0x3a,0x1f,0xed,0x21,0x6f,0x71,0x69,0x56,0x93,0x55,
+  0x08,0x7a,0x77,0xec,0x1f,0xc2,0xd7,0x9b,0xf8,0x1f,0x6b,0x84,0xbf,0x9f,0xee,0x08,
+  0xf7,0xe7,0x26,0x4f,0x9d,0x0f,0x22,0xae,0x37,0xbc,0xfe,0x15,0x1c,0x14,0xf3,0xd8,
+  0x3f,0xf3,0xb1,0x52,0xa1,0x68,0xe4,0x7f,0x46,0xa7,0x8e,0x87,0xfb,0xc9,0xaa,0xd2,
+  0x54,0xfc,0xc9,0x65,0x74,0x57,0xa9,0xae,0xd3,0x5c,0xff,0x9a,0xac,0x3f,0xf6,0xe4,
+  0xea,0x5f,0xa2,0x4d,0xf1,0x6e,0xfa,0x7e,0x91,0x45,0xff,0x33,0x8b,0x37,0x52,0x21,
+  0x65,0x3e,0x1a,0xcf,0x8f,0x40,0xd4,0xac,0xe1,0xfa,0xe7,0xdf,0xcf,0x7c,0xd8,0xa4,
+  0x2d,0x79,0x5a,0xfd,0xeb,0xb5,0x74,0xfd,0xb3,0x84,0x7f,0x92,0x36,0x86,0xda,0xfa,
+  0xd7,0x37,0x30,0x0c,0xb8,0x42,0xd9,0x8f,0x94,0xfa,0x17,0x1f,0x0b,0xfb,0x54,0x06,
+  0xfd,0xf3,0xb5,0xd8,0x1f,0x52,0x86,0x3d,0x9f,0x66,0xfd,0x4b,0x87,0x7f,0x0c,0xf5,
+  0xaf,0x0c,0xf5,0x44,0x70,0x3e,0xac,0xa1,0xff,0xeb,0xb3,0x50,0xff,0x5a,0xff,0xe9,
+  0xce,0x87,0x05,0x96,0x39,0x3f,0x65,0x3e,0xc8,0xa4,0xf4,0xcf,0xf8,0xb7,0x49,0x22,
+  0x28,0x5b,0xff,0xbb,0x1a,0x20,0x59,0xff,0x43,0xfd,0x21,0xdd,0xfb,0xc4,0x65,0x56,
+  0x4a,0xeb,0x9d,0x94,0xfe,0x27,0xc1,0xff,0xbc,0x22,0xf4,0xbb,0xc1,0xf7,0xff,0x69,
+  0xcc,0x07,0xc9,0x3e,0x1f,0x76,0x32,0xfa,0x1f,0x70,0x3e,0x08,0xa0,0x7f,0xa6,0xdf,
+  0xaf,0xe0,0x9f,0xa9,0x4a,0xa0,0x9d,0x8f,0x96,0x0c,0xe2,0xc6,0xf0,0x93,0x75,0xca,
+  0x7c,0x90,0xbe,0xf8,0xb4,0xf2,0xff,0x37,0xd2,0xff,0xcc,0x27,0xfe,0x90,0x63,0x77,
+  0xe0,0x89,0x57,0xed,0xea,0x7c,0x10,0xd2,0xff,0x45,0xf4,0x3f,0xdb,0xa8,0xfe,0x99,
+  0x04,0xc3,0x2a,0xff,0xe3,0xb1,0xd5,0xf1,0xeb,0x23,0xfd,0xb3,0x43,0x02,0x78,0x3e,
+  0x08,0x7e,0x8d,0x85,0xf3,0x99,0x9c,0x0f,0xb2,0x98,0x2e,0x53,0xa3,0xff,0x81,0xe6,
+  0x83,0x98,0xf6,0xdb,0x34,0xfc,0x43,0x82,0x13,0x2a,0xff,0x03,0xe3,0x9f,0x38,0x20,
+  0xe7,0x6f,0x5e,0x3b,0x1f,0x36,0x8b,0xfe,0x07,0xe3,0x1f,0x2f,0xce,0x46,0x20,0xf4,
+  0x7f,0xf1,0xfc,0x3c,0xf3,0x10,0x30,0x1f,0x8d,0x57,0x73,0xe8,0x32,0x07,0xe8,0x1b,
+  0xf7,0x80,0x52,0xff,0xba,0xe4,0xde,0x45,0xd5,0x3e,0x7c,0xbd,0x43,0x62,0x23,0xb3,
+  0x99,0xff,0x19,0x0f,0x26,0x16,0xb4,0x0e,0x14,0xba,0xf2,0xed,0xe1,0x1b,0x52,0x2b,
+  0xfe,0x86,0x16,0x5e,0xff,0x02,0xf0,0xcf,0x3b,0xe8,0x78,0x5f,0xe3,0x36,0x3c,0x31,
+  0xd6,0xe9,0x0d,0x1e,0x7e,0xb4,0xfa,0x5f,0x2d,0x8f,0xd7,0xbf,0x00,0xfd,0x4f,0xbf,
+  0x1f,0x3e,0x18,0x78,0x10,0x61,0x33,0xea,0x0d,0x9f,0x90,0xf5,0x2d,0x96,0x65,0x9a,
+  0x0f,0x12,0xa5,0xbd,0x11,0x85,0xdf,0x1f,0x5e,0xbf,0xab,0xb1,0x54,0x7d,0xa4,0xa3,
+  0x85,0xed,0x27,0xff,0xd7,0xde,0xd5,0x07,0xd7,0x55,0x5c,0xf7,0xb3,0xf7,0xed,0x95,
+  0xaf,0xa4,0x27,0xeb,0x3e,0xe9,0x3d,0xfb,0xc1,0x18,0xb8,0x92,0x0d,0x68,0x88,0x21,
+  0x4f,0xc2,0x80,0x83,0x29,0xba,0x7a,0xfa,0xb0,0xfc,0x01,0x7e,0xd8,0xb2,0x51,0xa9,
+  0xa6,0x73,0xcd,0xb8,0x0c,0x9d,0x71,0x33,0xb6,0x3b,0x0d,0x74,0x9a,0xc2,0x7d,0x92,
+  0x30,0x9a,0x40,0xca,0xab,0xe3,0x0e,0x62,0x86,0x19,0x5e,0x52,0x4f,0xca,0x4c,0x68,
+  0x47,0x40,0x08,0xce,0x40,0xe2,0x27,0x23,0x1b,0x07,0x13,0xaa,0x52,0x27,0xf1,0x50,
+  0x0f,0xb6,0x3b,0x2e,0xe3,0xb4,0x06,0x9c,0xc1,0x09,0x76,0xc0,0xb8,0x67,0x77,0xef,
+  0xc7,0xde,0xf7,0x25,0x19,0x02,0xed,0x24,0xf7,0xfc,0xe3,0xdf,0xec,0x5b,0x5d,0xef,
+  0xdd,0xbb,0x7b,0xf6,0xb7,0x67,0xf7,0x9c,0x53,0xc2,0x7f,0x38,0xf8,0x00,0x52,0x85,
+  0xc5,0xec,0x46,0xfd,0x2b,0x76,0x87,0xb9,0x66,0x77,0xbd,0x5e,0xea,0xff,0x15,0x18,
+  0x0f,0xe7,0x61,0x0f,0x03,0x9f,0xd8,0x17,0xd8,0x7a,0xd7,0x56,0xe6,0xfc,0xcb,0x35,
+  0xfb,0x30,0x70,0x82,0x5b,0xe4,0xa2,0xe2,0xc6,0x7e,0x87,0xb9,0xf8,0xd9,0xfa,0x54,
+  0xa5,0xfb,0x3f,0xee,0xfd,0x67,0xe4,0xc3,0x1a,0xe3,0xb7,0x2f,0xa9,0xad,0x47,0xf0,
+  0x45,0x3a,0x2a,0xd9,0x7f,0x9c,0xf9,0xf2,0x1c,0xf0,0xc0,0xce,0x94,0x97,0x20,0x48,
+  0x79,0xfa,0xe7,0x98,0x6c,0xff,0xd9,0xe3,0x1e,0x0c,0x7d,0xdf,0x5e,0x6c,0x69,0x5f,
+  0x57,0x2e,0x67,0x25,0x79,0x6d,0xb3,0x92,0x2c,0xc7,0x7f,0xb8,0xd9,0x87,0x81,0x29,
+  0x56,0x62,0x47,0x53,0x11,0xfc,0xc9,0x4c,0x15,0x10,0x5c,0x5a,0xc9,0xfe,0xb3,0xc7,
+  0xeb,0x28,0xf8,0xf2,0x34,0x8b,0x9f,0xa0,0xef,0x99,0x81,0xff,0x3c,0xb6,0x3b,0xf2,
+  0x2f,0xf0,0x1a,0x76,0x54,0x54,0xe8,0xab,0x0e,0xb3,0x71,0x3c,0x52,0xe7,0xfb,0x7f,
+  0x95,0xf0,0x1f,0x76,0xec,0x35,0xca,0xb6,0x51,0x8e,0x86,0xb1,0xeb,0x4d,0xe5,0x66,
+  0x29,0xde,0x45,0x31,0xff,0x39,0xab,0x6c,0x87,0x11,0xdb,0xe0,0x19,0x63,0xd9,0xfb,
+  0x5a,0xf5,0x49,0x69,0xff,0x85,0xfc,0x47,0x2f,0x1e,0x6f,0x51,0x65,0x04,0xf2,0x53,
+  0x6d,0x29,0xe5,0x0d,0x78,0x3e,0x63,0x1c,0xab,0x4f,0xd6,0x35,0x49,0xf1,0xb1,0x4b,
+  0xf9,0xcf,0xd3,0xf0,0x06,0xb4,0x4f,0xe0,0xb6,0xe2,0xb7,0xf0,0x89,0xfd,0x7c,0xbe,
+  0xf1,0xbf,0x23,0x4b,0x67,0xe6,0x3f,0x1a,0x03,0xe6,0x59,0xf8,0x31,0x9d,0x05,0xff,
+  0xf9,0x15,0x1b,0x36,0x08,0xe8,0x4f,0xb4,0x94,0x19,0x9d,0x89,0xff,0xfc,0x17,0xfc,
+  0x30,0xdd,0x9a,0xd1,0x72,0xfc,0xbe,0xca,0x77,0xcc,0xb6,0x9d,0x33,0xf1,0x1f,0xe3,
+  0x25,0xad,0x35,0xbd,0x72,0x9c,0x1f,0xdc,0xb4,0x9a,0x5a,0x6e,0x78,0x06,0xfe,0xb3,
+  0xeb,0xd9,0x36,0x63,0x65,0x9d,0x8e,0xf5,0xb3,0x00,0x2b,0xb5,0xa6,0xe1,0x19,0xf8,
+  0x8f,0x7d,0xd6,0xe8,0xd0,0xe6,0xb2,0x92,0x03,0xd0,0xa1,0xad,0x1e,0x96,0xfd,0xbf,
+  0xca,0xf0,0x9f,0x33,0x6c,0x7e,0x99,0x0d,0xd3,0xcd,0x67,0x94,0x5f,0xb3,0xd4,0x8d,
+  0xd3,0x33,0xdd,0x7f,0x36,0xce,0xb5,0x75,0xb0,0x8c,0x90,0xbc,0xa3,0x56,0x46,0x77,
+  0x8c,0x54,0xe5,0x3f,0xf8,0x45,0x76,0x9b,0xad,0x6e,0xa2,0xd8,0x6b,0x74,0x6d,0x2a,
+  0x10,0xff,0xa7,0x84,0xdd,0xa5,0xa7,0xe0,0x05,0xbb,0x25,0xa3,0x65,0x9a,0x0e,0xc1,
+  0x1e,0xf8,0xb6,0xa5,0x0d,0xca,0xf1,0xb1,0x03,0xfc,0x47,0x11,0xf1,0x97,0xcc,0x1f,
+  0xd1,0x85,0x66,0xdb,0x9b,0xca,0x19,0xfb,0x47,0xc6,0x97,0x98,0xa1,0xec,0x9d,0xaa,
+  0xe7,0x5f,0xef,0xc0,0xb9,0xc2,0x73,0xe9,0x28,0x03,0xbf,0xd2,0x3a,0x32,0x8b,0x77,
+  0x4a,0xfc,0xa7,0x5c,0xfc,0x1f,0xac,0x6f,0xdc,0xc2,0x1c,0xe1,0xdf,0x29,0x3d,0xff,
+  0x2a,0xe1,0x3f,0x73,0xdc,0xc0,0x0b,0xc2,0x11,0xde,0x4c,0xc1,0x9a,0x82,0x14,0x3f,
+  0xb9,0x84,0xff,0xc8,0xfe,0x5f,0xbf,0x44,0xd0,0xca,0x40,0xdd,0x4c,0xfc,0x47,0x44,
+  0x2c,0xf9,0xa9,0xcd,0xf4,0xcf,0x2a,0x03,0xeb,0xbb,0xe3,0xad,0x84,0xff,0x3c,0xc2,
+  0xc0,0x0b,0xc2,0x1e,0x72,0x84,0xf5,0x27,0xd4,0xdf,0xab,0xb4,0x79,0xf5,0xcb,0xd8,
+  0x7f,0x22,0x6f,0xc1,0x6f,0xec,0x3f,0xca,0x37,0x0e,0xf2,0x92,0x76,0x16,0x88,0xec,
+  0x1a,0xdf,0xff,0xab,0x0c,0xff,0x39,0xc9,0x5e,0xdc,0x8e,0xd8,0xac,0x84,0x62,0x57,
+  0x54,0xca,0x8f,0xe6,0x80,0x6e,0x76,0xfe,0x75,0xfd,0x71,0x2c,0xb9,0x14,0xf6,0x31,
+  0x46,0x74,0x32,0x52,0xb0,0x03,0xfc,0xa7,0x84,0xb6,0x3d,0xc4,0x88,0x8d,0x85,0x6a,
+  0x13,0x01,0x20,0x08,0xf8,0xbf,0x97,0xd4,0x3f,0x0c,0xdf,0x61,0x6a,0x6a,0x5a,0x19,
+  0x34,0xf8,0x1f,0xde,0x5f,0x99,0xff,0xf0,0x40,0x1c,0x27,0xc1,0xb6,0x21,0x5f,0xaf,
+  0x31,0xfb,0xcf,0x31,0x43,0xaf,0x5f,0x52,0x3e,0x3f,0x9a,0x7c,0x7f,0x20,0x8f,0x6a,
+  0x73,0xf7,0xc8,0x3d,0xf0,0xda,0x81,0x8e,0x63,0xf8,0xe9,0x25,0xff,0xaf,0x32,0xfc,
+  0xe7,0x3d,0x1c,0x36,0x2f,0xf7,0x34,0xe6,0x57,0xed,0x42,0x0d,0x76,0x8b,0x71,0x05,
+  0x48,0xfe,0x5f,0xc8,0x7f,0x92,0xa5,0xb7,0x3b,0xde,0x86,0x4e,0x35,0x3a,0xdd,0x7a,
+  0x06,0x15,0xdd,0xf5,0x7b,0xa3,0xff,0x36,0x02,0x9e,0xff,0x97,0x5d,0x86,0xff,0x9c,
+  0x04,0x76,0xbe,0x8c,0xf3,0x6b,0x0a,0x86,0xd9,0x42,0x9c,0x53,0x8c,0x99,0xec,0x3f,
+  0x2c,0x50,0xff,0x84,0xf2,0x9f,0x74,0x0c,0x57,0x40,0x96,0xca,0x79,0x06,0xfb,0x0f,
+  0xbb,0x86,0xd7,0x66,0x60,0x37,0x8e,0xd9,0x79,0x68,0x83,0x3a,0xa5,0x9a,0xfd,0x47,
+  0xa4,0x2d,0x80,0xd5,0xb9,0xc8,0x31,0x7a,0x80,0x2d,0x34,0xb9,0x08,0x54,0xb3,0xff,
+  0x44,0xce,0xc2,0xc7,0xa4,0x13,0xd6,0x98,0x91,0xd3,0xf0,0x31,0xed,0x84,0xc7,0xa6,
+  0x67,0xef,0xff,0xf5,0xaf,0x17,0x69,0xff,0xf9,0xde,0x45,0xdd,0x7f,0xf6,0x0c,0x5f,
+  0x55,0xce,0xbf,0x6a,0xcb,0x9d,0x27,0xce,0xfa,0xfe,0x33,0x0b,0xbd,0xbe,0x66,0xa2,
+  0x7b,0x36,0xfe,0x5f,0x0e,0xf8,0x72,0x15,0xfb,0x4f,0x45,0x50,0x64,0xff,0xa1,0x33,
+  0xdf,0x7f,0x76,0xc7,0x43,0xd5,0xfb,0xcf,0xa7,0x3e,0xcd,0xfd,0xe7,0x93,0x95,0xec,
+  0x3f,0xa5,0x66,0x1f,0x0e,0x0e,0x54,0x38,0xff,0x2a,0x8a,0x0f,0x30,0xf5,0xd4,0x69,
+  0xfe,0xbe,0xff,0x3f,0xed,0x3f,0xbe,0xff,0xd7,0x17,0x68,0xff,0xa1,0x9f,0xb7,0xfd,
+  0xe7,0x2b,0x17,0x7d,0xff,0xf9,0x1a,0x0e,0xc8,0xe7,0x66,0xff,0xa9,0x90,0x18,0xb7,
+  0xd8,0xff,0xeb,0x22,0xec,0x3f,0xb3,0xca,0xaf,0x5a,0xc9,0xff,0x6b,0x66,0xff,0xf7,
+  0xb2,0xf9,0x61,0x83,0xe0,0x91,0x80,0xfd,0x47,0x2d,0x63,0xff,0x29,0xed,0xcf,0x40,
+  0xfc,0x9f,0x32,0xcd,0x26,0xc1,0x44,0x78,0x92,0xfd,0x67,0x76,0xfe,0x5f,0x3e,0xff,
+  0x81,0x8b,0xb4,0xff,0x54,0xf1,0xff,0x2a,0x1b,0xff,0x30,0x51,0x45,0xff,0xf8,0xf6,
+  0x1f,0xef,0xfe,0x73,0x59,0xff,0xaf,0x2a,0xf1,0x7f,0xda,0xca,0xf0,0x1f,0x19,0xf0,
+  0x8c,0x21,0xcd,0xb3,0xb3,0xff,0x2c,0x2c,0xe7,0xff,0x95,0xa8,0xba,0x7e,0x39,0xf6,
+  0x1f,0xc9,0xff,0xeb,0x12,0x49,0xff,0x7c,0xe8,0x37,0x7b,0x31,0xb7,0x08,0x31,0x50,
+  0xc6,0xfe,0x53,0xf5,0x7d,0x99,0xfd,0xc7,0xcf,0x3f,0x68,0xd1,0x6a,0xfa,0xc7,0x75,
+  0xcd,0xa8,0xe0,0xff,0x55,0x16,0x4c,0x3e,0x26,0xc7,0xff,0x91,0xf9,0x0f,0x09,0x1c,
+  0x9c,0x3d,0x25,0xfd,0xe1,0x89,0xf2,0xf6,0x9f,0xf7,0x45,0x76,0xf8,0x59,0xfb,0x7f,
+  0x7d,0x54,0x1a,0xd8,0xa7,0xaa,0xff,0x57,0x00,0xd4,0x4d,0xf0,0x08,0x36,0x5f,0x2d,
+  0xe7,0xff,0xb5,0xb9,0xe2,0x78,0x23,0x9b,0xdf,0xaa,0x4f,0xb5,0x96,0xf8,0x7f,0xb9,
+  0xf6,0x9f,0x9b,0xa5,0xf3,0x3e,0x04,0x06,0x82,0xc3,0xe5,0xfc,0xbf,0xf8,0xdb,0xd1,
+  0x40,0x3e,0xb8,0x35,0xd2,0x89,0x86,0xc4,0x7f,0xbe,0x29,0x46,0x4b,0xd9,0xb0,0x87,
+  0xc8,0x7f,0x0a,0x45,0xf7,0x7f,0x0a,0x10,0xa4,0x3d,0xc7,0x05,0xd8,0x2e,0x2e,0x42,
+  0xeb,0x8f,0x40,0x6b,0x90,0xff,0x9c,0x64,0xf1,0x0f,0x69,0xa5,0xf5,0x3d,0x3f,0x62,
+  0x18,0xc2,0xbe,0xea,0x8e,0x1f,0x37,0xfe,0x8f,0x14,0x2d,0xb9,0x49,0x32,0x04,0x8d,
+  0x10,0x66,0x51,0x49,0x9f,0xf5,0xf4,0x89,0x4a,0xc5,0xf8,0x99,0x5b,0x6e,0x9a,0xbc,
+  0x01,0x07,0x29,0xb7,0xd8,0x94,0x8f,0xff,0x6c,0x14,0x0f,0x83,0x4f,0xd2,0x6e,0xff,
+  0xf8,0xfe,0x5f,0x5e,0xbc,0xcd,0x66,0x7f,0xe0,0xe9,0x5e,0xa2,0xd8,0x83,0xd0,0x31,
+  0x89,0xfc,0x4a,0x8a,0xff,0x13,0xf7,0xf8,0xf0,0xbb,0x65,0x0c,0x41,0xd8,0x3f,0x93,
+  0x41,0xff,0xaf,0x32,0x7c,0xf8,0x75,0x70,0x33,0xbc,0x93,0x11,0xe1,0x41,0x29,0xc5,
+  0xff,0x91,0xf2,0xc3,0x1a,0x5e,0xfc,0x67,0xc7,0x10,0xf4,0x0b,0xed,0xe1,0x42,0x4b,
+  0xf0,0xfc,0xeb,0x5e,0xe0,0xfc,0x67,0xca,0xa7,0x3d,0x37,0x63,0xb7,0x7c,0x04,0x4e,
+  0xc6,0xb4,0x83,0x34,0x55,0x74,0xfe,0x15,0xaf,0x36,0x1f,0xcd,0x8f,0x74,0x71,0x9e,
+  0xe8,0xc7,0x3f,0x8c,0x56,0xa9,0xff,0x1e,0x1c,0x1c,0xe6,0xfd,0xef,0xc7,0x77,0x3a,
+  0x50,0xac,0x4f,0x56,0x6d,0xf1,0xfd,0x4f,0x0f,0xf1,0xf3,0xf4,0x0a,0xf1,0x9f,0xcb,
+  0xf2,0x9f,0x87,0xc5,0x8b,0x4b,0xf1,0x9f,0x83,0xf7,0x0f,0x8b,0xe3,0xb9,0x8d,0x08,
+  0x0b,0x9b,0xcf,0x7f,0x0a,0xea,0xd3,0x7a,0x65,0xfe,0x83,0x03,0xf3,0xb9,0x2a,0xf1,
+  0x0f,0x4b,0x80,0x56,0xca,0x7f,0xfc,0xf5,0xee,0x1d,0x9b,0x81,0x86,0x19,0xf8,0x4f,
+  0x7c,0x91,0xeb,0xed,0xfe,0x0e,0x07,0x22,0xfe,0x1e,0x15,0x86,0x20,0xbb,0x6a,0x7e,
+  0x58,0x0e,0x6a,0xa5,0xfa,0xf8,0x84,0xe1,0x62,0xff,0x2f,0x08,0xf0,0x1f,0x7c,0xbe,
+  0xb8,0xff,0xb3,0xd9,0x29,0xc9,0x16,0xf9,0x7f,0x0d,0x82,0xcb,0x7f,0x9a,0xc5,0x6b,
+  0x36,0x48,0xef,0x5b,0xd0,0x4e,0x97,0xc4,0x7f,0xae,0xc6,0x67,0xce,0xec,0x72,0x3c,
+  0xe2,0xcb,0xda,0x7f,0x44,0x36,0xd8,0x35,0xfe,0xb5,0xf0,0xc8,0xaf,0xe1,0xa7,0xc5,
+  0xe7,0x5f,0xd5,0xf3,0xc3,0x6a,0x63,0xc5,0xfc,0xe7,0x5e,0x28,0xba,0xff,0xfc,0x27,
+  0x7a,0x93,0xec,0xff,0xd5,0x56,0x14,0xff,0x67,0x77,0xf9,0xfc,0xb0,0xa2,0x3f,0x4f,
+  0x8c,0x09,0xff,0xaf,0xb4,0x14,0xff,0xb9,0x3c,0xff,0xf1,0xfc,0xd7,0x04,0x11,0x92,
+  0xe2,0x1f,0xc2,0x2e,0xea,0x57,0x53,0x8a,0x68,0x9e,0xe2,0xda,0x7f,0xfc,0xf8,0x87,
+  0xd2,0x78,0x33,0x9c,0xc4,0x7c,0xd2,0xc0,0x3b,0x50,0xec,0xff,0x25,0xe5,0x87,0xfd,
+  0xc8,0xf6,0x69,0x0f,0xbd,0x4e,0xf8,0x7f,0xfd,0x5d,0x31,0xff,0x91,0xf6,0xe3,0x05,
+  0x0e,0xe4,0xf8,0xab,0xa7,0x94,0x11,0xa1,0xba,0x0f,0x7a,0xe3,0x81,0xf8,0x41,0xda,
+  0xa7,0x75,0x31,0x7f,0x95,0x23,0xfa,0x8b,0xe4,0x2f,0x84,0x61,0x64,0xbb,0xe3,0xff,
+  0xe5,0x3e,0x1e,0xb4,0x31,0x8f,0xff,0x88,0xfc,0xb0,0x73,0x25,0xfe,0xf3,0x1b,0x78,
+  0x55,0x80,0x83,0xde,0xfd,0xe7,0x36,0x5f,0xff,0xc8,0xf9,0x40,0x15,0x67,0x59,0x77,
+  0xf9,0xcf,0x76,0xf7,0x7d,0xcd,0x47,0x7f,0xdc,0xef,0xac,0x56,0x6f,0xc1,0xfb,0xa3,
+  0x08,0xce,0xb1,0x40,0xbe,0x3b,0x44,0xc6,0x34,0xb8,0x30,0xca,0x7f,0x0a,0xe4,0x87,
+  0xf5,0xb4,0x8d,0xc8,0xef,0x76,0x33,0x8b,0xff,0x9c,0x17,0x86,0x1d,0xeb,0x07,0xce,
+  0xfd,0x67,0xcf,0xfe,0x93,0x87,0x27,0x75,0xf7,0x7d,0xbd,0x8b,0x40,0xa6,0xe3,0xf6,
+  0x7e,0xa8,0xd4,0xff,0x4b,0x8a,0x7f,0x38,0xc5,0x77,0xf7,0x07,0x27,0x7c,0x45,0x34,
+  0xc5,0x23,0xfa,0x06,0xf8,0x8f,0xa6,0x3e,0x43,0xbd,0xf7,0xfd,0x5e,0xa9,0x61,0x87,
+  0x3e,0x50,0x68,0x0c,0xc4,0x7f,0x26,0x5e,0x3c,0xde,0xe3,0x3e,0x11,0x72,0x0d,0x23,
+  0xf1,0xb3,0xee,0xa3,0xdc,0xfa,0xc4,0x5f,0xef,0x4e,0xf3,0xb4,0x68,0x8d,0xa7,0x95,
+  0xaf,0x53,0x56,0x12,0x3d,0x1d,0xb9,0x80,0x0b,0xfd,0xf5,0x85,0x40,0xfc,0x9f,0xc9,
+  0xb8,0xe7,0xbf,0x33,0xe9,0xde,0xdf,0x10,0x2b,0x5a,0x03,0xae,0x5f,0xda,0x4b,0xb9,
+  0x56,0xe1,0xff,0xe5,0x7e,0x2f,0x1b,0x16,0xc3,0x32,0x85,0xb3,0x9d,0x93,0xc1,0xb4,
+  0x68,0x3c,0x70,0xf1,0x0f,0xc5,0xc2,0x17,0xe0,0x3f,0x9a,0xc3,0x7f,0x9c,0xfc,0xb0,
+  0x3f,0x50,0xbe,0x39,0xfa,0xbc,0xc1,0xdd,0xa0,0x0e,0x68,0x13,0x90,0x2f,0xac,0x4a,
+  0x35,0x49,0xfc,0x07,0x36,0xfb,0xe3,0x81,0xe7,0xcf,0x7d,0x39,0xf2,0x3e,0x7c,0xf4,
+  0xf4,0xad,0x4e,0xa0,0x48,0x45,0xac,0xef,0x1e,0xff,0xc9,0xfa,0xf7,0x9f,0x4f,0x13,
+  0x0e,0x5e,0x8e,0x3c,0xe8,0x84,0xed,0x65,0x1e,0xdf,0xb4,0x4c,0xfc,0x9f,0xa3,0xf6,
+  0x4d,0xdc,0x6c,0x18,0xbc,0x48,0x1f,0x3d,0x1b,0x79,0x8f,0x1e,0x1c,0x2e,0xf2,0xff,
+  0x92,0xed,0x3f,0xfa,0x32,0x04,0x11,0x97,0x08,0xd5,0xb9,0xf6,0x9f,0x80,0xff,0x97,
+  0x63,0xff,0x29,0xbd,0xff,0xcc,0x8e,0x75,0x4e,0x71,0xff,0xa6,0x64,0xc0,0xff,0xcb,
+  0xb1,0xff,0x44,0x26,0xf4,0x53,0xb0,0x4c,0xf6,0xff,0xfa,0x86,0x6b,0xff,0xa9,0x9b,
+  0x48,0x4b,0xf6,0x9f,0xf8,0x33,0xf1,0xff,0x20,0x37,0x4e,0x36,0x4e,0x90,0x53,0xf0,
+  0x37,0xe2,0x36,0xb8,0x18,0x3f,0xec,0xfc,0x45,0x3f,0xc8,0x01,0x6e,0xd5,0xdd,0xe7,
+  0x1f,0xb7,0x5f,0x86,0xa3,0xb0,0x06,0x3b,0x61,0xe1,0xc7,0xb4,0xa2,0x23,0x58,0xf9,
+  0xf3,0x2f,0x37,0x30,0xc5,0x62,0x8f,0x11,0xb9,0x25,0xc5,0xf9,0x2f,0xbe,0xca,0x0e,
+  0x49,0x5d,0xda,0x16,0x48,0x84,0xc1,0x03,0x63,0x82,0x1f,0xff,0xd9,0xe7,0x3f,0x69,
+  0xff,0xbc,0xc6,0x9d,0x2f,0xa7,0x5c,0x50,0x64,0xff,0x19,0x65,0xab,0x7f,0xda,0x3b,
+  0x0f,0x92,0x3d,0xc2,0xf2,0xd7,0x8a,0xab,0x41,0xee,0xf3,0x85,0xfd,0x67,0x71,0xa1,
+  0xb1,0xdd,0xe5,0x3f,0x13,0x11,0xc1,0x88,0xae,0x60,0xf1,0x9f,0x3f,0xc8,0xf3,0x40,
+  0xd0,0xb2,0xfd,0xe7,0x16,0xb9,0x37,0xae,0x28,0x34,0xca,0xf1,0x7f,0xcc,0x0b,0xfa,
+  0xad,0xe5,0xed,0x3f,0xb8,0x49,0x29,0x4a,0x9b,0x2b,0x25,0x3a,0x0c,0xda,0x7f,0x74,
+  0xcf,0x6c,0x5e,0x7e,0x63,0xb5,0x4a,0xf6,0xff,0xaa,0x66,0xff,0x49,0x7b,0x25,0xc7,
+  0x66,0xb2,0xff,0x90,0xcf,0x64,0xff,0xe9,0xae,0x98,0xff,0xa2,0x42,0x3e,0x88,0xd9,
+  0xda,0x7f,0xe2,0xe7,0xc8,0xc5,0xf9,0xbf,0x97,0xe4,0x87,0x2d,0xe1,0x3f,0x81,0xf5,
+  0xba,0x8c,0xfd,0x07,0x66,0xb2,0xff,0x74,0x05,0xec,0x3f,0xbb,0xb5,0xd9,0xf8,0x7f,
+  0x5d,0xac,0xfd,0xc7,0xf7,0xff,0x1a,0x9f,0x4d,0xfc,0x9f,0x8b,0xb6,0xff,0xbc,0x3d,
+  0x4b,0xfb,0xcf,0x82,0x67,0xc9,0x62,0xf3,0xa0,0xde,0x5a,0xe9,0xfc,0xab,0x02,0xa8,
+  0x91,0xfc,0xdf,0x8b,0xe3,0xff,0xcc,0x74,0xff,0x67,0x56,0xf6,0x9f,0x2a,0xe7,0x5f,
+  0x25,0x80,0x3c,0x16,0xc8,0x7f,0xf1,0xf9,0xc4,0xff,0xf1,0xec,0x3f,0x2d,0xcc,0xfe,
+  0x43,0x2f,0xca,0xfe,0x53,0xfb,0xe1,0x43,0x33,0xda,0x7f,0x7c,0xff,0xaf,0xcb,0x9e,
+  0x51,0x2b,0xef,0xbf,0x74,0x71,0xff,0xa7,0x3b,0x60,0xff,0x31,0x8f,0xe6,0x3a,0x8f,
+  0x3b,0xf1,0x7f,0x4a,0xec,0x3f,0x06,0x27,0x42,0x45,0xf6,0x1f,0xdd,0x8f,0xf6,0xe3,
+  0x35,0xfb,0xe4,0x2a,0x6e,0x11,0xd2,0x17,0x1f,0x0b,0xd8,0x7f,0xc6,0xe1,0x49,0xf2,
+  0xa2,0x52,0xc1,0xec,0x73,0x84,0x3d,0x8a,0x81,0x29,0xcf,0xff,0xcb,0xa2,0xaf,0xab,
+  0xc5,0xda,0xe6,0x75,0x4f,0xc3,0xc7,0x9d,0x9f,0x7c,0xfe,0xb3,0x34,0xf1,0x8c,0x97,
+  0xc6,0x42,0x2f,0x56,0x9b,0xa7,0x54,0x87,0xf8,0x95,0x8f,0xff,0x43,0x8a,0x17,0x26,
+  0xef,0x86,0x8c,0x1f,0xff,0x27,0xeb,0xd9,0x7f,0xaa,0xc5,0xfb,0xf5,0xd7,0xeb,0xc9,
+  0xd1,0xcd,0x7a,0x79,0x7b,0x8e,0xb7,0xa2,0x3d,0x12,0xf4,0xff,0xda,0xac,0x8b,0x43,
+  0x99,0xb5,0x22,0xbb,0x41,0x1d,0xaf,0xa6,0xcc,0x10,0xff,0x07,0x3b,0xe1,0x1e,0x2f,
+  0xdb,0x05,0xf6,0x4f,0xcd,0xe6,0x03,0xee,0xc1,0xeb,0xde,0x80,0xff,0x97,0xad,0x6d,
+  0xa6,0xff,0x23,0x3a,0xc1,0xcb,0x76,0xe1,0xdd,0xff,0x79,0x97,0x5d,0x44,0x39,0x8c,
+  0xe3,0xa1,0xc8,0xfe,0x23,0x48,0x8e,0x97,0xed,0xe2,0x63,0x37,0xec,0xcf,0xc7,0xf9,
+  0x0b,0x6d,0xb7,0xbe,0x16,0xe0,0x3f,0x15,0xf2,0xf1,0xe5,0x5f,0xff,0x5d,0xe7,0xe3,
+  0x6b,0xd5,0xc1,0xcd,0x8e,0xa7,0x8d,0x2a,0x2d,0x30,0x86,0x25,0x1e,0xf8,0x4c,0xcf,
+  0x0f,0xf3,0x21,0x7e,0x9e,0xf9,0x10,0xcd,0xa2,0x12,0xa8,0x94,0x0f,0x71,0x41,0xa1,
+  0xf4,0xb1,0x0f,0xa7,0x10,0xfc,0x65,0xf9,0x7c,0x88,0x7a,0x99,0x8e,0xa4,0x0c,0x98,
+  0xe5,0xfb,0x5f,0x2f,0xd3,0xed,0xa3,0x0c,0x98,0xe5,0xf3,0x21,0x46,0x0b,0x95,0xfb,
+  0x3c,0xcc,0x87,0x58,0x1d,0xfc,0x21,0xd7,0xff,0x02,0xe7,0x23,0xd7,0x7e,0x4c,0x1f,
+  0x3a,0x1a,0x52,0x0b,0xf3,0xc3,0xca,0xfd,0xff,0x70,0xea,0xf3,0xed,0x7f,0x7b,0xd6,
+  0xfa,0x90,0x29,0x3d,0xfe,0xb4,0x30,0x3f,0x6c,0x91,0x84,0xfa,0xf0,0xf7,0xbc,0xfe,
+  0xbe,0xae,0xc8,0x16,0xf3,0x88,0x7e,0x13,0xa8,0x59,0x01,0xe2,0xea,0xbe,0xc8,0x56,
+  0x73,0x48,0xbf,0x2f,0xde,0xf0,0x2a,0x03,0x99,0xf9,0xf4,0xb2,0x42,0xbb,0x57,0xbf,
+  0xb7,0x47,0xdd,0x4a,0x86,0xcc,0x3b,0x75,0x70,0x81,0x3a,0xc5,0x41,0xb7,0x9e,0x98,
+  0x22,0xa2,0x24,0x51,0x88,0xb9,0x7c,0x15,0x6c,0x85,0x18,0x76,0xbf,0xd1,0xa4,0xd1,
+  0x61,0x01,0x92,0x74,0x3b,0x69,0x41,0x30,0xdf,0x29,0xb1,0xf0,0x27,0xdb,0xf0,0x9e,
+  0x6f,0x03,0xb1,0x60,0x10,0xe6,0xc1,0x4e,0x5b,0x00,0x4d,0x45,0x40,0x06,0x95,0x79,
+  0x49,0x75,0x94,0x6c,0x24,0x83,0xb0,0x01,0x12,0x52,0xfd,0x7d,0x83,0x57,0xde,0x48,
+  0x6e,0xb3,0xd7,0x75,0xd1,0x31,0x75,0x1b,0x19,0xb2,0xef,0x34,0x12,0x07,0x38,0x98,
+  0x8f,0x80,0x20,0xc8,0x63,0x49,0xa1,0xdd,0x6b,0xcf,0xbe,0x2e,0xd3,0xd0,0x35,0xaa,
+  0x10,0xfc,0x9f,0x2c,0x48,0x9a,0x35,0x40,0x86,0xc1,0xb2,0x93,0xd0,0x07,0xc4,0xa6,
+  0x06,0x02,0x2c,0xb1,0xfd,0xf7,0xdd,0xd7,0x4f,0xef,0x26,0x49,0xbb,0xcf,0x80,0x31,
+  0xda,0x4a,0x34,0x3b,0x6d,0xe8,0x63,0xd4,0x10,0xc0,0xa6,0x16,0xd1,0x80,0x01,0xa9,
+  0xfe,0x2a,0x75,0x6d,0x76,0x20,0xbf,0xbe,0x8d,0xce,0x55,0xd3,0xd9,0xcc,0xe9,0x81,
+  0xb6,0x44,0x9d,0xda,0x35,0x9a,0xc9,0x23,0xa8,0x51,0xcd,0xd1,0x8c,0x11,0xbf,0x45,
+  0x05,0xbf,0x3d,0xf6,0x02,0x32,0x07,0xd6,0x17,0x12,0x19,0x7a,0x39,0xb9,0x13,0x41,
+  0x6c,0x8b,0x3a,0x44,0xd6,0xc1,0x40,0x21,0x91,0x52,0xff,0x94,0x44,0x18,0x58,0x4a,
+  0x3d,0xf3,0x0f,0xd6,0x67,0x1a,0xa0,0x09,0xa8,0xad,0x53,0xa6,0xf9,0x4c,0x02,0x31,
+  0x80,0x6e,0x1b,0xb5,0x97,0x4e,0x28,0xaa,0x86,0xa4,0x4d,0x75,0xe8,0x92,0xfa,0xc7,
+  0x52,0x34,0x60,0x1d,0x9d,0xcc,0x33,0x00,0x2d,0xa8,0x43,0x38,0x30,0x6c,0xcd,0xa8,
+  0x71,0x40,0x97,0xd4,0x3f,0x19,0x75,0x11,0xf9,0x63,0xd8,0x60,0xc6,0x73,0x64,0x13,
+  0x07,0x89,0x9c,0x6a,0xc1,0x61,0xd6,0xed,0x39,0xd5,0x20,0x87,0xe1,0x6b,0xd8,0xff,
+  0xd2,0xfb,0x9a,0x11,0xf6,0x99,0x6e,0xc4,0x16,0x45,0x58,0xb5,0xaf,0xc1,0x6d,0x76,
+  0xe4,0x6e,0x2c,0xb9,0x89,0x1d,0x25,0x21,0xb0,0xe7,0x21,0x90,0xc6,0x4f,0x9a,0xa6,
+  0xec,0xa8,0xd1,0xad,0x69,0xc3,0x34,0x95,0x65,0x40,0xdf,0xcb,0x41,0x1f,0x02,0x70,
+  0x4a,0xa4,0xef,0x85,0x92,0xc2,0x3d,0x55,0x84,0x8d,0x0c,0x07,0x14,0x38,0x50,0xd8,
+  0x61,0x8b,0x5b,0x22,0xf5,0x8f,0x42,0x52,0xf6,0x6a,0xa3,0x99,0x8d,0x2e,0x06,0xd6,
+  0x69,0x74,0x2f,0x49,0x4d,0xf2,0x92,0x83,0x0c,0xa4,0xb0,0x44,0xaa,0xbf,0x2f,0xad,
+  0x5a,0xd9,0x41,0x63,0x03,0xd0,0x61,0x01,0xb4,0x04,0x82,0x49,0x0e,0x46,0x08,0x4c,
+  0x0e,0xa6,0x10,0xd8,0x52,0xff,0xa4,0x79,0xcf,0xf1,0x2e,0x04,0x17,0x18,0xf8,0x46,
+  0x0c,0x50,0x06,0x22,0x1a,0xc8,0xef,0xbb,0x96,0x5a,0xd9,0xa4,0xd1,0xd7,0x0f,0x3b,
+  0x10,0x5c,0x82,0xaf,0x19,0x1b,0xa6,0x9b,0xd8,0xfb,0xf6,0xc7,0x76,0x50,0x83,0xbd,
+  0x6f,0x7f,0xcc,0x8e,0x49,0xdf,0x4b,0x1d,0x24,0x1b,0x60,0x3d,0x8e,0x45,0x0e,0x12,
+  0x76,0x02,0x4b,0x68,0x1f,0x96,0x20,0xd0,0x70,0x98,0xc6,0xec,0x84,0x29,0x8d,0x9f,
+  0x1a,0xb2,0xd5,0x1e,0xb0,0x12,0xe3,0xb4,0x86,0x74,0xd9,0x19,0x2b,0x9e,0x54,0x4b,
+  0x01,0x18,0xde,0x92,0x54,0x68,0xc2,0x4d,0xb3,0x66,0x00,0xb6,0x07,0xa7,0x40,0x97,
+  0x98,0x0b,0xd4,0xc6,0x49,0xd1,0x4f,0x9b,0xb0,0x84,0x03,0xef,0x78,0x01,0xdb,0xd3,
+  0xa7,0xc4,0xb2,0xa3,0x56,0x4b,0x32,0xd9,0x17,0xb9,0xc3,0x3e,0x64,0xdd,0x90,0x6c,
+  0x60,0x60,0x8a,0x83,0x39,0x4e,0x89,0xd4,0x9e,0xa9,0x3e,0xb2,0x35,0x3b,0x64,0xdd,
+  0xa9,0x5f,0xb6,0x5f,0xe5,0x20,0x99,0x60,0xe0,0xb0,0xe9,0x80,0x23,0xd6,0x7d,0xc9,
+  0x84,0xac,0x4f,0xb0,0xbe,0x3d,0x64,0xdd,0x94,0x6c,0xd8,0x1f,0xd9,0x6a,0x1f,0x71,
+  0x40,0x56,0x94,0x34,0xb3,0x9f,0xe6,0x27,0x1b,0x0a,0x31,0xa9,0x3e,0xe5,0x8f,0x1d,
+  0x84,0xfd,0x09,0x06,0xe6,0xb3,0xc7,0xde,0xf1,0x50,0x94,0xff,0x47,0xd0,0x92,0x8d,
+  0x5a,0xcb,0x93,0xeb,0x25,0xfd,0x03,0x6c,0x3c,0xf4,0xb7,0x34,0x69,0xea,0xb0,0xac,
+  0x88,0x86,0x7c,0x80,0x03,0xc3,0x96,0x46,0x1b,0xeb,0xb4,0x41,0x6b,0x5e,0x32,0xbe,
+  0x9d,0x6c,0xe4,0x40,0x95,0x40,0x4b,0x76,0xd0,0xda,0x90,0x54,0xa5,0xfa,0xbd,0x66,
+  0x22,0x45,0x56,0xc3,0x3a,0x1c,0xff,0xea,0x16,0x32,0x04,0xcb,0x21,0x51,0xe0,0xe0,
+  0x4e,0x04,0x24,0xe5,0x00,0xbf,0x3d,0xbd,0x38,0x7e,0xf2,0x5a,0x9b,0x52,0x07,0x5c,
+  0xed,0xe0,0x14,0x24,0x3e,0x60,0xfa,0x87,0x01,0x69,0x3c,0xf4,0xae,0xa4,0xd6,0xb7,
+  0x71,0xfc,0xd4,0xb1,0xd1,0x85,0x1f,0x2e,0xad,0xe9,0x12,0xb0,0x04,0x90,0xeb,0x77,
+  0x5d,0x99,0xe9,0x1a,0x68,0x5a,0x8f,0xec,0x53,0x35,0xb3,0x19,0x63,0x40,0x8b,0x31,
+  0x70,0x07,0x82,0x44,0x24,0x91,0xb1,0x51,0xff,0x68,0x09,0x90,0xfa,0xa7,0x8e,0x64,
+  0x0e,0x0c,0xa4,0x12,0x1a,0x8d,0x90,0x4c,0x61,0xc0,0x48,0x44,0xd5,0x6e,0x06,0x52,
+  0x08,0xd2,0x02,0x68,0xaa,0x29,0xf5,0x0f,0x98,0x66,0x4c,0xa7,0x94,0xe0,0x0e,0x2f,
+  0x0d,0xa8,0x02,0x0d,0xa6,0x02,0x29,0x07,0x00,0x77,0x83,0x03,0xfc,0xf6,0xa4,0x15,
+  0xc5,0xb6,0xf3,0x46,0xbf,0xad,0x28,0x60,0x33,0xed,0xa5,0x31,0x90,0x6d,0x33,0x10,
+  0x00,0x2b,0x41,0x20,0xb5,0xa7,0xd7,0x9c,0x63,0x31,0x25,0x1f,0xc1,0xfe,0xb4,0x1c,
+  0x6d,0x8f,0xe0,0x30,0x65,0xa0,0xc1,0x72,0xf4,0x8f,0x34,0x5f,0xcc,0xf9,0x4c,0xed,
+  0xcc,0x8b,0x3c,0x6a,0x47,0x18,0xb8,0x91,0xa9,0x1d,0x8b,0x0e,0x51,0x06,0xe6,0x18,
+  0x30,0x04,0xf3,0x11,0x48,0x0d,0x22,0x34,0x45,0x98,0xd2,0xb0,0x6d,0x0e,0xba,0x41,
+  0x2f,0x20,0x48,0x2a,0x0c,0x28,0x06,0x61,0x0b,0x81,0x5e,0x90,0xc7,0x83,0x50,0x32,
+  0x26,0x92,0xbb,0x76,0x88,0x9a,0x91,0x41,0x38,0x04,0x4b,0xa0,0x96,0x95,0x1c,0x32,
+  0x17,0x21,0x50,0x4c,0x90,0xeb,0xab,0x6a,0xbb,0xb9,0x3a,0xd3,0x9c,0xdb,0x39,0x42,
+  0x10,0x98,0xcd,0x71,0xfa,0x2a,0x69,0xef,0xba,0x3d,0x83,0x60,0x3f,0x69,0xe9,0x5a,
+  0x9d,0x59,0xa7,0x53,0xb9,0xfe,0x42,0xf5,0xde,0xc9,0xbb,0x52,0x1b,0xc6,0xe8,0x3f,
+  0xaa,0x7f,0x3e,0x79,0xd7,0x96,0x0d,0x4f,0x26,0xfe,0x89,0x95,0x18,0x1b,0x1e,0x15,
+  0x20,0x85,0x40,0x6e,0x3f,0xe5,0x49,0x01,0xf1,0x3f,0x15,0x5b,0x69,0x04,0x39,0x58,
+  0x24,0xda,0x23,0x00,0xff,0x49,0x92,0x1e,0x2b,0x96,0xa4,0x7d,0x04,0xd7,0x2f,0xb1,
+  0x90,0xc5,0x10,0xc4,0x92,0xa3,0xdd,0x2d,0x31,0xbb,0x87,0x81,0x3e,0x04,0x72,0xfd,
+  0x8d,0x99,0xd8,0x00,0x5d,0x8f,0x8b,0x89,0x8a,0xa0,0x67,0x3d,0x49,0x98,0xbd,0x19,
+  0x18,0xa0,0x77,0x40,0xc2,0xec,0xca,0xe8,0x03,0xd1,0x04,0x96,0x48,0xd5,0xb5,0x16,
+  0x45,0x33,0x87,0x75,0x63,0x54,0x6b,0x49,0x6b,0x99,0xe1,0xb8,0xa1,0x6a,0xc4,0x05,
+  0x1b,0xd7,0xb6,0x71,0x20,0x3f,0xbe,0x0e,0x14,0x1b,0xf2,0x99,0x36,0x1c,0x78,0x8a,
+  0x6d,0xe6,0xf5,0x36,0x8a,0x60,0x4c,0x00,0x70,0x4a,0xe4,0xfa,0x51,0xa5,0x19,0x46,
+  0x0b,0x7f,0x96,0x4a,0xae,0x8e,0xac,0x83,0x43,0x85,0xf6,0x54,0x83,0x00,0x37,0x20,
+  0xa8,0x69,0x16,0x40,0x6e,0x4f,0xad,0xba,0xad,0x6b,0x28,0xe7,0xd2,0x80,0xb1,0x79,
+  0x02,0x1c,0xe1,0xc4,0xa0,0x97,0x81,0xfb,0x8c,0x7f,0x90,0xfb,0xbf,0x7e,0x65,0xfa,
+  0xe7,0xb9,0x17,0x76,0x5d,0x5b,0xcb,0xc1,0xf7,0x77,0x5d,0xbb,0xa2,0x7e,0xed,0xca,
+  0xe9,0x1d,0x2f,0x2c,0xfa,0xe7,0xda,0xfa,0xf4,0xca,0x43,0x1c,0xc8,0xed,0x59,0xf6,
+  0xe0,0xed,0x17,0xfe,0x7d,0xcf,0x99,0x77,0xcf,0x71,0xf0,0xe2,0x99,0xf7,0xcf,0x2d,
+  0xfb,0x64,0xcd,0xd1,0x6f,0x5d,0x38,0x71,0xfe,0xdc,0xb2,0x07,0xd6,0x5c,0xe0,0x00,
+  0x3e,0x83,0xdc,0xfa,0x44,0xed,0x55,0xe9,0x15,0xb9,0x1d,0x9b,0x3a,0xcf,0x35,0x7e,
+  0xb7,0xfb,0x42,0xee,0xb7,0x7f,0x7b,0xeb,0x53,0x2b,0x1e,0x7c,0x73,0x45,0xee,0xf1,
+  0xf3,0x9d,0x17,0x56,0x5c,0xfd,0xe6,0x8a,0x33,0x8f,0x9f,0x97,0xeb,0x77,0x3e,0x70,
+  0xfb,0xd1,0x6f,0xbd,0x78,0xe2,0xdd,0x73,0x9d,0x4e,0x33,0xce,0x77,0xf2,0x86,0x9d,
+  0x78,0x1f,0xeb,0xdf,0x7e,0x94,0xb5,0x30,0x50,0x7f,0xe1,0xe5,0xfd,0x47,0x77,0xdc,
+  0x74,0xe2,0xd1,0x8d,0xcb,0xd8,0x1f,0x3e,0x8b,0x7f,0x88,0xe0,0xed,0xe6,0x17,0x47,
+  0xdf,0x3d,0xb7,0x30,0xc9,0xc1,0xa9,0xbf,0x0e,0x34,0xa8,0x75,0x8b,0xf9,0xa4,0x7e,
+  0xb5,0x9e,0x2d,0x28,0x08,0xe0,0x6a,0x5a,0x3b,0x09,0x5b,0xb1,0x64,0x4e,0xbc,0x76,
+  0x9f,0x82,0x20,0x73,0x35,0x25,0x72,0x7f,0x52,0x97,0x1f,0x8e,0x5e,0xe9,0xb0,0x41,
+  0xe4,0x87,0x30,0x64,0xce,0xe7,0xc0,0xe1,0x87,0x52,0xfd,0x62,0x7e,0xe8,0x01,0x5c,
+  0x91,0x19,0x51,0xe4,0xfc,0x30,0xd0,0x20,0xa4,0x6d,0x50,0x13,0xcb,0xd9,0x02,0x30,
+  0xda,0xb6,0x91,0x01,0x8d,0x6c,0x47,0x46,0xc4,0x4a,0x02,0xe3,0x59,0xeb,0xd9,0x46,
+  0xa2,0xc3,0xdd,0x0d,0xf6,0x58,0x4f,0x07,0x59,0x30,0xba,0xdc,0x88,0x1d,0xa0,0xdb,
+  0xc8,0x02,0x1b,0xc1,0xeb,0x74,0x5b,0x96,0x83,0x42,0xf0,0xf9,0x0e,0x3f,0xb4,0x0c,
+  0x48,0xea,0xec,0xf9,0xde,0x7f,0xc4,0x80,0xc1,0x81,0x2f,0x51,0xa4,0x85,0x38,0xad,
+  0x32,0x7c,0x7e,0x21,0x2d,0xb4,0xf4,0x1c,0xbd,0x6a,0x12,0xc1,0x16,0x7d,0x9c,0x5e,
+  0x45,0x6a,0xed,0xb4,0x19,0xd8,0xa3,0x7d,0x89,0xae,0xcc,0xce,0xcb,0xf7,0x8e,0xc1,
+  0x75,0xf4,0xae,0x6c,0xd3,0x44,0xcf,0xd3,0xb1,0x56,0x58,0x95,0x6d,0xca,0x23,0xb8,
+  0x0e,0x7f,0x42,0x30,0x2e,0xe9,0x4f,0xad,0xd0,0x08,0xcd,0x10,0x2f,0xa8,0x39,0x98,
+  0x8b,0x4a,0x2b,0x8e,0xdc,0x87,0xaf,0x36,0x58,0xb2,0xd4,0x07,0xa6,0xff,0x07,0xb8,
+  0x55,0xd5,0x71,0xb5,0xa7,0x5b,0x74,0x36,0x8b,0x70,0xd9,0x37,0x51,0xa5,0xf5,0xb2,
+  0xdd,0x6d,0x86,0xc4,0xf5,0x1e,0x64,0x8b,0x74,0x0b,0xf1,0xcc,0xe7,0xf8,0x7c,0xd3,
+  0xb1,0xbc,0x25,0xf9,0x06,0x53,0x17,0x76,0x3a,0xb6,0x25,0x35,0xc7,0xf4,0x56,0xaa,
+  0x65,0x15,0x56,0x22,0xd7,0x47,0xd2,0xcb,0x95,0x24,0x53,0xf4,0x49,0x48,0x63,0x6f,
+  0xd7,0xb0,0x92,0x7b,0x10,0xec,0x12,0x3f,0x5d,0x62,0x7b,0xf5,0x75,0x62,0x2a,0x16,
+  0x8c,0xc3,0x55,0x06,0xea,0x2c,0x0e,0xa0,0x76,0x0c,0x36,0x31,0xc0,0xae,0x32,0xb1,
+  0x9c,0xf6,0x57,0x19,0xb8,0x02,0xba,0x62,0x32,0x7e,0xc8,0x49,0x91,0x2e,0xf3,0xc3,
+  0x31,0x06,0x72,0x7b,0x97,0x88,0x92,0x9c,0xbf,0x9e,0xb2,0x37,0x2f,0xe1,0x87,0x66,
+  0x11,0x30,0x0b,0x9e,0x7d,0xde,0xc4,0xb7,0x4c,0x71,0x92,0xa6,0x0f,0x3b,0x00,0x5e,
+  0xa1,0x0e,0xd8,0x2b,0x4a,0xa2,0x92,0xfe,0x37,0x7b,0x4d,0xc1,0xdf,0xd8,0xd1,0x25,
+  0x02,0x40,0xfe,0x36,0xc2,0x7a,0xc0,0x60,0x44,0x4c,0xfc,0x44,0x91,0xbf,0x79,0xed,
+  0x21,0x12,0x3f,0xf4,0x40,0xaa,0xa8,0xc4,0x7f,0x7e,0x86,0xa4,0xc5,0x43,0x18,0x7b,
+  0x14,0x20,0xc6,0x5e,0xdc,0x01,0xa2,0xa4,0xa8,0x3d,0xf8,0x21,0xf1,0x8b,0x02,0x38,
+  0x20,0x86,0xdb,0x00,0x07,0xb8,0x3f,0xa5,0xbd,0xf6,0xf4,0xe3,0xb8,0xed,0xb2,0xe3,
+  0x96,0xca,0x06,0xf0,0x56,0x5b,0xb7,0x68,0x92,0xb0,0x92,0x20,0xf0,0x87,0x4f,0x3f,
+  0xb0,0x91,0xef,0xf1,0x5b,0x6f,0xaf,0x14,0x04,0x20,0xb5,0x67,0x03,0xb2,0x41,0xe4,
+  0x87,0x83,0xda,0x06,0x25,0x66,0xff,0xcc,0xe5,0x87,0x03,0x2e,0x10,0xfc,0xd0,0x5f,
+  0xdf,0x09,0xe3,0x6f,0x0b,0xac,0xe5,0x7a,0x6c,0xbf,0x00,0xc9,0xd8,0xfe,0x9a,0xbf,
+  0x22,0x08,0x32,0xb1,0x43,0x74,0x2b,0x59,0x60,0x2e,0x1f,0xbc,0x44,0x7a,0x5f,0xd2,
+  0x87,0xb4,0xf0,0x49,0xeb,0xea,0x24,0xd9,0xaf,0x08,0x50,0xbb,0x1f,0x5c,0xe0,0x94,
+  0x48,0xfa,0x27,0xd3,0xdb,0xa7,0xb6,0x73,0xda,0x09,0x12,0xff,0xbc,0xc1,0x66,0x8c,
+  0x31,0xf1,0xf3,0x84,0xa0,0x8e,0xfa,0x5e,0x69,0xfc,0x34,0x11,0x8b,0x69,0x1b,0xc6,
+  0x87,0x0d,0x7b,0x85,0xd0,0x3f,0x9b,0x78,0x89,0xab,0x88,0xfa,0xd5,0x82,0xd7,0x43,
+  0x26,0x0e,0xe0,0x8d,0x76,0xd2,0xaa,0x19,0xd7,0xbf,0x8b,0xe0,0x52,0xab,0x26,0x49,
+  0xb6,0xab,0xbc,0x04,0x81,0xf8,0x29,0x29,0xeb,0x9f,0x5e,0x8b,0xde,0xdf,0x32,0x17,
+  0x77,0x68,0x90,0x1f,0x5d,0x4a,0x2e,0x47,0x10,0x3b,0xb6,0xe8,0x7e,0x04,0xcb,0x11,
+  0x50,0x07,0x48,0xe3,0x99,0xac,0x45,0x36,0x88,0xfd,0x8f,0xed,0xc1,0xd1,0x72,0x09,
+  0x7e,0x08,0x9c,0x1d,0x9b,0x18,0x2d,0xec,0x27,0x3b,0x04,0x51,0xec,0x97,0xf4,0x0f,
+  0x8e,0x37,0x64,0x83,0x7c,0xfc,0x7c,0x83,0xb1,0xc1,0x7c,0x5f,0x80,0x1f,0x3a,0x40,
+  0xaa,0x8f,0xf3,0xcb,0xec,0x8a,0xeb,0xbd,0x38,0x5d,0x68,0x26,0xab,0x1b,0xbd,0x1a,
+  0x72,0x29,0x13,0x41,0x0f,0x02,0x2a,0x00,0x01,0xa9,0x7f,0x70,0xbe,0x14,0xe2,0x1d,
+  0xb8,0xf3,0xa8,0xc3,0x09,0x15,0x9f,0x20,0x51,0xd2,0x0d,0x99,0x42,0x3c,0xa5,0x22,
+  0x30,0x1c,0x60,0xfa,0xcf,0x47,0x65,0xa1,0xeb,0x9c,0x1f,0xda,0x66,0x2b,0xaa,0x1d,
+  0x82,0xfc,0xd0,0x74,0x89,0xa2,0x0b,0xe4,0xf1,0x93,0x6e,0x6d,0x62,0xfc,0x50,0x1b,
+  0x57,0x5a,0x91,0x93,0x75,0xb4,0x70,0x7e,0x38,0x06,0x86,0x51,0x37,0x86,0x25,0x79,
+  0xc6,0x0f,0xc7,0xa4,0xf6,0x10,0x57,0xff,0x24,0x85,0xfe,0xe9,0x73,0xf5,0x0f,0x03,
+  0x8b,0x70,0x9c,0x2b,0x4c,0xff,0x48,0xfd,0x63,0x72,0x25,0x53,0x63,0x8e,0xe5,0x50,
+  0x7b,0x3f,0x21,0xd4,0xce,0x16,0x6d,0x9c,0xa0,0x22,0xca,0x39,0x1a,0xa9,0x4b,0x9e,
+  0x5f,0x16,0x7e,0x26,0x54,0xb5,0xd8,0x26,0x1b,0x81,0x86,0x5b,0xeb,0x63,0x70,0xaf,
+  0x86,0x5f,0x70,0x38,0x77,0x6c,0xd1,0xd2,0xda,0xb9,0x0a,0x7e,0x41,0x7f,0xbe,0x67,
+  0x80,0xc0,0x57,0xac,0xb9,0x5b,0x22,0x2c,0x8c,0x54,0xca,0x8c,0xea,0x11,0x0a,0xaf,
+  0x22,0x31,0xe3,0x60,0x9f,0x21,0x4a,0x6c,0xa9,0x3d,0xc8,0xdf,0x96,0x98,0x0d,0x99,
+  0x48,0x26,0xb7,0x13,0xda,0xcd,0x06,0x33,0x32,0x00,0x3f,0xa3,0xed,0xfd,0xd1,0x4c,
+  0x24,0x0e,0xbf,0xc0,0x12,0x06,0xf4,0xbd,0x52,0x7b,0xba,0x29,0xee,0x46,0x53,0x7d,
+  0x49,0x40,0xb5,0x33,0x99,0x4c,0xf5,0x45,0x63,0x7f,0xef,0x82,0xc7,0x5d,0x20,0xeb,
+  0x1f,0x13,0xf9,0x61,0xb2,0xe0,0x1e,0x9e,0x54,0xb2,0x23,0xfa,0xfd,0xd3,0x8f,0xfc,
+  0x50,0x43,0x7e,0x68,0xdb,0x9b,0xee,0x66,0x44,0xd1,0x88,0x8d,0x53,0x87,0x16,0x7a,
+  0x40,0x1e,0x3f,0x66,0xaf,0x1a,0x4b,0xd4,0xf4,0x22,0x5d,0xee,0xc9,0xc4,0xe2,0xb4,
+  0x97,0xc4,0x4c,0x13,0xd5,0x0e,0x15,0xfa,0x87,0x95,0x00,0x31,0xa5,0xf1,0xa3,0x31,
+  0x96,0xea,0x6a,0x3e,0x7d,0x58,0xc5,0x61,0x60,0xe0,0x30,0x18,0x16,0x1b,0x07,0x3e,
+  0x1e,0xb2,0x20,0x09,0xa3,0x85,0x90,0x37,0x83,0xfc,0x90,0x83,0x1e,0xaf,0x44,0x1e,
+  0x3f,0xb7,0x2d,0x5c,0x67,0x8e,0x4e,0x6f,0x5c,0x32,0x7e,0x5b,0xcd,0x3a,0xf3,0xd0,
+  0xb4,0xb1,0xa4,0xe1,0x36,0xb2,0xce,0x1c,0x98,0xbe,0x01,0x41,0x84,0x95,0x20,0x90,
+  0xda,0x43,0xfa,0xe9,0xb6,0xae,0x05,0x39,0x5c,0xf4,0x7f,0xf2,0xb0,0x43,0x03,0x3c,
+  0x3e,0xc0,0x01,0x2c,0x37,0x24,0xfd,0x83,0xeb,0xb5,0xcf,0x0f,0x57,0xca,0xfc,0x70,
+  0x57,0x05,0x7e,0xd8,0xe9,0xf3,0xc3,0x35,0x32,0x3f,0x3c,0xf3,0x3b,0xe2,0x87,0x57,
+  0x32,0x5a,0xf8,0xcb,0xdc,0x85,0xf3,0x9d,0xe7,0x38,0x51,0x44,0x7e,0xf8,0x44,0x6d,
+  0x90,0x1f,0x9e,0x90,0xeb,0xf3,0xff,0xfd,0xc3,0x13,0x58,0xff,0x13,0x4e,0x14,0x91,
+  0x1f,0x3e,0x50,0xc4,0x0f,0x03,0xed,0x59,0xe6,0xf2,0xc3,0x85,0x97,0xdf,0x7e,0x74,
+  0x47,0x3b,0x23,0x96,0xf7,0x17,0xd5,0x3f,0xfe,0xe9,0x5b,0x9f,0x02,0x83,0xe0,0xfc,
+  0xc6,0x7f,0xbb,0xa3,0x9f,0xfe,0x29,0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0x4a,
+  0x28,0xa1,0x84,0x12,0xca,0xef,0xbb,0xf0,0xbd,0x03,0x0d,0xf7,0x0e,0xa1,0x84,0x12,
+  0x4a,0x28,0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0x4a,0x75,0xe1,0x7b,0x87,0x9a,
+  0x70,0xef,0x10,0x4a,0x28,0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0x4a,0x28,0xa1,
+  0x54,0x17,0xbe,0x77,0xd0,0xf8,0xde,0xe1,0xff,0xba,0x29,0xa1,0x84,0x12,0x4a,0x28,
+  0xa1,0x84,0x12,0x4a,0x28,0xa1,0x84,0x12,0xca,0x17,0x28,0x29,0x16,0x72,0x19,0x5e,
+  0xf9,0x20,0x05,0x36,0xf3,0x62,0x8a,0xa4,0xc0,0xbc,0xe8,0xf3,0x04,0xe7,0x6f,0xd5,
+  0x14,0xe4,0x89,0xff,0xcc,0xe3,0x77,0x15,0xd7,0xfb,0x5f,0x2b,0x92,0xad,0x46,0xf1,
+  0x33,0x01,0x00,
diff --git a/u-boot/board/dave/PPChameleonEVB/nand.c b/u-boot/board/dave/PPChameleonEVB/nand.c
new file mode 100644
index 0000000..14b61a4
--- /dev/null
+++ b/u-boot/board/dave/PPChameleonEVB/nand.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			MACRO_NAND_CTL_SETCLE((unsigned long)base);
+		else
+			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+		if ( ctrl & NAND_ALE )
+			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+		else
+			MACRO_NAND_CTL_CLRALE((unsigned long)base);
+		if ( ctrl & NAND_NCE )
+			MACRO_NAND_ENABLE_CE((unsigned long)base);
+		else
+			MACRO_NAND_DISABLE_CE((unsigned long)base);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * read device ready pin
+ * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong rb_gpio_pin;
+
+	/* use the base addr to find out which chip are we dealing with */
+	switch((ulong) this->IO_ADDR_W) {
+	case CONFIG_SYS_NAND0_BASE:
+		rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
+		break;
+	case CONFIG_SYS_NAND1_BASE:
+		rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
+		break;
+	default: /* this should never happen */
+		return 0;
+		break;
+	}
+
+	if (in32(GPIO0_IR) & rb_gpio_pin)
+		return 1;
+	return 0;
+}
+
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+
+	nand->cmd_ctrl = ppchameleonevb_hwcontrol;
+	nand->dev_ready = ppchameleonevb_device_ready;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->chip_delay = NAND_BIG_DELAY_US;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
+}
+#endif
diff --git a/u-boot/board/dave/PPChameleonEVB/u-boot.lds b/u-boot/board/dave/PPChameleonEVB/u-boot.lds
new file mode 100644
index 0000000..17f5919
--- /dev/null
+++ b/u-boot/board/dave/PPChameleonEVB/u-boot.lds
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "config.h"	/* CONFIG_BOARDDIR */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
+  . = 0xFFFF8000;
+  .ppcenv :
+  {
+    common/env_embedded.o(.ppcenv);
+  }
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/dave/common/flash.c b/u-boot/board/dave/common/flash.c
new file mode 100644
index 0000000..29caf47
--- /dev/null
+++ b/u-boot/board/dave/common/flash.c
@@ -0,0 +1,707 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("ST  ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_STMW320DT:	printf ("M29W320DT (32 M, top sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CONFIG_SYS_FLASH_READ0];
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;  break;	/* => 8 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n=0; n<2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
+		    l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+#ifdef CONFIG_B2
+			data = data | ((*(uchar *)cp)<<(8*i));
+#else
+			data = (data << 8) | (*(uchar *)cp);
+#endif
+		}
+		for (; i<4 && cnt>0; ++i) {
+#ifdef CONFIG_B2
+			data = data  | ((*src++)<<(8*i));
+#else
+			data = (data << 8) | *src++;
+#endif
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+			data = data | ((*(uchar *)cp)<<(8*i));
+#else
+			data = (data << 8) | (*(uchar *)cp);
+#endif
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+#ifdef CONFIG_B2
+		data = (*(ulong*)src);
+		src += 4;
+#else
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+#endif
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+#ifdef CONFIG_B2
+		data = data  | ((*src++)<<(8*i));
+#else
+		data = (data << 8) | *src++;
+#endif
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+		data = data | ((*(uchar *)cp)<<(8*i));
+#else
+		data = (data << 8) | (*(uchar *)cp);
+#endif
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile ulong *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/dave/common/fpga.c b/u-boot/board/dave/common/fpga.c
new file mode 100644
index 0000000..30bc196
--- /dev/null
+++ b/u-boot/board/dave/common/fpga.c
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2001-2003
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES               226
+
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG              CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000  /* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000  /* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000  /* FPGA init pin (ppc input)     */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+
+#define SET_FPGA(data)         out32(GPIO0_OR, data)
+
+#define FPGA_WRITE_1 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#if 0
+static int fpga_boot (unsigned char *fpgadata, int size)
+{
+	int i, index, len;
+	int count;
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	int j;
+#else
+	unsigned char b;
+	int bit;
+#endif
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	DBG ("FPGA: configdata starts at position 0x%x\n", index);
+	DBG ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	out32 (GPIO0_ODR, 0x00000000);	/* no open drain pins */
+	out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* setup for output */
+	out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* set pins to high */
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (in32 (GPIO0_IR) & FPGA_INIT) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	DBG ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+		for (j = 0; j < 8; j++) {
+			if ((fpgadata[i] & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			fpgadata[i] <<= 1;
+		}
+	}
+#else	/* ! CONFIG_SYS_FPGA_SPARTAN2 */
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif	/* CONFIG_SYS_FPGA_SPARTAN2 */
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG ("FPGA: Booting successful!\n");
+	return 0;
+}
+#endif	/* 0 */
diff --git a/u-boot/board/dave/common/pci.c b/u-boot/board/dave/common/pci.c
new file mode 100644
index 0000000..3036799
--- /dev/null
+++ b/u-boot/board/dave/common/pci.c
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
+
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_read_config_dword
+|  Description: Read a PCI configuration register
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               value           Address of the configuration register value
+|  Return value:
+|               0               Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+  unsigned long      conAdrVal;
+  unsigned long      val;
+
+  /* generate coded value for CON_ADR register */
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  /* Note: *pResult comes back as -1 if machine check happened */
+  val = in32r(PCI_PRIMARY_CDR);
+
+  *value = (unsigned long) val;
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  if ((*(unsigned long *)0x50000304) & 0x60000000)
+    {
+      /* clear pci master/target abort bits */
+      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_write_config_dword
+|  Description: Write a PCI configuration register.
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               Value           Configuration register value
+|  Return value:
+|               0               Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 value)
+{
+  unsigned long      conAdrVal;
+
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  out32r(PCI_PRIMARY_CDR, value);
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  /* clear pci master/target abort bits */
+  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+					struct pci_config_table *_)
+{
+  unsigned int iobase;
+  unsigned short status = 0;
+  unsigned char timer;
+
+  /*
+   * Configure PLX PCI9054
+   */
+  pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+  pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+  /* Check the latency timer for values >= 0x60.
+   */
+  pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  if (timer < 0x60)
+    {
+      pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+    }
+
+  /* Set I/O base register.
+   */
+  pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+  pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+  pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  if (pci9054_iobase == 0xffffffff)
+    {
+      printf("Error: Can not set I/O base register.\n");
+      return;
+    }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+				 CONFIG_SYS_ETH_IOBASE,
+				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
+    pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+  { }
+};
+
+static struct pci_controller pci9054_hose = {
+  config_table: pci9054_config_table,
+};
+
+void pci_init(void)
+{
+  struct pci_controller *hose = &pci9054_hose;
+
+  /*
+   * Register the hose
+   */
+  hose->first_busno = 0;
+  hose->last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(hose->regions + 0,
+		 0x00000000, 0x00000000, 0x01000000,
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+  /* PCI Memory space */
+  pci_set_region(hose->regions + 1,
+		 0x00000000, 0xc0000000, 0x10000000,
+		 PCI_REGION_MEM);
+
+  pci_set_ops(hose,
+	      pci_hose_read_config_byte_via_dword,
+	      pci_hose_read_config_word_via_dword,
+	      pci9054_read_config_dword,
+	      pci_hose_write_config_byte_via_dword,
+	      pci_hose_write_config_word_via_dword,
+	      pci9054_write_config_dword);
+
+  hose->region_count = 2;
+
+  pci_register_hose(hose);
+
+  hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/u-boot/board/davedenx/aria/Makefile b/u-boot/board/davedenx/aria/Makefile
new file mode 100644
index 0000000..30dba23
--- /dev/null
+++ b/u-boot/board/davedenx/aria/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davedenx/aria/aria.c b/u-boot/board/davedenx/aria/aria.c
new file mode 100644
index 0000000..31b079b
--- /dev/null
+++ b/u-boot/board/davedenx/aria/aria.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	/*
+	 * Initialize Local Window for the On Board FPGA access
+	 */
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
+		CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+	sync_law(&im->sysconf.lpcs2aw);
+
+	/*
+	 * Initialize Local Window for the On Board SRAM access
+	 */
+	out_be32(&im->sysconf.lpcs6aw,
+		CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
+		CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
+	sync_law(&im->sysconf.lpcs6aw);
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+
+	if (SVR_MJREV(spridr) >= 2)
+		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return fixed_sdram(NULL, NULL, 0);
+}
+
+int misc_init_r(void)
+{
+	u32 tmp;
+
+	/* we use I2C-2 for on-board eeprom */
+	i2c_set_bus_num(2);
+
+	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
+	printf("FPGA:  %u-%u.%u.%u\n",
+		(tmp & 0xFF000000) >> 24,
+		(tmp & 0x00FF0000) >> 16,
+		(tmp & 0x0000FF00) >>  8,
+		 tmp & 0x000000FF
+	);
+
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/*
+	 * FEC
+	 */
+
+	/* FEC on PSCx_x*/
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+
+	/*
+	 * DIU
+	 */
+	/* FUNC2=DIU CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/*
+	 * On board SRAM
+	 */
+	/* FUNC2=/LPC CS6 */
+	{
+		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+};
+
+int checkboard (void)
+{
+	puts("Board: ARIA\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/davedenx/qong/Makefile b/u-boot/board/davedenx/qong/Makefile
new file mode 100644
index 0000000..1dca60d
--- /dev/null
+++ b/u-boot/board/davedenx/qong/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2009
+# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= qong.o fpga.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davedenx/qong/config.mk b/u-boot/board/davedenx/qong/config.mk
new file mode 100644
index 0000000..ea1c1b0
--- /dev/null
+++ b/u-boot/board/davedenx/qong/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE = 0xa0000000
+
+# PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/u-boot/board/davedenx/qong/fpga.c b/u-boot/board/davedenx/qong/fpga.c
new file mode 100644
index 0000000..656d5cd
--- /dev/null
+++ b/u-boot/board/davedenx/qong/fpga.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <mxc_gpio.h>
+#include <fpga.h>
+#include <lattice.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+static void qong_jtag_init(void)
+{
+	return;
+}
+
+static void qong_fpga_jtag_set_tdi(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tms(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tck(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
+}
+
+static int qong_fpga_jtag_get_tdo(void)
+{
+	return mxc_gpio_get(QONG_FPGA_TDO_PIN);
+}
+
+lattice_board_specific_func qong_fpga_fns = {
+	qong_jtag_init,
+	qong_fpga_jtag_set_tdi,
+	qong_fpga_jtag_set_tms,
+	qong_fpga_jtag_set_tck,
+	qong_fpga_jtag_get_tdo
+};
+
+Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
+	{
+		Lattice_XP2,
+		lattice_jtag_mode,
+		356519,
+		(void *) &qong_fpga_fns,
+		NULL,
+		0,
+		"lfxp2_5e_ftbga256"
+	},
+};
+
+int qong_fpga_init(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		fpga_add(fpga_lattice, &qong_fpga[i]);
+	}
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/davedenx/qong/lowlevel_init.S b/u-boot/board/davedenx/qong/lowlevel_init.S
new file mode 100644
index 0000000..80bed92
--- /dev/null
+++ b/u-boot/board/davedenx/qong/lowlevel_init.S
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * Based on board/freescale/mx31ads/lowlevel_init.S
+ * by Guennadi Liakhovetski.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.macro SETUP_RAM cfg, ctl
+	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+	REG	0xB8001010, 0x00000004
+	ldr r3, =\cfg
+	ldr r2, =WEIM_ESDCFG0
+	str r3, [r2]
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	ldr r3, =\ctl
+	ldr r2, =WEIM_ESDCTL0
+	str r3, [r2]
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+.endm
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	init_drive_strength
+
+	/* Image Processing Unit: */
+	/* Too early to switch display on? */
+	/* Switch on Display Interface */
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5		/* Use CKIH, MCU PLL off */
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE			/* MCU PLL on */
+	/* Switch to MCU PLL */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	/* 399-133-66.5 */
+	ldr	r0, =CCM_BASE
+	ldr	r1, =0xFF871650
+	/* PDR0 */
+	str	r1, [r0, #0x4]
+	ldr	r1, MPCTL_PARAM_399
+	/* MPCTL */
+	str	r1, [r0, #0x10]
+
+	/* Set UPLL=240MHz, USB=60MHz */
+	ldr	r1, =0x49FCFE7F
+	/* PDR1 */
+	str	r1, [r0, #0x8]
+	ldr	r1, UPCTL_PARAM_240
+	/* UPCTL */
+	str	r1, [r0, #0x14]
+	/* default CLKO to 1/8 of the ARM core */
+	mov	r1, #0x00000208
+	/* COSR */
+	str	r1, [r0, #0x1c]
+
+	/* Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+check_ddr_module:
+/* Set stackpointer in internal RAM to call get_ram_size */
+	ldr	sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
+	stmfd	sp!, {r0-r11, ip, lr}
+	mov	ip, lr		/* save link reg across call */
+
+	ldr	r0,=0x08000000
+	SETUP_RAM	ESDCFG0_256MB, ESDCTL0_256MB
+	ldr	r0,=0x80000000
+	ldr	r1,=0x10000000
+	bl	get_ram_size
+	ldr	r1,=0x10000000
+	cmp	r0,r1
+	beq	restore_regs
+	SETUP_RAM	ESDCFG0_128MB, ESDCTL0_128MB
+	ldr	r0,=0x80000000
+	ldr	r1,=0x08000000
+	bl	get_ram_size
+	ldr	r1,=0x08000000
+	cmp	r0,r1
+	beq	restore_regs
+
+restore_regs:
+	ldmfd	sp!, {r0-r11, ip, lr}
+	mov	lr, ip		/* restore link reg */
+
+	mov	pc, lr
+
+
+MPCTL_PARAM_399:
+	.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
+UPCTL_PARAM_240:
+	.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3  << 0))
+
+	.equ	ESDCFG0_128MB, \
+		(0 << 21) + /* tXP */ \
+		(1 << 20) + /* tWTR */ \
+		(2 << 18) + /* tRP */ \
+		(1 << 16) + /* tMRD */ \
+		(0 << 15) + /* tWR */ \
+		(5 << 12) + /* tRAS */ \
+		(1 << 10) + /* tRRD */ \
+		(3 << 8) + /* tCAS */ \
+		(2 << 4) + /* tRCD */ \
+		(0x0F << 0) /* tRC */
+
+	.equ	ESDCTL0_128MB, \
+		(1 << 31)  +	/* enable */ \
+		(0 << 28)  +	/* mode */ \
+		(0 << 27)  +	/* supervisor protect */ \
+		(2 << 24)  +	/* 13 rows */ \
+		(2 << 20)  +	/* 10 cols */ \
+		(2 << 16)  +	/* 32 bit */ \
+		(3 << 13)  +	/* 7.81us (64ms/8192) */ \
+		(0 << 10)  +	/* power down timer */ \
+		(0 << 8)  +	/* full page */ \
+		(1 << 7)  +	/* burst length */ \
+		(0 << 0)	/* precharge timer */
+
+	.equ	ESDCFG0_256MB, \
+		(3 << 21)  + 	/* tXP */ \
+		(0 << 20)  + 	/* tWTR */ \
+		(2 << 18)  + 	/* tRP */ \
+		(1 << 16)  + 	/* tMRD */ \
+		(0 << 15)  + 	/* tWR */ \
+		(5 << 12)  + 	/* tRAS */ \
+		(1 << 10)  + 	/* tRRD */ \
+		(3 << 8)   + 	/* tCAS */ \
+		(2 << 4)   +	/* tRCD */ \
+		(7 << 0)	/* tRC */
+
+	.equ	ESDCTL0_256MB, \
+		(1 << 31)  + \
+		(0 << 28)  + \
+		(0 << 27)  + \
+		(3 << 24)  + /* 14 rows */ \
+		(2 << 20)  + /* 10 cols */ \
+		(2 << 16)  + \
+		(4 << 13)  + /* 3.91us (64ms/16384) */ \
+		(0 << 10)  + \
+		(0 << 8)   + \
+		(1 << 7)   + \
+		(0 << 0)
diff --git a/u-boot/board/davedenx/qong/qong.c b/u-boot/board/davedenx/qong/qong.c
new file mode 100644
index 0000000..8a81cfc
--- /dev/null
+++ b/u-boot/board/davedenx/qong/qong.c
@@ -0,0 +1,287 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <fsl_pmic.h>
+#include <mxc_gpio.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void qong_fpga_reset(void)
+{
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+	udelay(30);
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
+
+	udelay(300);
+}
+
+int board_early_init_f (void)
+{
+#ifdef CONFIG_QONG_FPGA
+	/* CS1: FPGA/Network Controller/GPIO */
+	/* 16-bit, no DTACK */
+	__REG(CSCR_U(1)) = 0x00000A01;
+	__REG(CSCR_L(1)) = 0x20040501;
+	__REG(CSCR_A(1)) = 0x04020C00;
+
+	/* setup pins for FPGA */
+	mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+
+	/* FPGA reset  Pin */
+	/* rstn = 0 */
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+	mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
+
+	/* set interrupt pin as input */
+	mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
+
+	/* FPGA JTAG Interface */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
+	mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
+#endif
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* setup pins for SPI (pmic) */
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+
+	/* Setup pins for USB2 Host */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+	mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+	mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+	mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
+	mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
+	mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
+	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
+	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
+	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
+
+	writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
+	return 0;
+
+}
+
+int board_init (void)
+{
+	/* Chip selects */
+	/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
+	/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
+	__REG(CSCR_U(0)) = ((0 << 31)	| /* SP */
+						(0 << 30)	| /* WP */
+						(0 << 28)	| /* BCD */
+						(0 << 24)	| /* BCS */
+						(0 << 22)	| /* PSZ */
+						(0 << 21)	| /* PME */
+						(0 << 20)	| /* SYNC */
+						(0 << 16)	| /* DOL */
+						(3 << 14)	| /* CNC */
+						(21 << 8)	| /* WSC */
+						(0 << 7)	| /* EW */
+						(0 << 4)	| /* WWS */
+						(6 << 0)	  /* EDC */
+					   );
+
+	__REG(CSCR_L(0)) = ((2 << 28)	| /* OEA */
+						(1 << 24)	| /* OEN */
+						(3 << 20)	| /* EBWA */
+						(3 << 16)	| /* EBWN */
+						(1 << 12)	| /* CSA */
+						(1 << 11)	| /* EBC */
+						(5 << 8)	| /* DSZ */
+						(1 << 4)	| /* CSN */
+						(0 << 3)	| /* PSR */
+						(0 << 2)	| /* CRE */
+						(0 << 1)	| /* WRAP */
+						(1 << 0)	  /* CSEN */
+					   );
+
+	__REG(CSCR_A(0)) = ((2 << 28)	| /* EBRA */
+						(1 << 24)	| /* EBRN */
+						(2 << 20)	| /* RWA */
+						(2 << 16)	| /* RWN */
+						(0 << 15)	| /* MUM */
+						(0 << 13)	| /* LAH */
+						(2 << 10)	| /* LBN */
+						(0 << 8)	| /* LBA */
+						(0 << 6)	| /* DWW */
+						(0 << 4)	| /* DCT */
+						(0 << 3)	| /* WWU */
+						(0 << 2)	| /* AGE */
+						(0 << 1)	| /* CNC2 */
+						(0 << 0)	  /* FCE */
+					   );
+
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_QONG;
+	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
+
+	qong_fpga_init();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u32 val;
+
+	/* Enable RTC battery */
+	val = pmic_reg_read(REG_POWER_CTL0);
+	pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
+	pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf("Board: DAVE/DENX Qong\n");
+	return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_QONG_FPGA
+	u32 tmp;
+
+	tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
+	printf("FPGA:  ");
+	printf("version register = %u.%u.%u\n",
+		(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
+	return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
+#else
+	return 0;
+#endif
+}
+
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
+static void board_nand_setup(void)
+{
+
+	/* CS3: NAND 8-bit */
+	__REG(CSCR_U(3)) = 0x00004f00;
+	__REG(CSCR_L(3)) = 0x20013b31;
+	__REG(CSCR_A(3)) = 0x00020800;
+	__REG(IOMUXC_GPR) |= 1 << 13;
+
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
+
+	/* Make sure to reset the fpga else you cannot access NAND */
+	qong_fpga_reset();
+
+	/* Enable NAND flash */
+	mxc_gpio_set(15, 1);
+	mxc_gpio_set(14, 1);
+	mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_set(15, 0);
+
+}
+
+int qong_nand_rdy(void *chip)
+{
+	udelay(1);
+	return mxc_gpio_get(16);
+}
+
+void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	if (chip >= 0)
+		mxc_gpio_set(15, 0);
+	else
+		mxc_gpio_set(15, 1);
+
+}
+
+void qong_nand_plat_init(void *chip)
+{
+	struct nand_chip *nand = (struct nand_chip *)chip;
+	nand->chip_delay = 20;
+	nand->select_chip = qong_nand_select_chip;
+	nand->options &= ~NAND_BUSWIDTH_16;
+	board_nand_setup();
+}
+
+#endif
diff --git a/u-boot/board/davedenx/qong/qong_fpga.h b/u-boot/board/davedenx/qong/qong_fpga.h
new file mode 100644
index 0000000..4e79ac2
--- /dev/null
+++ b/u-boot/board/davedenx/qong/qong_fpga.h
@@ -0,0 +1,39 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef QONG_FPGA_H
+#define QONG_FPGA_H
+
+#define QONG_FPGA_CTRL_BASE		CONFIG_FPGA_BASE
+#define QONG_FPGA_CTRL_VERSION		(QONG_FPGA_CTRL_BASE + 0x00000000)
+#define QONG_FPGA_PERIPH_SIZE		(1 << 24)
+
+#define	QONG_FPGA_TCK_PIN		26
+#define	QONG_FPGA_TMS_PIN		25
+#define	QONG_FPGA_TDI_PIN		8
+#define	QONG_FPGA_TDO_PIN		7
+#define	QONG_FPGA_RST_PIN		48
+#define	QONG_FPGA_IRQ_PIN		40
+
+int qong_fpga_init(void);
+#endif /* QONG_FPGA_H */
diff --git a/u-boot/board/davinci/common/Makefile b/u-boot/board/davinci/common/Makefile
new file mode 100644
index 0000000..a1d3de2
--- /dev/null
+++ b/u-boot/board/davinci/common/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS	:= misc.o davinci_pinmux.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/common/davinci_pinmux.c b/u-boot/board/davinci/common/davinci_pinmux.c
new file mode 100644
index 0000000..ce58f71
--- /dev/null
+++ b/u-boot/board/davinci/common/davinci_pinmux.c
@@ -0,0 +1,105 @@
+/*
+ * DaVinci pinmux functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ *	{ &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ *	{ &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+			      const int n_pins)
+{
+	int i;
+
+	/* check for invalid pinmux values */
+	for (i = 0; i < n_pins; i++) {
+		if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+		    (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+			return -1;
+	}
+
+	/* configure the pinmuxes */
+	for (i = 0; i < n_pins; i++) {
+		const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+		const unsigned int value = pins[i].value << offset;
+		const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+		const dv_reg *mux = pins[i].mux;
+
+		writel(value | (readl(mux) & (~mask)), mux);
+	}
+
+	return 0;
+}
+
+/*
+ * Configure multiple pinmux resources.
+ *
+ * Takes an pinmux_resource array of pinmux_config and pin counts:
+ *
+ * const struct pinmux_resource pinmuxes[] = {
+ *	PINMUX_ITEM(uart_pins),
+ *	PINMUX_ITEM(i2c_pins),
+ * };
+ *
+ * The number of items in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Each item entry is configured in the defined order. If configuration
+ * of any item fails, -1 is returned and none of the following items are
+ * configured. On success, 0 is returned.
+ */
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+				    const int n_items)
+{
+	int i;
+
+	for (i = 0; i < n_items; i++) {
+		if (davinci_configure_pin_mux(item[i].pins,
+					      item[i].n_pins) != 0)
+			return -1;
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/davinci/common/misc.c b/u-boot/board/davinci/common/misc.c
new file mode 100644
index 0000000..2bfdf23
--- /dev/null
+++ b/u-boot/board/davinci/common/misc.c
@@ -0,0 +1,149 @@
+/*
+ * Miscelaneous DaVinci functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_PRELOADER
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(volatile void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+/* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
+ * Returns 1 if found, 0 otherwise.
+ */
+int dvevm_read_mac_address(uint8_t *buf)
+{
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+	/* Read MAC address. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+		     (uint8_t *) &buf[0], 6))
+		goto i2cerr;
+
+	/* Check that MAC address is valid. */
+	if (!is_valid_ether_addr(buf))
+		goto err;
+
+	return 1; /* Found */
+
+i2cerr:
+	printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
+err:
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
+
+	return 0;
+}
+
+/*
+ * Set the mii mode as MII or RMII
+ */
+#if defined(CONFIG_SOC_DA8XX)
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+	int val;
+
+	val = readl(&davinci_syscfg_regs->cfgchip3);
+	if (mode_sel == 0)
+		val &= ~(1 << 8);
+	else
+		val |= (1 << 8);
+	writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+#endif
+/*
+ * If there is no MAC address in the environment, then it will be initialized
+ * (silently) from the value in the EEPROM.
+ */
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
+{
+	uint8_t env_enetaddr[6];
+
+	eth_getenv_enetaddr_by_index(0, env_enetaddr);
+	if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
+		/* There is no MAC address in the environment, so we initialize
+		 * it from the value in the EEPROM. */
+		debug("### Setting environment from EEPROM MAC address = "
+			"\"%pM\"\n",
+			env_enetaddr);
+		eth_setenv_enetaddr("ethaddr", rom_enetaddr);
+	}
+}
+
+#endif	/* CONFIG_DRIVER_TI_EMAC */
+
+#if defined(CONFIG_SOC_DA8XX)
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+	/*
+	 * Mask all IRQs by clearing the global enable and setting
+	 * the enable clear for all the 90 interrupts.
+	 */
+
+	writel(0, &davinci_aintc_regs->ger);
+
+	writel(0, &davinci_aintc_regs->hier);
+
+	writel(0xffffffff, &davinci_aintc_regs->ecr1);
+	writel(0xffffffff, &davinci_aintc_regs->ecr2);
+	writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+/*
+ * Enable PSC for various peripherals.
+ */
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+				    const int n_items)
+{
+	int i;
+
+	for (i = 0; i < n_items; i++)
+		lpsc_on(item[i].lpsc_no);
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/davinci/da8xxevm/Makefile b/u-boot/board/davinci/da8xxevm/Makefile
new file mode 100644
index 0000000..c1b2119
--- /dev/null
+++ b/u-boot/board/davinci/da8xxevm/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= da830evm.o
+COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= da850evm.o
+COBJS-$(CONFIG_MACH_DAVINCI_HAWK)	+= hawkboard.o
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/da8xxevm/da830evm.c b/u-boot/board/davinci/da8xxevm/da830evm.c
new file mode 100644
index 0000000..0650653
--- /dev/null
+++ b/u-boot/board/davinci/da8xxevm/da830evm.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ *
+ * Base on code from TI. Original Notices follow:
+ *
+ * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
+ *
+ * Modified for DA8xx EVM.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi0_pins[] = {
+	{ pinmux(7), 1, 3 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(7), 1, 6 },
+	{ pinmux(7), 1, 7 }
+};
+
+/* EMIF-A bus pins for 8-bit NAND support on CS3 */
+static const struct pinmux_config emifa_nand_pins[] = {
+	{ pinmux(13), 1, 6 },
+	{ pinmux(13), 1, 7 },
+	{ pinmux(14), 1, 0 },
+	{ pinmux(14), 1, 1 },
+	{ pinmux(14), 1, 2 },
+	{ pinmux(14), 1, 3 },
+	{ pinmux(14), 1, 4 },
+	{ pinmux(14), 1, 5 },
+	{ pinmux(15), 1, 7 },
+	{ pinmux(16), 1, 0 },
+	{ pinmux(18), 1, 1 },
+	{ pinmux(18), 1, 4 },
+	{ pinmux(18), 1, 5 },
+};
+
+/* EMAC PHY interface pins */
+static const struct pinmux_config emac_pins[] = {
+	{ pinmux(9), 0, 5 },
+	{ pinmux(10), 2, 1 },
+	{ pinmux(10), 2, 2 },
+	{ pinmux(10), 2, 3 },
+	{ pinmux(10), 2, 4 },
+	{ pinmux(10), 2, 5 },
+	{ pinmux(10), 2, 6 },
+	{ pinmux(10), 2, 7 },
+	{ pinmux(11), 2, 0 },
+	{ pinmux(11), 2, 1 },
+};
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+	{ pinmux(8), 2, 7 },
+	{ pinmux(9), 2, 0 }
+};
+
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+	{ pinmux(8), 2, 3 },
+	{ pinmux(8), 2, 4 }
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+static const struct pinmux_config usb_pins[] = {
+	{ pinmux(9), 1, 1 }
+};
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+	PINMUX_ITEM(spi0_pins),
+#endif
+	PINMUX_ITEM(uart_pins),
+	PINMUX_ITEM(i2c_pins),
+#ifdef CONFIG_USB_DA8XX
+	PINMUX_ITEM(usb_pins),
+#endif
+#ifdef CONFIG_USE_NAND
+	PINMUX_ITEM(emifa_nand_pins),
+#endif
+#if defined(CONFIG_DRIVER_TI_EMAC)
+	PINMUX_ITEM(emac_pins),
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI0 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	irq_init();
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+	/* EMIFA 100MHz clock select */
+	writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
+	       &davinci_syscfg_regs->cfgchip3);
+	/* NAND CS setup */
+	writel((DAVINCI_ABCR_WSETUP(0) |
+		DAVINCI_ABCR_WSTROBE(2) |
+		DAVINCI_ABCR_WHOLD(0) |
+		DAVINCI_ABCR_RSETUP(0) |
+		DAVINCI_ABCR_RSTROBE(2) |
+		DAVINCI_ABCR_RHOLD(0) |
+		DAVINCI_ABCR_TA(2) |
+		DAVINCI_ABCR_ASIZE_8BIT),
+	       &davinci_emif_regs->ab2cr);
+#endif
+
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+	return(0);
+}
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+#define PHY_SW_I2C_ADDR	0x5f /* Address of PHY on i2c bus */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+	u_int8_t mac_addr[6];
+	u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
+	struct eth_device *dev;
+
+	/* Read Ethernet MAC address from EEPROM */
+	if (dvevm_read_mac_address(mac_addr))
+		/* set address env if not already set */
+		davinci_sync_env_enetaddr(mac_addr);
+
+	/* read the address back from env */
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr))
+		return -1;
+
+	/* enable the Ethernet switch in the 3 port PHY */
+	if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
+			switch_start_cmd, sizeof(switch_start_cmd))) {
+		printf("Ethernet switch start failed!\n");
+		return -1;
+	}
+
+	/* finally, initialise the driver */
+	if (!davinci_emac_initialize()) {
+		printf("Error: Ethernet init failed!\n");
+		return -1;
+	}
+
+	dev = eth_get_dev();
+
+	/* provide the resulting addr to the driver */
+	memcpy(dev->enetaddr, mac_addr, 6);
+	dev->write_hwaddr(dev);
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/u-boot/board/davinci/da8xxevm/da850evm.c b/u-boot/board/davinci/da8xxevm/da850evm.c
new file mode 100644
index 0000000..b088c9c
--- /dev/null
+++ b/u-boot/board/davinci/da8xxevm/da850evm.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi1_pins[] = {
+	{ pinmux(5), 1, 1 },
+	{ pinmux(5), 1, 2 },
+	{ pinmux(5), 1, 4 },
+	{ pinmux(5), 1, 5 }
+};
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+	{ pinmux(0), 4, 6 },
+	{ pinmux(0), 4, 7 },
+	{ pinmux(4), 2, 4 },
+	{ pinmux(4), 2, 5 }
+};
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+static const struct pinmux_config emac_pins[] = {
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+	{ pinmux(14), 8, 2 },
+	{ pinmux(14), 8, 3 },
+	{ pinmux(14), 8, 4 },
+	{ pinmux(14), 8, 5 },
+	{ pinmux(14), 8, 6 },
+	{ pinmux(14), 8, 7 },
+	{ pinmux(15), 8, 1 },
+#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
+	{ pinmux(2), 8, 1 },
+	{ pinmux(2), 8, 2 },
+	{ pinmux(2), 8, 3 },
+	{ pinmux(2), 8, 4 },
+	{ pinmux(2), 8, 5 },
+	{ pinmux(2), 8, 6 },
+	{ pinmux(2), 8, 7 },
+	{ pinmux(3), 8, 0 },
+	{ pinmux(3), 8, 1 },
+	{ pinmux(3), 8, 2 },
+	{ pinmux(3), 8, 3 },
+	{ pinmux(3), 8, 4 },
+	{ pinmux(3), 8, 5 },
+	{ pinmux(3), 8, 6 },
+	{ pinmux(3), 8, 7 },
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+	{ pinmux(4), 8, 0 },
+	{ pinmux(4), 8, 1 }
+};
+
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+	{ pinmux(4), 2, 2 },
+	{ pinmux(4), 2, 3 }
+};
+
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+	{ pinmux(7), 1, 1 },
+	{ pinmux(7), 1, 2 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(9), 1, 0 },
+	{ pinmux(9), 1, 1 },
+	{ pinmux(9), 1, 2 },
+	{ pinmux(9), 1, 3 },
+	{ pinmux(9), 1, 4 },
+	{ pinmux(9), 1, 5 },
+	{ pinmux(9), 1, 6 },
+	{ pinmux(9), 1, 7 },
+	{ pinmux(12), 1, 5 },
+	{ pinmux(12), 1, 6 }
+};
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+	PINMUX_ITEM(spi1_pins),
+#endif
+	PINMUX_ITEM(uart_pins),
+	PINMUX_ITEM(i2c_pins),
+#ifdef CONFIG_NAND_DAVINCI
+	PINMUX_ITEM(nand_pins),
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
+#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
+#endif
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
+ *		0000b - 300 MHz
+ *		0001b - 372 MHz
+ *		0010b - 408 MHz
+ *		0011b - 456 MHz
+ */
+u32 get_board_rev(void)
+{
+	char *s;
+	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+	u32 rev = 0;
+
+	s = getenv("maxcpuclk");
+	if (s)
+		maxcpuclk = simple_strtoul(s, NULL, 10);
+
+	if (maxcpuclk >= 456000000)
+		rev = 3;
+	else if (maxcpuclk >= 408000000)
+		rev = 2;
+	else if (maxcpuclk >= 372000000)
+		rev = 1;
+
+	return rev;
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	irq_init();
+#endif
+
+
+#ifdef CONFIG_NAND_DAVINCI
+	/*
+	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
+	 * Linux kernel @ 25MHz EMIFA
+	 */
+	writel((DAVINCI_ABCR_WSETUP(0) |
+		DAVINCI_ABCR_WSTROBE(0) |
+		DAVINCI_ABCR_WHOLD(0) |
+		DAVINCI_ABCR_RSETUP(0) |
+		DAVINCI_ABCR_RSTROBE(1) |
+		DAVINCI_ABCR_RHOLD(0) |
+		DAVINCI_ABCR_TA(0) |
+		DAVINCI_ABCR_ASIZE_8BIT),
+	       &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+		return 1;
+
+	davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+/**
+ * rmii_hw_init
+ *
+ * DA850/OMAP-L138 EVM can interface to a daughter card for
+ * additional features. This card has an I2C GPIO Expander TCA6416
+ * to select the required functions like camera, RMII Ethernet,
+ * character LCD, video.
+ *
+ * Initialization of the expander involves configuring the
+ * polarity and direction of the ports. P07-P05 are used here.
+ * These ports are connected to a Mux chip which enables only one
+ * functionality at a time.
+ *
+ * For RMII phy to respond, the MII MDIO clock has to be  disabled
+ * since both the PHY devices have address as zero. The MII MDIO
+ * clock is controlled via GPIO2[6].
+ *
+ * This code is valid for Beta version of the hardware
+ */
+int rmii_hw_init(void)
+{
+	const struct pinmux_config gpio_pins[] = {
+		{ pinmux(6), 8, 1 }
+	};
+	u_int8_t buf[2];
+	unsigned int temp;
+	int ret;
+
+	/* PinMux for GPIO */
+	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+		return 1;
+
+	/* I2C Exapnder configuration */
+	/* Set polarity to non-inverted */
+	buf[0] = 0x0;
+	buf[1] = 0x0;
+	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+	if (ret) {
+		printf("\nExpander @ 0x%02x write FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+		return ret;
+	}
+
+	/* Configure P07-P05 as outputs */
+	buf[0] = 0x1f;
+	buf[1] = 0xff;
+	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+	if (ret) {
+		printf("\nExpander @ 0x%02x write FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+	}
+
+	/* For Ethernet RMII selection
+	 * P07(SelA)=0
+	 * P06(SelB)=1
+	 * P05(SelC)=1
+	 */
+	if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+		printf("\nExpander @ 0x%02x read FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+	}
+
+	buf[0] &= 0x1f;
+	buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
+	if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+		printf("\nExpander @ 0x%02x write FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+	}
+
+	/* Set the output as high */
+	temp = REG(GPIO_BANK2_REG_SET_ADDR);
+	temp |= (0x01 << 6);
+	REG(GPIO_BANK2_REG_SET_ADDR) = temp;
+
+	/* Set the GPIO direction as output */
+	temp = REG(GPIO_BANK2_REG_DIR_ADDR);
+	temp &= ~(0x01 << 6);
+	REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+	/* Select RMII fucntion through the expander */
+	if (rmii_hw_init())
+		printf("RMII hardware init failed!!!\n");
+#endif
+	if (!davinci_emac_initialize()) {
+		printf("Error: Ethernet init failed!\n");
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/u-boot/board/davinci/da8xxevm/hawkboard.c b/u-boot/board/davinci/da8xxevm/hawkboard.c
new file mode 100644
index 0000000..f34830e
--- /dev/null
+++ b/u-boot/board/davinci/da8xxevm/hawkboard.c
@@ -0,0 +1,68 @@
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc.  <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * Kick Registers need to be set to allow access to Pin Mux registers
+	 */
+	writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+	writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+	/* set cfgchip3 to select mii */
+	writel(readl(&davinci_syscfg_regs->cfgchip3) &
+	       ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char buf[32];
+
+	printf("ARM Clock : %s MHz\n",
+	       strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
+
+	return 0;
+}
diff --git a/u-boot/board/davinci/da8xxevm/hawkboard_nand_spl.c b/u-boot/board/davinci/da8xxevm/hawkboard_nand_spl.c
new file mode 100644
index 0000000..9155236
--- /dev/null
+++ b/u-boot/board/davinci/da8xxevm/hawkboard_nand_spl.c
@@ -0,0 +1,157 @@
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc.  <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x)			(&davinci_syscfg_regs->pinmux[x])
+
+static const struct pinmux_config mii_pins[] = {
+	{ pinmux(2), 8, 1 },
+	{ pinmux(2), 8, 2 },
+	{ pinmux(2), 8, 3 },
+	{ pinmux(2), 8, 4 },
+	{ pinmux(2), 8, 5 },
+	{ pinmux(2), 8, 6 },
+	{ pinmux(2), 8, 7 }
+};
+
+static const struct pinmux_config mdio_pins[] = {
+	{ pinmux(4), 8, 0 },
+	{ pinmux(4), 8, 1 }
+};
+
+static const struct pinmux_config nand_pins[] = {
+	{ pinmux(7), 1, 1 },
+	{ pinmux(7), 1, 2 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(9), 1, 0 },
+	{ pinmux(9), 1, 1 },
+	{ pinmux(9), 1, 2 },
+	{ pinmux(9), 1, 3 },
+	{ pinmux(9), 1, 4 },
+	{ pinmux(9), 1, 5 },
+	{ pinmux(9), 1, 6 },
+	{ pinmux(9), 1, 7 },
+	{ pinmux(12), 1, 5 },
+	{ pinmux(12), 1, 6 }
+};
+
+static const struct pinmux_config uart2_pins[] = {
+	{ pinmux(0), 4, 6 },
+	{ pinmux(0), 4, 7 },
+	{ pinmux(4), 2, 4 },
+	{ pinmux(4), 2, 5 }
+};
+
+static const struct pinmux_config i2c_pins[] = {
+	{ pinmux(4), 2, 4 },
+	{ pinmux(4), 2, 5 }
+};
+
+static const struct pinmux_resource pinmuxes[] = {
+	PINMUX_ITEM(mii_pins),
+	PINMUX_ITEM(mdio_pins),
+	PINMUX_ITEM(i2c_pins),
+	PINMUX_ITEM(nand_pins),
+	PINMUX_ITEM(uart2_pins),
+};
+
+static const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
+void board_init_f(ulong bootflag)
+{
+	/*
+	 * Kick Registers need to be set to allow access to Pin Mux registers
+	 */
+	writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+	writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc);
+
+	/* Power on required peripherals
+	 * ARM does not have acess by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc));
+
+	/* configure pinmux settings */
+	davinci_configure_pin_mux_items(pinmuxes,
+					ARRAY_SIZE(pinmuxes));
+
+	writel(readl(&davinci_uart2_ctrl_regs->pwremu_mgmt) |
+	       (DAVINCI_UART_PWREMU_MGMT_FREE) |
+	       (DAVINCI_UART_PWREMU_MGMT_URRST) |
+	       (DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+	NS16550_init((NS16550_t)(DAVINCI_UART2_BASE),
+			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+	puts("Nand boot...\n");
+
+	nand_boot();
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), '\r');
+
+	NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), c);
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/u-boot/board/davinci/dm355evm/Makefile b/u-boot/board/davinci/dm355evm/Makefile
new file mode 100644
index 0000000..4804597
--- /dev/null
+++ b/u-boot/board/davinci/dm355evm/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/dm355evm/config.mk b/u-boot/board/davinci/dm355evm/config.mk
new file mode 100644
index 0000000..9a06300
--- /dev/null
+++ b/u-boot/board/davinci/dm355evm/config.mk
@@ -0,0 +1,11 @@
+#
+# Spectrum Digital DM355 EVM board
+#	dm355evm board has 1 bank of 128 MB DDR RAM
+#	Physical Address: 8000'0000 to 8800'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/dm355evm/dm355evm.c b/u-boot/board/davinci/dm355evm/dm355evm.c
new file mode 100644
index 0000000..112851a
--- /dev/null
+++ b/u-boot/board/davinci/dm355evm/dm355evm.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/davinci_misc.h>
+#include <net.h>
+#include <netdev.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * With the DM355 EVM, u-boot is *always* a third stage loader,
+ * unless a JTAG debugger handles the first two stages:
+ *
+ *   - 1st stage is ROM Boot Loader (RBL), which searches for a
+ *     second stage loader in one of three places based on SW7:
+ *     NAND (with MMC/SD fallback), MMC/SD, or UART.
+ *
+ *   - 2nd stage is User Boot Loader (UBL), using at most 30KB
+ *     of on-chip SRAM, responsible for lowlevel init, and for
+ *     loading the third stage loader into DRAM.
+ *
+ *   - 3rd stage, that's us!
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	/* We expect the UBL to have handled "lowlevel init", which
+	 * involves setting up at least:
+	 *  - clocks
+	 *      + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
+	 *      + clock divisors for those PLLs
+	 *      + LPSC_DDR module enabled
+	 *      + LPSC_TIMER0 module (still) enabled
+	 *  - EMIF
+	 *      + DDR init and timings
+	 *      + AEMIF timings (for NAND and DM9000)
+	 *  - pinmux
+	 *
+	 * Some of that is repeated here, mostly as a precaution.
+	 */
+
+	/* AEMIF:  Some "address" lines are available as GPIOs.  A3..A13
+	 * could be too if we used A12 as a GPIO during NAND chipselect
+	 * (and Linux did too), letting us control the LED on A7/GPIO61.
+	 */
+	REG(PINMUX2) = 0x0c08;
+
+	/* UART0 may still be in SyncReset if we didn't boot from UART */
+	davinci_enable_uart0();
+
+	/* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
+	lpsc_on(DAVINCI_LPSC_TPCC);
+	lpsc_on(DAVINCI_LPSC_TPTC0);
+	lpsc_on(DAVINCI_LPSC_TPTC1);
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+
+static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip	*this = mtd->priv;
+	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
+	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
+
+	if (chip == 1) {
+		__set_bit(14, &wbase);
+		__set_bit(14, &rbase);
+	} else {
+		__clear_bit(14, &wbase);
+		__clear_bit(14, &rbase);
+	}
+	this->IO_ADDR_W = (void *)wbase;
+	this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+	nand->select_chip = nand_dm355evm_select_chip;
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.input_clk	= 108000000,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version	= MMC_CTLR_VERSION_1,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+	.input_clk	= 108000000,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version	= MMC_CTLR_VERSION_1,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+	int err;
+
+	/* Add slot-0 to mmc subsystem */
+	err = davinci_mmc_init(bis, &mmc_sd0);
+	if (err)
+		return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+	/* Add slot-1 to mmc subsystem */
+	err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+	return err;
+}
+#endif
diff --git a/u-boot/board/davinci/dm355leopard/Makefile b/u-boot/board/davinci/dm355leopard/Makefile
new file mode 100644
index 0000000..4804597
--- /dev/null
+++ b/u-boot/board/davinci/dm355leopard/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/dm355leopard/config.mk b/u-boot/board/davinci/dm355leopard/config.mk
new file mode 100644
index 0000000..28ff3f3
--- /dev/null
+++ b/u-boot/board/davinci/dm355leopard/config.mk
@@ -0,0 +1,6 @@
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/dm355leopard/dm355leopard.c b/u-boot/board/davinci/dm355leopard/dm355leopard.c
new file mode 100644
index 0000000..0ee0d11
--- /dev/null
+++ b/u-boot/board/davinci/dm355leopard/dm355leopard.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_defs.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/davinci_misc.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	struct davinci_gpio *gpio01_base =
+			(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
+	struct davinci_gpio *gpio23_base =
+			(struct davinci_gpio *)DAVINCI_GPIO_BANK23;
+	struct davinci_gpio *gpio67_base =
+			(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
+
+	gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	/* GIO 9 & 10 are used for IO */
+	writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
+
+	/* Interrupt set GIO 9 */
+	writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
+
+	/* set GIO 9 input */
+	writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
+
+	/* Both edge trigger GIO 9 */
+	writel((readl(&gpio01_base->set_rising) | (1 << 9)),
+						&gpio01_base->set_rising);
+	writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
+
+	/* output low */
+	writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
+						&gpio01_base->set_data);
+
+	/* set GIO 10 output */
+	writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
+
+	/* output high */
+	writel((readl(&gpio01_base->set_data) | (1 << 10)),
+						&gpio01_base->set_data);
+
+	/* set GIO 32 output */
+	writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
+
+	/* output High */
+	writel((readl(&gpio23_base->set_data) | (1 << 0)),
+						&gpio23_base->set_data);
+
+	/* Enable UART1 MUX Lines */
+	writel((readl(PINMUX0) & ~3), PINMUX0);
+	writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
+	writel((readl(&gpio67_base->set_data) | (1 << 6)),
+						&gpio67_base->set_data);
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/davinci/dm365evm/Makefile b/u-boot/board/davinci/dm365evm/Makefile
new file mode 100644
index 0000000..4804597
--- /dev/null
+++ b/u-boot/board/davinci/dm365evm/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/dm365evm/config.mk b/u-boot/board/davinci/dm365evm/config.mk
new file mode 100644
index 0000000..7b1e900
--- /dev/null
+++ b/u-boot/board/davinci/dm365evm/config.mk
@@ -0,0 +1,11 @@
+#
+# Spectrum Digital DM365 EVM board
+#	DM365 EVM board has 1 bank of 128 MB DDR RAM
+#	Physical Address: 8000'0000 to 8800'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/dm365evm/dm365evm.c b/u-boot/board/davinci/dm365evm/dm365evm.c
new file mode 100644
index 0000000..5fb7611
--- /dev/null
+++ b/u-boot/board/davinci/dm365evm/dm365evm.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/gpio_defs.h>
+#include <netdev.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+int board_eth_init(bd_t *bis)
+{
+	uint8_t eeprom_enetaddr[6];
+	int i;
+	struct davinci_gpio *gpio1_base =
+			(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
+
+	/* Configure PINMUX 3 to enable EMAC pins */
+	writel((readl(PINMUX3) | 0x1affff), PINMUX3);
+
+	/* Configure GPIO20 as output */
+	writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
+
+	/* Toggle GPIO 20 */
+	for (i = 0; i < 20; i++) {
+		/* GPIO 20 low */
+		writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
+						&gpio1_base->out_data);
+
+		udelay(1000);
+
+		/* GPIO 20 high */
+		writel((readl(&gpio1_base->out_data) | (1 << 20)),
+						&gpio1_base->out_data);
+	}
+
+	/* Configure I2C pins so that EEPROM can be read */
+	writel((readl(PINMUX3) | 0x01400000), PINMUX3);
+
+	/* Read Ethernet MAC address from EEPROM */
+	if (dvevm_read_mac_address(eeprom_enetaddr))
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+	davinci_emac_initialize();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip	*this = mtd->priv;
+	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
+	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
+
+	if (chip == 1) {
+		__set_bit(14, &wbase);
+		__set_bit(14, &rbase);
+	} else {
+		__clear_bit(14, &wbase);
+		__clear_bit(14, &rbase);
+	}
+	this->IO_ADDR_W = (void *)wbase;
+	this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+	nand->select_chip = nand_dm365evm_select_chip;
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.input_clk	= 121500000,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version	= MMC_CTLR_VERSION_2,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+	.input_clk	= 121500000,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version	= MMC_CTLR_VERSION_2,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+	int err;
+
+	/* Add slot-0 to mmc subsystem */
+	err = davinci_mmc_init(bis, &mmc_sd0);
+	if (err)
+		return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+#define PUPDCTL1		0x01c4007c
+	/* PINMUX(4)-DAT0-3/CMD;  PINMUX(0)-CLK */
+	writel((readl(PINMUX4) | 0x55400000), PINMUX4);
+	writel((readl(PINMUX0) | 0x00010000), PINMUX0);
+
+	/* Configure MMC/SD pins as pullup */
+	writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
+
+	/* Add slot-1 to mmc subsystem */
+	err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+	return err;
+}
+#endif
diff --git a/u-boot/board/davinci/dm6467evm/Makefile b/u-boot/board/davinci/dm6467evm/Makefile
new file mode 100644
index 0000000..4804597
--- /dev/null
+++ b/u-boot/board/davinci/dm6467evm/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/dm6467evm/config.mk b/u-boot/board/davinci/dm6467evm/config.mk
new file mode 100644
index 0000000..3751043
--- /dev/null
+++ b/u-boot/board/davinci/dm6467evm/config.mk
@@ -0,0 +1,2 @@
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/dm6467evm/dm6467evm.c b/u-boot/board/davinci/dm6467evm/dm6467evm.c
new file mode 100644
index 0000000..1a01c3c
--- /dev/null
+++ b/u-boot/board/davinci/dm6467evm/dm6467evm.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/nand_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
+	lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+	lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+	lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0x80000c0;
+
+	/* Select UART function on UART0 */
+	REG(PINMUX0) &= ~(0x0000003f << 18);
+	REG(PINMUX1) &= ~(0x00000003);
+
+	return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+int board_eth_init(bd_t *bis)
+{
+	if (!davinci_emac_initialize()) {
+		printf("Error: Ethernet init failed!\n");
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/davinci/dvevm/Makefile b/u-boot/board/davinci/dvevm/Makefile
new file mode 100644
index 0000000..72fd963
--- /dev/null
+++ b/u-boot/board/davinci/dvevm/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/dvevm/board_init.S b/u-boot/board/davinci/dvevm/board_init.S
new file mode 100644
index 0000000..81b23d0
--- /dev/null
+++ b/u-boot/board/davinci/dvevm/board_init.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+
+	mov	pc, lr
diff --git a/u-boot/board/davinci/dvevm/config.mk b/u-boot/board/davinci/dvevm/config.mk
new file mode 100644
index 0000000..ed80707
--- /dev/null
+++ b/u-boot/board/davinci/dvevm/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/dvevm/dvevm.c b/u-boot/board/davinci/dvevm/dvevm.c
new file mode 100644
index 0000000..d5c851b
--- /dev/null
+++ b/u-boot/board/davinci/dvevm/dvevm.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Configure AEMIF pins (although this should be configured at boot time
+	 * with pull-up/pull-down resistors) */
+	REG(PINMUX0) = 0x00000c1f;
+
+	davinci_errata_workarounds();
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_GPIO);
+	lpsc_on(DAVINCI_LPSC_USB);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+	/* Powerup the DSP */
+	dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+	davinci_enable_uart0();
+	davinci_enable_emac();
+	davinci_enable_i2c();
+
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r(void)
+{
+	uint8_t video_mode;
+	uint8_t eeprom_enetaddr[6];
+
+	/* Read Ethernet MAC address from EEPROM if available. */
+	if (dvevm_read_mac_address(eeprom_enetaddr))
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+	i2c_read(0x39, 0x00, 1, &video_mode, 1);
+
+	setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
+
+	return(0);
+}
+
+#ifdef CONFIG_USB_DAVINCI
+
+/* IO Expander I2C address and USB VBUS enable mask */
+#define IOEXP_I2C_ADDR 0x3A
+#define IOEXP_VBUSEN_MASK 1
+
+/*
+ * This function enables USB VBUS by writting to IO expander using I2C.
+ * Note that the I2C is already initialized at this stage. This
+ * function is used by davinci specific USB wrapper code.
+ */
+void enable_vbus(void)
+{
+	uchar data;  /* IO Expander data to enable VBUS */
+
+	/* Write to IO expander to enable VBUS */
+	i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
+	data &= ~IOEXP_VBUSEN_MASK;
+	i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
+}
+#endif
diff --git a/u-boot/board/davinci/ea20/Makefile b/u-boot/board/davinci/ea20/Makefile
new file mode 100644
index 0000000..ddd2564
--- /dev/null
+++ b/u-boot/board/davinci/ea20/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= ea20.o
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/ea20/ea20.c b/u-boot/board/davinci/ea20/ea20.c
new file mode 100644
index 0000000..9d0f71b
--- /dev/null
+++ b/u-boot/board/davinci/ea20/ea20.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Based on da850evm.c, original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi1_pins[] = {
+	{ pinmux(5), 1, 1 },
+	{ pinmux(5), 1, 2 },
+	{ pinmux(5), 1, 4 },
+	{ pinmux(5), 1, 5 }
+};
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+	{ pinmux(0), 4, 6 },
+	{ pinmux(0), 4, 7 },
+	{ pinmux(4), 2, 4 },
+	{ pinmux(4), 2, 5 }
+};
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define HAS_RMII 1
+static const struct pinmux_config emac_pins[] = {
+	{ pinmux(14), 8, 2 },
+	{ pinmux(14), 8, 3 },
+	{ pinmux(14), 8, 4 },
+	{ pinmux(14), 8, 5 },
+	{ pinmux(14), 8, 6 },
+	{ pinmux(14), 8, 7 },
+	{ pinmux(15), 8, 1 },
+	{ pinmux(4), 8, 0 },
+	{ pinmux(4), 8, 1 }
+};
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+	{ pinmux(7), 1, 1 },
+	{ pinmux(7), 1, 2 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(9), 1, 0 },
+	{ pinmux(9), 1, 1 },
+	{ pinmux(9), 1, 2 },
+	{ pinmux(9), 1, 3 },
+	{ pinmux(9), 1, 4 },
+	{ pinmux(9), 1, 5 },
+	{ pinmux(9), 1, 6 },
+	{ pinmux(9), 1, 7 },
+	{ pinmux(12), 1, 5 },
+	{ pinmux(12), 1, 6 }
+};
+#endif
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+	PINMUX_ITEM(spi1_pins),
+#endif
+	PINMUX_ITEM(uart_pins),
+#ifdef CONFIG_NAND_DAVINCI
+	PINMUX_ITEM(nand_pins),
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	irq_init();
+#endif
+
+
+#ifdef CONFIG_NAND_DAVINCI
+	/*
+	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
+	 * Linux kernel @ 25MHz EMIFA
+	 */
+	writel((DAVINCI_ABCR_WSETUP(0) |
+		DAVINCI_ABCR_WSTROBE(0) |
+		DAVINCI_ABCR_WHOLD(0) |
+		DAVINCI_ABCR_RSETUP(0) |
+		DAVINCI_ABCR_RSTROBE(1) |
+		DAVINCI_ABCR_RHOLD(0) |
+		DAVINCI_ABCR_TA(0) |
+		DAVINCI_ABCR_ASIZE_8BIT),
+	       &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+		return 1;
+
+	davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+	if (!davinci_emac_initialize()) {
+		printf("Error: Ethernet init failed!\n");
+		return -1;
+	}
+
+	/*
+	 * This board has a RMII PHY. However, the MDC line on the SOM
+	 * must not be disabled (there is no MII PHY on the
+	 * baseboard) via the GPIO2[6], because this pin
+	 * disables at the same time the SPI flash.
+	 */
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/u-boot/board/davinci/schmoogie/Makefile b/u-boot/board/davinci/schmoogie/Makefile
new file mode 100644
index 0000000..72fd963
--- /dev/null
+++ b/u-boot/board/davinci/schmoogie/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/schmoogie/board_init.S b/u-boot/board/davinci/schmoogie/board_init.S
new file mode 100644
index 0000000..81b23d0
--- /dev/null
+++ b/u-boot/board/davinci/schmoogie/board_init.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+
+	mov	pc, lr
diff --git a/u-boot/board/davinci/schmoogie/config.mk b/u-boot/board/davinci/schmoogie/config.mk
new file mode 100644
index 0000000..ed80707
--- /dev/null
+++ b/u-boot/board/davinci/schmoogie/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/schmoogie/schmoogie.c b/u-boot/board/davinci/schmoogie/schmoogie.c
new file mode 100644
index 0000000..8b615a9
--- /dev/null
+++ b/u-boot/board/davinci/schmoogie/schmoogie.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Configure AEMIF pins (although this should be configured at boot time
+	 * with pull-up/pull-down resistors) */
+	REG(PINMUX0) = 0x00000c1f;
+
+	davinci_errata_workarounds();
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+	/* Powerup the DSP */
+	dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+	davinci_enable_uart0();
+	davinci_enable_emac();
+	davinci_enable_i2c();
+
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r(void)
+{
+	u_int8_t	tmp[20], buf[10];
+	int		i = 0;
+
+	/* Set serial number from UID chip */
+	const u_int8_t	crc_tbl[256] = {
+			0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
+			0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
+			0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
+			0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
+			0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
+			0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
+			0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
+			0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
+			0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
+			0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
+			0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
+			0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
+			0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
+			0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
+			0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
+			0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
+			0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
+			0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
+			0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
+			0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
+			0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
+			0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
+			0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
+			0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
+			0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
+			0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
+			0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
+			0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
+			0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
+			0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
+			0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
+			0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
+		};
+
+	/* Set serial number from UID chip */
+	if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
+		printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
+		setenv("serial#", "FAILED");
+	} else {
+		if (buf[0] != 0x70) {
+			/* Device Family Code */
+			printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
+			setenv("serial#", "FAILED");
+		}
+	}
+	/* Now check CRC */
+	tmp[0] = 0;
+	for (i = 0; i < 8; i++)
+		tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
+
+	if (tmp[0] != 0) {
+		printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
+		setenv("serial#", "FAILED");
+	} else {
+		/* CRC OK, set "serial" env variable */
+		sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
+			buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
+		setenv("serial#", (char *)&tmp[0]);
+	}
+
+	return(0);
+}
diff --git a/u-boot/board/davinci/sffsdr/Makefile b/u-boot/board/davinci/sffsdr/Makefile
new file mode 100644
index 0000000..72fd963
--- /dev/null
+++ b/u-boot/board/davinci/sffsdr/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/sffsdr/board_init.S b/u-boot/board/davinci/sffsdr/board_init.S
new file mode 100644
index 0000000..81b23d0
--- /dev/null
+++ b/u-boot/board/davinci/sffsdr/board_init.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+
+	mov	pc, lr
diff --git a/u-boot/board/davinci/sffsdr/config.mk b/u-boot/board/davinci/sffsdr/config.mk
new file mode 100644
index 0000000..4fe9007
--- /dev/null
+++ b/u-boot/board/davinci/sffsdr/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+#
+# Lyrtech SFF SDR board (ARM926EJS) cpu
+#
+# SFF SDR board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 87FF'FFFF
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
+# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
+#
+# we load ourself to 8400'0000 to provide at least 32MB spacing
+# between us and the Integrity kernel image
+CONFIG_SYS_TEXT_BASE = 0x84000000
diff --git a/u-boot/board/davinci/sffsdr/sffsdr.c b/u-boot/board/davinci/sffsdr/sffsdr.c
new file mode 100644
index 0000000..cc3ff7d
--- /dev/null
+++ b/u-boot/board/davinci/sffsdr/sffsdr.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+#define DAVINCI_A3CR     (0x01E00014)	/* EMIF-A CS3 config register. */
+#define DAVINCI_A3CR_VAL (0x3FFFFFFD)	/* EMIF-A CS3 value for FPGA. */
+
+#define INTEGRITY_SYSCFG_OFFSET    0x7E8
+#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
+#define INTEGRITY_CHECKWORD_VALUE  0x10ADBEEF
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	davinci_errata_workarounds();
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+	/* Powerup the DSP */
+	dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+	davinci_enable_uart0();
+	davinci_enable_emac();
+	davinci_enable_i2c();
+
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	timer_init();
+
+	return(0);
+}
+
+/* Read ethernet MAC address from Integrity data structure inside EEPROM.
+ * Returns 1 if found, 0 otherwise.
+ */
+static int sffsdr_read_mac_address(uint8_t *buf)
+{
+	u_int32_t value, mac[2], address;
+
+	/* Read Integrity data structure checkword. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+		goto err;
+	if (value != INTEGRITY_CHECKWORD_VALUE)
+		return 0;
+
+	/* Read SYSCFG structure offset. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+		goto err;
+	address = 0x800 + (int) value; /* Address of SYSCFG structure. */
+
+	/* Read NET CONFIG structure offset. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+		goto err;
+	address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
+	address += 12; /* Address of NET INTERFACE CONFIG structure. */
+
+	/* Read NET INTERFACE CONFIG 2 structure offset. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+		goto err;
+	address = 0x800 + 16 + (int) value;	/* Address of NET INTERFACE
+						 * CONFIG 2 structure. */
+
+	/* Read MAC address. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
+		goto err;
+
+	buf[0] = mac[0] >> 24;
+	buf[1] = mac[0] >> 16;
+	buf[2] = mac[0] >> 8;
+	buf[3] = mac[0];
+	buf[4] = mac[1] >> 24;
+	buf[5] = mac[1] >> 16;
+
+	return 1; /* Found */
+
+err:
+	printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
+	return 0;
+}
+
+/* Platform dependent initialisation. */
+int misc_init_r(void)
+{
+	uint8_t i2cbuf;
+	uint8_t eeprom_enetaddr[6];
+
+	/* EMIF-A CS3 configuration for FPGA. */
+	REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
+
+	/* Configure I2C switch (PCA9543) to enable channel 0. */
+	i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
+	if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
+		      CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
+		printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
+		return 1;
+	}
+
+	/* Read Ethernet MAC address from EEPROM if available. */
+	if (sffsdr_read_mac_address(eeprom_enetaddr))
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+	return(0);
+}
diff --git a/u-boot/board/davinci/sonata/Makefile b/u-boot/board/davinci/sonata/Makefile
new file mode 100644
index 0000000..72fd963
--- /dev/null
+++ b/u-boot/board/davinci/sonata/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davinci/sonata/board_init.S b/u-boot/board/davinci/sonata/board_init.S
new file mode 100644
index 0000000..3e4c7a2
--- /dev/null
+++ b/u-boot/board/davinci/sonata/board_init.S
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
+ * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
+ * Visioneering if they reinvented the wheel once again to make sure :)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+#ifdef SONATA_BOARD_GPIOWP
+	/* Set PINMUX0 to enable GPIO4 */
+	ldr	r0, _PINMUX0
+	ldr	r1, GPIO4_EN_MASK
+	ldr	r2, [r0]
+	and	r2, r2, r1
+	str	r2, [r0]
+
+	/* Enable GPIO LPSC module */
+	ldr	r0, PTSTAT
+
+gpio_ptstat_loop1:
+	ldr	r2, [r0]
+	tst	r2, $0x00000001
+	bne	gpio_ptstat_loop1
+
+	ldr	r1, MDCTL_GPIO
+	ldr	r2, [r1]
+	and	r2, r2, $0xfffffff8
+	orr	r2, r2, $0x00000003
+	str	r2, [r1]
+
+	orr	r2, r2, $0x00000200
+	str	r2, [r1]
+
+	ldr	r1, PTCMD
+	mov	r2, $0x00000001
+	str	r2, [r1]
+
+gpio_ptstat_loop2:
+	ldr	r2, [r0]
+	tst	r2, $0x00000001
+	bne	gpio_ptstat_loop2
+
+	ldr	r0, MDSTAT_GPIO
+gpio_mdstat_loop:
+	ldr	r2, [r0]
+	and	r2, r2, $0x0000001f
+	teq	r2, $0x00000003
+	bne	gpio_mdstat_loop
+
+	/* GPIO4 -> output */
+	ldr	r0, GPIO_DIR01
+	mov	r1, $0x10
+	ldr	r2, [r0]
+	bic	r2, r2, r0
+	str	r2, [r0]
+
+	/* Set it to 0 (Write Protect) */
+	ldr	r0, GPIO_CLR_DATA01
+	str	r1, [r0]
+#endif
+
+	mov	pc, lr
+
+#ifdef SONATA_BOARD_GPIOWP
+.ltorg
+
+GPIO4_EN_MASK:
+	.word	0xf77fffff
+MDCTL_GPIO:
+	.word	0x01c41a68
+MDSTAT_GPIO:
+	.word	0x01c41868
+GPIO_DIR01:
+	.word	0x01c67010
+GPIO_CLR_DATA01:
+	.word	0x01c6701c
+#endif
diff --git a/u-boot/board/davinci/sonata/config.mk b/u-boot/board/davinci/sonata/config.mk
new file mode 100644
index 0000000..ed80707
--- /dev/null
+++ b/u-boot/board/davinci/sonata/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/u-boot/board/davinci/sonata/sonata.c b/u-boot/board/davinci/sonata/sonata.c
new file mode 100644
index 0000000..c194290
--- /dev/null
+++ b/u-boot/board/davinci/sonata/sonata.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_SONATA;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Configure AEMIF pins (although this should be configured at boot time
+	 * with pull-up/pull-down resistors) */
+	REG(PINMUX0) = 0x00000c1f;
+
+	davinci_errata_workarounds();
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+	/* Powerup the DSP */
+	dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+	davinci_enable_uart0();
+	davinci_enable_emac();
+	davinci_enable_i2c();
+
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r(void)
+{
+	uint8_t eeprom_enetaddr[6];
+
+	/* Read Ethernet MAC address from EEPROM if available. */
+	if (dvevm_read_mac_address(eeprom_enetaddr))
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+	return(0);
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+
+/* Set WP on deselect, write enable on select */
+static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
+{
+#define GPIO_SET_DATA01	0x01c67018
+#define GPIO_CLR_DATA01	0x01c6701c
+#define GPIO_NAND_WP	(1 << 4)
+#ifdef SONATA_BOARD_GPIOWP
+	if (chip < 0) {
+		REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
+	} else {
+		REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
+	}
+#endif
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+	nand->select_chip = nand_sonata_select_chip;
+	return 0;
+}
+
+#endif /* CONFIG_NAND_DAVINCI */
diff --git a/u-boot/board/dbau1x00/Makefile b/u-boot/board/dbau1x00/Makefile
new file mode 100644
index 0000000..e36a9d2
--- /dev/null
+++ b/u-boot/board/dbau1x00/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/dbau1x00/README b/u-boot/board/dbau1x00/README
new file mode 100644
index 0000000..b1e9494
--- /dev/null
+++ b/u-boot/board/dbau1x00/README
@@ -0,0 +1,63 @@
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+########     NOTE!!!!!!   #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/u-boot/board/dbau1x00/config.mk b/u-boot/board/dbau1x00/config.mk
new file mode 100644
index 0000000..3516b42
--- /dev/null
+++ b/u-boot/board/dbau1x00/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
+#
+
+# ROM version
+CONFIG_SYS_TEXT_BASE = 0xbfc00000
+
+# RAM version
+#CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/u-boot/board/dbau1x00/dbau1x00.c b/u-boot/board/dbau1x00/dbau1x00.c
new file mode 100644
index 0000000..b3c6d51
--- /dev/null
+++ b/u-boot/board/dbau1x00/dbau1x00.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+
+phys_size_t initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return MEM_SIZE*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN		0x0010
+#define BCSR_PCMCIA_PC0RST		0x0080
+
+/* In arch/mips/cpu/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+#ifdef CONFIG_IDE_PCMCIA
+	u16 status;
+	volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
+#endif	/* CONFIG_IDE_PCMCIA */
+	volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
+	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+	u32 proc_id;
+
+	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+	proc_id = read_c0_prid();
+
+	switch (proc_id >> 24) {
+	case 0:
+		puts ("Board: Merlot (DbAu1000)\n");
+		printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 1:
+		puts ("Board: DbAu1500\n");
+		printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 2:
+		puts ("Board: DbAu1100\n");
+		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 3:
+		puts ("Board: DbAu1550\n");
+		printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	default:
+		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+	}
+
+	set_io_port_base(0);
+
+#ifdef CONFIG_IDE_PCMCIA
+	/* Enable 3.3 V on slot 0 ( VCC )
+	   No 5V */
+	status = 4;
+	*pcmcia_bcsr = status;
+
+	status |= BCSR_PCMCIA_PC0DRVEN;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(300*1000);
+
+	status |= BCSR_PCMCIA_PC0RST;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(100*1000);
+
+	/* PCMCIA is on a 36 bit physical address.
+	   We need to map it into a 32 bit addresses */
+
+#if 0
+	/* We dont need theese unless we run whole pcmcia package */
+	write_one_tlb(20,                 /* index */
+		      0x01ffe000,         /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
+		      0x3C000017,         /* Lo0 */
+		      0x3C200017);        /* Lo1 */
+
+	write_one_tlb(21,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
+		      0x3D000017,           /* Lo0 */
+		      0x3D200017);          /* Lo1 */
+#endif	/* 0 */
+	write_one_tlb(22,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
+		      0x3E000017,           /* Lo0 */
+		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */
+
+	/* Release reset of ethernet PHY chips */
+	/* Always do this, because linux does not know about it */
+	*phy = 3;
+
+	return 0;
+}
diff --git a/u-boot/board/dbau1x00/lowlevel_init.S b/u-boot/board/dbau1x00/lowlevel_init.S
new file mode 100644
index 0000000..842fb76
--- /dev/null
+++ b/u-boot/board/dbau1x00/lowlevel_init.S
@@ -0,0 +1,589 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR		0xB1900000
+#define sys_endian		0x0038
+#define CP0_Config0		$16
+#define CPU_SCALE		((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/*
+	 * Step 1) Establish CPU endian mode.
+	 * Db1500-specific:
+	 * Switch S1.1 Off(bit7 reads 1) is Little Endian
+	 * Switch S1.1 On (bit7 reads 0) is Big Endian
+	 */
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000080
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#endif
+
+	li	t0, DB1XX0_BCSR_ADDR
+	lw	t1,8(t0)
+	andi	t1,t1,0x80
+	beq	zero,t1,big_endian
+	nop
+little_endian:
+
+	/* Change Au1 core to little endian */
+	li	t0, AU1500_SYS_ADDR
+	li	t1, 1
+	sw	t1, sys_endian(t0)
+	mfc0	t2, CP0_CONFIG
+	mtc0	t2, CP0_CONFIG
+	nop
+	nop
+
+	/* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+#ifdef CONFIG_DBAU1550
+	/* No workaround if running from ram */
+	lui	t0, 0xffc0
+	lui	t3, 0xbfc0
+	and	t1, ra, t0
+	bne	t1, t3, noCacheJump
+	nop
+
+	/*** From AMD YAMON ***/
+	/*
+	 * Step 8) Initialize the caches
+	 */
+	li		t0, (16*1024)
+	li		t1, 32
+	li		t2, 0x80000000
+	addu	t3, t0, t2
+cacheloop:
+	cache	0, 0(t2)
+	cache	1, 0(t2)
+	addu	t2, t1
+	bne		t2, t3, cacheloop
+	nop
+
+	/* Save return address */
+	move		t3, ra
+
+	/* Run from cacheable space now */
+	bal		cachehere
+	nop
+cachehere:
+	li		t1, ~0x20000000 /* convert to KSEG0 */
+	and		t0, ra, t1
+	addi	t0, 5*4			/* 5 insns beyond cachehere */
+	jr		t0
+	nop
+
+	/* Restore return address */
+	move		ra, t3
+
+	/*
+	 * Step 9) Initialize the TLB
+	 */
+	li		t0, 0			# index value
+	li		t1, 0x00000000		# entryhi value
+	li		t2, 32			# 32 entries
+
+tlbloop:
+	/* Probe TLB for matching EntryHi */
+	mtc0	t1, CP0_ENTRYHI
+	tlbp
+	nop
+
+	/* Examine Index[P], 1=no matching entry */
+	mfc0	t3, CP0_INDEX
+	li	t4, 0x80000000
+	and	t3, t4, t3
+	addiu	t1, t1, 1		# increment t1 (asid)
+	beq	zero, t3, tlbloop
+	nop
+
+	/* Initialize the TLB entry */
+	mtc0	t0, CP0_INDEX
+	mtc0	zero, CP0_ENTRYLO0
+	mtc0	zero, CP0_ENTRYLO1
+	mtc0	zero, CP0_PAGEMASK
+	tlbwi
+
+	/* Do it again */
+	addiu	t0, t0, 1
+	bne	t0, t2, tlbloop
+	nop
+
+#endif /* CONFIG_DBAU1550 */
+
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12 MHz crystal */
+	li	t0, SYS_CPUPLL
+	li	t1, CPU_SCALE  /* CPU clock */
+	sw	t1, 0(t0)
+	sync
+	nop
+	nop
+
+	/* wait 1mS for clocks to settle */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+	/* Setup AUX PLL */
+	li	t0, SYS_AUXPLL
+	li	t1, 0x20 /* 96 MHz */
+	sw	t1, 0(t0) /* aux pll */
+	sync
+
+#ifdef CONFIG_DBAU1550
+	/*  Static memory controller */
+	/* RCE0 - can not change while fetching, do so from icache */
+	move		t2, ra /* Store return address */
+	bal		getAddr
+	nop
+
+getAddr:
+	move		t1, ra
+	move		ra, t2 /* Move return addess back */
+
+	cache	0x14,0(t1)
+	cache	0x14,32(t1)
+	/*** /From YAMON ***/
+
+noCacheJump:
+#endif /* CONFIG_DBAU1550 */
+
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD MirrorBit Flash (?) */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000003
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11803E00
+	sw	t1, 0(t0)
+#else /* CONFIG_DBAU1550 */
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD 29LV640M MirrorBit Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000013
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11E03F80
+	sw	t1, 0(t0)
+#endif /* CONFIG_DBAU1550 */
+
+	/* RCE1 CPLD Board Logic */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000080
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+
+#ifdef CONFIG_DBAU1550
+	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+#endif
+
+	/* RCE3 PCMCIA 250ns */
+	li	t0, MEM_STCFG3
+	li	t1, 0x00000002
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0x280E3E07
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0x10000000
+	sw	t1, 0(t0)
+
+	sync
+
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+#ifdef CONFIG_DBAU1550
+/* SDCS 0,1,2 DDR SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0xe21003f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0xe21043f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0xe21083f0
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9030060a /* Program refresh - disabled */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDCONFIGB
+	li	t1, 0x00028000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	li	t1, 0
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	sw	zero, 0(t0)
+	sync
+
+	/* Issue 2 autoref */
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	/* Enable refresh */
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9830060a /* Program refresh - enabled */
+	sw	t1, 0(t0)
+	sync
+
+#else /* CONFIG_DBAU1550 */
+/* SDCS 0,1 SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x005522AA
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x005522AA
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0x001003F8
+	sw	t1, 0(t0)
+
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0x001023F8
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x64000C24 /* Disable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x66000C24 /* Enable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000033
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000033
+	sw	t1, 0(t0)
+	sync
+
+#endif /* CONFIG_DBAU1550 */
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+	li	t0, SYS_PINFUNC
+	li	t1, 0x00008080
+	sw	t1, 0(t0)
+
+	li	t0, SYS_TRIOUTCLR
+	li	t1, 0x00001FFF
+	sw	t1, 0(t0)
+
+	li	t0, SYS_OUTPUTCLR
+	li	t1, 0x00008000
+	sw	t1, 0(t0)
+	sync
+
+	jr	ra
+	nop
diff --git a/u-boot/board/dbau1x00/u-boot.lds b/u-boot/board/dbau1x00/u-boot.lds
new file mode 100644
index 0000000..3c4fbe3
--- /dev/null
+++ b/u-boot/board/dbau1x00/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/digsy_mtc/Makefile b/u-boot/board/digsy_mtc/Makefile
new file mode 100644
index 0000000..a40076c
--- /dev/null
+++ b/u-boot/board/digsy_mtc/Makefile
@@ -0,0 +1,32 @@
+
+#
+# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o cmd_mtc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/digsy_mtc/cmd_mtc.c b/u-boot/board/digsy_mtc/cmd_mtc.c
new file mode 100644
index 0000000..ba0c367
--- /dev/null
+++ b/u-boot/board/digsy_mtc/cmd_mtc.c
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2009
+ * Werner Pfister <Pfister_Werner@intercontrol.de>
+ *
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include "spi.h"
+#include "cmd_mtc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *led_names[] = {
+	"diag",
+	"can1",
+	"can2",
+	"can3",
+	"can4",
+	"usbpwr",
+	"usbbusy",
+	"user1",
+	"user2",
+	""
+};
+
+static int msp430_xfer(const void *dout, void *din)
+{
+	int err;
+
+	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din,
+		       SPI_XFER_BEGIN | SPI_XFER_END);
+
+	/* The MSP chip needs time to ready itself for the next command */
+	udelay(1000);
+
+	return err;
+}
+
+static void mtc_calculate_checksum(tx_msp_cmd *packet)
+{
+	int i;
+	uchar *buff;
+
+	buff = (uchar *) packet;
+
+	for (i = 0; i < 6; i++)
+		packet->cks += buff[i];
+}
+
+static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+	int i;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_SET_LED;
+
+	pcmd.cmd_val0 = 0xff;
+	for (i = 0; strlen(led_names[i]) != 0; i++) {
+		if (strncmp(argv[1], led_names[i], strlen(led_names[i])) == 0) {
+			pcmd.cmd_val0 = i;
+			break;
+		}
+	}
+
+	if (pcmd.cmd_val0 == 0xff) {
+		printf("Usage:\n%s\n", cmdtp->help);
+		return -1;
+	}
+
+	if (argc >= 3) {
+		if (strncmp(argv[2], "red", 3) == 0)
+			pcmd.cmd_val1 = 1;
+		else if (strncmp(argv[2], "green", 5) == 0)
+			pcmd.cmd_val1 = 2;
+		else if (strncmp(argv[2], "orange", 6) == 0)
+			pcmd.cmd_val1 = 3;
+		else
+			pcmd.cmd_val1 = 0;
+	}
+
+	if (argc >= 4)
+		pcmd.cmd_val2 = simple_strtol(argv[3], NULL, 10);
+	else
+		pcmd.cmd_val2 = 0;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	return err;
+}
+
+static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_GET_VIM;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	if (!err) {
+		/* function returns '0' if key is pressed */
+		err = (prx.input & 0x80) ? 0 : 1;
+	}
+
+	return err;
+}
+
+static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+	uchar channel_mask = 0;
+
+	if (argc < 3)
+		return cmd_usage(cmdtp);
+
+	if (strncmp(argv[1], "on", 2) == 0)
+		channel_mask |= 1;
+	if (strncmp(argv[2], "on", 2) == 0)
+		channel_mask |= 2;
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_GET_VIM;
+	pcmd.user_out = channel_mask;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	return err;
+}
+
+static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+	uchar channel_num = 0;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	channel_num = simple_strtol(argv[1], NULL, 10);
+	if ((channel_num != 1) && (channel_num != 2)) {
+		printf("mtc digin: invalid parameter - must be '1' or '2'\n");
+		return -1;
+	}
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_GET_VIM;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	if (!err) {
+		/* function returns '0' when digin is on */
+		err = (prx.input & channel_num) ? 0 : 1;
+	}
+
+	return err;
+}
+
+static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+	char buf[5];
+
+	/* read appreg */
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_WD_PARA;
+	pcmd.cmd_val0 = 5;	/* max. Count */
+	pcmd.cmd_val1 = 5;	/* max. Time */
+	pcmd.cmd_val2 = 0;	/* =0 means read appreg */
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	if (!err) {
+		sprintf(buf, "%d", prx.ack2);
+		setenv("appreg", buf);
+	}
+
+	return err;
+}
+
+static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_FW_VERSION;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	if (!err) {
+		printf("FW V%d.%d.%d / HW %d\n",
+		       prx.ack0, prx.ack1, prx.ack3, prx.ack2);
+	}
+
+	return err;
+}
+
+static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_WD_WDSTATE;
+	pcmd.cmd_val2 = 1;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	if (!err) {
+		printf("State     %02Xh\n", prx.state);
+		printf("Input     %02Xh\n", prx.input);
+		printf("UserWD    %02Xh\n", prx.ack2);
+		printf("Sys WD    %02Xh\n", prx.ack3);
+		printf("WD Timout %02Xh\n", prx.ack0);
+		printf("eSysState %02Xh\n", prx.ack1);
+	}
+
+	return err;
+}
+
+static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+cmd_tbl_t cmd_mtc_sub[] = {
+	U_BOOT_CMD_MKENT(led, 3, 1, do_mtc_led,
+	"set state of leds",
+	"[ledname] [state] [blink]\n"
+	" - lednames: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
+	" - state: off red green orange\n"
+	" - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
+	U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
+	"returns state of user key", ""),
+	U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
+	"returns firmware version of supervisor uC", ""),
+	U_BOOT_CMD_MKENT(appreg, 0, 1, do_mtc_appreg,
+	"reads appreg value and stores in environment variable 'appreg'", ""),
+	U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
+	"returns state of digital input",
+	"<channel_num> - get state of digital input (1 or 2)\n"),
+	U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
+	"sets digital outputs",
+	"<on|off> <on|off>- set state of digital output 1 and 2\n"),
+	U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state,
+	"displays state", ""),
+	U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
+	"[command] - get help for command\n"),
+};
+
+static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	extern int _do_help(cmd_tbl_t *cmd_start, int cmd_items,
+			    cmd_tbl_t *cmdtp, int flag,
+			    int argc, char * const argv[]);
+#ifdef CONFIG_SYS_LONGHELP
+	puts("mtc ");
+#endif
+	return _do_help(&cmd_mtc_sub[0],
+			ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
+}
+
+int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cmd_tbl_t *c;
+	int err = 0;
+
+	c = find_cmd_tbl(argv[1], &cmd_mtc_sub[0], ARRAY_SIZE(cmd_mtc_sub));
+	if (c) {
+		argc--;
+		argv++;
+		return c->cmd(c, flag, argc, argv);
+	} else {
+		/* Unrecognized command */
+		return cmd_usage(cmdtp);
+	}
+
+	return err;
+}
+
+U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
+	"special commands for digsyMTC",
+	"[subcommand] [args...]\n"
+	"Subcommands list:\n"
+	"led [ledname] [state] [blink] - set state of leds\n"
+	"  [ledname]: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
+	"  [state]: off red green orange\n"
+	"  [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n"
+	"key - returns state of user key\n"
+	"version - returns firmware version of supervisor uC\n"
+	"appreg - reads appreg value and stores in environment variable"
+	" 'appreg'\n"
+	"digin [channel] - returns state of digital input (1 or 2)\n"
+	"digout <on|off> <on|off> - sets state of two digital outputs\n"
+	"state - displays state\n"
+	"help [subcommand] - get help for subcommand\n"
+);
diff --git a/u-boot/board/digsy_mtc/cmd_mtc.h b/u-boot/board/digsy_mtc/cmd_mtc.h
new file mode 100644
index 0000000..81714e3
--- /dev/null
+++ b/u-boot/board/digsy_mtc/cmd_mtc.h
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2009
+ * Werner Pfister <Pfister_Werner@intercontrol.de>
+ *
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef CMD_MTC_H
+#define CMD_MTC_H
+
+#define	CMD_WD_PARA		0x02
+#define	CMD_WD_WDSTATE		0x04
+#define	CMD_FW_VERSION		0x10
+#define	CMD_GET_VIM		0x30
+#define	CMD_SET_LED		0x40
+
+typedef struct {
+	u8 cmd;
+	u8 sys_in;
+	u8 cmd_val0;
+	u8 cmd_val1;
+	u8 cmd_val2;
+	u8 user_out;
+	u8 cks;
+	u8 dummy1;
+	u8 dummy2;
+} tx_msp_cmd;
+
+typedef struct {
+	u8 input;
+	u8 state;
+	u8 ack2;
+	u8 ack3;
+	u8 ack0;
+	u8 ack1;
+	u8 ack;
+	u8 dummy;
+	u8 cks;
+} rx_msp_cmd;
+
+#define MTC_TRANSFER_SIZE (sizeof(tx_msp_cmd) * 8)
+
+#endif
diff --git a/u-boot/board/digsy_mtc/digsy_mtc.c b/u-boot/board/digsy_mtc/digsy_mtc.c
new file mode 100644
index 0000000..afb0948
--- /dev/null
+++ b/u-boot/board/digsy_mtc/digsy_mtc.c
@@ -0,0 +1,421 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2009
+ * Modified for InterControl digsyMTC MPC5200 board by
+ * Frank Bodammer, GCD Hard- & Software GmbH,
+ *                 frank.bodammer@gcd-solutions.de
+ *
+ * (C) Copyright 2009
+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <net.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "eeprom.h"
+#if defined(CONFIG_DIGSY_REV5)
+#include "is45s16800a2.h"
+#include <mtd/cfi_flash.h>
+#else
+#include "is42s16800a-7t.h"
+#endif
+#include <libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int usb_cpu_init(void);
+
+#if defined(CONFIG_DIGSY_REV5)
+/*
+ * The M29W128GH needs a specail reset command function,
+ * details see the doc/README.cfi file
+ */
+void flash_cmd_reset(flash_info_t *info)
+{
+	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+}
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
+
+	/* find RAM size using SDRAM CS1 only */
+	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+			0x08000000);
+		dramsize2 = test1;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
+			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+	return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts ("Board: InterControl digsyMTC");
+#if defined(CONFIG_DIGSY_REV5)
+	puts (" rev5");
+#endif
+	if (s != NULL) {
+		puts(", ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_MPC52XX_SPI
+	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
+#endif
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection
+	 * process.  Note that CS_BOOT cannot be cleared when executing in
+	 * flash.
+	 */
+	/* disable CS_BOOT */
+	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
+	/* enable CS1 */
+	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
+	/* enable CS0 */
+	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+	/* Low level USB init, required for proper kernel operation */
+	usb_cpu_init();
+#endif
+#ifdef CONFIG_MPC52XX_SPI
+	/* GPT 6 Output Enable */
+	out_be32(&gpt[6].emsr, 0x00000034);
+	/* GPT 7 Output Enable */
+	out_be32(&gpt[7].emsr, 0x00000034);
+#endif
+
+	return (0);
+}
+
+void board_get_enetaddr (uchar * enet)
+{
+	ushort read = 0;
+	ushort addr_of_eth_addr = 0;
+	ushort len_sys = 0;
+	ushort len_sys_cfg = 0;
+
+	/* check identification word */
+	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
+	if (read != EEPROM_IDENT)
+		return;
+
+	/* calculate offset of config area */
+	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
+	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
+		(uchar *)&len_sys_cfg, 2);
+	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
+	if (addr_of_eth_addr >= EEPROM_LEN)
+		return;
+
+	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
+}
+
+int misc_init_r(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_CMD_IDE
+
+#ifdef CONFIG_IDE_RESET
+
+void init_ide_reset(void)
+{
+	debug ("init_ide_reset\n");
+
+	/* set gpio output value to 1 */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+	/* open drain output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+	/* direction output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+	/* enable gpio */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+
+}
+
+void ide_set_reset(int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	/* set gpio output value to 0 */
+	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+	/* open drain output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+	/* direction output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+	/* enable gpio */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+
+	udelay(10000);
+
+	/* set gpio output value to 1 */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+	/* open drain output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+	/* direction output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+	/* enable gpio */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+}
+#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_CMD_IDE */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+static void ft_delete_node(void *fdt, const char *compat)
+{
+	int off = -1;
+	int ret;
+
+	off = fdt_node_offset_by_compatible(fdt, -1, compat);
+	if (off < 0) {
+		printf("Could not find %s node.\n", compat);
+		return;
+	}
+
+	ret = fdt_del_node(fdt, off);
+	if (ret < 0)
+		printf("Could not delete %s node.\n", compat);
+}
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+	flash_info_t	*dev = &flash_info[0];
+	int off;
+	struct fdt_property *prop;
+	int len;
+	u32 *reg, *reg2;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+	if (off < 0) {
+		printf("Could not find fsl,mpc5200b-lpb node.\n");
+		return;
+	}
+
+	/* found compatible property */
+	prop = fdt_get_property_w(blob, off, "ranges", &len);
+	if (prop) {
+		reg = reg2 = (u32 *)&prop->data[0];
+
+		reg[2] = dev->start[0];
+		reg[3] = dev->size;
+		fdt_setprop(blob, off, "ranges", reg2, len);
+	} else
+		printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Update the Flash Baseaddr settings */
+int update_flash_size (int flash_size)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	flash_info_t	*dev;
+	int	i;
+	int size = 0;
+	unsigned long base = 0x0;
+	u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+	for (i = 0; i < 2; i++) {
+		dev = &flash_info[i];
+
+		if (dev->size) {
+			/* calculate new base addr for this chipselect */
+			base -= dev->size;
+			out_be32(cs_reg, START_REG(base));
+			cs_reg++;
+			out_be32(cs_reg, STOP_REG(base, dev->size));
+			cs_reg++;
+			/* recalculate the sectoraddr in the cfi driver */
+			size += flash_get_size(base, i);
+		}
+	}
+	gd->bd->bi_flashstart = base;
+	return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	/*
+	 * There are 2 RTC nodes in the DTS, so remove
+	 * the unneeded node here.
+	 */
+#if defined(CONFIG_DIGSY_REV5)
+	ft_delete_node(blob, "dallas,ds1339");
+#else
+	ft_delete_node(blob, "mc,rv3029c2");
+#endif
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+	ft_adapt_flash_base(blob);
+#endif
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/digsy_mtc/eeprom.h b/u-boot/board/digsy_mtc/eeprom.h
new file mode 100644
index 0000000..39e0378
--- /dev/null
+++ b/u-boot/board/digsy_mtc/eeprom.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2009 Semihalf.
+ * Written by: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the anty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef CMD_EEPROM_H
+#define CMD_EEPROM_H
+
+#define EEPROM_ADDR		CONFIG_SYS_I2C_EEPROM_ADDR
+#define EEPROM_LEN		1024	/* eeprom length */
+#define EEPROM_IDENT		2408	/* identification word */
+#define EEPROM_ADDR_IDENT	0	/* identification word offset */
+#define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
+#define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
+#define EEPROM_ADDR_ETHADDR	23	/* ethernet addres offset */
+
+#endif
diff --git a/u-boot/board/digsy_mtc/is42s16800a-7t.h b/u-boot/board/digsy_mtc/is42s16800a-7t.h
new file mode 100644
index 0000000..64a81f4
--- /dev/null
+++ b/u-boot/board/digsy_mtc/is42s16800a-7t.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x505F0000
+#define SDRAM_CONFIG1	0xD2322900
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/digsy_mtc/is45s16800a2.h b/u-boot/board/digsy_mtc/is45s16800a2.h
new file mode 100644
index 0000000..6ab5c12
--- /dev/null
+++ b/u-boot/board/digsy_mtc/is45s16800a2.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * based on:
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x50470000
+#define SDRAM_CONFIG1	0xD2322900
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/dnp1110/Makefile b/u-boot/board/dnp1110/Makefile
new file mode 100644
index 0000000..8a86c0f
--- /dev/null
+++ b/u-boot/board/dnp1110/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= dnp1110.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/dnp1110/config.mk b/u-boot/board/dnp1110/config.mk
new file mode 100644
index 0000000..ccf8277
--- /dev/null
+++ b/u-boot/board/dnp1110/config.mk
@@ -0,0 +1,17 @@
+#
+# DNP/1110 board with SA1100 cpu
+#
+# http://www.dilnetpc.com
+#
+
+#
+# DILNETPC has 1 banks of 32 MB DRAM
+#
+# c000'0000
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c1f8'0000, the upper 1 MB of the first (only) bank
+#
+
+CONFIG_SYS_TEXT_BASE = 0xc1f80000
diff --git a/u-boot/board/dnp1110/dnp1110.c b/u-boot/board/dnp1110/dnp1110.c
new file mode 100644
index 0000000..c215f5f
--- /dev/null
+++ b/u-boot/board/dnp1110/dnp1110.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <SA-1100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of DNP1110-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_DNP1110;
+
+	/* flash vpp on */
+	PPDR |= 0x80;	/* assumes LCD controller is off */
+	PPSR |= 0x80;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/dnp1110/flash.c b/u-boot/board/dnp1110/flash.c
new file mode 100644
index 0000000..c81abc5
--- /dev/null
+++ b/u-boot/board/dnp1110/flash.c
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+void inline  spin_wheel(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+   int i;
+    ulong size = 0;
+
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+    {
+	switch (i)
+	{
+	   case 0:
+	    flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]);
+		 flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
+		break;
+	   default:
+		panic("configured too many flash banks!\n");
+		break;
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + monitor_flash_len  - 1,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F128J3A:
+				printf ("28F128J3A\n"); break;
+	default:		printf ("Unknown Chip Type\n"); break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+		printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0x00AA00AA;
+	addr[0x2AAA] = (FPW)0x00550055;
+	addr[0x5555] = (FPW)0x00900090;
+
+   mb();
+	value = addr[0];
+
+   switch (value) {
+
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+   mb();
+	value = addr[1];			/* device ID		*/
+   switch (value) {
+
+   case (FPW)INTEL_ID_28F128J3A:
+      info->flash_id += FLASH_28F128J3A;
+      info->sector_count = 128;
+      info->size = 0x02000000;
+      break;            /* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+    }
+
+	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+    }
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+   /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
+
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+			*addr = (FPW)0x00500050;	/* clear status register */
+			*addr = (FPW)0x00200020;	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW)0x00B000B0; /* suspend erase	  */
+					*addr = (FPW)0x00FF00FF; /* reset to read mode */
+					rcode = 1;
+					break;
+	}
+    }
+
+			*addr = (FPW)0x00500050; /* clear status register cmd.   */
+			*addr = (FPW)0x00FF00FF; /* resest to read mode          */
+
+			printf (" done\n");
+	}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+	}
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+	}
+
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+	    return (rc);
+	}
+		wp += port_width;
+    }
+
+    /*
+     * handle word aligned part
+     */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+	    return (rc);
+	}
+		wp  += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800)
+		{
+	 spin_wheel();
+			count = 0;
+		}
+    }
+
+    if (cnt == 0) {
+		return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+	--cnt;
+    }
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x00400040;		/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+    }
+
+	*addr = (FPW)0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+   static int p=0;
+   static char w[] = "\\/-";
+
+   printf("\010%c", w[p]);
+   (++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/dnp1110/lowlevel_init.S b/u-boot/board/dnp1110/lowlevel_init.S
new file mode 100644
index 0000000..7730be3
--- /dev/null
+++ b/u-boot/board/dnp1110/lowlevel_init.S
@@ -0,0 +1,135 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/* some parameters for the board */
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04		/* CAS waveform rotate reg 0       */
+#define MDCAS01		0x08		/* CAS waveform rotate reg 1 bank  */
+#define MDCAS02		0x0C		/* CAS waveform rotate reg 2 bank  */
+#define MDREFR		0x1C		/* DRAM refresh control reg        */
+#define MDCAS20		0x20		/* CAS waveform rotate reg 0 bank  */
+#define MDCAS21		0x24		/* CAS waveform rotate reg 1 bank  */
+#define MDCAS22		0x28		/* CAS waveform rotate reg 2 bank  */
+#define MECR		0x18		/* Expansion memory (PCMCIA) bus configuration  register */
+#define MSC0		0x10		/* static memory control reg 0     */
+#define MSC1		0x14		/* static memory control reg 1     */
+#define MSC2		0x2C		/* static memory control reg 2     */
+#define SMCNFG		0x30		/* SMROM configuration reg         */
+
+mdcas00:	.long	0x5555557F
+mdcas01:	.long	0x55555555
+mdcas02:	.long	0x55555555
+mdcas20:	.long	0x5555557F
+mdcas21:	.long	0x55555555
+mdcas22:	.long	0x55555555
+mdcnfg:		.long	0x0000B25C
+mdrefr:		.long	0x007000C1
+mecr:		.long	0x10841084
+msc0:		.long	0x00004774
+msc1:		.long	0x00000000
+msc2:		.long	0x00000000
+smcnfg:		.long	0x00000000
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	ldr	r0, MEM_BASE
+
+	/* Set up the DRAM */
+
+	/* MDCAS00 */
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+
+	/* MDCAS01 */
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+
+	/* MDCAS02 */
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+
+	/* MDCAS20 */
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+
+	/* MDCAS21 */
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+
+	/* MDCAS22 */
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+
+	/* MDREFR */
+	ldr	r1, mdrefr
+	str	r1, [r0, #MDREFR]
+
+	/* Set up PCMCIA space */
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	/* Setup the flash memory and other */
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	bic	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	/* Load something to activate bank */
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r1, [r2]
+.endr
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	orr	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/eNET/Makefile b/u-boot/board/eNET/Makefile
new file mode 100644
index 0000000..4980787
--- /dev/null
+++ b/u-boot/board/eNET/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= eNET.o
+COBJS-$(CONFIG_PCI) += eNET_pci.o
+SOBJS-y	+= eNET_start16.o
+SOBJS-y	+= eNET_start.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eNET/config.mk b/u-boot/board/eNET/config.mk
new file mode 100644
index 0000000..9d2dfa5
--- /dev/null
+++ b/u-boot/board/eNET/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LDPPFLAGS += -DFLASH_SIZE=0x40000
diff --git a/u-boot/board/eNET/eNET.c b/u-boot/board/eNET/eNET.c
new file mode 100644
index 0000000..dd0ce54
--- /dev/null
+++ b/u-boot/board/eNET/eNET.c
@@ -0,0 +1,287 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/ic/sc520.h>
+#include <net.h>
+#include <netdev.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+#include "hardware.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void enet_timer_isr(void);
+static void enet_toggle_run_led(void);
+static void enet_setup_pars(void);
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_early_init_f(void)
+{
+	u16 pio_out_cfg = 0x0000;
+
+	/* Configure General Purpose Bus timing */
+	writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
+	writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
+	writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
+	writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
+	writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
+	writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
+	writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
+
+	/* Configure Programmable Input/Output Pins */
+	writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
+	writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
+	writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
+	writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
+	writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
+	writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
+
+	/*
+	 * Turn off top board
+	 * Set StrataFlash chips to 16-bit width
+	 * Set StrataFlash chips to normal (non reset/power down) mode
+	 */
+	pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
+	pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
+	pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
+	pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
+	writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
+
+	/* Turn off auxiliary power output */
+	writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
+
+	/* Clear FPGA program mode */
+	writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
+
+	enet_setup_pars();
+
+	/* Disable Watchdog */
+	writew(0x3333, &sc520_mmcr->wdtmrctl);
+	writew(0xcccc, &sc520_mmcr->wdtmrctl);
+	writew(0x0000, &sc520_mmcr->wdtmrctl);
+
+	/* Chip Select Configuration */
+	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
+	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
+	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
+
+	writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
+	writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
+	writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
+
+	writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
+	writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
+
+	/* enable posted-writes */
+	writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
+
+	return 0;
+}
+
+static void enet_setup_pars(void)
+{
+	/*
+	 * PARs 11 and 12 are 2MB SRAM @ 0x19000000
+	 *
+	 * These are setup now because older version of U-Boot have them
+	 * mapped to a different PAR which gets clobbered which prevents
+	 * using SRAM for warm-booting a new image
+	 */
+	writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
+	writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
+
+	/* PARs 0 and 1 are Compact Flash slots (4kB each) */
+	writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
+	writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
+
+	/* PAR 2 is used for Cache-As-RAM */
+
+	/*
+	 * PARs 5 through 8 are additional NS16550 UARTS
+	 * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
+	 */
+	writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
+	writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
+	writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
+	writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
+
+	/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
+	writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
+	writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
+
+	/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
+	writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
+
+	/*
+	 * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
+	 * Already configured in board_init16 (eNET_start16.S)
+	 *
+	 * PAR 15 is Boot ROM
+	 * Already configured in board_init16 (eNET_start16.S)
+	 */
+}
+
+
+int board_early_init_r(void)
+{
+	/* CPU Speed to 100MHz */
+	gd->cpu_clk = 100000000;
+
+	/* Crystal is 33.000MHz */
+	gd->bus_clk = 33000000;
+
+	return 0;
+}
+
+void show_boot_progress(int val)
+{
+	uchar led_mask;
+
+	led_mask = 0x00;
+
+	if (val < 0)
+		led_mask |= LED_ERR_BITMASK;
+
+	led_mask |= (uchar)(val & 0x001f);
+	outb(led_mask, LED_LATCH_ADDRESS);
+}
+
+
+int last_stage_init(void)
+{
+	int minor;
+	int major;
+
+	major = minor = 0;
+
+	outb(0x00, LED_LATCH_ADDRESS);
+
+	register_timer_isr(enet_timer_isr);
+
+	printf("Serck Controls eNET\n");
+
+	return 0;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void setup_pcat_compatibility()
+{
+	/* disable global interrupt mode */
+	writeb(0x40, &sc520_mmcr->picicr);
+
+	/* set all irqs to edge */
+	writeb(0x00, &sc520_mmcr->pic_mode[0]);
+	writeb(0x00, &sc520_mmcr->pic_mode[1]);
+	writeb(0x00, &sc520_mmcr->pic_mode[2]);
+
+	/*
+	 *  active low polarity on PIC interrupt pins,
+	 *  active high polarity on all other irq pins
+	 */
+	writew(0x0000,&sc520_mmcr->intpinpol);
+
+	/*
+	 * PIT 0 -> IRQ0
+	 * RTC -> IRQ8
+	 * FP error -> IRQ13
+	 * UART1 -> IRQ4
+	 * UART2 -> IRQ3
+	 */
+	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
+	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
+	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
+	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
+	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
+
+	/* Disable all other interrupt sources */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
+}
+
+void enet_timer_isr(void)
+{
+	static long enet_ticks = 0;
+
+	enet_ticks++;
+
+	/* Toggle Watchdog every 100ms */
+	if ((enet_ticks % 100) == 0)
+		hw_watchdog_reset();
+
+	/* Toggle Run LED every 500ms */
+	if ((enet_ticks % 500) == 0)
+		enet_toggle_run_led();
+}
+
+void hw_watchdog_reset(void)
+{
+	/* Watchdog Reset must be atomic */
+	long flag = disable_interrupts();
+
+	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
+		sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
+	else
+		sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
+
+	if (flag)
+		enable_interrupts();
+}
+
+void enet_toggle_run_led(void)
+{
+	unsigned char leds_state= inb(LED_LATCH_ADDRESS);
+	if (leds_state & LED_RUN_BITMASK)
+		outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
+	else
+		outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
+}
diff --git a/u-boot/board/eNET/eNET_pci.c b/u-boot/board/eNET/eNET_pci.c
new file mode 100644
index 0000000..fefb1a4
--- /dev/null
+++ b/u-boot/board/eNET/eNET_pci.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/pci.h>
+
+static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* a configurable lists of IRQs to steal when we need one */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin -= 1; /* PCI config space use 1-based numbering */
+	if (pin == -1) {
+		return; /* device use no irq */
+	}
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 12:	/* First Ethernet Chip */
+		pin += SC520_PCI_INTA;
+		break;
+
+	case 13:	/* Second Ethernet Chip */
+		pin += SC520_PCI_INTB;
+		break;
+
+	default:
+		return;
+	}
+
+	pin &= 3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+	if (-1 != sc520_pci_ints[pin]) {
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+	printf("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller enet_hose = {
+	fixup_irq: pci_enet_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&enet_hose);
+}
+
+int pci_set_regions(struct pci_controller *hose)
+{
+	/* System memory space */
+	pci_set_region(hose->regions + 0,
+		       SC520_PCI_MEMORY_BUS,
+		       SC520_PCI_MEMORY_PHYS,
+		       SC520_PCI_MEMORY_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* ISA/PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       SC520_ISA_MEM_BUS,
+		       SC520_ISA_MEM_PHYS,
+		       SC520_ISA_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region(hose->regions + 2,
+		       SC520_PCI_IO_BUS,
+		       SC520_PCI_IO_PHYS,
+		       SC520_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* ISA/PCI I/O space */
+	pci_set_region(hose->regions + 3,
+		       SC520_ISA_IO_BUS,
+		       SC520_ISA_IO_PHYS,
+		       SC520_ISA_IO_SIZE,
+		       PCI_REGION_IO);
+
+	return 4;
+}
diff --git a/u-boot/board/eNET/eNET_start.S b/u-boot/board/eNET/eNET_start.S
new file mode 100644
index 0000000..1b3d289
--- /dev/null
+++ b/u-boot/board/eNET/eNET_start.S
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "hardware.h"
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+	/* No 32-bit board specific initialisation */
+	jmp	early_board_init_ret
+
diff --git a/u-boot/board/eNET/eNET_start16.S b/u-boot/board/eNET/eNET_start16.S
new file mode 100644
index 0000000..77e5519
--- /dev/null
+++ b/u-boot/board/eNET/eNET_start16.S
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+/* #include <asm/ic/sc520_defs.h> */
+
+#include "config.h"
+#include "hardware.h"
+#include <asm/ic/sc520.h>
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax
+	outl	%eax, %dx
+
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax
+	movw	%ax, %ds
+
+	/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
+	movl    $(SC520_PAR14 - SC520_MMCR_BASE), %edi
+	movl	$CONFIG_SYS_SC520_BOOTCS_PAR, %eax
+	movl	%eax, (%di)
+
+	/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
+	movl    $(SC520_PAR15 - SC520_MMCR_BASE), %edi
+	movl	$CONFIG_SYS_SC520_LLIO_PAR, %eax
+	movl	%eax, (%di)
+
+	/* Disabe MMCR alias */
+	movw	$0xfffc, %dx
+	movl	$0x000000cb, %eax
+	outl	%eax, %dx
+
+	jmp	board_init16_ret
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+.hidden realmode_reset
+.type realmode_reset, @function
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax
+	outl	%eax, %dx
+
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax
+	movw	%ax, %ds
+
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+	movb	$0x01, %al
+	movb	%al, (%di)
+
+1:	hlt
+	jmp	1
diff --git a/u-boot/board/eNET/hardware.h b/u-boot/board/eNET/hardware.h
new file mode 100644
index 0000000..dec2cd8
--- /dev/null
+++ b/u-boot/board/eNET/hardware.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+
+#define LED_LATCH_ADDRESS	0x1002
+#define LED_RUN_BITMASK		0x01
+#define LED_1_BITMASK		0x02
+#define LED_2_BITMASK		0x04
+#define LED_RX_BITMASK		0x08
+#define LED_TX_BITMASK		0x10
+#define LED_ERR_BITMASK		0x20
+#define WATCHDOG_PIO_BIT	0x8000
+
+#endif /* HARDWARE_H_ */
diff --git a/u-boot/board/eXalion/Makefile b/u-boot/board/eXalion/Makefile
new file mode 100644
index 0000000..fa87413
--- /dev/null
+++ b/u-boot/board/eXalion/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eXalion/eXalion.c b/u-boot/board/eXalion/eXalion.c
new file mode 100644
index 0000000..c17498f
--- /dev/null
+++ b/u-boot/board/eXalion/eXalion.c
@@ -0,0 +1,299 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <ide.h>
+#include <netdev.h>
+#include <timestamp.h>
+#include "piix_pci.h"
+#include "eXalion.h"
+
+int checkboard (void)
+{
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+
+	printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
+	printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
+	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
+
+	return 0;
+}
+
+int checkflash (void)
+{
+	printf ("checkflash\n");
+	flash_init ();
+	return (0);
+}
+
+phys_size_t initdram (int board_type)
+{
+	int i, cnt;
+	volatile uchar *base = CONFIG_SYS_SDRAM_BASE;
+	volatile ulong *addr;
+	ulong save[32];
+	ulong val, ret = 0;
+
+	for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
+	     cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof (long) - 1;
+			ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
+
+			mear1 = (mear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg (MEAR1, mear1);
+			mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+			ret = cnt * sizeof (long);
+			goto Done;
+		}
+	}
+
+	ret = CONFIG_SYS_MAX_RAM_SIZE;
+      Done:
+	return ret;
+}
+
+int misc_init_r (void)
+{
+	pci_dev_t bdf;
+	u32 val32;
+	u8 val8;
+
+	puts ("ISA:   ");
+	bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
+	if (bdf == -1) {
+		puts ("Unable to find PIIX4 ISA bridge !\n");
+		hang ();
+	}
+
+	/* set device for normal ISA instead EIO */
+	pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+	val32 |= 0x00000001;
+	pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
+	printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
+		PCI_DEV (bdf), PCI_FUNC (bdf));
+
+	puts ("ISA:   ");
+	bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
+	if (bdf == -1) {
+		puts ("Unable to find PIIX4 IDE controller !\n");
+		hang ();
+	}
+
+	/* Init BMIBA register  */
+	/* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
+	/* val32 |= 0x1000; */
+	/* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
+
+	/* Enable BUS master and IO access  */
+	val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+	pci_write_config_dword (bdf, PCI_COMMAND, val32);
+
+	/* Set latency  */
+	pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
+	val8 = 0x40;
+	pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
+
+	/* Enable Primary ATA/IDE  */
+	pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
+	/* val32 = 0xa307a307; */
+	val32 = 0x00008000;
+	pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
+
+
+	printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
+		PCI_DEV (bdf), PCI_FUNC (bdf));
+
+	/* Try to get FAT working... */
+	/* fat_register_read(ide_read); */
+
+
+	return (0);
+}
+
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+
+void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line;
+
+	switch (PCI_DEV (dev)) {
+	case 16:
+		line = PCI_INT_A;
+		break;
+	case 17:
+		line = PCI_INT_B;
+		break;
+	case 18:
+		line = PCI_INT_C;
+		break;
+	case 19:
+		line = PCI_INT_D;
+		break;
+#if defined (CONFIG_MPC8245)
+	case 20:
+		line = PCI_INT_A;
+		break;
+	case 21:
+		line = PCI_INT_B;
+		break;
+	case 22:
+		line = PCI_INT_NA;
+		break;
+#endif
+	default:
+		line = PCI_INT_A;
+		break;
+	}
+	pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+#if defined (CONFIG_MPC8240)
+static struct pci_config_table pci_eXalion_config_table[] = {
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 PCI to ISA bridge */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 IDE controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{}
+};
+#elif defined (CONFIG_MPC8245)
+static struct pci_config_table pci_eXalion_config_table[] = {
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
+				     PCI_ENET1_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Broadcom BCM5690 Gigabit switch */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
+				     PCI_ENET2_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Broadcom BCM5690 Gigabit switch */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
+				     PCI_ENET3_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 PCI to ISA bridge */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 IDE controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{}
+};
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#endif /* #ifndef CONFIG_PCI_PNP */
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_eXalion_config_table,
+	fixup_irq:pci_eXalion_fixup_irq,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/eXalion/eXalion.h b/u-boot/board/eXalion/eXalion.h
new file mode 100644
index 0000000..8dccabb
--- /dev/null
+++ b/u-boot/board/eXalion/eXalion.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXALION_H
+#define __EXALION_H
+
+/* IRQ settings */
+#define  PCI_INT_NA (0xff)   /* PCI Intr. not used */
+#define  PCI_INT_A  (0x09)   /* PCI Intr. A Interrupt Request Line Nr. */
+#define  PCI_INT_B  (0x0a)   /* PCI Intr. B Interrupt Request Line Nr. */
+#define  PCI_INT_C  (0x0b)   /* PCI Intr. C Interrupt Request Line Nr. */
+#define  PCI_INT_D  (0x0c)   /* PCI Intr. D Interrupt Request Line Nr. */
+#if defined (CPU_MPC8245)
+#define  LN_1_INT     PCI_INT_B  /* ethernet interrupt level */
+#define  LN_2_INT     PCI_INT_C  /* ethernet interrupt level */
+#define  BCM_1_INT    PCI_INT_A  /* BCM5690 interrupt level */
+#define  BCM_2_INT    PCI_INT_B  /* BCM5690 interrupt level */
+#elif defined (CPU_MPC8240)
+#define  BCM_INT      PCI_INT_B  /* BCM5600 interrupt level */
+#define  LN_INT       PCI_INT_C  /* ethernet interrupt level */
+#endif
+
+#ifndef __ASSEMBLY__
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __EXALION_H */
diff --git a/u-boot/board/eXalion/piix_pci.h b/u-boot/board/eXalion/piix_pci.h
new file mode 100644
index 0000000..b3c9c16
--- /dev/null
+++ b/u-boot/board/eXalion/piix_pci.h
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define PIIX4_VENDOR_ID         0x8086
+#define PIIX4_ISA_DEV_ID        0x7110
+#define PIIX4_IDE_DEV_ID        0x7111
+
+/* Function 0 ISA Bridge */
+#define PCI_CFG_PIIX4_IORT      0x4C    /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define PCI_CFG_PIIX4_XBCS      0x4E    /* 16 bit XBus Chip select reg (default 0x0003) */
+#define PCI_CFG_PIIX4_PIRQC     0x60    /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define PCI_CFG_PIIX4_SERIRQ    0x64
+#define PCI_CFG_PIIX4_TOM       0x69
+#define PCI_CFG_PIIX4_MSTAT     0x6A
+#define PCI_CFG_PIIX4_MBDMA     0x76
+#define PCI_CFG_PIIX4_APICBS    0x80
+#define PCI_CFG_PIIX4_DLC       0x82
+#define PCI_CFG_PIIX4_PDMACFG   0x90
+#define PCI_CFG_PIIX4_DDMABS    0x92
+#define PCI_CFG_PIIX4_GENCFG    0xB0
+#define PCI_CFG_PIIX4_RTCCFG    0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA    0x00
+#define PIIX4_ISA_DMA1_CH0CA    0x01
+#define PIIX4_ISA_DMA1_CH1BA    0x02
+#define PIIX4_ISA_DMA1_CH1CA    0x03
+#define PIIX4_ISA_DMA1_CH2BA    0x04
+#define PIIX4_ISA_DMA1_CH2CA    0x05
+#define PIIX4_ISA_DMA1_CH3BA    0x06
+#define PIIX4_ISA_DMA1_CH3CA    0x07
+#define PIIX4_ISA_DMA1_CMDST    0x08
+#define PIIX4_ISA_DMA1_REQ      0x09
+#define PIIX4_ISA_DMA1_WSBM     0x0A
+#define PIIX4_ISA_DMA1_CH_MOD   0x0B
+#define PIIX4_ISA_DMA1_CLR_PT   0x0C
+#define PIIX4_ISA_DMA1_M_CLR    0x0D
+#define PIIX4_ISA_DMA1_CLR_M    0x0E
+#define PIIX4_ISA_DMA1_RWAMB    0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA    0xC0
+#define PIIX4_ISA_DMA2_CH0CA    0xC1
+#define PIIX4_ISA_DMA2_CH1BA    0xC2
+#define PIIX4_ISA_DMA2_CH1CA    0xC3
+#define PIIX4_ISA_DMA2_CH2BA    0xC4
+#define PIIX4_ISA_DMA2_CH2CA    0xC5
+#define PIIX4_ISA_DMA2_CH3BA    0xC6
+#define PIIX4_ISA_DMA2_CH3CA    0xC7
+#define PIIX4_ISA_DMA2_CMDST    0xD0
+#define PIIX4_ISA_DMA2_REQ      0xD2
+#define PIIX4_ISA_DMA2_WSBM     0xD4
+#define PIIX4_ISA_DMA2_CH_MOD   0xD6
+#define PIIX4_ISA_DMA2_CLR_PT   0xD8
+#define PIIX4_ISA_DMA2_M_CLR    0xDA
+#define PIIX4_ISA_DMA2_CLR_M    0xDC
+#define PIIX4_ISA_DMA2_RWAMB    0xDE
+
+#define PIIX4_ISA_INT1_ICW1     0x20
+#define PIIX4_ISA_INT1_OCW2     0x20
+#define PIIX4_ISA_INT1_OCW3     0x20
+#define PIIX4_ISA_INT1_ICW2     0x21
+#define PIIX4_ISA_INT1_ICW3     0x21
+#define PIIX4_ISA_INT1_ICW4     0x21
+#define PIIX4_ISA_INT1_OCW1     0x21
+
+#define PIIX4_ISA_INT1_ELCR     0x4D0
+
+#define PIIX4_ISA_INT2_ICW1     0xA0
+#define PIIX4_ISA_INT2_OCW2     0xA0
+#define PIIX4_ISA_INT2_OCW3     0xA0
+#define PIIX4_ISA_INT2_ICW2     0xA1
+#define PIIX4_ISA_INT2_ICW3     0xA1
+#define PIIX4_ISA_INT2_ICW4     0xA1
+#define PIIX4_ISA_INT2_OCW1     0xA1
+#define PIIX4_ISA_INT2_IMR      0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR     0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST   0x40
+#define PIIX4_ISA_TMR1_CNT_ST   0x41
+#define PIIX4_ISA_TMR2_CNT_ST   0x42
+#define PIIX4_ISA_TMR_TCW       0x43
+
+#define PIIX4_ISA_RST_XBUS      0x60
+
+#define PIIX4_ISA_NMI_CNT_ST    0x61
+#define PIIX4_ISA_NMI_ENABLE    0x70
+
+#define PIIX4_ISA_RTC_INDEX     0x70
+#define PIIX4_ISA_RTC_DATA      0x71
+#define PIIX4_ISA_RTCEXT_IND    0x70
+#define PIIX4_ISA_RTCEXT_DATA   0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG   0x81
+#define PIIX4_ISA_DMA1_CH3LPG   0x82
+#define PIIX4_ISA_DMA1_CH1LPG   0x83
+#define PIIX4_ISA_DMA1_CH0LPG   0x87
+#define PIIX4_ISA_DMA2_CH2LPG   0x89
+#define PIIX4_ISA_DMA2_CH3LPG   0x8A
+#define PIIX4_ISA_DMA2_CH1LPG   0x8B
+#define PIIX4_ISA_DMA2_LPGRFR   0x8F
+
+#define PIIX4_ISA_PORT_92       0x92
+
+#define PIIX4_ISA_APM_CONTRL    0xB2
+#define PIIX4_ISA_APM_STATUS    0xB3
+
+#define PIIX4_ISA_COCPU_ERROR   0xF0
+
+/* Function 1 IDE Controller */
+#define PCI_CFG_PIIX4_BMIBA     0x20
+#define PCI_CFG_PIIX4_IDETIM    0x40
+#define PCI_CFG_PIIX4_SIDETIM   0x44
+#define PCI_CFG_PIIX4_UDMACTL   0x48
+#define PCI_CFG_PIIX4_UDMATIM   0x4A
+
+/* Function 2 USB Controller */
+#define PCI_CFG_PIIX4_SBRNUM    0x60
+#define PCI_CFG_PIIX4_LEGSUP    0xC0
+
+/* Function 3 Power Management */
+#define PCI_CFG_PIIX4_PMAB      0x40
+#define PCI_CFG_PIIX4_CNTA      0x44
+#define PCI_CFG_PIIX4_CNTB      0x48
+#define PCI_CFG_PIIX4_GPICTL    0x4C
+#define PCI_CFG_PIIX4_DEVRESD   0x50
+#define PCI_CFG_PIIX4_DEVACTA   0x54
+#define PCI_CFG_PIIX4_DEVACTB   0x58
+#define PCI_CFG_PIIX4_DEVRESA   0x5C
+#define PCI_CFG_PIIX4_DEVRESB   0x60
+#define PCI_CFG_PIIX4_DEVRESC   0x64
+#define PCI_CFG_PIIX4_DEVRESE   0x68
+#define PCI_CFG_PIIX4_DEVRESF   0x6C
+#define PCI_CFG_PIIX4_DEVRESG   0x70
+#define PCI_CFG_PIIX4_DEVRESH   0x74
+#define PCI_CFG_PIIX4_DEVRESI   0x78
+#define PCI_CFG_PIIX4_PMMISC    0x80
+#define PCI_CFG_PIIX4_SMBBA     0x90
+
+
+#endif  /* _PIIX4_PCI_H */
diff --git a/u-boot/board/earthlcd/favr-32-ezkit/Makefile b/u-boot/board/earthlcd/favr-32-ezkit/Makefile
new file mode 100644
index 0000000..00eb0f4
--- /dev/null
+++ b/u-boot/board/earthlcd/favr-32-ezkit/Makefile
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2008 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation; either version 2 of the License, or (at your option) any later
+# version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+# details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+# Place, Suite 330, Boston, MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/earthlcd/favr-32-ezkit/config.mk b/u-boot/board/earthlcd/favr-32-ezkit/config.mk
new file mode 100644
index 0000000..f8bc88d
--- /dev/null
+++ b/u-boot/board/earthlcd/favr-32-ezkit/config.mk
@@ -0,0 +1,4 @@
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
+CONFIG_SYS_TEXT_BASE		= 0x00000000
+LDSCRIPT		= $(src)board/earthlcd/favr-32-ezkit/u-boot.lds
diff --git a/u-boot/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/u-boot/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
new file mode 100644
index 0000000..b0eca93
--- /dev/null
+++ b/u-boot/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	/* MT48LC4M32B2P-6 (16 MB) */
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 12,
+	.col_bits	= 8,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 15.6 us */
+	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart3(PORTMUX_DRIVE_MIN);
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = uncached(EBI_SDRAM_BASE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	return 0;
+}
+
+#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bi)
+{
+	return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+}
+#endif
diff --git a/u-boot/board/earthlcd/favr-32-ezkit/flash.c b/u-boot/board/earthlcd/favr-32-ezkit/flash.c
new file mode 100644
index 0000000..0a26146
--- /dev/null
+++ b/u-boot/board/earthlcd/favr-32-ezkit/flash.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
+#include <asm/arch/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void flash_identify(uint16_t *flash, flash_info_t *info)
+{
+	unsigned long flags;
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+
+	writew(0xaa, flash + 0x555);
+	writew(0x55, flash + 0xaaa);
+	writew(0x90, flash + 0x555);
+	info->flash_id = readl(flash);
+	writew(0xff, flash);
+
+	readw(flash);
+
+	if (flags)
+		enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long addr;
+	unsigned int i;
+
+	flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+	flash_info[0].sector_count = 135;
+
+	flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
+
+	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+		flash_info[0].start[i] = addr;
+	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+		flash_info[0].start[i] = addr;
+
+	return CONFIG_SYS_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
+	       info->flash_id >> 16, info->flash_id & 0xffff);
+	printf("Size: %ld MB in %d sectors\n",
+	       info->size >> 10, info->sector_count);
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long flags;
+	unsigned long start_time;
+	uint16_t *fb, *sb;
+	unsigned int i;
+	int ret;
+	uint16_t status;
+
+	if ((s_first < 0) || (s_first > s_last)
+	    || (s_last >= info->sector_count)) {
+		puts("Error: first and/or last sector out of range\n");
+		return ERR_INVAL;
+	}
+
+	for (i = s_first; i < s_last; i++)
+		if (info->protect[i]) {
+			printf("Error: sector %d is protected\n", i);
+			return ERR_PROTECTED;
+		}
+
+	fb = (uint16_t *)uncached(info->start[0]);
+
+	dcache_flush_unlocked();
+
+	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+		printf("Erasing sector %3d...", i);
+
+		sb = (uint16_t *)uncached(info->start[i]);
+
+		flags = disable_interrupts();
+
+		start_time = get_timer(0);
+
+		/* Unlock sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x70, sb);
+
+		/* Erase sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x80, fb + 0x555);
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x30, sb);
+
+		/* Wait for completion */
+		ret = ERR_OK;
+		do {
+			/* TODO: Timeout */
+			status = readw(sb);
+		} while ((status != 0xffff) && !(status & 0x28));
+
+		writew(0xf0, fb);
+
+		/*
+		 * Make sure the command actually makes it to the bus
+		 * before we re-enable interrupts.
+		 */
+		readw(fb);
+
+		if (flags)
+			enable_interrupts();
+
+		if (status != 0xffff) {
+			printf("Flash erase error at address 0x%p: 0x%02x\n",
+			       sb, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (ctrlc())
+		printf("User interrupt!\n");
+
+	return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, uchar *src,
+			   ulong addr, ulong count)
+{
+	unsigned long flags;
+	uint16_t *base, *p, *s, *end;
+	uint16_t word, status, status1;
+	int ret = ERR_OK;
+
+	if (addr < info->start[0]
+	    || (addr + count) > (info->start[0] + info->size)
+	    || (addr + count) < addr) {
+		puts("Error: invalid address range\n");
+		return ERR_INVAL;
+	}
+
+	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+		puts("Error: misaligned source, destination or count\n");
+		return ERR_ALIGN;
+	}
+
+	base = (uint16_t *)uncached(info->start[0]);
+	end = (uint16_t *)uncached(addr + count);
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+	sync_write_buffer();
+
+	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+	     p < end && !ctrlc(); p++, s++) {
+		word = *s;
+
+		writew(0xaa, base + 0x555);
+		writew(0x55, base + 0xaaa);
+		writew(0xa0, base + 0x555);
+		writew(word, p);
+
+		sync_write_buffer();
+
+		/* Wait for completion */
+		status1 = readw(p);
+		do {
+			/* TODO: Timeout */
+			status = status1;
+			status1 = readw(p);
+		} while (((status ^ status1) & 0x40)	/* toggled */
+			 && !(status1 & 0x28));		/* error bits */
+
+		/*
+		 * We'll need to check once again for toggle bit
+		 * because the toggle bit may stop toggling as I/O5
+		 * changes to "1" (ref at49bv642.pdf p9)
+		 */
+		status1 = readw(p);
+		status = readw(p);
+		if ((status ^ status1) & 0x40) {
+			printf("Flash write error at address 0x%p: "
+			       "0x%02x != 0x%02x\n",
+			       p, status,word);
+			ret = ERR_PROG_ERROR;
+			writew(0xf0, base);
+			readw(base);
+			break;
+		}
+
+		writew(0xf0, base);
+		readw(base);
+	}
+
+	if (flags)
+		enable_interrupts();
+
+	return ret;
+}
+
+#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */
diff --git a/u-boot/board/earthlcd/favr-32-ezkit/u-boot.lds b/u-boot/board/earthlcd/favr-32-ezkit/u-boot.lds
new file mode 100644
index 0000000..0d413a0
--- /dev/null
+++ b/u-boot/board/earthlcd/favr-32-ezkit/u-boot.lds
@@ -0,0 +1,70 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss (NOLOAD) : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/u-boot/board/edb93xx/Makefile b/u-boot/board/edb93xx/Makefile
new file mode 100644
index 0000000..dcaed06
--- /dev/null
+++ b/u-boot/board/edb93xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/edb93xx/config.mk b/u-boot/board/edb93xx/config.mk
new file mode 100644
index 0000000..fab59ef
--- /dev/null
+++ b/u-boot/board/edb93xx/config.mk
@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+CONFIG_SYS_TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+CONFIG_SYS_TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+CONFIG_SYS_TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+CONFIG_SYS_TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+CONFIG_SYS_TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+CONFIG_SYS_TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+CONFIG_SYS_TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+CONFIG_SYS_TEXT_BASE = 0xc1f00000
+endif
diff --git a/u-boot/board/edb93xx/early_udelay.h b/u-boot/board/edb93xx/early_udelay.h
new file mode 100644
index 0000000..185283d
--- /dev/null
+++ b/u-boot/board/edb93xx/early_udelay.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+	/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+	register uint32_t loops = usecs * (1000 / 20);
+
+	__asm__ volatile ("1:\n"
+			"subs %0, %1, #1\n"
+			"bne 1b":"=r" (loops):"0" (loops));
+}
diff --git a/u-boot/board/edb93xx/edb93xx.c b/u-boot/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..dde30ff
--- /dev/null
+++ b/u-boot/board/edb93xx/edb93xx.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_BANK_SIZE	0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+	PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+	PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+	PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+	PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	icache_enable();
+
+#ifdef USE_920T_MMU
+	dcache_enable();
+#endif
+
+	/*
+	 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+	 * 14.7456/2 MHz
+	 */
+	uint32_t value = readl(&syscon->pwrcnt);
+	value |= SYSCON_PWRCNT_UART_BAUD;
+	writel(value, &syscon->pwrcnt);
+
+	/* Enable the uart in devicecfg */
+	value = readl(&syscon->devicecfg);
+	value |= 1<<18 /* U1EN */;
+	writel(0xAA, &syscon->sysswlock);
+	writel(value, &syscon->devicecfg);
+
+	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* We have a console */
+	gd->have_console = 1;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+int dram_init(void)
+{
+	unsigned int *src, *dst;
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		const ulong bank_size = get_ram_size((long *)bank_addr[i],
+						MAX_BANK_SIZE);
+		if (bank_size) {
+			gd->bd->bi_dram[i].start = bank_addr[i];
+			gd->bd->bi_dram[i].size = bank_size;
+		}
+	}
+
+	/* copy exception vectors */
+	src = (unsigned int *)_armboot_start;
+	dst = (unsigned int *)PHYS_SDRAM_1;
+	memcpy(dst, src, 16 * sizeof(unsigned int));
+
+	return 0;
+}
diff --git a/u-boot/board/edb93xx/flash_cfg.c b/u-boot/board/edb93xx/flash_cfg.c
new file mode 100644
index 0000000..a4c2048
--- /dev/null
+++ b/u-boot/board/edb93xx/flash_cfg.c
@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE	(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT |	\
+				SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT |		\
+				1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+	struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+	writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
diff --git a/u-boot/board/edb93xx/pll_cfg.c b/u-boot/board/edb93xx/pll_cfg.c
new file mode 100644
index 0000000..a687af0
--- /dev/null
+++ b/u-boot/board/edb93xx/pll_cfg.c
@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	/* setup PLL1 */
+	writel(CLKSET1_VAL, &syscon->clkset1);
+
+	/*
+	 * flush the pipeline
+	 * writing to CLKSET1 causes the EP93xx to enter standby for between
+	 * 8 ms to 16 ms, until PLL1 stabilizes
+	 */
+	asm("nop");
+	asm("nop");
+	asm("nop");
+	asm("nop");
+	asm("nop");
+
+	/* setup PLL2 */
+	writel(CLKSET2_VAL, &syscon->clkset2);
+
+	/*
+	 * the user's guide recommends to wait at least 1 ms for PLL2 to
+	 * stabilize
+	 */
+	early_udelay(1000);
+}
diff --git a/u-boot/board/edb93xx/pll_cfg.h b/u-boot/board/edb93xx/pll_cfg.h
new file mode 100644
index 0000000..0b6f469
--- /dev/null
+++ b/u-boot/board/edb93xx/pll_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
+	defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL	(7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	\
+			3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
+			SYSCON_CLKSET1_NBYP1 |			\
+			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
+	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
+	defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	\
+			2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
+			SYSCON_CLKSET1_NBYP1 |			\
+			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET_PLL_PS_SHIFT |	\
+			SYSCON_CLKSET2_PLL2_EN |		\
+			SYSCON_CLKSET2_NBYP2 |			\
+			3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/u-boot/board/edb93xx/sdram_cfg.c b/u-boot/board/edb93xx/sdram_cfg.c
new file mode 100644
index 0000000..440ad11
--- /dev/null
+++ b/u-boot/board/edb93xx/sdram_cfg.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank)		(*(volatile uint32_t *)		\
+		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank)		(*(volatile uint32_t *)		\
+		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
+
+static void precharge_all_banks(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+	/* Issue continous NOP commands */
+	writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+	early_udelay(200);
+
+	precharge_all_banks();
+
+	setup_refresh_timer();
+
+	program_mode_registers();
+
+	/* Select normal operation mode */
+	writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+static void precharge_all_banks(void)
+{
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	/* Issue PRECHARGE ALL commands */
+	writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
+
+	/*
+	 * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
+	 * issued
+	 *
+	 * Cirrus proposes a workaround which consists in performing a read from
+	 * each bank to force the precharge. This causes some boards to hang.
+	 * Writing to the SDRAM banks instead of reading has the same
+	 * side-effect (the SDRAM controller issues the necessary precharges),
+	 * but is known to work on all supported boards
+	 */
+
+	PRECHARGE_BANK(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	PRECHARGE_BANK(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	PRECHARGE_BANK(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+	PRECHARGE_BANK(3);
+#endif
+}
+
+static void setup_refresh_timer(void)
+{
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	/* Load refresh timer with 10 to issue refresh every 10 cycles */
+	writel(0x0a, &sdram->refrshtimr);
+
+	/*
+	 * Wait at least 80 clock cycles to provide 8 refresh cycles
+	 * to all SDRAMs
+	 */
+	early_udelay(1);
+
+	/*
+	 * Program refresh timer with normal value
+	 * We need 8192 refresh cycles every 64ms
+	 * at 15ns (HCLK >= 66MHz) per cycle:
+	 * 64ms / 8192 = 7.8125us
+	 * 7.8125us / 15ns = 520 (0x208)
+	 */
+	/*
+	 * TODO: redboot uses 0x1e0 for the slowest possible device
+	 * but i don't understand how this value is calculated
+	 */
+	writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	/* Select mode register update mode */
+	writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+	/*
+	 * The mode registers are programmed by performing a read from each
+	 * SDRAM bank. The value of the address that is read defines the value
+	 * that is written into the mode register
+	 */
+
+	PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+	PROGRAM_MODE_REG(3);
+#endif
+}
diff --git a/u-boot/board/edb93xx/sdram_cfg.h b/u-boot/board/edb93xx/sdram_cfg.h
new file mode 100644
index 0000000..757b63c
--- /dev/null
+++ b/u-boot/board/edb93xx/sdram_cfg.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR		PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG	devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG	devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
+	defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ *	@ CAS latency = 3: 7.5ns
+ *	@ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ *	20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT |			\
+				SDRAM_DEVCFG_SROMLL |			\
+				SDRAM_DEVCFG_CASLAT_2 |			\
+				SDRAM_DEVCFG_RASTOCAS_2 |		\
+				SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL	0x4600
+
+#define SDRAM_BANK_SEL_0	0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1	0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2	0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3	0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
+	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
+	defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ *	@ CAS latency = 3: 7.5ns
+ *	@ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ *	20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL	(SDRAM_DEVCFG_BANKCOUNT |		\
+				SDRAM_DEVCFG_SROMLL |			\
+				SDRAM_DEVCFG_CASLAT_2 |			\
+				SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL	0x8800
+
+#define SDRAM_BANK_SEL_0	0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1	0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2	0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3	0x00c00000 /* A[23:22] = b11 */
+#endif
diff --git a/u-boot/board/efikamx/Makefile b/u-boot/board/efikamx/Makefile
new file mode 100644
index 0000000..ee4a16e
--- /dev/null
+++ b/u-boot/board/efikamx/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= efikamx.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/efikamx/config.mk b/u-boot/board/efikamx/config.mk
new file mode 100644
index 0000000..6e90671
--- /dev/null
+++ b/u-boot/board/efikamx/config.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
diff --git a/u-boot/board/efikamx/efikamx.c b/u-boot/board/efikamx/efikamx.c
new file mode 100644
index 0000000..f735260
--- /dev/null
+++ b/u-boot/board/efikamx/efikamx.c
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <mxc_gpio.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Compile-time error checking
+ */
+#ifndef	CONFIG_MXC_SPI
+#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
+#endif
+
+/*
+ * Shared variables / local defines
+ */
+/* LED */
+#define	EFIKAMX_LED_BLUE	0x1
+#define	EFIKAMX_LED_GREEN	0x2
+#define	EFIKAMX_LED_RED		0x4
+
+void efikamx_toggle_led(uint32_t mask);
+
+/* Board revisions */
+#define	EFIKAMX_BOARD_REV_11	0x1
+#define	EFIKAMX_BOARD_REV_12	0x2
+#define	EFIKAMX_BOARD_REV_13	0x3
+#define	EFIKAMX_BOARD_REV_14	0x4
+
+/*
+ * Board identification
+ */
+u32 get_efika_rev(void)
+{
+	u32 rev = 0;
+	/*
+	 * Retrieve board ID:
+	 *      rev1.1: 1,1,1
+	 *      rev1.2: 1,1,0
+	 *      rev1.3: 1,0,1
+	 *      rev1.4: 1,0,0
+	 */
+	mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
+				MXC_GPIO_DIRECTION_OUT);
+	/* set to 1 in order to get correct value on board rev1.1 */
+	mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
+				MXC_GPIO_DIRECTION_IN);
+	rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1),
+				MXC_GPIO_DIRECTION_IN);
+	rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
+
+	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3),
+				MXC_GPIO_DIRECTION_IN);
+	rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
+
+	return (~rev & 0x7) + 1;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev() | (get_efika_rev() << 8);
+}
+
+/*
+ * DRAM initialization
+ */
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+/*
+ * UART configuration
+ */
+static void setup_iomux_uart(void)
+{
+	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+
+	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+/*
+ * SPI configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+
+	/* Configure SS0 as a GPIO */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
+				MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
+
+	/* Configure SS1 as a GPIO */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
+				MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
+
+	/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+#else
+static inline void setup_iomux_spi(void) { }
+#endif
+
+/*
+ * PMIC configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void power_init(void)
+{
+	unsigned int val;
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+	/* Write needed to Power Gate 2 register */
+	val = pmic_reg_read(REG_POWER_MISC);
+	val &= ~PWGT2SPIEN;
+	pmic_reg_write(REG_POWER_MISC, val);
+
+	/* Externally powered */
+	val = pmic_reg_read(REG_CHARGE);
+	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+	pmic_reg_write(REG_CHARGE, val);
+
+	/* power up the system first */
+	pmic_reg_write(REG_POWER_MISC, PWUP);
+
+	/* Set core voltage to 1.1V */
+	val = pmic_reg_read(REG_SW_0);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+	pmic_reg_write(REG_SW_0, val);
+
+	/* Setup VCC (SW2) to 1.25 */
+	val = pmic_reg_read(REG_SW_1);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+	pmic_reg_write(REG_SW_1, val);
+
+	/* Setup 1V2_DIG1 (SW3) to 1.25 */
+	val = pmic_reg_read(REG_SW_2);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+	pmic_reg_write(REG_SW_2, val);
+	udelay(50);
+
+	/* Raise the core frequency to 800MHz */
+	writel(0x0, &mxc_ccm->cacrr);
+
+	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
+	/* Setup the switcher mode for SW1 & SW2*/
+	val = pmic_reg_read(REG_SW_4);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	pmic_reg_write(REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	val = pmic_reg_read(REG_SW_5);
+	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+		(SWMODE_MASK << SWMODE4_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+	pmic_reg_write(REG_SW_5, val);
+
+	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+	val = pmic_reg_read(REG_SETTING_0);
+	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+	val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+	pmic_reg_write(REG_SETTING_0, val);
+
+	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+	val = pmic_reg_read(REG_SETTING_1);
+	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+	pmic_reg_write(REG_SETTING_1, val);
+
+	/* Configure VGEN3 and VCAM regulators to use external PNP */
+	val = VGEN3CONFIG | VCAMCONFIG;
+	pmic_reg_write(REG_MODE_1, val);
+	udelay(200);
+
+	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+		VVIDEOEN | VAUDIOEN  | VSDEN;
+	pmic_reg_write(REG_MODE_1, val);
+
+	val = pmic_reg_read(REG_POWER_CTL2);
+	val |= WDIRESET;
+	pmic_reg_write(REG_POWER_CTL2, val);
+
+	udelay(2500);
+}
+#else
+static inline void power_init(void) { }
+#endif
+
+/*
+ * MMC configuration
+ */
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+	{MMC_SDHC2_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *absent, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
+	else
+		*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
+
+	return 0;
+}
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/* SDHC1 is used on all revisions, setup control pins first */
+	mxc_request_iomux(MX51_PIN_GPIO1_0,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+		PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+		PAD_CTL_ODE_OPENDRAIN_NONE |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_GPIO1_1,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+		PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+		PAD_CTL_SRE_FAST);
+
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0),
+				MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1),
+				MXC_GPIO_DIRECTION_IN);
+
+	/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
+	if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
+		/* SDHC1 IOMUX */
+		mxc_request_iomux(MX51_PIN_SD1_CMD,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+			PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_CLK,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+			PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+			PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+			PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+			PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+			PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+		/* SDHC2 IOMUX */
+		mxc_request_iomux(MX51_PIN_SD2_CMD,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD2_CLK,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		/* SDHC2 Control lines IOMUX */
+		mxc_request_iomux(MX51_PIN_GPIO1_7,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
+			PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+			PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+			PAD_CTL_ODE_OPENDRAIN_NONE |
+			PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+		mxc_request_iomux(MX51_PIN_GPIO1_8,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
+			PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+			PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+			PAD_CTL_SRE_FAST);
+
+		mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8),
+					MXC_GPIO_DIRECTION_IN);
+		mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7),
+					MXC_GPIO_DIRECTION_IN);
+
+		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+		if (!ret)
+			ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
+	} else {	/* New boards use only SDHC1 */
+		/* SDHC1 IOMUX */
+		mxc_request_iomux(MX51_PIN_SD1_CMD,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_CLK,
+			IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+			PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+	}
+	return ret;
+}
+#endif
+
+/*
+ * ATA
+ */
+#ifdef	CONFIG_MX51_PATA
+#define	ATA_PAD_CONFIG	(PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
+void setup_iomux_ata(void)
+{
+	mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
+}
+#else
+static inline void setup_iomux_ata(void) { }
+#endif
+
+/*
+ * LED configuration
+ */
+void setup_iomux_led(void)
+{
+	/* Blue LED */
+	mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
+				MXC_GPIO_DIRECTION_OUT);
+	/* Green LED */
+	mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
+				MXC_GPIO_DIRECTION_OUT);
+	/* Red LED */
+	mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
+	mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
+				MXC_GPIO_DIRECTION_OUT);
+}
+
+void efikamx_toggle_led(uint32_t mask)
+{
+	mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
+			mask & EFIKAMX_LED_BLUE);
+	mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
+			mask & EFIKAMX_LED_GREEN);
+	mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
+			mask & EFIKAMX_LED_RED);
+}
+
+/*
+ * Board initialization
+ */
+static void init_drive_strength(void)
+{
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+
+	/* Setting pad options */
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+
+int board_early_init_f(void)
+{
+	init_drive_strength();
+
+	setup_iomux_uart();
+	setup_iomux_spi();
+	setup_iomux_led();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX51_EFIKAMX;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setup_iomux_spi();
+
+	power_init();
+
+	setup_iomux_led();
+	setup_iomux_ata();
+
+	efikamx_toggle_led(EFIKAMX_LED_BLUE);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 system_rev = get_cpu_rev();
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	puts("Board: Efika MX ");
+
+	switch (system_rev & 0xff) {
+	case CHIP_REV_3_0:
+		puts("3.0 [");
+		break;
+	case CHIP_REV_2_5:
+		puts("2.5 [");
+		break;
+	case CHIP_REV_2_0:
+		puts("2.0 [");
+		break;
+	case CHIP_REV_1_1:
+		puts("1.1 [");
+		break;
+	case CHIP_REV_1_0:
+	default:
+		puts("1.0 [");
+		break;
+	}
+
+	cause = src_regs->srsr;
+	switch (cause) {
+	case 0x0001:
+		puts("POR");
+		break;
+	case 0x0009:
+		puts("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		puts("WDOG");
+		break;
+	default:
+		printf("unknown 0x%x", cause);
+	}
+	puts("]\n");
+
+	return 0;
+}
diff --git a/u-boot/board/efikamx/imximage.cfg b/u-boot/board/efikamx/imximage.cfg
new file mode 100644
index 0000000..6fe0ff9
--- /dev/null
+++ b/u-boot/board/efikamx/imximage.cfg
@@ -0,0 +1,122 @@
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+BOOT_FROM	spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x73fa88a0 0x000
+DATA 4 0x73fa850c 0x20c5
+DATA 4 0x73fa8510 0x20c5
+DATA 4 0x73fa883c 0x5
+DATA 4 0x73fa8848 0x5
+DATA 4 0x73fa84b8 0xe7
+DATA 4 0x73fa84bc 0x45
+DATA 4 0x73fa84c0 0x45
+DATA 4 0x73fa84c4 0x45
+DATA 4 0x73fa84c8 0x45
+DATA 4 0x73fa8820 0x0
+DATA 4 0x73fa84a4 0x5
+DATA 4 0x73fa84a8 0x5
+DATA 4 0x73fa84ac 0xe5
+DATA 4 0x73fa84b0 0xe5
+DATA 4 0x73fa84b4 0xe5
+DATA 4 0x73fa84cc 0xe5
+DATA 4 0x73fa84d0 0xe4
+
+DATA 4 0x73fa882c 0x4
+DATA 4 0x73fa88a4 0x4
+DATA 4 0x73fa88ac 0x4
+DATA 4 0x73fa88b8 0x4
+
+# Setting DDR for micron
+# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+# CAS=3 BL=4
+# ESDCTL_ESDCTL0
+DATA 4 0x83fd9000 0x82a20000
+# ESDCTL_ESDCTL1
+DATA 4 0x83fd9008 0x82a20000
+# ESDCTL_ESDMISC
+DATA 4 0x83fd9010 0xcaaaf6d0
+# ESDCTL_ESDCFG0
+DATA 4 0x83fd9004 0x3f3574aa
+# ESDCTL_ESDCFG1
+DATA 4 0x83fd900c 0x3f3574aa
+
+# Init DRAM on CS0
+# ESDCTL_ESDSCR
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x0000801a
+DATA 4 0x83fd9014 0x0000801b
+DATA 4 0x83fd9014 0x00448019
+DATA 4 0x83fd9014 0x07328018
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x06328018
+DATA 4 0x83fd9014 0x03808019
+DATA 4 0x83fd9014 0x00408019
+DATA 4 0x83fd9014 0x00008000
+
+# Init DRAM on CS1
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x0000801e
+DATA 4 0x83fd9014 0x0000801f
+DATA 4 0x83fd9014 0x0000801d
+DATA 4 0x83fd9014 0x0732801c
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x0632801c
+DATA 4 0x83fd9014 0x0380801d
+DATA 4 0x83fd9014 0x0040801d
+DATA 4 0x83fd9014 0x00008004
+
+# Write to CTL0
+DATA 4 0x83fd9000 0xb2a20000
+# Write to CTL1
+DATA 4 0x83fd9008 0xb2a20000
+# ESDMISC
+DATA 4 0x83fd9010 0x000ad6d0
+#ESDCTL_ESDCDLYGD
+DATA 4 0x83fd9034 0x90000000
+DATA 4 0x83fd9014 0x00000000
diff --git a/u-boot/board/eltec/bab7xx/Makefile b/u-boot/board/eltec/bab7xx/Makefile
new file mode 100644
index 0000000..b22160f
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
+
+SOBJS	= asm_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eltec/bab7xx/asm_init.S b/u-boot/board/eltec/bab7xx/asm_init.S
new file mode 100644
index 0000000..a85fb8b
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/asm_init.S
@@ -0,0 +1,1476 @@
+/*
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * ELTEC BAB PPC RAM initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+#include <mpc106.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+/*
+ * This following contains the entry code for the initialization code
+ * for the MPC 106, a PCI Bridge/Memory Controller.
+ * Register usage:
+ * r0  = ramtest scratch register, toggleError loop counter
+ * r1  = 0xfec0 0cf8 CONFIG_ADDRESS
+ * r2  = 0xfee0 0cfc CONFIG_DATA
+ * r3  = scratch register, subroutine argument and return value, ramtest size
+ * r4  = scratch register, spdRead clock mask, OutHex loop count
+ * r5  = ramtest scratch register
+ * r6  = toggleError 1st value, spdRead port mask
+ * r7  = toggleError 2nd value, ramtest scratch register,
+ *       spdRead scratch register (0x00)
+ * r8  = ramtest scratch register, spdRead scratch register (0x80)
+ * r9  = ramtest scratch register, toggleError loop end, OutHex digit
+ * r10 = ramtest scratch register, spdWriteByte parameter,
+ *        spdReadByte return value, printf pointer to COM1
+ * r11 = startType
+ * r12 = ramtest scratch register, spdRead data mask
+ * r13 = pointer to message block
+ * r14 = pointer to GOT
+ * r15 = scratch register, SPD save
+ * r16 = bank0 size, total memory size
+ * r17 = bank1 size
+ * r18 = bank2 size
+ * r19 = bank3 size
+ * r20 = MCCR1, MSAR1
+ * r21 = MCCR3, MEAR1
+ * r22 = MCCR4, MBER
+ * r23 = EMSAR1
+ * r24 = EMEAR1
+ * r25 = save link register 1st level
+ * r26 = save link register 2nd level
+ * r27 = save link register 3rd level
+ * r30 = pointer to GPIO for spdRead
+ */
+
+
+.globl board_asm_init
+board_asm_init:
+/*
+ * setup pointer to message block
+ */
+    mflr    r25             /* save away link register */
+    bl      get_lnk_reg     /* r3=addr of next instruction */
+    subi    r4, r3, 8       /* r4=board_asm_init addr */
+    addi    r13, r4, (MessageBlock-board_asm_init)
+/*
+ * dcache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, HID0_DCE
+    andc    r3, r3, r4
+    mr      r2, r3
+    ori     r3, r3, HID0_DCI
+    sync
+    mtspr   HID0, r3
+    mtspr   HID0, r2
+    isync
+    sync
+/*
+ * icache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, 0
+    ori     r4, r4, HID0_ICE
+    andc    r3, r3, r4
+    sync
+    mtspr   HID0, r3
+/*
+ * invalidate caches
+ */
+    ori     r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
+    or      r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    andc    r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    isync
+/*
+ * icache_enable
+ */
+    mfspr   r3, HID0
+    ori     r3, r3, (HID0_ICE | HID0_ICFI)
+    sync
+    mtspr   HID0, r3
+
+    lis     r1, 0xfec0
+    ori     r1, r1, 0x0cf8
+    lis     r2, 0xfee0
+    ori     r2, r2, 0xcfc
+
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
+/*
+ * Switch to address map A if necessary.
+ */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR1
+    stwbrx  r3, 0, r1
+    sync
+    lwbrx   r4, 0, r2
+    sync
+    lis     r0, PICR1_XIO_MODE@h
+    ori     r0, r0, PICR1_XIO_MODE@l
+    andc    r4, r4, r0
+    lis     r0, PICR1_ADDRESS_MAP@h
+    ori     r0, r0, PICR1_ADDRESS_MAP@l
+    or      r4, r4, r0
+    stwbrx  r4, 0, r2
+    sync
+#endif
+
+/*
+ * Do the init for the SIO.
+ */
+    bl      .sioInit
+
+    addi    r3, r13, (MinitLogo-MessageBlock)
+    bl      Printf
+
+    addi    r3, r13, (Mspd01-MessageBlock)
+    bl      Printf
+/*
+ * Memory cofiguration using SPD information stored on the SODIMMs
+ */
+    li      r17, 0
+    li      r18, 0
+    li      r19, 0
+
+    li      r3, 0x0002          /* get RAM type from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     noSpdError
+
+    addi    r3, r13, (Mfail-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x00
+    b       toggleError         /* fail - loop forever */
+
+noSpdError:
+    mr      r15, r3             /* save r3 */
+
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+
+    cmpli   0, 0, r15, 0x0001   /* FPM ? */
+    beq     configFPM
+    cmpli   0, 0, r15, 0x0002   /* EDO ? */
+    beq     configEDO
+    cmpli   0, 0, r15, 0x0004   /* SDRAM ? */
+    beq     configSDRAM
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x01
+    b       toggleError         /* fail - loop forever */
+
+configSDRAM:
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+/*
+ * set the Memory Configuration Reg. 1
+ */
+    li      r3, 0x001f          /* get bank size from spd bank0/1 */
+    bl      spdRead
+
+    andi.   r3, r3, 0x0038
+    beq     SD16MB2B
+
+    li      r3, 0x0011          /* get number of internal banks */
+				/* from spd for bank0/1 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     SD64MB2B
+
+    cmpli   0, 0, r3, 0x04
+    beq     SD64MB4B
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x02
+    b       toggleError         /* fail - loop forever */
+
+SD64MB2B:
+    li      r20, 0x0005         /* 64-Mbit SDRAM 2 banks */
+    b       SDRow2nd
+
+SD64MB4B:
+    li      r20, 0x0000         /* 64-Mbit SDRAM 4 banks */
+    b       SDRow2nd
+
+SD16MB2B:
+    li      r20, 0x000f         /* 16-Mbit SDRAM 2 banks */
+
+SDRow2nd:
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0004
+    bne     S2D64MB4B           /* bank2/3 isn't present or no SDRAM */
+
+    li      r3, 0x011f          /* get bank size from spd bank2/3 */
+    bl      spdRead
+
+    andi.   r3, r3, 0x0038
+    beq     S2D16MB2B
+/*
+ * set the Memory Configuration Reg. 2
+ */
+    li      r3, 0x0111          /* get number of internal banks */
+				/* from spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     S2D64MB2B
+
+    cmpli   0, 0, r3, 0x04
+    beq     S2D64MB4B
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x03
+    b       toggleError         /* fail - loop forever */
+
+S2D64MB2B:
+    ori     r20, r20, 0x0050    /* 64-Mbit SDRAM 2 banks */
+    b       S2D64MB4B
+
+S2D16MB2B:
+    ori     r20, r20, 0x00f0    /* 16-Mbit SDRAM 2 banks */
+
+/*
+ * set the Memory Configuration Reg. 3
+ */
+S2D64MB4B:
+    lis     r21, 0x8630         /* BSTOPRE = 0x80, REFREC = 6, */
+				/* RDLAT = 3 */
+
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r22, 0x2430         /* PRETOACT = 2, ACTOPRE = 4, */
+				/* WCBUF = 1, RCBUF = 1 */
+    ori     r22, r22, 0x2220    /* SDMODE = 0x022, ACTORW = 2 */
+
+/*
+ * get the size of bank 0-3
+ */
+    li      r3, 0x001f          /* get bank size from spd bank0/1 */
+    bl      spdRead
+
+    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte */
+				/* (128 MB max.) */
+
+    li      r3, 0x0005          /* get number of banks from spd */
+				/* for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank1
+
+    mr      r17, r16
+
+SDRAMnobank1:
+    addi    r3, r13, (Mspd23-MessageBlock)
+    bl      Printf
+
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0001    /* FPM ? */
+    bne     noFPM23             /* handle as EDO */
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noFPM23:
+    cmpli   0, 0, r3, 0x0002    /* EDO ? */
+    bne     noEDO23
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noEDO23:
+    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
+    bne    noSDRAM23
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+    b       configSDRAM23
+noSDRAM23:
+    addi    r3, r13, (Mna-MessageBlock)
+    bl      Printf
+    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */
+
+configSDRAM23:
+    li      r3, 0x011f          /* get bank size from spd bank2/3 */
+    bl      spdRead
+
+    rlwinm  r18, r3, 2, 24, 29  /* calculate size in MByte */
+				/* (128 MB max.) */
+
+    li      r3, 0x0105          /* get number of banks from */
+				/* spd bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank3
+
+    mr    r19, r18
+
+SDRAMnobank3:
+    b       configRAMcommon
+
+configFPM:
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       configEDO0
+/*
+ * set the Memory Configuration Reg. 1
+ */
+configEDO:
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+configEDO0:
+    lis     r20, MCCR1_TYPE_EDO@h
+
+getSpdRowBank01:
+    li      r3, 0x0003          /* get number of row bits from */
+				/* spd from bank0/1 */
+    bl      spdRead
+    ori     r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS)
+    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS)
+    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS)
+    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS)
+    cmpli   0, 0, r3, 0x000c    /* bank0 -  12 row bits */
+    beq     getSpdRowBank23
+
+    cmpli   0, 0, r3, 0x000d    /* bank0 -  13 row bits */
+    beq     getSpdRowBank23
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x10
+    b       toggleError         /* fail - loop forever */
+
+getSpdRowBank23:
+    li     r3, 0x0103           /* get number of row bits from */
+				/* spd for bank2/3 */
+    bl      spdRead
+
+    ori     r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS)
+    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS)
+    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS)
+    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS)
+
+/*
+ * set the Memory Configuration Reg. 3
+ */
+writeRowBits:
+    lis     r21, 0x000a         /* CPX = 1, RAS6P = 4 */
+    ori     r21, r21, 0x2293    /* CAS5 = 2, CP4 = 1, */
+				/* CAS3 = 2, RCD2 = 2, RP = 3 */
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r22, 0x0010         /* all SDRAM parameter 0, */
+				/* WCBUF flow through, */
+				/* RCBUF registered */
+/*
+ * get the size of bank 0-3
+ */
+    li      r3, 0x0003          /* get row bits from spd  bank0/1 */
+    bl      spdRead
+
+    li      r16, 0              /* bank size is: */
+				/* (8*2^row*2^column)/0x100000 MB */
+    ori     r16, r16, 0x8000
+    rlwnm   r16, r16, r3, 0, 31
+
+    li      r3, 0x0004          /* get column bits from spd bank0/1 */
+    bl      spdRead
+
+    rlwnm   r16, r16, r3, 0, 31
+
+    li      r3, 0x0005          /* get number of banks from */
+				/* spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     EDOnobank1
+
+    mr      r17, r16
+
+EDOnobank1:
+    addi    r3, r13, (Mspd23-MessageBlock)
+    bl      Printf
+
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0001    /* FPM ? */
+    bne     noFPM231            /* handle as EDO */
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       EDObank2
+noFPM231:
+    cmpli   0, 0, r3, 0x0002    /* EDO ? */
+    bne     noEDO231
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+    b       EDObank2
+noEDO231:
+    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
+    bne     noSDRAM231
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noSDRAM231:
+    addi    r3, r13, (Mfail-MessageBlock)
+    bl      Printf
+    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */
+
+EDObank2:
+    li      r3, 0x0103          /* get row bits from spd for bank2/3 */
+    bl      spdRead
+
+    li      r18, 0              /* bank size is: */
+				/* (8*2^row*2^column)/0x100000 MB */
+    ori     r18, r18, 0x8000
+    rlwnm   r18, r18, r3, 0, 31
+
+    li      r3, 0x0104          /* get column bits from spd bank2/3 */
+    bl      spdRead
+
+    rlwnm   r18, r18, r3, 0, 31
+
+    li      r3, 0x0105          /* get number of banks from */
+				/* spd for bank2/3 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     configRAMcommon
+
+    mr      r19, r18
+
+configRAMcommon:
+    lis     r1, MPC106_REG_ADDR@h
+    ori     r1, r1, MPC106_REG_ADDR@l
+    lis     r2, MPC106_REG_DATA@h
+    ori     r2, r2, MPC106_REG_DATA@l
+
+    li      r0, 0
+
+/*
+ * If we are already running in RAM (debug mode), we should
+ * NOT reset the MEMGO flag. Otherwise we will stop all memory
+ * accesses.
+ */
+#ifdef IN_RAM
+    lis     r4, MCCR1_MEMGO@h
+    ori     r4, r4, MCCR1_MEMGO@l
+    or      r20, r20, r4
+#endif
+
+/*
+ * set the Memory Configuration Reg. 1
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR1    /* register number 0xf0 */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx  r20, r0, r2             /* write data to CONFIG_DATA */
+/*
+ * set the Memory Configuration Reg. 3
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR3    /* register number 0xf8 */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx    r21, r0, r2           /* write data to CONFIG_DATA */
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR4    /* register number 0xfc */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx  r22, r0, r2             /* write data to CONFIG_DATA */
+/*
+ * set the memory boundary registers for bank 0-3
+ */
+    li      r20, 0
+    li      r23, 0
+    li      r24, 0
+    subi    r21, r16, 1         /* calculate end address bank0 */
+    li      r22, (MBER_BANK0)
+
+    cmpi    0, 0, r17, 0        /* bank1 present ? */
+    beq     nobank1
+
+    rlwinm  r3, r16, 8, 16, 23  /* calculate start address of bank1 */
+    or      r20, r20, r3
+    add     r16, r16, r17       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank1 */
+    rlwinm  r3, r3, 8, 16, 23
+    or      r21, r21, r3
+    ori     r22, r22, (MBER_BANK1)      /* enable bank1 */
+    b       bank2
+
+nobank1:
+    ori     r23, r23, 0x0300    /* set bank1 start to unused area */
+    ori     r24, r24, 0x0300    /* set bank1 end to unused area */
+
+bank2:
+    cmpi    0, 0, r18, 0        /* bank2 present ? */
+    beq     nobank2
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank2 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 16, 8, 15
+    or      r20, r20, r3
+    rlwinm  r3, r4, 8, 8, 15
+    or      r23, r23, r3
+    add     r16, r16, r18       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank2 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 16, 8, 15
+    or      r21, r21, r3
+    rlwinm  r3, r4, 8, 8, 15
+    or      r24, r24, r3
+    ori     r22, r22, (MBER_BANK2)    /* enable bank2 */
+    b       bank3
+
+nobank2:
+    lis     r3, 0x0003
+    or      r23, r23, r3        /* set bank2 start to unused area */
+    or      r24, r24, r3        /* set bank2 end to unused area */
+
+bank3:
+    cmpi    0, 0, r19, 0        /* bank3 present ? */
+    beq     nobank3
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank3 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 24, 0, 7
+    or      r20, r20, r3
+    rlwinm  r3, r4, 16, 0, 7
+    or      r23, r23, r3
+    add     r16, r16, r19       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank3 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 24, 0, 7
+    or      r21, r21, r3
+    rlwinm  r3, r4, 16, 0, 7
+    or      r24, r24, r3
+    ori     r22, r22, (MBER_BANK3)    /* enable bank3 */
+    b       writebound
+
+nobank3:
+    lis     r3, 0x0300
+    or      r23, r23, r3        /* set bank3 start to unused area */
+    or      r24, r24, r3        /* set bank3 end to unused area */
+
+writebound:
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MSAR1    /* register number 0x80 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r20, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MEAR1    /* register number 0x90 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r21, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMSAR1    /* register number 0x88 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r23, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMEAR1    /* register number 0x98 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r24, r0, r2         /* write data to CONFIG_DATA */
+
+/*
+ * set boundaries of unused banks to unused address space
+ */
+    lis     r4, 0x0303
+    ori     r4, r4, 0x0303      /* bank 4-7 start and end adresses */
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMSAR2    /* register number 0x8C */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMEAR2    /* register number 0x9C */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+/*
+ * set the Memory Configuration Reg. 2
+ */
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR2    /* register number 0xf4 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+
+    li      r3, 0x000c          /* get refresh from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     common1
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x20
+    b       toggleError         /* fail - loop forever */
+
+common1:
+    andi.   r15, r3, 0x007f     /* mask selfrefresh bit */
+    li      r3, 0x010c          /* get refresh from spd for bank2/3 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    beq     common2
+    andi.   r3, r3, 0x007f      /* mask selfrefresh bit */
+    cmp     0, 0, r3, r15       /* find the lower */
+    blt     common3
+
+common2:
+    mr      r3, r15
+
+common3:
+    li      r4, 0x1010          /* refesh cycle 1028 clocks */
+				/*  left shifted 2 */
+    cmpli   0, 0, r3, 0x0000    /* 15.6 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x0808          /* refesh cycle 514 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0002    /* 7.8 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x2020          /* refesh cycle 2056 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0003    /* 31.3 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x4040          /* refesh cycle 4112 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0004    /* 62.5 us ? */
+    beq     writeRefresh
+
+    li      r4, 0
+    ori     r4, r4, 0x8080      /* refesh cycle 8224 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0005    /* 125 us ? */
+    beq     writeRefresh
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x21
+    b       toggleError         /* fail - loop forever */
+
+writeRefresh:
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+/*
+ * DRAM BANKS SHOULD BE ENABLED
+ */
+    addi    r3, r13, (Mactivate-MessageBlock)
+    bl      Printf
+    mr      r3, r16
+    bl      OutDec
+    addi    r3, r13, (Mmbyte-MessageBlock)
+    bl      Printf
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MBER /* register number 0xa0 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stb     r22, 0(r2)          /* write data to CONFIG_DATA */
+    li      r8, 0x63            /* PGMAX = 99 */
+    stb     r8, 3(r2)           /* write data to CONFIG_DATA */
+
+/*
+ *  DRAM SHOULD NOW BE CONFIGURED AND ENABLED
+ *  MUST WAIT 200us BEFORE ACCESSING
+ */
+    li      r0, 0x7800
+    mtctr   r0
+
+wait200us:
+    bdnz    wait200us
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR1    /* register number 0xf0 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+
+    lwbrx   r4, r0, r2          /* load r4 from CONFIG_DATA */
+
+    lis     r0, MCCR1_MEMGO@h   /* MEMGO=1 */
+    ori     r0, r0, MCCR1_MEMGO@l
+    or      r4, r4, r0          /* set the MEMGO bit */
+    stwbrx  r4, r0, r2          /* write mdfd data to CONFIG_DATA */
+
+    li      r0, 0x7000
+    mtctr   r0
+
+wait8ref:
+    bdnz    wait8ref
+
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+
+    mtlr    r25
+    blr
+
+/*
+ * Infinite loop called in case of an error during RAM initialisation.
+ * error codes in r6 and r7.
+ */
+toggleError:
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError1:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError1
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError2:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError2
+    b       toggleError
+
+
+/******************************************************************************
+ * This function performs a basic initialisation of the superio chip
+ * to enable basic console output and SPD access during RAM initialisation.
+ *
+ * Upon completion, SIO resource registers are mapped as follows:
+ * Resource     Enabled         Address
+ * UART1        Yes             3F8-3FF COM1
+ * UART2        Yes             2F8-2FF COM2
+ * GPIO         Yes             220-227
+ */
+.set    SIO_LUNINDEX, 0x07      /* SIO LUN index register */
+.set    SIO_CNFG1, 0x21         /* SIO configuration #1 register */
+.set    SIO_PCSCI, 0x23         /* SIO PCS configuration index reg */
+.set    SIO_PCSCD, 0x24         /* SIO PCS configuration data reg */
+.set    SIO_ACTIVATE, 0x30      /* SIO activate register */
+.set    SIO_IOBASEHI, 0x60      /* SIO I/O port base address, 15:8 */
+.set    SIO_IOBASELO, 0x61      /* SIO I/O port base address, 7:0 */
+.set    SIO_LUNENABLE, 0x01     /* SIO LUN enable */
+
+.sioInit:
+    mfspr   r7, 8               /* save link register */
+
+.sioInit_87308:
+
+/*
+ * Get base addr of ISA I/O space
+ */
+    lis     r6, CONFIG_SYS_ISA_IO@h
+    ori     r6, r6, CONFIG_SYS_ISA_IO@l
+
+/*
+ * Set offset to base address for config registers.
+ */
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
+    addi    r4, r0, 0x0279
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
+    addi    r4, r0, 0x015C
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
+    addi    r4, r0, 0x002E
+#endif
+    add     r6, r6, r4          /* add offset to base */
+    or      r3, r6, r6          /* make a copy */
+
+/*
+ * PMC (LUN 8)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select PMC LUN */
+    addi    r5, r0, 0x8
+    bl      .sio_bw
+    addi    r4, r0, SIO_IOBASEHI    /* initialize PMC address to 0x460 */
+    addi    r5, r0, 0x04
+    bl      .sio_bw
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0x60
+    bl      .sio_bw
+    addi    r4, r0, SIO_ACTIVATE    /* enable PMC */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+    lis     r8, CONFIG_SYS_ISA_IO@h
+    ori     r8, r8, 0x0460
+    li      r9, 0x03
+    stb     r9, 0(r8)               /* select PMC2 register */
+    eieio
+    li      r9, 0x00
+    stb     r9, 1(r8)               /* SuperI/O clock src: 24MHz via X1 */
+    eieio
+
+/*
+ * map UART1 (LUN 6) or UART2 (LUN 5) to COM1 (0x3F8)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select COM1 LUN */
+    addi    r5, r0, 0x6
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASEHI    /* initialize COM1 address to 0x3F8 */
+    addi    r5, r0, 0x03
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0xF8
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_ACTIVATE    /* enable COM1 */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+/*
+ * Init COM1 for polled output
+ */
+    lis     r8, CONFIG_SYS_ISA_IO@h
+    ori     r8, r8, 0x03f8
+    li      r9, 0x00
+    stb     r9, 1(r8)           /* int disabled */
+    eieio
+    li      r9, 0x00
+    stb     r9, 4(r8)           /* modem ctrl */
+    eieio
+    li      r9, 0x80
+    stb     r9, 3(r8)           /* link ctrl, bank select */
+    eieio
+    li      r9, 115200/CONFIG_BAUDRATE
+    stb     r9, 0(r8)           /* baud rate (LSB)*/
+    eieio
+    rotrwi  r9, r9, 8
+    stb     r9, 1(r8)           /* baud rate (MSB) */
+    eieio
+    li      r9, 0x03
+    stb     r9, 3(r8)           /* 8 data bits, 1 stop bit, */
+				/* no parity */
+    eieio
+    li      r9, 0x0b
+    stb     r9, 4(r8)           /* enable the receiver and transmitter */
+    eieio
+
+waitEmpty:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty
+    li      r9, 0x47
+    stb     r9, 3(r8)           /* send break, 8 data bits, */
+				/* 2 stop bits, no parity */
+    eieio
+
+    lis     r0, 0x0001
+    mtctr   r0
+
+waitCOM1:
+    lwz     r0, 5(r8)           /* load from port for delay */
+    bdnz    waitCOM1
+
+waitEmpty1:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty1
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bits, */
+				/* no parity */
+    eieio
+
+/*
+ * GPIO (LUN 7)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select GPIO LUN */
+    addi    r5, r0, 0x7
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASEHI    /* initialize GPIO address to 0x220 */
+    addi    r5, r0, 0x02
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0x20
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_ACTIVATE    /* enable GPIO */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+.sioInit_done:
+
+/*
+ * Get base addr of ISA I/O space
+ */
+    lis     r3, CONFIG_SYS_ISA_IO@h
+    ori     r3, r3, CONFIG_SYS_ISA_IO@l
+
+    addi    r3, r3, 0x015C      /* adjust to superI/O 87308 base */
+    or      r6, r3, r3          /* make a copy */
+/*
+ * CS0
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x01
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x76
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x02
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x40
+    bl      .sio_bw
+/*
+ * CS1
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x05
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x05
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x70
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x06
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x1C
+    bl      .sio_bw
+/*
+ * CS2
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x08
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x09
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x71
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x0A
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x1C
+    bl      .sio_bw
+
+    mtspr   8, r7               /* restore link register */
+    bclr    20, 0               /* return to caller */
+
+/*
+ * this function writes a register to the SIO chip
+ */
+.sio_bw:
+    stb     r4, 0(r3)           /* write index register with register offset */
+    eieio
+    sync
+    stb     r5, 1(r3)           /* 1st write */
+    eieio
+    sync
+    stb     r5, 1(r3)           /* 2nd write */
+    eieio
+    sync
+    bclr    20, 0               /* return to caller */
+/*
+ * this function reads a register from the SIO chip
+ */
+.sio_br:
+    stb     r4, 0(r3)           /* write index register with register offset */
+    eieio
+    sync
+    lbz     r3, 1(r3)           /* retrieve specified reg offset contents */
+    eieio
+    sync
+    bclr    20, 0               /* return to caller */
+
+/*
+ * Print a message to COM1 in polling mode
+ * r10=COM1 port, r3=(char*)string
+ */
+.globl Printf
+Printf:
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+WaitChr:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, WaitChr        /* wait till empty */
+    lbzx    r0, r0, r3          /* get char */
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addi    r3, r3, 1           /* next char */
+    lbzx    r0, r0, r3          /* get char */
+    cmpwi   cr1, r0, 0          /* end of string ? */
+    bne     cr1, WaitChr
+    blr
+
+/*
+ * Print 8/4/2 digits hex value to COM1 in polling mode
+ * r10=COM1 port, r3=val
+ */
+OutHex2:
+    li      r9, 4               /* shift reg for 2 digits */
+    b       OHstart
+OutHex4:
+    li      r9, 12              /* shift reg for 4 digits */
+    b       OHstart
+    .globl OutHex
+OutHex:
+    li      r9, 28              /* shift reg for 8 digits */
+OHstart:
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+OutDig:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDig
+    sraw    r0, r3, r9
+    clrlwi  r0, r0, 28
+    cmpwi   cr1, r0, 9
+    ble     cr1, digIsNum
+    addic   r0, r0, 55
+    b       nextDig
+digIsNum:
+    addic   r0, r0, 48
+nextDig:
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addic.  r9, r9, -4
+    bge     OutDig
+    blr
+/*
+ * Print 3 digits hdec value to COM1 in polling mode
+ * r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch
+ */
+.globl OutDec
+OutDec:
+    li      r6, 10
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r9 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r9, r10, r3
+
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r8 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r8, r10, r3
+
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r7, r10, r3
+
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+    or.     r7, r7, r7
+    bne     noblank1
+    li      r3, 0x20
+    b       OutDec4
+
+noblank1:
+    addi    r3, r7, 48          /* convert to ASCII */
+
+OutDec4:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec4
+    stb     r3, 0(r10)          /* x00 to transmit */
+    eieio
+
+    or.     r7, r7, r8
+    beq     OutDec5
+
+    addi    r3, r8, 48          /* convert to ASCII */
+OutDec5:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec5
+    stb     r3, 0(r10)          /* x0  to transmit */
+    eieio
+
+    addi    r3, r9, 48          /* convert to ASCII */
+OutDec6:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec6
+    stb     r3, 0(r10)          /* x   to transmit */
+    eieio
+    blr
+/*
+ * Print a char to COM1 in polling mode
+ * r10=COM1 port, r3=char
+ */
+.globl    OutChr
+OutChr:
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+OutChr1:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutChr1        /* wait till empty */
+    stb     r3, 0(r10)          /* write to transmit reg */
+    eieio
+    blr
+/*
+ * Input:  r3 adr to read
+ * Output: r3 val or -1 for error
+ */
+spdRead:
+    mfspr   r26, 8              /* save link register */
+
+    lis     r30, CONFIG_SYS_ISA_IO@h
+    ori     r30, r30, 0x220     /* GPIO Port 1 */
+    li      r7, 0x00
+    li      r8, 0x100
+    and.    r5, r3, r8
+    beq     spdbank0
+    li      r12, 0x08
+    li      r4, 0x10
+    li      r6, 0x18
+    b       spdRead1
+
+spdbank0:
+    li      r12, 0x20           /* set I2C data */
+    li      r4, 0x40            /* set I2C clock */
+    li      r6, 0x60            /* set I2C clock and data */
+
+spdRead1:
+    li      r8, 0x80
+
+    bl      spdStart            /* access I2C bus as master */
+    li      r10, 0xa0           /* write to SPD */
+    bl      spdWriteByte
+    bl      spdReadAck          /* ACK returns in r10 */
+    cmpw    cr0, r10, r7
+    bne     AckErr              /* r10 must be 0, if ACK received */
+    mr      r10, r3             /* adr to read */
+    bl      spdWriteByte
+    bl      spdReadAck
+    cmpw    cr0, r10, r7
+    bne     AckErr
+    bl      spdStart
+    li      r10, 0xa1           /* read from SPD */
+    bl      spdWriteByte
+    bl      spdReadAck
+    cmpw    cr0, r10, r7
+    bne     AckErr
+    bl      spdReadByte         /* return val in r10 */
+    bl      spdWriteAck
+    bl      spdStop             /* release I2C bus */
+    mr      r3, r10
+    mtspr   8, r26              /* restore link register */
+    blr
+/*
+ * ACK error occurred
+ */
+AckErr:
+    bl      spdStop
+    orc     r3, r0, r0          /* return -1 */
+    mtspr   8, r26              /* restore link register */
+    blr
+
+/*
+ * Routines to read from RAM spd.
+ * r30 - GPIO Port1 address in all cases.
+ * r4 - clock mask for SPD
+ * r6 - port mask for SPD
+ * r12 - data mask for SPD
+ */
+waitSpd:
+    li      r0, 0x1000
+    mtctr   r0
+wSpd:
+    bdnz    wSpd
+    bclr    20, 0               /* return to caller */
+
+/*
+ * establish START condition on I2C bus
+ */
+spdStart:
+    mfspr   r27, 8              /* save link register */
+    stb     r6, 0(r30)          /* set SDA and SCL */
+    eieio
+    stb     r6, 1(r30)          /* switch GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* reset SDA */
+    eieio
+    bl      waitSpd
+    stb     r7, 0(r30)          /* reset SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+/*
+ * establish STOP condition on I2C bus
+ */
+spdStop:
+    mfspr   r27, 8              /* save link register */
+    stb     r7, 0(r30)          /* reset SCL and SDA */
+    eieio
+    stb     r6, 1(r30)          /* switch GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    stb     r6, 0(r30)          /* set SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r7, 1(r30)          /* switch GPIO to input */
+    eieio
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+spdReadByte:
+    mfspr   r27, 8
+    stb     r4, 1(r30)          /* set GPIO for SCL output */
+    eieio
+    li      r9, 0x08
+    li      r10, 0x00
+loopRB:
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    lbz     r5, 0(r30)          /* read from GPIO Port1 */
+    rlwinm  r10, r10, 1, 0, 31
+    and.    r5, r5, r12
+    beq     clearBit
+    ori     r10, r10, 0x01      /* append _1_ */
+clearBit:
+    stb     r7, 0(r30)          /* reset SCL */
+    eieio
+    bl      waitSpd
+    addic.  r9, r9, -1
+    bne     loopRB
+    mtspr   8, r27
+    bclr    20, 0               /* return (r10) to caller */
+
+/*
+ * spdWriteByte writes bits 24 - 31 of r10 to I2C.
+ * r8 contains bit mask 0x80
+ */
+spdWriteByte:
+    mfspr   r27, 8              /* save link register */
+    li      r9, 0x08            /* write octet */
+    and.    r5, r10, r8
+    bne     sWB1
+    stb     r7, 0(r30)          /* set SDA to _0_ */
+    eieio
+    b       sWB2
+sWB1:
+    stb     r12, 0(r30)         /* set SDA to _1_ */
+    eieio
+sWB2:
+    stb     r6, 1(r30)          /* set GPIO to output */
+    eieio
+loopWB:
+    and.    r5, r10, r8
+    bne     sWB3
+    stb     r7, 0(r30)          /* set SDA to _0_ */
+    eieio
+    b       sWB4
+sWB3:
+    stb     r12, 0(r30)         /* set SDA to _1_ */
+    eieio
+sWB4:
+    bl      waitSpd
+    and.    r5, r10, r8
+    bne     sWB5
+    stb     r4, 0(r30)          /* set SDA to _0_ and SCL */
+    eieio
+    b       sWB6
+sWB5:
+    stb     r6, 0(r30)          /* set SDA to _1_ and SCL */
+    eieio
+sWB6:
+    bl      waitSpd
+    and.    r5, r10, r8
+    bne     sWB7
+    stb     r7, 0(r30)          /* set SDA to _0_ and reset SCL */
+    eieio
+    b       sWB8
+sWB7:
+    stb     r12, 0(r30)         /* set SDA to _1_ and reset SCL */
+    eieio
+sWB8:
+    bl      waitSpd
+    rlwinm  r10, r10, 1, 0, 31  /* next bit */
+    addic.  r9, r9, -1
+    bne     loopWB
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+/*
+ * Read ACK from SPD, return value in r10
+ */
+spdReadAck:
+    mfspr   r27, 8              /* save link register */
+    stb     r4, 1(r30)          /* set GPIO to output */
+    eieio
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    lbz     r10, 0(r30)         /* read GPIO Port 1 and mask SDA */
+    and     r10, r10, r12
+    bl      waitSpd
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return (r10) to caller */
+
+spdWriteAck:
+    mfspr   r27, 8
+    stb     r12, 0(r30)         /* set SCL */
+    eieio
+    stb     r6, 1(r30)          /* set GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r6, 0(r30)          /* SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r12, 0(r30)         /* reset SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+get_lnk_reg:
+    mflr    r3                  /* return link reg */
+    blr
+
+/*
+ * Messages for console output
+ */
+.globl MessageBlock
+MessageBlock:
+Mok:
+    .ascii  "OK\015\012\000"
+Mfail:
+    .ascii  "FAILED\015\012\000"
+Mna:
+    .ascii  "NA\015\012\000"
+MinitLogo:
+    .ascii  "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
+    .ascii  "\015\012Initialising RAM\015\012\000"
+Mspd01:
+    .ascii  "       Reading SPD of bank0/1 ..... \000"
+Mspd23:
+    .ascii  "       Reading SPD of bank2/3 ..... \000"
+MfpmRam:
+    .ascii  "       RAM-Type: FPM \015\012\000"
+MedoRam:
+    .ascii  "       RAM-Type: EDO \015\012\000"
+MsdRam:
+    .ascii  "       RAM-Type: SDRAM \015\012\000"
+Mactivate:
+    .ascii  "       Activating \000"
+Mmbyte:
+    .ascii  " MB .......... \000"
+    .align  4
diff --git a/u-boot/board/eltec/bab7xx/bab7xx.c b/u-boot/board/eltec/bab7xx/bab7xx.c
new file mode 100644
index 0000000..ea4897b
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/bab7xx.c
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc106.h>
+#include <mk48t59.h>
+#include <74xx_7xx.h>
+#include <ns87308.h>
+#include <video_fb.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*---------------------------------------------------------------------------*/
+/*
+ * Get Bus clock frequency
+ */
+ulong bab7xx_get_bus_freq (void)
+{
+	/*
+	 * The GPIO Port 1 on BAB7xx reflects the bus speed.
+	 */
+	volatile struct GPIO *gpio =
+		(struct GPIO *) (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_GPIO_BASE);
+
+	unsigned char data = gpio->dta1;
+
+	if (data & 0x02)
+		return 66666666;
+
+	return 83333333;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz)
+ */
+ulong bab7xx_get_gclk_freq (void)
+{
+	static const int pllratio_to_factor[] = {
+		00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
+			00,
+	};
+
+	return pllratio_to_factor[get_hid1 () >> 28] *
+		(bab7xx_get_bus_freq () / 10);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int checkcpu (void)
+{
+	uint pvr = get_pvr ();
+
+	printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
+	printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
+		bab7xx_get_bus_freq () / 1000000);
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkboard (void)
+{
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
+	puts ("Board: ELTEC BAB7xx PReP\n");
+#else
+	puts ("Board: ELTEC BAB7xx CHRP\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("2 MB ## Test not implemented yet ##\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static unsigned int mpc106_read_cfg_dword (unsigned int reg)
+{
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+
+	out32r (MPC106_REG_ADDR, reg_addr);
+
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int dram_size (int board_type)
+{
+	/* No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in ram_init.S.
+	 */
+
+	register unsigned long i, msar1, mear1, memSize;
+
+#if defined(CONFIG_SYS_MEMTEST)
+	register unsigned long reg;
+
+	printf ("Testing DRAM\n");
+
+	/* write each mem addr with it's address */
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
+		*reg = reg;
+
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
+#endif
+
+	/*
+	 * Since MPC106 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
+
+	do {
+		if (i & 0x01)	/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);
+
+	return (memSize * 0x100000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	return dram_size (board_type);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void after_reloc (ulong dest_addr)
+{
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *) gd, dest_addr);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * do_reset is done here because in this case it is board specific, since the
+ * 7xx CPUs can only be reset by external HW (the RTC in this case).
+ */
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#if defined(CONFIG_RTC_MK48T59)
+	/* trigger watchdog immediately */
+	rtc_set_watchdog (1, RTC_WD_RB_16TH);
+#else
+#error "You must define the macro CONFIG_RTC_MK48T59."
+#endif
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+/*
+ * Since the 7xx CPUs don't have an internal watchdog, this function is
+ * board specific.  We use the RTC here.
+ */
+void watchdog_reset (void)
+{
+#if defined(CONFIG_RTC_MK48T59)
+	/* we use a 32 sec watchdog timer */
+	rtc_set_watchdog (8, RTC_WD_RB_4);
+#else
+#error "You must define the macro CONFIG_RTC_MK48T59."
+#endif
+}
+#endif /* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
+			 (get_pvr () >> 8) & 0xFF,
+			 get_pvr () & 0xFF,
+			 bab7xx_get_gclk_freq () / 1000000,
+			 bab7xx_get_bus_freq () / 1000000);
+		return;
+	case 2:
+		sprintf (info,
+			 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
+			 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/eltec/bab7xx/dc_srom.c b/u-boot/board/eltec/bab7xx/dc_srom.c
new file mode 100644
index 0000000..a44af6e
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/dc_srom.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SRom I/O routines.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "srom.h"
+
+#define SROM_RD         0x00004000    /* Read from Boot ROM */
+#define SROM_WR         0x00002000    /* Write to Boot ROM */
+#define SROM_SR         0x00000800    /* Select Serial ROM when set */
+
+#define DT_IN           0x00000004    /* Serial Data In */
+#define DT_CLK          0x00000002    /* Serial ROM Clock */
+#define DT_CS           0x00000001    /* Serial ROM Chip Select */
+
+static u_int         dc_srom_iobase;
+
+/*----------------------------------------------------------------------------*/
+
+static int inl(u_long addr)
+{
+    return le32_to_cpu(*(volatile u_long *)(addr));
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void outl (int command, u_long addr)
+{
+    *(volatile u_long *)(addr) = cpu_to_le32(command);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void sendto_srom(u_int command, u_long addr)
+{
+    outl(command, addr);
+    udelay(1);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int getfrom_srom(u_long addr)
+{
+    s32 tmp;
+
+    tmp = inl(addr);
+    udelay(1);
+
+    return tmp;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_latch (u_int command, u_long addr)
+{
+    sendto_srom (command, addr);
+    sendto_srom (command | DT_CLK, addr);
+    sendto_srom (command, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_command_rd (u_int command, u_long addr)
+{
+    srom_latch (command, addr);
+    srom_latch (command, addr);
+    srom_latch ((command & 0x0000ff00) | DT_CS, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_command_wr (u_int command, u_long addr)
+{
+    srom_latch (command, addr);
+    srom_latch ((command & 0x0000ff00) | DT_CS, addr);
+    srom_latch (command, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_address(u_int command, u_long addr, u_char offset)
+{
+    int i;
+    signed char a;
+
+    a = (char)(offset << 2);
+    for (i=0; i<6; i++, a <<= 1)
+    {
+	srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
+    }
+    udelay(1);
+
+    i = (getfrom_srom(addr) >> 3) & 0x01;
+
+    return;
+}
+/*----------------------------------------------------------------------------*/
+
+static short srom_data_rd (u_int command, u_long addr)
+{
+    int i;
+    short word = 0;
+    s32 tmp;
+
+    for (i=0; i<16; i++)
+    {
+	sendto_srom(command  | DT_CLK, addr);
+	tmp = getfrom_srom(addr);
+	sendto_srom(command, addr);
+
+	word = (word << 1) | ((tmp >> 3) & 0x01);
+    }
+
+    sendto_srom(command & 0x0000ff00, addr);
+
+    return word;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int srom_data_wr (u_int command, u_long addr, short val)
+{
+    int i;
+    u_long longVal;
+    s32 tmp;
+
+    longVal = (u_long)(le16_to_cpu(val));
+
+    for (i=0; i<16; i++)
+    {
+	tmp = (longVal & 0x8000)>>13;
+
+	sendto_srom (tmp | command, addr);
+	sendto_srom (tmp | command  | DT_CLK, addr);
+	sendto_srom (tmp | command, addr);
+
+	longVal = longVal<<1;
+    }
+
+    sendto_srom(command & 0x0000ff00, addr);
+    sendto_srom(command, addr);
+
+    tmp = 100;
+    do
+    {
+	if ((getfrom_srom(dc_srom_iobase) & 0x8) == 0x8)
+	    break;
+	udelay(1000);
+    } while (--tmp);
+
+    if (tmp == 0)
+    {
+	printf("Write DEC21143 SRom timed out !\n");
+	return (-1);
+    }
+
+    return 0;
+}
+
+
+/*----------------------------------------------------------------------------*/
+static short srom_rd (u_long addr, u_char offset)
+{
+    sendto_srom (SROM_RD | SROM_SR, addr);
+    srom_latch (SROM_RD | SROM_SR | DT_CS, addr);
+
+    srom_command_rd (SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
+
+    srom_address (SROM_RD | SROM_SR | DT_CS, addr, offset);
+
+    return srom_data_rd (SROM_RD | SROM_SR | DT_CS, addr);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_wr_enable (u_long addr)
+{
+    int i;
+
+    sendto_srom (SROM_WR | SROM_SR, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    for (i=0; i<6; i++)
+    {
+	srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int srom_wr (u_long addr, u_char offset, short val)
+{
+    srom_wr_enable (addr);
+
+    sendto_srom (SROM_WR | SROM_SR, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    srom_command_wr (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+
+    srom_address (SROM_WR | SROM_SR | DT_CS, addr, offset);
+
+    return srom_data_wr (SROM_WR | SROM_SR | DT_CS, addr, val);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * load data from the srom
+ */
+int dc_srom_load (u_short *dest)
+{
+    int offset;
+    short tmp;
+
+    /* get srom iobase from local network controller */
+    pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
+    dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+    dc_srom_iobase  = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
+    dc_srom_iobase += 0x48;            /* io offset for srom access */
+
+    memset (dest, 0, 128);
+    for (offset=0; offset<64; offset++)
+    {
+	tmp = srom_rd (dc_srom_iobase, offset);
+	*dest++ = le16_to_cpu(tmp);
+    }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * store data into the srom
+ */
+int dc_srom_store (u_short *src)
+{
+    int offset;
+
+    /* get srom iobase from local network controller */
+    pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
+    dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+    dc_srom_iobase  = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
+    dc_srom_iobase += 0x48;            /* io offset for srom access */
+
+    for (offset=0; offset<64; offset++)
+    {
+	if (srom_wr (dc_srom_iobase, offset, *src) == -1)
+		return (-1);
+	src++;
+    }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/bab7xx/el_srom.c b/u-boot/board/eltec/bab7xx/el_srom.c
new file mode 100644
index 0000000..73f8066
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/el_srom.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "srom.h"
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  START sequence
+ *        _ _________
+ *  SCLK  _>         \____
+ *        _ ____
+ *  SDIO  _>    \_________
+ *         :    :    :
+ */
+static void eepStart (void)
+{
+    out8(I2C_BUS_DAT, 0x60);     /* SCLK = high  SDIO = high */
+    out8(I2C_BUS_DIR, 0x60);     /* set output direction for SCLK/SDIO */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);     /* SCLK = high  SDIO = low */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x00);     /* SCLK = low   SDIO = low */
+    udelay(10);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  STOP sequence
+ *              _______
+ *  SCLK  _____/
+ *        _         ___
+ *  SDIO  _>_______/
+ *         :   :   :
+ */
+static void eepStop (void)
+{
+    out8(I2C_BUS_DAT, 0x00);      /* SCLK = low   SDIO = low */
+    out8(I2C_BUS_DIR, 0x60);      /* set output direction for SCLK/SDIO */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);      /* SCLK = high  SDIO = low */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x60);      /* SCLK = high  SDIO = high */
+    udelay(10);
+    out8(I2C_BUS_DIR, 0x00);      /* reset to input direction */
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Read one byte from EEPROM
+ *            ___     ___     ___     ___     ___     ___     ___     ___
+ *  SCLK  ___/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \
+ *        _________________________________________________________________
+ *  SDIO  >     ^       ^       ^       ^       ^       ^       ^       ^
+ *        :  :   :   :   :   :   :   :   :   :   :   :   :   :   :   :   :
+ */
+static unsigned char eepReadByte (void)
+{
+    register unsigned char buf = 0x00;
+    register int i;
+
+    out8(I2C_BUS_DIR, 0x40);
+
+    for (i = 0; i < 8; i++)
+    {
+	out8(I2C_BUS_DAT, 0x00);    /* SCLK = low   SDIO = high */
+	udelay(10);
+	out8(I2C_BUS_DAT, 0x40);    /* SCLK = high  SDIO = high */
+	udelay(15);
+	buf <<= 1;
+	buf = (in8(I2C_BUS_DAT) & 0x20) ? (buf | 0x01) : (buf & 0xFE);
+	out8(I2C_BUS_DAT, 0x00);    /* SCLK = low   SDIO = high */
+	udelay(10);
+    }
+    return(buf);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Write one byte to EEPROM
+ *           ___     ___     ___     ___     ___     ___     ___     ___
+ *  SCLK  __/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \__
+ *         _______ _______ _______ _______ _______ _______ _______ ________
+ *  SDIO  X_______X_______X_______X_______X_______X_______X_______X________
+ *      :   7   :   6   :   5   :   4   :   3   :   2   :   1   :   0
+ */
+static void eepWriteByte (register unsigned char buf)
+{
+    register int    i;
+
+    (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00);     /* SCLK = low   SDIO = data */
+    out8(I2C_BUS_DIR, 0x60);
+
+    for (i = 7; i >= 0; i--)
+    {
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low  SDIO=data */
+	udelay(10);
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK=high SDIO=data */
+	udelay(15);
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low  SDIO=data */
+	udelay(10);
+	buf <<= 1;
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Read data acknowledge of EEPROM
+ *             _______
+ *  SCLK  ____/       \___
+ *         _______________
+ *  SDIO  >
+ *        :   :   ^   :
+ */
+static int eepReadAck (void)
+{
+    int retval;
+
+    out8(I2C_BUS_DIR, 0x40);
+    out8(I2C_BUS_DAT, 0x00);            /* SCLK = low   SDIO = high */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);            /* SCLK = high  SDIO = high */
+    udelay(10);
+    retval = (in8(I2C_BUS_DAT) & 0x20) ? ERROR : 0;
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x00);            /* SCLK = low   SDIO = high */
+    udelay(10);
+
+    return(retval);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Write data acknowledge to EEPROM
+ *             _______
+ *  SCLK  ____/       \___
+ *
+ *  SDIO  >_______________
+ *        :   :       :
+ */
+static void eepWriteAck (unsigned char ack)
+{
+    ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low   SDIO = ack */
+    out8(I2C_BUS_DIR, 0x60);
+    udelay(10);
+    ack ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK = high  SDIO = ack */
+    udelay(15);
+    ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low   SDIO = ack */
+    udelay(10);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Read bytes from EEPROM
+ */
+int el_srom_load (addr, buf, cnt, device, block)
+unsigned char addr;
+unsigned char *buf;
+int cnt;
+unsigned char device;
+unsigned char block;
+{
+    register int i;
+
+    for (i=0;i<cnt;i++)
+    {
+	eepStart();
+	eepWriteByte(0xA0 | device | block);
+	if (eepReadAck() == ERROR)
+	{
+	   eepStop();
+	    return(ERROR);
+	}
+	eepWriteByte(addr++);
+	if (eepReadAck() == ERROR)
+	{
+	    eepStop();
+	    return(ERROR);
+	}
+	eepStart();
+
+	eepWriteByte(0xA1 | device | block);
+	if (eepReadAck() == ERROR)
+	{
+	    eepStop();
+	    return(ERROR);
+	}
+
+	*buf++ = eepReadByte();
+	eepWriteAck(1);
+	eepStop();
+
+	if ((addr == 0) && (i != (cnt-1)))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+		return(ERROR);
+	}
+    }
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *
+ * Write bytes to EEPROM
+ *
+ */
+int el_srom_store (addr, buf, cnt, device, block)
+unsigned char    addr, *buf, device, block;
+int        cnt;
+{
+    register int i, retVal;
+
+    for (i=0;i<cnt;i++)
+    {
+	retVal = ERROR;
+	do
+	{
+	    eepStart();
+	    eepWriteByte(0xA0 | device | block);
+	    if ((retVal = eepReadAck()) == ERROR)
+		eepStop();
+	} while (retVal == ERROR);
+
+	eepWriteByte(addr++);
+	if (eepReadAck() == ERROR)  return(ERROR);
+
+	if ((addr == 0) && (i != (cnt-1)))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    return(ERROR);
+	}
+
+	eepWriteByte(*buf++);
+	if (eepReadAck() == ERROR)
+	    return(ERROR);
+
+	eepStop();
+    }
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * calculate checksum for ELTEC revision srom
+ */
+unsigned long el_srom_checksum (ptr, size)
+register unsigned char *ptr;
+unsigned long size;
+{
+    u_long f, accu = 0;
+    u_int  i;
+    u_char byte;
+
+    for (; size; size--)
+    {
+	byte = *ptr++;
+	for (i = 8; i; i--)
+	{
+	    f =  ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
+	    accu >>= 1; accu ^= f;
+	    byte >>= 1;
+	}
+    }
+    return(accu);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/bab7xx/flash.c b/u-boot/board/eltec/bab7xx/flash.c
new file mode 100644
index 0000000..21ae098
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
+ *        fixed monitor protection part
+ *
+ * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
+ *        of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
+ *        any other.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*----------------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+    unsigned long size1, size2;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* initialise 1st flash */
+    size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+    if (flash_info[0].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size1, size1<<20);
+    }
+
+    /* initialise 2nd flash */
+    size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    if (flash_info[1].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size2, size2<<20);
+    }
+
+    /* monitor protection ON by default */
+    if (size1 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE0_PRELIM,
+		FLASH_BASE0_PRELIM+monitor_flash_len-1,
+		&flash_info[0]);
+    }
+    if (size2 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE1_PRELIM,
+		FLASH_BASE1_PRELIM+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+    if (size2 == 4*1024*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+
+    return (size1 + size2);
+}
+
+/*----------------------------------------------------------------------------*/
+
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	flash_init();
+    }
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_AMD:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    case AMD_ID_F032B:
+	printf ("AM29F032B (32 Mbit)\n");
+	break;
+   default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    if (info->size >= (1 << 20)) {
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+    } else {
+	printf ("  Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	* Check if whole sector is erased
+	*/
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++) {
+	    if (*flash++ != 0xffffffff) {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   ");
+    }
+    printf ("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+    volatile unsigned char *caddr = (unsigned char *)addr;
+
+#ifdef DEBUG
+    printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
+#endif
+
+    /* Write auto select command: read Manufacturer ID */
+    caddr[0] = 0xF0;   /* reset bank */
+    udelay(10);
+
+    eieio();
+    caddr[0x555] = 0xAA;
+    udelay(10);
+    caddr[0x2AA] = 0x55;
+    udelay(10);
+    caddr[0x555] = 0x90;
+
+    udelay(10);
+
+    vendor = caddr[0];
+    devid = caddr[1];
+
+#ifdef DEBUG
+    printf("Manufacturer: 0x%lx\n", vendor);
+#endif
+
+    vendor &= 0xff;
+    devid &= 0xff;
+
+    /* We accept only two AMD types */
+    switch (vendor) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+
+    switch (devid) {
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id |= AMD_ID_F040B;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F016D:
+	info->flash_id |= AMD_ID_F016D;
+	info->sector_count = 32;
+	info->size         = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F032B:
+	info->flash_id |= AMD_ID_F032B;
+	info->sector_count = 64;
+	info->size         = 0x00400000;
+	break;              /* => 4 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+#ifdef DEBUG
+    printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
+#endif
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	caddr = (volatile unsigned char *)(info->start[i]);
+	info->protect[i] = caddr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	caddr = (volatile unsigned char *)info->start[0];
+	caddr[0] = 0xF0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    int rc = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > FLASH_AMD_COMP)) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+	    if (info->flash_id & FLASH_MAN_SST) {
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+		udelay(30000);  /* wait 30 ms */
+	    }
+	    else
+		addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return rc;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*----------------------------------------------------------------------------*/
+/* Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/bab7xx/l2cache.c b/u-boot/board/eltec/bab7xx/l2cache.c
new file mode 100644
index 0000000..787704f
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/l2cache.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_SYS_L2_BAB7xx)
+
+#include <pci.h>
+#include <mpc106.h>
+#include <asm/processor.h>
+
+/* defines L2CR register for MPC750 */
+
+#define L2CR_E           0x80000000
+#define L2CR_256K        0x10000000
+#define L2CR_512K        0x20000000
+#define L2CR_1024K       0x30000000
+#define L2CR_I           0x00200000
+#define L2CR_SL          0x00008000
+#define L2CR_IP          0x00000001
+
+/*----------------------------------------------------------------------------*/
+
+static int dummy (int dummy)
+{
+    return (dummy+1);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int l2_cache_enable (int l2control)
+{
+    if (l2control)              /* BAB750 */
+    {
+	mtspr(SPRN_L2CR, l2control);
+	mtspr(SPRN_L2CR, (l2control | L2CR_I));
+	while (mfspr(SPRN_L2CR) & L2CR_IP)
+	    ;
+	mtspr(SPRN_L2CR, (l2control | L2CR_E));
+	return (0);
+    }
+    else /* BAB740 */
+    {
+	int picr1, picr2, mask;
+	int picr2CacheSize, cacheSize;
+	int *d;
+	int devbusfn;
+	u32 reg32;
+
+	devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
+				   PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
+	if (devbusfn == -1)
+	    return (-1);
+
+	pci_read_config_dword  (devbusfn, PCI_PICR2, &reg32);
+	reg32 &= ~PICR2_L2_EN;
+	pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
+
+	/* cache size */
+	if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04)
+	{
+	    /* cache size is 512 KB */
+	    picr2CacheSize = PICR2_L2_SIZE_512K;
+	    cacheSize = 0x80000;
+	}
+	else
+	{
+	    /* cache size is 256 KB */
+	    picr2CacheSize = PICR2_L2_SIZE_256K;
+	    cacheSize = 0x40000;
+	}
+
+	/* setup PICR1 */
+	mask =
+	~(PICR1_CF_BREAD_WS(1) |
+	  PICR1_CF_BREAD_WS(2) |
+	  PICR1_CF_CBA(0xff) |
+	  PICR1_CF_CACHE_1G |
+	  PICR1_CF_DPARK |
+	  PICR1_CF_APARK |
+	  PICR1_CF_L2_CACHE_MASK);
+
+	picr1 =
+	(PICR1_CF_CBA(0x3f) |
+	 PICR1_CF_CACHE_1G |
+	 PICR1_CF_APARK |
+	 PICR1_CF_DPARK |
+	 PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
+
+	pci_read_config_dword  (devbusfn, PCI_PICR1, &reg32);
+	reg32 &= mask;
+	reg32 |= picr1;
+	pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
+
+	/*
+	 * invalidate all L2 cache
+	 */
+	picr2 =
+	(PICR2_CF_INV_MODE |
+	 PICR2_CF_HIT_HIGH |
+	 PICR2_CF_MOD_HIGH |
+	 PICR2_CF_L2_HIT_DELAY(1) |
+	 PICR2_CF_APHASE_WS(1) |
+	 picr2CacheSize);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
+
+	/*
+	 * dummy transactions
+	 */
+	for (d=0; d<(int *)(2*cacheSize); d++)
+	    dummy(*d);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2,
+				(picr2 | PICR2_CF_FLUSH_L2));
+
+	/* setup PICR2 */
+	picr2 =
+	(PICR2_CF_FAST_CASTOUT |
+	 PICR2_CF_WDATA |
+	 PICR2_CF_ADDR_ONLY_DISABLE |
+	 PICR2_CF_HIT_HIGH |
+	 PICR2_CF_MOD_HIGH |
+	 PICR2_L2_UPDATE_EN |
+	 PICR2_L2_EN |
+	 PICR2_CF_APHASE_WS(1) |
+	 PICR2_CF_DATA_RAM_PBURST |
+	 PICR2_CF_L2_HIT_DELAY(1) |
+	 PICR2_CF_SNOOP_WS(2) |
+	 picr2CacheSize);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
+    }
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+
+#endif /* (CONFIG_SYS_L2_BAB7xx) */
diff --git a/u-boot/board/eltec/bab7xx/misc.c b/u-boot/board/eltec/bab7xx/misc.c
new file mode 100644
index 0000000..bc6eb40
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/misc.c
@@ -0,0 +1,547 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include <linux/ctype.h>
+#include <pci.h>
+#include <net.h>
+#include <mpc106.h>
+#include <w83c553f.h>
+#include "srom.h"
+
+/* imports  */
+extern char console_buffer[CONFIG_SYS_CBSIZE];
+extern int l2_cache_enable (int l2control);
+extern void *nvram_read (void *dest, const short src, size_t count);
+extern void nvram_write (short dest, const void *src, size_t count);
+
+/* globals */
+unsigned int ata_reset_time = 60;
+unsigned int scsi_reset_time = 10;
+unsigned int eltec_board;
+
+/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860
+ * values fixed after board identification
+ */
+unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875;
+unsigned int   scsi_max_scsi_id = 15;
+unsigned char  scsi_sym53c8xx_ccf = 0x13;
+
+/*----------------------------------------------------------------------------*/
+/*
+ * handle sroms on BAB740/750
+ * fix ether address
+ * L2 cache initialization
+ * ide dma control
+ */
+int misc_init_r (void)
+{
+    revinfo eerev;
+    char *ptr;
+    u_int  i, l, initSrom, copyNv;
+    char buf[256];
+    char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+	     0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+    pci_dev_t bdf;
+
+    char sromSYM[] = {
+#ifdef TULIP_BUG
+    /* 10BaseT, 100BaseTx no full duplex modes */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
+    0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8
+#endif
+    /* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
+    0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88,
+    0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80,
+    0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77
+    };
+
+    char sromMII[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00,
+    0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08,
+    0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78,
+    0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41
+    };
+
+    /*
+     * Check/Remake revision info
+     */
+    initSrom = 0;
+    copyNv   = 0;
+
+    /* read out current revision srom contens */
+    el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
+		SECOND_DEVICE, FIRST_BLOCK);
+
+    /* read out current nvram shadow image */
+    nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
+
+    if (strcmp (eerev.magic, "ELTEC") != 0)
+    {
+	/* srom is not initialized -> create a default revision info */
+	for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
+	    *ptr++ = 0x00;
+	strcpy(eerev.magic, "ELTEC");
+	eerev.revrev[0] = 1;
+	eerev.revrev[1] = 0;
+	eerev.size = 0x00E0;
+	eerev.category[0] = 0x01;
+
+	/* node id from dead e128 as default */
+	eerev.etheraddr[0] = 0x00;
+	eerev.etheraddr[1] = 0x00;
+	eerev.etheraddr[2] = 0x5B;
+	eerev.etheraddr[3] = 0x00;
+	eerev.etheraddr[4] = 0x2E;
+	eerev.etheraddr[5] = 0x4D;
+
+	/* cache config word for bab750 */
+	*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
+
+	initSrom = 1;  /* force dialog */
+	copyNv   = 1;  /* copy to nvram */
+    }
+
+    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CONFIG_SYS_SROM_SIZE) !=
+		el_srom_checksum((u_char*)buf, CONFIG_SYS_SROM_SIZE)))
+    {
+	printf ("Invalid revision info copy in nvram !\n");
+	printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+	printf ("  <r> to reenter revision info.\n");
+	printf ("=> ");
+	if (0 != readline (NULL))
+	{
+	    switch ((char)toupper(console_buffer[0]))
+	    {
+	    case 'C':
+		copyNv = 1;
+		break;
+	    case 'R':
+		copyNv = 1;
+		initSrom = 1;
+		break;
+	    }
+	}
+    }
+
+    if (initSrom)
+    {
+	memcpy (buf, &eerev.revision[0][0], 14);     /* save all revision info */
+	printf ("Enter revision number (0-9): %c  ", eerev.revision[0][0]);
+	if (0 != readline (NULL))
+	{
+	    eerev.revision[0][0] = (char)toupper(console_buffer[0]);
+	    memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
+	}
+
+	printf ("Enter revision character (A-Z): %c  ", eerev.revision[0][1]);
+	if (1 == readline (NULL))
+	{
+	    eerev.revision[0][1] = (char)toupper(console_buffer[0]);
+	}
+
+	printf ("Enter board name (V-XXXX-XXXX): %s  ", (char *)&eerev.board);
+	if (11 == readline (NULL))
+	{
+	    for (i=0; i<11; i++)
+		eerev.board[i] =  (char)toupper(console_buffer[i]);
+	    eerev.board[11] = '\0';
+	}
+
+	printf ("Enter serial number: %s ", (char *)&eerev.serial );
+	if (6 == readline (NULL))
+	{
+	    for (i=0; i<6; i++)
+		eerev.serial[i] = console_buffer[i];
+	    eerev.serial[6] = '\0';
+	}
+
+	printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
+	    eerev.etheraddr[0], eerev.etheraddr[1],
+	    eerev.etheraddr[2], eerev.etheraddr[3],
+	    eerev.etheraddr[4], eerev.etheraddr[5]);
+	if (12 == readline (NULL))
+	{
+	    for (i=0; i<12; i+=2)
+	    eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
+			       hex[toupper(console_buffer[i+1])-'0']);
+	}
+
+	l = strlen ((char *)&eerev.text);
+	printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
+	if (0 != readline (NULL))
+	{
+	    for (i = l; i<63; i++)
+		eerev.text[i] = console_buffer[i-l];
+	    eerev.text[63] = '\0';
+	}
+
+	if (strstr ((char *)&eerev.board, "75") != NULL)
+	    eltec_board = 750;
+	else
+	    eltec_board = 740;
+
+	if (eltec_board == 750)
+	{
+	    if (CPU_TYPE == CPU_TYPE_750)
+		*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
+		else
+		*(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH;
+
+	    printf("Enter L2Cache config word with leading zero (HEX): %08X  ",
+		    *(int*)&eerev.res[0] );
+	    if (0 != readline (NULL))
+	    {
+		for (i=0; i<7; i+=2)
+		{
+		    eerev.res[i>>1] =
+		    (char)(16*hex[toupper(console_buffer[i])-'0'] +
+		    hex[toupper(console_buffer[i+1])-'0']);
+		}
+	    }
+
+	    /* prepare network eeprom */
+	    sromMII[20] = eerev.etheraddr[0];
+	    sromMII[21] = eerev.etheraddr[1];
+	    sromMII[22] = eerev.etheraddr[2];
+	    sromMII[23] = eerev.etheraddr[3];
+	    sromMII[24] = eerev.etheraddr[4];
+	    sromMII[25] = eerev.etheraddr[5];
+	    printf("\nSRom:  Writing DEC21143 MII info .. ");
+
+	    if (dc_srom_store ((u_short *)sromMII) == -1)
+		printf("FAILED\n");
+	    else
+		printf("OK\n");
+	}
+
+	if (eltec_board == 740)
+	{
+	    *(int *)&eerev.res[0] = 0;
+	    sromSYM[20] = eerev.etheraddr[0];
+	    sromSYM[21] = eerev.etheraddr[1];
+	    sromSYM[22] = eerev.etheraddr[2];
+	    sromSYM[23] = eerev.etheraddr[3];
+	    sromSYM[24] = eerev.etheraddr[4];
+	    sromSYM[25] = eerev.etheraddr[5];
+	    printf("\nSRom:  Writing DEC21143 SYM info .. ");
+
+	    if (dc_srom_store ((u_short *)sromSYM) == -1)
+		printf("FAILED\n");
+	    else
+		printf("OK\n");
+	}
+
+	/* update CRC */
+	eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
+
+	/* write new values */
+	printf("\nSRom:  Writing revision info ...... ");
+	if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
+			    sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+	    printf("FAILED\n\n");
+	else
+	    printf("OK\n\n");
+
+	/* write new values as shadow image to nvram */
+	nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
+
+    } /*if (initSrom) */
+
+    /* copy current values as shadow image to nvram */
+    if (initSrom == 0 && copyNv == 1)
+	nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
+
+    /* update environment */
+    sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+	    eerev.etheraddr[0], eerev.etheraddr[1],
+	    eerev.etheraddr[2], eerev.etheraddr[3],
+	    eerev.etheraddr[4], eerev.etheraddr[5]);
+    setenv ("ethaddr", buf);
+
+    /* print actual board identification */
+    printf("Ident: %s  Ser %s  Rev %c%c\n",
+	    eerev.board, (char *)&eerev.serial,
+	    eerev.revision[0][0], eerev.revision[0][1]);
+
+    /* global board ident */
+    if (strstr ((char *)&eerev.board, "75") != NULL)
+	eltec_board = 750;
+    else
+	eltec_board = 740;
+
+   /*
+    * L2 cache configuration
+    */
+#if defined(CONFIG_SYS_L2_BAB7xx)
+    ptr = getenv("l2cache");
+    if (*ptr == '0')
+    {
+	printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board);
+    }
+    else
+    {
+	printf ("Cache: L2 activated on BAB%d\n", eltec_board);
+	l2_cache_enable(*(int*)&eerev.res[0]);
+    }
+#endif
+
+   /*
+    * Reconfig ata reset timeout from environment
+    */
+    if ((ptr = getenv ("ata_reset_time")) != NULL)
+    {
+	ata_reset_time = (int)simple_strtoul (ptr, NULL, 10);
+    }
+    else
+    {
+	sprintf (buf, "%d", ata_reset_time);
+	setenv ("ata_reset_time", buf);
+    }
+
+   /*
+    * Reconfig scsi reset timeout from environment
+    */
+    if ((ptr = getenv ("scsi_reset_time")) != NULL)
+    {
+	scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10);
+    }
+    else
+    {
+	sprintf (buf, "%d", scsi_reset_time);
+	setenv ("scsi_reset_time", buf);
+    }
+
+
+    if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0)
+    {
+	if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0)
+	{
+	    /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 MHz */
+	    scsi_dev_id = PCI_DEVICE_ID_NCR_53C860;
+	    scsi_max_scsi_id = 7;
+	    scsi_sym53c8xx_ccf = 0x15;
+	    pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0);
+	}
+
+	if ((ptr = getenv ("ide_dma_off")) != NULL)
+	{
+	    u_long dma_off = simple_strtoul (ptr, NULL, 10);
+	    /*
+	    * setup user defined registers
+	    * s.a. linux/drivers/ide/sl82c105.c
+	    */
+	    bdf |= PCI_BDF(0,0,1);            /* ide user reg at bdf function 1 */
+	    if (dma_off & 1)
+	    {
+		pci_write_config_byte (bdf, 0x46, 1);
+		printf("IDE:   DMA off flag set: Bus 0 : Dev 0\n");
+	    }
+	    if (dma_off & 2)
+	    {
+		pci_write_config_byte (bdf, 0x4a, 1);
+		printf("IDE:   DMA off flag set: Bus 0 : Dev 1\n");
+	    }
+	    if (dma_off & 4)
+	    {
+		pci_write_config_byte (bdf, 0x4e, 1);
+		printf("IDE:   DMA off flag set: Bus 1 : Dev 0\n");
+	    }
+	    if (dma_off & 8)
+	    {
+		pci_write_config_byte (bdf, 0x52, 1);
+		printf("IDE:   DMA off flag set: Bus 1 : Dev 1\n");
+	    }
+	}
+    }
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * BAB740 uses KENDIN KS8761 modem chip with not common setup values
+ */
+#ifdef CONFIG_TULIP_SELECT_MEDIA
+
+/* Register bits.
+ */
+#define BMR_SWR         0x00000001      /* Software Reset */
+#define STS_TS          0x00700000      /* Transmit Process State */
+#define STS_RS          0x000e0000      /* Receive Process State */
+#define OMR_ST          0x00002000      /* Start/Stop Transmission Command */
+#define OMR_SR          0x00000002      /* Start/Stop Receive */
+#define OMR_PS          0x00040000      /* Port Select */
+#define OMR_SDP         0x02000000      /* SD Polarity - MUST BE ASSERTED */
+#define OMR_PM          0x00000080      /* Pass All Multicast */
+#define OMR_PR          0x00000040      /* Promiscuous Mode */
+#define OMR_PCS         0x00800000      /* PCS Function */
+#define OMR_TTM         0x00400000      /* Transmit Threshold Mode */
+
+/* Ethernet chip registers.
+ */
+#define DE4X5_BMR       0x000           /* Bus Mode Register */
+#define DE4X5_TPD       0x008           /* Transmit Poll Demand Reg */
+#define DE4X5_RRBA      0x018           /* RX Ring Base Address Reg */
+#define DE4X5_TRBA      0x020           /* TX Ring Base Address Reg */
+#define DE4X5_STS       0x028           /* Status Register */
+#define DE4X5_OMR       0x030           /* Operation Mode Register */
+#define DE4X5_SISR      0x060           /* SIA Status Register */
+#define DE4X5_SICR      0x068           /* SIA Connectivity Register */
+#define DE4X5_TXRX      0x070           /* SIA Transmit and Receive Register */
+#define DE4X5_GPPR      0x078           /* General Purpose Port register */
+#define DE4X5_APROM      0x048          /* Ethernet Address PROM */
+
+/*----------------------------------------------------------------------------*/
+
+static int INL(struct eth_device* dev, u_long addr)
+{
+    return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void OUTL(struct eth_device* dev, int command, u_long addr)
+{
+    *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void media_reg_init (
+    struct eth_device* dev,
+    u32 csr14,
+    u32 csr15_dir,
+    u32 csr15_v0,
+    u32 csr15_v1,
+    u32 csr6 )
+{
+    OUTL(dev, 0, DE4X5_OMR);            /* CSR6  */
+    udelay(10 * 1000);
+    OUTL(dev, 0, DE4X5_SICR);           /* CSR13 */
+    OUTL(dev, 1, DE4X5_SICR);           /* CSR13 */
+    udelay(10 * 1000);
+    OUTL(dev, csr14, DE4X5_TXRX);       /* CSR14 */
+    OUTL(dev, csr15_dir, DE4X5_GPPR);   /* CSR15 */
+    OUTL(dev, csr15_v0,  DE4X5_GPPR);   /* CSR15 */
+    udelay(10 * 1000);
+    OUTL(dev, csr15_v1,  DE4X5_GPPR);   /* CSR15 */
+    OUTL(dev, 0x00000301, DE4X5_SISR);  /* CSR12 */
+    OUTL(dev, csr6, DE4X5_OMR);         /* CSR6 */
+}
+
+/*----------------------------------------------------------------------------*/
+
+void dc21x4x_select_media(struct eth_device* dev)
+{
+    int i, status, ext;
+    extern unsigned int eltec_board;
+
+    if (eltec_board == 740)
+    {
+	printf("SYM media select "); /* BAB740 */
+	/* start autoneg. with 10 mbit */
+	media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080);
+	ext = status = 0;
+	for (i=0; i<2000+ext; i++)
+	{
+	    status = INL(dev, DE4X5_SISR);
+	    udelay(1000);
+	    if (status & 0x2000) ext = 2000;
+	    if ((status & 0x7000) == 0x5000) break;
+	}
+
+	/* autoneg. ok -> 100MB FD */
+	if ((status & 0x0100f000) == 0x0100d000)
+	{
+	    media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280);
+	    printf("100baseTx-FD\n");
+	}
+	/* autoneg. ok -> 100MB HD */
+	else if ((status & 0x0080f000) == 0x0080d000)
+	{
+	    media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080);
+	    printf("100baseTx\n");
+	}
+	/* autoneg. ok -> 10MB FD */
+	else if ((status & 0x0040f000) == 0x0040d000)
+	{
+	    media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280);
+	    printf("10baseT-FD\n");
+	}
+	/* autoneg. fail -> 10MB HD */
+	else
+	{
+	    media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008,
+			(OMR_SDP | OMR_TTM | OMR_PM));
+	    printf("10baseT\n");
+	}
+    }
+    else
+    {
+	printf("MII media selected\n");                     /* BAB750 */
+	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);    /* CSR6 */
+    }
+}
+#endif /* CONFIG_TULIP_SELECT_MEDIA */
+
+/*---------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/bab7xx/pci.c b/u-boot/board/eltec/bab7xx/pci.c
new file mode 100644
index 0000000..38dd498
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/pci.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u32 reg32;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
+    /*
+    * Attention: pci_hose_phys_to_bus() failes in address compare,
+    * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
+    */
+	CONFIG_SYS_PCI_MEMORY_SIZE-1,
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, &reg32);
+    reg32 |= PICR2_CF_SNOOP_WS(3) |
+	     PICR2_CF_FLUSH_L2 |
+	     PICR2_CF_L2_HIT_DELAY(3) |
+	     PICR2_CF_APHASE_WS(3);
+    reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
+    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);
+
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+
+    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, &reg32);
+    reg32 |= PICR1_CF_CBA(63) |
+	     PICR1_CF_BREAD_WS(2) |
+	     PICR1_MCP_EN |
+	     PICR1_CF_DPARK |
+	     PICR1_PROC_TYPE_604 |
+	     PICR1_CF_LOOP_SNOOP |
+	     PICR1_CF_APARK;
+    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/u-boot/board/eltec/bab7xx/srom.h b/u-boot/board/eltec/bab7xx/srom.h
new file mode 100644
index 0000000..504b742
--- /dev/null
+++ b/u-boot/board/eltec/bab7xx/srom.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* common srom defs */
+#define FIRST_DEVICE            0x00
+#define SECOND_DEVICE           0x04
+#define FIRST_BLOCK             0x00
+#define SECOND_BLOCK            0x02
+#define BLOCK_SIZE              0x100
+#define ERROR                   (-1)
+
+#define CLK2P0TO1_1MB_PB_0P5DH  0x79000100
+#define CLK2P5TO1_1MB_PB_0P5DH  0x7B000100
+
+#define CPU_TYPE_740            0x08
+#define CPU_TYPE_750            0x08
+#define CPU_TYPE                ((get_pvr()>>16)&0xffff)
+
+#define ABS(x)                  ((x<0)?-x:x)
+#define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
+
+/* bab7xx ELTEC srom */
+#define I2C_BUS_DAT             (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CONFIG_SYS_ISA_IO + 0x221)
+
+/* srom at mpc107 */
+#define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
+#define MPC107_I2CFDR           (mpc107_eumb_addr + 0x3004)     /* freq divider */
+#define MPC107_I2CCR            (mpc107_eumb_addr + 0x3008)     /* control      */
+#define MPC107_I2CSR            (mpc107_eumb_addr + 0x300c)     /* status       */
+#define MPC107_I2CDR            (mpc107_eumb_addr + 0x3010)     /* data         */
+#define MPC107_I2C_TIMEOUT      10000000
+
+/* i82559 */
+#define EE_ADDR_BITS            6
+#define EE_SIZE                 0x40                            /* 0x40 words */
+#define EE_CHECKSUM             0xBABA
+
+/* dc21143 */
+#define DEC_SROM_SIZE           128
+
+
+/*
+ * structure of revision srom
+ */
+typedef struct  {
+    char    magic[8];           /* 000 - Magic number */
+    char    revrev[2];          /* 008 - Revision of structure */
+    unsigned short size;        /* 00A - Size of CRC area */
+    unsigned long  crc;         /* 00C - CRC */
+    char    board[16];          /* 010 - Board Revision information */
+    char    option[4][16];      /* 020 - Option Revision information */
+    char    serial[8];          /* 060 - Board serial number */
+    char    etheraddr[6];       /* 068 - Ethernet node addresse */
+    char    reserved[2];        /* 06E - Reserved */
+    char    revision[7][2];     /* 070 - Revision codes */
+    char    category[2];        /* 07E - Category codes */
+    char    text[64];           /* 080 - Text field */
+    char    res[64];            /* 0C0 - Reserved */
+} revinfo;
+
+unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
+int el_srom_load  (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+
+int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
+int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
+int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
+			   unsigned char offset, unsigned char val);
+int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
+		      unsigned char device, unsigned char block);
+int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
+		       unsigned char device, unsigned char block);
+
+int dc_srom_load (unsigned short *dest);
+int dc_srom_store (unsigned short *src);
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata);
+void eepro100_srom_load (unsigned short *destination);
+int  eepro100_srom_store (unsigned short *source);
diff --git a/u-boot/board/eltec/elppc/Makefile b/u-boot/board/eltec/elppc/Makefile
new file mode 100644
index 0000000..367239a
--- /dev/null
+++ b/u-boot/board/eltec/elppc/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
+
+SOBJS	= asm_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eltec/elppc/asm_init.S b/u-boot/board/eltec/elppc/asm_init.S
new file mode 100644
index 0000000..8cbe9d8
--- /dev/null
+++ b/u-boot/board/eltec/elppc/asm_init.S
@@ -0,0 +1,878 @@
+/*
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * ELTEC ELPPC RAM initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/processor.h>
+#include <version.h>
+#include <mpc106.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+.globl board_asm_init
+board_asm_init:
+
+/*
+ * setup pointer to message block
+ */
+    mflr    r13                 /* save away link register */
+    bl      get_lnk_reg         /* r3=addr of next instruction */
+    subi    r4, r3, 8           /* r4=board_asm_init addr */
+    addi    r29, r4, (MessageBlock-board_asm_init)
+
+/*
+ * dcache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, HID0_DCE
+    andc    r3, r3, r4
+    mr      r2, r3
+    ori     r3, r3, HID0_DCI
+    sync
+    mtspr   HID0, r3
+    mtspr   HID0, r2
+    isync
+    sync
+/*
+ * icache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, 0
+    ori     r4, r4, HID0_ICE
+    andc    r3, r3, r4
+    sync
+    mtspr   HID0, r3
+/*
+ * invalidate caches
+ */
+    ori     r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
+    or      r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    andc    r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    isync
+/*
+ * icache_enable
+ */
+    mfspr   r3, HID0
+    ori     r3, r3, (HID0_ICE | HID0_ICFI)
+    sync
+    mtspr   HID0, r3
+
+
+/*
+ * setup memory controller
+ */
+    lis     r1, MPC106_REG_ADDR@h
+    ori     r1, r1, MPC106_REG_ADDR@l
+    lis     r2, MPC106_REG_DATA@h
+    ori     r2, r2, MPC106_REG_DATA@l
+
+    /* Configure PICR1 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR1
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFF14
+    ori     r3, r3, 0x1CC8
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure PICR2 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR2
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0000
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure EUMBAR */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, 0x0078      /* offest of EUMBAR in PCI config space */
+    stwbrx  r3, 0, r1
+    lis     r3, MPC107_EUMB_ADDR@h
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure Address Map B Option Reg */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, 0x00e0      /* offest of AMBOR in PCI config space */
+    stwbrx  r3, 0, r1
+    lis     r3, 0
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure I2C Controller */
+    lis     r14, MPC107_I2C_ADDR@h  /* base of I2C controller */
+    ori     r14, r14, MPC107_I2C_ADDR@l
+    lis     r3, 0x2b10          /* I2C clock = 100MHz/1024 */
+    stw     r3, 4(r14)
+    li      r3, 0               /* clear arbitration */
+    eieio
+    stw     r3, 12(r14)
+
+    /* Configure MCCR1 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR1
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0660      /* don't set MEMGO now ! */
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure MCCR2 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR2
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0400
+    ori     r3, r3, 0x1800
+    eieio
+    stwbrx  r3, 0, r2
+
+
+    /* Configure MCCR3 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR3
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0230
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure MCCR4 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR4
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x2532
+    ori     r3, r3, 0x2220
+    eieio
+    stwbrx  r3, 0, r2
+
+/*
+ * configure memory interface (MICRs)
+ */
+    addis   r3, r0, 0x8000      /* ADDR_80 */
+    ori     r3, r3, 0x0080      /* SMEMADD1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0x4000
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_84 */
+    ori     r3, r3, 0x0084      /* SMEMADD2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0xFFFF
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_88 */
+    ori     r3, r3, 0x0088      /* EXTSMEM1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_8C */
+    ori     r3, r3, 0x008c      /* EXTSMEM2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0303
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_90 */
+    ori     r3, r3, 0x0090      /* EMEMADD1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0x7F3F
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_94 */
+    ori     r3, r3, 0x0094      /* EMEMADD2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0xFFFF
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_98 */
+    ori     r3, r3, 0x0098      /* EXTEMEM1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_9C */
+    ori     r3, r3, 0x009c      /* EXTEMEM2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0303
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_A0 */
+    ori     r3, r3, 0x00a0      /* MEMBNKEN */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0000
+    ori     r3, r3, 0x0003
+    eieio
+    stwbrx  r3, 0, r2
+
+/*
+ * must wait at least 100us after HRESET to issue a MEMGO
+ */
+    lis     r0, 1
+    mtctr   r0
+memStartWait:
+    bdnz    memStartWait
+
+/*
+ * enable RAM Operations through MCCR1 (MEMGO)
+ */
+    lis     r3, 0x8000
+    ori     r3, r3, 0x00f0
+    stwbrx  r3, r0, r1
+    sync
+    lwbrx   r3, 0, r2
+    lis     r0, 0x0008
+    or      r3, r0, r3
+    stwbrx  r3, 0, r2
+    sync
+
+/*
+ * set LEDs first time
+ */
+    li      r3, 0x1
+    lis     r30, CONFIG_SYS_USR_LED_BASE@h
+    stb     r3, 2(r30)
+    sync
+
+/*
+ * init COM1 for polled output
+ */
+    lis     r8, CONFIG_SYS_NS16550_COM1@h  /* COM1 base address*/
+    ori     r8, r8, CONFIG_SYS_NS16550_COM1@l
+    li      r9, 0x00
+    stb     r9, 1(r8)           /* int disabled */
+    eieio
+    li      r9, 0x00
+    stb     r9, 4(r8)           /* modem ctrl */
+    eieio
+    li      r9, 0x80
+    stb     r9, 3(r8)           /* link ctrl */
+    eieio
+    li      r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE)
+    stb     r9, 0(r8)           /* baud rate (LSB)*/
+    eieio
+    li      r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
+    stb     r9, 1(r8)           /* baud rate (MSB) */
+    eieio
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bit, no parity */
+    eieio
+    li      r9, 0x0b
+    stb     r9, 4(r8)           /* enable the receiver and transmitter (modem ctrl) */
+    eieio
+waitEmpty:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty
+    li      r9, 0x47
+    stb     r9, 3(r8)           /* send break, 8 data bits, 2 stop bit, no parity */
+    eieio
+
+    lis     r0, 0x0001
+    mtctr   r0
+waitCOM1:
+    lwz     r0, 5(r8)           /* load from port for delay */
+    bdnz    waitCOM1
+
+waitEmpty1:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty1
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bit, no parity */
+    eieio
+
+/*
+ * intro message from message block
+ */
+    addi    r3, r29, (MnewLine-MessageBlock)
+    bl      Printf
+    addi    r3, r29, (MinitLogo-MessageBlock)
+    bl      Printf
+
+/*
+ * memory cofiguration using SPD information stored on the SODIMMs
+ */
+    addi    r3, r29, (Mspd01-MessageBlock)
+    bl      Printf
+
+    li      r17, 0
+
+    li      r3, 0x0002          /* get RAM type from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     noSpdError
+
+    addi    r3, r29, (Mfail-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xe             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+
+noSpdError:
+    mr      r15, r3             /* save r3 */
+
+    addi    r3, r29, (Mok-MessageBlock)
+    bl      Printf
+
+    cmpli   0, 0, r15, 0x0004   /* SDRAM ? */
+    beq     isSDRAM
+
+    addi    r3, r29, (MramTyp-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xd             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+
+isSDRAM:
+    li      r3, 0x0012          /* get supported CAS latencies from byte 18 */
+    bl      spdRead
+    mr      r15, r3
+    li      r3, 0x09
+    andi.   r0, r15, 0x04
+    bne     maxCLis3
+    li      r3, 0x17
+maxCLis3:
+    andi.   r0, r15, 0x02
+    bne     CL2
+
+    addi    r3, r29, (MramTyp-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xc             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+CL2:
+    bl      spdRead
+    cmpli   0, 0, r3, 0xa1      /* cycle time must be 10ns max. */
+    blt     speedOk
+
+    addi    r3, r29, (MramTyp-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xb             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+speedOk:
+    lis     r20, 0x06e8         /* preset MCR1 value */
+
+    li      r3, 0x0011          /* get number of internal banks from spd for bank0/1 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     SD_2B
+    cmpli   0, 0, r3, 0x04
+    beq     SD_4B
+memConfErr:
+    addi    r3, r29, (MramConfErr-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xa             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+
+SD_2B:
+    li      r3, 0x0003          /* get number of row bits from spd for bank0/1 */
+    bl      spdRead
+    cmpli   0, 0, r3, 0x0b
+    beq     row11x2
+    cmpli   0, 0, r3, 0x0c
+    beq     row12x2or13x2
+    cmpli   0, 0, r3, 0x0d
+    beq     row12x2or13x2
+    b       memConfErr
+SD_4B:
+    li      r3, 0x0003          /* get number of row bits from spd for bank0/1 */
+    bl      spdRead
+    cmpli   0, 0, r3, 0x0b
+    beq     row11x4or12x4
+    cmpli   0, 0, r3, 0x0c
+    beq     row11x4or12x4
+    cmpli   0, 0, r3, 0x0d
+    beq     row13x4
+    b       memConfErr
+row12x2or13x2:
+    ori     r20, r20, 0x05
+    b       row11x4or12x4
+row13x4:
+    ori     r20, r20, 0x0a
+    b       row11x4or12x4
+row11x2:
+    ori     r20, r20, 0x0f
+row11x4or12x4:
+    /* get the size of bank 0-1 */
+
+    li      r3, 0x001f          /* get bank size from spd for bank0/1 */
+    bl      spdRead
+
+    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte (128 MB max.) */
+
+    li      r3, 0x0005          /* get number of banks from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank1
+
+    mr      r17, r16
+
+SDRAMnobank1:
+    li      r3, 0x000c          /* get refresh from spd for bank0/1 */
+    bl      spdRead
+    andi.   r3, r3, 0x007f      /* mask selfrefresh bit */
+    li      r4, 0x1800          /* refesh cycle 1536 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0000    /* 15.6 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x0c00          /* refesh cycle 768 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0002    /* 7.8 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x3000          /* refesh cycle 3072 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0003    /* 31.3 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x6000          /* refesh cycle 6144 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0004    /* 62.5 us ? */
+    beq     writeRefresh
+
+    li      r4, 0
+    ori     r4, r4, 0xc000      /* refesh cycle 8224 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0005    /* 125 us ? */
+    beq     writeRefresh
+
+    b       memConfErr
+
+writeRefresh:
+    lis     r21, 0x0400         /* preset MCCR2 value */
+    or      r21, r21, r4
+
+    /* Overwrite MCCR1 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR1
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r20, 0, r2
+
+    /* Overwrite MCCR2 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR2
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r21, 0, r2
+
+    /* set the memory boundary registers for bank 0-3 */
+    li      r20, 0
+    lis     r23, 0x0303
+    lis     r24, 0x0303
+    subi    r21, r16, 1         /* calculate end address bank0 */
+    li      r22, 1
+
+    cmpi    0, 0, r17, 0        /* bank1 present ? */
+    beq     nobank1
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank1 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 8, 16, 23
+    or      r20, r20, r3
+    or      r23, r23, r4
+
+    add     r16, r16, r17       /* add to total memory size */
+
+    subi    r3, r16, 1          /* calculate end address of bank1 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 8, 16, 23
+    or      r21, r21, r3
+    or      r24, r24, r4
+
+    ori     r22, r22, 2         /* enable bank1 */
+    b       bankOk
+nobank1:
+    ori     r23, r23, 0x0300    /* set bank1 start to unused area */
+    ori     r24, r24, 0x0300    /* set bank1 end to unused area */
+bankOk:
+    addi    r3, r29, (Mactivate-MessageBlock)
+    bl      Printf
+    mr      r3, r16
+    bl      OutDec
+    addi    r3, r29, (Mact0123e-MessageBlock)
+    bl      Printf
+
+/*
+ * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1
+ */
+    addis   r3, r0, 0x8000      /* ADDR_80 */
+    ori     r3, r3, 0x0080      /* MSAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r20, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_88 */
+    ori     r3, r3, 0x0088      /* EMSAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r23, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_90 */
+    ori     r3, r3, 0x0090      /* MEAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r21, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_98 */
+    ori     r3, r3, 0x0098      /* EMEAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r24, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_A0 */
+    ori     r3, r3, 0x00a0      /* MBER */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r22, 0, r2
+
+/*
+ * delay to let SDRAM go through several initialization/refresh cycles
+ */
+    lis     r3, 3
+    mtctr   r3
+memStartWait_1:
+    bdnz    memStartWait_1
+    eieio
+
+/*
+ * set LEDs end
+ */
+    li      r3, 0xf
+    lis     r30, CONFIG_SYS_USR_LED_BASE@h
+    stb     r3, 2(r30)
+    sync
+
+    mtlr    r13
+    blr                         /* EXIT board_asm_init ... */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string)
+ */
+
+Printf:
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
+WaitChr:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, WaitChr        /* wait till empty */
+    lbzx    r0, r0, r3          /* get char */
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addi    r3, r3, 1           /* next char */
+    lbzx    r0, r0, r3          /* get char */
+    cmpwi   cr1, r0, 0          /* end of string ? */
+    bne     cr1, WaitChr
+    blr
+
+/*
+ * print a char to COM1 in polling mode (r10=COM1 port, r3=char)
+ */
+OutChr:
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
+OutChr1:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutChr1        /* wait till empty */
+    stb     r3, 0(r10)          /* write to transmit reg */
+    eieio
+    blr
+
+/*
+ * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val)
+ */
+OutHex2:
+    li      r9, 4               /* shift reg for 2 digits */
+    b       OHstart
+OutHex4:
+    li      r9, 12              /* shift reg for 4 digits */
+    b       OHstart
+OutHex:
+    li      r9, 28              /* shift reg for 8 digits */
+OHstart:
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
+OutDig:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDig
+    sraw    r0, r3, r9
+    clrlwi  r0, r0, 28
+    cmpwi   cr1, r0, 9
+    ble     cr1, digIsNum
+    addic   r0, r0, 55
+    b       nextDig
+digIsNum:
+    addic   r0, r0, 48
+nextDig:
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addic.  r9, r9, -4
+    bge     OutDig
+    blr
+
+/*
+ * print 3 digits hdec value to COM1 in polling mode
+ * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch)
+ */
+OutDec:
+    li      r6, 10
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r9 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r9, r10, r3
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r8 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r8, r10, r3
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r7, r10, r3
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
+    or.     r7, r7, r7
+    bne     noblank1
+    li      r3, 0x20
+    b       OutDec4
+noblank1:
+    addi    r3, r7, 48          /* convert to ASCII */
+OutDec4:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec4
+    stb     r3, 0(r10)          /* x00 to transmit */
+    eieio
+    or.     r7, r7, r8
+    beq     OutDec5
+    addi    r3, r8, 48          /* convert to ASCII */
+OutDec5:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec5
+    stb     r3, 0(r10)          /* x0  to transmit */
+    eieio
+    addi    r3, r9, 48          /* convert to ASCII */
+OutDec6:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec6
+    stb     r3, 0(r10)          /* x   to transmit */
+    eieio
+    blr
+
+/*
+ * hang endless loop
+ */
+toggleError:                    /* fail type in r6, r7=0xff, toggle LEDs */
+    stb     r7, 2(r30)          /* r7 to LED */
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError1:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError1
+    stb     r6, 2(r30)          /* r6 to LED */
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError2:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError2
+    b       toggleError
+
+/*
+ * routines to read from ram spd
+ */
+spdWaitIdle:
+    lis     r0, 0x1             /* timeout for about 100us */
+    mtctr   r0
+iSpd:
+    lbz     r10, 12(r14)
+    andi.   r10, r10, 0x20      /* mask and test MBB */
+    beq     idle
+    bdnz    iSpd
+    orc.    r10, r0, r0         /* return -1 to caller */
+idle:
+    bclr    20, 0               /* return to caller */
+
+waitSpd:
+    lis     r0, 0x10            /* timeout for about 1.5ms */
+    mtctr   r0
+wSpd:
+    lbz     r10, 12(r14)
+    andi.   r10, r10, 0x82
+    cmpli   0, 0, r10, 0x82     /* test MCF and MIF set */
+    beq     wend
+    bdnz    wSpd
+    orc.    r10, r0, r0         /* return -1 to caller */
+    bclr    20, 0               /* return to caller */
+
+wend:
+    li      r10, 0
+    stb     r10, 12(r14)        /* clear status */
+    bclr    20, 0               /* return to caller */
+
+/*
+ * spdread
+ * in:  r3 adr to read
+ * out: r3 val or -1 for error
+ * uses r10, assumes that r14 points to I2C controller
+ */
+spdRead:
+    mfspr   r25, 8              /* save link register */
+
+    bl      spdWaitIdle
+    bne     spdErr
+
+    li      r10, 0x80           /* start with MEN */
+    stb     r10, 8(r14)
+    eieio
+
+    li      r10, 0xb0           /* start as master */
+    stb     r10, 8(r14)
+    eieio
+
+    li      r10, 0xa0           /* write device 0xA0 */
+    stb     r10, 16(r14)
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+    lbz     r10, 12(r14)        /* test ACK */
+    andi.   r10, r10, 0x01
+    bne     gotNoAck
+
+    stb     r3, 16(r14)         /* data address */
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+
+    li      r10, 0xb4           /* switch to read - restart */
+    stb     r10, 8(r14)
+    eieio
+
+    li      r10, 0xa1           /* read device 0xA0 */
+    stb     r10, 16(r14)
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+    li      r10, 0xa8           /* no ACK */
+    stb     r10, 8(r14)
+    eieio
+
+    lbz     r10, 16(r14)        /* trigger read next byte */
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+    li      r10, 0x88           /* generate STOP condition */
+    stb     r10, 8(r14)
+    eieio
+
+    lbz     r3, 16(r14)         /* return read byte */
+
+    mtspr   8, r25              /* restore link register */
+    blr
+
+gotNoAck:
+    li      r10, 0x80           /* generate STOP condition */
+    stb     r10, 8(r14)
+    eieio
+spdErr:
+    orc     r3, r0, r0          /* return -1 */
+    mtspr   8, r25              /* restore link register */
+    blr
+
+get_lnk_reg:
+    mflr    r3                  /* return link reg */
+    blr
+
+MessageBlock:
+
+MinitLogo:
+    .ascii  "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
+    .ascii  "\015\012Initialising RAM\015\012\000"
+Mspd01:
+    .ascii  "       Reading SPD of SODIMM ...... \000"
+MramTyp:
+    .ascii  "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000"
+MramConfErr:
+    .ascii  "\015\012\Unsupported SODIMM Configuration!\015\012\000"
+Mactivate:
+    .ascii  "       Activating \000"
+Mact0123e:
+    .ascii  " MByte.\015\012\000"
+Mok:
+    .ascii  "OK \015\012\000"
+Mfail:
+    .ascii  "FAILED \015\012\000"
+MnewLine:
+    .ascii  "\015\012\000"
+    .align 4
diff --git a/u-boot/board/eltec/elppc/eepro100_srom.c b/u-boot/board/eltec/elppc/eepro100_srom.c
new file mode 100644
index 0000000..4a9da54
--- /dev/null
+++ b/u-boot/board/eltec/elppc/eepro100_srom.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Local network srom writing for first time run
+ */
+
+/* includes */
+#include <common.h>
+#include <pci.h>
+#include <net.h>
+#include "srom.h"
+
+extern int eepro100_write_eeprom (struct eth_device *dev,
+				  int location, int addr_len,
+				  unsigned short data);
+
+/*----------------------------------------------------------------------------*/
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata)
+{
+	unsigned short sum = 0;
+	unsigned int i;
+
+	for (i = 0; i < (EE_SIZE - 1); i++) {
+		sum += sromdata[i];
+	}
+	return (EE_CHECKSUM - sum);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int eepro100_srom_store (unsigned short *source)
+{
+	int count;
+	struct eth_device onboard_dev;
+
+	/* get onboard network iobase */
+	pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0,
+			       (unsigned int *) &onboard_dev.iobase);
+	onboard_dev.iobase &= ~0xf;
+
+	source[63] = eepro100_srom_checksum (source);
+
+	for (count = 0; count < EE_SIZE; count++) {
+		if (eepro100_write_eeprom ((struct eth_device *) &onboard_dev,
+					   count, EE_ADDR_BITS,
+					   SROM_SHORT (source)) == -1) {
+			return -1;
+		}
+		source++;
+	}
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+#ifdef EEPRO100_SROM_CHECK
+
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
+
+void eepro100_srom_load (unsigned short *destination)
+{
+	int count;
+	struct eth_device onboard_dev;
+
+#ifdef DEBUG
+	int lr = 0;
+
+	printf ("eepro100_srom_download:\n");
+#endif
+
+	/* get onboard network iobase */
+	pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0,
+			       &onboard_dev.iobase);
+	onboard_dev.iobase &= ~0xf;
+
+	memset (destination, 0x65, 128);
+
+	for (count = 0; count < 0x40; count++) {
+		*destination++ = read_eeprom ((struct eth_device *) &onboard_dev,
+					      count, EE_ADDR_BITS);
+#ifdef DEBUG
+		printf ("%04x ", *(destination - 1));
+		if (lr++ == 7) {
+			printf ("\n");
+			lr = 0;
+		}
+#endif
+	}
+}
+#endif /* EEPRO100_SROM_CHECK */
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/elppc/elppc.c b/u-boot/board/eltec/elppc/elppc.c
new file mode 100644
index 0000000..cb9ab86
--- /dev/null
+++ b/u-boot/board/eltec/elppc/elppc.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc106.h>
+#include <video_fb.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int checkboard (void)
+{
+	puts ("Board: ELTEC PowerPC\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkflash (void)
+{
+	/* TODO */
+	printf ("Test not implemented !\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned int mpc106_read_cfg_dword (unsigned int reg)
+{
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+
+	out32r (MPC106_REG_ADDR, reg_addr);
+
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int dram_size (int board_type)
+{
+	/*
+	 * No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in asm_init.S.
+	 */
+
+	register unsigned long i, msar1, mear1, memSize;
+
+#if defined(CONFIG_SYS_MEMTEST)
+	register unsigned long reg;
+
+	printf ("Testing DRAM\n");
+
+	/* write each mem addr with it's address */
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
+		*reg = reg;
+
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
+#endif
+
+	/*
+	 * Since MPC107 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
+
+	do {
+		if (i & 0x01)			/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);
+
+	return (memSize * 0x100000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	return dram_size (board_type);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * The BAB 911 can be reset by writing bit 0 of the Processor Initialization
+ * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities
+ * Memory Block).
+ */
+int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	out8 (MPC107_EUMB_PI, 1);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+
+/*
+ * Since the 7xx CPUs don't have an internal watchdog, this function is
+ * board specific.
+ */
+void watchdog_reset (void)
+{
+}
+#endif							/* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+void after_reloc (ulong dest_addr)
+{
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *)gd, dest_addr);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %d / %d MHz",
+				 (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100);
+		return;
+	case 2:
+		sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH",
+				 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/eltec/elppc/flash.c b/u-boot/board/eltec/elppc/flash.c
new file mode 100644
index 0000000..21ae098
--- /dev/null
+++ b/u-boot/board/eltec/elppc/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
+ *        fixed monitor protection part
+ *
+ * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
+ *        of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
+ *        any other.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*----------------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+    unsigned long size1, size2;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* initialise 1st flash */
+    size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+    if (flash_info[0].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size1, size1<<20);
+    }
+
+    /* initialise 2nd flash */
+    size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    if (flash_info[1].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size2, size2<<20);
+    }
+
+    /* monitor protection ON by default */
+    if (size1 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE0_PRELIM,
+		FLASH_BASE0_PRELIM+monitor_flash_len-1,
+		&flash_info[0]);
+    }
+    if (size2 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE1_PRELIM,
+		FLASH_BASE1_PRELIM+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+    if (size2 == 4*1024*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+
+    return (size1 + size2);
+}
+
+/*----------------------------------------------------------------------------*/
+
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	flash_init();
+    }
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_AMD:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    case AMD_ID_F032B:
+	printf ("AM29F032B (32 Mbit)\n");
+	break;
+   default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    if (info->size >= (1 << 20)) {
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+    } else {
+	printf ("  Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	* Check if whole sector is erased
+	*/
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++) {
+	    if (*flash++ != 0xffffffff) {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   ");
+    }
+    printf ("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+    volatile unsigned char *caddr = (unsigned char *)addr;
+
+#ifdef DEBUG
+    printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
+#endif
+
+    /* Write auto select command: read Manufacturer ID */
+    caddr[0] = 0xF0;   /* reset bank */
+    udelay(10);
+
+    eieio();
+    caddr[0x555] = 0xAA;
+    udelay(10);
+    caddr[0x2AA] = 0x55;
+    udelay(10);
+    caddr[0x555] = 0x90;
+
+    udelay(10);
+
+    vendor = caddr[0];
+    devid = caddr[1];
+
+#ifdef DEBUG
+    printf("Manufacturer: 0x%lx\n", vendor);
+#endif
+
+    vendor &= 0xff;
+    devid &= 0xff;
+
+    /* We accept only two AMD types */
+    switch (vendor) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+
+    switch (devid) {
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id |= AMD_ID_F040B;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F016D:
+	info->flash_id |= AMD_ID_F016D;
+	info->sector_count = 32;
+	info->size         = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F032B:
+	info->flash_id |= AMD_ID_F032B;
+	info->sector_count = 64;
+	info->size         = 0x00400000;
+	break;              /* => 4 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+#ifdef DEBUG
+    printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
+#endif
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	caddr = (volatile unsigned char *)(info->start[i]);
+	info->protect[i] = caddr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	caddr = (volatile unsigned char *)info->start[0];
+	caddr[0] = 0xF0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    int rc = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > FLASH_AMD_COMP)) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+	    if (info->flash_id & FLASH_MAN_SST) {
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+		udelay(30000);  /* wait 30 ms */
+	    }
+	    else
+		addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return rc;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*----------------------------------------------------------------------------*/
+/* Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/elppc/misc.c b/u-boot/board/eltec/elppc/misc.c
new file mode 100644
index 0000000..cbaf10b
--- /dev/null
+++ b/u-boot/board/eltec/elppc/misc.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include <linux/ctype.h>
+#include <pci.h>
+#include <net.h>
+#include "srom.h"
+
+/* imports  */
+extern char console_buffer[CONFIG_SYS_CBSIZE];
+extern int l2_cache_enable (int l2control);
+extern int eepro100_write_eeprom (struct eth_device *dev, int location,
+				  int addr_len, unsigned short data);
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
+
+/*----------------------------------------------------------------------------*/
+/*
+ * read/write to nvram is only byte access
+ */
+void *nvram_read (void *dest, const long src, size_t count)
+{
+	uchar *d = (uchar *) dest;
+	uchar *s = (uchar *) (CONFIG_ENV_MAP_ADRS + src);
+
+	while (count--)
+		*d++ = *s++;
+
+	return dest;
+}
+
+void nvram_write (long dest, const void *src, size_t count)
+{
+	uchar *d = (uchar *) (CONFIG_ENV_MAP_ADRS + dest);
+	uchar *s = (uchar *) src;
+
+	while (count--)
+		*d++ = *s++;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * handle sroms on ELPPC
+ * fix ether address
+ * set serial console as default
+ */
+int misc_init_r (void)
+{
+	revinfo eerev;
+	u_char *ptr;
+	u_int i, l, initSrom, copyNv;
+	char buf[256];
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
+
+	/* Clock setting for MPC107 i2c */
+	mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
+
+	/* Reset the EPIC */
+	out32r (MPC107_EUMB_GCR, 0xa0000000);
+	while (in32r (MPC107_EUMB_GCR) & 0x80000000);	/* Wait for reset to complete */
+	out32r (MPC107_EUMB_GCR, 0x20000000);	/* Put into into mixed mode */
+	while (in32r (MPC107_EUMB_IACKR) != 0xff);	/* Clear all pending interrupts */
+
+	/*
+	 * Check/Remake revision info
+	 */
+	initSrom = 0;
+	copyNv = 0;
+
+	/* read out current revision srom contens */
+	mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
+			  SECOND_DEVICE, FIRST_BLOCK);
+
+	/* read out current nvram shadow image */
+	nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
+
+	if (strcmp (eerev.magic, "ELTEC") != 0) {
+		/* srom is not initialized -> create a default revision info */
+		for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
+		     i++)
+			*ptr++ = 0x00;
+		strcpy (eerev.magic, "ELTEC");
+		eerev.revrev[0] = 1;
+		eerev.revrev[1] = 0;
+		eerev.size = 0x00E0;
+		eerev.category[0] = 0x01;
+
+		/* node id from dead e128 as default */
+		eerev.etheraddr[0] = 0x00;
+		eerev.etheraddr[1] = 0x00;
+		eerev.etheraddr[2] = 0x5B;
+		eerev.etheraddr[3] = 0x00;
+		eerev.etheraddr[4] = 0x2E;
+		eerev.etheraddr[5] = 0x4D;
+
+		/* cache config word for ELPPC */
+		*(int *) &eerev.res[0] = 0;
+
+		initSrom = 1;	/* force dialog */
+		copyNv = 1;	/* copy to nvram */
+	}
+
+	if ((copyNv == 0)
+	    && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) !=
+		el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) {
+		printf ("Invalid revision info copy in nvram !\n");
+		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+		printf ("  <r> to reenter revision info.\n");
+		printf ("=> ");
+		if (0 != readline (NULL)) {
+			switch ((char) toupper (console_buffer[0])) {
+			case 'C':
+				copyNv = 1;
+				break;
+			case 'R':
+				copyNv = 1;
+				initSrom = 1;
+				break;
+			}
+		}
+	}
+
+	if (initSrom) {
+		memcpy (buf, &eerev.revision[0][0], 14);	/* save all revision info */
+		printf ("Enter revision number (0-9): %c  ",
+			eerev.revision[0][0]);
+		if (0 != readline (NULL)) {
+			eerev.revision[0][0] =
+				(char) toupper (console_buffer[0]);
+			memcpy (&eerev.revision[1][0], buf, 12);	/* shift rest of rev info */
+		}
+
+		printf ("Enter revision character (A-Z): %c  ",
+			eerev.revision[0][1]);
+		if (1 == readline (NULL)) {
+			eerev.revision[0][1] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &eerev.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++)
+				eerev.board[i] =
+					(char) toupper (console_buffer[i]);
+			eerev.board[11] = '\0';
+		}
+
+		printf ("Enter serial number: %s ", (char *) &eerev.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++)
+				eerev.serial[i] = console_buffer[i];
+			eerev.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2)
+				eerev.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+		}
+
+		l = strlen ((char *) &eerev.text);
+		printf ("Add to text section (max 64 chr): %s ",
+			(char *) &eerev.text);
+		if (0 != readline (NULL)) {
+			for (i = l; i < 63; i++)
+				eerev.text[i] = console_buffer[i - l];
+			eerev.text[63] = '\0';
+		}
+
+		/* prepare network eeprom */
+		memset (buf, 0, 128);
+
+		buf[0] = eerev.etheraddr[1];
+		buf[1] = eerev.etheraddr[0];
+		buf[2] = eerev.etheraddr[3];
+		buf[3] = eerev.etheraddr[2];
+		buf[4] = eerev.etheraddr[5];
+		buf[5] = eerev.etheraddr[4];
+
+		*(unsigned short *) &buf[20] = 0x48B2;
+		*(unsigned short *) &buf[22] = 0x0004;
+		*(unsigned short *) &buf[24] = 0x1433;
+
+		printf ("\nSRom:  Writing i82559 info ........ ");
+		if (eepro100_srom_store ((unsigned short *) buf) == -1)
+			printf ("FAILED\n");
+		else
+			printf ("OK\n");
+
+		/* update CRC */
+		eerev.crc =
+			el_srom_checksum ((u_char *) eerev.board, eerev.size);
+
+		/* write new values */
+		printf ("\nSRom:  Writing revision info ...... ");
+		if (mpc107_srom_store
+		    ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
+		     sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+			printf ("FAILED\n\n");
+		else
+			printf ("OK\n\n");
+
+		/* write new values as shadow image to nvram */
+		nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CONFIG_SYS_SROM_SIZE);
+
+	}
+
+	/*if (initSrom) */
+	/* copy current values as shadow image to nvram */
+	if (initSrom == 0 && copyNv == 1)
+		nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CONFIG_SYS_SROM_SIZE);
+
+	/* update environment */
+	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 eerev.etheraddr[0], eerev.etheraddr[1],
+		 eerev.etheraddr[2], eerev.etheraddr[3],
+		 eerev.etheraddr[4], eerev.etheraddr[5]);
+	setenv ("ethaddr", buf);
+
+	/* print actual board identification */
+	printf ("Ident: %s  Ser %s  Rev %c%c\n",
+		eerev.board, (char *) &eerev.serial,
+		eerev.revision[0][0], eerev.revision[0][1]);
+
+	return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/elppc/mpc107_i2c.c b/u-boot/board/eltec/elppc/mpc107_i2c.c
new file mode 100644
index 0000000..ae6642e
--- /dev/null
+++ b/u-boot/board/eltec/elppc/mpc107_i2c.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include "srom.h"
+
+/* locals */
+static unsigned long mpc107_eumb_addr = 0;
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * calculate checksum for ELTEC revision srom
+ */
+unsigned long el_srom_checksum (ptr, size)
+register unsigned char *ptr;
+unsigned long size;
+{
+    u_long f, accu = 0;
+    u_int  i;
+    u_char byte;
+
+    for (; size; size--)
+    {
+	byte = *ptr++;
+	for (i = 8; i; i--)
+	{
+	    f =  ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
+	    accu >>= 1; accu ^= f;
+	    byte >>= 1;
+	}
+    }
+    return(accu);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int mpc107_i2c_wait ( unsigned long timeout )
+{
+    unsigned long x;
+
+    while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82)
+    {
+	if (!timeout--)
+	    return -1;
+    }
+
+    if (x & 0x10)
+    {
+	return -1;
+    }
+    out32r(MPC107_I2CSR, 0);
+
+    return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int mpc107_i2c_wait_idle ( unsigned long timeout )
+{
+    while (in32r(MPC107_I2CSR) & 0x20)
+    {
+	if (!timeout--)
+	    return -1;
+    }
+    return 0;
+}
+
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_read_byte (
+    unsigned char device,
+    unsigned char block,
+    unsigned char offset )
+{
+    unsigned long timeout = MPC107_I2C_TIMEOUT;
+    int data;
+
+    if (!mpc107_eumb_addr)
+	return -6;
+
+    mpc107_i2c_wait_idle (timeout);
+
+    /* Start with MEN */
+    out32r(MPC107_I2CCR, 0x80);
+
+    /* Start as master */
+    out32r(MPC107_I2CCR, 0xB0);
+    out32r(MPC107_I2CDR, (0xA0 | device | block));
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 1\n");
+	return -2;
+    }
+
+    if (in32r(MPC107_I2CSR)&0x1)
+    {
+	/* Generate STOP condition; device busy or not existing */
+	out32r(MPC107_I2CCR, 0x80);
+	return -1;
+    }
+
+    /* Data address */
+    out32r(MPC107_I2CDR, offset);
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 2\n");
+	return -3;
+    }
+
+    /* Switch to read - restart */
+    out32r(MPC107_I2CCR, 0xB4);
+    out32r(MPC107_I2CDR, (0xA1 | device | block));
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 3\n");
+	return -4;
+    }
+
+    out32r(MPC107_I2CCR, 0xA8); /* no ACK */
+    in32r(MPC107_I2CDR);
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 4\n");
+	return -5;
+    }
+    /* Generate STOP condition */
+    out32r(MPC107_I2CCR, 0x88);
+
+    /* read */
+    data = in32r(MPC107_I2CDR);
+
+    return (data);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_write_byte (
+    unsigned char device,
+    unsigned char block,
+    unsigned char offset,
+    unsigned char val )
+{
+
+    unsigned long timeout = MPC107_I2C_TIMEOUT;
+
+    if (!mpc107_eumb_addr)
+	return -6;
+
+    mpc107_i2c_wait_idle(timeout);
+
+    /* Start with MEN */
+    out32r(MPC107_I2CCR, 0x80);
+
+    /* Start as master */
+    out32r(MPC107_I2CCR, 0xB0);
+    out32r(MPC107_I2CDR, (0xA0 | device | block));
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_write Error 1\n");
+	return -1;
+    }
+
+    /* Data address */
+    out32r(MPC107_I2CDR, offset);
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_write Error 2\n");
+	return -1;
+    }
+
+    /* Write */
+    out32r(MPC107_I2CDR, val);
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_write Error 3\n");
+	return -1;
+    }
+
+    /* Generate Stop Condition */
+    out32r(MPC107_I2CCR, 0x80);
+
+    /* Return ACK or no ACK */
+    return (in32r(MPC107_I2CSR) & 0x01);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_srom_load (
+    unsigned char addr,
+    unsigned char *pBuf,
+    int          cnt,
+    unsigned char device,
+    unsigned char block )
+{
+    register int i;
+    int val;
+    int timeout;
+
+    for (i = 0; i < cnt; i++)
+    {
+	timeout=100;
+	do
+	{
+	    val = mpc107_i2c_read_byte (device, block, addr);
+	    if (val < -1)
+	    {
+	    printf("i2c_read_error %d at dev %x block %x addr %x\n",
+		   val, device, block, addr);
+	    return -1;
+	    }
+	    else if (timeout==0)
+	    {
+		printf ("i2c_read_error: timeout at dev %x block %x addr %x\n",
+			device, block, addr);
+		return -1;
+	    }
+	    timeout--;
+	} while (val == -1); /* if no ack: try again! */
+
+	*pBuf++ = (unsigned char)val;
+	addr++;
+
+	if ((addr == 0) && (i != cnt-1))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    {
+		printf ("ic2_read_error: read beyond 2. block !\n");
+		return -1;
+	    }
+	}
+    }
+    udelay(100000);
+    return (cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_srom_store (
+    unsigned char addr,
+    unsigned char *pBuf,
+    int          cnt,
+    unsigned char device,
+    unsigned char block )
+{
+    register int i;
+
+    for (i = 0; i < cnt; i++)
+    {
+	while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1);
+	addr++;
+	pBuf++;
+
+	if ((addr == 0) && (i != cnt-1))     /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    {
+		printf ("ic2_write_error: write beyond 2. block !\n");
+		return -1;
+	    }
+	}
+    }
+    udelay(100000);
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider )
+{
+    unsigned long x;
+
+    if (eumb_addr)
+	mpc107_eumb_addr = eumb_addr;
+    else
+	return -1;
+
+    /* Set I2C clock */
+    x = in32r(MPC107_I2CFDR) & 0xffffff00;
+    out32r(MPC107_I2CFDR, (x | divider));
+
+    /* Clear arbitration */
+    out32r(MPC107_I2CSR, 0);
+
+    return mpc107_eumb_addr;
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/u-boot/board/eltec/elppc/pci.c b/u-boot/board/eltec/elppc/pci.c
new file mode 100644
index 0000000..2948531
--- /dev/null
+++ b/u-boot/board/eltec/elppc/pci.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
+	CONFIG_SYS_PCI_MEMORY_SIZE,
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/u-boot/board/eltec/elppc/srom.h b/u-boot/board/eltec/elppc/srom.h
new file mode 100644
index 0000000..504b742
--- /dev/null
+++ b/u-boot/board/eltec/elppc/srom.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* common srom defs */
+#define FIRST_DEVICE            0x00
+#define SECOND_DEVICE           0x04
+#define FIRST_BLOCK             0x00
+#define SECOND_BLOCK            0x02
+#define BLOCK_SIZE              0x100
+#define ERROR                   (-1)
+
+#define CLK2P0TO1_1MB_PB_0P5DH  0x79000100
+#define CLK2P5TO1_1MB_PB_0P5DH  0x7B000100
+
+#define CPU_TYPE_740            0x08
+#define CPU_TYPE_750            0x08
+#define CPU_TYPE                ((get_pvr()>>16)&0xffff)
+
+#define ABS(x)                  ((x<0)?-x:x)
+#define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
+
+/* bab7xx ELTEC srom */
+#define I2C_BUS_DAT             (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CONFIG_SYS_ISA_IO + 0x221)
+
+/* srom at mpc107 */
+#define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
+#define MPC107_I2CFDR           (mpc107_eumb_addr + 0x3004)     /* freq divider */
+#define MPC107_I2CCR            (mpc107_eumb_addr + 0x3008)     /* control      */
+#define MPC107_I2CSR            (mpc107_eumb_addr + 0x300c)     /* status       */
+#define MPC107_I2CDR            (mpc107_eumb_addr + 0x3010)     /* data         */
+#define MPC107_I2C_TIMEOUT      10000000
+
+/* i82559 */
+#define EE_ADDR_BITS            6
+#define EE_SIZE                 0x40                            /* 0x40 words */
+#define EE_CHECKSUM             0xBABA
+
+/* dc21143 */
+#define DEC_SROM_SIZE           128
+
+
+/*
+ * structure of revision srom
+ */
+typedef struct  {
+    char    magic[8];           /* 000 - Magic number */
+    char    revrev[2];          /* 008 - Revision of structure */
+    unsigned short size;        /* 00A - Size of CRC area */
+    unsigned long  crc;         /* 00C - CRC */
+    char    board[16];          /* 010 - Board Revision information */
+    char    option[4][16];      /* 020 - Option Revision information */
+    char    serial[8];          /* 060 - Board serial number */
+    char    etheraddr[6];       /* 068 - Ethernet node addresse */
+    char    reserved[2];        /* 06E - Reserved */
+    char    revision[7][2];     /* 070 - Revision codes */
+    char    category[2];        /* 07E - Category codes */
+    char    text[64];           /* 080 - Text field */
+    char    res[64];            /* 0C0 - Reserved */
+} revinfo;
+
+unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
+int el_srom_load  (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+
+int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
+int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
+int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
+			   unsigned char offset, unsigned char val);
+int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
+		      unsigned char device, unsigned char block);
+int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
+		       unsigned char device, unsigned char block);
+
+int dc_srom_load (unsigned short *dest);
+int dc_srom_store (unsigned short *src);
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata);
+void eepro100_srom_load (unsigned short *destination);
+int  eepro100_srom_store (unsigned short *source);
diff --git a/u-boot/board/eltec/mhpc/Makefile b/u-boot/board/eltec/mhpc/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/eltec/mhpc/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eltec/mhpc/flash.c b/u-boot/board/eltec/mhpc/flash.c
new file mode 100644
index 0000000..2fbdb27
--- /dev/null
+++ b/u-boot/board/eltec/mhpc/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <linux/byteorder/swab.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)                         __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)                         __swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F640J5 :
+				printf ("28F640J5 \n"); break;
+	default:		printf ("Unknown Chip Type=0x%lXh\n",
+					info->flash_id & FLASH_TYPEMASK); break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0xAA00AA00;
+	addr[0x2AAA] = (FPW)0x55005500;
+	addr[0x5555] = (FPW)0x90009000;
+
+	value = SWAP(addr[0]);
+
+   switch (value) {
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
+		return (0);			      /* no or unknown flash	*/
+	}
+
+   value = SWAP(addr[1]);			        /* device ID no swap !*/
+
+   switch (value) {
+   case (FPW)INTEL_ID_28F640J5 :
+	info->flash_id += FLASH_28F640J5 ;
+	info->sector_count = 64;
+	info->size = 0x00800000;
+	break;            /* => 8 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rc = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = (FPW)0x50005000;	/* clear status register */
+			*addr = (FPW)0x20002000;	/* erase setup */
+			*addr = (FPW)0xD000D000;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW)0xB000B000; /* suspend erase */
+					*addr = (FPW)0xFF00FF00; /* reset to read mode */
+					rc = 1;
+					break;
+				}
+
+				/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = (FPW)0xFF00FF00;	/* reset to read mode */
+			printf (" done\n");
+		}
+	}
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += port_width;
+		cnt -= port_width;
+		if ((wp & 0xfff) == 0)
+		{
+			printf("%08lX",wp);
+			printf("\x1b[8D");
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x40004000;		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0xFF00FF00;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW)0xFF00FF00;	/* restore read mode */
+
+	return (0);
+}
diff --git a/u-boot/board/eltec/mhpc/mhpc.c b/u-boot/board/eltec/mhpc/mhpc.c
new file mode 100644
index 0000000..7cca6b2
--- /dev/null
+++ b/u-boot/board/eltec/mhpc/mhpc.c
@@ -0,0 +1,483 @@
+/*
+ * (C) Copyright 2001
+ * ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * Board specific routines for the miniHiPerCam
+ *
+ * - initialisation (eeprom)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <linux/ctype.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+#include <video_fb.h>
+
+/* imports from common/main.c */
+extern char console_buffer[CONFIG_SYS_CBSIZE];
+
+extern void eeprom_init (void);
+extern int eeprom_read (unsigned dev_addr, unsigned offset,
+			unsigned char *buffer, unsigned cnt);
+extern int eeprom_write (unsigned dev_addr, unsigned offset,
+			 unsigned char *buffer, unsigned cnt);
+
+/* globals */
+void *video_hw_init (void);
+void video_set_lut (unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+	);
+
+GraphicDevice gdev;
+
+/* locals */
+static void video_circle (char *center, int radius, int color, int pitch);
+static void video_test_image (void);
+static void video_default_lut (unsigned int clut_type);
+
+/* revision info foer MHPC EEPROM offset 480 */
+typedef struct {
+	char board[12];		/* 000 - Board Revision information */
+	char sensor;		/* 012 - Sensor Type information */
+	char serial[8];		/* 013 - Board serial number */
+	char etheraddr[6];	/* 021 - Ethernet node addresse */
+	char revision[2];	/* 027 - Revision code */
+	char option[3];		/* 029 - resevered for options */
+} revinfo;
+
+/* ------------------------------------------------------------------------- */
+
+static const unsigned int sdram_table[] = {
+	/* read single beat cycle */
+	0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
+	0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
+
+	/* read burst cycle */
+	0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
+	0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* write single beat cycle */
+	0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* write burst cycle */
+	0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
+	0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* periodic timer expired */
+	0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
+	0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* exception */
+	0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
+};
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
+
+	/* reset the port A s.a. cpm-routines */
+	ip->iop_padat = 0x0000;
+	ip->iop_papar = 0x0000;
+	ip->iop_padir = 0x0800;
+	ip->iop_paodr = 0x0000;
+
+	/* reset the port B for digital and LCD output */
+	cp->cp_pbdat = 0x0300;
+	cp->cp_pbpar = 0x5001;
+	cp->cp_pbdir = 0x5301;
+	cp->cp_pbodr = 0x0000;
+
+	/* reset the port C configured for SMC1 serial port and aqc. control */
+	ip->iop_pcdat = 0x0800;
+	ip->iop_pcpar = 0x0000;
+	ip->iop_pcdir = 0x0e30;
+	ip->iop_pcso = 0x0000;
+
+	/* Config port D for LCD output */
+	ip->iop_pdpar = 0x1fff;
+	ip->iop_pddir = 0x1fff;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	puts ("Board: ELTEC miniHiperCam\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r (void)
+{
+	revinfo mhpcRevInfo;
+	char nid[32];
+	char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+		"OMNIVISON OV7110 b&w", NULL
+	};
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
+	int i;
+
+	/* check revision data */
+	eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
+
+	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
+		printf ("Enter revision number (0-9): %c  ",
+			mhpcRevInfo.revision[0]);
+		if (0 != readline (NULL)) {
+			mhpcRevInfo.revision[0] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter revision character (A-Z): %c  ",
+			mhpcRevInfo.revision[1]);
+		if (1 == readline (NULL)) {
+			mhpcRevInfo.revision[1] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &mhpcRevInfo.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++) {
+				mhpcRevInfo.board[i] =
+					(char) toupper (console_buffer[i]);
+				mhpcRevInfo.board[11] = '\0';
+			}
+		}
+
+		printf ("Supported sensor types:\n");
+		i = 0;
+		do {
+			printf ("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
+		} while (mhpcSensorTypes[++i] != NULL);
+
+		do {
+			printf ("\nEnter sensor number (0-255): %d  ",
+				(int) mhpcRevInfo.sensor);
+			if (0 != readline (NULL)) {
+				mhpcRevInfo.sensor =
+					(unsigned char)
+					simple_strtoul (console_buffer, NULL,
+							10);
+			}
+		} while (mhpcRevInfo.sensor >= i);
+
+		printf ("Enter serial number: %s ",
+			(char *) &mhpcRevInfo.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++) {
+				mhpcRevInfo.serial[i] = console_buffer[i];
+			}
+			mhpcRevInfo.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2) {
+				mhpcRevInfo.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+			}
+		}
+
+		/* setup new revision data */
+		eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
+			      32);
+	}
+
+	/* set environment */
+	sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+		 mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+		 mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+	setenv ("ethaddr", nid);
+
+	/* print actual board identification */
+	printf ("Ident: %s %s Ser %s Rev %c%c\n",
+		mhpcRevInfo.board,
+		(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
+		(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
+		mhpcRevInfo.revision[1]);
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
+	memctl->memc_mptpr = MPTPR_PTP_DIV64;
+	memctl->memc_mar = 0x00008800;
+
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+	udelay (200);
+
+	/*
+	 * Map controller SDRAM bank 1
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
+
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002730;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (10000);
+
+	/* leave place for framebuffers */
+	return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_circle (char *center, int radius, int color, int pitch)
+{
+	int x, y, d, dE, dSE;
+
+	x = 0;
+	y = radius;
+	d = 1 - radius;
+	dE = 3;
+	dSE = -2 * radius + 5;
+
+	*(center + x + y * pitch) = color;
+	*(center + y + x * pitch) = color;
+	*(center + y - x * pitch) = color;
+	*(center + x - y * pitch) = color;
+	*(center - x - y * pitch) = color;
+	*(center - y - x * pitch) = color;
+	*(center - y + x * pitch) = color;
+	*(center - x + y * pitch) = color;
+	while (y > x) {
+		if (d < 0) {
+			d += dE;
+			dE += 2;
+			dSE += 2;
+			x++;
+		} else {
+			d += dSE;
+			dE += 2;
+			dSE += 4;
+			x++;
+			y--;
+		}
+		*(center + x + y * pitch) = color;
+		*(center + y + x * pitch) = color;
+		*(center + y - x * pitch) = color;
+		*(center + x - y * pitch) = color;
+		*(center - x - y * pitch) = color;
+		*(center - y - x * pitch) = color;
+		*(center - y + x * pitch) = color;
+		*(center - x + y * pitch) = color;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_test_image (void)
+{
+	char *di;
+	int i, n;
+
+	/* draw raster */
+	for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
+		memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
+			LCD_VIDEO_FG, LCD_VIDEO_COLS);
+		for (n = i + 1; n < i + 32; n++)
+			memset ((char *) (LCD_VIDEO_ADDR +
+					  n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
+				LCD_VIDEO_COLS);
+	}
+
+	for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
+		for (n = 0; n < LCD_VIDEO_ROWS; n++)
+			*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
+				LCD_VIDEO_FG;
+	}
+
+	/* draw gray bar */
+	di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
+		       97 * LCD_VIDEO_COLS);
+	for (n = 0; n < 63; n++) {
+		for (i = 0; i < 256; i++) {
+			*di++ = (char) i;
+			*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
+		}
+		di += LCD_VIDEO_COLS - 256;
+	}
+
+	video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
+		      LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
+		      LCD_VIDEO_FG, LCD_VIDEO_COLS);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_default_lut (unsigned int clut_type)
+{
+	unsigned int i;
+	unsigned char RGB[] = {
+		0x00, 0x00, 0x00,	/* black */
+		0x80, 0x80, 0x80,	/* gray */
+		0xff, 0x00, 0x00,	/* red */
+		0x00, 0xff, 0x00,	/* green */
+		0x00, 0x00, 0xff,	/* blue */
+		0x00, 0xff, 0xff,	/* cyan */
+		0xff, 0x00, 0xff,	/* magenta */
+		0xff, 0xff, 0x00,	/* yellow */
+		0x80, 0x00, 0x00,	/* dark red */
+		0x00, 0x80, 0x00,	/* dark green */
+		0x00, 0x00, 0x80,	/* dark blue */
+		0x00, 0x80, 0x80,	/* dark cyan */
+		0x80, 0x00, 0x80,	/* dark magenta */
+		0x80, 0x80, 0x00,	/* dark yellow */
+		0xc0, 0xc0, 0xc0,	/* light gray */
+		0xff, 0xff, 0xff,	/* white */
+	};
+
+	switch (clut_type) {
+	case 1:
+		for (i = 0; i < 240; i++)
+			video_set_lut (i, i, i, i);
+		for (i = 0; i < 16; i++)
+			video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
+				       RGB[i * 3 + 2]);
+		break;
+	default:
+		for (i = 0; i < 256; i++)
+			video_set_lut (i, i, i, i);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+void *video_hw_init (void)
+{
+	unsigned int clut = 0;
+	unsigned char *penv;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* enable video only on CLUT value */
+	if ((penv = (uchar *)getenv ("clut")) != NULL)
+		clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
+	else
+		return NULL;
+
+	/* disable graphic before write LCD regs. */
+	immr->im_lcd.lcd_lccr = 0x96000866;
+
+	/* config LCD regs. */
+	immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
+	immr->im_lcd.lcd_lchcr = 0x010a0093;
+	immr->im_lcd.lcd_lcvcr = 0x900f0024;
+
+	printf ("Video: 640x480 8Bit Index Lut %s\n",
+		(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
+
+	video_default_lut (clut);
+
+	/* clear framebuffer */
+	memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
+		LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
+
+	/* enable graphic */
+	immr->im_lcd.lcd_lccr = 0x96000867;
+
+	/* fill in Graphic Device */
+	gdev.frameAdrs = LCD_VIDEO_ADDR;
+	gdev.winSizeX = LCD_VIDEO_COLS;
+	gdev.winSizeY = LCD_VIDEO_ROWS;
+	gdev.gdfBytesPP = 1;
+	gdev.gdfIndex = GDF__8BIT_INDEX;
+
+	if (clut > 1)
+		/* return Graphic Device for console */
+		return (void *) &gdev;
+	else
+		/* just graphic enabled - draw something beautiful */
+		video_test_image ();
+
+	return NULL;		/* this disabels cfb - console */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void video_set_lut (unsigned int index,
+		    unsigned char r, unsigned char g, unsigned char b)
+{
+	unsigned int lum;
+	unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
+
+	/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
+	/* y = 0.299*R + 0.587*G + 0.114*B */
+	lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
+	pLut[index] =
+		((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
+								      0x3f);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/eltec/mhpc/u-boot.lds b/u-boot/board/eltec/mhpc/u-boot.lds
new file mode 100644
index 0000000..4a96388
--- /dev/null
+++ b/u-boot/board/eltec/mhpc/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/eltec/mhpc/u-boot.lds.debug b/u-boot/board/eltec/mhpc/u-boot.lds.debug
new file mode 100644
index 0000000..99098bf
--- /dev/null
+++ b/u-boot/board/eltec/mhpc/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/emk/common/am79c874.c b/u-boot/board/emk/common/am79c874.c
new file mode 100644
index 0000000..552813e
--- /dev/null
+++ b/u-boot/board/emk/common/am79c874.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*****************************************************************************
+ * check fiber optic link present, and then copper link present. do auto switch
+ * between both
+ *****************************************************************************/
diff --git a/u-boot/board/emk/common/flash.c b/u-boot/board/emk/common/flash.c
new file mode 100644
index 0000000..8579cfa
--- /dev/null
+++ b/u-boot/board/emk/common/flash.c
@@ -0,0 +1,591 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined (CONFIG_TOP860)
+  typedef unsigned short FLASH_PORT_WIDTH;
+  typedef volatile unsigned short FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0555
+  #define FLASH_CYCLE2	0x02aa
+  #define FLASH_ID1		0
+  #define FLASH_ID2		1
+  #define FLASH_ID3		0x0e
+  #define FLASH_ID4		0x0F
+#endif
+
+#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
+  typedef unsigned char FLASH_PORT_WIDTH;
+  typedef volatile unsigned char FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0aaa
+  #define FLASH_CYCLE2	0x0555
+  #define FLASH_ID1		0
+  #define FLASH_ID2		2
+  #define FLASH_ID3		0x1c
+  #define FLASH_ID4		0x1E
+#endif
+
+#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
+  typedef unsigned char FLASH_PORT_WIDTH;
+  typedef volatile unsigned char FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0555
+  #define FLASH_CYCLE2	0x02aa
+  #define FLASH_ID1		0
+  #define FLASH_ID2		1
+  #define FLASH_ID3		0x0E
+  #define FLASH_ID4		0x0F
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(uint, ulong, ulong);
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+	flash_preinit();
+
+	/* There is only ONE FLASH device */
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+	size += flash_info[i].size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size &&
+			info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+#if 0
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+#endif
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160T:
+	case FLASH_AM160B:
+		fmt = "29LV160%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_AMLV640U:
+		fmt = "29LV640M (64 Mbit)\n";
+		break;
+	case FLASH_AMDLV065D:
+		fmt = "29LV065D (64 Mbit)\n";
+		break;
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		ulong	size;
+		int		erased;
+		ulong	*flash = (unsigned long *) info->start[i];
+
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+			(i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+		(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (
+			flash = (unsigned long *) info->start[i], erased = 1;
+				(flash != (unsigned long *) info->start[i] + size) && erased;
+					flash++
+			)
+			erased = *flash == ~0x0UL;
+
+		printf (" %08lX %s %s",
+			info->start[i],
+			erased ? "E": " ",
+			info->protect[i] ? "(RO)" : "    ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int		i;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[FLASH_ID1] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+#if 0
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+#endif
+
+	default:
+		printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
+
+	case (FPW)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		info->start[0] = (ulong)addr;
+		info->start[1] = (ulong)addr + 0x4000;
+		info->start[2] = (ulong)addr + 0x6000;
+		info->start[3] = (ulong)addr + 0x8000;
+		for (i = 4; i < info->sector_count; i++)
+		{
+			info->start[i] = (ulong)addr + 0x10000 * (i-3);
+		}
+		break;
+
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for (i = 0; i < info->sector_count; i++)
+		{
+			info->start[i] = (ulong)addr + 0x10000 * i;
+		}
+		break;
+
+	case (FPW)AMD_ID_MIRROR:
+		/* MIRROR BIT FLASH, read more ID bytes */
+		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
+			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
+		{
+			info->flash_id += FLASH_AMLV640U;
+			info->sector_count = 128;
+			info->size = 0x00800000;
+			for (i = 0; i < info->sector_count; i++)
+			{
+				info->start[i] = (ulong)addr + 0x10000 * i;
+			}
+			break;
+		}
+		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
+			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
+		{
+			/* attention: only the first 16 MB will be used in u-boot */
+			info->flash_id += FLASH_AMLV256U;
+			info->sector_count = 256;
+			info->size = 0x01000000;
+			for (i = 0; i < info->sector_count; i++)
+			{
+				info->start[i] = (ulong)addr + 0x10000 * i;
+			}
+			break;
+		}
+
+		/* fall thru to here ! */
+	default:
+		printf ("unknown AMD device=%x %x %x",
+			(FPW)addr[FLASH_ID2],
+			(FPW)addr[FLASH_ID3],
+			(FPW)addr[FLASH_ID4]);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0x800000;
+		break;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:
+	case FLASH_AMLV640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode */
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
diff --git a/u-boot/board/emk/common/vpd.c b/u-boot/board/emk/common/vpd.c
new file mode 100644
index 0000000..c2af219
--- /dev/null
+++ b/u-boot/board/emk/common/vpd.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*****************************************************************************
+ * read "factory" part of EEPROM and set some environment variables
+ *****************************************************************************/
+void read_factory_r (void)
+{
+	/* read 'factory' part of EEPROM */
+	uchar buf[81];
+	uchar *p;
+	uint length;
+	uint addr;
+	uint len;
+
+	/* get length first */
+	addr = CONFIG_SYS_FACT_OFFSET;
+	if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) {
+	  bailout:
+		printf ("cannot read factory configuration\n");
+		printf ("be sure to set ethaddr	yourself!\n");
+		return;
+	}
+	length = buf[0] + (buf[1] << 8);
+	addr += 2;
+
+	/* sanity check */
+	if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2)
+		goto bailout;
+
+	/* read lines */
+	while (length > 0) {
+		/* read one line */
+		len = length > 80 ? 80 : length;
+		if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len))
+			goto bailout;
+		/* mark end of buffer */
+		buf[len] = 0;
+		/* search end of line */
+		for (p = buf; *p && *p != 0x0a; p++);
+		if (!*p)
+			goto bailout;
+		*p++ = 0;
+		/* advance to next line start */
+		length -= p - buf;
+		addr += p - buf;
+		/*printf ("%s\n", buf); */
+		/* search for our specific entry */
+		if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
+			setenv ("ethaddr", (char *)(buf + 19));
+		} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
+			setenv ("serial#", (char *)(buf + 15));
+		} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
+			setenv ("board_id", (char *)(buf + 13));
+		}
+	}
+}
diff --git a/u-boot/board/emk/top5200/Makefile b/u-boot/board/emk/top5200/Makefile
new file mode 100644
index 0000000..72db38d
--- /dev/null
+++ b/u-boot/board/emk/top5200/Makefile
@@ -0,0 +1,54 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/emk/top5200/top5200.c b/u-boot/board/emk/top5200/top5200.c
new file mode 100644
index 0000000..7efbcb0
--- /dev/null
+++ b/u-boot/board/emk/top5200/top5200.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+/*****************************************************************************
+ * initialize SDRAM/DDRAM controller.
+ * TBD: get data from I2C EEPROM
+ *****************************************************************************/
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+#if 0
+	ulong	t;
+	ulong	tap_del;
+#endif
+
+	#define	MODE_EN		0x80000000
+	#define	SOFT_PRE	2
+	#define	SOFT_REF	4
+
+	/* configure SDRAM start/end */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+#ifdef CONFIG_SYS_DRAM_DDR
+	/* set extended mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
+#endif
+	/* set mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
+	/* set mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
+	/* write default TAP delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
+
+#if 0
+	for (tap_del = 0; tap_del < 32; tap_del++)
+	{
+		*(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
+
+		printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
+		for (t = 0; t < 0x04000000; t+=4)
+			*(vu_long *) t = t;
+		printf ("Checking DRAM...\n");
+		for (t = 0; t < 0x04000000; t+=4)
+		{
+			ulong	rval = *(vu_long *) t;
+			if (rval != t)
+			{
+				printf ("mismatch at %x: ", t);
+				printf (" 1.read %x", rval);
+				printf (" 2.read %x", *(vu_long *) t);
+				printf (" 3.read %x", *(vu_long *) t);
+				break;
+			}
+		}
+	}
+#endif
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
+
+	/* return total ram size */
+	return dramsize;
+}
+
+/*****************************************************************************
+ * print board identification
+ *****************************************************************************/
+int checkboard (void)
+{
+#if defined (CONFIG_EVAL5200)
+	puts ("Board: EMK TOP5200 on EVAL5200\n");
+#else
+#if defined (CONFIG_LITE5200)
+	puts ("Board: LITE5200\n");
+#else
+#if defined (CONFIG_MINI5200)
+	puts ("Board: EMK TOP5200 on MINI5200\n");
+#else
+	puts ("Board: EMK TOP5200\n");
+#endif
+#endif
+#endif
+	return 0;
+}
+
+/*****************************************************************************
+ * prepare for FLASH detection
+ *****************************************************************************/
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+/*****************************************************************************
+ * finalize FLASH setup
+ *****************************************************************************/
+void flash_afterinit(uint bank, ulong start, ulong size)
+{
+	if (bank == 0) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START =
+		*(vu_long *)MPC5XXX_CS0_START =	START_REG(start);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP =
+		*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
+	}
+}
+
+/*****************************************************************************
+ * otherinits after RAM is there and we are relocated to RAM
+ * note: though this is an int function, nobody cares for the result!
+ *****************************************************************************/
+int misc_init_r (void)
+{
+#if !defined (CONFIG_LITE5200)
+	/* read 'factory' part of EEPROM */
+	extern void read_factory_r (void);
+	read_factory_r ();
+#endif
+	return (0);
+}
+
+/*****************************************************************************
+ * initialize the PCI system
+ *****************************************************************************/
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+/*****************************************************************************
+ * provide the IDE Reset Function
+ *****************************************************************************/
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+}
+#endif
diff --git a/u-boot/board/emk/top860/Makefile b/u-boot/board/emk/top860/Makefile
new file mode 100644
index 0000000..6b0a4fa
--- /dev/null
+++ b/u-boot/board/emk/top860/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/emk/top860/top860.c b/u-boot/board/emk/top860/top860.c
new file mode 100644
index 0000000..76f7a0c
--- /dev/null
+++ b/u-boot/board/emk/top860/top860.c
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2003
+ * EMK Elektronik GmbH <www.emk-elektronik.de>
+ * Reinhard Meyer <r.meyer@emk-elektronik.de>
+ *
+ * Board specific routines for the TOP860
+ *
+ * - initialisation
+ * - interface to VPD data (mac address, clock speeds)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+
+/*****************************************************************************
+ * UPM table for 60ns EDO RAM at 25 MHz bus/external clock
+ *****************************************************************************/
+static const uint edo_60ns_25MHz_tbl[] = {
+
+/* single read   (offset 0x00 in upm ram) */
+    0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,
+    0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,
+/* burst read    (offset 0x08 in upm ram) */
+    0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,
+    0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,
+    0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* single write  (offset 0x18 in upm ram) */
+    0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* burst write   (offset 0x20 in upm ram) */
+    0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,
+    0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,
+    0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* refresh       (offset 0x30 in upm ram) */
+    0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* exception     (offset 0x3C in upm ram) */
+    0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,
+};
+
+/*****************************************************************************
+ * Print Board Identity
+ *****************************************************************************/
+int checkboard (void)
+{
+	puts ("Board:"CONFIG_IDENT_STRING"\n");
+	return (0);
+}
+
+/*****************************************************************************
+ * Initialize DRAM controller
+ *****************************************************************************/
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/*
+	 * Only initialize memory controller when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		volatile uint *addr1, *addr2;
+		uint i, j;
+
+		upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
+			   sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
+		memctl->memc_mptpr = 0x0200;
+		memctl->memc_mamr = 0x0ca20330;
+		memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
+		memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
+		/*
+		 * Do 8 read accesses to DRAM
+		 */
+		addr1 = (volatile uint *) 0;
+		addr2 = (volatile uint *) 0x00400000;
+		for (i = 0, j = 0; i < 8; i++)
+			j = addr1[0];
+
+		/*
+		 * Now check whether we got 4MB or 16MB populated
+		 */
+		addr1[0] = 0x12345678;
+		addr1[1] = 0x9abcdef0;
+		addr2[0] = 0xfeedc0de;
+		addr2[1] = 0x47110815;
+		if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
+			/* only 4MB populated */
+			memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
+		}
+	}
+
+	return -(memctl->memc_or2 & 0xffff0000);
+}
+
+/*****************************************************************************
+ * prepare for FLASH detection
+ *****************************************************************************/
+void flash_preinit(void)
+{
+}
+
+/*****************************************************************************
+ * finalize FLASH setup
+ *****************************************************************************/
+void flash_afterinit(uint bank, ulong start, ulong size)
+{
+}
+
+/*****************************************************************************
+ * otherinits after RAM is there and we are relocated to RAM
+ * note: though this is an int function, nobody cares for the result!
+ *****************************************************************************/
+int misc_init_r (void)
+{
+	/* read 'factory' part of EEPROM */
+	extern void read_factory_r (void);
+	read_factory_r ();
+
+	return (0);
+}
diff --git a/u-boot/board/emk/top860/u-boot.lds b/u-boot/board/emk/top860/u-boot.lds
new file mode 100644
index 0000000..ae1a791
--- /dev/null
+++ b/u-boot/board/emk/top860/u-boot.lds
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/emk/top860/u-boot.lds.debug b/u-boot/board/emk/top860/u-boot.lds.debug
new file mode 100644
index 0000000..0f536f3
--- /dev/null
+++ b/u-boot/board/emk/top860/u-boot.lds.debug
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/emk/top9000/Makefile b/u-boot/board/emk/top9000/Makefile
new file mode 100644
index 0000000..3ac6f14
--- /dev/null
+++ b/u-boot/board/emk/top9000/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2010
+# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-$(CONFIG_ATMEL_SPI)	+= spi.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/emk/top9000/spi.c b/u-boot/board/emk/top9000/spi.c
new file mode 100644
index 0000000..b957986
--- /dev/null
+++ b/u-boot/board/emk/top9000/spi.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+static const struct {
+	u32	port;
+	u32	bit;
+} cs_to_portbit[2][4] = {
+	{{AT91_PIO_PORTA,  3}, {AT91_PIO_PORTC, 11},
+			{AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} },
+	{{AT91_PIO_PORTB,  3}, {AT91_PIO_PORTC,  5},
+			{AT91_PIO_PORTC,  4}, {AT91_PIO_PORTC,  3} }
+};
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs);
+	if (bus < 2 && cs < 4)
+		return 1;
+	return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs);
+	at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
+		cs_to_portbit[slave->bus][slave->cs].bit, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
+	at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
+		cs_to_portbit[slave->bus][slave->cs].bit, 1);
+}
diff --git a/u-boot/board/emk/top9000/top9000.c b/u-boot/board/emk/top9000/top9000.c
new file mode 100644
index 0000000..73dd706
--- /dev/null
+++ b/u-boot/board/emk/top9000/top9000.c
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <spi.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwn.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		AT91_SMC_EXNWMODE_DISABLE |
+		AT91_SMC_DBW_8 |
+		AT91_SMC_TDF_(2));
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void macb_hw_init(void)
+{
+	/* Enable EMAC clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/* Initialize EMAC=MACB hardware */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	/* Enable MCI clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI);
+
+	/* Initialize MCI hardware */
+	at91_mci_hw_init();
+
+	/* This calls the atmel_mmc_init in gen_atmel_mci.c */
+	return atmel_mci_init((void *)AT91_BASE_MCI);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	/*
+	 * the only currently existing use of this function
+	 * (fsl_esdhc.c) suggests this function must return
+	 * *cs = TRUE if a card is NOT detected -> in most
+	 * cases the value of the pin when the detect switch
+	 * closes to GND
+	 */
+	*cd = at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0;
+	return 0;
+}
+
+#endif
+
+int board_early_init_f(void)
+{
+	struct at91_shdwn *shdwn = (struct at91_shdwn *)AT91_SHDWN_BASE;
+
+	/*
+	 * make sure the board can be powered on by
+	 * any transition on WKUP
+	 */
+	writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
+		&shdwn->mr);
+
+	/* Enable clocks for all PIOs */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB);
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* set SCL0 and SDA0 to open drain */
+	at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
+	at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
+	at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
+	at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
+	at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
+	at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
+
+	/* set SCL1 and SDA1 to open drain */
+	at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
+	at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
+	at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
+	at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
+	at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
+	at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of TOP9000 Board */
+	gd->bd->bi_arch_number = MACH_TYPE_TOP9000;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	macb_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI0
+	/* (n+4) denotes to use nSPISEL(0) in GPIO mode! */
+	at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4));
+#endif
+#ifdef CONFIG_ATMEL_SPI1
+	at91_spi1_hw_init(1 << (ENC_CS_NUM + 4));
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	/* read 'factory' part of EEPROM */
+	read_factory_r();
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+	/*
+	 * Initialize ethernet HW addresses prior to starting Linux,
+	 * needed for nfsroot.
+	 * TODO: We need to investigate if that is really necessary.
+	 */
+	eth_init(gd->bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	int num = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0,
+		(void *)AT91_EMAC_BASE,
+		CONFIG_SYS_PHY_ID);
+	if (!rc)
+		num++;
+#endif
+#ifdef CONFIG_ENC28J60
+	rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM,
+		ENC_SPI_CLOCK, SPI_MODE_0);
+	if (!rc)
+		num++;
+# ifdef CONFIG_ENC28J60_2
+	rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1,
+		ENC_SPI_CLOCK, SPI_MODE_0);
+	if (!rc)
+		num++;
+#  ifdef CONFIG_ENC28J60_3
+	rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2,
+		ENC_SPI_CLOCK, SPI_MODE_0);
+	if (!rc)
+		num++;
+#  endif
+# endif
+#endif
+	return num;
+}
+
+/*
+ * I2C access functions
+ *
+ * Note:
+ * We need to access Bus 0 before relocation to access the
+ * environment settings.
+ * However i2c_get_bus_num() cannot be called before
+ * relocation.
+ */
+#ifdef CONFIG_SOFT_I2C
+void iic_init(void)
+{
+	/* ports are now initialized in board_early_init_f() */
+}
+
+int iic_read(void)
+{
+	switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+	case 0:
+		return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
+	case 1:
+		return at91_get_pio_value(I2C1_PORT, SDA1_PIN);
+	}
+	return 1;
+}
+
+void iic_sda(int bit)
+{
+	switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+	case 0:
+		at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
+		break;
+	case 1:
+		at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit);
+		break;
+	}
+}
+
+void iic_scl(int bit)
+{
+	switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+	case 0:
+		at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
+		break;
+	case 1:
+		at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit);
+		break;
+	}
+}
+
+#endif
diff --git a/u-boot/board/ep7312/Makefile b/u-boot/board/ep7312/Makefile
new file mode 100644
index 0000000..f2d8cf5
--- /dev/null
+++ b/u-boot/board/ep7312/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ep7312.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ep7312/config.mk b/u-boot/board/ep7312/config.mk
new file mode 100644
index 0000000..bdd08b8
--- /dev/null
+++ b/u-boot/board/ep7312/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xc0f80000
diff --git a/u-boot/board/ep7312/ep7312.c b/u-boot/board/ep7312/ep7312.c
new file mode 100644
index 0000000..8ed14ad
--- /dev/null
+++ b/u-boot/board/ep7312/ep7312.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <clps7111.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number MACH_TYPE_EDB7312 */
+	gd->bd->bi_arch_number = MACH_TYPE_EDB7312;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0xc0020100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ep7312/flash.c b/u-boot/board/ep7312/flash.c
new file mode 100644
index 0000000..0c2b3ae
--- /dev/null
+++ b/u-boot/board/ep7312/flash.c
@@ -0,0 +1,341 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x1000000
+#define MAIN_SECT_SIZE  0x20000
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+		printf ("28F128J3 (128Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			*addr = 0x20;		/* erase setup */
+			*addr = 0xD0;		/* erase confirm */
+
+			while ((*addr & 0x80) != 0x80) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			/* clear status register command */
+			*addr = 0x50;
+			/* reset to read mode */
+			*addr = 0xFF;
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+  outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* clear status register command */
+	*addr = 0x50;
+
+	/* program set-up command */
+	*addr = 0x40;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0xB0;
+			goto outahere;
+		}
+	}
+
+	if (val & 0x1A) {			/* check for error */
+		printf ("\nFlash write error %02x at address %08lx\n",
+				(int) val, (unsigned long) dest);
+		if (val & (1 << 3)) {
+			printf ("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if (val & (1 << 1)) {
+			printf ("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if (val & (1 << 4)) {
+			printf ("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+  outahere:
+	/* read array command */
+	*addr = 0xFF;
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/ep7312/lowlevel_init.S b/u-boot/board/ep7312/lowlevel_init.S
new file mode 100644
index 0000000..5dadb31
--- /dev/null
+++ b/u-boot/board/ep7312/lowlevel_init.S
@@ -0,0 +1,95 @@
+/*
+ * Memory Setup stuff - taken from ???
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+SYSCON1:	.long	0x80000100
+SYSCON2:	.long	0x80001100
+SYSCON3:	.long	0x80002200
+MEMCFG1:	.long	0x80000180
+MEMCFG2:	.long	0x800001C0
+SDCONF:		.long	0x80002300
+SDRFPR:		.long	0x80002340
+
+syscon1_val:	.long	0x00040100
+syscon2_val:	.long	0x00000102
+syscon3_val:	.long	0x0000020E
+memcfg1_val:	.long	0x1f101710
+memcfg2_mask:	.long	0x0000ffff @ only set lower 16 bits
+memcfg2_val:	.long	0x00001f13 @ upper 16 bits are reserved for CS7 + CS6
+sdrfpr_val:	.long	0x00000240
+sdconf_val:	.long	0x00000522
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	/*
+	 * SYSCON1-3
+	 */
+	ldr	r0, SYSCON1
+	ldr	r1, syscon1_val
+	str	r1, [r0]
+
+	ldr	r0, SYSCON2
+	ldr	r1, syscon2_val
+	str	r1, [r0]
+
+	ldr	r0, SYSCON3
+	ldr	r1, syscon3_val
+	str	r1, [r0]
+
+	/*
+	 * MEMCFG1
+	 */
+	ldr	r0, MEMCFG1
+	ldr	r1, memcfg1_val
+	str	r1, [r0]
+
+	/*
+	 * MEMCFG2
+	 */
+	ldr	r0, MEMCFG2
+	ldr	r2, [r0]
+	ldr	r1, memcfg2_mask
+	bic	r2, r2, r1
+	ldr	r1, memcfg2_val
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	/*
+	 * SDRFPR,SDCONF
+	 */
+	ldr	r0, SDCONF
+	ldr	r1, sdconf_val
+	str	r1, [r0]
+
+	ldr	r0, SDRFPR
+	ldr	r1, sdrfpr_val
+	str	r1, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/ep8248/Makefile b/u-boot/board/ep8248/Makefile
new file mode 100644
index 0000000..9079aad
--- /dev/null
+++ b/u-boot/board/ep8248/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ep8248/ep8248.c b/u-boot/board/ep8248/ep8248.c
new file mode 100644
index 0000000..5908943
--- /dev/null
+++ b/u-boot/board/ep8248/ep8248.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP8248 boards.
+ * Tested on EP8248E.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
+	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
+	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
+	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
+	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+	bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+	bcsr[7] |= 0x10;
+#endif
+
+#if CONFIG_SYS_FCC1
+	bcsr[8] |= 0xC0;
+#endif /* CONFIG_SYS_FCC1 */
+#if CONFIG_SYS_FCC2
+	bcsr[8] |= 0x30;
+#endif /* CONFIG_SYS_FCC2 */
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+	long int msize = 16L << (bcsr[2] & 3);
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
+	uchar c = 0xFF;
+	uint psdmr = CONFIG_SYS_PSDMR;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
+	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[0]) {
+	case 0x0C:
+		printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
+		break;
+	default:
+		printf("unknown: ID=%02X\n", bcsr[0]);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup( blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/u-boot/board/ep8260/Makefile b/u-boot/board/ep8260/Makefile
new file mode 100644
index 0000000..68a4803
--- /dev/null
+++ b/u-boot/board/ep8260/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o mii_phy.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ep8260/ep8260.c b/u-boot/board/ep8260/ep8260.c
new file mode 100644
index 0000000..90ab047
--- /dev/null
+++ b/u-boot/board/ep8260/ep8260.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "ep8260.h"
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB30 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB29 */ {   0,   1,   1,   1,   0,   0   }, /*  */
+	/* PB28 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB25 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB24 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB22 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /*  */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK15 */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK16 */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /*  */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /*  */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Setup CS4 to enable the Board Control/Status registers.
+ * Otherwise the smcs won't work.
+*/
+int board_early_init_f (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	regs->bcsr1 = 0x62;	/* to enable terminal on SMC1 */
+	regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
+	return 0;
+}
+
+void reset_phy (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+
+	regs->bcsr4 = 0xC0;
+}
+
+/*
+ * Check Board Identity:
+ * I don' know, how the next board revisions will be coded.
+ * Thats why its a static interpretation ...
+*/
+
+int checkboard (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+	uint major = 0, minor = 0;
+
+	switch (regs->bcsr0) {
+	case 0x02:
+		major = 1;
+		break;
+	case 0x03:
+		major = 1;
+		minor = 1;
+		break;
+	case 0x06:
+		major = 1;
+		minor = 3;
+		break;
+	default:
+		break;
+	}
+	printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
+		major, minor);
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0;
+	volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
+
+/*
+	ulong psdmr = CONFIG_SYS_PSDMR;
+#ifdef CONFIG_SYS_LSDRAM
+	ulong lsdmr = CONFIG_SYS_LSDMR;
+#endif
+*/
+	long size = CONFIG_SYS_SDRAM0_SIZE;
+	int i;
+
+
+/*
+* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+*
+* "At system reset, initialization software must set up the
+*  programmable parameters in the memory controller banks registers
+*  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+*  system software should execute the following initialization sequence
+*  for each SDRAM device.
+*
+*  1. Issue a PRECHARGE-ALL-BANKS command
+*  2. Issue eight CBR REFRESH commands
+*  3. Issue a MODE-SET command to initialize the mode register
+*
+*  The initial commands are executed by setting P/LSDMR[OP] and
+*  accessing the SDRAM with a single-byte transaction."
+*
+* The appropriate BRx/ORx registers have already been set when we
+* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+*/
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+#ifndef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_SYS_LSDRAM
+	size += CONFIG_SYS_SDRAM1_SIZE;
+	ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+#endif /* CONFIG_SYS_LSDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
+	return (size * 1024 * 1024);
+}
diff --git a/u-boot/board/ep8260/ep8260.h b/u-boot/board/ep8260/ep8260.h
new file mode 100644
index 0000000..3032b14
--- /dev/null
+++ b/u-boot/board/ep8260/ep8260.h
@@ -0,0 +1,24 @@
+#ifndef __EP8260_H__
+#define __EP8260_H__
+
+typedef struct tt_ep_regs {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+	volatile unsigned char bcsr6;
+	volatile unsigned char bcsr7;
+	volatile unsigned char bcsr8;
+	volatile unsigned char bcsr9;
+	volatile unsigned char bcsr10;
+	volatile unsigned char bcsr11;
+	volatile unsigned char bcsr12;
+	volatile unsigned char bcsr13;
+	volatile unsigned char bcsr14;
+	volatile unsigned char bcsr15;
+} t_ep_regs;
+typedef t_ep_regs *tp_ep_regs;
+
+#endif
diff --git a/u-boot/board/ep8260/flash.c b/u-boot/board/ep8260/flash.c
new file mode 100644
index 0000000..2a81de5
--- /dev/null
+++ b/u-boot/board/ep8260/flash.c
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * Flash Routines for AMD device AM29DL323DB on the EP8260 board.
+ *
+ * This file is based on board/tqm8260/flash.c.
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset(void)
+{
+	if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
+		V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
+		V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size( ulong baseaddr, flash_info_t *info )
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
+	V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
+	V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
+	V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG(baseaddr);		/* manufacturer ID	   */
+	flashtest_l = V_ULONG(baseaddr + 4);
+
+	if ((int)flashtest_h == AMD_MANUFACT) {
+		info->flash_id = FLASH_MAN_AMD;
+	} else {
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash	   */
+	}
+
+	flashtest_h = V_ULONG(baseaddr + 8);	        /* device ID		   */
+	flashtest_l = V_ULONG(baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+		return(0);
+	}
+
+	switch((int)flashtest_h) {
+	case AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;	 /* 4 * 4 MB = 16 MB	*/
+		break;
+	case AMD_ID_LV640U:	/* AMDLV640 and AMDLV641 have same ID */
+		info->flash_id += FLASH_AMLV640U;
+		info->sector_count = 128;
+		info->size = 0x02000000;	/* 4 * 8 MB = 32 MB	*/
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return(0);				/* no or unknown flash	   */
+	}
+
+	if(flashtest_h == AMD_ID_LV640U) {
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+	} else {
+		/* set up sector start adress table (bottom sector type) */
+		for (i = 0; i < 8; i++) {
+			info->start[i] = baseaddr + (i * 0x00008000);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
+		}
+	}
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
+		    (V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
+			info->protect[i] = 1;		/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset();
+	return(info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0>>20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case FLASH_MAN_AMD:	    printf ("AMD ");		    break;
+	default:		    printf ("Unknown Vendor ");	    break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:	printf ("29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("29LV640U (64 M, uniform sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG( info->start[sect] ) = 0x00300030;
+			V_ULONG( info->start[sect] + 4 ) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+ DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);	/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
+		if ((rc = write_dword(info, dp, bb)) != 0)
+		{
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword(info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp  += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
+	}
+	return (write_dword(info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
+{
+	ulong start;
+	ulong cl = 0, ch =0;
+	int flag, i;
+
+	for (ch=0, i=0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word	*/
+	for (cl=0, i=0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & ch)	!= ch
+	    ||(*((vu_long *)(dest + 4)) & cl)	!= cl)
+	{
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
+	V_ULONG( dest ) = ch;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
+	V_ULONG( dest + 4 ) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
+	       ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/ep8260/mii_phy.c b/u-boot/board/ep8260/mii_phy.c
new file mode 100644
index 0000000..c7aa275
--- /dev/null
+++ b/u-boot/board/ep8260/mii_phy.c
@@ -0,0 +1,107 @@
+#include <common.h>
+#include <mii_phy.h>
+#include "ep8260.h"
+
+#define MII_MDIO	0x01
+#define MII_MDCK	0x02
+#define MII_MDIR	0x04
+
+void
+mii_discover_phy(void)
+{
+    int known;
+    unsigned short phy_reg;
+    unsigned long phy_id;
+
+    known = 0;
+    printf("Discovering phy @ 0: ");
+    phy_id = mii_phy_read(2) << 16;
+    phy_id |= mii_phy_read(3);
+    if ((phy_id & 0xFFFFFC00) == 0x00137800) {
+	printf("Level One ");
+	if ((phy_id & 0x000003F0) == 0xE0) {
+	    printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
+	    known = 1;
+	}
+	else printf("unknown type\n");
+    }
+    else printf("unknown OUI = 0x%08lX\n", phy_id);
+
+    phy_reg = mii_phy_read(1);
+    if (!(phy_reg & 0x0004)) printf("Link is down\n");
+    if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
+    if (phy_reg & 0x0002) printf("Jabber condition detected\n");
+    if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
+
+    if (known) {
+	phy_reg = mii_phy_read(17);
+	if (phy_reg & 0x0400)
+	    printf("Phy operating at %d MBit/s in %s-duplex mode\n",
+		phy_reg & 0x4000 ? 100 : 10,
+		phy_reg & 0x0200 ? "full" : "half");
+	else
+	    printf("bad link!!\n");
+/*
+left  off: no link, green 100MBit, yellow 10MBit
+right off: no activity, green full-duplex, yellow half-duplex
+*/
+	mii_phy_write(20, 0x0452);
+    }
+}
+
+unsigned short
+mii_phy_read(unsigned short reg)
+{
+    int i;
+    unsigned short tmp, val = 0, adr = 0;
+    t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
+
+    tmp = 0x6002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    regs->bcsr4 |= MII_MDIR;
+    for (i = 0; i < 16; i++) {
+	val <<= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
+	if (regs->bcsr4 & MII_MDIO) val |= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
+    }
+    return val;
+}
+
+void
+mii_phy_write(unsigned short reg, unsigned short val)
+{
+    int i;
+    unsigned short tmp, adr = 0;
+    t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
+
+    tmp = 0x5002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	val <<= 1;
+    }
+}
diff --git a/u-boot/board/ep82xxm/Makefile b/u-boot/board/ep82xxm/Makefile
new file mode 100644
index 0000000..74b9a35
--- /dev/null
+++ b/u-boot/board/ep82xxm/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ep82xxm/ep82xxm.c b/u-boot/board/ep82xxm/ep82xxm.c
new file mode 100644
index 0000000..c1d6e91
--- /dev/null
+++ b/u-boot/board/ep82xxm/ep82xxm.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * Support for Embedded Planet EP82xxM boards.
+ * Tested on EP82xxM (MPC8270).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <asm/m8260_pci.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CONFIG_SYS_FCC2 1
+#define CONFIG_SYS_FCC3 1
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	     conf      ppar psor pdir podr pdat */
+	/* PA31 */ { 0,		 0,   0,   0,	0,   1 }, /* PA31	     */
+	/* PA30 */ { 0,		 0,   0,   0,	0,   1 }, /* PA30	     */
+	/* PA29 */ { 0,		 0,   0,   0,	0,   1 }, /* PA29	     */
+	/* PA28 */ { 0,		 0,   0,   0,	0,   1 }, /* PA28	     */
+	/* PA27 */ { 0,		 0,   0,   0,	0,   1 }, /* PA27	     */
+	/* PA26 */ { 0,		 0,   0,   0,	0,   1 }, /* PA26	     */
+	/* PA25 */ { 0,		 0,   0,   0,	0,   1 }, /* PA25	     */
+	/* PA24 */ { 0,		 0,   0,   0,	0,   1 }, /* PA24	     */
+	/* PA23 */ { 0,		 0,   0,   0,	0,   1 }, /* PA23	     */
+	/* PA22 */ { 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
+	/* PA21 */ { 0,		 0,   0,   0,	0,   1 }, /* PA21	     */
+	/* PA20 */ { 0,		 0,   0,   0,	0,   1 }, /* PA20	     */
+	/* PA19 */ { 0,		 0,   0,   0,	0,   1 }, /* PA19	     */
+	/* PA18 */ { 0,		 0,   0,   0,	0,   1 }, /* PA18	     */
+	/* PA17 */ { 0,		 0,   0,   0,	0,   1 }, /* PA17	     */
+	/* PA16 */ { 0,		 0,   0,   0,	0,   1 }, /* PA16	     */
+	/* PA15 */ { 0,		 0,   0,   0,	0,   1 }, /* PA15	     */
+	/* PA14 */ { 0,		 0,   0,   0,	0,   1 }, /* PA14	     */
+	/* PA13 */ { 0,		 0,   0,   0,	0,   1 }, /* PA13	     */
+	/* PA12 */ { 0,		 0,   0,   0,	0,   1 }, /* PA12	     */
+	/* PA11 */ { 0,		 0,   0,   0,	0,   1 }, /* PA11	     */
+	/* PA10 */ { 0,		 0,   0,   0,	0,   1 }, /* PA10	     */
+	/* PA9	*/ { 1,		 1,   0,   1,	0,   1 }, /* SMC2 TxD	     */
+	/* PA8	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC2 RxD	     */
+	/* PA7	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA7	     */
+	/* PA6	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA6	     */
+	/* PA5	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA5	     */
+	/* PA4	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA4	     */
+	/* PA3	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA3	     */
+	/* PA2	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA2	     */
+	/* PA1	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA1	     */
+	/* PA0	*/ { 0,		 0,   0,   0,	0,   1 }  /* PA0	     */
+    },
+
+    /* Port B */
+    {	/*	     conf	ppar psor pdir podr pdat */
+	/* PB31 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,	 1,   1,   1,	0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_DIV     */
+	/* PB16 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_ERR     */
+	/* PB15 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_ERR     */
+	/* PB14 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_EN      */
+	/* PB13 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:COL	     */
+	/* PB12 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:CRS	     */
+	/* PB11 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB10 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB9	*/ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB8	*/ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PB7	     */
+	/* PB6	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB5	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB4	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {	/*	     conf	ppar psor pdir podr pdat */
+	/* PC31 */ { 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
+	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
+	/* PC29 */ { 1,		 1,   1,   0,	0,   0 }, /* SCC1 CTS#	     */
+	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
+	/* PC27 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3: TXD[0]    */
+	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
+	/* PC25 */ { 0,		 0,   0,   0,	0,   0 }, /* PC25	     */
+	/* PC24 */ { 0,		 0,   0,   0,	0,   0 }, /* PC24	     */
+	/* PC23 */ { 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
+	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
+	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
+	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
+	/* PC19 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* RxClk (CLK13)   */
+	/* PC18 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* TxClk (CLK14)   */
+	/* PC17 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* RxClk (CLK15)   */
+	/* PC16 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* TxClk (CLK16)   */
+	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
+	/* PC14 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 CD#	     */
+	/* PC13 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CTS#	     */
+	/* PC12 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CD#	     */
+	/* PC11 */ { 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
+	/* PC10 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC3 CD#	     */
+	/* PC9	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC9	     */
+	/* PC8	*/ { 1,		 1,   1,   0,	0,   0 }, /* SCC3 CTS#	     */
+	/* PC7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
+	/* PC6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
+	/* PC5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
+	/* PC4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
+	/* PC3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
+	/* PC2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
+	/* PC1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
+	/* PC0	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
+    },
+
+    /* Port D */
+    {	/*	     conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 RXD	     */
+	/* PD30 */ { 1,		 1,   1,   1,	0,   1 }, /* SCC1 TXD	     */
+	/* PD29 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC1 RTS#	     */
+	/* PD28 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 RXD	     */
+	/* PD27 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC2 TXD	     */
+	/* PD26 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC2 RTS#	     */
+	/* PD25 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC3 RXD	     */
+	/* PD24 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC3 TXD	     */
+	/* PD23 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC3 RTS#	     */
+	/* PD22 */ { 0,		 0,   0,   0,	0,   1 }, /* PD22	     */
+	/* PD21 */ { 0,		 0,   0,   0,	0,   1 }, /* PD21	     */
+	/* PD20 */ { 0,		 0,   0,   0,	0,   1 }, /* PD20	     */
+	/* PD19 */ { 0,		 0,   0,   0,	0,   1 }, /* PD19	     */
+	/* PD18 */ { 0,		 0,   0,   0,	0,   1 }, /* PD18	     */
+	/* PD17 */ { 0,		 0,   0,   0,	0,   1 }, /* PD17	     */
+	/* PD16 */ { 0,		 0,   0,   0,	0,   1 }, /* PD16	     */
+	/* PD15 */ { 1,		 1,   1,   0,	1,   1 }, /* I2C SDA	     */
+	/* PD14 */ { 1,		 1,   1,   0,	1,   1 }, /* I2C SCL	     */
+	/* PD13 */ { 0,		 0,   0,   0,	0,   1 }, /* PD13	     */
+	/* PD12 */ { 0,		 0,   0,   0,	0,   1 }, /* PD12	     */
+	/* PD11 */ { 0,		 0,   0,   0,	0,   1 }, /* PD11	     */
+	/* PD10 */ { 0,		 0,   0,   0,	0,   1 }, /* PD10	     */
+	/* PD9	*/ { 1,		 1,   0,   1,	0,   1 }, /* SMC1 TxD	     */
+	/* PD8	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC1 RxD	     */
+	/* PD7	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC1 SMSYN      */
+	/* PD6	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD6	     */
+	/* PD5	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD5	     */
+	/* PD4	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD4	     */
+	/* PD3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
+    }
+};
+
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+	bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+	bcsr[7] |= 0x10;
+#endif
+
+#if CONFIG_SYS_FCC3
+	bcsr[8] |= 0xC0;
+#endif /* CONFIG_SYS_FCC3 */
+#if CONFIG_SYS_FCC2
+	bcsr[8] |= 0x30;
+#endif /* CONFIG_SYS_FCC2 */
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	/* Size in MB of SDRAM populated on board*/
+	long int msize = 256;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	uint psdmr = CONFIG_SYS_PSDMR;
+	int i;
+
+	unsigned char	ramtmp;
+	unsigned char	*ramptr1 = (unsigned char *)0x00000110;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+udelay(400);
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
+	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
+	memctl->memc_psdmr = psdmr;
+
+udelay(400);
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	ramtmp = *ramptr1;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++) {
+		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	}
+	ramtmp = *ramptr1;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramptr1  = 0xFF;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[0]) {
+	case 0x0A:
+		printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
+		break;
+	default:
+		printf("unknown: ID=%02X\n", bcsr[0]);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/u-boot/board/ep88x/Makefile b/u-boot/board/ep88x/Makefile
new file mode 100644
index 0000000..70205f1
--- /dev/null
+++ b/u-boot/board/ep88x/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ep88x/ep88x.c b/u-boot/board/ep88x/ep88x.c
new file mode 100644
index 0000000..7e95007
--- /dev/null
+++ b/u-boot/board/ep88x/ep88x.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP88x boards.
+ * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM uses two Micron chips.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
+	0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
+	0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
+	0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
+	0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
+	0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0x0FEA8034, 0x1FB54034,	0xFFFFCC34, 0xFFFFCC05
+};
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	bcsr[0] |= 0x0C; /* Turn the LEDs off */
+	bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
+			    flash detection by CFI driver
+			 */
+
+#if defined(CONFIG_8xx_CONS_SMC1)
+	bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#if defined(CONFIG_8xx_CONS_SCC2)
+	bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC1
+	bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC2
+	bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long int msize;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
+
+	memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */
+	udelay(100);
+
+	/* Run MRS pattern from location 0x36 */
+	memctl->memc_mar = 0x88;
+	memctl->memc_mcr = 0x80002236;
+	udelay(100);
+
+	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
+	memctl->memc_or1  |= ~(msize - 1);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[15]) {
+	case 0xE7:
+		puts("EP88xC 1.0");
+		break;
+	default:
+		printf("unknown ID=%02X", bcsr[15]);
+	}
+	printf("  CPLD revision %d\n", bcsr[14]);
+
+	return 0;
+}
diff --git a/u-boot/board/ep88x/u-boot.lds b/u-boot/board/ep88x/u-boot.lds
new file mode 100644
index 0000000..851348e
--- /dev/null
+++ b/u-boot/board/ep88x/u-boot.lds
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text          :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/u-boot/board/esd/adciop/Makefile b/u-boot/board/esd/adciop/Makefile
new file mode 100644
index 0000000..7b3d6dc
--- /dev/null
+++ b/u-boot/board/esd/adciop/Makefile
@@ -0,0 +1,54 @@
+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/adciop/adciop.c b/u-boot/board/esd/adciop/adciop.c
new file mode 100644
index 0000000..8e00785
--- /dev/null
+++ b/u-boot/board/esd/adciop/adciop.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include "adciop.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* ------------------------------------------------------------------------- */
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * Set port pin in escc2 to keep living, and configure user led output
+	 */
+	*(unsigned char *) 0x2000033e = 0x77;	/* ESCC2: PCR bit3=pwr on, bit7=led out */
+	*(unsigned char *) 0x2000033c = 0x88;	/* ESCC2: PVR pwr on, led off */
+
+	/*
+	 * Init pci regs
+	 */
+	*(unsigned long *) 0x50000304 = 0x02900007;	/* enable mem/io/master bits */
+	*(unsigned long *) 0x500001b4 = 0x00000000;	/* disable pci interrupt output enable */
+	*(unsigned long *) 0x50000354 = 0x00c05800;	/* disable emun interrupt output enable */
+	*(unsigned long *) 0x50000344 = 0x00000000;	/* disable pme interrupt output enable */
+	*(unsigned long *) 0x50000310 = 0x00000000;	/* pcibar0 */
+	*(unsigned long *) 0x50000314 = 0x00000000;	/* pcibar1 */
+	*(unsigned long *) 0x50000318 = 0x00000000;	/* pcibar2 */
+
+	return 0;
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "ADCIOP", 6)) {
+		puts ("### No HW ID - assuming ADCIOP\n");
+		return (1);
+	}
+
+	puts (str);
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/esd/adciop/adciop.h b/u-boot/board/esd/adciop/adciop.h
new file mode 100644
index 0000000..5fc313a
--- /dev/null
+++ b/u-boot/board/esd/adciop/adciop.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/adciop/flash.c b/u-boot/board/esd/adciop/flash.c
new file mode 100644
index 0000000..9559efb
--- /dev/null
+++ b/u-boot/board/esd/adciop/flash.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
+		      FLASH_BASE0_PRELIM+size_b0-1,
+		      &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len,
+			      FLASH_BASE0_PRELIM+size_b0+size_b1-1,
+			      &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
+			      FLASH_BASE0_PRELIM+size_b0-1,
+			      &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/u-boot/board/esd/apc405/Makefile b/u-boot/board/esd/apc405/Makefile
new file mode 100644
index 0000000..df391da
--- /dev/null
+++ b/u-boot/board/esd/apc405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o \
+	../common/misc.o \
+	../common/auto_update.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/apc405/apc405.c b/u-boot/board/esd/apc405/apc405.c
new file mode 100644
index 0000000..def8a4f
--- /dev/null
+++ b/u-boot/board/esd/apc405/apc405.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+#include <asm/4xx_pci.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef FPGA_DEBUG
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#ifdef CONFIG_LCD_USED
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+#include "../common/s1d13505_640_480_16bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#endif /* CONFIG_LCD_USED */
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+	{"preinst.img", 0, -1, AU_SCRIPT},
+	{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
+	{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
+	{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
+	{"work.img", 0xfe500000, 0x01400000, AU_NOR},
+	{"data.img", 0xff900000, 0x00580000, AU_NOR},
+	{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
+	{"postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+int board_revision(void)
+{
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
+
+	/* wait some time before reading input */
+	udelay(1000);
+
+	/* get config bits */
+	value = in_be32((void*)GPIO0_IR) & 0x001c0000;
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	switch (value) {
+	case 0x001c0000:
+		/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
+		return 2;
+	case 0x000c0000:
+		/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
+		return 3;
+	case 0x00180000:
+		/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
+		return 6;
+	case 0x00140000:
+		/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
+		return 8;
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+int board_early_init_f (void)
+{
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic
+	 */
+	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
+	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * New boards have a single 32MB flash connected to CS0
+	 * instead of two 16MB flashes on CS0+1.
+	 */
+	if (board_revision() >= 8) {
+		/* disable CS1 */
+		mtebc(PB1AP, 0);
+		mtebc(PB1CR, 0);
+
+		/* resize CS0 to 32MB */
+		mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
+		mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	if (gd->board_type >= 8)
+		cfi_flash_num_flash_banks = 1;
+
+	return 0;
+}
+
+#define FUJI_BASE    0xf0100200
+#define LCDBL_PWM    0xa0
+#define LCDBL_PWMMIN 0xa4
+#define LCDBL_PWMMAX 0xa8
+
+int misc_init_r(void)
+{
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+	u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
+	u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
+	u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long CPC0_CR0Reg;
+	char *str;
+	uchar *logo_addr;
+	ulong logo_size;
+	ushort minb, maxb;
+	int result;
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: "
+			       "INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: "
+			       "INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: "
+			       "DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len + 3;
+		}
+		putc('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index = 0; index < 1000; index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	/* restore gpio/cs settings */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index + 1]));
+		index += len + 3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Write board revision in FPGA
+	 */
+	out_be16(fpga_ctrl2,
+		 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
+	for (i=0;i<100;i++)
+		udelay(1000);
+	udelay(1000);
+	out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8(duart0_mcr, 0x08);
+	out_8(duart1_mcr, 0x08);
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	str = getenv("splashimage");
+	if (str) {
+		logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
+		logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+	} else {
+		logo_addr = logo_bmp;
+		logo_size = sizeof(logo_bmp);
+	}
+
+	if (gd->board_type >= 6) {
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				  regs_13505_640_480_16bpp,
+				  sizeof(regs_13505_640_480_16bpp) /
+				  sizeof(regs_13505_640_480_16bpp[0]),
+				  logo_addr, logo_size);
+		if (result && str) {
+			/* retry with internal image */
+			logo_addr = logo_bmp;
+			logo_size = sizeof(logo_bmp);
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				 regs_13505_640_480_16bpp,
+				 sizeof(regs_13505_640_480_16bpp) /
+				 sizeof(regs_13505_640_480_16bpp[0]),
+				 logo_addr, logo_size);
+		}
+	} else {
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				  regs_13806_640_480_16bpp,
+				  sizeof(regs_13806_640_480_16bpp) /
+				  sizeof(regs_13806_640_480_16bpp[0]),
+				  logo_addr, logo_size);
+		if (result && str) {
+			/* retry with internal image */
+			logo_addr = logo_bmp;
+			logo_size = sizeof(logo_bmp);
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				 regs_13806_640_480_16bpp,
+				 sizeof(regs_13806_640_480_16bpp) /
+				 sizeof(regs_13806_640_480_16bpp[0]),
+				 logo_addr, logo_size);
+		}
+	}
+
+	/*
+	 * Reset microcontroller and setup backlight PWM controller
+	 */
+	out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
+	for (i=0;i<10;i++)
+		udelay(1000);
+	out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
+
+	minb = 0;
+	maxb = 0xff;
+	str = getenv("lcdbl");
+	if (str) {
+		minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
+		if (str && (*str=',')) {
+			str++;
+			maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
+		} else
+			minb = 0;
+
+		out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
+		out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
+
+		printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
+	}
+	out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
+
+	/*
+	 * fix environment for field updated units
+	 */
+	if (getenv("altbootcmd") == NULL) {
+		setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+		setenv("usbargs", CONFIG_SYS_USB_ARGS);
+		setenv("bootcmd", CONFIG_BOOTCOMMAND);
+		setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+		setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+		setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
+		saveenv();
+	}
+
+	return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming APC405");
+	} else {
+		puts(str);
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev. 1.%ld\n", gd->board_type);
+
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {
+		out_be16(fpga_mode,
+			 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {
+		out_be16(fpga_mode,
+			 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	unsigned short tmp;
+	int i;
+
+	/*
+	 * reset PCI bus
+	 * This is required to make some very old Linux OHCI driver
+	 * work after U-Boot has used the OHCI controller.
+	 */
+	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
+	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
+
+	for (i = 0; i < 100; i++)
+		udelay(1000);
+
+	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
+	return 0;
+}
+
+int usb_board_init_fail(void)
+{
+	usb_board_stop();
+	return 0;
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/u-boot/board/esd/apc405/fpgadata.c b/u-boot/board/esd/apc405/fpgadata.c
new file mode 100644
index 0000000..0b4664e
--- /dev/null
+++ b/u-boot/board/esd/apc405/fpgadata.c
@@ -0,0 +1,2004 @@
+  0x1f,0x8b,0x08,0x08,0x49,0xe1,0xdb,0x46,0x00,0x03,0x61,0x62,0x67,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x33,0x2e,0x62,0x69,0x74,0x00,0xed,0xfd,0x7d,0x7c,0x14,0xd7,
+  0x75,0x3f,0x8e,0x9f,0xb9,0x33,0x12,0xa3,0xdd,0x95,0x76,0xf4,0xe4,0xac,0x6d,0x20,
+  0xa3,0x95,0x20,0x6b,0xb2,0x88,0x45,0x60,0x8c,0xb1,0x90,0x06,0x49,0x26,0x8a,0x4d,
+  0x8c,0x4c,0xdd,0x84,0xf6,0x9b,0xa6,0x6b,0x42,0x53,0xda,0x17,0x49,0x65,0x27,0x9f,
+  0x96,0xe6,0x93,0x26,0x57,0x2b,0x81,0x85,0x21,0xf6,0x1a,0x93,0x46,0x4e,0x69,0xba,
+  0x60,0xea,0xc8,0x09,0x4d,0x96,0x07,0x9b,0x07,0x53,0x3c,0xc2,0x32,0x11,0x18,0xdb,
+  0x0a,0x71,0x53,0xf9,0x21,0xf6,0x9a,0xc8,0x44,0xb6,0x89,0x23,0xdb,0xc4,0x11,0xcf,
+  0xdf,0x73,0xee,0xec,0x3c,0xec,0x4a,0x24,0xe9,0xe7,0xf3,0xf3,0xef,0xf7,0xc7,0x2f,
+  0x9b,0x3f,0x72,0x3c,0x7b,0x35,0xcc,0x3d,0x7b,0xe7,0xdc,0xf7,0x3d,0xe7,0x7d,0xce,
+  0x81,0xa2,0xe0,0xa8,0xf5,0x3f,0x00,0xe9,0x4e,0xd0,0xee,0x5c,0xf1,0xd7,0x73,0x63,
+  0xd7,0xff,0xe5,0xec,0xbf,0x8c,0xcd,0xa9,0xfd,0xd2,0xe7,0x57,0xc2,0x0a,0xf0,0xd5,
+  0x7d,0xf9,0xfa,0xd8,0x17,0xfe,0xba,0xee,0xfa,0x79,0xf0,0x79,0xf0,0xd7,0xc5,0x62,
+  0x37,0xcc,0xd2,0x6f,0x9c,0xa5,0xcf,0x81,0x95,0x50,0x34,0xbb,0x6e,0x41,0x5d,0xdd,
+  0x82,0x39,0xd7,0xc3,0x5f,0x81,0x54,0x1a,0xb8,0x8c,0x9f,0xef,0x3f,0xf4,0xa7,0x5f,
+  0x88,0x01,0x97,0x00,0x60,0x52,0x4c,0x8a,0xd3,0xff,0xfb,0x63,0x92,0x2e,0x01,0x6f,
+  0x9c,0x19,0x03,0x93,0xfe,0x1b,0xb2,0xdf,0x17,0xc5,0x40,0xf7,0xfe,0xb7,0x14,0x03,
+  0x03,0xda,0xa0,0x41,0x81,0x32,0xf8,0xfd,0x1f,0x09,0x14,0x6e,0xcb,0xff,0xd3,0xf1,
+  0xec,0x0f,0x18,0x8f,0x9f,0xff,0xe3,0xf1,0x7f,0xc8,0xf3,0x00,0x28,0xff,0xc7,0xe3,
+  0xb5,0x3f,0x6c,0xbc,0x2d,0x5c,0xd6,0xa0,0x02,0x0a,0x40,0x22,0xed,0x0a,0x01,0x50,
+  0xd1,0x1a,0x7e,0xef,0x5e,0x41,0xa1,0xb1,0xdf,0xbe,0xbf,0x59,0x70,0x09,0x2e,0xf3,
+  0xeb,0xe3,0xc5,0x63,0xf2,0x57,0xe0,0x35,0xde,0x98,0x09,0x8e,0xc9,0x74,0x65,0x61,
+  0xa6,0xe4,0x8c,0x3c,0x07,0x2e,0xeb,0x8d,0x03,0xb7,0x9e,0xa9,0x8e,0x49,0xed,0xd9,
+  0xf1,0x5c,0x7b,0x07,0x9e,0xe0,0x61,0x43,0xdd,0xc7,0x6a,0x60,0x03,0xaf,0xcd,0xf8,
+  0xf7,0x31,0xba,0x52,0x9b,0x51,0xff,0x17,0xd3,0xe1,0x49,0xf3,0xa6,0x51,0x3f,0x0a,
+  0x8a,0x9e,0x1d,0xdf,0x5d,0x70,0x1c,0x76,0x43,0xed,0xa2,0xa2,0x18,0x6b,0x81,0x07,
+  0x21,0x6a,0xfa,0x62,0x8c,0xae,0x44,0x4d,0x7f,0x1d,0x03,0xfe,0xb0,0x16,0xed,0xf7,
+  0xd5,0x41,0x18,0xd7,0x43,0xf6,0x79,0x2a,0x77,0xc0,0x13,0x30,0x23,0xa3,0xa6,0x99,
+  0x0c,0x1b,0xa0,0xd6,0xf4,0xa7,0xd9,0x69,0xbc,0x52,0x6b,0x5e,0x97,0x6e,0xfa,0x18,
+  0x3c,0xc1,0x66,0x98,0xd7,0xa6,0x59,0x4c,0x89,0xdb,0x13,0xae,0x3c,0x0d,0xe7,0xa1,
+  0xa1,0xbd,0x38,0x56,0xfe,0x05,0xf6,0x32,0x34,0x98,0xc1,0xb4,0x4c,0x57,0xea,0x51,
+  0x60,0xd3,0xe9,0x2b,0x73,0x69,0x5a,0x06,0xc5,0x7e,0xfe,0x8c,0x74,0x10,0x2e,0xc3,
+  0x0d,0xc6,0xd2,0x51,0x79,0x18,0x85,0x46,0x33,0x38,0x2a,0x5f,0x10,0x42,0xc9,0xa8,
+  0x7c,0x46,0xbb,0x0c,0x37,0x99,0x05,0xa3,0xf2,0x18,0xd8,0xf7,0x37,0xb4,0x1d,0x74,
+  0x13,0xa3,0x24,0x2d,0x4f,0x53,0xdf,0x76,0xef,0xdf,0x30,0x10,0x88,0x09,0x61,0x9e,
+  0x19,0x8c,0x55,0x6b,0xce,0x7c,0x07,0x0a,0xa2,0xb0,0xbb,0x3b,0x3a,0xa6,0xee,0x49,
+  0x4c,0x33,0x72,0x9e,0x3f,0x34,0xca,0xa2,0xf0,0x24,0x9f,0x35,0x50,0x32,0xda,0x7c,
+  0x37,0xfe,0x28,0xd9,0xe7,0x29,0x58,0x42,0xda,0xb8,0xdb,0x37,0x8f,0x29,0xf0,0x30,
+  0xa9,0xc5,0xd6,0x4f,0x6f,0xac,0xb0,0x45,0xda,0x9d,0xae,0x39,0x71,0x6b,0x8c,0xcd,
+  0xc7,0xdf,0xce,0xfa,0xc4,0xa5,0xa9,0xb0,0xb7,0x63,0x56,0x5c,0x5d,0xc3,0xae,0xd2,
+  0xef,0xe1,0x33,0x33,0xfe,0x35,0xec,0x55,0xd8,0xcb,0x67,0x0e,0x47,0xf0,0x0a,0x09,
+  0x99,0x6b,0xd6,0xb0,0x56,0xe7,0xfe,0xad,0x6a,0x00,0xde,0x47,0x6d,0x94,0xc4,0x26,
+  0x29,0xf0,0x0b,0x52,0x4b,0x4c,0x16,0xf7,0x3f,0xac,0xc6,0x64,0xc3,0x78,0x5f,0x9b,
+  0xdb,0x17,0x8c,0x4d,0x2a,0x73,0x56,0xbd,0x31,0x85,0xf4,0xd3,0xc8,0x83,0x77,0xf9,
+  0x2f,0x18,0x39,0xfa,0xf9,0xe8,0x99,0xd2,0x0b,0xa5,0x97,0x8d,0xc6,0xfe,0xe0,0xbb,
+  0xf2,0x60,0xa1,0xad,0x9f,0xde,0x02,0xa1,0x0d,0x43,0x4d,0xcb,0x01,0x78,0xc6,0xab,
+  0xff,0xc0,0xee,0xe6,0x61,0x38,0x1f,0xab,0x1f,0x08,0x1c,0x90,0x67,0x38,0xfa,0x6f,
+  0x2d,0xdd,0x02,0x7b,0x61,0xa6,0xa1,0xb6,0x37,0x55,0xc0,0x3d,0x30,0xd3,0xf4,0xb7,
+  0xb3,0x57,0xe8,0x8a,0xa9,0xb6,0xd7,0xbd,0xa0,0xec,0x55,0x66,0xbe,0xa0,0xfe,0x86,
+  0x95,0x39,0xbf,0xaf,0x09,0xdf,0x15,0x93,0xc2,0xf9,0x36,0x80,0x77,0xbe,0xa6,0x6a,
+  0x09,0xd7,0x8d,0x44,0xbe,0xca,0xda,0xc1,0xd6,0x7f,0x6b,0x85,0x58,0x6f,0x7c,0x20,
+  0xe6,0x2b,0x89,0x75,0x7a,0xf5,0xa9,0xa2,0x50,0x43,0x42,0x77,0x8c,0x2d,0x03,0x7b,
+  0xbd,0x8d,0x54,0xf6,0xc2,0x39,0x9c,0xaf,0xaa,0xcb,0x0b,0xd8,0x31,0xfc,0xc3,0x60,
+  0x4a,0x1e,0xc1,0x2b,0xf5,0x3c,0x90,0xaa,0x1e,0xe3,0xe7,0xa0,0x81,0xab,0x29,0xff,
+  0x57,0xc1,0x79,0x7e,0xc8,0xc0,0x18,0x34,0xc0,0x2c,0x2e,0x67,0x0c,0x12,0x82,0x28,
+  0x38,0x57,0x60,0x14,0xa6,0xd2,0x95,0x4d,0xce,0xf3,0xa8,0xda,0x30,0x9c,0x85,0x86,
+  0x55,0x81,0x9e,0xf2,0x47,0xf8,0x51,0x54,0x54,0x30,0x29,0xd3,0x95,0x05,0xf1,0x12,
+  0x14,0xa4,0xb3,0x50,0x67,0xdc,0x96,0x94,0x0f,0x3b,0xcf,0xc3,0x95,0x95,0xb0,0x5f,
+  0xab,0xbd,0x53,0xed,0x61,0xd3,0xc3,0xeb,0xa1,0xd6,0xf0,0x27,0xd9,0x30,0xec,0x47,
+  0xe1,0x1a,0x12,0x6e,0x04,0xfd,0x0e,0x35,0xc9,0x32,0x95,0xb6,0x59,0x08,0x15,0xd4,
+  0xd0,0xb7,0x83,0xea,0x03,0xb8,0x7e,0xbc,0xe3,0x5b,0x9a,0x92,0xe1,0x61,0x75,0x7f,
+  0x77,0xb8,0xe9,0xde,0x24,0x3b,0xe2,0xac,0x07,0x55,0x51,0x60,0x27,0x44,0x8d,0x88,
+  0xe6,0x53,0x12,0x1d,0x28,0xf8,0x35,0xd6,0x0f,0x3b,0x25,0x7c,0x31,0xcb,0x58,0xbf,
+  0xb4,0x53,0x8f,0xb7,0xaa,0x65,0xec,0xb0,0x64,0x3f,0xff,0xbe,0xe2,0x38,0xcd,0xae,
+  0x22,0xca,0xcb,0xb7,0x1a,0x03,0xee,0x7c,0x17,0x80,0x6f,0x6d,0xf3,0xeb,0xc6,0x3e,
+  0xd8,0x05,0x25,0x6b,0xe5,0x77,0x64,0x7b,0xfd,0xf4,0x4c,0xa1,0xd9,0x2d,0x34,0x83,
+  0x9a,0x7c,0xc6,0x38,0xeb,0xce,0x17,0x85,0x07,0x70,0x21,0x9d,0xd5,0xa6,0xb6,0xa0,
+  0x70,0x4a,0xb6,0xf5,0xd9,0x53,0x30,0x0c,0x3f,0x87,0x85,0x46,0x60,0x50,0x1e,0x8e,
+  0x7b,0xf4,0xb3,0xd0,0x28,0x79,0x50,0xae,0x69,0x79,0x43,0xa9,0x34,0x82,0x9b,0xe4,
+  0x23,0xce,0xfa,0x99,0xaf,0xe1,0xbf,0xce,0x6a,0xa1,0x9b,0xb3,0x01,0xe8,0x86,0x5a,
+  0xf0,0x73,0x96,0x81,0x7d,0x50,0x2b,0xa9,0x9d,0x68,0x7f,0x06,0x20,0xac,0x6c,0x48,
+  0x24,0x9e,0x2b,0xb4,0xf5,0xa9,0x16,0xf4,0xd3,0x7c,0x6f,0x51,0xb5,0xa6,0x7e,0x4e,
+  0xf3,0x2d,0x12,0xf3,0x45,0x01,0xe7,0xab,0x74,0x6d,0xad,0xd0,0x0d,0x7f,0x39,0xce,
+  0xd7,0xbe,0x7f,0xa8,0x72,0x3b,0x3c,0x8a,0x6a,0x8c,0x24,0xf5,0xe1,0x1c,0x7d,0x1a,
+  0x6a,0xd2,0xa7,0xf0,0x87,0x60,0x05,0x5d,0x39,0xe2,0xd8,0x87,0x54,0xe5,0xb0,0xfa,
+  0x10,0xda,0x9f,0x25,0x49,0xe9,0x97,0xcc,0xf3,0xfc,0x53,0x0d,0xfc,0x7d,0x6b,0xe0,
+  0x4d,0x78,0x1c,0xaf,0x48,0x23,0x8e,0x7d,0x88,0x48,0xdb,0xf1,0x6e,0x0d,0x5f,0x08,
+  0x26,0x13,0xcf,0xe5,0xe8,0x67,0x51,0x50,0xc3,0x7f,0xe8,0x75,0x68,0x68,0x9a,0x94,
+  0xc4,0x85,0x68,0x7f,0x22,0x5a,0x8a,0xf4,0xaf,0xdd,0xc6,0x9b,0xef,0xe4,0xb6,0xfe,
+  0x25,0x5a,0x6f,0xc5,0xf4,0x43,0x0c,0xc0,0xe3,0xb0,0x91,0xcb,0xc7,0xdc,0xfb,0x17,
+  0x44,0xe0,0x40,0xf7,0xac,0x6e,0x35,0x93,0x78,0x9b,0xdf,0x8b,0xeb,0xd9,0x9f,0x62,
+  0x23,0x70,0x00,0x66,0xee,0x50,0x51,0x60,0xaf,0xf2,0xea,0x54,0x71,0xca,0x7b,0x7f,
+  0xb4,0x3f,0x0f,0xf0,0xda,0x51,0x9f,0xce,0x96,0x40,0xa7,0x14,0xed,0xb3,0xdf,0x97,
+  0x51,0xb4,0xd8,0x4b,0xe0,0xc1,0x78,0xfc,0x05,0x35,0x56,0x78,0xcc,0xb1,0x3f,0x29,
+  0x69,0x32,0x3c,0x06,0xb3,0xcc,0xd6,0x36,0x36,0x24,0xde,0x5f,0xd9,0x7a,0x7f,0xbf,
+  0x68,0xb6,0xb6,0x5f,0xf5,0x0a,0x54,0xaa,0xd7,0xc5,0x8b,0xee,0x2a,0x1c,0xd0,0xec,
+  0xf5,0xd6,0xab,0x4e,0x85,0xdf,0xd0,0x6e,0xd2,0x3a,0x69,0x99,0xf1,0x63,0x14,0xe4,
+  0x35,0x32,0xbd,0xb6,0x0b,0x33,0xc5,0x6b,0x3a,0x2f,0x29,0x3f,0xe6,0x77,0x65,0x02,
+  0x6b,0xe4,0x63,0x8e,0xfd,0x51,0xa7,0x08,0x7b,0x0b,0xa8,0x96,0xd7,0xd9,0x79,0x8f,
+  0xbd,0x35,0x83,0xbb,0xe4,0xd3,0x91,0x37,0x95,0x15,0x06,0x0a,0x87,0x1d,0xfb,0x63,
+  0xe0,0xfe,0x75,0x91,0x2f,0xd4,0x03,0x43,0x8c,0xb6,0x2d,0xda,0xbf,0xfe,0xe4,0x90,
+  0x46,0xfb,0x57,0xf1,0x58,0xe7,0xa5,0xaa,0xff,0xe6,0x73,0x32,0x81,0x0b,0xf2,0xa0,
+  0xf3,0xfe,0xf6,0xa2,0xfd,0x79,0x0c,0x66,0x2e,0x9f,0xd9,0xc6,0x06,0xbb,0xf6,0xe6,
+  0xda,0x1f,0xf6,0x4a,0xd5,0xda,0x78,0x15,0xf7,0xb5,0x87,0xdf,0x72,0xec,0x8f,0x06,
+  0x34,0x7e,0x96,0x11,0x6a,0x63,0x2f,0x40,0x76,0xbc,0xb0,0x60,0x66,0x51,0x3b,0xbb,
+  0x00,0xeb,0x40,0xef,0x57,0xef,0x62,0xa6,0xf3,0xbe,0xc7,0xd1,0xfe,0xe0,0xea,0xd2,
+  0x71,0x99,0x3d,0x65,0xec,0xf6,0xda,0x9f,0x48,0x3a,0xfc,0x9c,0xce,0x41,0xa7,0x1d,
+  0xf0,0x45,0xc5,0x5e,0x9f,0xbd,0xb8,0xdf,0x9d,0x25,0x6b,0x99,0xb4,0xa7,0x99,0x96,
+  0x85,0x06,0xcc,0xe2,0x51,0xf9,0x22,0xbc,0x0c,0xbb,0xcc,0xc0,0xa8,0xec,0x3e,0x0f,
+  0x87,0xd3,0xb4,0x5a,0x8e,0x93,0x7e,0xb8,0x57,0x3f,0x83,0x24,0xa8,0x67,0x0d,0x71,
+  0x25,0xe3,0xda,0x13,0xed,0x02,0x5c,0x84,0xc6,0x78,0xc9,0xa0,0xfc,0x0a,0x3c,0xef,
+  0xb5,0xe7,0xd1,0x51,0xb9,0x1e,0x2e,0x9a,0x0b,0x8d,0xdb,0xda,0xcb,0xa1,0xc5,0x1e,
+  0xdf,0xa1,0xac,0xa6,0xd5,0x5e,0xa1,0x7e,0x97,0x9d,0xe4,0xee,0xfe,0x25,0x45,0xdb,
+  0x8b,0xd3,0xbe,0x28,0xec,0x33,0x6a,0xe3,0xb8,0x35,0xa7,0xda,0x6c,0xfb,0xc3,0x71,
+  0xbf,0xdb,0xcf,0x6b,0x0d,0x5f,0x4f,0xd9,0x69,0x77,0xbf,0xfb,0x17,0xa8,0x3d,0x86,
+  0xc3,0xa2,0xf0,0xa8,0x52,0x9b,0xf1,0xa5,0x0b,0x75,0x67,0xfd,0xa8,0x4a,0x00,0xf5,
+  0x83,0x6f,0x93,0xd6,0x64,0xb2,0x1c,0xfb,0x5c,0x14,0x5b,0x46,0x5f,0x45,0x39,0x1a,
+  0xea,0x84,0x64,0xaf,0x07,0x5e,0xbc,0x5a,0x58,0x8f,0x12,0xd2,0xcf,0x06,0xef,0x7a,
+  0x58,0x32,0x5a,0x5d,0x8f,0xef,0x57,0x03,0x6d,0xdc,0xc0,0xec,0xe7,0x49,0x4d,0x11,
+  0xf3,0x85,0xe0,0xa0,0x3c,0x9a,0xb3,0xbf,0xf3,0x92,0x51,0xf6,0x8a,0x7a,0x41,0x5c,
+  0xa9,0x1e,0x61,0x0e,0xde,0x10,0xf8,0x67,0x61,0xaa,0xd8,0x82,0x3d,0xb8,0x7e,0xde,
+  0x23,0x01,0xd5,0x12,0x7d,0x4f,0xae,0x83,0x57,0x3a,0xae,0xd7,0xef,0x3b,0x2a,0x8f,
+  0xca,0xb9,0xf8,0xa7,0x36,0xe5,0xc0,0x1e,0x4b,0x80,0x92,0xf6,0xc0,0x59,0xc4,0x1b,
+  0xdd,0x3c,0x5c,0xd5,0x9a,0x40,0x8b,0x64,0xaf,0x07,0x0b,0xff,0x44,0x79,0x91,0x03,
+  0x7b,0x66,0xa3,0xf0,0xa0,0x1e,0x6d,0xc1,0x2b,0x35,0x15,0x49,0x16,0x96,0xd4,0x3a,
+  0x76,0x32,0x0f,0xff,0xe0,0x6b,0x6b,0xc3,0x06,0x5b,0x68,0xef,0x4e,0xb3,0x2f,0xa0,
+  0x06,0x56,0x80,0xca,0xd9,0xa8,0xb3,0x1e,0x0c,0x0b,0xff,0xe8,0xc5,0xe9,0x6a,0x7b,
+  0xfd,0x88,0xf1,0x0d,0xf1,0xe2,0x98,0x2c,0xc3,0xcb,0xe6,0xbc,0x8f,0x04,0x52,0xf2,
+  0x60,0x1e,0xfe,0x69,0xec,0xc5,0x33,0xc0,0xd7,0x2c,0xfd,0xa4,0xb3,0xeb,0xe1,0xfe,
+  0x51,0x79,0x0f,0x7c,0x7d,0xd1,0x47,0xab,0x8a,0xdf,0x93,0xd6,0xe4,0xe3,0x9f,0x64,
+  0x20,0xed,0xae,0xcf,0xa8,0x78,0x43,0x03,0xe9,0x9f,0xfe,0x0a,0xed,0xf9,0x0c,0x76,
+  0xdf,0x1e,0x7f,0x2e,0xfe,0xa1,0xe7,0x57,0x9d,0xe7,0x27,0xd8,0xf3,0x04,0x6a,0x60,
+  0xca,0x28,0x7b,0x47,0xd9,0xdd,0x16,0x5d,0xa3,0xee,0x6b,0xaa,0xcb,0xc7,0x3f,0xc6,
+  0x75,0x8e,0x7e,0x62,0xbe,0x00,0xec,0x56,0xa2,0xf1,0xd6,0x58,0xd8,0x44,0xc4,0xb8,
+  0x1a,0x70,0x87,0x5a,0xe3,0xac,0x1f,0x9d,0xf0,0x4f,0x62,0x96,0x2e,0x65,0x61,0x00,
+  0xe1,0x01,0xbc,0xc2,0x67,0x9d,0x2c,0xfa,0x2a,0xfb,0x99,0x8e,0x82,0x5e,0xb4,0x26,
+  0x91,0x8f,0x7f,0xbe,0x66,0x14,0x5b,0xb0,0x47,0xe0,0x1f,0x81,0x88,0x5a,0xd4,0xd9,
+  0x9d,0x7d,0x37,0xff,0xb4,0xac,0xde,0x98,0x94,0x96,0x97,0xd9,0xcb,0x0d,0x8c,0xe2,
+  0x83,0xf0,0x0d,0xf8,0x86,0x51,0x62,0xbf,0x26,0xf6,0xfa,0x79,0x3a,0xf8,0xfe,0x53,
+  0xb8,0x7a,0xa0,0xb1,0x65,0xea,0xbb,0xd5,0x49,0x47,0xff,0x36,0xfe,0x09,0x7a,0xf4,
+  0x93,0xbd,0xf2,0x38,0xda,0xff,0xff,0x4d,0x86,0x7a,0x9f,0x3c,0x83,0xe5,0xe1,0x1f,
+  0x70,0xcc,0x8e,0xff,0xab,0xb6,0x50,0x97,0xa8,0x10,0x5f,0x45,0xda,0x0b,0xcb,0x1c,
+  0xfd,0x67,0xf1,0x4f,0xfc,0x5a,0x67,0xbe,0xff,0xdb,0x12,0xe2,0x34,0xf1,0x2a,0x9c,
+  0x6f,0x26,0x34,0xc6,0x62,0x9a,0xad,0x7f,0xc4,0x3f,0x0a,0xaa,0xb1,0xdc,0xef,0xea,
+  0xd3,0x12,0x4e,0xa2,0x50,0x92,0xdc,0xbd,0x62,0xf5,0x40,0xd1,0x5c,0xc4,0x57,0x79,
+  0xf8,0xa7,0xc7,0x8f,0xb0,0x47,0x3d,0x80,0x68,0x27,0x8b,0x7f,0x1a,0x93,0xc1,0x94,
+  0x7f,0x01,0x1c,0x32,0x1b,0xf7,0x7f,0xea,0xad,0x5b,0x17,0x38,0xf3,0xb5,0xf1,0x8f,
+  0x03,0x7b,0x6c,0x41,0x21,0x41,0x19,0xbb,0xa3,0x01,0x4a,0xd6,0xc9,0x27,0x1c,0xfb,
+  0x93,0xc5,0x3f,0x1e,0x18,0x90,0x15,0x5a,0xee,0x2f,0x93,0x57,0x8a,0x2b,0x4b,0x10,
+  0xff,0x28,0x39,0xf8,0x07,0xcf,0x0b,0xce,0xb6,0x6b,0x0b,0x71,0xff,0x96,0xf0,0x74,
+  0x65,0x3f,0xcc,0x5f,0xa5,0x6e,0xc6,0xf7,0x2b,0x0f,0xff,0x98,0x7e,0x44,0x3b,0xf6,
+  0xf8,0x95,0xb6,0x50,0xd3,0xf6,0x44,0xbc,0x30,0x1e,0x7a,0xac,0x69,0x3c,0xfe,0xf1,
+  0x6b,0x61,0x0b,0x06,0xf8,0xcb,0x2c,0x3c,0xd0,0x7a,0x6d,0x1d,0xa3,0xaf,0x66,0x20,
+  0x34,0x42,0x3c,0x60,0xaf,0x87,0x2c,0xfe,0x71,0xe7,0xfb,0x3c,0xe2,0x0d,0x31,0xcd,
+  0x20,0xaf,0xd6,0x55,0xba,0x12,0x58,0x5b,0xfd,0x8e,0x64,0xaf,0x4f,0x0b,0xff,0x34,
+  0xe6,0xc0,0x1e,0x14,0x58,0xe3,0xcd,0xc1,0x07,0xfc,0x67,0xd0,0x34,0xdd,0x68,0xcc,
+  0x6a,0x93,0x4f,0x39,0xef,0x63,0xa8,0x60,0xbc,0x7e,0x48,0x2d,0x8d,0xb7,0x28,0x27,
+  0x3a,0x69,0xfc,0x6c,0xa3,0xf8,0x05,0xf9,0x88,0xe6,0xc5,0x3f,0xfb,0xc8,0x3e,0x64,
+  0x61,0x0f,0xe1,0x1f,0x1d,0xf6,0x29,0xb5,0x49,0xb5,0x0b,0xe8,0x4a,0x18,0xed,0x43,
+  0xd9,0x73,0x8e,0x7e,0xb2,0xf8,0x27,0x0b,0xf3,0x48,0xa8,0xa0,0x69,0x46,0xa2,0xc6,
+  0xf2,0x18,0xeb,0x47,0x7d,0xae,0x34,0xae,0xd5,0xf2,0xf0,0x0f,0x6a,0xaf,0xd5,0xab,
+  0xff,0x1a,0xd5,0xc2,0x3f,0xe1,0x61,0x7d,0xbf,0x3a,0xdd,0xf0,0x6f,0x61,0x47,0x9c,
+  0xf5,0x80,0xf8,0x87,0x1e,0x3b,0x1e,0xb4,0xc6,0x3b,0xcf,0xdf,0xd0,0x16,0x4d,0x36,
+  0xfd,0x12,0xce,0xb6,0xcd,0x5b,0xbd,0x34,0x29,0x8f,0x38,0xf3,0x25,0xfc,0x63,0x8d,
+  0xb7,0xe7,0xab,0xf9,0xb7,0x2b,0xb6,0x06,0xf8,0x59,0xe5,0x40,0x5c,0x4d,0x2e,0x3a,
+  0xe6,0xac,0xff,0x2c,0xfe,0xc9,0x59,0x6f,0x74,0x65,0x3e,0x22,0xd2,0xa7,0x5e,0x57,
+  0x46,0x8c,0xa9,0x50,0xbc,0x4e,0xbe,0xd7,0x39,0xff,0x0a,0xfc,0xe3,0xc2,0x1e,0x21,
+  0x58,0x57,0xd4,0x0c,0x5e,0x59,0xa7,0xce,0x4c,0x15,0x9f,0x66,0x3e,0x67,0x3d,0x44,
+  0x2c,0xfb,0x63,0x7a,0xdf,0x97,0x8d,0x28,0x44,0x32,0x68,0x9f,0x9f,0x03,0x39,0x1e,
+  0x7d,0xaf,0x5b,0x67,0xcf,0xe4,0xe0,0x9f,0x1c,0xd8,0x80,0xe3,0xf1,0x8a,0x36,0xd3,
+  0x28,0x6a,0xbf,0xea,0x35,0x79,0x9d,0x34,0x8b,0x15,0x1d,0x6f,0x5a,0xa5,0xd8,0xf7,
+  0x27,0xfc,0xf3,0x5b,0x44,0x23,0x41,0x82,0x3d,0x59,0x81,0xde,0xe8,0xf9,0xf1,0xe2,
+  0x35,0xcd,0xaf,0xc2,0x1b,0xb8,0xf5,0x2c,0x59,0xd5,0xfc,0x96,0xfd,0xf8,0x36,0xfe,
+  0xf1,0xc0,0x9e,0x74,0xf3,0x69,0xb4,0x3f,0x62,0x07,0x3c,0x8e,0xd0,0xb7,0x04,0x82,
+  0xba,0x9c,0x70,0xcf,0xbf,0x05,0x36,0xec,0x29,0xbf,0xa4,0x5a,0x82,0xfc,0x75,0xbc,
+  0xf2,0x8d,0x4c,0xf1,0x3f,0xfa,0x51,0x78,0xa0,0x51,0x5f,0x32,0x82,0xab,0xd9,0x8b,
+  0x7f,0xe8,0xb1,0x6f,0x6d,0x87,0xec,0xf3,0xdf,0xc5,0xc4,0x8c,0x8e,0x91,0xd0,0xf5,
+  0x78,0xc5,0x4c,0x35,0x62,0xb0,0xef,0x3b,0xfa,0x07,0xd8,0x92,0x37,0xdf,0x76,0xf6,
+  0x59,0x21,0x3c,0xd3,0xce,0x2a,0xa4,0xc7,0xb5,0xbf,0x83,0xd0,0xed,0x09,0x70,0xec,
+  0xbf,0x5e,0x61,0x59,0x1b,0xd9,0xa3,0xcf,0x00,0xda,0xff,0x9a,0xcc,0xb5,0x10,0x5e,
+  0xa2,0xa7,0x97,0x47,0x43,0xb8,0x35,0x74,0x2b,0xf6,0xfa,0x24,0xfc,0x83,0xa7,0xc5,
+  0xc3,0x7e,0x8f,0xfd,0x5c,0x8d,0xf3,0xa5,0x8d,0x4f,0xae,0xe5,0xe7,0x79,0x83,0xb4,
+  0x64,0x87,0xfc,0xf1,0x1c,0xfc,0x93,0xa7,0x1f,0xfb,0xbc,0xbf,0x07,0x81,0x13,0x9e,
+  0xd7,0x34,0xb1,0x54,0x6c,0x7b,0x22,0x69,0x96,0x19,0x0f,0x38,0xf6,0xdc,0xda,0xef,
+  0xe6,0xb4,0x20,0x2c,0xbc,0x00,0x97,0xa0,0x3c,0x15,0xcd,0x74,0xe6,0xe2,0x1f,0xda,
+  0xb6,0x7c,0x79,0xfb,0xef,0x36,0x43,0xdd,0x17,0x3e,0x65,0xa4,0xb9,0x5e,0x16,0xd8,
+  0x9a,0x87,0x7f,0x68,0x98,0x9a,0x37,0x7e,0xba,0xa9,0x6e,0x27,0xc1,0x9c,0x51,0x04,
+  0x29,0x7c,0x43,0xed,0xf5,0x40,0xf8,0x67,0x37,0xdd,0x3f,0xd7,0x3e,0x2b,0xba,0x19,
+  0xd1,0x0b,0x8f,0x4b,0x07,0x20,0x02,0xaa,0xee,0xc1,0x3f,0x80,0xf8,0x87,0xa6,0x19,
+  0xc8,0x99,0xef,0x13,0x50,0x47,0x88,0x71,0x18,0xe7,0xbb,0x00,0x50,0x00,0xc7,0xfe,
+  0x10,0xfe,0xc9,0x39,0xb6,0xbb,0x82,0x29,0x9f,0x81,0x0b,0xd2,0xf5,0x90,0x68,0x2f,
+  0x7f,0xd3,0x79,0x1f,0xcd,0xb5,0x88,0x9f,0x93,0x73,0x38,0xe2,0x9f,0x0b,0xae,0xff,
+  0x07,0x85,0xe3,0x81,0x56,0x7f,0x19,0x5c,0xe0,0xb3,0xf9,0xfa,0x21,0xb9,0xdd,0xb1,
+  0x0f,0x26,0xe2,0x9f,0x03,0x7a,0x75,0xbb,0xba,0x0f,0xf1,0xb6,0xe5,0xff,0x91,0x09,
+  0x08,0xcd,0x1a,0x54,0x77,0x25,0x66,0xc0,0x01,0x1e,0xde,0xac,0xf6,0x94,0xe9,0x0e,
+  0x9e,0x1f,0x80,0x8d,0xea,0x4e,0x08,0x27,0xaf,0x8e,0x95,0x1d,0xd7,0x1e,0xf4,0xbc,
+  0x68,0xcf,0x46,0x74,0x1c,0x75,0x00,0x74,0x8e,0xe7,0xd9,0x15,0x05,0xf6,0xfa,0x31,
+  0x11,0xcf,0xec,0x24,0xff,0x12,0xa9,0x31,0x8b,0x27,0x77,0x58,0x1a,0x9e,0x4f,0x2f,
+  0x72,0xdb,0x36,0xde,0xb3,0xb3,0xc9,0xfe,0xb5,0xc0,0xf2,0xff,0x98,0x73,0x32,0xc5,
+  0xa4,0x96,0x97,0x6d,0xfc,0x23,0x34,0xf6,0x43,0xb9,0xc6,0x78,0x0f,0xea,0x52,0x33,
+  0x43,0xcd,0x46,0x8b,0x17,0xff,0x5c,0x82,0x27,0x5b,0x26,0xd0,0xcf,0xa8,0x3c,0xa6,
+  0x5f,0x82,0x85,0xfd,0xc1,0x21,0x8f,0xff,0xa7,0x85,0xf0,0x8f,0x5a,0x37,0x30,0x33,
+  0x8d,0x6f,0x5f,0xce,0xc2,0xc3,0x5f,0x64,0x3b,0xbc,0x65,0x34,0x0c,0xe0,0xf9,0x74,
+  0xd0,0x59,0xff,0x43,0xb4,0x1e,0x54,0x7d,0x55,0x6f,0x1a,0x4f,0x07,0x9e,0xf5,0x30,
+  0x0b,0xf1,0x3f,0x3e,0x3f,0x9e,0xc8,0x86,0xd4,0x3d,0x89,0xf7,0x72,0xf0,0xcf,0x4e,
+  0xae,0xb7,0xf5,0xe6,0xed,0xd7,0x38,0x5f,0x9d,0x35,0x2b,0x5b,0x33,0xab,0x93,0xbe,
+  0xc9,0x6c,0xd4,0xb1,0xe7,0x69,0xc2,0x3f,0x5c,0x1f,0x56,0x3d,0xf8,0xc7,0x12,0x5a,
+  0xcf,0x5e,0x73,0xb7,0xbe,0x96,0xcf,0x9c,0xa6,0x2e,0xc7,0xa3,0x99,0x3d,0x1e,0xf1,
+  0x0f,0x1e,0x33,0x63,0x46,0x00,0xf1,0x4f,0x05,0x02,0x21,0xcb,0xff,0xf3,0x3e,0x34,
+  0xf4,0x93,0xff,0x27,0xf0,0x0b,0xb5,0xbe,0xab,0x50,0xc3,0xfd,0xda,0x1e,0x6f,0x4c,
+  0x39,0xd8,0x7a,0x59,0x6b,0xcc,0x20,0xfe,0xb9,0x9c,0xab,0x9f,0xa5,0xa3,0x72,0x0c,
+  0x2e,0xc0,0x47,0x95,0x92,0x9f,0xc8,0x83,0x15,0xb6,0x7e,0x22,0x0a,0xbd,0xbf,0x75,
+  0xad,0xa8,0x8d,0x77,0xb8,0xd7,0x3f,0x76,0x04,0x85,0x47,0xb4,0x3e,0xa8,0x83,0xc9,
+  0xb4,0xbf,0xdb,0xfa,0x19,0xd0,0xc8,0x9e,0x54,0xf5,0x47,0xda,0xf1,0x2c,0xea,0xf5,
+  0xff,0x0c,0xc8,0xa3,0x4c,0x63,0x6b,0xa1,0xca,0x88,0xb4,0xb1,0x13,0x8e,0x3d,0x37,
+  0x04,0xfe,0x89,0x93,0xbf,0xeb,0x39,0xf3,0x7b,0x9e,0xf9,0xbe,0xd9,0xb9,0xa6,0xf0,
+  0x67,0xd0,0xd5,0x17,0x59,0x11,0x5a,0xce,0x06,0x3c,0xfe,0x1f,0xb4,0xde,0x5c,0xff,
+  0x09,0x79,0x7b,0x94,0x9c,0xf3,0x85,0x3f,0x5a,0xb8,0x14,0xb8,0xf1,0xb7,0xf1,0xa2,
+  0x58,0xd9,0x4b,0xce,0xf3,0x10,0xfe,0xf9,0xa0,0x7b,0x77,0x32,0x40,0xb0,0xe7,0x2d,
+  0x17,0xff,0xa0,0x90,0xe9,0x3c,0x1b,0x3f,0x02,0x37,0x25,0x03,0xdb,0xe4,0x73,0xae,
+  0xff,0xca,0xc2,0x3f,0xea,0x38,0xfc,0x03,0xc1,0x84,0xbc,0x15,0xc6,0x94,0x47,0x58,
+  0x09,0x87,0x13,0xce,0xfa,0x41,0xfc,0xa3,0x9e,0x85,0x7d,0xed,0x81,0xbc,0xfd,0xbd,
+  0xde,0xc0,0x2b,0xd3,0xe1,0xec,0xc0,0x82,0x55,0xb7,0x3c,0xe0,0x39,0xbf,0x0b,0xfc,
+  0x23,0x85,0x97,0xa9,0xb9,0xf8,0x87,0xd5,0x12,0x2c,0xf9,0x18,0x1e,0xb5,0xc2,0xf1,
+  0x49,0x3d,0x89,0x91,0x1c,0xfc,0xf3,0x84,0xf1,0xfd,0x3e,0xef,0xf8,0x95,0x59,0x7f,
+  0x05,0xab,0x69,0xd9,0x0f,0xbe,0x26,0x9f,0xd7,0xff,0x13,0x50,0xba,0xf0,0xdb,0x48,
+  0xab,0x8a,0x78,0x80,0xcf,0xf6,0x00,0x83,0x56,0x35,0x59,0xd8,0x82,0x5f,0xe9,0xad,
+  0x1f,0xd7,0xd8,0xb1,0x02,0x5b,0xff,0x63,0x88,0x7f,0x46,0xdb,0x16,0x20,0x7e,0xa7,
+  0x69,0x32,0x31,0xdf,0x38,0xc2,0x8c,0x86,0xca,0xc0,0x5a,0x39,0x82,0x57,0x16,0x54,
+  0x94,0x70,0xf9,0x03,0xd9,0xb6,0x3f,0x1b,0x11,0xff,0x5c,0x84,0xbd,0x37,0xd3,0x6e,
+  0x9e,0xe3,0xdf,0x68,0x09,0x0e,0xfa,0x37,0x6b,0x78,0x34,0x43,0x41,0x3e,0x99,0x83,
+  0x7f,0x2e,0x6a,0x73,0xe2,0xa4,0x1f,0xdd,0x3b,0x7e,0x99,0xb2,0x19,0xed,0xd5,0xcf,
+  0xa1,0xf1,0xd6,0xe2,0x41,0xf9,0x54,0x81,0xad,0x4f,0xc2,0x3f,0xbb,0x52,0x61,0xad,
+  0x9b,0x97,0x39,0xf8,0x47,0x08,0x21,0x95,0x8e,0x5d,0xf7,0xb2,0x5a,0x0d,0xcf,0x47,
+  0x47,0x1c,0x3c,0xd9,0x8a,0xf8,0x07,0xe7,0xdb,0xd6,0xad,0x35,0xe5,0x01,0x21,0x9f,
+  0x86,0x88,0x11,0x8f,0xa2,0x4d,0x7e,0xad,0xf0,0x84,0x64,0xeb,0xbf,0x47,0xe0,0x9f,
+  0xef,0x9b,0x79,0xfa,0xc7,0xf1,0xdf,0x4f,0x86,0x7f,0x09,0x8f,0xd6,0xd4,0xb6,0xf9,
+  0x36,0x15,0x9e,0x72,0xf1,0x4f,0xc5,0x76,0x78,0xb7,0x6d,0x81,0x11,0x4d,0x96,0x0f,
+  0x6b,0x39,0x40,0xae,0x64,0x73,0xe7,0x1b,0x80,0xe7,0xf1,0x36,0xbc,0x32,0xe2,0xec,
+  0xbf,0xab,0x00,0xd1,0x0e,0x9f,0x3b,0x1e,0x0f,0x1b,0x9f,0xda,0x82,0xc2,0x8b,0xd0,
+  0xb0,0xa8,0xb8,0x47,0x3e,0x91,0x8b,0x7f,0xe2,0xbb,0xd4,0x68,0xee,0x7a,0x2b,0x40,
+  0xd8,0xd9,0x55,0x8d,0xc2,0xed,0x0d,0x5a,0x34,0x21,0x1f,0xb6,0x7f,0x2e,0x7c,0x1f,
+  0x23,0x08,0xda,0xab,0x93,0xdd,0x1e,0xfc,0x23,0x84,0x0e,0x2d,0xc5,0x5e,0x36,0x0e,
+  0x0d,0xce,0xec,0x86,0x93,0xec,0x98,0x8b,0x7f,0x14,0xc4,0x3f,0x49,0x3d,0x2e,0xde,
+  0x97,0x1c,0x20,0xd4,0x8d,0x16,0x1b,0xe6,0x40,0x74,0xa8,0xbb,0x3e,0xfc,0x8c,0xb3,
+  0xde,0x74,0xf8,0x2c,0xec,0x01,0xbd,0xa9,0xdb,0x83,0x07,0x84,0x70,0x5c,0xbd,0x8b,
+  0xbd,0xa2,0xef,0x91,0xa2,0xa6,0xda,0x56,0x97,0x71,0xf6,0xf7,0x48,0xf7,0xe7,0x10,
+  0xf6,0xcc,0xce,0x44,0xd7,0x7c,0xfe,0x55,0x2f,0x10,0xaa,0x1f,0x56,0xbf,0xda,0x29,
+  0xae,0xdc,0x19,0x68,0x95,0x4f,0x86,0x1d,0xbc,0x8a,0xf8,0x67,0x6c,0x82,0xfd,0xbd,
+  0x61,0x60,0x16,0x09,0xf8,0x15,0xfe,0x22,0x38,0x5f,0x5b,0x3f,0x46,0xc1,0x25,0xe3,
+  0x32,0x9f,0x1d,0x0f,0x9c,0x6d,0xb6,0x81,0x50,0xf6,0x20,0x1f,0x18,0x2b,0x9f,0x0a,
+  0xcf,0xf1,0x39,0x7a,0x60,0x44,0x1e,0xd4,0xed,0xdf,0xf7,0xfb,0xd2,0x16,0x38,0x18,
+  0xda,0xaa,0x14,0xdf,0xd5,0x94,0xfb,0xfc,0x66,0x09,0x09,0x5d,0x50,0x6d,0x14,0x1b,
+  0xec,0x24,0xb3,0xc7,0x23,0xfe,0xd1,0xd0,0x5e,0x99,0x45,0xe3,0xc6,0xab,0xed,0x89,
+  0x36,0x58,0x07,0x33,0x5b,0x7c,0x71,0x7c,0xbf,0xec,0xf1,0xe4,0xff,0xd9,0x67,0xa4,
+  0x56,0x7d,0x72,0x9c,0x3d,0xf7,0x2f,0x40,0x81,0xbf,0x50,0xfb,0x95,0x5b,0x81,0xbd,
+  0xe8,0x8c,0xef,0xa5,0xfd,0x8b,0xd7,0xdd,0xbd,0x36,0x5d,0x7e,0x5a,0xf1,0xcc,0x17,
+  0x11,0xcb,0x19,0x39,0xaa,0x3f,0xd3,0xd7,0x30,0x5a,0x3b,0x5f,0x7e,0xc7,0x79,0x5f,
+  0xb8,0x84,0xfa,0x51,0xeb,0xdb,0x96,0xe6,0xeb,0xc7,0x2c,0x21,0xe1,0x9c,0x5a,0xd7,
+  0x2c,0x1d,0xc4,0x15,0x62,0xeb,0x47,0xd2,0xf0,0xbc,0x9f,0x9a,0x63,0xd4,0xa2,0x19,
+  0x17,0xd1,0x0d,0xc7,0x9e,0x17,0x8f,0xca,0x97,0x74,0x14,0x0c,0xe5,0xb0,0x1c,0x71,
+  0xec,0x0f,0xe1,0x9f,0x83,0x99,0x70,0x7b,0x16,0xff,0x34,0xd0,0xfe,0x65,0x23,0xa2,
+  0xb2,0x5f,0xe8,0xfb,0x78,0x6d,0xdc,0xd7,0x13,0x8e,0x18,0x2e,0xfe,0x21,0x7f,0x51,
+  0x38,0x2e,0xc6,0xdf,0xe4,0x8d,0x77,0x14,0xa5,0xcb,0x4e,0x27,0x0f,0xf0,0x5a,0xfd,
+  0x96,0x3d,0xe1,0x5c,0xfc,0xb3,0x0b,0x52,0xc6,0x7c,0x54,0x8b,0x96,0xd5,0x8f,0x85,
+  0xc0,0x05,0x22,0xda,0x45,0x2f,0x66,0x8c,0x31,0x17,0xff,0x40,0x14,0x0f,0x59,0x75,
+  0x46,0xad,0x35,0xcd,0x05,0xf6,0x7c,0x17,0xd2,0xf3,0x67,0xc8,0x50,0x1b,0x25,0x29,
+  0x59,0x9f,0x64,0xdb,0x9f,0x6d,0x57,0x8b,0xd9,0x19,0xc1,0xd1,0x6a,0x12,0xc4,0x7c,
+  0xbf,0x66,0x6f,0x64,0xa3,0xf0,0x01,0xa3,0xaf,0xe4,0x91,0x42,0x07,0xcf,0x54,0x8a,
+  0xd5,0x62,0x16,0x8f,0x55,0x3b,0xeb,0x67,0xd4,0x78,0x15,0x66,0xa7,0x82,0xef,0xc9,
+  0xff,0x99,0x7a,0x96,0x5f,0x1f,0x0f,0x0c,0x94,0xb7,0x97,0x39,0xfa,0x0f,0x09,0xb7,
+  0xcf,0x19,0xd5,0xf5,0xff,0x34,0x65,0x10,0x08,0x85,0x33,0xea,0x16,0x58,0x08,0xeb,
+  0xd7,0x86,0xe3,0x03,0x3d,0x65,0x31,0x67,0xfd,0x64,0xfd,0x3f,0xe6,0xd5,0x9e,0xf5,
+  0x70,0x18,0xbe,0x03,0xdb,0x4c,0xff,0xec,0xf0,0x46,0xfe,0x28,0xd4,0x18,0x3e,0x58,
+  0x7c,0xb7,0x33,0x5f,0xb3,0x60,0x47,0x20,0x1f,0x4f,0x9e,0x44,0x20,0x14,0x36,0xbb,
+  0x93,0xcb,0x02,0xf0,0xa8,0x16,0x5e,0xee,0xeb,0x61,0x31,0x67,0xfd,0x80,0xf0,0x3f,
+  0xcc,0x34,0x8b,0x3d,0xeb,0xe1,0x1d,0x18,0x6a,0x8d,0xb5,0x06,0xb7,0x21,0x1e,0xee,
+  0x83,0x8a,0xf6,0xda,0xcd,0x92,0x61,0xd8,0xe3,0xb3,0xfe,0x9f,0x3e,0x0f,0xec,0x29,
+  0x1f,0x83,0x8b,0x46,0xe3,0x48,0x30,0x8e,0x77,0x40,0x7b,0x1b,0xff,0xe6,0x20,0x6a,
+  0xc0,0x1e,0x6f,0x80,0x38,0x8f,0x0c,0x08,0xb5,0x3b,0xfb,0xfb,0x80,0xd1,0x30,0x58,
+  0xbc,0xbd,0x39,0x4a,0xf6,0xea,0xcf,0x4a,0xf6,0x74,0xfe,0xdc,0x79,0x1e,0xcb,0xff,
+  0x33,0xeb,0x27,0x5e,0xff,0xd5,0x08,0x74,0xd0,0x8c,0x1e,0x66,0xf5,0xe4,0x51,0x6f,
+  0x53,0xeb,0x13,0xe7,0x9c,0x5f,0xd7,0x54,0xc4,0xaf,0x3f,0x28,0x5e,0x13,0x2b,0xfe,
+  0x55,0x78,0x1a,0x12,0x14,0xaf,0xa9,0x29,0x0b,0x50,0xc4,0xb0,0xcd,0xaf,0x14,0xba,
+  0xf8,0x27,0xae,0x7d,0x2e,0x17,0xf6,0xf8,0xd7,0x4c,0x7f,0x15,0xee,0xe1,0xb3,0x86,
+  0x23,0xad,0x6c,0x2a,0xac,0xe5,0x5f,0xcc,0x14,0xb5,0xb2,0x33,0xce,0xfd,0x5b,0xd5,
+  0x25,0xc6,0xfb,0x5a,0x36,0xec,0x95,0x8d,0x7f,0x8d,0xe0,0x2f,0x50,0xdf,0x5f,0x5c,
+  0x35,0x29,0x60,0xfc,0x04,0xea,0x9b,0x82,0x65,0x68,0x6f,0xed,0x8f,0x51,0x79,0x50,
+  0xbb,0xac,0xe4,0xc1,0x42,0x03,0x11,0x51,0x7f,0xd0,0x28,0xbf,0x80,0xfb,0xd7,0x37,
+  0xcc,0xfb,0x46,0x3d,0x78,0x4f,0x2d,0x18,0x7f,0x1e,0xf9,0xba,0xfa,0x16,0xa4,0xcd,
+  0x40,0x6a,0xd2,0x69,0x78,0x9f,0xd7,0xe1,0xd6,0xf6,0x31,0x17,0xff,0xb4,0x5e,0x4d,
+  0xf8,0xe7,0xc6,0x9c,0xf3,0xd4,0x2b,0x68,0x46,0xaa,0x4c,0x35,0xce,0x5e,0xe9,0xdb,
+  0x0b,0x5b,0xcd,0x5b,0xda,0x96,0xbd,0xe7,0xac,0x1f,0x1d,0xa6,0xe6,0xcf,0x97,0xdd,
+  0x06,0xdb,0x78,0xf5,0x68,0x64,0x15,0x7b,0xd5,0x78,0x8c,0x5f,0x17,0xbf,0x66,0x4d,
+  0x99,0xeb,0x7f,0x5e,0xa5,0xd0,0x6b,0x15,0xf1,0x9e,0x67,0xcb,0x06,0x8c,0xce,0x6e,
+  0x7d,0x54,0x9d,0x89,0x57,0x76,0x76,0x44,0xb9,0x6f,0x76,0xd3,0x09,0x4f,0xfc,0x2b,
+  0x8b,0x76,0x1c,0xd8,0x93,0x92,0xbf,0x0a,0xef,0x64,0xe6,0xa4,0xa3,0x99,0x66,0xbc,
+  0x92,0xba,0xa9,0xab,0xe4,0x57,0xf2,0xfb,0xee,0xf3,0x4b,0x56,0x3c,0xc2,0x83,0x7f,
+  0x70,0x7d,0x8e,0xc1,0x21,0x75,0x16,0xef,0xcc,0x28,0x63,0x4a,0x18,0x7e,0xc4,0x51,
+  0x9f,0x8e,0x7e,0x34,0x3a,0xef,0xd7,0xb7,0xd7,0x78,0xf7,0xbb,0xd0,0xbb,0x52,0x9d,
+  0x31,0x79,0x33,0x58,0xae,0x83,0xa5,0xdf,0x69,0x7e,0x2a,0x17,0xff,0x58,0xe8,0x85,
+  0xbe,0x75,0xf6,0xdf,0x94,0xf1,0x29,0x21,0x0c,0xd5,0xae,0xf4,0x6f,0xc1,0x15,0x65,
+  0x7f,0xe6,0x4b,0xe4,0xff,0xf9,0x12,0x81,0x9c,0x9c,0xfd,0x3a,0x6c,0xcc,0xb0,0x84,
+  0x2f,0x35,0xe1,0x0a,0x7c,0xce,0x19,0x1f,0xa9,0x50,0x60,0xa7,0x12,0x6d,0xf5,0x11,
+  0x0c,0xd8,0x9a,0xc5,0x03,0xc9,0x9d,0x7a,0xd8,0xf0,0x5d,0x53,0xd6,0xcf,0x77,0xb2,
+  0xd5,0x86,0x3f,0x54,0x76,0xd8,0xc1,0x9f,0xb6,0xff,0xa7,0x84,0xe6,0xbb,0xcf,0xda,
+  0x7f,0x5f,0x37,0xc6,0xd0,0x50,0xdd,0x8b,0xc2,0x92,0x31,0x2b,0xde,0x77,0xc9,0x59,
+  0x9f,0x3d,0x96,0x3f,0xa7,0xa5,0xd8,0x33,0xdf,0x33,0x2d,0x17,0xb5,0x46,0xa3,0xf8,
+  0x27,0x6c,0xd8,0xb8,0x08,0x0b,0x0d,0xc2,0x3f,0xce,0x79,0xaa,0xa7,0x80,0xf4,0xd3,
+  0x18,0xcf,0xc1,0x03,0xfa,0x59,0xb5,0xce,0x28,0x19,0xec,0x5c,0x89,0x50,0x6a,0xa7,
+  0x31,0x79,0xf0,0xf3,0x61,0xc7,0x5f,0x3d,0x3f,0x94,0xd1,0xc6,0xa0,0x56,0xf3,0xf8,
+  0x7f,0x96,0xbd,0x4e,0x6e,0x1f,0x09,0x61,0x4f,0x95,0xb1,0x4f,0x0a,0x83,0x9a,0x2a,
+  0x2b,0x71,0x7e,0xdf,0x56,0xc4,0x7b,0x3b,0xe9,0x25,0x72,0xfc,0x3f,0x28,0xa4,0xf0,
+  0x44,0x46,0x66,0xb6,0x45,0xdf,0x09,0xba,0x71,0x5d,0xd2,0x57,0x26,0xd9,0xfa,0x0f,
+  0x29,0x56,0xfc,0xcb,0xe3,0xff,0x09,0xbf,0x21,0xf4,0x49,0x78,0x12,0xf1,0x27,0x6b,
+  0xfa,0xb3,0x07,0xd8,0x74,0xe7,0xf7,0x22,0xff,0x0f,0x0d,0xf3,0x3e,0xff,0x1b,0xca,
+  0x59,0x3d,0xfd,0xf7,0x25,0x04,0x74,0xdf,0x85,0xba,0xb6,0xa2,0x64,0x73,0xc4,0xd9,
+  0x7f,0x5b,0x85,0xff,0x27,0x77,0xfc,0xb0,0xfa,0xae,0x70,0x04,0xd9,0xc0,0x29,0xd9,
+  0xe9,0x5d,0x3f,0x62,0xbd,0xb1,0x7c,0xbc,0x5d,0x67,0xc5,0xbf,0x86,0xa0,0x21,0xa6,
+  0x76,0xc9,0xc7,0x9c,0xf1,0x11,0x89,0xbc,0x3d,0xb3,0x78,0x49,0x1e,0xfe,0x09,0x73,
+  0x5f,0xa6,0x69,0x04,0xee,0x53,0x67,0xa6,0x8a,0x56,0x32,0x0f,0x5e,0xb2,0xfc,0x3f,
+  0xc9,0x7c,0x7f,0xa9,0x6e,0x16,0xc5,0xb6,0x1d,0x57,0x1e,0x84,0x95,0x99,0xa2,0x7a,
+  0xf6,0x94,0x33,0x9e,0x97,0x5a,0xfe,0x9f,0x6b,0x72,0xde,0xdf,0x27,0xa1,0xda,0x9c,
+  0xd1,0xc6,0x5e,0x4d,0x7e,0x1b,0x66,0x3e,0x55,0xd4,0xbe,0xce,0x34,0xec,0xf1,0xdd,
+  0x96,0xff,0x47,0xf7,0xfa,0x7f,0x5e,0xe5,0xbf,0xe5,0x3b,0x33,0x5f,0x5c,0x53,0x7e,
+  0x59,0xfd,0x6f,0xbe,0x30,0x1e,0x6d,0x95,0x9f,0xb2,0x1f,0x1f,0xed,0x89,0x15,0xff,
+  0x2a,0xf1,0xda,0x73,0x83,0x22,0xf8,0xa8,0xa8,0xd3,0xfa,0xdb,0xac,0xa1,0xaf,0x24,
+  0x07,0xff,0x28,0x87,0x10,0xff,0x34,0xa6,0xe4,0xb3,0x72,0x0e,0xfe,0xd9,0x8d,0xf8,
+  0x47,0xfe,0x3a,0xfc,0xe7,0x03,0x0b,0xe3,0x1b,0x07,0xca,0x07,0x5d,0x7f,0x75,0x68,
+  0x0b,0xfc,0x52,0xf3,0xfa,0x73,0xee,0x22,0x41,0xa9,0x32,0x8b,0xdb,0xd8,0xe4,0xd6,
+  0xc7,0xb4,0x99,0x6d,0xea,0x5d,0x4d,0x6f,0x39,0xf6,0x5f,0x33,0x08,0xff,0x78,0xfd,
+  0xd5,0x96,0x50,0x8d,0x30,0x8f,0x1c,0x41,0x65,0xb3,0x8c,0x22,0x83,0x0d,0x73,0x7b,
+  0x7c,0x5c,0xd9,0x48,0x66,0x1c,0x72,0xf4,0xc9,0x77,0xeb,0xfa,0x68,0x51,0x88,0x05,
+  0x60,0xb7,0x14,0x6d,0x2a,0x2a,0x4d,0x0c,0x76,0xd9,0xe3,0x2d,0xff,0x4f,0x94,0x7b,
+  0xfd,0x3f,0x17,0xe1,0xbc,0x51,0xf7,0x41,0x20,0xf6,0xe0,0xd7,0x94,0x73,0x1d,0x0d,
+  0xc6,0x7f,0x74,0xc9,0x27,0x9d,0xf1,0xdc,0xda,0x8f,0x06,0x27,0x8d,0xc3,0x3f,0x41,
+  0xf2,0x8f,0x9d,0x6b,0x6b,0xb8,0xe3,0xbe,0x2e,0x5c,0x48,0xce,0xfa,0xb4,0xfc,0x3f,
+  0xbc,0x38,0xe7,0xbc,0xff,0x3e,0xcc,0x31,0x03,0xfc,0xa6,0xaf,0xb1,0xe7,0x11,0x2a,
+  0x04,0xcc,0xe6,0x91,0x16,0x7b,0xfc,0x56,0x45,0xf8,0x73,0xd2,0x79,0xfe,0x1f,0xa6,
+  0x9b,0xbe,0x8d,0x89,0x28,0x6c,0x50,0xa3,0xf1,0xde,0x7b,0xd9,0x59,0xe7,0xf7,0xe5,
+  0x05,0x51,0x0d,0x87,0x6d,0x9e,0xc0,0xff,0xb3,0xaf,0x29,0x0a,0xdd,0x50,0x12,0x2f,
+  0xea,0x0e,0x67,0x9c,0xf5,0xa3,0xde,0x21,0xa2,0x1b,0x3c,0xcf,0xff,0x03,0xd3,0xfb,
+  0x7c,0x1c,0xf5,0xc3,0xa1,0x56,0xba,0x1a,0x3c,0xfe,0x67,0x6e,0xf9,0x7f,0x78,0x20,
+  0x6f,0xbe,0x8f,0x9b,0x4b,0x92,0x72,0x3d,0x31,0x2e,0xf0,0x45,0x28,0x77,0xef,0x9f,
+  0xaa,0xb4,0xa3,0x5d,0xb9,0xfe,0x8d,0x1b,0xcd,0x59,0xa6,0x75,0x05,0x4a,0xcc,0xe6,
+  0xcc,0x3a,0x07,0xff,0x14,0x08,0x6f,0x4f,0xa6,0xd8,0x72,0x1b,0xba,0xf8,0xf9,0x18,
+  0xfe,0xe1,0xd7,0xe1,0x79,0xfd,0xfa,0x4c,0x71,0x2b,0x02,0x27,0x27,0x3e,0xa5,0xbd,
+  0x03,0xcf,0xf0,0x68,0x9f,0xba,0x2f,0x5c,0xeb,0x89,0x7f,0xf1,0x59,0x83,0x25,0x67,
+  0x59,0x2d,0xdc,0x6f,0x86,0x53,0x6a,0xb7,0x1c,0x73,0xec,0xd5,0x00,0xe2,0x9f,0x07,
+  0x45,0x74,0x2f,0x67,0xbe,0x2c,0x40,0xc2,0x6a,0x78,0x58,0xdb,0x61,0x16,0x69,0xec,
+  0x6e,0x8f,0xff,0x67,0x07,0xa2,0x9d,0xa8,0x29,0xa2,0x87,0xde,0xf8,0x97,0x79,0x6d,
+  0x3a,0xbc,0x3a,0xfe,0x03,0x98,0x91,0x28,0xea,0x49,0xb8,0x7c,0x24,0x28,0x3d,0x2e,
+  0xdc,0x3e,0xc5,0xb1,0xf2,0xfc,0xf5,0x10,0x2b,0xbf,0x4d,0xec,0xf8,0xc5,0x01,0xd9,
+  0x30,0xbc,0xfe,0x9f,0x5f,0x5b,0xde,0x8c,0x0b,0xf8,0xda,0xe6,0xf0,0x7f,0xaa,0x0f,
+  0xc1,0x6b,0xec,0x06,0x5e,0x62,0xca,0x63,0x6e,0x7c,0x4d,0xdb,0x01,0x4f,0x48,0xf8,
+  0xd2,0xed,0x1c,0xb7,0xde,0x76,0x4d,0xfa,0x25,0xbc,0xcc,0xe7,0x2d,0x0f,0x6e,0x96,
+  0x2b,0x3d,0xf1,0xaf,0x99,0xb4,0x1e,0x06,0xd4,0x83,0xf2,0x8e,0x1c,0xff,0x4f,0x9f,
+  0xff,0x02,0x7b,0xc3,0xb8,0x1f,0xb6,0xa5,0x42,0x49,0xe6,0x8d,0x7f,0x7d,0xca,0x44,
+  0xb5,0x0c,0xf8,0xea,0xcd,0xdc,0x78,0x8d,0x25,0x3c,0x08,0xfa,0xa0,0xcf,0x07,0x31,
+  0xc7,0xbf,0x97,0x91,0xa6,0xf2,0x6f,0x93,0xb7,0x67,0x0d,0xfb,0x6e,0x0e,0x30,0x78,
+  0x03,0x85,0x4b,0xf0,0xe0,0xa6,0xaa,0xad,0xea,0x40,0x49,0xd4,0x59,0x0f,0xe4,0xff,
+  0x41,0xeb,0xd1,0x57,0x62,0xb9,0x7d,0xb2,0x40,0x48,0x20,0xa2,0xd9,0x89,0xe3,0xf0,
+  0x53,0x88,0xdd,0xeb,0xd3,0x3a,0x5d,0x52,0x9a,0x31,0xe5,0xe0,0x20,0xaa,0xa5,0x1f,
+  0xd5,0x72,0x30,0xc7,0xff,0xf3,0x54,0xf0,0x8c,0x3c,0xa4,0xfe,0x08,0x6e,0xe2,0xf7,
+  0xf5,0x79,0xf0,0x4f,0x6f,0xc1,0x3b,0x82,0xf6,0x93,0xbf,0x3e,0x1b,0x4e,0x6e,0xd9,
+  0x49,0x11,0x49,0x35,0xf6,0x2e,0x1a,0x6a,0x8f,0xff,0xa7,0x74,0x8b,0xa0,0x0d,0xa8,
+  0x79,0xf6,0x04,0x7f,0xf1,0xbb,0x51,0xd8,0x0d,0x55,0x09,0xd5,0x60,0xef,0x39,0xef,
+  0x6f,0x07,0x7c,0x57,0xd0,0x7e,0x22,0xf9,0xfe,0xae,0x11,0xf5,0xab,0x61,0xd4,0xc0,
+  0xae,0x1f,0xc4,0xaf,0xce,0xf5,0xff,0x1c,0x87,0x4e,0x66,0xb1,0x7d,0x72,0xf5,0xa9,
+  0x92,0x3f,0x7f,0xb7,0x12,0x49,0x21,0xfe,0xcc,0xf1,0xff,0xe0,0x69,0x98,0x48,0x3e,
+  0xf2,0x88,0x92,0x03,0x84,0x02,0x29,0x79,0x3f,0x1c,0x60,0x33,0x0e,0x16,0x0f,0x77,
+  0x9e,0x77,0xf1,0x8f,0xe5,0xff,0xd1,0x82,0x5d,0x62,0x1b,0x9a,0xea,0xe1,0xff,0x28,
+  0xf2,0xeb,0xf1,0x35,0xc6,0x74,0xed,0xbe,0x5c,0xfc,0x23,0x36,0xb5,0x95,0x1b,0xbf,
+  0x93,0x7f,0xde,0x0f,0x7e,0x47,0x5e,0x69,0x9c,0xe5,0xf3,0x06,0x96,0x6e,0x92,0xbd,
+  0xf8,0xe7,0xaf,0x68,0x3f,0x6d,0x57,0x93,0x89,0xdc,0xf8,0xd7,0x22,0xff,0x66,0xf6,
+  0x31,0xbe,0x73,0x53,0xb8,0xad,0x24,0xc9,0xdc,0xf7,0x3d,0x54,0x30,0x0d,0xf6,0xa3,
+  0x51,0xcd,0xf7,0x57,0xd8,0x8e,0x20,0x75,0x7a,0xd3,0xb5,0x49,0x9c,0xb8,0xbd,0xde,
+  0x5c,0xfe,0x0f,0xcb,0xf5,0x87,0xb4,0xfa,0xcb,0x16,0xe3,0x57,0xba,0x6e,0xf8,0x42,
+  0x1e,0xff,0x8f,0x85,0x7f,0xea,0x2b,0x27,0xe7,0xec,0xbf,0xe4,0xff,0xb9,0x3f,0x55,
+  0x4e,0x5f,0xcd,0x13,0xf8,0xc7,0x39,0x7f,0xf5,0x4c,0xe9,0x87,0xb3,0xd2,0x44,0xf1,
+  0xbe,0x2c,0xff,0x07,0xf7,0xf7,0x41,0xf9,0x2d,0xc7,0x1f,0xd2,0x5d,0x70,0x46,0x22,
+  0xda,0x0c,0xf1,0x7f,0xbc,0xe3,0x17,0xb4,0x06,0x4e,0xc8,0x7b,0xe0,0x62,0xe0,0x06,
+  0xfa,0xea,0x39,0xc9,0x7e,0x1f,0xc9,0xff,0x33,0xc4,0xa2,0x3e,0x95,0xf0,0xcf,0x98,
+  0xeb,0xff,0x29,0xa1,0x2b,0x3a,0xec,0x6b,0x9a,0xce,0xd1,0x90,0x2e,0x2e,0xf4,0xf8,
+  0x7f,0x54,0xa2,0xfd,0xa8,0x79,0xf3,0x8d,0xb4,0xa9,0x15,0x61,0x82,0x46,0x3a,0xe2,
+  0xbd,0xc5,0x27,0x24,0xc7,0x9f,0x56,0xb9,0x5d,0x79,0x88,0xc6,0x93,0x1a,0x1f,0xf5,
+  0xfa,0x7f,0x22,0x88,0x7f,0xb4,0xfd,0x30,0xbd,0x05,0xf5,0xf9,0x05,0xe7,0x79,0xb6,
+  0x55,0x12,0x4d,0xa8,0xc1,0x10,0xfe,0xbd,0xfd,0x9e,0xe7,0xc7,0x3b,0xc8,0x8f,0xc0,
+  0x59,0x16,0x5b,0x24,0x6f,0xf6,0xe0,0xd5,0x55,0x56,0xfc,0xeb,0xf0,0xac,0x71,0xfe,
+  0x1f,0x14,0x1e,0xe1,0x67,0xe1,0xc0,0xa2,0x92,0x4d,0x9d,0x27,0x5c,0x3e,0x4f,0x36,
+  0xfe,0x15,0x48,0xe4,0xfb,0x1b,0xf1,0x17,0xd1,0xcd,0xb1,0xb2,0x3a,0xba,0xe2,0xbe,
+  0x5f,0x91,0x82,0x90,0x21,0xa2,0x5d,0xa7,0x09,0xf6,0x28,0x9e,0x40,0x58,0x28,0x5e,
+  0x78,0x13,0xcc,0x4b,0x56,0x27,0xfd,0x99,0x1c,0xfc,0x63,0x08,0xb6,0x8f,0x3a,0x3f,
+  0xef,0x7d,0xe9,0xeb,0x8e,0x6c,0x2b,0x81,0x07,0x0d,0x3d,0x21,0xf0,0x8f,0xad,0x9f,
+  0xad,0xa8,0x29,0x7c,0x6d,0x93,0xea,0x57,0xf2,0xfc,0x3f,0x03,0xbe,0x0a,0x36,0x19,
+  0xff,0xf0,0x4e,0xe6,0x6f,0xa9,0x33,0xdd,0xf8,0x8e,0x5a,0x46,0xb0,0x67,0x38,0xba,
+  0x4a,0xce,0xf1,0xff,0x34,0x8e,0xa8,0x6b,0x7c,0x57,0xc1,0x0b,0x7c,0x76,0xaa,0x78,
+  0x95,0x7c,0xd8,0xe3,0xff,0x49,0x91,0xf5,0xb8,0x7a,0x9c,0xff,0xe7,0xb9,0x5f,0xa5,
+  0xf0,0x87,0xf8,0x2a,0x1c,0xe2,0x62,0xbe,0xb6,0xfe,0xcd,0x82,0xf7,0x08,0xff,0xe8,
+  0x81,0xe5,0x72,0x43,0x9e,0xff,0x67,0x08,0xff,0xa1,0xe7,0xf0,0xab,0xe7,0x5f,0xac,
+  0x1e,0xd2,0xed,0xf1,0xbd,0xa5,0xdf,0xa2,0xa7,0xed,0x2f,0xce,0x86,0xbd,0x3c,0xfe,
+  0x9c,0x65,0xec,0xbf,0x60,0x9d,0xf4,0x45,0xcd,0x7f,0x07,0x7b,0xcb,0x39,0x7f,0x69,
+  0xb0,0x59,0xe0,0x1f,0xb4,0x57,0x79,0xe3,0x8b,0x88,0x11,0xb4,0x4e,0x9b,0xa9,0xf9,
+  0xe2,0xd3,0xbd,0xfc,0x9f,0xfe,0x2c,0x9b,0x85,0xd0,0x8e,0xbb,0xdf,0xa1,0xfd,0xd1,
+  0xca,0xfa,0xe9,0x60,0x5b,0x73,0x6d,0x21,0x1b,0x74,0xf4,0x3f,0x22,0xf8,0x1e,0xc2,
+  0x7e,0x46,0x21,0xc7,0xff,0x33,0x93,0x84,0x7b,0x21,0x9a,0x2e,0xb9,0x17,0xdf,0x17,
+  0xfb,0xfd,0x4a,0xe2,0xa1,0x49,0xf0,0xa3,0xf6,0x8c,0xdb,0x8f,0x36,0xcb,0xa7,0xf9,
+  0x39,0xa3,0xa1,0x14,0xf5,0x33,0xe2,0xe8,0x67,0x50,0xbb,0x64,0xb1,0x7d,0x2e,0xe4,
+  0xe2,0x01,0x1c,0x3f,0x26,0x9f,0x81,0x4b,0xc9,0x46,0xbe,0xc4,0x2c,0x1f,0x70,0xf0,
+  0x4f,0x87,0xf2,0xd7,0x06,0x6e,0x5b,0x47,0xd4,0x83,0x79,0xfc,0x13,0xd3,0xbf,0x87,
+  0xfd,0x02,0x0e,0x98,0xb5,0x19,0xb5,0x8b,0x8d,0x78,0xfc,0x3f,0x82,0xdd,0x01,0x6a,
+  0x3a,0x91,0x3f,0xfe,0xdf,0xf1,0x60,0x78,0x40,0xad,0x45,0x3c,0x80,0xf8,0xc7,0xe5,
+  0xff,0x80,0xc3,0xc6,0xcc,0xdb,0xef,0xe8,0xc5,0xdc,0x05,0xab,0x41,0x85,0xb2,0xc3,
+  0x8e,0xfd,0xe1,0xc5,0xab,0x94,0xf3,0xac,0x7e,0xdc,0xfe,0xd2,0x88,0xff,0x50,0x75,
+  0xc6,0x32,0xd4,0x5c,0x36,0x75,0xc7,0xff,0x33,0x65,0x54,0x9a,0x20,0xfe,0xc5,0x50,
+  0xc8,0x20,0x8c,0xb9,0x84,0x07,0x09,0xbf,0x29,0x8f,0x14,0xb8,0xf8,0x47,0x84,0xbd,
+  0xda,0x83,0x4f,0x21,0x9a,0x7a,0x9e,0xcf,0xc9,0x90,0xbf,0x88,0x3f,0xcf,0x1b,0x87,
+  0x03,0xef,0x75,0xbe,0xa7,0xe1,0x57,0x55,0xc5,0x03,0xd5,0xa3,0x8e,0xbd,0x22,0xfc,
+  0xb3,0x81,0xd7,0x9a,0x6a,0x27,0xa2,0x9d,0x0d,0x7a,0x38,0x83,0xf3,0x5d,0x68,0xfc,
+  0x00,0xaf,0xf8,0x2e,0xb0,0x53,0xf4,0x95,0x1e,0xe8,0x66,0xa3,0x8a,0x8b,0x7f,0xfa,
+  0x71,0x13,0xaf,0x1d,0x90,0x58,0x59,0x40,0x7a,0x58,0xd5,0x89,0xbd,0xbc,0x04,0x3a,
+  0xd1,0x9e,0xb4,0xc6,0x0a,0x33,0xe4,0x18,0x84,0x87,0x34,0xf6,0x9e,0xb3,0xbf,0x9b,
+  0x95,0xdb,0x8d,0x0d,0xf0,0x25,0x33,0x94,0x42,0xfc,0xf3,0x03,0x08,0x9b,0x88,0xaf,
+  0x48,0xa8,0x35,0x10,0x91,0xe2,0xfd,0x59,0x6d,0xc5,0xf2,0x54,0x59,0xc6,0x8d,0xff,
+  0x96,0x9e,0xd6,0x5f,0x86,0xe8,0x9f,0x16,0x8f,0x34,0x47,0x11,0xed,0xd4,0x99,0xc1,
+  0x6e,0x79,0x35,0xed,0xc8,0xc3,0xa8,0xb1,0xc3,0x08,0x8d,0xea,0xf5,0x29,0xdf,0x97,
+  0x86,0x1d,0xfb,0x90,0x91,0x7e,0x88,0x6a,0xf9,0xa8,0x51,0x7c,0xa7,0x7c,0x9c,0xbd,
+  0x96,0xab,0xa8,0xce,0x51,0x85,0xf0,0xe1,0xd2,0x77,0xe5,0x21,0xc3,0xbe,0xbd,0xa1,
+  0xfd,0x47,0x13,0xde,0xad,0x0d,0x17,0x55,0xd6,0xff,0xd3,0x2b,0x6f,0x24,0xc4,0x65,
+  0x08,0x9a,0xd9,0x98,0xbe,0xe0,0xa1,0xe0,0xc1,0xf2,0x17,0x3c,0xf8,0x27,0x00,0x1b,
+  0xa4,0xda,0x25,0xf2,0xa3,0x88,0x1f,0x36,0x94,0xe2,0x32,0x98,0xcf,0xea,0x29,0x90,
+  0x67,0xf8,0x47,0xf1,0xf9,0x9e,0x30,0x58,0xa8,0x68,0x27,0x7b,0xcf,0xe1,0x07,0x66,
+  0x0a,0x96,0x56,0xa1,0x36,0x06,0x65,0x89,0xbc,0xcd,0x06,0x2e,0x83,0x79,0x8c,0xdc,
+  0x3e,0xf8,0x87,0xf5,0xec,0x30,0x42,0x23,0xbd,0xcd,0x3f,0x97,0x8d,0x39,0xeb,0x67,
+  0x54,0x9a,0x4a,0x78,0x20,0x75,0x2b,0xe1,0x1f,0x02,0x42,0x78,0xff,0x12,0x8b,0x18,
+  0xfc,0x8f,0x02,0x18,0x6c,0x9d,0xf6,0xc9,0xe5,0xe1,0x0b,0xba,0x7d,0x7f,0xc2,0x3f,
+  0x4f,0x69,0xf5,0x03,0x41,0xe6,0xe2,0x9f,0x00,0xc2,0x1e,0x12,0x3a,0x4d,0xe3,0xfd,
+  0xd2,0xf9,0x06,0x5e,0x39,0x91,0xcb,0x7f,0x2e,0x68,0x04,0x52,0x8b,0xfe,0x6b,0xa1,
+  0x16,0xbf,0xc3,0x8f,0xba,0x00,0xbf,0x55,0x66,0x01,0x1e,0x25,0x06,0x99,0xad,0xff,
+  0xde,0xca,0x5f,0xe9,0xc4,0xf6,0xc1,0xf3,0x7e,0xd4,0xd2,0x4f,0x4a,0xae,0x1d,0x41,
+  0x21,0x13,0xa8,0xeb,0x24,0x53,0x56,0x1f,0x0f,0xc4,0xaa,0x5d,0xfe,0x33,0xe2,0x1f,
+  0xbe,0x17,0x8a,0x73,0xec,0x49,0x16,0x11,0xfd,0x3d,0x43,0xd3,0x2a,0x09,0x53,0xb3,
+  0x6b,0xba,0x7d,0x7f,0x0e,0xff,0x66,0x10,0xdb,0xa7,0x68,0x32,0xfb,0x6e,0xd7,0xf7,
+  0xf8,0x17,0x33,0xfe,0x88,0xaf,0x04,0xbe,0xc7,0x67,0x65,0x7c,0x6b,0x9a,0x36,0xc1,
+  0x1e,0x12,0xc6,0xd0,0x5a,0xd9,0xfa,0x6f,0x55,0x9e,0x12,0x7c,0xaa,0x90,0x45,0x63,
+  0x40,0x7d,0xa6,0x13,0x1b,0x69,0xbd,0xf5,0x45,0x62,0x4d,0xc5,0xca,0x6e,0x58,0x7d,
+  0x62,0xcd,0x3c,0xb6,0xc9,0xf5,0xff,0x14,0x3c,0xa1,0x9e,0x63,0x0b,0xbb,0x8b,0x4f,
+  0xfb,0x7b,0xad,0xf8,0xd7,0xb0,0x1c,0x11,0x42,0x49,0x4a,0x3e,0xc0,0x2f,0xbd,0xd4,
+  0x98,0x2a,0xf9,0x92,0x3c,0xc3,0xcb,0xff,0xe1,0x63,0x93,0xf0,0x3c,0x0e,0x1d,0x59,
+  0x62,0x4c,0x87,0x67,0x63,0xe2,0x63,0x85,0x0d,0x15,0xc1,0xae,0x66,0x97,0xcf,0xac,
+  0xc2,0x1b,0x16,0xc9,0xe7,0x3b,0xb2,0xc2,0x8e,0xa6,0xc4,0x36,0x57,0x63,0xe3,0x9f,
+  0xe9,0x06,0xf1,0x9f,0x8b,0x7b,0xe4,0x84,0xcb,0xff,0xa9,0xf8,0x22,0xa1,0x97,0x36,
+  0x5f,0x0f,0xab,0x51,0xd6,0x73,0x5c,0x36,0x3d,0x72,0x96,0xcf,0x13,0x62,0x35,0xb0,
+  0x33,0xc4,0x5a,0x36,0xfc,0x6b,0x38,0xe2,0x8d,0x7f,0xe9,0xfb,0x85,0xbf,0x34,0x51,
+  0x23,0x09,0xbe,0xee,0x26,0x97,0xff,0xb3,0x03,0x05,0x76,0x7b,0xd1,0xe6,0xa6,0xfb,
+  0xec,0x9f,0x97,0xf0,0x4f,0x92,0xf8,0x87,0xc4,0xfe,0x15,0x7c,0x60,0x7f,0x19,0x6b,
+  0xe1,0x02,0x18,0xd4,0x35,0x51,0xa8,0x1a,0xf1,0x80,0x56,0xc6,0x4a,0xed,0xf1,0x16,
+  0xfe,0x89,0x6e,0x0e,0xac,0xf5,0xeb,0x30,0xd0,0x86,0xd3,0x5c,0x2b,0xdf,0x49,0xc4,
+  0xef,0x0a,0x34,0x24,0x29,0x85,0x1c,0x41,0x05,0x5c,0xfe,0xa1,0xc3,0x3f,0xec,0x29,
+  0x1e,0x36,0xce,0x4a,0x8d,0x46,0xf0,0x27,0xf2,0xb0,0x21,0xf0,0x00,0xb9,0x7d,0x88,
+  0xcf,0x1c,0x7c,0x80,0x7d,0x05,0xfe,0x49,0xb8,0xa6,0xe5,0xf7,0x9c,0xf5,0xd3,0x53,
+  0x70,0x46,0x3f,0xca,0xf0,0x10,0x3a,0xd8,0xb7,0x32,0xfc,0x2c,0x8d,0x1f,0xec,0x5c,
+  0xa9,0x13,0x22,0x2a,0x19,0xec,0x3c,0x53,0xf6,0x06,0x8e,0x5f,0x3a,0xd8,0x7c,0x32,
+  0x87,0xff,0x3c,0x24,0x35,0x00,0x1a,0xe1,0xd7,0x6d,0xfe,0xb3,0x0e,0xbd,0x28,0x08,
+  0x44,0xd4,0x8d,0x56,0xe9,0x56,0xce,0x5e,0xcd,0x89,0x7f,0xe1,0x34,0x9b,0x7c,0x5a,
+  0xa2,0x05,0x3a,0x54,0xe2,0x3f,0x27,0x5a,0x52,0x78,0xe5,0x16,0x9f,0xc6,0x8e,0xd0,
+  0x57,0x71,0x7f,0x2e,0xff,0x87,0x94,0x16,0xbd,0xd9,0xb7,0x09,0xb2,0xfc,0xe7,0x9d,
+  0xa8,0xf6,0x47,0x21,0x20,0x10,0x91,0xb1,0xbe,0xa0,0x36,0xbe,0xe1,0x01,0xf0,0xf2,
+  0x7f,0x7e,0x49,0xb4,0xf6,0xbb,0x6b,0x93,0xf1,0x95,0x02,0x08,0x89,0xf8,0xe6,0x51,
+  0x8b,0xff,0xfc,0x34,0xbc,0x39,0x84,0xa6,0xa3,0x07,0x11,0xb5,0xbd,0x3e,0x57,0x49,
+  0x5d,0xfc,0x45,0x44,0x47,0xf8,0xa3,0xf7,0x67,0x61,0x4f,0x67,0xbf,0x85,0x0f,0x93,
+  0xcd,0x16,0x10,0x9a,0xd4,0xe3,0xc1,0xcf,0x11,0x6d,0x2b,0xb7,0xd8,0x65,0xcd,0x64,
+  0x6d,0x2c,0xfe,0x8f,0x32,0x56,0x20,0x60,0xe7,0x0a,0x18,0x63,0x75,0x2c,0xb8,0xce,
+  0xeb,0xff,0x29,0x88,0xc0,0x02,0xb8,0x69,0xf3,0xa2,0xd3,0x89,0x11,0x38,0xd4,0x8d,
+  0xf8,0x27,0x93,0xe5,0xff,0xf8,0xdf,0xe0,0x0b,0xf8,0xa1,0x21,0x39,0xed,0x1f,0xf6,
+  0xf2,0x9f,0x25,0xa3,0x62,0x0e,0x44,0x33,0xfe,0x58,0x12,0xb7,0x21,0x33,0xda,0xe7,
+  0xef,0xf5,0xe1,0x8b,0xa3,0xd4,0x98,0xb7,0xce,0x37,0x96,0x68,0x78,0xc5,0xbc,0x76,
+  0x76,0xf8,0x98,0xb3,0xbf,0xa4,0xf0,0x78,0xbe,0x17,0xae,0x03,0xbf,0x91,0x8d,0x07,
+  0xc9,0x5f,0x61,0x93,0xe9,0x8d,0xee,0xf7,0xab,0x6c,0x72,0x45,0x03,0x9f,0x76,0xd8,
+  0x6f,0xb0,0x01,0xc3,0xb0,0xed,0x83,0xcd,0xff,0x69,0x95,0x5f,0xd5,0x48,0x98,0x34,
+  0xe2,0xff,0x37,0xe3,0xb7,0xfc,0xfa,0x4c,0x70,0xb9,0xfc,0x39,0xf8,0x87,0x8e,0x85,
+  0x99,0xa5,0xcb,0xcb,0x8f,0x85,0x9d,0xf5,0x39,0xa5,0x97,0xc2,0x1c,0x50,0x4c,0x7c,
+  0xd7,0xcb,0xd9,0xfd,0x8e,0x88,0xbe,0xc7,0x70,0xbe,0xb4,0xf5,0x1f,0x20,0x0d,0x1f,
+  0x76,0xd6,0x8f,0x51,0xf0,0x12,0xfc,0x9a,0x60,0xcf,0x88,0xfc,0x75,0xe5,0x12,0x09,
+  0x6b,0xaa,0xf1,0xd8,0x4e,0xf8,0x67,0x00,0x81,0xd0,0x6f,0xbb,0xbe,0xbc,0xf2,0xfe,
+  0xa3,0xb2,0xe6,0xf0,0x0f,0x7b,0x4b,0x7b,0xe0,0x9e,0xd2,0x99,0x40,0x6c,0x1f,0xe3,
+  0x71,0x61,0x7f,0xc2,0x93,0xe1,0x1e,0x36,0xd3,0x2c,0x36,0xca,0x5e,0x80,0xdf,0xaa,
+  0x55,0x37,0xfb,0x6f,0x66,0x1f,0x77,0xfc,0x4b,0x1a,0x62,0xeb,0xef,0xd1,0x30,0xf2,
+  0xf6,0x88,0xf1,0xef,0xa2,0x20,0xec,0x55,0x1b,0x1b,0x32,0x9e,0x84,0x69,0xca,0xad,
+  0x7d,0xec,0x0b,0x29,0x5b,0xff,0xf1,0x0a,0x53,0xef,0x84,0x5a,0xdd,0xff,0x1f,0x6c,
+  0x89,0x72,0x40,0xec,0xef,0xeb,0xa2,0xf0,0x30,0xbe,0xa1,0xc2,0xad,0xb1,0x9b,0xd7,
+  0xb4,0xf9,0x8b,0xd9,0x9f,0x75,0xb9,0xfc,0xe7,0x87,0xc9,0x6c,0x1e,0x0e,0x6e,0x97,
+  0x2c,0xa2,0x4b,0x70,0x9f,0xfc,0x35,0xdc,0x2f,0x1a,0xcd,0x40,0x8a,0xfd,0x92,0x9f,
+  0x1d,0x7c,0xfc,0xb4,0x7f,0x8b,0xfc,0xb7,0x1e,0xfe,0x4f,0xc6,0xc0,0x61,0x65,0xb2,
+  0x60,0xfb,0x10,0xdb,0x79,0x4b,0x79,0x96,0xf8,0x01,0xf2,0x1b,0x30,0x22,0x2d,0x30,
+  0xfd,0xc9,0xce,0xed,0x1e,0xfe,0xf3,0x20,0xe0,0x36,0x97,0x09,0x24,0x9f,0xaa,0x27,
+  0xda,0x8f,0x19,0x6c,0xc7,0x8d,0x89,0x88,0xd0,0xc5,0x2f,0xca,0x73,0xf5,0x5f,0x6b,
+  0x8d,0xe4,0x8f,0xcd,0x38,0xfc,0x1f,0xae,0x7c,0x1e,0x77,0xdb,0x59,0x11,0xdf,0x48,
+  0x22,0x0a,0x07,0xfa,0x67,0x98,0xfe,0x83,0x2c,0xaa,0x10,0x11,0x45,0xed,0x66,0x61,
+  0xfe,0x04,0xaf,0x9d,0xed,0xdf,0xc2,0x46,0x3d,0xf8,0x47,0x37,0xfe,0x05,0x6a,0xfb,
+  0xd5,0x7d,0x64,0x6d,0xcc,0xb0,0xe9,0x23,0x81,0xc6,0x17,0xa5,0xd8,0x76,0x8e,0x40,
+  0x68,0x85,0xbf,0xdb,0x73,0x5e,0xa3,0xf3,0x17,0x85,0x39,0x7c,0xe0,0x0b,0x40,0xda,
+  0x72,0xd4,0x07,0xc8,0x3e,0x9b,0xaa,0x8a,0xe7,0x11,0x32,0xdd,0x32,0x4c,0x77,0xf1,
+  0x39,0x47,0xfb,0xf3,0xb2,0x05,0x72,0x04,0xd1,0x82,0xd6,0xc3,0x16,0x78,0x46,0x5a,
+  0x68,0x7e,0x2a,0x39,0x69,0x3b,0xa9,0x4e,0x18,0x5e,0xdd,0xe5,0x3f,0x9f,0xb1,0xf2,
+  0x77,0x06,0x05,0xbb,0x49,0xb0,0x9d,0x1d,0xfe,0x4f,0xbb,0xf0,0xff,0xdc,0x6f,0x94,
+  0xbb,0x7c,0x3c,0x8b,0xff,0xdc,0x98,0x72,0x60,0xb3,0x10,0x5e,0xe9,0x9a,0xad,0x07,
+  0xce,0xca,0xef,0xc1,0x7f,0xf3,0x39,0x55,0xf7,0xaf,0x91,0x47,0xdd,0xf8,0x17,0x90,
+  0xb7,0xa7,0x24,0xe5,0xdf,0x57,0xf6,0x0e,0xbc,0x6d,0xfb,0x7f,0xe6,0xf3,0x70,0x6b,
+  0x60,0x97,0xc0,0x3f,0x33,0xe2,0x9f,0xec,0x61,0x2e,0xff,0xca,0x8a,0x7f,0x91,0xb7,
+  0x67,0xb1,0x07,0xef,0xf5,0x80,0x7e,0x38,0x14,0x2b,0xcb,0x68,0x0f,0x42,0x04,0xae,
+  0xd5,0xd8,0x5b,0x2e,0xbf,0xa8,0x74,0x87,0xf6,0x84,0xe2,0x85,0x91,0x69,0xb6,0x5a,
+  0xd9,0xdf,0xa6,0x0f,0x5d,0x97,0x06,0xbc,0xbf,0x32,0x23,0xfe,0x50,0xd2,0xc3,0x7f,
+  0x86,0x09,0xf9,0xb7,0x2f,0x9a,0xbb,0x62,0x81,0xf4,0x9c,0x01,0xfe,0x72,0xeb,0x82,
+  0x3a,0xff,0xfe,0x66,0x17,0x9f,0x67,0x4a,0x0f,0xda,0x6c,0x96,0x0b,0xf0,0x6b,0x1b,
+  0xff,0x5c,0xe4,0x8d,0xf1,0x12,0x0a,0x84,0x5d,0xbe,0x0e,0xed,0xed,0xd8,0x53,0x63,
+  0x0e,0x1e,0xb6,0xf8,0xcf,0xf3,0x68,0x59,0x7a,0xee,0x3f,0x62,0x08,0xc4,0x7e,0xa7,
+  0x7e,0x7e,0xf1,0x02,0xf0,0x27,0xe5,0x1c,0xfe,0xb3,0x42,0xde,0x3f,0xff,0x63,0x8c,
+  0x96,0x65,0x76,0x22,0x73,0x50,0x28,0x4e,0xe3,0xfa,0x49,0x18,0x65,0x71,0x5c,0x3f,
+  0x75,0xce,0xef,0x6b,0x0a,0x3e,0x58,0x94,0xe7,0xba,0x7d,0xb6,0x22,0xa2,0xbe,0x9a,
+  0x02,0x85,0x0f,0x4b,0x51,0x28,0x9f,0xef,0xbc,0xbd,0x76,0x3c,0xe8,0x8b,0x29,0xe1,
+  0x06,0x71,0xf2,0xa1,0x1e,0x13,0xb4,0xe7,0xc2,0xc7,0xe1,0x7e,0x5e,0x15,0xef,0x1c,
+  0x62,0xad,0xce,0xf8,0xd6,0x50,0xc0,0x70,0xdc,0x3e,0x16,0xff,0x99,0x89,0x40,0x98,
+  0x51,0x9c,0x96,0x4d,0xfe,0x0b,0xf8,0x5a,0xe1,0xd2,0x58,0xa7,0x87,0xff,0x3c,0xf9,
+  0xa0,0x76,0x19,0x6e,0xb0,0xd4,0xe2,0xc5,0x87,0xb8,0x6d,0x4d,0xba,0x03,0x7e,0x25,
+  0x89,0xf7,0x25,0xe9,0xc6,0xbf,0x04,0xff,0xbc,0xde,0x88,0xe6,0xe8,0xff,0x2c,0x5f,
+  0x60,0xf8,0xd3,0x68,0xf6,0xc5,0x51,0x25,0x3d,0xe9,0xb0,0x9b,0x3f,0x25,0x6d,0x71,
+  0xb2,0x2d,0xdc,0xf3,0xd4,0x63,0x50,0x65,0xa0,0x30,0x64,0xbb,0x9a,0x5f,0x72,0xfc,
+  0x15,0xba,0xe0,0xff,0xcc,0xca,0xe4,0xf2,0x9d,0x9e,0xe4,0xd7,0xc5,0xfd,0x6b,0xc2,
+  0x27,0x74,0xbc,0xa2,0x6f,0xa0,0xf8,0x97,0xfd,0x59,0xa5,0x08,0x35,0x66,0xf2,0xce,
+  0x17,0x6d,0x08,0x23,0x85,0xf0,0x00,0x5e,0x99,0xdf,0x74,0xc2,0xe5,0x3f,0x2b,0x82,
+  0xff,0xdc,0x1d,0xf0,0xc4,0xbf,0x46,0xf0,0x58,0x74,0x53,0x57,0x30,0x55,0x7e,0x96,
+  0xde,0xa0,0x24,0x22,0xde,0x73,0x2e,0xbe,0x82,0xd4,0x95,0xf8,0x3f,0xf4,0x1a,0xae,
+  0x89,0x0b,0x44,0xe4,0x9e,0xdf,0x55,0x10,0xe7,0x7d,0x23,0xda,0x33,0xc1,0x79,0x7f,
+  0x25,0xdf,0x0f,0x07,0x6e,0x41,0xc1,0xc3,0xff,0xa9,0xa8,0x11,0xde,0x06,0xb5,0x27,
+  0x31,0xce,0x9f,0x53,0xf7,0x31,0xbe,0x33,0x1e,0x8e,0x6f,0x48,0x7a,0xfc,0x09,0x59,
+  0xfe,0xb3,0xa1,0x3e,0x90,0xeb,0xff,0x99,0x41,0x8e,0x8e,0x95,0xd2,0x7e,0xb6,0x62,
+  0x91,0x3f,0x99,0x38,0xe2,0x8c,0xb7,0xfc,0x3f,0xb5,0xe3,0xfc,0x21,0xd1,0x45,0x7e,
+  0xad,0x89,0xbe,0x8a,0x1b,0xff,0x92,0xc3,0x7f,0x9e,0x62,0xc1,0xbc,0x40,0xde,0x7c,
+  0x17,0x54,0xf8,0xd7,0xca,0x71,0xda,0x7f,0xf1,0x4a,0xf3,0xa9,0x42,0xdb,0xfe,0xec,
+  0x2b,0xce,0xe7,0x3f,0x93,0xf0,0x1b,0x71,0xa5,0x9c,0x4c,0xd3,0x8f,0x0c,0xff,0xa0,
+  0x7c,0x0a,0xff,0xd4,0xfa,0xcc,0xa7,0x78,0x99,0x82,0xfa,0xc9,0xf3,0xff,0x20,0x6c,
+  0xd8,0x5c,0x7e,0x86,0x3d,0x0d,0xb3,0xcd,0xe0,0x60,0xb3,0xcf,0x59,0x3f,0x21,0x48,
+  0x15,0x50,0x18,0x4e,0xf5,0xf0,0x9f,0x85,0xa0,0xfa,0x89,0xff,0xd3,0x0d,0x61,0xbc,
+  0x22,0x2f,0xce,0x8b,0x7f,0xd1,0x7c,0x0b,0xf3,0x89,0xd0,0x16,0xfe,0xd1,0x71,0xe2,
+  0xcc,0xcd,0xd7,0x0b,0x55,0x6c,0x57,0x49,0x7b,0x13,0xfa,0xd3,0x86,0xa5,0xf5,0xca,
+  0x23,0x71,0x7f,0x0f,0x3b,0xe2,0xc6,0xbf,0x14,0xe2,0x0b,0x45,0x97,0x05,0x72,0xfd,
+  0x39,0x03,0x0d,0xad,0x42,0xe8,0x83,0xba,0x55,0x41,0x4d,0xee,0x75,0xf1,0x8f,0xb6,
+  0x5d,0xcd,0x41,0x3b,0xd6,0xf8,0x4d,0x0d,0x2b,0xef,0x17,0xfc,0xe7,0x6b,0x16,0x18,
+  0x28,0x2c,0xcb,0xf5,0xff,0x20,0xde,0x9b,0xc4,0x3b,0xf3,0xd6,0x9b,0xc5,0x08,0x32,
+  0xe6,0x51,0x68,0xd2,0x5d,0x3f,0xaa,0x42,0xf8,0x87,0x60,0x0f,0xe4,0xf2,0x7f,0xb8,
+  0x9a,0x62,0x43,0x70,0x68,0x7b,0x38,0xa5,0xbe,0xed,0xf1,0xff,0xa8,0x59,0xfe,0xf3,
+  0xad,0xd7,0x1b,0xe3,0xfd,0xa5,0xc7,0x8d,0x9d,0x92,0xde,0x9f,0x08,0x94,0x1d,0x76,
+  0xf0,0x8f,0x6e,0xf3,0x9f,0xdb,0xc4,0xfb,0x5b,0xec,0xf8,0x43,0x46,0xd4,0xbb,0xf1,
+  0xfe,0x7b,0xa0,0x3a,0xa3,0x22,0xfe,0x69,0xb3,0xdf,0xdf,0x48,0xe8,0xbb,0x08,0x42,
+  0xc8,0xed,0x53,0x9d,0xeb,0xff,0x39,0x1d,0xf8,0x27,0x14,0xce,0xac,0x9d,0x9d,0xb9,
+  0x0d,0xf1,0x4f,0xa1,0xf3,0x3c,0x53,0x76,0x68,0xd9,0xa4,0xdd,0x3c,0xfe,0xcf,0x5f,
+  0x5a,0xfc,0x9f,0x03,0x66,0x0e,0xfe,0x89,0x2b,0x87,0x68,0xdb,0x1a,0x2e,0xfe,0xb3,
+  0x1c,0xff,0x4f,0x72,0xe1,0x49,0xdc,0xbf,0x3e,0x30,0xce,0x24,0x6f,0xc8,0xdc,0xbf,
+  0xaa,0x2a,0xe4,0xfa,0xab,0x61,0x8b,0xb1,0x57,0x23,0xf4,0x22,0x7f,0x36,0x9f,0xcf,
+  0xa3,0x0f,0x69,0x7b,0xe6,0x55,0x99,0x25,0x6d,0x6c,0x9b,0xcb,0xaf,0x10,0xfc,0xe7,
+  0x59,0x87,0x1f,0xca,0xf5,0xff,0xa8,0x7f,0x87,0xe3,0xcb,0x5e,0x81,0x83,0x6c,0xda,
+  0x20,0x5e,0x89,0x3b,0xe3,0x8d,0x0a,0x71,0xec,0xca,0x80,0x2e,0x68,0x2d,0x81,0xac,
+  0x3e,0xe3,0x35,0x83,0x6a,0x9a,0x7d,0xaa,0x2a,0x5d,0x5a,0x93,0x41,0xe0,0x3d,0xe8,
+  0xc4,0x97,0x7b,0x0b,0x76,0x50,0x92,0x88,0x59,0x90,0xcc,0xf1,0xff,0x98,0x8d,0xfd,
+  0x91,0x51,0xf9,0x1d,0xfc,0xe1,0xe6,0x7d,0x12,0xe7,0xeb,0xe2,0x9f,0x94,0xe6,0x44,
+  0xbb,0xc6,0x13,0x0f,0xde,0x81,0x73,0xea,0x02,0xb3,0x70,0x0b,0xae,0xb7,0x7c,0xfe,
+  0xb3,0xc0,0x03,0x79,0x8e,0x91,0xe6,0x7a,0x34,0x74,0x73,0x32,0xf8,0x95,0x39,0x8e,
+  0xff,0x8c,0x8b,0xdc,0xa6,0xf1,0x58,0xf9,0x5c,0x66,0x49,0x9a,0x45,0xa5,0x5d,0x3c,
+  0xfc,0xb4,0xff,0x3b,0x39,0xf8,0x27,0x3b,0x7e,0xcb,0x38,0x7f,0x51,0xba,0x6c,0x1a,
+  0xaa,0x3b,0xdc,0x87,0x08,0x21,0xe3,0xae,0x37,0x10,0xa4,0x0e,0xf2,0xf6,0xd8,0x69,
+  0x5f,0xcc,0x8a,0x10,0x09,0x20,0x94,0xe6,0x3a,0x65,0x20,0xba,0xfe,0x1f,0x08,0xad,
+  0x76,0xe7,0xfb,0x44,0x8e,0xff,0x67,0xd4,0x1f,0xc5,0x35,0x2e,0x10,0x91,0x59,0x98,
+  0xcb,0x7f,0x5e,0xe8,0xce,0xb7,0xd8,0xde,0xc8,0x44,0x44,0xec,0x02,0x3c,0x49,0x1a,
+  0xf0,0xfa,0x7f,0x2e,0xc1,0xcf,0x89,0x9f,0xf6,0x94,0xbf,0x1d,0xb7,0x95,0xdd,0x94,
+  0xff,0xd5,0x40,0x19,0xe2,0x99,0x49,0x67,0xe5,0x0b,0xc6,0x05,0x7e,0xc3,0x70,0xf0,
+  0xac,0xec,0xfa,0x7f,0x38,0x9c,0x56,0x37,0x48,0xe1,0x01,0x75,0x2d,0x0b,0x2b,0x44,
+  0xfb,0xf1,0x5f,0x64,0x3f,0xc4,0x3f,0x44,0x21,0xc9,0x2e,0x9a,0xfb,0x78,0xd8,0xf4,
+  0x6f,0x63,0xa3,0x8e,0xff,0xb9,0xfb,0xe6,0xe3,0xda,0xbf,0x20,0xda,0x51,0x81,0x2d,
+  0x46,0xe0,0x27,0xb2,0xff,0x68,0xc7,0xaf,0x31,0xe5,0x30,0x3b,0xce,0xf7,0xf1,0x9a,
+  0x14,0xaa,0xc2,0x8d,0x77,0x98,0x95,0x1b,0x11,0x3d,0x6e,0x4b,0xe1,0x6a,0x09,0x0b,
+  0xda,0x8f,0x3f,0x0d,0x3b,0xa4,0x27,0x48,0xe0,0x85,0xa7,0x61,0x5f,0x22,0xdc,0xef,
+  0xe7,0x87,0x47,0xbd,0xfc,0x9f,0xc0,0x4f,0xa5,0xba,0xf7,0x02,0x23,0x78,0x1a,0x7a,
+  0x1b,0xb5,0x51,0x42,0x8e,0xc4,0xf7,0xd9,0x3c,0x91,0x2f,0xa9,0x8e,0xf2,0xbf,0xd7,
+  0x97,0x76,0x54,0x9b,0x2d,0x4e,0xfc,0x88,0xf0,0x4f,0x0a,0xb5,0xf7,0x7a,0xf5,0x00,
+  0x88,0x8d,0xde,0xe2,0xc3,0xdf,0x64,0x06,0xcf,0x21,0x50,0xbc,0x20,0xdd,0x94,0xda,
+  0x90,0xc9,0xcb,0x7f,0xa7,0xf8,0x4e,0xc9,0x66,0x19,0xd1,0xa6,0x8e,0xfa,0x9f,0x4f,
+  0x0b,0x55,0x45,0xb5,0xef,0x29,0x5f,0x0d,0x63,0x21,0xdc,0x1a,0x36,0xcb,0xff,0x95,
+  0x93,0xff,0xf5,0x03,0x8b,0xbf,0x14,0x85,0xce,0x38,0xe5,0x7f,0xc9,0xab,0xe1,0x49,
+  0x7d,0x9e,0xb9,0x21,0x1d,0xae,0x87,0xf9,0x26,0x1a,0x22,0xce,0x5c,0xfe,0xb3,0xa9,
+  0x14,0xf3,0x4e,0x3a,0x8f,0x27,0xcb,0xba,0x7c,0x9d,0x6e,0xfe,0x85,0x6e,0x11,0xc3,
+  0x76,0x1a,0x51,0x43,0x8b,0x79,0xf8,0xcf,0x84,0x7f,0xc8,0xfb,0xa1,0x5e,0x17,0x2e,
+  0x73,0xf0,0x8f,0xb2,0x97,0x4f,0xcb,0xf8,0x97,0xb3,0xcf,0xc1,0x1e,0x3e,0x93,0xa8,
+  0xc2,0x17,0x1c,0xff,0x73,0x6b,0x28,0x2a,0x3d,0xa5,0x45,0xcd,0xef,0x6a,0xac,0x4b,
+  0x79,0x8a,0xf0,0x4f,0x9d,0xbc,0x11,0xde,0x87,0x98,0x79,0x7f,0x4a,0x5e,0x02,0xef,
+  0xc7,0x10,0x5a,0xd7,0xc9,0x27,0x9c,0xf3,0x3b,0xe2,0x1f,0xb8,0xac,0x35,0x9a,0xb7,
+  0x8e,0x7e,0xc2,0xc9,0x1f,0xfc,0x1a,0xfc,0x36,0x44,0xc2,0xa4,0x83,0x70,0x49,0x6b,
+  0xec,0xff,0xc6,0xe8,0x24,0x37,0x9e,0xae,0x8a,0xf8,0x57,0xbd,0x81,0xfb,0xe3,0xd7,
+  0xe0,0x56,0x5a,0x9f,0xc2,0x31,0xdb,0x8b,0xfa,0x99,0xef,0x9f,0x69,0x65,0x7c,0x77,
+  0x57,0x33,0x0f,0x7f,0xe6,0x20,0x9d,0x9e,0xfa,0x8a,0xe3,0x65,0x93,0xad,0xfc,0xf7,
+  0xbf,0x4f,0xbc,0x02,0xbb,0xf5,0x2a,0xb2,0xa8,0x93,0x8d,0x17,0xa4,0x1b,0x0d,0x7f,
+  0xbc,0x69,0x97,0x9b,0x4f,0x01,0xdf,0x65,0xf7,0x74,0xcf,0xca,0x84,0x42,0xec,0x36,
+  0xc9,0xc1,0x7b,0xdf,0x4e,0x55,0x65,0xfc,0x23,0x4d,0x25,0xc6,0xb7,0x10,0xff,0xf8,
+  0x96,0x97,0xa9,0xee,0xfe,0x42,0xf1,0x2f,0x1e,0x1d,0x28,0x3a,0xc0,0x02,0xdc,0xe5,
+  0x3f,0x33,0xd4,0xe7,0xdc,0x44,0xa0,0xf4,0xc1,0xb6,0x88,0x79,0xed,0x42,0xf6,0x1d,
+  0x37,0xfe,0x85,0xf8,0xe7,0x5e,0xd6,0xc8,0x03,0x99,0x8e,0x35,0xca,0x61,0x85,0xf0,
+  0xcf,0xe7,0x47,0xe0,0x25,0xd8,0xc6,0x83,0x27,0xe5,0x08,0xbc,0x0a,0x8d,0x8f,0x97,
+  0x64,0xaa,0x6f,0x72,0xf9,0xcf,0x4e,0x3e,0x4e,0x73,0xaa,0xd0,0x12,0xa4,0x8c,0x36,
+  0x66,0x88,0x8d,0xc9,0x84,0x31,0x75,0x06,0x0a,0x9d,0x5e,0xfe,0xf3,0x76,0xe3,0x4d,
+  0x26,0xb2,0x57,0x5a,0xe0,0xa8,0x56,0x67,0x58,0x1b,0x9f,0xfe,0x75,0x4a,0x8b,0xde,
+  0x0e,0x47,0x6b,0x28,0x74,0x52,0xed,0x8d,0x7f,0x21,0x9e,0x61,0x51,0xa3,0x3b,0xc9,
+  0x6a,0xd8,0x7a,0x08,0x67,0xf7,0x5f,0xf3,0x4b,0x86,0xc8,0xf0,0x5a,0x6f,0x12,0x35,
+  0xa8,0x7a,0x5c,0xfe,0x97,0xe1,0x4b,0x97,0xd4,0x28,0x62,0x7c,0x0f,0x8d,0x37,0x6a,
+  0xb3,0xe3,0xd5,0xe8,0xa2,0xc8,0xf8,0xf8,0x17,0xde,0xc4,0xf2,0xff,0xa4,0x0c,0x7f,
+  0x59,0x19,0xe2,0x01,0xdd,0x02,0x06,0xc2,0x23,0x14,0xd2,0xca,0x3c,0xf1,0xaf,0x29,
+  0x77,0xb6,0x8e,0xb5,0x35,0x54,0x94,0xac,0x2d,0xd7,0xd9,0x80,0x52,0x87,0x47,0x6b,
+  0xd9,0xca,0x40,0x0f,0xae,0x95,0xb7,0xb6,0x0e,0x48,0x0d,0x15,0x93,0x0b,0xe4,0x4b,
+  0x0e,0xff,0x79,0xdf,0x94,0x61,0xf5,0x22,0x08,0xff,0xcf,0x1e,0xc1,0x7f,0xbe,0x5f,
+  0xe4,0x7f,0x69,0xe4,0xd8,0x91,0x87,0xff,0xfc,0xe7,0x52,0xe3,0x22,0x14,0xb6,0xb9,
+  0xf9,0x5c,0x05,0xbf,0x21,0x7e,0x54,0x9b,0x7f,0xd3,0xfa,0xd5,0xba,0xe5,0xff,0x69,
+  0x22,0x06,0xf5,0x3c,0x41,0xa4,0x81,0x67,0xf1,0x79,0x82,0xc9,0xea,0xe9,0x4e,0xbc,
+  0x29,0x44,0xf1,0xc7,0x30,0xc2,0x9e,0x75,0x3e,0x5d,0x1d,0x12,0xf8,0x27,0x6c,0xa5,
+  0x7d,0x95,0x24,0x98,0xae,0x76,0xe3,0x46,0x5f,0xc2,0x27,0x95,0x78,0xe2,0x5f,0x88,
+  0x7f,0x54,0x9c,0x5d,0xe8,0x91,0x16,0xa9,0xc3,0xca,0xff,0xc2,0xf9,0x1a,0x3a,0xea,
+  0x67,0xdd,0x5a,0xd8,0xca,0xa3,0xb7,0xf8,0x37,0x25,0x36,0x49,0xb6,0xfe,0x11,0xff,
+  0x58,0x61,0xaf,0x4d,0xac,0xa6,0xcc,0xca,0x7f,0x2f,0x24,0xfe,0x79,0xd8,0xf0,0x6d,
+  0x66,0x0a,0x7b,0x94,0xd5,0xb6,0xb2,0x07,0xca,0x1e,0xb1,0xd5,0x83,0xf8,0x47,0x84,
+  0xbd,0x3e,0x19,0xec,0x91,0x57,0xf2,0xf5,0x40,0x3f,0xab,0x20,0x6e,0xed,0x32,0x82,
+  0xa5,0xf2,0x76,0xf5,0xcd,0xfe,0xda,0xb6,0xa0,0xd6,0xd9,0x5b,0xe1,0xf0,0x9f,0x89,
+  0x0f,0xa6,0x35,0xb4,0x07,0x7b,0x9a,0xed,0x40,0x61,0xf9,0x30,0xbc,0x0b,0x0b,0x16,
+  0x95,0xf4,0xe0,0xf8,0x17,0x8f,0x36,0x2c,0x0a,0x26,0xfd,0xcb,0xf2,0xf2,0xbf,0xea,
+  0x08,0xe4,0xc4,0xd5,0x21,0x4e,0xcb,0x6c,0x11,0xc2,0x4e,0xad,0x41,0x9a,0x64,0x03,
+  0xa1,0xdb,0xbc,0xf1,0x2f,0x55,0x59,0x40,0x6c,0x9f,0x0e,0x35,0x15,0x8e,0xc0,0x7d,
+  0x50,0xdb,0x21,0xf2,0xbf,0x0e,0x0d,0xd6,0xf2,0x6b,0x09,0x08,0x1d,0xb2,0x80,0xd0,
+  0x31,0xc7,0xff,0xac,0x16,0xdc,0x22,0xac,0x8d,0x2f,0xcd,0x02,0x5a,0x82,0xf2,0xdf,
+  0x35,0xda,0xb8,0x4d,0xeb,0xc5,0xd1,0xe6,0xa0,0xf0,0x37,0x31,0x38,0xe6,0xda,0x1f,
+  0x69,0x0a,0xec,0x4d,0x56,0x0f,0xab,0x77,0xe3,0xf9,0x7d,0x1d,0xbd,0xbf,0x6b,0x12,
+  0x93,0x11,0xf6,0x88,0x7c,0xf0,0x57,0xf8,0x63,0x2d,0xb3,0x4e,0xfb,0xdb,0xeb,0x32,
+  0x15,0x0e,0xff,0x39,0x54,0x86,0xf6,0x76,0xe7,0x9b,0x25,0x97,0x9a,0xa7,0x6a,0xfd,
+  0x84,0x7f,0xe6,0xcb,0x9f,0x13,0x40,0xc8,0xbf,0xa6,0xfa,0x35,0x12,0x46,0x82,0xff,
+  0x94,0xc3,0x7f,0xde,0x03,0xe7,0x79,0x43,0x1f,0xa5,0x81,0xe3,0xf3,0x66,0xf3,0xc1,
+  0xcf,0x32,0x2b,0x11,0x2c,0x85,0x2b,0x6a,0xa0,0x6b,0x97,0x27,0xfe,0x15,0x57,0x76,
+  0x09,0xd8,0x73,0xcf,0x58,0x79,0x03,0x7c,0x82,0xe2,0x17,0xd9,0x40,0xd8,0x70,0xf0,
+  0xe2,0x06,0xca,0x56,0x5c,0x38,0xda,0xfa,0x8f,0xd5,0x5a,0xd8,0x1e,0xdf,0x0b,0x9b,
+  0xe1,0x97,0x16,0x8c,0x99,0x1c,0x5e,0x57,0x6a,0x99,0x1d,0xcb,0xb1,0xd3,0xce,0xea,
+  0xe1,0x05,0x75,0xe1,0x91,0xd0,0x5d,0x6c,0x86,0x87,0xff,0x9c,0x44,0xb4,0x33,0xb3,
+  0x5f,0xf8,0x8b,0xd6,0x42,0x95,0xf8,0x43,0x31,0xdf,0x6b,0xdb,0xa7,0x4f,0x86,0x6f,
+  0x69,0xb3,0x4c,0x75,0x94,0x29,0x1e,0xfc,0xd3,0x45,0xfe,0x8d,0xb1,0x6b,0x1b,0x59,
+  0x10,0xb8,0x30,0xe3,0xc2,0xd1,0x11,0x35,0xaf,0xbd,0x9e,0x05,0xd4,0x07,0xba,0xa3,
+  0x87,0xbb,0xd3,0x75,0x21,0x97,0xff,0x8c,0xf8,0xe7,0x32,0xff,0x68,0x26,0x38,0xea,
+  0xaf,0x35,0x8e,0xc1,0x2e,0xda,0xe8,0xb3,0x40,0xe8,0x8c,0x5c,0x0f,0x2f,0x1b,0xb3,
+  0x32,0x81,0xb3,0x9d,0xb5,0x8e,0xfd,0x49,0x59,0xf9,0xc8,0xfd,0x41,0xaa,0xbe,0x32,
+  0x66,0x64,0xf1,0x80,0xc3,0x18,0x3f,0x6b,0x2c,0x30,0x67,0xa5,0x73,0xf8,0xcf,0xc2,
+  0x1f,0x62,0x2e,0xc1,0x6d,0x51,0xb9,0xc0,0xe7,0x98,0xa8,0x1f,0x9b,0x0f,0xdc,0x79,
+  0x41,0xb9,0xcc,0x6e,0x22,0xc7,0xbe,0x97,0xff,0x3c,0x0d,0xcf,0xef,0x33,0x29,0x5b,
+  0x27,0x8a,0x68,0x64,0x9b,0xe9,0x47,0x6b,0x04,0xfb,0x6d,0x8f,0xc4,0x3e,0x6e,0x65,
+  0x24,0x79,0xf0,0xcf,0x5f,0x09,0xb4,0xd3,0x4a,0xe3,0x0f,0xc4,0x71,0x9b,0x4e,0x0a,
+  0xbe,0xf4,0x0c,0x6b,0xfc,0x7e,0x53,0x8c,0xd7,0x73,0xec,0x8f,0xc8,0xee,0xb1,0xd4,
+  0xa2,0x13,0x10,0x22,0x46,0xb4,0xb5,0xde,0x8a,0xd2,0x92,0x10,0x12,0x1d,0x8e,0xfa,
+  0x43,0x35,0x70,0x9e,0x65,0xe3,0x83,0x63,0x84,0x76,0x92,0xb8,0x9f,0x8e,0x11,0x11,
+  0xba,0x9d,0xe2,0xe9,0xd2,0x4d,0x7d,0xc1,0xd1,0x6a,0xdd,0x93,0xff,0x75,0xc6,0xa6,
+  0xf5,0x12,0xda,0xc9,0x02,0xbf,0x0b,0x59,0xe0,0xa7,0x5e,0x90,0xbe,0x41,0xc2,0x9b,
+  0x5d,0x0e,0xfe,0xf9,0x96,0xe5,0xf6,0x29,0x1e,0x42,0xd8,0x8c,0xa7,0xdd,0x8c,0xd7,
+  0x11,0xf4,0x39,0xe8,0x87,0xeb,0xf5,0x99,0x23,0x72,0xcc,0x13,0xff,0xfa,0x21,0xd1,
+  0x7e,0x5e,0x57,0x7b,0xd8,0x3b,0x14,0x5f,0x76,0xeb,0xff,0xf8,0xeb,0xf0,0x45,0xeb,
+  0x1e,0x0c,0xc7,0x8b,0xba,0x99,0xee,0xd8,0x9f,0x01,0x65,0xa3,0xea,0xc0,0x3c,0x6b,
+  0x9a,0x85,0xf6,0x41,0x23,0xb1,0x04,0xd5,0x5d,0x63,0xf8,0xf4,0x70,0xd8,0xb1,0x6f,
+  0x66,0x01,0xc2,0x3c,0xc5,0xe2,0x3f,0xab,0x07,0xb4,0x5c,0x47,0x50,0x04,0xed,0x5b,
+  0x38,0xee,0xef,0x66,0x2e,0xff,0xc7,0x28,0x38,0x1d,0x12,0xd5,0x12,0x92,0xe5,0xa7,
+  0xd5,0x73,0x1d,0xb9,0x78,0xb8,0x05,0x5f,0xdc,0xb9,0x77,0x07,0xa3,0xb2,0x96,0x9f,
+  0xff,0x6e,0x06,0x5f,0x20,0xb5,0xf0,0xbc,0x40,0xa1,0x7a,0x29,0xd9,0x68,0x04,0x08,
+  0xff,0xd8,0xbf,0x57,0x4b,0x96,0xff,0x2c,0xe2,0x8f,0xe7,0x72,0xf1,0xf6,0xa4,0x1a,
+  0xfe,0x76,0x68,0xd7,0xf2,0x29,0x8f,0x78,0xea,0xff,0x0c,0x55,0x8a,0x78,0xe8,0x10,
+  0x9e,0x1f,0x4f,0xd3,0xb1,0xcb,0xf4,0xef,0x73,0x03,0xa3,0x51,0x48,0x40,0x78,0x85,
+  0xba,0x3d,0x31,0x2e,0xff,0x3d,0x13,0x71,0xf4,0xe3,0x04,0xe2,0xd3,0xac,0x18,0xb6,
+  0x19,0x29,0x43,0x53,0x99,0xcb,0xff,0x11,0xf9,0x5f,0x89,0x99,0x96,0x3f,0xe4,0xf1,
+  0x3c,0x62,0xf0,0x02,0x63,0x1d,0xaf,0xce,0x84,0x8e,0x86,0x55,0x6f,0xfe,0x97,0x49,
+  0xfe,0x1f,0xca,0xff,0x32,0xde,0x73,0xf8,0x3f,0x96,0x23,0x28,0x00,0xbf,0x80,0x98,
+  0xa1,0x4e,0x93,0x3d,0xf5,0x7f,0x8a,0x0f,0xb6,0x09,0xfc,0x4c,0x6a,0xb9,0x64,0xe4,
+  0xe8,0xe7,0xe3,0x63,0xb8,0x42,0x66,0x99,0x25,0x8b,0x3c,0xf5,0x7f,0xac,0xfc,0xaf,
+  0xac,0x5a,0xce,0x19,0xb9,0xfa,0x5f,0xa7,0x9c,0xc0,0xfb,0x17,0x6b,0xd5,0x4d,0xce,
+  0xfa,0xb1,0xf2,0xbf,0xb2,0xc7,0xa8,0xc7,0xf3,0x12,0x4b,0x05,0x11,0xda,0xf0,0x1b,
+  0xac,0xec,0x2a,0xfb,0xfe,0x06,0x78,0x68,0x4e,0xf9,0xf3,0xfd,0x40,0xff,0x36,0xff,
+  0x78,0xdc,0xbf,0x9a,0xb5,0xe6,0xe6,0x7f,0x65,0xd5,0xa8,0xee,0x4a,0xe6,0xf2,0xa9,
+  0x9e,0xe3,0x09,0x84,0x46,0xfe,0x1a,0x76,0x4d,0x5e,0xfd,0x9f,0x5a,0x1e,0xec,0xed,
+  0x1c,0x4f,0x84,0x1e,0x83,0x9f,0xf1,0x1b,0x37,0x15,0x8f,0x34,0x7f,0x55,0xb1,0xf5,
+  0x6f,0xe7,0xbf,0xdf,0x3f,0x81,0xff,0x87,0xf2,0x71,0xda,0x76,0x69,0x4a,0x57,0x75,
+  0x7e,0xfe,0x57,0xf6,0x98,0x7f,0x7e,0x82,0x44,0xef,0x05,0xab,0x02,0xc9,0xa7,0xee,
+  0xcd,0xe7,0x3f,0x2f,0x73,0xd2,0xbe,0xbc,0x44,0xdc,0x1a,0x7d,0xbf,0x19,0x5e,0xa5,
+  0x5e,0xc5,0x22,0xf9,0xf8,0xa7,0xc5,0x9f,0x6c,0xca,0xf7,0x57,0x68,0x14,0x08,0x0b,
+  0x85,0x89,0xb8,0xb2,0xce,0x93,0xff,0xa5,0x64,0xbd,0x3d,0xcc,0x85,0x3d,0xb6,0x3f,
+  0x84,0xf8,0x3f,0x61,0xc4,0x3f,0xcc,0x57,0x61,0xaf,0x87,0xb1,0x9c,0xfc,0xf7,0xdb,
+  0x3d,0x13,0xf7,0xaf,0x95,0x11,0x1a,0xe1,0xd6,0xbc,0x91,0x57,0x3f,0x22,0xdb,0xcf,
+  0xb3,0x71,0x4a,0x76,0x76,0x83,0x36,0xec,0xf1,0xcc,0x77,0x0f,0x5c,0xd4,0xfe,0xcd,
+  0x58,0x3a,0x28,0x9f,0x72,0xe3,0x4d,0x05,0x54,0x04,0xc9,0xeb,0x2f,0xf2,0x38,0x82,
+  0xae,0x87,0x8b,0xea,0x6e,0x23,0xda,0x26,0x2f,0x76,0xc6,0x67,0xf3,0xdf,0xb3,0x6e,
+  0x1f,0xdd,0xf5,0xff,0xc0,0xad,0x09,0xd0,0xd5,0x7d,0xc6,0x02,0x50,0x79,0xb8,0xd0,
+  0xcb,0xff,0xa1,0xd9,0x59,0xec,0x82,0x9d,0xad,0x39,0xf3,0x4d,0x28,0x0a,0xc5,0xfb,
+  0xf0,0x55,0x5d,0xe6,0xd8,0x9f,0x9e,0xca,0xed,0x15,0xfb,0x2d,0xfc,0x83,0x6a,0xd4,
+  0xbd,0xf5,0x04,0xb4,0x6b,0x28,0x11,0x7e,0x46,0x9b,0xba,0x99,0x15,0x3a,0xfe,0x31,
+  0x8b,0xff,0x3c,0x01,0xdf,0xc9,0x0a,0x74,0xbe,0xab,0xef,0x5a,0x89,0xe7,0xa3,0x55,
+  0x2e,0xfe,0xb1,0xf8,0x3f,0xd9,0x61,0xdc,0x16,0x10,0x08,0x4d,0x22,0x22,0x34,0xae,
+  0x87,0x45,0xfe,0x4d,0xf9,0xf9,0x5f,0x16,0xc9,0xca,0x59,0x6f,0xba,0x10,0x3e,0xca,
+  0x27,0x65,0x60,0x24,0xb6,0x40,0x29,0xe9,0xf6,0xbb,0xe7,0x0b,0x2b,0xff,0x7d,0x56,
+  0x97,0x70,0xfb,0x7c,0xc7,0xf2,0xff,0xf4,0xda,0x8e,0xa0,0x31,0xb8,0xcf,0xa8,0x4a,
+  0x76,0xc7,0xbd,0xf9,0xef,0xde,0xfc,0x8b,0x2c,0x0d,0x23,0x60,0x1f,0xcc,0x8f,0xc0,
+  0x56,0xb3,0xf7,0xbd,0x88,0x8e,0xe3,0x9d,0xfd,0x05,0x84,0xdb,0xc4,0x10,0x6f,0xeb,
+  0xb7,0xe9,0xb5,0x5d,0x9e,0xad,0x87,0xe3,0xbf,0x9b,0xfd,0x2c,0xc2,0xd9,0xe7,0xcd,
+  0x90,0xc9,0xf4,0x0a,0xfb,0xfe,0xbd,0xdd,0x9f,0xcb,0xcb,0x7f,0x5f,0x2e,0x5b,0x11,
+  0x31,0xff,0xd7,0xb6,0xbd,0x07,0xa7,0x3a,0x6e,0x4c,0xd5,0xae,0x92,0x67,0xe4,0xd7,
+  0xff,0x31,0x82,0xe9,0xf2,0xd3,0xf0,0x9a,0xd6,0x40,0x85,0xa4,0x2c,0x7b,0xe2,0xdf,
+  0x23,0x9f,0x21,0x2a,0x5a,0x5f,0x0e,0xff,0x07,0x44,0xfe,0x97,0xb5,0x6d,0xa1,0x70,
+  0x93,0x83,0x7f,0xac,0x8d,0xec,0x4c,0xc7,0x6c,0x5d,0x19,0x91,0x4d,0xc7,0xdf,0xfb,
+  0xfd,0xd2,0x2d,0xc6,0x6f,0xed,0xe7,0xa7,0xc4,0x2e,0xc4,0x3f,0xb6,0x45,0x6a,0x7a,
+  0x05,0x81,0x4d,0x15,0xa8,0x46,0xd3,0x49,0x47,0x9f,0x00,0x5b,0xda,0x6c,0xeb,0x24,
+  0xed,0x86,0xeb,0x2c,0xbc,0x44,0x0c,0x22,0xf2,0x57,0xeb,0x07,0xa1,0x3a,0x59,0x14,
+  0xf7,0xd4,0xff,0xa1,0xfc,0x77,0xc4,0x3f,0x46,0xf9,0x8d,0xa8,0xcf,0x27,0x92,0x62,
+  0x7f,0xb7,0x03,0xf1,0xec,0x39,0x25,0x6d,0xa4,0x52,0x45,0x15,0xec,0x68,0x81,0x1b,
+  0xff,0xca,0xba,0x35,0xf6,0xe1,0x7c,0x2f,0xf3,0x05,0x2e,0xfe,0x91,0xa9,0x42,0xdd,
+  0x98,0x11,0x5b,0x35,0x33,0xea,0xad,0xff,0x23,0xd9,0xfa,0x41,0xb5,0xdc,0x24,0xe5,
+  0xda,0xdb,0x37,0xf8,0x98,0xd4,0x30,0x58,0xd2,0x9b,0x93,0xff,0x7e,0x50,0x11,0xec,
+  0x17,0xaa,0xf6,0x23,0xe2,0x5f,0x3f,0x71,0xec,0x79,0xf5,0xdf,0xc3,0x05,0xf5,0x26,
+  0x98,0x9a,0xe9,0x54,0x5b,0xec,0xf7,0xd7,0xf2,0xff,0x4c,0x6f,0xf7,0xc7,0xae,0xa1,
+  0x8d,0x4c,0xf0,0x4f,0x2c,0xff,0xcf,0xad,0x69,0x56,0xc3,0xd3,0x99,0xf0,0x60,0xf7,
+  0x0f,0x99,0x9e,0xc7,0xff,0xa9,0x3d,0xe9,0xb7,0xf8,0xba,0xd3,0x09,0xff,0x38,0xfb,
+  0xdd,0xb0,0xb1,0x8f,0xcf,0x58,0x7c,0x4d,0x2f,0xd3,0x5d,0xbc,0x6d,0xc5,0x3b,0x16,
+  0xf9,0xd3,0x4d,0x96,0x1b,0xc4,0xef,0xfa,0x7f,0x9a,0x14,0x44,0x44,0xdb,0x0c,0xc4,
+  0xe7,0x3e,0xd7,0xff,0xf3,0xcd,0xd5,0xf6,0x7c,0xa3,0xaa,0x08,0xc4,0xd8,0x8e,0xaf,
+  0xbf,0x14,0xfa,0xa1,0x42,0x64,0x29,0x3f,0xc8,0x2e,0xfe,0xa1,0xd9,0xdd,0x00,0xd9,
+  0x6d,0xeb,0xa6,0x9c,0xfd,0x9d,0xf2,0xdf,0x05,0x11,0xe8,0x4d,0x17,0xcf,0x14,0x7c,
+  0x00,0xcf,0x85,0xe7,0xe8,0x81,0xa3,0xf2,0x07,0xda,0x2b,0x16,0xff,0xe7,0x7a,0xfe,
+  0x6b,0x27,0x11,0x9e,0xed,0x36,0x03,0xad,0xfe,0x76,0xd7,0xff,0xa3,0x9d,0x82,0x0d,
+  0x26,0x15,0xd9,0x60,0x27,0x01,0xcf,0x9b,0x19,0xff,0xa8,0x5c,0x05,0x3f,0xc8,0x06,
+  0xc2,0xb4,0x0d,0xbe,0xea,0x3e,0x15,0xf1,0x8f,0xb3,0xde,0xba,0x11,0xcf,0x24,0x9a,
+  0x56,0x18,0x2a,0xe0,0x34,0x93,0xd9,0x78,0x5f,0x9f,0x7b,0x30,0xd7,0xf5,0x7e,0x1f,
+  0xb0,0x15,0xa5,0x6e,0x3e,0xda,0x0f,0x61,0x43,0x77,0xf8,0xdd,0x50,0x8a,0xbd,0x45,
+  0xff,0x90,0x45,0x93,0xfe,0xb8,0xed,0x58,0xdb,0xa0,0xe3,0x51,0x25,0x95,0xf0,0xd6,
+  0x3f,0xfc,0x25,0xf4,0x19,0xb1,0x58,0xb4,0x53,0xfe,0x25,0x3f,0x61,0x52,0x7e,0x9c,
+  0xbf,0x46,0x7a,0x46,0x24,0xee,0x49,0xcf,0xea,0x3f,0x4d,0xd5,0xf5,0x95,0xd4,0x48,
+  0x86,0xb3,0x7f,0x65,0xa4,0x3d,0x9a,0x38,0x9f,0x0e,0xc9,0xa3,0xca,0x45,0xcb,0x1b,
+  0xd6,0xab,0x64,0xf5,0x73,0x8e,0x5f,0xe4,0x0d,0x66,0x91,0x99,0xe7,0xff,0x39,0x1b,
+  0x9f,0x77,0x47,0xf1,0x46,0xda,0xdf,0x07,0x1a,0xc4,0xfd,0xe1,0x65,0xa5,0xc1,0x24,
+  0x46,0xb4,0x7e,0xde,0xa8,0x43,0x68,0xda,0xd9,0xe6,0xe5,0xff,0x70,0xdc,0xa4,0x32,
+  0x91,0xee,0xa6,0xa3,0x14,0x2d,0x35,0xfd,0xa3,0x65,0x51,0x2b,0x91,0xff,0xb1,0xb2,
+  0x37,0x71,0x61,0x54,0x23,0xb4,0x93,0xbd,0xf5,0x0f,0x5b,0xf4,0x5d,0x66,0x4d,0xe4,
+  0x3a,0x60,0xfd,0x1d,0x59,0x18,0x5c,0xa3,0x59,0xf9,0x80,0x85,0xc7,0x8d,0xdd,0xf1,
+  0xed,0x66,0x44,0x63,0xfb,0x72,0xea,0x1f,0xee,0xd9,0x3c,0x2d,0x5a,0xf4,0x59,0x76,
+  0x22,0x8b,0x07,0xc2,0x65,0x16,0x1e,0xf8,0xc7,0xe9,0x3f,0x43,0x68,0x34,0x2d,0xa3,
+  0xbe,0xc8,0x06,0x3c,0xf5,0x7f,0x8a,0xe1,0xbd,0xd0,0xbc,0xd6,0x62,0x19,0x61,0x8f,
+  0xc0,0x3f,0xe9,0xf2,0x80,0xf6,0x3e,0xde,0x9f,0x18,0xd1,0xfc,0x3c,0xcc,0xed,0x0f,
+  0x48,0xf2,0xa6,0x1c,0xfe,0xcf,0x19,0xed,0xa6,0x81,0xda,0xd7,0x11,0x0d,0x5e,0xd6,
+  0x3e,0x6a,0x06,0xdf,0xc5,0xf5,0x63,0x15,0xce,0x6a,0xa6,0x85,0x74,0xad,0xf9,0x6f,
+  0xaf,0x37,0xb7,0xb9,0xfc,0x1f,0xfc,0x7d,0x7b,0x89,0xed,0x99,0xa8,0xa6,0x6a,0x0c,
+  0x8c,0xdc,0x6e,0x35,0x56,0xa2,0xe2,0x7c,0x79,0x47,0xea,0x32,0x34,0x9c,0xf8,0xe8,
+  0x7c,0xf9,0x6f,0xdd,0xf8,0x57,0xe9,0x16,0x4a,0x32,0xa5,0xec,0xd1,0x21,0xcb,0xfe,
+  0xfc,0x2f,0x16,0xb2,0xf1,0x8f,0x38,0x88,0x0d,0xa1,0x85,0x71,0xeb,0x1f,0xf6,0xc1,
+  0x01,0x9d,0x9b,0xd7,0xc5,0xd5,0x56,0x84,0x3d,0x87,0x3a,0xb6,0x66,0xfc,0x0b,0xd8,
+  0x55,0x16,0xf1,0xc9,0x62,0x80,0x7f,0x31,0xe3,0x1f,0xcb,0xa9,0x7f,0xf8,0x6c,0x92,
+  0xeb,0xe1,0x31,0xb5,0x86,0x1d,0x43,0x6d,0xd3,0xf9,0xeb,0x96,0x12,0x1b,0xff,0xf8,
+  0xe0,0xc0,0x72,0xc1,0xc8,0xf2,0xd6,0xff,0xe9,0x81,0xe7,0xf8,0x13,0xe9,0x1d,0x3b,
+  0xe4,0xb3,0xf1,0x4b,0xa9,0x3a,0x3e,0x29,0x25,0x2f,0xe0,0x2f,0x59,0xf8,0xe7,0xfb,
+  0x70,0x89,0x37,0x74,0x04,0x87,0x9f,0xfa,0xaa,0x87,0xff,0xf3,0x3a,0x13,0x7c,0x8c,
+  0x0e,0xf9,0x75,0x75,0x8c,0xce,0xe3,0x60,0x6f,0x4c,0x5d,0x22,0x31,0xaa,0x01,0x8a,
+  0xbb,0x3a,0xbd,0xf5,0x7f,0xde,0x80,0x9f,0x98,0xbb,0x56,0x45,0xd3,0xa9,0x61,0xf8,
+  0xc7,0x14,0xf9,0x7f,0xaa,0xb3,0xfc,0x9f,0x87,0xd8,0x3b,0x3a,0xf1,0x7f,0xd4,0xef,
+  0x54,0x7b,0xeb,0xff,0xfc,0x35,0xc7,0xd7,0x2a,0x8e,0xe7,0x8b,0x61,0x63,0x3f,0x27,
+  0xff,0xcf,0x35,0x35,0x4e,0x22,0x52,0x17,0x25,0x22,0xc1,0x26,0x96,0x93,0xff,0xae,
+  0x3c,0x04,0xcc,0x68,0xfd,0xe7,0xc2,0x61,0x7d,0xbf,0xe5,0x2f,0xb2,0xc7,0x27,0x86,
+  0x39,0x5d,0x61,0x39,0xfe,0x9f,0x96,0x1a,0xad,0x53,0xd7,0xb3,0xf1,0x20,0xae,0x13,
+  0xff,0x47,0xe1,0x6e,0x60,0x48,0xd7,0x29,0x35,0x2c,0xa7,0xfe,0x8f,0x36,0x24,0xd5,
+  0x55,0x04,0xd6,0xca,0x02,0xdd,0xc1,0xf3,0x6b,0xe5,0x2a,0x4f,0xe1,0xc7,0xb6,0x5d,
+  0x94,0xff,0xfe,0x8e,0x63,0x7f,0x7a,0xa6,0xbc,0x00,0x17,0x4b,0x9f,0x34,0x96,0x26,
+  0xe5,0x33,0xea,0x6f,0x2c,0xff,0x8f,0x5d,0x08,0x51,0xa3,0x54,0xf7,0x86,0x96,0x99,
+  0xa3,0xf2,0x29,0x27,0xff,0xb4,0xbb,0xe0,0x0c,0x3c,0xab,0xde,0x44,0x24,0xe7,0x33,
+  0xf0,0x4d,0xd4,0x06,0xfe,0xe1,0x1b,0x5c,0x8c,0x6f,0x43,0xfb,0x76,0xf1,0xba,0xba,
+  0xe5,0x81,0x41,0x69,0xb1,0x87,0xff,0x33,0x02,0xdd,0x46,0xb8,0xbb,0x9b,0x37,0x65,
+  0x58,0x37,0x6c,0x03,0x0a,0x7b,0xf1,0x2c,0x22,0x1a,0x81,0x7d,0x2d,0xdb,0xd4,0x08,
+  0x2f,0x2b,0x71,0xf4,0xa9,0x0a,0xfe,0xcf,0xaa,0xa6,0x88,0x96,0x40,0x41,0xc5,0xf9,
+  0x56,0x24,0x9e,0x76,0xe7,0xbb,0x55,0x8d,0xb4,0xa9,0x5a,0x59,0x53,0xa9,0xfd,0xfc,
+  0xc4,0x7f,0x5e,0x0f,0x2b,0x5a,0xd5,0x6f,0xb1,0x53,0x50,0x64,0x84,0x3d,0x78,0x32,
+  0x7d,0x15,0xfe,0x22,0xda,0x0c,0xa3,0x7b,0x57,0xb8,0xd0,0xb1,0x0f,0xdb,0x2a,0x8f,
+  0xb0,0xa3,0x08,0x5a,0x02,0x3d,0xf2,0x30,0xff,0x24,0xaf,0x13,0x78,0xc6,0xcc,0x22,
+  0x9c,0x5f,0x6a,0x67,0xe1,0xab,0x46,0x54,0x93,0x57,0x79,0xf2,0xb3,0xbe,0x07,0xef,
+  0xaa,0xe4,0xe4,0xb1,0xc2,0x5e,0xb4,0x1e,0x4e,0xd9,0x88,0xe8,0x1d,0x1c,0x3f,0x97,
+  0x34,0x70,0xd8,0xcb,0xff,0x21,0x23,0x5f,0x24,0xe2,0x8f,0x23,0xba,0x60,0x3b,0xdf,
+  0x69,0x03,0xa1,0x2a,0x18,0xd1,0x1a,0xa4,0x40,0x4e,0xfe,0x57,0xc1,0x8d,0xc6,0x21,
+  0x5e,0xcd,0x23,0x99,0xc4,0xcb,0x35,0xf7,0x75,0x87,0x11,0xf6,0x94,0x65,0xf9,0x3f,
+  0x6f,0xde,0x1b,0x69,0x3f,0x64,0x96,0xf0,0x81,0x37,0x72,0xea,0x1f,0x2e,0xd5,0x76,
+  0x1a,0xb5,0xf1,0xd6,0x05,0x4d,0xc7,0xf9,0xf7,0x0d,0x11,0x7d,0xc8,0x56,0x04,0x9a,
+  0xcb,0x3e,0x01,0x07,0x06,0x02,0x66,0xd1,0x5c,0x76,0xcc,0xb1,0x9f,0x5b,0x17,0x4d,
+  0xd6,0x77,0x1a,0xff,0x7e,0x58,0xc4,0xaf,0x1f,0xa1,0xf7,0x77,0x8d,0x1d,0x18,0x5a,
+  0xc5,0xee,0xa0,0xf7,0x77,0xa0,0x28,0x7e,0x95,0x6b,0x7f,0x7a,0xd5,0xa9,0xea,0x19,
+  0xde,0x18,0x0f,0x20,0xfe,0xd1,0xde,0xe1,0x3b,0x71,0x5b,0x69,0x76,0x10,0xd1,0xa7,
+  0x63,0x1f,0xf0,0xfa,0xb7,0x66,0xe6,0xd6,0x3f,0x4c,0x59,0xa7,0xfb,0x64,0xf9,0x71,
+  0x78,0x89,0xb6,0xf5,0x43,0x9d,0xef,0xd8,0x11,0x90,0xad,0x54,0x8f,0x74,0xb0,0x30,
+  0xe5,0xa9,0x7f,0x68,0x16,0xbc,0x6a,0x1c,0xa7,0x24,0x65,0x3c,0xbf,0x9b,0xcf,0x51,
+  0xfc,0x62,0xac,0xf3,0x90,0x2e,0xf0,0xcf,0x90,0xfc,0x01,0x7c,0x90,0x9c,0x73,0x32,
+  0xb0,0x0a,0xd1,0xb9,0xcb,0xff,0xd9,0x0c,0x6b,0xf5,0xaa,0x63,0x08,0x72,0x5e,0x69,
+  0xb9,0x9f,0xdc,0xce,0x0e,0x11,0x7a,0x11,0xfb,0xf9,0x12,0x4a,0x04,0x53,0xef,0x64,
+  0x2e,0xdf,0x4f,0x83,0x2d,0x65,0x5d,0xea,0x5f,0x0f,0x86,0xda,0xd8,0x2b,0x5d,0xeb,
+  0xac,0xf9,0x6e,0xd1,0xf7,0xc2,0x34,0xd3,0x1f,0x67,0x2f,0xc0,0x21,0xa6,0x9b,0x6a,
+  0xdc,0x07,0x39,0xf9,0xef,0x3c,0xbe,0x2d,0x83,0xfb,0xe3,0x51,0x3d,0x91,0xd2,0x29,
+  0x0c,0x54,0x6c,0xe9,0x13,0xf0,0x8d,0xdb,0x9d,0xc1,0xf1,0x91,0xa6,0x90,0xb3,0x3e,
+  0xc7,0x2a,0x7f,0x04,0xa6,0x39,0xaf,0x2d,0xba,0x45,0xfe,0x35,0x3c,0x33,0x50,0x47,
+  0xdb,0xd0,0x93,0x16,0xe3,0x22,0x2d,0x0f,0xc4,0xc7,0x32,0x73,0xcc,0xe8,0xbe,0xce,
+  0x19,0x1e,0xfe,0xcf,0x29,0x72,0xfb,0x0c,0x2e,0xfd,0x96,0x7c,0xda,0xc8,0x9e,0x37,
+  0xa9,0x30,0xcb,0xd7,0xc9,0xf1,0x3e,0x6c,0x39,0x82,0x52,0xcd,0x2e,0xfe,0x19,0xd4,
+  0x2e,0xe8,0x63,0xdb,0xe7,0xe0,0xa1,0xbe,0xf3,0xeb,0xca,0x73,0xb8,0x9b,0x13,0x10,
+  0xd2,0x9f,0x27,0x18,0x70,0x46,0x1e,0x85,0x7e,0xf2,0x08,0xf5,0xcb,0xdc,0x13,0xff,
+  0xfa,0xa2,0xbe,0xaf,0x2a,0x7c,0x92,0x75,0x87,0x4b,0x8c,0x04,0x45,0x73,0xd2,0x16,
+  0xff,0x96,0xf8,0xcf,0xaf,0x1b,0xbd,0x7c,0x9e,0x79,0x6b,0x20,0x17,0xff,0xf0,0x03,
+  0x08,0x03,0x5a,0x7b,0xb6,0xad,0xd6,0xd6,0xb7,0x65,0xc7,0x3b,0x85,0x10,0xbf,0xaf,
+  0xe1,0x95,0x54,0x59,0xca,0xc3,0x7f,0x56,0xb4,0x7d,0x8a,0xce,0x71,0xd3,0x8f,0x52,
+  0xf4,0x99,0xf2,0x73,0x03,0x76,0xe1,0xdf,0xd3,0x28,0x28,0xa6,0x5f,0x07,0x37,0xff,
+  0x9d,0x17,0xaf,0xd6,0xc8,0xed,0x13,0xe5,0xf2,0x6a,0x65,0x80,0xfc,0x3f,0xed,0xf8,
+  0x87,0xd9,0x42,0xbb,0x54,0xb1,0x04,0x9f,0x9f,0xcb,0x3c,0xa7,0xfe,0xe1,0x05,0x78,
+  0x92,0x07,0x4d,0x79,0x30,0xcb,0xff,0xf1,0x24,0x32,0xdb,0x44,0xa0,0x11,0x67,0xfd,
+  0x1c,0x96,0x70,0x10,0xbf,0x3e,0x55,0xf2,0xd9,0xe6,0x85,0x70,0x51,0x99,0x43,0x69,
+  0x83,0x54,0x51,0xf3,0x86,0x4c,0xf0,0x6c,0xf5,0x20,0xbc,0x92,0xb8,0x5e,0x2f,0x1e,
+  0x92,0x63,0x2e,0x5f,0x48,0x3b,0x4d,0x66,0xb6,0x55,0x4d,0x86,0x71,0xa3,0x8f,0xcc,
+  0xc8,0x64,0x13,0xe1,0x67,0x64,0xfc,0xbb,0xf0,0xa7,0xe9,0xe6,0x61,0x1d,0x4d,0xb7,
+  0xee,0xe6,0x7f,0xc1,0x46,0x69,0xb7,0x1a,0x7e,0xaa,0xbb,0x8e,0x05,0x38,0x5a,0x57,
+  0xaa,0xbe,0x7b,0x1c,0x0f,0xb6,0x8a,0x79,0x6d,0x1d,0xda,0x9f,0x24,0xd4,0x40,0x91,
+  0xc6,0xc2,0x92,0xbd,0x7e,0xcc,0xd2,0xd3,0x15,0xbb,0xc9,0xfe,0x1f,0x64,0x33,0x61,
+  0x3f,0x9f,0x61,0x27,0xc2,0x0b,0xc5,0x12,0xe3,0x71,0x7a,0xaa,0xa8,0x87,0xa5,0x9d,
+  0xf7,0x57,0xf0,0x73,0xb4,0xba,0xbb,0x03,0xbd,0xfe,0xa8,0x71,0x99,0x14,0x95,0x96,
+  0x4f,0xc1,0xbb,0xb8,0x7e,0xfc,0x69,0xf9,0x17,0x30,0xa4,0xcf,0x8b,0x7f,0xf3,0xbb,
+  0x7e,0x70,0xf8,0x3c,0x19,0x38,0xa8,0x5c,0xe4,0x4f,0x1a,0x54,0xfd,0x40,0x84,0x11,
+  0x51,0x2d,0x1f,0xb4,0x5e,0x4e,0x0a,0xe1,0x7d,0xe5,0x42,0xea,0x26,0x28,0x19,0xec,
+  0x6c,0x77,0xf3,0xdf,0x85,0xbf,0xb1,0xae,0xad,0x38,0x2d,0xcf,0x84,0x67,0x34,0x11,
+  0x6d,0x1c,0xb6,0xf1,0xf6,0x08,0x8c,0x2c,0x5b,0x80,0xf8,0xc7,0xef,0xf2,0x61,0x86,
+  0x24,0xca,0x07,0xd4,0x8d,0x82,0xb4,0x7f,0x35,0xdc,0xca,0xeb,0x05,0x0c,0x86,0x27,
+  0x98,0x28,0xa4,0xd0,0x04,0xdc,0xd4,0xb9,0xaa,0x35,0xbb,0xfc,0x9f,0x91,0x82,0x25,
+  0x7c,0x37,0xa4,0x8c,0xa2,0x34,0x5a,0x73,0x7f,0x46,0x84,0xbd,0xfa,0xed,0xfd,0xda,
+  0xc4,0xd3,0x42,0x64,0x3b,0x42,0x47,0x37,0xfe,0xf5,0x9e,0x34,0x55,0xda,0xcb,0xab,
+  0x57,0xee,0x3f,0x1b,0x9e,0x6a,0xc7,0xbf,0x7e,0xa6,0xee,0xe5,0xd7,0x09,0xc7,0x88,
+  0x8a,0x67,0xf1,0x54,0xeb,0x8b,0x9e,0x1a,0xe6,0x54,0xff,0xf0,0x3c,0x39,0x61,0x62,
+  0x8c,0xb3,0xa7,0xf4,0x18,0x39,0x4e,0xfb,0xe1,0x5d,0x2d,0x4a,0x8e,0xa0,0x7e,0x3c,
+  0x4c,0xcf,0x4f,0x06,0x40,0x3e,0x71,0x95,0xa3,0x4f,0xab,0xfe,0xb3,0x81,0xb0,0xf6,
+  0x37,0x06,0xf1,0xa3,0xfc,0xef,0xe2,0xfe,0x95,0x5d,0x3f,0x6b,0x60,0x0f,0x6b,0xe4,
+  0xc1,0xb6,0xe6,0xa1,0x42,0x7b,0xbe,0xd9,0xfa,0x3f,0x46,0x71,0xda,0x5f,0xa5,0x5d,
+  0x86,0x3c,0xfd,0x24,0x4c,0xa9,0x2e,0x53,0x9c,0x94,0x9b,0xf2,0xeb,0xff,0x18,0x59,
+  0xfe,0xb3,0xf0,0x27,0x3b,0x85,0x55,0x8f,0xeb,0x6b,0xa1,0x8a,0xab,0x6d,0xbe,0x32,
+  0xa7,0x9e,0xe1,0x22,0xf8,0x2e,0xae,0xe6,0xaa,0x15,0xea,0x18,0xbb,0x46,0x17,0x61,
+  0x3e,0x9c,0xaf,0xe3,0x11,0xd2,0x37,0xf2,0xaa,0xad,0x45,0xaf,0xb0,0x45,0x79,0xfe,
+  0x1f,0x7d,0x45,0x64,0x3e,0xfb,0xb8,0x7d,0xbe,0x40,0x7d,0x72,0x3a,0xcf,0x16,0x3e,
+  0xc3,0x13,0x47,0xf5,0x94,0x7a,0x55,0xd9,0x32,0x27,0x3e,0x68,0xf9,0x7f,0x66,0x27,
+  0x03,0x5f,0x2a,0x9f,0x61,0x9c,0x43,0x44,0x49,0xfe,0x1f,0xe9,0x1c,0x17,0xf8,0xe7,
+  0x6d,0x78,0x0e,0xe6,0xec,0x2b,0x1e,0x91,0xef,0x76,0xea,0xcf,0x58,0xfe,0x9f,0x43,
+  0x52,0x09,0xef,0xcc,0xa8,0x74,0xfa,0xb8,0x5f,0x14,0x82,0xd6,0x68,0x3f,0x2a,0x37,
+  0x61,0x4c,0x3b,0x14,0x1a,0x57,0xff,0xf9,0x28,0xec,0xa2,0xfc,0xa0,0xa8,0xd2,0x87,
+  0x40,0x31,0x98,0xfc,0x13,0xba,0x22,0xf6,0xbb,0x28,0x9c,0x4d,0x7e,0x95,0x42,0x63,
+  0x2c,0xa7,0xfe,0x61,0x87,0x11,0x26,0x27,0xc3,0x34,0x58,0x6f,0xcc,0xa3,0xfd,0xb7,
+  0x1f,0xc7,0x13,0x9e,0x59,0xb1,0x9d,0x75,0x18,0xf3,0x96,0xdf,0xaa,0x79,0xbc,0xf3,
+  0x21,0x45,0x81,0xf5,0x8b,0xc2,0x6d,0x37,0xd2,0xf8,0x87,0x8c,0x19,0x38,0xac,0x6c,
+  0x25,0x3c,0xe4,0xf8,0x7f,0x60,0x46,0x8b,0x6f,0x13,0x73,0xe8,0x15,0x10,0x00,0x2a,
+  0x13,0x1d,0x36,0xae,0xa6,0x6a,0xc6,0x0f,0xe8,0xdb,0x69,0xd8,0x30,0xb3,0x0b,0x41,
+  0x23,0xf4,0xaa,0xa1,0x88,0x8f,0xec,0xe4,0x63,0x8e,0xa9,0x77,0x1a,0x03,0x6d,0xb1,
+  0x8a,0x4f,0x22,0xec,0x69,0x1a,0x5c,0xb6,0x80,0xf2,0xfd,0xe3,0x94,0x76,0x4d,0xf1,
+  0xaf,0x38,0xaa,0x6e,0x06,0x94,0x70,0xff,0x3c,0x87,0xff,0xb3,0xf1,0xea,0x61,0x46,
+  0x6c,0x9f,0x92,0x76,0x79,0xd8,0xf8,0x95,0xd6,0x40,0x6c,0x16,0x2a,0x63,0x28,0xe6,
+  0xbb,0xa3,0xed,0x32,0x5c,0x67,0x4c,0x6a,0x93,0x7f,0xe1,0xd8,0xf3,0xee,0x02,0xd2,
+  0x46,0x5d,0x5b,0x60,0xb3,0x5c,0x93,0x7c,0x26,0x73,0x23,0x0d,0xdb,0xee,0xfa,0x8b,
+  0x9e,0xa6,0x5b,0x0d,0xfa,0x99,0x9b,0xff,0xae,0x9d,0xec,0xea,0x4e,0x6d,0xd3,0x23,
+  0xf7,0xfa,0xaa,0xd9,0xc6,0xc1,0x6d,0xe0,0x2d,0x84,0x58,0x65,0x10,0x23,0xfa,0x56,
+  0x5e,0x56,0xe8,0xf2,0x7f,0xf0,0x7c,0xb1,0x56,0xad,0x6a,0x55,0x97,0xb1,0xca,0xd4,
+  0x5a,0xc1,0xee,0x76,0xfd,0x3f,0xfd,0xa1,0xec,0xc4,0xaf,0x91,0xec,0xf9,0xf6,0x54,
+  0x76,0x01,0x2e,0xc2,0x36,0xb5,0x2d,0x5c,0x81,0xab,0x31,0x8b,0x7f,0x6e,0x14,0xfa,
+  0x0c,0xaf,0x26,0x46,0x74,0x5c,0x7e,0x80,0x7d,0xc9,0xa9,0x7f,0x95,0xaa,0x1c,0x66,
+  0x47,0x11,0xf6,0xd0,0xf3,0xe3,0x44,0x16,0x64,0xfd,0x39,0x49,0x2b,0x11,0xbe,0xe9,
+  0xa8,0xd9,0xd0,0x84,0x82,0x9b,0xff,0x2e,0xfc,0x3f,0x3a,0x7e,0xbb,0xb9,0x7a,0x98,
+  0x8f,0xcb,0xff,0xaa,0x39,0x6b,0x0a,0x46,0xf4,0x26,0x0f,0xfe,0xb1,0xe2,0x5f,0x01,
+  0x72,0xfb,0x1c,0xb7,0x04,0x5a,0x81,0x5f,0x27,0xfc,0xb3,0x08,0x46,0x06,0xeb,0x62,
+  0xc5,0x1d,0x72,0x22,0x87,0xff,0x4c,0xd9,0xee,0xd9,0xf8,0x57,0x75,0x87,0xea,0x49,
+  0x84,0xbf,0x49,0xbb,0x0f,0xed,0xc3,0x86,0x55,0xe5,0x4d,0xce,0x7a,0x88,0x74,0x05,
+  0xa8,0x5e,0x56,0xc6,0x47,0x69,0x14,0x9b,0xb8,0xce,0xbd,0xc4,0xb9,0x4f,0x69,0x0f,
+  0x73,0xbd,0xff,0xea,0x48,0x5d,0xc2,0xb1,0x3f,0x55,0x80,0xa7,0x15,0xa3,0x6a,0xd0,
+  0xf7,0x15,0x36,0x05,0xfe,0xd9,0xa8,0x4a,0xd9,0x44,0xbe,0x3e,0x3a,0xbf,0xd0,0xfb,
+  0x48,0x2f,0x72,0xab,0xe1,0xdc,0xbf,0x7b,0xaa,0x76,0x89,0xef,0x4e,0xd5,0x8e,0xe0,
+  0xc1,0xe5,0x35,0xbe,0x33,0x15,0xb5,0x1c,0x41,0x33,0xe9,0x7c,0x7d,0x1b,0xbc,0xd1,
+  0x75,0x97,0x5e,0xbc,0x4a,0xde,0xe0,0x2c,0x68,0x75,0x72,0xaf,0xf0,0xbe,0x16,0x93,
+  0x1b,0xf6,0x6d,0x3a,0x86,0x38,0xfe,0x8d,0xbd,0xf2,0x69,0x8d,0x18,0x79,0x68,0xb8,
+  0xdc,0x78,0x9f,0x29,0xea,0x3f,0xcf,0x21,0xfc,0x33,0x0f,0x2e,0xf0,0x39,0x16,0x91,
+  0xf5,0x79,0x72,0x04,0x5d,0x90,0xeb,0xd8,0xb3,0x5d,0x73,0xaa,0x4a,0xc6,0xe4,0x41,
+  0xc7,0x9e,0xec,0x28,0xed,0x31,0x1e,0x83,0x6a,0x2a,0x32,0x56,0x41,0xde,0x1e,0x2e,
+  0x1c,0x41,0xdf,0x13,0xfe,0x1c,0x79,0x39,0xac,0xd5,0xaa,0xba,0x10,0x11,0xbd,0xe5,
+  0xec,0x17,0x3d,0x7c,0x0b,0x1c,0x54,0xc9,0x29,0x84,0x5b,0xec,0x63,0x5c,0x8c,0xbf,
+  0x60,0x17,0xae,0x87,0x38,0x2e,0x15,0xcd,0xf7,0x95,0x44,0xca,0xd1,0xff,0xca,0x8a,
+  0x01,0x0a,0xeb,0x84,0x01,0x98,0x4c,0xd9,0x85,0xdc,0x2e,0x6c,0xd2,0x87,0xf6,0xff,
+  0x93,0x5a,0x87,0xa6,0x4f,0xc3,0xf3,0xd7,0xa0,0x07,0xff,0xec,0xa0,0xfa,0x3f,0x27,
+  0x03,0x31,0xff,0x4c,0x9c,0xf8,0x2e,0x6b,0xbe,0xb8,0xbf,0x53,0x85,0x96,0x59,0x70,
+  0xd4,0xac,0x33,0x4b,0x0e,0xca,0x2e,0x1f,0x89,0x03,0xf1,0xc3,0x0f,0xa1,0x75,0xad,
+  0x3e,0x6e,0x9c,0x73,0xf4,0xc3,0x85,0xbd,0x7d,0x56,0x3f,0xab,0x0b,0x06,0x82,0x5b,
+  0x7f,0xb8,0x4f,0xa3,0x7a,0x77,0x8d,0x7c,0x49,0xa6,0x73,0xbe,0xfe,0x14,0xcc,0xe1,
+  0x5e,0x3c,0x50,0x0f,0xcf,0xf6,0xcf,0x21,0xaa,0xb0,0xe9,0xec,0x77,0x7d,0x5d,0xf3,
+  0xe1,0x10,0xcc,0x44,0xfc,0xdc,0x34,0x1f,0x7e,0x04,0x33,0x72,0x0a,0x11,0xff,0x07,
+  0x21,0x96,0x94,0x4a,0xfc,0x67,0xfb,0xf7,0x42,0xfc,0x23,0xaa,0x83,0x16,0xe1,0xb1,
+  0x4b,0xc1,0xdd,0x39,0x67,0x7c,0x0d,0xac,0x57,0xc3,0xba,0x6f,0x5f,0x22,0xe3,0xe4,
+  0x53,0xa8,0x8a,0x2a,0xe2,0xef,0x7e,0xb4,0x3f,0x90,0x72,0x88,0xaf,0x2c,0x4b,0xfc,
+  0x58,0x4f,0x4b,0x37,0xc6,0xdc,0xfa,0x1b,0x88,0x7f,0x44,0x91,0xd5,0x62,0xc0,0xf5,
+  0x7f,0x14,0xe6,0x79,0xd6,0x43,0x3b,0xa3,0x37,0xae,0x8e,0x4a,0x25,0x98,0x2e,0xfe,
+  0xf9,0xd7,0x31,0x38,0x03,0x8d,0x10,0x30,0xe5,0x51,0xf5,0x22,0xdc,0x44,0xf3,0x7d,
+  0xc5,0xf6,0x77,0x5d,0x40,0xd3,0xf4,0x64,0x47,0xc9,0xa8,0x9c,0x71,0xf1,0x8c,0x74,
+  0x0e,0x2e,0xf3,0x1b,0xe2,0x1b,0x96,0xcb,0x75,0xda,0xf3,0x75,0x73,0x86,0x03,0x19,
+  0x7f,0x8c,0xf8,0xf3,0x94,0x1f,0x77,0x0e,0x0f,0xfe,0xbb,0xe3,0x4b,0xc6,0x3c,0xfc,
+  0x1f,0x13,0xde,0x81,0x1b,0xf9,0x36,0x22,0x01,0xce,0x80,0xfb,0x5b,0x22,0xa6,0x2f,
+  0xdd,0x54,0x65,0x6c,0xe0,0xb3,0x32,0x88,0x37,0xbe,0x4f,0x1e,0x9b,0xb8,0x6f,0x9f,
+  0x87,0xff,0x33,0x20,0xf8,0xcf,0xc2,0xec,0xe8,0xf0,0x70,0x0c,0xd1,0x2f,0x2f,0xec,
+  0x2a,0xcb,0xfa,0x7f,0x46,0x60,0x83,0x16,0x01,0x9c,0xaf,0x87,0xff,0x53,0xfa,0x08,
+  0x3c,0x11,0x5f,0x61,0x6c,0xd8,0x52,0x16,0x09,0xff,0x00,0xe8,0xfe,0x6c,0x87,0x5d,
+  0x58,0x1b,0xef,0x0f,0x33,0xe2,0xf7,0xa6,0x57,0x8c,0x3a,0xef,0xaf,0x51,0xf1,0x23,
+  0x38,0x6f,0xe2,0xb1,0x6b,0xfe,0xc7,0x75,0xc1,0xff,0x89,0xfe,0x07,0x5a,0x83,0x2c,
+  0x3e,0x3c,0xa6,0x1f,0x63,0xf3,0xf5,0x8d,0xa8,0x1f,0xb7,0xfe,0x21,0x88,0xfd,0x7d,
+  0xe4,0x13,0x84,0x06,0x2d,0x7e,0xaf,0xbf,0xdd,0x5e,0x0f,0xfb,0xe0,0x92,0x71,0x83,
+  0x11,0xcc,0xeb,0x7f,0xa1,0xbe,0x4c,0x7c,0xc5,0x9d,0xfe,0x2a,0xe5,0x6d,0x86,0xab,
+  0x71,0x3b,0x1a,0x3a,0xab,0x10,0x50,0x67,0xaf,0xf1,0x16,0x34,0xe8,0xc1,0x74,0xf3,
+  0x4f,0xdc,0xfd,0x5d,0x89,0xc2,0x6e,0xa3,0x76,0xd0,0xff,0x18,0x93,0xe3,0xaf,0x21,
+  0x0c,0x53,0xe7,0xb0,0x28,0xdf,0x00,0xb3,0xe8,0xf9,0x67,0x40,0x02,0x4a,0x6a,0x4a,
+  0xf6,0xb1,0x0f,0xf2,0xe3,0x5f,0xad,0xa8,0x0d,0x40,0x98,0xad,0xf7,0xf9,0xe6,0xfa,
+  0x5a,0x6d,0x3c,0xec,0xc3,0x57,0xa9,0x86,0xfb,0x6e,0xf2,0xe0,0x9f,0x77,0x29,0xfe,
+  0x65,0xce,0x8c,0xff,0x3f,0x88,0x07,0xe0,0xc1,0xd4,0x34,0xdc,0x84,0xd9,0xa7,0x6d,
+  0x20,0x74,0x0d,0x6c,0xe6,0x33,0x6b,0x7c,0x6b,0xd8,0x05,0x27,0xfe,0xde,0x8a,0x2b,
+  0xe7,0x7d,0xb5,0x9e,0x60,0x0f,0x68,0xbf,0x80,0x18,0xb9,0x7d,0x56,0xe1,0xfd,0xeb,
+  0xcd,0xe0,0x6e,0x59,0x35,0x46,0x6f,0xaf,0x87,0xa9,0xb3,0xbd,0xfc,0x9f,0x29,0x7b,
+  0x04,0x6c,0x9e,0x34,0x2a,0xbf,0x68,0x5c,0x8e,0x34,0x5a,0xf9,0x02,0xa8,0x9f,0x13,
+  0xc1,0x77,0xfd,0x43,0xa5,0xa7,0x71,0x3f,0xfa,0xf3,0x77,0x65,0x4f,0x3d,0x8d,0x82,
+  0x53,0xf0,0x4c,0x1c,0xcf,0xb3,0xf3,0x65,0xe0,0xff,0x8f,0xf0,0x86,0xc9,0x11,0x10,
+  0xf9,0x5f,0x69,0x91,0x51,0x5e,0x9f,0x42,0xe8,0xe8,0xcd,0x7f,0xdf,0x0c,0x93,0xd4,
+  0x99,0xb8,0x3f,0xb2,0x10,0x74,0x6a,0x37,0x98,0xbe,0x76,0xb6,0x07,0xed,0x49,0x74,
+  0x00,0x0d,0xe9,0x20,0x9d,0x1f,0xa1,0xa4,0x3d,0xfc,0x9e,0x1b,0x0f,0xc2,0x4b,0xd6,
+  0xec,0x7c,0x57,0x55,0x11,0xed,0x47,0x9d,0x8f,0xd3,0xa4,0x42,0x88,0xea,0x9a,0x15,
+  0x2f,0x91,0x07,0x8c,0x0a,0x41,0x7b,0xf3,0xdf,0x9f,0x86,0x4e,0x33,0xda,0xff,0xe7,
+  0x35,0x8c,0x75,0x74,0xc2,0x74,0x5a,0x3f,0x1b,0xad,0xfc,0x82,0x34,0xfb,0x31,0xec,
+  0xba,0x85,0x4a,0x73,0x34,0x79,0xf3,0xdf,0xf7,0x19,0xc7,0x86,0x1a,0x52,0xc1,0xd7,
+  0x65,0x1f,0x9e,0x37,0x77,0x71,0x3c,0x28,0xcd,0xd7,0xde,0xb2,0xf2,0xdf,0xc7,0xba,
+  0x2e,0x99,0x8d,0x1d,0xf7,0xeb,0xd5,0xe7,0xbd,0xf5,0x0f,0x9b,0xf2,0x69,0xcf,0xaf,
+  0x5b,0xf9,0xef,0x5d,0x94,0xff,0xa5,0x11,0x35,0x57,0xce,0x89,0x7f,0xc1,0x79,0x4a,
+  0xfb,0xda,0x2c,0x9f,0xee,0x7a,0x1d,0x81,0x62,0x49,0x8f,0xac,0x50,0xd9,0x28,0xba,
+  0x22,0x1c,0x41,0xb8,0x3f,0x36,0x77,0xe6,0xc6,0xbf,0xcc,0xda,0xe5,0xfe,0x2d,0xe1,
+  0x53,0x2a,0xbe,0xef,0x86,0xfa,0x80,0x6f,0x9a,0x21,0x88,0x28,0xff,0x1c,0x9e,0x6e,
+  0x39,0x22,0xbe,0x83,0xaf,0x92,0xe3,0xff,0x01,0x51,0xff,0xa7,0xf5,0x5a,0x2b,0x5f,
+  0x3b,0x6c,0xf8,0xd2,0xbe,0x99,0xda,0x43,0x96,0x85,0xd9,0xce,0x45,0x69,0xe8,0x4d,
+  0x5e,0xff,0x0f,0x28,0x54,0xe6,0xce,0xb8,0x96,0x60,0x61,0x87,0x5e,0x63,0x13,0x81,
+  0x70,0x05,0x6a,0x85,0x5d,0x14,0x11,0xbb,0x53,0xd6,0xd8,0x2d,0x2e,0xff,0x47,0x75,
+  0xe2,0x5f,0x23,0xca,0x48,0xdb,0xae,0x8a,0xfb,0xc8,0xff,0x93,0xc5,0x3f,0x29,0x2d,
+  0xfb,0x95,0xcb,0xff,0xe9,0xb9,0xfa,0x05,0x38,0xab,0x88,0x24,0x2f,0x7c,0x1e,0x8a,
+  0x7f,0xfd,0xc4,0x2f,0xfc,0x3f,0x2d,0x4b,0x93,0x8b,0xbe,0x02,0x54,0x08,0x28,0x98,
+  0xac,0xde,0xe6,0xe8,0xb3,0x5b,0xf4,0xbf,0x68,0xa0,0xf3,0xc8,0x19,0x38,0xaa,0x2e,
+  0x68,0x53,0x06,0xfd,0x73,0xa9,0x10,0xe2,0x2d,0x81,0x9f,0xe0,0x95,0xb3,0x30,0xc7,
+  0xa0,0xfa,0x87,0x8e,0xfd,0xa1,0xf8,0xd7,0x48,0x36,0xdb,0x8b,0x75,0x2b,0xe4,0x88,
+  0xde,0x14,0xa1,0xfa,0xcf,0xa0,0x26,0x44,0x45,0x44,0x51,0x08,0xe8,0x39,0x07,0x9f,
+  0x8b,0xf8,0x17,0xaf,0x35,0x3e,0xa9,0x15,0xf6,0x4b,0x1d,0xbe,0x88,0xd1,0x5a,0x5a,
+  0xd2,0xa5,0x13,0xfe,0x29,0x12,0x85,0xaf,0x2b,0xc2,0xf8,0x15,0xf3,0xf0,0x7f,0x2a,
+  0x1f,0x89,0x3d,0x1a,0xae,0x35,0xd5,0x24,0x9c,0x36,0xd6,0x8b,0xb2,0x3f,0x25,0xdb,
+  0x0d,0xc2,0x3f,0xd7,0x25,0x57,0x50,0x21,0xa0,0x6d,0x14,0x2f,0x3b,0xe5,0xd6,0x57,
+  0xa9,0xf8,0xf7,0xc9,0x2f,0x76,0xd5,0xff,0x55,0xf1,0xe6,0xcf,0x0f,0x73,0xc2,0x3f,
+  0xd1,0xa4,0xff,0x11,0xed,0x1f,0x45,0x46,0x64,0x35,0xa5,0xfe,0xc5,0x5a,0x11,0xff,
+  0xf7,0x3a,0xf3,0x25,0xfc,0x73,0x1d,0x6f,0x38,0x19,0x4c,0x2e,0x72,0xcb,0x20,0x88,
+  0x7a,0x98,0x25,0x94,0xda,0xfc,0x6e,0xc1,0xd4,0x56,0x44,0x8c,0xde,0xf8,0x17,0xf9,
+  0x7f,0x1a,0x24,0x51,0x76,0x72,0x44,0x10,0x81,0xaa,0xf5,0xec,0x2f,0xd2,0x99,0xd1,
+  0x46,0x60,0x57,0x2c,0x2f,0xff,0x3d,0x42,0x24,0x9f,0x7d,0xfe,0xe1,0xc4,0xf2,0x8a,
+  0x7b,0xa5,0x70,0x87,0x9a,0x81,0x05,0x5c,0xe0,0x1f,0xaa,0xff,0x7c,0x0e,0xaa,0xbb,
+  0xfd,0xbf,0xf0,0xd6,0x3f,0x5c,0xbb,0x84,0xa2,0x0f,0xe0,0x9f,0xd1,0xb4,0xd8,0x7c,
+  0x82,0x85,0xfb,0x7c,0x8f,0x25,0x6e,0xeb,0x11,0xc4,0x5d,0x9d,0x1d,0x31,0x84,0xe9,
+  0xa6,0xfe,0x17,0x0e,0xfe,0x91,0x26,0xc3,0xe3,0xbe,0x99,0xdc,0x1f,0x67,0xcb,0xd5,
+  0x07,0xf5,0xaa,0x7e,0xd0,0x99,0x87,0x48,0xbc,0x9b,0xe2,0xd7,0x6d,0x65,0x9e,0xfa,
+  0x87,0xea,0x54,0xed,0x0c,0x5f,0x58,0x13,0x5c,0x45,0xb4,0x9f,0xd4,0xee,0x0c,0x5b,
+  0xe3,0xff,0x73,0x27,0x22,0x16,0xfa,0x65,0xc7,0x5d,0xf1,0xe0,0xf2,0xf1,0xf5,0x0f,
+  0x7b,0x82,0xa9,0xe6,0xe3,0xda,0xdb,0xbc,0xe1,0x44,0x30,0x55,0x8e,0x3b,0x3e,0x05,
+  0x7a,0x32,0xf2,0x69,0xe5,0x6d,0xf8,0xba,0x14,0x4c,0x96,0x1f,0xee,0xb2,0xf5,0x43,
+  0xf5,0x0f,0x7f,0x9b,0x2c,0xaf,0x81,0xbf,0x91,0xa7,0xc2,0xf3,0x1b,0xf1,0xfc,0x7e,
+  0xb6,0xfc,0xab,0x6d,0xbf,0x26,0xfe,0xcf,0x59,0xf9,0x55,0xe9,0xb5,0xe4,0x1c,0x3d,
+  0x78,0xd4,0x63,0xaf,0x76,0x94,0x6e,0x31,0xe6,0x85,0xa4,0x2e,0xf5,0x4e,0x16,0x62,
+  0xf7,0xe0,0xf9,0xcb,0xf7,0x0f,0x85,0x3d,0x16,0x9e,0xb9,0x8b,0xbd,0x22,0xdd,0x13,
+  0xab,0x52,0xfc,0x06,0x7b,0xcb,0xa9,0xb7,0x93,0x84,0x2d,0xca,0x66,0xa9,0x8a,0xb7,
+  0xde,0x89,0xe8,0xae,0x93,0xca,0x94,0xb5,0x17,0x9a,0x55,0xdf,0x13,0x15,0xa4,0xd9,
+  0x85,0xf8,0x3d,0x0a,0xc5,0xeb,0x9b,0x8e,0x38,0xf8,0x6a,0x75,0xc5,0x73,0x84,0x7f,
+  0x52,0xaa,0xce,0x8a,0xd4,0x0d,0x44,0xac,0x9a,0xcb,0x9e,0x01,0x3b,0xde,0x51,0xd2,
+  0x09,0x7a,0xcc,0x0f,0x6c,0xc8,0xc1,0xe7,0x54,0xff,0xe7,0x25,0x5e,0x57,0x84,0xe7,
+  0xa3,0x69,0xb4,0xdb,0x9a,0x81,0x83,0xf2,0xaf,0xed,0x42,0x73,0xbf,0xa2,0xfe,0x17,
+  0x03,0xf8,0xfb,0xba,0xf5,0x22,0x70,0x59,0xc6,0xcf,0xc5,0x1b,0x4a,0x67,0x6d,0xc6,
+  0x4d,0xfc,0xbc,0x82,0xc3,0x0e,0x48,0x3b,0xf8,0x79,0x87,0x78,0x89,0xf6,0x64,0xe9,
+  0x66,0x7c,0xf5,0xec,0xf9,0x76,0x68,0x17,0x34,0xb4,0xe7,0xb1,0x60,0x26,0x71,0x66,
+  0x3a,0xc5,0xbf,0xd0,0xfe,0x2f,0xe0,0x16,0x23,0x9a,0x5d,0x4a,0xbd,0x0d,0x8d,0x83,
+  0x88,0x7f,0xdc,0xfc,0x44,0xb3,0x6b,0x35,0x1c,0xe8,0xaf,0x6d,0x97,0xd7,0xb2,0xc3,
+  0x6c,0x83,0x14,0x36,0x5b,0x0f,0xb2,0x88,0xcd,0x88,0x7e,0x47,0x42,0xa1,0x0a,0x85,
+  0x11,0x6f,0xfd,0x67,0xf5,0x80,0x89,0xa7,0x8f,0x64,0xe2,0x94,0xf0,0xb7,0x6f,0xe8,
+  0x29,0xcc,0x8e,0xdf,0xc1,0x4e,0xab,0x4f,0xd0,0x79,0x64,0xe3,0xf4,0x8c,0x53,0x0f,
+  0x9c,0xe2,0x5f,0x69,0x5a,0x6f,0xc0,0x4c,0x54,0x8b,0xde,0xd7,0x1d,0x0b,0xab,0xb8,
+  0x6c,0x56,0x3b,0x44,0x05,0xfc,0x6a,0xb1,0x37,0xff,0x7d,0xb5,0xc5,0x46,0xe0,0xe5,
+  0xc3,0xea,0x79,0x98,0x6d,0xde,0x96,0xf6,0x47,0x5c,0x46,0xf4,0xdb,0xf4,0x06,0xa1,
+  0x29,0xee,0xf4,0xc6,0xbf,0x2e,0xc0,0x42,0x08,0x9a,0xd5,0xa3,0xe3,0xdc,0x3e,0x56,
+  0xfd,0x1f,0xfc,0x6a,0xa4,0x26,0x37,0xff,0x6b,0x56,0x3c,0x60,0x96,0xff,0xbd,0xfa,
+  0xbc,0x1d,0xf6,0xfa,0x39,0x0a,0x25,0x24,0x5c,0x80,0x39,0xf1,0xe2,0x8c,0xec,0xc6,
+  0xbf,0xcc,0xe4,0x3b,0x2a,0xb1,0x7d,0x22,0x1c,0x77,0xf3,0x6c,0xff,0xaf,0xe3,0xb0,
+  0x9e,0xd7,0x9a,0xb8,0xad,0x9f,0xd6,0xf6,0x51,0xe9,0xe6,0x1e,0xb4,0xcf,0x2e,0xfe,
+  0x11,0xd1,0x4f,0xc3,0xa7,0x35,0x19,0x62,0x19,0xf8,0x3c,0x7c,0xef,0xe3,0x90,0xc2,
+  0xf1,0xeb,0xf5,0xf0,0xdf,0xba,0xf9,0x5f,0x95,0xa7,0xa9,0x7e,0x0e,0xde,0xc4,0xe7,
+  0x71,0xa3,0x75,0xf3,0xac,0x40,0xf5,0x6f,0xd5,0x0e,0x4f,0xff,0x2f,0x0d,0xc7,0x9f,
+  0x97,0xea,0xbb,0xa3,0xdd,0xb2,0xc1,0xec,0xfe,0x53,0xd2,0x8b,0x3c,0x1b,0x18,0x7d,
+  0x93,0xa7,0xee,0x2e,0x8e,0xca,0x86,0x9b,0xff,0x25,0x51,0x7e,0x13,0x6a,0x23,0xe5,
+  0x7f,0xd7,0xa1,0xfd,0x28,0x97,0x6d,0x7e,0xf8,0x6f,0xa4,0x27,0x8d,0xa5,0x19,0x39,
+  0x3f,0xff,0xab,0x01,0x02,0x0f,0x88,0xb0,0x8e,0x1d,0x6f,0xe5,0x75,0x56,0x45,0xc4,
+  0x81,0x58,0x43,0xeb,0x6d,0xa9,0xa0,0x87,0xff,0x63,0xc5,0x43,0x5b,0xd5,0x07,0xd8,
+  0xa3,0x86,0xc3,0x87,0xbf,0xd7,0x0c,0x0f,0x0a,0x61,0x3d,0x95,0x06,0xea,0x95,0xef,
+  0xb6,0x7f,0x5e,0x1b,0xff,0xd4,0x5d,0x97,0xf6,0x49,0x90,0x2d,0xdc,0x77,0x5a,0x7a,
+  0x18,0x74,0x11,0x91,0x67,0x1d,0x66,0x4d,0xbb,0x2f,0x72,0x38,0xe6,0x8c,0x1f,0x15,
+  0xf5,0x9f,0x67,0x6e,0x57,0xff,0x86,0x7d,0xc7,0x71,0x83,0x28,0xf7,0xf7,0x57,0xa1,
+  0x50,0xf8,0xaa,0xb4,0x96,0xcf,0x5a,0x1d,0x09,0xb1,0x56,0xcd,0xc3,0xff,0x21,0xb6,
+  0x0f,0x04,0xae,0x97,0xc1,0xad,0xff,0xf3,0x65,0x5c,0xa8,0xc1,0x58,0xf3,0x69,0x78,
+  0x0a,0xea,0x5b,0x4b,0xa6,0x25,0xae,0x71,0x1c,0x04,0x96,0xff,0x67,0x61,0x69,0xf0,
+  0xdd,0x66,0xab,0xff,0xd7,0x47,0x49,0x2d,0x1f,0x48,0xb6,0x23,0x51,0x5b,0xd8,0x1a,
+  0x1c,0x9d,0x34,0x38,0xc9,0xd6,0x3f,0xf9,0x7f,0x10,0x1f,0xf6,0xe0,0xfb,0xcb,0x3c,
+  0xfd,0xbf,0x3a,0xe6,0x65,0xf9,0x78,0xb8,0x83,0x07,0xa8,0x3e,0x6d,0x1e,0xff,0x87,
+  0xab,0x99,0xf2,0xe5,0xde,0xfe,0x5f,0xe2,0xd8,0xf8,0x8a,0xf2,0x18,0xcc,0x06,0xb5,
+  0x7d,0x9b,0x6b,0xff,0x0d,0x98,0xaa,0xe1,0x34,0xc3,0xea,0x1a,0x56,0x27,0x7d,0xcf,
+  0xf2,0xff,0x10,0xff,0x67,0x5a,0xa6,0xc8,0x12,0xfe,0x7d,0x85,0xda,0x8a,0xaf,0x92,
+  0xfd,0xc9,0xf2,0x7f,0x22,0x91,0x34,0xbb,0xd5,0x31,0x3b,0xb0,0xab,0x4b,0xb7,0xfc,
+  0xab,0xbb,0x75,0xbd,0x0d,0xf1,0xf6,0x4b,0x39,0xfd,0x2f,0x5e,0x82,0xfa,0x64,0x20,
+  0xb3,0x61,0xc1,0xe1,0x63,0xd0,0xd0,0x61,0xe5,0x7f,0xa5,0xe6,0xf1,0x7b,0x52,0xe5,
+  0x23,0x1a,0xe2,0xe1,0xf4,0xea,0xde,0x4e,0x6f,0xfe,0x97,0x0d,0x7b,0xfc,0x96,0xb0,
+  0x34,0x9f,0x08,0x54,0x46,0xfc,0x67,0x97,0x8f,0x6a,0xd5,0xff,0xc9,0x44,0xbf,0xe3,
+  0xf7,0x10,0x3f,0xfe,0xd1,0xaa,0xe7,0x3f,0xcc,0xfa,0xb6,0x96,0xb5,0x07,0xbc,0xf8,
+  0x10,0xf1,0x8f,0x46,0xdd,0x2e,0xf0,0x25,0xaa,0xe1,0x36,0x9f,0x47,0x41,0x44,0xd4,
+  0x4a,0x19,0x49,0x4a,0x91,0xb9,0x2d,0x5e,0xfc,0x40,0x22,0xe3,0xcc,0x37,0x54,0x40,
+  0x45,0x69,0x6a,0x5b,0x7c,0x49,0xb4,0x1c,0xd6,0xf8,0x32,0x1c,0xaf,0xe1,0x1b,0x97,
+  0x5c,0x8c,0x08,0x44,0xed,0x6d,0x6a,0xa5,0xfa,0xcf,0xf6,0x47,0x6d,0xb1,0xea,0xff,
+  0xdc,0x52,0xc6,0x10,0xed,0x30,0x0f,0x1f,0x46,0x64,0x84,0x75,0xe8,0xbd,0x04,0x0c,
+  0xdc,0xf8,0x97,0xcd,0xff,0x29,0x59,0xeb,0xb7,0x88,0xdf,0x93,0xa8,0xfe,0xe1,0x01,
+  0x68,0xa8,0x60,0x28,0xb4,0x0e,0xb0,0x05,0x15,0x01,0x2e,0xbf,0xe3,0xac,0x9f,0x6e,
+  0xc1,0xff,0xa9,0x37,0x8a,0x7f,0x22,0x7f,0xc5,0x9b,0xff,0x65,0x09,0xca,0x6f,0xb4,
+  0xc7,0xcc,0x49,0x0f,0xc8,0xef,0xe4,0xf4,0xff,0x7a,0x11,0x44,0x91,0x1f,0xcf,0x78,
+  0x87,0xff,0x7c,0x11,0xae,0x6f,0x09,0x6c,0x92,0x7d,0x5e,0xfc,0xa3,0x8c,0x09,0xfc,
+  0xe3,0x8f,0x7b,0xf3,0xbf,0x28,0xed,0x0b,0x32,0x9a,0xd5,0xff,0x82,0x79,0xfd,0x3f,
+  0xfd,0x76,0xbd,0xa3,0x23,0x42,0xa0,0xfe,0x5f,0xa9,0xfd,0x50,0x73,0x8b,0x35,0x71,
+  0xad,0xc6,0x08,0x95,0x16,0xba,0xfe,0xc6,0x9e,0xca,0xed,0xca,0xa3,0x12,0xd9,0x1f,
+  0x58,0xe9,0xe1,0x53,0xa9,0x76,0x20,0x4c,0xb4,0x3e,0x4c,0x14,0x7a,0xeb,0x1f,0x2a,
+  0x0f,0x49,0x73,0x57,0x06,0xfe,0xb9,0x68,0xa5,0xfb,0xfc,0xef,0x1e,0xfe,0xb4,0x25,
+  0xec,0x57,0xe7,0x7d,0x25,0x90,0xf4,0x47,0x9c,0xfa,0x78,0x84,0x7f,0x6e,0x14,0xc3,
+  0xaa,0x7f,0xe9,0x21,0x02,0xe1,0xb1,0xdd,0x2f,0xfe,0x10,0x1a,0xe2,0x7f,0x97,0xee,
+  0x74,0xf1,0xb9,0x9d,0xff,0x35,0xb3,0x4b,0x76,0x1b,0x61,0x28,0x63,0x37,0x53,0x45,
+  0xc4,0xea,0x38,0x0c,0xc4,0xeb,0xb4,0x12,0x90,0xef,0xed,0xb2,0xf5,0x9f,0xe5,0xff,
+  0xf4,0xa8,0x19,0xdf,0x7e,0x82,0x3d,0x1d,0xfe,0x2c,0xed,0x39,0x4d,0x82,0x76,0x9f,
+  0x51,0xb5,0xb9,0x3b,0xe5,0xd2,0xfd,0x04,0xff,0x07,0xad,0x71,0x6f,0xd1,0x5e,0xdf,
+  0xf1,0x6e,0x37,0xff,0x6b,0x20,0x9a,0x16,0xf6,0x67,0x13,0xd7,0x93,0xfe,0x9a,0xc2,
+  0xc3,0xf9,0xfc,0x1f,0x3c,0xb4,0xfa,0xb6,0x88,0xb6,0x5f,0xd4,0xff,0x8b,0xef,0x55,
+  0x8b,0x29,0x0d,0xea,0x55,0x50,0xd4,0x2a,0xf8,0x64,0x5b,0x59,0xab,0x9b,0xff,0xde,
+  0xfd,0x39,0x4a,0x7b,0xd7,0x8b,0xd7,0xf8,0xbf,0x9b,0x85,0x3d,0xd2,0x6b,0xfc,0xb7,
+  0x7c,0xca,0x30,0xe2,0x9f,0xcb,0x70,0xa4,0x63,0xb6,0x3e,0x6b,0x7e,0x6e,0xfe,0x17,
+  0xe5,0x93,0xc2,0xac,0x9c,0xb4,0x26,0x14,0x86,0x48,0x50,0xde,0xc7,0xa9,0x94,0xec,
+  0x91,0x13,0x65,0xf1,0xec,0x78,0xc3,0xca,0x5f,0xd6,0x83,0x6f,0x35,0x4f,0x85,0xec,
+  0xfe,0x75,0x19,0xf6,0x26,0x6f,0xc8,0x2c,0x1d,0x6b,0xbe,0x24,0x5d,0xe2,0x0b,0x53,
+  0x4b,0x2e,0xc8,0x9e,0xfc,0xaf,0x52,0x91,0xff,0x05,0xfe,0x4f,0xb3,0x50,0xcb,0x3d,
+  0xd9,0x42,0x88,0xda,0x63,0xb6,0xfd,0xd9,0xa3,0xe3,0xd4,0x16,0xb1,0xef,0x3b,0xe3,
+  0x35,0xbe,0x85,0x68,0x4e,0x85,0xfe,0xcf,0xdf,0x67,0xe5,0x6b,0x14,0xd1,0x34,0xf7,
+  0xc2,0x34,0xcb,0x71,0xf4,0x88,0x31,0xab,0x30,0x12,0xf3,0xd4,0xdf,0x58,0x65,0xf5,
+  0xbf,0x08,0xf9,0x1f,0xf7,0x05,0xdc,0xfe,0x83,0xbb,0xb2,0x8e,0x20,0x05,0xb7,0x7e,
+  0x5d,0xbd,0x91,0xb9,0xf1,0x02,0xe2,0xff,0xbc,0x0c,0xf5,0x19,0x7f,0xaf,0xbf,0xd6,
+  0xde,0xbf,0x2e,0xc0,0xf9,0xb6,0x79,0x96,0x70,0x8e,0xea,0x87,0x74,0xf9,0xdd,0xf8,
+  0x57,0xd2,0xe2,0xff,0xc0,0xd2,0x94,0x7c,0xda,0x38,0xcf,0x6c,0xe2,0xa5,0xd6,0x98,
+  0x15,0xa0,0xb1,0x2c,0x58,0xd1,0x39,0xe2,0xc9,0x7f,0x3f,0xa8,0xa2,0x19,0x6f,0xc1,
+  0xd3,0x5c,0xbd,0xdb,0xff,0xeb,0x35,0xfd,0xa3,0x23,0x42,0xf8,0x00,0xe6,0x40,0x49,
+  0x46,0x1e,0xd7,0xff,0x62,0xbe,0xba,0x11,0xee,0x73,0xf7,0xdf,0xfd,0x1d,0xb5,0xef,
+  0x59,0x8e,0x1d,0x1e,0x8e,0x6d,0xdc,0xc3,0x62,0xde,0xf8,0x97,0x2a,0xfa,0x3d,0xf5,
+  0x96,0x7d,0x4f,0x8c,0xdf,0x20,0x86,0x51,0xfe,0x45,0xba,0xf0,0x34,0x1c,0xe0,0x2b,
+  0xc2,0xb7,0xf4,0x78,0xfc,0xd5,0x88,0x7f,0x14,0x2a,0x7a,0xa3,0x02,0xdb,0x2e,0xfa,
+  0x7f,0x89,0x46,0x21,0x69,0x72,0xc3,0x5a,0x42,0x98,0xbe,0x62,0x39,0xf8,0x47,0xec,
+  0xbf,0x29,0x79,0x3b,0x38,0xfa,0xf9,0x17,0xe2,0x1f,0x52,0xc7,0xab,0x73,0xc2,0xff,
+  0x83,0x60,0xca,0x59,0x9f,0xff,0x6a,0x81,0x9c,0x7f,0xa3,0x6e,0x17,0x4e,0xbe,0x1b,
+  0x35,0x6e,0x12,0xc2,0x41,0x78,0x12,0xee,0xcb,0xc9,0xff,0xa2,0xfa,0xcf,0xa5,0x37,
+  0xa8,0x1b,0x33,0xf2,0xd7,0x94,0xe7,0x7d,0x37,0x0c,0x2f,0x7d,0xaf,0xba,0xc1,0x6a,
+  0x84,0xb1,0x86,0x2a,0x22,0x42,0xa3,0xa8,0xff,0xec,0xe4,0x6b,0x50,0xff,0xaf,0xbd,
+  0xf1,0x70,0x8d,0xda,0xcd,0x1a,0xd9,0xfd,0xf1,0xde,0x01,0xff,0xbb,0x9d,0xb5,0xf0,
+  0x8c,0x05,0x84,0x6a,0xe1,0x49,0x3c,0x6a,0xe1,0x57,0x31,0x37,0xff,0x8b,0xfc,0x3f,
+  0x2b,0x6b,0xc0,0x97,0x2a,0x3c,0x6e,0x3c,0xac,0xd6,0x0c,0xf8,0xeb,0xac,0xfa,0x3f,
+  0xe6,0x86,0x18,0x5b,0x42,0xd4,0x68,0xa3,0x28,0xc5,0xee,0xf6,0xe4,0x7f,0xed,0x40,
+  0xfc,0xb3,0xad,0xd5,0xc7,0xd9,0x0e,0xf8,0x01,0xcc,0x30,0x6f,0x4d,0x37,0x45,0x05,
+  0xff,0xaa,0x28,0xcd,0x56,0x93,0xaa,0xe3,0x45,0xdb,0xf2,0xea,0x3f,0x5f,0x86,0x1b,
+  0xe6,0xd7,0xbe,0xd0,0x89,0x68,0x50,0x9a,0x67,0x2e,0xa5,0xc0,0x53,0x56,0x51,0xab,
+  0x39,0x1e,0x1c,0x46,0x8b,0x35,0xd9,0x70,0xf3,0xbf,0xa4,0x83,0xf0,0x5b,0x68,0xcc,
+  0x14,0x3f,0x24,0x2f,0xc1,0x85,0x47,0xcb,0xe6,0xda,0x0b,0x2c,0x9b,0x08,0x7f,0x90,
+  0x53,0x44,0xec,0xfb,0x43,0x9d,0x17,0x3c,0xfb,0xef,0x0e,0xf5,0x7c,0x2c,0x9d,0x0c,
+  0x24,0x3b,0x6b,0x6b,0x9e,0xa2,0x6e,0x74,0xe9,0x6a,0x27,0x51,0x31,0x1a,0x3f,0x2f,
+  0xd5,0x25,0x97,0x3c,0xe0,0xc9,0x07,0x1f,0xb8,0x39,0xaa,0x3c,0x09,0xe1,0xff,0x86,
+  0x6b,0xd8,0x3f,0x91,0xff,0x90,0xb2,0x03,0x02,0xf0,0x84,0x84,0x0b,0x29,0x56,0xfe,
+  0x77,0xa8,0xfd,0xb0,0xa9,0x6e,0x66,0xf3,0x3c,0xf9,0x5f,0x88,0x7f,0xfa,0xf4,0x51,
+  0xbd,0xde,0x20,0x43,0xa4,0xd3,0x34,0xb3,0x85,0xb3,0x1a,0x18,0xa3,0xc2,0x98,0x46,
+  0x2b,0xb0,0x7d,0x79,0xf5,0x9f,0xf5,0x95,0x2a,0x65,0x7b,0x51,0xd8,0xab,0xc8,0xea,
+  0xff,0x35,0x93,0x84,0x4f,0xf3,0xbd,0xfc,0x7b,0xf8,0x55,0xb8,0xde,0xcd,0xff,0x52,
+  0x97,0x50,0xb6,0x17,0x04,0xea,0xfc,0x01,0xe5,0xa7,0x7a,0xca,0x7c,0x36,0xe6,0x0f,
+  0x70,0x04,0x42,0xfd,0x41,0x7c,0x3d,0xe1,0x7d,0x65,0xee,0x60,0x40,0x97,0xbf,0xe3,
+  0xfa,0x7f,0x2a,0x11,0xff,0x2c,0x6a,0x34,0x26,0x0d,0xca,0x07,0xe1,0xd7,0x46,0x63,
+  0x7f,0xed,0x68,0x02,0x57,0x54,0x16,0xff,0x74,0x5c,0xfe,0xe4,0x6c,0x73,0x56,0xbb,
+  0xec,0xcd,0xff,0x22,0x33,0x35,0x97,0xea,0x73,0x06,0xe0,0x99,0xaa,0xba,0xcc,0x92,
+  0x7d,0x9d,0x8e,0x7e,0x06,0x44,0x6a,0x58,0x34,0xe5,0xe1,0x33,0x50,0xfd,0x67,0xca,
+  0xf6,0x2a,0x26,0x6f,0xf9,0x7f,0x1b,0xd7,0x99,0xea,0xdd,0x3e,0x27,0xb1,0x74,0x10,
+  0xfe,0x5b,0x17,0xf5,0x7f,0xde,0x73,0xce,0xef,0x22,0xff,0x3d,0x39,0x2d,0x75,0xcb,
+  0xfc,0xc2,0x57,0x0d,0xf2,0xff,0xf8,0xbe,0x9a,0x9d,0xef,0x86,0x35,0xec,0x32,0x7c,
+  0x9b,0xcf,0x3a,0x19,0x5a,0xe5,0xf1,0xff,0x58,0xf9,0xef,0xfa,0x0b,0xfe,0xfa,0xa6,
+  0x25,0xf0,0x2f,0x2c,0x22,0x12,0x0d,0xec,0x42,0xeb,0xcf,0xf2,0x07,0xc9,0xd1,0x34,
+  0x9f,0xb9,0xf5,0x55,0xac,0xfa,0xcf,0x37,0xa4,0xee,0x7b,0x0b,0x61,0xcf,0x4b,0x6c,
+  0x17,0xff,0x52,0xaa,0x3a,0x62,0xf3,0x9f,0x5f,0x46,0x68,0xb4,0x30,0xbd,0xf1,0xb4,
+  0xec,0xf1,0xff,0x58,0xf5,0x9f,0xa1,0xa8,0x6b,0x43,0x47,0x76,0x3f,0x9a,0x64,0xf5,
+  0x23,0xb0,0x2a,0x22,0x4a,0xc2,0x31,0x92,0x93,0xff,0x45,0x4e,0x80,0x65,0xb5,0x21,
+  0x11,0x1f,0xd9,0x45,0xfb,0xdd,0x29,0x2b,0xf0,0xb1,0x49,0x3e,0xd5,0xf6,0xa6,0x28,
+  0x9d,0xd7,0x99,0x53,0xff,0x59,0xdd,0xff,0x52,0xb8,0x1d,0xd1,0xce,0xc7,0xe2,0x8f,
+  0x32,0x8a,0x7f,0x55,0x9f,0x2a,0x15,0x1b,0xf1,0x96,0x6d,0x6f,0x20,0x7e,0x2e,0x31,
+  0x02,0x9b,0x3c,0xfd,0xbf,0xe6,0x17,0xd4,0xc0,0x56,0x08,0x1b,0xa1,0x7f,0x2e,0x5b,
+  0xa9,0xad,0x87,0xf0,0xa2,0x5b,0x11,0xff,0x58,0xf9,0xef,0x94,0xaf,0xfd,0x28,0x8e,
+  0x8f,0xec,0xf2,0xf8,0x7f,0xa8,0xfe,0xf3,0x6c,0x5d,0x1f,0x08,0x95,0x15,0xb6,0xf0,
+  0xad,0xe1,0x1a,0xab,0xff,0xd7,0x03,0x76,0x3e,0xb8,0xa4,0x7f,0x09,0x81,0x50,0xd9,
+  0xb1,0x9c,0xfa,0xcf,0x23,0x6d,0x61,0x08,0x20,0xde,0x50,0xcd,0xdb,0x63,0x15,0xcf,
+  0x17,0xc8,0x04,0x33,0xae,0xa1,0x34,0x73,0x72,0xc5,0x34,0x10,0xfe,0xb9,0xe4,0xf0,
+  0x9f,0x7b,0x4a,0x89,0xf6,0xfc,0x64,0xcb,0xd2,0x9f,0xc8,0xdb,0xdb,0x04,0xff,0xf9,
+  0x81,0x6a,0x1b,0xf8,0x95,0x9f,0xc1,0xaf,0x28,0x9e,0x25,0x9f,0x2c,0xf0,0xe2,0x9f,
+  0x8b,0x70,0x93,0x11,0x3c,0xf1,0xd4,0x5c,0x11,0x08,0x0b,0x6e,0x66,0x73,0xad,0xf8,
+  0xe0,0xa0,0x7c,0x86,0x1d,0xf5,0xc7,0x28,0x5f,0xcc,0xe5,0x4b,0xcf,0x0f,0x65,0x94,
+  0x74,0x38,0xcc,0x6f,0xed,0xaa,0xbe,0xb3,0x6d,0x48,0x9f,0x81,0x8f,0x81,0x6b,0xc5,
+  0x2a,0x04,0x54,0x3d,0x22,0x75,0x1b,0x61,0xbe,0x81,0xfc,0x3f,0x0e,0xfe,0x01,0x84,
+  0x79,0xad,0x7a,0x9b,0x5f,0x2b,0x54,0xa0,0xa3,0x55,0x17,0xfd,0xbf,0x9c,0x78,0x1f,
+  0xaa,0x4e,0x6f,0xba,0x45,0x63,0x27,0xdc,0xfc,0x32,0xca,0x67,0x97,0xc2,0x8b,0xd0,
+  0xda,0xaf,0x54,0x4b,0x85,0x1a,0x17,0xd7,0x88,0x42,0x40,0x45,0x49,0xb6,0xbd,0x75,
+  0x3d,0x3b,0x89,0x57,0xc0,0xeb,0xff,0xa1,0xd9,0xd5,0xdd,0x19,0x4c,0x2e,0xab,0xa9,
+  0x38,0xaa,0x10,0xff,0x07,0x8d,0xa3,0x15,0xdf,0x64,0x4f,0xc3,0x7a,0xa9,0xae,0x3d,
+  0x98,0xd4,0x47,0x3c,0xeb,0x87,0xc6,0x1f,0xba,0x3b,0x98,0xec,0xb4,0xc3,0x5e,0x3e,
+  0x12,0xbe,0x2e,0x16,0x06,0x01,0xe3,0xd6,0xe0,0xa6,0x9c,0xfc,0x41,0x5c,0x6f,0xba,
+  0xc8,0xff,0x02,0x91,0xd1,0x1e,0xe5,0xb2,0xe3,0x91,0x3b,0xa9,0x8e,0x8a,0xd6,0xa8,
+  0xf9,0xfe,0x1f,0xa3,0x3a,0xc9,0xe2,0xc7,0x0e,0xc0,0xbd,0xb0,0xad,0x43,0x4d,0x15,
+  0xfa,0xf8,0x01,0xa9,0x96,0xfb,0x4f,0x27,0xc6,0xf0,0xef,0xeb,0x38,0x9c,0x96,0xef,
+  0xf5,0xf6,0xff,0x92,0x9e,0x30,0xf5,0x8c,0xaa,0xb3,0x5b,0x13,0x0f,0xe2,0xf9,0x6b,
+  0xc0,0xb1,0x3f,0x81,0x04,0xbe,0x4a,0x05,0x51,0xf3,0x16,0x60,0xae,0xff,0x87,0x97,
+  0x4e,0xd6,0xf6,0x2e,0xaa,0xda,0x86,0x4a,0x7b,0x48,0xf9,0xb6,0x5e,0x75,0xda,0x29,
+  0xe4,0x55,0x64,0xb0,0xa1,0xaa,0xbd,0x50,0x3d,0xa2,0xb6,0xef,0xca,0xb8,0xfc,0x4f,
+  0x51,0xff,0x27,0x9d,0x09,0x2c,0x97,0x6f,0xc1,0x6d,0xe5,0xa6,0xe1,0xc0,0x8d,0xbe,
+  0xab,0x44,0xfc,0xcb,0xbf,0x5c,0x3e,0x41,0xd0,0xe8,0x4c,0x49,0x8e,0xff,0xa7,0xd2,
+  0xca,0xa7,0x90,0xd3,0x88,0xf7,0x9e,0xa1,0x68,0xce,0xe3,0xe1,0x1a,0x4d,0x38,0x3a,
+  0x28,0xad,0xe9,0x3c,0xcc,0x1b,0x42,0x45,0xb9,0xfd,0xbf,0x0c,0xe5,0x10,0x5c,0xec,
+  0xfa,0xf8,0x70,0x60,0x88,0xa2,0x15,0x03,0x37,0x64,0x36,0x8e,0xdd,0x73,0x95,0xf1,
+  0xbc,0x55,0x11,0xe8,0x6e,0xab,0x10,0xe2,0x80,0x5f,0x73,0xeb,0x1f,0x86,0xb6,0xc0,
+  0x7f,0x6a,0x55,0x1b,0x8b,0xef,0x66,0x43,0xca,0x3d,0x44,0x44,0xbc,0x8b,0x51,0x23,
+  0xe6,0x1b,0xcd,0x92,0xb6,0xa6,0x50,0xab,0x48,0x84,0xff,0x0a,0x9b,0xe1,0xd8,0x1f,
+  0x0d,0xb6,0x18,0x8f,0xc1,0x34,0x68,0x6d,0x0f,0x0f,0xe0,0xb0,0x69,0x54,0x16,0xc0,
+  0x69,0xdc,0xdc,0x66,0x97,0xf2,0x28,0x74,0xf9,0x3f,0xca,0x46,0x54,0x72,0x4d,0xb2,
+  0x28,0x84,0xbb,0x79,0x27,0x10,0xdf,0xa3,0x49,0xc1,0x8d,0x3e,0x42,0x44,0xe8,0x45,
+  0xa4,0xd8,0xc3,0x11,0x85,0x79,0xf2,0xbf,0x2a,0xa9,0x69,0xd7,0xbc,0xcc,0xc6,0x4d,
+  0xf2,0x08,0x7b,0x9e,0xdd,0x60,0x46,0x47,0xfd,0xd9,0x46,0xd2,0x49,0xf9,0x0b,0x9c,
+  0x1a,0x3d,0xa8,0x0a,0x73,0xeb,0xa7,0xe1,0xaf,0xa7,0x9d,0x33,0x0e,0xac,0xbb,0x7f,
+  0x8f,0xfc,0xa6,0x9a,0x55,0x8b,0xd5,0x18,0xa2,0xa4,0xab,0xf9,0xdf,0x75,0xcb,0x31,
+  0x52,0xed,0xfa,0x7f,0xa8,0xfe,0xf3,0x25,0x65,0xb6,0x19,0x18,0x95,0x43,0xb0,0x41,
+  0x9a,0x43,0x66,0x7c,0xae,0x05,0x84,0x8e,0xc9,0xbf,0x15,0x08,0x61,0xe3,0x60,0x67,
+  0xaf,0xb3,0x7e,0xb6,0x22,0xfe,0xf9,0xcf,0x50,0x38,0xe3,0xd3,0xca,0x3e,0xde,0x75,
+  0x5e,0x09,0xf7,0x89,0x30,0x96,0x00,0x42,0xdf,0x65,0x6f,0xe8,0x74,0xa2,0x9f,0xb5,
+  0xa5,0xda,0xd3,0xff,0x42,0x8a,0xc2,0x3e,0xb6,0xa2,0x5f,0xdd,0xc9,0x66,0xc0,0xc3,
+  0xb8,0xbb,0xdd,0x4a,0xfc,0x55,0x31,0x9e,0x0e,0x26,0xa2,0x95,0xc3,0x4e,0x96,0x72,
+  0xfd,0xcf,0x15,0xe4,0xff,0x89,0x73,0xbc,0x3f,0xb9,0x7d,0x52,0x94,0x1f,0xa7,0x58,
+  0x8d,0x50,0x75,0x66,0x4a,0xbb,0xc5,0x46,0x1f,0x6e,0xca,0xc1,0x3f,0x63,0x50,0xd7,
+  0x81,0xe7,0xeb,0x08,0x6e,0xd3,0x82,0xbf,0x64,0x3d,0x0f,0xea,0x87,0xd6,0xc3,0x42,
+  0x13,0xbf,0x4a,0xb9,0xfc,0xe7,0xca,0x0b,0xea,0x05,0xf8,0xcf,0x8e,0xe0,0x68,0xf5,
+  0x98,0x9a,0x2d,0x5b,0x97,0x05,0x42,0x6d,0xd9,0x8e,0xa8,0x1f,0x35,0xe4,0x5e,0x37,
+  0xff,0x6b,0xad,0xe8,0x7f,0x1a,0x0f,0x0e,0xc9,0x31,0x52,0xcb,0x40,0xc0,0xce,0xff,
+  0xca,0x76,0x44,0x9d,0x13,0x2f,0x5e,0x93,0x93,0xff,0xf5,0x8e,0xf2,0x04,0xaf,0x8d,
+  0xdf,0xba,0x8f,0xa9,0x6c,0x03,0x54,0xcf,0x2d,0xce,0x69,0x84,0x7a,0x80,0xf8,0x3f,
+  0xfb,0x58,0xcc,0xad,0x7f,0x08,0x22,0xff,0x8b,0xaa,0xb7,0xd1,0x34,0x6b,0xf3,0x0a,
+  0x3f,0xd2,0x79,0xad,0x28,0x56,0x56,0xe7,0xe1,0x3f,0x8b,0xe8,0x61,0xdc,0xbf,0xaf,
+  0x6c,0x16,0x74,0xe2,0xb1,0xab,0x28,0xa7,0xb0,0xf6,0x01,0x60,0x61,0x95,0xfa,0xbf,
+  0xdb,0xfa,0xe4,0xd9,0xfe,0xef,0xc1,0x1e,0x79,0x0e,0x3c,0xd3,0x46,0x61,0x17,0x96,
+  0x53,0x18,0x21,0xa6,0x17,0x1f,0x92,0x15,0xe7,0xf7,0x1d,0xb5,0xf3,0xbf,0x46,0xe5,
+  0x21,0x76,0x9e,0x37,0xe4,0x37,0x02,0xdb,0x8e,0x40,0xf1,0x5d,0x79,0xcc,0xb0,0xd7,
+  0x4f,0x5b,0xb6,0xff,0x3b,0xf1,0x1b,0xd5,0x67,0xda,0xea,0xfa,0x72,0x0b,0x51,0x9e,
+  0x85,0xbb,0xa9,0x14,0x67,0x45,0x4e,0xfe,0x3b,0x3e,0x6d,0x46,0x9d,0x2b,0xfa,0x97,
+  0xe9,0x46,0x6e,0x61,0xf0,0xdd,0x10,0x8e,0x75,0xd7,0xb1,0x3a,0xc9,0x7e,0xfe,0xac,
+  0xff,0x67,0xb1,0x1a,0x4b,0x98,0xc0,0xd5,0x94,0x91,0xab,0x9f,0x9d,0x3c,0xf2,0xc5,
+  0x48,0x88,0xdd,0xe8,0x9c,0xbf,0xac,0xfc,0xaf,0x59,0x2b,0x29,0xff,0x4b,0x59,0xc7,
+  0xab,0x52,0x9e,0xc2,0x38,0x40,0x19,0x52,0x1f,0xd7,0xd5,0x31,0x16,0xf5,0xf6,0x3f,
+  0xa5,0xfa,0x3f,0x6d,0x01,0xa2,0xfd,0x98,0x90,0x36,0xa2,0x39,0x85,0xa0,0xdf,0x55,
+  0x23,0x10,0xd0,0x9a,0xc7,0xf5,0x7f,0x37,0x66,0x8d,0x96,0x5f,0x60,0x97,0xb4,0xc6,
+  0x4c,0xae,0x7e,0x3e,0x80,0xeb,0xa1,0xf0,0x27,0xe5,0xf9,0xf9,0x5f,0xf5,0xa9,0xc0,
+  0xbe,0xf2,0x18,0xbe,0xb6,0xa2,0x11,0x98,0x57,0xff,0x46,0x43,0x1c,0xd7,0xa7,0xeb,
+  0xbf,0x1d,0x48,0x66,0xfd,0x3f,0x71,0x34,0x02,0xf7,0x40,0xd5,0xe1,0x48,0x6e,0x21,
+  0x68,0x6d,0x26,0x2f,0x36,0xd8,0x7b,0xae,0x7d,0xb3,0xfb,0xbf,0x8f,0x21,0xec,0xe9,
+  0xe4,0x7a,0x3c,0xb7,0x10,0xd0,0x63,0x7c,0x66,0x3b,0x42,0xc1,0x8c,0xa7,0xff,0xa9,
+  0xf0,0xff,0x0c,0xaa,0x73,0x9b,0x4a,0x36,0x75,0x66,0xf4,0xc1,0x71,0x85,0x46,0x43,
+  0x45,0x57,0xb1,0x13,0x39,0xfe,0x1f,0x3c,0x34,0x75,0x05,0x32,0xf2,0x02,0xfe,0x9c,
+  0xb9,0x9b,0xe7,0x16,0x02,0xa2,0x46,0xa8,0xca,0x5b,0xf2,0xb9,0xfc,0xfe,0xa7,0xd2,
+  0xdf,0xf1,0x8f,0x67,0xd8,0x98,0x36,0xae,0x31,0x81,0x29,0x4a,0x43,0x8f,0xeb,0x7f,
+  0xda,0x16,0xfc,0x4e,0x67,0x3f,0x1c,0x35,0xd3,0x86,0xb7,0x50,0xcc,0x76,0x2b,0x34,
+  0xb6,0xa9,0xfc,0x70,0x85,0x97,0xff,0x23,0xd0,0x4e,0x0f,0x7b,0x83,0xad,0xe7,0x61,
+  0x23,0xaf,0xb1,0x85,0x44,0x5f,0x85,0x73,0xf2,0xdf,0x35,0xdb,0xed,0xa3,0x77,0x58,
+  0x6d,0x1a,0x9c,0xf1,0xdb,0x71,0xe1,0x7d,0xa1,0xa9,0x28,0x59,0xe6,0xf6,0x27,0xca,
+  0xe6,0x7f,0xd1,0xfb,0xd8,0x7f,0xb8,0x03,0x74,0xab,0x11,0x86,0xcd,0x07,0xd6,0x76,
+  0xc2,0x6a,0x3a,0x88,0x1d,0x76,0xe2,0xf5,0x59,0xff,0x0f,0x15,0xdd,0xed,0x83,0x81,
+  0x35,0x75,0x6e,0x21,0x20,0x3f,0x35,0xe2,0x44,0xd3,0x4d,0x8d,0x18,0xde,0x71,0xf8,
+  0x39,0xc7,0xed,0xfe,0xa7,0x6d,0xf2,0x19,0x53,0x74,0xfb,0xca,0x49,0x8c,0x3a,0x4f,
+  0x15,0x63,0xbc,0xf5,0x7f,0xac,0xfe,0xa7,0x22,0x4d,0xf5,0x03,0xfe,0x49,0x95,0xba,
+  0xa5,0x78,0xc7,0x5f,0x86,0x39,0x08,0x84,0xaa,0x5d,0xff,0xe1,0x1a,0x6f,0xfe,0x17,
+  0x87,0xf0,0xe6,0xfc,0x42,0x40,0xe4,0x08,0x62,0xcf,0xe5,0xd4,0x3f,0xcc,0xe6,0x7f,
+  0x3d,0x1d,0x26,0xfe,0xb3,0x55,0xf8,0x48,0xb2,0x33,0xe0,0x20,0x4e,0x13,0x3f,0xe1,
+  0xf6,0xe3,0xb0,0xfa,0x9f,0xde,0x8e,0xda,0x3b,0x85,0x66,0x3c,0x3c,0xae,0x10,0x50,
+  0x98,0xe2,0x89,0x47,0x9c,0xfc,0x26,0x0b,0xff,0xe0,0xef,0xbb,0x49,0x7e,0x83,0x13,
+  0xbe,0x8d,0xe6,0x3c,0xff,0xbb,0x06,0xe2,0x1f,0xdc,0xda,0x1c,0xfb,0xb0,0xca,0xaa,
+  0x07,0x45,0xfc,0xe7,0x7e,0x6a,0xc3,0x97,0x9f,0x38,0xd6,0x73,0x88,0xfa,0x85,0xbd,
+  0x94,0xc7,0xff,0xb1,0xea,0x4d,0x25,0x06,0xe8,0x20,0x93,0xbb,0xde,0x0c,0x2a,0x44,
+  0xe9,0xed,0xff,0xae,0x08,0xff,0xcf,0x03,0xfe,0xb7,0xd8,0x39,0xb8,0x37,0x49,0x44,
+  0x20,0x46,0x8d,0x7d,0x05,0xff,0x67,0x15,0x1c,0xda,0x3a,0x0b,0x97,0x75,0xe2,0x98,
+  0x3d,0xdc,0xce,0xff,0xe2,0x7e,0x2d,0xf1,0xb4,0xd2,0x09,0xa9,0xbe,0x48,0xae,0xfd,
+  0x81,0xa8,0x24,0xcf,0x2f,0x73,0xfb,0xbf,0xeb,0x59,0xff,0xcf,0x86,0xb6,0xa6,0x17,
+  0xf4,0x7b,0x54,0x8a,0x07,0xe5,0x15,0x82,0xe6,0xfe,0xf6,0x3a,0x4f,0xfd,0x1f,0xcb,
+  0xff,0x53,0xb5,0x74,0x8d,0xfc,0x1e,0x7b,0x9a,0xc7,0xa8,0xdb,0xbb,0xa7,0x10,0xd0,
+  0x6f,0xa8,0x35,0xc6,0x2a,0xf9,0x98,0x53,0x80,0xde,0xee,0xff,0xbe,0x34,0xd9,0x9c,
+  0x61,0x67,0xd5,0xdc,0xfc,0x26,0xab,0x15,0xc2,0xa4,0x54,0x4e,0xfd,0xc3,0x6c,0xfd,
+  0xba,0xb3,0xf2,0x39,0xf6,0x33,0x9e,0xe5,0xaf,0x3a,0xf9,0x5f,0xa2,0x35,0xfc,0x1a,
+  0x4f,0xfe,0xaf,0xf0,0xff,0xc0,0x4c,0xcd,0xff,0xbf,0x9a,0x86,0xd8,0x3a,0xb8,0x9e,
+  0x0e,0x62,0xde,0xe7,0x0f,0xa1,0xfd,0xf9,0x0a,0xdb,0xe6,0xd8,0x37,0xe0,0xc2,0x5e,
+  0x75,0xf9,0xef,0x0a,0xff,0x9c,0x6d,0x41,0x3c,0x93,0x3b,0xdf,0x3d,0xa8,0x8a,0xa2,
+  0x4c,0x42,0x77,0xec,0x4f,0xdc,0xf2,0xff,0xc4,0xfd,0x37,0xb0,0xe3,0x4d,0x5c,0xab,
+  0x39,0x93,0xdb,0xf8,0x60,0x57,0x26,0x9a,0x94,0x74,0xd6,0xe3,0x89,0x7f,0x89,0xd9,
+  0xa5,0xe4,0x5e,0x7c,0x89,0x5e,0xe2,0x75,0x83,0x8e,0xfd,0xf4,0xa7,0x27,0x89,0x56,
+  0xef,0x6d,0x45,0xfb,0x3c,0xf5,0x57,0xb3,0xf9,0x5f,0x15,0xc1,0x2e,0xd1,0xef,0xa0,
+  0x7e,0x60,0x5c,0xa1,0x6c,0x25,0x98,0xee,0xcc,0xc9,0xff,0x52,0x45,0x3d,0xc0,0xd1,
+  0xf2,0xe7,0xe1,0x34,0xdc,0x60,0x06,0x72,0xf7,0x3b,0xde,0xc8,0x88,0xff,0x73,0x47,
+  0x9e,0xff,0x27,0x76,0xeb,0x46,0xf6,0x2b,0x4a,0xc4,0xb0,0xf9,0xb7,0xd3,0xb3,0x89,
+  0xd8,0x72,0xad,0xee,0x3f,0xe8,0xe1,0x63,0x64,0xeb,0xff,0xa4,0x44,0x9a,0xd8,0xc3,
+  0xda,0xf4,0xbc,0x46,0xa8,0xfb,0xf5,0x2f,0xc5,0xaf,0xdd,0xc7,0x32,0xce,0x7e,0x97,
+  0xcd,0xff,0x02,0x52,0x0b,0xe2,0x81,0x1a,0x33,0xe2,0xf0,0xed,0x63,0x56,0x47,0x30,
+  0x2e,0x3a,0x64,0x39,0x9f,0x6e,0x71,0x9a,0xe6,0x94,0x0f,0xc8,0xde,0x84,0x79,0xa6,
+  0x47,0x3f,0x4c,0x24,0xfe,0xc3,0x5f,0xa6,0x9b,0x4d,0xe7,0xfc,0x95,0xed,0x7f,0x0a,
+  0xc1,0x4c,0x75,0x4e,0xfe,0xd7,0x0d,0x56,0x20,0xe3,0x92,0x50,0x85,0x3c,0x32,0xc9,
+  0xe5,0xff,0x9c,0xa0,0x34,0xf0,0xe3,0xc5,0xef,0xc9,0x17,0x8c,0xe7,0x61,0xce,0xe8,
+  0x92,0xb1,0xea,0x0b,0xdd,0x97,0x29,0x11,0x2c,0xbb,0x90,0x86,0x83,0x39,0xfc,0x1f,
+  0xed,0x24,0xec,0xe3,0x37,0xbe,0xa2,0xfe,0x86,0xfd,0x9c,0xff,0x28,0x36,0x63,0x00,
+  0xd1,0x4e,0xc6,0x7c,0x82,0x12,0xc1,0x04,0x10,0x4a,0xd4,0x0e,0xa0,0x30,0xea,0xe9,
+  0x7f,0x61,0x8a,0x32,0x8f,0x45,0x75,0x89,0xe3,0x4d,0x9d,0xaa,0x2e,0xf0,0x8f,0x6e,
+  0x01,0x3f,0xb1,0x30,0x44,0xc4,0xc7,0xcb,0xff,0x79,0x14,0x0e,0x84,0x2c,0xda,0x73,
+  0x88,0xfc,0x3f,0xaa,0xe0,0x0f,0x5b,0xfc,0x67,0x47,0xb1,0x63,0x2e,0x1f,0xac,0xf2,
+  0x17,0x30,0xc6,0x6f,0x32,0xbf,0x39,0x2a,0x9f,0x56,0x9e,0x91,0x88,0xff,0x5c,0x7d,
+  0xda,0x2e,0x14,0xe9,0x2c,0x8c,0x7e,0xa7,0xff,0xc5,0xa8,0xb4,0x17,0x2e,0x90,0x5a,
+  0x84,0x9b,0x31,0x27,0x3e,0x68,0x2f,0x0c,0xff,0xa8,0xa7,0xff,0x45,0x1b,0x9e,0xdf,
+  0x07,0x40,0x74,0x97,0xa3,0x42,0x40,0xbb,0xac,0xdb,0x3e,0xa3,0x78,0xee,0x8f,0xbf,
+  0xc8,0xa0,0x07,0xff,0x4c,0xc3,0x63,0x17,0x15,0x85,0x48,0xd4,0xc3,0x6b,0x82,0x86,
+  0xcd,0x7e,0xad,0xff,0x00,0xb6,0x51,0xfd,0x28,0xeb,0xf9,0x8b,0xd3,0x39,0xfc,0x1f,
+  0x43,0xe7,0x50,0xdb,0xe7,0xab,0x4f,0xec,0x80,0x7f,0xa1,0x69,0xc6,0x0a,0x8f,0xf3,
+  0x0d,0x56,0xfd,0x1f,0xa7,0x10,0x99,0xcb,0x77,0x1a,0x95,0xae,0x82,0x2e,0xfe,0xc5,
+  0x4c,0x68,0x0d,0x9b,0x6a,0x7e,0xbb,0x43,0xc4,0x83,0x4e,0xc0,0xf7,0x92,0x55,0x19,
+  0x9f,0x0d,0x0c,0x8a,0xd6,0xb0,0xd3,0xce,0xf9,0x9d,0xe2,0x5f,0x7d,0xb1,0xfa,0xfe,
+  0x92,0x98,0xbc,0xf1,0xf0,0x83,0x90,0x36,0x45,0xe1,0x88,0x0d,0x10,0x13,0xf8,0xc7,
+  0x78,0x5f,0x6b,0xa0,0xd4,0xf8,0x13,0xde,0xf8,0x17,0xbb,0xd0,0x36,0xab,0x7f,0x12,
+  0x6a,0x63,0xe0,0x32,0x35,0xc2,0xf0,0xf0,0x9f,0x2f,0xa8,0xe2,0xca,0xe8,0x47,0x3c,
+  0xfd,0x2f,0x2a,0x33,0x74,0x5a,0x1f,0x08,0xee,0xea,0xfc,0x15,0x47,0xfc,0x93,0x59,
+  0x42,0xfa,0x7f,0x9b,0x3b,0xfa,0xf9,0xba,0x20,0x62,0xb9,0xfa,0x79,0x60,0x33,0x9e,
+  0xc8,0x67,0x9e,0x40,0xeb,0x71,0xb1,0xe9,0x7b,0xab,0xae,0x23,0x7b,0x32,0x44,0x40,
+  0x28,0x27,0x11,0xde,0xed,0xff,0xc5,0xf1,0xd2,0x3d,0x7c,0xe6,0x08,0x55,0xb7,0xe6,
+  0x9d,0xdb,0xab,0x28,0xf1,0xff,0x39,0x9c,0x66,0x55,0x36,0x10,0xd6,0x21,0x80,0x90,
+  0x9b,0x7f,0xda,0x5a,0xd1,0x0f,0x89,0x01,0xd1,0xf6,0xeb,0xb8,0xf2,0x30,0x44,0xac,
+  0xb6,0x17,0x9d,0xee,0x7a,0x13,0x2f,0x9a,0xbb,0xbf,0x8c,0x14,0xec,0x83,0xc3,0x19,
+  0x0b,0xed,0xe0,0x31,0xb7,0x8e,0x47,0x53,0xf2,0x39,0xfd,0x1c,0x0a,0xde,0x44,0x78,
+  0x6f,0xff,0x8b,0xd7,0xf1,0x18,0x5d,0x0f,0x4b,0x79,0x75,0x46,0x1b,0xf5,0xf2,0x7f,
+  0xbc,0x40,0xc8,0xd3,0xff,0x02,0x7e,0x09,0xcf,0x6c,0xae,0x33,0xee,0xa3,0x7a,0xbf,
+  0x6f,0x0a,0x7e,0x6c,0xf9,0x29,0xdb,0x3f,0x60,0x6d,0x7c,0xf7,0x27,0x73,0xfa,0x5f,
+  0xb4,0xc0,0xa3,0x19,0xdc,0x76,0xff,0x99,0x0d,0xb3,0xf5,0xc2,0xff,0x10,0x7e,0x83,
+  0xe7,0x75,0xa4,0xca,0xe9,0x7f,0x51,0x43,0x6e,0x1f,0xe3,0x96,0x07,0x04,0xff,0x47,
+  0xb8,0x7d,0xfa,0x2d,0xbe,0x90,0x67,0x7c,0x6e,0xfd,0x9f,0x47,0x11,0xf6,0xa8,0x65,
+  0xac,0x3f,0x41,0xd1,0x2e,0x41,0x7b,0xb6,0x1b,0x81,0xd9,0x40,0xc8,0xdb,0xff,0x62,
+  0x15,0xae,0xff,0xba,0x8a,0x92,0xb5,0xf2,0xeb,0xc6,0xc8,0xb2,0xf9,0x15,0xf7,0x53,
+  0xfc,0xcb,0x6c,0x73,0xe7,0x5b,0x91,0xd3,0xff,0x62,0x60,0xca,0x0b,0xca,0x79,0xf8,
+  0x61,0x8b,0xf4,0x40,0xf5,0xb0,0x71,0xb6,0xcc,0xe2,0x3f,0x7b,0x1a,0xa1,0x32,0x21,
+  0xbc,0xe5,0xec,0x47,0x3d,0xa5,0x67,0xe0,0x59,0x68,0x68,0x2a,0x3e,0xd1,0xb9,0x72,
+  0xdb,0xd1,0xc0,0xae,0xb6,0x40,0xb2,0xfa,0x8c,0xdb,0x18,0xeb,0xac,0xd5,0x5a,0xe2,
+  0x39,0x67,0xfc,0x1a,0xc4,0x9f,0x03,0x6c,0x81,0xd6,0xbd,0x8e,0x55,0xf1,0x6e,0x5d,
+  0x44,0xbb,0x5e,0x37,0xd3,0xde,0x42,0x88,0xc5,0xdc,0xd3,0x8f,0x52,0x45,0x7c,0x45,
+  0xd5,0x9e,0xa9,0xec,0xb3,0xbe,0x35,0x8b,0x7f,0x74,0xea,0xff,0x6e,0xcf,0xb7,0x49,
+  0x25,0xfc,0x63,0x8f,0x0f,0x95,0xee,0x48,0xad,0x2f,0x9c,0x41,0xf5,0x97,0x84,0xa2,
+  0x04,0xfe,0xb1,0x19,0x9e,0x56,0x23,0x0c,0x14,0x4e,0xe5,0xd4,0x3f,0x3c,0xda,0x46,
+  0x6c,0x9f,0xf2,0x95,0xec,0x4d,0xa9,0x4e,0xe0,0x9f,0x9c,0x46,0xae,0xf8,0xfc,0xe5,
+  0x23,0x15,0xf6,0xf8,0x55,0xd2,0x23,0x68,0xc6,0xe7,0x13,0xc9,0x79,0x58,0x79,0x11,
+  0xec,0x44,0x30,0x2b,0x22,0xe6,0x00,0x21,0x4f,0xfd,0x67,0xd8,0xca,0x07,0x8c,0x3a,
+  0x08,0x42,0xb3,0x8e,0xc6,0xba,0x8e,0xfc,0x3f,0xaf,0xc3,0x10,0xd4,0xb9,0xeb,0x2d,
+  0x40,0xfe,0x1f,0xfb,0xf7,0x8a,0x14,0x5c,0x03,0xf7,0xf1,0xb0,0x55,0xf6,0xf9,0xab,
+  0x30,0x8f,0xf8,0xcf,0x63,0x70,0xaf,0xb2,0xcd,0x2d,0x84,0xe8,0x4b,0xe5,0xf4,0xbf,
+  0x68,0x31,0x3a,0xda,0x4d,0xf3,0x5f,0xe6,0xb3,0x80,0x4a,0xf8,0x47,0xb5,0xf8,0x09,
+  0xba,0xe9,0x14,0x2a,0x21,0x3e,0xaa,0xb3,0xdf,0xa5,0xa4,0x0a,0x58,0xcb,0xef,0xec,
+  0xbf,0xb6,0x3d,0x31,0x99,0xef,0x8d,0x4d,0x3b,0xae,0x52,0xb5,0xd2,0x7b,0x92,0x9e,
+  0xf7,0xd7,0xd7,0x1e,0x76,0xf3,0xcd,0x7b,0xf9,0x54,0xe8,0xe7,0xb3,0xdf,0x08,0x86,
+  0xfc,0x0d,0xf0,0x14,0x9f,0x33,0xb2,0x71,0x8d,0xfc,0x1c,0xfc,0x77,0xef,0x6c,0xa7,
+  0x10,0xe2,0x19,0xc4,0x27,0x87,0xa7,0xbb,0xfc,0x9f,0xee,0x42,0x7c,0xad,0x8e,0xda,
+  0x69,0xce,0x83,0xc1,0xb4,0x84,0xb0,0x39,0xe3,0x16,0xbe,0x1b,0xf2,0xa7,0xe5,0x26,
+  0xf7,0x7c,0x54,0xf0,0x01,0xbf,0x64,0xed,0x56,0x97,0x23,0xaf,0xf1,0x39,0xa3,0xd9,
+  0x6d,0xeb,0xa6,0x9c,0x42,0x2e,0x6e,0xff,0x8b,0xef,0x97,0x6e,0x86,0xc7,0xe3,0xd7,
+  0xf7,0x97,0xdc,0xc1,0x5e,0x61,0xf7,0x50,0x3e,0x3b,0xd9,0x9f,0xbd,0x79,0xf6,0xc7,
+  0xdb,0xff,0xe2,0x5f,0x93,0x7b,0xe0,0xaf,0x4c,0xbf,0x81,0xe3,0x1f,0x84,0xad,0xd9,
+  0x61,0xfc,0xba,0x9c,0xf1,0xde,0xfe,0x17,0xc7,0x21,0xdd,0xb6,0xd2,0xbc,0x97,0x0b,
+  0xff,0xcf,0x0c,0x91,0x7f,0xc1,0x9f,0xf0,0xda,0x73,0x14,0x06,0x3d,0xfe,0x9f,0xef,
+  0xe1,0xfe,0x75,0x03,0x79,0x33,0xa8,0x4c,0xdf,0x6e,0x91,0xc6,0x0e,0x97,0x95,0xaf,
+  0x3a,0xf3,0x25,0xe1,0x2d,0x4f,0xfd,0xbd,0x53,0xd9,0x24,0xaf,0x6a,0xa7,0x1f,0xf7,
+  0x88,0x91,0x57,0x08,0x91,0xb9,0xfd,0x2f,0xb8,0x76,0x41,0xf9,0x79,0x40,0x9c,0x2f,
+  0xbe,0xc6,0x7e,0x0c,0x73,0xcc,0x1d,0x96,0x3f,0x64,0x4e,0x4e,0x62,0x94,0xdb,0xff,
+  0x82,0x2b,0x4b,0x61,0xbd,0x31,0xcb,0xf4,0x6f,0x0c,0x47,0xb5,0x97,0x89,0xbf,0x4a,
+  0x69,0xec,0x4e,0x3d,0x1f,0xbb,0xa3,0xa5,0xc7,0xff,0x33,0x5d,0x44,0x67,0xae,0xed,
+  0x61,0xab,0x45,0xbd,0xbe,0xec,0x7e,0x3d,0x3d,0x67,0xbc,0xb7,0xff,0x85,0x82,0x6a,
+  0x59,0x4d,0xd9,0x70,0x01,0xd4,0x67,0x0d,0xad,0xae,0x81,0x71,0x8d,0x9f,0xbc,0xfc,
+  0x9f,0x95,0xf0,0xa2,0xd4,0x68,0xa2,0xd9,0xf9,0x2c,0x7b,0x86,0xda,0x96,0x51,0x7e,
+  0xcd,0x6f,0x61,0x5e,0x8e,0x7e,0x4c,0x67,0xfd,0xa4,0xae,0x3e,0x43,0xd5,0x56,0x4d,
+  0xbf,0x99,0xa5,0xb5,0x04,0xad,0xf9,0xe6,0x26,0xc2,0xbb,0xfa,0x31,0x0b,0x2e,0x19,
+  0x4f,0xf3,0xd9,0xe9,0xc0,0x69,0xf9,0x8c,0xf2,0x3c,0x9f,0x95,0xc9,0x2d,0x04,0x6d,
+  0x77,0x44,0xf5,0xe0,0x9f,0xe3,0xd4,0xf6,0x82,0xab,0xb1,0xa6,0x53,0xca,0x06,0xee,
+  0xad,0xff,0x63,0x09,0x0b,0x32,0x25,0x88,0x88,0x3c,0xfd,0x2f,0x8e,0x43,0x87,0x1a,
+  0x5e,0xaf,0x32,0xb4,0x36,0x9d,0x79,0xd3,0x74,0x84,0x93,0x1e,0xfe,0xcf,0xc6,0xb2,
+  0x0e,0xd8,0x96,0x56,0x7b,0xca,0x46,0xdc,0xf8,0x23,0xaa,0xb1,0x2f,0x2b,0xcc,0x20,
+  0x46,0xab,0xa7,0xfe,0x33,0xe2,0xe7,0xf5,0xc9,0xba,0x54,0x60,0x9f,0x9c,0xe1,0xcf,
+  0x78,0x97,0x81,0xa7,0xa3,0x1c,0x33,0x3d,0xfd,0x2f,0x0e,0xc2,0x45,0xca,0x8f,0x1b,
+  0x6d,0xfe,0x8d,0x3a,0x41,0xa3,0x10,0xbb,0xe3,0xa7,0x3d,0x9e,0xf8,0x3f,0xeb,0x71,
+  0x37,0x2c,0x79,0x40,0xd6,0x99,0xa8,0x7f,0x98,0x8f,0xb7,0x49,0x18,0xcc,0xf1,0xff,
+  0x3c,0x4a,0x4d,0xed,0xbf,0xc5,0x54,0xd8,0x60,0xe6,0xd6,0x2f,0x72,0x84,0xf7,0xec,
+  0xa7,0x27,0xff,0x0f,0xc7,0x63,0x38,0xdc,0x12,0x61,0x81,0xb6,0x87,0x07,0x49,0x1b,
+  0xe1,0xf1,0xfa,0xc9,0xed,0x7f,0xf1,0x4d,0xfe,0xf0,0xeb,0x08,0x03,0x4a,0x34,0xa7,
+  0x1e,0x60,0x7e,0x87,0xd0,0x81,0x1c,0xff,0x4f,0x1f,0xc4,0xba,0x4b,0xc2,0xfe,0x00,
+  0xff,0x45,0x6e,0xfd,0x1f,0x57,0xc8,0xe9,0x7f,0x51,0x76,0xd1,0x02,0xc9,0x17,0x45,
+  0x21,0x44,0x91,0xff,0x9e,0xaf,0x1f,0xd7,0xff,0x43,0xf9,0xef,0x2f,0x4a,0x75,0x1d,
+  0x01,0xca,0x8f,0x7b,0x8a,0xd7,0x4d,0xac,0x1f,0x8f,0xff,0xa7,0x74,0x0b,0x55,0x7b,
+  0xe6,0x6a,0x7b,0x38,0x40,0xb0,0xa7,0x2f,0xbf,0xb1,0xa0,0x10,0x4e,0x78,0xf2,0x3d,
+  0xbf,0x0b,0x8f,0x99,0xd5,0x29,0x75,0xcc,0x37,0x95,0xdd,0xe3,0xc0,0x1e,0x9c,0xa6,
+  0xcf,0xd3,0x01,0x6d,0xd4,0x83,0x7f,0x8e,0xd3,0x21,0x7d,0x9f,0xba,0x85,0x15,0x0b,
+  0xff,0xf3,0x44,0xeb,0xad,0xe9,0xa7,0xb9,0xfe,0x1f,0x3e,0xa7,0x37,0x3a,0xdc,0x19,
+  0x81,0x63,0x94,0x7f,0x91,0xe7,0xff,0x11,0x42,0xbe,0xff,0xe7,0x90,0xc8,0xf6,0x62,
+  0x59,0x37,0xc8,0xf8,0x42,0xd0,0x79,0xfe,0x9f,0xd4,0x2e,0x63,0x49,0xf2,0xc1,0xda,
+  0x70,0xb6,0xff,0xc5,0xf8,0x42,0x31,0x87,0x73,0xf2,0xbf,0xf6,0x9b,0x22,0xff,0x0b,
+  0x81,0x0d,0xcf,0xab,0x3f,0xec,0xe2,0x1f,0x8f,0xff,0x07,0xf6,0x5b,0xf9,0x62,0xdb,
+  0x13,0xf9,0xb0,0xc7,0x11,0xf2,0xeb,0x3f,0xeb,0x46,0x44,0x0b,0x67,0xfb,0x5f,0xe4,
+  0x17,0x82,0x26,0xc1,0xdd,0x1f,0xf7,0x15,0xdf,0x69,0x8c,0xb6,0xed,0xaa,0x08,0x10,
+  0xff,0xe7,0x58,0x7e,0xbd,0x6b,0x5b,0x78,0xc7,0xed,0x7f,0x21,0xfa,0xbf,0x2f,0x24,
+  0xff,0xcf,0x69,0x01,0x7b,0x96,0xe6,0xce,0x57,0x11,0xc2,0x29,0xa7,0xa2,0x39,0xc5,
+  0xbf,0xfa,0xa0,0xae,0x25,0xb0,0x59,0x9e,0xcb,0x9e,0xbd,0x52,0x21,0x9d,0xc3,0x9e,
+  0xfc,0xf7,0xc3,0x5b,0xbb,0xf9,0x36,0x3d,0x72,0xcc,0xa7,0x2b,0x43,0x1e,0xd8,0xe3,
+  0x15,0xe4,0xfb,0x72,0xea,0xff,0x64,0xf3,0xbf,0x14,0xb8,0xf2,0x7c,0x1d,0xff,0x73,
+  0x28,0x9b,0xff,0xb5,0xaa,0x6d,0xf1,0x74,0x70,0xf5,0xe9,0x2d,0xc4,0x74,0x2d,0xd5,
+  0x53,0xb2,0xd7,0x03,0xe5,0x7f,0xad,0xa7,0xfc,0x2f,0xe2,0xaf,0xae,0xbf,0xc2,0xf3,
+  0x37,0x7b,0xfc,0x3f,0x56,0xfe,0xd7,0xca,0xe0,0x43,0xf2,0x70,0x24,0x7f,0x9a,0x8e,
+  0x70,0x2c,0xc7,0xff,0x33,0x40,0x69,0x5f,0x66,0x39,0xe0,0x6b,0xed,0x51,0xfb,0x24,
+  0x8f,0xfe,0x3d,0xfe,0x9f,0x82,0x08,0x9e,0xbf,0xd0,0x3e,0x67,0xd8,0x8d,0xda,0x7d,
+  0x71,0x4f,0xfd,0x67,0x8f,0x50,0xe6,0xf1,0xff,0x14,0x10,0x1b,0x41,0x7f,0x5d,0x8d,
+  0xb0,0x25,0x06,0x8f,0x5f,0xc1,0x3e,0xbb,0xfe,0x9f,0x94,0x14,0x82,0xfb,0xa1,0x6a,
+  0x50,0x5d,0xc9,0x3e,0x1b,0xea,0x1a,0x57,0xbf,0xcb,0x12,0xea,0x72,0xfb,0x5f,0xf4,
+  0xf3,0xdd,0xa9,0xe8,0x98,0xff,0x36,0x78,0x3a,0xa7,0x10,0x90,0x47,0xf0,0xe6,0xbf,
+  0xf7,0xb2,0x31,0xeb,0xbc,0x7f,0x85,0x46,0xf0,0x24,0xb8,0xf9,0xef,0xc2,0xff,0xd3,
+  0x31,0x3b,0x1e,0x18,0x90,0xcf,0x19,0xcf,0x52,0x21,0xc1,0x89,0xf6,0xaf,0x41,0x4f,
+  0xfe,0x7b,0x0f,0x3c,0x49,0xf9,0xa7,0x06,0x1b,0x34,0xaf,0xf0,0xfc,0x77,0xb1,0xb7,
+  0x9c,0xdf,0x97,0xea,0x3f,0xef,0x51,0xab,0x41,0xa5,0x26,0x83,0x6b,0x27,0x18,0x2f,
+  0x80,0x50,0xc6,0x83,0x7f,0x44,0xfe,0x97,0xa2,0x4e,0x49,0x1c,0x45,0xe3,0x75,0x05,
+  0x7d,0x0e,0xb9,0xf8,0xd0,0xca,0xff,0xca,0x44,0xb6,0xcb,0xd4,0x96,0x24,0xcb,0x5f,
+  0x1d,0x67,0x3f,0x3d,0xf6,0x70,0xc4,0xca,0xff,0x4a,0xc9,0x47,0x6a,0xf2,0xeb,0xad,
+  0x9d,0xb6,0x88,0xe2,0x69,0x4f,0xfd,0x1f,0xc4,0x3f,0x44,0xe2,0x4d,0x44,0xc9,0x7a,
+  0x3f,0x9b,0x9a,0x33,0xf1,0x7e,0xe7,0xd6,0x7f,0xe6,0xca,0x1a,0xd8,0x83,0x98,0x5b,
+  0x1d,0x65,0xbf,0x66,0xdc,0x08,0x4f,0xbc,0x7f,0x8d,0xe6,0xd5,0xff,0x09,0x1b,0x45,
+  0xbc,0xec,0x94,0x7e,0xaf,0xb1,0x62,0xe2,0xf1,0x19,0x47,0x9b,0x94,0xff,0x45,0xe3,
+  0x55,0x60,0xfd,0x1a,0xcf,0x3b,0x96,0x4e,0x88,0x7f,0x44,0xfc,0x0b,0x3e,0x85,0x78,
+  0x98,0x0d,0xc0,0x15,0xf6,0x17,0xd3,0xc9,0x3f,0x4d,0x4d,0x19,0x13,0x6c,0x9f,0x59,
+  0x83,0xe5,0x6e,0xd9,0xc3,0x71,0xf3,0x1d,0x71,0xf4,0x6f,0x16,0x8c,0xea,0xbf,0x59,
+  0x3b,0x27,0x1e,0x78,0x45,0x9e,0xc7,0x9e,0x8f,0x89,0xb4,0xaf,0xbc,0xf5,0xb3,0x74,
+  0xac,0x7c,0xd4,0x89,0x97,0xf1,0xd0,0xc9,0x8a,0x1b,0xf9,0xbc,0x0c,0x1e,0x8b,0xa6,
+  0xc3,0x86,0xf6,0xda,0xe3,0x45,0x79,0xf8,0x47,0x08,0x6e,0xff,0xaf,0xee,0x9b,0x4d,
+  0xa2,0x85,0x1b,0xea,0x26,0x56,0x03,0x0f,0xeb,0xd1,0xc3,0x13,0xce,0xd7,0xe3,0xff,
+  0x91,0xb6,0xc1,0x13,0x5d,0xe1,0xd1,0x48,0x0f,0x0b,0x8b,0xb2,0x03,0x45,0x13,0xea,
+  0xdf,0xe5,0xff,0x54,0xfe,0x82,0x9f,0xd5,0x53,0xed,0x81,0x2d,0x9d,0xd3,0xe1,0x6d,
+  0x76,0x85,0xf7,0xa5,0xcf,0xd3,0xff,0x34,0x8d,0xf6,0x39,0x5b,0x16,0xf2,0xdf,0xae,
+  0x88,0x7f,0x3c,0xf9,0x5f,0x5b,0xe1,0xbc,0xf1,0x38,0x0b,0x24,0x1f,0x9e,0x06,0xcf,
+  0xf0,0x09,0x1a,0x7d,0x0a,0xfc,0xe3,0x3c,0xcf,0x40,0xc1,0x34,0x73,0x4e,0x4d,0xdd,
+  0xa8,0xaf,0x10,0xed,0xed,0x5f,0xb6,0xcd,0x32,0xf3,0x1b,0xe3,0x96,0x90,0xe0,0xfa,
+  0x7f,0x4c,0xf8,0x84,0x36,0x27,0x1e,0x6f,0x57,0xb5,0x6b,0x94,0x84,0xcc,0xa2,0x26,
+  0x78,0xfd,0x81,0xb6,0x30,0xea,0xf0,0x79,0xe2,0xda,0xa7,0xe1,0xf1,0x74,0xd5,0x1b,
+  0xbe,0x21,0x36,0x4f,0xf9,0x76,0xd7,0xcc,0xbc,0xc6,0x10,0x59,0xe1,0x82,0x97,0xff,
+  0x53,0xf4,0xbe,0x1e,0x6b,0x9a,0x5c,0x26,0x17,0xf0,0xa7,0xaa,0x1a,0xcc,0xe8,0x78,
+  0xfc,0x93,0x93,0xff,0x45,0xfc,0x9f,0x9a,0x85,0xe6,0xfd,0xed,0xd2,0x0b,0xca,0xc4,
+  0xf8,0xf0,0xa3,0xa3,0x5e,0xfe,0x4f,0xe5,0x91,0xd0,0x9b,0x08,0x7b,0x26,0x27,0xcb,
+  0x87,0xd5,0x67,0xa4,0x05,0xe6,0x04,0x8d,0x89,0xbd,0xfc,0xde,0xd6,0xab,0xb7,0x28,
+  0x93,0x28,0x8d,0xa2,0x8d,0xbd,0xa0,0xdc,0xd3,0x52,0x35,0x54,0x34,0x11,0xfe,0x71,
+  0xfb,0xad,0xeb,0xb0,0x57,0xf9,0x58,0x57,0x55,0xa6,0x9b,0xd2,0xde,0x1f,0x4e,0x5d,
+  0x77,0x25,0xbc,0x67,0x8f,0x27,0xfe,0x4f,0xe2,0x75,0xfd,0xb0,0x5a,0xcf,0x8e,0x28,
+  0x0f,0x8b,0x36,0xd6,0x13,0xac,0xb7,0x97,0xdd,0xfc,0xaf,0x82,0x73,0xf0,0x4e,0xea,
+  0xe1,0xe4,0xc6,0xbf,0x95,0xcf,0x85,0xdf,0x92,0x16,0x5c,0x09,0xff,0xb8,0xfc,0x8d,
+  0x87,0x29,0xe8,0x00,0x3f,0x4a,0x94,0x67,0xf4,0x1e,0xc3,0xda,0x86,0x94,0xf1,0xf8,
+  0xc7,0xd1,0x8f,0x15,0xef,0x88,0x07,0x92,0x4d,0xd3,0xa1,0x4f,0x8f,0x19,0xf9,0x8d,
+  0x32,0xb3,0xfb,0xbb,0xfd,0x3c,0xa2,0xff,0x29,0x8f,0xc6,0xd5,0x87,0xd8,0xa4,0xae,
+  0x47,0x8d,0x6d,0x13,0x37,0x62,0xf0,0xf2,0x7f,0xa6,0x13,0x3b,0xb1,0xa5,0x08,0xf1,
+  0x4f,0xd7,0xfa,0x09,0xe2,0x35,0x24,0x40,0x0e,0xff,0x87,0xef,0x94,0x6a,0xcd,0xeb,
+  0x28,0x3a,0xf6,0x70,0x8d,0xde,0x3a,0xae,0x11,0xc6,0x78,0xff,0xcf,0x39,0xd6,0x00,
+  0xc5,0x6b,0x65,0xdc,0x88,0x6f,0xaf,0xab,0x88,0x4e,0x84,0x7f,0x3c,0xf9,0x5f,0x95,
+  0x17,0x8c,0xdf,0x2a,0xff,0xb4,0xe8,0xbe,0x41,0xdf,0x1d,0xca,0x59,0xad,0xa1,0x65,
+  0xc2,0xfd,0xdd,0xed,0xe7,0x45,0xfd,0xbf,0xe8,0xbc,0x36,0x73,0xb0,0xb9,0x02,0x9e,
+  0xad,0x69,0x58,0x1e,0x98,0x68,0xfc,0x29,0x17,0xff,0x84,0x52,0x2a,0x81,0x9c,0x56,
+  0x2e,0xc7,0xb5,0xa1,0x48,0xad,0x4a,0xf1,0x2f,0x2d,0x0f,0xff,0xb0,0xe7,0xdc,0xf5,
+  0x96,0xed,0x7f,0xb1,0x3e,0x99,0x78,0x44,0xd9,0x6a,0x44,0x97,0xfb,0xb4,0xf0,0xf8,
+  0xf9,0x7a,0xfc,0x3f,0xf0,0x88,0x08,0x32,0x2e,0xdf,0x5c,0x76,0x4a,0xdb,0xaf,0xd4,
+  0xe6,0xc7,0x1f,0x2d,0xfc,0xe3,0xf1,0xff,0x94,0x0a,0x1a,0x73,0x6b,0x71,0x48,0x5e,
+  0xa7,0xbe,0x29,0x35,0x18,0xb5,0x13,0x3c,0x7f,0xf9,0x88,0xa7,0xff,0xcb,0x76,0x55,
+  0x94,0xfd,0xd9,0x24,0xe3,0xc1,0xb6,0xa8,0x9e,0x1a,0xe7,0x0d,0x8f,0xeb,0x08,0xef,
+  0xe2,0x7f,0x55,0x4b,0x49,0x63,0xea,0x2e,0x98,0xc9,0x65,0x3d,0x32,0x30,0x41,0x23,
+  0x12,0x21,0x24,0x3c,0xf8,0x67,0xbe,0xde,0x60,0x54,0xad,0x55,0x47,0xca,0xbf,0x0a,
+  0x9f,0xe3,0xb5,0xfc,0xfe,0x71,0xf8,0x27,0x98,0xf2,0xe6,0x7f,0x15,0x2c,0x9a,0x56,
+  0xa7,0xc5,0x4d,0x75,0x9e,0x26,0x43,0x67,0x9f,0xb0,0x3f,0xe3,0xdf,0x97,0x7b,0x3d,
+  0xfc,0x9f,0x90,0x74,0x88,0xe3,0xf9,0x65,0x30,0x71,0x97,0xfa,0x6d,0x75,0xe6,0x71,
+  0x41,0x1b,0xce,0x7f,0x7f,0xdd,0xfc,0x2f,0xe2,0xff,0x3c,0xce,0x77,0x66,0xa2,0xab,
+  0xe4,0x32,0x04,0x42,0x8d,0x99,0xc0,0x9a,0x72,0x7a,0x6d,0x73,0xf1,0xcf,0x36,0x2f,
+  0xff,0x47,0x19,0x53,0xea,0xcd,0x92,0x58,0xb5,0x98,0x9d,0xf9,0xcd,0x71,0xf6,0xa4,
+  0x24,0xed,0xa9,0x7f,0x68,0x28,0x07,0xe0,0x97,0x7c,0x76,0x26,0x30,0x36,0x6d,0x13,
+  0x3c,0xdf,0x85,0xdb,0xd6,0xd9,0x89,0xf0,0x8f,0xc3,0x3f,0xef,0x0d,0xf5,0x50,0xfd,
+  0x9f,0x23,0xea,0x20,0xd3,0xba,0x1c,0xfc,0x63,0x55,0x84,0x96,0xad,0x42,0x88,0x25,
+  0xed,0xec,0x2d,0x0f,0xff,0xa7,0x47,0xff,0x9e,0x8a,0x78,0xef,0xf6,0x44,0x1a,0x97,
+  0x06,0x0d,0x2b,0x1c,0x6f,0xaf,0xfa,0x9d,0xfa,0x06,0x71,0x65,0x3d,0xa7,0xb2,0xcf,
+  0xf8,0x5a,0x81,0xde,0xab,0xe4,0xd4,0xfb,0xb5,0x0a,0x21,0xf6,0xf9,0x62,0xde,0xfc,
+  0xaf,0x8a,0x4e,0x78,0x2b,0xb9,0x6b,0x34,0x1a,0x95,0xbb,0xcb,0xde,0x92,0x1a,0x27,
+  0xde,0xbf,0xde,0xf1,0xf0,0x7f,0x44,0xd0,0xd3,0x5c,0xba,0x4e,0x7e,0x1b,0xae,0x41,
+  0x61,0x12,0x85,0x05,0xdf,0xce,0xd3,0xcf,0xeb,0x1e,0xfe,0xcf,0x76,0x2a,0xe2,0x61,
+  0x04,0x4c,0x79,0xbe,0x71,0x5c,0xc9,0x36,0x36,0x72,0x1a,0x3f,0xfd,0xda,0xc6,0x03,
+  0xf6,0xf3,0x6f,0x55,0x56,0x40,0x6a,0x7d,0x64,0xc4,0x77,0x2f,0xfb,0x21,0x55,0xb3,
+  0x99,0x18,0xcf,0x78,0xfb,0x9f,0x86,0x81,0xda,0x40,0xa8,0xbd,0xac,0x57,0xef,0x36,
+  0xb3,0x6e,0x9f,0x1f,0xe4,0x8e,0x2f,0xcc,0x78,0xf8,0x3f,0x61,0x78,0x14,0x22,0xd4,
+  0xed,0xbd,0x97,0xf1,0xec,0xf9,0x54,0x72,0x1b,0x85,0x8c,0xc7,0x3f,0x71,0xa2,0x55,
+  0x18,0x1b,0x29,0xda,0x3e,0x60,0xbb,0x7d,0x9c,0xf9,0x66,0x05,0x4f,0xfe,0x57,0xe5,
+  0x28,0xed,0xef,0x7d,0x41,0x53,0x1e,0x85,0xaf,0x5d,0x11,0xff,0xe4,0xf1,0x7f,0x88,
+  0x2d,0xc6,0xa8,0x6c,0x42,0xe3,0x70,0xc9,0x98,0x5c,0x9f,0xfa,0x5d,0xfe,0x9f,0x2c,
+  0xc8,0xe9,0x45,0x90,0xfc,0x72,0xa2,0x76,0xa0,0x3b,0xcd,0x3e,0x2e,0xae,0x04,0x3d,
+  0xf8,0x27,0xe3,0xac,0x9f,0x2c,0xff,0x87,0xd8,0x4d,0xc7,0x85,0xff,0x27,0x42,0x85,
+  0xaf,0x3d,0xeb,0x21,0x62,0xf9,0x7f,0xec,0xf1,0x66,0xe5,0xe9,0x0a,0xa1,0xb4,0x94,
+  0xe0,0xcf,0x50,0xda,0xb2,0x4f,0x30,0x6a,0xfa,0x7c,0x13,0xe2,0x1f,0xa5,0x32,0xbb,
+  0x48,0x52,0x72,0xc6,0xdc,0x80,0xc2,0x92,0x98,0xbf,0xd6,0xa0,0xb0,0x8b,0xdf,0x8b,
+  0x0f,0x73,0xfa,0xbf,0x0b,0x25,0x64,0xe4,0xf7,0xec,0xfe,0x20,0x63,0xe3,0xf1,0x8f,
+  0xb7,0xff,0x7b,0xc5,0x79,0x98,0x6a,0x06,0xb7,0xfe,0x74,0x44,0x13,0xfd,0x1d,0x76,
+  0xb9,0x8d,0x5a,0x1c,0xc1,0xf5,0xff,0x64,0xf3,0xbf,0x28,0xfb,0xef,0x19,0xbe,0x01,
+  0x28,0x1a,0x78,0x2f,0x5d,0x59,0x80,0xcf,0xe3,0x8b,0xba,0xfe,0x1f,0x7b,0x3d,0x64,
+  0xf9,0x3f,0xa6,0xbf,0x86,0x1d,0xe7,0x9d,0x52,0x74,0x08,0x8f,0xc1,0x8a,0xad,0x1f,
+  0x47,0x51,0xde,0xf8,0x97,0xc5,0xfe,0xf5,0xaf,0x62,0xe7,0xec,0xb6,0xa7,0xd7,0x40,
+  0xb6,0xfe,0xcf,0x54,0x07,0x0f,0x78,0xe3,0x5f,0x56,0xff,0x2f,0xd2,0xbf,0xe8,0x7f,
+  0xb1,0x53,0x56,0x6c,0xd8,0x13,0xb0,0x81,0xd0,0x4b,0x4e,0xfc,0xdd,0x98,0x92,0xcd,
+  0x8f,0xcb,0xc8,0xaf,0x58,0x61,0xaf,0x77,0xed,0x42,0x9a,0xed,0x1e,0xff,0x8f,0xa3,
+  0x1f,0xa7,0xfe,0x73,0x4a,0x3e,0x95,0xca,0x46,0x03,0x6b,0xc6,0xe3,0x1f,0xe7,0x7d,
+  0x74,0xea,0x3f,0xc7,0xd9,0x20,0xdc,0x43,0xec,0xb5,0x51,0xb7,0xfe,0xe1,0x2b,0xb6,
+  0xfd,0x79,0xc9,0xf1,0x3f,0x2f,0xb2,0xeb,0x3f,0xaf,0x2a,0xfc,0x99,0xf6,0x6d,0x2b,
+  0xba,0x77,0xd5,0x38,0xfc,0xd3,0x3d,0xbe,0xfe,0xb3,0x5e,0xf8,0x9c,0x41,0x6d,0x07,
+  0x23,0x69,0x57,0x8d,0xd6,0xfb,0xe5,0x8b,0x95,0x79,0xf9,0xcf,0xbd,0xaa,0x00,0x39,
+  0x71,0xe2,0x3f,0x8b,0xc2,0x23,0xfe,0xf9,0xe3,0xf1,0x8f,0x37,0xff,0xcb,0x42,0x3b,
+  0x5d,0xec,0x75,0x7d,0x08,0x16,0x68,0x56,0xdb,0x0b,0xef,0x7e,0x54,0xc2,0xe5,0x71,
+  0xf9,0x5f,0xb4,0xdf,0x45,0x35,0x4a,0x03,0x0f,0x24,0xfd,0x35,0x76,0xfd,0x1f,0xf7,
+  0xbc,0x9f,0x5f,0xff,0x99,0x76,0xdb,0x69,0x24,0xac,0x89,0x6c,0x0e,0x13,0xff,0x76,
+  0x41,0x0e,0xfe,0x19,0xdf,0xff,0xcb,0x8f,0xf8,0x4a,0x17,0x8d,0xc0,0x92,0x89,0x1a,
+  0xc8,0x77,0x04,0x1d,0x19,0xd7,0xff,0x1d,0x57,0xa3,0x62,0xa7,0x7d,0x91,0x23,0x28,
+  0x92,0x87,0x7f,0xec,0xe7,0x19,0x0b,0xd8,0xd9,0xd6,0x8c,0x84,0xfa,0x8a,0xe8,0x5a,
+  0x59,0xcf,0x75,0x44,0xa0,0xf0,0x81,0x13,0xff,0xea,0x16,0xfd,0xbf,0xa6,0x12,0x7b,
+  0xb9,0xdf,0x8e,0xee,0x79,0xe3,0x5f,0xd6,0x46,0x7f,0x32,0x27,0xff,0xfd,0x45,0x8b,
+  0x06,0x3c,0x17,0xa8,0x4d,0x6a,0xe0,0x27,0x76,0x7f,0x58,0x4f,0x21,0xe8,0xdc,0xfe,
+  0xef,0xfb,0xe0,0x4b,0xe4,0xe4,0xd1,0x09,0xed,0x44,0x54,0xee,0xd3,0x8d,0x7c,0xfc,
+  0x73,0xc4,0xeb,0xff,0x29,0xcd,0xb2,0xbb,0xbb,0xac,0x68,0x57,0xd9,0x2d,0x85,0xea,
+  0x4e,0x91,0x91,0x9a,0x9d,0xaf,0x8f,0xf0,0x8f,0x3d,0x3e,0xcb,0xff,0xa1,0x22,0x48,
+  0x96,0xa0,0x26,0x7d,0x35,0xe3,0xf0,0xe7,0x29,0xe7,0x79,0x52,0xdf,0xa2,0xe7,0xc7,
+  0x49,0x69,0xd2,0xbf,0x0b,0x5a,0x7b,0x54,0xb3,0x9f,0xdf,0xfe,0x7d,0x4b,0xe8,0xf7,
+  0xb2,0xf5,0xe9,0xd4,0x7f,0x4e,0x3f,0x5c,0x93,0x5b,0xff,0xc7,0xeb,0x28,0xfb,0x69,
+  0x6e,0xfe,0x97,0x57,0xdb,0x81,0x6e,0xa7,0xfe,0xb3,0xab,0xff,0x5c,0xfe,0xb3,0x40,
+  0x3b,0xdb,0x18,0xb1,0x9d,0x67,0xf1,0x4f,0xd9,0xfd,0x4f,0xaf,0xcd,0xb8,0x40,0xc8,
+  0x13,0xff,0x52,0x96,0xc0,0x1c,0xeb,0xed,0x38,0x1a,0xb7,0x1a,0x13,0x64,0xdf,0x97,
+  0x0d,0xba,0x67,0x3f,0x72,0xfb,0xbf,0xc3,0x67,0xdd,0xf7,0x97,0x0a,0x41,0x4b,0x4e,
+  0x63,0xac,0xb8,0x37,0x1e,0x64,0x8f,0xa7,0xfc,0xaf,0x2c,0xda,0xf9,0x19,0xa1,0x9d,
+  0x78,0x60,0xcc,0x9f,0xad,0xff,0xbc,0x0a,0xdf,0xdf,0xdf,0x52,0xff,0xd3,0x35,0xe5,
+  0x87,0x73,0xf2,0xdf,0xcf,0x5b,0x66,0x96,0xd8,0xad,0x0d,0x49,0xcb,0x8c,0x28,0xc2,
+  0xc2,0x4c,0xe0,0xff,0xc9,0xf6,0xaf,0xcc,0x04,0x5f,0x61,0xe7,0x8c,0xcb,0xc9,0xc6,
+  0xd1,0xc0,0x98,0x7c,0x08,0xb2,0xfc,0x67,0xa7,0x10,0xf4,0x90,0xa3,0xff,0x47,0x25,
+  0x91,0xff,0x25,0xaa,0x37,0x13,0x11,0xc8,0x50,0xbf,0xc2,0xb2,0x8d,0x78,0xe2,0x92,
+  0x93,0x88,0x71,0xd2,0x13,0xff,0xda,0x62,0x3b,0x85,0x86,0x2a,0xf6,0x2a,0x33,0xe3,
+  0xaa,0xdd,0xaf,0x19,0xe7,0xeb,0x8c,0x37,0xed,0xe1,0xa2,0xfe,0xb3,0xa3,0x34,0x62,
+  0xb3,0x40,0xcc,0x57,0x0c,0x59,0x7e,0xef,0x12,0x69,0x5c,0xfc,0x6b,0xcc,0xde,0xbf,
+  0x38,0x7b,0x5b,0x08,0xd1,0xb4,0xfc,0x1f,0x16,0xff,0x39,0x95,0xdd,0x5f,0xfc,0x39,
+  0xf1,0x2f,0x29,0xab,0x9f,0x3d,0xf2,0x88,0x99,0xad,0x27,0xff,0x9c,0x6d,0x81,0x9d,
+  0x52,0xfc,0xde,0xfe,0xef,0x07,0xad,0x30,0xc7,0x98,0xdc,0x40,0x86,0xdd,0x08,0x8c,
+  0xca,0xab,0x75,0xe2,0x3f,0xfb,0x33,0x13,0xc5,0xbf,0x9c,0xfe,0x5f,0xf3,0x13,0x7f,
+  0x2b,0xf2,0x97,0xbb,0x27,0xdb,0xf5,0x0c,0x53,0x13,0xe3,0x9f,0xec,0xa6,0xf6,0x40,
+  0xd3,0x2a,0x6a,0x7c,0x70,0x58,0xdd,0x27,0x02,0x61,0xce,0xf8,0x2f,0xe5,0xc7,0xbf,
+  0x28,0xff,0x8b,0xaa,0x61,0x5f,0xd3,0x2a,0x0a,0x71,0x44,0xb4,0x6c,0xff,0xd3,0x6b,
+  0xf5,0x09,0xf1,0xcf,0xbf,0xae,0xb6,0x27,0x45,0x69,0xef,0x68,0x1f,0xec,0xfc,0x26,
+  0xbf,0x67,0x3d,0xe4,0xf7,0xff,0xca,0x56,0xb3,0x11,0x82,0x61,0x4f,0x33,0x9e,0x15,
+  0x26,0x21,0xfe,0x71,0xe3,0x4d,0x05,0x1f,0xc0,0x71,0x3e,0x3b,0x15,0x58,0x25,0xcf,
+  0x6b,0xb9,0xb0,0x79,0xce,0x15,0xe2,0x5f,0xcc,0xc5,0x3f,0xa7,0xd8,0xbd,0x3c,0x9c,
+  0x52,0x7b,0x7d,0x35,0xc9,0x03,0x55,0xe1,0x71,0xf1,0x2f,0x21,0xb4,0x7b,0xf2,0xdf,
+  0x87,0xa9,0x0d,0x0a,0x8f,0xa4,0x98,0xa2,0x7e,0x1f,0xe2,0x56,0xfe,0xfb,0xef,0xf0,
+  0xff,0x54,0x6e,0x37,0xd6,0x53,0xff,0xaf,0xde,0x70,0x8d,0x76,0xa0,0xdb,0xc1,0x9f,
+  0x9e,0x78,0xe2,0x86,0x34,0x5b,0xe3,0xe1,0xff,0x3c,0x07,0x78,0x66,0x49,0x05,0x66,
+  0xc8,0x55,0xc6,0x39,0x63,0xd7,0xc4,0xf8,0x79,0xc0,0x89,0x67,0x65,0xa4,0x3d,0x70,
+  0x21,0xd5,0xc8,0x83,0x99,0xea,0x33,0xca,0xd7,0x7f,0x7f,0xfc,0xab,0x4d,0xc3,0xf3,
+  0x48,0x59,0x5d,0x4f,0xf1,0x23,0x72,0x55,0x7e,0xff,0x0b,0x47,0x28,0x7f,0xc1,0xe3,
+  0xff,0xf9,0x18,0x15,0xa1,0xdd,0xa6,0xee,0x28,0x9b,0x0e,0xbb,0xf9,0x95,0xe2,0x5f,
+  0x0e,0x7f,0x3b,0x53,0xd0,0xc2,0xd3,0xbc,0x26,0x5d,0x74,0x3d,0x6b,0xe6,0xbb,0xb4,
+  0xd5,0xe6,0x84,0xfe,0x31,0x17,0xff,0xec,0x93,0xae,0x6a,0x79,0x7c,0xf0,0x63,0xba,
+  0xfa,0x37,0xec,0xcf,0xe1,0x71,0xf3,0x8b,0x13,0xfb,0x43,0x2e,0x39,0xe3,0x5b,0x55,
+  0x45,0x1f,0xd5,0xe6,0xf2,0xe2,0x2a,0x79,0x51,0xfc,0xbd,0x89,0xe2,0x5f,0x54,0x1a,
+  0xe8,0x25,0x67,0xbc,0x31,0x65,0x8f,0xf4,0x1b,0xed,0xa6,0xae,0xe0,0xeb,0xc1,0x7d,
+  0x76,0x21,0x20,0x52,0xcb,0x37,0x6c,0xfd,0x7c,0xc3,0xc2,0x3f,0xf6,0x7c,0x7b,0xf1,
+  0xf7,0x1d,0x80,0x18,0x0f,0xc4,0x64,0x5d,0xbb,0x92,0x7e,0xf2,0xf8,0x3f,0x3f,0xa3,
+  0xf8,0x97,0x81,0xb0,0xe7,0x71,0xc9,0x81,0x3d,0x37,0x5e,0x91,0xff,0xf3,0xcf,0xb0,
+  0x91,0x57,0xa5,0xae,0x59,0xb5,0xad,0x6c,0x5c,0xff,0x0b,0x47,0xc8,0xe5,0xff,0x24,
+  0xb9,0x6e,0xfa,0x22,0x33,0x54,0x1d,0x8f,0x55,0xb6,0x1a,0x23,0x39,0xfa,0xcc,0xc1,
+  0x3f,0x70,0xa4,0x7b,0xf7,0x96,0xdb,0x32,0xf2,0x8d,0x70,0xc9,0x6c,0x98,0xd8,0xff,
+  0xf3,0xbe,0x37,0xfe,0x65,0x8c,0xc5,0x1b,0xe0,0xba,0x2c,0xfb,0xd4,0xe9,0x07,0x7a,
+  0x25,0xfe,0x8f,0x76,0x8a,0x1f,0xe5,0xf3,0x8c,0x25,0x49,0x79,0x3a,0x0a,0x57,0x88,
+  0x77,0xe4,0xf2,0x7f,0xd6,0xb7,0xea,0x71,0x84,0x25,0xeb,0xd4,0xf5,0x83,0x57,0x8c,
+  0x7f,0xd9,0x1f,0xc2,0x3f,0xeb,0xcb,0xb6,0x65,0xd4,0x64,0xd9,0xca,0xd9,0x7f,0x50,
+  0xfc,0x2b,0x20,0xda,0x84,0xa9,0xb1,0xa6,0xfe,0xdf,0x11,0x0f,0x72,0xd7,0x1b,0x9e,
+  0xbf,0x44,0xfc,0x85,0x37,0xdf,0xd9,0x74,0xac,0xed,0x0a,0xf1,0xaf,0x0f,0x9c,0xfd,
+  0x6e,0x60,0xca,0x0b,0xec,0x37,0x4a,0xa3,0x39,0x6b,0x90,0xba,0x5d,0x5c,0x29,0xbe,
+  0x73,0xd2,0xa9,0xff,0x1c,0x2a,0xe8,0x07,0x51,0x8f,0x7d,0x50,0xbe,0x1e,0xae,0x18,
+  0xff,0x3a,0xe9,0xd8,0x9f,0x35,0xd9,0xfa,0x3f,0x7e,0x1e,0xd6,0xf9,0xb1,0x48,0xad,
+  0x45,0xc3,0xf6,0xe0,0x9f,0x05,0x02,0xff,0x78,0xf8,0x3f,0xd9,0x49,0xc5,0x10,0xc6,
+  0x5c,0x69,0xbe,0x65,0x2f,0x49,0xf6,0x78,0xea,0xff,0xfe,0x28,0x45,0xbb,0xf6,0x30,
+  0x07,0x46,0x5a,0x40,0xa8,0xc8,0x69,0x2c,0x9b,0x64,0xef,0x38,0x7c,0x57,0xc1,0x7f,
+  0x4e,0x35,0xb4,0x07,0x2b,0x64,0x85,0x5d,0xf1,0xf7,0xf5,0xe0,0x1f,0xd8,0xa1,0xbe,
+  0x69,0x34,0x2c,0x0b,0x6e,0xea,0x1c,0x86,0x37,0x53,0x59,0x1a,0x7c,0xfe,0x78,0x6f,
+  0xff,0x77,0x71,0xec,0xd5,0x96,0x72,0xbf,0x0e,0x43,0x79,0x8d,0x30,0x5c,0xfc,0xe3,
+  0x8e,0x57,0x66,0xb0,0xfb,0x32,0x1f,0x4f,0xcb,0xc3,0xec,0x46,0xe3,0x3e,0x33,0x6c,
+  0xd1,0x9e,0x09,0xf6,0x14,0xd9,0xfe,0x9f,0x0d,0x88,0x7f,0x6a,0xec,0xdf,0x37,0x52,
+  0xf0,0x29,0xde,0xd9,0xaa,0x27,0x3b,0xe7,0x96,0x7d,0xaa,0xe5,0xc1,0x98,0x62,0x9f,
+  0xc7,0x3d,0xf6,0x47,0xf6,0xf2,0x51,0x75,0xe9,0xa3,0x78,0xec,0xba,0x2e,0x89,0x2f,
+  0xe9,0x67,0x61,0xad,0x55,0xed,0xf0,0xb3,0xe3,0xe2,0x5f,0x6e,0x3d,0xbd,0x48,0xf7,
+  0x54,0xf8,0x31,0x9f,0x4d,0x24,0xe7,0xaf,0xc3,0x6b,0x5d,0xd7,0xbf,0x3e,0x61,0xfc,
+  0xeb,0xb0,0x3d,0x9c,0xf0,0x4f,0xea,0x7d,0x9a,0x54,0xac,0x7c,0x07,0x69,0xc3,0xb4,
+  0x69,0xcf,0x66,0x71,0x8e,0x3d,0xb1,0xdf,0x47,0x43,0xf4,0xbf,0x98,0x93,0x8a,0x8e,
+  0x95,0x7f,0xa0,0x7a,0x69,0xab,0xb9,0xfe,0x1f,0xa7,0xff,0xd7,0xf7,0x4b,0x37,0x67,
+  0x1e,0xa3,0x26,0x17,0x6d,0xec,0x05,0xbe,0x57,0xab,0xea,0xcf,0x8b,0x67,0x29,0xc2,
+  0x10,0xbd,0xed,0xc6,0x17,0x60,0x8b,0xf6,0x18,0x54,0x83,0xda,0x9e,0x78,0x01,0xfe,
+  0x33,0x8f,0x26,0xe4,0x08,0xa7,0x73,0xf8,0x3f,0xbb,0xf1,0xbf,0xd4,0x50,0xa2,0x9f,
+  0xef,0xfc,0x64,0x7c,0x9c,0x3d,0x17,0x86,0xc8,0xc5,0xb7,0xbd,0x95,0x3f,0x84,0xf7,
+  0x43,0x75,0x89,0x8d,0x15,0xf2,0xb3,0x70,0x3e,0x75,0x85,0xf8,0x8e,0x9b,0x6f,0x48,
+  0xf1,0xaf,0xb3,0x46,0xc3,0xa6,0xe0,0x66,0x79,0xb8,0xed,0xec,0x04,0xf6,0x96,0x3a,
+  0x20,0x54,0xbb,0xf1,0x38,0xea,0x7f,0xfa,0x1c,0xcc,0xa9,0x09,0x0c,0xca,0xf3,0xdc,
+  0xfc,0xf7,0xfc,0xfd,0x2e,0x13,0x77,0xee,0x4f,0xfc,0x9f,0x44,0x44,0x53,0x7b,0xa8,
+  0xfe,0xea,0x15,0xf8,0x1b,0x65,0xde,0xfa,0x87,0xab,0xf9,0x86,0xee,0xe9,0x87,0x71,
+  0x7c,0x34,0x7e,0xa5,0xf1,0xde,0xf8,0x17,0x04,0xf0,0x35,0xac,0xe5,0x68,0xdf,0x6a,
+  0x28,0x0d,0xf3,0x0a,0xf1,0x2f,0x70,0xff,0x60,0x35,0x1c,0x65,0x64,0x3f,0xad,0x63,
+  0xe3,0xc4,0xfa,0x71,0xfd,0xe1,0x84,0x7f,0x7e,0xc3,0x6e,0x84,0xfb,0x07,0xe5,0x51,
+  0x2a,0x84,0x38,0xe1,0x7c,0xcb,0x33,0xae,0xff,0xa7,0xc0,0xb3,0x5a,0x50,0x3f,0x24,
+  0x4c,0x85,0xa7,0x79,0xe3,0x00,0x0a,0xf3,0xec,0x44,0xb0,0x09,0xfc,0x3f,0x84,0x76,
+  0x36,0x98,0xb5,0x99,0x5b,0x29,0xed,0x7d,0x03,0xaf,0x1d,0xc6,0x2b,0xd3,0xc5,0x57,
+  0xc4,0x88,0xf6,0xe0,0x01,0xcf,0xec,0x3a,0x8c,0x28,0xe5,0xb3,0x0b,0xbc,0xc7,0xf1,
+  0x8a,0xe5,0xe8,0x28,0xca,0xf5,0xff,0x50,0xfe,0xbb,0xa5,0x3d,0x86,0xf6,0xe7,0xe8,
+  0x86,0x9d,0x74,0x7f,0x2a,0x64,0x41,0x89,0x78,0x4f,0x58,0xad,0x45,0x47,0xdd,0xfe,
+  0x2c,0x95,0x8e,0x12,0x8e,0xc3,0x33,0xc9,0x06,0xab,0x3f,0xe9,0x33,0x5a,0x43,0xbf,
+  0x68,0x54,0x91,0x7d,0x71,0x4c,0x0f,0xfe,0x39,0xe8,0x6a,0xe3,0xbc,0x35,0x5f,0x54,
+  0x0b,0x6b,0xc8,0x04,0x47,0xdd,0x8a,0x01,0xa3,0x79,0xf5,0x9f,0x9d,0x6c,0xaf,0xac,
+  0xff,0xed,0x19,0x22,0xca,0x66,0x0b,0x1d,0x1f,0xc6,0x2b,0x43,0x9e,0xf9,0x46,0xdd,
+  0x5f,0x7f,0x3f,0x0b,0xf7,0x95,0xa4,0x9b,0x8e,0x13,0x31,0x8c,0xab,0xf3,0xc5,0x7a,
+  0x20,0xe8,0xcb,0xce,0x39,0x3f,0xaf,0xe3,0xff,0xb1,0xdc,0xa4,0x56,0xbd,0x62,0x89,
+  0x88,0x2b,0x91,0xd9,0x56,0x21,0xe8,0x17,0x26,0xf6,0xff,0x58,0xbb,0x7f,0x55,0xe6,
+  0xde,0x35,0xec,0x35,0xd1,0xf6,0x5d,0xfd,0x9a,0x5b,0x18,0xd9,0x74,0xc6,0xb7,0xaa,
+  0x01,0x75,0xb7,0x8b,0x76,0xe6,0x12,0xda,0x39,0xae,0x3c,0x05,0xe9,0x41,0x91,0x11,
+  0x66,0xf3,0x7f,0x5c,0xfe,0xf3,0xa7,0x0e,0x8e,0x7b,0x3b,0x2e,0xb4,0x5e,0xd6,0x1a,
+  0x5b,0x6c,0xfd,0xf4,0x0b,0xfe,0x8f,0xf3,0xfe,0x16,0xe4,0xae,0x46,0xe3,0x9e,0x74,
+  0xf3,0x29,0xc2,0xe7,0x99,0x80,0xa7,0x10,0xb4,0x6b,0x9f,0x89,0xff,0x63,0x5b,0x0f,
+  0x75,0x2f,0xcb,0x36,0x92,0xbe,0x07,0xb7,0x21,0xf0,0x14,0x82,0x3e,0xe1,0xd6,0xff,
+  0xf4,0xf6,0xff,0x42,0xe1,0xa4,0x40,0x77,0xf7,0x58,0x81,0xbf,0x9f,0x4d,0x84,0x7f,
+  0xf2,0xdf,0xa6,0x1b,0xcb,0x84,0xe3,0x31,0x27,0xb1,0xce,0xf5,0xcf,0x58,0xf9,0x5f,
+  0x2e,0xda,0x49,0x05,0x7b,0x89,0x08,0xcd,0x1b,0x89,0x08,0xfd,0x96,0x9e,0xfd,0xca,
+  0xc5,0xe7,0x6e,0xfd,0x1f,0xd9,0xdb,0x08,0x4c,0x6b,0xc0,0xa3,0xb6,0xb8,0x52,0x9b,
+  0x8f,0x7f,0xc6,0xef,0x86,0x56,0xbf,0xa7,0xe0,0x77,0x3c,0xf1,0x2f,0xd7,0xbe,0x39,
+  0xfe,0x9f,0xb0,0x40,0x2f,0x8b,0x5c,0xfe,0x49,0x8f,0x85,0x67,0x56,0x8e,0xc3,0x3f,
+  0x79,0x68,0xa7,0xe9,0xd4,0xef,0xe5,0xff,0x38,0xdd,0x2e,0x5c,0x18,0xd0,0x9a,0x83,
+  0x7f,0x72,0xf2,0xdf,0xdd,0xb2,0x33,0x57,0xe2,0xff,0x7c,0x90,0xc3,0xff,0x71,0xcb,
+  0xf8,0x50,0xb5,0xc3,0x41,0x3c,0x1d,0x64,0x13,0xc1,0x1c,0x62,0xb3,0x37,0xfe,0x95,
+  0xa3,0x9f,0xba,0x45,0x1b,0x5d,0xda,0x70,0x98,0xf8,0xcf,0x8d,0x96,0x7e,0xec,0xf3,
+  0x94,0xf0,0xff,0x48,0x9e,0x6c,0x2f,0x95,0x97,0x59,0x6e,0x1f,0xd5,0xf4,0xf8,0x7f,
+  0xc6,0xd5,0xff,0x11,0xb3,0xdb,0x6b,0x50,0xe3,0x95,0x26,0xb1,0xcc,0x06,0x59,0x9b,
+  0x3b,0x5f,0x2f,0xfe,0x41,0xb4,0x23,0x67,0xb5,0xf7,0x9f,0x50,0x1d,0x5f,0x35,0xc4,
+  0xce,0xa0,0x30,0xcb,0x98,0x31,0xe8,0xea,0xf3,0x1d,0x6f,0xfd,0x1f,0x6f,0x3f,0x2f,
+  0x91,0xdf,0x77,0x8a,0x1a,0x9f,0x2d,0x2b,0xf1,0xf8,0xbb,0x32,0xb9,0xf5,0x9f,0x9d,
+  0xec,0x30,0xdd,0x2a,0x13,0x8d,0x7f,0x58,0x6f,0x7c,0x2a,0x29,0x3b,0x15,0xa1,0x4f,
+  0x38,0xbf,0xd7,0x38,0xff,0x0f,0xf5,0xdb,0x25,0x41,0x2b,0x36,0x27,0xc4,0x3f,0x59,
+  0xff,0xcf,0xb5,0x59,0xb4,0x63,0xd5,0xff,0x39,0xc7,0x9c,0xf8,0xd7,0xac,0x54,0x30,
+  0x97,0xff,0x6c,0xd9,0x9f,0x0d,0xf6,0xdb,0x71,0x6b,0xac,0x29,0x0b,0x7b,0xb2,0xe7,
+  0xf1,0x44,0x91,0x77,0x3f,0x4a,0xb9,0x4e,0x12,0x7b,0xf7,0x6f,0x1a,0x52,0x45,0x3d,
+  0xc0,0xac,0xff,0x47,0xc3,0xaf,0x06,0x5a,0xec,0xf1,0xbd,0xaa,0xe5,0xed,0xb9,0xd5,
+  0x46,0x3b,0xf7,0x93,0x23,0x68,0x6f,0x02,0x61,0x4f,0xab,0x75,0x25,0x55,0x4c,0xfc,
+  0x67,0xe7,0x7d,0x99,0xe2,0xb1,0xb7,0x56,0x7d,0x9b,0xea,0x8c,0x95,0xff,0xce,0x2d,
+  0x0b,0xc3,0x4b,0xbc,0xf1,0xf4,0x6c,0xfe,0x57,0xc6,0x7f,0x56,0x64,0x7b,0xcd,0x59,
+  0x19,0x18,0x62,0x0d,0xad,0x17,0x79,0x79,0x3c,0x30,0x22,0x0a,0x41,0x37,0xc6,0x09,
+  0xff,0x38,0xe7,0xa9,0xde,0xd2,0x2d,0xca,0xde,0x6c,0xd9,0x1f,0x78,0x8c,0x55,0x19,
+  0xea,0xed,0x78,0x10,0x13,0x02,0x3e,0xbf,0xfe,0x3d,0xab,0xfe,0xea,0x49,0x2f,0xfe,
+  0x71,0xbb,0x83,0x21,0x70,0x32,0x80,0x0a,0x47,0x93,0xa0,0xb6,0x5a,0x85,0xa0,0x0d,
+  0x8a,0xf7,0xb9,0xf1,0x2f,0xcb,0xfe,0xf4,0xdd,0x6a,0x65,0xcf,0xc5,0x8d,0x1e,0x8d,
+  0x81,0x60,0xdc,0xa9,0xc0,0x9e,0xa3,0xc2,0xb6,0xf0,0x9d,0xd8,0x32,0x6f,0xfe,0xc8,
+  0x0e,0xdc,0x14,0xa6,0x0a,0xa7,0x0d,0xbc,0x47,0x07,0x49,0x5d,0xae,0x85,0xbb,0x21,
+  0xb6,0x2d,0x60,0x6d,0x34,0x0d,0xfc,0xfe,0xb4,0x7c,0xd2,0x83,0x7f,0x1c,0x7b,0x6b,
+  0xd9,0xab,0xa5,0x68,0xaf,0x0c,0x51,0xaf,0x3e,0x5b,0xff,0x50,0x2b,0x49,0x7b,0xea,
+  0x3f,0x73,0xcd,0x43,0xea,0xb8,0x04,0x73,0x78,0x20,0x23,0xcf,0xb5,0x84,0xc1,0x6c,
+  0x3d,0xc0,0xc0,0xa8,0x67,0x7f,0xe4,0xb6,0xff,0x27,0xcd,0xde,0xe4,0x56,0x21,0x71,
+  0xa6,0x2b,0x42,0xb0,0x1a,0x7b,0x89,0xd2,0x6a,0x39,0xf5,0x9f,0x1d,0xa7,0x50,0xf6,
+  0x7d,0x64,0x51,0x4b,0xd8,0x63,0xe1,0x1f,0x45,0x4d,0x7b,0xfc,0xd5,0x8e,0xff,0x27,
+  0x56,0x36,0xa0,0xa4,0xb9,0xae,0xab,0x2a,0x53,0xa9,0xed,0xbb,0xde,0x9a,0x5d,0x78,
+  0xd0,0x1d,0x63,0xc7,0xbc,0xfd,0x2f,0x4a,0x9d,0xf9,0x66,0x0b,0xa1,0xd7,0xc0,0x18,
+  0x43,0x21,0xcb,0x90,0x07,0x54,0x94,0xe9,0xae,0xcf,0x29,0x9e,0xf9,0x9e,0xa1,0x42,
+  0x88,0x86,0x00,0x42,0x0b,0x25,0x3c,0x61,0xbd,0x62,0xa5,0x86,0x21,0xde,0x83,0xf1,
+  0xf8,0xa7,0xb9,0x01,0x2e,0x26,0x45,0xb6,0xd7,0x04,0xfe,0x1f,0x37,0xfe,0x18,0x72,
+  0xf0,0x4f,0xad,0xf2,0x84,0x2e,0xb2,0xbd,0xac,0x2b,0x25,0x1e,0xff,0xcf,0x58,0x6e,
+  0xfd,0x1f,0x58,0x6d,0x5e,0x1b,0xf3,0x6d,0xb4,0xcb,0x5c,0xe3,0x15,0x25,0xcf,0xff,
+  0xe3,0xf1,0x47,0xed,0x10,0xfa,0xbc,0x36,0xcd,0x50,0xe8,0xbe,0x02,0x9e,0x74,0xf9,
+  0x39,0x50,0x9a,0x5d,0x0f,0xb1,0xe6,0x1d,0x76,0x19,0xf0,0x09,0xf8,0x51,0x39,0xfc,
+  0x67,0x4b,0x3f,0xcd,0x5f,0xcb,0xe5,0x3f,0x97,0x5c,0x91,0xff,0xec,0x44,0xbb,0x26,
+  0xe0,0x9b,0x09,0xbc,0x2d,0x7b,0xea,0x3f,0x53,0x3d,0x28,0xa9,0xd6,0x94,0xd3,0xd2,
+  0x97,0x6a,0x0e,0xc4,0xad,0xc7,0x56,0xf2,0x9e,0x1f,0xcf,0xcb,0xf6,0xc7,0x54,0x84,
+  0x53,0xb4,0x4f,0xc6,0x1f,0x14,0x76,0xeb,0xe3,0xf1,0x70,0xc4,0xf2,0xff,0xd8,0xfe,
+  0x3d,0xab,0xfe,0x8f,0xd8,0xf4,0x3f,0x67,0xe4,0xbb,0x41,0x5e,0x95,0x6c,0xfe,0x8f,
+  0x87,0xff,0xbc,0xc4,0x70,0xa3,0x5d,0x15,0xc2,0xdb,0x83,0x40,0xa8,0x22,0x9a,0x45,
+  0x44,0xda,0x7c,0x11,0xff,0x72,0xf9,0xcf,0x95,0xd9,0xf8,0xd7,0x5d,0xcd,0x17,0x0a,
+  0x10,0xf6,0x3c,0x6d,0xe9,0x47,0xb1,0x15,0x65,0x09,0x49,0xc7,0xff,0xac,0xba,0xf8,
+  0xe7,0x39,0x78,0xe6,0x4a,0xf8,0xfc,0xa4,0xcb,0x7f,0xb8,0x7a,0x8b,0x5d,0x2d,0xff,
+  0x15,0x51,0x4f,0x23,0x6b,0x48,0xbf,0x98,0xeb,0xff,0x71,0xce,0x77,0xba,0x17,0xff,
+  0x7c,0xaf,0x43,0x94,0xfd,0x19,0xef,0xff,0x71,0xdf,0x77,0xab,0xfe,0x4f,0x56,0x7b,
+  0x0f,0x53,0x3c,0x7a,0xdc,0x79,0xd6,0x9f,0x5b,0xff,0xd0,0xf5,0xf6,0xa8,0xef,0xe8,
+  0x57,0xf0,0xff,0x78,0xf8,0xcf,0xd9,0xfa,0x3f,0x44,0x7b,0x66,0x3d,0x6a,0xed,0xc4,
+  0x78,0xc0,0xcb,0x7f,0xce,0xee,0x77,0x9b,0x9b,0x71,0x9b,0xdb,0x56,0x67,0x4c,0xc8,
+  0x6f,0xc9,0xe3,0x3f,0xdb,0xe8,0x65,0xa7,0x39,0x2e,0xff,0x7d,0x3c,0xff,0x27,0x07,
+  0xff,0x4c,0xcc,0xff,0xf1,0xe0,0x1f,0x51,0xff,0xc7,0xaa,0x36,0x46,0x85,0x91,0x53,
+  0x6e,0x18,0x28,0x07,0xff,0x38,0xf6,0x67,0x5f,0x4e,0xff,0xd3,0xb6,0xba,0x8a,0x09,
+  0xf9,0x27,0xef,0x38,0xeb,0xa7,0xc7,0x8b,0x07,0x2e,0x2a,0x13,0xfb,0x43,0xca,0xdd,
+  0xfe,0x5f,0x0e,0xfe,0x19,0x14,0x6d,0x32,0xea,0xda,0xee,0x9f,0xd0,0xff,0xe3,0xd6,
+  0x3f,0x0c,0x65,0x54,0x0b,0xe4,0x34,0x11,0xda,0xd9,0xa6,0x4e,0xc4,0x7f,0xc6,0x8d,
+  0x26,0xa7,0xfe,0x0f,0x44,0x17,0x5d,0x4b,0xfd,0xce,0xf6,0xab,0xfa,0xa2,0x09,0xfd,
+  0x5d,0x6e,0xfe,0xbb,0xa8,0xff,0x63,0x91,0x7c,0x2c,0x7d,0x4e,0xec,0x4f,0x73,0xd6,
+  0x83,0x17,0xff,0x28,0x67,0x53,0x75,0x57,0xf0,0xff,0xb8,0x7c,0x24,0x69,0xbb,0xe2,
+  0xb2,0x7d,0x8c,0x09,0x81,0xb1,0x37,0xff,0x5d,0xb5,0xf1,0x4f,0x82,0xb4,0xdd,0x7a,
+  0x05,0xfc,0x79,0x6c,0x5c,0xfc,0xeb,0xd6,0x11,0xf6,0x16,0x3c,0x6e,0x4c,0xcc,0x7f,
+  0x66,0x39,0xfc,0x67,0xd5,0xe9,0x17,0xbc,0xdb,0x8c,0xf6,0xfd,0x1e,0xfe,0x33,0xbf,
+  0x3d,0x8b,0x7f,0x56,0xb2,0xff,0x82,0x3d,0xea,0x95,0xf8,0xcf,0x2d,0x46,0x76,0x7c,
+  0x77,0x16,0xff,0x88,0xf8,0xd7,0x07,0x57,0xe0,0x3f,0x7f,0xcc,0xed,0x47,0x66,0xd7,
+  0xff,0x09,0xa6,0x9b,0x87,0x7f,0x07,0xff,0xd9,0xe9,0x3f,0x42,0xf5,0x7f,0xb2,0xdd,
+  0xbe,0x2e,0xe1,0xdd,0xe6,0x9c,0xfc,0x7d,0xfc,0xe7,0x50,0x16,0xcf,0x18,0x08,0x83,
+  0xf7,0x5c,0xc9,0x9f,0xe3,0xf2,0x8d,0x9d,0xf8,0x97,0xe8,0xf6,0x75,0xa5,0xf1,0xc3,
+  0xce,0x7e,0x41,0xf5,0x7f,0xb2,0x7c,0x8f,0x7e,0x69,0x1f,0x0f,0x4f,0xe0,0xdf,0xd8,
+  0x30,0x8e,0xff,0x6c,0xcf,0xf7,0x3c,0xa5,0x65,0x4d,0xc8,0xff,0x71,0xea,0x5d,0x3b,
+  0xf8,0x27,0x85,0xab,0xe5,0x5c,0x5b,0x43,0xdf,0x15,0xfc,0x21,0xf6,0xfd,0x53,0x36,
+  0xfe,0x79,0x49,0xfe,0x0d,0x11,0xa1,0xcd,0xc0,0x04,0xfe,0x90,0x49,0xdb,0x1d,0xfe,
+  0xf3,0x56,0x1b,0xff,0x50,0x91,0xf3,0x7d,0x30,0x23,0x8f,0xbf,0x7a,0xde,0xda,0xbf,
+  0xbc,0xf9,0xef,0x51,0x7b,0xfc,0x69,0xd8,0x17,0x72,0xf2,0xe5,0x45,0xd8,0xeb,0xb4,
+  0x34,0xde,0xff,0x53,0x91,0x65,0x23,0x00,0xbe,0x7d,0x69,0x2b,0x3f,0x77,0x02,0xff,
+  0x8f,0x17,0xff,0x64,0xe3,0x83,0xf2,0xb0,0xe8,0xff,0x1e,0xb1,0xa6,0x59,0x9b,0xc3,
+  0x6f,0x49,0xb9,0xf5,0x0f,0x2b,0x2f,0xd8,0xd5,0x9e,0xcf,0x4c,0xc0,0x7f,0xfe,0x35,
+  0x51,0x83,0x46,0xe5,0xde,0x49,0x1e,0xfc,0x13,0x78,0x92,0xa1,0x5a,0x28,0x6c,0x7a,
+  0xd9,0x9c,0x33,0x80,0xfa,0x69,0xb0,0x84,0x31,0xaa,0x7f,0x98,0xc5,0x3f,0x92,0xd7,
+  0xff,0xb3,0x13,0xd1,0x60,0x77,0x9a,0xd5,0xc2,0x13,0x7a,0x38,0x83,0xf8,0xb0,0x96,
+  0x18,0xdd,0x2b,0x55,0x2f,0xff,0x27,0xc7,0xff,0xf3,0x00,0x88,0xb6,0x32,0x1b,0xa9,
+  0xfa,0x6e,0x8b,0x3a,0x5b,0xc4,0x97,0x6b,0xb8,0x97,0x98,0xfa,0x96,0x13,0x7f,0xb7,
+  0xfc,0x3f,0x7a,0x4a,0xa5,0x36,0x6a,0xbb,0x21,0xbc,0xa2,0xbb,0x57,0x08,0xd3,0xab,
+  0x1c,0x22,0xb4,0xec,0xcd,0xff,0x32,0x2a,0x76,0xc0,0x8b,0x5a,0x5d,0x2a,0x90,0xae,
+  0xa2,0x85,0x54,0x67,0x06,0xac,0xfe,0xb9,0x7f,0x9f,0xe3,0x2f,0x35,0x9d,0xf5,0x40,
+  0xfd,0x2f,0x2e,0x76,0x1f,0xe2,0xb3,0xac,0xb2,0xcf,0x0d,0x56,0xe2,0xe1,0x65,0x79,
+  0x81,0x61,0xe3,0x9f,0xc3,0x84,0x7f,0x72,0xea,0x3f,0xbf,0x2f,0x09,0x6f,0x0f,0xfe,
+  0x10,0x3c,0xd6,0x12,0xd0,0xe8,0xfe,0x3c,0x26,0x88,0xd0,0xfc,0x3c,0x88,0x15,0xe8,
+  0xc9,0xff,0x52,0x70,0x3d,0xa8,0xe1,0xb4,0x78,0xfe,0x27,0x34,0xd1,0xc8,0x52,0x30,
+  0xe4,0x97,0x87,0xd2,0xa4,0x1f,0x58,0x30,0x54,0x92,0x97,0xff,0x45,0xdb,0x10,0xcd,
+  0x17,0xb5,0xd1,0xa4,0x73,0x9f,0x15,0x7f,0xd7,0x47,0x42,0xb1,0xc2,0x67,0x49,0x3f,
+  0x99,0x1c,0xff,0xcf,0x49,0x69,0x2a,0x3c,0xc6,0xb7,0xee,0x52,0xd7,0x94,0x11,0x30,
+  0xa8,0x4a,0xf9,0x56,0x25,0xc8,0x23,0x24,0xd9,0x44,0xe8,0xeb,0x28,0x31,0x6a,0xc0,
+  0x19,0x6f,0xd5,0x7f,0x8e,0xd1,0xf3,0x53,0xbe,0x64,0xac,0xab,0x84,0xee,0xff,0x04,
+  0x5e,0x51,0x11,0xff,0xcc,0x7d,0x5f,0xb2,0xf8,0x3f,0x9e,0xfc,0x77,0xf1,0x3e,0x76,
+  0x65,0xdd,0xce,0x87,0x78,0xf1,0xd6,0xec,0xb1,0xcb,0x7d,0xbf,0x76,0x7a,0xcf,0x53,
+  0x05,0xa7,0x03,0x67,0x75,0x04,0x6f,0x34,0xdf,0xf3,0xbc,0xae,0xcf,0x01,0x42,0x5e,
+  0xa2,0xf8,0xe1,0x9c,0xfc,0xaf,0x9d,0x5a,0x15,0xa8,0xa3,0x6c,0xb2,0x7a,0x03,0x74,
+  0x58,0x66,0xe4,0x1e,0x36,0xd3,0xbc,0xc5,0xe3,0x48,0x77,0xf9,0xc3,0xc2,0xff,0xd3,
+  0xad,0xa7,0xa8,0xcc,0xa3,0xe6,0xa4,0xbd,0x13,0xf1,0x89,0x5f,0x21,0xfe,0x85,0x6a,
+  0xe4,0xe1,0x83,0xd9,0x32,0x92,0xba,0x30,0xec,0x6e,0xe1,0x71,0x82,0x9a,0xfe,0xfc,
+  0xfa,0xcf,0xe7,0x60,0x4e,0x72,0x66,0x4a,0xa6,0xb2,0x87,0xb3,0x79,0x30,0xd3,0x39,
+  0x02,0xc7,0xa0,0x91,0x07,0x52,0x92,0x8b,0x7f,0x1c,0xbe,0x87,0xf0,0xff,0x18,0x87,
+  0xa8,0xe9,0x95,0xd8,0x7d,0x62,0xc1,0x6e,0x04,0x42,0x63,0x50,0xaf,0x8b,0x0e,0x05,
+  0x36,0xfe,0x71,0xeb,0xbd,0x53,0xff,0x0b,0xa8,0x6b,0x8f,0x5a,0xdd,0xde,0x1b,0xda,
+  0x4b,0xec,0x34,0xe7,0x2c,0x10,0xa2,0xc2,0x77,0xd5,0xf9,0xf5,0x9f,0x71,0xd9,0x88,
+  0x36,0xa6,0xbc,0xe1,0x6e,0xc2,0x33,0xda,0x7e,0xa9,0x76,0x99,0x0d,0x6c,0x56,0xe6,
+  0xe6,0x7f,0x29,0x35,0xb0,0x53,0xdd,0x66,0xaa,0xa2,0x4d,0xb9,0xe6,0x6c,0xdc,0x44,
+  0x5c,0x61,0xd4,0xaf,0xa1,0xb6,0x29,0xd7,0xff,0x03,0x8a,0x68,0x72,0x3a,0x5f,0x74,
+  0x7b,0xe7,0xd1,0x56,0xab,0x0d,0x04,0x0a,0x5e,0x22,0xb4,0x27,0xfe,0x45,0xfd,0x2f,
+  0xda,0x44,0xff,0xd3,0xb8,0x36,0x7a,0x7b,0x03,0xf5,0x3f,0xc5,0x89,0x2f,0x6b,0x80,
+  0xa8,0xc7,0xdf,0xf5,0x8e,0x93,0x7f,0xd1,0x73,0x35,0xd5,0x3f,0x24,0x6f,0x4f,0x33,
+  0xcd,0xee,0xa6,0x96,0xfb,0x7e,0x22,0xa6,0xb9,0x30,0x87,0x08,0xfd,0x8e,0x13,0xcf,
+  0x22,0xfe,0xcf,0x45,0x7d,0x77,0x4b,0x80,0xc6,0x5f,0x34,0x1a,0x8d,0x80,0x05,0x84,
+  0xe6,0x34,0x05,0xc8,0x5f,0x74,0x54,0x5a,0x40,0x0c,0xe1,0x63,0x79,0xfc,0x9f,0xb0,
+  0xa2,0x26,0x12,0x56,0xb4,0x4b,0x4d,0x10,0xec,0xa9,0x99,0xa1,0x01,0x0f,0x67,0x44,
+  0x21,0x44,0x3c,0x81,0x1e,0xc9,0xad,0xff,0xb3,0x4a,0xa7,0x36,0x1f,0x02,0x08,0xb5,
+  0xa9,0x15,0x09,0xbc,0x62,0x25,0xc2,0x1f,0x17,0x11,0xb1,0xa2,0x1c,0xfe,0x73,0xe5,
+  0x76,0x15,0x4f,0xeb,0x83,0x6a,0xb2,0xc9,0x8a,0x76,0x75,0x0b,0x20,0x5a,0x30,0x63,
+  0x91,0xd0,0x7f,0xb6,0x10,0xe2,0x11,0xe7,0xf7,0xda,0x46,0xf8,0x87,0x8b,0xb2,0x45,
+  0x04,0x74,0xeb,0xe3,0xd9,0x9f,0xb5,0x6e,0x19,0xfe,0xe2,0xfd,0xec,0x28,0x08,0x86,
+  0xb3,0x7b,0xfe,0x5d,0x45,0xf8,0x47,0x6f,0x68,0xfd,0x91,0x35,0x6c,0x41,0xeb,0x2c,
+  0x4b,0xa8,0x37,0xec,0x7c,0x7f,0xb3,0x04,0xf1,0x4f,0x0e,0xff,0x67,0x04,0xee,0x56,
+  0xbd,0xb4,0x73,0x1d,0xc6,0x54,0x2a,0x33,0x7e,0x25,0xfc,0x73,0x48,0xad,0x4e,0xa9,
+  0x56,0xd9,0xe7,0x59,0x09,0x7f,0xaf,0xbc,0x0a,0xcf,0xfb,0xb3,0xd2,0xd7,0xa6,0xd8,
+  0xd8,0xe4,0x03,0xd0,0xd0,0x8d,0xeb,0x39,0xe1,0x3c,0x0f,0xf9,0x7f,0x76,0xc6,0xf5,
+  0x64,0x77,0xf6,0xed,0x78,0xcf,0xee,0xff,0xfe,0x15,0xdc,0xa6,0x4d,0x12,0x7a,0x68,
+  0x3f,0xd2,0xed,0xfd,0x45,0xf4,0xbf,0x00,0xfd,0xb0,0x7a,0xf7,0x0a,0xf2,0x87,0x90,
+  0xff,0x36,0x31,0x59,0xf9,0x77,0x51,0xf6,0x67,0xc5,0x90,0xfd,0xfe,0x76,0xbb,0xf5,
+  0x7f,0xd4,0xa9,0xca,0xe9,0xae,0x2a,0x3d,0xf2,0xf5,0xe6,0x57,0xe1,0x83,0x8e,0x85,
+  0xf1,0xfb,0x07,0x19,0x31,0xa2,0x67,0xea,0xfe,0x35,0xe5,0xa2,0xfe,0xe1,0x70,0x70,
+  0x4d,0xb5,0x37,0xff,0x0b,0xed,0x8f,0x7c,0xc8,0x98,0x65,0x5b,0x8f,0x49,0x83,0xf2,
+  0x69,0x65,0x4c,0x71,0xec,0xcf,0x02,0xf2,0x6f,0xe4,0xe4,0x7f,0x51,0xfc,0xcb,0x39,
+  0xb6,0x5b,0xfd,0xbf,0x2e,0x27,0x17,0xea,0xb8,0x7f,0xbd,0x44,0xfe,0x9f,0x54,0x0e,
+  0xff,0xa7,0x57,0xda,0xa2,0x3c,0xa9,0x6c,0x3d,0x4e,0xdd,0x2e,0xe8,0xf9,0xbb,0xfc,
+  0xb7,0x93,0x20,0xdd,0x08,0x54,0x88,0xc3,0x10,0x85,0x10,0xdb,0xc3,0x6f,0x39,0xfa,
+  0x4c,0xc2,0x16,0x6d,0xaf,0x56,0x65,0x6e,0x20,0x33,0x45,0xdd,0x79,0x6c,0xd8,0x03,
+  0xea,0x5d,0xa2,0x70,0x07,0x4d,0x3c,0x27,0xff,0x8b,0xda,0xbe,0x87,0x7f,0x62,0xef,
+  0xe6,0xe0,0xa7,0x65,0xb6,0x13,0x77,0x05,0x35,0x06,0x64,0x88,0x22,0xe0,0xf3,0xfa,
+  0x7f,0xf6,0x55,0x52,0x98,0xaf,0xee,0x85,0x49,0xa3,0x38,0xbb,0xff,0x4d,0xd6,0x72,
+  0xb3,0x35,0xf1,0x15,0x81,0xb4,0x9e,0x61,0xcf,0x48,0x62,0xe2,0x6f,0x79,0xec,0x21,
+  0x15,0x3d,0x3e,0xa4,0x65,0xe3,0x11,0x0d,0x83,0x4b,0x37,0x09,0x47,0xd9,0x02,0x10,
+  0x1e,0x12,0x14,0x92,0x25,0x69,0x4f,0x7e,0xd3,0x03,0x49,0xaa,0x07,0x38,0xe7,0x6f,
+  0x02,0xd9,0xea,0x37,0x86,0x48,0xfc,0xb9,0x94,0x6a,0xd4,0x70,0x9b,0xdb,0x23,0x4a,
+  0xbd,0xa1,0xd0,0xe7,0xe0,0x1f,0x53,0xe0,0x9f,0x70,0xd2,0x82,0x31,0x4a,0xed,0x89,
+  0x5b,0x93,0x75,0xa7,0xd5,0x03,0x0a,0x1e,0x2b,0xe8,0xca,0xdb,0x50,0x1b,0x98,0x20,
+  0xff,0x6b,0xdb,0xb8,0x34,0x9f,0x5a,0xd8,0x40,0x6e,0x9f,0x27,0x58,0xad,0x74,0x6d,
+  0x1e,0xfe,0x51,0xa8,0xfa,0x4d,0x84,0xea,0x93,0x64,0x0b,0x73,0x51,0xd9,0x9f,0xd5,
+  0x40,0x30,0x5b,0x25,0xff,0xd8,0xbf,0xc4,0x56,0x78,0xfa,0x7f,0x4d,0x59,0x6d,0x6d,
+  0xeb,0x34,0xdf,0x73,0x76,0xd9,0xe7,0xf3,0x52,0x03,0xdc,0x4f,0xf5,0x91,0xc8,0xff,
+  0x13,0xcc,0xe9,0xff,0x45,0xf8,0x87,0xb9,0xb0,0x07,0x82,0xb6,0x9b,0x8b,0xfa,0x7f,
+  0x91,0x20,0x09,0xbe,0xf7,0x38,0xff,0xcf,0x80,0x7c,0x29,0x64,0xa1,0x9d,0xf2,0x4b,
+  0x56,0xfd,0xe7,0xb1,0xe6,0x4b,0x9a,0xa8,0x9f,0xe9,0x8d,0x7f,0x71,0x3b,0xfe,0xd5,
+  0x5d,0x26,0xaa,0xfd,0x64,0x69,0x3f,0x1d,0x1e,0xfe,0x8f,0xea,0xcd,0x7f,0xef,0xb6,
+  0xe3,0x5f,0x9a,0x8b,0x7e,0x8f,0x57,0xb8,0x8e,0x20,0x10,0xf5,0x25,0xbc,0xf9,0xef,
+  0x3b,0x84,0xff,0xc4,0x9f,0x74,0xa3,0x8d,0xb6,0x00,0xa7,0xdd,0xf8,0x97,0xbd,0x1e,
+  0x9c,0xf8,0x57,0xb7,0x17,0x06,0xbf,0xec,0xe0,0x61,0xa9,0xc1,0x5c,0x92,0x6e,0x1e,
+  0x74,0xe6,0x6b,0xfb,0x7f,0x96,0x66,0xd3,0xba,0xfb,0xfc,0x59,0x45,0x21,0x2c,0x5c,
+  0x74,0x01,0xbe,0x01,0xb3,0xf2,0xf3,0xbf,0xf0,0x7d,0x2c,0x70,0xbd,0xaf,0xe2,0xb6,
+  0xda,0xef,0xce,0x7f,0xc7,0x65,0x93,0xcd,0xd6,0x97,0xac,0xc7,0xd6,0x3c,0x0b,0x23,
+  0x7a,0x05,0xfe,0xb3,0x87,0xfd,0xe5,0x6c,0xd3,0x13,0xe4,0xbf,0xeb,0xd2,0x54,0xcb,
+  0xed,0xf3,0x37,0x65,0xe3,0xdd,0x20,0x13,0xe7,0xbf,0x3b,0x6c,0x1f,0x23,0xcb,0xf6,
+  0x21,0xb7,0x8f,0x1d,0x11,0xab,0x18,0x9f,0xff,0x3e,0x3e,0xfe,0xe5,0x11,0x0a,0xc6,
+  0xe5,0xbf,0x67,0xdd,0x3e,0xaa,0x1c,0x1d,0x97,0xb6,0x69,0x09,0x1f,0xf5,0xf2,0xf7,
+  0x5a,0x4b,0xb7,0xb0,0x7b,0xec,0x6e,0xef,0xee,0x31,0x8a,0x5d,0x29,0xff,0xdd,0x84,
+  0xef,0x32,0x41,0xf3,0x5e,0x42,0xec,0xee,0xc4,0x04,0xf3,0x7d,0xdd,0xbf,0x26,0x9c,
+  0x9b,0xff,0x2e,0xd8,0x86,0xf5,0x2e,0xcd,0x7e,0xfc,0xf9,0x22,0xb7,0xfe,0xe1,0x31,
+  0x02,0x39,0xa7,0xe5,0xc8,0x38,0xb7,0xcf,0x08,0x7c,0x75,0xe2,0xfc,0xf7,0x06,0x58,
+  0x9a,0x90,0xaf,0xd0,0xff,0x62,0x82,0xfc,0x77,0xe1,0xff,0x99,0xc0,0x2d,0x20,0x84,
+  0x95,0x57,0xf6,0xff,0x90,0x20,0x4f,0x94,0xcf,0x95,0x97,0xff,0x7e,0x25,0xda,0xcf,
+  0xef,0xe2,0x3f,0xc7,0x26,0x70,0x83,0xfc,0x5e,0xff,0xcf,0x15,0xf3,0xdf,0x3d,0xfd,
+  0xdf,0x1d,0x7f,0x8e,0x25,0x14,0x4f,0x98,0xcf,0xe5,0xe1,0xff,0x9c,0x61,0x47,0xf3,
+  0xd8,0xce,0x39,0x82,0x88,0x7f,0x1d,0xc9,0xe9,0xff,0xd5,0x7d,0x85,0xb4,0x77,0x37,
+  0x11,0xcc,0xad,0x7f,0x48,0xfc,0x9f,0xfc,0xea,0x46,0x13,0xcd,0xd7,0xcd,0x7f,0xdf,
+  0x9e,0xa5,0xfd,0xc0,0x84,0xfa,0x94,0xf2,0xfd,0x3f,0x15,0xdb,0xb3,0xd5,0x9c,0x3a,
+  0x27,0x7c,0x7e,0x96,0xf5,0xff,0xd8,0xf7,0x8f,0x80,0xdd,0xff,0xe2,0x4a,0xeb,0x41,
+  0xf0,0xe1,0x3d,0xfd,0xbf,0x52,0x36,0xa9,0x5e,0x9f,0x40,0xff,0x23,0xe3,0xf0,0x8f,
+  0xa2,0x5a,0x61,0xaf,0xcc,0xbd,0x11,0x37,0xfe,0xe5,0xf5,0xff,0xa4,0xfc,0xb9,0xf9,
+  0x5f,0x96,0xfd,0xf1,0xcd,0x4f,0x6c,0x04,0x6f,0x1b,0x26,0x47,0x30,0x44,0xff,0x2f,
+  0xd7,0xfe,0x4c,0xd6,0xc4,0x4b,0x3a,0xc6,0x2c,0xc7,0x48,0x67,0xbe,0x3f,0xa4,0xc9,
+  0xdf,0x5e,0x36,0xe2,0xde,0x3f,0xeb,0xff,0x29,0x59,0x23,0x5b,0xfd,0x2f,0x26,0xe5,
+  0xf8,0x7f,0x7e,0x69,0x09,0x6f,0xe5,0xe2,0x1f,0xe1,0xcf,0x97,0x57,0xc3,0x04,0xf6,
+  0x04,0xed,0xf9,0xd2,0xf1,0xf9,0xef,0x8d,0x99,0xa5,0x23,0xe5,0x0d,0xb4,0x5b,0xbd,
+  0xbe,0x14,0xf7,0x2f,0xe5,0x72,0x97,0xe5,0xff,0x91,0x2e,0x27,0x45,0x23,0x30,0xd3,
+  0x93,0xff,0x2e,0xea,0x1f,0x92,0xff,0x6a,0x5c,0x20,0x8f,0xbd,0x22,0x8d,0xf3,0xff,
+  0x38,0xf1,0xaf,0xc1,0x89,0xc6,0xc3,0x5e,0x49,0x34,0x02,0xcb,0xad,0xff,0x23,0xb4,
+  0x57,0xd1,0x74,0x65,0xfb,0x53,0x36,0x30,0xde,0xff,0xb3,0x85,0x8e,0xd5,0xe3,0xf3,
+  0x97,0xa5,0x86,0x45,0xc1,0xb4,0xe4,0xcd,0x7f,0xcf,0x7e,0xfb,0xc0,0x86,0xf1,0x6e,
+  0x9f,0xd3,0xaa,0x60,0x44,0x7b,0xfd,0x3f,0x92,0xed,0xff,0x19,0x96,0xeb,0x27,0xb2,
+  0xe7,0x4a,0x5e,0xfe,0xbb,0xc3,0x7f,0x8e,0xb0,0x1d,0xe3,0xc2,0x2e,0x2e,0x9f,0xc7,
+  0x83,0x7f,0xb2,0xe3,0x29,0xec,0x75,0xd3,0xf8,0xf1,0x4a,0xd6,0xff,0x63,0xaf,0x07,
+  0xe2,0xff,0x64,0xfd,0x3f,0x1b,0xc7,0xeb,0x47,0x1b,0xe7,0xff,0x21,0xfe,0x4f,0xd6,
+  0xff,0x13,0x55,0x27,0xde,0x5f,0x08,0xff,0xb8,0xf5,0x9f,0xed,0xf8,0x97,0x31,0xd1,
+  0xfe,0xa5,0x5a,0x1b,0xbd,0x3c,0xe2,0xd8,0x1f,0x78,0xba,0x40,0xbe,0xcb,0x78,0xa5,
+  0xed,0x06,0x98,0xf2,0x34,0x09,0xda,0x0d,0x15,0xc5,0x4f,0x57,0xde,0x25,0x7d,0x16,
+  0x3e,0x51,0x51,0xd9,0x27,0xdd,0xb5,0xe8,0x15,0xed,0x23,0x4a,0xb1,0x39,0xdb,0x79,
+  0x9e,0xa7,0x3f,0xa1,0xcc,0x5e,0x14,0x30,0x9a,0xb5,0x7f,0xed,0x2f,0xb8,0xab,0xe3,
+  0x2f,0x8c,0x26,0xad,0xb2,0xbf,0x70,0x36,0x04,0x8c,0xcf,0x84,0xa0,0x1f,0x66,0x4b,
+  0x77,0x18,0x9f,0xd1,0x2a,0x78,0xa9,0xfd,0x3c,0xd0,0xc5,0xa4,0xbb,0xf8,0x67,0xe3,
+  0x1f,0x51,0x15,0x4e,0x6d,0xe4,0xf4,0xf2,0x90,0xb2,0x0e,0xaf,0x2c,0xd7,0xcb,0xd4,
+  0x9b,0x0f,0xa3,0xd0,0x8a,0x82,0xe2,0xa4,0x27,0xd2,0x06,0xd0,0x11,0xd7,0x97,0xab,
+  0x57,0x41,0x41,0x02,0x0f,0x7d,0xcb,0x59,0x21,0x14,0x10,0xb9,0xa5,0x15,0x3e,0x1d,
+  0x5b,0xcb,0xa7,0xe1,0x15,0xf8,0x34,0x5d,0x71,0x9f,0x67,0x79,0x41,0x5d,0xc7,0x5f,
+  0xf0,0x3f,0x89,0x15,0x0c,0x15,0xd4,0x49,0x28,0xac,0xaa,0x18,0x92,0xc2,0xa5,0x9f,
+  0xed,0xfa,0x48,0x5c,0x19,0x90,0xee,0x86,0xc9,0xfc,0x13,0x7a,0xa5,0x19,0x73,0x9e,
+  0xe7,0x69,0xea,0x05,0x16,0xd2,0x19,0x48,0x5c,0x47,0x41,0x61,0x12,0xf0,0x16,0xea,
+  0x6a,0x5c,0x28,0x69,0x1c,0x97,0x19,0x0a,0xf8,0x55,0xa9,0x7b,0x7f,0x43,0x89,0x4b,
+  0x2a,0x5f,0x1c,0x83,0x6e,0x65,0x05,0x09,0x7a,0x69,0x42,0xa9,0xea,0x50,0x0d,0x06,
+  0x1a,0xaf,0x08,0x73,0x55,0x6b,0xd2,0x35,0xef,0xf8,0x5b,0x0b,0x96,0xf5,0xb5,0xa5,
+  0xfe,0x34,0x52,0xe0,0x57,0x50,0xe0,0x7f,0x3a,0xbf,0xb2,0x49,0x82,0x8e,0xb6,0x98,
+  0x82,0x07,0x4e,0xa9,0xc9,0xd4,0xa0,0x22,0x52,0x09,0xb3,0x9d,0xe7,0xe1,0x93,0xa5,
+  0x8f,0xc0,0xcd,0xe6,0x47,0xda,0x0b,0x3e,0x4b,0x42,0xe6,0x23,0x6b,0x50,0xf8,0x0c,
+  0x2c,0x1a,0x2c,0x6d,0x57,0x26,0x4b,0x93,0xa4,0x16,0xb3,0xb2,0xbd,0xc0,0x88,0x19,
+  0xce,0x78,0x9d,0x6b,0x50,0xa8,0x2a,0x9a,0x44,0x4d,0x30,0x0b,0x0d,0x25,0x29,0x45,
+  0xa0,0x54,0xd2,0xe2,0x8b,0xb8,0xf8,0x5e,0x31,0x15,0x90,0x24,0x8f,0x7e,0x56,0xb1,
+  0x6b,0x60,0x9d,0xaa,0x53,0xb1,0xb8,0x10,0xac,0x93,0x50,0xa8,0x61,0x45,0x52,0x02,
+  0xaa,0x92,0x21,0xbd,0x50,0x85,0x75,0xe4,0x9c,0x93,0xdc,0xdf,0xeb,0xe9,0xb6,0x82,
+  0x95,0xd2,0x9f,0xa9,0x57,0x19,0x05,0x49,0x69,0x25,0xfc,0x99,0xef,0xd3,0x28,0x4c,
+  0xc2,0x2b,0xf0,0x69,0x63,0x4a,0x72,0x52,0x8d,0xb4,0x1c,0xfe,0xde,0xa8,0xe4,0xb3,
+  0x35,0x67,0xbc,0xe1,0x6f,0x87,0x57,0xe0,0x06,0x2a,0x03,0x4c,0x8d,0xc1,0x6f,0x80,
+  0x82,0x6e,0xa9,0x1d,0x87,0x5d,0x05,0x95,0x26,0x6e,0x2b,0x43,0xfc,0x2a,0xfc,0xca,
+  0xb3,0x7e,0x9a,0x94,0x78,0x47,0x28,0xbc,0xd8,0xa7,0x35,0x29,0xb1,0x8e,0x40,0x78,
+  0xb1,0x9a,0x3c,0xac,0x54,0xf1,0xee,0x3b,0x3f,0x1f,0x29,0x4a,0x40,0xbc,0x23,0xa0,
+  0x37,0xab,0x9a,0xe9,0x3e,0x0f,0xa7,0x18,0x98,0x0a,0x8c,0xa0,0x50,0x0c,0x5f,0x1e,
+  0x12,0x34,0x11,0x06,0x06,0xa3,0x1b,0xcd,0xbe,0x22,0xc9,0xf4,0x95,0xbb,0x7e,0x98,
+  0x14,0xe3,0x4b,0xf4,0x72,0x55,0x39,0xec,0x08,0x05,0x75,0x66,0x6b,0x1a,0x85,0x67,
+  0x0a,0xf0,0x4a,0xec,0x4f,0x54,0xc5,0x74,0xf5,0xf9,0x74,0x53,0x41,0xbc,0x63,0xb9,
+  0xfe,0x69,0xb5,0x32,0x81,0x42,0x48,0x5f,0x2c,0x84,0xbe,0xd6,0xd8,0x67,0x54,0xa5,
+  0x53,0xd2,0x3b,0x96,0xc7,0x16,0xab,0xa5,0x9e,0xf5,0x2c,0xd6,0x8f,0x78,0x1e,0xa2,
+  0xf5,0xa3,0xa0,0x42,0x82,0xbc,0x69,0xa4,0x4b,0xae,0xe0,0x15,0x5d,0x46,0xc1,0x33,
+  0xdf,0x65,0xca,0xca,0x8e,0xab,0xf5,0xc5,0xad,0xa5,0x9b,0x6c,0x21,0xa1,0xcc,0xed,
+  0x28,0xd2,0x9b,0x5a,0x61,0x93,0x52,0x83,0x57,0x9a,0xe9,0xfe,0xee,0xf8,0x78,0xc1,
+  0x72,0xe9,0xd3,0xf0,0xa7,0xbc,0xd2,0x15,0xa4,0x10,0x2c,0xc6,0x45,0x09,0xb8,0x10,
+  0xf1,0x4a,0x29,0xaf,0x34,0x3c,0xeb,0xa7,0x10,0x5f,0xa2,0xb6,0x78,0x65,0x4f,0x41,
+  0x56,0x08,0x15,0x2c,0x96,0x8a,0xf8,0xb2,0x78,0x45,0x48,0x29,0x94,0x16,0xe1,0x15,
+  0x25,0x54,0xe0,0xa1,0x33,0xf0,0x32,0x50,0xb8,0xa1,0x6b,0xad,0x0a,0x09,0x8b,0x74,
+  0x68,0xd5,0x58,0xa9,0x22,0x49,0xd0,0x86,0x57,0xa4,0x1a,0xbc,0xa2,0xa9,0xb8,0x82,
+  0x5c,0xfd,0x2c,0x66,0xa5,0xfc,0xbf,0xe2,0xd3,0x42,0xc5,0x96,0x50,0xd5,0xaa,0xb6,
+  0x30,0x49,0xea,0x8f,0xcf,0xd6,0x42,0x8b,0x4b,0x6f,0xe7,0x2f,0xc4,0xaf,0x0f,0x15,
+  0x7b,0x9e,0xe7,0xe9,0xc5,0x68,0x16,0x3e,0xab,0x7f,0x46,0x95,0x8e,0x14,0xe0,0x8b,
+  0x8f,0x42,0xe5,0x91,0x49,0x78,0x25,0xfe,0x27,0xa1,0x28,0x5e,0xe9,0x98,0x1c,0xff,
+  0x87,0x10,0x2e,0x0c,0xe7,0x79,0x6e,0x6e,0x82,0xbb,0xf8,0xcf,0xf5,0x1b,0x42,0x45,
+  0x87,0xe5,0xbb,0xf8,0x5f,0xe8,0x37,0x2c,0x2f,0x16,0x7f,0x18,0xff,0x4c,0x28,0x70,
+  0x04,0x67,0xf4,0x0a,0x0a,0xc5,0x66,0xa9,0xf3,0x3c,0x37,0x8b,0xfb,0xc7,0x3f,0xb3,
+  0xfc,0x4f,0x8f,0x08,0xa1,0x2c,0x54,0x79,0x44,0xb9,0xbe,0x6b,0x7d,0xfc,0xf3,0x21,
+  0x38,0x02,0xb3,0xf1,0x4a,0x33,0xde,0xdf,0xfd,0xbd,0x80,0xe1,0x92,0x17,0x46,0x26,
+  0x61,0x09,0x38,0x6b,0xa9,0x1d,0x05,0x06,0x2d,0x09,0xa0,0x2b,0x1f,0x51,0x5b,0x3c,
+  0xfa,0x47,0x3b,0x70,0x27,0x5f,0x7e,0xe7,0x55,0xa1,0x82,0x75,0x24,0xc4,0xb3,0x42,
+  0x2b,0xfe,0x43,0x15,0xeb,0x0a,0xaa,0xac,0x2b,0x1c,0xdc,0xe7,0x31,0xae,0x6f,0x47,
+  0x6b,0xf9,0x19,0xa8,0x30,0xbb,0x50,0x60,0xcb,0x50,0x90,0x74,0x58,0x02,0x1f,0x61,
+  0x8a,0x59,0xaa,0xe3,0x57,0x1f,0x01,0xef,0x7a,0xbe,0xb9,0x89,0xc7,0x79,0x28,0x82,
+  0xab,0x25,0x21,0x04,0xe6,0x43,0x41,0xef,0x50,0x75,0xc5,0xa7,0x25,0x70,0xfd,0x88,
+  0x97,0x92,0x7b,0xf5,0xd3,0x45,0xdf,0x36,0xa9,0xa5,0x09,0x12,0x22,0x4d,0xbe,0x52,
+  0x7c,0x6c,0xbc,0xc2,0x54,0xed,0x5e,0xc5,0x12,0x4a,0xb9,0xe4,0xb9,0x7f,0x81,0xd1,
+  0xd1,0x16,0xbe,0x43,0x2d,0x15,0xc2,0xec,0xb6,0x40,0x65,0xf3,0x34,0xe0,0x46,0x55,
+  0x61,0x40,0x29,0x2f,0x45,0x43,0xa4,0xdf,0x11,0xa8,0x34,0x24,0xaf,0x7e,0xda,0xf8,
+  0x1d,0xb1,0xca,0x00,0xbe,0x2f,0x96,0xb0,0xb6,0x19,0x85,0x16,0xbd,0x54,0x2d,0xb8,
+  0x25,0x7b,0xa5,0xc0,0x70,0xf5,0x0f,0xaa,0xb1,0x02,0x42,0x5d,0x78,0x40,0x6f,0x35,
+  0x9a,0x40,0x53,0x14,0x09,0x0c,0xc3,0x90,0x70,0x29,0xe1,0x1a,0x02,0xbc,0xd2,0x81,
+  0xab,0x07,0x3c,0xbf,0xd7,0xb2,0x26,0x85,0x77,0xe8,0xfa,0x75,0xdd,0x4d,0x09,0xe0,
+  0xfc,0x61,0x98,0xdf,0x3d,0x95,0x29,0xeb,0xbb,0xc2,0x55,0x7f,0x0e,0x65,0xeb,0xf0,
+  0x8a,0xae,0x47,0x54,0x70,0xfa,0x15,0xa2,0x3e,0x97,0xc6,0xaf,0x5e,0xae,0x5c,0xd5,
+  0x54,0x99,0x5c,0x14,0x97,0x7a,0xd4,0x4f,0x37,0x7f,0x8b,0x37,0xc7,0x67,0x2f,0x57,
+  0xff,0x59,0xaa,0xe4,0x93,0xc8,0xfe,0xcf,0x83,0x4a,0xcf,0xef,0xb5,0xd6,0x68,0x8e,
+  0x6b,0x43,0x30,0x8f,0x7d,0x93,0x2f,0xc2,0x6f,0xd5,0xbf,0x97,0x8b,0xf1,0xf7,0x9d,
+  0x1f,0x52,0xe7,0xe1,0x36,0x21,0xe9,0x52,0x0f,0x7c,0x02,0xed,0x0f,0x78,0x3e,0x35,
+  0xed,0x45,0x01,0x5f,0xb3,0xa1,0x0d,0xd6,0xa0,0x3d,0x51,0x9a,0x8d,0xa4,0x59,0x13,
+  0x57,0xbb,0xd5,0xb0,0x78,0x16,0x29,0x00,0x5f,0x80,0x36,0xd3,0x33,0xbc,0x02,0x6a,
+  0xa0,0xb8,0x15,0x8d,0xcc,0xcf,0xe0,0x7a,0x6a,0x43,0xfe,0x67,0xfc,0x05,0xbc,0x52,
+  0x14,0xc7,0x5f,0x3a,0x09,0xd3,0x78,0xb1,0x65,0x9a,0x3c,0xb7,0x97,0x6e,0x84,0xdb,
+  0x96,0x95,0x57,0x28,0xfd,0xd2,0x6c,0x7e,0x5b,0x5b,0xf9,0x55,0xca,0x1b,0xff,0x7e,
+  0x23,0xee,0x5f,0x65,0x9b,0x2a,0xb6,0x17,0x54,0x49,0x4b,0xda,0xe4,0x0a,0xc5,0x3b,
+  0x3e,0x5c,0xb0,0xaa,0xe3,0xcf,0xe3,0x9f,0xde,0x58,0x59,0x55,0xb0,0xaa,0xef,0xcf,
+  0xf5,0xab,0xbe,0x5b,0xf9,0xc8,0xda,0x55,0xfc,0x73,0xb1,0x4f,0xdf,0x2b,0x6d,0x93,
+  0xf0,0x4a,0xec,0xaa,0x8d,0x95,0x3c,0xe7,0x79,0xe6,0xd2,0x63,0xc4,0xe9,0x5f,0x87,
+  0x22,0xd4,0x0d,0xf4,0xc0,0x5c,0xe9,0x6a,0x60,0x77,0x68,0x83,0xca,0xf5,0x50,0x04,
+  0x4c,0x07,0xef,0x78,0xb5,0xa5,0x4e,0x0a,0x74,0x35,0x4b,0xa5,0xdd,0x2d,0x2b,0xa4,
+  0x90,0x82,0x42,0xd7,0xca,0x58,0x11,0x6e,0x64,0x92,0x66,0xe2,0x57,0xa1,0xae,0x42,
+  0xe9,0x76,0xef,0x78,0xe9,0x0d,0xad,0xb4,0xc5,0xb8,0x5d,0xaa,0x34,0xfe,0xaa,0xad,
+  0xf4,0x0e,0xe5,0x76,0xa8,0x34,0x16,0x69,0xb1,0x16,0xa5,0x52,0x6a,0x41,0x41,0xab,
+  0x40,0xa1,0xd2,0xf0,0xde,0xbf,0xaa,0x49,0x6d,0xbb,0xb7,0x42,0x2f,0x68,0x95,0xf0,
+  0xd7,0xe7,0x54,0xfb,0xa8,0x8a,0xa9,0x77,0x74,0x56,0x84,0xbb,0xd4,0xd9,0xcb,0x94,
+  0x36,0x5c,0xd4,0x6b,0xbd,0xe3,0x7d,0x12,0xeb,0x36,0x52,0x5a,0x44,0x41,0xa1,0xc3,
+  0xd8,0x46,0x42,0x9c,0x3d,0x00,0xbd,0xda,0x75,0x06,0x5e,0xe1,0xf4,0x95,0x77,0x38,
+  0x04,0xe4,0x3f,0x81,0x17,0xcc,0xeb,0x63,0x45,0x4b,0x50,0xb8,0xc3,0xac,0x8a,0xa9,
+  0x81,0xa6,0xf2,0xaa,0xae,0x81,0xca,0xd9,0xa1,0x25,0x20,0x8b,0xaf,0x54,0xef,0x1f,
+  0x14,0x49,0x77,0x4b,0x9f,0x4d,0x7e,0x46,0xff,0xd6,0xd1,0x49,0x28,0x6c,0xfe,0x74,
+  0x4d,0xc1,0x80,0x7c,0x77,0xd1,0x67,0x13,0x9f,0xd1,0xa7,0x0c,0xd0,0x95,0xee,0x7f,
+  0x40,0x3c,0xe0,0x19,0x5f,0xad,0x1a,0x87,0xcb,0x62,0x5d,0x81,0x45,0xd5,0x60,0x98,
+  0x38,0xd1,0x80,0x24,0x6b,0x2d,0x28,0x28,0x28,0xe0,0x95,0x32,0x14,0xee,0xf4,0x3e,
+  0x4f,0xe3,0xe5,0xa5,0x97,0x7f,0x7a,0xe9,0xcc,0xe5,0x9f,0x0b,0xe1,0xf2,0x99,0xcb,
+  0x17,0xc7,0x0b,0xf0,0x7f,0xf1,0x69,0x78,0x6d,0xe9,0x5e,0xbc,0xff,0xde,0x9f,0x93,
+  0x70,0xe2,0x35,0xbc,0x1b,0x0a,0x78,0xdb,0xf4,0xf9,0x7f,0x8a,0xbe,0x1c,0xc4,0x2b,
+  0xe9,0xdd,0xab,0x73,0x9e,0xa7,0x71,0xe9,0xf3,0x38,0xfe,0xf9,0x9f,0x0b,0xa1,0x91,
+  0x1e,0xa3,0x91,0xc6,0xf7,0x5f,0xb8,0x38,0xa7,0x9e,0xae,0xf4,0x1f,0x7f,0xd7,0x3b,
+  0xbe,0x3a,0x74,0xdb,0x91,0xb2,0x86,0xae,0x8d,0x7f,0x51,0xfd,0xd1,0xdb,0x7e,0xbc,
+  0xa9,0xb1,0xeb,0xfe,0x8b,0xd5,0x6b,0x5a,0x8f,0x94,0xef,0xec,0xda,0x78,0x27,0x7e,
+  0xf5,0xe3,0x07,0xf7,0x76,0x7d,0xf3,0xac,0x77,0xbc,0x04,0x77,0x19,0x5b,0xb4,0x49,
+  0x4a,0xd1,0xd3,0x0c,0x85,0xb6,0x49,0x15,0x28,0xb4,0x0b,0x41,0xa2,0x2b,0x93,0x51,
+  0x58,0xef,0xd5,0xa7,0x32,0x09,0xd1,0xa3,0xf1,0x0f,0x5a,0x01,0xe2,0x43,0x21,0x54,
+  0xda,0xc2,0x14,0x12,0x08,0x3a,0x16,0x78,0xc7,0x3b,0xf6,0x59,0xe0,0x43,0x40,0x81,
+  0x40,0x0a,0xda,0x5b,0xcb,0x62,0x23,0x74,0x54,0x14,0x9e,0xa3,0xa1,0x3b,0xb9,0x00,
+  0x69,0x88,0x16,0x10,0xc8,0x15,0x86,0x68,0x63,0x24,0xd8,0xa6,0x49,0x5d,0x70,0x67,
+  0x11,0x42,0x0b,0xda,0x2a,0xdd,0x8f,0xaa,0xdc,0x2d,0x11,0x08,0x94,0x06,0x94,0xbb,
+  0x3b,0x48,0x28,0x3d,0x46,0x57,0x52,0x9f,0x88,0x94,0x3e,0x23,0xae,0x34,0xcf,0x94,
+  0xcc,0x9c,0xfb,0x5b,0x20,0xb0,0x34,0x7b,0x5b,0x90,0x72,0x05,0x85,0xd1,0x57,0xee,
+  0x47,0x53,0xa6,0x4b,0x45,0xd0,0x64,0x68,0x3d,0x96,0x10,0x47,0x21,0x6c,0x5f,0xa9,
+  0xb1,0x04,0xef,0xf8,0x6a,0xb8,0xa5,0x0f,0x17,0x55,0x77,0xe9,0xc7,0x95,0x5b,0x3a,
+  0x50,0xe8,0x2d,0x9d,0xa1,0xdc,0x4a,0xc2,0x46,0x69,0x96,0xd2,0xca,0xcb,0x74,0xa5,
+  0xc7,0xb3,0x1b,0xa9,0x66,0x00,0xca,0x11,0xd4,0x49,0x84,0x7d,0xca,0xa9,0x3e,0x14,
+  0x09,0x7f,0x42,0x9b,0x4c,0x0c,0x37,0x99,0x6b,0x8d,0xab,0x92,0x05,0x31,0x70,0xdc,
+  0x21,0x04,0x8e,0x94,0x0a,0x28,0x80,0x45,0x06,0xda,0x87,0x0a,0xfc,0xf1,0x9a,0x0d,
+  0xfc,0x72,0x11,0x1a,0x4c,0xb4,0x78,0x77,0x20,0x28,0x2b,0xcd,0x28,0x68,0xfb,0x63,
+  0xee,0xfd,0x0d,0xa6,0x41,0x17,0x20,0x02,0xd6,0xc2,0x1a,0x1a,0x8e,0x2a,0x1b,0xdc,
+  0xa0,0x80,0x5f,0x19,0x5c,0x43,0x94,0x9c,0x33,0x5e,0xb1,0xf0,0x08,0xa1,0x65,0x49,
+  0xb5,0x05,0xba,0x52,0x4a,0x42,0x0f,0xda,0x4f,0x8d,0x3b,0xe3,0x35,0x44,0x12,0x64,
+  0xa1,0x0a,0xa1,0x28,0xc9,0xb2,0x02,0xcf,0x0a,0x12,0x67,0x2b,0x10,0x9f,0x4f,0x82,
+  0x22,0x37,0x1e,0x61,0xdc,0xdc,0x54,0x88,0xb0,0x50,0xff,0xbc,0x0a,0x87,0x15,0x4b,
+  0xd0,0x50,0x58,0x4f,0x42,0xe8,0xb0,0x32,0xb7,0xef,0x6a,0xc4,0x63,0xe0,0xee,0xa7,
+  0x06,0x3e,0xae,0x68,0x8a,0xa0,0x83,0x69,0xa0,0xd0,0x25,0x67,0x81,0xa2,0xb8,0x82,
+  0x82,0x4a,0xf6,0xd0,0xfd,0x7d,0x0d,0xf0,0x13,0xc9,0x92,0xd8,0x6c,0x87,0x2d,0x41,
+  0xb5,0x05,0x71,0x85,0xf0,0x67,0xd4,0x3b,0xfe,0xe6,0x66,0xa5,0xbd,0x23,0x14,0xfb,
+  0x44,0x00,0x12,0x04,0x5c,0x63,0x9f,0xc0,0x8d,0xd8,0x12,0x02,0xa5,0x87,0x95,0x78,
+  0x1f,0x22,0xc6,0x00,0xb8,0xf8,0xd0,0x40,0x23,0x18,0x17,0x68,0x50,0x13,0xf8,0x90,
+  0x76,0xf3,0x44,0x56,0xc0,0x15,0xab,0xe3,0x8f,0x27,0xab,0x9e,0xf5,0xd0,0x26,0x35,
+  0xe1,0x26,0x1e,0xc2,0xfd,0x5d,0x13,0xb7,0x15,0x1b,0x7d,0x56,0x10,0x57,0x04,0x1e,
+  0xe6,0x9e,0xe7,0xc1,0xdf,0x53,0xa2,0x1f,0x56,0x03,0xa5,0x4d,0x08,0xa5,0x46,0x56,
+  0x00,0x14,0x80,0x76,0x5f,0x44,0x74,0xf6,0xf3,0xb4,0xa2,0x9e,0x17,0x71,0x0d,0x41,
+  0xa0,0x74,0x25,0x01,0x42,0x2e,0xda,0xc0,0xf1,0xac,0x00,0xd1,0x82,0xde,0xa6,0x8a,
+  0x93,0x51,0x56,0xd0,0x85,0x50,0x61,0x5d,0xc1,0x37,0x0a,0x3c,0xcf,0xb3,0x58,0xb6,
+  0x40,0xe0,0x14,0x5b,0x28,0xce,0x13,0xaa,0x96,0x4f,0x31,0x5c,0xfc,0x23,0x2d,0x56,
+  0x08,0x04,0x7e,0x22,0x54,0x7a,0xc4,0x15,0xbe,0xe2,0x5e,0xd9,0x12,0xff,0x6b,0xb5,
+  0xd4,0xa3,0x7f,0x69,0x31,0xe2,0xc3,0x2d,0xf1,0x49,0xa1,0xe2,0xc3,0x0c,0x05,0x1d,
+  0x85,0x23,0xcc,0xba,0x52,0x70,0x04,0x11,0xe3,0x64,0xba,0xe2,0x8e,0x6f,0xbb,0x79,
+  0x71,0x21,0x81,0x40,0x42,0x83,0x02,0x1f,0x7e,0x3e,0x54,0x71,0xa4,0xe0,0x7f,0x09,
+  0xe1,0xea,0x23,0x05,0xb3,0xd7,0x06,0xee,0x6c,0x0e,0x49,0x87,0x3d,0xeb,0xa7,0x0c,
+  0x6a,0xf8,0x27,0x75,0xd6,0x5a,0xb0,0x49,0xca,0x0a,0x64,0x76,0x48,0x50,0x36,0x49,
+  0x2b,0xcd,0xbf,0x88,0x7d,0xa4,0x55,0xf1,0xe8,0x1f,0xf5,0x59,0xc5,0x43,0xd4,0xbd,
+  0x66,0x1d,0x19,0x22,0x14,0x24,0x5b,0xa0,0x2b,0x1d,0xa1,0xf8,0xe2,0x1e,0xef,0xfe,
+  0x7b,0x73,0x5c,0x59,0x23,0x4d,0x85,0x4f,0x70,0xc8,0xa0,0x50,0x82,0x82,0x96,0x51,
+  0xe6,0x8b,0x2b,0xa5,0x74,0xc5,0xa7,0x36,0x71,0xef,0x7a,0x96,0x96,0xc1,0x4a,0x7e,
+  0xb5,0x5e,0xd8,0xaa,0x6d,0x42,0xa1,0x08,0x05,0x5c,0x3f,0x35,0xe2,0x8a,0x64,0x5d,
+  0x61,0xad,0xde,0xf5,0x20,0xd6,0x8f,0x85,0x0f,0x95,0x30,0x2d,0x9b,0x88,0x58,0x3f,
+  0xaa,0xb5,0x7e,0xb2,0x5f,0x79,0xd7,0x4f,0x13,0x18,0x1d,0x9a,0xae,0x04,0x4a,0x9b,
+  0x14,0xa3,0xaf,0x82,0x84,0x66,0xa5,0x8d,0xae,0xa8,0x12,0x53,0x0c,0x7c,0x65,0x14,
+  0xb5,0xd4,0xf0,0xe8,0x87,0x41,0x1b,0xc7,0xdd,0x5d,0x95,0x9a,0xf4,0x65,0x78,0xe0,
+  0x2d,0x88,0x48,0xcd,0x08,0x90,0xac,0x2b,0x24,0xc4,0x0a,0x54,0x17,0x0d,0xd3,0xfb,
+  0xa8,0x10,0x0c,0x68,0x01,0x49,0x35,0x70,0xa9,0x76,0xb5,0x80,0x05,0x0b,0x79,0xa1,
+  0x2e,0xd1,0x40,0x44,0x8c,0xf4,0xd4,0x9e,0xe7,0x61,0x02,0x78,0xa9,0x21,0x96,0x15,
+  0x54,0x1f,0x83,0x6e,0x8b,0x19,0xcc,0x18,0xe7,0x29,0x5d,0xed,0x31,0x34,0x57,0x3f,
+  0x86,0x63,0x6d,0x6a,0x3c,0x66,0x27,0x84,0x66,0xe7,0x6a,0x14,0x8a,0x7a,0xd8,0x17,
+  0xc8,0x3e,0x6b,0xee,0x78,0x44,0x6b,0x0f,0x01,0x33,0x44,0x84,0x9c,0x84,0xa2,0x64,
+  0x21,0x09,0x85,0x86,0x46,0x57,0xa6,0xc0,0x24,0x43,0xf5,0xea,0x27,0x5e,0x18,0xc1,
+  0x9f,0x69,0x05,0x87,0x54,0xcd,0x7c,0x21,0x88,0xdf,0xcb,0xba,0xa2,0xcc,0x2f,0xba,
+  0x86,0x2d,0x5e,0x0b,0xdc,0x79,0x9e,0x36,0x44,0xbd,0x55,0x46,0xa0,0x8d,0x29,0x70,
+  0x0f,0xc4,0x2c,0xe1,0xc7,0x10,0x6b,0x15,0x42,0x27,0xcc,0x36,0x7c,0xcb,0xd9,0x55,
+  0x88,0xe7,0x9d,0xe7,0xc1,0x17,0x74,0x1a,0xb5,0x38,0x6a,0x83,0xcd,0x84,0x27,0xe3,
+  0x28,0xfc,0x97,0x72,0xbd,0x41,0x57,0x34,0xbc,0x72,0x67,0x71,0x5b,0xf3,0xa7,0x21,
+  0xe1,0xd1,0x4f,0xb3,0x72,0x67,0x5f,0x28,0xb6,0x38,0x20,0x7d,0x1b,0xad,0xcd,0xd5,
+  0xed,0x8b,0x03,0xa5,0x9d,0x10,0xb7,0xae,0xdc,0xa3,0xe0,0x7a,0x83,0x96,0x12,0x89,
+  0x7b,0xf5,0x93,0x3d,0x9f,0x92,0xfd,0xb1,0x6c,0xf9,0x46,0xf7,0xc4,0x4a,0x8d,0x0c,
+  0xe5,0x8a,0x9c,0xf5,0xd3,0x4a,0xb0,0x10,0xd1,0x60,0x69,0x8f,0x12,0x2f,0xbd,0x9a,
+  0x04,0x1e,0x17,0x57,0x74,0xa9,0x1b,0xaf,0x04,0x08,0x31,0x7a,0xf5,0x63,0x18,0x6d,
+  0xa5,0x15,0x4a,0x81,0x54,0x6a,0xb4,0xd8,0x42,0x1b,0xda,0x9f,0x40,0x81,0x24,0x19,
+  0x2d,0xb7,0xab,0x05,0x9a,0x84,0x57,0x34,0x8f,0x7d,0xd6,0xf1,0xd7,0xa7,0x95,0xd8,
+  0x8a,0xcb,0xa0,0x02,0x8f,0x2c,0x52,0x2b,0x2c,0xa3,0xb5,0x59,0xd5,0xa1,0x42,0x93,
+  0x8a,0x57,0xc2,0x1d,0x86,0xc7,0x02,0xf9,0x0a,0x08,0x04,0xb6,0x45,0x08,0x28,0x72,
+  0xd8,0x4e,0x82,0x26,0xae,0x5c,0xa7,0xf8,0x3a,0x58,0x37,0xa4,0xb5,0x8f,0xe7,0xd8,
+  0x9f,0x4f,0xc9,0x7f,0x62,0xbc,0x30,0x78,0xfd,0xdc,0x10,0x09,0x5d,0x2f,0x5c,0x3f,
+  0x57,0xfd,0x14,0x2b,0xa7,0x2b,0xd7,0x17,0x7c,0xea,0x61,0xbc,0x32,0x38,0xed,0x86,
+  0xab,0x3d,0xeb,0x59,0x6a,0x15,0x78,0x60,0x92,0x5e,0x8a,0x78,0x40,0x78,0x87,0x48,
+  0x10,0x08,0xe1,0xc6,0x01,0xb8,0x5b,0xda,0xc2,0xff,0x41,0xff,0x96,0xe9,0xfe,0x03,
+  0x60,0xc1,0xc2,0x2c,0x1a,0xd4,0x10,0x28,0x4a,0xe5,0x9a,0x71,0x58,0x9b,0xdd,0x15,
+  0xb8,0x3d,0x0b,0x14,0x97,0x54,0x79,0x86,0xc3,0xef,0x80,0x85,0xff,0x1f,0xc1,0x87,
+  0x04,0x02,0x7f,0xfa,0x2b,0x04,0x81,0x0d,0xaf,0xdd,0x7a,0xc3,0x4f,0x7f,0x75,0x66,
+  0xf7,0x3f,0x21,0x3e,0xbc,0xf4,0xd4,0xaf,0xce,0x9c,0xff,0xa7,0x09,0xef,0x2f,0x40,
+  0xe0,0xfb,0x08,0x02,0x1b,0x1b,0x97,0xa0,0x70,0xe6,0xb8,0xc0,0x87,0xe5,0xef,0x9f,
+  0xb9,0x30,0xf1,0xf3,0xdc,0x44,0x20,0x90,0xd0,0x60,0xe3,0x47,0x5b,0x7f,0xfc,0xe0,
+  0xbb,0x5d,0x1b,0xff,0xb1,0xfa,0xeb,0xb7,0x5d,0xc6,0x2b,0xa7,0xef,0xbc,0x69,0x6a,
+  0xeb,0xab,0x65,0x37,0xe0,0x57,0xde,0xf1,0xac,0x0b,0xb6,0x42,0xe4,0xcb,0xbe,0xc9,
+  0x87,0x85,0x40,0x84,0xda,0xcd,0x11,0x7d,0x49,0xe0,0x2e,0xfc,0xd5,0xbb,0xa0,0x63,
+  0x23,0x5d,0xf1,0x8e,0xb7,0x37,0x16,0xcd,0x15,0x0a,0x7c,0x60,0xf0,0xdb,0x0b,0x2a,
+  0x5a,0x15,0x56,0x2a,0xae,0xe4,0x4c,0xb8,0x2b,0x0b,0x45,0x1c,0x41,0x5a,0xa7,0x57,
+  0x2d,0x89,0xdc,0xed,0x9b,0xcc,0xbb,0xf0,0x05,0x13,0x5f,0x79,0x3f,0xb4,0x03,0xc2,
+  0x97,0x61,0xf2,0x00,0xdd,0x9f,0x2c,0x0e,0x9a,0xec,0x8e,0x66,0xfd,0x76,0x84,0x43,
+  0xf8,0xd5,0x46,0x71,0xc5,0xfb,0xe1,0x1e,0x87,0x0e,0xa8,0x73,0x50,0xe8,0x88,0xe9,
+  0x09,0x98,0xed,0x53,0x79,0xf6,0xab,0x80,0xe9,0x9d,0x6f,0xfe,0x5f,0xa0,0x10,0x13,
+  0x0f,0xad,0x24,0xec,0x2b,0xae,0x41,0x54,0xbd,0xa3,0x99,0x25,0xa8,0x1d,0xe1,0xd4,
+  0xa7,0x7a,0xeb,0x66,0xa8,0x26,0x67,0x31,0xe8,0xc6,0x97,0xd2,0xed,0xc7,0xad,0xe6,
+  0xde,0x38,0x2b,0x5c,0x85,0xfa,0x99,0x1d,0x51,0xbb,0xb3,0x57,0x02,0x87,0x3d,0xe3,
+  0x7d,0xf7,0xd4,0x6d,0x85,0x5e,0x63,0x86,0xe6,0xeb,0x62,0x24,0xf8,0x34,0xdf,0x91,
+  0x19,0x55,0xca,0x8e,0x3b,0xc3,0x93,0xef,0xc5,0x2b,0xc7,0xbb,0xbf,0x7c,0x9d,0xc6,
+  0x3c,0xcf,0x9f,0xaf,0x7f,0xd0,0xf4,0x02,0x45,0xfa,0x31,0x61,0xca,0x56,0xeb,0x4a,
+  0x95,0x47,0x3f,0xea,0x04,0xfa,0x87,0x23,0xfa,0xd6,0x4f,0xc2,0x0a,0xf5,0xb3,0xa4,
+  0x7f,0x88,0x00,0xf3,0xdc,0x5f,0xd5,0x60,0x52,0x4c,0x3a,0x8e,0x0a,0x98,0x6c,0x0a,
+  0xe1,0xcb,0x90,0xac,0x9a,0xa4,0xf5,0x05,0x94,0x2f,0xb7,0x4e,0x36,0xec,0xaf,0xdc,
+  0xf8,0x3e,0xde,0xff,0x9e,0x98,0xb8,0xed,0x64,0xb3,0x8b,0xb2,0x6a,0xbe,0xcc,0xb4,
+  0x78,0xbf,0x52,0xd5,0x1d,0x68,0xf2,0xfc,0x8b,0x09,0xcf,0xf3,0xa3,0x5d,0x15,0x4a,
+  0xa1,0x7f,0x14,0xf7,0x0b,0x83,0xf0,0x95,0x66,0x2c,0xd2,0x71,0x63,0x70,0xf4,0x95,
+  0xb7,0x7e,0x84,0x2e,0x09,0xdc,0xea,0xb4,0x5a,0x10,0x20,0xea,0xa9,0xa3,0x2a,0xf3,
+  0x09,0xe7,0x22,0x3d,0xbf,0x77,0xbf,0xce,0xc1,0xea,0xf8,0xac,0x73,0xe8,0xff,0x22,
+  0xfc,0x28,0xb0,0x56,0xf7,0xbe,0xdc,0xcd,0x3f,0x9d,0xe0,0xa3,0xf1,0xb8,0x18,0x94,
+  0xe4,0xe3,0xbf,0xab,0xaf,0x9f,0x68,0x3c,0x2e,0x34,0xd0,0xda,0x06,0x9d,0xf1,0xc1,
+  0xe0,0xef,0xb8,0x3d,0x7c,0xac,0xf3,0x29,0xc3,0x88,0xb4,0x7f,0xea,0x5e,0x33,0x7b,
+  0xe1,0xea,0x09,0xfe,0x21,0xcf,0x67,0x2a,0xbf,0x77,0x2e,0x44,0xff,0x73,0xc6,0x75,
+  0xbf,0x73,0x94,0xfb,0x61,0x65,0x0c,0xa1,0x77,0x17,0x1e,0xa7,0x26,0xfa,0x34,0x5e,
+  0xbe,0x7c,0xd9,0xcc,0x13,0xce,0xe7,0x5d,0xf9,0x7d,0xe3,0x2f,0x3f,0x69,0x09,0xbf,
+  0x7e,0xed,0x0f,0x1c,0x9f,0x15,0x5e,0xbb,0xfc,0xda,0xff,0x64,0xfc,0xc2,0x3f,0xf8,
+  0x79,0xac,0xdb,0x36,0x3e,0xf9,0x87,0x8e,0xff,0x1d,0xf3,0x65,0x5d,0xca,0x03,0xaa,
+  0x30,0x83,0x8e,0x3d,0x1c,0x27,0x78,0xc7,0xab,0x05,0x85,0xf9,0xf6,0xd0,0x31,0x5c,
+  0xf6,0x1b,0x9a,0xf3,0x0f,0xac,0x53,0xab,0x54,0xd5,0x28,0xd4,0x26,0x78,0x31,0x1d,
+  0xc1,0xfb,0x21,0x17,0x1d,0xee,0x7b,0x9a,0x65,0x18,0xc5,0x6d,0xc7,0x09,0xde,0x0f,
+  0xbe,0x26,0x2a,0xbe,0x2f,0xdc,0x1c,0x67,0xe6,0x5c,0xc1,0x3b,0x5f,0x3c,0xdd,0x00,
+  0x61,0xbb,0xc3,0x13,0x0d,0xcc,0x7f,0x1f,0x55,0x4a,0xd8,0xd4,0xd5,0x6e,0x46,0xee,
+  0x36,0x61,0x0f,0x29,0x65,0x0c,0x74,0x61,0x06,0x55,0xfb,0xcf,0xbc,0xf6,0x30,0x04,
+  0xf4,0xa2,0xb2,0x2a,0xa3,0x7b,0xe2,0x47,0x21,0xc1,0x3b,0xde,0x77,0xcf,0xf4,0x07,
+  0x94,0xde,0x45,0x96,0x3d,0x3c,0xee,0x31,0x8c,0x33,0x26,0x1f,0x13,0xc2,0x97,0x67,
+  0x4c,0xf6,0xe4,0xd7,0x43,0x68,0xd2,0x55,0xa5,0x2a,0x6f,0xae,0xd2,0x26,0xd8,0x98,
+  0x6c,0xc1,0xfb,0xfc,0x70,0x8f,0x5e,0xa5,0xa8,0xcd,0x88,0xdb,0xf2,0xd5,0x9e,0x35,
+  0x95,0x79,0xf6,0x50,0x9b,0x34,0x5f,0x42,0x60,0x81,0xc7,0x71,0xd4,0x36,0xd9,0x43,
+  0xc7,0x30,0x6a,0xd6,0x95,0x7c,0x7b,0xb8,0x96,0x6e,0xd2,0x34,0xe1,0xcf,0x6a,0x0b,
+  0xde,0x5f,0xa0,0x8c,0xcc,0x97,0x2e,0xe1,0xa9,0xfa,0x0f,0xd1,0x3f,0x7e,0xa8,0xdd,
+  0x04,0x42,0xeb,0x2b,0x8f,0xce,0xf9,0x7d,0xb5,0xa4,0xa4,0xc0,0xef,0xfd,0x78,0xec,
+  0xa1,0xc6,0xf3,0xf6,0xef,0xdf,0xf9,0xa9,0xaf,0xa7,0x2a,0xe0,0x00,0xbf,0xfb,0x4f,
+  0xbc,0xf6,0x90,0x2d,0x67,0xc6,0x1f,0x7e,0x7f,0xeb,0x4f,0xf8,0xff,0x60,0x70,0x28,
+  0x12,0x8e,0xc4,0x7e,0xff,0x30,0xe7,0xf3,0x3f,0xb5,0x0f,0xff,0xff,0x36,0xfe,0x7f,
+  0xf6,0x89,0xe1,0x52,0x66,0xe2,0xff,0x9b,0x03,0x00,0x05,0xf3,0x3f,0xf7,0x67,0x46,
+  0x63,0xc3,0xff,0xfe,0xb3,0xff,0xbb,0x9b,0x5e,0xf1,0x13,0xf9,0x31,0x44,0x8d,0xea,
+  0x16,0xa8,0x30,0x3f,0x9c,0xfb,0x2b,0xbe,0x55,0x0f,0x71,0x7f,0xe5,0x13,0xad,0x1f,
+  0xce,0xed,0xa1,0xf1,0x79,0x7a,0x7e,0x03,0x1a,0xcd,0x0f,0xe7,0xfe,0x8a,0xbe,0x79,
+  0xab,0x79,0xcd,0x0b,0xdf,0xec,0xfe,0x70,0x6e,0x0f,0xb1,0xe7,0x63,0xa7,0x8d,0xea,
+  0x76,0x33,0x66,0x7e,0x38,0xf7,0x2f,0xbe,0xe1,0x9f,0xd6,0x9a,0x93,0x7f,0xf4,0xf9,
+  0xa5,0x1f,0xce,0xed,0x51,0xff,0xd6,0xf3,0x7f,0x58,0xfa,0x0f,0x7c,0x6c,0x0b,0x87,
+  0xfa,0x8f,0xa4,0x3e,0x3c,0xfd,0x07,0x71,0xfd,0x2c,0x85,0x0f,0x4b,0xff,0x25,0xd3,
+  0xf7,0x8d,0xc2,0xb5,0x7f,0xfa,0xd8,0x27,0x3f,0x9c,0xdb,0xa3,0xfe,0xad,0xe7,0xff,
+  0xd0,0xd6,0x7f,0x6d,0xe5,0xf7,0x0d,0xff,0x97,0x37,0xab,0xbf,0x7f,0xe8,0xff,0xd1,
+  0x27,0xf6,0x7c,0x23,0xae,0x9f,0x6f,0x7c,0x78,0xeb,0x5f,0x93,0xe6,0xc1,0xb4,0xa2,
+  0xeb,0x3e,0xbc,0xf5,0x6f,0x3d,0xff,0x87,0xa5,0xff,0xe2,0xaa,0x96,0xc5,0x50,0x77,
+  0x66,0xfa,0x87,0xb5,0x7e,0x62,0x97,0x4d,0xb2,0x9f,0xb1,0x51,0xf3,0xc3,0xb9,0xbf,
+  0xa2,0xde,0xf5,0x2d,0x73,0xde,0xee,0xcd,0x1f,0x9a,0xfd,0xcf,0x3e,0xff,0xff,0xed,
+  0xae,0x7b,0xa5,0x8f,0x52,0xbd,0xf9,0x3f,0xcc,0xea,0x8f,0x6c,0xfa,0xd0,0xec,0xcf,
+  0xe5,0x51,0xb2,0x9f,0xa3,0x1f,0x96,0xfe,0x83,0x0d,0xbf,0xf8,0xb5,0x79,0xfd,0x4b,
+  0x9f,0x79,0xfe,0xc3,0xb9,0x3d,0xea,0xdf,0x7a,0xfe,0x0f,0x4d,0xff,0x0d,0x1b,0xbf,
+  0xcb,0xe7,0x7c,0x64,0x47,0xd1,0x87,0x73,0x7b,0xd4,0xff,0xf3,0x64,0x3f,0x3f,0xb4,
+  0xf5,0x5f,0x38,0xf5,0x3f,0xfe,0x96,0x4f,0xff,0xcf,0x97,0x5b,0x7e,0xff,0xd0,0xff,
+  0xa3,0x4f,0x63,0xf6,0xf9,0x3f,0x34,0xfd,0x4f,0xfb,0xd3,0xc7,0x41,0xaf,0xfc,0xd7,
+  0x0f,0xcf,0xfe,0x5c,0x26,0xfb,0xf9,0xe1,0xad,0xff,0x6b,0x0a,0xaa,0x8c,0x86,0x1d,
+  0xc5,0xcf,0x7c,0x38,0xb7,0x27,0xc0,0x2f,0x9e,0xff,0xc3,0xd2,0xff,0xff,0xec,0x23,
+  0xce,0x0e,0x4c,0x9c,0x1d,0xfe,0x7f,0xfd,0x28,0x7f,0xfc,0xfc,0xf1,0xf3,0xc7,0xcf,
+  0x1f,0x3f,0x7f,0xfc,0xfc,0xf1,0xf3,0xc7,0xcf,0x1f,0x3f,0x7f,0xfc,0xfc,0xf1,0xf3,
+  0xc7,0xcf,0xff,0x17,0x3f,0x31,0x22,0x2e,0xc3,0x5d,0x5d,0x31,0x2b,0x97,0x42,0x8e,
+  0x81,0x11,0xf8,0x9f,0xdf,0x43,0xfc,0x6d,0x41,0x0c,0x52,0x92,0x7b,0xcf,0xd7,0xff,
+  0x3c,0x7f,0xdc,0xff,0x0b,0xeb,0x72,0x85,0xbc,0x58,0x11,0x01,0x00,
diff --git a/u-boot/board/esd/apc405/logo_640_480_24bpp.c b/u-boot/board/esd/apc405/logo_640_480_24bpp.c
new file mode 100644
index 0000000..eb81329
--- /dev/null
+++ b/u-boot/board/esd/apc405/logo_640_480_24bpp.c
@@ -0,0 +1,565 @@
+  0x1f,0x8b,0x08,0x08,0x30,0x72,0x03,0x48,0x00,0x03,0x56,0x6f,0x6c,0x76,0x6f,0x5f,
+  0x53,0x74,0x61,0x72,0x74,0x6c,0x6f,0x67,0x6f,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9d,
+  0x5f,0x70,0x14,0x47,0x7e,0xc7,0x25,0x7b,0x95,0x19,0xb6,0xdb,0x3a,0x9f,0x57,0xc7,
+  0x5d,0x24,0xee,0xb0,0x45,0x4c,0x59,0x96,0xcf,0x04,0x82,0xcf,0x10,0x0e,0xdb,0x01,
+  0xc7,0x94,0x75,0x18,0x9f,0x1d,0xc5,0x87,0x1c,0x22,0xaa,0x8c,0xb8,0x9c,0x51,0x91,
+  0x14,0x92,0xec,0x33,0xc1,0x50,0x8a,0x40,0x25,0x07,0x43,0x9d,0x0e,0x10,0xb7,0x1b,
+  0xa1,0xde,0x55,0x6f,0xf9,0xd1,0x55,0x79,0xc8,0x3d,0xfa,0x2d,0xe5,0x47,0x3f,0xfa,
+  0xd1,0x95,0x37,0x3f,0xfa,0xd1,0x8f,0x4e,0xf7,0xcc,0x74,0xf7,0xaf,0xe7,0xdf,0x4a,
+  0xe2,0x02,0xa2,0xf2,0xfd,0xc0,0x6c,0xcf,0xac,0x66,0x7a,0xfa,0xcf,0xaf,0x7f,0xfd,
+  0xeb,0x5f,0xf7,0xcc,0x1e,0x7a,0xed,0x67,0xff,0x55,0xe9,0xd2,0xfc,0x4c,0x05,0x4f,
+  0xa9,0x70,0xf6,0xa1,0xae,0xae,0xff,0xe9,0xee,0xea,0xea,0xee,0x0a,0xa3,0xef,0xbb,
+  0xfe,0xb3,0xd2,0xf5,0xdf,0xbd,0x5d,0xd1,0x66,0x38,0xf5,0xe8,0x13,0x5d,0x93,0x6a,
+  0x9b,0x56,0xdb,0xa9,0x1f,0xa9,0x7d,0xb5,0x4d,0xab,0xed,0xd4,0xa3,0x43,0xea,0xfb,
+  0x21,0xf5,0xfd,0x50,0xd7,0x05,0xb5,0x9d,0xfa,0x91,0x3a,0x56,0xdb,0xb4,0xda,0x4e,
+  0x3d,0xa1,0xf6,0xd5,0x36,0xad,0xc3,0x1f,0xed,0x56,0xdf,0xed,0x56,0xdf,0xed,0x56,
+  0xdf,0xa9,0x7d,0xb5,0x5d,0xd0,0xfb,0x43,0x6a,0x5f,0x6d,0x17,0x74,0xf8,0xc4,0x7e,
+  0x75,0xbc,0x5f,0x1d,0xef,0x57,0xc7,0xfb,0xbb,0xae,0xa8,0x6d,0x72,0xb7,0x3a,0x56,
+  0xdb,0x85,0xdd,0x7a,0xff,0x90,0xda,0x3f,0xa4,0xf6,0x0f,0x75,0x5d,0xd1,0xfb,0xfb,
+  0xd5,0xbe,0xde,0x76,0x8f,0xa8,0xfd,0x11,0xb5,0x3f,0xd2,0x75,0x45,0x87,0x87,0x54,
+  0xa8,0xb6,0x6b,0x87,0xf4,0xfe,0x9b,0x6a,0xff,0x4d,0xb5,0xff,0x66,0xd7,0x85,0x11,
+  0xb5,0xaf,0xb6,0x6b,0x51,0xf8,0xb6,0x0a,0xdf,0xee,0xba,0xa5,0xb6,0x2b,0x6f,0xaa,
+  0x7d,0xb5,0xdd,0x7a,0x53,0xef,0x9f,0x52,0xfb,0xa7,0xd4,0xbe,0x0a,0xdf,0x56,0xe1,
+  0xdb,0x3a,0x9c,0x54,0xe1,0x64,0xd7,0x1d,0xb5,0x5d,0x3b,0xa5,0xf6,0xd5,0x76,0x47,
+  0x87,0x93,0x7a,0x7f,0x5a,0xed,0x4f,0x77,0x7d,0xa2,0xb6,0x5b,0x93,0x6a,0x5f,0x6d,
+  0x9f,0x44,0xe1,0x05,0x15,0x5e,0xe8,0xba,0x33,0xad,0xc2,0x69,0x1d,0x5e,0x51,0xe1,
+  0x95,0xae,0x4f,0xd5,0x76,0xe7,0x82,0xda,0x57,0xdb,0xa7,0x51,0x78,0x4d,0x85,0xd7,
+  0xba,0x3e,0xb9,0xa2,0x42,0xb5,0xfd,0x51,0x87,0xd7,0xf4,0xfe,0x2d,0xb5,0x7f,0x4b,
+  0xed,0xab,0x50,0x6d,0x9f,0xde,0x52,0xa1,0xde,0xae,0xdd,0x51,0xfb,0x77,0xd4,0xfe,
+  0x9d,0xae,0xcf,0x74,0x78,0x47,0x85,0x77,0xf4,0xf1,0x27,0xea,0xf8,0x13,0x75,0xac,
+  0x42,0xb5,0x7d,0xae,0xc3,0x4f,0x54,0xf8,0x89,0x3e,0xfe,0x54,0x1d,0x7f,0xaa,0x8e,
+  0x55,0xa8,0xb7,0x4f,0xf5,0xf6,0xc7,0xae,0x2f,0xd4,0xf6,0xf9,0x1f,0x55,0xf8,0x47,
+  0x1d,0x7e,0xa6,0xc2,0xcf,0xba,0xbe,0xd4,0xe1,0x67,0x2a,0xfc,0x4c,0x87,0x9f,0xab,
+  0xf0,0xf3,0xae,0xaf,0x74,0xf8,0xb9,0x0a,0x3f,0xd7,0xe1,0x17,0x2a,0xfc,0xa2,0xeb,
+  0xcb,0x2f,0x54,0xf8,0x85,0x0e,0xbf,0x54,0xe1,0x97,0x5d,0x5f,0xab,0xed,0xcb,0x2f,
+  0xd5,0xbe,0xda,0xbe,0x8e,0xc2,0xaf,0x54,0xf8,0x55,0xd7,0x37,0x6a,0xfb,0xea,0x2b,
+  0xb5,0xaf,0xb6,0x6f,0xa2,0xf0,0x6b,0x15,0x7e,0xdd,0xf5,0xf5,0xd7,0x2a,0x8c,0xb6,
+  0x6f,0xba,0xbe,0x55,0xdb,0x37,0xdf,0xa8,0xf0,0x1b,0x1d,0x7e,0xab,0xc2,0x6f,0xbb,
+  0xbe,0x53,0xdb,0x37,0xdf,0xaa,0x7d,0xb5,0x7d,0x17,0x85,0xdf,0xa9,0xf0,0xbb,0xae,
+  0x6f,0xbf,0x53,0x21,0xb6,0x7b,0xbe,0xb5,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0xff,0x1f,0xa4,0x98,0xdc,0xd6,0x99,
+  0xc3,0x42,0xde,0xfd,0x9d,0xd4,0x26,0x64,0x4b,0x2c,0x5d,0x99,0x99,0x78,0xe3,0xa5,
+  0x9f,0x26,0x31,0xff,0xc5,0xfe,0x57,0x4f,0x4c,0x9e,0xbf,0xba,0x2c,0x5a,0x52,0xca,
+  0x76,0xa7,0xbb,0x34,0x4f,0xfc,0x78,0x0d,0xa9,0xdd,0x18,0x3f,0x2d,0xcb,0x63,0x6b,
+  0xf9,0x99,0xce,0x31,0x3c,0x3e,0xd7,0xba,0xeb,0x52,0x52,0x45,0x20,0xa5,0x90,0x62,
+  0xf9,0xea,0x85,0x7f,0x39,0xfe,0xea,0xcf,0x76,0xc4,0x31,0xef,0xf8,0xcb,0xbf,0x19,
+  0x9d,0x98,0x9e,0xbb,0xd1,0x54,0x65,0xd4,0x6e,0x76,0x2e,0xa7,0x07,0x07,0x59,0xdf,
+  0xce,0x18,0x0f,0xd4,0xc6,0x58,0x18,0x7d,0xaa,0x7d,0xfb,0x4d,0xb4,0xaf,0x83,0xf3,
+  0x77,0x7d,0x9f,0x76,0x4b,0x15,0xeb,0xe2,0xd4,0xb1,0xa7,0x75,0xe4,0x9c,0xeb,0x1b,
+  0xc4,0x77,0xe0,0xa1,0x0a,0xfa,0xfe,0x7a,0x6c,0xb6,0xa1,0xce,0xe8,0x14,0xcd,0x28,
+  0x4f,0xd2,0xe7,0x92,0x16,0x7d,0x72,0x73,0xc0,0x6d,0xda,0xb9,0x77,0x46,0x71,0x60,
+  0xb2,0xb9,0xa3,0xe4,0xe6,0x52,0x4c,0x70,0xff,0xda,0x74,0x02,0xa2,0xf2,0xdb,0xdb,
+  0x31,0xfd,0x9d,0x11,0x6d,0xd1,0x98,0x1d,0x3f,0x30,0x10,0xf0,0xb0,0x87,0x27,0x09,
+  0x54,0x9f,0x5b,0x2a,0xc1,0x16,0xc6,0x86,0x8e,0x4e,0xdd,0x10,0xb2,0x73,0x31,0x3d,
+  0x38,0x88,0xf1,0x9e,0xc0,0x2b,0x47,0x66,0x6b,0xce,0x96,0x33,0x67,0xe1,0xae,0xbb,
+  0xcf,0xf2,0xad,0xa9,0x23,0x3b,0x1f,0x8e,0xe3,0x56,0xe2,0x62,0x25,0x46,0x7f,0xa1,
+  0x04,0x3f,0xe4,0x95,0xbe,0x7d,0x27,0x3f,0xea,0xd4,0xb0,0x47,0x49,0xc3,0x88,0x93,
+  0x66,0x84,0x8f,0xc7,0x07,0xbe,0x58,0x18,0x29,0x8f,0x5b,0x56,0x12,0x24,0x67,0xba,
+  0x0b,0xe2,0xa3,0x32,0xf9,0x6b,0x2f,0x6d,0xb3,0xb2,0xca,0x4d,0xbb,0xa1,0xed,0x36,
+  0x11,0xfe,0x99,0xbb,0x2e,0x25,0x79,0x65,0xec,0x67,0xbd,0xac,0x27,0x29,0xa6,0x28,
+  0x6b,0x81,0xad,0x05,0xbd,0x53,0xd9,0xf9,0xda,0x6f,0xeb,0x77,0x7d,0x9b,0x4d,0xc3,
+  0x8d,0x3e,0xa7,0x3f,0x42,0xdb,0xae,0x13,0xf9,0xe0,0x4e,0x2a,0xff,0x59,0x6e,0xb0,
+  0x6f,0xd1,0x9d,0x45,0x53,0xde,0x3e,0xff,0x72,0x5f,0x54,0xe3,0x41,0x1c,0x9d,0x91,
+  0xf3,0xf8,0x0e,0x5a,0x1e,0x2b,0xd1,0x9f,0x7e,0xfa,0x8f,0x57,0x5b,0x2d,0x59,0x28,
+  0x85,0xab,0xa3,0x3c,0xa5,0x7f,0x9c,0xe6,0xa3,0xb2,0x64,0x02,0x5f,0x89,0xe7,0x06,
+  0x56,0x68,0x1f,0x2f,0x94,0x3f,0xa5,0xbb,0x47,0x55,0xe1,0x70,0xbf,0x95,0xfa,0x9f,
+  0x71,0x01,0x0e,0x2f,0x17,0xa7,0xbd,0x73,0x39,0x35,0x5b,0x57,0x4f,0x3e,0xad,0x23,
+  0xab,0x98,0x32,0x22,0xad,0x2d,0x8c,0x8b,0x29,0xfa,0xeb,0x0f,0x5e,0x79,0xaf,0xde,
+  0xd2,0xd6,0xcc,0x06,0xef,0xb5,0x79,0x10,0xc7,0x8c,0x1a,0x70,0x8d,0x98,0xd6,0x11,
+  0x37,0x7f,0x19,0x6c,0x28,0x31,0xda,0xd0,0x2d,0xe4,0x8a,0xb8,0x3c,0x32,0x10,0xc7,
+  0x69,0xb5,0x12,0x55,0x55,0xf6,0xce,0xb1,0x50,0x3d,0x73,0x62,0xa9,0x55,0x68,0xe0,
+  0x8c,0x72,0x7b,0x1e,0xf7,0x35,0x1f,0x67,0x59,0x05,0xc8,0x89,0x44,0x12,0x7d,0x95,
+  0x34,0x34,0xe6,0x72,0xae,0xc3,0x62,0xfd,0x27,0x9b,0x8b,0x7d,0x61,0x46,0xe5,0x59,
+  0x5d,0xe8,0xb4,0x70,0xc8,0xce,0x6c,0xd4,0x34,0x53,0xc6,0xc9,0xed,0x89,0x5d,0x44,
+  0xb1,0x52,0x69,0xe7,0x5e,0x61,0x45,0x37,0xda,0xfa,0xca,0x85,0xe6,0x86,0x65,0x7d,
+  0xd3,0x20,0xaf,0x7e,0xbf,0x27,0x34,0x22,0x60,0x1b,0x1b,0xad,0x15,0xa3,0x6c,0x7a,
+  0x4e,0xad,0xbf,0x07,0x96,0x5a,0x60,0xe5,0xf2,0x6f,0xf7,0x54,0x79,0x25,0x30,0xe2,
+  0xe2,0x2b,0x2e,0xee,0x14,0x61,0x52,0xd2,0xea,0xfb,0xbe,0xd1,0xeb,0x05,0x25,0xdb,
+  0x1a,0xf5,0x5a,0x87,0x8d,0x20,0x55,0x3d,0x4e,0xc0,0x3a,0x6a,0xbe,0xd0,0x7e,0x59,
+  0x22,0x7f,0x2b,0x23,0x41,0x36,0x86,0x1c,0xf5,0xc7,0xc2,0x9f,0x6c,0xa0,0x6b,0x8c,
+  0x4a,0x49,0x2e,0x8e,0xf6,0x25,0x11,0xf9,0x96,0x90,0x67,0x23,0xd8,0xa4,0x87,0xac,
+  0x87,0xed,0x9a,0x7e,0xd0,0x15,0xa0,0x14,0x87,0x3b,0xd5,0x8a,0x15,0x98,0x1f,0xdc,
+  0x5e,0x77,0xf4,0xcd,0xb6,0x6c,0xd5,0xcf,0x0c,0x71,0xd7,0xaf,0x5b,0x05,0xeb,0x0b,
+  0x5f,0x46,0x20,0x6b,0x23,0x0b,0x2d,0x91,0x37,0xcc,0x1b,0x4d,0xd4,0x0d,0xb7,0xba,
+  0x87,0x59,0x15,0xc4,0xd3,0x79,0xe1,0x44,0x55,0x19,0xbb,0x82,0x68,0x2e,0x77,0xeb,
+  0xe8,0xbb,0x6d,0x85,0xf2,0xd7,0x9a,0xaf,0x5a,0x93,0x84,0x5e,0x6f,0x74,0xb1,0x35,
+  0x65,0xd5,0xe7,0xd8,0x06,0xcc,0x14,0xd5,0xf1,0xce,0xbd,0x4a,0x93,0x9c,0x1a,0x40,
+  0x39,0x13,0xc3,0x53,0x0f,0x2c,0x7c,0xea,0xec,0xc6,0xfb,0xfb,0xcd,0x80,0xbc,0x54,
+  0xa1,0x55,0x44,0x3b,0x30,0x5a,0xa7,0xf1,0xdf,0x46,0x55,0x45,0xac,0x37,0xfe,0xe6,
+  0xcc,0x40,0x24,0x7d,0xae,0xa2,0xd2,0x5a,0x29,0x39,0xe0,0xbe,0x51,0x57,0x09,0xd9,
+  0xb1,0xdb,0x39,0x45,0xbb,0x1a,0xf7,0xbf,0x5e,0x67,0x9e,0x19,0x96,0x72,0x4f,0x28,
+  0xdc,0x87,0xaf,0x5a,0xec,0x85,0xa6,0x9a,0x8b,0xf4,0x9f,0x92,0x8e,0xe7,0xcd,0x88,
+  0x8c,0x74,0xf0,0xe9,0x51,0x70,0xfc,0x27,0x5e,0xbb,0xb9,0xee,0x5a,0x10,0xf2,0xe6,
+  0x21,0xed,0x04,0xf0,0x06,0xf1,0xa9,0xb6,0x64,0xeb,0x86,0x9a,0xbb,0xea,0xf3,0xc9,
+  0xf3,0x1b,0x35,0x8b,0x36,0x03,0x62,0x6f,0x0f,0xcb,0x64,0x95,0x76,0xbc,0xc4,0xf6,
+  0x08,0x6b,0xbf,0x5b,0x6f,0x0f,0x2c,0xff,0x30,0xa2,0x7d,0x2d,0x71,0x8c,0x39,0x9d,
+  0xa0,0x89,0x9c,0xbb,0x42,0x4f,0x64,0xa7,0xaa,0xae,0xd9,0xf1,0x61,0x2b,0x57,0xff,
+  0x69,0x2a,0xf1,0xa7,0x91,0x2e,0x62,0xda,0xa5,0xfa,0xc6,0xf8,0x44,0x13,0xb0,0xc8,
+  0xb0,0xaf,0x24,0x27,0xd0,0xe1,0x89,0xba,0x69,0x61,0xff,0x2b,0xcf,0x87,0xae,0xea,
+  0x13,0x5d,0x4e,0x2d,0x09,0x4e,0x2d,0x96,0xf0,0xf5,0xf6,0xfa,0x8a,0x49,0x69,0xf9,
+  0x7f,0xdd,0xae,0xa4,0xaf,0x1a,0x98,0xd2,0x77,0x41,0x60,0x9b,0x07,0x69,0x2a,0x9c,
+  0x28,0x76,0xf6,0x10,0x3f,0xd6,0x90,0xed,0x07,0x52,0x04,0xa5,0x94,0x33,0xa4,0x49,
+  0x85,0x34,0xfb,0x9e,0x61,0x6d,0xf2,0xfc,0xf2,0xfa,0x74,0xbd,0x14,0x73,0x43,0x29,
+  0x8d,0xe3,0x44,0x25,0x8c,0xdd,0x2e,0xd5,0x20,0xf2,0xfe,0xa5,0x07,0xb1,0xd1,0x1d,
+  0x43,0x36,0x5a,0x97,0xe9,0xca,0x1c,0xad,0x24,0xc2,0x54,0x49,0x62,0xf4,0xaf,0xf4,
+  0x92,0xcd,0x9d,0xd0,0x91,0x8f,0xaa,0x3e,0x21,0x74,0xf2,0x6a,0x75,0x72,0xc1,0xf8,
+  0x57,0xae,0x8a,0x61,0x6f,0x38,0xe0,0x8f,0xce,0x32,0x5e,0xc6,0xbe,0x85,0x75,0x15,
+  0x93,0x14,0xcb,0xa3,0x29,0xfb,0xce,0x06,0xaa,0x19,0xc6,0xc9,0x0c,0x74,0x27,0x42,
+  0xbd,0x62,0x34,0x78,0xea,0x92,0xee,0x97,0x1e,0x40,0x09,0x94,0x8d,0x21,0x93,0xa9,
+  0x8c,0xf0,0x51,0xc1,0xb1,0xed,0x7c,0x6e,0x3d,0x05,0xbb,0x2a,0x26,0x7a,0x8d,0xe1,
+  0xe7,0x1b,0xcf,0x11,0xd5,0x03,0x27,0x3f,0xb8,0x3e,0xfb,0x9b,0x91,0x3f,0xb7,0x46,
+  0x1c,0xb1,0xe1,0x92,0xaf,0x82,0x27,0x2f,0xa7,0x4c,0x40,0x59,0x5f,0x5a,0x5a,0xba,
+  0xb5,0x64,0x39,0x5f,0x75,0x62,0xed,0x27,0x5b,0x1f,0x54,0x2f,0x91,0x53,0xcd,0x85,
+  0x37,0xe6,0x26,0xdf,0xda,0x63,0xa5,0xdc,0xe9,0xfc,0xa2,0xfe,0x57,0x8a,0xb3,0xcc,
+  0x0c,0x9e,0x38,0x1d,0xe0,0x64,0x06,0xa5,0x49,0x3a,0x5e,0x6a,0xae,0xa7,0x98,0x9a,
+  0x1f,0xef,0xce,0x76,0xe8,0x46,0x2b,0x07,0x6c,0xe0,0x8d,0xc9,0xcb,0xd7,0x3f,0x38,
+  0x79,0xb0,0x4a,0x6f,0x64,0xd5,0x6f,0xa2,0x76,0x47,0x1f,0xcc,0x71,0xc8,0xca,0x99,
+  0x20,0x6b,0x8a,0xdb,0x5a,0xe4,0x44,0xf8,0xa2,0x12,0xaf,0xb0,0xe7,0xd7,0x3c,0xf3,
+  0xd3,0x94,0xb2,0x31,0x42,0xa6,0x53,0xfc,0xd1,0xaa,0xba,0xc7,0x91,0x79,0xd1,0x6a,
+  0x8b,0x55,0x29,0x96,0xc6,0x9f,0x08,0x79,0x85,0x9e,0x45,0xbb,0xea,0xbe,0x0f,0xd2,
+  0xb7,0x14,0x4a,0x21,0x29,0x93,0x2c,0xfe,0x68,0xcf,0x71,0x5a,0x79,0xb4,0x73,0x8c,
+  0xbe,0x59,0x90,0xed,0x55,0x35,0x08,0x97,0xf4,0x23,0x9a,0x03,0x5c,0x7c,0x67,0x27,
+  0xd1,0xed,0xf1,0xd5,0xdb,0x64,0xae,0x0e,0x91,0x8d,0x27,0x78,0xf1,0x54,0x0a,0xf7,
+  0xc7,0x6a,0x51,0xf7,0x3e,0xbb,0x76,0x33,0xb9,0x29,0x2f,0x0c,0xc4,0xe9,0x75,0x02,
+  0x9d,0x08,0x18,0x7f,0x98,0xf1,0x1d,0x67,0x1a,0x2d,0xd1,0x6e,0x35,0xa5,0x58,0x78,
+  0x29,0x5d,0x88,0x26,0xe3,0x5c,0x69,0xf5,0x97,0xea,0xeb,0x92,0xf9,0xcd,0x81,0x6c,
+  0x0c,0x30,0xaf,0xf4,0x78,0x46,0xf8,0x12,0xa7,0x67,0xf2,0xf7,0xb0,0x7a,0x7e,0xad,
+  0x5d,0x8b,0x5c,0x5d,0xdc,0x43,0x34,0x11,0xb7,0xae,0xb3,0x58,0xe0,0x07,0x2e,0x39,
+  0x5d,0xd3,0x5c,0x7a,0xc1,0x77,0x7c,0xd3,0xb1,0x50,0xd8,0x3b,0x51,0x3a,0xd9,0x34,
+  0xc7,0xec,0xa9,0x19,0xf5,0xc7,0x83,0xca,0xd5,0xa2,0xe6,0xd2,0x6c,0x37,0x8e,0x3f,
+  0xea,0x3c,0x86,0xd1,0x67,0x81,0xfe,0x13,0xe3,0xa4,0x48,0x9c,0xa4,0xd0,0xb1,0x54,
+  0x2a,0xa2,0xb5,0xcf,0xc2,0x49,0x31,0x51,0x73,0x96,0x9e,0x5f,0x1b,0x6a,0xff,0x17,
+  0x75,0xd7,0x24,0xc4,0x74,0x2d,0x4e,0x45,0x40,0x6e,0x68,0x47,0xe1,0xbb,0x6e,0x3d,
+  0x78,0x53,0x72,0xe2,0x44,0xe2,0xf6,0xa3,0xae,0x0c,0x7f,0x0e,0x98,0x9b,0xe2,0x48,
+  0x32,0x3b,0x2c,0xd6,0x98,0xcd,0x95,0x7f,0x1b,0x70,0xd7,0xb9,0x22,0x8d,0x5b,0x6e,
+  0xf7,0xee,0xdf,0x4b,0x57,0xb0,0x52,0x8a,0xb1,0x6a,0x56,0xf3,0x25,0xf7,0x55,0xc3,
+  0xee,0x52,0xf9,0xab,0x90,0x04,0x7a,0x52,0x12,0x45,0x51,0x28,0x7f,0xda,0xdd,0x7b,
+  0x79,0xc8,0xaf,0xf9,0x02,0xfb,0xef,0x66,0xbf,0xd2,0xfc,0xd6,0xe1,0x9d,0x4a,0x1f,
+  0x0d,0x6c,0x69,0xb2,0x99,0xb5,0xf6,0x12,0xcb,0xc7,0x2a,0xc6,0xc0,0x73,0x7a,0xcd,
+  0xcc,0xde,0xb0,0x77,0x49,0xb7,0xda,0x94,0xcd,0x85,0xa1,0x8a,0x57,0x4a,0xa4,0xc1,
+  0x85,0x7c,0x70,0xe1,0x41,0xd3,0x80,0x32,0xf2,0xe9,0x67,0xfb,0x2f,0xa3,0x3d,0xa2,
+  0xaf,0x46,0x76,0xd0,0x52,0x09,0xd8,0xe4,0x5a,0x32,0xa9,0x3a,0xc6,0x0b,0x35,0x6e,
+  0x86,0x98,0x9e,0xb3,0x2c,0x8a,0x7c,0x57,0x83,0xcc,0xe5,0xa9,0xee,0x55,0xb4,0x4e,
+  0xb2,0x8c,0xe6,0x63,0x66,0xea,0xb3,0xe7,0x68,0x89,0x75,0x33,0xeb,0x52,0x1d,0xa6,
+  0x84,0x4f,0xc7,0x77,0xb5,0xe8,0x4a,0x25,0xfd,0xab,0xf2,0xe6,0x4e,0xe3,0xad,0x89,
+  0x92,0x96,0xab,0xff,0x84,0x7c,0xc3,0x17,0x6c,0x9e,0x0e,0xd4,0x67,0xef,0xaf,0x88,
+  0x9d,0xa2,0x06,0x37,0x3b,0xff,0x63,0x4d,0xb2,0x20,0xc5,0xc1,0x90,0xa5,0xa4,0xd8,
+  0xf4,0xf4,0x2c,0x2e,0x6b,0x22,0x54,0x42,0xfe,0x7e,0x90,0x78,0x90,0x38,0xc9,0xb3,
+  0x9e,0x1e,0xe8,0x5f,0xc8,0x37,0x1f,0x36,0x2b,0xad,0xf6,0x51,0xaa,0x95,0xb8,0x27,
+  0x7c,0xc9,0x1f,0x7a,0xb6,0xde,0x9c,0x32,0x23,0xb0,0xf8,0x8f,0x3b,0xea,0x6b,0x28,
+  0x59,0x29,0x17,0xfb,0x73,0x5d,0xc2,0xba,0xb6,0x78,0xb8,0xfd,0x7a,0x5a,0x3d,0x48,
+  0x31,0x12,0xfa,0x0d,0x81,0xb4,0x6d,0x55,0x11,0xc5,0x13,0x13,0x46,0xff,0x71,0x92,
+  0x76,0xa2,0xcd,0xaf,0x96,0x25,0x53,0xb4,0x6f,0x3c,0x6d,0xee,0xa2,0x6b,0xf1,0xf1,
+  0x1c,0xb3,0x4d,0xca,0x8f,0x6b,0xdd,0xf9,0x63,0x5f,0x12,0x8c,0x35,0x86,0x7c,0xc3,
+  0xf9,0x9f,0xd6,0x62,0x01,0xca,0xe6,0xb8,0xeb,0xc6,0x5d,0x6f,0x1e,0x1f,0x85,0xec,
+  0x55,0xa1,0x6c,0x5c,0x8f,0x95,0xf9,0xa8,0xb3,0x4e,0x4f,0x98,0x26,0xee,0x8b,0xe1,
+  0x0d,0x4f,0x90,0xde,0x17,0xe4,0x7c,0x6f,0x40,0x73,0x91,0x12,0xbe,0xb8,0x0e,0xc7,
+  0xa5,0x78,0x96,0x9b,0xe3,0xe8,0xcc,0x7f,0x5c,0x4b,0x07,0xdc,0xd8,0x1b,0x79,0x55,
+  0x88,0xd4,0x11,0x8b,0xb2,0x77,0x36,0xe3,0xd6,0x13,0xb2,0xbe,0x27,0x74,0x86,0x5c,
+  0xaa,0x6d,0x87,0x7d,0xf3,0x85,0x37,0x9d,0x73,0x2a,0x23,0xe3,0x1b,0x66,0x25,0xf6,
+  0x5f,0x52,0x06,0x97,0x6b,0x64,0x7e,0x2b,0xb7,0xff,0x6d,0x1e,0xb6,0x91,0x73,0x3b,
+  0xad,0xe7,0x4f,0x1f,0x07,0x03,0xb7,0xda,0x33,0xe4,0x24,0x75,0xf3,0x81,0xfa,0x1a,
+  0x24,0x41,0x5e,0xee,0xf5,0x92,0xeb,0x75,0xf1,0xe1,0xce,0xdb,0xe9,0xa4,0x2b,0x9b,
+  0x65,0x9a,0xf1,0x3f,0x8b,0xcf,0xf5,0x84,0x2f,0xd6,0xa2,0x47,0x1e,0x24,0x13,0x50,
+  0x8a,0x97,0xfc,0x9a,0xe3,0xa9,0x7a,0xd7,0xdf,0x3f,0x79,0xbb,0x2d,0x3e,0x24,0xfa,
+  0x50,0xfd,0xb1,0xef,0x56,0xe7,0x75,0x30,0x62,0xd4,0xac,0x72,0xf1,0x4d,0xa6,0x58,
+  0xb8,0x46,0xf5,0x10,0x36,0x73,0xc9,0xbf,0xbb,0xee,0xd9,0x17,0x23,0x2d,0x94,0x83,
+  0xb7,0xda,0x05,0x82,0x94,0xd2,0x7f,0xb6,0x47,0x4c,0x64,0xb9,0x5c,0xfe,0x9a,0x32,
+  0x9a,0x4e,0x36,0x57,0xe7,0xf5,0xbf,0x62,0x8e,0x39,0x09,0x4f,0x69,0x3d,0xeb,0x29,
+  0x3e,0xad,0x2c,0x88,0xe7,0x38,0x4d,0x72,0xcf,0xaf,0x3a,0xc9,0x82,0x4a,0x57,0x7d,
+  0x28,0x8e,0x82,0x2e,0x6b,0x30,0xfd,0xd1,0xc3,0xec,0x52,0x36,0x06,0x35,0x80,0x3f,
+  0x14,0x92,0x06,0x47,0x8b,0x4a,0xd7,0xda,0xc4,0x6a,0xce,0x8d,0x36,0x29,0xf2,0x12,
+  0xeb,0xce,0xf1,0x1e,0x50,0x6d,0x18,0x56,0xcf,0xb6,0x54,0x27,0x71,0xd0,0x0d,0x46,
+  0xf5,0xb7,0x6f,0xe4,0x48,0x8f,0x47,0x53,0xce,0x54,0x2b,0xfe,0x44,0x26,0xd5,0xab,
+  0x03,0x4b,0xb9,0x97,0x8b,0x11,0x57,0xb0,0x21,0x51,0x32,0xb1,0x6f,0xe2,0xa5,0x4c,
+  0x5f,0x94,0x10,0xc9,0x5f,0x98,0x49,0xba,0xf9,0xec,0xa4,0xff,0x9a,0x8d,0x1d,0x6e,
+  0x54,0x9e,0xa7,0xff,0xc4,0x5e,0x2b,0x54,0x39,0x7d,0x65,0x9c,0xb5,0xc1,0x65,0x75,
+  0xde,0x2c,0x6d,0xc7,0x8c,0xd7,0x6e,0x74,0xe8,0x0b,0x95,0x8d,0xfc,0x9a,0x6d,0x95,
+  0x36,0xd1,0xb6,0x3e,0xc2,0x91,0xdc,0x61,0xbf,0xfc,0xa8,0xe6,0x8d,0x51,0x88,0xe3,
+  0x91,0xf1,0x6a,0xdf,0x5c,0xfb,0x81,0x91,0x40,0xf1,0x57,0xa1,0xad,0x28,0x32,0xb3,
+  0x6e,0x65,0x45,0x67,0x50,0xaf,0x39,0x5d,0x95,0xf3,0x55,0xaf,0x95,0x15,0xdb,0xf4,
+  0x86,0xfa,0x8e,0xf4,0xc4,0x39,0x77,0x02,0x52,0x79,0x27,0x5f,0xfc,0xda,0xbf,0xeb,
+  0x23,0xe7,0xa6,0x14,0x0d,0x0f,0x7e,0x9b,0xaf,0x74,0xe5,0x6c,0x4a,0x15,0xa5,0x5c,
+  0x13,0x1d,0xd2,0xaa,0x9a,0xd2,0x49,0x27,0x01,0x59,0xfd,0x27,0xdb,0xef,0x15,0xa4,
+  0xc9,0x0a,0x9f,0x62,0x4a,0xdd,0xa4,0x25,0x0f,0xd3,0xbf,0x2b,0xeb,0xad,0xd3,0x2c,
+  0x5c,0x6b,0x96,0x73,0xa7,0xfe,0xa8,0xdb,0x41,0x07,0x03,0x05,0xfe,0x14,0x79,0x2c,
+  0xe3,0x53,0xb0,0xc3,0xef,0x80,0xed,0x79,0x50,0x7a,0x60,0xd9,0x3e,0xc7,0x69,0x7b,
+  0x4d,0x09,0x5f,0xfc,0x55,0xe5,0x5f,0xb5,0xc3,0xb6,0xdd,0x1e,0xe1,0x4e,0xc1,0xa8,
+  0xed,0xa5,0x9c,0x59,0x59,0x1a,0xb5,0x98,0xd0,0x9a,0xd5,0x17,0x0a,0x73,0x97,0x90,
+  0x0d,0x34,0x72,0xaf,0x96,0x6d,0xf1,0x46,0x4f,0x95,0xce,0xb0,0x52,0x6d,0xc3,0x82,
+  0x5d,0x05,0x63,0x60,0xad,0xff,0xb8,0x9f,0x01,0x2a,0x31,0xa5,0xe3,0x0f,0x9d,0x37,
+  0x71,0xcd,0xd5,0x7e,0xd6,0xff,0x2c,0xc5,0x90,0x89,0x96,0xaa,0x3e,0xbf,0xe3,0xdb,
+  0xb3,0x12,0x9d,0xfa,0x51,0xaf,0x73,0x23,0xab,0xbf,0x54,0x17,0x3a,0x88,0xbe,0xd8,
+  0x13,0x64,0x1e,0x72,0x60,0xd6,0x58,0x9e,0x68,0xe6,0x6a,0xee,0xa6,0x5c,0xac,0x11,
+  0x9f,0x82,0xb5,0x41,0x79,0xb2,0x3a,0x7a,0xe6,0x01,0x59,0x0d,0x23,0x1b,0x4f,0xd2,
+  0xfa,0xf2,0x17,0xe1,0x99,0xfa,0x7f,0x21,0xae,0x73,0xb1,0x58,0x33,0x85,0x1a,0x17,
+  0x70,0xb9,0x7b,0x5f,0x2e,0x0d,0xb8,0x28,0xa9,0xe5,0x14,0x5f,0x3c,0x52,0x30,0x83,
+  0xd2,0x6c,0xcf,0x06,0xd5,0x8c,0x39,0xe0,0x22,0x99,0xca,0xbd,0xa9,0x9c,0x63,0x44,
+  0xde,0xa8,0xe6,0x8b,0x22,0xea,0x34,0xfe,0x50,0xdd,0x95,0xd8,0x65,0x6f,0x93,0xd1,
+  0x7f,0x52,0x4c,0xd2,0x86,0xe4,0x8f,0x15,0x6c,0xdb,0xbd,0xa4,0x6f,0xd1,0x94,0xe2,
+  0x97,0x64,0xb4,0x1f,0x32,0x7e,0xb0,0x7c,0x4e,0x4c,0x4e,0x5a,0xf3,0xd8,0x77,0xea,
+  0xc4,0xf7,0xb8,0x51,0x74,0x59,0xf3,0xb0,0x97,0x8c,0x54,0x71,0x0d,0x8b,0x07,0x63,
+  0x04,0x2c,0x27,0xf4,0x0a,0x46,0x6f,0x09,0x5d,0x26,0x43,0xbd,0xa6,0x05,0x8b,0x31,
+  0xd3,0x32,0xe3,0x82,0xdf,0x5b,0x6a,0x64,0x88,0x31,0xe7,0xad,0x35,0x03,0x69,0xdb,
+  0x67,0x84,0xec,0x82,0x9e,0x01,0xcb,0xbf,0x70,0x90,0x34,0x07,0x67,0x91,0x27,0x09,
+  0xdb,0xd1,0xc8,0xbd,0xc8,0xd9,0x7f,0x3c,0x2d,0x7c,0x6b,0xb0,0xff,0x74,0x49,0xbc,
+  0xd1,0x63,0xd4,0x59,0xc6,0xfe,0x13,0xf5,0xed,0x3c,0xd5,0xb5,0x73,0x17,0x24,0x19,
+  0x7a,0x21,0x76,0xd1,0xc9,0xe6,0x52,0x8d,0x2e,0xfb,0x67,0x95,0x8b,0xa5,0xb7,0x5e,
+  0x1a,0xe0,0x79,0xee,0x87,0x24,0xf6,0xbd,0x45,0x4d,0xbc,0x29,0x2f,0x55,0x79,0x95,
+  0xae,0xbf,0x31,0x5d,0x44,0x54,0x00,0x3d,0x93,0x7f,0x82,0x07,0xf0,0xee,0x01,0xb7,
+  0xfb,0x8d,0x34,0x59,0x05,0x43,0x85,0x2f,0xca,0xdc,0x51,0x53,0x1d,0x4a,0xa3,0x71,
+  0x57,0x3a,0xea,0xa4,0xf7,0xcb,0x5c,0xed,0xb7,0xcd,0x2a,0x5e,0xab,0x8e,0x48,0xd1,
+  0xb2,0x81,0xe5,0x62,0x89,0x78,0x23,0xb5,0x4c,0x95,0xa6,0xaf,0x87,0x9f,0xcb,0x5d,
+  0x7d,0x38,0xcb,0xb2,0x67,0x13,0x4b,0xa2,0xb3,0xfc,0xad,0xfe,0xda,0x9e,0xed,0xeb,
+  0x3f,0x75,0xa1,0x7c,0x3b,0xa7,0x6b,0x4f,0xb9,0xaa,0xd8,0x42,0x7c,0xb6,0xea,0x2f,
+  0xc7,0xe8,0x9f,0x2b,0xe1,0xee,0x62,0x63,0x4c,0x9f,0x9c,0xac,0x6d,0x31,0x31,0xf9,
+  0xeb,0x2e,0x26,0x0a,0x92,0xad,0x5a,0xbe,0x48,0xad,0x29,0xf2,0x6a,0xb0,0x7b,0xe8,
+  0x81,0xb0,0x00,0x57,0x8f,0x07,0x4e,0x57,0xa4,0x84,0xcf,0xc8,0x60,0xcd,0x75,0x01,
+  0x72,0xa2,0xe2,0xe9,0x97,0xa1,0xe5,0x92,0x5a,0x9d,0xf6,0x2c,0xc9,0x44,0x10,0xed,
+  0x88,0xf1,0x95,0xe2,0x0b,0x5b,0x97,0x9c,0x06,0x70,0x46,0x8d,0x19,0xdc,0x05,0x07,
+  0xf3,0x06,0x94,0xd2,0xcd,0xff,0xe6,0x38,0xd1,0x3b,0xfa,0xff,0xf4,0xf0,0xea,0x43,
+  0x9b,0xca,0x94,0xff,0xb9,0x29,0x6f,0xd6,0x3c,0xe5,0x92,0x09,0xf4,0x04,0xe5,0x51,
+  0x7b,0x03,0x59,0x7f,0xdc,0x24,0x3c,0xf2,0x5a,0x56,0xa7,0x0b,0x75,0x91,0x94,0xcd,
+  0x21,0xaa,0xea,0x19,0x15,0x3e,0x9d,0x85,0xeb,0xc5,0x29,0x96,0x63,0x46,0x6f,0x72,
+  0x7f,0xf8,0x1b,0xe5,0xba,0x7a,0xf9,0x01,0x30,0x00,0x5b,0xbf,0xaf,0x71,0x3a,0x2e,
+  0xf0,0xb2,0x60,0x3a,0x4e,0xb7,0x8e,0x5c,0xae,0x34,0x86,0x9c,0xb2,0x54,0x65,0xfe,
+  0xd0,0x99,0x02,0x6f,0x88,0x42,0xbc,0x1c,0x2f,0xec,0x63,0x8c,0x0a,0x9f,0xb9,0x38,
+  0x9c,0x28,0xee,0x1f,0x64,0xbd,0x46,0x2a,0x21,0x1d,0xf0,0xc7,0x6e,0xe5,0xc9,0x92,
+  0x9d,0xff,0x65,0x24,0x81,0x64,0xfc,0xdb,0xb9,0xff,0xbd,0x6a,0xaf,0x4c,0xf5,0xbf,
+  0xb2,0x79,0xac,0x70,0xc9,0x5d,0x12,0x04,0xac,0x76,0xc3,0x5d,0xb4,0x32,0x69,0xfe,
+  0x18,0x44,0x02,0x32,0x98,0x3f,0xd4,0x6a,0x6b,0xd1,0x9e,0x8f,0xce,0xf1,0x54,0x29,
+  0x69,0x3f,0x03,0x25,0x5a,0xac,0x35,0x93,0xb7,0x5a,0x32,0xb9,0x3c,0x64,0x6f,0x75,
+  0xc8,0xef,0x26,0x40,0x8a,0x5f,0xd8,0x64,0xa7,0xd7,0x55,0x1a,0x67,0x5d,0xb0,0xdd,
+  0xb3,0xb7,0xa6,0x9c,0xbf,0x4b,0x17,0xd0,0x8f,0x8b,0x66,0xe1,0x64,0xb3,0x5e,0xf3,
+  0x9c,0x2e,0xae,0x77,0x88,0x84,0xbc,0x72,0xa9,0x2c,0x5d,0xcf,0xbb,0xc7,0x39,0x3c,
+  0x4f,0x5b,0xec,0xb8,0x39,0x9b,0x37,0xee,0xb6,0xf6,0x9f,0x3f,0x85,0x6f,0x3e,0x3b,
+  0xca,0x9f,0x1a,0x50,0x56,0x8d,0x19,0x9c,0xea,0x7f,0xe5,0x47,0x8f,0x38,0xe3,0x35,
+  0x33,0xeb,0x9b,0xa4,0xcb,0x7b,0xda,0x43,0x0c,0xf9,0x73,0x63,0x13,0x45,0xcd,0x54,
+  0x46,0x7d,0xb5,0x3f,0x61,0x4d,0x4c,0x95,0x9e,0x7d,0x25,0x53,0xb9,0xf2,0x7a,0x85,
+  0x79,0x7d,0x04,0xb1,0xb0,0xf5,0xa2,0xf1,0x07,0xa0,0x03,0x9e,0xaf,0x9a,0x32,0x32,
+  0x99,0xe6,0xee,0x28,0x96,0x1e,0x7f,0xa1,0x41,0x33,0x72,0x16,0xd8,0x02,0x0a,0xab,
+  0x63,0x85,0x05,0x3b,0x45,0x84,0x8f,0xf4,0x0e,0xe6,0xda,0x7c,0xe7,0x73,0x7c,0x13,
+  0xf9,0x0f,0x44,0x09,0xa7,0xdb,0x37,0x67,0x07,0xf2,0x2e,0xcd,0xd1,0x7f,0x74,0x16,
+  0x64,0x0d,0xfa,0xef,0xfa,0xc3,0xe6,0x42,0x5f,0xff,0x49,0x71,0x38,0x24,0x71,0xe6,
+  0x69,0x9c,0x6a,0xc5,0x9b,0x67,0x93,0xcd,0x0f,0x48,0x47,0xaa,0x94,0x51,0x7f,0x66,
+  0x0a,0xcd,0x9e,0xb9,0x93,0x34,0x78,0x4f,0x13,0x44,0x05,0x37,0x5a,0x96,0x6a,0xf1,
+  0xc3,0xa2,0xf4,0x44,0x9f,0xb3,0x1d,0x32,0x7c,0xff,0xd1,0x33,0x1a,0xb4,0x9f,0xe3,
+  0xa9,0x3c,0x68,0x81,0x79,0x5a,0x78,0xee,0x03,0x79,0xd1,0x77,0x7e,0xf5,0xdd,0xcc,
+  0xaf,0x58,0x21,0x47,0x2b,0xd9,0x27,0xe8,0xb8,0xf5,0xe9,0x6c,0x2b,0xee,0xb8,0xf5,
+  0x63,0x16,0xf6,0x12,0xeb,0x49,0x23,0x9a,0xa1,0x96,0xa7,0x13,0x8c,0xfe,0xe3,0x9e,
+  0xd8,0xad,0x53,0xff,0x25,0x57,0x10,0xd5,0xa1,0x9f,0x98,0xbf,0xd4,0x5b,0x89,0xf3,
+  0x40,0x2c,0x4b,0x3f,0x60,0xfc,0x37,0x44,0x64,0x95,0xce,0x12,0xcf,0xb9,0x8e,0x54,
+  0x27,0x5c,0xc9,0x51,0x7e,0x7e,0x6f,0xb9,0xb1,0x2b,0x75,0x10,0x98,0xb4,0x9f,0x2d,
+  0x2b,0xa6,0x95,0x7d,0xdd,0x8c,0xf4,0x11,0x69,0x6f,0xe9,0x44,0x79,0x86,0xef,0x3f,
+  0x49,0x35,0xdb,0xb1,0xbe,0x13,0x42,0xa3,0xc5,0x15,0x1f,0xa4,0x0a,0x40,0xbc,0xc0,
+  0xb6,0xb8,0x46,0xc6,0x83,0x63,0x05,0xde,0x2d,0xf9,0x32,0x1d,0x2b,0xfa,0xcf,0x04,
+  0xa9,0x60,0xb8,0x64,0x56,0x40,0xb6,0xe7,0x49,0x1a,0x7c,0xf3,0x20,0xfa,0x2a,0xaf,
+  0xd3,0x37,0xfe,0x3f,0x1a,0x38,0xa7,0x44,0xe7,0xf1,0x47,0xbb,0x1d,0xe9,0xbf,0xe8,
+  0xca,0x41,0x92,0x27,0xa9,0x67,0xde,0x4c,0x63,0x2c,0xd0,0x34,0x01,0xdf,0xb9,0x9c,
+  0xca,0xc2,0x2c,0xab,0x90,0x16,0x10,0xd4,0x16,0xf3,0x9d,0x4d,0x72,0xc1,0xd7,0x00,
+  0xcc,0x0a,0x5f,0x6c,0x6a,0x7c,0x50,0x36,0x79,0x22,0x5f,0x28,0xea,0x23,0xa2,0x9c,
+  0x8f,0x75,0xca,0xf0,0xfd,0x46,0x3c,0x4b,0x47,0xfc,0xe9,0x1a,0x8f,0x67,0x39,0xfe,
+  0x3a,0x95,0xff,0x55,0x39,0xff,0x08,0x5d,0xfa,0x13,0xf4,0x16,0xbc,0xa8,0x45,0x3c,
+  0x47,0xcd,0x37,0x57,0x2a,0x71,0xc4,0x95,0xe7,0x4a,0xc4,0x41,0xb6,0x17,0xfd,0x2b,
+  0x52,0x23,0xe8,0xca,0xb5,0x9c,0x8b,0xf2,0xec,0x3f,0xd2,0xa5,0xad,0xc1,0xff,0x52,
+  0x3f,0x77,0x6e,0x2a,0xfe,0x37,0x43,0x32,0x2d,0xe4,0x4c,0xd5,0xb3,0x46,0x49,0xe0,
+  0xf4,0xfb,0x4c,0x6a,0x34,0x25,0xc4,0x61,0x2b,0x4a,0x91,0xe0,0x8e,0xe4,0xcb,0xd1,
+  0xea,0x79,0xd3,0xaa,0xe8,0xcc,0xba,0xab,0x8f,0xd9,0x32,0xdf,0xb5,0x1c,0xe9,0x31,
+  0xe9,0x22,0x5a,0xc3,0xa6,0xeb,0x48,0x87,0x0c,0xdf,0x67,0xa4,0x98,0xa6,0xb9,0x4d,
+  0x75,0xc3,0x89,0x4f,0xf4,0x91,0xb9,0x94,0xfa,0x53,0xea,0xe0,0x28,0xa7,0xd7,0xf0,
+  0x83,0xf9,0x4d,0x54,0x6e,0x27,0xad,0xd1,0x0d,0x22,0x8c,0x4c,0x1d,0x2c,0x29,0x57,
+  0xd1,0xbe,0xcd,0xa8,0x04,0x11,0x83,0x5c,0xef,0x76,0xf3,0x8b,0x39,0x17,0xe5,0xda,
+  0x7f,0xce,0xea,0xec,0xdc,0xff,0x46,0x93,0xc0,0xd1,0x26,0x05,0x71,0x30,0xca,0xfa,
+  0x10,0x4f,0x3d,0x63,0xe4,0x8d,0xb1,0xa3,0xd1,0x6f,0x7a,0xba,0xb5,0xa5,0x46,0xd3,
+  0x35,0x62,0x34,0xaa,0xdd,0xf9,0xfc,0x69,0x9b,0xc9,0xec,0x62,0x09,0x6a,0x2c,0xcf,
+  0x97,0x24,0xbb,0x29,0x47,0xbb,0xbd,0x36,0xe6,0x05,0x9c,0xed,0x2b,0xcf,0xf0,0xfd,
+  0xa6,0x55,0x7f,0x92,0xe6,0x97,0xda,0x67,0xe6,0x28,0x7f,0xf2,0xfc,0x46,0x9f,0xeb,
+  0xad,0x55,0x50,0xcd,0x93,0x86,0xb6,0x6c,0x6c,0xf5,0x1e,0x46,0xf3,0xfb,0xe1,0x80,
+  0xfd,0x6d,0x99,0x7b,0x5e,0xd6,0xfb,0x32,0xb6,0x38,0x35,0xe8,0xa6,0x4a,0xc6,0xbf,
+  0xbe,0x79,0x6a,0xac,0x84,0x35,0xe8,0xbf,0x7c,0x56,0xe5,0x24,0x91,0x0b,0x5f,0x05,
+  0x5a,0x57,0x40,0x30,0x9b,0x5d,0xb0,0xd0,0xfc,0xa5,0x37,0x6c,0xe7,0xe9,0x8e,0x24,
+  0x39,0x6d,0x2c,0x35,0x7e,0x4d,0xcd,0xf0,0x2d,0x96,0x16,0xd3,0x18,0x6d,0x63,0xb6,
+  0x8b,0x30,0x25,0xf5,0x17,0x1b,0xca,0xf0,0x3d,0x43,0x4c,0xb8,0x15,0x4b,0xe9,0x67,
+  0x68,0x4c,0x36,0x6a,0x8b,0x39,0xa5,0xb6,0x12,0xbb,0xf7,0xad,0x9b,0x3a,0xf7,0x21,
+  0x1b,0x29,0x6a,0x5e,0xc7,0x4b,0xba,0x79,0x7d,0x50,0x79,0xa5,0x74,0x60,0x57,0xef,
+  0x73,0xc2,0x94,0xd2,0x0f,0xfa,0xab,0x5c,0xf9,0xcb,0xea,0x26,0xd2,0xfd,0xad,0xc5,
+  0xfe,0xcb,0x25,0x99,0xf2,0xc9,0x9b,0x8c,0x36,0xe6,0xc4,0x9f,0xb1,0x17,0xf3,0xba,
+  0x80,0x1b,0x35,0x72,0xb2,0x4a,0x49,0xee,0x7b,0x13,0x57,0xc7,0xb3,0xfa,0x8f,0xae,
+  0x22,0x2b,0x7a,0xfb,0x4d,0x94,0x34,0x31,0xe6,0xab,0x65,0xda,0xd0,0x55,0xf0,0xf4,
+  0x86,0x32,0x7c,0xaf,0x50,0x05,0x5b,0x09,0xb3,0x09,0xf7,0x6c,0xe1,0xf0,0x78,0xde,
+  0xeb,0xa7,0xa2,0x75,0x05,0xa1,0x2d,0xa2,0x90,0xcd,0xe4,0x2c,0xf7,0x96,0xab,0x3b,
+  0xad,0xb8,0x38,0xab,0xd2,0x69,0xa5,0x17,0x4a,0xed,0xbf,0x25,0xe6,0xa5,0xc8,0x9a,
+  0x59,0x89,0x3c,0xe6,0xf9,0x0e,0xcd,0xfa,0x17,0xee,0x29,0xaa,0x75,0xd8,0x7f,0xf9,
+  0x29,0x69,0x1e,0xe7,0xcc,0x3e,0x89,0x9b,0x5a,0xf4,0x6c,0xfa,0x80,0xde,0x85,0xbc,
+  0xc8,0xa3,0xa7,0xe5,0xac,0x66,0x2a,0x78,0x6f,0xa2,0x98,0x0a,0x7d,0xfb,0x8f,0xce,
+  0xf3,0xa9,0xfd,0xf9,0xb2,0x54,0xcb,0xd7,0xc9,0x1d,0x78,0x26,0x8d,0x9b,0xbb,0xff,
+  0x15,0xe6,0xfd,0x29,0x64,0xdc,0x9b,0x1a,0x88,0xf0,0x81,0x5b,0x79,0x57,0xb6,0xe4,
+  0x84,0x2b,0x22,0x7d,0xc5,0xce,0xdc,0x67,0xe1,0xcc,0x0b,0x3d,0x8c,0x18,0x70,0x4f,
+  0x2b,0x3d,0x57,0x92,0x34,0xb9,0xba,0xe8,0x04,0x8e,0xd4,0x87,0x89,0xad,0xb2,0xb8,
+  0xe6,0xf1,0xaf,0xa9,0xd8,0x8d,0xe9,0xbf,0xd5,0xb6,0xb8,0xb1,0x35,0xcc,0xea,0x60,
+  0x1a,0x28,0xf1,0x1c,0xc9,0x77,0x12,0x37,0xb6,0xd3,0xd3,0x82,0xea,0xd9,0xbc,0x69,
+  0xeb,0x0b,0xd9,0x25,0x85,0x9c,0x7c,0x7e,0x58,0xda,0x4d,0x8c,0x14,0x18,0xa5,0xf1,
+  0xe7,0xc8,0xfa,0x33,0x7c,0x0f,0xb9,0x96,0x99,0xd2,0x24,0x26,0x5a,0x72,0xf4,0x9b,
+  0xfc,0x41,0x9b,0x6c,0x3c,0xe5,0x39,0xad,0x7a,0x26,0x72,0x9c,0x0b,0xf2,0x65,0xaa,
+  0xb9,0x9c,0xa9,0x94,0x0c,0x62,0x87,0xcb,0xdc,0x7f,0x91,0xff,0xc5,0x95,0xa9,0x91,
+  0x74,0xab,0xa6,0x73,0x06,0x85,0xb2,0xcc,0xfe,0xdb,0xb8,0xfe,0x13,0xc7,0xe8,0x92,
+  0x1a,0x9e,0x3b,0xce,0xec,0x2b,0x58,0x21,0xda,0x3a,0x4b,0x4c,0x3a,0x1e,0xf0,0xbc,
+  0x59,0xb8,0xd5,0x6b,0xcc,0x19,0xc5,0x4e,0x03,0x58,0x5f,0xcf,0xfb,0xa5,0xfa,0xef,
+  0x85,0x74,0x96,0xad,0x06,0xd5,0x3b,0x6f,0x6f,0x20,0xc3,0xf7,0x0a,0x29,0x5e,0xed,
+  0x76,0xf6,0x14,0xb3,0x7a,0xc9,0xeb,0x2e,0x87,0x1a,0xb9,0x8b,0x18,0xd5,0x20,0x71,
+  0x26,0xa0,0x4d,0x8e,0x0f,0x2c,0x65,0x4f,0x92,0x7f,0x4f,0x84,0xc7,0x13,0x86,0xe8,
+  0x9b,0xd2,0x57,0x2c,0x37,0x2f,0x32,0xbf,0x38,0xbd,0x34,0x56,0x1e,0xcf,0x9b,0x7f,
+  0xcb,0x5b,0xff,0x42,0x44,0x7e,0x43,0xf2,0xd7,0x94,0x0b,0xbd,0x41,0xda,0x3d,0x97,
+  0x09,0x8e,0x17,0x2c,0xf5,0x14,0xe2,0x2f,0x49,0x9b,0xe6,0xf9,0xef,0x4d,0xbc,0xdd,
+  0x9b,0x35,0x70,0x49,0x37,0x71,0xb6,0x6c,0xfc,0x21,0x9e,0xcf,0x7b,0xd2,0x20,0x89,
+  0x21,0x64,0x67,0xd7,0x9f,0xe1,0x7b,0x86,0x9c,0xfb,0x1e,0x15,0x3e,0x9e,0x36,0x5e,
+  0x75,0xb3,0xe5,0x33,0x85,0x2f,0x1c,0x10,0x7b,0xad,0x0e,0x88,0x64,0xe4,0x78,0x3b,
+  0xa3,0x01,0xc5,0x87,0x19,0xe1,0xb3,0x5e,0x05,0xfd,0x7d,0xd9,0x3b,0x04,0xe5,0xc9,
+  0x8a,0x5f,0x9c,0xbe,0xff,0x66,0x24,0x6f,0xd5,0x97,0x79,0xfe,0x2d,0xdf,0xfe,0xdb,
+  0xe0,0xf8,0x43,0xbc,0x68,0x6e,0x9b,0x5e,0xf1,0xe7,0xac,0xd1,0xed,0xb7,0x0b,0x17,
+  0xa1,0xbd,0xe7,0x8d,0xa1,0xc2,0xfe,0xa5,0x8c,0xd2,0x97,0xcd,0x3d,0xcc,0x59,0x7b,
+  0x46,0xf8,0xec,0x5d,0xca,0xe7,0xdf,0x56,0x7e,0x98,0x1a,0x36,0x5b,0x8b,0x25,0x8a,
+  0xa0,0x64,0xe9,0xcc,0x7d,0x47,0xec,0x73,0xba,0xce,0xf7,0xfc,0xd9,0x4e,0x93,0xef,
+  0x2d,0x9c,0xfb,0x91,0xf2,0x12,0xd5,0x01,0x21,0xaf,0xfd,0x2e,0x7b,0x4a,0x7d,0x80,
+  0xa8,0x20,0x2a,0xdc,0xb1,0x5f,0xec,0x52,0x49,0xcb,0x6e,0x3e,0x4f,0x9d,0x09,0xf4,
+  0x56,0x51,0x25,0xcd,0xe4,0x54,0x8a,0x2c,0xf4,0xff,0xc5,0xf7,0xdb,0x98,0xfd,0x77,
+  0x89,0xa7,0x62,0x4c,0x0d,0xd2,0xb4,0x78,0x4d,0x16,0x3f,0x85,0x20,0x0e,0xd8,0x12,
+  0xd0,0x89,0x78,0xe8,0xad,0xec,0x99,0xe2,0x64,0xd5,0x96,0x49,0xfa,0xe1,0x3a,0x65,
+  0x5a,0xee,0x2d,0x73,0x93,0x2e,0xc6,0xaf,0xf2,0xf2,0x46,0xcd,0xce,0x2c,0x7a,0x76,
+  0x13,0x2f,0x80,0x4e,0x66,0xde,0xb2,0x33,0xb3,0x2e,0x3b,0x0f,0x3d,0x32,0xd7,0x2c,
+  0x7a,0xd6,0xb1,0xbd,0x2a,0x0e,0x85,0x15,0x32,0x60,0x0b,0x72,0x1e,0xd2,0x12,0x47,
+  0x39,0x59,0xad,0xef,0x3f,0x2a,0xcd,0x82,0x9e,0x92,0xf5,0x57,0xed,0xc8,0xfd,0x42,
+  0xbd,0x0a,0x76,0x04,0xaa,0x3b,0x96,0xbe,0x7a,0x9e,0x5a,0xfe,0x3f,0xf0,0xff,0x49,
+  0xb1,0x27,0x6f,0xaa,0xd7,0xf8,0x5d,0xe2,0x76,0x34,0x5c,0xb8,0xb6,0x4a,0xf5,0x09,
+  0x73,0xbd,0x21,0x75,0x3b,0xd5,0x3e,0x4e,0x17,0x93,0xd4,0xab,0xbe,0xa8,0xfa,0xf3,
+  0x57,0x7f,0x04,0x65,0xeb,0xaf,0xe8,0x3b,0xf3,0x6c,0x14,0xa6,0xc1,0x84,0xfc,0xc4,
+  0xba,0xf3,0x7b,0xcf,0x90,0xcb,0xc3,0x4e,0x2b,0x65,0x47,0x1f,0x91,0x0a,0xe4,0x87,
+  0xcb,0xd6,0xef,0x88,0x8f,0xec,0x64,0x7d,0x14,0xf4,0x66,0x1e,0xb2,0x89,0x9f,0x18,
+  0xf3,0x5b,0x34,0xf1,0xf7,0x84,0x23,0x25,0xf2,0x77,0x91,0x75,0x53,0x55,0xec,0x39,
+  0x72,0x78,0xf8,0x62,0xee,0x35,0xb9,0xf6,0x9f,0xd3,0xee,0x1b,0x91,0x3f,0x31,0x5d,
+  0xe5,0xc4,0xd0,0xa5,0xc6,0x99,0xd1,0x83,0x8c,0xbd,0xb7,0x52,0x1c,0x81,0x14,0xaf,
+  0xc4,0x05,0x6a,0x0c,0xd1,0xc3,0x99,0x52,0x6a,0x36,0x87,0x83,0xac,0x92,0x75,0xd9,
+  0x2e,0x71,0x00,0xae,0x8e,0x25,0x4d,0xc0,0x1f,0x41,0x27,0x05,0x57,0x5d,0x58,0x77,
+  0x7e,0xef,0x19,0x7a,0x64,0x96,0x99,0x9b,0xf5,0x8e,0x18,0xeb,0xbd,0x56,0x52,0x61,
+  0xca,0xda,0x3b,0xca,0xac,0xbe,0xd1,0xa5,0xf0,0x42,0x56,0x5a,0xeb,0xb5,0xcc,0xb0,
+  0x8c,0x0c,0x89,0xfb,0x97,0x73,0xe2,0x8d,0x69,0x8e,0x6e,0x49,0x55,0x86,0x37,0x2c,
+  0x9a,0xca,0xbb,0x46,0x16,0xdb,0x7f,0x7c,0x83,0xf6,0x5f,0x6b,0x65,0x67,0xc8,0xd3,
+  0x33,0xbe,0x4e,0x97,0xc7,0xa2,0xb8,0xb7,0x6c,0x82,0x56,0xc8,0xeb,0x8f,0x6c,0xb1,
+  0x92,0xa5,0xa3,0x48,0xcf,0xc2,0x49,0xbd,0x00,0xd0,0x5f,0xba,0xe7,0x15,0x14,0x2f,
+  0x5a,0x7f,0xaf,0x58,0x1e,0x4a,0xbd,0x29,0xc0,0xd3,0x24,0xe9,0x15,0x11,0x9b,0x08,
+  0xd9,0x18,0xf4,0x5a,0x9c,0xd7,0xf7,0x26,0x43,0x85,0x60,0xb4,0xe4,0x01,0x3e,0x6d,
+  0x59,0x2c,0x6e,0x25,0x46,0x1d,0xaf,0xb0,0x8b,0xd9,0xe7,0x04,0x8f,0x9b,0xd7,0xdb,
+  0xa6,0xcd,0xa6,0x28,0xb8,0x58,0x78,0x03,0xb1,0xc3,0x89,0x9b,0x3f,0x2c,0xd2,0x5f,
+  0xee,0xc8,0x7f,0xaf,0x7c,0xb1,0xfd,0x17,0x3f,0xff,0xb1,0x7e,0xf5,0xd7,0x9c,0x48,
+  0x19,0xae,0xd9,0x20,0x64,0xb3,0xe5,0xef,0xfa,0x11,0xa3,0x5b,0xaa,0x56,0x30,0xd4,
+  0x15,0xfb,0xb2,0x13,0x75,0xf1,0x53,0x82,0x05,0xf6,0x65,0xb5,0xf0,0xf9,0x23,0xd9,
+  0xbe,0xe0,0x44,0xd5,0x4b,0x58,0xac,0x14,0xcf,0x6e,0xde,0xe5,0xa7,0x72,0x3c,0xb5,
+  0x54,0xcc,0x29,0x1a,0x13,0x84,0xfd,0x7f,0x28,0x7f,0xbb,0x81,0x14,0x63,0xa6,0xb1,
+  0xc6,0x31,0x3c,0x9b,0x51,0x04,0xad,0xa5,0xfe,0x9c,0xdb,0xd8,0x46,0xfa,0x5a,0xa1,
+  0xe6,0x98,0xf5,0xa6,0xa0,0xec,0xf5,0xc9,0x1a,0xbc,0x02,0x97,0x84,0x79,0xff,0x55,
+  0xc6,0xfe,0x8b,0x3f,0xcb,0x9f,0xff,0xcd,0xcb,0x60,0x7b,0xa9,0x7f,0x8b,0x6b,0x9c,
+  0x9c,0x28,0x19,0x66,0xa3,0x0f,0x0f,0x77,0x78,0xca,0x4c,0xde,0xec,0x7f,0x88,0xc8,
+  0x46,0xc8,0x3e,0xc8,0x88,0x6b,0x6b,0x32,0xe5,0x01,0xa4,0x96,0x50,0x95,0x2d,0x16,
+  0x44,0x2c,0x9a,0x87,0xe8,0xe0,0x8e,0x4e,0x23,0xeb,0xa3,0xe1,0xcd,0xab,0xfe,0xda,
+  0x37,0x33,0x2d,0xce,0x69,0xc0,0xd8,0x90,0xad,0x84,0xa7,0x4b,0x7e,0x7a,0x28,0x42,
+  0x2e,0x6d,0x67,0xd4,0x38,0xe2,0x53,0x19,0xdb,0x3a,0x9e,0x61,0x4e,0x19,0x26,0xe6,
+  0x28,0x18,0x28,0x58,0xba,0x2f,0xc4,0xeb,0x69,0x83,0x9c,0xa6,0x76,0xb8,0xe8,0xf9,
+  0xf3,0x1c,0x1d,0xe5,0x3e,0x37,0xd0,0xff,0x36,0x8f,0x87,0x99,0x08,0xd3,0x7a,0x3c,
+  0x6b,0xf6,0x66,0x72,0x73,0x92,0x9a,0x05,0x3c,0xcc,0x79,0x7c,0x7e,0x79,0x57,0xea,
+  0x0e,0xc4,0x4f,0x55,0xe5,0xef,0x14,0x44,0x2c,0x17,0xa3,0x17,0x70,0xe4,0x6a,0xc0,
+  0xa0,0xc2,0x8a,0x7d,0x67,0xf7,0x19,0x29,0xc5,0xdf,0x85,0xe9,0xe7,0x2a,0xa8,0xe6,
+  0x8e,0xa7,0xd4,0x8a,0x47,0x75,0x86,0xe6,0x99,0x2a,0x55,0x0a,0x95,0x9c,0x67,0xe1,
+  0xea,0x83,0x41,0xe8,0x0f,0x7b,0x93,0x1b,0xe8,0xef,0x2a,0x13,0xf9,0xef,0x2f,0xd2,
+  0x0f,0xf6,0xe7,0xb9,0x5d,0x62,0x3d,0x16,0xbe,0x5f,0xe0,0xee,0xc8,0x9d,0xff,0x75,
+  0xb6,0xe7,0x7a,0xe5,0x4f,0xae,0x2c,0xfe,0x80,0x5e,0xcf,0xbd,0x54,0x18,0x05,0x7b,
+  0xac,0x63,0x34,0xb2,0x3e,0xc8,0x9c,0x9c,0xa8,0x62,0x9a,0x4c,0xe7,0x5a,0x4a,0xf3,
+  0xc6,0x18,0xee,0xdb,0x1b,0x71,0x19,0x6c,0xbd,0x99,0x9b,0xf0,0x55,0x79,0x8c,0x11,
+  0x2f,0x24,0x27,0xa9,0xd3,0x25,0xb0,0x77,0xf3,0x3a,0x5f,0xe4,0xd5,0xef,0x33,0x7f,
+  0xf0,0x6a,0xab,0xd8,0xd6,0x7b,0x65,0xba,0xfc,0xd5,0x1a,0x51,0x3c,0x77,0x9e,0xf2,
+  0xa4,0x24,0x98,0xc8,0xda,0x36,0x33,0xd1,0x9d,0xa8,0xf7,0xc4,0xf8,0x44,0x38,0x0b,
+  0xb7,0x66,0x1f,0x01,0xd1,0x36,0x64,0xf4,0xfe,0xa1,0xec,0xc8,0x25,0xfe,0x92,0x1f,
+  0x2e,0xfa,0xa9,0xa9,0x7c,0xfb,0xcf,0x7e,0xae,0x5b,0xff,0xe9,0x64,0xe4,0x5b,0x7f,
+  0xce,0xc6,0xaf,0xdd,0xe8,0xdc,0x4a,0xe5,0x59,0x5f,0x47,0x6d,0x4f,0xb7,0x6c,0xb9,
+  0x2a,0x5f,0x4f,0x2f,0x3b,0x25,0xae,0x23,0x36,0x92,0xab,0xf0,0xe5,0xc7,0x8f,0xd2,
+  0x87,0x86,0x53,0x36,0xd4,0xf7,0xaf,0xac,0xfb,0x07,0x5a,0xee,0x15,0x52,0x1c,0x4e,
+  0x7c,0x2c,0xb6,0x15,0xfb,0x12,0xa2,0x0b,0x60,0x77,0xe7,0xd7,0xa8,0x2b,0x51,0x79,
+  0xcf,0xf8,0xdb,0xe3,0x02,0xc8,0x99,0x85,0x13,0xe3,0x01,0x29,0x15,0x6f,0x89,0xbf,
+  0xea,0x24,0x46,0xbd,0xb7,0x7a,0xc6,0xac,0xca,0x8f,0x1e,0xc9,0x79,0xcd,0x23,0x4f,
+  0x74,0xc8,0xd3,0xf5,0x22,0xbb,0xa0,0xc0,0xff,0x67,0x26,0x20,0xd6,0x2b,0x7f,0xad,
+  0x79,0xc6,0x72,0x4a,0x89,0x0e,0x87,0x02,0xf6,0x76,0xc7,0x4e,0x4e,0xff,0x94,0xe0,
+  0xb3,0x5b,0x48,0xdb,0xeb,0xe6,0x27,0xd3,0x66,0x4a,0x53,0xd6,0xe3,0x37,0x64,0xfb,
+  0xab,0x5c,0xcd,0x51,0xef,0xc5,0xbc,0xc7,0x9d,0x9b,0x87,0x43,0x6f,0x90,0xef,0x2b,
+  0xcf,0x73,0x9b,0xb4,0xf3,0x55,0xb4,0xe6,0x0a,0x1b,0xb5,0x69,0xa7,0x61,0x6f,0xce,
+  0x2b,0xe7,0xb2,0xc8,0xe6,0x1e,0xba,0xa4,0x8f,0xe9,0x21,0x73,0xaa,0x92,0xa3,0x65,
+  0xe8,0x9e,0x65,0x49,0xab,0xf0,0xd1,0xcc,0xfb,0x63,0x94,0x50,0x37,0xec,0xdb,0xca,
+  0x3d,0xf9,0xd1,0x0a,0x93,0xf1,0x6d,0x1f,0x17,0x4a,0x51,0x99,0xfe,0xdb,0xc0,0xf8,
+  0x37,0x9a,0xba,0xc8,0xd5,0x80,0xc6,0xfb,0xc2,0xc2,0xc1,0xfc,0x37,0x81,0xa4,0x63,
+  0x3a,0x6f,0x9b,0x5e,0xfc,0xc4,0xd6,0xad,0xcc,0xbc,0x92,0xbc,0xfe,0x23,0x4f,0x83,
+  0x71,0x7a,0x4b,0x3e,0x58,0xcf,0x1a,0x2a,0xe2,0x9c,0x9b,0x2d,0x49,0x0f,0x5a,0x54,
+  0x45,0x6c,0x5e,0xf1,0x6b,0x8b,0x7d,0x61,0xae,0xa2,0xa0,0x7a,0xf0,0xc5,0xb5,0xbc,
+  0x3c,0x4e,0xc6,0xaf,0xba,0x33,0xed,0x94,0x55,0x83,0x9c,0xd5,0xaa,0xb2,0xbe,0x8b,
+  0xcc,0x6b,0xba,0xa6,0x1a,0x69,0xce,0x70,0x7b,0xc6,0xbb,0x2a,0x45,0xf4,0xfb,0x7e,
+  0x9c,0x76,0x2a,0x81,0x13,0xc1,0x0b,0xc5,0x8f,0x83,0xcd,0xb2,0x7c,0xfb,0x6f,0x43,
+  0xe3,0xdf,0x66,0xfb,0x3c,0xf3,0x8a,0xc7,0x1f,0x5e,0x26,0x06,0xc7,0x64,0xd9,0xc3,
+  0x69,0x24,0x4b,0x07,0x9c,0xf0,0xe9,0xc4,0xfd,0x32,0xa3,0xf4,0xa5,0x98,0x21,0xb6,
+  0xb7,0x6b,0x7c,0x41,0x9c,0xf6,0x97,0xd3,0xbd,0x51,0x53,0x5e,0xae,0xb9,0x47,0x3f,
+  0xbc,0x2b,0x74,0x12,0xf5,0x0b,0x8f,0x36,0xed,0xeb,0xff,0x3e,0xc8,0x5b,0xca,0xeb,
+  0x37,0xf0,0x6a,0xb1,0x96,0x21,0xac,0xea,0xae,0xdc,0x8d,0x80,0x55,0x59,0x05,0x23,
+  0x69,0xab,0x51,0xb6,0x9b,0x8b,0x3b,0x6c,0xe9,0xa4,0x9f,0x68,0x63,0x6c,0x57,0xea,
+  0x4d,0xc5,0x52,0x9c,0xee,0x76,0x23,0x6a,0x2a,0x3f,0x51,0xcd,0x9d,0x29,0x76,0xb6,
+  0x15,0xcc,0xff,0xda,0xcf,0xf5,0xf5,0xbf,0x52,0x3c,0x1b,0x66,0xa3,0xf3,0x86,0x69,
+  0xec,0xa1,0xe1,0xb2,0x97,0x8f,0x10,0xc4,0x15,0x77,0x91,0xca,0x55,0xf0,0xd8,0xd5,
+  0xac,0x75,0x23,0x8e,0xbb,0x0e,0x88,0x0a,0x5f,0xfc,0x39,0xe9,0xbd,0xaa,0xa9,0xa5,
+  0x86,0x68,0x83,0x3d,0x2c,0x34,0xf2,0xe6,0x64,0x3b,0x36,0x52,0x76,0xdd,0xde,0xbc,
+  0xef,0x1f,0x97,0x8d,0xe1,0x48,0x61,0x65,0x15,0x05,0xf1,0x72,0xbd,0xbe,0xd6,0xaa,
+  0x6a,0xc6,0x0f,0xd9,0xd8,0x71,0x42,0x6f,0xce,0xcf,0x22,0x89,0xa5,0x5d,0x9e,0x75,
+  0x4d,0x06,0x94,0xbc,0x1a,0xec,0xa1,0x6f,0x20,0x97,0xf2,0xce,0x71,0xd3,0xa8,0x3d,
+  0x41,0x8d,0x8b,0xf8,0x7b,0x53,0x9d,0x7e,0xff,0x83,0xa8,0xf5,0xd4,0xb3,0x70,0xeb,
+  0xf3,0xbf,0xac,0xaa,0x41,0x83,0x93,0x84,0xbc,0xe9,0x09,0x9d,0xa8,0xf7,0xd7,0x68,
+  0xe2,0x4b,0x71,0xa4,0x4a,0x17,0x29,0x57,0x32,0x4e,0x43,0xfd,0xc0,0xf0,0x19,0x66,
+  0xa7,0xcb,0x19,0xcd,0x82,0xbe,0x55,0xed,0xd7,0xd4,0xea,0x95,0x62,0xe1,0x49,0xba,
+  0x4c,0xda,0x33,0x6d,0x42,0xb6,0xaf,0xe4,0xc9,0xfe,0xfb,0x8e,0x9c,0xec,0x66,0x74,
+  0x4e,0x33,0x2f,0xe8,0xbf,0xb9,0xe6,0x77,0x17,0xea,0x57,0xdd,0x11,0x2d,0x13,0x1e,
+  0xc8,0x4a,0x88,0x94,0x8d,0x83,0x56,0x88,0xd2,0xeb,0xd5,0x42,0xfe,0x93,0x4b,0xb6,
+  0x37,0x6a,0xca,0xa5,0x83,0xd1,0x19,0xb4,0x0f,0x4a,0x4a,0x58,0x57,0xc2,0x4c,0xe9,
+  0x8b,0x44,0x3d,0xfd,0x97,0x5d,0x54,0xbc,0x3e,0xfd,0xd7,0xd8,0x99,0xf5,0xa9,0xd9,
+  0xcf,0x28,0x55,0xbc,0x7c,0xe6,0xcd,0x2b,0x81,0xd6,0xe2,0x63,0xd4,0x95,0x18,0xb2,
+  0x7f,0xcb,0x59,0x3f,0x2b,0xde,0xab,0x71,0x2f,0xcf,0x44,0xc2,0x42,0x76,0x6c,0xd9,
+  0xa9,0x34,0x31,0xdd,0x47,0x7f,0xc7,0xd6,0xae,0x87,0x88,0xd3,0x76,0xb0,0xb1,0x26,
+  0xab,0xe0,0x5e,0xa1,0x86,0x04,0xaa,0xed,0x58,0x6e,0x6f,0x8f,0x66,0x34,0x53,0xde,
+  0x3f,0xee,0x54,0x85,0xca,0xc5,0x3b,0xc2,0x9e,0xde,0x8a,0x46,0x14,0xd2,0x8f,0x50,
+  0xb8,0x38,0x57,0x6e,0xd4,0xa8,0x1d,0xc9,0xd8,0xf9,0xf8,0x2f,0x2d,0x73,0x79,0x34,
+  0xbc,0x13,0xaf,0x9b,0xe1,0xab,0x53,0x51,0xa6,0x8b,0x09,0x7a,0x5f,0x99,0x5f,0x95,
+  0xaa,0x7f,0x91,0xcd,0xdb,0x27,0x7f,0x92,0x7a,0xc3,0x80,0xab,0x82,0x90,0x6f,0xbd,
+  0xe8,0x0f,0x36,0x5b,0xf4,0x36,0x32,0x76,0xa2,0xd1,0x89,0xdf,0x90,0x8e,0x5f,0x78,
+  0x75,0x41,0x7a,0xf8,0x1d,0x54,0xd3,0xfd,0x21,0x8a,0x6b,0xe5,0xa4,0x6f,0x1c,0xe7,
+  0x4c,0x4f,0x84,0xd5,0x39,0x41,0xae,0x49,0x19,0x1e,0x4d,0xfd,0xdb,0x5e,0x0e,0x31,
+  0xea,0x15,0x72,0x65,0xaf,0x70,0xf7,0xd2,0xe8,0xa7,0x3e,0x9b,0x72,0x6e,0x7b,0x48,
+  0xd5,0x1f,0x1d,0xdc,0x86,0x95,0x9d,0x93,0x8d,0x96,0x7e,0x61,0x67,0x6b,0x75,0xfe,
+  0x25,0x53,0x42,0x01,0x29,0x24,0x53,0x54,0x47,0x36,0x97,0xf8,0xb5,0xdf,0x9b,0x99,
+  0x9a,0x51,0xff,0xcd,0xbf,0xa3,0x45,0x4a,0xcf,0xb5,0xce,0xde,0x49,0x77,0xba,0xfa,
+  0x7f,0xce,0x5f,0xed,0x24,0xae,0x46,0xdf,0xda,0xbf,0x1e,0xe8,0xf6,0xb2,0x3f,0x6c,
+  0xaf,0x8b,0x83,0xc8,0x25,0xd3,0x12,0x13,0xb5,0x2d,0xde,0xd8,0xd7,0x99,0x36,0xea,
+  0xa0,0xba,0xef,0xef,0xde,0x39,0xfb,0xee,0xd8,0x91,0xad,0x69,0x63,0xd4,0x75,0xa5,
+  0x9c,0x3d,0x73,0x39,0xa5,0x6e,0xc4,0x95,0x99,0xe9,0x19,0x72,0xb7,0x13,0xa5,0x39,
+  0x7b,0xf8,0x9d,0x73,0xa4,0x14,0xa6,0xa6,0xbd,0x79,0x0b,0x29,0xaf,0xd2,0x1c,0xab,
+  0x5c,0x0d,0x10,0x7d,0x55,0x10,0xe5,0x4e,0xaf,0x94,0xa6,0x52,0xcf,0x49,0xaf,0xd8,
+  0xc4,0x45,0x27,0x9c,0x4e,0xe9,0xb4,0x13,0xd3,0xb4,0x98,0xa6,0x2e,0x6a,0xc9,0x6a,
+  0x8a,0x6b,0x7f,0xc5,0x42,0x96,0xee,0x24,0xe2,0x46,0xc4,0x59,0xb5,0xff,0xb5,0xf1,
+  0x77,0xcf,0xbe,0x33,0x7a,0xd0,0xfe,0xd5,0x3a,0x75,0xdc,0x5a,0xe0,0x47,0xc7,0x3a,
+  0xcf,0x1b,0xdc,0x5b,0xb6,0x25,0x15,0x1d,0x1b,0x7d,0x9c,0x0c,0x2e,0xf3,0x1e,0x66,
+  0x88,0x83,0xe4,0xbc,0x30,0x2e,0x0a,0x7f,0x8a,0x49,0xfe,0x03,0xab,0xc4,0x3f,0x59,
+  0x1a,0x1a,0xe9,0x20,0x11,0xb9,0x3b,0x25,0x77,0x9b,0xd5,0x17,0x2b,0x05,0x70,0x7d,
+  0x8f,0xad,0x3a,0x7f,0xa4,0xa7,0x8e,0xb6,0xe8,0xcb,0x02,0xce,0xa9,0xc1,0x66,0x17,
+  0x00,0xc7,0xa7,0xd5,0x4e,0x64,0x7f,0xdd,0x5b,0xff,0xfe,0x6a,0x48,0xfe,0xa7,0x2e,
+  0x4e,0xa9,0xf7,0xb8,0x2a,0x13,0xdd,0xcf,0xd9,0x98,0x27,0x7f,0xca,0xf8,0x72,0x05,
+  0xa4,0xff,0x9b,0xbc,0x15,0x94,0x91,0x1d,0x69,0xc6,0x07,0xba,0x30,0x0e,0xfb,0x89,
+  0xab,0x6f,0xad,0x24,0x25,0xc9,0xcc,0xf3,0x4b,0x4e,0x21,0x87,0xc9,0x02,0x79,0x53,
+  0xd0,0x2c,0x32,0x5b,0xf4,0x73,0xef,0xef,0x3c,0xe6,0x5a,0x66,0xea,0x05,0x0e,0x3c,
+  0x8c,0x52,0xa5,0x2f,0x76,0x0d,0x99,0xbb,0x22,0xd2,0x9f,0x7b,0x16,0x72,0x7f,0x29,
+  0xfe,0x7e,0xb2,0x2d,0xa9,0x9e,0x30,0x12,0x8e,0xa0,0x5c,0xf7,0x25,0x86,0x61,0x18,
+  0x95,0x5a,0x74,0x99,0x2a,0x04,0xff,0xfd,0x1a,0x62,0xdc,0xd4,0x92,0x29,0x7a,0x72,
+  0x71,0xb4,0xd8,0x32,0xfe,0x99,0xe9,0xf8,0xac,0x4a,0x24,0x7f,0xfa,0x97,0x26,0xc5,
+  0xe9,0x5a,0xf4,0x23,0xd1,0x99,0xc5,0xd6,0x2c,0xa9,0x89,0xec,0x90,0xd5,0xb6,0x1b,
+  0xf6,0xfc,0xc7,0xab,0x69,0x33,0x20,0xfa,0xfd,0xe9,0x24,0x89,0xb6,0x8e,0x8b,0x15,
+  0x56,0x92,0xda,0xe4,0xdc,0x6e,0x3e,0xe6,0x37,0xaa,0xd3,0x8c,0xa6,0x9a,0x07,0xac,
+  0x68,0xea,0x97,0xc8,0x83,0x89,0x32,0x4e,0x42,0xea,0x75,0x9a,0x8d,0x3e,0x73,0x42,
+  0x68,0xfb,0x4a,0x7b,0x75,0x68,0xaf,0x8a,0x3f,0x83,0xfd,0x51,0x6a,0x94,0x15,0xd0,
+  0xbc,0xba,0x97,0xf5,0xf8,0x36,0x70,0x22,0xf7,0xd6,0x82,0xb1,0x7f,0x4c,0x4d,0x7f,
+  0x70,0xb6,0xf5,0x5d,0xfd,0xdb,0x14,0x9b,0x4b,0xfc,0xda,0xdb,0xb8,0xf3,0x7a,0x98,
+  0x01,0x98,0x6b,0x40,0xd6,0xe3,0xee,0xfe,0x94,0xf1,0x06,0x5e,0xf5,0x46,0x6b,0xab,
+  0xe3,0xce,0x8f,0x42,0x7c,0xc3,0xf9,0x11,0x87,0xb1,0xfc,0x45,0x88,0x8f,0x0f,0xc6,
+  0x0d,0x9f,0x98,0x36,0xe4,0x36,0xce,0x8b,0x40,0xfd,0x2e,0x3a,0xe8,0x1e,0xfc,0xe7,
+  0xbc,0xa5,0x38,0xab,0xa3,0xc4,0x39,0x63,0x8d,0x76,0x9b,0x59,0x4e,0xd2,0x16,0x66,
+  0xf3,0x7a,0xc2,0xd3,0x7f,0xcd,0x49,0x6a,0xcd,0xe7,0x14,0x8d,0x1b,0x77,0xa4,0xf3,
+  0x9d,0x74,0x96,0xfc,0xb0,0x9f,0xba,0xe5,0x9a,0x73,0x7b,0x96,0x5c,0x97,0xd8,0xb9,
+  0xfb,0x6d,0xfe,0x84,0xf8,0xf5,0x80,0xb9,0xc8,0x5b,0x73,0x48,0x7a,0x5c,0x27,0x7b,
+  0xa4,0x6a,0xc3,0xde,0x43,0x79,0xef,0x0a,0xb8,0xef,0x6c,0x33,0xa3,0x5d,0x93,0x07,
+  0xda,0xf3,0xb1,0xf4,0x9f,0x68,0x93,0x32,0x39,0xf6,0x1f,0xae,0x6e,0x8e,0xd3,0x81,
+  0x19,0x2d,0x9c,0x74,0xc4,0xd1,0x01,0x99,0xe1,0x90,0xe2,0xb2,0xf9,0xed,0x64,0xa2,
+  0xdf,0xfc,0x28,0xb2,0x03,0xd7,0xe0,0x27,0x13,0xf9,0x4f,0xe1,0xb5,0x47,0x43,0x77,
+  0xb5,0x57,0x2b,0xa4,0x5b,0xf2,0xc6,0x30,0x24,0x67,0x39,0xf2,0x67,0xc5,0x25,0xe7,
+  0x74,0x96,0x89,0x29,0x75,0x5b,0x9e,0xee,0x7f,0x97,0xfb,0x9c,0xd0,0x16,0x5d,0xe7,
+  0x1c,0xb1,0x3f,0x4f,0x8a,0x58,0x3f,0xf0,0x20,0x1a,0xe3,0xfd,0xae,0x08,0x48,0x12,
+  0x5c,0xdb,0xf4,0x23,0x8e,0xb3,0xfb,0xa2,0x1e,0xc5,0xfd,0x89,0x64,0xe6,0x4f,0x49,
+  0xa4,0xff,0x6c,0xda,0x5d,0x73,0xb2,0x46,0x98,0xfb,0x53,0x40,0xbe,0x21,0x23,0xd0,
+  0xab,0x5e,0xb3,0x5a,0x1d,0xb7,0x15,0x5c,0x16,0x71,0x52,0xce,0x3d,0x4e,0xff,0xb5,
+  0xf5,0x10,0xf7,0xca,0xcf,0x59,0xd5,0x99,0x4e,0x54,0x20,0xbc,0xf1,0x9e,0x51,0x39,
+  0x0f,0xb1,0x1f,0x8e,0x37,0x8a,0x56,0x42,0x8c,0x72,0x5b,0x0d,0x24,0xf9,0x7e,0xda,
+  0x82,0x6c,0x5e,0xe3,0x9c,0x65,0xe5,0xaf,0xa0,0x68,0xbc,0x25,0x26,0x7e,0xe6,0xdc,
+  0x6d,0x8b,0xf4,0x5f,0xc9,0x75,0xde,0x4d,0x9c,0xfe,0xd3,0xbf,0xb1,0x2d,0x1a,0x13,
+  0x03,0x15,0xce,0x42,0xee,0x37,0x24,0xda,0x2c,0x9d,0x0c,0x46,0xe1,0xc3,0x07,0x66,
+  0x57,0x37,0xa9,0xcf,0xd9,0xea,0x3f,0x56,0x10,0x14,0xdb,0x4c,0x49,0x90,0x63,0xff,
+  0xad,0x3d,0xc6,0xd4,0x0c,0xaf,0x90,0x57,0x7e,0xa1,0x5a,0xf7,0x16,0xaa,0x94,0xad,
+  0x39,0x9f,0xd4,0x76,0x72,0x14,0xf0,0x1e,0x36,0x3c,0x7e,0xbb,0xd0,0xc9,0x26,0x47,
+  0x4b,0x66,0x28,0xca,0x73,0x16,0xe4,0xca,0xdf,0x7a,0xb2,0x95,0x8e,0x2e,0x33,0xfe,
+  0x58,0xee,0xe3,0x6b,0xbc,0x5a,0x07,0x3f,0xf7,0x3d,0x9b,0x4a,0x02,0xcf,0xec,0xa9,
+  0x52,0xa1,0x0d,0xdc,0xa8,0x2a,0x70,0xc2,0xa7,0x3e,0xc3,0x2d,0xbc,0x5a,0xfb,0xdb,
+  0x8b,0x9b,0xb1,0xe7,0x8d,0x31,0xf6,0x9f,0x31,0xe5,0x6d,0x3e,0xd8,0x1a,0xbf,0x4f,
+  0x8d,0x7f,0x23,0xfd,0xb7,0xe6,0x98,0x88,0xfd,0x97,0x5c,0x2e,0x45,0xfd,0xfc,0xa1,
+  0xc7,0xe8,0x9a,0x2a,0xe6,0xf0,0xea,0x65,0xd7,0x89,0x85,0x48,0x1b,0x14,0x09,0xa0,
+  0xb1,0xff,0x36,0x90,0x33,0x16,0x8e,0xd3,0x76,0x91,0xd8,0x7f,0x1b,0x2c,0xa0,0x58,
+  0xa5,0x1d,0xf6,0x13,0xb7,0x5c,0x5b,0x4f,0xb1,0xef,0xf7,0x4c,0x1c,0x21,0xb5,0x33,
+  0xe6,0xfa,0xc9,0xa1,0x74,0xf1,0xd0,0x23,0xd3,0x85,0xf7,0xbf,0xf2,0xfe,0x1f,0xe4,
+  0x26,0xfe,0xc1,0xe9,0x6d,0xb1,0x15,0x75,0x17,0x9b,0x6f,0xff,0x29,0xfd,0xb7,0x9e,
+  0xab,0x73,0x7e,0x21,0x49,0x15,0x6e,0x7d,0x6a,0x64,0xb8,0xd7,0x9c,0xa3,0x7f,0xa0,
+  0x35,0x72,0x4a,0x24,0x8e,0x0f,0x35,0x24,0xac,0x6c,0x3f,0x38,0xfe,0x71,0x2b,0x3a,
+  0xb5,0x38,0x67,0xa3,0xe1,0xc6,0x33,0x15,0x8e,0xfb,0xbe,0xec,0x7f,0xba,0xbb,0x32,
+  0x0a,0xd8,0x96,0xf4,0xf8,0xb7,0xb6,0x9e,0x18,0x7e,0x9e,0x32,0xdd,0xa2,0x07,0x5f,
+  0x45,0x7b,0x7e,0xec,0xc0,0x40,0x45,0x97,0x49,0xc0,0xad,0xb3,0x26,0x2a,0xa6,0x64,
+  0x10,0xdc,0xbb,0xeb,0xd8,0x7b,0x0d,0x99,0x7d,0xf4,0x7f,0x33,0xb1,0x4d,0x25,0x38,
+  0xbc,0xab,0x7f,0xbe,0xfe,0x6b,0x8d,0x6b,0xcb,0x64,0xad,0xff,0x32,0xfa,0x4f,0xa3,
+  0x17,0x2e,0x28,0x35,0x38,0x77,0xfa,0xe8,0x33,0xfd,0x55,0x5d,0xa2,0xba,0x78,0x43,
+  0x16,0xf9,0xb7,0x58,0x6d,0x60,0xdf,0x5b,0x33,0xbf,0x17,0x5a,0xed,0x75,0xf8,0xd9,
+  0xc8,0xd1,0xf5,0x24,0xc4,0xff,0xc7,0xc3,0x13,0xbe,0x51,0x31,0x79,0x97,0x65,0xc4,
+  0xc2,0x43,0x7e,0xea,0x96,0x6b,0x6c,0x1d,0x97,0xa7,0xe5,0xcf,0x24,0x4b,0x0a,0xb1,
+  0x38,0x33,0x76,0x60,0x30,0xfa,0x39,0x8a,0xe8,0x59,0xbc,0xb8,0xb0,0x58,0xb5,0x7f,
+  0x68,0xe4,0xf4,0x5c,0x5d,0xc8,0x4e,0xbf,0x6d,0x78,0xdf,0x79,0x66,0xdb,0xc0,0xb6,
+  0x6d,0xd1,0xb6,0xc1,0x8f,0xc1,0x94,0xfd,0x77,0x7a,0xdb,0x7a,0x62,0xc8,0x59,0x90,
+  0xa0,0x23,0x91,0xed,0x96,0x92,0xb0,0x96,0x10,0x37,0x17,0x66,0x4e,0xbf,0x35,0xf2,
+  0xea,0x91,0x91,0x23,0xaf,0xbe,0xf2,0xfa,0xc9,0x73,0x17,0xaf,0xdf,0x16,0x2d,0x3d,
+  0x2d,0x55,0xb4,0xca,0xd9,0x21,0x4f,0xdc,0x45,0xae,0x7e,0xec,0x3f,0xfd,0x2e,0xa6,
+  0xee,0xa2,0x80,0xf4,0xc7,0xc0,0x8f,0x8f,0xf9,0x8a,0xbe,0xb1,0x63,0x3d,0xc5,0xf4,
+  0x72,0xc1,0x93,0x08,0xda,0xfe,0x50,0xa5,0xd4,0xbc,0x7d,0xfd,0xe2,0xb9,0x93,0x47,
+  0x47,0x74,0x29,0x1d,0x79,0xf5,0x57,0xef,0xfe,0x76,0xe1,0xc6,0xb2,0x68,0xe9,0x39,
+  0x3f,0xb1,0x29,0xc7,0xbc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0xe0,0x4f,0xc5,0xff,0x02,0x04,0xc4,0x15,0x0c,0x36,0xb4,
+  0x04,0x00,
diff --git a/u-boot/board/esd/ar405/Makefile b/u-boot/board/esd/ar405/Makefile
new file mode 100644
index 0000000..bd08253
--- /dev/null
+++ b/u-boot/board/esd/ar405/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/ar405/ar405.c b/u-boot/board/esd/ar405/ar405.c
new file mode 100644
index 0000000..6ec507f
--- /dev/null
+++ b/u-boot/board/esd/ar405/ar405.c
@@ -0,0 +1,410 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "ar405.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+const unsigned char fpgadata_xl30[] = {
+#include "fpgadata_xl30.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	/* first try 40er image */
+	gd->board_type = 40;
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* try xl30er image */
+		gd->board_type = 30;
+		status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
+		if (status != 0) {
+			/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+			/* set up serial port with default baudrate */
+			(void) get_clocks ();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init ();
+			console_init_f ();
+#endif
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf ("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay (1000);
+			}
+			putc ('\n');
+			do_reset (NULL, 0, 0, NULL);
+		}
+	}
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+	const unsigned char *fpga;
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	if (gd->board_type == 30) {
+		fpga = fpgadata_xl30;
+	} else {
+		fpga = fpgadata;
+	}
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpga[index];
+		printf ("%s ", &(fpga[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+
+#if 1 /* test-only: some internal test routines... */
+#define DIGEN	((void *)0xf03000b4) /* u8 */
+#define DIGOUT	((void *)0xf03000b0) /* u16 */
+#define DIGIN	((void *)0xf03000a0) /* u16 */
+
+/*
+ * Some test routines
+ */
+int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	int k;
+	int start;
+	int end;
+
+	if (argc != 3) {
+		puts("Usage: digtest n_start n_end (digtest 0 7)\n");
+		return 0;
+	}
+
+	start = simple_strtol (argv[1], NULL, 10);
+	end = simple_strtol (argv[2], NULL, 10);
+
+	/*
+	 * Enable digital outputs
+	 */
+	out_8(DIGEN, 0x08);
+
+	printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
+	       start, end);
+
+	/*
+	 * Set outputs one by one
+	 */
+	for (;;) {
+		for (i=start; i<=end; i++) {
+			out_be16(DIGOUT, 0x0001 << i);
+			for (k=0; k<200; k++)
+				udelay(1000);
+
+			if (in_be16(DIGIN) != (0x0001 << i)) {
+				printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
+				       0x0001 << i, in_be16(DIGIN));
+				return 0;
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	digtest,	3,	1,	do_digtest,
+	"Test digital in-/output",
+	""
+);
+
+#define ERROR_DELTA     256
+
+struct io {
+	short val;
+	short dummy;
+};
+
+int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	short val;
+	int i;
+	int volt;
+	struct io *out;
+	struct io *in;
+
+	out = (struct io *)0xf0300090;
+	in = (struct io *)0xf0300000;
+
+	i = simple_strtol (argv[1], NULL, 10);
+
+	volt = 0;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+	udelay(10000);
+	val = in_be16((void *)&(in[i*2].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in_be16((void *)&(in[i*2+1].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 5;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+	udelay(10000);
+	val = in_be16((void *)&(in[i*2].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in_be16((void *)&(in[i*2+1].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 10;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+	udelay(10000);
+	val = in_be16((void *)&(in[i*2].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in_be16((void *)&(in[i*2+1].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	printf("Channel %d OK!\n", i);
+
+	return 0;
+}
+U_BOOT_CMD(
+	anatest,	2,	1,	do_anatest,
+	"Test analog in-/output",
+	""
+);
+
+
+int counter = 0;
+
+void cyclicInt(void *ptr)
+{
+	out_be16((void *)0xf03000e8, 0x0800); /* ack int */
+	counter++;
+}
+
+
+int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong *incin;
+	int i;
+
+	incin = (ulong *)0xf0300040;
+
+	/*
+	 * Clear inc counter
+	 */
+	out_be32((void *)&incin[0], 0);
+	out_be32((void *)&incin[1], 0);
+	out_be32((void *)&incin[2], 0);
+	out_be32((void *)&incin[3], 0);
+
+	incin = (ulong *)0xf0300050;
+
+	/*
+	 * Inc a little
+	 */
+	for (i=0; i<10000; i++) {
+		switch (i & 0x03) {
+		case 0:
+			out_8(DIGEN, 0x02);
+			break;
+		case 1:
+			out_8(DIGEN, 0x03);
+			break;
+		case 2:
+			out_8(DIGEN, 0x01);
+			break;
+		case 3:
+			out_8(DIGEN, 0x00);
+			break;
+		}
+		udelay(10);
+	}
+
+	printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
+	printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
+	printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
+	printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
+
+	out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
+	out_be16((void *)0xf03000ec,
+		 in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
+	irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
+	printf("counter=%d\n", counter);
+
+	return 0;
+}
+U_BOOT_CMD(
+	inctest,	3,	1,	do_inctest,
+	"Test incremental encoder inputs",
+	""
+);
+#endif
diff --git a/u-boot/board/esd/ar405/ar405.h b/u-boot/board/esd/ar405/ar405.h
new file mode 100644
index 0000000..5fc313a
--- /dev/null
+++ b/u-boot/board/esd/ar405/ar405.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/ar405/flash.c b/u-boot/board/esd/ar405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/ar405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/ar405/fpgadata.c b/u-boot/board/esd/ar405/fpgadata.c
new file mode 100644
index 0000000..5c337e0
--- /dev/null
+++ b/u-boot/board/esd/ar405/fpgadata.c
@@ -0,0 +1,2750 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x70,0x70,0x63,0x5f,0x61,0x72,0x30,0x31,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x34,0x30,0x78,0x6c,0x70,0x71,0x32,0x34,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x31,0x2f,0x30,0x32,0x2f,0x31,0x34,0x00,0x64,0x00,0x09,0x31,0x35,0x3a,0x34,
+ 0x30,0x3a,0x30,0x34,0x00,0x65,0xe2,0x01,0x00,0x00,0xab,0x8e,0xff,0x30,0xe5,0xe5,
+ 0xe8,0xe5,0x03,0xe8,0x04,0x01,0x02,0x11,0x09,0x09,0x01,0x07,0x02,0x04,0x04,0x06,
+ 0x09,0x07,0x04,0x04,0x04,0x04,0x03,0x07,0x02,0x04,0x09,0x04,0x04,0x0b,0x09,0x09,
+ 0x03,0x07,0x02,0x09,0x04,0x04,0x04,0x04,0x0e,0x04,0x04,0x09,0x03,0x07,0x02,0x04,
+ 0x03,0x03,0x03,0x07,0xe5,0x01,0x0d,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x19,0x03,0x02,0x02,0x03,0x02,0x08,0x09,0x07,0x13,0x03,0x11,0x02,0x06,0x03,0x05,
+ 0x03,0x05,0x11,0x1d,0x1f,0x13,0x10,0x01,0x01,0xe3,0x4c,0xe5,0x01,0x0a,0x04,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x09,0x04,0x04,0x02,0x06,0x01,0xe5,0x05,
+ 0x01,0x02,0x04,0x04,0x04,0x09,0x09,0x09,0x09,0x04,0x06,0x01,0x07,0x09,0x04,0x04,
+ 0x09,0x06,0x02,0x09,0x09,0x04,0x01,0xe7,0x03,0x04,0x07,0xe6,0x08,0x09,0x09,0x0e,
+ 0x01,0xe6,0x13,0x09,0x09,0x09,0x03,0x05,0x03,0x05,0x09,0x09,0x09,0x09,0xe5,0x07,
+ 0x03,0x05,0xe5,0x07,0xe5,0x01,0x05,0x0b,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe6,
+ 0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0xe6,0x04,
+ 0xe5,0x07,0x03,0x05,0xe5,0x07,0x0b,0x01,0x0e,0x05,0x03,0x05,0x03,0x05,0x1d,0x03,
+ 0x05,0x03,0x44,0xe5,0xe5,0x2e,0x1c,0x01,0x13,0x32,0x01,0xe3,0x4d,0xe5,0x0f,0x09,
+ 0x09,0x27,0x09,0x42,0x04,0x4a,0x44,0x01,0x01,0x01,0x12,0x09,0x09,0x01,0x06,0x01,
+ 0x12,0x09,0x0a,0x09,0x11,0x21,0x13,0x11,0x15,0x1d,0x1b,0x0c,0x0d,0x03,0x03,0x01,
+ 0x31,0x31,0x47,0x81,0xe5,0xe5,0xe5,0x77,0x3e,0xe5,0x19,0xe5,0x1b,0x3b,0xe5,0xe5,
+ 0x5a,0x3d,0x1f,0x74,0xe6,0xe5,0x28,0x5b,0x09,0xe5,0x0a,0x08,0xe5,0x08,0x1d,0x11,
+ 0xe6,0x37,0x12,0x01,0x01,0x09,0x06,0x09,0x09,0x09,0xe5,0x07,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x01,0x03,0x03,0x03,0x05,0x05,0x05,0x09,0x09,0x09,0x09,0x09,0xe5,
+ 0x07,0x09,0x09,0x09,0x05,0x03,0x09,0x09,0x09,0x10,0xe5,0x0f,0x09,0x09,0x04,0x04,
+ 0x09,0x09,0x05,0x03,0x05,0x03,0x01,0x07,0x09,0x09,0x09,0x09,0x07,0x01,0x07,0xe5,
+ 0x01,0x07,0x01,0x06,0x02,0x09,0x05,0x03,0x06,0x02,0x09,0x05,0x01,0x01,0x01,0x07,
+ 0x05,0x03,0x09,0x09,0x09,0x04,0x04,0x0e,0x01,0xe5,0x02,0x09,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x01,
+ 0x01,0x03,0xe5,0x01,0x05,0xe5,0x07,0xe5,0xe5,0x05,0x09,0x09,0x01,0x02,0x06,0x04,
+ 0x04,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0xe5,0x07,0x09,0xe5,0x02,0x04,0xe5,
+ 0x01,0x05,0x09,0x09,0xe5,0x07,0xe5,0x04,0x0b,0x01,0x10,0x09,0x09,0x09,0x09,0x05,
+ 0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x02,0x06,0x02,0x06,0xe6,0x01,0x06,0x02,
+ 0x06,0x02,0x09,0x09,0x03,0x02,0x02,0x09,0x06,0x02,0x09,0x09,0x06,0x02,0x06,0x02,
+ 0x09,0x09,0x0d,0x02,0xe5,0x02,0x01,0xe5,0x05,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x02,0x04,0xe5,0x03,0x03,0x05,0x03,0x0b,0x04,0xe5,0x02,0x06,0x02,0x09,0xe5,
+ 0x07,0xe5,0x01,0x05,0x05,0x03,0xe5,0x03,0x03,0x05,0x03,0xe5,0x07,0xe5,0x07,0x09,
+ 0x09,0xe5,0x07,0xe5,0x07,0x02,0x03,0xe5,0xe6,0x08,0x05,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe5,0x05,0x06,0x09,0x07,0xe6,0x08,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,0x0a,0x09,0x08,0x01,0x03,0x06,0x08,0x09,
+ 0x09,0x0a,0x08,0x0a,0x07,0xe5,0x08,0x0a,0x09,0x08,0x09,0x11,0xe5,0xe5,0x01,0x0a,
+ 0x02,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x01,0x04,0x02,0x03,0x02,0x02,
+ 0x06,0x02,0x05,0xe5,0x01,0x05,0xe5,0x01,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x08,0x02,0x05,0xe5,0x01,0x06,0x02,0x05,0xe5,0x01,0x04,0x01,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x01,0x04,0x02,0x06,0x02,0x06,0x02,0x05,0xe5,0x01,0x06,0x02,0x06,
+ 0x02,0x08,0x04,0xe5,0xe6,0x02,0x11,0x04,0xe6,0x24,0x09,0xe5,0x2f,0x06,0xe5,0xe5,
+ 0x05,0x0e,0x06,0xe5,0x10,0x17,0x09,0x06,0x02,0x45,0x03,0x02,0xe5,0x15,0x0f,0x13,
+ 0x27,0x1e,0x05,0x02,0x01,0x01,0x05,0x08,0x3c,0x06,0x01,0x45,0x04,0xe8,0x11,0x01,
+ 0xe5,0x07,0x15,0x13,0x23,0x22,0xe5,0x04,0x01,0x06,0x2e,0x13,0x1d,0x2d,0xe5,0xe6,
+ 0x18,0x02,0x0c,0x17,0x09,0x31,0x0d,0xe5,0x0c,0x31,0xe7,0x58,0x04,0xe5,0xe6,0x0f,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x01,0x02,0xe5,0x02,0x09,0x09,0x05,0x03,0x05,0x03,
+ 0xe5,0x07,0x09,0x0b,0x09,0x09,0x09,0x01,0x03,0x03,0x07,0x01,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x0f,0xe6,0x13,0x1d,0x03,0x01,0x1a,0x13,0xe5,0xe5,0x0f,0x01,
+ 0xe5,0x07,0xe5,0x05,0x01,0xe5,0x06,0xe6,0xe5,0x05,0x02,0x06,0x01,0xe5,0x09,0x12,
+ 0x09,0x10,0x0a,0x01,0x08,0xe5,0x0f,0x01,0xe5,0x17,0xe5,0xe5,0x50,0x01,0x07,0x09,
+ 0x01,0x14,0x05,0x01,0x08,0x0a,0x0a,0x02,0x09,0x0d,0x0b,0x14,0x4e,0xe5,0x01,0x3c,
+ 0x0b,0x12,0x34,0x0b,0x06,0x01,0x0e,0x18,0x04,0x04,0x04,0x0f,0x27,0x19,0x02,0xe5,
+ 0x05,0x67,0x09,0x3d,0x33,0x07,0x1d,0x17,0x05,0xe5,0xe6,0x05,0x15,0x5b,0x35,0x81,
+ 0xe6,0x34,0x01,0x07,0x1d,0xe6,0x06,0x01,0x0b,0x05,0x01,0x0b,0x0b,0x2d,0x01,0x07,
+ 0x0b,0x05,0x03,0x11,0xe6,0x1a,0x01,0x03,0x17,0xe5,0x1a,0x1c,0x09,0x24,0x01,0x11,
+ 0x01,0x0e,0x07,0x15,0x1b,0x09,0x03,0x21,0x1c,0x01,0x18,0x01,0x01,0x35,0x20,0x01,
+ 0x04,0x01,0x13,0x0d,0x0b,0x12,0x10,0x02,0x0a,0x03,0x11,0x01,0x09,0x02,0x03,0x07,
+ 0x06,0x2a,0x0c,0x02,0x1a,0x0a,0x08,0x13,0x09,0x10,0xe5,0xe5,0x0b,0x03,0xe5,0x0e,
+ 0x07,0x1e,0x03,0x01,0x12,0x0f,0x02,0x01,0x02,0x17,0x02,0x01,0x02,0x11,0x0d,0x13,
+ 0xe5,0x01,0x27,0xe5,0x33,0x07,0x0d,0x3b,0x02,0x0b,0x09,0x0e,0x03,0x1c,0x35,0x01,
+ 0xe6,0x64,0x09,0x2a,0x03,0x06,0x01,0x03,0x07,0x02,0x2b,0x05,0x20,0xe6,0x24,0xe5,
+ 0xe5,0x06,0x43,0x0e,0x37,0x01,0x28,0x23,0x27,0x0c,0x15,0xe5,0xe6,0x68,0x0c,0x03,
+ 0x02,0x13,0x05,0x02,0x14,0x01,0x0b,0x03,0x07,0x08,0x06,0x16,0x06,0x36,0xe5,0xe6,
+ 0x60,0x07,0x13,0x02,0x10,0x0d,0x11,0x02,0x20,0x10,0x01,0x0c,0x01,0x02,0x34,0xe7,
+ 0x09,0x06,0x58,0x10,0x01,0x11,0x01,0x1f,0x04,0x08,0x17,0x18,0x04,0x2c,0x0b,0x03,
+ 0xe6,0x6e,0x37,0x0f,0x02,0x03,0xe5,0xe5,0x04,0xe5,0x06,0x01,0xe5,0x03,0xe5,0xe6,
+ 0x05,0x08,0xe6,0x03,0x05,0xe5,0x07,0xe5,0x05,0x1e,0xe7,0xe6,0x01,0x01,0x6c,0x13,
+ 0xe5,0x21,0xe5,0x0d,0x04,0x04,0x04,0x01,0x01,0x07,0xe5,0xe5,0x04,0xe5,0x0f,0x05,
+ 0xe6,0x03,0xe5,0x06,0xe5,0x21,0x01,0x06,0x04,0x6c,0x10,0xe5,0x16,0x06,0x01,0xe5,
+ 0xe5,0x0b,0x04,0x06,0xe5,0x10,0xe5,0x05,0xe5,0x07,0x0c,0xe5,0x18,0x1b,0x05,0x01,
+ 0xe5,0x01,0x57,0x16,0x10,0x13,0xe5,0x04,0x07,0x01,0x04,0xe5,0xe5,0x08,0x06,0x12,
+ 0xe5,0x1c,0x38,0x03,0xe5,0xe5,0x5a,0x27,0x03,0x22,0x06,0xe5,0x04,0xe5,0x06,0x01,
+ 0x0e,0x07,0x02,0x02,0x05,0x0c,0x01,0x01,0x02,0xe5,0x01,0x05,0x09,0x1f,0xe5,0xe6,
+ 0x01,0x5e,0x13,0x0f,0x03,0x04,0x10,0x01,0x02,0x04,0x08,0x02,0x01,0xe6,0x02,0x05,
+ 0x03,0x0f,0x02,0x02,0x02,0x14,0x01,0x02,0x01,0x01,0x2c,0x02,0x01,0x01,0xe5,0x5b,
+ 0x01,0x2d,0x0d,0x09,0x01,0x03,0xe5,0x03,0x04,0x01,0xe5,0x05,0x01,0x11,0x02,0x0e,
+ 0x0b,0x01,0x02,0x0b,0x09,0xe5,0xe5,0xe5,0x19,0xe5,0x02,0x5d,0x01,0x3a,0x02,0x07,
+ 0x01,0x01,0xe5,0xe5,0x01,0x02,0x06,0x17,0xe8,0xe5,0x01,0x0a,0xe5,0x0d,0x0e,0x09,
+ 0x1f,0xe5,0xe6,0x6c,0xe5,0x25,0x12,0x04,0x04,0x02,0x09,0x10,0x09,0x09,0x1d,0x09,
+ 0x21,0xe8,0x63,0x09,0x09,0x09,0x09,0x0b,0x0f,0xe5,0x0d,0x07,0xe6,0x06,0x05,0xe5,
+ 0x0b,0xe5,0x03,0xe5,0x15,0x05,0xe5,0x07,0xe5,0x1f,0x02,0xe6,0x0d,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x03,0x02,0x02,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x02,0x02,0x06,0x01,0x02,0x02,0x06,0xe5,0x04,0x02,0xe5,0x07,0x06,0x02,0x02,
+ 0xe5,0x04,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe6,0x06,0xe6,0x06,
+ 0x09,0x06,0x06,0x02,0x01,0x02,0x59,0x08,0x0a,0x09,0x10,0x02,0x06,0x17,0x13,0x11,
+ 0x02,0x1d,0x30,0xe5,0x03,0x05,0xe5,0x58,0x13,0x0a,0x13,0x0d,0x0e,0x27,0x03,0x0f,
+ 0x0d,0x2f,0x0a,0x01,0x01,0x5f,0x07,0x01,0x04,0x02,0x1c,0x0c,0x0c,0xe6,0x06,0x06,
+ 0x01,0x09,0x0a,0xe6,0x06,0x09,0xe6,0x0a,0x04,0x0a,0xe6,0x06,0xe6,0x1e,0xe8,0x5b,
+ 0xe5,0x01,0x06,0x01,0xe5,0x07,0xe5,0x08,0x09,0x09,0x03,0x06,0xe5,0x09,0x0f,0x01,
+ 0xe5,0x02,0x02,0x02,0x0a,0x13,0x0f,0x01,0x01,0x09,0x09,0x19,0xe5,0x02,0x01,0xe8,
+ 0x66,0x12,0x1f,0xe5,0x0c,0x01,0x05,0x06,0x2b,0x03,0x0e,0x03,0x09,0x07,0x16,0x0a,
+ 0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,
+ 0x05,0xe5,0x05,0xe7,0x01,0x04,0xe6,0x07,0xe5,0x07,0xe5,0x02,0x02,0xe7,0x07,0xe5,
+ 0x05,0xe7,0x07,0xe5,0x01,0x05,0xe5,0x02,0x02,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe6,
+ 0x03,0x01,0xe8,0x5e,0x07,0x01,0x07,0x02,0x10,0x01,0x16,0x09,0x09,0xe5,0x04,0x01,
+ 0xe5,0x07,0x0a,0x08,0x0a,0x09,0xe5,0x06,0x0a,0x09,0x1b,0x08,0xe5,0x5c,0x09,0x01,
+ 0x09,0x11,0x01,0x1c,0x03,0x01,0xe5,0x01,0x07,0x01,0xe5,0xe5,0x06,0x0e,0xe5,0x01,
+ 0xe5,0xe5,0x0b,0xe5,0x01,0x0a,0x01,0x02,0x09,0xe5,0x01,0x03,0x01,0xe5,0x01,0x1c,
+ 0xe7,0x0b,0x5a,0x01,0x0a,0x06,0x13,0x0a,0x03,0x0d,0xe5,0x02,0x0a,0x13,0x03,0xe5,
+ 0x0d,0x03,0xe5,0x0c,0x0a,0x03,0xe5,0x07,0xe5,0x1b,0xe6,0xe5,0x66,0x01,0x0a,0x29,
+ 0x03,0x01,0x06,0x01,0xe6,0x01,0x03,0x01,0x03,0x09,0x0c,0x01,0xe5,0x01,0x0d,0x01,
+ 0xe5,0x02,0x08,0x0d,0x01,0xe5,0x05,0x01,0xe5,0x1b,0xe5,0xe5,0x73,0x1e,0x1e,0x06,
+ 0xe5,0xe5,0x05,0x01,0xe5,0x11,0xe5,0x27,0x09,0x23,0xe5,0x10,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,
+ 0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x09,0x01,0xe5,0x05,
+ 0x01,0xe6,0x04,0x01,0x03,0x03,0x01,0xe5,0xe5,0xe5,0xe6,0xe5,0x06,0xe6,0x06,0x01,
+ 0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x0a,0xe5,0x01,0x20,0x50,0x01,0xe5,0x04,0x1d,0x01,0x02,0xe5,0xe5,0x06,0xe6,0x01,
+ 0x01,0x0b,0x0c,0x02,0x04,0x0e,0x03,0xe6,0x06,0x0f,0x03,0xe7,0x07,0x20,0xe6,0xe6,
+ 0x08,0x33,0x26,0x05,0x06,0x02,0x17,0x0f,0x05,0x02,0x0f,0x0a,0x0c,0x07,0x05,0xe5,
+ 0xe5,0xe5,0xe6,0x0d,0x07,0x04,0x2c,0x02,0xe7,0x6b,0x04,0x20,0x06,0xe5,0x07,0x15,
+ 0x11,0x1a,0x02,0x01,0x13,0x0d,0x1e,0x02,0xe6,0x02,0xe5,0x5d,0xe5,0x01,0xe6,0x03,
+ 0x05,0x08,0x07,0x01,0x09,0x09,0x02,0x09,0x03,0x04,0x02,0x0b,0x11,0x01,0x02,0x01,
+ 0x53,0xe5,0x01,0xe6,0x66,0x02,0x10,0x08,0x01,0x03,0x03,0x08,0xe6,0x01,0x11,0x05,
+ 0xe5,0x12,0x0c,0x02,0x05,0x4d,0xe5,0x01,0xe5,0x11,0x4c,0x12,0x02,0x09,0x15,0x02,
+ 0x16,0xe5,0x08,0x08,0xe5,0x11,0xe5,0x12,0x08,0xe5,0x01,0x07,0x0b,0x09,0x0a,0x0a,
+ 0xe9,0x42,0x11,0x24,0x08,0x07,0x07,0x09,0x09,0x0b,0x04,0xe5,0x02,0x02,0x01,0x02,
+ 0xe5,0x09,0x01,0x02,0x01,0xe5,0x01,0xe5,0x09,0x01,0xe5,0x07,0x01,0x0e,0x27,0xe8,
+ 0x04,0x22,0x4b,0x01,0x06,0x1b,0xe5,0x1a,0x04,0x01,0x07,0x16,0x0c,0x01,0x18,0x15,
+ 0x17,0x05,0x16,0x40,0xe5,0xe6,0x2b,0xe7,0x05,0xe5,0x15,0x09,0x0c,0x04,0xe5,0xe5,
+ 0x06,0xe6,0x05,0x01,0x09,0x05,0x17,0x1a,0x09,0x02,0x05,0x59,0x29,0x06,0x08,0x05,
+ 0x11,0x08,0x03,0x1b,0x09,0x07,0x0f,0x0d,0x23,0xe6,0xe5,0x50,0x0c,0xe5,0x19,0x36,
+ 0x04,0x02,0x01,0x04,0x02,0x01,0x02,0xe6,0x04,0x10,0x01,0xe5,0x0f,0x01,0x18,0x09,
+ 0x13,0x01,0x01,0x5f,0x04,0x04,0x06,0x13,0x02,0x0c,0x0b,0x09,0x06,0x01,0x02,0x0b,
+ 0x02,0x0a,0x01,0x03,0x02,0x09,0x06,0x0c,0x01,0x07,0x2c,0xe8,0x1b,0x43,0x08,0x1d,
+ 0x0c,0x05,0x14,0xe5,0x0b,0x06,0x13,0x0a,0x04,0x0e,0x06,0x02,0x06,0x06,0x1e,0xe5,
+ 0x01,0xe6,0x71,0xe6,0x09,0xe5,0x05,0xe5,0xe5,0xe5,0x03,0x02,0xe5,0x05,0x03,0x01,
+ 0x04,0x09,0xe5,0x06,0xe5,0x01,0xe5,0x03,0xe6,0x07,0x13,0xe5,0x14,0xe5,0x04,0x09,
+ 0x1e,0x02,0x02,0x02,0x01,0x5d,0x12,0xe5,0x09,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x03,0xe5,0x04,0x01,0x04,0x02,0x01,0x04,0x05,0x02,0x03,0xe5,0x0e,0x05,0x05,0xe5,
+ 0x1c,0x01,0x04,0x09,0x1b,0x01,0x03,0xe5,0xe5,0x03,0x5f,0x01,0xe5,0x03,0x01,0x01,
+ 0x07,0x01,0xe5,0xe5,0x10,0x01,0x0b,0x18,0x01,0x07,0xe5,0xe5,0x02,0xe5,0x0a,0x01,
+ 0x0e,0x01,0xe5,0x03,0x04,0xe5,0x02,0x31,0x04,0xe6,0xe5,0x01,0x6b,0x0c,0x01,0x0e,
+ 0xe5,0xe5,0xe5,0x08,0x19,0xe5,0x01,0x06,0x13,0x1d,0xe5,0x2f,0x06,0x05,0xe5,0x6e,
+ 0x01,0x18,0x09,0x08,0x06,0x05,0x04,0x01,0x02,0x07,0x04,0x04,0x03,0x01,0x05,0x02,
+ 0x04,0x0b,0x07,0x09,0x0b,0x09,0x16,0x07,0xe9,0x01,0x68,0x04,0xe5,0x02,0x09,0x13,
+ 0x07,0x03,0x01,0x01,0xe5,0x09,0x01,0x01,0x08,0x03,0x01,0x03,0x05,0x0a,0x02,0x03,
+ 0x01,0x0a,0x02,0x09,0x05,0x2c,0x02,0xe6,0xe6,0x65,0x07,0x12,0x08,0xe5,0x01,0x01,
+ 0x02,0x08,0x0c,0xe6,0x01,0x01,0x01,0x07,0x02,0x04,0x01,0x05,0x08,0x02,0x15,0x07,
+ 0x01,0x05,0x05,0x02,0x01,0x04,0x02,0x01,0x1a,0x01,0x02,0x81,0xe6,0x04,0xe5,0xe5,
+ 0xe6,0xe5,0xe6,0x05,0x06,0x06,0xe5,0xe5,0xe6,0xe5,0x01,0x04,0x02,0x06,0x02,0x0a,
+ 0xe5,0xe8,0x01,0x0a,0xe5,0x03,0x02,0x06,0x02,0x0b,0xe6,0x06,0xe6,0x1d,0x02,0x6d,
+ 0x1a,0x02,0xe5,0x04,0x0b,0x02,0xe6,0x03,0x09,0x02,0xe5,0x04,0x02,0x02,0x03,0x09,
+ 0x09,0x09,0x02,0xe5,0x04,0x02,0x02,0x03,0x02,0x02,0x03,0x09,0x1b,0x04,0x01,0x02,
+ 0x60,0x0f,0x17,0xe5,0x07,0xe5,0x0a,0x08,0xe5,0x07,0xe5,0x15,0xe5,0x03,0xe5,0x0b,
+ 0x05,0xe5,0x0b,0x0f,0xe5,0x01,0x05,0xe5,0x20,0x02,0xe5,0x0d,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x04,0x01,0x02,0xe5,0x02,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,
+ 0x02,0x03,0x02,0xe5,0x07,0xe5,0x04,0x04,0x01,0x07,0xe5,0x04,0x02,0xe6,0x01,0x01,
+ 0x02,0xe5,0xe5,0x05,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x02,0xe6,0x01,0xe5,0x02,0x01,
+ 0x02,0xe5,0xe6,0x04,0xe5,0x04,0x02,0xe6,0xe5,0x04,0xe6,0x06,0x09,0x0d,0xe5,0x02,
+ 0x02,0x59,0x09,0x09,0x09,0x08,0xe5,0x11,0x15,0xe5,0x08,0x09,0x12,0xe5,0x12,0x12,
+ 0xe5,0x2b,0x02,0xe6,0xe5,0x58,0x0b,0x09,0x07,0x0b,0x05,0x09,0x15,0x03,0x07,0x0b,
+ 0x0f,0x03,0x0f,0x01,0x15,0x31,0xe7,0x59,0x02,0x01,0x01,0x05,0x13,0x09,0x01,0xe7,
+ 0x06,0xe6,0x04,0xe5,0xe7,0x07,0xe6,0x03,0x01,0xe7,0x06,0x09,0x03,0x05,0xe6,0x02,
+ 0x03,0x05,0xe5,0xe8,0x06,0x09,0x06,0x01,0xe7,0x06,0xe6,0x20,0x01,0x5d,0x01,0xe5,
+ 0x07,0xe5,0x09,0x04,0x02,0xe5,0x04,0xe5,0xe7,0x01,0x06,0x07,0x01,0xe6,0x08,0x04,
+ 0xe5,0xe7,0x10,0x0b,0x0f,0x01,0xe6,0x10,0x07,0x01,0xe6,0x08,0x20,0x01,0xe7,0x5b,
+ 0x01,0xe5,0x05,0x06,0x0c,0x06,0x02,0x01,0x01,0x08,0x05,0x02,0x01,0x03,0x0a,0x02,
+ 0x01,0x04,0x02,0x01,0x07,0x0c,0x02,0x0d,0x01,0xe5,0x02,0x04,0x11,0x01,0x03,0xe5,
+ 0x04,0x21,0xe6,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe6,0xe5,
+ 0x02,0xe7,0x05,0xe7,0xe6,0xe6,0x02,0xe6,0x02,0x02,0xe8,0xe6,0x02,0xe6,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x05,0xe7,0x07,0xe6,0xe5,0x02,0xe7,0x01,0x05,0xe5,0x01,0x05,
+ 0xe6,0xe6,0x01,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,0x5f,0xe5,0x05,
+ 0x0b,0x0a,0xe5,0x04,0x01,0x13,0x01,0x04,0x05,0xe5,0x04,0x01,0xe5,0x08,0x13,0xe5,
+ 0x04,0x01,0xe5,0x05,0x01,0xe5,0x08,0x06,0x09,0x01,0xe6,0x07,0xe5,0x23,0x5d,0x01,
+ 0xe5,0x0f,0x13,0x01,0x03,0x02,0x06,0x02,0x01,0xe5,0xe5,0x01,0x03,0x06,0x02,0xe5,
+ 0xe6,0x04,0x0c,0x0d,0x02,0x02,0xe5,0x05,0x01,0x03,0x02,0x03,0x08,0x07,0x01,0x03,
+ 0x02,0x06,0x02,0x14,0xe5,0x03,0xe6,0x01,0x5f,0x07,0x0b,0x13,0x04,0xe5,0x07,0xe5,
+ 0x04,0x0e,0xe5,0x02,0x04,0x04,0xe5,0x16,0xe5,0x02,0x09,0xe5,0x02,0xe5,0x02,0x13,
+ 0x04,0xe5,0x07,0xe5,0x14,0x07,0xe5,0xe5,0x5c,0x01,0xe5,0x0f,0x04,0x07,0x06,0x01,
+ 0x02,0xe5,0xe6,0x04,0xe5,0xe6,0x01,0x01,0x06,0x05,0xe5,0xe7,0xe5,0x01,0x03,0x03,
+ 0x15,0xe5,0xe6,0x02,0x06,0x01,0x02,0xe5,0xe7,0x01,0x10,0x01,0x02,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x14,0x03,0x05,0x11,0x55,0x01,0xe6,0x04,0x03,0xe5,0x08,0x19,0x1e,0xe5,
+ 0xe5,0x13,0x05,0x17,0xe5,0x03,0x03,0x36,0x01,0x11,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x04,0x02,
+ 0x01,0xe5,0x04,0xe5,0xe6,0x05,0x01,0x01,0x05,0x01,0x01,0x06,0xe5,0xe5,0x01,0x04,
+ 0xe8,0x04,0x01,0x04,0x02,0x01,0x02,0x04,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x03,
+ 0xe6,0xe5,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,
+ 0x07,0x01,0x0b,0x01,0xe5,0x6d,0x04,0x0b,0x07,0xe5,0x07,0xe5,0x0e,0x04,0xe6,0x06,
+ 0xe5,0x03,0x03,0xe5,0x11,0xe6,0x05,0x0a,0xe5,0x03,0x05,0x04,0x01,0x03,0x06,0xe5,
+ 0x01,0x05,0xe6,0x20,0xe8,0x4f,0x0a,0x04,0x09,0x02,0x13,0x04,0x06,0x02,0xe5,0x13,
+ 0xe5,0x07,0x07,0x02,0x0b,0x06,0x03,0x0e,0x07,0x13,0x02,0x03,0x05,0xe5,0x04,0x1a,
+ 0xe5,0xe5,0xe5,0x47,0x1a,0x06,0x07,0x12,0x09,0x14,0xe5,0x08,0x04,0x06,0x11,0x04,
+ 0x0f,0x1a,0x01,0x09,0x0f,0x14,0x02,0xe5,0x1c,0x33,0x0b,0x09,0x0b,0x07,0x03,0x09,
+ 0x03,0x09,0x03,0x01,0x0e,0x01,0x02,0x07,0x01,0x04,0x09,0x01,0x0a,0x01,0x09,0xe5,
+ 0x05,0x01,0x07,0x01,0x01,0x01,0x05,0x05,0x26,0x02,0xe6,0x5d,0x01,0x08,0x06,0x0b,
+ 0x10,0x09,0xe6,0x01,0x12,0x08,0x02,0x04,0x13,0x04,0x06,0x09,0x01,0x05,0x04,0x06,
+ 0x05,0x2a,0xe7,0x02,0x0d,0x50,0x0e,0xe6,0x07,0x0c,0x06,0x03,0xe5,0x01,0x01,0x01,
+ 0x03,0xe5,0x0a,0x02,0x03,0x0f,0x03,0x09,0x03,0xe6,0xe5,0xe5,0x13,0x02,0xe6,0x03,
+ 0x09,0x0d,0xe5,0x1b,0xe5,0x01,0x09,0x01,0x2a,0x02,0x0e,0x0c,0x06,0xe5,0x04,0x09,
+ 0x09,0xe5,0x10,0xe6,0x07,0xe7,0x07,0x09,0xe5,0x07,0x09,0xe5,0xe5,0x01,0xe5,0x01,
+ 0x02,0x06,0x02,0x09,0x0b,0x03,0xe5,0x01,0x1a,0x1e,0x29,0x38,0x06,0x01,0xe5,0x02,
+ 0x02,0x01,0x07,0x02,0x10,0x06,0xe5,0x02,0x07,0x08,0x02,0x09,0x06,0x02,0x01,0x07,
+ 0x06,0x02,0x02,0x01,0x18,0x0b,0xe5,0x0f,0x04,0x13,0x03,0xe5,0x7a,0x1c,0x05,0xe5,
+ 0xe5,0xe5,0x07,0x04,0x19,0x1b,0x09,0x0d,0x02,0x2a,0xe5,0x01,0x7c,0x0d,0x0a,0x03,
+ 0x57,0x08,0x07,0x0c,0x1f,0x01,0xe5,0x32,0x24,0x0e,0x01,0xe5,0x05,0x01,0x07,0x01,
+ 0x16,0x06,0x01,0x11,0x01,0x02,0x18,0x01,0x0f,0x0a,0x09,0x02,0x1d,0x18,0xe6,0xe5,
+ 0x72,0x03,0x05,0x10,0xe5,0xe5,0x03,0x07,0x08,0x02,0x24,0x09,0xe5,0x16,0x03,0xe5,
+ 0x21,0x12,0xe5,0xe7,0x61,0x0f,0x02,0x04,0x02,0x0b,0x09,0x10,0x01,0x02,0x25,0x09,
+ 0x0b,0x11,0x03,0x07,0x02,0x0c,0x1c,0x01,0x01,0x6a,0x04,0x1d,0x0a,0xe5,0x01,0x02,
+ 0xe5,0x01,0x02,0xe5,0x04,0x09,0x09,0x02,0xe5,0x04,0x02,0xe5,0x04,0x09,0x02,0x09,
+ 0x09,0x0a,0x02,0xe5,0x04,0x1e,0xe6,0xe5,0xe5,0x01,0x01,0x6c,0xe5,0x2d,0xe5,0x1c,
+ 0x01,0x0e,0x0f,0x21,0x02,0xe5,0x04,0x1b,0x01,0x03,0x01,0xe5,0x03,0x5f,0xe5,0x0a,
+ 0x01,0x04,0x01,0xe5,0x0f,0x07,0x01,0x09,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,
+ 0x06,0x02,0x07,0x01,0x09,0x01,0x48,0x06,0x01,0x64,0x09,0x02,0x01,0x04,0x02,0xe5,
+ 0x0e,0x01,0xe5,0x05,0x01,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x19,0xe5,0x1b,0xe5,0x18,0x03,0x01,
+ 0xe6,0x04,0x05,0xe5,0x05,0x01,0x4e,0x09,0x01,0x01,0x02,0xe5,0xe7,0x01,0x06,0x01,
+ 0x07,0x01,0x06,0x02,0x01,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x03,0x02,0xe5,0x14,0xe5,0x04,0x05,0x09,0x07,0x03,0x01,0x13,0xe6,
+ 0x08,0x01,0xe5,0x01,0x04,0x01,0x54,0x05,0x01,0x02,0x03,0xe5,0x08,0x01,0x01,0x07,
+ 0x01,0x01,0x01,0xe5,0x03,0x01,0x01,0x01,0xe5,0x01,0x01,0x01,0x01,0xe5,0x01,0x01,
+ 0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0xe5,0x15,0x03,
+ 0xe6,0x13,0x02,0x05,0x0e,0x03,0x01,0xe5,0x0c,0x5b,0x07,0x01,0x05,0x04,0x06,0x01,
+ 0x09,0x0b,0x04,0x01,0x02,0x09,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x04,0xe5,
+ 0x07,0x01,0x07,0x02,0x01,0x0b,0x01,0xe5,0x05,0x01,0xe5,0x03,0x05,0x11,0x01,0xe5,
+ 0xe5,0x0e,0x59,0x07,0x01,0x0a,0x06,0x01,0x07,0x01,0x09,0x01,0x04,0x01,0xe5,0xe5,
+ 0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x03,0xe6,0x06,0xe5,0x08,0xe5,
+ 0xe5,0x01,0x03,0x07,0x01,0x01,0x05,0x01,0x01,0xe5,0xe6,0x16,0x02,0xe6,0x07,0x02,
+ 0x06,0xe5,0x57,0x02,0x06,0x06,0x10,0x0b,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,
+ 0x05,0x03,0x05,0x03,0x05,0x09,0x0b,0x04,0x02,0x01,0xe5,0x02,0x09,0x09,0x02,0xe5,
+ 0x0c,0x05,0xe5,0xe6,0x09,0xe5,0x04,0x02,0x65,0x04,0x21,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x01,0x01,0xe5,0x08,0x09,0x05,0xe5,
+ 0x07,0xe5,0x23,0xe5,0x0d,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x02,
+ 0x06,0x09,0x09,0x04,0x01,0xe5,0xe5,0x08,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,
+ 0xe5,0xe5,0x01,0x04,0x01,0x06,0xe5,0xe5,0x01,0x06,0x09,0x05,0x03,0xe5,0x03,0x03,
+ 0xe6,0x06,0xe6,0x03,0x02,0xe5,0xe5,0x05,0x0d,0xe5,0xe7,0x01,0x63,0x09,0x13,0x0a,
+ 0x0b,0x08,0xe5,0x08,0x08,0xe5,0x06,0xe6,0x07,0xe5,0x06,0xe6,0x1b,0x1c,0x19,0x03,
+ 0xe5,0xe5,0x64,0x09,0x13,0x1a,0x04,0x04,0x09,0x04,0x04,0x04,0x04,0x03,0x05,0x04,
+ 0x04,0x16,0x3e,0x01,0x0a,0x59,0x02,0x06,0x0e,0xe5,0x07,0x12,0x02,0x09,0x09,0x04,
+ 0x01,0x02,0x09,0x09,0x09,0x07,0x01,0x07,0x01,0x0a,0x03,0x05,0xe6,0x06,0xe6,0x03,
+ 0x02,0x15,0x02,0xe7,0x10,0x01,0x53,0x03,0x05,0x01,0x01,0x07,0xe6,0xe5,0x02,0x03,
+ 0x02,0x01,0x02,0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x04,0xe5,0xe6,0x02,0x01,0xe5,0xe7,0xe5,0x02,
+ 0x01,0x01,0x05,0x0d,0x09,0x05,0x1e,0x0d,0x01,0x57,0x01,0x09,0x03,0xe5,0x03,0x09,
+ 0x23,0x14,0x13,0x0b,0x21,0x0c,0x1e,0x01,0x01,0x04,0x08,0x01,0x05,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,
+ 0x06,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x01,0x05,0xe5,0xe5,0x01,0x04,0xe6,0x01,0x03,
+ 0x01,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x03,0xe7,0x01,0x05,
+ 0xe5,0x05,0x01,0xe5,0x07,0xe6,0x06,0xe5,0x05,0xe7,0x02,0x02,0xe7,0x07,0xe5,0x07,
+ 0xe5,0x0a,0x67,0x01,0x27,0xe5,0x14,0x09,0x09,0x09,0x13,0xe5,0x04,0x01,0x11,0x0c,
+ 0xe5,0x07,0xe5,0x22,0xe5,0x66,0x27,0x01,0x0b,0x06,0x02,0x03,0x02,0x02,0x06,0x02,
+ 0x09,0x09,0x06,0x02,0x07,0x01,0x06,0x05,0x04,0x0f,0x02,0x06,0x02,0xe5,0x12,0xe5,
+ 0x03,0xe5,0x01,0xe5,0x0c,0x01,0x01,0x55,0x01,0x01,0x09,0x09,0x09,0x07,0xe5,0x06,
+ 0x02,0x04,0x04,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x03,0xe6,0x02,0x0b,
+ 0x01,0x01,0x19,0x02,0xe5,0x04,0x02,0xe5,0x14,0x06,0xe5,0xe6,0x0c,0x01,0x57,0x27,
+ 0x01,0xe5,0x07,0x01,0x06,0xe5,0xe6,0x01,0xe8,0xe6,0x02,0x01,0xe5,0xe6,0x05,0x01,
+ 0xe5,0x05,0x01,0x03,0xe8,0xe6,0x0c,0xe6,0x19,0x01,0xe5,0x05,0x01,0xe6,0x13,0x03,
+ 0x01,0xe5,0x01,0x61,0x08,0x06,0x09,0x02,0x0a,0x05,0x02,0x08,0x02,0x06,0x02,0x09,
+ 0x06,0xe5,0xe6,0x07,0xe5,0x01,0x02,0xe5,0xe6,0x07,0xe5,0x01,0x02,0xe5,0xe5,0x0f,
+ 0x02,0x1a,0x1b,0xe5,0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0xe6,0x04,0x01,0x03,0x03,0x01,0x03,0x03,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0xe5,0xe5,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x03,
+ 0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x03,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0b,0xe5,0xe5,0x01,0x0e,
+ 0x48,0x0c,0x13,0x02,0x02,0x02,0x04,0x05,0xe7,0x01,0x04,0xe6,0x03,0x03,0xe7,0x01,
+ 0xe5,0x01,0x02,0xe5,0x02,0x03,0x07,0x02,0x01,0x06,0xe5,0x01,0x03,0x07,0x02,0x0c,
+ 0x05,0xe5,0x02,0x06,0xe5,0x01,0xe5,0xe5,0x01,0xe6,0x01,0x03,0x05,0x15,0x01,0xe5,
+ 0x3c,0x12,0x28,0xe5,0x02,0x0e,0x06,0x01,0x09,0x03,0x05,0x03,0x06,0x0b,0xe5,0x02,
+ 0x09,0x0e,0x06,0x1d,0x14,0x12,0x02,0xe6,0x29,0x56,0x06,0x06,0x01,0x06,0x0e,0x01,
+ 0x01,0x02,0x03,0x01,0x03,0x01,0x01,0x10,0x01,0x02,0x07,0x13,0x10,0x01,0x07,0x01,
+ 0x24,0xe7,0x31,0x25,0x0f,0x07,0xe5,0x09,0x09,0x07,0xe5,0x09,0x01,0x03,0x01,0x01,
+ 0x01,0x07,0x01,0xe5,0x02,0x02,0x04,0x01,0xe5,0xe5,0x03,0x06,0x07,0x13,0xe6,0x08,
+ 0x1b,0x01,0x19,0x01,0xe5,0x44,0x21,0x06,0x06,0x03,0x01,0x12,0x06,0x03,0x04,0x08,
+ 0x09,0x09,0x09,0x05,0x09,0x03,0x01,0x15,0x01,0x22,0x1b,0xe5,0x07,0x04,0xe5,0x02,
+ 0x43,0x01,0x1b,0x0b,0x03,0xe6,0x02,0x04,0xe5,0x01,0x04,0xe8,0x02,0x03,0x05,0x03,
+ 0x04,0x06,0x03,0x05,0x03,0x03,0x0b,0xe5,0x0b,0x03,0x09,0xe6,0x02,0x13,0x03,0x0f,
+ 0x0e,0x0d,0x01,0x0f,0x10,0x2c,0x01,0x14,0x09,0x02,0x03,0x01,0x2e,0x02,0xe8,0x04,
+ 0xe6,0x09,0x03,0x02,0xe6,0x19,0xe5,0xe5,0x37,0xe6,0x09,0x42,0x14,0x1d,0x12,0xe5,
+ 0x03,0x0f,0x0a,0x09,0xe5,0x07,0x13,0x01,0x01,0x13,0x04,0x0a,0x08,0x0c,0x13,0x03,
+ 0x53,0xe5,0x03,0x0d,0xe5,0x07,0xe5,0x03,0x1f,0x01,0x09,0xe7,0x04,0x02,0xe5,0x18,
+ 0x02,0xe5,0x06,0x0a,0xe5,0x0d,0x01,0x0b,0xe5,0x07,0xe5,0x03,0x06,0x17,0x01,0xe6,
+ 0x54,0x13,0x09,0x06,0x11,0x09,0x02,0x05,0x08,0xe5,0x07,0xe5,0x03,0x12,0x04,0x13,
+ 0xe5,0x16,0x04,0x09,0x22,0x02,0x0f,0x44,0x02,0x07,0x08,0x04,0x04,0xe5,0x02,0x01,
+ 0x01,0x01,0x09,0x09,0x08,0x03,0x07,0x09,0x0a,0x09,0x08,0x04,0x02,0x02,0x08,0x07,
+ 0x03,0x08,0x08,0x01,0x07,0x03,0x20,0x01,0xe5,0x0e,0x3e,0x1a,0xe5,0x07,0x09,0x07,
+ 0xe6,0x08,0x03,0x16,0x0e,0x09,0x04,0x09,0x02,0xe6,0x03,0x18,0x0e,0x09,0x0b,0x10,
+ 0x01,0x02,0x0d,0xe5,0x3e,0x0e,0x0b,0x0a,0xe5,0x06,0x01,0x0f,0x01,0x08,0x1e,0xe5,
+ 0x06,0xe6,0x10,0x1a,0x03,0xe5,0x38,0xe8,0x0a,0x3e,0xe5,0x39,0xe5,0x17,0xe5,0xe5,
+ 0x02,0x02,0xe5,0xe5,0x02,0xe5,0x14,0xe5,0x04,0x13,0x08,0xe5,0x01,0xe5,0x03,0xe5,
+ 0x01,0xe5,0x04,0x02,0xe5,0x04,0x0a,0x13,0xe7,0xe6,0x01,0x01,0x08,0xe6,0x35,0x01,
+ 0x15,0x03,0x22,0x03,0x1b,0x02,0x01,0x04,0x02,0x1d,0x0d,0x01,0x03,0x0a,0x12,0x09,
+ 0x06,0xe5,0x13,0x01,0x03,0x01,0xe5,0x03,0x05,0xe5,0xe5,0xe5,0x3c,0x11,0x22,0xe5,
+ 0x20,0x09,0x06,0x01,0x06,0xe5,0x12,0xe5,0x1b,0x01,0x02,0x01,0x16,0x01,0xe5,0x14,
+ 0x04,0x03,0x02,0x0a,0x01,0x72,0xe5,0x10,0xe5,0x0d,0x09,0x06,0xe5,0x1a,0xe5,0x1f,
+ 0x1a,0x04,0x15,0x02,0xe6,0xe5,0x0e,0x04,0x01,0x7a,0x02,0xe5,0x01,0x07,0x04,0x04,
+ 0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x11,0x02,0x02,0x05,0x09,0x02,0x03,0x02,0xe5,
+ 0x01,0x12,0x02,0x02,0x0a,0x03,0x02,0x01,0x4a,0x04,0x25,0x01,0xe5,0x03,0x0b,0x04,
+ 0x03,0x05,0x03,0x0a,0x09,0x13,0x1b,0x05,0x14,0x04,0x12,0x05,0xe6,0x0b,0x01,0x55,
+ 0x2b,0x09,0x01,0x07,0x09,0x03,0x05,0x01,0x07,0x01,0x11,0x01,0x1b,0x07,0x05,0x09,
+ 0x05,0x19,0xe5,0x02,0x0d,0x01,0x7f,0x0a,0xe5,0xe5,0x06,0x03,0xe5,0x03,0x04,0x04,
+ 0x01,0x07,0x01,0x0b,0xe5,0x03,0x01,0x0b,0xe7,0x0b,0x02,0x0b,0xe6,0x06,0x06,0x18,
+ 0xe8,0x12,0xe5,0x4d,0x02,0x10,0x1d,0xe5,0x09,0xe5,0x04,0x09,0x0c,0xe5,0x0e,0x13,
+ 0x13,0x02,0x06,0x09,0x25,0x14,0x4f,0xe5,0x07,0x0b,0x07,0xe5,0x04,0x0c,0xe5,0x09,
+ 0xe5,0x03,0xe5,0x07,0xe5,0x1b,0xe5,0x11,0xe5,0x17,0x03,0xe5,0x07,0xe5,0x15,0x09,
+ 0xe5,0xe7,0x0d,0x02,0xe5,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x09,
+ 0x04,0xe6,0x01,0x06,0x02,0x09,0x09,0x04,0x01,0x01,0x02,0x09,0xe5,0x07,0xe7,0x05,
+ 0x04,0x01,0x02,0x09,0xe5,0x02,0x01,0x02,0x09,0xe5,0x07,0x09,0xe5,0x07,0xe6,0x06,
+ 0xe6,0x03,0x02,0x04,0x01,0x02,0x03,0x09,0x01,0xe7,0x01,0x59,0x09,0x09,0x06,0x02,
+ 0x1d,0x29,0x31,0x1c,0xe5,0x08,0x0e,0x03,0xe5,0xe5,0x5a,0x09,0x08,0x09,0x1e,0x02,
+ 0x0e,0x17,0x0f,0x13,0x0b,0x1f,0x09,0x15,0xe5,0xe5,0x6e,0x01,0x10,0xe5,0xe5,0x08,
+ 0x0b,0x0a,0x01,0x01,0x05,0xe6,0xe5,0x03,0x04,0x04,0x0a,0x01,0x01,0x04,0x0a,0xe6,
+ 0x0d,0x02,0x03,0x05,0xe6,0x06,0xe6,0x03,0x09,0x0e,0x03,0x01,0x0a,0x06,0x4f,0x05,
+ 0x02,0x06,0x01,0xe5,0x04,0x02,0xe5,0x02,0x02,0x01,0xe6,0xe5,0x04,0x01,0x07,0x03,
+ 0x09,0x09,0x07,0x01,0x09,0x02,0x06,0x09,0x09,0x11,0x0b,0x09,0x07,0x01,0x05,0x01,
+ 0x01,0x0d,0xe7,0x0e,0x53,0x0a,0x02,0x01,0x11,0x01,0x04,0x09,0x03,0x2a,0x13,0x0b,
+ 0x01,0x0d,0x1a,0x02,0x0b,0x03,0x0b,0xe7,0x0e,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,
+ 0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x08,0xe6,0x05,0xe7,0x02,0x03,0xe6,0x07,0xe5,
+ 0x07,0xe5,0x05,0xe7,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x02,0x02,0xe7,0x02,
+ 0x02,0xe7,0x01,0x05,0xe5,0x07,0xe5,0x09,0xe5,0x55,0x13,0x08,0xe5,0x11,0x09,0x0b,
+ 0x14,0x08,0x09,0x13,0x28,0xe5,0x07,0x06,0x09,0x01,0x0e,0xe6,0xe5,0x11,0x43,0x06,
+ 0x03,0x08,0x06,0x01,0xe5,0x11,0x02,0x06,0x01,0x07,0x03,0x04,0x05,0xe5,0x01,0x05,
+ 0x03,0x02,0x01,0x09,0x0a,0xe5,0x01,0x04,0x0a,0xe5,0x01,0x0c,0x0c,0xe5,0x01,0x05,
+ 0xe5,0x01,0x02,0x01,0x05,0x01,0x01,0x0f,0xe5,0x0e,0x61,0x01,0x13,0x12,0x07,0x09,
+ 0xe5,0x03,0x03,0x0e,0x0e,0xe5,0x02,0x0e,0xe5,0x1b,0xe5,0x03,0x03,0xe5,0xe5,0x19,
+ 0x03,0x0f,0x46,0x13,0x06,0x01,0xe5,0x11,0x1a,0x01,0x06,0x01,0xe5,0x08,0x1a,0x01,
+ 0xe5,0x0f,0x01,0xe5,0x19,0x01,0xe5,0x05,0x01,0xe5,0x01,0x1a,0x01,0x12,0x45,0x04,
+ 0x0d,0xe5,0x07,0x0f,0x02,0xe5,0x1d,0x06,0x04,0x12,0x2d,0x02,0x0a,0x26,0x03,0xe5,
+ 0x01,0x01,0x0f,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x02,0x04,0x01,0x04,0x01,0xe5,0xe5,0xe5,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x02,0x04,0x01,0x09,0x01,0x06,0xe5,0xe6,0x05,0x01,0x07,0x01,0x07,0x01,0x02,0x03,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x06,0xe7,0x06,0x01,0x07,
+ 0x01,0x07,0x01,0x08,0x02,0xe7,0x0a,0x05,0x45,0x09,0x04,0x09,0x14,0xe6,0x11,0x05,
+ 0x04,0x01,0xe6,0x05,0xe6,0x15,0x05,0xe5,0x18,0x02,0xe5,0x04,0xe6,0x0e,0x04,0xe5,
+ 0x02,0x07,0x08,0x0e,0xe7,0x03,0x06,0x30,0x1e,0x06,0x07,0x09,0x0e,0x12,0x0d,0x08,
+ 0xe5,0x05,0x11,0x05,0xe5,0x1c,0x0d,0x0e,0xe5,0x05,0x08,0x11,0x01,0x02,0x5c,0x09,
+ 0x07,0x07,0x07,0x07,0x13,0x06,0x05,0xe5,0xe5,0x05,0x02,0x15,0x07,0x09,0x01,0x0c,
+ 0x44,0x01,0x10,0x5f,0xe8,0x05,0x02,0x08,0xe5,0x01,0x06,0x19,0x13,0x0b,0x07,0x1a,
+ 0x07,0x25,0xe6,0x0d,0x03,0x08,0x02,0x4b,0x0b,0x0d,0x0b,0x07,0x04,0x0e,0x05,0x53,
+ 0x01,0x28,0x11,0xe6,0x18,0x21,0x18,0xe5,0x16,0x06,0x01,0x14,0x09,0x03,0x03,0x03,
+ 0x06,0x0b,0x06,0x03,0x01,0x03,0x03,0x06,0x09,0x0c,0x07,0x15,0x07,0x21,0xe5,0xe5,
+ 0x10,0x05,0xe5,0x34,0x04,0x04,0xe5,0x02,0x01,0x07,0x01,0xe5,0x05,0x01,0x0a,0x09,
+ 0x09,0x08,0xe5,0xe5,0x09,0x0f,0xe5,0x06,0xe6,0x1e,0x1d,0x03,0x07,0x04,0x1e,0x01,
+ 0x08,0x0c,0x3b,0x04,0x0b,0xe5,0x07,0x06,0x02,0x07,0x18,0x03,0x0b,0x0c,0x04,0x02,
+ 0x04,0x10,0x09,0x0b,0x23,0x04,0x06,0x01,0x14,0xe5,0x0d,0x04,0x40,0x04,0x03,0xe5,
+ 0x03,0x13,0x0e,0x01,0xe5,0x0e,0xe6,0x13,0x0f,0x05,0x06,0xe5,0x11,0xe5,0x18,0x02,
+ 0xe5,0x07,0xe5,0x0a,0x17,0xe8,0x0f,0x03,0x41,0x08,0x27,0x11,0x01,0x0e,0x06,0x05,
+ 0x15,0x01,0x02,0x03,0x0a,0x01,0x15,0x05,0x01,0x07,0x01,0x06,0x1c,0xe7,0x04,0x04,
+ 0x02,0x01,0x45,0x04,0x03,0xe5,0x06,0x01,0x09,0x07,0x01,0x1c,0xe5,0xe5,0x02,0x09,
+ 0x0d,0x01,0xe5,0x1b,0x01,0x08,0x31,0x17,0x01,0xe7,0x04,0x08,0x09,0x3a,0x0a,0x01,
+ 0x11,0x09,0x1f,0x14,0xe5,0x06,0x04,0x02,0x01,0x13,0x39,0x01,0x17,0x04,0x05,0xe5,
+ 0x02,0x03,0x09,0x44,0x01,0x0b,0x05,0x01,0x09,0x0b,0x10,0x02,0x17,0x05,0x0d,0x0c,
+ 0x03,0x0a,0x27,0x09,0x16,0x03,0xe6,0x55,0x04,0x02,0xe5,0x0e,0x16,0xe5,0x13,0xe5,
+ 0x01,0xe5,0x0a,0x03,0x16,0xe5,0x04,0x0c,0xe5,0x04,0x05,0x10,0xe5,0x04,0x02,0xe5,
+ 0x04,0xe5,0x08,0x13,0xe7,0xe6,0x01,0x01,0x0d,0x40,0xe5,0x07,0x02,0x10,0x17,0x14,
+ 0x0d,0x01,0xe5,0x01,0x1d,0x13,0x06,0x16,0x09,0x1c,0x01,0x04,0x01,0x04,0x0b,0x3f,
+ 0xe5,0x0a,0x13,0x3d,0x3b,0x3d,0x04,0xe5,0x01,0x02,0x0b,0x02,0x01,0xe5,0x3a,0x13,
+ 0x31,0x18,0x06,0x08,0xe5,0x29,0x24,0xe5,0x18,0x02,0xe5,0x01,0x05,0x0a,0x0b,0x34,
+ 0x03,0xe5,0xe6,0x01,0xe5,0x05,0xe7,0x08,0x01,0x04,0x01,0x1c,0x03,0x02,0x03,0x01,
+ 0x05,0x04,0x04,0x02,0x06,0x13,0x13,0x04,0x18,0x09,0x0a,0x02,0x11,0xe5,0xe6,0x01,
+ 0x02,0x16,0x39,0x06,0x03,0x01,0x02,0x02,0x01,0x01,0x02,0x2a,0x02,0x02,0x02,0x0a,
+ 0x03,0x0a,0x2c,0x03,0x23,0x08,0x0e,0x03,0x01,0xe6,0x03,0x0a,0x06,0x01,0x3e,0x18,
+ 0x04,0x23,0x02,0x0e,0x01,0xe5,0x02,0xe5,0x03,0x01,0x07,0x01,0x0c,0x18,0x17,0x09,
+ 0x0d,0x11,0x01,0x01,0xe5,0x0f,0x06,0x01,0x3c,0xe5,0x42,0x02,0x0a,0xe5,0xe5,0xe6,
+ 0x03,0x04,0x01,0x07,0x01,0x0b,0xe5,0x11,0xe5,0x03,0x10,0x01,0x05,0x09,0x21,0xe6,
+ 0x04,0x0a,0x02,0x02,0x3f,0x02,0x02,0x41,0x02,0x06,0x09,0x1d,0x13,0x1d,0x09,0x0c,
+ 0xe5,0x12,0xe5,0x01,0x10,0x0d,0x37,0x03,0x09,0x09,0x06,0x24,0x09,0x03,0xe5,0x07,
+ 0xe5,0x12,0x02,0x05,0xe5,0x11,0xe5,0x1b,0xe5,0x07,0xe5,0x08,0x16,0xe9,0xe5,0x06,
+ 0x01,0x02,0xe5,0xe5,0x05,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0xe5,0x03,0xe5,0x01,
+ 0x05,0x03,0x02,0x02,0x03,0x09,0x09,0x09,0x06,0x04,0xe5,0x07,0xe5,0x07,0xe6,0x01,
+ 0x01,0x02,0x09,0x05,0x03,0xe5,0x07,0x09,0xe5,0x07,0x09,0x09,0xe6,0x06,0xe6,0x01,
+ 0x01,0x02,0x09,0x0d,0x01,0xe5,0xe5,0x01,0x09,0x09,0x42,0x02,0x09,0x2e,0x02,0x3d,
+ 0x3b,0x18,0x02,0x01,0x01,0x09,0x09,0x47,0x08,0x31,0x12,0x27,0x01,0x11,0x29,0x1e,
+ 0xe8,0x0c,0x01,0xe6,0x04,0x01,0x3b,0xe6,0x0b,0x02,0x01,0x04,0x0e,0x1c,0xe5,0x01,
+ 0x09,0x01,0x07,0xe6,0x05,0x09,0x0a,0x01,0x01,0x04,0x0a,0x01,0x1b,0xe6,0x06,0xe6,
+ 0x03,0x1b,0xe7,0x0c,0x01,0xe5,0x07,0x01,0x39,0x01,0x04,0x03,0x06,0x01,0x01,0x02,
+ 0x06,0x01,0x05,0xe5,0x1b,0x0d,0x09,0x09,0x07,0x01,0x01,0x07,0x05,0x01,0xe5,0x09,
+ 0x0c,0x10,0x09,0x05,0x01,0x01,0x01,0x0d,0xe5,0x01,0xe5,0x02,0x01,0xe5,0x0b,0x02,
+ 0x0c,0x14,0x23,0x0c,0xe5,0x01,0x01,0x09,0x06,0x02,0x04,0x18,0x06,0x13,0x04,0x1b,
+ 0x01,0x04,0x27,0x0e,0x19,0x01,0xe5,0x0c,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x05,0xe7,0x05,0xe7,0x02,0x03,0xe6,
+ 0x07,0xe5,0x07,0xe5,0x05,0xe8,0xe5,0x04,0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x02,
+ 0x02,0xe7,0x02,0x02,0xe7,0x06,0xe6,0x07,0xe7,0x02,0x02,0x02,0x0d,0x01,0x28,0x2e,
+ 0x01,0x07,0x0b,0x0a,0x09,0x1f,0x08,0x09,0x11,0x01,0xe5,0x1c,0xe5,0x07,0x09,0x06,
+ 0x08,0x0f,0x03,0x01,0x0d,0x01,0x07,0x03,0x3c,0x0e,0x01,0x02,0x04,0x04,0x06,0x0a,
+ 0x12,0x07,0xe5,0x03,0x01,0x02,0x04,0x04,0x05,0x06,0x02,0x08,0x01,0x02,0xe5,0xe5,
+ 0x0a,0x01,0x02,0x18,0x01,0x02,0x04,0x01,0x02,0xe5,0xe5,0x01,0x01,0x0c,0xe5,0x03,
+ 0xe5,0x01,0xe6,0x0b,0x01,0x28,0x26,0x09,0x09,0x09,0x14,0x07,0x06,0xe5,0x08,0xe5,
+ 0x03,0x03,0x04,0x18,0xe5,0xe5,0xe6,0x0c,0xe5,0x17,0x03,0xe5,0x03,0x03,0xe5,0x02,
+ 0x11,0x08,0xe6,0x03,0x08,0x01,0x28,0x2e,0x01,0x09,0x09,0x0a,0x09,0x0f,0x01,0x06,
+ 0x01,0xe5,0x08,0x1a,0x01,0xe6,0xe6,0x0b,0x01,0xe5,0x0c,0x0c,0x01,0xe5,0x05,0x01,
+ 0xe5,0x06,0x0d,0x03,0x01,0x02,0xe6,0x51,0x01,0xe5,0x07,0xe5,0x0f,0x02,0x14,0x03,
+ 0x06,0x06,0x01,0xe6,0x0e,0x3b,0xe5,0xe5,0x25,0xe5,0x17,0x02,0x03,0xe5,0x0b,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x06,0x02,0xe6,0x06,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0xe6,0xe5,0x04,0x01,0x02,
+ 0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x03,0x06,0xe6,0xe5,0x03,0x0a,0xe5,0x01,0x07,0x1b,0x33,0x05,0xe5,0x01,
+ 0x04,0x0c,0xe6,0x03,0x02,0xe5,0x06,0x0c,0xe5,0x07,0xe6,0x03,0x09,0x04,0x03,0x03,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x06,0x14,0xe5,0x07,0xe5,0x1c,0x07,0xe5,0x0b,0x08,0x4e,
+ 0x12,0x0d,0xe6,0x01,0x03,0x07,0xe5,0x0a,0x01,0x07,0xe5,0x05,0x15,0x01,0xe5,0x07,
+ 0xe5,0xe6,0x02,0xe5,0x05,0x0a,0x0a,0xe5,0x07,0xe5,0x05,0x0b,0x10,0xe5,0xe7,0x01,
+ 0x02,0x09,0x26,0x23,0x01,0x34,0x15,0x02,0x06,0x22,0x0e,0x1d,0x05,0x03,0x23,0xe5,
+ 0xe5,0x07,0x06,0x09,0x01,0x37,0x09,0x01,0x01,0x04,0xe6,0x07,0xe6,0x28,0x0d,0x6c,
+ 0x07,0x0f,0xe6,0x08,0x01,0x01,0x48,0x02,0x03,0x02,0x11,0x02,0x23,0xe5,0x10,0x1e,
+ 0x3c,0x26,0xe7,0x16,0xe6,0x16,0x13,0x12,0x06,0xe5,0x06,0xe5,0x13,0x01,0x0a,0x06,
+ 0x01,0x04,0x01,0x0f,0x04,0xe5,0x01,0x0a,0x05,0x0f,0x05,0x01,0x1a,0x16,0x20,0xe6,
+ 0x0f,0x06,0x01,0x0a,0x1d,0x0e,0x15,0x01,0x02,0x0d,0x1b,0x03,0x03,0x09,0x1a,0x01,
+ 0xe5,0x54,0x11,0x01,0x01,0x01,0x08,0x07,0x4d,0xe5,0xe5,0x09,0x09,0x07,0x18,0x27,
+ 0x04,0x0d,0x5d,0x05,0x0e,0x1d,0x3e,0xe5,0x08,0x05,0x02,0xe6,0x05,0xe7,0x05,0xe5,
+ 0x01,0x02,0x04,0xe5,0x01,0x06,0x09,0x07,0x01,0xe5,0x07,0x01,0x07,0xe5,0x06,0x01,
+ 0x33,0x19,0xe6,0x01,0x0e,0x46,0x18,0xe5,0x08,0x0b,0x08,0x07,0x02,0x08,0x09,0x09,
+ 0x0b,0x11,0x01,0x0a,0x49,0xe5,0x01,0x03,0x15,0x22,0x22,0xe5,0x03,0xe5,0x01,0x09,
+ 0x18,0x0d,0x06,0x06,0x02,0x05,0x04,0x0d,0x05,0x0b,0x0d,0x2d,0x1d,0xe7,0x01,0x15,
+ 0x01,0x43,0x09,0x09,0x2c,0x0d,0x02,0xe6,0x12,0x04,0x60,0x01,0xe7,0x16,0xe5,0x1f,
+ 0x0b,0x1a,0x06,0xe5,0x0a,0x1e,0x06,0x14,0xe5,0x1f,0x01,0x14,0x0b,0x09,0x04,0x04,
+ 0x29,0xe6,0x48,0xe7,0x0a,0xe5,0x02,0x13,0x09,0x01,0x01,0xe5,0x05,0x02,0x01,0x02,
+ 0x01,0x01,0xe5,0x07,0x01,0xe5,0x05,0x12,0xe5,0x07,0xe5,0x01,0xe5,0x04,0xe5,0x07,
+ 0x20,0x01,0x04,0x09,0x1e,0xea,0x01,0x01,0x41,0x01,0x11,0xe5,0x0a,0xe5,0x14,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x03,0x01,0x05,0x02,0xe5,0x04,0x13,0x09,0x03,0x01,0x04,
+ 0x02,0x01,0x03,0x20,0xe5,0x05,0x02,0x01,0x04,0x1b,0x01,0x04,0x01,0x04,0x0f,0xe5,
+ 0x36,0x0f,0x01,0x09,0x42,0x01,0x02,0x07,0x01,0x6d,0x05,0xe7,0x01,0x11,0x45,0x02,
+ 0x01,0x07,0x43,0xe5,0x01,0x06,0x02,0x01,0x6f,0x02,0x01,0x01,0x15,0x08,0x01,0x3a,
+ 0x03,0x02,0x01,0x01,0x09,0x0f,0x09,0x09,0x0b,0x09,0x07,0x03,0xe6,0x09,0x01,0x0c,
+ 0x09,0x09,0x1d,0x09,0x1f,0xe5,0x01,0x02,0x18,0x01,0x02,0x3c,0x01,0x02,0xe5,0x01,
+ 0x04,0x01,0x01,0xe5,0x3d,0x02,0x02,0x02,0x04,0x05,0x01,0x01,0x60,0x02,0x02,0x02,
+ 0xe6,0x17,0x43,0x01,0x20,0x01,0x08,0xe5,0x11,0xe5,0x09,0xe5,0x0b,0x01,0x07,0x01,
+ 0x22,0x1a,0x02,0x06,0x02,0x01,0x1a,0xe5,0xe7,0x16,0x45,0x01,0x1f,0xe8,0x04,0xe5,
+ 0xe5,0xe5,0x03,0xe5,0x04,0x05,0x01,0x01,0x04,0xe5,0xe5,0xe6,0x01,0x06,0x01,0x07,
+ 0x01,0x0b,0xe5,0x07,0xe7,0x05,0xe5,0xe6,0x19,0x01,0xe6,0x04,0xe6,0x1d,0x01,0xe5,
+ 0x04,0x71,0x06,0x09,0x09,0x0b,0x09,0x09,0x1d,0x09,0x09,0x04,0x18,0x09,0x21,0xe8,
+ 0x1d,0x41,0x19,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x0b,0x19,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x1b,0xe5,0x07,0xe5,0x23,0xe5,0x0d,0x09,0x05,0x03,0x09,0x09,
+ 0x09,0x09,0x09,0x04,0x01,0x02,0xe5,0x07,0x02,0x01,0x01,0x02,0x09,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x06,0x02,0xe6,0x06,0xe5,0x07,0xe5,0x03,0xe5,0x01,0x02,0x06,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0x09,0x09,0xe6,0x06,0xe6,0x06,0x09,0x0d,0xe5,0xe5,0xe5,
+ 0x01,0x13,0x45,0x13,0x3d,0x06,0x02,0x72,0x02,0x02,0xe5,0x14,0x43,0x14,0x10,0x09,
+ 0x09,0x06,0x0e,0x03,0x08,0x1a,0x09,0x09,0x48,0xe6,0xe5,0x13,0x02,0x01,0x43,0x01,
+ 0x01,0x0c,0x02,0x01,0x0a,0x01,0x01,0x05,0xe6,0x06,0x01,0x09,0xe6,0x06,0xe6,0x06,
+ 0x08,0x14,0xe6,0x03,0x01,0xe7,0x06,0xe6,0x1a,0xe6,0x06,0xe6,0x14,0x09,0xe8,0x18,
+ 0x01,0x41,0x02,0xe5,0x03,0x03,0x06,0x01,0xe5,0x09,0x09,0x09,0x0b,0x09,0x0f,0x02,
+ 0x14,0x05,0x01,0xe6,0x08,0x1d,0x09,0x19,0xe5,0x02,0x02,0x02,0xe5,0x5b,0x01,0x11,
+ 0x01,0x15,0x0b,0x04,0x04,0x11,0x09,0x03,0x09,0x06,0x03,0x02,0x01,0x01,0x08,0x4b,
+ 0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe6,0x01,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x05,0xe7,0x05,0xe7,0x08,
+ 0xe6,0x02,0x02,0xe7,0x01,0x05,0xe6,0x06,0xe5,0x07,0xe5,0x05,0xe8,0xe5,0x03,0xe6,
+ 0x05,0xe7,0x07,0xe5,0x07,0xe5,0x02,0x02,0xe7,0x02,0x02,0xe7,0x07,0xe5,0x07,0xe6,
+ 0x03,0x01,0x02,0xe5,0x16,0x01,0x3c,0x06,0x01,0x09,0x07,0x01,0xe5,0x08,0xe5,0x27,
+ 0xe5,0x07,0x08,0x24,0x03,0x1d,0xe5,0x07,0xe5,0x19,0x05,0xe8,0x18,0x02,0x40,0x01,
+ 0x02,0x06,0x07,0x02,0x0b,0x09,0xe5,0x01,0x05,0xe5,0x01,0x07,0x01,0x01,0x05,0xe5,
+ 0x01,0x03,0x05,0xe5,0x17,0xe5,0x01,0x05,0x09,0xe5,0x01,0x19,0xe5,0x01,0x05,0xe5,
+ 0x01,0x14,0xe5,0x03,0xe5,0x01,0xe5,0x55,0x06,0x01,0x09,0x07,0x01,0x18,0xe5,0x07,
+ 0xe5,0x01,0x11,0xe5,0x02,0x09,0x18,0xe5,0x07,0x05,0x03,0xe5,0x1b,0xe5,0x07,0xe5,
+ 0x14,0x06,0x03,0x56,0x06,0x01,0xe5,0x07,0x07,0x01,0xe5,0x15,0x01,0xe5,0x05,0x01,
+ 0xe5,0x08,0x01,0x06,0x01,0xe6,0x01,0x03,0x01,0xe5,0x18,0x01,0xe5,0x0f,0x01,0xe5,
+ 0x19,0x01,0xe5,0x05,0x01,0xe5,0x18,0x01,0xe5,0xe7,0x19,0x44,0x48,0xe5,0x03,0x03,
+ 0x0c,0x14,0x3b,0x16,0x08,0xe5,0x0b,0x04,0xe6,0x06,0x01,0x07,0x01,0x07,0x01,0x01,
+ 0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,
+ 0x01,0x02,0x04,0x01,0x07,0x01,0xe5,0x05,0x01,0xe5,0x04,0xe5,0xe6,0x07,0x01,0x07,
+ 0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0x01,0xe5,0x03,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x02,
+ 0x04,0x01,0x0a,0xe5,0xe6,0x54,0xe5,0x05,0x18,0x07,0xe5,0x10,0xe5,0x04,0x01,0x18,
+ 0x17,0x03,0xe5,0x11,0xe5,0x03,0x17,0xe5,0x07,0xe5,0x21,0x02,0xe5,0x1d,0x35,0x0b,
+ 0x13,0xe5,0x02,0xe5,0x06,0x09,0x01,0x0e,0x02,0x02,0x27,0xe5,0x07,0x04,0x04,0x01,
+ 0x10,0x0a,0xe5,0xe5,0x05,0xe5,0x07,0x05,0x0d,0x01,0x04,0x01,0xe5,0xe5,0x52,0x0f,
+ 0x1c,0x10,0xe5,0x16,0x24,0x12,0x10,0x17,0x25,0xe5,0x2e,0x13,0x0b,0x0d,0x01,0x09,
+ 0x07,0xe6,0x1e,0x14,0x03,0x04,0x01,0x23,0xe6,0x09,0x19,0x33,0x01,0x09,0x53,0x01,
+ 0x05,0x09,0x05,0x21,0xe5,0x06,0x58,0x33,0xe7,0x08,0x08,0x28,0x0f,0xe5,0xe5,0x0d,
+ 0x01,0x13,0x09,0x0a,0x01,0x06,0xe5,0x05,0xe5,0x02,0x0c,0x03,0x16,0x10,0x05,0x09,
+ 0x0b,0x09,0x07,0x2a,0x01,0x0d,0x0f,0x2b,0x13,0x13,0x09,0x13,0x2c,0xe5,0x11,0x09,
+ 0x02,0x02,0x03,0x15,0x2e,0x04,0x03,0x03,0x0b,0x02,0x83,0x02,0x14,0x10,0x12,0x03,
+ 0x3b,0x1b,0x01,0x01,0x01,0x08,0x29,0x09,0xe5,0x07,0x01,0x07,0x09,0x0a,0xe6,0x10,
+ 0xe5,0x12,0x08,0xe5,0x02,0x01,0x03,0x28,0x01,0x0f,0x02,0x1c,0xe6,0x2c,0xe7,0x27,
+ 0x16,0x0c,0x1d,0x10,0x01,0x14,0x01,0xe5,0x02,0x1e,0x04,0x26,0x1b,0x2f,0xe6,0x0e,
+ 0x1e,0x1c,0x13,0x13,0x09,0x05,0x0d,0x0c,0xe5,0xe5,0x08,0x09,0x13,0x02,0x03,0x3b,
+ 0x22,0xe5,0xe6,0x0d,0x01,0x39,0x13,0xe5,0x03,0x08,0x04,0x09,0x13,0x10,0x2d,0x5c,
+ 0x02,0xe6,0x0c,0xe5,0x22,0x19,0x03,0x06,0x08,0xe5,0x11,0x09,0x13,0xe5,0x01,0x08,
+ 0x09,0x33,0x07,0x02,0x1a,0x2b,0x02,0xe6,0x07,0xe5,0x03,0xe6,0x17,0x02,0xe5,0x12,
+ 0xe5,0x08,0x01,0xe5,0x04,0x02,0x01,0x04,0x05,0x03,0x02,0x01,0x02,0x01,0xe5,0x07,
+ 0x09,0xe5,0x0a,0x01,0x02,0x03,0x01,0xe5,0x05,0x02,0xe5,0x04,0x16,0x01,0x04,0x07,
+ 0x0b,0x16,0x01,0x04,0x09,0x1e,0xe5,0x01,0xe6,0x01,0x01,0x08,0xe6,0x1a,0x03,0x0c,
+ 0xe5,0x10,0xe5,0x07,0xe5,0x05,0x05,0x02,0x03,0x01,0x04,0x08,0x03,0xe5,0x0b,0x05,
+ 0xe5,0x02,0x04,0xe6,0x05,0x05,0xe5,0x01,0x16,0x01,0x04,0x13,0x15,0xe5,0x05,0x02,
+ 0xe5,0x04,0x1b,0x01,0x02,0x01,0xe6,0x03,0x05,0x01,0xe5,0xe5,0xe5,0x18,0x13,0x01,
+ 0x01,0x02,0xe5,0x02,0x02,0x08,0x02,0xe5,0x02,0x02,0x04,0x04,0x01,0xe5,0x02,0x04,
+ 0x01,0x02,0x02,0x08,0x07,0x09,0x03,0x11,0x77,0x05,0x01,0xe5,0x01,0x0a,0x01,0x1b,
+ 0x10,0x02,0x01,0x04,0x04,0x0e,0x04,0x07,0x06,0x04,0x04,0x04,0x0d,0xe5,0x0d,0x13,
+ 0x7b,0x02,0xe5,0xe6,0x0c,0x01,0x04,0x01,0x14,0x11,0x06,0x02,0x03,0x02,0x01,0x01,
+ 0x05,0x02,0x03,0x02,0x01,0x01,0xe5,0x03,0x02,0x03,0x02,0x02,0x03,0x02,0x01,0x01,
+ 0x05,0x09,0xe5,0x01,0x02,0x04,0x09,0x06,0x02,0x01,0x01,0x19,0x13,0x1d,0x09,0x19,
+ 0x06,0xe7,0x01,0x0a,0x01,0x01,0x02,0x01,0x14,0x03,0x13,0x09,0x01,0x02,0x0e,0x01,
+ 0x02,0xe5,0x02,0x09,0x01,0x02,0x04,0x04,0x0e,0x02,0x01,0x02,0x03,0x0f,0x03,0x01,
+ 0x02,0x72,0x04,0x01,0xe5,0x0b,0x01,0x1b,0x13,0x01,0x01,0x07,0x01,0x02,0x01,0x04,
+ 0x02,0x04,0x01,0x02,0x01,0xe5,0x02,0x02,0x04,0x01,0x02,0x01,0x02,0x01,0x02,0xe6,
+ 0x06,0x04,0x04,0x01,0x02,0x04,0x01,0x01,0x06,0xe5,0x03,0x01,0x33,0xe5,0x19,0x09,
+ 0x02,0x01,0x1a,0xe5,0xe7,0xe6,0x09,0x01,0x1b,0x13,0x01,0x02,0x09,0x01,0x07,0x02,
+ 0x06,0x01,0x02,0x04,0xe7,0x05,0xe6,0x06,0xe6,0x05,0xe5,0xe6,0x02,0x01,0xe5,0xe5,
+ 0xe5,0xe6,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0xe6,0x03,0x01,0x01,0x18,0xe5,0x11,0xe5,
+ 0xe5,0x1a,0x09,0xe6,0x1f,0xe5,0x12,0xe5,0x2c,0x09,0x02,0xe6,0x03,0x09,0x04,0x04,
+ 0x09,0x02,0xe5,0x04,0x09,0x04,0x04,0x02,0xe5,0x06,0x04,0x04,0x09,0x1d,0x13,0x04,
+ 0x18,0x09,0x25,0x14,0x2d,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0xe5,0x05,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x1b,0xe5,0x11,0xe5,0x1b,0xe5,0x07,0xe5,0x1f,0x01,0xe7,0x0d,0x03,0xe5,0xe5,0x01,
+ 0x06,0x02,0x09,0x02,0x06,0x09,0xe6,0x01,0x01,0x02,0xe6,0x06,0xe6,0x01,0x01,0x02,
+ 0xe6,0xe5,0x04,0xe6,0x01,0x01,0x02,0xe7,0xe5,0xe5,0x01,0xe6,0xe5,0x04,0xe5,0x04,
+ 0x02,0xe5,0x04,0x01,0x02,0xe5,0x07,0xe5,0x07,0xe6,0x06,0x09,0x09,0xe5,0x07,0x09,
+ 0xe5,0x07,0x09,0x09,0xe6,0x06,0xe6,0x06,0x09,0x0d,0x03,0xe5,0x01,0x13,0x08,0xe5,
+ 0x26,0x13,0x13,0x1c,0xe5,0x07,0xe5,0x91,0x05,0xe5,0x13,0x08,0x29,0x11,0x13,0x1b,
+ 0x03,0x05,0x03,0x02,0x04,0x09,0x27,0x13,0x49,0x01,0xe5,0x16,0x08,0x02,0x1e,0xe6,
+ 0xe5,0x04,0xe6,0x03,0x01,0xe5,0xe5,0xe5,0x04,0xe6,0xe5,0x04,0x01,0x01,0x05,0xe6,
+ 0x06,0xe6,0x06,0xe6,0x06,0xe6,0xe5,0x05,0xe7,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0x14,
+ 0x05,0xe6,0x10,0xe6,0x14,0x05,0xe6,0xe5,0x04,0xe6,0x1e,0xe6,0xe5,0x01,0x0e,0x07,
+ 0x01,0x05,0x02,0x1e,0x08,0xe5,0x04,0x01,0xe6,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,
+ 0x08,0x08,0xe5,0x06,0x02,0xe5,0x08,0x09,0x1d,0x13,0x1d,0x09,0x19,0xe5,0x02,0x01,
+ 0x03,0xe5,0x0d,0x07,0x05,0x05,0x1e,0x05,0x03,0x06,0x01,0x03,0x02,0x06,0x09,0x07,
+ 0x02,0x06,0x01,0x07,0x02,0x05,0x02,0x02,0x01,0x02,0x01,0x30,0x13,0x02,0x1d,0x28,
+ 0x01,0xe6,0x0e,0x05,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe6,0xe5,0x04,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x01,0x06,0xe6,0x02,0x02,0xe7,0x02,0x03,0xe6,0x07,0xe5,0x07,0xe5,0x05,
+ 0xe7,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x02,0x02,0xe7,0x02,0x02,0xe7,0x07,
+ 0xe5,0x07,0xe6,0x03,0x01,0xe6,0xe5,0x08,0x19,0x1e,0x06,0x01,0xe5,0x08,0xe5,0x04,
+ 0x01,0xe6,0x07,0xe5,0x04,0x01,0x07,0x01,0xe5,0x08,0x08,0xe5,0x09,0xe5,0x04,0x03,
+ 0xe5,0x03,0x03,0xe5,0x03,0x1d,0x0d,0xe5,0x03,0x17,0x05,0x03,0xe5,0x03,0x15,0x05,
+ 0x01,0xe6,0x03,0x0d,0x09,0x04,0x22,0x04,0x04,0x09,0x04,0x04,0x09,0x04,0x04,0x04,
+ 0x04,0x09,0x04,0x01,0x02,0x06,0x04,0x03,0x05,0xe5,0xe6,0x04,0x03,0x19,0xe5,0xe6,
+ 0x0e,0xe5,0xe6,0x16,0x01,0xe5,0xe6,0x04,0xe5,0xe6,0x13,0xe5,0x03,0xe6,0xe7,0x0d,
+ 0x13,0x1e,0x08,0xe5,0x11,0x13,0x09,0xe5,0x08,0x09,0x07,0x02,0xe5,0x02,0x09,0xe5,
+ 0x07,0x1d,0xe5,0x11,0xe5,0x1b,0xe5,0x07,0xe5,0x14,0x06,0xe6,0xe5,0x08,0x05,0x11,
+ 0x6d,0x0b,0x06,0x08,0x27,0x13,0x1d,0x09,0x1c,0x01,0x03,0x03,0x09,0x02,0x1a,0x1e,
+ 0x01,0x0e,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x11,0x01,0x1a,0x05,0xe5,0x2f,
+ 0x0c,0x10,0x09,0x1a,0x06,0xe7,0x01,0x02,0x05,0x02,0x02,0x01,0x02,0x04,0x01,0x01,
+ 0x05,0x01,0x04,0x02,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0xe6,0x06,0x01,
+ 0x07,0xe6,0x06,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0xe6,0x08,0x01,
+ 0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,
+ 0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x0c,0x01,0x03,
+ 0x09,0x1f,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,
+ 0x03,0x03,0xe5,0x01,0x05,0xe6,0x07,0x07,0x02,0x09,0xe5,0x02,0x04,0xe5,0x1b,0xe5,
+ 0x11,0xe5,0x03,0x0a,0x0c,0xe5,0x07,0xe5,0x20,0xe5,0x01,0xe5,0x29,0x06,0x0c,0x06,
+ 0x03,0x08,0x03,0x02,0x02,0x01,0x07,0x01,0x07,0x01,0x04,0x03,0x07,0x01,0xe5,0x02,
+ 0x02,0x01,0x02,0x02,0x03,0x03,0x08,0x02,0x02,0x03,0x1d,0x10,0x02,0xe5,0x1b,0x09,
+ 0x10,0x10,0x04,0x01,0xe5,0x01,0x27,0x13,0x09,0x09,0x1f,0x04,0x01,0x07,0x11,0x01,
+ 0x03,0x07,0xe5,0x01,0x06,0x0f,0x0d,0x13,0x1d,0x09,0x1e,0x05,0xe5,0x01,0x17,0xe6,
+ 0x2e,0xe6,0x06,0xe7,0x05,0xe6,0x10,0xe6,0x06,0xe6,0x10,0xe6,0x1f,0x17,0x08,0x0a,
+ 0x50,0x01,0xe5,0x17,0x16,0x15,0x03,0x05,0x0d,0x05,0x08,0xe5,0x02,0x09,0x07,0x0b,
+ 0x04,0x04,0x05,0x32,0xe5,0x59,0x01,0x01,0x0b,0x06,0x17,0x10,0x0e,0xe5,0x06,0x0a,
+ 0xe5,0x12,0x03,0x0e,0xe5,0x02,0x0d,0x04,0x01,0x0a,0x08,0x11,0x12,0xe5,0xe5,0x1f,
+ 0x07,0x09,0x1f,0xe7,0x2f,0x0e,0x04,0x04,0x01,0x0a,0x03,0x02,0x01,0x04,0x01,0x0a,
+ 0x02,0x09,0x06,0x0d,0x01,0x09,0x03,0x1a,0x18,0x57,0xe7,0x05,0x01,0x20,0x15,0x12,
+ 0x09,0x28,0x13,0x05,0x09,0x34,0xe5,0x46,0x06,0x01,0x01,0x17,0xe5,0x2e,0x07,0x0c,
+ 0xe6,0x02,0x04,0x09,0x26,0x08,0x0d,0x08,0xe6,0x06,0xe5,0x07,0xe5,0x12,0x1c,0xe6,
+ 0x29,0x02,0x01,0xe5,0x18,0x46,0x08,0x0a,0xe5,0x08,0x0e,0x0a,0x17,0x05,0x03,0x0a,
+ 0x04,0x04,0x03,0x0f,0x1b,0x2e,0x01,0xe5,0x17,0x29,0x13,0x0d,0x04,0x04,0x04,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x08,0x06,0x09,0x10,0x07,0x09,0xe6,0x07,0x03,0x09,0x0f,
+ 0x36,0xe9,0x66,0xe5,0x01,0x06,0x09,0x09,0x0c,0x0b,0x09,0x07,0x17,0x02,0x01,0x04,
+ 0x03,0xe5,0xe5,0x19,0xe5,0x34,0x01,0x01,0xe5,0xe5,0x02,0x03,0x07,0x31,0xe5,0x0c,
+ 0x04,0x0c,0x01,0x01,0x07,0x03,0x01,0x03,0x01,0x07,0x01,0x0d,0x03,0x01,0x07,0x09,
+ 0x1f,0xe5,0x07,0x02,0x06,0x04,0x02,0x01,0x0b,0x1b,0x09,0x09,0x08,0xe9,0x25,0xe5,
+ 0x03,0xe5,0x01,0x01,0x03,0xe5,0x04,0x01,0xe6,0x04,0x06,0xe5,0xe5,0xe7,0x06,0x04,
+ 0xe5,0xe5,0xe5,0xe8,0x05,0xe5,0x05,0x11,0x01,0x0c,0xe5,0xe6,0x05,0x02,0xe5,0x04,
+ 0x01,0xe5,0x05,0x13,0x05,0x01,0x0b,0x16,0x01,0x04,0x09,0x02,0xe5,0x19,0xe6,0x01,
+ 0xe5,0x01,0x01,0x2c,0xe5,0x08,0x01,0xe5,0x08,0x06,0x01,0xe6,0x01,0x0c,0xe5,0xe5,
+ 0x01,0x03,0x01,0xe5,0x01,0x06,0xe5,0x11,0x0f,0x02,0x01,0x04,0x02,0xe5,0x04,0x15,
+ 0xe5,0x0b,0xe6,0x02,0xe5,0x1b,0xe5,0x05,0x02,0x01,0x04,0x02,0x01,0x16,0x01,0x02,
+ 0x01,0xe6,0x03,0x2a,0x09,0x05,0x03,0x05,0x09,0x01,0x03,0xe5,0x01,0x01,0x07,0x13,
+ 0x01,0x07,0x01,0x04,0xe5,0xe5,0xe5,0x02,0xe5,0x03,0x01,0x1f,0x13,0x02,0xe5,0xe5,
+ 0xe5,0x0a,0x43,0x04,0xe5,0x01,0x02,0x3c,0x09,0x09,0x09,0x01,0x07,0x05,0xe5,0x01,
+ 0x06,0xe5,0xe5,0xe5,0x06,0x01,0x04,0x02,0x01,0x04,0xe5,0x02,0x01,0x36,0x02,0x01,
+ 0x51,0x02,0x02,0xe5,0x3e,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x04,0x09,0xe5,
+ 0x01,0x02,0x03,0x02,0xe5,0xe5,0x04,0x01,0x1a,0x09,0x09,0x13,0x02,0x01,0x01,0x03,
+ 0x02,0x05,0x1d,0x09,0x18,0x06,0xe8,0x01,0x02,0x39,0x01,0x01,0x05,0x01,0x01,0x05,
+ 0x03,0x02,0x01,0xe5,0xe5,0xe5,0x04,0x03,0x09,0x05,0x03,0x02,0x01,0xe5,0xe5,0xe5,
+ 0x04,0x03,0x0b,0x37,0x03,0x02,0x01,0x4a,0x03,0x01,0xe6,0x2e,0x0a,0xe5,0x01,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x09,0x09,0x01,0x07,0x01,0x07,0x01,0x09,0x01,
+ 0x0d,0xe5,0x05,0x0a,0x18,0x01,0x29,0x09,0x02,0x01,0x11,0x08,0x02,0x01,0x3c,0x01,
+ 0xe5,0xe5,0x06,0x01,0x07,0x09,0x01,0x07,0x03,0xe5,0xe5,0xe6,0x02,0xe5,0x03,0x01,
+ 0x07,0x01,0x07,0x01,0x08,0xe5,0xe5,0x0a,0xe5,0xe5,0xe5,0x04,0x08,0xe5,0x11,0xe5,
+ 0x03,0x01,0x0b,0xe5,0x1c,0x09,0xe6,0x12,0xe6,0x06,0xe5,0xe6,0x69,0x09,0x33,0x09,
+ 0x09,0x13,0x13,0x1d,0x09,0x22,0x01,0xe5,0x01,0x67,0xe5,0x07,0xe5,0x01,0x2f,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x11,0xe5,0x11,0xe5,0x1b,0xe5,0x07,0xe5,0x1f,0xe5,0x01,0xe5,
+ 0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0xe5,0x04,0x02,0xe5,0x03,0x03,
+ 0x04,0x01,0x02,0x09,0x08,0x02,0x02,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x07,0x09,0xe5,
+ 0x07,0x09,0xe5,0x07,0x09,0x09,0xe6,0x06,0xe6,0x06,0x09,0x0d,0xe5,0xe7,0x01,0x3b,
+ 0x09,0x09,0x09,0x12,0xe5,0x12,0x1f,0x86,0x02,0xe5,0x01,0x3d,0x09,0x08,0x0a,0x0f,
+ 0x03,0x05,0x0d,0x16,0x06,0x07,0x13,0x13,0x13,0x48,0xe5,0xe6,0x07,0x36,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x09,0xe7,0x05,0xe5,0xe5,0x03,0x01,0x09,0x07,0x01,0x09,
+ 0x01,0x04,0x04,0xe7,0x06,0xe6,0x06,0xe6,0x0a,0x04,0xe5,0xe5,0x03,0x01,0x04,0x05,
+ 0xe6,0x0f,0x04,0x05,0xe6,0xe5,0x04,0xe6,0x1f,0xe7,0x3e,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x07,0x01,0xe5,0x05,0x02,0xe5,0x08,0x09,0x11,0xe6,0x04,
+ 0x02,0x0a,0x11,0xe5,0x09,0x09,0x19,0xe5,0x02,0x01,0xe6,0xe6,0x3d,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0x09,0x04,0x0c,0x01,0x09,0x07,0x01,0x08,0xe5,0xe5,0x08,
+ 0x14,0x12,0x07,0x01,0x0a,0x12,0x22,0x13,0x01,0x01,0xe5,0x13,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x05,0xe8,0xe5,0x02,0xe8,0xe5,0x02,0xe8,0xe5,0x02,0xe8,0xe5,0x02,
+ 0xe7,0x01,0xe5,0x01,0xe8,0x04,0x02,0xe5,0xe5,0x02,0xe5,0xe6,0xe5,0x02,0xe5,0xe6,
+ 0xe5,0x02,0xe7,0x01,0x01,0x04,0xe7,0x01,0x02,0xe7,0x02,0x03,0xe6,0x05,0x01,0xe5,
+ 0x07,0xe5,0x01,0x03,0xe8,0x06,0xe5,0x05,0xe7,0x07,0xe5,0x01,0x05,0xe5,0x02,0x02,
+ 0xe7,0x02,0x02,0xe7,0x05,0x01,0xe5,0x06,0xe7,0xe5,0x01,0x03,0x01,0x1a,0x1d,0xe5,
+ 0x06,0x03,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x03,0xe5,0x01,0xe5,0x03,0xe6,0x01,
+ 0x0e,0x03,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x0c,0x02,0xe6,0x03,0x03,0x05,0x03,
+ 0x09,0x08,0xe5,0x04,0x02,0x0a,0x05,0x0c,0x0a,0x05,0x03,0xe5,0x03,0x0d,0xe5,0x03,
+ 0x01,0x08,0xe5,0x19,0x21,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0x02,
+ 0x02,0x03,0x05,0x03,0x02,0x06,0xe5,0xe5,0x05,0x02,0x06,0x0b,0xe5,0x03,0xe5,0xe6,
+ 0x02,0x01,0x03,0x05,0xe5,0xe5,0x03,0x08,0xe5,0xe6,0xe6,0x0e,0xe5,0xe6,0x0b,0x0a,
+ 0x01,0xe5,0xe6,0x04,0xe5,0xe6,0x07,0x0b,0xe5,0x03,0x01,0xe7,0x3a,0x01,0x03,0x05,
+ 0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x03,0x01,0x07,0x01,0xe5,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x01,0x05,0x02,0x07,0x04,0x04,0xe5,0x07,0x05,0x12,0x04,0xe5,0x02,0x0a,
+ 0x03,0xe5,0x0c,0x0e,0xe5,0x07,0xe5,0x06,0x0a,0x02,0x07,0x02,0x1a,0x1d,0x03,0xe7,
+ 0x05,0xe7,0x04,0x01,0xe6,0x01,0x02,0x01,0xe6,0x01,0x03,0xe6,0x01,0x03,0x01,0xe5,
+ 0x05,0xe5,0x03,0x03,0x03,0x01,0x03,0x05,0x03,0x01,0xe5,0x08,0x02,0x05,0x13,0x06,
+ 0x08,0x03,0x13,0x0f,0x0d,0x09,0x06,0x02,0x06,0x03,0x04,0x02,0x01,0x01,0xe7,0x3d,
+ 0x02,0x10,0x02,0x10,0x09,0x02,0x0e,0x0b,0x02,0x10,0x19,0x19,0x02,0x1e,0x13,0x1a,
+ 0x05,0x02,0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0x01,
+ 0x02,0x02,0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x07,0x01,0x04,0x02,
+ 0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x04,0x02,0x01,0x09,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,0x05,0xe5,0x02,0xe6,
+ 0xe5,0x3e,0x07,0x0b,0x02,0x0a,0x03,0x02,0x04,0x03,0x02,0x05,0x14,0x08,0x01,0x03,
+ 0x08,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x0d,0x03,0xe5,0x04,0xe5,0x0a,0xe5,0x03,0x17,
+ 0xe5,0x07,0xe5,0x22,0xe7,0x0a,0x13,0x08,0x14,0x06,0x09,0x03,0x04,0xe5,0x0b,0x09,
+ 0xe5,0x07,0x11,0x09,0x05,0x02,0x07,0x01,0x02,0x04,0x08,0xe5,0x0e,0x02,0x06,0x0c,
+ 0x11,0x0c,0x09,0x1a,0x06,0x01,0xe5,0xe5,0x42,0x13,0x09,0x0a,0x26,0xe5,0x04,0x05,
+ 0x04,0x09,0x11,0x0c,0x03,0x0f,0x1c,0x09,0x11,0x0d,0xe5,0x02,0xe8,0x24,0x1b,0x07,
+ 0x02,0x06,0x01,0x07,0x01,0x0a,0x0a,0x05,0x01,0x0a,0x06,0x01,0xe5,0x02,0x06,0x06,
+ 0x27,0x07,0x01,0xe5,0xe6,0x02,0xe5,0x03,0x01,0x02,0x44,0xe6,0xe5,0x3a,0xe5,0x01,
+ 0x0b,0x0a,0x03,0x05,0x03,0xe5,0x10,0x01,0x04,0xe5,0x11,0x04,0x01,0x01,0x0d,0x0b,
+ 0x23,0x21,0x36,0x13,0x09,0x23,0x0d,0x03,0x01,0x05,0x01,0x01,0x02,0x06,0x05,0x08,
+ 0x02,0x01,0x0d,0xe5,0x01,0x01,0x07,0x04,0x09,0x01,0x1c,0x03,0x0b,0x01,0x01,0x01,
+ 0x04,0xe5,0x36,0x06,0x0c,0x02,0x02,0x0d,0x15,0x13,0xe5,0x02,0x13,0x04,0x04,0x09,
+ 0x02,0xe5,0x0d,0xe5,0x11,0xe5,0x09,0x23,0x01,0x08,0x0d,0x09,0x04,0x4b,0x03,0x21,
+ 0x3f,0x05,0x2d,0x3b,0x0b,0x38,0x16,0xe5,0x05,0x38,0xe5,0x11,0xe5,0x07,0xe6,0x02,
+ 0x03,0xe6,0x02,0x07,0x02,0x01,0x01,0x01,0x06,0xe6,0x03,0x03,0x08,0x16,0x07,0x14,
+ 0x01,0x01,0x05,0x01,0x01,0x03,0x02,0x16,0x19,0xe6,0x18,0x01,0xe5,0x3e,0xe5,0x11,
+ 0xe5,0x0a,0x09,0x13,0x05,0x03,0x09,0x06,0x08,0x0e,0x32,0x21,0x0e,0x14,0x05,0xe6,
+ 0x01,0xe5,0x10,0x12,0x09,0x09,0x04,0x04,0x0b,0x02,0x04,0x04,0x04,0x01,0x02,0x13,
+ 0x10,0x02,0x0f,0x09,0xe5,0x04,0x03,0x0a,0x0f,0x07,0xe5,0x09,0xe5,0x07,0x09,0x16,
+ 0x12,0x0b,0x01,0xe6,0x01,0x3d,0x13,0xe5,0x03,0x03,0x09,0x0c,0x06,0x06,0x0c,0x02,
+ 0x01,0x09,0x09,0x07,0x26,0x01,0xe5,0x32,0x1c,0xe7,0xe5,0x1a,0x0c,0x19,0x05,0x0d,
+ 0x03,0x05,0x09,0xe5,0x0b,0x05,0x13,0x01,0x0f,0x0e,0x13,0x12,0x0d,0x2e,0x0f,0x06,
+ 0xe6,0xe7,0x17,0xe6,0xe5,0xe5,0x02,0xe5,0x0b,0xe5,0x05,0x01,0xe5,0x04,0x09,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0x08,0xe5,0x01,0xe5,0xe5,0x02,0x09,0xe5,0x03,0x03,0xe5,
+ 0x07,0xe5,0xe5,0xe5,0x04,0xe5,0xe6,0x05,0x09,0x01,0xe5,0x04,0xe5,0x01,0x01,0xe5,
+ 0x01,0xe5,0x08,0xe5,0x03,0x03,0x09,0xe5,0x10,0xe5,0x01,0x01,0x04,0x02,0xe5,0x04,
+ 0x1e,0xe5,0xe6,0xe5,0x01,0x01,0x01,0x0d,0xe5,0x06,0xe5,0x1c,0xe5,0x01,0x01,0x03,
+ 0xe5,0x07,0xe5,0x01,0x01,0x06,0x03,0x09,0xe5,0xe5,0xe6,0x02,0x05,0x02,0x06,0x03,
+ 0x05,0x02,0x03,0xe5,0x09,0x01,0x04,0x09,0x01,0xe5,0x08,0x01,0xe5,0x0c,0x05,0xe5,
+ 0x0b,0x0c,0x01,0x06,0xe5,0x01,0xe5,0x01,0x09,0x1b,0x01,0x02,0x02,0xe5,0x03,0x01,
+ 0x14,0x02,0x01,0xe5,0xe5,0xe5,0x1a,0x0b,0x07,0x04,0xe5,0x06,0xe5,0x0b,0x13,0x19,
+ 0x1d,0x05,0x03,0xe5,0xe5,0xe6,0xe5,0x03,0x01,0xe5,0xe5,0xe5,0x1c,0x07,0x04,0x01,
+ 0xe5,0xe5,0x1c,0x06,0xe6,0x01,0x1a,0xe5,0x01,0x01,0x17,0xe5,0x11,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x0b,0x06,0xe5,0xe5,0x08,0x05,0xe5,0x01,0x33,0x06,0x02,0x01,0x07,
+ 0x01,0x25,0x09,0x01,0x1f,0x03,0xe7,0x39,0x09,0xe5,0x01,0x05,0x09,0xe5,0x01,0x05,
+ 0x01,0x01,0x07,0x01,0xe5,0x03,0x09,0xe5,0x01,0xe5,0x03,0x09,0xe5,0x01,0x11,0x09,
+ 0x0e,0x07,0x06,0x04,0x01,0x02,0x01,0x01,0xe5,0xe5,0x01,0x1a,0x02,0x09,0x22,0xe5,
+ 0x01,0x02,0x1f,0x1d,0x02,0x01,0x0e,0x09,0x04,0x04,0x02,0x01,0xe5,0x02,0x09,0x05,
+ 0x03,0x09,0x2f,0x03,0x09,0x05,0x01,0x01,0x01,0x02,0xe5,0xe5,0xe5,0x18,0x03,0x04,
+ 0x04,0x1d,0x04,0x01,0xe5,0x1f,0x01,0x0e,0x0e,0x0e,0x04,0x07,0x04,0x02,0x0b,0x06,
+ 0x02,0x06,0x01,0xe5,0x05,0x02,0x10,0x01,0x01,0x05,0xe6,0x05,0x0f,0x09,0x01,0x04,
+ 0x01,0xe5,0xe5,0x06,0x01,0x03,0xe5,0x17,0x01,0xe5,0xe8,0xe5,0xe5,0x01,0x01,0x1a,
+ 0x01,0x02,0x21,0x01,0x0e,0xe5,0x04,0xe7,0x03,0x01,0xe5,0x07,0xe5,0xe7,0x01,0x01,
+ 0xe5,0x03,0x03,0xe5,0x05,0x07,0x03,0xe5,0x01,0x01,0x03,0xe5,0xe5,0xe6,0x02,0xe5,
+ 0xe8,0x02,0xe5,0xe5,0xe5,0x08,0x06,0xe5,0xe5,0xe5,0x04,0x0e,0x09,0x01,0x01,0xe5,
+ 0xe5,0xe6,0xe5,0xe6,0x03,0x01,0x01,0xe5,0xe5,0x15,0x04,0xe6,0x01,0x01,0x02,0xe6,
+ 0x1f,0xe5,0x30,0x01,0xe5,0x02,0x09,0x09,0x09,0x09,0x02,0x02,0x0d,0x09,0x09,0x09,
+ 0x10,0x04,0x09,0x02,0xe5,0x18,0x09,0x09,0x04,0x18,0x09,0x21,0x03,0x02,0x35,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x0b,0xe5,0x03,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x01,0x11,0xe5,0x07,0xe5,0x1b,0xe5,0x07,0xe5,0x07,0xe5,0x1b,0xe5,
+ 0x07,0xe5,0x1f,0xe6,0xe6,0x0d,0x09,0x09,0x09,0x09,0xe5,0x04,0x02,0xe5,0x07,0xe5,
+ 0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x02,0x01,0x02,0x09,0xe5,0x04,0x02,0xe5,0xe5,
+ 0xe5,0xe5,0x01,0xe5,0xe5,0x02,0x02,0xe5,0x03,0x05,0x06,0x02,0xe5,0x07,0xe6,0x06,
+ 0x09,0x09,0xe5,0xe5,0x05,0xe5,0x07,0xe5,0xe5,0x05,0x09,0x09,0xe7,0x05,0xe7,0x05,
+ 0x09,0x0d,0xe5,0xe7,0x01,0x31,0x08,0xe5,0x11,0xe5,0x07,0xe5,0x08,0x12,0xe5,0x08,
+ 0x08,0xe5,0x11,0x02,0x31,0x54,0x02,0xe6,0xe5,0x32,0x05,0x03,0x05,0x09,0x03,0x05,
+ 0x03,0x05,0x03,0x0f,0x03,0x05,0x01,0x07,0x03,0x05,0x0d,0x07,0x27,0x03,0x05,0x09,
+ 0x48,0xe5,0xe6,0xe5,0x28,0x01,0x09,0xe5,0xe5,0x06,0x01,0x04,0x01,0xe7,0x06,0x01,
+ 0x03,0x02,0xe7,0x03,0x01,0x0a,0xe6,0x02,0x02,0xe7,0x05,0xe7,0x02,0x02,0xe7,0xe5,
+ 0x02,0x07,0x04,0xe7,0xe5,0x01,0x01,0xe7,0x1a,0xe6,0xe5,0x03,0xe7,0xe5,0xe6,0xe8,
+ 0x1a,0xe6,0x06,0xe6,0x1e,0xe5,0x01,0x2b,0x01,0xe5,0x05,0x02,0xe5,0x07,0xe5,0x04,
+ 0x01,0xe6,0x03,0x03,0xe5,0x04,0x01,0xe6,0x04,0x01,0xe5,0x09,0x05,0x01,0xe6,0x03,
+ 0xe5,0x01,0xe5,0x04,0x01,0xe6,0x10,0x02,0xe5,0x04,0x01,0xe6,0x0b,0x09,0x06,0x07,
+ 0xe6,0x04,0x01,0xe6,0x1c,0x09,0x19,0xe5,0x02,0x02,0xe7,0x27,0x0e,0x04,0x01,0x06,
+ 0x03,0x01,0x01,0x02,0x09,0x0c,0x01,0x0b,0x01,0xe5,0x05,0x07,0xe5,0x02,0x06,0x13,
+ 0x0b,0x0c,0x08,0x06,0x08,0xe5,0x05,0x01,0xe5,0x20,0x09,0x1e,0x01,0xe5,0x14,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x01,
+ 0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe5,0xe5,0x06,0xe7,
+ 0x01,0x02,0xe7,0x06,0xe6,0x07,0xe5,0x07,0xe5,0x05,0xe7,0x01,0x05,0xe6,0xe5,0x02,
+ 0xe7,0x07,0xe5,0x06,0xe6,0x02,0x02,0xe7,0x02,0x02,0xe7,0x07,0xe5,0x07,0xe7,0x02,
+ 0x04,0xe5,0x2a,0x01,0xe6,0x06,0x09,0x0a,0x08,0x0a,0x06,0x01,0xe5,0x12,0x08,0xe6,
+ 0x07,0x0b,0xe5,0x06,0xe6,0x04,0x01,0xe5,0x08,0x09,0x09,0xe5,0x06,0xe5,0x08,0xe5,
+ 0x17,0x03,0xe5,0x07,0xe5,0x07,0x17,0x01,0x01,0x2b,0x01,0x07,0x09,0x01,0x11,0x01,
+ 0x0a,0x06,0x01,0xe5,0x19,0x14,0x09,0xe5,0x04,0x02,0xe5,0xe6,0x04,0x1a,0x02,0xe5,
+ 0x0e,0x02,0x1a,0x02,0x06,0x02,0x03,0x10,0xe5,0x03,0xe5,0x01,0xe5,0x36,0x14,0x1a,
+ 0x01,0x14,0x08,0x0a,0x0f,0x04,0x04,0xe5,0x07,0x05,0x09,0x0d,0xe5,0x02,0xe5,0x0c,
+ 0xe5,0x11,0x09,0xe5,0x07,0xe5,0x14,0x08,0x01,0x2e,0x06,0x04,0x04,0x04,0x09,0x04,
+ 0x04,0x09,0x04,0x02,0x0b,0x09,0x04,0x04,0x09,0x09,0x03,0x01,0xe5,0x03,0xe5,0xe6,
+ 0x04,0x03,0x03,0x09,0x0b,0xe5,0xe7,0x03,0x09,0xe5,0xe6,0x10,0x07,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x02,0x11,0x03,0x03,0x01,0x1b,0x09,0x17,0x01,0xe5,0xe5,0x0f,0x02,0x06,
+ 0x02,0x06,0x02,0x06,0x01,0xe5,0xe5,0x03,0x02,0x06,0x01,0xe5,0x05,0x02,0x01,0x05,
+ 0x28,0xe5,0xe5,0x0f,0x02,0x17,0xe5,0x08,0x30,0x03,0x01,0xe5,0x01,0x0b,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x01,0x01,0x05,
+ 0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0xe5,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,
+ 0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x09,0x01,0xe6,0x04,0x01,0xe5,
+ 0x05,0x01,0xe6,0x04,0x01,0x03,0x03,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x01,0x05,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0x01,
+ 0x01,0x0b,0x23,0x07,0x09,0xe5,0x07,0xe5,0x03,0x01,0xe7,0x05,0x01,0x07,0x01,0x01,
+ 0x01,0x05,0x07,0x01,0xe5,0x07,0x07,0x01,0xe5,0x13,0xe5,0x07,0xe5,0x08,0xe5,0x01,
+ 0x04,0xe5,0x07,0xe5,0x05,0x01,0x09,0xe5,0x1b,0xe5,0x07,0xe5,0x02,0x1d,0xe5,0xe7,
+ 0x09,0x1e,0x04,0x01,0x01,0x03,0x01,0x01,0x02,0x01,0xe5,0x02,0x02,0x01,0x04,0x02,
+ 0x01,0x07,0x02,0x06,0x04,0x01,0x09,0x02,0x03,0x02,0x02,0x04,0x01,0x02,0x02,0xe5,
+ 0x01,0xe5,0x09,0x0b,0x07,0x03,0x06,0x02,0x01,0x04,0x03,0x0a,0x01,0x0c,0x1b,0x01,
+ 0x15,0x10,0x03,0xe5,0x14,0x0a,0x09,0x06,0x02,0x04,0x11,0x08,0x10,0x02,0x02,0x01,
+ 0x05,0x07,0x01,0x09,0x07,0x11,0x03,0x01,0x07,0x01,0x14,0x03,0x03,0x12,0x01,0x1b,
+ 0x01,0x07,0x01,0x20,0x01,0x01,0xe6,0x0f,0x04,0x04,0x14,0x08,0x08,0x07,0x01,0x09,
+ 0x0e,0xe5,0xe5,0xe5,0x0f,0x07,0x14,0x26,0xe5,0x05,0x10,0xe5,0xe5,0x05,0x02,0x09,
+ 0x3f,0xe5,0xe6,0x30,0x07,0x06,0x06,0x01,0x01,0x04,0xe5,0x06,0x0f,0x23,0x07,0x02,
+ 0xe6,0x19,0x0a,0x22,0x4a,0x03,0x18,0xe5,0x08,0x13,0x03,0x05,0x03,0x05,0x07,0x01,
+ 0x09,0x07,0x01,0xe5,0x03,0x03,0x05,0x03,0x02,0x06,0x09,0x06,0xe5,0x01,0xe5,0x02,
+ 0x05,0xe5,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x01,0x0d,0x03,
+ 0x12,0x37,0x0b,0x05,0xe5,0x08,0x04,0xe5,0x03,0x0e,0x01,0x03,0x03,0x09,0x01,0x01,
+ 0x05,0x03,0x01,0x03,0x01,0x07,0x09,0x09,0x09,0x09,0x08,0x01,0x0a,0x08,0x01,0x03,
+ 0x07,0x05,0xe5,0x08,0x10,0x01,0xe7,0x0a,0x11,0x13,0x0f,0x07,0xe6,0xe5,0x02,0x10,
+ 0xe5,0x0a,0x06,0x30,0x3c,0x02,0x01,0x18,0x09,0x06,0x0b,0x3e,0x1d,0x01,0x01,0x13,
+ 0x22,0x07,0xe5,0x09,0x02,0xe5,0x03,0x0a,0x08,0x13,0xe5,0x11,0xe5,0x07,0xe5,0x09,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x03,0x0b,0xe9,0x04,0xe6,0x07,0xe6,0x06,0xe5,0x1b,0xe5,
+ 0x0f,0x08,0x02,0x06,0x02,0xe5,0x02,0x18,0x19,0x08,0x0a,0x08,0x0a,0x06,0x01,0x11,
+ 0x01,0xe5,0x06,0x0a,0xe5,0x07,0x0b,0xe5,0x01,0x05,0x01,0x01,0x05,0x01,0x14,0x06,
+ 0x02,0x07,0x0a,0x1b,0x01,0x1f,0x03,0x01,0xe5,0x20,0x01,0x01,0xe5,0x0f,0x03,0x05,
+ 0x09,0x04,0x04,0x06,0x02,0x03,0x05,0x05,0x03,0x03,0x05,0x09,0x06,0x02,0x0b,0x03,
+ 0x05,0x03,0x05,0x07,0x01,0x07,0x01,0x01,0x07,0x09,0x03,0xe5,0x07,0x04,0x0e,0x34,
+ 0xe7,0x17,0x09,0x10,0x01,0xe6,0x06,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x09,0x09,0xe5,0x08,
+ 0xe5,0x07,0x06,0x02,0x01,0xe5,0x05,0x09,0x28,0x2a,0xe5,0x01,0xe5,0x18,0x09,0x0c,
+ 0x05,0x09,0x09,0x02,0x06,0x09,0x05,0x03,0x02,0x06,0x03,0x05,0x09,0x02,0x06,0x07,
+ 0x01,0x0b,0x08,0xe5,0x08,0x0a,0x07,0xe5,0x07,0x01,0x0e,0x30,0x14,0xe6,0xe7,0x0a,
+ 0x09,0x09,0x0c,0xe5,0x01,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0xe5,0xe5,0x02,
+ 0x02,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x02,0x05,0x03,0x02,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x02,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x01,0xe5,0x03,0x03,0x02,0xe5,0xe5,0x02,
+ 0x05,0x03,0x02,0xe5,0xe5,0x02,0xe5,0xe5,0xe6,0x02,0xe5,0x07,0x0b,0xe5,0x05,0x19,
+ 0x0c,0xe5,0x1d,0xea,0x01,0x01,0x08,0x04,0x04,0xe6,0x06,0xe6,0x0a,0x02,0xe5,0x02,
+ 0xe5,0x02,0xe5,0x02,0xe5,0x01,0xe5,0x03,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0x07,0xe5,
+ 0x02,0x01,0x02,0xe5,0x07,0x02,0x06,0xe5,0x07,0x09,0xe5,0xe5,0x07,0x09,0xe5,0x07,
+ 0xe5,0x02,0xe5,0x02,0xe5,0x02,0x01,0x02,0x04,0xe5,0x01,0xe5,0x0d,0x01,0x1e,0x0c,
+ 0x1c,0x01,0x02,0xe8,0x03,0x08,0x06,0xe5,0xe5,0xe5,0x03,0x01,0x02,0x04,0xe5,0xe5,
+ 0xe5,0x03,0x04,0x04,0x04,0x02,0x01,0x04,0x04,0x04,0x02,0x01,0x04,0x02,0x01,0x04,
+ 0x04,0x04,0x04,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x04,0x06,0x01,0xe5,0xe5,0x03,
+ 0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x01,0x02,0x02,0x03,0xe5,0x11,0x19,
+ 0x29,0x06,0xe6,0x01,0x0a,0x06,0x02,0x01,0x07,0x06,0xe5,0xe5,0xe5,0x03,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x02,0x06,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x30,0x2b,0x04,
+ 0xe6,0x0c,0x07,0x01,0x01,0x02,0x04,0x01,0x03,0x02,0x0c,0x02,0x01,0x01,0x02,0x02,
+ 0xe5,0x01,0x02,0x02,0x03,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,
+ 0x01,0x02,0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0xe5,0x01,0x04,0x02,0x06,0x02,
+ 0x06,0x02,0x06,0x02,0x06,0x02,0x04,0x04,0x0e,0x01,0x02,0x18,0x30,0x01,0x02,0x0a,
+ 0x03,0x05,0x01,0x02,0x04,0x01,0x01,0x02,0x01,0x04,0x05,0x03,0x02,0x01,0xe5,0x02,
+ 0x05,0x03,0x01,0x01,0xe6,0x02,0x04,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,
+ 0x02,0x05,0x03,0x01,0x02,0xe5,0x02,0x01,0x01,0xe6,0x02,0x07,0x03,0x01,0x02,0xe5,
+ 0x02,0x05,0x03,0x02,0x01,0xe5,0x02,0x01,0x02,0xe5,0x02,0x05,0x03,0x0f,0x01,0x01,
+ 0x19,0x03,0x27,0x04,0x01,0xe5,0x03,0xe5,0x05,0x0b,0x04,0x02,0x01,0x07,0x01,0x07,
+ 0x03,0x05,0x03,0x05,0x09,0x07,0x01,0x03,0x05,0x03,0x05,0x03,0x02,0x02,0x09,0x06,
+ 0x02,0x0b,0x06,0x02,0x09,0x04,0x01,0x02,0x09,0x06,0x04,0x01,0x0f,0x01,0x02,0x01,
+ 0x16,0x2d,0x02,0xe6,0x01,0x03,0x06,0x0b,0x04,0xe5,0xe5,0xe5,0x06,0x01,0x09,0x02,
+ 0x06,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x02,0xe6,0x03,0x02,0x06,0x02,0x01,
+ 0xe5,0x02,0x01,0xe5,0x05,0x01,0xe5,0xe6,0x02,0x01,0xe5,0x07,0x01,0xe5,0xe7,0x01,
+ 0x01,0xe5,0x05,0x01,0xe5,0xe7,0x01,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0x02,0x0e,
+ 0x01,0x01,0xe5,0xe6,0x14,0x2b,0x04,0x01,0x01,0x1d,0x15,0x02,0x02,0x02,0xe5,0x01,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x01,0x01,0x02,0x02,0x05,0x02,0x02,0x03,0x02,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x10,0x04,0x42,0x05,
+ 0x01,0x1c,0x19,0xe5,0x01,0x05,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x06,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x0e,0xe5,0x47,0xe5,0x01,0xe5,0x0d,0x04,0x01,0x02,0x05,0x03,0x02,0x06,
+ 0x04,0x01,0xe5,0xe7,0xe5,0x02,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe6,0x06,0x09,0xe5,0x07,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x02,0x13,
+ 0x1d,0xe5,0x08,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,
+ 0x09,0x5d,0x02,0x02,0xe5,0x12,0x1d,0x03,0x09,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x06,
+ 0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0x14,0x4a,0xe6,0x16,0x01,0x07,0x15,0xe5,0xe5,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,
+ 0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,
+ 0x01,0x04,0x02,0xe6,0x05,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0x01,0x04,0x02,0xe6,
+ 0x03,0x02,0x01,0x01,0x01,0xe5,0x01,0xe6,0x02,0x02,0x0a,0xe6,0x44,0x01,0x01,0xe6,
+ 0x16,0x02,0xe5,0x04,0x03,0x0f,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x03,
+ 0xe5,0x01,0xe5,0x04,0x02,0xe5,0x06,0xe5,0x02,0x06,0x48,0xe9,0x15,0x01,0x07,0x0f,
+ 0x0f,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x01,0x07,0x04,0x01,0x02,0x09,
+ 0x09,0x09,0xe5,0x07,0x0b,0x02,0x45,0x01,0xe6,0x08,0x0b,0xe6,0x05,0xe7,0x06,0xe5,
+ 0x07,0xe5,0x05,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,
+ 0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,
+ 0x01,0x03,0xe7,0x01,0xe5,0x01,0xe7,0x03,0x04,0xe6,0x01,0xe5,0x01,0xe7,0x01,0x03,
+ 0xe7,0x01,0xe5,0x03,0xe5,0x01,0x05,0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x05,
+ 0xe7,0x07,0xe5,0x07,0xe5,0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x07,0x02,0x1a,
+ 0xe5,0x03,0x03,0x10,0x01,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0x09,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,
+ 0x06,0xe5,0x07,0xe5,0x08,0x03,0x05,0x16,0x29,0x01,0xe5,0x1d,0x16,0x01,0x03,0x02,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x01,0x02,0x06,0x02,0x03,
+ 0x02,0x02,0x05,0xe5,0x01,0x09,0x09,0x06,0x02,0xe5,0x03,0x04,0x05,0x03,0x19,0x09,
+ 0x1d,0x01,0x17,0x01,0x0a,0x10,0x06,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x03,0xe5,
+ 0xe5,0x01,0x03,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x03,0xe5,0xe5,
+ 0x01,0x03,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x03,0xe5,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0xe5,0xe5,0x04,0xe5,0x01,0x02,0x06,0x09,0x02,0x02,0x01,0x03,0x0d,0x01,0x1c,0xe5,
+ 0x06,0xe6,0x1b,0x01,0x01,0x17,0x02,0x01,0x01,0x05,0x01,0x10,0x02,0xe5,0xe7,0x03,
+ 0xe5,0xe7,0x03,0xe5,0xe7,0x03,0xe5,0xe7,0x03,0xe5,0xe7,0x03,0xe5,0xe7,0x03,0xe5,
+ 0xe7,0x03,0xe5,0xe7,0x03,0xe5,0xe7,0x03,0xe5,0xe6,0x01,0x04,0x03,0xe5,0x03,0xe5,
+ 0xe7,0x03,0xe6,0xe6,0x03,0x04,0x04,0x04,0x04,0xe8,0x01,0xe5,0x01,0x08,0xe5,0xe6,
+ 0x02,0x17,0xe6,0x05,0x01,0xe5,0x1c,0x01,0x0d,0x09,0xe5,0xe5,0x0a,0x1c,0x0a,0x08,
+ 0x27,0x1a,0x04,0x2d,0x04,0x08,0x03,0x1f,0xe5,0xe5,0xe5,0x07,0x1c,0x06,0xe5,0xe5,
+ 0x07,0x03,0x02,0x01,0x03,0x03,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x01,0x05,
+ 0x01,0x07,0x01,0x07,0xe6,0x06,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x01,0x05,0xe6,
+ 0x01,0x04,0x01,0x07,0x01,0x09,0xe6,0x01,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x02,0x02,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,
+ 0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x08,0x03,0xe6,0x22,0x01,
+ 0x02,0x04,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0x07,0xe5,0x01,0x05,0x09,0xe5,0x0b,0xe5,
+ 0x03,0x03,0x02,0x02,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x09,0xe5,0x07,
+ 0xe5,0x01,0x02,0x03,0x05,0x02,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x02,0x2b,0x2f,0x01,
+ 0xe5,0x0a,0x08,0xe5,0x03,0x0e,0xe5,0xe5,0x07,0xe5,0x01,0xe5,0x02,0x03,0x01,0x05,
+ 0x01,0x02,0xe5,0xe5,0x02,0x04,0x09,0x04,0x06,0xe5,0x03,0x02,0x03,0x06,0xe5,0x03,
+ 0x03,0x02,0x04,0x02,0x03,0x06,0xe5,0xe5,0x04,0x02,0x07,0xe5,0x02,0x02,0x02,0x03,
+ 0x03,0x0f,0x08,0xe5,0x01,0x06,0x01,0x07,0x0c,0x07,0x15,0x06,0x04,0x02,0x1f,0x0c,
+ 0xe5,0x02,0x0c,0x03,0x0a,0x04,0x02,0x0f,0x03,0x10,0x13,0x05,0x05,0x02,0x11,0x03,
+ 0x07,0x03,0xe5,0x0a,0xe5,0x5d,0xe5,0xe5,0x16,0x09,0x01,0x03,0x01,0x0b,0x01,0x05,
+ 0x01,0x01,0x07,0x01,0x16,0x04,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,
+ 0x07,0x09,0x01,0x01,0x09,0x07,0x02,0x03,0x02,0x01,0xe5,0x01,0xe5,0xe6,0xe5,0x5d,
+ 0xe5,0x01,0x02,0x11,0x05,0x08,0x13,0x07,0x01,0x05,0x03,0x05,0xe5,0x05,0x02,0x0d,
+ 0xe5,0xe5,0x02,0x01,0x05,0x01,0x01,0x09,0x05,0x01,0x01,0x06,0xe6,0x09,0x01,0x07,
+ 0x0c,0x07,0x01,0x09,0x0e,0x51,0xe5,0x0f,0x01,0x03,0x02,0x02,0x04,0x01,0x11,0x05,
+ 0x0d,0xe6,0x02,0x04,0xe5,0x03,0x08,0xe5,0x01,0x01,0x05,0x06,0x05,0xe5,0x02,0x03,
+ 0x03,0x01,0x04,0xe5,0x02,0x03,0x02,0xe5,0x0c,0x05,0x05,0x07,0x06,0x06,0x01,0x02,
+ 0x0a,0x05,0x03,0x09,0x08,0x06,0x09,0x14,0x0d,0xe8,0x16,0xe5,0x05,0x06,0x14,0x03,
+ 0x04,0x04,0x09,0x01,0x02,0x04,0x01,0x07,0xe5,0x05,0x01,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x08,0xe5,0xe5,0xe5,0x01,0x04,0x09,0xe5,0x0a,0x0c,0x02,0x01,0x0b,0x07,0x01,
+ 0x14,0x06,0x09,0x25,0xe6,0x09,0xe5,0x0c,0x0a,0x03,0x13,0x04,0x02,0x06,0x02,0x08,
+ 0x02,0x0e,0x02,0x0d,0x16,0x01,0xe5,0xe5,0x01,0x0b,0x07,0xe5,0x01,0x02,0x08,0x27,
+ 0x49,0xe5,0xe5,0xe5,0x12,0x06,0x0e,0xe6,0x03,0x01,0x1c,0x0f,0x04,0x01,0x0e,0x11,
+ 0xe6,0xe5,0x0a,0x15,0xe6,0x0a,0x04,0x07,0x0b,0xe6,0x02,0x03,0x08,0xe8,0x05,0x06,
+ 0x02,0x12,0x20,0x2e,0x0a,0x02,0x09,0xe5,0x12,0xe5,0x0b,0x04,0x06,0x02,0x09,0x09,
+ 0xe5,0x0a,0x08,0x01,0x07,0x05,0x18,0x0b,0x01,0x13,0x44,0x01,0x01,0x13,0x01,0x0a,
+ 0x04,0x04,0x05,0x14,0x01,0xe5,0x05,0x01,0x02,0x06,0x0a,0x08,0xe5,0x05,0x01,0x06,
+ 0x02,0xe5,0x05,0x01,0xe5,0x07,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x1a,0x02,0x05,
+ 0x03,0x09,0x05,0x03,0x03,0x01,0x03,0x09,0x05,0xe5,0x07,0x1f,0x03,0xe5,0xe7,0x0e,
+ 0x2f,0x0d,0x02,0x0c,0x0c,0x06,0x0e,0x04,0x0d,0x08,0x1d,0x01,0xe5,0x05,0x01,0x05,
+ 0xe5,0x01,0x0f,0xe5,0x08,0x12,0xe5,0x06,0x01,0x20,0xe6,0x02,0x1c,0x1f,0x04,0x1b,
+ 0x01,0x11,0x01,0x02,0x0e,0x01,0x12,0x09,0x05,0x03,0x1f,0x0c,0x06,0x0a,0x12,0x08,
+ 0x08,0x1c,0xe5,0xe7,0x2b,0xe5,0x06,0xe5,0x09,0xe5,0x07,0x09,0x09,0x09,0x09,0xe5,
+ 0x07,0x09,0x09,0xe5,0x04,0x06,0xe5,0x05,0x02,0xe5,0x04,0x05,0x02,0xe5,0x07,0xe5,
+ 0xe6,0x05,0x08,0xe5,0x28,0xe5,0x05,0x1e,0xe7,0xe6,0x01,0x01,0x12,0xe5,0x11,0xe5,
+ 0x01,0x0a,0x04,0xe5,0x01,0x09,0x09,0x05,0xe5,0x01,0x08,0x06,0xe5,0x01,0x09,0x05,
+ 0xe5,0x01,0x09,0x0d,0xe5,0x01,0xe5,0x0a,0x03,0x01,0xe5,0x0c,0x01,0xe5,0x01,0xe5,
+ 0x0a,0x2a,0xe5,0x21,0x01,0x02,0x01,0xe6,0x03,0x05,0xe5,0xe5,0xe5,0x03,0x01,0xe5,
+ 0xe5,0x12,0x02,0xe6,0x01,0x01,0x09,0x04,0xe5,0x02,0x04,0x01,0xe5,0x04,0xe5,0x03,
+ 0x13,0x04,0x01,0x02,0x09,0x04,0x01,0xe5,0x04,0xe5,0x05,0x04,0xe5,0x04,0x0f,0x03,
+ 0x0c,0xe5,0x02,0x01,0x0f,0x01,0x1b,0x01,0x07,0x01,0x01,0x1b,0x08,0x02,0x06,0xe5,
+ 0x01,0x01,0x04,0x02,0x01,0x11,0x06,0xe5,0xe5,0xe5,0x06,0x06,0xe5,0xe5,0x08,0x06,
+ 0xe5,0xe5,0x0f,0xe5,0xe5,0x08,0x09,0x09,0x06,0xe5,0x01,0xe5,0x05,0xe5,0x14,0x10,
+ 0x02,0x13,0x01,0x18,0x02,0x01,0x07,0x01,0x1f,0x02,0xe8,0x14,0x08,0x01,0x02,0x09,
+ 0x11,0x04,0xe5,0x01,0xe5,0x08,0x01,0x02,0x09,0xe5,0x01,0xe5,0xe5,0x01,0x09,0x01,
+ 0x01,0xe5,0xe5,0x01,0x01,0x01,0xe5,0x04,0x02,0xe5,0xe5,0x01,0x06,0x04,0x06,0x02,
+ 0xe5,0x01,0xe5,0xe5,0x01,0x04,0x11,0x07,0x02,0x0c,0x06,0x12,0x03,0x02,0x03,0x02,
+ 0x02,0x03,0x1d,0xe6,0x01,0x0e,0x0c,0x01,0x02,0x07,0x03,0x04,0x04,0x05,0x04,0x03,
+ 0x02,0x06,0xe5,0xe5,0x01,0x09,0x03,0xe5,0xe5,0xe5,0x09,0x04,0x01,0x02,0x01,0x01,
+ 0xe5,0x07,0xe5,0xe5,0x01,0x08,0x02,0x01,0x01,0xe5,0x03,0x03,0xe5,0xe5,0xe5,0x04,
+ 0x03,0x18,0x0a,0x07,0xe5,0x13,0x04,0x02,0x01,0x04,0x02,0x19,0x02,0x01,0xe7,0x0b,
+ 0x01,0x13,0x09,0x05,0x01,0x01,0x04,0x02,0x07,0x01,0x01,0x05,0x01,0x04,0x04,0x01,
+ 0x05,0x01,0x01,0x04,0x02,0x01,0x09,0x07,0x07,0x01,0x0b,0x01,0x07,0x01,0x02,0x02,
+ 0x01,0x01,0x01,0xe5,0x03,0x04,0x0e,0x01,0x05,0x0d,0x05,0x17,0x09,0x1b,0xe5,0x03,
+ 0x04,0x01,0xe5,0x09,0x01,0x13,0x07,0x09,0x01,0x05,0x01,0x04,0x04,0x01,0x02,0x04,
+ 0x04,0x04,0x01,0x02,0x04,0x01,0x01,0xe8,0xe5,0xe5,0x01,0x04,0x04,0x04,0x04,0x04,
+ 0x04,0x06,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x13,0x01,0x02,0x0e,0x04,
+ 0x18,0x04,0x04,0x04,0x18,0x08,0xe6,0x3a,0xe5,0x11,0x02,0x17,0x20,0xe5,0x07,0x02,
+ 0x08,0x02,0x06,0x02,0x03,0x2a,0x02,0x2e,0x02,0x1b,0x03,0x1b,0x02,0x06,0x16,0x09,
+ 0xe5,0x04,0x02,0xe5,0x17,0xe5,0x0b,0x10,0x18,0x09,0x05,0xe5,0x1c,0x13,0x2a,0x1d,
+ 0xe5,0x01,0xe5,0x0d,0x06,0x02,0x03,0x05,0x09,0x09,0x03,0x05,0x09,0x09,0x04,0x01,
+ 0x02,0x06,0x02,0xe5,0x07,0x03,0x05,0x09,0x09,0x0b,0x03,0x02,0x02,0x03,0x05,0xe6,
+ 0x06,0x02,0x06,0x06,0x02,0x09,0x04,0x01,0x02,0x09,0x09,0x04,0x01,0x02,0x09,0x03,
+ 0x05,0x09,0x0d,0xe7,0xe5,0x01,0x12,0xe5,0x30,0x09,0x09,0x06,0x02,0x13,0x13,0x12,
+ 0x02,0x26,0xe5,0x12,0x1d,0x09,0x22,0x06,0x15,0x30,0x08,0x0b,0x08,0x06,0x0b,0x13,
+ 0x15,0x27,0x15,0x1b,0x09,0x2c,0x01,0x14,0xe5,0x05,0x16,0x01,0x07,0x01,0x02,0x01,
+ 0x04,0x02,0x06,0x02,0x01,0x04,0x02,0x01,0x01,0x02,0xe7,0xe5,0x01,0x01,0x02,0x01,
+ 0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x04,0x02,0x05,0xe5,0xe5,0x01,0x01,0x04,0x02,
+ 0x07,0x01,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x04,0x04,0x02,0x06,0x0e,
+ 0x04,0x02,0x01,0x04,0x02,0x1f,0xe6,0xe5,0x16,0x02,0xe5,0xe5,0x06,0x01,0xe5,0x0b,
+ 0x01,0xe5,0x05,0x01,0x01,0x05,0x03,0x01,0xe5,0x01,0x01,0x01,0x02,0x02,0x01,0x01,
+ 0x05,0x02,0xe5,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x01,0x03,0x01,0x01,
+ 0x02,0x04,0x01,0x01,0x05,0x03,0x09,0x04,0xe5,0xe6,0x05,0x01,0xe5,0x02,0x02,0x03,
+ 0x01,0x03,0x01,0xe5,0x05,0x01,0x01,0x01,0x05,0xe5,0x0f,0x01,0x01,0x05,0x03,0x19,
+ 0xe5,0x02,0x02,0x02,0x14,0x02,0x01,0x04,0x1c,0xe5,0x03,0x04,0x04,0x03,0x05,0x09,
+ 0x03,0x05,0x01,0x02,0x04,0x04,0x04,0x04,0x04,0x03,0xe5,0x0f,0x03,0xe5,0x03,0x04,
+ 0x0c,0x01,0x06,0xe5,0xe5,0x06,0x01,0x03,0x02,0x0c,0x04,0x04,0x13,0x03,0x05,0x22,
+ 0xe6,0xe5,0x14,0xe6,0x06,0xe5,0x07,0xe5,0x06,0xe6,0x05,0xe7,0x01,0x03,0xe7,0x01,
+ 0x03,0xe8,0xe5,0x02,0xe8,0xe5,0x02,0xe8,0x04,0xe7,0x01,0x03,0xe8,0xe5,0x02,0xe7,
+ 0x01,0x03,0xe7,0x01,0x03,0xe7,0xe5,0x01,0x04,0xe6,0x01,0x03,0xe7,0x06,0xe7,0xe5,
+ 0x04,0xe6,0xe5,0x04,0xe6,0x04,0xe7,0x07,0xe6,0xe5,0x02,0xe7,0x01,0x05,0xe5,0x07,
+ 0xe6,0xe5,0x02,0xe7,0x01,0x03,0xe7,0x07,0xe5,0x07,0xe7,0x02,0x01,0x01,0xe6,0x16,
+ 0x01,0x07,0x01,0x0a,0x05,0xe5,0xe6,0x02,0x01,0xe5,0x07,0x02,0x06,0x09,0x09,0x02,
+ 0xe5,0x01,0xe5,0xe6,0x07,0x09,0xe5,0x07,0x02,0x06,0x0b,0x02,0x06,0x07,0x01,0x03,
+ 0x12,0x06,0xe5,0xe5,0x0f,0x02,0xe5,0x18,0x02,0x06,0x1b,0x01,0x01,0x17,0x01,0x07,
+ 0x01,0x0a,0x06,0x01,0x03,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x01,0x04,0xe7,
+ 0x04,0x01,0xe6,0x06,0xe6,0x04,0x01,0xe5,0x01,0x04,0xe7,0x04,0x01,0xe6,0xe5,0x03,
+ 0xe6,0x08,0x01,0xe5,0x05,0xe6,0x08,0x1a,0x01,0xe6,0xe5,0x06,0x05,0x01,0xe5,0x01,
+ 0xe5,0x0f,0x05,0x01,0xe6,0x04,0x01,0xe5,0x13,0xe5,0x03,0x01,0xe5,0xe5,0x16,0x01,
+ 0x01,0x05,0x01,0x01,0x0c,0x05,0x04,0x05,0x02,0xe5,0x02,0x01,0x02,0xe5,0x04,0x01,
+ 0x01,0x05,0x02,0xe5,0x02,0xe6,0x02,0x05,0x02,0xe5,0x04,0x01,0x01,0x05,0x02,0xe5,
+ 0x04,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x01,0x01,0x05,0x08,0x12,0x01,0x02,0xe5,
+ 0x0e,0x02,0xe5,0x02,0x15,0x02,0xe5,0x02,0x01,0x02,0xe5,0x14,0x06,0xe6,0xe5,0x16,
+ 0x01,0x07,0x01,0x0a,0x03,0x05,0x02,0xe5,0x07,0x05,0x03,0x05,0x04,0x02,0x05,0x03,
+ 0x05,0x09,0x05,0x04,0x08,0x05,0x04,0x06,0x04,0x04,0x04,0x0f,0x16,0x0d,0x05,0x05,
+ 0xe5,0x0f,0x05,0x05,0x03,0x18,0x03,0x01,0x03,0x02,0x0e,0x0f,0xe5,0xe5,0x09,0xe5,
+ 0x10,0x04,0x0b,0xe5,0xe7,0x2b,0xe5,0xe5,0x05,0x02,0x01,0x22,0x03,0xe5,0x3c,0x33,
+ 0x02,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x02,0x04,0x01,
+ 0x01,0x05,0x01,0xe6,0x04,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,
+ 0x06,0xe5,0xe5,0xe5,0x04,0x01,0x01,0x02,0x02,0x01,0xe6,0x06,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0xe6,0x05,0xe5,0xe5,0xe5,0x04,0x01,
+ 0x07,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x0d,0xe5,0x28,0x03,0xe5,
+ 0x07,0xe5,0x02,0x02,0x01,0xe5,0xe5,0x05,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x0b,0x05,
+ 0xe5,0x01,0x05,0xe5,0xe5,0x04,0xe6,0x05,0x01,0xe5,0x06,0x05,0x03,0x0c,0x09,0x01,
+ 0x04,0x19,0x21,0x2f,0x01,0xe7,0x0a,0x08,0x05,0x10,0x09,0x07,0x10,0x02,0x0f,0x16,
+ 0x11,0x1c,0x02,0xe6,0x02,0xe5,0x01,0xe5,0x11,0x09,0x0a,0x08,0x02,0x06,0xe5,0x08,
+ 0x0b,0x07,0x0b,0x10,0xe5,0x02,0x24,0x07,0x03,0x05,0x08,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x0b,0x05,0x01,0x06,0xe5,0xe5,0xe5,0x04,0x01,0x03,0x03,0x01,0x0e,0x14,
+ 0x04,0x01,0x03,0x28,0xe5,0x3c,0x03,0x01,0x02,0xe5,0x07,0x07,0x06,0xe6,0x02,0x03,
+ 0xe6,0x09,0xe5,0x03,0x0a,0x04,0x0d,0xe7,0x01,0x01,0x02,0xe5,0x11,0x01,0x02,0x04,
+ 0xe7,0x05,0x01,0x13,0x01,0x03,0x17,0x06,0x02,0xe5,0x07,0x13,0x01,0x4e,0x13,0x04,
+ 0x09,0x04,0x1a,0x02,0x0c,0xe5,0x0d,0x03,0x09,0x01,0x01,0x04,0x02,0x02,0x05,0x02,
+ 0x04,0x0b,0x01,0x02,0x1c,0x0e,0x04,0x0e,0x02,0x01,0x4a,0x03,0x09,0x05,0x0d,0x19,
+ 0x03,0xe5,0x0c,0xe6,0x01,0x04,0xe5,0x02,0x09,0x0a,0x12,0xe5,0x06,0x01,0x0c,0x07,
+ 0x09,0x0a,0x06,0x07,0x03,0x05,0x03,0x05,0x02,0x02,0x07,0x09,0x19,0x24,0x01,0x01,
+ 0x0b,0xe5,0xe5,0x14,0x02,0x06,0x01,0x02,0x02,0xe5,0x09,0x04,0x09,0x09,0x02,0x06,
+ 0x01,0x02,0x04,0x02,0x06,0x01,0x07,0x02,0x04,0x01,0x01,0x02,0xe5,0x04,0x02,0x06,
+ 0x01,0xe5,0x01,0x03,0x04,0x04,0x01,0x07,0xe5,0x18,0x02,0x1b,0x0c,0x25,0x01,0x06,
+ 0x06,0x10,0x14,0x05,0x0e,0xe5,0x02,0xe5,0x03,0x0b,0x0c,0x01,0x04,0x01,0x0a,0x06,
+ 0x01,0x0c,0x02,0x03,0x01,0xe5,0x0f,0x02,0x08,0x07,0x0a,0x09,0xe5,0x06,0x04,0x12,
+ 0x34,0xe6,0x09,0x1d,0x01,0x07,0x01,0x09,0xe7,0x0f,0xe6,0x04,0x03,0x08,0x0a,0x03,
+ 0x04,0x0a,0x04,0x03,0xe6,0x06,0xe6,0x08,0x04,0x05,0x0d,0xe5,0x01,0x09,0xe7,0x06,
+ 0xe6,0x06,0x0d,0x40,0x01,0x3c,0x04,0x0d,0x03,0x02,0x04,0xe5,0xe5,0x03,0xe5,0xe6,
+ 0x0a,0x02,0x04,0x0a,0x0b,0x06,0x01,0x07,0x01,0x06,0x01,0x01,0x05,0xe5,0x11,0x05,
+ 0x09,0x05,0xe5,0x0c,0x34,0x05,0x03,0xe5,0x01,0x0c,0xe5,0xe5,0x13,0x02,0x05,0x05,
+ 0xe5,0x01,0x06,0x07,0x04,0x06,0x02,0x03,0x0f,0x04,0x0e,0x01,0x04,0x07,0x04,0x04,
+ 0x10,0x13,0x07,0x01,0x03,0x08,0xe6,0x07,0x01,0x4e,0x02,0xe6,0x0d,0x01,0x12,0x08,
+ 0x04,0x04,0x01,0x0e,0x01,0x02,0x06,0x0a,0x01,0x07,0x05,0x03,0x01,0x07,0x09,0x09,
+ 0x0b,0x01,0xe5,0x05,0x09,0x09,0x01,0x07,0x16,0x06,0xe5,0xe5,0x1a,0x21,0x08,0x03,
+ 0xe5,0xe5,0x03,0x07,0x1f,0x09,0x23,0x02,0x07,0x01,0x09,0x07,0x01,0x09,0x02,0xe5,
+ 0x02,0x01,0x0b,0x07,0x01,0x09,0x07,0x01,0x09,0x0b,0x11,0x04,0x49,0xe6,0x0a,0x16,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x01,0xe5,0x03,0xe5,0x04,0x09,0x03,0x01,0xe5,
+ 0x01,0x03,0xe5,0x03,0x03,0x05,0x09,0x03,0x05,0x03,0x05,0x03,0x02,0x01,0x02,0x03,
+ 0x02,0xe5,0xe5,0x02,0x05,0x03,0x05,0x06,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x01,
+ 0xe5,0x01,0x03,0x09,0x05,0x16,0xe5,0x27,0xe6,0x01,0xe5,0x01,0x01,0x08,0xe6,0x14,
+ 0x05,0x03,0x05,0xe6,0xe5,0x01,0x01,0x06,0xe5,0x03,0x04,0x01,0x02,0x03,0xe5,0x03,
+ 0xe5,0x01,0xe5,0x03,0xe5,0x07,0x09,0xe5,0x07,0xe5,0x02,0x01,0x02,0x0b,0x04,0x01,
+ 0x02,0xe5,0x07,0xe5,0x01,0xe5,0x03,0x04,0x01,0x02,0x04,0x01,0x02,0x03,0xe5,0x03,
+ 0x08,0xe6,0x07,0x02,0x12,0x25,0x01,0x02,0x02,0xe5,0x03,0x08,0x01,0x02,0x18,0x09,
+ 0x01,0x0b,0x02,0x04,0x04,0x04,0x01,0xe5,0xe5,0x03,0x04,0x04,0x04,0x04,0x04,0x04,
+ 0x04,0x04,0x02,0x01,0x04,0x01,0xe5,0xe5,0x05,0x01,0x02,0x04,0x02,0x01,0x04,0x02,
+ 0x01,0x04,0x04,0x04,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x01,
+ 0x04,0x04,0x3d,0x04,0x03,0x02,0x06,0xe5,0x03,0x1b,0x09,0x01,0x0e,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x0a,0x3d,0x04,0xe6,
+ 0x0f,0x1a,0x09,0x01,0x04,0x01,0x0c,0x02,0x03,0x02,0x02,0x06,0x02,0xe5,0x01,0x02,
+ 0x02,0x01,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x01,0x01,0x02,0x02,0x01,
+ 0x01,0x04,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x06,0x02,0x01,0x01,0x02,0x02,0x06,
+ 0x02,0x03,0x02,0x02,0x04,0x04,0x04,0x1d,0x01,0x22,0xe5,0x01,0x02,0x0e,0x01,0x02,
+ 0x14,0x03,0x05,0x01,0x01,0x04,0x0a,0x03,0x02,0xe7,0x02,0x05,0x03,0x04,0xe5,0x02,
+ 0x05,0x03,0x05,0x03,0x01,0x02,0xe5,0x02,0x04,0xe5,0x02,0x07,0x03,0x04,0xe5,0x02,
+ 0x02,0x01,0xe5,0x02,0x01,0x02,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0x02,0x01,0x01,
+ 0xe6,0x02,0x01,0x02,0xe5,0x02,0x07,0x01,0x01,0x02,0x14,0x01,0x01,0x1d,0x03,0xe8,
+ 0x29,0x09,0x01,0x04,0xe6,0x04,0x04,0x03,0x05,0x09,0x07,0x01,0x04,0x04,0x09,0x03,
+ 0xe7,0x01,0x05,0xe6,0xe5,0x03,0x06,0x03,0x03,0x01,0x04,0x04,0x03,0x02,0x02,0x03,
+ 0x02,0xe7,0x03,0x01,0xe5,0xe5,0x03,0x04,0x06,0x04,0x01,0xe5,0xe5,0x01,0x1d,0x01,
+ 0x21,0x02,0x01,0x10,0x1a,0x05,0xe5,0x01,0x06,0x01,0x0c,0x02,0x01,0x01,0x02,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x02,0x06,0x01,0xe5,
+ 0xe5,0x03,0x01,0xe5,0x04,0x02,0x02,0x06,0x01,0xe5,0x05,0x02,0x01,0xe6,0x01,0x02,
+ 0x01,0x01,0x02,0x01,0xe8,0x02,0x01,0xe5,0x05,0x01,0xe5,0xe6,0x02,0x02,0x02,0x03,
+ 0x1b,0x01,0x1f,0x05,0xe5,0x0f,0x02,0x02,0x1a,0xe5,0x15,0x02,0x02,0xe5,0x01,0x02,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x01,0x02,0x02,0x03,0x02,
+ 0x02,0x01,0x01,0x02,0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x04,0x02,0x44,0x02,0xe7,
+ 0x0f,0x21,0xe5,0x17,0xe5,0x01,0xe5,0x03,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x06,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x08,0x3c,0xe8,0x08,0x01,0x02,0xe5,0x07,0x09,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x09,0x07,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x06,0xe5,0xe7,0x04,
+ 0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe6,0x06,0x03,0x05,0x09,0x09,0x09,0x09,0x0d,0xe6,0xe6,0x01,0x09,
+ 0x1d,0x1e,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x49,0x02,0x01,0xe6,0x0a,0x1d,0x1f,0x09,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x05,0xe5,0x01,0x06,
+ 0x02,0xe5,0x04,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0x4a,0xe7,0x0e,0xe5,0x19,0x01,0x11,0x01,0x09,0xe7,0x03,0x02,0x01,0x04,0x02,
+ 0xe6,0x03,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0xe6,0x03,0x02,0x01,0x04,0x02,0x01,
+ 0x06,0x02,0x01,0x03,0xe5,0x01,0x01,0x04,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0x01,
+ 0x04,0x02,0x01,0x04,0x02,0xe6,0x03,0x02,0x01,0x4b,0x11,0x19,0x01,0xe5,0x08,0x06,
+ 0x01,0xe5,0x05,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x03,
+ 0xe5,0x01,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x03,0x02,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x01,0x02,0x02,0xe5,0x07,0x35,0x02,0xe5,0x02,0x03,0x01,0xe5,0x26,
+ 0x02,0x01,0x11,0x01,0x04,0x0e,0x04,0x01,0x02,0x09,0x09,0x04,0x04,0x01,0x04,0x02,
+ 0x04,0x04,0x08,0x02,0x04,0x04,0x09,0x01,0x07,0x04,0x01,0x02,0x04,0x04,0x09,0xe5,
+ 0x07,0x07,0x01,0x17,0x28,0xe5,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x01,
+ 0x03,0xe8,0xe5,0x02,0xe7,0x02,0x02,0x01,0xe5,0x01,0x05,0xe5,0x01,0xe5,0x02,0xe6,
+ 0x01,0x03,0xe7,0x01,0x05,0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,0x03,0x01,
+ 0xe5,0x03,0x04,0xe6,0x01,0x04,0xe6,0x01,0x04,0xe6,0x01,0xe5,0x03,0xe5,0x01,0x05,
+ 0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,0x03,0x01,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe5,0x06,0xe6,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe6,0x03,0x03,0x01,0x09,0x10,0x10,
+ 0x01,0xe6,0x07,0xe5,0x07,0x06,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x09,0xe5,0x07,
+ 0xe5,0x07,0xe6,0x06,0xe5,0x09,0xe5,0x07,0x09,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,
+ 0x07,0xe6,0x06,0xe6,0x28,0x18,0x07,0x01,0x12,0x18,0x01,0x0e,0x01,0x03,0x02,0x02,
+ 0xe5,0xe5,0x01,0x03,0x02,0xe5,0xe5,0x02,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0xe5,
+ 0xe5,0x02,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0xe5,0xe5,0x02,0x04,0xe5,0xe5,0x02,
+ 0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0xe5,0xe5,0x02,0x02,0x02,
+ 0x06,0x02,0x03,0x1d,0x09,0x14,0xe5,0x03,0x01,0x02,0xe5,0x18,0x10,0x01,0x0d,0x01,
+ 0x08,0xe5,0xe5,0x01,0x02,0x01,0x01,0x07,0x01,0x02,0x03,0xe5,0xe5,0x04,0xe6,0xe5,
+ 0x06,0x01,0x02,0x02,0x01,0x01,0x07,0x01,0x05,0x01,0x02,0xe5,0x05,0x02,0x06,0xe5,
+ 0xe5,0x01,0x03,0x02,0x02,0x06,0x09,0x05,0x01,0x01,0x09,0x05,0x01,0x01,0x01,0x18,
+ 0xe5,0x08,0x15,0x09,0xe5,0x02,0x16,0x10,0x01,0xe5,0x08,0x02,0xe7,0x02,0x02,0xe7,
+ 0x01,0x03,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,
+ 0xe7,0x01,0x06,0x01,0xe5,0x04,0xe8,0x07,0xe5,0x08,0x09,0x05,0xe8,0x08,0x05,0xe8,
+ 0xe5,0x16,0xe7,0x06,0xe6,0x14,0x03,0x01,0x01,0xe6,0x0f,0x1a,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0xe5,0x07,0x09,0x09,0x31,0x09,0x1f,0x2d,0xe5,0xe5,0xe5,0x1b,0xe5,0x2c,0x0b,
+ 0x05,0x01,0x02,0x04,0x01,0x07,0x01,0x03,0x03,0x01,0x02,0x01,0x02,0x01,0xe5,0x05,
+ 0xe7,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0xe7,0x05,0x01,0x02,0x04,0x01,0xe6,0x04,
+ 0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x02,0x06,0x01,0x07,0xe8,0x04,0x01,0x02,0x04,
+ 0x01,0x01,0x05,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0xe6,0x04,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x09,0x01,0x02,0x08,
+ 0x01,0x01,0xe5,0x01,0x05,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0xe5,0x03,0xe5,0x0a,
+ 0x06,0xe5,0x02,0x04,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x02,0xe5,0x01,0xe5,0x03,0xe5,
+ 0xe5,0x05,0xe5,0x01,0xe6,0x02,0xe5,0x01,0xe5,0x03,0xe5,0xe5,0x04,0x02,0xe5,0x07,
+ 0x09,0xe6,0xe6,0x03,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x0c,0x01,0x01,0x16,0x05,
+ 0x2c,0x03,0xe5,0x0a,0x01,0x06,0x01,0x07,0x01,0x08,0xe5,0x01,0xe5,0x02,0x01,0x06,
+ 0x06,0x06,0x04,0x02,0xe5,0x07,0xe5,0x08,0x04,0xe5,0xe5,0xe5,0x08,0x05,0x03,0x0a,
+ 0xe5,0x08,0x05,0x08,0x03,0xe5,0x04,0x04,0x03,0xe5,0x03,0x01,0x07,0xe6,0x04,0x06,
+ 0x04,0x01,0x05,0x06,0x01,0x07,0x0c,0x09,0x1a,0xe6,0x01,0x05,0x08,0x0a,0x09,0x08,
+ 0x04,0x05,0x02,0x03,0x09,0x02,0x08,0x03,0x03,0x01,0x03,0x06,0x08,0x03,0x03,0x02,
+ 0x03,0x04,0x0d,0x01,0x01,0x04,0x02,0x03,0x02,0x09,0x02,0x05,0x0a,0x18,0x05,0x05,
+ 0x15,0x23,0x09,0x03,0x0f,0x01,0x19,0x01,0x09,0x07,0xe7,0x11,0xe5,0x02,0x02,0x02,
+ 0x02,0x01,0x01,0x04,0x02,0x03,0x13,0x07,0x01,0xe5,0x07,0x02,0xe5,0x01,0xe5,0xe5,
+ 0xe5,0x01,0x01,0xe5,0x03,0x04,0x01,0x03,0x05,0x01,0x07,0x01,0x09,0xe5,0x12,0x05,
+ 0x03,0x09,0x0c,0x1c,0x01,0x02,0xe5,0xe5,0x0a,0x0f,0x0d,0x01,0x01,0x04,0x01,0x06,
+ 0x09,0x09,0x09,0x03,0x06,0x02,0x06,0x08,0x13,0xe5,0x01,0x07,0xe5,0x01,0x07,0x02,
+ 0x02,0x02,0x06,0x06,0x09,0x08,0x55,0x0b,0xe5,0x0e,0x03,0x13,0x05,0x03,0x0d,0xe6,
+ 0x02,0x0a,0x02,0xe6,0xe5,0xe5,0x04,0x0d,0x03,0x0a,0xe5,0x02,0x03,0x01,0x02,0x04,
+ 0xe6,0x02,0x03,0x03,0x01,0x07,0x0e,0x08,0x03,0xe6,0x06,0x05,0x03,0x05,0x06,0x01,
+ 0x0a,0x13,0x08,0x1f,0xe6,0xe5,0x07,0x04,0xe5,0x03,0x08,0x0e,0xe5,0x0a,0x06,0x01,
+ 0xe5,0x05,0x04,0x04,0x09,0x02,0x09,0x0a,0xe5,0x06,0x05,0xe6,0xe5,0x11,0xe5,0x02,
+ 0x04,0x04,0x04,0x13,0x01,0x01,0x05,0x01,0x0a,0x03,0x02,0x01,0x0a,0x0b,0x02,0x01,
+ 0x09,0x01,0x0c,0x15,0x03,0x03,0x02,0x08,0x0e,0x07,0x02,0x03,0x06,0x04,0x02,0x0b,
+ 0xe5,0x08,0x05,0x03,0x02,0x0d,0x01,0x05,0x09,0x01,0x01,0x02,0x0e,0x02,0x03,0x01,
+ 0xe5,0x03,0x02,0x01,0x01,0x04,0x02,0x08,0xe5,0x11,0x16,0x18,0x0c,0x15,0x06,0x03,
+ 0x01,0xe5,0x01,0x0e,0x05,0xe6,0x06,0xe6,0x06,0xe5,0x05,0x02,0x02,0x0b,0x01,0x04,
+ 0x02,0x06,0x04,0x07,0x01,0xe5,0xe5,0x0f,0x07,0x02,0x08,0xe5,0x03,0x05,0x09,0x0f,
+ 0x01,0x01,0xe8,0x02,0xe5,0x07,0x07,0x02,0x01,0x05,0x01,0x01,0x0a,0x03,0xe6,0x01,
+ 0xe7,0x05,0x09,0x0a,0xe6,0x10,0x07,0xe7,0x01,0x01,0x14,0x09,0x07,0x01,0x08,0x16,
+ 0x03,0x05,0x10,0x03,0x0a,0x13,0x0d,0x13,0x0d,0x01,0x1d,0x09,0x03,0x01,0x0b,0x1e,
+ 0x17,0x01,0xe6,0x09,0x01,0x04,0x0b,0x09,0x06,0x01,0xe5,0x09,0x01,0xe5,0xe6,0x01,
+ 0x08,0xe6,0x17,0x04,0x05,0x05,0x03,0x02,0xe5,0x01,0x01,0x0c,0x01,0x01,0x01,0x0c,
+ 0xe5,0x01,0xe5,0x07,0x0f,0x04,0x04,0x0d,0x02,0x02,0xe5,0x01,0x09,0x09,0x05,0x09,
+ 0xe5,0x14,0x02,0x0b,0xe6,0x18,0x20,0x05,0x14,0x12,0x05,0xe6,0xe6,0x01,0x03,0x01,
+ 0x02,0x06,0x02,0xe5,0x08,0x04,0x05,0xe5,0x01,0x02,0x07,0x01,0x0a,0x12,0x02,0x07,
+ 0x03,0x04,0x1c,0x0a,0x20,0xe5,0x01,0xe6,0x12,0x2d,0x28,0xe5,0x17,0x02,0x01,0x15,
+ 0x05,0x01,0x1b,0x09,0x01,0x11,0x01,0x25,0x01,0x24,0x01,0xe6,0x06,0xe5,0x01,0x01,
+ 0xe7,0x06,0xe5,0x07,0xe6,0x06,0x06,0x01,0x01,0xe5,0x07,0x07,0x01,0xe5,0xe5,0xe5,
+ 0x03,0x07,0x01,0xe5,0x06,0xe5,0x04,0x01,0x0b,0x09,0x02,0x01,0x02,0x01,0xe5,0xe5,
+ 0xe5,0x03,0xe7,0x07,0x09,0x08,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x01,0xe5,0xe5,0x02,
+ 0x12,0xe6,0x07,0x09,0xe5,0x1c,0x01,0xe6,0xe5,0x01,0x01,0x04,0xe5,0x03,0x04,0xe5,
+ 0x0e,0x0f,0x03,0x09,0x05,0x03,0x02,0xe5,0x0e,0x08,0x01,0x0e,0xe5,0x01,0x05,0xe5,
+ 0x01,0x02,0x01,0xe6,0x04,0xe5,0x06,0x09,0x05,0xe5,0x01,0x13,0xe5,0x07,0x09,0x05,
+ 0x16,0x0a,0x09,0x1b,0x01,0x03,0x02,0x04,0x08,0x01,0x01,0x09,0x14,0x04,0x06,0x01,
+ 0xe5,0x12,0x03,0x01,0xe5,0x03,0x03,0xe5,0x01,0x01,0x07,0x01,0x04,0x01,0x02,0x09,
+ 0x04,0x01,0x02,0x01,0x0c,0x04,0x0b,0x03,0xe5,0x01,0x01,0x01,0x0f,0x01,0x11,0x03,
+ 0x19,0x01,0x07,0x01,0x1d,0x04,0x01,0x01,0x02,0x07,0x02,0x01,0x25,0x06,0xe5,0xe5,
+ 0x08,0x09,0x06,0xe5,0xe5,0x08,0x01,0x04,0xe5,0xe5,0x08,0x05,0xe5,0x01,0x09,0x15,
+ 0x09,0x05,0xe5,0x01,0x01,0x11,0x01,0x11,0x1d,0x01,0x07,0x01,0x18,0xe5,0x04,0x04,
+ 0xe6,0x0a,0x01,0x01,0x03,0x02,0x14,0x01,0x07,0x0b,0x02,0x04,0x05,0x02,0xe5,0xe5,
+ 0x06,0x04,0xe5,0x01,0x0a,0x04,0xe5,0x01,0x06,0x02,0x07,0x01,0x06,0x02,0x02,0x01,
+ 0x07,0x01,0x02,0x04,0x04,0xe5,0x01,0x0a,0x01,0x07,0x15,0x06,0x16,0x02,0x03,0x02,
+ 0x02,0x03,0x1a,0x04,0x02,0x0a,0x01,0x01,0x02,0x01,0x14,0x01,0x01,0x05,0x03,0x07,
+ 0x02,0x04,0x01,0x06,0xe5,0xe5,0x08,0x02,0x01,0x01,0x04,0x0a,0x01,0x01,0x09,0x07,
+ 0x01,0x09,0x02,0x01,0x01,0x05,0x01,0x02,0x04,0x04,0x03,0x04,0x05,0x01,0x01,0x05,
+ 0x13,0x07,0xe5,0x13,0x04,0x02,0x01,0x04,0x02,0x19,0x02,0x01,0xe7,0x0b,0x01,0x0c,
+ 0x0e,0x01,0x04,0x02,0x09,0x01,0x07,0x07,0x01,0x09,0x01,0x07,0x01,0x02,0x01,0x02,
+ 0x01,0x02,0x01,0x01,0xe5,0xe5,0x04,0x01,0x01,0x07,0x01,0x05,0x02,0xe5,0xe5,0x06,
+ 0x04,0x04,0x07,0x01,0x01,0x07,0x01,0x04,0x02,0x15,0x02,0x02,0x17,0x09,0x21,0xe5,
+ 0xe5,0xe5,0x01,0x0a,0x01,0x1b,0x01,0x04,0xe5,0xe5,0x03,0x04,0x01,0x02,0x04,0x01,
+ 0x02,0x04,0x04,0x04,0x01,0x02,0x04,0x01,0x03,0xe6,0xe5,0x03,0x01,0x02,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x06,0x01,0x07,0x04,0x04,0x04,0x04,0x01,0x07,0x01,
+ 0x04,0xe7,0x03,0x0a,0xe5,0x01,0x04,0x18,0x04,0x04,0x04,0x1c,0x03,0xe5,0xe5,0xe5,
+ 0x10,0x1f,0x07,0x13,0xe5,0x07,0x02,0x10,0x0b,0x11,0x02,0x06,0x0b,0x02,0x10,0x31,
+ 0xe5,0x42,0xe5,0xe5,0x01,0x16,0x22,0x04,0x0e,0x02,0xe5,0x04,0x02,0x09,0x09,0x01,
+ 0x07,0x06,0x09,0x02,0x06,0x02,0x01,0x01,0x07,0x09,0x0b,0x18,0x13,0x02,0x1d,0x27,
+ 0x03,0xe5,0x08,0x01,0x02,0x02,0x06,0x09,0x09,0x04,0x01,0x02,0x02,0x01,0x01,0x02,
+ 0x09,0x04,0x01,0x02,0x03,0x05,0x03,0x02,0x02,0x03,0x05,0x03,0xe5,0xe5,0x01,0x09,
+ 0x04,0xe6,0x01,0x03,0x07,0x03,0x02,0x02,0x03,0xe5,0xe5,0x01,0x09,0x09,0x06,0x02,
+ 0x09,0x04,0x01,0x02,0x03,0x05,0x09,0x04,0x01,0x02,0x05,0x03,0x09,0x09,0x0d,0xe6,
+ 0x01,0x02,0x09,0x27,0x13,0x1c,0x14,0x13,0x12,0x02,0x09,0x1c,0xe5,0x12,0x1d,0x09,
+ 0x1d,0x04,0x02,0x03,0x0b,0x25,0x07,0x0d,0x2f,0x13,0x15,0x0b,0x1b,0x15,0x1d,0x07,
+ 0x1f,0x08,0xe8,0x0e,0x04,0x09,0x09,0x02,0x01,0x09,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x04,0x01,0x02,0x04,0x01,0x09,0x02,0x01,0x04,0x02,0x04,0x01,0x02,0x04,0x01,
+ 0x02,0x01,0x03,0xe5,0xe5,0x06,0x01,0x02,0x06,0x02,0x06,0x09,0x04,0x02,0x01,0x02,
+ 0x01,0x09,0x04,0x02,0x15,0x02,0x01,0x02,0x04,0x01,0x02,0x20,0x02,0x0c,0xe5,0x01,
+ 0x1a,0x01,0xe5,0x02,0x02,0x03,0x05,0x03,0x05,0x03,0x01,0x03,0x01,0x01,0x01,0x03,
+ 0x01,0x01,0x05,0x01,0xe5,0x07,0x01,0x02,0x02,0x01,0x01,0x01,0x03,0x01,0x01,0x01,
+ 0xe5,0x01,0x01,0x01,0x01,0xe5,0x03,0x01,0xe5,0x05,0x03,0x02,0x02,0x03,0x07,0xe5,
+ 0x07,0xe5,0x05,0x03,0x01,0x0d,0x01,0x01,0x01,0x19,0x01,0x02,0x02,0x03,0x20,0x01,
+ 0x01,0xe5,0x0d,0x1b,0x01,0x09,0x09,0x07,0x01,0x13,0x07,0x09,0x01,0x09,0x09,0x09,
+ 0x08,0x0c,0x09,0x03,0xe5,0xe5,0x01,0x06,0x02,0x03,0xe5,0x01,0x01,0x0d,0xe5,0x21,
+ 0x07,0x01,0x03,0x1e,0x03,0xe5,0x0b,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,
+ 0x04,0xe8,0x04,0xe8,0xe5,0x02,0xe7,0x01,0x03,0xe7,0x01,0x03,0xe8,0xe5,0x02,0xe8,
+ 0xe5,0x02,0xe8,0xe5,0x02,0xe7,0x01,0x03,0xe8,0x04,0xe7,0x08,0xe6,0x05,0xe7,0x01,
+ 0x04,0xe6,0x01,0x05,0xe5,0x01,0x05,0xe6,0x04,0xe7,0x07,0xe6,0x04,0xe7,0x07,0xe5,
+ 0x07,0xe5,0x05,0xe8,0x04,0xe7,0x07,0xe5,0x07,0xe5,0x07,0x02,0x09,0x03,0x01,0x0a,
+ 0x09,0x09,0x06,0x01,0xe5,0x07,0x09,0x09,0x11,0x01,0xe6,0x06,0x11,0x09,0x0b,0x01,
+ 0x04,0x02,0x01,0x09,0x09,0xe5,0x07,0xe6,0x06,0x0a,0xe5,0x06,0x0a,0x10,0x01,0x09,
+ 0x0a,0x19,0xe6,0x0c,0x01,0x0a,0x09,0x09,0x06,0x01,0xe6,0xe5,0x01,0x02,0x01,0x01,
+ 0x02,0xe5,0x02,0x01,0x02,0xe5,0xe5,0xe5,0xe5,0x01,0x04,0x01,0x02,0xe5,0xe5,0x03,
+ 0x01,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0xe5,0x02,0x01,0x02,0x02,0x01,0x01,
+ 0x02,0x02,0x01,0x06,0xe5,0x02,0x02,0x01,0xe5,0x02,0x04,0x02,0xe5,0x07,0x0b,0x01,
+ 0x02,0x0a,0x01,0x01,0x01,0x02,0x03,0x04,0x0d,0x01,0x01,0x02,0x04,0x01,0x02,0x03,
+ 0x17,0xe5,0xe6,0x3b,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0xe5,
+ 0xe5,0x02,0x01,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x0c,0x03,0x01,0x03,
+ 0x04,0x04,0x09,0x09,0x04,0xe5,0x11,0xe5,0x16,0x04,0xe5,0x02,0x04,0xe5,0x1c,0xe7,
+ 0x19,0x09,0x09,0x0c,0x01,0xe5,0x01,0x03,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0x01,
+ 0xe5,0x01,0x03,0x01,0xe6,0xe6,0x01,0xe7,0x05,0x01,0xe5,0x01,0x03,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x04,0x03,0x01,0x07,0xe6,0x01,0x06,0x02,0xe5,0x07,0xe5,
+ 0x0b,0x01,0xe5,0x02,0x06,0x05,0x01,0xe5,0x02,0x02,0x13,0x01,0xe5,0x05,0x01,0xe5,
+ 0x02,0x17,0x02,0xe5,0x1b,0x1a,0xe5,0x05,0x02,0x06,0x09,0xe5,0xe5,0x13,0x05,0x02,
+ 0x32,0xe5,0x07,0xe5,0x1b,0xe5,0x0f,0x02,0x3f,0x0a,0xe7,0xe5,0x0e,0x01,0x07,0x01,
+ 0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x02,0x02,0xe6,0x01,0x01,0x02,0x01,
+ 0x03,0x03,0xe6,0x01,0x04,0xe8,0x03,0xe8,0x02,0x02,0xe6,0xe5,0x04,0x01,0x02,0x04,
+ 0xe6,0xe5,0x04,0x01,0xe5,0x07,0x01,0xe6,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,
+ 0x02,0x04,0x01,0x07,0x01,0x02,0x04,0x01,0x0a,0x01,0x01,0x14,0x0b,0x02,0x03,0x0f,
+ 0x02,0x01,0x02,0x01,0x01,0xe5,0x05,0x01,0x01,0xe5,0x0d,0xe6,0x09,0x04,0x03,0x07,
+ 0x09,0xe5,0x02,0x07,0x03,0x01,0x03,0xe6,0x05,0x01,0x02,0x04,0x04,0x0b,0x02,0xe5,
+ 0x03,0x03,0xe5,0x07,0xe5,0x02,0x02,0xe5,0x1d,0x01,0x07,0x1a,0x07,0xe5,0xe7,0x0a,
+ 0x0d,0x03,0x0b,0x09,0x02,0x06,0x02,0x09,0x03,0x02,0x0b,0x0c,0x02,0x0e,0xe5,0x01,
+ 0x04,0x0d,0x06,0x02,0x08,0x06,0x02,0x06,0x0c,0x04,0x03,0x07,0x01,0xe5,0x02,0x06,
+ 0x05,0x06,0x02,0x06,0x05,0x05,0x03,0x06,0x1a,0x04,0x02,0x0d,0x11,0x17,0x03,0x04,
+ 0x03,0x05,0x0a,0x06,0x03,0x07,0x0b,0x0f,0x10,0x12,0x17,0x0b,0xe5,0x03,0x05,0x08,
+ 0x19,0x2c,0x02,0x03,0x0d,0x01,0x01,0x09,0x08,0x06,0x01,0xe5,0x01,0x06,0x09,0x04,
+ 0x01,0x02,0x09,0xe5,0x01,0x02,0x01,0x04,0x04,0xe5,0x02,0xe5,0xe5,0x07,0xe7,0x06,
+ 0x01,0xe5,0x05,0xe6,0x03,0x02,0x08,0x01,0x08,0x1f,0x04,0x1c,0x17,0x01,0x19,0x09,
+ 0xe5,0x02,0x0d,0x02,0x1a,0x01,0x03,0x01,0x09,0x07,0x06,0x04,0x0c,0x01,0x04,0x0e,
+ 0xe5,0x01,0x03,0x06,0x01,0x02,0x05,0xe5,0x04,0x01,0x02,0x2e,0x01,0x03,0x03,0x37,
+ 0x1a,0x04,0x03,0xe5,0xe5,0x08,0x05,0xe5,0x0b,0x09,0x0a,0x04,0x02,0x10,0x01,0xe5,
+ 0x05,0x03,0x05,0x03,0x03,0x05,0x05,0x0a,0x03,0x0e,0x07,0x03,0x01,0x01,0x01,0x03,
+ 0x03,0xe5,0x07,0x08,0x0b,0x04,0x08,0xe5,0x0c,0x0b,0x1a,0x1e,0xe5,0x01,0xe5,0x09,
+ 0x02,0x03,0x12,0x0b,0x04,0x02,0x03,0x05,0x06,0x09,0x09,0x06,0x07,0x04,0x04,0x0b,
+ 0x05,0x03,0x02,0x04,0x06,0x02,0x06,0xe6,0x09,0x03,0x02,0x01,0x11,0x01,0x0c,0x01,
+ 0x05,0x0a,0xe5,0x10,0x03,0x09,0x12,0x0b,0x02,0x03,0x01,0x0b,0xe5,0xe5,0x08,0x1b,
+ 0x12,0xe5,0x03,0x02,0x0b,0x09,0x26,0x04,0xe6,0x0e,0x01,0x07,0x09,0x0b,0x05,0x17,
+ 0x07,0x08,0x2b,0x0a,0xe6,0x04,0x0d,0x08,0x17,0x01,0x07,0x09,0xe6,0x05,0x02,0x13,
+ 0x05,0x03,0x01,0x02,0xe5,0xe7,0x03,0xe5,0xe7,0x07,0xe5,0x07,0x01,0xe6,0x0f,0x10,
+ 0x03,0xe6,0x06,0x01,0x07,0xe5,0x11,0x01,0x07,0xe6,0x37,0x01,0x03,0x01,0x22,0x06,
+ 0x06,0x05,0x0c,0x02,0x05,0x02,0x0c,0x05,0x0b,0x06,0xe5,0x07,0x02,0x04,0xe5,0xe5,
+ 0x03,0x03,0x03,0x1a,0x07,0x04,0x11,0x01,0x1e,0x20,0x14,0xe6,0xe5,0x0e,0x19,0x04,
+ 0x01,0x06,0x03,0x02,0x05,0x01,0x04,0x09,0x02,0xe6,0x03,0xe6,0x0d,0x02,0xe5,0x04,
+ 0x06,0x03,0x01,0x08,0x05,0x06,0x06,0x03,0x02,0xe5,0x03,0x09,0x0e,0x05,0x03,0x02,
+ 0x01,0x06,0x07,0x18,0x03,0x09,0x15,0x08,0x01,0x01,0xe5,0xe5,0xe5,0x09,0x02,0x0b,
+ 0x18,0xe5,0x0b,0xe5,0x03,0x02,0x06,0xe5,0x04,0x02,0x03,0xe5,0x05,0xe5,0x05,0x0a,
+ 0x06,0x01,0x03,0x07,0x09,0x03,0x06,0x07,0xe5,0x02,0x05,0x10,0x09,0x0c,0x1c,0xe5,
+ 0x13,0x14,0x03,0xe7,0x0c,0x01,0x28,0x13,0x09,0x09,0xe5,0x11,0x14,0xe5,0x12,0x02,
+ 0x08,0x05,0x02,0xe5,0x06,0x0a,0x0a,0x0f,0x02,0x09,0x02,0x0e,0x01,0x09,0x20,0xe5,
+ 0x01,0xe6,0x0a,0x09,0x16,0xe5,0x07,0xe5,0x04,0x01,0xe6,0x04,0x02,0x0b,0x01,0xe5,
+ 0x06,0xe5,0x05,0x08,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x11,0x01,0xe5,0xe6,0x01,0x02,
+ 0xe5,0xe6,0x04,0xe6,0xe6,0x03,0x08,0xe6,0x04,0x02,0xe5,0xe6,0x06,0x04,0x17,0x02,
+ 0x01,0xe5,0x08,0x22,0x02,0x01,0xe5,0x01,0x01,0x08,0xe6,0x06,0x17,0xe5,0x05,0xe5,
+ 0x05,0x03,0x05,0xe6,0x15,0xe6,0x05,0x05,0x03,0x09,0xe5,0x03,0xe7,0xe5,0x04,0x09,
+ 0x04,0x01,0xe5,0x01,0xe6,0x01,0xe6,0x02,0xe5,0x01,0xe6,0x08,0xe5,0x0a,0xe7,0xe7,
+ 0x0d,0x02,0x0a,0xe5,0x07,0xe5,0x01,0xe6,0x01,0x06,0x1d,0x01,0x02,0x01,0x01,0x04,
+ 0x05,0x01,0xe5,0xe5,0x06,0x13,0x01,0x04,0x01,0x0a,0x06,0x01,0xe5,0xe5,0x03,0x01,
+ 0xe5,0x03,0x01,0xe5,0xe5,0x05,0x01,0xe5,0xe5,0x02,0xe5,0x06,0x01,0x01,0xe5,0xe5,
+ 0x03,0xe5,0x07,0xe5,0x06,0xe5,0x0d,0x01,0x01,0x07,0x01,0xe5,0x08,0x08,0x05,0x01,
+ 0x0a,0x06,0x09,0x01,0x0b,0x01,0xe5,0x0b,0x04,0x1a,0x08,0x02,0x07,0x02,0x01,0x07,
+ 0x10,0x02,0x01,0x04,0x0c,0x06,0xe5,0xe5,0x05,0x08,0xe5,0x01,0x09,0x01,0x04,0x0c,
+ 0x01,0x04,0xe5,0x06,0xe5,0x0c,0x0a,0x01,0x09,0x1b,0x01,0x08,0x0a,0x04,0x02,0x01,
+ 0x0e,0x0e,0x18,0xe5,0x04,0x02,0x02,0xe5,0x0a,0x01,0x01,0x02,0xe5,0x01,0xe5,0x10,
+ 0x09,0x07,0x02,0xe5,0x08,0x01,0x03,0x01,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0x02,0x07,0x02,0x0a,0x01,0x0c,0xe5,0x01,0x08,0x02,0x0c,0x07,0x01,0x1d,0xe8,0x01,
+ 0xe5,0x06,0xe5,0x0e,0x02,0x01,0x01,0x07,0x08,0x1a,0xe6,0x01,0x02,0x0a,0x03,0x02,
+ 0x01,0xe5,0x02,0x13,0x09,0x02,0x01,0xe5,0x02,0x05,0x01,0x01,0x02,0x01,0x05,0x04,
+ 0x03,0x04,0x04,0x09,0x09,0x05,0x01,0x01,0x09,0x07,0x03,0x09,0x07,0x01,0x05,0x01,
+ 0x01,0x13,0x05,0x02,0xe5,0x06,0x01,0x01,0x01,0xe5,0x03,0x0f,0x01,0x01,0x07,0x01,
+ 0x03,0xe5,0x17,0x02,0xe6,0xe6,0x0b,0x01,0x07,0x13,0x01,0x04,0x07,0x04,0x05,0xe5,
+ 0x01,0x01,0x18,0xe5,0xe5,0xe5,0x10,0x01,0x0c,0x08,0x02,0x09,0x0a,0xe5,0x03,0x07,
+ 0x01,0x04,0x18,0x07,0x09,0x01,0x1b,0x07,0x1b,0xe9,0x0c,0x01,0xe6,0x04,0x13,0x01,
+ 0x05,0x0b,0x09,0x01,0x03,0xe5,0x0b,0x03,0xe5,0x01,0x01,0x01,0x01,0xe5,0x0d,0x01,
+ 0x16,0x01,0xe6,0xe5,0x10,0x04,0x07,0x01,0x03,0xe6,0x10,0xe5,0x01,0x02,0xe5,0x06,
+ 0x04,0x01,0xe5,0xe5,0x0a,0xe5,0x0f,0x1f,0xe5,0x01,0x02,0x05,0xe5,0x08,0x2a,0x1d,
+ 0x06,0x02,0x02,0x03,0x0c,0x1a,0x02,0x02,0x08,0x02,0x08,0x25,0x06,0x02,0x1a,0x02,
+ 0x13,0xe5,0x07,0x0d,0xe5,0x03,0x01,0x02,0x05,0x36,0x01,0x11,0x05,0x05,0x03,0xe5,
+ 0x07,0xe5,0x0d,0x17,0xe5,0x01,0xe5,0x3b,0xe6,0x06,0x01,0x17,0xe5,0x01,0x01,0x11,
+ 0x09,0x01,0x0b,0x05,0xe9,0xe5,0x0b,0x09,0x09,0x06,0x02,0x06,0x02,0x02,0xe5,0x04,
+ 0x06,0x02,0x03,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0x09,0x09,0x09,0xe6,0x03,
+ 0x04,0x02,0x03,0x02,0x09,0x06,0x02,0x09,0x09,0x04,0x01,0x02,0x03,0x05,0x09,0x09,
+ 0xe5,0x03,0x03,0x09,0x03,0x05,0x05,0x03,0x0d,0x01,0xe5,0xe5,0x01,0x24,0x02,0x08,
+ 0xe5,0x11,0x0a,0x1a,0x29,0xe5,0xe5,0x07,0xe5,0x0f,0x20,0x4f,0x04,0x02,0xe5,0x01,
+ 0x27,0x0b,0x1c,0x10,0x09,0x2b,0x02,0x08,0x2f,0x25,0x2b,0x09,0xe7,0xe5,0x07,0x16,
+ 0x01,0x04,0x01,0x02,0x07,0x01,0x07,0x01,0x04,0x0c,0x01,0x01,0x04,0x02,0xe7,0xe5,
+ 0x01,0x01,0xe7,0x05,0x11,0x0c,0x01,0x01,0x04,0x01,0x04,0x02,0x06,0x02,0x09,0x01,
+ 0x09,0x04,0x0c,0x01,0xe6,0x04,0x13,0x01,0xe7,0x03,0x13,0x01,0x1a,0x01,0x10,0xe5,
+ 0x0e,0x01,0xe5,0x05,0x02,0x06,0x01,0xe5,0x02,0x02,0x01,0xe5,0x08,0x06,0x01,0xe6,
+ 0x01,0x02,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x02,0x0c,0x02,0x09,0xe5,0x06,
+ 0x01,0xe5,0x07,0xe5,0x04,0xe5,0x01,0x06,0x01,0xe5,0x04,0xe5,0x01,0x09,0x06,0x01,
+ 0x01,0x05,0x02,0x0d,0x02,0x01,0xe6,0x04,0x02,0x09,0x06,0x01,0xe5,0x16,0x01,0xe6,
+ 0x13,0x0c,0x01,0x09,0x07,0x01,0x07,0x01,0x03,0x0a,0x04,0xe5,0x0f,0x01,0xe5,0x05,
+ 0x01,0x0d,0x03,0x08,0xe5,0xe5,0x07,0x02,0x06,0xe5,0x08,0x09,0x01,0x09,0x03,0x03,
+ 0x01,0x07,0x01,0xe5,0x02,0x02,0x16,0x05,0xe5,0x08,0x01,0x24,0xe6,0x13,0xe6,0x07,
+ 0xe6,0xe5,0x04,0xe6,0x06,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe6,
+ 0x01,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x04,0xe8,0xe5,0x03,0xe6,
+ 0x01,0x01,0x04,0xe6,0x01,0x03,0xe8,0x05,0xe7,0xe5,0x03,0xe7,0x06,0xe6,0xe5,0x02,
+ 0xe8,0xe5,0x04,0xe6,0x04,0xe7,0x07,0xe5,0x07,0xe6,0x04,0xe8,0xe5,0x02,0xe7,0x07,
+ 0xe5,0x07,0xe5,0x06,0xe5,0xe6,0x03,0x08,0x02,0x03,0x01,0x03,0x0f,0x02,0xe6,0x04,
+ 0x01,0xe5,0x08,0xe5,0x07,0x06,0x01,0xe5,0x08,0x10,0x01,0xe5,0x08,0x06,0x05,0xe5,
+ 0x04,0x08,0x01,0xe5,0x05,0x02,0xe5,0xe6,0x01,0x02,0x03,0x02,0x01,0x06,0x02,0xe5,
+ 0x08,0xe5,0xe6,0x01,0x01,0x07,0x02,0xe5,0xe6,0x04,0x06,0x01,0xe5,0x05,0x05,0xe5,
+ 0x07,0xe5,0x01,0x01,0x18,0x03,0x0d,0x04,0x02,0x15,0x09,0x01,0x14,0x06,0x01,0xe5,
+ 0xe5,0x08,0x09,0x04,0x01,0xe5,0x08,0x06,0x08,0x03,0x01,0x03,0x02,0x01,0xe5,0x04,
+ 0x02,0x06,0xe5,0x07,0xe5,0xe5,0x06,0x02,0x0f,0xe5,0xe5,0x01,0x04,0x08,0x03,0x06,
+ 0x01,0x02,0x04,0x08,0x09,0xe5,0xe5,0x1a,0xe5,0x0c,0x02,0x09,0x12,0x07,0x01,0xe5,
+ 0x19,0x01,0x0a,0x10,0x01,0x11,0x07,0x08,0xe5,0x01,0xe5,0xe5,0x03,0x02,0x07,0x01,
+ 0x02,0x08,0x04,0x04,0x07,0x01,0x05,0x03,0x07,0x07,0x0e,0x06,0x07,0x01,0x01,0x05,
+ 0x1c,0x01,0x01,0x0d,0x02,0x02,0xe5,0x04,0x0d,0x02,0x02,0x06,0x01,0xe5,0x08,0x08,
+ 0xe5,0x05,0x01,0xe5,0x19,0x01,0xe5,0x08,0x06,0x05,0x01,0xe5,0x05,0xe7,0x01,0x01,
+ 0xe5,0x02,0x01,0x02,0xe5,0x01,0x01,0xe6,0x01,0x03,0x01,0xe5,0xe6,0x05,0x02,0x06,
+ 0x01,0xe5,0x01,0x01,0xe6,0xe6,0x05,0x02,0x02,0x01,0xe5,0x02,0x10,0x02,0x03,0xe7,
+ 0xe5,0x03,0xe6,0x1a,0xe5,0xe6,0x0c,0x02,0x06,0x02,0xe5,0x0c,0x09,0x03,0xe5,0x05,
+ 0x02,0x06,0xe5,0xe5,0x03,0x06,0x04,0x03,0x0d,0x01,0x02,0x01,0x02,0x15,0x02,0x04,
+ 0x03,0x02,0x0b,0x04,0x01,0xe5,0x0d,0x06,0x1c,0x09,0x14,0x12,0x16,0xe5,0xe6,0xe5,
+ 0x0b,0x02,0x01,0x04,0x02,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,
+ 0x02,0x03,0x01,0x07,0x01,0xe6,0x04,0x01,0x07,0xe6,0xe5,0xe5,0x01,0xe5,0xe5,0xe5,
+ 0x04,0x01,0x01,0x05,0x01,0x01,0x03,0xe6,0xe5,0xe5,0x04,0x01,0x01,0x01,0x05,0x01,
+ 0x07,0x01,0xe6,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0xe5,
+ 0x03,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x0b,0x02,
+ 0x0d,0x01,0xe5,0xe5,0x03,0x01,0xe5,0x01,0x09,0x05,0xe5,0xe5,0x02,0x02,0x01,0x01,
+ 0x01,0x01,0xe6,0x02,0x02,0x15,0xe5,0x02,0x05,0xe5,0x02,0x02,0x01,0x01,0x07,0x04,
+ 0x0e,0xe6,0xe5,0x03,0x02,0xe5,0x01,0xe5,0x08,0x03,0xe6,0x01,0x07,0x01,0x0a,0xe5,
+ 0x13,0x05,0x08,0x03,0x03,0xe5,0x09,0x04,0x06,0x16,0x08,0x02,0xe5,0x0b,0x08,0xe5,
+ 0xe5,0x02,0x09,0xe5,0x01,0x0d,0x04,0x02,0x03,0x07,0x01,0x02,0x03,0x05,0x03,0x07,
+ 0xe5,0x01,0x03,0x02,0x01,0x04,0x0d,0xe5,0x03,0x05,0xe5,0x01,0x02,0x01,0xe6,0xe5,
+ 0x0d,0xe5,0x01,0x03,0x04,0x01,0x02,0x09,0x09,0x1d,0xe5,0x36,0xe5,0xe5,0xe5,0x01,
+ 0x09,0x02,0x1c,0x0a,0x04,0x08,0x06,0x02,0x06,0x02,0x02,0x01,0x07,0x08,0x04,0xe5,
+ 0x01,0xe5,0x01,0x04,0x07,0x01,0x01,0x01,0xe5,0x04,0x17,0x06,0x02,0x06,0x09,0x02,
+ 0x05,0x0b,0xe5,0x16,0x03,0x15,0x12,0x06,0xe5,0x03,0xe5,0x08,0x03,0x04,0x07,0x03,
+ 0x02,0x01,0x02,0x01,0xe5,0x07,0x02,0x01,0x07,0x03,0x05,0xe6,0x06,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0xe5,0x19,0x01,0xe6,0x06,0xe6,0xe5,0x05,0x03,0x0a,0x05,0x01,0x01,
+ 0x03,0x0e,0xe5,0x03,0xe5,0x18,0x0c,0x1d,0x10,0x03,0xe5,0x07,0x06,0x03,0xe5,0xe5,
+ 0x05,0x02,0xe5,0x01,0x0c,0x01,0x01,0x02,0x09,0x03,0x03,0x06,0x04,0x09,0x04,0x03,
+ 0x10,0x11,0x01,0x07,0x22,0x01,0x01,0x0b,0x01,0x0d,0x04,0x01,0x10,0xe6,0x06,0x09,
+ 0x2c,0x09,0x05,0x2b,0x05,0x03,0x0a,0x02,0xe6,0x02,0x03,0x05,0xe5,0x01,0x05,0x09,
+ 0x09,0xe5,0x0b,0x01,0x03,0x03,0x09,0x03,0x02,0x01,0x08,0x0a,0x04,0x0c,0x03,0x0f,
+ 0x27,0x0a,0x09,0x02,0x06,0xe6,0xe6,0x09,0x02,0xe5,0x0c,0x07,0x0a,0xe5,0x02,0x03,
+ 0x06,0x0e,0x04,0x02,0x05,0x08,0x04,0x0c,0x02,0x03,0x0b,0x01,0x02,0x02,0x04,0xe5,
+ 0x04,0x05,0x0d,0x10,0x04,0x11,0x18,0x09,0x06,0x12,0x14,0x01,0x03,0x01,0xe5,0x0b,
+ 0x02,0x09,0x01,0x09,0x07,0x09,0x01,0x08,0x0d,0x10,0x01,0x05,0x12,0x02,0x0c,0x02,
+ 0x06,0x0a,0x03,0x01,0x01,0x09,0x07,0x0b,0x0b,0x09,0x25,0x09,0x1d,0x01,0xe6,0x0b,
+ 0x01,0x02,0x10,0x11,0xe7,0x05,0x01,0x02,0x04,0x01,0x01,0x06,0xe6,0x04,0x01,0x01,
+ 0x07,0xe5,0x01,0x04,0xe7,0x05,0x05,0x03,0x06,0xe5,0x01,0xe5,0x01,0x05,0x01,0xe5,
+ 0xe5,0x05,0xe5,0x03,0x03,0xe5,0x0f,0x01,0xe6,0xe5,0x04,0x01,0xe5,0x01,0x03,0x01,
+ 0x07,0xe5,0x03,0x03,0x09,0x03,0x05,0xe6,0x01,0xe5,0x02,0xe5,0x02,0x22,0xe5,0xe5,
+ 0x05,0xe5,0x03,0x05,0x01,0x0c,0x01,0x12,0x07,0x0a,0x06,0x03,0xe5,0x01,0x09,0x02,
+ 0xe5,0x09,0x1d,0x02,0x04,0x01,0x02,0x09,0x09,0x0c,0xe5,0x02,0x0c,0x02,0x0f,0xe5,
+ 0x04,0x09,0x06,0x03,0x0b,0xe5,0x08,0x16,0x02,0xe5,0x02,0x04,0x25,0x05,0x09,0x02,
+ 0x01,0x0b,0x09,0x05,0x02,0x04,0x01,0x04,0x01,0x02,0x01,0x04,0x02,0x0a,0x01,0x05,
+ 0x06,0x02,0x02,0x02,0xe5,0x03,0xe7,0xe5,0x01,0x01,0x01,0x08,0x06,0x03,0x05,0x02,
+ 0xe5,0xe5,0x06,0x02,0xe5,0x02,0x04,0x08,0x0c,0x03,0x01,0x06,0x02,0x1b,0x05,0x01,
+ 0xe6,0x01,0xe5,0x0d,0x11,0xe5,0x08,0x04,0x01,0x01,0x07,0x0b,0x0e,0x02,0x03,0x08,
+ 0x06,0x03,0x05,0x01,0x07,0x09,0x03,0x05,0xe6,0x0a,0x0b,0x10,0xe6,0xe5,0x03,0x07,
+ 0x01,0xe5,0x09,0x0b,0x0e,0x05,0x27,0xe8,0xe5,0x1a,0x08,0xe5,0x12,0x06,0x03,0x08,
+ 0x02,0x0a,0xe5,0x03,0x09,0x03,0x01,0x07,0xe5,0x02,0xe5,0x03,0x0a,0x13,0x05,0x0d,
+ 0x13,0x01,0x06,0x2e,0x26,0x03,0x01,0x0b,0xe5,0x01,0xe5,0x08,0x01,0x09,0x04,0x04,
+ 0x09,0x06,0x0c,0x04,0x04,0x07,0x0a,0x05,0x0e,0x08,0x05,0x03,0x0c,0x09,0x06,0x08,
+ 0x09,0x09,0x09,0x08,0x02,0x08,0x26,0xe5,0x07,0x01,0x10,0xe5,0x03,0xe5,0xe5,0x01,
+ 0x03,0x02,0x05,0x02,0xe5,0x08,0x05,0x03,0x05,0x02,0xe5,0x07,0xe5,0x04,0x02,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,
+ 0x09,0xe5,0x07,0x06,0x02,0x07,0x02,0x08,0xe5,0x07,0x0a,0x06,0x01,0xe5,0x07,0xe5,
+ 0x05,0x02,0x08,0xe5,0x07,0x09,0x06,0x0a,0x05,0x01,0xe8,0x07,0xe5,0xe5,0x01,0xe5,
+ 0x07,0xe5,0x04,0x02,0xe5,0xe6,0x04,0xe5,0x04,0x03,0x0a,0xe6,0x03,0x01,0xe5,0x07,
+ 0x05,0x02,0xe5,0xe6,0x05,0x05,0x04,0xe6,0x04,0xe5,0x07,0xe5,0x14,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x0b,0xe5,0x05,0x02,0x01,0x04,0x05,0x02,0xe5,0x08,0x08,0xe5,0x08,
+ 0x02,0xe5,0x05,0x08,0xe5,0x06,0xe5,0x13,0xe5,0x01,0xe6,0x01,0x01,0x08,0xe6,0x0a,
+ 0x05,0x02,0x03,0xe5,0xe6,0x07,0x03,0x05,0x0d,0x01,0xe5,0x05,0x05,0x02,0x02,0xe5,
+ 0x06,0x04,0x06,0x01,0x04,0x05,0xe5,0x01,0x02,0xe5,0x10,0x02,0x01,0x03,0x03,0x01,
+ 0x03,0x06,0xe5,0x07,0xe6,0x03,0x01,0xe6,0x07,0x03,0x05,0xe5,0xe5,0x09,0x02,0x01,
+ 0x07,0x01,0x0d,0x0a,0x11,0x01,0x03,0x02,0x04,0x05,0xe5,0xe5,0x02,0xe5,0x0d,0x0b,
+ 0x01,0x05,0x05,0xe5,0x07,0xe5,0x01,0x01,0x04,0x01,0xe5,0x01,0x06,0x04,0x01,0xe5,
+ 0xe5,0xe5,0xe5,0x04,0x06,0x01,0xe5,0xe5,0x08,0x03,0xe5,0x03,0xe5,0x1b,0x01,0x09,
+ 0x04,0xe5,0xe5,0xe5,0xe5,0x06,0x01,0x05,0x04,0x06,0x15,0x2f,0x05,0x02,0x02,0x07,
+ 0xe5,0xe5,0xe5,0x10,0x09,0x09,0x09,0x06,0x02,0x01,0x07,0xe5,0xe5,0x05,0x06,0xe5,
+ 0xe5,0xe5,0x06,0x09,0x01,0x07,0x06,0x03,0xe6,0x1b,0x01,0x07,0x06,0xe5,0xe5,0xe5,
+ 0x06,0x09,0x09,0x49,0x02,0xe5,0x01,0x0d,0x01,0x11,0x0b,0x03,0x02,0xe5,0x03,0x09,
+ 0x01,0xe6,0x04,0x04,0x01,0xe5,0xe5,0x03,0x0e,0x04,0x04,0x10,0x05,0xe6,0x03,0x0b,
+ 0x04,0x01,0x02,0x09,0x06,0x03,0x02,0xe5,0xe5,0x01,0x01,0x01,0x02,0x02,0x03,0xe5,
+ 0x0a,0x02,0x01,0x01,0x0f,0x09,0x09,0x1f,0xe6,0xe5,0x01,0x0a,0x01,0x01,0x0f,0x03,
+ 0x05,0x03,0x01,0x02,0xe5,0x02,0x09,0x09,0x05,0x01,0x02,0x04,0x03,0x09,0x05,0x04,
+ 0x08,0x05,0x03,0x03,0x01,0x02,0x12,0x01,0x01,0x09,0x05,0x03,0x01,0x02,0xe5,0xe5,
+ 0xe5,0x04,0x03,0x02,0xe7,0x02,0x05,0x03,0x01,0x02,0x40,0x03,0x02,0xe5,0x0b,0x01,
+ 0x02,0x0e,0x0b,0x07,0x04,0x04,0x03,0x02,0x02,0x01,0x01,0x05,0x09,0x09,0x01,0x01,
+ 0xe5,0xe5,0x01,0x09,0x01,0x09,0x07,0x01,0x01,0xe5,0x0f,0x01,0x07,0x01,0x01,0x07,
+ 0x07,0x01,0x01,0x07,0x07,0x0b,0x04,0x1a,0x02,0x01,0x04,0x02,0x1c,0x02,0x01,0x01,
+ 0xe5,0x09,0x01,0x11,0x09,0x09,0x03,0xe5,0xe5,0x01,0x04,0xe7,0xe5,0xe5,0x01,0x04,
+ 0x04,0x04,0x06,0x01,0xe5,0xe5,0x01,0x02,0x01,0x09,0x01,0x07,0x09,0x01,0xe5,0xe7,
+ 0x07,0xe5,0xe5,0x01,0x01,0x01,0xe5,0x03,0x01,0x02,0x04,0x09,0x01,0x02,0x04,0x03,
+ 0xe5,0x03,0x09,0x03,0xe8,0x0e,0xe5,0x08,0x01,0x01,0x05,0xe7,0x1e,0xe5,0x30,0x06,
+ 0x04,0x04,0x02,0xe5,0x04,0x1d,0x0c,0xe5,0x11,0x02,0x03,0x02,0x08,0x04,0x04,0x09,
+ 0x13,0x02,0x06,0x0c,0x02,0x03,0x13,0x09,0x09,0x22,0x02,0x14,0x1d,0xe6,0x02,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x11,0xe5,0x07,0xe5,0x15,0x05,0xe5,0x03,0x05,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x0b,0x05,0xe5,0x01,0xe6,0x02,0xe5,0x0b,0x05,0xe5,0x11,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x1f,0xe5,0x01,0xe5,0xe5,0x06,0x01,0x02,0x02,0xe6,0xe5,0x01,
+ 0x09,0x09,0x02,0x06,0xe5,0x04,0x02,0xe6,0x06,0xe6,0x03,0x02,0xe6,0x06,0x09,0xe6,
+ 0x06,0xe5,0xe5,0x05,0x09,0x04,0xe6,0x01,0xe5,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,
+ 0xe6,0x03,0x02,0x03,0x05,0xe6,0x06,0xe5,0x02,0x01,0x02,0x05,0x03,0xe5,0x07,0x09,
+ 0xe5,0x07,0xe6,0x06,0xe6,0x06,0x09,0x06,0x04,0x01,0xe6,0x01,0x02,0x09,0x09,0x24,
+ 0x02,0x10,0x34,0x26,0x02,0x06,0x02,0x6c,0x05,0x02,0x03,0x0b,0x08,0x24,0x03,0x37,
+ 0x0c,0x17,0x04,0x09,0x02,0x0a,0x19,0x13,0x13,0x34,0x02,0xe5,0xe5,0x0a,0x01,0x06,
+ 0x02,0x11,0x01,0x09,0xe7,0x03,0x01,0xe7,0x02,0xe5,0xe8,0x05,0xe7,0x02,0x02,0x06,
+ 0x02,0xe7,0x0c,0x02,0x07,0x01,0x06,0x03,0x01,0x03,0x04,0xe7,0x05,0xe5,0xe5,0x05,
+ 0xe7,0x03,0x01,0x04,0x02,0x01,0xe7,0x05,0xe7,0x02,0xe5,0xe5,0x09,0xe6,0x10,0x01,
+ 0x06,0xe7,0xe5,0x04,0x01,0x15,0x0d,0x0d,0x01,0xe5,0x05,0x02,0x03,0x0c,0x01,0xe5,
+ 0x07,0xe6,0x03,0xe5,0x01,0xe5,0x04,0x01,0xe6,0x04,0x02,0xe5,0x06,0xe5,0x07,0xe6,
+ 0x01,0x04,0xe6,0x06,0xe5,0x05,0x01,0xe5,0x05,0x02,0xe5,0xe5,0x06,0xe6,0x06,0xe6,
+ 0x04,0x02,0xe5,0x04,0x01,0xe5,0x05,0x01,0xe6,0x01,0x04,0xe6,0x04,0x01,0xe5,0x02,
+ 0x06,0x13,0x04,0x02,0xe6,0x08,0x19,0xe5,0x02,0x01,0x02,0xe5,0x0e,0x09,0x0d,0x0c,
+ 0x02,0x01,0x07,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe5,0x01,0x05,0x09,0xe5,0x05,0x06,
+ 0x04,0x07,0x01,0x07,0x0a,0x02,0x01,0x01,0x05,0x04,0x04,0x07,0x01,0x09,0xe5,0x07,
+ 0xe5,0x05,0x01,0x0b,0x16,0x04,0xe5,0x2a,0xe8,0x0c,0x05,0x01,0xe6,0x06,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x01,0x05,0xe5,
+ 0x01,0x05,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x03,
+ 0x04,0xe6,0x01,0x03,0xe8,0x01,0x03,0xe7,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x03,
+ 0xe8,0xe5,0x04,0xe5,0x05,0xe7,0x07,0xe5,0x06,0xe6,0x01,0x03,0xe7,0x05,0xe7,0x07,
+ 0xe5,0x07,0xe7,0x02,0x01,0x01,0x01,0x10,0x02,0x05,0x0a,0x06,0x01,0xe5,0x07,0xe5,
+ 0x08,0x1c,0xe6,0x06,0xe6,0x06,0xe5,0x07,0x07,0x01,0x09,0xe5,0x09,0xe5,0x04,0x02,
+ 0x06,0x02,0xe5,0x04,0xe5,0xe6,0x08,0x08,0xe5,0x04,0xe5,0xe6,0x08,0x05,0x03,0x09,
+ 0x05,0x02,0x06,0x03,0xe5,0x03,0x1b,0x02,0xe5,0x0f,0x04,0x01,0x13,0x01,0x09,0xe5,
+ 0xe5,0x08,0x09,0x09,0x06,0x09,0x02,0x04,0x01,0xe5,0xe5,0x05,0x07,0x01,0x07,0x01,
+ 0xe5,0xe5,0x07,0xe5,0xe5,0x02,0x02,0x02,0xe5,0xe7,0x03,0x03,0xe5,0xe5,0x0b,0x06,
+ 0x02,0xe5,0xe7,0xe6,0x0a,0xe5,0xe6,0x02,0x09,0x01,0x06,0x02,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x1c,0x01,0x0f,0x09,0x0a,0x09,0x08,0x0a,0x1c,0x09,0x13,0x09,0x12,0x02,0x04,
+ 0x04,0x04,0xe5,0x02,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x02,0xe5,0x02,0x0a,
+ 0x03,0xe5,0x11,0x04,0x04,0xe5,0x07,0xe5,0x1c,0x02,0x0d,0x02,0x02,0x03,0x0c,0x09,
+ 0x08,0x27,0xe5,0x07,0x07,0x0b,0xe5,0x05,0x01,0x09,0x0b,0x04,0x04,0x03,0x03,0x09,
+ 0x01,0xe5,0x07,0x09,0x03,0x03,0x01,0xe5,0x0b,0x06,0x12,0x03,0x09,0x1f,0xe7,0x0f,
+ 0x10,0x01,0xe5,0x0f,0x01,0xe5,0x05,0xe5,0xe5,0xe5,0x08,0x04,0x09,0x01,0xe6,0x09,
+ 0x04,0x01,0xe6,0x18,0xe5,0xe6,0x18,0x0f,0x17,0x01,0x17,0xe5,0x15,0x26,0xe8,0xe5,
+ 0x0e,0x01,0x07,0x01,0x04,0x02,0xe6,0x06,0x01,0x01,0x05,0x01,0x01,0x02,0x02,0x01,
+ 0x01,0x05,0x01,0x01,0x01,0x03,0x01,0xe5,0x02,0x02,0x01,0xe5,0x05,0x01,0x02,0x01,
+ 0x02,0x01,0xe5,0xe5,0x03,0x01,0x01,0x05,0xe7,0x01,0x03,0xe7,0x07,0x01,0xe6,0x04,
+ 0x01,0xe5,0xe5,0x03,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x02,0x01,0x02,0x01,
+ 0x07,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0xe6,0x01,0x04,
+ 0x01,0x07,0x01,0x02,0x08,0x02,0x0d,0x05,0x05,0x03,0x05,0x01,0x08,0x03,0x03,0xe6,
+ 0x08,0x08,0xe6,0x01,0x04,0x01,0x09,0x04,0x04,0x07,0xe6,0xe5,0x04,0x04,0x04,0xe5,
+ 0xe5,0x02,0x02,0x02,0x05,0x02,0xe7,0x05,0xe5,0xe5,0x05,0x03,0x05,0xe5,0x01,0xe5,
+ 0x03,0xe5,0x04,0x03,0x02,0x05,0xe5,0x02,0xe5,0x02,0xe5,0x01,0x05,0x09,0xe6,0x0a,
+ 0x05,0xe5,0x07,0xe5,0x16,0x02,0xe6,0x0a,0x0c,0x06,0x02,0x06,0x01,0x07,0xe5,0x04,
+ 0x02,0xe5,0x03,0x04,0x08,0x02,0x06,0x15,0x04,0x05,0x03,0x04,0x03,0x0d,0x03,0x07,
+ 0x01,0xe5,0x09,0xe5,0xe5,0x01,0x02,0x04,0x03,0xe5,0xe5,0x04,0x07,0x03,0x08,0x04,
+ 0x05,0x05,0x01,0x08,0x04,0x0d,0x1b,0x02,0x01,0x26,0x07,0x08,0x13,0x06,0x03,0x01,
+ 0x13,0x06,0x0c,0x06,0x01,0x06,0x03,0x08,0x01,0x01,0x0c,0x02,0x06,0xe5,0x0b,0xe6,
+ 0x08,0x02,0x01,0x02,0xe5,0x05,0x14,0x02,0x02,0xe5,0x09,0x01,0x07,0x01,0x0f,0x08,
+ 0xe5,0xe6,0x07,0x02,0x01,0xe6,0x04,0x05,0x02,0x09,0x18,0x0b,0xe5,0x05,0x04,0x01,
+ 0x14,0x05,0x12,0x04,0xe7,0x05,0x05,0x0b,0xe5,0x0d,0x07,0xe5,0xe5,0x08,0x06,0x01,
+ 0x18,0x0f,0x0a,0x16,0x08,0xe5,0x02,0x02,0x0b,0x17,0x03,0x08,0x0c,0x03,0x0f,0x0e,
+ 0x10,0x04,0x11,0x01,0x05,0x05,0x05,0x16,0x1b,0xe5,0x02,0x01,0x35,0x0b,0x0f,0x02,
+ 0xe5,0xe6,0x18,0xe5,0x08,0x17,0x04,0x03,0xe5,0x03,0x04,0x08,0x13,0x04,0xe5,0x0c,
+ 0x04,0xe5,0x06,0x07,0x01,0x04,0x04,0x0d,0xe5,0x04,0xe5,0x04,0xe6,0x03,0x02,0x04,
+ 0xe5,0x08,0x03,0x04,0xe5,0x0c,0x01,0x0c,0xe5,0x07,0xe5,0x16,0x09,0x04,0x01,0x09,
+ 0x0a,0xe6,0x20,0x05,0x08,0x0c,0x0c,0x06,0x06,0x02,0x09,0x06,0x06,0x06,0xe5,0x09,
+ 0x10,0x0b,0x03,0x0c,0x09,0x01,0x07,0x04,0x13,0x04,0x09,0x01,0x26,0x12,0x06,0x04,
+ 0x09,0x06,0xe5,0x0a,0x06,0x16,0x07,0x01,0x06,0x01,0x05,0x05,0xe5,0x06,0x04,0x02,
+ 0x0e,0x1c,0x0a,0x05,0x02,0x04,0x02,0x07,0x08,0x1a,0x02,0x04,0x09,0x1f,0xe6,0x01,
+ 0x08,0x02,0x09,0x08,0xe6,0x11,0x01,0x05,0xe6,0x0a,0x02,0x03,0xe5,0x11,0xe6,0x06,
+ 0xe5,0x08,0x01,0x07,0x02,0x02,0x09,0x02,0x04,0x02,0x03,0xe7,0x01,0x03,0xe6,0x02,
+ 0x03,0xe6,0x02,0x03,0xe6,0x02,0x02,0xe6,0x01,0x03,0xe7,0x06,0x09,0xe6,0xe5,0x04,
+ 0xe6,0x0b,0x05,0xe5,0x22,0xe5,0xe6,0x0d,0x09,0x03,0x06,0x0b,0x03,0x03,0x09,0x06,
+ 0x08,0x01,0xe5,0x01,0x12,0x01,0x04,0x02,0xe5,0x06,0x09,0x0e,0x02,0x05,0x08,0xe5,
+ 0x02,0x03,0x08,0x02,0x08,0x06,0xe5,0x03,0x03,0x01,0x0e,0x04,0x07,0xe5,0x14,0x21,
+ 0xe8,0xe5,0xe5,0x0e,0x05,0x18,0x04,0x04,0x03,0x03,0x01,0x04,0x04,0x0b,0x25,0xe7,
+ 0xe5,0x05,0xe5,0xe5,0x07,0x03,0x02,0xe6,0x02,0x02,0xe5,0x06,0x05,0x01,0x06,0x07,
+ 0x01,0x04,0x07,0x01,0x02,0x01,0x0b,0x0d,0x01,0x0d,0x1f,0x04,0x02,0xe5,0x07,0x06,
+ 0x08,0x05,0x0f,0x07,0xe5,0x01,0x06,0x02,0x05,0x25,0x01,0x17,0x05,0xe6,0xe5,0x0d,
+ 0x02,0x0a,0x0a,0x0d,0x07,0xe5,0x03,0xe5,0xe5,0x07,0xe6,0x0e,0x0b,0x01,0xe5,0x12,
+ 0x14,0xe5,0xe5,0x01,0x06,0x10,0x03,0x07,0x01,0x06,0x05,0x01,0x14,0x0a,0x38,0x0f,
+ 0x04,0xe5,0x01,0xe5,0xe5,0x0f,0x19,0x01,0x15,0x06,0x33,0x03,0xe5,0xe8,0x0a,0x02,
+ 0xe5,0xe6,0x04,0xe5,0x01,0x01,0x03,0xe5,0x07,0x03,0xe5,0x04,0x07,0x01,0x02,0xe5,
+ 0x02,0x02,0x08,0xe7,0x04,0x02,0xe5,0x05,0x07,0x03,0xe5,0x05,0xe5,0x06,0xe5,0x07,
+ 0xe5,0x0b,0x07,0xe5,0x07,0xe5,0x01,0xe5,0x07,0xe5,0x04,0x0c,0xe5,0x04,0x12,0xe5,
+ 0x1b,0xe5,0x1d,0x02,0x01,0xe5,0x01,0x01,0x05,0x01,0xe5,0x01,0x0d,0xe5,0x11,0x01,
+ 0x04,0x09,0x13,0x01,0xe5,0x07,0xe5,0x01,0xe5,0x15,0x05,0x02,0x06,0x03,0x07,0xe5,
+ 0x02,0x04,0x02,0x03,0xe5,0x03,0x01,0x01,0xe5,0xe6,0x03,0xe5,0x01,0xe5,0x07,0x06,
+ 0xe5,0x04,0x05,0x0c,0x1d,0x1c,0x01,0x02,0xe5,0xe6,0x03,0x08,0x0d,0x09,0x02,0x01,
+ 0xe5,0xe5,0x17,0x01,0xe5,0x1e,0x01,0x02,0x01,0xe5,0x01,0x1a,0x0d,0x04,0x01,0xe5,
+ 0x03,0x10,0x09,0x01,0x0a,0x29,0xe5,0xe5,0x05,0xe5,0xe5,0x19,0xe5,0x02,0x04,0xe5,
+ 0xe6,0x01,0x0a,0x1d,0x01,0x18,0x02,0x1d,0x09,0xe5,0x01,0x0f,0x06,0x0e,0x06,0xe5,
+ 0x14,0x09,0x09,0x13,0x1a,0x02,0x06,0x02,0x1a,0x06,0x05,0xe5,0x0c,0x09,0x01,0x20,
+ 0x04,0x01,0x02,0x02,0x06,0xe5,0x01,0x05,0x10,0x02,0x01,0x01,0xe5,0xe6,0xe5,0x08,
+ 0x04,0x05,0x01,0xe5,0x05,0x02,0x04,0x02,0x03,0x07,0x01,0xe5,0xe5,0x02,0x02,0x02,
+ 0x02,0xe5,0x01,0x02,0x02,0x03,0xe5,0x04,0x02,0xe5,0xe5,0x01,0x04,0x1b,0x01,0x07,
+ 0x01,0x1b,0x07,0x01,0xe5,0xe5,0x01,0x0a,0x03,0x05,0x01,0x01,0x13,0x0f,0x01,0x01,
+ 0x05,0x03,0x04,0x14,0x03,0x05,0x01,0x15,0x02,0x01,0xe5,0x02,0x07,0x04,0xe5,0xe7,
+ 0x02,0x09,0x04,0xe5,0x02,0x04,0xe5,0x02,0x02,0xe6,0x03,0x02,0x01,0xe5,0xe5,0xe5,
+ 0x08,0x04,0x14,0x03,0x05,0x03,0x1d,0x02,0x03,0xe5,0x0b,0x04,0x04,0x01,0x11,0x01,
+ 0x0c,0x04,0x01,0x01,0x01,0xe5,0x05,0x03,0x17,0x04,0x01,0xe5,0x05,0x01,0x0a,0x04,
+ 0x04,0x05,0xe5,0x05,0x07,0x06,0x01,0xe5,0xe5,0x01,0x02,0x03,0x04,0xe5,0x02,0x04,
+ 0x02,0x09,0x01,0x07,0x07,0x43,0x02,0x01,0x02,0x0a,0x09,0x01,0x11,0x01,0x04,0x01,
+ 0x04,0xe5,0x03,0x01,0x02,0x01,0x02,0x04,0x01,0x01,0x04,0xe7,0x0b,0x03,0xe5,0xe5,
+ 0x01,0x03,0xe5,0xe5,0x05,0xe5,0x19,0x06,0x01,0x14,0x03,0xe5,0x01,0x01,0x03,0xe5,
+ 0xe6,0x0a,0x01,0x01,0xe5,0x4d,0xe5,0x04,0x01,0x1b,0x1a,0x09,0x04,0x04,0x02,0xe5,
+ 0x04,0x13,0x04,0x09,0x04,0x22,0x1a,0x09,0x04,0x0e,0x20,0x02,0x2e,0xe5,0xe5,0xe5,
+ 0x1d,0x01,0x17,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x1b,0xe5,0x03,0x11,0x05,0xe5,0x07,0xe5,0x0b,0x05,0xe5,0x0b,0x13,0x09,0x09,
+ 0x20,0xe6,0xe5,0x0b,0x02,0x01,0x01,0x02,0x03,0xe5,0xe5,0x01,0x09,0x09,0xe5,0x07,
+ 0xe7,0xe5,0xe5,0x01,0xe6,0x03,0x02,0xe5,0x07,0x04,0x01,0x02,0xe5,0xe5,0xe5,0xe5,
+ 0x01,0xe5,0x07,0xe5,0x01,0x05,0x09,0x0b,0xe5,0x07,0x09,0x03,0x05,0xe5,0x07,0xe5,
+ 0x07,0x05,0x03,0xe5,0x07,0x05,0x03,0x09,0x05,0x03,0x03,0x05,0x05,0x03,0x09,0x04,
+ 0x01,0x06,0xe5,0xe7,0x01,0x45,0x06,0x16,0x09,0x13,0x09,0x15,0x1d,0x09,0x13,0x13,
+ 0x09,0x09,0x1d,0x04,0x02,0x03,0x39,0x0d,0x0f,0x0c,0x06,0x03,0x0f,0x01,0x09,0x0e,
+ 0x04,0x01,0x1b,0x02,0x06,0x01,0x11,0x01,0x13,0x09,0x09,0x1f,0x09,0x01,0xe5,0xe5,
+ 0x14,0x01,0x09,0x13,0xe7,0x06,0xe6,0x03,0x01,0xe5,0xe5,0x05,0xe7,0x0a,0x01,0x02,
+ 0xe7,0xe5,0x03,0xe7,0x03,0x01,0xe7,0x0a,0x0b,0x02,0x03,0x0e,0xe5,0x0a,0xe7,0x05,
+ 0xe7,0x0f,0xe7,0x16,0xe5,0xe5,0x06,0x10,0x1d,0x01,0x01,0x17,0x01,0xe5,0x05,0x02,
+ 0x12,0xe6,0x08,0x04,0xe5,0x01,0xe5,0x01,0x02,0x02,0xe5,0x0e,0x02,0xe5,0x07,0xe5,
+ 0xe5,0x01,0xe5,0xe7,0x01,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,0x06,0xe6,0x06,
+ 0xe5,0x02,0x02,0x02,0x03,0x04,0xe6,0x01,0x02,0x02,0xe5,0x01,0x05,0x05,0x02,0xe6,
+ 0x03,0x03,0x10,0x01,0xe5,0x04,0x02,0xe5,0x08,0x21,0xe5,0xe6,0x16,0x01,0x03,0x05,
+ 0x03,0xe5,0x0d,0x0b,0x02,0x04,0x09,0xe5,0x11,0xe5,0x02,0x01,0x02,0xe5,0x24,0x02,
+ 0x01,0x02,0x08,0xe5,0x03,0x09,0xe5,0x07,0x01,0x07,0x09,0xe5,0x07,0x11,0x01,0x09,
+ 0x09,0x03,0x1f,0x01,0xe5,0x14,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x01,0xe5,0x03,
+ 0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x02,0x04,0xe6,
+ 0x04,0xe6,0xe5,0x04,0xe6,0x04,0x04,0xe6,0x01,0x03,0xe5,0xe5,0x01,0x04,0xe6,0x01,
+ 0x03,0x01,0xe6,0x06,0xe6,0x04,0xe6,0x02,0x03,0x01,0xe6,0x04,0xe6,0x08,0xe6,0xe5,
+ 0x04,0xe6,0x04,0xe5,0xe6,0x04,0xe6,0x08,0xe5,0x07,0xe5,0x06,0x03,0x04,0x12,0x01,
+ 0xe5,0x07,0xe5,0x08,0x08,0xe5,0x08,0x12,0xe6,0x10,0xe6,0x06,0x07,0x01,0xe5,0x07,
+ 0xe5,0x01,0xe6,0x02,0xe6,0xe7,0x02,0x02,0x08,0xe6,0xe6,0x08,0x04,0x09,0xe5,0x07,
+ 0xe5,0x01,0xe6,0x02,0x09,0xe5,0x01,0xe6,0x09,0xe5,0xe6,0x0b,0xe5,0x03,0x03,0xe6,
+ 0x03,0x1a,0xe5,0x16,0x01,0xe5,0x05,0x02,0x12,0xe5,0xe5,0x06,0x01,0x09,0x03,0xe5,
+ 0x03,0x0e,0x04,0x09,0x04,0x01,0xe5,0xe5,0x0c,0x09,0x02,0x04,0x03,0x09,0x09,0x02,
+ 0x02,0x02,0x01,0x02,0x01,0x04,0x02,0x05,0x02,0x02,0x02,0x01,0x08,0x0a,0x01,0xe5,
+ 0x0e,0xe5,0x07,0x08,0x13,0xe7,0x16,0x01,0x09,0x0a,0x08,0x1d,0x13,0x09,0x13,0xe5,
+ 0x03,0x03,0x05,0x02,0x02,0xe5,0x02,0x01,0x02,0x05,0xe5,0x08,0x02,0x03,0x05,0x0f,
+ 0x03,0x03,0x06,0x04,0x0d,0x0f,0xe5,0x07,0x04,0x18,0x02,0x10,0x06,0x01,0xe5,0x05,
+ 0x02,0x09,0x08,0x18,0x01,0xe5,0x0b,0x06,0x20,0x02,0x06,0x02,0x05,0x06,0x05,0x02,
+ 0x06,0x03,0x04,0x03,0x03,0x0c,0x02,0x05,0x0a,0x02,0x0a,0x02,0x01,0xe5,0x0c,0x09,
+ 0x05,0x02,0x14,0xe8,0x02,0x0b,0xe5,0x32,0x04,0x02,0x24,0x02,0x10,0x09,0x15,0x03,
+ 0xe5,0x03,0x01,0xe5,0x19,0x03,0x0f,0x1b,0x05,0x05,0x25,0x02,0x01,0x0f,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0xe6,0x04,0x01,0xe5,0xe5,0x03,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0x01,0x05,0x01,0xe5,0xe5,0x03,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x01,
+ 0x03,0x01,0x03,0x03,0x01,0x09,0x01,0xe5,0x02,0x02,0x01,0x04,0x02,0x01,0x01,0x05,
+ 0x01,0xe5,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x03,0x03,0xe6,0xe5,0x04,0x01,0x07,
+ 0x01,0x01,0x05,0x01,0x03,0x03,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x06,0x2d,
+ 0xe5,0x07,0x01,0x07,0xe6,0x01,0x02,0xe6,0x03,0x04,0xe5,0xe5,0x07,0xe5,0x09,0x03,
+ 0xe5,0x09,0x05,0x03,0xe5,0x01,0x05,0x03,0x04,0x02,0xe6,0xe5,0x1e,0x08,0xe5,0x0c,
+ 0x09,0x21,0x10,0x03,0x15,0xe7,0x01,0x08,0x03,0x05,0x13,0xe5,0x07,0x0a,0x08,0x0a,
+ 0x08,0x0d,0x02,0xe5,0x0a,0x02,0x05,0x02,0x05,0x04,0x06,0x03,0x04,0x0b,0x14,0x08,
+ 0x11,0x01,0x0a,0x09,0x03,0x02,0x02,0x09,0x0b,0x13,0x04,0x01,0x02,0x01,0x0a,0x09,
+ 0x06,0x0a,0x04,0x05,0x02,0x02,0xe5,0x05,0xe5,0x07,0x02,0x06,0x02,0x01,0x0b,0x04,
+ 0x0b,0x08,0x05,0x02,0x04,0x07,0x03,0x01,0x17,0x0c,0x06,0x08,0x06,0x0a,0x01,0x08,
+ 0x1e,0x21,0xe5,0xe5,0x26,0x07,0xe5,0x06,0x03,0x05,0x08,0x1f,0x18,0xe5,0x08,0xe5,
+ 0x07,0x03,0xe5,0x02,0xe5,0x03,0xe5,0x04,0xe7,0x02,0x05,0x03,0x0a,0x01,0x02,0x03,
+ 0x05,0xe5,0x04,0x02,0x10,0xe6,0x06,0x06,0x02,0x01,0x0f,0x06,0x01,0x08,0xe5,0x01,
+ 0xe5,0x1c,0x0b,0x27,0x25,0x09,0x06,0x0a,0x04,0xe5,0x01,0x04,0x02,0x04,0x02,0xe5,
+ 0x01,0x06,0x07,0x01,0x0e,0x13,0x0c,0x04,0x0a,0x0a,0x03,0x01,0x0f,0x08,0x04,0x01,
+ 0x09,0x1d,0x09,0x05,0xe5,0x07,0x04,0x02,0x01,0xe5,0xe5,0x07,0x03,0x04,0xe6,0x04,
+ 0xe5,0x08,0x05,0x0d,0x04,0x01,0x06,0x03,0x17,0x03,0x13,0x05,0x02,0x10,0x02,0x1e,
+ 0x03,0x01,0x0d,0x09,0x09,0x02,0xe6,0x11,0x08,0x12,0x06,0x08,0xe5,0x01,0x06,0x0c,
+ 0x0d,0x02,0x04,0x04,0x04,0x01,0x01,0x07,0x01,0xe7,0x01,0xe5,0x01,0x11,0x01,0x05,
+ 0x06,0xe5,0x07,0x03,0xe5,0x03,0x01,0xe5,0x05,0xe6,0x09,0x06,0xe6,0x02,0x02,0x05,
+ 0x07,0x0f,0xe7,0x05,0x1f,0x03,0x0e,0x1d,0x04,0x02,0x20,0x09,0x05,0x20,0x09,0x04,
+ 0xe5,0x04,0x0b,0x02,0x07,0x01,0x03,0x02,0x09,0x0b,0x23,0x27,0x0f,0x1b,0x08,0x06,
+ 0xe6,0x06,0xe5,0x06,0x10,0x03,0xe6,0xe5,0x01,0x02,0x05,0xe5,0xe7,0xe5,0x01,0x04,
+ 0x0b,0x06,0xe5,0x0d,0x01,0x01,0x01,0xe5,0x06,0xe6,0xe5,0x04,0x08,0x05,0x0b,0x03,
+ 0xe5,0xe6,0xe5,0x02,0xe5,0x01,0x06,0x1c,0xe5,0x2c,0xe5,0x01,0x25,0x07,0x07,0xe5,
+ 0x01,0x0e,0x0d,0x06,0x0b,0x06,0x03,0xe5,0x02,0x0a,0xe5,0xe5,0x02,0x0d,0x03,0x09,
+ 0x01,0x1d,0x05,0x02,0x06,0xe5,0x09,0x18,0x02,0xe5,0x06,0x04,0x1c,0x05,0x01,0x01,
+ 0x01,0x19,0x09,0x09,0x06,0x01,0xe6,0x03,0x03,0x05,0x03,0x0c,0x02,0xe5,0x05,0xe6,
+ 0x01,0x06,0x03,0x01,0x0e,0x09,0x09,0xe5,0x02,0x02,0x01,0x04,0x03,0x01,0x04,0x0e,
+ 0x04,0x01,0x07,0x09,0x05,0x02,0xe5,0x07,0x09,0x09,0x05,0xe5,0x20,0x02,0xe6,0x06,
+ 0x01,0x0f,0x01,0x24,0x01,0xe5,0x05,0x0b,0xe5,0x01,0x02,0xe5,0x01,0x06,0x01,0x07,
+ 0x02,0x0c,0x10,0x03,0x02,0xe6,0xe6,0x11,0x01,0x0e,0xe5,0xe5,0x13,0x07,0x24,0xe6,
+ 0x17,0x06,0x03,0x01,0xe5,0x01,0x0e,0x13,0x1c,0x09,0x0c,0x05,0x09,0x0a,0x0a,0x14,
+ 0x05,0x29,0x16,0x04,0x10,0x07,0x18,0x1f,0xe6,0x07,0xe5,0x02,0xe6,0x0b,0xe5,0x0a,
+ 0x02,0xe6,0x03,0x02,0xe5,0x01,0xe5,0x01,0xe5,0xe6,0x04,0x03,0x01,0xe5,0xe5,0xe7,
+ 0x04,0x02,0xe5,0xe6,0x01,0x03,0x06,0x02,0xe5,0x06,0x02,0xe5,0x05,0x02,0x01,0x06,
+ 0xe5,0x07,0x01,0xe5,0x01,0x03,0x02,0x01,0xe5,0x03,0x01,0xe5,0x03,0xe8,0x04,0xe5,
+ 0x08,0x09,0x09,0x09,0xe5,0xe6,0x02,0x01,0x02,0xe5,0x04,0x02,0x01,0x04,0x02,0xe5,
+ 0x0a,0x02,0xe5,0x09,0x01,0xe6,0xe5,0x01,0x01,0x05,0xe5,0x1e,0x02,0x06,0x02,0x06,
+ 0x03,0x02,0x01,0xe5,0x08,0x09,0x02,0x02,0xe5,0x01,0xe6,0xe5,0x05,0x02,0x0b,0xe5,
+ 0x04,0x03,0xe5,0x07,0x01,0x01,0xe6,0xe5,0x02,0x01,0xe5,0x01,0x03,0x01,0xe5,0x0e,
+ 0xe5,0x08,0xe5,0x03,0x0a,0x08,0x03,0xe5,0x04,0x09,0x02,0x01,0x03,0x03,0x01,0x03,
+ 0x10,0x03,0x07,0x01,0x02,0xe8,0x03,0x0c,0x19,0x09,0x05,0xe5,0x08,0x01,0x05,0x04,
+ 0x01,0x01,0x05,0x04,0x04,0x01,0x09,0x02,0x26,0x07,0x06,0x01,0x03,0x0a,0xe5,0x07,
+ 0x0f,0x01,0x43,0x0b,0x04,0x02,0xe5,0x01,0x28,0x09,0x09,0x06,0xe5,0xe5,0x08,0x01,
+ 0x07,0x05,0xe5,0x01,0x05,0xe5,0x2a,0xe5,0x08,0x05,0xe5,0x02,0x02,0x20,0xe5,0xe5,
+ 0xe5,0x42,0x0d,0x02,0xe5,0x01,0x01,0x03,0x25,0x09,0x01,0x0c,0xe5,0x01,0x05,0xe5,
+ 0x01,0xe5,0x08,0x09,0x01,0x02,0x09,0xe5,0x01,0x0a,0x01,0x02,0x09,0x08,0x02,0xe5,
+ 0x01,0xe5,0x03,0x07,0x01,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x09,0x04,0x01,0x02,
+ 0x09,0x09,0x09,0x04,0x01,0x02,0x0e,0x0f,0xe6,0xe6,0x01,0x28,0x03,0x05,0x01,0x01,
+ 0x09,0x09,0x05,0x03,0x05,0x03,0x05,0x01,0x01,0x09,0x0f,0x01,0x01,0x11,0x03,0x05,
+ 0x03,0x08,0x01,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x09,0x05,0x01,0x01,
+ 0x23,0x01,0x01,0x0f,0x03,0x09,0x02,0xe5,0x01,0x02,0x02,0x0c,0x18,0x09,0x01,0x07,
+ 0x05,0xe5,0x01,0x06,0x02,0x01,0x02,0x04,0x04,0x01,0x02,0x01,0x01,0xe5,0x05,0x04,
+ 0x07,0x04,0x01,0x03,0xe5,0x08,0x06,0x01,0xe5,0x03,0x13,0x01,0x07,0x01,0x03,0xe5,
+ 0x01,0x01,0x03,0xe5,0x01,0x01,0x07,0x01,0x04,0x01,0x18,0x05,0x01,0x04,0x0c,0x09,
+ 0xe5,0x03,0x04,0x2b,0x09,0x01,0x07,0x03,0xe5,0xe5,0xe6,0x02,0xe5,0x01,0x01,0x01,
+ 0x07,0x05,0xe6,0xe5,0xe5,0x01,0x06,0x01,0xe5,0x01,0x08,0x01,0xe5,0xe5,0xe6,0xe5,
+ 0xe5,0x03,0xe8,0x02,0x04,0x04,0x03,0xe5,0x06,0x06,0x01,0x07,0x01,0x04,0x01,0xe5,
+ 0xe5,0xe6,0x03,0x01,0x01,0xe7,0x01,0x01,0x01,0xe5,0xe5,0x05,0xe7,0x05,0xe7,0x06,
+ 0x01,0x02,0x01,0x01,0xe5,0xe7,0x09,0x09,0x07,0xe7,0x08,0x31,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x1a,0x09,0x13,0x09,0x0b,0x09,0x0c,0x1a,0x09,0x09,0x04,0x04,0x09,0x09,
+ 0x04,0x04,0x20,0x03,0xe5,0xe5,0x07,0x01,0x2f,0x05,0xe5,0x01,0x05,0xe5,0x03,0x17,
+ 0xe5,0x07,0xe5,0x01,0x0f,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x17,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x21,0x01,0xe5,
+ 0x07,0x05,0x09,0x09,0x09,0x09,0x05,0xe5,0x01,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,
+ 0x06,0x02,0x09,0xe6,0x03,0x02,0xe5,0x01,0x05,0x09,0xe5,0x02,0x01,0x02,0xe5,0x09,
+ 0xe6,0x03,0x02,0xe5,0x04,0x02,0xe5,0x02,0x01,0x02,0x09,0x09,0xe5,0x04,0x02,0xe5,
+ 0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0x06,0x02,0x02,0x0a,
+ 0x03,0xe5,0x01,0x3a,0xe5,0x07,0xe5,0x07,0x07,0x02,0x12,0xe5,0x2f,0x02,0x08,0xe5,
+ 0x08,0x1a,0x02,0x12,0xe5,0x2f,0xe5,0x08,0x04,0x02,0x03,0x3d,0x05,0x03,0x05,0x0d,
+ 0x13,0x05,0x13,0x09,0x06,0x08,0x05,0x02,0x06,0x03,0x19,0x03,0x05,0x09,0x03,0x05,
+ 0x09,0x13,0x0d,0x07,0x0e,0x35,0x01,0x09,0xe7,0x05,0xe7,0x03,0x01,0x07,0x01,0x07,
+ 0x02,0xe6,0x06,0xe6,0x02,0xe5,0xe5,0x03,0x01,0xe5,0xe8,0xe5,0x03,0xe7,0x07,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x03,0x02,0xe5,0x03,0x0c,0x04,0x05,0xe6,0x05,0xe7,0xe5,0x04,
+ 0xe6,0x05,0xe7,0x06,0xe6,0x06,0xe6,0xe5,0x03,0xe7,0x0f,0x0f,0xe7,0x34,0x01,0xe5,
+ 0x04,0xe5,0xe7,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x02,0xe5,0x07,
+ 0xe5,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x02,0xe5,0x01,0x01,0x04,0xe6,0x03,0xe5,
+ 0x01,0xe5,0x04,0x02,0xe5,0x07,0x08,0xe5,0x09,0x05,0x02,0xe5,0x08,0x05,0x02,0xe5,
+ 0x08,0x09,0x04,0x02,0xe6,0x0e,0x02,0x0d,0xe5,0x01,0xe5,0x33,0x01,0x04,0x06,0x02,
+ 0x09,0x02,0x01,0x04,0x02,0x01,0x06,0xe5,0x01,0x03,0x05,0x06,0x01,0x07,0x01,0x01,
+ 0x07,0x08,0x02,0x03,0x05,0x09,0x13,0x03,0x07,0x04,0x02,0xe5,0x01,0x07,0x04,0x02,
+ 0x01,0x09,0x01,0xe5,0x05,0x07,0x10,0x02,0x03,0x0c,0x01,0xe5,0x07,0x0b,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe6,0x01,0x04,0xe6,0xe5,0x04,0xe6,
+ 0xe5,0x04,0xe6,0x06,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x02,0xe5,0xe6,0x01,0x02,
+ 0xe6,0x04,0x04,0xe7,0x04,0xe8,0x01,0x04,0x09,0xe5,0x01,0x05,0xe5,0x05,0xe8,0x06,
+ 0xe5,0x05,0xe8,0x06,0xe5,0x07,0xe5,0x05,0xe7,0x01,0xe5,0x01,0xe7,0x07,0xe6,0x06,
+ 0xe5,0x06,0xe6,0xe5,0x34,0x01,0x14,0x08,0xe5,0x07,0xe6,0x04,0x0b,0xe6,0x07,0x12,
+ 0xe5,0x03,0x05,0x06,0x02,0x06,0xe5,0x01,0xe5,0x06,0xe5,0x07,0xe6,0x0d,0x02,0xe6,
+ 0x07,0x05,0x02,0x1a,0x02,0xe6,0x03,0x1b,0xe6,0xe5,0x34,0x01,0x0c,0x09,0x04,0x02,
+ 0x06,0x01,0x07,0x04,0x04,0x01,0x02,0x13,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x04,0x02,
+ 0x01,0x01,0xe5,0x03,0xe5,0xe6,0x01,0x02,0x03,0xe5,0x0a,0x0c,0xe5,0xe7,0x03,0x09,
+ 0xe5,0xe7,0x03,0x09,0x09,0xe5,0xe6,0x01,0x02,0x01,0xe6,0x1a,0x01,0xe6,0x4b,0x08,
+ 0x09,0x07,0x16,0x0d,0xe6,0x01,0xe5,0x02,0xe5,0x01,0x02,0x09,0x04,0xe5,0x02,0x09,
+ 0xe5,0x07,0x0e,0xe5,0x02,0x0a,0x03,0xe5,0x02,0x18,0xe5,0x02,0x03,0x01,0x1d,0xe7,
+ 0x01,0x21,0x2e,0x02,0x06,0x01,0xe5,0x05,0x09,0x0c,0x0c,0x03,0x05,0x07,0x04,0x02,
+ 0x05,0x05,0x04,0x02,0x02,0x08,0xe5,0x0b,0x03,0x0f,0x03,0x19,0x05,0x04,0x05,0x19,
+ 0x01,0xe5,0x26,0xe5,0x01,0x01,0x0a,0x05,0x02,0x06,0x02,0x10,0x09,0x01,0xe5,0x05,
+ 0x02,0x15,0x15,0x04,0x02,0x09,0x04,0x2d,0x38,0x01,0xe5,0x0b,0xe6,0xe5,0x10,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0xe6,0x04,0x01,0xe5,0xe5,0x01,0x01,0x01,0xe6,0x02,
+ 0x01,0x01,0xe5,0x05,0x01,0xe5,0x04,0xe5,0xe5,0x02,0x03,0x01,0xe5,0x03,0x01,0x01,
+ 0xe6,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x07,0x01,0x01,0x01,0x03,0x01,
+ 0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,
+ 0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x06,0xe7,0x0c,0xe5,
+ 0x01,0x37,0x06,0xe5,0x01,0x05,0xe5,0x0b,0x04,0x0a,0x03,0x02,0x02,0xe5,0x01,0x05,
+ 0xe5,0x11,0xe5,0x03,0x02,0x02,0x07,0x01,0x01,0x05,0x01,0xe5,0x07,0x03,0x12,0x06,
+ 0x01,0x03,0x03,0xe5,0x07,0x02,0x07,0xe5,0x15,0x06,0x07,0xe5,0x0e,0xe7,0x0e,0x03,
+ 0x0b,0x13,0x08,0x02,0xe5,0x02,0x02,0xe5,0x02,0x01,0x02,0x06,0x02,0x03,0x09,0x06,
+ 0x05,0x04,0x04,0x0f,0xe5,0x04,0x05,0x10,0x01,0x06,0x09,0x04,0x16,0x03,0x12,0x07,
+ 0x1b,0xe5,0x0e,0x02,0x02,0xe6,0x1b,0x12,0xe5,0x02,0x06,0x02,0x0c,0x02,0x19,0x04,
+ 0x04,0x03,0x06,0x01,0x0f,0x02,0x05,0x04,0xe5,0x02,0x01,0x01,0x01,0x01,0x09,0x06,
+ 0x0c,0x02,0xe5,0x06,0x03,0x06,0x02,0x06,0x02,0x11,0x1e,0x01,0x0e,0xe6,0xe6,0x11,
+ 0x06,0x09,0xe5,0x10,0x04,0x02,0x01,0x06,0xe5,0xe6,0x02,0x04,0x07,0xe6,0x0a,0x05,
+ 0x01,0xe5,0x02,0xe5,0xe5,0xe6,0x02,0xe5,0xe5,0xe5,0x10,0x0e,0x04,0x03,0x07,0xe5,
+ 0xe5,0x02,0x06,0x01,0x1e,0x06,0x0d,0x1f,0x01,0x0d,0x01,0x02,0x1b,0x0b,0x01,0x0c,
+ 0x04,0x15,0x02,0x04,0x08,0x19,0x01,0x07,0x01,0x11,0x08,0x13,0x1a,0x17,0x24,0x01,
+ 0x0d,0x0c,0x05,0xe5,0x07,0x05,0x0d,0x13,0x0f,0x03,0x04,0xe5,0x02,0x05,0x07,0x06,
+ 0x04,0x03,0x07,0x15,0x07,0x01,0x03,0x04,0x0c,0x01,0x01,0x05,0x09,0x01,0x05,0x0b,
+ 0x0b,0x17,0x0d,0x17,0x0f,0x03,0xe5,0x0c,0x04,0xe5,0x11,0x07,0x0b,0x04,0x09,0x02,
+ 0x06,0x13,0xe7,0x03,0x04,0x09,0x09,0x0f,0x08,0x1a,0x09,0x13,0x0b,0x07,0x04,0x01,
+ 0x18,0x04,0x01,0x07,0x01,0xe5,0x0c,0x03,0x2f,0x0a,0x10,0x0f,0x07,0x14,0x07,0x01,
+ 0x07,0x01,0x07,0x04,0x0f,0x03,0x12,0x07,0x1f,0x07,0x09,0x12,0x19,0x02,0x04,0x02,
+ 0x08,0x30,0x06,0x07,0x06,0x02,0xe7,0x06,0xe5,0x03,0x01,0x02,0x04,0x07,0x01,0x09,
+ 0x03,0xe5,0x03,0x03,0xe5,0x04,0x01,0xe5,0x01,0x04,0xe5,0xe5,0x11,0x02,0x02,0xe5,
+ 0x04,0x06,0x01,0xe5,0x07,0xe5,0x06,0xe5,0xe5,0x05,0x0a,0xe6,0x06,0xe6,0x07,0x10,
+ 0xe5,0x10,0x03,0x03,0x3c,0x10,0x03,0x01,0x04,0xe6,0x01,0x06,0x1a,0xe5,0x02,0x08,
+ 0x01,0x05,0x02,0x0c,0x04,0x04,0x07,0x06,0x03,0x04,0x01,0x02,0x06,0x01,0x04,0x15,
+ 0x02,0x08,0x09,0x05,0x15,0x09,0x01,0xe5,0x01,0x06,0x04,0x02,0x14,0x09,0x07,0x01,
+ 0xe5,0x03,0x03,0x0f,0x06,0x08,0x03,0xe5,0x0e,0x03,0x02,0x03,0xe6,0x02,0x04,0x04,
+ 0x0b,0x07,0x02,0xe5,0x06,0x06,0x1d,0x01,0x1a,0x1d,0xe5,0x07,0x0e,0xe5,0x01,0x01,
+ 0x01,0x0b,0x01,0x2f,0x01,0x11,0x01,0x09,0x04,0x01,0xe5,0x06,0x01,0x01,0x08,0x01,
+ 0x09,0x03,0x05,0x0b,0x11,0x1c,0x16,0x09,0x06,0x1d,0x09,0x0e,0x03,0x10,0x0b,0x08,
+ 0x1c,0x13,0x12,0x01,0x0b,0x08,0x20,0x1b,0x09,0x07,0x17,0x07,0x08,0x01,0x18,0x01,
+ 0x07,0x01,0x0f,0xe5,0xe7,0x0a,0x19,0xe5,0x04,0xe5,0x01,0xe5,0x03,0x0a,0xe5,0xe6,
+ 0xe5,0x03,0xe6,0x05,0x01,0xe5,0x01,0x02,0xe6,0x03,0x03,0x05,0x01,0xe6,0xe6,0x01,
+ 0x02,0xe5,0xe6,0x01,0x05,0xe5,0x05,0xe5,0x07,0xe9,0x01,0x05,0xe5,0x0b,0x01,0x01,
+ 0x02,0xe5,0xe5,0x02,0x05,0x03,0x08,0xe5,0x08,0x05,0x06,0xe5,0x04,0x01,0xe5,0x05,
+ 0x09,0x1e,0xe6,0xe5,0xe5,0x01,0x01,0x08,0xe5,0x18,0xe5,0x07,0xe5,0x0d,0x03,0x01,
+ 0xe5,0x04,0xe5,0x04,0x02,0xe5,0x01,0x02,0x06,0xe7,0x02,0xe5,0xe6,0x03,0xe5,0x01,
+ 0x05,0xe5,0x01,0x05,0xe5,0x10,0x01,0x01,0x01,0xe5,0x03,0x01,0x01,0x05,0x01,0xe5,
+ 0xe5,0x01,0x03,0xe5,0xe5,0x02,0x05,0x03,0xe5,0x07,0x09,0x05,0x05,0xe5,0x07,0xe5,
+ 0x05,0x09,0x05,0xe5,0x08,0xe5,0x08,0x01,0x02,0xe8,0x03,0x04,0xe5,0x01,0x01,0x0e,
+ 0xe5,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,0xe5,0x01,0x01,0x01,0x02,
+ 0x04,0x01,0x03,0x03,0x01,0x02,0x07,0x05,0xe5,0x01,0x01,0x07,0x01,0x01,0x05,0x03,
+ 0x05,0x04,0xe6,0x01,0x01,0x01,0xe7,0x03,0x01,0x07,0x09,0x01,0x07,0x09,0x09,0x1d,
+ 0x06,0x01,0xe5,0x02,0xe5,0x13,0xe5,0x03,0x09,0x09,0x06,0xe6,0x01,0x07,0x02,0x01,
+ 0x0e,0x02,0x01,0x07,0x01,0x07,0x01,0x04,0x04,0x04,0xe5,0x01,0x02,0x02,0x04,0x07,
+ 0x09,0x01,0x07,0x09,0x09,0x09,0x01,0x09,0x01,0x07,0x06,0xe5,0xe5,0xe5,0x06,0x09,
+ 0x09,0x1d,0x06,0x02,0x19,0xe5,0x01,0x0b,0x0b,0x03,0x02,0x0b,0x01,0x01,0x0f,0x1d,
+ 0x03,0x02,0xe5,0x01,0xe5,0x01,0x01,0x02,0x03,0x02,0xe5,0x01,0xe5,0x0a,0x02,0x01,
+ 0x01,0xe5,0xe5,0x02,0x02,0xe5,0x08,0x04,0x09,0x10,0x04,0x09,0x04,0x04,0x04,0x04,
+ 0x04,0x04,0x13,0x04,0x07,0x06,0x01,0x01,0x05,0x09,0x06,0x02,0xe5,0x01,0xe5,0xe5,
+ 0x01,0x0f,0x02,0x0a,0x01,0x01,0x04,0x0e,0x09,0x09,0x09,0x04,0xe5,0x03,0x08,0x04,
+ 0xe5,0x02,0x05,0x01,0x01,0x04,0xe5,0x02,0x04,0xe5,0x02,0x05,0x03,0x09,0x0b,0x05,
+ 0x03,0x09,0x05,0x03,0x05,0x03,0x05,0x03,0x19,0x03,0x05,0x03,0x01,0x02,0x14,0x04,
+ 0x01,0x01,0xe5,0xe5,0x01,0x08,0x02,0x02,0xe6,0x0b,0x01,0x05,0x0b,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x04,0x01,0x02,0xe7,0xe5,0x08,0x01,0xe5,0x01,0x01,0x09,0x01,0x04,
+ 0xe7,0xe5,0x04,0x01,0x04,0x01,0x02,0x09,0x01,0x09,0x01,0x07,0x09,0x01,0x01,0x01,
+ 0xe5,0x01,0x09,0x09,0x06,0x13,0x01,0xe5,0x0c,0x09,0x09,0x02,0x02,0x01,0x07,0x01,
+ 0x0d,0xe9,0x0c,0x01,0x11,0x01,0x07,0x01,0x07,0x01,0x05,0x06,0x01,0x02,0x01,0x02,
+ 0x01,0x07,0x04,0x09,0x01,0x01,0xe7,0x01,0x09,0x05,0xe6,0xe5,0x02,0xe5,0x03,0x01,
+ 0x01,0xe5,0x04,0xe5,0xe5,0x06,0x03,0xe5,0xe5,0xe6,0xe5,0x01,0x01,0x02,0x03,0xe5,
+ 0xe5,0xe6,0x02,0xe5,0x03,0x03,0xe8,0x0e,0xe5,0xe5,0x01,0x09,0x04,0x09,0x09,0x01,
+ 0xe6,0x0b,0x0b,0x02,0xe5,0x01,0x13,0x02,0x2b,0x02,0xe6,0x08,0x04,0x13,0x02,0x02,
+ 0x17,0x09,0x15,0x02,0x06,0x04,0x04,0x09,0x09,0x0c,0xe5,0x04,0x04,0x0e,0x09,0x09,
+ 0x0c,0xe5,0x04,0x02,0x02,0x05,0x01,0x02,0xe5,0xe5,0x11,0xe5,0x25,0x05,0xe5,0x07,
+ 0xe5,0x01,0x05,0xe5,0x01,0xe5,0x04,0x08,0xe5,0x01,0xe5,0x17,0xe5,0x07,0xe5,0x13,
+ 0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x11,0xe5,0x11,0xe5,0x01,0x05,
+ 0xe5,0x07,0xe5,0x0b,0x06,0x02,0x0b,0x01,0xe5,0x08,0x01,0x02,0x04,0x01,0x02,0x09,
+ 0x09,0x09,0x03,0x02,0x02,0xe6,0x06,0xe6,0x02,0x03,0xe6,0x01,0x01,0x02,0x09,0xe5,
+ 0xe5,0x05,0x09,0x09,0xe5,0x07,0xe5,0x06,0x02,0x09,0xe5,0x07,0xe6,0x06,0xe5,0xe5,
+ 0x05,0xe5,0x07,0xe5,0x07,0x09,0xe5,0x07,0x04,0x01,0x02,0xe6,0xe5,0x04,0xe6,0x06,
+ 0xe6,0x06,0x04,0xe6,0x01,0x01,0x03,0x05,0x01,0xe5,0xe5,0xe5,0x01,0x09,0x09,0x26,
+ 0x1e,0x31,0x1f,0x7c,0x04,0x01,0x0a,0x09,0x46,0x05,0x09,0x1d,0x01,0x07,0x06,0x0e,
+ 0x02,0x10,0x09,0x09,0x13,0x48,0xe6,0xe5,0xe5,0x13,0x02,0x1b,0x01,0x0a,0x01,0x03,
+ 0xe5,0xe8,0x02,0x03,0x01,0x0d,0x02,0xe7,0x03,0x01,0x04,0x02,0x01,0x04,0x04,0xe7,
+ 0x05,0xe5,0xe5,0x05,0x01,0x07,0x01,0xe5,0xe5,0xe5,0x03,0xe7,0x03,0x01,0xe7,0x06,
+ 0xe6,0xe5,0x03,0xe7,0x02,0xe5,0xe5,0x03,0x05,0xe6,0x0d,0x01,0xe5,0xe5,0xe5,0x04,
+ 0xe6,0xe5,0x04,0xe6,0x03,0x0c,0x0f,0xe6,0x0f,0x06,0x02,0x17,0x02,0x01,0xe5,0x08,
+ 0xe5,0x04,0x01,0xe6,0x07,0xe5,0x03,0x03,0xe5,0x06,0xe6,0x04,0x01,0xe5,0x05,0x01,
+ 0xe5,0x07,0xe6,0x03,0xe5,0x01,0xe5,0x06,0x01,0xe5,0x02,0x02,0x01,0xe6,0x04,0x02,
+ 0xe5,0x03,0xe5,0xe7,0x01,0x06,0x04,0x02,0xe6,0x01,0x02,0x01,0xe5,0x09,0x02,0x0c,
+ 0x02,0xe5,0x08,0x09,0x05,0x03,0x02,0x05,0xe5,0x04,0xe5,0x02,0x01,0x02,0xe5,0x0c,
+ 0x0b,0x22,0x13,0x16,0x01,0x01,0x05,0x01,0x03,0x02,0xe5,0xe5,0x08,0xe5,0x01,0x05,
+ 0x06,0x01,0xe5,0xe5,0x05,0x09,0x02,0x03,0x03,0x01,0x01,0x0b,0x05,0xe5,0x01,0x11,
+ 0x0c,0x04,0x03,0x09,0x06,0x03,0x02,0x01,0x03,0x09,0x0a,0xe5,0x01,0x15,0xe6,0x06,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe6,
+ 0xe5,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x01,0x03,0xe8,0x04,0xe7,0x01,0x01,
+ 0x04,0xe6,0x05,0xe8,0x01,0x03,0xe7,0xe5,0x04,0xe5,0x02,0x04,0xe5,0x01,0x03,0xe7,
+ 0x07,0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x02,0x02,0xe7,0x05,0xe8,0xe5,0x04,0xe5,
+ 0x07,0xe7,0x02,0x01,0x03,0x04,0x14,0x1b,0x01,0x07,0x01,0xe6,0x0e,0x01,0x09,0x09,
+ 0xe5,0x07,0xe5,0x08,0xe5,0x06,0x09,0xe5,0x0a,0x06,0x01,0x09,0xe5,0x12,0x08,0xe6,
+ 0x04,0x01,0xe5,0x08,0x09,0x09,0x09,0x09,0xe5,0x06,0x19,0x01,0xe5,0x16,0x1d,0x01,
+ 0x07,0x04,0x09,0x04,0x04,0x04,0x04,0x06,0x02,0x06,0x13,0x02,0xe5,0x01,0xe5,0x01,
+ 0x01,0xe5,0x01,0x09,0x01,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0x03,0x03,0x05,0x07,0x01,
+ 0x06,0x02,0xe5,0x01,0xe5,0xe6,0x08,0x01,0xe5,0x01,0x0d,0x01,0x07,0x01,0xe5,0x01,
+ 0x05,0xe5,0x01,0x02,0x01,0x09,0x0c,0x01,0xe6,0x0b,0x0c,0x27,0x13,0x09,0x0a,0x08,
+ 0xe5,0x11,0x04,0xe5,0x02,0x04,0xe5,0x01,0x03,0x0d,0xe5,0x02,0xe5,0x02,0x18,0x04,
+ 0xe5,0x11,0xe5,0x03,0x17,0xe5,0x07,0xe5,0x0a,0x10,0x01,0xe6,0x16,0x20,0x24,0x15,
+ 0xe5,0x08,0x08,0x03,0x01,0xe6,0x04,0x01,0xe5,0x04,0x03,0x01,0x06,0x01,0xe6,0x07,
+ 0x16,0x03,0x01,0xe5,0x02,0x0c,0x01,0xe5,0x02,0x16,0x01,0xe5,0x05,0x01,0xe5,0x1c,
+ 0x01,0x0d,0x02,0x03,0x13,0x16,0x02,0x04,0x01,0x02,0x06,0x02,0x06,0xe5,0xe6,0x02,
+ 0x01,0x02,0xe5,0x04,0x02,0x06,0x02,0xe6,0x03,0x03,0x1b,0xe5,0xe5,0x0f,0x09,0x09,
+ 0xe5,0xe5,0x19,0x0b,0xe5,0x09,0x0f,0x02,0x03,0x02,0x02,0x04,0x05,0x06,0x01,0x0c,
+ 0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x02,0x02,0x01,
+ 0xe5,0x02,0x02,0x01,0xe6,0xe5,0x02,0x01,0xe6,0xe5,0x02,0x01,0x03,0x03,0x01,0x04,
+ 0x02,0x01,0x06,0xe5,0xe5,0x02,0x03,0x01,0x07,0x01,0x09,0x01,0x01,0x01,0x03,0x01,
+ 0x02,0x04,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe5,0x02,0x02,0x01,0x03,0x03,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x07,0xe6,0xe5,0x04,0x01,0x01,0x05,0x01,
+ 0x02,0x03,0xe7,0xe5,0x01,0x02,0x01,0x0a,0xe6,0xe5,0x0c,0x04,0x17,0x14,0x01,0x06,
+ 0xe5,0xe6,0x05,0x01,0x11,0x01,0x03,0x02,0xe5,0xe5,0xe5,0x04,0xe5,0x10,0x02,0x08,
+ 0x02,0xe5,0x01,0xe5,0x03,0xe5,0x07,0x02,0x08,0x01,0x05,0x09,0xe5,0x01,0xe5,0x0d,
+ 0xe5,0x02,0x04,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x05,0xe5,0x01,0x05,0x01,0xe5,0x04,
+ 0x07,0xe5,0x01,0xe5,0x0a,0x04,0x04,0x06,0x02,0x06,0x09,0x02,0x03,0x02,0x02,0x04,
+ 0x01,0x05,0x01,0x04,0x06,0x02,0x06,0x01,0x03,0x03,0x05,0x01,0x08,0x0b,0x01,0x04,
+ 0x02,0x01,0x04,0x01,0x03,0x03,0x07,0x1c,0x04,0x06,0x08,0x03,0x12,0x02,0x07,0x09,
+ 0x10,0x01,0xe5,0xe5,0x0a,0x01,0xe7,0xe6,0x08,0x23,0x0a,0x02,0x01,0x08,0x02,0x01,
+ 0x03,0x01,0x0c,0x13,0xe5,0xe5,0x08,0x0f,0x05,0x0a,0x02,0x02,0xe5,0x05,0x0d,0x05,
+ 0x02,0x04,0x04,0x0e,0x09,0x01,0x11,0x09,0x17,0x0c,0xe5,0x01,0x10,0xe5,0xe5,0x05,
+ 0x09,0x09,0x1c,0x07,0xe5,0x06,0x02,0x05,0x03,0xe5,0x05,0x01,0x07,0xe6,0x09,0x0b,
+ 0x06,0x01,0xe5,0x01,0x02,0x03,0x09,0x06,0x06,0x06,0x0d,0x21,0x1d,0x07,0x01,0xe5,
+ 0x07,0xe5,0x02,0xe5,0x01,0x25,0x01,0x01,0x07,0x2b,0x06,0x02,0x0b,0x04,0x09,0x09,
+ 0x0c,0xe5,0xe6,0x0e,0x09,0x04,0x04,0x0a,0x27,0xe5,0x0e,0x0b,0x07,0x01,0x01,0x01,
+ 0x0d,0xe6,0x01,0x13,0x1f,0x0c,0xe5,0x02,0x03,0x03,0x0a,0x0a,0x0d,0x01,0x07,0x03,
+ 0x01,0x09,0x09,0xe5,0x01,0x03,0x0e,0x04,0x09,0x0e,0x04,0x0d,0x05,0x03,0x09,0x04,
+ 0xe5,0x1a,0x0a,0xe5,0x0c,0x01,0xe5,0xe5,0xe5,0x0a,0x01,0x03,0xe5,0x06,0x09,0x01,
+ 0x07,0x09,0x04,0x2c,0x04,0x04,0x07,0x09,0x09,0x03,0x04,0x0c,0x03,0x01,0xe5,0x02,
+ 0x05,0x02,0x0b,0x04,0x01,0x04,0x01,0x03,0x03,0x01,0xe5,0xe5,0x05,0x0a,0x01,0x02,
+ 0x09,0x07,0x10,0x02,0x0c,0x02,0x01,0x06,0x01,0xe5,0x28,0x0d,0x01,0x02,0x11,0x0a,
+ 0x02,0x0e,0x02,0x12,0xe5,0x0b,0x11,0x03,0x02,0x05,0x07,0x07,0x07,0x13,0xe5,0x09,
+ 0x1e,0x0f,0x0c,0x01,0x03,0x22,0x0f,0x05,0x05,0xe6,0x07,0xe5,0x01,0xe5,0x0d,0xe5,
+ 0x0d,0x03,0xe7,0x01,0x0a,0x02,0xe6,0xe5,0x03,0xe7,0x05,0xe7,0x03,0x03,0x09,0xe5,
+ 0x08,0xe6,0x06,0xe5,0x06,0x06,0xe5,0x16,0x26,0xe5,0xe5,0x15,0xe7,0xe5,0xe5,0x01,
+ 0x1d,0x16,0x07,0x03,0x02,0xe6,0x01,0xe5,0x0d,0x02,0xe6,0x0f,0x14,0x07,0x08,0x01,
+ 0x13,0x0c,0x01,0x04,0x02,0x03,0x21,0x29,0x03,0x13,0x03,0x01,0x01,0x06,0x02,0x01,
+ 0x09,0x0d,0x08,0xe5,0x05,0x02,0x02,0x01,0xe5,0x0c,0x06,0xe5,0x03,0xe5,0xe5,0x03,
+ 0x0e,0x04,0x01,0x06,0x02,0x0a,0x01,0x08,0x02,0x04,0x12,0xe5,0x03,0x03,0x02,0x06,
+ 0x02,0x02,0xe5,0x01,0x05,0x09,0x11,0x01,0x1c,0x01,0xe5,0xe5,0x05,0x09,0xe6,0xea,
+ 0x0d,0x09,0x27,0x0b,0x04,0x0c,0x0c,0x03,0x02,0x0b,0x09,0xe5,0x01,0x03,0xe5,0xe5,
+ 0x07,0x01,0x1b,0x01,0x0f,0x01,0x07,0x01,0x07,0x01,0x15,0x18,0x07,0x10,0x02,0x03,
+ 0x05,0x04,0x04,0x0a,0x0d,0x13,0x02,0x01,0x0b,0x01,0x0f,0x01,0x02,0x06,0x08,0x1b,
+ 0x09,0x03,0x15,0x07,0x10,0x08,0xe5,0x07,0xe5,0x07,0x0f,0xe5,0x24,0x0c,0x02,0xe7,
+ 0x1b,0xe5,0x03,0xe5,0x01,0xe5,0xe5,0x01,0xe6,0x06,0x0a,0x08,0xe5,0x04,0x02,0xe5,
+ 0x07,0xe5,0x07,0xe5,0xe6,0x05,0x08,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x01,0x04,0xe5,
+ 0xe6,0x03,0x02,0x05,0x02,0xe5,0x04,0x02,0xe5,0x06,0x01,0xe5,0xe5,0xe5,0x01,0xe6,
+ 0x09,0x01,0xe5,0x02,0x13,0x07,0x01,0x04,0x01,0xe5,0x01,0xe5,0x04,0x0c,0xe5,0xe6,
+ 0x01,0x0e,0xe5,0xe6,0xe5,0x01,0x01,0x0a,0x0e,0xe5,0x0a,0x09,0xe5,0x07,0xe5,0x01,
+ 0x08,0x06,0x03,0xe5,0x03,0xe5,0xe5,0x02,0xe5,0xe6,0x01,0x01,0xe5,0x01,0x03,0x08,
+ 0x03,0x01,0xe6,0x02,0xe6,0x0c,0xe5,0x01,0x06,0x09,0x02,0x01,0x07,0x03,0xe5,0x03,
+ 0x06,0x06,0xe5,0x0a,0xe5,0x11,0x06,0x01,0x02,0x09,0x0a,0x03,0xe5,0x02,0x09,0x01,
+ 0x02,0x02,0xe5,0x03,0x0d,0x12,0x05,0x03,0x07,0x02,0x01,0x01,0x07,0xe5,0xe5,0xe5,
+ 0x06,0x0b,0x09,0x0e,0x01,0xe5,0xe5,0x08,0x01,0x05,0x01,0x01,0xe5,0x0f,0x03,0x05,
+ 0x06,0x01,0x02,0x0e,0x01,0xe5,0x0f,0xe5,0xe5,0x12,0x09,0x03,0x05,0x10,0x01,0xe5,
+ 0x0a,0x08,0x02,0x06,0xe5,0x1f,0x09,0x06,0xe5,0x01,0x05,0x02,0x01,0x07,0x09,0x09,
+ 0x09,0x09,0x01,0x07,0x06,0xe5,0xe5,0xe5,0x07,0xe5,0x08,0x09,0x06,0x04,0x0e,0x02,
+ 0x01,0x0e,0xe5,0xe5,0x12,0x0b,0x09,0x13,0x0b,0x02,0x01,0x01,0x13,0x02,0x14,0x0b,
+ 0x06,0x02,0xe5,0xe5,0x01,0x0b,0x0b,0x09,0x0c,0x03,0x0c,0x06,0x05,0x0b,0xe5,0x01,
+ 0xe5,0x08,0x01,0x05,0x03,0x02,0x04,0x01,0x05,0x01,0x04,0x0e,0x04,0x03,0x0a,0x01,
+ 0x07,0x05,0x02,0xe5,0x05,0x01,0x0a,0x04,0x01,0x01,0x07,0x03,0x02,0x0e,0x19,0x03,
+ 0x05,0x03,0x02,0xe7,0x07,0x04,0x05,0x03,0x05,0x03,0x05,0x03,0x04,0x04,0x02,0xe6,
+ 0x03,0x05,0x03,0x03,0x05,0x0b,0x02,0x01,0xe5,0x02,0x05,0x01,0x01,0x09,0x01,0x02,
+ 0xe5,0xe5,0xe5,0x04,0x04,0x01,0x01,0x0a,0x04,0x02,0xe5,0x09,0x01,0x01,0x07,0x01,
+ 0x02,0x01,0x02,0x01,0x01,0x02,0x0a,0x01,0x01,0x01,0x02,0x04,0x04,0xe7,0x24,0x04,
+ 0x0b,0x04,0x01,0xe5,0xe5,0x04,0x01,0x01,0x02,0x04,0x0b,0x09,0x05,0x01,0x09,0x01,
+ 0x09,0x07,0x01,0x01,0x07,0x09,0x04,0x04,0x01,0x02,0x06,0x01,0x05,0x01,0x02,0x04,
+ 0x13,0x04,0x02,0x0b,0x01,0x07,0x09,0x10,0x01,0x04,0x0b,0xe5,0x01,0xe5,0xe6,0x27,
+ 0x09,0x05,0xe5,0x01,0x01,0x01,0xe5,0x03,0x01,0x07,0x05,0xe5,0x01,0x09,0x09,0x03,
+ 0xe5,0x03,0x01,0x07,0x09,0x01,0x02,0xe6,0x02,0xe5,0x02,0xe5,0x03,0x09,0x01,0x0c,
+ 0x01,0x01,0xe5,0xe5,0x06,0x13,0x13,0x01,0x09,0x09,0x0e,0x01,0xe5,0xe5,0x0d,0xe5,
+ 0x01,0x74,0x1d,0x0b,0x02,0xe5,0x07,0x02,0x06,0x02,0x03,0x02,0xe5,0x11,0x02,0x10,
+ 0x02,0x44,0x02,0x14,0x09,0x23,0xe5,0x2f,0xe5,0x01,0xe5,0x17,0xe5,0x09,0xe5,0x01,
+ 0xe5,0x07,0xe5,0x07,0x05,0xe5,0x15,0xe5,0x11,0x45,0xe9,0x0d,0x05,0xe5,0x01,0x05,
+ 0x03,0x09,0x02,0x06,0x06,0x02,0xe5,0x04,0x02,0x09,0x09,0x09,0x02,0x03,0x02,0xe5,
+ 0x07,0x06,0x02,0x09,0xe6,0x05,0x02,0xe5,0x07,0x09,0x05,0x03,0xe6,0x06,0x09,0x09,
+ 0x06,0x02,0x03,0x05,0x09,0x09,0x09,0x09,0x06,0x02,0x0d,0xe9,0x01,0x12,0xe5,0x23,
+ 0x09,0x02,0x26,0xe5,0x11,0x48,0x12,0xe5,0x1c,0x1c,0xe5,0x0d,0x04,0x01,0x15,0x30,
+ 0x28,0x05,0x24,0x04,0x2b,0x13,0x1d,0x1d,0x12,0xe5,0xe6,0x0c,0x01,0x06,0xe5,0xe5,
+ 0x17,0x09,0x01,0x02,0xe7,0x05,0x04,0x02,0x01,0x09,0x07,0x01,0x09,0xe7,0x0f,0x04,
+ 0x04,0xe7,0x07,0xe7,0x03,0x01,0x07,0x01,0x0a,0x01,0x04,0x01,0x04,0x04,0x09,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x1a,0x02,0x0e,0x01,0xe6,0xe5,0x0c,0x01,0xe5,0x05,
+ 0x01,0xe5,0x0c,0x19,0xe5,0xe5,0x02,0x02,0x06,0x01,0xe5,0x07,0xe5,0x05,0x01,0xe5,
+ 0x04,0xe5,0xe7,0x01,0x0c,0x02,0x08,0xe6,0x01,0x01,0x02,0x01,0xe6,0x01,0x02,0x01,
+ 0xe5,0x02,0x02,0x01,0xe5,0x04,0x03,0xe5,0x04,0x01,0xe5,0x05,0x03,0x04,0x02,0xe5,
+ 0x05,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x08,0x12,0x01,0x0c,0x02,
+ 0xe6,0x0a,0xe5,0xe5,0x06,0x01,0x27,0x01,0x01,0x05,0x07,0x01,0x09,0x04,0x02,0x01,
+ 0x03,0xe5,0x12,0x04,0x09,0xe5,0x06,0x06,0x0d,0x01,0x04,0x0c,0x01,0x09,0x04,0x04,
+ 0x09,0x07,0x01,0x07,0x01,0x07,0x10,0x09,0x02,0x10,0xe9,0x07,0x03,0x01,0x05,0xe6,
+ 0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0xe5,0x04,0xe5,
+ 0x01,0x05,0xe6,0xe5,0x04,0xe6,0x01,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x01,0x04,0xe5,
+ 0x02,0x02,0x03,0xe5,0x08,0xe6,0xe5,0x03,0xe6,0x07,0xe6,0xe5,0x04,0xe6,0x04,0xe5,
+ 0xe5,0x01,0x05,0xe6,0xe5,0x02,0xe6,0xe5,0xe5,0x04,0xe6,0xe5,0x02,0x01,0xe5,0x01,
+ 0x03,0xe7,0x05,0xe5,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0x02,0x04,0x04,0x05,0x07,
+ 0x01,0x0a,0x09,0x09,0x08,0x09,0x0a,0xe5,0x06,0x14,0x09,0x08,0xe5,0x07,0xe6,0x01,
+ 0x07,0x06,0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0xe6,0x0e,0x01,0x09,0x14,0x08,
+ 0xe5,0x05,0x05,0xe5,0xe6,0xe5,0x02,0xe5,0x04,0xe5,0x06,0x10,0x01,0x0f,0x07,0x01,
+ 0x0a,0x1f,0x04,0x15,0x14,0x01,0x0e,0x02,0x08,0x02,0x03,0x07,0x03,0xe5,0xe5,0x06,
+ 0x01,0x06,0xe5,0x03,0x0e,0x04,0x01,0x01,0x02,0x0c,0x01,0xe6,0x02,0x08,0x03,0x01,
+ 0x03,0x05,0xe6,0xe5,0x05,0x0a,0x03,0x0d,0xe7,0x0c,0x01,0x07,0x16,0x09,0x08,0x09,
+ 0x13,0x1e,0x08,0x09,0x08,0x03,0x03,0x05,0x09,0x05,0x02,0x13,0x03,0x01,0xe5,0x01,
+ 0x0d,0x01,0x0d,0xe5,0x05,0x07,0x01,0x01,0x05,0xe5,0x0b,0x0e,0x02,0xe5,0x0c,0x01,
+ 0x07,0x01,0x0a,0x09,0x09,0x10,0x0c,0x08,0x0a,0x13,0x06,0x02,0x08,0x04,0x0b,0x05,
+ 0x09,0x03,0x0f,0x0d,0x04,0xe5,0x05,0x06,0x05,0x08,0xe5,0x01,0x05,0x04,0x02,0x01,
+ 0x04,0x05,0x06,0x12,0x01,0xe5,0xe5,0x09,0xe5,0xe5,0x19,0x01,0xe6,0x0c,0x13,0x01,
+ 0x01,0xe6,0x12,0x05,0x02,0x26,0x02,0xe5,0x04,0x13,0x15,0xe5,0x0f,0xe5,0xe5,0x0d,
+ 0x01,0x02,0x0a,0x09,0x0c,0x05,0x0e,0x02,0x0d,0x03,0x01,0x07,0x01,0x01,0x05,0x01,
+ 0x02,0x01,0x02,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0x02,0x04,0x01,0xe5,0x02,0x02,
+ 0x01,0x02,0x04,0x01,0x07,0x01,0x03,0x02,0xe5,0xe5,0x06,0x01,0x07,0x01,0xe5,0x05,
+ 0x01,0x07,0x01,0x01,0x04,0x02,0x01,0x07,0x01,0x02,0x04,0x01,0xe5,0x05,0x01,0x07,
+ 0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0x07,
+ 0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x04,0xe5,0xe5,0x05,0x01,0x01,0x02,0xe5,
+ 0x2c,0xe5,0x07,0x03,0x06,0x12,0x02,0x10,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe5,0x01,
+ 0x08,0x0b,0x03,0x02,0xe5,0x07,0xe5,0x02,0x01,0x02,0xe5,0x01,0x04,0x04,0x0a,0x08,
+ 0x02,0x09,0x04,0x0f,0x02,0x03,0x0a,0x15,0x11,0x01,0xe6,0x09,0x09,0x13,0x01,0x01,
+ 0x05,0x03,0x06,0x01,0x02,0x0d,0x03,0x01,0x03,0x07,0x04,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x08,0x06,0xe5,0xe5,0x02,0x04,0xe5,0x01,0xe5,0xe5,0xe5,0xe5,0x02,
+ 0x02,0x04,0x04,0x03,0x06,0x02,0x1b,0x01,0x09,0x02,0x03,0x2a,0x08,0x02,0x01,0x01,
+ 0x0a,0x09,0x19,0x1e,0x11,0x0e,0x06,0x01,0x0f,0x09,0x09,0x12,0x03,0x0a,0x02,0x0f,
+ 0x17,0x0e,0x17,0x05,0x16,0x01,0xe6,0x0c,0x19,0x1a,0x0f,0xe7,0x0b,0x01,0x02,0x01,
+ 0xe5,0x05,0xe5,0x16,0x01,0x01,0x05,0x06,0x01,0x02,0x0e,0x01,0x07,0x01,0x04,0x02,
+ 0x03,0x03,0x09,0x0d,0x03,0x03,0x01,0x07,0x01,0x0a,0x08,0x05,0x0b,0xe5,0x0e,0x01,
+ 0x01,0x0f,0x2e,0x09,0x0b,0x05,0x0b,0x01,0x01,0x03,0x09,0x06,0x03,0x14,0x01,0x07,
+ 0x0f,0x03,0x01,0x03,0x04,0x03,0x26,0xe5,0x04,0x03,0x11,0x11,0x10,0x01,0x03,0x09,
+ 0x18,0xe5,0x02,0x16,0x07,0x05,0x0c,0x01,0x07,0x04,0xe5,0xe6,0x06,0x04,0x0d,0x11,
+ 0x03,0x01,0x0f,0x09,0x01,0x09,0x03,0x0f,0x07,0x05,0x05,0x07,0x01,0x20,0x12,0x06,
+ 0x01,0x0f,0xe5,0x10,0x09,0x01,0x09,0x01,0x02,0x04,0x0e,0x13,0x01,0x07,0x05,0x08,
+ 0x04,0xe5,0x02,0x03,0x03,0x05,0x02,0xe5,0x02,0x04,0x02,0x02,0x07,0x05,0x04,0x04,
+ 0x0c,0x06,0x02,0x0e,0x01,0x02,0x06,0x38,0x01,0xe6,0x05,0x22,0x17,0x02,0x09,0x04,
+ 0x03,0xe5,0x11,0xe5,0x03,0x03,0xe5,0xe5,0x08,0x04,0x01,0x02,0x0c,0x03,0x01,0xe5,
+ 0x03,0x03,0x02,0x1f,0x04,0x01,0x02,0x0f,0x09,0x20,0xe5,0x0e,0x08,0x03,0x02,0x02,
+ 0x0d,0x1a,0xe5,0x08,0x0c,0x02,0x0b,0x06,0x0a,0x01,0x06,0x02,0xe7,0x02,0x0d,0xe6,
+ 0xe6,0x02,0x01,0x06,0xe6,0x09,0xe6,0x10,0x01,0x07,0xe8,0x06,0x01,0x11,0x0c,0x06,
+ 0x08,0x01,0x07,0xe6,0x21,0xe5,0xe6,0x05,0x1f,0x04,0x01,0x08,0x06,0x05,0x03,0xe5,
+ 0x03,0x01,0xe5,0x09,0xe5,0x03,0x09,0x06,0x10,0xe5,0x01,0x0a,0x01,0x04,0x07,0x03,
+ 0x02,0x11,0x04,0x05,0x04,0x03,0x13,0x13,0x13,0x18,0x0a,0xe5,0xe6,0x08,0x05,0x11,
+ 0x01,0x03,0x09,0x08,0xe5,0x05,0x0f,0x06,0x01,0x06,0xe5,0x01,0x02,0x03,0x03,0x01,
+ 0x06,0x1d,0x0c,0x01,0x03,0x01,0x01,0x01,0x02,0xe6,0x03,0x06,0x02,0x09,0x09,0x03,
+ 0x09,0x05,0x01,0x02,0x04,0x04,0x1c,0x14,0xe9,0x08,0x03,0xe5,0x02,0x0f,0xe5,0x1f,
+ 0x07,0xe5,0x17,0xe6,0x01,0x04,0x01,0x07,0x01,0x18,0x09,0xe5,0x04,0x09,0x09,0x01,
+ 0xe5,0x05,0xe5,0x07,0x01,0x07,0x13,0x01,0x04,0x02,0x04,0x2f,0xe5,0xe5,0x01,0x01,
+ 0x06,0x05,0x13,0x0d,0x1d,0x1e,0x12,0x26,0x09,0x0a,0x09,0x06,0x01,0x01,0x04,0x03,
+ 0x13,0xe5,0x07,0x0c,0x1b,0x0a,0x01,0xe5,0x01,0xe6,0x17,0xe5,0x04,0x03,0x08,0xe5,
+ 0xe6,0x04,0xe5,0x0e,0x02,0xe5,0x04,0x03,0x05,0x06,0xe5,0x04,0xe5,0x03,0x03,0x09,
+ 0x09,0x02,0x01,0x04,0x06,0x04,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0xe5,0x07,0xe5,
+ 0x05,0x01,0xe5,0xe6,0xe5,0x02,0x02,0xe5,0x04,0x07,0x01,0xe5,0xe6,0x04,0x0a,0x0b,
+ 0x01,0x04,0x05,0x06,0x01,0x0f,0x02,0xe7,0x01,0x01,0x16,0x01,0xe5,0x01,0x0c,0x02,
+ 0xe5,0x06,0x04,0xe5,0x04,0xe5,0xe5,0x08,0x03,0x05,0x06,0x01,0xe5,0x08,0x02,0x06,
+ 0x03,0x09,0x02,0x01,0xe6,0x01,0x01,0xe5,0x0a,0x01,0x04,0x02,0x01,0xe5,0x02,0xe5,
+ 0xe6,0x04,0x0b,0xe5,0x01,0x02,0x09,0x09,0x03,0x01,0x03,0x17,0xe5,0x0a,0x05,0xe5,
+ 0x0d,0x01,0x03,0xe7,0x03,0x1c,0x03,0x0c,0xe5,0xe5,0xe5,0xe5,0x0e,0x03,0x01,0xe5,
+ 0x0b,0x0d,0x05,0x06,0xe5,0x02,0x13,0x09,0x03,0x0f,0x06,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x02,0x05,0x06,0x01,0xe5,0x0f,0xe5,0xe5,0x05,0xe5,0x02,0x15,0x05,0x10,0xe5,0x02,
+ 0x06,0xe6,0x01,0x1e,0x10,0x02,0x01,0x04,0x0c,0x13,0x09,0x09,0x06,0xe5,0xe5,0xe5,
+ 0x10,0x05,0xe5,0x03,0x13,0x06,0x02,0x06,0x02,0x09,0x06,0x02,0x10,0x02,0x06,0x04,
+ 0x1b,0x0f,0xe5,0x05,0x04,0x01,0x23,0x02,0x0c,0x09,0x03,0x02,0xe5,0x01,0xe5,0x08,
+ 0x09,0x0b,0x04,0x01,0x02,0x02,0x01,0x01,0x05,0xe5,0x01,0xe5,0xe5,0x01,0x06,0x02,
+ 0x03,0x01,0xe5,0xe5,0x01,0x04,0x01,0x02,0x04,0x04,0x02,0x06,0x02,0x06,0xe5,0x01,
+ 0xe5,0x03,0x02,0x06,0x01,0x01,0x05,0x02,0x06,0xe5,0xe6,0x01,0x02,0xe5,0x01,0x05,
+ 0x09,0x04,0x19,0x01,0xe7,0x01,0x1e,0x04,0x03,0x0e,0x05,0x04,0x03,0xe5,0x02,0x05,
+ 0x09,0x03,0x05,0x01,0x07,0x04,0x04,0x04,0x04,0x01,0x01,0x05,0x03,0x03,0xe5,0x01,
+ 0x01,0x02,0x04,0x01,0x01,0x05,0x03,0x05,0x03,0x05,0x03,0x02,0x01,0xe5,0x02,0x05,
+ 0x03,0x01,0x02,0x0a,0x03,0x09,0x01,0x02,0x14,0x03,0x13,0x02,0x01,0x01,0xe5,0x21,
+ 0x02,0x02,0x0b,0x01,0x02,0x04,0x01,0x04,0xe5,0xe5,0x08,0x01,0x07,0x0b,0x09,0x09,
+ 0x07,0x01,0x03,0xe5,0x03,0x02,0x02,0x03,0x09,0x01,0x07,0x03,0x01,0xe5,0x05,0x09,
+ 0x05,0x06,0x06,0x0b,0xe5,0x05,0x07,0x01,0x09,0x02,0x01,0x04,0x02,0x01,0xe5,0x05,
+ 0x01,0x10,0x01,0x01,0xe5,0x20,0x04,0x0e,0x01,0x07,0x01,0x02,0xe7,0xe5,0x08,0x01,
+ 0x02,0x04,0x09,0x01,0x02,0x04,0x04,0x04,0x01,0x02,0x04,0x01,0x01,0xe5,0xe5,0xe6,
+ 0x02,0xe5,0x05,0x04,0x04,0x01,0x01,0xe5,0x03,0x04,0x01,0x01,0xe5,0x03,0x04,0x04,
+ 0x04,0x03,0xe5,0xe6,0xe5,0x03,0x08,0xe5,0xe5,0x01,0x04,0x09,0x01,0x01,0x05,0x01,
+ 0x07,0x04,0x05,0xe5,0x13,0xe5,0xe5,0x44,0x13,0x27,0x06,0x09,0x15,0x09,0x09,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x04,0x04,0x09,0x04,0x04,0x09,0x02,0xe5,0x04,0x04,0x04,
+ 0x20,0x01,0x02,0x46,0xe6,0x0d,0x04,0x0e,0x16,0x01,0x03,0xe5,0x07,0xe5,0x13,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x20,0xe8,0x0d,0x09,0x09,0x09,0x09,0x06,0x02,0x09,
+ 0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x09,0x03,0x05,0xe5,0x07,0xe5,0x02,0x01,
+ 0x04,0x09,0xe5,0xe5,0x05,0xe6,0x01,0x01,0x02,0xe6,0x06,0xe6,0x06,0xe5,0x02,0x01,
+ 0x02,0xe6,0xe5,0x04,0xe5,0x02,0x01,0x02,0xe6,0xe5,0x01,0x02,0xe6,0x06,0xe6,0x06,
+ 0xe6,0x06,0x09,0x04,0x01,0x06,0x03,0xe5,0x01,0x1d,0x1a,0x13,0x09,0x02,0x06,0x02,
+ 0x06,0x2a,0x51,0x06,0x02,0x31,0x04,0x06,0x1e,0x3a,0x09,0x25,0x09,0x03,0x02,0x0e,
+ 0x27,0x13,0x01,0x0a,0x32,0x0c,0x0f,0x13,0x02,0x0e,0x01,0x07,0x01,0x02,0x01,0x02,
+ 0x01,0x07,0x01,0x02,0x06,0x04,0x04,0x02,0x06,0x02,0x06,0x02,0x04,0x01,0xe7,0x03,
+ 0x01,0xe7,0xe5,0x03,0x01,0x02,0x06,0xe7,0xe5,0x03,0xe7,0xe5,0xe6,0xe8,0xe5,0x01,
+ 0x01,0xe7,0x05,0xe7,0x03,0x01,0xe7,0x03,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe7,0xe5,
+ 0x04,0x01,0x07,0xe6,0x06,0xe6,0xe5,0x1e,0xe6,0x0e,0xe5,0x0f,0x01,0x01,0x0f,0x01,
+ 0xe5,0x05,0x01,0x01,0x05,0x01,0xe5,0x02,0x02,0x01,0x01,0x01,0x03,0x02,0x08,0x01,
+ 0x01,0xe5,0x03,0x01,0x07,0x01,0x05,0x01,0xe6,0x04,0x01,0xe6,0x08,0x01,0x07,0xe6,
+ 0x06,0xe6,0x04,0x02,0xe5,0x04,0x02,0xe5,0x06,0xe6,0x04,0x02,0xe5,0x04,0x01,0xe6,
+ 0x04,0x02,0xe5,0x03,0x03,0xe5,0x08,0x09,0x20,0xe5,0x01,0xe5,0x0d,0x0d,0xe5,0x03,
+ 0x03,0x0d,0x01,0x04,0x04,0x07,0x01,0x03,0x05,0x04,0x04,0x04,0x04,0x09,0x03,0x05,
+ 0x03,0x03,0x01,0x01,0x05,0x01,0xe5,0x06,0xe5,0xe5,0x08,0xe5,0x07,0x09,0x09,0xe5,
+ 0x07,0x01,0x02,0x04,0x03,0x03,0x01,0x09,0x03,0x10,0x0a,0x0c,0x15,0x01,0x0f,0x05,
+ 0xe5,0x05,0x01,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x04,0xe6,0xe5,0xe5,
+ 0x04,0xe6,0x06,0xe6,0x06,0xe5,0x01,0x05,0x03,0x05,0xe5,0x01,0x05,0xe6,0xe5,0x02,
+ 0xe8,0xe5,0x02,0xe7,0x03,0x05,0xe5,0x01,0x03,0xe7,0x01,0xe5,0x02,0xe6,0x02,0x04,
+ 0xe5,0x07,0xe5,0x01,0x03,0xe7,0x02,0x03,0xe7,0xe5,0x02,0xe7,0x02,0x04,0xe5,0x07,
+ 0xe5,0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x07,0x02,0x0f,0x28,0x0e,0x04,0x06,
+ 0x0b,0xe5,0x07,0x09,0x07,0x01,0x0a,0x14,0x09,0x09,0xe6,0x07,0x09,0x08,0x0a,0x03,
+ 0x01,0x03,0xe5,0x07,0x06,0x01,0xe5,0x08,0x09,0x09,0xe5,0x18,0xe5,0x0e,0x0f,0x01,
+ 0x04,0x11,0x0b,0xe5,0x01,0x0c,0x02,0x04,0x09,0x04,0x03,0xe5,0x03,0x04,0x01,0x02,
+ 0x07,0x01,0xe5,0x01,0x05,0xe5,0x01,0x07,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x03,
+ 0x03,0x01,0x09,0x06,0x02,0xe5,0x01,0x05,0x09,0xe5,0x01,0x05,0x04,0x02,0x01,0x09,
+ 0xe5,0x01,0x03,0x01,0xe5,0x01,0x1c,0x01,0xe6,0x0d,0x0d,0x23,0x04,0xe5,0x03,0x12,
+ 0xe5,0x07,0x09,0x18,0xe5,0x07,0xe5,0x01,0x02,0x09,0x04,0xe5,0x02,0x04,0x0f,0x08,
+ 0x04,0xe5,0x03,0x0d,0xe5,0x03,0x08,0x0a,0x03,0xe5,0x07,0xe5,0x1c,0x02,0x03,0x0b,
+ 0x0d,0x03,0x16,0x06,0x05,0x06,0x10,0x02,0x06,0x06,0x02,0x19,0x01,0xe5,0x05,0x01,
+ 0xe5,0x08,0x01,0x02,0x03,0x01,0xe5,0x01,0x06,0x16,0x03,0x01,0xe5,0x0f,0x01,0xe5,
+ 0x19,0x01,0xe5,0x05,0x01,0xe5,0x02,0x09,0x11,0x02,0x39,0x0c,0x04,0x04,0x01,0xe5,
+ 0x05,0x02,0x01,0x04,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x03,0x19,0xe5,0x0f,0x02,
+ 0x06,0x09,0x01,0xe5,0x05,0xe5,0xe5,0x05,0x01,0xe7,0x0d,0x01,0xe5,0x05,0x01,0xe5,
+ 0x19,0x02,0x17,0xe5,0x01,0x10,0xe5,0xe5,0x06,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0xe6,0x06,0x01,0xe6,0xe5,0x02,0x01,0xe6,0x01,0x02,0x01,0xe5,0xe5,0x02,0xe5,0xe5,
+ 0x06,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x07,0xe7,0x04,0xe5,0xe6,0xe5,0x05,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x04,0x02,0x01,0x01,
+ 0x02,0x02,0x01,0x01,0xe5,0x03,0x01,0x01,0x02,0x02,0x01,0x04,0x02,0x01,0x01,0x05,
+ 0x01,0x01,0x05,0x01,0x02,0x02,0x01,0x01,0x01,0x05,0x01,0x0a,0xe5,0xe6,0x09,0x0e,
+ 0xe5,0xe5,0x07,0x0a,0x09,0x08,0x07,0x0a,0x02,0x03,0xe7,0x06,0x08,0x03,0xe5,0x01,
+ 0x02,0x02,0x01,0xe5,0x03,0x01,0x04,0x02,0x01,0x06,0x0c,0x04,0x02,0xe6,0x08,0xe5,
+ 0x01,0x06,0x0b,0x06,0xe5,0x03,0x03,0x09,0xe5,0x12,0x14,0x16,0x03,0xe5,0x14,0xe5,
+ 0xe5,0x05,0x03,0x05,0x08,0x08,0x01,0x0c,0x01,0x04,0x01,0x09,0x02,0x03,0x0a,0x09,
+ 0x05,0x06,0x01,0x07,0x01,0x01,0x0a,0xe5,0x04,0x01,0x01,0x05,0xe5,0x06,0x08,0x03,
+ 0x04,0x05,0x03,0x01,0x0a,0x02,0x0a,0x09,0x04,0x04,0x09,0x14,0x08,0xe7,0xe5,0x1a,
+ 0x04,0x09,0x05,0x03,0x06,0x06,0x05,0x06,0x0c,0x02,0x02,0x09,0x08,0xe5,0x07,0x0a,
+ 0x0a,0x0e,0x06,0x0e,0x07,0x06,0x0f,0x11,0x01,0x10,0x31,0x01,0x21,0x01,0x0a,0x0c,
+ 0x03,0x01,0x01,0x02,0x02,0x09,0xe6,0x03,0x05,0x03,0xe5,0xe7,0x03,0x02,0xe6,0x06,
+ 0xe6,0x06,0x0b,0x04,0xe5,0xe7,0xe5,0x02,0xe5,0x09,0x0b,0x06,0x02,0x13,0x09,0xe5,
+ 0x09,0x07,0x01,0x04,0x1a,0x13,0x01,0xe6,0x01,0x02,0x20,0x19,0x03,0x05,0x04,0x05,
+ 0x01,0x06,0x07,0x0b,0x13,0x03,0x07,0x05,0x02,0xe5,0x03,0x16,0x01,0x03,0x01,0x08,
+ 0x03,0x0a,0x04,0x0e,0x09,0x01,0x01,0x03,0x1f,0x12,0xe6,0xe5,0x08,0x09,0x05,0xe5,
+ 0x05,0x01,0x03,0x05,0x03,0x05,0x04,0x02,0x01,0x01,0x01,0x05,0x09,0x03,0x05,0x07,
+ 0x01,0x07,0x01,0x03,0xe6,0xe5,0xe5,0x02,0xe5,0x03,0x05,0x03,0x07,0x01,0x0f,0x13,
+ 0x05,0x03,0x0a,0x0e,0x03,0x03,0x18,0x10,0x02,0x08,0xe5,0x09,0xe9,0x17,0x09,0x02,
+ 0x06,0x04,0x04,0x09,0x01,0x04,0xe5,0xe5,0xe5,0x06,0x09,0x06,0x02,0x09,0x09,0x01,
+ 0x07,0x01,0x07,0x03,0x06,0x01,0xe5,0x05,0x02,0x02,0x03,0x01,0x01,0x08,0x04,0x01,
+ 0x1d,0x02,0x09,0x04,0x14,0x03,0x06,0xe6,0x15,0x03,0xe6,0x02,0x0e,0x0c,0x10,0x0a,
+ 0x0a,0x09,0x07,0xe5,0x07,0x13,0x01,0x09,0x07,0x01,0x07,0x12,0x01,0x02,0x14,0x64,
+ 0x0b,0x0c,0x09,0xe7,0x02,0x02,0xe6,0x03,0x02,0x09,0xe6,0x01,0xe5,0x02,0xe5,0x03,
+ 0xe5,0x02,0xe5,0x02,0x05,0x10,0xe7,0x02,0x03,0xe6,0x06,0xe6,0x07,0xe6,0x05,0x0a,
+ 0x07,0x11,0xe5,0x02,0xe7,0x02,0x01,0xe7,0x05,0xe5,0xe5,0x01,0xe5,0x02,0xe6,0x01,
+ 0xe5,0x0d,0xe6,0xe5,0x18,0xe5,0x0f,0xe5,0x10,0xe8,0xe5,0x01,0x04,0x07,0x02,0x05,
+ 0x06,0xe5,0x0e,0x05,0x06,0x04,0x07,0x01,0x02,0xe5,0x02,0x03,0xe6,0x0c,0x03,0x02,
+ 0xe5,0x07,0xe5,0x02,0x02,0xe5,0x02,0x02,0x09,0x03,0x20,0x05,0x02,0x01,0x08,0x08,
+ 0x02,0x0a,0x07,0x03,0x1a,0x21,0xe5,0x01,0x02,0x10,0x05,0x03,0x02,0x02,0x03,0x05,
+ 0x03,0x04,0xe5,0x08,0x01,0x01,0x02,0x01,0xe5,0x08,0x04,0x04,0x05,0xe5,0xe6,0x08,
+ 0x04,0x01,0x02,0x03,0x05,0x04,0x04,0xe5,0x02,0x01,0x04,0x04,0xe5,0x06,0xe5,0x03,
+ 0x03,0xe5,0x03,0x03,0x05,0x03,0x02,0x06,0x03,0x01,0x03,0x05,0x18,0x04,0x04,0x03,
+ 0x02,0x02,0x05,0x0b,0x0d,0x01,0xe5,0x16,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0x07,0xe5,
+ 0xe5,0x05,0xe5,0x07,0xe5,0xe5,0xe5,0x03,0xe6,0xe5,0x01,0x02,0xe5,0x01,0x02,0x02,
+ 0xe6,0x03,0x02,0xe6,0x03,0x02,0xe5,0x07,0xe5,0x01,0x02,0x02,0xe5,0x02,0x07,0xe5,
+ 0x07,0xe5,0x04,0x02,0x09,0x01,0x07,0x13,0x09,0x0c,0x09,0x05,0xe5,0x01,0x29,0xe8,
+ 0x17,0x09,0x02,0x06,0x09,0x02,0x06,0x09,0x09,0x02,0x06,0x09,0x09,0x02,0x06,0x02,
+ 0x01,0x02,0x01,0x09,0x03,0x06,0x01,0x02,0x06,0x07,0x01,0x0a,0x09,0x0a,0x07,0x0a,
+ 0xe5,0x01,0x0b,0x0b,0x02,0x09,0x20,0xe5,0x01,0x01,0xe5,0x13,0x03,0x05,0x03,0x02,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x05,0x03,0x05,0x03,0x05,0x03,0x02,0xe5,0xe5,0x02,
+ 0x02,0xe5,0xe5,0x02,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x02,0x01,0x02,0x03,
+ 0xe5,0xe6,0xe5,0x05,0xe5,0x0a,0x03,0xe5,0x08,0x07,0xe5,0x01,0xe5,0x03,0xe5,0xe6,
+ 0x05,0xe5,0x06,0xe5,0x01,0xe5,0x0c,0x07,0x02,0xe5,0x07,0xe5,0x13,0x01,0x01,0xe7,
+ 0xe5,0xe5,0x13,0x01,0x07,0x01,0x07,0x02,0x06,0xe5,0x07,0x01,0x02,0x01,0x02,0xe5,
+ 0x07,0x01,0x01,0xe5,0x03,0x01,0x07,0xe5,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x09,0x04,0x01,0x02,0x04,0x01,0x01,0xe5,0x06,0x03,0x06,0x03,0x08,0x02,0xe5,0x03,
+ 0x07,0x03,0x08,0x02,0xe5,0x11,0x01,0xe5,0x01,0x0a,0x11,0x01,0x02,0x03,0x02,0x01,
+ 0x0f,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x02,0x01,
+ 0x04,0x04,0x04,0x02,0x01,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x02,0x01,0x06,0x01,
+ 0x02,0x04,0x02,0x01,0x02,0x04,0x04,0x06,0x01,0x02,0x04,0x01,0xe5,0xe5,0x01,0x0b,
+ 0x01,0x02,0x01,0x23,0x1f,0x04,0xe6,0xe5,0x01,0x11,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,0x08,0x06,0xe5,0x0a,0x01,0x0e,0xe5,
+ 0x28,0x21,0x03,0x01,0xe7,0x16,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x06,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x01,
+ 0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x06,0x02,0xe5,0x01,0x04,0x02,0x06,0x02,0x04,
+ 0x04,0x04,0x04,0x09,0xe5,0x01,0x19,0xe5,0x01,0x1e,0x09,0x01,0x17,0x04,0x02,0x06,
+ 0x02,0x0a,0x03,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x05,
+ 0x03,0x02,0x01,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x01,0xe6,0x02,0x01,0x01,0xe6,
+ 0x02,0x05,0x03,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x02,
+ 0x01,0x02,0x03,0x04,0xe5,0x02,0x05,0x03,0x05,0x04,0x08,0x09,0x13,0x23,0x03,0x05,
+ 0x01,0x01,0x13,0x04,0xe6,0x01,0x14,0x03,0xe5,0x03,0x03,0xe5,0x03,0x04,0x01,0x01,
+ 0xe5,0x02,0x05,0x03,0xe5,0xe5,0xe6,0x02,0x05,0x03,0xe5,0xe5,0x01,0x03,0x01,0xe5,
+ 0x01,0x09,0x09,0x04,0x04,0x06,0x02,0x0b,0x03,0x02,0xe5,0xe5,0x05,0x04,0x04,0x01,
+ 0xe5,0x05,0x01,0x02,0x04,0x02,0x01,0x13,0x0c,0x18,0x09,0x01,0x11,0xe5,0x03,0x02,
+ 0xe6,0x18,0x02,0x06,0x02,0xe6,0x03,0x01,0xe5,0xe5,0xe5,0x01,0x02,0x06,0x02,0x01,
+ 0x01,0x02,0x02,0x06,0x02,0x01,0xe5,0x02,0x02,0x01,0x04,0x01,0xe5,0x05,0x01,0xe7,
+ 0x03,0x01,0xe7,0x03,0x01,0xe5,0xe6,0x02,0x01,0xe5,0xe5,0xe5,0x03,0x02,0xe7,0x02,
+ 0x01,0xe5,0xe6,0x02,0x01,0xe5,0xe5,0xe6,0x03,0x01,0x04,0x01,0xe8,0xe5,0xe5,0x12,
+ 0x01,0xe5,0xe5,0x1f,0x09,0x01,0x11,0x08,0xe7,0x15,0x02,0x02,0x02,0xe5,0x01,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,
+ 0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x01,0x01,0x02,0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x01,0x04,0x02,0x09,0xe6,0x03,
+ 0x02,0x1a,0x04,0x43,0x01,0xe7,0xe5,0x17,0xe5,0x07,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x06,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x01,0x17,0xe5,
+ 0x01,0x46,0xe5,0xe6,0x0d,0x04,0x01,0xe5,0xe7,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,
+ 0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe7,0x03,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0xe5,0x07,0x01,
+ 0xe7,0x03,0x01,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe5,0xe5,0x05,0xe5,0x03,0x03,0x02,
+ 0x06,0x06,0x02,0xe5,0x01,0x05,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x16,0xe5,
+ 0x08,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x05,
+ 0x02,0x13,0x12,0xe5,0x49,0x02,0xe5,0x01,0x15,0x01,0x09,0x02,0x06,0x02,0xe5,0x04,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x05,0xe5,0x01,0x06,0x02,0xe5,0x04,0x02,
+ 0xe5,0x02,0x05,0x09,0x03,0x13,0x05,0x4c,0x08,0x10,0xe7,0x03,0x02,0xe6,0x03,0x02,
+ 0xe6,0x03,0x02,0xe6,0x02,0xe5,0x01,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,
+ 0xe6,0xe5,0x01,0x02,0xe6,0x03,0x02,0xe6,0x02,0xe5,0x01,0xe6,0x02,0xe5,0x01,0xe6,
+ 0x03,0x02,0xe6,0x05,0x02,0x01,0x04,0x02,0xe6,0x03,0x02,0xe6,0x03,0x01,0x01,0xe5,
+ 0x06,0x01,0x06,0x09,0x0a,0x01,0x1a,0x2d,0x01,0xe5,0x16,0x02,0xe5,0x03,0xe5,0x01,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x01,0x02,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x01,0x02,0x02,0xe5,0x01,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x01,
+ 0xe6,0x01,0x05,0xe5,0x04,0x02,0x08,0xe5,0x08,0xe5,0x1a,0xe5,0x2e,0x1b,0x02,0x04,
+ 0xe5,0x07,0x09,0x03,0x05,0x01,0x07,0x03,0x05,0x01,0x04,0x02,0x01,0x01,0x05,0x03,
+ 0xe5,0x03,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0x02,0x02,0x06,0x01,0x02,0x04,0x04,
+ 0x06,0x02,0x03,0x03,0x01,0xe5,0x11,0x03,0x05,0x04,0x13,0x0e,0x2d,0xe8,0x13,0xe5,
+ 0x07,0xe5,0x01,0x05,0xe5,0x01,0xe5,0x03,0xe5,0x01,0xe5,0x01,0xe7,0x01,0x03,0x01,
+ 0xe5,0x01,0xe5,0x01,0xe7,0x01,0x05,0xe5,0x01,0x04,0xe6,0x01,0xe5,0x02,0xe6,0x01,
+ 0x04,0xe6,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,0xe5,0x02,0xe6,0x03,0x05,0xe5,
+ 0x01,0xe5,0x02,0xe6,0x01,0xe5,0x03,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x04,0xe7,0x01,
+ 0x05,0xe5,0x06,0xe6,0x07,0xe5,0x07,0xe5,0x01,0x03,0xe7,0x05,0xe7,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0xe5,0x16,0x01,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0x09,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x08,0xe6,
+ 0x06,0xe5,0x07,0xe5,0x05,0x01,0xe6,0x06,0xe5,0x07,0xe5,0x02,0x04,0x09,0xe6,0x07,
+ 0x12,0x03,0x09,0x1e,0xe5,0xe6,0x16,0x01,0xe5,0xe5,0x05,0x02,0x02,0x03,0x02,0x06,
+ 0x02,0x03,0x02,0xe5,0xe5,0x02,0x02,0x02,0x03,0x02,0xe5,0xe5,0x02,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x04,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0xe5,0xe5,0x01,0x04,0x01,0xe5,0xe5,0x03,
+ 0x02,0x02,0x02,0x02,0x07,0x01,0x02,0x03,0x03,0x12,0x06,0x09,0x14,0xe5,0x03,0xe5,
+ 0x02,0x17,0x09,0x09,0x02,0x06,0x02,0x02,0xe6,0xe5,0x04,0x01,0x01,0x02,0x02,0xe6,
+ 0xe5,0x06,0x01,0x06,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x05,0xe5,0xe5,0x04,0x01,0x01,
+ 0x07,0x01,0x06,0xe5,0x01,0xe5,0x08,0x02,0x03,0xe5,0xe5,0x01,0x06,0x01,0x13,0x05,
+ 0x03,0x0e,0xe5,0x16,0x04,0xe5,0x07,0xe5,0x14,0x07,0x02,0x19,0x07,0x05,0x03,0x09,
+ 0x05,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,
+ 0x04,0xe8,0x04,0xe7,0x01,0x06,0x01,0xe5,0x04,0xe8,0x05,0x01,0x02,0x07,0x09,0x02,
+ 0x02,0xe7,0x01,0xe5,0x05,0x05,0xe7,0x02,0x09,0x08,0x03,0xe7,0x02,0x04,0xe5,0x14,
+ 0x03,0x02,0x02,0xe5,0x01,0x2b,0xe5,0x26,0x02,0x37,0x1b,0x09,0x01,0xe5,0x05,0x03,
+ 0x1b,0xe6,0x23,0x01,0x0a,0x03,0x12,0x03,0x03,0x0d,0x01,0x06,0xe5,0xe5,0x01,0x04,
+ 0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x02,
+ 0x04,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,
+ 0x02,0x06,0x01,0x01,0x05,0xe6,0xe5,0xe5,0x02,0xe6,0x01,0x04,0x01,0xe6,0x04,0x01,
+ 0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,
+ 0x01,0x07,0x01,0x06,0xe7,0x0a,0xe7,0x18,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x01,
+ 0x02,0x02,0xe6,0x01,0xe5,0x02,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x04,0x02,0xe5,0x01,0x01,0x03,0xe5,0x07,0xe5,0x01,0xe5,0x02,0x02,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0xe5,0x06,0x02,0x06,0x01,0x08,0x0e,0x04,0xe5,0x01,0x05,
+ 0xe5,0x1d,0x07,0x1a,0x01,0xe5,0x14,0x03,0x09,0x05,0xe5,0x06,0x02,0xe6,0x0b,0x02,
+ 0xe5,0x01,0x02,0x01,0x04,0x04,0x0a,0x01,0xe7,0x03,0x03,0xe5,0x0c,0x09,0x04,0x04,
+ 0x03,0x01,0x06,0x01,0xe7,0x03,0x01,0xe5,0x0a,0xe6,0x01,0x01,0x04,0x01,0x07,0x01,
+ 0x07,0xe5,0x02,0xe5,0xe5,0xe5,0x01,0xe5,0x01,0x05,0x07,0x0a,0x07,0xe5,0x07,0xe5,
+ 0x0a,0x06,0x03,0xe5,0x16,0x01,0xe5,0x05,0x01,0x03,0x05,0xe5,0x0b,0x03,0x01,0x01,
+ 0xe5,0x02,0x02,0x03,0x03,0x01,0x04,0x02,0x01,0x02,0x01,0x09,0x02,0x01,0xe5,0x05,
+ 0x01,0x02,0x03,0xe5,0xe5,0x06,0x01,0x05,0xe5,0x08,0x08,0xe5,0x1a,0x01,0x03,0x0c,
+ 0x04,0x09,0x01,0x27,0x02,0x16,0x03,0xe5,0xe5,0x0d,0x05,0xe6,0x08,0x0a,0x03,0x0c,
+ 0x01,0x03,0x03,0xe6,0x04,0x01,0x09,0x01,0x07,0x01,0x13,0x07,0x01,0x06,0xe5,0x08,
+ 0x01,0x1a,0x02,0x01,0x03,0x03,0x01,0x06,0x07,0x07,0x04,0x01,0x10,0x03,0x03,0x05,
+ 0xe5,0x07,0x09,0x17,0x03,0x13,0x16,0x09,0x07,0x01,0x03,0x02,0x04,0x04,0x05,0x09,
+ 0x05,0x01,0x01,0x0b,0x0f,0x01,0x0a,0x06,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0x04,
+ 0x09,0x03,0x0a,0x0b,0x02,0x04,0x11,0x02,0x07,0x14,0x0a,0x04,0x02,0xe6,0xe6,0x06,
+ 0x0e,0x03,0x05,0x04,0x05,0xe5,0x02,0x04,0xe5,0x02,0x01,0x01,0x0b,0x04,0x08,0x03,
+ 0x0c,0x01,0x02,0x02,0xe5,0x01,0x01,0x02,0x0d,0x03,0x08,0x01,0xe5,0x0f,0x08,0xe5,
+ 0x03,0x09,0x04,0x07,0x05,0x07,0x0b,0x0c,0x09,0x14,0x18,0xe7,0x2a,0x09,0x01,0x01,
+ 0x04,0xe5,0xe5,0x10,0x02,0x03,0x05,0x06,0x13,0x01,0x07,0x01,0xe5,0x05,0x02,0x02,
+ 0x08,0x02,0x03,0x09,0x0e,0x04,0x01,0x14,0x09,0x03,0x05,0x06,0x02,0x04,0x01,0x02,
+ 0x03,0x02,0x04,0x04,0x01,0x0a,0x0d,0xe5,0xe6,0x05,0x0d,0x0a,0x0d,0x02,0x01,0x06,
+ 0x01,0xe5,0xe5,0x04,0xe5,0x05,0x08,0x02,0xe5,0x07,0xe5,0x01,0x02,0x03,0x02,0x05,
+ 0xe5,0x01,0x14,0x04,0xe5,0x02,0x06,0x02,0x01,0x06,0x01,0xe5,0x02,0xe5,0x16,0x04,
+ 0xe5,0x08,0x1a,0xe5,0x11,0x1e,0x04,0xe5,0xe5,0x05,0x14,0x05,0xe5,0x03,0x03,0xe5,
+ 0x0c,0x0c,0x04,0xe5,0x01,0x01,0x04,0x05,0xe5,0x05,0x01,0xe5,0x0f,0x08,0x09,0x01,
+ 0x09,0xe5,0x06,0x20,0x06,0x04,0x18,0x09,0xe5,0x0b,0x1c,0x0a,0x03,0x02,0xe5,0x01,
+ 0x03,0x06,0x18,0x04,0x04,0x01,0x09,0xe5,0x1e,0x01,0x02,0x04,0x04,0x02,0x01,0x09,
+ 0x01,0x08,0x06,0x09,0x04,0x0a,0x1b,0x06,0x06,0x0c,0x23,0x2e,0xe5,0x01,0xe5,0x01,
+ 0x10,0x0a,0x02,0x08,0xe6,0x03,0x02,0x01,0xe5,0x08,0x05,0x09,0x02,0x08,0x01,0xe5,
+ 0x04,0xe7,0x08,0x08,0x03,0x09,0x0c,0x08,0x06,0x04,0x04,0x09,0x08,0x04,0x09,0x08,
+ 0xe5,0x04,0x0c,0x09,0xe5,0x03,0x13,0xe5,0x19,0xe5,0x02,0x18,0x09,0x06,0x02,0xe6,
+ 0x03,0x05,0xe6,0xe5,0x04,0x0c,0xe5,0x01,0x18,0x01,0x08,0x05,0x02,0x01,0x09,0x0e,
+ 0x04,0x01,0x02,0x04,0x01,0xe5,0x03,0x07,0x05,0x0e,0x05,0x03,0x07,0x06,0xe5,0xe5,
+ 0x0f,0x09,0x08,0x18,0xe6,0xe6,0x07,0x09,0x08,0x01,0x0f,0x09,0x01,0x13,0x02,0x03,
+ 0x02,0x27,0x09,0xe5,0x04,0x32,0x01,0x24,0x02,0x0c,0x07,0x08,0x24,0x01,0x01,0xe5,
+ 0x09,0x16,0xe6,0x07,0x0b,0xe5,0x01,0x04,0x08,0xe5,0x03,0x03,0x05,0x03,0x09,0xe5,
+ 0x07,0x02,0xe5,0x04,0xe5,0x03,0x03,0x05,0x03,0x0b,0x0b,0xe5,0x05,0x05,0x02,0xe5,
+ 0x12,0x02,0x01,0xe5,0x01,0x0a,0x02,0x01,0x03,0xe6,0x11,0xe5,0x12,0x13,0x01,0xe9,
+ 0xe5,0xe5,0x07,0x0e,0x01,0x01,0x03,0x06,0x02,0x0c,0xe5,0x03,0x02,0x01,0x01,0x0a,
+ 0x03,0x08,0x06,0xe5,0xe5,0x05,0xe5,0x01,0x02,0xe5,0x0a,0x03,0x09,0x07,0xe5,0x01,
+ 0x0b,0xe5,0x08,0xe5,0xe5,0x02,0x0f,0x02,0x02,0xe5,0x01,0x09,0x03,0x02,0xe5,0x0f,
+ 0x01,0x01,0x03,0x26,0x01,0x03,0x02,0x02,0x01,0x08,0x06,0xe5,0xe5,0xe5,0x17,0x01,
+ 0xe5,0xe5,0x03,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0x02,0x01,0xe5,0x08,0x01,0xe5,0xe5,
+ 0x0d,0xe5,0x07,0x01,0x02,0x01,0x02,0xe5,0x0a,0x05,0xe5,0x03,0x09,0x01,0x07,0x01,
+ 0x01,0x05,0x06,0x01,0x0c,0x07,0x06,0x01,0x02,0x0b,0x0c,0xe5,0x02,0x0c,0x1a,0x04,
+ 0x01,0x01,0x02,0x0a,0x09,0x01,0x11,0x06,0x02,0x01,0x07,0x01,0x07,0x13,0x05,0xe5,
+ 0x07,0xe5,0x0d,0x04,0x18,0x09,0x01,0x07,0x01,0x07,0x06,0x0c,0x01,0x07,0x09,0x01,
+ 0x18,0x04,0x0e,0x13,0x06,0x02,0xe6,0xe7,0x0a,0x1d,0x04,0xe5,0xe6,0x01,0x02,0x09,
+ 0xe5,0x01,0xe5,0xe5,0x01,0x04,0x04,0x04,0x05,0x02,0x02,0x02,0xe5,0x01,0x02,0x02,
+ 0x04,0x04,0x02,0x01,0x09,0x01,0x02,0x01,0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0xe5,0x06,0x01,0x01,0x0c,0x04,0x12,0x0a,0x01,0x05,0x03,0x02,0x03,
+ 0x02,0x04,0xe6,0x05,0x02,0x08,0x07,0x02,0x01,0x02,0x09,0xe5,0x02,0x09,0x0f,0x01,
+ 0x02,0x01,0x01,0xe5,0x03,0x03,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0x01,0x04,0x04,0x0e,
+ 0x04,0x03,0xe5,0x03,0x01,0x01,0xe5,0x03,0x04,0x09,0x04,0x03,0x02,0x04,0xe5,0x01,
+ 0xe5,0x03,0x01,0xe7,0x03,0x02,0xe6,0x02,0x05,0x01,0x07,0x04,0x04,0x03,0x05,0x07,
+ 0xe5,0x09,0x01,0x01,0x09,0x02,0xe7,0x02,0x01,0x02,0x04,0x02,0x01,0x0e,0x02,0xe5,
+ 0x01,0x02,0x08,0x01,0x09,0x01,0x11,0x0b,0x04,0xe5,0xe5,0xe5,0xe5,0xe7,0xe5,0x08,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x05,0x01,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x05,
+ 0x03,0x04,0x06,0x09,0x05,0x01,0x15,0x07,0x06,0x04,0x05,0x0b,0x01,0x09,0x01,0x07,
+ 0x07,0x19,0x02,0x01,0x02,0x0a,0x09,0x01,0x03,0xe5,0x0b,0x01,0x02,0x04,0x04,0x01,
+ 0xe7,0xe5,0x01,0x04,0x04,0x04,0x01,0x02,0x04,0x04,0x04,0x01,0x02,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x04,0x06,0x04,0x04,0x04,0x04,0x04,0x04,0x13,
+ 0x01,0x02,0x04,0x06,0xe5,0xe5,0xe5,0x01,0x0e,0x01,0x0c,0x04,0x0b,0x15,0xe5,0xe5,
+ 0x02,0xe6,0x06,0x45,0x27,0xe5,0x07,0x02,0x1c,0x13,0x02,0x1a,0x02,0x08,0x07,0xe5,
+ 0x18,0x02,0xe5,0x11,0x02,0x06,0x09,0x01,0x02,0x01,0x08,0x01,0x25,0x1f,0x07,0xe5,
+ 0x04,0x02,0x24,0x0c,0xe5,0x09,0xe6,0x06,0xe5,0x07,0x10,0x1d,0x02,0x19,0xe5,0x0b,
+ 0x09,0x0b,0x07,0x02,0xe6,0x07,0x05,0x09,0x09,0x09,0x03,0xe5,0xe5,0x01,0x06,0x02,
+ 0x06,0x02,0x06,0x02,0x09,0x03,0xe5,0xe5,0x01,0x09,0x09,0x09,0x09,0x06,0x04,0x09,
+ 0x09,0x03,0x02,0x02,0x02,0x03,0x02,0x09,0x09,0x04,0x01,0x02,0x03,0x05,0x09,0x09,
+ 0xe6,0x06,0x04,0xe6,0x01,0x05,0xe5,0x01,0x0d,0xe5,0x01,0xe5,0x33,0x08,0xe5,0x07,
+ 0xe5,0x05,0x0c,0x09,0x1d,0x10,0x0e,0x09,0x06,0x02,0x06,0x0c,0x3b,0x09,0x08,0x0f,
+ 0x02,0x01,0x01,0x31,0x09,0x09,0x15,0x09,0x1d,0x1e,0x0a,0x07,0x14,0x3c,0x09,0x1f,
+ 0xe5,0x13,0x09,0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x04,
+ 0x01,0x02,0x01,0x02,0x01,0x02,0x04,0x01,0x02,0x01,0x04,0x02,0x04,0x01,0x02,0x04,
+ 0x01,0x02,0x04,0x01,0x02,0x06,0x02,0x05,0xe5,0xe5,0x01,0x04,0x01,0x02,0x06,0x02,
+ 0x06,0x11,0x01,0x02,0x06,0x04,0x02,0x01,0x02,0x15,0x05,0xe6,0x0a,0x02,0x01,0x1c,
+ 0x21,0x01,0xe5,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x01,0x01,0x02,0x02,
+ 0x01,0x01,0x07,0x01,0x05,0x01,0x01,0x01,0x03,0x01,0x01,0x05,0x01,0x01,0x05,0x01,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x01,
+ 0x01,0x05,0x02,0x06,0x03,0x01,0xe5,0x01,0x01,0x01,0x05,0x02,0x06,0x01,0x01,0x01,
+ 0x06,0x0f,0x03,0xe5,0x06,0xe5,0x05,0x01,0x01,0x04,0xe5,0x01,0x0f,0x01,0xe5,0x08,
+ 0x16,0x01,0x09,0x09,0x09,0x09,0x03,0x05,0x03,0xe5,0x08,0x04,0x04,0x02,0x0b,0x03,
+ 0x03,0x01,0x03,0xe5,0x01,0x01,0x03,0x07,0x03,0x05,0x13,0x04,0x12,0x05,0x03,0xe5,
+ 0x30,0x02,0x01,0x1c,0xe5,0x13,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe6,0xe5,
+ 0x02,0x01,0xe6,0xe5,0x02,0x01,0xe6,0x04,0xe6,0x06,0xe5,0xe5,0x07,0xe6,0xe5,0x02,
+ 0xe8,0x04,0xe6,0x02,0x03,0xe6,0x02,0x03,0xe6,0xe5,0xe5,0x02,0xe6,0x01,0xe5,0x05,
+ 0xe5,0x07,0xe7,0x06,0x01,0x07,0xe6,0x05,0xe6,0x05,0xe6,0xe5,0x06,0xe5,0x05,0xe6,
+ 0x08,0xe5,0x07,0xe5,0x02,0x03,0xe6,0x06,0xe7,0xe5,0x04,0xe5,0x07,0xe5,0x08,0x01,
+ 0x09,0x06,0x09,0xe5,0x2c,0x07,0x01,0x01,0x09,0x13,0x05,0x09,0x03,0x05,0x03,0x05,
+ 0x03,0x09,0x01,0x09,0x09,0x10,0x02,0x05,0x03,0x09,0x05,0x03,0x11,0x01,0xe5,0x0f,
+ 0x01,0x18,0xe8,0x32,0x03,0x06,0x02,0x06,0x02,0x04,0x01,0x02,0x04,0x01,0xe5,0x07,
+ 0x02,0x06,0x02,0x03,0x02,0x07,0x01,0x06,0x02,0x02,0x04,0x01,0x01,0x02,0x04,0x01,
+ 0xe5,0x07,0xe5,0xe5,0x05,0xe5,0x0d,0x01,0xe5,0xe5,0x05,0x01,0xe5,0x08,0x05,0x02,
+ 0x02,0x11,0x08,0x02,0x06,0xe5,0xe5,0x01,0x17,0x01,0xe5,0x0e,0x1c,0x0d,0x01,0x07,
+ 0x01,0x07,0x01,0x03,0x03,0x01,0xe5,0x01,0x05,0x07,0xe6,0x07,0xe5,0x02,0x03,0x01,
+ 0x03,0x04,0xe5,0x06,0x01,0x0f,0x04,0xe5,0x0c,0x13,0x03,0x01,0x03,0x09,0x04,0xe5,
+ 0x02,0x13,0xe5,0x02,0xe5,0x07,0xe5,0x02,0x19,0x01,0xe5,0x0f,0x09,0x09,0x08,0x02,
+ 0xe5,0x04,0x02,0xe8,0x01,0x02,0xe8,0x04,0x01,0x07,0x01,0x02,0x04,0xe8,0x01,0x02,
+ 0xe8,0x04,0xe5,0x04,0x02,0x01,0x07,0xe5,0x07,0x01,0x09,0x01,0x07,0xe9,0x03,0x01,
+ 0x02,0x02,0x0c,0xe5,0x01,0x04,0x01,0x02,0x02,0x06,0x04,0xe5,0x04,0x16,0xe8,0x05,
+ 0xe8,0xe5,0x18,0x02,0xe5,0x01,0x09,0xe5,0xe5,0x0d,0x0b,0xe5,0xe5,0x0f,0x0c,0xe5,
+ 0x04,0x02,0x01,0x12,0x0a,0x04,0xe5,0xe5,0x05,0x02,0x01,0x04,0x02,0x07,0x03,0xe5,
+ 0x12,0x05,0xe5,0xe5,0x09,0x05,0x09,0x09,0xe5,0xe5,0x19,0x11,0x1c,0xe5,0xe6,0x0a,
+ 0x01,0x03,0x01,0x07,0x01,0x07,0x01,0x01,0x01,0x03,0x01,0x07,0x01,0x04,0x02,0x01,
+ 0xe5,0x05,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0xe6,0x02,
+ 0x03,0x01,0x03,0x03,0xe6,0x08,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02,0x01,0xe5,
+ 0x05,0xe6,0xe5,0x04,0x01,0xe5,0x02,0x02,0x01,0x04,0x01,0xe8,0x05,0x01,0xe6,0x04,
+ 0x01,0x03,0x03,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x0e,0x0f,0x2b,0x0d,
+ 0x05,0xe5,0x01,0x01,0x0d,0x0b,0x03,0xe6,0x01,0x06,0x04,0xe5,0xe7,0x04,0x01,0xe5,
+ 0x04,0x02,0x01,0xe5,0x02,0x11,0x06,0x12,0x0c,0x01,0x05,0x01,0x1b,0x2c,0xe5,0xe7,
+ 0x12,0x0f,0xe5,0x0c,0x04,0x03,0x05,0x04,0x07,0x02,0x02,0x0e,0x0a,0xe6,0x03,0x01,
+ 0xe6,0x09,0x08,0x01,0x05,0x05,0x01,0x04,0x1b,0x06,0x05,0x0e,0x13,0x0d,0x0a,0x12,
+ 0x0a,0x06,0x02,0x01,0x04,0x06,0xe5,0xe5,0x15,0x03,0xe5,0x02,0x0a,0x02,0x01,0x03,
+ 0x13,0xe6,0x02,0x10,0x02,0x02,0x06,0x05,0x03,0x02,0x06,0x01,0x03,0x03,0x03,0x1e,
+ 0x02,0x17,0x05,0x03,0x01,0x04,0x14,0x01,0x01,0x0b,0x22,0x01,0xe6,0x08,0x10,0x05,
+ 0xe6,0x06,0x01,0xe5,0x02,0x02,0xe6,0x10,0x02,0x09,0x06,0x01,0x05,0x03,0x07,0x01,
+ 0x02,0x04,0x05,0xe5,0x01,0x01,0x02,0x04,0x01,0xe5,0x06,0xe5,0xe5,0x02,0x06,0x03,
+ 0x05,0x03,0x01,0x0a,0x01,0x04,0x02,0x01,0x02,0x10,0x01,0x04,0xe5,0xe5,0xe6,0x06,
+ 0x06,0x01,0xe5,0x08,0xe5,0x04,0x06,0x02,0xe6,0x0c,0xe6,0xe6,0x07,0x16,0x07,0x05,
+ 0x08,0x05,0x0a,0x04,0x10,0x02,0x07,0x0a,0x05,0x03,0x09,0x05,0x03,0x05,0x01,0x01,
+ 0x02,0x26,0x01,0x08,0x0d,0x03,0x0a,0x11,0x01,0x13,0x05,0x02,0x0f,0xe9,0x07,0x09,
+ 0x09,0x03,0x09,0x05,0x06,0x13,0x01,0x0a,0xe5,0x03,0xe5,0x08,0x01,0x04,0xe6,0x08,
+ 0xe6,0x04,0x02,0x06,0xe6,0x02,0x03,0x07,0x09,0x0f,0x07,0x01,0x03,0x03,0xe7,0x01,
+ 0x17,0x01,0x05,0x03,0x0b,0x07,0x03,0x05,0xe5,0x15,0x01,0xe7,0xe5,0x13,0xe5,0xe7,
+ 0x09,0x07,0x13,0x02,0x01,0x0b,0x06,0x02,0xe5,0x04,0xe5,0xe5,0xe5,0x03,0x07,0x03,
+ 0x05,0x0e,0x01,0x07,0x04,0x09,0x0a,0xe5,0x0d,0x01,0xe5,0x05,0x0e,0x0a,0x03,0x02,
+ 0x06,0x0c,0x06,0xe5,0x02,0x04,0xe5,0x07,0x11,0xe5,0xe5,0x05,0x01,0x1d,0xe6,0x05,
+ 0xe5,0x07,0x01,0x02,0x0f,0x01,0x01,0x02,0x02,0x02,0x03,0x10,0x04,0x08,0x15,0x04,
+ 0x05,0x09,0xe5,0xe5,0x0e,0xe5,0x07,0x02,0x05,0x02,0x09,0x0e,0x02,0x08,0xe6,0xe5,
+ 0x08,0xe5,0x01,0x07,0x01,0x03,0xe5,0x05,0x10,0x01,0x06,0x23,0x0a,0xe5,0x04,0x02,
+ 0xe5,0x06,0x13,0xe5,0x01,0x09,0x07,0x0e,0x0a,0x0c,0x0a,0xe5,0x09,0x01,0x19,0x12,
+ 0x02,0x01,0x02,0x09,0x0d,0xe6,0x05,0xe5,0x01,0xe5,0x03,0x09,0x07,0x05,0x07,0x35,
+ 0xe5,0x0a,0x02,0xe5,0x15,0x05,0x08,0x06,0x04,0x1e,0x01,0x0b,0x0b,0x03,0x07,0x02,
+ 0x22,0x04,0x07,0x03,0x0b,0x08,0x05,0x1e,0xe9,0x01,0x1d,0x01,0xe5,0x03,0x08,0x0d,
+ 0x01,0x05,0x02,0x10,0x02,0xe5,0x07,0x01,0x05,0x01,0x06,0x03,0x03,0x31,0x07,0x0d,
+ 0x01,0xe5,0xe6,0x02,0x01,0x02,0x09,0x07,0x01,0x09,0x06,0x02,0x01,0x02,0x04,0x04,
+ 0x04,0x05,0x04,0x0e,0x02,0x03,0x1f,0x0a,0xe5,0x03,0x09,0x02,0xe5,0x06,0xe5,0xe5,
+ 0x06,0x05,0x03,0x06,0x02,0x06,0x02,0x10,0x02,0x05,0xe5,0x07,0x05,0xe5,0xe6,0x09,
+ 0xe5,0x0d,0x05,0xe5,0xe5,0x01,0x09,0x06,0x1d,0x02,0x06,0x09,0x09,0xe5,0x18,0xe6,
+ 0x01,0x20,0x1d,0x09,0x09,0x07,0xe5,0x07,0x01,0x06,0x02,0x0b,0x06,0x02,0x0b,0x07,
+ 0x06,0x05,0x17,0x0e,0x05,0xe5,0x02,0x04,0x13,0x01,0x07,0x01,0x07,0x01,0x07,0xe5,
+ 0x04,0x10,0x06,0x01,0xe6,0x1f,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x0e,0x0e,0x07,0x06,
+ 0x0c,0xe5,0x14,0xe5,0x05,0x0b,0x08,0x09,0xe5,0x0e,0x03,0x08,0xe5,0x04,0x03,0x08,
+ 0xe5,0x01,0xe5,0x03,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0x06,
+ 0x02,0x01,0x03,0xe5,0xe5,0x1a,0x01,0xe6,0x0b,0x05,0x02,0x03,0x01,0xe5,0x05,0x01,
+ 0xe5,0x03,0x01,0x01,0x0f,0x01,0x01,0x07,0xe5,0x03,0x01,0x04,0x09,0x05,0xe5,0x01,
+ 0x0a,0xe6,0x01,0x05,0xe5,0x0a,0x07,0x05,0xe5,0xe5,0x08,0xe5,0x01,0x02,0x01,0xe5,
+ 0x08,0x02,0x10,0x04,0x07,0x06,0x02,0x0a,0x01,0xe5,0x0f,0x03,0xe5,0xe5,0x01,0x01,
+ 0x1e,0x01,0x05,0x01,0x07,0x06,0x01,0xe5,0x08,0x06,0xe5,0xe5,0x01,0x10,0x01,0x02,
+ 0x15,0xe5,0x02,0x0b,0x07,0x09,0x01,0x13,0x04,0x01,0x04,0x07,0x04,0x01,0x02,0x01,
+ 0x11,0x01,0x0b,0xe5,0x01,0x01,0x16,0x08,0x0c,0x01,0x01,0xe5,0xe5,0x1d,0x06,0x02,
+ 0x01,0x07,0x06,0x02,0xe6,0x06,0x06,0xe5,0x01,0xe5,0x0d,0xe5,0x02,0x11,0x06,0xe5,
+ 0xe5,0xe5,0x06,0x05,0xe5,0x03,0x09,0x01,0x25,0x06,0xe5,0xe5,0x08,0x06,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0x02,0x01,0x07,0x10,0x0d,0x02,0x01,0x03,0xe7,0x14,0x01,0x09,
+ 0x03,0x01,0xe5,0x09,0x07,0x06,0x03,0xe5,0x03,0x08,0xe5,0x03,0x01,0x07,0x01,0x02,
+ 0xe5,0x01,0xe5,0xe5,0x06,0x05,0x02,0x05,0x03,0xe5,0x03,0xe5,0x01,0x01,0x02,0x02,
+ 0x06,0x06,0x11,0x01,0xe5,0x03,0x04,0x01,0x03,0x02,0xe5,0x03,0x03,0x13,0x06,0x01,
+ 0xe5,0x0f,0x02,0x02,0x05,0x11,0xea,0xe5,0x13,0x01,0x01,0x05,0x03,0x02,0x01,0x04,
+ 0x05,0x03,0x05,0x02,0x01,0x02,0xe6,0x0d,0x01,0x01,0xe5,0xe5,0xe5,0x04,0x03,0x02,
+ 0x01,0xe5,0xe5,0xe5,0x04,0x01,0x06,0xe5,0x03,0x02,0xe6,0xe5,0x01,0x06,0x04,0x03,
+ 0xe5,0x02,0x01,0x01,0xe5,0x10,0x01,0xe5,0x03,0x04,0x01,0x01,0x05,0x04,0x02,0x05,
+ 0x09,0x01,0x01,0xe6,0x02,0x02,0x01,0x04,0x09,0x02,0x01,0xe5,0x02,0x04,0x04,0x09,
+ 0x01,0x01,0x01,0xe5,0x01,0x14,0x01,0x09,0x07,0x01,0x04,0x02,0x06,0x02,0x07,0x01,
+ 0x03,0xe5,0x0d,0x01,0x04,0x01,0x02,0x01,0x05,0x01,0x07,0x06,0xe6,0x01,0x04,0xe7,
+ 0x0a,0x07,0x01,0x01,0x0e,0x01,0x05,0x04,0x01,0x07,0x01,0x09,0x13,0x02,0x0e,0x01,
+ 0x13,0x05,0x01,0x01,0x0d,0xe6,0xe7,0x15,0x01,0x07,0x06,0x01,0xe5,0xe5,0x04,0x01,
+ 0x07,0x01,0x01,0xe5,0xe7,0x01,0x10,0x02,0x01,0x03,0xe5,0x08,0x01,0xe5,0xe5,0x06,
+ 0x01,0x02,0x01,0x02,0x01,0x02,0x01,0x02,0x01,0x02,0x06,0x04,0x04,0x01,0x03,0xe5,
+ 0x08,0x01,0x0a,0x01,0x02,0x04,0x01,0x07,0x04,0x22,0x01,0x11,0x09,0x01,0x0d,0xe5,
+ 0x01,0xe5,0x08,0x02,0x35,0x16,0x01,0xe5,0x0c,0x16,0xe6,0x08,0x07,0xe5,0x09,0x02,
+ 0x1a,0x02,0x24,0x02,0x06,0x27,0x14,0xe5,0x01,0x0a,0x37,0xe5,0x01,0x05,0xe5,0x01,
+ 0xe5,0x07,0x0f,0xe5,0x01,0x10,0x02,0xe5,0x31,0x06,0x02,0x27,0x0b,0x11,0x09,0x0b,
+ 0x13,0xe7,0x09,0x03,0x09,0x09,0x09,0x09,0x06,0x02,0xe5,0xe7,0xe5,0x01,0xe5,0x07,
+ 0x03,0x05,0x04,0x01,0x02,0xe6,0xe5,0x04,0x09,0x09,0x09,0x04,0x01,0x04,0x09,0x09,
+ 0x05,0x03,0x05,0x03,0x06,0x02,0x06,0x02,0x09,0x05,0xe5,0x01,0x04,0x01,0x02,0x09,
+ 0x04,0xe6,0x01,0x03,0x02,0x02,0x09,0x02,0x09,0xea,0x3a,0x02,0x09,0x1d,0x1d,0x09,
+ 0x09,0x29,0x06,0x02,0x08,0x13,0xe5,0x08,0x13,0x08,0xe5,0x08,0x09,0x04,0x06,0x3d,
+ 0x05,0x01,0x1d,0x1d,0x09,0x0b,0x27,0x0a,0x1e,0x09,0x13,0x07,0x09,0x0b,0x08,0xe5,
+ 0xe6,0x22,0x11,0x01,0x07,0x02,0x01,0x03,0xe5,0x08,0x01,0xe5,0x04,0x02,0x06,0xe5,
+ 0xe7,0x03,0x02,0x07,0x01,0x02,0x06,0x02,0x01,0x02,0x01,0x02,0x01,0x06,0x02,0x04,
+ 0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x02,0x06,0x07,0x01,0x02,0x04,0x13,0x01,
+ 0x09,0x07,0x08,0x02,0x06,0x02,0x10,0x01,0x1e,0x04,0xe5,0x0c,0x02,0x01,0xe5,0x02,
+ 0x04,0xe6,0x07,0xe5,0xe5,0x01,0xe5,0xe7,0x01,0x04,0xe5,0x02,0x04,0xe6,0x06,0xe5,
+ 0x05,0x01,0x01,0x01,0xe5,0x01,0x03,0x05,0x01,0x01,0x07,0x01,0x01,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0x01,0x01,0x05,0x01,0x05,0x01,0xe5,0x07,0x01,0x05,0x03,
+ 0x09,0x05,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,0xe5,0x08,0x06,0x02,0x0d,0x01,0x01,
+ 0xe5,0x21,0x04,0x0b,0xe5,0xe5,0x08,0x07,0x01,0x07,0x0b,0x07,0x01,0x01,0x02,0x04,
+ 0x04,0x0e,0x03,0x05,0x03,0x0f,0x01,0x11,0x01,0x03,0x03,0x01,0x03,0x05,0x07,0x01,
+ 0x03,0x03,0x0f,0xe5,0x01,0x01,0x09,0x1d,0x0e,0x03,0xe5,0x13,0xe5,0x07,0xe5,0x01,
+ 0x04,0xe6,0x07,0xe6,0xe5,0x03,0xe5,0x02,0x05,0xe6,0x06,0xe6,0x04,0x01,0xe5,0x01,
+ 0x05,0xe6,0x06,0xe5,0x01,0x05,0xe5,0x07,0xe6,0x05,0xe7,0x04,0x01,0xe5,0x03,0x05,
+ 0xe6,0xe5,0x02,0xe7,0x06,0xe7,0xe5,0x04,0xe5,0x01,0x05,0xe6,0xe5,0x02,0xe6,0x02,
+ 0x05,0xe6,0x04,0x01,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x04,0xe6,0x06,0xe6,0x08,0xe6,
+ 0x06,0xe5,0x08,0xe6,0x22,0xe6,0x03,0x03,0xe5,0x07,0xe5,0x04,0x09,0x01,0x09,0x09,
+ 0xe5,0x05,0x01,0x09,0x13,0x15,0x09,0xe5,0x01,0xe5,0xe6,0xe7,0x01,0x0e,0x09,0x03,
+ 0xe6,0x02,0x07,0x0b,0x07,0x01,0x09,0xe5,0x01,0x06,0x04,0x1c,0xe6,0xe5,0x22,0x18,
+ 0x01,0xe5,0x0a,0x09,0x03,0x02,0x02,0xe5,0x07,0x09,0x13,0x06,0x0b,0xe5,0xe5,0x05,
+ 0x02,0xe5,0x03,0xe6,0xe5,0x05,0x14,0x01,0x06,0x0a,0x08,0x0a,0x01,0x07,0x07,0xe5,
+ 0x05,0x02,0x1c,0xe8,0x21,0x04,0x18,0x09,0x05,0x01,0x01,0x05,0x03,0x07,0x01,0x09,
+ 0x0b,0x03,0x03,0x01,0x02,0x04,0x03,0x01,0x0f,0x05,0x0d,0x01,0x07,0x09,0x05,0x03,
+ 0x0b,0x01,0x01,0x05,0x07,0x01,0x07,0xe5,0x02,0xe5,0x03,0x03,0xe5,0x1b,0xe6,0xe5,
+ 0x02,0x1f,0xe5,0x02,0x05,0x09,0x03,0x02,0x04,0x09,0xe5,0xe5,0xe5,0xe6,0xe9,0x01,
+ 0xe5,0x05,0x04,0x06,0xe5,0x0b,0x01,0x03,0x04,0x01,0xe5,0x03,0xe5,0xe5,0x04,0x02,
+ 0x01,0x01,0x02,0xe5,0x01,0x06,0x03,0x01,0x02,0x0c,0x04,0x01,0x03,0x08,0x0b,0xe6,
+ 0x09,0x01,0x07,0x02,0x09,0x02,0x1e,0xe6,0xe5,0x37,0x06,0xe5,0xe5,0x05,0x01,0xe5,
+ 0x1c,0x10,0x09,0x02,0x07,0x01,0x07,0xe5,0x1c,0x02,0x01,0x04,0x02,0x10,0x09,0x09,
+ 0x01,0xe5,0x05,0x02,0x0b,0x04,0x02,0xe5,0x08,0x18,0xe6,0x10,0x01,0x01,0x05,0x01,
+ 0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x03,0x03,0x01,0xe6,0x01,0x02,0xe6,0x01,0x04,
+ 0x01,0xe6,0x04,0x01,0x07,0xe6,0xe5,0x04,0xe7,0x01,0x03,0x01,0x06,0xe5,0xe5,0x06,
+ 0x01,0x06,0x02,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0xe5,
+ 0x01,0x01,0xe5,0xe5,0x03,0x01,0x02,0x01,0x02,0x01,0x04,0x02,0x01,0x01,0x02,0x02,
+ 0x01,0x01,0x04,0xe5,0xe5,0xe5,0x04,0x01,0x02,0xe5,0x02,0x01,0x01,0x05,0xe6,0x06,
+ 0x01,0x0c,0x01,0x0c,0x21,0x01,0x04,0x05,0x05,0xe7,0x01,0x03,0x05,0x03,0xe5,0x0b,
+ 0xe5,0xe6,0x0e,0x02,0x09,0xe6,0x03,0x11,0x03,0x13,0xe5,0x01,0xe5,0x01,0x05,0x03,
+ 0x07,0xe5,0x0b,0xe5,0x0f,0x05,0xe5,0x01,0x04,0x02,0x01,0x05,0x01,0x04,0x04,0xe5,
+ 0x16,0x01,0xe7,0x14,0x07,0x0c,0x08,0x06,0x01,0xe5,0xe5,0x06,0x0b,0x07,0x06,0x07,
+ 0x04,0x07,0x05,0x03,0x08,0x01,0x07,0x0b,0x09,0x01,0x07,0xe5,0x09,0x0b,0x02,0x02,
+ 0x09,0x09,0x02,0x09,0x08,0x05,0x04,0x04,0x04,0x02,0x06,0x10,0x01,0xe7,0xe5,0x2f,
+ 0x09,0x01,0x01,0x07,0x02,0x09,0xe5,0xe5,0x02,0x0f,0x01,0x06,0xe5,0x06,0x03,0x07,
+ 0x09,0x03,0x04,0x29,0xe5,0x04,0x07,0x05,0x08,0xe5,0xe5,0xe5,0x08,0x0b,0x07,0x01,
+ 0x04,0x03,0x1d,0xe6,0x06,0x01,0x1c,0x01,0x0b,0x01,0x07,0x02,0x06,0x18,0x02,0x13,
+ 0x05,0x02,0x04,0xe5,0x03,0x01,0x01,0xe5,0x06,0x08,0x01,0x01,0x13,0x01,0xe5,0x05,
+ 0x03,0xe5,0x05,0x02,0x02,0x01,0xe5,0x04,0xe5,0x08,0x0b,0xe5,0x03,0x01,0x01,0x07,
+ 0x0b,0x07,0x01,0x0d,0xe6,0x01,0x33,0x03,0x04,0xe5,0x02,0x05,0x04,0x02,0x01,0x11,
+ 0x0b,0x0a,0x09,0x06,0xe5,0xe5,0xe5,0xe5,0x03,0x01,0x05,0x01,0x05,0x04,0x09,0xe5,
+ 0x06,0xe6,0x01,0x03,0x0a,0x05,0x03,0x05,0x05,0x03,0x08,0x04,0x03,0x01,0x0a,0x06,
+ 0x05,0x05,0x03,0x0a,0x01,0xe7,0x1b,0x08,0x0e,0x01,0x03,0x05,0xe5,0x01,0x05,0x08,
+ 0xe5,0x02,0x04,0xe5,0x08,0x02,0x06,0x03,0x05,0x03,0x03,0x01,0x03,0x05,0x03,0x02,
+ 0xe5,0x02,0x03,0x03,0x01,0x02,0x06,0x07,0x01,0x09,0x09,0x07,0x0b,0x09,0x09,0x0d,
+ 0xe5,0x07,0xe5,0x02,0xe5,0x01,0x04,0x0f,0x01,0xe7,0x19,0x04,0x0e,0x06,0x02,0x06,
+ 0x07,0x01,0x04,0xe5,0x02,0x02,0x06,0x06,0x02,0x02,0x06,0x09,0x02,0xe5,0x04,0x09,
+ 0x02,0x05,0xe5,0xe5,0x08,0x02,0x06,0x03,0x05,0x04,0x04,0x02,0x06,0x0e,0x04,0x02,
+ 0x0b,0x07,0x06,0x02,0x04,0x01,0x01,0x07,0x01,0x03,0x03,0x01,0x0e,0xe6,0xe5,0x2f,
+ 0x06,0xe5,0x01,0x03,0x02,0x02,0x01,0x03,0xe5,0xe7,0xe5,0x01,0x06,0x02,0x09,0xe5,
+ 0x07,0xe5,0x01,0x05,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0x05,0x01,0x02,0x06,0x02,
+ 0x06,0x02,0x01,0x04,0x02,0x03,0x02,0x02,0x01,0x03,0xe5,0x01,0x0a,0xe5,0x03,0x02,
+ 0x03,0x05,0xe6,0x06,0x08,0x02,0x02,0x0f,0xe5,0x10,0x03,0x03,0x16,0x09,0x14,0xe5,
+ 0x05,0xe5,0x03,0x03,0xe5,0xe5,0x0d,0x01,0x08,0x01,0x09,0xe6,0x06,0x0b,0x04,0x03,
+ 0xe6,0x02,0xe5,0x01,0x02,0x07,0xe6,0xe5,0x05,0xe6,0x05,0xe5,0x07,0xe6,0x07,0xe5,
+ 0x06,0x10,0x09,0x01,0xe5,0x0a,0x19,0x14,0xe5,0xe5,0x02,0x07,0x19,0x0f,0x01,0x0e,
+ 0x03,0x26,0xe5,0x12,0x03,0x06,0x07,0x02,0x08,0x01,0x09,0x07,0x09,0xe5,0x07,0x01,
+ 0x03,0x09,0x0b,0x09,0x06,0x01,0xe5,0x02,0x06,0x25,0x01,0xe7,0x07,0x09,0x09,0x06,
+ 0x10,0x01,0x06,0x06,0x02,0xe5,0xe5,0x03,0x04,0x03,0x05,0x06,0xe5,0xe5,0x04,0xe6,
+ 0xe5,0x05,0xe5,0xe5,0x02,0xe5,0xe6,0xe5,0x03,0x01,0xe5,0xe5,0x0f,0x09,0x09,0x09,
+ 0x09,0xe5,0x09,0x10,0xe5,0x07,0x05,0xe5,0x11,0x07,0x01,0x0a,0x0e,0x01,0xe5,0x09,
+ 0x2a,0x01,0x01,0x07,0x02,0x04,0x01,0xe5,0x04,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x04,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x03,0x04,0x02,0x06,0xe5,0x01,
+ 0x02,0x02,0x09,0x09,0xe5,0x02,0xe6,0x01,0x0a,0x0f,0x02,0x08,0xe5,0x08,0x09,0x03,
+ 0x05,0x0b,0x0c,0x02,0xe5,0x05,0x39,0x14,0x09,0x0b,0x02,0x13,0x19,0x09,0x09,0x09,
+ 0x09,0x09,0x0c,0x09,0x06,0x0a,0x09,0x07,0x01,0x06,0x02,0x18,0xe6,0xe5,0xe6,0x0c,
+ 0x09,0xe6,0x06,0xe5,0x0b,0xe5,0xe5,0x02,0x01,0xe5,0x01,0x03,0x02,0x01,0xe5,0x02,
+ 0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x08,0x03,0x05,0x09,0x09,0x06,
+ 0x01,0x01,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,
+ 0x02,0xe5,0xe5,0xe6,0x02,0xe5,0x07,0x08,0xe5,0x07,0x09,0x03,0xe5,0x28,0x02,0xe5,
+ 0x09,0x02,0xe5,0xe6,0xe5,0xe5,0x0e,0xe5,0x07,0xe5,0x04,0x05,0xe5,0x04,0x01,0x02,
+ 0xe5,0x07,0x01,0x02,0x01,0x02,0x04,0xe5,0x02,0x02,0x01,0xe5,0x02,0x01,0x07,0x09,
+ 0x01,0x02,0xe5,0x02,0x04,0xe5,0x02,0x02,0x06,0x02,0x08,0x09,0xe5,0x02,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x08,0xe6,0x19,0xe5,0x2c,0x01,0xe5,0x0a,0x01,0x02,
+ 0xe5,0xe6,0x01,0x01,0x16,0x11,0x04,0x04,0x04,0x04,0x02,0x01,0x04,0x01,0xe5,0xe5,
+ 0x03,0x04,0x04,0x04,0x04,0x02,0x01,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x06,
+ 0x01,0x02,0x04,0x02,0x01,0x04,0x01,0xe5,0xe5,0x03,0x01,0x02,0x04,0x01,0x02,0x02,
+ 0x09,0x01,0x01,0xe5,0xe5,0xe5,0x0b,0x02,0x09,0xe6,0x01,0x06,0x01,0x06,0xe5,0x01,
+ 0x01,0x07,0x03,0x02,0xe5,0x02,0x04,0xe5,0xe6,0x01,0x28,0x06,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x04,0xe5,0x01,0x01,
+ 0x04,0x0c,0x06,0x0c,0x13,0x01,0x07,0x06,0x06,0x02,0xe6,0xe7,0x09,0x20,0x03,0x02,
+ 0x02,0x02,0x06,0x02,0x06,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,
+ 0x02,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,
+ 0xe5,0x01,0x04,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x03,0x02,
+ 0x02,0x01,0x01,0xe5,0x03,0x0c,0x01,0x0f,0x01,0xe6,0x11,0xe5,0x01,0x01,0x07,0x01,
+ 0x0c,0x07,0x02,0xe6,0x01,0x06,0x01,0xe5,0x1d,0x03,0x04,0xe5,0x02,0x05,0x03,0x05,
+ 0x03,0x05,0x03,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x05,0x03,0x05,0x03,0x02,
+ 0x01,0xe5,0x02,0x04,0xe5,0x02,0x02,0x01,0x02,0x03,0x02,0x01,0xe5,0x02,0x05,0x03,
+ 0x04,0xe5,0x02,0x01,0x01,0xe6,0x02,0x01,0x02,0xe5,0x02,0x09,0x05,0x03,0x09,0x02,
+ 0x01,0xe5,0x02,0x01,0x02,0x04,0x01,0x01,0xe6,0x01,0x06,0x02,0x0a,0x09,0x02,0x03,
+ 0x02,0x2a,0x04,0xe7,0x02,0x02,0x02,0x03,0x02,0x02,0x09,0x06,0x01,0xe5,0x02,0x05,
+ 0x03,0x02,0x01,0xe5,0x02,0x02,0x02,0x06,0x01,0xe5,0x05,0xe7,0x05,0x01,0x02,0x09,
+ 0x09,0x04,0x02,0x01,0x06,0x02,0x0b,0x01,0x01,0xe5,0x01,0x01,0x18,0x01,0xe5,0x03,
+ 0x04,0x09,0x06,0x02,0x01,0x02,0x14,0xe5,0xe7,0x12,0xe5,0x15,0x0b,0x02,0x01,0xe6,
+ 0x01,0x02,0x02,0x03,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x02,0x01,0x01,0x02,0x02,
+ 0x01,0x01,0x02,0x02,0x02,0x03,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe5,0xe5,0xe5,0x01,
+ 0x01,0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe7,0x03,0x01,0xe8,0x02,0x01,
+ 0xe7,0x03,0x02,0x04,0x01,0x17,0xe5,0x18,0xe5,0x01,0xe7,0xe7,0x15,0x02,0xe6,0x03,
+ 0xe5,0x2d,0x02,0x02,0x02,0xe5,0x01,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x01,
+ 0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,
+ 0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x06,0x02,0x13,0x02,0x10,0xe5,0x07,0x06,0x02,0x02,0x03,0x16,0x02,0x01,0x05,0x32,
+ 0xe5,0x07,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x06,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x1c,0x09,
+ 0xe5,0x07,0x01,0x03,0x0a,0x02,0xe5,0x11,0x02,0xe6,0x0d,0x09,0x09,0x09,0x02,0x03,
+ 0xe5,0xe7,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,0x01,0xe5,
+ 0xe5,0x03,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,
+ 0x06,0x06,0x02,0x09,0x03,0x05,0x04,0x01,0x02,0x02,0xe6,0xe5,0x01,0xe5,0x04,0x02,
+ 0xe6,0x01,0x01,0x02,0x04,0x01,0x06,0xe5,0x01,0xe5,0x32,0x01,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x11,0xe5,0x08,0x09,0x09,
+ 0x10,0x02,0x09,0x09,0x04,0x06,0x35,0x09,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x06,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0x0e,
+ 0x08,0x0a,0x07,0x14,0x08,0x0b,0x08,0x02,0xe5,0x1d,0x02,0x01,0x04,0x0e,0xe7,0x03,
+ 0x02,0xe6,0x03,0x02,0x01,0x04,0x02,0xe6,0x03,0x02,0xe6,0x02,0xe5,0x01,0xe6,0x03,
+ 0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0x01,0x05,0xe5,0x01,0x01,0x04,
+ 0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x02,0xe5,
+ 0xe5,0x03,0x02,0x13,0x01,0x07,0x01,0x0a,0xe5,0x01,0x05,0x19,0xe6,0x20,0x01,0xe5,
+ 0x0f,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x03,0xe5,0x01,
+ 0xe5,0x06,0x02,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x01,0x01,0xe5,0x01,0xe5,0x04,0x01,0xe5,0x07,0x01,0x07,0xe5,0x02,0x02,0x01,
+ 0x01,0x05,0x01,0xe5,0x07,0x01,0x05,0x03,0x04,0x03,0x0d,0xe5,0x01,0xe5,0x11,0x0d,
+ 0x01,0x15,0x07,0x09,0x09,0x09,0x09,0x09,0xe5,0x07,0x09,0xe5,0x07,0x0b,0x09,0x09,
+ 0x01,0x07,0x01,0x07,0xe5,0x07,0x01,0x01,0xe5,0x01,0x01,0x04,0x04,0x04,0x04,0x07,
+ 0x01,0x13,0x04,0x1d,0x01,0x01,0x15,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x05,
+ 0xe7,0x01,0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,
+ 0x01,0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0x03,
+ 0xe7,0xe5,0x01,0x04,0xe6,0x01,0xe5,0x01,0xe7,0x01,0x04,0xe6,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe6,0x04,0xe7,0x01,0x05,0xe6,0xe5,0x04,0xe5,
+ 0x01,0x03,0xe7,0x01,0xe5,0x01,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,0x2e,
+ 0xe5,0x04,0x01,0x06,0x02,0xe6,0x03,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe6,0x03,
+ 0x02,0xe5,0x04,0x02,0xe6,0x03,0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x04,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x07,0xe6,0x06,0xe5,0x04,0x03,0x0f,
+ 0x03,0x06,0x01,0x07,0x01,0xe5,0x04,0x03,0xe5,0x03,0x02,0x09,0x12,0x35,0x01,0x03,
+ 0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0xe5,0x01,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,
+ 0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,
+ 0x03,0x01,0xe5,0x01,0xe5,0x01,0x01,0xe5,0x03,0xe5,0x04,0x02,0x03,0x01,0xe5,0x01,
+ 0xe5,0x04,0x02,0xe5,0x07,0x09,0x05,0xe5,0x0e,0x02,0xe5,0x09,0x01,0x02,0x04,0x01,
+ 0xe5,0x01,0x01,0xe5,0x04,0xe5,0xe7,0x03,0x04,0x14,0xe5,0x33,0x03,0x02,0xe5,0xe5,
+ 0x02,0x02,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x02,0x02,0xe5,
+ 0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x02,
+ 0x02,0xe5,0xe5,0x02,0x02,0xe5,0x01,0xe5,0x02,0x02,0x02,0x02,0xe5,0x01,0xe5,0xe5,
+ 0x02,0x02,0x02,0x03,0x05,0x03,0x05,0x02,0xe5,0x02,0x04,0x0c,0xe6,0x03,0x08,0x0e,
+ 0xe5,0x08,0x0d,0x0f,0x01,0xe5,0x23,0x09,0x08,0x03,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x05,0x09,0x05,0x03,
+ 0x06,0x02,0x09,0x09,0x05,0xe5,0x04,0x0c,0x06,0x06,0x01,0xe5,0x08,0x02,0xe5,0x04,
+ 0x02,0xe5,0x0b,0x10,0xe6,0xe5,0x45,0x10,0x20,0x06,0x0c,0x07,0x05,0x08,0x2c,0x0d,
+ 0x02,0xe5,0xe5,0x0f,0xe5,0xe5,0x08,0x06,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x09,
+ 0x04,0x01,0x0b,0x05,0x01,0x07,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0x01,0x05,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0xe5,0x04,0xe5,0xe5,0x06,0xe7,0xe5,0x03,
+ 0xe7,0xe5,0x03,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,0xe7,0x05,0x01,0x01,0x05,0xe6,
+ 0xe5,0x04,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x02,
+ 0xe5,0x01,0xe5,0xe5,0x01,0x04,0x01,0x03,0x03,0x01,0x01,0x05,0x01,0x01,0xe6,0x02,
+ 0x01,0x02,0x01,0x02,0x01,0x02,0xe5,0x02,0x01,0x0b,0x02,0x02,0x13,0x09,0x20,0xe5,
+ 0x02,0x05,0x03,0x01,0x02,0xe5,0xe5,0x05,0x04,0x04,0x09,0xe5,0x07,0xe5,0xe5,0xe5,
+ 0x0d,0x0c,0x02,0x05,0xe5,0x13,0x01,0x0d,0x02,0x08,0xe5,0x11,0xe5,0x0f,0x10,0x02,
+ 0x1c,0xe7,0x1c,0x21,0x09,0x02,0x02,0x02,0x03,0xe5,0x02,0x02,0x02,0x03,0x0b,0x03,
+ 0x04,0x01,0x06,0x05,0xe5,0xe5,0x02,0x0a,0x02,0x06,0xe5,0x09,0x0c,0x01,0x07,0x01,
+ 0x01,0x05,0x03,0x10,0x02,0x01,0x06,0x05,0x03,0x04,0xe5,0x1f,0x07,0x01,0xe7,0x02,
+ 0xe5,0x28,0x03,0x05,0x03,0x04,0x0a,0x05,0x02,0x0a,0x08,0x02,0x01,0x04,0x01,0x0d,
+ 0x05,0x0a,0x0b,0x0c,0x05,0x0a,0x0d,0x05,0x05,0x03,0x09,0x03,0x03,0x28,0x02,0x13,
+ 0xe5,0xe6,0x01,0x01,0x03,0x14,0x05,0x13,0x05,0x03,0x01,0x0f,0x04,0x06,0x01,0xe5,
+ 0x03,0xe8,0x06,0x02,0x02,0x03,0xe6,0x02,0x0b,0x01,0x01,0x04,0x05,0x06,0x01,0x06,
+ 0xe7,0x06,0x01,0xe5,0x01,0x01,0x01,0x01,0xe5,0x05,0xe5,0x06,0xe5,0xe6,0x05,0xe7,
+ 0x07,0xe5,0x03,0x03,0x01,0x07,0x02,0x04,0xe6,0x06,0x09,0xe6,0x0c,0xe5,0x02,0xe5,
+ 0x01,0x1d,0x05,0x0a,0x08,0xe5,0x0f,0x03,0x04,0x0b,0x05,0x11,0xe5,0x03,0x0e,0x01,
+ 0x02,0x05,0x07,0x01,0xe5,0xe5,0x01,0x05,0x03,0xe5,0xe5,0xe5,0xe5,0x07,0x01,0x0b,
+ 0x05,0xe5,0x02,0x04,0x03,0xe5,0xe5,0xe5,0x08,0x05,0x03,0x05,0x04,0x04,0x05,0x08,
+ 0x10,0x02,0xe5,0x1b,0x12,0x04,0x09,0x05,0x01,0xe5,0x01,0x04,0x05,0x06,0x02,0x01,
+ 0x01,0x05,0x06,0x02,0x01,0x09,0x01,0x05,0x04,0x03,0x05,0x01,0x03,0x02,0x05,0xe5,
+ 0x02,0x13,0x04,0xe5,0x12,0x05,0x02,0xe5,0x08,0x01,0xe5,0x0e,0xe5,0x03,0x07,0x1e,
+ 0x02,0xe7,0x10,0x1e,0x17,0xe5,0x1f,0x20,0x0c,0x01,0x05,0x03,0x01,0x14,0x06,0x03,
+ 0x0a,0x04,0xe5,0x07,0x02,0x06,0xe5,0x0a,0x35,0xe6,0xe5,0x02,0x06,0x10,0x2a,0x02,
+ 0x10,0x01,0x05,0x01,0x01,0x06,0x1e,0x05,0x06,0x10,0x09,0x0e,0x0d,0x04,0xe5,0x05,
+ 0x04,0x09,0x16,0x0d,0x05,0x08,0x0d,0xe5,0xe6,0x16,0x0c,0x0f,0xe6,0x0a,0x04,0x08,
+ 0xe8,0x11,0x01,0x11,0x02,0x02,0x16,0xe8,0x0a,0x0f,0x03,0x0e,0x01,0x01,0x03,0x08,
+ 0x09,0x06,0xe5,0x0c,0xe7,0x04,0x01,0x08,0x0e,0x0e,0xe5,0xe5,0x17,0x17,0x05,0x02,
+ 0x1a,0x05,0x06,0x06,0x14,0x1b,0x03,0x04,0x01,0x14,0x06,0x06,0x02,0x03,0x0d,0x1e,
+ 0x05,0x2d,0xe8,0x23,0x01,0x09,0x09,0x06,0x01,0x08,0x04,0x02,0x0a,0x06,0x01,0x28,
+ 0x05,0x04,0xe5,0x01,0x06,0x02,0x06,0x08,0x09,0xe5,0x15,0xe5,0x0b,0x01,0xe5,0x02,
+ 0x04,0x08,0x06,0xe5,0x25,0x01,0xe5,0x2e,0x0a,0x12,0x07,0x02,0x09,0x06,0x04,0x09,
+ 0x14,0x0c,0x02,0xe5,0x05,0x01,0x06,0x0b,0x02,0xe5,0x04,0x01,0xe6,0x01,0x03,0x03,
+ 0x0d,0x01,0x06,0x02,0x01,0x02,0x01,0x02,0x09,0x07,0x01,0x0c,0x15,0xe8,0x30,0x21,
+ 0xe5,0x02,0x0f,0x1b,0x11,0x07,0x14,0x1a,0x16,0x07,0x07,0xe5,0x09,0x0c,0x08,0xe5,
+ 0x14,0xe6,0xe7,0x17,0xe5,0x0e,0x16,0xe5,0x11,0x06,0x02,0xe5,0x07,0xe8,0x01,0x02,
+ 0xe5,0x07,0x03,0xe5,0x04,0x05,0x0c,0x02,0x0a,0x07,0x09,0xe5,0xe6,0x04,0x09,0xe5,
+ 0x07,0xe6,0x09,0xe5,0x04,0x03,0xe5,0x0d,0xe5,0x15,0x01,0x03,0xe5,0x09,0xe6,0xe7,
+ 0x01,0x01,0x15,0x10,0x10,0x01,0x04,0x02,0xe5,0x14,0x03,0x05,0xe5,0x01,0x02,0xe5,
+ 0xe5,0x02,0x05,0xe5,0x04,0x01,0xe6,0x01,0x05,0x0a,0x01,0x01,0x0d,0x01,0xe6,0x07,
+ 0xe5,0xe5,0x12,0x01,0xe6,0x06,0x04,0xe5,0x03,0xe5,0x08,0xe5,0x0e,0x05,0xe5,0x0d,
+ 0xe5,0x0d,0x01,0x04,0xe6,0x03,0x26,0x13,0x01,0x1b,0x0b,0x02,0x04,0x0b,0x09,0x07,
+ 0x05,0xe5,0x03,0x01,0x02,0xe6,0x03,0x09,0x09,0x04,0x01,0x05,0x01,0xe5,0x02,0x0b,
+ 0x07,0x04,0x01,0x0a,0x01,0x04,0x01,0x06,0xe5,0x01,0x01,0x09,0x0b,0x07,0x04,0xe5,
+ 0xe6,0x01,0x28,0x10,0x02,0x01,0x1b,0x09,0x09,0x09,0x09,0x09,0x05,0xe5,0x03,0x06,
+ 0xe5,0xe5,0x08,0x09,0x10,0xe5,0xe5,0x05,0xe5,0x0a,0x10,0xe5,0xe5,0xe5,0x0d,0x02,
+ 0x01,0x04,0xe5,0xe5,0x16,0x03,0x02,0x2b,0x11,0x0b,0x01,0x11,0x0b,0x04,0x01,0xe5,
+ 0x0a,0x04,0x01,0x02,0x02,0x01,0x01,0x05,0x0b,0x04,0x04,0x01,0x01,0x02,0x03,0x02,
+ 0x02,0x0a,0x19,0xe5,0xe5,0x03,0x01,0x1c,0xe5,0x01,0x0d,0x02,0x11,0x02,0xe5,0x01,
+ 0x28,0x03,0x13,0x05,0x01,0x01,0x0f,0x03,0x05,0x03,0x01,0x02,0xe5,0x02,0x05,0x03,
+ 0x01,0x02,0xe5,0x02,0x01,0x02,0x04,0x06,0x04,0x07,0x02,0x03,0xe5,0x02,0x02,0x01,
+ 0xe5,0x02,0x01,0x02,0xe5,0x02,0x04,0x04,0x01,0x02,0x04,0x01,0x01,0xe6,0xe5,0xe5,
+ 0x08,0x09,0x09,0x02,0xe7,0x02,0x01,0x02,0x04,0x13,0x02,0x02,0xe6,0x26,0x02,0x13,
+ 0x01,0x07,0x01,0x11,0x06,0x01,0x02,0x07,0x04,0x06,0x03,0xe5,0x03,0x01,0x09,0x0e,
+ 0x02,0x01,0x05,0x03,0x03,0xe5,0x03,0x02,0x0c,0x03,0x07,0x01,0x07,0x01,0x07,0x06,
+ 0x02,0x01,0x09,0x02,0x04,0x01,0x09,0x17,0xe6,0x01,0x27,0xe6,0xe5,0x12,0x01,0x07,
+ 0x01,0x0d,0xe5,0x01,0x06,0x01,0xe5,0x08,0x09,0x06,0x02,0x04,0x01,0x01,0x0b,0x04,
+ 0xe5,0xe6,0xe5,0xe5,0x01,0xe6,0x01,0x06,0x02,0x05,0xe5,0x04,0x06,0x0b,0x03,0xe5,
+ 0x01,0x01,0x07,0x06,0xe5,0xe5,0xe5,0x06,0x09,0x01,0x07,0x17,0xe5,0xe5,0xe7,0x44,
+ 0x09,0x33,0x04,0x0c,0x08,0x02,0x01,0xe5,0x05,0x0b,0x0e,0x02,0x02,0x06,0x02,0x06,
+ 0x15,0x07,0x02,0x1a,0x02,0x12,0xe7,0x45,0xe6,0x06,0x01,0x25,0x0f,0xe5,0x0b,0x01,
+ 0x05,0xe5,0x01,0x09,0xe6,0x16,0x03,0xe5,0x07,0xe5,0x09,0x1b,0x31,0xe5,0xe7,0x0d,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x05,0x03,0x09,0xe6,0x03,
+ 0x02,0x03,0x04,0x02,0xe5,0x01,0x05,0x04,0x01,0x02,0x09,0x09,0xe5,0x02,0x01,0x02,
+ 0x04,0x01,0x02,0x06,0x02,0x09,0x06,0x02,0x02,0x02,0x03,0x02,0x06,0x04,0x01,0x02,
+ 0x09,0x0d,0x02,0x01,0x02,0x88,0x0c,0x15,0x13,0x09,0x09,0x06,0x0c,0x06,0x0c,0x09,
+ 0x09,0x18,0x06,0x97,0x02,0x04,0x0d,0x11,0x09,0x09,0x13,0x15,0x08,0x08,0x1e,0xe5,
+ 0xe6,0xe5,0x11,0x09,0x1d,0x01,0xe5,0xe5,0x03,0x02,0x01,0x09,0x0e,0x04,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0xe7,0x0a,0x04,0x02,0xe6,0xe5,0x01,0x01,0x02,0x06,0x04,0x04,
+ 0x09,0xe6,0x01,0x02,0x01,0x04,0x0e,0x04,0x04,0x09,0x09,0x09,0x09,0x16,0x03,0xe6,
+ 0x3e,0x01,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe5,0x11,0xe5,0x05,0x01,0xe5,0x02,0x02,
+ 0x01,0xe5,0x05,0x01,0xe6,0x08,0x04,0x02,0x02,0xe5,0x04,0x01,0x01,0x02,0x02,0x02,
+ 0x08,0xe5,0x0c,0x02,0x01,0x01,0x02,0x05,0x06,0x01,0xe5,0x08,0x09,0x05,0x03,0x03,
+ 0x02,0x01,0xe5,0x05,0x02,0x17,0xe8,0x45,0x09,0x04,0x04,0x0b,0x02,0x04,0x0c,0x01,
+ 0x07,0x01,0x01,0x01,0x0e,0x04,0x02,0x0e,0x09,0x13,0x06,0x02,0x09,0x09,0x04,0x01,
+ 0x0c,0x09,0x22,0x01,0x01,0x14,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0x03,0x01,0xe5,0x05,0x01,0x01,
+ 0x01,0x05,0xe6,0xe5,0x02,0x01,0xe5,0x07,0xe5,0x09,0xe5,0x05,0xe6,0xe5,0x06,0xe5,
+ 0x01,0x05,0xe5,0x02,0x04,0xe6,0xe5,0x02,0xe8,0x06,0xe6,0xe5,0x02,0xe5,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x05,0x01,0xe6,0xe5,0x02,0xe7,0x07,0xe5,0x07,0xe5,0x06,0x03,0x16,
+ 0x03,0x09,0xe5,0x11,0x04,0x01,0x01,0x07,0x01,0x09,0xe5,0x08,0xe5,0x06,0xe5,0x03,
+ 0x01,0x01,0x03,0x01,0x04,0x0c,0x01,0x01,0x02,0x0b,0x08,0x05,0x03,0x09,0xe6,0x0e,
+ 0x01,0x0a,0xe5,0x06,0x03,0xe5,0x03,0x13,0xe5,0x03,0xe5,0x01,0xe5,0x01,0xe5,0xe5,
+ 0x01,0x19,0x01,0xe5,0x37,0x02,0x03,0x01,0x07,0x01,0x09,0xe5,0x11,0xe5,0x01,0x03,
+ 0x01,0x06,0x03,0x0a,0x07,0x02,0x06,0x04,0x06,0x02,0x01,0x01,0xe5,0x0a,0x11,0x01,
+ 0x01,0x04,0x0a,0x01,0x06,0x17,0x02,0x02,0xe5,0xe5,0x04,0xe6,0x19,0x03,0x14,0x05,
+ 0x22,0x17,0x13,0x05,0x09,0x13,0x04,0x07,0x03,0x08,0x03,0x01,0x03,0x09,0x13,0x03,
+ 0xe6,0x0c,0x05,0xe5,0x01,0x13,0x05,0x03,0xe5,0x03,0x1e,0x01,0x0c,0x07,0x05,0x09,
+ 0x13,0x02,0x06,0x09,0x08,0xe5,0x08,0x08,0xe5,0x01,0x06,0x02,0xe5,0x04,0x0c,0x0f,
+ 0x0b,0x04,0x02,0x02,0x08,0xe5,0x11,0x03,0xe7,0x02,0x06,0x01,0x03,0x06,0x09,0x09,
+ 0x02,0xe5,0x01,0x01,0xe5,0x02,0x21,0x1e,0x06,0x05,0x01,0xe5,0x2d,0xe5,0xe6,0x0e,
+ 0x01,0xe5,0x19,0x02,0x07,0xe5,0x01,0x0b,0x18,0x02,0xe5,0x02,0x0b,0xe5,0xe5,0x0f,
+ 0xe5,0xe5,0x27,0x13,0x02,0xe6,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x04,0x02,
+ 0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x01,0x05,0x01,0x01,0x01,0x03,0x01,
+ 0x07,0x01,0x03,0x03,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x07,
+ 0x01,0x01,0x04,0xe5,0xe5,0xe5,0x04,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x01,0x01,
+ 0x03,0x01,0x06,0xe5,0xe5,0x02,0x03,0x01,0x07,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,
+ 0xe6,0x04,0x01,0x07,0x01,0x01,0x06,0x04,0xe5,0x19,0x19,0x18,0x0b,0x01,0x0d,0xe5,
+ 0x02,0x04,0xe5,0xe5,0x02,0x06,0xe5,0xe5,0x01,0xe6,0x04,0xe8,0x02,0x05,0x25,0xe5,
+ 0x03,0x02,0x04,0xe5,0x1f,0x0e,0x08,0x22,0x03,0xe5,0x15,0x10,0x1d,0x08,0x08,0xe5,
+ 0x01,0x08,0x01,0x01,0x04,0x01,0xe5,0x0c,0x01,0xe5,0x02,0xe5,0x05,0xe5,0x06,0x08,
+ 0xe5,0xe5,0x09,0x0e,0x0b,0x13,0x09,0x07,0xe5,0xe5,0x0b,0x0b,0x21,0xe6,0xe6,0x3d,
+ 0x09,0x05,0x0c,0x09,0x04,0x01,0x05,0x07,0x09,0x05,0x03,0x01,0x01,0x02,0x02,0x03,
+ 0x02,0x01,0x20,0x09,0x09,0x58,0x02,0x05,0x03,0x42,0x13,0x09,0x0d,0x02,0x02,0x06,
+ 0x02,0xe5,0x04,0x01,0x04,0x04,0x01,0x03,0x03,0x01,0xe5,0x08,0x0b,0x06,0xe5,0x05,
+ 0x09,0xe6,0x0a,0x09,0x02,0x04,0xe5,0x0e,0x26,0xe7,0x04,0x02,0x35,0x12,0x0a,0x09,
+ 0x0f,0x06,0x06,0x02,0x0a,0x04,0x07,0x04,0x02,0x0f,0x18,0x07,0x10,0x07,0x03,0x3b,
+ 0xe5,0x12,0x09,0x09,0x27,0x0f,0x03,0x0e,0xe5,0x17,0x02,0x09,0x03,0x07,0x01,0x12,
+ 0xe5,0x01,0x04,0xe6,0x09,0x28,0x15,0x1f,0x02,0x01,0xe5,0x01,0x06,0x07,0x05,0x09,
+ 0x09,0x09,0x09,0x04,0x06,0x07,0x06,0xe6,0x06,0x01,0x02,0xe5,0x0f,0x0a,0x08,0x08,
+ 0xe5,0xe5,0x05,0x01,0x02,0x0c,0x0b,0x01,0x01,0x12,0x06,0x01,0xe5,0x12,0x09,0x2b,
+ 0x01,0x01,0x64,0x0a,0x05,0x1f,0x03,0x01,0x0c,0x05,0x11,0x1b,0x0d,0x08,0xe5,0x03,
+ 0x2e,0x05,0x01,0x01,0x08,0x0d,0x09,0x09,0x09,0x09,0x09,0xe7,0x04,0xe5,0x09,0xe5,
+ 0x0c,0x18,0xe5,0x04,0x01,0x09,0xe5,0xe6,0xe5,0x05,0x01,0x02,0x04,0xe5,0x07,0xe5,
+ 0x06,0x08,0xe7,0x07,0xe6,0x06,0xe5,0x1e,0x06,0xe6,0x06,0xe5,0x0c,0x05,0x05,0xe5,
+ 0x01,0x01,0x07,0x42,0xe5,0xe5,0x0c,0xe5,0x02,0x09,0x18,0xe5,0x11,0x04,0x05,0x0a,
+ 0x02,0xe5,0x04,0x02,0x0a,0x05,0x02,0x07,0x0b,0x27,0x06,0x01,0x01,0x10,0x06,0xe5,
+ 0xe5,0x09,0x05,0x0c,0x09,0x09,0x09,0x01,0x08,0x02,0x01,0x0d,0x03,0x01,0x09,0x07,
+ 0x01,0x0a,0x17,0x05,0x03,0xe6,0x01,0x01,0x03,0xe5,0x04,0x03,0x04,0xe5,0x11,0x03,
+ 0x05,0x08,0xe5,0x08,0xe5,0xe5,0x1e,0x09,0x06,0x0f,0xe6,0x07,0xe5,0x53,0x13,0x02,
+ 0x09,0x03,0x05,0x09,0x12,0x06,0x08,0x03,0x01,0x09,0x07,0x01,0x02,0x04,0x05,0x03,
+ 0x09,0x0c,0x0b,0x24,0x01,0x01,0xe5,0xe5,0x44,0x18,0x07,0xe5,0x09,0x27,0x09,0x02,
+ 0x10,0x03,0x13,0xe5,0x07,0x09,0x05,0xe6,0x1a,0x1b,0x07,0x01,0xe5,0xe8,0x0d,0xe5,
+ 0x0a,0xe5,0x04,0xe5,0x2d,0x0c,0x05,0x06,0xe5,0xe5,0x08,0x05,0xe5,0x05,0x0b,0xe5,
+ 0x07,0x09,0x0c,0x01,0x04,0x08,0x06,0x0d,0x09,0x02,0xe5,0x03,0xe8,0x12,0x01,0x04,
+ 0x1e,0x01,0x01,0x01,0x02,0x01,0x0c,0x0c,0xe5,0x2d,0x0e,0xe5,0xe5,0x05,0xe5,0x02,
+ 0x01,0x01,0xe5,0x12,0xe5,0x04,0x01,0x05,0x05,0x03,0x09,0x0b,0xe6,0x15,0x0c,0x03,
+ 0x01,0x03,0x03,0xe5,0x11,0x01,0x07,0x01,0x20,0x01,0x03,0x02,0x04,0x20,0x20,0xe5,
+ 0xe5,0xe5,0x0c,0xe5,0x0b,0x01,0x02,0x01,0x01,0xe5,0xe6,0x02,0x01,0xe5,0xe5,0x08,
+ 0x01,0x05,0x01,0x18,0x01,0x01,0xe5,0xe5,0x0a,0x0f,0x1a,0xe5,0xe5,0xe5,0xe5,0x1c,
+ 0x15,0xe5,0x03,0x04,0xe5,0x01,0x02,0x46,0x01,0x1b,0x01,0x04,0x02,0xe6,0x06,0x09,
+ 0x05,0xe5,0x01,0x01,0x1d,0x01,0x0e,0x02,0x09,0x1a,0x02,0x01,0x3d,0x04,0xe6,0xe5,
+ 0x5c,0x02,0x03,0xe5,0xe5,0x04,0xe5,0x02,0xe6,0x03,0x08,0x02,0x02,0x09,0x06,0x01,
+ 0x02,0x04,0x01,0x02,0x09,0x04,0x01,0x02,0x02,0x0b,0x04,0x09,0x04,0x01,0x02,0x02,
+ 0x10,0x09,0x09,0x09,0x14,0xe6,0xe6,0x01,0x4a,0x0f,0x04,0xe5,0xe7,0xe5,0xe5,0xe5,
+ 0xe6,0x02,0x0d,0xe7,0x02,0x02,0x01,0x04,0x06,0xe5,0xe5,0xe5,0x04,0x01,0x01,0x09,
+ 0x05,0x01,0x01,0x09,0x01,0x02,0xe5,0x02,0x0f,0x01,0x01,0x09,0x3b,0x03,0xe5,0xe5,
+ 0x01,0x46,0x01,0x11,0x01,0x07,0x01,0x07,0x01,0xe5,0x02,0x01,0xe5,0xe5,0x08,0x07,
+ 0x01,0x04,0x04,0x01,0x07,0x01,0x04,0x02,0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0x09,
+ 0xe6,0x01,0x06,0x01,0x04,0x05,0x01,0x07,0x01,0x0d,0xe5,0x05,0x02,0x01,0x04,0x02,
+ 0x08,0xe5,0x11,0x04,0x49,0x01,0x0e,0x01,0xe5,0xe5,0x01,0x04,0x01,0x07,0x01,0x01,
+ 0x02,0x01,0xe5,0x08,0x03,0xe7,0x01,0x01,0x01,0xe5,0xe7,0x01,0x01,0x01,0xe5,0x03,
+ 0x01,0x01,0xe5,0x01,0x01,0x01,0x02,0xe6,0x01,0x01,0x02,0x0a,0xe5,0x01,0x03,0xe5,
+ 0xe5,0xe5,0x04,0x01,0x01,0xe5,0xe5,0xe6,0x03,0x01,0x0b,0xe5,0x08,0x01,0x01,0x05,
+ 0x01,0xe5,0x04,0xe7,0x12,0x01,0x01,0x09,0x63,0x02,0x03,0x13,0x02,0x02,0x03,0x0b,
+ 0x09,0x09,0x09,0x13,0x09,0x09,0x13,0x09,0x09,0x04,0x04,0x16,0x02,0xe6,0x09,0x01,
+ 0x57,0x09,0xe5,0x03,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x15,0xe9,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x02,0x05,0x03,0x06,
+ 0x02,0xe5,0x04,0x02,0x09,0xe5,0x07,0xe5,0x04,0x04,0xe5,0x07,0xe5,0x07,0xe6,0x06,
+ 0xe6,0x03,0x02,0x09,0xe5,0x07,0xe6,0x06,0xe5,0x07,0x09,0xe5,0x07,0xe6,0x06,0xe6,
+ 0x06,0xe5,0x07,0x0d,0xe5,0x01,0xe5,0x01,0x4f,0x06,0x0c,0x08,0xe5,0x05,0x1d,0x29,
+ 0x02,0x63,0x04,0x03,0x01,0xe5,0x50,0x12,0x0a,0x19,0x09,0x0b,0x09,0x16,0x10,0x13,
+ 0x13,0x1d,0x0d,0x0a,0x01,0x01,0x44,0x04,0x09,0x04,0x02,0x01,0x02,0x04,0x01,0x0a,
+ 0xe5,0x06,0x07,0x01,0xe7,0x03,0x01,0xe7,0x04,0x02,0xe7,0x05,0xe7,0x03,0x01,0xe7,
+ 0x02,0x02,0xe7,0xe5,0x0d,0xe7,0x05,0xe7,0x05,0xe7,0x05,0x0a,0x01,0x07,0x01,0x07,
+ 0xe6,0xe5,0x04,0x01,0x16,0xe7,0x4a,0xe5,0x02,0x02,0x01,0xe5,0x02,0x04,0x01,0x07,
+ 0xe5,0x02,0x06,0x01,0x03,0x03,0x01,0x03,0x01,0xe6,0x03,0xe5,0xe7,0x06,0x02,0xe5,
+ 0x06,0xe6,0x01,0x02,0x01,0xe6,0x06,0xe6,0x07,0xe5,0x03,0x02,0xe6,0x06,0xe6,0x06,
+ 0xe6,0x06,0xe5,0x09,0x09,0x09,0x09,0x17,0x01,0xe5,0x07,0x3f,0x02,0x09,0x09,0x03,
+ 0x03,0x01,0x0d,0xe5,0x03,0x03,0x07,0x05,0x01,0x0b,0x09,0x01,0x05,0x01,0xe5,0x07,
+ 0xe5,0x11,0xe5,0x04,0x02,0x01,0x01,0x02,0x02,0x09,0x0d,0x11,0x20,0x03,0x15,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe5,
+ 0x05,0x01,0xe5,0x01,0x05,0xe5,0x02,0x04,0xe6,0x06,0xe5,0x05,0xe6,0xe5,0xe6,0x01,
+ 0xe5,0x02,0xe5,0x01,0x03,0xe5,0x02,0x03,0xe8,0xe5,0x03,0xe6,0x01,0x05,0xe5,0x07,
+ 0xe5,0x01,0x03,0xe7,0x01,0x05,0xe5,0x01,0xe5,0x01,0xe7,0x01,0x05,0xe5,0x07,0xe5,
+ 0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x03,0x46,0xe5,0x05,0x01,
+ 0xe6,0x04,0x01,0x05,0x0b,0x0b,0x07,0x01,0xe5,0x03,0x04,0x0a,0xe5,0x07,0xe5,0x08,
+ 0x03,0x04,0xe5,0x07,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x1e,0x09,0x17,0xe6,0xe5,
+ 0x4a,0xe5,0x05,0x01,0x09,0x03,0x19,0x02,0x04,0x01,0xe5,0xe6,0x01,0x05,0xe5,0x01,
+ 0x01,0xe5,0x03,0x03,0x02,0x02,0xe5,0x01,0x05,0x03,0x02,0x02,0x04,0x04,0x06,0x02,
+ 0xe5,0x01,0x02,0x02,0x06,0x02,0xe5,0x01,0x02,0x0c,0x09,0xe5,0x01,0x03,0x01,0xe5,
+ 0x01,0x03,0x01,0x15,0xe5,0x01,0x09,0x41,0x07,0x01,0x09,0x05,0x01,0x01,0x07,0x0b,
+ 0x0e,0xe5,0x03,0x03,0xe5,0x04,0xe5,0x02,0x04,0xe5,0x02,0xe5,0x03,0x08,0xe5,0x07,
+ 0x09,0xe5,0x02,0xe5,0x02,0xe5,0x07,0xe5,0x02,0xe5,0x02,0x18,0xe5,0x07,0xe5,0x1c,
+ 0xe7,0x4a,0xe5,0x05,0x01,0xe5,0x0a,0xe5,0x04,0x0c,0x06,0x0d,0x09,0x05,0x0b,0x03,
+ 0x01,0xe5,0x06,0x01,0x02,0x07,0x0b,0x03,0x01,0xe5,0x01,0x09,0x03,0x01,0xe5,0x01,
+ 0x17,0x01,0xe5,0x05,0x01,0xe5,0x1e,0xe5,0x58,0x0c,0x09,0x02,0x06,0x02,0x1b,0x04,
+ 0x0c,0x10,0x05,0x02,0x07,0x01,0x0a,0x3e,0x14,0xe7,0x01,0x0e,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,0x01,0x05,
+ 0x01,0x04,0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x01,0x05,0x01,0xe6,0x06,
+ 0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0xe6,0xe5,0x04,
+ 0x01,0x01,0x05,0x01,0x01,0x05,0xe6,0xe5,0x04,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0x06,0xe5,0xe5,0x09,0x03,0x10,0x0f,0x09,0x1c,0x19,0x0b,0xe5,0x01,0xe5,0x01,
+ 0x01,0x03,0x08,0x0c,0x03,0x07,0xe5,0x08,0x08,0xe6,0x06,0xe5,0x05,0xe5,0x01,0x13,
+ 0x07,0x13,0xe6,0x06,0x13,0xe6,0x02,0x12,0x01,0x01,0xe5,0x07,0x04,0x38,0x06,0x01,
+ 0x07,0x0c,0x07,0x09,0x01,0x07,0x07,0x01,0x07,0x01,0x06,0x04,0x01,0x02,0x02,0x06,
+ 0x04,0x03,0x04,0x07,0x16,0x09,0x0d,0x06,0x16,0x06,0x07,0x0a,0xe6,0x01,0x0c,0x45,
+ 0x03,0x05,0x03,0x0b,0x1d,0x03,0x02,0x01,0xe5,0x02,0x04,0x03,0x0f,0x08,0x02,0x08,
+ 0x1b,0x04,0x0e,0x09,0x06,0x0c,0x1a,0xe5,0xe6,0x4c,0x04,0x01,0x02,0x03,0x03,0x02,
+ 0x03,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x02,0x09,0x02,0xe7,0x02,0x11,0x04,
+ 0x03,0xe5,0x02,0x0e,0x01,0x08,0x09,0x02,0x14,0x3a,0xe5,0xe7,0x12,0x09,0x49,0x01,
+ 0x09,0x02,0x07,0x03,0xe5,0x08,0x0b,0x05,0x0f,0x05,0x02,0x10,0x09,0x5b,0x02,0xe5,
+ 0x0f,0x1c,0x0c,0x09,0x1c,0x03,0x0a,0x01,0xe5,0x05,0x05,0x0d,0x01,0x02,0x04,0x04,
+ 0x01,0x06,0x14,0x06,0x0b,0x09,0x04,0x01,0x0f,0x16,0x25,0x02,0x01,0x08,0x09,0x11,
+ 0x13,0x09,0x04,0x04,0x0f,0x0d,0xe5,0x03,0xe5,0x0b,0x09,0x06,0xe6,0x12,0x02,0x1a,
+ 0x01,0x02,0x03,0xe5,0x08,0x02,0x02,0x1a,0x13,0x13,0x0d,0x01,0x01,0x06,0x0e,0x50,
+ 0x05,0x01,0x04,0xe5,0x02,0x11,0x08,0x05,0x0b,0x02,0x01,0x15,0x09,0x02,0x02,0x08,
+ 0xe5,0x1f,0x34,0xe6,0x07,0x0a,0x2a,0x09,0x09,0x04,0x02,0x01,0x03,0x06,0xe6,0x0b,
+ 0x0d,0x0b,0x08,0xe5,0x02,0xe5,0x03,0xe6,0x10,0x01,0x02,0xe5,0x03,0xe6,0x0b,0x0a,
+ 0x0d,0x03,0x04,0x05,0x03,0x09,0x23,0x01,0xe5,0x01,0x6a,0xe5,0x1e,0x01,0xe5,0x01,
+ 0x03,0x03,0xe5,0x07,0x01,0xe5,0x14,0x05,0x02,0x01,0x16,0x0c,0x42,0xe6,0xe6,0x36,
+ 0x02,0x09,0x01,0x07,0x14,0x0e,0xe6,0x09,0x01,0x01,0x07,0x09,0x09,0xe7,0x03,0x09,
+ 0x0c,0xe5,0x07,0x02,0x06,0xe5,0x01,0x01,0x2b,0x06,0x02,0x1f,0x01,0xe5,0x57,0x19,
+ 0xe6,0x02,0x01,0x03,0xe5,0x02,0x03,0x02,0x0a,0x02,0x11,0x09,0x07,0x12,0x07,0x01,
+ 0x0b,0x04,0x05,0x3f,0x01,0x4d,0x25,0x13,0x10,0x06,0x2a,0x03,0x03,0x08,0x02,0x1a,
+ 0x35,0x01,0xe5,0xe6,0x05,0xe5,0x04,0xe5,0x25,0xe5,0x25,0x01,0x04,0x09,0x04,0xe6,
+ 0x01,0x04,0x09,0x0a,0xe5,0x03,0x02,0x09,0x02,0xe5,0x04,0xe5,0x04,0x02,0xe5,0x07,
+ 0xe5,0x15,0xe5,0x03,0xe5,0x15,0xe5,0x03,0xe5,0xe6,0x04,0x1f,0x01,0xe5,0x01,0xe5,
+ 0xe5,0xe5,0x04,0x01,0x2c,0x2a,0x01,0x05,0x04,0xe6,0x06,0x09,0x10,0xe5,0x01,0xe5,
+ 0x0d,0xe6,0x0b,0x02,0x01,0x01,0x01,0x03,0x10,0xe5,0x0c,0x1f,0xe5,0x20,0x01,0x03,
+ 0xe5,0xe5,0x01,0x01,0x0c,0x55,0x01,0x09,0x07,0x06,0x01,0x02,0x13,0x17,0x05,0x0e,
+ 0x01,0x01,0x06,0xe5,0x0b,0x01,0x01,0x1d,0x02,0x01,0xe5,0xe5,0x01,0x15,0x01,0x02,
+ 0x05,0x02,0x02,0x61,0xe5,0xe5,0x08,0x01,0x07,0x06,0x02,0x01,0x13,0x1d,0x10,0x09,
+ 0x09,0xe5,0xe5,0xe5,0x24,0x01,0x17,0xe5,0x05,0x05,0xe7,0x64,0x04,0x01,0x01,0x05,
+ 0xe5,0x01,0xe5,0x03,0x02,0x0a,0xe5,0xe5,0x01,0x05,0xe5,0x08,0x01,0x11,0x09,0x01,
+ 0x05,0x03,0x02,0x01,0xe6,0x06,0x01,0x4c,0xe6,0x01,0x02,0x06,0x02,0x5e,0x01,0x02,
+ 0x05,0x01,0x01,0xe5,0x02,0x05,0x07,0xe6,0xe5,0xe5,0x06,0x03,0x05,0x01,0x01,0x0f,
+ 0x03,0x05,0x01,0x01,0x05,0x04,0x01,0x01,0x07,0x01,0x04,0x27,0x1d,0x03,0xe7,0x01,
+ 0x60,0xe5,0x01,0x01,0x01,0x0f,0x06,0x04,0x05,0x01,0x01,0x04,0x04,0x06,0x01,0xe5,
+ 0xe5,0x03,0x0c,0x09,0x01,0x1b,0x01,0x22,0x01,0xe5,0xe5,0x0d,0x01,0x10,0x03,0xe5,
+ 0xe6,0x5f,0xe5,0x01,0x04,0x0e,0x03,0xe5,0x01,0x01,0x01,0x07,0x01,0x01,0xe5,0x01,
+ 0x03,0x09,0x01,0x04,0xe6,0x09,0x09,0x01,0x1b,0x01,0x25,0x01,0x03,0xe5,0x07,0xe5,
+ 0x14,0xe7,0x68,0x13,0x02,0x09,0xe5,0x04,0x0e,0xe5,0x1b,0x09,0x02,0x06,0xe5,0x07,
+ 0xe5,0x4d,0x01,0x01,0xe5,0x59,0xe5,0x07,0x05,0xe5,0x01,0x0f,0xe5,0x03,0x04,0x08,
+ 0xe5,0x01,0xe5,0x29,0x11,0x06,0x02,0x31,0x1f,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x05,0x03,0xe6,0x02,0xe5,0x01,0x09,0xe5,0x07,0x09,0xe5,0x09,0x02,
+ 0x06,0x04,0x01,0x02,0x09,0x09,0x06,0x02,0x03,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x01,
+ 0x09,0x09,0x09,0x09,0x05,0x03,0x09,0x0d,0x04,0x66,0x08,0xe5,0x3c,0x1c,0xe5,0x08,
+ 0x09,0x4a,0x02,0xe8,0x62,0x0b,0x0f,0x13,0x19,0x1d,0x08,0x08,0x50,0xe8,0x31,0x20,
+ 0x01,0x07,0x01,0x09,0xe7,0xe5,0x0b,0x01,0xe5,0xe5,0xe5,0x03,0x07,0x01,0xe5,0xe5,
+ 0x05,0x01,0x07,0x01,0x09,0x07,0x01,0x07,0x01,0x07,0x15,0x25,0x01,0x22,0x01,0x01,
+ 0x46,0x0c,0x01,0xe5,0x05,0x01,0xe5,0x05,0x02,0xe5,0x06,0x01,0x04,0xe5,0xe7,0x06,
+ 0x01,0x01,0x03,0x01,0xe6,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x02,0x05,0xe5,0xe6,
+ 0x02,0x02,0x01,0xe5,0x02,0x06,0x09,0x01,0x03,0x02,0x03,0x1d,0x02,0x01,0xe5,0x21,
+ 0x01,0xe6,0x11,0x53,0x01,0xe5,0x01,0x09,0x0a,0x04,0x03,0x02,0x07,0x01,0x0b,0xe5,
+ 0xe5,0x05,0x02,0x03,0x02,0x09,0x06,0x09,0x03,0x0b,0x03,0x14,0x08,0x28,0x01,0x01,
+ 0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x06,0xe5,0xe5,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x07,0x03,0x05,0xe5,0x07,0xe5,0x09,
+ 0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe8,0x37,0x13,
+ 0x06,0x01,0x07,0x01,0x04,0x04,0x11,0x01,0x07,0x01,0x07,0x01,0xe5,0x07,0x01,0x0a,
+ 0x08,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x15,0xe5,0x08,0x13,0xe5,0x04,0x01,0x0a,
+ 0xe5,0x15,0x01,0x01,0x38,0x1a,0x01,0x07,0x01,0x06,0xe5,0x0a,0x07,0x01,0x06,0xe5,
+ 0xe5,0x06,0x01,0xe5,0x06,0xe5,0xe5,0x09,0x06,0x09,0x01,0x07,0x01,0x1b,0x0c,0x1a,
+ 0x01,0x22,0xe6,0xe5,0x4b,0x32,0x09,0x09,0x1d,0xe5,0x08,0x1a,0x0b,0xe5,0x4c,0x38,
+ 0x13,0x17,0x07,0x06,0x02,0x0b,0x1b,0x09,0x06,0x02,0x09,0x09,0x0b,0x09,0x04,0x02,
+ 0x09,0x13,0x09,0x09,0x18,0xe8,0x65,0x03,0x05,0xe5,0xe5,0x05,0x02,0x06,0x14,0x01,
+ 0x01,0x17,0x02,0xe5,0xe5,0xe5,0x12,0x27,0x1c,0x1a,0x11,0x01,0x07,0x01,0x01,0x05,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,
+ 0x01,0x01,0x02,0x02,0x01,0x03,0x03,0x01,0x02,0xe5,0x02,0x01,0x01,0x05,0x01,0xe5,
+ 0xe5,0x03,0xe7,0xe5,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x01,0x01,0x03,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x0b,0xe5,0xe5,0x0b,0x1c,0xe5,0x0b,0xe5,
+ 0x0d,0x03,0x02,0x2c,0x01,0xe6,0x05,0x0a,0xe6,0x1c,0x01,0x07,0xe5,0x0e,0x0e,0x07,
+ 0xe5,0x29,0x20,0xe7,0x34,0x10,0x06,0x0a,0x09,0x02,0x04,0x08,0x04,0x01,0x13,0x07,
+ 0x11,0x07,0x03,0x03,0x03,0x02,0x15,0x06,0x02,0x01,0x01,0x02,0x09,0x02,0x08,0x0f,
+ 0x0d,0x08,0x08,0xe5,0x01,0xe5,0x35,0x13,0x21,0x0f,0x05,0x06,0xe5,0x01,0xe5,0xe5,
+ 0x23,0x02,0x01,0x0b,0x19,0x01,0x2f,0x09,0x15,0x04,0x29,0x34,0x03,0x01,0xe5,0x09,
+ 0x02,0x0a,0x01,0x01,0x04,0x09,0x0c,0x01,0x01,0xe5,0x0c,0x05,0xe5,0x07,0xe5,0x07,
+ 0x02,0x08,0x0c,0x04,0x03,0x07,0x07,0x04,0x21,0x01,0xe5,0x04,0xe5,0x65,0x01,0x0d,
+ 0x07,0x08,0x02,0x01,0x09,0x01,0xe5,0x05,0x03,0x01,0x0f,0x09,0x09,0x0a,0x05,0x21,
+ 0x09,0x24,0xe5,0x02,0xe5,0x01,0x0c,0x09,0x09,0x01,0x28,0x06,0x04,0x05,0x08,0x01,
+ 0x06,0x0a,0x02,0x03,0x01,0x08,0xe5,0x06,0x03,0x09,0x03,0xe6,0x02,0x02,0x06,0xe5,
+ 0x07,0x09,0x09,0x02,0x06,0x13,0x09,0x09,0x03,0x11,0x08,0x02,0xe5,0xe9,0x1d,0x0d,
+ 0x09,0x09,0x2e,0xe5,0x1e,0xe5,0x01,0xe5,0xe5,0x01,0x05,0x03,0x01,0xe5,0x01,0x03,
+ 0x06,0x02,0x09,0x01,0x02,0x04,0x01,0x07,0x05,0x03,0x01,0x11,0x01,0x07,0x05,0x03,
+ 0x01,0x0e,0x09,0x07,0x01,0x01,0xe5,0x07,0x15,0x52,0x0f,0x06,0x02,0x0b,0x01,0x05,
+ 0xe5,0x08,0x08,0x04,0x05,0x1e,0x01,0x07,0x12,0x01,0x31,0xe6,0xe6,0x48,0x18,0x03,
+ 0xe5,0x03,0x0a,0x06,0x0f,0xe6,0x01,0x03,0xe5,0xe7,0x06,0xe6,0x06,0xe5,0x08,0x04,
+ 0xe6,0x01,0x07,0xe7,0x05,0xe5,0xe5,0x05,0xe6,0x01,0x0e,0xe5,0xe5,0x06,0xe5,0x21,
+ 0x09,0xe5,0x01,0xe5,0x05,0x43,0x0c,0x0c,0x02,0xe5,0x23,0x04,0x02,0x03,0xe5,0x01,
+ 0x06,0x03,0x06,0x02,0x09,0x09,0x08,0x11,0x02,0x19,0xe5,0x01,0x2b,0x01,0xe7,0x07,
+ 0x0f,0x53,0x09,0x01,0x08,0x05,0x03,0x04,0x04,0x04,0x01,0x03,0xe5,0x01,0x01,0x03,
+ 0xe5,0x01,0x01,0x07,0x01,0x06,0xe5,0xe6,0x04,0x1d,0x03,0x01,0xe5,0x04,0x03,0xe5,
+ 0x03,0xe5,0x05,0x01,0xe5,0x1a,0x06,0xe5,0xe5,0x12,0x04,0xe5,0x0d,0x41,0x15,0x09,
+ 0x02,0x02,0xe5,0x08,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,
+ 0x04,0x01,0x01,0xe5,0x03,0x01,0xe5,0x10,0xe5,0xe5,0x05,0xe5,0x05,0xe5,0xe5,0x1a,
+ 0x07,0xe5,0xe5,0xe5,0x15,0x5c,0x09,0x11,0x17,0x13,0x39,0x02,0x06,0x15,0x10,0x07,
+ 0xe8,0x06,0xe5,0x04,0xe5,0x01,0x01,0x32,0x02,0xe5,0x14,0xe5,0x05,0x08,0xe5,0x01,
+ 0x01,0xe5,0x01,0xe5,0x01,0xe5,0x19,0xe5,0x07,0xe5,0x08,0xe7,0x05,0x02,0x01,0x04,
+ 0x01,0xe5,0x04,0xe5,0x08,0xe5,0x06,0x01,0x07,0xe5,0x0a,0xe5,0x05,0x01,0xe5,0x04,
+ 0x02,0xe5,0x04,0xe5,0x13,0x05,0x02,0x01,0x05,0xe5,0x06,0xe5,0x12,0x01,0x1e,0x02,
+ 0x20,0xe5,0x07,0xe5,0x01,0x06,0xe5,0x07,0x01,0x0b,0x03,0x09,0x09,0x02,0xe5,0x04,
+ 0x03,0xe5,0x03,0x03,0xe5,0x03,0x09,0x14,0x0b,0xe5,0x08,0x01,0x07,0xe5,0x16,0x01,
+ 0x02,0x02,0xe5,0x03,0x0c,0x37,0x04,0x1c,0x09,0x05,0x03,0x02,0xe5,0xe5,0xe5,0x07,
+ 0x05,0xe5,0x03,0x09,0x01,0x07,0x01,0x03,0x01,0x01,0x01,0x07,0x01,0x03,0xe5,0x01,
+ 0x01,0x03,0x01,0x01,0x01,0x03,0x01,0x01,0x01,0x11,0x04,0xe5,0x02,0x01,0xe5,0x01,
+ 0xe5,0x01,0x01,0x0a,0x0b,0xe5,0x03,0x04,0xe5,0xe6,0x01,0x46,0x31,0x06,0x02,0x01,
+ 0x0e,0x0a,0xe5,0x05,0x02,0xe5,0x07,0xe5,0x04,0x01,0xe5,0x07,0xe5,0x04,0x0a,0x09,
+ 0x0b,0xe5,0x08,0xe5,0x07,0xe5,0x03,0x16,0xe5,0x05,0x02,0x03,0x01,0x47,0x22,0x04,
+ 0x01,0x07,0x07,0x06,0x09,0x02,0x1b,0xe5,0x08,0x08,0xe5,0x12,0xe5,0x01,0x1b,0x01,
+ 0x04,0xe5,0x09,0x02,0x1a,0x04,0x02,0x46,0x03,0x23,0x01,0x01,0x05,0x03,0x09,0x09,
+ 0x04,0x01,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x02,0x01,0x04,
+ 0x04,0x04,0x13,0x04,0x04,0x09,0x02,0x01,0x18,0x02,0x01,0x01,0x02,0x46,0x04,0x0b,
+ 0x01,0x14,0x01,0x02,0x01,0x01,0xe5,0x03,0x01,0x01,0x04,0x06,0x02,0xe5,0x01,0x04,
+ 0x06,0x02,0x05,0xe6,0xe5,0x01,0x01,0xe6,0x01,0x06,0x02,0x02,0xe8,0x01,0x09,0x06,
+ 0x02,0x04,0xe5,0x0c,0x06,0x02,0x04,0xe5,0x02,0x22,0xe5,0xe5,0xe5,0x48,0x21,0xe5,
+ 0x03,0x01,0x07,0x18,0x01,0x01,0x13,0x01,0x05,0x08,0xe5,0xe5,0xe5,0x04,0xe6,0x0f,
+ 0xe5,0x09,0xe5,0x19,0xe5,0xe5,0xe5,0x06,0x01,0x1c,0xe7,0x08,0x02,0x5d,0x16,0xe5,
+ 0x07,0x05,0xe5,0x01,0xe5,0x05,0x03,0x02,0x02,0x03,0xe5,0x03,0xe5,0x07,0xe5,0x01,
+ 0x02,0x02,0xe5,0x01,0x02,0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x13,0x03,0x02,
+ 0x02,0xe5,0x01,0x02,0x02,0x03,0xe5,0x1b,0x04,0x0a,0xe5,0x5d,0xe5,0x15,0x0b,0x03,
+ 0xe5,0x0d,0x0f,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x11,0xe5,0x0b,0x13,0x05,0xe5,
+ 0x0b,0xe5,0x1d,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,
+ 0xe5,0x04,0x02,0x09,0x02,0x02,0x03,0x06,0x02,0xe6,0x03,0x04,0x05,0xe5,0x01,0x06,
+ 0x02,0xe6,0x02,0xe5,0x01,0xe5,0x02,0xe6,0x01,0xe6,0x03,0x02,0x04,0x01,0x02,0xe5,
+ 0x02,0x01,0x02,0x05,0x03,0x06,0x02,0x05,0x03,0xe5,0x04,0x02,0x09,0x09,0x0d,0x01,
+ 0x01,0xe5,0x01,0x63,0x08,0xe5,0x12,0x06,0x02,0x08,0xe5,0x09,0xe5,0x07,0xe5,0x05,
+ 0x13,0x02,0x13,0x10,0x02,0x09,0x06,0x02,0x1d,0x04,0x02,0x02,0xe5,0x62,0x07,0x02,
+ 0x13,0x0a,0x03,0x05,0x05,0x05,0x03,0x05,0x03,0x09,0x01,0x07,0x04,0x04,0x09,0x01,
+ 0x01,0x05,0x0e,0x04,0x05,0x03,0x01,0x02,0x04,0x17,0x0a,0xe5,0x01,0x01,0x06,0x10,
+ 0x36,0x18,0xe5,0xe5,0xe5,0x03,0x07,0x01,0x04,0x0f,0xe6,0x04,0x17,0xe6,0x06,0xe6,
+ 0x06,0x01,0x11,0xe6,0x24,0x01,0x2b,0x01,0x19,0xe5,0x4b,0x02,0xe5,0x04,0x02,0x03,
+ 0x02,0x01,0xe5,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x13,0x09,0x09,
+ 0x20,0x01,0xe6,0x12,0xe5,0x03,0x4a,0x04,0x09,0x4b,0xe5,0x6c,0x01,0x01,0x15,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x02,0x01,0xe5,0xe5,0x06,0xe5,
+ 0x06,0xe7,0x02,0x03,0xe6,0x02,0x04,0xe5,0x07,0xe5,0x05,0xe7,0x02,0x04,0xe5,0x05,
+ 0xe7,0x07,0xe5,0x07,0xe5,0x05,0xe7,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,
+ 0xe5,0x03,0x14,0x3c,0xe5,0x10,0xe5,0x07,0xe6,0x04,0x01,0xe6,0x11,0x02,0x0c,0x05,
+ 0xe5,0x01,0x05,0x03,0x05,0xe5,0x11,0x03,0x05,0xe5,0x07,0x03,0x0f,0x09,0x03,0x05,
+ 0x02,0x1f,0x01,0xe5,0x18,0x4d,0x02,0x06,0x09,0x01,0x10,0x05,0x03,0x01,0x05,0x03,
+ 0x05,0x03,0x05,0x03,0x05,0x09,0x09,0x03,0x05,0x07,0x01,0x03,0x0f,0x07,0x01,0x03,
+ 0x05,0x03,0x1b,0x01,0xe6,0x18,0x4f,0x09,0x13,0x05,0x04,0x04,0x13,0x01,0x04,0x1d,
+ 0x02,0x01,0x11,0x01,0x0e,0x0c,0x01,0x04,0x04,0x1d,0x02,0x19,0xe5,0x12,0x27,0x10,
+ 0x04,0x04,0x02,0x09,0x06,0x04,0x02,0xe5,0x07,0xe5,0x13,0xe5,0x08,0x1c,0xe5,0x0f,
+ 0x01,0xe5,0x19,0x01,0xe5,0x07,0xe5,0x1b,0x01,0xe6,0x31,0x15,0x06,0x28,0x01,0x0d,
+ 0x05,0x02,0x07,0xe5,0x01,0x03,0x02,0x02,0xe5,0x04,0x02,0x06,0x02,0x06,0x02,0x03,
+ 0x02,0x02,0x06,0x02,0x06,0x02,0x10,0x02,0x06,0x02,0x06,0x02,0x21,0xe5,0xe6,0x10,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0xe5,
+ 0xe5,0xe5,0x01,0x01,0xe5,0x05,0x01,0x01,0x05,0xe6,0x01,0x04,0x01,0x02,0x04,0x01,
+ 0x02,0x01,0x02,0x01,0x01,0x05,0xe6,0x04,0x01,0x01,0x01,0x05,0x01,0x01,0x01,0x03,
+ 0x01,0x01,0x05,0x01,0x01,0x01,0x03,0x01,0x01,0x01,0x03,0x01,0x01,0x01,0xe5,0x01,
+ 0x01,0x01,0x02,0x02,0x01,0x01,0x01,0xe5,0x01,0x01,0x01,0x07,0x01,0x01,0x03,0x01,
+ 0x01,0x05,0x01,0x01,0x02,0x02,0x01,0x01,0x07,0x01,0x01,0x05,0x01,0x0d,0xe5,0x27,
+ 0x06,0x3a,0x15,0x0d,0x02,0xe6,0x01,0x17,0x02,0xe6,0x08,0x07,0xe5,0x07,0xe5,0x03,
+ 0x07,0x0f,0xe5,0x07,0x05,0x04,0x2b,0x01,0x01,0xe5,0x19,0x15,0x09,0x09,0x06,0x02,
+ 0x01,0x07,0x0e,0x0b,0x04,0x15,0x02,0x07,0x0f,0x04,0x08,0x06,0x02,0xe5,0x01,0x02,
+ 0x03,0x04,0x18,0x13,0x05,0x09,0x0c,0x0d,0x02,0xe7,0xe5,0x02,0x37,0x01,0x13,0x11,
+ 0x08,0x02,0x08,0x11,0x05,0x02,0x1c,0x13,0x05,0x03,0x1e,0x04,0x03,0x01,0x35,0xe5,
+ 0x01,0xe5,0x0f,0x09,0x3a,0x05,0x2a,0x04,0x02,0x01,0x09,0x01,0xe5,0x05,0x01,0x0f,
+ 0x01,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0x01,0x06,0x06,0x01,0xe5,
+ 0x05,0x01,0x02,0x04,0x01,0x21,0x01,0xe7,0x15,0x27,0x22,0x04,0x09,0x14,0x09,0x01,
+ 0x07,0xe5,0xe5,0xe5,0x06,0x01,0x11,0x01,0x02,0x01,0x02,0x01,0x07,0x01,0x02,0x04,
+ 0x01,0x02,0x04,0x01,0x11,0x01,0x04,0x02,0x01,0x07,0x01,0x25,0xe5,0x0d,0x09,0x09,
+ 0x13,0x03,0x04,0xe5,0x02,0x04,0xe5,0x05,0x02,0x01,0x07,0x09,0x03,0x0e,0xe5,0x09,
+ 0x04,0x04,0x01,0x02,0x01,0x07,0x29,0xe5,0xe6,0x08,0x09,0x13,0x04,0x01,0x0c,0x08,
+ 0xe5,0x16,0xe5,0x01,0xe5,0x0c,0xe5,0x07,0xe5,0x07,0x13,0x01,0x14,0x07,0x01,0x03,
+ 0x02,0x02,0x09,0x10,0x17,0x02,0x07,0x09,0x09,0x0a,0x08,0x06,0x09,0xe5,0x07,0xe5,
+ 0xe5,0x0f,0x02,0x02,0x0d,0xe5,0x05,0x01,0x1c,0xe6,0x0e,0x04,0x02,0x09,0x02,0x13,
+ 0x26,0xe5,0x08,0x12,0x15,0x05,0xe5,0x19,0x17,0x09,0x09,0x13,0x02,0x04,0x0b,0x09,
+ 0x1a,0x01,0x01,0x01,0x1c,0x25,0x26,0x04,0x1c,0xe5,0x08,0xe5,0x43,0x28,0x26,0x01,
+ 0xe6,0x44,0xe5,0x2d,0x04,0x04,0x03,0x15,0xe5,0x92,0x02,0xe6,0x17,0x09,0x0b,0x07,
+ 0x09,0x0e,0x04,0x09,0x1d,0x03,0x07,0xe6,0x06,0xe6,0x07,0xe5,0x01,0x08,0x08,0xe5,
+ 0x08,0x09,0x03,0x01,0x02,0xe5,0x08,0x14,0x04,0x05,0x07,0x0f,0x18,0xe8,0x17,0x17,
+ 0x04,0xe6,0xe6,0x0f,0x08,0xe5,0x02,0x04,0xe5,0x02,0x05,0x02,0x09,0x09,0x08,0x10,
+ 0x04,0x2f,0x07,0x01,0x07,0x01,0x07,0x01,0x14,0x08,0x09,0x19,0x02,0x21,0x19,0x03,
+ 0x0b,0x09,0x09,0x09,0x11,0x2f,0x12,0x10,0x0b,0x0a,0x09,0x01,0x02,0x15,0x07,0xe5,
+ 0x19,0xe7,0x02,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x01,0x03,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x08,
+ 0x06,0xe7,0x03,0x01,0xe5,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x08,0x08,0xe5,0x07,0xe5,
+ 0x0b,0x03,0xe5,0x01,0x0b,0x01,0x05,0x01,0x01,0x02,0x05,0xe5,0x08,0x08,0xe5,0x08,
+ 0x09,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x01,0x02,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x01,0x03,0x08,0xe6,0x06,0xe5,0x04,0x03,0x07,0xe6,0x01,0x06,
+ 0x08,0x08,0xe6,0x06,0xe5,0x05,0x02,0xe5,0x03,0x04,0x09,0x09,0x09,0x0f,0x01,0x02,
+ 0xe5,0x03,0x06,0xe5,0x03,0x03,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0x07,0x06,0x02,0xe6,
+ 0x06,0xe5,0x02,0x04,0xe6,0xe5,0x01,0x02,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0x02,
+ 0x01,0x04,0xe6,0x06,0x09,0x01,0x09,0x01,0xe5,0x05,0x02,0x04,0xe6,0x08,0x02,0x03,
+ 0x02,0x07,0x01,0x01,0x04,0x02,0x06,0xe5,0xe6,0x07,0x09,0xe5,0x06,0xe5,0x06,0x01,
+ 0x09,0x09,0x10,0xe6,0x23,0x0b,0x25,0x09,0x09,0x16,0x05,0x02,0xe5,0x07,0x0c,0x05,
+ 0x03,0x06,0x13,0x12,0x07,0x02,0x08,0x02,0x03,0x02,0x0d,0x2b,0xe5,0x0e,0x05,0x03,
+ 0x09,0x09,0x09,0xe5,0x02,0x04,0x09,0x09,0x04,0x04,0x09,0x04,0x04,0xe5,0x07,0xe5,
+ 0x07,0x01,0x01,0x05,0xe5,0x09,0x09,0x08,0xe5,0x08,0x09,0x02,0x04,0x01,0x09,0x10,
+ 0x02,0x13,0x08,0xe5,0x08,0x09,0x0e,0x01,0x01,0x0d,0xe5,0x01,0x03,0x01,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x02,
+ 0x03,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x02,0x05,
+ 0x03,0x04,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x10,0xe6,0x0c,0x02,0x04,0x01,
+ 0x02,0x06,0x02,0x06,0x09,0x02,0x05,0xe5,0x01,0x05,0xe5,0x01,0x06,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x01,0xe5,0x02,0x09,0x02,0x06,0x06,0x02,0x08,0x01,0xe5,0x06,
+ 0x01,0x09,0x05,0x03,0x09,0x0a,0x02,0x05,0x02,0x01,0xe5,0x03,0x04,0x03,0x02,0x06,
+ 0x05,0x04,0x09,0x08,0x09,0x11,0x01,0xe5,0x0d,0xe5,0x07,0x09,0x09,0xe5,0xe5,0x05,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x07,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0x09,0x09,0x09,0xe5,0x07,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x0b,0xe5,0xe6,0x09,0x03,0x02,0x06,0x01,0x07,0x01,0x07,0x09,0x01,0x03,0x03,
+ 0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x04,0x04,0x01,0x07,0x04,
+ 0x04,0x04,0x06,0x05,0x03,0x05,0x03,0x09,0x09,0x13,0x13,0x04,0x04,0x03,0x11,0x07,
+ 0x03,0x05,0x0f,0x02,0xe5,0x18,0x09,0x04,0x0e,0x09,0x01,0x02,0x04,0x01,0x07,0x09,
+ 0x06,0x02,0x01,0x11,0x01,0xe5,0xe5,0x1f,0x06,0x17,0x05,0x01,0x02,0x03,0x08,0x06,
+ 0x02,0x09,0x10,0x04,0x04,0x24,0xe6,0xe5,0x0d,0x05,0x03,0x03,0x05,0x02,0x02,0x06,
+ 0x06,0x09,0x09,0x03,0x05,0x02,0x06,0x02,0x02,0xe5,0x01,0x09,0x09,0x09,0x05,0xe5,
+ 0x01,0x08,0x02,0x09,0x02,0x06,0x0d,0x05,0x0d,0x05,0x02,0x04,0x04,0xe5,0x04,0x09,
+ 0x02,0x1a,0x09,0x0f,0xe8,0x2b,0x11,0x1d,0x1d,0x18,0x04,0xe5,0x09,0x13,0x01,0x1a,
+ 0xe5,0x09,0xe5,0xe5,0x04,0x1f,0x25,0xe6,0x0f,0x03,0x05,0x09,0x09,0x09,0x09,0x01,
+ 0x07,0x09,0x09,0x09,0xe5,0x07,0x05,0x03,0x09,0x01,0x07,0x06,0xe5,0x02,0x09,0x09,
+ 0x01,0x03,0x03,0x05,0x03,0x09,0xe5,0x07,0x09,0x09,0x01,0x07,0x09,0x07,0x01,0x09,
+ 0x09,0x0d,0x01,0x01,0x04,0x27,0x39,0x25,0x09,0x0b,0x09,0x09,0x02,0xe5,0x0e,0x02,
+ 0x07,0x0b,0x1d,0x2e,0xe5,0xe6,0x50,0xe5,0x1b,0x13,0x04,0x04,0x04,0x06,0x04,0x09,
+ 0x04,0x04,0x13,0x0e,0x13,0x1d,0x27,0xe7,0x21,0xc6,0x40,0x03,0x03,0x07,0xe3,0x09,
+ 0x3a,0x03,0x07,0x29,0x1f,0x25,0x0b,0x3b,0x15,0xe5,0x2d,0x01,0x27,0xe7,0x6e,0x16,
+ 0x05,0xe5,0x01,0x05,0x02,0x02,0x05,0x03,0x05,0xe5,0x01,0x05,0x0d,0x05,0x5c,0x06,
+ 0x01,0x01,0x05,0x93,0x59,0x34,0x05,0xe5,0x01,0x04,0xe5,0xe3,0x34,0x10,0x02,0xe5,
+ 0x13,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,0x09,0x09,0x03,0x05,0x0a,0xe5,
+ 0xe5,0x04,0x09,0x08,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x08,0x09,0x07,0x03,0x09,0x09,0x09,0x09,0x09,
+ 0x04,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x08,0x08,0xe5,0x08,0x07,0xe6,
+ 0x11,0x16,0x09,0x09,0x0f,0x03,0x09,0x09,0x05,0x03,0x09,0x05,0x03,0x13,0x04,0x09,
+ 0x05,0x05,0x09,0x09,0x13,0x14,0x03,0x09,0x09,0x05,0x03,0x2f,0xe5,0x01,0x0d,0x03,
+ 0x03,0x05,0x03,0x05,0x03,0x01,0x0d,0x03,0x05,0x03,0x09,0x05,0x03,0x09,0x09,0x01,
+ 0x11,0x01,0x04,0x04,0x04,0x06,0x04,0x04,0x04,0x04,0x04,0x04,0x09,0x04,0x06,0x0b,
+ 0x03,0x05,0x03,0x09,0x09,0x01,0x0d,0x03,0x03,0x05,0x03,0x0e,0xe8,0x0a,0x06,0x01,
+ 0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0xe5,0x02,0x07,0xe5,0xe5,0x03,0x02,0x01,
+ 0x01,0xe5,0xe5,0x01,0x01,0x01,0xe5,0xe5,0x01,0x01,0x04,0x02,0x01,0x01,0xe5,0xe5,
+ 0x01,0x01,0x01,0x02,0x03,0x07,0xe5,0xe5,0xe6,0xe5,0x04,0x02,0x02,0x03,0x02,0x02,
+ 0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x07,0x03,0x02,0x02,0x02,0x04,
+ 0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0x05,0x04,0x03,0x07,0xe5,
+ 0xe5,0x03,0x04,0x04,0x0b,0x02,0xe5,0x01,0xe5,0x01,0xe5,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
diff --git a/u-boot/board/esd/ar405/fpgadata_xl30.c b/u-boot/board/esd/ar405/fpgadata_xl30.c
new file mode 100644
index 0000000..57d327a
--- /dev/null
+++ b/u-boot/board/esd/ar405/fpgadata_xl30.c
@@ -0,0 +1,2436 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x70,0x70,0x63,0x5f,0x61,0x72,0x30,0x31,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x33,0x30,0x78,0x6c,0x70,0x71,0x32,0x34,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x34,0x2f,0x31,0x32,0x2f,0x31,0x34,0x00,0x64,0x00,0x09,0x31,0x37,0x3a,0x30,
+ 0x33,0x3a,0x32,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x97,0xf2,0xff,0x30,0xe6,0x03,
+ 0xe5,0x01,0x01,0x01,0xe5,0xe6,0x04,0x01,0x02,0x11,0x09,0x09,0x02,0x04,0x04,0x06,
+ 0x09,0x07,0x09,0x04,0x04,0x04,0x04,0x09,0x09,0x0b,0x09,0x09,0x04,0x04,0x04,0x04,
+ 0x04,0x09,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x03,0x07,0x08,0x01,0xe5,
+ 0x0c,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x13,0x03,0x02,0x02,0x03,0x02,0x08,
+ 0x09,0x11,0x03,0x11,0x02,0x06,0x03,0x05,0x03,0x21,0x33,0x11,0xe5,0xe5,0xe3,0x17,
+ 0x0b,0xe5,0x01,0x0f,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x04,0x04,0x02,
+ 0x06,0x01,0xe5,0x05,0x01,0x02,0x02,0xe6,0x03,0x04,0x09,0x09,0x07,0xe6,0x03,0x06,
+ 0x01,0x07,0x09,0x04,0x04,0x09,0x09,0x06,0x02,0x04,0x04,0x04,0x04,0x09,0x09,0x09,
+ 0x12,0x14,0x09,0x09,0x03,0x05,0x03,0x05,0x09,0x09,0x03,0x05,0x09,0xe5,0x01,0x05,
+ 0xe5,0x07,0xe5,0xe6,0x04,0x0b,0xe5,0x07,0xe5,0x07,0x03,0x05,0xe5,0x01,0x05,0xe5,
+ 0x01,0x05,0xe6,0xe5,0x04,0x03,0x05,0x03,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,
+ 0x07,0x09,0x03,0x0e,0x05,0x03,0x05,0x03,0x05,0x13,0x03,0x05,0x03,0x08,0x31,0xe5,
+ 0xe5,0x37,0x44,0x01,0x01,0x01,0x79,0x8a,0xe5,0x01,0x10,0x09,0x09,0x1d,0x09,0x38,
+ 0x04,0x36,0x45,0xe7,0xe5,0x11,0x09,0x09,0x13,0x09,0x3e,0x09,0x3b,0x1d,0x18,0x05,
+ 0x01,0x01,0x06,0x73,0x12,0x77,0xe5,0xe5,0xe5,0xa2,0xe5,0x41,0x1c,0xe8,0x84,0x1f,
+ 0x25,0x3a,0xe5,0xe6,0x3c,0x70,0x4e,0x0c,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x03,0x07,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0xe5,0x07,0x09,
+ 0x09,0x09,0x01,0x07,0x0d,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x05,0x03,0x05,0x03,0x05,0x03,0x07,0x03,0x09,0x05,0x03,0x05,0x03,0x09,0x09,0x09,
+ 0x05,0x03,0x09,0x01,0x07,0x09,0x09,0x08,0x06,0x01,0x0d,0xe5,0x05,0x01,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x04,0x01,0xe6,0x07,0xe5,0x03,0x02,0xe6,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,
+ 0xe5,0x07,0xe5,0x01,0x0c,0xe8,0x0f,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x01,0x07,0x09,0xe5,0x07,0xe5,0x01,0x02,0xe5,0x02,0x09,0x09,0x09,0x09,0x01,0x01,
+ 0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x0a,0x05,0xe5,0x05,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x02,0x06,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x04,0x02,
+ 0xe5,0x02,0x01,0x02,0xe5,0x01,0x05,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x03,
+ 0x03,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0x02,0x03,0x03,0x0f,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x08,0x07,0x01,0x0d,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x09,0x09,
+ 0x09,0x09,0x09,0x05,0x03,0x09,0x01,0x03,0x05,0x09,0x09,0x08,0xe5,0x06,0x01,0x09,
+ 0x08,0xe5,0x08,0x09,0x09,0x09,0x0a,0x07,0xe6,0x01,0x03,0x06,0x02,0xe5,0x04,0x02,
+ 0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x04,0x01,0x02,0x05,0xe5,0x01,0x08,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x04,0x01,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x06,0x02,0xe5,0x02,0x37,0xe5,0x04,0x09,0x31,0x05,0x05,0x13,0x09,0x04,0x24,0x07,
+ 0x09,0x17,0x02,0x02,0x01,0x01,0x03,0x42,0x01,0x13,0x13,0x10,0x0c,0x01,0x09,0x07,
+ 0x01,0x06,0x05,0x24,0x06,0x0a,0x0f,0x0f,0x01,0xe6,0xe5,0x1d,0x1b,0x21,0x09,0x09,
+ 0x13,0x01,0x13,0x1d,0x05,0x17,0x2b,0x05,0xe6,0x33,0x04,0x05,0xe5,0x05,0x03,0x06,
+ 0x2c,0x0b,0x04,0x1d,0x59,0xe6,0x0f,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x01,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x0d,0xe5,0x01,0x2b,0x02,0x1a,0x13,0x02,0x09,0x06,0x0c,0x08,0xe5,0xe5,0x05,
+ 0x02,0xe5,0x07,0x06,0x01,0xe5,0x09,0x0f,0x01,0xe5,0x0f,0x09,0x03,0x03,0x01,0x1b,
+ 0xe5,0xe5,0x2a,0x12,0x2f,0xe5,0x08,0x09,0x0b,0x16,0x06,0x16,0x12,0x06,0x03,0x08,
+ 0x1c,0x01,0x2b,0x1e,0x03,0x0e,0xe5,0x07,0x0a,0x03,0x04,0x0c,0x04,0x03,0xe5,0x07,
+ 0x6a,0xe5,0x01,0x59,0x06,0x03,0x1c,0x0b,0x0b,0x18,0x0d,0x13,0x2b,0x06,0xe7,0x14,
+ 0x0a,0x09,0x2c,0x15,0x64,0x34,0x01,0xe5,0x13,0x16,0x09,0x01,0x17,0x0b,0x01,0x09,
+ 0x01,0x01,0x2a,0x0e,0x01,0x04,0x02,0x01,0x09,0x07,0x01,0x02,0x04,0x01,0x07,0xe6,
+ 0x01,0xe5,0x02,0xe7,0x05,0x01,0x13,0x05,0xe7,0x2d,0x06,0x02,0x0a,0x0c,0x0f,0x06,
+ 0x01,0x0d,0x0e,0x1e,0x01,0x07,0x02,0x07,0x09,0xe5,0x08,0x08,0x08,0x0a,0x01,0x19,
+ 0x01,0x54,0xe5,0x26,0x03,0x01,0x12,0x10,0x02,0x13,0x0e,0x06,0x08,0x23,0x04,0x01,
+ 0x01,0x10,0x13,0xe5,0x02,0x04,0x09,0x09,0x09,0x02,0x06,0x15,0x09,0x01,0x02,0x02,
+ 0x07,0x05,0x11,0x06,0x01,0x0a,0x13,0x0d,0x02,0x30,0xe6,0x01,0x0f,0x34,0x23,0x11,
+ 0xe5,0x28,0x30,0x0b,0x1b,0x07,0xe5,0x26,0x12,0x11,0xe5,0x26,0x25,0xe6,0xe5,0x0b,
+ 0x05,0x03,0x01,0x4d,0x02,0xe5,0x10,0x5a,0x14,0xe6,0x18,0x2d,0x10,0x13,0x17,0x01,
+ 0x33,0x33,0x01,0x04,0x02,0x01,0x09,0x08,0x02,0xe6,0xe6,0x03,0x04,0x02,0x01,0x04,
+ 0x04,0x07,0x01,0x0a,0x06,0x01,0x07,0x01,0x0a,0x08,0x15,0x0d,0xe7,0x19,0x04,0x13,
+ 0x21,0x01,0x11,0x09,0x07,0xe6,0x09,0x03,0x05,0xe5,0x01,0x10,0x06,0x02,0x0b,0x05,
+ 0x01,0x1d,0x06,0x1b,0x01,0xe6,0x24,0x2f,0x13,0x08,0x13,0x0c,0x14,0x07,0x30,0x01,
+ 0x02,0x21,0x01,0xe6,0x1f,0x1f,0xe5,0x25,0xe5,0x0e,0x0a,0x03,0x09,0x06,0x02,0xe5,
+ 0x11,0xe5,0x07,0xe5,0x04,0x06,0xe5,0x03,0x0b,0x27,0xe7,0xe6,0x01,0x01,0x2d,0x01,
+ 0x0e,0x20,0x01,0x01,0x12,0x0b,0xe5,0x02,0x0b,0x01,0xe5,0x0f,0xe5,0xe6,0x01,0xe5,
+ 0x03,0xe5,0x01,0x07,0x03,0xe5,0x0b,0x09,0x14,0xe5,0x08,0x01,0x04,0x01,0x04,0x40,
+ 0xe5,0x01,0x01,0x1d,0x01,0x0f,0x04,0x01,0xe5,0x09,0xe5,0xe5,0xe5,0x06,0x03,0xe5,
+ 0x0a,0xe5,0x0c,0x07,0x10,0x01,0xe5,0x05,0xe5,0x02,0x0e,0x01,0x02,0x09,0x05,0x01,
+ 0xe5,0x01,0x43,0x02,0x01,0x2f,0x06,0x0b,0x02,0x01,0x07,0x10,0x0c,0x0b,0x0e,0x02,
+ 0x06,0xe5,0x11,0x02,0x01,0x0b,0x02,0x02,0xe5,0x46,0x0d,0x13,0x19,0x02,0x02,0x05,
+ 0xe5,0x09,0x09,0x01,0x05,0x03,0x09,0x06,0xe5,0x10,0x06,0x03,0x09,0x08,0x03,0x02,
+ 0xe5,0x01,0x08,0xe5,0xe5,0x01,0x4a,0x05,0x03,0x01,0x02,0x0e,0x04,0x0e,0x07,0x03,
+ 0x03,0xe5,0x03,0x05,0x03,0x05,0x01,0x01,0x05,0x03,0x04,0xe5,0x02,0x03,0x03,0x01,
+ 0x01,0x02,0x0a,0x04,0x01,0xe7,0x04,0x01,0xe5,0x0b,0x02,0x01,0x01,0x04,0x03,0xe8,
+ 0x42,0x04,0x01,0x09,0x13,0x05,0x1e,0xe7,0xe5,0x03,0x01,0xe5,0x08,0x01,0x0f,0x03,
+ 0x07,0x0e,0x01,0x01,0x05,0x06,0x13,0x0d,0x03,0xe5,0x48,0x01,0x07,0x3a,0x02,0x01,
+ 0x04,0x02,0x09,0x01,0x11,0x0b,0x0d,0xe5,0x01,0x01,0x1b,0x01,0x0e,0xe8,0x08,0x02,
+ 0x6a,0xe5,0x07,0x0d,0x07,0xe6,0x10,0x02,0x06,0x09,0x1d,0x02,0x06,0x1e,0xe5,0xe6,
+ 0x09,0xe5,0x75,0xe6,0x12,0x09,0x09,0x0b,0x07,0x01,0x11,0x09,0x06,0x04,0x11,0x09,
+ 0x02,0xe6,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0x06,0x09,0x09,0x02,0x03,0x02,
+ 0x09,0x0b,0x09,0x03,0x02,0x02,0x03,0xe5,0xe5,0x01,0x05,0x03,0x06,0x02,0x03,0x05,
+ 0x02,0x01,0x01,0x02,0x03,0x02,0x02,0x05,0x03,0x04,0x01,0x02,0x06,0x02,0x03,0x09,
+ 0x02,0x01,0x02,0x6a,0x02,0x1f,0x08,0x0a,0x10,0x02,0x13,0x08,0xe5,0x1b,0xe5,0x0d,
+ 0x02,0x03,0x6e,0x1e,0x14,0x12,0x13,0x0b,0x1d,0x13,0x02,0x21,0x01,0x2e,0x02,0x11,
+ 0x13,0x0a,0x0a,0x01,0x07,0x01,0x07,0x01,0x06,0x02,0x09,0x07,0x08,0xe5,0xe5,0x06,
+ 0x01,0x06,0x0c,0x07,0x01,0x04,0x09,0xe8,0x20,0x01,0xe5,0x0c,0x22,0xe5,0x0f,0x02,
+ 0x09,0x06,0x02,0x08,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,
+ 0x05,0x03,0x05,0x02,0x03,0x02,0x01,0xe5,0x05,0x01,0x01,0x02,0x02,0x01,0xe6,0xe5,
+ 0x01,0xe5,0x01,0x06,0x01,0x01,0x05,0xe5,0x02,0x02,0xe5,0xe5,0x1f,0xe5,0xe5,0x30,
+ 0x11,0x29,0x01,0x07,0x01,0x06,0xe5,0xe5,0x0d,0x02,0x01,0x06,0xe5,0x08,0x01,0x04,
+ 0x02,0x01,0x13,0x09,0x03,0x0a,0x02,0xe5,0x14,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,
+ 0x06,0xe6,0xe6,0x04,0xe5,0xe6,0xe5,0x02,0xe5,0xe6,0xe5,0x02,0xe5,0xe6,0x04,0xe5,
+ 0xe5,0x05,0xe5,0xe6,0xe5,0x05,0xe5,0x04,0x02,0xe5,0xe5,0x04,0x01,0x01,0x05,0xe5,
+ 0x07,0xe6,0x06,0xe6,0x06,0xe7,0x02,0x02,0x01,0xe5,0x7a,0x06,0x07,0x03,0x02,0x01,
+ 0x03,0x03,0x01,0xe5,0x05,0x01,0xe5,0x02,0x04,0x04,0x04,0x07,0x09,0x01,0x05,0x01,
+ 0x01,0x09,0x07,0x0b,0x0e,0x01,0x01,0x7b,0x08,0x01,0xe5,0x04,0x02,0xe5,0xe5,0x05,
+ 0xe5,0xe6,0x02,0x01,0xe5,0xe5,0x02,0x02,0x02,0x03,0x02,0xe5,0x07,0xe5,0x08,0x01,
+ 0x06,0xe5,0xe5,0x08,0x09,0x07,0x10,0xe5,0xe6,0x70,0x12,0x05,0x04,0xe5,0x01,0x04,
+ 0xe6,0x01,0x03,0x01,0xe6,0xe6,0x03,0xe5,0x07,0xe5,0x01,0x05,0xe6,0x04,0x01,0x03,
+ 0x05,0x15,0x0b,0x0e,0x01,0xe6,0x37,0x4e,0x02,0x02,0xe5,0x01,0x01,0x04,0x02,0x01,
+ 0xe5,0x02,0x02,0x01,0xe5,0x01,0x06,0x02,0x03,0x04,0xe5,0x02,0x05,0x03,0x01,0xe5,
+ 0x05,0x04,0x09,0x06,0x07,0x04,0x0b,0xe6,0xe5,0x66,0x13,0x02,0x07,0x14,0xe5,0xe5,
+ 0x37,0xe5,0xe5,0x08,0x10,0x02,0x0d,0xe8,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x04,0x02,0x01,
+ 0x07,0x01,0x01,0x02,0x02,0x01,0xe5,0x07,0x01,0xe5,0xe5,0x03,0x01,0x04,0x02,0x01,
+ 0x07,0x01,0x01,0x05,0x01,0xe6,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,
+ 0xe6,0xe5,0x04,0x01,0x01,0x05,0x01,0x02,0x08,0xe5,0xe5,0x1f,0x20,0x0d,0x0b,0x1b,
+ 0x03,0x05,0x07,0xe5,0x01,0x13,0x05,0x0a,0x08,0xe6,0x0d,0x05,0x05,0x02,0x05,0x03,
+ 0x0f,0xe5,0x01,0x0d,0xe8,0x09,0x12,0x1f,0x1d,0x08,0x04,0x04,0x05,0x09,0x08,0x16,
+ 0x0f,0x25,0x2f,0xe5,0xe8,0x3e,0x0c,0x03,0xe5,0x34,0x0d,0x0f,0x05,0x06,0x03,0xe6,
+ 0xe5,0x0b,0x12,0x0d,0x1b,0xe5,0x02,0xe5,0x11,0xe5,0x0b,0x01,0x2f,0xe6,0x1a,0x0c,
+ 0x12,0x01,0x01,0x02,0x02,0x09,0x0d,0x07,0x01,0x02,0x09,0x02,0x01,0x04,0x08,0x05,
+ 0x07,0xe6,0x08,0x05,0x07,0x02,0x01,0x2f,0x01,0x34,0x0c,0x06,0x08,0x01,0xe5,0x0c,
+ 0x08,0x09,0x0c,0x14,0x05,0x0f,0x01,0x08,0x01,0x0d,0x09,0x01,0x03,0x2f,0x23,0x15,
+ 0x09,0x02,0x01,0x0c,0xe5,0x05,0x03,0xe6,0x0d,0x16,0x11,0x01,0x0a,0xe5,0x0b,0x0a,
+ 0x03,0x05,0x0a,0xe5,0xe6,0x0f,0x02,0x08,0x13,0x31,0x04,0x02,0x0d,0x05,0x05,0xe5,
+ 0x0d,0x06,0x02,0x13,0xe5,0x07,0x13,0x06,0x01,0x02,0x0d,0x08,0xe5,0x05,0x0b,0x02,
+ 0x0a,0xe5,0x2d,0x2c,0x02,0x09,0x18,0xe5,0x08,0x02,0x0d,0x22,0x08,0x30,0x01,0x01,
+ 0x1d,0x04,0x04,0x35,0x01,0x0b,0x08,0x03,0x08,0x02,0xe5,0x04,0xe6,0x01,0x04,0xe5,
+ 0x02,0xe7,0x01,0x03,0xe5,0x07,0xe7,0x03,0x01,0x09,0x44,0xe5,0xe5,0x21,0x48,0x19,
+ 0x17,0x07,0x0b,0x0e,0x41,0x03,0xe5,0x01,0x02,0x6b,0x05,0x0d,0x04,0x01,0x04,0x09,
+ 0x09,0x0e,0x0a,0x23,0x17,0x11,0x6c,0x01,0x04,0x1a,0x1d,0x04,0x1a,0x39,0xe6,0xe5,
+ 0x04,0x6d,0x12,0x25,0x02,0x01,0x0d,0x2a,0x1c,0x01,0xe7,0x07,0x01,0x05,0x01,0xe5,
+ 0x04,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0xe5,0x02,0xe5,0x44,0x10,0x02,0x18,0xe5,0x03,
+ 0xe5,0xe6,0x04,0xe5,0x01,0xe5,0x03,0xe5,0x0b,0x01,0x11,0xe5,0x05,0x01,0x01,0x04,
+ 0xe5,0x08,0x09,0x01,0xe6,0xe5,0x01,0x01,0x04,0xe5,0x11,0xe5,0x04,0x02,0xe5,0x4b,
+ 0x02,0x01,0xe5,0x03,0x06,0xe5,0x07,0x09,0x06,0xe5,0xe5,0x01,0x06,0xe5,0x07,0x09,
+ 0x05,0xe5,0x01,0x1a,0xe5,0x16,0x01,0x02,0x01,0xe6,0x03,0x16,0x13,0x15,0xe5,0x01,
+ 0x01,0x25,0x06,0x01,0x02,0x0b,0x1d,0x02,0x06,0x01,0x07,0x01,0x02,0xe5,0x02,0x04,
+ 0xe5,0x02,0x04,0x01,0x18,0x11,0x04,0xe6,0xe5,0x01,0x43,0xe5,0xe5,0xe5,0x21,0xe5,
+ 0xe5,0x13,0xe5,0x08,0x09,0x06,0xe5,0x0a,0x06,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x25,
+ 0x06,0x04,0xe6,0x11,0x09,0x09,0x3b,0x04,0x08,0xe5,0xe5,0x0c,0x02,0x04,0x09,0x03,
+ 0x02,0xe5,0x0e,0x02,0x02,0x05,0xe5,0x05,0x02,0x06,0x02,0x06,0x02,0xe5,0xe5,0x02,
+ 0x02,0x05,0x09,0x0c,0x07,0x02,0xe6,0x01,0x4a,0x1b,0x01,0x02,0xe7,0xe5,0x06,0x03,
+ 0x02,0x01,0x02,0x03,0x01,0x02,0x04,0x02,0x01,0x04,0x02,0x01,0xe5,0x02,0x02,0x01,
+ 0xe5,0x02,0x03,0xe6,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,
+ 0xe5,0xe5,0x01,0x01,0x1f,0x02,0x02,0x01,0xe7,0x12,0x09,0x06,0x0a,0x18,0x01,0x15,
+ 0x02,0x01,0xe5,0x08,0x0b,0x0b,0x09,0x07,0x0b,0x09,0x05,0x03,0x09,0x09,0x07,0x01,
+ 0x0e,0x01,0x04,0x02,0x01,0x10,0xe5,0x01,0xe5,0x10,0xe8,0x04,0xe5,0xe6,0x05,0x22,
+ 0x01,0x16,0x01,0x04,0x07,0x04,0x10,0x27,0x29,0x0b,0xe5,0xe5,0x06,0x01,0x15,0xe6,
+ 0x08,0x02,0x03,0x09,0x04,0x04,0x3b,0x04,0x07,0x02,0x10,0x02,0x08,0xe5,0x07,0x02,
+ 0x06,0x02,0x06,0x02,0x06,0xe5,0x07,0xe5,0x11,0xe5,0x0e,0x02,0x01,0x04,0x04,0x07,
+ 0x02,0x06,0xe5,0x02,0x0a,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x39,0xe5,0x0b,0x06,0x2c,
+ 0x09,0x13,0xe5,0x1b,0x05,0xe5,0x01,0xe6,0x02,0xe5,0x0b,0x09,0x01,0x01,0xe6,0x06,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe6,0x06,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x02,0xe5,
+ 0x01,0x02,0x09,0x04,0x01,0x04,0x09,0x09,0x02,0x02,0x03,0x04,0xe6,0x01,0x06,0x02,
+ 0x09,0x02,0x06,0x02,0x01,0x01,0x02,0x03,0x05,0xe5,0x07,0xe6,0x06,0x05,0x07,0x02,
+ 0x01,0x02,0x6c,0xe5,0x08,0x15,0x09,0x09,0x12,0x0a,0x09,0x27,0x0e,0x05,0xe5,0x10,
+ 0x09,0x53,0x08,0x14,0x09,0x09,0x1d,0x09,0x1b,0x0d,0x12,0xe8,0x0f,0x01,0x07,0xe6,
+ 0x06,0x01,0x39,0x01,0x10,0x02,0x03,0xe5,0x09,0x0a,0x08,0xe5,0x08,0x09,0x01,0x07,
+ 0x09,0x09,0x13,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x16,0x01,0x11,0x09,0x09,0x3b,
+ 0x08,0x06,0x03,0x01,0x05,0xe5,0x0a,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x09,0x05,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,
+ 0x01,0x09,0x02,0xe9,0x19,0x47,0x02,0x0c,0x09,0x15,0x09,0x04,0x04,0x06,0xe5,0xe5,
+ 0x1c,0x09,0x03,0x0d,0x01,0x09,0x03,0x0b,0xe5,0xe5,0x12,0xe7,0x05,0xe7,0x05,0xe7,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe6,0x06,
+ 0xe6,0x04,0xe7,0xe5,0x06,0xe7,0x04,0xe8,0x04,0xe8,0x05,0xe7,0xe5,0x02,0xe7,0x05,
+ 0x01,0xe5,0x05,0x01,0xe6,0x04,0xe8,0x06,0xe5,0x05,0xe5,0xe6,0xe5,0x02,0xe5,0xe5,
+ 0x01,0x05,0xe5,0x06,0x01,0x01,0x1a,0x45,0x06,0x01,0x09,0x0e,0x01,0x09,0x01,0x06,
+ 0x02,0x03,0x03,0x01,0x07,0x01,0xe5,0xe6,0x04,0x02,0x03,0x02,0x02,0x03,0x09,0xe5,
+ 0xe5,0x09,0x01,0x0a,0xe5,0x06,0x0c,0x02,0x02,0x13,0x02,0x06,0x02,0x06,0x02,0x35,
+ 0x02,0x03,0x01,0x09,0x02,0x0a,0x02,0x01,0x08,0xe5,0x07,0xe5,0x02,0x02,0x01,0xe5,
+ 0x07,0xe6,0xe6,0x02,0xe7,0x06,0xe6,0x06,0x09,0xe5,0x09,0x01,0x03,0x02,0x06,0x02,
+ 0x02,0x02,0x04,0xe5,0x03,0xe5,0xe5,0xe5,0x10,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x04,
+ 0x02,0xe5,0x36,0x03,0x0d,0x0f,0x03,0x07,0x08,0xe5,0x08,0x09,0x03,0x03,0x01,0x09,
+ 0x09,0x09,0x03,0x01,0x09,0x02,0xe6,0x03,0x02,0xe6,0x01,0x07,0x06,0xe6,0xe5,0x12,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x37,0x01,0x0d,0x0a,0x02,0x01,0x09,0x09,
+ 0xe5,0x04,0x02,0x06,0x02,0xe5,0x01,0x01,0xe5,0x02,0x08,0xe5,0x0e,0x02,0x03,0x0f,
+ 0x09,0x05,0x08,0x03,0x01,0xe5,0x01,0x6b,0x05,0x09,0x02,0x01,0x10,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0xe5,0x11,0x05,0xe5,0xe6,0x04,0xe5,0xe5,0x05,0x02,0x03,
+ 0xe5,0x26,0x02,0x11,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0x01,0x05,0x01,0x06,0xe5,
+ 0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0xe6,0x06,0x01,
+ 0xe5,0x02,0x04,0x01,0x03,0x03,0x01,0x02,0x01,0x02,0x01,0xe5,0x02,0x02,0x01,0x07,
+ 0x01,0xe5,0x05,0x01,0x03,0x03,0x01,0x03,0x03,0x01,0x04,0x02,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x0a,0x01,0x01,0x0b,0xe5,0x02,0x04,0x03,0xe5,0x07,0xe5,0x29,0x0f,
+ 0xe5,0x03,0x0c,0x02,0x05,0xe5,0x36,0x03,0x06,0x17,0x04,0x06,0x01,0x07,0x14,0x03,
+ 0xe5,0x01,0xe5,0x03,0x08,0x13,0x0f,0x09,0x0a,0x16,0x07,0x09,0x08,0x0a,0x0b,0x04,
+ 0xe6,0xe5,0x08,0x09,0x19,0xe5,0x01,0x0a,0x0c,0x05,0x05,0x04,0x03,0x0a,0x01,0x01,
+ 0x02,0x13,0x02,0xe5,0xe5,0x07,0x3b,0x19,0x01,0x09,0x05,0x0d,0x05,0x02,0x07,0x01,
+ 0xe5,0x06,0x12,0x09,0x1a,0x04,0x0a,0x09,0xe9,0x18,0x45,0x06,0x01,0xe5,0x05,0x02,
+ 0x06,0x04,0xe5,0x03,0xe6,0x04,0x01,0x02,0x07,0x06,0x02,0x0b,0x04,0x04,0xe5,0x02,
+ 0x02,0x01,0x04,0x02,0x06,0x07,0x02,0x0b,0x01,0x07,0x01,0x0c,0x02,0xe5,0xe5,0x0a,
+ 0x1c,0x3a,0x01,0x02,0x01,0x09,0x04,0x04,0x02,0x01,0x01,0x07,0x03,0x0c,0x05,0x03,
+ 0x06,0x15,0x0a,0x1c,0x01,0x07,0x0e,0xe6,0xe6,0x21,0x0d,0x3c,0xe5,0x02,0x03,0x0d,
+ 0x03,0x09,0x02,0x05,0xe5,0xe5,0x02,0x07,0x09,0x03,0x05,0x01,0x01,0x01,0x02,0x02,
+ 0x06,0x0a,0x05,0x07,0x09,0x04,0x0c,0xe7,0x11,0x02,0x05,0xe5,0x1d,0x0d,0x04,0x09,
+ 0x09,0x09,0x07,0x10,0x01,0x04,0x05,0x08,0x10,0x16,0xe6,0x0a,0x08,0x06,0xe5,0x07,
+ 0x05,0x03,0x11,0xe7,0x23,0x26,0x18,0x09,0x05,0x03,0x0d,0x0f,0x06,0x02,0x02,0x1c,
+ 0x11,0xe5,0x0e,0x04,0x04,0x04,0x02,0x10,0xe5,0xe6,0x09,0x05,0x09,0x09,0x02,0x53,
+ 0x01,0x07,0x01,0xe5,0x01,0x03,0x01,0xe6,0x03,0x10,0x08,0x06,0xe5,0x0d,0x0e,0x0b,
+ 0x05,0x03,0x09,0x0d,0xe5,0x01,0x46,0x39,0x04,0x04,0x08,0x22,0x02,0x01,0x01,0x1b,
+ 0x0b,0x21,0xe5,0xe5,0x08,0x05,0x01,0x07,0x01,0x09,0x0d,0x3a,0x05,0x03,0x01,0x0c,
+ 0xe6,0x08,0x09,0x04,0x01,0x09,0x31,0xe5,0xe6,0x09,0x03,0x04,0x05,0x07,0x02,0xe5,
+ 0x0f,0xe5,0x0d,0x02,0x27,0x2d,0x08,0x0a,0x03,0x01,0x01,0x03,0x03,0x03,0x08,0x12,
+ 0x04,0x19,0x06,0x09,0x06,0x10,0xe6,0xe6,0x0b,0xe5,0x08,0x03,0x06,0x02,0x02,0x21,
+ 0x16,0x0b,0x14,0x0b,0x02,0x05,0x02,0xe6,0x33,0x11,0x04,0x03,0x02,0x02,0x13,0x01,
+ 0x01,0x01,0x01,0x5d,0xe5,0x06,0x10,0x02,0xe5,0x05,0x01,0x0b,0x09,0x09,0xe5,0x11,
+ 0xe5,0x04,0x02,0xe5,0x12,0x02,0xe5,0x03,0xe5,0x1d,0xe5,0x01,0x01,0x02,0x03,0x1f,
+ 0x33,0x01,0x04,0x05,0xe5,0x02,0x10,0xe5,0x11,0x04,0x04,0x04,0x01,0x01,0x01,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x05,0xe6,0xe5,0x05,0xe5,0x0a,0x23,0x01,0x01,0x02,0xe5,0xe6,
+ 0x03,0x01,0x02,0xe5,0x01,0x06,0x01,0x02,0x04,0x01,0xe5,0x23,0x01,0x05,0x1a,0x07,
+ 0x09,0x04,0x05,0x05,0x0b,0x01,0xe5,0xe5,0x08,0x01,0x07,0x09,0x07,0x01,0x09,0x15,
+ 0x02,0xe5,0x02,0x04,0xe5,0x0a,0x01,0x05,0x02,0xe5,0xe5,0x05,0xe5,0x01,0x09,0x2e,
+ 0x20,0x06,0x02,0x0b,0x13,0x06,0x02,0x01,0x09,0x09,0x09,0x07,0x01,0x09,0x0d,0xe5,
+ 0x11,0xe5,0x0f,0x02,0x01,0xe7,0xe5,0x0c,0x02,0x02,0x03,0x03,0x01,0x03,0x05,0x1c,
+ 0x1a,0x06,0x05,0xe6,0xe5,0x06,0x08,0x02,0x01,0x07,0x06,0xe6,0x05,0x02,0x02,0x09,
+ 0x09,0x13,0x0c,0x06,0xe5,0x02,0x01,0x03,0x02,0x02,0x11,0xe9,0x03,0x0a,0x05,0xe5,
+ 0x01,0x06,0x02,0x03,0xe6,0x21,0x19,0x03,0x03,0x01,0x01,0x09,0x01,0x03,0x03,0x01,
+ 0x01,0x09,0x04,0x04,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x09,0x07,0x01,0x12,0x05,
+ 0x03,0x05,0x0b,0x02,0x02,0xe5,0xe6,0x0e,0x05,0x0b,0x27,0x17,0x07,0x07,0x05,0xe5,
+ 0x01,0x0b,0x01,0x07,0x06,0xe5,0xe5,0xe5,0x03,0xe5,0x02,0x04,0x04,0x04,0x01,0x02,
+ 0x04,0x0e,0x0c,0x04,0x01,0x05,0x01,0x01,0x05,0x03,0x08,0x04,0xe6,0x01,0xe5,0x0b,
+ 0x02,0x06,0x02,0x06,0x02,0x24,0x18,0xe6,0x01,0x05,0xe5,0x01,0x04,0x06,0x09,0x01,
+ 0x0e,0xe7,0xe5,0x03,0xe6,0x01,0x05,0x03,0x04,0x04,0x05,0x0d,0x0b,0xe5,0xe5,0x01,
+ 0x02,0x03,0x01,0xe5,0x01,0x1a,0xe5,0x08,0x02,0x03,0x02,0xe5,0x04,0x09,0x02,0x1d,
+ 0x1a,0x2c,0x27,0xe6,0x10,0x02,0x06,0x02,0x03,0x04,0x04,0x02,0xe5,0x04,0x0c,0x02,
+ 0x07,0xe5,0x01,0x14,0x13,0x01,0x1b,0xe6,0x16,0xe5,0x12,0x18,0x01,0x11,0x27,0x0f,
+ 0xe5,0x1c,0x02,0x06,0x02,0xe6,0xe6,0x0a,0x02,0xe5,0x01,0x02,0x02,0xe5,0xe5,0x02,
+ 0x02,0xe5,0x01,0x05,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x06,0x02,0x09,0x06,0x04,
+ 0x03,0x02,0x02,0x09,0x03,0x05,0x09,0x02,0x06,0x09,0x03,0x05,0x09,0xe5,0x04,0x02,
+ 0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x05,0x05,0x07,0x03,0xe5,0x01,0x06,0x02,0x06,0x09,
+ 0x2a,0x24,0x02,0x12,0xe5,0x07,0x02,0x4c,0x0b,0xe5,0x08,0x0e,0x02,0x03,0x0b,0x39,
+ 0x28,0x14,0x0b,0x4b,0x0b,0x09,0x16,0xe6,0x0c,0x02,0x09,0x09,0x19,0xe5,0xe5,0x06,
+ 0x01,0x14,0xe6,0x0a,0x04,0x02,0x03,0x0b,0xe5,0xe5,0x2d,0x1e,0x01,0xe7,0xe5,0x04,
+ 0x09,0x15,0x01,0x02,0xe5,0x0e,0x2f,0x01,0xe5,0x05,0x03,0x13,0x0f,0x03,0x01,0x02,
+ 0x03,0x05,0x02,0x01,0xe5,0x05,0x02,0x0a,0x04,0x03,0x05,0x03,0x09,0x05,0x03,0x09,
+ 0x06,0x01,0xe6,0x04,0x0b,0x07,0x01,0x01,0x01,0x0d,0xe5,0x0c,0x09,0x01,0x2c,0x02,
+ 0x01,0x0e,0x18,0x0d,0x05,0x01,0x06,0x07,0x12,0x03,0x01,0x11,0x01,0x07,0x01,0x07,
+ 0x01,0xe5,0x1b,0x0e,0x01,0x01,0x15,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe6,0x06,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x06,0xe6,0xe6,
+ 0xe5,0x03,0x01,0xe5,0x04,0xe5,0xe5,0x06,0xe6,0x05,0xe8,0xe5,0x02,0xe7,0x05,0xe8,
+ 0xe5,0x02,0x01,0xe6,0xe5,0x02,0xe8,0xe5,0x02,0x01,0xe6,0x06,0xe5,0x01,0x05,0xe5,
+ 0x01,0x04,0xe6,0x07,0x02,0x23,0x1b,0x01,0x1e,0xe5,0x07,0x10,0x01,0x04,0x04,0x01,
+ 0xe5,0x07,0xe5,0x0f,0x01,0xe6,0xe5,0x05,0xe5,0xe5,0x02,0x01,0xe6,0xe5,0x08,0x09,
+ 0xe5,0x04,0xe5,0x04,0x02,0xe5,0x04,0x12,0x07,0x02,0xe5,0x0e,0x13,0x1b,0x01,0x34,
+ 0x04,0x01,0x06,0x01,0xe5,0xe6,0x02,0x01,0x03,0x02,0x02,0x05,0x03,0xe5,0xe5,0x03,
+ 0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0x13,0x06,0x01,0x01,0x0b,0x07,0x01,0x02,0x01,
+ 0x02,0xe5,0x03,0xe9,0x08,0x0f,0x09,0x46,0x10,0x01,0x06,0x04,0x05,0xe5,0x01,0x04,
+ 0xe6,0x01,0x04,0xe5,0xe5,0xe5,0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,
+ 0x01,0x01,0x05,0x21,0x07,0x06,0x03,0x21,0x2c,0x13,0x07,0x10,0x01,0x09,0x01,0xe5,
+ 0x01,0xe5,0x04,0x02,0x05,0x03,0x01,0xe6,0xe6,0x01,0xe8,0xe6,0x02,0xe7,0xe6,0x01,
+ 0xe8,0xe5,0x04,0x01,0x01,0x03,0x01,0xe5,0x04,0xe5,0x05,0x12,0x04,0x03,0x03,0x05,
+ 0x0d,0x01,0xe5,0x05,0x01,0xe5,0x05,0x02,0x24,0x04,0x22,0x14,0x0c,0xe5,0x05,0xe5,
+ 0xe5,0x05,0x0c,0x06,0x01,0xe5,0x0f,0x07,0x0b,0x09,0x16,0x03,0x01,0x01,0x0e,0x02,
+ 0x01,0x02,0x01,0x02,0x01,0x03,0x03,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,
+ 0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x03,0x03,0x01,0x01,0x05,0x01,
+ 0xe5,0x06,0xe5,0xe5,0xe5,0x04,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x04,0x02,
+ 0x01,0xe5,0x05,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0xe6,0x04,
+ 0x01,0xe6,0x04,0x01,0x0a,0x03,0x13,0x0c,0xe5,0x27,0x02,0x11,0xe5,0x08,0x2b,0x0a,
+ 0xe5,0x02,0x04,0x02,0xe5,0x04,0x09,0x05,0x04,0xe5,0x0c,0xe6,0x05,0x09,0x04,0x14,
+ 0x02,0xe6,0x09,0x09,0x30,0x15,0x01,0x09,0x06,0x0a,0x08,0x07,0x04,0x09,0x06,0x02,
+ 0x06,0x09,0x02,0x06,0x02,0x06,0x02,0x0b,0xe5,0xe5,0x1f,0x08,0xe5,0x02,0x02,0x19,
+ 0x42,0x0b,0x02,0x09,0x07,0x09,0x02,0x08,0x09,0x09,0x09,0x0f,0x0f,0x11,0x20,0x01,
+ 0xe6,0x15,0x01,0x07,0xe5,0x04,0x06,0x19,0x01,0x0b,0x1d,0x05,0x01,0x04,0x04,0x01,
+ 0x07,0x0b,0xe5,0x05,0xe5,0xe5,0x08,0x06,0x01,0xe5,0x02,0x05,0x10,0xe6,0x06,0x01,
+ 0x07,0x01,0x04,0x15,0xe6,0x0b,0x0a,0x02,0x18,0x18,0x18,0x0a,0x07,0xe5,0xe5,0x01,
+ 0x01,0x02,0x01,0x05,0x01,0x01,0x03,0x07,0x10,0x08,0x04,0x01,0x0e,0x0b,0x06,0x05,
+ 0x09,0x04,0x08,0x0a,0x01,0xe6,0x2b,0x03,0x05,0x11,0x06,0x18,0xe5,0x07,0x0d,0x03,
+ 0x11,0x06,0x0c,0x0a,0x08,0x09,0x09,0x0d,0x09,0x0b,0x02,0x0b,0x03,0x2b,0x01,0x2a,
+ 0x0d,0xe5,0xe5,0x09,0x09,0x06,0x0e,0x0d,0x11,0x07,0x13,0x0c,0x06,0x05,0x1c,0x02,
+ 0x0b,0x22,0x09,0x14,0x1c,0x02,0xe5,0x04,0x02,0x0a,0x01,0xe5,0x19,0x13,0x27,0x03,
+ 0x05,0x11,0x05,0x07,0x03,0x09,0x01,0x11,0x3d,0x1c,0x0d,0x03,0x02,0x02,0xe6,0x04,
+ 0x02,0xe6,0x06,0xe5,0x02,0x01,0x0c,0xe5,0x02,0x02,0x01,0xe5,0x03,0x03,0xe5,0xe6,
+ 0x1e,0x01,0x12,0x03,0x02,0xe5,0x18,0x44,0x17,0x08,0x01,0xe5,0x09,0xe5,0x02,0x06,
+ 0x07,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x1d,0x0f,0x03,0xe6,0xe5,0x11,0x0d,
+ 0x0c,0x0a,0x12,0x28,0xe5,0x06,0x03,0xe5,0x08,0xe5,0x08,0x05,0x15,0x02,0x22,0xe5,
+ 0x02,0x09,0x0f,0x0d,0xe6,0xe5,0x27,0x02,0x01,0x2c,0x0c,0x01,0x02,0x01,0x0a,0x01,
+ 0xe6,0x01,0x0a,0x11,0x02,0xe5,0x0a,0x03,0x01,0xe5,0x23,0x22,0x08,0x03,0xe5,0x04,
+ 0x25,0x1d,0x0f,0x07,0x09,0x1a,0x14,0x01,0x01,0x11,0x25,0xe5,0x04,0x27,0x02,0xe7,
+ 0x0e,0xe5,0x07,0x09,0x1c,0x01,0x15,0x01,0xe5,0x02,0xe5,0x06,0x1b,0x04,0xe7,0x05,
+ 0x01,0xe5,0x05,0x05,0x03,0x02,0x01,0x0e,0x09,0x02,0x01,0x04,0x08,0xe5,0x01,0xe5,
+ 0x04,0xe5,0x07,0x05,0x0e,0xe7,0x01,0x02,0x01,0x05,0x01,0x04,0x02,0x01,0x04,0x02,
+ 0x01,0x04,0x23,0x09,0xe5,0x03,0xe5,0x01,0x03,0x05,0x0f,0xe5,0x07,0xe5,0x03,0xe5,
+ 0x01,0x15,0xe5,0x01,0x02,0x03,0xe5,0xe5,0x0b,0x09,0x02,0xe5,0x04,0x0a,0x01,0xe5,
+ 0x01,0xe5,0x01,0xe5,0xe5,0xe5,0x03,0x05,0x0b,0x01,0x03,0x02,0x04,0x26,0x29,0x07,
+ 0x06,0x01,0x07,0xe5,0xe5,0x08,0x01,0x0b,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x0c,
+ 0x20,0xe5,0x03,0x09,0x11,0x0b,0x05,0x02,0x02,0x24,0xe5,0x01,0x1d,0x09,0x09,0x09,
+ 0x06,0xe5,0x06,0xe5,0x01,0x01,0x08,0xe5,0x04,0xe5,0x01,0x01,0x04,0xe5,0xe5,0xe5,
+ 0x06,0x09,0xe5,0xe5,0x23,0x09,0x13,0x0d,0x04,0x01,0x12,0x09,0x09,0x07,0x02,0x02,
+ 0xe5,0x17,0xe5,0x01,0x02,0x06,0xe5,0x03,0x07,0x03,0x01,0xe5,0xe5,0x01,0x01,0x01,
+ 0x05,0x08,0x02,0x09,0x09,0x04,0x04,0x07,0x0b,0x09,0x09,0x07,0x08,0x02,0x03,0x05,
+ 0x06,0x02,0x0b,0xe5,0xe6,0x01,0x28,0x02,0x08,0x04,0x01,0x0a,0x04,0x01,0x01,0xe5,
+ 0x02,0x03,0xe6,0x02,0x08,0x08,0x01,0xe5,0x02,0x04,0x07,0x03,0x09,0x09,0x05,0x03,
+ 0x05,0x02,0xe5,0xe5,0x01,0x21,0x05,0xe5,0x02,0x03,0xe5,0x0b,0x02,0x08,0x02,0x01,
+ 0xe7,0x11,0xe5,0x06,0x08,0x0f,0x10,0x01,0x0c,0x05,0x01,0x03,0x02,0x01,0x02,0x04,
+ 0x04,0x05,0x01,0x01,0x0b,0x04,0x01,0xe5,0xe5,0x06,0x01,0x02,0x04,0x18,0x0b,0x01,
+ 0x07,0x01,0xe5,0x06,0x03,0x05,0x05,0x07,0x0d,0xe5,0x01,0xe5,0x10,0xe5,0xe5,0x05,
+ 0xe5,0x08,0xe6,0x01,0x02,0x08,0x0d,0xe5,0x01,0x09,0x09,0x04,0x01,0x01,0xe5,0x01,
+ 0x03,0xe6,0x01,0x07,0x01,0x01,0xe5,0xe5,0x03,0x03,0xe5,0xe5,0xe6,0xe5,0xe6,0x03,
+ 0x01,0x01,0xe5,0x03,0x03,0xe5,0x03,0x02,0x0a,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x01,0x02,0x06,0x03,0xe5,0xe5,0x06,0xe6,0x03,0x0b,0x02,0xe6,0xe5,0x04,0x0a,0x04,
+ 0x04,0x09,0x09,0x02,0x09,0x02,0x10,0xe5,0x0e,0x09,0x02,0x10,0x04,0x06,0x02,0xe5,
+ 0x04,0x09,0x09,0x09,0x02,0x06,0x09,0x04,0x04,0x02,0x01,0x04,0x02,0x06,0x04,0x04,
+ 0x14,0x02,0xe6,0xe5,0x0f,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0xe6,0x03,0x02,0x13,0xe5,
+ 0x0d,0xe5,0x0b,0x01,0x07,0xe5,0x03,0xe5,0x09,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x08,0x02,0x01,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x07,0x01,0x03,0xe5,0x07,
+ 0xe5,0x12,0x03,0xe5,0xe6,0x0d,0xe5,0x07,0xe5,0x07,0xe6,0x01,0x01,0x02,0xe5,0x07,
+ 0x03,0x05,0x09,0x09,0x09,0xe7,0xe5,0xe5,0x01,0xe5,0x01,0x05,0x09,0xe5,0x09,0xe5,
+ 0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x01,0x02,0x01,0x01,0x05,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x04,0x02,0xe5,0xe6,0x04,0xe5,0x07,0xe6,0x06,0x0d,0x03,0xe5,0x01,0x27,
+ 0x3b,0x47,0x24,0x2f,0x02,0xe8,0x10,0x09,0x0b,0x3d,0x19,0x0b,0x09,0x09,0x09,0x03,
+ 0x0f,0x09,0x09,0x13,0x21,0xe7,0x0f,0xe6,0x06,0xe6,0x06,0xe6,0x06,0x03,0x13,0x04,
+ 0x14,0xe6,0x06,0x0d,0x04,0xe5,0xe5,0x04,0xe5,0xe8,0x03,0x01,0xe7,0xe5,0x03,0xe5,
+ 0xe5,0xe5,0x04,0xe6,0x03,0x01,0xe5,0x08,0xe6,0x06,0xe6,0xe5,0x01,0x01,0xe7,0x06,
+ 0x09,0xe6,0x06,0xe6,0xe5,0x12,0x02,0xe5,0x09,0x06,0x09,0x09,0x13,0x01,0x0a,0x04,
+ 0x01,0x13,0x0c,0x05,0xe5,0x06,0xe6,0x06,0x01,0xe6,0x03,0xe5,0xe7,0x03,0x02,0xe6,
+ 0x08,0x05,0x01,0x01,0x09,0x09,0x05,0x01,0xe6,0x06,0x0b,0x09,0x09,0x05,0xe5,0x02,
+ 0x01,0xe9,0x0f,0x09,0x0b,0x0d,0x01,0x13,0x21,0x03,0x06,0x04,0x03,0x09,0x05,0x01,
+ 0xe5,0x01,0x05,0x0d,0xe5,0x01,0x01,0x0d,0x07,0x01,0x09,0x03,0x19,0xe5,0x0a,0x0a,
+ 0xe5,0x12,0xe7,0x05,0xe7,0x02,0x02,0xe7,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x02,0x02,0x01,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x03,0xe6,0x01,
+ 0x06,0xe6,0xe5,0xe5,0x02,0xe6,0x02,0x03,0xe6,0x03,0x02,0xe6,0xe5,0xe5,0x02,0x01,
+ 0xe5,0x02,0x02,0xe7,0x05,0x01,0xe5,0x02,0x02,0xe7,0x01,0x05,0xe5,0x02,0x02,0xe7,
+ 0x02,0x02,0xe7,0x07,0xe7,0x02,0x05,0x24,0xe5,0x06,0x1d,0x14,0xe5,0x06,0xe5,0x07,
+ 0x09,0x03,0x05,0x01,0x05,0x04,0x03,0xe5,0x02,0xe5,0x01,0x01,0x04,0x02,0x01,0x01,
+ 0x01,0x06,0x03,0x05,0x03,0x06,0x01,0xe6,0x03,0x0d,0xe5,0x07,0xe5,0x04,0x01,0x0e,
+ 0x03,0x13,0x02,0x06,0x02,0x06,0x02,0xe5,0xe5,0x1c,0x17,0x05,0x07,0x04,0x06,0x06,
+ 0x01,0xe5,0xe5,0x03,0x01,0x06,0x02,0x02,0xe5,0x04,0x07,0x01,0xe5,0xe5,0x04,0xe5,
+ 0x05,0x01,0xe5,0x07,0x01,0x01,0x03,0x01,0xe5,0x01,0x0d,0x02,0x06,0x02,0xe5,0xe5,
+ 0x01,0x02,0x01,0xe5,0x03,0x04,0x11,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x0a,
+ 0x01,0x01,0x11,0x01,0x13,0x03,0x03,0xe5,0x07,0x09,0x01,0x02,0xe5,0x06,0x01,0x01,
+ 0x04,0xe5,0x02,0x03,0x01,0x02,0xe5,0x03,0xe5,0x02,0x03,0x01,0x01,0x01,0x04,0xe5,
+ 0x01,0xe5,0x03,0xe5,0xe5,0xe5,0x04,0x02,0xe5,0x0e,0x02,0xe5,0x04,0x02,0xe5,0xe5,
+ 0xe5,0x06,0x06,0xe6,0xe5,0x08,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,
+ 0x08,0x01,0x2b,0x01,0x01,0x02,0x06,0x0b,0x05,0x09,0xe5,0x07,0x05,0x0e,0x02,0x01,
+ 0x03,0xe5,0x07,0xe5,0x11,0x13,0x01,0xe5,0x05,0x01,0xe6,0xe5,0x02,0x04,0x03,0x02,
+ 0xe8,0x0f,0x09,0x0a,0x04,0x01,0xe5,0x2d,0x09,0x03,0x06,0x01,0x01,0x02,0x05,0x0c,
+ 0x0c,0x0b,0x02,0x01,0x04,0x02,0x24,0xe5,0xe5,0x19,0x02,0x0d,0x01,0x01,0x11,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x04,0x02,0x01,0xe5,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x02,0x01,0x04,0x01,
+ 0xe5,0x05,0xe6,0xe5,0x04,0x01,0x03,0x03,0x01,0x02,0xe5,0x02,0x01,0x06,0xe7,0x06,
+ 0x01,0x07,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x07,0x01,0xe5,0x05,0x01,0x0a,0x01,
+ 0x01,0x02,0x0c,0xe5,0x01,0x05,0xe5,0x07,0xe6,0x05,0x0c,0x20,0x04,0xe5,0x06,0xe7,
+ 0x0b,0x04,0xe5,0x09,0xe5,0xe6,0x04,0xe5,0x08,0x06,0x01,0xe5,0x05,0x01,0xe5,0x01,
+ 0x06,0xe5,0x01,0x05,0x0f,0x02,0xe5,0x07,0xe6,0xe5,0xe5,0x02,0xe5,0x01,0x03,0xe5,
+ 0x01,0x0c,0x01,0xe7,0xe5,0x04,0x35,0x27,0x01,0x04,0xe5,0x0c,0x02,0x03,0x03,0x06,
+ 0x03,0x03,0x04,0x03,0x03,0x02,0x08,0x08,0x01,0x03,0x04,0x06,0x05,0xe5,0x0a,0x0c,
+ 0x1a,0xe5,0x02,0x01,0x0b,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x10,0x23,0x01,0x09,
+ 0x0c,0x05,0x01,0x03,0x01,0x01,0x01,0x07,0x02,0x01,0x04,0x03,0x05,0x02,0xe5,0xe5,
+ 0x05,0x02,0x22,0x01,0x07,0x01,0x02,0x04,0x01,0x18,0x03,0x28,0x02,0x01,0x17,0x0a,
+ 0x06,0x02,0x09,0x02,0x01,0x01,0x05,0xe6,0x17,0x01,0x02,0x01,0x18,0x04,0xe5,0x1d,
+ 0x07,0xe6,0x07,0x09,0x03,0x04,0x04,0x09,0x01,0x01,0x2c,0x01,0xe5,0x01,0x0a,0x27,
+ 0x02,0x01,0x06,0x07,0x09,0x01,0xe5,0x07,0x01,0x02,0x03,0x1f,0x06,0x0b,0x1b,0x0b,
+ 0x12,0x01,0x01,0x13,0x07,0x01,0x09,0x04,0xe5,0x02,0x01,0x02,0xe5,0x14,0x01,0x04,
+ 0xe5,0x14,0x01,0xe5,0x07,0x06,0x01,0x04,0xe5,0x02,0x0c,0x09,0xe5,0x0b,0x05,0x13,
+ 0x09,0x03,0x04,0x0b,0x08,0x03,0x01,0x03,0x0c,0xe6,0x1c,0x0d,0x09,0x01,0x0e,0x0c,
+ 0x20,0x0f,0xe5,0x0d,0x15,0x13,0x11,0x14,0x0f,0xe5,0x0f,0x02,0x1c,0xe5,0x07,0x06,
+ 0x02,0x1e,0x05,0x0b,0x0c,0x06,0x0c,0x0c,0x10,0x01,0x11,0x08,0x37,0x10,0x03,0x0d,
+ 0xe5,0x07,0xe5,0x35,0x24,0x03,0x02,0xe5,0x03,0x02,0xe5,0xe6,0x01,0x02,0x01,0xe6,
+ 0x02,0x03,0xe5,0x04,0x02,0xe6,0x03,0x02,0x09,0x09,0x07,0x02,0x01,0x11,0xe5,0x02,
+ 0x04,0xe5,0x18,0x01,0xe6,0x05,0x09,0x09,0x3e,0x08,0x12,0x05,0x02,0xe5,0x04,0x01,
+ 0x02,0x06,0x02,0x06,0x09,0x02,0x21,0x01,0x0f,0x07,0x09,0x17,0x02,0xe5,0x0d,0x09,
+ 0x07,0x06,0x05,0x04,0x04,0x04,0x09,0x02,0x01,0x09,0x19,0x0a,0xe5,0xe5,0x01,0x01,
+ 0x03,0x0c,0x06,0x06,0x05,0x04,0x12,0x14,0x09,0x01,0x01,0x09,0x08,0x01,0x0f,0x01,
+ 0xe6,0x18,0x04,0x09,0x02,0xe5,0x08,0x11,0x01,0x04,0x0f,0x0b,0x10,0x0c,0x02,0x05,
+ 0x01,0x08,0x05,0x02,0x01,0x08,0x05,0x02,0x0a,0x02,0x1e,0x05,0x02,0x11,0x01,0x01,
+ 0x01,0xe5,0x2c,0x04,0x02,0xe5,0x1b,0x28,0x17,0xe5,0x11,0x12,0x10,0x1b,0x17,0x05,
+ 0xe6,0xe7,0x0e,0x09,0x02,0xe5,0x04,0xe5,0x0d,0x24,0x01,0x04,0x01,0xe5,0x01,0x17,
+ 0x0b,0x02,0xe5,0xe5,0x02,0x02,0xe5,0x05,0x01,0x01,0x04,0x02,0xe5,0x06,0xe5,0x01,
+ 0xe5,0x0b,0x02,0x01,0x04,0x05,0x06,0x01,0x04,0x09,0xe5,0x12,0xe5,0xe8,0x01,0x01,
+ 0x0b,0x09,0x03,0xe5,0x04,0x0f,0xe6,0x21,0xe5,0xe6,0x01,0x05,0x09,0xe5,0x0a,0x07,
+ 0x03,0x02,0xe5,0x01,0x02,0x02,0xe5,0x08,0x01,0xe6,0xe5,0x01,0xe5,0x0b,0x04,0x01,
+ 0x01,0x04,0x01,0xe5,0x05,0x05,0x05,0xe5,0x04,0x09,0x12,0x01,0x02,0x01,0x01,0x04,
+ 0x23,0x01,0x06,0xe5,0x01,0x01,0x18,0xe5,0x0c,0x02,0x04,0x06,0xe5,0x02,0x07,0x01,
+ 0x03,0xe5,0x03,0x01,0x07,0x09,0x01,0x09,0x03,0xe5,0x01,0x01,0x04,0xe5,0x05,0x0e,
+ 0x01,0x07,0x29,0x05,0x02,0x02,0x25,0x09,0x02,0x01,0x18,0xe5,0x0a,0x09,0x06,0xe5,
+ 0xe5,0x08,0x01,0x09,0x01,0x07,0x06,0xe5,0xe5,0xe5,0x06,0x09,0x01,0x04,0x16,0x01,
+ 0x07,0x19,0xe5,0x0f,0x03,0xe5,0xe5,0x05,0x0b,0x09,0x09,0x02,0x01,0x02,0x04,0xe5,
+ 0x01,0x1b,0x02,0x05,0x02,0x02,0x03,0xe5,0x03,0x04,0x01,0x02,0x01,0x01,0x05,0x0b,
+ 0x04,0x04,0x09,0x06,0x02,0x01,0x01,0x05,0x02,0x01,0x01,0x02,0x01,0x01,0x05,0x09,
+ 0x04,0x0e,0x09,0x07,0x05,0x07,0xe6,0xe5,0x01,0x2b,0x03,0xe7,0x02,0x02,0x01,0x17,
+ 0x03,0xe7,0x02,0x03,0xe6,0x02,0x05,0x01,0x02,0x08,0x06,0x04,0x05,0x03,0x09,0x05,
+ 0x03,0x01,0x02,0x04,0x05,0x04,0x01,0x01,0x0e,0x05,0x03,0x19,0x02,0x03,0xe6,0xe5,
+ 0x01,0x03,0xe5,0xe6,0x03,0xe5,0x0c,0x09,0x06,0x02,0x02,0x01,0x07,0x01,0x1b,0x01,
+ 0x09,0x01,0x03,0x01,0x05,0xe5,0x01,0x01,0x07,0x01,0x01,0xe5,0x05,0x01,0x02,0x01,
+ 0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x04,0x02,0x04,0x01,0x04,0x04,0x0e,0x01,0xe5,
+ 0xe5,0x06,0x0e,0x08,0x02,0x02,0x0f,0x01,0x01,0xe5,0x05,0x0a,0xe8,0x04,0xe8,0x05,
+ 0xe7,0xe5,0x01,0x06,0x01,0x1b,0x02,0x06,0x04,0x01,0x01,0xe5,0x02,0xe5,0x03,0x09,
+ 0x01,0x02,0x01,0x01,0x02,0x01,0x01,0xe5,0xe5,0xe6,0x02,0xe5,0xe5,0xe6,0xe5,0xe6,
+ 0x01,0x01,0x03,0xe5,0x03,0x01,0x01,0xe5,0x01,0x01,0x0d,0xe5,0xe5,0x01,0x01,0x01,
+ 0xe5,0x03,0x0d,0xe5,0xe5,0xe5,0x04,0xe7,0xe5,0xe6,0x0d,0xe7,0x0f,0x09,0x09,0x09,
+ 0x02,0x09,0x02,0x17,0x09,0x09,0x13,0x0b,0x09,0x09,0x09,0x09,0x13,0x02,0x01,0x04,
+ 0x13,0x09,0x09,0x02,0x0b,0x02,0x10,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0x01,0x07,0x1d,
+ 0x05,0xe5,0x07,0xe5,0x11,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0x09,0xe5,0x03,0x03,0xe5,0x11,0xe5,0x07,0xe5,0x0b,0x01,0x08,0xea,0x0b,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x01,0x01,0x02,0xe5,0xe6,0x04,0x03,0x05,0x09,0x06,0x02,0xe5,
+ 0x03,0x03,0xe6,0x06,0xe5,0x07,0x09,0xe6,0x03,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x09,0xe5,0x07,0xe6,0x03,
+ 0x02,0xe5,0x01,0x08,0xe8,0xe5,0x01,0x4c,0x02,0x2e,0x02,0x32,0xe5,0x1c,0x1a,0x02,
+ 0x0e,0x04,0x01,0x11,0x09,0x35,0x19,0x17,0x07,0x09,0x09,0x09,0x09,0x01,0x11,0x09,
+ 0x01,0x11,0x0c,0x17,0x0a,0x05,0xe6,0x06,0xe6,0x06,0xe6,0x03,0x02,0x1c,0x07,0x02,
+ 0x09,0xe6,0x06,0xe6,0x03,0x06,0x04,0xe7,0xe5,0x02,0x02,0xe7,0xe5,0x03,0xe7,0xe5,
+ 0x01,0x01,0xe7,0xe5,0x03,0xe5,0xe5,0x03,0x01,0xe7,0x03,0x01,0x04,0x02,0x01,0xe7,
+ 0xe5,0x01,0x01,0xe7,0x05,0x04,0x05,0xe6,0x06,0x01,0x04,0x02,0x0d,0xe5,0xe6,0x10,
+ 0x09,0x09,0x05,0x0d,0x11,0xe5,0x07,0x0b,0x02,0x06,0x02,0x04,0x01,0x07,0xe6,0x06,
+ 0x02,0xe5,0x03,0x02,0xe6,0x04,0x01,0xe6,0x06,0xe6,0x04,0x01,0xe6,0x06,0xe6,0x04,
+ 0x01,0xe6,0x03,0xe5,0xe7,0x04,0x02,0x0a,0x09,0x05,0x09,0xe5,0x02,0x02,0xe8,0x07,
+ 0x07,0x09,0x1b,0x10,0x02,0x07,0x10,0x0c,0x08,0x02,0x01,0x09,0x01,0x07,0x03,0xe5,
+ 0xe6,0xe6,0x07,0x06,0xe5,0xe5,0x02,0x03,0x01,0x0b,0x01,0x03,0x01,0x03,0x05,0x2c,
+ 0xe5,0x01,0x13,0xe7,0x05,0xe7,0x02,0x02,0xe8,0x06,0xe5,0x01,0x05,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x02,0x02,0x01,0xe5,0x02,0x04,0xe5,0x01,0x05,0xe5,0x01,
+ 0x03,0xe7,0xe6,0x04,0xe7,0x01,0xe5,0x01,0x01,0xe6,0xe5,0x02,0xe7,0x01,0x03,0xe8,
+ 0xe6,0x01,0xe7,0x01,0x03,0xe7,0x05,0x01,0xe6,0xe6,0x01,0xe8,0x06,0xe5,0x02,0x02,
+ 0xe7,0x05,0xe8,0x06,0xe7,0x02,0x01,0x01,0x01,0x10,0x09,0x09,0xe5,0x24,0x14,0xe5,
+ 0x07,0x12,0xe5,0x01,0x02,0x04,0xe5,0x01,0x02,0x02,0xe6,0x03,0x06,0x02,0x02,0x06,
+ 0x03,0x02,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x09,0x05,0x0d,0xe5,0x07,0xe5,0x17,0x01,
+ 0x13,0x02,0x06,0x02,0x06,0x02,0x20,0x09,0x0d,0x12,0x06,0x04,0x01,0x01,0xe5,0x05,
+ 0xe6,0x01,0x03,0x01,0xe5,0x07,0xe5,0x01,0x04,0xe6,0x07,0xe6,0xe5,0x02,0x01,0xe6,
+ 0xe5,0x04,0x04,0x02,0x01,0xe5,0x0f,0x02,0x06,0x02,0x0a,0xe5,0x03,0xe5,0xe8,0x0e,
+ 0x03,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x0c,0x13,0x19,0x04,0x12,0xe5,0x03,0x05,0xe5,
+ 0x03,0x03,0x05,0x08,0xe5,0x02,0x03,0x01,0x04,0x03,0xe5,0xe5,0xe5,0x03,0xe5,0x06,
+ 0x01,0x08,0xe5,0x11,0xe5,0x07,0xe5,0x0a,0x06,0xe5,0x01,0x12,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe7,0x0a,0x02,0x10,0x16,0xe5,0xe5,0x05,0x10,0x02,0x01,0xe5,0x02,
+ 0x04,0x01,0x04,0x02,0xe6,0x06,0x06,0x02,0xe6,0x06,0x04,0x01,0xe5,0xe7,0x06,0x09,
+ 0xe5,0x11,0xe5,0xe6,0x04,0xe5,0xe7,0x09,0x03,0x02,0x02,0x11,0x19,0xe5,0xe5,0xe5,
+ 0x08,0x18,0x02,0x0a,0x05,0x01,0xe6,0x06,0xe5,0x0d,0x02,0x0d,0x0e,0x17,0xe5,0x0d,
+ 0x0e,0x01,0x1a,0xe5,0x0c,0x02,0xe5,0x08,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x03,
+ 0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x01,
+ 0x05,0x01,0x01,0x05,0x01,0xe6,0x06,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x06,0xe7,0x06,0xe6,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0xe6,
+ 0x06,0x01,0x0a,0xe6,0xe5,0x0e,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x03,0x0f,0x19,0xe5,
+ 0x05,0xe5,0x01,0xe6,0x05,0xe6,0xe5,0x07,0x07,0xe5,0x09,0x03,0x03,0x19,0x06,0xe6,
+ 0x02,0x02,0x0a,0x02,0x06,0x06,0x0f,0x05,0xe6,0x02,0x0f,0x03,0x02,0xe5,0x06,0x02,
+ 0x01,0x01,0x05,0x01,0x01,0x03,0x02,0x01,0x04,0x20,0x10,0x04,0x09,0x07,0x07,0x02,
+ 0x01,0x0c,0x17,0x06,0x02,0x03,0x03,0x08,0x05,0x06,0x02,0x0d,0x0d,0x01,0x01,0x17,
+ 0xe5,0xe5,0xe5,0x04,0x0c,0x0b,0x04,0x04,0x07,0x2e,0x08,0x07,0x05,0x03,0x09,0x04,
+ 0x06,0x27,0x02,0x3d,0x0d,0x02,0x2d,0x25,0xe5,0x06,0x03,0x03,0x06,0x02,0x02,0x01,
+ 0x0c,0xe5,0x03,0x07,0x0b,0xe5,0x05,0x09,0x04,0x02,0x02,0x01,0x01,0x06,0x0c,0xe5,
+ 0x05,0x01,0x0e,0x09,0x04,0x0f,0xe7,0x27,0x03,0x10,0x28,0x08,0x03,0x05,0x09,0x01,
+ 0x09,0x08,0x04,0x11,0x17,0x05,0x09,0x01,0x04,0x17,0x0f,0xe5,0x01,0x09,0x09,0x09,
+ 0x08,0x1d,0x06,0x03,0x01,0x08,0x12,0x03,0x06,0x06,0xe5,0x03,0x05,0x29,0x31,0x0b,
+ 0x04,0x0f,0xe6,0x12,0x35,0x27,0x0c,0x0d,0x07,0x03,0x0f,0x04,0x0f,0x1c,0x09,0x09,
+ 0x0c,0x02,0x04,0x02,0x01,0x01,0x06,0x15,0xe5,0x01,0x28,0x02,0x0d,0x13,0x02,0x10,
+ 0x02,0xe5,0x0e,0x08,0x02,0x08,0xe6,0x18,0x1e,0x15,0x02,0x06,0x03,0x01,0x06,0x19,
+ 0x04,0x01,0x04,0x17,0x1d,0x02,0xe5,0x03,0x09,0x02,0x09,0xe5,0x01,0x02,0x01,0x02,
+ 0xe6,0x04,0x01,0xe6,0x06,0x0a,0x01,0x07,0x05,0x0d,0xe5,0x0b,0x2c,0x01,0x1e,0x03,
+ 0x0f,0x37,0x16,0x03,0x03,0x09,0x07,0x01,0x1b,0x0d,0x07,0x01,0x02,0x24,0x0e,0xe6,
+ 0xe5,0xe5,0x06,0x0e,0x0b,0xe5,0x04,0x3a,0xe5,0xe6,0xe5,0x03,0x04,0x01,0xe5,0xe5,
+ 0x03,0x0a,0xe5,0xe5,0xe5,0x03,0x07,0x01,0xe5,0x03,0xe5,0x04,0xe5,0xe5,0x01,0x0a,
+ 0x05,0x04,0x03,0x0a,0x05,0xe5,0x03,0x0a,0x11,0x07,0xe5,0x31,0x05,0x14,0x09,0xe5,
+ 0x07,0x05,0xe5,0x08,0x09,0x04,0x09,0x09,0x0a,0x04,0xe5,0x03,0xe5,0x08,0x0e,0x12,
+ 0x02,0x25,0x02,0xe6,0x01,0x09,0x1b,0x05,0x0d,0x14,0x17,0x01,0x08,0xe5,0x01,0x07,
+ 0x26,0x01,0x1c,0x05,0x0a,0x02,0xe5,0x30,0xe6,0x0e,0x02,0x01,0x04,0x02,0xe5,0x04,
+ 0xe5,0x0d,0x20,0xe5,0x01,0xe5,0x04,0x0f,0x06,0xe5,0x04,0x06,0x04,0x02,0xe5,0xe5,
+ 0x02,0xe5,0x07,0x0c,0x01,0x02,0x07,0x10,0x01,0x04,0x0c,0xe5,0x05,0x01,0x01,0x04,
+ 0xe5,0x06,0x01,0x09,0xe6,0x01,0xe5,0x01,0x01,0x05,0xe5,0x04,0x02,0xe5,0x04,0xe5,
+ 0xe5,0xe5,0x03,0x0f,0x13,0xe6,0x03,0x01,0x07,0xe5,0x04,0x05,0xe5,0x0c,0x08,0x0b,
+ 0x01,0xe5,0x01,0x02,0x01,0x08,0x0b,0xe5,0x0b,0x0f,0xe5,0x04,0x0d,0xe5,0x07,0x01,
+ 0x0b,0xe5,0x08,0x01,0x02,0xe5,0xe6,0x03,0x0f,0xe5,0xe5,0xe5,0x0c,0xe5,0x03,0x07,
+ 0x15,0x0b,0x11,0x04,0x01,0x0a,0x01,0x03,0xe5,0x03,0x01,0x07,0x09,0x01,0x04,0xe5,
+ 0xe5,0x05,0x01,0xe5,0xe5,0x06,0x06,0x01,0xe5,0x0f,0x01,0x18,0x07,0x09,0x06,0x01,
+ 0x02,0x14,0x01,0x0d,0xe5,0x01,0x09,0x13,0x01,0x1b,0x06,0xe5,0x02,0x04,0xe5,0xe5,
+ 0xe5,0x07,0xe5,0xe5,0x06,0x05,0xe5,0x01,0x01,0x04,0xe5,0x0a,0x01,0x07,0x06,0x02,
+ 0x10,0x02,0x1f,0x0b,0x04,0x01,0x12,0x09,0x09,0x07,0x02,0x02,0xe5,0x12,0x01,0x04,
+ 0x01,0x0f,0x06,0x02,0x03,0x07,0x01,0x05,0x0b,0x04,0x04,0x09,0x09,0xe5,0x01,0x05,
+ 0x04,0x04,0x02,0x01,0x0e,0x02,0x07,0x02,0x05,0x09,0x06,0x0e,0x03,0x02,0x18,0x12,
+ 0x05,0xe5,0x02,0x0f,0x01,0x01,0x19,0x03,0x03,0x05,0x04,0x04,0x0b,0x05,0x03,0x09,
+ 0x0a,0x01,0x01,0x04,0x05,0x03,0x05,0x17,0x04,0x16,0x01,0x09,0x03,0xe8,0x15,0x01,
+ 0x04,0x01,0x04,0x05,0x07,0x01,0x13,0x01,0x15,0x07,0x03,0xe5,0x09,0x01,0x01,0x01,
+ 0xe5,0x05,0x01,0x02,0x01,0x01,0xe5,0x05,0x02,0x01,0x01,0x02,0x01,0xe5,0x08,0x01,
+ 0x07,0x03,0x01,0xe5,0x1d,0x08,0x01,0x04,0x01,0xe5,0x03,0x04,0x01,0x01,0x04,0xe9,
+ 0x10,0xe5,0x03,0x01,0x01,0xe5,0xe5,0xe5,0x04,0x04,0x02,0x06,0x13,0x01,0x16,0x04,
+ 0x03,0xe5,0x05,0x07,0x01,0x02,0xe6,0x03,0x01,0x01,0xe5,0xe5,0xe6,0x02,0xe5,0xe6,
+ 0xe5,0xe5,0x01,0xe6,0x0b,0x01,0x01,0xe5,0xe5,0x01,0x04,0x12,0xe5,0x11,0xe5,0xe5,
+ 0xe5,0x04,0x01,0x04,0x03,0xe5,0x09,0x01,0xe5,0x0f,0x09,0x02,0x06,0x09,0x31,0x02,
+ 0x06,0x0c,0x02,0x03,0x0b,0x09,0x02,0x01,0x04,0x13,0x04,0x04,0x13,0x0c,0x06,0x09,
+ 0x04,0x07,0x02,0x08,0x02,0x02,0x0d,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0x39,0xe5,
+ 0x01,0xe6,0x02,0xe5,0x11,0xe5,0x09,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0x11,0xe5,
+ 0x07,0xe5,0x08,0x08,0xe5,0x0b,0x01,0x03,0xe5,0x07,0xe5,0x0b,0xe5,0x05,0x01,0xe6,
+ 0xe6,0x0d,0xe5,0x07,0xe5,0x03,0x03,0xe6,0x03,0x02,0xe5,0xe5,0x05,0x09,0x06,0x02,
+ 0x02,0x06,0x09,0xe6,0x06,0xe5,0x04,0x02,0x09,0xe6,0x08,0xe5,0x07,0xe5,0x03,0x03,
+ 0xe6,0x03,0x02,0x09,0xe5,0x07,0xe7,0x05,0x09,0xe5,0x04,0x02,0x03,0x05,0xe5,0x07,
+ 0xe6,0x06,0x0d,0xe6,0x01,0x02,0x24,0x02,0x1c,0xe5,0x25,0xe5,0x31,0xe5,0x2f,0xe5,
+ 0x2b,0x03,0xe7,0x10,0x09,0x0d,0x1d,0x23,0x03,0x1b,0x09,0x0d,0x0f,0x1d,0x03,0x0f,
+ 0x20,0x01,0xe6,0x0f,0xe6,0x02,0xe5,0xe8,0x06,0xe6,0x03,0x02,0x2e,0x01,0xe7,0xe5,
+ 0x03,0xe5,0xe5,0x03,0x01,0x09,0xe7,0x04,0xe5,0xe8,0x02,0xe5,0xe8,0x03,0x01,0xe7,
+ 0x03,0x01,0x09,0xe7,0xe5,0x01,0x01,0xe7,0x03,0x0c,0xe6,0x10,0x01,0x01,0x05,0x01,
+ 0x03,0x11,0xe5,0xe6,0x10,0x05,0x01,0xe6,0x08,0x07,0x1f,0x0c,0x02,0x01,0xe6,0x06,
+ 0xe6,0x04,0x01,0xe6,0x01,0x04,0xe6,0x01,0x01,0x02,0x01,0xe6,0x01,0x02,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x03,0x04,0x02,0xe6,0x04,0x01,0xe6,0x04,0x03,0x01,0x07,0x04,
+ 0xe5,0xe7,0x08,0x09,0x08,0x06,0xe5,0x02,0x01,0xe5,0x01,0xe5,0x0f,0x09,0x02,0x2c,
+ 0x0d,0x02,0x06,0x05,0x04,0x02,0x01,0x09,0x01,0x07,0x01,0x01,0x0f,0x01,0xe5,0x01,
+ 0x03,0x01,0x03,0x05,0xe5,0x01,0xe5,0x01,0x01,0xe5,0x02,0x02,0x10,0x04,0x1b,0x01,
+ 0x0e,0x03,0x13,0xe7,0x05,0xe7,0x02,0x02,0xe7,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe6,
+ 0x06,0xe5,0x07,0xe5,0x02,0x02,0x01,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x01,0x03,
+ 0xe7,0xe6,0xe5,0x02,0xe7,0x02,0x02,0x01,0xe6,0xe5,0x02,0xe8,0x04,0x01,0xe5,0x01,
+ 0x03,0xe8,0xe5,0x02,0xe8,0x04,0x01,0xe5,0x02,0x02,0xe8,0x05,0xe6,0x05,0xe7,0x05,
+ 0xe8,0xe5,0x04,0xe7,0x02,0x02,0xe7,0x16,0x01,0x0a,0x06,0x31,0x01,0xe6,0x06,0xe5,
+ 0x07,0x09,0x03,0x08,0x02,0x03,0x01,0xe6,0x07,0xe5,0xe5,0x04,0x09,0x03,0x06,0x02,
+ 0x10,0x0d,0x01,0x09,0x03,0xe5,0x03,0x13,0x01,0x13,0x02,0xe5,0xe5,0x02,0x02,0x03,
+ 0x02,0x02,0x32,0x01,0x03,0x05,0xe5,0x05,0x04,0x06,0x04,0x01,0x05,0x03,0x01,0xe5,
+ 0xe5,0x02,0x02,0x05,0x03,0xe5,0x03,0x03,0x02,0x06,0x09,0x05,0x0a,0x02,0x05,0x0a,
+ 0x01,0xe5,0x05,0x01,0xe5,0x09,0xe5,0x03,0xe5,0x02,0x11,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x20,0x01,0x13,0x03,0x03,0x01,0x11,0x01,0x03,0xe5,0xe5,0x03,0x03,
+ 0x05,0x03,0x08,0xe5,0x02,0x03,0x01,0x03,0x01,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x06,
+ 0x01,0x04,0xe5,0x01,0xe5,0x0e,0x02,0xe5,0x04,0x02,0xe5,0xe5,0xe5,0x06,0x06,0x01,
+ 0x01,0x13,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x1d,0x19,0x01,0x03,0x07,0x0b,
+ 0x04,0xe5,0x09,0xe6,0x05,0xe7,0x06,0xe7,0x04,0xe7,0x01,0x05,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0x07,0x01,0xe5,0x0f,0x09,0x03,0x01,0x08,0x03,0x02,0x02,0xe5,0x0f,0x09,
+ 0x09,0x08,0x06,0x01,0xe5,0x0f,0x45,0x01,0x13,0x02,0x0a,0x08,0x06,0x02,0x0b,0x04,
+ 0x01,0xe5,0x09,0x09,0x05,0x02,0x01,0x08,0x03,0xe7,0x01,0x03,0x0a,0xe6,0x01,0x04,
+ 0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x03,0x03,0x01,0x07,0x01,0x03,0x03,0x01,0x07,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x07,0x01,0xe6,
+ 0x01,0x02,0x01,0xe5,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x01,0x01,0x03,
+ 0x01,0x07,0x01,0x04,0x02,0xe6,0x06,0x01,0x07,0x01,0x02,0x04,0x01,0x0a,0xe5,0xe6,
+ 0x0e,0xe6,0x06,0xe5,0x07,0xe5,0x05,0x12,0x20,0xe5,0x04,0x02,0xe5,0x01,0x02,0x15,
+ 0x06,0x08,0x06,0xe6,0x01,0x01,0xe6,0x01,0x04,0x0a,0x02,0x06,0x03,0x01,0x05,0x06,
+ 0x07,0x04,0x03,0x05,0xe5,0x05,0xe5,0x0f,0xe5,0xe6,0x09,0x08,0x13,0x09,0x15,0x13,
+ 0x0c,0x1a,0x01,0x03,0x05,0x08,0x02,0xe5,0xe5,0x14,0x03,0x05,0x09,0x02,0x02,0x03,
+ 0xe5,0x0a,0x08,0x01,0x01,0x04,0x0a,0x07,0x02,0xe6,0x02,0x09,0x01,0x02,0x04,0x01,
+ 0x07,0x01,0x0c,0x07,0x24,0x01,0x07,0x06,0x06,0xe5,0xe5,0x08,0x01,0x0b,0x17,0x0b,
+ 0x13,0x0d,0x09,0x02,0x06,0x05,0x0b,0x07,0x02,0xe5,0xe5,0x0a,0x12,0x09,0x02,0x17,
+ 0x16,0x09,0x22,0x01,0x0e,0x02,0x02,0x08,0x11,0xe6,0x06,0xe5,0x11,0xe5,0x02,0x1e,
+ 0x0a,0xe5,0x01,0x08,0x16,0x0d,0x0f,0x05,0x29,0x01,0x07,0xe5,0xe5,0x09,0x02,0xe5,
+ 0x05,0x08,0x03,0x04,0x10,0x06,0x06,0x1d,0x0a,0x1b,0x02,0xe5,0x08,0x09,0x09,0x09,
+ 0x08,0x0f,0xe5,0x20,0x0f,0x0b,0x01,0x03,0x03,0x09,0x02,0x07,0x06,0x01,0xe5,0x07,
+ 0x01,0x07,0x0c,0x0f,0xe6,0x07,0x03,0x09,0x09,0x0e,0x01,0x18,0xe5,0x07,0x1a,0x01,
+ 0x02,0x09,0xe5,0x07,0x07,0x0b,0x04,0x0c,0x08,0x06,0x02,0x02,0x03,0x0c,0x01,0x07,
+ 0x09,0x01,0x0f,0x06,0x04,0x09,0xe5,0xe5,0x02,0x08,0x06,0x08,0x04,0x02,0xe5,0x07,
+ 0x09,0x01,0x07,0x16,0x12,0x13,0x07,0x08,0x01,0xe5,0x01,0x02,0x05,0x04,0x04,0xe5,
+ 0xe5,0x01,0x06,0x02,0x02,0x10,0x0b,0x07,0x17,0x04,0x07,0x1a,0x0a,0x02,0x06,0x10,
+ 0xe5,0x06,0x2e,0x11,0x09,0xe5,0xe5,0x05,0x09,0x02,0x02,0xe5,0x0a,0x05,0x02,0xe5,
+ 0x02,0x0a,0xe5,0x08,0x16,0xe5,0x07,0xe5,0x0c,0x04,0xe6,0x17,0x02,0xe5,0x02,0x13,
+ 0x02,0x0d,0x01,0x41,0x18,0x0d,0x06,0xe6,0x06,0x2b,0x06,0x01,0x12,0x19,0x02,0xe5,
+ 0x02,0x0b,0x22,0x09,0x09,0x05,0x03,0x04,0x02,0xe6,0x03,0x03,0x0f,0x03,0xe5,0xe5,
+ 0x05,0x05,0x01,0x09,0xe5,0x05,0x01,0x04,0x04,0x03,0x02,0x06,0x05,0x03,0xe6,0x06,
+ 0x04,0x04,0xe5,0xe5,0x01,0x04,0x01,0x16,0x0b,0x03,0x01,0xe6,0x01,0x06,0x02,0xe6,
+ 0x17,0x04,0x26,0xe5,0x03,0x02,0xe6,0xe5,0x0c,0xe5,0x0b,0x02,0x05,0x02,0x02,0xe5,
+ 0x03,0x03,0x06,0x07,0x01,0xe5,0x09,0x05,0x01,0x19,0x02,0xe5,0x1c,0x0d,0x01,0xe7,
+ 0x0b,0x0e,0x10,0x20,0x07,0x1b,0x0a,0x0b,0x13,0x08,0x03,0x09,0x05,0x1c,0x02,0x04,
+ 0x06,0x12,0x0e,0xe9,0x07,0xe5,0x04,0x09,0x02,0x01,0x0d,0xe5,0x07,0xe6,0x03,0x02,
+ 0x17,0xe5,0x2c,0xe6,0x01,0xe5,0x03,0xe5,0x13,0x04,0x0b,0x02,0x01,0x01,0xe5,0xe7,
+ 0x04,0x01,0x18,0x01,0x02,0x01,0x05,0x01,0x0c,0xe8,0xe5,0x01,0x01,0x05,0x01,0x04,
+ 0x08,0x02,0xe5,0x0f,0x02,0x01,0x0a,0xe6,0x17,0xe5,0xe6,0x0e,0xe5,0x1a,0x02,0x01,
+ 0x14,0x09,0xe6,0x06,0xe5,0x04,0x01,0xe7,0x08,0x18,0xe5,0x04,0x05,0x0b,0x01,0x02,
+ 0xe6,0xe5,0x03,0x34,0x02,0xe5,0xe5,0xe5,0x03,0x01,0x02,0x04,0xe5,0x0c,0x03,0xe5,
+ 0x03,0x04,0xe5,0x07,0x01,0x02,0x03,0xe5,0x08,0x01,0xe5,0x01,0x02,0x02,0x01,0xe5,
+ 0xe5,0x01,0x01,0x01,0x02,0x04,0x01,0xe5,0xe5,0x06,0x06,0xe5,0x04,0x05,0x10,0x01,
+ 0xe5,0x05,0x01,0xe5,0xe5,0x06,0x0b,0x05,0x02,0x02,0x39,0xe5,0xe5,0xe5,0x03,0x04,
+ 0x11,0x06,0xe5,0xe5,0x04,0xe5,0x03,0x04,0xe5,0xe5,0x10,0xe5,0x08,0xe5,0xe5,0xe5,
+ 0x03,0xe5,0xe5,0xe5,0x03,0x02,0x01,0x04,0xe5,0xe5,0x05,0x0e,0x0e,0xe5,0x07,0x02,
+ 0x01,0x07,0x0d,0x02,0xe5,0xe6,0x11,0x09,0x09,0x18,0x01,0x05,0x06,0x0a,0x02,0x02,
+ 0x02,0x0b,0x01,0xe5,0x05,0x01,0xe5,0x03,0x01,0x01,0x04,0x03,0x02,0x0f,0x06,0x02,
+ 0xe5,0xe7,0xe5,0x01,0x04,0x04,0x02,0x01,0x01,0x07,0x0b,0xe5,0xe5,0xe5,0xe5,0x07,
+ 0x06,0x04,0x0a,0x06,0xe7,0x01,0x3c,0x03,0x0a,0x0d,0xe5,0x02,0x02,0x01,0x09,0xe5,
+ 0x02,0x04,0x02,0x02,0xe5,0x01,0x10,0x02,0x01,0x04,0x05,0x04,0x04,0x03,0x02,0x01,
+ 0xe5,0x03,0x01,0x01,0xe5,0xe5,0xe5,0x06,0x01,0x01,0x02,0xe5,0x01,0x05,0x03,0x0a,
+ 0x05,0x03,0x09,0x02,0xe6,0xe6,0x12,0x01,0x07,0x06,0x02,0x01,0x05,0x0e,0x01,0x02,
+ 0x01,0x01,0x02,0x0f,0x03,0x01,0xe5,0xe5,0x03,0x02,0x02,0x01,0x04,0x02,0x01,0x01,
+ 0x0e,0x05,0x03,0x04,0x01,0x04,0x04,0x07,0x01,0x04,0x01,0xe5,0x0d,0x04,0x0b,0x02,
+ 0x02,0x0b,0x01,0x01,0x05,0x06,0x08,0x01,0xe5,0xe5,0x10,0xe7,0x05,0xe5,0x01,0x06,
+ 0x01,0x16,0x01,0x04,0x01,0x02,0x09,0x07,0x04,0x01,0xe7,0x08,0x09,0x01,0x08,0x14,
+ 0x01,0x01,0xe5,0x01,0x01,0x09,0x01,0xe6,0xe6,0x01,0x15,0x0a,0xe5,0x0e,0x01,0x02,
+ 0x04,0x05,0xe6,0x08,0xe7,0x0f,0x09,0x09,0x04,0x36,0x0c,0x09,0x02,0x12,0x05,0x03,
+ 0x06,0x13,0x27,0x0c,0x06,0x0c,0x02,0x07,0x02,0xe5,0x0f,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x1f,0x10,0x08,0xe5,0x08,0x02,0xe6,0x06,0x09,0x07,0xe5,0x03,0x07,0x01,0x03,0xe5,
+ 0x1f,0x13,0x09,0xe5,0x04,0x02,0x01,0x03,0xe5,0x0b,0xe5,0x08,0x02,0xe5,0x0d,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x06,0x09,0x09,0x05,0x03,0x09,0x09,0xe6,0x06,0x06,0x02,0x05,
+ 0x03,0x05,0x02,0x02,0xe5,0x07,0x02,0xe5,0x04,0xe5,0x04,0x02,0x09,0x06,0x02,0x05,
+ 0x03,0x09,0x03,0x05,0xe5,0x02,0x01,0x02,0xe6,0xe5,0x04,0xe7,0x02,0x02,0x02,0x0a,
+ 0x03,0xe5,0x01,0x6a,0x02,0x13,0x0b,0x12,0xe5,0x08,0x08,0xe5,0x1c,0x1c,0xe5,0x0d,
+ 0x02,0xe5,0x01,0x11,0x09,0x52,0x12,0x04,0x08,0x03,0x0b,0x03,0x07,0x0b,0x1c,0x1e,
+ 0x13,0xe5,0xe5,0x09,0x04,0xe7,0xe5,0x04,0x01,0x01,0x02,0x01,0xe5,0xe5,0x05,0x07,
+ 0x01,0x1a,0xe5,0xe5,0x08,0xe7,0x19,0x09,0x01,0x01,0x11,0xe5,0xe5,0x05,0x13,0x1d,
+ 0xe5,0x0c,0x05,0xe6,0x02,0xe5,0xe5,0x0e,0x01,0xe5,0x0e,0xe6,0x08,0x04,0xe5,0xe7,
+ 0x03,0x02,0xe5,0x05,0x01,0xe5,0x09,0x09,0x02,0x02,0x01,0xe6,0xe5,0x04,0xe6,0x08,
+ 0x01,0x07,0x02,0x04,0x01,0x07,0x01,0xe6,0xe5,0x06,0x07,0xe6,0x04,0x03,0x08,0xe5,
+ 0x04,0x03,0x08,0x03,0x05,0x06,0x03,0x02,0x05,0xe5,0x08,0x02,0x02,0x01,0xe5,0x05,
+ 0xe5,0x02,0x02,0xe5,0xe6,0x0d,0x01,0x0f,0x01,0x09,0x07,0x01,0x0e,0x08,0x03,0x01,
+ 0x04,0x04,0x03,0x03,0x01,0x13,0x08,0x02,0x01,0x01,0x0f,0x03,0xe5,0x03,0x0e,0x02,
+ 0x01,0x11,0x01,0x11,0x01,0x0a,0x06,0x01,0x0e,0x01,0x01,0x0f,0x05,0xe5,0x07,0xe6,
+ 0xe5,0x04,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,
+ 0x01,0xe5,0x01,0x01,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x01,0x01,0x05,
+ 0xe5,0x07,0xe5,0x01,0x05,0xe6,0x05,0xe5,0x06,0xe6,0xe5,0x04,0x01,0x07,0x01,0xe6,
+ 0xe5,0x02,0xe6,0x02,0x05,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x03,0x02,
+ 0xe7,0x08,0x05,0x0a,0xe5,0x10,0x11,0x01,0x07,0x01,0x09,0x09,0xe5,0x03,0x17,0x09,
+ 0x01,0x0a,0x08,0xe5,0x05,0x01,0x07,0x02,0xe5,0x02,0x03,0x05,0x01,0x01,0xe5,0x01,
+ 0x01,0x04,0x02,0xe6,0x02,0xe5,0x19,0x01,0xe6,0x05,0x05,0x02,0xe5,0x08,0x05,0x02,
+ 0x09,0x09,0x06,0x11,0x01,0x02,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0xe5,0x07,0x08,
+ 0x07,0x01,0x07,0x01,0x02,0x08,0x07,0xe6,0x04,0x04,0x03,0x02,0x02,0x03,0xe5,0x03,
+ 0x03,0xe5,0xe5,0x09,0x05,0xe5,0x01,0xe5,0x08,0x0a,0x04,0x01,0x07,0xe5,0x03,0x01,
+ 0xe5,0xe6,0x0d,0x1d,0x1b,0x01,0x09,0x09,0xe5,0x03,0x17,0x08,0xe5,0xe5,0x09,0x08,
+ 0x09,0x04,0x02,0x05,0xe6,0x02,0x03,0x01,0x01,0x01,0xe5,0x03,0x01,0x01,0x05,0x0d,
+ 0x11,0x09,0x07,0x01,0xe5,0x01,0x0c,0x1d,0x1b,0x01,0x09,0x09,0x03,0x10,0x06,0x0b,
+ 0x01,0x13,0x13,0xe5,0x01,0xe5,0x08,0x02,0x01,0xe5,0x05,0x01,0xe5,0x01,0x06,0x06,
+ 0x13,0x01,0xe5,0x0a,0x01,0x02,0xe5,0x2e,0x12,0x06,0x02,0x06,0x02,0x14,0x05,0x01,
+ 0xe6,0x10,0x02,0x09,0x10,0xe5,0xe5,0x03,0x01,0x02,0x06,0xe5,0xe5,0x13,0x05,0x02,
+ 0x06,0x02,0x10,0xe5,0xe5,0x06,0x05,0xe5,0xe6,0x0a,0x05,0x01,0x07,0x01,0x01,0x05,
+ 0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x01,0x03,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x05,0x03,0x01,0x02,0x04,0x01,0xe5,0x05,
+ 0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x03,0x03,0x01,
+ 0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0xe6,0x01,0x02,0x02,0xe5,0xe6,0x0f,0x01,
+ 0x02,0x03,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x0d,0x01,0x03,0xe5,0x03,0x09,0xe5,0x01,
+ 0x03,0x03,0xe5,0x09,0x01,0x02,0x04,0x10,0xe5,0xe6,0xe5,0x03,0x01,0xe5,0x01,0x05,
+ 0xe6,0xe5,0x0c,0xe5,0x01,0x06,0x05,0x04,0xe5,0x01,0x0c,0xe5,0x03,0xe6,0x01,0xe5,
+ 0x03,0xe5,0x0c,0x04,0x0c,0xe7,0x01,0x08,0xe5,0x07,0xe5,0x07,0x01,0x05,0x0a,0x14,
+ 0x07,0x09,0x03,0x04,0x0a,0x0f,0x08,0x02,0x03,0x03,0x01,0x04,0x01,0x08,0x1d,0x01,
+ 0xe5,0xe5,0x03,0x11,0x0b,0x08,0x0a,0x01,0x04,0xe5,0xe5,0xe5,0x01,0x01,0x06,0x06,
+ 0x05,0x09,0x08,0x01,0x17,0x01,0x0e,0x07,0x02,0xe5,0x20,0x04,0x01,0x01,0x01,0x03,
+ 0x01,0x01,0x04,0x11,0x09,0x09,0x19,0x13,0x0f,0x02,0x03,0xe7,0x09,0x0f,0x06,0x13,
+ 0x01,0x03,0x0a,0x01,0xe6,0x05,0x03,0x0e,0x02,0x01,0x06,0xe5,0xe5,0x01,0x07,0x01,
+ 0x06,0x01,0x09,0x04,0x05,0xe5,0x01,0x01,0xe8,0x07,0x07,0x01,0xe6,0xe5,0x02,0xe6,
+ 0x04,0x0b,0x01,0x07,0x01,0x11,0x01,0x01,0x06,0x02,0x03,0x02,0x02,0x08,0x13,0x03,
+ 0x12,0x01,0x16,0x09,0x07,0x07,0x07,0x01,0x03,0x02,0x0a,0x03,0x02,0xe5,0x17,0x08,
+ 0x07,0x03,0x03,0x04,0x10,0x01,0x01,0x09,0x05,0x09,0x01,0x02,0x07,0x05,0x01,0xe6,
+ 0x08,0x01,0x07,0x09,0x09,0x15,0x03,0x08,0xe5,0x06,0x01,0x02,0x07,0x01,0x02,0x01,
+ 0x01,0x05,0x02,0xe5,0x08,0x07,0x01,0x01,0x07,0x01,0x03,0x01,0x03,0x03,0x0e,0xe5,
+ 0x03,0x02,0x01,0x09,0x01,0x03,0x03,0x0e,0x02,0x05,0x05,0x03,0x05,0x03,0x0e,0x0c,
+ 0x0d,0x03,0x1b,0x0e,0x01,0x07,0xe5,0x07,0x03,0x05,0xe6,0x01,0x04,0x05,0x03,0xe7,
+ 0x07,0x05,0x03,0x02,0x05,0xe5,0x0b,0x05,0x0a,0x04,0x03,0xe5,0x01,0x06,0x04,0x01,
+ 0x05,0x10,0x02,0xe5,0x03,0xe5,0x09,0x06,0x01,0xe5,0x11,0x01,0x06,0xe5,0x24,0x05,
+ 0x0c,0x02,0x04,0x04,0xe5,0x08,0x03,0x07,0x0b,0x06,0x01,0xe6,0x01,0xe6,0x03,0x02,
+ 0xe5,0xe5,0x07,0x09,0x27,0x0a,0x03,0x0e,0x02,0x07,0x04,0xe5,0x07,0x02,0x0b,0xe6,
+ 0x06,0x01,0x07,0xe6,0x0a,0x06,0x03,0x1c,0x04,0x07,0x09,0x0b,0xe5,0x0a,0xe5,0x02,
+ 0x01,0x02,0xe5,0x04,0x02,0xe5,0xe5,0x01,0x03,0xe5,0xe7,0x02,0x01,0x06,0xe7,0x03,
+ 0x02,0xe6,0x03,0xe5,0x05,0x04,0xe7,0x06,0xe6,0x02,0x08,0x0c,0xe7,0xe5,0x0e,0x08,
+ 0x13,0xe5,0x11,0x29,0x18,0x05,0x04,0x03,0x02,0x03,0x01,0x01,0x03,0xe6,0xe5,0x04,
+ 0xe6,0xe5,0x03,0x03,0x04,0x05,0x07,0x02,0x13,0xe5,0xe6,0x03,0x1a,0xe6,0x01,0x36,
+ 0x03,0x03,0xe6,0x06,0x1d,0x06,0x02,0x03,0x05,0xe5,0x01,0x07,0x08,0x08,0x01,0xe5,
+ 0x09,0x02,0x08,0x05,0x08,0x03,0x08,0xe5,0x05,0x06,0x11,0xe5,0x11,0x02,0xe6,0x19,
+ 0x25,0x01,0x07,0x01,0x01,0x01,0x0a,0x0b,0xe5,0x04,0x03,0x02,0x04,0xe6,0xe6,0x07,
+ 0xe5,0xe5,0x10,0x1c,0xe5,0x07,0x03,0x07,0x04,0x03,0x1e,0x0b,0xe6,0xe6,0x3e,0xe5,
+ 0x07,0xe5,0x03,0x07,0x10,0x08,0xe5,0x16,0x16,0x09,0x0c,0x03,0x08,0x01,0x0f,0x2e,
+ 0x01,0xe8,0x07,0xe5,0x02,0x01,0xe5,0x0a,0x01,0x04,0x08,0xe5,0x15,0xe5,0x03,0xe6,
+ 0xe5,0xe6,0x04,0xe5,0x06,0x14,0xe5,0x04,0x0f,0xe5,0x04,0x02,0xe5,0x04,0x0a,0x01,
+ 0xe5,0x04,0x08,0xe6,0x03,0x02,0xe6,0x03,0xe5,0x01,0x0a,0x01,0x01,0x04,0xe5,0xe6,
+ 0x04,0x01,0xe5,0x05,0x0a,0xe6,0xe5,0xe5,0x01,0x01,0x05,0x01,0x04,0x05,0xe5,0x03,
+ 0xe5,0x05,0x08,0x10,0xe5,0x04,0xe5,0x06,0xe5,0x03,0x03,0xe5,0x15,0xe5,0x03,0xe5,
+ 0x0c,0x05,0x01,0x01,0x03,0x03,0x01,0x04,0x02,0xe5,0x0e,0x08,0x03,0xe5,0xe7,0x06,
+ 0xe5,0x01,0x05,0x04,0x01,0xe5,0x03,0x03,0x01,0x03,0x0a,0x07,0x01,0x02,0xe6,0xe5,
+ 0x03,0x14,0x21,0xe5,0x08,0xe5,0x04,0x05,0x1a,0xe5,0x02,0x03,0xe5,0x08,0xe5,0x02,
+ 0x06,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x02,0xe5,0x01,0x01,0x1b,0x01,0x01,0xe5,
+ 0x03,0x01,0x03,0xe5,0x03,0x16,0x10,0x04,0x02,0xe5,0x01,0x14,0x23,0xe5,0x08,0x09,
+ 0xe5,0x1a,0xe5,0x01,0x0f,0xe5,0x09,0xe5,0x07,0xe5,0x08,0x02,0x01,0x0d,0xe5,0x08,
+ 0x02,0x01,0x04,0xe5,0xe5,0xe5,0x02,0xe5,0x01,0x19,0xe5,0x03,0x0b,0x03,0x01,0xe5,
+ 0x11,0x06,0x02,0xe5,0x01,0x05,0x1a,0x04,0xe6,0x09,0x01,0x04,0x01,0xe5,0xe5,0x01,
+ 0x04,0x01,0x02,0x09,0xe5,0x01,0x02,0x10,0x01,0x04,0xe6,0x01,0x04,0xe5,0x01,0x06,
+ 0x04,0x01,0x02,0x0c,0x01,0x01,0x07,0x01,0x02,0x03,0x09,0x05,0x04,0x01,0x02,0x09,
+ 0x03,0x09,0xe6,0x01,0x14,0x03,0x01,0x02,0x1e,0x01,0x01,0x01,0x02,0x02,0x01,0x01,
+ 0x02,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0xe5,0x04,0x01,0x01,0x0a,0x01,0x01,0x04,0x06,
+ 0x04,0x04,0x04,0x09,0x02,0x01,0x04,0x05,0x01,0x01,0x09,0x02,0x01,0xe5,0x02,0x02,
+ 0x01,0xe5,0xe5,0xe5,0x02,0x01,0x03,0x02,0xe6,0x09,0x01,0x01,0x09,0x03,0xe5,0x03,
+ 0x02,0xe5,0xe7,0x12,0x01,0x02,0x04,0x06,0x1b,0x11,0x04,0x02,0x01,0x01,0x01,0x02,
+ 0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe5,0xe5,0x19,0xe6,0xe5,0x01,0x02,0x03,0x02,0x05,
+ 0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0x04,0x09,0x01,0x07,0x01,0x04,0x09,0x01,0x0a,
+ 0x01,0x01,0xe5,0x0b,0x07,0xe7,0xe5,0x10,0xe7,0x01,0x03,0xe5,0xe6,0x05,0x1a,0x11,
+ 0x09,0x01,0x02,0x01,0x02,0x01,0x04,0x01,0xe5,0xe5,0x11,0x07,0x07,0x01,0xe5,0x05,
+ 0x04,0x01,0x02,0x01,0x02,0x01,0x02,0x0e,0x01,0x07,0x01,0x01,0xe5,0xe8,0x0c,0xe5,
+ 0x03,0x01,0x02,0x08,0xe5,0x0a,0xe6,0xe5,0x0f,0x09,0x04,0x04,0x20,0x02,0x06,0xe5,
+ 0x07,0x02,0x03,0x04,0x1b,0x0b,0x01,0x03,0xe5,0x01,0x01,0x03,0xe5,0x01,0xe5,0x04,
+ 0x04,0x04,0x0c,0x02,0x06,0xe5,0x04,0x02,0xe5,0x0e,0x09,0x09,0x02,0x0a,0xe5,0x01,
+ 0x10,0xe5,0x07,0xe5,0x07,0xe5,0x1f,0x13,0x05,0xe5,0x21,0x0b,0x03,0xe5,0x01,0x01,
+ 0x03,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x0b,0x09,0x05,0xe5,0x01,0x09,0xe5,0x03,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x03,0x07,0x03,0xe5,0x0d,0xe5,0x07,0xe5,0x07,0xe6,0x06,
+ 0x09,0x09,0x03,0x02,0x02,0x06,0x02,0x02,0xe5,0x04,0xe6,0x06,0x02,0x01,0x01,0x02,
+ 0x06,0x02,0x06,0x01,0x02,0x09,0xe6,0xe5,0x01,0x02,0xe6,0x06,0xe7,0x05,0xe7,0x02,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x04,0x01,0x02,0xe5,0x04,
+ 0x02,0xe6,0x06,0xe5,0x0a,0xe5,0x02,0xe5,0x01,0x42,0x09,0x02,0x24,0x09,0x0e,0x06,
+ 0x1f,0xe5,0x05,0x0b,0xe5,0x05,0x02,0x09,0x08,0xe5,0x17,0x02,0xe5,0x01,0x11,0x09,
+ 0x35,0x34,0x06,0x05,0x09,0x19,0x13,0x05,0x03,0x08,0x06,0x02,0x10,0x10,0x01,0x0e,
+ 0xe6,0x06,0x01,0x07,0xe6,0x20,0xe5,0xe5,0x06,0x06,0x05,0xe6,0x05,0x07,0x01,0x06,
+ 0xe5,0xe5,0x08,0x01,0x0a,0x01,0x07,0xe6,0x06,0xe6,0x03,0x01,0xe7,0x02,0xe5,0xe5,
+ 0x08,0x07,0x01,0xe7,0x05,0x04,0x04,0xe7,0xe5,0x03,0xe7,0x06,0xe6,0x0a,0xe5,0x01,
+ 0x11,0x09,0x02,0x06,0x16,0x06,0x05,0x02,0x08,0x01,0x09,0x07,0xe6,0x06,0x01,0x05,
+ 0x01,0xe5,0x07,0x01,0xe5,0x02,0x06,0x02,0x06,0x09,0x05,0x01,0xe6,0x04,0x01,0xe5,
+ 0x05,0x02,0x06,0x01,0xe6,0x06,0xe6,0x04,0x02,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x04,
+ 0xe5,0x02,0x01,0xe6,0xe5,0x10,0x02,0x0f,0x02,0x19,0x07,0x01,0x07,0x01,0x10,0x02,
+ 0x07,0x01,0x03,0x03,0x01,0x03,0xe5,0xe5,0xe6,0xe5,0x13,0x03,0x05,0x06,0x01,0xe5,
+ 0x01,0x03,0x01,0x09,0x03,0xe5,0x03,0x01,0x07,0x09,0x09,0x07,0x01,0x06,0x0a,0xe5,
+ 0x12,0xe7,0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe6,
+ 0xe5,0x04,0xe5,0x02,0x02,0x01,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe6,0xe5,0x02,0x01,
+ 0xe5,0x01,0x01,0x05,0xe5,0x05,0x01,0xe5,0x05,0x01,0x08,0xe5,0xe5,0xe5,0x03,0xe5,
+ 0x02,0x03,0xe6,0x02,0x03,0xe8,0x06,0x03,0x05,0xe6,0x01,0x02,0xe8,0x01,0x02,0xe8,
+ 0xe6,0x03,0xe6,0x03,0x01,0xe8,0x19,0x27,0x06,0x01,0x07,0x01,0x0a,0x08,0xe6,0x06,
+ 0x09,0x09,0x01,0xe6,0x0c,0x09,0x09,0x08,0xe5,0xe5,0xe5,0x04,0x03,0xe5,0x02,0xe6,
+ 0x02,0x04,0x04,0xe5,0x06,0xe5,0x07,0xe5,0x08,0xe5,0x05,0x06,0xe7,0x11,0xe5,0x01,
+ 0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,0x17,0x01,0x04,0x01,0x07,0x01,0x02,0x09,0xe5,
+ 0x04,0x02,0x08,0x05,0x01,0x03,0x04,0xe5,0x0c,0x09,0x04,0x04,0x04,0x04,0x04,0xe5,
+ 0xe5,0x05,0xe5,0x01,0x09,0x01,0x03,0xe5,0x02,0x05,0x04,0xe5,0x01,0xe5,0x03,0xe5,
+ 0x01,0x05,0x04,0xe5,0x03,0xe9,0x13,0xe5,0x07,0xe5,0x07,0xe5,0x16,0x07,0x01,0x07,
+ 0x01,0x0a,0x04,0x03,0x09,0x07,0x01,0x05,0x03,0x01,0x0d,0x01,0x07,0x01,0x08,0xe5,
+ 0x08,0x01,0x01,0x03,0xe6,0x02,0x03,0x01,0x03,0x05,0x03,0x09,0xe5,0x02,0xe5,0x02,
+ 0xe5,0x02,0xe5,0x0a,0x06,0x01,0xe6,0x12,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x15,0xe5,0x05,0x01,0x07,0x01,0xe5,0x0b,0x01,0x03,0x11,0x01,0xe5,0x01,0x01,0x03,
+ 0x01,0xe5,0x0b,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0x03,0xe5,0x01,
+ 0xe5,0x01,0x05,0xe5,0x04,0x06,0x05,0x01,0xe6,0x04,0x01,0xe5,0x0e,0x04,0xe5,0x13,
+ 0x13,0x16,0x02,0x06,0xe5,0xe5,0x05,0x27,0xe5,0xe5,0x07,0x09,0xe5,0xe5,0x08,0x01,
+ 0x13,0x02,0x01,0xe5,0xe6,0x04,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x1b,0xe5,0x06,0x05,
+ 0xe5,0xe6,0xe6,0x06,0x06,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,
+ 0x05,0x01,0x04,0x01,0xe5,0xe5,0xe5,0x04,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0xe6,
+ 0x04,0x01,0x07,0x01,0x01,0x04,0xe5,0xe6,0x02,0xe5,0x01,0xe9,0xe5,0x02,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x04,0x02,0x01,0x01,0x02,
+ 0x02,0x01,0xe6,0xe5,0x02,0x01,0xe6,0x04,0x01,0x06,0xe5,0xe5,0xe5,0x04,0x01,0x04,
+ 0x02,0x02,0x03,0x0f,0xe5,0x01,0x08,0x02,0xe5,0x01,0xe5,0x19,0x05,0x04,0x09,0x06,
+ 0x03,0xe5,0x02,0xe5,0x0e,0x06,0x16,0x03,0x03,0x01,0xe5,0x11,0x0c,0x08,0x07,0xe5,
+ 0x0b,0x06,0x02,0x05,0x09,0xe5,0x0e,0x01,0xe5,0x06,0x03,0xe5,0xe5,0x05,0x0a,0x01,
+ 0x10,0x0d,0x05,0x15,0x18,0x09,0xe5,0x09,0x02,0x06,0x13,0x02,0x02,0x0c,0x0d,0xe5,
+ 0xe5,0x05,0x0a,0x07,0x05,0x04,0xe5,0xe5,0xe5,0x03,0x03,0x02,0x01,0x02,0x02,0x0f,
+ 0x35,0x06,0x02,0x08,0x02,0x0f,0x24,0x06,0xe5,0xe6,0x04,0x09,0x09,0x09,0x09,0x09,
+ 0x16,0x05,0x04,0xe5,0x0b,0x01,0x01,0x01,0x06,0xe6,0x18,0x09,0x14,0x03,0x01,0xe6,
+ 0x06,0x01,0x01,0x03,0x05,0xe5,0x0c,0x02,0x01,0xe5,0x01,0x01,0xe7,0x07,0x01,0xe5,
+ 0x02,0x04,0xe5,0x07,0x01,0x02,0x0c,0x01,0x02,0xe5,0x04,0xe5,0x09,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x02,0x05,0x0a,0x05,0xe7,0x0c,0x01,0xe6,0x0a,0x08,0x2e,0x03,0x0e,
+ 0x03,0x01,0x11,0x12,0x03,0xe5,0x01,0x0d,0x09,0x0e,0x01,0x03,0x03,0x04,0x17,0x02,
+ 0x0d,0x20,0xe5,0x0e,0x03,0x09,0x09,0x06,0x1a,0xe6,0x02,0x03,0xe6,0x08,0x08,0xe5,
+ 0x04,0x01,0x04,0x03,0xe5,0x08,0x01,0x05,0x03,0x02,0x06,0x0c,0x02,0x15,0x03,0x03,
+ 0x01,0x0d,0x0d,0x01,0x03,0x03,0x03,0x01,0x03,0x0a,0x01,0xe6,0x0c,0x03,0x01,0x2e,
+ 0x0d,0x02,0x09,0x02,0x06,0x10,0x0d,0x13,0x28,0xe5,0x0f,0x06,0x0e,0xe6,0x0c,0x0b,
+ 0x01,0xe5,0x02,0x18,0x02,0x24,0x0e,0x08,0xe5,0x01,0xe5,0x04,0x0d,0x1a,0x05,0x03,
+ 0x07,0x09,0x16,0x10,0x05,0x01,0x01,0x09,0x0f,0x0b,0x01,0x01,0x01,0x0e,0x12,0xe5,
+ 0x11,0x01,0x03,0x04,0x08,0xe6,0x02,0x12,0x01,0x08,0x02,0x03,0x07,0x08,0xe8,0x02,
+ 0x03,0x05,0xe5,0x02,0x0b,0x02,0xe5,0x0e,0x02,0x09,0x07,0x01,0x09,0x07,0x01,0x03,
+ 0xe6,0x02,0x06,0x0d,0xe8,0x02,0x0c,0x02,0x0d,0xe5,0x1c,0x0a,0x16,0x17,0x01,0x04,
+ 0xe5,0x01,0x04,0x04,0x01,0x0b,0x05,0x09,0xe5,0x08,0x19,0x02,0x05,0x03,0x0c,0x19,
+ 0xe6,0xe5,0x13,0x1d,0x09,0x04,0x04,0x02,0x01,0x09,0x0e,0x04,0xe5,0x02,0x15,0x04,
+ 0x03,0xe5,0x07,0x09,0x1b,0x01,0x07,0x01,0xe5,0x07,0xe5,0x01,0x01,0xe5,0x02,0x04,
+ 0xe5,0x0a,0x07,0x09,0x01,0x01,0xe5,0xe7,0x11,0x07,0x0d,0x16,0xe5,0x08,0x06,0x01,
+ 0xe5,0x01,0x01,0x0d,0x03,0x1a,0xe6,0x01,0x01,0x11,0x10,0xe6,0x02,0x05,0x0a,0x10,
+ 0xe5,0x07,0x01,0xe5,0x1d,0xe5,0xe7,0x04,0x0b,0x20,0x0d,0x09,0x09,0x02,0xe5,0x2c,
+ 0x05,0x24,0x27,0x06,0xe5,0xe5,0x05,0x0e,0x09,0x02,0xe5,0x01,0xe6,0x07,0xe5,0x04,
+ 0x05,0x04,0x01,0x01,0x04,0x26,0xe6,0xe5,0xe5,0x06,0xe5,0x01,0x02,0x01,0xe5,0x01,
+ 0x02,0xe5,0x09,0x01,0xe5,0x0b,0x04,0x09,0x09,0x02,0xe5,0x0a,0x03,0x05,0x17,0x32,
+ 0xe5,0xe6,0xe5,0x01,0x01,0x05,0x01,0x03,0x01,0xe6,0x01,0x04,0xe6,0x04,0x26,0xe5,
+ 0x02,0xe5,0x01,0xe5,0x02,0xe5,0x07,0xe5,0x06,0x04,0xe5,0x04,0x01,0x0c,0xe5,0x01,
+ 0x09,0x05,0xe5,0x07,0xe5,0x07,0x03,0x02,0x01,0xe5,0x05,0x01,0x06,0xe5,0x12,0x01,
+ 0xe6,0x1d,0x01,0x02,0x03,0x04,0x0d,0x04,0x04,0x1e,0xe5,0x01,0x01,0x04,0x01,0x05,
+ 0xe6,0x03,0x0b,0x02,0x01,0x04,0xe5,0xe6,0x18,0x13,0x01,0x07,0x07,0x09,0x17,0x01,
+ 0xe5,0x01,0x0b,0x0d,0xe5,0x04,0x08,0x05,0xe7,0x01,0x14,0x24,0x02,0x01,0x0d,0xe5,
+ 0x03,0x0e,0x04,0x04,0x18,0x13,0x09,0x09,0x09,0x19,0xe5,0x0b,0x14,0x01,0x0a,0x03,
+ 0x02,0x05,0x07,0x01,0x02,0x04,0x04,0x09,0x16,0x11,0x02,0x02,0xe5,0x04,0xe5,0xe5,
+ 0x01,0x02,0x04,0x04,0xe5,0x01,0x03,0x02,0x05,0x08,0x02,0x03,0x05,0x06,0x02,0x01,
+ 0x01,0x02,0x02,0x04,0x04,0x04,0x04,0x04,0x01,0x02,0x09,0x06,0x02,0x01,0x01,0x02,
+ 0x02,0xe5,0x01,0xe5,0xe5,0x01,0x04,0x04,0x01,0x01,0x07,0x01,0x01,0x02,0x0a,0x01,
+ 0x01,0x05,0x03,0x27,0x09,0x07,0x01,0x02,0xe7,0xe5,0xe5,0x04,0x02,0x02,0x01,0xe6,
+ 0x02,0x10,0xe5,0x02,0x01,0x01,0xe5,0x09,0x03,0x01,0x02,0xe5,0x02,0x02,0x01,0xe5,
+ 0x02,0x05,0x03,0x05,0x01,0x01,0x0f,0x03,0xe5,0x02,0xe5,0x02,0x01,0x02,0xe5,0xe5,
+ 0xe5,0x0b,0x01,0x04,0x04,0x01,0xe5,0x0b,0x01,0x02,0x01,0x01,0xe5,0x04,0xe5,0x05,
+ 0x19,0x01,0x1b,0x01,0x01,0x01,0xe5,0x03,0x04,0x01,0x07,0x01,0x0b,0x02,0x02,0x0a,
+ 0xe5,0x03,0x04,0x01,0x02,0x01,0x05,0x09,0x05,0xe5,0x01,0x01,0x01,0xe7,0x07,0xe5,
+ 0x03,0x05,0x03,0x04,0x01,0xe5,0xe5,0xe5,0x01,0x06,0x01,0xe5,0x07,0xe5,0xe5,0xe5,
+ 0x01,0x0a,0x01,0x01,0xe7,0x01,0x03,0xe5,0x08,0x18,0x01,0x13,0xe5,0x05,0x01,0x02,
+ 0x01,0x05,0x03,0x08,0xe5,0x05,0xe5,0x05,0x03,0xe5,0xe5,0x05,0xe5,0x03,0x03,0xe5,
+ 0xe5,0x01,0x04,0x01,0x02,0x03,0xe7,0x01,0x03,0xe5,0x03,0x01,0x02,0x08,0xe5,0xe5,
+ 0x01,0x01,0x07,0x03,0xe5,0xe5,0x01,0x01,0x02,0x01,0xe5,0x03,0x02,0xe5,0x09,0xe5,
+ 0xe5,0x01,0x0d,0x09,0x09,0x31,0x02,0x06,0x04,0x04,0x02,0x01,0x07,0x06,0x0b,0x04,
+ 0x04,0x09,0x04,0x04,0x04,0x04,0x09,0x09,0x02,0xe5,0x04,0x04,0x07,0xe5,0x04,0x04,
+ 0x04,0x02,0xe6,0x13,0x01,0x10,0xe5,0x07,0xe5,0x07,0xe5,0x29,0xe5,0x03,0x03,0x01,
+ 0x03,0xe5,0x07,0xe5,0x03,0x04,0x02,0x01,0x03,0xe5,0x01,0x03,0x03,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x0f,0xe5,
+ 0x07,0xe5,0x01,0x06,0x0d,0x02,0xe5,0x0d,0xe5,0x07,0xe5,0x07,0xe6,0x06,0x09,0x09,
+ 0x09,0x06,0x02,0xe5,0x01,0x05,0xe6,0x03,0x02,0xe5,0x02,0x01,0x02,0x05,0x03,0xe5,
+ 0x01,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe6,
+ 0xe5,0x04,0xe5,0x01,0x02,0x02,0x02,0x06,0xe5,0x07,0xe6,0x02,0x03,0x0d,0xe5,0xe7,
+ 0x01,0x45,0x06,0x02,0x12,0xe5,0x08,0x32,0x2f,0x02,0x2c,0x02,0xe5,0xe6,0x10,0x09,
+ 0x29,0x0b,0x13,0x05,0x03,0x05,0x09,0x0b,0x09,0x09,0x13,0x09,0x13,0x03,0x0f,0x20,
+ 0xe5,0xe6,0x0c,0x01,0xe7,0x06,0xe6,0x03,0x01,0xe5,0xe5,0x19,0x04,0x02,0x01,0x04,
+ 0x04,0xe6,0x04,0x01,0xe7,0x06,0xe5,0x0d,0xe5,0xe8,0x04,0x02,0xe7,0x03,0x01,0xe7,
+ 0x03,0x01,0xe7,0x05,0xe7,0x05,0xe7,0x06,0x01,0x04,0x01,0xe5,0xe5,0x03,0x01,0xe5,
+ 0xe5,0x02,0x02,0x09,0xe5,0xe5,0x02,0xe5,0xe8,0x14,0x01,0xe6,0x0c,0x01,0xe6,0x08,
+ 0x05,0x01,0xe6,0x1a,0xe5,0x05,0x01,0xe5,0x09,0x02,0x01,0xe5,0xe7,0x04,0x02,0xe5,
+ 0x01,0x06,0x05,0x01,0xe6,0x03,0x04,0xe6,0x04,0x01,0xe6,0x03,0xe5,0xe7,0x03,0xe5,
+ 0x01,0xe5,0x01,0x04,0xe6,0x08,0x05,0x01,0xe6,0x04,0x01,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x04,0x01,0xe6,0x07,0xe5,0xe5,0x02,0xe5,0x02,0x03,0x01,0xe5,0x0b,0x01,0x01,0x0e,
+ 0xe5,0xe5,0x02,0x16,0x02,0x07,0x01,0x06,0x0a,0x01,0x01,0x02,0x01,0x02,0x14,0x02,
+ 0x07,0xe5,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0xe5,0x07,0x09,0x01,0x18,0x0c,0x06,
+ 0x02,0x0a,0x02,0x16,0xe6,0x0c,0x01,0x03,0xe7,0x02,0x02,0xe8,0xe5,0x02,0xe7,0x07,
+ 0xe5,0x07,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x02,0x04,0xe6,0xe5,0x02,0x01,0xe5,0x02,
+ 0x04,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x01,0x03,0xe8,0xe5,0x02,0xe8,0xe5,0x02,0xe8,
+ 0x01,0x02,0xe7,0x01,0x03,0xe7,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0xe8,0xe5,0x04,
+ 0xe5,0x01,0x03,0xe7,0x05,0xe7,0x07,0xe7,0x02,0x02,0x01,0xe5,0x15,0x03,0x05,0x09,
+ 0x0d,0x08,0xe5,0x05,0x01,0xe5,0x12,0x06,0x02,0xe5,0x07,0xe5,0x04,0x01,0x0b,0xe6,
+ 0x01,0x05,0x09,0xe5,0x06,0xe5,0x02,0x04,0xe5,0x02,0x0c,0x01,0x07,0x01,0xe6,0x10,
+ 0x06,0xe5,0xe6,0x04,0xe5,0x01,0xe5,0x0b,0x03,0x11,0x01,0x01,0xe5,0x03,0x01,0x01,
+ 0xe5,0x03,0x01,0x01,0xe5,0x0c,0x08,0xe5,0x05,0x01,0x0b,0x09,0x01,0x01,0x05,0x09,
+ 0x05,0x01,0x01,0x03,0xe5,0x03,0x02,0xe5,0x01,0x03,0x01,0x03,0x05,0x03,0xe5,0x03,
+ 0x03,0x02,0xe5,0xe5,0x02,0x05,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x02,0x01,0x02,0xe5,
+ 0x01,0xe5,0x03,0x06,0x01,0x01,0x01,0xe6,0xe5,0xe5,0xe5,0xe6,0x01,0x02,0x04,0xe5,
+ 0x03,0xe6,0xe6,0x13,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x16,0x07,0x01,0xe5,0x12,0x04,
+ 0x0d,0x0f,0x05,0x05,0x07,0xe6,0x06,0xe6,0x02,0xe5,0x01,0x01,0x03,0x03,0x01,0x09,
+ 0x09,0x08,0xe5,0x0c,0x04,0xe5,0x03,0x03,0xe5,0xe5,0x08,0x0a,0x13,0x09,0x09,0x10,
+ 0x08,0xe5,0x05,0x01,0xe5,0x15,0x05,0x07,0x0f,0xe5,0xe5,0x03,0x03,0x01,0xe5,0x05,
+ 0x01,0xe5,0x06,0xe7,0x06,0xe5,0x01,0x04,0xe6,0x05,0xe7,0x05,0x01,0x07,0x01,0xe5,
+ 0x0b,0x03,0x09,0x05,0x08,0x03,0x01,0xe8,0x16,0x02,0x30,0xe5,0x03,0x01,0xe5,0xe5,
+ 0x0f,0x02,0x3e,0xe5,0x03,0x02,0x08,0xe5,0x19,0x02,0x1c,0xe5,0x0c,0x01,0xe6,0xe5,
+ 0x08,0x05,0x01,0x05,0x01,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,
+ 0x05,0xe6,0xe5,0x04,0x01,0x01,0x01,0x03,0x01,0x01,0x05,0x01,0x01,0x02,0x02,0x01,
+ 0x01,0x05,0x01,0xe6,0x04,0x01,0x02,0x06,0x01,0x01,0x05,0xe6,0x06,0x01,0x02,0x04,
+ 0x01,0x02,0xe5,0x02,0x01,0x07,0xe6,0x06,0x01,0x07,0x01,0x01,0x05,0xe6,0xe5,0x03,
+ 0xe7,0xe5,0x04,0x01,0x07,0x01,0x06,0x03,0xe6,0xe5,0x14,0x03,0xe5,0x07,0xe5,0x04,
+ 0x18,0x08,0x0d,0xe5,0x02,0xe5,0x05,0x05,0x1b,0xe5,0x07,0xe5,0xe5,0x09,0x05,0xe5,
+ 0x05,0x01,0xe5,0x01,0x05,0xe5,0x04,0x02,0xe5,0x04,0x02,0x07,0xe5,0x01,0x02,0x04,
+ 0x01,0x07,0x09,0x0b,0x02,0x02,0xe6,0x0a,0x04,0x04,0xe5,0xe5,0x04,0x02,0x1f,0x06,
+ 0x03,0x0b,0x02,0x01,0x07,0x0f,0xe6,0x07,0x01,0x03,0x01,0x02,0x01,0x02,0x03,0x04,
+ 0x06,0xe5,0x01,0x09,0x04,0xe5,0x03,0x09,0x03,0x06,0x0b,0xe5,0x02,0x02,0x01,0x04,
+ 0x0c,0x04,0x05,0x02,0x02,0xe6,0x08,0x18,0x16,0x03,0xe5,0x0c,0x0c,0x04,0x0b,0x03,
+ 0x01,0x09,0x08,0x06,0x08,0x02,0x10,0xe5,0x06,0x0a,0xe5,0x04,0x02,0x01,0x0a,0x19,
+ 0x03,0x0b,0x05,0x04,0xe7,0x07,0x01,0x02,0xe6,0x09,0x06,0xe6,0x1e,0x05,0x01,0x03,
+ 0x03,0xe6,0x06,0x01,0x02,0x07,0x06,0x01,0x04,0x05,0x07,0x09,0xe8,0x01,0x03,0x01,
+ 0xe5,0x08,0x0d,0x05,0x17,0x04,0x0b,0x0f,0x01,0x0e,0x02,0xe5,0xe5,0x0b,0x19,0x1e,
+ 0x01,0x02,0x06,0x19,0x03,0x01,0x05,0x0b,0x0c,0x08,0x02,0x19,0x06,0x1b,0x03,0x09,
+ 0x07,0x01,0x04,0x0b,0x05,0x10,0x09,0x05,0xe5,0x15,0x0b,0x06,0xe5,0x08,0x01,0x0a,
+ 0x1a,0xe5,0x04,0x03,0x09,0xe5,0x07,0x0c,0x05,0xe5,0x09,0x07,0xe5,0x0c,0x03,0x05,
+ 0x06,0xe5,0x0e,0x05,0x0b,0xe7,0x24,0xe6,0x0f,0x10,0xe5,0x14,0x13,0x04,0x0b,0x04,
+ 0xe5,0x01,0x0f,0x0e,0x01,0x02,0x53,0xe8,0x4a,0x36,0x02,0xe5,0x02,0x09,0x09,0x0d,
+ 0x02,0x0d,0x09,0x0b,0x01,0x05,0x0a,0x0a,0x07,0x08,0x04,0x01,0xe5,0x34,0xe6,0x02,
+ 0x13,0x03,0xe5,0x15,0xe5,0xe5,0x08,0x02,0xe5,0x06,0xe5,0xe6,0x06,0x08,0xe5,0x06,
+ 0x01,0x01,0x04,0x02,0x06,0x03,0xe5,0x06,0xe6,0x17,0xe5,0x01,0x01,0x01,0x01,0x06,
+ 0x06,0xe5,0x01,0x0c,0x01,0xe6,0xe5,0x35,0x0b,0x0c,0x01,0x01,0x16,0x0c,0x01,0xe5,
+ 0x02,0x06,0xe5,0x1e,0x0e,0xe6,0xe5,0x02,0x03,0x01,0x01,0x01,0xe5,0xe5,0x1a,0x0c,
+ 0x01,0x07,0x07,0x01,0xe5,0x01,0x08,0x35,0x04,0x02,0x01,0x0a,0x01,0x06,0x01,0x02,
+ 0x1c,0xe5,0x02,0x13,0x06,0x02,0x09,0xe5,0xe5,0x01,0xe5,0x04,0x09,0x13,0x09,0x0e,
+ 0x04,0x0e,0xe5,0x01,0xe6,0x08,0x19,0x1b,0x09,0x01,0x11,0x0b,0x0a,0x07,0x0d,0x02,
+ 0x18,0x08,0x04,0x02,0xe6,0x04,0x03,0x05,0x09,0x02,0xe5,0x06,0xe6,0x01,0x11,0x0c,
+ 0x04,0x06,0x0a,0x09,0x09,0x01,0x11,0x05,0xe5,0x03,0x02,0x02,0x11,0xe5,0x03,0x14,
+ 0x07,0x0f,0x05,0x09,0x0f,0x12,0xe5,0x13,0x0e,0x06,0x05,0x05,0x04,0x03,0x02,0x02,
+ 0xe6,0x11,0x01,0x0a,0x16,0x0d,0x01,0xe5,0x01,0xe6,0x03,0x02,0xe6,0xe5,0xe5,0x02,
+ 0xe5,0x01,0xe5,0x03,0xe5,0xe6,0x05,0x09,0x06,0x04,0x05,0xe5,0x01,0x05,0x03,0x05,
+ 0x09,0x03,0x16,0x01,0x11,0xe5,0x23,0xe6,0x02,0x02,0x01,0x1c,0x1d,0xe5,0x03,0xe5,
+ 0x01,0x01,0x01,0x02,0x01,0xe5,0x0f,0xe5,0xe6,0x01,0x06,0x08,0xe5,0xe5,0x07,0xe5,
+ 0xe5,0x05,0x03,0x05,0x03,0x05,0x0d,0x01,0xe5,0x12,0xe5,0x0a,0xe5,0x11,0xe5,0x13,
+ 0x01,0x04,0x01,0x04,0x1c,0x0f,0xe5,0x01,0x01,0x09,0x07,0x09,0x03,0xe5,0x07,0x07,
+ 0x03,0xe5,0x01,0x01,0x01,0x05,0x0d,0x04,0x01,0xe5,0x05,0xe5,0xe5,0x08,0x04,0x04,
+ 0x24,0x01,0x02,0x0a,0x03,0x01,0xe5,0xe5,0x09,0x08,0x05,0x01,0xe5,0x01,0x1e,0x10,
+ 0xe5,0xe5,0xe5,0x06,0x09,0x01,0x07,0x13,0x09,0x05,0xe5,0x01,0x0b,0x09,0x09,0x09,
+ 0x2e,0xe5,0xe5,0x09,0x05,0x0d,0x02,0x09,0x02,0x02,0xe5,0x20,0x1f,0x06,0xe5,0xe5,
+ 0x03,0x01,0xe5,0x14,0x06,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x01,0xe5,0x03,
+ 0xe5,0x01,0x05,0x09,0x04,0x04,0x04,0x01,0x02,0x09,0x04,0x01,0x02,0x09,0x04,0x01,
+ 0xe5,0xe5,0xe5,0xe5,0x02,0xe5,0x02,0x03,0x02,0xe5,0x01,0x03,0x0f,0xe6,0x01,0x1e,
+ 0x03,0x13,0x05,0x03,0x03,0xe6,0xe5,0xe5,0xe5,0x01,0xe5,0x02,0x0f,0x03,0x03,0xe5,
+ 0x04,0x03,0xe5,0x03,0x03,0x02,0x04,0x03,0x05,0x09,0x04,0x03,0x05,0x04,0x0e,0x01,
+ 0x01,0x0f,0x02,0x09,0x06,0x04,0x01,0x01,0x03,0x0a,0x02,0xe5,0xe7,0x1f,0x13,0x01,
+ 0x04,0x04,0x05,0x01,0x01,0x07,0x04,0x09,0x06,0x05,0x01,0x01,0x05,0x01,0x07,0x02,
+ 0xe5,0x06,0x01,0x01,0x07,0x01,0x07,0x06,0x01,0xe5,0xe5,0x0a,0x01,0xe5,0x01,0x01,
+ 0x01,0x01,0xe5,0x06,0xe6,0x01,0x01,0x0a,0x06,0x01,0x02,0x14,0xe5,0x02,0x02,0x1e,
+ 0x13,0x01,0x05,0x01,0x09,0x01,0x07,0x13,0x09,0x04,0x04,0x04,0x06,0x04,0x04,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x03,0xe5,0xe5,0x01,0x04,0x09,0x04,0x01,0x02,0x08,0xe5,
+ 0x03,0x01,0xe6,0x07,0x03,0x01,0x1c,0xe5,0xe5,0x01,0x2e,0x02,0x10,0x02,0x06,0xe5,
+ 0x1b,0xe5,0x07,0xe5,0x2e,0x02,0x01,0xe5,0x05,0x02,0x03,0x09,0x09,0x09,0x09,0x02,
+ 0x13,0xe5,0x0c,0x32,0xe5,0x39,0xe5,0x15,0x21,0xe5,0x01,0xe5,0x07,0x05,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x0b,0x09,0x01,0x0d,0xe5,0x01,0x09,0xe6,0xe6,0x0a,0x02,0x09,0x09,
+ 0x09,0x09,0x04,0x01,0x02,0x04,0x01,0x02,0x09,0x09,0x09,0x02,0x03,0x02,0x06,0x02,
+ 0x0b,0x09,0x06,0x02,0x09,0xe5,0x04,0x02,0x05,0x03,0xe6,0x06,0xe6,0x06,0xe5,0x02,
+ 0x01,0x02,0xe5,0x01,0x05,0xe5,0x03,0xe5,0x01,0x04,0x01,0x02,0x01,0x03,0x07,0x01,
+ 0x02,0x02,0x08,0xe5,0x30,0x09,0x24,0x02,0x08,0xe5,0x08,0x0b,0x06,0x02,0x12,0x28,
+ 0x12,0xe5,0x08,0x0e,0x03,0xe5,0xe5,0x09,0x31,0x0a,0x25,0x09,0x0a,0x0b,0x09,0x10,
+ 0x27,0x01,0x15,0x07,0x18,0x0f,0x1b,0x01,0x07,0x01,0x07,0x01,0x18,0x04,0x07,0x01,
+ 0x09,0x02,0x01,0x02,0x01,0x02,0x05,0x02,0x02,0x06,0x02,0x04,0x01,0x02,0x01,0x02,
+ 0x01,0xe5,0xe5,0x05,0x02,0x06,0xe7,0x05,0xe7,0x03,0x01,0xe7,0x06,0x06,0x01,0xe6,
+ 0x04,0x0c,0xe5,0x0b,0x01,0x01,0x0d,0x02,0x1a,0x01,0xe5,0x04,0xe5,0xe6,0x05,0x01,
+ 0xe5,0x08,0x12,0xe5,0x04,0xe5,0xe6,0x05,0x03,0x05,0x03,0x07,0x01,0x01,0x05,0x01,
+ 0x01,0x05,0x03,0x05,0x01,0xe6,0x06,0x01,0x07,0xe6,0x06,0xe6,0x03,0xe5,0xe7,0x08,
+ 0x04,0xe5,0x01,0x08,0x01,0x02,0x02,0x01,0x01,0x05,0xe5,0x02,0x03,0xe7,0x0d,0x04,
+ 0x15,0x07,0x02,0x01,0x03,0x03,0x01,0x0e,0x0e,0x0d,0xe5,0x01,0x01,0x03,0x03,0x01,
+ 0x03,0x07,0x03,0x05,0x03,0x03,0x01,0x03,0x0f,0x03,0x02,0x02,0xe5,0x04,0x02,0xe5,
+ 0x02,0x13,0x02,0x01,0xe5,0x02,0x02,0x05,0x05,0xe5,0x04,0x07,0xe5,0x01,0x0d,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0xe6,0xe5,0x04,0xe6,0xe5,
+ 0x04,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x02,0x04,
+ 0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe7,0x02,0x02,0xe7,0x0e,
+ 0x1b,0x01,0x0a,0x06,0x01,0x14,0x08,0xe5,0x05,0x01,0x09,0x09,0x1f,0x07,0x01,0xe5,
+ 0x07,0x09,0x09,0xe5,0x05,0x01,0xe5,0x0f,0x01,0x09,0x09,0x0e,0x01,0x01,0x0d,0x1d,
+ 0x01,0x0a,0x06,0x01,0x14,0x08,0x07,0x01,0x07,0x03,0x09,0x07,0x03,0x05,0x03,0x09,
+ 0x05,0x01,0xe5,0xe5,0x05,0x01,0x07,0x02,0x06,0x02,0x04,0x01,0x02,0x09,0x04,0x01,
+ 0x07,0x04,0x06,0x02,0x04,0xe5,0x03,0xe5,0xe8,0x07,0x02,0x02,0x31,0x07,0x15,0xe5,
+ 0x1b,0x1f,0x13,0x09,0x09,0xe5,0x08,0x08,0x07,0x01,0x09,0x09,0x07,0x09,0xe5,0x01,
+ 0x0a,0x0c,0x1d,0x06,0x01,0x0a,0x09,0x08,0xe5,0x08,0x1c,0x09,0x1d,0x0b,0x09,0x1b,
+ 0x01,0xe5,0x05,0x0b,0x0c,0x03,0x01,0x0b,0x15,0xe5,0xe5,0x0d,0x15,0x01,0xe5,0x05,
+ 0xe5,0xe5,0x1b,0xe5,0x05,0x02,0x08,0x09,0x01,0xe5,0x0f,0x01,0xe5,0xe5,0x03,0x01,
+ 0xe5,0x1e,0x04,0x02,0x10,0x02,0x04,0x08,0x03,0x07,0x01,0x11,0x01,0xe6,0x04,0x01,
+ 0xe5,0x02,0x02,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,
+ 0x04,0x02,0x01,0x01,0x05,0x01,0x01,0xe5,0x03,0xe6,0xe5,0x04,0x01,0x04,0x01,0xe5,
+ 0xe7,0x02,0x03,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x04,0x01,0xe5,0xe6,0xe5,0xe5,
+ 0x01,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0x03,0x02,0x01,0x07,0x01,0x03,0x03,
+ 0x01,0x07,0x01,0x02,0x07,0xe5,0x01,0x4a,0xe6,0x0b,0x05,0xe5,0xe5,0x05,0xe5,0x0b,
+ 0x03,0x05,0x0b,0x05,0xe5,0x01,0x05,0xe5,0x01,0x0f,0xe5,0x01,0x0b,0x03,0x09,0x07,
+ 0x13,0x03,0x08,0x0a,0x03,0x02,0xe5,0x0a,0x09,0x09,0x1d,0x08,0x01,0x03,0x04,0x09,
+ 0x04,0x06,0x0e,0x02,0x06,0x02,0x08,0x02,0xe5,0x01,0x02,0x03,0x05,0x07,0x01,0x03,
+ 0x05,0xe5,0x07,0x09,0x0c,0x09,0x09,0x06,0x02,0xe5,0x05,0x08,0xe5,0xe7,0xe5,0x01,
+ 0x03,0x01,0x08,0x37,0x03,0x07,0x05,0x01,0x01,0x06,0x01,0x01,0x0b,0x01,0x15,0x01,
+ 0x04,0x02,0x01,0x0c,0x06,0x13,0x09,0x05,0x06,0xe5,0x01,0x27,0xe7,0x0a,0x10,0x08,
+ 0xe5,0x06,0x08,0x07,0x01,0x07,0x02,0x0b,0x09,0x0a,0x03,0x01,0x05,0x01,0x01,0x02,
+ 0x09,0x02,0x03,0x01,0x01,0x05,0x01,0xe5,0x0c,0x01,0x04,0xe5,0x06,0x1a,0x01,0x07,
+ 0xe6,0x06,0xe5,0x01,0xe5,0x05,0x0e,0x03,0x35,0x09,0x02,0x09,0x03,0x01,0x09,0x07,
+ 0x07,0x06,0x09,0x07,0x08,0x09,0x04,0x18,0xe5,0x07,0x19,0x05,0xe5,0x06,0x11,0x0c,
+ 0x01,0x13,0x09,0x0f,0x02,0x06,0x01,0x02,0x04,0x09,0x01,0x1f,0x03,0x05,0x03,0xe6,
+ 0x02,0x03,0x03,0x03,0x09,0x03,0x04,0x0a,0x06,0x09,0x01,0x0a,0x05,0xe5,0x05,0x05,
+ 0x09,0x0d,0x03,0x0d,0x01,0xe5,0x08,0x1a,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x06,0x02,0x03,0x02,0x01,0x07,0x02,0x04,0x01,0x01,0xe5,0x08,0x03,0x01,0xe5,0xe6,
+ 0x01,0x01,0x02,0xe5,0x01,0x04,0x01,0x09,0x09,0x09,0x09,0x09,0xe6,0x36,0x01,0xe5,
+ 0x02,0x11,0x1c,0x11,0x10,0x0b,0x07,0x04,0x1a,0x02,0x04,0x03,0x04,0xe5,0x08,0x03,
+ 0xe5,0x03,0x04,0x04,0x03,0x05,0x0e,0xe5,0x0a,0x06,0x1b,0x05,0x01,0x0d,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x08,0x03,0x1f,0x0c,0x09,0x01,0x0a,0x0b,0x04,0x0a,0x15,0x04,
+ 0x0e,0x07,0x09,0xe6,0x12,0x04,0x03,0x0f,0x0a,0xe5,0xe6,0x02,0x06,0x02,0x01,0x07,
+ 0x01,0x07,0x01,0x08,0x0c,0x09,0x18,0xe5,0x19,0x07,0x04,0x20,0x13,0x0f,0x02,0xe5,
+ 0x14,0xe5,0x04,0x16,0x04,0x01,0xe5,0x16,0x01,0x07,0x01,0x02,0x06,0x06,0x02,0x06,
+ 0x02,0x09,0x13,0x06,0x0c,0x07,0x01,0x06,0x02,0x01,0x06,0x13,0x09,0x25,0x02,0x01,
+ 0x03,0xe5,0xe5,0x05,0x09,0x15,0x02,0xe5,0x06,0x10,0x09,0x07,0xe6,0x06,0xe6,0x06,
+ 0xe6,0x06,0xe6,0x05,0x02,0x02,0x06,0x02,0x06,0x02,0x03,0x02,0xe5,0xe5,0x01,0xe5,
+ 0x01,0xe5,0x03,0x05,0xe5,0xe5,0x01,0x01,0x01,0xe5,0xe5,0x01,0xe6,0xe8,0x01,0x01,
+ 0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x01,0xe6,0xe5,0x01,0x04,0x01,0x13,0x2b,0xe6,
+ 0x01,0x02,0x02,0x0d,0x04,0x09,0x21,0x08,0x07,0x02,0x04,0x01,0x09,0x01,0x05,0x01,
+ 0x08,0x09,0x02,0x0b,0x27,0x09,0x10,0x0e,0x0c,0x04,0x0c,0xe6,0xe7,0x06,0xe5,0x05,
+ 0x05,0x03,0x05,0x01,0x01,0x05,0x06,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,0x02,0x02,
+ 0x01,0xe5,0x02,0x02,0xe5,0xe5,0x02,0x05,0x01,0x01,0x05,0x03,0x05,0x01,0x01,0x02,
+ 0xe5,0xe5,0x02,0x02,0xe5,0x02,0x01,0x01,0x02,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x02,
+ 0xe5,0xe6,0xe5,0x02,0x05,0x03,0x01,0xe5,0x01,0x01,0x01,0x02,0xe5,0x04,0x05,0x01,
+ 0x01,0x06,0x08,0x20,0x01,0x03,0xe6,0x01,0x01,0x05,0xe5,0x03,0x03,0x01,0xe5,0x01,
+ 0x03,0x01,0xe5,0x01,0x08,0x04,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x01,0xe5,0x03,
+ 0x04,0xe5,0x02,0x01,0x07,0xe5,0x02,0xe5,0x02,0x09,0x01,0x02,0x01,0x02,0x04,0x01,
+ 0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0xe5,0x07,0x01,0x02,0x01,
+ 0x02,0x08,0xe5,0xe5,0x04,0x02,0x06,0xe5,0x04,0x01,0xe5,0x20,0x02,0x03,0x04,0x12,
+ 0x09,0x06,0x04,0x04,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x01,0xe5,0xe5,0x03,0x04,
+ 0x04,0x04,0x04,0x01,0xe5,0xe5,0x03,0x02,0x01,0x04,0x01,0xe5,0xe5,0x05,0x01,0xe5,
+ 0xe5,0x03,0x01,0x02,0x04,0x01,0x02,0x04,0x04,0x04,0x04,0x04,0x01,0x02,0x02,0x04,
+ 0x04,0x0b,0x07,0x06,0xe5,0xe5,0xe5,0x17,0xe8,0x01,0x14,0x09,0x06,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0xe5,0xe5,0x08,
+ 0x09,0x05,0xe5,0x01,0x01,0x12,0x02,0x01,0xe5,0x02,0x12,0x04,0x04,0x04,0x04,0x06,
+ 0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,
+ 0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,
+ 0x02,0x01,0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,
+ 0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0xe5,0x01,0xe5,0x03,0x09,0x06,0x04,
+ 0x01,0xe5,0x03,0x09,0x14,0x04,0x02,0x14,0x03,0x05,0x03,0x05,0x03,0x02,0x01,0xe5,
+ 0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,
+ 0x02,0x02,0x01,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0x01,
+ 0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x04,0xe5,
+ 0x02,0x01,0x02,0xe5,0x02,0x02,0x01,0xe5,0x02,0x0a,0x04,0x03,0x01,0x02,0xe5,0x02,
+ 0x09,0x13,0x01,0x01,0xe8,0x10,0xe6,0x01,0x04,0xe6,0x01,0x03,0xe7,0x01,0x03,0x02,
+ 0x02,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x09,0x03,0x05,0x03,0x05,0x0b,0x04,
+ 0x04,0x09,0x03,0x05,0x07,0x01,0x09,0x0b,0x02,0x01,0x02,0x01,0x09,0x07,0x03,0x01,
+ 0xe5,0x01,0x01,0x01,0xe5,0xe5,0xe5,0x0f,0xe6,0x01,0x11,0xe5,0xe5,0xe6,0x02,0xe5,
+ 0xe5,0xe6,0x03,0x01,0x01,0x02,0x02,0x01,0xe6,0x01,0x02,0x01,0x01,0x02,0x02,0x01,
+ 0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0x01,0x02,
+ 0x06,0x02,0xe6,0x03,0x01,0xe7,0x05,0x01,0xe7,0x03,0x01,0xe7,0x03,0x02,0xe6,0x03,
+ 0x01,0xe5,0x05,0x01,0xe7,0x03,0x01,0xe5,0x05,0x01,0xe5,0xe6,0xe5,0xe5,0x01,0x04,
+ 0x09,0x04,0x04,0x01,0x02,0x14,0xe7,0xe5,0x0f,0x09,0x09,0x06,0x02,0x02,0x03,0x02,
+ 0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x01,0x07,0xe5,0x0e,0x09,0x17,
+ 0x01,0xe6,0x0f,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x06,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x18,0xe5,0x07,0xe5,0x19,0xe5,0x08,
+ 0x01,0x02,0xe5,0x07,0xe5,0xe5,0x05,0xe6,0x01,0x01,0xe5,0xe8,0x01,0x01,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,
+ 0x01,0xe6,0x04,0x01,0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0xe5,0x04,0x02,0x09,0x09,0xe7,
+ 0x05,0xe6,0x06,0x0d,0xe5,0x02,0x02,0x09,0x1d,0xe5,0x08,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0xe5,0x08,0x2c,0x03,0x01,0xe5,
+ 0x08,0x07,0x09,0x0d,0x01,0x09,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,
+ 0x04,0x02,0x06,0x02,0x06,0x02,0xe5,0x05,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x02,0x08,0x31,0x03,
+ 0x0c,0x02,0xe7,0x05,0xe7,0x05,0xe7,0x05,0xe5,0xe5,0x03,0x02,0xe6,0x03,0x02,0xe6,
+ 0x02,0xe5,0x01,0x01,0x04,0x02,0xe6,0x03,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0xe6,
+ 0x03,0x02,0xe6,0x05,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x02,
+ 0xe5,0x01,0xe6,0x03,0x02,0x01,0x04,0x02,0xe6,0x05,0x02,0x06,0x0a,0xe6,0x06,0xe6,
+ 0x14,0x01,0xe6,0x0c,0x02,0xe5,0x06,0xe6,0x06,0xe6,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x01,0x02,
+ 0x02,0xe5,0x03,0xe5,0x01,0xe5,0x03,0xe5,0x01,0xe5,0x03,0x02,0x02,0xe5,0x03,0xe5,
+ 0x01,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,
+ 0x04,0x02,0xe5,0x04,0x03,0x05,0x01,0xe5,0x02,0x06,0x09,0x17,0x02,0xe5,0x08,0x04,
+ 0x01,0x07,0x01,0x07,0x10,0x02,0x09,0x09,0x09,0x09,0x06,0x02,0x09,0xe5,0x02,0x04,
+ 0xe5,0x06,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0x04,0x04,0xe5,0x07,0x04,0x04,
+ 0x09,0x03,0xe5,0x03,0x0a,0x02,0xe5,0x04,0x17,0x01,0x01,0x0d,0x05,0xe7,0x01,0x03,
+ 0xe7,0x01,0xe5,0x01,0xe7,0x05,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x01,
+ 0xe5,0xe5,0x01,0x03,0xe7,0x01,0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0x04,0xe6,0x01,
+ 0x03,0xe7,0x01,0x03,0xe7,0x03,0x03,0xe7,0x01,0x03,0x01,0xe5,0x01,0x04,0xe6,0x01,
+ 0xe5,0x01,0xe7,0x01,0x04,0xe6,0x01,0x03,0xe7,0x01,0xe5,0x03,0xe5,0x01,0x03,0x01,
+ 0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x07,0x01,0xe5,0x0e,0x06,0x02,
+ 0x06,0x02,0xe6,0x03,0xe5,0xe6,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x06,0xe5,0x07,0xe6,0x06,0xe6,0x08,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe6,
+ 0x06,0xe5,0x07,0xe6,0x06,0x07,0x01,0xe5,0x0e,0x03,0x05,0x0c,0x05,0xe7,0x0c,0x04,
+ 0xe5,0xe6,0x01,0x02,0xe5,0xe6,0x01,0x02,0xe5,0xe7,0xe6,0xe6,0x01,0x02,0x02,0xe5,
+ 0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x01,
+ 0xe6,0x01,0xe5,0xe5,0x02,0x02,0x02,0xe5,0x01,0x02,0x02,0x02,0xe5,0x03,0x02,0x01,
+ 0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x03,
+ 0x02,0xe5,0xe5,0xe5,0xe5,0x01,0x02,0x04,0x04,0x03,0xe5,0xe5,0x0b,0x02,0xe5,0x04,
+ 0xe5,0xe6,0x10,0x01,0xe6,0x0e,0x04,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0xe5,0x05,
+ 0xe7,0x05,0xe7,0x05,0xe7,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x04,0x01,0x01,0x06,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x04,0xe6,0x01,0xe5,0x04,0x01,0x01,0x07,0x01,0x07,0x01,0x02,
+ 0x02,0x01,0x01,0x06,0xe5,0xe5,0x04,0x01,0x01,0x07,0x03,0x03,0x01,0x01,0x01,0xe5,
+ 0x0d,0x04,0x03,0xe5,0x11,0xe5,0xe6,0x0c,0x05,0x05,0x03,0x05,0x03,0x05,0x03,0x03,
+ 0x05,0x03,0x05,0x03,0x05,0x01,0xe6,0x04,0x01,0xe6,0x04,0xe5,0xe6,0x04,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x02,0x02,0x05,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0x01,
+ 0xe6,0x04,0xe8,0x04,0x01,0x03,0x03,0xe8,0xe6,0x0b,0xe5,0x07,0x14,0xe8,0x18,0xe5,
+ 0x05,0xe5,0xe5,0xe5,0x01,0x3b,0x09,0x2f,0x23,0x09,0xe5,0xe5,0x0c,0x02,0x02,0x25,
+ 0x01,0x0f,0x01,0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x07,
+ 0x01,0x07,0x01,0xe5,0x05,0xe6,0x06,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x04,0xe5,0xe5,0xe5,0x04,0x01,0x02,0xe5,0x02,
+ 0x01,0x01,0x01,0x03,0x01,0x01,0x05,0x01,0xe6,0x02,0x01,0x01,0x07,0x01,0x01,0x05,
+ 0x01,0x0b,0x01,0xe5,0x01,0xe5,0x20,0x04,0x03,0x01,0x07,0x02,0x06,0x02,0x05,0xe5,
+ 0x01,0x06,0x02,0x05,0xe5,0x07,0xe5,0x01,0x06,0x0f,0x01,0x10,0x09,0x05,0xe5,0x01,
+ 0x01,0xe5,0x01,0x03,0xe5,0x03,0xe5,0x07,0x03,0x07,0x01,0x05,0x05,0x0d,0x15,0x04,
+ 0xe7,0x0a,0x09,0x04,0x04,0x0b,0x07,0x01,0x04,0x01,0xe5,0xe5,0x04,0xe5,0xe5,0xe6,
+ 0x03,0xe6,0x04,0x01,0xe5,0xe5,0x06,0xe5,0x09,0x07,0x0f,0x0f,0x09,0x01,0x11,0xe5,
+ 0x04,0x06,0xe5,0xe5,0x01,0x0e,0xe5,0x0c,0x1a,0xe5,0x02,0x0c,0x04,0x1f,0x0c,0x07,
+ 0x01,0x07,0x07,0x06,0x02,0x01,0x04,0x03,0x02,0x06,0x02,0x05,0x03,0x01,0x09,0x05,
+ 0x01,0x0e,0x02,0x06,0x02,0x03,0x01,0x02,0x01,0xe5,0x03,0x03,0x0e,0x14,0x1a,0xe6,
+ 0x08,0x08,0x22,0x06,0x02,0x09,0x09,0x07,0x01,0x01,0x07,0x09,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0xe5,0x11,0xe5,0xe5,0x07,0x1b,0x01,
+ 0x01,0x25,0xe5,0x02,0xe5,0x01,0x11,0x18,0x0c,0x0a,0x09,0x03,0xe5,0x03,0x09,0x02,
+ 0xe6,0x02,0x0d,0x09,0x03,0xe5,0x0a,0x01,0x0e,0xe5,0x07,0x09,0x0a,0x26,0x09,0x0f,
+ 0xe6,0x01,0x01,0x08,0x11,0x08,0x03,0x05,0x03,0xe6,0x02,0x03,0x04,0xe6,0x06,0xe5,
+ 0x02,0x04,0xe5,0x02,0x03,0x01,0x01,0x0a,0x06,0x0d,0x03,0x03,0x03,0x09,0x09,0xe5,
+ 0x07,0x04,0xe6,0x01,0x03,0x01,0xe5,0xe5,0x0f,0x06,0x24,0x09,0xe5,0x02,0x02,0x0e,
+ 0x0f,0x09,0x02,0x06,0x06,0x02,0x01,0x05,0x01,0x09,0x02,0x06,0x04,0x02,0x0b,0x15,
+ 0x0d,0x0f,0x09,0x09,0x05,0x03,0x04,0x04,0x2e,0x08,0xe6,0x01,0x03,0x27,0x02,0x01,
+ 0x02,0xe5,0x0d,0xe5,0x05,0x07,0x03,0x02,0x13,0x16,0x1a,0x04,0x03,0xe5,0x03,0x15,
+ 0x04,0x1b,0x1b,0x03,0xe5,0x01,0x13,0x0e,0x02,0x05,0xe5,0x01,0x05,0xe6,0x05,0x01,
+ 0x11,0xe6,0x06,0x04,0x01,0x02,0x09,0xe5,0x0f,0x02,0xe5,0x02,0x0b,0x05,0x07,0x03,
+ 0x03,0x01,0xe5,0x04,0x03,0x06,0x0c,0xe5,0xe5,0x02,0x0c,0xe5,0x04,0x01,0x0b,0x04,
+ 0x09,0x01,0xe5,0xe5,0x02,0x1f,0x07,0x02,0x04,0x04,0x02,0x04,0x12,0xe5,0x0e,0x0c,
+ 0x05,0xe5,0xe5,0x04,0xe5,0x02,0xe5,0x08,0x06,0x05,0x03,0x0d,0x09,0x0f,0x03,0xe5,
+ 0x0f,0x03,0x10,0x02,0x0a,0x03,0xe5,0x01,0x0b,0x06,0x10,0x02,0x0b,0x04,0x0d,0x06,
+ 0x06,0x01,0x02,0x01,0x01,0x02,0x03,0x02,0x02,0x03,0x05,0x15,0x0b,0xe5,0x01,0x08,
+ 0x01,0x02,0x06,0x03,0x03,0x04,0x0a,0x01,0x01,0x04,0x06,0x0b,0x07,0x0c,0x0e,0xe9,
+ 0xe5,0x1f,0x13,0x22,0x04,0x08,0xe5,0xe5,0x06,0x03,0x09,0x02,0x04,0x03,0x0c,0x04,
+ 0x01,0x04,0xe5,0x02,0x08,0xe5,0x04,0x02,0x10,0xe5,0x0d,0x16,0xe5,0xe5,0x0b,0x03,
+ 0x1b,0x08,0x13,0x21,0x05,0x07,0x0b,0x15,0x1c,0x0c,0x07,0x13,0x0c,0x12,0xe5,0x03,
+ 0x03,0x03,0x09,0xe8,0x20,0x01,0x01,0xe5,0x04,0xe5,0x08,0x01,0xe5,0x04,0xe5,0x01,
+ 0x01,0x03,0xe5,0x08,0x09,0xe5,0x06,0xe5,0x08,0x01,0xe5,0x01,0x02,0x03,0xe5,0x06,
+ 0x05,0x02,0xe5,0x01,0x01,0x04,0x0c,0xe5,0x03,0xe5,0x08,0xe5,0x06,0x0a,0x02,0xe5,
+ 0x02,0xe5,0xe5,0x06,0xe5,0x11,0xe6,0x08,0x04,0xe5,0x01,0x01,0x1d,0x02,0xe5,0x0e,
+ 0x02,0xe5,0xe5,0xe7,0x04,0xe5,0x0d,0x07,0x02,0x05,0xe5,0x01,0x06,0x02,0x02,0x01,
+ 0xe5,0x05,0xe5,0x03,0x05,0x01,0xe5,0x02,0x01,0xe5,0x01,0xe5,0xe5,0x05,0xe5,0x04,
+ 0xe5,0xe6,0x03,0xe5,0x02,0x02,0x10,0x02,0xe5,0xe6,0x0d,0x10,0xe5,0x01,0x07,0x01,
+ 0x02,0x02,0xe5,0x03,0x04,0xe5,0x01,0x01,0x13,0x03,0xe5,0x01,0x01,0x01,0x02,0xe5,
+ 0x02,0x09,0x01,0x01,0xe5,0x01,0x01,0x01,0x01,0xe5,0x01,0x02,0x03,0xe5,0x02,0x02,
+ 0x04,0x01,0x04,0x01,0x02,0x02,0x04,0x01,0x04,0x01,0x04,0x01,0xe5,0x03,0x01,0x09,
+ 0x04,0xe5,0x02,0x09,0x01,0x01,0xe5,0x03,0x04,0x01,0xe5,0xe5,0x03,0xe5,0x02,0x03,
+ 0xe5,0x01,0x01,0x1d,0x03,0xe5,0x03,0x05,0xe7,0x01,0x06,0xe5,0x01,0x01,0x0d,0xe5,
+ 0x07,0xe5,0x01,0x01,0x04,0xe5,0x0a,0x05,0xe5,0x01,0x01,0x07,0xe5,0x01,0x02,0x0c,
+ 0x01,0x11,0x01,0x04,0xe5,0x0c,0x01,0x07,0x05,0xe5,0x01,0x09,0x13,0x01,0x04,0x08,
+ 0xe5,0x01,0x01,0x1b,0x05,0xe5,0x05,0x02,0x02,0xe5,0x25,0x01,0x01,0xe5,0xe5,0x0b,
+ 0x01,0x01,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x08,0xe5,0xe5,0x01,0x06,0xe5,0x01,0x02,
+ 0x04,0x01,0x05,0xe5,0x01,0xe5,0x0f,0x01,0x01,0xe5,0x0a,0x02,0xe5,0x01,0x05,0x04,
+ 0x01,0x04,0x01,0x05,0xe5,0x01,0xe5,0xe5,0x04,0x06,0x01,0x01,0x20,0x04,0x01,0x06,
+ 0x01,0x01,0xe5,0x01,0x0e,0x13,0x04,0xe5,0xe5,0xe5,0x08,0x04,0xe5,0xe5,0xe5,0x01,
+ 0x01,0xe5,0xe5,0xe5,0x06,0x0b,0x05,0x03,0x02,0x01,0x04,0x02,0x01,0xe5,0x02,0x0b,
+ 0x04,0xe5,0x02,0x05,0x03,0x0a,0x01,0x01,0xe5,0xe5,0xe5,0x01,0x01,0x04,0x05,0x01,
+ 0x01,0x09,0x04,0x04,0x19,0x03,0x09,0x03,0xe5,0xe6,0x0b,0x01,0x13,0x02,0x01,0xe5,
+ 0xe5,0xe5,0x01,0x06,0x02,0x02,0x01,0x01,0x07,0x01,0x07,0x01,0x09,0x07,0x01,0x02,
+ 0x06,0x04,0x02,0x01,0x02,0xe6,0x05,0x02,0x02,0x01,0x01,0x09,0x01,0x01,0xe5,0x01,
+ 0x01,0x02,0x04,0x01,0x09,0x07,0x01,0x04,0x04,0x02,0x02,0x01,0x01,0x04,0x01,0x16,
+ 0x0d,0x01,0x01,0xe5,0x0c,0x01,0x13,0x01,0xe5,0xe8,0xe5,0x08,0x01,0xe5,0x03,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0xe5,0x05,0x01,0xe5,0xe5,0xe6,0xe5,0x03,0x01,0x02,0x01,
+ 0xe5,0xe6,0xe5,0xe5,0x0a,0x01,0xe5,0xe5,0xe6,0xe5,0x06,0x04,0x01,0x01,0xe5,0xe5,
+ 0x01,0x01,0x02,0x01,0x09,0x01,0xe5,0x03,0x01,0x03,0xe6,0x02,0x01,0xe7,0x01,0x01,
+ 0x04,0x16,0x0d,0x04,0x01,0x24,0x13,0x02,0x24,0x13,0x02,0x01,0xe5,0x0e,0x02,0x02,
+ 0x0d,0x0c,0xe6,0x06,0x02,0x03,0x02,0x09,0x02,0x03,0x02,0xe5,0x09,0x23,0x01,0x01,
+ 0xe7,0x23,0xe5,0x01,0x0f,0xe5,0x01,0x01,0x17,0xe5,0x01,0xe5,0x03,0xe5,0x11,0xe5,
+ 0x01,0x11,0xe5,0x01,0x0f,0xe5,0x15,0x05,0xe5,0x03,0x07,0x05,0xe5,0x33,0xe6,0xe6,
+ 0x08,0x01,0x02,0x09,0x06,0x02,0xe5,0x03,0x03,0x06,0x02,0xe5,0x03,0x03,0x06,0x02,
+ 0x09,0xe5,0x07,0xe5,0x07,0x09,0xe5,0x03,0x03,0x06,0x04,0xe5,0x02,0xe6,0x01,0x09,
+ 0xe6,0x06,0x09,0x05,0xe5,0x01,0xe5,0x07,0x05,0x03,0xe5,0x07,0x09,0x09,0x09,0x0d,
+ 0xe5,0xe5,0xe5,0x01,0x09,0x12,0xe5,0x08,0x08,0xe5,0x08,0x06,0x3d,0xe5,0x0a,0x13,
+ 0x12,0xe5,0x49,0x02,0xe5,0xe6,0x09,0x14,0x05,0x02,0x0a,0x05,0x02,0x24,0x13,0x0d,
+ 0x02,0x04,0x03,0x13,0x13,0x05,0x13,0x34,0xe8,0xe5,0x0c,0x14,0xe6,0x03,0x01,0x0a,
+ 0xe6,0x03,0x01,0x07,0x01,0x09,0xe7,0x06,0xe6,0x03,0x01,0x0a,0xe6,0x02,0xe5,0xe5,
+ 0x0b,0xe6,0x03,0x01,0x07,0x01,0xe7,0x05,0x02,0x03,0xe5,0xe5,0x09,0xe6,0x03,0x01,
+ 0x0a,0xe6,0x23,0x0e,0xe8,0x0c,0x02,0x13,0xe5,0x04,0x01,0xe5,0x04,0x03,0xe5,0x01,
+ 0x02,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe6,0xe6,0x04,0xe5,0x04,0x01,0xe5,0x02,0x05,
+ 0xe5,0x04,0x01,0xe5,0x0a,0xe5,0x04,0x01,0xe5,0x02,0x02,0x01,0xe6,0x01,0x04,0x01,
+ 0x05,0x01,0xe5,0x04,0x03,0xe5,0x01,0x02,0x01,0xe5,0x02,0x01,0x03,0xe5,0x24,0xe5,
+ 0x0c,0x02,0xe5,0x0e,0x0e,0x06,0x05,0x01,0x04,0x05,0x06,0x01,0x07,0x01,0x0b,0x08,
+ 0x06,0x01,0x0b,0x01,0xe5,0x01,0x01,0x04,0x03,0x03,0x06,0x01,0x07,0x01,0x04,0x04,
+ 0x07,0x01,0x04,0x0c,0x01,0x0a,0x16,0x0f,0x0e,0x02,0xe5,0x0c,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe6,0xe5,0x02,0xe7,0x05,0x01,0xe6,0xe5,0x02,0xe8,0xe5,0x02,0xe7,0x05,0x01,
+ 0xe5,0x07,0xe6,0xe5,0x02,0xe7,0x05,0x01,0xe6,0xe5,0x03,0xe6,0x09,0xe6,0xe5,0x02,
+ 0xe8,0xe6,0x01,0xe8,0x04,0xe8,0xe5,0x02,0xe7,0x02,0x04,0xe6,0xe5,0x02,0x01,0xe5,
+ 0x06,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x06,0x01,0x01,0x0f,0x13,
+ 0xe5,0x07,0xe5,0x01,0xe5,0xe5,0x01,0xe6,0x03,0x02,0xe5,0x01,0xe5,0xe5,0x01,0xe5,
+ 0x01,0xe5,0xe5,0x01,0x06,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe5,0x04,0x02,0x04,
+ 0x01,0x04,0xe6,0x03,0x02,0x04,0x01,0x03,0xe5,0x01,0x01,0x02,0x06,0xe5,0xe6,0x02,
+ 0x01,0x02,0xe5,0x04,0xe5,0xe6,0x01,0x05,0xe6,0x03,0x20,0xe5,0x0d,0x01,0xe5,0x0c,
+ 0x13,0x01,0xe5,0xe5,0x03,0x02,0x04,0xe6,0xe5,0x01,0x02,0xe6,0x01,0x04,0xe6,0x06,
+ 0xe5,0x01,0x02,0x02,0xe6,0xe5,0x01,0x03,0x02,0x03,0x01,0xe6,0xe6,0xe5,0x01,0xe6,
+ 0x07,0x02,0x01,0x02,0x02,0xe6,0x06,0xe5,0x04,0x02,0xe5,0x01,0x02,0x02,0xe6,0xe6,
+ 0x03,0xe6,0xe6,0xe5,0x01,0xe6,0xe5,0x04,0x01,0x01,0x02,0x02,0xe5,0x1f,0xe5,0x0c,
+ 0xe6,0xe5,0x0e,0x1d,0x05,0x07,0x01,0x03,0x05,0x03,0xe5,0x03,0x07,0x01,0x0d,0x04,
+ 0xe5,0x06,0x01,0x03,0x08,0x08,0x03,0x03,0x01,0x07,0x01,0x03,0x03,0xe6,0x06,0x01,
+ 0x09,0x04,0x04,0x08,0xe5,0x20,0x0e,0xe5,0x01,0x0d,0x13,0x09,0x02,0x03,0x02,0x05,
+ 0xe5,0x01,0x02,0x03,0x02,0x02,0x03,0x08,0xe5,0x01,0x06,0x04,0xe5,0x01,0xe5,0x01,
+ 0x05,0xe5,0x01,0x02,0x08,0x05,0xe5,0x01,0x02,0x0c,0xe5,0x01,0x05,0xe5,0x04,0x02,
+ 0x03,0x05,0xe5,0x04,0x06,0x05,0xe5,0x04,0x1c,0xe5,0x0c,0xe6,0xe5,0x1e,0x02,0x01,
+ 0x11,0x01,0x0a,0x11,0xe5,0x06,0x01,0x11,0x01,0x06,0x02,0x08,0xe5,0xe5,0xe5,0x03,
+ 0x0e,0x09,0x0e,0x02,0x10,0x03,0x13,0xe5,0x1f,0xe5,0xe5,0xe6,0x0d,0x01,0x01,0x05,
+ 0x01,0x07,0x01,0xe6,0x04,0xe8,0x04,0xe8,0x03,0xe7,0x06,0xe7,0xe5,0x03,0x01,0x01,
+ 0x05,0x01,0x02,0x04,0xe6,0xe5,0x04,0x01,0x01,0x05,0x01,0xe5,0xe5,0x01,0x03,0x01,
+ 0x02,0x01,0x01,0xe5,0xe5,0x06,0x01,0x07,0x01,0x01,0x05,0x01,0xe6,0x01,0x02,0x01,
+ 0x07,0x01,0x01,0x01,0x03,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,
+ 0x01,0x0b,0x01,0xe5,0x23,0x01,0x11,0x12,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0x09,
+ 0xe5,0x05,0xe5,0x08,0x0c,0xe5,0x01,0x0b,0x09,0x07,0x03,0x01,0xe5,0x04,0x02,0xe5,
+ 0x07,0xe5,0x01,0x07,0x14,0x08,0x0c,0x03,0xe5,0x07,0x02,0x09,0x09,0xe5,0x11,0xe5,
+ 0x07,0x09,0xe5,0xe5,0x01,0x05,0x08,0x01,0x03,0x01,0x05,0x05,0x01,0xe5,0x0b,0x01,
+ 0x0b,0x01,0x01,0x01,0x01,0x01,0x09,0x0a,0x09,0x02,0x07,0x01,0xe6,0x03,0x02,0x0d,
+ 0x02,0x09,0x09,0x04,0x04,0x04,0x01,0x01,0xe7,0xe6,0x2b,0x14,0x0d,0x02,0x0c,0x02,
+ 0x02,0x06,0x08,0x01,0x06,0x02,0x11,0x07,0x03,0x09,0x0b,0xe5,0x03,0x07,0xe5,0x02,
+ 0x01,0x3a,0x01,0x09,0x12,0x04,0xe6,0x01,0x04,0x01,0xe5,0x02,0xe5,0xe7,0x01,0x01,
+ 0x02,0x01,0xe5,0x05,0x01,0x02,0x01,0x07,0x01,0x02,0xe6,0x03,0xe5,0xe5,0xe6,0x05,
+ 0xe6,0x06,0x01,0x04,0x02,0x01,0xe7,0x04,0xe5,0xe5,0x09,0x05,0x0a,0x01,0x01,0x08,
+ 0x03,0x01,0x0a,0x01,0x06,0x21,0xe5,0xe5,0x08,0x01,0xe7,0x0a,0x05,0x0f,0x05,0x01,
+ 0x01,0x02,0x05,0xe5,0x06,0x04,0x05,0x02,0x05,0x06,0x03,0xe5,0x04,0x02,0xe5,0x01,
+ 0x06,0x07,0x01,0x02,0x06,0x02,0x08,0x02,0x0a,0x0c,0x01,0x02,0x05,0x12,0x04,0x03,
+ 0xe5,0x07,0x0b,0x09,0x06,0x0b,0xe5,0xe6,0x08,0x0f,0x01,0x02,0x04,0x0d,0x04,0xe5,
+ 0x02,0x03,0xe6,0x02,0xe5,0x01,0xe6,0x02,0x09,0x04,0xe5,0x0c,0x05,0xe5,0x07,0x03,
+ 0x03,0x03,0xe5,0x07,0xe5,0x0b,0x06,0x01,0x04,0xe6,0x01,0x07,0x0c,0x03,0xe6,0x08,
+ 0x0d,0x04,0xe5,0x0b,0x08,0x01,0xe5,0x01,0xe5,0xe5,0x06,0xe5,0x06,0x05,0x08,0x04,
+ 0x07,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x02,0x01,0x09,0x01,0x0a,0x13,
+ 0x07,0x0d,0x09,0x0c,0xe5,0x09,0x06,0x09,0x04,0x01,0x07,0x0c,0x04,0x01,0x09,0x10,
+ 0x01,0xe6,0x07,0x09,0x09,0x09,0x09,0x0b,0x09,0x0c,0x06,0x0b,0x07,0x05,0x09,0x06,
+ 0xe5,0x02,0x01,0x07,0x01,0x0b,0x1d,0x06,0xe5,0xe5,0x0a,0x05,0xe6,0x06,0x02,0x01,
+ 0x09,0x06,0x05,0x03,0xe6,0xe5,0x08,0x07,0x01,0x09,0x03,0xe6,0xe5,0x0f,0x07,0x06,
+ 0x02,0x05,0x04,0xe5,0x01,0xe5,0x02,0xe6,0x01,0x02,0x0b,0x04,0x01,0x02,0x09,0xe5,
+ 0x04,0x04,0x06,0x02,0xe5,0xe5,0x01,0xe5,0x01,0xe6,0x0d,0x16,0x05,0x04,0xe5,0x07,
+ 0xe5,0x04,0x0c,0xe5,0x0e,0xe8,0x02,0x10,0x0f,0x02,0x01,0xe5,0x07,0xe5,0x01,0x02,
+ 0xe5,0x13,0x02,0x02,0x06,0x02,0x02,0x1e,0x02,0x07,0xe5,0xe5,0x13,0x01,0x10,0x0f,
+ 0x09,0x07,0x08,0x11,0x02,0x09,0x03,0xe5,0xe6,0x16,0x01,0x04,0x04,0xe5,0x02,0x09,
+ 0x04,0x06,0x06,0x01,0x0f,0x04,0x02,0x0e,0x15,0x0e,0x04,0x01,0x09,0x06,0x02,0xe5,
+ 0xe5,0x03,0x04,0x04,0x09,0x02,0x01,0x03,0xe5,0x02,0xe5,0x03,0x03,0x07,0x02,0x02,
+ 0x03,0x02,0xe5,0x03,0x08,0x01,0xe7,0x02,0x03,0x0e,0x01,0x09,0x02,0x07,0x07,0x0d,
+ 0x07,0x02,0x02,0xe5,0xe6,0x03,0x03,0x02,0x03,0x0f,0x0b,0x09,0x06,0xe5,0x1c,0x08,
+ 0x06,0x06,0x0f,0x05,0x05,0x03,0x02,0x02,0x07,0x05,0x05,0x02,0x03,0x16,0x0d,0x15,
+ 0x12,0x09,0x05,0x01,0x2d,0x02,0xe6,0x0c,0x1b,0x1d,0xe6,0x17,0x01,0x07,0x07,0xe7,
+ 0x02,0x0c,0x0b,0x09,0x04,0x04,0x10,0xe5,0x06,0x0b,0x07,0x12,0x03,0xe5,0x03,0x0d,
+ 0x0b,0xe5,0x12,0x04,0x0c,0x01,0x0e,0x03,0xe5,0x05,0x09,0x16,0x0b,0xe6,0xe5,0x04,
+ 0x01,0xe5,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x04,
+ 0x02,0xe5,0x07,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x09,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x06,
+ 0x03,0x08,0xe5,0x07,0x0d,0x09,0x03,0xe6,0x07,0x01,0x03,0xe6,0x06,0x08,0x01,0x01,
+ 0xe5,0x0d,0x01,0xe5,0x12,0x08,0x09,0x1e,0x16,0xe5,0x05,0x08,0xe5,0x01,0xe5,0x0d,
+ 0x09,0xe5,0x0b,0x01,0x0a,0x02,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x08,0x0a,0xe5,0xe5,
+ 0xe6,0x01,0x01,0x04,0xe5,0x06,0x0a,0xe5,0x02,0x04,0xe5,0x0b,0x02,0x06,0x16,0x09,
+ 0x25,0x10,0xe5,0x01,0xe5,0x0a,0x02,0xe5,0x08,0xe5,0x05,0x04,0xe5,0x0e,0xe5,0x01,
+ 0x08,0x03,0x02,0x01,0xe7,0x03,0xe5,0x04,0x07,0x01,0x02,0x01,0xe6,0x03,0x05,0xe5,
+ 0xe5,0xe5,0xe5,0x0b,0xe5,0x02,0x01,0xe7,0x01,0x01,0x17,0xe5,0x01,0x06,0xe5,0xe5,
+ 0xe5,0x08,0x04,0xe5,0x02,0x33,0x01,0x05,0x01,0x04,0xe5,0x01,0x01,0x03,0xe5,0xe5,
+ 0xe5,0x08,0x01,0x07,0x04,0x01,0x02,0x07,0x01,0x07,0x01,0x01,0x02,0xe5,0x01,0x01,
+ 0x08,0x04,0x01,0xe6,0x01,0x0a,0x01,0x18,0x02,0x01,0x07,0x09,0x06,0x02,0x06,0xe5,
+ 0xe5,0xe5,0x02,0xe5,0x01,0x05,0xe5,0x01,0x33,0x06,0x02,0x01,0x04,0xe5,0x04,0x02,
+ 0x02,0x01,0x07,0x06,0x02,0x10,0x02,0x01,0x03,0xe5,0x01,0x01,0x04,0x10,0x03,0xe5,
+ 0xe5,0x16,0x01,0x0c,0x02,0x0d,0x02,0xe5,0x01,0xe5,0x03,0xe5,0xe6,0x01,0x02,0x06,
+ 0x02,0x01,0x01,0xe5,0xe5,0x01,0xe5,0x01,0x05,0x04,0x09,0x0d,0x09,0x06,0x02,0x02,
+ 0xe5,0xe6,0x11,0x0d,0x05,0xe6,0x04,0x02,0x05,0xe5,0xe7,0x08,0x07,0x05,0xe6,0x01,
+ 0x01,0x05,0xe8,0x01,0x0e,0x05,0x01,0x01,0x09,0x09,0x05,0x01,0x02,0x03,0xe5,0xe5,
+ 0x01,0x06,0x02,0x04,0x04,0x01,0x01,0xe5,0xe5,0x01,0x01,0x01,0x05,0x04,0x09,0x0a,
+ 0xe5,0x04,0x02,0xe5,0x05,0xe7,0x02,0x02,0x01,0x04,0x09,0x01,0x02,0x04,0x05,0x03,
+ 0x03,0xe5,0x01,0x0b,0x02,0x01,0xe5,0x02,0x05,0x01,0x01,0x02,0x01,0x04,0x09,0x02,
+ 0xe9,0x0b,0x01,0x03,0xe5,0x01,0x01,0x02,0x06,0x07,0x01,0x04,0x01,0x02,0x05,0x01,
+ 0x06,0x02,0x01,0x04,0x04,0x09,0x02,0x06,0x02,0x04,0x09,0x0d,0x09,0x09,0x01,0xe5,
+ 0xe5,0x01,0x01,0x08,0x08,0x01,0x09,0x05,0x01,0x01,0x09,0x04,0x02,0x01,0x07,0x01,
+ 0x08,0x0e,0x04,0x0d,0x01,0x04,0x01,0xe5,0xe5,0x03,0x01,0x02,0x01,0xe5,0x03,0x01,
+ 0x02,0x01,0x01,0xe5,0xe5,0x01,0x04,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x04,
+ 0x04,0x04,0x04,0x09,0x09,0x0a,0xe5,0x08,0x09,0x04,0x01,0xe5,0xe5,0xe5,0x10,0x01,
+ 0x04,0x01,0xe5,0x08,0x01,0x02,0x01,0x04,0x01,0xe5,0xe8,0xe5,0x06,0x01,0x0b,0xe5,
+ 0xe5,0xe5,0x06,0xe8,0x23,0x02,0x1d,0xe5,0x07,0x09,0x02,0x41,0x04,0x0d,0x03,0xe5,
+ 0x07,0x15,0x04,0x02,0xe5,0x07,0x09,0x02,0x02,0xe5,0x01,0xe5,0x0a,0x01,0x24,0xe5,
+ 0x03,0x04,0x02,0x1d,0x01,0x07,0x1a,0x09,0x0b,0x09,0x08,0xe5,0x15,0xe5,0x07,0x01,
+ 0x0e,0x08,0xe5,0x01,0x09,0xe6,0x06,0x05,0xe5,0x01,0x09,0xe6,0xe7,0x07,0x01,0x02,
+ 0x09,0x02,0x03,0x02,0xe5,0x04,0x02,0x05,0x03,0x06,0x02,0x06,0x02,0x03,0x05,0x04,
+ 0xe6,0x01,0x09,0x09,0x09,0x08,0x02,0x09,0x06,0x02,0xe6,0x06,0x06,0x02,0x04,0x01,
+ 0x02,0x05,0x03,0x04,0x01,0x02,0x09,0xe5,0xe6,0x01,0x02,0x04,0x01,0x02,0x03,0x02,
+ 0x02,0xe5,0x03,0xe5,0x05,0xe5,0xe5,0xe5,0x01,0x09,0x12,0xe5,0x07,0x0a,0x06,0x02,
+ 0x06,0x02,0x13,0x09,0x29,0x06,0x02,0x10,0x0c,0x13,0x09,0x06,0x0c,0x06,0x02,0x06,
+ 0x02,0x04,0x02,0xe5,0x01,0x0a,0x14,0x05,0x09,0x01,0x0a,0x08,0x15,0x08,0x21,0x07,
+ 0x0a,0x17,0x05,0x13,0x09,0x05,0x0d,0x07,0x05,0x01,0x02,0x09,0xe5,0x01,0x01,0x0a,
+ 0x02,0x09,0x06,0x03,0x01,0x06,0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x04,
+ 0x02,0x01,0x02,0x01,0x02,0x01,0x04,0x02,0x06,0x09,0x09,0x0b,0x09,0x09,0xe7,0x05,
+ 0x11,0x01,0x09,0x04,0x04,0x02,0x01,0x05,0xe6,0x03,0x01,0x07,0x01,0x0a,0xe6,0x0a,
+ 0xe6,0xe5,0x01,0x07,0x02,0x02,0x08,0xe5,0x08,0xe5,0x01,0x02,0x03,0x07,0x01,0x05,
+ 0x01,0x01,0x05,0x03,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x03,0x07,0x01,0x01,0x05,
+ 0x01,0x01,0x07,0x01,0x01,0x07,0x01,0x03,0x02,0xe5,0x06,0x01,0x09,0x05,0x01,0xe5,
+ 0x04,0xe5,0x01,0x06,0x01,0x01,0x01,0x06,0xe5,0x01,0x02,0x01,0xe5,0x04,0xe5,0xe6,
+ 0x09,0x05,0xe5,0x02,0x01,0xe8,0x0e,0x09,0x04,0x0e,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x05,0x03,0x05,0x09,0x09,0x03,0x05,0x04,0x03,0x02,0x03,0x05,0x03,0xe5,0x03,
+ 0xe5,0x07,0x11,0x01,0x06,0x02,0x09,0x03,0x09,0x05,0x07,0x01,0x03,0x14,0x02,0xe5,
+ 0x0c,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe6,0x04,0xe7,0x01,0x03,0xe8,0x04,0xe8,0x04,
+ 0xe7,0x01,0x03,0xe8,0xe5,0x02,0xe8,0x06,0xe5,0x01,0x03,0x01,0xe5,0x01,0x04,0xe6,
+ 0x03,0x04,0xe6,0x07,0xe6,0x04,0xe7,0x01,0x03,0xe7,0x05,0xe8,0xe5,0x02,0xe8,0x04,
+ 0x01,0xe6,0xe5,0x02,0xe7,0x02,0x04,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x02,0x04,0xe7,
+ 0x02,0x02,0x01,0xe5,0xe5,0x0c,0xe6,0x06,0x09,0xe5,0x05,0x01,0x09,0x11,0x01,0x07,
+ 0x3f,0x09,0xe6,0xe6,0x07,0x0d,0x01,0x09,0xe5,0x11,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x08,0x0d,0xe8,0x0c,0x0b,0x07,0x01,0xe5,0xe5,0x03,0x01,0x02,0xe5,0x01,0xe5,
+ 0x03,0xe5,0x01,0x05,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x02,
+ 0x02,0xe5,0x01,0x04,0x04,0x04,0x04,0x04,0x04,0x06,0x04,0x04,0x04,0xe5,0x03,0x03,
+ 0x04,0x04,0x04,0x04,0xe5,0xe5,0x02,0x02,0xe5,0x01,0x02,0x05,0x02,0xe5,0x01,0xe5,
+ 0xe6,0xe5,0x03,0x01,0xe5,0x07,0x0a,0xe5,0x0d,0x01,0x0f,0x09,0x18,0xe5,0x02,0x04,
+ 0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x07,0x01,0x08,0x03,0x07,
+ 0xe5,0x02,0x05,0x03,0x05,0x08,0xe5,0x06,0xe6,0xe5,0xe5,0x03,0xe5,0x02,0x05,0x08,
+ 0xe5,0x0c,0x07,0x01,0xe5,0x16,0x02,0xe5,0x0c,0x02,0x08,0x07,0x0f,0x01,0xe6,0x04,
+ 0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0xe7,0x05,0xe7,
+ 0x05,0xe7,0x06,0x01,0x08,0xe7,0x05,0xe8,0x05,0xe6,0x07,0xe5,0x05,0xe7,0x01,0xe5,
+ 0x01,0x01,0xe6,0x01,0x02,0x01,0x03,0x03,0x01,0xe6,0x08,0x02,0x06,0x01,0xe5,0x11,
+ 0x07,0xe5,0x1a,0x08,0x10,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x17,0x05,0xe5,0x03,
+ 0x04,0x04,0x03,0xe5,0x21,0x0b,0x02,0xe6,0x08,0x09,0x08,0xe5,0x03,0x04,0x04,0x09,
+ 0x02,0x06,0x02,0x01,0x06,0x05,0xe5,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x01,0x05,0x01,
+ 0xe6,0x03,0xe5,0xe7,0x04,0x01,0x02,0x01,0x01,0xe5,0xe7,0x04,0x01,0xe6,0x04,0x01,
+ 0xe5,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x09,0x01,0x01,0x05,0xe6,0x01,
+ 0x04,0xe8,0x03,0xe5,0xe6,0x03,0x01,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,
+ 0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,0xe6,0x01,0x02,0x01,0xe5,0x03,0x01,0x01,
+ 0x06,0x03,0x03,0x02,0xe5,0x03,0x18,0x01,0xe5,0x0d,0x02,0x04,0xe6,0xe5,0x09,0x0e,
+ 0x18,0x09,0x02,0x06,0x06,0x08,0x09,0x08,0x07,0xe5,0x2f,0xe5,0x01,0x03,0x01,0xe5,
+ 0x01,0x05,0xe5,0x08,0xe5,0x01,0x01,0x01,0xe5,0x03,0x06,0x09,0x09,0xe5,0x17,0x09,
+ 0x09,0x11,0x02,0x02,0x08,0x0a,0x15,0x05,0x07,0x10,0x01,0x05,0x04,0xe5,0xe5,0x01,
+ 0x06,0x01,0x07,0x07,0xe5,0xe5,0x02,0x07,0x01,0x07,0x02,0x04,0x08,0x01,0x01,0xe5,
+ 0xe5,0x0f,0x0d,0x02,0x01,0xe5,0x0c,0x04,0x1f,0x09,0xe5,0x06,0x0a,0x07,0xe5,0x18,
+ 0x0d,0x01,0x07,0x17,0x18,0x09,0x05,0x01,0x04,0x0b,0xe5,0x01,0x15,0x0d,0x04,0x02,
+ 0xe6,0x06,0xe6,0x06,0x01,0x02,0x01,0x02,0xe6,0x01,0x08,0x01,0xe5,0x01,0x01,0x05,
+ 0x01,0x03,0x04,0x02,0x05,0x0c,0xe5,0xe5,0x04,0x08,0x06,0x04,0xe5,0x0a,0x02,0x02,
+ 0x03,0x04,0x13,0xe5,0xe5,0x04,0x19,0x0d,0xe9,0x07,0x18,0x05,0x0b,0x09,0x03,0x10,
+ 0x08,0x01,0x01,0x04,0x05,0x0d,0x09,0x01,0xe5,0xe5,0xe5,0x1c,0x03,0x07,0x02,0x02,
+ 0x10,0x01,0x0c,0x05,0x1d,0x05,0x02,0xe5,0xe6,0x08,0x05,0x08,0xe6,0x07,0x07,0xe6,
+ 0x06,0x01,0x07,0x05,0x03,0x05,0x05,0x03,0x05,0xe5,0x06,0xe5,0x06,0x01,0x09,0xe5,
+ 0x05,0x03,0x02,0x05,0xe5,0x02,0x05,0x03,0x01,0x0b,0x0c,0x0c,0x12,0x07,0x04,0x05,
+ 0x01,0x01,0x01,0x04,0x0a,0xe6,0xe6,0x0c,0xe5,0x02,0x04,0x09,0x03,0x05,0x04,0x04,
+ 0x02,0x04,0x0e,0x02,0x03,0x07,0x01,0xe5,0x07,0x07,0x02,0x03,0x04,0x06,0x05,0x08,
+ 0x11,0x01,0x12,0xe5,0x08,0x05,0x03,0x02,0x05,0xe5,0x08,0x03,0x05,0x02,0x06,0x06,
+ 0x07,0x02,0xe7,0xe6,0x06,0x02,0x06,0x02,0x05,0x0d,0x10,0x06,0x01,0xe5,0x0a,0x02,
+ 0xe5,0x01,0x03,0x08,0xe5,0x0e,0xe6,0xe5,0x01,0x01,0x04,0x05,0xe5,0x03,0x03,0x04,
+ 0x03,0x01,0x02,0x03,0x04,0x0c,0x09,0x03,0x05,0x09,0x09,0x04,0x04,0x09,0x04,0xe5,
+ 0x09,0x01,0xe6,0x07,0xe5,0x02,0xe5,0x0d,0x03,0xe5,0x05,0x0c,0x01,0x02,0x15,0x02,
+ 0x06,0x07,0x0a,0x01,0x01,0x09,0x07,0xe5,0xe5,0x05,0x01,0xe7,0x01,0x01,0x02,0x03,
+ 0x01,0x04,0x01,0x06,0xe6,0x04,0xe7,0x03,0x01,0xe8,0x04,0xe5,0x08,0xe6,0x03,0xe5,
+ 0xe6,0x07,0xe6,0xe5,0x01,0x0a,0x0a,0xe7,0x0f,0x0a,0xe5,0x03,0x01,0x12,0x10,0xe5,
+ 0x0c,0x1b,0x07,0x01,0x08,0x01,0x0b,0x07,0x0b,0x05,0x02,0x03,0x06,0x0a,0xe5,0x01,
+ 0x0e,0x07,0x03,0x05,0x02,0x13,0x03,0xe6,0xe5,0xe5,0xe5,0x09,0xe5,0x04,0x08,0x04,
+ 0x03,0x08,0x01,0x01,0x02,0x04,0x01,0x07,0x04,0x09,0x09,0x04,0x0b,0x02,0x01,0x0e,
+ 0x04,0x09,0x09,0x01,0x04,0x08,0x03,0x06,0x01,0xe5,0x02,0x03,0x01,0x03,0x05,0x03,
+ 0xe5,0x02,0xe5,0x02,0x05,0x03,0xe5,0x03,0x06,0x02,0x0e,0x02,0xe6,0x0c,0x14,0x0b,
+ 0x03,0x03,0x13,0x05,0x03,0x06,0x02,0x0a,0x04,0x02,0xe5,0x01,0x02,0x06,0x08,0x01,
+ 0xe6,0x04,0xe5,0x03,0xe5,0x15,0x03,0x04,0xe5,0x01,0x09,0x09,0x08,0xe5,0xe5,0x06,
+ 0x01,0x05,0xe6,0x07,0x0e,0x01,0x1e,0x05,0x01,0x11,0xe5,0x0e,0x01,0x07,0x01,0x01,
+ 0x05,0xe5,0x0e,0x04,0x01,0x11,0x01,0x07,0xe5,0x04,0x02,0x05,0x0d,0x01,0x09,0x04,
+ 0x09,0x02,0x03,0xe5,0x03,0x09,0x09,0x09,0x03,0x0c,0xea,0x0d,0xe6,0x03,0x02,0x0a,
+ 0xe5,0x03,0x01,0x09,0x02,0x06,0x09,0x07,0x06,0xe5,0xe5,0x01,0xe5,0x01,0x01,0xe5,
+ 0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,0x08,0x01,0xe6,0x04,0x02,0x03,0xe5,0xe5,0x01,
+ 0xe5,0x01,0xe5,0x03,0xe5,0x01,0x01,0xe5,0xe5,0x03,0x01,0x04,0x08,0xe5,0x07,0xe5,
+ 0x01,0xe5,0x02,0x01,0x01,0xe5,0x04,0xe5,0x01,0xe5,0x19,0x01,0xe5,0xe6,0x01,0x01,
+ 0x0b,0x01,0x04,0x05,0xe5,0x02,0x08,0x0a,0x08,0x09,0x10,0x01,0x07,0xe5,0x04,0x08,
+ 0x11,0x03,0x0d,0xe5,0x03,0x03,0xe5,0x05,0xe6,0x01,0x06,0xe5,0x03,0x0a,0x09,0x02,
+ 0x01,0x03,0x0b,0x01,0x01,0x07,0x01,0x0c,0x01,0x02,0x01,0xe6,0x03,0x12,0x05,0xe5,
+ 0x03,0x01,0x05,0x0b,0x18,0x09,0x06,0xe5,0xe5,0x08,0x07,0x01,0x09,0x0b,0x07,0x01,
+ 0x10,0x05,0x06,0x01,0x01,0x01,0x03,0xe5,0x01,0x05,0x01,0x01,0x01,0x02,0xe5,0x02,
+ 0x01,0x03,0xe5,0x01,0x01,0xe5,0x05,0x01,0x03,0x01,0x01,0x01,0x02,0xe5,0x03,0x05,
+ 0x01,0xe5,0x01,0x14,0x06,0xe5,0x0a,0x13,0x09,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x02,0x06,0x01,0xe5,0x05,0x01,
+ 0xe5,0x12,0x0d,0x02,0x10,0x01,0xe5,0x05,0x02,0x09,0xe5,0x04,0x0c,0x06,0x02,0x02,
+ 0xe5,0x0c,0x01,0x07,0x01,0x0c,0xe5,0x01,0xe5,0xe5,0x0b,0xe5,0x01,0x06,0x02,0x06,
+ 0x02,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x05,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x03,0x01,
+ 0xe5,0xe5,0x02,0x02,0x02,0x01,0x04,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x02,0x02,
+ 0xe5,0xe5,0x06,0x04,0x09,0x01,0xe6,0x06,0x01,0x0f,0xe5,0xe6,0x03,0x01,0x02,0x05,
+ 0xe5,0x01,0x04,0x01,0x01,0xe5,0x05,0xe5,0x01,0xe5,0x01,0x0a,0x01,0x01,0x05,0x01,
+ 0x01,0x09,0x05,0x01,0x01,0x09,0x05,0x09,0x06,0x01,0x02,0x01,0x04,0x02,0x01,0x02,
+ 0xe6,0x01,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x06,0x02,0x01,0x01,0x02,0x02,0x01,
+ 0x01,0x02,0x02,0x01,0x04,0xe5,0xe5,0xe5,0x04,0x03,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x03,0xe5,0xe6,0x0b,0x01,0x07,0x01,0x04,0x01,0x02,0x07,0x01,0x09,0x03,
+ 0xe5,0x10,0x06,0x05,0x03,0x09,0x09,0x02,0x06,0x03,0xe5,0x02,0x02,0x04,0x01,0x02,
+ 0x09,0x05,0x01,0x01,0x07,0x05,0xe5,0x02,0x02,0x02,0x03,0x03,0x01,0x03,0x05,0x01,
+ 0x01,0x02,0xe5,0xe5,0xe5,0xe5,0x02,0x05,0x02,0x01,0xe5,0x02,0x0e,0x01,0x02,0x02,
+ 0x0a,0x01,0x07,0x01,0x04,0x04,0x01,0xe7,0x01,0x01,0x09,0x01,0xe5,0x03,0x09,0x09,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x03,0xe5,0x01,0x01,0x04,
+ 0x01,0xe5,0xe5,0x06,0x01,0x07,0x03,0xe5,0x08,0x02,0x09,0x08,0x07,0x01,0x09,0x07,
+ 0x0a,0xe5,0x05,0xe5,0xe5,0x02,0x02,0x1a,0x01,0xe5,0x02,0x0c,0x02,0x03,0x02,0x02,
+ 0x06,0xe5,0x0b,0x09,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x05,0x05,0x03,0x05,0x03,
+ 0x05,0x09,0x06,0x08,0xe5,0x01,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe6,0x02,0xe5,0x01,
+ 0xe6,0x02,0x05,0x03,0xe5,0x07,0x03,0xe5,0x07,0x02,0xe6,0x1d,0x05,0xe5,0x0b,0xe5,
+ 0x03,0xe5,0x01,0x06,0x02,0xe5,0x04,0x02,0x12,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x02,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x03,0xe5,0x01,0xe5,0x07,0xe5,0x03,0xe5,0x01,0xe5,0x07,
+ 0x0a,0xe5,0xe6,0x0d,0x09,0x02,0x02,0x03,0xe5,0x07,0x06,0x02,0xe5,0x01,0x05,0x09,
+ 0x03,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0x02,0x01,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0x08,0x09,0xe5,0x01,0x02,0x02,
+ 0xe6,0x03,0x02,0x06,0x02,0x06,0x02,0xe6,0x03,0x02,0x06,0x02,0xe6,0x03,0x02,0x05,
+ 0xe5,0x05,0xe5,0xe5,0xe5,0x01,0x27,0x08,0xe5,0x1b,0xe6,0x06,0xe6,0x07,0xe5,0x04,
+ 0x02,0xe5,0x04,0x02,0xe5,0x04,0x05,0x05,0x03,0x05,0x03,0x19,0x02,0x06,0x09,0x09,
+ 0x0b,0x09,0x07,0x02,0x06,0x07,0x02,0x01,0x01,0x25,0x01,0x0b,0x05,0x17,0x09,0x04,
+ 0x03,0x05,0x03,0x05,0x02,0x06,0x0b,0x09,0x09,0x14,0x02,0x04,0x09,0x09,0x09,0x09,
+ 0x09,0x03,0x05,0x0e,0x02,0xe5,0xe5,0x09,0x02,0x07,0x01,0x0a,0xe6,0x03,0x01,0x0a,
+ 0xe6,0x03,0x01,0x09,0x0e,0x04,0x09,0x09,0x06,0x02,0x06,0x01,0x02,0x09,0x06,0x02,
+ 0x07,0x01,0x07,0x01,0xe7,0x06,0xe6,0x1a,0xe6,0x10,0xe6,0x14,0xe5,0x01,0x0f,0xe5,
+ 0x02,0x02,0x01,0xe5,0x02,0x01,0x03,0xe5,0x04,0x01,0xe5,0x08,0xe5,0x04,0x01,0x01,
+ 0x01,0x05,0x01,0x01,0x05,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x04,0xe5,0xe6,0x05,
+ 0x01,0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x02,0x01,
+ 0xe5,0xe7,0x08,0x09,0x09,0x02,0x06,0x09,0x02,0x06,0x09,0x0c,0xe5,0x01,0x0f,0x07,
+ 0x01,0x0a,0x08,0x04,0x01,0x03,0x57,0x1e,0x01,0xe5,0x02,0x06,0x01,0x1b,0x02,0x0f,
+ 0x02,0x15,0x01,0xe5,0x0e,0x05,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0xe5,0x01,0x04,0xe6,0x01,0x03,0x01,0xe5,0x01,0x03,0xe7,0x05,
+ 0xe8,0xe5,0x02,0xe7,0x05,0xe7,0x05,0x01,0xe5,0x06,0xe6,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x08,0x01,0x0f,0x07,0x01,0xe5,0x07,0xe6,0x04,0x01,0x09,0xe5,0x11,
+ 0x09,0xe5,0x08,0x04,0x0e,0x09,0x05,0x05,0xe5,0x03,0x03,0x05,0x09,0xe5,0xe6,0x04,
+ 0xe5,0xe5,0x03,0x01,0x07,0x01,0x03,0xe5,0xe5,0x05,0xe5,0x01,0x01,0x0d,0x19,0x08,
+ 0x01,0xe5,0x0e,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x0a,0x06,0x02,
+ 0x04,0x01,0xe5,0x07,0x09,0x09,0x09,0xe5,0x04,0x04,0x04,0xe6,0x01,0xe5,0x01,0x01,
+ 0xe5,0x01,0x04,0xe7,0xe6,0x01,0x01,0xe6,0xe5,0xe5,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0x06,0x02,0xe5,0x04,0x07,0x01,0x09,0x09,0x0e,0xe5,0x0e,0x0a,0x12,0x0a,0x1c,
+ 0x09,0xe5,0x01,0x01,0x03,0x09,0xe5,0x07,0x08,0x02,0x05,0x03,0x05,0x03,0x03,0x01,
+ 0x08,0xe5,0x02,0x03,0x01,0x07,0x01,0x09,0x09,0x31,0x02,0x0f,0x0a,0x06,0x09,0x09,
+ 0x1d,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,
+ 0x01,0xe5,0x02,0x02,0x01,0xe5,0x01,0x03,0x01,0xe5,0x02,0x05,0x02,0x03,0x01,0x03,
+ 0x09,0x24,0x17,0x09,0xe8,0x02,0x13,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x13,0x05,0x02,0x06,0xe5,0xe5,0x05,0x0b,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe6,0x08,0x05,0x01,0xe5,0x05,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0x04,0x08,0xe8,0xe5,
+ 0x0e,0x01,0x03,0x03,0x01,0x02,0xe5,0x02,0x01,0x01,0x01,0x03,0xe6,0xe5,0xe5,0x02,
+ 0x01,0x03,0x03,0x01,0x02,0xe5,0x02,0x01,0x07,0x01,0x07,0xe7,0x05,0x01,0x01,0x01,
+ 0x03,0x01,0xe5,0x02,0x02,0x01,0x06,0x02,0x01,0x01,0x02,0x01,0xe5,0xe5,0x03,0x02,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x05,0x01,0x01,0xe5,0x03,0x01,0x01,0xe5,0x03,0x01,
+ 0x01,0x05,0x01,0x01,0x01,0x03,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0xe6,0x06,0x02,
+ 0x02,0xe5,0x18,0xe5,0x0a,0x01,0x0f,0x02,0x02,0x1a,0x02,0x02,0x07,0xe8,0xe5,0x05,
+ 0x04,0x0a,0x01,0x06,0x22,0x07,0x02,0xe5,0x07,0x06,0x02,0xe5,0x04,0x02,0xe5,0x0e,
+ 0x03,0x02,0x0c,0x07,0x02,0xe6,0x0a,0x03,0x05,0xe5,0xe5,0xe5,0x02,0x0f,0x05,0x06,
+ 0x07,0x0a,0xe5,0x05,0x01,0x05,0xe5,0x04,0x01,0xe6,0x06,0x06,0x04,0x0b,0x05,0x03,
+ 0x13,0xe5,0x02,0x08,0x05,0x02,0x06,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x03,0x02,
+ 0xe5,0x01,0x04,0xe5,0x01,0x07,0x08,0x02,0xe6,0x10,0x03,0xe5,0x0e,0x1b,0x0d,0x08,
+ 0x13,0x07,0x08,0x07,0x2b,0x03,0x02,0x01,0x08,0x08,0x01,0x04,0x02,0x01,0x1f,0x09,
+ 0xe5,0x03,0xe5,0x01,0x07,0x08,0x03,0x01,0x07,0xe6,0x09,0x06,0xe7,0x04,0xe5,0xe5,
+ 0x03,0x0c,0x06,0x04,0x06,0xe5,0xe5,0x08,0x07,0xe5,0x05,0x05,0xe6,0x04,0xe7,0x05,
+ 0xe5,0xe5,0x0e,0xe5,0xe6,0x04,0x02,0xe5,0x02,0x04,0x09,0x02,0x03,0x02,0x09,0x09,
+ 0xe5,0x07,0x05,0x02,0x04,0xe7,0xe5,0x19,0x01,0x05,0x10,0x02,0x0a,0x0f,0x04,0x06,
+ 0x0a,0x01,0x03,0xe5,0x01,0x07,0x04,0x02,0x02,0x0b,0x10,0x09,0x02,0x02,0x0b,0x1f,
+ 0xe5,0x1a,0x04,0x05,0xe8,0x08,0x09,0xe5,0x01,0x04,0x09,0x06,0x02,0x06,0x07,0x01,
+ 0x02,0x06,0x08,0xe5,0x02,0x09,0x1d,0x03,0x01,0x01,0x19,0x06,0xe5,0xe5,0x02,0xe5,
+ 0x05,0x09,0x05,0x01,0x01,0x02,0x01,0x04,0x01,0x07,0x05,0x03,0x05,0xe5,0x01,0x0f,
+ 0xe7,0xe5,0x08,0x06,0x13,0x06,0x07,0x01,0x09,0x03,0x05,0x02,0x06,0x02,0x0e,0x06,
+ 0x1a,0x1a,0x02,0x09,0x0c,0x1a,0x0d,0x0b,0x0e,0x05,0xe5,0xe6,0x02,0x1a,0x06,0x20,
+ 0x0e,0x01,0x1d,0x02,0x01,0x06,0x03,0xe5,0x04,0x0a,0x07,0xe6,0x02,0x03,0x04,0x06,
+ 0x02,0x06,0x0c,0x04,0x0b,0x0b,0x06,0x08,0x02,0x0b,0xe6,0x07,0xe6,0x01,0xe6,0x02,
+ 0xe5,0x01,0xe5,0x12,0x01,0x0e,0x02,0x07,0x06,0xe5,0xe5,0xe5,0x04,0x08,0x01,0x01,
+ 0xe6,0xe5,0x0a,0x03,0x01,0x04,0x01,0xe5,0x09,0x09,0xe5,0x07,0x06,0x01,0x01,0x1b,
+ 0x07,0x01,0x01,0x08,0x03,0x04,0x01,0xe6,0x07,0x01,0x0f,0xe6,0x02,0x0c,0xe5,0x07,
+ 0x02,0x09,0xe5,0x03,0x0e,0x05,0x01,0x11,0x05,0x04,0x02,0x03,0x04,0xe5,0xe5,0x0f,
+ 0x03,0x15,0x10,0x02,0x11,0x13,0x01,0x04,0x11,0x07,0x0b,0x04,0xe7,0x04,0x12,0x05,
+ 0x0e,0x06,0x02,0x06,0x02,0x06,0x02,0x0e,0x01,0x02,0x13,0xe5,0x02,0x02,0x01,0x06,
+ 0x04,0x04,0x09,0x01,0x09,0x05,0xe5,0x04,0x0e,0x0b,0x0c,0x0a,0xe5,0x06,0x02,0x02,
+ 0xe5,0x12,0xe7,0xe5,0x02,0x08,0x15,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0xe5,0x01,
+ 0x05,0x02,0x01,0x05,0x01,0x09,0x08,0x08,0x05,0x02,0xe6,0x08,0x05,0x17,0x01,0x04,
+ 0x02,0x05,0x09,0x03,0x03,0x07,0x07,0x0f,0x03,0x16,0x02,0xe5,0xe5,0x04,0x08,0x1f,
+ 0x09,0x09,0x09,0xe5,0x0e,0x06,0x01,0x04,0x05,0x0b,0x0c,0x1c,0x02,0x07,0x12,0x14,
+ 0x0d,0x05,0x1a,0xe7,0x07,0x01,0x03,0xe5,0x04,0x01,0xe7,0x03,0x01,0xe5,0x07,0x01,
+ 0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x06,0x04,0x02,0xe5,0x04,0x06,0xe5,0x06,0xe5,
+ 0x01,0x03,0x02,0xe5,0xe5,0x03,0x01,0x01,0x01,0x01,0x02,0x01,0xe5,0x01,0x09,0x03,
+ 0x02,0xe5,0x04,0xe5,0x07,0x02,0x01,0x04,0x09,0xe5,0x03,0x03,0x07,0x01,0x02,0xe5,
+ 0xe5,0xe6,0x07,0xe6,0xe6,0x04,0xe5,0x09,0x03,0x01,0x02,0x01,0x05,0x01,0xe6,0xe5,
+ 0x05,0x03,0xe5,0x03,0xe5,0x03,0xe5,0x02,0x08,0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,
+ 0x01,0x04,0x04,0xe7,0x05,0x04,0x04,0xe5,0x04,0x01,0xe5,0x02,0x02,0x01,0xe5,0x04,
+ 0xe5,0x03,0x06,0x01,0xe5,0x08,0x03,0xe7,0x05,0x05,0x02,0x02,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x01,0x0a,0x02,0x05,0x04,0x08,0xe5,0x03,0xe5,0xe5,0x07,0x01,0x04,0x01,0x04,
+ 0x0a,0x07,0x09,0x01,0x04,0xe5,0x02,0x01,0x01,0xe5,0x07,0xe5,0x08,0x01,0x07,0x01,
+ 0xe5,0xe5,0x06,0x0b,0x07,0x09,0x06,0xe5,0x01,0x04,0x05,0x09,0x10,0x01,0x05,0x08,
+ 0x09,0x05,0x03,0x02,0x01,0x02,0x02,0x04,0x01,0x13,0x03,0xe5,0x03,0x05,0xe5,0xe5,
+ 0x01,0x0a,0x09,0x09,0x0f,0xe5,0x01,0x06,0x02,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,
+ 0x09,0x09,0x13,0x1d,0x05,0xe5,0x0b,0x01,0x11,0x06,0xe5,0x04,0x04,0x01,0x02,0x0c,
+ 0x04,0x01,0xe5,0x08,0x01,0x06,0x05,0xe5,0x01,0x05,0x01,0xe6,0x04,0xe5,0x01,0x05,
+ 0xe5,0x01,0xe5,0xe5,0x06,0x04,0x06,0x02,0x04,0x04,0x04,0x04,0x0b,0xe5,0x01,0xe5,
+ 0x03,0x04,0x04,0x04,0x01,0x02,0x09,0xe5,0x01,0x05,0x09,0x04,0x04,0x09,0xe5,0x01,
+ 0xe5,0x14,0x06,0x06,0xe5,0x01,0xe5,0x0c,0x03,0x04,0xe5,0x02,0x05,0x03,0x01,0x01,
+ 0xe5,0x03,0x09,0x04,0x04,0x04,0x04,0x05,0x01,0x01,0x01,0x02,0xe5,0x02,0x05,0x03,
+ 0x04,0xe5,0x02,0x05,0x03,0x0b,0x02,0x01,0xe5,0x02,0x05,0x03,0x05,0x01,0x01,0x09,
+ 0x02,0x01,0x14,0x03,0x09,0x02,0x01,0xe5,0x02,0x0f,0x03,0x02,0xe6,0x03,0x03,0xe7,
+ 0x0e,0x02,0x02,0x01,0x09,0x01,0x04,0x04,0x07,0x04,0x02,0x01,0x03,0xe5,0x01,0x01,
+ 0x06,0x01,0xe5,0x05,0x02,0x0b,0x01,0xe5,0xe6,0xe5,0x05,0x02,0x04,0xe6,0x03,0x06,
+ 0x02,0x06,0x02,0x03,0x01,0xe5,0x01,0x01,0x07,0x10,0x0c,0x06,0x04,0x07,0x01,0x03,
+ 0xe5,0x0d,0x0d,0xe6,0xe6,0x0c,0x09,0x09,0x05,0xe6,0x02,0x01,0xe7,0x01,0x03,0xe7,
+ 0x01,0x04,0x04,0x03,0xe7,0x01,0x05,0xe6,0xe5,0x02,0x05,0x04,0x01,0xe5,0xe5,0x02,
+ 0xe5,0xe6,0xe5,0x02,0xe5,0x04,0xe5,0x02,0xe5,0x01,0x01,0x03,0xe5,0xe8,0x03,0x01,
+ 0x02,0x01,0x01,0xe5,0x03,0x03,0xe5,0x07,0xe8,0x04,0xe5,0xe5,0xe6,0x02,0xe5,0xe7,
+ 0x01,0x01,0xe7,0x01,0x01,0x04,0x01,0x0a,0x0d,0x03,0x01,0xe5,0x26,0x02,0x03,0x02,
+ 0xe5,0x04,0x02,0x06,0x09,0x02,0x02,0x0d,0x02,0x06,0x04,0x04,0x02,0x01,0xe5,0x02,
+ 0x02,0xe5,0x06,0x02,0x06,0x09,0x04,0x04,0x09,0x02,0x06,0x09,0x02,0xe5,0x04,0x09,
+ 0x02,0xe5,0x11,0x02,0x0f,0xe5,0xe5,0xe6,0x09,0x1d,0x05,0xe5,0x01,0xe5,0x03,0xe5,
+ 0x01,0x01,0x03,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x13,0x01,0x03,0xe5,0x07,0xe5,0x01,
+ 0xe5,0x03,0xe5,0x09,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x03,
+ 0x03,0xe5,0x07,0xe5,0x07,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x0f,0x03,0x09,0x07,0x02,
+ 0x02,0xe5,0x09,0x03,0x09,0x09,0x05,0x03,0xe5,0x04,0x02,0xe5,0x01,0x02,0x02,0xe7,
+ 0x05,0xe5,0x03,0x03,0x02,0x03,0x02,0x03,0x05,0xe6,0x06,0xe5,0xe5,0x02,0x02,0xe5,
+ 0x04,0x01,0x02,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x04,
+ 0x02,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x02,0xe6,0x01,0x09,0xe5,0x03,0x03,0x04,0xe6,
+ 0x05,0xe6,0x01,0x02,0x1d,0x12,0xe5,0x05,0x02,0x13,0x08,0x1d,0xe5,0x07,0xe5,0x28,
+ 0x12,0xe5,0x11,0xe5,0x08,0x1d,0x04,0x02,0x02,0xe5,0x1d,0x10,0x03,0x05,0x01,0x11,
+ 0x01,0x25,0x03,0x05,0x03,0x02,0x04,0x09,0x13,0x03,0x05,0x09,0x03,0x05,0x09,0x03,
+ 0x05,0x03,0x1b,0x0a,0x01,0xe6,0x0e,0x07,0x01,0x07,0x01,0x0a,0xe6,0x05,0xe7,0x03,
+ 0x01,0xe7,0x05,0xe5,0xe5,0x03,0x09,0x01,0xe6,0x04,0x01,0xe7,0x02,0xe5,0xe8,0x02,
+ 0xe5,0xe8,0x07,0xe7,0x03,0x01,0xe5,0xe5,0x02,0xe5,0xe8,0x05,0xe7,0xe5,0x03,0xe5,
+ 0xe5,0x05,0xe7,0x02,0xe5,0xe6,0xe5,0x03,0x01,0xe7,0x06,0xe6,0xe5,0xe6,0xe5,0x06,
+ 0x01,0x01,0x05,0x01,0x0e,0x01,0x01,0x0c,0x02,0xe5,0x04,0xe5,0xe6,0x05,0x01,0xe5,
+ 0x02,0x01,0x03,0xe5,0x03,0xe5,0xe7,0x03,0xe5,0x01,0xe5,0x01,0x02,0x01,0xe6,0x06,
+ 0xe5,0x04,0xe5,0xe7,0x04,0x01,0xe6,0x01,0x02,0x01,0xe6,0x04,0x01,0xe6,0x06,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x06,0xe6,0x03,0xe5,0xe7,0x04,0x02,0xe5,0x01,
+ 0x02,0x01,0xe6,0x03,0xe5,0xe7,0x07,0xe5,0x04,0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,
+ 0x01,0xe5,0x0c,0xe5,0x01,0xe5,0x06,0xe5,0x04,0x07,0x01,0x04,0x04,0x0b,0x02,0x06,
+ 0x07,0xe5,0x0c,0x02,0x06,0x02,0x01,0x07,0x01,0xe5,0x01,0x03,0x01,0x04,0x02,0x01,
+ 0xe5,0x02,0x03,0x04,0x01,0xe5,0x01,0x01,0x03,0x06,0x03,0x04,0xe5,0x0b,0xe5,0x03,
+ 0x01,0x02,0x02,0x01,0x0b,0x02,0x05,0x02,0x03,0x01,0x07,0x01,0xe5,0x17,0xe8,0x0d,
+ 0x05,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x01,
+ 0x05,0xe6,0xe6,0x03,0xe6,0xe5,0x04,0xe6,0xe6,0x03,0xe6,0xe5,0x03,0xe6,0x01,0x05,
+ 0x01,0xe6,0xe5,0x02,0xe7,0x06,0xe6,0x01,0x04,0xe7,0x05,0xe7,0x04,0xe8,0xe5,0x02,
+ 0x01,0xe5,0x05,0xe7,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x05,0x01,0xe5,0x06,
+ 0x02,0xe5,0x0e,0x0a,0x06,0x01,0x09,0xe5,0x23,0x02,0xe5,0x04,0x01,0xe5,0x0f,0x01,
+ 0xe6,0x04,0x01,0x0c,0x0c,0xe5,0x01,0x01,0xe6,0x06,0x0a,0xe5,0x06,0xe5,0x01,0x03,
+ 0x01,0xe6,0x04,0x01,0xe5,0x07,0xe6,0x06,0x07,0x01,0x07,0x01,0x03,0x0b,0xe5,0xe5,
+ 0xe5,0x0c,0x0a,0x06,0x01,0x07,0x01,0xe5,0xe5,0x08,0x09,0x09,0x06,0x07,0x01,0x01,
+ 0x0a,0x04,0x01,0x02,0x04,0x01,0x02,0x03,0x07,0x03,0x05,0x03,0xe5,0xe5,0x01,0x01,
+ 0x01,0x02,0x02,0x01,0x01,0x05,0x03,0xe5,0x03,0x03,0xe5,0xe5,0x01,0x04,0x01,0x02,
+ 0xe5,0x01,0xe5,0xe5,0x01,0x04,0x09,0x01,0x07,0x01,0x05,0x0c,0x08,0x06,0x13,0x2f,
+ 0x0b,0xe5,0x11,0x09,0x04,0x03,0x03,0x02,0x01,0x09,0x09,0x03,0x05,0x08,0xe5,0x02,
+ 0xe5,0x02,0xe5,0x02,0x03,0x01,0x04,0x03,0xe5,0x0c,0x09,0x19,0x01,0xe5,0x0e,0xe5,
+ 0x08,0x06,0x02,0x06,0x29,0xe5,0x05,0x01,0xe5,0x0f,0x01,0x07,0x01,0x06,0x08,0xe7,
+ 0x05,0x01,0xe5,0x05,0xe7,0x01,0x03,0xe7,0x05,0xe8,0x04,0xe8,0xe5,0x04,0x07,0x01,
+ 0xe6,0x08,0x02,0x08,0x0a,0x02,0x0a,0xe5,0xe7,0x15,0x02,0x13,0x06,0xe5,0xe5,0x03,
+ 0x04,0x06,0x04,0x02,0x01,0x01,0xe5,0x07,0xe5,0xe5,0x0e,0x01,0x06,0x0b,0x02,0x09,
+ 0x06,0x01,0xe5,0x09,0x05,0x0e,0x0c,0x01,0xe5,0xe5,0xe5,0x03,0x02,0x06,0x02,0x01,
+ 0x1f,0xe5,0xe6,0x10,0x01,0x04,0x02,0x01,0x01,0x05,0xe6,0xe5,0x04,0x01,0xe6,0xe5,
+ 0x02,0x01,0x01,0x05,0xe6,0x06,0x01,0x04,0x02,0x01,0x07,0x01,0x02,0x04,0xe7,0x05,
+ 0x01,0x07,0x01,0x07,0x01,0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0x07,0x01,0x04,
+ 0x02,0x01,0x02,0x04,0x01,0x07,0x01,0x03,0x03,0x01,0xe6,0xe5,0x02,0x01,0x04,0x02,
+ 0x01,0xe5,0x05,0x01,0x02,0x04,0x01,0x02,0x01,0x02,0x02,0x02,0xe5,0x01,0x0e,0xe5,
+ 0x03,0x01,0xe5,0x0f,0x05,0x06,0x02,0xe5,0x01,0x02,0xe5,0x05,0xe6,0x02,0x0e,0xe5,
+ 0x09,0x04,0x02,0xe6,0x01,0x03,0x09,0x02,0xe5,0x01,0x03,0x01,0xe5,0x03,0x03,0xe5,
+ 0x07,0xe5,0x07,0x09,0xe5,0x04,0x02,0x0a,0xe5,0x04,0x02,0x05,0xe5,0x02,0x07,0x18,
+ 0xe9,0x01,0x04,0x03,0x09,0xe5,0xe5,0x02,0x02,0x04,0xe5,0x02,0x0b,0x09,0x05,0x02,
+ 0x03,0x02,0x06,0x04,0x0d,0xe5,0x04,0x01,0x03,0x09,0x01,0x02,0xe5,0x04,0xe5,0x01,
+ 0x0b,0x02,0x06,0x01,0x07,0x07,0x01,0x09,0x03,0xe5,0x01,0x0a,0x11,0x02,0x01,0x02,
+ 0x12,0x04,0x12,0x17,0x05,0x03,0x09,0x09,0x01,0x07,0x03,0x06,0x01,0x01,0x02,0x06,
+ 0x16,0x06,0x06,0x02,0x06,0xe5,0x05,0x02,0x05,0xe5,0x04,0x05,0x05,0x0c,0x07,0x02,
+ 0x0e,0x15,0x0a,0xe9,0x12,0x02,0x15,0x07,0xe6,0x08,0xe5,0x02,0x02,0x01,0x11,0x01,
+ 0xe5,0x05,0xe6,0x06,0xe5,0xe5,0x07,0xe5,0x06,0xe5,0xe5,0x08,0x03,0xe5,0x0a,0x0a,
+ 0x11,0x03,0x11,0xe5,0x01,0x03,0x01,0x01,0x07,0xe8,0x0b,0x08,0xe6,0x01,0x01,0x11,
+ 0x02,0x02,0x06,0x0a,0x07,0x02,0x06,0x01,0x0c,0x04,0x0a,0x02,0x04,0x01,0xe5,0x12,
+ 0x08,0xe5,0x10,0x01,0x17,0x03,0x1f,0x0d,0x08,0x05,0x06,0x0c,0x03,0xe6,0x05,0x10,
+ 0x09,0x04,0x04,0x09,0x03,0xe5,0x03,0x02,0x04,0x01,0xe5,0x02,0x04,0x04,0x02,0x01,
+ 0x09,0x02,0x06,0x09,0x07,0x03,0x01,0x01,0x03,0x0b,0x03,0x05,0x05,0x03,0x09,0xe6,
+ 0x04,0x01,0x01,0x01,0xe5,0x03,0x09,0x07,0x01,0xe5,0x07,0x17,0x01,0x02,0x09,0x0d,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0xe7,0x05,0xe6,0x06,0xe6,0x04,0x01,0xe6,0x06,0xe6,
+ 0x06,0xe6,0xe5,0x04,0xe7,0x02,0x02,0xe6,0x01,0x06,0xe7,0x05,0x09,0xe6,0x06,0xe6,
+ 0x05,0xe7,0x02,0xe5,0x01,0xe6,0x06,0xe6,0x01,0x04,0xe6,0x06,0x09,0x09,0x03,0x08,
+ 0x0e,0xe5,0xe5,0x05,0x0c,0x28,0x06,0x0c,0x06,0x02,0x09,0x09,0x08,0x02,0x04,0x05,
+ 0x0b,0x19,0x08,0x1e,0x29,0x08,0x03,0x08,0x0f,0x01,0x05,0xe7,0x05,0xe7,0x02,0x02,
+ 0xe6,0x07,0xe5,0x02,0x01,0x07,0x0e,0x01,0x06,0x01,0x07,0x07,0x0b,0x02,0xe8,0x03,
+ 0xe8,0x05,0xe7,0x01,0x02,0x09,0x06,0x04,0x13,0x03,0x04,0xe5,0xe6,0x04,0xe5,0x07,
+ 0xe5,0xe5,0x17,0x01,0xe5,0x02,0x11,0x02,0x09,0x09,0x0a,0x02,0x03,0x02,0x02,0x1c,
+ 0x06,0x1c,0x02,0x09,0x06,0xe5,0xe5,0x1a,0x02,0x13,0x07,0x01,0x03,0x03,0x01,0x0a,
+ 0x18,0xe5,0xe6,0x0a,0x02,0x02,0x06,0x06,0x02,0x09,0x08,0xe5,0x07,0xe5,0x05,0x02,
+ 0x04,0x01,0x02,0x04,0x04,0x04,0x04,0x04,0xe6,0x01,0x03,0x05,0x03,0xe5,0xe5,0x03,
+ 0x03,0x02,0x05,0xe5,0x04,0x06,0x02,0x02,0x06,0x09,0x03,0x05,0x09,0x09,0x03,0x05,
+ 0x08,0xe5,0x0e,0x04,0xe5,0x02,0x02,0x01,0x0d,0x09,0x05,0x03,0x01,0x07,0x07,0xe6,
+ 0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x05,0xe7,0x08,0xe6,
+ 0x06,0x01,0x07,0xe7,0x05,0xe6,0x06,0xe6,0x01,0x04,0xe6,0x06,0xe7,0x05,0xe6,0x08,
+ 0x06,0x02,0xe5,0xe5,0x05,0x14,0x03,0xe5,0x01,0x10,0x09,0xe5,0x07,0x09,0x33,0x08,
+ 0x18,0x0b,0x05,0x12,0x0a,0x15,0x0f,0x09,0xe6,0x06,0x03,0x10,0x02,0x01,0xe8,0x07,
+ 0xe5,0x03,0x14,0xe5,0x07,0xe5,0x03,0x03,0x01,0xe5,0x01,0x03,0x05,0x03,0x01,0xe5,
+ 0x01,0x09,0x03,0x05,0x06,0xe5,0xe5,0x02,0x05,0x01,0x04,0x01,0x02,0x03,0x02,0xe5,
+ 0xe5,0x02,0x02,0xe5,0xe5,0x02,0x02,0x01,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x02,
+ 0x05,0x0d,0x09,0x09,0x09,0x02,0xe5,0xe5,0x0d,0xe6,0xe7,0x01,0x01,0x0d,0x04,0x06,
+ 0x01,0xe5,0x01,0x06,0x02,0x08,0xe5,0x01,0xe5,0x03,0xe5,0x07,0x01,0x01,0xe5,0x03,
+ 0x02,0x06,0xe5,0x07,0x04,0x01,0x02,0x03,0xe5,0x03,0x04,0xe5,0x04,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0x02,0xe5,0x02,0x09,0x09,0xe5,0xe5,0xe5,0xe5,0x01,0x08,0xe6,
+ 0xe5,0xe5,0xe6,0x02,0x02,0x01,0xe5,0x01,0x06,0x03,0x02,0xe5,0xe5,0x0a,0x01,0x02,
+ 0x03,0x04,0x05,0xe5,0xe5,0xe5,0x21,0x04,0x04,0x04,0x02,0x01,0x04,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x04,0x04,0x01,0xe5,0xe5,0x03,0x02,0x01,0x06,0x04,0x04,0x04,0x04,
+ 0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x04,0x04,0x02,0x01,0x02,0x06,0x01,
+ 0x11,0xe5,0x0a,0x0b,0x04,0x01,0x01,0x02,0x07,0x02,0x01,0x04,0xe5,0xe5,0x08,0x09,
+ 0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x02,0x06,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x08,0x09,0x05,0xe5,0x01,0x09,0x0d,0x05,0xe5,0x0a,0x10,0x01,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,
+ 0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,
+ 0x02,0xe5,0x01,0x04,0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x03,0x02,
+ 0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x03,0xe5,0x03,0x09,0x01,0x01,0x05,0xe5,
+ 0x01,0x05,0x01,0x01,0xe5,0x0f,0x03,0x02,0x0e,0x09,0x04,0x04,0x09,0x05,0x03,0x05,
+ 0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x02,0x01,0xe5,0x02,0x02,0x01,0xe5,
+ 0x02,0x07,0x03,0x02,0xe7,0x02,0x04,0xe5,0x02,0x01,0x02,0xe5,0x02,0x02,0xe7,0x02,
+ 0x02,0xe7,0x02,0x05,0x03,0x02,0xe7,0x02,0x09,0x04,0x04,0x02,0x01,0x04,0x04,0xe5,
+ 0x02,0x09,0x02,0xe5,0x01,0xe5,0x0b,0x01,0x04,0x02,0x04,0x01,0xe5,0xe5,0x05,0x02,
+ 0x06,0x02,0x03,0xe5,0x03,0x06,0x02,0x03,0xe5,0x03,0x06,0x01,0xe5,0x02,0xe5,0x03,
+ 0x06,0x02,0x03,0xe5,0x03,0x06,0x04,0x04,0x04,0x05,0xe6,0xe5,0x08,0x06,0x02,0x06,
+ 0x02,0x03,0x05,0x06,0x04,0x04,0x01,0xe5,0x03,0x02,0x01,0x09,0x04,0x01,0xe7,0x0e,
+ 0x04,0x02,0x0a,0x01,0x04,0xe5,0xe5,0x02,0xe5,0xe8,0x02,0xe5,0x01,0x01,0x03,0xe5,
+ 0xe6,0x02,0x02,0x01,0x01,0x02,0x01,0xe5,0xe7,0x01,0x02,0x01,0x01,0x02,0x01,0xe7,
+ 0x03,0x02,0x01,0x01,0x02,0x01,0xe5,0xe7,0x01,0x02,0x01,0x01,0x02,0x01,0xe5,0xe7,
+ 0x03,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0xe5,0x05,0x01,0xe5,0xe7,0x01,0x01,
+ 0xe5,0xe7,0x01,0x02,0x06,0x01,0xe5,0xe6,0x02,0x01,0xe5,0xe5,0xe6,0x02,0xe5,0x03,
+ 0x03,0xe5,0x03,0x03,0xe5,0xe5,0x01,0x0d,0x02,0x02,0xe5,0xe5,0x12,0x04,0x02,0x06,
+ 0x09,0x02,0x01,0x01,0x02,0x02,0x02,0xe5,0x01,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x05,0x02,0x02,0x03,
+ 0x02,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x01,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,0x06,0x04,0x0f,0x02,0x02,0xe5,
+ 0x13,0xe5,0x03,0xe5,0x01,0x01,0x03,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x01,0x03,0xe5,
+ 0x01,0x05,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x06,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0x07,0xe5,0x01,0x01,0x03,0xe5,0x01,0x14,0xe5,0xe6,0x0a,0x02,0x06,0x02,0xe5,0xe6,
+ 0x01,0x02,0xe5,0x04,0x02,0xe5,0xe6,0x02,0x01,0xe8,0x02,0x01,0xe5,0x05,0x01,0xe7,
+ 0x03,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x07,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x01,0x02,0x02,
+ 0xe5,0x01,0x02,0x02,0x02,0x01,0x01,0x05,0xe5,0xe5,0x01,0x02,0x06,0x02,0x08,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x08,0xe5,0x08,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x04,0x03,
+ 0xe7,0x08,0x0b,0x05,0x03,0x05,0x03,0x05,0x02,0x02,0x09,0x02,0xe5,0x04,0x02,0x06,
+ 0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x05,0xe5,0x01,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0x06,0x02,
+ 0xe5,0x04,0x02,0xe5,0x02,0x05,0x03,0x05,0x03,0x05,0x01,0x09,0x0a,0x03,0x0c,0xe5,
+ 0xe5,0x05,0x02,0xe5,0xe5,0x05,0xe7,0x05,0xe5,0xe5,0x05,0xe7,0x03,0x02,0xe6,0x03,
+ 0x02,0xe6,0x03,0x02,0x01,0x01,0x02,0x02,0xe6,0x03,0x02,0x01,0x01,0x02,0x02,0x01,
+ 0x04,0x02,0xe6,0x05,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,
+ 0x02,0xe6,0xe5,0x01,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0x01,0x06,0xe7,0x05,0xe7,
+ 0x05,0xe7,0x02,0x02,0x0f,0xe7,0x0c,0x01,0xe5,0x05,0x01,0xe6,0x03,0xe5,0xe7,0x04,
+ 0x01,0xe6,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x06,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0xe5,0x04,0x01,0xe6,0x03,0xe5,0xe7,0x04,0x01,0xe6,0x04,0x02,0x06,0xe5,0x02,
+ 0x03,0xe7,0x0d,0x04,0x09,0x09,0x01,0x07,0x01,0x04,0x07,0x01,0x02,0x01,0x02,0x01,
+ 0x07,0x09,0x01,0x04,0x02,0x09,0x06,0x02,0x08,0x02,0x09,0x01,0x02,0x04,0x06,0x02,
+ 0x09,0x09,0x09,0x09,0x04,0x09,0x08,0xe5,0x05,0x07,0x12,0x0d,0x01,0x03,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x01,0x02,0xe5,0xe6,0x04,0x01,0xe5,0x06,0xe6,0x01,0x03,0x01,0xe5,
+ 0x01,0x04,0xe6,0x01,0x03,0x01,0xe5,0x01,0x03,0xe7,0x01,0x03,0x01,0xe5,0x01,0x03,
+ 0xe7,0x01,0xe5,0x03,0xe5,0x03,0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0xe5,0x01,0xe7,
+ 0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0x01,0xe5,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,
+ 0x01,0xe5,0x01,0x03,0xe8,0x01,0x04,0xe6,0x01,0x02,0xe6,0xe5,0x04,0xe6,0xe5,0x06,
+ 0xe7,0x02,0x01,0x01,0x01,0x08,0x04,0x01,0x0a,0x09,0xe5,0x07,0xe5,0x03,0xe5,0xe5,
+ 0x05,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0xe6,0x03,0x02,
+ 0xe5,0x03,0xe5,0x03,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x07,0xe6,0x03,0x03,0x09,0x04,0x04,0x04,0x03,0x0f,
+ 0x02,0x09,0x03,0x01,0x03,0x02,0x03,0x01,0x03,0x05,0x03,0x05,0x02,0xe6,0xe5,0x01,
+ 0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,
+ 0x02,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x03,0x04,0x02,
+ 0xe5,0xe6,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0xe5,0xe6,0x01,0x02,
+ 0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x03,0x02,0xe5,0xe6,0x02,0x01,0x09,
+ 0x03,0x03,0x01,0x03,0xe5,0x0f,0xe6,0xe5,0x0b,0xe5,0xe5,0x03,0xe6,0x05,0xe7,0x05,
+ 0xe7,0x05,0x01,0x01,0x06,0xe5,0xe5,0x04,0x01,0x01,0x06,0xe5,0xe5,0x04,0x01,0x01,
+ 0x05,0xe6,0xe5,0x04,0x01,0x01,0x05,0xe6,0xe5,0x01,0x04,0x02,0xe5,0x01,0x03,0xe5,
+ 0xe5,0x04,0xe6,0xe5,0x01,0x02,0xe6,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x02,0x01,0x01,
+ 0x02,0x02,0xe6,0xe5,0x01,0x02,0x01,0x01,0x06,0xe5,0x0d,0x02,0xe6,0x06,0xe6,0x02,
+ 0x11,0xe5,0x0c,0x01,0xe5,0x01,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x01,
+ 0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x06,0x02,0x05,0xe5,
+ 0x01,0x05,0xe5,0x03,0x05,0xe5,0x01,0x05,0x03,0x06,0x02,0x05,0xe5,0x01,0x06,0x02,
+ 0x06,0x02,0x09,0x05,0x13,0xe5,0x07,0xe5,0x01,0x02,0x11,0xe5,0x01,0x0d,0x08,0x06,
+ 0xe5,0xe5,0x05,0x02,0x28,0x13,0x1f,0x13,0x09,0x23,0x09,0x02,0x06,0x07,0x01,0x02,
+ 0xe5,0x07,0xe5,0x0b,0x01,0x01,0x0b,0x05,0x01,0x01,0x05,0x01,0x02,0xe5,0x02,0x01,
+ 0xe6,0x04,0x01,0x07,0x01,0x07,0xe6,0xe5,0x04,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,
+ 0x01,0x05,0x01,0xe5,0x05,0xe6,0x01,0x04,0xe6,0x08,0xe6,0x06,0x01,0x07,0xe6,0x01,
+ 0x04,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0xe6,0x05,0xe5,0xe6,0x01,0x03,0x01,0xe6,
+ 0x01,0x02,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x0a,0x02,0xe5,0x01,0x10,0x03,0x01,
+ 0xe5,0x01,0xe5,0x07,0x03,0xe6,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x04,0x07,0x01,0xe6,
+ 0x03,0xe5,0xe5,0x09,0x05,0x09,0xe5,0xe5,0x05,0x02,0x05,0x02,0xe5,0x02,0x08,0xe5,
+ 0x03,0xe5,0x07,0xe5,0x01,0xe5,0x03,0xe5,0x01,0xe5,0x03,0x03,0x05,0xe5,0x02,0x01,
+ 0x01,0xe5,0x03,0x02,0x02,0x02,0x05,0xe5,0x05,0xe5,0xe5,0x05,0x10,0xe6,0xe6,0x11,
+ 0x09,0x09,0x02,0x0f,0xe5,0x0b,0x01,0x03,0x04,0x07,0x06,0x0a,0x04,0x03,0x10,0x04,
+ 0x03,0x04,0x03,0x01,0x07,0x01,0x02,0x04,0x02,0x05,0x07,0x03,0x01,0x0a,0xe6,0x01,
+ 0x02,0x03,0x01,0x02,0x01,0x07,0xe5,0x02,0x0e,0x06,0xe5,0xe7,0x11,0x04,0x01,0x0c,
+ 0x03,0x02,0x02,0x0d,0x05,0x0f,0x03,0x0b,0x04,0x09,0x09,0x06,0x04,0x0c,0x06,0x09,
+ 0x06,0x02,0x09,0x09,0x0a,0x12,0xe5,0x04,0x12,0xe5,0x06,0x03,0x0d,0xe6,0x08,0x07,
+ 0xe6,0x03,0x04,0xe5,0x03,0x01,0x0c,0x03,0xe5,0x02,0x03,0x05,0xe5,0x02,0xe5,0x02,
+ 0x05,0x01,0x01,0xe5,0x05,0x01,0x06,0xe8,0x05,0x01,0x01,0x06,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x02,0x01,0xe6,0xe5,0x04,0xe6,0xe5,0x06,0x01,0x07,0x01,0x07,
+ 0xe5,0x07,0x06,0x04,0x06,0x07,0x06,0x01,0xe9,0x07,0x05,0x06,0x01,0x08,0x01,0x04,
+ 0x0c,0x02,0x03,0x07,0x0b,0x01,0x07,0x0a,0x02,0x02,0x09,0x06,0x06,0xe5,0xe5,0xe5,
+ 0xe5,0x08,0x07,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x07,0x01,0x02,0x01,0x02,0x01,
+ 0x07,0x01,0x05,0x05,0x07,0x10,0x08,0x0c,0x09,0x09,0x08,0x0e,0x01,0x08,0xe5,0x07,
+ 0xe6,0x05,0x03,0x05,0xe6,0x06,0xe6,0x02,0x04,0xe5,0x04,0x01,0xe6,0x08,0x03,0x03,
+ 0x03,0x04,0xe5,0xe5,0x04,0xe6,0x01,0xe5,0x04,0x07,0x05,0x04,0x07,0x05,0xe5,0x02,
+ 0x04,0xe6,0x15,0x03,0x05,0x11,0x01,0x03,0xe5,0x01,0x0d,0x03,0x20,0x01,0x0f,0x0b,
+ 0x09,0x05,0x03,0x01,0x02,0x0e,0x0b,0x01,0x02,0x04,0x09,0x01,0x07,0x0e,0x0e,0x01,
+ 0xe5,0x05,0x0c,0x09,0x09,0x02,0x07,0xe5,0x0a,0x03,0x02,0x10,0x07,0x01,0x07,0x08,
+ 0x0b,0x01,0x07,0x09,0x04,0x07,0x01,0x03,0x09,0x0c,0x01,0x07,0x02,0x04,0xe5,0x04,
+ 0x0d,0x02,0x04,0x01,0x08,0xe5,0x01,0x07,0x08,0x07,0x01,0x0a,0x0d,0x07,0x08,0x06,
+ 0x03,0x01,0xe6,0x07,0xe5,0x0b,0x09,0x12,0xe5,0x05,0x09,0x01,0x08,0x06,0x01,0x06,
+ 0x04,0xe5,0x06,0x01,0x06,0x02,0xe8,0x05,0xe5,0x05,0x06,0x01,0xe5,0xe5,0x04,0x0e,
+ 0x06,0x08,0xe5,0x01,0x04,0x04,0x09,0xe6,0x07,0xe5,0x08,0x01,0x15,0x01,0xe5,0xe6,
+ 0x05,0x04,0x06,0x14,0x01,0x19,0x1d,0x13,0x08,0x03,0xe7,0x04,0x03,0xe5,0x06,0x09,
+ 0xe5,0x07,0x06,0xe5,0xe7,0x03,0x02,0x09,0x0e,0x03,0x02,0x02,0x09,0x0b,0x0d,0x02,
+ 0x02,0x0c,0x1b,0x01,0x06,0xe5,0xe6,0x01,0x02,0x09,0x06,0x02,0xe5,0xe5,0x01,0x09,
+ 0xe5,0x02,0x01,0x05,0xe5,0x04,0xe5,0x04,0x09,0x01,0x03,0x03,0x01,0xe5,0x04,0x10,
+ 0x03,0x01,0x07,0x01,0x03,0x0d,0x01,0x08,0x06,0x02,0xe6,0x0b,0x15,0x02,0xe5,0xe5,
+ 0x0b,0x0b,0xe5,0x07,0xe5,0x05,0x03,0x05,0x0a,0x06,0x01,0x02,0x06,0xe5,0x04,0x0c,
+ 0xe5,0x11,0xe5,0x09,0x0a,0x06,0x01,0x03,0x05,0x09,0xe5,0x0f,0x01,0xe5,0x0b,0x09,
+ 0x05,0x01,0x09,0x07,0xe5,0x02,0x09,0x03,0x10,0x03,0x17,0x09,0x1d,0x13,0x15,0x0a,
+ 0x06,0x16,0x09,0x2f,0xe5,0x10,0x02,0x0c,0x01,0xe5,0x01,0xe6,0x0d,0xe5,0x01,0x01,
+ 0x04,0x02,0xe5,0x0e,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x09,
+ 0xe5,0x04,0x02,0xe5,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0xe5,0xe6,0x04,0x13,0xe5,
+ 0x07,0x08,0xe5,0x01,0xe5,0x03,0xe5,0x09,0x05,0x02,0x01,0x08,0xe5,0x01,0x02,0xe5,
+ 0x18,0xe5,0x07,0x09,0x06,0x02,0x09,0x02,0x01,0x04,0x09,0x05,0xe5,0x01,0x05,0x03,
+ 0x07,0xe5,0x01,0x06,0x02,0x09,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x02,
+ 0xe5,0x14,0xe5,0xe5,0xe5,0xe5,0xe7,0xe5,0x08,0x03,0xe5,0x0c,0x01,0x02,0x03,0x04,
+ 0x0a,0x02,0x01,0xe5,0xe5,0xe5,0xe5,0x04,0x01,0x0e,0xe5,0xe5,0x05,0xe5,0xe5,0x04,
+ 0xe5,0x01,0x01,0x04,0x01,0x02,0x04,0xe5,0x02,0xe5,0x05,0x10,0xe5,0x05,0x01,0xe5,
+ 0x01,0x0c,0x04,0xe5,0xe5,0x04,0xe5,0x03,0x03,0xe5,0x08,0x01,0xe5,0x04,0xe5,0x03,
+ 0x01,0x05,0x0b,0x09,0x04,0xe5,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0xe6,0x05,0x07,0xe5,
+ 0x01,0x0a,0x06,0x02,0x01,0x04,0xe5,0xe5,0xe5,0x0c,0xe5,0x01,0x06,0x02,0x06,0x02,
+ 0x06,0x02,0x05,0xe5,0x01,0xe5,0xe5,0x02,0xe5,0xe5,0x04,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe5,0x13,0xe5,0x01,0x09,0x13,0x09,0x06,0x02,0x09,0x09,0x06,0x02,0x01,0x07,0x01,
+ 0x0b,0x06,0x05,0x09,0x05,0x06,0x09,0x04,0x01,0x07,0x01,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x01,0xe7,0x03,0x04,0x01,0xe5,0xe5,0x05,0x09,0x02,0xe5,0x01,0x05,0xe5,
+ 0x01,0x04,0x02,0x01,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x01,0x09,0xe5,0x01,0x02,
+ 0x02,0xe5,0x01,0x02,0x02,0x01,0x01,0xe5,0xe5,0x01,0xe5,0xe6,0x01,0x02,0x06,0x02,
+ 0x03,0x02,0x02,0xe5,0xe6,0x13,0x05,0xe5,0x01,0xe5,0x01,0x0a,0x03,0x04,0x04,0x09,
+ 0x05,0x01,0x01,0x05,0x01,0x02,0x06,0x02,0x09,0x06,0x02,0x04,0x01,0x04,0x01,0x02,
+ 0x07,0x04,0x03,0x04,0x07,0x04,0x04,0x09,0x01,0x02,0x09,0x03,0xe5,0x03,0x03,0xe5,
+ 0x03,0x04,0x01,0x02,0x01,0x01,0x02,0x02,0x04,0x03,0x03,0x01,0x03,0x02,0x01,0x04,
+ 0x09,0x09,0x05,0xe6,0x0d,0x05,0x01,0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0x01,0x02,
+ 0x01,0x02,0x01,0x02,0x09,0x01,0x02,0x04,0x01,0x07,0x01,0x02,0x06,0x04,0x02,0x01,
+ 0x07,0x01,0x05,0x01,0x06,0x01,0x02,0x01,0x07,0x01,0x02,0x04,0x09,0x01,0x05,0x01,
+ 0x01,0x02,0x02,0x01,0x0b,0x02,0x04,0x01,0x04,0x04,0x01,0x07,0x07,0x01,0x07,0x01,
+ 0x0d,0xe5,0xe7,0x0c,0x09,0x01,0x02,0x01,0x02,0x01,0x02,0x02,0x01,0x01,0x02,0x01,
+ 0xe5,0xe5,0x03,0x04,0x01,0x02,0x04,0x04,0x04,0x01,0x02,0x04,0x03,0xe5,0xe6,0xe5,
+ 0xe5,0x01,0x04,0x01,0x02,0x04,0x03,0xe5,0xe5,0x03,0x01,0x02,0x04,0x04,0x04,0x04,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x04,0x04,0x04,0x04,0x01,0x02,0x02,0x01,0x04,
+ 0x04,0x03,0xe5,0x03,0x01,0x07,0x01,0x0e,0x02,0xe5,0x19,0x04,0x04,0x0e,0x11,0x02,
+ 0x06,0x02,0x06,0x02,0x06,0xe6,0x10,0x02,0x03,0x04,0x13,0x02,0x2e,0xe5,0x07,0x02,
+ 0x03,0x09,0x20,0xe6,0xe6,0x13,0xe5,0x03,0xe5,0x07,0xe5,0x08,0x16,0x09,0xe5,0x07,
+ 0x05,0xe5,0x01,0xe5,0x04,0x12,0xe5,0x14,0x02,0x13,0x13,0xe5,0x07,0x09,0x05,0xe5,
+ 0x07,0xe5,0x1c,0x02,0x03,0xe5,0x0a,0x02,0x04,0x01,0x02,0xe6,0x06,0xe6,0x06,0x06,
+ 0x02,0x09,0x05,0x03,0x09,0x05,0x03,0xe5,0x07,0x09,0x06,0x02,0xe5,0x04,0x04,0x09,
+ 0x05,0x03,0x09,0x03,0x02,0x02,0x06,0x02,0x06,0x02,0x03,0x05,0x03,0x05,0xe6,0x06,
+ 0xe5,0x07,0x09,0x0d,0x01,0xe7,0x01,0x06,0x02,0x09,0x13,0x06,0x02,0x09,0x27,0x09,
+ 0x06,0x09,0x18,0x09,0x06,0x0b,0x07,0x43,0x02,0xe5,0x01,0x09,0x0a,0x12,0x07,0x02,
+ 0x09,0x26,0x09,0x11,0x06,0x11,0x0a,0x41,0x20,0xe5,0xe6,0x0c,0x01,0x09,0xe7,0x03,
+ 0x01,0xe5,0xe5,0x05,0x02,0x06,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x01,0x04,0x02,
+ 0x04,0x01,0xe7,0x05,0x02,0x06,0x02,0x04,0x01,0xe7,0x07,0x02,0x01,0x02,0x01,0x02,
+ 0x01,0x04,0x02,0x06,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x06,0x02,0x04,0x01,0x02,
+ 0x01,0x05,0xe6,0x05,0xe5,0xe5,0x0f,0x0e,0xe5,0x01,0x0d,0x01,0xe5,0x04,0xe5,0x01,
+ 0xe5,0x03,0xe5,0xe7,0x01,0x02,0x03,0x02,0x02,0x03,0x05,0x01,0x01,0x05,0x01,0x01,
+ 0x05,0x03,0x04,0xe5,0xe7,0xe5,0x02,0x03,0x01,0xe5,0x01,0x03,0x05,0x02,0xe5,0x06,
+ 0x03,0x05,0x01,0x01,0x01,0x03,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x07,0x01,
+ 0x05,0x01,0x01,0x05,0x01,0x01,0x09,0x04,0x02,0xe6,0x10,0xe5,0x0c,0x01,0x01,0x0d,
+ 0x01,0x09,0x01,0x05,0x01,0x09,0x03,0x05,0x04,0x18,0x0b,0x07,0x09,0x03,0x02,0x02,
+ 0x01,0x02,0x03,0x02,0x09,0x04,0x04,0x03,0xe5,0x08,0x09,0x04,0x04,0x09,0x18,0x13,
+ 0x03,0x0b,0xe8,0x0d,0x05,0xe6,0x06,0xe6,0xe5,0x04,0xe6,0x04,0xe8,0x04,0xe7,0x05,
+ 0xe7,0x05,0xe7,0x01,0x03,0xe7,0x06,0xe7,0x05,0xe7,0x04,0xe7,0x07,0xe5,0x01,0x05,
+ 0xe7,0x01,0x04,0xe7,0xe5,0x02,0xe8,0x04,0x01,0xe5,0x01,0x03,0xe8,0x04,0x01,0xe5,
+ 0x01,0x03,0x01,0xe5,0x05,0xe7,0x02,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe5,0x06,0x01,0xe6,0x0c,0x01,0x09,0xe5,0x11,0xe6,0x06,0x09,0x09,0x09,0x13,0x07,
+ 0x01,0x0a,0x0a,0x1d,0x09,0x09,0x09,0x09,0x0a,0x08,0x13,0x0f,0xe7,0x0c,0x01,0x07,
+ 0x04,0x09,0x06,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x02,0x02,
+ 0xe5,0x01,0xe5,0x03,0xe5,0x01,0x05,0x01,0x01,0x02,0x02,0x01,0x01,0xe5,0xe5,0x01,
+ 0xe5,0x01,0x03,0x01,0x03,0x04,0x02,0x03,0x05,0x03,0x02,0x02,0xe5,0x01,0xe5,0xe5,
+ 0x01,0x03,0xe5,0xe5,0x01,0xe5,0x01,0x02,0x02,0x03,0xe5,0xe5,0x01,0xe5,0x04,0x02,
+ 0x01,0x01,0x05,0x06,0x02,0x10,0x0f,0x01,0xe6,0x0b,0x01,0x09,0xe5,0x11,0x04,0xe5,
+ 0x02,0x04,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0x08,0x03,0x05,0x08,
+ 0xe5,0x0b,0x02,0x03,0xe6,0x02,0x04,0xe5,0x07,0xe5,0x06,0x01,0x08,0xe5,0x02,0x03,
+ 0x01,0x09,0x03,0x03,0x01,0x04,0x08,0x13,0x11,0xe5,0x02,0x09,0x01,0xe5,0x05,0x15,
+ 0x03,0x01,0xe5,0x01,0x03,0x01,0xe6,0x04,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,
+ 0x01,0xe5,0x05,0xe7,0x01,0x03,0xe7,0x05,0x01,0xe5,0x06,0x01,0x04,0x04,0xe6,0x01,
+ 0x03,0x01,0xe5,0x01,0x03,0xe8,0x05,0xe6,0x01,0x03,0xe8,0x05,0xe6,0x01,0x03,0x01,
+ 0x03,0x04,0xe6,0x0b,0x13,0x0e,0x02,0xe5,0x01,0x2f,0x02,0x02,0x08,0xe5,0x07,0xe5,
+ 0x1b,0xe5,0x0f,0x02,0x12,0x09,0x01,0xe5,0x1c,0x0b,0x04,0xe5,0xe5,0x31,0x02,0x03,
+ 0x11,0x01,0x07,0x01,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe6,0xe5,0x04,0xe6,0x06,0xe6,
+ 0x06,0xe6,0x06,0x01,0x07,0x01,0x07,0x01,0x05,0x01,0x01,0x01,0x07,0x01,0x03,0x03,
+ 0xe6,0xe5,0x04,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x02,0x01,
+ 0x02,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x01,0x09,0xe7,0x0f,
+ 0x08,0xe5,0x01,0x05,0xe7,0xe5,0x03,0xe5,0xe5,0x03,0xe7,0x07,0xe6,0x06,0xe6,0x06,
+ 0xe6,0x06,0xe5,0x01,0x05,0xe5,0x03,0x03,0xe5,0x08,0x03,0x03,0x02,0xe5,0x07,0xe6,
+ 0x01,0xe5,0x01,0xe6,0xe5,0x05,0xe6,0x06,0xe5,0x05,0x01,0xe5,0x1b,0xe5,0x01,0x01,
+ 0x03,0xe5,0x02,0x1a,0x02,0x02,0xe6,0x09,0x02,0x02,0x05,0x08,0xe5,0x03,0x0b,0x0b,
+ 0x11,0x0b,0x12,0x0c,0x07,0x03,0x06,0x01,0x08,0xe5,0xe5,0x01,0x01,0x02,0x09,0x01,
+ 0x02,0x01,0xe5,0xe5,0x06,0x06,0x02,0x0b,0x01,0xe5,0x06,0xe5,0x04,0x09,0x05,0x0b,
+ 0x02,0x01,0x01,0x11,0x02,0x02,0x06,0x02,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0x04,0x01,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x09,0x03,0x04,
+ 0x09,0x05,0xe5,0x0b,0x06,0x09,0x02,0xe5,0x02,0xe5,0x09,0x05,0x03,0x09,0x04,0x0c,
+ 0x06,0x0e,0x01,0x0d,0xe6,0x02,0x08,0x04,0x07,0x01,0x01,0x07,0x01,0x07,0x01,0x04,
+ 0x02,0x01,0x11,0xe6,0x06,0x01,0x07,0x01,0xe5,0x03,0x01,0x01,0x07,0x01,0x01,0x04,
+ 0x08,0x05,0x0a,0x13,0x12,0xe5,0x08,0x1d,0x04,0x03,0xe5,0x02,0xe5,0xe6,0x08,0x04,
+ 0x02,0x03,0x09,0x04,0x08,0x09,0x03,0x03,0x02,0x06,0x02,0x02,0x01,0x11,0x01,0x01,
+ 0x02,0x02,0x03,0x02,0x02,0x0b,0x01,0xe6,0xe5,0x02,0x02,0x08,0x01,0x05,0x0a,0xe5,
+ 0x08,0x08,0x09,0x03,0x04,0x01,0x07,0xe6,0x10,0x09,0x09,0xe7,0xe5,0x0f,0x09,0x10,
+ 0x01,0x03,0x03,0x01,0x01,0x07,0xe5,0x07,0x09,0x07,0x01,0x09,0x09,0x02,0x01,0x04,
+ 0x03,0xe5,0x01,0x03,0x09,0x09,0x05,0x03,0x02,0x06,0x09,0xe5,0x07,0x03,0x2d,0x0d,
+ 0xe5,0xe5,0xe5,0x0b,0x0e,0x10,0x01,0x07,0x05,0x03,0x09,0x09,0x01,0x04,0x02,0x09,
+ 0x03,0x05,0x09,0x04,0x01,0x04,0x03,0x05,0x09,0x09,0x09,0x03,0x02,0x02,0x09,0x0d,
+ 0x11,0x0c,0x02,0xe7,0xe5,0x0a,0xe9,0xe5,0x06,0xe5,0x06,0x0b,0x06,0x04,0x06,0x1d,
+ 0x0c,0x1b,0x0a,0x01,0x0a,0x09,0x0e,0x03,0x0f,0x1d,0x09,0x13,0x08,0x03,0xe5,0x01,
+ 0x01,0x06,0x0f,0x04,0x02,0xe6,0x03,0x0c,0x05,0x03,0x09,0x08,0xe5,0x09,0xe6,0xe5,
+ 0x04,0xe7,0x05,0xe6,0x13,0x03,0x22,0xe6,0x02,0x08,0x03,0x1e,0xe6,0x16,0x09,0xe9,
+ 0x02,0x11,0x03,0x07,0x02,0x0e,0x12,0x09,0x0d,0x09,0x09,0x12,0x02,0x25,0x02,0x05,
+ 0x14,0x11,0x05,0x03,0x1f,0xe6,0x09,0x09,0x09,0x01,0x02,0x03,0xe5,0x03,0x04,0x04,
+ 0x03,0x05,0x06,0x02,0x06,0x02,0x04,0x04,0x04,0x04,0x04,0x01,0x02,0x04,0x01,0x02,
+ 0x04,0x06,0x01,0x01,0x05,0x02,0x03,0x02,0x03,0x05,0x09,0x03,0xe5,0xe5,0x01,0x04,
+ 0x04,0x04,0x0b,0x02,0x19,0x0e,0x03,0x03,0xe5,0x0e,0x0b,0x05,0xe5,0xe6,0x02,0x01,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0xe5,0x03,0xe5,0x01,0x05,0xe5,0x01,0xe5,0x03,
+ 0xe5,0x01,0x05,0xe5,0x01,0x05,0xe6,0x01,0x04,0xe6,0x01,0x02,0x01,0x01,0xe5,0x07,
+ 0xe6,0x02,0x03,0xe5,0x01,0x03,0x01,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe6,0x06,0xe5,
+ 0x0a,0x07,0x06,0x04,0x09,0x12,0x03,0x01,0xe6,0x1a,0x07,0x08,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x09,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x0b,0x09,0x09,0x09,0x09,
+ 0x03,0xe5,0x03,0x09,0x02,0x09,0x08,0x0a,0x20,0x01,0xe6,0x0c,0x06,0xe5,0xe5,0x02,
+ 0x09,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x05,0x06,0xe5,0xe5,0x02,0x02,0xe5,0xe5,
+ 0x02,0x02,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x02,0x02,0xe5,0xe5,
+ 0x05,0xe5,0x02,0x03,0x01,0xe5,0x01,0x09,0x06,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,
+ 0x02,0x02,0xe5,0xe5,0x02,0x01,0xe5,0x05,0x02,0xe5,0x0d,0xe5,0x08,0x05,0x0c,0xe5,
+ 0x09,0x02,0xe5,0xe6,0xe5,0xe5,0x07,0x09,0x04,0x04,0xe5,0xe5,0x07,0x02,0x06,0x01,
+ 0x02,0x01,0x02,0x09,0x01,0xe5,0x05,0x01,0x02,0x01,0x02,0xe5,0xe5,0x05,0xe5,0x02,
+ 0x01,0x02,0xe5,0x02,0x01,0x02,0x02,0x08,0xe5,0xe5,0x05,0x03,0xe5,0x03,0x02,0x01,
+ 0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x03,0xe5,0x02,0xe5,0x01,0xe6,0x0f,0x02,
+ 0x01,0xe6,0x07,0x06,0x01,0x0c,0x01,0x04,0x01,0x04,0x08,0x09,0x03,0x07,0x04,0x04,
+ 0x04,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x04,0x04,0x02,0x01,0x04,0x04,0x04,0x02,
+ 0x01,0x04,0x02,0x01,0x04,0x04,0x06,0x04,0x04,0x02,0x01,0x04,0x04,0x04,0x01,0xe5,
+ 0xe5,0x03,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x01,0x03,0x05,0x01,0x04,0x01,0xe5,
+ 0xe5,0x08,0x01,0x05,0x0d,0x02,0xe5,0x02,0x04,0x02,0xe5,0xe6,0x09,0x09,0x09,0x06,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x02,0x06,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x08,
+ 0x01,0x07,0x01,0x07,0x09,0x10,0xe5,0x04,0x02,0xe9,0xe5,0x09,0x09,0x04,0x06,0x02,
+ 0x06,0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0xe5,0x01,0x02,
+ 0x02,0x01,0x01,0x02,0x02,0x06,0x02,0x01,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x08,
+ 0x02,0x06,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x02,0x04,0x04,0x09,
+ 0x10,0x02,0xe5,0x01,0xe5,0x08,0x01,0x0d,0x01,0xe5,0xe5,0x08,0x02,0xe5,0x02,0x05,
+ 0x03,0x05,0x03,0x05,0x03,0x02,0xe7,0x02,0x05,0x03,0x04,0xe5,0x02,0x05,0x03,0x04,
+ 0xe5,0x02,0x05,0x03,0x04,0xe5,0x02,0x05,0x03,0x01,0x02,0x02,0x03,0x05,0x03,0x02,
+ 0xe7,0x02,0x02,0xe7,0x02,0x04,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0x02,0x09,0x09,
+ 0x05,0x03,0x02,0x01,0xe5,0x02,0x05,0x01,0x01,0x09,0x02,0x01,0xe6,0x0c,0x09,0x03,
+ 0xe5,0xe5,0x03,0x01,0x02,0x01,0xe5,0x02,0x02,0x02,0x03,0x05,0x03,0x02,0xe7,0x02,
+ 0x05,0x03,0x01,0xe6,0xe5,0x08,0x03,0x03,0x01,0x03,0x05,0x06,0x04,0x04,0x04,0x09,
+ 0x03,0x02,0x02,0x06,0xe5,0xe5,0x06,0x01,0x06,0xe5,0x02,0x02,0x01,0x02,0x01,0x03,
+ 0xe5,0x01,0x01,0x04,0x04,0x01,0x05,0x09,0x01,0x0d,0x02,0xe6,0x01,0x0a,0x09,0x04,
+ 0x02,0x01,0x04,0x01,0x01,0x02,0x02,0x02,0x03,0x02,0x06,0x02,0xe6,0x03,0x02,0x06,
+ 0x02,0x01,0x04,0x01,0xe5,0x05,0x02,0x06,0x02,0x06,0x01,0xe5,0xe7,0x03,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x02,0x01,0xe6,0x01,0x01,0xe8,0x02,0x01,0xe5,0x05,0x01,0xe8,
+ 0x02,0x01,0xe8,0xe5,0xe5,0xe6,0x03,0x01,0x04,0xe5,0xe5,0x03,0x04,0x09,0x01,0x0b,
+ 0xe5,0x02,0x01,0xe5,0xe5,0x16,0x09,0x06,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x0c,0x01,0x04,0x20,0x01,0xe5,0xe5,0x19,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x06,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0x0d,0x03,0xe5,0x20,0xe8,0x0d,0x02,0x06,0xe6,0x06,
+ 0xe6,0x01,0x01,0xe5,0xe7,0x02,0x01,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,
+ 0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe5,0x07,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x07,0xe5,0x04,0x02,0x02,0x06,0xe6,0x06,0x09,0x0d,0x01,0x01,0xe5,
+ 0x29,0xe5,0x08,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x0f,0x02,0x2c,0x02,0x01,0x01,0x29,0x01,0x09,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0xe5,0x04,0x02,0x06,0x02,0x06,0x02,0xe5,0x05,0xe5,0x01,0xe5,0x04,
+ 0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x08,0x01,0x32,0xe5,0xe6,0x0c,0x01,0x0a,0xe6,0x05,0xe5,0xe5,0x05,0xe7,0x03,0x02,
+ 0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,
+ 0x03,0x02,0xe6,0x03,0x02,0xe6,0x05,0x02,0xe6,0x03,0x02,0x01,0x04,0x02,0xe6,0x03,
+ 0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x01,0x01,0xe5,0xe6,0xe5,
+ 0x03,0x01,0x07,0x01,0xe5,0xe5,0xe5,0x1d,0x01,0xe5,0x0c,0x01,0xe5,0x09,0x07,0xe6,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x06,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x21,0x01,0xe5,0x0a,0xe5,0xe5,
+ 0x0a,0x07,0x13,0x09,0x09,0x09,0x09,0x03,0xe5,0x03,0x09,0x09,0x08,0x02,0x09,0x03,
+ 0x05,0x03,0x05,0x04,0x04,0x09,0x04,0x04,0x07,0x01,0x03,0x03,0x01,0x06,0xe5,0xe5,
+ 0x22,0x01,0xe5,0x08,0x03,0x01,0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x02,0x02,0xe7,
+ 0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,
+ 0x01,0xe5,0x01,0xe7,0x01,0xe5,0x02,0xe6,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x02,0xe6,
+ 0x03,0xe5,0x02,0xe6,0x01,0x03,0x01,0xe5,0x01,0xe5,0x01,0xe7,0x01,0x04,0xe6,0x01,
+ 0x04,0xe6,0x01,0x03,0xe7,0x01,0x05,0xe6,0xe5,0x02,0x01,0xe6,0x06,0xe6,0xe5,0x04,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,0x1a,0x08,0xe6,0x04,0x01,0xe5,0x04,0x02,
+ 0xe6,0x03,0x02,0xe5,0x04,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x04,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,
+ 0xe6,0x03,0x02,0xe5,0x04,0x02,0xe6,0x03,0x02,0xe6,0x0d,0xe5,0xe7,0x07,0x09,0x09,
+ 0x0d,0xe6,0xe5,0x19,0x01,0x06,0x02,0x04,0x01,0x02,0xe5,0xe6,0x01,0x02,0xe5,0xe6,
+ 0x01,0x02,0xe5,0xe6,0x01,0x02,0xe5,0xe6,0x01,0x02,0xe5,0xe6,0x01,0x02,0x01,0xe6,
+ 0x01,0x02,0x02,0xe5,0x01,0x02,0xe5,0xe6,0x01,0x02,0x03,0x04,0x02,0x01,0xe6,0x01,
+ 0x02,0xe5,0xe6,0x01,0x02,0x01,0xe6,0x01,0x02,0x01,0xe6,0x01,0xe5,0xe5,0x01,0xe5,
+ 0x01,0x02,0x01,0xe6,0x01,0x02,0x02,0x06,0x02,0xe6,0xe5,0x09,0x01,0x18,0xe5,0x03,
+ 0xe5,0xe5,0xe6,0x21,0x07,0x02,0x03,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x03,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x02,0x01,0x01,0x02,0x03,0xe5,0xe5,0x01,0x03,
+ 0xe5,0xe5,0x01,0x03,0x03,0xe5,0x01,0x04,0x01,0x07,0x01,0x02,0x02,0x01,0x01,0x07,
+ 0x01,0x06,0xe5,0xe5,0x04,0x01,0x01,0x07,0x07,0x01,0x01,0x01,0x14,0x09,0x06,0x06,
+ 0xe5,0x01,0x03,0x1f,0x09,0x03,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0xe5,0x01,0x05,0x03,0x05,0x03,0x0b,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x01,0x05,0x03,0x05,0xe5,0x01,0x05,0x09,0xe5,0x01,0x01,0xe5,0x12,0x09,
+ 0x07,0x03,0x01,0x01,0xe6,0x0c,0x01,0xe5,0x05,0xe5,0xe5,0x3b,0x13,0x13,0x15,0x17,
+ 0x0f,0x05,0x02,0x0a,0x1b,0xe5,0x16,0xe8,0x0d,0x02,0x01,0x01,0x01,0x03,0xe6,0x06,
+ 0x01,0x02,0x04,0x01,0x01,0x05,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0x01,0x01,0x05,0xe6,
+ 0x06,0x01,0xe6,0x04,0xe6,0x06,0xe6,0xe5,0x04,0x01,0x02,0x06,0x01,0x01,0x05,0xe6,
+ 0x06,0x01,0x02,0x04,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x01,0x02,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x03,0x03,0x02,0xe5,0xe6,
+ 0x1a,0x04,0x02,0x03,0x05,0xe5,0x01,0xe5,0x03,0x09,0xe5,0xe5,0x06,0x09,0x08,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0xe5,0xe6,0x02,0xe5,0x06,0x02,0xe5,0x01,0xe5,0x03,0xe5,
+ 0x04,0x02,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x03,0x01,0xe5,0x04,
+ 0x05,0x03,0x04,0x07,0x01,0x07,0xe5,0x02,0x04,0xe5,0x0e,0x01,0xe5,0x0a,0x09,0x07,
+ 0x04,0x04,0x03,0x0c,0x06,0x07,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0xe5,0xe5,0x03,
+ 0xe5,0x02,0x04,0x01,0xe5,0xe5,0x03,0xe5,0x03,0x02,0x04,0xe7,0x03,0xe5,0x09,0xe5,
+ 0x04,0x02,0xe5,0x05,0xe5,0xe5,0x07,0x08,0x01,0xe5,0x20,0x03,0x11,0x06,0xe9,0xe5,
+ 0x18,0x0c,0x01,0x02,0x06,0x02,0x05,0xe5,0xe5,0x02,0xe5,0x0b,0x05,0x10,0x02,0x03,
+ 0x05,0x03,0x02,0x06,0x0e,0x14,0x03,0x05,0x07,0x05,0x08,0x08,0x07,0x03,0x03,0x09,
+ 0x08,0x01,0x0f,0x01,0xe5,0x0c,0x01,0x0d,0x01,0x0b,0x01,0x01,0x05,0x01,0x07,0xe6,
+ 0x03,0x04,0x02,0x04,0x01,0x11,0x01,0x07,0x01,0x09,0x02,0x01,0x02,0x01,0x01,0x05,
+ 0x01,0x07,0xe8,0x01,0x04,0x01,0xe5,0x03,0x01,0x0b,0xe5,0x05,0x08,0xe7,0x08,0x02,
+ 0xe5,0x04,0xe5,0x23,0xe6,0x0c,0xe5,0x04,0x0a,0x0a,0x01,0x03,0x03,0x01,0x19,0x01,
+ 0x01,0x03,0x01,0xe5,0x03,0x01,0x01,0x01,0x01,0x05,0x01,0x01,0x05,0x0b,0x01,0x01,
+ 0x03,0x02,0x02,0x02,0x01,0x08,0xe5,0x03,0x04,0x05,0x07,0x0b,0x07,0x06,0x09,0x01,
+ 0x06,0x06,0x01,0x01,0x06,0x02,0x09,0xe5,0xe6,0x02,0x04,0x23,0x08,0xe5,0x06,0xe6,
+ 0x06,0xe6,0x03,0x01,0x01,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x02,0xe5,0x02,0xe5,0x02,
+ 0xe5,0x01,0xe6,0x02,0x03,0xe5,0xe6,0x07,0xe5,0x02,0x03,0xe6,0x04,0x01,0x01,0x03,
+ 0x04,0xe5,0x02,0x04,0xe6,0x0b,0x0a,0x02,0x0a,0xe5,0x21,0x01,0x01,0xe5,0x01,0x0c,
+ 0x09,0x0d,0x0c,0x01,0x07,0x01,0x02,0x02,0x01,0x04,0xe5,0x02,0x01,0x07,0x07,0x01,
+ 0x01,0x07,0x01,0x07,0x0b,0x04,0x04,0x01,0x07,0x06,0x02,0x09,0x01,0x07,0x01,0x0d,
+ 0x08,0x09,0x09,0x08,0x08,0x11,0x0a,0x07,0x09,0x01,0x07,0x07,0xe5,0x09,0x0b,0x01,
+ 0x02,0x02,0x10,0x06,0x0f,0x01,0x04,0x01,0x05,0xe5,0x01,0x02,0x03,0x04,0x07,0x01,
+ 0x15,0x26,0x03,0x08,0x05,0x01,0x14,0xe9,0x0c,0x12,0xe5,0x08,0x02,0x05,0xe5,0x04,
+ 0x02,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0x01,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0x11,0x07,0x05,0xe6,0x03,0x01,0xe6,0x01,0xe6,0x01,0xe6,0x01,0xe5,0xe5,0xe5,
+ 0x03,0x01,0x02,0x06,0x02,0xe6,0x01,0x1f,0x07,0x04,0x01,0x03,0x0b,0x13,0x01,0x02,
+ 0xe5,0x02,0x04,0x04,0x09,0x01,0x07,0x04,0x04,0x0e,0x04,0x04,0x04,0x09,0x01,0x02,
+ 0x02,0x0f,0x11,0x0a,0x09,0x17,0x02,0x01,0x2c,0xe5,0xe7,0x06,0x19,0x0a,0x02,0x03,
+ 0xe7,0x06,0xe6,0x03,0x02,0xe6,0x05,0x01,0xe5,0x09,0x06,0xe6,0x05,0xe8,0x04,0xe7,
+ 0x05,0x04,0xe5,0x05,0x01,0x06,0x03,0x08,0x06,0x01,0x01,0x03,0xe6,0xe5,0x03,0x09,
+ 0xe5,0x07,0x02,0x16,0x02,0x08,0x0c,0x01,0x01,0x01,0x22,0x02,0x04,0xe5,0x02,0x0c,
+ 0x02,0x0d,0x04,0xe5,0x0c,0x19,0x03,0x06,0x04,0x05,0x07,0x01,0x03,0x05,0x01,0x1e,
+ 0x04,0x01,0x0c,0x08,0xe5,0x05,0x0a,0x0c,0xe5,0xe5,0xe5,0x04,0x27,0x13,0x06,0x09,
+ 0x01,0x28,0x01,0x13,0x14,0x02,0x31,0x09,0x06,0x0f,0x04,0x03,0x01,0xe5,0x02,0x0c,
+ 0xe5,0x04,0x01,0xe5,0xe5,0x06,0xe5,0x08,0x09,0xe5,0x07,0x09,0xe5,0x07,0x07,0x0b,
+ 0x07,0x01,0xe5,0x07,0x0c,0x01,0xe5,0x02,0x01,0x0a,0xe6,0x05,0x09,0x09,0x09,0x02,
+ 0x01,0x04,0x02,0xe5,0x02,0x01,0x01,0xe5,0x01,0x04,0x01,0x01,0x03,0xe5,0x13,0x04,
+ 0xe6,0xe5,0x0c,0x06,0x0c,0x10,0x02,0x09,0x09,0x06,0x02,0x13,0x09,0x06,0x02,0x0f,
+ 0xe5,0xe5,0x12,0x03,0x05,0x02,0x09,0x06,0x03,0x02,0x01,0xe5,0x0b,0x06,0xe5,0x04,
+ 0xe5,0x0a,0xe5,0x02,0x06,0x01,0x02,0x03,0x02,0x14,0x17,0x0c,0xe5,0xe5,0x04,0xe5,
+ 0x01,0x10,0xe5,0x02,0xe5,0x07,0x07,0x17,0x0b,0x02,0xe5,0xe5,0x05,0xe5,0x14,0x0b,
+ 0x03,0xe5,0x01,0x03,0x02,0xe5,0xe5,0xe5,0x01,0x04,0x01,0x0b,0x07,0x09,0x04,0xe5,
+ 0xe7,0x03,0x11,0x1d,0x06,0x02,0x06,0x02,0x09,0x05,0xe5,0x01,0xe5,0x01,0x01,0xe5,
+ 0x01,0x06,0xe5,0xe5,0x08,0x05,0xe5,0x03,0x09,0x09,0x05,0xe5,0x01,0x09,0x06,0x02,
+ 0x09,0x01,0x03,0xe5,0x01,0x01,0x04,0xe5,0xe5,0xe5,0x06,0x13,0x05,0xe5,0x05,0x04,
+ 0xe7,0x15,0x13,0x01,0x09,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x06,0x02,0xe5,0x01,
+ 0xe5,0xe6,0xe5,0x03,0x01,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x06,0x01,0x02,0x06,
+ 0x04,0x01,0x02,0x02,0x09,0x01,0x01,0x02,0x05,0x03,0x17,0x02,0x05,0x04,0x01,0x02,
+ 0x03,0x0c,0x04,0x01,0x06,0xe5,0xe5,0xe6,0xe5,0x13,0x03,0x0f,0x01,0x01,0x05,0x01,
+ 0x02,0x03,0x02,0x02,0x06,0x02,0x04,0x01,0x02,0x01,0x01,0xe5,0xe5,0x01,0x01,0x01,
+ 0xe5,0xe5,0x01,0x06,0x02,0x04,0x01,0x02,0x01,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,
+ 0xe5,0x05,0x02,0x02,0x08,0x04,0xe5,0xe5,0x08,0x07,0x08,0xe5,0x0c,0x05,0x01,0x01,
+ 0x03,0x0b,0x03,0x04,0x04,0x02,0x03,0x01,0x15,0x0e,0x04,0x01,0x09,0x05,0x01,0x01,
+ 0x02,0x04,0x01,0x09,0x02,0x06,0x02,0x01,0x04,0x02,0x04,0x01,0x09,0x0b,0x04,0x04,
+ 0x05,0x01,0x01,0x04,0x02,0x04,0x02,0x03,0x07,0x01,0x02,0x06,0x02,0x02,0x01,0x09,
+ 0x01,0x02,0x04,0x01,0x04,0x0e,0x05,0x07,0x01,0xe5,0xe6,0x15,0x06,0x0c,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x04,0x02,0x01,
+ 0x04,0x04,0x01,0x02,0x04,0x01,0x02,0x06,0x04,0x01,0xe5,0xe5,0xe5,0x01,0x04,0x01,
+ 0x02,0x01,0xe5,0xe5,0x02,0xe5,0x03,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,
+ 0x01,0x02,0x04,0x01,0x01,0xe5,0x03,0x01,0x01,0xe5,0xe6,0x0a,0x0d,0x02,0x02,0xe5,
+ 0x1e,0x2f,0x02,0x06,0x02,0x06,0xe5,0x29,0x07,0xe5,0x09,0x04,0x02,0xe5,0x11,0x09,
+ 0xe5,0x07,0x02,0x03,0x09,0x02,0x01,0x19,0x01,0xe5,0xe7,0x2e,0x20,0xe5,0x07,0x05,
+ 0xe5,0x01,0xe5,0x2e,0x12,0xe5,0x01,0xe5,0x04,0x09,0x04,0x04,0x02,0x06,0x02,0x05,
+ 0xe5,0x07,0xe5,0x01,0x01,0x07,0x11,0x05,0xe5,0x0d,0x09,0x04,0x01,0x02,0x09,0x06,
+ 0x02,0x09,0x09,0x06,0x02,0x04,0xe6,0x01,0xe6,0x06,0x09,0x06,0x02,0x04,0x01,0x04,
+ 0x09,0x04,0x01,0x02,0x09,0xe5,0x07,0x04,0x01,0x02,0x04,0x01,0x02,0x03,0xe5,0xe5,
+ 0x01,0x03,0x05,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0x03,0x05,0x04,0x01,0x06,0x01,
+ 0x01,0xe5,0x1f,0x09,0x06,0x02,0x09,0x10,0x0c,0x09,0x09,0x08,0xe5,0x08,0x15,0x13,
+ 0x09,0x09,0x09,0x12,0xe5,0x05,0x02,0x13,0x04,0x05,0xe5,0x1c,0x09,0x07,0x02,0x09,
+ 0x1e,0x07,0x09,0x09,0x0b,0x02,0x12,0x0f,0x02,0x0a,0x09,0x09,0x0f,0x03,0x05,0x02,
+ 0x12,0x0a,0xe8,0x22,0x04,0x04,0x02,0x01,0x04,0x02,0x06,0x02,0x01,0x02,0x01,0x02,
+ 0x01,0x04,0x02,0x06,0xe7,0xe5,0x03,0x02,0x06,0x02,0x06,0x02,0x01,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x06,0x02,0x06,0xe7,0xe5,0x01,0x01,0x02,0x01,0x02,0x01,0x02,0x01,
+ 0x02,0x01,0x02,0x01,0x04,0x02,0x04,0x01,0xe7,0x03,0x01,0xe5,0xe5,0x03,0x01,0x1a,
+ 0x01,0x14,0x09,0x02,0x02,0x06,0x03,0x05,0x03,0x05,0x03,0x05,0x01,0x01,0x07,0x01,
+ 0x02,0x01,0xe5,0x01,0xe5,0x04,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x09,0x01,0x05,
+ 0x01,0x01,0x01,0x03,0x01,0x01,0x02,0x02,0x01,0xe6,0x04,0x01,0x01,0x01,0x03,0x01,
+ 0x01,0x01,0x03,0x01,0x01,0x01,0xe5,0x01,0x01,0x01,0x01,0x03,0x01,0xe6,0x03,0xe5,
+ 0xe7,0x01,0x02,0x02,0x19,0xe7,0x11,0x0f,0x04,0x04,0x04,0x04,0x09,0x0e,0x04,0x04,
+ 0x05,0x03,0x04,0x04,0x04,0x09,0x04,0x03,0xe5,0xe5,0x03,0x04,0x09,0x35,0xe5,0x01,
+ 0x01,0x04,0x0c,0x01,0x18,0x03,0x15,0xe5,0x07,0xe6,0x06,0xe6,0x04,0xe8,0x04,0xe8,
+ 0x04,0xe7,0x05,0xe8,0x04,0xe7,0x05,0xe8,0x04,0xe8,0x04,0xe8,0x05,0xe6,0x03,0x04,
+ 0xe6,0x01,0x03,0xe8,0xe5,0x03,0xe7,0x01,0x03,0xe6,0x05,0x01,0xe5,0x05,0xe7,0x05,
+ 0x01,0xe5,0x01,0x03,0xe8,0xe6,0x03,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,
+ 0xe5,0xe5,0x19,0x08,0xe5,0x07,0xe5,0x07,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,
+ 0x1e,0x08,0x09,0x09,0x09,0x0a,0x08,0x07,0x01,0xe5,0x17,0xe7,0x20,0x0b,0xe5,0xe6,
+ 0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,
+ 0x01,0xe5,0x03,0x03,0x02,0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0x01,0x01,0x07,
+ 0x03,0x05,0xe5,0x01,0x02,0x02,0x01,0x01,0x03,0x01,0x03,0xe5,0x03,0x03,0xe5,0x03,
+ 0xe5,0x01,0xe5,0x03,0x04,0x01,0x02,0xe5,0x01,0x05,0x04,0x04,0x04,0x01,0x19,0x01,
+ 0xe6,0x18,0x08,0xe5,0x07,0x04,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,0x02,0x04,0xe5,
+ 0x02,0x04,0xe5,0x06,0xe6,0x02,0x03,0xe6,0x02,0x04,0xe5,0x02,0x08,0x02,0x04,0xe5,
+ 0x02,0x04,0xe5,0x08,0x08,0xe5,0x02,0x03,0x01,0x03,0x04,0xe5,0x02,0x03,0x01,0x08,
+ 0xe5,0x03,0x08,0x07,0x01,0xe5,0x16,0x01,0xe6,0x02,0x16,0x06,0x02,0x08,0x03,0x01,
+ 0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,0x01,0xe6,0x04,0x01,0xe5,
+ 0x05,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x04,0x01,0x08,0x01,
+ 0xe5,0x01,0x03,0xe7,0x01,0x03,0xe7,0x05,0xe8,0x05,0xe7,0x04,0xe8,0x06,0x03,0x03,
+ 0x01,0xe5,0x09,0x09,0x01,0xe5,0x17,0x01,0xe5,0x16,0xe5,0xe5,0x0d,0x0b,0xe5,0xe5,
+ 0x02,0x02,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,0x05,0x1d,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x13,0xe5,0x07,0xe5,0x06,0x01,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x10,0x03,0x20,
+ 0x02,0xe5,0x10,0x01,0xe6,0xe5,0x02,0x01,0xe5,0x04,0xe5,0xe7,0x04,0x01,0x07,0x01,
+ 0x02,0x04,0x01,0x07,0x01,0x03,0x03,0x01,0x07,0xe6,0x01,0x04,0x01,0x07,0x01,0x06,
+ 0xe5,0xe6,0x07,0xe6,0xe5,0x04,0x01,0x07,0x01,0x01,0x05,0xe6,0x06,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x01,0x01,0x03,0x01,0x01,0x04,0xe5,0xe5,
+ 0x01,0x04,0x01,0x0b,0xe5,0xe5,0x18,0x09,0xe5,0x01,0x09,0x04,0x09,0x02,0x06,0x02,
+ 0xe5,0x0a,0x01,0x02,0xe5,0x0a,0x01,0x01,0x01,0x02,0x06,0x02,0x06,0x0e,0x03,0x06,
+ 0x06,0xe5,0x04,0x16,0xe5,0x05,0x0b,0xe5,0x08,0x08,0xe5,0x17,0xe5,0xe6,0x14,0x02,
+ 0x06,0xe5,0x04,0x09,0x01,0x07,0x08,0x14,0x12,0x01,0x05,0x04,0x04,0x03,0x0a,0x0c,
+ 0x03,0x05,0xe5,0x02,0x02,0x09,0x07,0x05,0x01,0x0b,0x0a,0x02,0xe5,0x04,0x03,0x03,
+ 0x0c,0x08,0x01,0x01,0xe5,0x19,0x08,0x03,0x09,0x01,0x0e,0x0e,0x0a,0xe5,0xe5,0x05,
+ 0x09,0x03,0x03,0x01,0x06,0x02,0x13,0x08,0xe5,0x03,0x1d,0x0a,0x06,0x01,0x01,0x09,
+ 0x06,0x02,0xe5,0x02,0x09,0x07,0xe5,0x01,0x04,0x03,0x17,0x0a,0xe6,0x06,0xe6,0x01,
+ 0x03,0xe7,0x03,0x02,0xe6,0x05,0x05,0x07,0x02,0x03,0xe6,0x06,0xe6,0x06,0xe6,0x03,
+ 0x02,0xe5,0x01,0x07,0xe6,0x06,0x08,0xe7,0x02,0xe5,0x01,0x01,0xe5,0x05,0x01,0x07,
+ 0x01,0x04,0x06,0x02,0x02,0x01,0x05,0x01,0x01,0x02,0x01,0x04,0x17,0xe5,0xe5,0xe6,
+ 0x01,0x2d,0x15,0x1b,0x01,0x11,0x02,0x08,0x01,0x02,0x09,0x0a,0x07,0x09,0x02,0x04,
+ 0x01,0x02,0x06,0x02,0x03,0x08,0x01,0x02,0x01,0x05,0xe5,0xe5,0xe5,0x02,0x09,0x0f,
+ 0x02,0x01,0x01,0xe5,0x08,0x0e,0x09,0x06,0xe5,0x04,0x03,0x02,0x01,0x04,0x09,0x06,
+ 0x0e,0x04,0x02,0x02,0x06,0x01,0x07,0x05,0x03,0x07,0x05,0xe5,0xe5,0x01,0x07,0x09,
+ 0x09,0x05,0x0d,0x0f,0x03,0x05,0x03,0x03,0x05,0x08,0x0a,0x04,0xe5,0x13,0x01,0x02,
+ 0x02,0xe5,0xe5,0x13,0x01,0x01,0x02,0x0a,0x15,0x04,0x0e,0x04,0x0c,0x0d,0x03,0x02,
+ 0x0f,0x0c,0x03,0xe5,0x0c,0x09,0x01,0x02,0x02,0x09,0x05,0x11,0x09,0x03,0x03,0x06,
+ 0x07,0x11,0x0b,0x0a,0x12,0x03,0x07,0xe6,0x0e,0x0b,0x0c,0x09,0x07,0x08,0x03,0x05,
+ 0x10,0x04,0x23,0x01,0x13,0x0c,0x01,0xe6,0x1f,0x01,0x01,0x04,0xe5,0x07,0x0a,0xe6,
+ 0x03,0x02,0xe5,0x07,0xe7,0x05,0xe8,0x02,0x02,0x08,0x02,0x06,0xe5,0x07,0x01,0xe5,
+ 0x0a,0x0d,0x02,0xe6,0x0b,0xe5,0x0d,0x01,0x09,0x02,0x06,0xe5,0x0d,0x09,0x14,0xe5,
+ 0x02,0x05,0x21,0x15,0x07,0xe5,0x03,0x06,0x07,0x05,0x04,0x05,0x01,0x07,0xe6,0xe5,
+ 0x01,0x01,0x02,0x01,0xe5,0x1e,0x1d,0x17,0x27,0x02,0xe6,0x11,0x05,0x03,0x09,0x09,
+ 0x02,0x03,0x05,0x0d,0x03,0x02,0x01,0x03,0x05,0x03,0x02,0x06,0x05,0x03,0xe5,0x04,
+ 0x05,0x08,0xe5,0x03,0x06,0x03,0x0c,0xe5,0x04,0x03,0x01,0x06,0x03,0x01,0x04,0x04,
+ 0x06,0x09,0x08,0x03,0x0a,0x09,0x07,0x19,0x0b,0xe5,0x08,0x09,0x09,0x01,0x07,0x06,
+ 0x01,0x07,0x0c,0x06,0x01,0x0d,0x06,0x01,0x06,0x02,0x07,0x01,0x09,0x03,0x03,0x01,
+ 0x08,0xe5,0x05,0xe5,0xe5,0x04,0xe5,0x12,0x09,0x15,0x02,0xe5,0xe6,0x01,0x02,0x14,
+ 0x0c,0x13,0x02,0x04,0x10,0x04,0x06,0x13,0x0a,0x01,0x0b,0x06,0x2f,0x05,0x03,0x13,
+ 0x0b,0x0c,0x02,0x03,0x03,0xe5,0xe6,0x08,0xe5,0x04,0xe5,0x12,0xe5,0x07,0x02,0x01,
+ 0x04,0x09,0xe5,0x03,0x0d,0xe5,0xe6,0x01,0x02,0xe5,0x07,0x06,0x03,0x04,0x03,0x02,
+ 0xe5,0x01,0xe5,0x02,0xe5,0x07,0xe5,0x07,0x09,0xe5,0x11,0x09,0xe5,0x07,0x02,0x01,
+ 0x07,0xe5,0xe5,0x02,0x01,0xe5,0x01,0x04,0x01,0x01,0x03,0xe5,0x09,0x04,0xe6,0x02,
+ 0x05,0x01,0x17,0x0a,0x02,0x01,0x0a,0xe5,0xe5,0x05,0x05,0xe5,0x08,0xe5,0xe5,0x01,
+ 0x06,0xe5,0x01,0x05,0x06,0x01,0xe5,0x02,0xe5,0xe6,0x02,0x03,0xe5,0xe6,0xe5,0x02,
+ 0xe5,0x07,0x09,0x05,0x06,0x01,0x04,0x05,0xe5,0x01,0x02,0x01,0x04,0x02,0xe5,0xe7,
+ 0x03,0xe5,0xe7,0x03,0x01,0xe5,0x03,0xe6,0x0d,0x01,0x02,0x01,0xe6,0x03,0x0c,0x27,
+ 0xe5,0x05,0x07,0x06,0x01,0xe5,0xe5,0xe5,0x09,0x06,0x03,0xe5,0x0b,0x0a,0xe5,0x19,
+ 0xe5,0xe5,0xe5,0x03,0xe5,0x16,0x03,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x07,0x01,
+ 0x01,0x05,0x0d,0x07,0x04,0x02,0xe5,0x13,0xe5,0x28,0x09,0x09,0x01,0x03,0xe5,0x01,
+ 0x09,0x09,0x09,0x0b,0x05,0xe5,0x01,0x10,0x02,0x01,0x04,0x16,0x09,0x01,0x04,0xe5,
+ 0xe5,0xe5,0x03,0x02,0x01,0x07,0x10,0xe5,0x04,0x02,0x03,0xe5,0x0a,0x0a,0x09,0x01,
+ 0x02,0x09,0x04,0x01,0x02,0x06,0x02,0x03,0xe5,0x03,0x09,0x09,0xe5,0x01,0x02,0x02,
+ 0xe5,0x01,0x05,0xe5,0x01,0xe5,0x03,0x06,0x04,0x09,0xe5,0x01,0x05,0x02,0x06,0x02,
+ 0x0a,0xe5,0xe5,0x01,0x06,0x02,0x09,0x04,0x01,0x02,0x02,0x01,0x01,0x02,0x03,0xe5,
+ 0x03,0x14,0xe5,0xe5,0xe5,0x01,0x07,0xe6,0x0d,0x02,0x01,0xe5,0xe5,0xe5,0x0e,0x01,
+ 0x01,0x05,0x03,0x02,0xe7,0x02,0x09,0x09,0x05,0x03,0x02,0x01,0x04,0x05,0x03,0x07,
+ 0x03,0x09,0x13,0x05,0x05,0x01,0xe6,0xe5,0xe5,0x04,0x03,0x01,0x02,0x04,0x05,0x01,
+ 0x01,0x02,0x01,0xe5,0x02,0x03,0x01,0x04,0x12,0x04,0x01,0x02,0x1e,0x01,0x0c,0xe6,
+ 0x01,0x01,0x03,0xe5,0x03,0x01,0x05,0x03,0x01,0xe5,0x01,0x01,0x03,0xe5,0x01,0x0b,
+ 0x02,0x04,0x06,0x02,0x0b,0x09,0x06,0x0c,0x01,0x02,0x0e,0x01,0x02,0x01,0x01,0x02,
+ 0x04,0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0x02,0x01,0xe5,0x05,0x12,
+ 0x01,0xe5,0xe5,0x01,0x1e,0x01,0x01,0xe7,0x05,0xe5,0x03,0x01,0x01,0xe5,0x03,0x04,
+ 0x01,0x02,0x04,0x04,0x01,0x01,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0xe6,0x02,0xe5,0xe5,
+ 0x01,0x03,0xe5,0xe8,0x02,0xe5,0x05,0x03,0xe5,0x03,0x03,0xe8,0x04,0xe5,0x03,0x01,
+ 0x01,0xe5,0x0d,0x01,0x01,0xe5,0xe5,0x01,0x03,0xe5,0xe6,0xe5,0xe5,0xe6,0xe8,0xe5,
+ 0xe6,0xe6,0xe5,0xe5,0x01,0xe6,0x01,0x04,0x01,0xe5,0x11,0x01,0x01,0xe6,0x1a,0x02,
+ 0x03,0x09,0x09,0x09,0x04,0x04,0x02,0xe5,0x04,0x04,0x04,0x09,0x02,0x01,0x04,0x02,
+ 0xe5,0x04,0x0b,0x09,0x02,0xe5,0x04,0x02,0x06,0x0c,0x06,0x04,0x04,0x04,0x04,0x09,
+ 0x02,0x01,0x04,0x0e,0x11,0x01,0x01,0xe5,0x1d,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x01,0x03,0xe5,
+ 0x01,0xe5,0x03,0xe5,0x01,0x07,0xe5,0x07,0xe5,0x01,0xe5,0x03,0xe5,0x01,0xe6,0x02,
+ 0xe5,0x08,0x02,0xe6,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x07,
+ 0xe5,0x01,0x13,0xe5,0x01,0xe5,0x0a,0x02,0x04,0x01,0x02,0x02,0xe5,0x04,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe7,0x05,0xe7,0x05,0xe5,0xe5,0x05,0xe5,0x03,0x03,0xe5,0xe6,
+ 0x01,0x02,0xe5,0x07,0xe5,0x03,0x05,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x02,0x01,0x02,
+ 0xe5,0x07,0x09,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe6,0x03,
+ 0x02,0xe5,0x03,0x03,0x04,0x01,0x06,0xe5,0x02,0x0b,0xe5,0x08,0x27,0x30,0xe5,0x1d,
+ 0xe5,0x12,0x09,0x09,0x1a,0x02,0x06,0x09,0x02,0x18,0x05,0xe5,0x0a,0x07,0x11,0x09,
+ 0x09,0x01,0x1b,0x09,0x09,0x03,0x05,0x09,0x06,0x04,0x03,0x05,0x09,0x01,0x07,0x03,
+ 0x07,0x07,0x09,0x09,0x01,0x07,0x0c,0x06,0x16,0xe5,0xe6,0x0e,0x0e,0x02,0x01,0xe7,
+ 0x02,0xe5,0xe8,0x03,0x01,0xe7,0x05,0xe7,0xe5,0x01,0x01,0xe7,0x02,0x02,0xe7,0x05,
+ 0xe7,0x03,0x01,0xe7,0x05,0xe7,0x03,0x01,0xe7,0x02,0x02,0x01,0xe7,0x05,0xe7,0x02,
+ 0xe5,0xe8,0x02,0x02,0xe7,0x0f,0xe7,0x02,0x02,0xe7,0x05,0xe7,0x05,0xe5,0xe5,0x05,
+ 0xe7,0x03,0x01,0x02,0x15,0xe5,0xe6,0x0c,0x02,0x09,0x06,0x01,0xe6,0x04,0x01,0xe6,
+ 0x01,0x02,0x01,0xe6,0x03,0xe5,0x01,0xe5,0x04,0x01,0xe6,0x06,0xe6,0x01,0x02,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x06,0x01,0xe6,0x04,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x02,0xe5,0x08,0x01,0xe5,0x01,0x02,0xe5,0x06,0xe6,0x06,0xe6,
+ 0x04,0x02,0xe5,0x04,0x01,0xe6,0x04,0x01,0xe6,0x16,0x02,0xe5,0x0d,0x03,0xe5,0x01,
+ 0x09,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x02,0x04,0x01,0x04,0x03,0x08,0xe5,
+ 0x13,0x02,0x05,0x0f,0x01,0xe5,0xe5,0x03,0x01,0x04,0x08,0x08,0xe5,0x11,0x01,0x07,
+ 0xe5,0x07,0x01,0x01,0x02,0xe5,0xe5,0x08,0x01,0x02,0x02,0x01,0x18,0x02,0xe5,0x0c,
+ 0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x07,
+ 0xe5,0x01,0x05,0xe6,0x01,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x02,0x03,0xe6,0x01,0x01,
+ 0xe5,0x01,0xe8,0x06,0xe5,0x05,0x01,0xe6,0x04,0xe7,0x07,0xe6,0x04,0xe7,0x01,0x03,
+ 0x01,0xe5,0x01,0x03,0xe8,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,
+ 0x08,0x01,0x0f,0x0a,0x09,0x09,0x09,0x08,0x07,0x01,0xe5,0x07,0xe6,0x07,0xe5,0x04,
+ 0x01,0xe5,0x08,0x06,0x01,0xe5,0x02,0x07,0x10,0x01,0xe6,0x06,0x04,0x02,0x0b,0x09,
+ 0xe6,0x06,0x09,0x0a,0x08,0x18,0xe5,0xe6,0x0c,0x18,0x07,0x01,0x09,0x04,0x04,0x04,
+ 0x01,0x02,0x06,0x02,0x09,0x04,0x01,0xe5,0xe5,0x08,0x04,0x01,0xe5,0xe5,0x02,0x05,
+ 0x01,0x03,0x05,0x03,0xe5,0xe5,0x01,0x03,0xe5,0x03,0xe5,0x01,0x02,0x02,0x03,0xe5,
+ 0x03,0xe5,0x01,0x02,0x02,0x06,0x02,0xe5,0x01,0xe5,0x03,0x04,0x04,0x04,0x01,0x02,
+ 0x16,0xe8,0x0d,0x0a,0x09,0x13,0x08,0x0a,0x08,0x1e,0x11,0x06,0xe6,0x08,0x07,0x01,
+ 0x03,0x05,0x09,0x03,0x04,0xe5,0x02,0x03,0x01,0x03,0x04,0xe5,0x0d,0x06,0x01,0x19,
+ 0xe5,0xe5,0x02,0x09,0x0c,0x24,0x15,0x2c,0x01,0x08,0xe7,0x05,0xe7,0x05,0xe8,0x04,
+ 0x01,0xe5,0x05,0xe8,0x04,0xe7,0x01,0x05,0x03,0x03,0x01,0xe5,0x09,0x09,0x01,0x18,
+ 0x02,0xe5,0x16,0xe5,0xe5,0x03,0x0f,0x03,0x15,0xe5,0xe5,0x0f,0x02,0x10,0x02,0x06,
+ 0x02,0x01,0x06,0xe5,0xe5,0x23,0x27,0xe5,0xe5,0x07,0xe6,0x04,0xe5,0xe5,0x16,0xe5,
+ 0xe6,0x10,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x07,0x01,0x05,0x01,0xe7,0x04,0xe5,0xe5,0x04,0x01,0xe6,0x03,0x02,
+ 0x01,0x05,0x03,0x01,0x07,0xe6,0x06,0xe6,0x06,0x01,0x03,0x03,0x01,0xe5,0x05,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x02,0x01,0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x01,0x04,
+ 0xe7,0x01,0x07,0xe8,0x08,0x0f,0xe5,0x07,0xe5,0x08,0xe5,0xe6,0x03,0xe5,0x01,0x0e,
+ 0xe5,0x01,0x1b,0xe5,0x01,0x05,0x01,0x04,0x02,0x07,0x03,0xe5,0x02,0x04,0x03,0x05,
+ 0xe5,0x06,0xe5,0xe5,0xe5,0x05,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x04,
+ 0x03,0x08,0xe5,0x04,0x0e,0x02,0xe5,0x01,0xe5,0xe5,0x08,0x09,0x01,0x06,0x02,0x01,
+ 0x05,0x01,0x02,0x03,0x02,0xe5,0xe5,0x0c,0x0a,0x06,0x01,0x0a,0x01,0x02,0x01,0x02,
+ 0xe5,0x07,0x01,0x06,0x04,0x04,0x02,0xe5,0x09,0x0a,0x02,0x02,0x0d,0xe5,0xe5,0x05,
+ 0x02,0x02,0xe5,0x01,0x01,0x01,0x01,0x01,0x05,0x01,0x02,0x02,0x01,0x02,0xe5,0xe5,
+ 0xe5,0xe5,0x0f,0x02,0xe7,0xe5,0xe5,0x15,0x0a,0xe5,0x01,0xe5,0x0a,0x09,0x09,0x02,
+ 0x0f,0xe5,0x12,0x06,0x02,0x05,0x01,0x01,0x0b,0x09,0x07,0x01,0xe5,0x07,0x09,0xe5,
+ 0x08,0x09,0x06,0xe5,0x02,0x0e,0x07,0x08,0x0c,0x01,0xe7,0x06,0xe5,0x05,0x08,0x04,
+ 0x02,0x01,0x11,0xe6,0xe5,0x12,0x04,0x05,0x04,0x01,0xe6,0x01,0x07,0x04,0x01,0x11,
+ 0xe5,0x01,0x01,0x05,0x01,0x0a,0x10,0x01,0xe5,0x02,0x12,0xe5,0x04,0x06,0xe5,0x05,
+ 0x01,0x01,0x02,0x1e,0xe5,0xe5,0xe5,0x17,0x0a,0x04,0x01,0x08,0x01,0x07,0x09,0x1b,
+ 0x01,0x1d,0x01,0x01,0x06,0x02,0x01,0x0f,0x0b,0x01,0x03,0x1f,0x08,0x01,0xe5,0x01,
+ 0xe5,0x02,0x07,0x09,0x01,0x09,0xe8,0x11,0x0d,0x05,0x0f,0x04,0x04,0x04,0x04,0x02,
+ 0x01,0xe5,0x02,0x02,0x06,0x01,0x07,0x09,0x03,0xe5,0x03,0x02,0x04,0x03,0x02,0x05,
+ 0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x08,0x09,0x01,0x17,
+ 0x09,0x11,0xe9,0x19,0x09,0x03,0x02,0x02,0x05,0xe5,0xe6,0x02,0x02,0x01,0xe6,0x04,
+ 0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x03,0x03,0x01,0x07,0x01,0x06,0x02,0xe5,
+ 0x03,0x03,0x09,0x09,0x09,0x04,0x01,0xe5,0x0a,0xe5,0x02,0x05,0x01,0x0b,0x07,0x0a,
+ 0x0c,0x01,0x07,0xe5,0xe6,0x02,0x11,0x10,0x06,0x03,0x06,0x02,0x06,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0x01,0x07,0x03,0x05,0xe5,0x04,0x03,0x03,0x05,0x09,0x05,
+ 0x03,0x06,0x02,0x02,0x01,0x09,0x04,0x20,0x20,0xe7,0x07,0x12,0x02,0x03,0x02,0x04,
+ 0xe8,0x02,0x0f,0x02,0x06,0x06,0xe6,0x03,0x02,0xe6,0xe5,0xe5,0xe5,0x15,0x0b,0x0e,
+ 0x01,0x09,0x02,0x0e,0x0e,0x09,0x09,0x06,0x01,0x01,0x04,0x02,0xe5,0x0c,0x0b,0x03,
+ 0x11,0xe5,0x0e,0x09,0x07,0x09,0x11,0x03,0x09,0x05,0x08,0x07,0x07,0x04,0x02,0x03,
+ 0x1d,0x15,0x07,0x09,0x08,0x12,0x01,0x02,0x16,0xe5,0xe6,0xe5,0x0b,0x24,0x02,0x01,
+ 0x07,0x03,0x05,0x09,0x02,0x06,0x06,0x02,0x04,0x04,0x06,0x02,0x06,0x02,0x01,0x09,
+ 0x02,0xe5,0x01,0x02,0x02,0xe5,0x04,0x03,0x01,0x03,0x06,0xe5,0xe5,0x02,0x03,0x01,
+ 0x09,0x04,0x01,0x02,0x04,0x01,0x06,0x09,0xe5,0x13,0xe7,0x0e,0x01,0x14,0x0e,0x01,
+ 0x02,0x02,0x01,0x01,0x07,0x01,0x05,0x01,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x03,0x01,0x01,0xe5,0xe5,0x01,0x05,0x02,0x02,0x02,0xe5,0x01,0x05,0xe5,0x01,
+ 0x03,0x01,0xe5,0x01,0x03,0x01,0xe5,0x01,0x06,0x02,0x06,0xe5,0xe5,0x04,0xe5,0x06,
+ 0x01,0xe5,0x07,0xe5,0x17,0x09,0xe5,0xe5,0x01,0x02,0x0a,0x02,0x21,0x09,0x09,0x09,
+ 0x03,0x05,0x08,0xe5,0x08,0x09,0x0d,0x09,0x09,0x04,0x04,0x01,0x07,0x02,0x05,0x0a,
+ 0x01,0x06,0x05,0x02,0x0a,0x03,0x22,0xe5,0xe5,0x06,0xe5,0x04,0xe6,0x1b,0x05,0x03,
+ 0x05,0x09,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x05,0xe5,0x01,0x03,0x07,0x03,
+ 0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x02,0xe5,0xe5,0x04,0xe5,0x01,
+ 0x03,0x02,0xe5,0xe5,0x02,0x09,0x0f,0x02,0xe5,0x04,0x02,0xe5,0x04,0x0e,0x01,0xe5,
+ 0x01,0xe5,0x02,0x05,0xe5,0xe6,0x1e,0x08,0x01,0x01,0xe5,0x03,0x09,0x01,0x01,0xe5,
+ 0x03,0xe5,0x02,0xe5,0x02,0xe5,0x07,0x01,0x01,0xe5,0x03,0x03,0xe5,0x03,0xe5,0x09,
+ 0xe5,0x01,0xe5,0x03,0x09,0x09,0xe5,0xe5,0x05,0x04,0x01,0x02,0x09,0xe5,0x02,0x01,
+ 0x01,0xe6,0x0f,0x01,0xe5,0x05,0x03,0x05,0x0b,0x01,0x04,0xe6,0xe5,0x01,0x0a,0x01,
+ 0x1e,0x01,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x02,0x01,0x04,
+ 0x04,0x04,0x02,0x01,0x06,0x04,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x04,0x04,0x02,
+ 0x01,0x04,0x01,0xe5,0xe5,0x03,0x02,0x01,0x02,0x04,0x0b,0xe5,0xe5,0xe5,0x01,0x04,
+ 0x09,0x06,0xe5,0x02,0x04,0x01,0x01,0x0d,0x24,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0x02,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x0f,0x02,0x01,0x07,0x09,0x06,0x06,0x02,
+ 0xe6,0xe6,0x08,0x01,0x02,0x16,0x04,0x01,0x02,0x06,0x02,0xe5,0x01,0x02,0x02,0xe5,
+ 0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x06,0x02,0x01,0x01,0x02,0x02,0x06,0x02,0x01,
+ 0x01,0x02,0x02,0xe5,0x01,0x04,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x01,0x02,0x02,0x04,0x04,0x09,0x02,0x01,0x08,
+ 0xe5,0x08,0x07,0x07,0xe7,0xe5,0x08,0x02,0xe5,0x02,0x01,0x02,0x14,0x01,0x01,0x05,
+ 0x03,0x05,0x03,0x02,0x01,0xe5,0x02,0x04,0xe5,0x02,0x05,0x03,0x05,0x03,0x05,0x03,
+ 0x05,0x03,0x07,0x03,0x05,0x03,0x02,0x01,0xe5,0x02,0x02,0xe7,0x02,0x02,0xe7,0x02,
+ 0x02,0xe7,0x02,0x01,0x02,0xe5,0x02,0x05,0x03,0x0f,0x01,0x01,0x03,0x01,0x03,0x05,
+ 0x03,0x09,0x04,0x01,0x0f,0x16,0x01,0x02,0x01,0x07,0x03,0xe5,0x03,0x06,0x01,0xe5,
+ 0x02,0x03,0x01,0x09,0x03,0x05,0x09,0x03,0xe5,0xe5,0x01,0x0b,0x04,0x04,0x09,0x09,
+ 0x04,0x04,0x05,0xe5,0x01,0x04,0xe6,0x01,0x0b,0x0e,0x01,0xe5,0xe5,0x06,0x04,0x04,
+ 0x09,0xe5,0x03,0x01,0xe7,0xe6,0x09,0x17,0xe5,0xe8,0xe5,0xe6,0xe5,0xe5,0x01,0x02,
+ 0x01,0x01,0x02,0x01,0xe7,0x03,0x02,0x01,0x01,0x02,0x01,0xe5,0x05,0x02,0x06,0x01,
+ 0xe5,0xe5,0xe5,0x01,0x02,0x01,0xe6,0x01,0x01,0xe5,0x07,0x01,0xe5,0xe5,0x03,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0xe5,0xe6,0xe5,0x06,0x09,0x09,0x0a,0xe5,0x11,
+ 0x09,0x02,0x03,0x09,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x05,
+ 0x02,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x0c,0xe5,0x1b,0x01,0xe5,0xe5,0x09,0x09,
+ 0x01,0x07,0xe5,0x03,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x06,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0x2d,0xe6,0x06,0x02,0x02,0x05,
+ 0x03,0x09,0xe5,0x07,0xe5,0x01,0x02,0xe5,0xe7,0xe5,0x02,0x01,0xe5,0xe5,0x03,0x01,
+ 0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,
+ 0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0x02,0x06,0x02,0x06,0x06,
+ 0x06,0xe5,0x01,0xe5,0x08,0x02,0x24,0x02,0xe5,0x08,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x2d,0x02,0x04,0x04,0x01,0x09,0x1b,0x09,
+ 0x03,0x01,0x09,0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,
+ 0x02,0x06,0x02,0xe5,0x05,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x08,0x21,0x08,
+ 0xe5,0x01,0x0d,0x01,0x07,0x01,0x06,0xe5,0xe8,0x03,0x01,0xe7,0x05,0xe7,0x03,0x02,
+ 0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x02,0xe5,0x01,0x01,0x04,0x02,0xe6,0x03,0x02,
+ 0x01,0x04,0x02,0x01,0x03,0x02,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,
+ 0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,0x02,0x01,0x06,0xe5,0xe5,
+ 0x03,0x01,0x04,0x1d,0xe5,0x01,0x0d,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,
+ 0x01,0xe6,0x04,0x02,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x04,0x02,0xe5,0x04,
+ 0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x06,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x03,0x02,0xe6,0x04,0x01,0xe5,0x20,0x03,0xe5,0x08,0x02,0x01,0x0e,
+ 0x02,0x01,0xe5,0x02,0x06,0x02,0x06,0x04,0x02,0x04,0x04,0x01,0x07,0x04,0x04,0x09,
+ 0x01,0x02,0x04,0x09,0x08,0x02,0x01,0x07,0x04,0x04,0x09,0x09,0x06,0x02,0x01,0x07,
+ 0x09,0x09,0x09,0x23,0x01,0xe5,0x0c,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x05,
+ 0x01,0xe5,0x06,0xe6,0x01,0xe5,0x01,0x01,0xe5,0x01,0x04,0xe6,0x01,0xe5,0x01,0x01,
+ 0xe5,0x01,0x03,0xe7,0x01,0x03,0x01,0xe5,0x01,0x04,0xe6,0x01,0x05,0xe5,0x03,0x03,
+ 0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0x01,0xe5,0x01,0xe5,0x01,0xe7,0x01,0xe5,
+ 0x01,0x01,0xe5,0x01,0x03,0xe7,0x01,0xe5,0x01,0x01,0xe5,0x01,0x03,0xe7,0x01,0x03,
+ 0xe7,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x0c,0x01,0xe5,0x05,0x01,
+ 0x0a,0x06,0x01,0xe5,0x04,0xe5,0xe5,0x05,0x02,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x04,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x07,0x06,0x02,0xe5,
+ 0x04,0xe5,0x0b,0x17,0xe5,0xe6,0x0c,0x01,0x07,0x01,0x0c,0x04,0x01,0x02,0x02,0xe6,
+ 0xe5,0x01,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,
+ 0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x03,0x04,
+ 0x02,0xe5,0xe6,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0xe5,0xe6,0x01,
+ 0x02,0x02,0xe5,0x01,0x02,0xe5,0xe6,0x01,0x02,0x02,0x03,0x02,0xe5,0xe6,0x01,0xe5,
+ 0xe5,0xe6,0xe5,0x0b,0x17,0x01,0x01,0x09,0x03,0x01,0xe5,0x12,0x09,0x02,0x01,0x01,
+ 0x06,0xe5,0xe5,0x01,0x02,0x01,0x01,0x06,0xe5,0xe5,0x01,0x02,0x01,0x01,0x05,0xe6,
+ 0xe5,0x04,0x01,0x01,0x06,0xe5,0xe5,0x09,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x02,0xe6,
+ 0xe5,0x01,0x02,0x01,0x01,0x02,0x03,0xe5,0xe5,0x01,0x02,0x01,0x01,0x02,0x03,0xe5,
+ 0xe5,0x01,0x02,0x01,0x01,0x06,0xe5,0x02,0x03,0x28,0x02,0xe5,0x01,0x0a,0x02,0x20,
+ 0xe5,0x03,0x03,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,
+ 0x01,0x06,0x02,0x05,0xe5,0x01,0x06,0x04,0x05,0xe5,0x01,0x05,0x03,0x06,0x02,0x05,
+ 0xe5,0x01,0x06,0x02,0x05,0xe5,0x01,0x09,0x05,0x05,0x04,0x0f,0x17,0x02,0xe6,0x41,
+ 0x1d,0x6b,0x02,0xe5,0x0e,0x02,0x07,0x01,0x06,0xe5,0xe5,0x10,0x11,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x06,0xe5,0xe5,0xe5,0x04,0x01,
+ 0xe6,0x04,0x01,0x07,0x01,0x07,0xe6,0x01,0x04,0x01,0x01,0x07,0xe6,0xe5,0x04,0xe6,
+ 0xe5,0x04,0xe6,0x06,0x01,0x01,0x05,0xe6,0x01,0x04,0xe6,0x06,0x01,0x04,0x02,0x01,
+ 0x01,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x0a,0x01,0x01,0x02,0x0c,0xe5,
+ 0x04,0x0c,0xe5,0xe5,0x05,0xe5,0x01,0x05,0xe5,0x02,0x05,0x01,0x03,0x02,0x03,0xe5,
+ 0x04,0x01,0x06,0xe5,0xe5,0xe5,0x04,0x02,0x02,0x02,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,
+ 0xe5,0x02,0x02,0x0a,0x08,0xe5,0x02,0x04,0xe5,0x01,0xe5,0x03,0xe5,0x02,0x04,0xe5,
+ 0x07,0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x05,0x05,0x05,0x08,0x13,0xe5,0x0c,
+ 0x02,0x0e,0xe5,0xe5,0x03,0x02,0x01,0x03,0x02,0x01,0xe5,0x01,0x03,0xe5,0x0d,0x03,
+ 0xe5,0x03,0x04,0x07,0x02,0x03,0x05,0x06,0x01,0x10,0x03,0x01,0x02,0x06,0x05,0x01,
+ 0x01,0x03,0x03,0x01,0x09,0x03,0x01,0x03,0xe5,0x03,0x02,0x03,0x04,0xe5,0xe5,0x0f,
+ 0x1a,0xe6,0x01,0x0e,0x19,0x07,0x07,0x05,0x05,0x06,0x06,0x0b,0x03,0x03,0x09,0x01,
+ 0x09,0x03,0x08,0x13,0x09,0x09,0x09,0x13,0x1a,0x02,0x06,0x11,0xe5,0x01,0xe5,0x0b,
+ 0x05,0x0d,0x01,0x0a,0x08,0x02,0x09,0x01,0x04,0x07,0x01,0x04,0x04,0x09,0x02,0x01,
+ 0x04,0x05,0x03,0xe5,0x05,0x03,0x07,0x01,0x05,0x01,0x01,0xe5,0x03,0x07,0x03,0x01,
+ 0xe5,0x05,0x10,0x02,0x10,0x25,0xe6,0xe7,0x0e,0x12,0xe5,0x0f,0x10,0x0b,0x02,0x01,
+ 0x01,0x0c,0x0c,0x10,0x01,0x0a,0x02,0x06,0xe5,0xe5,0x05,0x06,0x01,0x01,0x01,0x0a,
+ 0x05,0x06,0x02,0x02,0x05,0x13,0x1c,0xe5,0x01,0xe5,0x07,0x27,0x03,0xe7,0x06,0xe5,
+ 0x04,0x01,0x06,0x08,0x03,0x06,0x01,0xe5,0x04,0x04,0xe5,0x06,0x01,0x03,0x03,0x01,
+ 0x03,0x01,0x03,0xe6,0x02,0xe5,0x02,0xe5,0x11,0xe5,0x02,0x04,0xe5,0x02,0x08,0x14,
+ 0x01,0x1d,0x06,0xea,0x39,0x04,0x01,0x0b,0xe5,0x0b,0x06,0xe5,0x02,0x09,0x01,0xe5,
+ 0x06,0x0d,0x06,0x01,0x02,0x04,0x01,0xe5,0x0b,0x03,0x01,0xe5,0x05,0x01,0x20,0x11,
+ 0x04,0x12,0xe5,0x01,0x08,0x02,0x23,0x0c,0x13,0x07,0x03,0x07,0x02,0x08,0x05,0x0e,
+ 0x19,0x09,0xe5,0x07,0xe5,0xe5,0x05,0x02,0x0b,0x2d,0x01,0x0a,0x02,0x1b,0x03,0x04,
+ 0x06,0x03,0x01,0x01,0x04,0x02,0x09,0x01,0xe5,0x04,0xe5,0x01,0x08,0x01,0x08,0x03,
+ 0x02,0x01,0x05,0x03,0x04,0x02,0x01,0x01,0xe5,0x02,0x0c,0x01,0x05,0x09,0x01,0x07,
+ 0x01,0x09,0x07,0x04,0x0a,0xe5,0x0b,0xe5,0x08,0x19,0x06,0x24,0x07,0x05,0x03,0xe5,
+ 0x0e,0x08,0x05,0x0d,0x02,0x09,0x06,0x03,0x01,0x09,0x08,0x13,0x29,0x03,0x2c,0x02,
+ 0xe6,0xe5,0x16,0x03,0x05,0x09,0xe5,0x09,0x0c,0xe5,0xe6,0x01,0x05,0x01,0x08,0x02,
+ 0xe5,0xe5,0x04,0x04,0x01,0x02,0xe5,0x01,0x02,0x02,0x09,0x02,0x03,0x01,0xe5,0x04,
+ 0x05,0x03,0x06,0x02,0x09,0x06,0x06,0x06,0x01,0x08,0x07,0x02,0x23,0xe7,0xe5,0x07,
+ 0x37,0x08,0x08,0x01,0x08,0x0a,0x08,0x0a,0x11,0x03,0x06,0x01,0x09,0x07,0x01,0xe5,
+ 0x0f,0x01,0xe5,0x16,0x04,0x23,0x02,0x1d,0x2c,0x14,0x12,0x08,0x08,0x01,0x20,0x3c,
+ 0x21,0x02,0xe7,0x28,0x03,0xe5,0x07,0x09,0x09,0x09,0x07,0x01,0x09,0x0a,0x08,0xe5,
+ 0xe5,0xe5,0x03,0x01,0x09,0x07,0x01,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x01,0x02,
+ 0xe5,0x26,0x01,0x01,0xe6,0x01,0x01,0x0f,0xe5,0x14,0x03,0xe5,0x07,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x05,0x03,0x09,0x0b,0xe5,0x02,0x05,0xe5,0x01,0xe6,0x07,0x03,0x09,
+ 0x06,0x02,0x05,0x03,0x09,0x05,0xe5,0x01,0x06,0x02,0x01,0xe5,0x04,0x26,0x01,0x03,
+ 0x01,0xe5,0x03,0x26,0x09,0x0b,0x03,0xe5,0x01,0x01,0x04,0x01,0xe5,0xe5,0x03,0x01,
+ 0x02,0xe5,0x02,0x01,0x02,0x07,0x0b,0x01,0x09,0x01,0x0f,0x05,0xe5,0x01,0x01,0x11,
+ 0x09,0x09,0x01,0x03,0xe5,0x01,0x01,0x22,0x01,0x02,0x04,0xe5,0xe6,0x2a,0x09,0x10,
+ 0x02,0x09,0x09,0xe7,0x02,0x04,0x04,0xe5,0xe5,0x13,0xe5,0x08,0x05,0xe5,0x01,0x09,
+ 0x09,0x06,0xe5,0xe5,0x04,0xe5,0x01,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0xe5,0x21,0x06,
+ 0x02,0x01,0x01,0x2b,0x0b,0x02,0x04,0x01,0x02,0x02,0x03,0x02,0x03,0x02,0x02,0x07,
+ 0x01,0x02,0x01,0x0b,0x02,0x04,0x01,0x02,0x08,0x02,0x06,0x09,0x02,0x06,0x02,0x01,
+ 0x01,0x02,0x02,0x06,0x02,0x06,0x02,0xe5,0x01,0x02,0x03,0x02,0x05,0x20,0x07,0xe6,
+ 0xe6,0x01,0x28,0x03,0x07,0x02,0x04,0x04,0xe5,0x01,0x05,0xe5,0xe6,0x04,0xe5,0x01,
+ 0xe5,0x03,0x01,0x01,0xe5,0x0a,0x02,0x04,0x04,0xe5,0x01,0x02,0x03,0x02,0x01,0xe5,
+ 0xe5,0x03,0x01,0x02,0x02,0x09,0x04,0x01,0x02,0x06,0x02,0x04,0x04,0x03,0x09,0x04,
+ 0x27,0x02,0xe8,0x01,0x11,0x01,0x14,0x04,0x04,0x01,0x07,0x01,0x02,0x04,0x01,0x07,
+ 0x01,0x09,0x02,0x04,0x01,0x02,0x04,0x01,0x03,0xe5,0x01,0x01,0x0b,0x01,0x02,0x04,
+ 0x07,0x01,0x07,0x01,0x09,0x02,0x04,0x01,0x07,0x04,0x02,0x01,0x01,0x05,0x01,0x01,
+ 0x01,0x29,0x01,0xe7,0x01,0x11,0x01,0x14,0x04,0x04,0x01,0x02,0x04,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x04,0x06,0x04,0x01,
+ 0xe7,0xe5,0x01,0x04,0x01,0x02,0x04,0x04,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x04,
+ 0x04,0x04,0x04,0x01,0x02,0x2b,0xe6,0xe5,0x06,0x27,0x02,0x06,0x02,0x06,0x02,0x10,
+ 0x13,0xe5,0x1a,0x0c,0x27,0x09,0xe5,0x07,0xe5,0x04,0x0c,0xe5,0x1b,0xe5,0x01,0xe5,
+ 0x09,0x01,0x22,0x16,0x13,0x01,0x03,0xe5,0x08,0x1e,0xe5,0x08,0x02,0x01,0x27,0x07,
+ 0x06,0x08,0xe5,0x0b,0xe5,0x1b,0xe9,0x07,0x05,0x09,0x09,0x09,0x04,0x01,0x02,0x09,
+ 0x04,0xe6,0x01,0x09,0x03,0x02,0x02,0xe6,0x06,0x09,0x06,0x02,0x04,0x01,0x04,0xe6,
+ 0x06,0x04,0xe6,0x01,0x04,0x01,0x02,0x09,0x09,0x09,0x03,0x05,0x09,0xe7,0x02,0x02,
+ 0x09,0x09,0x04,0x01,0x06,0xe6,0x01,0x02,0x27,0x09,0x09,0x09,0x12,0xe5,0x08,0x09,
+ 0x08,0xe5,0x08,0x15,0x09,0x13,0x24,0x02,0x1d,0x04,0x03,0xe5,0xe5,0x28,0x05,0x01,
+ 0x09,0x09,0x15,0x09,0x09,0x07,0x0b,0x02,0x10,0x0b,0x13,0x26,0x1e,0x08,0x01,0x01,
+ 0x01,0x08,0x22,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0xe7,0x05,0x02,
+ 0x06,0x02,0x06,0x02,0x08,0xe5,0xe5,0x03,0x01,0x02,0x01,0x04,0x02,0x01,0x04,0x02,
+ 0x01,0x02,0x01,0x02,0x04,0x01,0x02,0x01,0x02,0x01,0x02,0x04,0x01,0x02,0x04,0x01,
+ 0xe5,0xe5,0x03,0x01,0x23,0xe5,0xe5,0x2a,0x03,0x02,0x02,0x03,0x05,0x03,0x05,0x03,
+ 0x07,0x01,0x08,0xe5,0x04,0x03,0x01,0x03,0x03,0x05,0x03,0x07,0x02,0xe5,0x01,0x02,
+ 0x01,0x01,0x01,0x03,0x03,0x02,0x04,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x02,0x02,
+ 0x01,0x01,0x02,0x02,0x01,0x01,0x01,0x03,0x01,0xe6,0x04,0x01,0xe5,0x21,0xe5,0xe5,
+ 0x13,0x18,0x09,0x03,0x05,0x09,0x03,0x05,0x03,0x05,0xe5,0x07,0x09,0x03,0x05,0x08,
+ 0x02,0x0e,0x04,0x09,0x03,0xe5,0x11,0x0f,0x04,0x02,0x01,0x07,0x01,0x22,0xe8,0x14,
+ 0xe5,0x07,0xe5,0x07,0xe6,0x04,0xe8,0x04,0xe8,0x04,0xe8,0x04,0xe7,0x01,0x03,0xe7,
+ 0x06,0xe7,0x04,0xe8,0x04,0xe8,0x05,0xe6,0x01,0x05,0xe7,0x06,0xe7,0x04,0xe7,0x01,
+ 0x03,0x01,0xe5,0x05,0xe7,0x05,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0xe8,0xe5,0x04,
+ 0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x0f,0xe5,0x18,0x01,0xe5,
+ 0x05,0x01,0x07,0x01,0x09,0x07,0x01,0x09,0x07,0x01,0x09,0x09,0x0b,0xe6,0xe6,0x03,
+ 0x09,0x09,0x09,0x09,0x09,0x1b,0x01,0x25,0xe5,0x2a,0x01,0xe5,0xe6,0x01,0xe5,0xe5,
+ 0x01,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x01,0x02,0x02,0xe5,0x01,0xe5,0xe5,0x01,0xe5,
+ 0x01,0x05,0x03,0xe5,0xe5,0x01,0x01,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0x01,0x01,
+ 0x02,0x04,0x03,0x02,0x02,0x03,0x02,0x02,0xe5,0x01,0xe5,0x03,0x03,0x02,0x02,0xe5,
+ 0x01,0xe5,0x03,0x03,0x02,0x02,0xe5,0x07,0xe5,0x01,0x05,0x04,0x01,0x24,0xe6,0x31,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x06,0x01,0x03,
+ 0x04,0xe5,0x02,0x08,0x02,0x05,0x03,0x04,0xe5,0x02,0x04,0xe5,0x02,0x03,0x01,0x03,
+ 0x04,0xe5,0x02,0x03,0x01,0x03,0x05,0x03,0x04,0xe5,0x0a,0x24,0x01,0xe6,0x0f,0x09,
+ 0x16,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0xe7,0x01,0x03,0x01,0xe5,0x01,0x04,0x01,0x02,0x05,0x01,0xe5,
+ 0x01,0x03,0x01,0xe5,0x01,0x03,0xe8,0x05,0xe6,0x01,0x03,0xe8,0x05,0xe6,0x01,0x03,
+ 0x01,0x03,0x03,0x01,0xe5,0x09,0x01,0x23,0xe8,0x01,0x27,0xe5,0xe5,0x05,0xe5,0xe6,
+ 0x04,0xe5,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x03,0x0d,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe6,0x04,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x13,0x1d,0x03,0x02,0x06,0x04,0x05,0x01,0x07,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0xe6,0x04,0x01,0x07,0xe7,0x05,0x01,0x02,0x04,0xe6,
+ 0xe5,0x04,0xe6,0xe5,0x04,0x01,0x02,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x06,0x01,0x01,
+ 0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,0x03,0x02,
+ 0x01,0xe5,0xe5,0x02,0xe5,0xe5,0x01,0x04,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x0d,0xe5,0x15,0x15,0xe7,0x05,0xe6,0x06,0xe7,0x06,0xe5,0x01,0x05,0xe6,0x06,0xe6,
+ 0x06,0xe5,0x01,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe6,0x05,0xe6,0x02,0xe5,
+ 0x01,0xe6,0x06,0xe6,0x01,0x04,0xe6,0x06,0xe6,0x07,0xe5,0x06,0xe6,0x08,0x2d,0xe7,
+ 0x06,0x24,0x09,0xe5,0x07,0x05,0x03,0x03,0x01,0x03,0x09,0x06,0x02,0x02,0xe5,0xe5,
+ 0x09,0x0d,0xe5,0x05,0x02,0x06,0x02,0x02,0x03,0x02,0x09,0x02,0x06,0x05,0x03,0x02,
+ 0x06,0x07,0x03,0x04,0x04,0x04,0x11,0x08,0xe5,0xe5,0xe5,0xe5,0x08,0x05,0x02,0x0f,
+ 0x06,0x09,0x09,0x05,0x03,0x06,0x02,0x09,0x08,0xe5,0x07,0x0f,0x05,0x0a,0x05,0x03,
+ 0x07,0x01,0x03,0x02,0x02,0x03,0x05,0x09,0x09,0x0f,0x13,0x14,0xe5,0x01,0xe5,0x29,
+ 0xe6,0x05,0xe7,0x06,0xe6,0xe5,0x01,0x02,0x01,0x07,0x01,0xe5,0x08,0x02,0x03,0x01,
+ 0x04,0x02,0xe6,0x05,0xe7,0x06,0xe5,0x02,0x06,0xe6,0x06,0xe6,0x06,0xe7,0x05,0xe6,
+ 0x06,0xe7,0x05,0xe6,0x03,0x02,0xe6,0x06,0x01,0x0a,0x04,0x0f,0x0b,0xe7,0xe5,0x1e,
+ 0x1b,0x0d,0x02,0x02,0x01,0x01,0x02,0x03,0x09,0x02,0x02,0x02,0x13,0x20,0x08,0x09,
+ 0x17,0x07,0x19,0x14,0x01,0xe5,0xe7,0x07,0x1a,0x06,0x02,0x05,0xe5,0xe5,0x03,0x02,
+ 0x05,0x13,0x05,0x03,0x05,0x07,0x05,0x03,0x09,0x03,0x03,0xe5,0x01,0xe6,0x02,0x03,
+ 0x01,0x03,0x03,0x07,0x01,0x01,0x07,0x09,0x02,0x1c,0x21,0x01,0x02,0x0a,0x34,0x01,
+ 0xe5,0x02,0x07,0xe5,0x05,0x06,0x02,0x06,0xe5,0x02,0x08,0x02,0x0d,0xe5,0x03,0x04,
+ 0x02,0x06,0x02,0x10,0xe5,0x06,0x17,0x10,0x0f,0x15,0xe7,0x01,0x12,0x22,0x14,0xe5,
+ 0x08,0x10,0x04,0x0b,0x07,0x02,0x0a,0x02,0x02,0x13,0x06,0x01,0xe5,0x09,0xe5,0x0f,
+ 0x11,0xe5,0xe5,0x08,0x15,0x01,0x01,0x2b,0xe6,0x0d,0x01,0x0a,0xe5,0x07,0x01,0x05,
+ 0x01,0xe8,0x03,0xe6,0x02,0x05,0x04,0xe5,0x04,0x02,0x03,0xe7,0x08,0x08,0xe5,0x24,
+ 0x09,0x07,0x05,0x2b,0x01,0xe6,0x07,0x23,0x0e,0x0c,0xe6,0x03,0x0e,0x08,0xe5,0x09,
+ 0x11,0x04,0x07,0x08,0x01,0x18,0xe5,0x11,0x0b,0x2f,0xe9,0x3c,0x11,0x0a,0x03,0x06,
+ 0xe5,0xe6,0x07,0xe5,0x01,0x09,0x06,0xe5,0x0f,0x02,0x03,0x02,0x09,0x06,0x0f,0x15,
+ 0x02,0x01,0xe5,0xe5,0x03,0x1d,0xe5,0xe6,0x37,0x02,0x09,0x06,0x01,0xe5,0x07,0x03,
+ 0x02,0x02,0x07,0xe5,0xe5,0x03,0xe5,0xe6,0x07,0x09,0x05,0x05,0x01,0x05,0x0a,0x13,
+ 0x02,0x0b,0x15,0x01,0x22,0xe5,0xe6,0x01,0x06,0x25,0x13,0x0c,0x0f,0xe5,0x08,0x07,
+ 0x12,0x03,0x0c,0x06,0x20,0x03,0x03,0x09,0x01,0x02,0x1a,0x14,0xe6,0xe5,0xe5,0xe5,
+ 0x08,0x10,0xe5,0x17,0x03,0xe5,0x03,0x14,0x09,0xe5,0x0d,0x03,0x05,0x0f,0xe5,0x06,
+ 0xe5,0x08,0x01,0xe5,0x04,0xe5,0x01,0xe5,0x03,0xe5,0x08,0x05,0x09,0x06,0xe5,0x1e,
+ 0x0c,0x01,0x01,0x03,0xe5,0x0b,0x10,0xe5,0x19,0x15,0x01,0x04,0x06,0x01,0x01,0x0e,
+ 0x03,0x05,0x06,0xe5,0x01,0x01,0x02,0x08,0x07,0x01,0x03,0xe5,0xe6,0x0e,0x01,0x15,
+ 0xe5,0x02,0xe5,0x06,0x18,0x0d,0x03,0x01,0xe5,0xe5,0x0a,0x45,0x01,0x02,0xe6,0x03,
+ 0x11,0x09,0x06,0x01,0x01,0x02,0x02,0x04,0x01,0x04,0x01,0x02,0x07,0x01,0x01,0x09,
+ 0x09,0x05,0x0b,0x07,0x01,0x1b,0x0b,0x05,0xe5,0xe6,0x03,0x07,0x45,0x01,0x1b,0x09,
+ 0x15,0x01,0x04,0xe5,0x07,0x02,0x01,0x22,0xe5,0x02,0x04,0xe5,0xe5,0xe5,0x02,0xe5,
+ 0x15,0x0d,0x01,0xea,0x0b,0x27,0x01,0x07,0x01,0x0c,0x09,0x09,0xe5,0x01,0xe5,0xe5,
+ 0x01,0x04,0x04,0x04,0x04,0x0b,0xe5,0x01,0xe5,0xe5,0x0b,0x01,0xe6,0x01,0x04,0x01,
+ 0xe5,0xe5,0x0b,0x04,0x05,0x02,0xe5,0xe5,0x01,0xe5,0x01,0x05,0x06,0x11,0x0f,0xea,
+ 0x0b,0x03,0x23,0x01,0x01,0x05,0x01,0x01,0x13,0x09,0x05,0x01,0x01,0x05,0x03,0x05,
+ 0x03,0x0b,0x05,0x01,0x01,0x09,0x04,0xe5,0x02,0x02,0x01,0xe5,0xe5,0xe5,0x10,0x09,
+ 0x02,0x08,0x07,0x11,0x03,0x09,0x01,0xe5,0xe5,0xe5,0x0c,0x27,0x01,0x04,0x01,0xe5,
+ 0xe5,0x01,0x01,0x01,0x07,0x02,0x01,0x02,0x06,0x03,0xe5,0x01,0x01,0x04,0x02,0x09,
+ 0x03,0x09,0x07,0x01,0x02,0xe6,0x03,0x02,0xe7,0xe5,0xe5,0x03,0x02,0x01,0x0c,0x04,
+ 0x09,0x01,0x07,0x01,0x01,0x02,0x16,0x05,0xe5,0x07,0xe7,0xe6,0x0b,0x27,0x01,0x04,
+ 0x01,0xe5,0xe5,0x03,0x01,0x04,0xe5,0xe8,0xe5,0xe6,0x05,0x01,0xe5,0xe5,0x01,0x01,
+ 0x01,0xe5,0xe8,0x02,0xe5,0xe5,0x01,0x0d,0x01,0xe5,0x03,0x01,0x03,0xe5,0x03,0x01,
+ 0xe5,0xe5,0xe6,0xe5,0x03,0xe7,0xe5,0x0a,0xe7,0x03,0x09,0x07,0x01,0x02,0xe7,0x14,
+ 0x06,0x06,0x01,0x01,0x01,0xe5,0x4b,0x09,0x09,0x02,0xe6,0x03,0x09,0x04,0x10,0x02,
+ 0x02,0x0d,0x02,0x09,0x10,0x02,0xe5,0x07,0x10,0x22,0x06,0x02,0xe5,0xe5,0x45,0x05,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x13,0xe5,0x01,0x0f,0xe5,
+ 0x03,0x07,0xe6,0x03,0x08,0xe5,0x01,0x06,0x04,0x0d,0xe5,0x08,0x21,0xe5,0xe6,0x0d,
+ 0x09,0x09,0x09,0x09,0x09,0x02,0x02,0x03,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0x0b,0xe5,0x03,0x03,0x06,0x02,0xe5,0xe5,0xe5,0xe5,0x01,0x09,0x09,
+ 0xe5,0x03,0xe5,0x01,0x09,0x09,0xe7,0xe5,0xe5,0x01,0x09,0x09,0x06,0x06,0xe5,0xe7,
+ 0x5a,0xe5,0x32,0x08,0xe5,0x08,0x1a,0x02,0x09,0x09,0x09,0x1c,0xe5,0x03,0x03,0xe7,
+ 0x4c,0x09,0x03,0x05,0x09,0x09,0x15,0x03,0x09,0x05,0x03,0x0f,0x09,0x01,0x09,0x0b,
+ 0x09,0x1c,0x09,0x01,0x01,0x0d,0x01,0x18,0x09,0x09,0x02,0x01,0x04,0x02,0x01,0xe7,
+ 0x06,0xe6,0x06,0x01,0x03,0x02,0xe7,0x05,0xe7,0x03,0x01,0x0c,0xe6,0x03,0x01,0x0a,
+ 0xe6,0xe5,0x01,0x01,0x07,0x01,0x07,0x01,0xe7,0xe5,0x01,0x01,0x13,0xe7,0x0d,0x01,
+ 0x07,0x01,0x0f,0xe7,0x0c,0x01,0xe5,0x20,0x0c,0x01,0xe5,0x04,0xe5,0xe7,0x08,0x08,
+ 0xe5,0x01,0x04,0xe6,0x03,0x02,0xe6,0x04,0x01,0xe6,0x01,0x07,0xe5,0x04,0x01,0xe5,
+ 0x08,0xe5,0x04,0x01,0xe5,0x04,0xe5,0xe7,0x04,0x01,0xe6,0x04,0x01,0x01,0x01,0x07,
+ 0x05,0x02,0xe5,0x08,0x01,0x03,0x01,0xe5,0x05,0x01,0xe5,0x0d,0xe5,0xe5,0x0c,0x01,
+ 0x39,0x01,0xe5,0x08,0x03,0x0e,0xe5,0x02,0x04,0x01,0x0b,0x08,0x03,0x01,0xe5,0xe5,
+ 0x03,0x06,0x07,0x04,0x02,0x01,0x03,0xe5,0xe5,0x02,0x06,0x01,0x03,0xe5,0x08,0x01,
+ 0x02,0x03,0x0c,0xe5,0xe5,0x03,0x02,0x01,0x09,0x05,0xe8,0x0b,0x01,0x05,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x09,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x06,
+ 0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x01,0x04,0xe5,0x07,0xe6,
+ 0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe7,0x2d,0x09,0x06,0x01,0x0a,0x12,0xe6,0x06,
+ 0xe5,0x07,0xe5,0x05,0x01,0xe5,0x09,0x09,0xe6,0x06,0xe5,0x05,0x01,0xe6,0x07,0x06,
+ 0x01,0xe6,0x04,0x01,0x09,0x09,0xe5,0x05,0x16,0xe5,0x0f,0x2e,0x10,0x01,0x1b,0x01,
+ 0x09,0x09,0xe5,0x05,0x01,0x08,0xe5,0xe5,0x06,0x09,0x01,0x07,0x01,0x11,0x01,0x07,
+ 0x01,0x07,0x09,0x31,0xe6,0x36,0x13,0x1c,0xe5,0x07,0x0a,0x14,0x0a,0x08,0x0a,0x12,
+ 0x09,0x09,0xe5,0x05,0x25,0xe5,0xe5,0x02,0x20,0x09,0x09,0x09,0x0b,0x09,0x04,0x04,
+ 0x06,0x02,0x06,0x02,0x09,0x06,0x04,0x04,0x02,0x06,0x04,0x04,0x02,0x0b,0x09,0x04,
+ 0x01,0x02,0x04,0x04,0x04,0x04,0x09,0x11,0x0d,0xe8,0x0a,0x01,0x01,0xe5,0x3e,0x1a,
+ 0x05,0x02,0x03,0x02,0x02,0x07,0xe5,0x01,0x01,0x08,0x05,0x02,0x14,0xe5,0x01,0x09,
+ 0x01,0x02,0x1a,0x01,0xe5,0xe5,0x0b,0x01,0x02,0x0d,0xe5,0x01,0x0e,0x02,0x01,0x01,
+ 0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x02,0x04,
+ 0x01,0x02,0x04,0x01,0x01,0x05,0xe7,0xe5,0x03,0xe7,0x05,0x01,0xe6,0xe5,0x02,0xe8,
+ 0x06,0x01,0xe6,0x04,0x01,0x07,0x01,0xe6,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x01,
+ 0x04,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0xe5,0xe5,0x02,0x01,0x02,0x04,0x01,
+ 0x05,0x01,0x01,0x0a,0xe6,0xe5,0x01,0x34,0xe5,0x0d,0x04,0x03,0x05,0xe5,0xe6,0x03,
+ 0x02,0x02,0x04,0x06,0xe5,0xe5,0x05,0x01,0xe5,0x07,0xe7,0xe5,0x0d,0xe6,0x12,0xe5,
+ 0x0f,0xe5,0x01,0x04,0x04,0x07,0xe5,0x09,0x24,0xe5,0x0f,0x24,0xe5,0x0e,0x01,0x07,
+ 0x02,0x04,0x02,0x03,0x06,0x07,0x02,0x04,0x02,0x01,0xe5,0xe6,0x15,0x18,0x0b,0x1a,
+ 0x01,0x02,0x1b,0xe5,0x0a,0xe5,0xe7,0x5b,0x01,0x07,0x09,0x09,0x04,0x03,0x02,0xe5,
+ 0xe5,0x05,0x07,0x01,0x01,0x02,0x04,0x03,0x07,0x02,0x03,0x05,0x0c,0x27,0x11,0x01,
+ 0xe8,0x03,0xe5,0x02,0x03,0xe6,0x3a,0xe5,0x08,0x06,0x01,0x0e,0x15,0xe5,0x02,0x04,
+ 0x02,0x01,0x09,0x01,0xe5,0xe5,0x04,0x05,0xe5,0xe5,0xe6,0x0d,0x01,0x07,0xe6,0x10,
+ 0x01,0x01,0x05,0xe6,0x06,0xe6,0x0c,0xe7,0xe6,0x01,0x01,0x07,0x11,0x29,0x0f,0x01,
+ 0x01,0x01,0x05,0x07,0x09,0x01,0x0b,0xe5,0x09,0x02,0x02,0x13,0x04,0xe5,0x01,0xe5,
+ 0x0e,0x1c,0xe5,0x10,0x10,0xe5,0xe7,0x07,0x2e,0x01,0x05,0xe5,0x01,0x03,0x08,0x08,
+ 0x08,0x0b,0x03,0x09,0x09,0x02,0xe6,0x02,0x02,0x07,0x01,0x0f,0x03,0x09,0x04,0x02,
+ 0x09,0xe6,0x08,0x11,0x08,0x10,0x03,0xe6,0x03,0x06,0x03,0x13,0x09,0x1e,0xe5,0x08,
+ 0x13,0x04,0x06,0x05,0x02,0x03,0x0b,0x06,0x02,0x04,0x09,0x04,0x0f,0x02,0x0a,0x01,
+ 0x07,0xe5,0x01,0xe5,0x0a,0x05,0x17,0xe5,0xe6,0x02,0x4a,0x08,0xe5,0x12,0x03,0xe5,
+ 0x01,0x04,0x04,0x06,0x0a,0xe5,0x01,0x01,0x03,0xe5,0x01,0x03,0x06,0xe5,0x03,0x02,
+ 0x09,0x0a,0x01,0x07,0xe5,0xe5,0x01,0x0e,0x09,0x02,0x12,0xe5,0x01,0xe5,0xe5,0x3a,
+ 0x04,0x02,0x01,0x09,0x09,0xe5,0xe5,0xe5,0xe5,0x01,0xe7,0x0c,0x0b,0x01,0x05,0x03,
+ 0x01,0xe5,0x0a,0xe5,0x05,0x02,0x03,0x02,0x01,0x1a,0xe6,0x06,0x01,0x2c,0x03,0x3b,
+ 0x13,0x1a,0x17,0x02,0x0b,0x02,0x11,0x05,0x04,0x1a,0x02,0x34,0x01,0x01,0xe7,0x3c,
+ 0x04,0x01,0x0a,0x08,0xe5,0xe5,0x05,0x01,0xe5,0x05,0x06,0x06,0x01,0xe5,0x01,0x08,
+ 0x08,0x0e,0x01,0x04,0x03,0x0b,0x01,0xe5,0x11,0x03,0xe5,0x01,0x01,0x04,0x01,0x25,
+ 0x03,0x1e,0x3e,0x01,0x0b,0x04,0x02,0x09,0x01,0x0c,0x02,0x02,0xe5,0x04,0x08,0x0e,
+ 0x09,0x13,0x01,0x07,0x05,0x21,0x02,0x02,0x01,0xe5,0x24,0x47,0x04,0x09,0x16,0x1c,
+ 0x0a,0x11,0xe5,0x01,0x07,0x2d,0x02,0xe6,0x43,0x01,0x03,0xe6,0x06,0xe5,0x07,0xe6,
+ 0x06,0x02,0xe5,0x04,0x0d,0xe5,0x06,0x05,0x02,0x0b,0x01,0xe5,0x04,0x08,0x13,0x06,
+ 0x02,0xe5,0x2e,0x02,0x01,0xe5,0xe6,0x01,0x01,0x40,0xe5,0x0b,0xe5,0x01,0x05,0xe5,
+ 0xe5,0x0b,0xe5,0x02,0x03,0x0b,0x01,0x02,0xe5,0x11,0xe5,0x04,0xe5,0x04,0x16,0x01,
+ 0x0a,0xe5,0xe5,0x31,0x02,0x02,0xe5,0x03,0x48,0x07,0x07,0x01,0x04,0xe5,0xe5,0xe5,
+ 0x03,0x01,0x18,0x01,0xe5,0xe6,0x0c,0x04,0x01,0xe5,0xe5,0x01,0xe6,0x12,0xe5,0xe5,
+ 0xe5,0x01,0x01,0x01,0xe5,0xe5,0x03,0x01,0x02,0x02,0xe6,0x01,0x01,0x24,0xe6,0x52,
+ 0x09,0x01,0x04,0x02,0x01,0x04,0x04,0x13,0x06,0xe5,0x02,0x07,0x05,0xe5,0x01,0x01,
+ 0x07,0x01,0x0e,0x02,0x01,0x04,0x02,0x01,0x04,0x04,0x03,0xe5,0x01,0x01,0x1c,0x02,
+ 0x01,0x01,0xe7,0x3e,0x01,0x13,0x09,0x04,0xe6,0x07,0x04,0x06,0x06,0x01,0x04,0x02,
+ 0x01,0x01,0x03,0x0c,0x02,0x05,0x07,0x06,0x07,0xe5,0x07,0x01,0x01,0x03,0x01,0xe6,
+ 0x03,0x28,0xe9,0x01,0x3c,0x01,0x01,0x0f,0x03,0x05,0x03,0x09,0x05,0x02,0x08,0x01,
+ 0x01,0x02,0x02,0x03,0x02,0x01,0xe5,0x01,0x03,0x01,0x04,0x09,0x05,0x01,0xe5,0x02,
+ 0x01,0x02,0x01,0x01,0x01,0xe5,0x03,0x05,0x01,0x01,0x05,0x03,0x09,0x1d,0x01,0x01,
+ 0x01,0xe5,0x01,0x39,0x01,0xe5,0xe5,0x12,0x04,0x01,0xe5,0xe5,0x02,0xe5,0x01,0x01,
+ 0x04,0x01,0xe5,0x05,0x02,0x06,0x06,0x01,0x02,0x01,0x02,0x04,0x01,0x05,0x04,0x01,
+ 0x0e,0x01,0xe5,0x08,0x01,0x04,0x01,0xe5,0xe5,0x06,0x01,0x04,0x02,0x01,0x21,0xe5,
+ 0xe7,0x3e,0x01,0x11,0x09,0x01,0x03,0xe5,0x01,0x01,0x0a,0x02,0xe6,0x02,0x03,0xe6,
+ 0x02,0x04,0x01,0x01,0x03,0x10,0x01,0x01,0xe5,0x06,0x08,0x07,0x01,0x03,0xe5,0x01,
+ 0x01,0x07,0x01,0x01,0xe5,0xe6,0xe5,0xe5,0x20,0x02,0xe6,0x08,0x02,0x1a,0x02,0x06,
+ 0xe5,0x11,0x13,0x13,0xe5,0x04,0x02,0x02,0x06,0x02,0x05,0x09,0x02,0x09,0x02,0x03,
+ 0x02,0xe5,0x04,0x02,0x02,0x10,0xe5,0x07,0xe5,0x04,0x04,0x26,0x02,0xe5,0xe5,0x25,
+ 0xe5,0x07,0x13,0x01,0x13,0x11,0x05,0xe5,0x01,0x06,0x02,0xe5,0x05,0xe5,0x07,0xe5,
+ 0x03,0x04,0x02,0x05,0xe5,0x01,0x05,0xe5,0x01,0x06,0x02,0xe5,0x04,0x02,0x0f,0xe5,
+ 0x01,0x28,0x02,0xe5,0x0d,0x09,0x09,0x09,0x03,0x05,0x09,0x02,0x02,0x03,0x09,0x02,
+ 0x01,0x01,0x02,0x09,0x05,0xe5,0x01,0xe5,0x03,0x03,0x0b,0xe6,0x06,0xe5,0xe5,0x02,
+ 0x02,0x02,0xe5,0x04,0xe5,0x03,0xe5,0x01,0xe5,0x01,0x02,0x02,0x02,0x06,0x05,0xe5,
+ 0x01,0x06,0x02,0xe5,0x03,0xe5,0x01,0x09,0x09,0x06,0x06,0xe6,0x01,0x02,0x45,0x13,
+ 0x12,0xe5,0x27,0xe5,0x0f,0x0b,0xe5,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x19,0x02,0x04,
+ 0x03,0x01,0xe5,0x46,0x13,0x13,0x05,0x09,0x15,0x03,0x05,0x09,0x09,0x03,0x05,0x09,
+ 0x03,0x07,0x07,0x03,0x1c,0x09,0xe8,0xe5,0x1e,0x01,0x07,0x01,0x04,0x0c,0x01,0x09,
+ 0x07,0x01,0x04,0x04,0x07,0x01,0x06,0x03,0xe5,0x0b,0x07,0x01,0x07,0xe5,0x0e,0x01,
+ 0xe7,0x06,0xe5,0x0e,0x01,0x04,0x02,0x01,0x07,0x01,0xe5,0xe5,0x05,0x22,0x02,0xe5,
+ 0x20,0x01,0xe5,0x05,0x01,0xe5,0x0e,0xe5,0xe6,0x05,0x02,0x05,0xe5,0xe6,0x05,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x02,0xe5,0x08,0x0b,0x02,0x02,0x02,0xe5,0x01,0x06,0x05,
+ 0x01,0xe6,0x07,0xe5,0x01,0x06,0x05,0x01,0xe6,0x03,0xe5,0xe7,0x03,0xe5,0x01,0xe5,
+ 0x04,0x02,0x24,0xe5,0x4a,0x13,0x06,0x07,0x02,0x06,0x1a,0xe5,0x0c,0x09,0x02,0x01,
+ 0xe5,0x0b,0xe5,0x08,0x0e,0x03,0x05,0x22,0xe5,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0xe5,0x02,0x01,0xe5,0x07,0xe5,
+ 0x02,0x04,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x06,
+ 0xe5,0xe6,0x20,0x01,0x07,0x01,0x0a,0xe5,0x04,0x01,0x09,0x07,0x01,0xe6,0x06,0xe6,
+ 0xe5,0xe5,0xe5,0xe6,0x07,0xe5,0x08,0xe5,0x09,0xe5,0x04,0x02,0x06,0x02,0x06,0x01,
+ 0xe5,0x05,0x01,0xe5,0x08,0x06,0x01,0x07,0x01,0x07,0x01,0xe5,0x07,0x22,0xe5,0xe6,
+ 0x20,0x01,0x07,0x01,0x11,0x01,0x07,0x09,0x01,0x07,0x01,0x07,0x01,0xe5,0x1a,0x16,
+ 0x07,0x01,0xe5,0x19,0x01,0x07,0x01,0x07,0x02,0x06,0x24,0xe6,0xe6,0x49,0x13,0x05,
+ 0x0e,0x08,0x16,0x09,0x13,0x09,0x1c,0x09,0x23,0xe7,0x02,0x34,0x10,0x0c,0x06,0x01,
+ 0xe5,0x08,0x08,0x02,0x06,0x02,0x0b,0x06,0x02,0x09,0x09,0x09,0x06,0x02,0x09,0x04,
+ 0x04,0x09,0x04,0x26,0x01,0x6c,0x04,0x01,0xe5,0x0c,0x03,0x0a,0x3b,0x01,0xe5,0x02,
+ 0x0a,0x26,0x02,0xe5,0x01,0xe5,0x0c,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,
+ 0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0xe6,0x04,0x01,0x01,0x05,0x01,0x01,
+ 0x05,0x01,0x02,0x01,0x02,0x01,0x01,0x05,0x01,0x09,0x01,0x01,0x05,0x01,0xe5,0xe5,
+ 0x03,0x01,0x01,0x05,0x01,0x02,0x04,0xe6,0x01,0x04,0x01,0x01,0x05,0xe6,0x02,0x03,
+ 0x01,0x02,0x04,0xe6,0xe5,0x04,0x01,0x06,0xe5,0xe5,0x06,0x01,0x02,0x07,0x02,0xe5,
+ 0x0b,0x11,0x32,0x03,0x04,0x08,0x0f,0xe5,0x13,0xe5,0x06,0xe5,0x08,0xe5,0x07,0xe5,
+ 0x01,0x05,0x09,0xe5,0x0e,0x08,0x03,0xe5,0x2c,0xe7,0x07,0x25,0x18,0x09,0x09,0x06,
+ 0x02,0x0a,0x01,0x06,0x0c,0x01,0x09,0x05,0x02,0x08,0x04,0x06,0x08,0x03,0xe5,0x12,
+ 0x04,0x0c,0x1f,0xe6,0xe6,0xe5,0x52,0x0d,0x01,0x09,0x12,0x01,0x18,0x01,0x07,0x05,
+ 0x0c,0x1d,0x0b,0x21,0x01,0x01,0xe5,0x24,0x0d,0x21,0x0f,0x09,0xe5,0x02,0x04,0xe5,
+ 0x04,0x03,0x0a,0xe5,0xe5,0x02,0x03,0x01,0x02,0x02,0x04,0x06,0x01,0xe5,0x51,0x01,
+ 0xe7,0x1e,0x05,0x35,0x08,0x0f,0x08,0x05,0x01,0xe5,0x05,0x06,0x09,0x0f,0xe5,0xe5,
+ 0x19,0x06,0x27,0x0b,0x01,0xe6,0x07,0x04,0xe5,0xe5,0x10,0x09,0x09,0x2b,0x09,0x09,
+ 0x01,0x0a,0xe5,0x04,0x05,0x09,0x10,0x01,0x02,0x0a,0x09,0x03,0x01,0x02,0x09,0x13,
+ 0x17,0x01,0x02,0x0a,0x02,0x13,0x09,0xe7,0x05,0xe5,0xe5,0x08,0x06,0x01,0xe5,0x08,
+ 0x03,0x0f,0x03,0x05,0x09,0xe5,0x04,0x0e,0x16,0x0d,0x01,0x0f,0x14,0xe5,0x01,0x06,
+ 0x0d,0x0c,0x03,0x02,0x0c,0x13,0xe5,0x11,0x1a,0x1d,0x12,0x01,0x08,0xe5,0x04,0xe6,
+ 0x19,0x1d,0x05,0x03,0x05,0x02,0x07,0x02,0x17,0x02,0xe5,0x11,0x12,0x18,0x09,0x04,
+ 0x0c,0x06,0x14,0x0e,0x06,0x08,0x03,0x14,0x04,0x03,0x0a,0x04,0x1c,0x03,0x12,0x0a,
+ 0x01,0x01,0x46,0x1b,0x02,0x0f,0x03,0x06,0x03,0xe6,0x1b,0x05,0xe5,0x13,0x0c,0x3d,
+ 0xe5,0x0f,0x02,0x04,0x02,0x01,0x02,0x01,0x04,0xe5,0x02,0x09,0x04,0x04,0x03,0x05,
+ 0x01,0x02,0x04,0x09,0x01,0x02,0x04,0x2b,0x16,0x04,0x09,0x0d,0x01,0x03,0x04,0x02,
+ 0x01,0x13,0x01,0x07,0x09,0x06,0x01,0x04,0x0c,0x01,0x03,0x01,0x09,0x08,0x07,0x01,
+ 0xe5,0xe5,0xe5,0x03,0xe5,0x0c,0x05,0x09,0x08,0xe6,0xe5,0x13,0x13,0x08,0x0a,0x07,
+ 0x06,0x02,0x07,0x01,0x09,0x09,0x07,0x01,0x09,0x02,0x06,0x02,0x0e,0xe5,0x16,0x0a,
+ 0x0e,0x05,0x09,0x03,0x03,0x09,0x01,0x01,0xe5,0x03,0xe5,0x09,0x06,0x1f,0x1e,0xe5,
+ 0x07,0xe5,0x11,0xe5,0x04,0x04,0x01,0x0f,0xe5,0x07,0x01,0x0b,0x03,0xe5,0xe5,0x0b,
+ 0x02,0xe5,0x08,0x09,0x09,0x09,0x04,0xe5,0x02,0x09,0x09,0x05,0x02,0xe5,0xe5,0x01,
+ 0xe5,0x01,0xe5,0xe5,0x03,0xe7,0x07,0xe5,0x03,0x05,0xe5,0x05,0xe7,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x08,0x04,0xe5,0x02,0x04,0x04,0x08,0xe5,0x03,0x04,0x08,0xe5,0x07,
+ 0xe5,0x0c,0x02,0xe5,0x17,0x14,0x05,0x0a,0x09,0x01,0x0a,0x08,0x01,0x08,0xe5,0x01,
+ 0x01,0x02,0x01,0x09,0x02,0x07,0xe5,0x06,0x01,0x09,0x08,0xe5,0x08,0x0e,0x18,0x09,
+ 0x09,0x09,0x0e,0x02,0x03,0x0b,0x06,0x02,0x06,0x0c,0x06,0x0c,0x0e,0x01,0x02,0x02,
+ 0x06,0x03,0x05,0x03,0x05,0x06,0x02,0x04,0x01,0x04,0x03,0x02,0x02,0x09,0x09,0x03,
+ 0x03,0x01,0x07,0x01,0x07,0x07,0x01,0x01,0x09,0xe5,0x11,0x09,0x0f,0x02,0x08,0xe5,
+ 0x1c,0x08,0x13,0x09,0x03,0x09,0x0d,0x0b,0x09,0x0b,0x17,0x03,0x0b,0x09,0xe5,0x07,
+ 0x27,0x12,0x02,0xe6,0xe5,0x0e,0x01,0x0c,0x04,0x04,0x05,0x05,0x02,0x13,0x0a,0x03,
+ 0x18,0x09,0x0b,0xe5,0x04,0x02,0x09,0x01,0x07,0x07,0x01,0x07,0x08,0xe5,0xe5,0x02,
+ 0x01,0x01,0x01,0x04,0x0e,0x09,0x09,0x0f,0x01,0xe5,0x0b,0xe6,0x07,0xe5,0x05,0x01,
+ 0xe5,0x02,0x04,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x07,
+ 0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x08,0xe6,0x07,0xe5,0x07,0xe5,0x06,0xe6,0x07,
+ 0x13,0x03,0x03,0x0b,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0x01,0xe6,0x02,
+ 0x09,0x01,0x07,0x05,0x03,0x01,0x07,0x07,0x01,0x01,0x07,0x08,0xe5,0xe5,0x06,0x09,
+ 0x04,0x04,0x09,0x09,0x0a,0xe5,0x02,0x05,0x09,0x05,0x03,0x12,0x0c,0x04,0x05,0x06,
+ 0x08,0xe5,0x08,0x09,0x0b,0x06,0x01,0x0e,0xe5,0x07,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0x09,0x09,0xe5,0x07,0x02,0x06,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x0b,0x02,0xe5,0x0d,0x02,0x06,0x01,0x07,0x09,0x01,0x02,0x04,
+ 0x09,0x01,0x07,0x09,0x01,0x07,0x03,0x05,0x05,0x03,0x02,0x06,0x0b,0x04,0x04,0x09,
+ 0x1f,0x07,0x13,0x09,0x09,0x09,0x02,0x10,0x12,0x44,0x02,0x04,0xe5,0x04,0x02,0xe5,
+ 0x18,0x25,0x01,0x01,0x21,0x2f,0x05,0x01,0x01,0x0e,0x09,0x02,0x06,0x02,0x06,0x09,
+ 0x02,0x01,0x02,0x01,0x02,0x01,0x04,0x09,0x09,0x09,0x01,0xe5,0x05,0x05,0x03,0x02,
+ 0x05,0x02,0x09,0x02,0xe5,0x04,0x04,0x03,0xe5,0x07,0x03,0x05,0xe5,0x08,0x05,0x02,
+ 0xe5,0x02,0x03,0x01,0x04,0x04,0x09,0x09,0x09,0x06,0xe5,0xe5,0x06,0x18,0x09,0x09,
+ 0x1d,0x0f,0x13,0x03,0x0a,0x0a,0x04,0x10,0x09,0x06,0xe5,0xe5,0x4a,0xe5,0x01,0x07,
+ 0x08,0xe5,0x07,0x09,0x09,0x03,0x05,0x09,0x09,0xe5,0x07,0x09,0x09,0x09,0x05,0x03,
+ 0x06,0xe5,0x02,0x09,0x09,0x09,0xe5,0x07,0x07,0x01,0x01,0x07,0x01,0x07,0x05,0x03,
+ 0x01,0x07,0x09,0x09,0x0e,0x01,0xe5,0x03,0x61,0x11,0x01,0x07,0x0b,0x09,0x09,0x03,
+ 0x05,0x02,0xe5,0x05,0x15,0x3b,0xe5,0x14,0x13,0x13,0x09,0x14,0x09,0x0d,0x09,0x06,
+ 0x04,0x09,0x04,0xe5,0x02,0x04,0x04,0x18,0x13,0x09,0x27,0xe5,0xe5,0x09,0x17,0x06,
+ 0x02,0x4f,0x4f,0x09,0x2b,0x05,0xe6,0x0a,0x3b,0x27,0x5b,0x3c,0xe6,0x3c,0x5b,0x1e,
+ 0x26,0x27,0xe5,0xe5,0x03,0x10,0x31,0x2a,0x05,0x03,0x05,0x02,0x02,0x05,0x03,0x05,
+ 0x03,0x05,0xe5,0x01,0x05,0x14,0x13,0x29,0x06,0xe5,0xe6,0x46,0x27,0x15,0x46,0x33,
+ 0x05,0xe5,0x01,0x04,0x57,0xa9,0x03,0x14,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,
+ 0xe6,0x06,0x09,0xe6,0x06,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,
+ 0x09,0x09,0x09,0x0a,0x02,0x05,0x09,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x05,0x01,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x05,0x02,0x09,0x07,0x03,
+ 0x09,0x09,0x09,0x09,0x04,0x03,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x08,0x09,0x10,0xe6,0x15,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x05,0x03,0x09,0x05,0x03,0x04,0x09,0x05,0x05,0x09,0x09,0x09,0x14,0x03,0x09,
+ 0x05,0x03,0x09,0x27,0x01,0x0d,0x03,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,
+ 0x09,0x05,0x03,0x09,0x05,0x03,0x09,0x01,0x04,0x04,0x04,0x06,0x04,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x06,0x0b,0x03,0x09,0x09,0x09,0x09,0x03,0x05,0x03,0x0d,0x02,0x01,
+ 0x0b,0x06,0x01,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,
+ 0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,
+ 0x06,0x02,0x02,0x03,0x02,0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x02,0x04,0x02,0x01,0x04,0x02,0x01,0x01,0xe5,0x03,0x01,0x01,0x02,0x04,
+ 0x02,0x01,0x02,0x01,0x01,0x02,0x04,0x04,0x04,0x06,0x02,0x02,0xe6,0xe5,0xe5,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
diff --git a/u-boot/board/esd/ash405/Makefile b/u-boot/board/esd/ash405/Makefile
new file mode 100644
index 0000000..401622f
--- /dev/null
+++ b/u-boot/board/esd/ash405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/ash405/ash405.c b/u-boot/board/esd/ash405/ash405.c
new file mode 100644
index 0000000..1b0365e
--- /dev/null
+++ b/u-boot/board/esd/ash405/ash405.c
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10); /* wait 10us */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)(DUART0_BA + 4), 0x08);
+	out_8((void *)(DUART1_BA + 4), 0x08);
+	out_8((void *)(DUART2_BA + 4), 0x08);
+	out_8((void *)(DUART3_BA + 4), 0x08);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming ASH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/u-boot/board/esd/ash405/flash.c b/u-boot/board/esd/ash405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/ash405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/ash405/fpgadata.c b/u-boot/board/esd/ash405/fpgadata.c
new file mode 100644
index 0000000..94e8db8
--- /dev/null
+++ b/u-boot/board/esd/ash405/fpgadata.c
@@ -0,0 +1,2492 @@
+  0x1f,0x8b,0x08,0x08,0x5c,0xa1,0x5d,0x3f,0x00,0x03,0x61,0x73,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x32,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x1c,0xe5,
+  0x91,0x2f,0x0a,0x57,0xbf,0xdd,0x92,0x5f,0x4d,0x8f,0x34,0xad,0x91,0x4c,0x14,0x30,
+  0xa6,0x35,0x92,0xcd,0x58,0x19,0xc9,0xe3,0x91,0x90,0x85,0x10,0xa3,0xb6,0x24,0x58,
+  0x45,0x36,0x58,0x71,0xd8,0x2c,0x67,0x97,0x93,0x1d,0x88,0x93,0xe3,0xdd,0x75,0x72,
+  0x1c,0x36,0x37,0xc7,0x21,0x6c,0xf2,0x6a,0x24,0xe3,0xb1,0x65,0xe3,0xc1,0x38,0xc1,
+  0x04,0x92,0x3b,0xfe,0x43,0x10,0xe0,0x24,0x63,0xd9,0x60,0x19,0x1b,0x68,0x09,0x41,
+  0xc6,0xb6,0xb0,0x15,0xc7,0x9b,0x35,0xc4,0x0b,0x63,0x50,0x88,0x30,0x82,0xc8,0xe0,
+  0x24,0xb2,0x2d,0xec,0x5b,0xd5,0x23,0xcd,0xf4,0x38,0x7b,0xf6,0xec,0xde,0xf3,0xdc,
+  0xef,0xdb,0xef,0xbb,0xab,0x73,0x9e,0x67,0x2b,0xdd,0xed,0xa6,0xfb,0x9d,0xb7,0xab,
+  0x7e,0x55,0xf5,0xab,0x2a,0xc8,0x73,0x8d,0xa7,0xfe,0x1f,0x80,0x74,0x37,0x68,0x77,
+  0xff,0xfd,0x8a,0x1a,0xff,0x0d,0x7f,0xbd,0xe0,0xaf,0xfd,0x81,0xaa,0xaf,0x7d,0x69,
+  0x39,0xdc,0x03,0x6a,0xe0,0xef,0x6f,0xf0,0x7f,0xf9,0x1b,0x5f,0x5f,0x50,0x53,0x03,
+  0x5f,0xc2,0xff,0xe5,0xf7,0x57,0xcf,0xf7,0xdf,0x88,0xff,0x1f,0x96,0x43,0xde,0x82,
+  0x05,0xf5,0x35,0xb5,0xf5,0xfe,0x1a,0xf8,0x32,0x48,0xd5,0x3b,0x2f,0xe3,0xdf,0xd3,
+  0x8f,0xfe,0xf9,0x57,0xfc,0x20,0x24,0x00,0x98,0xe1,0x97,0x42,0xf4,0x7f,0x55,0xbf,
+  0xa4,0x4b,0x20,0x1a,0x2b,0xfd,0x60,0xd2,0xff,0x86,0xa9,0xf3,0x79,0x7e,0xd0,0xed,
+  0xff,0x5b,0xf2,0x83,0x01,0xed,0x60,0x6c,0x00,0xb7,0x1f,0xfe,0xd7,0x7f,0x86,0x22,
+  0xa6,0xc5,0x7f,0xe7,0xf5,0x97,0x0f,0x8b,0xff,0xe9,0x55,0x99,0xbf,0xc6,0x8f,0x62,
+  0xd3,0x22,0xfb,0x37,0xdc,0x5f,0x32,0x20,0x7d,0xff,0x37,0xfe,0x4d,0xf7,0xff,0xc3,
+  0xf4,0xfd,0xff,0xbd,0xd7,0x83,0xfb,0xdf,0x70,0x39,0x80,0x92,0x7e,0x1e,0x37,0x38,
+  0x80,0x09,0x88,0x81,0xf7,0x5f,0x11,0x1a,0x07,0xa7,0xff,0x61,0x7f,0xce,0x09,0x71,
+  0x4c,0x34,0x24,0x67,0xac,0x92,0x67,0x19,0x93,0x7c,0x61,0xd2,0x15,0xed,0x3c,0x17,
+  0x3b,0x2a,0x1a,0x93,0xae,0x44,0xd9,0x4a,0x76,0xac,0xa3,0x5a,0x5f,0x3a,0x51,0x34,
+  0xae,0xad,0x9a,0xba,0xde,0x2c,0xf9,0x2d,0x74,0x8b,0x82,0x10,0x8f,0xb3,0xca,0x48,
+  0x1f,0x38,0x92,0x05,0x1b,0xd8,0x6f,0xf4,0xf5,0xa2,0x2a,0xa9,0xf6,0xc1,0x8b,0x7c,
+  0x9d,0xa8,0x30,0xd4,0x3e,0x96,0x54,0xf4,0xa9,0xeb,0x13,0xd0,0x65,0x74,0x82,0xcf,
+  0x7c,0xcc,0x9f,0x9b,0xaf,0x3c,0x9f,0x17,0x33,0x55,0x0d,0x06,0x79,0x58,0xf2,0xa1,
+  0x90,0xeb,0x84,0x67,0x84,0x6e,0xa8,0xfe,0xa6,0xc3,0xd2,0xf4,0xf5,0x66,0xce,0x8f,
+  0xa1,0x1b,0xaa,0x42,0x25,0xc2,0xb1,0x12,0xfa,0xc2,0x1e,0xd3,0xb1,0x81,0x7d,0x85,
+  0x45,0xb4,0xaa,0x41,0x75,0x6b,0x93,0x0f,0x9e,0xd1,0x2b,0x5a,0xd5,0x38,0x9b,0x50,
+  0xa6,0x9f,0x67,0xd1,0xcc,0x77,0xc3,0x47,0x1e,0x08,0xbe,0xe3,0xda,0x5b,0xe6,0x83,
+  0x71,0x11,0xe8,0xbf,0xee,0x71,0xf9,0x5d,0x38,0x6c,0x04,0x93,0x2e,0xbd,0xcc,0x09,
+  0xef,0xac,0x09,0xac,0x72,0xc5,0xe5,0xe1,0x96,0xe9,0xeb,0x63,0x52,0x5c,0xb9,0xbc,
+  0xa8,0x71,0x91,0xeb,0x5b,0xf2,0x41,0xf8,0x04,0x1a,0xcd,0xa5,0xa6,0x3c,0x0e,0x97,
+  0x44,0xa3,0xe9,0x1a,0x57,0x27,0xb5,0x1f,0x2a,0x2f,0xdd,0xed,0x1a,0x6f,0x1e,0x85,
+  0xd0,0xd4,0xf5,0x27,0xb4,0x2e,0xfe,0x3e,0xd4,0x0f,0x5c,0xb7,0xfb,0xf3,0x63,0xca,
+  0xaf,0xcb,0xeb,0xcd,0x25,0x8f,0x7f,0x6a,0x44,0x9a,0x80,0xa0,0xe9,0xea,0x93,0x3f,
+  0x84,0xf3,0x22,0x60,0x6c,0x88,0xcb,0xe3,0xca,0xf4,0x7a,0x26,0x72,0x74,0xd1,0x3d,
+  0xa2,0x1b,0xfc,0x59,0xd6,0x80,0x2f,0xe2,0x49,0xb4,0x46,0xd9,0xbb,0x30,0x21,0xaa,
+  0xde,0x56,0x9f,0x65,0x93,0xb0,0xbf,0xab,0xd6,0xcc,0x8f,0xb3,0x8f,0x70,0xf7,0x4f,
+  0xbd,0xaf,0xb2,0x44,0xd9,0x91,0xe0,0xe3,0x8e,0x9a,0xdc,0x8d,0x7a,0x54,0xd2,0x4f,
+  0x73,0xb7,0x7b,0x44,0xe9,0x15,0xbe,0xa4,0xaa,0xb0,0x21,0xa8,0x86,0x98,0xc1,0xfd,
+  0x6c,0x02,0xbf,0x95,0xd4,0xdf,0xb8,0xf6,0x5d,0xf8,0x94,0x28,0xfb,0x69,0xeb,0x6a,
+  0xcf,0x6c,0xe8,0xea,0xbb,0x3b,0xe9,0xbd,0x93,0xfd,0x2a,0x54,0x1e,0xa9,0x4c,0xaa,
+  0x2b,0xd8,0x9b,0xc6,0xbe,0xe1,0x39,0xa1,0xbc,0xd5,0xec,0x64,0xfa,0xfe,0xad,0x7c,
+  0x89,0xf1,0x0e,0xd4,0x8d,0x3a,0x6a,0x9b,0x37,0xc0,0x2f,0xcd,0x78,0xff,0x92,0x9b,
+  0x9a,0x86,0x8c,0x5e,0xad,0x21,0xe9,0xaa,0x29,0x3b,0x2a,0x3e,0x86,0x40,0xbb,0xd3,
+  0x2f,0x1f,0x67,0xd3,0xcf,0x6f,0xcc,0x3c,0x08,0xbf,0x85,0xe0,0xa0,0x67,0x5c,0xde,
+  0x05,0xfb,0xe0,0x06,0x13,0x57,0x6f,0xd2,0xb8,0x5f,0xc3,0xf7,0x1d,0x97,0x27,0xe1,
+  0x8f,0x4a,0x63,0x8b,0x3a,0x2e,0x0f,0xb3,0xe9,0xf5,0xe1,0x33,0x7b,0xe0,0x22,0xf8,
+  0x4d,0x67,0xbc,0x79,0x97,0x11,0x67,0x6e,0x73,0x69,0x54,0x1a,0x81,0x93,0x10,0x4c,
+  0x3a,0xe3,0xf2,0x07,0xe6,0x00,0x04,0x42,0x28,0x0c,0x40,0x7a,0x3f,0x68,0x51,0x78,
+  0x16,0x4a,0xcd,0xfc,0x55,0x15,0xb3,0xa2,0x7b,0x51,0x58,0xdc,0xce,0x06,0xa1,0x0b,
+  0x6e,0x34,0x1d,0xab,0x9a,0x86,0xf4,0x5f,0xc1,0x53,0x06,0x5f,0x85,0xeb,0x33,0x7d,
+  0xbd,0x0e,0x8f,0xc1,0x4b,0xa2,0x2c,0xf9,0xe8,0x6a,0xc7,0x8f,0xe0,0xa5,0xf0,0x9c,
+  0x64,0xdb,0x6a,0xcf,0x9b,0xd0,0x25,0xe6,0x27,0xf3,0x56,0x2f,0x7b,0x53,0xac,0x15,
+  0xd7,0xdf,0xc3,0x57,0x33,0x33,0xbd,0xdf,0x46,0x8b,0xd7,0xc3,0x6e,0xd0,0x5f,0xcf,
+  0x0b,0x38,0x36,0xf0,0x3d,0xc9,0x72,0x53,0xad,0x61,0x1f,0xe4,0x75,0xc4,0xbc,0x21,
+  0xf5,0x06,0x5c,0xcf,0x87,0x4d,0x5f,0xc8,0xeb,0x67,0xc7,0xd3,0xd7,0x8f,0xcc,0xbc,
+  0x08,0x17,0x62,0xd5,0xd1,0xfc,0x0f,0xd5,0x1e,0xb8,0xb4,0xad,0x56,0x14,0x7c,0x59,
+  0x3e,0xcf,0x1e,0x0c,0x05,0x3b,0xf3,0x56,0x7c,0x7e,0x14,0x5e,0x8d,0x2d,0x8c,0x3b,
+  0x63,0xf2,0x84,0x32,0xfd,0xbe,0xad,0x92,0xd0,0x27,0xe0,0x45,0xcd,0xd5,0x25,0xdf,
+  0x0d,0x13,0xec,0x79,0x40,0x21,0x19,0x19,0x65,0x41,0x28,0x10,0x9d,0x49,0x3e,0x01,
+  0xf7,0x31,0x97,0x90,0x8f,0xc3,0xb4,0x16,0x71,0x6a,0x3b,0x9b,0x0e,0x41,0xaf,0xe1,
+  0x8c,0xca,0xb9,0xe1,0x43,0xa2,0xb6,0xc5,0xb5,0x55,0xfe,0x4a,0xd7,0xa1,0x45,0xc1,
+  0x90,0xeb,0x71,0xf9,0x01,0x71,0x28,0x12,0x30,0x36,0x45,0xe5,0x01,0x65,0xfa,0x7a,
+  0x01,0x5f,0x81,0x0e,0x43,0xff,0x2f,0x8e,0xab,0xcb,0x7e,0x13,0xe9,0x10,0x9e,0x90,
+  0xfa,0x28,0x2b,0x87,0xd7,0xa1,0xca,0x50,0xa3,0xee,0xb9,0xf0,0x7a,0xc8,0x83,0x02,
+  0x4b,0x82,0x36,0x75,0x7d,0x5d,0x4e,0x39,0xac,0x03,0x8f,0xd1,0xba,0x19,0x2f,0x5b,
+  0x17,0xfa,0x31,0x9e,0x0d,0xaf,0xa4,0x2f,0xa8,0x55,0xdd,0xc2,0x76,0xc2,0x3a,0xdd,
+  0xba,0xfe,0xd5,0xf4,0x7e,0xf0,0x16,0x3b,0xb7,0xad,0x13,0x1e,0xa3,0xcd,0xbd,0x7e,
+  0xb0,0xa7,0xc3,0x1b,0x32,0x54,0xf7,0x80,0xb2,0xed,0x21,0x70,0x1a,0xaa,0xc6,0x94,
+  0xd8,0xa3,0x90,0x24,0x61,0x60,0x7a,0x3b,0xc0,0xea,0xfc,0x90,0x48,0x40,0x00,0x78,
+  0x58,0xd5,0x45,0x42,0xaf,0x95,0xd4,0xb0,0x4c,0x47,0x82,0xa0,0x0a,0x39,0x86,0x42,
+  0x2f,0xe0,0xfb,0xbe,0x29,0x4d,0x3f,0xcf,0xd6,0x99,0xe7,0xe0,0xf7,0xd0,0x68,0x2c,
+  0x5d,0xf6,0xf2,0xce,0xd8,0x27,0xde,0xa0,0xe1,0x1a,0x96,0xce,0x6d,0xfb,0x04,0x6e,
+  0x36,0xd4,0x61,0x79,0x04,0x2e,0xc3,0xcd,0x6d,0xae,0xa8,0xfc,0x95,0x9c,0xe9,0xef,
+  0xb1,0x24,0x67,0x2f,0xd0,0xd9,0x45,0xc7,0x17,0xef,0x15,0xff,0xc0,0xaa,0xf1,0x1f,
+  0xb2,0x1b,0xc4,0x3f,0xe4,0xdc,0x64,0xac,0x1d,0x96,0xf7,0xe2,0xad,0x7a,0x5b,0xf0,
+  0xfa,0x57,0x61,0xfa,0xfa,0xba,0x92,0xd3,0xd0,0xa7,0x54,0x09,0x1e,0x0e,0xeb,0xa2,
+  0x17,0xf0,0x79,0xba,0x1c,0xa5,0xa2,0x0f,0x3c,0xa0,0xc6,0x58,0x29,0xa0,0x20,0x54,
+  0xc1,0x8e,0xa6,0xd7,0xb3,0x55,0xe9,0x32,0x76,0x83,0xcf,0xc8,0x2b,0x72,0x6c,0x8c,
+  0xed,0x87,0x90,0xb1,0xb8,0xd8,0x93,0x03,0xfb,0xc3,0xba,0xb1,0x58,0x73,0xaf,0x51,
+  0xf6,0x33,0x9d,0xde,0xf7,0xb8,0x34,0x7d,0xff,0xad,0xca,0x2e,0xe9,0x00,0xae,0x36,
+  0x8f,0xe2,0x7a,0xee,0x87,0xb9,0xb4,0x7a,0xe5,0xfa,0x7e,0xd8,0x6e,0x74,0x3f,0x64,
+  0x1d,0xb1,0xd6,0xf3,0xdd,0xf4,0x7e,0x88,0xcd,0x7c,0xb7,0xe4,0xbc,0xd2,0xd0,0x7e,
+  0xdb,0x6c,0x75,0x27,0x9c,0x1f,0xf6,0x18,0xae,0xc7,0x3b,0xe7,0xc2,0xf9,0xa6,0xfa,
+  0xd0,0x75,0x5b,0x71,0xfd,0xcf,0xb6,0x07,0x96,0xe3,0xf3,0x8f,0xa6,0xf5,0x55,0x62,
+  0xd1,0x4e,0x71,0x9e,0xe3,0xb2,0x6c,0xc6,0xd5,0x38,0x0f,0x28,0x3c,0x2a,0xbf,0xbb,
+  0xe8,0x7c,0x6b,0x70,0x05,0x6e,0x0c,0x3c,0x22,0xf0,0x48,0x54,0xbe,0x90,0xd6,0x3f,
+  0x5c,0x8b,0xe1,0xd7,0x5c,0x0f,0xf9,0xe2,0x4b,0xba,0x38,0x19,0xaa,0x85,0x7c,0x90,
+  0x75,0xa0,0xf5,0xf7,0x09,0x59,0x37,0x4e,0x42,0x40,0xcb,0x17,0xf2,0xe1,0xf4,0x7e,
+  0xf6,0xe6,0xd4,0xc3,0x51,0xa3,0x4c,0xf0,0xa4,0xfb,0x46,0xc8,0x6d,0xa9,0x88,0x5d,
+  0x33,0xc6,0xbc,0xf0,0x40,0x17,0xae,0xd8,0x0a,0xd6,0x07,0x6f,0x0a,0x5c,0x9f,0x18,
+  0x3b,0x9c,0xd9,0x0f,0x4a,0x0b,0x74,0x1a,0xde,0x81,0x3c,0xdd,0x93,0x0f,0x0f,0x47,
+  0xf5,0x91,0xcf,0x56,0x7b,0x9c,0x78,0xc4,0x97,0x44,0xb5,0x93,0x0b,0x3b,0x56,0xe9,
+  0xfd,0x79,0x7e,0xbc,0x7e,0xfa,0xf7,0x15,0xda,0x17,0xf4,0xb5,0xa2,0xcc,0xf4,0x7e,
+  0x83,0x39,0x60,0x0d,0xcc,0x33,0xd4,0x71,0x36,0x1b,0xd6,0xf0,0xfc,0x7b,0x5a,0xc7,
+  0x07,0x7e,0xc4,0x1f,0x91,0x4a,0x4d,0x75,0x95,0x67,0x34,0x7d,0x7d,0x24,0x72,0x2b,
+  0xfc,0x5c,0xdc,0x98,0xbc,0xcd,0x3b,0x63,0x36,0xff,0x95,0x58,0x80,0xda,0xa9,0xa8,
+  0x80,0xbd,0x22,0x6e,0x0e,0x39,0xef,0x94,0x67,0xc3,0x6f,0xc5,0x82,0x64,0xfe,0x6a,
+  0xe9,0x8c,0x67,0xfa,0x7a,0x2e,0xed,0x82,0x77,0x48,0xbb,0xc6,0xd4,0x51,0x98,0x80,
+  0xfa,0x45,0xae,0xb8,0x3a,0x86,0x0b,0xd5,0x60,0xb8,0xfc,0xf2,0x10,0xaa,0x9a,0x17,
+  0x07,0x51,0x23,0x0d,0x3c,0x30,0xbd,0x3e,0x4c,0x39,0x08,0x97,0xf1,0x26,0xce,0x51,
+  0x39,0xd8,0xb2,0xb6,0xe3,0x33,0xcb,0x5d,0x13,0xec,0x45,0x98,0x14,0x8d,0x21,0x57,
+  0x9d,0xf4,0x1d,0xf8,0xa4,0x03,0x4f,0x4d,0xc8,0x66,0x7a,0xff,0xf4,0x94,0x3c,0x2e,
+  0xf6,0xf1,0xd2,0x01,0x3e,0xce,0xea,0x59,0x87,0x5e,0x6a,0xa8,0xdf,0x61,0xb3,0xc4,
+  0x5e,0xf0,0x35,0xa9,0xdf,0x96,0x67,0x89,0x7d,0xb0,0xdb,0x44,0xfd,0x73,0x46,0x4c,
+  0xdf,0x1f,0xc4,0xe3,0x8b,0xf6,0xa1,0x9a,0xe2,0xcb,0x1d,0x77,0x88,0x4d,0xac,0xd2,
+  0x58,0x1c,0x60,0xa7,0x60,0x2f,0x54,0x1a,0xea,0x32,0x76,0x8a,0xbf,0x00,0xd7,0xd3,
+  0xf5,0x19,0xfd,0xa3,0x2b,0x0f,0x6a,0xbd,0x22,0x66,0x72,0x70,0x87,0x34,0x01,0x8a,
+  0x81,0xfa,0xe7,0x36,0x88,0x0b,0xdf,0xdd,0xaa,0x9b,0x6d,0x80,0x38,0xe8,0x6f,0xe3,
+  0xc2,0x26,0xd2,0xfb,0xb3,0x67,0xe6,0x00,0xfe,0xe8,0x7e,0xc3,0xb7,0x4b,0x5e,0x09,
+  0x47,0xb4,0x17,0x0d,0xd7,0x5e,0x79,0x4c,0x99,0x68,0x9a,0x1d,0xba,0xe6,0xa0,0x3c,
+  0xa6,0x5d,0x14,0x0b,0xdf,0x46,0xfd,0x79,0x26,0xbd,0x7f,0x84,0xb4,0x33,0x74,0x11,
+  0x82,0xc3,0xf3,0xfb,0xe4,0x1e,0x38,0xab,0xd5,0x1b,0xd7,0xc5,0x5f,0xde,0x29,0x26,
+  0xda,0x83,0xc6,0xd2,0x83,0x78,0x87,0x8b,0x22,0x48,0x1a,0x3b,0x99,0xde,0x3f,0xa5,
+  0xda,0x5e,0xf6,0xcf,0xd0,0xd8,0xb4,0x31,0xa9,0xd6,0xc1,0x9b,0x50,0x6d,0xa0,0x75,
+  0x9b,0x14,0x8f,0xf3,0xea,0xe5,0x6b,0x87,0x9b,0x83,0xf8,0x3d,0x56,0x93,0x62,0x37,
+  0x5b,0xa6,0x9f,0x7f,0x9b,0xf2,0x15,0xe8,0x36,0xab,0x3e,0xe2,0x5e,0xdc,0x36,0x91,
+  0x98,0x65,0xcd,0x8f,0x32,0xf1,0x36,0x0a,0x3e,0x77,0x15,0xec,0xe9,0xf0,0x98,0x68,
+  0x7f,0x93,0x46,0x7a,0x3f,0xe4,0x54,0xc0,0x3a,0x51,0x15,0xca,0xeb,0xf1,0x54,0xc1,
+  0x56,0xe1,0xb9,0xdb,0xd1,0xc7,0xc6,0xa0,0x27,0x8c,0x9f,0xc9,0x41,0xe6,0x8b,0xee,
+  0x17,0x1e,0x73,0x71,0xbc,0x29,0x99,0xde,0x6f,0xbc,0xd8,0x09,0x0f,0x23,0x1e,0xc0,
+  0x45,0x70,0x88,0xe8,0x22,0xaf,0xa1,0x06,0xd8,0x08,0xf4,0xc0,0x8a,0x16,0x35,0x8e,
+  0x78,0xe0,0x00,0xe8,0xa6,0xea,0x67,0x03,0xd2,0xf4,0xf2,0x43,0xfe,0x4a,0xed,0x10,
+  0x04,0x95,0xfc,0x18,0xda,0xf7,0x37,0x8c,0x80,0xe1,0xda,0xb7,0x63,0x0c,0x37,0x46,
+  0xc0,0x58,0x1c,0x57,0x2b,0x95,0x8b,0xd0,0x4b,0xef,0x6b,0xa6,0xf5,0xcf,0xf6,0x99,
+  0xe7,0xf8,0x6f,0xa1,0x31,0x31,0x3f,0x29,0xbf,0xc7,0xc7,0x50,0x11,0xa1,0x76,0x9a,
+  0x84,0x53,0xd0,0xd8,0xba,0xe9,0xb4,0x3c,0x19,0xfb,0x03,0x90,0xa1,0x97,0x47,0x73,
+  0xa6,0xd7,0xdf,0xbc,0x65,0x3c,0x3a,0x08,0xf5,0xdc,0x35,0x50,0xa6,0x8b,0x49,0x7f,
+  0x63,0x89,0x53,0xc8,0xe3,0x5d,0x93,0x7a,0x23,0x9f,0x35,0xd0,0x39,0xae,0x0f,0x79,
+  0xaa,0xb9,0x6b,0x18,0x11,0x42,0x7a,0xfd,0xb5,0x0f,0x94,0x5f,0x9b,0x9e,0xc1,0x82,
+  0x83,0x57,0xcd,0x87,0x03,0x86,0x6f,0xd8,0x7b,0xb0,0xe9,0x43,0xe3,0x40,0xb4,0xea,
+  0x1c,0x3f,0xc8,0xe6,0xc3,0x33,0x51,0xcf,0x88,0xba,0x0b,0xf5,0xf3,0xf4,0xfd,0x39,
+  0xf4,0x43,0xa7,0xd6,0x03,0x6a,0x79,0x20,0x47,0xd9,0x1d,0xf2,0x6d,0xe5,0x0b,0x98,
+  0xc9,0xe3,0xb4,0x02,0xe0,0x4e,0x40,0x07,0xda,0x77,0xdc,0x21,0x03,0x69,0xfd,0x63,
+  0xce,0xdc,0x85,0x3a,0xc8,0x63,0xb6,0x45,0xd9,0x0a,0x78,0x3e,0x07,0x15,0x91,0x60,
+  0x63,0xfc,0x80,0x56,0x05,0x3c,0xde,0x54,0x0e,0x4f,0xa3,0x7e,0xeb,0x14,0x6c,0x3c,
+  0xad,0x7f,0xa0,0x78,0x07,0x4f,0x28,0xf5,0xa6,0x2b,0xaa,0x7a,0xf8,0x84,0x14,0xd4,
+  0x96,0x88,0x2f,0x8d,0xf1,0x09,0x33,0x08,0xde,0xa8,0x3c,0x08,0x68,0x7f,0x05,0xea,
+  0x13,0x33,0xbd,0xdf,0x4e,0x8b,0x97,0xe0,0xbb,0xac,0x51,0xba,0x3d,0x24,0xbf,0xa4,
+  0x5d,0xd6,0x68,0x35,0xca,0xc6,0xf1,0x0b,0xba,0xd9,0x74,0x9d,0x9e,0x31,0x01,0x9f,
+  0x30,0x5c,0xb1,0xa4,0x3c,0x61,0x4c,0xef,0x07,0x53,0xdb,0x26,0x5d,0xe4,0xbd,0x89,
+  0x4d,0xf1,0x32,0xd4,0x4e,0x4a,0x6d,0xd4,0xd9,0x2b,0x8f,0x41,0xc2,0xc0,0x6d,0x16,
+  0x2d,0xdb,0xa5,0x1f,0xe1,0x01,0x5c,0xff,0x66,0x7f,0x06,0xef,0x29,0x55,0x10,0x37,
+  0x51,0x1b,0x47,0xd8,0x28,0xd4,0x2b,0x1e,0x23,0xff,0x41,0xf6,0x36,0xda,0xa3,0xaf,
+  0x79,0xd5,0x79,0x4c,0xf7,0x9f,0xd4,0xb7,0x93,0xe1,0xb8,0x37,0xfd,0xf3,0x26,0x73,
+  0xbe,0x86,0x1f,0x45,0x4c,0xbb,0x86,0x33,0xb4,0x25,0x2c,0xd7,0x68,0x75,0x36,0x0d,
+  0x28,0x9d,0x9a,0x4f,0x57,0xbd,0xac,0x93,0x09,0x53,0x87,0xc5,0x1a,0xab,0x4b,0xe3,
+  0x9f,0x90,0xe4,0x86,0x7d,0x91,0xd2,0x91,0x6b,0x56,0xe7,0xfe,0x4a,0xdf,0xfd,0x40,
+  0x69,0x8c,0xdf,0x07,0x47,0xf5,0x2e,0x81,0xf8,0xe7,0x4e,0x54,0x44,0x8f,0xc4,0x4b,
+  0x93,0xf8,0x0f,0xef,0x54,0xa6,0xf7,0x5b,0x2b,0x77,0xea,0x7b,0xc0,0x3f,0xd7,0x55,
+  0xda,0x79,0x14,0x3e,0x96,0x6a,0x7e,0xc1,0x6f,0x92,0xcd,0xa6,0x97,0x0d,0x9f,0xe9,
+  0xd2,0x3b,0x23,0xd0,0xaf,0xfb,0x5b,0x50,0xb1,0xb8,0x73,0xa7,0x9f,0xc7,0xc8,0x8f,
+  0x1b,0x93,0x5a,0x63,0xff,0x52,0xfc,0xd1,0x8d,0x09,0x68,0x84,0xf9,0xfd,0xcd,0x93,
+  0x78,0xa4,0x0a,0x5c,0x5a,0xd1,0x09,0xe3,0x23,0xbd,0x51,0xb8,0x12,0xf2,0x70,0x7a,
+  0xfd,0x7b,0x72,0xc6,0xc0,0x84,0xda,0xa4,0x33,0x5a,0x36,0x0a,0x67,0x44,0x2f,0xee,
+  0xb7,0xb2,0x31,0x54,0x53,0x0d,0x3a,0x7e,0xb6,0x83,0x70,0x38,0xb5,0xfe,0x67,0xd2,
+  0xfb,0x27,0x51,0x18,0x65,0x6b,0xa1,0x0c,0xf2,0x43,0x72,0x17,0xea,0xcf,0x52,0x81,
+  0xda,0x63,0x98,0xf4,0x89,0xe9,0x30,0x50,0xd1,0xaf,0x61,0xa8,0x91,0x42,0xec,0xa3,
+  0xf4,0xf3,0x9b,0xf0,0x23,0x78,0x52,0x54,0x8e,0x23,0xc8,0x79,0x13,0x76,0x88,0xd2,
+  0xa4,0x63,0x35,0x7b,0x0b,0xf6,0xe1,0xfb,0x5a,0x47,0x1e,0x8e,0x94,0xbe,0xad,0xae,
+  0x66,0xe3,0x69,0xbc,0xd4,0x5a,0x6c,0x12,0xc0,0xf7,0xe7,0x31,0x44,0xfa,0x02,0x0f,
+  0x73,0x60,0x2f,0x43,0x5c,0xf1,0x49,0x0e,0x85,0xf5,0x43,0x54,0xe8,0xba,0x0a,0x88,
+  0x7f,0xa6,0xf7,0xc3,0x28,0xe2,0xb7,0x33,0x30,0x3b,0xbe,0x44,0x97,0x13,0x70,0x46,
+  0x0a,0x74,0x14,0xc4,0xe4,0xf7,0xe1,0x02,0x04,0x05,0xc2,0x9e,0x51,0xf6,0x06,0xf4,
+  0x0a,0xdc,0x0f,0x17,0x32,0xf8,0x07,0xce,0xc2,0x5d,0xb0,0xb0,0xc4,0x65,0xca,0x71,
+  0x98,0xc4,0xf5,0xf9,0x22,0xe2,0x67,0x71,0x0e,0x05,0xd7,0x20,0x7e,0x26,0x23,0xc6,
+  0xcd,0x80,0xa7,0x32,0xf8,0x27,0xd2,0xfe,0xaa,0xf2,0x8b,0xc2,0x00,0xc1,0x9e,0xff,
+  0x06,0x87,0x50,0x8d,0x3b,0xa3,0x45,0x23,0x2d,0xe7,0x63,0x9e,0x90,0x4b,0xeb,0x54,
+  0x62,0x87,0xa2,0x01,0xc3,0xa9,0xc9,0x2c,0x83,0x7f,0x94,0xe5,0xa1,0x75,0x03,0x9e,
+  0x56,0x75,0x2b,0x9b,0x8b,0xc0,0xa6,0xca,0x28,0xf9,0x3e,0xea,0x87,0xfd,0xe2,0x9e,
+  0x90,0xfa,0x90,0x63,0xae,0x78,0xbd,0x09,0x77,0x54,0x54,0x0e,0xa5,0xed,0x4b,0x89,
+  0xe2,0x83,0x1f,0xc2,0x0e,0x43,0x3d,0xce,0xbe,0xc1,0x36,0xc2,0x7c,0xe3,0xd1,0x61,
+  0x76,0x4e,0x79,0x01,0x3e,0xd3,0xaa,0x0e,0x7b,0x6a,0x60,0x23,0x94,0x19,0x91,0x61,
+  0x96,0xfe,0x79,0x81,0x2b,0xc5,0xb1,0x35,0xde,0xd2,0x36,0x75,0x59,0x98,0x84,0xca,
+  0xb6,0x75,0xcb,0xc2,0x27,0x62,0xcf,0x7a,0xe7,0x2d,0x96,0xef,0x7d,0xa0,0x38,0xf6,
+  0x08,0x9e,0xca,0x5b,0x16,0x6e,0x4a,0x5f,0xdf,0xc7,0x43,0xe2,0x0d,0x3d,0xc0,0x5d,
+  0x16,0xec,0xd1,0x1b,0x78,0x5e,0x58,0x4e,0x8a,0x3e,0xfd,0x69,0x3a,0x42,0x88,0x28,
+  0x90,0xe7,0x1c,0x90,0x0b,0x58,0x1a,0xff,0x38,0x07,0x63,0x68,0xd6,0x09,0xe4,0xe0,
+  0xf7,0xe2,0x0d,0xb6,0x55,0x45,0xa5,0xe5,0x68,0xbf,0x6a,0xd1,0xac,0x17,0x8d,0xf0,
+  0xf3,0xf0,0x53,0xb2,0xef,0xef,0xe6,0xa6,0xf1,0x06,0xe2,0xa5,0x0f,0xa0,0xba,0xbd,
+  0xe0,0xb8,0x5c,0x13,0x3b,0xe4,0x0f,0x7c,0x6e,0x16,0xc1,0x9e,0xd7,0xf4,0xc6,0x36,
+  0x27,0x1e,0x81,0xd7,0x50,0xd1,0x39,0x37,0xcb,0xb9,0xd2,0xf4,0xfa,0xd7,0x41,0xa9,
+  0x1e,0x01,0x8f,0x82,0x6a,0x41,0x87,0x88,0xdf,0xa3,0x91,0x60,0x44,0x00,0xf5,0x43,
+  0x87,0xa3,0x14,0xd6,0x83,0xa7,0x0b,0x8f,0x14,0xa4,0xd7,0x93,0xdf,0x31,0x78,0x7c,
+  0x5b,0x61,0x8f,0x51,0x51,0xc8,0x14,0xe8,0xd0,0xf5,0x25,0xbc,0x90,0x75,0x41,0x87,
+  0xe6,0x33,0x38,0xe2,0x3d,0xa3,0x43,0xf3,0x18,0x78,0x84,0x49,0xd3,0xd7,0x97,0xe4,
+  0x20,0x68,0x34,0x50,0x45,0x45,0x51,0xdb,0xac,0x33,0x3c,0x29,0x20,0x84,0x3f,0x44,
+  0xab,0x81,0x82,0x81,0x1e,0x8d,0xc1,0x1f,0x62,0xb9,0x19,0xfc,0xa3,0xec,0xe4,0xef,
+  0xa1,0x19,0x2a,0x88,0xb2,0x39,0xfa,0x67,0xf1,0x69,0xf9,0x0f,0x3b,0x77,0xe2,0x0f,
+  0x1d,0x5c,0x86,0x88,0x77,0x2e,0x1c,0x32,0xfc,0xed,0xce,0xad,0xb2,0xb7,0x6b,0xfa,
+  0x7d,0x9f,0x86,0x9d,0xb0,0x5b,0xa0,0x35,0xff,0xb4,0x3a,0xe2,0x3e,0x0f,0x07,0x97,
+  0xcf,0x47,0x35,0xc5,0xd0,0xbe,0x87,0x50,0x18,0x61,0x67,0xe1,0x45,0x63,0x7e,0x54,
+  0x3d,0x93,0xb6,0x5f,0x5e,0xdc,0xc4,0x27,0x5b,0x03,0x04,0xaa,0x25,0x18,0x36,0x02,
+  0xe0,0x64,0xcd,0xba,0x81,0x88,0x54,0x6b,0x00,0x19,0xe0,0x24,0xc7,0x23,0x20,0x3b,
+  0xba,0xa6,0xf7,0xbf,0x0e,0x37,0x72,0xc4,0x3f,0xf1,0x82,0x58,0x93,0x57,0xff,0x81,
+  0xe2,0x11,0xde,0x24,0xab,0xa0,0x65,0xd9,0xce,0xc7,0x50,0x8d,0x1c,0xe5,0x9e,0x0e,
+  0x1e,0x63,0x3c,0x83,0x7f,0xbe,0xb7,0x24,0xdc,0x69,0xf4,0x9c,0x5b,0x5c,0x82,0xcb,
+  0xf2,0x30,0x78,0x4d,0xee,0x73,0x28,0xee,0x0e,0x11,0x0b,0x39,0xfc,0xeb,0xf3,0x3d,
+  0xe1,0xae,0x98,0xb9,0xc2,0xdf,0xe6,0x48,0xeb,0x9f,0x52,0x49,0xc1,0xcf,0xf6,0x29,
+  0xf3,0xea,0x6f,0xb8,0x1f,0x87,0x47,0x60,0x5e,0x82,0xfb,0xc3,0xb3,0x40,0x36,0xb7,
+  0x99,0xeb,0x61,0xbb,0xa2,0x3f,0x00,0x77,0x93,0x69,0xe3,0x46,0xfa,0xfe,0x30,0x1b,
+  0x5e,0x16,0x37,0x9e,0x76,0xd5,0xa9,0x3f,0x82,0xb7,0x22,0x37,0xbd,0x6d,0xac,0x96,
+  0x0b,0x10,0x11,0xf9,0xf1,0x43,0x46,0xfc,0x33,0x80,0x82,0x73,0xb5,0xec,0x48,0xfb,
+  0x5f,0xbc,0x70,0x97,0xf2,0x3e,0xd4,0x92,0x51,0x43,0x6b,0x1e,0xaa,0x3d,0xb1,0x89,
+  0xf0,0x0f,0x5a,0x7c,0x73,0x23,0xae,0x0f,0x3f,0x83,0xc2,0x52,0xc4,0x3f,0x69,0xff,
+  0xcb,0xc8,0x19,0x93,0xfe,0x49,0x2c,0x4c,0x16,0x4c,0xc8,0x97,0xe0,0xf2,0xe3,0x37,
+  0x25,0x1d,0x37,0xca,0x41,0xbc,0x7f,0xf5,0xa8,0x6b,0xa2,0xb9,0xa2,0xfd,0xe8,0xe6,
+  0xea,0xa4,0xeb,0xbc,0x3c,0x9c,0xc1,0x3f,0x85,0xcf,0xed,0x5c,0xa3,0x97,0x0e,0xf2,
+  0xaf,0x87,0x4f,0x29,0x7f,0x8c,0xde,0xf0,0x2a,0x5f,0x1d,0x9e,0xa5,0xff,0x13,0x2f,
+  0x7d,0x3b,0xef,0xaf,0xc2,0x57,0x85,0x1e,0xa8,0x2b,0x1d,0x54,0xff,0x3e,0x7c,0x26,
+  0xfd,0xfb,0x3e,0x04,0x5b,0x17,0xad,0x85,0x72,0xf3,0x33,0xab,0xd8,0x29,0x63,0x1f,
+  0x9a,0x2d,0xc7,0xbd,0x6c,0x56,0xd3,0x5a,0x98,0x67,0x2e,0x5e,0xc5,0x9c,0x5d,0x61,
+  0xb8,0x7b,0x40,0x5d,0xe5,0x4e,0x6a,0xd3,0xeb,0xbf,0xa2,0xf8,0x0c,0xeb,0x6c,0x5f,
+  0x7e,0x22,0xaf,0x86,0x0d,0x69,0x7b,0x58,0xf9,0x30,0x6f,0x60,0xf9,0xfc,0x61,0x53,
+  0x1f,0x96,0x1a,0x58,0x81,0x16,0x36,0x96,0x8f,0xab,0x75,0xec,0x64,0x7a,0x7f,0xea,
+  0x33,0x9f,0xd6,0x5e,0x36,0x6a,0xfb,0x5d,0x7d,0xec,0x77,0xd2,0xe5,0x64,0x63,0xd2,
+  0xb1,0x55,0x76,0xc1,0x11,0xf1,0x7c,0x12,0xfd,0x6b,0x14,0xcc,0xc0,0xb0,0xeb,0x20,
+  0xe2,0xdb,0xe9,0xe7,0x11,0x90,0xd4,0xdf,0xd3,0xeb,0x13,0x05,0xfe,0xce,0x31,0xf3,
+  0x7d,0xbd,0x6e,0xc0,0x55,0xb3,0x63,0x4c,0xbc,0xc3,0x1b,0x06,0x50,0x9f,0x8f,0x89,
+  0x8f,0xf0,0x94,0xab,0xf7,0xf3,0x19,0xfb,0xdb,0xa1,0x4d,0xc0,0x31,0xa8,0x1e,0xce,
+  0x1f,0x97,0x1b,0xe1,0x08,0x2b,0x33,0x9d,0xc3,0x72,0x95,0xb2,0x29,0x56,0x64,0xde,
+  0x36,0x5e,0xd6,0xc0,0x8e,0x1a,0x53,0xf8,0x67,0xfa,0xfa,0x7e,0xf8,0x1b,0x78,0xc6,
+  0xa8,0x30,0x13,0x71,0xd9,0xc9,0xba,0x59,0x85,0xc9,0x0f,0x22,0xec,0xe9,0x46,0xd8,
+  0xc3,0xfb,0x50,0x23,0xad,0x37,0xb7,0x23,0xfe,0x69,0x1a,0xb7,0xe1,0x1f,0x6f,0xe9,
+  0x63,0x3c,0x64,0xe6,0xf5,0x32,0x1f,0x74,0x02,0x5d,0xcf,0x7c,0xe2,0x19,0xa8,0x48,
+  0xe0,0xf5,0x15,0xfc,0x79,0xe6,0x31,0xbb,0xe3,0x1e,0x1b,0xfe,0x51,0x40,0xec,0x06,
+  0xef,0x70,0x89,0xbf,0x62,0x25,0x74,0x72,0xaf,0xe9,0x0d,0xfc,0xad,0x93,0xed,0x80,
+  0x1e,0x73,0x54,0x5b,0xef,0x84,0xcd,0x53,0xf8,0xa7,0x70,0x7a,0x3f,0x88,0xfc,0x15,
+  0xf0,0x6b,0xdc,0xed,0xb7,0xc5,0x67,0x54,0xf2,0x63,0x70,0x93,0xb9,0xe4,0x59,0xd9,
+  0x47,0x11,0x89,0xc4,0x86,0x5e,0xd9,0x17,0xb9,0x00,0x01,0x0b,0xff,0xc8,0xd3,0xfb,
+  0x33,0x76,0xed,0x44,0xeb,0x87,0x29,0x90,0x73,0x70,0xd7,0x45,0x14,0xae,0x3b,0x5b,
+  0x3a,0x09,0x6f,0x41,0xed,0xf0,0x52,0x3f,0x3a,0xf2,0x63,0x53,0xf8,0x27,0x37,0x83,
+  0x37,0x7e,0x05,0x6f,0x56,0x7e,0x7b,0x70,0xc9,0x59,0xf9,0x20,0xfa,0xdf,0xd5,0xa6,
+  0xef,0xa4,0x5a,0xd3,0x74,0x0c,0x1a,0x75,0xdf,0x73,0x32,0xae,0x8f,0x67,0x41,0x9e,
+  0xf3,0x7e,0x1b,0xfe,0x31,0xb5,0x0f,0x71,0x11,0xaa,0x4f,0xf1,0x3f,0xb2,0x83,0x20,
+  0x0c,0xfd,0x0b,0x5c,0x0b,0xcf,0xd1,0xba,0x9d,0x55,0x31,0xde,0xcb,0x7e,0x06,0xeb,
+  0xa3,0x1e,0xc1,0x11,0x1f,0xa6,0x7f,0xdf,0x44,0xce,0x10,0xee,0x21,0xaf,0xd9,0x8a,
+  0xfe,0xb8,0x58,0xbf,0xc2,0x9b,0xe0,0x6e,0x56,0x6e,0x76,0xea,0xbe,0x0e,0x47,0x31,
+  0x73,0x1a,0x4f,0x83,0xee,0xe7,0x01,0x96,0x89,0x0f,0x98,0x33,0x7f,0x0a,0x91,0x45,
+  0x9e,0x7e,0xbc,0xc9,0x06,0xde,0x2d,0x9e,0x36,0xf9,0x66,0x5c,0x76,0xf4,0x67,0xa3,
+  0x8e,0xb8,0x7b,0x17,0xc7,0xeb,0x75,0x3c,0x35,0x9e,0xc6,0xc3,0xa6,0xf4,0x5b,0x78,
+  0x43,0x5c,0x6d,0xfa,0xe2,0xf2,0x2e,0x30,0x23,0xf5,0xe6,0x86,0xa8,0x3c,0x03,0x8e,
+  0x18,0xc1,0xbd,0x05,0x71,0xd9,0xa7,0xbc,0x1f,0xeb,0x25,0x43,0x3c,0x7c,0xcb,0xf4,
+  0xfd,0x63,0x52,0x03,0xfc,0x21,0x86,0x68,0x67,0x95,0xdc,0x00,0x93,0x7c,0xa1,0xb9,
+  0xf4,0xa4,0x7c,0x0e,0x2e,0xc7,0x1a,0x45,0xde,0xb8,0x7a,0xbf,0xfe,0x97,0x4d,0x8d,
+  0xe6,0x7c,0x5c,0x9f,0xb4,0xfe,0x19,0x84,0x9f,0xc1,0xfb,0x46,0xfd,0xcb,0xd6,0xf7,
+  0x78,0x58,0xab,0x4d,0xa0,0x5a,0xd3,0xe1,0x08,0xda,0x47,0x3c,0x32,0x26,0x21,0xfe,
+  0x04,0x44,0x44,0x19,0xfc,0x63,0xe6,0x38,0xe0,0x99,0xcf,0x95,0x8d,0xab,0xe3,0x0f,
+  0xdf,0xaf,0xad,0x1f,0xd4,0x87,0xf9,0xcc,0x8a,0x72,0xfc,0x05,0x7d,0x42,0xed,0x65,
+  0x6f,0x89,0x3d,0x08,0xed,0xf8,0x5e,0xc4,0x3f,0xd3,0xfb,0x21,0x99,0xb3,0xa4,0x6c,
+  0x3b,0xf3,0x0e,0xe2,0x8f,0xee,0x54,0x62,0x52,0xf9,0x60,0x1b,0xaa,0xe5,0xbc,0x30,
+  0xf8,0x62,0x72,0x9c,0xbd,0xa6,0x69,0x64,0xc1,0x6b,0x98,0x3f,0x13,0xff,0x91,0x82,
+  0xd2,0x8f,0xc5,0xbc,0xf7,0xd4,0xd5,0x8e,0xdb,0x8d,0x9d,0xa2,0x34,0xe4,0xf8,0x4b,
+  0x0d,0x61,0x8f,0xa8,0xdc,0xae,0x52,0x60,0xe4,0x39,0x51,0x96,0xf4,0xae,0x66,0x77,
+  0xda,0xe2,0x3f,0x4e,0xf6,0x0e,0xac,0x1e,0x55,0xe3,0x65,0x05,0xee,0xd3,0x50,0x63,
+  0x16,0x5c,0x23,0x97,0xeb,0xfd,0x9f,0x73,0xc6,0x36,0x5d,0x53,0x34,0xd4,0xde,0x5b,
+  0xe8,0x37,0x9c,0x7e,0xf9,0xea,0x4c,0xfc,0xe7,0x87,0xbb,0xe0,0x7f,0x90,0xfe,0x19,
+  0xef,0x7c,0x61,0xfd,0x5b,0xd0,0x38,0x98,0x1f,0x6d,0x9e,0x84,0xef,0x5e,0x65,0x01,
+  0xc5,0x31,0xed,0x92,0x62,0xed,0x9f,0xe1,0xdc,0xe9,0xf5,0x21,0xfc,0x73,0x18,0x82,
+  0x03,0xf3,0xf7,0x4a,0x63,0xe2,0x90,0x52,0x6b,0xaa,0x64,0xf8,0x2e,0x4a,0x0d,0x31,
+  0x5c,0x76,0x72,0xdc,0x82,0x80,0xc2,0xe1,0x4c,0xfc,0xe7,0xa1,0xc7,0xe1,0x01,0x69,
+  0xb5,0x39,0xeb,0xde,0xce,0x06,0xf8,0x47,0x2b,0xfe,0x13,0x38,0x05,0x7f,0x64,0x95,
+  0xc2,0xb1,0xaa,0xe9,0x14,0xfa,0x5f,0x08,0x84,0x56,0xb1,0x0b,0xe9,0xf5,0x14,0xf0,
+  0x22,0x5b,0x2b,0x2a,0x47,0x1c,0xf5,0xec,0x47,0xc6,0x5a,0xc4,0x3f,0xea,0x9d,0xee,
+  0x5f,0xc1,0x3e,0x73,0x7e,0x8c,0xe3,0xfb,0x2e,0x42,0x20,0xa4,0x53,0xfc,0xc7,0x86,
+  0x7f,0x86,0x38,0x7d,0x86,0xe8,0xb4,0xa2,0xa3,0xd1,0xa4,0x8f,0xa0,0xb6,0x19,0xea,
+  0xda,0x03,0xbe,0xed,0x6d,0x75,0x9e,0x21,0x05,0x85,0x71,0x87,0x3d,0xfe,0x93,0x9c,
+  0xf9,0xa8,0xf1,0xaa,0x19,0x14,0x08,0x7b,0x7a,0xb4,0x57,0x97,0x23,0x5a,0x7b,0x5a,
+  0x3e,0x2f,0x5d,0x32,0x1b,0xc3,0x84,0x7f,0x72,0x2e,0x41,0x63,0x5f,0x76,0xfc,0x07,
+  0x92,0x30,0x51,0x53,0xaf,0x15,0x40,0x51,0x8c,0x4f,0xf0,0xe7,0x29,0xfa,0x61,0x4a,
+  0xa3,0x3c,0x08,0xae,0x0e,0x74,0xbb,0x26,0x60,0x16,0x9b,0xdf,0x65,0xc3,0x3f,0x5c,
+  0x1b,0x41,0x6b,0x58,0x4f,0xa0,0xa5,0x8b,0x1f,0xc2,0xf5,0x55,0xa3,0xcd,0x78,0x24,
+  0x37,0xd8,0xba,0x49,0x43,0xfb,0x78,0x96,0xa3,0x7d,0xff,0x81,0x3d,0xfe,0xa3,0x7c,
+  0x19,0xcd,0x6e,0xc5,0x1d,0x87,0x29,0xec,0x73,0xa8,0xb5,0x76,0x19,0x27,0xfc,0xf3,
+  0x94,0x15,0xff,0x69,0xfa,0xb1,0xb1,0x9f,0x21,0xfe,0xf9,0x91,0x2d,0xfe,0x53,0x22,
+  0x55,0xd2,0xf5,0xed,0x91,0x28,0xdb,0xc9,0xd6,0x41,0x85,0xe1,0x88,0xa2,0xff,0xb5,
+  0x4e,0xaa,0x32,0x16,0x47,0xdd,0xe5,0x9c,0xe2,0x15,0xdc,0x1e,0xff,0xe1,0x4a,0xb9,
+  0xd2,0xe1,0xf5,0xb6,0x5d,0xed,0x1e,0x50,0x76,0xae,0x9b,0xe7,0x6b,0x53,0x35,0x36,
+  0x18,0xdb,0xe6,0xf5,0x19,0xaa,0xfb,0xd5,0xae,0xd8,0x6e,0xaf,0xde,0xb6,0x4e,0xb3,
+  0xf9,0x5f,0x75,0xf9,0x21,0x48,0xe8,0xf5,0xdc,0x19,0x9e,0x11,0x43,0x30,0x1e,0xe0,
+  0xb7,0x0b,0xc4,0x3f,0x11,0x1d,0xdf,0x37,0x5c,0xe4,0xed,0x9a,0xd0,0xe3,0x1c,0x3d,
+  0xa6,0x37,0xd3,0xfa,0xe7,0xe4,0xa7,0x4f,0xb0,0x4f,0x20,0xb8,0xd8,0xb5,0xb9,0x73,
+  0x24,0xf6,0xc1,0xbc,0x85,0x6d,0xbe,0xe3,0xe1,0x73,0xdb,0x3f,0xf1,0xa2,0x5b,0x71,
+  0x3c,0x3c,0x42,0x11,0xd7,0xc3,0x78,0x2a,0x83,0x7f,0x4a,0x72,0xce,0xc1,0x3f,0x48,
+  0x8d,0x2d,0xfc,0x38,0x2f,0xdf,0xfe,0x1a,0xf9,0x6b,0xc3,0x72,0x4d,0xfb,0x21,0xbd,
+  0xda,0x58,0xf2,0x4b,0xf9,0x9c,0x82,0x40,0xa2,0x05,0x35,0x76,0x26,0xfe,0xb3,0x5a,
+  0x5b,0x01,0x7d,0x52,0x95,0x62,0xc5,0x7f,0x22,0x73,0xab,0x4a,0x54,0x08,0x7b,0x8d,
+  0xc8,0xbc,0x0a,0xe1,0xe8,0x64,0xa7,0xc1,0x02,0x42,0xe1,0xb0,0x2d,0xfe,0x73,0x4b,
+  0x4b,0xc9,0x43,0x84,0x76,0x8a,0xdc,0xca,0xce,0x8e,0x3c,0xdf,0xe7,0xd5,0x28,0x53,
+  0xb4,0x6d,0x35,0x15,0x06,0x2a,0xa2,0x41,0xa3,0xa3,0xd0,0x47,0x42,0x26,0xfe,0x53,
+  0x32,0x73,0xa7,0xb1,0x5f,0xaf,0x32,0xbc,0x51,0x40,0xd8,0x53,0x8a,0xcb,0xbe,0xd9,
+  0x51,0x9e,0xfb,0x54,0x7b,0x45,0x0b,0x2e,0xec,0x08,0x5b,0x97,0x0a,0x0d,0xd9,0xe3,
+  0x3f,0xbf,0x81,0xd7,0x63,0x41,0x43,0x89,0x4a,0xf4,0x7b,0x05,0x11,0xd6,0xca,0xe5,
+  0xf0,0x1e,0xac,0x5e,0xe5,0x7c,0x14,0x3d,0xa6,0x43,0xa5,0xc1,0x90,0xcf,0x1e,0xff,
+  0x19,0x95,0x76,0x82,0x15,0xff,0x21,0x6b,0x8e,0x42,0xbb,0x05,0x14,0x5f,0xef,0xc0,
+  0x7f,0xb8,0xb5,0x6c,0x10,0xce,0x6b,0xc1,0xd6,0xac,0xf8,0x8f,0x57,0x8b,0x19,0x13,
+  0x2c,0xc0,0x9d,0x50,0x96,0x54,0x4e,0x36,0x05,0x60,0x06,0xc2,0x4e,0x18,0x5f,0x54,
+  0x5b,0x8c,0x1b,0x4f,0x87,0x09,0x25,0xa8,0x39,0xc3,0x59,0xf1,0x9f,0x9b,0xe0,0x43,
+  0x28,0x8b,0x3a,0x10,0xff,0x68,0x0f,0x1a,0x65,0x5b,0xd4,0x91,0x36,0xaf,0xfe,0x3c,
+  0xb0,0xd8,0x91,0x1e,0x76,0x23,0x42,0xfd,0x2a,0x74,0x1d,0xec,0xf1,0x9f,0x9c,0x3f,
+  0x8b,0x6e,0x6f,0xaf,0x20,0xd0,0xb2,0x12,0x1e,0x36,0xd0,0xfa,0xd4,0xe5,0x56,0x41,
+  0x35,0x5a,0x7c,0x75,0x41,0xae,0xb3,0x63,0x07,0x54,0x99,0xfc,0x06,0x5b,0xfc,0x27,
+  0xb6,0xa8,0x18,0xb6,0x0b,0x2f,0x7e,0xa4,0x6e,0xa7,0x99,0x23,0x24,0x43,0xfd,0x86,
+  0x67,0x16,0xec,0xa3,0x40,0xca,0x6a,0x36,0x4b,0x7f,0x12,0x2a,0x13,0x79,0xab,0xdc,
+  0x99,0xf8,0x4f,0x4f,0xe4,0x2a,0x78,0x57,0x7c,0x2b,0xe9,0xac,0xfb,0xd2,0x17,0xc5,
+  0x3f,0x89,0x05,0x49,0x95,0x60,0xcf,0x4b,0xc9,0x1b,0x42,0xae,0x09,0x2b,0xfe,0xd3,
+  0x38,0xe2,0x5b,0x2d,0xdb,0xe2,0x3f,0x9f,0xde,0x89,0x0f,0xf9,0x9c,0x81,0xda,0xf5,
+  0x83,0x18,0xa1,0xc1,0xee,0xb8,0x84,0xf8,0x47,0xc2,0x15,0x43,0x20,0xa4,0xbd,0x0f,
+  0xc1,0x53,0x9b,0x62,0xf6,0xf8,0x8f,0x74,0xc2,0x7c,0x25,0x7e,0x53,0x72,0x03,0xe1,
+  0x9f,0x97,0x45,0x75,0x32,0xff,0x24,0x01,0xa1,0x8e,0xfa,0xbb,0xf1,0xfe,0x41,0x7e,
+  0x24,0x7a,0x73,0xd2,0x79,0x1e,0x81,0x62,0x06,0xff,0x7c,0x1f,0xba,0xdc,0xfa,0x28,
+  0x3f,0xcb,0x36,0x40,0x57,0xbc,0xd4,0xe0,0xf9,0xe1,0xbb,0x60,0x1f,0x83,0x95,0x79,
+  0xed,0xee,0xd9,0xe2,0xc9,0x58,0x65,0xc2,0x31,0xce,0x9e,0xee,0x9a,0xbe,0x3f,0x88,
+  0x2d,0x03,0x5b,0x42,0x7f,0x13,0x41,0x37,0x6d,0x16,0x6c,0xd2,0xd1,0x5f,0x6b,0x67,
+  0xa7,0x60,0x5f,0xc9,0xbc,0x96,0xee,0x55,0xac,0x58,0x3c,0x19,0x9a,0x6f,0xf6,0xac,
+  0x62,0x46,0x26,0x5e,0x5d,0xfc,0x0a,0x47,0xb7,0xcb,0x28,0xf1,0xbb,0x77,0x41,0x87,
+  0xd0,0x43,0x11,0x8d,0x2d,0x95,0xf6,0x38,0xbd,0xcb,0xf2,0x34,0x54,0xb2,0x3b,0x50,
+  0xff,0xb4,0x65,0xc7,0x7f,0x3a,0xd1,0xc7,0xab,0x17,0x68,0xbf,0x1a,0xf8,0xa1,0xb6,
+  0xc0,0x3d,0x4b,0xb6,0xa2,0xda,0xc4,0xe7,0x5f,0x86,0xef,0xeb,0x83,0xf7,0xe1,0xe6,
+  0x61,0xd4,0x3f,0x7f,0x9b,0x89,0xff,0xc0,0x87,0x62,0x62,0x51,0x30,0x8a,0xeb,0xb3,
+  0x8b,0x9d,0x0d,0xbd,0xd8,0x5e,0xd5,0x25,0x2d,0x1f,0x3c,0x80,0xfe,0xc5,0x8c,0x3e,
+  0xf4,0x40,0x0f,0x88,0xe0,0xe0,0xd2,0x98,0x1c,0x4b,0xef,0x1f,0x49,0x3b,0x07,0x43,
+  0xb0,0x40,0x38,0xdf,0x28,0x9b,0x44,0x6f,0xa2,0x9a,0xc2,0xb0,0x97,0x70,0x3d,0xf1,
+  0x43,0xeb,0x93,0x2f,0x45,0x2e,0x2b,0x8d,0x03,0xce,0xd3,0xb6,0xf8,0x8f,0x50,0xbe,
+  0x26,0x4d,0x88,0xed,0x5b,0xd1,0xc8,0x8e,0x21,0xcc,0xad,0x58,0x55,0xb0,0x95,0xbd,
+  0xcb,0x0f,0x28,0x73,0x29,0x10,0xf4,0x36,0x85,0x46,0x4d,0xc4,0xcf,0xf6,0xf8,0xcf,
+  0x5c,0xbe,0x35,0xe2,0x89,0x78,0xe3,0x6c,0x17,0x8b,0x44,0x3c,0xf7,0xa0,0xe3,0x36,
+  0x26,0x0e,0x50,0xfc,0x79,0x37,0xde,0xe1,0x19,0xba,0x5e,0x30,0x3b,0xfe,0xc9,0x85,
+  0x1e,0xd0,0x1f,0xe0,0x7e,0xf7,0x10,0x08,0xdd,0x6b,0x5c,0x0d,0xdb,0x11,0x28,0x02,
+  0xea,0x9f,0x1a,0xf7,0x51,0xd8,0xa3,0xe3,0xf5,0x1c,0xec,0xf1,0x9f,0xe5,0x5d,0x11,
+  0x16,0x88,0xa2,0xd9,0x7d,0x1c,0x0e,0x29,0x7e,0xc3,0xf5,0x50,0xb3,0xb5,0x1f,0x5a,
+  0x29,0x50,0x16,0x79,0x9f,0x37,0x9a,0xb8,0x3e,0x76,0xfc,0x33,0x62,0xdc,0x2f,0x35,
+  0x88,0xa5,0xe3,0xf2,0x64,0xf9,0x0b,0x5a,0x23,0x39,0x26,0x93,0x70,0x19,0x3e,0x75,
+  0xeb,0xd2,0x71,0x66,0xb6,0x5c,0x46,0xfc,0x33,0x3f,0x69,0xc7,0x3f,0x39,0x1f,0xc1,
+  0xef,0x16,0x2c,0x1c,0xcc,0x3f,0x57,0x76,0x69,0xd1,0xfb,0xd1,0x9b,0x47,0x9c,0x1f,
+  0x77,0xee,0x1d,0x18,0x8a,0xfa,0xe7,0xf8,0x3e,0x56,0xaf,0x86,0x9f,0x47,0x17,0x8c,
+  0x3b,0xc7,0x55,0xbf,0x2d,0xfe,0x93,0xd4,0xbb,0xfd,0x55,0x08,0xfb,0x11,0xdf,0xd2,
+  0x6a,0xcc,0x3b,0x87,0x8a,0x3a,0xa2,0xe0,0x17,0xf4,0x1c,0xa3,0xfc,0x94,0x27,0xc1,
+  0x6b,0xc3,0x7a,0xc6,0xff,0xca,0x31,0xc5,0x0e,0xcf,0xf2,0x44,0x6b,0x20,0x77,0xa8,
+  0x6b,0x47,0xa9,0x2f,0xb1,0x28,0xc0,0x72,0x94,0x88,0x84,0x3e,0x5b,0x8d,0xdb,0x17,
+  0xdf,0xa1,0xeb,0x78,0x3d,0x6b,0xb2,0xc5,0x7f,0x3a,0x69,0xd1,0xba,0x78,0x3c,0x3c,
+  0x26,0x6e,0xc2,0xd5,0xc8,0x8b,0x3b,0xf0,0xfe,0x1d,0x15,0x49,0x88,0x23,0x10,0x7a,
+  0xaa,0x4b,0x37,0xf1,0xa7,0xf1,0xa7,0xf5,0x8f,0x31,0xf3,0x9d,0x12,0xf4,0x17,0x86,
+  0x9d,0x7d,0xb8,0x6d,0xde,0x57,0x82,0x26,0x5a,0xdb,0x9d,0x30,0x10,0x0b,0xac,0x40,
+  0xa1,0x80,0xbf,0x2f,0x7a,0x09,0x1a,0x69,0xe9,0xfd,0x93,0x94,0xe2,0xfc,0x2d,0xe9,
+  0xe6,0x64,0xc1,0x05,0xf9,0x92,0x7e,0x59,0xcc,0x1f,0x2e,0x18,0x6f,0xfe,0xd0,0xb8,
+  0x04,0xd7,0x21,0x8c,0x2c,0x9a,0xe4,0xb8,0x3e,0xa3,0x68,0xdf,0x27,0xd2,0xfb,0xc7,
+  0xd4,0x62,0x88,0x76,0x9e,0x1b,0xbe,0x6e,0x8b,0xec,0x93,0x8f,0x14,0x06,0xcc,0x25,
+  0x7e,0xd9,0x87,0x16,0xbf,0xde,0x50,0x10,0x5f,0xa1,0x63,0x12,0xa0,0xff,0xa2,0x2d,
+  0xfe,0x93,0x53,0x6a,0x6c,0x3a,0xee,0x39,0xa5,0xee,0x6b,0xaa,0x84,0xee,0x3b,0x3c,
+  0xbf,0xe2,0xbf,0x7f,0xb0,0x72,0xd1,0x1b,0x77,0xd6,0x9e,0xd8,0xf8,0x7b,0xc7,0xfc,
+  0xe1,0x43,0xed,0xb5,0xc9,0xfc,0xdf,0xb3,0x80,0x0d,0xff,0x18,0xc6,0xc3,0x39,0xe5,
+  0xfd,0xaa,0xbf,0xe9,0xa8,0xb4,0xa3,0xc3,0x93,0xdc,0x5a,0xc7,0xe6,0x1a,0x61,0x31,
+  0x77,0xc4,0xb1,0x9f,0x81,0xf2,0x58,0x21,0x7e,0xaa,0xfb,0xb3,0xe2,0x3f,0xfe,0xa6,
+  0x47,0xb6,0xce,0x41,0x35,0xe2,0xf8,0x22,0x3c,0x19,0x2b,0x4b,0xc2,0x8d,0xe8,0x61,
+  0x6d,0xe9,0xba,0x7e,0x44,0xfd,0x96,0x23,0x28,0x6d,0xea,0x98,0xf1,0x76,0xde,0x6a,
+  0x56,0x62,0xc3,0x3f,0x30,0xfc,0xeb,0xc2,0x9a,0x57,0xfe,0x4a,0x67,0x43,0xb1,0x67,
+  0x62,0x7e,0x52,0x74,0x0a,0xfa,0x83,0x75,0xa3,0x05,0x7e,0x55,0x81,0x8f,0x75,0x3f,
+  0xbe,0x91,0xea,0xce,0xe0,0x9f,0xdb,0xb6,0x28,0xbf,0xd3,0x6e,0x1a,0xc4,0x45,0x68,
+  0x80,0xb7,0x28,0x3e,0x76,0x4e,0x9e,0xa4,0x40,0x87,0x99,0x1f,0x57,0xcf,0xc1,0xef,
+  0x08,0x3f,0xef,0xee,0xb4,0xe3,0x9f,0x24,0x7e,0xa4,0xa4,0x9d,0x68,0xfd,0x29,0x70,
+  0xdd,0x8b,0xfa,0x9f,0x60,0xf9,0x83,0x71,0x79,0x03,0x2e,0x9d,0x85,0xcf,0x2b,0x6c,
+  0xf1,0x9f,0xb8,0xb2,0x36,0x54,0x6a,0x16,0xa0,0x3f,0x85,0xd0,0xb5,0xb2,0x3f,0xef,
+  0xa3,0xa6,0xc7,0xe1,0x39,0xf4,0xa7,0xf8,0x37,0x51,0xc3,0xfc,0x0c,0x11,0x51,0xf7,
+  0xbd,0x2c,0x90,0xfe,0x7d,0x4d,0xf8,0x01,0xec,0xe8,0x98,0x77,0xd6,0x41,0xd1,0x9e,
+  0x7d,0x66,0x65,0x32,0xef,0x5b,0xec,0x2a,0xfd,0xa5,0xae,0x39,0x14,0x08,0xba,0x04,
+  0x6b,0xc3,0x88,0x88,0xea,0x10,0x1f,0x4e,0xaf,0x7f,0x6b,0xf1,0x80,0xde,0x89,0xfe,
+  0x85,0xa3,0x06,0x8d,0xfe,0x36,0xe1,0xfb,0x32,0x02,0xa1,0x07,0xa1,0xb7,0xc5,0x4b,
+  0x2f,0xbe,0xd4,0xb3,0x1d,0xf4,0x16,0x84,0x9a,0x6e,0x5b,0xfc,0x67,0x3f,0xfb,0x10,
+  0x6e,0x12,0x05,0xa3,0x0f,0x27,0x94,0x0b,0x52,0x30,0xe6,0x8a,0xc9,0x5e,0xb8,0x14,
+  0x5a,0xf8,0x50,0x41,0x52,0xbe,0xa8,0x1f,0x35,0xe2,0x78,0x44,0xad,0xb7,0xe3,0x1f,
+  0x63,0x02,0x3c,0xee,0x02,0x11,0x4e,0x1a,0xa3,0x88,0xee,0xd0,0x0c,0x11,0xec,0x09,
+  0x92,0x87,0xbe,0x0d,0x26,0x78,0x50,0xcb,0xca,0x7f,0x59,0xf8,0x47,0x0a,0x50,0xfe,
+  0xab,0x9c,0xaf,0x83,0x94,0x00,0x87,0xf8,0xb4,0x00,0xee,0x56,0x1e,0xcd,0x8e,0xff,
+  0xa0,0x91,0xdd,0x6e,0xac,0x88,0x3a,0xe6,0xc2,0xeb,0xaf,0x6f,0xff,0x66,0x45,0xd4,
+  0x51,0xce,0x5e,0x87,0x30,0x5a,0x64,0xc7,0x9c,0x30,0x9e,0x5a,0x95,0x1f,0x75,0xe8,
+  0x36,0xfc,0xa3,0xa0,0x7f,0xa1,0x9b,0x5e,0x8d,0xed,0x6c,0xdd,0x86,0x8a,0x97,0xc2,
+  0x1a,0xd0,0x01,0xdc,0x12,0xd8,0xc3,0x84,0x88,0x34,0x96,0x6b,0xd3,0x3f,0x78,0xbd,
+  0x37,0xd4,0xc6,0xdd,0x61,0x05,0x76,0x43,0xc8,0x70,0xa0,0x10,0x43,0x0f,0x05,0x61,
+  0xc0,0x03,0x74,0x2b,0x2f,0x02,0xa1,0x30,0xcb,0xc2,0x3f,0x27,0xf5,0x40,0x84,0x87,
+  0xcb,0x62,0x30,0x0a,0x01,0x58,0x42,0x89,0xb0,0x08,0xd4,0x81,0x93,0xc9,0xba,0x72,
+  0x27,0xab,0x17,0x05,0x61,0xb9,0x20,0xad,0x7f,0xb6,0x5e,0x7b,0xae,0xe7,0x3d,0x6f,
+  0x63,0x9b,0xeb,0x78,0xe7,0x37,0x62,0x3f,0xf4,0x36,0x2e,0xce,0xdf,0xdc,0x79,0x2e,
+  0xf6,0x7b,0xef,0xf5,0x6d,0x2e,0x12,0x3e,0xf0,0x2e,0x6c,0xdb,0x98,0x85,0x7f,0x66,
+  0x8e,0x20,0x5a,0xa8,0x6f,0x71,0x6e,0x2e,0x52,0xd8,0x21,0xad,0xd7,0x02,0x06,0xc6,
+  0xeb,0xb8,0x50,0xae,0x87,0x8b,0x14,0x5c,0x9f,0x40,0x0b,0xc5,0x7f,0x32,0xf9,0x2f,
+  0x2d,0x59,0x2e,0xb8,0xa7,0xab,0x95,0xf0,0x8f,0xd0,0x3d,0x4c,0xc6,0x1f,0x02,0x22,
+  0xde,0x0a,0xae,0x76,0x3a,0xbc,0xfa,0xd3,0xdc,0x03,0x91,0x81,0xb0,0x2d,0xfe,0x93,
+  0x73,0x4e,0x3c,0xa1,0xcd,0x33,0x1c,0x9f,0x67,0xc5,0xb1,0x8d,0x7a,0x69,0xab,0xfa,
+  0x39,0x76,0x0e,0xbe,0xa7,0xcf,0x6b,0x53,0x8f,0xa3,0xfd,0x5a,0x03,0x68,0x01,0x3f,
+  0xef,0x60,0x19,0xfc,0x93,0xb3,0x53,0xa7,0xa0,0x99,0xe3,0x57,0xac,0x18,0xf2,0x51,
+  0x50,0x87,0xf1,0xfa,0x35,0xf0,0x99,0x45,0xea,0xb0,0xa7,0x96,0x3f,0x51,0x5e,0xda,
+  0xc2,0x87,0xed,0xf1,0x9f,0x9c,0x9f,0xd3,0xf3,0xaf,0x0a,0x3e,0x8e,0xbf,0x57,0x3f,
+  0x3d,0x36,0x85,0x9d,0x5f,0xff,0x6c,0x60,0xd9,0xa6,0xd4,0xef,0xbb,0xdd,0x40,0xfc,
+  0xe3,0xcd,0x99,0xde,0x9f,0x3d,0xd2,0x93,0x70,0x16,0x82,0xad,0x88,0x87,0xdf,0x15,
+  0xe7,0xa3,0xc1,0x15,0x14,0x0d,0x33,0x28,0x11,0xb6,0x29,0x9a,0xca,0x88,0x11,0x82,
+  0xb2,0xc7,0x7f,0x76,0xa3,0xfd,0x5a,0xa8,0x38,0x07,0x65,0xbf,0x4e,0xf9,0x70,0xd7,
+  0x80,0xec,0x87,0x49,0xa3,0x51,0xcb,0x37,0xe5,0xaf,0x2b,0x43,0xc6,0x75,0xe0,0x32,
+  0x55,0x47,0x06,0xff,0x14,0x7a,0x9d,0x4f,0x83,0x27,0x36,0x23,0xc6,0xe6,0x29,0xeb,
+  0x11,0xaa,0x14,0xec,0x72,0x7b,0xe1,0x79,0xa9,0xaa,0x8f,0x7b,0x98,0x37,0xba,0x1e,
+  0xf1,0x8f,0x3a,0xca,0x1c,0x36,0xfc,0x43,0x5c,0x8e,0xb9,0x3a,0x17,0x1e,0x89,0xc5,
+  0xf0,0x33,0x72,0x00,0xea,0x82,0xb8,0x52,0x5e,0x97,0xc7,0x58,0x08,0x4f,0xf9,0x40,
+  0x95,0x3c,0x99,0xf8,0x4f,0x0c,0x1a,0xe0,0x49,0xa0,0x24,0x97,0xa3,0x41,0x22,0xc1,
+  0xd1,0x80,0x9f,0x2d,0xba,0x2d,0x49,0x44,0x08,0x0d,0xfc,0x49,0xf8,0xaa,0x79,0xcd,
+  0x2a,0xe6,0x4d,0xdf,0xbf,0x87,0xbb,0x79,0x97,0xa8,0x09,0x39,0x13,0xf2,0xd5,0x56,
+  0xb6,0x2b,0xb7,0x55,0x76,0xc3,0xb9,0x8e,0x46,0xfd,0xb6,0x44,0xd1,0x17,0x58,0x97,
+  0xb8,0x39,0xe9,0x4a,0xc8,0x15,0x99,0xf8,0xcf,0x92,0x0d,0xda,0x45,0xf4,0x2e,0xd1,
+  0x7b,0xb5,0xd2,0xe8,0xe0,0x20,0xc5,0x42,0xf1,0x1f,0x54,0x23,0xa3,0xe8,0x48,0xe2,
+  0x17,0x17,0x97,0x07,0xd2,0xfa,0x07,0x72,0xde,0x36,0x4e,0x89,0xc6,0xd8,0x75,0x09,
+  0x79,0xae,0x34,0x29,0x1a,0xcb,0x9d,0xfb,0xcb,0x02,0x30,0x89,0x40,0x08,0xf1,0x4f,
+  0x3d,0x09,0xba,0x6b,0x34,0x0b,0xff,0xfc,0xa8,0xe5,0x9f,0x60,0x7e,0x4b,0xc9,0xbd,
+  0x9d,0x7f,0x29,0xf6,0xe9,0xf3,0x4d,0x6f,0xc2,0x31,0x4b,0x7b,0xc9,0xb9,0x1b,0x54,
+  0x83,0x15,0x2b,0x7f,0x44,0x45,0xa4,0xb6,0xb3,0x8a,0x4c,0x7e,0x01,0xe2,0xbb,0xbb,
+  0xac,0xe8,0x74,0xd3,0x5d,0xb1,0x7d,0x79,0x95,0xe6,0xba,0x55,0x4c,0xd3,0xf7,0x42,
+  0xe5,0x80,0x4a,0x88,0x68,0x2f,0xc7,0xa5,0x58,0xc1,0xc0,0x86,0x7f,0x5e,0xa3,0xfc,
+  0xce,0x2c,0x5e,0xcf,0x9a,0xa0,0x2f,0xec,0xd3,0x39,0xb0,0x2a,0xd8,0x93,0xa0,0xb0,
+  0x73,0x93,0xae,0xed,0x31,0xbc,0xba,0xaa,0x39,0xb8,0x0d,0xff,0xfc,0x04,0x5e,0x4e,
+  0xbd,0x94,0x0e,0x7d,0x22,0x08,0x4b,0x44,0x59,0x95,0xf6,0xb1,0x59,0x03,0xdd,0x42,
+  0xd5,0x4b,0x2f,0x16,0x07,0xbc,0xa8,0x4f,0x2a,0x6c,0xf1,0x9f,0xd3,0x3a,0xe2,0x1f,
+  0xd3,0xa5,0xe0,0xb2,0x1c,0x50,0x82,0x83,0x56,0xb6,0x6b,0x22,0xb5,0x3e,0x63,0x62,
+  0xd4,0x98,0xca,0x7f,0x4d,0xdf,0x5f,0xd2,0x10,0x0d,0x8a,0x6a,0x42,0x3b,0x75,0xca,
+  0x65,0x28,0x33,0xf3,0x0d,0xb9,0x41,0xfc,0x4e,0xaf,0x66,0x4b,0x84,0x7c,0x8e,0x1d,
+  0x8b,0x56,0x9b,0x2e,0x90,0x21,0x1d,0xff,0xe9,0x80,0xe6,0x15,0x91,0x93,0x1e,0xa1,
+  0x6e,0xec,0x1c,0x81,0x3e,0xd8,0x0e,0xad,0x71,0xb6,0x43,0x9c,0x3c,0x4d,0x49,0x1b,
+  0x36,0xca,0x23,0x94,0xda,0x88,0x3b,0x74,0x1b,0xfe,0xf1,0x21,0x28,0xc2,0xeb,0xe3,
+  0x08,0x03,0xfa,0xc0,0x2b,0xe1,0x65,0x3e,0xe8,0x96,0x3c,0xd6,0xf5,0x50,0xc6,0x3d,
+  0x52,0x77,0x8c,0xe9,0x36,0xfd,0xa3,0x77,0x44,0x40,0x5f,0xa4,0x02,0x4b,0x44,0xf6,
+  0xc0,0x0a,0x93,0xe3,0x3f,0x86,0xad,0xec,0x1e,0xf4,0x6b,0xd8,0x20,0x1a,0x5b,0x9d,
+  0x18,0x32,0xcc,0x9e,0xff,0x8a,0x51,0x92,0x4b,0x45,0x6b,0x2b,0x2e,0x36,0xd5,0x9b,
+  0x95,0xbd,0x32,0xc1,0xc2,0xde,0xe1,0x59,0xb4,0x31,0xde,0xa1,0xfc,0x57,0x4c,0x06,
+  0x1b,0xfe,0x19,0xd6,0x28,0x2c,0xef,0x32,0x8b,0x76,0xc3,0xa4,0x77,0x21,0x14,0xf4,
+  0xcb,0xe3,0x30,0x29,0x35,0x82,0x4a,0x44,0x97,0x53,0x0a,0x9e,0x1a,0xce,0xc2,0x3f,
+  0xe3,0x70,0x59,0xa9,0x36,0x37,0x7c,0x24,0xff,0x4a,0x79,0xdf,0x7f,0x93,0x70,0x8d,
+  0xab,0xd5,0x70,0x0c,0x1a,0x5f,0x29,0xf8,0xa8,0xf3,0xfb,0xca,0xcb,0xfa,0x02,0xc3,
+  0x39,0x9e,0x95,0xff,0xda,0x0e,0x9b,0x60,0xe1,0x38,0x3f,0xc7,0x46,0xc4,0xda,0x1a,
+  0x56,0x5c,0x70,0xc3,0x80,0x57,0x74,0x0f,0xcf,0x1f,0xe2,0x93,0x8e,0x1f,0x6b,0x3f,
+  0x0b,0x78,0xee,0x70,0xf4,0xd9,0xe2,0x3f,0x5c,0x31,0xf9,0x0e,0x88,0x0d,0x6e,0x5d,
+  0xc0,0x06,0xf5,0x1d,0xe0,0x35,0xd5,0x80,0x47,0xb0,0x4e,0xc5,0x97,0x60,0x7e,0xb6,
+  0x13,0x3a,0x7d,0x7a,0xdb,0x7a,0xbf,0x3d,0xff,0xf5,0xb9,0xa7,0x11,0xff,0xcc,0x35,
+  0x4b,0xe2,0xee,0x41,0xe8,0xcc,0xf5,0x0c,0xa8,0x71,0xa8,0xf0,0x77,0x13,0x8c,0x8c,
+  0xb3,0x9d,0x2d,0xcf,0x80,0x27,0xe4,0x78,0x2e,0x2b,0xff,0xd5,0x29,0xde,0x47,0x23,
+  0xbb,0x24,0x5e,0xf8,0x2e,0x2e,0x4b,0x3d,0x01,0xe3,0xed,0xfc,0x08,0x02,0x21,0xfc,
+  0x82,0x1e,0x40,0xfb,0xeb,0x5e,0x91,0x7b,0x50,0x36,0xd3,0xfa,0xe7,0x34,0xc4,0x9d,
+  0xc7,0xa0,0xc1,0x9c,0x3f,0xde,0xfc,0x47,0x84,0x85,0x8d,0x1d,0x05,0xe3,0x65,0x13,
+  0xca,0x45,0xb8,0xd9,0x74,0x8d,0x37,0x9f,0xd3,0x2f,0xc3,0x4b,0x4c,0x45,0xfc,0x33,
+  0xfd,0x73,0x21,0xfe,0x79,0x0a,0x28,0xc9,0x45,0xdf,0x23,0x7b,0x5f,0xaf,0xc7,0xff,
+  0x90,0x5a,0x0a,0x17,0xb5,0x5e,0x82,0x3d,0xe5,0xec,0x08,0x8f,0x1b,0xce,0xec,0xfc,
+  0x97,0x17,0x36,0x99,0x65,0x49,0xfe,0x87,0xa6,0x11,0x78,0x6b,0x91,0xa7,0xdf,0xf1,
+  0x0f,0xa8,0x0d,0x5e,0x5a,0x53,0x66,0xf2,0xff,0xa3,0x69,0xae,0xb2,0xd6,0xf0,0xb4,
+  0x23,0x54,0xce,0xc2,0x3f,0xfe,0xc7,0x86,0xf5,0xe4,0x35,0x35,0xe1,0x41,0xf4,0x0e,
+  0xbc,0x82,0xdf,0xc8,0x7a,0x60,0x0f,0x6e,0x03,0x5e,0xd7,0xa4,0x40,0x27,0xf4,0xb4,
+  0x33,0xb0,0xe3,0x9f,0x45,0x57,0x2b,0x0f,0x8b,0xbb,0xc7,0x3e,0x4d,0xd6,0xff,0x91,
+  0x68,0xa9,0xee,0xb8,0x8f,0xfd,0x00,0xf6,0x09,0x3d,0xc9,0xeb,0xd8,0x55,0xb0,0x36,
+  0xf2,0x99,0xe5,0x8e,0x3a,0x3b,0xfe,0x69,0x65,0xed,0xbf,0x04,0xff,0x19,0x97,0x1f,
+  0xd5,0xf2,0x3b,0xb1,0x7a,0xe1,0xbc,0x49,0x8e,0x10,0xec,0x49,0x38,0xfd,0x1d,0xb9,
+  0x2b,0x3a,0x45,0x9d,0x39,0x7b,0x81,0x6c,0xc3,0x3f,0xd7,0x6e,0x25,0x90,0x33,0x5c,
+  0x70,0x4e,0x3e,0x07,0xdf,0x6d,0x45,0xb4,0x73,0x56,0x5e,0x0d,0x2f,0x21,0x3e,0x9c,
+  0xbf,0xbb,0xe3,0x1c,0xae,0xd8,0x42,0x33,0x3f,0x2b,0xfe,0x33,0x73,0x1c,0x2e,0xae,
+  0xa8,0x3b,0xe1,0x7b,0x16,0xb5,0xfd,0xcb,0x7a,0x40,0xdc,0x1e,0x97,0x92,0xb8,0x3e,
+  0xc1,0x84,0x73,0xef,0x8e,0x72,0xb8,0xd8,0x6a,0xf1,0x7f,0x6c,0xf9,0xaf,0x4f,0x97,
+  0xc0,0x9e,0x50,0x69,0x02,0xb5,0xe5,0x5e,0x58,0x4b,0xf9,0xaf,0x6f,0xb2,0x93,0xa4,
+  0x3f,0x07,0xf8,0xbd,0x68,0x71,0xf6,0x18,0x68,0xaa,0x56,0xb1,0x8f,0x6c,0xf8,0xe7,
+  0xff,0x84,0x7d,0xb1,0xbf,0x49,0xe6,0xd5,0xe7,0xe2,0xdb,0x89,0x9d,0x08,0xfc,0xd8,
+  0xaf,0x94,0x85,0xc2,0x37,0xc6,0xeb,0xe6,0x5e,0x85,0xa7,0xe6,0x24,0x4b,0xee,0xb7,
+  0xe7,0xbf,0x94,0xa3,0xd6,0xea,0xe5,0xf9,0x73,0x1f,0x30,0x3a,0xe5,0xf2,0x5f,0x21,
+  0xfe,0x39,0x82,0x47,0x28,0xe3,0x9c,0x5b,0x00,0x7b,0x98,0x2f,0xe1,0xa8,0x1b,0xb0,
+  0xe5,0xbf,0x72,0x0e,0x18,0x17,0xd0,0xff,0xca,0x27,0xd8,0x73,0x14,0x6e,0x40,0xb4,
+  0xd3,0x7c,0x41,0x5c,0x80,0xef,0x08,0x67,0xec,0x9a,0x0a,0xe7,0x05,0x58,0x28,0x9c,
+  0xa3,0x33,0x6c,0xf9,0x2f,0xed,0x34,0x3a,0xdd,0x0d,0x50,0x00,0x72,0x92,0x8d,0x1b,
+  0xf5,0x50,0x20,0x9a,0x93,0x62,0x02,0xee,0x87,0xf9,0x08,0x84,0x8c,0x09,0x3c,0xe2,
+  0x12,0x33,0xec,0xf8,0xe7,0xd5,0xc8,0x7b,0xfa,0xd5,0xcb,0xf3,0xb7,0xca,0xcb,0x81,
+  0xf2,0x23,0x4e,0x8a,0x0f,0x9c,0x2d,0xbf,0xca,0xc8,0x7f,0xfc,0x9a,0x72,0xe3,0xbc,
+  0x6e,0x59,0x4c,0x3b,0xff,0x67,0x39,0xea,0x20,0x8f,0x11,0x21,0xeb,0xbf,0xee,0x6e,
+  0x8f,0xc1,0xbf,0xef,0x49,0xd1,0x4e,0x38,0xfd,0xc3,0xfd,0x89,0x8a,0x6c,0xfe,0x4f,
+  0x89,0x52,0x2e,0x3d,0xc5,0x2a,0x8c,0x12,0x4a,0xd3,0x3c,0x05,0xf7,0x18,0x7f,0x13,
+  0x6d,0x5a,0x8e,0xd7,0x57,0x18,0x9f,0xa5,0x23,0xbb,0xe1,0x9e,0x76,0x8b,0xff,0x33,
+  0xfd,0x87,0xf8,0x67,0x5b,0x87,0xcf,0xdb,0xd6,0xe7,0x0e,0x97,0xc3,0x36,0xaf,0xa7,
+  0x2d,0xcf,0x1d,0x6e,0x91,0x76,0x7b,0xbd,0x16,0x22,0xb2,0x04,0xc4,0x3f,0xb6,0xf8,
+  0x0f,0x5f,0x21,0x46,0xad,0xf8,0x8f,0xaa,0xb3,0x51,0xdd,0xc3,0x6f,0x0b,0xe7,0x85,
+  0x60,0x42,0x0f,0xa2,0xdf,0x5c,0xa4,0xf3,0x09,0xdd,0x4f,0x89,0xb0,0xa3,0xe9,0xfd,
+  0xb3,0xf5,0xda,0xbd,0xf0,0x2d,0x6f,0xad,0x81,0x68,0x67,0x6f,0xec,0x75,0xef,0x4b,
+  0x6d,0x05,0x28,0xf4,0x9c,0x97,0x9e,0x6b,0x9b,0x11,0x55,0xf7,0xf2,0xf3,0x04,0x8d,
+  0x86,0xcb,0xb2,0xe3,0x3f,0x9f,0xe0,0xcf,0xee,0x3c,0x2e,0x2b,0xf0,0x82,0x1f,0xd7,
+  0x67,0xb8,0x73,0xd0,0x78,0x4d,0x0f,0x20,0x82,0xa2,0x44,0x98,0xb4,0xa7,0xc5,0xb5,
+  0xd9,0xce,0xff,0xd1,0xde,0x83,0xbe,0x7c,0x4f,0x8e,0x97,0xf0,0x4f,0x9f,0xdf,0xa3,
+  0xe5,0x77,0x11,0xfe,0x01,0x4f,0x9e,0xda,0xc1,0x74,0x16,0x51,0x3c,0x8a,0x1a,0xb3,
+  0xf1,0x7f,0x78,0xce,0xa0,0xb1,0x5b,0x43,0x58,0x58,0xc4,0x94,0xf8,0x6e,0x5d,0xbf,
+  0xbd,0x55,0xcb,0x1d,0x81,0x0e,0x4d,0x5f,0xac,0x6a,0x56,0x22,0x4c,0x37,0xd4,0x42,
+  0x9b,0xfe,0x29,0x99,0xb9,0x33,0x15,0x34,0xd3,0x2a,0xca,0x5b,0xf6,0x4b,0x9e,0x36,
+  0x5c,0xc6,0x11,0x8b,0x61,0xb5,0x18,0xd7,0xb3,0x64,0x1d,0xf3,0xb4,0xd0,0x7a,0x66,
+  0xf0,0x4f,0xf1,0x13,0x88,0x5e,0x02,0x88,0x4e,0xe5,0xb9,0x88,0x5e,0x02,0xab,0x10,
+  0xd6,0x0e,0xea,0x87,0x72,0xac,0x9f,0x95,0x12,0x61,0x81,0x15,0x33,0xb6,0xce,0x18,
+  0x4d,0xe7,0xa7,0x9e,0x86,0x9d,0x5e,0x8b,0xf6,0x13,0xed,0x7c,0x17,0x28,0xbe,0x41,
+  0x78,0x8f,0x9d,0xb7,0x84,0xce,0x77,0x5b,0xf1,0x54,0x93,0x6b,0x0b,0x7e,0x2f,0xd3,
+  0xd7,0x7b,0xb5,0x6d,0x6c,0x58,0xf2,0x83,0x8f,0xa2,0x8b,0x27,0xcb,0x03,0x70,0x2c,
+  0x2c,0x9f,0x86,0x04,0xd4,0x82,0x13,0x9a,0x75,0x7d,0x98,0xe2,0xcf,0x42,0x3e,0x9c,
+  0xc9,0x7f,0x29,0x75,0xfa,0xd1,0x50,0x85,0xe0,0x49,0xb4,0x3e,0x0f,0x2e,0xf2,0x88,
+  0xc5,0x23,0x28,0x84,0x99,0x47,0x38,0x92,0xe1,0x4f,0xc3,0x51,0xb3,0x6c,0x33,0xfa,
+  0xef,0x89,0xf4,0x7e,0xf0,0xae,0x69,0x82,0x30,0xc7,0xf5,0xa9,0x63,0x43,0x88,0x96,
+  0x3d,0xe6,0x62,0x74,0x6c,0x79,0xa7,0x56,0x6e,0xf2,0x1a,0x47,0x81,0xd4,0xb9,0x5d,
+  0x37,0xdb,0xfc,0x9e,0xc3,0x99,0xfc,0x57,0x21,0xd3,0x1e,0xa0,0x34,0xd9,0x2a,0xd4,
+  0x3f,0x9d,0x7c,0x1b,0xa2,0x85,0xb9,0x93,0xa2,0x03,0x4a,0x47,0x1c,0x7e,0x56,0xec,
+  0xe9,0xe4,0xa5,0x49,0xfc,0x7e,0x13,0x99,0xfc,0x57,0xeb,0xd5,0x7c,0x88,0xf8,0x39,
+  0xab,0xe5,0x37,0xf5,0x7f,0x12,0x0b,0x46,0xd5,0xd5,0xf2,0x5b,0xe1,0x57,0xc4,0xc2,
+  0x31,0xdf,0x9d,0x65,0xb3,0xe1,0x15,0x3c,0x55,0xb0,0x5a,0x3e,0x6c,0xcb,0x7f,0xf5,
+  0x20,0xcc,0x26,0x23,0x5e,0xf4,0x81,0x40,0xd8,0x33,0xe8,0x8a,0x16,0x59,0x61,0x64,
+  0x93,0x80,0xa5,0xf2,0x1e,0x34,0x88,0x4a,0x3b,0xfe,0x31,0x72,0x26,0xcc,0xef,0x94,
+  0x06,0x97,0x6f,0x9a,0x90,0xab,0x42,0xff,0x98,0x82,0x3d,0x6f,0x36,0xbd,0x16,0x0d,
+  0x8e,0x38,0xcf,0xcb,0x41,0x78,0x29,0x5c,0x7d,0xb7,0x73,0x42,0xd6,0x6c,0xf8,0x27,
+  0xd2,0xb1,0xb7,0x3d,0x36,0xaa,0x8e,0x37,0x05,0xc5,0x1a,0x0d,0xd1,0x8b,0x26,0x3f,
+  0x6e,0xae,0xf1,0x57,0x8e,0xf2,0xd5,0x4c,0x11,0xcf,0xe9,0xdb,0x48,0xff,0x54,0xa4,
+  0xf1,0xa7,0x30,0xb6,0xb6,0xef,0x85,0x39,0x84,0xf7,0xee,0x2a,0xdd,0x00,0xa5,0x04,
+  0x7b,0xee,0x57,0xbe,0x87,0x88,0x28,0x2f,0xc0,0x66,0xf1,0x67,0x61,0x8e,0x91,0xb7,
+  0x0a,0xed,0xfb,0xf4,0xfa,0x87,0x8a,0x5b,0x8d,0x78,0x2a,0x89,0x73,0x3b,0x7e,0xc8,
+  0x64,0xcd,0xdd,0x3f,0xfb,0xf2,0x43,0x92,0xcf,0x5c,0xa7,0x31,0x27,0xc4,0xa1,0xfc,
+  0xbf,0xa8,0x41,0x56,0x92,0xde,0x9f,0xde,0x99,0x3f,0x05,0x8a,0xde,0x6c,0x8a,0xcb,
+  0xf7,0xc3,0x21,0x65,0xcf,0x38,0xbe,0xe6,0xa4,0xf2,0x3a,0xba,0x99,0xb3,0xe2,0xd7,
+  0x70,0x74,0x24,0x7f,0x6c,0xa0,0xe3,0xe9,0xb0,0xe1,0x9f,0x51,0xca,0xce,0x53,0x12,
+  0x70,0x17,0x3b,0x4d,0x68,0x47,0x20,0x0c,0x78,0x0f,0x8f,0x54,0xed,0x2d,0xfb,0xe0,
+  0x8e,0x8f,0xa4,0x3a,0xa3,0x60,0x77,0x16,0xfe,0x99,0x30,0xce,0xa2,0xd2,0x9e,0x31,
+  0x59,0x34,0x09,0xff,0x15,0x6e,0x18,0x98,0x35,0xdc,0xdc,0x00,0xaf,0xc4,0x16,0x9a,
+  0x79,0xc3,0xe8,0xe6,0x27,0x60,0x21,0xc5,0xe7,0x6d,0xf9,0x2f,0xe5,0xef,0xa0,0x8f,
+  0x92,0x56,0x5d,0xe1,0x21,0x6d,0x9d,0xe9,0x31,0xf3,0xb7,0x22,0x9e,0x59,0x47,0x78,
+  0xe6,0x79,0xf6,0xae,0x38,0x29,0x02,0x7e,0xca,0xbf,0x64,0xf0,0x8f,0xe2,0xd5,0x9f,
+  0x17,0x3f,0x36,0x10,0xff,0x8c,0x49,0xfb,0x23,0x9e,0x7e,0xee,0x74,0xf8,0xa4,0x75,
+  0xb0,0xdc,0x44,0x18,0xf0,0x21,0x3c,0x1a,0xb9,0xe7,0x4b,0x25,0x71,0x4f,0x52,0x9a,
+  0xde,0x0f,0x5c,0xe1,0x46,0x2f,0xe8,0x89,0xc5,0xfe,0xdc,0x31,0xb1,0x8d,0x14,0x35,
+  0x30,0x27,0xc3,0x85,0x3a,0xbc,0x1e,0x3d,0xf4,0xe6,0xcd,0xe4,0xc1,0x21,0x1e,0x48,
+  0xf3,0x69,0x81,0x7b,0x11,0x56,0xd5,0x9e,0x20,0x1a,0x6a,0xec,0x7c,0x4b,0xc0,0xe4,
+  0x51,0xb7,0x4f,0x39,0xc4,0x6e,0x48,0x54,0xf6,0x36,0x7d,0x00,0x27,0x17,0xf9,0x0d,
+  0x1f,0x3e,0xff,0x8c,0x74,0x7c,0xf2,0xda,0x09,0x31,0x09,0x37,0x0d,0xb9,0xc6,0xcb,
+  0x26,0xe1,0x9f,0xbd,0x2f,0x99,0xe8,0x88,0x4d,0x5a,0x44,0xdf,0xfc,0x9d,0x88,0x8f,
+  0x27,0xf9,0x4b,0xc6,0xd2,0x71,0x5b,0x3c,0xd6,0xcc,0xf9,0x88,0xbf,0x65,0x7e,0x4b,
+  0xc7,0x4d,0xf2,0xa2,0xf2,0x47,0xd1,0x38,0xa7,0x60,0x5c,0xfe,0x03,0x8c,0x74,0x35,
+  0xea,0xe8,0xc8,0x07,0xe1,0x18,0x11,0xa1,0xfb,0xe4,0xf1,0x0c,0x3e,0xd1,0xde,0x25,
+  0x5a,0x2f,0xcf,0xa7,0x7c,0xdf,0x01,0xa8,0xa2,0x34,0xdf,0xbb,0x10,0x11,0x55,0x31,
+  0xf5,0xa0,0x5c,0x85,0xa0,0xb5,0x2a,0xa1,0xf6,0x65,0xe5,0xbf,0x06,0x61,0x8f,0xee,
+  0x75,0x38,0xe2,0xe1,0x0d,0x68,0x86,0x56,0x26,0xd4,0x05,0xac,0x05,0x61,0xa5,0x4f,
+  0x2c,0xae,0xc9,0x75,0x52,0x3c,0x70,0xc0,0xe2,0x3b,0x4d,0xff,0xbe,0xe6,0xcc,0x1f,
+  0xe3,0xc1,0x0a,0xc0,0x9b,0xec,0xa2,0xfb,0x27,0xf3,0xe2,0xa8,0x7f,0x10,0xff,0x44,
+  0x10,0x76,0xfa,0x04,0x01,0x21,0x44,0x44,0xb6,0xfc,0xd7,0xcc,0x01,0xf4,0x0e,0xbc,
+  0x5a,0x81,0x5f,0xde,0x85,0x66,0xb7,0x2a,0xe9,0x8a,0x97,0xbd,0x0b,0xef,0xe9,0xb3,
+  0xb7,0xba,0xe2,0x92,0x0f,0x4d,0x9f,0x85,0x87,0x33,0xfc,0xe7,0xb8,0xb4,0x17,0xde,
+  0x62,0x0b,0xe7,0xa2,0x11,0xbf,0x5f,0xa1,0x68,0x18,0xbd,0xaf,0xb8,0x6c,0x34,0x0a,
+  0xd7,0x2a,0xf9,0x20,0x21,0x22,0x2b,0x3f,0x68,0x8b,0xff,0xec,0x2a,0x25,0x58,0x85,
+  0xf8,0x67,0x4c,0xbf,0xc8,0xbf,0x69,0x5e,0x87,0x40,0x48,0x7f,0xbd,0x3d,0x20,0xf2,
+  0xe3,0xfd,0xbb,0x28,0x11,0x46,0x40,0x68,0x3c,0x8d,0x7f,0x4e,0xe6,0xcc,0xa1,0xf5,
+  0xd9,0xec,0x88,0xc3,0xef,0xf8,0x01,0xdc,0x3f,0x78,0xb7,0x35,0x78,0xa4,0x36,0xac,
+  0x9e,0x93,0x97,0x1a,0xbf,0x4e,0x01,0xb9,0x8f,0x6c,0xf8,0xa7,0x19,0xca,0x80,0x03,
+  0x2e,0xc2,0x31,0x63,0x0f,0x5e,0xaf,0x2e,0x08,0xbf,0x6a,0x3c,0x3c,0xe4,0xed,0x43,
+  0xc3,0x7d,0x8c,0x75,0xc2,0x4a,0x33,0x9b,0xff,0x2c,0x11,0x0c,0x28,0xd3,0xd5,0xd5,
+  0xb9,0x6f,0x6a,0x2f,0x45,0x2c,0x3e,0xcc,0xf7,0xa5,0x4d,0x68,0xbf,0xd5,0xd5,0xe1,
+  0x37,0xf5,0x47,0x52,0xc4,0x98,0x0c,0xff,0xb9,0x8d,0xe7,0x26,0x9f,0x41,0x2f,0xd2,
+  0xe5,0xf7,0x10,0xdb,0x59,0x1f,0x56,0xeb,0x11,0x08,0x1d,0x87,0x3a,0x91,0x57,0xf7,
+  0xa5,0x21,0xf1,0x32,0x3d,0x7f,0x9d,0x9d,0xff,0x7c,0x6d,0x17,0xbf,0x4c,0x6c,0xde,
+  0x71,0x79,0xd2,0xb8,0x0c,0x07,0x06,0x5d,0xbb,0x3b,0xb7,0x18,0x04,0x7b,0x5c,0xab,
+  0xca,0x96,0x4c,0xaf,0x4f,0x56,0xfc,0x87,0x5f,0x24,0x5a,0x0b,0xe5,0x07,0x8f,0xb0,
+  0x60,0x32,0xdf,0x8f,0x66,0x9a,0x3c,0x38,0xd7,0x02,0x8f,0x8f,0xfc,0x35,0xb3,0xa0,
+  0x4e,0x76,0xd8,0xf2,0x5f,0x5b,0x08,0xed,0x40,0xfe,0x2a,0x76,0x8a,0xaf,0x95,0x66,
+  0x98,0x79,0xf7,0xe6,0x16,0xf3,0x3f,0x42,0xa5,0xc8,0x5b,0xa5,0xcf,0x42,0x44,0x54,
+  0x89,0xaa,0x86,0x05,0x6c,0xf9,0xaf,0x1f,0xc1,0xbe,0x8e,0xca,0xd0,0xd6,0x54,0xb4,
+  0x27,0x3f,0xc9,0x27,0xd8,0x17,0x88,0xff,0x13,0x5b,0x3c,0x01,0x5f,0xc4,0xa5,0xa8,
+  0x24,0x44,0x94,0xfe,0x5a,0x28,0xff,0x45,0x68,0xa7,0xee,0xd3,0x1a,0xa5,0x81,0x44,
+  0xf9,0x47,0xb8,0x7a,0xb7,0x4b,0x7b,0xb6,0xfa,0xf6,0xe0,0x7a,0xb6,0x20,0x9e,0xac,
+  0x32,0xad,0xf8,0xcf,0xf4,0xfd,0x93,0x33,0x9f,0xd7,0x9f,0x87,0x9b,0x23,0xce,0x98,
+  0xbc,0x02,0x0e,0xc7,0x1a,0xfb,0xf2,0x43,0x6c,0x85,0xb8,0xd4,0x74,0xb3,0x70,0x25,
+  0xd5,0x56,0xf6,0x06,0xb9,0xa2,0x31,0xb5,0xce,0x16,0xff,0x39,0x4d,0xde,0x16,0x85,
+  0x7d,0x50,0x68,0xa9,0x25,0xd8,0x13,0x03,0x74,0xbb,0x94,0xfc,0x2e,0x14,0xa6,0x4e,
+  0xd9,0xf1,0xcf,0xbb,0xd2,0x21,0xcb,0xde,0xc9,0xef,0xc2,0x21,0x3d,0xb0,0x48,0xdd,
+  0x5a,0xf6,0x15,0x7e,0x5e,0xd4,0x1b,0x4e,0xb7,0xfc,0x15,0x46,0xa7,0x78,0x16,0xfe,
+  0x51,0x6e,0x59,0xf4,0x14,0x54,0xad,0xae,0x88,0xe6,0x8e,0xac,0x78,0x6a,0x7d,0x85,
+  0x51,0xf0,0x10,0xba,0x09,0xbb,0x4b,0x6a,0x57,0x14,0x10,0xff,0x64,0x1d,0xb3,0xf2,
+  0x2f,0x36,0xfc,0x63,0xf1,0x9f,0xab,0x12,0x9f,0x8d,0xe6,0x2e,0x4f,0x99,0xe9,0x2d,
+  0x57,0x95,0x8b,0xa7,0x24,0x4f,0x4b,0x6b,0xd4,0xbd,0x5c,0x59,0xa7,0x54,0x19,0x57,
+  0x5f,0x91,0xff,0x82,0x6d,0x50,0x45,0x41,0xa1,0x41,0x14,0xbc,0x86,0xc3,0xfd,0xfd,
+  0x07,0x10,0x26,0xcd,0xb5,0x02,0x41,0xa8,0xb1,0x7d,0x74,0xca,0x9e,0xff,0x5a,0x81,
+  0xe8,0x22,0x08,0xf9,0x14,0xc4,0x8e,0x40,0x00,0x5c,0xe1,0x32,0x9d,0x88,0xa9,0xe0,
+  0xdc,0xae,0x86,0x10,0xee,0x07,0xa1,0x2a,0x2b,0xff,0x75,0xed,0x39,0xe9,0x7c,0x2a,
+  0xfe,0x73,0x22,0xf6,0x89,0xaf,0xb1,0xad,0x20,0x5a,0xb8,0x17,0x6e,0x06,0x0a,0x44,
+  0xcb,0x27,0xc8,0x90,0x2d,0xce,0xb7,0xf3,0x7f,0x4a,0x72,0x4e,0x00,0x6a,0xfb,0x45,
+  0xce,0x05,0x88,0xb7,0x3f,0x91,0x82,0x2d,0x05,0xed,0x72,0xb1,0xf2,0x81,0xd4,0xb8,
+  0xc8,0x75,0xbc,0xfb,0x2e,0x76,0x28,0x27,0x88,0x88,0xa8,0xd9,0x9e,0xff,0x4a,0x72,
+  0x93,0x57,0x01,0x05,0xd5,0x63,0x75,0x08,0xcc,0x78,0x17,0x8b,0x11,0x23,0x1a,0x64,
+  0x8b,0x11,0x04,0x55,0xcc,0x61,0xe7,0x3f,0xf3,0x5b,0x06,0x59,0x87,0xee,0x33,0x4b,
+  0xb4,0xa6,0x41,0xb1,0xdb,0x5b,0xd5,0xea,0x28,0x74,0x2b,0xb0,0x5b,0xf2,0x19,0x8b,
+  0xb5,0xdc,0x96,0xe9,0xf7,0xcd,0xca,0x7f,0x89,0x75,0xe0,0x6b,0xe5,0x04,0x7b,0x0e,
+  0xc0,0xdf,0xb6,0xa0,0xb0,0x53,0x1c,0x80,0x82,0xe6,0xbc,0x29,0x22,0x10,0x65,0x18,
+  0xed,0xf9,0xaf,0x57,0xc4,0x21,0x29,0x68,0xf8,0x2c,0xf6,0x32,0x34,0xb4,0xde,0x1e,
+  0x95,0xcb,0xa5,0xf3,0x89,0xe0,0xd7,0xf1,0x17,0x5f,0x8e,0xf8,0xa7,0x8a,0x5e,0x3c,
+  0x2b,0xff,0xa5,0xe3,0x22,0xdc,0xe3,0x7a,0xb4,0x6c,0x84,0x9f,0x8f,0xd6,0x1b,0xf9,
+  0x1a,0xfd,0x43,0x2d,0xd8,0x82,0xf8,0xe7,0xb7,0x70,0x5e,0xb9,0x82,0xff,0x8c,0xf8,
+  0xc7,0x62,0x3b,0xe7,0x08,0x59,0xef,0x98,0xda,0x5d,0x3a,0x24,0xf4,0x00,0x73,0x0a,
+  0x35,0x45,0x44,0x77,0x65,0xf3,0x9f,0xeb,0x10,0x63,0x15,0x21,0xda,0xc9,0xbd,0x51,
+  0xfc,0x28,0x54,0x45,0xf8,0xa7,0x4f,0xff,0xa9,0x58,0x18,0xcd,0xff,0x0a,0x2b,0xd1,
+  0xd6,0x23,0xd4,0x97,0x89,0xff,0x9c,0xbe,0xbf,0x74,0x1b,0xa7,0x78,0xe9,0x3c,0xca,
+  0x17,0xef,0x89,0xac,0x34,0xd1,0x17,0x72,0xe9,0x1d,0xc2,0x7b,0x02,0x11,0x51,0x81,
+  0x41,0xa9,0x64,0x95,0xf8,0xcf,0xd3,0xeb,0x49,0xf9,0xaf,0x27,0xbb,0xca,0xcc,0xbc,
+  0x6f,0xb3,0x59,0xf0,0x08,0x54,0x26,0xd4,0xf6,0xf0,0x8b,0xf0,0x04,0xd5,0x5f,0x68,
+  0x78,0x64,0x06,0xcc,0x1b,0x54,0x57,0x35,0xd9,0xf3,0x5f,0x6e,0xf8,0x79,0xe4,0xc6,
+  0x64,0xfe,0x7d,0x6c,0x36,0x7e,0xb6,0x37,0x8f,0xbb,0x88,0xa6,0xf8,0x8a,0xb8,0x11,
+  0x11,0x51,0xd1,0x6c,0x46,0xd4,0x68,0x57,0x56,0xfe,0xeb,0xda,0x18,0x5c,0x6c,0xaf,
+  0x33,0x6f,0x8f,0x97,0x8d,0x59,0xda,0xc3,0x15,0x95,0xc6,0x10,0x28,0xd6,0x98,0xaf,
+  0x45,0xd1,0x22,0x5c,0x84,0xab,0xcd,0x9c,0x2c,0xfe,0x73,0xce,0x1b,0xf2,0x5b,0xda,
+  0x82,0xd0,0x06,0x44,0x3b,0xc6,0xfb,0x51,0xb4,0x56,0x27,0xe5,0x37,0xe1,0x37,0x22,
+  0x90,0x54,0x6e,0x94,0x9f,0xe3,0x64,0xbf,0x88,0xff,0xac,0x4f,0xaf,0xff,0x53,0x85,
+  0xc2,0x38,0x06,0xa5,0x5a,0xfe,0x44,0x93,0x13,0xd6,0xc6,0x50,0xdb,0x68,0xec,0x14,
+  0xfc,0x23,0xcc,0x9b,0x74,0xdc,0x87,0x1b,0xef,0x49,0x98,0x6f,0x3a,0xbe,0xce,0xce,
+  0x14,0x4f,0xdf,0x1f,0x20,0x0a,0x6b,0xfd,0x65,0x86,0x77,0x15,0x9b,0xa5,0x3d,0xa9,
+  0x57,0x52,0x74,0xe8,0x94,0xfe,0x13,0x5e,0x66,0x96,0xdc,0x9b,0x7b,0xce,0xd2,0x57,
+  0xc4,0x7f,0xb6,0xc5,0x7f,0x06,0x70,0xd1,0x74,0x2d,0xaf,0x0e,0xd7,0xb3,0x93,0xac,
+  0x9b,0xc6,0x8e,0x6a,0x0f,0x71,0xef,0x9d,0x0e,0x60,0x05,0x50,0xa6,0x54,0x99,0x8e,
+  0xec,0xfc,0xd7,0x5a,0x7e,0x0c,0x02,0x51,0x3e,0xde,0x4d,0x61,0x8d,0x46,0xb2,0x56,
+  0x1f,0x4a,0xef,0x0b,0xcf,0xf1,0x25,0x71,0x76,0x86,0x1f,0xc1,0x23,0xe4,0x3f,0xa6,
+  0xeb,0x05,0x04,0x24,0xd1,0xdf,0x7f,0xb1,0x9d,0xa2,0x3d,0xa8,0x46,0x82,0x49,0xdc,
+  0x2d,0x88,0x7f,0xa4,0x20,0xd1,0x2c,0xc7,0xda,0xa7,0x02,0x65,0xc9,0xf4,0xf3,0x48,
+  0xda,0x47,0x14,0xcd,0x08,0xe7,0x53,0xf5,0xca,0x65,0xad,0xda,0x44,0x47,0x03,0xf1,
+  0x80,0xa7,0xf1,0x6e,0xe7,0xb8,0x15,0x11,0xfa,0xae,0xd9,0x65,0xe7,0xff,0x08,0xdc,
+  0xd9,0xcf,0x80,0x2f,0x8e,0x46,0xea,0x43,0x78,0xcc,0x40,0xa0,0xbb,0xd9,0xfd,0xdf,
+  0x95,0xfd,0x86,0xef,0xac,0xa3,0x0e,0xaa,0xf4,0x03,0xec,0x6b,0x66,0x24,0x9b,0xff,
+  0x5c,0x4a,0x46,0x59,0x47,0x33,0xfd,0x81,0xe8,0x45,0xfc,0xcc,0xa3,0x9e,0xdf,0x69,
+  0x4f,0xa5,0x80,0xc1,0x4f,0xad,0x0c,0x91,0x23,0x9e,0x95,0xff,0xa2,0x24,0x20,0x7e,
+  0xbf,0x01,0x36,0xe4,0xdc,0xc3,0x2b,0x4c,0xae,0xb1,0x25,0xa8,0x7f,0x7c,0xe1,0xf5,
+  0x01,0xf4,0xf7,0xc9,0x51,0x75,0x64,0xf3,0x9f,0xef,0xc6,0xe7,0x0f,0x4a,0xf9,0xbd,
+  0x72,0xbf,0x71,0x51,0x0f,0x98,0x1b,0xbe,0x57,0x36,0xa6,0x9c,0x87,0xef,0x70,0xe7,
+  0x5e,0x95,0xf6,0x43,0x95,0x59,0xf5,0x6c,0x56,0xfe,0x6b,0x3c,0x76,0x99,0x35,0x82,
+  0x6b,0x37,0xbe,0xe6,0x5b,0xac,0xd1,0xfc,0xcc,0x00,0xc5,0x7f,0xd0,0xe2,0xb8,0xde,
+  0x79,0xec,0x2e,0x34,0x6d,0x08,0x84,0x3e,0xca,0x8a,0xff,0x4c,0xc0,0x90,0x16,0x30,
+  0x9d,0xe7,0x8b,0x26,0x95,0x63,0x1d,0x8d,0xaf,0x39,0xf3,0xe4,0x17,0x8d,0xcb,0xd1,
+  0xc0,0x88,0xf3,0x2c,0xe2,0x81,0x0f,0xe6,0x2d,0x28,0x77,0x9e,0x2b,0xb3,0xc7,0x7f,
+  0x26,0xf4,0x0d,0xb0,0x30,0x71,0x27,0x7e,0x80,0x9e,0x1d,0xbc,0x6a,0x88,0xf7,0x2e,
+  0xdb,0x85,0x8f,0xed,0x49,0xe0,0x8a,0x35,0x18,0xeb,0x56,0x54,0xb4,0x46,0xfc,0xf6,
+  0xf8,0x4f,0x4e,0x02,0xf5,0x89,0x3e,0xc0,0x7b,0xd9,0x06,0xd1,0x59,0x5a,0x6e,0x96,
+  0xc4,0xd9,0x86,0xae,0x3d,0x7a,0xcc,0xe4,0x81,0xa6,0x0d,0x31,0xf4,0x58,0x4d,0x47,
+  0x20,0x8b,0xff,0xec,0xd5,0xd6,0x49,0x73,0xfb,0x7b,0xe2,0xcc,0xa7,0x3c,0x23,0x21,
+  0x5a,0xe8,0x0b,0x57,0x69,0x07,0x34,0x3d,0xc1,0x76,0x23,0xe2,0x7a,0x4a,0x54,0xf4,
+  0x33,0xc2,0x3f,0xd3,0xfb,0xd3,0x98,0x39,0xda,0x74,0x38,0x1a,0x30,0xe1,0x46,0xc4,
+  0x3f,0x47,0x0a,0x83,0x66,0x79,0x9d,0xfc,0xd3,0x08,0xa5,0xa5,0x7c,0x07,0xf1,0x7b,
+  0x79,0x2f,0x12,0x58,0x5e,0x70,0xf0,0xe5,0x61,0x5b,0xfe,0xeb,0x07,0x4a,0x8a,0x1f,
+  0x55,0x74,0x0a,0x2e,0x8b,0x06,0x73,0xd3,0x38,0xf1,0x7f,0x78,0x63,0x12,0x77,0xc8,
+  0x98,0xf6,0xcf,0xf0,0x5d,0xa3,0xf2,0xa3,0xac,0xfc,0xd7,0x2e,0x39,0xe1,0x0e,0xf4,
+  0x2b,0xf1,0x66,0x9f,0x71,0x44,0xc2,0x85,0x7a,0x56,0x5e,0x29,0x1f,0x81,0x5e,0x4a,
+  0x1b,0x39,0x21,0x61,0x04,0x28,0xff,0x68,0xcf,0x7f,0x7d,0xa6,0x55,0x9c,0x28,0xfb,
+  0x95,0xe3,0xd9,0x70,0xb0,0xa5,0xdb,0x59,0xf6,0x8f,0x05,0x2f,0xb0,0xeb,0xef,0xec,
+  0x36,0xef,0x39,0xc5,0xf7,0xb1,0x86,0xba,0x75,0xab,0xf4,0xdf,0xdf,0xb2,0x2f,0x8b,
+  0xff,0x63,0x40,0x18,0x95,0x4c,0x45,0x5d,0x6e,0x01,0xeb,0x8c,0xc5,0x88,0x08,0xb4,
+  0x04,0x9e,0x91,0x74,0x13,0xbf,0x17,0x97,0xfe,0x14,0x94,0x93,0x63,0xd5,0x67,0xe7,
+  0x3f,0xfb,0x1f,0x8c,0x96,0x8e,0x44,0x56,0xa3,0x1a,0x59,0x1b,0x45,0xfc,0x73,0x9e,
+  0xcd,0xd6,0x9f,0x14,0xa5,0xc9,0xc3,0xf7,0xc1,0x6c,0xd1,0x29,0xae,0x4f,0x2e,0xbe,
+  0x2f,0xab,0xfe,0xcb,0x0b,0x9d,0x4a,0xfd,0x28,0xe2,0x43,0x27,0xbc,0x0c,0xfe,0x84,
+  0xab,0xbe,0x68,0xa5,0xb2,0x83,0x7b,0x92,0x55,0x2f,0x2e,0x72,0x42,0x3f,0xec,0x35,
+  0x0b,0x6e,0x92,0x37,0xdb,0xf0,0xcf,0x7e,0xf8,0x23,0xcc,0x1f,0xa6,0x6a,0x38,0x0b,
+  0xed,0x54,0x8e,0x4b,0xb8,0x91,0xb4,0xe0,0x20,0x7d,0x41,0xe1,0x8b,0x70,0x93,0x99,
+  0x7f,0xb6,0xb9,0xdd,0x86,0x7f,0x0e,0xc1,0x99,0x7b,0x02,0x83,0x8e,0xb8,0x34,0xa6,
+  0x1c,0x81,0xfa,0xc1,0x82,0x78,0x91,0x2f,0x95,0x08,0x8b,0x17,0x55,0xfa,0x0f,0x31,
+  0x5c,0x9f,0x68,0xa1,0x9d,0xff,0xbc,0x15,0x8e,0xa2,0xdb,0x78,0x1b,0xe2,0x1f,0xd8,
+  0x04,0x65,0x26,0x1f,0x77,0x34,0x4c,0xc3,0x9e,0x1f,0xa2,0x30,0xaf,0xff,0x8a,0xf8,
+  0xcf,0x8b,0xf0,0xe3,0x0e,0x3d,0x59,0xb2,0xda,0x7d,0xb4,0x75,0xad,0x98,0x87,0x6e,
+  0x9a,0x39,0x7b,0x1a,0xf6,0x7c,0x11,0xd6,0x88,0x39,0xa7,0x23,0xab,0x6f,0xb5,0xf3,
+  0x9f,0x0f,0x49,0x61,0x43,0x37,0xa5,0x12,0x36,0x44,0xf9,0x77,0x33,0x52,0xe7,0x51,
+  0x6b,0x3a,0x84,0x6f,0x79,0x77,0x5d,0x78,0x48,0x79,0xb8,0x15,0xbf,0xaf,0x9a,0x07,
+  0xec,0xfc,0xe7,0xe7,0xe1,0x43,0x11,0x10,0xfc,0x69,0x39,0x01,0x87,0x3b,0xea,0x45,
+  0xd5,0x88,0x5c,0x0f,0x4f,0xc7,0x50,0x9f,0x8c,0xec,0x59,0xc1,0x8e,0x52,0xfc,0x67,
+  0x24,0x8b,0xff,0x9c,0x34,0x47,0x4b,0x5e,0xb4,0xd2,0x5e,0x6c,0x42,0xb3,0xb2,0x5d,
+  0xb1,0xa6,0x29,0xc3,0x44,0x19,0xa2,0x7a,0xcd,0xd5,0xf1,0x27,0xfc,0x9f,0x74,0xb6,
+  0x0b,0x61,0x4f,0xb4,0x73,0x39,0x3c,0x25,0x5d,0x65,0x6c,0xf8,0x81,0xdb,0xca,0xef,
+  0xdc,0xe3,0xbc,0x32,0xff,0xf5,0x14,0x6c,0xa7,0x6c,0x57,0xb9,0xde,0x01,0x9e,0x3b,
+  0xbd,0xd1,0xab,0xcb,0xd9,0x53,0x39,0x55,0xc6,0x4f,0xb6,0xa2,0x40,0xf9,0x2f,0xef,
+  0x56,0xd5,0x96,0xff,0xca,0x51,0x44,0x87,0xa4,0xb7,0xb7,0x16,0x33,0x3a,0xab,0x1b,
+  0xad,0x94,0xff,0x7a,0x14,0xca,0x29,0xff,0xb5,0x53,0xea,0x80,0xd8,0x20,0x77,0x67,
+  0xe7,0xbf,0x62,0x1d,0x5e,0xbd,0x8d,0xb2,0x63,0xb1,0x75,0x92,0xde,0x06,0xda,0x55,
+  0x29,0xd8,0xc3,0xdd,0x0f,0x74,0x6d,0xc3,0x53,0x28,0x64,0xe7,0xbf,0x88,0xe4,0xcc,
+  0x97,0xa0,0xd9,0x15,0x11,0x29,0x40,0x6c,0x1f,0x9d,0x4f,0xc0,0x5c,0x88,0x30,0x59,
+  0x74,0x99,0x7a,0x5c,0x38,0x29,0xff,0x95,0xe6,0x3f,0x5f,0x7b,0x6e,0xfb,0x65,0x6f,
+  0x90,0xf0,0xcf,0x48,0xec,0x13,0xef,0x73,0x24,0xec,0x8d,0xbd,0x60,0x21,0xa2,0x8e,
+  0xe5,0x78,0xc4,0x82,0x46,0x3f,0x9e,0x11,0x4a,0x3f,0xff,0x88,0x49,0xeb,0xf3,0xe0,
+  0x43,0xf2,0x88,0x38,0x04,0x9e,0x25,0xae,0xa8,0x8a,0x0b,0xa5,0x11,0xed,0x39,0x5c,
+  0x6e,0x5a,0x19,0xc3,0x87,0xb2,0xf2,0x5f,0xa3,0xfd,0x91,0x56,0x0f,0xb3,0xf0,0x4f,
+  0x44,0xf7,0x38,0x55,0x08,0xeb,0xc4,0x88,0x76,0xf0,0xed,0x4d,0xba,0xd9,0xd3,0x5a,
+  0xc1,0x1c,0xa7,0x59,0x56,0xfe,0x2b,0xbc,0xc6,0x5f,0xda,0xd2,0xd6,0xce,0x4e,0x98,
+  0x6b,0xe6,0x95,0xb6,0xaa,0xc7,0x1d,0xc5,0x3c,0x07,0x4a,0x5b,0xf9,0xb2,0x81,0x62,
+  0xb1,0x06,0x4d,0x1b,0x6f,0x67,0xcc,0x8e,0x7f,0xd8,0x1a,0xd8,0xb6,0x88,0x1f,0x67,
+  0xe7,0x50,0x68,0x36,0xd4,0x53,0xac,0x58,0x5f,0x03,0x3b,0x0c,0xc7,0x2f,0x58,0x0d,
+  0xfc,0x44,0xfa,0x4c,0x93,0xe3,0xb8,0x3d,0xff,0x35,0x73,0x04,0xd6,0x99,0x01,0x02,
+  0x39,0xf8,0x43,0x8b,0xed,0x8b,0xae,0xd3,0xe4,0x72,0x76,0xc8,0x7d,0x6f,0xc8,0xf7,
+  0xb8,0x5a,0xae,0x1d,0x0a,0xf5,0x86,0x9c,0x51,0xd5,0x9b,0xd6,0x3f,0x3d,0xd2,0x8f,
+  0x5b,0xce,0x97,0x5b,0x20,0x67,0x90,0x9f,0x8f,0xa5,0x88,0x40,0x70,0x5e,0xcc,0x6e,
+  0xff,0x61,0xb4,0x79,0x04,0x15,0x7b,0xb0,0xd5,0xb5,0xd5,0x9e,0xff,0xd2,0xe2,0x70,
+  0xca,0x58,0x48,0xa4,0x7a,0xfa,0x62,0x1a,0xd1,0x3e,0xc8,0x0b,0x60,0x92,0x34,0xbc,
+  0x29,0x8f,0x6b,0x43,0xe8,0xbf,0x2b,0x83,0xb2,0x2d,0xff,0x95,0xc3,0x5b,0x9e,0x86,
+  0xe7,0x63,0x6a,0x8c,0x55,0x68,0xeb,0xa9,0x50,0xae,0x87,0x79,0x3b,0x9e,0xd7,0xab,
+  0xfa,0xf0,0xc8,0x28,0xac,0x07,0xbf,0xc8,0x4f,0xca,0xb6,0xfc,0x17,0x7a,0xe6,0x51,
+  0xd0,0xcb,0x55,0x60,0x06,0xc4,0xc1,0x87,0x0b,0xf6,0x80,0x1c,0x8d,0x27,0xab,0xb8,
+  0x8a,0x2b,0x9c,0x17,0x41,0x4c,0x89,0x4b,0xdd,0x96,0xc9,0x7f,0x49,0xb3,0x50,0x9f,
+  0xcc,0x33,0xbb,0x57,0x7b,0x96,0xe8,0x6b,0xad,0xb4,0xd7,0x55,0xb3,0x94,0x7d,0x8a,
+  0xf5,0xfd,0x9e,0x72,0xaf,0x85,0x52,0x33,0x2f,0x3b,0xff,0x55,0x0f,0x27,0xc4,0x82,
+  0x10,0xc2,0x92,0x2f,0x28,0xe7,0xc2,0x8d,0x21,0x67,0x2b,0x73,0xc3,0xde,0x70,0xa5,
+  0xee,0x5a,0x81,0xb0,0xdf,0xa4,0xd0,0x90,0x57,0xfd,0xdb,0x4c,0xfc,0xe7,0xda,0x9d,
+  0x68,0xd4,0xea,0x85,0x2b,0x26,0xf7,0x58,0x6e,0xd4,0x14,0xff,0xb9,0xca,0x5c,0x4c,
+  0x86,0xfe,0xa2,0x52,0x07,0x14,0x2f,0xb5,0xe5,0xbf,0xde,0x5d,0x34,0xa8,0xd5,0xc6,
+  0x36,0x26,0x9a,0xef,0x53,0xc6,0x44,0x11,0x39,0xf2,0xc1,0x9c,0xcb,0xd1,0xea,0xdf,
+  0x38,0x13,0xf2,0xdb,0xc6,0x50,0xb4,0x5a,0x77,0x25,0xb2,0xf2,0x5f,0x3f,0xe8,0x58,
+  0x1b,0x2a,0x5d,0xb9,0x78,0xdc,0x51,0x8c,0xfa,0x67,0x9b,0xc9,0x07,0x98,0x56,0x7e,
+  0x4e,0x93,0xc0,0x51,0xef,0xb9,0x14,0x5e,0x1b,0xd9,0x66,0xaa,0xbd,0xec,0x69,0x5b,
+  0xfe,0x6b,0x83,0xd8,0x40,0x61,0xa2,0xf6,0xf0,0x2c,0xd8,0x69,0x45,0x7b,0xb6,0xcf,
+  0x82,0x97,0x0a,0xcb,0x06,0x22,0xf7,0x78,0x86,0xcd,0x2d,0x94,0x0a,0x5c,0x31,0x60,
+  0xcf,0x7f,0x99,0xac,0x13,0x17,0x4d,0xf5,0xe6,0x02,0x74,0x8a,0x72,0x31,0x2f,0x97,
+  0x49,0x5d,0x7d,0x9a,0xae,0x3b,0x66,0xe7,0x0e,0xc1,0xc3,0x11,0xdd,0xbd,0x58,0x63,
+  0x91,0x0c,0xfe,0x29,0x8c,0x19,0xdd,0xd0,0x0b,0x6a,0x0f,0xc2,0xda,0xf7,0x63,0xb5,
+  0xe2,0xda,0x88,0x5c,0x0a,0x7d,0xe2,0x23,0xdd,0xf9,0x23,0x36,0xa6,0xfc,0x9a,0x3c,
+  0x8e,0xc8,0x0c,0x7b,0xfe,0x6b,0x0c,0xc6,0xa1,0x8e,0xa2,0x61,0xbb,0x60,0x62,0x51,
+  0xbd,0x51,0x90,0x22,0x1e,0x7c,0x87,0xd2,0x40,0xa7,0x61,0xb4,0x89,0x14,0xef,0x0c,
+  0x7b,0xfc,0xe7,0x24,0xf1,0x9f,0x8d,0xfc,0x0b,0xe8,0x7d,0x1c,0xd3,0xe6,0x27,0x69,
+  0xdb,0x28,0xa7,0x70,0xdb,0x6c,0x22,0x06,0xec,0x31,0x51,0x6d,0xba,0x42,0xdd,0xb6,
+  0xfc,0x97,0xb2,0x5c,0xeb,0x31,0x9e,0x16,0x05,0x54,0xbf,0x73,0x52,0xaf,0x02,0x35,
+  0x8e,0x8a,0x14,0x3d,0x7a,0x53,0xed,0x62,0x65,0x1e,0x61,0x6c,0x87,0x6b,0xa2,0xcc,
+  0x96,0xff,0x92,0xca,0xe1,0x31,0xf7,0x57,0x44,0x24,0xe6,0xee,0x61,0xa9,0x30,0x05,
+  0x3a,0x9e,0xd6,0xf5,0x5b,0x1c,0x1b,0x3a,0xba,0x4b,0xe6,0x82,0x43,0x64,0xe5,0xbf,
+  0xb8,0x10,0xb0,0xb2,0x85,0x68,0x87,0x2c,0x4a,0xb4,0x1f,0x60,0x49,0x46,0x85,0x2a,
+  0xb2,0x87,0x81,0x88,0x58,0xc4,0x33,0x96,0x95,0xff,0x12,0xbf,0x86,0xe7,0x12,0xd7,
+  0xc6,0x8b,0x36,0xb0,0x23,0xd0,0x60,0x22,0xb0,0x21,0x60,0xfc,0xdc,0xa0,0x6b,0xdf,
+  0x0c,0x9f,0x78,0x59,0xaf,0xbd,0x32,0xff,0x75,0x96,0x4f,0xc2,0x01,0x67,0x01,0xbe,
+  0x26,0xb3,0x12,0x61,0x03,0xd2,0xb8,0x74,0x0e,0x6e,0xe6,0xae,0x4e,0xf9,0xac,0x73,
+  0xc2,0xb8,0x09,0x36,0x1d,0xcf,0xc2,0x3f,0x49,0x38,0x07,0x01,0xa5,0xa0,0x4b,0x1e,
+  0x5f,0x3f,0xe4,0xaf,0x46,0xff,0x6e,0x59,0x5c,0x4c,0xf2,0x6f,0xab,0x94,0x71,0xee,
+  0x9a,0xd4,0xf7,0x70,0xd7,0xf1,0xac,0xfc,0xd7,0xcf,0x8c,0x03,0xc3,0x1e,0xb2,0xe6,
+  0x43,0xa1,0x67,0xbe,0xc1,0x4e,0xaa,0x2f,0xb0,0xf9,0xc6,0x81,0xfe,0xaa,0x71,0x7e,
+  0x03,0xf3,0xb5,0x1c,0x28,0xf1,0x9c,0x53,0x7f,0x92,0x95,0xff,0x1a,0x52,0xf6,0x48,
+  0x31,0xb3,0xcd,0xef,0x1e,0xea,0x12,0xba,0x70,0xe3,0xfb,0x3a,0x95,0x28,0xe5,0x23,
+  0x58,0xee,0xe0,0xce,0x98,0x47,0x07,0xcb,0xdf,0xcc,0xe0,0x1f,0xf4,0xe6,0xc0,0xfa,
+  0xe8,0x92,0x08,0x44,0x89,0x6d,0xee,0xd0,0xf9,0x01,0x9d,0xea,0xbf,0x2a,0xbc,0xe8,
+  0x91,0xe1,0xc2,0xc6,0x98,0x1d,0xff,0x50,0xf6,0x33,0x00,0x0f,0xa2,0x3d,0x52,0x8e,
+  0x28,0x16,0xdb,0x44,0x87,0xf3,0xd2,0x7d,0x88,0x61,0xf1,0x0b,0x7a,0x07,0xac,0xd4,
+  0x95,0x1d,0xff,0x1c,0x54,0xfe,0x88,0x66,0x5d,0x45,0x6b,0xae,0xdd,0x21,0x35,0xc2,
+  0x5f,0x9b,0xcd,0x63,0x70,0x89,0xdd,0x6c,0xe2,0xc6,0x38,0xa7,0xa4,0x52,0x87,0xd9,
+  0xf8,0x07,0x8e,0xe8,0x56,0xb6,0x6b,0x97,0x7e,0x04,0x82,0x03,0x4e,0x3f,0xae,0xff,
+  0x21,0x78,0xae,0x9f,0x22,0x1e,0xda,0x45,0xdd,0xc2,0xdb,0xe3,0x36,0xfc,0x83,0x4e,
+  0xa8,0xe9,0xa1,0xe7,0xef,0x17,0x11,0xe6,0xa9,0xe3,0x11,0x96,0xd4,0xd7,0x47,0xe8,
+  0x08,0xbe,0x56,0x5f,0x08,0x77,0x94,0xc8,0x8a,0xff,0x18,0x56,0x99,0x52,0x09,0x75,
+  0x26,0x10,0xe8,0x61,0x96,0x70,0x36,0x00,0x61,0xa1,0xd3,0x65,0xa8,0x91,0x0c,0x9f,
+  0x8e,0xeb,0x33,0x61,0xc3,0x3f,0x05,0xe2,0x91,0x48,0xa9,0xc9,0xef,0x63,0x6f,0xb2,
+  0xb5,0x94,0xf6,0x5a,0xcd,0xde,0x34,0xd6,0xa0,0xb0,0xf8,0x3e,0xf7,0x8f,0x94,0x7d,
+  0xd1,0xca,0xb7,0xd5,0x15,0x59,0xf8,0xa7,0x80,0xd2,0x52,0x63,0xce,0x7a,0x79,0x43,
+  0x34,0xb1,0xad,0x06,0x9c,0xbc,0x73,0x08,0xff,0x0b,0x35,0x89,0xf9,0x6a,0x73,0x8b,
+  0x36,0x1e,0x6b,0x80,0x02,0x2d,0x2b,0xfe,0x13,0x63,0x63,0xd2,0x6c,0x27,0x2e,0x42,
+  0x12,0x2e,0x17,0x2e,0x1c,0x9c,0x8f,0x6f,0x07,0xbf,0x27,0x1a,0xf3,0x59,0xb9,0xce,
+  0xb0,0xe2,0x3f,0xa3,0xd9,0xf1,0x1f,0x5c,0xff,0x5a,0x20,0x6f,0xd4,0x62,0x43,0xf9,
+  0xfc,0x45,0xdb,0x29,0xec,0x46,0xeb,0x7f,0x86,0x11,0x50,0x2c,0xc8,0xca,0x7f,0x15,
+  0x3e,0x4e,0xf1,0x1f,0x0a,0x6a,0xcd,0x82,0x83,0xac,0x14,0xb8,0xe1,0x76,0x42,0x17,
+  0xf8,0xfa,0xb9,0xc1,0x4e,0xa0,0x50,0x4a,0x89,0x78,0x3b,0xfe,0xb1,0xe2,0x3f,0xf4,
+  0x9a,0xb3,0x53,0x69,0xbe,0xd5,0xe1,0x14,0xfe,0xc1,0x23,0x47,0xa1,0xf3,0x5f,0xaa,
+  0xff,0x8a,0xa3,0x7f,0xd1,0x0a,0x0c,0x77,0x4c,0x12,0xd7,0x9f,0xf8,0x0c,0x82,0xfb,
+  0x20,0x52,0xe0,0x19,0x00,0xd2,0xe7,0x7f,0x52,0xff,0x75,0x01,0x6a,0x3b,0x9c,0x94,
+  0xff,0xba,0x90,0x0c,0x44,0x96,0xec,0x9a,0xd1,0x43,0xfd,0x13,0x84,0xf3,0xa7,0xf2,
+  0x99,0xc8,0x61,0x33,0x10,0x77,0x9d,0xc9,0xc2,0x3f,0xe3,0x56,0xd9,0x97,0xcb,0x90,
+  0x77,0x03,0x95,0x7d,0xcd,0xc7,0xad,0x04,0x53,0xdb,0x66,0x9c,0x88,0x19,0xb0,0xd4,
+  0xbc,0x02,0xff,0x9c,0x97,0x82,0xc6,0x92,0x68,0x11,0xb1,0x91,0x03,0xa1,0x25,0x57,
+  0x77,0x96,0xa3,0xbd,0x6b,0x30,0x96,0x6b,0x65,0xe5,0xfc,0x7c,0x22,0xd0,0x94,0x7f,
+  0x45,0xfd,0x17,0xec,0x87,0x02,0x83,0x23,0xfe,0xa1,0x44,0xcc,0x8a,0xfc,0xad,0x54,
+  0x76,0x2d,0xaa,0x8c,0x88,0x55,0x91,0x2d,0x62,0x08,0x8d,0x98,0x9e,0x15,0xff,0x79,
+  0x41,0x92,0x8d,0xbc,0x61,0x56,0xa3,0xbf,0x00,0x3b,0x5a,0x49,0x30,0x5e,0xd0,0xe7,
+  0x1b,0x8e,0x61,0x47,0x0d,0xbc,0x00,0x65,0xad,0xc4,0x57,0xb1,0xe9,0x9f,0xe2,0xd8,
+  0xb3,0xde,0xca,0xb6,0x79,0xcb,0xde,0x25,0xc1,0xaa,0xf6,0x4a,0x1d,0x71,0xa0,0x10,
+  0x7f,0xd6,0x2b,0xb7,0xf1,0x65,0x57,0xe0,0x9f,0xe7,0xf5,0x3a,0x9e,0x4f,0xd5,0x5e,
+  0x13,0x08,0x84,0x48,0x88,0x50,0xfe,0xeb,0xf6,0x70,0x91,0x2e,0x2e,0xe0,0x11,0xe7,
+  0x80,0x6a,0xe7,0xff,0x58,0x6c,0x8d,0xc3,0x05,0xbd,0x88,0x7f,0xce,0x57,0x50,0x21,
+  0x98,0x9a,0x5a,0x81,0xdb,0x36,0x3f,0x8c,0x47,0xbc,0x41,0x82,0x0a,0xb6,0xf8,0xcf,
+  0x2d,0x23,0xfc,0x9f,0x53,0x24,0x9f,0x9a,0x58,0x87,0xbf,0x9a,0xd8,0xce,0x35,0xf0,
+  0x9a,0x5e,0xd4,0xe6,0x7c,0x58,0x5e,0x6e,0x31,0x36,0x79,0x36,0xff,0xe7,0x34,0x6c,
+  0x95,0x3c,0x39,0xf9,0x94,0xff,0xea,0xa9,0xf1,0x94,0xe0,0x87,0xe6,0x35,0x10,0xff,
+  0x80,0xb7,0xb3,0xa9,0xd4,0x1f,0xe1,0x56,0x69,0x98,0x1d,0xff,0x0c,0xde,0xda,0x31,
+  0x73,0xbb,0x95,0xff,0x8a,0x6d,0xd3,0x63,0x2d,0x75,0x85,0x15,0x8a,0x95,0xf6,0x42,
+  0x58,0xd8,0x62,0x76,0xa0,0xf9,0xf1,0x16,0x66,0xe3,0x1f,0x8a,0xf6,0x1b,0x79,0x51,
+  0xc7,0x1c,0xb1,0xcd,0x62,0x8f,0x7b,0xca,0x8d,0x75,0x08,0x44,0x79,0x94,0xcd,0x61,
+  0xeb,0x52,0x7c,0x72,0x1b,0xfe,0x29,0xfc,0x2d,0xbc,0x6e,0x06,0x56,0x39,0x1f,0xff,
+  0xd4,0xf5,0xf0,0x5e,0x0a,0xe8,0x5e,0x4f,0xb0,0x96,0x12,0x61,0x5f,0x9e,0x86,0xbe,
+  0x76,0xfc,0xf3,0x04,0x9c,0x37,0x82,0xed,0x4b,0xb7,0x34,0x8f,0x4c,0x47,0x7b,0x5e,
+  0x65,0xd3,0x89,0xb0,0x54,0x45,0xbc,0x66,0xaf,0xff,0xd2,0x04,0x0c,0xeb,0x01,0xb4,
+  0xc2,0x5f,0xa2,0x66,0x22,0x68,0x0d,0x81,0x02,0x8f,0x28,0x2c,0x15,0xcd,0x12,0x9e,
+  0xf2,0x53,0x21,0xbc,0x3d,0xfe,0xe3,0x85,0xa3,0x09,0x8f,0xf0,0xc6,0xe4,0x1b,0xa1,
+  0x80,0xed,0x10,0x6a,0x0f,0x1a,0xb2,0xe7,0x41,0xa7,0xb2,0x77,0xca,0xf0,0x7a,0x62,
+  0x3c,0xab,0xfe,0x3d,0x67,0x09,0xfa,0x5f,0xdb,0x4d,0x1e,0x6f,0xbb,0xcd,0xd3,0x09,
+  0x9e,0x21,0xb5,0x84,0xbd,0x0a,0xbb,0xd1,0x71,0x40,0xc5,0xeb,0x64,0x9d,0xa9,0xfe,
+  0x1b,0x87,0x6d,0xf8,0xc7,0x89,0x68,0xb9,0x74,0x10,0x0f,0x16,0x53,0xfe,0x1a,0x61,
+  0x4f,0xf8,0x94,0xbe,0xcf,0x28,0xa5,0xc4,0xd9,0x2c,0xd1,0x09,0xa5,0x03,0x7c,0x15,
+  0xfe,0x17,0xa7,0xef,0xdf,0xc3,0x67,0x53,0xb5,0xd7,0x19,0xe7,0x7d,0xf2,0xed,0xce,
+  0x9f,0x87,0x2d,0xfe,0xf3,0x9b,0xf0,0xb1,0xd8,0x4d,0x61,0x9f,0x02,0xf1,0x6a,0xaa,
+  0xfe,0xeb,0x4c,0x06,0xff,0x7c,0x7a,0x17,0x7b,0x0f,0x66,0x27,0xd0,0xcc,0x8d,0x4c,
+  0xd1,0x9e,0x09,0xf6,0xb0,0x60,0xbf,0x6b,0x37,0x2a,0xea,0x54,0x6a,0x2c,0x0b,0xff,
+  0x4c,0x9a,0x97,0x45,0x35,0x05,0x79,0x82,0x70,0x2c,0xb1,0x70,0xa7,0x93,0x88,0xd0,
+  0x68,0xd6,0x7f,0xe3,0x3a,0x28,0x07,0xf5,0x63,0xa2,0x28,0xe9,0xda,0x6f,0xaf,0x7f,
+  0x2f,0xfc,0x51,0xff,0x6f,0x5b,0x4b,0xdf,0xf3,0x8e,0x87,0x8b,0x61,0x87,0x62,0xd5,
+  0x9f,0x9e,0xf2,0xac,0x2d,0x29,0x35,0x8b,0xea,0xd7,0x37,0x28,0xdb,0xf9,0x0d,0xa6,
+  0xfa,0x2d,0x5b,0xfd,0x17,0xc0,0xe3,0xb0,0x43,0x2b,0x4d,0x20,0xa8,0x9b,0xa5,0x3f,
+  0x02,0xe5,0x74,0xfd,0x90,0x41,0x2f,0x2e,0xdf,0xcb,0xee,0xc2,0xa5,0xc3,0x15,0xb8,
+  0x37,0x2b,0xfe,0x73,0xd4,0xd8,0x21,0x62,0xe3,0x79,0xf5,0xb9,0x33,0x60,0x8f,0xa1,
+  0x47,0xbd,0x37,0xb2,0x21,0xd1,0xd9,0xa2,0x1f,0x52,0x1b,0xd8,0x6d,0xd0,0xd3,0x65,
+  0x75,0xe4,0xb0,0xc7,0x7f,0x76,0xc1,0x3b,0xa2,0xfa,0xed,0xca,0x49,0xdc,0x36,0x6f,
+  0xb5,0xd7,0x8e,0x6e,0x88,0xcb,0xc7,0xe0,0x88,0xe8,0x1d,0x77,0x4d,0xc8,0xdf,0x8d,
+  0x1c,0x11,0x7e,0x6a,0xb4,0x72,0x26,0x5d,0x0f,0x8b,0xf8,0x47,0x7f,0xbf,0xb5,0x61,
+  0xa0,0x20,0xde,0x9c,0x14,0xef,0x68,0xc1,0x88,0x2b,0xbe,0x76,0x0c,0x3e,0xce,0x0b,
+  0x0e,0xba,0xfc,0x9d,0xbb,0xc4,0x45,0xfe,0x9d,0xb7,0x51,0xb0,0xe3,0x9f,0x53,0xf0,
+  0x56,0xb8,0xd6,0x74,0xae,0xc2,0xcf,0x0a,0x81,0x90,0xb9,0xe4,0x7e,0x39,0x98,0x77,
+  0xc4,0xb4,0xca,0xbe,0x66,0xc1,0x51,0x7d,0x61,0x72,0xc9,0x78,0x99,0x1d,0xff,0xac,
+  0xd4,0xba,0x4d,0x8f,0xd9,0x1a,0x47,0xa5,0xd1,0x8d,0xfe,0x94,0x37,0x4e,0xf5,0x5f,
+  0x60,0x95,0xbd,0xfb,0x60,0xbd,0x5e,0xdb,0x9f,0x1f,0x67,0x59,0xfc,0x1f,0xe8,0xd6,
+  0xe7,0x52,0x52,0x63,0xae,0x8e,0x97,0x45,0x89,0xff,0x63,0x3c,0x66,0x5d,0xef,0xf0,
+  0xc1,0x63,0x54,0x08,0x16,0xb7,0xe3,0x1f,0xc8,0xc7,0x4d,0xa5,0x9f,0xac,0x5b,0x80,
+  0xda,0xac,0x53,0xd3,0x85,0xc3,0xef,0xa0,0x8a,0xf8,0x58,0xbf,0x1a,0x70,0x38,0x95,
+  0x87,0xb5,0x72,0x33,0xcf,0x7f,0xb5,0x0d,0xff,0x38,0xbf,0x0a,0x47,0x60,0xe1,0x2f,
+  0x9d,0x7b,0xcb,0x14,0xf6,0x73,0xa3,0x57,0x38,0x9f,0x65,0x3e,0xfe,0x18,0xd1,0x4a,
+  0xbf,0x29,0x5b,0x15,0xf1,0x64,0x9a,0xed,0xf8,0x67,0x6c,0xd1,0xef,0x60,0x36,0xbe,
+  0x5d,0xf5,0x39,0xb8,0xcc,0x1a,0x85,0x15,0xf8,0xb2,0x68,0xab,0x1f,0x77,0x4e,0x82,
+  0x15,0xfa,0x38,0x97,0x85,0x7f,0x06,0x61,0xa8,0x2b,0x00,0xf3,0xef,0x94,0x27,0x43,
+  0x68,0xdd,0xa0,0xa0,0x4f,0xbe,0x16,0x7e,0x47,0x8c,0xa9,0x8f,0xe4,0x11,0xf6,0x0a,
+  0x54,0xeb,0xbe,0x89,0x2c,0xfc,0xf3,0xa1,0x32,0xcc,0x3c,0x12,0xdf,0xea,0xa9,0x14,
+  0x2f,0x41,0x15,0x15,0x6a,0x35,0x88,0x67,0xf4,0xb2,0x90,0xfa,0x09,0xfb,0x03,0x5b,
+  0x67,0x56,0x24,0x79,0x6f,0xd8,0x1e,0xff,0x19,0xb4,0x5a,0x0e,0xa9,0x51,0xb6,0x24,
+  0x15,0xdd,0x8a,0x33,0xa7,0xe8,0xe4,0xba,0x81,0xdf,0xcb,0x20,0x8b,0x19,0x1e,0x51,
+  0x12,0xb8,0xa2,0xfe,0xfd,0x07,0x06,0xa2,0x85,0x68,0x2a,0xbf,0x36,0xc0,0xfb,0x88,
+  0x56,0x2d,0xb6,0x1b,0x8b,0xe3,0x30,0xa6,0xf5,0x88,0x8a,0x64,0x24,0x9e,0x85,0x7f,
+  0x46,0xee,0x4c,0xb4,0xfb,0x6b,0x5c,0x85,0xea,0x4a,0x85,0x1a,0x23,0x14,0x10,0x3f,
+  0xf9,0x7d,0xf4,0xc8,0x36,0xc5,0xe5,0x11,0xe3,0x3d,0xd3,0xdf,0xe3,0xcc,0xc6,0x3f,
+  0x3f,0x42,0x7c,0x18,0x84,0xa5,0x27,0xe5,0x95,0x30,0xc5,0x76,0x9e,0xa4,0xb2,0xf7,
+  0xdf,0xb8,0xc6,0x3b,0xcf,0xc1,0x3f,0xa7,0xf2,0x3b,0x59,0xfc,0x67,0x91,0x08,0x05,
+  0x34,0xdf,0x66,0xd9,0xc7,0x8f,0x40,0xcd,0x70,0x3e,0x7e,0x8f,0xf2,0x11,0xaa,0xe7,
+  0x25,0x86,0xde,0x2f,0x8c,0xc0,0x16,0x67,0x5c,0xb5,0xc7,0x7f,0xe6,0x87,0x23,0xfd,
+  0x4f,0x07,0xbc,0x5b,0x58,0x83,0x7b,0x13,0xae,0x8f,0x77,0x1f,0x9b,0x0c,0x59,0xfd,
+  0x5b,0x26,0xc2,0x83,0x94,0xa1,0xa0,0xfe,0x3f,0x76,0xfe,0xcf,0xad,0x10,0x11,0xe5,
+  0x03,0xbc,0xd8,0x8a,0x97,0x96,0x13,0x8d,0xe7,0x03,0x34,0xd1,0xe5,0x2d,0x79,0x75,
+  0x6c,0x10,0x76,0x7f,0x5d,0x4f,0xe6,0xf9,0xb3,0xf8,0xcf,0xb3,0x87,0xbb,0xa2,0x95,
+  0x94,0x06,0x9a,0x6d,0xac,0x15,0x5f,0x1d,0xe5,0xf7,0x35,0xbd,0x49,0x78,0x20,0xd4,
+  0xbd,0x9a,0xfd,0x0a,0xf2,0x63,0xdb,0x4e,0x4b,0xd9,0xfc,0xe7,0x5c,0x61,0xf2,0x9a,
+  0x78,0x44,0x53,0x9d,0xf0,0x72,0xbc,0x66,0xc0,0x79,0xa3,0x3c,0x04,0x9d,0x46,0xcd,
+  0x92,0xfc,0xc0,0x8c,0xa3,0xfa,0xb2,0x98,0x7f,0x70,0x4d,0x3c,0x8b,0xff,0x73,0xd0,
+  0x98,0x94,0xea,0x37,0xb8,0xce,0x96,0x8d,0xc1,0xe5,0x96,0x6b,0x13,0xd4,0x2f,0x42,
+  0xbf,0xac,0x05,0xef,0xc0,0x65,0xf9,0x67,0xe5,0xb2,0x45,0x94,0xca,0xc2,0x3f,0x83,
+  0x90,0x90,0x02,0x46,0x6e,0x54,0xfe,0x29,0x3b,0xd2,0x6e,0xd1,0xae,0xc6,0xc4,0xb7,
+  0xa1,0x7e,0xd8,0xf5,0x1c,0xba,0x06,0xaf,0xcb,0x01,0x73,0x53,0xbc,0xd9,0x8e,0x7f,
+  0xb6,0x20,0xc8,0xd9,0x41,0x41,0xe3,0x59,0x62,0xad,0x5e,0x69,0x52,0x22,0xcc,0x24,
+  0x44,0xa4,0xde,0x8b,0x1a,0x69,0x8d,0xa5,0x51,0xb3,0xf0,0x4f,0x80,0xad,0x11,0x77,
+  0x27,0xdb,0x4e,0xe6,0x1e,0x5d,0xb4,0x56,0xf8,0x92,0xeb,0x89,0x08,0xfd,0x88,0x98,
+  0x33,0xae,0xde,0xc8,0xbe,0x08,0x8f,0x74,0x94,0x26,0xaf,0xc9,0xc6,0x3f,0x47,0x41,
+  0xe8,0xfa,0x29,0x4e,0x61,0xb4,0x4e,0xf0,0x8d,0xe5,0x15,0xa2,0xff,0xd2,0x1b,0xf3,
+  0x25,0xbb,0xad,0x23,0xa1,0xd0,0x88,0xea,0xcf,0xc2,0x3f,0x7d,0xa1,0xa3,0x7a,0x35,
+  0x82,0x6c,0x99,0xbc,0xe3,0x9b,0x63,0x05,0x3d,0x28,0x5c,0x4a,0xd6,0x13,0xed,0x79,
+  0x05,0xbc,0xd9,0xb2,0x87,0x5c,0xd1,0xac,0xf8,0x0f,0x9f,0x90,0x1a,0xb4,0xa5,0xe9,
+  0x6c,0x57,0x97,0x9c,0xce,0x88,0x09,0xe3,0x5f,0xc8,0x7f,0x0d,0x4a,0x64,0x0d,0x97,
+  0x44,0x9b,0xa9,0x0c,0x3c,0xd0,0x92,0x1f,0x95,0xe7,0x8a,0xd7,0xa5,0xda,0x90,0x13,
+  0x11,0x91,0x58,0x07,0xf5,0xc4,0x8f,0x1d,0xc8,0xc2,0x3f,0xb8,0x49,0x56,0x38,0xb6,
+  0x10,0xda,0x61,0x15,0xab,0xf2,0xb7,0x38,0xe6,0x78,0xd7,0x49,0xe5,0x46,0x8f,0x56,
+  0xf6,0xdf,0x94,0x0e,0xca,0x8f,0x5f,0x91,0xff,0x62,0x1d,0xc2,0x43,0x49,0x99,0xe5,
+  0xb0,0x1b,0x2a,0xda,0x1d,0x5a,0x58,0xc1,0x3b,0xcc,0x6d,0x8d,0x6c,0xc9,0xdd,0xe9,
+  0x79,0x46,0xab,0x68,0xbd,0xa2,0xfe,0x2b,0x37,0x86,0x46,0xad,0x6d,0xbd,0x3f,0x57,
+  0x89,0xed,0x9e,0xc7,0xdb,0xd0,0x1b,0x55,0x76,0x74,0x48,0x73,0x89,0xff,0x43,0x85,
+  0x60,0x1e,0x03,0xae,0xa8,0xff,0x42,0x7f,0x2d,0xc0,0xab,0x84,0x1c,0x42,0xfc,0x53,
+  0x41,0x82,0x2e,0x12,0x70,0x15,0xdf,0x10,0x6e,0x8e,0x45,0x47,0xf5,0x7a,0xe2,0x9f,
+  0x1c,0xb5,0xf3,0x9f,0xe1,0x93,0x8a,0xc6,0x36,0x57,0xbb,0x3c,0x12,0x3f,0x8f,0x42,
+  0xfe,0xf1,0xce,0x91,0x9d,0x56,0xfd,0x57,0xb4,0xf9,0x0e,0xf6,0x8f,0x54,0xe1,0x75,
+  0x65,0xfd,0xd7,0x2b,0xd0,0x88,0xb0,0x87,0xed,0x8c,0x1d,0xf2,0x57,0x1b,0x88,0x7f,
+  0xce,0x21,0x6c,0xb0,0xea,0xdf,0xcf,0x81,0x55,0x11,0x16,0xcd,0xc6,0x3f,0x5a,0x2b,
+  0xaf,0x52,0x22,0x82,0x85,0x44,0xc4,0xbf,0x70,0x73,0x05,0x84,0x93,0x46,0xc4,0x5b,
+  0x05,0x8e,0x0e,0x76,0x1a,0x4e,0x4a,0xe8,0x5f,0x84,0x37,0x3f,0x68,0xd7,0x3f,0x4d,
+  0x1d,0x92,0xcf,0xc8,0xd3,0x3c,0x83,0xb1,0x87,0x74,0x7d,0x49,0x1e,0x25,0xfe,0x3a,
+  0x62,0x54,0xff,0xee,0x1e,0x31,0xa8,0x10,0xbe,0xdb,0x9d,0x8d,0x7f,0xba,0x1e,0xbd,
+  0xa7,0x0a,0xf1,0x0f,0xae,0xe7,0xa3,0x50,0x7e,0x8b,0x9a,0xe2,0xff,0x54,0xdd,0xe2,
+  0x88,0x7a,0x46,0xe0,0xd1,0x10,0x15,0xe2,0xb1,0x07,0xec,0xf1,0x1f,0x71,0x68,0x20,
+  0xb8,0x22,0x3f,0x5a,0xb4,0x93,0x11,0x6d,0x3b,0x9f,0xf8,0x3c,0x87,0x20,0x88,0xbf,
+  0x6f,0xf3,0x20,0x1c,0x12,0xc1,0x90,0x2b,0x1b,0xff,0x3c,0x40,0x6c,0x8d,0xf6,0x2a,
+  0x62,0x07,0xa1,0x60,0x14,0x50,0x99,0x58,0x8a,0x11,0xd4,0x4c,0x44,0xe8,0xd9,0xab,
+  0x36,0x45,0xb3,0xe2,0x3f,0xdb,0xfc,0x77,0x7a,0xfc,0x57,0xf9,0xc8,0x89,0x1e,0x87,
+  0x80,0x8e,0x8e,0x86,0x8e,0x30,0xa0,0x56,0xa1,0x44,0x98,0x9f,0xea,0xdf,0x51,0xb0,
+  0xc7,0x7f,0x6e,0x54,0x8e,0xea,0x65,0xb1,0xd6,0x10,0xeb,0x41,0xd8,0xf3,0xb7,0x7d,
+  0xde,0x51,0xf7,0xa7,0xcd,0xf5,0xe0,0x8b,0x2d,0x1e,0x91,0xbf,0x25,0x3e,0x3c,0xd4,
+  0x19,0x53,0x63,0x4d,0x76,0xfe,0xf3,0x67,0x59,0xa7,0x59,0x3e,0xce,0xab,0x99,0x4f,
+  0xdb,0xa3,0xe8,0x94,0x7d,0x70,0xf2,0x1d,0xe4,0x98,0x57,0x86,0x0b,0x58,0xa7,0x80,
+  0x51,0x34,0x7c,0x36,0xfe,0xb3,0xd4,0x80,0x58,0xac,0xdc,0xe4,0x21,0xc7,0xe3,0x62,
+  0x8f,0x7f,0x9e,0x19,0xb9,0x33,0x5c,0x2c,0x59,0xf1,0xdb,0x56,0xd6,0x02,0x4f,0x0a,
+  0x8b,0x21,0x63,0x8f,0xff,0xcc,0x56,0x06,0x3b,0x6e,0x48,0x3a,0x43,0xf2,0xec,0x9e,
+  0x3f,0x8a,0xd2,0x98,0x63,0x05,0x3e,0xed,0x6f,0xf1,0xc8,0xd2,0xd5,0x33,0x66,0x43,
+  0xbf,0x58,0x90,0x5c,0x3a,0xa1,0xda,0xf8,0xcf,0x9f,0xdd,0x80,0x6f,0xf7,0xbc,0xb9,
+  0x54,0x97,0xc7,0xcc,0x8b,0x6d,0x0d,0x61,0x57,0x94,0xf8,0x84,0xee,0x20,0xd1,0x74,
+  0x47,0x58,0x1e,0x20,0x10,0xca,0xc6,0x3f,0xa7,0x8c,0x7f,0x12,0x0b,0x7f,0x93,0x9f,
+  0x90,0x5f,0x84,0xb7,0x3a,0x1a,0x93,0x9b,0x26,0xca,0x50,0x10,0xd5,0x23,0xce,0xa7,
+  0xe4,0xab,0xb5,0x9f,0x77,0x11,0x34,0xea,0xb4,0xe3,0x9f,0x1f,0x0a,0x74,0xb2,0xfa,
+  0x12,0x4d,0xe8,0x4f,0xfd,0x12,0xae,0x3f,0x34,0xe3,0x5e,0x7d,0x0b,0x02,0x83,0xd2,
+  0xd1,0x82,0xaf,0xb1,0x42,0x65,0x07,0x15,0x62,0x7c,0x9d,0xd9,0xf1,0xcf,0x41,0xee,
+  0x82,0x39,0x83,0x79,0x26,0x3b,0xa5,0xd1,0x6b,0xb6,0x85,0x62,0x11,0x78,0x04,0xe6,
+  0xf4,0xe7,0xe9,0xe8,0xc1,0x11,0x83,0xe8,0x8a,0xfc,0xd7,0x31,0x11,0x21,0xf6,0x26,
+  0xa0,0xb6,0x79,0x0c,0xca,0x07,0xf2,0xfa,0xf0,0xdd,0x3a,0x23,0xe5,0xa6,0x43,0x67,
+  0x05,0xc6,0x0e,0xa5,0x67,0x18,0x2d,0xa6,0x1d,0xff,0x3c,0xc0,0xba,0x79,0xed,0xdb,
+  0xf9,0x9c,0x4d,0xe2,0x63,0x34,0x0c,0x17,0x50,0xfd,0xce,0x5b,0xf0,0x63,0x33,0x3f,
+  0xa6,0x56,0x41,0xa7,0x14,0x38,0xed,0x1b,0x2f,0x3b,0x63,0x8f,0xff,0xb4,0x8e,0x4a,
+  0xc1,0xe1,0xa5,0x11,0x75,0x17,0xbf,0x08,0xb5,0x83,0x05,0xd1,0xb2,0xdf,0xc0,0x45,
+  0xad,0x2e,0x89,0x8a,0xe8,0x03,0xb8,0xc8,0x83,0xa7,0xae,0xe0,0x3f,0x9f,0x83,0x37,
+  0x79,0xb5,0xe9,0x33,0x9b,0x1b,0x88,0xbd,0x29,0x66,0x24,0xcb,0x7e,0xc5,0x8e,0x01,
+  0x4b,0x14,0x24,0xe5,0x49,0xe5,0xad,0x62,0x5c,0xa8,0xf1,0x2c,0xfe,0xf3,0xd7,0x20,
+  0xa2,0xe8,0xc9,0xd6,0x08,0xda,0xc7,0x03,0x88,0x96,0x57,0x44,0x99,0x07,0x17,0xca,
+  0x93,0x44,0x47,0xfe,0x55,0x78,0x06,0xf4,0x51,0x9e,0x8d,0x7f,0xe6,0xc2,0x63,0xc2,
+  0x13,0xe2,0x1b,0xc8,0x5e,0x4b,0x5f,0x49,0xe4,0xc5,0xd9,0xdf,0x10,0x4d,0xd7,0x6c,
+  0xeb,0xf1,0x7c,0xc8,0x51,0x10,0x91,0x2c,0xfc,0xa3,0x38,0x25,0xc4,0x03,0x27,0xad,
+  0xf5,0x21,0xa2,0xa6,0xd7,0x8f,0xeb,0xf3,0x18,0xc4,0x12,0x1c,0xc2,0xaf,0x71,0x8f,
+  0xe9,0xe9,0xe0,0xfe,0x02,0x7b,0xfc,0xe7,0xcb,0x8b,0x7e,0x0d,0xbd,0xc7,0xb9,0x28,
+  0x9b,0xd5,0x75,0xb9,0xbd,0xd6,0xcc,0x9f,0x23,0x87,0x94,0x23,0x8a,0xfb,0x70,0x41,
+  0x4c,0xfe,0xa0,0xf0,0xf5,0x45,0x01,0x2a,0x9d,0xb3,0xe3,0x9f,0x49,0x31,0x06,0x0d,
+  0xe6,0x0c,0x43,0x1a,0x33,0xbe,0x5b,0xde,0x68,0x6c,0xfc,0x08,0xd1,0xcb,0x65,0xf8,
+  0x8e,0x39,0xc3,0x94,0x27,0xd9,0x51,0xf4,0x11,0xb3,0xeb,0xdf,0x73,0x3e,0xbc,0xe5,
+  0x72,0xb4,0x31,0xe9,0x3b,0x2f,0x4f,0x8a,0x63,0x62,0x4f,0x79,0x41,0x9f,0x2b,0x08,
+  0xbf,0x8b,0x06,0x5e,0xd9,0x70,0x56,0xbe,0x09,0xde,0x8a,0x56,0x27,0x97,0x4c,0x96,
+  0xd9,0xeb,0xbf,0xa8,0x2c,0xcb,0x47,0xa0,0xee,0xab,0xb1,0x6e,0xaf,0x27,0xa1,0xf6,
+  0x32,0x5f,0x4c,0xf6,0x54,0x44,0x5a,0xff,0x78,0x4f,0x0f,0x7f,0xa6,0xd4,0x93,0x40,
+  0x84,0x63,0xaf,0xff,0x1a,0x8a,0x96,0xe9,0xbe,0x01,0xee,0x87,0x8d,0xf8,0x6b,0xea,
+  0x89,0x6e,0x7f,0xd8,0xa9,0xec,0x90,0xbc,0xe6,0x0a,0xbf,0xc3,0x27,0xf6,0xe8,0x9e,
+  0x01,0x1e,0xb0,0xd5,0x5f,0x10,0xfe,0x39,0x90,0x22,0xc9,0x50,0x1b,0x37,0x0f,0xf1,
+  0x7f,0x9c,0x28,0x78,0x4f,0xa2,0x45,0xfb,0x29,0x6c,0x8f,0x78,0x08,0x41,0xd9,0xeb,
+  0xbf,0x52,0xd5,0x01,0xce,0xfd,0xf2,0x2e,0x76,0xa4,0x23,0x90,0x7c,0xf0,0xa0,0xbb,
+  0xaa,0xf0,0x7d,0xa8,0x1f,0x6f,0x8d,0x17,0xb9,0xf4,0xd7,0x45,0x9c,0x1a,0xf1,0xd9,
+  0xeb,0xbf,0x0e,0xf2,0xef,0x42,0xe3,0xb8,0x05,0x7b,0x2e,0x7b,0x10,0xed,0x7c,0x44,
+  0x65,0x80,0xd1,0x60,0x72,0xe9,0xb8,0x7c,0x8e,0xbf,0xa4,0x34,0x8e,0x5c,0x81,0x7f,
+  0x76,0xc1,0xfb,0x4a,0x00,0x41,0x4b,0x91,0x4f,0x79,0x5f,0xaa,0x35,0x7d,0x7b,0x55,
+  0x9f,0x76,0x11,0x02,0x89,0xfc,0x3d,0xf2,0x57,0x0d,0x8a,0x6f,0x5c,0x51,0xff,0x55,
+  0x69,0x1c,0xb8,0xd3,0x73,0x82,0xef,0xcb,0xbd,0x76,0xf9,0x81,0x76,0xcf,0xaf,0xf8,
+  0xb3,0x1e,0x9f,0x38,0x70,0xe7,0x17,0x4e,0xf2,0x73,0x6c,0xbe,0xb1,0x5e,0xd4,0x9e,
+  0xcb,0x7f,0x21,0xbb,0xfe,0xdd,0x78,0x18,0xb6,0x8f,0x20,0xc8,0x29,0x80,0x67,0xa2,
+  0xe5,0x66,0xc5,0x7e,0x96,0x5f,0x7e,0x40,0xe8,0x8b,0xf2,0xea,0x72,0xbb,0x78,0x67,
+  0xab,0x9e,0x2c,0x89,0xb3,0xd5,0x76,0xfc,0x03,0xfb,0xa2,0xa5,0x56,0x3c,0x44,0x90,
+  0x10,0xb9,0x2f,0x97,0x02,0x23,0x73,0x92,0x25,0x75,0xec,0x39,0x58,0xbb,0xfe,0xcb,
+  0x49,0xe9,0xbe,0x2b,0xe2,0x3f,0x17,0x35,0x3f,0x3e,0xbf,0xc3,0x69,0xbc,0x0f,0xb5,
+  0x27,0x0a,0x5e,0xa4,0x44,0x3f,0xe8,0x44,0xd4,0x19,0x42,0x43,0xe3,0x1f,0x70,0x3e,
+  0xdf,0xb9,0x2c,0x0b,0xff,0x7c,0xd7,0x6a,0x8b,0x24,0x4d,0x0e,0x5f,0x4c,0x55,0xbb,
+  0x4f,0x1a,0xdf,0x85,0xe0,0xe0,0xa6,0xbd,0xea,0x5d,0xec,0xa2,0x76,0xf3,0xa0,0xeb,
+  0xac,0x6c,0xcf,0x7f,0x8d,0x21,0x3e,0xaf,0xb7,0x60,0x0f,0x0a,0xb5,0xe6,0xa6,0x68,
+  0xd9,0x87,0x1a,0xd1,0xa2,0x0a,0xf6,0xc8,0x2b,0xf9,0x21,0x11,0xa0,0x40,0x99,0xbd,
+  0xfe,0xeb,0x20,0x6c,0x02,0x4b,0x69,0xfc,0xb3,0xe5,0x3f,0xca,0x54,0x4f,0xba,0x96,
+  0xe2,0x81,0x1f,0xb1,0xbd,0xec,0x49,0x78,0xaa,0x9f,0xaf,0xca,0xaa,0xff,0xfa,0x11,
+  0xa2,0xbb,0xf9,0x44,0x73,0x7a,0x53,0x6c,0xa2,0xfa,0xf7,0xd5,0xa1,0x4b,0x84,0xf7,
+  0xc6,0xf1,0xc8,0x6c,0x7d,0xa3,0xb0,0x96,0xc2,0x5e,0xff,0x35,0x44,0x30,0xb2,0x85,
+  0x7f,0x9a,0xf2,0x5f,0x61,0x7d,0x52,0x9d,0xc3,0x6e,0x85,0x8e,0x42,0xdf,0x30,0xee,
+  0x9f,0x8d,0x62,0x87,0xf0,0x86,0x78,0x76,0xfd,0x57,0x0f,0x7a,0xb7,0x56,0xfd,0xfb,
+  0x28,0x1c,0x8d,0x55,0x47,0x5d,0x49,0x79,0x14,0x8f,0x34,0xc6,0x1c,0x31,0xb9,0x9e,
+  0x1f,0x15,0x81,0xf0,0xae,0x2b,0xea,0xbf,0x2c,0xf6,0xcb,0x52,0xc1,0x4e,0xb3,0x09,
+  0xe9,0x79,0x70,0x85,0x89,0xf6,0x4c,0xf5,0x5f,0x4a,0x11,0x22,0x22,0xed,0xc5,0x2b,
+  0xf1,0xcf,0x08,0x1c,0x62,0x96,0x59,0x2c,0xe7,0x87,0xa0,0x82,0xfa,0xff,0x94,0x13,
+  0x10,0x32,0x36,0x3c,0x4a,0x19,0x31,0xa5,0xca,0x70,0x6e,0xcd,0x8a,0xff,0x7c,0xd9,
+  0xb3,0xae,0x75,0xfb,0x32,0xca,0x7f,0xb1,0x43,0xad,0xe1,0x65,0xde,0x2d,0xeb,0xaf,
+  0x0f,0xed,0x97,0xb6,0x2f,0x42,0x18,0x73,0xfd,0x3d,0x68,0x88,0xdb,0xbd,0x8f,0x5e,
+  0x51,0xff,0xd5,0x01,0x21,0xab,0xda,0xab,0x9c,0xea,0xbf,0xd0,0xbe,0x97,0xc3,0x36,
+  0x89,0x60,0xd2,0x83,0x04,0x84,0xac,0x46,0x37,0xd9,0xf5,0x5f,0x1d,0x53,0x65,0x62,
+  0x31,0xba,0x2c,0x4f,0x03,0x2a,0x04,0xd3,0xdb,0xbc,0xd3,0xfc,0x1f,0x3c,0x95,0x5d,
+  0xff,0x45,0x61,0x07,0x04,0x39,0x20,0xa8,0xfe,0x2b,0xdf,0x2a,0xbb,0x46,0x44,0x34,
+  0x2b,0x6c,0x35,0xe2,0x6b,0xe8,0x70,0x42,0x56,0xfd,0xd7,0x48,0xcf,0x79,0xef,0xcd,
+  0x6d,0xae,0xe3,0xdd,0x23,0xb1,0x35,0xde,0x85,0x87,0x0b,0x8e,0xbf,0x7c,0x22,0xf6,
+  0xc2,0xbc,0xc6,0x36,0x79,0x73,0xe7,0xb9,0x9e,0xdf,0x53,0xfe,0x2b,0x1b,0xff,0x50,
+  0x7e,0x30,0xd8,0x52,0x80,0xeb,0x13,0x3b,0xaf,0x35,0x58,0x89,0x42,0x03,0x8f,0x50,
+  0xfc,0x87,0xf2,0x83,0x1e,0xab,0xff,0xa1,0x94,0xc1,0x3f,0x49,0x5d,0xe4,0x59,0x45,
+  0xee,0xba,0xe8,0xd3,0x89,0xed,0x13,0xd6,0x01,0xf1,0x4f,0x84,0x77,0x32,0x5d,0xef,
+  0xe1,0x15,0xa0,0x0e,0x84,0x8f,0xa6,0xbf,0x47,0x9e,0x73,0x42,0xac,0x91,0x2a,0x0d,
+  0xc7,0xb2,0xab,0x4e,0xec,0x7c,0x56,0xaf,0x6c,0xe5,0xed,0x0c,0x61,0xf6,0x9c,0xca,
+  0x36,0xbe,0x2c,0x50,0x23,0x9e,0x80,0xbb,0xa9,0x91,0xdd,0x40,0xa6,0xff,0xcf,0xcc,
+  0x2e,0xab,0x8d,0x12,0xff,0x05,0xb5,0x51,0xd2,0xf1,0x1f,0xb6,0x3b,0x6a,0x0c,0x3c,
+  0xd2,0xca,0x87,0x1d,0x35,0xde,0x27,0xe0,0x33,0x54,0x11,0xf6,0x6a,0x56,0xfe,0xcb,
+  0x7a,0xfe,0xad,0xaa,0x05,0x63,0xda,0x9d,0xdf,0x9f,0x81,0x3f,0x5c,0x34,0xd8,0x8e,
+  0xb0,0x76,0x0e,0xbc,0x17,0x0f,0x84,0xb2,0xfa,0x1f,0xf6,0x50,0xfd,0x3b,0x58,0xa0,
+  0xa8,0x9c,0xc2,0x62,0xcb,0x5d,0x0f,0xc9,0xef,0x52,0xdb,0x43,0x2a,0xfb,0x1a,0x31,
+  0x50,0x68,0x77,0x65,0xe3,0x1f,0xea,0xc7,0xb5,0x50,0x71,0x59,0x65,0x2c,0x50,0x0d,
+  0xce,0x57,0x50,0x18,0xd2,0xac,0x78,0xe3,0x2a,0x38,0x55,0x5c,0xad,0xa0,0x60,0x8f,
+  0xff,0x54,0xc0,0x19,0xe1,0x89,0xa9,0xbb,0xd8,0x19,0xfd,0x79,0xe1,0x11,0x0e,0x8a,
+  0xff,0x1c,0x36,0xab,0x9e,0x53,0xa9,0xed,0xcf,0x61,0xb3,0x36,0xa6,0x66,0xd7,0xbf,
+  0x1b,0xe8,0x9d,0xce,0x05,0x55,0x98,0x14,0x38,0xf5,0x42,0x04,0x10,0x5d,0x47,0x79,
+  0x15,0x5c,0x03,0xcb,0x0c,0x06,0xbc,0x9c,0xe2,0xa5,0x87,0xb3,0xf2,0x5f,0x08,0x72,
+  0xd0,0x49,0x71,0x9f,0x82,0x97,0x22,0x7f,0x47,0xdd,0x2a,0x4e,0xb1,0x19,0xa9,0xfc,
+  0x75,0x03,0x7e,0xda,0x5f,0xa6,0xfa,0x2f,0x7b,0xfc,0xe7,0x2a,0xfe,0x1b,0x71,0x43,
+  0x48,0x6d,0x95,0x7f,0x05,0xbf,0xef,0xba,0x31,0xc4,0xef,0x64,0x97,0xe0,0x84,0xb8,
+  0x59,0x57,0xeb,0xe4,0x2f,0xc2,0x20,0x9e,0x72,0xad,0xb0,0xc7,0x7f,0x3e,0x4b,0xfd,
+  0xb8,0xa8,0xbb,0x88,0x34,0x0a,0x1f,0x29,0xb5,0xe4,0x7d,0x24,0xad,0xfc,0x97,0x4a,
+  0x85,0x96,0xef,0x80,0x45,0x74,0xc9,0xf4,0xff,0x81,0x9c,0x09,0x71,0x29,0xda,0xb8,
+  0xd3,0xd5,0xd7,0xfc,0x3c,0x1c,0xa5,0x6c,0xd7,0x0a,0x35,0x00,0x56,0x44,0xe8,0x90,
+  0x1c,0xa0,0x46,0x40,0x31,0x57,0x22,0x2b,0xfe,0xb3,0x05,0x9e,0xf5,0x57,0x1a,0x6a,
+  0x1b,0x2b,0x66,0x6b,0x1e,0x47,0x45,0xd4,0x4e,0x81,0x68,0x65,0x87,0xee,0xb8,0xcf,
+  0x3d,0x0b,0x76,0x6a,0xa5,0x06,0xfa,0x47,0x59,0xf1,0x1f,0x63,0x5f,0x4e,0xe5,0xcb,
+  0xd7,0x9c,0x0d,0x93,0x9a,0x2a,0x33,0x1c,0xe3,0x6c,0x96,0xbe,0x8f,0xcf,0xe9,0xe7,
+  0xf7,0x3a,0x66,0xe9,0x9b,0xac,0xfc,0x57,0x16,0xfe,0x49,0x52,0x1a,0x51,0x7f,0x0c,
+  0x3c,0x86,0x24,0x84,0xfe,0x1c,0xcf,0x65,0x0c,0xe2,0xa2,0xbc,0xc6,0x21,0xf0,0x25,
+  0x63,0x14,0xd8,0xd7,0xb2,0xf0,0x0f,0x2a,0x0d,0x29,0x58,0xea,0x8a,0x34,0x27,0xf1,
+  0x6b,0xea,0x8d,0xdf,0x2e,0x8a,0x3c,0xca,0x84,0x32,0x17,0x81,0xae,0xec,0x81,0x44,
+  0x4b,0xaf,0x8e,0xfa,0x24,0x0b,0xff,0xa0,0x7d,0xb4,0x82,0x60,0xbb,0xac,0xf8,0x98,
+  0xa5,0x78,0x0f,0x48,0xf5,0xa6,0xd5,0x28,0xf2,0xa2,0x7f,0xaa,0x22,0xcc,0x8e,0x7f,
+  0xfe,0x99,0x9c,0x08,0x53,0x1e,0x54,0xd0,0x9b,0x18,0x54,0x87,0xe5,0x06,0x18,0x92,
+  0xaa,0x65,0xbc,0xac,0x01,0x55,0x6f,0x35,0xf5,0xbb,0x33,0x6d,0xf1,0x9f,0x15,0x60,
+  0x15,0x09,0xc6,0xad,0x6c,0x69,0x95,0xae,0xea,0x4c,0x67,0x9d,0xa8,0xd8,0x55,0xe1,
+  0x00,0x77,0x37,0x6c,0x17,0x54,0x7f,0x61,0xef,0xff,0x03,0x3f,0x98,0xba,0x9e,0xd1,
+  0x3f,0xbc,0x3a,0x86,0xaf,0xd9,0x4d,0xb4,0x31,0x42,0xec,0x9d,0x56,0x3f,0xd2,0x5c,
+  0x3b,0xff,0x47,0x31,0x1e,0x22,0x74,0xcd,0x72,0x07,0x95,0x0e,0xdd,0x47,0xde,0x84,
+  0x13,0x37,0x9d,0x8f,0xe3,0xb2,0xfb,0x50,0xad,0x51,0x3f,0x64,0x77,0x56,0xff,0xc3,
+  0x14,0x0d,0xac,0x37,0x3c,0x46,0x85,0x72,0x66,0xc1,0x6e,0xd5,0x47,0x16,0x67,0xd0,
+  0xd5,0xdb,0xe9,0x54,0x7e,0x4d,0x19,0x9f,0x27,0xb2,0xf9,0x3f,0x5d,0x63,0xd0,0x28,
+  0xb9,0x0c,0xfc,0x4c,0x26,0xa8,0x1b,0xdb,0x80,0x44,0x1f,0xce,0x5c,0x22,0x2a,0x8c,
+  0xe3,0xe2,0xfd,0x49,0xfd,0xd7,0xa5,0xcf,0x7d,0x62,0x54,0x8f,0x3b,0x57,0xcb,0xc1,
+  0x92,0x63,0x88,0x96,0x2b,0x0e,0x35,0x07,0xe1,0x98,0x51,0xad,0x5b,0xfc,0xf9,0x63,
+  0x0f,0x2d,0x20,0x21,0x1b,0xff,0xbc,0x40,0x45,0xee,0xf1,0xcd,0x3e,0xbd,0x5b,0xf7,
+  0x1c,0x89,0xf4,0x82,0x33,0xd6,0xbd,0xaa,0x82,0xf1,0x00,0xdb,0xa9,0x77,0x2a,0xb5,
+  0x61,0xde,0xdb,0xd4,0x93,0x3b,0xbd,0x9e,0xde,0x9c,0x21,0x71,0x40,0x0a,0x99,0x3d,
+  0x01,0x87,0x33,0xdc,0xc9,0x89,0xf6,0x43,0x61,0x55,0xa9,0x87,0xd7,0x21,0xb0,0x09,
+  0xaf,0xd3,0xbd,0xbc,0x1e,0xf1,0x4f,0xfa,0xf7,0x42,0xfc,0xa3,0x1c,0x88,0xe8,0x87,
+  0xbc,0x7e,0x2b,0x1e,0xe2,0x31,0x79,0x1d,0xc5,0x8b,0x14,0xf0,0x50,0x47,0x20,0x58,
+  0x2f,0xca,0xb7,0xa3,0x87,0x12,0x4f,0xf3,0xa5,0x41,0xd9,0x05,0xcf,0x8b,0x40,0xb2,
+  0x75,0x7f,0x73,0x15,0x1c,0x11,0x01,0xd3,0x79,0x50,0xb6,0xd6,0x67,0x9b,0xb3,0x0e,
+  0x85,0x97,0xcd,0xfa,0x52,0xdc,0x21,0x70,0xc7,0xf4,0xfd,0xb7,0x69,0x07,0xf9,0x25,
+  0x78,0x29,0x49,0xfc,0xf0,0xf6,0xcb,0x9b,0xa7,0x81,0x10,0x34,0x8a,0xa5,0x17,0x1e,
+  0xbe,0xac,0x51,0x45,0x58,0x3e,0xe2,0x43,0x5b,0xff,0xc3,0x9f,0x48,0xef,0x1b,0xb5,
+  0x09,0x57,0xaf,0xbc,0x52,0x5c,0xd4,0x7b,0xa9,0xbe,0x7b,0x65,0xe4,0x48,0x79,0xf0,
+  0x71,0x67,0x5c,0xf5,0x89,0x23,0x46,0xa0,0xa4,0xa0,0xd7,0x9e,0xff,0x52,0x7c,0x8e,
+  0x4e,0xbf,0xe7,0xa3,0x6b,0x5e,0x64,0xf3,0xe1,0x80,0xe9,0x39,0xf1,0xa3,0x83,0xe1,
+  0x0f,0xf4,0xb7,0x92,0x05,0x71,0xfe,0x1c,0xab,0xec,0x7a,0x43,0xf2,0x8c,0xf3,0x17,
+  0xd9,0x47,0xe9,0x9f,0xd7,0x54,0xf2,0x43,0x3b,0x0c,0xdd,0x5c,0xec,0xf7,0x2c,0x31,
+  0xf6,0x48,0x9e,0x91,0x6b,0xfc,0x94,0xd6,0x01,0x9f,0xb0,0x3a,0xd8,0x74,0x26,0xf4,
+  0x2e,0xdc,0x18,0x67,0xd3,0xf6,0x2e,0xa4,0x05,0x5b,0x37,0x89,0x39,0x63,0xea,0x44,
+  0xee,0xec,0xbc,0x7d,0x91,0xd2,0xe9,0x78,0xc8,0xfc,0x58,0x1e,0xe2,0x01,0xfe,0xbd,
+  0x48,0x59,0xec,0xb3,0xab,0xd9,0x49,0x65,0xfa,0xfa,0x56,0xee,0x34,0x76,0xe8,0xfe,
+  0xa4,0xea,0x97,0x97,0xc0,0x45,0xdd,0x9f,0x50,0x17,0x20,0xec,0x79,0x19,0x1a,0xf4,
+  0x7c,0xdc,0x6f,0x5a,0xbf,0xee,0x07,0x97,0x5f,0xfe,0x75,0xba,0x7f,0x9d,0x31,0x73,
+  0xa3,0xf1,0x47,0xc4,0x33,0xd3,0xcb,0x62,0xaa,0xf1,0xe6,0x31,0x78,0x09,0x6e,0x86,
+  0xdc,0x71,0x79,0xcc,0xf8,0x04,0x1a,0xbb,0x0a,0xc6,0x6d,0xfd,0x0f,0x39,0xe1,0x1f,
+  0xa9,0xa6,0x1f,0x41,0x78,0x01,0x0a,0x81,0xfe,0x7c,0x2b,0x5e,0x2d,0xea,0x05,0x65,
+  0x0c,0xd9,0x11,0x70,0xc7,0xf2,0xfb,0x64,0x96,0xd6,0x0f,0xa3,0xd2,0x41,0xe8,0x24,
+  0xa7,0x09,0xd5,0x88,0x85,0x7f,0x0c,0xa2,0x35,0xec,0xd3,0xcb,0x4c,0x2f,0x09,0x3f,
+  0x93,0xe6,0x89,0xd6,0x71,0xd6,0x9b,0x3b,0x7d,0x3d,0xb4,0xff,0x48,0x59,0x2b,0xae,
+  0xa7,0xfe,0x87,0xb3,0xd9,0x5a,0x51,0xf6,0x0e,0xac,0x86,0x37,0x61,0xcf,0x96,0xbf,
+  0xa1,0xf7,0xbd,0x64,0x51,0xc1,0x3f,0xbb,0x3a,0xd3,0xde,0x8f,0xf8,0x3f,0xd0,0xa9,
+  0xa3,0x3f,0x42,0xdd,0xed,0xd6,0x09,0x3d,0x84,0xab,0xfd,0x2e,0xe2,0xbd,0x7b,0x9e,
+  0xcb,0xdb,0xea,0x39,0x0a,0x3b,0xc2,0xde,0x28,0xe2,0x9f,0x1f,0x64,0x9e,0x47,0x89,
+  0xb0,0xa3,0x7c,0x5f,0x8c,0xc7,0xc2,0x5e,0x38,0x1c,0xeb,0xed,0x70,0x8e,0xc9,0x67,
+  0xc4,0x05,0xf8,0xb6,0xc8,0x7f,0x1a,0x85,0x57,0x63,0xd5,0x54,0x1a,0x56,0x97,0xb6,
+  0x5f,0xad,0x5a,0x4c,0x19,0x07,0x2a,0xf2,0x52,0xad,0xb2,0x53,0xa8,0x4a,0xb5,0xfd,
+  0xa1,0xfe,0xcf,0x24,0x18,0x2f,0xba,0x2d,0xfc,0x93,0x5e,0x1f,0x6d,0x97,0x7e,0x08,
+  0x6a,0xc9,0xac,0x5b,0xf1,0x9f,0x45,0x1b,0xa2,0x33,0x88,0x08,0x14,0x5c,0x64,0x55,
+  0xc4,0x7f,0xb6,0xc3,0xb2,0x8f,0x03,0x19,0xbe,0xb7,0x52,0xce,0x28,0xff,0xb2,0x22,
+  0xd5,0x76,0xd8,0x63,0x11,0x81,0x60,0x5d,0xb4,0x0a,0xf1,0x8f,0x67,0x0e,0xac,0x33,
+  0x9f,0x5b,0xa5,0x6e,0xcd,0x8a,0xff,0xf8,0x10,0xe4,0xdc,0x83,0xa0,0xc5,0x2a,0xfb,
+  0x42,0x3c,0x13,0x9f,0xa2,0xe9,0x22,0x5e,0x52,0xe0,0x19,0x6d,0x6e,0x8b,0xba,0x19,
+  0x77,0xd4,0xf4,0x1f,0x87,0x72,0xb0,0x48,0x3e,0x1a,0xd1,0x80,0x59,0x8c,0xf0,0x12,
+  0xc2,0x1e,0xaf,0x8f,0x88,0x43,0x4e,0xf6,0x14,0x94,0x53,0x3f,0xe4,0xc3,0xe9,0xfa,
+  0x0b,0x62,0x7e,0x27,0xf4,0x00,0x2c,0x11,0x33,0x42,0xf8,0xe2,0x84,0x7f,0x50,0x1f,
+  0x26,0x4a,0xa9,0xff,0xb0,0xaa,0xc3,0x19,0xb2,0x50,0x42,0x7e,0x33,0xbd,0x7f,0xfa,
+  0x66,0x8e,0xc5,0x2f,0x7b,0x0f,0x10,0xc9,0xe7,0x5c,0xec,0x13,0x04,0x42,0x05,0xc7,
+  0xbb,0xcf,0xc5,0xa6,0x19,0xd1,0x7b,0xff,0x6b,0xc5,0xcd,0x04,0x84,0xde,0x4d,0xaf,
+  0x67,0x9d,0x55,0xff,0x5e,0xd1,0xe2,0xa4,0xec,0xcf,0x59,0x2d,0xb8,0xa8,0x40,0x2b,
+  0x6a,0x31,0xce,0xeb,0x7e,0xa2,0xfd,0x94,0xa7,0xea,0xdf,0xed,0xfd,0x9f,0x4b,0x78,
+  0x52,0x8f,0x70,0x0f,0xb4,0x86,0xc3,0xd4,0x86,0xb1,0x4a,0xe6,0x84,0x7f,0xea,0xbc,
+  0x1e,0xca,0x73,0xea,0xfe,0x30,0x9e,0x72,0x20,0xfe,0x49,0xeb,0x9f,0x56,0x28,0x16,
+  0xcf,0x6a,0x9f,0x59,0xc4,0x97,0x79,0x4e,0xc4,0x08,0xff,0x38,0x08,0xff,0x3c,0xeb,
+  0x2f,0x45,0xfc,0x43,0xf5,0xef,0xac,0xd4,0x28,0x59,0xc6,0x8e,0xa7,0xf7,0x43,0x89,
+  0xd2,0x05,0x3f,0x2c,0x2c,0x6b,0xed,0x19,0x86,0x73,0xf0,0x42,0x79,0xe5,0x22,0xfe,
+  0x39,0x47,0x8d,0x78,0x01,0x4a,0xef,0xf0,0x0e,0xb3,0x5a,0x58,0x53,0x58,0xda,0xe4,
+  0x18,0xc6,0x1d,0x35,0x7d,0x7d,0x4c,0x79,0x02,0x7f,0xd6,0x3e,0x43,0x99,0xca,0x5e,
+  0x2d,0x2f,0xd8,0xba,0x83,0xf0,0xad,0x3b,0xe4,0xdc,0xaa,0x22,0x10,0x32,0x7a,0x57,
+  0x39,0xa3,0xd7,0x8f,0xa6,0xfb,0x1f,0x9e,0xd1,0x76,0xc2,0x7b,0xd4,0xe4,0xf9,0xd1,
+  0xb2,0x11,0x71,0x9e,0x05,0x17,0xa5,0xda,0x3e,0x53,0xfe,0x6b,0x4b,0xea,0x0e,0xab,
+  0x70,0x3f,0x7c,0x94,0xc5,0xff,0x99,0x6c,0xaf,0x56,0x36,0xf4,0x37,0xa3,0x1a,0xcf,
+  0xdb,0x03,0x4b,0x5f,0x41,0x6d,0x3c,0x04,0x0b,0x4b,0x9c,0xfd,0x54,0x08,0x0f,0xd5,
+  0x85,0x4e,0x53,0x1e,0x48,0xd7,0x7f,0x81,0xe2,0xd5,0x0e,0x9b,0x9e,0x38,0xdf,0xc5,
+  0x46,0xf5,0xe7,0x07,0x3d,0x51,0x04,0x42,0x5e,0x58,0x6f,0x78,0xe2,0xf9,0x24,0x9c,
+  0x91,0x3c,0x82,0x27,0x9b,0x12,0x99,0xfd,0xb9,0xc6,0x80,0x9e,0x44,0x0c,0x95,0xf2,
+  0xe6,0x01,0x88,0x0f,0xeb,0x6e,0xd5,0xb9,0x1e,0x20,0xd2,0xea,0x03,0xbe,0x01,0x17,
+  0x36,0x06,0xba,0x34,0x8f,0xf0,0xcf,0xf4,0xfd,0x4b,0xa5,0x06,0xcb,0x7f,0xa9,0xa0,
+  0xaf,0xf5,0x25,0x02,0x42,0xe3,0x2c,0x88,0xfa,0xea,0x33,0xc3,0x94,0x21,0x82,0x27,
+  0x61,0x9b,0x99,0xb7,0xaa,0xc9,0x6c,0x99,0x7e,0x1c,0x6f,0x89,0x1b,0x46,0x44,0xb5,
+  0x5e,0x40,0xf8,0x67,0xaf,0x58,0xa0,0x77,0xb7,0x4a,0x6e,0xf6,0x2a,0xe2,0x9f,0x25,
+  0xad,0xea,0x55,0xca,0x6f,0xc5,0xee,0x64,0xfe,0x0a,0x79,0xc0,0x93,0xde,0x9f,0x79,
+  0x1b,0xac,0xfe,0xcf,0xf9,0x54,0xed,0x8e,0x8e,0x6d,0xff,0xa6,0x54,0x1b,0xb1,0xda,
+  0x54,0xfd,0xfb,0x28,0xf8,0x20,0x37,0x6a,0x7b,0xdf,0x50,0x7e,0xdc,0xf8,0x5d,0xd7,
+  0x8d,0x23,0xce,0x09,0xf9,0x02,0xc2,0x9e,0xc6,0x90,0x73,0xa2,0xa8,0x17,0x5e,0xa3,
+  0xb2,0x9d,0x09,0x5c,0xc6,0xc4,0x66,0xb4,0x5f,0x09,0x79,0x38,0xfd,0xfc,0x3d,0xd2,
+  0x8b,0x62,0x10,0x62,0xe5,0xad,0xa9,0x6c,0xfb,0x4d,0x5d,0xbc,0x95,0x35,0xb0,0x07,
+  0xa8,0xcc,0xdf,0x20,0x47,0xac,0xe7,0x86,0xc3,0x14,0xff,0xf9,0x7e,0xfa,0x7b,0x84,
+  0xe8,0xa2,0x7d,0x30,0x9f,0xea,0x55,0x27,0xf5,0x27,0x79,0xa5,0x81,0x8a,0x2b,0xaa,
+  0xaf,0xd5,0x08,0xef,0x85,0xcf,0xc1,0x26,0x7f,0x99,0x59,0xb2,0x82,0x65,0xf8,0xc6,
+  0x46,0xf1,0x90,0xc0,0x6f,0x78,0x0e,0x17,0x6c,0x00,0xff,0xb1,0x57,0xf0,0x0d,0xe8,
+  0xd8,0x46,0x24,0x1f,0x53,0xb9,0x3b,0x41,0x9f,0xb7,0x86,0x1f,0xe6,0xc9,0x4c,0x7d,
+  0x5f,0xce,0x2e,0x4a,0xea,0x81,0x2f,0x82,0xda,0xa3,0x47,0x14,0x84,0x7d,0x1b,0xe4,
+  0x9f,0x5a,0x15,0x07,0x9b,0x22,0xf8,0xbe,0x89,0x68,0x40,0xb1,0xf2,0x9b,0xd3,0xbf,
+  0x57,0x4c,0x4b,0x2a,0xef,0x93,0x7e,0xde,0x2d,0x8f,0x29,0xef,0x33,0xdc,0x48,0xbb,
+  0x3b,0x4f,0x13,0x10,0xa2,0xf5,0x79,0x57,0xbb,0xa8,0x58,0xa5,0x61,0x76,0xfe,0xf3,
+  0x24,0x0c,0x4a,0x7f,0x0f,0xf9,0x66,0x5e,0x0d,0x0c,0xe5,0x36,0x0a,0x97,0xc9,0xee,
+  0x37,0x2e,0xa1,0x46,0x9c,0x61,0xca,0x97,0x8c,0xcb,0x52,0xb5,0xe9,0x4a,0xaa,0x3c,
+  0xdd,0xff,0xa7,0x5f,0xf9,0xd2,0x3d,0x8f,0x81,0xd5,0x64,0xc6,0xab,0x74,0x2b,0x55,
+  0xcb,0xd5,0xb8,0x7c,0x0f,0xd5,0x9f,0x9a,0x8b,0x89,0xc6,0x4c,0x15,0xf1,0x88,0x58,
+  0xea,0x8c,0xe9,0xdf,0x4b,0xe4,0x50,0x98,0xeb,0x1e,0x13,0xd5,0x4e,0x84,0x1a,0xd7,
+  0xf4,0xab,0x71,0xcf,0x2e,0x52,0x5c,0xa6,0x85,0xa0,0xe2,0x92,0x47,0x52,0xb3,0xf8,
+  0x3f,0xf8,0x4f,0xa2,0xf0,0xb6,0x86,0x9f,0x6b,0x17,0xee,0x2e,0x5c,0x76,0x21,0x4c,
+  0xe8,0xc5,0xe7,0x5d,0x0c,0xee,0x41,0x6d,0x0f,0xa7,0xd2,0x39,0x37,0xcb,0x81,0xf4,
+  0xdf,0x4a,0xfe,0x32,0xdb,0x7e,0x32,0x9f,0xac,0x09,0xd1,0x9c,0x36,0x59,0xc0,0xcf,
+  0x6a,0xab,0x42,0x8d,0x80,0x74,0xf7,0x15,0xfc,0x9f,0x99,0x49,0x63,0x8c,0xfa,0xf3,
+  0x13,0x24,0x3a,0x05,0xdf,0xa5,0x7c,0xf1,0x2a,0xaa,0x7f,0x77,0xe0,0x91,0x61,0xe5,
+  0xdc,0x14,0xfe,0xb1,0xd5,0x7f,0x5d,0x82,0x4f,0xbc,0xd5,0xaf,0xe4,0x9f,0x97,0xef,
+  0x87,0x21,0xbe,0x60,0xe4,0xf6,0xb3,0xf2,0x65,0xb8,0xac,0xd7,0x27,0x9d,0x3b,0xf0,
+  0xc8,0xcf,0xa1,0xec,0x35,0x34,0x85,0xfe,0x0c,0xff,0xbc,0xe4,0x43,0x65,0x7f,0x8b,
+  0x27,0xa1,0x06,0xd0,0xfa,0x70,0x02,0x42,0x7f,0x60,0x3e,0xf1,0x92,0xe9,0xb9,0xdb,
+  0xf1,0x63,0xb4,0xf8,0xdd,0xf7,0x7a,0x86,0xd5,0x89,0xec,0xf8,0x4f,0x21,0xba,0x15,
+  0x09,0x34,0xe2,0x43,0x6c,0x3d,0x0f,0x25,0x1c,0xb5,0x6c,0x89,0xd8,0xa3,0x79,0xcd,
+  0xf5,0xb9,0xec,0x36,0xe8,0xf4,0xea,0xaf,0xe1,0x29,0x96,0xa9,0xff,0xca,0xd9,0xc5,
+  0xf7,0x8b,0x8a,0x41,0x8b,0x46,0xc5,0x85,0xf5,0x43,0x50,0x22,0xcc,0x93,0x74,0xc4,
+  0xd8,0x2e,0xd6,0xad,0x50,0x3f,0x49,0x96,0xc1,0x63,0x14,0xff,0x39,0x6f,0xf6,0x9a,
+  0xb7,0xc5,0xe5,0x95,0x4a,0x22,0xb1,0x79,0x24,0x85,0x87,0xa1,0x3e,0x99,0x1b,0x6b,
+  0x6e,0x51,0x16,0x43,0xaf,0xf9,0x67,0x71,0x15,0x16,0x4d,0xff,0xbe,0x31,0x89,0xc6,
+  0x5e,0x7c,0xaa,0x7f,0xc6,0x38,0xde,0xff,0x13,0x86,0x9f,0xc9,0xaa,0xa2,0x49,0xf8,
+  0x18,0xf1,0xcf,0xcf,0x92,0xf8,0xbe,0x97,0xc1,0x1a,0xf4,0x60,0xc7,0x3f,0xbb,0x60,
+  0x62,0x95,0xb5,0xbb,0x9c,0xd2,0xfb,0xc2,0xca,0x36,0xa2,0xc5,0xcf,0x0d,0xbc,0xed,
+  0xdc,0x29,0xfb,0x94,0x23,0xbc,0xd7,0x74,0xfa,0xd5,0xe9,0xb7,0xa5,0xf8,0x8f,0x8f,
+  0xd8,0x1a,0xa6,0x1c,0xc7,0xcf,0xaa,0x53,0x6c,0x37,0x9d,0xf4,0x1f,0x7a,0x6b,0x9b,
+  0x9e,0xcc,0x8f,0xe1,0x8b,0xfc,0x93,0x59,0x36,0x8a,0x5f,0x50,0x20,0x7d,0xbd,0xa9,
+  0x2c,0x81,0xfd,0xa6,0x0f,0x64,0x42,0x3b,0x02,0x56,0x9a,0x0e,0x7f,0xd3,0x10,0x74,
+  0x0a,0xef,0x2f,0x9e,0x8e,0xb3,0x02,0x7d,0x87,0x11,0x4a,0x22,0xde,0xab,0x53,0xd2,
+  0xf1,0x1f,0xed,0x8b,0xf0,0x6c,0x8a,0xfd,0x3b,0x1b,0x36,0x46,0x29,0x30,0x02,0x84,
+  0x7f,0xf2,0x42,0xea,0x19,0xc7,0x6c,0x7d,0x5f,0x47,0x69,0x32,0xbb,0xfe,0x9d,0x2f,
+  0x31,0xe2,0x46,0xc3,0xb0,0x7a,0xa3,0xec,0x34,0xc2,0xd0,0xd0,0xef,0xf0,0x4b,0x63,
+  0xc6,0xcb,0x50,0x97,0x74,0x5c,0x2d,0x3b,0xb5,0x1d,0xdc,0x3f,0x58,0xe0,0xb7,0xe7,
+  0xbf,0x72,0x52,0x63,0x41,0xfe,0x7a,0x7c,0xf1,0x27,0xca,0x3f,0x41,0x35,0x3e,0x3f,
+  0x15,0x82,0x69,0xcf,0x9a,0x1b,0xfd,0x65,0xa7,0xe0,0x2d,0x3c,0x95,0x17,0xb7,0xf5,
+  0xff,0x21,0xfc,0x83,0x68,0x87,0xf4,0xd5,0x07,0xca,0x04,0x6e,0x4b,0xc7,0xf3,0xdd,
+  0x3e,0xe5,0xe2,0xf6,0x7a,0x03,0x7f,0x91,0xf2,0xd4,0x46,0x7d,0xce,0x5e,0xff,0xf5,
+  0xe9,0xc7,0x61,0x8f,0x62,0xc5,0x7f,0xee,0x12,0xbb,0xa7,0x12,0x61,0xf0,0x4e,0x61,
+  0x29,0x38,0x49,0xd8,0x77,0x77,0xe9,0xf0,0xe2,0x7b,0xc3,0xbd,0x99,0x7e,0xf2,0xc4,
+  0xff,0x11,0x5e,0x7c,0x4d,0xcf,0x9b,0xe6,0x73,0x0f,0xcc,0x49,0x3a,0x6e,0x74,0x7f,
+  0x11,0xf6,0xc5,0x69,0xfe,0x05,0xbb,0x4e,0x7a,0x38,0x36,0xe7,0xf4,0x35,0x75,0xb6,
+  0xfe,0x1b,0x2b,0x94,0x21,0xd8,0x53,0xa2,0x7f,0x54,0x11,0x67,0x4b,0xe0,0xc0,0x40,
+  0x79,0xc8,0x4a,0x84,0xed,0x00,0xdf,0xbb,0x79,0x0d,0xe1,0x02,0xfc,0xec,0x7f,0x4c,
+  0xf5,0x2c,0x9b,0x33,0xf3,0x32,0x66,0x8e,0xc2,0x25,0xf3,0xa6,0x54,0xfc,0xe7,0xd2,
+  0x70,0x2d,0xf5,0x7f,0x5e,0x01,0x17,0x58,0x63,0x2c,0xff,0xdd,0x66,0xaf,0x72,0x41,
+  0x22,0x0f,0x94,0xd9,0xea,0xbf,0x24,0x1d,0x41,0x4e,0x83,0xc2,0x45,0x73,0x52,0x9b,
+  0xd0,0xea,0x15,0x8b,0xf6,0x3c,0x01,0x6e,0xad,0x20,0x85,0x88,0xea,0xaf,0x8c,0xff,
+  0x90,0x35,0xac,0x32,0x72,0x2c,0x7f,0x1f,0xee,0xb5,0xf2,0x23,0x0a,0xf1,0x61,0x9c,
+  0xda,0x8c,0xeb,0xe1,0x5b,0xf0,0xa7,0xfd,0x9f,0x39,0xb1,0x7d,0xa8,0xed,0xb0,0xb4,
+  0xdf,0xaa,0x0e,0xa3,0xfe,0xcf,0x8a,0x6f,0xc9,0xa6,0x68,0xf3,0xbb,0xb0,0xdf,0xea,
+  0x48,0x2c,0x67,0xfa,0x3f,0xd3,0xfc,0x0b,0xea,0xd7,0x77,0x4d,0x6a,0x5e,0x83,0x4e,
+  0x89,0x9b,0x9d,0x39,0xfb,0xf5,0xaf,0x19,0xab,0xe3,0xee,0xf2,0x39,0xbb,0xe7,0xbd,
+  0x1d,0x2a,0x89,0xba,0x73,0xd3,0xf5,0xa7,0xde,0x62,0x84,0x3d,0x5e,0x5f,0x9b,0x83,
+  0xe2,0x3f,0xbb,0xbd,0x2b,0x8c,0x3c,0x77,0x78,0x10,0x8f,0x54,0x19,0x9f,0x76,0x0f,
+  0x74,0x6d,0xdb,0xed,0x0d,0x51,0x20,0x28,0xbb,0xff,0xe1,0x85,0xd2,0x20,0x5f,0x8a,
+  0x68,0x47,0xd4,0x79,0x3c,0x90,0x1f,0x96,0xf0,0x7d,0xf5,0x2a,0xc9,0xcb,0xdc,0xba,
+  0x98,0xf0,0x04,0xb8,0x33,0x2c,0xcd,0xce,0xc4,0x7f,0x0a,0x47,0x80,0xd8,0xce,0xf9,
+  0x9b,0x3b,0x47,0xb4,0xcb,0x54,0xff,0xb5,0xf9,0x9d,0x91,0xd8,0x79,0xe5,0xe6,0x7e,
+  0xd7,0xf1,0x97,0xcf,0xc1,0x7e,0xaf,0xd5,0x1a,0xfa,0x2b,0x72,0x26,0xdf,0x44,0x4d,
+  0x11,0xeb,0x6f,0xb1,0xe2,0x3f,0xaf,0x69,0x56,0xa0,0x6c,0xb9,0xf1,0x89,0x8e,0x1e,
+  0xeb,0xc3,0x72,0x8d,0xf6,0x89,0x52,0x4d,0xf5,0xef,0x59,0xfd,0x7f,0xa0,0x8f,0x48,
+  0x3e,0x6c,0xbd,0x0e,0xde,0xd2,0x00,0x53,0x09,0xff,0x50,0xfd,0x97,0x43,0x96,0xee,
+  0x86,0x3e,0xc9,0xa3,0xa0,0xbe,0x2d,0x48,0xaf,0x4f,0x2b,0x1a,0xb9,0xdd,0x85,0x5e,
+  0xa3,0xcd,0xed,0x6e,0xe1,0x85,0xba,0xde,0xba,0xb8,0xf0,0xea,0x16,0x65,0xb7,0xe6,
+  0x33,0x3a,0xdd,0x4c,0x69,0xdf,0xad,0x85,0xa8,0xfe,0x7d,0x99,0x34,0xfd,0xfc,0x25,
+  0xc5,0x3b,0x95,0xdd,0xd4,0x0d,0x49,0x63,0xcb,0xb5,0x79,0xf0,0x40,0xab,0x9a,0x5a,
+  0xd8,0x02,0x93,0x47,0xef,0x59,0x6e,0xec,0x07,0x46,0x85,0xf0,0x73,0xb3,0xe2,0x3f,
+  0xe7,0x79,0xfd,0xea,0x02,0xc2,0xb7,0x53,0xf9,0x2f,0x02,0xa2,0xc1,0xe5,0x9b,0x1e,
+  0xea,0x2c,0x87,0xb3,0xd2,0x66,0x63,0x69,0xd4,0xd6,0xff,0x39,0x61,0xc5,0x7f,0x6a,
+  0x69,0x28,0x46,0x17,0x3f,0xaf,0xd7,0x87,0x5c,0xe9,0xb6,0x3f,0x25,0xd4,0x11,0x31,
+  0x8f,0x12,0x61,0x6a,0xd6,0xfc,0x0b,0x8a,0x0f,0x68,0x34,0xed,0xc2,0xea,0xbf,0xe4,
+  0x04,0xb4,0x6e,0xa3,0x50,0x4b,0x13,0x58,0x62,0x61,0xea,0x90,0xe3,0x04,0x29,0x53,
+  0xff,0xee,0xcd,0xf1,0xf2,0x17,0x9b,0xaa,0x44,0x24,0xe6,0x41,0xd8,0x03,0x6f,0x0b,
+  0x4e,0xb4,0xe7,0xe7,0x59,0xe9,0x76,0x15,0x61,0x3c,0x1c,0x35,0xaa,0x3a,0xac,0xfa,
+  0xf7,0xf4,0x7e,0x40,0xfb,0xb5,0x63,0x15,0x75,0x87,0xf0,0x38,0x9d,0xdd,0x6e,0xab,
+  0x4d,0xd6,0x90,0xb4,0x43,0xf8,0xe8,0x33,0x79,0x0d,0x3a,0x4f,0x58,0xa3,0x0a,0x0e,
+  0x4f,0x6f,0x07,0x10,0x85,0x56,0xb7,0x9f,0x84,0xf7,0x5e,0xea,0x07,0xa8,0xcc,0x1b,
+  0x6d,0x25,0x20,0xf4,0x6c,0x64,0x9e,0xa9,0xde,0x9b,0xeb,0x52,0x72,0x52,0x8d,0x80,
+  0x12,0xd3,0xb7,0x87,0x08,0x9f,0x0d,0xbf,0xed,0x68,0x1c,0x73,0xa6,0xda,0x3e,0x7f,
+  0x66,0x92,0xdf,0x27,0xbf,0x29,0x4e,0x8b,0x9b,0x43,0xae,0x7f,0x90,0xdf,0x84,0x57,
+  0xa9,0x3e,0x6b,0xb5,0x7c,0xb8,0x76,0xfa,0x7a,0x8e,0xfe,0xef,0x45,0x98,0x3d,0xe8,
+  0xda,0xd7,0x3d,0x96,0xfb,0x4b,0xa8,0x1d,0x9e,0xbf,0x97,0x65,0xe1,0x9f,0x2a,0xe3,
+  0x33,0xf1,0xe6,0x81,0x07,0xa6,0xdf,0x17,0xfd,0x5f,0xe3,0x72,0x34,0xc5,0xff,0xd1,
+  0x8e,0xc5,0x50,0x9f,0x1f,0xdc,0xf1,0xa2,0xfe,0x49,0x8a,0x11,0x74,0x49,0x43,0x44,
+  0x94,0x54,0x27,0xca,0x6c,0xf5,0xef,0x25,0x3f,0x12,0xcf,0x19,0xa5,0x94,0xbf,0x98,
+  0x05,0x6b,0x88,0xb6,0x7d,0x1f,0x0a,0xcf,0x22,0x6c,0xcb,0xbf,0x77,0xd9,0x29,0xef,
+  0x5e,0x02,0x36,0xdf,0x66,0x15,0x99,0xf9,0x17,0xf0,0xf8,0xa2,0xdd,0x92,0xa5,0xaf,
+  0x9c,0xb0,0x56,0xaf,0x1c,0x50,0xef,0x65,0x8f,0xd3,0x04,0x9f,0x96,0xbc,0x55,0xc6,
+  0x09,0xe3,0x59,0x0a,0x7c,0x55,0x7b,0x74,0xdb,0xfc,0x8b,0x0d,0xca,0x1e,0xd0,0xcf,
+  0x95,0x90,0x3e,0xef,0x28,0xf1,0x25,0x55,0xca,0x5f,0xec,0xa6,0x0f,0xb3,0x3e,0x37,
+  0x81,0x60,0xd6,0x47,0xf1,0x8d,0x92,0x2c,0xfe,0xcf,0x45,0x63,0xcf,0x88,0x73,0x9c,
+  0xc2,0x1a,0x03,0x8d,0xfd,0xd4,0xb8,0x18,0xaf,0xf7,0x8f,0xe7,0x8d,0xa7,0x1b,0x1f,
+  0x7d,0xc6,0x91,0x33,0xfd,0x3c,0x02,0xc6,0x38,0x1d,0x9c,0x1f,0x97,0x87,0xd8,0xc5,
+  0x54,0x36,0x70,0x4c,0x3a,0x2f,0x7d,0x67,0xc2,0xb5,0x9b,0x1a,0x05,0x4c,0xf7,0xff,
+  0x99,0xbe,0xbe,0x14,0xf1,0xcf,0x65,0x6f,0xb5,0x79,0x3b,0xdd,0xf6,0x58,0x6a,0xda,
+  0xc5,0xfd,0x70,0xbe,0xab,0xda,0x58,0x32,0x3e,0xe3,0x2d,0x38,0x0a,0xdf,0x45,0x0b,
+  0x28,0x43,0x1a,0xaf,0x6e,0x53,0x56,0x3a,0xf7,0x58,0xb4,0x5b,0x5c,0xf6,0xce,0xe8,
+  0xd3,0x29,0xda,0xcf,0x7e,0xa8,0x88,0x3b,0xe2,0xcd,0x1f,0x6a,0x11,0x1a,0x74,0x85,
+  0xf6,0x77,0xfa,0x73,0xb1,0xf8,0x3f,0x07,0x14,0x0b,0xed,0x8c,0xb1,0x14,0x4d,0xa8,
+  0x69,0xa5,0xb4,0x5f,0xf7,0x24,0xff,0x32,0xee,0xfe,0x00,0x0e,0x98,0x55,0x83,0x08,
+  0x9c,0xf4,0xf4,0xf7,0xc5,0x8b,0x9d,0xe2,0x80,0xa4,0x13,0xc9,0x79,0x48,0xe9,0xb6,
+  0x1a,0x05,0xb8,0x69,0x7d,0x2a,0x4c,0xc7,0x02,0xd6,0xc5,0xa2,0xe0,0xc4,0x23,0xeb,
+  0xb3,0xf9,0xcf,0x17,0x61,0x81,0x59,0x30,0xde,0x4c,0xd5,0xd6,0x65,0xd4,0xb8,0x78,
+  0x25,0x39,0x92,0x83,0x05,0xe3,0x88,0xc7,0xde,0x80,0x2a,0x8a,0x48,0x40,0x26,0x3e,
+  0x39,0x73,0x32,0x45,0x52,0xfd,0x88,0xfc,0x77,0xa9,0xd1,0x5c,0x7a,0x96,0xf8,0x2d,
+  0x70,0x73,0x87,0xeb,0xa3,0xe6,0x71,0x65,0xcc,0xf2,0xe8,0xbf,0x94,0xc1,0x3f,0x40,
+  0x38,0xcc,0xaa,0x83,0xd5,0xfe,0x15,0x01,0xec,0x7f,0x0a,0xe0,0xd3,0x19,0xa0,0xfd,
+  0x6b,0x82,0xfd,0x8f,0x38,0xad,0xdc,0x40,0x0f,0xf1,0x5f,0x11,0xfe,0x77,0xee,0x3f,
+  0x35,0xe5,0xe0,0x5f,0x15,0x6c,0x7f,0xff,0xfa,0x85,0x29,0xe1,0x7f,0xe7,0xfe,0xff,
+  0xde,0xbf,0xff,0x60,0xeb,0xaf,0xd1,0x2c,0xbf,0x21,0xf8,0x7b,0x98,0x65,0xfe,0x2b,
+  0x82,0xf2,0x7f,0xfb,0xfe,0xff,0x0f,0xaf,0xbf,0xa2,0x89,0x7f,0xc3,0x9a,0x4b,0x69,
+  0x7d,0xf5,0xef,0xfd,0x6b,0x68,0xf8,0xb7,0x5c,0xe5,0x72,0xfd,0xdf,0xbc,0xfd,0xff,
+  0x07,0xfe,0x1a,0x2f,0x5f,0xbe,0x6c,0xfe,0x2f,0x84,0xff,0x37,0x5f,0xff,0x1f,0xec,
+  0x7b,0xfc,0x4f,0x7d,0xf8,0x9f,0xfa,0xf0,0x7f,0x63,0xfd,0xff,0x53,0x1f,0xfe,0xaf,
+  0xfe,0xfe,0xa3,0xe9,0x9f,0xff,0x58,0xd7,0x9b,0x33,0x27,0xe1,0x77,0x8a,0x15,0x06,
+  0x69,0x30,0xd2,0xf8,0xf9,0x18,0x31,0x8e,0x56,0xc9,0x0d,0xda,0x11,0x8a,0x90,0x98,
+  0xf6,0xfc,0x60,0xc9,0x87,0xd0,0x2d,0x3c,0x49,0xde,0xc7,0xca,0xc5,0x3a,0x4a,0xc4,
+  0x47,0xd8,0xdb,0x0c,0x61,0x73,0xb3,0x23,0xe2,0xf0,0xc0,0xba,0x70,0xad,0xee,0x10,
+  0x56,0xa3,0xd5,0xd4,0x1f,0x87,0x5d,0xf8,0x4d,0x87,0x24,0x9e,0xca,0xf7,0xe9,0xb0,
+  0x58,0x67,0x86,0x26,0x14,0xa7,0x98,0xda,0xd0,0xbb,0x24,0x14,0x1c,0xd2,0xf4,0xf5,
+  0x66,0xce,0x18,0xac,0xe3,0x1e,0xe0,0xbb,0xa9,0x1b,0x4c,0xc9,0x76,0x1a,0xfb,0x98,
+  0x0c,0x45,0x8a,0x7d,0x26,0xa3,0x30,0xe3,0x3a,0xc3,0xaa,0x37,0xec,0x4b,0xe3,0x5b,
+  0x09,0xb6,0xc3,0xfb,0x46,0x6f,0xd2,0x77,0x50,0xad,0x60,0x87,0xcd,0x40,0xcf,0xe2,
+  0x70,0xd9,0x97,0x20,0x91,0x08,0x6a,0xce,0xc7,0xcb,0xe6,0x8b,0xc3,0x50,0x57,0xbc,
+  0x61,0x83,0x8d,0xff,0xb6,0x4d,0xdb,0xdc,0xfa,0x47,0x08,0x8e,0xb8,0x56,0x49,0x03,
+  0x30,0xd1,0xd1,0xb8,0xd3,0x35,0x24,0x5b,0x42,0xab,0xeb,0xf5,0xea,0x37,0xc5,0xe5,
+  0x27,0xbe,0x0b,0x78,0xc4,0x1e,0x1f,0xdb,0x29,0x1d,0x31,0xfc,0x4b,0x9c,0xbb,0x67,
+  0xf8,0xd8,0xe1,0xf6,0x5e,0xd8,0xb8,0x5d,0xbe,0xbb,0x29,0x61,0xf4,0x8a,0x25,0x6e,
+  0x75,0xbe,0x38,0x73,0x67,0xb0,0xb8,0xaa,0x2b,0xab,0x3f,0x64,0x79,0x5e,0xf7,0x71,
+  0x8f,0xc1,0xfb,0x66,0x2c,0x07,0x21,0x3c,0xdc,0xb7,0x8b,0xf8,0x1b,0x91,0x6f,0x26,
+  0xf9,0x16,0x47,0x25,0x74,0x8a,0x82,0x1a,0x2e,0xb2,0xf9,0x51,0x3c,0xcc,0xca,0x93,
+  0xad,0x9c,0x6d,0xc0,0xb3,0x7a,0x92,0x97,0xb8,0x6f,0x57,0x68,0xa1,0x2a,0xca,0x3d,
+  0xa0,0x08,0xf0,0x11,0x9f,0xd0,0xce,0x0f,0x2f,0x58,0x14,0x16,0x73,0x46,0x79,0x2b,
+  0x23,0xe2,0x90,0xfe,0x41,0xc9,0x5f,0xb2,0xd9,0x5d,0x6b,0x69,0x50,0xc8,0xdf,0x39,
+  0x18,0xac,0x89,0x39,0x89,0x2f,0x94,0x35,0x1f,0xcd,0x10,0x7c,0x6f,0xcf,0x92,0x62,
+  0xc7,0x06,0x78,0x59,0xf7,0x0f,0x29,0x37,0xca,0xb7,0x8b,0x97,0x35,0xfd,0xe9,0xdb,
+  0x3d,0x2a,0x63,0x66,0xac,0xe1,0x64,0xc1,0x5e,0xfb,0x7c,0xb4,0x6b,0x77,0x2d,0x9b,
+  0xd4,0x6e,0x12,0xf3,0xdb,0xad,0x68,0x61,0xe3,0x10,0x2e,0x14,0x35,0xd6,0xb8,0x79,
+  0x30,0xef,0x6d,0x36,0x0e,0x9f,0x10,0x75,0x6a,0xc2,0x96,0x1f,0xf4,0xfe,0x79,0x0f,
+  0xa7,0x26,0xd8,0x4e,0x72,0xc3,0x2f,0x52,0xfc,0x30,0x6a,0x11,0xa5,0xd0,0x6d,0xef,
+  0x93,0x9d,0x70,0xd8,0x1a,0x1d,0x9b,0x35,0x1f,0x76,0xab,0xd6,0xa9,0x94,0xf6,0xf3,
+  0x10,0x3b,0x09,0x7b,0x00,0x85,0xf6,0xa6,0x21,0x98,0x41,0x8c,0x94,0x55,0x6c,0x96,
+  0x62,0x75,0xdc,0x25,0x7e,0xf8,0xf4,0xf5,0x00,0x0f,0xc2,0x23,0x56,0x59,0x9c,0xfb,
+  0x4d,0xab,0x3e,0xce,0x58,0xcd,0xde,0xe4,0x33,0x22,0x95,0xdb,0xf3,0xea,0xd8,0x6c,
+  0xd8,0x2e,0xb6,0xd1,0x3c,0x14,0x61,0xe3,0x47,0x1d,0xd3,0x3b,0x3f,0xa7,0x9b,0x1c,
+  0xfd,0x2f,0xaa,0x4f,0x49,0xf0,0x00,0x3b,0x26,0x3a,0x13,0xbe,0xb3,0x79,0x37,0x3a,
+  0x5c,0x7c,0xc7,0x3d,0xfa,0x6f,0xb2,0xe7,0x83,0xe4,0x44,0xd8,0x1b,0x22,0x10,0xf5,
+  0xf6,0xc8,0xef,0xc1,0x05,0x23,0x2e,0x7c,0xdb,0xe5,0xd1,0xf0,0x61,0xa8,0x12,0xb7,
+  0x3d,0xa1,0x56,0x44,0xb6,0x1b,0x81,0x2e,0x9a,0x0f,0x92,0xee,0x2f,0xda,0xaa,0x9d,
+  0x36,0x26,0xf8,0x41,0xb7,0x0b,0x64,0x53,0x4c,0xf0,0xa9,0xfe,0xd8,0xe3,0x10,0x64,
+  0x94,0x1f,0xac,0xe8,0xd3,0x82,0xd9,0xf3,0xd1,0x88,0x1f,0xd5,0x0f,0xf7,0xb6,0xa7,
+  0xfa,0x03,0x18,0xc1,0x76,0x67,0x09,0x09,0x4d,0xfe,0xe5,0xd4,0x48,0x50,0x3b,0x54,
+  0xb8,0xea,0xcb,0xce,0xec,0xfc,0xe0,0x7f,0x9b,0xb1,0x4e,0x6c,0x5f,0x9d,0x1a,0xcb,
+  0x25,0xaa,0x8c,0xfc,0xc7,0xe5,0x16,0xaa,0xcf,0x0a,0xf1,0x2d,0x44,0x54,0xee,0xfc,
+  0x26,0xd5,0xc7,0xd9,0xfb,0x43,0xd6,0xb4,0x6c,0xd4,0xca,0x0c,0x7e,0x3c,0xb7,0x46,
+  0x22,0x62,0x4f,0xde,0x2f,0xc2,0xdf,0x80,0x8d,0x14,0x78,0x1c,0xdf,0xfc,0x7b,0x65,
+  0xa3,0x84,0xa7,0x86,0xb3,0xfa,0x43,0xce,0xb2,0xe6,0xa3,0x79,0x97,0xad,0x2f,0xde,
+  0x41,0xf3,0xd1,0xf2,0x50,0xd8,0x9e,0x3a,0x12,0x3e,0x11,0x5b,0x53,0x35,0x87,0xea,
+  0xe3,0x06,0xd2,0xd7,0xaf,0xe6,0x21,0xb1,0xde,0xe3,0xe1,0xce,0xd4,0x34,0x34,0x6a,
+  0x0b,0xc9,0x42,0x5b,0x12,0xfa,0xbd,0x74,0x24,0x19,0x4e,0xe8,0x78,0x6a,0xc0,0x96,
+  0x1f,0xdc,0x9a,0xbf,0x53,0x49,0xb1,0x9d,0xe5,0x91,0xd8,0x14,0xed,0x99,0xe2,0x3f,
+  0x05,0x6d,0x54,0x4f,0x51,0x68,0x1d,0xb9,0x92,0x1f,0xfe,0x9a,0x34,0xdf,0x78,0xf0,
+  0x38,0x5e,0xff,0x89,0x6e,0xf1,0xc3,0x6b,0xe0,0x83,0x72,0xe2,0x87,0xab,0x35,0xf0,
+  0x4a,0xce,0x02,0x9a,0x8f,0x96,0xdd,0x1f,0x32,0x02,0xf5,0x54,0x04,0x97,0x14,0x7d,
+  0x9a,0x47,0x03,0xc1,0xbc,0xad,0x3d,0x4a,0x95,0x68,0xed,0x60,0xa5,0xd0,0x03,0xdb,
+  0x95,0x8a,0xf0,0xe6,0x07,0xd3,0xeb,0xdf,0x9a,0x33,0x68,0x91,0xc0,0x1d,0x85,0x4d,
+  0x5d,0x7d,0xbb,0x41,0x6f,0x59,0x47,0x83,0xd2,0x4a,0x8b,0x53,0xb4,0x31,0x63,0x5b,
+  0xaa,0x75,0xa4,0x3b,0x33,0x1f,0x76,0xe6,0x4e,0xb6,0x4e,0xaf,0x32,0x70,0xb5,0x7f,
+  0x63,0xb5,0xe5,0xcc,0xdb,0xec,0xc1,0x1f,0x42,0xaf,0x6a,0xf5,0x6e,0x66,0x73,0xf9,
+  0x53,0xed,0x9e,0x3b,0x1c,0x51,0xf6,0xe3,0xac,0xf9,0x20,0x87,0x44,0xf0,0xd6,0x02,
+  0x2b,0xec,0x09,0xe1,0x25,0x95,0x5b,0x36,0x5d,0x0f,0xef,0x45,0x82,0x86,0x33,0x2a,
+  0xcd,0x80,0xf7,0x44,0x20,0x84,0xbf,0xef,0x8a,0x4c,0x7e,0x50,0xea,0xd2,0xcf,0x43,
+  0x7d,0x93,0x15,0x16,0x3b,0xab,0x50,0xb5,0x60,0xd1,0x6f,0xa4,0xf3,0xe0,0x5b,0x94,
+  0x5a,0x28,0x4a,0x1d,0x6a,0xd9,0xfd,0x91,0x9a,0x4e,0x42,0x2d,0xe4,0x53,0x36,0x36,
+  0x81,0xcb,0xe0,0xa2,0xb6,0xe4,0x27,0xdb,0x7b,0x35,0xa7,0xd4,0xa9,0xeb,0x27,0x21,
+  0x95,0x3f,0xca,0xf4,0x87,0xcc,0xa1,0x20,0x58,0x69,0x8c,0xda,0x02,0xc0,0x7a,0x8e,
+  0xfa,0x79,0xc4,0x73,0x35,0xcd,0x47,0xeb,0xe1,0x49,0xf5,0x5b,0xe1,0x5b,0xef,0xb8,
+  0x51,0x64,0xc7,0xc7,0xba,0x72,0x21,0x1c,0x29,0xdf,0x9b,0x57,0x42,0xf1,0x1c,0xf0,
+  0x26,0xd5,0x1b,0xdd,0xb9,0xed,0x0f,0x81,0x9e,0xf4,0xd6,0xb1,0x75,0xd0,0x69,0xea,
+  0xef,0x71,0xbf,0x91,0x89,0x8f,0x95,0x42,0xb1,0xb6,0x96,0xea,0x73,0xeb,0xc2,0xb3,
+  0xdb,0xd6,0xc2,0xdf,0x34,0xa9,0x54,0xe8,0x3a,0x43,0x94,0x1a,0x5b,0x57,0xe5,0x9e,
+  0x82,0x35,0xc6,0x53,0xc0,0xff,0xde,0x16,0x1f,0xf3,0x46,0x1c,0xf0,0x73,0xf1,0x7f,
+  0x24,0xf3,0x57,0xcf,0x08,0x8a,0x97,0xc5,0x3c,0x6a,0xec,0x3f,0x1b,0xfe,0x42,0xf8,
+  0x47,0x9c,0x2b,0x8a,0x7e,0xc4,0x7e,0x2e,0x76,0x5b,0xf1,0xb1,0xb9,0xe9,0xfd,0x59,
+  0xd2,0xc3,0xdf,0xa1,0x32,0x70,0x2b,0xfb,0x03,0x0f,0x50,0xb4,0x67,0x08,0x3e,0xa6,
+  0xfe,0xe1,0x7e,0x69,0x09,0x7b,0x4a,0xa9,0x97,0xac,0xf9,0xb0,0xd3,0xef,0xdb,0x94,
+  0x33,0xc1,0x36,0x49,0x55,0xa3,0xca,0x84,0xfc,0x1d,0x38,0xd6,0x65,0x75,0x43,0xba,
+  0xa4,0x5c,0xee,0x08,0x24,0x37,0x9d,0x6f,0xfe,0x11,0xcd,0x37,0xa7,0x23,0xf6,0xf9,
+  0x68,0x8f,0x89,0xb5,0x7e,0xdf,0x58,0x09,0xb1,0xb9,0xd6,0xb2,0x7c,0x2b,0x1e,0x08,
+  0xfb,0x60,0xdb,0x0a,0x75,0x35,0xdb,0xa8,0xaf,0xe1,0xdb,0x0c,0xca,0x0f,0xa6,0xe7,
+  0x83,0x08,0xb1,0x75,0x11,0x65,0x03,0x23,0x7e,0x36,0x6b,0xaa,0x1b,0x52,0xf8,0x14,
+  0xec,0xe1,0xa5,0xaf,0xaa,0xdf,0x0c,0x3f,0x8e,0x47,0x74,0x33,0xef,0x1b,0xb6,0xfc,
+  0x60,0xa8,0x38,0xc1,0x69,0x1e,0x7a,0xab,0x9f,0x11,0xbb,0x1e,0xb5,0x77,0x0d,0x3b,
+  0x2a,0xf6,0x0c,0xea,0xed,0xb8,0x50,0x9b,0x68,0x3d,0x07,0xf3,0xec,0xf3,0xd1,0xbc,
+  0xc5,0xa4,0x3f,0x83,0xa6,0xcf,0xaf,0x06,0xe1,0x88,0x40,0xa1,0x4f,0xfe,0x50,0xb9,
+  0x38,0x18,0x18,0x77,0x1d,0x64,0x3f,0xb9,0xf5,0x08,0x78,0xc6,0x2b,0x3f,0xb2,0xf1,
+  0xdf,0x04,0x6e,0xf1,0x8b,0x46,0x70,0x98,0x96,0xc5,0xb8,0x48,0x63,0xbb,0xfd,0x24,
+  0x40,0x43,0xc2,0xb5,0x57,0xfd,0x00,0x3e,0xe6,0xc1,0x81,0x82,0xec,0xfc,0x60,0x1f,
+  0x85,0xc5,0x06,0x9d,0x1f,0x51,0x37,0x00,0x08,0xbe,0xed,0x1a,0xef,0x6c,0x68,0xfd,
+  0xf9,0xd6,0xea,0xe5,0xce,0xf1,0xa2,0xfb,0xe1,0xc8,0xb6,0x1b,0x4c,0xc5,0x3e,0x1f,
+  0xb6,0x5f,0x71,0x90,0x19,0x3a,0xe9,0xa5,0xb2,0xac,0x6e,0xa8,0x4a,0xd2,0x98,0x57,
+  0x1a,0x94,0x66,0x78,0xeb,0xe4,0xdb,0x61,0x9d,0xe9,0x59,0x65,0xf5,0x87,0x9c,0xfe,
+  0xbd,0x68,0x3e,0xec,0x63,0xe6,0xdc,0x54,0x1a,0xab,0x5b,0xaf,0x4a,0xd0,0xf5,0x12,
+  0x05,0xca,0x5a,0x1f,0x77,0x7c,0x0d,0x1e,0x33,0x3c,0xe3,0x57,0xf4,0x47,0xe2,0xfa,
+  0xc3,0x52,0x39,0xb1,0x55,0xa9,0xfa,0xd2,0x47,0x81,0x32,0xdc,0xc9,0xc4,0xd8,0x74,
+  0x3b,0x5a,0x8c,0xcd,0x5a,0xcc,0xbc,0x3a,0xbb,0x3f,0xd2,0x8a,0xf5,0xbf,0xa6,0xf9,
+  0x17,0x71,0x8b,0x16,0x55,0x45,0xfb,0xa1,0x12,0x85,0x3d,0xad,0xf8,0x59,0x7d,0x15,
+  0x7e,0x2d,0x05,0xcc,0xaa,0xec,0xf9,0x68,0x09,0xf8,0x80,0xed,0x5f,0x92,0xe6,0xb7,
+  0xb8,0x06,0xd4,0xc9,0x5d,0xdf,0x85,0xc6,0x5b,0x5d,0x85,0xf2,0x39,0xfe,0xa1,0xfe,
+  0x6d,0xea,0x6f,0x9c,0xe1,0x47,0x0d,0xcc,0xbc,0xc4,0x8f,0x89,0xea,0x91,0xa1,0x8f,
+  0xe5,0xa0,0xf1,0x73,0xb3,0xda,0xef,0x3c,0xaf,0x06,0x8d,0xc9,0x28,0xae,0xd8,0x04,
+  0x11,0xc9,0xa2,0x7b,0x4a,0x9c,0x07,0x9b,0x33,0xf8,0xc7,0xd4,0xc6,0xb6,0x74,0x96,
+  0xa2,0x7d,0x39,0xdb,0xe4,0x13,0xdd,0x34,0xdd,0xa3,0x97,0x39,0x45,0xaf,0xfe,0x99,
+  0x93,0xb7,0xc7,0x99,0xb3,0x6b,0x9d,0x8e,0xd0,0xc5,0xcf,0xfc,0x99,0xfe,0x90,0xb0,
+  0xc1,0xd3,0xc9,0x63,0x89,0x15,0x81,0x0a,0x27,0x93,0x45,0x2c,0xb9,0x02,0x5f,0x5c,
+  0x3c,0x0f,0xfa,0x30,0x0f,0xac,0xdf,0x50,0x86,0x86,0x6b,0xab,0x37,0x70,0x75,0x20,
+  0xc3,0x0f,0x2f,0xde,0x40,0x30,0xc9,0xb4,0xf0,0x52,0x07,0x19,0x3e,0xa2,0x8d,0x3d,
+  0x0f,0x15,0xfd,0xb8,0x7f,0x36,0x2c,0x0a,0x73,0x3d,0x64,0xdd,0x7f,0x7a,0x7f,0x2e,
+  0x9a,0x89,0xd6,0x96,0x59,0x69,0xbb,0x2a,0xa3,0x5b,0x04,0x92,0x4b,0xfa,0xca,0x7c,
+  0xd2,0x05,0xea,0xf8,0xd4,0x27,0xff,0x44,0x3f,0x62,0x04,0x02,0x78,0x4a,0x4f,0xdb,
+  0x2f,0xca,0x0f,0x4e,0x35,0x39,0x9c,0xb4,0xfa,0x43,0xba,0xce,0x95,0x5d,0x8a,0x5d,
+  0xe2,0x8d,0xe6,0xed,0x17,0xe4,0xfb,0xb5,0xcb,0xd1,0x46,0xd8,0x74,0x45,0x7f,0x48,
+  0x71,0x51,0xaf,0x4d,0xe4,0xf7,0xca,0x3e,0xf1,0xbe,0x1e,0x48,0x38,0xe3,0xdd,0x2b,
+  0x09,0x08,0x99,0x05,0xbd,0xc4,0x8f,0xe2,0x81,0xad,0x0f,0xd2,0x7c,0xb4,0xe9,0x9f,
+  0xcb,0xcc,0xa9,0x14,0x07,0x12,0x9e,0x09,0x7e,0x2e,0x3c,0x1f,0xf6,0x27,0x3c,0x27,
+  0xef,0xec,0x63,0x3f,0x11,0x61,0x63,0xe1,0xdb,0xfc,0x20,0xab,0xd4,0x7f,0xcd,0x3d,
+  0x13,0xad,0x2f,0xca,0xdf,0x4c,0xef,0x87,0x84,0x42,0x65,0x02,0x54,0x14,0xe9,0x70,
+  0xb6,0xee,0x91,0xf0,0xc5,0x6b,0x10,0x08,0x85,0xc5,0xdc,0xe3,0x57,0xd3,0x60,0x8b,
+  0xcd,0x46,0x0c,0xf2,0xfc,0xac,0x3e,0xd3,0x1f,0x52,0xfb,0x22,0xc2,0x80,0xd2,0x24,
+  0xff,0xd6,0xb2,0xd9,0xc6,0x4b,0x28,0x94,0xac,0x7e,0xe0,0x47,0xf0,0x00,0x2e,0x54,
+  0x64,0x75,0x78,0x59,0xf1,0xf7,0x84,0xbe,0xfc,0xd3,0xab,0xd9,0xfd,0xb6,0xfc,0xe0,
+  0xed,0xa8,0x3d,0x6a,0x06,0x6f,0xdb,0x9d,0xeb,0x44,0xc1,0x9f,0xe0,0x7d,0xf2,0x12,
+  0x18,0xc0,0xff,0x62,0x41,0xaf,0xbc,0x01,0x1e,0xa3,0x7e,0x29,0x75,0xf6,0xfc,0xe0,
+  0x4c,0x5a,0x9f,0xe0,0xa0,0xd5,0x5f,0xeb,0x32,0xbc,0x64,0xaa,0x67,0xe5,0xfb,0x8d,
+  0x4b,0x16,0x63,0x5c,0xde,0x45,0xf3,0x53,0xfa,0x3d,0xf6,0xfa,0x38,0x4e,0xf1,0x6d,
+  0x8a,0xde,0xbf,0x80,0x9f,0x2d,0xfe,0x10,0x49,0x5c,0xf6,0x5d,0x70,0x41,0x04,0x0e,
+  0xa7,0x88,0x52,0xd4,0x3a,0xb2,0xaf,0xd9,0xc6,0x0f,0xd7,0x52,0xfd,0x01,0xd4,0x8f,
+  0xd9,0x2c,0xbe,0x36,0xd5,0x1f,0x69,0x16,0xbc,0xc4,0x4a,0x4d,0x2b,0xd1,0xb0,0x8f,
+  0x55,0x1a,0x3d,0xe3,0xac,0xb7,0x7c,0xfa,0xfe,0xa9,0xfc,0x20,0xcd,0x43,0x61,0x2f,
+  0x5a,0xd3,0x40,0xac,0x46,0x01,0xcf,0x09,0x18,0xc9,0x5b,0xed,0x79,0x53,0xdf,0xd7,
+  0x51,0x19,0xc3,0x23,0x7a,0x1a,0xaf,0x8e,0x2a,0xbb,0xe0,0x00,0xab,0x32,0xbb,0xfd,
+  0x4c,0x31,0xd6,0x3b,0x62,0x13,0xbc,0x84,0xe5,0x42,0x2f,0x35,0x6e,0xdd,0xda,0x74,
+  0x14,0x0e,0x24,0xac,0x7c,0xc7,0xe6,0xf4,0xfe,0x4c,0x4a,0xa3,0x40,0x49,0xc0,0x4d,
+  0x31,0xf9,0x69,0x34,0x1c,0xd5,0x71,0xe7,0xd3,0xf2,0xd3,0xde,0x4b,0x91,0x5e,0x91,
+  0xdf,0x23,0x4f,0x18,0x97,0x06,0x1a,0x37,0x3a,0x89,0x1f,0x35,0xfd,0x3c,0xad,0x94,
+  0x1d,0x83,0x2a,0xd8,0x44,0x6d,0xf6,0x26,0x20,0xa8,0x34,0x8a,0x14,0x3f,0x4a,0x4b,
+  0xcd,0x47,0xd3,0x52,0xf5,0x71,0x5a,0x1a,0xff,0xc0,0x4e,0xfe,0xba,0x45,0xf2,0x41,
+  0xeb,0xf6,0x2d,0x3d,0xd0,0xb2,0x18,0x0d,0xdf,0x2d,0xd4,0x16,0x52,0xb1,0x32,0x86,
+  0x9a,0xc5,0xff,0xb9,0xb2,0x3e,0xee,0xe9,0x55,0xf9,0x56,0x5a,0x10,0xb6,0x37,0x59,
+  0xdd,0xad,0x89,0xef,0xe4,0xb5,0x12,0x55,0xa8,0x7f,0xf2,0xed,0xf8,0xa7,0x6e,0x66,
+  0x39,0x3c,0x0a,0x9e,0xa6,0x54,0x1a,0x11,0xa8,0x8d,0xb3,0xdb,0xea,0xa7,0x4a,0x15,
+  0x73,0xe5,0xca,0x7e,0xae,0x37,0x65,0xd5,0xc7,0x51,0x7e,0x90,0xfa,0x6f,0xe7,0xb9,
+  0xc3,0x43,0x56,0xda,0x42,0xd5,0xd8,0x08,0xeb,0x00,0xdf,0x61,0x87,0xe6,0x50,0x76,
+  0xee,0x66,0xb1,0xb6,0x3c,0xad,0x29,0xa3,0x7f,0x56,0xd3,0x7c,0x10,0x4a,0x4b,0x85,
+  0x09,0xe6,0x49,0x81,0x14,0xde,0x8b,0x40,0x90,0x17,0x50,0xa1,0x1c,0x11,0xc5,0x9d,
+  0x42,0xfe,0x30,0x93,0x1f,0x9c,0x39,0x12,0x3f,0x3f,0x2f,0xd8,0xb6,0x74,0x33,0xf5,
+  0x87,0x4c,0xd1,0xa2,0xce,0xc5,0xa8,0x63,0xd2,0x6b,0x29,0xc6,0x54,0x63,0xdb,0xa6,
+  0xcd,0x9d,0x7f,0x60,0x76,0x7e,0xf8,0xeb,0xc4,0xaf,0xde,0x4c,0xb0,0x50,0x0b,0x5a,
+  0xfc,0x79,0xe3,0x10,0x04,0xda,0x9c,0x85,0xf2,0x88,0x86,0xc2,0x2d,0xce,0x68,0x99,
+  0x8d,0x4f,0x55,0x12,0xd3,0x23,0xd4,0x1f,0x32,0xdc,0x69,0x0a,0xae,0x57,0xc9,0x4e,
+  0xca,0x0f,0x0a,0x6f,0x05,0x6f,0x0a,0xc3,0xe9,0xf2,0x08,0xdf,0x0e,0x7c,0x20,0xfc,
+  0x66,0x66,0x3e,0x9a,0xb2,0x45,0xac,0x81,0x4a,0x9a,0x0f,0x72,0x47,0x6c,0x8d,0x5e,
+  0xd9,0xda,0xda,0xee,0x2e,0x56,0x36,0x96,0x96,0xb6,0x89,0x65,0xd4,0x31,0x49,0xda,
+  0x41,0xd4,0xa9,0x4c,0x7f,0xc8,0xad,0xca,0x4e,0xb0,0xf8,0xe1,0xc3,0x6c,0xaf,0xb1,
+  0x11,0x5c,0x6d,0xad,0xed,0xac,0xc6,0xd8,0xa8,0xcd,0x5b,0xe4,0x3d,0xce,0x7e,0x1f,
+  0x5e,0x03,0x65,0xed,0xde,0x61,0xdb,0x7a,0xc6,0x66,0x5a,0xd5,0x70,0x34,0x86,0x69,
+  0x39,0x1c,0x4a,0x50,0xa3,0x48,0xb5,0x9c,0xf5,0x9b,0x56,0x5b,0x00,0xc4,0xab,0x5b,
+  0x03,0x08,0x7d,0xd9,0xa8,0x98,0x5e,0x1f,0xca,0x0f,0xbe,0x67,0x35,0x01,0xe8,0x7c,
+  0x97,0x9d,0x37,0x82,0x8b,0x0a,0x2c,0x5a,0x94,0x98,0xea,0x20,0x7a,0x3e,0x6c,0xf1,
+  0xa3,0xec,0xf9,0xc1,0x78,0xa4,0x41,0xb7,0xfa,0x23,0xc5,0x61,0x08,0xaa,0x35,0xd7,
+  0x40,0xd1,0x78,0x78,0xa8,0xe5,0xef,0xe9,0x48,0xa1,0x38,0x65,0x54,0x03,0xfa,0xa7,
+  0x87,0xc5,0xf4,0xfe,0xf7,0xe6,0x7c,0x06,0xce,0x98,0x1e,0xea,0x06,0x90,0x80,0xf5,
+  0x8b,0xee,0x11,0x8b,0x77,0xb9,0xdf,0x53,0xd6,0x4b,0x15,0x78,0xa4,0xf9,0xef,0x88,
+  0xe8,0x24,0x1c,0x49,0x39,0x92,0xd9,0x0f,0xca,0x97,0x20,0x66,0xce,0x05,0xd5,0xc9,
+  0x4c,0x10,0x9f,0xad,0x80,0x6b,0x9c,0xb8,0xbb,0x50,0x2d,0x4b,0xaa,0xc4,0x64,0x2b,
+  0xe0,0x12,0x01,0x76,0x38,0xcd,0x4f,0x10,0xda,0x7f,0x85,0x27,0xcd,0x54,0x5b,0x00,
+  0xe9,0x49,0x31,0xcf,0x54,0xbf,0x61,0xd5,0x77,0xa0,0x30,0xc1,0x6e,0xe3,0x9b,0x10,
+  0x78,0xa3,0xff,0x32,0x6a,0x4c,0xdf,0x3f,0x12,0x59,0x06,0x63,0xe2,0x86,0xa4,0x8b,
+  0xf8,0x51,0x47,0x09,0xff,0xb4,0xca,0x17,0x94,0x41,0xb1,0x2d,0xe4,0x6a,0x2d,0x73,
+  0x23,0x34,0x5a,0x90,0x74,0xb6,0xca,0x67,0x32,0xfc,0xa8,0xc2,0x5d,0xf0,0x77,0xa9,
+  0x79,0x19,0xa3,0xec,0x75,0x78,0x0e,0x54,0x2a,0x43,0x46,0x0d,0x63,0xcd,0xa3,0x84,
+  0x24,0x20,0xd8,0x8a,0xcb,0xe1,0x4c,0x7f,0x48,0xe5,0xa0,0xf1,0x96,0xf8,0x6e,0x39,
+  0x3a,0x65,0x01,0xf8,0x44,0x34,0xea,0xb7,0x4d,0xc8,0x7f,0x80,0xc9,0x8e,0x60,0xf9,
+  0x8c,0xa7,0x10,0x08,0x0d,0x89,0x6a,0xe2,0x47,0x8d,0xdb,0xf2,0x83,0x82,0xa6,0x51,
+  0x8f,0xaa,0x6d,0xea,0x2c,0xe3,0x39,0x54,0x44,0x39,0x40,0xfd,0xf9,0x19,0x1e,0xb9,
+  0xd3,0x3d,0xce,0x9e,0xa4,0xfa,0xb8,0x55,0x36,0xfc,0x03,0xe2,0xf1,0x45,0xa4,0xaf,
+  0xba,0x03,0xec,0x04,0x2a,0xae,0xf9,0x74,0xf6,0x14,0xde,0x61,0xce,0x12,0xf5,0x9e,
+  0xed,0xa7,0x8c,0xb5,0x30,0x7f,0x18,0x5d,0xd1,0xc1,0x0c,0x3f,0x5c,0x11,0x56,0x7f,
+  0x12,0x15,0x18,0x07,0xf4,0xa6,0xb4,0x3c,0x09,0x17,0xf6,0x80,0xe6,0x13,0x8b,0x4b,
+  0x98,0xd9,0x1e,0x33,0x7c,0xe0,0x8d,0xdb,0xf0,0x4f,0xcf,0xcc,0x24,0x9f,0x2a,0xaa,
+  0x7d,0x5a,0xf4,0x99,0xe8,0x36,0x46,0xe4,0xa4,0x7e,0xf1,0xc4,0x37,0xc5,0x5f,0x6f,
+  0x2d,0x4b,0x4a,0x09,0xb3,0x81,0xa3,0xfe,0x39,0x69,0xe3,0x87,0xef,0xb2,0x92,0x86,
+  0xd7,0x51,0x19,0xdd,0xc5,0x92,0x60,0xd2,0x6a,0x14,0x89,0x77,0x30,0xae,0xdb,0x29,
+  0x8f,0x95,0x5e,0xf4,0xd3,0xa8,0x74,0xf9,0x74,0x1a,0xff,0x97,0x6a,0xe3,0x34,0x1d,
+  0xde,0xf4,0x99,0xf0,0x1d,0xf8,0x10,0xbe,0x3b,0xa0,0x9a,0x72,0x1d,0x1c,0xd3,0xaa,
+  0x93,0xf9,0xc3,0xb2,0x1f,0x15,0x6f,0xb5,0xe9,0x1c,0x55,0x33,0xf6,0x7a,0x9b,0x42,
+  0x65,0x59,0xd4,0x8d,0x87,0xe9,0x4b,0xf6,0x53,0xbf,0x2c,0x3f,0xaa,0x9d,0x93,0xe8,
+  0x56,0x78,0x63,0xf2,0x4a,0x7c,0xb5,0x0a,0x2a,0x5d,0xcf,0xd4,0xa7,0x88,0x1c,0x27,
+  0x1a,0x11,0xbc,0xde,0x9f,0x3b,0x8a,0xfa,0xe7,0x6b,0x90,0x17,0x47,0xff,0xa2,0x9b,
+  0xeb,0x1d,0xad,0xfe,0xcd,0x3e,0xad,0x8f,0x21,0x1e,0xd8,0x66,0xe7,0x47,0x15,0x4b,
+  0x10,0x65,0xbe,0x81,0x08,0x84,0xbb,0xa0,0xd7,0x9a,0x9e,0x96,0xcb,0x21,0x6a,0x0d,
+  0xb2,0x0a,0x1b,0xd4,0x91,0xd5,0xcc,0xaa,0x4f,0x81,0xfc,0xaf,0x12,0x3f,0x1c,0x61,
+  0x86,0x9c,0x6a,0x93,0x95,0x9f,0x02,0x42,0x6e,0xb2,0x2f,0x3e,0xb4,0x68,0x68,0xe8,
+  0xb7,0xc9,0x7a,0x5a,0xff,0x6c,0x9b,0x39,0x2e,0xc6,0x52,0xeb,0xb9,0x0a,0x26,0xe1,
+  0x66,0xc8,0x37,0x3b,0x53,0xfd,0x5b,0x36,0x9a,0x45,0xe3,0xd6,0x11,0x97,0xbd,0x3f,
+  0x52,0x7f,0xce,0x78,0xf4,0x94,0xee,0x80,0x02,0xa3,0x33,0x2e,0xf0,0x32,0x07,0x35,
+  0x56,0x8a,0xe2,0x87,0xc6,0x5d,0xf4,0x0f,0x07,0xa1,0xda,0xed,0x6a,0xb7,0xcd,0x47,
+  0x33,0x4b,0x7e,0x4a,0xfd,0x91,0xc6,0xd1,0x9a,0xcf,0x87,0x03,0xd1,0xaa,0x71,0xbe,
+  0xdf,0xf8,0x9d,0xd1,0x6d,0x7a,0xc6,0x11,0xf8,0x7d,0x15,0x9e,0x31,0x2b,0x4e,0xaa,
+  0x3f,0x61,0x7a,0x9a,0x9f,0x99,0x50,0x36,0x48,0x7b,0xd0,0x8b,0x71,0xe8,0x4c,0x18,
+  0xbb,0xa9,0x1b,0x2d,0x30,0x13,0x45,0x5d,0xb1,0xf2,0xef,0x28,0xb4,0x5e,0xad,0xb1,
+  0x70,0x86,0x1f,0xae,0x50,0x7f,0x24,0xcf,0x49,0xea,0x0f,0xa0,0x3f,0x0f,0x05,0xb8,
+  0x9b,0xdc,0xd4,0x6f,0x8a,0x99,0xaa,0x68,0x0a,0xc1,0x33,0x32,0x7d,0xc8,0xcc,0x9f,
+  0xe6,0x53,0x7d,0xce,0xea,0x8f,0x54,0x01,0xe8,0x7f,0xed,0x80,0xd5,0x9a,0x35,0x58,
+  0x67,0xb4,0xfc,0x08,0xf4,0xb6,0x58,0x8a,0xfa,0x65,0x54,0xdd,0x78,0x2a,0x6a,0x9b,
+  0x0f,0x4b,0xf6,0xfd,0x66,0xd3,0x95,0x94,0x2f,0xb5,0x5e,0x16,0x8d,0x06,0x5e,0x76,
+  0x8e,0xfa,0xad,0x09,0x0b,0x31,0x4e,0x52,0xc7,0x80,0x33,0xd9,0xf8,0x07,0xfe,0x9e,
+  0x8c,0x9a,0x5f,0xde,0x86,0x8a,0xba,0x81,0xb2,0xb1,0x5e,0xea,0x3f,0xd9,0x54,0xd0,
+  0x3b,0x63,0x83,0xf1,0xbe,0xdf,0xaa,0xf8,0xce,0xc4,0x7f,0x4e,0xe6,0x94,0xb5,0xf4,
+  0xb5,0x23,0x6c,0x16,0xac,0x4a,0xac,0x17,0x56,0x37,0x24,0x05,0x3f,0x84,0xe0,0x6e,
+  0xde,0x35,0xe3,0x1e,0x88,0x18,0x1e,0x11,0xd1,0x9b,0x32,0xfd,0x01,0x4c,0x65,0x91,
+  0x11,0xc7,0xdd,0x89,0x6f,0xf8,0x20,0xf4,0x46,0x7d,0xa5,0xaa,0xe2,0x50,0x16,0x45,
+  0x85,0x37,0xda,0x86,0xef,0xac,0xc4,0x94,0x58,0xcc,0x8b,0x78,0x2f,0xbd,0xdf,0x10,
+  0xff,0x74,0x3d,0x22,0x2a,0x2b,0xd4,0x6f,0x31,0x37,0x3c,0x21,0x2a,0x93,0xd7,0xac,
+  0xce,0xbd,0x3a,0x67,0xcf,0xb6,0xca,0xe5,0xfc,0x5b,0xa9,0x8e,0x91,0x21,0xfc,0x1e,
+  0x4b,0x6c,0xfc,0xf0,0xdb,0xc5,0xc7,0x7a,0xc3,0xe8,0x26,0x1d,0x61,0xd5,0xc7,0xe0,
+  0x6b,0x9a,0x01,0x45,0x8a,0x81,0xf0,0x3b,0x5c,0xe0,0x67,0x63,0x10,0xa3,0xfd,0x43,
+  0xfc,0xa8,0x34,0x3f,0x3c,0xc7,0x1a,0xfb,0xae,0xb8,0x86,0xe5,0x61,0xe3,0x24,0x55,
+  0xa3,0x8c,0x17,0x4d,0x18,0x97,0xf5,0x99,0x86,0xcb,0x68,0x1e,0x47,0x68,0xd1,0x08,
+  0x05,0x89,0x2c,0x7e,0x78,0x0c,0x95,0x52,0x20,0xa9,0x47,0xf1,0xeb,0xf8,0x08,0x6a,
+  0x63,0x3e,0xcb,0x71,0x13,0x61,0x13,0xdd,0xd2,0x10,0xfb,0x35,0xd4,0x88,0x7c,0x8a,
+  0xff,0x4c,0x5f,0x9f,0x28,0xd9,0x40,0x4e,0x13,0xf0,0x10,0x6e,0xd9,0x67,0x69,0x3a,
+  0x95,0xc1,0x86,0x9d,0x7b,0x95,0x52,0xfa,0xd0,0x36,0xe0,0xe7,0xbd,0x8d,0x8e,0x7c,
+  0x94,0xe6,0x87,0x23,0xfe,0xd1,0x9e,0x14,0x53,0xb0,0x67,0x5f,0x07,0x24,0xf3,0xee,
+  0x67,0x6f,0xc2,0x9e,0x81,0xf2,0xe4,0x3a,0xab,0x43,0x26,0x42,0xa3,0xbc,0xd5,0xa8,
+  0xea,0xa7,0xaf,0x1f,0x55,0x04,0x08,0xfc,0x7a,0x78,0xae,0x87,0xfa,0xdd,0xe9,0xf0,
+  0x69,0x52,0xec,0x71,0xa3,0x5c,0xcb,0xb3,0x3a,0x50,0x71,0x9d,0xe2,0x8d,0x6f,0xa4,
+  0xaf,0x4f,0xce,0x1c,0x85,0x33,0x88,0x37,0xf9,0x4e,0xf4,0x97,0x9f,0x87,0x40,0xcf,
+  0xb5,0x31,0xf9,0x0c,0x3c,0x6f,0xd6,0x46,0xf3,0x63,0xcd,0x5e,0x38,0x3c,0x50,0x4b,
+  0xfd,0xf4,0x26,0x32,0xfc,0x70,0x29,0xae,0x51,0x13,0xa4,0x54,0x37,0x24,0xfc,0x5e,
+  0x0b,0x5e,0xc5,0x85,0x9a,0xd4,0x6f,0xe2,0x0f,0x92,0x85,0x1a,0x2b,0x7c,0x21,0x15,
+  0xff,0x49,0xaf,0x8f,0xf6,0x00,0xfc,0x22,0x56,0x6b,0xb8,0xdc,0x6c,0x79,0x53,0x7f,
+  0xb4,0xb6,0xf5,0xba,0xad,0x33,0x46,0x8c,0x43,0x9e,0xfb,0xd1,0x3e,0xaa,0x0a,0xf4,
+  0x47,0x11,0xff,0x10,0x3f,0x6a,0xfa,0x79,0x84,0xf2,0x65,0x8d,0xc6,0xb2,0xd3,0x18,
+  0x53,0x58,0x27,0x50,0x78,0x88,0x8d,0x48,0xaf,0x4b,0x55,0xab,0xb8,0x16,0x2e,0x87,
+  0xd7,0xf3,0x6a,0x43,0xf9,0x57,0xf0,0xa3,0xc4,0x0f,0xe1,0xfa,0x16,0x1a,0xe3,0x25,
+  0x6d,0x64,0xd7,0x1b,0xd7,0x9c,0x70,0x9f,0x23,0x0b,0xde,0xc6,0x89,0xcf,0x4c,0xa3,
+  0xbe,0x50,0x28,0xb0,0xe1,0x9f,0xe2,0xd8,0x5a,0x6f,0x69,0x9b,0xba,0x2c,0xbc,0x37,
+  0xb6,0xc6,0x7b,0x37,0x09,0xa7,0x9e,0xfa,0x9e,0xb7,0xb2,0x2d,0x42,0x8d,0x92,0xbe,
+  0xe7,0x9d,0x43,0x1d,0x93,0xda,0xd2,0xfc,0xcc,0xd5,0xf9,0x2b,0xc4,0x49,0xbd,0x96,
+  0xab,0xe1,0xb2,0xa4,0x48,0xa0,0xb0,0x38,0xdc,0x44,0xf3,0x61,0xab,0xb8,0x2f,0x15,
+  0x11,0x0a,0xe4,0x39,0x07,0xe4,0xd9,0x76,0xfc,0x93,0x6a,0xfb,0xa3,0x95,0x2d,0x9f,
+  0x2a,0x7b,0x2f,0x5a,0xae,0x4d,0x45,0x84,0xc6,0x28,0x22,0x74,0x98,0x0c,0xbd,0x92,
+  0xc1,0x3f,0xe7,0xac,0x26,0x48,0xae,0xe3,0xac,0x66,0xef,0x6b,0x7a,0x91,0xa1,0x0c,
+  0xd3,0x58,0x10,0x7d,0x01,0xf5,0x07,0xa8,0x81,0x7c,0xa5,0x9a,0x46,0x87,0xd8,0xf8,
+  0x51,0x25,0x34,0x04,0xd6,0x22,0x41,0x85,0x20,0xa2,0x79,0x34,0x2e,0x10,0xfd,0x46,
+  0x50,0x03,0x78,0xb7,0x79,0x4a,0xf5,0x08,0xb3,0xfa,0x23,0x3d,0x68,0xe3,0x87,0x77,
+  0x35,0x75,0x68,0x5e,0x22,0x41,0xb5,0x20,0xcc,0x8b,0xb5,0xf0,0xc2,0x26,0x85,0x75,
+  0x68,0x60,0x70,0xc4,0x7b,0x66,0x87,0xf6,0xb4,0xc1,0x0b,0xf1,0x53,0x9a,0x5e,0x7f,
+  0xc4,0x3f,0x79,0xd4,0x04,0x49,0xdd,0x8c,0x78,0x66,0x9d,0x71,0x4f,0xbb,0x37,0xd5,
+  0x16,0xbb,0xc2,0x80,0x87,0x58,0xb9,0x44,0x02,0xaa,0xa6,0x1f,0x67,0xf8,0xe1,0x33,
+  0x7f,0x2b,0x0e,0x95,0xd7,0x1b,0xae,0xad,0x56,0x7c,0x2f,0xd0,0xbe,0x21,0x35,0x16,
+  0xc4,0x4f,0xf8,0x47,0xd1,0x0e,0xb1,0x3a,0x2a,0x94,0xcb,0xf4,0x07,0x48,0x48,0x3f,
+  0x8e,0x9c,0xd7,0x9f,0xc7,0xeb,0xbb,0x77,0x6a,0x67,0x2d,0x20,0xd4,0x3d,0x02,0x29,
+  0xa1,0xf3,0x37,0x8e,0xb3,0xac,0xd6,0xc8,0xe2,0x87,0x73,0xad,0x03,0x86,0x11,0x76,
+  0x2a,0x20,0x83,0x55,0x86,0xb0,0x49,0x94,0x91,0x57,0x99,0x8a,0x37,0xc2,0x49,0xb9,
+  0x5e,0xdb,0x00,0x72,0x93,0xad,0x3e,0x6e,0xbf,0x38,0xba,0xc8,0x13,0xe6,0x63,0x61,
+  0xdc,0xcf,0xdc,0x27,0x54,0x6a,0x94,0xbd,0x1e,0xe6,0xd3,0xc4,0x90,0x09,0x38,0x1a,
+  0xa9,0x25,0xc1,0x91,0x89,0x2f,0x29,0xb7,0x87,0xc3,0xc9,0x58,0xb2,0xa2,0xc6,0xa1,
+  0xc0,0x6e,0xe1,0x33,0x54,0x1f,0x73,0x85,0x3b,0x84,0x4f,0xd4,0xdd,0xcc,0x86,0x9a,
+  0x3a,0x85,0x3e,0xd2,0xa3,0x3b,0x1c,0x69,0xfd,0x2c,0x34,0x03,0x3a,0xb9,0x7e,0xda,
+  0xe1,0xa7,0x32,0x31,0x1a,0x13,0xf6,0x0d,0x70,0xc2,0x5a,0xa3,0x12,0xa8,0x71,0x10,
+  0xac,0x51,0x9e,0xe8,0x47,0xc8,0xad,0xa7,0xf5,0x4f,0x24,0xf2,0x45,0x78,0x35,0x35,
+  0x04,0x64,0x36,0xfc,0x51,0x5c,0x9b,0xec,0xae,0xb3,0x3a,0x26,0xdd,0xbc,0x8d,0x26,
+  0x86,0x50,0xeb,0xa4,0x7b,0x9c,0x2b,0x64,0x4f,0xa6,0x3f,0x36,0xe2,0x9f,0x33,0x29,
+  0x7e,0x78,0x8a,0x1d,0x34,0x23,0x6e,0xd5,0xc7,0x05,0x21,0x3f,0x5e,0x34,0x06,0xef,
+  0xb0,0xd9,0xe6,0x8c,0x98,0x3c,0x90,0xc6,0x27,0x4c,0x89,0x8b,0x4b,0x22,0x98,0x2c,
+  0x68,0x92,0x5f,0xd4,0x7e,0x27,0x6e,0x4a,0xde,0x56,0x57,0x56,0x85,0x1e,0xfd,0x7c,
+  0x62,0x8c,0x57,0x29,0x7f,0xdc,0x56,0x3d,0xe2,0x1c,0x95,0x33,0xf5,0x6b,0x3d,0x25,
+  0x1d,0xfa,0x73,0x25,0x95,0x67,0xb8,0x11,0x4e,0xd5,0xa7,0x6c,0xfc,0x76,0xf7,0x5f,
+  0x27,0xff,0x08,0x37,0xcf,0xc2,0xe7,0xff,0xd1,0xc8,0xb3,0xc3,0xa5,0x4b,0x1c,0x77,
+  0x77,0x3e,0x9d,0xe6,0x87,0x83,0xd8,0x82,0x30,0xc9,0x37,0xe4,0x08,0x51,0x3c,0x99,
+  0xe2,0x3f,0xf7,0x5a,0x81,0x20,0x9f,0xb0,0xf8,0xf0,0xfb,0x24,0xd4,0x60,0x21,0x7b,
+  0x7d,0x9c,0xf2,0x00,0xf4,0x0a,0xdf,0x28,0xf7,0xb2,0xdb,0xe1,0xe1,0xcf,0x95,0x0f,
+  0xe7,0xd5,0xb8,0xdb,0xf8,0x1e,0x03,0x81,0xd0,0x0d,0xec,0xc1,0xe8,0xee,0xf6,0xd8,
+  0x2a,0x87,0xcf,0xa6,0xaf,0x7a,0x66,0xbe,0x0a,0x13,0x66,0xc3,0xaa,0x82,0x5d,0x14,
+  0xf6,0x61,0xc1,0x51,0xdf,0xd6,0xb2,0x2a,0x38,0x12,0xfb,0x62,0x4f,0x65,0xbc,0x68,
+  0x3e,0x7c,0xac,0x05,0x3e,0x5a,0xd2,0x23,0x9f,0xc9,0xcc,0x87,0x95,0x76,0xea,0x13,
+  0xd4,0x94,0xef,0xc7,0xf2,0xae,0xd0,0x3b,0xbc,0x6e,0xa0,0x40,0xeb,0xfc,0x89,0x8e,
+  0x02,0xea,0xf3,0x1d,0x16,0x3f,0x2a,0xe1,0xd2,0xfb,0x63,0x36,0x7e,0xd4,0x5e,0x38,
+  0x15,0x5b,0x98,0x44,0x25,0xf6,0x1d,0xb8,0x2c,0xb9,0x4d,0xe7,0x78,0x8e,0x0f,0x7e,
+  0x26,0x16,0xee,0x74,0xc6,0xe5,0xa0,0xb8,0x0c,0xd5,0x2d,0x9b,0x92,0x72,0x86,0x1f,
+  0xbe,0x0d,0xfe,0x1b,0xc4,0xb8,0xc7,0xe4,0x3e,0xf5,0x6b,0x70,0xa0,0xb0,0x62,0x90,
+  0x1f,0xdc,0x9e,0x0b,0xcf,0x00,0x7e,0x68,0xcf,0x33,0x1f,0x47,0xc5,0x18,0xa2,0x46,
+  0x5b,0xf6,0xfe,0x00,0x85,0x5b,0x61,0x6e,0x22,0x6f,0x97,0x63,0xa5,0x71,0x80,0x68,
+  0x4e,0x7d,0x6c,0x97,0xd1,0xad,0x7b,0x04,0xdf,0x8a,0xd7,0x1f,0x10,0x56,0x3f,0xc3,
+  0x10,0xee,0x9a,0xa9,0xdf,0x57,0x51,0xb4,0xcd,0xd4,0x2f,0x5a,0xb7,0xfa,0x03,0xf4,
+  0x98,0x7d,0x7e,0x47,0x04,0x3a,0x21,0xd6,0x81,0x18,0xc1,0xd9,0xb1,0x87,0x95,0x1b,
+  0xaa,0xee,0x68,0xca,0xf0,0xc3,0xf3,0x97,0x23,0xfa,0xaa,0x35,0xf3,0x09,0x7d,0x11,
+  0xdb,0xf6,0xf6,0x38,0xfb,0xf1,0xf6,0xf7,0x11,0x0f,0xe3,0xf7,0xe5,0x8b,0x5d,0x94,
+  0x16,0x18,0xae,0x98,0x6c,0x64,0xe2,0x3f,0x3f,0xfc,0x43,0x6c,0x0c,0x1a,0x07,0x96,
+  0x26,0x2d,0xff,0xfd,0x7a,0x9a,0x6f,0xb5,0x0a,0x5e,0x92,0x1a,0x25,0x97,0x29,0x9d,
+  0x83,0x0b,0x5a,0x23,0xd5,0x03,0xf6,0xd8,0xe6,0x6b,0x5c,0x6a,0xbf,0xdc,0xd9,0x38,
+  0xb2,0xf2,0x39,0xaa,0x86,0x2b,0xac,0x1e,0xc9,0x5f,0x5d,0xd4,0x08,0xc7,0xcc,0x3d,
+  0x83,0xbb,0x26,0x9b,0xeb,0x8d,0x63,0x75,0xd5,0x23,0xae,0xf3,0xf6,0xf9,0xb0,0x25,
+  0x43,0x5d,0x7b,0xbc,0xbe,0x04,0x3f,0xcb,0x7c,0xe2,0x99,0x50,0x45,0x02,0x7a,0x07,
+  0x7c,0xa2,0x53,0x47,0xc4,0x12,0x6f,0x8a,0x28,0xcf,0xa4,0xa8,0xe0,0x59,0xfc,0x70,
+  0x61,0x4d,0xa7,0x0a,0x20,0x9e,0xe9,0x0c,0x41,0x82,0xfa,0x6f,0xe4,0x76,0x82,0xf7,
+  0x64,0xc9,0x66,0xe6,0x7c,0xa0,0x53,0xd7,0x4d,0x35,0xc0,0xc2,0x99,0xf8,0x4f,0xce,
+  0x2e,0xe9,0x80,0x64,0xf5,0x07,0xf0,0xb5,0x3e,0x03,0xba,0x59,0x5f,0x67,0xf5,0x07,
+  0xc0,0x5f,0xa4,0x87,0xfd,0x54,0xdf,0x41,0x85,0x87,0x71,0x16,0xcf,0xd4,0x6f,0x52,
+  0x7f,0x80,0xd4,0x58,0x58,0x82,0x85,0xbd,0xc9,0xd9,0x07,0x1f,0x46,0xe1,0xa1,0x80,
+  0xb9,0xa1,0x4e,0xae,0xe2,0x8b,0x53,0xf3,0x49,0x85,0xbd,0x3f,0xc0,0x54,0xfc,0x47,
+  0x9d,0xe4,0x17,0xa1,0x31,0xb1,0x71,0xdc,0x75,0xa9,0xe5,0xb2,0xd5,0x51,0x4a,0x3e,
+  0xa7,0x7c,0x37,0x15,0x1a,0x5a,0x9d,0x85,0x7f,0x7e,0xad,0xd5,0x9a,0xb7,0x2d,0x68,
+  0xfe,0x1a,0xd0,0xa0,0xba,0x86,0xe8,0x0c,0xdf,0x2b,0x24,0xe4,0xa7,0xfe,0x8b,0x7f,
+  0x32,0x1f,0x16,0x7d,0x85,0x76,0xcf,0x09,0x3e,0xc1,0x2a,0x95,0x97,0xda,0x3d,0xe7,
+  0xf2,0xbe,0x17,0xae,0x84,0x03,0xcb,0xbe,0x34,0xec,0x38,0xe0,0x99,0x6f,0xbc,0xf5,
+  0xb9,0xda,0x3f,0x6c,0x7c,0x36,0x3b,0xff,0x05,0x0f,0x8b,0xb9,0x23,0x79,0x01,0xcf,
+  0x4a,0xfd,0x40,0xa1,0x6e,0x4a,0x75,0xf8,0xe1,0x1c,0xd8,0xe2,0x99,0xfc,0x6c,0x0d,
+  0x2b,0xe7,0x3b,0x34,0x3d,0xd9,0xba,0x1f,0xb2,0xfa,0x23,0xc1,0x23,0x84,0x07,0xea,
+  0xd9,0x17,0x8d,0x7d,0xe2,0xee,0xb7,0xf3,0x26,0xd8,0x17,0x61,0x5f,0x57,0xe9,0xa8,
+  0x3a,0xe1,0xb8,0x0a,0xf6,0x89,0x2f,0x27,0xf3,0xbe,0x05,0x77,0xda,0xe2,0x3f,0x4e,
+  0xf8,0x25,0xd4,0x98,0xf9,0xf5,0xf2,0x12,0x83,0xd0,0xb2,0xc5,0x97,0xde,0x03,0xfa,
+  0x68,0x7e,0x49,0x91,0x53,0x7f,0x5f,0xf7,0x0f,0x3a,0xfd,0x7f,0x66,0xef,0x8f,0xb4,
+  0x0b,0x7e,0xa7,0x5d,0x37,0x38,0xe3,0xac,0xbc,0xab,0xf5,0x72,0x49,0x23,0x15,0xfe,
+  0x1f,0xb4,0x18,0x77,0xeb,0x43,0xd4,0x71,0x9d,0x13,0x83,0xb1,0xd9,0xde,0x1f,0x89,
+  0xd4,0x54,0xbd,0xe9,0xdc,0xd7,0x59,0x35,0x35,0x0d,0xb6,0xec,0x43,0x14,0xbe,0xd3,
+  0xbf,0x34,0xfa,0x25,0x6a,0x94,0x4d,0xfd,0x91,0xfe,0xa4,0x3f,0x40,0x99,0xc9,0x3f,
+  0x72,0xcc,0x62,0x9b,0xf4,0x52,0xb3,0x79,0x15,0x9b,0xa4,0xc0,0xf2,0x49,0x9a,0x37,
+  0x0d,0x3f,0xcb,0x29,0xed,0x57,0xc7,0x59,0x6f,0x56,0x7f,0x00,0x74,0x33,0x53,0xf8,
+  0x67,0x2d,0xbe,0x78,0xe7,0xea,0xf0,0x9b,0xe5,0x6b,0x45,0xfe,0x7b,0xdd,0x27,0xaf,
+  0x0e,0x52,0xa9,0x32,0x85,0x86,0xfc,0xe9,0xf8,0x4f,0x6b,0xf1,0x10,0x9f,0x8a,0x1f,
+  0xe6,0x52,0x20,0x91,0xf4,0xf9,0xab,0x80,0xfa,0xdc,0xbc,0xe6,0x66,0xea,0x4f,0x92,
+  0x1a,0x5d,0xb4,0xd9,0xde,0x1f,0x00,0xf5,0x6d,0xbd,0x40,0x27,0xab,0x42,0x1c,0x86,
+  0xde,0x58,0xaa,0x3f,0x00,0x47,0xe0,0x77,0x1a,0x1d,0xa5,0x33,0xa8,0xcc,0xf0,0xfb,
+  0xca,0xee,0x0f,0x40,0xf5,0x2c,0xf3,0xa7,0xc2,0x3e,0x0a,0xf5,0x07,0x98,0xee,0x8f,
+  0xf4,0x4e,0x2a,0x10,0xf4,0x2f,0xcd,0x87,0x5d,0xa2,0x15,0x95,0xf3,0xf3,0xd3,0x8d,
+  0xb2,0xad,0xfe,0x00,0x51,0x75,0x0e,0x1c,0xb2,0xf2,0x23,0xcc,0xc6,0x0f,0x87,0xd4,
+  0x7c,0x58,0x6f,0x8a,0x66,0x9c,0x6a,0x94,0x6d,0x09,0x4e,0xcd,0x73,0x7d,0x78,0x9d,
+  0xb9,0x7d,0x95,0x37,0x6b,0x3e,0x6c,0x8e,0x22,0x4d,0x35,0x4d,0x1a,0x49,0xd1,0x50,
+  0xb5,0xdc,0x72,0x4b,0xb0,0xea,0xe3,0x3a,0x34,0xbd,0x05,0xfd,0xa9,0x07,0xfe,0xb4,
+  0x3f,0x40,0x8a,0x16,0xae,0x1b,0x9f,0xb6,0xfa,0x03,0x48,0x7a,0x1b,0x5d,0xaf,0x74,
+  0x5a,0xa5,0x73,0xf8,0x3d,0x4e,0xef,0x87,0x74,0x7f,0x80,0x70,0x91,0x80,0x3e,0x3d,
+  0x60,0x0d,0xaa,0x80,0xa9,0xb0,0x8f,0x35,0xa8,0x42,0xa0,0xf0,0x53,0x7b,0x7f,0x80,
+  0xd8,0x79,0x5f,0x90,0x9a,0x00,0x7c,0x83,0xca,0xe2,0x16,0x17,0x1c,0x7f,0x98,0xc2,
+  0x3e,0x55,0x6d,0x3f,0x5d,0xd6,0x79,0x22,0x7e,0x9e,0xf8,0xe1,0x9b,0x5f,0xfe,0x4a,
+  0xd6,0x7c,0x58,0xaa,0xaf,0x77,0x51,0xfc,0xe7,0xbc,0x3f,0x68,0xc1,0x06,0xa3,0x1f,
+  0x6a,0x29,0xfe,0x93,0x9a,0x0f,0x6b,0x05,0x46,0x32,0xf8,0x27,0x69,0xc5,0x7f,0x54,
+  0xd6,0x09,0x11,0xe1,0x9f,0xaa,0x8f,0xeb,0xf1,0x56,0x71,0x6f,0xb8,0x49,0xf7,0x44,
+  0x78,0x6d,0xaa,0x3f,0x40,0x46,0xff,0x9c,0xb0,0xe2,0x3f,0xea,0xe7,0xdd,0x35,0xb1,
+  0x27,0xf4,0xca,0xd6,0xbc,0x76,0x77,0x31,0xac,0xd1,0x2b,0xdb,0x38,0x22,0x2e,0xb1,
+  0xc6,0x5d,0x6a,0x74,0x2f,0xb3,0xcf,0x47,0xcb,0x49,0xc5,0x7f,0xd4,0x76,0x56,0x43,
+  0x42,0xeb,0xbc,0xe3,0x4d,0xc5,0xc6,0x4f,0xac,0x88,0xd0,0xd5,0x35,0xa1,0x8d,0x70,
+  0xfd,0x15,0xfd,0x01,0xb4,0x9d,0x2c,0x35,0xff,0x45,0xcd,0xa5,0xc0,0x0e,0xa2,0xd3,
+  0x75,0x54,0xd6,0x57,0x6b,0x38,0xbf,0x2f,0xcf,0x61,0x87,0x72,0xad,0x41,0x69,0x99,
+  0xfa,0xb8,0x1e,0xd8,0x39,0x05,0x0b,0x11,0x06,0x5b,0xfd,0x91,0x2c,0x7e,0xf8,0x43,
+  0x0d,0x86,0xeb,0x71,0x79,0x0a,0x08,0x5d,0xd1,0x1f,0x60,0xba,0xfb,0xe8,0x2a,0x38,
+  0xc5,0xaa,0xc1,0x35,0x48,0xfd,0x01,0xa0,0x9a,0x1a,0x65,0xfb,0xa9,0xbe,0x9b,0x4e,
+  0xd9,0xf8,0xe1,0x8a,0x57,0x9c,0xd1,0xab,0x22,0xea,0x76,0xf9,0xef,0x10,0xf6,0x58,
+  0x81,0xa0,0x51,0x58,0xaf,0x7b,0xfa,0x78,0x15,0xf5,0x07,0x00,0xf4,0x1f,0x93,0x59,
+  0xfc,0xf0,0x2f,0x89,0x58,0xd2,0x57,0xa7,0x16,0x30,0x43,0x44,0xc1,0x43,0xfe,0x9a,
+  0xa9,0x08,0xa1,0x73,0x8e,0x28,0xc9,0x22,0x32,0x74,0xdb,0xfb,0x03,0xe8,0xd4,0x1f,
+  0x20,0xd5,0x0d,0xe0,0x2e,0xfa,0x1e,0xcd,0x6b,0x56,0xe5,0x4e,0xb2,0x4d,0xc2,0xaa,
+  0x78,0x6d,0x80,0x1d,0xf0,0x14,0x9e,0x82,0x4c,0xfc,0xc7,0xcb,0xa9,0x3e,0xee,0x66,
+  0xdd,0xd5,0x2a,0x2f,0x83,0x13,0x62,0xb7,0xae,0xb6,0xca,0xc7,0x95,0x41,0xb1,0x47,
+  0x5f,0xd2,0x8a,0x88,0x88,0x26,0xc6,0xe2,0xa9,0xac,0xfe,0x90,0xda,0xfb,0xe9,0xfa,
+  0xf7,0x54,0xbe,0xc3,0x02,0x42,0xfd,0x16,0xed,0x39,0x71,0xe5,0x7c,0x58,0x23,0x67,
+  0xd2,0xb8,0x9c,0xaa,0x86,0xbb,0x64,0x4d,0x83,0xb5,0xda,0x02,0xbc,0x99,0x1a,0x6b,
+  0x45,0x83,0x62,0x17,0xe8,0xce,0x75,0xf6,0xf8,0x4f,0xe1,0x66,0xb1,0x17,0x2a,0x41,
+  0x35,0xdd,0xcb,0xe0,0xb7,0xd4,0xcd,0xfb,0x42,0xdb,0x2c,0x78,0x56,0xf3,0x41,0x81,
+  0xea,0xa0,0xd0,0xf4,0x3c,0xb3,0xed,0xbe,0xec,0xfe,0x00,0x62,0x5f,0xea,0x7d,0x1f,
+  0x47,0x28,0x51,0x66,0xd1,0x9b,0xf4,0xe7,0xac,0x7e,0x6e,0x16,0x02,0xc4,0x17,0x6f,
+  0xb3,0xc5,0x7f,0x42,0xc5,0x26,0xfa,0xef,0x3e,0x8a,0xff,0x34,0x29,0x3b,0x2c,0x45,
+  0xe4,0xae,0x82,0xfd,0x62,0x25,0xac,0x17,0xe8,0xe6,0x53,0x07,0x06,0xb4,0x80,0x6f,
+  0xd8,0xe6,0xa3,0xa5,0x87,0x0a,0x85,0x85,0x35,0x6d,0x7c,0xb7,0x5c,0x05,0xaf,0xc7,
+  0xf0,0xc8,0x83,0xb2,0xc7,0x6a,0x04,0x8a,0xaa,0xe9,0x8d,0xac,0xfe,0x00,0x17,0xa7,
+  0xd7,0x67,0xd4,0x08,0xfa,0xad,0xfe,0x6c,0x17,0x0c,0x6b,0x30,0xf7,0xd4,0x29,0xdc,
+  0x5a,0xb6,0xfe,0x00,0xe8,0xa6,0x29,0xd5,0xd4,0xcf,0x76,0x15,0x3b,0x12,0x6d,0x1c,
+  0x99,0x71,0x5e,0xbe,0x64,0xbc,0x46,0x63,0xd1,0x4c,0x47,0x43,0x8a,0x31,0x9e,0x94,
+  0xc7,0xd3,0xcf,0xd3,0xa1,0x50,0x5b,0x24,0xe2,0x87,0x37,0xf9,0x20,0x62,0x56,0xf9,
+  0xaf,0xdb,0xc0,0xde,0x61,0xeb,0x0d,0x9a,0xf7,0x2a,0x1b,0x04,0x45,0x24,0xaa,0xcf,
+  0xb5,0xe1,0x9f,0x95,0xa9,0xa6,0xcd,0xf1,0xdc,0x95,0xd0,0x9d,0x5f,0x35,0xa0,0xc6,
+  0xc3,0x63,0xde,0x6e,0x6e,0x15,0x76,0xc5,0xc0,0xda,0x51,0xdb,0xed,0xf9,0x2f,0xfc,
+  0x27,0xe4,0x96,0xaa,0x8a,0xc5,0x7e,0xf1,0xd1,0x3c,0x62,0x53,0x12,0x52,0x0c,0xb8,
+  0xc4,0xc6,0x94,0x87,0xa9,0x3f,0xb6,0xdb,0x9e,0xff,0xe2,0x68,0x16,0xc9,0xac,0xec,
+  0xa5,0xf9,0x53,0xd4,0x26,0xa2,0x97,0x59,0x8d,0x68,0x06,0x7d,0x34,0x11,0xec,0x97,
+  0x74,0x6a,0xbb,0x9c,0xb4,0xe5,0xbf,0x92,0xd3,0x4d,0x9e,0x93,0x86,0x15,0xed,0xe9,
+  0x2a,0x1b,0x87,0x83,0xd0,0xc8,0x67,0xbc,0xcc,0x56,0xe1,0x52,0xe0,0xa9,0x5f,0x64,
+  0xf7,0x47,0xc2,0x4d,0xd2,0x08,0xce,0x8f,0x8a,0xea,0x8d,0x21,0xca,0x7f,0x45,0xe4,
+  0x6a,0x98,0x8c,0x56,0x97,0xe6,0xd3,0xa0,0x99,0x41,0xdc,0xba,0xf9,0x1f,0x65,0xf5,
+  0x07,0xf8,0x10,0xfa,0x44,0x55,0x88,0xaf,0x43,0xfc,0xd3,0x83,0x6f,0xe7,0x88,0x51,
+  0x7d,0x0a,0x54,0xe8,0x7c,0x73,0xf8,0x2b,0xb0,0x7e,0x4d,0x95,0x4e,0x2f,0x6e,0xc7,
+  0x3f,0xd4,0x2f,0xc2,0xc0,0x1f,0xdd,0x8b,0x5f,0x95,0x97,0xf3,0xb0,0x43,0x11,0x7d,
+  0xba,0x17,0xf2,0xdc,0x6c,0x48,0xee,0x84,0x95,0x90,0x57,0xc3,0xb2,0xfa,0x23,0x71,
+  0xba,0xbf,0x43,0x30,0x1f,0x2a,0x8b,0x0a,0x70,0xec,0xb4,0x06,0xef,0x56,0x30,0xd4,
+  0xcf,0x2b,0x35,0x1a,0xc5,0xd2,0x7a,0x25,0xfe,0x99,0x10,0xbe,0x64,0xc1,0x73,0xaa,
+  0x17,0xad,0xc9,0xf3,0x06,0xa7,0xb6,0x12,0x67,0xa1,0xae,0x26,0x7f,0xaf,0xfc,0xae,
+  0x71,0x44,0x04,0x63,0x1b,0xe3,0x32,0x64,0xf8,0x1e,0x88,0x7f,0x26,0x71,0x93,0x54,
+  0x12,0x3e,0xfc,0x24,0xba,0xb0,0x1d,0x7f,0xfd,0x8f,0x8c,0x4f,0x62,0xdf,0xa5,0xb6,
+  0x51,0x7f,0x80,0xcb,0x66,0x63,0xd8,0xe5,0x97,0x27,0xb2,0xeb,0xe3,0x3a,0x82,0xa6,
+  0x6f,0xaf,0xbc,0x02,0x0e,0xc5,0x02,0x46,0x7e,0x97,0xfc,0x15,0xaa,0xd7,0xd0,0x9c,
+  0x7b,0x55,0x1f,0xfc,0xda,0x4f,0x13,0x69,0xb3,0xfa,0x43,0xfa,0x68,0x7d,0x4c,0xf0,
+  0x22,0x6c,0x23,0xff,0x1d,0x81,0xee,0xdc,0x9c,0xfd,0x50,0x00,0xde,0xb8,0xdb,0x19,
+  0xe9,0x56,0x74,0xe1,0x1c,0xcf,0xea,0x0f,0xb9,0x84,0xd6,0x87,0xf8,0x2a,0x9f,0x15,
+  0xeb,0x17,0x31,0x91,0xa7,0xb1,0x56,0xe8,0x05,0xdf,0xdb,0xa8,0x80,0x14,0xd8,0x6c,
+  0x7a,0x85,0xe3,0x8a,0xfe,0x90,0xb0,0x37,0x5a,0x39,0xca,0x4b,0x10,0x0f,0x3c,0x10,
+  0x2b,0xdd,0xc5,0xbf,0xcd,0xae,0x86,0xe7,0xc4,0x57,0xdf,0x2e,0x69,0x45,0x7f,0xff,
+  0x47,0xd1,0xeb,0x63,0x7c,0x75,0x6e,0x89,0x8d,0xff,0x53,0x60,0x8c,0x4b,0x0d,0xc3,
+  0xb8,0x5b,0x56,0xc0,0x61,0xd1,0xdb,0x93,0xff,0x03,0x79,0x09,0xde,0xbf,0x61,0xd0,
+  0xd9,0xf5,0x32,0x42,0xa3,0x58,0x9d,0x96,0x5d,0x1f,0x77,0xed,0x41,0x31,0x09,0x55,
+  0x89,0x4d,0xc3,0xd2,0x18,0xbb,0x04,0x8d,0x5d,0x6a,0x5c,0x9e,0x34,0xbe,0x23,0x35,
+  0x0c,0x2e,0x4d,0x14,0x11,0x55,0xec,0x26,0x5c,0xa8,0xce,0x4c,0xfc,0x07,0xf1,0x0f,
+  0x37,0x85,0x3f,0x49,0x61,0x37,0xa0,0xfe,0x54,0xa8,0xbd,0x57,0xc0,0xfb,0xc2,0x6a,
+  0xdb,0x5e,0x0e,0x1f,0xa7,0x02,0xd7,0x7f,0x9b,0xd5,0x1f,0x7b,0x2d,0xdc,0x90,0x0a,
+  0x23,0x53,0xd8,0x3c,0xb2,0xca,0x51,0x62,0x55,0x1c,0xa3,0x5a,0xa6,0xd1,0x69,0x56,
+  0xbf,0xd9,0x4c,0x7f,0xa4,0x7e,0xc4,0x3f,0x5d,0x66,0xd9,0xdb,0x8e,0xd5,0xe1,0x37,
+  0xac,0x68,0x8f,0x83,0xe6,0x2b,0xad,0xed,0xfa,0x72,0x72,0xf1,0x4a,0x63,0x36,0xbc,
+  0xd4,0xb1,0x2d,0x76,0x4d,0x1d,0x6e,0xec,0xe9,0xf5,0x6f,0xdd,0x32,0xc4,0xc3,0xc9,
+  0xf2,0x71,0x4a,0xeb,0x3b,0x3a,0x59,0xf9,0x71,0x2b,0x7f,0xda,0x69,0xe8,0xe6,0x5f,
+  0x51,0x04,0x0c,0x81,0x5f,0xe4,0x9a,0x78,0x56,0x7f,0xa4,0xc8,0x55,0x47,0xcd,0xea,
+  0x78,0x01,0xc2,0x1e,0x38,0xbc,0xe8,0xb9,0x68,0x41,0x4c,0xf6,0xb2,0x33,0x1a,0x3e,
+  0x76,0x8f,0xec,0x15,0x7f,0x30,0x16,0xc4,0xf0,0x45,0xee,0xcb,0xe0,0x1f,0x23,0xa9,
+  0x4d,0x48,0x41,0x6e,0x45,0x17,0x27,0x1c,0x34,0x1f,0x56,0x8e,0x39,0x27,0x94,0xef,
+  0x68,0x56,0x47,0xf1,0x09,0xad,0xbe,0x78,0xe9,0x9f,0xe0,0x1f,0x23,0xf8,0x65,0x97,
+  0x5b,0xa6,0x69,0x59,0x05,0x34,0x0f,0x7d,0xae,0x38,0x04,0x55,0x08,0x7b,0xf8,0x4e,
+  0x38,0xe4,0x0d,0x50,0x7f,0x48,0x56,0x9c,0xc9,0x7f,0x7d,0xa5,0xe5,0x29,0xa8,0x5a,
+  0x84,0x4a,0xa6,0x5c,0x5a,0xb7,0xa8,0x2a,0xd4,0xad,0xb1,0x27,0xe0,0x75,0xd9,0xd7,
+  0x7e,0xed,0x16,0x96,0x03,0xeb,0x94,0xfa,0x76,0xab,0x3e,0x6e,0xfa,0x7a,0xea,0x8f,
+  0x4d,0xd9,0x2e,0x35,0xca,0x5a,0xc2,0x68,0xaf,0x9b,0xd0,0x3a,0x7f,0xa3,0x78,0xa3,
+  0x34,0xff,0x96,0x92,0x76,0x62,0xe8,0x51,0xeb,0x80,0x28,0xcb,0x34,0x50,0x20,0xfc,
+  0xb3,0x0d,0x7c,0x34,0x04,0x56,0x81,0x35,0xe2,0xab,0x64,0xcd,0x7f,0x05,0x33,0x89,
+  0x38,0x74,0x27,0x23,0x28,0x55,0x41,0xd0,0xa8,0x29,0xad,0x7f,0xfa,0x2c,0xfc,0x13,
+  0xe4,0x6a,0x18,0xb5,0x9f,0x80,0x06,0x54,0xd4,0x0e,0x03,0x8f,0x54,0x09,0x6e,0x16,
+  0x79,0xd1,0x90,0x06,0xac,0xf9,0x20,0x2c,0x8d,0x7f,0xf2,0x07,0xe1,0x13,0xa9,0xd1,
+  0x98,0x31,0x2c,0x5b,0xdd,0xb0,0xdb,0x5c,0xee,0xce,0x72,0xab,0x2d,0x36,0x21,0x22,
+  0xf8,0x04,0x6e,0x32,0xd4,0xcd,0x0f,0xbf,0x3b,0x23,0x9d,0x6f,0xb2,0xe6,0xc3,0xde,
+  0x94,0x6a,0x0b,0xf9,0x09,0xdc,0xdc,0x32,0x2b,0x4a,0xfd,0x21,0xb5,0xc6,0x45,0xae,
+  0x61,0xf9,0x04,0xbc,0x42,0xa3,0x0d,0x1e,0xca,0xe2,0xff,0x50,0x91,0xb2,0x07,0x15,
+  0x35,0x4b,0xf6,0xf4,0xe9,0x55,0xfc,0x2f,0x45,0x78,0x54,0xef,0xa1,0x8c,0x03,0x43,
+  0x35,0x4b,0x1a,0x23,0xd2,0x91,0x3d,0x1f,0x4d,0xd9,0x0f,0x15,0xcb,0x11,0xd4,0xd1,
+  0x7c,0x34,0x5f,0x6b,0xab,0x9b,0xfa,0x43,0x52,0x99,0x12,0x21,0x40,0x2b,0x15,0xa8,
+  0x65,0xcf,0x87,0x55,0xf6,0x1b,0x8c,0xb2,0x8d,0x23,0xb0,0x5f,0xf2,0x19,0xad,0x51,
+  0xbc,0xfe,0x29,0x85,0x56,0x38,0x77,0x04,0x9e,0x8a,0x54,0x0c,0xf0,0xac,0xf9,0xb0,
+  0x33,0x97,0xa3,0xb6,0xb9,0xba,0xdd,0xca,0x76,0x51,0xd9,0x23,0x02,0xd7,0xdf,0x40,
+  0x7a,0x22,0x5e,0xbf,0xe1,0x6f,0xcf,0xa7,0xfe,0x48,0xd3,0xfb,0xd3,0xea,0x8f,0x24,
+  0x4d,0x8f,0x05,0x81,0x2b,0x04,0x83,0x3a,0x0c,0x58,0xf8,0x67,0xfa,0x7a,0xaf,0x16,
+  0x93,0x12,0x30,0x9b,0xfa,0x53,0xe9,0x12,0x19,0xca,0x25,0xa2,0xf9,0x34,0x23,0x18,
+  0x90,0xc2,0x9f,0xfc,0x39,0x2a,0x5d,0x74,0xd8,0xf8,0x3f,0xf5,0x08,0x7b,0x2a,0x7b,
+  0xbc,0x31,0x54,0x1a,0x2f,0xb2,0xff,0x2e,0x9c,0x14,0xf6,0xa1,0xf8,0x4f,0x7e,0x52,
+  0xfe,0x4b,0xf8,0xa9,0x59,0x4d,0xa3,0x43,0xf8,0xf4,0xe5,0xe0,0x5d,0x73,0x2b,0xd1,
+  0x7e,0x4c,0x5e,0x97,0xeb,0x54,0xc8,0x51,0xcd,0x23,0x3e,0x4c,0x27,0x2c,0x19,0xe2,
+  0x9a,0x7b,0x89,0x1f,0x3d,0x88,0x73,0xe8,0x2f,0xd8,0xfb,0x43,0x5e,0x05,0x4f,0xc0,
+  0x7c,0xb3,0xe7,0xfe,0xab,0x4a,0xe0,0x59,0x14,0xf2,0x56,0xb1,0x13,0xb0,0xd6,0x3d,
+  0x3f,0xf9,0xd9,0xd5,0x9e,0xff,0xaa,0x3c,0xc1,0x4b,0xcd,0xc5,0x75,0x8c,0xa7,0xf1,
+  0x4f,0x0f,0xbf,0x8a,0xad,0xa1,0x69,0x68,0x75,0xea,0x55,0xf0,0x5c,0x47,0x65,0xb2,
+  0xf2,0xbe,0xa6,0x0b,0x14,0xff,0xa1,0xb4,0xd7,0x17,0xe1,0xe7,0x5d,0x0b,0xa8,0x51,
+  0xb6,0x23,0x83,0x7f,0xae,0xed,0xd2,0xac,0x30,0x7b,0x1c,0x1d,0x0d,0x1a,0x0b,0xfb,
+  0x60,0xbc,0x6c,0xd4,0x4a,0xa3,0xab,0x31,0x79,0x2c,0xf7,0xf5,0x54,0x69,0x7c,0x06,
+  0xff,0x98,0x39,0x7f,0x90,0x3e,0xd1,0x1a,0x93,0xbe,0x89,0xe6,0x4b,0xc6,0x5b,0x16,
+  0x10,0xea,0xbc,0x04,0x97,0xd1,0xd0,0x3b,0xb7,0xca,0xc7,0xdd,0xbf,0xb5,0x4a,0xe7,
+  0xec,0xf5,0x71,0x85,0x5b,0xa4,0xdf,0x40,0xe5,0xa8,0x77,0x15,0x62,0x8b,0x6d,0x50,
+  0x75,0x0e,0xf5,0xe7,0x3f,0x46,0xf7,0x81,0xeb,0x09,0xc7,0xb7,0xd9,0xb0,0xde,0x11,
+  0x28,0x35,0xbd,0xe3,0xec,0xe9,0x34,0xfe,0xa4,0xfe,0xd8,0x4f,0x68,0x95,0x09,0xbe,
+  0x2a,0x7c,0x42,0x7b,0x00,0xe6,0xf7,0x3b,0xbe,0xbe,0xf9,0xa4,0xb2,0x4f,0x72,0x25,
+  0x54,0xea,0x30,0xf0,0x24,0xbb,0x9b,0x54,0x59,0x66,0x3e,0xac,0x5e,0x3c,0x04,0xdb,
+  0x0c,0xdf,0x00,0x6f,0x60,0x06,0x6d,0x33,0xb3,0xb5,0x0f,0x7f,0xad,0x3d,0x50,0x2e,
+  0xd4,0x5d,0xe1,0xa3,0x7c,0x47,0x47,0x6c,0x18,0x57,0x78,0x6b,0x7a,0x7f,0xae,0x98,
+  0x59,0x0e,0xef,0xbc,0xdd,0x60,0x3a,0xf7,0x16,0x91,0x59,0x6f,0x80,0x82,0x89,0xa6,
+  0x31,0xed,0x8f,0x92,0x85,0x67,0x8e,0xc2,0xfb,0xb1,0x00,0x51,0x73,0xed,0xf3,0x61,
+  0x47,0xf8,0x7b,0x29,0xfc,0x33,0xa6,0xbf,0x2f,0x05,0x01,0x15,0xef,0x6f,0xa4,0x6f,
+  0x53,0x63,0xe4,0xbd,0x88,0x7f,0xfe,0xca,0x08,0x0e,0xe3,0x8a,0x65,0xfa,0x23,0x99,
+  0x1a,0x7e,0x56,0xfc,0xf3,0xc9,0xfc,0x55,0x9d,0x41,0x71,0x49,0xa4,0x88,0xbe,0xfc,
+  0x32,0xdc,0x74,0x1a,0xed,0x5d,0x03,0x3b,0x26,0x8a,0x06,0x5c,0xab,0x58,0xd6,0x7c,
+  0x10,0x44,0x6b,0xf7,0x98,0x7c,0xbf,0xdb,0x07,0x07,0x36,0x7b,0x86,0x11,0xf6,0x7c,
+  0x40,0x13,0x6c,0xdb,0xd5,0x17,0xc2,0xf3,0xa1,0x23,0x16,0x48,0x2e,0x8e,0xa3,0xbf,
+  0x99,0xc1,0x3f,0xe5,0x70,0xc0,0x53,0xd5,0x32,0x2f,0xee,0xf6,0xe9,0x7b,0x24,0x8f,
+  0x52,0x32,0x55,0xcf,0x7e,0x42,0x8d,0xb3,0x2a,0xbd,0x5b,0xaf,0x0a,0xa1,0xbe,0x8d,
+  0x65,0xea,0xe3,0x14,0xc5,0xd8,0x0f,0x73,0xa9,0xe9,0xba,0x53,0xda,0x03,0xf7,0xf0,
+  0x15,0x71,0x4f,0x97,0x76,0x00,0xca,0x07,0x54,0x7f,0x93,0xc2,0xc3,0xd0,0x63,0xa8,
+  0x7e,0x47,0xb8,0x78,0x7a,0xf5,0x45,0x3e,0x55,0xc3,0x51,0xda,0xcb,0xe1,0x53,0x2e,
+  0xb4,0x07,0xfe,0xd1,0xf9,0x1c,0xde,0x1f,0x81,0x22,0x77,0xf5,0x3a,0x7c,0x70,0xa4,
+  0x9d,0x3a,0xa8,0x97,0x89,0xdc,0xe9,0xe7,0xa1,0xfe,0x90,0xff,0x00,0xfe,0xc1,0xf9,
+  0xc3,0x14,0xff,0xd1,0x83,0x83,0x33,0x9e,0xfb,0x25,0x0a,0x68,0x1a,0x5d,0xe7,0xf0,
+  0xc8,0x25,0x58,0x40,0x86,0x7e,0x45,0x3a,0x1e,0x32,0x90,0xf3,0x21,0xbf,0x2c,0x16,
+  0x26,0x9c,0xd4,0xfd,0xe6,0x25,0x51,0x7d,0xda,0x95,0x40,0x20,0x7d,0xd9,0xb3,0x30,
+  0x99,0x3f,0xa1,0x36,0x18,0xc7,0xc4,0x42,0xdd,0x39,0xf1,0xa5,0x71,0x5b,0xfe,0xeb,
+  0x43,0x38,0x20,0xea,0xc7,0xf9,0x0b,0xee,0x0f,0xcc,0x9b,0x44,0x6d,0x52,0xa5,0x31,
+  0xb8,0x37,0x99,0x1e,0xd3,0xb1,0xd5,0xfd,0x13,0xb2,0xf8,0x21,0x47,0x1f,0x1b,0xb7,
+  0xf3,0x7f,0x94,0x3d,0xcc,0x37,0x7c,0x18,0x3f,0x2b,0xfc,0xbe,0xc0,0xb4,0xe6,0x7f,
+  0x3d,0x6c,0xcc,0xa5,0x46,0x2e,0xf9,0xd1,0x6e,0x56,0x6e,0x44,0xfc,0xec,0xa3,0x0c,
+  0xfe,0x51,0xd2,0xfd,0x21,0xc7,0xe0,0x80,0x36,0x97,0xa6,0xcd,0x8e,0x49,0x8f,0x81,
+  0x27,0xc9,0xfa,0x1c,0xbb,0x58,0xb7,0xf0,0xb4,0x3b,0xec,0xfd,0xb1,0x17,0x59,0xfd,
+  0x21,0x6b,0x4d,0x67,0xbc,0x68,0x8c,0xda,0x36,0xf6,0x23,0xec,0xa7,0x23,0x35,0xa3,
+  0x95,0x75,0xb2,0xcf,0xf9,0x72,0xb2,0xf6,0x8e,0x0d,0x34,0xbf,0x23,0xf3,0xfd,0x52,
+  0xfc,0xe7,0x46,0x73,0x7e,0xbc,0xcc,0xe2,0x47,0x25,0xd3,0xfd,0x91,0xfe,0x2c,0x15,
+  0x31,0x7b,0xe9,0x9e,0x2b,0xe7,0xc3,0xa6,0x40,0x75,0x1f,0xb5,0xdd,0x86,0xef,0x0c,
+  0x5a,0xf5,0x98,0x14,0xf1,0x28,0xa0,0x23,0x47,0x4a,0x02,0xed,0xce,0xb8,0x7c,0xd6,
+  0x96,0xff,0xa2,0x5f,0x7f,0x7e,0x52,0x45,0x6f,0x48,0xe9,0xbc,0xb3,0xca,0x2a,0x9c,
+  0xd4,0xf7,0x09,0x8f,0xc8,0xef,0x93,0xef,0x87,0x6e,0xd3,0x7b,0x4f,0x7e,0x9c,0xfd,
+  0x21,0x8b,0xff,0xf3,0x30,0xf8,0x92,0x2a,0xb5,0x49,0xef,0xec,0x40,0xa1,0x8e,0x1d,
+  0x85,0x3d,0x71,0xd4,0x48,0xb5,0x81,0x31,0xa2,0xa2,0x19,0xd9,0xf3,0x61,0xb5,0x2f,
+  0x8a,0x7d,0x53,0xfd,0x01,0xd8,0xd4,0x98,0xb0,0x37,0x61,0x5f,0xb8,0x6c,0x79,0xde,
+  0xc9,0xab,0xbe,0x08,0x5d,0xd1,0x79,0xcb,0xf3,0x56,0xb3,0xc9,0x6c,0xfe,0x8f,0xd6,
+  0xf0,0x2a,0x82,0xba,0x2a,0x6a,0xbb,0x64,0xba,0xfc,0x9d,0x14,0xc8,0xa5,0x41,0x5d,
+  0xf2,0x18,0xeb,0xa7,0x40,0xfd,0x4d,0xf6,0xf9,0x20,0x16,0xff,0xa7,0xf1,0xe7,0xae,
+  0xb3,0x9d,0x93,0xfa,0xaf,0xe1,0xba,0x14,0x51,0xea,0x8f,0xa8,0x9f,0x51,0x8d,0x4f,
+  0xb2,0xdf,0x43,0xbe,0x91,0xd5,0x1f,0xdb,0xea,0x0f,0x90,0x9a,0x86,0xe6,0x83,0xc5,
+  0xa8,0xb8,0x9c,0xb4,0x2c,0x78,0x24,0xa9,0x50,0xa3,0xf2,0x97,0x21,0x6e,0x2c,0x89,
+  0x4b,0xb6,0xfe,0xd8,0x25,0x8f,0xa3,0xdb,0x65,0xf9,0x53,0xb3,0xc4,0x5a,0x29,0xdf,
+  0x6c,0x5d,0x25,0xdf,0x05,0xfb,0x8c,0xf9,0x66,0x5b,0x88,0xfd,0x10,0x1e,0x48,0xb5,
+  0x8e,0xfc,0x28,0x9b,0xff,0x13,0xc6,0xd7,0xac,0x67,0x0f,0x86,0xad,0xe9,0xb7,0x93,
+  0x14,0xef,0xda,0x3e,0x67,0x3c,0xef,0x7e,0x04,0x95,0xe8,0x78,0xae,0xf2,0xae,0xce,
+  0x4d,0x4e,0x3f,0x3e,0x8c,0x2a,0x43,0xd4,0x0d,0x80,0xb6,0x19,0xf1,0xc7,0x7c,0x06,
+  0x0f,0xa6,0x1a,0xb3,0x7f,0xa4,0x36,0x34,0x6d,0xa0,0x8e,0xf4,0xab,0xb8,0xbd,0x3f,
+  0x36,0xe5,0xbf,0x2e,0x50,0x9a,0x4f,0x97,0xbd,0xf0,0x46,0x2c,0x18,0x73,0x8e,0x50,
+  0x7f,0x00,0x68,0x8c,0xe7,0xaf,0xc4,0x23,0x47,0x45,0x75,0x9c,0xf8,0xcf,0x76,0xfe,
+  0x0f,0x1f,0x85,0xef,0x4c,0xf5,0x47,0x32,0x82,0x39,0xf3,0x45,0x91,0x15,0xff,0x91,
+  0x0a,0xba,0x3a,0xc9,0xd4,0x04,0x4b,0x5c,0x82,0xd9,0xf1,0x4f,0xca,0xdf,0x5f,0x1a,
+  0x2d,0x52,0xa4,0xf7,0x84,0x35,0x36,0x02,0xed,0x9d,0x19,0x40,0x3c,0x50,0x46,0xfd,
+  0x1b,0x89,0x1f,0x72,0x05,0xff,0x67,0x3f,0xe1,0x99,0xad,0xd4,0xc8,0x88,0xa6,0x33,
+  0x3c,0x84,0x66,0x77,0xb7,0xe1,0x21,0x86,0x49,0x39,0xfc,0x82,0xd5,0x2c,0xcb,0xe2,
+  0x3f,0x5b,0xfd,0x01,0x10,0x4d,0xa9,0x0f,0xb1,0x72,0xe5,0x29,0xdd,0x63,0x7c,0x26,
+  0xce,0x52,0x6d,0x04,0xa8,0xb0,0x9d,0x3f,0xa5,0x59,0xf3,0x2c,0xb2,0xf9,0x3f,0xbb,
+  0x95,0x14,0xfe,0x89,0xad,0x4b,0x59,0x7f,0x0a,0x04,0x85,0x88,0x2f,0xa4,0xc4,0x0e,
+  0xa4,0x06,0xab,0x65,0xf3,0x7f,0xf0,0xa5,0xb8,0x2b,0x2c,0xeb,0x5d,0x4f,0xa3,0x37,
+  0x4a,0x63,0xb3,0x60,0x42,0x0f,0x00,0xc2,0x42,0x5d,0x8c,0x2a,0x01,0x9a,0x4f,0x71,
+  0x34,0x3b,0xff,0x95,0x8a,0x87,0x8c,0xc4,0x3e,0x81,0xc6,0x45,0x05,0xed,0x12,0xf5,
+  0x37,0x78,0xa9,0xed,0xf6,0x61,0x3c,0x62,0xb5,0xaa,0x8b,0x36,0xff,0x21,0x13,0xff,
+  0x91,0xe8,0xfa,0x4f,0x19,0x2e,0x8b,0xff,0x4c,0x67,0x29,0xff,0xf5,0x89,0x8e,0xeb,
+  0xd3,0x2e,0x2f,0xd7,0x5e,0x93,0x16,0x2c,0x72,0x0e,0xb3,0x07,0xec,0xf1,0x1f,0xa9,
+  0x0f,0xaa,0xa6,0xf8,0xcf,0x50,0x95,0x7a,0x9e,0x3e,0x88,0x71,0x55,0x78,0xb6,0xe9,
+  0x11,0xc4,0xdb,0x78,0xca,0xc6,0xff,0xa1,0xfe,0x00,0x60,0xf1,0x9f,0x07,0x77,0x92,
+  0xa0,0x96,0xd0,0xfb,0x6a,0x7a,0x1b,0x4d,0x68,0x32,0x3b,0x14,0x8a,0x77,0xcd,0xb5,
+  0xf1,0x7f,0x60,0xa7,0xb5,0xfe,0x56,0x3c,0xed,0x26,0x28,0x68,0xa1,0xfe,0xd8,0xd2,
+  0x7e,0xf0,0xb4,0xaa,0x5b,0xd8,0x4e,0x58,0xc7,0xe7,0xb6,0x5c,0x81,0x7f,0x88,0x76,
+  0x55,0x3b,0x15,0xc6,0x21,0x1a,0xcf,0xe3,0x16,0x10,0x0a,0xa4,0x06,0xdf,0xf7,0x0f,
+  0x5b,0x11,0xbf,0x1e,0x5b,0xfe,0x6b,0xa7,0x0d,0xf6,0xe8,0x28,0xfc,0x80,0xc2,0x3e,
+  0xd4,0xe8,0xe6,0x07,0x65,0x83,0x9c,0x4e,0xcd,0xcf,0xe6,0xff,0x50,0x7c,0xe0,0x3b,
+  0x52,0x0a,0x6f,0xd3,0x7c,0x90,0x0e,0xab,0x1f,0x69,0x6d,0x0a,0xff,0x9c,0x34,0x02,
+  0x7f,0x3a,0x1f,0xe4,0x0c,0xf8,0xb6,0xe7,0xc5,0x36,0x8f,0xc2,0x87,0x46,0x6d,0x4c,
+  0xed,0x91,0x7b,0xe0,0x45,0xd4,0x3f,0xbe,0x15,0xcc,0xcb,0x8f,0x26,0x2c,0x6a,0xb4,
+  0xad,0x3f,0xa4,0x42,0xdd,0x33,0x56,0xd2,0xb2,0xa0,0x5a,0x48,0x7a,0x43,0x6a,0x49,
+  0xee,0xab,0xb0,0x27,0x9a,0x62,0x24,0x42,0xf8,0xb3,0xfa,0x6f,0xd0,0xd5,0xca,0xc4,
+  0x7f,0x84,0x76,0x97,0x15,0xff,0xc9,0xa3,0xb6,0xf6,0x3f,0x8b,0xcc,0xa1,0x6e,0xd8,
+  0xa7,0x70,0x47,0x6d,0x1b,0xe5,0xe7,0xd8,0xac,0x81,0x07,0xe9,0xfb,0x6d,0x0f,0x67,
+  0xfa,0x43,0x46,0x22,0x6f,0xc2,0x6f,0xf1,0xb3,0x75,0x51,0xb6,0xeb,0x25,0x04,0x42,
+  0xd6,0x7c,0x90,0x3f,0x76,0xdc,0x70,0x26,0x7f,0xb5,0x1c,0x0c,0x53,0x6a,0xcc,0x79,
+  0xe7,0x15,0xfc,0x9f,0xa9,0xf8,0x0f,0xe9,0xf3,0xda,0x54,0xa0,0xe3,0x3c,0x55,0xac,
+  0x50,0x20,0xe8,0x6d,0x78,0x91,0xf8,0x2d,0xb6,0xf9,0xb0,0x70,0x50,0x5c,0x4e,0x45,
+  0x7b,0xa8,0x2d,0x36,0x0a,0xe7,0xe5,0x37,0xd1,0x6c,0xdd,0x90,0xbc,0xfd,0xa4,0x5c,
+  0x85,0x16,0x6d,0x41,0xc8,0x77,0xa7,0x64,0x9b,0x8f,0x56,0x92,0xe2,0xf3,0x14,0xdc,
+  0x97,0x0a,0x3b,0x5b,0x63,0xdd,0xe0,0x49,0xed,0x06,0x44,0x38,0xf2,0x17,0xc5,0x73,
+  0xfa,0x36,0xca,0x87,0x3e,0x6d,0xe7,0xff,0xa4,0xf8,0x8a,0xd4,0x16,0x60,0x2d,0xaf,
+  0xb4,0x1a,0x63,0xf2,0x47,0xa0,0x2c,0x19,0x6e,0x67,0x77,0x89,0x17,0xa1,0xac,0x25,
+  0xaf,0xdd,0xd6,0x9f,0x44,0x57,0x36,0x4c,0x0f,0x39,0xa5,0x36,0x2f,0xbe,0x41,0xb5,
+  0x26,0x3c,0x24,0xed,0x86,0xf2,0x73,0x25,0x34,0x08,0xb5,0x37,0xa1,0x9b,0x79,0x59,
+  0xf3,0xd1,0x66,0xa6,0xfb,0x3d,0x1e,0x84,0x97,0x45,0xea,0xc5,0xe1,0xd7,0xb0,0x20,
+  0x59,0x50,0x87,0xf6,0xe2,0x42,0x32,0xf0,0x2a,0x2a,0xde,0x8a,0xcc,0x7c,0x10,0x69,
+  0xca,0x1e,0xd1,0xfc,0x5c,0x6b,0xa1,0xfa,0x9a,0xc7,0xe0,0x3d,0x25,0xd8,0xef,0x3a,
+  0x38,0x63,0xcc,0x0a,0x04,0xcd,0x8e,0xda,0xfa,0x43,0x96,0x6a,0x29,0xbe,0x47,0xc1,
+  0x05,0xcb,0xba,0x2d,0x1c,0xc6,0xf5,0x69,0x30,0x2e,0xc2,0xc2,0x01,0xe7,0x78,0xe7,
+  0x5d,0xfc,0x28,0xbe,0x88,0xf3,0x94,0xad,0x3f,0x24,0xf1,0x7f,0x28,0xec,0xd6,0x4a,
+  0xb4,0x93,0x03,0x83,0x1e,0xb4,0x47,0xf2,0x4a,0xe8,0x45,0xfb,0xce,0x77,0x31,0x9f,
+  0x72,0x3c,0xa1,0xf7,0x54,0xd8,0xfb,0xb3,0x51,0x7f,0x80,0x67,0xa0,0x6a,0xd0,0x11,
+  0xcf,0x1d,0xd3,0x0e,0x88,0xb9,0xa9,0x7e,0x02,0xcf,0x44,0xe6,0x9a,0xad,0x8f,0xb3,
+  0x95,0xf0,0x03,0xad,0x22,0x51,0x62,0xe7,0x3f,0x3b,0x34,0xea,0x4e,0xec,0xeb,0xe7,
+  0x01,0xcf,0x90,0xd5,0x1f,0x5b,0x8d,0x5b,0xfa,0x19,0x11,0x17,0xee,0xb7,0x8e,0x1f,
+  0xa4,0x1a,0x05,0xd8,0xe2,0x3f,0xce,0x95,0x06,0x3d,0x4f,0x41,0xbc,0xe8,0x03,0xea,
+  0x07,0x8e,0xd7,0x5b,0x86,0x78,0xa1,0xe9,0xa3,0x89,0xe4,0x6f,0xc0,0xf3,0x86,0x33,
+  0x5e,0x66,0xda,0xf8,0x3f,0x93,0xd2,0xef,0x52,0x43,0x40,0x26,0x63,0x93,0x2c,0x65,
+  0xbf,0x10,0xf6,0xe0,0x91,0x50,0xd9,0xa4,0x71,0x02,0x16,0x8a,0x2b,0xe6,0xc3,0x8e,
+  0x0f,0x0e,0x95,0x37,0x72,0xe2,0x33,0xa0,0xe3,0x5f,0xcd,0x6f,0x1f,0x68,0x26,0xa2,
+  0xdd,0x4d,0xdc,0xf7,0xb2,0xea,0x1f,0x18,0x2a,0xaf,0xe6,0xe8,0x9a,0xd9,0xe7,0x83,
+  0x8c,0x19,0xdd,0xd1,0xaa,0x11,0xf5,0x20,0xfb,0x1d,0x1c,0x18,0xa8,0x18,0x59,0xbc,
+  0x9f,0xda,0x22,0x99,0x9e,0x71,0xea,0x7f,0x68,0x74,0x6f,0xf1,0x8c,0x7b,0x77,0x66,
+  0xcd,0x87,0x4d,0x6e,0xa6,0x30,0x97,0x2a,0xa1,0xad,0xed,0xd5,0x74,0x38,0x0c,0xb9,
+  0xa2,0x45,0x18,0xde,0x16,0xbe,0x80,0x41,0x97,0x80,0x90,0xe2,0x28,0xbe,0x62,0x3e,
+  0x48,0x37,0x85,0xb9,0x70,0xfd,0xc5,0x7e,0x56,0x91,0xb0,0xd6,0xb3,0x5b,0xf3,0x74,
+  0xa1,0x5a,0xf3,0xe9,0x2a,0x78,0xfa,0x1d,0x59,0xf3,0xd1,0x0a,0x47,0xee,0x3c,0x1c,
+  0xaa,0xf2,0x58,0xd3,0x3a,0xce,0x2b,0x81,0xbb,0x0b,0x1e,0x2a,0xda,0xce,0x12,0x52,
+  0x1d,0x2c,0x81,0x32,0x2f,0x65,0x64,0x16,0x3c,0x98,0x3d,0x1f,0xa4,0x0f,0x3e,0x51,
+  0x1a,0x13,0xf8,0xbe,0x17,0x68,0x59,0x62,0xae,0x64,0xe7,0x5b,0xd3,0x3b,0x6a,0x04,
+  0x26,0xe1,0xa5,0xf1,0x7c,0x91,0xd5,0x1f,0x7b,0x67,0xf1,0x1b,0x79,0x41,0xf8,0x14,
+  0x75,0xdf,0x3a,0xa2,0x59,0xb4,0xd5,0x18,0x65,0x04,0x68,0x22,0xfc,0x3c,0xb4,0xef,
+  0x75,0xda,0x15,0xf1,0x1f,0x2f,0xac,0x33,0xab,0x46,0xd5,0x08,0xaa,0x1d,0x01,0x55,
+  0x7d,0xdc,0xeb,0xf1,0xc1,0x2f,0x87,0x6b,0x63,0x5e,0xc1,0xca,0xb5,0x08,0x02,0x39,
+  0xd4,0xd8,0xf6,0xf8,0xcf,0x0a,0xe9,0x21,0x81,0xb0,0x87,0xe7,0x26,0x28,0x1e,0xd8,
+  0x7b,0xe7,0x9c,0xa6,0x21,0xa3,0x73,0x50,0x8f,0x39,0x00,0xed,0x5d,0x8c,0x10,0x91,
+  0x96,0x15,0xff,0xc9,0x35,0x1e,0x10,0x95,0xba,0xba,0x3a,0xfc,0x7d,0x58,0x1b,0xad,
+  0xa4,0x7e,0xb3,0x4d,0xc6,0x16,0x31,0x67,0xb9,0x63,0x35,0xbb,0x3a,0x77,0x47,0x24,
+  0xc7,0xa3,0xae,0x00,0x7b,0x7f,0x24,0x0e,0xbf,0x70,0x34,0x98,0x2a,0xb8,0x13,0x6c,
+  0x40,0x6b,0xe8,0x71,0xea,0xf2,0x6b,0xc6,0xcb,0x77,0xfa,0xdf,0x2d,0xf0,0xcb,0x0a,
+  0xfa,0x58,0x0d,0xe6,0x26,0x2d,0x2b,0xfe,0xb3,0xb3,0xe4,0x12,0xda,0xf7,0xb5,0xe3,
+  0xf2,0x09,0xe3,0x13,0xed,0x66,0xe3,0xbf,0xb7,0x97,0xc5,0x0d,0x8a,0x28,0xde,0xd6,
+  0xaf,0x4e,0xc0,0x5b,0x70,0x93,0x72,0xc5,0x7c,0xb4,0x0f,0x29,0xc9,0x95,0xfc,0x9a,
+  0xbf,0xec,0xa7,0xec,0x10,0x10,0xff,0xb9,0x99,0xda,0x42,0x06,0x85,0x53,0xa8,0xbe,
+  0x5c,0xca,0x48,0xfa,0xb2,0xf3,0x5f,0x51,0x85,0xd8,0x95,0x9c,0x22,0x6c,0x0f,0xb0,
+  0x52,0x68,0x4b,0xd5,0xcd,0x56,0x52,0xfd,0x97,0x66,0x11,0x2f,0xb9,0x99,0x95,0xff,
+  0x7a,0x50,0x79,0xb2,0x63,0x5e,0xb2,0x75,0xb5,0xf6,0x23,0xc4,0x87,0xe5,0xc9,0xb6,
+  0x3a,0xf7,0x83,0xca,0x5a,0xf4,0x66,0xf3,0xea,0x3c,0x05,0xb0,0x36,0x52,0x4a,0xfc,
+  0x1f,0x7b,0x7f,0x6c,0x53,0x80,0xe2,0x85,0x56,0xc6,0x40,0x08,0xbd,0x9c,0xaf,0x67,
+  0x56,0xa0,0xb5,0x1c,0xf2,0x04,0xf3,0x38,0x89,0xcf,0x99,0x07,0x57,0xe4,0xbf,0x2a,
+  0xf4,0x7a,0xc1,0xb7,0xe3,0xef,0x75,0x18,0x9e,0xa3,0x46,0x49,0x11,0x14,0x1a,0x44,
+  0xa5,0x95,0x11,0x33,0x03,0x22,0xff,0x4c,0x56,0xfe,0x8b,0x68,0x3f,0x8f,0x40,0x8e,
+  0x51,0x36,0x0e,0xe7,0xd0,0x42,0x5a,0x44,0x20,0x6a,0x3b,0x56,0x90,0x62,0x04,0xa1,
+  0x60,0x5c,0x11,0xff,0x39,0x0b,0x81,0x15,0x05,0x5b,0xe5,0xb9,0xca,0x79,0x14,0xba,
+  0x1f,0xb2,0xe2,0x03,0xf5,0xed,0x4a,0xb4,0x6c,0x39,0x9c,0xe6,0x01,0x63,0x53,0xf4,
+  0x4f,0xe6,0xa3,0x79,0x42,0x68,0x76,0xc9,0x10,0x7b,0xda,0xd5,0xef,0x23,0xfe,0xb1,
+  0x02,0x89,0x51,0x2a,0x44,0x82,0x5a,0xb2,0xc8,0x57,0xcc,0x47,0x13,0x65,0x86,0xfa,
+  0x0b,0xb6,0xb7,0xe5,0x05,0xf1,0xa5,0x76,0x22,0x02,0xb1,0x8d,0xfa,0x0e,0xc3,0x31,
+  0xcc,0xbe,0x01,0x3f,0x29,0x2e,0x33,0xaf,0xf9,0x93,0xf9,0x68,0xbb,0x88,0xff,0xb3,
+  0x7e,0x4b,0xec,0x59,0xef,0xb6,0x36,0x99,0xca,0xbe,0xd6,0xce,0x2b,0xb5,0xe6,0xa3,
+  0xc5,0xd6,0x78,0xe7,0x10,0x23,0x28,0x7b,0x3e,0x1a,0x8d,0x45,0x73,0x4d,0xcf,0x47,
+  0x73,0x85,0x59,0xb2,0x2b,0x51,0x1a,0xe0,0x55,0x61,0x39,0x24,0x56,0xe0,0x91,0xa5,
+  0xd9,0xf3,0xd1,0x46,0x76,0x5b,0xdd,0x0e,0x89,0x0f,0x4c,0x44,0xa0,0x19,0x51,0x6b,
+  0xfe,0x45,0x8d,0x49,0x1d,0x93,0x62,0x56,0xe8,0xe3,0xca,0xfe,0xd8,0x14,0xe4,0x21,
+  0xb6,0x4f,0xec,0x35,0xbd,0xd1,0x28,0x48,0xf1,0x7f,0xaa,0xdb,0x9c,0xbf,0x94,0xcf,
+  0xc1,0x07,0x74,0xea,0x8a,0xf9,0x68,0x34,0x0d,0x96,0xf0,0x8f,0x0e,0xa3,0xee,0x2a,
+  0xcd,0x9b,0xe2,0xff,0x30,0xe0,0x3b,0xd8,0x69,0x4f,0x04,0xb6,0xa3,0x13,0x19,0xce,
+  0x9a,0x0f,0x32,0xb0,0xbb,0x58,0x27,0xa3,0x46,0x78,0xd2,0xd7,0x82,0x42,0x17,0xeb,
+  0xd0,0x7a,0x0c,0xaf,0x9b,0xf0,0x0f,0xe1,0xc3,0xa2,0x2b,0xe6,0xa3,0x3d,0x0a,0xb4,
+  0xda,0xb8,0x65,0x9e,0x4a,0x01,0xa1,0x29,0xfe,0xcf,0x66,0x6b,0x50,0x88,0x85,0x27,
+  0xb3,0xe6,0x83,0xc0,0x54,0x5a,0x53,0xa1,0x42,0xb0,0x45,0x05,0x29,0xfe,0xcf,0xd5,
+  0xed,0x4e,0x6a,0xfc,0x78,0x3a,0x45,0x04,0xb2,0xcf,0x07,0xe9,0x82,0xf7,0xe0,0xa0,
+  0x31,0x5f,0x53,0x47,0xe0,0x3d,0x63,0x0a,0x08,0x9d,0x85,0xda,0xe9,0x40,0xd0,0x73,
+  0x84,0x7f,0xec,0xf9,0xaf,0x58,0x9e,0xe6,0xb1,0xd0,0x0e,0xe1,0x1f,0x3f,0x77,0x5a,
+  0x44,0xa0,0x92,0x1a,0xab,0x51,0xb9,0x36,0xa1,0x59,0xad,0xcb,0xed,0xf3,0x41,0xbc,
+  0xca,0x51,0xd3,0x83,0xfb,0x99,0x8d,0x6a,0xcf,0xc7,0xca,0x04,0x1f,0xcd,0xad,0x90,
+  0x5e,0x34,0xe6,0xf7,0xf0,0x24,0xe3,0xda,0x51,0xa8,0x0d,0xe7,0xc7,0x98,0x7d,0x3e,
+  0xc8,0x12,0x10,0xfd,0xe5,0x21,0x6e,0xe1,0x1f,0x88,0x45,0xbd,0x0d,0x87,0x15,0x63,
+  0x8f,0x51,0x1e,0x42,0xb5,0xa3,0x28,0xdb,0xc8,0xff,0x8a,0x3b,0xb2,0xe6,0xc3,0x86,
+  0x1f,0x68,0x2a,0x1f,0x58,0x81,0xb0,0x01,0xdd,0x3a,0xca,0xef,0x84,0xad,0x8e,0x49,
+  0xa6,0xe3,0x2f,0x1d,0xc5,0x5d,0x33,0xa4,0x2f,0x53,0x04,0xc9,0xde,0x1f,0x3b,0x48,
+  0x4d,0xb0,0x93,0xce,0xd4,0x58,0xb4,0x05,0xd3,0x83,0x0e,0x6b,0x92,0xae,0x12,0xb9,
+  0xd6,0xca,0x7f,0xe1,0xa9,0xbf,0xb5,0xe7,0xbf,0x60,0x14,0x8d,0xe0,0x74,0xda,0x2b,
+  0x23,0xe4,0x50,0x7c,0xec,0x1d,0xa5,0xa1,0xdf,0xb5,0x5b,0x66,0xf6,0xf9,0x68,0xc9,
+  0x73,0xa2,0xf1,0x74,0x01,0xcd,0x47,0xbb,0x18,0x9d,0x4a,0x84,0x59,0x88,0xe8,0xce,
+  0xce,0x5a,0xe3,0x48,0x2a,0x35,0x66,0xef,0x8f,0xfd,0xa2,0xb9,0x46,0x2b,0x7d,0x95,
+  0x7f,0x7d,0x73,0xb1,0xb1,0x2f,0xe6,0x1b,0x50,0xbf,0x11,0x3e,0x05,0xfb,0x16,0xf9,
+  0x68,0xf0,0xfd,0x55,0xb0,0x76,0x37,0x21,0x9c,0xcd,0xd9,0xf9,0xaf,0x9d,0xe0,0xb5,
+  0xfc,0x35,0x7a,0xcd,0x41,0x0b,0x2f,0x59,0x88,0xa8,0xdd,0xd1,0x22,0xd6,0xa6,0x8e,
+  0xd8,0xfb,0x63,0xbf,0x66,0x88,0xa8,0x7e,0x28,0xaf,0xa6,0xa9,0x40,0xec,0xf9,0x95,
+  0x6f,0x5c,0x6d,0x40,0x47,0x7e,0x4f,0xbb,0x6f,0x44,0x2d,0x66,0xb7,0x40,0x67,0xdc,
+  0x37,0x8a,0x47,0xec,0xfd,0xb1,0x0f,0xc2,0xa8,0x51,0x37,0x8e,0xf8,0x6d,0xbe,0xf7,
+  0xbc,0x11,0x0c,0xa1,0xf0,0xa1,0xb0,0x10,0xd1,0x1b,0xf2,0x37,0xc5,0x11,0x23,0x48,
+  0x83,0xd2,0xec,0xfd,0xb1,0x87,0xf4,0x0b,0x3a,0x7a,0xdf,0xfe,0x1d,0x43,0x70,0x51,
+  0xbf,0x7f,0xc0,0x55,0xd3,0x39,0x56,0x4a,0x65,0x5f,0x2e,0xad,0xb3,0x6b,0x2e,0x2e,
+  0xd4,0xe0,0x75,0xd9,0xf3,0xd1,0x26,0xe1,0x04,0x54,0x9b,0xf9,0x71,0xa9,0x91,0xba,
+  0x1d,0x5a,0xf1,0x1f,0xe5,0x2d,0xc4,0x57,0x56,0xa1,0xe5,0xcf,0xad,0x8a,0xef,0xec,
+  0xf9,0x68,0xc4,0xaf,0x33,0x39,0x8d,0x45,0x3b,0x02,0x9e,0xb3,0xfc,0x60,0x53,0x15,
+  0xd9,0xf7,0x11,0x4b,0xff,0x74,0x2b,0x9e,0xdf,0xa8,0x59,0xf3,0x41,0x24,0x1f,0x5e,
+  0x7f,0x4f,0x22,0xaf,0x97,0xed,0x82,0x67,0x44,0xc5,0x3d,0x34,0xcf,0xcb,0x78,0x4c,
+  0xe0,0x1d,0xe8,0xc3,0x79,0x4c,0xb7,0x5a,0x27,0xd9,0xfb,0x43,0x3a,0xc3,0xe8,0xd6,
+  0xe1,0xb6,0x69,0xdb,0xc0,0x76,0x48,0x3d,0xa6,0xd7,0xcf,0x7d,0xc4,0xff,0x31,0x57,
+  0x68,0x0e,0x25,0xfc,0xb0,0x1e,0x43,0xd7,0xd5,0x61,0x9f,0x8f,0xb6,0x92,0xac,0x2d,
+  0x3e,0xff,0x97,0x10,0x18,0xc7,0xea,0x4f,0x58,0x44,0x97,0x5f,0x43,0xe0,0xc4,0x86,
+  0xa8,0x5c,0x1e,0xff,0x75,0x9e,0xc5,0x6f,0xc9,0x9e,0x8f,0x36,0x96,0x22,0xb1,0xdc,
+  0x0f,0xc7,0x8c,0x85,0xc9,0x4d,0x66,0x8a,0xd6,0x6b,0xa2,0x63,0x35,0x92,0x1a,0x94,
+  0x36,0xde,0x9c,0xd5,0x1f,0xdb,0xf8,0x5d,0xaa,0xbf,0xd6,0x25,0x76,0x4c,0x34,0x8e,
+  0xf8,0x26,0xe5,0xa0,0x71,0x6e,0x4b,0xf5,0x88,0xf3,0xe0,0xe2,0x60,0xfb,0xe5,0x68,
+  0xf5,0xc8,0x75,0xe7,0x9b,0xed,0xf8,0x67,0x08,0xf1,0xaa,0x9e,0x88,0xf4,0xb2,0xb1,
+  0x68,0xb7,0xa7,0x20,0x61,0x15,0xbe,0xdd,0xa4,0x7b,0x0e,0xb5,0xc5,0xd1,0xbc,0x1c,
+  0xc8,0xf1,0xe0,0x52,0x80,0x1d,0xff,0x0c,0x75,0xed,0x28,0x8d,0x0d,0xf4,0xf8,0xc3,
+  0x4b,0x74,0x99,0xfb,0xcc,0xd6,0x40,0x93,0x33,0xb2,0x87,0x56,0xa0,0x97,0x6d,0x50,
+  0xf6,0xe0,0xfb,0x3a,0xfc,0x57,0xe0,0x9f,0x03,0x12,0xad,0x3f,0x8d,0xe5,0x15,0x73,
+  0x13,0x3c,0xe0,0xde,0xa5,0x10,0x8d,0x8a,0xc5,0xd9,0x7c,0xbe,0x07,0xd7,0x33,0x2f,
+  0x7b,0x3e,0x1a,0xc1,0xe0,0xc0,0x20,0x2e,0xcb,0xd7,0xa8,0xec,0x3a,0xb9,0x84,0xf8,
+  0xe1,0x17,0x77,0x52,0xfd,0x57,0xd9,0x4f,0x95,0x8b,0xa2,0x97,0xf8,0x27,0xc3,0xd9,
+  0xfc,0x1f,0x13,0x3f,0x8a,0x73,0x88,0x06,0x2f,0x4b,0x56,0xfc,0xe7,0x1f,0xa8,0x10,
+  0x6c,0x7c,0xd3,0xf9,0x2f,0x9d,0xa3,0x0f,0xa7,0xff,0x4f,0xe6,0x83,0x50,0x7d,0xe2,
+  0x06,0xbc,0x2d,0xcd,0x87,0xb5,0xbe,0x47,0x7e,0x91,0xda,0x92,0xef,0x46,0xc7,0xe4,
+  0x48,0x69,0x10,0x81,0x68,0x73,0xf6,0x7c,0x90,0xee,0xe1,0xaa,0x73,0xfc,0x05,0x0f,
+  0x6e,0x9b,0xf6,0xaa,0x13,0xea,0x3e,0xf6,0x81,0x49,0x13,0x75,0xd5,0x1b,0x4a,0xbf,
+  0x1c,0xea,0x4e,0x56,0xfd,0x1e,0x9e,0xcd,0xce,0x7f,0x19,0x84,0xf7,0xbc,0x7e,0xe6,
+  0x32,0x1e,0x2e,0xac,0x1a,0xe9,0x26,0xc7,0x81,0x32,0xaa,0xdd,0x64,0xdf,0x3b,0xc1,
+  0x97,0x84,0x05,0x57,0xe4,0xbf,0x66,0x88,0xca,0x11,0x7e,0x5f,0x78,0xb6,0xf6,0x48,
+  0x34,0x15,0xff,0x41,0x37,0x67,0x5b,0x52,0xbd,0xc0,0xbe,0x08,0x6b,0x63,0x95,0xd4,
+  0x7f,0xd2,0x8e,0x7f,0x9c,0xf0,0x32,0x6f,0x18,0x70,0x3e,0x2f,0x3b,0xd9,0x2f,0x35,
+  0x9f,0x55,0x2f,0x09,0x1f,0x73,0x8d,0x1c,0x87,0x0d,0x4d,0x2f,0x43,0xc3,0xcb,0xce,
+  0xdd,0xd9,0xf9,0xaf,0xa6,0xcb,0x5a,0x23,0x95,0x7d,0x9d,0x82,0xdf,0x15,0xd3,0x6e,
+  0x29,0x9a,0x54,0x1a,0xa9,0xfe,0x2b,0x4e,0x85,0xf0,0xfa,0xcd,0x87,0x5c,0x7b,0xe4,
+  0x6c,0xfe,0xcf,0x11,0xc9,0x1a,0x02,0x8b,0x8e,0x09,0x0b,0xa4,0xf4,0x15,0x11,0x81,
+  0x36,0xc4,0xad,0x40,0x90,0xc5,0x8f,0xfa,0x97,0xe6,0x83,0xb8,0x4f,0x69,0x2f,0x49,
+  0xa5,0x66,0x37,0xe9,0x93,0x4d,0x56,0x07,0x36,0x37,0x6a,0x98,0x9c,0x52,0xb3,0x64,
+  0xfc,0x8a,0xf9,0x20,0x8f,0x88,0xcf,0x58,0xf3,0x41,0xf8,0x23,0xa9,0x42,0xb0,0x4b,
+  0xde,0xb5,0x5d,0x16,0x23,0xfa,0xba,0x54,0x29,0xdc,0x95,0xf3,0x41,0x1e,0x02,0x3d,
+  0xc4,0x0b,0x3d,0xaf,0x6a,0xe8,0xe6,0x87,0x68,0xde,0xa5,0xd6,0xb9,0x4a,0x5f,0x5e,
+  0x52,0xc2,0xf2,0x10,0x51,0xc4,0xfa,0xff,0x64,0x3e,0xc8,0x1b,0x10,0xa0,0xb1,0x68,
+  0x4f,0x8b,0x37,0xc4,0x73,0x61,0x57,0xac,0xf3,0x0c,0x1c,0x35,0x7b,0x63,0xb3,0xce,
+  0xa8,0x75,0xfc,0x02,0x04,0x84,0xef,0xca,0xf9,0x20,0xa3,0x2d,0xc1,0x62,0xf4,0xc7,
+  0x4f,0x6b,0x13,0x86,0x35,0x1f,0x2d,0xc9,0x50,0xd0,0x88,0x11,0xa4,0xff,0xcb,0xfc,
+  0x9f,0x41,0xb4,0x8f,0x8f,0xcb,0xff,0xcd,0x32,0xac,0xce,0x87,0x32,0xf3,0x43,0xcb,
+  0xe1,0x50,0x7f,0x60,0x79,0xf6,0x7c,0x10,0xe2,0xff,0x98,0xdb,0xdb,0x57,0x6c,0x55,
+  0x67,0xc0,0x3a,0x63,0x7b,0xc8,0xfb,0xb8,0x63,0x2e,0x43,0x81,0x68,0x3f,0x73,0xd8,
+  0xba,0x2e,0xab,0x63,0x76,0x16,0xff,0x67,0x7a,0xde,0x47,0x39,0xec,0x96,0xbc,0x2d,
+  0x79,0xd4,0x45,0x26,0x75,0xc4,0xad,0xe8,0xeb,0x40,0x6f,0x42,0x8b,0x7f,0x6b,0x16,
+  0xff,0x87,0xf8,0x51,0x11,0x0d,0x3f,0xdb,0x1d,0xe0,0x35,0xf2,0xfc,0x4d,0x5d,0xa9,
+  0x8a,0x4b,0xad,0x09,0x6f,0x65,0xc5,0x43,0x58,0x93,0x1d,0xff,0x4c,0xcd,0x07,0x29,
+  0xd2,0xad,0xee,0x97,0x68,0x76,0x63,0x5a,0x02,0xdf,0x4f,0x01,0x59,0x07,0x9a,0x29,
+  0x81,0xf6,0xf7,0x76,0xfb,0x7c,0x34,0xab,0x2d,0xb6,0x55,0xf6,0xf5,0xcf,0xde,0x85,
+  0x6d,0x05,0xc7,0x3b,0xef,0xe8,0x4b,0x15,0x82,0xbd,0x3c,0x89,0xa7,0x82,0x74,0xea,
+  0xc7,0x59,0xf8,0xe7,0xe5,0x9c,0xc0,0x2d,0xa9,0x79,0x19,0x5a,0x3d,0x05,0x52,0xac,
+  0xfa,0x2f,0x5a,0xa8,0x11,0x8a,0xe8,0xde,0xb2,0x29,0x7b,0x3e,0x5a,0xaa,0x3f,0xb6,
+  0x1a,0x0e,0x83,0xe8,0xd3,0x75,0x46,0xfc,0x1f,0x2d,0xe2,0xdd,0xce,0x39,0x02,0x33,
+  0xbd,0xcf,0x9a,0x0f,0xb2,0xdd,0x3e,0x1f,0xf6,0x9c,0x58,0x03,0x44,0xf2,0x71,0x20,
+  0xf0,0xd3,0x3f,0x63,0xf5,0xc7,0xd6,0x36,0xea,0x56,0x7f,0xec,0x13,0xeb,0x5e,0x50,
+  0x4a,0x0d,0xf5,0xf8,0x15,0xf8,0x67,0x0d,0xec,0x48,0xf1,0x7f,0x5e,0x48,0xb1,0xc7,
+  0x6b,0x60,0x23,0x47,0xe1,0x17,0x4d,0xe7,0xf0,0x08,0xcd,0x07,0xc9,0xb5,0xcd,0x87,
+  0x9d,0x39,0x08,0x87,0xb4,0xc0,0x72,0x17,0xe2,0x5b,0xe3,0x7c,0xb4,0x2e,0x54,0x10,
+  0xa5,0xfa,0x2f,0xc3,0x1d,0xf2,0x6d,0x45,0xa0,0x7b,0x56,0x09,0x2c,0x72,0x69,0x59,
+  0xf8,0x67,0x27,0x3b,0xcf,0xd0,0xcc,0x6d,0xa6,0x6a,0x2f,0x08,0xde,0xea,0x7a,0xfc,
+  0xcf,0x46,0xc4,0xf9,0x68,0x10,0xef,0x40,0x40,0x31,0x6a,0x85,0xce,0xae,0xe4,0xff,
+  0x2c,0x4c,0xc1,0xec,0x53,0x88,0xae,0xad,0x6e,0x24,0x04,0xb3,0x37,0x51,0x8c,0xf3,
+  0x54,0x8a,0xea,0x90,0x15,0xff,0xe9,0x3a,0x93,0xa6,0xfd,0x48,0x55,0x54,0xed,0xee,
+  0x85,0xe7,0x51,0x50,0x7b,0x98,0x97,0x1f,0x86,0xaa,0x8e,0x2b,0xe6,0x83,0x34,0x8b,
+  0x18,0x94,0xa3,0x63,0x89,0x46,0x7c,0xab,0xf0,0x69,0x5c,0x78,0x74,0xab,0x82,0xc9,
+  0xc1,0xc9,0x71,0x40,0x1f,0xfe,0x4f,0xe6,0x83,0xfc,0x0c,0x4a,0x5f,0x46,0xa3,0xff,
+  0xa6,0x15,0x0f,0xf1,0xa6,0x68,0xc0,0x95,0xe6,0xe2,0xfb,0x29,0x31,0x9d,0x8a,0xa8,
+  0xd8,0xf1,0x8f,0x1b,0x41,0x8e,0x35,0x04,0xe4,0x4d,0xf8,0x47,0x71,0x73,0x8c,0x4f,
+  0xc8,0x57,0xc3,0xef,0xc5,0xcd,0x49,0x57,0x42,0xaa,0x85,0x57,0x49,0x58,0x91,0xcd,
+  0xff,0x21,0x7e,0x1d,0x0d,0x01,0x49,0x6a,0x17,0x28,0x50,0x26,0x10,0x28,0x5e,0x90,
+  0x82,0x54,0x08,0x36,0x4a,0x81,0x0e,0xa0,0xf8,0x8f,0x0d,0xff,0x8c,0x89,0x31,0xd1,
+  0xb8,0xcd,0x95,0x28,0x0a,0xc0,0xa5,0x8e,0x85,0x77,0xe7,0x27,0xe4,0x00,0x1f,0x12,
+  0xd5,0xe5,0xae,0xd1,0xe6,0x00,0x9c,0x12,0xd5,0xba,0x2b,0x21,0xdb,0xe2,0x3f,0x85,
+  0xbd,0x1d,0xf8,0x90,0x86,0x1c,0xb7,0xda,0x42,0xaa,0xc2,0x41,0x85,0xf0,0x54,0xf6,
+  0x85,0xbf,0xf8,0x41,0xb6,0x56,0x42,0xe1,0x22,0x7b,0x3a,0x6b,0x3e,0xc8,0x93,0xbc,
+  0xf2,0x55,0x35,0x64,0xe1,0x9f,0xd2,0x01,0x3e,0xee,0x28,0x81,0xef,0xc1,0x9c,0x01,
+  0x5c,0xc6,0x62,0x78,0x80,0x5b,0xf3,0x41,0x6c,0xf1,0x9f,0x62,0x13,0xfd,0xae,0x2a,
+  0x40,0xb5,0x03,0x46,0x5c,0xf3,0xea,0xe8,0xc6,0xe6,0x42,0x6f,0x02,0x5d,0xf7,0xad,
+  0xf8,0x61,0xaf,0x03,0x2f,0xcd,0x07,0xb1,0xc7,0x7f,0x62,0x30,0x2a,0x82,0xba,0x2b,
+  0xda,0xe9,0x81,0x09,0x51,0xab,0x3b,0x23,0x9d,0x73,0xf5,0x37,0x92,0xb5,0xba,0xeb,
+  0x07,0xcd,0x15,0xa4,0x28,0x28,0xf4,0x57,0xf1,0x27,0xfc,0x9f,0x4d,0xb1,0xa2,0x94,
+  0x80,0x8a,0xf7,0x3d,0x44,0xd4,0xf5,0xc4,0x37,0x18,0xe1,0x67,0xa4,0x20,0xd9,0xbb,
+  0x64,0x16,0xff,0x07,0xad,0x9b,0xe1,0x1c,0xaf,0x68,0x80,0x4f,0x60,0xa1,0xb8,0x8e,
+  0xe2,0x21,0x44,0xfb,0x41,0xfc,0xd3,0x20,0x8e,0xc1,0x1e,0xe2,0xff,0x64,0xe1,0x1f,
+  0xa5,0x0f,0x77,0x4b,0xab,0x72,0x55,0x0c,0x7a,0xa9,0x10,0x40,0xb8,0x4f,0xfb,0x84,
+  0x68,0x80,0xd6,0x9d,0xf5,0x4c,0x3b,0x19,0xc2,0x4f,0x2f,0x2a,0x87,0xb2,0xe6,0xc3,
+  0xf6,0x51,0x36,0x7c,0x0b,0x8b,0xc1,0xf3,0x30,0x17,0xaf,0x67,0x83,0xd2,0x7a,0x7d,
+  0x2e,0xf0,0xbd,0xb8,0xf1,0x1e,0x55,0x18,0xee,0x9f,0x26,0xfb,0x7c,0x34,0x20,0x3e,
+  0xb0,0x81,0xdb,0x72,0x03,0xf5,0xb3,0x15,0xb8,0x89,0x13,0xe4,0x5f,0x98,0x11,0x85,
+  0x95,0x2b,0x9b,0xc1,0xe2,0x03,0x67,0xf4,0x0f,0xcd,0x07,0xa1,0xee,0xdf,0x4b,0x76,
+  0xbb,0x7d,0xfc,0xe3,0x54,0xfc,0x87,0x06,0x85,0xcc,0x35,0x7d,0x7b,0xcb,0x7c,0x16,
+  0xff,0x67,0xe9,0xf6,0x66,0x3b,0xfe,0x19,0xb7,0xbc,0x75,0xd5,0x94,0x56,0x59,0x9f,
+  0xc9,0x0c,0x63,0xca,0x2d,0xcd,0x6f,0x42,0xe1,0x7e,0xfa,0x5e,0x1e,0xca,0x8a,0xff,
+  0xfc,0xe1,0xce,0x9f,0xf9,0x1b,0x87,0x9c,0xdf,0x52,0x5f,0x34,0x7e,0xa7,0xed,0x19,
+  0x77,0x9d,0x57,0x67,0x37,0x1d,0x8b,0xee,0x1f,0xf1,0xb5,0xca,0x01,0xf8,0x7d,0x14,
+  0xa1,0xe3,0x1f,0x9a,0xed,0xfc,0x9f,0x84,0xe8,0x0c,0x55,0x51,0x53,0x9a,0x25,0x62,
+  0x9d,0x81,0x68,0x27,0xc0,0xa8,0x10,0xde,0x93,0xe0,0xd1,0x70,0x4f,0x0c,0xed,0xcb,
+  0x00,0xdf,0xcd,0x62,0xb9,0x19,0xfd,0x33,0x88,0xda,0xc4,0x37,0x98,0xe7,0x77,0xaf,
+  0x84,0x3d,0xf7,0x78,0x10,0xed,0xb8,0x9d,0xa2,0x53,0x02,0xd3,0xe1,0x61,0x06,0x3c,
+  0xaf,0x5b,0x1d,0x5a,0xec,0xf3,0x41,0x9e,0xa0,0x36,0x02,0xfd,0xf3,0xfa,0xf0,0xcb,
+  0x7b,0x94,0xda,0x9e,0x58,0xf1,0x1f,0xfc,0x3a,0xd1,0x6c,0xf5,0x28,0xcf,0x83,0x67,
+  0x80,0xfb,0x9b,0x32,0xf3,0x41,0x8c,0x99,0x1f,0x20,0xec,0x0c,0xd2,0x58,0x8a,0x02,
+  0xb8,0x20,0xfc,0xc9,0xeb,0xe2,0x65,0xd6,0x7c,0x90,0x11,0xaa,0xcf,0x45,0xc7,0xca,
+  0x4d,0x81,0x32,0xad,0xc5,0x1e,0xff,0xb9,0x0c,0x0d,0x66,0xc1,0xb8,0xfc,0x82,0xfe,
+  0x01,0x9a,0xf5,0x4d,0xe7,0x9f,0x44,0x20,0x64,0x58,0xf8,0x70,0x02,0x3e,0x61,0x37,
+  0x8f,0x58,0x8d,0x58,0xa7,0xef,0x6f,0x6a,0x3f,0x41,0xb4,0x49,0xf9,0x35,0x79,0x25,
+  0xaa,0x81,0xc0,0x80,0x2b,0x55,0x7f,0x17,0x34,0x9d,0xb1,0x19,0xdb,0xe0,0x30,0x0b,
+  0x0c,0xe3,0xa9,0xb8,0x1d,0xff,0x0c,0x77,0xaf,0x2a,0x3b,0xc5,0x9f,0x65,0xf3,0xf5,
+  0x75,0x9f,0xf7,0x34,0xa9,0x7b,0x59,0x65,0x3f,0x01,0x21,0xfe,0x92,0xfc,0x37,0xcb,
+  0xdf,0x68,0xf7,0x24,0xf2,0xff,0x98,0x85,0x7f,0x96,0xa3,0xbd,0x2e,0x37,0xf9,0x7e,
+  0x76,0x14,0xba,0xb7,0xe8,0x49,0x75,0x3f,0x02,0xe9,0xee,0xcd,0x5f,0x1b,0x41,0x9f,
+  0xf6,0x01,0xd8,0xa6,0x79,0x7b,0xf0,0xc5,0xe3,0x99,0xf9,0x20,0xd2,0x2c,0x63,0x0d,
+  0x19,0xfd,0x09,0xf6,0x23,0xe8,0x8c,0x96,0x8e,0x5e,0xb3,0x9a,0xbd,0x28,0xd1,0x04,
+  0x31,0x38,0x89,0xfa,0xe7,0x05,0x31,0x2f,0xf6,0xe9,0xd5,0x59,0xf5,0x5f,0xb9,0xc6,
+  0x2f,0xd0,0xfb,0x76,0xfa,0xad,0xb1,0x20,0xfa,0x2b,0xb2,0x5f,0xde,0x60,0x74,0x6a,
+  0xb3,0x4c,0x9f,0xce,0x9e,0x80,0xb7,0xa1,0x2e,0x82,0xa7,0x36,0x67,0xea,0xbf,0xae,
+  0xdd,0x6b,0xf5,0xc7,0x9e,0x4f,0xf8,0x19,0xf1,0xe1,0x10,0x01,0x69,0xf6,0x12,0x34,
+  0x0e,0x5a,0x81,0xc4,0x37,0xa3,0xfb,0xa8,0x50,0xce,0xce,0xff,0x19,0x9a,0x9a,0x8f,
+  0x56,0xb4,0x8b,0x06,0xcd,0x53,0x22,0x72,0x97,0xd5,0xa6,0x7e,0x83,0x90,0xbb,0x52,
+  0xf3,0xc1,0x77,0xdb,0xfb,0xff,0x14,0x3e,0xce,0x36,0x41,0x59,0xc2,0x9a,0x0f,0x42,
+  0x6c,0x9f,0xbc,0x29,0xc7,0xca,0x74,0x0c,0xa3,0xb0,0x11,0x4a,0x17,0x51,0xfe,0x2b,
+  0x5d,0xff,0x65,0xc2,0x8b,0xda,0x5a,0x31,0x6f,0xcc,0x71,0x3f,0xbe,0x6f,0x6f,0x47,
+  0x69,0x32,0x6f,0xc2,0x81,0xfe,0xa3,0x59,0xf9,0x36,0x1f,0x65,0xcf,0x51,0xe1,0x7f,
+  0x88,0xdf,0x67,0xab,0xa7,0xa0,0xf9,0xb0,0x29,0x6b,0x8e,0x6a,0x67,0x4f,0xab,0xbe,
+  0x35,0xaf,0x90,0xda,0x20,0x77,0xf8,0x42,0x44,0xbc,0x87,0x30,0xe8,0x5f,0xc0,0xf5,
+  0xcc,0xd4,0x7f,0x8d,0xce,0xec,0x83,0xc3,0x50,0x2f,0x10,0xff,0xac,0x87,0x4b,0x50,
+  0x44,0x83,0xc5,0xbd,0x56,0x46,0xcc,0x19,0xa3,0x88,0x10,0xdb,0x1d,0xf7,0xc5,0xec,
+  0xf5,0x5f,0x90,0x6c,0xb1,0x8a,0xdc,0xbb,0xac,0x34,0xc4,0xf3,0x53,0x63,0x41,0xd0,
+  0x5e,0xd0,0x11,0xf7,0xe4,0xf4,0x7c,0xd8,0xe9,0xf5,0x41,0xfc,0x13,0x3d,0x34,0xdd,
+  0x36,0xf9,0x3d,0x08,0x84,0x94,0xad,0xf2,0x1c,0x38,0x14,0x0d,0x18,0x1b,0xac,0x8a,
+  0x21,0x2d,0xd0,0xc2,0xa3,0x59,0xf5,0x5f,0x88,0x7f,0xa4,0xed,0x86,0x77,0xcb,0x7a,
+  0x0a,0x3b,0x6c,0x6f,0xe1,0x0f,0x31,0xc4,0x3f,0x02,0x8f,0x3c,0xee,0x28,0x67,0xaf,
+  0x9b,0xdb,0x57,0xf1,0x2b,0xf1,0xcf,0x43,0xd3,0x63,0xd1,0x88,0xc8,0xe1,0xb0,0xe6,
+  0x7d,0xe0,0x11,0x47,0x21,0xea,0xe7,0xef,0x71,0x4f,0x73,0x85,0x66,0xab,0xff,0x22,
+  0xfc,0xf3,0x90,0x57,0x6f,0xe3,0xd6,0x65,0x15,0x2b,0x8c,0x7a,0x74,0xbb,0xb8,0x04,
+  0x21,0xc3,0x1a,0x9c,0xf1,0x3d,0x88,0xb5,0x39,0xdc,0x61,0x47,0xba,0xfe,0x82,0xf0,
+  0xcf,0x49,0x3d,0xc0,0x37,0x22,0xfe,0x61,0x09,0xbd,0x4e,0x72,0x08,0x89,0x1a,0xd1,
+  0xf8,0xa1,0x20,0x86,0xdf,0xd7,0x29,0xe6,0xe6,0x05,0x61,0x7b,0xfd,0x17,0xe2,0x9f,
+  0x0f,0x52,0x20,0x27,0x85,0x7f,0xf2,0x97,0x85,0x53,0x65,0xef,0x56,0xfc,0xe7,0x62,
+  0x4a,0xb0,0xd7,0x7f,0x8d,0x4c,0x0f,0x01,0x41,0xeb,0xef,0xef,0xa5,0xec,0x58,0x0a,
+  0xff,0x2c,0x45,0xfc,0x93,0x3a,0xb5,0xf9,0x4f,0xf1,0x8f,0xc2,0x59,0xd8,0x14,0x7d,
+  0x7e,0x0f,0xf5,0xc7,0x06,0x88,0x78,0x19,0x57,0xf1,0xb7,0xd5,0x05,0xaf,0x50,0xf8,
+  0x40,0xf8,0x41,0x9b,0xfe,0xf9,0x55,0x14,0xfd,0x7d,0x83,0xd0,0x0e,0xe2,0x9f,0xd2,
+  0x56,0xb5,0x1d,0x8a,0x81,0xea,0xdf,0xbb,0x8f,0xb3,0x73,0x1d,0x6b,0xa4,0x52,0x23,
+  0xf2,0x79,0x5b,0xfd,0x57,0xc9,0xcc,0x1f,0x4f,0x17,0xcd,0x9d,0x33,0x10,0xff,0xb4,
+  0xaa,0xc7,0x1d,0x35,0x62,0x63,0x69,0x19,0x55,0xd8,0xd5,0xb0,0x8d,0x30,0xcf,0x30,
+  0x86,0xb3,0xea,0xbf,0x46,0xd8,0x3a,0xe8,0x25,0x12,0x17,0xe1,0x19,0xcf,0x32,0x02,
+  0x72,0xac,0x1f,0xac,0xb1,0x2f,0x83,0x88,0x60,0x89,0xdf,0xa5,0x7a,0xd3,0xfd,0x37,
+  0x7a,0xa6,0xf3,0x5f,0x8f,0xe3,0xf5,0x67,0xd3,0x89,0xb0,0xae,0x17,0x43,0x56,0x22,
+  0x2c,0x85,0x7f,0xb2,0xe7,0x83,0xe8,0x93,0x7c,0x21,0x73,0x11,0xdb,0x79,0x48,0xaf,
+  0x66,0x56,0x3d,0xef,0x10,0x4b,0x55,0x20,0x8a,0x53,0x56,0x04,0x52,0x65,0x36,0xfc,
+  0x33,0x0f,0x9e,0x37,0x3d,0x71,0x2a,0xd2,0xa1,0xb6,0x3f,0x51,0xe7,0xce,0xd4,0xa0,
+  0x2b,0xa1,0xea,0x9e,0xf7,0x99,0xc5,0x88,0xce,0xaa,0xff,0xca,0xb9,0x1b,0xfa,0x86,
+  0xe7,0xd6,0xa8,0x53,0xed,0x05,0x35,0xde,0xd5,0x94,0xb4,0x88,0xa9,0x78,0xe4,0x65,
+  0x74,0xed,0x75,0xca,0x30,0x66,0xea,0xbf,0x62,0x30,0x8b,0xda,0x76,0x99,0x94,0x7f,
+  0x97,0xd6,0x1a,0xa5,0x49,0xef,0xaa,0xa6,0x53,0xd3,0xb0,0xe7,0x13,0x8d,0x2a,0xaa,
+  0x54,0xbf,0xad,0xfe,0xab,0x87,0x5f,0x0d,0x7b,0xc5,0x0d,0xba,0xeb,0xce,0x22,0x37,
+  0x0c,0x89,0x3d,0x31,0xe7,0x8a,0xe6,0x37,0x38,0xcd,0x07,0xd9,0xb4,0x1a,0x3f,0x93,
+  0xb5,0x16,0xff,0x59,0xb5,0xd5,0x7f,0xcd,0xda,0xe9,0xb4,0xc2,0x3e,0x31,0xd5,0xb2,
+  0xef,0xc6,0x83,0x94,0x46,0x24,0x22,0x10,0x7e,0x56,0x43,0x30,0x8a,0x5a,0x00,0xed,
+  0x7b,0xa6,0xfe,0x0b,0x72,0xfe,0xc0,0x97,0x52,0x90,0x27,0x21,0xdf,0x63,0x5c,0x16,
+  0xd5,0xa1,0x47,0x5e,0x97,0x3f,0x6a,0x1d,0xeb,0x08,0x50,0xd9,0xfb,0x8b,0xf8,0x5f,
+  0xac,0x9e,0xe3,0x3c,0x24,0x67,0xf0,0x49,0x4f,0x61,0x04,0xba,0xf4,0x4a,0x50,0x57,
+  0xdd,0xf3,0x26,0xec,0xd5,0xca,0x44,0xe5,0xdd,0xec,0x12,0x6c,0x32,0xca,0x46,0x51,
+  0xed,0xf8,0x9b,0xd6,0x96,0x6c,0x33,0xf9,0xdf,0x3b,0x2a,0x32,0xf5,0x5f,0x08,0x79,
+  0xad,0xb7,0x6b,0x67,0xc3,0x68,0xb8,0xb7,0x0d,0xe2,0x65,0x13,0xb1,0x1f,0x97,0xcc,
+  0xe1,0xa8,0xc1,0x1e,0xb7,0x2a,0xc8,0x5a,0x5b,0xe7,0xda,0xf1,0x4f,0x52,0xb3,0x56,
+  0xcf,0xeb,0x1e,0x32,0xe2,0xb8,0x9e,0x25,0x79,0xb9,0xaf,0xe6,0x75,0xc0,0xf2,0x41,
+  0xde,0xc5,0x88,0xfd,0xab,0x53,0xa1,0x2b,0xb7,0xd5,0x7f,0x51,0xa3,0x82,0xa0,0xe4,
+  0xea,0x91,0x3f,0x84,0xbe,0x44,0xc0,0xc9,0x05,0x6e,0x8c,0xa7,0xc4,0x73,0x49,0x7d,
+  0x8d,0xbc,0x1d,0x5a,0x07,0x2c,0xfe,0x73,0x45,0xa6,0xfe,0x0b,0x3e,0x4c,0x85,0xc5,
+  0x1e,0x92,0x4f,0xc3,0x45,0xdd,0x2a,0x84,0x7f,0x4f,0xbb,0x60,0xd4,0x13,0x2d,0x7c,
+  0x6c,0xc9,0x45,0xde,0x60,0xba,0xa2,0xd5,0x99,0xfe,0xd8,0x92,0x36,0xc1,0x4f,0x10,
+  0x49,0x3e,0x55,0xdd,0x5c,0x2d,0x0a,0x52,0x34,0x8f,0x32,0xd4,0xe7,0x0e,0x3f,0x02,
+  0xa1,0x5e,0x93,0x7b,0x6d,0xf5,0x5f,0xc4,0xff,0xb1,0xda,0x5c,0xaf,0x63,0x49,0x71,
+  0x00,0xac,0x34,0xfa,0x69,0xd1,0x07,0x01,0x3f,0x6e,0x03,0x1a,0x64,0xe6,0x81,0xd6,
+  0x68,0x56,0xfd,0x57,0x39,0x3c,0x46,0x7c,0xe9,0x18,0x1b,0x33,0xf6,0x58,0xfd,0x37,
+  0xac,0x42,0x8c,0x8a,0x81,0x6e,0xc1,0x76,0x31,0xa1,0x78,0xc0,0xb1,0x8d,0xc5,0x6c,
+  0xf5,0x5f,0xf3,0xac,0xa6,0x0a,0xaa,0xd6,0x44,0xbe,0x13,0xe2,0x1f,0xdd,0x9d,0x40,
+  0xa0,0x35,0xca,0x16,0xfb,0x1d,0x31,0x4b,0x75,0xa3,0x06,0xb3,0xcd,0x07,0xc9,0x4f,
+  0x35,0xf9,0x59,0x1a,0x6f,0x1a,0x9b,0x1a,0x0b,0x52,0x34,0xb6,0xf3,0xa2,0x72,0xb5,
+  0xf9,0xd7,0xe4,0x71,0xbf,0x8c,0x47,0xaa,0x62,0xaa,0x1d,0xff,0x0c,0x6b,0x53,0xfc,
+  0xe7,0xf1,0x45,0x93,0xf0,0x12,0xba,0x09,0x72,0x52,0xa2,0xc1,0x82,0xc4,0x00,0x4f,
+  0x01,0xa1,0xec,0xf9,0x20,0xe3,0xb1,0xb1,0xba,0xc6,0x02,0xe7,0xab,0x9d,0xf1,0xc3,
+  0x43,0xfe,0x6a,0xad,0x6a,0x90,0xea,0xdf,0xfd,0x8d,0xdc,0x37,0xd0,0xe9,0x17,0x43,
+  0xf5,0x7b,0x9c,0xce,0x87,0x3b,0xfd,0x52,0x06,0xff,0x7c,0x10,0x43,0xfc,0x73,0x92,
+  0x3f,0xe7,0xf6,0x19,0xdd,0x86,0xe7,0x24,0x5f,0x28,0xff,0xc4,0xec,0x0e,0xf9,0x4e,
+  0xde,0xb6,0xd7,0x4d,0x82,0xe7,0x64,0x64,0x67,0x56,0xfd,0x57,0xc2,0x1a,0x83,0xc2,
+  0xc1,0x61,0x76,0x89,0x40,0x6c,0x98,0x6b,0x9e,0x84,0x47,0xf8,0xcb,0x7f,0xce,0xdd,
+  0xdb,0x9d,0x3a,0x3a,0x1b,0x2d,0x91,0x2c,0xfc,0x53,0xb8,0x93,0xf2,0x5f,0x27,0x11,
+  0xe4,0xdc,0x46,0x65,0x65,0x10,0x89,0x31,0x3c,0xa2,0x54,0x41,0x9e,0x87,0xc5,0x58,
+  0x27,0xc4,0x44,0xab,0x68,0xf2,0xdb,0xf8,0xcf,0x23,0x94,0x06,0xf5,0x3b,0x1f,0x94,
+  0xdf,0xa1,0x69,0xa4,0xa8,0x96,0x3f,0x75,0xda,0x9b,0x38,0x69,0x35,0x52,0xd0,0x29,
+  0x10,0x21,0x9c,0x51,0x15,0x6c,0xf1,0x9f,0x1e,0x04,0x81,0xe8,0x74,0x7c,0x84,0x5f,
+  0xc7,0x85,0x0e,0x82,0x3d,0x65,0x07,0xf9,0x65,0xf1,0x5d,0x42,0x44,0x56,0xa0,0xcc,
+  0x98,0x1f,0xba,0x32,0xfe,0xa3,0xd5,0x6a,0xce,0xb0,0x7c,0x77,0xe8,0xbc,0x1e,0x18,
+  0x28,0x88,0xab,0xf3,0xbc,0x13,0xad,0xbd,0xa6,0x33,0xda,0xed,0x64,0x47,0x4a,0x28,
+  0xbe,0x91,0x95,0xff,0x42,0x85,0x3a,0xec,0xf9,0x15,0xdf,0x1b,0xf6,0x49,0x17,0x5a,
+  0x11,0x2d,0xaf,0x65,0x73,0xe1,0x80,0xf0,0x14,0x5f,0xdb,0xc3,0xca,0x8c,0x08,0xbe,
+  0x70,0x64,0x63,0x16,0xfe,0x09,0x19,0x42,0x5a,0x7e,0x9a,0xd7,0x05,0x5e,0x73,0xf6,
+  0x86,0x3d,0xe5,0x0e,0x08,0x94,0x3b,0xf7,0xc8,0x15,0xe5,0x11,0x1d,0x35,0x52,0xcc,
+  0x08,0x39,0x79,0x76,0xfe,0x8b,0x68,0x3f,0xba,0x1e,0x69,0x65,0x9b,0xe1,0x89,0x68,
+  0xe9,0x88,0xfa,0x2d,0x76,0xb5,0xb1,0x37,0xf2,0x37,0x49,0xfe,0x5f,0xc2,0xb3,0xf5,
+  0xb2,0x28,0x9a,0xfe,0x15,0xc2,0x1e,0xff,0x71,0x20,0x86,0xa8,0x21,0xfc,0x36,0xa4,
+  0xf4,0x6a,0xf1,0xc1,0xd9,0xda,0x0c,0x67,0xe8,0x22,0xd4,0x99,0x7c,0xb7,0xec,0xeb,
+  0x4a,0x6a,0xf1,0x16,0xe7,0x81,0xac,0xf8,0xcf,0x5e,0xaa,0xf6,0x02,0x57,0xc7,0xa7,
+  0x56,0xb5,0x7c,0xa2,0x35,0x2a,0x54,0x1d,0xd0,0x7a,0xbf,0xb6,0x10,0xe6,0xf7,0xa3,
+  0xa1,0x7f,0x4b,0x6b,0x8c,0xb8,0x12,0xcd,0xc3,0xee,0xe9,0xf5,0xe9,0x41,0xfb,0x45,
+  0xd1,0x1e,0x5f,0x5f,0x99,0x4f,0xbb,0x28,0xe8,0x6b,0x45,0xff,0xf7,0x88,0x55,0xb6,
+  0xd0,0xac,0xd3,0x8e,0x15,0x16,0x9f,0x33,0x13,0xff,0xe9,0x83,0x0d,0xb0,0x0d,0xb8,
+  0x81,0x2a,0xcf,0xcf,0xac,0xf9,0x8c,0x25,0xd0,0x95,0x5b,0x66,0x16,0xb4,0xa3,0x6a,
+  0x3d,0x08,0xdb,0x8c,0xc5,0x21,0xf6,0xd1,0x15,0xf3,0x61,0xf5,0x24,0xaf,0xb3,0xc2,
+  0xe6,0xa5,0x29,0x61,0x2a,0xfe,0x93,0x3a,0x82,0xaa,0x78,0xdc,0x56,0xff,0x65,0xa2,
+  0x11,0xa4,0x2e,0xb1,0x6e,0x80,0x78,0xa9,0x2e,0xb5,0x92,0x62,0x8f,0x50,0x3f,0x13,
+  0x62,0xcd,0xc6,0xf1,0x14,0x0a,0xc7,0xb3,0xe2,0x3f,0x87,0x15,0xdc,0x24,0x31,0x95,
+  0x60,0x4f,0xaf,0xf0,0xc5,0x9a,0xbd,0x08,0x74,0x7b,0xad,0x23,0xca,0x05,0xa5,0x57,
+  0xe0,0x0a,0x5c,0xc8,0xce,0x7f,0x69,0xe9,0xfa,0xf7,0x9b,0xc1,0xd5,0x5f,0x36,0x4c,
+  0xdb,0x46,0xb2,0xf2,0x5f,0xe7,0xdc,0x8d,0x8a,0x55,0xff,0x9e,0xd6,0xe7,0xda,0x48,
+  0x0a,0x04,0xa6,0xfa,0xe3,0x59,0xf5,0x4d,0x73,0xd8,0xa1,0xd4,0x58,0x90,0x72,0x65,
+  0xea,0x14,0x4b,0xdb,0x0b,0x0b,0xff,0x58,0x65,0x5f,0x4d,0x23,0x53,0x44,0x14,0x9a,
+  0x8f,0x06,0x14,0xf6,0xf1,0x94,0xe3,0xa9,0x98,0xf1,0x27,0xf8,0x87,0xe2,0x1b,0x79,
+  0x68,0xaf,0x51,0x55,0xcf,0x37,0xf2,0xda,0x3d,0x35,0xca,0x46,0x6a,0x2c,0x30,0x8c,
+  0x78,0x86,0x4c,0x79,0x5e,0xfb,0x15,0xf9,0x2f,0xea,0x76,0x98,0x47,0x69,0xaf,0x67,
+  0xad,0xfe,0x87,0xe1,0x59,0xb1,0x35,0xf3,0xb6,0xb5,0xf1,0x65,0xeb,0xe9,0x54,0x59,
+  0xdb,0xbc,0x2b,0xf3,0x5f,0x09,0xc4,0x3f,0xf9,0x61,0x39,0x29,0x26,0xf4,0x06,0x12,
+  0x40,0x98,0x78,0xc4,0xc9,0x64,0xbd,0x2b,0xa1,0xf7,0xf2,0xfc,0x01,0xb9,0x2a,0xbb,
+  0xfe,0x0b,0xf1,0xcf,0xed,0x9b,0x1f,0xb6,0x84,0xc3,0x55,0x56,0xda,0x8b,0x10,0x51,
+  0xef,0xc3,0x63,0x28,0xcc,0x6e,0xcb,0xcd,0xca,0x7f,0xcd,0x4c,0x83,0x1c,0x25,0x76,
+  0xc8,0x1f,0x98,0x9a,0x0f,0xab,0x07,0x68,0x3e,0x6c,0x39,0x9b,0x3a,0x35,0xd7,0xd6,
+  0xff,0xe7,0x34,0xe1,0x9f,0x1c,0x6f,0x38,0x1c,0x13,0x11,0xbf,0xee,0xa6,0xf9,0xb0,
+  0x46,0xc4,0xeb,0xe1,0xbc,0x93,0x95,0xa6,0xa0,0xd1,0x40,0x56,0xfe,0xeb,0xc4,0xc0,
+  0x1a,0x6d,0x9b,0xc1,0x7f,0xc9,0x8a,0xb7,0xaf,0xd1,0xb7,0x2d,0xf1,0x7e,0x8e,0x15,
+  0xbb,0xd7,0xf8,0xb7,0x59,0xf3,0xd1,0x86,0xad,0x53,0x9f,0xb7,0xc7,0x7f,0x72,0x76,
+  0x52,0x7d,0x22,0x7e,0xc3,0x6c,0xef,0xf4,0x3c,0x50,0x2a,0x04,0x2b,0x6b,0x6e,0x1d,
+  0xf6,0xd0,0x7a,0xe2,0xc2,0xb6,0xa3,0x63,0x32,0xbd,0x1f,0x62,0xc5,0x3b,0xad,0xdf,
+  0x77,0x56,0xb4,0xa8,0x3c,0xf5,0xb3,0x7e,0x5f,0x9d,0x4b,0x47,0xbe,0x91,0x8a,0xef,
+  0x41,0x60,0x99,0xef,0x51,0xd9,0x2b,0xd2,0xf1,0x07,0x78,0x62,0x8a,0x0f,0x66,0x65,
+  0xbb,0x1a,0x68,0x1a,0xec,0xa0,0xa0,0xf9,0x20,0xf3,0x35,0xf5,0x37,0x29,0x44,0xb4,
+  0x35,0x2b,0xff,0x15,0x05,0xcb,0x7e,0x99,0xaa,0x66,0x95,0x7d,0x59,0xf1,0x9f,0x41,
+  0x6d,0x41,0x89,0x93,0x3a,0xa2,0x9d,0xd2,0xaa,0x8b,0xf1,0x88,0x23,0xd3,0xff,0x47,
+  0xf1,0xc2,0x61,0xb1,0x9d,0xe2,0x3f,0x5e,0xb6,0x5e,0x78,0x10,0xcf,0x6f,0x47,0x20,
+  0x24,0xb6,0xf7,0x72,0x9a,0x18,0x72,0xd8,0xdc,0x4e,0xf5,0xef,0xdc,0x16,0xff,0x31,
+  0x98,0x10,0x54,0xf6,0xe5,0xa0,0x66,0x7f,0x31,0xe0,0x96,0x10,0x89,0xe9,0x1c,0x9d,
+  0x85,0x26,0x91,0x20,0x1c,0xe5,0x70,0xa4,0xf9,0x93,0xba,0xe4,0x84,0xb5,0x14,0xf4,
+  0x58,0xe5,0x69,0x80,0x4e,0x14,0x52,0x8d,0x6d,0x25,0x9d,0xfa,0x77,0x39,0x2d,0x3c,
+  0x80,0x47,0xbc,0x59,0xf5,0x5f,0xa6,0x58,0xa0,0xbb,0xb8,0xec,0x86,0x41,0x14,0x38,
+  0x95,0x7d,0x91,0xe0,0xa3,0x23,0x74,0xca,0xd9,0x2a,0x57,0x64,0xc5,0x7f,0xfe,0xce,
+  0x0a,0xb3,0x4b,0xe9,0xfc,0x57,0x92,0xa5,0x13,0x61,0x7f,0x67,0x51,0xa3,0xed,0xf5,
+  0x5f,0xd2,0xb8,0xb8,0x24,0x6e,0xb2,0xca,0xbe,0xb4,0xa3,0x54,0xff,0x35,0x8a,0x6e,
+  0xfb,0xb1,0xae,0xea,0x11,0xd7,0x7e,0xf9,0x79,0xe5,0x58,0xb8,0x1a,0xa1,0x91,0xad,
+  0x7e,0xb9,0xa7,0x70,0x83,0x8e,0xb0,0x76,0xd8,0x3b,0xe9,0xb8,0x56,0x6c,0xe4,0x3b,
+  0x4c,0x3e,0x1c,0x6e,0x80,0x2e,0x7e,0xa3,0x53,0x3d,0x14,0xae,0x89,0xed,0x84,0x52,
+  0x84,0x46,0xe1,0x0a,0x5b,0xfc,0x27,0x4a,0x6d,0x82,0x80,0x37,0x69,0xed,0xfc,0x01,
+  0x6a,0x6f,0x1d,0xb2,0xea,0xdf,0xe7,0xf4,0xab,0xf7,0xb2,0xad,0xdc,0xc2,0x7b,0x9c,
+  0xdd,0x6a,0xab,0xff,0x3a,0x0a,0xbb,0xa3,0xe5,0xc3,0xfc,0xe6,0xb9,0x4b,0x58,0x87,
+  0xa9,0xff,0x23,0x9f,0xe5,0x90,0x0c,0xf1,0xaa,0x57,0x57,0x15,0x36,0x03,0x62,0xed,
+  0xb1,0x99,0x6a,0x03,0xbb,0xd3,0x56,0xff,0xf5,0x53,0xda,0x0f,0xa3,0xce,0xbd,0xf2,
+  0x12,0xaa,0x06,0x35,0x67,0x6d,0x95,0xd1,0xd1,0x18,0xae,0x0d,0xb8,0x22,0xf2,0x93,
+  0x9f,0x4b,0x18,0x01,0x40,0x68,0xf4,0x97,0xb6,0xf8,0x4f,0x52,0xbf,0xc0,0xeb,0xdc,
+  0xae,0x07,0x8a,0xb6,0x85,0x3e,0xe2,0x0d,0xe8,0x65,0x77,0x0e,0x79,0x3f,0x66,0xc1,
+  0x84,0xcb,0xbf,0xe3,0x10,0x22,0xa2,0x83,0x94,0x08,0xdb,0x69,0x8b,0xff,0x5c,0x82,
+  0x7f,0x84,0xea,0xa4,0x73,0x75,0x51,0x50,0x79,0x8d,0xba,0xfd,0x0c,0x17,0x35,0xe0,
+  0x46,0x5a,0x40,0x1b,0xa9,0xc6,0xda,0x5a,0xca,0x7b,0x72,0xa6,0xff,0x4f,0x07,0x7c,
+  0x49,0x7f,0xc3,0xf0,0xf8,0xf9,0x06,0xb9,0x0c,0xde,0x68,0xf2,0xd4,0xf2,0x9d,0x0e,
+  0x3d,0x55,0x7f,0x1d,0x67,0x5e,0xab,0xb1,0x21,0xf5,0xff,0xb1,0xe5,0xbf,0x96,0x18,
+  0x8f,0xc1,0x3d,0x83,0x7c,0x37,0xf3,0x19,0xcf,0x80,0x95,0x9d,0xd1,0xe1,0x31,0xc5,
+  0xd3,0x4f,0x81,0x0b,0x2f,0x5d,0xef,0x88,0x65,0xcf,0x47,0x93,0xa2,0x88,0x08,0x70,
+  0x53,0xa1,0x36,0xb6,0x04,0xd4,0x24,0x51,0x5c,0xbf,0x56,0xd6,0x86,0x8b,0x4d,0x8d,
+  0x7f,0xb5,0x0a,0x5b,0xfe,0x8b,0x7f,0x95,0xff,0x3a,0x95,0x44,0x70,0x5a,0xd5,0xc4,
+  0xce,0xb8,0x15,0xf6,0xe9,0x35,0x7d,0xbd,0xb2,0x8f,0x51,0xfc,0xe7,0xc1,0x98,0xad,
+  0xff,0x4f,0xec,0xda,0x71,0xaf,0x35,0x04,0xb6,0xa3,0x39,0x6e,0xc5,0x4b,0x37,0x99,
+  0xd6,0x58,0xd8,0xf9,0x60,0x4d,0x58,0xa6,0x53,0xf9,0xc7,0x3b,0x6d,0xfd,0x0f,0xf3,
+  0xc7,0xb5,0x53,0xd4,0xcd,0xcc,0xec,0x4c,0xa2,0x1a,0xbf,0x09,0x0a,0xc2,0x9d,0xe3,
+  0x62,0xd2,0x13,0x80,0xa5,0xc6,0x33,0xfe,0x28,0xde,0x81,0xe7,0x1f,0x97,0xc7,0xd3,
+  0xf3,0x8c,0x4c,0x18,0x5a,0xde,0x1d,0xad,0x1a,0x16,0x07,0xd9,0x07,0xe2,0x00,0xd1,
+  0x7e,0x88,0xff,0x7c,0xa0,0xab,0x82,0x1a,0x45,0xfe,0x0c,0x9e,0x69,0xaf,0xc2,0xf7,
+  0x0d,0x67,0xe2,0x6f,0x09,0xe8,0x42,0x07,0xcd,0xa7,0x38,0xc0,0xdd,0xaf,0xf7,0x19,
+  0x56,0x23,0xa0,0x7e,0x25,0xae,0xe9,0x0a,0x79,0x1c,0x06,0x9e,0xd2,0xd0,0x43,0x1f,
+  0x48,0xc7,0x73,0x4c,0xa5,0xc7,0x58,0x07,0x55,0x83,0x5e,0x1a,0x8b,0x73,0x20,0xb5,
+  0xda,0x63,0x70,0x0d,0x54,0x9c,0x54,0xe3,0x4d,0xbb,0x28,0x23,0x3f,0xe8,0x88,0x35,
+  0x8d,0x67,0xfa,0x5b,0x2a,0x31,0x48,0x48,0xc1,0x50,0x55,0xac,0xe8,0xbd,0xf2,0x8b,
+  0x52,0xfd,0xf2,0x07,0x85,0x3c,0x96,0x87,0x66,0x17,0x96,0xc6,0xcb,0x48,0xff,0x54,
+  0x95,0xe4,0x47,0x8b,0xcc,0xf6,0xcc,0xef,0x7b,0x90,0x92,0x80,0x31,0x17,0x95,0x99,
+  0xa0,0xd9,0x0a,0x23,0x30,0x1e,0x2f,0x9c,0x50,0x82,0x49,0xc4,0x87,0x17,0xe1,0x52,
+  0x2e,0x22,0xa2,0x31,0x74,0xed,0xa7,0xef,0x7f,0x02,0x76,0xc2,0x61,0x29,0x68,0x54,
+  0xee,0x94,0xbd,0xf0,0x6b,0xa8,0x37,0x7c,0xdb,0x8b,0xc6,0xc8,0xbe,0x6b,0xce,0x5e,
+  0xb9,0x4b,0xfc,0x9a,0x84,0xa8,0x5c,0x97,0x89,0x27,0x14,0x7b,0xa9,0x5b,0x9d,0xb0,
+  0xb2,0x9f,0x11,0xc9,0xbb,0xad,0x84,0xd8,0xaa,0x31,0xe1,0x31,0x4b,0xd6,0x33,0x6f,
+  0xe4,0x64,0x89,0x27,0x99,0x4f,0xf5,0x44,0xd3,0x3f,0x6f,0x52,0xf1,0x6a,0x1d,0x02,
+  0xbd,0xb3,0x12,0xa6,0x28,0x5b,0xa5,0x50,0x17,0xa2,0x1d,0x93,0xc6,0x28,0x27,0x39,
+  0x34,0x1d,0xce,0x8b,0xb2,0x7b,0xa8,0x03,0xe4,0xf4,0xd3,0x03,0x5a,0xdf,0xab,0xe0,
+  0x81,0x48,0xe5,0x0a,0xef,0x8a,0xb0,0x43,0xac,0x5d,0xbf,0x22,0xc4,0x57,0xe4,0xbe,
+  0x29,0x9e,0x14,0xf3,0x3c,0xfc,0xbe,0xdc,0xab,0xa4,0x87,0xbb,0x42,0x81,0xbc,0xd6,
+  0x74,0x35,0x0e,0xc0,0x0a,0x70,0xc2,0xcb,0x46,0xb0,0xc7,0xa5,0xa9,0xb9,0x62,0x58,
+  0x8a,0x0b,0xde,0x20,0x0f,0xec,0x14,0x3c,0x96,0xf4,0x72,0x39,0xd2,0xb5,0x0c,0xe2,
+  0xb4,0xb5,0xdc,0xe9,0xeb,0x8d,0x99,0x56,0x3d,0x66,0xcb,0x7c,0x9a,0x17,0xf6,0x71,
+  0xe1,0xdc,0x96,0x19,0xa2,0x6c,0x08,0xfe,0x4a,0xbb,0x4a,0x41,0xb5,0x33,0x48,0x9f,
+  0x2a,0xe0,0x87,0x39,0x9c,0x99,0x3f,0x9e,0xdf,0x03,0xdf,0x12,0xf5,0xa6,0xd3,0x5f,
+  0xb4,0xcb,0xea,0xff,0xec,0x8a,0x32,0x04,0x42,0x5d,0x01,0xb3,0xc0,0x2f,0xfb,0x94,
+  0xd7,0xa1,0x36,0x49,0xfd,0x9f,0xd9,0xf4,0xf5,0x09,0xd8,0x82,0x68,0x3f,0x55,0x46,
+  0x0a,0x7b,0x49,0xdb,0x84,0x58,0x54,0x89,0xc3,0x3c,0x50,0xa9,0x89,0x43,0x58,0xb1,
+  0x1a,0xe8,0x7f,0x9c,0x5e,0x4f,0xb0,0xfa,0x1f,0xce,0xa3,0x26,0xcf,0x6f,0xc2,0x1e,
+  0x31,0x27,0xb9,0xb8,0x2e,0x34,0x7b,0xaa,0x23,0x62,0x38,0xd5,0xff,0x07,0x4f,0x65,
+  0xf2,0xef,0x09,0x25,0xc6,0xd1,0xad,0x60,0x9c,0xb3,0x7b,0x20,0xde,0x52,0xee,0xc6,
+  0x6d,0x26,0x8b,0xb8,0xe6,0xa5,0x8a,0x4b,0x43,0x13,0x2d,0xe5,0xc4,0xff,0xf9,0x65,
+  0xfa,0x7a,0xdc,0x6f,0x08,0x7b,0xea,0x85,0xb3,0x07,0x8d,0xce,0x85,0x4f,0x3f,0x17,
+  0xdd,0x14,0x43,0x6b,0x75,0x81,0xca,0xd6,0x74,0xd9,0xeb,0x3e,0xac,0xd5,0x0a,0x27,
+  0x22,0xc0,0xf4,0xf5,0x2b,0x60,0xaa,0x1e,0x79,0x91,0x4c,0xb4,0x28,0xf4,0xbe,0x0d,
+  0x75,0xbc,0x70,0x92,0x37,0x4a,0xae,0x41,0xf9,0xac,0x7f,0x0c,0xf5,0x49,0x01,0xe1,
+  0x9f,0xe9,0xeb,0xbd,0xf0,0xe3,0x8e,0x43,0x5a,0x03,0x15,0x31,0x11,0xda,0x69,0x68,
+  0x19,0xdc,0x2a,0xcf,0x50,0x0e,0xc5,0x82,0xcb,0x37,0x6d,0xed,0xcc,0xb5,0x02,0x1d,
+  0x2e,0xcd,0x36,0x3f,0x57,0x14,0xcf,0x9d,0x9e,0xee,0x6a,0x8d,0x85,0x6d,0xcf,0x7f,
+  0x14,0xf1,0xf3,0x3a,0xf1,0xb5,0x90,0xba,0x25,0x77,0x8e,0xbe,0xce,0xa2,0x06,0xc9,
+  0xa1,0x34,0x5e,0x2a,0x51,0xca,0xd1,0x28,0x7f,0x86,0xf0,0x4f,0x0d,0x50,0x99,0xb6,
+  0x7a,0xc2,0x0a,0x53,0xa0,0x70,0x7c,0x7d,0x0d,0x5f,0x03,0x5f,0x6a,0xb9,0x66,0xd8,
+  0x9d,0x5b,0x68,0x4c,0xff,0x5e,0x40,0x20,0xc7,0x82,0x3d,0xc5,0xbb,0x9f,0xf0,0x56,
+  0x1e,0x56,0x53,0xb0,0xa7,0x92,0x68,0x3f,0x24,0x6c,0x23,0x21,0x13,0x7f,0xbe,0x13,
+  0x42,0xe1,0x88,0x5e,0xcf,0x6f,0x0b,0xab,0x7a,0x78,0x54,0x27,0x22,0xb4,0x44,0xb0,
+  0xa7,0x2a,0xaf,0x3b,0xec,0xd6,0xc3,0x08,0x8d,0x22,0xae,0x01,0xf9,0xaa,0x74,0x7d,
+  0xc7,0xd6,0x99,0x56,0xdb,0xe7,0x36,0xe2,0x03,0xc7,0x1e,0x45,0x6b,0x9e,0x67,0xb5,
+  0x35,0xc6,0x2f,0x48,0xa6,0x7e,0xd7,0xe7,0xbd,0x0d,0x8b,0x89,0xff,0x93,0x9e,0xb7,
+  0x58,0x92,0xf7,0xfb,0xe2,0x8d,0x0a,0x82,0x1c,0xe2,0x3f,0xbf,0xa6,0x57,0x2f,0x42,
+  0xfd,0x5c,0xa3,0x58,0xfc,0x9f,0xe3,0x72,0x8d,0x7b,0x23,0x2c,0xb0,0xe2,0x3f,0x99,
+  0x7e,0x89,0xf0,0xb2,0x20,0xfe,0x8f,0x93,0xf8,0xcf,0x59,0xfd,0x7f,0x0a,0x3a,0xe4,
+  0x52,0xe8,0x21,0xfc,0x13,0x0e,0x3f,0x90,0xe9,0xff,0x0c,0x5d,0x27,0x3a,0x0a,0x2d,
+  0xfe,0xcf,0x60,0xac,0x03,0xf4,0x16,0x5e,0xe8,0x56,0x80,0x8e,0x80,0xc6,0x5a,0x8c,
+  0x8e,0x54,0xff,0xe7,0xab,0x33,0xfd,0x7f,0x10,0xcf,0x4c,0x91,0x7c,0xa6,0xd8,0x3e,
+  0xa9,0x79,0xbb,0xe8,0x08,0xc7,0x1d,0xcb,0x51,0xff,0x58,0xa7,0x7e,0x9a,0x89,0xff,
+  0x28,0x3b,0xf5,0x43,0xda,0x54,0xb7,0x43,0x0b,0xff,0x3c,0x9a,0x82,0x3d,0x84,0x6f,
+  0x5b,0xe0,0x90,0xd6,0x6b,0xf1,0x7f,0xd2,0xf8,0xe4,0x30,0xec,0x64,0xe7,0xc5,0x41,
+  0xa3,0x2a,0x15,0xd6,0x78,0x71,0xd1,0x7c,0x6d,0x93,0x25,0x18,0x16,0x71,0x88,0x84,
+  0xf9,0x14,0xff,0x49,0x7f,0x5f,0xd0,0xc1,0x86,0xa7,0xd9,0xce,0x26,0xba,0x6e,0x28,
+  0x90,0x16,0xa8,0x4f,0x1d,0x19,0xc6,0x17,0x75,0x82,0xcc,0xd2,0xf7,0x87,0x9c,0x0a,
+  0xc4,0x3f,0x9e,0x0e,0xbe,0xdd,0xea,0xff,0xfc,0xdd,0x9d,0xfc,0x6d,0xca,0x7f,0x09,
+  0x3d,0xcc,0xdf,0x96,0x57,0xeb,0x47,0xa5,0xb2,0xef,0xf3,0x18,0x83,0xb4,0xfe,0xe1,
+  0x5d,0x54,0x26,0x50,0x6e,0x96,0x94,0x38,0x7c,0xd4,0x06,0x73,0xc4,0xeb,0x73,0xe4,
+  0xa2,0x05,0x8f,0x85,0xbc,0x75,0xac,0xc0,0xd1,0xa9,0xc5,0x50,0xff,0xd8,0xe6,0x77,
+  0x4b,0x30,0xcb,0x8b,0xf8,0x67,0xa8,0x75,0x35,0xd5,0x2f,0x50,0xe1,0xd8,0x2a,0x36,
+  0x4b,0x27,0x22,0x2b,0x0f,0x39,0x96,0x28,0x9d,0xf4,0x69,0x07,0x58,0xda,0xdc,0x21,
+  0x9c,0xba,0x8a,0xfd,0xbc,0xa3,0x66,0x74,0x56,0x9d,0xec,0x82,0x9f,0x53,0xfd,0x42,
+  0x9d,0xd5,0x08,0x68,0x41,0x72,0xd6,0x9d,0x32,0x35,0x02,0x5a,0x10,0x72,0x7e,0x47,
+  0xce,0x28,0x38,0x2f,0x3c,0x11,0x7b,0x27,0x35,0xff,0x2b,0x35,0x08,0x6c,0xc6,0x34,
+  0x10,0xba,0x4e,0x73,0x8d,0x29,0xef,0xc3,0x6c,0x03,0x4f,0x65,0xea,0xfd,0x9b,0x94,
+  0x9d,0xed,0xc7,0xc4,0x55,0x23,0x05,0x13,0xf2,0x25,0x7e,0x2c,0x7a,0xd3,0x6f,0x5c,
+  0x13,0xcd,0x97,0xe0,0x58,0x8a,0xf6,0x53,0x0b,0x9f,0x6c,0xa9,0x26,0x41,0xcb,0xc4,
+  0x5b,0xda,0xbf,0x2f,0xd6,0x6a,0x65,0x67,0xa8,0xfe,0xd4,0xbb,0xb6,0xb0,0xf4,0x5d,
+  0xf5,0xeb,0xe1,0xa1,0xf2,0xb5,0x25,0x95,0x03,0xaa,0xce,0x8a,0x63,0xfb,0x56,0xcf,
+  0xc3,0xef,0x39,0x9c,0x89,0xff,0xc4,0xc4,0x83,0xfd,0x08,0x72,0x06,0x1d,0xab,0xd8,
+  0xa4,0xd1,0x59,0x3c,0x2f,0x41,0x85,0xff,0x4d,0x56,0x44,0x48,0x63,0xc5,0xfc,0x59,
+  0x28,0x7d,0x15,0x8f,0xac,0x48,0xdf,0xdf,0x28,0x7e,0xd0,0xe8,0x8c,0xea,0x88,0x7f,
+  0x68,0xba,0x5c,0xd4,0x93,0x54,0x6b,0x68,0xde,0x77,0x87,0x45,0x04,0x72,0x95,0x1c,
+  0x10,0x5e,0x43,0x6d,0x70,0xb7,0x67,0xf2,0xe3,0xca,0x4f,0xb4,0x6e,0x63,0x4f,0x72,
+  0xf6,0x5e,0xf9,0x32,0x3b,0x62,0x54,0x9c,0xbd,0x6e,0x96,0xfc,0x55,0xed,0x88,0x89,
+  0xf6,0xa8,0x77,0xf1,0xfc,0x45,0x17,0xd0,0xc2,0xba,0x26,0xd4,0xa6,0x8c,0x7e,0x80,
+  0x5d,0xe1,0x8b,0x7a,0xdd,0x00,0x55,0xbb,0x77,0x5c,0xd4,0x83,0x27,0x5d,0xdf,0x97,
+  0x87,0xc4,0x45,0xbd,0x61,0xc0,0x55,0xf3,0xf2,0x10,0xbf,0xe8,0x09,0xde,0xe9,0xf2,
+  0x77,0xc6,0x6c,0xbf,0xd7,0x16,0x44,0x0b,0x08,0x7b,0x56,0x97,0x35,0xc0,0x1f,0x4b,
+  0x8b,0xcc,0x8d,0xe3,0x72,0x95,0xb1,0xc9,0x6c,0x4c,0x3a,0xc7,0xe5,0x60,0xde,0x61,
+  0xa8,0x1e,0x46,0x0b,0x08,0x69,0x7b,0xd7,0xaf,0x94,0x6b,0x8f,0x45,0xd1,0xec,0xf6,
+  0xa5,0xca,0xb8,0x3e,0x26,0x41,0xe9,0x86,0x82,0x64,0xeb,0x56,0x36,0x6f,0x0d,0xe2,
+  0x99,0x45,0x34,0x1f,0x6d,0x51,0x26,0xfe,0xb3,0x1c,0x1e,0x23,0x33,0xdd,0x6b,0x5d,
+  0x5f,0x91,0xcc,0x4b,0xfd,0x43,0x34,0xd3,0x28,0x88,0x3e,0xc5,0xf3,0x0b,0x8b,0xff,
+  0x93,0xde,0x0f,0x9a,0xc2,0x1e,0x86,0xd8,0x90,0xd7,0xdf,0x46,0x44,0xe8,0xa7,0x5f,
+  0x8e,0xf8,0xdd,0x4e,0xb6,0x07,0x7c,0xaf,0x54,0xf8,0x1d,0x0a,0x3c,0x2c,0x01,0xd5,
+  0x7f,0xb1,0xcc,0xbc,0x15,0x7e,0x7f,0x74,0x0a,0xff,0x54,0xc2,0x45,0xe5,0xbe,0xa4,
+  0xd5,0xff,0xf0,0xd7,0x2c,0x68,0x56,0x3d,0x8b,0xf8,0x67,0x2b,0x02,0x21,0xe2,0xff,
+  0xa4,0xf3,0x17,0x1d,0x33,0x27,0x17,0xa1,0x7d,0x3f,0x89,0x2f,0x75,0x2a,0x76,0x19,
+  0x3f,0x1c,0xaa,0x07,0xf4,0x1d,0x53,0x1a,0x13,0x79,0x17,0x8a,0x26,0xc8,0xf4,0x1b,
+  0xae,0xf1,0xe6,0xa4,0xad,0xff,0xcf,0x78,0x64,0x68,0xce,0x4d,0x92,0x4b,0x74,0xae,
+  0x8a,0x4f,0x7a,0xaa,0xf9,0x94,0x63,0x4b,0x8c,0x68,0x29,0x29,0x26,0xf5,0x46,0xe6,
+  0x3c,0x91,0x3d,0xff,0xc2,0xd9,0x4d,0x24,0xde,0x3e,0x47,0x95,0x76,0x40,0x90,0xe0,
+  0xf9,0x5d,0xeb,0xdf,0x0d,0x57,0x8d,0x74,0xbe,0xc0,0x3e,0x2c,0x3e,0x20,0xaa,0x92,
+  0x8e,0xed,0x2c,0x9e,0xd6,0xcf,0x3c,0xa7,0x9f,0x75,0xde,0xe8,0x6d,0x39,0x82,0xfe,
+  0xb8,0xd3,0xdf,0x14,0x53,0xd4,0x52,0x66,0xa2,0xbd,0x5b,0x09,0x7f,0x05,0xac,0x1f,
+  0x68,0x50,0x23,0xaf,0x65,0x81,0xb4,0xfe,0x34,0xa5,0x5d,0xe8,0x23,0x79,0x84,0x1a,
+  0x07,0x9f,0xb0,0x1a,0x0b,0x44,0xdd,0x63,0xda,0x01,0xbd,0x8a,0x80,0xe5,0x98,0x78,
+  0x1e,0xa8,0xab,0xa0,0xbd,0xfe,0xbd,0x78,0x87,0x48,0xe4,0xd4,0x97,0x2e,0xdd,0xfa,
+  0x79,0x8f,0xff,0xef,0x89,0x7f,0x82,0x8a,0xa5,0xe5,0x7c,0x47,0xf0,0x16,0x57,0xbc,
+  0x79,0xa4,0xd8,0x4a,0x64,0x44,0x65,0x3d,0xfd,0xbe,0xa7,0xe1,0xc5,0xe8,0x5b,0xd0,
+  0x98,0x70,0xbd,0xdd,0xfc,0xa2,0x66,0x35,0x5e,0x48,0x76,0x4e,0xc0,0x87,0x82,0x06,
+  0x07,0xcb,0x17,0x50,0xff,0xe0,0xfa,0x84,0xb2,0xf2,0x5f,0x1d,0xd4,0x7d,0xbd,0x15,
+  0x8d,0x54,0xd2,0x8a,0xbf,0xf9,0xe2,0x72,0xb9,0xf6,0x3a,0x02,0xa1,0x07,0x7b,0x2d,
+  0x7e,0x42,0xef,0x60,0x36,0xff,0x59,0xa9,0xe2,0x75,0xac,0x8a,0x8a,0x4c,0xa9,0x30,
+  0xdf,0xa3,0xf3,0x07,0xe5,0x15,0xb0,0xbe,0xfc,0xea,0x58,0x81,0x60,0x67,0xa0,0x4f,
+  0x58,0xf1,0x64,0xff,0x95,0xf5,0xef,0x51,0xd5,0x8b,0x9f,0x49,0x3c,0x84,0x30,0xd8,
+  0xc9,0xf8,0x92,0xcd,0x87,0xbc,0x31,0x87,0x92,0x9b,0xa0,0x08,0xaa,0xae,0x6a,0x4d,
+  0x99,0xfe,0xcf,0xf7,0x48,0x6e,0xb4,0xfe,0x95,0xcb,0xd5,0xbf,0x62,0xc7,0xa5,0x27,
+  0xe3,0xdb,0xde,0xe6,0x13,0xec,0x56,0x63,0x8d,0x98,0x77,0x8f,0xe3,0xdb,0x9e,0x5f,
+  0x89,0x7d,0x11,0x04,0x06,0x7f,0xc3,0x1a,0xec,0xfc,0x1f,0xfd,0x63,0xf0,0xbd,0xea,
+  0xaa,0x08,0x0f,0x85,0xe2,0x3d,0x7e,0x8a,0xa6,0x72,0xe3,0x38,0xd4,0x89,0x02,0xc7,
+  0xa7,0x0e,0x47,0xcf,0x82,0xbf,0x05,0xf7,0x8f,0x3d,0xfe,0x13,0x9b,0xea,0x7f,0x58,
+  0x34,0xee,0x7c,0x8b,0x68,0x3f,0x51,0x76,0xae,0x95,0x2a,0x9a,0x37,0x9d,0x9d,0x71,
+  0xce,0xf8,0x0e,0x7c,0x46,0xa8,0x89,0xec,0xfe,0x3f,0x14,0xbf,0x15,0xbe,0x78,0x11,
+  0xc5,0x7f,0x10,0x96,0x6f,0x55,0x0b,0xa8,0x63,0xa7,0x59,0x19,0xc7,0xfd,0x79,0x58,
+  0x58,0xf1,0x9f,0x4c,0xfc,0x36,0x51,0x28,0x28,0x9e,0x6c,0x70,0x9a,0x72,0x44,0xdd,
+  0x30,0xb8,0x9e,0xe2,0x3f,0x23,0xec,0xd1,0x05,0xc2,0xd3,0x79,0x46,0x77,0x52,0xbe,
+  0x37,0x5d,0xff,0x95,0xe2,0xff,0xf8,0xac,0x68,0x8f,0xb4,0xaf,0x43,0x4a,0xe6,0xad,
+  0x76,0x7f,0x51,0x59,0xdb,0xe1,0x4b,0xb6,0xd5,0x95,0xcc,0x26,0xfe,0xf3,0xdb,0xaa,
+  0xbd,0xff,0x73,0x6b,0xb1,0x09,0x5b,0x29,0xde,0x98,0x8b,0xaf,0x14,0x9f,0xa3,0xf3,
+  0x3c,0xc6,0x0c,0x21,0xd0,0xdb,0xe4,0xac,0x09,0x1d,0x5c,0xca,0xbf,0x0b,0xb6,0x2c,
+  0x1d,0x3f,0x21,0xfe,0xf3,0x0f,0x68,0x93,0x10,0xbe,0xbd,0x80,0xd6,0x1c,0xd1,0xe9,
+  0x0a,0xb4,0x52,0x41,0x51,0xb0,0x5d,0x26,0x57,0x3a,0x40,0x1d,0x81,0xea,0xd2,0xfb,
+  0x81,0xe2,0x3f,0x63,0x53,0xf1,0x55,0xb4,0x46,0x2f,0x40,0xc1,0xe0,0x8c,0xb8,0x63,
+  0xc4,0xb8,0xd9,0xe2,0x3f,0x4f,0xb7,0x9e,0xc8,0xf0,0x7f,0x22,0xda,0xab,0xe2,0x10,
+  0xd4,0x18,0x1b,0x4a,0xe4,0xb9,0x1d,0x87,0x20,0xb8,0x02,0xad,0xf9,0x13,0x70,0x3e,
+  0x86,0xf6,0xb1,0x58,0x56,0xf8,0x21,0xd4,0xe7,0xb8,0x3e,0x19,0xfb,0x22,0xe0,0x2b,
+  0x64,0x6d,0xdb,0x23,0x5b,0xaf,0xb9,0x15,0x9e,0x1a,0xaf,0x0a,0xf1,0xc7,0xa9,0x10,
+  0x3b,0x56,0x1b,0xca,0xdf,0x2a,0x2f,0x27,0x44,0x44,0xfc,0xe7,0x98,0x6d,0xfe,0x45,
+  0x39,0x8d,0xbd,0x68,0xe2,0xbf,0x68,0xb2,0xfa,0xd5,0x58,0x81,0x20,0x4e,0x89,0x1b,
+  0x22,0xae,0x18,0x1b,0x2d,0xbe,0x0a,0xcb,0x4d,0xd7,0x8f,0x70,0x65,0x0b,0x82,0x9c,
+  0x79,0x34,0xe4,0xa2,0x66,0xdb,0x13,0x29,0x20,0x74,0x62,0xdb,0xb3,0xd4,0xf6,0xf0,
+  0xde,0xf0,0x1d,0xd3,0x40,0x28,0xd3,0xff,0xa7,0x8f,0xeb,0xe1,0x56,0x84,0x3d,0xce,
+  0x30,0xd3,0xad,0xb6,0x87,0xf9,0xdb,0xe5,0x98,0x45,0x84,0x4e,0x4f,0xc4,0x70,0x5d,
+  0x11,0xff,0x91,0xce,0x7b,0x6b,0x8d,0xeb,0xb5,0xa9,0xb2,0x6e,0x32,0xf4,0x34,0x2f,
+  0xd5,0x1a,0x8c,0xcb,0xa6,0xe6,0x5f,0x64,0xea,0xbf,0xa8,0xfe,0xfd,0xd0,0x34,0xff,
+  0x99,0xe6,0x5f,0xe0,0xc6,0xab,0xd1,0x5e,0x2b,0x4f,0xe1,0x1f,0xab,0x35,0x22,0xc5,
+  0x7f,0xd2,0xf1,0x99,0x3a,0xed,0x34,0x58,0x41,0x1e,0xe2,0x3f,0xd3,0xfc,0x0b,0x9a,
+  0xbe,0x6d,0x24,0xc0,0x03,0x9c,0xe6,0x5f,0x3c,0x0d,0x9e,0x2e,0xc4,0x3f,0xb3,0x33,
+  0xf8,0x3c,0x67,0xb0,0xad,0x43,0x8b,0x99,0x75,0x85,0xd4,0xdf,0x0f,0x7a,0x5a,0x64,
+  0x14,0x18,0x1e,0x21,0x57,0xac,0xab,0xd5,0x12,0x8a,0x1c,0x6e,0x69,0x7a,0xfd,0x89,
+  0xff,0xb3,0xce,0xf0,0xb4,0x13,0xfe,0xe4,0xfb,0xa1,0xc2,0x2a,0xa3,0x83,0x75,0xcc,
+  0x93,0x42,0xa4,0x4f,0xa1,0x10,0x79,0xc8,0xce,0xff,0xa1,0xf8,0x8f,0x08,0xb4,0x4f,
+  0xb5,0x75,0xaa,0x37,0x5c,0xd1,0x69,0xfc,0x13,0x9d,0xea,0x88,0xa8,0x6c,0x2d,0xca,
+  0xcc,0x87,0x7d,0x1a,0xf7,0xfa,0xd9,0x2c,0xda,0xb3,0xbb,0x73,0x44,0x7b,0x8f,0xa7,
+  0x23,0x42,0x41,0x63,0x53,0x49,0xd6,0xfc,0x0b,0xf2,0x47,0xfc,0x34,0xe6,0x9b,0x5e,
+  0x93,0x80,0x50,0x11,0x51,0x75,0x6a,0x60,0x16,0x1e,0x91,0x86,0x17,0xf9,0xb5,0x25,
+  0xa2,0xc8,0x56,0xff,0xae,0x78,0xe1,0x8c,0xf4,0x77,0x51,0x75,0x94,0x55,0x48,0x0f,
+  0x76,0x78,0x62,0x3c,0xe9,0xaa,0x28,0x7d,0x90,0x7b,0x62,0xd7,0x8e,0x32,0x07,0x6e,
+  0xec,0xda,0xd8,0xc6,0x18,0x8b,0xa4,0xf3,0x11,0xde,0x35,0x2d,0xce,0x1d,0x4c,0xdf,
+  0xaa,0x96,0x20,0xec,0xe9,0x6c,0x53,0x96,0xb7,0x96,0xb3,0x16,0xe8,0x5c,0x54,0x6e,
+  0xb4,0xce,0xf7,0x28,0x8b,0x3a,0x84,0xbe,0xfc,0x6a,0x7f,0x41,0x86,0xff,0x5c,0x2a,
+  0xcd,0xd2,0x77,0xb0,0x79,0x26,0x9a,0xf5,0xd9,0x14,0x08,0x4a,0x4e,0x0f,0x36,0x1a,
+  0xc8,0x5b,0xe5,0xb8,0x8b,0xad,0xe5,0x73,0xfa,0xd5,0x55,0x6e,0x7b,0xff,0x1f,0x9a,
+  0x0f,0x5b,0x4a,0xf5,0x5f,0x05,0x7c,0xad,0xb8,0x81,0xbc,0x95,0x2f,0x02,0x09,0xad,
+  0x75,0x65,0x34,0x31,0xd6,0x7f,0xba,0xa0,0xae,0xe8,0x6f,0x33,0xf5,0x5f,0x9f,0xde,
+  0x05,0xef,0x6b,0xa9,0x68,0x0f,0xba,0x41,0x56,0xb4,0x67,0x4c,0x99,0xaa,0x30,0xdd,
+  0x05,0xef,0xa4,0x5a,0x23,0xb2,0xcd,0xd3,0xeb,0x33,0xdd,0xff,0xc7,0x39,0x21,0xbf,
+  0x09,0xc7,0x3a,0x1a,0x93,0x4b,0x57,0xcb,0x41,0xc4,0x57,0x37,0x25,0x5d,0xfb,0xa7,
+  0x89,0xd0,0xfb,0x1f,0xb6,0xc7,0x7f,0x52,0xf5,0x5c,0x34,0xc6,0x42,0xef,0x9c,0x2a,
+  0x44,0xe5,0x7f,0xf4,0x94,0x26,0x0a,0xea,0xdc,0xa7,0xa8,0xd5,0xcf,0xab,0xa8,0x4f,
+  0x2a,0xd2,0xf9,0xb5,0x28,0x50,0xbd,0x98,0x8f,0x9a,0x5a,0xa7,0xd3,0x7c,0xb3,0x60,
+  0x1f,0x9b,0xd7,0xdf,0x7d,0x2f,0x3b,0xa5,0x59,0x44,0xe8,0x00,0xae,0xd8,0xf4,0xfa,
+  0x87,0x8a,0x87,0x5e,0xd9,0xf3,0x39,0xbc,0xbe,0x2e,0xf7,0x18,0x74,0xfa,0x7d,0x63,
+  0x6a,0x35,0x2b,0x80,0x1d,0x5b,0xac,0xb6,0x63,0x47,0x87,0xf6,0x74,0xf8,0xcc,0xee,
+  0x67,0x2b,0xec,0xf1,0x9f,0x8d,0x70,0xb9,0xbd,0x61,0xc5,0xd7,0xea,0x8a,0x3e,0x30,
+  0xd0,0x51,0xfd,0xc5,0x75,0x5b,0xd4,0x2a,0xfd,0x00,0xac,0x1e,0x75,0x69,0x45,0x1f,
+  0xc0,0xc5,0xc8,0x77,0xcc,0xa5,0xe7,0xca,0x32,0xf1,0x9f,0x28,0xa2,0x41,0xb4,0x47,
+  0x03,0x33,0xe3,0x0f,0x0f,0xa5,0xc2,0x62,0x35,0xd4,0xf6,0x99,0x07,0x07,0x1e,0x7c,
+  0xa8,0x13,0x81,0x22,0x0f,0xbe,0x8c,0xd0,0x28,0x13,0xff,0x79,0x48,0x7b,0x11,0xde,
+  0x92,0xaa,0x8d,0xfc,0xf1,0xb2,0xfb,0x11,0x16,0x2e,0x18,0x5d,0x32,0x2e,0xcf,0x36,
+  0x7e,0xce,0xaa,0x07,0x9d,0xe3,0x5f,0x9a,0x25,0xfd,0x1c,0xf1,0x0f,0x02,0xa1,0x4c,
+  0xfc,0xa7,0xbf,0xeb,0x6b,0x14,0xed,0xa1,0xf9,0x56,0x3e,0xad,0x3b,0x51,0x91,0xe4,
+  0x07,0x99,0x8f,0x77,0x27,0x3c,0x49,0x6f,0x9f,0x83,0x92,0xa2,0x3a,0x22,0x10,0xb6,
+  0x2d,0x53,0xff,0xa5,0xf8,0x5a,0xa9,0x3a,0x3b,0x6f,0x37,0x5b,0x29,0xba,0x35,0x04,
+  0x42,0x54,0xf6,0xd5,0x4d,0xfc,0xe7,0xbe,0xb0,0x4f,0x3c,0xa3,0x53,0xe0,0xc8,0x93,
+  0xc5,0x7f,0x56,0x1e,0x06,0x7d,0x6a,0xdb,0x68,0x5e,0x22,0xbe,0x3a,0x2d,0xfe,0x73,
+  0x84,0x26,0x62,0x3c,0x4c,0x11,0xa4,0x40,0x6e,0x46,0xff,0x08,0xbe,0x12,0xad,0x49,
+  0xaf,0x99,0xbf,0x5b,0x5e,0x89,0xf8,0xd0,0xca,0xb6,0xf8,0x58,0x37,0x21,0xa2,0xe7,
+  0x9a,0x2b,0xf9,0xfb,0x78,0xca,0x19,0x2f,0xb3,0xc7,0x7f,0x26,0x53,0x24,0xe7,0x8f,
+  0xa6,0x69,0xcf,0xe3,0xd3,0xc2,0xc7,0x9d,0x93,0xb1,0xa9,0xd2,0xb0,0x4c,0xfc,0xe7,
+  0xdf,0x34,0x8f,0x6f,0x96,0x09,0xb6,0xbf,0x7f,0xe7,0x3c,0x3e,0xde,0x85,0x7a,0x29,
+  0x62,0xa0,0xa7,0xf6,0x3f,0x17,0xe0,0xdf,0x77,0xff,0xec,0xe7,0x99,0x1a,0x8a,0xe7,
+  0x34,0xaf,0x14,0xac,0x53,0x43,0xff,0xdf,0x9a,0x87,0xe8,0x34,0xaf,0x14,0xfe,0xe5,
+  0xbf,0xff,0x1f,0x98,0x87,0x68,0xdd,0x76,0x4a,0xa0,0x23,0x5a,0xc6,0x7f,0x4c,0xdd,
+  0x7f,0x08,0x6f,0x32,0xcb,0xfc,0x9f,0xde,0x3f,0xeb,0xf7,0x62,0x14,0x84,0xc3,0x65,
+  0xd3,0xfe,0xe7,0x2b,0x9a,0xfd,0xfc,0x82,0x6e,0x02,0xa9,0xe2,0xb0,0x7f,0x79,0xfd,
+  0x6d,0xd7,0xa7,0xe6,0x21,0x0e,0xfd,0xeb,0xcb,0xee,0xec,0xff,0xcf,0x79,0x88,0xff,
+  0x41,0xe6,0x0f,0xfe,0xc7,0xbb,0x9e,0xad,0xf5,0xff,0x3f,0xfa,0x3d,0xfe,0xbb,0xf5,
+  0x21,0x7e,0x86,0xff,0xef,0x9c,0x0f,0xfb,0x3f,0xff,0x21,0xfe,0x77,0xd6,0x3f,0xa3,
+  0x9d,0xc4,0xbf,0x59,0x1f,0xa6,0x8c,0xce,0x94,0xf6,0xfb,0xcf,0xf9,0xb0,0xb6,0xbf,
+  0xff,0xd4,0x87,0xff,0x7f,0x7e,0xfd,0x9a,0x45,0xf2,0x2a,0xe3,0x94,0xb6,0x10,0xf2,
+  0xfb,0x2d,0xe1,0x7f,0x14,0xe7,0xaf,0x91,0xbf,0xbe,0xe8,0x2e,0x6d,0x61,0x71,0xfe,
+  0x2b,0x33,0xbe,0x6e,0xcc,0x6a,0xff,0x94,0x92,0x6f,0x2e,0x48,0x5f,0x3f,0xb8,0x24,
+  0xe7,0xeb,0xd2,0x5d,0xc6,0x5f,0x68,0xc6,0x60,0x4a,0x28,0x29,0x4e,0x09,0xcd,0xda,
+  0xcc,0x41,0x29,0x75,0x6a,0xa6,0x59,0x98,0xce,0x50,0x75,0x38,0x24,0x5d,0xb4,0xea,
+  0x6e,0x0e,0xe1,0x29,0x41,0x79,0xc0,0x12,0x3e,0x45,0x42,0xa9,0x68,0x0d,0xe1,0x91,
+  0x4c,0x78,0x1b,0xb1,0x83,0x14,0x82,0x3b,0xe1,0x2a,0xf8,0x9e,0x20,0x41,0xfa,0x82,
+  0x96,0x23,0xa4,0xbb,0xe1,0x4e,0x76,0x15,0x0a,0x39,0xa1,0x8e,0x3b,0xe1,0x0b,0x90,
+  0x63,0xbb,0x7e,0xf0,0xce,0x9c,0x5a,0xe9,0x36,0xf1,0xf9,0x45,0x0a,0xcf,0xb9,0x57,
+  0xba,0x4b,0xfc,0x85,0x3e,0xf3,0x70,0xce,0xbd,0x1d,0x28,0x78,0x67,0x26,0xa6,0x8f,
+  0x98,0x0b,0xd2,0xcf,0xb3,0xe6,0xb3,0x86,0xae,0x95,0x28,0x2c,0x07,0x3f,0xd6,0x10,
+  0x94,0x40,0x2e,0x48,0xe2,0x4f,0x85,0xcc,0xfb,0xbe,0x62,0x28,0xf7,0x48,0x5c,0xdc,
+  0xaa,0xc3,0x06,0xc5,0x23,0x71,0xb3,0x49,0xd7,0x22,0x4a,0x29,0x1e,0x69,0xf2,0x6b,
+  0x61,0x45,0x97,0xa8,0x1b,0xbe,0x66,0xbf,0xbe,0x29,0x67,0x59,0xc7,0x1d,0xb1,0x3f,
+  0xf7,0x2a,0x8e,0x9c,0xa6,0x8e,0xf6,0x78,0xb1,0x77,0xa6,0x23,0xc7,0xe8,0x68,0x8f,
+  0xdd,0xe1,0x9d,0x99,0x2b,0x19,0xa2,0x5d,0x2f,0x6e,0x98,0x09,0x99,0xe7,0x11,0xc5,
+  0xd2,0x0c,0xf8,0x73,0x73,0x66,0xbb,0x32,0x4b,0xfa,0x0b,0x14,0x0a,0x57,0xe5,0xdc,
+  0x25,0x7d,0x1e,0xee,0x30,0x67,0xd6,0xe5,0x7c,0x51,0x92,0x2d,0x41,0x49,0x87,0x7f,
+  0xf0,0x7a,0x5d,0x10,0xf7,0x47,0x11,0xa8,0xfc,0x50,0xf3,0x85,0x24,0x52,0x81,0xcd,
+  0x02,0x75,0xa1,0x26,0x29,0xa8,0x1a,0x34,0xea,0x95,0xb5,0x28,0x73,0xfd,0x2b,0x2b,
+  0x18,0x31,0x1d,0x74,0x41,0x49,0x33,0x14,0x4a,0x05,0xd7,0xa7,0x8e,0x70,0x3d,0x77,
+  0x4a,0x58,0x94,0x79,0x9e,0x57,0xda,0xa5,0x72,0xe9,0xbf,0xc0,0x17,0x0c,0x25,0x9a,
+  0xb3,0x1c,0x85,0xab,0x8c,0x99,0xd1,0x9c,0x90,0x74,0x12,0x97,0x1d,0x05,0x1d,0x85,
+  0x6f,0xc2,0xcc,0xac,0xf5,0x91,0x69,0x82,0xd6,0x55,0xf8,0x44,0x96,0xf0,0x4d,0xc8,
+  0x17,0x45,0xf7,0xa0,0xb0,0x10,0xf2,0xc4,0x8c,0x7b,0xe0,0x4e,0x71,0x15,0x1e,0xb1,
+  0xaf,0x8f,0xe2,0xef,0x70,0xea,0x32,0xe7,0x61,0x4b,0x68,0xe6,0xda,0x80,0xe2,0x17,
+  0x4e,0xfd,0x56,0x14,0xd8,0xd4,0x11,0xdb,0xfe,0x11,0x90,0x4a,0x81,0x90,0x34,0x25,
+  0x98,0x56,0x75,0x16,0xa3,0x64,0xa3,0x5f,0x99,0x3a,0x92,0x59,0x1f,0x26,0xf9,0xc5,
+  0x12,0xbd,0x88,0x2b,0x61,0x12,0x4a,0x51,0x18,0x90,0xfc,0xfd,0xd6,0x91,0x23,0x24,
+  0xf8,0x3f,0xcf,0x15,0xd3,0xb6,0x3e,0x4d,0xb4,0xa9,0xf4,0x2f,0x80,0x12,0xb6,0x84,
+  0xab,0xf8,0x4c,0x14,0xfa,0xf1,0x08,0x9f,0xd9,0x99,0xa3,0xf7,0xdf,0xe9,0x47,0x41,
+  0x64,0x9e,0xe7,0x95,0x26,0x6b,0xe5,0xd2,0x4b,0x38,0x25,0x38,0x33,0x82,0xcc,0xc1,
+  0xfe,0xbe,0xcb,0x94,0x50,0x47,0x89,0x7e,0x6b,0x2b,0x6c,0x46,0xe1,0xd3,0xb8,0xe4,
+  0x85,0x61,0x65,0x39,0xbe,0xe6,0xad,0xad,0x85,0x9b,0x15,0x9d,0xde,0xb7,0xb5,0x50,
+  0x14,0x66,0xae,0x0f,0xe5,0xdc,0x29,0x5d,0x05,0x7f,0x2e,0x14,0x1d,0x05,0x5c,0x74,
+  0x31,0x13,0x8f,0xc0,0xad,0x78,0x64,0x66,0x48,0xe2,0x28,0x14,0x8a,0x99,0x86,0x6d,
+  0xff,0xe4,0x4a,0x9f,0x13,0x77,0x85,0x3e,0xb5,0x55,0xca,0x95,0x16,0x89,0xf6,0xd0,
+  0x1d,0x25,0x39,0x29,0xa1,0xd8,0x26,0xa0,0x59,0x4a,0x5f,0xef,0xb6,0xcc,0x88,0xd1,
+  0x0a,0x6e,0x09,0xc4,0x22,0x5d,0xe3,0x0a,0x93,0x14,0x81,0x1f,0x45,0xab,0xe2,0x2e,
+  0x84,0x94,0x60,0x4b,0xcf,0xbe,0x72,0x2b,0x2b,0x14,0x5d,0xa1,0xbb,0x4b,0x4a,0x6e,
+  0x95,0x3f,0x27,0x4e,0x84,0x6e,0x28,0xc9,0x27,0xe1,0x0e,0x4b,0x98,0x91,0x3a,0xe2,
+  0xb4,0x3d,0xcf,0x2b,0xb7,0x4a,0x5f,0xef,0xb8,0x2b,0xf4,0x17,0xda,0xb5,0xaf,0xe6,
+  0x90,0xf0,0xa9,0x92,0x99,0x96,0x80,0x8a,0xc2,0x12,0x4e,0x85,0xfe,0x47,0xc9,0x4c,
+  0xdb,0xfb,0xde,0x72,0xab,0xfc,0x75,0xf1,0x78,0x68,0x61,0x49,0xce,0xab,0x28,0x9c,
+  0x0a,0xfd,0x45,0x49,0x3e,0x09,0x77,0xe1,0x91,0xfc,0x57,0xa5,0xbb,0xe9,0xd5,0x4a,
+  0xf2,0x4d,0xfb,0xf5,0xd6,0x6d,0xff,0xe2,0x4e,0xc9,0xba,0xed,0xdd,0x53,0xf7,0x57,
+  0x42,0x74,0x7f,0x69,0x41,0x87,0x33,0xd4,0x5c,0x52,0x6c,0xdb,0x3f,0xc0,0xa6,0xd5,
+  0x4e,0x4a,0xff,0x2c,0x4b,0x09,0x77,0x59,0x47,0x72,0x48,0xf8,0x14,0xcf,0x11,0x99,
+  0xfd,0x03,0xb9,0xf8,0x1f,0xbd,0x33,0x74,0x55,0x49,0xf1,0x03,0x53,0x42,0x0e,0x0a,
+  0x1d,0x36,0xe1,0x0b,0x25,0xf6,0xeb,0x6f,0x31,0xe6,0xf8,0xa5,0x25,0xf0,0x79,0xdc,
+  0xff,0x39,0xab,0xa4,0xbb,0xe0,0x53,0x30,0xd3,0xb4,0x84,0xbf,0x40,0x41,0xf2,0x4f,
+  0x09,0x99,0xe7,0xb9,0xa5,0x89,0x72,0xff,0x5e,0x56,0x80,0xbb,0x25,0x24,0x4a,0x70,
+  0x3f,0x48,0x19,0x41,0xd1,0x53,0x82,0x7d,0x7d,0xda,0xba,0x42,0xdb,0x70,0xff,0x38,
+  0x00,0xcf,0x76,0xd0,0x7e,0xd3,0x52,0x42,0x13,0x09,0xa1,0x94,0x60,0xbf,0x7e,0x51,
+  0x4e,0xbb,0x74,0x87,0xfb,0xcf,0xa1,0x8b,0x29,0xa8,0x76,0xf4,0x62,0x3e,0x93,0xe5,
+  0x18,0xe2,0x73,0xfa,0x1d,0x7c,0xa6,0x9c,0xd3,0x2e,0xac,0x23,0x60,0x5b,0x1f,0x55,
+  0x6a,0x4f,0xdc,0xe1,0x9f,0xc9,0x95,0x66,0xa9,0xdd,0xbc,0x43,0xff,0x73,0x67,0x8e,
+  0x25,0xf8,0x67,0x3a,0x73,0x9a,0x52,0x02,0xcf,0x31,0x6c,0xeb,0x03,0x86,0xa1,0x69,
+  0x8a,0x22,0x69,0x1c,0x9a,0x50,0xdb,0x90,0x0a,0x9c,0x16,0x20,0x23,0x64,0x9e,0xa7,
+  0x99,0x31,0x21,0x62,0x7a,0xeb,0xd6,0x54,0xc7,0x0e,0xe0,0x9c,0x84,0x0e,0x2f,0x75,
+  0xe0,0x26,0x4a,0x96,0x8e,0x82,0xed,0x79,0x6e,0x31,0xa4,0x90,0x84,0xfb,0x5d,0x9e,
+  0x89,0xda,0x5e,0x22,0x6d,0x6f,0x09,0x27,0x15,0xda,0xf8,0x96,0x22,0x22,0xfd,0x63,
+  0xfb,0x5e,0x0c,0xcb,0x5e,0xd4,0xca,0x1b,0x85,0x4c,0xfa,0x87,0x46,0xe9,0xa2,0x70,
+  0x97,0xf2,0x4d,0xab,0x83,0x02,0xd0,0x2f,0x92,0x6f,0xff,0x7d,0x25,0x4b,0x8d,0x34,
+  0x43,0x44,0x28,0x7e,0x89,0xb4,0x87,0x66,0xa2,0x50,0xc2,0x9a,0x51,0x00,0x5d,0x2a,
+  0xc1,0x2f,0x0c,0x85,0xcc,0x9f,0x92,0x52,0x3b,0x06,0xda,0x8b,0x05,0xe0,0x24,0x12,
+  0xc3,0x09,0xa8,0x81,0x3c,0x3a,0x72,0xc2,0xb0,0xd8,0x06,0x59,0xfa,0x07,0x72,0xa4,
+  0x05,0xc6,0x92,0xf6,0xa2,0x68,0xd7,0xcf,0x49,0x08,0xc9,0xb3,0x94,0x57,0xa4,0x05,
+  0x8b,0x6e,0x6f,0x2f,0x2a,0x56,0x06,0xa5,0xd2,0x45,0x4b,0xda,0x3f,0xaf,0x29,0xf6,
+  0xeb,0xaf,0xcf,0x59,0xd1,0xff,0x97,0xfe,0x2f,0x44,0x94,0x6d,0x29,0xe1,0xf1,0x99,
+  0x3b,0x48,0xd0,0xaf,0xda,0x30,0x73,0x87,0x64,0x1d,0xd9,0x30,0xd3,0xfe,0xfc,0x40,
+  0xb1,0x60,0xc1,0x8c,0x69,0x78,0x6b,0xc0,0x16,0xea,0x7e,0x02,0xcd,0x06,0x7c,0x4f,
+  0x99,0x7a,0x9e,0xac,0xeb,0x97,0x87,0x0a,0x4b,0x94,0x5b,0x25,0x88,0xa0,0x21,0x2b,
+  0x41,0x43,0x56,0x88,0x42,0x61,0x49,0x57,0x73,0x69,0xa1,0x68,0x21,0xe1,0x56,0x14,
+  0xec,0xef,0xdb,0xd2,0x5e,0x78,0x87,0xf2,0xe7,0x68,0x4c,0x72,0xda,0x3f,0x47,0xc2,
+  0xcc,0x45,0xb7,0xb4,0xc3,0x1d,0xca,0xe7,0x60,0xa6,0x71,0x4b,0xbb,0x76,0x87,0x32,
+  0x53,0x9a,0x69,0xdf,0x0f,0xbc,0x94,0x71,0x23,0xac,0xe9,0x5d,0xbc,0xb4,0x89,0xb7,
+  0x87,0x53,0xfb,0xc1,0xab,0x85,0x8b,0xf5,0x1c,0x7e,0xf7,0xb2,0x92,0x76,0x14,0x3a,
+  0xec,0x8f,0x43,0xe1,0x69,0x88,0x69,0x68,0x1f,0x25,0x26,0x8c,0x6c,0x01,0x50,0xd8,
+  0x8e,0x82,0xfd,0x7a,0x67,0x6e,0x91,0xd4,0x65,0xce,0xf1,0x97,0x38,0xe5,0x22,0x38,
+  0x61,0xce,0xf4,0xe7,0x2f,0x91,0x3f,0x8f,0xc2,0x0d,0x28,0xe4,0x16,0xa5,0x04,0xfb,
+  0xf3,0xe4,0xe5,0xdc,0xbb,0xe8,0xae,0x28,0x1a,0xfd,0x84,0x74,0x8f,0x74,0x57,0x98,
+  0x04,0x84,0x01,0xa7,0x08,0x06,0x24,0x6e,0x21,0xe1,0x7f,0x78,0x66,0xda,0xd7,0xff,
+  0x9a,0xb6,0xa6,0x5f,0x45,0x9f,0xdd,0x59,0x99,0xa7,0x92,0xb0,0x77,0x67,0xe5,0x67,
+  0xd5,0x65,0x6d,0xc3,0x9b,0x9f,0x2d,0xff,0x49,0x9e,0xda,0xd4,0x76,0x82,0x84,0x79,
+  0xf6,0xe7,0xb9,0xe9,0xbb,0xb7,0x5f,0xfe,0xe5,0x4b,0xe7,0x3e,0x38,0x6f,0x09,0xfb,
+  0xce,0xfd,0xee,0xfc,0x4d,0x97,0x96,0xbe,0xf5,0xf0,0xe5,0x91,0x4f,0xce,0xdf,0xf4,
+  0x9d,0xa5,0x97,0x49,0xf8,0x04,0xfe,0x37,0xfe,0x82,0x8f,0xe6,0xcd,0x6d,0xfa,0x6c,
+  0x74,0xf3,0xf2,0xc6,0xf3,0xae,0x1f,0x37,0x5f,0x8e,0x5e,0xf8,0x87,0xe0,0xff,0xf9,
+  0xd9,0xef,0x1e,0xff,0x6c,0xf4,0x91,0x4f,0x1a,0x2f,0x7f,0xf6,0xfa,0xe3,0x9f,0x3d,
+  0xf7,0xc8,0x88,0xfd,0xfa,0xc6,0xef,0xdc,0xfe,0xd6,0xc3,0xfb,0x46,0x3e,0x38,0xdf,
+  0x38,0xf5,0x18,0x9f,0x34,0x5a,0x0f,0x36,0xf2,0x3b,0xbc,0xfe,0xf6,0xb7,0xac,0x27,
+  0xb4,0x5f,0x5f,0x36,0xbb,0xf5,0xad,0xcd,0x0b,0x47,0x36,0xdc,0x7d,0x13,0xfd,0xc3,
+  0xdd,0xf8,0x0f,0x51,0x78,0xb3,0x68,0x5f,0xd7,0x07,0xe7,0xcb,0x4a,0x2c,0x61,0xec,
+  0x5b,0x59,0x0f,0x14,0x5e,0x65,0x3c,0xae,0x5d,0x5f,0xb2,0xce,0x2c,0x43,0x01,0xae,
+  0x57,0xf2,0xfa,0xe1,0xeb,0x78,0xe4,0xbf,0xcd,0xca,0xfb,0x39,0x43,0xa1,0xfd,0x7a,
+  0x45,0xb2,0xaf,0xa7,0x32,0x85,0x0f,0x61,0x30,0x67,0x81,0x25,0xfc,0xf9,0x14,0x50,
+  0x44,0x7c,0x98,0x32,0x04,0x5a,0x8e,0xfd,0xfa,0x29,0xfd,0x5c,0x82,0xf8,0x30,0x34,
+  0xad,0xa8,0x4b,0xad,0x23,0xca,0x7a,0x3a,0x85,0xf8,0xb0,0x58,0x64,0x3d,0x50,0x0a,
+  0xa4,0x75,0x64,0xd0,0x9a,0x42,0xc2,0xad,0x20,0x6d,0x80,0xbb,0xad,0x23,0x59,0xfb,
+  0x39,0xaf,0xe5,0xde,0x3c,0x67,0xb8,0x59,0x16,0x91,0xe5,0x01,0x69,0x56,0xd7,0x9f,
+  0xe9,0x85,0x09,0xe5,0x5e,0x69,0x96,0x98,0xa1,0x17,0x9a,0x96,0x80,0x47,0xcc,0xec,
+  0xfb,0x6b,0xbc,0x98,0x49,0xd0,0x81,0xa8,0xab,0x44,0xfb,0x13,0x7c,0xa8,0x5b,0x42,
+  0xe6,0x8f,0x23,0x2c,0xc4,0xcf,0xca,0x40,0x7c,0x48,0x40,0x11,0xd1,0x60,0x54,0xb9,
+  0xbe,0x03,0xbf,0xd0,0x90,0xb6,0x55,0x99,0x2b,0xe5,0x89,0xa6,0xf6,0x2c,0x1f,0xed,
+  0x33,0x4a,0x5b,0xc7,0x55,0xf1,0x5b,0x84,0x56,0xa1,0xfc,0x65,0x87,0x3b,0xd6,0xd2,
+  0x53,0xe8,0x81,0x36,0x14,0x94,0xbe,0xc2,0xb9,0x0a,0x09,0x2d,0x11,0x9b,0xfe,0xe4,
+  0x66,0x1e,0x14,0x41,0xb1,0x99,0x43,0xb4,0x72,0x19,0x05,0x48,0x59,0x1b,0x3c,0x52,
+  0x27,0xdd,0x9e,0x12,0xfc,0x92,0x91,0xf9,0x07,0xe8,0xaa,0xfe,0x5f,0xed,0x9d,0x41,
+  0x6c,0xdb,0x54,0x18,0xc7,0xbf,0x97,0xbc,0x66,0x0e,0x4a,0x2b,0x7b,0xca,0x84,0x03,
+  0x55,0x95,0x8c,0x52,0x76,0x74,0x24,0x2a,0x15,0x71,0xd8,0x4b,0x53,0x27,0x61,0x52,
+  0xc1,0x50,0x40,0x13,0x27,0x17,0xf5,0x30,0x26,0x21,0xa5,0x08,0xa4,0x9d,0x90,0x53,
+  0x02,0x2a,0x1c,0x50,0x56,0x81,0x68,0x6f,0x39,0x4c,0x70,0xe2,0xc8,0x3d,0x2b,0x62,
+  0x62,0xb7,0x1d,0xa2,0x71,0xa4,0x93,0xb8,0x70,0x47,0x42,0x1c,0xc6,0xf8,0x3e,0x3f,
+  0xc7,0x7e,0xcd,0xa6,0x48,0xdb,0x01,0x24,0xf4,0xfd,0x4f,0x7f,0x3d,0xbf,0xba,0xcf,
+  0xf6,0xf3,0xdf,0xbf,0xcf,0x96,0x1d,0x9b,0x2a,0xe3,0x00,0xe8,0xa3,0xd0,0x54,0x89,
+  0x62,0xa4,0xf9,0xc4,0x87,0x81,0x28,0xc3,0x06,0x38,0x20,0xaf,0x89,0xf4,0xf6,0x39,
+  0xae,0x5f,0x57,0xca,0xd5,0xaa,0xae,0x54,0xed,0xb8,0xc0,0x94,0x16,0x21,0xc2,0xbe,
+  0x7d,0x5e,0x5a,0xbd,0xf8,0xe1,0xbe,0xd9,0x5f,0x86,0x3a,0x24,0xa3,0x38,0x2d,0xd7,
+  0x71,0x6f,0x17,0x74,0x8b,0x13,0x25,0x8b,0xea,0x51,0xda,0xdf,0x16,0x2a,0x1f,0xc2,
+  0x21,0xac,0x54,0x69,0x8f,0xe0,0x6e,0x5c,0x81,0xe2,0x3e,0xec,0x50,0x8b,0x2a,0xd2,
+  0x37,0x84,0x8e,0x70,0x11,0x5e,0x01,0x27,0x52,0xfe,0xba,0xec,0x12,0x14,0x5d,0xc1,
+  0xeb,0x1d,0x61,0xa1,0xe6,0xc3,0xcf,0xc9,0x0c,0x8e,0x97,0x35,0x1f,0x0e,0x46,0xe9,
+  0xf3,0x74,0xda,0xf2,0xea,0x34,0x1f,0xaa,0x87,0x4c,0x5a,0x91,0x2b,0xdc,0x4a,0x4f,
+  0x43,0xda,0xde,0xc4,0xfc,0x28,0x13,0x73,0xac,0x5b,0x4a,0xf6,0x28,0x7d,0x7e,0xa4,
+  0x7c,0xa5,0xf9,0x8d,0x1e,0x05,0xa0,0x81,0x96,0xe5,0x7c,0x42,0x9b,0x59,0xd5,0xdb,
+  0x4b,0x8b,0xa4,0x93,0xf1,0xa1,0x12,0x8f,0xe2,0x43,0x6f,0xaa,0x25,0x1b,0x4f,0x20,
+  0xd6,0xf5,0x4a,0x70,0x69,0x62,0x1c,0x02,0xe3,0xc4,0xe8,0x16,0x7b,0x94,0xce,0x08,
+  0x1a,0x0f,0x1d,0x48,0x1f,0x92,0x23,0xea,0x83,0x83,0x65,0x40,0x62,0x92,0x16,0x58,
+  0x4f,0xc7,0xd3,0xc1,0x69,0xd0,0x88,0xca,0xe1,0x9c,0x2b,0x0a,0xb0,0x1b,0xd9,0xa1,
+  0x24,0xd3,0x98,0x32,0x20,0xd2,0xf7,0x49,0xf1,0x7c,0x04,0xfd,0x82,0x01,0xdd,0xc8,
+  0x55,0x31,0x1f,0x6a,0x2c,0x24,0x50,0x4c,0x4c,0x36,0xdd,0x94,0xff,0x36,0xd2,0x60,
+  0x3f,0xac,0xe1,0x95,0x1a,0x41,0xf1,0xad,0x09,0x1f,0x8e,0x4f,0x19,0x95,0x5d,0xdf,
+  0x45,0x4b,0xee,0xf6,0x16,0xc3,0xb6,0xed,0xdc,0xd2,0xc6,0x75,0x6e,0x15,0x3e,0x12,
+  0x68,0x02,0x67,0x2c,0x77,0xc5,0xa2,0x6a,0x5f,0xae,0x8c,0xb2,0xf5,0x8b,0x16,0x10,
+  0x1f,0x9e,0x41,0x1a,0xcc,0x91,0x79,0xc1,0x2d,0x66,0x26,0xbf,0x1d,0x1b,0x23,0x4f,
+  0x02,0x5f,0xf3,0xe7,0xd3,0xae,0xc8,0xf8,0x13,0x56,0x63,0x62,0x3c,0x77,0x17,0xf9,
+  0x90,0x8c,0x73,0x9c,0x1d,0x2f,0xc4,0xe0,0x38,0x7f,0x3a,0xf2,0x00,0xcd,0x2b,0x3a,
+  0x7f,0x3e,0xcc,0x5a,0x62,0x63,0x8c,0x07,0x27,0xf0,0x76,0xe4,0x86,0x85,0x43,0xf8,
+  0x16,0xcd,0x33,0x61,0xc1,0x15,0x9f,0xc9,0xb8,0x05,0x8d,0x5e,0xe4,0x9a,0xf9,0xe3,
+  0x87,0x73,0x17,0x6a,0x0b,0x58,0xa1,0xc1,0xb0,0xbf,0x26,0x96,0xd0,0x38,0x27,0x78,
+  0x06,0x2e,0x41,0x1b,0x4d,0x3f,0x31,0x23,0x63,0xfe,0xbc,0x81,0x34,0x18,0xff,0xba,
+  0xd8,0x01,0x96,0x7a,0x15,0x2f,0x87,0x58,0x18,0xed,0x10,0x16,0x76,0xc4,0x81,0x06,
+  0xc5,0x8e,0x91,0x3f,0x38,0xdf,0x90,0x06,0x63,0x3e,0xfc,0xa2,0x8f,0x34,0x38,0x6c,
+  0x9d,0xe2,0xc3,0xc4,0x18,0xfd,0xf1,0xfc,0x52,0x8d,0xf2,0x59,0x1f,0x06,0x38,0x7f,
+  0x7a,0x76,0xd5,0xb7,0x1c,0x3c,0xd5,0xe3,0xdf,0xd1,0xc1,0x68,0xd0,0x46,0x80,0xb1,
+  0x7f,0xb0,0xa4,0x1c,0x95,0xbd,0x39,0x0b,0x2e,0xd1,0xaf,0x97,0x0f,0x45,0x49,0x34,
+  0x21,0xa0,0x16,0xc3,0xa8,0x6c,0x7e,0x62,0x1e,0x7a,0xc8,0x87,0x1b,0x34,0x55,0xf0,
+  0x4f,0x41,0xd0,0xb7,0xe0,0x34,0x16,0x36,0x26,0xc6,0xc8,0x37,0x1c,0x4f,0xf5,0x2c,
+  0xf2,0x61,0x88,0xf1,0x70,0x1e,0x69,0x10,0x4b,0x6c,0xc2,0xc2,0x7d,0xc2,0xc2,0xfd,
+  0xdc,0x10,0x5b,0x96,0xd1,0x18,0xe3,0x11,0x49,0xfe,0xe4,0xb1,0x2a,0xc1,0xfc,0xb1,
+  0xf4,0x69,0x58,0xa7,0xd8,0xb9,0x1e,0x7d,0x15,0x56,0xc8,0x54,0xcc,0xfd,0xa3,0x30,
+  0x6d,0x2a,0xb0,0xd2,0xec,0x0d,0xf6,0x42,0x71,0x64,0x61,0xfe,0x0c,0x44,0x77,0x0d,
+  0xf3,0x27,0x57,0xc4,0x16,0x1b,0x0d,0x18,0xd7,0x2f,0xe5,0x87,0xd1,0x1a,0xd0,0xf1,
+  0x1a,0xd1,0xf1,0xfa,0x52,0x62,0x69,0x7d,0x22,0x2f,0x58,0xd8,0xb2,0x37,0x38,0xd9,
+  0x59,0x2b,0x2e,0xe4,0x9a,0x3d,0xe3,0x7c,0x0f,0x40,0xc8,0x97,0xc2,0x85,0xcb,0xf9,
+  0xaf,0xe1,0x3b,0xfa,0x16,0x98,0x9d,0x97,0xf0,0xd3,0x43,0xc6,0x18,0x0f,0xf2,0xe4,
+  0xaa,0x9a,0xef,0xe6,0x83,0xc1,0x18,0xea,0x6a,0x5e,0xe5,0xcb,0xf0,0x8b,0xac,0x77,
+  0x4a,0x01,0x19,0x6c,0x21,0x63,0x1f,0x1b,0xe3,0x69,0xca,0xed,0x9b,0x6e,0x17,0xf3,
+  0x01,0x63,0x67,0xe4,0x7a,0xad,0x92,0xf3,0x8d,0x0c,0x6f,0x9e,0x36,0x66,0xfe,0x28,
+  0xcd,0x87,0x65,0xe4,0xd5,0x19,0xf7,0x11,0xb3,0xfd,0xd3,0xd9,0x48,0xf8,0x30,0xda,
+  0x79,0xd7,0x46,0x53,0x73,0x0e,0x65,0x82,0x85,0xa9,0x89,0xcc,0xfc,0xf1,0xe5,0xeb,
+  0xe7,0xa4,0x8f,0xb8,0xbc,0x11,0xd8,0x65,0xe9,0x0b,0x47,0x29,0x8c,0x1d,0xa9,0xf3,
+  0xc7,0x21,0x23,0x94,0x31,0x7f,0x68,0x02,0xa6,0xc9,0x67,0x63,0xc9,0x45,0x53,0x12,
+  0xec,0x3d,0xa3,0x70,0xe8,0x65,0xf9,0x03,0x44,0x83,0x3d,0xba,0x0d,0x6c,0x3f,0xe5,
+  0x10,0x16,0xc2,0xa3,0x40,0xd1,0x9c,0x3f,0x9b,0x62,0xab,0xd1,0xbf,0x53,0x7b,0xd1,
+  0xdd,0xcc,0x6d,0xa9,0x31,0x9a,0xf9,0xcd,0xfc,0x96,0x7a,0xf3,0xce,0xaa,0x36,0x63,
+  0x32,0xc6,0x78,0x84,0xb5,0xfc,0x41,0x63,0x71,0xd0,0xae,0x39,0xb7,0x3f,0xed,0xea,
+  0xab,0xff,0xcf,0x85,0x18,0x03,0x20,0x01,0x83,0x76,0xd5,0xc8,0x1f,0xbc,0x5e,0x5f,
+  0x6d,0xdd,0xbd,0xfe,0xc3,0x8d,0xf7,0x8f,0x9e,0xbd,0x7a,0x89,0xf8,0xf0,0xfb,0xf7,
+  0x34,0x1f,0xde,0xc8,0xf8,0xb0,0x68,0x74,0x87,0x8b,0x19,0x1f,0xbe,0x46,0x7c,0xf8,
+  0xe0,0xbe,0xe6,0xc3,0x3f,0x32,0x3e,0x3c,0xc5,0x63,0x8f,0xab,0xe7,0x09,0x0b,0x7f,
+  0x1f,0x3c,0xb8,0x7f,0xf1,0xaf,0x04,0x14,0x91,0x18,0x67,0xf0,0x61,0xfc,0xdf,0xff,
+  0xfc,0x0d,0xfb,0xff,0x3d,0x01,0xc5,0x8f,0x67,0xf1,0xe1,0xcb,0x13,0x3e,0x7c,0x6e,
+  0xe9,0xd5,0x5f,0x0f,0xea,0xd4,0xff,0xda,0x54,0xff,0x7b,0x4f,0x3e,0x7a,0x0f,0xa1,
+  0x81,0xbe,0xd8,0xe8,0x41,0xb3,0xf4,0xe4,0x6b,0x61,0xb1,0x58,0x2c,0x16,0x8b,0xc5,
+  0x62,0xb1,0x58,0xff,0x77,0xc5,0xb5,0x83,0xe4,0xda,0x81,0xc5,0x62,0xb1,0x58,0x2c,
+  0x16,0x8b,0xc5,0x62,0xcd,0x56,0x5c,0x3b,0x14,0xb8,0x76,0x60,0xb1,0x58,0x2c,0x16,
+  0x8b,0xc5,0x62,0xb1,0x58,0xb3,0x15,0xd7,0x0e,0x56,0x5c,0x3b,0xfc,0xd7,0x43,0x61,
+  0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62,0xb1,0x58,0xff,0xa2,0x3c,0x7a,0x81,0x1c,0x0a,
+  0xb7,0x3d,0x88,0xdf,0x89,0xc9,0x7b,0xa0,0x1e,0xfb,0x79,0x42,0xf2,0xb7,0x73,0x1e,
+  0x0c,0x45,0xb6,0xce,0x7b,0xef,0x4c,0xf7,0xfb,0x07,0x18,0x78,0xae,0x50,0xf1,0x33,
+  0x01,0x00,
diff --git a/u-boot/board/esd/canbt/Makefile b/u-boot/board/esd/canbt/Makefile
new file mode 100644
index 0000000..bd08253
--- /dev/null
+++ b/u-boot/board/esd/canbt/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/canbt/canbt.c b/u-boot/board/esd/canbt/canbt.c
new file mode 100644
index 0000000..cc537f2
--- /dev/null
+++ b/u-boot/board/esd/canbt/canbt.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2001
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "canbt.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	unsigned long CPC0_CR0Reg;
+	int index, len, i;
+	int status;
+
+	/*
+	 * Setup GPIO pins
+	 */
+	CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
+	CPC0_CR0Reg |= 0x0070f000;
+	mtdcr (CPC0_CR0, CPC0_CR0Reg);
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * Setup port pins for normal operation
+	 */
+	out_be32 ((void *)GPIO0_ODR, 0x00000000);	/* no open drain pins */
+	out_be32 ((void *)GPIO0_TCR, 0x07038100);	/* setup for output */
+	out_be32 ((void *)GPIO0_OR, 0x07030100);	/* set output pins to high (default) */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "CANBT", 5)) {
+		puts ("### No HW ID - assuming CANBT\n");
+		return (0);
+	}
+
+	puts (str);
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	return 0;
+}
diff --git a/u-boot/board/esd/canbt/canbt.h b/u-boot/board/esd/canbt/canbt.h
new file mode 100644
index 0000000..5fc313a
--- /dev/null
+++ b/u-boot/board/esd/canbt/canbt.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/canbt/flash.c b/u-boot/board/esd/canbt/flash.c
new file mode 100644
index 0000000..b210281
--- /dev/null
+++ b/u-boot/board/esd/canbt/flash.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+	/*          printf("PB1CR = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/canbt/fpgadata.c b/u-boot/board/esd/canbt/fpgadata.c
new file mode 100644
index 0000000..0de7d92
--- /dev/null
+++ b/u-boot/board/esd/canbt/fpgadata.c
@@ -0,0 +1,404 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0c,
+ 0x69,0x6f,0x5f,0x63,0x68,0x69,0x70,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,0x73,
+ 0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,0x30,
+ 0x31,0x2f,0x31,0x31,0x2f,0x32,0x33,0x00,0x64,0x00,0x09,0x31,0x33,0x3a,0x33,0x34,
+ 0x3a,0x34,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x18,0xe6,0xff,0x30,0xe8,0x01,0x01,
+ 0x01,0x01,0xe7,0xe6,0x04,0x01,0x0d,0x04,0x07,0x03,0x05,0x03,0x05,0x03,0xe5,0xe5,
+ 0x05,0x09,0x04,0x06,0x01,0x07,0x09,0x01,0x07,0x0b,0x0f,0x07,0x03,0x05,0x03,0x05,
+ 0x03,0x11,0x03,0x0f,0x09,0x03,0x05,0x10,0xe5,0xe6,0x1a,0x0a,0x13,0x29,0x19,0x05,
+ 0x09,0x04,0x04,0x09,0x09,0x09,0x0b,0x04,0x04,0x09,0x09,0x09,0x0e,0xe5,0x01,0x14,
+ 0x09,0x09,0x09,0x03,0x05,0x0b,0x03,0x05,0x09,0x09,0x09,0x09,0x01,0xe6,0x7b,0x01,
+ 0x01,0x02,0x75,0xe8,0x3e,0x3b,0x02,0x34,0x0a,0x09,0x07,0x09,0x01,0x11,0x0a,0xe5,
+ 0xe6,0x5c,0x1e,0xe6,0xe5,0x0a,0xe5,0x50,0x1d,0x0d,0x31,0x09,0x14,0x13,0x07,0x01,
+ 0x01,0x2a,0x08,0x0b,0x1e,0x1c,0x01,0xe5,0x0f,0x09,0x09,0xe5,0x07,0x09,0xe6,0x08,
+ 0x05,0x03,0x01,0x07,0x09,0x09,0x0d,0xe8,0x0f,0x09,0xe5,0x07,0x09,0x04,0x05,0x0a,
+ 0x01,0x07,0x01,0x07,0x09,0x09,0x0d,0xe5,0xe6,0x0c,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x03,0x03,0xe5,0x06,0xe5,0xe6,0x03,0x03,0xe5,0x04,0x02,0xe5,0x01,0x05,0xe5,
+ 0x07,0xe5,0x01,0x07,0x05,0xe7,0x0f,0x09,0x09,0x09,0x10,0x04,0x05,0x03,0x03,0x05,
+ 0x09,0x09,0x08,0x08,0x04,0x01,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x02,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0x02,0x03,
+ 0x02,0xe5,0x0e,0x09,0x09,0x09,0x15,0x09,0x09,0x09,0x09,0x0e,0xe6,0xe5,0x0c,0x09,
+ 0x09,0x09,0x09,0x04,0x04,0x01,0x09,0x06,0x02,0x09,0x09,0x11,0xe7,0x0c,0x02,0x06,
+ 0x02,0x04,0x01,0x02,0x01,0x01,0x02,0x02,0x06,0x02,0x03,0x02,0x01,0x02,0x06,0x02,
+ 0x01,0x04,0x02,0x06,0x02,0x03,0x02,0x02,0x11,0x03,0x17,0x03,0x05,0x12,0x15,0x02,
+ 0x23,0x08,0x16,0x06,0x0c,0x05,0x15,0x07,0x01,0x0a,0x02,0x0f,0x01,0x07,0x02,0xe5,
+ 0xe5,0x08,0x07,0x02,0x07,0x02,0x10,0x03,0x11,0x03,0x2b,0x05,0xe6,0x2b,0x0a,0x06,
+ 0x01,0x01,0x11,0x0b,0x0e,0xe5,0x08,0xe6,0xe5,0x0f,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x01,0x07,0x09,0x0e,0x01,0xe5,0x0f,0x0d,0x22,0xe5,0xe5,0x27,0x0e,0xe6,0x47,
+ 0x11,0x17,0x02,0x04,0x01,0x01,0x0d,0x0d,0x1f,0x04,0x01,0x24,0x10,0x03,0x01,0x2a,
+ 0x12,0x0c,0x06,0xe5,0x0a,0x09,0x11,0xe5,0x01,0x1c,0x09,0x17,0x0b,0x09,0x09,0x04,
+ 0x19,0xe5,0x0c,0x01,0x0d,0x22,0x0a,0x01,0x0d,0xe5,0x04,0x18,0x01,0xe5,0x01,0x05,
+ 0x04,0x01,0x02,0xe5,0x14,0x10,0x0b,0x02,0x01,0x02,0x02,0xe5,0x19,0x0d,0xe5,0xe5,
+ 0x0e,0x09,0x09,0x02,0x06,0x09,0x02,0x03,0x04,0x03,0x05,0x09,0x15,0x0c,0x02,0xe5,
+ 0x01,0x0b,0x04,0x04,0x09,0x09,0x02,0x06,0x09,0xe5,0x01,0x06,0x05,0x03,0x06,0x1e,
+ 0x02,0x1c,0x1d,0x08,0xe5,0x05,0x02,0x06,0x02,0x03,0xe5,0x1b,0x03,0x17,0xe5,0x08,
+ 0x02,0x09,0xe5,0x09,0x0f,0xe5,0x08,0x07,0x09,0x06,0x0b,0x02,0x17,0xe5,0x09,0x01,
+ 0x1f,0x05,0xe5,0x02,0x05,0x03,0x1f,0xe5,0xe6,0x0e,0x09,0x03,0x05,0x03,0x05,0x09,
+ 0x11,0x01,0x01,0x04,0x0c,0x01,0x0a,0x0e,0x01,0xe5,0x0c,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x06,0xe6,0x02,0x03,0xe6,0x03,0x03,0x02,0x09,0x06,0xe5,0xe5,0x25,0x14,0x1a,0x12,
+ 0x05,0x04,0x02,0x13,0x16,0xe7,0xe5,0x11,0xe5,0x11,0xe5,0x06,0xe5,0x14,0xe5,0x11,
+ 0xe5,0x03,0xe5,0x08,0xe5,0x06,0x01,0x02,0x02,0x02,0x01,0x2c,0xe5,0x08,0x01,0x1d,
+ 0xe5,0xe6,0x01,0x02,0x01,0x04,0x09,0x01,0x02,0xe6,0x03,0x04,0xe5,0x02,0x01,0x02,
+ 0xe5,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0xe5,0x04,0x01,0x07,0x05,0xe5,
+ 0x01,0x01,0x02,0xe5,0x07,0xe5,0x01,0x01,0xe5,0x09,0xe5,0xe5,0xe7,0x01,0x0e,0x08,
+ 0x03,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x0d,0xe5,0x07,0xe5,0x08,0xe5,0x07,0x05,
+ 0x07,0x02,0x01,0x01,0xe8,0xe5,0x10,0x01,0x05,0x0c,0x10,0xe5,0x01,0x06,0xe5,0x08,
+ 0x08,0xe6,0x01,0x02,0x05,0xe5,0x04,0xe5,0x01,0x06,0xe5,0x01,0xe5,0x01,0x10,0x02,
+ 0x05,0xe5,0x01,0x06,0x02,0x06,0x02,0x05,0x03,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0x04,0x03,0x03,0xe5,0x04,0x08,0xe6,0xe5,0xe6,0x01,0x0b,0x05,0x03,0x09,0x09,0x09,
+ 0x06,0x04,0x05,0x01,0x01,0x09,0x05,0x0a,0x01,0x01,0x02,0x08,0x02,0xe5,0xe6,0x01,
+ 0x11,0xe5,0x31,0x14,0x10,0x0a,0x02,0xe8,0x0c,0x03,0xe6,0x02,0x03,0x05,0x03,0x05,
+ 0x03,0x02,0x02,0x03,0x02,0x04,0x03,0x01,0x03,0x03,0x05,0x0d,0xe5,0x06,0x0b,0x01,
+ 0x01,0x11,0x0c,0x01,0x04,0x02,0x01,0x04,0x02,0x09,0x0b,0x01,0x07,0x01,0x07,0x09,
+ 0x13,0xe6,0xe6,0x0a,0x02,0x06,0x02,0x03,0x02,0x02,0x04,0xe6,0x01,0x05,0xe5,0x01,
+ 0x03,0x07,0x03,0x02,0x02,0x05,0xe5,0x01,0x03,0x02,0x02,0x03,0xe5,0xe5,0x01,0x06,
+ 0x04,0x01,0x01,0xe5,0xe5,0x01,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x08,
+ 0x0a,0xe5,0x05,0x09,0x02,0x09,0x05,0xe5,0x01,0x07,0xe5,0xe6,0x08,0x05,0x03,0x05,
+ 0x03,0x05,0x05,0x03,0x03,0x05,0x03,0x07,0x03,0x05,0x09,0x03,0x0a,0x08,0x0d,0xe5,
+ 0x5e,0x06,0x07,0x0b,0xe8,0x10,0x01,0x07,0x09,0x01,0x07,0x01,0x07,0x0b,0x09,0x09,
+ 0x08,0x03,0x06,0x0c,0xe8,0x09,0x54,0x01,0x0d,0x02,0x07,0x01,0x01,0x15,0xe5,0x05,
+ 0xe7,0x05,0xe7,0x07,0xe5,0x06,0xe6,0x08,0xe6,0x05,0xe7,0x06,0xe7,0xe5,0x02,0xe7,
+ 0x05,0xe7,0x0a,0x10,0xe5,0x07,0x09,0x33,0x06,0x0b,0x0f,0xe7,0x19,0x05,0x03,0x02,
+ 0x02,0x13,0x0b,0x09,0x03,0x05,0x06,0x02,0xe5,0x07,0x08,0x02,0xe5,0x1b,0xe6,0x07,
+ 0xe5,0x11,0xe5,0x01,0x07,0xe5,0x06,0xe6,0x07,0xe5,0xe5,0xe5,0x03,0xe5,0x02,0x03,
+ 0xe6,0x0a,0xe5,0x02,0x0e,0x09,0xe5,0xe6,0x04,0xe8,0x04,0x09,0xe5,0xe6,0x06,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe7,0xe6,0x01,0x01,0xe6,0x03,0xe8,0x06,0x01,0x01,
+ 0x0e,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x09,0x01,0x07,0x01,
+ 0x07,0x01,0x01,0x08,0x08,0x01,0x0a,0xe9,0x10,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0x01,0x02,0x03,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0x06,
+ 0x01,0x02,0x04,0x01,0x07,0x01,0xe5,0x08,0x01,0xe6,0x0e,0xe5,0x02,0x0e,0xe5,0x07,
+ 0xe5,0x07,0xe5,0xe5,0x0d,0x09,0xe5,0x06,0x04,0xe5,0x05,0x01,0xe5,0x0c,0xe6,0xe6,
+ 0x1e,0x07,0x15,0x07,0x09,0xe5,0x0d,0xe5,0xe5,0xe5,0x01,0x01,0x09,0x04,0xe6,0xe6,
+ 0x04,0x02,0x04,0x01,0x02,0x09,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02,0x08,
+ 0x0b,0x06,0x0e,0x10,0xe5,0xe6,0x0b,0x01,0x07,0x01,0x03,0xe5,0x01,0x01,0x07,0x01,
+ 0x07,0x01,0x02,0x05,0x09,0x17,0x04,0x03,0x03,0x09,0xe7,0xe5,0x0d,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x04,0x01,0x0a,0x07,0x06,0x01,0x02,0x0a,0x13,
+ 0xe6,0x0d,0x03,0x05,0x09,0x03,0x05,0x09,0x03,0x03,0x03,0x02,0x05,0xe5,0x02,0x04,
+ 0xe5,0x07,0xe5,0x01,0x03,0x02,0x0d,0x01,0x02,0x0d,0x02,0x02,0x03,0x09,0x02,0x06,
+ 0x04,0x04,0x02,0xe5,0x04,0x01,0x05,0x03,0x01,0xe5,0x05,0x01,0x07,0x01,0x08,0x0c,
+ 0x06,0x06,0x02,0x05,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x03,0xe5,
+ 0x01,0xe5,0xe5,0xe5,0x06,0x09,0x01,0xe5,0x17,0x03,0x01,0xe6,0x09,0x02,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe6,0x07,0x11,0xe5,0xe5,0x09,0x02,
+ 0x0e,0x0b,0x04,0x01,0x03,0x03,0x09,0x01,0x07,0x04,0x04,0x02,0xe5,0xe6,0x03,0x07,
+ 0x18,0xe5,0x13,0xe5,0xe6,0x0c,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,
+ 0xe5,0x0a,0x03,0xe5,0x01,0x01,0x07,0x01,0xe5,0x03,0xe5,0x09,0x01,0x0a,0x02,0x03,
+ 0xe5,0x0c,0xe6,0x06,0xe6,0x01,0x04,0xe6,0x06,0xe7,0xe5,0x03,0xe6,0x01,0x05,0x02,
+ 0x09,0x05,0x03,0x07,0x01,0x02,0x06,0x0a,0x03,0xe5,0xe6,0xe5,0x06,0x1c,0x1a,0xe5,
+ 0x02,0x05,0x0a,0x12,0x02,0x0c,0xe5,0x01,0x01,0x1b,0xe5,0x04,0x03,0x01,0x06,0xe5,
+ 0x10,0xe5,0x01,0xe5,0x03,0xe5,0x12,0xe5,0x06,0xe5,0x07,0x01,0x03,0xe9,0xe5,0x17,
+ 0xe5,0x08,0xe5,0x06,0xe5,0x08,0xe5,0x09,0xe5,0x17,0x03,0x01,0x0e,0x01,0x01,0x02,
+ 0x02,0x01,0x04,0xe5,0x02,0x04,0xe5,0x02,0x09,0x09,0x09,0x04,0xe5,0x04,0x01,0xe5,
+ 0x05,0x01,0xe5,0x05,0x01,0x08,0xe5,0x01,0xe5,0x05,0xe5,0x07,0xe5,0x01,0x01,0xe5,
+ 0x01,0x1b,0x09,0xe5,0x07,0x14,0xe5,0x05,0x01,0xe5,0x04,0x02,0xe5,0x01,0x06,0x0d,
+ 0x02,0x01,0xe5,0x02,0xe5,0xe5,0x06,0x01,0x05,0xe5,0x01,0x05,0x02,0x10,0xe5,0xe6,
+ 0x04,0x01,0x01,0x06,0x01,0x02,0x0f,0xe5,0x01,0xe5,0x02,0xe5,0x01,0x08,0x01,0x06,
+ 0xe5,0xe7,0x01,0x06,0x02,0x05,0x01,0x01,0x05,0x03,0x07,0x01,0x05,0x01,0x01,0x05,
+ 0x0d,0x01,0x0f,0x04,0x04,0x08,0x01,0x02,0x04,0xe6,0x01,0xe6,0x01,0x0b,0x09,0x06,
+ 0x02,0x09,0x09,0x0b,0x05,0x03,0x09,0x0a,0x02,0x06,0x08,0x02,0x02,0xe6,0xe5,0x12,
+ 0xe5,0x11,0xe5,0x1d,0xe6,0x14,0x04,0xe6,0x01,0x0f,0x03,0xe6,0x07,0x05,0x03,0x02,
+ 0x02,0x03,0x05,0x03,0xe5,0x03,0x03,0x02,0x02,0x03,0x02,0x04,0x03,0xe5,0x03,0x03,
+ 0x05,0x03,0x08,0xe5,0x01,0x12,0xe5,0xe5,0xe5,0x07,0x01,0x07,0xe5,0x07,0x01,0x04,
+ 0x16,0x08,0x02,0xe5,0x04,0x02,0x01,0x07,0x01,0x07,0xe5,0x07,0x09,0xe5,0x01,0xe5,
+ 0x09,0xe5,0x01,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x02,0x03,0x07,0x06,0x02,
+ 0x03,0x05,0x03,0xe5,0xe5,0x01,0x04,0x01,0x02,0x05,0xe5,0x05,0x01,0xe5,0xe5,0x0a,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0x09,0xe5,0x08,0x0a,0xe5,0x08,0x09,0x05,0x03,0x06,
+ 0x02,0x07,0xe8,0x08,0x05,0x03,0x05,0x03,0x05,0x09,0x03,0x05,0x05,0x05,0x03,0x05,
+ 0x03,0x05,0x04,0x09,0x0a,0x08,0xe5,0xe6,0x5b,0x07,0x17,0xe6,0x01,0x0e,0x09,0x09,
+ 0x01,0x07,0x09,0x0b,0x01,0x07,0x01,0x07,0x05,0x03,0x04,0xe5,0x01,0x0e,0xe5,0xe6,
+ 0x1c,0x1c,0xe5,0x1e,0x04,0x09,0x0e,0x01,0xe6,0x08,0x0b,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe7,0x05,0xe7,0x05,0x01,0xe6,0x04,0x01,
+ 0xe6,0x04,0xe7,0x06,0x02,0xe5,0xe5,0x0d,0xe5,0x07,0x29,0x09,0x09,0x08,0x09,0x0e,
+ 0x03,0x20,0x09,0x13,0x05,0x05,0x03,0x05,0x09,0x09,0xe5,0x07,0x09,0xe6,0x19,0x02,
+ 0x01,0x07,0x01,0x11,0x01,0x02,0x06,0xe6,0x06,0xe6,0x03,0x02,0x01,0x07,0x01,0x03,
+ 0x03,0xe6,0x07,0xe5,0xe6,0x11,0x09,0xe8,0x04,0x01,0xe6,0x04,0x09,0xe8,0x06,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe8,0x04,0xe9,0x04,0x01,0xe5,0x06,0x03,0xe5,0x0b,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe5,0xe5,
+ 0x05,0xe5,0xe6,0x04,0x02,0x06,0x02,0x01,0x14,0xe9,0x05,0x0a,0x01,0xe5,0x05,0x01,
+ 0xe5,0x05,0x01,0xe6,0x04,0x01,0x01,0x05,0x01,0xe6,0x01,0x04,0x01,0x01,0x05,0x01,
+ 0xe6,0x01,0x02,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x02,0x07,0xe8,0x02,0x05,0x04,
+ 0x07,0x01,0xe5,0x07,0x03,0x02,0x02,0x09,0x04,0x01,0x04,0x04,0xe5,0x02,0xe6,0x02,
+ 0x02,0x02,0x03,0x02,0xe5,0x01,0x1a,0xe5,0x1a,0x02,0x06,0x0a,0x02,0x16,0x08,0xe5,
+ 0x06,0x04,0x02,0x02,0x0d,0xe5,0xe5,0x01,0xe6,0x12,0x04,0x1b,0x04,0x05,0x0a,0x02,
+ 0x02,0x07,0x0b,0x15,0xe5,0x01,0xe5,0x0b,0xe6,0x03,0x02,0xe6,0x03,0x02,0xe6,0x03,
+ 0x02,0xe7,0x05,0xe6,0x02,0x08,0x09,0x06,0xe6,0x01,0x02,0x03,0x09,0xe5,0x01,0x09,
+ 0x04,0x09,0x03,0x09,0x09,0x09,0x09,0x03,0x03,0x01,0xe5,0x07,0x0b,0x19,0x0c,0xe7,
+ 0x08,0x08,0x06,0xe6,0x0c,0x01,0xe6,0x04,0x0a,0xe5,0x05,0xe5,0x03,0x02,0x0a,0x03,
+ 0x05,0x03,0x05,0x09,0x04,0x10,0x13,0x06,0x02,0x09,0x02,0x03,0x04,0x04,0x04,0x09,
+ 0x0f,0x12,0x02,0x01,0x04,0x15,0x02,0x08,0x02,0x04,0x0e,0x08,0x05,0x28,0x04,0x01,
+ 0x03,0x19,0x20,0xe6,0x08,0x06,0x10,0x19,0x01,0x06,0x01,0x1d,0x15,0x02,0x0a,0x08,
+ 0x06,0x01,0xe6,0x06,0x07,0x0b,0x02,0xe7,0xe5,0x05,0x09,0x01,0x11,0x04,0xe5,0x02,
+ 0x04,0xe5,0x04,0x01,0x08,0x07,0x08,0xe5,0x05,0x16,0x01,0x02,0x19,0x10,0x01,0x0a,
+ 0x08,0x0d,0x0a,0x0b,0x0a,0x09,0x01,0x01,0x19,0x0e,0x07,0x04,0xe5,0x1a,0x28,0x02,
+ 0x01,0x26,0xe5,0x04,0x11,0x02,0xe5,0x01,0xe5,0xe5,0x08,0x02,0xe5,0x07,0xe5,0x13,
+ 0x01,0xe5,0xe9,0xe5,0x1b,0xe5,0x12,0xe5,0x03,0x01,0x02,0x03,0x01,0xe5,0x01,0xe6,
+ 0x03,0x01,0xe5,0x0c,0x11,0x01,0x01,0xe5,0xe5,0xe5,0x01,0x01,0x12,0x01,0x09,0x02,
+ 0x01,0xe5,0xe5,0xe7,0x01,0xe5,0x03,0x08,0x06,0x01,0xe5,0x01,0x01,0x04,0x03,0x16,
+ 0x01,0x02,0x01,0xe5,0xe6,0x01,0x02,0x11,0xe5,0xe5,0xe5,0x06,0x06,0xe5,0xe5,0xe5,
+ 0x02,0xe5,0x05,0x07,0x0b,0x07,0x19,0xe5,0x05,0x02,0xe6,0xe6,0xe5,0x01,0x03,0x02,
+ 0x16,0x09,0x01,0x01,0x02,0x02,0x09,0x09,0x01,0x01,0xe5,0x03,0x23,0xe5,0x01,0xe5,
+ 0x01,0x06,0x02,0x0e,0x05,0x03,0x0c,0x01,0x02,0x01,0x07,0x03,0x05,0x01,0x01,0x05,
+ 0x03,0x1d,0xe5,0x02,0x01,0x02,0x14,0x01,0x09,0x07,0x04,0x01,0x0e,0x04,0x04,0x03,
+ 0xe5,0xe5,0xe6,0x03,0x19,0x02,0x02,0x03,0x17,0x01,0x07,0x09,0x04,0x01,0xe5,0x0c,
+ 0x09,0x01,0x04,0x01,0xe5,0x25,0x01,0xe5,0x03,0x03,0x26,0xe5,0xe5,0x05,0x0c,0x08,
+ 0x0a,0xe5,0x1b,0x02,0xe6,0x09,0x01,0x22,0x02,0x01,0x13,0x01,0x04,0x02,0xe5,0x11,
+ 0xe5,0x12,0xe5,0xe6,0x07,0x05,0x09,0x09,0x09,0x03,0x05,0x0b,0x03,0x05,0x09,0x09,
+ 0x09,0x06,0x06,0x03,0xe5,0x29,0x05,0x03,0x05,0x0f,0x05,0x20,0x0b,0xe5,0x27,0x09,
+ 0x14,0x07,0x2b,0xe7,0x15,0x02,0x16,0x10,0x01,0x04,0x02,0x09,0x01,0x07,0x01,0x18,
+ 0x03,0x19,0xe5,0x0c,0x02,0x01,0x01,0x01,0x06,0xe5,0x03,0x02,0x01,0xe5,0x07,0xe6,
+ 0x04,0x01,0xe5,0x04,0xe5,0xe6,0x16,0x03,0xe5,0x17,0x22,0x0b,0x02,0x2e,0xe5,0x01,
+ 0x15,0xe5,0x01,0x03,0xe5,0xe5,0x05,0x02,0xe5,0xe5,0x04,0xe5,0x07,0x0a,0xe7,0xe5,
+ 0x04,0xe5,0x06,0xe6,0x07,0xe5,0x07,0xe5,0x06,0x03,0x04,0x14,0x03,0x23,0x01,0x04,
+ 0x0c,0x01,0xe6,0x04,0x01,0x1b,0xe5,0x18,0x06,0x09,0xe5,0xe5,0x0f,0x02,0x01,0x06,
+ 0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x18,0x02,0x19,0x04,0xe6,0x05,0x01,0xe5,0x09,0x0a,
+ 0x09,0x09,0x07,0x01,0x1b,0x01,0x01,0x19,0x04,0x08,0xe5,0x01,0x04,0x09,0x01,0x07,
+ 0x0b,0x01,0x05,0x21,0x01,0x01,0xe5,0x0f,0x19,0xe5,0xe5,0x11,0x01,0xe6,0x04,0x01,
+ 0xe5,0xe5,0x03,0xe5,0xe5,0xe5,0x1d,0x01,0xe7,0x05,0x0a,0x01,0x02,0x04,0x01,0x07,
+ 0x01,0xe5,0x02,0x01,0xe5,0xe6,0xe5,0x03,0x01,0x01,0x02,0x01,0x02,0x01,0xe5,0x01,
+ 0x03,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x0b,0x01,0xe5,0x08,0x20,0x09,0x02,
+ 0xe6,0xe6,0x05,0x03,0x0e,0x0a,0xe5,0x01,0x16,0xe7,0x1d,0x08,0x07,0x04,0x01,0x03,
+ 0x02,0x05,0x02,0x06,0x05,0x0b,0x07,0x07,0x08,0xe5,0x01,0xe5,0x11,0x16,0x0f,0xe5,
+ 0x03,0xe5,0xe5,0x01,0x04,0x03,0x04,0x05,0x06,0x19,0xe6,0xe7,0x05,0xe5,0x05,0x09,
+ 0x03,0x09,0x04,0x02,0x01,0x02,0x01,0x10,0x02,0x01,0x04,0x01,0x03,0x20,0x02,0xe6,
+ 0x10,0x18,0xe5,0x03,0x04,0x01,0x05,0x01,0x09,0x04,0x14,0x16,0xe5,0x01,0xe5,0x12,
+ 0x0b,0x04,0x07,0x0e,0x02,0xe5,0x02,0x06,0x05,0x26,0xe6,0xe7,0x12,0xe5,0x04,0x0f,
+ 0x03,0x0b,0x04,0x0e,0x0f,0x03,0x18,0x01,0xe5,0x1a,0xe5,0x10,0x05,0x0a,0x11,0x14,
+ 0x14,0xe5,0xe5,0x16,0xe6,0x02,0x02,0xe7,0x02,0x03,0xe6,0x06,0xe6,0xe6,0x03,0xe5,
+ 0x08,0xe7,0xe5,0x29,0x03,0x02,0x10,0x06,0x03,0x05,0x03,0x01,0x02,0x0a,0x03,0x02,
+ 0x07,0xe5,0x04,0x0a,0x20,0x01,0x01,0xe5,0x14,0x17,0x02,0xe5,0x19,0x01,0xe5,0xe5,
+ 0xe5,0x02,0x03,0x06,0x0d,0x07,0xe6,0x01,0x2e,0x03,0x02,0x01,0x03,0x02,0x01,0x0b,
+ 0xe5,0x09,0x01,0x1f,0x01,0xe6,0x12,0x0c,0x0e,0x17,0x05,0x0d,0x09,0x14,0x02,0xe5,
+ 0xe5,0x01,0x0b,0xe5,0xe6,0x05,0x02,0xe5,0x10,0xe5,0x01,0x0e,0xe8,0x05,0xe5,0xe6,
+ 0xe5,0x01,0xe5,0x1d,0x02,0x01,0xe5,0x01,0x0e,0x01,0xe5,0x04,0x03,0x01,0x0c,0x03,
+ 0xe5,0x01,0x0b,0xe5,0x01,0x01,0xe5,0x05,0xe5,0x03,0x03,0x1b,0x01,0x01,0xe5,0xe5,
+ 0xe5,0x03,0x15,0x12,0x07,0x0b,0x01,0x04,0xe5,0x03,0x06,0x1a,0x01,0x02,0x01,0xe5,
+ 0xe6,0xe7,0xe5,0x16,0x10,0x01,0x07,0x05,0xe5,0x03,0x01,0x04,0xe5,0xe5,0x01,0x06,
+ 0x1a,0xe5,0x04,0x02,0x01,0x01,0xe5,0xe5,0x18,0x09,0x04,0x04,0x04,0x04,0x08,0x0c,
+ 0x04,0x23,0xe6,0xe7,0xe5,0x01,0x25,0x04,0x04,0x03,0x07,0x03,0x01,0x02,0x04,0x04,
+ 0xe5,0x02,0x1d,0xe5,0xe6,0x01,0x02,0x18,0x02,0x06,0x02,0x02,0x01,0x04,0x02,0x06,
+ 0x01,0x02,0x01,0x03,0xe5,0x08,0xe7,0x20,0x06,0xe5,0x1a,0x01,0xe5,0x05,0xe7,0xe5,
+ 0x03,0x01,0xe7,0x02,0xe7,0x03,0x01,0x04,0x02,0x03,0xe5,0xe5,0x01,0x25,0x01,0xe5,
+ 0x04,0x14,0x01,0xe5,0xe6,0x02,0x01,0x09,0x07,0x01,0x0c,0x01,0xe5,0x02,0x01,0x02,
+ 0x25,0x01,0x02,0x01,0x18,0xe5,0x07,0xe5,0x11,0xe5,0x13,0xe5,0x01,0x27,0x02,0xe6,
+ 0x0d,0x09,0xe6,0x06,0xe6,0x06,0x09,0xe5,0x04,0x04,0x09,0xe5,0x01,0x05,0x02,0x01,
+ 0x01,0x02,0x09,0x0d,0xe9,0x01,0x19,0x09,0x09,0x09,0xe5,0x01,0x11,0x2a,0x02,0x39,
+ 0x01,0x13,0x2b,0x02,0x17,0x01,0xe7,0x06,0x01,0x09,0x06,0xe7,0x02,0x02,0x01,0x04,
+ 0x05,0xe6,0xe5,0xe6,0xe5,0x08,0x18,0xe8,0x16,0x01,0xe6,0x08,0x09,0x04,0x02,0xe6,
+ 0x01,0x04,0x01,0xe5,0x04,0x02,0xe6,0x04,0x01,0xe5,0x05,0x02,0x17,0xe8,0x15,0x04,
+ 0x0c,0x0e,0x09,0x01,0x04,0x04,0x01,0x05,0x01,0x06,0x02,0x18,0xe6,0xe5,0x14,0xe5,
+ 0x05,0xe6,0x06,0xe6,0x08,0xe5,0x01,0xe5,0x02,0xe5,0x02,0x01,0x04,0xe5,0x02,0x04,
+ 0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0x06,0xe5,0x07,0xe5,0x0a,0x17,0x01,0xe5,0x03,0x09,
+ 0x01,0x01,0x09,0xe5,0x07,0x01,0xe6,0x06,0xe5,0x11,0x18,0xe5,0x01,0x17,0x01,0x03,
+ 0x02,0x06,0x02,0xe5,0xe5,0x08,0x06,0x02,0x01,0x06,0x02,0xe5,0x04,0x09,0xe5,0x19,
+ 0xe8,0x19,0x03,0xe5,0x07,0xe5,0xe5,0xe5,0x08,0xe5,0x02,0x03,0x02,0x04,0x04,0x04,
+ 0x09,0x04,0x17,0xe9,0x1b,0xe5,0x07,0xe5,0x02,0x01,0x02,0x06,0x02,0x06,0x02,0x03,
+ 0x04,0x02,0x07,0x03,0x02,0x1a,0xe9,0x09,0x09,0x09,0x08,0x05,0xe5,0x07,0x0c,0x05,
+ 0x02,0x06,0x24,0x03,0x0b,0x05,0x01,0x06,0xe5,0xe5,0x06,0xe6,0xe5,0x04,0x01,0xe5,
+ 0x05,0x01,0x04,0x04,0xe7,0x01,0x03,0x01,0xe6,0x04,0x01,0x07,0x01,0xe5,0xe5,0x03,
+ 0x01,0x0a,0xe8,0x0e,0xe5,0x09,0x07,0xe5,0x05,0x08,0xe5,0xe5,0x02,0x08,0xe6,0xe5,
+ 0xe6,0xe6,0x01,0x04,0xe5,0x0c,0x0a,0x06,0x02,0x01,0xe7,0x13,0x07,0xe5,0x01,0x01,
+ 0x06,0x0c,0xe5,0x03,0x03,0x03,0x05,0x12,0x1a,0x01,0x02,0x0d,0x01,0x03,0x09,0x02,
+ 0x04,0x01,0xe5,0xe5,0x08,0x09,0xe5,0x05,0x03,0x01,0x07,0x01,0x0d,0x0f,0xe5,0x03,
+ 0x03,0x03,0xe5,0x18,0x0e,0x12,0xe7,0x06,0x01,0x09,0x03,0x19,0x05,0x02,0xe5,0x06,
+ 0x09,0x09,0xe5,0x07,0x02,0x01,0x05,0x01,0x0b,0x01,0x07,0x03,0x01,0x03,0x01,0x0f,
+ 0x10,0x02,0xe5,0xe8,0x08,0x01,0x06,0x12,0x06,0x09,0x03,0xe5,0x01,0x03,0x03,0x03,
+ 0xe6,0x08,0x06,0x10,0x01,0x07,0xe5,0xe8,0xe5,0x0c,0x0f,0x0b,0x02,0xe5,0x04,0x04,
+ 0x03,0xe5,0x02,0x03,0x02,0x02,0x01,0x04,0x06,0x0b,0x10,0x01,0xe5,0xe5,0x11,0x01,
+ 0x06,0x14,0x08,0x02,0x01,0xe5,0x03,0xe5,0xe5,0x01,0x02,0x04,0x02,0x02,0x01,0x1f,
+ 0x03,0xe5,0x0a,0x09,0x09,0xe7,0x02,0x0d,0xe6,0x06,0xe6,0x03,0x05,0x04,0x27,0xe7,
+ 0xe5,0xe5,0x06,0x1a,0x03,0x0e,0x07,0x01,0x0a,0x23,0x0b,0xe7,0xe6,0x11,0x02,0x0a,
+ 0xe5,0xe5,0x01,0x02,0x01,0x07,0x03,0xe5,0x05,0x0d,0x02,0x02,0x05,0x1b,0x02,0x01,
+ 0x03,0x0f,0x09,0xe5,0x06,0x05,0xe5,0xe7,0x01,0x01,0xe6,0xe5,0x04,0xe7,0x05,0x02,
+ 0xe5,0x06,0xe5,0x04,0x1d,0x02,0x17,0x0d,0x06,0x02,0x06,0x16,0x09,0x24,0x01,0x01,
+ 0x11,0xe5,0x08,0x01,0x0d,0xe5,0x04,0x02,0xe5,0x0b,0x08,0x05,0x02,0xe6,0x06,0xe5,
+ 0x13,0x01,0xe6,0xe5,0x01,0x01,0x0e,0xe5,0x08,0xe5,0xe6,0x03,0xe5,0x0f,0x15,0x06,
+ 0xe6,0x09,0x11,0x01,0x01,0x02,0xe6,0x03,0x15,0x08,0xe5,0x09,0x05,0x06,0x01,0x04,
+ 0x11,0x01,0x02,0x15,0x01,0x02,0x01,0xe5,0xe6,0x01,0x02,0x17,0x06,0x03,0x01,0xe5,
+ 0x12,0x1a,0x18,0xe5,0x04,0x03,0xe5,0xe6,0xe5,0x18,0x06,0x02,0x03,0xe5,0x08,0x01,
+ 0x05,0x03,0x04,0x01,0x01,0x06,0x02,0xe5,0xe6,0x02,0x01,0x1a,0xe5,0xe5,0xe5,0x01,
+ 0x1e,0x03,0x02,0xe6,0x01,0x01,0x01,0x02,0xe5,0xe5,0xe5,0x06,0x04,0x04,0x08,0xe5,
+ 0xe6,0x01,0x02,0x15,0x02,0xe5,0x03,0xe5,0x01,0x18,0x07,0x04,0x01,0x0a,0x01,0x09,
+ 0x01,0x02,0x01,0x01,0x08,0x01,0x01,0x0c,0x12,0x02,0xe8,0x1b,0xe6,0x01,0x03,0xe5,
+ 0xe5,0x0b,0x01,0x09,0x04,0x01,0x01,0xe5,0x08,0x01,0xe5,0x22,0x01,0xe5,0x07,0x10,
+ 0x01,0xe5,0x01,0x03,0x01,0x02,0x07,0x02,0x06,0xe5,0x08,0xe5,0x01,0x06,0xe5,0x07,
+ 0x09,0x02,0x10,0x04,0x0a,0x01,0x0d,0xe5,0x01,0x05,0xe5,0x15,0x0b,0xe5,0x04,0x02,
+ 0xe5,0x07,0xe6,0x1a,0x01,0xe8,0x06,0x05,0x09,0xe6,0xe5,0x04,0xe5,0x02,0x01,0x02,
+ 0x02,0x06,0x02,0xe5,0x01,0x04,0x09,0x09,0xe5,0x02,0x01,0x02,0x09,0x0d,0x01,0x02,
+ 0x02,0x19,0x03,0x04,0xe5,0x02,0x09,0x08,0xe5,0x06,0x09,0x03,0x09,0x1f,0x1f,0x05,
+ 0x03,0x09,0x09,0x13,0x09,0x1e,0x01,0x01,0x17,0x01,0xe5,0xe5,0x05,0xe7,0x02,0x02,
+ 0x07,0x01,0x04,0x09,0x01,0x01,0xe5,0x03,0x04,0x02,0x08,0x07,0x01,0x0e,0xe5,0xe6,
+ 0x15,0xe5,0xe7,0x01,0x02,0x02,0xe5,0x01,0x02,0x01,0xe5,0x05,0x01,0xe5,0x09,0x01,
+ 0x05,0x02,0xe5,0xe5,0x01,0xe5,0xe6,0x05,0x02,0x06,0x01,0xe5,0x0c,0x01,0x01,0x08,
+ 0x0b,0x02,0x0b,0xe5,0x05,0x01,0x09,0x04,0x06,0x07,0x09,0x09,0x09,0x01,0x10,0x01,
+ 0x15,0xe6,0x04,0xe8,0x04,0xe8,0xe5,0x04,0xe6,0xe5,0x03,0xe5,0x0a,0x01,0x07,0x01,
+ 0x01,0x05,0x03,0x05,0xe6,0xe5,0x04,0xe5,0x06,0xe5,0x01,0x1a,0x08,0x09,0xe5,0x05,
+ 0x01,0xe5,0x09,0x07,0x01,0x07,0x0b,0x1b,0xe5,0x19,0x02,0x02,0xe5,0x05,0x01,0xe5,
+ 0xe5,0x06,0x01,0xe5,0x02,0x01,0x0b,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0x19,0x01,
+ 0x01,0xe5,0x15,0x06,0xe5,0x02,0x03,0x01,0x01,0x01,0xe5,0x07,0x08,0x02,0x07,0x09,
+ 0x09,0x1b,0xe7,0x16,0x04,0xe5,0xe7,0x03,0x01,0xe7,0xe6,0x05,0x01,0xe5,0x02,0x09,
+ 0x01,0x02,0x04,0x04,0x0b,0x1a,0x01,0xe5,0x34,0x01,0x03,0x04,0x01,0xe6,0x01,0xe5,
+ 0x03,0xe5,0x02,0x01,0x23,0x01,0x01,0xe5,0x10,0x01,0x07,0x01,0xe5,0x05,0x01,0x06,
+ 0xe5,0xe6,0x05,0x01,0x04,0xe5,0x02,0x01,0x07,0x01,0x02,0xe5,0x02,0x01,0xe5,0xe5,
+ 0x03,0x01,0xe6,0x04,0x01,0x0a,0x03,0x16,0x02,0xe5,0x07,0x06,0x02,0xe5,0x04,0x02,
+ 0xe5,0x02,0x08,0x01,0x03,0x01,0xe5,0x08,0x02,0x05,0xe5,0x01,0x0a,0x09,0x01,0x01,
+ 0xe5,0x15,0x01,0x05,0x0c,0x09,0xe5,0xe5,0x01,0x03,0x06,0x02,0xe5,0xe5,0x02,0xe5,
+ 0x01,0x03,0x01,0x03,0x08,0x09,0x06,0xe5,0xe7,0x04,0x1d,0x01,0x07,0x0a,0xe5,0x03,
+ 0xe5,0x05,0x03,0x05,0xe5,0x01,0x0c,0x18,0xe9,0x17,0x05,0x0a,0x05,0x09,0x06,0x06,
+ 0x04,0x07,0xe6,0xe5,0x0e,0x0b,0x05,0xe5,0xe5,0x15,0xe5,0x07,0x0e,0x01,0x01,0x0b,
+ 0x04,0xe5,0x02,0x01,0x05,0xe6,0xe5,0x15,0x09,0x02,0x03,0xe7,0x17,0x12,0x0d,0x03,
+ 0x0a,0x09,0x01,0xe5,0x02,0x01,0x1b,0x01,0xe5,0xe5,0x11,0x0d,0x0a,0xe6,0x05,0xe5,
+ 0x02,0x05,0xe5,0x09,0x01,0x03,0x06,0x04,0x1b,0x01,0xe5,0xe5,0x1a,0x0a,0x0b,0x01,
+ 0xe5,0x05,0x02,0xe5,0x04,0xe6,0x08,0x09,0x14,0x08,0xe5,0x01,0x06,0x11,0x0c,0x01,
+ 0x11,0x04,0xe5,0x09,0x05,0x08,0x1f,0xe5,0xe7,0x0a,0x06,0x03,0x02,0x06,0x1e,0x09,
+ 0x07,0x0c,0x04,0x09,0x0d,0x02,0xe5,0x01,0x06,0x09,0x05,0x03,0x04,0x06,0x02,0x10,
+ 0x06,0x08,0x03,0x02,0x01,0x01,0x07,0x12,0x04,0x04,0x03,0x18,0x0d,0x02,0x0d,0x04,
+ 0x05,0x02,0x03,0x03,0x05,0x03,0x05,0x11,0x09,0xe5,0xe5,0x1e,0x05,0x03,0x01,0x17,
+ 0x06,0x09,0x05,0x02,0xe5,0x12,0x07,0x01,0x03,0x06,0x23,0x06,0x04,0x0b,0x10,0x01,
+ 0x08,0x11,0x02,0x02,0xe5,0xe6,0x07,0x07,0x14,0x08,0x06,0x18,0x09,0x09,0x09,0x0e,
+ 0x02,0xe6,0x0a,0x09,0x09,0x02,0xe5,0x1d,0xe5,0x01,0x01,0x04,0xe5,0x24,0xe6,0xe9,
+ 0x01,0x01,0x08,0x09,0xe6,0x06,0xe6,0xe5,0x1e,0x02,0x01,0xe5,0x2a,0x01,0x01,0xe5,
+ 0xe5,0x03,0x08,0x06,0x01,0x0a,0x2c,0xe5,0x26,0x02,0xe5,0xe6,0x01,0x0a,0x06,0xe5,
+ 0x02,0x04,0x02,0x01,0x27,0x06,0xe5,0x02,0x1c,0x02,0x01,0xe6,0xe6,0x0c,0x09,0x01,
+ 0x02,0x02,0x01,0x01,0x03,0x02,0xe5,0xe5,0x06,0x01,0x15,0x01,0xe5,0xe5,0xe5,0x05,
+ 0x02,0x19,0xe6,0xe7,0x01,0x0a,0x03,0x05,0x01,0x02,0x01,0x01,0xe5,0xe5,0xe5,0x03,
+ 0xe5,0xe5,0xe5,0x04,0x01,0x01,0x16,0x08,0x02,0x01,0x15,0x02,0x01,0xe5,0x02,0xe5,
+ 0x03,0xe5,0x05,0x0e,0x04,0x01,0x03,0xe6,0xe5,0xe5,0x06,0x01,0x15,0x02,0x0b,0x1a,
+ 0x02,0xe5,0xe6,0x05,0x06,0x0b,0x07,0x05,0xe5,0x01,0x01,0x07,0x01,0x18,0xe6,0x07,
+ 0xe6,0x18,0x01,0xe6,0xe6,0x12,0x08,0x0a,0x02,0x25,0x14,0xe5,0x0c,0x02,0x03,0x02,
+ 0x0a,0x09,0x01,0x11,0xe5,0x31,0x09,0xe5,0x12,0x02,0xe5,0x09,0x03,0x05,0xe5,0x01,
+ 0x06,0x02,0x02,0x06,0x09,0x0b,0x09,0x04,0x01,0x02,0x03,0x05,0x09,0x0d,0xe9,0x01,
+ 0x12,0x09,0xe5,0x2e,0x03,0x26,0xe5,0xe5,0x1e,0x31,0x2b,0xe5,0xe5,0x0a,0x01,0x09,
+ 0x04,0x02,0x06,0x1f,0x07,0x01,0x0e,0x1a,0x01,0x0d,0x01,0xe5,0x04,0xe5,0x01,0xe5,
+ 0x07,0x05,0x03,0x19,0x06,0x07,0xe5,0x04,0x02,0xe5,0x17,0x02,0x0c,0x0c,0x06,0x3e,
+ 0x1a,0x01,0x01,0x13,0xe5,0xe6,0x04,0xe6,0x06,0xe6,0x06,0xe6,0x08,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x06,0x01,0xe6,0x13,0x05,0x04,0x04,0xe5,
+ 0x02,0x01,0x02,0x03,0xe5,0x18,0x0a,0xe5,0x04,0x1a,0xe5,0xe6,0x15,0x07,0x01,0x09,
+ 0xe5,0x07,0x18,0x11,0x1b,0xe5,0xe5,0x12,0x01,0xe5,0x02,0x02,0x01,0x07,0xe6,0xe5,
+ 0x01,0x02,0x01,0x0c,0x0c,0x13,0x18,0x01,0xe6,0x12,0x06,0x01,0xe6,0x04,0x03,0x02,
+ 0x02,0x02,0x1b,0x02,0x07,0x08,0x18,0xe5,0x01,0x0d,0xe5,0xe5,0x05,0x01,0xe5,0x02,
+ 0x02,0x03,0x0a,0x02,0x17,0x02,0x03,0x05,0x0e,0x11,0x02,0x01,0x0a,0x06,0x01,0xe5,
+ 0x01,0x03,0x01,0x04,0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x01,0x04,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x02,0x04,0xe6,0x06,0x01,0x0b,0x02,0x09,0x04,0x0a,0x09,0xe5,
+ 0x01,0x05,0xe5,0x13,0xe5,0x01,0x03,0xe5,0x01,0x05,0x05,0x1e,0x01,0x01,0xe5,0xe5,
+ 0x01,0x0b,0x04,0x05,0x04,0x01,0x05,0x03,0x12,0xe5,0xe5,0x0b,0x01,0x06,0x01,0x1d,
+ 0x02,0x01,0x0b,0x0d,0x11,0x0e,0x04,0x09,0x30,0x03,0xe5,0x03,0x02,0x04,0x01,0x02,
+ 0x01,0xe5,0xe7,0x04,0x01,0x01,0x07,0x01,0x0a,0x0b,0x08,0x09,0xe5,0x05,0x01,0xe5,
+ 0x11,0x05,0x02,0x02,0x02,0x09,0x03,0x04,0x0a,0x0a,0x02,0x01,0x07,0x03,0x11,0x01,
+ 0x01,0x05,0x05,0x0d,0x06,0x02,0xe5,0xe5,0xe6,0x0b,0x08,0x06,0xe8,0xe5,0x03,0xe5,
+ 0xe5,0xe5,0x10,0x04,0x04,0x01,0x0a,0xe5,0x01,0x04,0xe6,0x16,0x02,0x01,0x05,0x0a,
+ 0x06,0x02,0x02,0x04,0x01,0x15,0x04,0x05,0x04,0x0a,0x01,0x21,0x03,0xe5,0x05,0x12,
+ 0x04,0x07,0x07,0x10,0x12,0x27,0xe8,0x02,0x08,0x0f,0x16,0x08,0x02,0x0a,0x05,0x03,
+ 0x07,0x1c,0xe6,0xe6,0xe5,0x11,0x1a,0x01,0x02,0x08,0x01,0x06,0x1c,0x16,0xe5,0xe6,
+ 0x08,0xe5,0x07,0x0c,0x02,0xe5,0x07,0x09,0x10,0x08,0x05,0xe5,0x03,0x01,0x01,0x17,
+ 0x01,0xe7,0x18,0x08,0xe5,0x02,0x05,0x08,0xe5,0x07,0x16,0x05,0xe5,0x01,0x01,0x18,
+ 0xe6,0x18,0x08,0x08,0xe5,0x09,0x17,0x01,0x03,0xe5,0x08,0x16,0x03,0x02,0x03,0x09,
+ 0x09,0x13,0x04,0x20,0xe5,0x01,0x02,0x06,0x17,0xe5,0x01,0x01,0xe6,0x0b,0x0b,0x02,
+ 0x0b,0x01,0xe7,0x22,0xe5,0x02,0x09,0x14,0x01,0x01,0x03,0xe5,0x0c,0x05,0xe5,0x0e,
+ 0x02,0xe5,0x04,0x22,0xe5,0x03,0x07,0x0f,0xe5,0x03,0x01,0x04,0x01,0xe5,0xe5,0x01,
+ 0x07,0x19,0xe5,0x01,0x01,0xe5,0x22,0x04,0x04,0xe5,0xe5,0x0e,0xe5,0x05,0x02,0x01,
+ 0x01,0xe5,0x0b,0x12,0xe5,0x02,0x05,0x01,0x02,0xe5,0x01,0x1e,0x01,0x02,0x1f,0xeb,
+ 0xe5,0x09,0x03,0x09,0x01,0x01,0xe6,0x08,0x01,0x04,0x01,0x20,0x02,0x06,0x01,0x01,
+ 0x01,0x02,0x0e,0x05,0xe6,0x0b,0x13,0x09,0x01,0x27,0x01,0x04,0x04,0x15,0x04,0xe7,
+ 0x0b,0x13,0x06,0x01,0xe5,0xe5,0xe5,0x2b,0xe5,0x02,0x1a,0xe6,0x1c,0x02,0x05,0xe5,
+ 0x07,0xe5,0x01,0x06,0x1c,0x02,0x01,0xe5,0x05,0x02,0x0b,0x04,0xe5,0x02,0x0a,0x13,
+ 0x06,0x02,0x01,0x05,0x01,0x0b,0x1d,0x1d,0x01,0xe7,0x09,0x03,0x02,0x06,0x02,0x02,
+ 0x03,0x03,0x05,0xe5,0xe5,0xe7,0x01,0x0b,0x09,0x04,0x01,0x02,0x02,0x01,0xe6,0x01,
+ 0x02,0x06,0x0d,0x01,0xe7,0x15,0x09,0x05,0x03,0x09,0x1f,0x09,0x1b,0xe8,0x14,0x09,
+ 0x08,0x08,0x20,0x08,0x1e,0xe5,0x01,0x16,0xe5,0xe5,0x06,0x01,0x06,0xe5,0x07,0x20,
+ 0x01,0xe6,0x04,0x01,0x19,0x01,0xe5,0x01,0x14,0x01,0xe5,0x05,0x01,0x01,0x01,0x06,
+ 0xe5,0x07,0x1c,0x08,0xe5,0x01,0x17,0xe6,0xe6,0x15,0x01,0x04,0x40,0x01,0x18,0xe8,
+ 0x14,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe6,0x01,
+ 0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x06,0x02,0xe5,0x16,0x01,0x07,0x01,0x57,0xe7,
+ 0x03,0x12,0x01,0x07,0x01,0x13,0x1f,0x07,0x1c,0xe6,0x16,0x01,0x26,0x14,0x01,0x07,
+ 0x1c,0x01,0x04,0x12,0x01,0x07,0x04,0x09,0x26,0x07,0x15,0x01,0x04,0xe6,0x0c,0x01,
+ 0xe5,0x09,0x05,0xe5,0xe5,0x13,0x1b,0x06,0x02,0x10,0x04,0x03,0xe6,0xe6,0x02,0xe5,
+ 0x06,0x01,0x02,0x01,0xe5,0x05,0x01,0x04,0x02,0xe6,0x06,0x01,0x01,0x05,0x01,0x04,
+ 0x04,0x01,0x02,0x04,0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x01,0x04,
+ 0x05,0xe6,0x02,0x12,0x0e,0x07,0x03,0x0c,0x08,0x0c,0x06,0x1e,0x01,0xe7,0x1d,0x08,
+ 0x01,0x0e,0x24,0x13,0x06,0xe5,0xe5,0xe5,0x14,0x09,0xe5,0x07,0xe5,0x01,0x01,0x0a,
+ 0x02,0x01,0x05,0x34,0xe9,0xe5,0x01,0x02,0x0e,0x01,0x07,0x01,0xe5,0x05,0xe7,0x01,
+ 0xe5,0x01,0x0f,0x0f,0x09,0x15,0x07,0xe5,0x16,0x01,0x0a,0x03,0x03,0x06,0x03,0x02,
+ 0x04,0x13,0x03,0x09,0x03,0x10,0x02,0x01,0xe5,0xe6,0x18,0x06,0x0b,0xe6,0x07,0x06,
+ 0x06,0x07,0x0e,0x1b,0xe9,0x0f,0x05,0x04,0x08,0x06,0xe5,0x04,0x05,0x02,0x03,0x14,
+ 0x04,0x03,0x1b,0x01,0x02,0x11,0x0a,0xe5,0x07,0x06,0x11,0xe5,0x39,0x02,0x0d,0xe5,
+ 0x0b,0x03,0x0c,0x10,0x01,0x39,0x01,0xe5,0xe5,0x0c,0x02,0x05,0x04,0x10,0x05,0xe5,
+ 0x0a,0x3a,0xe5,0xe6,0x01,0x16,0x0d,0x02,0x06,0x05,0xe5,0x06,0xe5,0xe5,0x0e,0x25,
+ 0xe5,0x01,0xe5,0x1b,0x09,0xe5,0x04,0x08,0xe5,0x07,0x02,0x19,0x11,0x0b,0x02,0x17,
+ 0x15,0x06,0x02,0x0a,0x3a,0xe7,0x11,0xe5,0x04,0x0f,0x4b,0xe5,0x02,0xe6,0x01,0x01,
+ 0x0e,0xe5,0x05,0x0f,0xe6,0x11,0x34,0x01,0x01,0x03,0xe5,0x03,0x05,0x01,0xe5,0xe5,
+ 0x03,0xe5,0xe5,0xe6,0x0f,0x01,0x04,0x01,0xe5,0x01,0x03,0xe5,0x02,0x04,0x28,0xe5,
+ 0x03,0x01,0x03,0x02,0x02,0x07,0x02,0x01,0x04,0xe5,0xe5,0xe6,0x0c,0xe5,0xe5,0xe5,
+ 0x03,0xe5,0x02,0x04,0x32,0xe5,0x05,0x02,0x01,0x01,0x0b,0x01,0x01,0x02,0x04,0x21,
+ 0xe5,0x01,0xe5,0xe5,0x05,0x02,0x2d,0xe7,0xe6,0x01,0x0a,0x01,0x02,0x04,0x13,0x01,
+ 0x01,0x01,0x02,0x05,0x02,0xe5,0x05,0x2e,0x02,0x03,0x01,0xe6,0x17,0x11,0x01,0x07,
+ 0x07,0x03,0x35,0x02,0xe8,0x11,0x06,0x11,0x01,0x09,0x03,0xe5,0x3d,0x01,0xe5,0x11,
+ 0x09,0x14,0x02,0x05,0x3e,0xe7,0xe5,0x1a,0xe5,0x1e,0x3d,0xe5,0x01,0xe5,0x0a,0x02,
+ 0x09,0x09,0x09,0x06,0x02,0x03,0x02,0x04,0x09,0x09,0x09,0x09,0x0d,0xe9,0x01,0x08,
+ 0xe5,0x04,0x09,0x14,0x02,0x05,0x02,0xe5,0x3a,0xe5,0xe6,0x0a,0x26,0x08,0x40,0xe6,
+ 0x0c,0x04,0x04,0x01,0x02,0x15,0x0b,0x04,0x36,0xe8,0x0e,0x01,0x02,0x02,0x01,0xe6,
+ 0xe5,0x0f,0x0a,0x09,0xe5,0x35,0xe8,0x08,0x02,0x09,0x01,0x10,0x07,0x08,0x07,0x2e,
+ 0x08,0xe7,0x0e,0x05,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x0c,0x09,0x01,0x14,0x14,0x36,
+ 0x02,0xe5,0x0e,0x07,0x16,0x4d,0x01,0xe5,0x0b,0x09,0x01,0x11,0x0b,0x01,0x06,0x02,
+ 0x36,0xe5,0xe6,0x02,0x0b,0x02,0x04,0x04,0x0e,0x02,0x11,0x39,0xe5,0x01,0x2b,0x15,
+ 0x01,0xe5,0x20,0x12,0xe5,0xe7,0x10,0x01,0x02,0x03,0xe5,0xe5,0x06,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0b,0xe5,
+ 0xe5,0x18,0x12,0x02,0x09,0x21,0x01,0x1c,0xe6,0xe6,0x13,0x1c,0x0b,0x01,0x13,0x24,
+ 0xe5,0x01,0xe5,0x18,0x14,0x10,0x3b,0x02,0x17,0x01,0x0e,0x02,0x01,0x07,0xe5,0x09,
+ 0x01,0x16,0x1a,0x05,0x02,0x17,0x01,0x13,0x0d,0x03,0x04,0x03,0x10,0x1c,0x02,0x02,
+ 0xe6,0x19,0x09,0x06,0x05,0x0f,0x37,0x01,0xe7,0x25,0x04,0x01,0x11,0x08,0x10,0x1f,
+ 0x02,0x01,0x26,0x08,0x0f,0x06,0x33,0x01,0x01,0x0a,0x10,0x0f,0x13,0x07,0x31,0x02,
+ 0xe6,0x11,0x16,0x01,0x03,0x0f,0x3b,0x02,0x14,0x01,0x16,0xe5,0x0c,0x28,0x13,0x04,
+ 0xe5,0x2b,0x0a,0x36,0x0a,0x01,0x01,0x2b,0xe5,0x0d,0x3e,0xe8,0xe5,0x75,0xe5,0x03,
+ 0x02,0x01,0x28,0x47,0x01,0x02,0xe6,0xe5,0x03,0x23,0x01,0x4a,0x04,0xe5,0x01,0x02,
+ 0x74,0x02,0xe6,0xe6,0x04,0x05,0x21,0x01,0x01,0x01,0x45,0x01,0xe6,0x01,0x08,0x25,
+ 0x02,0x3f,0x02,0x05,0xe6,0x72,0x04,0xe5,0xe5,0xe5,0x01,0x2c,0x4a,0x03,0xe6,0x2d,
+ 0x43,0x06,0x01,0xe5,0x7a,0xe8,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,
+ 0x0d,0x03,0xe5,0x01,0x27,0x4c,0x06,0x29,0x52,0x01,0x2d,0xe5,0x48,0x03,0x01,0x16,
+ 0x03,0x14,0x4a,0xe6,0xe5,0x2c,0x03,0x4a,0xe6,0x03,0x10,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,
+ 0xe5,0x16,0x01,0x13,0x4c,0x03,0x17,0x01,0x63,0xe6,0x15,0x01,0x13,0x12,0x39,0x03,
+ 0x03,0x13,0x01,0x16,0x49,0xe5,0xe6,0x2a,0x01,0xe5,0x49,0x02,0xe6,0x10,0x01,0x01,
+ 0x05,0x01,0x02,0x03,0xe5,0xe5,0x02,0x03,0x01,0x01,0x05,0x01,0x01,0x02,0x03,0xe5,
+ 0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe5,0x01,0x5b,0x22,0xe5,0x09,
+ 0x34,0x07,0x09,0x0b,0x1a,0x02,0x01,0x3f,0x3a,0xe6,0xe5,0x16,0x10,0x17,0x07,0x2b,
+ 0x08,0xe5,0x19,0x16,0x09,0x03,0x3b,0xe7,0x23,0x1a,0x04,0xe5,0x33,0x01,0xe6,0x1b,
+ 0x22,0x0a,0x0d,0x23,0x01,0x3f,0x3c,0xe6,0x20,0xe6,0x15,0x04,0x2a,0x09,0x06,0xe5,
+ 0xe5,0x23,0x1a,0xe5,0x28,0x0f,0x02,0xe5,0x38,0x41,0xe5,0xe6,0xe5,0x24,0x04,0x1a,
+ 0x30,0x01,0xe5,0xe5,0x2c,0x4c,0xe5,0x01,0xe6,0x75,0xe8,0xe5,0x01,0x01,0x70,0x01,
+ 0x03,0xe5,0xe5,0x03,0x70,0x04,0xe5,0x01,0x02,0x74,0x02,0x01,0xe6,0x01,0x78,0x02,
+ 0x74,0x02,0x02,0xe8,0x13,0x5f,0x04,0x03,0xe5,0x13,0xe5,0x63,0x01,0xe6,0x08,0x02,
+ 0x08,0x64,0xe5,0x01,0x0a,0xe5,0x6e,0xe5,0xe6,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x09,0x09,0x0d,0xe9,0x01,0x74,0x06,0x7a,0x03,0x01,0x2b,0x4d,0xe5,0xe5,0x23,
+ 0x08,0xe5,0x47,0x02,0xe8,0x2c,0x4b,0xe5,0x01,0xe5,0x12,0x01,0x07,0xe6,0x07,0xe5,
+ 0x02,0x03,0x01,0x09,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,
+ 0x01,0xe6,0x0f,0xe5,0x02,0x09,0x01,0x01,0xe5,0x03,0x03,0x03,0x01,0x38,0x0b,0x01,
+ 0x01,0x01,0x13,0x02,0x09,0xe5,0xe6,0x02,0x01,0x02,0x06,0x37,0x0d,0x01,0x01,0x15,
+ 0x07,0xe6,0xe5,0xe5,0x04,0x03,0x05,0x47,0xe5,0xe5,0x0f,0x02,0xe5,0x07,0xe5,0x01,
+ 0x01,0xe5,0x01,0xe5,0x03,0x03,0xe5,0x38,0x0e,0x01,0xe5,0x2e,0x33,0x15,0xe5,0xe5,
+ 0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x02,0xe5,0xe6,
+ 0x07,0x01,0xe5,0x05,0x01,0xe6,0x04,0xe7,0x05,0x01,0x07,0x01,0x0b,0xe7,0x3d,0x15,
+ 0x21,0x03,0x03,0xe5,0x3e,0x38,0xe5,0xe5,0xe5,0x12,0x02,0x09,0x1e,0x07,0x32,0x03,
+ 0xe5,0x19,0x05,0x01,0x0a,0x09,0x06,0x3a,0xe5,0x01,0x23,0x03,0x17,0x3a,0x03,0xe5,
+ 0x1f,0x1d,0x16,0xe5,0x24,0xe5,0x1e,0x09,0x12,0x02,0x15,0x01,0x23,0xe7,0x3e,0x23,
+ 0x17,0x01,0xe5,0x3e,0x3c,0xe6,0x24,0x19,0x3d,0xe6,0x1b,0xe5,0x04,0x02,0xe5,0x08,
+ 0x38,0x12,0x33,0x36,0xe6,0x0b,0x01,0xe5,0xe5,0x6a,0x10,0xe6,0x02,0x0b,0xe5,0xe5,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x0b,0x03,0xe5,0x0f,0x09,0x09,0x09,0x09,0x04,0x04,0x01,0x09,0x09,0x09,
+ 0x01,0x07,0x0d,0xe5,0xe6,0x0e,0x09,0x03,0x05,0x09,0x09,0x04,0x06,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x09,0x0e,0x03,0x26,0x57,0x0f,0x09,0x09,0x09,0x09,0x0b,0x01,0x07,
+ 0x09,0x09,0x02,0x06,0x0e,0xe5,0xe6,0x0c,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0x03,0x03,0x09,0x09,
+ 0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x12,0xe6,0x0d,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0b,0x03,0x0e,0x09,0x09,0x09,0x09,0x03,
+ 0x07,0x09,0x09,0x09,0x09,0x0f,0x02,0xe5,0x79,0xe5,0x01,0x0e,0x09,0x09,0x09,0x09,
+ 0x08,0x02,0x09,0x09,0x09,0x09,0x11,0xe6,0x3e,0x3b,0x02,0x10,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x09,0x10,0xe5,0x7d,0x3f,0x3a,0xe5,0x01,0x3f,0x36,0x04,0x02,
+ 0x7a,0x01,0x01,0x13,0x3d,0x28,0x01,0x01,0x3f,0x33,0x0a,0x3f,0x34,0x08,0xe5,0x79,
+ 0x01,0x01,0x14,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0xe5,0x01,0x0f,
+ 0x09,0x09,0x09,0x09,0x07,0x03,0x09,0x09,0x09,0x08,0xe5,0x0d,0x03,0x3a,0x04,0x3a,
+ 0x02,0xe5,0x0c,0x09,0x03,0x05,0x09,0x09,0x03,0x07,0x09,0x09,0x07,0x01,0x1b,0x01,
+ 0xe5,0x0a,0x02,0x07,0x05,0x03,0x01,0x03,0x03,0x01,0x03,0x03,0x09,0x06,0xe5,0x02,
+ 0x04,0x04,0x04,0x02,0x06,0xe5,0x02,0x02,0x06,0x02,0xe5,0x02,0x03,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,
diff --git a/u-boot/board/esd/cms700/Makefile b/u-boot/board/esd/cms700/Makefile
new file mode 100644
index 0000000..15a32a0
--- /dev/null
+++ b/u-boot/board/esd/cms700/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	$(CPLD) \
+	../common/esd405ep_nand.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/cms700/cms700.c b/u-boot/board/esd/cms700/cms700.c
new file mode 100644
index 0000000..dcd49d4
--- /dev/null
+++ b/u-boot/board/esd/cms700/cms700.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2005-2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO12 (CS3) pin
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Setup and enable EEPROM write protection
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
+int checkboard (void)
+{
+	char str[64];
+	int flashcnt;
+	int delay;
+
+	puts ("Board: ");
+
+	if (getenv_f("serial#", str, sizeof(str))  == -1) {
+		puts ("### No HW ID - assuming CMS700");
+	} else {
+		puts(str);
+	}
+
+	printf(" (PLD-Version=%02d)\n",
+	       in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
+
+	/*
+	 * Flash LEDs
+	 */
+	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+		out_8((void *)LED_REG, 0x00); /* LEDs off */
+		for (delay = 0; delay < 100; delay++)
+			udelay(1000);
+		out_8((void *)LED_REG, 0x0f); /* LEDs on */
+		for (delay = 0; delay < 50; delay++)
+			udelay(1000);
+	}
+	out_8((void *)LED_REG, 0x70);
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/u-boot/board/esd/cms700/flash.c b/u-boot/board/esd/cms700/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/cms700/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/common/auto_update.c b/u-boot/board/esd/common/auto_update.c
new file mode 100644
index 0000000..4dfea71
--- /dev/null
+++ b/u-boot/board/esd/common/auto_update.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2003-2004
+ * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <command.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <fat.h>
+#include <part.h>
+
+#include "auto_update.h"
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#if !defined(CONFIG_CMD_FAT)
+#error "must define CONFIG_CMD_FAT"
+#endif
+
+extern au_image_t au_image[];
+extern int N_AU_IMAGES;
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x100000)
+#define MAX_LOADSZ 0x1c00000
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+long do_fat_read (const char *filename, void *buffer,
+		  unsigned long maxsize, int dols);
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+
+extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+int au_check_cksum_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	if ((au_image[i].type == AU_FIRMWARE) &&
+	    (au_image[i].size != image_get_data_size (hdr))) {
+		printf ("Image %s has wrong size\n", au_image[i].name);
+		return -1;
+	}
+
+	if (nbytes != (image_get_image_size (hdr))) {
+		printf ("Image %s bad total SIZE\n", au_image[i].name);
+		return -1;
+	}
+
+	/* check the data CRC */
+	if (!image_check_dcrc (hdr)) {
+		printf ("Image %s bad data checksum\n", au_image[i].name);
+		return -1;
+	}
+	return 0;
+}
+
+int au_check_header_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* check the easy ones first */
+	if (nbytes < image_get_header_size ()) {
+		printf ("Image %s bad header SIZE\n", au_image[i].name);
+		return -1;
+	}
+	if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
+		printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
+		return -1;
+	}
+	if (!image_check_hcrc (hdr)) {
+		printf ("Image %s bad header checksum\n", au_image[i].name);
+		return -1;
+	}
+
+	/* check the type - could do this all in one gigantic if() */
+	if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) &&
+	    !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+	if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) &&
+	    !image_check_type (hdr, IH_TYPE_SCRIPT)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+
+	/* recycle checksum */
+	checksum = image_get_data_size (hdr);
+
+	return 0;
+}
+
+int au_do_update(int i, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+	int k;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	switch (au_image[i].type & AU_TYPEMASK) {
+	case AU_SCRIPT:
+		printf("Executing script %s\n", au_image[i].name);
+
+		/* execute a script */
+		if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
+			addr = (char *)((char *)hdr + image_get_header_size ());
+			/* stick a NULL at the end of the script, otherwise */
+			/* parse_string_outer() runs off the end. */
+			addr[image_get_data_size (hdr)] = 0;
+			addr += 8;
+
+			/*
+			 * Replace cr/lf with ;
+			 */
+			k = 0;
+			while (addr[k] != 0) {
+				if ((addr[k] == 10) || (addr[k] == 13)) {
+					addr[k] = ';';
+				}
+				k++;
+			}
+
+			run_command(addr, 0);
+			return 0;
+		}
+
+		break;
+
+	case AU_FIRMWARE:
+	case AU_NOR:
+	case AU_NAND:
+		start = au_image[i].start;
+		end = au_image[i].start + au_image[i].size - 1;
+
+		/*
+		 * do not update firmware when image is already in flash.
+		 */
+		if (au_image[i].type == AU_FIRMWARE) {
+			char *orig = (char*)start;
+			char *new  = (char *)((char *)hdr +
+					      image_get_header_size ());
+			nbytes = image_get_data_size (hdr);
+
+			while (--nbytes) {
+				if (*orig++ != *new++) {
+					break;
+				}
+			}
+			if (!nbytes) {
+				printf ("Skipping firmware update - "
+					"images are identical\n");
+				break;
+			}
+		}
+
+		/* unprotect the address range */
+		if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
+		    (au_image[i].type == AU_FIRMWARE)) {
+			flash_sect_protect (0, start, end);
+		}
+
+		/*
+		 * erase the address range.
+		 */
+		if (au_image[i].type != AU_NAND) {
+			printf ("Updating NOR FLASH with image %s\n",
+				au_image[i].name);
+			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+			flash_sect_erase (start, end);
+		}
+
+		udelay(10000);
+
+		/* strip the header - except for the kernel and ramdisk */
+		if (au_image[i].type != AU_FIRMWARE) {
+			addr = (char *)hdr;
+			off = image_get_header_size ();
+			nbytes = image_get_image_size (hdr);
+		} else {
+			addr = (char *)((char *)hdr + image_get_header_size ());
+			off = 0;
+			nbytes = image_get_data_size (hdr);
+		}
+
+		/*
+		 * copy the data from RAM to FLASH
+		 */
+		if (au_image[i].type != AU_NAND) {
+			debug ("flash_write(%p, %lx, %x)\n",
+			       addr, start, nbytes);
+			rc = flash_write ((char *)addr, start,
+					  (nbytes + 1) & ~1);
+		} else {
+			rc = -1;
+		}
+		if (rc != 0) {
+			printf ("Flashing failed due to error %d\n", rc);
+			return -1;
+		}
+
+		/*
+		 * check the dcrc of the copy
+		 */
+		if (au_image[i].type != AU_NAND) {
+			rc = crc32 (0, (uchar *)(start + off),
+				    image_get_data_size (hdr));
+		}
+		if (rc != image_get_dcrc (hdr)) {
+			printf ("Image %s Bad Data Checksum After COPY\n",
+				au_image[i].name);
+			return -1;
+		}
+
+		/* protect the address range */
+		/* this assumes that ONLY the firmware is protected! */
+		if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
+		    (au_image[i].type == AU_FIRMWARE)) {
+			flash_sect_protect (1, start, end);
+		}
+
+		break;
+
+	default:
+		printf("Wrong image type selected!\n");
+	}
+
+	return 0;
+}
+
+static void process_macros (const char *input, char *output)
+{
+	char c, prev;
+	const char *varname_start = NULL;
+	int inputcnt  = strlen (input);
+	int outputcnt = CONFIG_SYS_CBSIZE;
+	int state = 0;	/* 0 = waiting for '$'	*/
+			/* 1 = waiting for '(' or '{' */
+			/* 2 = waiting for ')' or '}' */
+			/* 3 = waiting for '''  */
+#ifdef DEBUG_PARSER
+	char *output_start = output;
+
+	printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n",
+		strlen(input), input);
+#endif
+
+	prev = '\0';			/* previous character */
+
+	while (inputcnt && outputcnt) {
+	    c = *input++;
+	    inputcnt--;
+
+	    if (state != 3) {
+	    /* remove one level of escape characters */
+	    if ((c == '\\') && (prev != '\\')) {
+		if (inputcnt-- == 0)
+			break;
+		prev = c;
+		c = *input++;
+	    }
+	    }
+
+	    switch (state) {
+	    case 0:			/* Waiting for (unescaped) $ */
+		if ((c == '\'') && (prev != '\\')) {
+			state = 3;
+			break;
+		}
+		if ((c == '$') && (prev != '\\')) {
+			state++;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    case 1:			/* Waiting for ( */
+		if (c == '(' || c == '{') {
+			state++;
+			varname_start = input;
+		} else {
+			state = 0;
+			*(output++) = '$';
+			outputcnt--;
+
+			if (outputcnt) {
+				*(output++) = c;
+				outputcnt--;
+			}
+		}
+		break;
+	    case 2:			/* Waiting for )	*/
+		if (c == ')' || c == '}') {
+			int i;
+			char envname[CONFIG_SYS_CBSIZE], *envval;
+			/* Varname # of chars */
+			int envcnt = input - varname_start - 1;
+
+			/* Get the varname */
+			for (i = 0; i < envcnt; i++) {
+				envname[i] = varname_start[i];
+			}
+			envname[i] = 0;
+
+			/* Get its value */
+			envval = getenv (envname);
+
+			/* Copy into the line if it exists */
+			if (envval != NULL)
+				while ((*envval) && outputcnt) {
+					*(output++) = *(envval++);
+					outputcnt--;
+				}
+			/* Look for another '$' */
+			state = 0;
+		}
+		break;
+	    case 3:			/* Waiting for '	*/
+		if ((c == '\'') && (prev != '\\')) {
+			state = 0;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    }
+	    prev = c;
+	}
+
+	if (outputcnt)
+		*output = 0;
+
+#ifdef DEBUG_PARSER
+	printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
+		strlen (output_start), output_start);
+#endif
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev = NULL;
+	long sz;
+	int i, res, cnt, old_ctrlc, got_ctrlc;
+	char buffer[32];
+	char str[80];
+	int n;
+
+	if  (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) {
+		stor_dev = get_dev ("ide", 0);
+		if (stor_dev == NULL) {
+			debug ("ide: unknown device\n");
+			return -1;
+		}
+	}
+
+	if (fat_register_device (stor_dev, 1) != 0) {
+		debug ("Unable to register ide disk 0:1\n");
+		return -1;
+	}
+
+	/*
+	 * Check if magic file is present
+	 */
+	if ((n = do_fat_read (AU_MAGIC_FILE, buffer,
+			      sizeof(buffer), LS_NO)) <= 0) {
+		debug ("No auto_update magic file (n=%d)\n", n);
+		return -1;
+	}
+
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show (1);
+#endif
+	puts("\nAutoUpdate Disk detected! Trying to update system...\n");
+
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc (0);
+
+	/* just loop thru all the possible files */
+	for (i = 0; i < N_AU_IMAGES; i++) {
+		/*
+		 * Try to expand the environment var in the fname
+		 */
+		process_macros (au_image[i].name, str);
+		strcpy (au_image[i].name, str);
+
+		printf("Reading %s ...", au_image[i].name);
+		/* just read the header */
+		sz = do_fat_read (au_image[i].name, LOAD_ADDR,
+				  image_get_header_size (), LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, image_get_header_size ());
+		if (sz <= 0 || sz < image_get_header_size ()) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_header_valid (i, sz) < 0) {
+			puts(" header not valid\n");
+			continue;
+		}
+		sz = do_fat_read (au_image[i].name, LOAD_ADDR,
+				  MAX_LOADSZ, LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, image_get_header_size ());
+		if (sz <= 0 || sz <= image_get_header_size ()) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_cksum_valid (i, sz) < 0) {
+			puts(" checksum not valid\n");
+			continue;
+		}
+		puts(" done\n");
+
+		do {
+			res = au_do_update (i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc ()) {
+				clear_ctrlc ();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+		} while (res < 0);
+	}
+
+	/* restore the old state */
+	disable_ctrlc (old_ctrlc);
+
+	puts("AutoUpdate finished\n\n");
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show (0);
+#endif
+
+	return 0;
+}
+
+int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	do_auto_update();
+
+	return 0;
+}
+U_BOOT_CMD(
+	autoupd,	1,	1,	auto_update,
+	"Automatically update images",
+	""
+);
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/u-boot/board/esd/common/auto_update.h b/u-boot/board/esd/common/auto_update.h
new file mode 100644
index 0000000..3ed0e16
--- /dev/null
+++ b/u-boot/board/esd/common/auto_update.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _AUTO_UPDATE_H_
+#define _AUTO_UPDATE_H_
+
+#define MBR_MAGIC       0x07081967
+#define MBR_MAGIC_ADDR  0x100           /* offset 0x100 should be free space */
+
+#define AU_MAGIC_FILE   "__auto_update"
+
+#define AU_TYPEMASK     0x000000ff
+#define AU_FLAGMASK     0xffff0000
+
+#define AU_PROTECT      0x80000000
+
+#define AU_SCRIPT       0x01
+#define AU_FIRMWARE     (0x02 | AU_PROTECT)
+#define AU_NOR          0x03
+#define AU_NAND         0x04
+
+struct au_image_s {
+	char name[80];
+	ulong start;
+	ulong size;
+	ulong type;
+};
+
+typedef struct au_image_s au_image_t;
+
+int do_auto_update(void);
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+void board_auto_update_show(int au_active);
+#endif
+
+#endif /* #ifndef _AUTO_UPDATE_H_ */
diff --git a/u-boot/board/esd/common/cmd_loadpci.c b/u-boot/board/esd/common/cmd_loadpci.c
new file mode 100644
index 0000000..8f4ad84
--- /dev/null
+++ b/u-boot/board/esd/common/cmd_loadpci.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#if !defined(CONFIG_440)
+#include <asm/4xx_pci.h>
+#endif
+
+#if defined(CONFIG_CMD_BSP)
+
+extern int do_source (cmd_tbl_t *, int, int, char *[]);
+
+#define ADDRMASK 0xfffff000
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 *ptr = 0;
+	int count = 0;
+	int count2 = 0;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+	u32 la, ptm1la;
+
+#if defined(CONFIG_440)
+	ptm1la = in32r(PCIL0_PTM1LA);
+#else
+	ptm1la = in32r(PTM1LA);
+#endif
+	while(1) {
+		/*
+		 * Mark sync address
+		 */
+		ptr = (u32 *)ptm1la;
+		memset(ptr, 0, 0x20);
+
+		*ptr = 0xffffffff;
+		puts("\nWaiting for action from pci host -");
+
+		/*
+		 * Wait for host to write the start address
+		 */
+		while (*ptr == 0xffffffff) {
+			count++;
+			if (!(count % 100)) {
+				count2++;
+				putc(0x08); /* backspace */
+				putc(str[count2 % 4]);
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			udelay(1000);
+		}
+
+		printf("\nGot bootcode %08x: ", *ptr);
+		la = ptm1la + (*ptr & ADDRMASK);
+		sprintf(addr, "%08x", la);
+
+		switch (*ptr & ~ADDRMASK) {
+		case 0:
+			/*
+			 * Boot image via bootm
+			 */
+			printf("booting image at addr 0x%s ...\n", addr);
+			setenv("loadaddr", addr);
+			do_bootm(cmdtp, 0, 0, NULL);
+			break;
+
+		case 1:
+			/*
+			 * Boot image via "source" command
+			 */
+			printf("executing script at addr 0x%s ...\n", addr);
+			local_args[0] = addr;
+			local_args[1] = NULL;
+			do_source(cmdtp, 0, 1, local_args);
+			break;
+
+		case 2:
+			/*
+			 * Call run_cmd
+			 */
+			printf("running command at addr 0x%s ...\n", addr);
+			run_command((char*)la, 0);
+			break;
+
+		default:
+			printf("unhandled boot method\n");
+			break;
+		}
+	}
+}
+
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"Wait for pci bootcmd and boot it",
+	""
+);
+
+#endif
diff --git a/u-boot/board/esd/common/esd405ep_nand.c b/u-boot/board/esd/common/esd405ep_nand.c
new file mode 100644
index 0000000..736176f
--- /dev/null
+++ b/u-boot/board/esd/common/esd405ep_nand.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
+		if ( ctrl & NAND_ALE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
+		if ( ctrl & NAND_NCE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+	if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
+		return 1;
+	return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+	/*
+	 * Set NAND-FLASH GPIO signals to defaults
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Initialize nand_chip structure
+	 */
+	nand->cmd_ctrl = esd405ep_nand_hwcontrol;
+	nand->dev_ready = esd405ep_nand_device_ready;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->chip_delay = NAND_BIG_DELAY_US;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
+}
+#endif
diff --git a/u-boot/board/esd/common/flash.c b/u-boot/board/esd/common/flash.c
new file mode 100644
index 0000000..b9c7885
--- /dev/null
+++ b/u-boot/board/esd/common/flash.c
@@ -0,0 +1,675 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef __PPC__
+#include <asm/ppc4xx.h>
+#endif
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST320:	printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST640:	printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CONFIG_SYS_FLASH_READ0];
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;  break;	/* => 8 MB	*/
+
+#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
+		info->flash_id += FLASH_SST320;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
+		info->flash_id += FLASH_SST640;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
+		    l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/esd/common/fpga.c b/u-boot/board/esd/common/fpga.c
new file mode 100644
index 0000000..62c3243
--- /dev/null
+++ b/u-boot/board/esd/common/fpga.c
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2001-2004
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES               226
+
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG              CONFIG_SYS_FPGA_PRG	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              CONFIG_SYS_FPGA_CLK	/* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CONFIG_SYS_FPGA_DATA	/* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CONFIG_SYS_FPGA_DONE	/* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CONFIG_SYS_FPGA_INIT	/* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000	/* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000	/* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000	/* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000	/* FPGA init pin (ppc input)     */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1	/* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2	/* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3	/* Timeout after programming     */
+
+#ifndef SET_FPGA
+# define SET_FPGA(data)         out_be32((void *)GPIO0_OR, data)
+#endif
+
+#ifdef FPGA_PROG_ACTIVE_HIGH
+# define FPGA_PRG_LOW           FPGA_PRG
+# define FPGA_PRG_HIGH          0
+#else
+# define FPGA_PRG_LOW           0
+# define FPGA_PRG_HIGH          FPGA_PRG
+#endif
+
+#define FPGA_CLK_LOW            0
+#define FPGA_CLK_HIGH           FPGA_CLK
+
+#define FPGA_DATA_LOW           0
+#define FPGA_DATA_HIGH          FPGA_DATA
+
+#define FPGA_WRITE_1 {                                                                   \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);}	/* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_LOW);   /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW);   /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);}	/* set data to 1  */
+
+#ifndef FPGA_DONE_STATE
+# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
+#endif
+#ifndef FPGA_INIT_STATE
+# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
+#endif
+
+
+static int fpga_boot (const unsigned char *fpgadata, int size)
+{
+	int i, index, len;
+	int count;
+	unsigned char b;
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	int j;
+#else
+	int bit;
+#endif
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	DBG ("FPGA: configdata starts at position 0x%x\n", index);
+	DBG ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+#ifndef CONFIG_M5249
+	out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+	/* setup for output */
+	out_be32 ((void *)GPIO0_TCR,
+		  in_be32 ((void *)GPIO0_TCR) |
+		  FPGA_PRG | FPGA_CLK | FPGA_DATA);
+#endif
+	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set pins to high */
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog active */
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (FPGA_INIT_STATE) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog inactive */
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(FPGA_INIT_STATE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	DBG ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			if ((b & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			b <<= 1;
+		}
+	}
+#else
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(FPGA_DONE_STATE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG ("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/u-boot/board/esd/common/lcd.c b/u-boot/board/esd/common/lcd.c
new file mode 100644
index 0000000..3dfbf3b
--- /dev/null
+++ b/u-boot/board/esd/common/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "asm/io.h"
+#include "lcd.h"
+
+
+extern int video_display_bitmap (ulong, int, int);
+
+
+int palette_index;
+int palette_value;
+int lcd_depth;
+unsigned char *glob_lcd_reg;
+unsigned char *glob_lcd_mem;
+
+#if defined(CONFIG_SYS_LCD_ENDIAN)
+void lcd_setup(int lcd, int config)
+{
+	if (lcd == 0) {
+		/*
+		 * Set endianess and reset lcd controller 0 (small)
+		 */
+
+		/* set reset to low */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			/* big-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+		} else {
+			/* little-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
+		}
+		udelay(10); /* wait 10us */
+		/* set reset to high */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
+	} else {
+		/*
+		 * Set endianess and reset lcd controller 1 (big)
+		 */
+
+		/* set reset to low */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			/* big-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+		} else {
+			/* little-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
+		}
+		udelay(10); /* wait 10us */
+		/* set reset to high */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
+	}
+
+	/*
+	 * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+}
+#endif /* CONFIG_SYS_LCD_ENDIAN */
+
+
+int lcd_bmp(uchar *logo_bmp)
+{
+	int i;
+	uchar *ptr;
+	ushort *ptr2;
+	ushort val;
+	unsigned char *dst = NULL;
+	int x, y;
+	int width, height, bpp, colors, line_size;
+	int header_size;
+	unsigned char *bmp;
+	unsigned char r, g, b;
+	BITMAPINFOHEADER *bm_info;
+	ulong len;
+
+	/*
+	 * Check for bmp mark 'BM'
+	 */
+	if (*(ushort *)logo_bmp != 0x424d) {
+		/*
+		 * Decompress bmp image
+		 */
+		len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+		dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
+		if (dst == NULL) {
+			printf("Error: malloc for gunzip failed!\n");
+			return 1;
+		}
+		if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+			   (uchar *)logo_bmp, &len) != 0) {
+			free(dst);
+			return 1;
+		}
+		if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
+			printf("Image could be truncated"
+			       " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
+		}
+
+		/*
+		 * Check for bmp mark 'BM'
+		 */
+		if (*(ushort *)dst != 0x424d) {
+			printf("LCD: Unknown image format!\n");
+			free(dst);
+			return 1;
+		}
+	} else {
+		/*
+		 * Uncompressed BMP image, just use this pointer
+		 */
+		dst = (uchar *)logo_bmp;
+	}
+
+	/*
+	 * Get image info from bmp-header
+	 */
+	bm_info = (BITMAPINFOHEADER *)(dst + 14);
+	bpp = LOAD_SHORT(bm_info->biBitCount);
+	width = LOAD_LONG(bm_info->biWidth);
+	height = LOAD_LONG(bm_info->biHeight);
+	switch (bpp) {
+	case 1:
+		colors = 1;
+		line_size = width >> 3;
+		break;
+	case 4:
+		colors = 16;
+		line_size = width >> 1;
+		break;
+	case 8:
+		colors = 256;
+		line_size = width;
+		break;
+	case 24:
+		colors = 0;
+		line_size = width * 3;
+		break;
+	default:
+		printf("LCD: Unknown bpp (%d) im image!\n", bpp);
+		if ((dst != NULL) && (dst != (uchar *)logo_bmp))
+			free(dst);
+		return 1;
+	}
+	printf(" (%d*%d, %dbpp)\n", width, height, bpp);
+
+	/*
+	 * Write color palette
+	 */
+	if ((colors <= 256) && (lcd_depth <= 8)) {
+		ptr = (unsigned char *)(dst + 14 + 40);
+		for (i = 0; i < colors; i++) {
+			b = *ptr++;
+			g = *ptr++;
+			r = *ptr++;
+			ptr++;
+			S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
+		}
+	}
+
+	/*
+	 * Write bitmap data into framebuffer
+	 */
+	ptr = glob_lcd_mem;
+	ptr2 = (ushort *)glob_lcd_mem;
+	header_size = 14 + 40 + 4*colors;          /* skip bmp header */
+	for (y = 0; y < height; y++) {
+		bmp = &dst[(height-1-y)*line_size + header_size];
+		if (lcd_depth == 16) {
+			if (bpp == 24) {
+				for (x = 0; x < width; x++) {
+					/*
+					 * Generate epson 16bpp fb-format
+					 * from 24bpp image
+					 */
+					b = *bmp++ >> 3;
+					g = *bmp++ >> 2;
+					r = *bmp++ >> 3;
+					val = ((r & 0x1f) << 11) |
+						((g & 0x3f) << 5) |
+						(b & 0x1f);
+					*ptr2++ = val;
+				}
+			} else if (bpp == 8) {
+				for (x = 0; x < line_size; x++) {
+					/* query rgb value from palette */
+					ptr = (unsigned char *)(dst + 14 + 40);
+					ptr += (*bmp++) << 2;
+					b = *ptr++ >> 3;
+					g = *ptr++ >> 2;
+					r = *ptr++ >> 3;
+					val = ((r & 0x1f) << 11) |
+						((g & 0x3f) << 5) |
+						(b & 0x1f);
+					*ptr2++ = val;
+				}
+			}
+		} else {
+			for (x = 0; x < line_size; x++)
+				*ptr++ = *bmp++;
+		}
+	}
+
+	if ((dst != NULL) && (dst != (uchar *)logo_bmp))
+		free(dst);
+	return 0;
+}
+
+
+int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+	     uchar *logo_bmp, ulong len)
+{
+	int i;
+	ushort s1dReg;
+	uchar s1dValue;
+	int reg_byte_swap;
+
+	/*
+	 * Detect epson
+	 */
+	out_8(&lcd_reg[0], 0x00);
+	out_8(&lcd_reg[1], 0x00);
+
+	if (in_8(&lcd_reg[0]) == 0x1c) {
+		/*
+		 * Big epson detected
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x1e2;
+		palette_value = 0x1e4;
+		lcd_depth = 16;
+		puts("LCD:   S1D13806");
+	} else if (in_8(&lcd_reg[1]) == 0x1c) {
+		/*
+		 * Big epson detected (with register swap bug)
+		 */
+		reg_byte_swap = TRUE;
+		palette_index = 0x1e3;
+		palette_value = 0x1e5;
+		lcd_depth = 16;
+		puts("LCD:   S1D13806S");
+	} else if (in_8(&lcd_reg[0]) == 0x18) {
+		/*
+		 * Small epson detected (704)
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_depth = 8;
+		puts("LCD:   S1D13704");
+	} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
+		/*
+		 * Small epson detected (705)
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_depth = 8;
+		lcd_reg += 0x10000; /* add offset for 705 regs */
+		puts("LCD:   S1D13705");
+	} else {
+		out_8(&lcd_reg[0x1a], 0x00);
+		udelay(1000);
+		if (in_8(&lcd_reg[1]) == 0x0c) {
+			/*
+			 * S1D13505 detected
+			 */
+			reg_byte_swap = TRUE;
+			palette_index = 0x25;
+			palette_value = 0x27;
+			lcd_depth = 16;
+
+			puts("LCD:   S1D13505");
+		} else {
+			puts("LCD:   No controller detected!\n");
+			return 1;
+		}
+	}
+
+	/*
+	 * Setup lcd controller regs
+	 */
+	for (i = 0; i < reg_count; i++) {
+		s1dReg = regs[i].Index;
+		if (reg_byte_swap) {
+			if ((s1dReg & 0x0001) == 0)
+				s1dReg |= 0x0001;
+			else
+				s1dReg &= ~0x0001;
+		}
+		s1dValue = regs[i].Value;
+		out_8(&lcd_reg[s1dReg], s1dValue);
+	}
+
+	/*
+	 * Save reg & mem pointer for later usage (e.g. bmp command)
+	 */
+	glob_lcd_reg = lcd_reg;
+	glob_lcd_mem = lcd_mem;
+
+	/*
+	 * Display bmp image
+	 */
+	return lcd_bmp(logo_bmp);
+}
+
+int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+#ifdef CONFIG_VIDEO_SM501
+	char *str;
+#endif
+	if (argc != 2)
+		return cmd_usage(cmdtp);
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+#ifdef CONFIG_VIDEO_SM501
+	str = getenv("bd_type");
+	if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
+		/*
+		 * SM501 available, use standard bmp command
+		 */
+		return video_display_bitmap(addr, 0, 0);
+	} else {
+		/*
+		 * No SM501 available, use esd epson bmp command
+		 */
+		return lcd_bmp((uchar *)addr);
+	}
+#else
+	return lcd_bmp((uchar *)addr);
+#endif
+}
+
+U_BOOT_CMD(
+	esdbmp,	2,	1,	do_esdbmp,
+	"display BMP image",
+	"<imageAddr> - display image"
+);
diff --git a/u-boot/board/esd/common/lcd.h b/u-boot/board/esd/common/lcd.h
new file mode 100644
index 0000000..01f6019
--- /dev/null
+++ b/u-boot/board/esd/common/lcd.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Neutralize little endians.
+ */
+#define SWAP_LONG(data) ((unsigned long)                                  \
+		         (((unsigned long)(data) >> 24)                 | \
+			  ((unsigned long)(data)  << 24)                | \
+			  (((unsigned long)(data) >> 8) & 0x0000ff00 )  | \
+			   (((unsigned long)(data) << 8) & 0x00ff0000 )))
+#define SWAP_SHORT(data) ((unsigned short)                                \
+			  (((unsigned short)(data) >> 8 )  |              \
+			   ((unsigned short)(data) << 8 )))
+#define LOAD_LONG(data)   SWAP_LONG(data)
+#define LOAD_SHORT(data)  SWAP_SHORT(data)
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b)					\
+	{								\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(i));	\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(r));	\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(g));	\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(b));	\
+	}
+
+typedef struct
+{
+    ushort Index;
+    uchar  Value;
+} S1D_REGS;
+
+typedef struct                       /**** BMP file info structure ****/
+{
+	unsigned int   biSize;           /* Size of info header */
+	int            biWidth;          /* Width of image */
+	int            biHeight;         /* Height of image */
+	unsigned short biPlanes;         /* Number of color planes */
+	unsigned short biBitCount;       /* Number of bits per pixel */
+	unsigned int   biCompression;    /* Type of compression to use */
+	unsigned int   biSizeImage;      /* Size of image data */
+	int            biXPelsPerMeter;  /* X pixels per meter */
+	int            biYPelsPerMeter;  /* Y pixels per meter */
+	unsigned int   biClrUsed;        /* Number of colors used */
+	unsigned int   biClrImportant;   /* Number of important colors */
+} BITMAPINFOHEADER;
diff --git a/u-boot/board/esd/common/misc.c b/u-boot/board/esd/common/misc.c
new file mode 100644
index 0000000..48b4b7c
--- /dev/null
+++ b/u-boot/board/esd/common/misc.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+#include <miiphy.h>
+#endif
+
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+void lxt971_no_sleep(void)
+{
+	unsigned short reg;
+
+	miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
+	reg &= ~0x0040;                  /* disable sleep mode */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
+}
+#endif /* CONFIG_LXT971_NO_SLEEP */
diff --git a/u-boot/board/esd/common/pci.c b/u-boot/board/esd/common/pci.c
new file mode 100644
index 0000000..11e55c5
--- /dev/null
+++ b/u-boot/board/esd/common/pci.c
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
+
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_read_config_dword
+|  Description: Read a PCI configuration register
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               value           Address of the configuration register value
+|  Return value:
+|               0               Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+  unsigned long      conAdrVal;
+  unsigned long      val;
+
+  /* generate coded value for CON_ADR register */
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  /* Note: *pResult comes back as -1 if machine check happened */
+  val = in32r(PCI_PRIMARY_CDR);
+
+  *value = (unsigned long) val;
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  if ((*(unsigned long *)0x50000304) & 0x60000000)
+    {
+      /* clear pci master/target abort bits */
+      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_write_config_dword
+|  Description: Write a PCI configuration register.
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               Value           Configuration register value
+|  Return value:
+|               0               Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 value)
+{
+  unsigned long      conAdrVal;
+
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  out32r(PCI_PRIMARY_CDR, value);
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  /* clear pci master/target abort bits */
+  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+					struct pci_config_table *_)
+{
+  unsigned int iobase;
+  unsigned short status = 0;
+  unsigned char timer;
+
+  /*
+   * Configure PLX PCI9054
+   */
+  pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+  pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+  /* Check the latency timer for values >= 0x60.
+   */
+  pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  if (timer < 0x60)
+    {
+      pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+    }
+
+  /* Set I/O base register.
+   */
+  pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+  pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+  pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  if (pci9054_iobase == 0xffffffff)
+    {
+      printf("Error: Can not set I/O base register.\n");
+      return;
+    }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+				 CONFIG_SYS_ETH_IOBASE,
+				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
+    pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+  { }
+};
+
+static struct pci_controller pci9054_hose = {
+  config_table: pci9054_config_table,
+};
+
+void pci_init_board(void)
+{
+  struct pci_controller *hose = &pci9054_hose;
+
+  /*
+   * Register the hose
+   */
+  hose->first_busno = 0;
+  hose->last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(hose->regions + 0,
+		 0x00000000, 0x00000000, 0x01000000,
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+  /* PCI Memory space */
+  pci_set_region(hose->regions + 1,
+		 0x00000000, 0xc0000000, 0x10000000,
+		 PCI_REGION_MEM);
+
+  pci_set_ops(hose,
+	      pci_hose_read_config_byte_via_dword,
+	      pci_hose_read_config_word_via_dword,
+	      pci9054_read_config_dword,
+	      pci_hose_write_config_byte_via_dword,
+	      pci_hose_write_config_word_via_dword,
+	      pci9054_write_config_dword);
+
+  hose->region_count = 2;
+
+  pci_register_hose(hose);
+
+  hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/u-boot/board/esd/common/s1d13505_640_480_16bpp.h b/u-boot/board/esd/common/s1d13505_640_480_16bpp.h
new file mode 100644
index 0000000..02b3b92
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13505_640_480_16bpp.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Panel:  640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
+ * Memory:  DRAM (MCLK=40.000 MHz)
+ */
+static S1D_REGS regs_13505_640_480_16bpp[] =
+{
+	{0x1B,0x00},   /* Miscellaneous Register */
+	{0x23,0x20},   /* Performance Enhancement Register 1 */
+	{0x01,0x30},   /* Memory Configuration Register */
+	{0x22,0x24},   /* Performance Enhancement Register 0 */
+	{0x02,0x25},   /* Panel Type Register */
+	{0x03,0x00},   /* MOD Rate Register */
+	{0x04,0x4F},   /* Horizontal Display Width Register */
+	{0x05,0x0c},   /* Horizontal Non-Display Period Register */
+	{0x06,0x00},   /* HRTC/FPLINE Start Position Register */
+	{0x07,0x01},   /* HRTC/FPLINE Pulse Width Register */
+	{0x08,0xDF},   /* Vertical Display Height Register 0 */
+	{0x09,0x01},   /* Vertical Display Height Register 1 */
+	{0x0A,0x3E},   /* Vertical Non-Display Period Register */
+	{0x0B,0x00},   /* VRTC/FPFRAME Start Position Register */
+	{0x0C,0x01},   /* VRTC/FPFRAME Pulse Width Register */
+	{0x0E,0xFF},   /* Screen 1 Line Compare Register 0 */
+	{0x0F,0x03},   /* Screen 1 Line Compare Register 1 */
+	{0x10,0x00},   /* Screen 1 Display Start Address Register 0 */
+	{0x11,0x00},   /* Screen 1 Display Start Address Register 1 */
+	{0x12,0x00},   /* Screen 1 Display Start Address Register 2 */
+	{0x13,0x00},   /* Screen 2 Display Start Address Register 0 */
+	{0x14,0x00},   /* Screen 2 Display Start Address Register 1 */
+	{0x15,0x00},   /* Screen 2 Display Start Address Register 2 */
+	{0x16,0x80},   /* Memory Address Offset Register 0 */
+	{0x17,0x02},   /* Memory Address Offset Register 1 */
+	{0x18,0x00},   /* Pixel Panning Register */
+	{0x19,0x01},   /* Clock Configuration Register */
+	{0x1A,0x00},   /* Power Save Configuration Register */
+	{0x1C,0x00},   /* MD Configuration Readback Register 0 */
+	{0x1E,0x06},   /* General IO Pins Configuration Register 0 */
+	{0x1F,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x20,0x00},   /* General IO Pins Control Register 0 */
+	{0x21,0x00},   /* General IO Pins Control Register 1 */
+	{0x23,0x20},   /* Performance Enhancement Register 1 */
+	{0x0D,0x15},   /* Display Mode Register */
+};
diff --git a/u-boot/board/esd/common/s1d13704_320_240_4bpp.h b/u-boot/board/esd/common/s1d13704_320_240_4bpp.h
new file mode 100644
index 0000000..57cf5f7
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13704_320_240_4bpp.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
+ */
+
+static S1D_REGS regs_13704_320_240_4bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x04 }, /*00*/      /* Mode Register 0 Register */
+	{ 0x02,             0xA4 }, /*a0*/      /* Mode Register 1 Register */
+	{ 0x03,             0x83 }, /*03*/      /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x00 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xA0 },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
diff --git a/u-boot/board/esd/common/s1d13705_320_240_8bpp.h b/u-boot/board/esd/common/s1d13705_320_240_8bpp.h
new file mode 100644
index 0000000..634889a
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13705_320_240_8bpp.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
+ */
+
+static S1D_REGS regs_13705_320_240_8bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x23 },       /* Mode Register 0 Register */
+	{ 0x02,             0xE0 },       /* Mode Register 1 Register */
+	{ 0x03,             0x03 },       /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x01 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xFF },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
diff --git a/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h b/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h
new file mode 100644
index 0000000..0b420b2
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_1024_768_8bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x00},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x00},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x01},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x55},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x7F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x12},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xFF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x02},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x00},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/u-boot/board/esd/common/s1d13806_320_240_4bpp.h b/u-boot/board/esd/common/s1d13806_320_240_4bpp.h
new file mode 100644
index 0000000..5aab2c1
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13806_320_240_4bpp.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_320_240_4bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x08},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x08},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x08},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x32},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x00},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x27},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x03},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xEF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x00},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x02},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x50},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x00},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/u-boot/board/esd/common/s1d13806_640_480_16bpp.h b/u-boot/board/esd/common/s1d13806_640_480_16bpp.h
new file mode 100644
index 0000000..f851278
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13806_640_480_16bpp.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_640_480_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x05},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/u-boot/board/esd/common/s1d13806_640_480_8bpp.h b/u-boot/board/esd/common/s1d13806_640_480_8bpp.h
new file mode 100644
index 0000000..17fa1d3
--- /dev/null
+++ b/u-boot/board/esd/common/s1d13806_640_480_8bpp.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_640_320_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register (8bpp) */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/u-boot/board/esd/common/xilinx_jtag/lenval.c b/u-boot/board/esd/common/xilinx_jtag/lenval.c
new file mode 100644
index 0000000..7316266
--- /dev/null
+++ b/u-boot/board/esd/common/xilinx_jtag/lenval.c
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: lenval.c                                      */
+/* abstract:  This file contains routines for using    */
+/*            the lenVal data structure.               */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "lenval.h"
+#include "ports.h"
+
+
+/*****************************************************************************
+ * Function:     value
+ * Description:  Extract the long value from the lenval array.
+ * Parameters:   plvValue    - ptr to lenval.
+ * Returns:      long        - the extracted value.
+ *****************************************************************************/
+long value( lenVal*     plvValue )
+{
+	long    lValue;         /* result to hold the accumulated result */
+	short   sIndex;
+
+	lValue  = 0;
+	for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
+	{
+		lValue <<= 8;                       /* shift the accumulated result */
+		lValue |= plvValue->val[ sIndex];   /* get the last byte first */
+	}
+
+	return( lValue );
+}
+
+/*****************************************************************************
+ * Function:     initLenVal
+ * Description:  Initialize the lenval array with the given value.
+ *               Assumes lValue is less than 256.
+ * Parameters:   plv         - ptr to lenval.
+ *               lValue      - the value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void initLenVal( lenVal*    plv,
+		 long       lValue )
+{
+	plv->len    = 1;
+	plv->val[0] = (unsigned char)lValue;
+}
+
+/*****************************************************************************
+ * Function:     EqualLenVal
+ * Description:  Compare two lenval arrays with an optional mask.
+ * Parameters:   plvTdoExpected  - ptr to lenval #1.
+ *               plvTdoCaptured  - ptr to lenval #2.
+ *               plvTdoMask      - optional ptr to mask (=0 if no mask).
+ * Returns:      short   - 0 = mismatch; 1 = equal.
+ *****************************************************************************/
+short EqualLenVal( lenVal*  plvTdoExpected,
+		   lenVal*  plvTdoCaptured,
+		   lenVal*  plvTdoMask )
+{
+	short           sEqual;
+	short           sIndex;
+	unsigned char   ucByteVal1;
+	unsigned char   ucByteVal2;
+	unsigned char   ucByteMask;
+
+	sEqual  = 1;
+	sIndex  = plvTdoExpected->len;
+
+	while ( sEqual && sIndex-- )
+	{
+		ucByteVal1  = plvTdoExpected->val[ sIndex ];
+		ucByteVal2  = plvTdoCaptured->val[ sIndex ];
+		if ( plvTdoMask )
+		{
+			ucByteMask  = plvTdoMask->val[ sIndex ];
+			ucByteVal1  &= ucByteMask;
+			ucByteVal2  &= ucByteMask;
+		}
+		if ( ucByteVal1 != ucByteVal2 )
+		{
+			sEqual  = 0;
+		}
+	}
+
+	return( sEqual );
+}
+
+
+/*****************************************************************************
+ * Function:     RetBit
+ * Description:  return the (byte, bit) of lv (reading from left to right).
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb)
+ * Returns:      short   - the bit value.
+ *****************************************************************************/
+short RetBit( lenVal*   plv,
+	      int       iByte,
+	      int       iBit )
+{
+	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
+	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
+	return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
+}
+
+/*****************************************************************************
+ * Function:     SetBit
+ * Description:  set the (byte, bit) of lv equal to val
+ * Example:      SetBit("00000000",byte, 1) equals "01000000".
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb).
+ *               sVal    - the bit value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void SetBit( lenVal*    plv,
+	     int        iByte,
+	     int        iBit,
+	     short      sVal )
+{
+	unsigned char   ucByteVal;
+	unsigned char   ucBitMask;
+
+	ucBitMask   = (unsigned char)(1 << ( 7 - iBit ));
+	ucByteVal   = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
+
+	if ( sVal )
+	{
+		ucByteVal   |= ucBitMask;
+	}
+	plv->val[ iByte ]   = ucByteVal;
+}
+
+/*****************************************************************************
+ * Function:     AddVal
+ * Description:  add val1 to val2 and store in resVal;
+ *               assumes val1 and val2  are of equal length.
+ * Parameters:   plvResVal   - ptr to result.
+ *               plvVal1     - ptr of addendum.
+ *               plvVal2     - ptr of addendum.
+ * Returns:      void.
+ *****************************************************************************/
+void addVal( lenVal*    plvResVal,
+	     lenVal*    plvVal1,
+	     lenVal*    plvVal2 )
+{
+	unsigned char   ucCarry;
+	unsigned short  usSum;
+	unsigned short  usVal1;
+	unsigned short  usVal2;
+	short           sIndex;
+
+	plvResVal->len  = plvVal1->len;         /* set up length of result */
+
+	/* start at least significant bit and add bytes    */
+	ucCarry = 0;
+	sIndex  = plvVal1->len;
+	while ( sIndex-- )
+	{
+		usVal1  = plvVal1->val[ sIndex ];   /* i'th byte of val1 */
+		usVal2  = plvVal2->val[ sIndex ];   /* i'th byte of val2 */
+
+		/* add the two bytes plus carry from previous addition */
+		usSum   = (unsigned short)( usVal1 + usVal2 + ucCarry );
+
+		/* set up carry for next byte */
+		ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
+
+		/* set the i'th byte of the result */
+		plvResVal->val[ sIndex ]    = (unsigned char)usSum;
+	}
+}
+
+/*****************************************************************************
+ * Function:     readVal
+ * Description:  read from XSVF numBytes bytes of data into x.
+ * Parameters:   plv         - ptr to lenval in which to put the bytes read.
+ *               sNumBytes   - the number of bytes to read.
+ * Returns:      void.
+ *****************************************************************************/
+void readVal( lenVal*   plv,
+	      short     sNumBytes )
+{
+	unsigned char*  pucVal;
+
+	plv->len    = sNumBytes;        /* set the length of the lenVal        */
+	for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
+	{
+		/* read a byte of data into the lenVal */
+		readByte( pucVal );
+	}
+}
diff --git a/u-boot/board/esd/common/xilinx_jtag/lenval.h b/u-boot/board/esd/common/xilinx_jtag/lenval.h
new file mode 100644
index 0000000..6bec4ea
--- /dev/null
+++ b/u-boot/board/esd/common/xilinx_jtag/lenval.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: lenval.h                                      */
+/* abstract:  This file contains a description of the  */
+/*            data structure "lenval".                 */
+/*******************************************************/
+
+#ifndef lenval_dot_h
+#define lenval_dot_h
+
+/* the lenVal structure is a byte oriented type used to store an */
+/* arbitrary length binary value. As an example, the hex value   */
+/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes   */
+/* and val[0]=0e and val[1]=3d.  val[2-MAX_LEN] are undefined    */
+
+/* maximum length (in bytes) of value to read in        */
+/* this needs to be at least 4, and longer than the     */
+/* length of the longest SDR instruction.  If there is, */
+/* only 1 device in the chain, MAX_LEN must be at least */
+/* ceil(27/8) == 4.  For 6 devices in a chain, MAX_LEN  */
+/* must be 5, for 14 devices MAX_LEN must be 6, for 20  */
+/* devices MAX_LEN must be 7, etc..                     */
+/* You can safely set MAX_LEN to a smaller number if you*/
+/* know how many devices will be in your chain.         */
+#define MAX_LEN 7000
+
+
+typedef struct var_len_byte
+{
+	short len;   /* number of chars in this value */
+	unsigned char val[MAX_LEN+1];  /* bytes of data */
+} lenVal;
+
+
+/* return the long representation of a lenVal */
+extern long value(lenVal *x);
+
+/* set lenVal equal to value */
+extern void initLenVal(lenVal *x, long value);
+
+/* check if expected equals actual (taking the mask into account) */
+extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
+
+/* add val1+val2 and put the result in resVal */
+extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
+
+/* return the (byte, bit) of lv (reading from left to right) */
+extern short RetBit(lenVal *lv, int byte, int bit);
+
+/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
+   equals "01000000" */
+extern void SetBit(lenVal *lv, int byte, int bit, short val);
+
+/* read from XSVF numBytes bytes of data into x */
+extern void  readVal(lenVal *x, short numBytes);
+
+#endif
diff --git a/u-boot/board/esd/common/xilinx_jtag/micro.c b/u-boot/board/esd/common/xilinx_jtag/micro.c
new file mode 100644
index 0000000..9823e5e
--- /dev/null
+++ b/u-boot/board/esd/common/xilinx_jtag/micro.c
@@ -0,0 +1,1872 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * file:         micro.c
+ * abstract:     This file contains the function, xsvfExecute(),
+ *               call for interpreting the XSVF commands.
+ * Usage:        Call xsvfExecute() to process XSVF data.
+ *               The XSVF data is retrieved by readByte() in ports.c
+ *               Remove the main function if you already have one.
+ * Options:      XSVF_SUPPORT_COMPRESSION
+ *                   This define supports the XC9500/XL compression scheme.
+ *                   This define adds support for XSDRINC and XSETSDRMASKS.
+ *               XSVF_SUPPORT_ERRORCODES
+ *                   This define causes the xsvfExecute function to return
+ *                   an error code for specific errors.  See error codes below.
+ *                   If this is not defined, the return value defaults to the
+ *                   legacy values for backward compatibility:
+ *                   1 = success;  0 = failure.
+ * Debugging:    DEBUG_MODE (Legacy name)
+ *               Define DEBUG_MODE to compile with debugging features.
+ *               Both micro.c and ports.c must be compiled with the DEBUG_MODE
+ *               defined to enable the standalone main implementation in
+ *               micro.c that reads XSVF from a file.
+ * History:      v2.00   - Original XSVF implementation.
+ *               v4.04   - Added delay at end of XSIR for XC18v00 support.
+ *                         Added new commands for CoolRunner support:
+ *                         XSTATE, XENDIR, XENDDR
+ *               v4.05   - Cleanup micro.c but leave ports.c intact.
+ *               v4.06   - Fix xsvfGotoTapState for retry transition.
+ *               v4.07   - Update example waitTime implementations for
+ *                         compatibility with Virtex-II.
+ *               v4.10   - Add new XSIR2 command that supports a 2-byte
+ *                         IR-length parameter for IR shifts > 255 bits.
+ *               v4.11   - No change.  Update version to match SVF2XSVF xlator.
+ *               v4.14   - Added XCOMMENT.
+ *               v5.00   - Improve XSTATE support.
+ *                         Added XWAIT.
+ *****************************************************************************/
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#include "micro.h"
+#include "lenval.h"
+#include "ports.h"
+
+const unsigned char *xsvfdata;
+
+/*============================================================================
+ * XSVF #define
+ ============================================================================*/
+
+#define XSVF_VERSION    "5.00"
+
+/*****************************************************************************
+ * Define:       XSVF_SUPPORT_COMPRESSION
+ * Description:  Define this to support the XC9500/XL XSVF data compression
+ *               scheme.
+ *               Code size can be reduced by NOT supporting this feature.
+ *               However, you must use the -nc (no compress) option when
+ *               translating SVF to XSVF using the SVF2XSVF translator.
+ *               Corresponding, uncompressed XSVF may be larger.
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_COMPRESSION
+#define XSVF_SUPPORT_COMPRESSION    1
+#endif
+
+/*****************************************************************************
+ * Define:       XSVF_SUPPORT_ERRORCODES
+ * Description:  Define this to support the new XSVF error codes.
+ *               (The original XSVF player just returned 1 for success and
+ *               0 for an unspecified failure.)
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_ERRORCODES
+#define XSVF_SUPPORT_ERRORCODES     1
+#endif
+
+#ifdef  XSVF_SUPPORT_ERRORCODES
+#define XSVF_ERRORCODE(errorCode)   errorCode
+#else   /* Use legacy error code */
+#define XSVF_ERRORCODE(errorCode)   ((errorCode==XSVF_ERROR_NONE)?1:0)
+#endif  /* XSVF_SUPPORT_ERRORCODES */
+
+
+/*============================================================================
+ * DEBUG_MODE #define
+ ============================================================================*/
+#define DEBUG_MODE
+
+#ifdef  DEBUG_MODE
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat ); }
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1 ); }
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2 ); }
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2, arg3 ); }
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    xsvfPrintLenVal(plenVal); }
+#else   /* !DEBUG_MODE */
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2)
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3)
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal)
+#endif  /* DEBUG_MODE */
+
+
+/*============================================================================
+ * XSVF Type Declarations
+ ============================================================================*/
+
+/*****************************************************************************
+ * Struct:       SXsvfInfo
+ * Description:  This structure contains all of the data used during the
+ *               execution of the XSVF.  Some data is persistent, predefined
+ *               information (e.g. lRunTestTime).  The bulk of this struct's
+ *               size is due to the lenVal structs (defined in lenval.h)
+ *               which contain buffers for the active shift data.  The MAX_LEN
+ *               #define in lenval.h defines the size of these buffers.
+ *               These buffers must be large enough to store the longest
+ *               shift data in your XSVF file.  For example:
+ *                   MAX_LEN >= ( longest_shift_data_in_bits / 8 )
+ *               Because the lenVal struct dominates the space usage of this
+ *               struct, the rough size of this struct is:
+ *                   sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals)
+ *               xsvfInitialize() contains initialization code for the data
+ *               in this struct.
+ *               xsvfCleanup() contains cleanup code for the data in this
+ *               struct.
+ *****************************************************************************/
+typedef struct tagSXsvfInfo
+{
+	/* XSVF status information */
+	unsigned char   ucComplete;         /* 0 = running; 1 = complete */
+	unsigned char   ucCommand;          /* Current XSVF command byte */
+	long            lCommandCount;      /* Number of commands processed */
+	int             iErrorCode;         /* An error code. 0 = no error. */
+
+	/* TAP state/sequencing information */
+	unsigned char   ucTapState;         /* Current TAP state */
+	unsigned char   ucEndIR;            /* ENDIR TAP state (See SVF) */
+	unsigned char   ucEndDR;            /* ENDDR TAP state (See SVF) */
+
+	/* RUNTEST information */
+	unsigned char   ucMaxRepeat;        /* Max repeat loops (for xc9500/xl) */
+	long            lRunTestTime;       /* Pre-specified RUNTEST time (usec) */
+
+	/* Shift Data Info and Buffers */
+	long            lShiftLengthBits;   /* Len. current shift data in bits */
+	short           sShiftLengthBytes;  /* Len. current shift data in bytes */
+
+	lenVal          lvTdi;              /* Current TDI shift data */
+	lenVal          lvTdoExpected;      /* Expected TDO shift data */
+	lenVal          lvTdoCaptured;      /* Captured TDO shift data */
+	lenVal          lvTdoMask;          /* TDO mask: 0=dontcare; 1=compare */
+
+#ifdef  XSVF_SUPPORT_COMPRESSION
+	/* XSDRINC Data Buffers */
+	lenVal          lvAddressMask;      /* Address mask for XSDRINC */
+	lenVal          lvDataMask;         /* Data mask for XSDRINC */
+	lenVal          lvNextData;         /* Next data for XSDRINC */
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+} SXsvfInfo;
+
+/* Declare pointer to functions that perform XSVF commands */
+typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* );
+
+/*============================================================================
+ * XSVF Command Bytes
+ ============================================================================*/
+
+/* encodings of xsvf instructions */
+#define XCOMPLETE        0
+#define XTDOMASK         1
+#define XSIR             2
+#define XSDR             3
+#define XRUNTEST         4
+/* Reserved              5 */
+/* Reserved              6 */
+#define XREPEAT          7
+#define XSDRSIZE         8
+#define XSDRTDO          9
+#define XSETSDRMASKS     10
+#define XSDRINC          11
+#define XSDRB            12
+#define XSDRC            13
+#define XSDRE            14
+#define XSDRTDOB         15
+#define XSDRTDOC         16
+#define XSDRTDOE         17
+#define XSTATE           18         /* 4.00 */
+#define XENDIR           19         /* 4.04 */
+#define XENDDR           20         /* 4.04 */
+#define XSIR2            21         /* 4.10 */
+#define XCOMMENT         22         /* 4.14 */
+#define XWAIT            23         /* 5.00 */
+/* Insert new commands here */
+/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */
+#define XLASTCMD         24         /* Last command marker */
+
+
+/*============================================================================
+ * XSVF Command Parameter Values
+ ============================================================================*/
+
+#define XSTATE_RESET     0          /* 4.00 parameter for XSTATE */
+#define XSTATE_RUNTEST   1          /* 4.00 parameter for XSTATE */
+
+#define XENDXR_RUNTEST   0          /* 4.04 parameter for XENDIR/DR */
+#define XENDXR_PAUSE     1          /* 4.04 parameter for XENDIR/DR */
+
+/* TAP states */
+#define XTAPSTATE_RESET     0x00
+#define XTAPSTATE_RUNTEST   0x01    /* a.k.a. IDLE */
+#define XTAPSTATE_SELECTDR  0x02
+#define XTAPSTATE_CAPTUREDR 0x03
+#define XTAPSTATE_SHIFTDR   0x04
+#define XTAPSTATE_EXIT1DR   0x05
+#define XTAPSTATE_PAUSEDR   0x06
+#define XTAPSTATE_EXIT2DR   0x07
+#define XTAPSTATE_UPDATEDR  0x08
+#define XTAPSTATE_IRSTATES  0x09    /* All IR states begin here */
+#define XTAPSTATE_SELECTIR  0x09
+#define XTAPSTATE_CAPTUREIR 0x0A
+#define XTAPSTATE_SHIFTIR   0x0B
+#define XTAPSTATE_EXIT1IR   0x0C
+#define XTAPSTATE_PAUSEIR   0x0D
+#define XTAPSTATE_EXIT2IR   0x0E
+#define XTAPSTATE_UPDATEIR  0x0F
+
+/*============================================================================
+ * XSVF Function Prototypes
+ ============================================================================*/
+
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo );   /* Illegal command function */
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo );
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo );
+/* Insert new command functions here */
+
+/*============================================================================
+ * XSVF Global Variables
+ ============================================================================*/
+
+/* Array of XSVF command functions.  Must follow command byte value order! */
+/* If your compiler cannot take this form, then convert to a switch statement*/
+TXsvfDoCmdFuncPtr   xsvf_pfDoCmd[]  =
+{
+	xsvfDoXCOMPLETE,        /*  0 */
+	xsvfDoXTDOMASK,         /*  1 */
+	xsvfDoXSIR,             /*  2 */
+	xsvfDoXSDR,             /*  3 */
+	xsvfDoXRUNTEST,         /*  4 */
+	xsvfDoIllegalCmd,       /*  5 */
+	xsvfDoIllegalCmd,       /*  6 */
+	xsvfDoXREPEAT,          /*  7 */
+	xsvfDoXSDRSIZE,         /*  8 */
+	xsvfDoXSDRTDO,          /*  9 */
+#ifdef  XSVF_SUPPORT_COMPRESSION
+	xsvfDoXSETSDRMASKS,     /* 10 */
+	xsvfDoXSDRINC,          /* 11 */
+#else
+	xsvfDoIllegalCmd,       /* 10 */
+	xsvfDoIllegalCmd,       /* 11 */
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+	xsvfDoXSDRBCE,          /* 12 */
+	xsvfDoXSDRBCE,          /* 13 */
+	xsvfDoXSDRBCE,          /* 14 */
+	xsvfDoXSDRTDOBCE,       /* 15 */
+	xsvfDoXSDRTDOBCE,       /* 16 */
+	xsvfDoXSDRTDOBCE,       /* 17 */
+	xsvfDoXSTATE,           /* 18 */
+	xsvfDoXENDXR,           /* 19 */
+	xsvfDoXENDXR,           /* 20 */
+	xsvfDoXSIR2,            /* 21 */
+	xsvfDoXCOMMENT,         /* 22 */
+	xsvfDoXWAIT             /* 23 */
+/* Insert new command functions here */
+};
+
+#ifdef  DEBUG_MODE
+char* xsvf_pzCommandName[]  =
+{
+	"XCOMPLETE",
+	"XTDOMASK",
+	"XSIR",
+	"XSDR",
+	"XRUNTEST",
+	"Reserved5",
+	"Reserved6",
+	"XREPEAT",
+	"XSDRSIZE",
+	"XSDRTDO",
+	"XSETSDRMASKS",
+	"XSDRINC",
+	"XSDRB",
+	"XSDRC",
+	"XSDRE",
+	"XSDRTDOB",
+	"XSDRTDOC",
+	"XSDRTDOE",
+	"XSTATE",
+	"XENDIR",
+	"XENDDR",
+	"XSIR2",
+	"XCOMMENT",
+	"XWAIT"
+};
+
+char*   xsvf_pzErrorName[]  =
+{
+	"No error",
+	"ERROR:  Unknown",
+	"ERROR:  TDO mismatch",
+	"ERROR:  TDO mismatch and exceeded max retries",
+	"ERROR:  Unsupported XSVF command",
+	"ERROR:  Illegal state specification",
+	"ERROR:  Data overflows allocated MAX_LEN buffer size"
+};
+
+char*   xsvf_pzTapState[] =
+{
+	"RESET",        /* 0x00 */
+	"RUNTEST/IDLE", /* 0x01 */
+	"DRSELECT",     /* 0x02 */
+	"DRCAPTURE",    /* 0x03 */
+	"DRSHIFT",      /* 0x04 */
+	"DREXIT1",      /* 0x05 */
+	"DRPAUSE",      /* 0x06 */
+	"DREXIT2",      /* 0x07 */
+	"DRUPDATE",     /* 0x08 */
+	"IRSELECT",     /* 0x09 */
+	"IRCAPTURE",    /* 0x0A */
+	"IRSHIFT",      /* 0x0B */
+	"IREXIT1",      /* 0x0C */
+	"IRPAUSE",      /* 0x0D */
+	"IREXIT2",      /* 0x0E */
+	"IRUPDATE"      /* 0x0F */
+};
+#endif  /* DEBUG_MODE */
+
+/*#ifdef DEBUG_MODE	*/
+/*    FILE* in;   /XXX* Legacy DEBUG_MODE file pointer */
+int xsvf_iDebugLevel;
+/*#endif /XXX* DEBUG_MODE */
+
+/*============================================================================
+ * Utility Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfPrintLenVal
+ * Description:  Print the lenval value in hex.
+ * Parameters:   plv     - ptr to lenval.
+ * Returns:      void.
+ *****************************************************************************/
+#ifdef  DEBUG_MODE
+void xsvfPrintLenVal( lenVal *plv )
+{
+	int i;
+
+	if ( plv )
+	{
+		printf( "0x" );
+		for ( i = 0; i < plv->len; ++i )
+		{
+			printf( "%02x", ((unsigned int)(plv->val[ i ])) );
+		}
+	}
+}
+#endif  /* DEBUG_MODE */
+
+
+/*****************************************************************************
+ * Function:     xsvfInfoInit
+ * Description:  Initialize the xsvfInfo data.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
+ * Returns:      int         - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInfoInit( SXsvfInfo* pXsvfInfo )
+{
+	XSVFDBG_PRINTF1( 4, "    sizeof( SXsvfInfo ) = %d bytes\n",
+			 sizeof( SXsvfInfo ) );
+
+	pXsvfInfo->ucComplete       = 0;
+	pXsvfInfo->ucCommand        = XCOMPLETE;
+	pXsvfInfo->lCommandCount    = 0;
+	pXsvfInfo->iErrorCode       = XSVF_ERROR_NONE;
+	pXsvfInfo->ucMaxRepeat      = 0;
+	pXsvfInfo->ucTapState       = XTAPSTATE_RESET;
+	pXsvfInfo->ucEndIR          = XTAPSTATE_RUNTEST;
+	pXsvfInfo->ucEndDR          = XTAPSTATE_RUNTEST;
+	pXsvfInfo->lShiftLengthBits = 0L;
+	pXsvfInfo->sShiftLengthBytes= 0;
+	pXsvfInfo->lRunTestTime     = 0L;
+
+	return( 0 );
+}
+
+/*****************************************************************************
+ * Function:     xsvfInfoCleanup
+ * Description:  Cleanup the xsvfInfo data.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo )
+{
+}
+
+/*****************************************************************************
+ * Function:     xsvfGetAsNumBytes
+ * Description:  Calculate the number of bytes the given number of bits
+ *               consumes.
+ * Parameters:   lNumBits    - the number of bits.
+ * Returns:      short       - the number of bytes to store the number of bits.
+ *****************************************************************************/
+short xsvfGetAsNumBytes( long lNumBits )
+{
+	return( (short)( ( lNumBits + 7L ) / 8L ) );
+}
+
+/*****************************************************************************
+ * Function:     xsvfTmsTransition
+ * Description:  Apply TMS and transition TAP controller by applying one TCK
+ *               cycle.
+ * Parameters:   sTms    - new TMS value.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfTmsTransition( short sTms )
+{
+	setPort( TMS, sTms );
+	setPort( TCK, 0 );
+	setPort( TCK, 1 );
+}
+
+/*****************************************************************************
+ * Function:     xsvfGotoTapState
+ * Description:  From the current TAP state, go to the named TAP state.
+ *               A target state of RESET ALWAYS causes TMS reset sequence.
+ *               All SVF standard stable state paths are supported.
+ *               All state transitions are supported except for the following
+ *               which cause an XSVF_ERROR_ILLEGALSTATE:
+ *                   - Target==DREXIT2;  Start!=DRPAUSE
+ *                   - Target==IREXIT2;  Start!=IRPAUSE
+ * Parameters:   pucTapState     - Current TAP state; returns final TAP state.
+ *               ucTargetState   - New target TAP state.
+ * Returns:      int             - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfGotoTapState( unsigned char*   pucTapState,
+		      unsigned char    ucTargetState )
+{
+	int i;
+	int iErrorCode;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	if ( ucTargetState == XTAPSTATE_RESET )
+	{
+		/* If RESET, always perform TMS reset sequence to reset/sync TAPs */
+		xsvfTmsTransition( 1 );
+		for ( i = 0; i < 5; ++i )
+		{
+			setPort( TCK, 0 );
+			setPort( TCK, 1 );
+		}
+		*pucTapState    = XTAPSTATE_RESET;
+		XSVFDBG_PRINTF( 3, "   TMS Reset Sequence -> Test-Logic-Reset\n" );
+		XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+				 xsvf_pzTapState[ *pucTapState ] );
+	} else if ( ( ucTargetState != *pucTapState ) &&
+		  ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) ||
+		    ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) )
+	{
+		/* Trap illegal TAP state path specification */
+		iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
+	} else {
+		if ( ucTargetState == *pucTapState )
+		{
+			/* Already in target state.  Do nothing except when in DRPAUSE
+			   or in IRPAUSE to comply with SVF standard */
+			if ( ucTargetState == XTAPSTATE_PAUSEDR )
+			{
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2DR;
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+			}
+			else if ( ucTargetState == XTAPSTATE_PAUSEIR )
+			{
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2IR;
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+			}
+		}
+
+		/* Perform TAP state transitions to get to the target state */
+		while ( ucTargetState != *pucTapState )
+		{
+			switch ( *pucTapState )
+			{
+			case XTAPSTATE_RESET:
+				xsvfTmsTransition( 0 );
+				*pucTapState    = XTAPSTATE_RUNTEST;
+				break;
+			case XTAPSTATE_RUNTEST:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_SELECTDR;
+				break;
+			case XTAPSTATE_SELECTDR:
+				if ( ucTargetState >= XTAPSTATE_IRSTATES )
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_CAPTUREDR;
+				}
+				break;
+			case XTAPSTATE_CAPTUREDR:
+				if ( ucTargetState == XTAPSTATE_SHIFTDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_EXIT1DR;
+				}
+				break;
+			case XTAPSTATE_SHIFTDR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT1DR;
+				break;
+			case XTAPSTATE_EXIT1DR:
+				if ( ucTargetState == XTAPSTATE_PAUSEDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_PAUSEDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEDR;
+				}
+				break;
+			case XTAPSTATE_PAUSEDR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2DR;
+				break;
+			case XTAPSTATE_EXIT2DR:
+				if ( ucTargetState == XTAPSTATE_SHIFTDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEDR;
+				}
+				break;
+			case XTAPSTATE_UPDATEDR:
+				if ( ucTargetState == XTAPSTATE_RUNTEST )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_RUNTEST;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTDR;
+				}
+				break;
+			case XTAPSTATE_SELECTIR:
+				xsvfTmsTransition( 0 );
+				*pucTapState    = XTAPSTATE_CAPTUREIR;
+				break;
+			case XTAPSTATE_CAPTUREIR:
+				if ( ucTargetState == XTAPSTATE_SHIFTIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_EXIT1IR;
+				}
+				break;
+			case XTAPSTATE_SHIFTIR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT1IR;
+				break;
+			case XTAPSTATE_EXIT1IR:
+				if ( ucTargetState == XTAPSTATE_PAUSEIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_PAUSEIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEIR;
+				}
+				break;
+			case XTAPSTATE_PAUSEIR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2IR;
+				break;
+			case XTAPSTATE_EXIT2IR:
+				if ( ucTargetState == XTAPSTATE_SHIFTIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEIR;
+				}
+				break;
+			case XTAPSTATE_UPDATEIR:
+				if ( ucTargetState == XTAPSTATE_RUNTEST )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_RUNTEST;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTDR;
+				}
+				break;
+			default:
+				iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
+				*pucTapState    = ucTargetState;    /* Exit while loop */
+				break;
+			}
+			XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+					 xsvf_pzTapState[ *pucTapState ] );
+		}
+	}
+
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfShiftOnly
+ * Description:  Assumes that starting TAP state is SHIFT-DR or SHIFT-IR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Optionally, save the TDO data shifted out of the scan chain.
+ *               Last shift cycle is special:  capture last TDO, set last TDI,
+ *               but does not pulse TCK.  Caller must pulse TCK and optionally
+ *               set TMS=1 to exit shift state.
+ * Parameters:   lNumBits        - number of bits to shift.
+ *               plvTdi          - ptr to lenval for TDI data.
+ *               plvTdoCaptured  - ptr to lenval for storing captured TDO data.
+ *               iExitShift      - 1=exit at end of shift; 0=stay in Shift-DR.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfShiftOnly( long    lNumBits,
+		    lenVal* plvTdi,
+		    lenVal* plvTdoCaptured,
+		    int     iExitShift )
+{
+	unsigned char*  pucTdi;
+	unsigned char*  pucTdo;
+	unsigned char   ucTdiByte;
+	unsigned char   ucTdoByte;
+	unsigned char   ucTdoBit;
+	int             i;
+
+	/* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */
+
+	/* Initialize TDO storage len == TDI len */
+	pucTdo  = 0;
+	if ( plvTdoCaptured )
+	{
+		plvTdoCaptured->len = plvTdi->len;
+		pucTdo              = plvTdoCaptured->val + plvTdi->len;
+	}
+
+	/* Shift LSB first.  val[N-1] == LSB.  val[0] == MSB. */
+	pucTdi  = plvTdi->val + plvTdi->len;
+	while ( lNumBits )
+	{
+		/* Process on a byte-basis */
+		ucTdiByte   = (*(--pucTdi));
+		ucTdoByte   = 0;
+		for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i )
+		{
+			--lNumBits;
+			if ( iExitShift && !lNumBits )
+			{
+				/* Exit Shift-DR state */
+				setPort( TMS, 1 );
+			}
+
+			/* Set the new TDI value */
+			setPort( TDI, (short)(ucTdiByte & 1) );
+			ucTdiByte   >>= 1;
+
+			/* Set TCK low */
+			setPort( TCK, 0 );
+
+			if ( pucTdo )
+			{
+				/* Save the TDO value */
+				ucTdoBit    = readTDOBit();
+				ucTdoByte   |= ( ucTdoBit << i );
+			}
+
+			/* Set TCK high */
+			setPort( TCK, 1 );
+		}
+
+		/* Save the TDO byte value */
+		if ( pucTdo )
+		{
+			(*(--pucTdo))   = ucTdoByte;
+		}
+	}
+}
+
+/*****************************************************************************
+ * Function:     xsvfShift
+ * Description:  Goes to the given starting TAP state.
+ *               Calls xsvfShiftOnly to shift in the given TDI data and
+ *               optionally capture the TDO data.
+ *               Compares the TDO captured data against the TDO expected
+ *               data.
+ *               If a data mismatch occurs, then executes the exception
+ *               handling loop upto ucMaxRepeat times.
+ * Parameters:   pucTapState     - Ptr to current TAP state.
+ *               ucStartState    - Starting shift state: Shift-DR or Shift-IR.
+ *               lNumBits        - number of bits to shift.
+ *               plvTdi          - ptr to lenval for TDI data.
+ *               plvTdoCaptured  - ptr to lenval for storing TDO data.
+ *               plvTdoExpected  - ptr to expected TDO data.
+ *               plvTdoMask      - ptr to TDO mask.
+ *               ucEndState      - state in which to end the shift.
+ *               lRunTestTime    - amount of time to wait after the shift.
+ *               ucMaxRepeat     - Maximum number of retries on TDO mismatch.
+ * Returns:      int             - 0 = success; otherwise TDO mismatch.
+ * Notes:        XC9500XL-only Optimization:
+ *               Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1]
+ *               is NOT all zeros and sMatch==1.
+ *****************************************************************************/
+int xsvfShift( unsigned char*   pucTapState,
+	       unsigned char    ucStartState,
+	       long             lNumBits,
+	       lenVal*          plvTdi,
+	       lenVal*          plvTdoCaptured,
+	       lenVal*          plvTdoExpected,
+	       lenVal*          plvTdoMask,
+	       unsigned char    ucEndState,
+	       long             lRunTestTime,
+	       unsigned char    ucMaxRepeat )
+{
+	int             iErrorCode;
+	int             iMismatch;
+	unsigned char   ucRepeat;
+	int             iExitShift;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	iMismatch   = 0;
+	ucRepeat    = 0;
+	iExitShift  = ( ucStartState != ucEndState );
+
+	XSVFDBG_PRINTF1( 3, "   Shift Length = %ld\n", lNumBits );
+	XSVFDBG_PRINTF( 4, "    TDI          = ");
+	XSVFDBG_PRINTLENVAL( 4, plvTdi );
+	XSVFDBG_PRINTF( 4, "\n");
+	XSVFDBG_PRINTF( 4, "    TDO Expected = ");
+	XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+	XSVFDBG_PRINTF( 4, "\n");
+
+	if ( !lNumBits )
+	{
+		/* Compatibility with XSVF2.00:  XSDR 0 = no shift, but wait in RTI */
+		if ( lRunTestTime )
+		{
+			/* Wait for prespecified XRUNTEST time */
+			xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+			XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
+			waitTime( lRunTestTime );
+		}
+	}
+	else
+	{
+		do
+		{
+			/* Goto Shift-DR or Shift-IR */
+			xsvfGotoTapState( pucTapState, ucStartState );
+
+			/* Shift TDI and capture TDO */
+			xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift );
+
+			if ( plvTdoExpected )
+			{
+				/* Compare TDO data to expected TDO data */
+				iMismatch   = !EqualLenVal( plvTdoExpected,
+							    plvTdoCaptured,
+							    plvTdoMask );
+			}
+
+			if ( iExitShift )
+			{
+				/* Update TAP state:  Shift->Exit */
+				++(*pucTapState);
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+
+				if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) )
+				{
+					XSVFDBG_PRINTF( 4, "    TDO Expected = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF( 4, "    TDO Captured = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoMask );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF1( 3, "   Retry #%d\n", ( ucRepeat + 1 ) );
+					/* Do exception handling retry - ShiftDR only */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR );
+					/* Shift 1 extra bit */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR );
+					/* Increment RUNTEST time by an additional 25% */
+					lRunTestTime    += ( lRunTestTime >> 2 );
+				}
+				else
+				{
+					/* Do normal exit from Shift-XR */
+					xsvfGotoTapState( pucTapState, ucEndState );
+				}
+
+				if ( lRunTestTime )
+				{
+					/* Wait for prespecified XRUNTEST time */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+					XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
+					waitTime( lRunTestTime );
+				}
+			}
+		} while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) );
+	}
+
+	if ( iMismatch )
+	{
+		XSVFDBG_PRINTF( 1, " TDO Expected = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoExpected );
+		XSVFDBG_PRINTF( 1, "\n");
+		XSVFDBG_PRINTF( 1, " TDO Captured = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured );
+		XSVFDBG_PRINTF( 1, "\n");
+		XSVFDBG_PRINTF( 1, " TDO Mask     = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoMask );
+		XSVFDBG_PRINTF( 1, "\n");
+		if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) )
+		{
+			iErrorCode  = XSVF_ERROR_MAXRETRIES;
+		}
+		else
+		{
+			iErrorCode  = XSVF_ERROR_TDOMISMATCH;
+		}
+	}
+
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfBasicXSDRTDO
+ * Description:  Get the XSDRTDO parameters and execute the XSDRTDO command.
+ *               This is the common function for all XSDRTDO commands.
+ * Parameters:   pucTapState         - Current TAP state.
+ *               lShiftLengthBits    - number of bits to shift.
+ *               sShiftLengthBytes   - number of bytes to read.
+ *               plvTdi              - ptr to lenval for TDI data.
+ *               lvTdoCaptured       - ptr to lenval for storing TDO data.
+ *               iEndState           - state in which to end the shift.
+ *               lRunTestTime        - amount of time to wait after the shift.
+ *               ucMaxRepeat         - maximum xc9500/xl retries.
+ * Returns:      int                 - 0 = success; otherwise TDO mismatch.
+ *****************************************************************************/
+int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
+		      long              lShiftLengthBits,
+		      short             sShiftLengthBytes,
+		      lenVal*           plvTdi,
+		      lenVal*           plvTdoCaptured,
+		      lenVal*           plvTdoExpected,
+		      lenVal*           plvTdoMask,
+		      unsigned char     ucEndState,
+		      long              lRunTestTime,
+		      unsigned char     ucMaxRepeat )
+{
+	readVal( plvTdi, sShiftLengthBytes );
+	if ( plvTdoExpected )
+	{
+		readVal( plvTdoExpected, sShiftLengthBytes );
+	}
+	return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits,
+			   plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask,
+			   ucEndState, lRunTestTime, ucMaxRepeat ) );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoSDRMasking
+ * Description:  Update the data value with the next XSDRINC data and address.
+ * Example:      dataVal=0x01ff, nextData=0xab, addressMask=0x0100,
+ *               dataMask=0x00ff, should set dataVal to 0x02ab
+ * Parameters:   plvTdi          - The current TDI value.
+ *               plvNextData     - the next data value.
+ *               plvAddressMask  - the address mask.
+ *               plvDataMask     - the data mask.
+ * Returns:      void.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+void xsvfDoSDRMasking( lenVal*  plvTdi,
+		       lenVal*  plvNextData,
+		       lenVal*  plvAddressMask,
+		       lenVal*  plvDataMask )
+{
+	int             i;
+	unsigned char   ucTdi;
+	unsigned char   ucTdiMask;
+	unsigned char   ucDataMask;
+	unsigned char   ucNextData;
+	unsigned char   ucNextMask;
+	short           sNextData;
+
+	/* add the address Mask to dataVal and return as a new dataVal */
+	addVal( plvTdi, plvTdi, plvAddressMask );
+
+	ucNextData  = 0;
+	ucNextMask  = 0;
+	sNextData   = plvNextData->len;
+	for ( i = plvDataMask->len - 1; i >= 0; --i )
+	{
+		/* Go through data mask in reverse order looking for mask (1) bits */
+		ucDataMask  = plvDataMask->val[ i ];
+		if ( ucDataMask )
+		{
+			/* Retrieve the corresponding TDI byte value */
+			ucTdi       = plvTdi->val[ i ];
+
+			/* For each bit in the data mask byte, look for 1's */
+			ucTdiMask   = 1;
+			while ( ucDataMask )
+			{
+				if ( ucDataMask & 1 )
+				{
+					if ( !ucNextMask )
+					{
+						/* Get the next data byte */
+						ucNextData  = plvNextData->val[ --sNextData ];
+						ucNextMask  = 1;
+					}
+
+					/* Set or clear the data bit according to the next data */
+					if ( ucNextData & ucNextMask )
+					{
+						ucTdi   |= ucTdiMask;       /* Set bit */
+					}
+					else
+					{
+						ucTdi   &= ( ~ucTdiMask );  /* Clear bit */
+					}
+
+					/* Update the next data */
+					ucNextMask  <<= 1;
+				}
+				ucTdiMask   <<= 1;
+				ucDataMask  >>= 1;
+			}
+
+			/* Update the TDI value */
+			plvTdi->val[ i ]    = ucTdi;
+		}
+	}
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*============================================================================
+ * XSVF Command Functions (type = TXsvfDoCmdFuncPtr)
+ * These functions update pXsvfInfo->iErrorCode only on an error.
+ * Otherwise, the error code is left alone.
+ * The function returns the error code from the function.
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfDoIllegalCmd
+ * Description:  Function place holder for illegal/unsupported commands.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo )
+{
+	XSVFDBG_PRINTF2( 0, "ERROR:  Encountered unsupported command #%d (%s)\n",
+			 ((unsigned int)(pXsvfInfo->ucCommand)),
+			 ((pXsvfInfo->ucCommand < XLASTCMD)
+			  ? (xsvf_pzCommandName[pXsvfInfo->ucCommand])
+			  : "Unknown") );
+	pXsvfInfo->iErrorCode   = XSVF_ERROR_ILLEGALCMD;
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXCOMPLETE
+ * Description:  XCOMPLETE (no parameters)
+ *               Update complete status for XSVF player.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo )
+{
+	pXsvfInfo->ucComplete   = 1;
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXTDOMASK
+ * Description:  XTDOMASK <lenVal.TdoMask[XSDRSIZE]>
+ *               Prespecify the TDO compare mask.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo )
+{
+	readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes );
+	XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) );
+	XSVFDBG_PRINTF( 4, "\n");
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSIR
+ * Description:  XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]>
+ *               Get the instruction and shift the instruction into the TAP.
+ *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ *               the shift for XRUNTEST usec.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucShiftIrBits;
+	short           sShiftIrBytes;
+	int             iErrorCode;
+
+	/* Get the shift length and store */
+	readByte( &ucShiftIrBits );
+	sShiftIrBytes   = xsvfGetAsNumBytes( ucShiftIrBits );
+	XSVFDBG_PRINTF1( 3, "   XSIR length = %d\n",
+			 ((unsigned int)ucShiftIrBits) );
+
+	if ( sShiftIrBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+	}
+	else
+	{
+		/* Get and store instruction to shift in */
+		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) );
+
+		/* Shift the data */
+		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+					 ucShiftIrBits, &(pXsvfInfo->lvTdi),
+					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSIR2
+ * Description:  XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]>
+ *               Get the instruction and shift the instruction into the TAP.
+ *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ *               the shift for XRUNTEST usec.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo )
+{
+	long            lShiftIrBits;
+	short           sShiftIrBytes;
+	int             iErrorCode;
+
+	/* Get the shift length and store */
+	readVal( &(pXsvfInfo->lvTdi), 2 );
+	lShiftIrBits    = value( &(pXsvfInfo->lvTdi) );
+	sShiftIrBytes   = xsvfGetAsNumBytes( lShiftIrBits );
+	XSVFDBG_PRINTF1( 3, "   XSIR2 length = %d\n", (int)lShiftIrBits);
+
+	if ( sShiftIrBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+	}
+	else
+	{
+		/* Get and store instruction to shift in */
+		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) );
+
+		/* Shift the data */
+		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+					 lShiftIrBits, &(pXsvfInfo->lvTdi),
+					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDR
+ * Description:  XSDR <lenVal.TDI[XSDRSIZE]>
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Compare the captured TDO with the expected TDO from the
+ *               previous XSDRTDO command using the previously specified
+ *               XTDOMASK.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+	/* use TDOExpected from last XSDRTDO instruction */
+	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+				 pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi),
+				 &(pXsvfInfo->lvTdoCaptured),
+				 &(pXsvfInfo->lvTdoExpected),
+				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXRUNTEST
+ * Description:  XRUNTEST <uint32>
+ *               Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo )
+{
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) );
+	XSVFDBG_PRINTF1( 3, "   XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime );
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXREPEAT
+ * Description:  XREPEAT <byte>
+ *               Prespecify the maximum number of XC9500/XL retries.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo )
+{
+	readByte( &(pXsvfInfo->ucMaxRepeat) );
+	XSVFDBG_PRINTF1( 3, "   XREPEAT = %d\n",
+			 ((unsigned int)(pXsvfInfo->ucMaxRepeat)) );
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRSIZE
+ * Description:  XSDRSIZE <uint32>
+ *               Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	iErrorCode  = XSVF_ERROR_NONE;
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) );
+	pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits );
+	XSVFDBG_PRINTF1( 3, "   XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits );
+	if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRTDO
+ * Description:  XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ *               Get the TDI and expected TDO values.  Then, shift.
+ *               Compare the expected TDO with the captured TDO using the
+ *               prespecified XTDOMASK.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					&(pXsvfInfo->lvTdoCaptured),
+					&(pXsvfInfo->lvTdoExpected),
+					&(pXsvfInfo->lvTdoMask),
+					pXsvfInfo->ucEndDR,
+					pXsvfInfo->lRunTestTime,
+					pXsvfInfo->ucMaxRepeat );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSETSDRMASKS
+ * Description:  XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]>
+ *                            <lenVal.DataMask[XSDRSIZE]>
+ *               Get the prespecified address and data mask for the XSDRINC
+ *               command.
+ *               Used for xc9500/xl compressed XSVF data.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo )
+{
+	/* read the addressMask */
+	readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes );
+	/* read the dataMask    */
+	readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes );
+
+	XSVFDBG_PRINTF( 4, "    Address Mask = " );
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) );
+	XSVFDBG_PRINTF( 4, "\n" );
+	XSVFDBG_PRINTF( 4, "    Data Mask    = " );
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) );
+	XSVFDBG_PRINTF( 4, "\n" );
+
+	return( XSVF_ERROR_NONE );
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRINC
+ * Description:  XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)>
+ *                       <lenVal.data[XSETSDRMASKS.dataMask.len]> ...
+ *               Get the XSDRINC parameters and execute the XSDRINC command.
+ *               XSDRINC starts by loading the first TDI shift value.
+ *               Then, for numTimes, XSDRINC gets the next piece of data,
+ *               replaces the bits from the starting TDI as defined by the
+ *               XSETSDRMASKS.dataMask, adds the address mask from
+ *               XSETSDRMASKS.addressMask, shifts the new TDI value,
+ *               and compares the TDO to the expected TDO from the previous
+ *               XSDRTDO command using the XTDOMASK.
+ *               Used for xc9500/xl compressed XSVF data.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo )
+{
+	int             iErrorCode;
+	int             iDataMaskLen;
+	unsigned char   ucDataMask;
+	unsigned char   ucNumTimes;
+	unsigned char   i;
+
+	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+				 pXsvfInfo->lShiftLengthBits,
+				 &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured),
+				 &(pXsvfInfo->lvTdoExpected),
+				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+	if ( !iErrorCode )
+	{
+		/* Calculate number of data mask bits */
+		iDataMaskLen    = 0;
+		for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i )
+		{
+			ucDataMask  = pXsvfInfo->lvDataMask.val[ i ];
+			while ( ucDataMask )
+			{
+				iDataMaskLen    += ( ucDataMask & 1 );
+				ucDataMask      >>= 1;
+			}
+		}
+
+		/* Get the number of data pieces, i.e. number of times to shift */
+		readByte( &ucNumTimes );
+
+		/* For numTimes, get data, fix TDI, and shift */
+		for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i )
+		{
+			readVal( &(pXsvfInfo->lvNextData),
+				 xsvfGetAsNumBytes( iDataMaskLen ) );
+			xsvfDoSDRMasking( &(pXsvfInfo->lvTdi),
+					  &(pXsvfInfo->lvNextData),
+					  &(pXsvfInfo->lvAddressMask),
+					  &(pXsvfInfo->lvDataMask) );
+			iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState),
+						 XTAPSTATE_SHIFTDR,
+						 pXsvfInfo->lShiftLengthBits,
+						 &(pXsvfInfo->lvTdi),
+						 &(pXsvfInfo->lvTdoCaptured),
+						 &(pXsvfInfo->lvTdoExpected),
+						 &(pXsvfInfo->lvTdoMask),
+						 pXsvfInfo->ucEndDR,
+						 pXsvfInfo->lRunTestTime,
+						 pXsvfInfo->ucMaxRepeat );
+		}
+	}
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRBCE
+ * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]>
+ *               If not already in SHIFTDR, goto SHIFTDR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Ignore TDO.
+ *               If cmd==XSDRE, then goto ENDDR.  Otherwise, stay in ShiftDR.
+ *               XSDRB, XSDRC, and XSDRE are the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucEndDR;
+	int             iErrorCode;
+	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ?
+				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					/*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					/*plvTdoMask*/0, ucEndDR,
+					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRTDOBCE
+ * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ *               If not already in SHIFTDR, goto SHIFTDR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Compare TDO, but do NOT use XTDOMASK.
+ *               If cmd==XSDRTDOE, then goto ENDDR.  Otherwise, stay in ShiftDR.
+ *               XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucEndDR;
+	int             iErrorCode;
+	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ?
+				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					&(pXsvfInfo->lvTdoCaptured),
+					&(pXsvfInfo->lvTdoExpected),
+					/*plvTdoMask*/0, ucEndDR,
+					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSTATE
+ * Description:  XSTATE <byte>
+ *               <byte> == XTAPSTATE;
+ *               Get the state parameter and transition the TAP to that state.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucNextState;
+	int             iErrorCode;
+	readByte( &ucNextState );
+	iErrorCode  = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXENDXR
+ * Description:  XENDIR/XENDDR <byte>
+ *               <byte>:  0 = RUNTEST;  1 = PAUSE.
+ *               Get the prespecified XENDIR or XENDDR.
+ *               Both XENDIR and XENDDR use the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo )
+{
+	int             iErrorCode;
+	unsigned char   ucEndState;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	readByte( &ucEndState );
+	if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) )
+	{
+		iErrorCode  = XSVF_ERROR_ILLEGALSTATE;
+	}
+	else
+	{
+
+		if ( pXsvfInfo->ucCommand == XENDIR )
+		{
+			if ( ucEndState == XENDXR_RUNTEST )
+			{
+				pXsvfInfo->ucEndIR  = XTAPSTATE_RUNTEST;
+			}
+			else
+			{
+				pXsvfInfo->ucEndIR  = XTAPSTATE_PAUSEIR;
+			}
+			XSVFDBG_PRINTF1( 3, "   ENDIR State = %s\n",
+					 xsvf_pzTapState[ pXsvfInfo->ucEndIR ] );
+		}
+		else    /* XENDDR */
+		{
+			if ( ucEndState == XENDXR_RUNTEST )
+			{
+				pXsvfInfo->ucEndDR  = XTAPSTATE_RUNTEST;
+			}
+			else
+			{
+				pXsvfInfo->ucEndDR  = XTAPSTATE_PAUSEDR;
+			}
+			XSVFDBG_PRINTF1( 3, "   ENDDR State = %s\n",
+					 xsvf_pzTapState[ pXsvfInfo->ucEndDR ] );
+		}
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXCOMMENT
+ * Description:  XCOMMENT <text string ending in \0>
+ *               <text string ending in \0> == text comment;
+ *               Arbitrary comment embedded in the XSVF.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo )
+{
+	/* Use the comment for debugging */
+	/* Otherwise, read through the comment to the end '\0' and ignore */
+	unsigned char   ucText;
+
+	if ( xsvf_iDebugLevel > 0 )
+	{
+		putc( ' ' );
+	}
+
+	do
+	{
+		readByte( &ucText );
+		if ( xsvf_iDebugLevel > 0 )
+		{
+			putc( ucText ? ucText : '\n' );
+		}
+	} while ( ucText );
+
+	pXsvfInfo->iErrorCode   = XSVF_ERROR_NONE;
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXWAIT
+ * Description:  XWAIT <wait_state> <end_state> <wait_time>
+ *               If not already in <wait_state>, then go to <wait_state>.
+ *               Wait in <wait_state> for <wait_time> microseconds.
+ *               Finally, if not already in <end_state>, then goto <end_state>.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucWaitState;
+	unsigned char   ucEndState;
+	long            lWaitTime;
+
+	/* Get Parameters */
+	/* <wait_state> */
+	readVal( &(pXsvfInfo->lvTdi), 1 );
+	ucWaitState = pXsvfInfo->lvTdi.val[0];
+
+	/* <end_state> */
+	readVal( &(pXsvfInfo->lvTdi), 1 );
+	ucEndState = pXsvfInfo->lvTdi.val[0];
+
+	/* <wait_time> */
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	lWaitTime = value( &(pXsvfInfo->lvTdi) );
+	XSVFDBG_PRINTF2( 3, "   XWAIT:  state = %s; time = %ld\n",
+			 xsvf_pzTapState[ ucWaitState ], lWaitTime );
+
+	/* If not already in <wait_state>, go to <wait_state> */
+	if ( pXsvfInfo->ucTapState != ucWaitState )
+	{
+		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState );
+	}
+
+	/* Wait for <wait_time> microseconds */
+	waitTime( lWaitTime );
+
+	/* If not already in <end_state>, go to <end_state> */
+	if ( pXsvfInfo->ucTapState != ucEndState )
+	{
+		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState );
+	}
+
+	return( XSVF_ERROR_NONE );
+}
+
+
+/*============================================================================
+ * Execution Control Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfInitialize
+ * Description:  Initialize the xsvf player.
+ *               Call this before running the player to initialize the data
+ *               in the SXsvfInfo struct.
+ *               xsvfCleanup is called to clean up the data in SXsvfInfo
+ *               after the XSVF is played.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInitialize( SXsvfInfo* pXsvfInfo )
+{
+	/* Initialize values */
+	pXsvfInfo->iErrorCode   = xsvfInfoInit( pXsvfInfo );
+
+	if ( !pXsvfInfo->iErrorCode )
+	{
+		/* Initialize the TAPs */
+		pXsvfInfo->iErrorCode   = xsvfGotoTapState( &(pXsvfInfo->ucTapState),
+							    XTAPSTATE_RESET );
+	}
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfRun
+ * Description:  Run the xsvf player for a single command and return.
+ *               First, call xsvfInitialize.
+ *               Then, repeatedly call this function until an error is detected
+ *               or until the pXsvfInfo->ucComplete variable is non-zero.
+ *               Finally, call xsvfCleanup to cleanup any remnants.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      int         - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfRun( SXsvfInfo* pXsvfInfo )
+{
+	/* Process the XSVF commands */
+	if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) )
+	{
+		/* read 1 byte for the instruction */
+		readByte( &(pXsvfInfo->ucCommand) );
+		++(pXsvfInfo->lCommandCount);
+
+		if ( pXsvfInfo->ucCommand < XLASTCMD )
+		{
+			/* Execute the command.  Func sets error code. */
+			XSVFDBG_PRINTF1( 2, "  %s\n",
+					 xsvf_pzCommandName[pXsvfInfo->ucCommand] );
+			/* If your compiler cannot take this form,
+			   then convert to a switch statement */
+#if 0 /* test-only */
+			xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo );
+#else
+			switch (pXsvfInfo->ucCommand) {
+			case 0:
+				xsvfDoXCOMPLETE(pXsvfInfo);        /*  0 */
+				break;
+			case 1:
+				xsvfDoXTDOMASK(pXsvfInfo);         /*  1 */
+				break;
+			case 2:
+				xsvfDoXSIR(pXsvfInfo);             /*  2 */
+				break;
+			case 3:
+				xsvfDoXSDR(pXsvfInfo);             /*  3 */
+				break;
+			case 4:
+				xsvfDoXRUNTEST(pXsvfInfo);         /*  4 */
+				break;
+			case 5:
+				xsvfDoIllegalCmd(pXsvfInfo);       /*  5 */
+				break;
+			case 6:
+				xsvfDoIllegalCmd(pXsvfInfo);       /*  6 */
+				break;
+			case 7:
+				xsvfDoXREPEAT(pXsvfInfo);          /*  7 */
+				break;
+			case 8:
+				xsvfDoXSDRSIZE(pXsvfInfo);         /*  8 */
+				break;
+			case 9:
+				xsvfDoXSDRTDO(pXsvfInfo);          /*  9 */
+				break;
+#ifdef  XSVF_SUPPORT_COMPRESSION
+			case 10:
+				xsvfDoXSETSDRMASKS(pXsvfInfo);     /* 10 */
+				break;
+			case 11:
+				xsvfDoXSDRINC(pXsvfInfo);          /* 11 */
+				break;
+#else
+			case 10:
+				xsvfDoIllegalCmd(pXsvfInfo);       /* 10 */
+				break;
+			case 11:
+				xsvfDoIllegalCmd(pXsvfInfo);       /* 11 */
+				break;
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+			case 12:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 12 */
+				break;
+			case 13:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 13 */
+				break;
+			case 14:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 14 */
+				break;
+			case 15:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 15 */
+				break;
+			case 16:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 16 */
+				break;
+			case 17:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 17 */
+				break;
+			case 18:
+				xsvfDoXSTATE(pXsvfInfo);           /* 18 */
+				break;
+			case 19:
+				xsvfDoXENDXR(pXsvfInfo);           /* 19 */
+				break;
+			case 20:
+				xsvfDoXENDXR(pXsvfInfo);           /* 20 */
+				break;
+			case 21:
+				xsvfDoXSIR2(pXsvfInfo);            /* 21 */
+				break;
+			case 22:
+				xsvfDoXCOMMENT(pXsvfInfo);         /* 22 */
+				break;
+			case 23:
+				xsvfDoXWAIT(pXsvfInfo);             /* 23 */
+				break;
+			}
+#endif
+		}
+		else
+		{
+			/* Illegal command value.  Func sets error code. */
+			xsvfDoIllegalCmd( pXsvfInfo );
+		}
+	}
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfCleanup
+ * Description:  cleanup remnants of the xsvf player.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfCleanup( SXsvfInfo* pXsvfInfo )
+{
+	xsvfInfoCleanup( pXsvfInfo );
+}
+
+
+/*============================================================================
+ * xsvfExecute() - The primary entry point to the XSVF player
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - Legacy result values:  1 == success;  0 == failed.
+ *****************************************************************************/
+int xsvfExecute(void)
+{
+	SXsvfInfo   xsvfInfo;
+
+	xsvfInitialize( &xsvfInfo );
+
+	while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) )
+	{
+		xsvfRun( &xsvfInfo );
+	}
+
+	if ( xsvfInfo.iErrorCode )
+	{
+		XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[
+					 ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST )
+					 ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] );
+		XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld.  See line #%ld in the XSVF ASCII file.\n",
+				 xsvfInfo.lCommandCount, xsvfInfo.lCommandCount );
+	}
+	else
+	{
+		XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" );
+	}
+
+	xsvfCleanup( &xsvfInfo );
+
+	return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) );
+}
+
+
+/*****************************************************************************
+ * Function:     do_cpld
+ * Description:  main function.
+ *               Specified here for creating stand-alone debug executable.
+ *               Embedded users should call xsvfExecute() directly.
+ * Parameters:   iArgc    - number of command-line arguments.
+ *               ppzArgv  - array of ptrs to strings (command-line arguments).
+ * Returns:      int      - Legacy return value:  1 = success; 0 = error.
+ *****************************************************************************/
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int     iErrorCode;
+	char*   pzXsvfFileName;
+	unsigned long duration;
+	unsigned long long startClock, endClock;
+
+	if (argc == 2)
+		xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16);
+	else {
+#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR
+		xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR;
+#else
+		printf("Usage:\ncpld %s\n", cmdtp->help);
+		return -1;
+#endif
+	}
+
+	iErrorCode          = XSVF_ERRORCODE( XSVF_ERROR_NONE );
+	pzXsvfFileName      = 0;
+	xsvf_iDebugLevel    = 0;
+
+	printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
+	printf("Reading XSVF data @ %p\n", xsvfdata);
+
+	/* Initialize the I/O.  SetPort initializes I/O on first call */
+	setPort( TMS, 1 );
+
+	/* Execute the XSVF in the file */
+	startClock  = get_ticks();
+	iErrorCode  = xsvfExecute();
+	endClock    = get_ticks();
+	duration    = (unsigned long)(endClock - startClock);
+	printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk()));
+
+	return( iErrorCode );
+}
+U_BOOT_CMD(
+	cpld,	2,	1,	do_cpld,
+	"program onboard CPLD",
+	"<xsvf-addr>"
+);
diff --git a/u-boot/board/esd/common/xilinx_jtag/micro.h b/u-boot/board/esd/common/xilinx_jtag/micro.h
new file mode 100644
index 0000000..3c463ab
--- /dev/null
+++ b/u-boot/board/esd/common/xilinx_jtag/micro.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File:         micro.h
+ * Description:  This header file contains the function prototype to the
+ *               primary interface function for the XSVF player.
+ * Usage:        FIRST - PORTS.C
+ *               Customize the ports.c function implementations to establish
+ *               the correct protocol for communicating with your JTAG ports
+ *               (setPort() and readTDOBit()) and tune the waitTime() delay
+ *               function.  Also, establish access to the XSVF data source
+ *               in the readByte() function.
+ *               FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR   0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE         0
+#define XSVF_ERROR_UNKNOWN      1
+#define XSVF_ERROR_TDOMISMATCH  2
+#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD   4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST         7
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif  /* XSVF_MICRO_H */
diff --git a/u-boot/board/esd/common/xilinx_jtag/ports.c b/u-boot/board/esd/common/xilinx_jtag/ports.c
new file mode 100644
index 0000000..f039d04
--- /dev/null
+++ b/u-boot/board/esd/common/xilinx_jtag/ports.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: ports.c                                       */
+/* abstract:  This file contains the routines to       */
+/*            output values on the JTAG ports, to read */
+/*            the TDO bit, and to read a byte of data  */
+/*            from the prom                            */
+/*                                                     */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include "ports.h"
+
+static unsigned long output = 0;
+static int filepos = 0;
+static int oldstate = 0;
+static int newstate = 0;
+static int readptr = 0;
+
+extern const unsigned char *xsvfdata;
+
+/* if in debugging mode, then just set the variables */
+void setPort(short p,short val)
+{
+	if (p==TMS) {
+		if (val) {
+			output |= JTAG_TMS;
+		} else {
+			output &= ~JTAG_TMS;
+		}
+	}
+	if (p==TDI) {
+		if (val) {
+			output |= JTAG_TDI;
+		} else {
+			output &= ~JTAG_TDI;
+		}
+	}
+	if (p==TCK) {
+		if (val) {
+			output |= JTAG_TCK;
+		} else {
+			output &= ~JTAG_TCK;
+		}
+		out_be32((void *)GPIO0_OR, output);
+	}
+}
+
+
+/* toggle tck LH */
+void pulseClock(void)
+{
+	setPort(TCK,0);  /* set the TCK port to low  */
+	setPort(TCK,1);  /* set the TCK port to high */
+}
+
+
+/* read in a byte of data from the prom */
+void readByte(unsigned char *data)
+{
+	/* pretend reading using a file */
+	*data = xsvfdata[readptr++];
+	newstate = filepos++ >> 10;
+	if (newstate != oldstate) {
+		printf("%4d kB\r\r\r\r", newstate);
+		oldstate = newstate;
+	}
+}
+
+/* read the TDO bit from port */
+unsigned char readTDOBit(void)
+{
+	unsigned long inputs;
+
+	inputs = in_be32((void *)GPIO0_IR);
+	if (inputs & JTAG_TDO)
+		return 1;
+	else
+		return 0;
+}
+
+
+/* Wait at least the specified number of microsec.                           */
+/* Use a timer if possible; otherwise estimate the number of instructions    */
+/* necessary to be run based on the microcontroller speed.  For this example */
+/* we pulse the TCK port a number of times based on the processor speed.     */
+void waitTime(long microsec)
+{
+	udelay(microsec); /* esd */
+}
diff --git a/u-boot/board/esd/common/xilinx_jtag/ports.h b/u-boot/board/esd/common/xilinx_jtag/ports.h
new file mode 100644
index 0000000..b702fdd
--- /dev/null
+++ b/u-boot/board/esd/common/xilinx_jtag/ports.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: ports.h                                       */
+/* abstract:  This file contains extern declarations   */
+/*            for providing stimulus to the JTAG ports.*/
+/*******************************************************/
+
+#ifndef ports_dot_h
+#define ports_dot_h
+
+/* these constants are used to send the appropriate ports to setPort */
+/* they should be enumerated types, but some of the microcontroller  */
+/* compilers don't like enumerated types */
+#define TCK (short) 0
+#define TMS (short) 1
+#define TDI (short) 2
+
+/*
+ * Use CONFIG_SYS_FPGA_xxx defines from board include file.
+ */
+#define JTAG_TMS   CONFIG_SYS_FPGA_PRG     /* output */
+#define JTAG_TCK   CONFIG_SYS_FPGA_CLK     /* output */
+#define JTAG_TDI   CONFIG_SYS_FPGA_DATA    /* output */
+#define JTAG_TDO   CONFIG_SYS_FPGA_DONE    /* input */
+
+/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
+void setPort(short p, short val);
+
+/* read the TDO bit and store it in val */
+unsigned char readTDOBit(void);
+
+/* make clock go down->up->down*/
+void pulseClock(void);
+
+/* read the next byte of data from the xsvf file */
+void readByte(unsigned char *data);
+
+void waitTime(long microsec);
+
+#endif
diff --git a/u-boot/board/esd/cpci2dp/Makefile b/u-boot/board/esd/cpci2dp/Makefile
new file mode 100644
index 0000000..be65097
--- /dev/null
+++ b/u-boot/board/esd/cpci2dp/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/cpci2dp/cpci2dp.c b/u-boot/board/esd/cpci2dp/cpci2dp.c
new file mode 100644
index 0000000..ecfcf59
--- /dev/null
+++ b/u-boot/board/esd/cpci2dp/cpci2dp.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/*
+	 * Setup GPIO pins
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg |
+	      ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
+		CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
+
+	/* set output pins to high */
+	out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
+	/* setup for output (LED=off) */
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) unused
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
+
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Select cts (and not dsr) on uart1
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming CPCI2DP");
+	} else {
+		puts(str);
+	}
+
+	printf(" (Ver 1.0)");
+
+	putc ('\n');
+
+	return 0;
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *	   <state>     -1: deliver current state
+ *		       0: disable write
+ *		       1: enable write
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(
+	eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/u-boot/board/esd/cpci2dp/flash.c b/u-boot/board/esd/cpci2dp/flash.c
new file mode 100644
index 0000000..b210281
--- /dev/null
+++ b/u-boot/board/esd/cpci2dp/flash.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+	/*          printf("PB1CR = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/cpci405/Makefile b/u-boot/board/esd/cpci405/Makefile
new file mode 100644
index 0000000..c6e1d40
--- /dev/null
+++ b/u-boot/board/esd/cpci405/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	+= ../common/cmd_loadpci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/cpci405/cpci405.c b/u-boot/board/esd/cpci405/cpci405.c
new file mode 100644
index 0000000..98a8584
--- /dev/null
+++ b/u-boot/board/esd/cpci405/cpci405.c
@@ -0,0 +1,791 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+#undef FPGA_DEBUG
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#if defined(CONFIG_CPCI405_VER2)
+# if defined(CONFIG_CPCI405AB)
+#  include "fpgadata_cpci405ab.c"
+# else
+#  include "fpgadata_cpci4052.c"
+# endif
+#else
+# include "fpgadata_cpci405.c"
+#endif
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+#include "../common/auto_update.h"
+
+#if defined(CONFIG_CPCI405AB)
+au_image_t au_image[] = {
+	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+#if defined(CONFIG_CPCI405_VER2)
+au_image_t au_image[] = {
+	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+au_image_t au_image[] = {
+	{"cpci405/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
+	{"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
+	{"cpci405/postinst.img", 0, 0, AU_SCRIPT},
+};
+#endif
+#endif
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+/* Prototypes */
+int cpci405_version(void);
+void lxt971_no_sleep(void);
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_CPCI405_VER2
+	int index, len, i;
+	int status;
+#endif
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void)get_clocks();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	console_init_f();
+#endif
+
+	/*
+	 * First pull fpga-prg pin low,
+	 * to disable fpga logic (on version 2 board)
+	 */
+	out_be32((void *)GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output	*/
+	out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+	out_be32((void *)GPIO0_OR, 0);		     /* pull prg low		*/
+
+	/*
+	 * Boot onboard FPGA
+	 */
+#ifndef CONFIG_CPCI405_VER2
+	if (cpci405_version() == 1) {
+		status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+		if (status != 0) {
+			/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+			/* set up serial port with default baudrate */
+			(void)get_clocks();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init();
+			console_init_f();
+#endif
+			printf("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf("Rebooting in %2d seconds \r",i);
+				for (index = 0; index < 1000; index++)
+					udelay(1000);
+			}
+			putc('\n');
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+#endif /* !CONFIG_CPCI405_VER2 */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
+#if defined(CONFIG_CPCI405_6U)
+	if (cpci405_version() == 3) {
+		mtdcr(UIC0PR, 0xFFFFFF99);	/* set int polarities */
+	} else {
+		mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	}
+#else
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
+#endif
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,
+					 * INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int ctermm2(void)
+{
+#if defined(CONFIG_CPCI405_VER2)
+	return 0;			/* no, board is cpci405 */
+#else
+	if ((in_8((void*)0xf0000400) == 0x00) &&
+	    (in_8((void*)0xf0000401) == 0x01))
+		return 0;		/* no, board is cpci405 */
+	else
+		return -1;		/* yes, board is cterm-m2 */
+#endif
+}
+
+int cpci405_host(void)
+{
+	if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
+		return -1;		/* yes, board is cpci405 host */
+	else
+		return 0;		/* no, board is cpci405 adapter */
+}
+
+int cpci405_version(void)
+{
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
+	udelay(1000); /* wait some time before reading input */
+	value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version 1 */
+		return 1;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 2 */
+		return 2;
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 3 or 6U board */
+		return 3;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 4 */
+		return 4;
+	default:
+		/* should not be reached! */
+		return 2;
+	}
+}
+
+int misc_init_r (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_CPCI405_VER2)
+	{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	/*
+	 * On CPCI-405 version 2 the environment is saved in eeprom!
+	 * FPGA can be gzip compressed (malloc) and booted this late.
+	 */
+	if (cpci405_version() >= 2) {
+		/*
+		 * Setup GPIO pins (CS6+CS7 as GPIO)
+		 */
+		CPC0_CR0Reg = mfdcr(CPC0_CR0);
+		mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+		if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+			   (uchar *)fpgadata, &len) != 0) {
+			printf("GUNZIP ERROR - must RESET board to recover\n");
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		status = fpga_boot(dst, len);
+		if (status != 0) {
+			printf("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = dst[index];
+				printf("FPGA: %s\n", &(dst[index + 1]));
+				index += len + 3;
+			}
+			putc('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay(1000);
+			}
+			putc('\n');
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		/* restore gpio/cs settings */
+		mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+		puts("FPGA:  ");
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = dst[index];
+			printf("%s ", &(dst[index + 1]));
+			index += len + 3;
+		}
+		putc('\n');
+
+		free(dst);
+
+		/*
+		 * Reset FPGA via FPGA_DATA pin
+		 */
+		SET_FPGA(FPGA_PRG | FPGA_CLK);
+		udelay(1000); /* wait 1ms */
+		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+		udelay(1000); /* wait 1ms */
+
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
+		if (cpci405_version() == 3) {
+			/*
+			 * Enable outputs in fpga on version 3 board
+			 */
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
+
+			/*
+			 * Set outputs to 0
+			 */
+			out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
+
+			/*
+			 * Reset external DUART
+			 */
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_DUART_RESET);
+			udelay(100);
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+				 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
+		}
+#endif
+	}
+	else {
+		puts("\n*** U-Boot Version does not match Board Version!\n");
+		puts("*** CPCI-405 Version 1.x detected!\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI405 instead of CPCI4052)!\n\n");
+	}
+	}
+#else /* CONFIG_CPCI405_VER2 */
+	if (cpci405_version() >= 2) {
+		puts("\n*** U-Boot Version does not match Board Version!\n");
+		puts("*** CPCI-405 Board Version 2.x detected!\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI4052 instead of CPCI405)!\n\n");
+	}
+#endif /* CONFIG_CPCI405_VER2 */
+
+	/*
+	 * Select cts (and not dsr) on uart1
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+#ifndef CONFIG_CPCI405_VER2
+	int index;
+	int len;
+#endif
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+	unsigned short ver;
+
+	puts("Board: ");
+
+	if (i == -1)
+		puts("### No HW ID - assuming CPCI405");
+	else
+		puts(str);
+
+	ver = cpci405_version();
+	printf(" (Ver %d.x, ", ver);
+
+	if (ctermm2()) {
+		char str[4];
+
+		/*
+		 * Read board-id and save in env-variable
+		 */
+		sprintf(str, "%d", *(unsigned char *)0xf0000400);
+		setenv("boardid", str);
+		printf("CTERM-M2 - Id=%s)", str);
+	} else {
+		if (cpci405_host())
+			puts("PCI Host Version)");
+		else
+			puts("PCI Adapter Version)");
+	}
+
+#ifndef CONFIG_CPCI405_VER2
+	puts("\nFPGA:	");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+#endif
+
+	putc('\n');
+	return 0;
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_LXT971_NO_SLEEP)
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {	/* assert RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+			 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+	} else {	/* release RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+			 CONFIG_SYS_FPGA_MODE_CF_RESET);
+	}
+}
+
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
+
+#if defined(CONFIG_PCI)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = 0xff;
+
+	/*
+	 * Write pci interrupt line register (cpci405 specific)
+	 */
+	switch (PCI_DEV(dev) & 0x03) {
+	case 0:
+		int_line = 27 + 2;
+		break;
+	case 1:
+		int_line = 27 + 3;
+		break;
+	case 2:
+		int_line = 27 + 0;
+		break;
+	case 3:
+		int_line = 27 + 1;
+		break;
+	}
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+	hose->fixup_irq = cpci405_pci_fixup_irq;
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in adapter mode.
+	 */
+	if (!cpci405_host()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) | \
+					  CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_SET	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) & \
+					  ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_GET	 (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+					  CONFIG_SYS_FPGA_STATUS)) &  \
+			  CONFIG_SYS_FPGA_MODE_1WIRE)
+
+/*
+ * Generate a 1-wire reset, return 1 if no presence detect was found,
+ * return 0 otherwise.
+ * (NOTE: Does not handle alarm presence from DS2404/DS1994)
+ */
+int OWTouchReset(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(480);
+	ONE_WIRE_SET;
+	udelay(70);
+
+	result = ONE_WIRE_GET;
+
+	udelay(410);
+	return result;
+}
+
+/*
+ * Send 1 a 1-wire write bit.
+ * Provide 10us recovery time.
+ */
+void OWWriteBit(int bit)
+{
+	if (bit) {
+		/*
+		 * write '1' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(6);
+		ONE_WIRE_SET;
+		udelay(64);
+	} else {
+		/*
+		 * write '0' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(60);
+		ONE_WIRE_SET;
+		udelay(10);
+	}
+}
+
+/*
+ * Read a bit from the 1-wire bus and return it.
+ * Provide 10us recovery time.
+ */
+int OWReadBit(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(6);
+	ONE_WIRE_SET;
+	udelay(9);
+
+	result = ONE_WIRE_GET;
+
+	udelay(55);
+	return result;
+}
+
+void OWWriteByte(int data)
+{
+	int loop;
+
+	for (loop = 0; loop < 8; loop++) {
+		OWWriteBit(data & 0x01);
+		data >>= 1;
+	}
+}
+
+int OWReadByte(void)
+{
+	int loop, result = 0;
+
+	for (loop = 0; loop < 8; loop++) {
+		result >>= 1;
+		if (OWReadBit())
+			result |= 0x80;
+	}
+
+	return result;
+}
+
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned short val;
+	int result;
+	int i;
+	unsigned char ow_id[6];
+	char str[32];
+	unsigned char ow_crc;
+
+	/*
+	 * Clear 1-wire bit (open drain with pull-up)
+	 */
+	val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			      CONFIG_SYS_FPGA_MODE));
+	val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+	out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			 CONFIG_SYS_FPGA_MODE), val);
+
+	result = OWTouchReset();
+	if (result != 0)
+		puts("No 1-wire device detected!\n");
+
+	OWWriteByte(0x33); /* send read rom command */
+	OWReadByte(); /* skip family code ( == 0x01) */
+	for (i = 0; i < 6; i++)
+		ow_id[i] = OWReadByte();
+	ow_crc = OWReadByte(); /* read crc */
+
+	sprintf(str, "%08X%04X",
+		*(unsigned int *)&ow_id[0],
+		*(unsigned short *)&ow_id[4]);
+	printf("Setting environment variable 'ow_id' to %s\n", str);
+	setenv("ow_id", str);
+
+	return 0;
+}
+U_BOOT_CMD(
+	onewire,	1,	1,	do_onewire,
+	"Read 1-write ID",
+	""
+);
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
+
+/*
+ * Write backplane ip-address...
+ */
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	bd_t *bd = gd->bd;
+	char *buf;
+	ulong crc;
+	char str[32];
+	char *ptr;
+	IPaddr_t ipaddr;
+
+	buf = malloc(CONFIG_ENV_SIZE_2);
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+			(uchar *)buf, CONFIG_ENV_SIZE_2))
+		puts("\nError reading backplane EEPROM!\n");
+	else {
+		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
+		if (crc != *(ulong *)buf) {
+			printf("ERROR: crc mismatch %08lx %08lx\n",
+			       crc, *(ulong *)buf);
+			return -1;
+		}
+
+		/*
+		 * Find bp_ip
+		 */
+		ptr = strstr(buf+4, "bp_ip=");
+		if (ptr == NULL) {
+			printf("ERROR: bp_ip not found!\n");
+			return -1;
+		}
+		ptr += 6;
+		ipaddr = string_to_ip(ptr);
+
+		/*
+		 * Update whole ip-addr
+		 */
+		bd->bi_ip_addr = ipaddr;
+		sprintf(str, "%ld.%ld.%ld.%ld",
+			(bd->bi_ip_addr & 0xff000000) >> 24,
+			(bd->bi_ip_addr & 0x00ff0000) >> 16,
+			(bd->bi_ip_addr & 0x0000ff00) >> 8,
+			(bd->bi_ip_addr & 0x000000ff));
+		setenv("ipaddr", str);
+		printf("Updated ip_addr from bp_eeprom to %s!\n", str);
+	}
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getbpip,	1,	1,	do_get_bpip,
+	"Update IP-Address with Backplane IP-Address",
+	""
+);
+
+/*
+ * Set and print backplane ip...
+ */
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *buf;
+	char str[32];
+	ulong crc;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	printf("Setting bp_ip to %s\n", argv[1]);
+	buf = malloc(CONFIG_ENV_SIZE_2);
+	memset(buf, 0, CONFIG_ENV_SIZE_2);
+	sprintf(str, "bp_ip=%s", argv[1]);
+	strcpy(buf+4, str);
+	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
+	*(ulong *)buf = crc;
+
+	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+			 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
+		puts("\nError writing backplane EEPROM!\n");
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	setbpip,	2,	1,	do_set_bpip,
+	"Write Backplane IP-Address",
+	""
+);
+
+#endif /* CONFIG_CPCI405AB */
diff --git a/u-boot/board/esd/cpci405/flash.c b/u-boot/board/esd/cpci405/flash.c
new file mode 100644
index 0000000..4b12e92
--- /dev/null
+++ b/u-boot/board/esd/cpci405/flash.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long calc_size(unsigned long size)
+{
+	switch (size) {
+	case 1 << 20:
+		return 0;
+	case 2 << 20:
+		return 1;
+	case 4 << 20:
+		return 2;
+	case 8 << 20:
+		return 3;
+	case 16 << 20:
+		return 4;
+	default:
+		return 0;
+	}
+}
+
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		if (size_b1 < (1 << 20)) {
+			/* minimum CS size on PPC405GP is 1MB !!! */
+			size_b1 = 1 << 20;
+		}
+		base_b1 = -size_b1;
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+#if 0 /* test-only */
+		printf("size_b1=%x base_b1=%x PB1CR = %x\n",
+		       size_b1, base_b1, pbcr); /* test-only */
+#endif
+	}
+
+	if (size_b0) {
+		if (size_b0 < (1 << 20)) {
+			/* minimum CS size on PPC405GP is 1MB !!! */
+			size_b0 = 1 << 20;
+		}
+		base_b0 = base_b1 - size_b0;
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+#if 0 /* test-only */
+		printf("size_b0=%x base_b0=%x PB0CR = %x\n",
+		       size_b0, base_b0, pbcr); /* test-only */
+#endif
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/u-boot/board/esd/cpci405/fpgadata_cpci405.c b/u-boot/board/esd/cpci405/fpgadata_cpci405.c
new file mode 100644
index 0000000..20e61c1
--- /dev/null
+++ b/u-boot/board/esd/cpci405/fpgadata_cpci405.c
@@ -0,0 +1,342 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x63,0x70,0x63,0x69,0x34,0x30,0x35,0x32,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x31,0x2f,0x30,0x35,0x2f,0x31,0x30,0x00,0x64,0x00,0x09,0x31,0x35,0x3a,0x31,
+ 0x35,0x3a,0x32,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x15,0x08,0xff,0x30,0xe8,0x01,
+ 0x01,0x01,0x01,0xe7,0xe6,0x04,0x01,0x02,0x11,0x05,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x04,0x04,0x0b,0x02,0x02,0x01,0x04,0x02,0x01,0x0b,0x07,0x01,0x01,0x0d,0x03,
+ 0x05,0x09,0x03,0x05,0x03,0x05,0x03,0x0b,0x13,0x01,0x06,0xe5,0xe5,0x02,0x03,0x0c,
+ 0x01,0xe6,0x11,0x08,0x13,0x16,0x08,0x1e,0x0b,0xe5,0xe6,0x0e,0x09,0x09,0x09,0x09,
+ 0x0b,0x07,0xe6,0x08,0x02,0xe5,0x04,0x01,0xe6,0x04,0x0e,0x01,0x01,0x14,0x09,0x09,
+ 0x09,0x09,0x05,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0x01,0x05,0xe5,0x07,0x0c,0xe5,
+ 0x5b,0x01,0x01,0x05,0x01,0x11,0x02,0xe5,0xe5,0x48,0x13,0x1a,0x01,0xe6,0x3e,0x0b,
+ 0x10,0x03,0x05,0x13,0x03,0x01,0x28,0x14,0x11,0x24,0x03,0xe5,0xe6,0xe5,0x5d,0x01,
+ 0x17,0xe5,0x01,0x01,0x0b,0xe5,0x12,0x09,0x49,0x03,0x01,0x01,0x0d,0x31,0x0a,0x2f,
+ 0x01,0xe6,0x28,0x15,0x1e,0x1b,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,
+ 0x09,0x09,0x05,0x02,0x04,0x03,0x10,0x09,0x09,0x04,0x04,0x09,0x01,0x05,0x03,0x09,
+ 0x13,0x05,0x03,0x0e,0x01,0xe5,0x0c,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x03,0xe6,0x07,0xe5,0x04,0x02,0xe5,0x05,0x01,0xe5,0xe5,0x05,
+ 0xe5,0x0e,0x03,0x10,0x09,0x09,0x09,0x09,0x06,0x0d,0x0a,0xe5,0x06,0x0a,0x0e,0x01,
+ 0xe5,0x05,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x09,0xe5,0x07,
+ 0xe5,0x02,0x04,0xe5,0xe5,0x01,0x03,0xe5,0x07,0xe5,0x07,0x02,0x05,0xe6,0x0e,0x09,
+ 0x09,0x09,0x09,0x0d,0x13,0x03,0x05,0x02,0xe5,0x02,0x08,0x05,0xe8,0x0c,0x07,0x01,
+ 0x09,0x09,0x06,0x02,0x05,0x03,0x01,0x02,0x02,0x01,0x01,0x06,0x02,0x02,0x06,0x02,
+ 0x06,0x0a,0x06,0xe5,0xe5,0x0c,0x02,0x06,0x02,0x06,0x02,0x04,0x01,0x02,0x06,0x02,
+ 0x06,0x01,0x02,0x06,0x02,0x06,0x01,0xe6,0x02,0xe6,0xe6,0x05,0x02,0x0d,0x02,0xe5,
+ 0x02,0x2b,0x01,0x06,0x0b,0x0c,0x06,0x01,0x01,0xe5,0x14,0x02,0x03,0xe5,0xe6,0x13,
+ 0x23,0x0a,0x14,0x04,0x1c,0xe5,0xe6,0x27,0x01,0x0e,0x0a,0x03,0x13,0x1d,0x02,0xe5,
+ 0x0d,0x04,0xe7,0x14,0x0e,0x05,0xe5,0x05,0x0c,0x03,0x0a,0x01,0x09,0x0a,0x01,0x10,
+ 0x04,0xe5,0x02,0x09,0x09,0x09,0x09,0xe6,0x08,0x09,0x09,0xe5,0x07,0x0e,0xe5,0xe5,
+ 0x32,0x0d,0x10,0x02,0x02,0x03,0x02,0x02,0x03,0x15,0xe6,0x47,0x09,0x02,0x09,0x07,
+ 0x12,0xe5,0xe6,0x24,0x1c,0x12,0x09,0x16,0x03,0xe5,0x01,0x06,0x27,0x16,0x04,0x08,
+ 0x22,0x05,0x01,0x47,0x15,0x09,0x05,0x0c,0x02,0xe5,0x40,0xe5,0x11,0xe6,0x06,0x01,
+ 0x18,0xe8,0x05,0x3e,0x0f,0x0c,0x18,0x01,0xe5,0x2f,0x0f,0x13,0x08,0xe6,0x19,0xe6,
+ 0xe5,0x0b,0x2b,0x15,0x14,0x05,0x10,0x01,0xe6,0x3f,0x28,0x07,0x0a,0xe6,0x09,0x2e,
+ 0x2d,0x12,0xe8,0x59,0x08,0x0f,0xe5,0x04,0x01,0x01,0x23,0x07,0x01,0x01,0x17,0x2c,
+ 0x05,0xe8,0x22,0x09,0x02,0x28,0x0a,0x15,0xe6,0xe5,0x12,0x0d,0xe5,0x01,0x06,0x2e,
+ 0x09,0x16,0xe8,0x74,0xe5,0xe5,0xe7,0x01,0x01,0x50,0xe5,0x1d,0x01,0x02,0x01,0x01,
+ 0x04,0x52,0x18,0x01,0x02,0x01,0x03,0xe7,0x01,0x52,0x1a,0x06,0x02,0x03,0x57,0x11,
+ 0x01,0x05,0x06,0xe5,0x03,0x02,0x52,0x03,0x01,0x02,0x0a,0x01,0x01,0x06,0x02,0x02,
+ 0x01,0xe7,0x55,0x11,0x01,0x0b,0x02,0xe5,0x01,0x55,0x13,0x01,0x0e,0xe5,0xe6,0x04,
+ 0xe5,0x01,0x02,0x6c,0xe7,0xe5,0x04,0x04,0x6f,0xe6,0xe6,0x09,0x03,0x09,0x09,0x09,
+ 0x09,0x0b,0x09,0x09,0x09,0x09,0x06,0x06,0xe6,0xe6,0x01,0x6c,0x02,0x09,0xe6,0x6e,
+ 0x08,0x01,0xe5,0xe6,0x22,0x09,0x4e,0x01,0x23,0xe5,0x07,0xe5,0x4a,0xe9,0x1e,0x02,
+ 0x09,0x4d,0x01,0xe5,0x14,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0xe5,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0x02,0x09,0x19,0x09,
+ 0x50,0x23,0x09,0x4c,0xe5,0x01,0x23,0x09,0x4c,0x02,0xe5,0x08,0x19,0x09,0x4c,0xe5,
+ 0xe6,0x1e,0x59,0x02,0xe6,0x10,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x01,0x05,0x01,
+ 0x07,0x01,0x09,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe6,0xe5,
+ 0x77,0x02,0x02,0xe5,0x28,0x04,0x03,0x08,0x03,0x13,0x24,0xe6,0xe6,0x3e,0x3b,0xe5,
+ 0xe6,0x22,0x1a,0x39,0x02,0xe6,0x3e,0x3a,0x01,0x01,0xe5,0x11,0x2b,0x1b,0x1d,0xe5,
+ 0x02,0x3f,0x32,0x07,0xe5,0xe6,0x07,0x36,0x3c,0x01,0x1a,0x24,0xe5,0x38,0xe6,0xe5,
+ 0x0a,0x0a,0x28,0x3c,0x01,0x1b,0x5f,0xe7,0x7a,0xe7,0x7a,0x02,0x01,0x01,0x73,0xe5,
+ 0x02,0xe6,0x01,0x72,0x01,0x03,0xe7,0x03,0x6b,0x01,0x02,0x01,0x02,0x01,0xe7,0xe5,
+ 0x6b,0xe5,0x05,0x02,0x03,0xe5,0x77,0x02,0xe7,0xe5,0x73,0x03,0xe8,0x77,0x01,0xe8,
+ 0x78,0xe6,0xe5,0x78,0xe5,0x01,0xe5,0x7a,0xe8,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x09,0x09,0x0d,0xe5,0xe7,0x01,0x77,0xe8,0x77,0x01,0x02,0xe5,0x6f,0x0d,0x7a,
+ 0x01,0xe6,0x78,0xe5,0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x7a,0xe5,0xe5,0x79,
+ 0x01,0xe6,0x79,0x01,0x01,0x7e,0x7c,0xe6,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x02,0x05,0x04,0xe5,0x7b,0xe7,0x1e,0x29,0x08,0x25,0xe9,0x3e,0x3c,0x01,0x03,0xe5,
+ 0x39,0x3d,0xe7,0x3c,0x3b,0x02,0xe5,0x2f,0x0d,0x3b,0xe5,0xe6,0x3d,0x3a,0x01,0x01,
+ 0x3f,0x3c,0xe7,0x03,0x25,0xe6,0x10,0x1f,0xe6,0x1a,0xe5,0x2d,0x10,0x21,0x18,0xe5,
+ 0xe6,0x15,0x63,0xe6,0xe5,0x13,0x22,0x41,0xe7,0xe5,0x36,0x42,0x01,0x01,0x01,0x76,
+ 0xe5,0x01,0xe6,0x01,0x01,0x70,0x01,0x06,0x01,0xe5,0xe5,0x6f,0x04,0xe5,0x01,0x02,
+ 0x74,0x06,0xe5,0x0a,0x6e,0x01,0xe5,0xe6,0x06,0xe6,0x69,0x04,0x01,0x02,0x76,0xe9,
+ 0x79,0xe5,0xe7,0x7a,0x01,0x63,0x16,0xe9,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,
+ 0x09,0x09,0x04,0x01,0x06,0x02,0xe6,0x71,0x04,0x02,0x02,0xe5,0xe5,0x60,0x0b,0x0b,
+ 0xe5,0xe5,0x36,0x27,0x01,0x16,0x03,0x01,0x37,0xe5,0x25,0x01,0x01,0x16,0x01,0xe7,
+ 0x26,0x0e,0x27,0x01,0x03,0x14,0xe5,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x2d,0x08,0x2a,0x17,0xe6,0xe5,0x2d,0x08,0x2a,0x18,0xe5,0xe5,0x08,0x2d,0x08,0x39,
+ 0x02,0xe5,0x2d,0x08,0x2c,0x19,0xe5,0x12,0xe5,0x63,0x01,0xe6,0x05,0x0a,0x01,0x07,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x0a,0xe5,0xe6,0xe5,0x06,0x4a,0x0e,0x16,0xe9,0x32,0x09,0x13,
+ 0x13,0x12,0xe5,0x02,0x0a,0x33,0xe6,0x12,0x09,0x1b,0x01,0x01,0xe5,0x07,0x06,0x03,
+ 0x1a,0x1a,0x16,0x17,0x01,0x02,0x13,0x2b,0xe5,0x0e,0x2b,0x01,0xe5,0x0a,0x32,0x03,
+ 0x17,0x03,0xe6,0x16,0x02,0x01,0x26,0x02,0x01,0x07,0x0b,0x01,0xe6,0x04,0x15,0x01,
+ 0x18,0xe8,0x08,0x1e,0x02,0x13,0x3a,0x03,0x05,0x02,0x36,0x15,0xe5,0x06,0xe7,0x17,
+ 0xe5,0xe6,0x38,0x05,0x15,0x02,0x07,0x1a,0x02,0x02,0x13,0x16,0x2a,0x0e,0x03,0x12,
+ 0x19,0x04,0x0d,0x03,0x0b,0x2d,0xe5,0x11,0x19,0x20,0x2f,0x11,0x01,0x01,0x49,0x02,
+ 0xe6,0x0d,0x02,0xe5,0x04,0x0e,0x03,0x01,0x02,0x01,0x41,0x04,0x03,0xe5,0x0d,0x02,
+ 0x06,0x0b,0x01,0x03,0x02,0x01,0xe5,0xe5,0x22,0xe5,0x05,0x1a,0x10,0x01,0xe5,0xe5,
+ 0x01,0x04,0x02,0x08,0x04,0x01,0x01,0x02,0x48,0x10,0xe5,0xe5,0xe5,0x06,0xe6,0xe5,
+ 0xe6,0x05,0x02,0xe9,0x04,0x05,0x20,0x04,0x01,0x0c,0x01,0x07,0x0e,0x04,0x01,0xe5,
+ 0x05,0x02,0x03,0x01,0x06,0xe5,0xe5,0xe5,0xe6,0x07,0x23,0x01,0x02,0x0c,0x01,0x01,
+ 0x05,0x03,0x0f,0x01,0xe5,0x05,0x03,0x04,0x04,0x02,0xe8,0x01,0x3e,0x01,0x07,0x0d,
+ 0x02,0x01,0xe5,0xe5,0x06,0x05,0xe6,0x06,0xe7,0xe5,0x40,0x01,0x07,0x10,0x01,0xe5,
+ 0xe6,0x05,0x01,0xe5,0x02,0x0a,0x01,0xe6,0x1b,0x02,0x10,0x26,0x09,0x09,0x04,0x07,
+ 0x01,0xe7,0x01,0x1b,0xe5,0x13,0x23,0xe5,0x0b,0x09,0xe5,0x09,0x01,0xe5,0x0d,0x09,
+ 0x09,0x04,0x01,0x02,0x09,0x0b,0x09,0x09,0xe6,0x06,0xe5,0x02,0xe6,0x01,0xe5,0xe5,
+ 0xe5,0xe5,0x05,0x01,0x02,0x16,0x13,0x33,0x13,0x04,0x02,0xe5,0xe6,0xe5,0x10,0x14,
+ 0x32,0x14,0x0b,0xe6,0x16,0x01,0x11,0x01,0x24,0x05,0xe5,0x04,0x01,0xe5,0x05,0x01,
+ 0xe6,0x0d,0x01,0x16,0xe5,0xe6,0x0f,0x01,0xe5,0x29,0x05,0x01,0x07,0x01,0x0f,0xe8,
+ 0x15,0x01,0x11,0x01,0x2a,0x08,0x07,0x01,0x01,0x0c,0xe5,0xe6,0x03,0x10,0xe6,0xe5,
+ 0x04,0x09,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0x02,0x06,0x01,0xe5,0x06,0xe7,0xe5,
+ 0x02,0x01,0xe6,0xe5,0x04,0xe5,0x08,0x01,0x17,0x01,0x05,0x0b,0x01,0x0f,0x09,0x0b,
+ 0x04,0xe5,0x04,0x01,0x09,0x0f,0xe5,0xe5,0x16,0x01,0x06,0x0a,0x01,0x30,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x0d,0x01,0xe7,0x17,0x05,0x0b,0x01,0x0f,0x02,0x08,0x07,0x01,0x08,
+ 0x04,0x03,0x01,0x16,0x17,0x01,0x03,0xe5,0x0d,0x0d,0x15,0x08,0x01,0x01,0xe5,0xe5,
+ 0x03,0xe6,0x10,0xe6,0xe5,0x10,0x1c,0x03,0x18,0x13,0xe5,0xe5,0x05,0x14,0x11,0x01,
+ 0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x02,0x04,0x01,0x04,
+ 0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x03,0x03,0x01,0x0b,0xe7,0xe5,0x12,0x15,0x05,
+ 0x0a,0x10,0xe5,0x17,0x03,0xe5,0x0c,0x01,0xe7,0x48,0x03,0x0e,0x0c,0x03,0x01,0x08,
+ 0x04,0x05,0x02,0x0b,0x0b,0x09,0x08,0xe5,0x03,0x05,0x0b,0x01,0x02,0x0b,0x0e,0x01,
+ 0x0c,0x01,0xe6,0xe5,0x01,0x0f,0x02,0xe6,0x03,0x0e,0x03,0x18,0x0d,0x20,0xea,0x01,
+ 0x06,0x20,0x03,0x0f,0x05,0x21,0x14,0x01,0xe5,0x15,0x1f,0x07,0x09,0x1b,0x13,0x04,
+ 0xe5,0x06,0x04,0x0c,0x0a,0xe5,0x09,0x04,0x06,0xe6,0x24,0x03,0x01,0x0e,0x01,0xe6,
+ 0x0a,0x03,0x17,0xe5,0x15,0x11,0x11,0x09,0x0c,0x02,0xe6,0x06,0x02,0x0b,0xe6,0x17,
+ 0x09,0x02,0x07,0x12,0x04,0xe6,0x06,0xe5,0xe6,0x0c,0xe7,0x18,0x15,0xe5,0x0d,0x10,
+ 0x11,0x06,0x01,0x0e,0x01,0xe6,0x3c,0x06,0x03,0x22,0x0e,0x01,0xe6,0x09,0x04,0x58,
+ 0x11,0x02,0xe5,0x08,0x05,0x2a,0x01,0x1c,0x0f,0x10,0xe6,0xe5,0xe5,0x01,0x05,0xe5,
+ 0xe5,0x01,0xe5,0x01,0x01,0x03,0xe5,0x11,0x09,0x02,0xe5,0x06,0xe5,0x22,0x0e,0x01,
+ 0x03,0x02,0x06,0xe5,0x01,0xe6,0x21,0xe5,0xe5,0x2f,0x01,0xe5,0x0a,0x01,0x06,0x01,
+ 0xe5,0xe5,0x04,0x01,0xe5,0xe5,0xe5,0x08,0x1b,0x02,0x0a,0x23,0x06,0xe5,0x02,0x06,
+ 0x01,0xe5,0xe5,0x06,0x02,0x27,0x33,0x05,0xe5,0x05,0x02,0x02,0xe6,0x09,0x01,0x01,
+ 0x27,0x06,0x25,0x04,0x01,0x02,0x09,0xe5,0xe6,0xe8,0x09,0x01,0x01,0x02,0x01,0x1e,
+ 0x03,0x02,0xe6,0x29,0x01,0x01,0x09,0x02,0x03,0x02,0x0a,0x01,0x18,0x01,0x07,0x01,
+ 0x02,0x04,0x01,0x07,0x01,0x20,0x01,0x01,0x06,0x02,0x04,0x01,0xe5,0xe5,0x09,0x01,
+ 0x18,0x01,0x0a,0x12,0xe5,0x18,0x05,0x01,0x0e,0xe8,0xe5,0x10,0x02,0x24,0xe5,0x0b,
+ 0x07,0xe5,0x07,0x06,0x02,0xe5,0x04,0x02,0x02,0x06,0xe7,0xe5,0x13,0x3d,0x09,0x01,
+ 0x03,0xe5,0x01,0x05,0xe5,0x01,0xe5,0x0b,0xe5,0x0a,0x02,0x02,0xe6,0xe5,0x01,0x09,
+ 0x09,0x04,0x01,0x02,0x0b,0x09,0x03,0x05,0x05,0x03,0xe5,0x01,0x05,0xe6,0x03,0x06,
+ 0x01,0xe5,0xe5,0x0a,0xe5,0x08,0x27,0x32,0xe5,0x03,0x03,0x01,0xe5,0xe5,0x08,0x07,
+ 0x27,0x27,0x0b,0x0b,0xe5,0xe5,0x0c,0x01,0x04,0x04,0x1a,0xe5,0xe5,0x08,0x01,0x07,
+ 0x01,0x07,0x01,0x04,0x02,0x01,0xe5,0x05,0x01,0xe6,0x0f,0x02,0x0a,0x01,0xe5,0x05,
+ 0x02,0x1a,0x01,0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,
+ 0x01,0x01,0xe5,0xe7,0x0b,0xe5,0x01,0xe5,0x0a,0xe5,0xe5,0x08,0x03,0x13,0x05,0x03,
+ 0xe5,0x03,0x01,0x25,0x01,0xe5,0x07,0x04,0x03,0x0d,0x01,0x05,0xe6,0x04,0xe5,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x04,0x01,0xe5,0x01,0x01,0x05,0xe5,0x07,0xe5,0x06,0xe6,0x05,
+ 0xe5,0xe6,0xe5,0x04,0xe5,0x0a,0x09,0x05,0x09,0xe5,0x02,0x05,0xe5,0x07,0x08,0x05,
+ 0x05,0xe6,0x02,0x01,0x01,0x05,0x01,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01,
+ 0x0e,0xe8,0x03,0x08,0x01,0x07,0x02,0x05,0x14,0x05,0x05,0x09,0x01,0x07,0x01,0x06,
+ 0xe5,0xe6,0x04,0xe5,0xe5,0x0f,0xe6,0x08,0x03,0x01,0x09,0x03,0x01,0xe5,0x0c,0x08,
+ 0x05,0x02,0x02,0x05,0x09,0x04,0x05,0x06,0x01,0xe5,0x01,0x0e,0x03,0x04,0x08,0x01,
+ 0x07,0x02,0x02,0xe5,0x04,0x09,0x06,0x02,0x02,0x05,0x02,0x13,0x03,0x07,0xe6,0x01,
+ 0x01,0x02,0x0b,0x02,0xe6,0x02,0x08,0x01,0xe5,0x0c,0x19,0x0f,0x1a,0x05,0x01,0xe5,
+ 0x0b,0x01,0x01,0xe5,0x02,0x02,0x07,0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x04,0x04,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x02,0x02,
+ 0x01,0x0b,0x02,0x01,0x01,0x07,0x14,0x0c,0x01,0x05,0x07,0xe5,0x06,0x03,0x0c,0xe6,
+ 0x06,0xe6,0x13,0x01,0x02,0xe6,0x06,0x24,0xe5,0x01,0x02,0x04,0x02,0x12,0x01,0x02,
+ 0xe5,0xe5,0x06,0x08,0x07,0x08,0xe6,0xe6,0x08,0x14,0x01,0x07,0x01,0x0e,0x02,0xe7,
+ 0x0f,0x0f,0x19,0xe5,0xe6,0x03,0x08,0x06,0x10,0x0e,0xe5,0x03,0x08,0x01,0x1f,0xe6,
+ 0xe5,0x03,0x0a,0x02,0x01,0xe5,0x01,0x0c,0x16,0xe5,0x07,0xe5,0x03,0x05,0x01,0xe6,
+ 0x03,0x01,0x15,0x08,0x04,0x0e,0xe5,0xe6,0x11,0x01,0x02,0xe5,0x1b,0xe5,0x06,0x03,
+ 0x05,0x05,0x0b,0x1d,0xe7,0xe6,0x06,0x03,0x0d,0x0e,0x0b,0x01,0x01,0xe6,0x02,0x01,
+ 0xe7,0x05,0x1d,0x11,0x02,0x28,0x06,0x03,0x07,0xe5,0x01,0x0b,0x18,0x06,0x06,0x07,
+ 0x03,0xe5,0x1e,0x01,0x07,0x07,0x0c,0x07,0x02,0xe5,0xe5,0x02,0x02,0xe6,0x06,0x15,
+ 0x05,0x02,0xe5,0x1c,0x05,0x10,0x05,0x04,0x05,0x12,0x01,0x15,0x09,0x02,0xe5,0x0b,
+ 0x07,0x0e,0x04,0xe5,0x02,0x02,0x10,0x01,0xe5,0xe5,0xe5,0x0b,0xe6,0x01,0x01,0x1d,
+ 0xe6,0xe5,0xe5,0x0f,0x09,0x05,0xe6,0x06,0xe5,0x04,0x03,0x0b,0x0b,0x07,0xe5,0x03,
+ 0x0a,0x02,0x01,0x07,0x04,0xe8,0x11,0x01,0x0d,0x05,0x04,0x09,0x02,0x01,0x05,0x03,
+ 0xe5,0x0e,0x04,0x0e,0x03,0x0a,0xe5,0xe6,0x01,0x0e,0x06,0xe5,0xe5,0x0f,0x02,0x12,
+ 0x03,0x10,0x08,0xe6,0x10,0x02,0x03,0xe5,0xe5,0x03,0x01,0xe6,0x02,0x03,0x07,0x0b,
+ 0x07,0x01,0x12,0x02,0x09,0xe5,0x04,0x0a,0x08,0x05,0x0b,0xe5,0xe7,0x17,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x04,0x02,0x02,0xe5,0x06,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x04,0x17,
+ 0xe5,0x01,0xe5,0xe5,0x01,0x01,0x01,0x06,0xe5,0x0a,0x08,0xe5,0x05,0xe5,0x01,0x05,
+ 0xe6,0x09,0xe5,0x09,0x09,0x10,0x0b,0x01,0x02,0x01,0xe6,0x03,0x01,0x08,0x0e,0x01,
+ 0x0c,0x07,0x01,0x02,0x08,0x01,0x05,0x13,0x06,0x01,0xe5,0xe5,0x03,0x01,0x02,0x01,
+ 0x03,0x01,0xe5,0x0c,0x1d,0x05,0xe5,0x01,0x01,0x0b,0x09,0x1b,0x01,0x04,0x06,0x02,
+ 0x03,0x0f,0x06,0xe5,0xe5,0x09,0x08,0x06,0xe5,0xe6,0x04,0x02,0x08,0x03,0x03,0x01,
+ 0x0a,0x08,0xe5,0xe5,0x03,0xe6,0x04,0xe5,0x02,0xe5,0x01,0x02,0x07,0x03,0x03,0x01,
+ 0x01,0x01,0x07,0x01,0x05,0x03,0x03,0x01,0x01,0xe5,0x03,0xe5,0x03,0x01,0x03,0xe5,
+ 0x05,0x02,0x11,0xe7,0xe5,0xe5,0x01,0x01,0x01,0x02,0x06,0x01,0x0d,0x07,0x01,0x03,
+ 0xe5,0x0d,0x07,0x01,0x04,0xe6,0x01,0x07,0x15,0x09,0x01,0x0b,0x02,0xe5,0x01,0x0d,
+ 0x09,0x01,0x04,0x01,0x03,0x06,0x09,0x02,0x03,0x06,0x25,0x01,0x10,0xe6,0x08,0x1d,
+ 0x02,0x06,0x06,0x02,0x01,0xe5,0x11,0x02,0x10,0x02,0x06,0xe5,0x01,0xe5,0x03,0x04,
+ 0x0a,0x01,0x1b,0x09,0x01,0x13,0xe5,0x07,0x10,0xe5,0xe5,0x08,0x03,0x06,0x02,0xe5,
+ 0x07,0x05,0x09,0x06,0x02,0x02,0x02,0x03,0x03,0x05,0xe5,0x04,0x04,0x09,0x04,0xe6,
+ 0x01,0x04,0x01,0x02,0x03,0x05,0x03,0x02,0x06,0x01,0xe7,0x01,0x1a,0x02,0x13,0x08,
+ 0xe5,0x1e,0x09,0x06,0x0a,0x01,0xe6,0x1e,0x13,0x07,0x21,0x07,0x12,0x02,0xe7,0xe5,
+ 0x0a,0x01,0x15,0x05,0x01,0x07,0x01,0xe5,0x07,0x01,0x13,0x04,0x02,0x01,0x07,0x01,
+ 0x0f,0xe5,0xe5,0x0c,0x01,0xe5,0x16,0x02,0x01,0x01,0x04,0xe5,0xe5,0x05,0x02,0x01,
+ 0xe5,0x08,0x06,0x01,0xe5,0x05,0x01,0x01,0x01,0x02,0xe5,0xe6,0x0c,0xe5,0xe6,0x0c,
+ 0x01,0x0d,0x07,0x0c,0x04,0x09,0x01,0x13,0x09,0x07,0x01,0x0d,0xe6,0x01,0x0d,0x01,
+ 0x03,0xe7,0x05,0xe7,0x05,0xe6,0xe5,0x04,0xe8,0xe5,0x03,0xe6,0x01,0x01,0x03,0x02,
+ 0x06,0xe5,0xe6,0xe5,0x02,0xe8,0x06,0xe5,0x01,0x05,0xe5,0x07,0x02,0x13,0xe5,0xe5,
+ 0x02,0xe5,0xe5,0x05,0x04,0x01,0x01,0x04,0x02,0x01,0xe5,0x07,0x01,0xe5,0x08,0xe5,
+ 0x0e,0x01,0x07,0x01,0x0e,0xe5,0xe6,0x14,0xe5,0x06,0x01,0x07,0x01,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0x04,0x03,0x02,0x07,0x01,0x09,0xe5,0xe5,0x08,0x0e,0xe5,0x01,0xe5,
+ 0x0a,0x08,0x09,0x01,0x02,0x02,0x01,0x07,0x01,0xe6,0xe6,0x02,0xe5,0x01,0xe5,0xe6,
+ 0x03,0xe6,0xe5,0x02,0x01,0x07,0xe6,0x0a,0x01,0x0e,0xe8,0x13,0x05,0x03,0xe6,0x02,
+ 0x03,0x02,0x04,0xe5,0xe5,0xe5,0xe6,0x01,0x01,0xe5,0x01,0x01,0xe5,0x01,0xe5,0x01,
+ 0x01,0xe5,0x02,0x01,0x07,0xe6,0x04,0x06,0x0e,0x02,0xe5,0x01,0x07,0x16,0x0d,0xe5,
+ 0x03,0x02,0xe5,0x08,0xe5,0x05,0x02,0x10,0x02,0x06,0x02,0x0c,0xe6,0xe6,0x10,0x01,
+ 0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x04,0x04,0x01,
+ 0x02,0x01,0x01,0xe7,0x06,0x01,0x03,0x03,0x01,0x04,0x02,0x01,0xe5,0x0a,0xe6,0xe5,
+ 0x20,0xe5,0x07,0xe5,0x05,0x02,0x05,0x04,0xe5,0xe5,0x03,0x01,0x11,0x09,0x0e,0x05,
+ 0xe5,0x0a,0x07,0x0a,0x03,0x01,0x01,0x03,0x01,0x06,0xe5,0x01,0x0a,0x0e,0x13,0x12,
+ 0xe9,0x03,0x05,0x16,0x05,0x02,0x11,0x02,0x01,0x03,0x07,0x02,0x03,0x11,0x13,0x03,
+ 0xe5,0x0a,0xe7,0x03,0x0e,0x04,0x0b,0xe7,0xe5,0x05,0xe7,0x03,0x02,0x01,0x07,0x01,
+ 0x05,0x01,0xe5,0x16,0xe5,0x02,0xe5,0x35,0x08,0x01,0x03,0x05,0x01,0x08,0xe5,0x03,
+ 0x1e,0xe8,0x07,0x03,0x05,0x04,0xe5,0x02,0x02,0xe7,0x01,0x05,0xe5,0x02,0xe6,0x06,
+ 0x01,0xe6,0x02,0x0d,0x05,0x0f,0x11,0xe9,0x20,0x09,0x0c,0x06,0x01,0x01,0x02,0x0b,
+ 0x02,0x05,0x11,0x0c,0x02,0xe5,0x0b,0x16,0x02,0x03,0x02,0x05,0x0a,0xe5,0x03,0x01,
+ 0x0a,0x05,0xe6,0xe5,0x07,0x15,0x02,0xe5,0x0c,0xe5,0x15,0x02,0x07,0x03,0xe5,0x08,
+ 0x07,0x02,0x0b,0x02,0x15,0x0a,0xe6,0xe5,0x03,0x05,0x05,0x24,0x06,0xe5,0xe6,0x03,
+ 0x09,0x03,0x04,0x25,0x0e,0x05,0x02,0x01,0x02,0x07,0x02,0x0f,0x02,0x08,0x04,0x02,
+ 0x01,0x04,0xe5,0x03,0xe5,0x20,0xe7,0x08,0x0f,0x01,0x0d,0x01,0x01,0x03,0x04,0xe5,
+ 0xe5,0x01,0x03,0xe5,0xe5,0x08,0x09,0x23,0x01,0xe5,0x01,0x15,0x1d,0x04,0x05,0x0a,
+ 0x03,0x06,0x22,0xe6,0xe5,0x0c,0x09,0x09,0x18,0xe6,0x03,0x02,0xe6,0xe5,0xe5,0x02,
+ 0x03,0xe5,0x05,0x07,0xe6,0x06,0x01,0x08,0xe5,0xe5,0x01,0xe5,0x03,0x08,0x09,0xe5,
+ 0x07,0xe5,0x17,0xe5,0x03,0x05,0xe5,0x06,0x01,0xe5,0x0e,0x05,0xe5,0x02,0x06,0x01,
+ 0x02,0xe5,0xe6,0x03,0x08,0x05,0xe5,0x03,0x04,0xe5,0x02,0x03,0xe5,0x08,0x01,0x02,
+ 0x04,0x01,0x02,0x01,0x01,0xe5,0xe6,0xe5,0x0b,0x12,0x04,0xe5,0x02,0x01,0x02,0x01,
+ 0x01,0x02,0x0a,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0x02,0x06,0x04,0x01,0x07,
+ 0x0a,0x01,0x10,0x0d,0x03,0xe8,0x04,0x05,0xe5,0x08,0x01,0x06,0x02,0x03,0x01,0xe6,
+ 0xe6,0xe6,0xe6,0x04,0x02,0xe5,0x01,0x01,0x11,0x04,0x10,0x06,0x05,0xe6,0x01,0xe5,
+ 0x01,0x07,0xe7,0x02,0x05,0x01,0x01,0x01,0x01,0xe6,0x05,0x01,0xe5,0x01,0x05,0x05,
+ 0x01,0xe6,0x01,0x01,0x01,0x09,0x07,0x04,0x01,0x0a,0x03,0x03,0xe5,0x03,0x02,0xe5,
+ 0x01,0xe5,0x0b,0x09,0x01,0x09,0x07,0x01,0x02,0x01,0xe5,0x02,0x09,0x01,0x07,0x06,
+ 0x01,0xe5,0x02,0x02,0x0e,0x05,0x05,0x02,0x02,0xe5,0x0c,0x09,0x01,0x07,0x09,0x01,
+ 0xe6,0x01,0xe5,0xe5,0x0a,0x01,0x07,0x05,0xe5,0x03,0x03,0xe6,0x0a,0x05,0xe5,0x08,
+ 0x03,0xe5,0x07,0x13,0x09,0xe5,0x04,0x04,0x04,0x02,0x0b,0x09,0x09,0x02,0x1a,0xe9,
+ 0x0b,0x13,0x04,0x0a,0x01,0xe5,0x07,0xe6,0x08,0xe6,0x06,0xe6,0x03,0x20,0x01,0xe7,
+ 0x0d,0x09,0x09,0x06,0x02,0xe5,0x07,0x06,0x04,0x09,0x04,0x01,0x02,0xe5,0xe5,0x05,
+ 0x09,0x0d,0x04,0x27,0x0c,0x08,0xe5,0x0a,0x09,0x1d,0x08,0x01,0xe5,0xe5,0x2e,0x0b,
+ 0x09,0x0b,0x1b,0x08,0x01,0x01,0x01,0x1e,0x0c,0x01,0xe5,0x05,0x01,0xe5,0x07,0x01,
+ 0x06,0xe5,0xe5,0x08,0x01,0x16,0x01,0x09,0xe6,0x19,0x0a,0x01,0x03,0x01,0x01,0x02,
+ 0x01,0xe5,0xe7,0x06,0x01,0xe5,0x05,0x01,0xe5,0x08,0xe5,0xe5,0x1e,0x01,0xe6,0x07,
+ 0x0c,0xe5,0x05,0x08,0x03,0x01,0x09,0x06,0x02,0x01,0x07,0x01,0x04,0x01,0x04,0x1f,
+ 0x03,0xe6,0x12,0xe7,0x06,0x09,0xe6,0xe5,0x03,0xe7,0xe5,0x02,0xe5,0xe5,0x01,0x01,
+ 0x04,0xe7,0xe5,0x02,0xe7,0x05,0x02,0x08,0xe5,0x07,0xe5,0x06,0xe8,0x0f,0x03,0x01,
+ 0x08,0x01,0x01,0x06,0x03,0xe5,0x02,0xe6,0xe6,0x09,0xe5,0x04,0xe5,0xe5,0x09,0x22,
+ 0xe5,0xe5,0x0f,0x04,0xe5,0x08,0xe5,0xe5,0x04,0xe5,0x06,0x01,0xe5,0xe6,0x04,0x02,
+ 0x01,0x04,0xe7,0xe5,0x03,0xe6,0x02,0x05,0x1b,0x01,0x01,0x15,0x01,0x07,0x09,0x09,
+ 0x01,0x01,0x03,0xe7,0xe6,0xe6,0x03,0x03,0x03,0x01,0xe5,0x05,0x01,0xe5,0x1a,0xe5,
+ 0x01,0x10,0x02,0x03,0x05,0xe5,0x06,0xe6,0x01,0x02,0x01,0xe6,0x01,0x01,0xe5,0xe7,
+ 0x03,0x01,0xe5,0x01,0xe5,0x01,0x01,0xe5,0x02,0x07,0xe6,0x1c,0xe5,0x01,0x0d,0x01,
+ 0xe5,0x05,0x02,0x09,0x07,0x01,0x12,0x01,0xe5,0x05,0xe5,0xe5,0x1d,0x0b,0xe5,0xe5,
+ 0xe5,0x08,0xe5,0x02,0x02,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,
+ 0x01,0x02,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x0b,0x02,
+ 0x0b,0x09,0x01,0x09,0x0f,0x05,0xe5,0x09,0xe5,0x06,0x03,0x08,0x08,0x15,0x03,0x01,
+ 0xe5,0x06,0x15,0x17,0x07,0x02,0x02,0x09,0xe5,0x0d,0x01,0x05,0x12,0x03,0xe5,0x02,
+ 0x0f,0xe5,0x05,0x0b,0xe5,0x05,0x06,0x08,0x03,0x15,0x0e,0x04,0x08,0x04,0x01,0xe6,
+ 0x08,0x12,0x03,0x01,0x07,0x01,0x04,0x02,0x01,0xe5,0x07,0xe7,0x0e,0xe7,0x03,0x12,
+ 0xe5,0x07,0x01,0xe5,0xe5,0x0a,0x05,0x0d,0x01,0x01,0x08,0x01,0x07,0xe5,0x06,0xe5,
+ 0xe5,0x02,0x0e,0x27,0xe6,0x07,0x09,0x04,0xe5,0x02,0xe5,0x0c,0xe5,0x01,0x0a,0x03,
+ 0xe5,0x01,0x04,0x0a,0x03,0x05,0x11,0x09,0xe5,0x02,0x24,0x16,0x03,0x02,0x01,0x0a,
+ 0x05,0x01,0x1d,0x05,0xe5,0xe5,0x02,0x22,0x09,0x0e,0xe5,0x03,0x03,0x06,0x07,0x21,
+ 0xe5,0x01,0x08,0x0f,0x0e,0x0b,0x0a,0xe5,0x04,0x02,0x01,0x09,0x03,0x19,0x01,0x06,
+ 0x02,0x13,0x04,0x19,0xe5,0x04,0x02,0x02,0x19,0x1b,0x05,0xe7,0x04,0x22,0x12,0x09,
+ 0xe5,0x05,0x0e,0x21,0x06,0x03,0x1a,0x1d,0x03,0x05,0x01,0xe5,0x11,0x04,0x13,0x01,
+ 0x05,0x0b,0x13,0x1c,0x08,0x01,0x26,0x05,0xe6,0xe5,0xe5,0x17,0xe6,0xe5,0xe5,0x02,
+ 0xe5,0x15,0x01,0x05,0xe5,0x01,0xe5,0x03,0xe5,0x0e,0x05,0xe5,0x01,0x02,0xe5,0x09,
+ 0xe8,0xe5,0x01,0x01,0x15,0x02,0xe5,0x01,0xe5,0x01,0x02,0xe5,0x10,0xe5,0x03,0xe5,
+ 0x11,0xe5,0x07,0x06,0x01,0xe5,0x0a,0x01,0x02,0xe5,0x01,0x04,0x05,0xe5,0xe5,0xe5,
+ 0x12,0x1d,0x01,0x01,0x01,0xe5,0x03,0x01,0x05,0x01,0x07,0x09,0x03,0x07,0x08,0x02,
+ 0x0a,0x01,0x11,0x1f,0x01,0x09,0x07,0x01,0x07,0x09,0x0d,0x03,0x02,0xe5,0x08,0x01,
+ 0x0a,0x01,0x09,0x06,0xe5,0xe5,0x12,0x01,0x03,0x02,0xe5,0xe6,0x05,0x01,0x06,0xe5,
+ 0x08,0x0a,0x06,0x01,0xe5,0x01,0x06,0x02,0x04,0x05,0x01,0x01,0x05,0x03,0x03,0xe6,
+ 0xe5,0xe5,0x10,0x03,0x05,0x01,0x07,0x01,0x01,0x02,0xe7,0x02,0x05,0x03,0x06,0x02,
+ 0x02,0x01,0x01,0xe5,0x0b,0x01,0x07,0x01,0x04,0x04,0x05,0x01,0x01,0x13,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x06,0x02,0x0a,0x04,0x02,0xe6,0x0c,0x01,0x07,0x01,0x04,0xe5,
+ 0xe5,0x08,0x01,0x13,0x01,0x07,0x01,0x07,0x01,0x07,0x05,0xe6,0xe5,0x0f,0xe5,0xe7,
+ 0x07,0xe5,0x13,0x2e,0x02,0x02,0x06,0x22,0x02,0x4f,0x09,0x01,0x1b,0xe5,0x01,0xe5,
+ 0x0a,0x02,0x09,0x06,0x02,0x09,0x09,0x04,0x01,0x04,0x02,0x01,0x01,0x02,0x04,0xe6,
+ 0x01,0x03,0x05,0x09,0x0d,0xe5,0xe7,0x01,0x06,0x02,0x12,0xe5,0x1c,0x0b,0x2c,0x04,
+ 0xe6,0x08,0x13,0x1d,0x0b,0x32,0x01,0x01,0x0f,0x10,0x02,0x1f,0x07,0x01,0xe5,0x05,
+ 0x01,0x04,0x1d,0xe5,0x01,0x0d,0x02,0x10,0x02,0x19,0x02,0x02,0x06,0x01,0xe5,0x04,
+ 0xe5,0xe6,0x24,0x0f,0x04,0x0e,0x18,0x01,0x04,0x07,0x01,0x09,0x21,0xe5,0x01,0xe5,
+ 0x0c,0x05,0xe5,0xe5,0x07,0xe6,0x04,0xe5,0xe5,0x06,0xe6,0x07,0xe5,0x01,0x05,0x02,
+ 0xe5,0x04,0x02,0xe5,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe6,0xe6,0x0e,0x03,0xe5,
+ 0x04,0xe5,0x06,0x1d,0x01,0xe6,0x04,0x01,0x07,0x01,0x0a,0xe5,0x15,0xe5,0x01,0x0d,
+ 0x08,0x0a,0x05,0x02,0x09,0x0c,0x08,0xe5,0xe5,0x06,0x01,0x22,0x03,0x0f,0x05,0xe5,
+ 0x0b,0x04,0xe6,0x06,0x01,0x0c,0x01,0x03,0x01,0xe6,0xe5,0x02,0x01,0x01,0x01,0x22,
+ 0xe6,0xe5,0x0c,0x06,0x05,0x06,0x02,0x02,0x06,0x03,0x0e,0x02,0x02,0xe5,0x01,0x01,
+ 0x07,0x01,0x0a,0x1a,0xe5,0x40,0xe5,0xe5,0x19,0x01,0xe5,0x05,0x01,0xe5,0x0b,0x01,
+ 0x01,0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0xe5,0x04,
+ 0xe7,0x06,0x01,0x03,0x03,0x01,0x07,0x01,0x0b,0x01,0xe5,0x22,0x0d,0x01,0xe5,0x08,
+ 0x03,0x07,0x02,0xe5,0x18,0x01,0x0a,0x05,0xe8,0x0a,0x16,0xe5,0x21,0xe5,0x01,0x26,
+ 0x06,0x01,0x01,0xe5,0x30,0x06,0x03,0x02,0x0d,0x0b,0x24,0xe5,0x03,0x2c,0x05,0x06,
+ 0x03,0x04,0x02,0xe5,0x01,0x05,0x01,0x18,0x09,0xe8,0x04,0x05,0x07,0x0b,0x1f,0xe5,
+ 0x0f,0x06,0x03,0x1b,0x01,0x03,0xe5,0xe5,0x19,0x07,0x0b,0x09,0x03,0xe6,0x07,0x04,
+ 0x03,0x01,0x24,0x03,0x01,0x03,0x1a,0x17,0x06,0x12,0x1c,0x0a,0xe6,0xe5,0x05,0x0e,
+ 0x06,0x01,0x07,0x09,0x0d,0xe5,0x10,0x16,0x12,0xe7,0x12,0x02,0x09,0x09,0x08,0xe5,
+ 0x09,0xe5,0x08,0x04,0x2c,0xe6,0x27,0x13,0xe5,0xe6,0x05,0x33,0x02,0x09,0x01,0x05,
+ 0x01,0x09,0xe5,0x07,0x1b,0x02,0x06,0x09,0x22,0xe8,0x31,0x10,0x08,0xe5,0x07,0xe5,
+ 0x05,0x0e,0x0b,0xe5,0xe7,0x07,0x15,0x10,0x0e,0x02,0xe5,0x09,0x09,0x17,0x0a,0xe5,
+ 0x01,0xe6,0x48,0x09,0x22,0xe5,0x01,0xe6,0x01,0x01,0x46,0xe6,0x01,0x04,0x1f,0x01,
+ 0x02,0x03,0x04,0x43,0x01,0x02,0x04,0x01,0x02,0x0e,0xe5,0xe5,0xe5,0x08,0x04,0x02,
+ 0xe5,0x01,0x45,0x04,0x09,0x0e,0x02,0x01,0x0b,0x02,0xe6,0xe5,0x48,0x01,0x01,0x07,
+ 0x11,0x14,0x01,0x02,0x48,0x01,0x01,0x05,0x03,0x13,0x09,0x02,0x02,0xe6,0x4b,0x09,
+ 0x04,0x0c,0x01,0x08,0x04,0xe6,0x01,0x31,0xe5,0x19,0x09,0x05,0x0b,0x01,0x10,0xe6,
+ 0x08,0x47,0x02,0x06,0x02,0x15,0x06,0xe7,0x09,0x01,0x45,0xe5,0x07,0x1d,0x03,0xe5,
+ 0x07,0x05,0x09,0x09,0x09,0x09,0x0b,0x04,0x01,0x02,0x09,0x05,0x03,0x09,0x0d,0x01,
+ 0xe7,0x01,0x47,0x09,0x22,0x04,0xe6,0x46,0x09,0x28,0xe5,0xe6,0x42,0x06,0x02,0x07,
+ 0x01,0x20,0x03,0x01,0x43,0xe5,0x08,0x08,0xe5,0x20,0x03,0xe5,0x41,0x06,0x07,0x02,
+ 0x28,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x05,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x2d,0xe5,0x12,0x13,0xe6,
+ 0x1f,0x02,0xe5,0x42,0x11,0x01,0x22,0xe5,0x01,0x43,0x13,0x21,0xe7,0xe5,0x2d,0x14,
+ 0x11,0x02,0x1c,0xe5,0x03,0x02,0x4b,0x01,0xe5,0x05,0x23,0xe7,0xe5,0x10,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0xe6,0x06,0x01,0x09,0x01,0x02,0xe5,0x02,0x01,0x04,0x02,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0x03,0xe5,0x06,0x2f,0x2e,0x1c,0x02,0xe5,0x1e,0x28,0x1e,
+ 0x10,0xe6,0xe6,0x1a,0x14,0x0e,0x09,0xe5,0x2a,0x03,0x02,0xe6,0x08,0x14,0x19,0x05,
+ 0x07,0x03,0xe6,0x06,0x06,0x17,0x06,0xe7,0x3e,0x0b,0x0b,0x22,0xe9,0x07,0x09,0x09,
+ 0x10,0x09,0x04,0x01,0x04,0xe6,0x27,0x0a,0x02,0xe5,0x29,0x14,0x0a,0x2a,0x04,0x02,
+ 0xe5,0x0a,0x12,0x20,0x3a,0xe5,0xe6,0x0a,0x07,0x10,0x18,0x01,0x05,0x0b,0x08,0x19,
+ 0x06,0xe5,0xe5,0x1b,0x13,0x0e,0xe5,0x0d,0x09,0x21,0x02,0x32,0x1c,0x2a,0x01,0x01,
+ 0x0a,0x2f,0x15,0x0b,0x1c,0xe5,0xe7,0x09,0x27,0x41,0x06,0xe9,0x4f,0xe5,0xe5,0x02,
+ 0xe5,0x1c,0xe5,0x01,0x01,0x02,0x01,0x4c,0xe5,0x21,0x01,0x03,0xe5,0xe5,0x03,0x0e,
+ 0xe5,0x01,0x01,0x17,0xe5,0x01,0x01,0x1d,0x03,0x1b,0x05,0x01,0xe5,0x01,0x11,0xe5,
+ 0xe5,0xe5,0x17,0xe5,0xe5,0xe5,0x3e,0x02,0xe8,0x54,0x04,0x03,0x1c,0x02,0x02,0x18,
+ 0x1d,0x20,0x01,0xe6,0x17,0x03,0x01,0xe6,0x15,0x01,0x1b,0x01,0x1d,0x23,0xe5,0x01,
+ 0xe5,0x16,0x01,0x1b,0x01,0x22,0x1f,0x03,0x09,0x02,0x4e,0x1e,0xe8,0xe5,0x59,0x01,
+ 0x1d,0xe7,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x03,0x05,0x09,0x0d,0x01,0x01,
+ 0xe5,0x01,0x74,0x04,0xe6,0x7a,0xe5,0xe5,0x79,0xe5,0xe6,0x53,0x03,0xe5,0x1f,0xe9,
+ 0x53,0x01,0x21,0xe5,0x01,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0x02,0x55,
+ 0x01,0x26,0x55,0x01,0x22,0x03,0x40,0x14,0x01,0x23,0x02,0x04,0x50,0x01,0x02,0x22,
+ 0xe5,0x01,0x0e,0x43,0x1b,0x0b,0xe5,0x02,0xe5,0x0b,0x01,0x07,0x01,0x07,0x01,0xe5,
+ 0x05,0x01,0x07,0x01,0x04,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,
+ 0x06,0x01,0x02,0x05,0x04,0xe5,0x53,0x01,0x27,0xe5,0x72,0x04,0xe7,0xe5,0x2f,0x0e,
+ 0xe5,0x11,0x0a,0x09,0x11,0x03,0xe5,0x1b,0x1b,0x1b,0x01,0x01,0x14,0x0e,0xe5,0x1c,
+ 0x13,0x07,0x05,0xe5,0x16,0x15,0x0b,0xe5,0x01,0xe5,0x0c,0xe5,0xe5,0x17,0x02,0x0a,
+ 0x06,0xe5,0x05,0x0d,0x1a,0x0a,0x01,0xe5,0x12,0x17,0xe5,0x11,0x0f,0x17,0x12,0x01,
+ 0xe6,0x1b,0x10,0x11,0x19,0x20,0xe5,0x01,0x1e,0x20,0x3e,0x3f,0x24,0x19,0x02,0x0a,
+ 0x01,0x30,0xe5,0xe5,0x28,0x0d,0xe5,0xe5,0x0e,0x33,0x2c,0x08,0x02,0xe6,0x0e,0x17,
+ 0x1a,0x37,0xe5,0xe6,0x02,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x06,
+ 0xe8,0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x0b,0xe6,0xe6,0x0f,0x09,0x09,0x07,
+ 0x01,0x09,0x09,0x01,0x05,0x01,0x01,0x07,0x01,0x09,0x07,0x01,0x01,0x0b,0xe6,0xe5,
+ 0x0e,0x0a,0x03,0x04,0xe5,0x07,0x0a,0x07,0x02,0x01,0x02,0x04,0x09,0x05,0xe5,0x01,
+ 0x04,0x04,0x10,0x01,0x11,0x4b,0x1c,0xe6,0xe5,0x18,0x09,0x04,0x06,0x07,0x01,0x09,
+ 0x09,0x09,0x09,0x09,0x02,0x0b,0x02,0xe5,0x0c,0xe6,0x05,0xe6,0x01,0x05,0xe5,0x07,
+ 0xe6,0x06,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x06,0x04,
+ 0x03,0x02,0x03,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x01,0x05,0x03,0x09,0x09,0x09,
+ 0x09,0x11,0x02,0x0e,0xe5,0x07,0x09,0x09,0xe5,0x07,0x0b,0x02,0x06,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0e,0xe5,0x0d,0x09,0x09,0x09,0x09,0x0b,
+ 0x09,0x09,0x09,0x09,0x0f,0xe5,0x01,0x12,0x06,0x09,0xe5,0x11,0x05,0x05,0xe5,0x37,
+ 0xe5,0x0d,0x06,0x02,0x09,0x09,0x09,0x08,0x02,0x09,0x09,0x09,0x09,0x0f,0xe8,0x3e,
+ 0x1d,0x20,0x10,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x0d,0x02,0xe5,0x03,
+ 0x04,0x1f,0x33,0x20,0x3f,0x3b,0xe5,0xe5,0x17,0x1d,0x08,0x02,0x33,0x05,0xe6,0x03,
+ 0x13,0x06,0x02,0x13,0x06,0x0b,0x16,0x06,0x13,0x01,0xe5,0x03,0x4c,0x0c,0x1b,0xe5,
+ 0x01,0x17,0x08,0x14,0x08,0xe5,0x1e,0x13,0x06,0x01,0xe6,0x20,0x1d,0x34,0x06,0xe5,
+ 0xe5,0x48,0x15,0x07,0x12,0xe8,0x13,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04,
+ 0xe6,0x08,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe6,0x06,0x09,0xe8,0x0d,0xe5,0x06,0xe6,
+ 0x05,0xe7,0x08,0x07,0xe6,0x05,0xe5,0x01,0xe5,0x05,0x02,0x09,0x07,0xe6,0x05,0x02,
+ 0x0e,0xe8,0x25,0x18,0x3b,0x01,0xe5,0x14,0x05,0x03,0x09,0x01,0x07,0x05,0x03,0x07,
+ 0x03,0x01,0x03,0x05,0x03,0x0d,0x01,0x03,0x0c,0x01,0xe6,0x0a,0x03,0x02,0x01,0x06,
+ 0xe5,0x07,0x02,0x03,0x03,0x01,0x07,0x08,0x0b,0x04,0x05,0x03,0x0e,0x04,0xe9,0x03,
+ 0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,
diff --git a/u-boot/board/esd/cpci405/fpgadata_cpci4052.c b/u-boot/board/esd/cpci405/fpgadata_cpci4052.c
new file mode 100644
index 0000000..7204028
--- /dev/null
+++ b/u-boot/board/esd/cpci405/fpgadata_cpci4052.c
@@ -0,0 +1,765 @@
+  0x1f,0x8b,0x08,0x08,0xe9,0xf4,0x75,0x3e,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30,
+  0x35,0x5f,0x32,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xed,0x7c,0x0f,0x74,0x14,
+  0xd7,0x79,0xef,0x37,0x77,0x66,0xc5,0x68,0x77,0xa5,0x1d,0xad,0x56,0xce,0xda,0x16,
+  0xf2,0x68,0x25,0xc8,0xa2,0xae,0xc4,0xb2,0xc2,0x58,0x96,0xc5,0x6a,0xb4,0x92,0xe9,
+  0xda,0xe0,0xb0,0x26,0x6e,0xc3,0x6b,0xfd,0x92,0xc5,0x26,0xad,0xfa,0x0e,0x71,0x85,
+  0xd3,0xe6,0xa9,0x6e,0x5f,0xdf,0xd5,0x6a,0x31,0x02,0x61,0x58,0xff,0x69,0xa3,0xb8,
+  0x24,0x59,0x88,0xda,0x28,0x2e,0xc9,0x5b,0x04,0x01,0x61,0x1c,0x7b,0x50,0x65,0x2c,
+  0x40,0x06,0x85,0xfa,0xbc,0x87,0x6d,0x6a,0x2f,0x8e,0xea,0xa7,0x60,0x99,0xca,0x40,
+  0x1d,0xf1,0xcf,0x7a,0xdf,0x9d,0x7f,0xbb,0x22,0x89,0xdb,0xd3,0xd7,0x73,0xfa,0xce,
+  0x79,0x9e,0xc4,0xc7,0xd7,0xba,0xba,0x33,0xf7,0x7e,0xf3,0xdd,0xdf,0xf7,0xfb,0x7d,
+  0xdf,0x1d,0x41,0xa1,0x6b,0x5a,0xff,0x1f,0x00,0xb7,0x0e,0x4a,0x1e,0xed,0x78,0xf4,
+  0x0f,0x96,0x06,0xef,0xfc,0x4a,0xe8,0x2b,0xc1,0xa5,0x75,0x8f,0x3d,0xba,0x1e,0x1e,
+  0x01,0x7b,0xe8,0xeb,0x4b,0xee,0xfc,0xa3,0x8d,0x4b,0x96,0x2e,0x85,0x47,0xc1,0x11,
+  0x0a,0x06,0xeb,0x17,0xe3,0xff,0x97,0xdc,0x05,0xeb,0xa1,0x70,0xc9,0x5d,0x8d,0x4b,
+  0x96,0x35,0x2e,0x0d,0xc2,0x57,0x01,0xe2,0x3d,0xb3,0x78,0xbd,0xf0,0xad,0xdf,0xfa,
+  0xbd,0x20,0x50,0x0e,0x00,0xe6,0x05,0xb9,0x38,0xfb,0x77,0x41,0x90,0x93,0x39,0xa0,
+  0xcd,0xb5,0x41,0x50,0xd9,0x7f,0x83,0xd1,0x5f,0x18,0x04,0x39,0xff,0xbf,0xb9,0x20,
+  0x28,0x10,0x03,0xcf,0xd7,0xc0,0x1d,0x84,0x9b,0x2e,0x0e,0x04,0xaa,0xb7,0x3e,0xad,
+  0x8f,0xdc,0xdc,0xc5,0xae,0x7f,0x45,0x9f,0xfb,0x57,0x74,0x09,0xff,0xd6,0x3e,0xfd,
+  0x5f,0xb3,0x6e,0xf0,0xe0,0xcc,0x38,0x6d,0x45,0x60,0x63,0x0d,0xa9,0x79,0x44,0x1f,
+  0xa7,0xda,0x2e,0xc1,0x58,0x72,0x99,0xbc,0x6a,0x0b,0xa9,0x22,0x63,0xea,0x37,0x82,
+  0xae,0x3e,0x3e,0x08,0x1d,0xfa,0x8c,0xa4,0xf7,0x68,0xcf,0x80,0xcf,0x27,0x8a,0xa4,
+  0x1a,0x7a,0x40,0xa6,0x8e,0xe7,0x13,0x69,0xd0,0xd7,0xdc,0x63,0x9b,0xa4,0xbb,0x64,
+  0x19,0x44,0x72,0x9b,0xd8,0xd5,0x93,0x96,0xa3,0x0e,0x42,0x7c,0x9c,0x3e,0x4e,0x2d,
+  0x19,0x20,0x3f,0x00,0xec,0x03,0xe2,0xe4,0x7a,0x38,0x9f,0xea,0xa0,0x24,0x23,0xc4,
+  0xf5,0xc9,0x94,0xa9,0x70,0x1e,0x0e,0xa8,0x81,0xdd,0xbc,0x0c,0xc3,0x64,0x19,0xb8,
+  0x32,0xbc,0x24,0xe8,0xe3,0xb2,0x5c,0x1a,0xde,0x81,0x57,0x54,0x57,0x96,0xbf,0x0c,
+  0x7f,0x0e,0x77,0x50,0xd7,0x34,0x3f,0x03,0xfa,0x38,0x45,0x1a,0x80,0x13,0x10,0xca,
+  0x16,0x0d,0xf0,0x7e,0xbc,0x41,0x48,0x71,0xa6,0x71,0x9c,0xac,0xf5,0x8d,0xda,0xfc,
+  0xf0,0x1b,0x31,0x5f,0x56,0x1c,0x20,0x01,0x38,0x2f,0xf8,0x54,0x31,0xcd,0x3f,0x8e,
+  0xef,0x4f,0xbb,0xa7,0xad,0x0d,0x7a,0x14,0x19,0x0a,0x25,0x02,0xb6,0x5d,0xd0,0xce,
+  0x89,0x29,0x32,0x84,0x76,0x60,0x97,0xcc,0x2d,0xa3,0x7b,0xd2,0x95,0xd5,0xe2,0xef,
+  0x92,0x5b,0x1e,0xfa,0x21,0xad,0x4c,0x8b,0x6b,0xc9,0x5a,0x63,0x5c,0x34,0xea,0x4a,
+  0x1d,0x49,0xef,0x5e,0x54,0x74,0x9b,0xc3,0x4e,0xcf,0xa5,0x83,0x71,0x67,0x0f,0x6f,
+  0x9a,0x58,0x99,0xbf,0x47,0xf9,0x67,0x29,0x0c,0xae,0xf1,0xd6,0xeb,0xb0,0x44,0x6a,
+  0x3e,0xb6,0x78,0xb4,0x7e,0xbc,0x40,0x9f,0xe7,0x80,0x6d,0x02,0x8e,0xc3,0x8b,0xaa,
+  0x33,0xc3,0xfb,0xe0,0x44,0x32,0x24,0x07,0x32,0x55,0x35,0x86,0x3d,0xa3,0x25,0xcf,
+  0x09,0x4f,0x42,0xa5,0x2a,0x4e,0x47,0x96,0xc2,0x66,0xa8,0xa2,0xe2,0x34,0x71,0x1b,
+  0x76,0x51,0xe1,0x3b,0xf0,0x4d,0xba,0x28,0xdb,0xde,0x59,0xf0,0xbc,0x63,0x33,0xad,
+  0x8c,0x17,0xb6,0x93,0x0e,0xd0,0xd7,0x17,0xf5,0x4c,0x91,0xc3,0xd4,0x77,0x56,0xbc,
+  0xbb,0xc0,0x09,0xdd,0x20,0xab,0x85,0x7e,0xfb,0x1a,0x41,0x7f,0x0f,0x93,0x65,0x93,
+  0xf0,0xd6,0xae,0xc6,0xcc,0xb6,0xf4,0x3c,0xbf,0x70,0x9c,0x84,0x68,0xd1,0x0b,0xfc,
+  0x13,0xc6,0x3d,0xa3,0x90,0x26,0x3d,0x80,0xf3,0xa4,0x8e,0x2c,0xcc,0x60,0xa3,0x58,
+  0xe5,0x9f,0x31,0xde,0x9f,0x28,0x4d,0x90,0x63,0x74,0x50,0x81,0x14,0x59,0x0f,0x3f,
+  0x87,0x70,0xcb,0xbc,0xa7,0x79,0x62,0xdc,0x93,0x0a,0xeb,0x61,0x0b,0xec,0x8e,0x89,
+  0xcf,0xe1,0x7b,0x3f,0x24,0xd4,0x29,0x8e,0x9d,0x44,0x06,0x49,0xeb,0xf3,0xda,0x96,
+  0x92,0xa7,0xe4,0x2a,0xc5,0x1e,0xb3,0xef,0x17,0x7f,0x02,0x8b,0x15,0x47,0xac,0xa0,
+  0xc0,0xb0,0x99,0x28,0x78,0x60,0x13,0x54,0xc6,0xed,0x6b,0x89,0x07,0x7e,0x0c,0xb5,
+  0xca,0xed,0x6b,0x09,0xe1,0x74,0x9b,0x0d,0x15,0x1d,0x51,0xd4,0x35,0x41,0x4f,0xdd,
+  0x26,0x7e,0x57,0x5b,0x76,0x4d,0xd8,0xe3,0x7a,0xd5,0x51,0xc7,0xeb,0x76,0xe9,0x9b,
+  0x3f,0x51,0x70,0x05,0xc2,0x4a,0x51,0x6a,0xe5,0x7a,0x60,0x8d,0x95,0x29,0xfe,0xfd,
+  0x82,0x0e,0xe3,0x79,0x97,0xe1,0x86,0x50,0xaf,0xdc,0x31,0xce,0x57,0xc3,0x35,0x21,
+  0xac,0xb8,0xc6,0xf9,0x85,0x86,0x3d,0x1b,0xa4,0x6c,0x72,0x08,0x88,0x28,0x26,0x88,
+  0x4c,0x87,0xe4,0x3a,0xd1,0xb1,0x9b,0x6c,0x37,0xd6,0x20,0xda,0x46,0xe4,0xbd,0x7e,
+  0x39,0x62,0x97,0x12,0x82,0xbc,0x57,0x0c,0x3c,0xe2,0x90,0x12,0xc4,0xf0,0x4f,0x6f,
+  0x59,0xbf,0x77,0xaf,0x22,0x2b,0xd1,0x4c,0xc1,0x42,0xe9,0x10,0x14,0x2b,0x0e,0x89,
+  0x3c,0x69,0xd8,0x2c,0x2d,0xf5,0xe3,0x14,0x7c,0x8a,0x2b,0xe5,0xa8,0x16,0xaf,0x10,
+  0x7c,0xde,0x73,0xbc,0xdf,0xf0,0x33,0x3f,0xfc,0x8d,0x72,0x05,0x5e,0x56,0xe6,0xa5,
+  0xf8,0x09,0x6d,0x9e,0xae,0x14,0x7f,0xdc,0x78,0x47,0x7e,0x29,0x1d,0x1f,0x85,0x10,
+  0xda,0x9a,0x4f,0xa3,0xad,0xb1,0x91,0x74,0xd8,0xcd,0x71,0xc2,0xdd,0xb0,0x1d,0xaa,
+  0xba,0xc4,0x2c,0xfa,0xee,0x8b,0x9c,0x8f,0xae,0xcc,0x46,0xec,0x86,0x2f,0xf9,0x6d,
+  0x5f,0xe0,0xba,0x21,0xad,0x8a,0x19,0xb2,0x0d,0xf6,0x81,0x5f,0xc5,0xb9,0xd8,0x2d,
+  0xff,0x0c,0x73,0xe8,0x2f,0x8a,0x18,0x73,0x97,0xf7,0x1c,0x4c,0x2f,0x1a,0xbd,0x3d,
+  0x46,0x44,0xc3,0xd6,0x7e,0xb1,0x02,0x4e,0xd1,0xfa,0x74,0xf1,0x24,0xff,0x5d,0x3a,
+  0x9b,0xbe,0x7b,0xe6,0x2b,0x93,0xa5,0x76,0x03,0x57,0xc4,0xf9,0xdb,0x4a,0xaf,0xe2,
+  0xeb,0x7e,0x99,0xf2,0x53,0x70,0x4f,0x6c,0xd9,0xb0,0x2b,0xcd,0x0f,0x1b,0xfe,0xa9,
+  0xd8,0x3e,0x81,0x13,0xa9,0xaf,0x4f,0x3a,0x0f,0xb9,0x4f,0xc1,0xa9,0x9f,0x86,0x27,
+  0x9c,0x7d,0xfc,0xb8,0x61,0xcf,0x81,0x92,0xff,0x41,0x13,0xe9,0xaa,0xf5,0xb8,0x0d,
+  0x2a,0x68,0x37,0xad,0xcd,0x62,0xe3,0xbc,0xb9,0x6f,0x61,0xe7,0xf0,0x0e,0xa9,0x92,
+  0x16,0x3e,0xe2,0x5b,0xde,0xb3,0x19,0x16,0x8f,0xae,0x5d,0x4f,0x46,0xa8,0xbe,0xbe,
+  0xb8,0x67,0xcc,0x9d,0x40,0x3b,0x14,0x52,0xe2,0x14,0xba,0x21,0xa0,0x8a,0x7e,0x72,
+  0x26,0xa9,0xbf,0x87,0x81,0xb2,0x34,0x1c,0x83,0x41,0xf5,0x81,0x0c,0xff,0x67,0xde,
+  0x53,0x64,0x39,0xdb,0x18,0x17,0x92,0xfa,0x3d,0x29,0x9c,0x83,0x2b,0x4a,0x78,0xbc,
+  0x78,0xbf,0x63,0x0a,0xde,0x86,0x70,0xd6,0xb5,0xb7,0x34,0x6b,0xf8,0x27,0x17,0xbb,
+  0x24,0x9d,0xa2,0xfb,0xb2,0xab,0x2e,0xb6,0x36,0x09,0xa7,0xa0,0x59,0x15,0x66,0xf8,
+  0x89,0x36,0xbd,0xaf,0x4b,0x58,0x07,0xbd,0x3d,0xbe,0xa3,0xfe,0x21,0xe2,0x84,0x5e,
+  0xa8,0x3b,0x12,0xdd,0x9f,0xc8,0x2a,0xba,0x7f,0x52,0xdb,0x2a,0xe8,0x5a,0x20,0xab,
+  0x7d,0x19,0x7b,0x80,0xf5,0xa9,0xf6,0x41,0x92,0x35,0xec,0x29,0x0a,0x45,0x72,0xd7,
+  0x7a,0x79,0x54,0x0c,0x92,0x5a,0xb9,0x5b,0xae,0x3b,0xb3,0x35,0x44,0x86,0x8d,0xd5,
+  0x41,0xe1,0xd7,0xe0,0x44,0x74,0xf0,0x2d,0xe7,0x32,0x7e,0xb9,0x70,0x6a,0x7d,0xf3,
+  0x78,0xf1,0x81,0xee,0x2c,0xd1,0xef,0x99,0x9e,0x3f,0x95,0xf8,0x85,0x5c,0x71,0xdc,
+  0xf5,0xf1,0xf7,0xae,0xd3,0x6b,0x4d,0xcb,0xcf,0x14,0x5d,0xec,0x9e,0x34,0xfc,0x53,
+  0xb5,0x4d,0x29,0xef,0x76,0x85,0xcf,0xb9,0x2e,0x95,0x7e,0xa2,0x5c,0xa3,0xf5,0xd9,
+  0x3b,0x66,0xf8,0x69,0x0b,0x3f,0x6f,0x24,0x0f,0x27,0xea,0xb2,0x2b,0xbf,0x4e,0xc6,
+  0xe8,0xe1,0x17,0x7c,0x59,0xc7,0x10,0xc9,0x0a,0x26,0x7e,0x8e,0x29,0xfb,0xd0,0x54,
+  0x8e,0x20,0xf6,0xed,0x13,0xd2,0xac,0xf1,0x9e,0x89,0x9f,0x65,0x7b,0xe0,0x30,0x4e,
+  0x7d,0x65,0x86,0x4c,0xc1,0x3e,0xc4,0x4f,0x6c,0x4c,0x1b,0xef,0x41,0x29,0x9b,0x92,
+  0xd0,0x54,0xea,0xea,0x0c,0x37,0x05,0xd7,0x20,0x84,0x7d,0xad,0xe3,0x16,0x7e,0xbe,
+  0x04,0xaf,0xa0,0xa9,0x5c,0xd3,0x55,0xd7,0x61,0x56,0x6b,0xe4,0xe1,0xe7,0x1e,0xee,
+  0x03,0x1c,0xe7,0xcc,0x94,0x4e,0x91,0x13,0xd8,0xa8,0xcb,0xf0,0xe3,0x46,0x7c,0x18,
+  0xb5,0x35,0x31,0x53,0x4d,0xd8,0xa7,0x49,0x40,0xc4,0xc6,0x2f,0x8a,0x32,0xe4,0xa2,
+  0x85,0x9f,0xab,0xe0,0x7b,0x10,0xc8,0x16,0x06,0xc9,0x2a,0x78,0x56,0x0e,0xa8,0xde,
+  0x20,0x99,0xb1,0xfc,0xb3,0xa2,0x67,0x73,0xa2,0x36,0xeb,0xf8,0x13,0x52,0x01,0xdf,
+  0x4c,0xd5,0x66,0xb9,0x4e,0x32,0x6a,0xe2,0xa7,0x58,0x07,0xdf,0xa3,0x4d,0xef,0x15,
+  0x35,0x96,0x7e,0x61,0xfc,0xef,0xd3,0x4d,0x53,0xce,0x7b,0xf8,0xd3,0x86,0x7f,0x2a,
+  0xf3,0x7f,0x08,0xd7,0xa4,0x26,0xf5,0x64,0x86,0xdf,0x00,0x1f,0x40,0x93,0x8a,0x31,
+  0x20,0x87,0x9f,0x17,0x12,0x27,0x84,0xb0,0xfa,0xc0,0x8b,0x2b,0x03,0xda,0xfa,0xb0,
+  0xef,0xbc,0x85,0x9f,0x4f,0x51,0x74,0x3d,0x55,0xbc,0x9c,0x28,0x87,0x83,0xb0,0x48,
+  0x75,0x74,0x90,0xd3,0x39,0xfc,0xa4,0x9b,0xe9,0xe2,0x6c,0xe1,0x13,0x91,0x0a,0x38,
+  0x48,0x2b,0xb3,0x8e,0x4e,0x32,0x6d,0xbc,0xda,0xa8,0x67,0x0c,0x61,0x33,0x70,0x24,
+  0x1a,0x8c,0x38,0xd1,0xb0,0x7e,0x66,0xeb,0xd3,0x16,0x7e,0x0e,0x20,0x5e,0x87,0x69,
+  0x51,0x1a,0xf7,0xe6,0x55,0xf0,0x51,0xdc,0x2b,0x57,0x2d,0xfc,0xd4,0x61,0x13,0xf7,
+  0xb4,0xd6,0x90,0x5c,0xb4,0xf4,0x74,0x0e,0x3f,0xe1,0x0a,0x1f,0x56,0x8a,0x75,0x2c,
+  0x08,0xad,0x47,0x2c,0x18,0xce,0xc3,0xcf,0x43,0x5c,0xa0,0x03,0x43,0xcd,0x04,0x1c,
+  0x82,0xdd,0x8a,0x23,0x85,0x3e,0x68,0xe2,0x27,0x42,0x2a,0xd4,0xad,0xb5,0xeb,0x7d,
+  0x3e,0xd6,0x77,0xd4,0xc2,0x4f,0x81,0x2e,0x11,0x02,0x8a,0xe8,0x26,0x23,0xb0,0x17,
+  0x71,0x1e,0xb1,0x60,0xd8,0xc2,0xcf,0x75,0x4a,0x27,0xce,0x65,0xfb,0x26,0xfe,0x9c,
+  0x32,0x1d,0x63,0x40,0xf3,0xe8,0x05,0x5e,0x7f,0x0f,0x88,0x9f,0xca,0x15,0x06,0x8d,
+  0x4f,0xb3,0xb9,0xcc,0x0b,0x33,0x80,0xca,0xe1,0xe7,0x84,0x7c,0x0c,0x9a,0x95,0xd5,
+  0xa9,0xee,0x09,0xb8,0xa1,0xd4,0x2b,0xce,0x14,0x7f,0xd4,0xc2,0xcf,0x73,0x89,0x1e,
+  0x52,0x07,0x7c,0x32,0x92,0x45,0xfc,0xac,0x01,0x91,0x92,0x93,0x79,0xf8,0xd9,0x05,
+  0x7e,0xc5,0xe1,0x4e,0x20,0x90,0x82,0xac,0x88,0x6c,0x2e,0xc6,0x3d,0x4b,0xfa,0xc5,
+  0x2d,0x50,0xc7,0xa6,0x3e,0x21,0xee,0xc5,0x86,0x1f,0xd7,0x60,0xe2,0x67,0xd9,0x04,
+  0xee,0xf7,0x46,0x06,0xe1,0x13,0xc2,0x15,0x16,0xa7,0x53,0xfc,0xa4,0xe1,0x9f,0x7e,
+  0x2e,0x09,0x1a,0xa4,0xea,0x36,0x6b,0xd4,0xf1,0x53,0x5f,0x3b,0xe2,0xa7,0x30,0xc3,
+  0x85,0x61,0x35,0x45,0x5e,0x30,0x4a,0x31,0x56,0x51,0xfe,0xb8,0x89,0x9f,0x18,0xdf,
+  0x5f,0x84,0xc5,0x83,0x8e,0x34,0xf1,0x0b,0xef,0x70,0xb5,0x43,0xd1,0x34,0xb1,0xc6,
+  0xa1,0x7f,0xe2,0x3e,0xea,0xc1,0x57,0x8a,0xb1,0x51,0x0a,0x44,0xec,0xc1,0xc8,0x71,
+  0xc3,0x3f,0xd3,0x5c,0xb9,0x78,0x17,0xa9,0xa5,0x8e,0x06,0x7c,0xe8,0x37,0xa1,0x96,
+  0xfa,0x3b,0xc8,0xa4,0x31,0x6e,0x40,0xac,0x48,0xff,0x82,0x2e,0xcf,0xba,0x3a,0xf9,
+  0x70,0xfa,0x35,0xba,0x5c,0x2e,0xee,0xe4,0xcf,0x5b,0xf8,0xf9,0x43,0x7a,0x8d,0x84,
+  0x8f,0xb8,0x0e,0xf0,0x1f,0x0a,0xd7,0xa0,0x89,0x71,0x94,0x61,0xa2,0xaf,0x0f,0x6c,
+  0x9f,0xc4,0x4f,0x25,0xc3,0xe9,0xd5,0x3f,0xe9,0xfe,0x91,0x72,0x32,0x15,0x92,0x8b,
+  0x86,0x78,0xd5,0xc2,0xcf,0xef,0x24,0xba,0x9f,0xae,0x4d,0xe3,0xf3,0xea,0xc8,0x8e,
+  0x4d,0x7e,0x59,0xbc,0x27,0x1f,0x3f,0x61,0xb3,0x1b,0xe7,0x12,0x24,0x3b,0xe9,0x93,
+  0x72,0x25,0x6c,0xe9,0x70,0xab,0x92,0xbe,0x3e,0x59,0xf7,0x4f,0xaa,0xaf,0x01,0xc3,
+  0x0c,0x02,0xd4,0xa8,0x60,0xe2,0xe7,0x4b,0xc8,0x7b,0xc2,0x48,0x85,0xaa,0x5e,0x42,
+  0xc3,0xfa,0x00,0xf7,0xa6,0x79,0x4f,0x0a,0x53,0xe2,0x35,0x2e,0x9c,0x5a,0x9d,0xe1,
+  0xa7,0xd0,0xd6,0x68,0xbc,0x4c,0x0e,0x3f,0x25,0x84,0x00,0xae,0x99,0xee,0x98,0xe6,
+  0xaf,0xc3,0x0d,0xb8,0x0b,0xec,0xd3,0xbc,0x6a,0xe1,0xe7,0x06,0x86,0x2f,0xff,0xd3,
+  0x81,0xf8,0x22,0x1c,0xc2,0x01,0x18,0x7c,0x72,0xf8,0x19,0x80,0xc3,0x5c,0x5d,0x17,
+  0xeb,0x83,0x41,0xea,0xbb,0xd5,0x8e,0x7d,0x96,0x7f,0x3a,0x95,0xfa,0x78,0xa0,0xd7,
+  0xb1,0x74,0x78,0x2c,0xbe,0x4f,0x96,0x9d,0xf6,0x65,0x96,0x7f,0x42,0xd1,0xc3,0xf2,
+  0x35,0x08,0xf7,0xb8,0x2e,0xf2,0x37,0xe8,0x55,0xf4,0xcf,0xe2,0x0c,0xaf,0x1a,0xfe,
+  0x99,0xbe,0x15,0xa1,0x4a,0x6a,0xb6,0xf3,0x17,0x79,0xc4,0xcf,0xf5,0x77,0x4b,0x45,
+  0x1f,0xf1,0x39,0xfc,0xfc,0x04,0x66,0x4b,0xee,0x91,0x1f,0xb8,0x54,0x58,0xa7,0x8e,
+  0xd1,0x3f,0x9f,0x71,0x36,0xe4,0xe1,0xe7,0x8f,0xa4,0x83,0x1d,0xbe,0xb8,0xe3,0x12,
+  0x59,0x10,0xeb,0x95,0xeb,0x46,0xec,0x43,0x88,0x83,0x06,0x7e,0x0a,0x63,0x80,0x53,
+  0xc8,0xa2,0xcd,0x44,0xd2,0x5d,0x18,0xf8,0x39,0xda,0xec,0x62,0x3e,0x7e,0x0a,0x08,
+  0xb7,0x19,0xe2,0x23,0xbd,0xb4,0xf8,0x55,0x7b,0x0e,0x3f,0xc1,0xa6,0xc1,0x66,0x1c,
+  0x5f,0x69,0x00,0x56,0x8e,0xd6,0xa5,0x31,0x1e,0xa9,0x26,0x7e,0x96,0xbc,0x24,0xce,
+  0xc2,0x2b,0x0a,0xc2,0xe6,0x04,0xcc,0xf2,0xcb,0xe7,0xf2,0xcf,0x3d,0x26,0x1c,0x8d,
+  0x49,0xf8,0x42,0xba,0x9c,0x99,0x3c,0xfe,0x19,0x10,0x5f,0x01,0x7c,0xde,0x34,0xee,
+  0x69,0xc4,0xcf,0x2e,0x7c,0x47,0x21,0xc3,0x66,0xaa,0xc0,0x20,0x47,0xce,0xde,0x9e,
+  0x29,0xd0,0x80,0xb4,0x45,0x0c,0xba,0x1b,0x4c,0xfc,0x94,0x2a,0xfa,0x10,0xaa,0x26,
+  0x11,0xaa,0xde,0x69,0xfb,0x3e,0x0d,0xb4,0x17,0x3e,0x41,0x9a,0x24,0x7d,0x5c,0x54,
+  0x2c,0xa6,0xfb,0x20,0x78,0xde,0x15,0xe4,0x8f,0xd3,0x9f,0xa5,0x9b,0xda,0x9d,0x8d,
+  0xbc,0xdb,0xc4,0x4f,0xcf,0x4b,0x38,0x97,0x57,0x46,0x5c,0x97,0xbb,0x26,0x0b,0xde,
+  0x96,0x9a,0x95,0x3c,0xfc,0x14,0xd9,0xfa,0x64,0xf4,0xdd,0x41,0x86,0xad,0x5c,0xe8,
+  0x08,0xce,0xf3,0xbc,0xb1,0xbe,0x28,0xb7,0x13,0x0e,0x46,0x6b,0x55,0x47,0x08,0xfd,
+  0x6c,0x07,0x04,0xd5,0xad,0x1d,0xe4,0xa2,0x61,0x17,0x19,0xf9,0xe7,0xc1,0x34,0x62,
+  0xf9,0x13,0xe4,0xcb,0xf0,0x7d,0xfa,0xd5,0xac,0xd8,0x89,0xef,0x5d,0x5f,0x5f,0x3b,
+  0xfa,0xa7,0x11,0xab,0x9c,0x52,0x37,0x95,0x55,0x7b,0x1e,0x7e,0x0a,0x03,0x08,0x9b,
+  0xcd,0x0c,0x36,0x3b,0xe1,0x42,0xf4,0xae,0x64,0x00,0xf1,0xd3,0xb0,0x59,0x54,0x62,
+  0x54,0x28,0x2c,0x23,0x7e,0xbe,0x07,0x33,0xa2,0x06,0xa4,0x39,0xfc,0xec,0x87,0x37,
+  0xa1,0xb1,0xbd,0x48,0xe2,0x93,0x70,0x4c,0x08,0x22,0x4e,0x70,0xc3,0x60,0xe2,0x67,
+  0x35,0xec,0xe5,0xe4,0x38,0xe2,0x67,0x35,0x74,0x91,0xdd,0x8a,0x78,0x33,0x7e,0xd6,
+  0x28,0x85,0x29,0xd2,0x0f,0x5b,0x38,0x5f,0x8b,0x38,0x07,0x3f,0x61,0x6f,0xb5,0x8f,
+  0xe1,0xa7,0x40,0xb7,0x40,0x3c,0x2a,0xe6,0xe1,0xe7,0xfc,0x38,0xcc,0xc4,0x1a,0xa1,
+  0x08,0xf9,0xa7,0x32,0x1a,0x0b,0x79,0x02,0x94,0x37,0xf1,0x73,0x68,0x3e,0xc2,0x91,
+  0xd4,0x7c,0x04,0xf1,0xf3,0xf2,0x1a,0x8c,0x9b,0x6d,0xae,0x1c,0x7e,0x36,0x20,0x9f,
+  0x7f,0xb3,0xa5,0x19,0x29,0x62,0x62,0x22,0x7d,0x9f,0xb4,0x6c,0xd4,0x39,0xee,0x7b,
+  0xdf,0xf0,0x4f,0x2f,0x64,0xa5,0x21,0xa5,0x0e,0x1c,0x4f,0x26,0x14,0x4a,0x41,0xb6,
+  0xfb,0x73,0xf8,0x19,0xb5,0x25,0x61,0x6f,0x3c,0xa0,0xdc,0x8a,0x58,0x9e,0x46,0x32,
+  0xbd,0x4a,0x94,0xe0,0xb4,0x89,0x9f,0x9e,0x7e,0x16,0x03,0xe2,0x2b,0x53,0xc2,0x7a,
+  0xb2,0x05,0x63,0x80,0x37,0x0f,0x3f,0x85,0x7e,0xef,0x9b,0x10,0x8e,0x17,0xa5,0xd6,
+  0xfd,0xe3,0xd2,0x23,0xc9,0x6f,0xb4,0xac,0x4a,0xb5,0x9a,0xf8,0xd9,0x2e,0xb1,0x71,
+  0x1a,0x7e,0xb6,0x49,0x48,0x9c,0x58,0xe3,0x2d,0xc3,0xd6,0x7e,0xcd,0xd6,0x3e,0xa9,
+  0x88,0xb6,0x56,0xc2,0x68,0x24,0x04,0x47,0x69,0x95,0x89,0x9f,0xa2,0xe0,0x87,0x97,
+  0xc1,0x37,0x20,0x66,0x89,0x1f,0xb6,0x62,0x8c,0x2b,0xce,0x5a,0xf8,0x29,0x22,0x7e,
+  0x3e,0x8b,0xfe,0x89,0xf1,0x7d,0x1b,0x62,0x4f,0x8d,0x5a,0x28,0x93,0xe3,0x56,0x7c,
+  0x2f,0x17,0x0e,0xa6,0xab,0xb2,0x85,0x9d,0xe4,0x2c,0x6c,0x96,0x17,0x8d,0x88,0x71,
+  0x0b,0x3f,0xfd,0xde,0x0a,0xd8,0x37,0x50,0x9f,0x7d,0xe0,0x4f,0xab,0xbe,0x4b,0x5f,
+  0x7b,0xe1,0xee,0xac,0xab,0x3d,0x0f,0x3f,0x71,0xff,0x75,0xbc,0xac,0x16,0x0f,0xf2,
+  0xb5,0xe8,0xa8,0xcb,0xc6,0x17,0xe7,0xf8,0x67,0x5c,0xf8,0x11,0x30,0x9a,0xb4,0xe3,
+  0x4a,0xf7,0xac,0xf2,0x41,0x5f,0xf3,0xe5,0x40,0x7b,0x95,0x64,0xe2,0xa7,0xb4,0x7d,
+  0xe4,0x20,0x95,0x27,0x0b,0x67,0x48,0xb8,0xba,0x9b,0x2e,0x9e,0xf4,0xb6,0x93,0x9a,
+  0x3c,0xfc,0xfc,0xa6,0x5c,0x39,0x8a,0x7b,0x0c,0x9d,0x18,0x6a,0x55,0x31,0x5e,0x53,
+  0x60,0xf8,0xa7,0xe2,0xd9,0x26,0xec,0x23,0xb2,0xda,0x1b,0x24,0xc5,0x52,0xa9,0x8a,
+  0xfc,0x53,0x26,0x5e,0x13,0x3f,0x6d,0x7b,0xe0,0x5d,0x08,0xbd,0x31,0x6f,0x9a,0x7f,
+  0x19,0x66,0xa3,0xcd,0xaa,0x33,0x7d,0x7b,0x9d,0xc5,0xf5,0x19,0x16,0x84,0xd5,0xa2,
+  0x0c,0xbf,0x07,0x18,0x39,0x72,0xa5,0xe7,0xe0,0xe7,0x35,0x68,0xce,0xba,0xa6,0xed,
+  0xe5,0xe4,0x54,0xe1,0x72,0x15,0x8d,0x67,0x72,0x37,0x03,0x3f,0x55,0xc4,0x17,0xe4,
+  0x98,0xa4,0x4e,0x2d,0x4a,0xfb,0x4c,0xff,0xa4,0x36,0xd6,0x57,0x33,0x82,0x5b,0x64,
+  0x0f,0x72,0xa9,0xc7,0x54,0x7b,0x3a,0x87,0x9f,0x92,0x53,0xde,0x27,0x06,0x46,0x1d,
+  0xa1,0x82,0x6d,0xe9,0xee,0x75,0x81,0x9f,0xf2,0x0b,0x13,0x16,0x7e,0x8a,0x1b,0x90,
+  0xbb,0x35,0xaa,0xc5,0x17,0xb9,0x9f,0xa8,0xa7,0xe4,0xe6,0xd1,0xe2,0x7e,0x3e,0x6b,
+  0xe2,0x67,0xd9,0x75,0x79,0x16,0xc2,0x6b,0x90,0x1e,0x6f,0x10,0x67,0xe3,0xe1,0x31,
+  0x24,0x2b,0x93,0x11,0x0b,0x3f,0x3d,0xd3,0xc9,0xc3,0x72,0x51,0x94,0x34,0xc0,0x25,
+  0x7a,0x57,0xb6,0x18,0xf9,0xa7,0xe1,0x2f,0x14,0x2e,0x88,0x43,0xd4,0x27,0xa3,0x5b,
+  0xfa,0x00,0x05,0x24,0xe3,0x9f,0xd3,0x96,0x7e,0x1f,0x83,0x0c,0x0b,0x35,0x80,0x12,
+  0x71,0x1f,0xf4,0xb3,0xcd,0x9d,0x8f,0x9f,0x38,0xce,0x27,0xf6,0x3c,0x33,0x00,0xf7,
+  0x80,0x8f,0x2d,0x34,0x1f,0x3f,0xaf,0xa4,0x1b,0x82,0x45,0x4e,0xfe,0x07,0x70,0x09,
+  0x96,0xa9,0xc5,0x19,0x62,0xea,0x07,0xc4,0x4f,0xe7,0x75,0x68,0xe6,0x76,0x8c,0xf3,
+  0x7f,0x60,0xf2,0xcf,0xeb,0x79,0xf8,0x89,0xfb,0x1d,0x9c,0xc9,0xee,0x01,0x8d,0x7f,
+  0xba,0x32,0xe4,0x0d,0xe3,0xfd,0x21,0x7e,0x52,0x4a,0x6b,0x0a,0xc4,0xe7,0xc9,0x00,
+  0xe2,0xa7,0xf6,0xbc,0x8b,0x39,0xfc,0x14,0x52,0x6e,0x3f,0xe2,0xa1,0xd2,0x83,0xf8,
+  0xa9,0x71,0x37,0x93,0xd7,0xc9,0x4a,0x05,0x6c,0xa3,0x8b,0x64,0xf1,0x18,0x79,0x3e,
+  0xf9,0x7d,0x06,0xa4,0x4f,0xc0,0x75,0xa3,0x2f,0xea,0x75,0xc2,0x78,0xba,0x41,0x0e,
+  0xd8,0xf9,0xde,0xe4,0xcf,0x92,0x0d,0x93,0x2e,0xe4,0x9f,0x05,0x7a,0x9f,0x52,0xbe,
+  0x13,0xae,0x56,0x2e,0x87,0x1d,0x09,0x7e,0x52,0x79,0x1b,0x8d,0xee,0x42,0x0e,0x5d,
+  0x60,0xec,0x95,0xb2,0x29,0x61,0x1a,0x96,0xb5,0x6c,0xa5,0x3c,0x03,0xfc,0x85,0x0c,
+  0xf0,0x87,0x4d,0xfe,0x79,0x5f,0x39,0xec,0x27,0x95,0x8a,0x4d,0x25,0x5e,0xf4,0xc1,
+  0x4a,0xe4,0x9f,0x70,0xd1,0x58,0x9f,0x0c,0x15,0xb0,0x9f,0x2e,0x96,0xed,0x51,0x82,
+  0x40,0x4a,0x17,0x30,0xfe,0x79,0xc6,0x98,0x4b,0x3b,0xc6,0xaa,0xcc,0x1a,0x7f,0x62,
+  0x4b,0x6d,0x82,0xd9,0xba,0x9a,0xad,0xe1,0xad,0x3c,0xfe,0xf9,0xb1,0xba,0xbc,0xa7,
+  0x22,0xcb,0x7f,0x4b,0xbe,0x0a,0xcb,0xa8,0x83,0xe1,0xa7,0x3e,0x17,0xd4,0xef,0x30,
+  0x24,0x2e,0x2c,0xb9,0x23,0x59,0x1a,0x4f,0xcd,0xa0,0xf1,0x5c,0xb4,0xea,0xb4,0xb9,
+  0xa7,0x19,0xff,0x4c,0x84,0x62,0xfc,0xf3,0x7c,0xb5,0x74,0x2c,0xb2,0x90,0x71,0xbe,
+  0x61,0xa3,0x8f,0x0a,0x0b,0x94,0x43,0xf4,0x85,0xb5,0x3d,0x5e,0xc4,0xcf,0x5d,0xd4,
+  0xa7,0xf3,0x4f,0xfd,0xd2,0xf0,0x53,0xaa,0x41,0x48,0xb5,0x57,0x9b,0x24,0x6e,0x0e,
+  0x7e,0x22,0xb6,0x8a,0x92,0xbd,0x3a,0x59,0xc9,0xc8,0x1f,0xc3,0x4f,0xfd,0x9e,0x43,
+  0xf3,0xdb,0x11,0xe7,0x1b,0xa1,0xf6,0xaf,0x19,0x3f,0xd3,0x49,0xf1,0x85,0x79,0x39,
+  0xfc,0xbc,0x01,0xcb,0x95,0xa2,0x71,0xfe,0xb2,0xf2,0x11,0xdc,0xc2,0xe6,0x72,0xc1,
+  0xc2,0xcf,0xfd,0xf0,0x0f,0x64,0xb9,0xe2,0x8c,0x71,0xd5,0xf2,0x3f,0x40,0x85,0x72,
+  0x47,0xaa,0xea,0x82,0xe1,0x83,0x88,0x9f,0x30,0x84,0xae,0x59,0x44,0xa1,0x12,0x7a,
+  0x00,0x81,0x94,0xe2,0x5c,0x0c,0xfc,0x14,0x92,0xc2,0xb7,0xa0,0x5a,0xf1,0xbb,0x13,
+  0xd5,0xe4,0x69,0x08,0x28,0x76,0x89,0x9c,0x36,0xe6,0xe2,0x8d,0xf5,0x6b,0xd4,0xb9,
+  0x10,0xd7,0x40,0xd9,0x1a,0x56,0x32,0xfc,0xd4,0xfb,0xd2,0x6d,0xfd,0xc2,0x4f,0xe9,
+  0xd2,0x3f,0xf1,0x78,0xb9,0x6a,0x74,0xb8,0x3f,0x67,0x18,0x39,0x69,0xc6,0xb1,0x12,
+  0xd4,0xf6,0xfe,0x70,0xc7,0x1d,0xcf,0x39,0x18,0xff,0xd4,0xfa,0xde,0x32,0x39,0xa6,
+  0x24,0xcb,0xa8,0xdf,0xbd,0x2e,0xda,0x9a,0xd6,0xd6,0xf7,0x54,0x8e,0x7f,0x8a,0xb6,
+  0x46,0x28,0x56,0xaa,0x32,0xf6,0xf7,0x71,0xaf,0xbc,0xd3,0x56,0x87,0xbf,0x12,0x31,
+  0x75,0xa3,0x68,0x5b,0x01,0x5d,0x0f,0xca,0x9b,0x6e,0x0d,0x24,0x9c,0xb0,0x3b,0xab,
+  0x05,0xc9,0xe1,0x9c,0x3e,0xf2,0x3d,0x05,0xeb,0x90,0x7a,0x91,0x97,0xe0,0x2f,0x8b,
+  0xbe,0xc6,0xf4,0xca,0xa8,0x89,0xd7,0x5e,0x37,0x42,0xf4,0x12,0xb9,0xa8,0x93,0xaf,
+  0x80,0x09,0x3a,0x3f,0xfb,0xed,0x4e,0x2b,0x97,0x20,0xce,0xa7,0x30,0x8d,0x88,0xbd,
+  0x38,0x33,0x6f,0x4c,0x9a,0x81,0x0a,0x14,0x7b,0x7c,0xe4,0x16,0x7d,0x5c,0x5c,0x78,
+  0x1e,0xa6,0xe8,0x8b,0xeb,0xeb,0x3a,0xab,0x2a,0x50,0xc8,0x37,0x4f,0xb8,0x66,0xf8,
+  0x33,0xc6,0x3c,0x07,0xa0,0x2f,0x99,0x94,0x97,0xca,0x45,0x41,0x7b,0x31,0xdd,0xbc,
+  0x2b,0x90,0x45,0x22,0x7a,0x9e,0xc8,0x86,0xd3,0xa7,0x0a,0xf6,0xc0,0x22,0xa7,0xe3,
+  0x23,0xd2,0x44,0x37,0x05,0x6b,0x47,0x71,0x2e,0x47,0x15,0xbd,0x4f,0xf1,0x50,0xa0,
+  0x4a,0xbf,0x5c,0xb8,0x94,0x14,0x91,0x2e,0x2d,0xd0,0xfb,0xc6,0x0d,0x6d,0x3f,0x80,
+  0x9c,0x3d,0xab,0x36,0x90,0xe2,0xfd,0xbc,0x8b,0x24,0x04,0xb6,0x6f,0xf9,0x0b,0x54,
+  0x9f,0x4b,0x1a,0x7d,0x70,0x26,0x16,0x96,0x16,0xff,0x98,0x9f,0x52,0xae,0x46,0xc2,
+  0xea,0x8e,0x4c,0xd5,0xa4,0xa5,0xdf,0xa7,0x85,0x29,0xb1,0x5e,0x2e,0x9a,0x7e,0xf6,
+  0xba,0x7c,0x76,0x77,0x95,0xba,0x7a,0xba,0x34,0x6e,0x70,0xcc,0x2e,0xe1,0x11,0x18,
+  0x18,0xf5,0x85,0x6a,0xfb,0xc8,0x14,0xe9,0x39,0x57,0x83,0xfb,0xdd,0x97,0xe3,0x9f,
+  0xd8,0x97,0xd8,0x2d,0x2e,0x7a,0x09,0xfb,0x86,0xa0,0xe6,0x48,0x61,0xc6,0x9d,0xd3,
+  0xef,0xf8,0x4c,0x48,0x17,0xde,0xb7,0x84,0x7c,0x88,0xe4,0xbe,0x7d,0xd4,0xb1,0xb4,
+  0x60,0x58,0x30,0x1d,0x5b,0x86,0xc9,0x58,0xe8,0xb6,0xa2,0xfd,0xa5,0x1f,0xd2,0x19,
+  0xa9,0xf1,0x9d,0xa2,0x03,0x5d,0x71,0xd9,0xd4,0xef,0xd3,0x70,0x19,0x96,0xdb,0x71,
+  0x0a,0x53,0x23,0x67,0xdd,0xe1,0x51,0xdc,0xef,0x66,0x4c,0x55,0x6d,0xff,0x04,0xa7,
+  0x68,0x48,0x2d,0x7c,0x89,0x7f,0x5f,0x79,0x97,0x86,0xc7,0x03,0x43,0x16,0xff,0x54,
+  0xa5,0x09,0xd2,0xdd,0x53,0x75,0x19,0xa9,0xe5,0x18,0xf4,0xd2,0xba,0x37,0xc4,0x21,
+  0xc8,0x5a,0xf1,0x7d,0x8a,0x7e,0x4f,0x4e,0x33,0x2e,0x35,0x46,0x9f,0x85,0xc0,0xe8,
+  0xad,0xf9,0xfa,0xbd,0xbf,0xfc,0x6f,0x11,0xc6,0xc4,0x4c,0xc1,0x94,0xd4,0xcb,0xd5,
+  0xa9,0x85,0x39,0xfc,0xa4,0x65,0x23,0x18,0x6a,0x42,0x68,0x2a,0xfe,0x82,0x26,0xe4,
+  0x31,0xf8,0x98,0xfa,0x21,0xcb,0xed,0x17,0xde,0x25,0xcb,0x19,0x6c,0xce,0x22,0x7e,
+  0x2e,0x57,0x8b,0x91,0x7f,0x9a,0xba,0x1f,0x63,0xff,0x35,0x18,0x44,0xb8,0xd5,0x63,
+  0xd5,0x11,0xc6,0xf9,0x8c,0xf7,0xde,0x83,0x7b,0xfa,0xf0,0xd6,0x2a,0x7c,0xde,0x1a,
+  0x96,0xf3,0x58,0x7c,0xc4,0x31,0x47,0xbf,0x8b,0xc8,0x3f,0x91,0xb2,0x45,0xa6,0x18,
+  0xff,0x3c,0x92,0x87,0x9f,0xe9,0xae,0x5b,0xd4,0x83,0x29,0xf9,0x9c,0xd8,0xe9,0xfe,
+  0xf2,0xc8,0x66,0x5a,0x8b,0xf8,0x49,0xce,0x18,0xf6,0x8c,0x46,0x8b,0xe1,0x52,0x26,
+  0x98,0x2d,0x6e,0xe0,0x4f,0xc2,0xcf,0x68,0xd3,0xa4,0xab,0x31,0x4f,0xbf,0xef,0x67,
+  0xb1,0x71,0x1c,0xa7,0xb0,0x47,0xc2,0xc0,0x34,0xec,0xda,0x6b,0xcd,0x65,0xc0,0x36,
+  0x51,0x78,0x02,0x06,0xb1,0xaf,0x4a,0xcb,0x33,0x64,0x8b,0xf2,0xf0,0xf3,0xe9,0xe7,
+  0xb8,0xcd,0x50,0x79,0x06,0x5d,0x0f,0xf9,0x04,0x2c,0x1e,0x15,0x51,0xbf,0x1b,0xfb,
+  0x81,0xc2,0x01,0xd8,0x9c,0xd4,0x64,0xfb,0x27,0x12,0xce,0x85,0x91,0x8e,0x51,0x2b,
+  0xff,0xf9,0x7e,0xe4,0x6f,0x99,0x1c,0x66,0xef,0x41,0xcb,0x2f,0xcd,0xc1,0x4f,0xe9,
+  0x38,0x0a,0x15,0xe4,0x9f,0x93,0xa6,0x90,0xbf,0xca,0xe9,0xf7,0x64,0xfa,0x7d,0xad,
+  0xa1,0xdf,0x15,0x43,0xc8,0x9b,0xf9,0x02,0x2d,0xff,0x09,0xa1,0x16,0x17,0xd3,0xe1,
+  0xc7,0x74,0x52,0x95,0xc3,0xcf,0xf5,0xb0,0x85,0x68,0xb0,0x39,0x42,0xb6,0x70,0x8f,
+  0xdd,0x84,0x9f,0xe2,0x16,0x5d,0xb6,0x4f,0xc0,0xcd,0xf8,0xd9,0x26,0x40,0x17,0xa4,
+  0xa3,0x08,0x9b,0x13,0xd0,0xc5,0x05,0xa2,0x73,0xf5,0x7b,0x4c,0x65,0xb2,0x9d,0xe9,
+  0xf7,0x51,0xa8,0xf3,0xec,0xc8,0xe1,0xe7,0xe8,0xfc,0x37,0x58,0x3a,0xb1,0x6d,0x75,
+  0xaa,0xf5,0x0d,0x91,0x35,0x5c,0x39,0xfc,0xf4,0xda,0x5e,0x45,0x6c,0x0d,0x99,0x9a,
+  0x39,0x7c,0xbf,0x8b,0xe1,0xa7,0xde,0xd7,0x29,0x21,0x7e,0xca,0xbb,0x19,0x6c,0x62,
+  0x03,0xea,0xbc,0x0e,0xea,0x36,0xf1,0x13,0xf5,0x3b,0xec,0x15,0xe5,0x18,0xf2,0x56,
+  0xa6,0xdf,0x03,0x11,0x9c,0xcb,0x69,0xc3,0x9e,0xde,0xb2,0x7e,0xc4,0x79,0x63,0x0d,
+  0x87,0x8c,0x35,0x98,0xf8,0xe9,0x61,0xf9,0x4f,0xed,0x79,0xef,0x03,0x4b,0x2a,0xec,
+  0xc8,0xc3,0x4f,0xe8,0x37,0xd2,0x9e,0x8f,0x4e,0x28,0x46,0xfe,0x33,0x87,0x9f,0x08,
+  0x9b,0x74,0x90,0x99,0xd8,0x8a,0x0f,0x96,0x7e,0x47,0xfe,0xb9,0x1d,0x69,0x27,0xd3,
+  0xef,0xf0,0x82,0x50,0xc7,0x1a,0x26,0x7e,0x32,0xfd,0xde,0xad,0xbd,0x5b,0x9f,0x9e,
+  0x3b,0x9c,0x83,0x9f,0x61,0xba,0x99,0x85,0xd9,0x4e,0xd4,0xef,0xdf,0x87,0xda,0x57,
+  0x35,0xfc,0xd4,0x6d,0xed,0x17,0x2b,0xc8,0x29,0xba,0x24,0xeb,0xba,0xc6,0x87,0x55,
+  0xd4,0xef,0x93,0xae,0xce,0xaa,0xe3,0x46,0x7c,0x47,0xfe,0x49,0x19,0xaf,0x43,0x0d,
+  0xf4,0xa1,0xde,0xc8,0xe4,0xe5,0x3f,0xff,0x29,0x7e,0x72,0x33,0xe3,0x9f,0x3f,0x43,
+  0xe1,0x49,0x91,0xe0,0xcd,0x94,0x9e,0x31,0xd6,0x87,0xfa,0xdd,0xb7,0x15,0xee,0x3c,
+  0xe2,0xe8,0x8c,0x9c,0xad,0xde,0x47,0x6b,0xa7,0x56,0xfe,0xa9,0xfb,0xbc,0xb1,0x06,
+  0xa0,0x3b,0xe9,0x76,0x2d,0xe4,0xa3,0xef,0x1e,0x14,0x10,0x3f,0x1f,0x27,0x23,0x06,
+  0x7e,0xc6,0x3d,0x27,0x91,0x56,0x57,0xb3,0x6d,0x87,0x42,0x49,0xa8,0x53,0x57,0x06,
+  0x89,0xb5,0x1f,0xca,0x5e,0x96,0x8e,0x31,0xdd,0xc8,0xa8,0xd0,0x35,0x61,0x31,0xce,
+  0xe5,0x8b,0xe7,0x2d,0x9f,0x9f,0x92,0x8c,0xe9,0xe9,0x44,0x94,0x35,0x84,0x1c,0xff,
+  0xbc,0x01,0xf5,0x6c,0x5c,0x93,0xc6,0xa5,0x9c,0xd3,0x7c,0xb6,0xcd,0xd4,0x47,0x8c,
+  0x63,0x32,0x9a,0xb4,0x66,0x0f,0x13,0xeb,0x2a,0xea,0xdb,0x73,0x16,0x7e,0x6e,0x80,
+  0x43,0x3d,0x3e,0x9d,0x9b,0x32,0x92,0xca,0xb4,0xbd,0x89,0x9f,0x80,0xfc,0x93,0xd9,
+  0x3a,0xe3,0x7e,0x4a,0xd8,0x57,0x55,0x37,0x8c,0x24,0x35,0xc7,0x3f,0xff,0x33,0xbd,
+  0x22,0x85,0x46,0x5c,0xff,0x5c,0xba,0x1c,0xae,0x29,0xe1,0xf1,0x6d,0xfb,0xf8,0xac,
+  0xb1,0xdf,0xd3,0xf3,0xaf,0xa7,0x67,0xab,0x9b,0x8f,0xb9,0xf6,0x31,0xfd,0xde,0x10,
+  0x3e,0xe1,0x3a,0x90,0xd3,0xef,0xdc,0x27,0xc8,0xe7,0x97,0xc7,0x5d,0x43,0x7c,0x0d,
+  0x8c,0xe1,0xfe,0xbb,0x63,0xc8,0xaa,0x1f,0xa9,0xe2,0x05,0x38,0x9c,0x40,0xf7,0xca,
+  0x90,0x1a,0x78,0xab,0xab,0x8e,0xf1,0x4f,0x99,0xe8,0x6b,0x18,0x45,0xfe,0xb9,0x8f,
+  0x6c,0x50,0xf0,0x75,0xfb,0xc0,0x78,0xef,0x16,0x7e,0xda,0x98,0x7e,0x7f,0x2c,0xae,
+  0xe9,0xf7,0xbf,0x82,0xba,0x11,0x96,0xff,0x34,0x6c,0x26,0x95,0x69,0xa6,0x92,0x4f,
+  0x05,0x79,0x3b,0x8c,0x46,0xc3,0x69,0x47,0xc6,0x91,0x97,0xff,0xf4,0xa2,0xa9,0x50,
+  0xbf,0x3b,0x66,0xe0,0x13,0x96,0x4f,0x9e,0x76,0x34,0x18,0xe3,0x62,0x9a,0x7e,0x47,
+  0xfd,0xa7,0xd5,0x65,0x20,0x34,0xd2,0x94,0xc3,0x4f,0xa6,0xdf,0xd1,0x54,0xdf,0x10,
+  0x87,0x50,0x53,0xf6,0xc2,0xb2,0xac,0x18,0x8c,0xe4,0xf8,0x27,0xcb,0x2f,0xf9,0x95,
+  0xc2,0x06,0x22,0x72,0x5d,0x44,0x90,0xc5,0x20,0x4c,0x73,0xba,0x3d,0xa7,0xe1,0xcb,
+  0xf4,0x20,0xad,0x5d,0x8f,0x52,0xf9,0xf9,0xae,0x1d,0x5d,0x0b,0x3a,0xb1,0x31,0x2a,
+  0xe9,0xef,0x21,0x0a,0x5f,0xa0,0x97,0x52,0x0d,0x3f,0x7f,0x60,0xa8,0x97,0xd0,0x13,
+  0x74,0xe9,0xa4,0x88,0xfc,0xd3,0x30,0xb5,0x32,0x1f,0xf5,0xbb,0x3b,0xcc,0x64,0xbb,
+  0xaa,0xbd,0xf7,0x53,0x37,0xe9,0x77,0x5c,0xdf,0xfc,0x0c,0xef,0x87,0x63,0x34,0x24,
+  0x3b,0x73,0xf8,0x39,0x7a,0xab,0x26,0x7d,0x94,0xb5,0xd3,0xfc,0x5a,0xf8,0x5f,0x50,
+  0xa9,0xf4,0x74,0xf8,0x4e,0x1b,0xe3,0x34,0xfd,0x8e,0xfc,0xf3,0xbe,0xce,0xd0,0x60,
+  0x10,0x35,0x3a,0xd3,0xef,0x3d,0xe6,0xbe,0x45,0xfe,0x79,0x18,0x02,0x31,0x31,0x68,
+  0x3f,0x8e,0x62,0x2f,0xad,0xfa,0x11,0x3f,0x21,0x57,0x3f,0x42,0xfd,0x3e,0x84,0xb0,
+  0x39,0x04,0x27,0xa1,0x9e,0x3a,0xd3,0xfc,0x8b,0x56,0xbe,0x40,0xd3,0xef,0x6e,0x17,
+  0x25,0x8f,0x98,0x89,0x50,0x13,0xaf,0x45,0xad,0x4e,0x12,0x8a,0xbb,0xfa,0x4a,0xab,
+  0x7f,0x15,0x7e,0x1e,0x22,0xbe,0x0e,0x47,0x9f,0x4f,0x80,0x2d,0x2d,0x75,0xb1,0xbc,
+  0xfc,0x67,0x83,0xa6,0xdf,0x7d,0x6b,0x1d,0x6e,0xe4,0xa6,0x5b,0x0a,0xeb,0x22,0xd8,
+  0x77,0xd2,0xdc,0xd3,0x1e,0x01,0xfb,0x64,0xa5,0x57,0x22,0x0b,0xa1,0x4b,0xd6,0xf0,
+  0xf3,0xb8,0x4d,0xb7,0xd9,0x50,0x51,0x5c,0x98,0x81,0xc1,0x32,0xc4,0x4f,0x59,0x62,
+  0xf8,0xb2,0x23,0xa7,0xdf,0xfb,0xca,0x18,0x34,0x2e,0x67,0x35,0x9b,0x37,0x0a,0x6e,
+  0x48,0xba,0x7e,0x37,0x6c,0xd6,0x67,0x63,0x7d,0xcd,0x8a,0x73,0xbc,0x4a,0x90,0x8e,
+  0x89,0xe1,0xfb,0x9d,0xe3,0xfc,0x51,0xc3,0xcf,0x1a,0xbc,0x1a,0x6c,0x8a,0x48,0xf5,
+  0xe2,0xd0,0xd3,0xb2,0x58,0x62,0xf9,0xcf,0x02,0x23,0xbe,0x03,0xea,0x77,0x08,0xb4,
+  0xde,0x16,0xa2,0xfb,0xc5,0x4d,0x5d,0xb5,0x71,0x91,0xf1,0x4f,0x7d,0xed,0x5e,0x81,
+  0xf1,0xcf,0xc7,0x94,0xdb,0x53,0x35,0x13,0xbb,0x9f,0x92,0x17,0x47,0xb5,0x1c,0x84,
+  0xb1,0x57,0xca,0x26,0xa4,0x2b,0xd0,0xa4,0x6c,0x4f,0xb1,0xbc,0x46,0x4b,0x38,0x16,
+  0xc8,0xe5,0x3f,0xa3,0x9c,0x86,0x9f,0xeb,0x8b,0x52,0x3c,0xab,0x73,0x35,0x31,0x9b,
+  0xe5,0xec,0xa9,0xd9,0x1a,0xee,0xa0,0xa5,0x95,0xc2,0x28,0xd4,0x43,0x80,0x5a,0xf6,
+  0x34,0xf2,0x9f,0x03,0x8e,0x2c,0x68,0xfa,0x3d,0x2d,0xfe,0x52,0xfe,0xf3,0x1c,0x9f,
+  0x89,0x38,0xa5,0xee,0x84,0x4c,0x31,0x36,0x9a,0xfa,0x9d,0x96,0x94,0x6b,0x52,0x19,
+  0x31,0x6b,0x29,0xd9,0xac,0x56,0x26,0x30,0xde,0x66,0x05,0x7d,0x5c,0x8f,0x58,0x01,
+  0x2c,0xff,0xe9,0xe8,0x74,0xdc,0x06,0xc3,0x34,0x93,0x75,0x76,0xf2,0xef,0x99,0xfa,
+  0xbd,0x6c,0x8f,0x0e,0x47,0xcb,0xfe,0x2e,0x2b,0x5e,0x45,0xae,0xf1,0x5d,0xe6,0x83,
+  0xfa,0x3c,0x15,0xa6,0xdf,0x91,0x76,0x3a,0xaf,0xf0,0x61,0xee,0x18,0xad,0xaf,0x76,
+  0x75,0xf2,0x60,0xe2,0xa7,0x77,0xbb,0x70,0x30,0x5d,0x37,0xd9,0xd3,0xe9,0xbb,0x25,
+  0xdd,0x95,0xa9,0xf4,0x23,0x70,0xd7,0x18,0xba,0x0a,0xf5,0xbb,0x84,0x73,0x19,0x16,
+  0x1f,0x27,0xde,0x48,0x52,0xae,0x8c,0xe3,0xa4,0xcc,0x71,0x71,0x61,0x9b,0xb4,0x0f,
+  0xea,0xa6,0x11,0xaa,0x98,0xf3,0x60,0xd0,0x0a,0x12,0xd1,0xe8,0x1b,0xd2,0xe7,0xf2,
+  0x6a,0x20,0xb3,0xb2,0x16,0x4e,0xd0,0xc1,0x94,0x2b,0xe3,0x30,0x73,0x02,0x49,0xd0,
+  0xf6,0x0a,0xc5,0x7d,0x34,0x21,0x5c,0xa2,0x4d,0xac,0x61,0xea,0xf7,0xb4,0xa4,0x95,
+  0x40,0x46,0x9d,0x33,0x7c,0x83,0x7c,0x1c,0xea,0x87,0x11,0x3f,0x47,0x0d,0xfc,0xdc,
+  0xa5,0xeb,0xf7,0x71,0x84,0x4d,0x8a,0xf1,0x88,0x11,0x35,0x32,0x99,0xcb,0x7f,0x0a,
+  0x87,0x85,0xba,0x61,0x71,0x10,0xf1,0x73,0x0b,0xe7,0xd3,0x72,0xa3,0xb9,0xfc,0x27,
+  0xdd,0xe7,0x0b,0x14,0xda,0xdd,0xa4,0x3f,0xb9,0x2b,0x22,0x83,0xbf,0x9e,0x0c,0x1b,
+  0xfe,0x49,0x8b,0x36,0x28,0x08,0x8d,0xef,0x3a,0x3f,0xae,0xf2,0x2b,0xa3,0xf1,0xc1,
+  0xb5,0xab,0x06,0xab,0xac,0xfc,0xe7,0xb7,0xaf,0xab,0xb3,0x72,0xf8,0x98,0xab,0xbe,
+  0x5b,0x55,0xaf,0xc7,0xc3,0x5f,0x40,0x20,0xb5,0xf8,0x67,0xd9,0x75,0xd8,0x80,0xdb,
+  0xbc,0x68,0x94,0x0f,0xb3,0x78,0x74,0xbf,0x33,0xa7,0xdf,0x55,0xef,0xac,0xb0,0x95,
+  0xca,0x8f,0x38,0x7a,0x48,0x40,0x3e,0x4c,0xeb,0xa6,0xed,0x39,0xfd,0x3e,0x6a,0x7b,
+  0x5d,0xf4,0xa3,0x8d,0x1c,0x90,0x70,0x6e,0xd9,0xa7,0x73,0x22,0x4b,0xbf,0x73,0x7b,
+  0x98,0x9b,0x28,0xc8,0x0b,0xf4,0x18,0x60,0xcf,0xf8,0x4c,0x1e,0x29,0x21,0xbe,0x9c,
+  0x83,0x10,0x9a,0xca,0xc1,0xfa,0x2a,0x58,0x3d,0x6e,0xd4,0xe2,0x9f,0x2f,0x31,0x9b,
+  0x0d,0x6b,0xb1,0x6a,0x96,0x2c,0x9f,0xce,0xcf,0x7f,0xc2,0x1e,0xe5,0xcd,0x92,0x50,
+  0x7a,0xd5,0x10,0xcf,0xea,0x32,0x8c,0x43,0xf3,0xa6,0x7e,0x3f,0x63,0x2b,0x47,0x7a,
+  0xec,0xcb,0x22,0x7e,0x06,0x90,0x9b,0xd6,0x4d,0xcf,0xe1,0x9f,0x0f,0xd4,0x64,0x84,
+  0x6a,0xc9,0x4f,0xc9,0x36,0x09,0xbd,0xfa,0x72,0x1e,0xff,0x9c,0xe6,0x2a,0x60,0x7b,
+  0x7a,0x41,0xbb,0x18,0x2d,0x60,0xe0,0x55,0x9b,0xe5,0x3b,0x23,0x9f,0x18,0x7d,0x51,
+  0xd1,0xa9,0x4c,0xd3,0xa5,0x72,0xa0,0x87,0xdf,0xae,0xe2,0xbb,0x55,0x5d,0x4b,0xf8,
+  0xb7,0x4c,0xfd,0x3e,0xff,0x29,0xf8,0x98,0xbb,0x47,0x71,0xa9,0x8e,0x3f,0x83,0x0f,
+  0x24,0x2d,0xcf,0x60,0xea,0xf7,0x01,0x96,0x9f,0x40,0x9f,0x98,0xff,0x22,0x72,0x53,
+  0x23,0xa6,0x1e,0x37,0xf1,0xb3,0x64,0xa7,0x70,0x90,0xd5,0x8f,0x36,0xda,0xad,0x8d,
+  0x71,0x51,0xd2,0xd7,0x47,0xe1,0x3b,0x23,0x3f,0x4e,0xd6,0xa6,0xa3,0x9d,0xa4,0x42,
+  0x9b,0x0b,0xfa,0xae,0x6a,0xf1,0x4f,0x2d,0xff,0x39,0x21,0xde,0x4d,0x9c,0xac,0x91,
+  0x9d,0x53,0x3f,0xea,0x81,0xab,0x42,0x98,0xd6,0xee,0x21,0xac,0xb6,0x1b,0x1e,0x70,
+  0xe5,0xeb,0xf7,0xac,0x30,0x43,0x19,0x6c,0x76,0xc7,0x2d,0xfc,0xcc,0xe9,0x77,0xf2,
+  0x73,0x84,0xcd,0x55,0xcf,0xf3,0x8c,0x7f,0x36,0x29,0x81,0x9b,0xf8,0x27,0x57,0x17,
+  0x8b,0xee,0x24,0x13,0x02,0x72,0xcc,0x87,0xc5,0x39,0xfc,0x93,0xfc,0x80,0xd6,0x2a,
+  0x85,0xe3,0xee,0x11,0x8d,0x7f,0xce,0xc9,0x7f,0x3a,0xe9,0x26,0xa8,0x8d,0xfb,0xd7,
+  0x92,0x91,0x5b,0x50,0xc7,0xcd,0xc9,0x7f,0x16,0xc5,0x61,0x12,0xc2,0x9e,0x55,0xf7,
+  0x7e,0x1e,0xf9,0x27,0x17,0x06,0x67,0x8e,0x7f,0x6a,0xf5,0x23,0xb0,0xea,0x32,0xcd,
+  0xf9,0xfc,0xb3,0xcf,0x76,0x99,0xbc,0x0e,0xf7,0xb4,0x39,0xc7,0x1d,0xd5,0xac,0xef,
+  0x7e,0x04,0xaf,0x0b,0xb9,0xfa,0x11,0xca,0x76,0xd4,0xef,0x04,0x71,0x07,0x81,0x94,
+  0xe1,0xa7,0xa5,0xdf,0x6d,0x23,0x0a,0xab,0x1f,0xd9,0xdd,0x3e,0x21,0x8d,0x40,0xaa,
+  0x14,0xce,0xe1,0x9f,0x25,0x5b,0x10,0xe7,0x11,0xde,0xab,0xb9,0x43,0xc6,0x1a,0x4c,
+  0xfe,0xc9,0xea,0x47,0x42,0xa3,0x52,0xc3,0x72,0xbf,0xc8,0x3f,0x5b,0xbe,0x8d,0xf8,
+  0x69,0xf8,0x75,0x3b,0xab,0x1f,0xe1,0x3c,0x9d,0x38,0x4f,0xe9,0x8a,0xd0,0x14,0xbd,
+  0x99,0x7f,0x42,0x98,0xab,0x65,0xfc,0x13,0x6d,0x2d,0x14,0xe5,0xf1,0x4f,0xae,0x81,
+  0x0c,0xd3,0xc5,0xd4,0x99,0x25,0x7e,0xee,0x45,0x6e,0x31,0x15,0x6f,0xe2,0x9f,0x29,
+  0xb6,0x7d,0xec,0x4e,0x89,0xbd,0x5b,0x7f,0x30,0x32,0x6c,0xd5,0x8f,0x24,0x94,0x29,
+  0x68,0xeb,0x18,0x29,0xa7,0x07,0x71,0x0d,0x62,0x07,0x98,0xfc,0x73,0x40,0x2c,0x86,
+  0xd7,0x68,0x73,0x3a,0xd0,0x7e,0xfb,0x1d,0xe8,0x2f,0xcb,0x11,0x3f,0x2b,0x2d,0xfe,
+  0x79,0x2b,0xd3,0x6a,0x61,0xa5,0x38,0xcd,0x7f,0x98,0xbe,0xc6,0xce,0x5d,0x64,0xe6,
+  0xd4,0xdf,0xaf,0xd1,0xe6,0x89,0x00,0xe2,0x27,0xd3,0xef,0xd9,0xa2,0x7c,0xfe,0x99,
+  0x81,0xee,0x3e,0x0c,0x35,0x7d,0xf6,0x3a,0xd2,0x4d,0x6b,0xdb,0xc5,0x3f,0xe1,0xcf,
+  0x9b,0x36,0x83,0x97,0xe0,0xfb,0x25,0xb5,0x3d,0x3d,0x8f,0x90,0x72,0xf1,0x9b,0x72,
+  0xed,0xf1,0xff,0xb4,0x31,0xaf,0xfe,0x3e,0xc2,0xd2,0x90,0xb1,0x68,0x5a,0xab,0x1f,
+  0x05,0xe4,0x1e,0xe6,0x9f,0x7a,0x1f,0xc3,0xcf,0x0f,0x28,0xab,0xfb,0x3a,0x9a,0xe0,
+  0x6d,0xa1,0x89,0xe9,0xb1,0x1c,0xff,0x9c,0x64,0xdb,0x75,0xd8,0xf5,0x1c,0xf2,0xcf,
+  0x0f,0x40,0x23,0x24,0x7b,0xcc,0x1a,0xa6,0xf4,0x09,0x9c,0x92,0xef,0x4a,0x6f,0x9b,
+  0xbe,0x9d,0xf1,0x4f,0xbc,0xc1,0x74,0xa9,0xc5,0x3f,0x61,0x15,0xdb,0xef,0x13,0xe2,
+  0xfe,0x52,0x0d,0x5f,0x64,0x3f,0x6a,0xf4,0x1c,0x7e,0x2a,0xbd,0xb0,0x10,0x21,0x35,
+  0xa1,0x15,0xb1,0xb3,0x22,0x6a,0x7b,0xc3,0x9e,0x76,0x41,0x84,0x5e,0x8f,0xfc,0x9a,
+  0xdf,0x93,0xd8,0x46,0xf7,0x31,0xff,0x0c,0x5a,0xef,0x01,0xf1,0x93,0x9c,0xa8,0x5e,
+  0xda,0x13,0x38,0xc0,0xbf,0x24,0x5c,0x5b,0x17,0x8e,0xb6,0x0d,0xf2,0xd9,0x02,0x43,
+  0xbf,0x7f,0x1b,0xb9,0x70,0x50,0x83,0x9c,0x40,0x7c,0xb6,0x21,0x2c,0xac,0xde,0xdb,
+  0x3a,0xf9,0x64,0x5e,0xfd,0x88,0x86,0xd3,0xc8,0x3f,0xb3,0xa8,0xc4,0x43,0x59,0x57,
+  0x9e,0x7e,0x07,0xe4,0x9f,0xdd,0x75,0xbb,0x1c,0x43,0xca,0x05,0xd8,0x42,0x77,0x6b,
+  0xf9,0x4f,0x21,0x8f,0x7f,0xea,0x35,0xb7,0x31,0x76,0xb6,0xe9,0xe6,0xfc,0x27,0x4e,
+  0x3d,0xa5,0xd5,0xc0,0xb6,0xfc,0x72,0xfe,0x13,0x5f,0x69,0x46,0x0b,0x35,0xea,0xa8,
+  0x56,0x10,0xca,0xe6,0xea,0x47,0x5a,0xcc,0x71,0x4c,0x93,0xeb,0xc2,0x4f,0x52,0xcd,
+  0xea,0xea,0x9b,0xeb,0x47,0xe1,0x94,0xc6,0xf5,0x67,0x94,0x65,0x5a,0xcd,0xdb,0xd0,
+  0xda,0xaa,0x2d,0x60,0xe6,0x93,0xc7,0x18,0x39,0xd2,0x9e,0x67,0xf8,0xd9,0xa8,0xe0,
+  0x34,0xe6,0xe9,0x56,0xa5,0x8c,0x9e,0x3b,0xbc,0x0a,0x26,0xff,0xac,0x60,0xfc,0xd3,
+  0x8f,0xb2,0xfd,0x1d,0x78,0x89,0xd5,0xbc,0x9f,0x20,0xd7,0x65,0x7d,0x5c,0xd4,0x5b,
+  0x4c,0x11,0x36,0x07,0xbe,0xd2,0xd8,0x7a,0x12,0xa6,0xfb,0x97,0x4e,0xe5,0xeb,0xf7,
+  0xf2,0x3d,0xec,0x95,0x26,0x5d,0x1f,0xf1,0xd7,0x5b,0xa6,0x19,0x7e,0x7e,0xc4,0x8f,
+  0x3f,0xa9,0xcf,0x13,0xf9,0xa7,0xf8,0x75,0xca,0xe2,0x43,0x6b,0x16,0x1f,0xa0,0xd7,
+  0xdf,0xa9,0x81,0x9f,0xac,0x7e,0x04,0x95,0xb4,0x97,0x69,0xa0,0xfd,0x28,0x86,0x7e,
+  0x17,0xf1,0xb3,0x5a,0x1f,0xa7,0xf3,0xcf,0xca,0x34,0xab,0x65,0xc1,0x01,0xbd,0xfe,
+  0x3e,0xb7,0x7e,0x24,0x0f,0x6b,0xb6,0xce,0xe8,0xb6,0xb6,0xf0,0x13,0x58,0xfd,0x68,
+  0x5f,0xca,0x91,0x46,0x53,0x7d,0x92,0x0e,0xcd,0xa9,0xbf,0x1b,0x9c,0x68,0x9e,0x56,
+  0x7f,0x17,0x1a,0x6f,0xae,0x1f,0xe5,0x61,0xd6,0x32,0x65,0x4e,0xfd,0x1d,0x39,0x26,
+  0xa9,0x6b,0xd9,0xce,0xf4,0xed,0xde,0x5f,0x59,0x7f,0x37,0xb5,0xef,0xcd,0xf5,0x77,
+  0xd8,0x2b,0x68,0xa9,0xc6,0x11,0x7a,0x48,0x07,0xa8,0x5c,0xfd,0x48,0x3f,0x0b,0x70,
+  0x3b,0x6d,0x65,0x0d,0xb7,0x96,0xff,0xe4,0x25,0xa3,0x4f,0x83,0x4d,0xb5,0x38,0xc5,
+  0x5f,0x8e,0xde,0xd0,0x27,0x75,0x71,0x9e,0xbe,0x86,0x21,0x1b,0xcb,0x8d,0x86,0x55,
+  0x84,0xcd,0xcb,0xf2,0xeb,0x28,0xac,0x8b,0x73,0xdc,0x54,0xcb,0x7f,0x42,0x1d,0x2b,
+  0xbb,0x9f,0x43,0xb2,0x5e,0xc3,0x0e,0xd0,0xbc,0x63,0xe2,0xa7,0xc6,0x3f,0xeb,0x18,
+  0x6c,0x1e,0x05,0x06,0x96,0x5a,0xfe,0xd3,0xaa,0x1f,0x49,0x6c,0x0d,0xde,0x94,0xef,
+  0x7d,0xd8,0x22,0x6b,0xc5,0xb0,0xbc,0xfa,0x91,0x78,0xc5,0x16,0x8e,0x3f,0x95,0x2a,
+  0x9d,0x90,0x8e,0xe8,0xcf,0xb3,0xea,0x47,0x31,0xcd,0x66,0xf7,0x9e,0xd2,0x6c,0x46,
+  0x7f,0x45,0xfd,0x88,0x1d,0x71,0xd0,0xce,0x3a,0x84,0xf2,0xf5,0xbb,0x28,0xf8,0xc5,
+  0x17,0x99,0x0f,0xa6,0x23,0xa3,0xf0,0x22,0xa9,0x62,0xfa,0x3d,0xbf,0x7e,0x64,0x9e,
+  0x63,0x61,0xb9,0x6d,0xb6,0xa1,0xf2,0xea,0x47,0x92,0x11,0x66,0x51,0x33,0xc3,0x02,
+  0x8a,0x8d,0x49,0x83,0x7f,0xb2,0xfa,0x91,0x51,0x7f,0x7f,0x07,0x1b,0x77,0xa6,0xb1,
+  0x71,0x5e,0x7f,0x1c,0x88,0x45,0x3a,0xff,0xd4,0xf6,0xdf,0x25,0x68,0x44,0x67,0x2c,
+  0x1d,0xf6,0xe8,0xf3,0x8c,0x0b,0x9f,0xc0,0xe1,0xae,0xdf,0xc8,0xce,0x1b,0xc2,0x30,
+  0x74,0x2a,0x15,0xea,0x77,0x0e,0xe5,0xce,0x2f,0xc1,0xf6,0x24,0xca,0xf6,0xf7,0x99,
+  0x0f,0x2a,0xdd,0x78,0x4f,0xd4,0x40,0xe7,0x8d,0xb3,0x46,0x12,0xec,0x54,0xf4,0xb9,
+  0x44,0x5e,0x6f,0xdb,0x01,0xeb,0x7a,0xec,0x1d,0x05,0x23,0x73,0xe3,0x3b,0x5b,0xc3,
+  0x49,0xe8,0x56,0xfa,0x29,0xea,0xe2,0x33,0x79,0xf5,0x23,0xd4,0x8d,0x59,0x6d,0xdf,
+  0x9e,0x48,0x85,0x28,0x62,0xf9,0x05,0xc3,0xd6,0x19,0xbd,0x7e,0x34,0xcc,0xfa,0xa2,
+  0xd7,0xa4,0x30,0xb5,0xe5,0xf8,0x67,0x97,0x74,0xdd,0x66,0xc8,0xf6,0xb3,0x70,0x0a,
+  0x75,0x15,0x2b,0x2a,0x9b,0xf5,0xa3,0x24,0xf2,0xcf,0x82,0x00,0x93,0xed,0x53,0x88,
+  0xd7,0xbb,0xf1,0x9e,0x24,0xaf,0x7e,0xc4,0xf8,0x27,0xa3,0xa4,0x53,0xac,0x16,0x42,
+  0xf3,0xeb,0xef,0x18,0xb4,0xf7,0x29,0x48,0xe7,0x42,0x89,0xb1,0xd1,0x5e,0x31,0xfd,
+  0x4c,0x9e,0x7e,0xa7,0xde,0x0d,0xea,0xe1,0x68,0x78,0x64,0xd5,0x41,0xfe,0x43,0x7a,
+  0x22,0x1e,0xea,0x2b,0xfe,0xf1,0xf7,0xac,0xfa,0xd1,0xb7,0xa7,0x46,0x70,0xbf,0x9f,
+  0x61,0xb5,0x79,0xf1,0x92,0x7f,0x39,0x2d,0xbe,0x98,0x57,0x7f,0xbf,0x4c,0x5e,0x4d,
+  0x35,0x83,0xf3,0xbd,0xee,0x26,0xe9,0x94,0x96,0x0f,0xe1,0xa7,0x13,0xfa,0xfa,0x54,
+  0xe9,0x43,0xb9,0x57,0xc6,0xb9,0x24,0xc9,0x62,0x96,0xff,0xd4,0xf0,0x33,0x61,0xe2,
+  0x67,0x56,0xed,0x96,0x03,0x6a,0x21,0x90,0x2d,0xa6,0x7e,0xbf,0xc8,0xe9,0xf6,0x54,
+  0xcb,0x58,0x19,0xa7,0x6e,0xda,0x9f,0xbe,0x3f,0xcd,0xf5,0x6a,0xc0,0xe6,0x9b,0x36,
+  0x6c,0x4d,0x3d,0x54,0x39,0x91,0x0a,0x67,0x8b,0xf6,0x74,0xbf,0x40,0x4e,0xe8,0xf9,
+  0x64,0xd5,0xc8,0xa3,0x7c,0x04,0x2f,0x88,0xb3,0xec,0x38,0xd0,0x5b,0xfc,0x13,0x8a,
+  0x51,0x3f,0x9a,0x36,0x73,0xd4,0x52,0x3f,0x41,0xd9,0x3e,0xee,0xa4,0xa5,0x4e,0xd6,
+  0x60,0xe3,0xce,0x9a,0xfc,0x53,0x58,0x3e,0x8a,0xa6,0x7a,0x43,0xfc,0x6b,0x14,0xce,
+  0xbd,0xb0,0x9b,0x39,0xce,0x55,0xdd,0x2c,0xec,0xfc,0x27,0x61,0xf9,0x25,0xa4,0x18,
+  0xc5,0xac,0xd0,0xa9,0xd5,0x8f,0xa8,0xde,0x97,0xe1,0x2a,0x84,0x1d,0xb4,0x72,0x42,
+  0x7c,0xd3,0x5e,0x01,0xdf,0xd5,0x31,0xeb,0x63,0xa3,0xef,0x7e,0x91,0x90,0xbf,0x23,
+  0x41,0x75,0x55,0xb0,0x54,0x84,0xb7,0xa5,0xe0,0x11,0xe4,0x9f,0xa6,0x7e,0x8f,0xcc,
+  0x1f,0x52,0x66,0xa5,0x97,0xd5,0xc5,0x1d,0xfc,0x99,0xf8,0x3f,0x69,0xf3,0x2c,0x1d,
+  0x37,0x63,0xf8,0x6f,0x4d,0xb2,0xf3,0x1a,0x6a,0x45,0xaa,0xd4,0x8f,0x8d,0x46,0xbd,
+  0x7e,0xa4,0xf7,0x8d,0x3e,0xfd,0x7c,0x62,0x33,0x59,0xac,0x16,0xc5,0x88,0x9d,0x6e,
+  0x36,0xf8,0xa7,0xc9,0xf9,0xe0,0x9b,0x0a,0x3b,0xbf,0x74,0x7f,0xc3,0x6d,0x15,0xb0,
+  0x99,0x2e,0xd2,0xf8,0xa7,0x64,0xfa,0xe7,0xeb,0xd0,0x4d,0x02,0xd3,0x62,0x70,0x77,
+  0xb1,0xc8,0xc3,0x06,0x1d,0x3f,0xf5,0xbe,0x49,0xdb,0x10,0x1c,0xa7,0x77,0x64,0xec,
+  0xd9,0xaa,0x7b,0x0a,0xee,0x67,0x7b,0x25,0xcd,0x5f,0xb4,0xf8,0xa7,0x2a,0xcf,0x48,
+  0x61,0x27,0x6e,0x65,0x35,0x6e,0xe9,0x77,0xd9,0xf0,0xa5,0xf7,0xe9,0x31,0xa2,0x71,
+  0xa9,0x85,0xc8,0x3f,0xeb,0x34,0xfc,0x34,0xdf,0x91,0xf0,0xfb,0xf6,0x2d,0xf3,0xd8,
+  0xb1,0x1e,0xfb,0x42,0x33,0xc7,0x99,0x35,0xd6,0xee,0x15,0x16,0xe0,0x8f,0x02,0x5a,
+  0x8d,0x48,0xb1,0xf2,0x9f,0x60,0xdc,0x53,0x48,0x68,0xb4,0xd3,0x4d,0xb4,0xc6,0x1c,
+  0xfc,0x14,0xd7,0x45,0x46,0xd7,0x84,0x3d,0x7d,0x9b,0xea,0xad,0xfc,0xe0,0xc7,0xc4,
+  0xc8,0x7f,0x16,0xbd,0x81,0xb0,0xd9,0x3c,0x82,0x61,0xe8,0xb2,0x49,0x44,0xdf,0x9b,
+  0xa7,0xfb,0xa7,0xc8,0x7d,0xac,0x1e,0x83,0x65,0x6d,0xce,0x3e,0xfe,0x1b,0x5a,0x9e,
+  0x81,0x60,0x1f,0x31,0xf3,0x9f,0x3f,0x23,0x54,0x0c,0x08,0xe2,0x30,0x72,0xef,0x9b,
+  0xeb,0x47,0xb6,0x11,0x95,0x4d,0xa1,0xe7,0xa1,0x84,0x0d,0x76,0xe9,0x73,0x79,0xcb,
+  0xe2,0x9f,0x7f,0x0d,0x3f,0xa0,0x75,0x4a,0xcf,0x69,0x7b,0x35,0xfc,0x40,0x5b,0x03,
+  0x32,0x05,0xbd,0x2f,0xfd,0x17,0x13,0xe4,0x18,0x17,0x6e,0xf3,0x3f,0xc7,0x2f,0x20,
+  0x7f,0x00,0xe1,0x96,0xef,0xe4,0xe7,0x3f,0x93,0xca,0x9b,0xd0,0x14,0x77,0x79,0xf9,
+  0xa3,0xf4,0x4d,0xed,0x20,0x53,0xd5,0x69,0x83,0x83,0x21,0x7e,0x26,0xd8,0xf9,0x4f,
+  0x27,0x85,0x4a,0xa2,0xaf,0xaf,0x6a,0xd8,0xec,0xc3,0xd0,0xb5,0x95,0xf3,0x75,0x21,
+  0xed,0xac,0x41,0x61,0xd6,0xa8,0xe5,0x3f,0xab,0x75,0xbb,0xf8,0x6d,0x0f,0x70,0xa5,
+  0xcc,0x3f,0x1b,0xdc,0xdb,0x59,0x7e,0x5e,0xcf,0x7f,0xea,0x57,0x25,0x57,0xee,0xdb,
+  0x9c,0xae,0xa4,0xfe,0xf5,0xe4,0x29,0xf8,0xbe,0x76,0xde,0x2d,0xa2,0x2a,0xc6,0xb8,
+  0x9e,0x30,0x79,0x8d,0x2e,0xc9,0x3a,0x67,0x7a,0xbf,0x43,0xfe,0x37,0x02,0xe9,0x6b,
+  0x9d,0x55,0xc3,0xb2,0xf1,0x1e,0xe6,0x23,0xff,0x0c,0x17,0x53,0xd7,0xee,0xd6,0x0d,
+  0xec,0x5c,0xa5,0xa6,0x81,0x92,0xc6,0x3e,0xb2,0x7d,0x1c,0x79,0x1b,0x69,0x27,0xda,
+  0x33,0x0c,0xda,0x7e,0x1f,0xaa,0x1a,0xdf,0xad,0xf7,0xfd,0xa0,0x64,0x73,0x7a,0x33,
+  0xad,0xed,0x11,0xa3,0x89,0x72,0x46,0x7c,0xd5,0x95,0x4f,0x90,0xf3,0x92,0xe9,0x9f,
+  0x49,0xcd,0x65,0xa3,0x31,0xf2,0xb0,0xfc,0x7d,0xe6,0xbb,0x1b,0xc9,0x94,0x95,0xff,
+  0x9c,0x92,0x7a,0x21,0x90,0x11,0x81,0x7c,0x01,0xb1,0xc0,0x89,0x6b,0x88,0x98,0xfe,
+  0x39,0x50,0x36,0x85,0xf0,0x57,0xa7,0xfa,0x97,0x3a,0x1e,0x23,0x1f,0xa0,0xde,0x74,
+  0x65,0xbe,0xf8,0x9e,0xe9,0x67,0x68,0xfc,0x0f,0x12,0xe1,0x27,0xd1,0x65,0x11,0x64,
+  0x49,0x58,0xbd,0x03,0x85,0xbc,0xd1,0xc7,0xc5,0xae,0x8b,0xef,0x72,0x21,0xfc,0x51,
+  0x77,0x00,0x4e,0x69,0x7b,0x4c,0xce,0x1a,0xcf,0x53,0x85,0xaf,0xe2,0xf3,0x76,0xa3,
+  0x19,0xed,0x4e,0x5c,0x9f,0x46,0x9c,0xa6,0x0d,0xbb,0x50,0xa8,0x86,0xbf,0x62,0x14,
+  0x2a,0x45,0x02,0xb4,0x57,0x3b,0x44,0xe9,0x36,0x7d,0x57,0x84,0xea,0x23,0xdd,0x10,
+  0xa7,0x9a,0x2e,0x7e,0x56,0xb3,0xf5,0x33,0xa6,0x7f,0x2a,0xe2,0x57,0x07,0xde,0x85,
+  0xd0,0x11,0x47,0x0a,0xf5,0xad,0x5e,0x9f,0xe6,0x4d,0xde,0xba,0x7b,0xfe,0x14,0xcc,
+  0x4a,0xcd,0x5d,0xae,0x23,0xfc,0x65,0xa3,0xae,0xfd,0x68,0xb6,0xd2,0xd4,0xda,0x17,
+  0x30,0x7c,0x0d,0x9e,0xab,0x53,0xf9,0x10,0x1c,0xe3,0xea,0xb3,0x81,0x99,0xbc,0xfa,
+  0xd1,0x05,0x89,0x95,0xdd,0x31,0xbe,0xa7,0x71,0xd3,0x1c,0x40,0x81,0xac,0x64,0x21,
+  0xc7,0x3f,0xd9,0x51,0x44,0x3b,0x52,0x09,0xa9,0xdb,0xd6,0x7e,0x44,0x0c,0x16,0xcc,
+  0x39,0xff,0x49,0x6b,0x46,0x06,0x20,0x42,0x9d,0x5b,0x68,0x31,0x12,0xbf,0x1c,0xff,
+  0x44,0x7b,0x5e,0x3a,0xd6,0x78,0x66,0x7b,0xc6,0xe1,0x23,0x47,0x68,0x03,0x3b,0xd0,
+  0x69,0xd6,0x8f,0xa6,0x35,0xfd,0x7e,0x50,0x5d,0x7d,0xbd,0xfb,0x17,0xd2,0x0d,0xb8,
+  0x4b,0x3b,0xff,0x69,0xd5,0x8f,0xd0,0xc4,0xde,0x90,0xea,0xdc,0xef,0xa8,0x84,0xb7,
+  0xe5,0xd0,0xb0,0x2b,0x77,0x7e,0xe9,0x8c,0x2d,0x20,0x1e,0x52,0x14,0x8c,0x39,0x76,
+  0x36,0xcf,0xd0,0xf8,0xca,0x4c,0xde,0xf9,0xf9,0x55,0x30,0x08,0x69,0x75,0x91,0x44,
+  0x04,0x78,0xfa,0xa1,0x6d,0x4c,0xbf,0x77,0x18,0xf6,0x64,0xfa,0xfd,0x95,0x74,0x55,
+  0xf6,0xd6,0xdb,0x12,0x07,0x94,0xcd,0xbb,0x17,0x4d,0x3a,0x66,0x0a,0xa2,0x46,0x5f,
+  0x14,0xf5,0xd1,0xc5,0xb4,0x9c,0xbd,0xf7,0x36,0x87,0x1d,0xde,0xa2,0x4d,0x59,0xd7,
+  0x8b,0xfc,0x1a,0x4b,0xbf,0xef,0x51,0x5e,0x2c,0x59,0x3e,0x56,0xfc,0x2c,0x7f,0xa6,
+  0xed,0x2a,0x87,0x5c,0x78,0x6f,0xbe,0x7e,0x17,0xae,0x32,0x5c,0xca,0x38,0x64,0x78,
+  0x1d,0x06,0xd5,0xd5,0x0d,0xad,0x24,0xa7,0xdf,0x3d,0x2c,0xff,0x29,0x4a,0x05,0x3b,
+  0xdd,0x9b,0xf5,0x64,0xbc,0xdb,0xd2,0x32,0xdf,0x41,0xda,0xf9,0xb5,0x20,0x74,0x92,
+  0x10,0x74,0xd3,0x75,0xd9,0xdb,0x3b,0xad,0x1c,0x12,0x8b,0xef,0x83,0x10,0x58,0xeb,
+  0x3f,0x44,0x06,0x8c,0x62,0x03,0xb9,0xcd,0xe4,0x9f,0x25,0x03,0xf0,0x09,0x34,0x67,
+  0x9c,0x53,0x8e,0x7b,0xe8,0x49,0xbd,0x90,0xd4,0x98,0x57,0x3f,0xd2,0x61,0xb3,0x3b,
+  0x2b,0xeb,0x42,0x9e,0x9f,0x53,0x7f,0x87,0x70,0xfb,0xaa,0x3e,0x9e,0xe5,0x3f,0x1f,
+  0x67,0x40,0x7a,0xd3,0xf9,0x4f,0xe5,0x0f,0xfb,0xe4,0x6a,0xa1,0x4b,0x68,0x57,0xc4,
+  0x9b,0xea,0xef,0x50,0x17,0x13,0x0f,0x90,0x00,0xc1,0xa0,0x15,0xbd,0xf9,0xfc,0x12,
+  0x45,0xa8,0x7a,0x06,0x6d,0xdd,0x85,0xbc,0xce,0x9f,0x57,0x7f,0x2f,0xd2,0x53,0x08,
+  0xce,0x4d,0x8e,0xca,0xc8,0xe8,0x83,0x3e,0x6e,0xae,0x7e,0x87,0xff,0xc6,0x2d,0x57,
+  0x5c,0x3f,0xe5,0xdf,0x80,0x1b,0x52,0xb3,0xb2,0x78,0xae,0x7e,0x3f,0x05,0xac,0xfe,
+  0xde,0x5b,0x0d,0x4f,0x79,0xeb,0x95,0xd5,0xe3,0xfc,0x49,0x4b,0xbf,0xc7,0x35,0xd8,
+  0xec,0x49,0x46,0xfc,0x64,0xab,0x5c,0x73,0x13,0x7e,0xb2,0x3c,0x99,0xd2,0xee,0x4e,
+  0x08,0xbb,0xb6,0xc8,0x1a,0x17,0xce,0xaf,0x1f,0x6d,0x81,0x62,0xc5,0x9f,0xd1,0xce,
+  0x59,0xd5,0x28,0xb7,0xcf,0xd1,0xef,0xc2,0xb1,0x3f,0xaa,0x88,0x6c,0x4b,0x15,0x2e,
+  0x94,0x8e,0xc5,0x06,0x5b,0x56,0xe7,0xe1,0x27,0xd7,0x4f,0x0e,0x31,0xd8,0x7c,0xbe,
+  0xea,0x7d,0xf8,0x15,0xf5,0xa3,0x19,0x25,0x24,0x39,0xe9,0x17,0x71,0xa1,0xca,0xa0,
+  0xe0,0xcc,0x3f,0xff,0x29,0x0a,0x2f,0xb7,0x2c,0xda,0x62,0x9f,0x70,0xfb,0xe1,0x00,
+  0x54,0xa5,0x0a,0xe6,0xea,0xf7,0xbd,0xb2,0x9f,0x8a,0x83,0x8c,0x7f,0x52,0xf9,0xf4,
+  0x96,0x5c,0xfd,0x28,0xcd,0x95,0xc3,0xc1,0xe4,0x62,0x6a,0x8f,0x93,0xf2,0xfb,0xf6,
+  0x8b,0x95,0xe7,0xde,0xca,0xd5,0xdf,0x07,0xc4,0x0a,0xf8,0x31,0xbd,0x3b,0xbb,0x6a,
+  0x6d,0xd5,0x3b,0xf0,0xdf,0xe9,0xc6,0xac,0xad,0x93,0xcf,0xab,0x1f,0x31,0xda,0xa9,
+  0x3a,0xfe,0x86,0x9f,0x92,0x67,0xc0,0xc3,0xce,0x87,0xe4,0xeb,0xf7,0xe7,0xd2,0x0d,
+  0xfd,0x5f,0xf8,0x09,0xff,0x58,0xdb,0x6b,0xcf,0x86,0x26,0x9d,0x0d,0x2b,0xbd,0x26,
+  0xd6,0x71,0xdf,0x19,0x19,0x1c,0xaf,0x4c,0x8b,0x35,0xa4,0x4e,0x7e,0x32,0x2d,0xf7,
+  0xfb,0x1b,0xed,0x35,0x96,0x7e,0xdf,0x09,0x7f,0x21,0x2e,0x3a,0xe3,0x28,0x21,0xe5,
+  0x9b,0x76,0x70,0x9f,0x57,0x1d,0x8f,0x13,0x6a,0xe6,0x3f,0x99,0x7f,0x72,0xb2,0x5a,
+  0xb8,0x88,0x38,0x0b,0x12,0xb0,0x10,0xd0,0x3f,0x53,0xa6,0x7e,0x2f,0xd1,0xce,0xcd,
+  0x8c,0xef,0x18,0xa8,0x59,0x0e,0xc7,0xd3,0x07,0x94,0x3f,0xcc,0xf0,0x2f,0xe4,0xce,
+  0x7f,0xc2,0x95,0xf5,0x61,0xb5,0xb8,0x1f,0xf1,0x73,0x46,0x69,0x54,0xc4,0x0c,0xd7,
+  0x6e,0x9e,0xa1,0x93,0xae,0x73,0x37,0xa0,0x5e,0x79,0x20,0x66,0x6b,0x92,0x4f,0xc2,
+  0xe7,0xe3,0xce,0xe9,0x56,0x35,0xaf,0x7e,0xb4,0x57,0x4d,0x77,0x6e,0xef,0xbf,0x2d,
+  0x00,0x54,0x59,0x16,0x2f,0x9a,0x7b,0xfe,0xf3,0x10,0xf5,0xc5,0xa3,0xec,0x7b,0x84,
+  0x17,0x94,0xba,0xa8,0x88,0xf8,0x59,0x62,0xf8,0xa7,0xc7,0x09,0x43,0x1e,0xdf,0x4a,
+  0x7b,0x95,0xfd,0x29,0x92,0x40,0xc7,0xb9,0x35,0x4f,0xbf,0xdb,0x36,0x28,0x87,0x94,
+  0xd0,0x5a,0xe7,0xe9,0x82,0x97,0x92,0xe7,0xe5,0xf0,0x1a,0xe7,0x01,0x5e,0x9d,0x67,
+  0xe8,0xf7,0x07,0xa7,0x94,0x99,0x78,0x73,0xa4,0xf8,0xfd,0xd2,0x3f,0x53,0xae,0x96,
+  0xdf,0x69,0x77,0x7d,0x9c,0x77,0x7e,0x7e,0x1a,0x35,0x60,0x3d,0xb8,0x54,0xbe,0x03,
+  0xc6,0x58,0x00,0x1d,0xe7,0x83,0x29,0xe3,0xfc,0x92,0xf7,0x3c,0xf4,0x50,0x9f,0xec,
+  0xe8,0x21,0x3e,0x6c,0xd4,0xc8,0xf6,0x3e,0x12,0x34,0x6b,0xde,0x90,0x86,0x5d,0x44,
+  0x86,0x95,0xe0,0xd3,0x41,0xbf,0x30,0x48,0x42,0xc6,0x5e,0x51,0x85,0x01,0x3f,0xca,
+  0x76,0x74,0x67,0x0c,0x5e,0xe8,0xe0,0x82,0x3d,0xe3,0x36,0xc7,0x71,0x65,0xe7,0xd8,
+  0xe7,0x43,0xf1,0xd5,0x19,0xc7,0x42,0x72,0x8c,0x2e,0x8b,0xa3,0x9f,0x81,0x11,0x57,
+  0xb2,0x5c,0x1f,0x7c,0x0c,0xcd,0xeb,0x11,0x36,0x3f,0x56,0xfe,0x39,0xd5,0x18,0x77,
+  0x29,0x8e,0x1c,0xff,0xdc,0x25,0x5f,0xf3,0x84,0x14,0x67,0x90,0x17,0x84,0x37,0x49,
+  0x50,0x09,0xa4,0x79,0x8f,0x75,0x7e,0xa9,0xa6,0xaf,0x37,0xe1,0x53,0xc4,0x21,0x56,
+  0xd3,0x40,0x4d,0x89,0x81,0xbe,0x91,0x82,0x31,0x97,0x7b,0x49,0x86,0xca,0x54,0xe4,
+  0x50,0xe1,0x3d,0x03,0xd8,0x90,0x48,0x83,0xd1,0x17,0x97,0xbe,0x0c,0x94,0xca,0x69,
+  0x51,0x24,0x2f,0x8a,0x09,0xf6,0xfd,0x91,0xb7,0x20,0x9c,0xd4,0xfb,0xa2,0xe2,0x0a,
+  0xf8,0x88,0x06,0x69,0x80,0x73,0x0c,0xc0,0x69,0xc8,0xa4,0x9d,0x4b,0x1c,0xb7,0x99,
+  0xfa,0xbd,0x6c,0x9b,0x7a,0x45,0x0e,0x27,0xe7,0x51,0xae,0x5d,0xb9,0x8a,0xba,0xc3,
+  0x75,0xa8,0x75,0xdc,0xd2,0x6a,0xfd,0xce,0x61,0x08,0x65,0xd9,0x67,0x16,0xec,0xfb,
+  0x23,0x15,0x31,0x6b,0xd8,0x38,0x03,0x12,0x15,0xb7,0xc1,0x93,0xb0,0x4b,0x15,0xf5,
+  0xfa,0x3b,0xe2,0xa7,0x42,0x4c,0xae,0x28,0xc3,0x5f,0x92,0xcd,0x7a,0xd9,0x08,0x35,
+  0x10,0xe3,0xc2,0xed,0x56,0xfe,0xb3,0x5d,0xd8,0x86,0x3f,0x92,0xc7,0xc5,0x26,0x56,
+  0x7f,0x57,0xe4,0x33,0x8e,0x7e,0x0b,0x0b,0x26,0xcb,0x46,0xc9,0x71,0x94,0xed,0x81,
+  0x17,0xf8,0x9f,0xa3,0xf0,0x1b,0x4c,0xb9,0xb2,0x39,0xfe,0xa9,0xd7,0x8f,0x88,0x8e,
+  0x9f,0x62,0x13,0xec,0x50,0xbb,0x2d,0xfe,0x89,0x7c,0xfe,0x1c,0xab,0x33,0xbb,0xf9,
+  0x6a,0x0d,0x0b,0x56,0xa5,0x4a,0x89,0x64,0xbe,0xbf,0xf5,0x9a,0x19,0x1d,0x7d,0x3e,
+  0x5d,0xac,0x23,0x46,0xca,0x46,0xae,0xa4,0xc1,0xb6,0x14,0x7e,0x28,0x57,0x29,0x8e,
+  0x71,0xb2,0x14,0xd8,0xf7,0x47,0xe2,0x38,0x31,0xb6,0x2d,0xf2,0x2c,0x0f,0xdd,0x24,
+  0x57,0x46,0x1d,0x6b,0x88,0x87,0xfe,0x58,0xae,0x8d,0x8a,0xa7,0xed,0xe6,0xf7,0x47,
+  0x33,0xf3,0x59,0xfe,0x93,0xd5,0xa7,0x1d,0x5a,0x7e,0x10,0xa3,0x3f,0xbf,0xcc,0x18,
+  0xd7,0x33,0x7f,0xe2,0xa1,0x2b,0x9e,0x70,0x9b,0xeb,0xe9,0xd6,0x89,0x98,0xde,0xe0,
+  0xdf,0x13,0x4c,0xfc,0x7c,0x83,0xbe,0x2e,0x87,0x23,0xae,0xd3,0xdd,0x13,0x70,0x9f,
+  0xd8,0x8c,0x98,0xd5,0xed,0x23,0xb9,0xfa,0xd1,0x56,0x46,0x3b,0x93,0x91,0x2c,0xf3,
+  0xb3,0xb2,0xde,0x24,0x79,0xd2,0xd2,0xef,0x9b,0xa0,0xab,0x2d,0xa0,0xf0,0x12,0x79,
+  0xd5,0xd3,0xc5,0x69,0xfc,0xf3,0x36,0x63,0xed,0x7d,0x42,0x3f,0xd1,0xa9,0x73,0x44,
+  0x3f,0x43,0xd0,0x9b,0x22,0x3f,0x32,0xf9,0x27,0xcb,0x7f,0xea,0x47,0x3b,0xd9,0x01,
+  0x05,0x6c,0xf4,0xf1,0x7e,0xcb,0x9e,0x49,0xe1,0x0a,0x67,0xe5,0x3c,0xb0,0xf1,0x0c,
+  0x6f,0xf2,0x4f,0x56,0x3f,0x3a,0xa3,0x0c,0xb2,0xb2,0x11,0x2e,0x96,0x60,0xac,0x02,
+  0x9e,0x98,0xdf,0x26,0xd9,0xee,0x86,0xad,0x5d,0x3e,0x2a,0x0e,0xb0,0x1c,0x35,0xd4,
+  0x51,0x47,0x96,0x8f,0x98,0xfc,0x53,0xb8,0x8f,0x3e,0x9b,0x42,0xfe,0x79,0xb7,0x4f,
+  0xcb,0x7f,0xaa,0x2b,0x65,0x62,0x8e,0xa3,0xd2,0x5a,0xd0,0x7d,0xa2,0xa0,0x9c,0xd3,
+  0xc4,0xb3,0x4c,0x14,0xc5,0xb0,0x59,0xcf,0xef,0xc0,0xdf,0xa3,0x9b,0x38,0x3b,0x1d,
+  0x86,0x90,0x6f,0xe7,0xcd,0xa3,0x46,0x62,0xd9,0x80,0x70,0x8d,0x43,0x0a,0x15,0xe4,
+  0xa7,0xc4,0x3f,0xd5,0xce,0x55,0x5a,0xb9,0x6d,0xc5,0xf6,0x42,0xc4,0x90,0x99,0x9f,
+  0xc0,0x6c,0x6a,0x79,0x56,0x9c,0xe4,0xc7,0x8d,0x81,0x2f,0xdc,0xba,0x55,0xdd,0x2c,
+  0x6b,0x47,0x93,0xce,0x6a,0xf9,0xf9,0xbe,0x47,0x42,0xe7,0x8d,0xfd,0x27,0x41,0x5f,
+  0x6a,0xb3,0x50,0xab,0xf6,0x76,0x90,0x87,0xe1,0x60,0x41,0xad,0x2a,0xae,0x77,0x4f,
+  0x50,0xd3,0x3f,0xb7,0x6a,0x12,0x74,0xa5,0x9e,0x83,0x60,0xdf,0x1f,0x85,0x2c,0x3d,
+  0x56,0xf6,0xde,0x02,0x43,0x66,0x6e,0xd0,0x92,0x0a,0xce,0x3d,0x7f,0x67,0xf2,0xcf,
+  0x14,0x37,0x80,0x3f,0x6a,0xd2,0xeb,0xef,0x97,0x70,0xc2,0x8b,0xd3,0xf3,0xfe,0xd1,
+  0x7c,0x0f,0x52,0x4a,0x3a,0x95,0x46,0xfd,0xde,0xc1,0x97,0x3b,0x4f,0x91,0x25,0xaa,
+  0x98,0x2d,0x9d,0x34,0xe6,0xb2,0x0b,0x43,0x3a,0xca,0x61,0xa6,0xd1,0x03,0xc8,0x3f,
+  0x7d,0x47,0x8a,0xd2,0x6b,0x66,0xda,0xf4,0xb5,0xd3,0x16,0x39,0xd8,0x0b,0xff,0x45,
+  0x8d,0xee,0x2d,0x08,0x68,0x67,0x19,0xb5,0xf3,0x9f,0x86,0x5d,0x3c,0x4e,0x59,0x3f,
+  0xbe,0x82,0xbc,0x15,0xb5,0xe8,0x78,0xaf,0xec,0xce,0xe5,0x3f,0xd7,0x25,0x7a,0x95,
+  0x46,0x35,0x90,0xe1,0x03,0x02,0x3b,0x40,0x53,0x9c,0xe6,0xcd,0x9c,0x40,0xba,0xec,
+  0x6c,0xfa,0x86,0x1f,0x69,0xe7,0x38,0xaf,0x7f,0xd7,0xf3,0x54,0x96,0xcf,0x26,0x4d,
+  0xfc,0xbc,0x00,0x33,0x05,0xf5,0xba,0x3d,0xaf,0x41,0xbd,0xea,0xcc,0xff,0xfe,0xe8,
+  0x02,0x0c,0x15,0xb0,0x63,0x9f,0xca,0x05,0x78,0x85,0x7e,0x4f,0x15,0xe7,0x7c,0x7f,
+  0x04,0x19,0xa2,0x7d,0x76,0x34,0xe6,0x65,0x87,0x67,0xc5,0xb9,0xdf,0x1f,0x0d,0xe9,
+  0x32,0x7a,0x8a,0x1d,0x5e,0x67,0x0b,0x9d,0x36,0xf2,0x36,0x8c,0x7f,0xce,0xe8,0x69,
+  0xcf,0x29,0xf1,0x1a,0x09,0xb1,0x09,0xe7,0xd5,0xdf,0x3d,0x9f,0x1c,0xd5,0x8f,0x7d,
+  0x7a,0xb5,0xda,0xcb,0xdc,0xfc,0xe7,0x01,0x39,0x64,0xd8,0x1a,0x79,0x9d,0x7f,0x4e,
+  0xfd,0x1d,0xdd,0x52,0x4b,0x7b,0x4e,0x09,0x48,0x28,0x8f,0x88,0x99,0x48,0xde,0xf9,
+  0x25,0x29,0xa3,0x68,0x67,0x7b,0xf1,0xdd,0x26,0x31,0x48,0xe6,0xbe,0x3f,0x8a,0xb7,
+  0x54,0xc0,0x81,0xcc,0x2e,0x26,0x95,0xdf,0xa1,0x07,0x53,0x95,0x53,0x85,0xf9,0xdf,
+  0x1f,0x15,0xab,0x57,0xd2,0xc1,0xec,0x8e,0x06,0xfe,0xa4,0x72,0x29,0x15,0xcc,0x16,
+  0xe5,0x7f,0x7f,0xc4,0xce,0xcf,0x37,0x33,0xda,0xa9,0x25,0x70,0x8e,0x14,0xe7,0x7f,
+  0x7f,0x84,0x31,0x55,0x1c,0x34,0xce,0x64,0xc8,0xa1,0xd1,0x40,0xfe,0xf7,0x47,0xe5,
+  0x82,0x7e,0xec,0xd3,0x7d,0x56,0x7c,0x25,0xe6,0x7f,0x43,0x9c,0xf3,0xfd,0x11,0x32,
+  0x6f,0x2d,0x85,0xf0,0x0e,0x92,0xe2,0x05,0x93,0x22,0xfb,0xfe,0x48,0x5f,0x9f,0x96,
+  0x5f,0x3a,0x22,0x9b,0x39,0xb2,0x3a,0x66,0xeb,0xfc,0xef,0x8f,0xae,0xd2,0x90,0x7e,
+  0x7e,0xe9,0x22,0x2c,0x63,0xf5,0xf7,0x39,0xdf,0x1f,0x55,0x5a,0xdf,0x1f,0xdd,0x94,
+  0xff,0x9c,0x80,0x6b,0xca,0xa0,0xb2,0x3a,0xd5,0x3a,0xe1,0xd1,0xbf,0xb3,0x69,0x9d,
+  0xc3,0x3f,0x61,0xb7,0xf2,0x57,0x5a,0x8e,0x53,0x62,0xe7,0xe7,0xf9,0x74,0x5e,0xfe,
+  0x73,0x2f,0xa9,0x51,0x56,0x22,0xf6,0x70,0x87,0x14,0x8c,0x55,0xa9,0x48,0x3e,0xff,
+  0xdc,0x27,0x6b,0xc7,0x3e,0x47,0x90,0x54,0xc9,0x51,0xe4,0x9f,0x89,0xbc,0xfa,0xd1,
+  0x74,0x8c,0x51,0xc4,0xd6,0x2c,0x74,0x42,0xc8,0xe3,0xcc,0xe5,0x3f,0xfb,0xb4,0xf3,
+  0xf3,0xcb,0x10,0xcf,0x18,0x2e,0x49,0xe1,0xb6,0x1d,0x29,0xfe,0x6f,0x8c,0xfc,0x27,
+  0xab,0xbf,0xdf,0xf0,0xb3,0x73,0x56,0xd8,0x77,0x43,0xd4,0x0e,0x16,0xe5,0xbe,0x3f,
+  0xca,0xc2,0x50,0x7c,0x10,0xef,0xe9,0x63,0x89,0x50,0xdf,0xfc,0xde,0x39,0xdf,0x1f,
+  0xc1,0x5e,0xa7,0x46,0x3b,0x47,0xa4,0xbd,0x20,0x47,0x1c,0x79,0xdf,0x1f,0x21,0xff,
+  0x3c,0x14,0x5f,0x38,0x37,0x87,0x9b,0xf7,0xfd,0xd1,0x15,0x45,0x3f,0x2f,0x25,0x5c,
+  0x81,0x41,0xed,0xfc,0xa7,0xf5,0xfd,0x51,0x3f,0x5c,0x11,0x1a,0xf3,0xf0,0x93,0x7d,
+  0x7f,0xa4,0x8f,0x33,0xf8,0xa7,0x66,0x6b,0xef,0x8c,0x26,0xe4,0xe7,0x7c,0x7f,0xf4,
+  0x72,0x0f,0xd3,0x9b,0xee,0x49,0x38,0x90,0xf2,0xd1,0x9b,0xea,0xef,0x87,0xa9,0xf1,
+  0x6e,0x07,0xb1,0xd1,0x93,0xcb,0x7f,0x32,0xfe,0x79,0xc0,0x3c,0x33,0x74,0x40,0xac,
+  0x9c,0x14,0x3b,0xdc,0x79,0xdf,0x1f,0xc1,0x2c,0x3b,0xbf,0xc4,0xf2,0x9f,0x97,0x92,
+  0xf5,0x33,0x81,0xce,0x39,0xe7,0xe7,0xaf,0x02,0x3b,0x4e,0xa9,0xf9,0xe7,0xcb,0x6f,
+  0xcd,0x39,0xbf,0x74,0x01,0x6e,0xd0,0x30,0xee,0xf7,0x79,0xfa,0xf7,0x86,0xb8,0xdf,
+  0xf3,0xbe,0x3f,0xa2,0xfb,0xd3,0x81,0x49,0x47,0xe3,0x2d,0x27,0xe1,0x60,0x56,0x9e,
+  0x14,0x1b,0xad,0x6f,0x85,0x90,0x7f,0xd2,0x83,0x0c,0x5b,0x1f,0x77,0x9f,0xa5,0x07,
+  0x25,0x79,0x54,0x7c,0xdc,0x8a,0xef,0x1a,0xff,0xa4,0x7a,0x0e,0x57,0x60,0x07,0x84,
+  0xe6,0x7c,0x7f,0xb4,0x87,0x1d,0x01,0xd0,0xf7,0xfb,0x47,0xb0,0x8f,0xed,0x77,0xf3,
+  0x9e,0x29,0xe4,0x9f,0x48,0x3f,0x8c,0xbd,0xd2,0xc2,0x3e,0x4a,0xb4,0xf2,0x9f,0x94,
+  0xd5,0xdf,0x49,0xbd,0x71,0xee,0x89,0xe1,0xd2,0xdc,0xef,0x8f,0x5e,0x54,0x7c,0x47,
+  0x7a,0x33,0xbe,0x29,0xe1,0xb0,0xca,0xea,0xef,0xbe,0x7c,0xfe,0x99,0x51,0x16,0x1a,
+  0xd8,0x43,0x65,0x75,0x6e,0xfd,0x5d,0xcd,0x04,0xe5,0x31,0x76,0xe6,0xb2,0x6b,0x5f,
+  0x95,0x3c,0x3a,0x19,0xb4,0xce,0xcf,0xd3,0xa2,0x0d,0xe9,0x6b,0x10,0x1a,0x75,0x1d,
+  0xec,0xfe,0x30,0x73,0xcd,0x5d,0x3f,0xee,0x3c,0x58,0x6a,0xd5,0xdf,0xe7,0x5f,0x4f,
+  0x5e,0x8d,0x37,0x8f,0x9d,0x1a,0x6c,0x9d,0x4a,0xcf,0x06,0xc3,0x27,0x5d,0x83,0x56,
+  0xfe,0x13,0xd4,0x16,0x5b,0x87,0x72,0x56,0xfa,0x9c,0x60,0x7b,0x95,0xdb,0xb8,0xe5,
+  0xe1,0xe8,0x97,0x84,0xf9,0xaa,0x3e,0x4d,0x80,0x57,0xdb,0x6c,0x1b,0x61,0x55,0xcb,
+  0xe7,0xa4,0xb2,0xa3,0x05,0x72,0xb0,0x7c,0x55,0x95,0x64,0x53,0x97,0xc4,0x8c,0x71,
+  0x11,0x0e,0xc9,0x9c,0xec,0x16,0x85,0x27,0x5b,0xe4,0xfd,0xd1,0x0d,0x44,0x14,0xa8,
+  0x71,0xde,0x14,0xf9,0x28,0x2a,0xc8,0xb5,0x70,0x0b,0xd8,0x68,0x65,0x47,0x61,0xd4,
+  0xee,0x96,0x6d,0xd4,0xba,0x67,0x94,0x7b,0x1c,0x1e,0xa6,0x9f,0x93,0x6d,0xa3,0x9b,
+  0xfe,0xb8,0xe1,0xbe,0xa5,0xee,0xf5,0x1e,0x6a,0xde,0xf3,0xd5,0x18,0xc4,0x39,0x2f,
+  0xac,0x80,0x12,0x0a,0xf1,0x07,0x45,0x21,0xc2,0x01,0x5d,0x62,0x8e,0x53,0x40,0xe6,
+  0x44,0x88,0x80,0x44,0x85,0x2a,0x4e,0xa4,0xac,0x61,0xf5,0x7d,0xb1,0x4c,0xe9,0x8a,
+  0xc9,0x0f,0x89,0x65,0x3c,0x17,0xc9,0x2a,0x93,0x92,0xb7,0x0c,0x4a,0x8c,0x7b,0x52,
+  0x27,0xf7,0x39,0x68,0x51,0xa5,0x0e,0xc1,0xc9,0xdd,0x29,0xb7,0xac,0x95,0xbe,0x21,
+  0x40,0xa5,0x31,0x8e,0x2a,0x02,0x9b,0x31,0xb3,0xae,0x70,0x2b,0x67,0x8f,0x22,0x41,
+  0xe5,0x8c,0xfa,0x11,0xbc,0x1a,0x27,0x5e,0x2e,0x81,0xbf,0x83,0xce,0xee,0x05,0x22,
+  0x41,0xd2,0xcb,0x99,0xf3,0x3c,0x12,0xe3,0xd6,0xc3,0x7d,0xb0,0x46,0x29,0xa7,0xb6,
+  0xf5,0xdc,0x7d,0xa8,0x7e,0x1f,0xa2,0xe6,0x3d,0x5f,0x85,0x42,0xb6,0xf6,0x65,0x50,
+  0x44,0x39,0x56,0x2e,0x5d,0x83,0x46,0xb0,0xe6,0x19,0x29,0x08,0x76,0x39,0x65,0x5e,
+  0x04,0x74,0x67,0x34,0x1e,0xd2,0x11,0xcb,0x9e,0x49,0x31,0x16,0x62,0xa2,0x8f,0x65,
+  0x07,0x65,0x41,0x64,0x7f,0x23,0x41,0xb5,0xec,0xe9,0xe0,0x42,0xea,0x2a,0x2d,0x32,
+  0x72,0x41,0x1a,0x45,0xa3,0xb7,0xa9,0xb2,0x79,0xcf,0xd6,0x05,0x71,0x35,0x1a,0xbc,
+  0xc5,0x29,0x74,0xdb,0x3a,0xb4,0x3e,0x5b,0xce,0x9e,0x11,0x78,0xbc,0x4b,0x94,0x57,
+  0xf8,0x25,0xb4,0x27,0xa0,0xf1,0xc4,0x3c,0x9b,0xad,0x11,0x16,0x76,0x15,0xa6,0x23,
+  0xed,0xd2,0xf3,0x42,0x35,0x2d,0x0c,0x46,0xa2,0x79,0x7d,0xf8,0x16,0xb8,0x08,0xc4,
+  0xa8,0x47,0x36,0x1b,0x60,0xde,0x93,0x16,0x70,0x2d,0x34,0x16,0xf7,0x78,0x6d,0x05,
+  0xdc,0x7d,0x94,0xc4,0x25,0xaf,0x79,0x02,0x19,0xfb,0xdc,0x36,0x01,0x09,0x80,0x14,
+  0x15,0x9e,0x31,0x1a,0xa6,0x44,0xc0,0x7b,0xae,0xe0,0x1f,0xa4,0x6f,0xc4,0xff,0xd8,
+  0x3b,0x9f,0x35,0x70,0x3a,0x5e,0x50,0xac,0x79,0xae,0x28,0xdc,0xd8,0x75,0x36,0xfe,
+  0x25,0x6f,0xd9,0x51,0x5b,0x47,0xd7,0xc3,0xf2,0x7f,0xf5,0x96,0x59,0x73,0xb9,0x37,
+  0xc2,0x6d,0xa4,0x67,0xe3,0x77,0x79,0x8b,0x8e,0x72,0x1d,0xf4,0x6c,0xe5,0x5d,0xe2,
+  0x7c,0xb5,0xc4,0xec,0x5b,0x51,0xb0,0x84,0x3a,0xe3,0xf3,0xbc,0xca,0xd1,0x82,0x3f,
+  0xa6,0x45,0xf1,0x2a,0xaf,0x48,0xcd,0xf7,0x0e,0x84,0x7b,0x84,0xf9,0xa7,0x1f,0xb6,
+  0xa2,0xa3,0x3a,0xe5,0x5b,0xd0,0x3f,0x8d,0x7d,0x04,0x50,0xc0,0x55,0x25,0xa3,0xd3,
+  0xee,0x06,0x61,0x3b,0x57,0x49,0xd7,0xc6,0xdd,0x5e,0xec,0x33,0xef,0xa9,0x94,0x75,
+  0xc0,0x2a,0x28,0x05,0x41,0xb5,0x75,0xc8,0x51,0xc2,0x1a,0xe6,0x3d,0xef,0x8d,0x40,
+  0x1c,0xed,0x89,0x66,0x4c,0x40,0x3c,0x2d,0xfa,0x89,0x5d,0xa2,0xd6,0x5c,0x22,0x82,
+  0xdc,0xe5,0x95,0x57,0x88,0x25,0x09,0x01,0x37,0x06,0xf6,0x95,0xe4,0xf5,0x55,0x2a,
+  0x47,0x1e,0x0a,0xde,0xeb,0x2c,0x8b,0x70,0x4a,0x97,0x22,0xbb,0x9d,0x36,0x25,0x6f,
+  0x9e,0x31,0xfa,0x90,0x5c,0x26,0xda,0x22,0xd8,0x50,0xe4,0x12,0x71,0x93,0x39,0x4b,
+  0x96,0xb1,0x53,0x30,0x6e,0x15,0x40,0x8b,0x28,0x20,0x3e,0x08,0xc0,0x71,0x56,0xd7,
+  0xbd,0x11,0x22,0x77,0x51,0x39,0x2e,0x7a,0xdd,0x09,0x61,0x80,0x5b,0x08,0xa2,0xd7,
+  0xf2,0xf9,0x7b,0x95,0x79,0x71,0x65,0x2d,0xfc,0xb6,0x50,0xd6,0x75,0x6f,0xbc,0x04,
+  0x35,0x29,0x94,0x59,0x73,0x79,0x55,0xe1,0x82,0xa0,0x67,0x6a,0x5b,0x64,0xf9,0x4c,
+  0xd1,0x2d,0x50,0x6e,0xad,0x1d,0x0d,0x83,0xaf,0x8b,0xa2,0xeb,0xf5,0x2c,0x94,0xfd,
+  0x62,0x41,0x81,0x00,0xb9,0x3e,0x89,0x89,0x4c,0x20,0x0a,0xc2,0xde,0x02,0xa9,0x30,
+  0x4e,0x62,0x79,0x7d,0x02,0xb7,0x04,0xa2,0x8a,0x5b,0x12,0xfa,0xb9,0x45,0x70,0xbf,
+  0x52,0x5a,0xee,0x51,0xad,0xbe,0x2a,0x5b,0xbb,0xfa,0x3b,0xc1,0x5b,0xb6,0xd9,0x76,
+  0xdb,0xda,0xe9,0xfd,0x71,0xf7,0xce,0x92,0x39,0xf7,0xe4,0x0a,0x21,0xa2,0x48,0x29,
+  0xb8,0x53,0xd1,0x6e,0x9e,0xeb,0x13,0x85,0x78,0x89,0x57,0x58,0xc1,0x95,0xf4,0xb4,
+  0x05,0x25,0xb1,0x80,0x70,0x4f,0xe7,0xcd,0xb3,0x25,0x56,0xe2,0x11,0x7e,0x8b,0x2b,
+  0x53,0x5a,0xa4,0x12,0x45,0x78,0x90,0xb3,0xe5,0xd9,0xac,0x32,0x22,0x3e,0x94,0x28,
+  0x93,0x37,0x45,0x2b,0x23,0x7e,0x05,0x1b,0xc9,0xdc,0x30,0x3b,0x47,0xa8,0x92,0x96,
+  0xfc,0x60,0x5f,0x80,0x8d,0xdd,0x8a,0x3f,0xd7,0x05,0x4e,0xfe,0x41,0xee,0x39,0x15,
+  0xfd,0xb9,0x8d,0xff,0x22,0xcb,0x6b,0x06,0xbd,0x79,0xf7,0x9c,0x87,0x98,0x05,0x5f,
+  0x92,0xcb,0x46,0x6d,0x8f,0x97,0x3c,0x9c,0xf8,0x92,0xaf,0x2c,0xb7,0x3e,0x94,0xcf,
+  0xaa,0x14,0x44,0x74,0xa9,0x32,0x1b,0xb9,0x7b,0x36,0xcf,0xae,0x9e,0xfd,0xfb,0xd9,
+  0xcb,0xb3,0x37,0xac,0x06,0xfc,0xab,0xae,0x65,0x6f,0x3b,0x96,0x0d,0xbf,0x9e,0xd9,
+  0xb7,0x21,0xf0,0xae,0x3e,0x6e,0x2a,0xd7,0xf7,0xf9,0xa6,0x55,0xa7,0x4a,0xeb,0x47,
+  0xc6,0x3e,0xaa,0x6f,0xd6,0xfb,0x3e,0xca,0x7b,0x9e,0x37,0x7a,0xd4,0xbd,0x24,0xb9,
+  0x6d,0xdd,0x3d,0x66,0x23,0xd7,0x67,0x23,0x1b,0x95,0x9d,0xb1,0x79,0x9e,0xc2,0x57,
+  0x59,0xa3,0xe3,0x2e,0x4f,0x61,0x6e,0x0d,0xc2,0xbc,0x8d,0xdc,0xc3,0xb8,0xff,0x6c,
+  0x23,0x1c,0x36,0xf0,0x45,0x96,0xe4,0xfa,0x0a,0x70,0xfb,0x44,0x81,0xe1,0x3c,0xee,
+  0x95,0xe8,0x9c,0xbd,0x82,0x20,0xb5,0x0e,0xf7,0xf1,0x0a,0x89,0xd3,0x37,0x74,0x01,
+  0xe4,0xb0,0x00,0xdf,0xdf,0xe3,0xe8,0x5a,0xbf,0x29,0x73,0xa3,0x08,0x42,0xe5,0xb4,
+  0xd4,0x9f,0x77,0x4f,0x80,0x75,0x1c,0xfb,0x75,0xdc,0x2b,0x6c,0xdc,0x0a,0xe0,0x72,
+  0xf7,0xf4,0x08,0x0b,0xba,0x34,0x9f,0x78,0x4e,0x58,0xc8,0x15,0x2a,0x91,0x3f,0x92,
+  0x72,0x7d,0x55,0x10,0xed,0x72,0x83,0xd0,0x57,0xe2,0x13,0xee,0xe7,0xdc,0xf2,0xbd,
+  0x03,0x25,0xd6,0xd3,0x54,0x27,0xee,0x59,0x94,0x03,0x0d,0xe0,0x04,0x9e,0x22,0x1f,
+  0x0d,0x72,0x46,0x48,0xc5,0x9f,0xde,0x02,0x65,0xc0,0x65,0x85,0x98,0x72,0x8b,0x64,
+  0x63,0xb1,0x29,0xc6,0x19,0x61,0x1a,0xc7,0x29,0x88,0xed,0x2c,0x13,0xc5,0xe6,0x03,
+  0x3a,0x4e,0xe6,0xfa,0x84,0x38,0xc6,0x9c,0xdf,0x63,0x31,0x47,0x0f,0x3e,0x25,0x66,
+  0x1c,0x93,0x38,0xc5,0x13,0xb7,0x79,0x69,0x01,0x14,0xb2,0x31,0x7d,0xf8,0x4b,0x85,
+  0x09,0xe3,0x71,0x0a,0x62,0x81,0xd4,0xb5,0x4d,0x6e,0x15,0x25,0xa4,0xa4,0x1a,0xe0,
+  0x4b,0x26,0x86,0x28,0x78,0xfb,0x10,0x9b,0x22,0xc3,0xf9,0x20,0x63,0x59,0x8c,0x3b,
+  0x1b,0xe3,0x14,0x07,0x84,0x54,0x67,0xb0,0x95,0x65,0xe0,0x83,0xd4,0x99,0x69,0x15,
+  0x8d,0xbf,0xd2,0xc3,0xee,0xd9,0x0a,0x1d,0x48,0x4c,0x7e,0x5b,0xfb,0x0b,0x28,0x5d,
+  0xde,0x20,0x02,0x0d,0xb5,0xee,0x89,0xb8,0x84,0x58,0x87,0x8f,0xd1,0xb0,0x47,0x26,
+  0xa2,0xb5,0x8f,0x62,0x08,0xdf,0xec,0x47,0x2b,0xb4,0x3e,0x04,0xa8,0x88,0x68,0xed,
+  0x3f,0xe5,0x5e,0x3d,0xfe,0x71,0xa0,0x61,0x8b,0x07,0x9b,0x0f,0x46,0x8c,0x7b,0x46,
+  0x19,0xea,0x50,0x29,0x2e,0x78,0x39,0xbd,0x21,0x79,0x2d,0xbf,0x8e,0x2a,0xc4,0x06,
+  0x08,0x63,0x92,0x28,0x60,0x83,0x6a,0x0d,0xb0,0xe6,0xa9,0xe3,0xfc,0x9d,0xde,0x22,
+  0xd6,0x18,0x89,0x7f,0xd5,0x5b,0x94,0xc3,0xba,0x15,0xb0,0xb1,0xab,0x3c,0xfe,0xfb,
+  0xde,0x92,0xa3,0xc2,0xc6,0xae,0x55,0xf1,0xdf,0xf4,0x5a,0x3e,0xa1,0x70,0x2b,0x60,
+  0x09,0xdd,0x19,0xff,0x9c,0xf7,0xd6,0xa3,0x05,0x1b,0xbb,0x76,0xc6,0x3f,0xef,0xb5,
+  0xfc,0x33,0xa6,0xe1,0xbc,0x88,0xbf,0x1e,0x3d,0x0a,0x4b,0xba,0x1e,0xc6,0xc8,0x5c,
+  0x36,0x6c,0xae,0x9d,0x73,0x73,0xd5,0xf4,0x3e,0xb9,0x94,0x05,0x6f,0xd6,0x70,0x47,
+  0x05,0x13,0xe7,0x15,0x5c,0x43,0x25,0x8e,0x5b,0xe1,0x85,0x27,0xa1,0xb2,0xcb,0xcb,
+  0x22,0x3a,0x35,0xbe,0x2f,0x86,0x7b,0xe3,0x42,0x27,0x14,0xc3,0x6f,0x52,0x29,0x2b,
+  0x34,0x70,0xc5,0xe8,0x33,0xb9,0x77,0xc4,0xad,0x81,0xf5,0x5d,0x85,0x72,0x81,0x7e,
+  0xcf,0x42,0x39,0x12,0x45,0x3e,0x67,0xcc,0xd3,0x46,0x4c,0x33,0x26,0x84,0x47,0x74,
+  0xc0,0xb7,0xfa,0x30,0x3e,0x28,0x47,0x3c,0x32,0x42,0x40,0xab,0x10,0x53,0x3d,0x08,
+  0xf8,0x25,0x4a,0xde,0x3b,0xc2,0x30,0x1a,0xb4,0x89,0xf8,0x42,0xd6,0x60,0x60,0xb5,
+  0x39,0xd1,0x3f,0x8d,0x3e,0x41,0xc3,0x79,0xaa,0x19,0x51,0xd1,0x5f,0x86,0x69,0x6b,
+  0xbc,0x27,0x01,0xc4,0x79,0x59,0xf4,0x92,0x02,0x99,0x22,0xe0,0xfb,0x45,0xb0,0xe6,
+  0x09,0x05,0x8c,0x2f,0xfd,0x1e,0xba,0xa5,0x60,0x11,0x27,0xd3,0x9e,0xa0,0xe1,0xf5,
+  0x3c,0xc5,0x3b,0x4e,0xaa,0xe1,0x5b,0xf0,0x88,0x52,0x98,0x7b,0xef,0xf1,0x02,0x91,
+  0xb3,0xc3,0x0a,0x8a,0x32,0xdf,0x8f,0x6b,0xf7,0xe5,0xd6,0x1e,0x13,0x38,0xa8,0x8c,
+  0x89,0x31,0x52,0xc6,0xfe,0x94,0x4d,0xcc,0xf9,0x10,0xf1,0xa0,0x7f,0x9a,0xf6,0x6c,
+  0x03,0x1b,0x14,0x76,0xb4,0xc6,0x3c,0x6f,0xc0,0x02,0x28,0x8a,0x93,0xdf,0x86,0x61,
+  0x6b,0xed,0xad,0x42,0x5c,0x91,0xa4,0xb6,0xf2,0x92,0x6e,0x14,0xa6,0x5e,0x69,0x45,
+  0x45,0xce,0x3f,0x39,0x9d,0xbb,0x61,0x5c,0x49,0x0a,0xda,0x9f,0x45,0x92,0xc1,0x7a,
+  0x47,0x9c,0xd8,0x86,0x38,0x4f,0x11,0xe7,0xe9,0x7a,0x1d,0xf0,0x9f,0xce,0xd9,0x53,
+  0x51,0x62,0x1b,0x3d,0x60,0xb3,0x71,0x2d,0x23,0xb1,0x07,0x3d,0x82,0x4d,0xca,0xd9,
+  0x53,0x10,0xd3,0x11,0xd1,0xb3,0x55,0xa8,0xec,0x42,0x9c,0x07,0xcf,0x93,0x36,0x19,
+  0xed,0x69,0xbc,0x5b,0xce,0x6e,0x23,0xda,0xda,0x04,0x0d,0xf0,0xf7,0x80,0xdf,0xc2,
+  0x25,0xe5,0xde,0x07,0xf8,0x2f,0x2a,0xc9,0xd3,0x77,0x2e,0x5d,0xfb,0xc0,0xbc,0x52,
+  0xe5,0xb9,0xb3,0xeb,0x96,0x16,0x5a,0xf7,0xe4,0xa2,0xf2,0xe3,0x95,0x3b,0xe1,0xf7,
+  0x71,0x2e,0x6d,0x8f,0x94,0x3c,0x2c,0xcc,0x83,0x3c,0x9c,0xd7,0xe1,0x1d,0x21,0xb5,
+  0xca,0x1b,0x1d,0x61,0xd8,0xfa,0xef,0x80,0xf3,0xb5,0x9f,0x32,0xae,0xfe,0x53,0xfa,
+  0x18,0xbc,0x97,0x1e,0xd4,0xe7,0xf2,0xda,0x33,0x4b,0x92,0x4f,0x5d,0xc9,0xf5,0x91,
+  0x24,0xec,0x62,0x07,0x0f,0x25,0xab,0x91,0xeb,0xc3,0x0d,0xcb,0x19,0x1b,0xd6,0x68,
+  0xe4,0x4d,0x26,0x89,0xbc,0x58,0x64,0x68,0x68,0x35,0x72,0xd7,0x5c,0xd7,0x54,0x20,
+  0xbf,0x0f,0xc1,0x73,0x4c,0x7b,0xb9,0xdd,0x41,0xa3,0x91,0x9b,0x8b,0xd6,0x0b,0x62,
+  0xae,0x61,0xcd,0x84,0xf1,0x0c,0x59,0x3b,0x3e,0x69,0xfd,0x0a,0xb1,0xfa,0xd8,0x7f,
+  0x8d,0x69,0x3f,0xe6,0x43,0x7a,0x7f,0xae,0xcf,0x9e,0x24,0xbb,0x60,0x40,0xa9,0x91,
+  0xf4,0x06,0xd4,0x48,0xb9,0x27,0xde,0xb4,0xbe,0xca,0xdc,0xfa,0xc4,0x9b,0xd7,0x57,
+  0x49,0xac,0x71,0xa2,0xc4,0xfe,0x3e,0xda,0x18,0x2e,0xab,0x5c,0xc5,0x86,0xb6,0x3e,
+  0x22,0x58,0xe3,0x36,0x07,0xf1,0xd7,0xbf,0x8e,0xe3,0xcc,0x46,0xee,0x79,0x84,0x11,
+  0x24,0x59,0x11,0x73,0x8d,0x39,0xf6,0x94,0xd9,0xf3,0xf2,0x1a,0xe6,0x25,0x51,0x9e,
+  0x85,0x91,0x7a,0xfc,0x87,0x37,0x75,0x91,0xf9,0x9d,0xcd,0xa7,0x5c,0x4d,0x4d,0xbf,
+  0xfc,0x33,0x97,0xeb,0x5f,0x1c,0xf6,0x7f,0x71,0x35,0xcf,0xce,0xce,0xaa,0x73,0x1a,
+  0xff,0x6f,0xf6,0x7d,0x9a,0xcf,0x03,0x73,0x05,0xc8,0xf9,0x3c,0xfc,0x3b,0xf9,0x7c,
+  0xbe,0x57,0xe7,0x79,0xe0,0xa7,0xfa,0xbc,0x68,0xfa,0xbc,0xd5,0x98,0xeb,0xf3,0x73,
+  0x47,0xfe,0x1a,0x9f,0x1f,0x1b,0xf8,0x7a,0x4d,0xf9,0x70,0x6e,0xdc,0xaf,0xdd,0xd3,
+  0xbf,0xe4,0xf3,0xca,0x1c,0x9f,0xb7,0x96,0xa5,0x39,0xff,0xd7,0xa1,0x7c,0x58,0xf8,
+  0x97,0xc7,0x7d,0xda,0x9e,0xfe,0x34,0xbb,0x40,0x1e,0x8b,0xcb,0x59,0x58,0xfe,0xe5,
+  0x9f,0xdd,0x74,0x7d,0xe6,0xf3,0xbf,0xae,0xef,0xd7,0x5f,0xec,0x6f,0x39,0x12,0xed,
+  0xdf,0x2d,0xaf,0xfd,0x6b,0xc7,0x7c,0x76,0x7d,0x76,0x7d,0x76,0x7d,0x76,0x7d,0x76,
+  0x7d,0x76,0xfd,0xff,0x72,0x69,0x71,0x92,0x68,0x71,0x52,0xfd,0x8f,0x9e,0xcb,0x67,
+  0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x7f,0xc4,0x15,0x64,0x65,
+  0x00,0xd8,0xfb,0xb2,0xf1,0xf7,0xff,0xf9,0x20,0x28,0xf3,0x3e,0xfd,0xf7,0xb5,0xdf,
+  0xb3,0x05,0x21,0xcd,0xe5,0xc6,0xf7,0xa7,0x6e,0x9e,0xeb,0xff,0x01,0x51,0x16,0x5f,
+  0xd0,0xd5,0x60,0x00,0x00,
diff --git a/u-boot/board/esd/cpci405/fpgadata_cpci405ab.c b/u-boot/board/esd/cpci405/fpgadata_cpci405ab.c
new file mode 100644
index 0000000..3f78473
--- /dev/null
+++ b/u-boot/board/esd/cpci405/fpgadata_cpci405ab.c
@@ -0,0 +1,1285 @@
+  0x1f,0x8b,0x08,0x08,0x73,0xed,0xb5,0x40,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30,
+  0x35,0x5f,0x32,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,0x74,0x1c,
+  0xd5,0x95,0x36,0xba,0xeb,0x54,0xb5,0x54,0xea,0x6e,0xa9,0x4b,0x2d,0x89,0x08,0xfc,
+  0xa0,0xd4,0x92,0x8d,0xec,0xb4,0xe4,0x76,0xdb,0x18,0x23,0x84,0x54,0x6e,0x09,0xa7,
+  0x01,0x83,0x15,0x1e,0x09,0x33,0xc3,0xcd,0xb4,0xc1,0x99,0xf1,0xcc,0x72,0x66,0x84,
+  0x93,0x95,0x31,0x24,0x93,0x39,0x7a,0xd8,0x16,0x96,0xc1,0x6d,0xe3,0x99,0x98,0xc0,
+  0xe5,0x6f,0x3f,0x48,0x0c,0x71,0xf2,0xb7,0x65,0xc0,0xe2,0x31,0x50,0x12,0xc2,0xb4,
+  0x1f,0xd8,0x0a,0xf0,0xcf,0x98,0xc7,0x98,0x36,0x51,0x88,0x00,0x01,0xf2,0xe3,0x27,
+  0x32,0x96,0xad,0xbb,0xcf,0x39,0x55,0xd5,0x2d,0xc9,0x64,0x32,0x6b,0xcd,0xba,0x8f,
+  0x75,0xe9,0xac,0x95,0xec,0x94,0x8e,0xab,0xcf,0xa9,0x53,0x67,0x7f,0xfb,0xdb,0xfb,
+  0x3b,0xa7,0x21,0xcf,0x37,0x2c,0xfe,0x03,0x20,0x2d,0x83,0xc2,0xbb,0x9b,0xef,0xfe,
+  0x9b,0xf9,0xa1,0x2b,0xff,0x32,0xfc,0x97,0xa1,0x2b,0xab,0xff,0xee,0xee,0xe5,0x70,
+  0x17,0xb8,0xc3,0xdf,0x9f,0x17,0xfa,0xc1,0x3d,0x73,0xe7,0xcf,0x87,0xbb,0xc1,0x13,
+  0x0e,0x85,0xe6,0xcf,0x09,0x5d,0x39,0x27,0x7c,0x15,0x2c,0x87,0xbc,0xb9,0x57,0xd6,
+  0xcc,0x9b,0x5b,0x13,0x5a,0x08,0xdf,0x05,0xd8,0xd9,0x3c,0x86,0x9f,0x27,0x1f,0xbe,
+  0xfd,0xaf,0x42,0x40,0x25,0x00,0xc8,0x0d,0x49,0x31,0xf6,0xbf,0x6a,0x48,0xd2,0x25,
+  0xa0,0xf5,0x55,0x21,0x30,0xd9,0xff,0x07,0xeb,0xef,0x79,0x21,0xd0,0xb3,0xff,0xbf,
+  0x14,0x02,0x03,0x9a,0xa0,0xe2,0x6e,0xf0,0x87,0xe0,0xcb,0x3e,0x12,0x28,0x94,0x1b,
+  0x7f,0x4a,0x1b,0xf2,0xa5,0x4d,0xd8,0xe7,0x4f,0x6f,0xe3,0xff,0x63,0x4d,0x94,0xff,
+  0xae,0x36,0xfc,0xbf,0xc7,0xfc,0x50,0x8c,0xa6,0xc4,0x9e,0x44,0x31,0xb8,0xc6,0x1b,
+  0xf5,0x7d,0xfc,0x3e,0xa6,0xeb,0x82,0x31,0x46,0xeb,0x0e,0xfb,0x4e,0xc9,0xaf,0x47,
+  0x8e,0x42,0x67,0xff,0xd2,0xb3,0x72,0xd0,0x3c,0x0a,0xf3,0x52,0xdf,0x1b,0x69,0x18,
+  0x86,0x66,0xde,0x71,0x6d,0xc8,0xfb,0x7c,0x7b,0xd5,0x6b,0x9e,0x93,0x24,0x4d,0x37,
+  0xf6,0x95,0xf7,0x79,0x36,0x93,0x6b,0x8d,0x8d,0xfd,0x5f,0xff,0xdf,0x4b,0xba,0x49,
+  0x5a,0xe1,0x0f,0xaf,0xc3,0x75,0xb8,0x63,0x2f,0x04,0x53,0x9e,0x50,0xdc,0xec,0x68,
+  0x33,0x2a,0x53,0xd8,0x66,0x09,0x6d,0x83,0x4a,0x53,0x0d,0x45,0xde,0x97,0xf8,0x7d,
+  0xcc,0xc2,0xdd,0xca,0xf3,0x50,0x6d,0x7a,0x92,0xe4,0x03,0xe8,0x24,0x01,0xd3,0x13,
+  0x9f,0xbd,0x12,0x3c,0x78,0x45,0x4d,0x92,0x61,0x25,0xc6,0x3b,0x5d,0x38,0x04,0xe7,
+  0x48,0x9d,0xe9,0x4b,0xca,0xbf,0x85,0x43,0x50,0x63,0xfa,0x34,0x79,0x25,0x74,0xa2,
+  0x31,0x35,0x19,0xe8,0x57,0xf8,0x7d,0xd2,0xd2,0x0b,0x30,0x46,0xea,0xcd,0x8d,0xc3,
+  0x0d,0xc3,0xa5,0xcc,0xf0,0xf5,0xcb,0xbb,0xe1,0x0f,0x70,0xb5,0x79,0xf9,0xb0,0x3c,
+  0x02,0xfc,0x3e,0x86,0xb6,0x1b,0xce,0x49,0x75,0x66,0x30,0x29,0x97,0xc1,0x3b,0x6a,
+  0xd8,0xf4,0x26,0xe5,0xc3,0xea,0x21,0x8d,0xdf,0xb9,0x5f,0xd1,0x59,0x9b,0x94,0x2b,
+  0x08,0xcf,0xc3,0x1c,0xb3,0x74,0x38,0x37,0x56,0xfc,0xea,0xe1,0x72,0x53,0x8d,0x93,
+  0x51,0xf5,0x28,0x9d,0xc2,0x7a,0x78,0x0a,0x5f,0x20,0xf6,0x5d,0xae,0x25,0x80,0xe3,
+  0xc2,0x51,0x04,0x74,0xf2,0x50,0xaf,0x6e,0x96,0x86,0xc8,0x61,0xd8,0x01,0xde,0x1e,
+  0x4f,0x88,0x8c,0xe0,0xf3,0xc4,0x8f,0x2e,0x4d,0x5f,0xb4,0x8f,0x56,0xa5,0xd5,0xd5,
+  0x64,0x15,0xb4,0x6d,0x59,0x96,0x56,0xff,0x2c,0x70,0x1c,0xf0,0xca,0xa0,0xe7,0x3e,
+  0x72,0x4c,0xdc,0x27,0xaa,0x16,0xd0,0xd3,0x50,0x3b,0xa8,0x3e,0x1b,0x20,0xbd,0x6f,
+  0x48,0xe1,0xc1,0xe0,0x14,0xf9,0x48,0xde,0x6f,0x1f,0xaf,0x3d,0xe1,0xab,0x91,0x5f,
+  0x17,0x2f,0x8e,0x31,0xed,0x05,0x63,0x0c,0xea,0xdf,0xf4,0xe1,0xb8,0x60,0x4c,0xad,
+  0xff,0x37,0xdf,0x26,0x79,0x14,0x0e,0x69,0xd7,0xf4,0x5e,0x8e,0x7d,0xf6,0xf3,0x71,
+  0xed,0x72,0x7d,0x8a,0x8f,0xa5,0xee,0x4d,0xfa,0x54,0x5b,0x1a,0xce,0x41,0x78,0xb8,
+  0x63,0x2b,0xf9,0xac,0xfd,0xe3,0x9e,0xf0,0x01,0x1c,0xd7,0x47,0x62,0xbe,0xa2,0x85,
+  0x8f,0xc2,0x3a,0xa5,0x2a,0xa5,0xfe,0x80,0xf4,0xc3,0xbe,0x70,0x59,0x4a,0x6d,0x22,
+  0xb5,0x46,0x5b,0xa8,0xec,0xa0,0xa7,0x99,0xbc,0x2e,0x9e,0xb3,0x09,0x8f,0xc1,0x4f,
+  0x69,0x30,0xad,0xde,0x17,0x78,0x5d,0xdf,0x4b,0x13,0x69,0xf7,0xea,0xc8,0xf4,0xd4,
+  0x2f,0x92,0x65,0x83,0x9e,0xd5,0x64,0x18,0xf8,0xf3,0x89,0x16,0x1f,0x86,0x87,0x70,
+  0xec,0xd1,0x10,0x39,0xd0,0xbe,0x17,0x74,0xd3,0xad,0x91,0x25,0xd0,0x06,0x31,0xd3,
+  0x13,0xf2,0xbf,0x2e,0xe6,0x7d,0xb0,0x70,0x17,0xbc,0x0d,0x75,0x74,0x49,0x42,0x3e,
+  0x0b,0xa7,0x20,0x4c,0x1f,0x4c,0xb4,0x55,0xc2,0x47,0x68,0x5c,0x9e,0x90,0xbf,0x10,
+  0xdf,0x15,0x85,0x34,0x0c,0x42,0x2d,0xf8,0xa8,0x9c,0x56,0x47,0x8c,0x3a,0x90,0xa8,
+  0x9c,0x80,0x11,0xa8,0x83,0xa5,0x54,0x7e,0x1d,0xf8,0x7d,0x54,0x6d,0x00,0xce,0xc2,
+  0x4f,0x0c,0x6f,0xbc,0xa8,0x02,0xde,0xd2,0xc2,0xc6,0xd1,0xb8,0x3c,0xa0,0x9d,0x85,
+  0x3a,0xc3,0x13,0x97,0x7b,0xc5,0x77,0x51,0x74,0x13,0xcf,0x42,0xb5,0x91,0x1f,0x2f,
+  0x5a,0xae,0xdc,0xbf,0x3d,0xc0,0xfe,0xb4,0x13,0x9e,0xa5,0xd5,0x68,0x90,0x18,0x68,
+  0xac,0x4d,0xa9,0xab,0x42,0x62,0x6d,0x54,0x8d,0x78,0xf3,0x1e,0x26,0xac,0x0d,0x19,
+  0x80,0x67,0x75,0xd6,0x26,0xb2,0x5f,0xcc,0x85,0x5a,0xdc,0x0e,0x7b,0x94,0x60,0x34,
+  0xcf,0x4f,0x1a,0x41,0xaa,0xd0,0xa3,0x1e,0x8d,0xf4,0xd1,0x3d,0x7a,0x90,0x19,0x11,
+  0xee,0x46,0xa0,0x3b,0x7f,0x91,0x31,0x02,0xd5,0xc5,0xde,0x35,0x72,0x99,0x71,0x07,
+  0x74,0x95,0xf8,0x5c,0x77,0x9f,0x30,0x46,0x48,0x1d,0x6c,0xa4,0xf2,0xa7,0x32,0x9f,
+  0xf7,0xad,0x25,0xd8,0x67,0xa5,0xee,0x3a,0xdf,0xa6,0x79,0xa3,0x70,0x56,0xab,0x6b,
+  0xc4,0xf7,0x70,0xa7,0xc1,0x8d,0xb8,0xfc,0x41,0x4e,0xb3,0xe8,0xcf,0x00,0xbc,0x45,
+  0xea,0x22,0xbe,0xf8,0x26,0x05,0x7e,0xa5,0x2e,0x88,0x6c,0xc0,0x71,0x55,0x9e,0xd7,
+  0xeb,0xae,0x67,0x6d,0xc4,0x7c,0x2d,0xd4,0xd2,0xd0,0x4d,0xaa,0xc1,0x43,0xdd,0xba,
+  0xd6,0xdd,0x58,0x59,0xaa,0xb6,0x12,0xbc,0x62,0x54,0x6b,0x1e,0x4a,0x8e,0x88,0xb1,
+  0xab,0xae,0x3e,0x7d,0x13,0x04,0x23,0x1e,0x7f,0xab,0x92,0xd8,0x06,0x15,0x11,0x55,
+  0xdb,0xde,0xa7,0xef,0xd5,0x82,0x8d,0xd8,0xe7,0x5e,0xb1,0xbe,0x4a,0x4b,0xf0,0x69,
+  0x28,0xfc,0x69,0xec,0xa4,0xec,0x21,0xac,0xd8,0x44,0x06,0x14,0x66,0xb0,0xb1,0x8b,
+  0xb9,0x48,0x14,0xef,0x84,0xb7,0xa0,0x6e,0x91,0x2f,0x2e,0xcd,0x80,0x0f,0x61,0x81,
+  0xa1,0x6c,0x15,0xcf,0x19,0xaf,0xc8,0x83,0x62,0x5d,0x54,0xc2,0x4e,0xfe,0xe4,0x71,
+  0xe9,0x2d,0xc7,0x01,0x3e,0x67,0xf8,0xb0,0x0d,0xf0,0x2b,0x71,0xf9,0xa0,0x78,0x37,
+  0x2a,0xb5,0x04,0xa4,0x70,0x06,0x7d,0xb4,0xa1,0x4c,0x19,0x41,0xb7,0xec,0xc5,0xc9,
+  0x85,0x11,0xb5,0x0e,0xd0,0x38,0x68,0xdd,0x47,0xa9,0x24,0x6e,0xa8,0xa6,0x9e,0x04,
+  0xa9,0x84,0xb5,0xad,0x01,0xaa,0x26,0xc8,0x60,0xf1,0x8b,0x46,0x41,0x4b,0x47,0x82,
+  0x1c,0x14,0x9e,0xaa,0xd2,0xb5,0x44,0x91,0xf1,0x1d,0xf3,0x84,0xb4,0x0d,0xb0,0x07,
+  0xf4,0x1e,0x37,0x5b,0x5f,0x49,0xf0,0x9a,0xb3,0x42,0xd8,0xc6,0x5e,0x5f,0x34,0x17,
+  0xaa,0x52,0x9e,0x7b,0xc8,0x8b,0xb4,0xdd,0xd8,0xd6,0xe7,0x6e,0xce,0x79,0x97,0x3e,
+  0x03,0xf9,0xe9,0xbc,0x66,0x92,0x12,0x73,0x5a,0xa9,0xd6,0xd3,0x57,0xe9,0xb5,0x43,
+  0xbe,0x6b,0xe4,0xc7,0xf4,0xcf,0xe9,0xdc,0xc1,0x99,0x3f,0x92,0x8f,0xc3,0xe7,0x74,
+  0x6a,0xfa,0xa6,0xd5,0xe5,0x07,0xc5,0xfa,0x52,0xf3,0x77,0xeb,0xe7,0xa0,0xee,0x5d,
+  0xdf,0x53,0xf2,0xca,0xd4,0x30,0xd4,0xbd,0x95,0xbf,0x57,0x1e,0x82,0x2f,0xa0,0xce,
+  0x2c,0x48,0xca,0xbd,0x39,0xc2,0x6f,0xb8,0x2e,0x68,0x63,0xb4,0x3e,0xed,0x7d,0x56,
+  0xfe,0xd4,0x38,0x13,0x0f,0x9f,0xd9,0x38,0xf2,0x8d,0xba,0xd8,0x1f,0xe8,0xbc,0x13,
+  0xbe,0x11,0xb9,0x5f,0xcc,0xd7,0x2e,0x69,0x03,0xec,0x43,0xbf,0x51,0xb9,0x90,0x1c,
+  0xa1,0x4f,0xcd,0xad,0x1c,0xf4,0x74,0xb7,0x4e,0x35,0xf6,0x26,0x57,0x98,0x9e,0xab,
+  0x8b,0x9e,0xb4,0xfc,0x18,0x3c,0x8a,0x6d,0xaa,0x4c,0xec,0xe1,0xbb,0xf0,0x14,0x2c,
+  0xeb,0xf3,0x34,0x47,0xee,0x54,0xf7,0x41,0x99,0xe9,0xb9,0x27,0xd2,0x27,0x9e,0x61,
+  0x0c,0xd7,0xd7,0x5e,0x29,0x68,0xe6,0x85,0x70,0x59,0x25,0xa5,0x4a,0xb3,0x33,0x14,
+  0x59,0x89,0x57,0x2a,0xf1,0x69,0x90,0x9f,0x89,0x79,0xdf,0x55,0xf2,0x02,0x2e,0xf3,
+  0x7a,0x33,0x7f,0x58,0x1e,0x33,0x86,0x61,0x5e,0x8f,0x6f,0xf8,0xeb,0x3f,0xc6,0x3e,
+  0x87,0xd1,0x47,0xc9,0x1f,0xb5,0xc7,0xc4,0xba,0x18,0x52,0x70,0x5c,0xe6,0x83,0xc9,
+  0xf2,0x21,0x03,0xd7,0x17,0x73,0x71,0xbb,0xe1,0x0b,0x99,0x1b,0x3b,0xc5,0xfa,0x92,
+  0xb4,0x51,0x40,0xdf,0x62,0xfa,0x86,0xd1,0xa5,0x8c,0x2a,0x57,0x09,0xe3,0x88,0xb8,
+  0x12,0x5b,0xce,0xdb,0xb4,0x28,0x2b,0xe1,0x11,0xf4,0xc6,0x9d,0x49,0x9c,0x82,0x63,
+  0xe6,0x76,0xe6,0x06,0x87,0x60,0x3d,0xe5,0x1e,0x3b,0x6d,0xf0,0xf5,0x45,0xa5,0x95,
+  0x20,0x7c,0xb8,0x7f,0x08,0xba,0x3b,0x7e,0x6e,0xb5,0xe9,0xa8,0xee,0x59,0x8f,0x6d,
+  0xc4,0x7c,0xa9,0xc5,0xf9,0xdc,0x6f,0x4c,0x09,0xfb,0x87,0x22,0x71,0xd0,0x8f,0x79,
+  0x42,0xad,0x87,0xa1,0xd5,0xc0,0x91,0x2e,0x20,0xbd,0x02,0x9b,0x40,0xfa,0x31,0x1f,
+  0x97,0xef,0xe4,0x43,0xa3,0x74,0x04,0xb0,0x3f,0x67,0xe4,0x21,0xe5,0xe0,0xca,0xba,
+  0x37,0x1f,0x7c,0xa6,0x2d,0x46,0xf8,0x77,0x25,0x4a,0x46,0xe1,0x3d,0xa8,0xef,0xf5,
+  0x9c,0x92,0x47,0xcd,0x51,0xa8,0xff,0x8d,0xaf,0xab,0x6d,0x74,0xfb,0x17,0x50,0x8f,
+  0xbe,0xae,0x68,0x50,0x60,0x01,0xc3,0xaf,0xcf,0x8c,0x79,0x87,0x0b,0x4e,0xb6,0xfd,
+  0x6b,0xeb,0xd1,0xbf,0x99,0xf7,0x56,0xfe,0x9e,0xa2,0x5a,0xe3,0x63,0x6d,0xde,0xd1,
+  0x60,0x97,0xdc,0x2c,0x59,0xf8,0x75,0xb8,0x7d,0x9d,0x51,0xfe,0xa6,0xf7,0x8c,0x31,
+  0xd5,0xd8,0x68,0xec,0xe8,0xf7,0xfc,0x90,0xfc,0x2b,0x7d,0xa9,0xf9,0xeb,0xfd,0xea,
+  0x19,0xaa,0xdb,0xf8,0x35,0x04,0x3b,0x42,0xe8,0xe2,0x42,0xb0,0x81,0xb6,0xe9,0xfa,
+  0x31,0xec,0xaa,0xd7,0xdc,0xab,0xe8,0xa9,0xe8,0x3c,0x08,0x88,0x67,0x68,0x96,0x6c,
+  0x40,0x24,0xd2,0xcd,0xbc,0x24,0x09,0xaa,0x9d,0x4a,0x80,0x4d,0xd3,0x6e,0x78,0xde,
+  0x35,0x9b,0xe1,0x57,0xb3,0x98,0x77,0xa3,0x64,0x08,0x3e,0x26,0x61,0x7c,0xa3,0xf0,
+  0x4f,0x87,0x70,0x9a,0xf2,0x93,0x0d,0xc1,0xfc,0x8f,0x25,0x3f,0x02,0x90,0x47,0xcb,
+  0xe0,0xd7,0x1f,0xe0,0x25,0xb3,0x60,0xb8,0x61,0x54,0xfd,0x83,0x3d,0x29,0x63,0xae,
+  0x7a,0x36,0x5f,0xdd,0x0e,0x7e,0xd1,0x43,0x6a,0xf8,0x70,0x7e,0x52,0xde,0x00,0x1f,
+  0x2b,0x0b,0xf0,0x9f,0x17,0x05,0xb5,0x73,0x7a,0xb8,0x77,0x43,0x72,0x47,0xdc,0xc6,
+  0xaf,0x39,0xda,0x46,0xd8,0x31,0xdc,0x31,0xea,0xae,0xa5,0x1b,0xf5,0xf2,0x94,0xeb,
+  0x14,0xa9,0xa5,0x2f,0x99,0xe5,0x3d,0xea,0x30,0x09,0xdb,0xf8,0xb5,0x14,0xda,0x34,
+  0xbd,0x3f,0xef,0x39,0xe2,0x6b,0xdf,0x71,0xa2,0x62,0x84,0x84,0x89,0xb7,0xe5,0x97,
+  0xe6,0xec,0x3e,0x75,0x0f,0xe9,0x76,0xd6,0x17,0xac,0x4b,0x94,0x9d,0xc8,0xbb,0x26,
+  0x67,0x7a,0xd3,0x3a,0x3a,0x6b,0x90,0xdc,0x47,0xa6,0xc3,0xde,0x44,0xde,0x40,0xe5,
+  0x7d,0x44,0xd5,0x2c,0xfc,0xf2,0x26,0xda,0x70,0x38,0x55,0x0b,0x77,0x14,0x74,0x60,
+  0x7f,0xd2,0xb3,0x6b,0x3c,0x5e,0x38,0x7d,0xff,0xcf,0x5e,0xf1,0xd6,0xc8,0x9b,0x6d,
+  0xfc,0xda,0x4d,0xc6,0x56,0xd4,0xf7,0x15,0x74,0xc9,0xdf,0xd3,0xff,0x49,0x5d,0x80,
+  0x63,0xc7,0x71,0x9d,0x83,0x05,0x6f,0x32,0xcc,0x25,0x16,0x7e,0x0d,0xc1,0xa1,0x45,
+  0x5d,0x47,0xbd,0x7b,0xa5,0x5f,0xc1,0xc7,0xee,0x05,0x47,0xf2,0x9f,0xe9,0xac,0x32,
+  0x0e,0x11,0x7f,0xbf,0xb7,0xcb,0x33,0xdb,0xc1,0x2f,0xd5,0x07,0x7a,0x4a,0x5d,0xd5,
+  0x3a,0x95,0xae,0xab,0x28,0x33,0x1f,0x58,0x45,0xa6,0xea,0x1b,0x57,0x94,0xf5,0xab,
+  0x73,0xc9,0x66,0x07,0xbf,0x4a,0xaf,0x48,0x94,0x0d,0x22,0xe6,0x3e,0x86,0x50,0xbb,
+  0x6c,0x50,0xbd,0xd7,0xf8,0x0e,0xac,0xa3,0x55,0x27,0x3a,0x7e,0x44,0xac,0x70,0x2e,
+  0x5a,0x3c,0x04,0xbf,0xc4,0xf9,0x2a,0x4d,0x92,0x0d,0xf8,0x42,0x26,0xd8,0x42,0x5b,
+  0x49,0xda,0x60,0xb7,0x59,0x99,0xc4,0xfb,0x08,0xfc,0x2a,0xd9,0x45,0x18,0x5a,0xad,
+  0x4c,0xc8,0xbb,0xd8,0xb2,0xa2,0xde,0x84,0xbc,0x42,0x3a,0xa8,0xd4,0xa1,0x51,0x54,
+  0x63,0xe3,0xd7,0x09,0xa5,0x14,0xea,0x34,0x5f,0xbb,0xb4,0x4c,0x1b,0x84,0x1a,0x74,
+  0xd4,0x0c,0xbf,0x0c,0xc2,0x10,0xcd,0xc1,0xaf,0x0f,0xe2,0x07,0x12,0x0b,0x1a,0xf3,
+  0x7f,0x76,0x45,0x8e,0xf1,0x56,0x3c,0xdc,0xf8,0x77,0xf1,0x45,0x3f,0xa7,0x07,0x34,
+  0xfd,0xbb,0x4b,0xb6,0x36,0xb4,0x5a,0xf8,0xa5,0xfc,0x35,0xdc,0x4f,0x03,0x4d,0xea,
+  0xa3,0x39,0x33,0xe0,0x7e,0x23,0xd0,0x54,0x1a,0x27,0x57,0xc0,0xfd,0xe6,0x82,0x66,
+  0xf5,0x51,0xb7,0xee,0xe0,0x17,0xdc,0x0f,0x15,0x46,0x5e,0x3c,0x52,0xa1,0x6e,0xca,
+  0x4b,0x7c,0x53,0xf5,0xf7,0xee,0xd4,0x5b,0x60,0x76,0x43,0xe5,0xbf,0x90,0xb5,0x16,
+  0x7e,0x29,0x8a,0x82,0xaf,0xe8,0xf5,0xaa,0xdf,0xaf,0xb4,0xb4,0x04,0xf4,0xa8,0xdb,
+  0xff,0x57,0x4a,0xbc,0x45,0xf7,0x46,0x55,0x7f,0x84,0xd8,0xf8,0x75,0x7d,0x24,0xd5,
+  0xf4,0xcc,0x96,0xfc,0x19,0xee,0x3c,0xa3,0xbf,0x29,0x54,0xec,0x76,0xc9,0x2d,0x91,
+  0x83,0xb7,0x96,0x32,0x44,0xfb,0xb5,0xcc,0xbf,0x6b,0xeb,0x34,0xf4,0xfc,0xc5,0x75,
+  0x8d,0x4b,0x37,0xc1,0x80,0x71,0xb6,0xb0,0xae,0xf1,0xa6,0x4d,0xf2,0x72,0xe3,0xde,
+  0xe2,0x05,0x8d,0xb9,0x9b,0xe4,0x0f,0x72,0x63,0x16,0x7e,0x91,0x03,0x95,0xe1,0x1b,
+  0xbc,0xf1,0xb6,0x81,0xfd,0x6f,0xdd,0xd5,0xd5,0x98,0xbf,0x45,0xae,0xa8,0x3c,0xb0,
+  0x28,0xdc,0x84,0x57,0x72,0x6c,0xfc,0x32,0xa1,0x23,0xa6,0x97,0xaa,0x4a,0xa4,0x07,
+  0x3a,0xf4,0x40,0x71,0x55,0x3b,0xd9,0x46,0xa8,0x9e,0x00,0x75,0xbf,0xbb,0xc0,0x7a,
+  0x3e,0xae,0x37,0x13,0x6b,0xd4,0xb2,0x88,0x7a,0x4b,0xeb,0x9b,0xe6,0x3f,0x2f,0x2b,
+  0x8b,0x96,0x7e,0x8b,0x4c,0x4d,0xac,0x31,0xca,0x9a,0xf2,0x9a,0xb6,0x13,0x97,0x85,
+  0x5f,0x4f,0xc1,0x03,0x52,0xb9,0xa1,0xf6,0x93,0x33,0xf0,0x00,0x94,0x2d,0xba,0xb4,
+  0x3f,0x8c,0x57,0xe0,0x6e,0xe3,0x89,0x26,0x92,0x63,0xe1,0x17,0x62,0xee,0x01,0x08,
+  0x1b,0xc1,0x78,0x39,0x02,0xab,0x14,0x36,0x36,0xb0,0x80,0x81,0x5d,0xb9,0x29,0x1e,
+  0xa8,0x14,0xeb,0xab,0x52,0xda,0x89,0x68,0xf5,0x02,0xa2,0x55,0xd1,0x00,0x61,0xb0,
+  0xb5,0x54,0x2b,0xef,0xd3,0x4e,0xa2,0xf1,0x60,0xdc,0x73,0x50,0xac,0xaf,0x4a,0x2d,
+  0x59,0xd8,0x07,0xd7,0xc0,0x06,0xb3,0x21,0xa4,0x1e,0x26,0xdf,0x47,0xc0,0xf9,0x7a,
+  0x08,0x0e,0xc3,0x5c,0x28,0x30,0x65,0xb7,0x85,0x5f,0xae,0x59,0xb7,0xac,0xd7,0x03,
+  0x5b,0x2a,0x13,0xee,0xca,0x9c,0xf5,0x52,0x80,0x6e,0x78,0x3c,0x52,0x89,0xd1,0xce,
+  0xf6,0x7f,0x56,0xb7,0xcb,0x6e,0x0b,0x77,0x5c,0x3f,0x86,0x75,0xed,0xb3,0x4c,0xb5,
+  0x39,0xa7,0x16,0x36,0xc2,0x32,0x74,0xf8,0xee,0xa9,0xda,0x4f,0xe9,0x0c,0xd3,0xdd,
+  0x8c,0xe0,0xc7,0xd7,0x57,0x42,0x9a,0x0a,0xeb,0xd0,0xf3,0xab,0xab,0x2f,0xb1,0x0c,
+  0xde,0xc6,0x98,0x81,0x06,0x59,0x21,0xee,0xb3,0x4b,0x9d,0x8e,0x91,0xc5,0xd5,0x18,
+  0x43,0x16,0x4d,0x87,0x97,0x5b,0xf4,0xf4,0x4d,0x23,0xb7,0x16,0xc0,0xbf,0xd3,0x2b,
+  0xd3,0x05,0x23,0xb8,0x2e,0x04,0x7e,0x4d,0x13,0x51,0xd3,0x46,0x5a,0xc4,0x02,0x86,
+  0x17,0xa5,0x39,0xb4,0x1c,0x31,0x17,0x5f,0x48,0x5f,0x3b,0xbe,0x63,0x02,0x77,0x5c,
+  0x5f,0x18,0xaf,0xd1,0x05,0x09,0x44,0xab,0xba,0xbe,0xcf,0x5a,0xaf,0x3a,0x91,0x3f,
+  0xe8,0x9f,0xa9,0xbe,0xb6,0xa9,0x3e,0xf1,0xc0,0x7f,0x78,0xc0,0xc2,0xaf,0xc2,0x17,
+  0xb5,0x75,0x1a,0x46,0x7a,0x35,0x45,0x7f,0x0f,0x1b,0x0d,0x3d,0xad,0xde,0x9b,0x33,
+  0xdd,0xfc,0x03,0x9d,0x33,0xa8,0xfe,0x88,0x38,0xf8,0xb5,0x95,0xae,0x81,0x19,0x1d,
+  0x0d,0xb8,0xf4,0x52,0xbf,0x80,0xb2,0x14,0x9b,0x57,0xba,0x46,0xaf,0xea,0xc8,0xbb,
+  0x05,0x57,0x3b,0x7f,0x3e,0x7a,0x71,0x9a,0x50,0x7c,0x54,0x1e,0xc8,0x31,0xa0,0x03,
+  0xb6,0xc3,0x9f,0x51,0xbf,0xae,0x24,0x94,0x20,0xec,0x02,0xd2,0x61,0xe3,0xd7,0x4e,
+  0x38,0x88,0x61,0x06,0x46,0x4d,0x3a,0x0c,0x2a,0x61,0xf0,0xc6,0x3d,0x95,0xb0,0x1e,
+  0x23,0xbd,0xfc,0x44,0xf9,0x6c,0xc5,0xb0,0xf0,0x0b,0x63,0xfe,0x17,0x4d,0xdf,0x7c,
+  0x84,0xe3,0x73,0x18,0xea,0x23,0x1c,0xa3,0xe1,0x62,0xf8,0x85,0x23,0xb5,0xf0,0xeb,
+  0x0c,0x39,0x02,0xf3,0x0c,0x5f,0x87,0xbc,0xaa,0xfd,0xb0,0x14,0xae,0x5c,0xd9,0x4f,
+  0x16,0x32,0xfc,0x32,0xbc,0x31,0x99,0x36,0x5a,0xf8,0x15,0xc3,0xf7,0x30,0x00,0x97,
+  0x3e,0x48,0xca,0xa1,0x63,0x51,0xc0,0xef,0x66,0xfd,0x39,0x76,0x7d,0x35,0xac,0x6f,
+  0x6f,0xd5,0x2d,0xfc,0x72,0xe9,0x06,0x85,0xed,0x8a,0xa7,0x85,0x18,0xa4,0x83,0x06,
+  0x24,0xb5,0x85,0x24,0xb0,0xbf,0x41,0x45,0xa5,0x68,0x58,0xeb,0xcb,0x8b,0xcc,0x45,
+  0x4f,0x79,0xc2,0x7e,0x34,0x14,0xfd,0x35,0x77,0x98,0x3c,0xa8,0x3e,0xa4,0x06,0x4d,
+  0xf7,0xfc,0x56,0x6b,0x7d,0x41,0x7e,0x0c,0x7d,0x50,0x18,0x6e,0xa4,0x2f,0xc7,0x62,
+  0x29,0x34,0xbc,0xed,0x32,0xa5,0x29,0xa3,0x4e,0xf5,0xe6,0xc8,0x54,0xc4,0x87,0x89,
+  0x69,0x69,0x03,0x61,0xcb,0x95,0x4f,0x31,0x56,0x1f,0x85,0x67,0xbc,0xbe,0xb5,0x9d,
+  0xcd,0xc6,0xb1,0xca,0x6a,0x65,0x69,0xab,0x3c,0x28,0xe2,0x43,0x53,0xba,0x00,0xef,
+  0xd1,0x6b,0x2b,0xaa,0xee,0x97,0x5a,0xe1,0xf7,0x14,0xfd,0xfc,0x48,0xf9,0x05,0x18,
+  0xa3,0xf3,0xd2,0xbe,0x93,0xf2,0xb0,0x85,0x5f,0xa5,0x9f,0xc2,0xf3,0xb4,0x5a,0x55,
+  0xa9,0x3b,0x00,0x9d,0xb4,0x7c,0x58,0xed,0xda,0x3e,0x94,0x78,0xbe,0x22,0xd0,0xeb,
+  0xf9,0x9c,0x0c,0xe7,0x58,0xf8,0xb5,0x01,0x79,0x4a,0x35,0xa8,0xad,0x39,0x54,0xdb,
+  0xa1,0x54,0xf4,0xe7,0x85,0x02,0x87,0xe9,0x5e,0x15,0x47,0x31,0x8f,0x9c,0x92,0x84,
+  0xcf,0x44,0xdf,0x8b,0xd8,0x1d,0x50,0x29,0x22,0x5a,0x67,0x2c,0x80,0x6e,0x30,0x87,
+  0x5d,0x09,0x30,0x10,0xb7,0x62,0x7e,0xa3,0x64,0x25,0xbc,0x03,0xc1,0x90,0x17,0xe4,
+  0xed,0x65,0x1f,0x9b,0x0b,0xcc,0x07,0x18,0xbe,0x23,0xd1,0xe8,0x59,0x9a,0x6c,0xe8,
+  0x6f,0x74,0xf0,0xeb,0x9f,0xa0,0x5e,0xf2,0x1d,0xc0,0x1e,0x8e,0xd1,0x6b,0x4d,0x0f,
+  0xc7,0x2f,0xa8,0xef,0xf1,0x25,0xcb,0xb3,0xf9,0x17,0x46,0x95,0x0f,0x52,0x79,0x99,
+  0x76,0xd0,0x60,0xf7,0x41,0x1e,0xc7,0xa2,0x14,0xc4,0x02,0x2d,0x9b,0x7f,0x61,0x9f,
+  0x13,0x01,0x13,0x51,0xf9,0x2a,0x16,0xd2,0xec,0x16,0xd1,0xc5,0x30,0x59,0x20,0xe6,
+  0xc2,0x54,0x38,0xff,0x02,0x37,0x90,0x08,0xb4,0x35,0xed,0x14,0xc1,0xd2,0xf3,0xb0,
+  0x92,0x81,0x6f,0x48,0xf8,0x4c,0x5d,0xfb,0x0e,0x42,0xc0,0x1c,0x5d,0xbd,0x9e,0x9c,
+  0x4a,0xcc,0xa1,0x8f,0x0f,0x7a,0xee,0x0d,0x20,0x28,0x24,0xaa,0xd2,0xf2,0x7d,0xa4,
+  0x5a,0xd1,0x04,0x7e,0x2d,0x81,0xd3,0x78,0x9f,0x02,0x8f,0x1c,0xf1,0xbe,0x0c,0xf3,
+  0x07,0xa5,0x1a,0x79,0x89,0x7a,0x9a,0xd6,0x9a,0xbe,0x85,0xb2,0x5f,0xc4,0x1b,0x46,
+  0xc9,0x0b,0xae,0x31,0xb6,0xbe,0x4c,0xc6,0xbf,0xa0,0xbe,0x1f,0x71,0x79,0x88,0x19,
+  0x7d,0x1b,0x4f,0xb6,0xf5,0x8b,0x75,0xa1,0xba,0xf8,0x2b,0x0a,0xc1,0x38,0xae,0xa6,
+  0xd3,0x10,0x3e,0xe6,0xeb,0x6e,0x08,0x12,0x64,0x64,0x66,0xf0,0xc5,0x4e,0x62,0xf1,
+  0xa6,0x4b,0x59,0xec,0x37,0x07,0x54,0x13,0xef,0xfb,0xef,0xf0,0x44,0x0a,0x87,0x83,
+  0x8c,0x0c,0xa3,0x41,0xf5,0x14,0x09,0xe7,0x88,0xb5,0x83,0xfc,0x6b,0x5f,0x4b,0xd5,
+  0xb6,0x8e,0xe8,0x4c,0x3f,0x3c,0x4d,0xcb,0x06,0x90,0x76,0x21,0x0a,0xb7,0x54,0x9d,
+  0x50,0x57,0xe7,0xa8,0xe2,0x3e,0x2b,0x94,0xc3,0x6c,0xec,0x9a,0xaa,0xac,0x2d,0x30,
+  0x1e,0x52,0x59,0x58,0x98,0xb3,0x1b,0xf9,0x17,0xf2,0xe5,0x10,0xa9,0x11,0x6d,0x10,
+  0xbf,0x10,0xb6,0xea,0xe9,0xd4,0x58,0xee,0xd5,0xf0,0x79,0x6f,0x98,0xfa,0x58,0xb0,
+  0x7d,0x10,0x18,0x7e,0xc9,0x35,0xc2,0x1f,0x32,0xfe,0x85,0x7e,0xc3,0x7b,0x79,0x4b,
+  0x6e,0x5a,0x19,0x29,0x14,0x44,0x8c,0x7b,0x12,0x8e,0x5f,0x62,0x5c,0x9a,0x88,0xf0,
+  0xbd,0xf1,0xf2,0x99,0xa1,0x03,0xda,0x73,0x68,0xc8,0xcc,0xd3,0xd6,0xa1,0x83,0x45,
+  0xfe,0xa5,0x0b,0xfc,0x5a,0xae,0x72,0x6e,0x15,0x27,0x8a,0xf1,0x04,0x0d,0x18,0x1d,
+  0x8c,0x5b,0xdd,0x2f,0xae,0xa4,0xc5,0x5c,0x2c,0x44,0xfc,0x7a,0x16,0x82,0x06,0x46,
+  0x44,0x15,0xfa,0xfd,0x79,0xb3,0xd9,0x9f,0xec,0x36,0x81,0x23,0x96,0xcf,0x2c,0x56,
+  0x30,0xd4,0x0f,0xe2,0x3f,0x77,0x57,0xc0,0x36,0xd0,0xa3,0x95,0xc8,0xbf,0xa0,0x05,
+  0xaf,0xe8,0x7e,0x72,0xd0,0x65,0xe1,0x57,0x0c,0x46,0xa4,0xba,0xe2,0xe0,0x1a,0xf4,
+  0x1b,0x29,0x1c,0xad,0x77,0x4d,0x51,0x0f,0x22,0x5a,0x6d,0xb1,0xb2,0x46,0xbe,0x90,
+  0xc5,0xbf,0xd0,0x03,0x78,0xfa,0xf1,0xf5,0xfb,0x47,0xe0,0xb4,0xcb,0xe2,0x29,0x9b,
+  0xe4,0xf7,0xc1,0xe1,0x5f,0x67,0xa1,0xd6,0xc8,0x2d,0x96,0xe7,0xc3,0x7f,0x40,0x17,
+  0xa3,0x30,0x33,0xe0,0xac,0x51,0x63,0xf8,0x36,0xb7,0xe6,0x88,0xf5,0xb5,0xb0,0x34,
+  0xad,0x76,0xf3,0xf7,0x10,0x51,0xb8,0x03,0x02,0xc5,0x9e,0x56,0xa2,0xd3,0x6e,0xa9,
+  0xda,0xe3,0x59,0xeb,0x2e,0x20,0x62,0x4e,0x5d,0xc8,0x19,0xa1,0xfa,0x06,0xb7,0xdf,
+  0x5f,0x21,0x3f,0x44,0x2b,0x8c,0x47,0xb4,0xd6,0xc6,0x8e,0x3d,0x65,0x95,0xc6,0x8d,
+  0x5a,0xab,0xdf,0xc5,0xdb,0x94,0x2a,0x3b,0xd9,0xf3,0x69,0x52,0xfd,0xa4,0xc2,0xb8,
+  0x9f,0xce,0x34,0x3c,0xda,0x0d,0x82,0xb1,0x7a,0xb4,0xc8,0x4c,0x31,0x5f,0x09,0xce,
+  0x19,0x6b,0x9b,0x0b,0xb6,0xc8,0x0a,0x12,0xb1,0x05,0xac,0x3f,0x48,0xb2,0xa0,0x86,
+  0x19,0x16,0x7e,0x45,0x39,0x7e,0xd5,0x35,0xb3,0xe1,0x84,0xac,0x3f,0xed,0xe4,0xec,
+  0x18,0x0d,0x67,0xbe,0x12,0xec,0xf9,0x40,0x3e,0x2d,0x8a,0xa9,0x23,0xe8,0x7f,0xac,
+  0x39,0xe5,0x06,0xb1,0xf1,0xab,0x12,0x9e,0x43,0xfe,0x15,0x4d,0x90,0x1a,0x7d,0xad,
+  0x32,0xbb,0x05,0x89,0xd8,0x20,0x5e,0x09,0x30,0x46,0xb6,0xde,0xc6,0x2f,0x91,0xdf,
+  0x28,0x0d,0xf9,0x6f,0xd0,0xb6,0xeb,0x8c,0x88,0x11,0xf6,0xd6,0xe9,0x68,0xdc,0xb5,
+  0x5e,0xcc,0x29,0x2d,0x9c,0xaa,0xe1,0xfb,0x9c,0xaa,0x3c,0xe5,0xd7,0x10,0xe3,0xaa,
+  0xcc,0x29,0xab,0xc8,0xbb,0xf1,0xab,0xe8,0x32,0xd3,0xb3,0x0a,0x7d,0xa6,0xf0,0x3f,
+  0x88,0x5f,0x7f,0xa0,0xd7,0x0e,0x7a,0x7f,0x24,0xdf,0x82,0x7e,0xec,0xda,0xb4,0x07,
+  0xf9,0x97,0xf1,0x4f,0xe9,0xb9,0x83,0x4b,0x6b,0xda,0x02,0x3a,0xbf,0x8f,0x5a,0xb2,
+  0x9b,0xf1,0x94,0x63,0xe8,0xde,0x4d,0xf2,0x5b,0xf4,0xf3,0x4b,0x9f,0x29,0x1a,0x32,
+  0xce,0xc1,0x63,0xff,0xb6,0x74,0x8f,0x1c,0xb1,0x70,0x47,0xf9,0x35,0x8c,0x6d,0xba,
+  0xfc,0x54,0xde,0x73,0xeb,0x7b,0xe1,0xb3,0xd6,0x9a,0xb4,0xaf,0xbb,0xed,0x02,0x9c,
+  0x8b,0xd7,0xa4,0x37,0x3e,0x2b,0x9b,0xe2,0x19,0xee,0x2a,0x7d,0xcc,0xdc,0xa7,0x55,
+  0xa5,0x11,0xad,0xfc,0xb8,0xbe,0xb6,0x0d,0xde,0xb8,0x90,0x1c,0x47,0xfe,0x55,0x35,
+  0xe8,0x5b,0x48,0x3e,0x12,0xeb,0x8b,0xf3,0x2f,0x69,0x8e,0x99,0x37,0x1c,0x88,0xc3,
+  0xff,0x34,0x66,0xf5,0x21,0x11,0x7b,0xd4,0xd8,0xa7,0x23,0x8b,0x6c,0xce,0x31,0x75,
+  0xb1,0x06,0x95,0x0d,0x22,0xb7,0x73,0xb5,0x1b,0xf4,0x87,0xf8,0x90,0xd9,0xd8,0x09,
+  0x7b,0x08,0x81,0x94,0xf5,0x5d,0x25,0xcc,0x8f,0xd5,0x7f,0x90,0x3f,0x4c,0xb6,0xb5,
+  0x3e,0xd9,0x57,0x83,0x37,0x94,0x5f,0x40,0x9f,0x70,0x0d,0xcb,0x35,0x7d,0x24,0xe6,
+  0x8b,0xe3,0x17,0x7a,0x80,0x8d,0x49,0x79,0x1b,0x9c,0xa3,0x75,0xe6,0xe5,0x48,0xc4,
+  0x78,0xf6,0x09,0x47,0x9a,0x16,0xf3,0x55,0x86,0xfc,0xeb,0x33,0x0c,0xf5,0xbd,0xc3,
+  0x6d,0xcd,0xf8,0x1e,0xce,0x33,0x5f,0x1b,0x5e,0xf5,0x63,0x75,0x4c,0x99,0xc3,0x98,
+  0x5d,0xaa,0x91,0x7f,0xd7,0x36,0x60,0xdc,0x2a,0x68,0x56,0x86,0xe4,0x48,0xeb,0x1b,
+  0x2d,0x01,0xc1,0xad,0x1e,0x81,0x99,0x8c,0x6d,0x0d,0x5a,0x73,0x21,0x71,0x9f,0xc9,
+  0x18,0xc7,0x5f,0xb9,0x1f,0xa1,0x01,0xd3,0x9d,0xcc,0x59,0xa9,0x3e,0x0f,0x7f,0xc7,
+  0x58,0x5b,0xda,0xc1,0xaf,0x16,0xc4,0x02,0x33,0xba,0x27,0x10,0x33,0xf9,0xb8,0xc2,
+  0x39,0x87,0xd5,0x87,0xa2,0x4a,0xca,0xb3,0x00,0x7a,0xc5,0xfa,0x82,0xfc,0x95,0x89,
+  0x8f,0xa1,0x3e,0xe5,0xfd,0x5c,0x8e,0xd1,0x77,0x20,0x9c,0xca,0x3f,0x25,0x23,0x23,
+  0x8b,0x5d,0x9e,0xca,0x3f,0xd3,0x60,0xda,0xf8,0xc5,0xbc,0x7a,0x6d,0xbf,0xef,0x87,
+  0x53,0x86,0x4d,0xe4,0x29,0x47,0x96,0x7e,0xde,0x36,0x14,0x65,0xfe,0x10,0xc9,0xda,
+  0x60,0xbb,0x85,0x5f,0xe9,0xd4,0x50,0xac,0xde,0x9b,0xbf,0x56,0xd6,0xe9,0xe1,0x50,
+  0x5d,0xbe,0xb7,0x45,0x0e,0x19,0x29,0x3d,0x5c,0x8a,0x0e,0x24,0x64,0xe7,0x0f,0x4f,
+  0x98,0x1d,0xa1,0xea,0x62,0x75,0x0d,0x29,0x83,0x8e,0x6f,0x56,0x17,0xbb,0xd7,0x92,
+  0xb2,0x78,0xc7,0xea,0x40,0x9f,0xba,0x80,0x38,0xfc,0xeb,0x30,0xdd,0xa1,0x07,0x53,
+  0x53,0xc2,0x24,0x5f,0x6f,0xd3,0x83,0x07,0x2e,0x9b,0xef,0x7f,0xa0,0xa3,0xad,0x4c,
+  0x4f,0x75,0x94,0xb5,0xde,0x65,0xe5,0x0f,0x4b,0x12,0xd0,0xa1,0xfc,0x9d,0x74,0x03,
+  0xf8,0xd1,0x40,0x67,0x5e,0x49,0x73,0x12,0x1a,0x2e,0x58,0x7c,0x1a,0x11,0x8b,0x7f,
+  0x41,0xc9,0x09,0x18,0x64,0x3e,0x7c,0x43,0x5b,0xb9,0x91,0x22,0x75,0xe4,0xe6,0x96,
+  0xa2,0x04,0xa4,0xb4,0x2e,0x0c,0x3c,0xe4,0x26,0x85,0x8f,0x2b,0x2d,0x75,0xa8,0x8c,
+  0x0b,0x57,0x6d,0xf0,0x34,0x91,0x0b,0x50,0x3f,0xc3,0x77,0xc7,0x5f,0x2c,0x21,0x67,
+  0x5b,0x6b,0xcd,0x39,0xcd,0x1e,0x87,0x7f,0x21,0x3d,0x61,0x68,0xf5,0x54,0x79,0x15,
+  0x02,0x22,0x23,0x74,0x72,0x10,0x5e,0x46,0x03,0xfd,0xaa,0x83,0x5f,0x95,0xc8,0x07,
+  0x11,0xad,0x68,0x20,0xa1,0x3c,0x07,0x35,0x92,0x1c,0x47,0x62,0x78,0xbf,0xc2,0xf9,
+  0xa0,0xc3,0xbf,0x0c,0x48,0xa0,0x6f,0xf1,0xb0,0xd7,0x24,0x09,0x15,0x08,0x64,0x61,
+  0x93,0x50,0xe4,0x5c,0xaa,0x86,0x01,0x8c,0xe0,0x5f,0x85,0x97,0x40,0x3b,0xad,0xaa,
+  0xe8,0x64,0x5c,0x66,0x4f,0xeb,0xac,0xf4,0x8d,0xb3,0xc9,0x2d,0x8d,0x6b,0xdb,0x67,
+  0x0d,0xa9,0xf7,0x91,0x52,0x27,0x7f,0x08,0xbf,0x25,0xb5,0x43,0xbe,0x1a,0x79,0x23,
+  0x7d,0xa3,0x71,0xfe,0x60,0x4e,0x8d,0x7c,0xb3,0xf9,0x72,0x8b,0x36,0x14,0xac,0x44,
+  0xfc,0xe2,0x43,0x37,0x30,0x7e,0xc6,0x78,0x03,0x7c,0x7b,0xc8,0x10,0x3d,0xaf,0xd5,
+  0xf5,0xf9,0xd2,0x9e,0x24,0x5c,0x60,0xf3,0x75,0x56,0xee,0x17,0xf9,0x8d,0x5d,0x25,
+  0x69,0x48,0x21,0x7e,0x79,0x69,0x03,0xf3,0x75,0x61,0x58,0x82,0x81,0x99,0x92,0x52,
+  0xc2,0x12,0x3e,0x1f,0x9b,0x7f,0x5d,0x3a,0x15,0x59,0x92,0xde,0x53,0x39,0x2c,0xdf,
+  0x09,0xbf,0x40,0x6e,0xae,0x86,0xe4,0x25,0xf0,0x06,0xcc,0x37,0xf3,0x43,0xb2,0x5f,
+  0x3c,0x1f,0x91,0x3f,0x9c,0xc5,0x72,0x9e,0x37,0x4b,0x0f,0xb5,0x73,0x03,0xf1,0x8b,
+  0xce,0x48,0xe7,0xad,0x40,0x5c,0x16,0x3e,0x53,0x79,0x17,0x7e,0x0a,0xcb,0x06,0x30,
+  0xca,0xbd,0x93,0xa5,0x43,0x4d,0xf5,0x07,0xe4,0xce,0xca,0x9f,0xc6,0x66,0xb0,0xac,
+  0x88,0xdf,0xe6,0x5f,0x1f,0xc1,0x9f,0x0f,0xd7,0x6c,0xf1,0x26,0xae,0xa8,0x54,0xdf,
+  0xd6,0x6b,0x10,0xb6,0x72,0x2b,0x2b,0x0e,0x36,0x2e,0xa0,0xf9,0x09,0x8f,0xc3,0xbf,
+  0x92,0xc6,0x10,0x1b,0x97,0x99,0x1b,0x87,0x01,0x98,0x01,0x4b,0x8d,0xdc,0x7e,0x6d,
+  0x54,0xb9,0x16,0x7c,0x86,0xbc,0xd9,0xe6,0x5f,0x7d,0x6a,0x0f,0xcc,0x5f,0xe4,0xd5,
+  0xe4,0x0a,0xe5,0x80,0x12,0x36,0xf2,0xe3,0x0f,0x2d,0x87,0x1e,0xe4,0x05,0x4b,0xe2,
+  0xe8,0x0f,0x2d,0xfe,0xb5,0x1c,0xee,0x57,0x02,0x46,0x34,0x7e,0x17,0x23,0x59,0x01,
+  0xe3,0x86,0x38,0xa9,0x50,0x9e,0x90,0x66,0x2f,0x52,0xe3,0xf8,0x46,0x59,0xfc,0xab,
+  0x16,0x19,0xc7,0x1c,0xc6,0x41,0xe6,0x93,0x5f,0xc1,0x0e,0x23,0xaf,0xdf,0x3d,0x1f,
+  0x59,0xc9,0x0e,0xa3,0xb4,0x9f,0xe4,0xd8,0xeb,0xab,0xb8,0x75,0x8d,0xfe,0xc4,0xf5,
+  0x95,0xb7,0xcc,0x2e,0xa6,0x8f,0xeb,0x65,0x51,0xf7,0x2d,0xee,0xe2,0xf6,0xc7,0xf5,
+  0x59,0xd1,0xca,0x5b,0xdc,0xad,0x99,0xfc,0x61,0xaa,0xa9,0x0e,0xd9,0x56,0x79,0x99,
+  0x31,0xd8,0x14,0x2e,0xce,0x5f,0xd3,0x50,0x86,0x57,0xc2,0xc5,0x4b,0x5e,0x91,0xab,
+  0x25,0x81,0x5f,0xd3,0x90,0x76,0x69,0x97,0x34,0x22,0x5a,0x0d,0x19,0xef,0x20,0xff,
+  0xca,0xdf,0xd4,0x30,0x10,0x65,0xf9,0xc3,0x8d,0xc8,0xbf,0x2e,0xb1,0xf1,0xcb,0xf8,
+  0x10,0xa1,0xcd,0xbb,0xb9,0xed,0x77,0xfa,0x01,0x35,0xbc,0xf8,0xe6,0xb8,0x67,0xa7,
+  0x71,0x20,0xba,0xaa,0x69,0xc9,0x26,0x79,0xa6,0xcd,0xbf,0x3e,0x34,0x3a,0x9a,0xaa,
+  0xb7,0xe4,0xaf,0x25,0x88,0xef,0x80,0x8f,0x6e,0x9d,0x7f,0x56,0xe3,0xdb,0xfa,0x6c,
+  0x4d,0xa5,0xfe,0x02,0x27,0x7f,0x48,0xb7,0xa9,0xc1,0xa8,0xaa,0x6d,0xee,0x93,0xb6,
+  0xa9,0x7a,0xf4,0x46,0x6d,0x73,0x7b,0x7b,0x0b,0xc4,0x9a,0xd4,0x4b,0x48,0xab,0x93,
+  0x3f,0xec,0xb8,0x3f,0x16,0x8c,0x3e,0xbc,0x39,0x32,0x80,0xb0,0x35,0xf3,0xfa,0xbc,
+  0x2d,0xa4,0x02,0x1e,0x96,0x66,0x37,0xa9,0x5b,0xc8,0x5a,0x3b,0x7f,0xf8,0x38,0x60,
+  0x7f,0x9a,0xbc,0x9b,0x8b,0x3e,0xd0,0x3e,0x84,0x70,0xd3,0xf4,0xad,0xf2,0x2f,0xe0,
+  0x80,0x41,0x62,0x4b,0xb6,0x7a,0x76,0xd9,0xf9,0xc3,0x76,0xaf,0xc8,0x16,0x16,0x0d,
+  0xd0,0xb3,0xdb,0x5f,0x88,0x15,0xf8,0x8b,0xfa,0xe8,0xd9,0xc6,0xda,0xe8,0x1c,0xbf,
+  0x7c,0x83,0x9d,0x3f,0xdc,0x46,0x8e,0x19,0x5d,0x5a,0xb0,0xfd,0x6b,0x94,0x98,0x39,
+  0x61,0xad,0x9a,0xca,0x65,0x24,0x65,0x74,0xb1,0x44,0xa2,0xdb,0xc9,0x1f,0x22,0x53,
+  0x08,0xd0,0x1b,0x90,0x7f,0xe1,0xba,0x61,0xf9,0x43,0x46,0xc4,0x90,0xa4,0x57,0x26,
+  0x22,0x6e,0xe1,0xc6,0x18,0x7e,0x31,0x17,0x87,0x61,0xa1,0x97,0x1b,0x51,0x66,0x74,
+  0x42,0xa5,0xe9,0x0e,0xe9,0x6e,0x3b,0xbf,0x31,0xd5,0x58,0x47,0xcb,0xfa,0x3c,0xf7,
+  0x92,0xa9,0xc6,0x43,0xe1,0x32,0x33,0xda,0x4c,0xa6,0xd2,0x75,0xd2,0xac,0x94,0x7a,
+  0x0f,0xe9,0xb0,0xf3,0x87,0x05,0xe6,0x7b,0xc3,0xa1,0xc1,0xfc,0x85,0xee,0x3a,0xfa,
+  0xef,0xc9,0x64,0x1a,0xe3,0xf0,0x82,0xc4,0xcb,0xe9,0x6b,0x86,0x0a,0x46,0xda,0xdc,
+  0x56,0xfe,0x70,0xda,0xaf,0xd0,0xcf,0x57,0xf7,0x3f,0xf8,0x54,0xf9,0x4a,0xfd,0x63,
+  0xa3,0xee,0xb0,0xef,0x19,0xf9,0x93,0xfe,0x73,0xb0,0xe0,0x5d,0x8c,0x7b,0x23,0x22,
+  0xbf,0x61,0xb8,0x2e,0xc0,0x51,0x7a,0xcd,0xb0,0xf7,0xbc,0xfc,0x13,0xe3,0x28,0xdd,
+  0x31,0xa2,0xbc,0xb8,0xa3,0xce,0x38,0xd4,0x7f,0x15,0xcb,0x28,0x6a,0x36,0xff,0x7a,
+  0x41,0x5b,0xa7,0xe8,0x66,0xfe,0x6a,0xf9,0x3b,0x4d,0xc8,0xad,0x3e,0x89,0xde,0x4b,
+  0xbc,0xe6,0xba,0x9d,0x48,0x0c,0xef,0x25,0xb3,0x33,0xf9,0x43,0x5e,0x3d,0x59,0x15,
+  0x99,0xda,0xb2,0x4e,0x9b,0x61,0x5e,0x7f,0x0f,0x79,0xb4,0xe0,0xa7,0xfa,0x77,0xfb,
+  0xdc,0xcd,0x9a,0x62,0xe7,0x0f,0x5f,0xc3,0x90,0x58,0x1f,0xce,0x9b,0x4b,0x96,0x34,
+  0xfe,0x52,0xab,0x38,0x35,0x65,0x61,0xc1,0xee,0xf8,0x43,0x6e,0xbd,0x77,0x76,0xa8,
+  0xf5,0x32,0x9b,0x7f,0xfd,0x2b,0x3d,0x0a,0xcf,0xef,0xf7,0x0e,0x97,0xd7,0xc2,0x51,
+  0x5c,0xcb,0x55,0x67,0xe4,0x97,0xe8,0x7b,0xd2,0x55,0xc3,0x05,0xa3,0xee,0x4a,0xf1,
+  0x5d,0x88,0x5f,0xeb,0x39,0x7e,0x85,0xda,0x86,0x2a,0xce,0xa9,0x0b,0xfb,0x3a,0xf6,
+  0xca,0x2b,0xb5,0x8f,0x8b,0x6b,0xfa,0x5c,0x7b,0x1a,0xac,0xb8,0x4e,0xd2,0xde,0x85,
+  0xf7,0xd4,0xb9,0x18,0xc6,0x97,0xaf,0x84,0xa5,0x2c,0xaf,0xd5,0xfc,0xfd,0x5a,0xf5,
+  0x55,0x98,0x6b,0x7a,0x43,0xb2,0x6e,0xf3,0x2f,0x56,0xa9,0x61,0x90,0x44,0x76,0x43,
+  0x27,0xd9,0xce,0x0d,0xc2,0x12,0x65,0xeb,0x93,0x72,0x22,0x66,0xf1,0xaf,0x95,0x38,
+  0x4d,0x01,0x73,0x56,0xd2,0xef,0x85,0x5f,0x72,0xd7,0x1d,0x08,0xaa,0x9d,0xc0,0x7d,
+  0xa6,0x6e,0xe5,0x0f,0x21,0xd8,0xd8,0x06,0x09,0xf3,0x86,0xf9,0x64,0x43,0xeb,0x0e,
+  0x88,0xa5,0x2e,0x9b,0x0b,0x1b,0xa4,0x36,0x18,0x34,0xdd,0xf3,0x9c,0xfc,0xa1,0xfa,
+  0x63,0x78,0x4f,0x9a,0xf7,0x4a,0xfe,0x19,0xb9,0x56,0xff,0x3d,0x94,0xbf,0x7b,0xd3,
+  0x2a,0x79,0xaa,0xf1,0xea,0xdd,0x57,0xff,0x2f,0xef,0x70,0x83,0x6e,0xe5,0x0f,0xa7,
+  0x8d,0xd2,0x31,0xb8,0x2a,0xe5,0xdb,0x2b,0x0f,0xe9,0xef,0x01,0xfa,0xc3,0xd3,0x32,
+  0x5e,0x59,0x71,0x85,0xb9,0xf1,0xb4,0xbc,0xcb,0xce,0x1f,0x62,0xbc,0x41,0xeb,0xd3,
+  0xd3,0xbb,0xe5,0xf7,0x8d,0x23,0x10,0x8a,0x79,0xbb,0x65,0x16,0x6f,0x84,0xd3,0xde,
+  0x6e,0xa7,0xfe,0x25,0xf8,0x57,0xba,0xb3,0xdb,0x9f,0x56,0xdf,0xa2,0x81,0x88,0xda,
+  0x4d,0xf0,0x8a,0xbe,0xa0,0x57,0xed,0x8e,0x0c,0x5b,0xf1,0x8f,0x88,0xd5,0xcd,0xcb,
+  0x42,0x24,0xcd,0xc8,0x63,0x14,0x43,0xf4,0xc3,0xae,0x3d,0x44,0x4f,0xa1,0x71,0xca,
+  0x65,0x7d,0x97,0x60,0x37,0x53,0x92,0xe4,0x7d,0x78,0x84,0xea,0x4d,0x08,0x5b,0x43,
+  0xda,0xb3,0x5a,0x85,0x19,0x75,0xea,0x5f,0x2c,0x7f,0x78,0x4e,0x64,0xa4,0x5f,0x86,
+  0x43,0x2d,0xe1,0xc6,0x20,0xe3,0xc2,0x67,0x61,0x15,0xab,0x64,0x65,0xd7,0xbf,0x18,
+  0xdb,0x1a,0x6e,0x1b,0x66,0x01,0x70,0x8c,0xe7,0x0f,0xcf,0x03,0xab,0x88,0xc9,0xe3,
+  0xf9,0x97,0x99,0x9f,0xbc,0x75,0x19,0x4b,0xc1,0x35,0x09,0x4e,0xcd,0xf9,0x57,0xc3,
+  0x9b,0x59,0xfc,0x8b,0x54,0x0f,0xba,0x5f,0xf8,0x73,0x1d,0xf6,0x1a,0x01,0x16,0xb4,
+  0x0f,0x59,0xd9,0x5d,0xbb,0xfe,0x65,0xf1,0xaf,0x5e,0xf5,0x6a,0x62,0x40,0x17,0xbe,
+  0x77,0x3c,0x3f,0xff,0x2c,0xcf,0xd8,0x93,0x2f,0xac,0xf5,0xc5,0xf9,0x57,0xd5,0xa0,
+  0xfb,0x3e,0x8c,0xc7,0xf6,0x99,0x3b,0x74,0x84,0xad,0xe3,0x2d,0x4f,0xb7,0x54,0xb1,
+  0x5a,0xd2,0x90,0x9d,0x3f,0xbc,0x19,0x58,0xfd,0xcb,0x7b,0x8d,0xdc,0x80,0xc6,0x7c,
+  0xbd,0xa0,0x46,0x3e,0x42,0x4f,0xc6,0x6b,0x07,0x7d,0xd7,0x60,0x4c,0x6b,0xe1,0x17,
+  0xab,0x7f,0x5d,0x6b,0x16,0x84,0xe4,0x34,0x1a,0x2f,0x2a,0x48,0x81,0xc5,0xb8,0x70,
+  0x80,0xe3,0xf8,0x17,0x67,0x91,0xef,0xc3,0x21,0x98,0x4f,0xf9,0xb8,0xce,0x92,0x3a,
+  0x56,0xe0,0xb3,0xeb,0x5f,0x97,0x8a,0xdc,0xbb,0xa7,0xf9,0xae,0x7e,0x8c,0x0f,0xcb,
+  0xa8,0x9b,0x25,0xe1,0x9f,0xce,0x99,0x63,0xaa,0xcd,0xb7,0x9c,0x12,0xf7,0xe1,0xfc,
+  0x8b,0x56,0xa5,0xdd,0xab,0xc9,0xe7,0xda,0x3a,0x7a,0x45,0x02,0x8d,0xe3,0xf0,0xb4,
+  0xc9,0xab,0x78,0xe9,0x71,0xfc,0x8b,0x8d,0x34,0xc5,0x7c,0x4b,0xe2,0x67,0x6c,0xec,
+  0x7b,0x04,0xff,0x7a,0xdd,0xc9,0x1f,0xb2,0x0a,0x02,0x2d,0x48,0xe4,0x9e,0xa5,0x47,
+  0xe0,0xaa,0x6d,0x05,0x09,0x79,0x10,0xbe,0xa0,0x75,0x34,0x98,0xa9,0x7f,0x49,0x36,
+  0xdb,0xca,0x45,0x83,0xd6,0x28,0xb9,0xe3,0xf8,0x97,0x85,0x5f,0xbc,0x2e,0x63,0x14,
+  0x3c,0x2c,0xef,0x5c,0x78,0x16,0x61,0xab,0x20,0x7e,0x37,0x63,0x2e,0x0b,0x18,0x11,
+  0xeb,0xcd,0xe0,0x17,0xb2,0x89,0x66,0x4f,0x31,0xba,0xe5,0x3d,0x24,0xc1,0xb9,0x95,
+  0xf2,0x2c,0x99,0xcc,0xbf,0xaa,0x17,0x7b,0x10,0xda,0xd0,0xb8,0xcb,0x70,0xf3,0xfa,
+  0x17,0xcc,0x64,0x6d,0xf6,0x8f,0xe7,0x5f,0x1e,0xcd,0x8d,0x86,0x1e,0x60,0xc5,0xb2,
+  0x3e,0x7e,0x45,0x65,0xb5,0x24,0x0b,0xbf,0x62,0xa2,0x87,0x09,0xb9,0xcc,0x40,0x5a,
+  0x51,0xfc,0x20,0xef,0xf3,0x2d,0x0b,0x8a,0x83,0xe3,0xeb,0x5f,0xd8,0xe7,0xcb,0xe3,
+  0xf2,0x9b,0xf0,0xbf,0xb5,0x7a,0x63,0x23,0x12,0x16,0xf5,0xbc,0xa8,0x13,0x65,0xd5,
+  0xbf,0x18,0x47,0xf3,0xf5,0x37,0xcc,0x80,0xdf,0x55,0x86,0x9b,0xf2,0x39,0x47,0x33,
+  0xc2,0x4d,0x2b,0xe3,0xf2,0x7e,0xb0,0xf9,0x97,0xc2,0xf8,0x97,0x87,0xa2,0x9f,0x5d,
+  0x6f,0xcc,0x06,0x95,0xb2,0xfa,0x97,0x1e,0x40,0xa3,0xc8,0xaa,0x7f,0x45,0xa1,0xdd,
+  0xee,0x73,0x23,0xdd,0x83,0x20,0x9e,0xc7,0xfa,0xbc,0xad,0x0c,0x17,0x9a,0x46,0x5e,
+  0xb7,0xf0,0x4b,0xd9,0xc9,0xc6,0xbe,0x08,0xdf,0xde,0xef,0xc2,0xc3,0xda,0x6c,0xa3,
+  0x34,0x6e,0xe0,0xd8,0x5b,0x75,0x1c,0xbb,0x53,0xff,0xb2,0xfa,0x9c,0x1b,0x97,0xbf,
+  0x0b,0x27,0x0d,0x16,0x27,0x60,0x7f,0x3e,0xc4,0x07,0xe5,0x65,0xf5,0xaf,0x6c,0xfe,
+  0xc5,0x46,0xf1,0x0b,0xf8,0x90,0x72,0x83,0xfd,0xab,0x0b,0x8b,0x7c,0xf1,0x86,0x9f,
+  0x65,0xf1,0x2f,0xe0,0xd5,0xae,0x18,0x86,0x97,0x0b,0x90,0x88,0x59,0x73,0x1a,0xcc,
+  0xd4,0xbf,0x38,0xff,0x9a,0x93,0x74,0xc7,0x90,0x92,0x3f,0x08,0x3a,0x23,0x62,0x83,
+  0x9c,0x91,0xa9,0xac,0xfe,0x25,0xe6,0x42,0xf0,0x2f,0xd5,0x3d,0x9b,0xac,0x04,0x9a,
+  0xaa,0x10,0xf5,0xe5,0xe7,0x79,0xc5,0xd9,0xae,0x7f,0x21,0xff,0x82,0xab,0xa0,0x2a,
+  0xe4,0x36,0x36,0x4f,0x35,0xd7,0x80,0xc4,0xd2,0x86,0xef,0xb2,0x37,0xbc,0xaf,0xa3,
+  0x19,0x6f,0xc8,0xef,0xd3,0xa1,0x3e,0xc6,0xf8,0x57,0xa2,0x20,0x2a,0x7f,0x87,0xf6,
+  0xd1,0xab,0x86,0xbd,0xab,0xe5,0xe3,0xf0,0x87,0x74,0xfd,0xc0,0x86,0xd5,0xf2,0x47,
+  0x16,0x7e,0x95,0xec,0xd6,0xce,0xb1,0x3a,0x2c,0xc8,0x9f,0x28,0x38,0xc0,0x63,0xd5,
+  0xb8,0x76,0xf0,0x4a,0x5d,0x3f,0xae,0xa6,0x5e,0x81,0x5f,0xa0,0xbc,0x88,0xfe,0xf0,
+  0x5a,0xdd,0x1b,0x95,0x5f,0x32,0x2e,0xd0,0x3d,0x67,0x5c,0xdd,0xe5,0x17,0xd0,0xfb,
+  0xd5,0x23,0x45,0x2e,0x32,0x35,0x81,0x5f,0xa5,0xc8,0xa4,0x30,0xfc,0xce,0xbf,0xc1,
+  0x3f,0x1d,0x3e,0xd7,0xaf,0x1c,0x54,0xef,0x93,0x37,0xc0,0xbe,0x78,0x95,0x99,0x7f,
+  0x2f,0xf9,0x48,0x3c,0x1f,0xab,0xfe,0x65,0xa8,0x8b,0xc8,0xa3,0xf0,0x0c,0x29,0x4f,
+  0xe5,0xad,0x12,0x7d,0x66,0x9d,0x37,0xc5,0xf3,0xb1,0xf8,0x17,0xe4,0x01,0xf1,0xd1,
+  0xed,0xfd,0x15,0x0c,0xc4,0xf1,0x8a,0x8b,0x57,0xc4,0x52,0x36,0x7e,0x31,0x3f,0x56,
+  0x0b,0x5e,0x90,0x5f,0xd0,0xbb,0xcd,0xbd,0xe8,0xd0,0xca,0x59,0x4e,0xe6,0x9f,0xf8,
+  0x7a,0x77,0xf0,0x8b,0xf9,0x04,0xed,0x28,0xfd,0xfa,0x6e,0x60,0xf5,0x2f,0xe1,0xeb,
+  0x24,0x46,0xc4,0x64,0x2b,0x7f,0x58,0x26,0xea,0x5f,0xe0,0xed,0x41,0x9a,0x73,0x78,
+  0xeb,0x3c,0x24,0x62,0x3c,0x67,0x35,0x0f,0x7d,0x4b,0x83,0x29,0xf0,0x4b,0xf0,0xaf,
+  0xea,0x79,0xee,0x76,0xcf,0x12,0x25,0x81,0x00,0x94,0xcf,0xfc,0xe1,0x5e,0x91,0x1f,
+  0xb3,0xd6,0x17,0x15,0x39,0x2b,0x1d,0x5f,0xd1,0x95,0xca,0x56,0x95,0xf3,0xaf,0x21,
+  0xf8,0x25,0xc7,0xb8,0x9c,0x0c,0xff,0x52,0x70,0x5c,0x8a,0xbb,0x18,0xe7,0x34,0xa1,
+  0x6c,0x7f,0x79,0x4a,0x38,0x8c,0x73,0x7a,0x7d,0xc2,0xf4,0xcc,0xdd,0xdc,0x6b,0xe7,
+  0x0f,0xd9,0x77,0xd5,0x69,0xde,0xb5,0xf2,0x3f,0x9a,0xc7,0xa4,0x79,0xef,0x16,0xec,
+  0x91,0x3f,0x81,0x8f,0x8d,0x42,0x56,0x2b,0x31,0x25,0x9b,0x7f,0x25,0xb0,0xcf,0xaa,
+  0x6f,0x6d,0xd1,0x50,0xe3,0x19,0xa8,0x4b,0xe5,0x7f,0xde,0xc0,0xaf,0x98,0x4b,0x87,
+  0xe5,0x4c,0xfd,0x8b,0xe3,0x97,0xef,0x59,0xf9,0x20,0x0c,0xd1,0x9a,0x3e,0xef,0x88,
+  0x3c,0xda,0x3e,0x16,0xb8,0xb2,0x02,0x0d,0x47,0xbf,0x21,0xf0,0xeb,0xc6,0x2e,0xed,
+  0x23,0x38,0x46,0xb7,0xbd,0xab,0x76,0xb5,0x8e,0xc6,0x5e,0x8a,0xe3,0x42,0x4b,0xb6,
+  0x66,0xf4,0x1b,0xc2,0xd7,0x85,0xf5,0xc1,0x4b,0x76,0x41,0x65,0x8f,0x1a,0x0a,0x6c,
+  0xa0,0x7b,0x61,0xb9,0xda,0x11,0xce,0xb1,0xf5,0x1b,0x25,0xac,0xda,0xc5,0xd0,0x21,
+  0x32,0xa8,0x6e,0xd5,0x03,0xe6,0x8a,0x24,0x0c,0x15,0x5e,0x03,0x95,0xd7,0x67,0xe9,
+  0x37,0x4a,0x9c,0x2c,0xdf,0x21,0x33,0xad,0xd6,0xb0,0x69,0xda,0xad,0x9e,0x23,0x0b,
+  0x12,0xde,0x89,0xf8,0x25,0xd0,0x6a,0x94,0xda,0xf5,0x2f,0x0c,0x4e,0xe6,0x4c,0xc2,
+  0xaf,0xa5,0xc9,0xa2,0x0f,0x03,0xa9,0x45,0x4c,0xc8,0xc1,0x38,0x35,0x59,0xc0,0x1c,
+  0xfe,0x38,0xfd,0x46,0xb5,0x79,0x63,0x32,0x30,0x88,0x5c,0xe6,0xef,0x7b,0xb0,0x1b,
+  0xa3,0xea,0x3e,0x3d,0xd0,0x93,0x9f,0x94,0xbb,0xc6,0xe9,0x37,0x7a,0x3a,0xd9,0x1b,
+  0x45,0x85,0xeb,0xc6,0x91,0xa6,0x39,0x90,0x65,0xf4,0x1b,0x1c,0x0b,0x30,0x3e,0xbc,
+  0xd0,0x84,0x44,0x8c,0x15,0x95,0x8e,0xc3,0xde,0x96,0xf2,0x0a,0x69,0xb5,0xb6,0xd5,
+  0xe6,0x5f,0x5e,0x86,0x5f,0x26,0xf2,0xaf,0x83,0x09,0x80,0x60,0x1a,0x81,0xec,0xb0,
+  0x7a,0x3a,0x19,0x82,0x82,0x6c,0xfd,0x06,0x8e,0x02,0xc7,0x7e,0x52,0x1e,0xa1,0xa3,
+  0xc0,0x6b,0xac,0x9f,0xe8,0x63,0xe4,0x79,0x03,0xaf,0xd8,0xfc,0xcb,0x35,0x54,0xca,
+  0x9f,0x4f,0xb7,0x5c,0x09,0x27,0xa0,0xeb,0x30,0x3e,0xa8,0x4f,0xe0,0x5c,0xf4,0x27,
+  0x65,0x18,0x78,0x64,0xea,0x5f,0x16,0x7e,0x45,0x4a,0xb5,0x76,0x28,0xeb,0xf5,0xe0,
+  0x7a,0xa7,0xfb,0xf4,0xbf,0x37,0xd4,0x61,0xe4,0x4d,0xfc,0x3e,0xa6,0x85,0x5f,0x88,
+  0xb0,0x61,0x78,0xa1,0xbd,0xec,0x43,0x46,0x1e,0x29,0xae,0xc1,0xb9,0x95,0xab,0x1d,
+  0xfe,0x55,0xec,0xe0,0x57,0x5e,0xac,0x95,0xb2,0xfc,0xc6,0x62,0x7e,0xa5,0x19,0x1f,
+  0x82,0xc3,0xbf,0x06,0x39,0x7e,0xf9,0x12,0xb9,0xa5,0x70,0xc1,0x64,0xf9,0x43,0x59,
+  0x64,0x14,0x97,0x24,0xca,0x1d,0xfe,0x95,0x50,0x58,0xae,0x69,0x29,0x95,0x4f,0x68,
+  0x23,0xa1,0x1f,0xc3,0x4d,0xb4,0x88,0x11,0x8d,0x3a,0x75,0x29,0xcd,0x1d,0xa7,0xdf,
+  0xe0,0x7e,0xf5,0x03,0xe3,0x00,0xc2,0xd6,0x91,0x78,0xa4,0x0f,0x79,0x41,0x98,0x39,
+  0xcf,0xf1,0xf8,0x65,0xe4,0xc5,0xc9,0x07,0xb4,0x05,0xf9,0x57,0x20,0x1e,0x58,0xae,
+  0xb4,0x98,0x81,0x45,0x1e,0x07,0xbf,0x4a,0x05,0x7e,0x09,0xd9,0xc6,0xfd,0x1c,0xb6,
+  0xfc,0x03,0x9c,0xac,0x79,0x1c,0xfc,0x52,0x15,0x81,0x05,0x08,0x01,0x03,0x24,0x8f,
+  0xe8,0x51,0xb7,0x46,0x1a,0x1f,0x6a,0xab,0xd0,0x0d,0x4f,0x06,0xbf,0xbc,0x16,0xc2,
+  0xba,0xd0,0x03,0x44,0x61,0x41,0x71,0xc1,0x1a,0xf9,0x44,0x53,0x0a,0xba,0x8a,0x7d,
+  0x6b,0x1c,0xfc,0x9a,0x66,0xfb,0xf9,0xc2,0x37,0xe1,0xbc,0x82,0xfc,0x0b,0xfd,0x3c,
+  0x32,0x32,0x44,0xab,0x78,0x79,0xb6,0x7e,0x43,0x70,0x99,0x1f,0x28,0x3d,0x24,0xdc,
+  0x58,0x80,0xa4,0xc6,0x38,0x9f,0x17,0x32,0x36,0x60,0x1b,0x47,0xbf,0xa1,0x75,0x2b,
+  0xd5,0x92,0xa7,0x95,0xa4,0x55,0x96,0x3f,0xac,0x84,0x48,0xcf,0x6d,0xdd,0x46,0x40,
+  0xca,0x6f,0x85,0x8c,0x7e,0xc3,0xc2,0xaf,0xd6,0x3e,0xf2,0x04,0xc6,0x87,0x51,0x34,
+  0xe8,0x1e,0x08,0xdc,0x80,0x46,0xb6,0x7e,0xc3,0x1a,0x3b,0x7d,0xa2,0x69,0xbb,0x01,
+  0x02,0xbb,0x03,0xac,0x1a,0x98,0xd1,0x6f,0x28,0x6f,0x91,0x3a,0x63,0x69,0xfc,0xd6,
+  0xef,0x6e,0x3d,0x21,0x85,0x8d,0x9c,0xf8,0xad,0x03,0xca,0x59,0xe2,0xbf,0xc5,0x1b,
+  0x2f,0xca,0xe8,0x37,0xf0,0x5f,0xb1,0x3e,0x13,0xd6,0xf9,0x5a,0x36,0x9c,0x01,0xed,
+  0x24,0xfc,0x7a,0xd1,0xe5,0xf1,0xdc,0x2c,0xfd,0x86,0x15,0x81,0x24,0xd4,0x54,0x4e,
+  0x98,0xe1,0x97,0x8e,0x2b,0xca,0xd2,0x6f,0xf0,0x67,0xc8,0xf8,0x17,0xa2,0x15,0x4b,
+  0x1b,0x4e,0x31,0x9f,0x14,0x69,0x43,0x04,0xb2,0x74,0x10,0xf1,0xcb,0x9f,0xd1,0x6f,
+  0xd8,0xef,0x98,0xa4,0xc9,0x36,0x11,0x6b,0x29,0xe3,0x8a,0x29,0x47,0xbf,0x31,0x55,
+  0xbc,0xcf,0xab,0x49,0x29,0xbc,0x04,0x33,0xfa,0xe4,0xfb,0x10,0x38,0xda,0xc9,0x9c,
+  0xbe,0xca,0x55,0x19,0xfd,0x06,0xcf,0x1f,0xa6,0x7d,0x23,0x6d,0x9b,0xe1,0x55,0x3a,
+  0x77,0xc8,0x75,0x5f,0xdb,0x74,0x63,0x3f,0x9d,0x96,0xf6,0xde,0x2b,0xdb,0xfa,0x8d,
+  0x69,0xc2,0x27,0xf8,0x9e,0x92,0x4d,0xf5,0x63,0x78,0x0e,0x61,0xcb,0xf3,0x49,0x74,
+  0x44,0xa9,0xeb,0xf7,0xec,0xcd,0xe8,0x37,0x3e,0xb5,0xfc,0x61,0xdb,0x7e,0xe3,0x3d,
+  0x5a,0x33,0xb0,0xf1,0xd9,0x1d,0x75,0x8d,0xa9,0xd6,0xf0,0x30,0xae,0x2f,0x87,0x7f,
+  0x3d,0xc6,0xfa,0x83,0xd1,0xa9,0xff,0x75,0x58,0xa7,0xcf,0x4a,0x7b,0x9e,0x0b,0x3c,
+  0xa6,0xd1,0xe4,0xac,0xc1,0xfc,0x1a,0xb7,0xcd,0xbf,0x0c,0xbe,0x06,0x53,0xb8,0xf4,
+  0xfa,0xe9,0xff,0x50,0x66,0x31,0x63,0x89,0xb1,0x65,0xee,0x15,0xa9,0x4b,0x57,0x91,
+  0xf6,0x2c,0xfd,0x86,0x18,0x7b,0x0f,0xec,0xe0,0xf9,0x79,0xc4,0x8b,0x38,0xd9,0xdd,
+  0x8f,0x0f,0x61,0x6b,0x36,0x7e,0xd5,0x31,0x57,0x60,0xde,0xf5,0x4e,0xfa,0x1a,0x66,
+  0xfc,0x98,0x1c,0xc3,0x30,0x79,0xc9,0xb0,0xfc,0xeb,0x71,0xf8,0x85,0x3e,0xb3,0xfc,
+  0x84,0xfa,0x08,0xbc,0x88,0x4e,0x4f,0xde,0x0d,0x83,0x50,0x83,0xf8,0x25,0x2d,0x9b,
+  0xa4,0xdf,0x18,0x86,0xf7,0xd0,0xb7,0x5c,0x3e,0x0c,0xa3,0x70,0x18,0xe6,0xf5,0x22,
+  0x90,0xa5,0x33,0xfc,0xcb,0x8a,0xde,0xdf,0xd7,0xdf,0x80,0x05,0xe6,0x23,0x88,0x5f,
+  0xe8,0xf4,0x76,0x99,0x1d,0x88,0x5f,0xb1,0x09,0xfa,0x0d,0xc6,0x41,0x24,0x4b,0xbf,
+  0xb1,0x2b,0xc6,0x88,0x98,0xdf,0xd6,0x6f,0x20,0xda,0xce,0x63,0xfa,0x8d,0x05,0xc4,
+  0x8c,0x3c,0x02,0x15,0x08,0x0a,0xfe,0xc3,0x89,0x04,0xcc,0xee,0xc5,0xbe,0x38,0xfc,
+  0x8b,0xfb,0xf9,0x94,0xef,0x94,0x9c,0x6e,0x7d,0x07,0xae,0x3a,0xe6,0x19,0x2e,0x1a,
+  0x6d,0x1d,0x5c,0x3d,0x2f,0xe5,0xfd,0x07,0x39,0x6d,0xf1,0xaf,0x4b,0xcf,0x33,0x7f,
+  0xd8,0xef,0xfb,0xbc,0x68,0xb8,0xef,0x1f,0xa0,0xfe,0x88,0xe7,0xf3,0x97,0x87,0x94,
+  0x37,0x03,0xd7,0x9a,0x7f,0xff,0xb9,0x3c,0xe8,0xca,0xc6,0xaf,0x01,0xdf,0x08,0xd2,
+  0xae,0x31,0x13,0x27,0x8e,0xf3,0x2f,0x6d,0x1e,0x33,0xc6,0xe3,0x57,0xca,0x83,0xb4,
+  0x4b,0x79,0x5e,0xaf,0x4e,0x7b,0x92,0x9b,0x87,0xf4,0x97,0x20,0x90,0xf6,0x64,0xeb,
+  0x0f,0xed,0xb9,0xb0,0x81,0x8c,0x1c,0xa6,0x7b,0x2b,0x78,0x52,0x37,0x1b,0xbf,0x2c,
+  0xed,0x8a,0x2d,0x44,0xcc,0xd4,0xbf,0xc6,0xf3,0x2f,0x1f,0x0b,0x21,0x9e,0x17,0x49,
+  0x5d,0x5e,0xff,0x12,0xba,0xc1,0x71,0xf8,0x65,0xc1,0xd6,0x78,0x63,0x02,0x7e,0xb1,
+  0xfb,0x28,0xe7,0x94,0xe9,0xe2,0x86,0xa7,0x99,0xa0,0x71,0x12,0x7e,0x21,0x9e,0x3a,
+  0xb4,0x6b,0x08,0x17,0xc8,0xf6,0x8b,0xe8,0x0f,0x33,0xe3,0xca,0xe4,0xe7,0x27,0xe0,
+  0xd7,0x89,0xce,0x7b,0xc9,0x71,0xca,0x65,0x87,0x0c,0xbf,0x5e,0x8a,0x97,0xa5,0x3d,
+  0xf7,0xd9,0xeb,0xcb,0xc1,0xaf,0xab,0x1b,0x8e,0x30,0x21,0x62,0xda,0xb7,0x50,0x3e,
+  0x0c,0xe7,0x12,0x0b,0xcd,0x6c,0xfd,0xe1,0x6e,0x31,0x8a,0x64,0xc3,0x90,0x31,0x26,
+  0x3a,0x3f,0x6a,0x9c,0xb3,0x34,0x93,0x0e,0x7e,0x89,0x71,0x2d,0xcc,0x0d,0x66,0x1e,
+  0xd4,0xb9,0x8e,0x1f,0xa2,0xb1,0xe8,0xa3,0x89,0xf8,0x95,0x63,0x2d,0x7c,0x16,0xaf,
+  0xbe,0x64,0x2c,0x33,0xc7,0xeb,0x0f,0x2d,0xfc,0x9a,0xae,0x59,0xc6,0x71,0xd8,0xd7,
+  0x5e,0x76,0x62,0xbc,0xfe,0x70,0xaf,0x12,0x34,0x65,0xe6,0x52,0xf8,0xd8,0x93,0x99,
+  0xb1,0x4f,0xe0,0x5f,0xbe,0x84,0xa7,0xd2,0x32,0x18,0xff,0x82,0x05,0xcc,0xc8,0xd2,
+  0x1f,0x5a,0x6a,0x43,0x87,0x76,0x4d,0xe6,0x5f,0x8e,0xc2,0x4d,0x18,0x88,0x05,0x15,
+  0xaa,0x75,0x65,0x02,0x7e,0x09,0x49,0xa1,0xc4,0x65,0x75,0x15,0x9a,0x75,0xe5,0x62,
+  0xf8,0x65,0x19,0xce,0x15,0x07,0xbf,0x6c,0xfe,0x45,0xfa,0xb2,0x89,0x58,0x30,0x1b,
+  0xbf,0x04,0xff,0x2a,0x16,0x5d,0x6d,0xaa,0x83,0x07,0x98,0x10,0x71,0xe4,0x36,0xde,
+  0x67,0x07,0xbf,0x26,0xf4,0xf9,0x26,0x6e,0x68,0x13,0xf9,0x17,0xc7,0xaf,0x7e,0xf6,
+  0x27,0xc2,0x4b,0x63,0x68,0xdc,0xcc,0xdb,0xec,0xcf,0xd2,0x1f,0x42,0xb5,0xea,0x61,
+  0xb4,0x2b,0xc9,0x93,0xd5,0x18,0xa2,0x27,0x0d,0xc6,0xc8,0x26,0xe0,0x57,0x44,0xf4,
+  0x59,0x45,0xf0,0xf5,0x47,0xfa,0x12,0xd6,0x28,0x26,0xe1,0x17,0x0c,0x64,0x3d,0x04,
+  0xa5,0x80,0x8f,0x3d,0xc3,0xbf,0xde,0xca,0xee,0xb3,0x65,0x4c,0x67,0x62,0xce,0xc1,
+  0x8c,0x7e,0xe3,0xde,0xf1,0x6d,0x8a,0xb2,0xf4,0x87,0xb1,0x6c,0xfc,0xe2,0xfc,0x6b,
+  0x04,0x16,0xb0,0xc7,0xc2,0xf3,0xd8,0x50,0x30,0x81,0x7f,0x31,0xb6,0x15,0x11,0x65,
+  0xaf,0x1b,0x19,0x7e,0xad,0x17,0x46,0x16,0xff,0x7a,0x48,0xb0,0x2d,0xb6,0xd0,0x2a,
+  0x98,0xac,0xd7,0x0b,0x2c,0xfb,0xed,0x71,0xf8,0x57,0x42,0xe0,0x57,0x5a,0xd0,0x2e,
+  0x5a,0x66,0xca,0xf7,0x92,0xe9,0xdf,0x5c,0x97,0x98,0xc5,0xde,0xe7,0xc1,0x8c,0x7e,
+  0xe3,0x0f,0xe8,0xc7,0x90,0x76,0x7d,0x07,0xfe,0xd0,0x71,0x65,0xda,0xb7,0x5a,0x9e,
+  0xae,0xbf,0x9a,0x98,0x9b,0xde,0x98,0xe1,0x5f,0xd3,0x76,0x4b,0xb8,0x64,0x0e,0x0b,
+  0x9f,0xa0,0xe3,0xda,0xe9,0x92,0x87,0xda,0xcf,0x2d,0x7f,0x86,0x2d,0x22,0x0b,0xbf,
+  0x40,0xe8,0xb1,0x07,0xbc,0x67,0x65,0x34,0x3a,0xe6,0x0d,0xf8,0xce,0xcb,0x9f,0x1a,
+  0x47,0x53,0xf3,0xd2,0x9d,0x23,0xb2,0xe9,0xe0,0x17,0xe5,0xfd,0x61,0xfa,0xc3,0x97,
+  0xca,0x74,0xb6,0xde,0x2f,0x18,0xeb,0xda,0xcb,0x06,0x0b,0x7e,0x44,0x3e,0x72,0xf2,
+  0x87,0x06,0xd7,0x1f,0x72,0xda,0x45,0x66,0x88,0x35,0xf8,0x53,0x28,0x43,0x20,0x0b,
+  0x98,0xb6,0x7e,0x43,0xb8,0x94,0xbc,0x2c,0x97,0x72,0x98,0x27,0x51,0x71,0xa1,0x8d,
+  0xe3,0x5f,0xf5,0x66,0x55,0x92,0x97,0xc2,0xbb,0x58,0xd0,0x3e,0x4a,0xde,0x53,0xfc,
+  0x5c,0x7f,0x38,0x1e,0xbf,0x0a,0xd0,0x6f,0x30,0xa3,0x87,0xfb,0x84,0x8f,0xc1,0xaa,
+  0x7f,0x65,0xf0,0x4b,0x72,0x5c,0xe5,0x3f,0xa1,0x51,0x34,0x2a,0x14,0x80,0xc3,0x32,
+  0x8c,0xc7,0xaf,0x1b,0xd1,0x3f,0x4b,0xcf,0x2b,0x75,0xb6,0x7f,0xae,0x36,0x6f,0x4e,
+  0xca,0x09,0x5b,0xbf,0x11,0xb4,0x73,0x68,0xb6,0xcf,0x9c,0xe9,0x38,0x4f,0x3d,0xa3,
+  0xdf,0x10,0x5a,0xf4,0x08,0x2b,0xe7,0x55,0xa6,0x0e,0x31,0xfd,0xe1,0x5e,0x3d,0x98,
+  0x72,0x77,0xf9,0x5b,0x33,0xfc,0xeb,0x1c,0x5c,0xdb,0xeb,0xdb,0x27,0x7f,0x42,0x5f,
+  0x82,0xea,0x37,0x59,0x6e,0x10,0xc6,0x98,0x78,0xf2,0x69,0x19,0xac,0xfa,0xd7,0xa5,
+  0xcc,0x0d,0x62,0x0f,0x9f,0x91,0x87,0xd2,0x63,0x4a,0x5d,0x9f,0xaf,0xab,0x01,0xfd,
+  0xe1,0xc2,0xba,0xbe,0x82,0x67,0xe4,0x5d,0x96,0x7e,0xc3,0xf5,0x22,0x7c,0xb6,0xb6,
+  0x0e,0xe3,0x16,0xf9,0x45,0x72,0x34,0x30,0xaf,0x1f,0x8d,0x21,0x38,0xea,0xaa,0x4f,
+  0x2d,0x3d,0xeb,0x71,0xea,0x5f,0x9f,0xba,0x18,0xff,0x42,0xd8,0xfa,0x54,0xdb,0x78,
+  0x5f,0x79,0x3f,0x76,0x75,0x0c,0x3a,0xfb,0xe7,0x0c,0xdc,0xd8,0x15,0xb0,0xeb,0x5f,
+  0x56,0xae,0xc9,0x1d,0x66,0x14,0x18,0x2a,0x8e,0xb1,0xb9,0x88,0xb6,0x09,0x20,0xdb,
+  0x3e,0x11,0xbf,0xf8,0xd8,0x67,0x73,0x20,0xcb,0xe9,0x84,0xea,0x1e,0x4f,0x32,0x27,
+  0x64,0xe1,0x57,0xa1,0x93,0x3f,0xdc,0xed,0x3d,0x07,0xab,0xd8,0x34,0x0d,0x31,0xc5,
+  0x38,0x7b,0xc7,0xe2,0x13,0xf1,0xeb,0xee,0x51,0xfd,0x55,0x0c,0x45,0xbe,0x21,0x74,
+  0x0e,0x75,0x93,0xf0,0x2b,0x6c,0x3a,0x69,0x43,0x37,0x1a,0xe4,0x90,0xc2,0xf3,0x6c,
+  0xe3,0xf0,0x8b,0xa1,0xa7,0xfc,0x20,0xad,0x87,0x39,0xc8,0xbf,0x02,0xc7,0x61,0x23,
+  0xcc,0x61,0xb9,0xdc,0x71,0xf8,0x65,0x97,0x56,0x61,0xa5,0x79,0x03,0x1a,0xc6,0x0e,
+  0x12,0x34,0xa3,0x49,0x25,0x83,0x5f,0xd2,0x4b,0x09,0xae,0x3c,0x7f,0xac,0x1d,0xb1,
+  0x60,0x88,0xf3,0x2f,0xae,0xa8,0xbf,0x2f,0xe2,0xe0,0x57,0x81,0x79,0x2e,0x91,0xfc,
+  0xf0,0xc1,0x1a,0xf9,0x08,0x9c,0xa6,0x75,0x43,0x05,0x0b,0x1b,0x8e,0x98,0xbf,0x5d,
+  0x53,0x3b,0x14,0xac,0x91,0xb2,0xf9,0x97,0x56,0xdf,0xc7,0xd2,0x86,0xaa,0x90,0xa3,
+  0xc8,0xe7,0xe1,0x46,0x36,0xd2,0x3d,0xd9,0xfa,0x43,0x36,0x9c,0xcb,0xbb,0x65,0xc4,
+  0xaf,0x85,0x75,0x29,0x36,0x40,0x7a,0x8e,0xd4,0xbd,0xee,0x9b,0xcc,0xbf,0x86,0x09,
+  0x5b,0xf8,0xc1,0x37,0xec,0x7c,0xcb,0x31,0x4f,0xb3,0x3b,0xab,0xfe,0x25,0x60,0x6b,
+  0xd5,0xf4,0xd2,0x5f,0xec,0x14,0x9c,0xd1,0xdc,0x97,0xe4,0x40,0x96,0x54,0x6c,0xfc,
+  0x52,0x04,0x64,0x47,0xbc,0xd6,0x26,0x02,0x01,0xe2,0xcc,0xb7,0x6c,0x9e,0x88,0x5f,
+  0xc8,0x07,0x3f,0x92,0x58,0xda,0xb0,0x41,0x30,0xb2,0xa5,0x09,0xf9,0xb9,0xf1,0xf8,
+  0xe5,0xc0,0xd6,0x37,0x28,0x2f,0xf4,0xb0,0x2b,0xd2,0x2d,0x93,0xf1,0x8b,0xe5,0x76,
+  0x8c,0x95,0x68,0xd0,0x93,0xca,0xc5,0xf8,0x17,0x7a,0xe3,0xe5,0x29,0x2b,0x6d,0xf8,
+  0x01,0xe2,0xd7,0xec,0x2f,0xc5,0x2f,0x29,0xb8,0x48,0xb5,0x39,0xc8,0x45,0xf1,0xab,
+  0x11,0xf6,0x04,0x82,0xd1,0x94,0xd0,0xcf,0x57,0x46,0x27,0xe1,0x17,0x20,0xdb,0xe2,
+  0xf8,0x55,0xbc,0x61,0x8d,0xad,0x4f,0x70,0xc9,0x9f,0x4a,0xe3,0xf1,0xab,0xbf,0x68,
+  0xb9,0xd0,0xcf,0x23,0x4f,0x71,0xf4,0xf3,0xe2,0x5d,0x2d,0x95,0x44,0x9b,0xa5,0x71,
+  0xf9,0x07,0x70,0x00,0x6a,0xd8,0x9f,0xce,0xc0,0x59,0x7d,0x15,0xc7,0x2f,0x25,0x1b,
+  0xbf,0xc0,0x43,0x70,0x14,0xbb,0xf4,0x00,0x20,0x11,0x3b,0xb1,0xa8,0x5b,0x5a,0xa0,
+  0xa1,0xe1,0xe0,0x57,0xa3,0xc3,0xbf,0xa0,0x25,0xaa,0xdf,0xc1,0x8d,0x3d,0x86,0xde,
+  0xe4,0xb9,0x28,0xff,0x92,0x9e,0x90,0x02,0x86,0xcc,0xc6,0x7e,0x35,0x99,0x29,0xc6,
+  0xee,0xe0,0x97,0xc5,0x73,0x07,0xe0,0x80,0x54,0x23,0x40,0x8a,0x3d,0x1f,0xa6,0x9f,
+  0x07,0x07,0xbf,0x32,0xd0,0x46,0x5e,0xe4,0x79,0x51,0x38,0x79,0x51,0xfc,0x62,0xb4,
+  0xcb,0x1c,0x86,0x9f,0xb0,0xb2,0x97,0x6e,0xcf,0xb2,0xcd,0xd1,0x38,0x7e,0x15,0x30,
+  0xda,0x35,0x05,0x8d,0x9f,0xb0,0xb4,0xa1,0x40,0xb4,0x86,0x44,0xc3,0x04,0xfd,0xc6,
+  0xc3,0x21,0x92,0xc3,0x5f,0x36,0x77,0x88,0x28,0x3c,0x6a,0x62,0xf8,0xa5,0x64,0xe3,
+  0x97,0x89,0xd1,0xa0,0x06,0xfb,0x34,0x95,0x25,0xbd,0xd9,0x95,0x7c,0xb3,0xb3,0x99,
+  0xec,0xca,0xc6,0xaf,0x6b,0xd3,0x37,0xdd,0xd7,0x76,0x19,0x1a,0xf9,0xe9,0xe9,0x67,
+  0xe5,0x4b,0xf2,0x38,0x23,0x5b,0x2d,0x7d,0x94,0xcd,0xbf,0xa6,0xb3,0xd5,0x94,0x86,
+  0x73,0xee,0xba,0xfe,0xfc,0xae,0xaf,0x0f,0x88,0x20,0xf0,0x99,0xb6,0x0c,0x7e,0x01,
+  0xc3,0x2f,0xdf,0xb3,0x32,0x31,0x8e,0xb6,0x84,0x3f,0x47,0x42,0xf7,0xb9,0x71,0x94,
+  0x29,0xea,0xcf,0x3e,0xe4,0xe0,0xd7,0x83,0xb0,0x77,0x3b,0x86,0xa9,0x0b,0x67,0x13,
+  0xfa,0x06,0xe8,0xe9,0x29,0x0b,0x71,0x7d,0xed,0x48,0x06,0xcd,0xca,0x1a,0x7f,0x06,
+  0xbf,0xb4,0x7d,0x7a,0x95,0xe9,0x1e,0x26,0x4d,0xb0,0x4e,0x2b,0x33,0x6f,0x6c,0x26,
+  0x7d,0xca,0x3a,0x7f,0x90,0xe7,0x0f,0xb3,0xf1,0x8b,0x2b,0xc1,0x0c,0xe4,0x32,0xdc,
+  0xc9,0xf4,0xc1,0x0e,0xae,0x66,0xc9,0xc2,0x2f,0x0c,0xbf,0xd1,0x1f,0x0e,0xcb,0x06,
+  0x1c,0x85,0xbd,0xe8,0xe2,0x70,0x4e,0x99,0x3f,0xf4,0x0e,0x4f,0xc4,0x2f,0x0c,0xf5,
+  0x13,0x3c,0x6d,0x88,0x7e,0xc3,0x1a,0x17,0xe3,0x44,0x13,0xf8,0x57,0xf9,0x30,0x7c,
+  0x06,0xf3,0x18,0x0e,0x2e,0x00,0x91,0x8b,0x0b,0x98,0x93,0xf8,0xd7,0x6f,0x95,0x4e,
+  0x0c,0xe3,0x0b,0x92,0xe4,0xd7,0xf6,0x95,0xf4,0x78,0xfc,0xc2,0x98,0xff,0x7d,0x9d,
+  0xd5,0xbf,0xb0,0xcf,0x15,0xd4,0x6e,0xe3,0xe0,0x97,0xbe,0x57,0x0d,0xf6,0x79,0xe6,
+  0x13,0xd3,0xc4,0x50,0xe4,0xf0,0xc1,0x30,0x59,0xa3,0xe2,0x15,0xd3,0x33,0x8f,0x38,
+  0xf9,0xc3,0xef,0x99,0xcf,0x37,0x23,0xff,0xfa,0x5c,0x4e,0xd3,0xdf,0x37,0x21,0xee,
+  0x7c,0xfe,0xb5,0x19,0xda,0xb9,0x50,0xdd,0x9b,0x4b,0x87,0xcb,0x1d,0xfd,0x06,0x1b,
+  0x57,0xfd,0x31,0xdf,0x0f,0x1b,0x86,0xcd,0x31,0x7d,0xce,0x2b,0x05,0x7b,0xdb,0x46,
+  0xe3,0xe7,0xca,0xea,0x0f,0x20,0xa2,0xd9,0xfa,0x43,0x31,0x5f,0x69,0xce,0xbf,0x5e,
+  0x12,0x44,0xec,0xd7,0xf0,0x39,0x63,0xd0,0x4e,0xfe,0xd0,0xb4,0xf2,0x87,0x9e,0xae,
+  0x56,0x87,0x88,0x0d,0xd1,0xe7,0xf0,0x4a,0x1e,0xf2,0x2f,0xf1,0x7c,0xa2,0x4e,0xfe,
+  0x90,0x6c,0x50,0xe7,0x59,0x3c,0x45,0xef,0x12,0xc6,0x47,0x93,0xf9,0x57,0x06,0xc8,
+  0x9e,0x13,0x86,0xc5,0xbf,0x68,0x86,0x7f,0x09,0x02,0x75,0x79,0xd2,0xda,0xa3,0x81,
+  0x57,0x2c,0x4d,0x4e,0x06,0xbf,0x1a,0x46,0xad,0x29,0x40,0xec,0xbe,0xc0,0x77,0x49,
+  0x34,0x8c,0x08,0x2d,0x0d,0xc3,0xaf,0x8f,0x1d,0xfe,0x05,0x82,0x7f,0x15,0x7f,0x41,
+  0xfd,0x59,0xfc,0xab,0xc3,0x15,0xa4,0x59,0x78,0xea,0xf4,0x67,0x22,0xff,0xda,0x31,
+  0x89,0x7f,0x75,0x09,0x44,0x1b,0x16,0x53,0x91,0x68,0x99,0x4e,0x05,0x16,0xe4,0xd8,
+  0xfc,0x2b,0x70,0x9c,0xbe,0x48,0xcb,0x18,0x16,0x1c,0xa3,0xbc,0x0d,0xdb,0xff,0xf5,
+  0x5b,0xe0,0xfa,0x8d,0x23,0xc6,0x69,0xad,0x76,0xd0,0x87,0xf8,0x45,0x4f,0xc5,0x43,
+  0x8c,0x88,0xbd,0x9d,0xc3,0xdb,0x88,0xfc,0x21,0xdb,0x13,0x51,0x64,0xbd,0x6c,0x7b,
+  0x70,0x5c,0x5f,0x48,0x88,0x68,0x88,0x5f,0x42,0xd7,0xb4,0xcb,0x75,0x58,0x3d,0x24,
+  0xf2,0x87,0x41,0xce,0x4f,0x79,0xac,0x75,0x50,0x18,0xbd,0x16,0x7e,0x6d,0x12,0x6a,
+  0x43,0x0b,0xbf,0x2c,0xfe,0xb5,0x56,0x18,0xaf,0xdb,0xef,0xfc,0x63,0x4c,0x2d,0xcf,
+  0xf9,0x17,0x38,0xfc,0x6b,0x2d,0x1a,0x37,0xae,0xb6,0xe3,0x43,0xc4,0x2f,0xd2,0x26,
+  0x86,0xec,0x95,0xac,0xb1,0x0f,0x41,0x2b,0x78,0xb3,0xf9,0x57,0x61,0x07,0x30,0xb5,
+  0x3c,0x97,0x1d,0x7e,0x81,0xae,0x29,0x37,0x41,0x06,0xc9,0x83,0x84,0xef,0xfa,0xf9,
+  0x42,0xf8,0xba,0x49,0xf8,0x35,0x8e,0x7f,0x89,0xb9,0x60,0xf8,0x75,0x60,0x22,0x2f,
+  0x50,0x0e,0xc4,0x2d,0xfe,0xc5,0xdb,0x20,0x7e,0x11,0xa6,0x24,0xf4,0xc5,0xc3,0x36,
+  0xbf,0xf0,0x0f,0x28,0x6f,0x91,0x1a,0x81,0x5f,0xfc,0x23,0xf4,0xf3,0x36,0x7e,0x11,
+  0x27,0x91,0x68,0xf1,0x2f,0xe1,0xc7,0x14,0x45,0x6b,0xc9,0xf0,0xaf,0x95,0x8b,0x1e,
+  0x41,0x43,0xdb,0x24,0xae,0x44,0x44,0x1b,0x86,0x5f,0x6c,0x7f,0x93,0x67,0x0d,0x87,
+  0xda,0x9f,0x14,0x6f,0xa4,0x72,0xcf,0xa2,0x14,0xfc,0x04,0x2e,0x47,0xfe,0x25,0xf2,
+  0x1b,0xa9,0x7c,0xd1,0xd5,0x02,0xab,0xcf,0x8b,0x38,0x36,0x9d,0x17,0x82,0xbd,0x4f,
+  0x2d,0xfe,0x25,0x21,0x5a,0x49,0xfc,0x4f,0x03,0xd2,0x59,0xa9,0xfa,0x9b,0x68,0x3c,
+  0x2e,0xbd,0x06,0x1c,0x97,0x2d,0xbe,0xbc,0xda,0xc2,0xaf,0xcb,0x81,0x58,0x40,0x46,
+  0x89,0xde,0xda,0x01,0x01,0x66,0xec,0xb7,0xf5,0xf3,0x99,0xfc,0x21,0x1a,0x15,0x62,
+  0x93,0x57,0x0b,0xf0,0x9c,0xe7,0xeb,0x62,0xbe,0x4a,0x6f,0x17,0xf8,0xb5,0x3e,0xc3,
+  0x3d,0xfd,0x15,0xca,0x2c,0xc4,0xa6,0x97,0xe3,0xe1,0xfd,0xe2,0x19,0x26,0x8a,0x77,
+  0x7a,0x59,0x7f,0x3c,0x02,0xb6,0x18,0xb4,0xc9,0xed,0xf8,0x7c,0x78,0x7f,0x06,0x85,
+  0x2e,0x6e,0x85,0x93,0x3f,0x74,0xe6,0x82,0x89,0xed,0xe1,0x45,0x76,0xe5,0x6d,0x8b,
+  0x5b,0x39,0xfb,0xbf,0x8a,0x74,0xc5,0x9e,0x53,0x6e,0x60,0x9f,0x33,0xfb,0xbf,0x40,
+  0xec,0xff,0x8a,0x30,0xd8,0xaa,0x61,0xb4,0x6b,0x50,0xeb,0xa2,0xec,0x4a,0xb8,0x57,
+  0x3c,0xe7,0x4a,0x57,0xa3,0xc4,0xde,0xb1,0x29,0xe3,0x38,0xfe,0x1e,0x1a,0x34,0x6f,
+  0x0c,0xf9,0x7b,0xed,0xf8,0xf0,0x12,0xfe,0x3e,0x77,0xde,0x97,0xf5,0x3e,0xd3,0xa7,
+  0x55,0x66,0xe8,0x29,0x83,0xaf,0xd3,0x4a,0xf5,0x12,0xf2,0x2a,0x43,0xab,0x7f,0x92,
+  0xa7,0x2b,0x7f,0x68,0x67,0xb0,0x25,0x1f,0x4f,0x0a,0xfc,0x92,0x0f,0x8a,0xf5,0xa5,
+  0x4e,0x6b,0xcf,0x4a,0x59,0x48,0x97,0xf5,0x31,0x83,0x71,0xfc,0x2c,0xfe,0x65,0x94,
+  0x7c,0x6e,0xd7,0x53,0x3e,0xe5,0x8e,0xd1,0x8b,0x8e,0x51,0x7f,0x1a,0x1f,0x00,0xfa,
+  0xc3,0x63,0x96,0x26,0xf0,0xd2,0x76,0xd1,0x8d,0x85,0x91,0x23,0x48,0xc4,0xaa,0x19,
+  0x11,0x7b,0x17,0xf6,0x3c,0x85,0x3e,0x61,0x21,0xf9,0x58,0xb4,0x01,0xba,0x25,0xd3,
+  0xd5,0x7d,0x1a,0xdb,0x08,0x16,0x79,0xd7,0xf8,0x57,0x9d,0x03,0xd9,0x4e,0x2b,0x7f,
+  0xa8,0xf4,0x65,0xa7,0x74,0xaa,0x33,0x44,0xec,0x91,0x10,0xfc,0x46,0xb1,0xd6,0xfb,
+  0x4e,0xde,0x67,0xcf,0x30,0x07,0x29,0x46,0xc4,0xa4,0x51,0xec,0x33,0xcf,0x47,0x3d,
+  0x09,0xd6,0x5a,0x1e,0xb2,0x6a,0x25,0x56,0xac,0xfe,0xa0,0xd0,0x0c,0x58,0xde,0x4f,
+  0xe0,0x17,0x7c,0xce,0x5d,0x4a,0x81,0x90,0x2f,0xd6,0xdb,0xf5,0x2f,0x46,0xc4,0xe4,
+  0xf4,0x72,0x2b,0x3e,0x5c,0x99,0x71,0x83,0x1f,0x4b,0xd5,0xa2,0xb6,0x85,0x2f,0x52,
+  0x0f,0x02,0xd9,0x49,0x7b,0xff,0xd7,0xf2,0xf1,0x3e,0xb3,0x94,0x19,0xcf,0x72,0x32,
+  0x42,0xd2,0x12,0x9f,0x0b,0x15,0xf2,0xd9,0xb8,0xfa,0x59,0xda,0x90,0xee,0x50,0x56,
+  0x9a,0xee,0x05,0x6c,0x4e,0xb5,0x60,0x9f,0x3b,0xec,0xb7,0xe6,0x1d,0xd4,0xe5,0x62,
+  0x2e,0x4e,0xb7,0x0d,0xc5,0xd0,0x8f,0x1d,0xf3,0x3e,0x45,0xce,0xc3,0xd9,0x15,0x78,
+  0x65,0xaf,0x9c,0xce,0xb5,0xf5,0x1b,0xac,0xab,0x29,0xce,0x19,0x3f,0x23,0xf5,0x47,
+  0x98,0x3f,0xdc,0x75,0x4e,0xaf,0x4f,0x15,0xec,0x2d,0x72,0xf0,0xeb,0xd7,0xf0,0x0e,
+  0xce,0x57,0xfe,0x88,0xa7,0x8e,0x1c,0x5e,0x36,0xcf,0xfb,0xe0,0xb3,0x2c,0x7f,0x48,
+  0xeb,0xb3,0xf2,0x87,0x66,0xe9,0xa7,0xda,0xf3,0xb4,0x86,0x65,0x0b,0xab,0xbd,0xeb,
+  0x43,0x7a,0xbe,0xda,0x55,0xf4,0x6b,0x51,0x11,0x43,0xfc,0x12,0xfa,0xf9,0x54,0xe3,
+  0x61,0xe5,0x21,0xc2,0x5f,0xbf,0x0d,0xb0,0x0d,0x2a,0x4c,0x77,0x96,0xc3,0x7f,0xdf,
+  0xd6,0xcf,0x3b,0xfc,0x2b,0xa8,0x26,0x20,0x07,0x2a,0x93,0x11,0xbc,0x22,0x15,0x30,
+  0x34,0xb7,0xb4,0xfa,0x80,0xf8,0xf5,0x0e,0x86,0x10,0xf9,0x21,0xf4,0xcf,0x83,0xf0,
+  0xb9,0xb6,0x38,0xa3,0xbb,0x18,0x9f,0x3f,0xbc,0x06,0xe7,0x54,0x1a,0x85,0x77,0xe0,
+  0x6a,0xea,0x63,0xc6,0xf8,0xfc,0xe1,0x6d,0x9c,0x7f,0xfd,0xc4,0xf4,0x76,0x31,0x7a,
+  0x82,0xbc,0x3b,0xdf,0xbe,0xcf,0xc6,0x49,0xf9,0x43,0xf5,0xa9,0xd6,0xa3,0x8c,0x88,
+  0x51,0x95,0xd5,0xc8,0x26,0xe9,0x37,0x34,0xce,0xf1,0x6b,0xc9,0x51,0xf4,0x24,0x95,
+  0xe0,0x61,0xbb,0x5c,0xac,0xa8,0x69,0x58,0xc4,0xfc,0xc3,0xda,0x77,0x38,0x6c,0xe5,
+  0xdd,0x47,0x8e,0x97,0x3d,0x43,0x67,0x2d,0x6f,0x65,0x42,0xc4,0xab,0x12,0x55,0x3c,
+  0x7f,0x68,0xeb,0xe7,0x6f,0xa6,0xa7,0x93,0xc1,0xc1,0x7c,0xc4,0x2f,0xf3,0x24,0x2c,
+  0x1c,0xfc,0xcb,0x85,0xc8,0x4f,0x4f,0x27,0x6a,0x45,0xfe,0x50,0x13,0x6b,0x67,0x37,
+  0xd3,0x6f,0xf4,0x55,0xef,0xc1,0xae,0x8e,0x4a,0x3f,0x34,0xc4,0xfe,0x2f,0x96,0x3f,
+  0xdc,0x93,0xa5,0xdf,0x50,0x7e,0xa4,0xd4,0xf0,0x1c,0x23,0xa7,0x03,0xf9,0xc9,0x22,
+  0x5e,0x83,0xc6,0x2b,0x77,0xf7,0x8a,0xe7,0x93,0x72,0xf4,0x1b,0x2c,0x6d,0x08,0x7a,
+  0x5f,0x47,0xb3,0xec,0x5c,0x79,0x3d,0x5b,0xbf,0x31,0x8b,0x63,0x2e,0xcb,0xc9,0xbc,
+  0xbf,0x62,0xb5,0xd8,0x73,0xcd,0x80,0x2c,0xe5,0xe8,0x37,0x34,0x31,0x83,0x39,0x87,
+  0xf1,0x9f,0x97,0xa7,0x3b,0x78,0x7d,0x59,0xcc,0xe9,0xdb,0x90,0x55,0xff,0xaa,0x41,
+  0xfc,0x2a,0x4a,0xc1,0x17,0xc3,0x7c,0xff,0x97,0x5d,0x11,0x93,0xbf,0xb0,0xf0,0x54,
+  0x4a,0x64,0x60,0xeb,0x0c,0xf6,0xe8,0x66,0x7b,0xff,0xf2,0xe5,0x59,0xfa,0x79,0x2b,
+  0xe6,0x7f,0x38,0xf7,0xf7,0x7c,0x3b,0x92,0x37,0x0b,0xc8,0x7a,0x45,0x7f,0x1c,0xfe,
+  0xf5,0x33,0xc2,0x38,0xda,0x76,0xa3,0x52,0x38,0xea,0xba,0x2c,0xfe,0xb5,0x50,0xca,
+  0xf0,0x2f,0xfd,0x61,0xe0,0x7b,0xd2,0x9d,0x64,0xda,0x11,0xb1,0x5f,0xc6,0xd6,0x6f,
+  0x1c,0x62,0xf8,0xf5,0xb4,0x5e,0x16,0x55,0x33,0x89,0xc4,0x71,0xfa,0x79,0xde,0x67,
+  0xbc,0x73,0xea,0x96,0x79,0x36,0xff,0x1a,0x97,0x3f,0x2c,0xb1,0xf9,0x17,0x76,0xf5,
+  0x2d,0x26,0x3b,0x14,0x7d,0xae,0x61,0x84,0xc5,0xe2,0x5f,0x5b,0x1d,0xfd,0x06,0x42,
+  0xdb,0x81,0xca,0xf0,0xe2,0x9b,0x37,0x65,0xc6,0xe5,0xe8,0x37,0x62,0x36,0x6c,0xa5,
+  0x61,0x7d,0x0c,0xdf,0xc3,0xd6,0x0c,0x90,0x1d,0x11,0x71,0x0b,0xd7,0x6f,0x10,0x81,
+  0xb9,0xa4,0x45,0xd5,0xc7,0xf5,0xf9,0x75,0x89,0xb7,0xb1,0xf4,0x1b,0x36,0x64,0xb3,
+  0xfd,0x05,0x81,0x81,0x4c,0xee,0x94,0xb7,0xb1,0xf9,0x17,0xc7,0xa6,0x03,0x66,0xe0,
+  0x07,0xd9,0xcf,0x39,0xa3,0xdf,0x28,0xb5,0xdb,0x90,0x93,0xfe,0x17,0x8d,0xaa,0xac,
+  0x36,0xaf,0x4f,0xd0,0x6f,0xb4,0x20,0xed,0x3a,0x66,0x24,0xb5,0x20,0x95,0x18,0x90,
+  0x4d,0x67,0xcf,0xa7,0xd7,0xc9,0x1f,0x2a,0x3c,0x7f,0x38,0x80,0xfc,0x6b,0xbd,0x12,
+  0xc8,0xf0,0x2f,0xcf,0x44,0xfd,0x86,0xa9,0x56,0xb4,0x4a,0xe1,0x87,0x90,0x83,0x48,
+  0x0e,0x90,0x8d,0xd3,0x6f,0xf0,0x7c,0x5d,0xd4,0x5d,0xa8,0xae,0x2b,0x2b,0x4b,0xe5,
+  0xad,0xce,0x24,0xc6,0xd3,0x62,0x4e,0x2d,0xfd,0x7c,0xda,0x7b,0x87,0x7c,0x19,0xdc,
+  0x9a,0x48,0x0e,0x56,0x8d,0x78,0xac,0x8a,0xd8,0x6a,0xf9,0x7d,0xb1,0x07,0x41,0x15,
+  0x5a,0x08,0xd3,0x07,0xb2,0x09,0xe7,0x6e,0xa9,0xfb,0x5f,0x05,0x4f,0x89,0x84,0x9b,
+  0x99,0x8b,0xf8,0x65,0xe5,0x7f,0xae,0x7b,0xb1,0x71,0xac,0x15,0xf9,0x57,0x54,0xf6,
+  0xc3,0x7b,0xe9,0x79,0xa3,0x1b,0xce,0xb7,0x59,0x15,0xb1,0x11,0x47,0x3f,0x7f,0xe9,
+  0x63,0x74,0x5f,0x22,0x98,0x9e,0x52,0x20,0x47,0x3a,0x5e,0xdd,0xaa,0x7f,0x52,0x70,
+  0x9f,0x5d,0x38,0xb8,0xcf,0xd6,0xcf,0xab,0x4c,0xbf,0x81,0xfc,0xcb,0x13,0x21,0x9a,
+  0xf9,0x53,0xa5,0x2c,0x25,0xaf,0x62,0x40,0x06,0xdf,0x4b,0x79,0x56,0xd9,0xfc,0x2b,
+  0xc6,0xf4,0x1b,0x8c,0x69,0x82,0xdb,0x80,0xb6,0x25,0x89,0xbe,0x6c,0x9f,0x99,0xd1,
+  0xcf,0x8b,0xd5,0x0d,0x32,0xc0,0x7b,0x74,0xef,0x70,0xd5,0x30,0x62,0x2e,0xf3,0x6c,
+  0xbe,0x64,0xf9,0x47,0x62,0xec,0x71,0x18,0x92,0xb8,0x67,0x63,0xeb,0xeb,0xb4,0x52,
+  0xd7,0x6b,0xf9,0x3a,0xd6,0xc6,0xce,0x1f,0x26,0x34,0x0b,0xad,0xcc,0xa2,0x66,0xf5,
+  0x1d,0x08,0x99,0xc1,0x61,0xb9,0x16,0xde,0x83,0x39,0x8c,0x88,0xa5,0xc6,0xe9,0x37,
+  0x4c,0xcf,0x86,0x29,0x77,0x6b,0x4c,0x52,0xa8,0xb1,0x3d,0x47,0x96,0x3f,0x1c,0x74,
+  0xf8,0x97,0xf2,0xbc,0x54,0xdd,0xe3,0xe9,0xf0,0xdf,0x15,0x7a,0x04,0xf9,0x97,0x14,
+  0x82,0x20,0x4f,0xa6,0xc9,0x19,0xfe,0x55,0x8c,0xe1,0xee,0xa2,0xe0,0x6f,0x3c,0xd0,
+  0x6a,0xb0,0x23,0x2c,0x0e,0x5c,0xb6,0xc0,0xbd,0x84,0xee,0x35,0x56,0xa6,0x3c,0x73,
+  0x89,0xa5,0x9f,0xa7,0xf9,0x2b,0x53,0xe7,0x62,0xd5,0x6f,0xf9,0xda,0xe4,0xe5,0x03,
+  0xef,0xe9,0xf3,0x0e,0x7b,0x87,0xdb,0x82,0xf4,0x9d,0x15,0xc8,0xc8,0x92,0xb2,0xcd,
+  0xbf,0xfe,0x79,0xa8,0xff,0x5c,0xac,0xfe,0xf0,0xd2,0xd6,0xc2,0x74,0xfc,0x5c,0x71,
+  0xdd,0xe1,0x9b,0xba,0xe4,0x17,0x8c,0x73,0x65,0x75,0x7d,0x8c,0x7f,0x59,0xd8,0xe4,
+  0x1a,0xad,0x3c,0xa2,0xcf,0x8d,0x79,0xb6,0x62,0xbc,0x31,0x0a,0x75,0xe9,0xa5,0x23,
+  0xe5,0x0b,0x00,0x6f,0x98,0x2e,0x40,0xfe,0x45,0x2d,0xfc,0x1a,0x62,0xdb,0x45,0x6d,
+  0xcc,0x9d,0xc9,0x01,0x08,0xfe,0xa7,0x31,0x3b,0x3d,0xa5,0xdb,0xae,0x95,0xa4,0x5c,
+  0x1b,0x80,0x6a,0xfa,0x38,0x9e,0x12,0x84,0x36,0x7f,0x0c,0x81,0x2c,0x72,0x4a,0xac,
+  0x2f,0x53,0xd9,0x4d,0x3a,0x0d,0x64,0x37,0x7b,0xd8,0x7d,0x4c,0x7c,0x2c,0x21,0x77,
+  0x10,0x7e,0x29,0xb0,0x7b,0x44,0xbc,0xf3,0x52,0xc9,0x60,0xef,0x41,0x8c,0xaf,0x3d,
+  0xdd,0x6c,0x0a,0x4c,0x0e,0x5b,0x05,0x06,0xdb,0xc8,0x3c,0x1d,0xc7,0x65,0xf0,0x36,
+  0x69,0xe9,0x49,0x38,0xcf,0x8e,0xdd,0x18,0x61,0x21,0x84,0xbd,0x97,0x5c,0x6c,0x64,
+  0x6e,0x18,0x11,0x6d,0x0c,0xad,0x83,0xa4,0x0c,0x76,0xec,0x86,0x27,0x08,0x1f,0x1b,
+  0xfc,0x20,0x8e,0x21,0xbe,0x21,0x1a,0x6f,0xf8,0x1b,0xd1,0xe7,0x63,0xae,0x85,0xd0,
+  0x09,0x0b,0x58,0xb6,0xd0,0xd9,0xd4,0x30,0x04,0x1b,0x69,0x80,0x15,0x2e,0x3f,0xe7,
+  0x8f,0x19,0x4c,0x88,0x92,0x0e,0x8c,0x88,0x54,0xb6,0xac,0x76,0x28,0x95,0x22,0x87,
+  0xd6,0xa6,0x55,0x70,0xfc,0x12,0x79,0xa4,0x11,0xed,0x16,0xf2,0x00,0xbd,0x82,0x4b,
+  0xd0,0x0d,0x91,0x36,0x24,0xc7,0xa5,0x75,0xfd,0x33,0x18,0x16,0x8c,0x52,0x7e,0x9f,
+  0xa8,0x1a,0x25,0xbd,0xf8,0xda,0x78,0xbb,0x65,0x24,0x62,0x04,0xe3,0xba,0x1a,0x96,
+  0xcf,0x4c,0x3c,0x65,0x7a,0xae,0x71,0xf8,0x57,0x49,0x37,0x8e,0xa2,0xce,0xbc,0xe2,
+  0xa4,0x3c,0xaa,0x8d,0xc1,0xe5,0x7d,0x9e,0x93,0x3c,0x2f,0xca,0x8b,0xb6,0x16,0xff,
+  0x52,0x95,0xdd,0xea,0x01,0xb6,0x0b,0x20,0x59,0x54,0xad,0x1c,0xa2,0x4c,0x26,0x8a,
+  0x40,0x7f,0xd4,0xe0,0xe3,0x3a,0x28,0xd6,0x69,0xaa,0xf4,0xb1,0xd6,0x35,0x7c,0x9b,
+  0x27,0x99,0xaa,0xae,0xb3,0x0c,0x58,0xa7,0x96,0xb1,0xf5,0x7e,0xca,0xca,0x5d,0x60,
+  0x34,0xbd,0x96,0x96,0x0d,0x5b,0xb2,0xf9,0x32,0x4b,0x3f,0x9f,0xe4,0x9c,0xd1,0x5a,
+  0x5f,0x83,0xca,0x03,0x46,0x1b,0xb2,0xd1,0xca,0x85,0x6e,0xaf,0xdc,0x66,0x26,0xcc,
+  0xca,0x90,0xbb,0x20,0xc2,0x94,0xb1,0x1c,0xbf,0x44,0x9b,0x92,0x2f,0xe0,0x88,0x81,
+  0xb0,0xf5,0xa4,0x5c,0x09,0x47,0x68,0x18,0x7d,0x94,0xcc,0xf6,0x7f,0x71,0x21,0x87,
+  0xf5,0x5d,0x51,0x89,0xea,0x23,0xba,0x4d,0xbb,0x34,0xcb,0x18,0xb6,0xeb,0x5f,0x62,
+  0x5c,0x88,0x5f,0x3d,0xd0,0xc5,0x60,0xab,0x02,0xce,0xaa,0xac,0xfe,0xd5,0x20,0x76,
+  0xda,0x8e,0xc3,0x2f,0x85,0x6d,0x5b,0x56,0xb7,0x90,0x19,0xf0,0x6c,0xa4,0xba,0xc9,
+  0xb3,0x25,0xf0,0x3b,0xf6,0x66,0x72,0xfc,0x12,0x75,0x61,0xa6,0x3f,0xbc,0x5f,0x0d,
+  0x44,0x54,0xad,0xb5,0x42,0x7f,0x56,0xad,0x8e,0x78,0xe2,0xad,0x7d,0x3a,0x5e,0xc9,
+  0xe2,0x5f,0x88,0x5f,0xb4,0x45,0xd7,0x99,0xda,0xd0,0x29,0x7b,0x21,0x28,0xe8,0x42,
+  0xbf,0x21,0xbe,0x6b,0x24,0x7f,0x99,0x61,0x36,0x85,0x8a,0xbd,0x2e,0x8f,0x64,0x0c,
+  0x7f,0xb3,0xb6,0x78,0xa3,0x4b,0xee,0x69,0x34,0x9b,0xba,0x58,0x9f,0x3f,0x17,0x58,
+  0xd9,0x51,0xf2,0x66,0xe4,0xbc,0x56,0x6f,0xcc,0x61,0xf8,0xc5,0x8c,0x8d,0x0c,0xa4,
+  0xce,0x6a,0x8c,0x21,0x16,0xbd,0x6f,0xe3,0x17,0xc2,0x31,0x0d,0x1b,0xca,0x16,0x79,
+  0x06,0x1b,0x4e,0x53,0x70,0x8b,0xfc,0x3b,0xa6,0x3f,0x64,0xe3,0xda,0x4e,0x2c,0xfc,
+  0xea,0x31,0x3b,0xf4,0x80,0xaa,0x22,0xed,0x82,0x0e,0x9d,0xe9,0x0f,0x03,0x69,0x78,
+  0xca,0xd8,0x9e,0xc5,0xbf,0x10,0xbf,0xe8,0x9a,0x68,0x59,0x83,0xfa,0x3a,0x29,0x5e,
+  0xbb,0x26,0x5a,0x6e,0xa8,0xb7,0x90,0x37,0xe9,0xd3,0x31,0xd6,0xe7,0x9c,0x9f,0x89,
+  0x36,0x5b,0x95,0x9d,0xc6,0x9a,0xd8,0x36,0xa3,0xf2,0x75,0x77,0x31,0x3c,0x40,0xbf,
+  0xce,0x37,0x32,0xd3,0x7f,0x15,0xb9,0xd3,0x4f,0x45,0x0c,0x89,0xf8,0x45,0x78,0x78,
+  0xa0,0xe1,0x73,0x3e,0xa0,0x86,0x0c,0x95,0x27,0x6c,0x45,0x9e,0x76,0x97,0x3d,0x5f,
+  0x3f,0x87,0xb3,0x54,0xec,0xff,0xb2,0xd3,0x86,0x8e,0xf1,0x3a,0xb5,0xe6,0x8b,0x76,
+  0xb0,0x6d,0xa7,0x1b,0xd8,0x16,0xe0,0x94,0xd1,0x05,0x5e,0x9a,0xab,0x63,0x64,0xc7,
+  0xf7,0x7f,0xf5,0x8a,0x36,0x2c,0x7f,0xb8,0x9e,0xcb,0xe6,0x73,0x06,0xc9,0x7a,0x1a,
+  0x68,0xe1,0xf8,0xf5,0x6b,0xba,0x00,0x89,0x98,0xdc,0x5a,0x21,0xe6,0x42,0xb9,0x09,
+  0xda,0x68,0x65,0x1a,0x97,0xd5,0x11,0x56,0xf6,0x62,0x5c,0xa6,0x00,0x5a,0x5b,0x99,
+  0x27,0xb1,0x63,0x75,0xaa,0xbd,0x5b,0x9c,0x6b,0xcc,0xfa,0x0d,0xbe,0xc6,0xff,0xa1,
+  0xe1,0x6b,0xdc,0xaf,0xfe,0x98,0x5c,0x2e,0xfd,0x3c,0x8f,0x17,0x95,0x52,0xdc,0x65,
+  0x42,0x47,0xc7,0x77,0xc8,0x11,0xfa,0x7c,0x22,0xb8,0x22,0xf0,0x05,0xb9,0x99,0x96,
+  0x27,0x82,0x83,0xee,0x1a,0xf2,0x6a,0xeb,0x5c,0xce,0xbf,0x78,0x77,0x38,0x7e,0xb1,
+  0xca,0xec,0xfd,0x59,0x21,0xd6,0x20,0x06,0xc0,0xdc,0xc9,0xb4,0xb6,0x0b,0xbf,0xa1,
+  0x3c,0x49,0x5f,0x6b,0x99,0xb7,0xfc,0x86,0x67,0xe5,0x0f,0xe0,0x3c,0x5d,0xb0,0xdc,
+  0xbb,0xd5,0xb3,0x00,0x46,0xe2,0x61,0x16,0xcf,0xf7,0x6f,0xe7,0x6d,0x9e,0x2c,0xfd,
+  0x99,0xb9,0x06,0xca,0x57,0xe2,0x92,0xf9,0x37,0xf3,0x69,0x28,0x5b,0xa1,0x5e,0x46,
+  0x2e,0x89,0x77,0x27,0xca,0x4e,0x78,0x6a,0xc8,0x47,0xe2,0x19,0x6a,0xb0,0x35,0xb4,
+  0x05,0xca,0xd5,0x47,0xee,0x6a,0xed,0xcf,0x7b,0x4a,0x2d,0x83,0xbc,0x5e,0xd2,0x14,
+  0x7b,0x9a,0x96,0xb1,0xcd,0x6b,0x03,0x36,0x7e,0x75,0x40,0x7c,0x58,0xd7,0x0b,0x77,
+  0xe1,0x8a,0xeb,0xc6,0x67,0x26,0x51,0x02,0xc5,0x7b,0x44,0x6e,0xa7,0x5f,0xb4,0xe9,
+  0x2e,0xf9,0x14,0xde,0x30,0xba,0xde,0xf7,0x6d,0x65,0xdb,0x60,0x7b,0xc2,0xe6,0xaf,
+  0x92,0x9e,0x95,0x85,0xcf,0x61,0x40,0x8e,0xf1,0xea,0x07,0xd6,0xba,0x90,0x76,0x13,
+  0x96,0x6b,0xba,0x39,0x9e,0xd9,0xbf,0xbc,0x1b,0x4e,0xf1,0x58,0x3d,0xd7,0xd2,0x12,
+  0x27,0xb4,0x47,0x71,0x55,0xee,0xa5,0xbe,0x9e,0xdc,0x85,0x70,0x41,0xbd,0x8a,0xfa,
+  0xd2,0xf2,0x42,0x5b,0x7f,0x98,0x16,0x3e,0x73,0x27,0xe2,0x17,0x9b,0x2f,0x0f,0x95,
+  0x59,0x98,0x11,0x16,0x7a,0x9b,0xe7,0xd1,0x43,0xde,0x98,0x24,0x67,0x96,0x8b,0xb9,
+  0xc0,0x39,0x65,0xa1,0x91,0x9b,0x95,0x95,0x9f,0x80,0xd9,0xc6,0x8d,0x68,0x48,0xbb,
+  0x78,0x15,0xc6,0x9f,0x16,0xf3,0xe5,0x2e,0x56,0xe9,0xfd,0xa0,0xdf,0xe0,0xb9,0xc4,
+  0x7d,0x5d,0x7c,0x0f,0x54,0xde,0xe1,0x29,0x9e,0xad,0x24,0x92,0xa1,0x8a,0x14,0x46,
+  0xc2,0xf6,0x9c,0xe6,0x47,0x13,0x29,0x29,0xac,0x16,0xe0,0x3b,0x4f,0xd3,0xb0,0x50,
+  0xf5,0xb5,0xb6,0xe9,0x70,0x36,0x16,0x4e,0xf9,0xf6,0xc9,0x56,0x2c,0x9a,0xd8,0x34,
+  0x42,0x46,0x99,0x97,0x78,0x39,0x37,0x69,0x8c,0xc2,0xbc,0x52,0x9f,0x81,0x7f,0x3a,
+  0xbf,0xac,0xfe,0x95,0x8d,0xa7,0x8b,0xd2,0x15,0x16,0x7e,0xf1,0xe8,0x22,0x96,0xbf,
+  0x55,0x0e,0x08,0xbe,0xcc,0x62,0xfe,0x43,0x2c,0xa3,0x88,0xfc,0xcb,0x15,0x13,0x3e,
+  0x9c,0xa7,0x0d,0x63,0x6a,0x77,0x20,0xa1,0x74,0x42,0x75,0xaf,0x3a,0x4c,0x2e,0x60,
+  0x9b,0x6a,0x64,0x64,0x72,0x52,0xf0,0xd3,0x14,0xcf,0x1f,0x72,0x6d,0x58,0x0e,0xec,
+  0xa8,0x0c,0xa6,0xf2,0x42,0x7e,0x8b,0x91,0x85,0xc8,0x29,0x89,0xb7,0xb1,0xf2,0x87,
+  0x51,0x75,0xab,0xff,0xe7,0x78,0x9f,0x20,0x3b,0xc6,0x61,0x48,0xec,0xc0,0x4a,0x92,
+  0xa4,0xa5,0x3b,0xe5,0xf5,0x9d,0xda,0x58,0xfe,0x54,0x39,0x47,0xf9,0x58,0xaa,0xeb,
+  0xf1,0x32,0xdc,0xb1,0xde,0x31,0x2b,0xff,0x9c,0x2e,0xe4,0xe7,0x47,0xa5,0x59,0x4c,
+  0xab,0x7f,0xc6,0x05,0x0f,0xf2,0x50,0x60,0x3c,0xff,0x6a,0xd2,0x76,0x63,0x94,0x52,
+  0x17,0x29,0x88,0x7b,0x2a,0x08,0x23,0x74,0x1b,0x11,0xc8,0x88,0x75,0x9f,0xdf,0xd8,
+  0x98,0x1b,0xd4,0xb0,0x3f,0x23,0x18,0xa2,0xcf,0x0c,0xb1,0x6e,0xf8,0x86,0xc9,0xb4,
+  0x38,0x1a,0x1f,0xf2,0xfd,0xd4,0x7c,0x61,0x98,0x0a,0x8f,0x06,0x9b,0xdd,0xa5,0x24,
+  0x8f,0x17,0x9a,0x71,0x38,0xaf,0x81,0x95,0x55,0x1b,0x11,0xf9,0x79,0x16,0x75,0x22,
+  0x6c,0xad,0x50,0xcf,0xaf,0xbd,0x8c,0xae,0x8b,0x33,0x21,0x7d,0xc1,0x71,0x63,0x1d,
+  0xc6,0x63,0xf2,0xea,0x9c,0x51,0xab,0xfe,0x55,0x5a,0x00,0x7b,0x93,0xb5,0x2b,0x0a,
+  0x2e,0x6b,0xa8,0x86,0x37,0xa0,0x76,0xd0,0xc3,0x88,0xd8,0xcb,0x49,0xa6,0x9f,0xcf,
+  0xb5,0xeb,0x5f,0x53,0xd9,0xbe,0xec,0x5a,0xc3,0x17,0xc2,0x65,0x25,0xca,0x79,0x6d,
+  0xb5,0x7c,0xff,0x32,0xc7,0x2f,0x3e,0x2e,0xd5,0x75,0x84,0x3d,0x0d,0xc3,0xa7,0x7a,
+  0x2a,0x70,0x0a,0xc2,0xac,0x06,0x1d,0x34,0x0f,0x01,0x9f,0x38,0x2b,0x1f,0x95,0x92,
+  0x78,0xfe,0xd0,0xf0,0x18,0xe4,0x29,0x7e,0x5e,0x41,0xde,0x3d,0xc4,0x6b,0xfc,0x54,
+  0x68,0x77,0xb3,0xf4,0xf3,0xd8,0xc3,0x98,0x27,0x45,0x2e,0xe1,0xf8,0x85,0xa1,0xe3,
+  0x74,0xfa,0x53,0x04,0xdf,0xbc,0xd5,0x11,0x5b,0x3f,0x5f,0x7c,0x58,0x8c,0x34,0x8f,
+  0xac,0x41,0x23,0xc0,0xb5,0x61,0x84,0x3d,0x84,0x59,0x99,0xfc,0xa1,0xb4,0x0b,0xc3,
+  0xe4,0x5a,0x5c,0x0e,0xb9,0x0b,0x23,0x02,0xb6,0xf8,0xfe,0xe5,0x6a,0x9a,0x97,0xd1,
+  0x6f,0x68,0xec,0xfc,0xa8,0xba,0x62,0xdf,0x06,0x5c,0x29,0x23,0xf0,0x22,0xba,0x65,
+  0x0f,0xdf,0xe5,0xa7,0x15,0x8c,0xd3,0xcf,0x63,0x84,0x1f,0x43,0xfc,0xfa,0x80,0x1e,
+  0x40,0x0a,0x73,0x38,0xfe,0xfd,0xe5,0xd1,0x03,0x62,0x53,0xf0,0xf8,0xfa,0x57,0x34,
+  0xff,0x5f,0xc8,0x07,0xf6,0xb6,0xe5,0x5c,0x5c,0x29,0xd5,0xcd,0x93,0xea,0x5f,0x8d,
+  0x6a,0xd2,0xdf,0x07,0xf7,0x4b,0xec,0x20,0x29,0x77,0x85,0xf4,0xf0,0x44,0xfd,0x46,
+  0xa9,0xa5,0x3f,0x44,0xd8,0x42,0xa3,0xd2,0x4f,0x94,0xd6,0x4d,0x30,0x4e,0xbf,0x31,
+  0x2d,0x66,0xe9,0x13,0x8a,0x4e,0x44,0xcc,0x5b,0x6a,0x8a,0x97,0xb8,0x1a,0x90,0x68,
+  0x30,0xa7,0xe7,0xf0,0xaf,0xee,0x69,0x8c,0xdd,0x30,0x6e,0x55,0x78,0xc6,0xde,0xb6,
+  0xcc,0x76,0x7b,0xd5,0x66,0xe9,0x37,0xba,0x4b,0xce,0xd8,0xfc,0xeb,0x07,0x3c,0x41,
+  0xba,0x71,0x73,0xdb,0x99,0xc4,0x01,0x76,0xc5,0x39,0x3f,0xaa,0x14,0x32,0x69,0x43,
+  0x65,0x17,0x13,0x72,0xac,0x25,0x27,0xa0,0xc3,0xe2,0x5f,0x13,0xf5,0xf3,0x64,0xb9,
+  0xde,0xa2,0x32,0x21,0x47,0xab,0xd8,0x73,0xed,0x99,0xa8,0x9f,0x37,0x3d,0xf1,0xc8,
+  0x4e,0xfd,0x09,0x1c,0xb2,0x6c,0xe5,0x4e,0xcd,0x2c,0xfd,0x06,0xf0,0xe7,0xdc,0xe8,
+  0xd3,0xe4,0x46,0xec,0xcf,0xdf,0x09,0x92,0x65,0x65,0x6e,0x07,0xc5,0x3e,0xe8,0x15,
+  0xa2,0x4d,0xcc,0xf7,0xa8,0xbc,0xdc,0x96,0xd0,0xf4,0xd9,0xfc,0xeb,0x6d,0xab,0xfe,
+  0x05,0x8e,0x7e,0xa3,0xcc,0x4a,0x24,0x32,0xfd,0x21,0xd4,0x29,0x3e,0x47,0xbf,0xa1,
+  0x02,0xd7,0xcf,0x6f,0xcf,0xff,0xa4,0x68,0xb5,0xb6,0x5e,0xd0,0xae,0x85,0xd2,0x7a,
+  0x32,0x27,0x91,0xe1,0x5f,0x6a,0x09,0xe7,0x5f,0x46,0xa9,0xa6,0xa9,0x0a,0x7b,0xd9,
+  0xe4,0x10,0xc9,0xc9,0x69,0x53,0xb2,0xf9,0x97,0x2e,0x4d,0x95,0xf6,0xc1,0x9c,0xf4,
+  0xfd,0x3f,0x20,0x77,0xc2,0x3a,0x9d,0x17,0xc2,0x4a,0xf5,0x75,0x42,0xa1,0x64,0xe9,
+  0x37,0x2a,0x4b,0xb9,0x7e,0x23,0x81,0xfc,0x2b,0x1c,0x79,0x95,0xfe,0xe3,0x80,0xaf,
+  0xc6,0x73,0x19,0xbe,0xd8,0x9c,0x7f,0x8d,0xab,0x7f,0xe1,0x32,0x0f,0xc9,0x9f,0xd0,
+  0x73,0x35,0x75,0xfd,0xbe,0x3d,0x9d,0x29,0x3b,0xb7,0x63,0xe9,0xe7,0x63,0x5c,0x3f,
+  0x5f,0x9f,0xf2,0xdd,0x5b,0x5e,0x43,0xdf,0x8b,0xd7,0xbf,0xbf,0xf1,0x59,0x79,0x3a,
+  0x1c,0x8a,0xf3,0x8c,0xa2,0x7d,0x7e,0x14,0x72,0x2b,0x1e,0xa2,0xaf,0x76,0xff,0x0f,
+  0xb6,0xd0,0xd2,0x9e,0x11,0xa2,0x1a,0xbf,0xa0,0x55,0x66,0xc1,0x6a,0x5b,0xbf,0xe1,
+  0x17,0xfa,0xf9,0x76,0x64,0x5b,0xa1,0xc6,0x9f,0x92,0x2a,0xb6,0xd5,0xfa,0x0e,0xd1,
+  0xf9,0x55,0xa4,0xcf,0xce,0xcf,0x6f,0x60,0xf9,0x8d,0xb4,0x67,0x21,0x79,0x40,0xed,
+  0xe4,0xb9,0x53,0x77,0x94,0x55,0x2b,0x0c,0x24,0x62,0x6f,0x8b,0x79,0xdf,0x2e,0x71,
+  0xce,0xd8,0xea,0x83,0xce,0x59,0xec,0x30,0x25,0xe6,0xe2,0x56,0xa0,0xcf,0xfc,0xb1,
+  0xe1,0x73,0xf4,0x1b,0x09,0x6d,0x48,0x39,0x47,0xea,0xe2,0x1b,0x93,0x45,0x1f,0xda,
+  0xc3,0xb9,0x9f,0x9d,0xc2,0xc7,0x36,0x0d,0x0d,0x88,0xf5,0xd5,0x22,0xea,0x5f,0x74,
+  0x49,0xbf,0xdc,0x5c,0xf9,0x1e,0x61,0xb0,0x25,0x2f,0x8c,0x1c,0x85,0x7a,0x3d,0x7f,
+  0xb8,0xc8,0xd2,0xe0,0x59,0xf5,0xaf,0x64,0xd5,0x53,0x97,0xe5,0xa1,0xab,0xe4,0x65,
+  0x94,0x59,0xcc,0x3f,0x2b,0x97,0x65,0xf4,0xf3,0x42,0x7f,0x98,0xb8,0xfe,0x29,0xb2,
+  0x82,0x6f,0x16,0xb3,0xdb,0xb0,0xcd,0x47,0x16,0xff,0x72,0x17,0x7b,0x8d,0xbd,0xb0,
+  0xb2,0xe5,0xe1,0xb0,0xbb,0x32,0x86,0x9c,0xba,0xdf,0x13,0x46,0xe7,0xd9,0x36,0x33,
+  0xd8,0xe4,0x9e,0x6b,0xaf,0x2f,0x76,0x1f,0xec,0x6a,0x7b,0xfe,0x3e,0xb9,0x59,0x3d,
+  0xaa,0xcc,0x33,0x37,0x9e,0x6a,0xab,0x84,0x43,0xa1,0x3a,0xcd,0x9b,0x6c,0x4b,0x8b,
+  0xf5,0xb5,0xbd,0x64,0x34,0xfe,0xd2,0xac,0xfa,0x0e,0xdf,0x9e,0xa2,0x54,0x7c,0x0c,
+  0xa6,0xff,0xc6,0x77,0xaa,0x73,0x84,0x8e,0x85,0xea,0x01,0x39,0xa3,0x73,0xfe,0x86,
+  0xc5,0x8e,0xbb,0x91,0x7f,0x7d,0x82,0xf1,0x3c,0x2f,0x84,0x7d,0x6c,0xe1,0x97,0xa5,
+  0xdf,0x80,0x21,0x51,0xff,0x62,0xdb,0xbe,0x3a,0x69,0x40,0x18,0xe2,0x4a,0x64,0x70,
+  0x92,0xfe,0x90,0x71,0xb4,0x0a,0x41,0xc4,0x76,0xd8,0xf9,0xc3,0xc9,0xfa,0x8d,0x47,
+  0xe8,0xcc,0x71,0x85,0xa7,0x11,0xab,0xee,0x59,0x9c,0xd1,0x0d,0xc2,0x69,0x84,0x7e,
+  0x47,0x4b,0xe3,0x41,0xfc,0x12,0xeb,0xe2,0x04,0x64,0xe9,0x0f,0x3f,0x13,0xf4,0xc4,
+  0x29,0x84,0x8d,0xc4,0x78,0x9b,0x6c,0xfd,0xe1,0x24,0xc3,0xce,0x1f,0x2a,0x41,0xc8,
+  0xca,0xe5,0xd6,0x65,0xf7,0x47,0xee,0xe2,0xbd,0x41,0x7c,0x5f,0x92,0x19,0xd7,0x44,
+  0x21,0xa2,0xa5,0xdf,0x88,0x49,0x59,0x25,0x24,0x91,0x94,0x63,0x46,0xa2,0xea,0x84,
+  0xbc,0x9a,0x58,0xfa,0xf9,0x15,0x50,0xa0,0x59,0xb2,0xc3,0x23,0xe6,0x69,0x2d,0x98,
+  0xc6,0x45,0x74,0x18,0x4e,0x27,0xf8,0x15,0x1b,0xbf,0xfe,0x8f,0x17,0x84,0xde,0xe6,
+  0x24,0x1f,0x4e,0x5d,0x96,0xae,0xf2,0xe4,0x78,0xfd,0x61,0x6d,0xda,0x6b,0x0f,0xc7,
+  0x23,0x0c,0x76,0xa5,0xe1,0x7d,0x47,0xbf,0x21,0x59,0x3b,0x4d,0xde,0x55,0x9c,0x44,
+  0xe2,0x3e,0xb8,0x9a,0x5d,0xc9,0xd6,0x1f,0xb6,0xb3,0xdd,0x5e,0xdf,0x3a,0x6e,0xe9,
+  0x0f,0x23,0xc7,0x8b,0xf7,0xb5,0x7f,0x0f,0xf1,0xcb,0xe6,0xd4,0x2b,0x2c,0x7d,0x94,
+  0x6a,0xe7,0xe7,0xad,0xb1,0x57,0x32,0x20,0x9b,0xa0,0x3f,0x0c,0x5a,0x31,0x6d,0x8b,
+  0xcf,0x36,0xaa,0x26,0xe9,0x0f,0x27,0xd7,0xbf,0x32,0xf8,0xd5,0x31,0x59,0x7f,0x98,
+  0x9b,0xc9,0x1f,0x7e,0x89,0xfe,0x30,0x3b,0x37,0x68,0xe3,0x97,0x32,0x41,0x7f,0x98,
+  0x97,0xd5,0x66,0xbf,0x9d,0x9f,0xcf,0xd6,0x1f,0x92,0x6a,0x6b,0xff,0x97,0x22,0xf0,
+  0x4b,0xcc,0x7b,0xb7,0xba,0xcc,0x18,0xd7,0xd5,0x07,0x58,0x72,0xcf,0xc9,0x1f,0xf2,
+  0xef,0xda,0x3a,0xed,0x4c,0xa6,0xcf,0xe7,0xc9,0xf8,0xe2,0x9d,0x85,0x5f,0x1d,0xec,
+  0xfc,0x28,0x8e,0x5f,0x18,0x6f,0x9c,0x73,0x12,0x77,0xe2,0x4a,0xc0,0xd1,0x1f,0xea,
+  0x16,0x5a,0xe9,0x4e,0x22,0x91,0x74,0x48,0xdc,0x70,0xf6,0x2f,0x0f,0xd0,0x16,0x91,
+  0x3f,0xcc,0xea,0xbc,0x85,0x5f,0x11,0x47,0xbf,0x21,0x3d,0x31,0x5e,0x72,0x19,0x71,
+  0x6a,0x7f,0x8b,0x2d,0x5f,0xb7,0xa5,0x1d,0x0e,0xb8,0x78,0x3d,0xae,0x82,0x91,0x2c,
+  0x81,0x4d,0x16,0x7e,0xad,0xc8,0xe8,0xe7,0x85,0x46,0xd1,0x83,0xc3,0x89,0x8f,0x1b,
+  0x97,0x67,0xbd,0xc5,0xad,0xb4,0xc4,0x97,0xd7,0x34,0x33,0xf5,0x2f,0xe5,0x23,0x06,
+  0x5b,0x3a,0x19,0x54,0xac,0xb4,0xe1,0x88,0xfa,0x9c,0xb8,0x62,0x71,0x22,0x96,0x3f,
+  0x9c,0x37,0x61,0x59,0xa5,0x26,0xe4,0x0f,0xcb,0xa4,0xa9,0xf0,0x8b,0xcc,0x6b,0x5c,
+  0x65,0xca,0xcd,0x4c,0x41,0x2e,0xae,0x38,0xf5,0x2f,0x27,0x5b,0x78,0xdc,0x36,0xde,
+  0xb6,0x8c,0xf2,0x83,0xe2,0xb0,0x58,0xf5,0xd2,0x17,0x8c,0x8c,0x26,0x59,0x18,0x83,
+  0x0e,0x7e,0x39,0xe7,0x1f,0xda,0xd9,0xc2,0x17,0x8d,0xb1,0x38,0x77,0x8c,0x5f,0xc0,
+  0xb9,0xf8,0xb5,0xe9,0xfc,0x6e,0x62,0xe3,0x17,0xd7,0x47,0x61,0x0f,0xbf,0xc0,0x90,
+  0x8f,0x77,0xe3,0x47,0xac,0x3f,0x09,0x5c,0x71,0x3f,0xca,0xb5,0xce,0x8f,0xda,0x6c,
+  0x9d,0x7f,0xe8,0x39,0x49,0xd0,0xe0,0xa5,0x3a,0x74,0x05,0xfb,0x34,0x76,0x52,0x96,
+  0xcd,0xbf,0xfe,0xb6,0x78,0xc8,0xd2,0x47,0xb1,0x94,0x29,0x15,0x63,0xe7,0x19,0x7b,
+  0x08,0x05,0x2c,0xfd,0xfc,0x93,0x25,0x2f,0xc0,0x8f,0xc4,0xae,0xd5,0xdd,0xfc,0x6c,
+  0x0d,0xec,0xea,0xae,0x62,0x46,0xb2,0x2a,0x92,0xc4,0x3a,0xff,0x30,0x0e,0x19,0x17,
+  0x27,0x8d,0x1b,0xd7,0xd2,0xa4,0xfc,0xb8,0x58,0x5f,0x54,0x1b,0xd5,0x8e,0x5a,0x3e,
+  0x53,0x75,0x42,0x7d,0xcb,0xb0,0xea,0x5f,0x3d,0x7c,0xff,0xb2,0xd0,0x1f,0x3a,0x69,
+  0x43,0x78,0x5e,0x12,0xfa,0x84,0x8c,0x7e,0xa3,0x73,0x82,0x66,0x60,0x90,0x1b,0xee,
+  0xa4,0x5d,0x83,0x66,0xfa,0x79,0x11,0xe1,0xb7,0x1e,0x66,0x42,0xc4,0x3e,0xc4,0x2f,
+  0x9c,0x53,0xdd,0x6b,0xe6,0x85,0xed,0xf5,0x45,0xbd,0x2b,0x8d,0x43,0x6c,0x4b,0xf2,
+  0x3e,0xf9,0x13,0x33,0xd3,0x67,0xa3,0xee,0xcd,0x82,0xa7,0x1d,0xfd,0xbc,0xa8,0x7f,
+  0x1d,0xf0,0x75,0x15,0x0d,0xf5,0xf3,0x42,0xd8,0x49,0xd6,0xe7,0x15,0xdc,0xc8,0xd2,
+  0x6f,0x70,0x75,0x4d,0xb7,0x67,0x17,0x1a,0x75,0xe9,0xaa,0x11,0x9c,0x2f,0x7e,0x65,
+  0x44,0x6e,0x56,0x1c,0xfd,0x46,0x27,0xa2,0x95,0x1a,0x2a,0x5f,0x29,0x8c,0x6e,0x32,
+  0xa4,0x58,0x86,0x9e,0xe1,0x5f,0xac,0xcf,0x6a,0x32,0xa7,0x43,0x6b,0x83,0x95,0xac,
+  0xfe,0x75,0x90,0x5f,0x41,0x5f,0x17,0xc8,0xe0,0x17,0x1b,0xfb,0xd6,0x4d,0x05,0x2b,
+  0x75,0x66,0xf8,0x93,0xd8,0x86,0x19,0x79,0x49,0x12,0xb2,0x78,0x53,0x89,0x50,0x1b,
+  0x7a,0x43,0xf2,0x36,0x6e,0x14,0x24,0x1b,0x06,0xb9,0x91,0x9f,0xcc,0xb5,0xf6,0x5f,
+  0xa4,0xa5,0x17,0x08,0x7b,0xf2,0x73,0x46,0x3c,0xc3,0xdc,0x08,0xda,0x73,0x51,0x3d,
+  0xec,0x99,0xa4,0x9f,0xf7,0x54,0x72,0x4e,0xcd,0x53,0xc1,0x16,0xff,0xea,0xb7,0xf3,
+  0x87,0x5e,0xbe,0x53,0xb2,0x33,0x1e,0xf9,0x7a,0xf4,0x79,0x51,0x3b,0x1e,0x84,0x4e,
+  0xf1,0x46,0x4d,0xd4,0xcf,0x2f,0x24,0x7f,0xcb,0x5d,0x77,0x03,0xbe,0x63,0x92,0x45,
+  0xc4,0x86,0x45,0x6d,0x2b,0x29,0xf0,0x6b,0x00,0xc3,0xc2,0xef,0x58,0x42,0x8e,0xc0,
+  0x05,0x69,0x1d,0xcd,0xe7,0xb5,0x24,0xbb,0xfe,0xe5,0x35,0xc4,0xfe,0xaf,0xce,0x1b,
+  0x12,0xa7,0x61,0x21,0x83,0xad,0x14,0xbc,0x21,0xce,0x8f,0xb2,0xeb,0x5f,0xd3,0x5e,
+  0xd0,0x18,0x6c,0x6d,0xec,0x2f,0xe7,0x40,0xc6,0x68,0x57,0xca,0xc1,0x2f,0x65,0x1c,
+  0x7e,0x05,0x93,0x18,0xee,0x1e,0xb2,0x71,0xf9,0x65,0x1a,0xce,0xd2,0x6f,0xa4,0x70,
+  0x7d,0x5d,0x25,0xf0,0x4b,0x21,0xbc,0xf0,0xdd,0x4c,0x46,0x09,0x23,0x62,0xac,0xfe,
+  0x25,0xd6,0x29,0x85,0xc7,0x54,0x71,0xe6,0xb0,0x7f,0x8a,0x64,0x09,0x39,0xde,0x11,
+  0x44,0xcc,0xa9,0x7f,0xd9,0xfb,0xbf,0x3a,0xf6,0xdc,0x10,0xb4,0x29,0xe7,0x20,0xdb,
+  0x9c,0x3e,0xae,0xfe,0x25,0xf0,0xcb,0xbb,0x4b,0x5e,0xc8,0x8f,0x8d,0xf2,0xb1,0x83,
+  0x7c,0x0f,0x42,0x97,0xd0,0xcf,0x37,0x4f,0xc4,0x2f,0x6a,0x89,0xd6,0x6c,0xfd,0xe1,
+  0xc4,0xf3,0xa3,0x7c,0x9b,0xe5,0x0a,0x6a,0x0b,0x39,0x6c,0x5e,0x90,0xd1,0x6f,0x08,
+  0xb7,0xbc,0x35,0x30,0x93,0x0b,0x39,0xe4,0x2c,0x6d,0xc6,0x24,0xfd,0xa1,0x3b,0x4b,
+  0xc8,0x61,0x19,0x47,0x26,0xea,0x0f,0xdd,0x0a,0x6d,0x99,0x80,0x05,0x13,0xeb,0x5f,
+  0x2e,0xb9,0xcc,0xb0,0xf8,0xc5,0x09,0xdb,0x98,0xa8,0x9f,0xef,0x97,0xcf,0x18,0x42,
+  0x64,0xd8,0xe0,0x20,0x9a,0xcd,0xad,0x5c,0x67,0x38,0x5a,0xe5,0xf7,0xcb,0x4f,0xab,
+  0xcc,0x08,0xc6,0xe5,0xdf,0xc1,0x6b,0x02,0xbf,0xec,0xf3,0xa3,0x90,0x9f,0x32,0xfc,
+  0xea,0x6c,0x25,0x09,0x6e,0xb0,0xfd,0xcb,0xad,0x02,0xd1,0xe4,0x82,0x1c,0x4b,0x1f,
+  0x25,0x7a,0x98,0xa7,0xad,0x5f,0xc3,0x0d,0x86,0xb9,0x5b,0xac,0x3e,0xfb,0x33,0xfa,
+  0x43,0x36,0xd2,0x4e,0x7f,0x60,0x27,0xb1,0xf8,0x69,0x5f,0xc2,0x1a,0x7b,0x8e,0x93,
+  0x3f,0xe4,0x68,0x95,0x1f,0x2f,0xfa,0x39,0x7f,0xbc,0x5e,0xd6,0x1f,0xeb,0x39,0x5b,
+  0xe7,0x47,0xad,0x90,0x76,0x12,0x9b,0x76,0x51,0x66,0xcc,0x61,0xe5,0xbc,0xf1,0xf5,
+  0xaf,0x0c,0x7e,0x15,0xe9,0xad,0x29,0x1b,0xbf,0x52,0xa4,0x6e,0x5c,0xfd,0x4b,0xd5,
+  0x18,0x5a,0xc9,0xef,0x93,0x6b,0x2a,0xd7,0x43,0x90,0x4e,0x61,0xfb,0x97,0xd7,0x5b,
+  0xf8,0x35,0xbe,0xfe,0xe5,0x09,0xbb,0x0b,0x94,0x36,0xc9,0x02,0xb2,0x87,0x14,0xae,
+  0xe8,0x18,0xaf,0x9f,0xef,0xf1,0x34,0x91,0x52,0x21,0x4c,0x42,0x20,0x33,0x7f,0x0a,
+  0xf9,0x59,0xf5,0xaf,0x5d,0xce,0xfe,0x2f,0xb9,0x00,0x98,0x90,0x83,0x69,0xda,0xc9,
+  0xb7,0xed,0xfa,0x97,0xf0,0xab,0xd3,0x76,0x0b,0xc9,0x53,0x1c,0x23,0x73,0xcb,0x67,
+  0x7e,0x92,0xb0,0x54,0x5e,0xbd,0xf6,0xf9,0x87,0x9f,0x8a,0xd3,0xf3,0xba,0xcb,0x67,
+  0x1b,0x47,0x45,0x18,0x7f,0xc1,0x78,0xb9,0x3d,0x3c,0xe0,0x5b,0xe8,0xb1,0xce,0x2d,
+  0x64,0xfa,0xf9,0x97,0x68,0xd9,0x90,0xe7,0x2f,0x88,0x1f,0xd6,0x91,0xaa,0x21,0x4f,
+  0x0d,0x39,0x4e,0xdf,0x48,0x6c,0x1b,0xf4,0xd4,0xb8,0x67,0x3b,0xe7,0x47,0x19,0x2f,
+  0x49,0x65,0xa9,0x29,0xcd,0x44,0xa5,0xbc,0xcf,0xf7,0x90,0x51,0xe4,0x5f,0x33,0x18,
+  0xff,0x72,0xce,0x3f,0xb4,0x64,0xf3,0x5b,0x89,0x44,0xac,0x50,0xff,0x88,0xfe,0x90,
+  0xd8,0x44,0xa0,0x3a,0xf5,0x2f,0x95,0x95,0xef,0x71,0x5d,0x54,0x19,0xd6,0x7a,0x1f,
+  0x6b,0x39,0x04,0x4c,0xf3,0xef,0x99,0x3d,0x61,0xff,0x57,0xfc,0xeb,0x83,0xf0,0x17,
+  0x99,0x58,0xbd,0x26,0xab,0xfe,0xe5,0xe8,0x0f,0xcf,0xc8,0xc5,0xc0,0x80,0xec,0xf2,
+  0x61,0xe2,0x68,0x06,0xac,0xfa,0x17,0xb5,0xeb,0x5f,0x5b,0xe4,0xbb,0x26,0x83,0xd4,
+  0x78,0xfd,0xa1,0x3b,0xd1,0x3a,0x7b,0x52,0x9b,0x6c,0xfd,0x21,0x3b,0x0a,0x0c,0xb6,
+  0x1b,0xbd,0x6d,0x24,0xd8,0xcb,0xf6,0x52,0xc1,0xde,0x90,0xd0,0x1f,0x3a,0xe7,0x47,
+  0xd1,0x73,0x7a,0xdd,0xc1,0x82,0x32,0x59,0xa7,0x38,0xae,0x63,0x9e,0x3d,0xf2,0x68,
+  0x07,0xdb,0x11,0xb6,0xb4,0x6b,0x87,0x29,0x83,0x85,0x5f,0x2a,0xaf,0xfe,0xf7,0xca,
+  0x49,0x73,0x4c,0xa9,0x3f,0xe8,0x3b,0x5d,0x7e,0xd8,0x18,0x8b,0xa1,0x63,0x3c,0x25,
+  0x0f,0x4a,0x0e,0x7e,0xbd,0x27,0xe2,0x8d,0x5a,0xf8,0x8c,0xe2,0xb2,0xa2,0x3c,0x7f,
+  0x58,0x3f,0x6e,0xff,0xd7,0x10,0x87,0x2d,0xec,0x61,0x05,0xeb,0x33,0x45,0x63,0xd4,
+  0xf8,0xa5,0x35,0x2e,0x87,0x7f,0x69,0x0f,0xd9,0xb1,0xc4,0x0e,0x09,0x97,0x15,0x10,
+  0x81,0x68,0x53,0x32,0xfc,0xeb,0xf6,0x0d,0xd6,0x90,0xdd,0x15,0x84,0xdf,0x67,0x1b,
+  0x61,0x27,0xc4,0x4e,0xe4,0x5f,0x1c,0x65,0x42,0x72,0xb5,0x81,0xaf,0xd6,0x4a,0xdf,
+  0x7a,0xc9,0xd1,0xcf,0x4f,0xe6,0x5f,0x7d,0xcc,0xe8,0x15,0x3c,0x85,0x8c,0xaf,0x7f,
+  0x65,0xf4,0x87,0xfa,0xa1,0x52,0x1e,0xea,0x1f,0x86,0x73,0x6a,0x5d,0x6f,0x36,0xff,
+  0xaa,0x32,0xac,0x29,0x18,0x80,0x4e,0xa3,0xba,0x5b,0x7d,0x1c,0xe7,0x14,0x79,0xe5,
+  0x29,0x24,0x98,0xa7,0xc4,0x63,0x46,0xfc,0x32,0xac,0x57,0xeb,0x15,0x36,0x9c,0x10,
+  0xbe,0x6a,0xaf,0xc5,0x70,0xc5,0x9d,0xf4,0x2c,0x6c,0x1d,0xc9,0xec,0xaf,0x5c,0x27,
+  0xf6,0x2f,0x1f,0x4f,0xac,0xa3,0xc1,0x98,0x7a,0x07,0xe3,0x5f,0xad,0xfc,0xfc,0xc3,
+  0x63,0x94,0xcf,0x69,0x54,0x0d,0x1a,0xbf,0xe5,0xf8,0x55,0xbe,0x9f,0xbe,0x0c,0xb5,
+  0x89,0x02,0xb6,0xff,0xeb,0x74,0x47,0xad,0x99,0x5b,0xd3,0x36,0xfe,0xfc,0x79,0xa6,
+  0x71,0x1d,0xcd,0x19,0x13,0x42,0xdf,0xf3,0xb1,0x89,0xfc,0xeb,0x53,0xb0,0xf4,0x87,
+  0x3f,0x67,0xe7,0x93,0x80,0xb7,0x43,0xfe,0x35,0x65,0x85,0xb0,0x25,0xdd,0x72,0xc0,
+  0xe6,0x5f,0x2f,0x64,0xf4,0x87,0x08,0x5b,0xa0,0xf6,0xb3,0xf3,0x76,0x08,0x2f,0x84,
+  0x39,0xfb,0x97,0x5f,0x14,0x7d,0x1e,0x21,0xff,0x86,0x86,0x94,0x76,0x8f,0x90,0xc7,
+  0xe0,0x17,0x74,0xc6,0x09,0x75,0x35,0x49,0x66,0xf0,0xcb,0x82,0xad,0x25,0xa4,0x0d,
+  0xb6,0xbf,0x3e,0x9b,0xe5,0x0f,0x77,0xc0,0x4e,0x56,0x08,0xf3,0x67,0xf8,0xd7,0x41,
+  0xbb,0x94,0xb0,0x1e,0xe6,0xc5,0x0b,0xd2,0xe5,0xbb,0xe0,0x23,0x58,0xc0,0x84,0x1c,
+  0x93,0xf5,0xf3,0xc2,0xe9,0xe5,0x31,0x5f,0xb7,0x95,0x9d,0x9b,0x9a,0xd1,0xcf,0x37,
+  0x4d,0xe0,0x5f,0x1d,0xb6,0xe1,0xb9,0x08,0xff,0x0a,0xfc,0x8e,0xd7,0xbf,0xa6,0x6d,
+  0xb1,0x0c,0xcf,0x96,0x0c,0xff,0x9a,0x99,0xd1,0x6f,0xb0,0xfa,0xd7,0xdf,0x6e,0xb1,
+  0x0c,0x4f,0xbc,0xd5,0xd6,0x1f,0x66,0xf1,0x2f,0xba,0x07,0xaa,0xa3,0x6e,0x3f,0x37,
+  0xc6,0xe5,0x0f,0x91,0x7f,0x75,0x0b,0xfd,0x7c,0x8f,0x31,0xdc,0x54,0x5b,0xbc,0xde,
+  0x36,0x98,0x7e,0x9e,0x8c,0xc7,0xaf,0x38,0xc7,0xaf,0xfa,0xc6,0xfc,0xdf,0x14,0x0d,
+  0x18,0x36,0x7e,0xe5,0xf2,0xb9,0x50,0x5d,0x0e,0xa2,0xcd,0x48,0x88,0x83,0x9b,0xda,
+  0x2a,0xf8,0x09,0x4e,0x78,0xe5,0x7d,0xe7,0xfc,0x5e,0x7d,0x50,0xe8,0xe7,0x59,0xfd,
+  0xab,0x1a,0x3a,0x7e,0xee,0xd6,0x15,0x66,0xe4,0xf5,0x66,0x9d,0x3f,0xdf,0x61,0xe9,
+  0x0f,0xb7,0xc0,0xe3,0x6a,0x55,0xb3,0xda,0xd4,0x5a,0xa2,0xa3,0x61,0x78,0x9a,0x1c,
+  0xfd,0xbc,0xa5,0x3f,0x44,0x5c,0x7e,0x0a,0x7e,0x05,0x73,0xf0,0x3d,0xcc,0x99,0xcf,
+  0x4f,0xd3,0xca,0xeb,0x77,0xf2,0x87,0x5b,0x1c,0x6d,0xfc,0x4e,0xd6,0x0d,0x23,0xb8,
+  0x45,0xe2,0xfd,0xc1,0x2b,0x52,0xd6,0xfe,0x65,0x71,0x45,0x6e,0xb4,0xf6,0x2f,0x67,
+  0xf2,0x87,0x07,0x6d,0xfe,0xb5,0x9d,0x9f,0xf3,0xe6,0x6b,0x95,0x99,0xa0,0x69,0x1e,
+  0x82,0x89,0x2c,0x94,0x4d,0x5e,0xb3,0xcc,0x2d,0x6a,0x49,0x95,0xca,0x42,0x9e,0x49,
+  0xf6,0xd8,0xdb,0xbe,0x78,0xfd,0xeb,0x6d,0x8a,0x46,0x9a,0x64,0x9d,0x1f,0x55,0xce,
+  0xde,0xb1,0xf9,0x50,0x00,0x6d,0x94,0xd7,0xbf,0xf0,0xad,0x23,0xdc,0x58,0xaf,0x5b,
+  0xfc,0x6b,0xba,0x0d,0x5b,0x85,0xd0,0x6e,0x2e,0xd3,0xd4,0x46,0x62,0xc2,0x96,0x8e,
+  0xb2,0x90,0xba,0x84,0x74,0x38,0xfa,0x43,0x71,0xec,0xe1,0x6a,0x04,0x93,0x23,0x74,
+  0x6f,0x22,0x38,0xe8,0x79,0x1b,0x8e,0xd0,0x79,0xcc,0x58,0x6f,0xe1,0xd7,0xa5,0x6c,
+  0xff,0xd7,0x74,0x21,0x2f,0x17,0xc3,0xc1,0xb1,0x5b,0xc2,0xd1,0x88,0xcd,0xbf,0xbe,
+  0x30,0xb8,0x1e,0xfb,0x43,0xf9,0x73,0xe3,0x93,0x96,0xab,0x62,0xca,0x5b,0x72,0x35,
+  0xbc,0x46,0xeb,0x97,0x7b,0xdf,0x72,0xf2,0x87,0x62,0xff,0xd7,0x60,0x67,0x25,0xf9,
+  0x88,0xae,0x45,0x5c,0x56,0xff,0x96,0xf8,0xcd,0x9f,0x27,0xe7,0xec,0x42,0xc3,0xd1,
+  0xb4,0xc7,0x29,0xdf,0xbf,0x7c,0x17,0x19,0xd6,0x77,0x42,0x95,0xa6,0x46,0x48,0x94,
+  0xb6,0xc3,0x1c,0x55,0x8d,0x92,0x01,0xf1,0x0c,0x9d,0xfd,0xcb,0x3a,0xaf,0xfd,0x61,
+  0xf0,0x3f,0xbf,0x75,0xb9,0x5a,0x2e,0x32,0x1e,0xc7,0x26,0xec,0x5f,0x4e,0xca,0x9f,
+  0xaa,0xbf,0x64,0x81,0x7d,0xb2,0x68,0x39,0xf7,0x00,0xd1,0x64,0xf9,0xe0,0xc4,0xfd,
+  0xcb,0x82,0x02,0xeb,0x3e,0x55,0xde,0xc5,0x17,0x5a,0x3d,0xcd,0x3a,0xbf,0xd7,0xf6,
+  0x99,0xc7,0xe0,0x38,0xe1,0x0b,0x36,0x64,0x3c,0x88,0x2d,0x7c,0xe9,0x72,0x6b,0xff,
+  0x72,0x4f,0x46,0x7f,0x28,0x42,0xbe,0xce,0x38,0x09,0x5a,0xb1,0xdf,0x2d,0xb6,0xfe,
+  0x50,0xa9,0x14,0x6d,0x12,0xd8,0xc6,0x4a,0xcb,0xef,0x84,0x27,0xec,0x18,0xd2,0x5a,
+  0x5f,0xbc,0xe6,0x92,0xc2,0x71,0xa5,0x62,0xad,0x24,0x48,0x3b,0xf5,0xb5,0x1d,0x81,
+  0xed,0x52,0xb0,0x55,0xae,0x88,0x5b,0xfc,0xcb,0x50,0x63,0xed,0xe7,0x08,0x7a,0xe3,
+  0x6d,0x18,0xd3,0x1e,0x63,0x87,0x7b,0xaf,0xf5,0x24,0xe8,0xa0,0x56,0xa7,0xfa,0xd6,
+  0x96,0x3b,0xfc,0xcb,0xda,0xff,0xb5,0x4d,0x1e,0xa2,0x63,0x70,0xf9,0x41,0x5f,0x57,
+  0xdb,0x8f,0xe1,0x1d,0x44,0xb4,0x8d,0x5d,0x45,0x93,0xf4,0xf3,0x77,0x3b,0xc4,0xf9,
+  0x7d,0x72,0x94,0x45,0x20,0x23,0xf2,0xb0,0xa5,0x1b,0xb4,0xf5,0xf3,0xdd,0x60,0x1b,
+  0xd8,0xd5,0x4e,0x98,0xcd,0x8d,0x1c,0x9b,0x7f,0xa9,0xec,0xb7,0x00,0x6e,0x0c,0x19,
+  0x68,0x08,0xa7,0x97,0x06,0x2b,0x56,0x7f,0x7f,0x5c,0xfd,0x8b,0x43,0xb6,0xe6,0x40,
+  0x76,0xa7,0xd0,0x6f,0x0c,0x5b,0xbc,0xa9,0x64,0x72,0xba,0xef,0x65,0x7e,0x6e,0xe1,
+  0x1f,0xdf,0xbf,0x7c,0xfa,0x8f,0xec,0x5f,0xb6,0x8d,0x13,0xfc,0x20,0xc4,0x0c,0x7e,
+  0x1d,0x63,0x5a,0x1a,0x71,0xfe,0x86,0x08,0x21,0x7c,0x9c,0x7f,0xd1,0x40,0x96,0xfe,
+  0x70,0xd0,0xc9,0x1f,0xe6,0x38,0xf9,0x8d,0x57,0xe9,0x43,0x54,0xcf,0xd2,0x1f,0x22,
+  0xff,0xb2,0xd4,0x47,0x77,0xf1,0x5c,0xdc,0x20,0x3b,0x94,0x89,0xae,0xa3,0xcb,0xf0,
+  0x4a,0x8e,0xc3,0xbf,0x0a,0xde,0xdc,0x0b,0xb5,0x83,0x4c,0x3f,0x6f,0xb2,0x83,0xa4,
+  0x3c,0x0b,0xe5,0xfd,0x15,0xef,0x74,0x24,0x07,0xb3,0xf4,0x87,0xd3,0x76,0x73,0xda,
+  0x75,0x39,0x8e,0x4b,0xe1,0xfc,0x6b,0x0f,0x2e,0x99,0x73,0x96,0x91,0xcd,0xbf,0xd8,
+  0xfe,0x65,0x8f,0xf8,0x81,0x98,0xdc,0xcc,0x00,0x17,0x65,0xf1,0x2f,0x2b,0xbb,0x92,
+  0xa5,0x9f,0xb7,0xf5,0x87,0x39,0x86,0x78,0xe7,0x99,0xfe,0xf0,0x7b,0x2c,0x4c,0xfd,
+  0x0e,0x3b,0xc8,0x37,0x2d,0xaf,0x46,0x20,0x1b,0xaf,0x3f,0x44,0xfc,0xb2,0xa7,0x72,
+  0x89,0xb5,0xd1,0x32,0xf0,0xe9,0x24,0xfd,0xa1,0xb3,0xff,0x6b,0x85,0x6d,0x9c,0x35,
+  0x85,0x41,0x26,0xe7,0x0f,0x9d,0x9f,0x4d,0x49,0xb3,0x83,0x6e,0x04,0xff,0x12,0x7e,
+  0x5e,0x1b,0x90,0xc6,0xe1,0x17,0x13,0x78,0x4b,0x07,0xec,0xfd,0x5f,0xba,0x8d,0x5f,
+  0x0f,0x67,0xe7,0x06,0xf9,0x01,0x11,0x2d,0x46,0x80,0x15,0x91,0xd3,0xd2,0x04,0xfe,
+  0x95,0x49,0x1b,0x0e,0x11,0xeb,0xfc,0x8d,0x49,0xfc,0xcb,0x92,0xf0,0xb9,0x99,0x71,
+  0x3f,0x24,0x26,0xf0,0xaf,0xee,0xec,0xb4,0x98,0x87,0xf1,0xaf,0xf5,0x4d,0x4c,0x9f,
+  0x90,0xfb,0xa9,0x88,0x0f,0x19,0x7e,0x4d,0xdc,0x0b,0xcc,0xf4,0xf3,0x02,0xbf,0x2c,
+  0x4c,0xb1,0xf6,0x7f,0x6d,0xec,0x97,0x2b,0x2c,0xb2,0xe6,0x99,0x6f,0x9c,0xd7,0xf8,
+  0xb8,0xf6,0xbb,0x1c,0xfe,0x25,0xd2,0x86,0x6e,0x3d,0xdb,0x08,0x67,0xd7,0xbf,0x1c,
+  0xfd,0x7c,0x26,0x7f,0x98,0x43,0xf7,0x08,0xcd,0xc9,0xeb,0x62,0x9d,0x66,0xed,0xff,
+  0x72,0x1e,0x02,0x43,0xf3,0xed,0x17,0xd7,0x1f,0x56,0x64,0x8c,0x93,0x96,0x7e,0x1e,
+  0x6c,0xfe,0x35,0x3e,0x96,0xf0,0xd9,0xba,0xca,0x8b,0xf1,0xaf,0xec,0xfc,0x61,0x4a,
+  0x15,0xfa,0x8d,0xec,0xfd,0x5f,0x22,0x7f,0xc8,0xf5,0xf3,0x68,0x9c,0x55,0x1f,0xec,
+  0x09,0x5c,0x44,0x7f,0xf8,0x48,0x56,0xfe,0xf0,0x28,0x6d,0xd3,0x62,0xe6,0x45,0xf6,
+  0x7f,0x89,0xd7,0x98,0x6f,0x5b,0x7e,0x0f,0xd6,0x88,0x7c,0xc2,0x44,0xfe,0x65,0xe7,
+  0x0f,0xa7,0xac,0x96,0x2f,0x20,0x90,0xed,0xc9,0xd6,0x1f,0x4e,0x9b,0xec,0x13,0x46,
+  0x59,0xe7,0x59,0x12,0x3e,0xc3,0xbf,0x8c,0x73,0x6c,0x1b,0x51,0xb7,0xfc,0x29,0xdf,
+  0xc8,0xec,0x3b,0x2b,0x7f,0xc1,0x70,0x30,0x5b,0x7f,0x58,0xf8,0x20,0xdd,0xb7,0x9d,
+  0xe9,0xe7,0xf1,0x8d,0xda,0x27,0x0a,0x58,0x6f,0x42,0x6b,0x02,0x7d,0x42,0x8d,0xfc,
+  0x64,0xd6,0xf9,0xbd,0x7a,0x55,0xcf,0x8d,0x5c,0x3f,0xcf,0x80,0x6c,0x15,0x39,0x06,
+  0x3f,0xd7,0xcb,0xcc,0x8c,0xfe,0x50,0xcf,0x9c,0xbf,0x61,0x1f,0xdb,0x8b,0x71,0xd4,
+  0x76,0xe1,0x33,0x3b,0xb2,0xcf,0xef,0xe5,0x27,0xc9,0x33,0xd9,0x21,0xef,0xf3,0xef,
+  0x31,0x32,0x67,0xfa,0x8d,0x89,0xfb,0xbf,0xb2,0xc7,0xf5,0x01,0xfc,0x99,0x30,0x12,
+  0xe3,0xf6,0x2f,0xf7,0x64,0xfb,0xcc,0x33,0xca,0x85,0xf1,0xfc,0xcb,0xc1,0xaf,0x00,
+  0x2b,0xd9,0x70,0xff,0xfc,0x7b,0xf6,0x42,0x66,0xf3,0x2f,0x29,0xab,0xe6,0x62,0x51,
+  0x8f,0x4f,0xf5,0xe7,0xec,0xfc,0xa1,0xb5,0xbe,0xbc,0x74,0xaf,0xca,0xf4,0xf3,0xa2,
+  0x84,0xd4,0xdf,0x19,0xda,0xfe,0x0a,0xf0,0xbd,0x54,0x73,0xb3,0xf8,0x57,0x9a,0x6d,
+  0xb5,0x5e,0xfa,0x4c,0xf9,0x27,0x26,0x27,0x1a,0x5d,0x6c,0x9f,0xd4,0x7d,0xec,0x2c,
+  0xaf,0xb6,0x71,0xe7,0xf7,0xd6,0xa7,0x7c,0xa7,0x5f,0x1e,0x35,0x3f,0x63,0xe7,0x99,
+  0x77,0x3d,0xf4,0x26,0x3d,0xa5,0xd7,0x33,0x0e,0xe2,0x9c,0x1f,0x35,0x0a,0xaf,0xea,
+  0x7b,0x79,0xd9,0x4b,0xb2,0x0e,0xfe,0x5a,0x50,0x7a,0xd8,0x98,0xd7,0xe4,0x1d,0x2c,
+  0x67,0x67,0x15,0x83,0x38,0xff,0xb0,0x33,0x96,0x29,0x7b,0xe9,0x6a,0x47,0x60,0x26,
+  0x3b,0x77,0xd7,0xe8,0x48,0xb4,0xda,0xe7,0x1f,0xc2,0x06,0x68,0x2d,0x75,0xf4,0x87,
+  0x18,0x43,0xc6,0x91,0x02,0x53,0x5d,0x8f,0xaa,0x81,0x88,0x7d,0xfe,0x3c,0xec,0x56,
+  0xd7,0xab,0x01,0x67,0xff,0x57,0x40,0xdd,0x4a,0x2a,0x49,0x87,0xba,0xdd,0xc0,0xc0,
+  0x6c,0x44,0xcc,0x97,0x74,0x3b,0xb2,0x2d,0xa3,0xcb,0xb4,0xce,0xdf,0xe0,0x07,0x7f,
+  0x29,0xca,0x81,0xfe,0xc0,0x80,0x37,0x51,0x9e,0xb2,0xf5,0x87,0x8f,0xc2,0x1f,0xb4,
+  0x97,0x1c,0xfc,0x02,0x9f,0x59,0x7e,0x06,0x9d,0x79,0x6d,0x4f,0x7d,0xfa,0xee,0x2c,
+  0xfe,0x75,0x50,0xcc,0xf2,0x90,0xfa,0xb1,0xab,0x8e,0x1d,0x6f,0x5b,0x89,0x6b,0xb0,
+  0xcb,0x40,0x5e,0xd0,0x6f,0xeb,0x37,0x6a,0xe9,0x83,0x60,0xe9,0x2a,0x3f,0x26,0xd5,
+  0xa0,0xc6,0x31,0x3e,0xdc,0x8b,0xe3,0x52,0x77,0x6f,0xfe,0x5c,0xe8,0xd9,0xd8,0xf9,
+  0x87,0xad,0x6a,0x96,0xae,0x52,0xd5,0x89,0xa2,0x74,0x81,0xde,0x83,0x86,0xc5,0xd1,
+  0x62,0xda,0x77,0x8c,0x07,0xe9,0x32,0xbb,0xfe,0x55,0x95,0x56,0x57,0x90,0x4b,0xe0,
+  0x19,0xbc,0xa2,0xae,0x8c,0x38,0xfa,0xc3,0x25,0xd0,0x03,0x21,0xd3,0x37,0x97,0xd1,
+  0x2e,0xa8,0xed,0x53,0xc3,0xb2,0x0a,0xa7,0xf5,0x90,0x19,0xd4,0xe5,0xb7,0xc5,0x7d,
+  0x8c,0x92,0x0d,0xc4,0x3a,0xa1,0x71,0xc8,0x26,0x8f,0x1f,0x89,0x8c,0x7d,0xc2,0xc6,
+  0x5c,0x55,0x79,0x4c,0x3d,0x28,0x50,0x78,0x08,0x4e,0xd3,0x1a,0xd3,0xa7,0xcb,0x39,
+  0x90,0x62,0xf9,0xc3,0x84,0xec,0x2e,0xe6,0x6d,0xa2,0xa5,0xff,0x27,0xb4,0x9a,0xdb,
+  0xec,0xf5,0x8e,0x4b,0x26,0x16,0x29,0x86,0x56,0x66,0xa4,0x49,0x58,0xac,0x65,0x1d,
+  0x1e,0xa3,0xeb,0x12,0xdb,0xb2,0x6a,0x76,0x23,0xe4,0x32,0x58,0x63,0x96,0xc5,0x3c,
+  0x2b,0xdc,0x60,0xeb,0xe7,0x19,0x5f,0x4e,0xd8,0x63,0xe7,0x0f,0x41,0x85,0xb6,0x98,
+  0x1e,0x43,0x47,0xe4,0xb7,0xf5,0x87,0x83,0x70,0x44,0xa8,0x0d,0x85,0x8f,0xc2,0xfe,
+  0x54,0xc2,0x11,0xb3,0xab,0xd5,0x97,0x96,0xc3,0xb6,0x9e,0x0d,0xa7,0x57,0x1b,0xe7,
+  0xeb,0xa6,0x0c,0x93,0x89,0xfb,0xbf,0xd0,0x67,0xc6,0xc3,0xe3,0xf6,0x1c,0xcd,0x6c,
+  0xb7,0x4e,0x81,0xb0,0xce,0x33,0x37,0x19,0xff,0xe2,0x6a,0x43,0x3f,0xc7,0x26,0xa4,
+  0x5d,0x91,0x2b,0xc4,0x26,0xaf,0x52,0xb7,0xe5,0x35,0x16,0x5e,0x57,0xa1,0x3d,0xab,
+  0x06,0xb2,0xf0,0xab,0x9f,0xcc,0x17,0xbf,0x81,0xb5,0x89,0x08,0x99,0x27,0xd7,0x1f,
+  0xee,0xd1,0x13,0x36,0x7e,0x55,0xc5,0x3c,0xc7,0xc8,0x25,0xca,0x9e,0xb2,0x60,0x14,
+  0xff,0x95,0xf5,0x1b,0x7e,0x23,0x2c,0x7f,0xd8,0x24,0x8e,0x55,0xcf,0xb3,0xba,0x1a,
+  0xe2,0x1b,0x99,0x91,0x91,0x2d,0xb0,0xf5,0x87,0x03,0x88,0x44,0x59,0x7e,0x7e,0x69,
+  0xd2,0xc3,0x85,0x88,0xd7,0xf9,0xfa,0xe5,0xf7,0x73,0x2c,0xfd,0xe1,0x19,0x7a,0x3e,
+  0xdd,0xc5,0xe1,0x98,0x43,0x1b,0xd7,0xab,0x5f,0x5f,0xc9,0x7e,0x3f,0x45,0x0e,0x08,
+  0xcd,0xc0,0xc2,0x52,0xc4,0x2f,0x1a,0x10,0xfa,0x79,0x86,0x5f,0x1d,0xcc,0x60,0xbf,
+  0x64,0xa1,0x9a,0xd8,0x67,0x4b,0xbf,0xb1,0x86,0xed,0x56,0xb6,0xfb,0x5c,0x6d,0xa8,
+  0x4d,0xe4,0x0c,0xac,0x51,0xcb,0x9a,0xd4,0x5b,0x5a,0x2f,0x93,0xf8,0xe8,0xb7,0x2a,
+  0x3b,0xe1,0x79,0x3d,0x20,0xca,0x5e,0xec,0x20,0x44,0xa6,0x3f,0x0c,0xac,0x6b,0x64,
+  0xbc,0xdb,0x5f,0x6d,0xed,0xff,0xba,0x7d,0x80,0xa9,0xbc,0x32,0x7d,0xf6,0x6e,0x69,
+  0xe8,0x33,0x0e,0x40,0x38,0xe6,0xc5,0x97,0x5f,0xb7,0xe6,0x6b,0xa7,0x72,0x52,0x79,
+  0x31,0xd3,0x86,0xe5,0x0f,0xd1,0x78,0x31,0x3a,0x27,0xee,0x71,0xf4,0x87,0x88,0x5f,
+  0xba,0x75,0xec,0xfc,0xa0,0x10,0x72,0x9c,0x80,0x11,0x05,0x0d,0xb3,0x88,0xd8,0xfa,
+  0xc3,0xd9,0xfa,0x8b,0x94,0xa3,0xd5,0xa0,0xf6,0x1c,0x04,0x99,0xfe,0xd0,0x3a,0xff,
+  0x30,0x4d,0x88,0x26,0xda,0x28,0x8d,0xb0,0xd7,0x4c,0x64,0xad,0x2f,0x16,0x28,0x22,
+  0x40,0xa7,0x71,0x7d,0x59,0x73,0x41,0xb5,0xdb,0xe0,0x19,0xa1,0x9e,0x65,0x67,0x59,
+  0xcc,0xe1,0x85,0x5d,0x78,0x5a,0xaa,0xea,0xc7,0xfb,0x08,0x97,0x09,0x1d,0x1d,0xdf,
+  0xc2,0xf0,0x7b,0x8f,0xc0,0x2f,0x24,0x62,0x09,0xef,0x0a,0x84,0xda,0xff,0x8d,0x01,
+  0x79,0x30,0x25,0x8b,0x57,0x1e,0xd4,0x92,0x9d,0xd9,0x7e,0xbe,0x96,0xce,0x49,0x60,
+  0xe7,0xd9,0x3e,0xa9,0x5c,0xea,0x39,0x68,0xeb,0x0f,0xff,0xe5,0x16,0x2b,0x7a,0x47,
+  0x7f,0x18,0xaf,0x1f,0xdc,0xb8,0x3a,0xb7,0xce,0x38,0x4f,0xeb,0x63,0xbe,0x41,0xb9,
+  0x5f,0x8c,0xeb,0xc9,0xd2,0x2d,0xb0,0x56,0xb3,0xfa,0xf3,0x07,0x0e,0xac,0xf2,0x9d,
+  0xc6,0xd3,0x5a,0x55,0x63,0x5e,0x8c,0x7c,0xb4,0x98,0xb7,0xd1,0x60,0x8b,0xd6,0x02,
+  0x76,0x9f,0xa5,0xaa,0x8e,0xce,0x65,0x6e,0x2d,0xfa,0x34,0xe3,0xcb,0xd7,0xa3,0xb7,
+  0xe1,0x6d,0x62,0x4a,0x3b,0x62,0x8f,0xe5,0x5b,0x90,0x76,0x31,0x7c,0x27,0xf0,0x2c,
+  0x0d,0x1a,0x79,0x10,0xb6,0xbe,0x6b,0x17,0xcb,0xf7,0xea,0x5d,0xa2,0xcc,0xcd,0x63,
+  0xec,0x38,0xa9,0xd2,0xbf,0x68,0xab,0xa3,0x1e,0x76,0x02,0x2a,0x7f,0x37,0xe2,0x18,
+  0x6f,0x58,0x3f,0xfb,0x65,0xd5,0xf5,0xe2,0x48,0x58,0xbe,0x30,0xea,0xe2,0xb9,0x4f,
+  0xc9,0x03,0xb6,0xfe,0xf0,0x29,0x38,0x6f,0xec,0x75,0x7c,0x26,0xf5,0xa5,0xca,0x87,
+  0xd5,0x0b,0xbd,0x73,0xa9,0xb7,0x5f,0xb6,0xf4,0x87,0x8f,0xe3,0xfa,0x4a,0x1a,0xdb,
+  0x9d,0x94,0x20,0xf5,0x74,0x60,0x58,0xf8,0x9c,0x11,0x88,0xab,0x5b,0x22,0x27,0x97,
+  0x59,0xf9,0x43,0x16,0x11,0x05,0xb2,0xd2,0x86,0x9b,0x91,0x8c,0x3c,0x07,0x01,0x88,
+  0x26,0x03,0x69,0x31,0x5f,0x88,0x5f,0x90,0x84,0x6c,0x2d,0xba,0x86,0xc6,0x73,0xf8,
+  0x92,0x22,0xaf,0x74,0xf4,0x87,0xcb,0xed,0x53,0x95,0x38,0xe6,0x32,0x59,0x54,0xba,
+  0xf4,0x39,0x29,0x0c,0xc1,0xb8,0x9c,0x6e,0x75,0xea,0x5f,0x17,0xb2,0x78,0x0a,0xdd,
+  0x68,0xde,0x35,0x8c,0x98,0xfb,0x12,0xf8,0xfa,0xbf,0x9f,0x9e,0x69,0xe9,0x37,0x1c,
+  0xda,0x75,0xc1,0x16,0x72,0x4c,0xdc,0xff,0x45,0x1d,0xfe,0x45,0xec,0x83,0x7c,0xc9,
+  0xa7,0xda,0xf3,0xed,0xd5,0x27,0x3c,0xdd,0x91,0xec,0xf3,0xa3,0x64,0x7e,0x32,0xc3,
+  0x61,0x76,0x04,0x25,0x1a,0x77,0x65,0xed,0xff,0x12,0xdf,0x55,0x28,0xf8,0x57,0xa7,
+  0xcd,0xbf,0xa6,0x64,0x1d,0xdc,0xe4,0x9c,0x7f,0x38,0xb9,0x16,0x29,0xce,0xa2,0x5c,
+  0x9a,0x2c,0x9a,0x74,0x7e,0xaf,0x3c,0x7a,0xe9,0x38,0x22,0xe6,0xb9,0x08,0xff,0x6a,
+  0x18,0x1a,0xf7,0xa0,0xb2,0xf5,0x1b,0x56,0x2e,0x57,0x16,0x3f,0xd1,0xb2,0x20,0x3b,
+  0x97,0x1b,0xb9,0xf8,0xf9,0x51,0xe3,0x37,0x08,0x64,0xf4,0x1b,0x71,0x06,0x5b,0x53,
+  0xee,0x23,0xc7,0xe3,0x2f,0xd1,0x19,0xe2,0xfc,0xa8,0x7d,0xdb,0xaa,0x4e,0x70,0x2e,
+  0xc3,0xef,0xc3,0x7f,0xbf,0x32,0x59,0xdb,0xc7,0xf9,0xd7,0x39,0x08,0x0d,0xfa,0xae,
+  0x66,0x40,0x46,0x6b,0xcd,0x8d,0xd7,0x64,0x9d,0x1f,0xd5,0x78,0x4e,0x6c,0x5b,0x1e,
+  0x6a,0xfa,0x98,0x15,0x37,0x93,0xdf,0x18,0xb5,0x37,0xd4,0x67,0xeb,0x37,0x14,0x8c,
+  0x5b,0xf8,0x71,0x8e,0xca,0xb8,0xa0,0xab,0x61,0xd2,0xf9,0x51,0x19,0xda,0xf5,0xee,
+  0x84,0xfd,0x5f,0xb6,0x7e,0xc3,0xc1,0x5c,0xc7,0x98,0x32,0xfe,0xfc,0xa8,0x49,0x7b,
+  0xb7,0xf7,0x8a,0x22,0xc5,0xa4,0xf3,0xa3,0x2c,0x4d,0xf2,0xc6,0x44,0xd1,0xa0,0xf7,
+  0x0b,0x91,0xa0,0xf8,0x4f,0xf5,0x1b,0x7f,0xe4,0xfc,0xa8,0xa5,0xd9,0xfb,0xbf,0x2e,
+  0xa6,0xdf,0xc8,0x18,0x35,0x7f,0xec,0xfc,0xa8,0x22,0xcb,0x58,0xf4,0x65,0xe7,0x47,
+  0x29,0x0e,0x11,0xab,0xcc,0xce,0x1f,0x66,0xef,0xff,0x9a,0xd8,0xe7,0x8b,0x9e,0x1f,
+  0x45,0xc6,0xf3,0x14,0x4b,0xbf,0xb1,0x55,0x1a,0xb8,0x28,0x97,0xb9,0xc8,0xf9,0x51,
+  0x92,0x83,0x5f,0xd9,0xc6,0x11,0xc1,0xdf,0x33,0xfb,0x97,0x2d,0xce,0xd8,0xa6,0x45,
+  0x9c,0x2b,0x17,0x39,0x7f,0x63,0xb2,0x76,0xc5,0xca,0x1f,0x16,0xda,0xdf,0xde,0x30,
+  0xb9,0x3f,0x59,0xe7,0x47,0x89,0x29,0xb8,0x48,0xe7,0x0f,0xfe,0x31,0xfe,0x35,0x41,
+  0xbf,0x61,0xf3,0x2f,0x76,0x24,0xe6,0x73,0x8a,0xd8,0xbf,0xfc,0x25,0xfb,0xbf,0xa6,
+  0x4c,0x38,0x9f,0x2d,0x5b,0xbf,0x91,0xc5,0xbf,0x1e,0xb5,0xf9,0x97,0xf3,0x3e,0x0f,
+  0x8a,0xf3,0xb1,0x33,0xfc,0xeb,0xd6,0xe3,0x59,0x44,0xac,0x7d,0xb2,0xfe,0x90,0xad,
+  0x14,0xc9,0x3e,0x67,0xa9,0xc8,0xf1,0x09,0x19,0xfd,0x86,0xc8,0x1f,0xf2,0xf3,0xa3,
+  0x18,0x11,0x3b,0xcb,0x89,0x18,0x37,0x32,0xe7,0x6f,0xd0,0xbd,0xec,0xfc,0xc3,0x6b,
+  0x08,0xdb,0xbf,0x1c,0xe4,0xeb,0x9d,0xb2,0xdf,0x4b,0xf2,0xac,0x8e,0x58,0x9c,0xa8,
+  0x14,0xac,0xf3,0x0f,0xad,0x63,0x7b,0xb9,0x21,0xed,0xd3,0xaa,0xb2,0xf7,0x7f,0x39,
+  0xeb,0xcb,0x9f,0x19,0xbb,0xad,0xe8,0xb0,0xce,0xdf,0x48,0x38,0xfc,0xab,0x7c,0x32,
+  0xc9,0xfa,0x23,0xfc,0x2b,0x2b,0xa3,0x68,0xeb,0x37,0x60,0x4c,0x19,0xcf,0xbf,0x18,
+  0x23,0xfb,0x11,0x3f,0x59,0x71,0xe2,0xf9,0x1b,0x19,0xfe,0x35,0xa4,0xb2,0x8a,0x61,
+  0x27,0x62,0xd3,0x45,0xf8,0xd7,0x44,0xc3,0xe1,0x5f,0xf9,0x99,0xa9,0x44,0xfe,0x75,
+  0x50,0xd4,0xbf,0x58,0x45,0x6c,0xbe,0xa3,0x3f,0xcc,0x5f,0xc9,0xab,0x5d,0x1b,0x9f,
+  0xf1,0x73,0xfd,0x06,0x3f,0x64,0x3e,0x71,0xae,0xb6,0x06,0xb9,0x55,0xe6,0xf7,0x53,
+  0x86,0x8c,0xb1,0x59,0xf5,0x7d,0xbe,0xbd,0x6d,0x43,0x7d,0x9f,0x41,0xdd,0x41,0xdf,
+  0x33,0x6c,0x3f,0x6c,0xa0,0x86,0x9d,0x60,0x39,0xe8,0xe7,0x73,0x01,0xaf,0x2c,0x92,
+  0x9b,0x8d,0x3b,0xb5,0xab,0x94,0xfc,0x1e,0x89,0x19,0x5f,0xcb,0xc9,0x7f,0x45,0xba,
+  0x27,0xef,0x4e,0xf5,0xaa,0xb2,0x7c,0x73,0x2e,0x88,0x36,0x8d,0xb9,0xf7,0x48,0x77,
+  0x1a,0x5f,0xd3,0x4a,0xfa,0xb8,0xf1,0x6d,0xad,0xc4,0x54,0xe6,0xc2,0x06,0xe3,0x1b,
+  0xc5,0x8a,0x59,0xd8,0x24,0x3a,0x44,0x24,0x9d,0x46,0x75,0xbf,0xaa,0xb4,0x0a,0xc3,
+  0x8b,0xc6,0x3d,0x54,0xd5,0x8b,0x54,0x97,0x08,0x25,0xd8,0x83,0x46,0x22,0x76,0x07,
+  0x5c,0x02,0x2e,0x2a,0xc5,0xa4,0x3b,0xe0,0x36,0x34,0x1e,0x8f,0xa9,0x51,0x7e,0xc5,
+  0x6a,0xf3,0x4a,0xd4,0xb5,0x4a,0xba,0x93,0x7e,0x4d,0x2f,0x49,0x71,0xe3,0xdb,0xdf,
+  0x2d,0x4e,0xb9,0x7e,0x50,0x1b,0xed,0xfb,0xf6,0x32,0xe7,0xbb,0x5e,0x69,0xc2,0x45,
+  0x54,0x0a,0x8b,0x15,0xa9,0x85,0x1b,0x39,0x12,0x6d,0x85,0xd8,0x26,0x15,0x8d,0x38,
+  0xb5,0xfb,0x6c,0x28,0x01,0x49,0x85,0x88,0xae,0x51,0x45,0xe7,0x46,0x21,0x2d,0xc6,
+  0x2b,0x66,0x04,0x34,0xa7,0xcd,0xad,0x52,0xa4,0xa7,0x49,0xbf,0x2d,0x58,0x42,0x24,
+  0x83,0x36,0x95,0x15,0x2f,0xbc,0x3d,0x22,0x45,0xa0,0x29,0x79,0x5b,0x69,0x09,0xd8,
+  0xe3,0xf2,0x4a,0x45,0x70,0x9d,0xa9,0x35,0xbb,0x96,0x48,0x5f,0x33,0x6e,0x33,0x4b,
+  0x7e,0xa0,0x78,0xa5,0xdb,0x4d,0xa3,0xbf,0xb0,0xd9,0xfa,0x19,0x04,0x36,0x2e,0x74,
+  0x9e,0x8c,0xaf,0x49,0xa0,0xf8,0xf1,0xf6,0x4a,0x1c,0x54,0xb8,0x1e,0x54,0x43,0xda,
+  0x0a,0x92,0x3d,0xae,0x18,0x29,0x85,0xb5,0x10,0xc3,0x27,0x42,0x4a,0x8d,0x56,0xd0,
+  0xdb,0xd1,0x50,0x0d,0x02,0x65,0xb4,0x54,0x72,0xc6,0xe5,0x8a,0x49,0x6f,0xc1,0xb7,
+  0x8c,0x19,0xd4,0xb5,0x5c,0x3a,0x06,0x3f,0x34,0x8a,0x69,0xee,0x72,0x29,0x85,0x57,
+  0x8a,0x33,0xe3,0xca,0x8b,0xc1,0x31,0x7c,0x62,0xf9,0x54,0xba,0x0b,0xee,0xa0,0x97,
+  0xc0,0xb4,0x0e,0xa9,0x59,0x8a,0xc2,0x02,0x98,0xe6,0xb4,0x89,0xe4,0x84,0x5a,0xbc,
+  0x7a,0x83,0xaa,0xbd,0x7c,0x49,0xe8,0x15,0x66,0x94,0xbe,0xac,0xb0,0x6f,0x6e,0xf0,
+  0x82,0x39,0xd7,0x1a,0x97,0x6a,0x84,0x58,0xd0,0x8c,0x30,0x8e,0x6f,0xb8,0x17,0xbb,
+  0x8e,0x98,0xc6,0x72,0xd7,0x78,0xc5,0xb0,0xc7,0xe5,0x91,0x42,0x74,0x49,0xb2,0x48,
+  0x55,0x0e,0x4a,0xa1,0x96,0x25,0xa1,0x5b,0x55,0xa5,0xd7,0x15,0xc2,0xc9,0x2d,0x52,
+  0x8b,0x4d,0xf1,0x9b,0x4a,0xf0,0x4a,0xc3,0x8c,0xe6,0x96,0x3b,0x42,0x7e,0xb5,0xa4,
+  0xcd,0xd5,0xdc,0x73,0x87,0xfe,0x2d,0xd5,0xd5,0xe6,0x8a,0xd1,0x52,0x34,0x4a,0xa8,
+  0xf5,0x5d,0xaf,0x44,0x40,0xc7,0x6f,0x8f,0xa8,0x48,0x02,0x63,0xac,0x30,0xa6,0x6a,
+  0x14,0x42,0x12,0x7b,0x00,0x40,0x43,0x56,0x9f,0x6f,0x51,0xe6,0xb7,0x5c,0x8a,0x6d,
+  0x0a,0x37,0x2b,0x7a,0x8b,0x37,0xd9,0xb0,0xe2,0x9b,0xeb,0xf1,0x4a,0x9e,0xbe,0x38,
+  0xaa,0xd1,0x42,0xfb,0x19,0x4a,0xa5,0xd2,0xb7,0xa0,0x89,0x96,0xa0,0x01,0x8b,0xa1,
+  0x90,0xba,0xd8,0x95,0x08,0xdc,0x4e,0x15,0xc3,0x9e,0xaf,0x1c,0x69,0x11,0x6d,0x8a,
+  0x15,0x97,0xba,0x2c,0x63,0xab,0x6b,0xb1,0x74,0x3d,0x8d,0x30,0x03,0xac,0x0f,0xf5,
+  0xbb,0x14,0xba,0x48,0x6f,0x52,0x15,0xbf,0x0b,0xa8,0xa1,0x6b,0x51,0x85,0x14,0x2a,
+  0x2d,0x8b,0xd0,0x60,0x73,0x28,0xbe,0x6b,0xb1,0xfc,0x4d,0xfa,0x66,0xec,0xca,0x52,
+  0xaf,0x6d,0xa8,0x39,0x68,0x28,0x68,0x94,0x1a,0x21,0x6b,0x5c,0x8b,0x5d,0xf7,0xd0,
+  0x3b,0x63,0xdf,0x2e,0x75,0xad,0x45,0xe3,0xdd,0xf4,0x3f,0xa8,0x25,0xfb,0x73,0xf1,
+  0x69,0xe8,0xdf,0x56,0x4b,0xec,0xb5,0x73,0x5d,0x04,0x57,0xc1,0xbb,0xb1,0xaf,0x95,
+  0xe6,0xef,0x47,0xe3,0xce,0x13,0x57,0xa9,0x68,0x34,0xb7,0xdc,0x19,0x43,0xc3,0xb4,
+  0xc6,0x75,0xdd,0xe2,0x9c,0xb9,0x78,0xa5,0xa1,0xf4,0xf6,0xfd,0x68,0x78,0x97,0xc9,
+  0x77,0x14,0xee,0x57,0xae,0x6c,0xcf,0x8b,0x7d,0xfb,0x0e,0xa0,0xd6,0xb8,0x80,0x48,
+  0xcd,0xf8,0xe4,0x09,0xae,0x2f,0x7c,0x98,0x77,0xea,0x5f,0xc3,0xb9,0xe0,0x57,0x70,
+  0xc5,0x51,0x6b,0x5c,0x52,0x8e,0xb4,0x8c,0xde,0x81,0x2f,0x1a,0x8e,0xbd,0xac,0xe5,
+  0x8e,0xe1,0x6f,0x2d,0x74,0x6d,0x74,0x2d,0x6b,0x89,0xc6,0x2e,0x29,0xc5,0x36,0x86,
+  0xf8,0x2e,0xa3,0xa4,0x59,0xba,0x13,0x8a,0xa0,0xd8,0x74,0x35,0x4b,0x4b,0xe2,0xdf,
+  0xe6,0x06,0xc6,0x18,0xdf,0x26,0xce,0xfa,0x72,0x45,0x80,0xcd,0xa0,0x35,0x5f,0xaa,
+  0x9e,0xe3,0x66,0xc6,0x36,0x34,0x0a,0x9c,0xb9,0xb8,0x2e,0x82,0xd3,0xa4,0xea,0x8b,
+  0xd5,0xc2,0x56,0x34,0xb0,0xf1,0x6c,0x66,0x6c,0x63,0xb3,0x5c,0x98,0x69,0x53,0x66,
+  0xb4,0x34,0x85,0x6e,0xf7,0x96,0x44,0x24,0xc3,0xbc,0xad,0xac,0x58,0x65,0x46,0x87,
+  0xc1,0xde,0x0d,0xc3,0x19,0x17,0xce,0xe7,0x6d,0x7a,0x89,0xd7,0x15,0x91,0x9a,0xcc,
+  0xdb,0x42,0x25,0x95,0xed,0x0d,0x52,0x13,0x6d,0xd4,0x0b,0xbd,0x0a,0x88,0x98,0x84,
+  0x7d,0xee,0xe2,0x2b,0x4c,0x52,0x15,0x43,0xc1,0xf5,0x25,0xe1,0x7b,0x6a,0x14,0xa3,
+  0x33,0x95,0xec,0xbf,0xe3,0x77,0x11,0x9d,0x52,0x5d,0xaf,0x54,0x09,0x21,0x68,0x80,
+  0xda,0xe1,0x27,0x4a,0x07,0x04,0xca,0xbc,0x5b,0xed,0xb5,0x7c,0x9d,0x91,0xcb,0xdc,
+  0xce,0x0f,0xd1,0xdb,0xe0,0x8b,0x73,0x0c,0xbe,0x95,0x53,0x4c,0xbf,0x11,0x9b,0x9b,
+  0x52,0xbf,0x05,0xc5,0x76,0x9f,0xd7,0x18,0x12,0xdb,0x27,0xc1,0x0e,0x24,0x46,0xdf,
+  0x72,0x27,0x7c,0x8d,0xe4,0x51,0xb9,0xf9,0xea,0xa8,0xfa,0x2d,0x32,0x95,0x3a,0xdf,
+  0x96,0xa3,0x4b,0x5e,0xec,0xb9,0x66,0xa2,0x81,0x6f,0x62,0x85,0x96,0xd2,0x63,0xd1,
+  0x8e,0x52,0x99,0xa8,0x4e,0x1b,0x0d,0xbd,0x43,0x3e,0xb6,0x81,0x7e,0xa8,0x60,0x47,
+  0xcc,0xfb,0x69,0x3f,0xcc,0xd0,0x54,0x76,0xb6,0x9f,0xd3,0x46,0x91,0xca,0x60,0x89,
+  0xe1,0x2f,0x56,0xfa,0xa4,0xb2,0x45,0x4b,0x9a,0x6e,0x2d,0x56,0x7e,0x37,0xe3,0xea,
+  0xd4,0x92,0xa6,0xa2,0xcb,0x9c,0x39,0x85,0x72,0xd7,0x8a,0x9e,0x3f,0x0f,0x5d,0xb2,
+  0xa1,0x64,0x07,0x37,0xbe,0xb5,0xa1,0x64,0xbb,0xeb,0x6f,0xe8,0x0d,0xa1,0x4b,0x1e,
+  0x93,0x9c,0x36,0xa5,0xf8,0x5d,0x79,0xe8,0xe2,0x20,0x0e,0x33,0xd9,0x77,0x69,0x68,
+  0xcc,0x47,0xa7,0x47,0x0c,0xcd,0x69,0xa3,0x2a,0x77,0x15,0x96,0x2a,0x8b,0xa5,0xc2,
+  0x8e,0xc6,0x58,0x61,0x69,0xfb,0xe2,0x42,0x34,0x42,0x85,0x6a,0x7b,0x8e,0xb4,0x29,
+  0x33,0xae,0x45,0x4d,0x85,0xb7,0x29,0xb7,0x4b,0x25,0xc6,0xa2,0x26,0xed,0x36,0xa5,
+  0x84,0x19,0x9a,0x66,0xe0,0x15,0x97,0xe1,0xdc,0xa7,0x2c,0xc2,0x6b,0xaf,0x6b,0xa2,
+  0x68,0xdc,0x46,0x8a,0xd1,0x91,0x6d,0x8b,0xa0,0x47,0x43,0xc3,0xb9,0x8d,0xdb,0x45,
+  0xa8,0x91,0x44,0x72,0xcd,0x0c,0xe4,0x7e,0xb3,0xc1,0xbd,0x08,0x8d,0x5d,0x5a,0xa5,
+  0xd3,0x04,0xbc,0xf2,0xad,0xf0,0xa6,0xb9,0x2c,0xa4,0x32,0xa3,0xdd,0xbc,0x32,0xac,
+  0x36,0x7e,0xe3,0x56,0x5d,0x49,0x95,0x84,0xb6,0x66,0xbe,0x8b,0x41,0x40,0xfc,0xdb,
+  0xba,0x2b,0x25,0xad,0x82,0x77,0xe1,0x1f,0x94,0x7f,0x46,0x50,0x28,0x7b,0xb7,0xfd,
+  0xaf,0xf5,0x12,0xd3,0x6e,0x23,0x43,0xb4,0x57,0x0b,0x29,0xde,0x65,0xe5,0x60,0xf4,
+  0xf9,0xe7,0x2a,0xde,0xb2,0x72,0xcd,0x30,0xfd,0xa1,0x76,0x6f,0xe6,0xe5,0xa8,0x1f,
+  0x5b,0x3a,0xf6,0xc6,0xd8,0x99,0xb1,0xf3,0x93,0x0d,0xf8,0xaf,0x7c,0x16,0xbc,0xe3,
+  0x59,0xd0,0xfb,0x5a,0x72,0xef,0xca,0xa0,0x30,0xc6,0x86,0x82,0xef,0x2d,0x1d,0x7b,
+  0xfd,0x3d,0x34,0x9c,0x36,0x57,0xd4,0x2e,0x39,0x5a,0x34,0xaf,0xef,0xf0,0xc9,0x79,
+  0xc2,0x18,0x3b,0x39,0xaf,0x1e,0xbf,0xab,0x1e,0x8d,0x4c,0x7f,0x4a,0x6f,0x7e,0x75,
+  0xf3,0xdc,0xf6,0x07,0xce,0x5e,0x53,0x1a,0x3d,0x5e,0xb4,0xaf,0x7d,0xc3,0xbd,0xd7,
+  0xac,0x8e,0xee,0x2f,0xda,0x33,0xb0,0x61,0x99,0xd3,0xc6,0x45,0x9a,0x8d,0xa9,0xcd,
+  0x57,0x28,0x79,0xaf,0xc0,0x3d,0x68,0x2c,0xb0,0x0c,0xed,0x8a,0xe2,0x4b,0x9d,0xb1,
+  0x2b,0x36,0x1c,0xf7,0x7d,0x8d,0x19,0x45,0xda,0xed,0x7d,0xae,0x7b,0xa4,0x77,0xf1,
+  0xca,0x34,0xa7,0x0d,0xc7,0x65,0xc8,0xe0,0xb2,0xaa,0xac,0x15,0x06,0x28,0xd4,0xb9,
+  0x8f,0x80,0x51,0x90,0xda,0x61,0x99,0x54,0x6a,0x2c,0x06,0x89,0x2a,0xcb,0xd8,0x15,
+  0x35,0xf3,0x8e,0xb9,0x95,0x55,0xd2,0x54,0xfa,0x0d,0x5d,0x3b,0x64,0x19,0x85,0x29,
+  0x65,0xd5,0x22,0x66,0x48,0xce,0x77,0x81,0x05,0xc7,0xf8,0x86,0xa3,0x03,0x61,0x37,
+  0x6c,0xb5,0xef,0xec,0xdc,0xa7,0x50,0x29,0x97,0xf2,0x4c,0x84,0xe3,0x2d,0x4a,0x85,
+  0xc4,0x5e,0x5a,0x2d,0xae,0xcc,0x68,0x51,0x69,0xa4,0x39,0xb3,0x2e,0xca,0xe1,0x86,
+  0x1e,0x7f,0xa2,0x71,0x57,0xe1,0xdd,0x10,0xe5,0xbf,0xe9,0x5a,0x88,0xfc,0xde,0xf4,
+  0x0f,0x37,0xee,0xb2,0xe7,0x54,0x35,0x55,0x28,0xa2,0x8a,0x89,0x30,0xb2,0x44,0x38,
+  0x33,0x06,0x62,0xb7,0x82,0x62,0x4a,0xf3,0x25,0xc3,0x72,0x1b,0x66,0x31,0x14,0x02,
+  0xdb,0x03,0x28,0x15,0x23,0x60,0x16,0xd2,0x9c,0x52,0xec,0xcb,0x75,0x2e,0x05,0x9d,
+  0x80,0x24,0xc2,0x3a,0xbc,0x8f,0x81,0xab,0xa5,0x5d,0x42,0x7f,0xc1,0x96,0x0d,0xeb,
+  0x81,0xca,0x16,0x6d,0x3b,0x94,0x29,0x6a,0xa6,0x4d,0x71,0xcc,0xb5,0x15,0x22,0xec,
+  0x16,0x31,0xb2,0x95,0x23,0x4f,0x8e,0x80,0xa0,0x32,0x0b,0xbf,0x34,0xc9,0xc0,0x91,
+  0x6e,0x65,0xcb,0x8f,0x92,0xbb,0xa0,0x94,0xe6,0x40,0x5e,0x87,0xc2,0xc6,0x3e,0x13,
+  0x2e,0x6d,0x15,0x31,0xb6,0x71,0x9d,0x83,0xcb,0xbd,0x8e,0xa1,0x84,0x5a,0x36,0x30,
+  0xc3,0xf2,0xf3,0x06,0xa8,0x1c,0x8e,0x1d,0x5c,0x96,0x81,0xff,0xce,0xab,0x30,0xc4,
+  0xb8,0x0c,0xf0,0x40,0x88,0x7a,0xcb,0x64,0x15,0x0e,0x41,0xa8,0xc7,0x1b,0x6a,0x50,
+  0x0d,0xfe,0xcb,0x70,0xba,0xac,0x2a,0x20,0xfc,0x98,0x71,0x5d,0x83,0xd2,0x8c,0x6e,
+  0x19,0xfd,0x73,0x9b,0xd2,0xdc,0x53,0x1a,0x62,0x06,0xc4,0x7a,0xd8,0x15,0x89,0x8a,
+  0x7d,0xeb,0x86,0x14,0x11,0xf1,0x88,0x85,0xcb,0xf8,0xcf,0xd1,0x08,0xa1,0xe7,0x67,
+  0xb8,0x2c,0xda,0x34,0x49,0x11,0xee,0xde,0x2d,0x3f,0xcf,0xfa,0x5c,0x88,0x6d,0xb8,
+  0xe7,0xb7,0xe7,0xd4,0xb8,0xce,0xc0,0xf1,0x17,0xc3,0x75,0x50,0x68,0x08,0x37,0x0d,
+  0xc5,0x80,0xb4,0xcb,0xc0,0x5b,0x14,0x46,0xc4,0xb8,0xa2,0xf8,0x0e,0x2c,0xa2,0x5a,
+  0x4c,0x29,0x95,0xf6,0xdb,0x86,0x73,0xc5,0x9a,0xd3,0x28,0x10,0x01,0xc7,0x38,0x03,
+  0x92,0x30,0x10,0x97,0xa1,0x85,0x1b,0x16,0x2e,0x1b,0xd7,0x39,0x70,0xbc,0x9f,0x1b,
+  0x57,0x95,0xe6,0xdb,0x57,0xf2,0x6d,0x4c,0x91,0x16,0x2b,0xf7,0xb4,0x4c,0x8d,0xe5,
+  0x96,0x22,0x8c,0xde,0x43,0x1f,0x8d,0xfd,0x35,0x7e,0x29,0x61,0x57,0xbe,0x51,0x2a,
+  0x99,0xa2,0xce,0x68,0x48,0x8b,0x81,0xfd,0xe9,0x0a,0x35,0x4f,0xb4,0xc9,0x2d,0xcd,
+  0xe3,0x00,0x1d,0xbb,0xa2,0x34,0xcf,0x7a,0x9f,0x9b,0x2c,0x5c,0xfe,0x76,0x69,0xc9,
+  0x7e,0x05,0x71,0x19,0x01,0x1a,0x8d,0x7b,0x5a,0x1e,0x65,0x57,0x7a,0xed,0xf9,0xf2,
+  0x43,0x05,0xbd,0x9e,0x2d,0xab,0xcd,0x88,0xcb,0x77,0xe8,0x5f,0x8b,0xe2,0x42,0x9b,
+  0xcf,0xae,0x44,0x15,0x6a,0xf5,0x19,0xc7,0x8e,0x51,0x5e,0x2c,0xa7,0x54,0x5a,0xab,
+  0x94,0x21,0x1c,0x2f,0x66,0xc6,0x32,0x71,0xc5,0x7e,0xe7,0xaf,0x8b,0x29,0xab,0xa5,
+  0xe9,0x52,0x43,0xab,0x96,0x46,0xe3,0x06,0x68,0xa0,0xdc,0x98,0x0e,0xdf,0xa0,0x9a,
+  0x85,0xcb,0x86,0x74,0x0b,0x2c,0xa7,0x97,0xb2,0xd9,0xd9,0x2c,0x26,0x2e,0x8a,0xf3,
+  0xc5,0xae,0xe4,0x44,0xed,0xb5,0x63,0xf0,0xf9,0x52,0x13,0x62,0xbe,0xd6,0xe0,0xc4,
+  0x55,0xf2,0x89,0x13,0xb8,0x6c,0xcf,0x57,0x04,0x8c,0x16,0x2d,0x74,0x9d,0xb7,0x10,
+  0x0d,0x53,0x0b,0xb9,0xb8,0x41,0x35,0xbd,0xd1,0x5b,0x68,0xd8,0xe3,0x62,0xb8,0x5c,
+  0x9c,0x70,0x79,0x59,0x40,0x6c,0x16,0x87,0x5c,0x95,0x52,0x03,0xbb,0xa2,0xe3,0x15,
+  0xc3,0xba,0x0f,0x62,0x4a,0x04,0xe7,0x59,0x91,0x18,0x2e,0x5b,0x00,0x0d,0x11,0x09,
+  0x01,0x1a,0x67,0xcb,0x9e,0xaf,0x08,0x81,0x2c,0x5c,0x4e,0xe8,0xaa,0xda,0x8a,0x57,
+  0x3a,0xd8,0x15,0xb0,0xc7,0x65,0x28,0x76,0x40,0xc7,0x8d,0xbf,0xca,0xac,0xaf,0x42,
+  0x6a,0xcf,0x17,0x2b,0x0a,0x3c,0x0c,0x33,0x8d,0x3c,0x8a,0x78,0x3a,0x0d,0x72,0xd1,
+  0x50,0x7e,0x80,0xab,0x65,0xa6,0x71,0xbd,0x33,0xae,0x58,0x4e,0xa5,0x54,0xc0,0x1f,
+  0x5d,0x4e,0xa5,0xeb,0x32,0x58,0x8c,0x46,0xf1,0x0a,0x69,0xbd,0xd6,0xe0,0x3c,0xc3,
+  0x26,0x8c,0x1d,0x74,0xc3,0xdb,0x24,0x6f,0x81,0x1e,0x28,0x6b,0x42,0x00,0x2b,0x61,
+  0x86,0xa1,0x6a,0x72,0x09,0x98,0xf6,0xb8,0x14,0x28,0x83,0xfc,0x45,0xf2,0x6d,0xd0,
+  0x07,0x33,0x16,0xe5,0x37,0x35,0x34,0xc1,0x2b,0x70,0x25,0xa8,0x4d,0x78,0xa5,0xd7,
+  0x5e,0xcb,0x0d,0x0a,0xae,0xa6,0xe6,0xc5,0x5e,0x5c,0x5f,0xdc,0x98,0x2a,0xd6,0x57,
+  0x08,0x0d,0xea,0x8c,0x0b,0xb8,0x5f,0x09,0xe1,0xec,0x94,0x1b,0x2a,0xfb,0x79,0x21,
+  0xca,0xe4,0x68,0x40,0x2a,0x90,0x50,0x5a,0xf3,0x15,0x6d,0xe4,0xb8,0xac,0x09,0x5c,
+  0x56,0x18,0x2e,0x1b,0x77,0x49,0x08,0xd0,0x52,0xa1,0xdd,0xe6,0x3a,0xc3,0x68,0x2a,
+  0x2c,0x5e,0x7c,0xdd,0xa2,0x4d,0x86,0xd9,0xa4,0x15,0x17,0xbb,0xa4,0x42,0xe3,0x3a,
+  0x68,0x2a,0x56,0xd8,0x8a,0x73,0xfc,0x46,0x22,0x82,0x5e,0xc4,0xc5,0x03,0xed,0xd2,
+  0xe2,0xb5,0x2e,0x1d,0x5f,0xb4,0x48,0xa9,0x86,0x93,0x8f,0xfe,0x50,0xcc,0x98,0xe1,
+  0xee,0x41,0x5c,0x4e,0x08,0x5c,0x6e,0x81,0x84,0x81,0x86,0x44,0x5a,0x8c,0x04,0xc7,
+  0x65,0xf1,0x9c,0xaf,0xbb,0xe9,0xe5,0x5b,0x63,0x6f,0xf6,0x97,0xcd,0x57,0xf3,0x8b,
+  0x6e,0x35,0xda,0xd1,0xc8,0xbb,0x49,0xbe,0xd5,0x78,0xb3,0xff,0xca,0xf9,0xaa,0xe1,
+  0x8c,0x6b,0x6d,0xf3,0x8c,0xa9,0xad,0xb9,0x4a,0xa1,0x59,0x81,0x58,0x00,0xdf,0x28,
+  0x2b,0x49,0x91,0x55,0x85,0x53,0xdb,0x11,0x14,0x4c,0x7b,0x35,0x97,0x0b,0x5c,0x5e,
+  0xb2,0xac,0xbc,0x34,0xba,0xdf,0x3f,0xb7,0x7d,0x03,0x1a,0x06,0x37,0xfe,0xfb,0x71,
+  0xb9,0x6a,0xec,0xc6,0x9f,0xbc,0x3c,0x76,0xe6,0xdc,0xca,0xaa,0xb1,0xa5,0xfb,0xde,
+  0xf8,0xe4,0x4c,0x06,0x97,0x33,0xf7,0x99,0x37,0xb6,0x64,0xac,0x68,0xec,0xcc,0xe8,
+  0xc9,0x79,0x63,0x4b,0x8f,0xbe,0x71,0xfa,0x4c,0x06,0x97,0x33,0x6d,0xae,0xe1,0xb8,
+  0x3c,0x20,0x70,0xd9,0x7f,0x15,0xc7,0xe5,0x9b,0x19,0x2e,0x3f,0x70,0xd6,0x69,0x43,
+  0xda,0x61,0x1b,0x54,0x1a,0xee,0xa9,0xbd,0x96,0xa1,0xb1,0x2b,0x87,0x99,0xe1,0xb4,
+  0x41,0xbf,0xe5,0x38,0xb0,0x09,0x46,0xa6,0xd3,0xed,0xec,0x55,0xe0,0xe8,0x33,0xc9,
+  0x70,0x3e,0xdc,0xed,0x19,0x30,0xd5,0xb4,0x0c,0xbe,0xc6,0x0e,0x73,0xc3,0xf9,0x50,
+  0xf1,0x92,0x4d,0x36,0xbc,0xa6,0xd3,0xe7,0x2f,0x6f,0x65,0xf7,0x98,0x31,0x78,0xfe,
+  0xeb,0xc3,0x20,0x8e,0xa1,0xc8,0x6e,0x4a,0xec,0x36,0x17,0xfd,0x1a,0x6e,0x78,0x7b,
+  0xed,0x36,0xee,0x76,0xb2,0x0d,0x76,0x19,0xb3,0x35,0xf7,0xba,0x30,0x37,0xa6,0x1e,
+  0xb4,0xaf,0x90,0x3f,0xfd,0xf9,0xa8,0x93,0x9f,0x4f,0xe6,0x8a,0xdd,0x1f,0x0d,0x72,
+  0x43,0xf8,0x34,0xbe,0x8f,0xcf,0x87,0x1b,0xce,0xf3,0xf9,0x3e,0x30,0x99,0x85,0x75,
+  0x9f,0x75,0xa1,0x2f,0x7b,0xce,0x4e,0x7f,0xb0,0xf1,0x7f,0xf2,0x7c,0xf8,0x7c,0x7d,
+  0xc9,0x73,0x76,0x5a,0x68,0xac,0x46,0xf7,0x65,0x1f,0x91,0xd3,0xfb,0x53,0x3e,0xb5,
+  0xb5,0x7f,0xe4,0x8f,0x3e,0xdf,0x9f,0x7a,0x9b,0xff,0xc6,0x4f,0xfd,0xd8,0xd8,0x98,
+  0x79,0x71,0xe3,0xff,0xd3,0x6d,0x48,0xf6,0x12,0x1e,0x6f,0x64,0x1a,0x89,0xa5,0x37,
+  0xf1,0x5d,0x1d,0xbf,0x06,0xff,0x0b,0x6b,0x59,0xbb,0x88,0xe1,0x7c,0xbe,0x74,0x2d,
+  0xdb,0x0d,0xbe,0x7c,0x05,0x66,0x5a,0xa9,0x99,0x25,0xac,0x4e,0x58,0xd4,0x81,0x3f,
+  0x65,0x2d,0x67,0xda,0x88,0xb5,0xfc,0x7d,0x5c,0xcb,0xd6,0x12,0x9e,0xb4,0x96,0xd5,
+  0x3f,0xb6,0x96,0x9d,0x36,0x7f,0xe4,0xf9,0x8c,0x5b,0xcb,0xc0,0xd7,0xb2,0xb5,0x84,
+  0xad,0x45,0x8d,0x46,0xaf,0xf2,0x27,0xdf,0xe7,0x4f,0xf1,0x75,0x7f,0xca,0x73,0x86,
+  0x0c,0x71,0xbe,0xc8,0xe7,0xab,0xb5,0xfc,0xff,0xbe,0x36,0xff,0xf9,0x27,0x04,0xba,
+  0x44,0xf8,0xff,0x46,0xae,0xff,0x2f,0xfe,0xd3,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c,
+  0xf5,0xf9,0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0x5f,0x7c,0x78,0xbc,0x44,
+  0x78,0xbc,0x64,0xfc,0x3f,0xdd,0x97,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c,0xf5,0xf9,
+  0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0xbb,0x3f,0x21,0x2e,0x0c,0x7b,0xa3,
+  0x36,0x04,0xbc,0xa8,0x2b,0x87,0xc0,0xc8,0xfb,0xd3,0xfe,0x1d,0x6f,0xef,0x0a,0x41,
+  0x42,0xca,0xdc,0xa7,0xe7,0x1f,0x27,0xf6,0xf5,0xff,0x02,0xd6,0x2c,0x67,0x26,0xbd,
+  0xa4,0x00,0x00,
diff --git a/u-boot/board/esd/cpci5200/Makefile b/u-boot/board/esd/cpci5200/Makefile
new file mode 100644
index 0000000..d41cbcd
--- /dev/null
+++ b/u-boot/board/esd/cpci5200/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+# ifneq ($(OBJTREE),$(SRCTREE))
+# $(shell mkdir -p $(obj)../common/xilinx_jtag)
+# endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+#	  ../common/xilinx_jtag/micro.o \
+#	  ../common/xilinx_jtag/ports.o
+
+# COBJS	= $(BOARD).o flash.o $(CPLD)
+COBJS	= $(BOARD).o strataflash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/cpci5200/cpci5200.c b/u-boot/board/esd/cpci5200/cpci5200.c
new file mode 100644
index 0000000..abac217
--- /dev/null
+++ b/u-boot/board/esd/cpci5200/cpci5200.c
@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpci5200.c - main board support/init for the esd cpci5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_ata_reset(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_ata_reset();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPCI5200 (cpci5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+	}
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_ata_reset(void)
+{
+	debug("init_ata_reset\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	   "Write some data to pcibus",
+	   "<addr> <size>\n"
+	   ""
+);
diff --git a/u-boot/board/esd/cpci5200/mt46v16m16-75.h b/u-boot/board/esd/cpci5200/mt46v16m16-75.h
new file mode 100644
index 0000000..cf63806
--- /dev/null
+++ b/u-boot/board/esd/cpci5200/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/esd/cpci5200/strataflash.c b/u-boot/board/esd/cpci5200/strataflash.c
new file mode 100644
index 0000000..9b578b5
--- /dev/null
+++ b/u-boot/board/esd/cpci5200/strataflash.c
@@ -0,0 +1,804 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char *cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset,
+			 uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+			       cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 8) |
+		addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 24) |
+		(addr[(info->portwidth) - 1] << 16) |
+		(addr[(4 * info->portwidth) - 1] << 8) |
+		addr[(3 * info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size;
+	int i;
+	unsigned long address;
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CONFIG_SYS_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CONFIG_SYS_FLASH_INCREMENT;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf
+			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			     i, flash_info[0].size, flash_info[i].size << 20);
+		}
+	}
+
+#if 0				/* test-only */
+	/* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for (i = 0;
+	     flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
+	     i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth << 3), (info->chipwidth << 3));
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	printf
+	    (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	     info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
+	     info->buffer_size);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n");
+		printf(" %08lX%5s",
+		       info->start[i], info->protect[i] ? " (RO)" : " ");
+	}
+	printf("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while (cnt >= info->portwidth) {
+		i = info->buffer_size > cnt ? cnt : info->buffer_size;
+		if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	/* handle the aligned part */
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif				/* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check(info, sector, info->erase_blk_tout,
+				     prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			int i;
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
+			      char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer(0);
+	while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt,
+			       info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if ((retcode == ERR_OK)
+	    && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,
+		       info->start[sector]);
+		if (flash_isset
+		    (info, sector, 0,
+		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+			printf("Command Sequence Error.\n");
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
+{
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *) cmdbuf;
+	for (i = 0; i < info->portwidth; i++)
+		*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+					FLASH_CMD_CFI);
+			if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
+					     'R')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
+					     'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio = 0;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+#if 0
+	invalidate_dcache_range(base, base + 0x400);
+#endif
+	if (flash_detect_cfi(info)) {
+
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions =
+		    flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp =
+			    flash_read_long(info, 0,
+					    FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size =
+			    (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) + 1;
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] =
+				    flash_isset(info, sect_cnt,
+						FLASH_OFFSET_PROTECT,
+						FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+		    (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+		    size_ratio;
+		info->buffer_size =
+		    (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
+		    1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+#ifdef DEBUG_FLASH
+	printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
+#endif
+#ifdef DEBUG_FLASH
+	printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+	printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t * info, ulong addr)
+{
+	int sector;
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					  "write to buffer")) == ERR_OK) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0,
+				FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+		    flash_full_status_check(info, sector,
+					    info->buffer_write_tout,
+					    "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif				/* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/u-boot/board/esd/cpci750/64360.h b/u-boot/board/esd/cpci750/64360.h
new file mode 100644
index 0000000..262abf3
--- /dev/null
+++ b/u-boot/board/esd/cpci750/64360.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ * for cpci750 Reinhard Arlt
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the cpci750.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */
diff --git a/u-boot/board/esd/cpci750/Makefile b/u-boot/board/esd/cpci750/Makefile
new file mode 100644
index 0000000..4c9275b
--- /dev/null
+++ b/u-boot/board/esd/cpci750/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../Marvell/common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	= misc.o
+
+COBJS	= $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
+	  mv_eth.o  mpsc.o i2c.o \
+	  sdram_init.o ide.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/cpci750/cpci750.c b/u-boot/board/esd/cpci750/cpci750.c
new file mode 100644
index 0000000..f27d65e
--- /dev/null
+++ b/u-boot/board/esd/cpci750/cpci750.c
@@ -0,0 +1,1103 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
+ */
+
+/*
+ * cpci750.c - main board support/init for the esd cpci750.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
+				     {"PCI0DLL_1     "},  /* 30 */
+				     {"PCI0DLL_0     "},  /* 29 */
+				     {"PCI1DLL_2     "},  /* 28 */
+				     {"PCI1DLL_1     "},  /* 27 */
+				     {"PCI1DLL_0     "},  /* 26 */
+				     {"BbEP2En       "},  /* 25 */
+				     {"SDRAMRdDataDel"},  /* 24 */
+				     {"SDRAMRdDel    "},  /* 23 */
+				     {"SDRAMSync     "},  /* 22 */
+				     {"SDRAMPipeSel_1"},  /* 21 */
+				     {"SDRAMPipeSel_0"},  /* 20 */
+				     {"SDRAMAddDel   "},  /* 19 */
+				     {"SDRAMClkSel   "},  /* 18 */
+				     {"Reserved(1!)  "},  /* 17 */
+				     {"PCIRty        "},  /* 16 */
+				     {"BootCSWidth_1 "},  /* 15 */
+				     {"BootCSWidth_0 "},  /* 14 */
+				     {"PCI1PadsCal   "},  /* 13 */
+				     {"PCI0PadsCal   "},  /* 12 */
+				     {"MultiMVId_1   "},  /* 11 */
+				     {"MultiMVId_0   "},  /* 10 */
+				     {"MultiGTEn     "},  /* 09 */
+				     {"Int60xArb     "},  /* 08 */
+				     {"CPUBusConfig_1"},  /* 07 */
+				     {"CPUBusConfig_0"},  /* 06 */
+				     {"DefIntSpc     "},  /* 05 */
+				     {0               },  /* 04 */
+				     {"SROMAdd_1     "},  /* 03 */
+				     {"SROMAdd_0     "},  /* 02 */
+				     {"DRAMPadCal    "},  /* 01 */
+				     {"SInitEn       "},  /* 00 */
+				     {0               },  /* 31 */
+				     {0               },  /* 30 */
+				     {0               },  /* 29 */
+				     {0               },  /* 28 */
+				     {0               },  /* 27 */
+				     {0               },  /* 26 */
+				     {0               },  /* 25 */
+				     {0               },  /* 24 */
+				     {0               },  /* 23 */
+				     {0               },  /* 22 */
+				     {"JTAGCalBy     "},  /* 21 */
+				     {"GB2Sel        "},  /* 20 */
+				     {"GB1Sel        "},  /* 19 */
+				     {"DRAMPLL_MDiv_5"},  /* 18 */
+				     {"DRAMPLL_MDiv_4"},  /* 17 */
+				     {"DRAMPLL_MDiv_3"},  /* 16 */
+				     {"DRAMPLL_MDiv_2"},  /* 15 */
+				     {"DRAMPLL_MDiv_1"},  /* 14 */
+				     {"DRAMPLL_MDiv_0"},  /* 13 */
+				     {"GB0Sel        "},  /* 12 */
+				     {"DRAMPLLPU     "},  /* 11 */
+				     {"DRAMPLL_HIKVCO"},  /* 10 */
+				     {"DRAMPLLNP     "},  /* 09 */
+				     {"DRAMPLL_NDiv_7"},  /* 08 */
+				     {"DRAMPLL_NDiv_6"},  /* 07 */
+				     {"CPUPadCal     "},  /* 06 */
+				     {"DRAMPLL_NDiv_5"},  /* 05 */
+				     {"DRAMPLL_NDiv_4"},  /* 04 */
+				     {"DRAMPLL_NDiv_3"},  /* 03 */
+				     {"DRAMPLL_NDiv_2"},  /* 02 */
+				     {"DRAMPLL_NDiv_1"},  /* 01 */
+				     {"DRAMPLL_NDiv_0"}}; /* 00 */
+
+extern flash_info_t flash_info[];
+
+extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+int display_mem_map (void);
+
+/*
+ * Skip video initialization on slave variant.
+ * This function will overwrite the weak default in cfb_console.c
+ */
+int board_video_skip(void)
+{
+	return CPCI750_SLAVE_TEST;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int data;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++) {
+		data = pciReadConfigReg(stat,
+					PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+					SELF);
+		data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, data);
+	}
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+
+	memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
+
+
+	/* configure device timing */
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
+
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CONFIG_SYS_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CONFIG_SYS_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
+		unsigned int flash_offset;
+		unsigned int l;
+
+		flash_offset =  CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
+		for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
+			if (flash_info[3].start[l] != 0) {
+			      flash_info[3].start[l] += flash_offset;
+			}
+		}
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len  - 1,
+			       &flash_info[3]);
+	}
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
+			      CONFIG_SYS_BOOT_SIZE);
+
+	display_mem_map ();
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+#ifdef CONFIG_PCI
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+#endif /* of CONFIG_PCI */
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- FLASH\n");
+		else if (i == 1)
+			printf ("\t- FLASH\n");
+		else if (i == 2)
+			printf ("\t- FLASH\n");
+		else
+			printf ("\t- RTC/REGS/CAN\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	volatile unsigned int *ptr;
+	int count = 0;
+	int count2 = 0;
+	int status;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+
+	/*
+	 * Mark sync address
+	 */
+	ptr = 0;
+	ptr[0] = 0xffffffff;
+	ptr[1] = 0xffffffff;
+	puts("\nWaiting for image from pci host -");
+
+	/*
+	 * Wait for host to write the start address
+	 */
+	while (*ptr == 0xffffffff) {
+		count++;
+		if (!(count % 100)) {
+			count2++;
+			putc(0x08); /* backspace */
+			putc(str[count2 % 4]);
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	sprintf(addr, "%08x", *ptr);
+	printf("\nBooting Image at addr 0x%s ...\n", addr);
+	setenv("loadaddr", addr);
+
+	switch (ptr[1] == 0) {
+	case 0:
+		/*
+		 * Boot image via bootm
+		 */
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootm (cmdtp, 0, 1, local_args);
+		break;
+	case 1:
+		/*
+		 * Boot image via bootvx
+		 */
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootvx (cmdtp, 0, 1, local_args);
+		break;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"loadpci - Wait for pci-image and boot it\n",
+	NULL
+	);
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CONFIG_SYS_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0		*/
+	return;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaLL,
+	0xccccccccccccccccLL,
+	0xf0f0f0f0f0f0f0f0LL,
+	0xff00ff00ff00ff00LL,
+	0xffff0000ffff0000LL,
+	0xffffffff00000000LL,
+	0x00000000ffffffffLL,
+	0x0000ffff0000ffffLL,
+	0x00ff00ff00ff00ffLL,
+	0x0f0f0f0f0f0f0f0fLL,
+	0x3333333333333333LL,
+	0x5555555555555555LL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;		*/
+		/* lo = temp64 & 0xffffffff;			*/
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo);	*/
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
+
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
+
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata    = 0;
+	int runaddress = 0;
+	int runwalk    = 0;
+
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+#endif
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+	}
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function		*/
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.						*/
+/*  - we diable and invalidate the icache and dcache.			*/
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+/*	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
+/*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
+
+	icache_disable ();
+	dcache_disable ();
+}
+
+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int reset_sample_low;
+	unsigned int reset_sample_high;
+	unsigned int l, l1, l2;
+
+	GT_REG_READ(0x3c4, &reset_sample_low);
+	GT_REG_READ(0x3d4, &reset_sample_high);
+	printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+
+	l2 = 0;
+	for (l=0; l<63; l++) {
+		if (show_config_tab[l][0] != 0) {
+			printf("%14s:%1x ", show_config_tab[l],
+			       ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
+			l2++;
+			if ((l2 % 4) == 0)
+				printf("\n");
+		} else {
+			l1++;
+		}
+		if (l == 32)
+			reset_sample_low = reset_sample_high;
+	}
+	printf("\n");
+
+	return(0);
+}
+
+U_BOOT_CMD(
+	show_config,	1,	1,	do_show_config,
+	"Show Marvell strapping register",
+	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
+);
+
+int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pldver, 1, 1, do_pldver,
+	"Show PLD version",
+	"Show PLD version)");
diff --git a/u-boot/board/esd/cpci750/eth.h b/u-boot/board/esd/cpci750/eth.h
new file mode 100644
index 0000000..aab32d2
--- /dev/null
+++ b/u-boot/board/esd/cpci750/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/u-boot/board/esd/cpci750/i2c.c b/u-boot/board/esd/cpci750/i2c.c
new file mode 100644
index 0000000..b752903
--- /dev/null
+++ b/u-boot/board/esd/cpci750/i2c.c
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ * for cpci750 by reinhard.arlt@esd-electronics.com
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include <i2c.h>
+#include "../../Marvell/include/mv_gen_reg.h"
+#include "../../Marvell/include/core.h"
+
+#define I2C_DELAY	    100
+#undef	DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CONFIG_SYS_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+	/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+	asm(" sync");
+	GT_REG_WRITE (I2C_CONTROL, 0);
+	asm(" sync");
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	asm(" sync");
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+	asm(" sync");
+}
+
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	unsigned int control;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |=  (0x1 << 2);
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+
+	count = 0;
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to set startbit: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			asm(" sync");
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	DP (puts ("i2c_select_device:write addr byte\n"));
+
+	/* assert the address */
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write address: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		asm(" sync");
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		RESET_REG_BITS (I2C_CONTROL, BIT3);
+		asm(" sync");
+
+		/* Get and return the data */
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			if (count > 20) {
+#ifdef DEBUG_I2C
+				printf ("Failed to get data len status: 0x%02x\n", status);
+#endif
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	asm(" sync");
+	count = 0;
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	while ((status & 0xff) != 0x58) {
+		if (count > 2000) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+	asm(" sync");
+
+	return (0);
+}
+
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		count = 0;
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		count = 0;
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+	table[1] = (offset     ) & 0x0ff;	/* low byte */
+	table[0] = (offset >> 8) & 0x0ff;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+22		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+int
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device for data read: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not read: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+	asm(" sync");
+}
+
+
+int
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+		}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+		}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+
+int i2c_probe (uchar chip)
+{
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
diff --git a/u-boot/board/esd/cpci750/i2c.h b/u-boot/board/esd/cpci750/i2c.h
new file mode 100644
index 0000000..b669ff0
--- /dev/null
+++ b/u-boot/board/esd/cpci750/i2c.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/u-boot/board/esd/cpci750/ide.c b/u-boot/board/esd/cpci750/ide.c
new file mode 100644
index 0000000..a3bd1b7
--- /dev/null
+++ b/u-boot/board/esd/cpci750/ide.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* ide.c - ide support functions */
+
+
+#include <common.h>
+#if defined(CONFIG_CMD_IDE)
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
+
+int ide_preinit (void)
+{
+	int status;
+	pci_dev_t devbusfn;
+	int l;
+
+	status = 1;
+	if (CPCI750_SLAVE_TEST != 0)
+		return status;
+	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
+		ide_bus_offset[l] = -ATA_STATUS;
+	}
+	devbusfn = pci_find_device (0x1103, 0x0004, 0);
+	if (devbusfn == -1)
+	        devbusfn = pci_find_device (0x1095, 0x3114, 0);
+	if (devbusfn != -1) {
+		ulong *ide_bus_offset_ptr;
+
+		status = 0;
+
+		ide_bus_offset_ptr = &ide_bus_offset[0];
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+				       (u32 *)ide_bus_offset_ptr);
+		ide_bus_offset[0] &= 0xfffffffe;
+		ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
+		ide_bus_offset_ptr = &ide_bus_offset[1];
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
+				       (u32 *)ide_bus_offset_ptr);
+		ide_bus_offset[1] &= 0xfffffffe;
+		ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
+	}
+	return status;
+}
+
+void ide_set_reset (int flag) {
+	return;
+}
+
+#endif /* of CONFIG_CMDS_IDE */
diff --git a/u-boot/board/esd/cpci750/local.h b/u-boot/board/esd/cpci750/local.h
new file mode 100644
index 0000000..de3758a
--- /dev/null
+++ b/u-boot/board/esd/cpci750/local.h
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells PPCBoot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! PPCBOOT figures this out  based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+#define CONFIG_750FX       /* The 750FX doesn't support as many things in L2CR like 750CX*/
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CONFIG_SYS_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY  */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+/* #define CONFIG_ETHADDR          86:06:2d:7e:c6:53 */
+#define CONFIG_ETHADDR          64:36:00:00:00:01
+
+/* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		86:06:2d:7e:c6:54
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		86:06:2d:7e:c6:55
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
diff --git a/u-boot/board/esd/cpci750/misc.S b/u-boot/board/esd/cpci750/misc.S
new file mode 100644
index 0000000..233fd83
--- /dev/null
+++ b/u-boot/board/esd/cpci750/misc.S
@@ -0,0 +1,245 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../../Marvell/include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CONFIG_SYS_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
+	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
+	rlwinm  r3, r3, 16, 16, 31
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTEGRATED_SRAM_BASE_ADDR
+	stwbrx  r3, r5, r4
+
+2:	lwbrx	r6, r5, r4
+	cmp	cr0, r3, r6
+	bne	2b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
diff --git a/u-boot/board/esd/cpci750/mpsc.c b/u-boot/board/esd/cpci750/mpsc.c
new file mode 100644
index 0000000..c89426d
--- /dev/null
+++ b/u-boot/board/esd/cpci750/mpsc.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../../Marvell/include/memory.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64360 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/u-boot/board/esd/cpci750/mpsc.h b/u-boot/board/esd/cpci750/mpsc.h
new file mode 100644
index 0000000..aa0f862
--- /dev/null
+++ b/u-boot/board/esd/cpci750/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../../Marvell/include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/u-boot/board/esd/cpci750/mv_eth.c b/u-boot/board/esd/cpci750/mv_eth.c
new file mode 100644
index 0000000..781ad23
--- /dev/null
+++ b/u-boot/board/esd/cpci750/mv_eth.c
@@ -0,0 +1,3185 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64360_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64360_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64360_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64360_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64360 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64360_eth_real_open (struct eth_device *eth);
+static int mv64360_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64360_eth_update_stat (struct eth_device *dev);
+bool db64360_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64360_eth_receive (struct eth_device *dev);
+
+int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64360_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64360_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64360_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64360_eth
+ *
+ **********************************************************************/
+int db64360_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64360_eth_start (dev));
+}
+
+int db64360_eth_poll (struct eth_device *dev)
+{
+	return mv64360_eth_receive (dev);
+}
+
+int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64360_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64360_eth_disable (struct eth_device *dev)
+{
+	mv64360_eth_stop (dev);
+}
+
+
+void mv6436x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64360_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64360_eth_transmit;
+		dev->recv = (void *) db64360_eth_poll;
+
+		ethernet_private =
+			calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *) ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private =
+			calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64360_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64360_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64360_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64360_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64360_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64360_eth_open (struct eth_device *dev)
+{
+	return (mv64360_eth_real_open (dev));
+}
+
+/* Helper function for mv64360_eth_open */
+static int mv64360_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status, phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64360_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64360_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64360_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64360_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64360_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64360_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64360_eth_stop */
+
+static int mv64360_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64360_eth_free_tx_rings (dev);
+	mv64360_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64360_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64360_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64360_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64360_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64360_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64360_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64360_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64360_eth_start (struct eth_device *dev)
+{
+	return (mv64360_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ *	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/u-boot/board/esd/cpci750/mv_eth.h b/u-boot/board/esd/cpci750/mv_eth.h
new file mode 100644
index 0000000..b761135
--- /dev/null
+++ b/u-boot/board/esd/cpci750/mv_eth.h
@@ -0,0 +1,844 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64360_ETH_H__
+#define __DB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include <asm/errno.h>
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64360_TX_QUEUE_NUM 1
+#define MV64360_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#else
+#define MV64360_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#else
+#define MV64360_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64360_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64360_TX_BUFFER_SIZE 1600
+#endif
+
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64360_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+
+int mv64360_eth_init (struct eth_device *dev);
+int mv64360_eth_stop (struct eth_device *dev);
+int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64360_eth0_poll(); */
+
+int mv64360_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64360_ETH_ */
diff --git a/u-boot/board/esd/cpci750/mv_regs.h b/u-boot/board/esd/cpci750/mv_regs.h
new file mode 100644
index 0000000..0d6370b
--- /dev/null
+++ b/u-boot/board/esd/cpci750/mv_regs.h
@@ -0,0 +1,1124 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64360r.h - GT-64360 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64360
+
+/* Supported by the Atlantis */
+#define MV64360_INCLUDE_PCI_1
+#define MV64360_INCLUDE_PCI_0_ARBITER
+#define MV64360_INCLUDE_PCI_1_ARBITER
+#define MV64360_INCLUDE_SNOOP_SUPPORT
+#define MV64360_INCLUDE_P2P
+#define MV64360_INCLUDE_ETH_PORT_2
+#define MV64360_INCLUDE_CPU_MAPPING
+#define MV64360_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64360_CS_0_BASE_ADDR					    0x008
+#define MV64360_CS_0_SIZE					    0x010
+#define MV64360_CS_1_BASE_ADDR					    0x208
+#define MV64360_CS_1_SIZE					    0x210
+#define MV64360_CS_2_BASE_ADDR					    0x018
+#define MV64360_CS_2_SIZE					    0x020
+#define MV64360_CS_3_BASE_ADDR					    0x218
+#define MV64360_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64360_PCI_0_IO_SIZE					    0x050
+#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64360_PCI_1_IO_SIZE					    0x098
+#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64360_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64360_CPU_CONFIG					    0x000
+#define MV64360_CPU_MODE					    0x120
+#define MV64360_CPU_MASTER_CONTROL				    0x160
+#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64360_SMP_WHO_AM_I					    0x200
+#define MV64360_SMP_CPU0_DOORBELL				    0x214
+#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64360_SMP_CPU1_DOORBELL				    0x224
+#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64360_SMP_SEMAPHOR0					    0x244
+#define MV64360_SMP_SEMAPHOR1					    0x24c
+#define MV64360_SMP_SEMAPHOR2					    0x254
+#define MV64360_SMP_SEMAPHOR3					    0x25c
+#define MV64360_SMP_SEMAPHOR4					    0x264
+#define MV64360_SMP_SEMAPHOR5					    0x26c
+#define MV64360_SMP_SEMAPHOR6					    0x274
+#define MV64360_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64360_CPU_ERROR_DATA_LOW				    0x128
+#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64360_CPU_ERROR_PARITY				    0x138
+#define MV64360_CPU_ERROR_CAUSE					    0x140
+#define MV64360_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64360_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64360_SRAM_CONFIG					    0x380
+#define MV64360_SRAM_TEST_MODE					    0X3F4
+#define MV64360_SRAM_ERROR_CAUSE				    0x388
+#define MV64360_SRAM_ERROR_ADDR					    0x390
+#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64360_SDRAM_CONFIG					    0x1400
+#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64360_SDRAM_OPERATION					    0x1418
+#define MV64360_SDRAM_MODE					    0x141c
+#define MV64360_EXTENDED_DRAM_MODE				    0x1420
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64360_SDRAM_ERROR_ADDR				    0x1450
+#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64360_SDRAM_ECC_CONTROL				    0x1454
+#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64360_DFCDL_CONFIG0					    0x1480
+#define MV64360_DFCDL_CONFIG1					    0x1484
+#define MV64360_DLL_WRITE					    0x1488
+#define MV64360_DLL_READ					    0x148c
+#define MV64360_SRAM_ADDR					    0x1490
+#define MV64360_SRAM_DATA0					    0x1494
+#define MV64360_SRAM_DATA1					    0x1498
+#define MV64360_SRAM_DATA2					    0x149c
+#define MV64360_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64360_DUNIT_DEBUG_LOW					    0x1460
+#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64360_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64360_DEVICE_ERROR_DATA				    0x4dc
+#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64360_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64360_PCI_0_COMMAND					    0xc00
+#define MV64360_PCI_1_COMMAND					    0xc80
+#define MV64360_PCI_0_MODE					    0xd00
+#define MV64360_PCI_1_MODE					    0xd80
+#define MV64360_PCI_0_RETRY					    0xc04
+#define MV64360_PCI_1_RETRY					    0xc84
+#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_SERR_MASK					    0xc28
+#define MV64360_PCI_1_SERR_MASK					    0xca8
+#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_MMASK					    0X1D24
+#define MV64360_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64360_PCI_VPD_ADDR					    0x048
+#define MV64360_PCI_VPD_DATA					    0x04c
+#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64360_PCI_X_COMMAND					    0x060
+#define MV64360_PCI_X_STATUS					    0x064
+#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64360_ETH_PHY_ADDR_REG				    0x2000
+#define MV64360_ETH_SMI_REG					    0x2004
+#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64360_ETH_BAR_0					    0x2200
+#define MV64360_ETH_BAR_1					    0x2208
+#define MV64360_ETH_BAR_2					    0x2210
+#define MV64360_ETH_BAR_3					    0x2218
+#define MV64360_ETH_BAR_4					    0x2220
+#define MV64360_ETH_BAR_5					    0x2228
+#define MV64360_ETH_SIZE_REG_0					    0x2204
+#define MV64360_ETH_SIZE_REG_1					    0x220c
+#define MV64360_ETH_SIZE_REG_2					    0x2214
+#define MV64360_ETH_SIZE_REG_3					    0x221c
+#define MV64360_ETH_SIZE_REG_4					    0x2224
+#define MV64360_ETH_SIZE_REG_5					    0x222c
+#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64360_CUNIT_SIZE0					    0xf204
+#define MV64360_CUNIT_SIZE1					    0xf20c
+#define MV64360_CUNIT_SIZE2					    0xf214
+#define MV64360_CUNIT_SIZE3					    0xf21c
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64360_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64360_CUNIT_CONFIG_REG				    0xb40c
+#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64360_CUNIT_DEBUG_LOW					    0xf340
+#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64360_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64360_MPSC_ROUTING_REG				    0xb400
+#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64360_SDMA_CAUSE_REG					    0xb800
+#define MV64360_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64360_SDMA_SRAM_TARGET				    0x0003
+#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64360_PCI_0_TARGET					    0x0003
+#define MV64360_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64360_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64360_BRG_CAUSE_REG					    0xb834
+#define MV64360_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64360_DMA_SIZE_REG0					    0xa04
+#define MV64360_DMA_SIZE_REG1					    0xa0c
+#define MV64360_DMA_SIZE_REG2					    0xa14
+#define MV64360_DMA_SIZE_REG3					    0xa1c
+#define MV64360_DMA_SIZE_REG4					    0xa24
+#define MV64360_DMA_SIZE_REG5					    0xa2c
+#define MV64360_DMA_SIZE_REG6					    0xa34
+#define MV64360_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64360_DMA_ARBITER_CONTROL				    0x860
+#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64360_DMA_ERROR_ADDR					    0x8c8
+#define MV64360_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64360_DMA_DEBUG_LOW					    0x8e0
+#define MV64360_DMA_DEBUG_HIGH					    0x8e4
+#define MV64360_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64360_TIMER_COUNTER0					    0x850
+#define MV64360_TIMER_COUNTER1					    0x854
+#define MV64360_TIMER_COUNTER2					    0x858
+#define MV64360_TIMER_COUNTER3					    0x85C
+#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64360_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64360_I2C_SLAVE_ADDR					    0xc000
+#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64360_I2C_DATA					    0xc004
+#define MV64360_I2C_CONTROL					    0xc008
+#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64360_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_GPP_IO_CONTROL					    0xf100
+#define MV64360_GPP_LEVEL_CONTROL				    0xf110
+#define MV64360_GPP_VALUE					    0xf104
+#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64360_GPP_VALUE_SET					    0xf118
+#define MV64360_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_MPP_CONTROL0					    0xf000
+#define MV64360_MPP_CONTROL1					    0xf004
+#define MV64360_MPP_CONTROL2					    0xf008
+#define MV64360_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64360_SERIAL_INIT_CONTROL				    0xf328
+#define MV64360_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64360rh */
diff --git a/u-boot/board/esd/cpci750/pci.c b/u-boot/board/esd/cpci750/pci.c
new file mode 100644
index 0000000..a2c1c50
--- /dev/null
+++ b/u-boot/board/esd/cpci750/pci.c
@@ -0,0 +1,1050 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+
+#ifdef CONFIG_PCI_PNP
+void pciauto_config_init(struct pci_controller *hose);
+int  pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+#endif
+
+#include "../../Marvell/include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+	unsigned int base;
+	unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*		    - Make sure the GT is configured as a master before writing
+*		      to another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*		   (or any other PCI device spec)
+*	    pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*		    - Make sure the GT is configured as a master before reading
+*		      from another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			spec)
+*	    pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*				the agent is placed on another Bus. For more
+*				information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*	    GT spec (or any other PCI device spec).
+*	    unsigned int pciDevNum - The device number needs to be addressed.
+*	    unsigned int busNum - On which bus does the Target agent connect
+*				  to.
+*	    unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*				the agent target locate on another PCI bus.
+*			      - Make sure the GT is configured as a master
+*				before reading from another device on the PCI.
+*			      - The function takes care of Big/Little endian
+*				conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			 spec). (configuration register offset.)
+*	    pciDevNum: The device number needs to be addressed.
+*	    busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*	    - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*			  feature bits given as an input.
+*			- Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*	  unsigned int features - See file: pci.h there are defintion for those
+*				  region features.
+*	  unsigned int baseAddress - The region base Address.
+*	  unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*			    to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*	    PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*	    PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*	    PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*	    PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*	    PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*	    PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*		       disable the park on last mechanism for each agent.
+*		       disabling this option for all agents results parking
+*		       on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*	  PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*	  PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*	  PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*	  PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*	  PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*	  PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*			respond to grant assertion within a window specified in
+*			the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*			grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*			    Detection mechanism.
+*			    NOTE: This operation may cause a dead lock on the
+*			    pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*		  For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*				       Boundry.
+*	   unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*				       Boundry.
+*	   unsigned int busNum - The CPI bus number to which the PCI interface
+*				       is connected.
+*	   unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*			   supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*	  snoopType - There is four optional Types:
+*			 1. No Snoop.
+*			 2. Snoop to WT region.
+*			 3. Snoop to WB region.
+*			 4. Snoop & Invalidate to WB region.
+*	  baseAddress - Base Address of this region.
+*	  regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+	        *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
+					   offset | (PCI_FUNC(dev) << 8),
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
+						     offset | (PCI_FUNC(dev) << 8),
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+				   offset | (PCI_FUNC(dev) << 8),
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset | (PCI_FUNC(dev) << 8),
+					     PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	if (CPCI750_SLAVE_TEST != 0)
+		return;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					     0x0);
+		pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					    &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					     bar_value);
+	}
+}
+
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+			      pci_dev_t dev, struct pci_config_table *entry)
+{
+	u32		  bar_value, pci_response;
+
+	if (CPCI750_SLAVE_TEST != 0)
+		return;
+
+	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+	pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+	pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+	gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+	gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+	unsigned char	  data;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return(0);
+		}
+	data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+	return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+	unsigned int	  off;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return;
+	}
+	off = data;
+	off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+	in8(off);
+	return;
+}
+#endif
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260	*/
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+	{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+	unsigned int slave;
+#ifdef CONFIG_PCI_PNP
+	unsigned int bar;
+#endif
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+#ifdef CONFIG_USE_CPCIDVI
+	gt_cpcidvi_rom.init = 0;
+	gt_cpcidvi_rom.base = 0;
+#endif
+
+	slave = CPCI750_SLAVE_TEST;
+
+	pci0_hose.config_table = gt_config_table;
+	pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+	gt_config_table[0].config_device =  gt_setup_cpcidvi;
+#endif
+	gt_config_table[1].config_device =  gt_setup_ide;
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	if (slave == 0) {
+		pciArbiterEnable (PCI_HOST0);
+		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MASTER;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MEMORY;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+		pciauto_config_init(&pci0_hose);
+		pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+#endif
+#ifdef CONFIG_PCI_SCAN_SHOW
+		printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+		pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
+							  pci0_hose.first_busno);
+
+#ifdef DEBUG
+		gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	} else {
+		pciArbiterDisable (PCI_HOST0);
+		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MASTER;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MEMORY;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		pci0_hose.last_busno = pci0_hose.first_busno;
+	}
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci1_hose);
+	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
+#endif
+	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
+#endif /* of CONFIG_PCI */
diff --git a/u-boot/board/esd/cpci750/sdram_init.c b/u-boot/board/esd/cpci750/sdram_init.c
new file mode 100644
index 0000000..615e32a
--- /dev/null
+++ b/u-boot/board/esd/cpci750/sdram_init.c
@@ -0,0 +1,1839 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64360 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ *
+ * adaption for the cpci750 Board
+ * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
+ *************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../../Marvell/common/i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+/* #define DEBUG */
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit(void);	/* setup delay line of Mv64360 */
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank(unsigned int bankNo,
+		unsigned int bankBase,
+		unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf("mapping bank %d at %08x - %08x\n",
+		       bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank(bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
+		const int features=
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 |
+			PCI_NO_SWAP;
+
+		pciMapMemoryBank(host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
+				bankLength);
+
+		pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB	   (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
+
+typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+				SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+			       } VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;			/* ECC , PARITY.. */
+	unsigned int sdramWidth;			/* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;		/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;		/* measured in ns */
+
+	int addrAndCommandHoldTime;			/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;			/* (measured in ns/100) */
+	int dataInputSetupTime;				/* LoP left of point (measured in ns) */
+	int dataInputHoldTime;				/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+	unsigned int clockToDataOut_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;		/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;		/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;		/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;			/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;					/* DRAM size in n*64Mbit */
+	uchar slot;					/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];			/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+	uchar manufactura[8];				/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];				/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];				/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;			/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;			/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;			/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;				/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short
+NS10to10PS(unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return(ns*100 + ns10*10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short
+NSto10PS(unsigned char spd_byte)
+{
+	return(spd_byte*100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	unsigned long spd_checksum;
+
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	memset (data, 0, sizeof (data));
+
+
+	ret = 0;
+
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 2, data, 128);
+
+	DP (puts ("after i2c read\n"));
+
+	if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
+	    || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
+	    || (data[70] != 'b') || (data[71] != 'h')) {
+		ret = -1;
+	}
+
+	if ((ret != 0) && (slot == 0)) {
+		memset (data, 0, sizeof (data));
+		data[0] = 0x80;
+		data[1] = 0x08;
+		data[2] = 0x07;
+		data[3] = 0x0c;
+		data[4] = 0x09;
+		data[5] = 0x01;
+		data[6] = 0x48;
+		data[7] = 0x00;
+		data[8] = 0x04;
+		data[9] = 0x75;
+		data[10] = 0x80;
+		data[11] = 0x02;
+		data[12] = 0x80;
+		data[13] = 0x10;
+		data[14] = 0x08;
+		data[15] = 0x01;
+		data[16] = 0x0e;
+		data[17] = 0x04;
+		data[18] = 0x0c;
+		data[19] = 0x01;
+		data[20] = 0x02;
+		data[21] = 0x20;
+		data[22] = 0x00;
+		data[23] = 0xa0;
+		data[24] = 0x80;
+		data[25] = 0x00;
+		data[26] = 0x00;
+		data[27] = 0x50;
+		data[28] = 0x3c;
+		data[29] = 0x50;
+		data[30] = 0x32;
+		data[31] = 0x10;
+		data[32] = 0xb0;
+		data[33] = 0xb0;
+		data[34] = 0x60;
+		data[35] = 0x60;
+		data[64] = 'e';
+		data[65] = 's';
+		data[66] = 'd';
+		data[67] = '-';
+		data[68] = 'g';
+		data[69] = 'm';
+		data[70] = 'b';
+		data[71] = 'h';
+		ret = 0;
+	}
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+	/* find Manufacturer of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by:		%s\n",
+		dimmInfo->manufactura);
+
+	/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is:		%s\n",
+		dimmInfo->modul_id);
+
+	/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is:		%s\n",
+		dimmInfo->vendor_data);
+
+	/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+	/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+	/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+	/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is:		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	spd_checksum = 0;
+#if 0				/* test-only */
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+#endif /* test-only */
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2:	/* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				DP (printf
+				    ("Dram_type in slot %d is:			SDRAM\n",
+				     dimmInfo->slot));
+			if (dimmInfo->memoryType == 1)
+				DP (printf
+				    ("Dram_type in slot %d is:			DDRAM\n",
+				     dimmInfo->slot));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3:	/* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			DP (printf
+			    ("Module Number of row addresses:		%d\n",
+			     dimmInfo->numOfRowAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4:	/* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			DP (printf
+			    ("Module Number of col addresses:		%d\n",
+			     dimmInfo->numOfColAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5:	/* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			DP (printf
+			    ("Number of Banks on Mod. : 				%d\n",
+			     dimmInfo->numOfModuleBanks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6:	/* Data Width */
+			dimmInfo->dataWidth = data[i];
+			DP (printf
+			    ("Module Data Width:				%d\n",
+			     dimmInfo->dataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8:	/* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				DP (printf
+				    ("Module is 					LVTTL\n"));
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				DP (printf
+				    ("Module is 					HSTL_1_5V\n"));
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				DP (printf
+				    ("Module is 					SSTL_2_5V\n"));
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				DP (printf
+				    ("Module is 					VOLTAGE_UNKNOWN\n"));
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9:	/* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out:				%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+#ifdef CONFIG_MV64360_ECC
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			DP (printf
+			    ("Error Check Type (0=NONE):			%d\n",
+			     dimmInfo->errorCheckType));
+			break;
+#endif /* of ifdef CONFIG_MV64360_ECC */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			DP (printf
+			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			DP (printf
+			    ("Sdram Width:					%d\n",
+			     dimmInfo->sdramWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			DP (printf
+			    ("Error Check Data Width:			%d\n",
+			     dimmInfo->errorCheckDataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			DP (printf
+			    ("Minimum Clock Delay:				%d\n",
+			     dimmInfo->minClkDelay));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8   |  4	 |   2	|   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Burst Length Supported:			"));
+			if (dimmInfo->burstLengthSupported & 0x01)
+				DP (printf ("1, "));
+			if (dimmInfo->burstLengthSupported & 0x02)
+				DP (printf ("2, "));
+			if (dimmInfo->burstLengthSupported & 0x04)
+				DP (printf ("4, "));
+			if (dimmInfo->burstLengthSupported & 0x08)
+				DP (printf ("8, "));
+			DP (printf (" Bit \n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			DP (printf
+			    ("Number Of Banks On Each Chip:			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	| TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	|  7   |  6   |  5   |	4   |  3   |   2  |   1  *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Suported Cas Latencies: (CL)			"));
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						DP (printf
+						    ("%d,			",
+						     k + 1));
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					DP (printf ("1, "));
+				if (dimmInfo->suportedCasLatencies & 2)
+					DP (printf ("1.5, "));
+				if (dimmInfo->suportedCasLatencies & 4)
+					DP (printf ("2, "));
+				if (dimmInfo->suportedCasLatencies & 8)
+					DP (printf ("2.5, "));
+				if (dimmInfo->suportedCasLatencies & 16)
+					DP (printf ("3, "));
+				if (dimmInfo->suportedCasLatencies & 32)
+					DP (printf ("3.5, "));
+
+			}
+			DP (printf ("\n"));
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3.5 clk's\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			1.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
+						DP (printf
+						    ("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD));
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+#ifdef DEBUG
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Buffered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Buffered Address/Control Input:		No \n"));
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Registered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Registered Address/Control Input:		No \n"));
+
+			if (dimmInfo->onCardPLL == 1)
+				DP (printf
+				    (" - On-Card PLL (clock):				Yes \n"));
+			else
+				DP (printf
+				    (" - On-Card PLL (clock):				No \n"));
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				Yes \n"));
+			else
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				No \n"));
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				DP (printf
+				    (" - Registered DQMB Inputs:			Yes \n"));
+			else
+				DP (printf
+				    (" - Registered DQMB Inputs:			No \n"));
+
+			if (dimmInfo->differentialClockInput == 1)
+				DP (printf
+				    (" - Differential Clock Input:			Yes \n"));
+			else
+				DP (printf
+				    (" - Differential Clock Input:			No \n"));
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				DP (printf
+				    (" - redundant Row Addressing:			Yes \n"));
+			else
+				DP (printf
+				    (" - redundant Row Addressing:			No \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+#ifdef DEBUG
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				DP (printf
+				    (" - Early Ras Precharge:			Yes \n"));
+			else
+				DP (printf
+				    (" -  Early Ras Precharge:			No \n"));
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				DP (printf
+				    (" - AutoPreCharge:				Yes \n"));
+			else
+				DP (printf
+				    (" -  AutoPreCharge:				No \n"));
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				DP (printf
+				    (" - Precharge All:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Precharge All:				No \n"));
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				DP (printf
+				    (" - Write 1/ReadBurst:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Write 1/ReadBurst:				No \n"));
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				DP (printf
+				    (" - lower VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    ("	- lower VCC tolerance:			10 Percent \n"));
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				DP (printf
+				    (" - upper VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    (" -  upper VCC tolerance:			10 Percent \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100));
+			DP (printf
+			    ("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trrd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trcd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks));
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			DP (printf
+			    ("Module Bank Density:				%d\n",
+			     dimmInfo->moduleBankDensity));
+#ifdef DEBUG
+			DP (printf
+			    ("*** Offered Densities (more than 1 = Multisize-Module): "));
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					DP (printf ("4MB, "));
+				if (dimmInfo->moduleBankDensity & 2)
+					DP (printf ("8MB, "));
+				if (dimmInfo->moduleBankDensity & 4)
+					DP (printf ("16MB, "));
+				if (dimmInfo->moduleBankDensity & 8)
+					DP (printf ("32MB, "));
+				if (dimmInfo->moduleBankDensity & 16)
+					DP (printf ("64MB, "));
+				if (dimmInfo->moduleBankDensity & 32)
+					DP (printf ("128MB, "));
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					DP (printf ("ERROR, "));
+					hang ();
+				}
+			}
+			DP (printf ("\n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Setup Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Hold Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Setup Time [ns]:			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Hold Time [ns]:			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices - devicesForErrCheck);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
+	dimmInfo->drb_size = (uchar) tmp;
+	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 8) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 6;
+	}
+	if (supp_cal & 4) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 5;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 4;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val * 5));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		hang ();
+		return 0;
+	}
+
+	return true;
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
+	int i;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+
+	/* Program the GT with the discovered data */
+	if (info->registeredAddrAndControlInputs == true)
+		DP (printf
+		    ("Module is registered, but we do not support registered Modules !!!\n"));
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	DP (printf ("Delay line set done\n"));
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+	}
+
+#ifdef CONFIG_MV64360_ECC
+	if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg |= BIT18;
+		DP(printf("Enabling ECC\n"));
+	}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+	/* SDRAM configuration */
+	GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
+	DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM open pages controll keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	DP (printf
+	    ("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+	else
+		DP (printf
+		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+
+	/* SDRAM set CAS Lentency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		DP (printf ("### SD-RAM not supported yet !!!\n"));
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+
+	case DDR:
+		DP (printf ("### SET-CL for DDR-RAM\n"));
+
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_dunit_control_low = 0x3c000000;	/* Read-Data sampled on falling edge of Clk */
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			DP (printf
+			    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+			     tmp_sdram_mode, tmp_dunit_control_low));
+			break;
+
+		case DDR_CL_2_5:
+			if (tmp == 1) {	/* clocks sync */
+				tmp_dunit_control_low = 0x24000000;	/* Read-Data sampled on falling edge of Clk */
+				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	  */
+
+				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		case DDR_CL_2:
+			if (tmp == 1) {	/* Sync */
+				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* Not sync.	  */
+
+				tmp_dunit_control_low = 0x3b000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		case DDR_CL_1_5:
+			if (tmp == 1) {	/* Sync */
+				tmp_dunit_control_low = 0x23000000;	/* Read-Data sampled on falling edge of Clk */
+				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* not sync */
+
+				tmp_dunit_control_low = 0x1a000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}
+		break;
+	}
+
+	/* Write results of CL detection procedure */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+	}
+
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp != 1) {		/*clocks are not sync */
+		/* asyncmode */
+		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
+			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
+			      0x18110780 | tmp_dunit_control_low);
+	} else {
+		/* syncmode */
+		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
+			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
+			      0x00110000 | tmp_dunit_control_low);
+	}
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+	}
+
+/*------------------------------------------------------------------------------ */
+
+
+	/* bank parameters */
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	tmp = 0x02;
+
+
+	DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+	switch (info->drb_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		return 1;
+	}
+
+	/* SDRAM bank parameters */
+	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
+	DP (printf
+	    ("setting up slot %d config with: %08lx \n", info->slot, tmp));
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+
+/* ------------------------------------------------------------------------------ */
+
+	DP (printf
+	    ("setting up sdram_timing_control_low with: %08x \n",
+	     0x11511220));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		DP (printf
+		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs));
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV64360 */
+	tmp |= (1 << 26);
+	DP (printf
+	    ("Before Buffer assignment - sdram_conf: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+	DP (printf
+	    ("After Buffer assignment - sdram_conf: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM timing To_do: */
+
+
+	tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
+	DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
+
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
+	DP (printf
+	    ("SDRAM address control (before: decode): %08x  ",
+	     GTREGREAD (SDRAM_ADDR_CONTROL)));
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
+	DP (printf
+	    ("SDRAM address control (after: decode): %08x\n",
+	     GTREGREAD (SDRAM_ADDR_CONTROL)));
+
+	/* set the SDRAM configuration for each bank */
+
+/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		int l, l1;
+
+		i = info->slot;
+		DP (printf
+		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+#if 1				/* test only */
+
+		tmp = GTREGREAD (SDRAM_MODE);
+		GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x4);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+
+		GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+		l1 = 0;
+		for (l=0;l<200;l++)
+			l1 += GTREGREAD (SDRAM_OPERATION);
+
+		GT_REG_WRITE (SDRAM_MODE, tmp);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+
+#endif /* test only */
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int
+dram_size(long int *base, long int maxsize)
+{
+    volatile long int	 *addr, *b=base;
+    long int	 cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
+	    addr = base + cnt;	/* pointer arith! */
+
+	    save1 = *addr;		/* save contents of addr */
+	    save2 = *b;		/* save contents of base */
+
+	    *addr=cnt;		/* write cnt to addr */
+	    *b=0;			/* put null at base */
+
+	    /* check at base address */
+	    if ((*b) != 0) {
+		*addr=save1;	/* restore *addr */
+		*b=save2;	/* restore *b */
+		return (0);
+	    }
+	    val = *addr;		/* read *addr */
+	    val = *addr;		/* read *addr */
+
+	    *addr=save1;
+	    *b=save2;
+
+	    if (val != cnt) {
+		    DP(printf("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
+		    /* fix boundary condition.. STARTVAL means zero */
+		    if(cnt==STARTVAL/sizeof(long)) cnt=0;
+		    return (cnt * sizeof(long));
+	    }
+    }
+    return maxsize;
+}
+
+#ifdef CONFIG_MV64360_ECC
+/*
+ * mv_dma_is_channel_active:
+ * Checks if a engine is busy.
+ */
+int mv_dma_is_channel_active(int engine)
+{
+	ulong data;
+
+	data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14)	/* activity status */
+		return 1;
+
+	return 0;
+}
+
+/*
+ * mv_dma_set_memory_space:
+ * Set a DMA memory window for the DMA's address decoding map.
+ */
+int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
+			    ulong mem_space_attr, ulong base_address,
+			    ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (base_address % size != 0)
+		return 0;
+
+	if (size >= 0x10000) {
+		size &= 0xffff0000;
+		base_address = (base_address & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
+			     (base_address | mem_space_target |
+			      mem_space_attr));
+		GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
+			     (size - 1) & 0xffff0000);
+		temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
+			     (temp & ~(BIT0 << mem_space)));
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ * mv_dma_transfer:
+ * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
+ */
+int mv_dma_transfer(int engine, ulong source_addr,
+		    ulong dest_addr, ulong bytes, ulong command)
+{
+	ulong eng_off_reg;	/* Engine Offset Register */
+
+	if (bytes > 0xffff)
+		command = command | BIT31;	 /* DMA_16M_DESCRIPTOR_MODE */
+
+	command = command | ((command >> 6) & 0x7);
+	eng_off_reg = engine * 4;
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
+		     bytes);
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
+		     source_addr);
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
+		     dest_addr);
+	command |= BIT12	/* DMA_CHANNEL_ENABLE */
+		| BIT9;		/* DMA_NON_CHAIN_MODE */
+
+	/* Activate DMA engine By writting to mv_dma_control_register */
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
+
+	return 1;
+}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+phys_size_t
+initdram(int board_type)
+{
+	int s0 = 0, s1 = 0;
+	int checkbank[4] = { [0 ... 3] = 0 };
+	ulong realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int bank_no, nhr;
+#ifdef CONFIG_MV64360_ECC
+	ulong dest, mem_space_attr;
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0() & (1 << 16);
+
+	if (nhr) {
+		printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		s0 = check_dimm(0, &dimmInfo1);
+
+		/* DIMM1 */
+		s1 = check_dimm(1, &dimmInfo2);
+
+		memory_map_bank(0, 0, 0);
+		memory_map_bank(1, 0, 0);
+		memory_map_bank(2, 0, 0);
+		memory_map_bank(3, 0, 0);
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
+			printf("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
+			printf("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0(get_hid0() | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB/4;
+	if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
+	if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf("Error, SPD claims DIMM1 has >2 banks\n");
+
+	if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
+	if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf("Error, SPD claims DIMM2 has >2 banks\n");
+
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (! checkbank[bank_no])
+			continue;
+
+		if ((total + check) > CONFIG_SYS_GT_REGS)
+			check = CONFIG_SYS_GT_REGS - total;
+
+		memory_map_bank(bank_no, total, check);
+		realsize = dram_size((long int *)total, check);
+		memory_map_bank(bank_no, total, realsize);
+
+#ifdef CONFIG_MV64360_ECC
+		if (((dimmInfo1.errorCheckType != 0) &&
+		     ((dimmInfo2.errorCheckType != 0) ||
+		      (dimmInfo2.numOfModuleBanks == 0))) &&
+		    (CPCI750_ECC_TEST)) {
+			printf("ECC Initialization of Bank %d:", bank_no);
+			mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mv_dma_set_memory_space(0, 0, mem_space_attr, total,
+						realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mv_dma_transfer(0, total, dest, _8M,
+						BIT8 |	/* DMA_DTL_128BYTES */
+						BIT3 |	/* DMA_HOLD_SOURCE_ADDR */
+						BIT11);	/* DMA_BLOCK_TRANSFER_MODE */
+				while (mv_dma_is_channel_active(0))
+					;
+			}
+			printf(" PASS\n");
+		}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+		total += realsize;
+	}
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	return(total);
+}
+
+/* ***************************************************************************************
+! *				SDRAM INIT						*
+! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+! *		  This procedure fits only the Atlantis				       *
+! *											*
+! *************************************************************************************** */
+
+
+/* ***************************************************************************************
+! *				DFCDL initialize MV643xx Design Considerations		   *
+! *											*
+! *************************************************************************************** */
+int set_dfcdlInit (void)
+{
+	int i;
+	unsigned int dfcdl_word = 0x0000014f;
+
+	for (i = 0; i < 64; i++) {
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
+	}
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+
+	return (0);
+}
+
+int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int ecc_counter;
+	unsigned int ecc_addr;
+
+	GT_REG_READ(0x1458, &ecc_counter);
+	GT_REG_READ(0x1450, &ecc_addr);
+	GT_REG_WRITE(0x1450, 0);
+
+	printf("Error Counter since Reset:  %8d\n", ecc_counter);
+	printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
+	if (ecc_addr & 0x01)
+		printf("double");
+	else
+		printf("single");
+	printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	show_ecc, 1, 1, do_show_ecc,
+	"Show Marvell MV64360 ECC Info",
+	"Show Marvell MV64360 ECC Counter and last error."
+);
diff --git a/u-boot/board/esd/cpci750/serial.c b/u-boot/board/esd/cpci750/serial.c
new file mode 100644
index 0000000..e1af37e
--- /dev/null
+++ b/u-boot/board/esd/cpci750/serial.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * modified for cpci750 board by
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for esd cpci750 board
+ */
+
+/* supports the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../../Marvell/include/memory.h"
+#include "serial.h"
+
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int serial_init (void)
+{
+	mpsc_init (gd->baudrate);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/u-boot/board/esd/cpci750/serial.h b/u-boot/board/esd/cpci750/serial.h
new file mode 100644
index 0000000..c7fc8c1
--- /dev/null
+++ b/u-boot/board/esd/cpci750/serial.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/u-boot/board/esd/cpciiser4/Makefile b/u-boot/board/esd/cpciiser4/Makefile
new file mode 100644
index 0000000..bd08253
--- /dev/null
+++ b/u-boot/board/esd/cpciiser4/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/cpciiser4/cpciiser4.c b/u-boot/board/esd/cpciiser4/cpciiser4.c
new file mode 100644
index 0000000..8afc50d
--- /dev/null
+++ b/u-boot/board/esd/cpciiser4/cpciiser4.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2000
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "cpciiser4.h"
+#include <asm/processor.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * Init FPGA via RESET (read access on CS3)
+	 */
+	in_8((void *)0xf0200000);
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	/*  mtdcr(UIC0PR, 0xFFFFFF81);   /  set int polarities */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
diff --git a/u-boot/board/esd/cpciiser4/cpciiser4.h b/u-boot/board/esd/cpciiser4/cpciiser4.h
new file mode 100644
index 0000000..5fc313a
--- /dev/null
+++ b/u-boot/board/esd/cpciiser4/cpciiser4.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/cpciiser4/flash.c b/u-boot/board/esd/cpciiser4/flash.c
new file mode 100644
index 0000000..b210281
--- /dev/null
+++ b/u-boot/board/esd/cpciiser4/flash.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+	/*          printf("PB1CR = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/cpciiser4/fpgadata.c b/u-boot/board/esd/cpciiser4/fpgadata.c
new file mode 100644
index 0000000..5e02097
--- /dev/null
+++ b/u-boot/board/esd/cpciiser4/fpgadata.c
@@ -0,0 +1,2068 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0c,
+ 0x69,0x73,0x65,0x72,0x34,0x5f,0x31,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,0x73,
+ 0x34,0x30,0x78,0x6c,0x70,0x71,0x32,0x30,0x38,0x00,0x63,0x00,0x0b,0x32,0x30,0x30,
+ 0x31,0x2f,0x30,0x33,0x2f,0x31,0x39,0x00,0x64,0x00,0x09,0x31,0x36,0x3a,0x31,0x34,
+ 0x3a,0x32,0x35,0x00,0x65,0xe2,0x01,0x00,0x00,0x80,0xf0,0xff,0x30,0xe5,0xe5,0xe8,
+ 0xe5,0x03,0xe8,0x04,0x01,0x02,0x09,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x07,0x0b,0x01,0x07,0x01,0x05,0x09,0x03,0x07,0x09,0x01,0x05,0x03,0x05,0x0b,0x0c,
+ 0x08,0x01,0x07,0x01,0x05,0x03,0x05,0x03,0x07,0x01,0x07,0x02,0x04,0x03,0x07,0x01,
+ 0x09,0x07,0x01,0x07,0x01,0x07,0x08,0xe7,0x0c,0x09,0x09,0x09,0x09,0x09,0x02,0x04,
+ 0x0b,0x09,0x06,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x08,0x02,0x06,0x07,0x01,0x06,0xe5,
+ 0x02,0x02,0x04,0x01,0x02,0xe5,0x02,0x02,0x08,0x09,0x09,0x09,0x09,0x13,0x09,0x07,
+ 0x01,0x09,0x09,0x13,0xe5,0x47,0x05,0x17,0x04,0x04,0x0e,0x0e,0x09,0x06,0x04,0x09,
+ 0x59,0x25,0x02,0xe5,0x0e,0x09,0x09,0x09,0x09,0x09,0x01,0x05,0xe6,0x08,0x09,0x09,
+ 0x01,0x07,0x09,0x01,0x07,0x09,0x0b,0x01,0x07,0x01,0x04,0x01,0x0a,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0xe8,0x13,0x09,0x09,0x09,0x09,0x0a,0xe7,
+ 0x04,0x09,0x0a,0xe5,0x07,0xe5,0x06,0x09,0x0a,0xe5,0x07,0xe5,0x09,0xe5,0x06,0xe8,
+ 0x04,0x09,0x09,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe5,0x07,0x0a,0xe5,0x06,0x09,
+ 0x09,0x09,0x03,0x40,0x08,0x1d,0xe5,0x12,0x1f,0x08,0xe5,0x07,0x01,0x55,0x26,0x01,
+ 0xe6,0xe5,0x46,0x31,0x1f,0x13,0x58,0x25,0xe6,0xe5,0x3f,0x04,0x1d,0x04,0x04,0x0e,
+ 0x0e,0x09,0x03,0x02,0x04,0x04,0x0a,0x53,0x28,0x02,0xe5,0xe5,0x10,0x09,0x09,0x02,
+ 0x06,0x09,0x1d,0x1d,0x09,0x17,0x1b,0x01,0x07,0x1d,0x09,0x02,0x10,0x13,0x09,0x09,
+ 0x0a,0x03,0x01,0x48,0x1f,0x11,0x01,0x1d,0x01,0x09,0x07,0x7e,0x01,0xe5,0xe5,0x42,
+ 0x1d,0x04,0x04,0x1d,0x09,0x0b,0x15,0x4d,0x28,0x01,0x01,0x99,0x95,0xe7,0x28,0x6f,
+ 0x0a,0x44,0x44,0xe5,0xe6,0x0f,0x09,0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x03,0x05,
+ 0x05,0x03,0x09,0x09,0x09,0x09,0x0b,0x01,0x01,0x01,0x03,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x0e,0xe7,0x0f,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x03,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x03,0x0d,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,
+ 0x02,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x08,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x0f,0x01,0xe5,0x0f,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x09,0x09,0xe5,0x07,0x09,0x09,0x06,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x04,0x0b,0xe5,0x05,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0x02,0x06,0xe5,0x0e,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,
+ 0x04,0x09,0x04,0x04,0x09,0x0b,0x04,0x04,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x12,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x08,
+ 0xe5,0x08,0x06,0x02,0x09,0x09,0x09,0x01,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x07,0x08,0xe5,0x01,0x0d,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x09,0x06,0x02,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x04,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x05,0xe5,0x01,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x0e,0xe7,0x02,0x3b,0x11,0x25,0x1c,0x06,0x04,0x89,0x04,0x02,0x03,
+ 0x4d,0x46,0x02,0x19,0x0a,0x6f,0xe6,0x02,0x3b,0x12,0x22,0x02,0x1d,0x03,0x07,0x01,
+ 0x89,0xe5,0xe6,0x3f,0x08,0xe5,0x05,0x2a,0x17,0x11,0x18,0xe5,0x01,0xe5,0x68,0x03,
+ 0x10,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x04,0x04,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,
+ 0x01,0x01,0x3f,0x01,0xe5,0x0d,0x0b,0x01,0xe5,0x02,0x02,0x1d,0x09,0x02,0x08,0x21,
+ 0x0f,0x02,0x1a,0x01,0xe5,0x3f,0xe5,0xe5,0x10,0x2d,0x1e,0x26,0x09,0x06,0x37,0x60,
+ 0x01,0xe5,0x67,0x26,0x0c,0x30,0x1e,0x43,0xe6,0x05,0x54,0x0f,0x2a,0x08,0xe5,0x0b,
+ 0x80,0x02,0xe5,0xd0,0x60,0x56,0x09,0x8a,0x01,0x40,0xe5,0x01,0x6e,0x1a,0x61,0x01,
+ 0x40,0xe8,0x05,0x85,0xa1,0xe5,0x01,0x61,0x38,0x14,0x09,0x01,0x0e,0x63,0xe6,0xe5,
+ 0x10,0x3f,0x5f,0x7c,0x02,0xe5,0x8e,0xe6,0x9f,0x91,0x9d,0x02,0x88,0x0c,0x98,0x03,
+ 0x63,0x3f,0x05,0x07,0x7c,0xe8,0xaa,0x05,0x40,0x3b,0x01,0x01,0xe6,0x06,0xe5,0x65,
+ 0x16,0x03,0xe5,0x04,0x1f,0xe5,0x07,0x0f,0x5e,0xe5,0x03,0x02,0x01,0x04,0xe5,0x65,
+ 0x20,0x20,0x09,0x0f,0x5b,0x01,0x06,0x04,0x6c,0x30,0xe5,0xe5,0xe5,0x08,0x04,0x01,
+ 0xe5,0x12,0x5b,0x04,0xe5,0xe6,0x01,0x6e,0x30,0x02,0x01,0x03,0xe5,0x01,0x09,0x13,
+ 0x5d,0x02,0xe8,0x70,0x22,0x0e,0x10,0x09,0x0e,0x61,0xe5,0xe5,0x01,0x6e,0x03,0x33,
+ 0x05,0x04,0x03,0x05,0x0e,0x03,0x59,0x02,0x01,0xe7,0x6f,0x1a,0x01,0x04,0x11,0x01,
+ 0x09,0x04,0xe5,0x02,0x11,0x5f,0x01,0xe5,0xe5,0x70,0x22,0x01,0x01,0x0c,0x01,0x0c,
+ 0xe7,0x02,0x02,0x0e,0x63,0xe5,0x91,0x1f,0x02,0x02,0x75,0xe5,0xe6,0x10,0x80,0xe5,
+ 0x1e,0x02,0x78,0xe5,0xe6,0x08,0x01,0x02,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x02,0x06,0x09,0x09,0xe6,0x08,0x09,0x09,0x01,0x01,0x05,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0xe5,0xe5,0x01,0x09,0xa1,0x09,0x72,
+ 0x03,0x02,0x0b,0x05,0x9b,0x07,0x7a,0x01,0x92,0xe6,0x16,0x05,0xe6,0x08,0x6d,0x02,
+ 0xe7,0xe5,0x03,0x0a,0x81,0x1b,0x01,0x01,0x02,0x06,0x73,0xe5,0x92,0x01,0x1b,0x01,
+ 0x01,0x78,0xe5,0x01,0x01,0x04,0x0e,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x09,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe8,
+ 0x08,0x05,0xa1,0x09,0x74,0x01,0x0d,0xa1,0x09,0x74,0xe5,0x01,0x0f,0x8a,0x16,0x09,
+ 0x73,0xe5,0xe5,0x0c,0x04,0x81,0x1a,0x04,0x04,0x04,0x6f,0xe5,0xe6,0x70,0x01,0xe5,
+ 0x39,0x02,0x06,0x02,0x0d,0x02,0xe5,0xe5,0x5c,0xe5,0xe6,0xe5,0x0e,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x03,0x03,0x01,0x07,0x01,0x07,0x01,0xe6,0x04,0x01,0x01,0x02,0x04,0x01,0x01,0x05,
+ 0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0x03,
+ 0x7a,0x08,0x2b,0x01,0xe5,0x05,0x01,0xe5,0x71,0x01,0xe6,0x88,0x0d,0x17,0xe5,0x04,
+ 0x02,0xe5,0x70,0xe6,0xe6,0x83,0x04,0x0f,0x1e,0x75,0x03,0x0f,0x5e,0x1d,0x0b,0x01,
+ 0x04,0x0f,0x01,0x05,0x77,0xe7,0x0c,0x80,0x0a,0x15,0x02,0xe5,0x7a,0x02,0x7d,0x04,
+ 0x04,0x08,0xe5,0x06,0x05,0xe5,0x0e,0xe5,0x16,0x64,0x01,0x01,0x82,0x02,0xe5,0xe5,
+ 0x05,0x09,0x15,0x09,0x04,0x08,0x04,0x62,0xe5,0xe5,0x6e,0x0e,0x08,0x09,0x07,0x15,
+ 0x0b,0x72,0xe6,0xe5,0x6e,0x1a,0x03,0x0a,0xe5,0x16,0x05,0x75,0xe5,0xe6,0x77,0x1d,
+ 0x01,0xe5,0x0f,0x83,0x02,0xe5,0x7c,0xe5,0xe5,0x09,0x05,0x1d,0x01,0x7d,0xe8,0x7a,
+ 0x07,0x02,0x0a,0x0c,0x11,0x06,0x02,0x0d,0x63,0xe6,0x01,0x11,0x5c,0x18,0x07,0x20,
+ 0x02,0x07,0x73,0xe9,0x72,0x09,0x02,0xe5,0x04,0xe5,0x03,0x0b,0x13,0x09,0x72,0xe8,
+ 0xe5,0x01,0x01,0x6d,0xe5,0xe5,0x08,0x02,0xe5,0xe5,0x02,0x05,0xe5,0x02,0x06,0x1d,
+ 0xe5,0x6d,0x01,0x02,0xe6,0xe5,0x03,0x69,0xe5,0xe5,0xe5,0x17,0xe5,0xe5,0xe5,0x03,
+ 0x01,0x02,0x01,0x0e,0xe5,0x07,0xe5,0xe5,0x6e,0x04,0xe8,0x01,0x6a,0xe5,0x01,0x01,
+ 0x0d,0xe5,0x01,0x06,0x02,0x01,0x04,0xe5,0x02,0x01,0x0e,0x09,0x02,0x71,0x02,0x03,
+ 0x73,0x02,0x04,0x0e,0x02,0x01,0x01,0xe5,0x02,0x01,0x02,0x11,0x04,0x04,0xe6,0x05,
+ 0x01,0x6c,0x02,0x02,0x70,0x02,0x04,0x09,0x03,0x05,0x01,0xe5,0x01,0x02,0x02,0x03,
+ 0x17,0x01,0x03,0x02,0x01,0x68,0x02,0xe5,0xe7,0x6f,0x01,0x07,0x09,0x01,0x02,0x04,
+ 0x01,0x09,0x01,0x1b,0x73,0x04,0x71,0x01,0x02,0x04,0x04,0x04,0x01,0x01,0xe5,0x03,
+ 0x01,0xe5,0x07,0x01,0x1b,0x75,0xe7,0x80,0x02,0x03,0x09,0x02,0x02,0x08,0x02,0x1a,
+ 0xe5,0x6e,0xe6,0x75,0x01,0x06,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x07,0x0b,0x13,0x09,
+ 0x6d,0x01,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x02,
+ 0x02,0x09,0xe5,0x04,0x02,0xe5,0x01,0x02,0x04,0x05,0x03,0x09,0x05,0x03,0x02,0xe5,
+ 0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,0xe5,0x01,0x6d,
+ 0x04,0x03,0xe5,0x08,0x06,0x0b,0x20,0x72,0x02,0xe8,0x6c,0x0b,0x08,0x06,0x2d,0x77,
+ 0x02,0x01,0x71,0x02,0x04,0x01,0x02,0x01,0x02,0x01,0xe7,0x03,0x01,0xe5,0x1e,0x79,
+ 0x01,0x03,0x71,0x03,0x05,0x01,0x01,0x01,0x03,0x01,0xe6,0x04,0x01,0x06,0x05,0x19,
+ 0x03,0x71,0xe6,0xe5,0x72,0x03,0x05,0x03,0x03,0x01,0x03,0x03,0x01,0x1f,0x7d,0xe5,
+ 0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0xe5,0x04,0xe6,0xe6,0x03,0xe6,0xe5,0x04,0xe5,
+ 0x09,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe8,0x70,
+ 0x01,0x09,0x07,0x01,0xe5,0x05,0x01,0x0b,0x1b,0x01,0x74,0x01,0x71,0x01,0x07,0x01,
+ 0x07,0x02,0x06,0x01,0x09,0x1d,0x75,0x01,0xe5,0x7c,0x09,0x09,0x08,0x93,0x03,0x76,
+ 0x04,0x01,0x02,0x04,0x04,0x04,0x01,0xa0,0x71,0x09,0x02,0x06,0x02,0x06,0xe5,0xe5,
+ 0x07,0x17,0x05,0x01,0xe5,0x71,0x02,0x01,0x0f,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x04,
+ 0x02,0x01,0x04,0x02,0x01,0x01,0x01,0x03,0x01,0x02,0x01,0x01,0x02,0x01,0x07,0x01,
+ 0x07,0x01,0x02,0x01,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x03,0xe6,0x72,0x01,0x05,
+ 0x01,0xe5,0x02,0x02,0x01,0xe5,0xa7,0xe6,0x5a,0x08,0x07,0x0b,0x01,0x06,0xe5,0xe5,
+ 0xe5,0xe5,0x03,0x13,0x10,0xe5,0x01,0x75,0xe9,0x6d,0x03,0x0a,0x10,0x0a,0x94,0xe5,
+ 0xe6,0x70,0x04,0x04,0x01,0xe5,0x05,0x01,0x04,0x02,0x01,0x04,0x01,0x02,0x13,0x08,
+ 0xe5,0x74,0x02,0x73,0x04,0x01,0xe5,0xe5,0x09,0x04,0x03,0x07,0x03,0x13,0x0a,0x73,
+ 0x01,0x41,0x26,0xe5,0x12,0x04,0x02,0x01,0x07,0x01,0x07,0x1a,0x05,0xe5,0x02,0x6e,
+ 0x01,0xe6,0x2f,0x0e,0xe5,0x20,0x04,0x01,0x0c,0x04,0x01,0x04,0x12,0x03,0x13,0x04,
+ 0x7b,0x03,0x41,0x29,0x12,0xe5,0x07,0x09,0x03,0x02,0x0a,0x8b,0xe6,0x4d,0x23,0x0f,
+ 0x01,0x0a,0xe6,0x02,0x02,0xe5,0x93,0x02,0xe5,0x3a,0x33,0x03,0x19,0x03,0x07,0x19,
+ 0x7b,0x02,0x45,0x05,0x1d,0x0a,0x09,0x13,0x1e,0x04,0xe5,0xe5,0xe5,0x08,0x68,0xe6,
+ 0xe6,0x3d,0x01,0x02,0x05,0xe5,0x21,0x07,0x07,0x04,0x05,0x10,0x16,0x01,0x07,0x09,
+ 0x67,0x02,0xe6,0x43,0x06,0x1a,0xe5,0x16,0xe5,0x07,0x25,0x01,0x08,0x04,0x03,0x01,
+ 0x6b,0xe7,0x32,0x06,0x01,0x2c,0x02,0x01,0x04,0x0f,0x0d,0x1b,0x03,0x05,0x0d,0x64,
+ 0xe6,0xe7,0x01,0x01,0x31,0xe5,0x02,0xe5,0x02,0xe5,0x21,0x01,0x1e,0x0c,0x0a,0x11,
+ 0x03,0x07,0x0b,0x61,0x01,0x04,0xe6,0x03,0x32,0x02,0x06,0x02,0x1f,0x01,0xe5,0x02,
+ 0x09,0x01,0xe5,0x03,0x07,0x29,0x06,0x01,0x05,0x6a,0x05,0x01,0xe5,0x01,0x2f,0xe5,
+ 0xe5,0xe5,0x08,0x25,0x13,0x06,0xe5,0xe5,0x0f,0xe5,0x16,0x7b,0x03,0x02,0x35,0x01,
+ 0x04,0x01,0x09,0x1e,0x01,0x02,0x09,0x0a,0x02,0xe5,0xe5,0x26,0x09,0x06,0x01,0x6c,
+ 0xe7,0x01,0x34,0x01,0x04,0xe5,0xe5,0xe5,0x02,0x1f,0x01,0x02,0x15,0x01,0xe5,0xe5,
+ 0xe5,0x06,0x04,0x01,0x04,0x01,0x04,0x0a,0x03,0x05,0x01,0x01,0x02,0x01,0x68,0x04,
+ 0xe7,0x35,0x05,0x29,0x13,0x01,0x04,0x02,0x06,0x16,0x0b,0x7d,0xe5,0xe7,0x34,0x01,
+ 0x07,0x01,0x25,0x04,0x08,0xe5,0x03,0x04,0xe7,0xe5,0x05,0xe6,0x01,0x02,0x1a,0x04,
+ 0x79,0xe5,0x01,0x45,0x09,0x02,0x21,0x0c,0x02,0x06,0x02,0x06,0x0b,0x02,0x10,0x02,
+ 0x06,0x02,0x6c,0xe7,0x3b,0xe5,0x07,0x01,0x07,0xe5,0x19,0x07,0xe6,0x07,0x02,0x09,
+ 0x06,0x04,0x09,0xe5,0x11,0xe5,0x07,0x6e,0xe8,0x0d,0x09,0x09,0x09,0x09,0x06,0x02,
+ 0x05,0xe5,0x01,0x09,0x09,0x09,0x09,0xe5,0x07,0x03,0xe5,0xe5,0x01,0x03,0x02,0x02,
+ 0x04,0x01,0x04,0x02,0x06,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x0d,0xe9,0x01,0x38,0x02,0x06,0x02,0x1d,0x04,0x09,0x0e,0x06,0x02,0x09,
+ 0x1f,0x72,0x03,0x02,0x3d,0x07,0x1d,0x11,0x0b,0x0a,0x08,0x1f,0x78,0xe5,0xe6,0xe5,
+ 0x32,0x01,0x07,0x09,0x01,0x1d,0x02,0x01,0x05,0xe6,0x03,0x01,0x02,0x03,0x02,0x09,
+ 0x02,0x26,0x07,0x04,0x63,0x04,0xe5,0x34,0x01,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x19,
+ 0x01,0x01,0x09,0x05,0x01,0x01,0x01,0xe5,0x04,0x03,0x02,0x03,0x01,0x08,0x14,0x05,
+ 0x01,0xe5,0x02,0x02,0x03,0x69,0xe5,0x34,0x01,0x07,0x08,0xe5,0x1e,0x0a,0x0d,0x04,
+ 0x10,0x04,0x11,0x0b,0x07,0x6a,0xe5,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,
+ 0xe5,0x04,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x06,0xe8,0x3e,0x09,0x01,0x28,0x10,0x01,0xe6,0x06,0x29,0x07,
+ 0x6b,0x01,0xe5,0x40,0x07,0x01,0x1d,0x1b,0x01,0x07,0x29,0x01,0x07,0x6e,0x35,0x01,
+ 0x07,0x0b,0x28,0x12,0x12,0x14,0x0b,0x07,0x6a,0x02,0xe5,0x34,0x01,0x09,0xe5,0x07,
+ 0x1d,0x02,0x09,0x09,0x07,0x0b,0x1a,0x04,0x04,0x01,0x07,0x04,0x65,0x01,0xe6,0x35,
+ 0x01,0x06,0xe5,0xe5,0x31,0x05,0x02,0x01,0x04,0xe5,0xe5,0x08,0x08,0x14,0x01,0x01,
+ 0x04,0x02,0x71,0xe6,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x01,0x03,
+ 0x01,0x02,0xe5,0x02,0x01,0x07,0x01,0xe5,0x02,0x04,0x01,0xe5,0x05,0x01,0x01,0x05,
+ 0x01,0x04,0x02,0xe6,0xe5,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0xe5,0x01,0x3b,0x09,0x1f,
+ 0x05,0x07,0xe5,0x05,0x03,0x0f,0x06,0x01,0x03,0x0d,0x06,0xe5,0x04,0xe5,0x0a,0xe5,
+ 0x66,0x01,0xe7,0x27,0x0e,0x03,0x26,0x0a,0x03,0x19,0x09,0x0c,0x0c,0xe5,0x0a,0x06,
+ 0x0f,0x58,0x01,0xe7,0x44,0x0c,0x04,0x16,0x03,0x05,0x20,0x05,0x24,0x6a,0x01,0xe5,
+ 0x34,0xe6,0x08,0x01,0x23,0x01,0xe5,0x04,0x04,0x05,0x01,0x07,0x06,0x0e,0x01,0x1b,
+ 0x02,0x04,0x6d,0x02,0x32,0x02,0x0a,0x07,0x1c,0x03,0x0f,0x03,0x03,0xe5,0x04,0x10,
+ 0x04,0x19,0x03,0x02,0x6e,0x03,0x3a,0x06,0x08,0xe5,0x08,0x08,0xe5,0x04,0x01,0x06,
+ 0x0c,0x01,0x19,0x01,0x01,0x04,0x19,0xe5,0x09,0x12,0x02,0x52,0xe5,0xe5,0x26,0x0d,
+ 0x01,0x07,0x02,0xe5,0x04,0x09,0x01,0x07,0x01,0x0c,0x09,0x04,0xe5,0x07,0x01,0x0c,
+ 0x04,0xe5,0x0c,0x06,0x01,0x07,0x1d,0xe5,0x55,0x01,0xe5,0x28,0x17,0xe5,0x05,0x04,
+ 0x07,0x26,0x18,0x02,0x0f,0x0f,0x1f,0x54,0xe6,0xe5,0x27,0x12,0x35,0xe5,0x07,0xe5,
+ 0x03,0x02,0xe7,0x05,0xe6,0x03,0x03,0x0b,0xe5,0x11,0xe5,0x20,0x51,0x01,0x01,0x39,
+ 0x09,0x20,0x08,0x05,0x09,0x09,0x09,0x06,0xe5,0x04,0x07,0x04,0x0b,0xe6,0x72,0xe5,
+ 0x01,0x30,0x06,0x13,0x05,0x01,0x01,0x0a,0x09,0x07,0xe5,0x02,0x03,0xe6,0x03,0x0d,
+ 0x0c,0x02,0x05,0xe5,0x08,0x01,0x23,0x01,0x54,0x03,0xe5,0x2d,0x06,0xe5,0x01,0x04,
+ 0x01,0xe5,0x01,0x05,0x09,0x04,0x01,0x02,0x1d,0x01,0x07,0x22,0x06,0x09,0x1d,0x53,
+ 0xe5,0xe5,0xe5,0x35,0x12,0x01,0x09,0x09,0x11,0x0b,0x01,0x06,0x13,0xe5,0x08,0x09,
+ 0x01,0x03,0x05,0x06,0x16,0x02,0x54,0xe7,0x32,0x09,0x09,0x10,0xe5,0x04,0x02,0xe5,
+ 0xe5,0x05,0xe5,0x04,0x02,0x01,0xe5,0x02,0xe5,0x03,0x05,0xe5,0x05,0x0a,0xe8,0x05,
+ 0x09,0x09,0x02,0xe5,0x04,0x64,0xe6,0x01,0xe5,0x01,0x01,0x30,0x09,0x06,0x01,0xe6,
+ 0x11,0x06,0x01,0xe5,0x03,0x01,0x01,0x01,0x01,0x02,0xe5,0x01,0xe5,0xe5,0x06,0x04,
+ 0xe5,0x04,0x0c,0x02,0x01,0x03,0x06,0x03,0x08,0x03,0xe5,0x16,0x4f,0x01,0x02,0xe5,
+ 0xe6,0x03,0x23,0x01,0x0a,0x02,0x06,0x09,0x01,0x07,0x0d,0x05,0x0b,0x07,0x01,0x03,
+ 0xe5,0x1c,0x01,0xe5,0x05,0x01,0x01,0xe5,0x04,0xe5,0x03,0x02,0x08,0x14,0x4c,0x04,
+ 0xe8,0x01,0x2e,0xe5,0x01,0xe5,0x07,0x09,0x01,0x04,0x02,0x09,0x09,0x10,0x02,0x01,
+ 0x24,0xe5,0xe5,0x08,0x05,0xe5,0x01,0x1f,0x51,0x06,0x35,0x02,0xe5,0x04,0x01,0x06,
+ 0xe5,0xe5,0x02,0x01,0xe6,0xe5,0x06,0x04,0x04,0x04,0x09,0x02,0x01,0x01,0x02,0x01,
+ 0x01,0xe5,0xe5,0x01,0x01,0x01,0x05,0x15,0x03,0xe5,0x04,0x02,0xe5,0x03,0x01,0x01,
+ 0x05,0x17,0x4e,0x01,0xe5,0x01,0x2c,0x05,0x02,0xe5,0x06,0x01,0x03,0x01,0x01,0x07,
+ 0x01,0x01,0x05,0x01,0x02,0xe5,0x01,0xe5,0x02,0x09,0x01,0x02,0xe5,0xe5,0xe5,0x03,
+ 0x05,0x03,0x0e,0x01,0x02,0x01,0x04,0x02,0xe7,0x07,0xe5,0x02,0x04,0x16,0x01,0x01,
+ 0x01,0xe5,0x49,0x02,0x03,0xe5,0x35,0x04,0x01,0xe5,0xe5,0x06,0x01,0x09,0x07,0x09,
+ 0x03,0x02,0x01,0x04,0x01,0xe5,0x01,0x01,0x01,0x03,0x01,0x01,0x02,0x02,0x05,0x01,
+ 0xe5,0x17,0x07,0x01,0x01,0x01,0xe5,0x01,0x05,0x0c,0x02,0x50,0x04,0xe6,0xe6,0x2a,
+ 0x0b,0x04,0x01,0x02,0x07,0x01,0x09,0x07,0x01,0x02,0x04,0x04,0x09,0x01,0x01,0xe5,
+ 0xe5,0x01,0x04,0x01,0x02,0x01,0x01,0x05,0x01,0x01,0x04,0x0b,0xe5,0x03,0x09,0x04,
+ 0x09,0x01,0x01,0x08,0x03,0x54,0x01,0x01,0x31,0x02,0x03,0x02,0x02,0x06,0x09,0xe5,
+ 0x18,0x09,0x02,0x02,0x03,0x0c,0x06,0x0e,0x02,0x03,0x02,0x1a,0x16,0x52,0xe6,0x31,
+ 0x09,0xe5,0x07,0x01,0x04,0x02,0x09,0xe5,0x05,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x0d,
+ 0x03,0xe5,0x0d,0x05,0xe6,0xe5,0xe5,0x03,0x02,0xe5,0x07,0x05,0xe5,0x01,0x15,0x4f,
+ 0x01,0xe5,0x0d,0x09,0x09,0x09,0x02,0x02,0x03,0x02,0x06,0x04,0xe6,0x01,0xe6,0xe6,
+ 0xe5,0x01,0x09,0x09,0xe6,0x06,0xe6,0x03,0x02,0xe6,0x06,0x09,0xe6,0x08,0x03,0x05,
+ 0xe5,0x01,0x02,0x02,0x09,0x05,0x03,0xe6,0xe6,0xe5,0x01,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x04,0x01,0x06,0x01,0x02,0x02,0x31,0x09,0x09,0x09,0x09,0x04,0x09,
+ 0x0b,0x02,0x09,0x24,0x03,0xe5,0x1c,0x09,0x4f,0x04,0x03,0xe5,0xe5,0x31,0x08,0x0b,
+ 0x07,0x0a,0x1d,0x08,0x27,0x03,0x1c,0x08,0x50,0x0a,0x01,0xe5,0xe5,0x28,0x01,0x07,
+ 0x02,0x06,0x01,0x09,0x01,0x05,0x01,0x09,0x02,0x07,0x01,0x07,0xe6,0x05,0xe5,0xe5,
+ 0x02,0xe5,0xe5,0x05,0xe5,0x01,0xe6,0x07,0x04,0x05,0x01,0x04,0x01,0x02,0x04,0x01,
+ 0x07,0x01,0xe7,0x03,0x04,0x04,0x01,0x52,0x01,0xe8,0x2a,0x01,0xe5,0x05,0x01,0x0a,
+ 0x06,0x01,0xe6,0x04,0x01,0xe5,0x07,0x01,0x09,0x08,0xe5,0x01,0x01,0xe5,0x01,0xe5,
+ 0x04,0x01,0xe6,0x01,0x04,0xe6,0x03,0x04,0xe5,0x02,0x05,0xe5,0x04,0x01,0xe6,0xe5,
+ 0x01,0xe5,0xe7,0x04,0x01,0xe6,0x06,0x01,0x04,0xe5,0xe6,0x52,0x03,0x35,0x01,0x0e,
+ 0x01,0x02,0x07,0x01,0x09,0x04,0x0c,0x03,0x07,0x03,0x05,0x07,0x08,0x02,0x01,0x0e,
+ 0x04,0x10,0x04,0x01,0x03,0x0b,0x54,0xe5,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x01,0x04,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x06,
+ 0xe7,0x05,0xe7,0x04,0xe8,0xe5,0x02,0xe7,0x01,0xe5,0x02,0xe6,0x01,0x01,0x05,0xe5,
+ 0x07,0xe6,0x06,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,
+ 0x37,0x07,0x01,0x09,0x09,0x09,0x0e,0x0e,0x07,0x01,0xe5,0x05,0x01,0xe6,0x08,0x11,
+ 0x01,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x09,0x01,0x54,0xe8,0x4a,0x07,0x01,0x07,
+ 0x12,0x07,0x01,0xe5,0xe5,0x02,0x02,0xe5,0xe6,0x01,0x02,0xe5,0xe5,0x05,0x04,0x07,
+ 0x09,0x01,0x07,0x01,0x07,0x01,0x09,0x07,0x01,0x54,0x01,0x01,0x3f,0x15,0x09,0x0f,
+ 0x0d,0x04,0xe5,0x02,0x04,0xe5,0xe5,0xe5,0x03,0x03,0xe5,0xe5,0x12,0x0a,0x09,0x06,
+ 0x61,0xe7,0x40,0x0c,0x04,0x09,0x04,0x09,0xe5,0xe6,0x04,0x01,0x01,0xe5,0xe5,0x01,
+ 0xe5,0xe6,0x01,0xe5,0xea,0xe5,0x01,0x03,0x02,0x01,0x0c,0x04,0x01,0x02,0x09,0x09,
+ 0x06,0x02,0x06,0x55,0x01,0xe5,0x2a,0x01,0xe5,0x03,0x01,0x09,0xe5,0xe5,0x05,0x02,
+ 0x06,0x09,0xe5,0xe5,0x05,0x01,0xe6,0x04,0x02,0x06,0x09,0x03,0x14,0x06,0xe5,0xe5,
+ 0x08,0xe5,0x06,0xe5,0x19,0x02,0x52,0xe6,0x01,0x01,0x0f,0x01,0x07,0x01,0x07,0x01,
+ 0x04,0x02,0x01,0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0x02,0xe5,0x02,0x01,0x04,0x02,
+ 0x01,0x03,0x03,0x01,0x04,0x02,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x06,0xe5,0xe5,
+ 0x01,0x04,0x01,0x04,0x04,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0xe6,0x03,0x02,0xe6,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x0a,0x01,0x01,0x32,0x03,0xe6,0x02,0x0c,0x20,0x03,0x02,0x0a,0x07,0x01,
+ 0x11,0x02,0x01,0xe5,0x07,0xe5,0x02,0x02,0x01,0xe5,0xe5,0x06,0x02,0x05,0xe6,0x08,
+ 0x05,0x57,0x02,0xe5,0x27,0x09,0x01,0x0e,0xe5,0xe5,0x07,0x01,0x09,0x07,0x01,0x01,
+ 0x15,0x03,0x05,0x02,0x01,0x0c,0xe5,0x0a,0x01,0x01,0xe5,0x01,0x01,0x02,0x03,0x01,
+ 0x04,0xe7,0xe6,0x66,0x01,0xe5,0xe5,0x36,0xe5,0x1e,0x02,0x0a,0x09,0x09,0x03,0x01,
+ 0x14,0x03,0x03,0xe5,0x05,0x06,0x11,0x0c,0x62,0xe6,0xe5,0x04,0x22,0x02,0x04,0x04,
+ 0x01,0x02,0x06,0x09,0x05,0x01,0x06,0x02,0x13,0xe5,0x09,0x07,0x01,0x01,0x05,0x01,
+ 0x13,0xe7,0x07,0x09,0x05,0x14,0xe7,0x02,0x4f,0x02,0x01,0x05,0x28,0x09,0x02,0x04,
+ 0x05,0xe5,0x09,0x02,0x09,0x1b,0x05,0xe5,0x02,0x01,0x03,0x05,0x02,0xe5,0x01,0x0c,
+ 0x08,0x06,0x02,0x1e,0x55,0x01,0x01,0x2c,0xe5,0x06,0x13,0x05,0x0e,0xe5,0x02,0x12,
+ 0x10,0x01,0x05,0xe6,0x06,0x05,0x11,0xe5,0xe5,0x04,0xe5,0x1c,0x53,0x01,0xe5,0xe5,
+ 0x04,0x2a,0x04,0x01,0x07,0x02,0x04,0x01,0x07,0x01,0x01,0x07,0x02,0x0c,0x0b,0x01,
+ 0x01,0xe5,0x05,0x02,0x06,0x01,0xe6,0x04,0x04,0x09,0x02,0x03,0x09,0x01,0x19,0x01,
+ 0xe5,0x54,0xe5,0xe6,0x2e,0x11,0x05,0x01,0x15,0x27,0xe5,0x0f,0x0f,0x05,0x02,0x26,
+ 0x04,0x4f,0x02,0xe5,0x2d,0xe5,0x08,0xe6,0x05,0xe5,0x30,0xe5,0x09,0x03,0x01,0x03,
+ 0xe5,0x08,0x02,0x07,0x03,0xe6,0x06,0xe6,0xe6,0x08,0x03,0xe7,0x10,0xe5,0x54,0x02,
+ 0xe5,0x3a,0x1b,0x1f,0x08,0x18,0x0e,0x03,0x05,0x13,0x10,0xe5,0x55,0xe7,0x33,0x02,
+ 0x09,0x02,0xe5,0x0a,0x03,0x0a,0x19,0x0a,0x01,0x03,0x16,0xe5,0x02,0x04,0x04,0x09,
+ 0x0a,0x0d,0x02,0x01,0x53,0xe5,0x02,0xe5,0x29,0x01,0x09,0x09,0x07,0x01,0x09,0x06,
+ 0x02,0xe5,0x12,0x10,0x01,0x02,0x04,0x01,0xe6,0x01,0x10,0x09,0xe5,0x01,0x02,0xe5,
+ 0xe5,0x1c,0x01,0x54,0x01,0x35,0x01,0x07,0xe5,0x11,0x01,0x09,0x15,0x09,0x04,0x20,
+ 0xe5,0x07,0xe5,0x07,0x08,0x0e,0x01,0x05,0x55,0xe9,0x2f,0xe5,0x0a,0x1a,0xe5,0x04,
+ 0x09,0x02,0x01,0x04,0x05,0x09,0x23,0x05,0x02,0xe5,0x04,0x05,0xe5,0x05,0x0c,0x01,
+ 0x04,0x50,0xe6,0x01,0xe5,0x01,0x01,0x30,0xe5,0x02,0x04,0x01,0x18,0xe5,0xe5,0x04,
+ 0xe5,0x05,0x0f,0xe5,0x07,0x22,0x06,0xe5,0xe5,0x05,0xe5,0x03,0xe5,0x04,0x0c,0xe5,
+ 0x04,0x4e,0x01,0x02,0xe8,0x03,0x2d,0xe5,0x02,0x03,0xe5,0x08,0xe5,0x06,0xe5,0x06,
+ 0x08,0x13,0x05,0x01,0x02,0x04,0x04,0x01,0xe5,0x20,0x06,0xe5,0xe5,0xe5,0x17,0x01,
+ 0x02,0x4f,0x06,0x01,0x02,0x2e,0xe5,0x01,0x05,0xe5,0x01,0x06,0xe5,0x06,0xe5,0x0b,
+ 0x1a,0x02,0x01,0x07,0x06,0x1e,0xe5,0x01,0x05,0xe5,0x01,0x01,0x18,0x02,0x53,0x03,
+ 0xe5,0xe5,0x2a,0x01,0x02,0x06,0x24,0xe5,0x03,0x09,0x09,0x02,0x01,0x01,0xe5,0x04,
+ 0xe5,0xe5,0x01,0x01,0xe6,0x01,0x04,0x01,0x0c,0x09,0x02,0x03,0x01,0xe5,0xe6,0x0a,
+ 0x0c,0x01,0x08,0x47,0x08,0xe5,0x01,0x02,0x25,0x04,0xe5,0x01,0xe5,0x02,0x01,0x02,
+ 0x04,0x02,0x01,0x04,0x01,0x02,0x04,0x02,0xe7,0xe5,0x01,0x03,0x14,0x01,0xe5,0x01,
+ 0x01,0xe6,0x02,0x09,0x04,0x0c,0x09,0x02,0x06,0x01,0xe5,0x01,0x02,0x14,0x03,0x03,
+ 0xe5,0x49,0x04,0x01,0xe5,0x29,0x01,0x02,0x04,0x01,0x25,0x07,0x05,0x01,0xe5,0x07,
+ 0xe5,0x01,0x01,0x07,0x01,0x07,0x01,0x05,0x0d,0x09,0x09,0x01,0x1b,0x01,0x05,0x48,
+ 0x04,0xe6,0xe6,0x2a,0x04,0x01,0x01,0x14,0x09,0x09,0x01,0x02,0x09,0x01,0x01,0x04,
+ 0xe5,0xe5,0xe6,0xe6,0x05,0x01,0x01,0xe5,0xe5,0x01,0x15,0x04,0x04,0x02,0x06,0x01,
+ 0xe5,0x09,0xe5,0x0d,0x5a,0x05,0x2b,0x02,0x10,0xe5,0x1b,0x02,0x03,0x09,0x09,0x09,
+ 0x04,0x07,0x02,0x19,0x09,0x02,0x02,0x03,0x6a,0xe5,0x3b,0xe5,0x23,0x01,0xe5,0x03,
+ 0xe6,0x06,0xe6,0x10,0xe5,0x0b,0x12,0x09,0x0c,0x05,0xe5,0x12,0x02,0x4f,0xe9,0x0d,
+ 0x09,0x09,0x09,0x09,0x06,0x02,0x02,0x06,0x02,0x01,0x01,0x02,0x09,0x09,0xe6,0x06,
+ 0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0x05,0x05,0x06,0x02,0x09,0xe6,0x03,0x02,0xe5,
+ 0x01,0x05,0xe5,0x07,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x06,0x01,
+ 0x01,0xe5,0x01,0x27,0x09,0x06,0x02,0x13,0x09,0x04,0x09,0x09,0x0b,0x0c,0x12,0x02,
+ 0x09,0x06,0x02,0x09,0x13,0x4e,0xe5,0x03,0x02,0xe8,0x28,0x08,0x0a,0x11,0x0a,0x1a,
+ 0x13,0x03,0x14,0x08,0x0b,0x08,0x06,0x0d,0x05,0x48,0x0c,0xe5,0xe5,0x25,0x07,0x10,
+ 0x07,0x01,0x07,0x01,0x09,0x02,0x07,0xe6,0xe5,0x04,0xe6,0x03,0x01,0xe5,0x07,0xe5,
+ 0xe5,0x03,0x12,0x02,0x04,0x07,0x01,0x04,0x01,0xe5,0x08,0x01,0x0e,0x01,0x02,0x4f,
+ 0x05,0x02,0x28,0x01,0x01,0x05,0x02,0x09,0x08,0xe5,0x08,0x08,0x01,0x09,0x09,0x05,
+ 0x01,0x07,0x01,0xe6,0x04,0x01,0xe5,0x0e,0x06,0x01,0x05,0x01,0x05,0x01,0x0a,0xe5,
+ 0x0b,0x02,0x01,0xe6,0x52,0x02,0x49,0x01,0x06,0xe5,0xe5,0x08,0x0b,0x09,0x01,0x03,
+ 0x01,0x04,0x04,0x06,0x16,0x13,0x01,0x07,0x10,0x02,0x01,0x57,0xe5,0x14,0xe5,0x07,
+ 0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe6,0x06,
+ 0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x01,0x05,0xe5,0x09,0xe5,0x07,
+ 0xe5,0x01,0x03,0x01,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x03,
+ 0x53,0x01,0x09,0x14,0x06,0x01,0x09,0xe5,0x07,0x27,0x01,0x07,0x01,0x6c,0xe5,0x02,
+ 0x01,0x24,0x01,0x31,0x1b,0x01,0x07,0x01,0xe5,0x2b,0x01,0x01,0x01,0x07,0x01,0x11,
+ 0x56,0xe5,0xe6,0x05,0x30,0x1b,0x01,0x09,0x14,0x12,0x07,0x01,0x08,0x20,0x07,0x6e,
+ 0x01,0x01,0xe5,0x2a,0x07,0x24,0x04,0x09,0x09,0x0e,0x04,0x04,0x1a,0x09,0xe5,0x02,
+ 0x01,0x09,0x02,0x13,0x4c,0x06,0xe7,0x02,0x26,0x02,0x06,0x02,0x08,0xe5,0x05,0xe5,
+ 0xe5,0x05,0x01,0xe5,0x05,0x02,0x1a,0x02,0x06,0x02,0x06,0xe5,0xe6,0x10,0x0b,0xe5,
+ 0x03,0x01,0x02,0x1a,0xe5,0xe5,0x51,0xe6,0xe6,0x02,0x0d,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x02,0xe5,0x02,0x01,0x02,0xe5,0x02,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0xe5,0x05,0x01,0x04,0x02,0x01,0x04,0x02,0xe6,0x02,0x03,
+ 0x01,0x04,0x04,0x01,0x01,0x02,0x02,0x01,0xe5,0x05,0xe6,0xe5,0xe5,0x02,0xe6,0x06,
+ 0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x05,0xe5,0x02,0x01,0xe7,0x01,0x27,0xe5,0x06,0xe5,0x02,0x1f,
+ 0x03,0xe5,0x09,0xe6,0x06,0xe5,0x03,0x01,0x04,0x03,0xe5,0x07,0x09,0x15,0x0a,0x1b,
+ 0xe5,0x51,0x05,0xe5,0xe6,0x12,0x1c,0x07,0x13,0x0a,0x03,0x06,0x04,0x05,0x04,0x05,
+ 0x44,0x17,0x56,0x01,0x02,0x28,0x11,0x03,0x09,0x1d,0x02,0x06,0xe5,0x02,0x01,0x08,
+ 0x08,0x02,0x0c,0xe5,0x05,0x0a,0x09,0x01,0x09,0x04,0x13,0x52,0x03,0x2d,0x0a,0x08,
+ 0x01,0x02,0x02,0x02,0x1f,0x01,0x0c,0xe7,0x02,0x05,0x08,0xe5,0x11,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x69,0xe6,0xe6,0x3f,0x02,0x07,0x10,0x1d,0x01,0x06,0x07,0x04,
+ 0x08,0x0e,0x09,0x09,0x08,0x04,0x63,0x01,0xe6,0x2a,0x01,0x0a,0x07,0xe5,0x27,0x05,
+ 0x02,0x01,0x08,0x16,0xe5,0x01,0xe5,0x09,0x09,0xe6,0x06,0xe6,0x01,0x03,0x1a,0xe5,
+ 0x4d,0xe9,0x3e,0x07,0x10,0x18,0x13,0x01,0xe5,0x04,0x0a,0x15,0x02,0x06,0x01,0x0d,
+ 0x0d,0x57,0x02,0x2e,0xe5,0x03,0x0c,0x2f,0x02,0x01,0x1c,0x05,0x05,0x0a,0x01,0x02,
+ 0x03,0x0a,0x03,0x16,0x04,0x06,0x48,0xe5,0x01,0x05,0x2f,0xe6,0x09,0x06,0xe6,0x16,
+ 0x13,0x14,0x02,0x09,0xe5,0x08,0x09,0xe6,0xe5,0x01,0x02,0x04,0x0f,0x62,0x01,0x34,
+ 0x03,0x01,0x08,0x08,0x21,0x0a,0x0f,0x05,0x05,0x01,0x01,0x15,0xe5,0x0e,0x06,0x05,
+ 0x0d,0x53,0x02,0x2d,0xe5,0x01,0x03,0x01,0x03,0x05,0x01,0x01,0x26,0x0d,0x0c,0x13,
+ 0x01,0x07,0x01,0xe5,0x0a,0x0a,0x0a,0xe5,0x0c,0x53,0xe6,0x01,0xe5,0x2b,0xe5,0x07,
+ 0x08,0xe5,0x0c,0x37,0xe5,0x13,0x03,0x05,0x1e,0x02,0x05,0x08,0xe5,0x49,0x09,0xe6,
+ 0xe5,0x04,0x25,0x01,0x08,0x0a,0x1f,0x14,0x0e,0x01,0x0d,0x07,0x08,0x0c,0x16,0x03,
+ 0x07,0x01,0x57,0xe8,0x36,0x08,0xe5,0x08,0xe5,0x07,0x09,0xe5,0x07,0x09,0x05,0x06,
+ 0xe5,0x04,0x09,0x01,0xe5,0x07,0x09,0x09,0x02,0xe5,0xe5,0x02,0xe5,0x03,0x0d,0x05,
+ 0x0d,0x46,0xe5,0xe5,0xe6,0x01,0x01,0x2d,0xe5,0x0e,0x07,0x01,0x06,0x02,0x06,0x02,
+ 0x06,0x02,0x07,0x01,0x05,0x04,0x01,0x01,0x01,0x08,0x02,0x02,0xe5,0x0a,0x01,0x0e,
+ 0x02,0xe5,0xe6,0x01,0x05,0x0c,0x06,0xe5,0x0b,0x43,0x01,0x04,0x01,0x04,0x23,0x01,
+ 0xe5,0xe5,0x0a,0x01,0xe5,0x01,0x02,0x0d,0x09,0x09,0x09,0xe5,0x02,0x07,0x05,0xe5,
+ 0x01,0x01,0x01,0x02,0x01,0x02,0x0d,0x09,0x02,0xe5,0x02,0x04,0xe5,0xe5,0xe5,0x06,
+ 0x10,0xe5,0x02,0x07,0x47,0x05,0xe7,0x01,0x25,0x02,0x14,0x01,0x08,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x04,0xe5,0x0a,0x09,0x01,0x04,0xe5,0xe5,0xe5,0x19,
+ 0x02,0x06,0x02,0x01,0x07,0x10,0xe5,0xe5,0x05,0x02,0x49,0x02,0xe5,0xe6,0x28,0x01,
+ 0x01,0x02,0x0e,0x02,0x0b,0xe5,0x01,0x02,0x02,0x01,0x01,0x02,0x02,0xe5,0x01,0x02,
+ 0x02,0x01,0x01,0xe5,0x05,0x01,0xe5,0x08,0x01,0x03,0x02,0x09,0x07,0x0c,0x01,0x05,
+ 0x01,0xe6,0xe5,0x01,0x04,0x15,0x05,0xe5,0x04,0x47,0xe8,0x01,0x28,0x04,0xe5,0x01,
+ 0x0d,0xe5,0xe5,0x01,0x02,0x02,0x09,0x03,0x05,0x09,0x03,0x04,0x04,0xe5,0x02,0x05,
+ 0x01,0x01,0x05,0x06,0xe6,0x15,0x03,0x02,0x01,0xe5,0xe5,0xe5,0x04,0x03,0x0f,0x03,
+ 0x01,0x01,0xe5,0x04,0x45,0x03,0xe7,0x38,0x04,0x04,0x13,0x02,0x10,0x02,0x09,0x01,
+ 0x04,0x04,0x01,0x03,0xe5,0x03,0x0f,0xe5,0x0b,0x01,0x07,0x01,0x01,0x05,0x15,0x09,
+ 0x4b,0x02,0x30,0xe6,0x06,0x10,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x04,0x09,0x04,
+ 0x01,0x02,0x01,0x04,0x01,0xe5,0xe5,0x01,0x0a,0xe5,0xe5,0xe5,0x04,0x04,0x04,0x04,
+ 0x01,0x02,0x04,0x13,0x0b,0x02,0x47,0xe8,0x04,0xe5,0x01,0xe5,0x25,0x02,0x06,0x02,
+ 0x03,0x02,0x03,0x09,0x05,0x03,0x05,0x03,0x05,0x09,0x0b,0x11,0x02,0x05,0x3e,0x50,
+ 0x01,0xe6,0x04,0x04,0x31,0x09,0x01,0x10,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,
+ 0x05,0x09,0x02,0x06,0xe5,0x08,0xe6,0x11,0x0a,0x21,0x51,0xe5,0x07,0x05,0x09,0x09,
+ 0x09,0x09,0x05,0xe5,0x01,0x03,0x05,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0x02,0x09,
+ 0x09,0x05,0xe5,0x01,0x0b,0xe5,0x04,0x02,0x06,0x02,0x06,0x02,0x02,0x06,0x09,0x09,
+ 0x06,0x02,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x06,0x02,0x01,0x02,0x31,0x06,0x16,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x04,0xe5,0x08,0x09,0x08,0xe5,0x03,0x0b,
+ 0x01,0x0b,0xe5,0x07,0x14,0x09,0x06,0x02,0x44,0x05,0x02,0x01,0x01,0x33,0x1c,0x05,
+ 0x03,0x05,0x03,0x05,0x04,0x09,0x05,0x03,0x05,0x03,0x11,0x0d,0x05,0x17,0x07,0x0a,
+ 0x50,0xe7,0x27,0x07,0x04,0x01,0x0a,0x15,0x09,0x09,0x09,0x01,0x04,0x02,0x03,0xe5,
+ 0xe5,0x01,0x04,0x01,0x02,0x01,0x06,0xe7,0x0f,0x02,0x01,0x02,0x01,0x02,0x0b,0x02,
+ 0x04,0x13,0x45,0x03,0xe6,0x2e,0x05,0x01,0x01,0x04,0xe5,0xe5,0x0a,0x09,0x09,0x09,
+ 0x09,0x02,0x02,0x03,0x05,0x01,0xe6,0x04,0x01,0x01,0x01,0x07,0xe6,0x08,0x05,0x03,
+ 0x02,0x02,0x01,0x01,0x0c,0x06,0x08,0x0a,0x49,0xe5,0xe6,0x26,0x0e,0x09,0x0d,0x03,
+ 0x09,0x09,0x06,0x0e,0x04,0x02,0x01,0x03,0xe5,0x0a,0x04,0x01,0x11,0x03,0x03,0x01,
+ 0x11,0x09,0x01,0x54,0xe5,0xe6,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe6,0x06,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x03,0xe6,0x08,0xe6,
+ 0x06,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x03,0x05,0xe5,0x07,0xe6,0x06,0xe6,0xe5,0x04,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0a,0x2b,0x01,0x09,0xe5,0x07,0x0a,0x06,0x09,0x09,
+ 0x07,0x01,0x0b,0xe5,0x05,0x01,0xe6,0x06,0x0b,0xe5,0x05,0x01,0x0a,0x08,0x11,0x15,
+ 0x4a,0x01,0xe6,0x2a,0x01,0x07,0x01,0xe5,0x05,0x0c,0x08,0x09,0x09,0x06,0x02,0x07,
+ 0x01,0x07,0x01,0x07,0x0d,0xe5,0x12,0x06,0x07,0x1f,0x4e,0xe6,0x2c,0x09,0x09,0x2b,
+ 0xe6,0x02,0x09,0xe5,0x07,0x09,0x08,0x02,0x07,0x01,0x13,0x11,0x15,0x4a,0xe8,0x2c,
+ 0x02,0x06,0xe5,0xe5,0x03,0x0c,0x01,0x09,0x09,0x09,0xe6,0x01,0x04,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x04,0x08,0x02,0x09,0x09,0x04,0x04,0xe5,0x11,0x0e,0x04,0x47,
+ 0x01,0xe6,0x2a,0xe5,0xe5,0x12,0xe5,0x04,0x04,0x04,0x03,0x05,0x09,0x09,0x01,0xe5,
+ 0x05,0x01,0xe6,0x04,0x09,0xe5,0xe5,0x1b,0x02,0x06,0x09,0xe5,0xe5,0x0f,0x02,0x06,
+ 0x02,0x4a,0x02,0x11,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,
+ 0x03,0x03,0x01,0x03,0x03,0x01,0x03,0x03,0x01,0x02,0xe5,0x02,0x01,0x03,0x03,0x01,
+ 0x04,0x02,0xe7,0xe6,0x02,0x01,0x01,0x02,0x02,0x01,0xe5,0x02,0x04,0x01,0x06,0xe5,
+ 0xe5,0x02,0x03,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02,0x01,0x03,
+ 0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe6,
+ 0xe5,0x2e,0x0f,0x02,0x05,0x02,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x06,0xe5,
+ 0x07,0xe5,0x01,0x2d,0x01,0xe5,0x06,0xe6,0x06,0x12,0x09,0x01,0xe5,0x4c,0x01,0x30,
+ 0x05,0x06,0x11,0x0a,0x1a,0x03,0x26,0x0c,0x01,0x07,0x21,0x06,0x4a,0x02,0xe7,0x45,
+ 0x01,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x03,0x05,
+ 0x02,0x0b,0x0c,0xe5,0x05,0x15,0x03,0x26,0x4c,0xe8,0x02,0x01,0x26,0x09,0x07,0x01,
+ 0xe5,0x0e,0x02,0x05,0x01,0xe5,0x09,0x02,0x04,0x01,0x03,0x03,0x01,0x02,0x04,0x01,
+ 0xe5,0x07,0xe5,0x11,0x09,0xe5,0x01,0x02,0x02,0x01,0x10,0x0d,0x03,0x02,0xe5,0x49,
+ 0x01,0x01,0xe6,0x02,0x30,0x0b,0x0d,0x1f,0x03,0x0a,0x05,0xe5,0x01,0x02,0x04,0x02,
+ 0x05,0x0e,0x13,0x02,0x1d,0x50,0x02,0xe6,0x02,0x01,0x24,0x0a,0xe5,0x06,0x13,0x0d,
+ 0x01,0x03,0x09,0x04,0x04,0x0b,0x09,0x07,0x03,0x02,0x01,0x06,0x0b,0x01,0x01,0x1e,
+ 0xe5,0x01,0x05,0xe5,0x48,0xe5,0xe5,0xe5,0x02,0x05,0x21,0x01,0xe5,0x05,0x02,0x0b,
+ 0x11,0x06,0x01,0x2f,0xe5,0x01,0x05,0xe7,0x0c,0x04,0x11,0x13,0x01,0x02,0x05,0x42,
+ 0x0a,0xe5,0x01,0xe5,0x35,0x1f,0x04,0x05,0x03,0x05,0x08,0x12,0xe5,0x04,0x04,0x04,
+ 0x01,0x03,0x09,0x05,0x0d,0x03,0xe5,0x13,0x06,0x53,0xe5,0x3c,0xe7,0x10,0xe5,0x06,
+ 0x09,0xe6,0x06,0xe6,0x03,0x0b,0x04,0x10,0x0b,0xe5,0x03,0x06,0x06,0xe6,0x06,0xe5,
+ 0x07,0xe5,0x11,0x01,0x08,0x44,0xe5,0x30,0xe6,0x0c,0x10,0x03,0x12,0x07,0xe5,0x25,
+ 0x05,0x08,0x12,0x0a,0x08,0x03,0x1a,0x3f,0x02,0xe5,0x4f,0x01,0x01,0xe5,0x06,0x01,
+ 0x08,0x04,0xe5,0x06,0xe5,0x01,0x02,0x09,0xe5,0x03,0x01,0x01,0x09,0x01,0x08,0x03,
+ 0x06,0x12,0x03,0x05,0x03,0x04,0x01,0x03,0x05,0x0e,0x3b,0x03,0x37,0x1a,0x01,0x01,
+ 0xe5,0x02,0x03,0xe5,0x03,0x0f,0x0a,0xe5,0x03,0x2a,0xe5,0x01,0x02,0x20,0x02,0x05,
+ 0xe6,0x03,0x44,0xe6,0xe5,0x2e,0x06,0x02,0x15,0x0e,0x0c,0x04,0x0a,0x03,0x01,0x2d,
+ 0x01,0x1f,0xe5,0x05,0x09,0x02,0x15,0x32,0xe5,0xe7,0x2c,0xe5,0x28,0xe5,0xe5,0x01,
+ 0xe5,0x08,0x05,0x03,0xe7,0x01,0x06,0xe5,0x04,0x05,0x06,0xe5,0x02,0x03,0x09,0x13,
+ 0x02,0x01,0x04,0x02,0xe5,0x04,0x13,0x09,0x3c,0xe5,0xe8,0x01,0x01,0x2a,0x2a,0xe5,
+ 0xe5,0x08,0xe5,0x01,0x05,0x02,0x02,0xe5,0x02,0xe5,0x02,0xe5,0x05,0xe5,0x03,0xe6,
+ 0x03,0xe5,0x02,0x0d,0x05,0x0c,0x02,0xe5,0x08,0x01,0x11,0x01,0x03,0x09,0x3a,0x01,
+ 0x03,0x01,0xe5,0x03,0x26,0x09,0x01,0x17,0xe5,0x01,0x01,0x09,0x01,0x07,0x07,0x05,
+ 0xe5,0x01,0x01,0x09,0x07,0x01,0x09,0x03,0x0f,0x01,0x09,0x0b,0x09,0x01,0xe5,0x08,
+ 0x01,0x48,0x05,0xe5,0xe5,0x01,0x25,0xe5,0xe5,0x04,0xe5,0x01,0x01,0x22,0x04,0x07,
+ 0x09,0x0b,0x04,0xe5,0x0a,0x01,0x09,0x10,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0x18,0xe5,
+ 0x08,0xe5,0x4a,0x02,0xe5,0xe6,0x2f,0x06,0x0c,0x0e,0x01,0x02,0xe5,0xe6,0x01,0x09,
+ 0x02,0x03,0xe5,0x03,0x04,0x01,0x02,0x04,0x01,0x02,0xe5,0x01,0x02,0x02,0x08,0x06,
+ 0x05,0x06,0x06,0x05,0x01,0x01,0x05,0x09,0x07,0x05,0xe5,0x03,0x01,0x01,0x05,0x3d,
+ 0xe6,0xe5,0x01,0x2d,0xe5,0x01,0x02,0x01,0x1d,0x04,0xe5,0x07,0xe5,0x02,0x03,0xe6,
+ 0x02,0x07,0x01,0x04,0xe5,0xe5,0xe5,0x03,0xe5,0x03,0x03,0x02,0x06,0xe6,0x09,0x03,
+ 0x03,0xe5,0x04,0xe5,0x01,0x16,0x04,0xe7,0x03,0x44,0x04,0x01,0xe5,0x29,0x01,0x07,
+ 0x01,0x0b,0xe5,0xe5,0x0b,0x01,0x05,0x03,0x05,0x03,0x01,0xe8,0xe5,0x02,0x02,0x06,
+ 0x03,0x01,0x01,0x01,0x03,0x03,0x04,0xe5,0x04,0x0d,0xe5,0x01,0x01,0x05,0x03,0x25,
+ 0x01,0x02,0x08,0x3d,0x02,0xe6,0x2a,0x04,0x04,0x01,0x0c,0x01,0xe6,0x0d,0x05,0x09,
+ 0x04,0x01,0x01,0xe5,0x03,0x01,0xe5,0x05,0x01,0x02,0x01,0x02,0x04,0x04,0x01,0xe5,
+ 0x02,0x04,0x08,0xe5,0xe5,0xe6,0xe5,0x06,0x04,0x08,0xe5,0x07,0xe5,0x12,0x09,0x01,
+ 0x01,0x39,0xe5,0xe6,0x3a,0x02,0x03,0x13,0x0c,0xe5,0x04,0x0e,0x09,0x13,0x09,0x02,
+ 0x03,0x0c,0x10,0x09,0x13,0x09,0x43,0x3c,0x05,0xe5,0x12,0x02,0x06,0x02,0xe5,0x03,
+ 0xe5,0x1d,0x09,0x01,0x08,0xe5,0x06,0xe6,0x0a,0xe6,0x06,0x05,0xe6,0x06,0xe6,0x0a,
+ 0xe5,0x04,0x02,0xe5,0x03,0xe5,0x3e,0xe8,0x0d,0x09,0x09,0x09,0x06,0x02,0x02,0xe5,
+ 0x04,0xe6,0x06,0x04,0x01,0x02,0x01,0x01,0x02,0x02,0x09,0xe6,0x06,0x09,0x02,0x01,
+ 0x01,0x02,0x09,0x03,0x07,0x09,0xe5,0x02,0x01,0x02,0x04,0x01,0x02,0x05,0x03,0xe5,
+ 0x07,0xe5,0x07,0x02,0x03,0x02,0x01,0x07,0xe6,0x06,0x09,0x09,0x09,0x09,0x0d,0x02,
+ 0x01,0x02,0x27,0x06,0x02,0x24,0x02,0x1d,0x04,0x04,0x09,0x04,0x0b,0x09,0x04,0x09,
+ 0x0e,0x09,0x0d,0x4b,0x04,0x01,0x29,0x09,0x26,0x1d,0x08,0x0b,0x1b,0x03,0x07,0x11,
+ 0x09,0x5e,0xe6,0xe5,0x2a,0x02,0x06,0x0a,0xe6,0x0f,0xe6,0x04,0x01,0x02,0x07,0xe6,
+ 0x0a,0x04,0x02,0x0e,0x01,0x02,0x06,0x01,0x02,0x01,0x05,0xe6,0x05,0x06,0xe5,0x0b,
+ 0x01,0x07,0xe6,0x06,0x06,0x02,0xe6,0x06,0xe6,0x3a,0x01,0xe5,0xe6,0x2a,0x03,0x05,
+ 0x02,0x0a,0x0c,0x01,0x03,0xe5,0x04,0x01,0xe6,0xe5,0x06,0x09,0x09,0x08,0xe5,0x04,
+ 0x03,0x07,0x01,0x01,0x01,0x07,0x05,0x01,0xe5,0x04,0x02,0xe6,0x08,0x09,0x0f,0x01,
+ 0x01,0x09,0x3f,0xe7,0x2c,0x14,0x13,0x05,0xe5,0xe5,0x02,0x06,0x12,0x13,0x03,0x05,
+ 0x0d,0x04,0x02,0x17,0x07,0x01,0x05,0x07,0x01,0x0b,0x01,0x3f,0xe5,0x14,0xe5,0x07,
+ 0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,
+ 0x05,0xe5,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x07,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe6,0xe6,0x03,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x36,0x0a,
+ 0x1a,0x01,0x0a,0xe5,0x07,0xe5,0x06,0x09,0x07,0x01,0x0b,0x0a,0x08,0x07,0x0c,0x09,
+ 0x12,0x0a,0x3f,0xe8,0x34,0x01,0x25,0x01,0x0d,0x02,0x1e,0x0d,0x0a,0x06,0x01,0x09,
+ 0x0a,0x09,0x5d,0xe6,0xe5,0x36,0x0a,0x1c,0x0e,0xe6,0x0b,0x09,0x09,0x08,0x16,0x3c,
+ 0x3f,0xe6,0xe5,0x0b,0x23,0x06,0x0c,0x13,0x09,0x09,0xe5,0x07,0x09,0x09,0x09,0x0b,
+ 0x09,0x06,0x0c,0x09,0x09,0x13,0x09,0x3f,0xe6,0x2a,0x02,0x06,0x02,0xe5,0x18,0xe5,
+ 0xe5,0x02,0x02,0x02,0x10,0x01,0xe5,0x08,0x06,0x15,0x03,0x09,0x08,0x2e,0xe5,0xe5,
+ 0x49,0x01,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x04,0x02,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x02,0x04,0x01,0xe5,0x05,0x01,0x04,0x02,
+ 0x01,0x01,0x05,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x01,0x02,0x01,0x02,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0xe5,0x01,0x2b,0x01,
+ 0x05,0x01,0x0b,0xe5,0x14,0x04,0xe5,0x01,0x01,0x05,0xe5,0x0f,0x0c,0x02,0x13,0x07,
+ 0xe5,0x05,0x15,0x1f,0x07,0xe5,0x3f,0xe5,0xe6,0x14,0x13,0x02,0x06,0x08,0x02,0xe5,
+ 0x04,0x0e,0x0d,0x03,0x07,0x15,0x02,0x04,0x17,0x23,0x0f,0x0b,0x02,0x01,0x01,0x3f,
+ 0xe5,0x01,0xe5,0x09,0x29,0x0f,0x08,0x13,0x07,0x16,0x08,0x01,0x08,0x04,0x06,0x05,
+ 0x1e,0x23,0x0a,0x04,0x03,0x26,0x09,0xe6,0xe5,0x2a,0x01,0x03,0x03,0x01,0xe5,0x03,
+ 0x04,0x09,0x06,0x01,0x0a,0x09,0xe5,0x18,0x02,0x09,0x0a,0xe5,0x36,0xe7,0x08,0x24,
+ 0x29,0x2a,0x02,0x09,0x1e,0xe5,0x01,0x0b,0x0f,0x0c,0x03,0x05,0x07,0x03,0x25,0x18,
+ 0x19,0x3b,0x02,0xe5,0x0b,0x1e,0x06,0x02,0x05,0x04,0xe5,0x04,0x04,0x06,0x01,0x06,
+ 0x02,0x02,0x1b,0x0c,0x0d,0x01,0x01,0xe5,0x2b,0x15,0x01,0x08,0xe5,0x08,0x02,0x2b,
+ 0x07,0x01,0xe6,0x33,0xe5,0xe6,0x05,0x09,0x09,0xe6,0x06,0xe6,0x13,0xe5,0x0e,0x01,
+ 0x0c,0x04,0x01,0xe5,0x07,0x01,0x11,0x20,0x02,0x04,0x12,0x01,0x36,0xe6,0xe5,0x27,
+ 0xe5,0x0e,0x07,0x07,0x19,0x08,0x2c,0x03,0x1d,0x3c,0x35,0x02,0xe5,0x08,0x2a,0x01,
+ 0x02,0x05,0x08,0xe7,0x0c,0x08,0x05,0x12,0xe5,0x0b,0x08,0x06,0x0c,0x04,0x1a,0x18,
+ 0x4f,0xe5,0xe5,0x37,0x02,0x03,0x0a,0x17,0x07,0x05,0x0c,0x1b,0xe5,0x06,0x03,0x0c,
+ 0x7a,0xe8,0x31,0x09,0x02,0x01,0x04,0x05,0x0c,0x05,0x09,0x04,0x02,0x01,0x08,0x07,
+ 0x02,0x0f,0x2d,0x09,0x0f,0x03,0x09,0x09,0x38,0xe7,0x28,0x03,0x02,0x03,0x01,0x06,
+ 0xe5,0xe6,0x09,0xe5,0x08,0x05,0xe5,0x03,0x03,0x03,0x02,0x06,0x04,0x01,0x09,0x02,
+ 0xe5,0x1c,0x1a,0xe6,0x06,0xe6,0x10,0xe5,0xe5,0x0e,0x01,0x35,0xe5,0xe5,0xe5,0x2e,
+ 0x01,0x2d,0x0b,0x0c,0x01,0x0a,0x01,0x0b,0x31,0x09,0x12,0x02,0x01,0x03,0x03,0x05,
+ 0x12,0x25,0xe8,0xe5,0x36,0xe5,0x03,0x02,0xe6,0xe6,0x04,0x05,0x0c,0xe6,0x07,0x01,
+ 0xe5,0x05,0xe5,0xe5,0xe6,0x02,0x09,0x09,0x0d,0xe5,0x01,0x03,0x02,0x01,0x04,0x0a,
+ 0x0b,0xe5,0x04,0x02,0xe5,0x04,0x05,0x09,0x40,0xe6,0x02,0xe5,0xe5,0xe5,0x26,0x0b,
+ 0x06,0xe5,0xe5,0x02,0xe5,0xe5,0x01,0x01,0x04,0xe5,0x0b,0x09,0x01,0xe5,0x05,0x01,
+ 0xe5,0x01,0x03,0x05,0x02,0x03,0xe5,0x0c,0x06,0x01,0xe8,0x01,0xe5,0x05,0x0f,0x05,
+ 0xe5,0x01,0x06,0x01,0x0a,0x04,0x04,0xe5,0x0c,0x2e,0x01,0x05,0xe5,0x03,0x23,0xe5,
+ 0x0c,0x04,0xe5,0xe5,0xe5,0x06,0x09,0x01,0x0d,0xe5,0x01,0x01,0x11,0x05,0xe5,0x01,
+ 0x01,0x0b,0x0e,0xe5,0xe5,0x12,0x0b,0x09,0x01,0x09,0x0c,0x01,0xe5,0xe5,0x06,0x01,
+ 0x31,0x04,0xe6,0xe5,0x01,0x25,0x09,0x02,0x05,0xe5,0x01,0x01,0x04,0x02,0x09,0x01,
+ 0x0e,0x02,0x01,0x11,0x09,0x01,0x13,0x06,0x04,0x0e,0xe5,0xe5,0x04,0xe5,0x01,0x01,
+ 0x04,0xe5,0xe5,0xe5,0x0c,0xe5,0x0b,0x01,0x04,0xe5,0xe5,0xe5,0x32,0x02,0xe5,0x01,
+ 0xe5,0x0a,0x1c,0x03,0x05,0x01,0x04,0x01,0x01,0xe5,0xe6,0x02,0xe7,0xe5,0x01,0x04,
+ 0x01,0xe5,0x0d,0x06,0x09,0x04,0x04,0x0a,0x02,0x05,0x06,0x06,0xe6,0x01,0x02,0x03,
+ 0x05,0x06,0x0e,0x01,0x05,0x01,0x01,0x05,0x0e,0x01,0xe5,0x05,0x01,0x36,0x01,0xe6,
+ 0x01,0x08,0x23,0x04,0xe5,0x02,0x04,0xe5,0xe6,0x04,0xe5,0xe5,0xe5,0x04,0x01,0xe5,
+ 0x04,0xe5,0x02,0x01,0x02,0x04,0x0f,0x03,0x09,0x04,0x0c,0x01,0x06,0x02,0x01,0x02,
+ 0xe6,0x0b,0x07,0x05,0x02,0xe5,0x03,0xe5,0x01,0x0e,0x05,0x01,0xe5,0x04,0xe5,0xe5,
+ 0xe5,0x2d,0x03,0x05,0xe5,0x30,0xe5,0xe5,0xe5,0x02,0xe6,0xe5,0xe5,0x04,0x01,0x01,
+ 0x04,0x02,0x01,0x05,0x03,0x04,0x02,0x01,0x03,0xe5,0x08,0x02,0x03,0x05,0x01,0x05,
+ 0x05,0xe7,0x03,0x07,0x07,0xe5,0x08,0x02,0x01,0x04,0x04,0x04,0x04,0x0d,0xe5,0x0b,
+ 0x01,0x05,0x01,0x01,0x30,0x06,0xe7,0x31,0xe5,0xe5,0x02,0xe5,0x03,0x01,0xe5,0x05,
+ 0x01,0x01,0xe5,0xe6,0xe5,0xe6,0x05,0x01,0x04,0xe5,0xe5,0xe5,0xe6,0xe5,0xe5,0x03,
+ 0xe5,0xe8,0x03,0x04,0x01,0x0c,0x06,0x01,0x02,0xe6,0x03,0x01,0xe5,0x07,0xe5,0xe8,
+ 0xe5,0x01,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x02,0x08,0xe5,0xe5,0xe5,0x09,0x01,
+ 0xe5,0x05,0x01,0x37,0x01,0xe6,0x03,0x2b,0x01,0xe5,0x02,0x02,0x06,0x02,0xe5,0x04,
+ 0x02,0x01,0xe5,0x02,0x0c,0x01,0x04,0x09,0x02,0x02,0x03,0x13,0x15,0x09,0x27,0x13,
+ 0x43,0x32,0xe5,0x03,0xe5,0x03,0x0d,0xe5,0x0b,0x09,0x01,0x03,0xe6,0xe5,0x04,0xe6,
+ 0x06,0xe5,0x01,0x0f,0xe5,0x0a,0xe5,0xe6,0x03,0xe5,0x07,0xe6,0x07,0xe5,0xe5,0x05,
+ 0xe5,0x08,0x01,0x05,0xe6,0x14,0xe5,0x39,0xe9,0x0d,0x09,0x09,0x09,0x02,0x03,0x02,
+ 0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,0x02,0x02,0xe5,0x07,0xe5,0x01,0x05,0x04,0xe6,
+ 0x01,0xe5,0x01,0x02,0x02,0xe5,0x04,0x02,0xe8,0x04,0x09,0xe6,0x08,0x09,0xe5,0x07,
+ 0xe5,0x07,0x05,0x03,0x09,0x03,0x05,0xe5,0x02,0x01,0x02,0x04,0x01,0x02,0xe5,0x02,
+ 0x01,0x02,0x02,0x06,0x09,0x09,0x09,0x06,0x06,0x01,0x01,0xe5,0x01,0x30,0x0a,0x06,
+ 0x02,0x1d,0x04,0x01,0x02,0x06,0x02,0x1d,0x06,0x04,0x0e,0x04,0x04,0x09,0x09,0x09,
+ 0x04,0x09,0x09,0x30,0x05,0x02,0xe5,0xe6,0x38,0x03,0x08,0x06,0x15,0x07,0x03,0x05,
+ 0x02,0x1c,0x0c,0x06,0x09,0x03,0x23,0x03,0x07,0x09,0x3f,0xe5,0x27,0x02,0x01,0x07,
+ 0x01,0xe5,0xe5,0x03,0x01,0xe5,0x02,0x02,0x01,0xe7,0x03,0x01,0xe5,0x05,0x0b,0xe7,
+ 0x05,0xe7,0xe5,0xe5,0x01,0xe7,0x03,0x01,0x02,0x07,0x01,0x08,0x02,0x01,0x04,0xe7,
+ 0x06,0xe6,0xe5,0x01,0x01,0x02,0x06,0x02,0x06,0x02,0x07,0x01,0x0e,0x01,0xe5,0x3c,
+ 0x01,0xe8,0x29,0xe5,0xe6,0x05,0x01,0xe6,0x04,0x01,0x07,0x01,0xe6,0x03,0xe5,0xe5,
+ 0x03,0x04,0xe5,0x02,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x02,0xe6,0x01,0x06,0x07,
+ 0x03,0x01,0x03,0x02,0xe5,0x08,0x05,0x01,0x01,0x01,0xe5,0x03,0x01,0x01,0x05,0x01,
+ 0x09,0x05,0x02,0x06,0x01,0x09,0xe5,0x34,0x01,0xe6,0x34,0x01,0x07,0x01,0x06,0x02,
+ 0x07,0x01,0x09,0x0a,0x02,0xe5,0xe5,0x0c,0x02,0x03,0x01,0x13,0x01,0x09,0x01,0x09,
+ 0x01,0x0f,0x03,0x05,0x03,0x09,0x02,0x0a,0x01,0x44,0x15,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0x01,0x04,0xe6,0xe5,0x04,0xe6,0x06,0xe5,
+ 0x01,0x03,0xe5,0xe6,0x01,0x03,0xe6,0x01,0x03,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x06,
+ 0xe6,0x01,0x01,0x05,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0xe5,0x07,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x2a,0x01,0xe6,0x06,0xe6,0x04,0x01,0x07,0x01,0xe6,
+ 0x04,0x01,0x09,0xe6,0x07,0xe5,0x07,0xe5,0x0e,0x01,0x0a,0xe5,0x08,0x07,0x01,0x13,
+ 0x09,0x07,0x01,0x0a,0xe5,0x0e,0x01,0x44,0x2b,0x01,0x09,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x09,0x07,0x06,0x01,0x02,0x06,0xe5,0x04,0x02,0xe5,0xe5,0x05,0x08,0xe5,0x01,
+ 0x09,0x01,0x11,0x09,0x09,0x01,0x1b,0x01,0x39,0x05,0xe6,0xe6,0x0b,0x1e,0x01,0x09,
+ 0x09,0x1b,0x09,0x05,0x01,0xe6,0x05,0x01,0xe5,0x05,0xe7,0xe5,0x02,0xe7,0x06,0x01,
+ 0x01,0x0a,0x01,0x13,0x09,0x27,0x39,0x07,0xe5,0xe5,0x2a,0x01,0xe5,0x05,0x01,0x02,
+ 0x04,0x01,0x0c,0x0e,0x02,0x0b,0x01,0x07,0x09,0xe5,0x02,0x01,0x02,0xe6,0x06,0xe5,
+ 0x09,0x04,0x01,0x02,0x09,0x04,0x04,0x04,0x04,0x09,0x09,0x0e,0x01,0x3e,0x01,0x01,
+ 0x01,0xe5,0x29,0x02,0x06,0x02,0x06,0xe5,0xe5,0x05,0x09,0x09,0x1d,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x09,0x07,0x09,0x16,0x06,0xe5,0xe5,0x08,0x10,0x03,0x05,0xe5,0xe5,0x3e,
+ 0x03,0x11,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x01,
+ 0x03,0x01,0x04,0x02,0xe6,0x03,0x02,0x01,0x03,0x03,0xe7,0x05,0x01,0xe5,0x05,0x01,
+ 0x04,0x02,0x01,0x04,0x01,0xe9,0x04,0x01,0x02,0x01,0xe5,0x02,0x01,0x01,0x01,0x03,
+ 0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x02,0x02,
+ 0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x0a,
+ 0xe8,0x2a,0x08,0xe5,0x01,0x14,0x0a,0x02,0x04,0x09,0x08,0x04,0x05,0x01,0x10,0x0d,
+ 0x12,0x06,0x04,0x02,0x0b,0x03,0x07,0xe5,0x48,0x09,0x01,0xe7,0x03,0x23,0x0b,0x02,
+ 0x0d,0x0a,0xe5,0x06,0xe5,0x01,0x07,0xe5,0x12,0x08,0x03,0x08,0x08,0x13,0x01,0x05,
+ 0x12,0x0f,0x15,0x02,0x3a,0xe5,0xe7,0x38,0x18,0x05,0x01,0x06,0x10,0x03,0x22,0x0a,
+ 0x13,0x09,0x14,0x06,0x11,0x08,0x35,0x02,0x05,0x25,0x04,0x01,0x02,0x01,0xe5,0x07,
+ 0x07,0x09,0x01,0x05,0x01,0x01,0xe5,0x02,0x02,0xe5,0xe5,0x05,0x01,0xe5,0x05,0xe7,
+ 0x07,0x0a,0x0a,0x07,0x01,0x04,0x0e,0xe5,0x05,0xe6,0x08,0x11,0x04,0x04,0x01,0x04,
+ 0x02,0x01,0x06,0x2e,0xe6,0xe6,0x28,0xe5,0x01,0x03,0x05,0x08,0x07,0x02,0x04,0x02,
+ 0x02,0x08,0x11,0x02,0x07,0x06,0x02,0x04,0x08,0x04,0x0b,0x02,0x0e,0x01,0x05,0x04,
+ 0x03,0x04,0x11,0x03,0x01,0x07,0x03,0x05,0x03,0x32,0xe6,0xe5,0x23,0x08,0x03,0x03,
+ 0x02,0x0f,0x02,0x0a,0x06,0x18,0x0b,0x11,0x02,0x01,0x01,0x03,0x0a,0x15,0x07,0x22,
+ 0x01,0x07,0x01,0x1a,0x1a,0x01,0xe5,0xe5,0x2a,0xe5,0x07,0x18,0xe5,0x02,0x09,0x01,
+ 0x16,0x0d,0x11,0x01,0xe5,0x08,0x10,0x04,0x07,0x06,0x01,0x07,0x04,0x09,0x01,0x06,
+ 0x45,0xe6,0x27,0x04,0x09,0x14,0x06,0x05,0x28,0x12,0x03,0x09,0x17,0x0b,0x09,0x07,
+ 0x02,0x08,0x01,0x06,0x09,0x37,0x01,0x2c,0x0f,0x12,0x03,0xe5,0x06,0x11,0x01,0x03,
+ 0x05,0x09,0xe6,0xe5,0x04,0xe5,0xe5,0x03,0x02,0x01,0x01,0x0d,0x17,0xe6,0x10,0xe5,
+ 0x07,0xe5,0x04,0x0b,0x04,0x01,0x32,0x02,0xe5,0x2d,0x0a,0x04,0x16,0x0b,0x09,0x1c,
+ 0x01,0x0a,0x03,0x09,0x05,0x17,0x03,0x06,0x0d,0x09,0x49,0x03,0x2a,0x14,0x01,0x07,
+ 0x01,0xe5,0xe5,0x04,0x01,0x0c,0x05,0x06,0x03,0x03,0x06,0x02,0x03,0x04,0x07,0x06,
+ 0xe5,0xe6,0xe5,0x17,0x01,0x09,0x06,0x02,0x08,0x06,0x02,0xe5,0x06,0x01,0xe5,0x3d,
+ 0xe6,0x01,0xe5,0x35,0x0b,0x07,0x03,0x0f,0x08,0xe5,0x12,0x02,0x11,0x07,0x02,0x03,
+ 0x02,0x20,0x04,0x0e,0x09,0x09,0x05,0x01,0x01,0x3a,0x06,0x2b,0x04,0x01,0x11,0x13,
+ 0x08,0x0c,0x07,0x0b,0x12,0x04,0x11,0x0f,0xe5,0x04,0x02,0x0b,0x01,0x05,0x01,0x08,
+ 0x04,0x3d,0x01,0xe7,0x2c,0x1d,0xe7,0x01,0x03,0x05,0x03,0x0f,0x02,0xe5,0x04,0x09,
+ 0x03,0x09,0x02,0x01,0x06,0x02,0x01,0x25,0xe5,0xe5,0x02,0x01,0xe5,0x01,0x03,0xe5,
+ 0x07,0xe5,0x07,0x02,0xe5,0x04,0x32,0xea,0x01,0x01,0x27,0x01,0x08,0x07,0xe5,0x0a,
+ 0x03,0xe5,0xe6,0x04,0x01,0xe6,0x11,0x03,0x05,0x09,0x02,0x09,0x02,0xe5,0x06,0x03,
+ 0xe5,0x1e,0x05,0xe5,0x01,0xe6,0x03,0x01,0x03,0x01,0x07,0x0a,0x02,0xe5,0xe5,0x02,
+ 0x2f,0x01,0x02,0xe6,0xe5,0x03,0x28,0x0e,0xe5,0xe5,0xe5,0x0d,0x01,0xe5,0xe5,0xe6,
+ 0x03,0x03,0x0f,0x09,0x04,0x04,0x30,0x01,0x0a,0x09,0x03,0x05,0x0e,0xe6,0x07,0xe5,
+ 0x35,0x05,0xe7,0x01,0x34,0x04,0x02,0x01,0x11,0x01,0x03,0xe5,0x01,0x13,0x09,0x09,
+ 0x3d,0x01,0x04,0xe5,0xe5,0x0f,0xe5,0xe5,0x05,0x08,0xe5,0x01,0x35,0x02,0xe8,0x31,
+ 0x01,0x08,0x03,0x09,0x07,0x01,0x02,0x03,0xe5,0xe5,0x10,0x09,0x09,0x04,0x09,0x0b,
+ 0x1a,0x06,0xe5,0x03,0xe5,0x01,0xe5,0xe5,0x01,0x09,0xe5,0x01,0x05,0x02,0xe5,0x01,
+ 0x0c,0x35,0x01,0x02,0x31,0x04,0x01,0x02,0xe5,0x02,0x04,0xe5,0x04,0x02,0xe5,0xe5,
+ 0xe5,0x01,0xe7,0xe5,0xe5,0x01,0x01,0x0a,0x03,0x05,0x03,0x05,0x03,0x2f,0x03,0x02,
+ 0xe7,0xe5,0x01,0x01,0x01,0xe5,0xe5,0x01,0x08,0x02,0x01,0x04,0x02,0xe6,0x01,0x07,
+ 0x03,0x01,0x02,0x2c,0x02,0x03,0xe5,0x2e,0x02,0x08,0x02,0x01,0x05,0x03,0x07,0x01,
+ 0x01,0xe5,0xe5,0xe6,0xe5,0x02,0xe5,0x07,0xe5,0x01,0x09,0x09,0x03,0xe5,0x09,0xe5,
+ 0x0a,0x01,0x0f,0x01,0x01,0xe5,0x0f,0x02,0x19,0xe5,0x0b,0x01,0x02,0x32,0xe5,0x01,
+ 0xe5,0x2f,0x0b,0xe5,0xe5,0xe5,0x06,0x04,0x04,0x01,0x02,0xe6,0x01,0x01,0x04,0x01,
+ 0x0a,0x09,0x09,0x04,0x08,0xe5,0x09,0xe7,0x10,0x01,0x02,0x09,0x04,0x02,0x01,0x04,
+ 0x08,0xe5,0x07,0xe5,0xe5,0xe5,0x04,0x04,0x01,0x01,0xe7,0x31,0xe5,0xe5,0x30,0x09,
+ 0x01,0xe5,0x05,0x02,0x06,0x06,0x0c,0x02,0x21,0x02,0x02,0x03,0x0b,0x16,0x01,0xe5,
+ 0x05,0x02,0x17,0x09,0x02,0x10,0x37,0xe6,0x2e,0x02,0x01,0x11,0xe5,0x04,0x04,0x03,
+ 0xe5,0x01,0x06,0x02,0x06,0x1c,0xe5,0x01,0xe5,0x03,0xe6,0x08,0xe6,0x11,0x02,0x13,
+ 0xe5,0x05,0x01,0x05,0xe5,0x01,0x05,0xe6,0xe5,0xe5,0x03,0x02,0xe5,0x03,0xe5,0x01,
+ 0xe5,0x30,0x01,0xe6,0x0d,0x09,0x09,0x09,0x03,0x05,0x09,0x02,0x03,0x02,0x04,0x01,
+ 0x02,0xe6,0x02,0x03,0x03,0x05,0x09,0x09,0x09,0xe6,0x06,0xe5,0x09,0xe5,0x07,0x06,
+ 0x02,0x05,0x03,0x02,0x03,0x02,0x04,0x01,0x02,0x03,0x05,0xe5,0x01,0xe5,0xe5,0x01,
+ 0xe5,0x01,0x05,0x04,0x01,0x02,0xe5,0x07,0x09,0x09,0x09,0x0d,0x02,0xe6,0x01,0x3b,
+ 0x06,0x02,0x09,0x09,0x36,0x0b,0x0d,0x0a,0x06,0x02,0x09,0x04,0x0e,0x04,0x0e,0x36,
+ 0x03,0xe5,0xe5,0x3c,0x09,0x09,0x08,0x06,0x09,0x27,0x0b,0x13,0x01,0x0a,0x08,0x11,
+ 0x01,0x07,0x0b,0x07,0x34,0xe5,0x01,0x28,0x02,0x01,0x02,0x01,0x02,0x13,0x01,0x02,
+ 0x01,0x02,0x01,0xe7,0x02,0xe5,0xe5,0x01,0x06,0x02,0x10,0x06,0x03,0xe6,0xe5,0x04,
+ 0xe6,0xe5,0x05,0xe7,0x0d,0x01,0x02,0x0e,0x01,0x04,0x04,0x02,0x07,0xe6,0x03,0x02,
+ 0x01,0x06,0x02,0x01,0x04,0xe7,0x30,0x02,0xe7,0x2a,0x01,0x01,0x01,0x03,0x02,0x05,
+ 0x03,0x06,0x01,0x01,0x01,0x03,0x01,0xe6,0x04,0x01,0xe6,0x01,0x04,0xe6,0x10,0xe5,
+ 0x08,0xe5,0x08,0x09,0xe6,0x0e,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,
+ 0x01,0x08,0xe5,0x01,0x05,0xe5,0x06,0x01,0x01,0x02,0xe5,0xe7,0x34,0x01,0xe6,0x26,
+ 0x18,0x07,0x01,0x0a,0x06,0x01,0x03,0x05,0x13,0x07,0x01,0x01,0x09,0x04,0x04,0x11,
+ 0x01,0x03,0x03,0x09,0x01,0x10,0x06,0x02,0x16,0x39,0xe5,0x14,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x01,
+ 0x04,0xe6,0x06,0xe6,0x01,0x04,0xe7,0xe5,0x02,0xe7,0x07,0xe5,0x03,0xe5,0x03,0xe5,
+ 0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe6,0xe5,0x03,0xe6,0x01,0x05,0xe5,0x02,0x04,0xe5,
+ 0x07,0xe5,0x07,0xe6,0xe6,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,
+ 0x02,0xe5,0x37,0xe5,0x10,0x07,0x01,0xe6,0x04,0x01,0xe6,0x06,0xe5,0x02,0x09,0x04,
+ 0x04,0x02,0x01,0xe5,0x01,0x06,0x0a,0xe6,0x0e,0x02,0x08,0x09,0xe5,0x02,0x01,0x02,
+ 0x07,0x02,0x09,0xe5,0x06,0x07,0x01,0xe6,0x33,0xe5,0xe6,0x48,0x01,0x07,0x01,0x07,
+ 0x01,0x09,0x06,0x09,0x02,0x06,0xe5,0xe5,0x03,0x01,0x09,0x04,0x13,0x09,0x07,0x01,
+ 0xe5,0x05,0x01,0x07,0x15,0x07,0x01,0x36,0x01,0x01,0x41,0x09,0x09,0x09,0x09,0xe5,
+ 0x03,0x0d,0x05,0x01,0x01,0xe5,0x03,0x04,0x07,0x02,0x14,0x06,0x01,0x09,0x14,0x1c,
+ 0x37,0xe5,0xe5,0x2f,0x07,0x12,0x02,0x04,0x04,0x04,0x01,0x02,0x06,0x02,0xe8,0x08,
+ 0x02,0x03,0xe8,0xe5,0x01,0x01,0xe6,0x04,0x01,0x01,0x04,0x02,0x07,0x0b,0x0e,0x02,
+ 0x01,0x01,0x04,0x02,0x09,0x09,0x09,0x04,0x01,0x02,0x33,0x01,0xe6,0x2c,0xe5,0x06,
+ 0x01,0x15,0x01,0x02,0xe5,0xe6,0x04,0x04,0x08,0x05,0xe5,0xe5,0x05,0x02,0xe5,0x07,
+ 0xe5,0x0c,0x1b,0x05,0xe5,0xe5,0xe5,0x06,0x09,0xe5,0x04,0x02,0x04,0x04,0x06,0x09,
+ 0xe5,0xe6,0x34,0xe7,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0x07,0x01,0x01,0x01,0x03,0x01,0xe5,0xe6,0x02,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x04,0x02,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x02,0x04,0x01,0x07,0x01,0x07,
+ 0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x07,0xe6,0x01,0x01,
+ 0x02,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x05,0x57,
+ 0x11,0xe5,0x06,0xe6,0x05,0x09,0x03,0x07,0x1f,0xe6,0x0e,0x06,0x02,0x09,0x01,0x02,
+ 0x03,0xe5,0xe6,0xe5,0x05,0x01,0x07,0x06,0x30,0x01,0xe6,0x14,0x26,0x07,0xe5,0x0a,
+ 0x04,0x0e,0x01,0xe5,0x03,0x02,0x10,0x05,0x03,0x04,0xe5,0x02,0x03,0x08,0x07,0x03,
+ 0x04,0xe5,0x0b,0x03,0x12,0x06,0x02,0x05,0x03,0xe5,0x02,0x04,0x02,0x32,0xe7,0xe5,
+ 0x63,0x0e,0x02,0x22,0x0f,0x04,0x02,0x06,0x09,0x09,0x06,0x0d,0x05,0x02,0x04,0x02,
+ 0x3b,0x01,0xe6,0x24,0x05,0xe6,0x06,0xe6,0x10,0xe6,0x08,0xe5,0xe5,0x03,0x01,0x23,
+ 0x03,0x20,0x03,0x04,0x07,0xe6,0xe5,0x04,0x0d,0x0b,0x01,0x03,0x04,0x0c,0xe5,0x0b,
+ 0x2a,0xe9,0x27,0x02,0x08,0x0d,0x01,0x01,0x02,0x0e,0x06,0x04,0x14,0x1e,0x08,0x14,
+ 0x02,0x03,0x06,0x15,0x01,0x02,0xe5,0x0e,0x0b,0x31,0x01,0xe6,0x0f,0x11,0x12,0xe6,
+ 0x19,0x09,0xe6,0xe5,0x06,0x04,0x04,0x02,0x06,0x07,0x01,0x03,0x05,0x03,0x03,0xe5,
+ 0x01,0x09,0x07,0x06,0x04,0x04,0x03,0xe5,0x07,0xe5,0x08,0x09,0xe5,0x07,0x09,0x09,
+ 0x02,0x29,0xe5,0xe7,0x1f,0x01,0x0a,0x29,0x04,0x01,0xe5,0x01,0x03,0x06,0x02,0x08,
+ 0xe5,0x08,0x09,0x02,0x03,0x02,0x06,0x03,0xe6,0xe6,0x0a,0x06,0x06,0x09,0x02,0x01,
+ 0x01,0x02,0x01,0x07,0xe6,0x06,0xe7,0x02,0x02,0xe6,0x06,0xe6,0x2b,0x01,0x01,0x24,
+ 0x2a,0x07,0x11,0xe5,0x07,0xe6,0x01,0x04,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0x02,0x02,
+ 0xe5,0x02,0x01,0x03,0xe5,0x0f,0x05,0xe5,0x06,0x05,0x01,0x0c,0x0b,0x12,0x36,0xe7,
+ 0x11,0x25,0x05,0xe5,0x0e,0x11,0xe5,0x01,0x1b,0x02,0xe6,0x10,0x02,0x03,0x02,0x0a,
+ 0x09,0x04,0x0f,0xe6,0x06,0xe6,0x54,0x02,0x3f,0xe5,0x16,0x02,0x2c,0x10,0x04,0x31,
+ 0x08,0x18,0x3e,0xe5,0x20,0x01,0x02,0x03,0x06,0x09,0x06,0x12,0x03,0xe5,0x01,0x01,
+ 0xe5,0x01,0xe5,0x01,0x01,0x05,0xe6,0xe5,0x06,0x01,0x07,0x01,0x03,0x03,0x01,0x02,
+ 0x06,0x01,0xe5,0x07,0x0c,0x03,0x02,0x10,0xe5,0xe5,0x08,0x09,0x09,0x06,0xe5,0xe5,
+ 0x04,0x01,0x01,0x2d,0xe5,0xe5,0x22,0x07,0x01,0xe5,0xe5,0xe5,0x01,0x01,0x06,0x06,
+ 0x0b,0x15,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x03,0x05,0x01,0x04,
+ 0x01,0x02,0x1e,0x0a,0x06,0xe5,0x02,0x03,0xe6,0x06,0xe6,0x08,0x03,0x05,0x2b,0xe5,
+ 0x01,0xe5,0x21,0x07,0x22,0x04,0xe5,0x02,0x09,0x29,0x19,0xe5,0x01,0x0f,0x1c,0x02,
+ 0x01,0x02,0x06,0x09,0x07,0x03,0x05,0x2c,0x02,0xe7,0x2c,0x05,0x03,0x02,0xe5,0x04,
+ 0x0a,0x08,0x05,0x03,0x09,0x05,0x0d,0x09,0x11,0x03,0x01,0xe5,0x12,0xe5,0xe5,0x08,
+ 0x06,0x01,0x04,0x09,0x01,0xe5,0x05,0x0c,0x01,0x04,0x32,0xe5,0x01,0x01,0x02,0x01,
+ 0x2a,0x05,0xe5,0x01,0x02,0xe5,0x03,0x06,0x0c,0x06,0xe7,0x09,0x05,0x0d,0x08,0x12,
+ 0xe6,0xe5,0xe6,0x01,0xe5,0x0e,0x01,0xe6,0x07,0xe5,0x04,0xe5,0x03,0x09,0x02,0xe5,
+ 0x0b,0xe5,0x04,0xe5,0x0c,0x27,0x01,0x03,0x01,0xe5,0x03,0x19,0xe5,0x02,0x04,0xe5,
+ 0xe5,0x05,0x01,0x02,0x22,0x01,0xe5,0x12,0x1a,0xe5,0x11,0x01,0xe5,0x02,0x11,0x01,
+ 0x07,0x01,0x02,0xe6,0x01,0x01,0x15,0x02,0x01,0xe5,0xe5,0x03,0xe5,0x04,0x2f,0x04,
+ 0x02,0xe5,0x01,0x1b,0x02,0x05,0xe5,0x01,0x06,0xe5,0xe5,0x12,0x15,0x11,0x1a,0xe5,
+ 0x06,0xe5,0x0a,0x02,0x01,0x0e,0x02,0x01,0x07,0x01,0x04,0xe5,0xe5,0x1c,0x01,0x03,
+ 0xe5,0x01,0x0b,0x29,0x03,0x01,0xe5,0x1e,0x01,0x04,0xe5,0x01,0x05,0x06,0xe5,0xe5,
+ 0x02,0x05,0x09,0x09,0x06,0x09,0x02,0x10,0x02,0x06,0x02,0x10,0x01,0x02,0xe5,0xe7,
+ 0xe5,0x01,0x03,0x05,0x02,0x01,0x01,0x02,0x01,0x01,0xe5,0xe6,0x04,0xe5,0xe5,0x01,
+ 0x01,0x01,0x02,0x03,0x02,0xe5,0xe5,0x01,0xe5,0x01,0x02,0x10,0x06,0x02,0x1e,0x06,
+ 0xe8,0x01,0x1e,0x03,0x0a,0x04,0x02,0x03,0xe6,0x09,0x04,0x03,0x0c,0x01,0x05,0x04,
+ 0xe5,0x01,0x0a,0x04,0x01,0x01,0xe5,0x03,0x10,0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,
+ 0xe5,0xe6,0x09,0x01,0x01,0x04,0xe5,0xe6,0x01,0x01,0xe6,0xe5,0xe5,0x03,0xe5,0x05,
+ 0x01,0xe5,0x03,0x01,0x01,0xe5,0x02,0x01,0x02,0x08,0x05,0x02,0x01,0x22,0x02,0xe5,
+ 0xe7,0x1f,0x01,0x01,0xe5,0x03,0x0b,0x02,0x16,0x05,0x02,0x09,0x04,0x0e,0x04,0x09,
+ 0x07,0x01,0x02,0x01,0x01,0x04,0x01,0x05,0x01,0x01,0x09,0xe5,0xe5,0xe6,0xe5,0x03,
+ 0xe7,0xe5,0x06,0x01,0x05,0x03,0x02,0x04,0x01,0x02,0x06,0x07,0x01,0x30,0x04,0xe5,
+ 0xe5,0xe5,0x20,0x04,0x01,0x02,0x04,0x04,0x02,0xe6,0x07,0xe5,0x03,0x04,0x01,0x07,
+ 0x01,0xe6,0x01,0x02,0x01,0xe7,0x03,0x09,0x01,0xe5,0xe5,0x03,0x04,0x04,0x04,0x01,
+ 0x02,0x01,0x01,0x02,0x04,0x04,0x01,0x02,0xe6,0x06,0x01,0x02,0x01,0x01,0xe5,0xe5,
+ 0xe6,0xe6,0x05,0x01,0x01,0xe5,0x03,0x04,0x04,0x01,0x02,0x04,0x09,0x01,0x02,0x33,
+ 0xe8,0x28,0x0e,0x09,0x02,0x02,0x06,0x01,0xe5,0x19,0x0b,0x31,0x09,0x01,0xe5,0x02,
+ 0x09,0x09,0x0c,0x02,0x10,0x09,0x33,0x02,0x28,0x09,0x0f,0xe5,0x01,0x09,0xe5,0x07,
+ 0xe5,0x04,0xe5,0x0a,0x01,0x04,0x0c,0x10,0x0b,0x0e,0x07,0x05,0xe5,0x01,0xe5,0x0d,
+ 0xe5,0x08,0x02,0x06,0x02,0x09,0x01,0x04,0x02,0x01,0x2f,0x01,0x01,0xe5,0x0d,0x09,
+ 0x09,0x03,0x05,0x05,0xe5,0x01,0xe5,0x07,0xe5,0x01,0x05,0x09,0x09,0x09,0x03,0x05,
+ 0x09,0x05,0xe5,0x01,0x09,0x04,0x01,0x04,0x09,0x06,0x02,0x05,0x03,0xe5,0x04,0x02,
+ 0xe5,0x04,0x02,0xe5,0x07,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x09,0x09,0x09,
+ 0x06,0x06,0xe5,0xe5,0xe5,0x01,0x2e,0x02,0x09,0x31,0x12,0xe5,0x12,0x0b,0x08,0x05,
+ 0x0b,0x09,0x02,0x13,0x09,0x3a,0xe5,0x03,0x02,0x01,0xe6,0x31,0x0a,0x05,0x1d,0x0d,
+ 0x13,0x13,0x07,0x01,0x1b,0x0c,0x06,0x0d,0x07,0x3c,0x09,0xe6,0xe5,0xe5,0x1b,0x04,
+ 0x02,0x09,0x07,0x03,0x05,0xe6,0x0a,0x04,0x02,0x01,0x04,0x02,0x06,0x02,0x01,0x07,
+ 0x06,0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x01,0x02,0x04,0x01,0x09,0x02,0x01,0x02,
+ 0x01,0xe5,0xe5,0x03,0x01,0xe5,0x07,0xe7,0x03,0x01,0x02,0x04,0x01,0x02,0x06,0x04,
+ 0x04,0x02,0x03,0xe5,0xe5,0x29,0x03,0x01,0x1e,0x04,0x01,0x09,0x05,0x03,0x08,0xe5,
+ 0x07,0xe5,0x06,0x01,0x02,0x04,0x01,0x07,0x01,0x05,0x03,0x01,0x05,0x01,0x09,0x07,
+ 0x01,0x01,0x07,0xe6,0x03,0xe5,0xe7,0x04,0x03,0x04,0xe5,0xe7,0x04,0x01,0x06,0xe5,
+ 0xe7,0x04,0x01,0x01,0x01,0x02,0xe5,0xe7,0xe5,0x05,0x08,0x01,0x01,0x03,0x01,0xe5,
+ 0x2a,0xe8,0x26,0x03,0x05,0x09,0xe5,0x03,0x07,0x01,0x03,0xe5,0x03,0x09,0x04,0x22,
+ 0x09,0x06,0x02,0x01,0x04,0x02,0x01,0x03,0xe5,0x0b,0x01,0x07,0x01,0x04,0x04,0x09,
+ 0x03,0x03,0x01,0x07,0x01,0x11,0x01,0x2d,0x02,0x15,0xe5,0x07,0xe5,0x07,0xe6,0x06,
+ 0xe6,0x06,0xe6,0x01,0x04,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x04,0xe6,0x05,
+ 0xe6,0xe5,0x05,0xe5,0x06,0xe6,0x06,0x01,0x03,0x04,0xe5,0x04,0x05,0xe6,0xe5,0x04,
+ 0xe5,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0xe6,0x03,0xe6,0xe5,0x04,0xe6,0xe5,
+ 0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x05,0x02,0x23,0xe5,0x19,0x02,0x10,0x01,0xe6,0x07,0xe5,0x01,0x01,0x02,0x05,
+ 0x0d,0x05,0x03,0x05,0x0d,0x01,0xe5,0x05,0x01,0x09,0xe5,0x05,0x0b,0x09,0xe5,0x05,
+ 0x01,0x07,0x01,0x09,0x09,0x07,0x2e,0xe6,0xe5,0x22,0x1d,0x11,0x01,0x13,0x03,0x02,
+ 0xe5,0x07,0x02,0x03,0x02,0x09,0x07,0x01,0x04,0xe5,0x05,0x01,0x07,0x09,0x09,0x09,
+ 0x09,0x01,0x07,0x15,0x07,0x2f,0xe5,0xe5,0x23,0x1a,0x01,0xe5,0x11,0x18,0xe5,0x07,
+ 0x09,0xe5,0x02,0x03,0x01,0x0c,0xe5,0xe5,0x08,0x0a,0x12,0x09,0xe5,0x07,0x09,0x09,
+ 0x11,0x2e,0x01,0x01,0x26,0x09,0x09,0x04,0x01,0x02,0x09,0x06,0x02,0x09,0x09,0xe5,
+ 0x02,0x04,0x01,0x07,0xe5,0x07,0x01,0x07,0x01,0x06,0x02,0x04,0x01,0x02,0x09,0x09,
+ 0x04,0x09,0x04,0x04,0x04,0x04,0x04,0x13,0x04,0x2e,0x01,0xe6,0x20,0xe5,0xe6,0x07,
+ 0x06,0xe5,0xe5,0xe5,0x07,0x05,0xe5,0xe5,0x0f,0x0d,0xe5,0x03,0x01,0xe6,0x08,0xe5,
+ 0x23,0x0d,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x02,0x10,0x01,0xe5,0x0f,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x0c,0x1c,0xe5,0xe7,0xe5,0x0e,0x01,0x07,0x01,0x04,0x02,0xe6,0x06,
+ 0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x01,0x02,0x02,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x04,0x04,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x03,0x03,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x07,0x01,0x04,
+ 0x02,0xe6,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0b,0xe7,
+ 0x22,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x06,0x13,0x02,0x02,0xe5,0x11,
+ 0xe6,0x0d,0x0e,0xe5,0x01,0x02,0x01,0x05,0x04,0xe5,0x07,0xe5,0x0f,0xe5,0xe5,0x04,
+ 0x1f,0x05,0x03,0x2e,0xe5,0xe6,0x1f,0x02,0x01,0xe5,0x01,0xe5,0x04,0x03,0x02,0x06,
+ 0x11,0x28,0x09,0x0f,0x03,0x03,0x02,0x0e,0xe5,0x01,0x04,0x03,0x11,0x08,0x06,0xe5,
+ 0x4d,0x01,0x02,0x23,0x06,0x01,0x07,0x01,0x05,0x04,0x02,0x12,0x0c,0x02,0x01,0x06,
+ 0x05,0x03,0xe5,0xe5,0x05,0x04,0x04,0x05,0x04,0x02,0x14,0x07,0x0c,0x1d,0x03,0x01,
+ 0x07,0x3b,0xe8,0x2a,0xe7,0x0f,0x01,0xe6,0x06,0x03,0x01,0x01,0x01,0x07,0x01,0x28,
+ 0x06,0x01,0x04,0x0e,0x10,0x02,0xe7,0x07,0x07,0x01,0x09,0x07,0xe5,0x01,0x01,0xe5,
+ 0x03,0x04,0x0c,0xe6,0x2a,0xe5,0x01,0xe5,0x2b,0x13,0xe5,0x03,0x03,0x07,0x02,0x01,
+ 0x07,0x05,0x08,0xe5,0x08,0x08,0xe5,0x08,0x04,0x06,0x0e,0x0c,0x01,0x02,0x02,0x05,
+ 0x09,0x02,0x20,0x3c,0x01,0x01,0x1f,0x0d,0x13,0x08,0xe5,0x02,0x03,0x05,0x03,0x01,
+ 0x03,0x04,0xe5,0x0c,0x05,0x03,0x0a,0x02,0x01,0x03,0x03,0x02,0xe5,0x01,0x25,0x10,
+ 0x01,0x11,0x13,0x2d,0x04,0x35,0x01,0xe5,0x05,0xe7,0x05,0x02,0xe5,0x11,0x1a,0x13,
+ 0x05,0x03,0x01,0x19,0x02,0x03,0x13,0x06,0x01,0x07,0x01,0x05,0x0a,0x39,0xe6,0xe5,
+ 0x2d,0x0f,0x0a,0x05,0xe5,0x0e,0x01,0xe6,0xe5,0x0d,0x03,0x03,0xe5,0x0a,0x06,0xe7,
+ 0x03,0x03,0x0b,0x0a,0x01,0x1e,0x04,0x01,0x12,0x3e,0xe5,0xe6,0x12,0x0d,0xe5,0x10,
+ 0x08,0x0f,0x05,0x08,0x11,0x02,0xe5,0x0f,0x01,0xe5,0x0f,0x01,0x09,0x8b,0x02,0x21,
+ 0xe5,0x0e,0x09,0x06,0x02,0x0c,0x06,0x18,0x04,0x0e,0x04,0x09,0x02,0x55,0x3e,0xe5,
+ 0xe6,0x2a,0x01,0x13,0x02,0x06,0x04,0x02,0x01,0x0a,0x03,0xe5,0x02,0xe5,0x04,0x01,
+ 0x04,0x03,0x01,0x03,0x04,0xe5,0x05,0xe5,0xe5,0x12,0x01,0x13,0x03,0x09,0x09,0x05,
+ 0x03,0x02,0x02,0x2b,0x09,0x13,0xea,0x22,0x04,0xe5,0x01,0x11,0xe6,0x07,0x0a,0x05,
+ 0x0a,0x02,0x01,0x09,0x05,0x01,0x08,0xe6,0x03,0x01,0x01,0x0c,0x08,0x0a,0x07,0xe5,
+ 0x0b,0x0e,0x01,0x08,0x01,0x40,0x0c,0x25,0x06,0x02,0x15,0x0f,0x03,0x0d,0xe5,0x1c,
+ 0x0c,0x10,0x01,0x11,0x02,0x0c,0x0e,0x03,0x4c,0x06,0x01,0xe7,0x1b,0xe5,0x04,0x05,
+ 0x0f,0xe5,0x01,0x03,0x09,0x09,0x02,0xe5,0x04,0xe5,0x07,0x09,0x05,0x03,0x01,0xe5,
+ 0x01,0x03,0x05,0x03,0x01,0xe5,0x0a,0xe5,0xe5,0x02,0x13,0x09,0x02,0xe5,0x07,0xe5,
+ 0x03,0xe8,0x05,0x09,0x3c,0x02,0x01,0xe5,0x01,0x01,0x19,0xe5,0x03,0x06,0xe5,0x02,
+ 0x04,0x09,0xe5,0x0b,0x05,0xe5,0x01,0x01,0xe5,0x05,0xe5,0x07,0x08,0x06,0x03,0x02,
+ 0x01,0xe5,0x01,0x06,0x03,0x01,0xe5,0x08,0xe6,0x01,0x03,0xe5,0x11,0x09,0x02,0xe5,
+ 0x07,0xe5,0x06,0xe5,0x0f,0x39,0x02,0xe5,0xe6,0xe5,0x03,0x26,0x01,0x03,0xe5,0x01,
+ 0x04,0x01,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0x0c,0x04,0xe5,0xe5,0x05,0xe5,0x14,0x09,
+ 0x09,0x0e,0x06,0x35,0x02,0xe5,0xe5,0x02,0x3d,0xe5,0x03,0x04,0xe6,0xe5,0x01,0x25,
+ 0xe5,0xe5,0xe5,0x02,0xe5,0x01,0x06,0xe5,0xe5,0xe5,0x03,0x0c,0x0f,0xe5,0x08,0xe5,
+ 0x02,0x07,0x09,0x09,0x0c,0x02,0x05,0x38,0x02,0x41,0xe5,0x05,0x02,0x02,0xe5,0x25,
+ 0x04,0x01,0xe5,0x04,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x01,0xe5,0xe7,0xe5,0x08,0x06,
+ 0xe5,0xe5,0x01,0x01,0x01,0x05,0x03,0x05,0x01,0x01,0x0a,0x04,0x12,0xe5,0x05,0x01,
+ 0x02,0x09,0x1d,0x06,0x05,0x03,0x02,0x01,0x01,0x02,0x06,0x38,0x01,0x01,0xe5,0x01,
+ 0x28,0x01,0xe5,0x01,0x01,0xe6,0xe5,0xe5,0xe5,0x01,0xe5,0xe5,0xe5,0x04,0x06,0x01,
+ 0xe5,0x02,0x01,0x01,0xe6,0xe5,0xe5,0x01,0x01,0x04,0x01,0x01,0xe5,0x03,0x0f,0x03,
+ 0x11,0x02,0x05,0xe5,0xe5,0xe5,0x2c,0x08,0xe5,0x02,0x04,0xe5,0x05,0xe6,0x32,0x03,
+ 0x02,0xe8,0x26,0x02,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x09,0x02,0x04,0x01,
+ 0x01,0x07,0x01,0x01,0xe5,0x05,0x01,0xe5,0x0b,0x03,0xe5,0xe5,0xe5,0x0d,0xe5,0x03,
+ 0x01,0x01,0x01,0x09,0x02,0x01,0x05,0x15,0x04,0x05,0x01,0x01,0x01,0xe5,0x01,0x03,
+ 0x41,0xe5,0xe5,0x24,0xe5,0x01,0x01,0x01,0xe5,0x05,0x01,0x07,0x01,0x02,0x04,0x01,
+ 0x07,0x04,0x04,0x01,0x02,0x09,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x04,0x04,0x01,
+ 0x07,0x06,0x02,0x03,0x02,0x01,0x02,0x09,0x01,0x07,0x12,0xe5,0xe6,0xe5,0x08,0x04,
+ 0x04,0x04,0x40,0xe5,0x23,0x09,0x0c,0x09,0xe5,0x07,0xe5,0x11,0xe5,0x04,0x09,0x13,
+ 0x04,0x15,0x13,0x07,0x02,0x06,0x02,0x03,0x04,0x07,0x02,0x10,0x02,0x33,0x04,0x02,
+ 0x01,0x24,0xe5,0x0b,0x0b,0x05,0x08,0x14,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x08,0x08,
+ 0xe5,0x08,0x0b,0x0a,0x15,0x09,0xe5,0x03,0xe5,0x01,0x06,0x02,0xe5,0x07,0xe5,0x04,
+ 0x3e,0xe5,0x01,0xe5,0x0d,0x09,0x09,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0x09,0x06,
+ 0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0xe6,0xe6,0xe5,0x01,0xe6,0x06,0x09,0xe6,
+ 0x06,0x04,0x01,0x04,0xe5,0x07,0x09,0x04,0x01,0x02,0x03,0x02,0x02,0x09,0xe5,0x03,
+ 0x03,0x09,0x04,0x01,0x02,0x09,0x09,0x09,0x09,0x09,0x0d,0x01,0x01,0xe5,0x01,0x24,
+ 0x02,0x06,0x02,0x12,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x02,0x04,0x04,0x09,0x1d,0x1f,
+ 0x08,0xe5,0x08,0x1d,0x43,0x01,0x01,0x25,0x02,0x0a,0x13,0x07,0x09,0x0a,0x08,0x0b,
+ 0x1d,0x1f,0x07,0x0b,0x05,0x16,0x45,0xe5,0x01,0x01,0x1c,0x05,0xe6,0x03,0x01,0xe5,
+ 0x04,0xe5,0xe5,0x06,0x01,0x02,0x03,0xe5,0xe5,0x01,0x0d,0x07,0x05,0xe6,0x02,0x03,
+ 0xe6,0xe5,0x06,0x04,0x02,0xe6,0x08,0x06,0x01,0xe7,0x03,0x01,0x13,0x04,0x07,0x01,
+ 0x05,0xe6,0x03,0x04,0x06,0x02,0x09,0x3f,0xe6,0x24,0x05,0x01,0x07,0x01,0xe5,0x05,
+ 0x01,0x01,0x05,0x01,0xe6,0xe5,0x06,0x08,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x04,0x03,
+ 0x01,0x03,0x02,0xe5,0x01,0x02,0x03,0x01,0x05,0x01,0xe6,0xe5,0x02,0x01,0xe6,0x08,
+ 0x08,0xe5,0x08,0x04,0x03,0xe5,0x04,0x02,0xe5,0xe5,0x04,0x01,0x09,0x01,0x35,0x04,
+ 0x02,0xe7,0x26,0x03,0x01,0x09,0x04,0x04,0x03,0xe5,0x01,0x01,0x13,0x0a,0x02,0xe5,
+ 0x05,0x02,0x08,0x03,0x03,0x11,0x01,0x07,0x01,0x1d,0x09,0x03,0x17,0x42,0x02,0xe5,
+ 0x14,0xe5,0x07,0xe5,0x02,0x04,0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x01,0x05,0xe6,0x06,
+ 0xe5,0x06,0xe7,0x06,0xe5,0x05,0xe7,0x06,0xe7,0x06,0xe6,0x05,0xe7,0x06,0xe5,0x01,
+ 0x01,0xe5,0x03,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x01,0x04,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe6,0x03,0x04,0xe5,0x23,0xe5,0x04,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x07,
+ 0x01,0xe5,0x04,0x0d,0xe5,0x04,0x02,0x10,0x01,0x13,0x0b,0x0a,0x08,0x11,0x02,0x06,
+ 0x0b,0xe5,0x49,0x01,0xe5,0x2a,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0x10,0x05,
+ 0x02,0x02,0x04,0xe7,0x07,0xe5,0xe5,0x03,0x01,0xe5,0x07,0x04,0x09,0x0a,0x1c,0x07,
+ 0x0b,0x43,0x05,0x02,0xe6,0x2c,0x13,0xe5,0x07,0x07,0x01,0x04,0x13,0xe5,0x03,0x0e,
+ 0x01,0x01,0x05,0x0c,0xe5,0x0a,0x1b,0x09,0x01,0xe5,0x12,0x42,0x06,0x02,0xe5,0x25,
+ 0x04,0x01,0x13,0x02,0x04,0x04,0x07,0x01,0x09,0x09,0xe5,0xe6,0x04,0xe6,0xe6,0x03,
+ 0xe9,0xe5,0x01,0xe9,0x03,0x01,0x01,0x04,0x02,0x06,0x02,0x09,0x09,0x06,0x02,0x04,
+ 0x01,0x02,0x09,0x09,0x09,0x3b,0x02,0x02,0x2b,0xe5,0xe5,0x05,0x01,0xe5,0x08,0xe5,
+ 0x07,0x10,0x02,0x09,0xe5,0x04,0xe5,0xe5,0x05,0x01,0xe5,0x03,0x03,0xe6,0x02,0x01,
+ 0x45,0x0e,0x17,0x1d,0x0a,0x0a,0x01,0x01,0x0f,0x01,0x07,0x01,0x07,0x01,0x03,0x03,
+ 0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x07,0xe6,0xe5,0x04,0x01,0x07,0x01,0xe6,0x04,
+ 0x01,0xe5,0x01,0x03,0x01,0x04,0x02,0xe6,0xe5,0x03,0xe5,0xe5,0x06,0x01,0xe6,0x01,
+ 0x04,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0xe6,
+ 0x03,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x03,0x07,0xe7,0x3e,0x02,0x06,0x01,0xe5,0x07,0xe5,0xe5,0x01,0xe7,0xe5,
+ 0x01,0x03,0x0b,0x01,0xe5,0x05,0xe5,0x09,0x06,0xe6,0x09,0xe6,0x06,0x14,0x04,0x03,
+ 0xe5,0x04,0x02,0xe5,0xe5,0x07,0x05,0x01,0x04,0x04,0xe5,0x41,0xe6,0x14,0x1b,0x0b,
+ 0xe5,0x04,0x03,0x14,0x11,0x02,0xe5,0x05,0x08,0x03,0xe5,0x03,0xe5,0x01,0x07,0xe5,
+ 0x04,0x09,0x09,0xe5,0x01,0x06,0x0d,0xe5,0x03,0x0b,0x02,0x02,0x04,0x01,0x3f,0x01,
+ 0xe7,0x1e,0x05,0x01,0x0c,0x03,0x0a,0xe5,0x04,0x08,0x01,0x04,0x06,0x08,0x0e,0x03,
+ 0x04,0x01,0x09,0x02,0x05,0xe6,0x02,0x03,0x05,0x1b,0x01,0x06,0x61,0xe8,0x24,0x05,
+ 0xe5,0x01,0x02,0x02,0x08,0x0c,0x07,0xe5,0x09,0x09,0x07,0xe6,0x05,0x0c,0x04,0x10,
+ 0x05,0x01,0x01,0x14,0x06,0x01,0x01,0x05,0xe6,0x01,0x09,0x0e,0xe6,0x3a,0x05,0x01,
+ 0xe5,0x37,0x10,0x03,0x15,0x03,0x0a,0x06,0x09,0x15,0x05,0x05,0x01,0x03,0x08,0x0d,
+ 0x02,0x08,0x1d,0x3d,0x02,0xe6,0x01,0x23,0x0a,0x07,0xe5,0x02,0x01,0x03,0x0d,0x09,
+ 0x03,0x01,0x17,0x0d,0x05,0x09,0x02,0xe5,0xe5,0x24,0x01,0x01,0x08,0xe5,0x03,0x0e,
+ 0xe5,0x47,0x01,0x02,0x11,0x0c,0x02,0xe5,0x02,0x02,0x07,0x03,0x02,0x06,0x02,0x17,
+ 0x02,0xe5,0x0c,0x04,0x01,0x0a,0x0f,0x03,0x06,0x10,0x01,0x07,0x0a,0x03,0x07,0x0b,
+ 0x01,0x02,0x04,0xe5,0xe5,0x31,0x15,0x01,0xe5,0xe5,0x20,0x05,0x0d,0x09,0x02,0x16,
+ 0x03,0x06,0x1a,0x0e,0x05,0x04,0xe5,0x27,0x02,0x05,0x14,0x4d,0x02,0x47,0x08,0x12,
+ 0x03,0xe5,0x01,0x05,0xe6,0x06,0xe6,0x0b,0xe5,0x02,0x07,0x01,0x07,0x07,0x0f,0xe5,
+ 0x11,0xe6,0x10,0xe6,0x48,0xe5,0xe5,0xe5,0x13,0x39,0x1a,0x04,0x04,0x09,0x0e,0x02,
+ 0x09,0x05,0x19,0xe5,0x01,0x11,0x02,0x01,0x06,0x02,0x04,0x0d,0x3c,0x01,0xe6,0x27,
+ 0x09,0x02,0x01,0x02,0x21,0x06,0x04,0x07,0x02,0x09,0x0a,0x1b,0x14,0x01,0x09,0x04,
+ 0x02,0x01,0xe5,0x05,0x01,0x01,0x04,0xe5,0xe5,0x48,0xea,0x09,0x19,0x11,0x07,0x01,
+ 0xe5,0x03,0x10,0x02,0x06,0x0b,0x03,0x01,0x02,0x04,0xe5,0x17,0x0b,0x08,0x18,0x0a,
+ 0x01,0x07,0x09,0x35,0x16,0x01,0x05,0xe5,0x1d,0x11,0x03,0x07,0x13,0x13,0x10,0x11,
+ 0x1f,0x18,0x06,0x09,0x04,0x04,0x02,0x09,0x38,0x05,0xe6,0xe7,0x32,0x0d,0xe5,0x25,
+ 0x12,0xe5,0x08,0x01,0xe5,0x05,0x01,0xe5,0x11,0x13,0x0c,0xe5,0xe5,0x02,0x05,0x0d,
+ 0x46,0x03,0x01,0x02,0x01,0x1d,0x08,0xe5,0x07,0xe6,0x03,0xe5,0x25,0x01,0x11,0x01,
+ 0x0b,0x02,0x01,0xe5,0x04,0x02,0xe5,0x10,0x0d,0x01,0x0a,0x06,0xe5,0xe6,0xe5,0x05,
+ 0xe5,0x0a,0x44,0x02,0xe6,0x01,0xe5,0x03,0x19,0x01,0x0c,0x04,0x01,0x0a,0x03,0x0f,
+ 0x01,0x04,0x01,0xe5,0xe5,0x0a,0x12,0xe6,0x05,0x35,0x01,0xe5,0x03,0x04,0xe5,0xe5,
+ 0xe5,0x06,0x01,0x04,0xe5,0xe5,0xe5,0x3f,0x01,0x02,0x05,0x02,0x02,0x28,0x06,0x08,
+ 0xe5,0x01,0x13,0x01,0x04,0x02,0x01,0x1c,0x42,0xe5,0x01,0x06,0x02,0x01,0x04,0x02,
+ 0x01,0x03,0xe5,0x01,0x01,0x40,0xe5,0x04,0x02,0x01,0xe6,0x23,0x05,0x02,0x05,0xe5,
+ 0x06,0x01,0x02,0x02,0xe5,0x01,0x12,0x01,0x06,0x01,0x05,0x06,0x06,0x03,0xe5,0x06,
+ 0x06,0x34,0x01,0x05,0xe6,0xe5,0x01,0xe5,0xe7,0xe6,0x02,0x01,0x03,0x05,0x42,0xe7,
+ 0xe5,0x01,0x26,0x01,0x03,0x03,0x01,0x03,0x02,0x01,0xe5,0x02,0x02,0x01,0x0e,0x09,
+ 0x02,0x01,0x0e,0x01,0x01,0xe5,0x02,0x0d,0xe6,0x33,0x01,0x01,0x03,0x01,0x01,0x01,
+ 0x04,0xe5,0xe6,0x01,0x02,0x02,0xe5,0x03,0x3e,0x03,0x01,0x01,0x01,0xe5,0x2b,0x11,
+ 0x01,0x01,0x0f,0x01,0x07,0x01,0x02,0xe6,0x05,0x07,0x0a,0x08,0x19,0xe5,0x1f,0x01,
+ 0x07,0x01,0x01,0xe5,0x01,0x01,0x01,0x07,0x01,0x4a,0x01,0xe6,0x2a,0x13,0x04,0x0e,
+ 0x01,0x07,0x01,0x02,0x09,0x15,0x01,0x05,0x33,0x04,0x01,0x07,0x01,0x02,0x04,0x01,
+ 0xe5,0x05,0x01,0xe5,0x4b,0xe5,0x26,0x13,0xe5,0x07,0x02,0x06,0x13,0xe5,0x04,0x0c,
+ 0x02,0x26,0x02,0x06,0x13,0x02,0x06,0x02,0x06,0xe5,0x04,0x09,0x02,0xe5,0x43,0x04,
+ 0x28,0x01,0x1b,0xe5,0x07,0x01,0x11,0x05,0xe5,0x0b,0xe5,0x03,0x0a,0x02,0x06,0x0b,
+ 0x0e,0x0e,0x02,0x11,0x01,0xe5,0x07,0x06,0x02,0x46,0x02,0xe5,0x0d,0x09,0x06,0x02,
+ 0x03,0x05,0x09,0x02,0x03,0x02,0x09,0x03,0x05,0x02,0x03,0x02,0x03,0x05,0xe6,0x06,
+ 0x02,0x03,0x02,0xe5,0x07,0x05,0x03,0x0b,0x09,0x09,0x09,0x03,0x05,0x09,0x06,0x02,
+ 0xe5,0x01,0x05,0xe6,0xe5,0x04,0x09,0x09,0x09,0x09,0x09,0x0d,0x01,0x02,0x02,0x1c,
+ 0xe5,0x12,0x08,0xe5,0x08,0x12,0xe5,0x1b,0x3e,0x1c,0x0a,0x4d,0xe5,0x01,0x1f,0x11,
+ 0x0a,0x09,0x12,0x39,0x0b,0x17,0x05,0x1f,0x51,0x01,0xe5,0x23,0x12,0x07,0x01,0x09,
+ 0x11,0x01,0x0a,0xe6,0x03,0x01,0x04,0x02,0x02,0x0b,0x01,0x07,0x06,0x01,0x02,0x09,
+ 0x0e,0x04,0x03,0xe5,0xe5,0x03,0x02,0x01,0x02,0x04,0x01,0xe5,0x02,0x05,0x01,0x47,
+ 0xe5,0x01,0x35,0x01,0xe5,0x05,0x01,0xe6,0x04,0x02,0x0d,0x01,0xe5,0xe7,0x08,0x04,
+ 0xe5,0xe6,0x05,0x02,0x03,0x06,0x01,0x07,0x07,0x01,0xe6,0x03,0x03,0xe5,0x0e,0x02,
+ 0xe5,0x04,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x09,0x01,0x41,0x04,0x01,0xe6,0xe6,
+ 0x21,0x13,0x07,0x01,0x03,0x03,0x01,0x11,0x0c,0x06,0x09,0x09,0x01,0x1d,0x01,0x0e,
+ 0x01,0x06,0x02,0x02,0x04,0x04,0x07,0x01,0x4a,0x09,0x03,0x15,0xe5,0x07,0xe6,0x06,
+ 0xe5,0x07,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe5,0x05,0xe5,0xe6,0x06,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe6,0xe5,
+ 0x04,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x03,0x01,0xe5,
+ 0x01,0x37,0x0a,0x06,0x01,0x0a,0x06,0x01,0xe5,0x08,0xe5,0x04,0x01,0xe5,0x05,0x02,
+ 0x1c,0x01,0x1e,0x06,0x01,0x07,0x01,0x07,0x01,0x54,0x01,0xe6,0x34,0x01,0x07,0x09,
+ 0x01,0x11,0x01,0x0d,0x02,0xe5,0xe6,0x08,0x1c,0x01,0x1b,0x02,0x06,0x01,0x07,0x01,
+ 0x07,0x01,0x09,0x43,0x05,0x02,0xe6,0x36,0x0a,0x06,0x01,0x0a,0x06,0x01,0xe5,0x0c,
+ 0xe7,0x08,0x1e,0x0a,0x01,0x27,0x09,0x4d,0x06,0x01,0xe6,0x34,0x01,0x0c,0x04,0x01,
+ 0x0a,0x06,0x01,0xe5,0xe5,0x08,0xe5,0x02,0x02,0x09,0x0b,0x09,0x0b,0x04,0x01,0x02,
+ 0x13,0x10,0x02,0x04,0x01,0x0c,0x45,0x01,0x01,0xe6,0x20,0x01,0xe5,0x11,0xe5,0x05,
+ 0xe5,0xe5,0x13,0x05,0x27,0xe5,0xe5,0x39,0xe5,0xe5,0x19,0x4d,0x02,0x11,0x01,0x07,
+ 0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0xe5,0x01,0x03,0x01,0x07,0x01,0x07,0x01,
+ 0xe5,0x02,0x02,0x01,0xe5,0x04,0xe5,0xe7,0x04,0x01,0x01,0x05,0x01,0x01,0x01,0x03,
+ 0x01,0xe5,0xe5,0x03,0x01,0xe5,0x02,0x03,0xe5,0xe5,0x06,0x01,0x02,0x04,0x01,0x01,
+ 0x05,0x01,0x03,0x03,0x01,0x02,0x04,0xe6,0x06,0x01,0x04,0x01,0xe5,0xe5,0x06,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x0a,0x02,0xe5,0x21,
+ 0x05,0x19,0x0c,0x05,0x03,0x05,0xe5,0x09,0xe5,0x07,0x01,0xe6,0x06,0x05,0xe5,0x18,
+ 0x01,0x31,0x4d,0x09,0xe5,0xe7,0x28,0x15,0x01,0x0a,0x04,0x0a,0x01,0xe5,0x02,0x0a,
+ 0x14,0x01,0x11,0x01,0x24,0x09,0x12,0x50,0xe5,0xe5,0xe5,0x25,0x03,0x09,0x19,0x01,
+ 0xe5,0x01,0x0b,0x0e,0x05,0x01,0x07,0x07,0x11,0x09,0x09,0x06,0x7a,0x02,0x35,0x01,
+ 0x01,0x04,0xe5,0x08,0x01,0x0b,0x03,0x01,0x0c,0x03,0x0c,0x01,0xe5,0x05,0xe5,0xe6,
+ 0x07,0x03,0x16,0x0d,0x07,0xe6,0x12,0x4f,0x06,0xe7,0x1e,0x17,0xe5,0x06,0x03,0x03,
+ 0x01,0x13,0x18,0x03,0xe5,0x01,0x0c,0x0b,0x2a,0x13,0x51,0x02,0xe6,0xe7,0x12,0x04,
+ 0x08,0xe5,0x10,0x07,0xe5,0x0f,0x07,0x08,0x12,0x02,0x02,0x05,0x08,0x08,0x03,0x03,
+ 0x03,0xe5,0x0d,0x0b,0x16,0x0c,0x2a,0x24,0x01,0x01,0xe6,0x15,0x06,0x02,0x21,0xe5,
+ 0x03,0x13,0x01,0x0c,0x03,0xe5,0x0b,0x09,0x02,0x04,0x01,0x06,0x01,0xe5,0x28,0x0f,
+ 0x10,0x07,0x3d,0xe9,0x13,0x02,0x02,0xe5,0x04,0x10,0x11,0x06,0x0b,0x0c,0x0c,0x02,
+ 0x17,0x0c,0xe6,0x0f,0x09,0x6e,0x0b,0xe6,0x07,0x21,0x0c,0x07,0x02,0x15,0x08,0x04,
+ 0xe7,0x0c,0x03,0x02,0x01,0x06,0x02,0x04,0x01,0x06,0x01,0xe7,0x1f,0x0b,0x0b,0x07,
+ 0x04,0x48,0xe9,0x2a,0x0d,0x07,0x04,0x09,0x19,0x03,0x0e,0x0c,0x06,0x07,0x04,0xe5,
+ 0xe5,0x31,0x02,0x03,0x53,0x01,0xe5,0x18,0x09,0x0c,0x06,0x10,0x0a,0x01,0x04,0xe5,
+ 0xe5,0xe5,0xe5,0x01,0x06,0x02,0x04,0x2b,0x07,0x07,0x01,0x33,0x47,0x02,0xe6,0x09,
+ 0x17,0x32,0x09,0x06,0x18,0xe5,0x06,0x1e,0xe5,0x07,0x32,0x04,0x45,0x02,0x17,0x1d,
+ 0x1f,0x01,0x07,0x04,0x0c,0x2d,0x05,0x01,0x09,0x17,0x0a,0x59,0x01,0x01,0x01,0x19,
+ 0x09,0x09,0xe5,0x03,0x02,0x0a,0x0f,0x02,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x28,
+ 0xe5,0x32,0xe5,0x04,0x4e,0x01,0x03,0x01,0x02,0x01,0x16,0x09,0x08,0x13,0x10,0x03,
+ 0x09,0x05,0x02,0x01,0x01,0xe5,0x0a,0xe5,0x07,0x18,0x35,0xe5,0x55,0x02,0x01,0xe5,
+ 0x03,0x0f,0x01,0x02,0x04,0xe5,0x11,0x01,0xe5,0xe5,0x0d,0x01,0x0a,0x04,0x0a,0xe5,
+ 0x0d,0x01,0x07,0x5d,0x53,0xe5,0xe6,0xe5,0x10,0xe5,0xe5,0x05,0x13,0x02,0x01,0x0e,
+ 0x0c,0x10,0x0c,0x09,0x09,0xa2,0x02,0x01,0x01,0xe8,0x1a,0x02,0x03,0x02,0x01,0x01,
+ 0x08,0x13,0x0a,0xe5,0x08,0x06,0xe6,0x05,0x02,0x09,0x02,0x03,0x02,0x09,0xe5,0xe5,
+ 0x0a,0x3e,0x50,0xe5,0xe5,0xe6,0xe5,0x01,0x11,0x04,0x01,0x01,0xe5,0x03,0x03,0x0e,
+ 0x02,0x01,0x0e,0x01,0x01,0xe6,0x02,0x09,0x02,0x01,0xe5,0x02,0x04,0x04,0x02,0xe7,
+ 0x02,0x02,0x01,0xe5,0x01,0x04,0x01,0x01,0x01,0x09,0x8a,0x03,0xe6,0xe8,0x17,0x04,
+ 0x02,0x04,0x02,0x0b,0x01,0x02,0x0e,0x09,0x09,0x11,0x08,0x04,0x0a,0x06,0x01,0x04,
+ 0x06,0x3d,0x52,0x01,0xe7,0x1a,0x01,0xe6,0x01,0x02,0x09,0x04,0x01,0x04,0x01,0x0c,
+ 0x07,0x1a,0x01,0x07,0xe5,0xe5,0x05,0x02,0x06,0x01,0xe5,0xe5,0x02,0xe6,0x04,0x02,
+ 0x3b,0x01,0x01,0x4c,0x02,0x01,0x1a,0x02,0x02,0x1a,0x02,0x06,0xe5,0x07,0x02,0x1a,
+ 0x02,0x06,0x01,0xe5,0x07,0x04,0x02,0xe5,0x4c,0x53,0x03,0x1b,0x20,0x09,0x09,0x1d,
+ 0x10,0x08,0xe5,0x01,0x06,0x0b,0x3a,0xe5,0x51,0xe9,0x0d,0x06,0x02,0x01,0x07,0x06,
+ 0x02,0x06,0x02,0x03,0x05,0x03,0x02,0x02,0x05,0x03,0x04,0x01,0x02,0x02,0x06,0x03,
+ 0x05,0x09,0x04,0x01,0x02,0xe5,0x01,0x05,0x02,0x08,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0xe6,0x06,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x06,0x01,0xe5,0xe5,0x01,0x12,0xe5,
+ 0x08,0x06,0x02,0x08,0xe5,0x11,0xe5,0x1c,0x1d,0xa0,0x08,0xe5,0xe6,0x14,0x09,0x08,
+ 0x0a,0x13,0x1b,0x1b,0x01,0x11,0x9c,0x01,0x1a,0xe6,0xe5,0x06,0x04,0x09,0x0e,0x04,
+ 0x01,0x09,0x07,0x01,0x07,0x01,0x07,0x01,0x0c,0x07,0x01,0x03,0xe5,0x03,0x0b,0x06,
+ 0x09,0x28,0xe6,0x54,0x17,0x01,0x01,0x07,0x01,0x07,0x01,0x07,0xe5,0x02,0x06,0x05,
+ 0x01,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x04,0xe5,0xe6,0x02,0x02,0x01,0xe5,0x09,0x08,
+ 0xe5,0xe5,0x04,0xe6,0x01,0x08,0x01,0x05,0xe5,0x07,0xe5,0x27,0x52,0xe5,0xe6,0x13,
+ 0x04,0x01,0x02,0x0c,0x09,0x09,0x09,0x0b,0x07,0x01,0x07,0x09,0x13,0x01,0x07,0x11,
+ 0x02,0x02,0x06,0x02,0x22,0x06,0x01,0x52,0xe6,0x14,0xe6,0x06,0xe5,0x01,0x05,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x01,0x03,0xe8,0x05,0xe6,0x05,0x01,0xe6,0xe5,0x02,0xe7,0x01,0x04,0xe6,
+ 0x09,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0xe5,0x18,0x11,0x1d,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0xe6,0x04,0x01,0xe6,
+ 0x07,0x13,0x0a,0x09,0x09,0x28,0x54,0x02,0x17,0x0b,0x09,0x1b,0x01,0x05,0x01,0x01,
+ 0x09,0x07,0x01,0x04,0x01,0xe5,0xe5,0x05,0x03,0x02,0x02,0x09,0x03,0x03,0x01,0x02,
+ 0x0b,0x09,0x28,0x4c,0x05,0xe6,0xe6,0x0b,0x0c,0x11,0x13,0x09,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x05,0x01,0x01,0x06,0x0a,0x01,0x05,0xe6,0x0b,0x02,0x09,0x09,0x75,0x06,
+ 0x03,0x17,0x04,0x06,0x02,0x06,0x02,0x10,0x02,0x04,0x01,0x07,0x01,0x09,0x09,0xe5,
+ 0x02,0xe7,0x01,0x05,0x05,0xe5,0xe6,0x01,0x02,0xe8,0x04,0x01,0x01,0x02,0x04,0x06,
+ 0x09,0x2a,0x4f,0x01,0xe5,0x01,0xe5,0x15,0xe5,0xe5,0x19,0x02,0x1a,0xe5,0xe5,0x05,
+ 0x09,0x02,0x04,0x15,0x04,0x11,0x01,0x90,0x01,0xe5,0x10,0x01,0x04,0x02,0x01,0x07,
+ 0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x02,0x03,0xe5,0xe5,0x02,0x03,0x01,0xe5,
+ 0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,0x06,0xe5,0xe5,0x06,0x01,0x01,
+ 0x02,0x04,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0x06,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0c,
+ 0xe6,0x19,0x08,0x10,0xe5,0x18,0x05,0xe5,0x06,0xe6,0x05,0xe5,0x0d,0x0c,0x01,0xe7,
+ 0x03,0x04,0x02,0x08,0x8e,0xe5,0xe7,0x14,0xe5,0x0d,0x17,0x0e,0xe5,0x01,0x02,0xe5,
+ 0xe5,0x02,0x07,0x10,0xe5,0x03,0x03,0x07,0x1a,0xe5,0x08,0x80,0x01,0x02,0x22,0x11,
+ 0x21,0x02,0x03,0x01,0x0a,0x05,0x09,0x06,0x05,0x05,0x0a,0xe5,0x19,0x0c,0x05,0x20,
+ 0x46,0x02,0x0a,0x0e,0xe5,0x2f,0x07,0x01,0x18,0x15,0x02,0x09,0x09,0xe6,0x05,0x7f,
+ 0x03,0x04,0xe5,0xe7,0x17,0x30,0x0b,0x01,0x03,0x2a,0x12,0x01,0x04,0x0a,0x09,0x72,
+ 0x05,0xe5,0x01,0x3b,0x13,0x02,0xe5,0x01,0x1b,0xe5,0x09,0x03,0x08,0xe5,0x01,0x03,
+ 0x05,0x0c,0xe5,0x0c,0x07,0x01,0x05,0x02,0x21,0x05,0x13,0x28,0xe5,0xe5,0xe5,0x09,
+ 0x19,0x04,0x11,0x08,0x1d,0x02,0x04,0x06,0x01,0xe5,0x02,0x09,0x02,0x02,0x09,0x06,
+ 0x04,0x06,0x01,0x06,0x05,0x0e,0x04,0x11,0x0a,0x0a,0x0a,0x2c,0x05,0x02,0xe5,0xe5,
+ 0x41,0x01,0x07,0x01,0x01,0x07,0xe5,0x07,0x09,0x16,0x03,0xe5,0x0d,0x06,0x15,0x0e,
+ 0xe5,0x66,0xe5,0xe6,0x05,0x2b,0x26,0x0e,0x04,0x03,0x09,0xe5,0x03,0x07,0x01,0x01,
+ 0x07,0x03,0xe5,0x0c,0x27,0x10,0x4c,0x01,0xe6,0x38,0x0d,0x13,0x0a,0x03,0x06,0x0c,
+ 0x1a,0x47,0x4c,0x02,0xe5,0x04,0x36,0x0f,0x12,0x1c,0x03,0x08,0x01,0x09,0x13,0x17,
+ 0x0f,0x5b,0x02,0x01,0xe5,0x04,0x4b,0x16,0x01,0x09,0x09,0x05,0x01,0x19,0x82,0x0a,
+ 0xe7,0x04,0x03,0x3c,0x16,0x0b,0x24,0x04,0x10,0x8b,0xe6,0xe5,0x46,0x0d,0x0c,0xe5,
+ 0xe5,0x02,0x08,0xe5,0xe6,0x05,0x02,0xe5,0xe5,0x02,0x01,0xe5,0x06,0x14,0x4e,0xe5,
+ 0x31,0x01,0x02,0xe6,0xe5,0xe5,0x45,0x0b,0x0f,0x0c,0x02,0xe5,0x07,0xe5,0x01,0xe6,
+ 0x03,0xe5,0xe6,0x17,0x48,0x01,0x34,0x02,0x03,0xe6,0x03,0x44,0x06,0xe5,0xe5,0xe5,
+ 0x01,0x0e,0x03,0x02,0x01,0x0a,0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0x06,0x67,0x29,
+ 0xe5,0x03,0x04,0x01,0xe6,0x01,0x48,0x07,0x01,0x04,0x0c,0x06,0x09,0x02,0x01,0x04,
+ 0xe5,0xe5,0xe5,0x06,0x93,0xe5,0x05,0x05,0xe6,0x47,0x04,0x0c,0x08,0x01,0xe5,0x03,
+ 0x02,0x01,0x07,0x06,0x09,0x03,0x02,0x02,0xe5,0x01,0x0c,0x1d,0x01,0x67,0x02,0x01,
+ 0x02,0x06,0x02,0x3e,0x02,0x01,0x01,0x04,0x09,0x02,0x01,0xe5,0x02,0x05,0x03,0x09,
+ 0x09,0x03,0x01,0x03,0x02,0x01,0x0c,0x1d,0x01,0x01,0x64,0x02,0xe8,0x47,0x09,0x01,
+ 0x07,0x09,0x03,0x0f,0x01,0x01,0x07,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0x0d,0x1d,
+ 0x01,0x6a,0xe6,0x4a,0x07,0x01,0x02,0x06,0x07,0x04,0x0e,0x01,0x02,0x04,0x04,0xe6,
+ 0x01,0x05,0xe5,0x0d,0x04,0x18,0x01,0x6a,0xe7,0x57,0xe5,0x07,0xe5,0x11,0x02,0x10,
+ 0x06,0x9a,0xe6,0xe6,0x4c,0xe5,0x0a,0x09,0x13,0xe5,0x0e,0x02,0x01,0x03,0xe5,0x14,
+ 0x85,0x02,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x06,0x02,0x06,0x02,0x03,0x05,0x03,
+ 0x05,0x09,0x09,0x09,0x02,0x02,0x03,0xe6,0x08,0x06,0x02,0x09,0x06,0x02,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x06,0xe7,0xe5,0x01,0x44,0xe5,0x03,
+ 0x01,0x02,0x4e,0x02,0x12,0xe5,0x69,0x02,0x07,0x01,0xe6,0x46,0x08,0x38,0x18,0x13,
+ 0x6c,0x0a,0xe6,0xe5,0x3d,0xe5,0xe5,0x03,0x02,0x01,0x09,0x13,0x07,0x01,0x0e,0x02,
+ 0x01,0x02,0x04,0x01,0xe6,0x12,0x02,0x10,0x73,0x01,0xe5,0x3e,0x01,0xe5,0x07,0xe6,
+ 0xe5,0x02,0x02,0xe5,0x07,0x08,0xe6,0x03,0xe5,0xe6,0x09,0x04,0xe5,0xe7,0x04,0x01,
+ 0xe6,0x10,0x03,0x01,0x0d,0x02,0x72,0xe7,0x3e,0x01,0x07,0x01,0x06,0x06,0x05,0x09,
+ 0x1b,0x06,0x01,0xe5,0xe5,0x14,0x03,0x0c,0x02,0x3f,0x32,0xe5,0x01,0x15,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x01,
+ 0x03,0x01,0xe5,0x01,0x04,0x01,0x07,0xe6,0x05,0x02,0xe5,0x04,0x02,0xe5,0xe6,0x02,
+ 0xe6,0x09,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,
+ 0x48,0x01,0x17,0x03,0x01,0xe5,0x05,0x01,0x0a,0x06,0x01,0xe6,0x07,0xe5,0x01,0x24,
+ 0x28,0x4b,0x01,0x49,0x01,0x19,0x01,0x01,0xe5,0x04,0xe5,0xe5,0x05,0x03,0x05,0xe5,
+ 0xe5,0x05,0x09,0x20,0x2a,0x4c,0xe5,0x48,0x01,0x1b,0x01,0x04,0xe7,0xe5,0x03,0x01,
+ 0x06,0x01,0xe6,0x04,0x01,0xe5,0x08,0x01,0x20,0x72,0xe8,0x48,0x01,0x02,0x09,0x0e,
+ 0x01,0x02,0xe5,0x02,0x01,0x0c,0x01,0x02,0x04,0xe6,0x06,0x15,0x0e,0x2a,0x49,0x02,
+ 0xe5,0x56,0x0f,0x01,0xe5,0x05,0x2e,0x05,0x01,0x17,0x60,0x0d,0xe7,0xe5,0x0e,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0xe6,0xe5,0x02,0x01,0x04,0x02,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0x05,
+ 0x01,0x04,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x0a,0xe8,0x0b,0x30,0x11,0x09,0x16,0x06,0x2f,0x0f,0x77,0xe5,0xe6,0x1c,0x0b,0x12,
+ 0x0a,0x09,0x07,0x23,0x0e,0x07,0xe5,0x0c,0x09,0x05,0x5c,0x1b,0xe9,0x3c,0x05,0x13,
+ 0x2b,0x04,0x10,0x06,0x06,0x35,0x11,0x0c,0x32,0x02,0x0a,0x34,0x01,0xe5,0x01,0x05,
+ 0xe5,0x05,0xe7,0x05,0x02,0x06,0x01,0xe5,0x02,0x02,0x02,0x17,0xe5,0xe5,0xe5,0x12,
+ 0xe6,0x0b,0x0c,0x10,0x5a,0x01,0xe7,0x3f,0xe5,0xe5,0xe5,0x02,0x0f,0x01,0x03,0x06,
+ 0x01,0xe5,0x05,0x02,0x0d,0x01,0x0b,0x02,0x03,0x02,0x0b,0x12,0x04,0x02,0x29,0x0f,
+ 0x33,0x01,0xe6,0x3a,0x05,0x0f,0x01,0x06,0x07,0x05,0xe5,0x1b,0xe5,0x08,0x03,0x03,
+ 0x03,0x10,0x05,0x3b,0x09,0x03,0x1b,0x06,0x0b,0x01,0x01,0xe5,0x0b,0x23,0x0e,0x04,
+ 0x11,0x10,0x02,0x04,0x06,0x09,0x04,0x03,0x05,0x01,0xe5,0x02,0x02,0x02,0x0b,0x0e,
+ 0x04,0xe5,0x11,0x0c,0x06,0x4d,0x05,0x39,0x02,0x03,0x07,0x0b,0x0c,0x0d,0x02,0x07,
+ 0xe5,0x04,0x02,0x01,0x05,0x01,0x04,0xe5,0x04,0x15,0x31,0xe5,0x36,0x10,0x05,0x47,
+ 0x03,0x07,0x04,0x06,0x05,0x01,0x02,0xe6,0xe5,0x04,0x07,0x01,0x04,0x04,0x06,0x03,
+ 0x01,0xe6,0x10,0x01,0x3a,0x13,0x0d,0x04,0xe6,0x17,0x01,0xe6,0x04,0x49,0x10,0xe5,
+ 0x02,0x08,0x04,0x15,0x0f,0x03,0x4e,0x15,0x13,0x19,0xe6,0x04,0x39,0x01,0x04,0x06,
+ 0x04,0x02,0x1a,0xe7,0x12,0x15,0x19,0x1b,0x09,0x26,0x29,0x02,0xe6,0x04,0x3a,0x11,
+ 0xe6,0x14,0xe5,0x03,0x01,0x01,0x07,0x08,0xe5,0x01,0x02,0x06,0x07,0xe5,0x01,0x1e,
+ 0x24,0x3f,0x09,0x03,0x05,0x3b,0x2b,0x0c,0x01,0x05,0x04,0x0e,0x05,0x0c,0x5c,0x27,
+ 0xe6,0xe5,0x01,0x08,0x1a,0x09,0x25,0x06,0x02,0x11,0xe5,0x08,0x08,0xe5,0x0a,0x08,
+ 0xe5,0xe5,0x05,0x01,0x07,0x21,0x09,0x22,0x1d,0x03,0x06,0x07,0xe6,0x07,0x01,0x41,
+ 0xe5,0x12,0x06,0x01,0x06,0x02,0xe5,0x07,0xe5,0x07,0x07,0x01,0x09,0x09,0x09,0x09,
+ 0x01,0xe5,0x04,0x21,0x12,0xe5,0x04,0x03,0x08,0xe5,0x07,0x06,0x05,0x07,0xe5,0xe6,
+ 0xe8,0x54,0x02,0xe5,0x04,0x05,0x03,0xe5,0x07,0x01,0xe5,0x0b,0x06,0x01,0x10,0x02,
+ 0xe5,0x04,0x02,0xe5,0x0e,0xe7,0x08,0xe5,0x04,0x09,0x02,0xe5,0x04,0x13,0x09,0x02,
+ 0x01,0x04,0x09,0x09,0x0a,0xe8,0xe5,0x01,0x01,0x37,0xe5,0x14,0xe5,0x01,0x02,0xe5,
+ 0x04,0x02,0x01,0x01,0xe5,0x0a,0x02,0xe5,0x0a,0x06,0x01,0x0c,0xe5,0xe5,0x02,0xe5,
+ 0x04,0x11,0x01,0x01,0xe5,0x02,0x05,0xe5,0x01,0x01,0x07,0x01,0x03,0xe5,0x01,0x01,
+ 0x03,0xe5,0x01,0x05,0xe5,0x01,0x03,0x01,0xe5,0x01,0x05,0xe5,0x01,0x02,0x06,0x02,
+ 0x02,0xe5,0x04,0x07,0x01,0x02,0xe5,0x01,0x04,0x37,0xe5,0xe5,0x14,0x0e,0x01,0xe5,
+ 0xe5,0xe5,0xe6,0x01,0x01,0x11,0x0e,0x08,0x22,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x09,0x06,0x02,0x06,0xe5,0xe5,0x06,0x01,0x0c,0x01,0x09,0x04,0xe5,0xe6,0x01,
+ 0x38,0xe5,0x01,0x13,0x15,0x03,0xe5,0x01,0x01,0x11,0x05,0xe5,0x0d,0x1f,0x04,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0xe5,0xe5,0xe5,0x0a,0x03,0xe5,
+ 0xe5,0x54,0x02,0x03,0x05,0x04,0x01,0x02,0x09,0x09,0x09,0x06,0x06,0x08,0x02,0x05,
+ 0x09,0x09,0xe5,0x01,0x02,0x02,0x06,0x02,0x03,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,
+ 0x01,0x02,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x02,0x01,0x01,0x02,0x02,0x01,0x01,
+ 0x02,0x02,0x03,0x05,0x0c,0x01,0xe5,0x01,0x40,0x0f,0x03,0x03,0x0d,0x01,0x01,0x02,
+ 0x04,0x14,0x08,0x01,0x01,0xe5,0x21,0x02,0x08,0x01,0x02,0x04,0x01,0x01,0xe5,0x03,
+ 0x09,0x02,0x01,0x04,0x02,0x01,0x04,0x03,0x05,0x02,0x01,0x04,0x02,0x01,0x04,0x02,
+ 0xe6,0x03,0x0a,0x05,0xe5,0x53,0x01,0x09,0x0b,0xe5,0x01,0x01,0x01,0x14,0x01,0x01,
+ 0x1d,0x11,0x01,0x06,0x09,0x0b,0xe5,0x19,0x02,0x01,0x0e,0x0c,0x02,0x01,0x01,0x0c,
+ 0x03,0x50,0x02,0x04,0x09,0x08,0xe5,0xe5,0xe6,0xe5,0x01,0x01,0x06,0x0a,0x01,0x01,
+ 0x11,0x08,0xe5,0xe6,0x04,0xe7,0x03,0x02,0xe7,0x02,0x02,0xe6,0x03,0x02,0x01,0x01,
+ 0x02,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe7,0x03,0x02,0xe6,
+ 0x03,0x01,0xe5,0xe5,0xe5,0x01,0x02,0x01,0x01,0x02,0x01,0xe5,0xe8,0xe5,0x01,0x0b,
+ 0xe5,0xe6,0x08,0x47,0x07,0xe5,0x04,0x09,0x02,0x02,0x03,0x04,0x04,0x29,0x04,0x04,
+ 0x06,0x09,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,
+ 0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x09,0x0a,0x01,0x01,
+ 0x0a,0x01,0x40,0x0c,0xe5,0x03,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0xe5,
+ 0x10,0x08,0xe5,0x07,0xe5,0x08,0x02,0x05,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x03,0x02,0xe6,0x08,0x01,0xe7,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x06,0x02,0x09,0xe6,0x02,0xe5,0x01,0xe5,0x07,0xe6,0x06,0xe5,0x07,0x04,0x01,0x02,
+ 0x0b,0x09,0xe5,0x07,0xe5,0x07,0x05,0xe6,0xe7,0x03,0xe5,0xe7,0x03,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe7,0x03,0xe5,0xe6,0x02,0x01,0xe5,0xe7,0x01,
+ 0x01,0xe5,0xe6,0xe5,0x05,0x06,0x06,0xe5,0xe7,0x01,0x3b,0x10,0x02,0x10,0x02,0x27,
+ 0x32,0xe6,0xe5,0x04,0xe6,0xe5,0x02,0x03,0x01,0x03,0x03,0x01,0x03,0x03,0x01,0x03,
+ 0x03,0x01,0x03,0x02,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0a,0x03,0x05,0x02,
+ 0xe5,0xe6,0x3b,0x10,0x02,0x12,0x07,0x13,0x0b,0x1d,0x09,0x09,0x01,0x06,0x02,0x06,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x02,0x06,0xe5,0x02,0x04,0x04,0x04,0xe5,0x15,
+ 0xe5,0x01,0x01,0x3d,0x01,0x0c,0x09,0x04,0x01,0xe7,0x02,0xe5,0xe6,0xe5,0x05,0xe7,
+ 0x05,0xe5,0x02,0x02,0x04,0x10,0x04,0x07,0xe6,0x06,0xe6,0x03,0x01,0x02,0x07,0xe6,
+ 0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,
+ 0xe5,0x06,0x09,0x01,0x01,0x01,0x41,0xe5,0x09,0x08,0xe5,0x04,0x01,0xe6,0x01,0x02,
+ 0x01,0xe6,0x06,0xe6,0x06,0xe6,0x04,0x03,0x02,0x01,0x03,0x08,0x03,0x01,0x07,0x09,
+ 0x05,0x01,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x01,0x06,0x0c,0x01,0x01,0x3f,0x01,0x13,0x0a,0x06,0x08,
+ 0x02,0x01,0x07,0x03,0x0d,0x01,0x09,0x05,0x10,0x0c,0x02,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x02,0x04,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x01,0x05,0xe5,0x08,0x02,
+ 0x03,0x08,0x0a,0x02,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x05,0xe7,0x01,0x03,0xe5,0xe5,0x01,0x03,0x01,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x05,0x02,0x08,0x03,0x02,0xe7,0x05,0xe7,0x05,
+ 0xe7,0x01,0xe5,0x01,0xe7,0x01,0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0x03,0xe7,0x01,
+ 0xe5,0x01,0xe7,0x01,0x03,0xe7,0x01,0x03,0xe7,0x01,0xe5,0x01,0xe7,0x01,0x03,0xe7,
+ 0x06,0xe6,0x07,0xe7,0x3e,0x01,0x0a,0x10,0x01,0x07,0x01,0xe6,0x06,0xe5,0x07,0x07,
+ 0x22,0xe5,0x0e,0x01,0xe6,0x01,0x02,0x02,0x06,0x02,0xe5,0x04,0x02,0x06,0x09,0x02,
+ 0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x06,0x09,0x03,0x41,
+ 0x1b,0x01,0x03,0x02,0xe5,0xe5,0x03,0x01,0x02,0xe5,0x01,0x05,0x07,0x1e,0x06,0x02,
+ 0x06,0x02,0xe5,0xe5,0x05,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0xe5,0x01,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x06,0x0b,0x3f,0x01,0x0a,0x08,0x0e,0xe5,0xe5,0x04,0x01,0xe5,0x01,0x05,
+ 0x03,0x13,0x05,0x02,0x08,0xe5,0x06,0xe5,0x07,0xe5,0x06,0x01,0x04,0x03,0xe5,0x07,
+ 0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x02,0x05,0x09,0x01,0xe5,0x40,0xe5,0x0a,0x09,0x09,0xe5,0xe6,0x01,0x02,0x01,
+ 0x04,0x02,0xe5,0xe5,0x02,0x02,0x09,0x04,0x02,0x0d,0xe6,0x06,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe8,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe7,0x03,0xe5,
+ 0xe6,0x08,0xe6,0x68,0xe5,0x19,0x09,0x02,0x0c,0x0a,0x08,0x05,0xe5,0xe5,0x03,0x01,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x06,0x01,0xe5,0x04,0xe5,0xe5,0x05,0xe5,0xe5,0x06,0x01,
+ 0x08,0xe5,0x02,0x03,0x01,0x04,0x02,0x01,0x18,0xe7,0x10,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0xe5,
+ 0x03,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x01,0x03,0x01,0x04,
+ 0x04,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0xe5,0x02,0x02,0x01,0x04,0x02,0xe6,
+ 0x06,0x01,0x01,0x02,0x02,0x01,0x04,0x02,0x01,0xe6,0x04,0x01,0x07,0x01,0x07,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0x0a,0xe5,0xe6,0x15,0x2c,0x07,0xe5,0x01,0x05,0x04,
+ 0x04,0x13,0xe5,0x07,0xe5,0x06,0x03,0x04,0x05,0x09,0x08,0x12,0xe5,0x07,0x03,0x01,
+ 0x0e,0x02,0x09,0x0f,0xe5,0x03,0x07,0x06,0x02,0x05,0x09,0xe5,0x0c,0x03,0xe5,0x3c,
+ 0x06,0x04,0xe5,0x02,0x11,0x0e,0x01,0x07,0x01,0x02,0x03,0x06,0x03,0x04,0x01,0xe5,
+ 0x08,0x02,0x01,0x06,0x0b,0x01,0x11,0x05,0x04,0x02,0x05,0x05,0x09,0x05,0x0f,0x02,
+ 0x07,0x05,0x04,0xe5,0x09,0x04,0xe5,0x02,0x44,0x09,0x05,0x0a,0x05,0x09,0x02,0x0a,
+ 0x18,0xe5,0xe6,0x02,0x0a,0x0a,0x06,0x08,0x19,0x0a,0x0c,0x03,0x19,0x0a,0x10,0xe7,
+ 0x46,0x0c,0x01,0x03,0x04,0x03,0x05,0x03,0xe5,0x05,0x02,0x06,0x09,0x04,0xe6,0x02,
+ 0x07,0x1e,0x03,0x02,0xe7,0x05,0x04,0x06,0x07,0xe7,0x05,0x01,0x07,0x01,0xe5,0x07,
+ 0x07,0x01,0x07,0x01,0x07,0xe6,0x0c,0xe6,0xe6,0x51,0x30,0x05,0x02,0xe5,0xe5,0x07,
+ 0xe6,0x08,0x10,0x0e,0x05,0x05,0x03,0x03,0x09,0x08,0x01,0x09,0x08,0x08,0x02,0x06,
+ 0x02,0x06,0x10,0x03,0xe5,0x43,0x0d,0x05,0x20,0x10,0x08,0xe5,0x02,0x01,0x04,0x0a,
+ 0x1c,0x17,0x06,0x01,0x0b,0x01,0x09,0x03,0x08,0x06,0x17,0x02,0xe6,0x3c,0x01,0x16,
+ 0x09,0x02,0x03,0x02,0x01,0x04,0x02,0x09,0xe5,0x07,0x10,0xe5,0x2a,0x0b,0xe5,0x05,
+ 0x09,0x09,0x06,0xe5,0xe5,0x05,0x04,0x0e,0xe6,0x12,0x08,0x03,0x3d,0x0c,0x08,0x01,
+ 0xe5,0x0d,0x06,0x02,0x01,0x13,0x03,0x0b,0x37,0x16,0x0c,0x03,0x05,0x02,0x03,0x06,
+ 0x20,0x02,0xe5,0x34,0x10,0x0d,0x02,0x01,0x07,0x08,0x04,0x08,0x03,0x01,0x0b,0xe5,
+ 0x07,0x03,0xe6,0x1a,0x0c,0x01,0x07,0xe5,0x05,0x04,0x20,0x03,0xe5,0xe5,0x05,0xe5,
+ 0x0f,0x01,0xe5,0x0e,0x01,0xe6,0x34,0x0d,0x0b,0x05,0x0d,0x19,0x02,0x0c,0x0b,0x30,
+ 0x02,0xe5,0x31,0x0a,0x13,0x0e,0xe5,0xe6,0x3c,0x07,0xe5,0x09,0x0c,0x1d,0x18,0x10,
+ 0x19,0x10,0x15,0x04,0x0c,0x04,0xe6,0x02,0xe5,0x02,0xe5,0x02,0xe5,0x01,0x01,0x03,
+ 0x04,0x11,0x01,0x3c,0x0b,0x03,0x02,0x09,0x04,0xe5,0x1c,0xe5,0x01,0x08,0x0a,0x07,
+ 0x01,0x07,0x09,0x3e,0x03,0xe5,0xe5,0x08,0x07,0x01,0x07,0x01,0x0f,0x08,0x02,0xe5,
+ 0x4c,0x02,0x06,0x07,0x0d,0x0d,0x01,0x03,0x13,0x07,0x07,0xe5,0x08,0x05,0x06,0x1e,
+ 0x0b,0x02,0x04,0x10,0x07,0x04,0x09,0x15,0xe5,0x01,0x01,0x3d,0x10,0xe5,0x04,0x09,
+ 0x02,0x01,0x07,0x01,0x04,0x05,0x0f,0xe5,0x07,0xe5,0x0a,0xe5,0x04,0x08,0xe5,0x15,
+ 0x01,0x04,0x08,0xe5,0x25,0xe5,0x08,0x1e,0x01,0x02,0xe6,0xe5,0xe5,0x39,0xe6,0x06,
+ 0x17,0x0c,0x01,0x0a,0x04,0x0a,0xe5,0x07,0xe5,0x03,0xe5,0x03,0xe5,0x0f,0x16,0x01,
+ 0x07,0xe5,0x25,0xe5,0x03,0x03,0x01,0x1e,0x01,0x02,0xe8,0xe5,0x03,0x3a,0x01,0x0c,
+ 0x08,0x01,0xe5,0x11,0xe5,0x05,0x05,0x06,0xe5,0xe5,0x16,0x0a,0xe5,0x26,0x09,0x16,
+ 0xe5,0x06,0xe5,0x0f,0x15,0xe5,0x01,0x01,0x05,0x01,0xe5,0x01,0x3c,0x01,0x07,0x0a,
+ 0x04,0xe5,0x11,0xe5,0x0b,0x06,0xe5,0x02,0x13,0x0a,0x55,0x26,0xe5,0x05,0x03,0xe8,
+ 0x08,0x01,0x32,0x0e,0x01,0x01,0x03,0x01,0x04,0x01,0x07,0x01,0x02,0x04,0x01,0x07,
+ 0x04,0x0b,0x01,0x0e,0x02,0x07,0xe5,0x27,0x27,0x02,0xe5,0x0e,0x04,0x01,0x17,0xe6,
+ 0x01,0x02,0x3c,0x09,0x02,0x01,0x07,0x06,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x03,
+ 0x1b,0x03,0x01,0x02,0x03,0x54,0x15,0x01,0x01,0x10,0x03,0x04,0xe6,0x3d,0x0c,0x01,
+ 0x07,0xe5,0x0e,0x01,0x01,0xe7,0x0b,0x03,0x02,0x02,0x06,0x09,0x06,0x01,0x02,0x05,
+ 0x03,0x24,0xe5,0xe5,0x23,0x02,0x09,0x01,0x0a,0x01,0x19,0xe7,0x3e,0x09,0x04,0x01,
+ 0x01,0x03,0x01,0x09,0x04,0x01,0x03,0xe5,0x06,0x04,0x04,0xe7,0x02,0x02,0x01,0xe6,
+ 0x06,0xe5,0x02,0x04,0x01,0xe6,0x02,0x04,0x24,0x01,0xe5,0x1e,0x07,0x01,0x06,0x01,
+ 0x04,0xe5,0x03,0x01,0x19,0x02,0xe5,0x43,0xe5,0x04,0x02,0xe5,0x18,0x2c,0x38,0x04,
+ 0x1b,0x13,0x02,0x03,0x1a,0xe5,0x03,0xe9,0x42,0x02,0x05,0x14,0x08,0xe5,0x08,0x13,
+ 0x09,0x02,0x12,0x0c,0xe5,0x17,0xe6,0x20,0x04,0x02,0x09,0xe5,0x03,0xe5,0x01,0x17,
+ 0x08,0xe6,0x0d,0x09,0x09,0x09,0x09,0x06,0x02,0x04,0xe6,0x01,0xe5,0x04,0x02,0xe5,
+ 0x07,0x09,0xe6,0x03,0x02,0x09,0x09,0x09,0x04,0xe6,0x03,0x04,0x01,0x02,0xe5,0x07,
+ 0x09,0x09,0x09,0xe6,0x06,0x09,0x09,0x09,0x01,0x01,0x05,0x04,0x01,0x02,0xe5,0x01,
+ 0x05,0x09,0x0d,0xe6,0x01,0x02,0x3a,0xe5,0x03,0x04,0x06,0x1d,0x02,0x27,0x38,0x22,
+ 0x13,0x26,0xe5,0xe5,0x3c,0x07,0x29,0x23,0x03,0x11,0x47,0x15,0x05,0x21,0xe7,0x4b,
+ 0x08,0xe5,0x0a,0x07,0xe5,0x04,0x04,0x06,0x0c,0x04,0x01,0x02,0x06,0x01,0x07,0x01,
+ 0xe5,0xe5,0x05,0x02,0x1b,0xe6,0x17,0x0b,0xe6,0x06,0xe6,0x03,0x02,0xe5,0xe5,0x05,
+ 0x1c,0x3e,0x03,0xe5,0xe5,0x01,0x03,0xe5,0x04,0x02,0xe5,0x01,0x02,0x03,0x01,0x07,
+ 0x07,0x01,0x01,0x05,0xe6,0x08,0x01,0x03,0x01,0xe6,0x01,0x06,0xe6,0x03,0x02,0xe6,
+ 0x06,0xe6,0x0b,0x09,0x06,0x19,0x03,0x09,0x04,0x0d,0xe5,0x06,0xe5,0x0f,0x04,0x05,
+ 0x32,0x09,0x02,0x09,0x01,0x06,0x02,0x0d,0xe5,0x0b,0x05,0x05,0x07,0x01,0x10,0x02,
+ 0x01,0x04,0x02,0x01,0x06,0x06,0x14,0x05,0x17,0x09,0x06,0x09,0x11,0x19,0x02,0x15,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe6,0xe5,0x04,0xe6,0x06,
+ 0xe6,0x06,0xe5,0x02,0x02,0xe7,0x01,0x05,0xe5,0x01,0x03,0x01,0xe6,0xe5,0x04,0xe5,
+ 0x06,0xe6,0x03,0x05,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x05,0xe7,0x07,0xe5,0x01,0x03,0xe7,
+ 0x07,0xe6,0x03,0x01,0xe6,0xe5,0x37,0x1a,0x01,0xe5,0x12,0xe5,0x01,0x01,0x09,0x02,
+ 0xe5,0x04,0x09,0xe5,0xe5,0x05,0x02,0x01,0x07,0x01,0xe5,0x1c,0x09,0xe5,0x18,0x0c,
+ 0x05,0x09,0x03,0x05,0x02,0x03,0xe5,0xe5,0x02,0x0d,0xe8,0x37,0x0e,0x0b,0x01,0x07,
+ 0x11,0xe5,0x08,0x02,0xe5,0x03,0xe5,0x07,0xe6,0xe5,0x03,0x01,0x04,0x09,0x1e,0x24,
+ 0x11,0xe5,0x06,0xe6,0x02,0x05,0x02,0x05,0xe5,0x02,0x11,0x49,0x09,0x01,0xe5,0x15,
+ 0x01,0x0d,0x03,0x01,0x09,0x0c,0xe5,0xe5,0x06,0x01,0xe5,0x4e,0x02,0x01,0x07,0x01,
+ 0x0d,0x05,0x14,0x01,0x0c,0x2b,0x0b,0xe5,0x04,0x02,0x04,0x01,0x02,0x04,0x04,0x09,
+ 0xe5,0x07,0x01,0x04,0x02,0x09,0xe6,0x06,0x01,0x06,0xe5,0xe5,0x05,0x02,0x09,0x11,
+ 0x0b,0x1d,0x09,0xe6,0x04,0x03,0x07,0x01,0x04,0x04,0x05,0x0e,0x02,0x3f,0xe5,0xe5,
+ 0x02,0x02,0x03,0xe5,0x0b,0x19,0x05,0x02,0x73,0x02,0x02,0x09,0x2b,0xe5,0xe6,0x10,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0xe5,0x05,0x01,0x01,0x05,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x01,
+ 0x01,0x05,0x01,0x01,0x02,0x04,0xe6,0x06,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0xe5,0x05,0x01,0xe5,0x05,
+ 0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x0a,0x01,0x01,0x40,0x02,0x04,0x02,0xe5,0x07,
+ 0xe5,0x04,0x02,0xe5,0x0c,0x06,0x05,0x0f,0x09,0x09,0x07,0xe5,0x07,0x17,0x13,0x09,
+ 0x0d,0x01,0xe6,0x04,0x05,0x01,0x04,0x02,0x20,0xe7,0x1e,0x09,0x13,0x03,0x02,0x02,
+ 0xe5,0x02,0x06,0x05,0x03,0x07,0x09,0x05,0x09,0x0d,0x04,0x06,0x06,0xe5,0x01,0x0f,
+ 0x0a,0x0b,0x13,0x09,0x09,0xe5,0x01,0x05,0x09,0x01,0x07,0x1a,0x01,0xe7,0x0a,0x30,
+ 0x0b,0x02,0x06,0x01,0x0a,0x0c,0x17,0x04,0x02,0x0c,0x0c,0x01,0x07,0x03,0x41,0x04,
+ 0x33,0x01,0xe5,0x15,0x32,0xe7,0x07,0x02,0x0b,0x01,0x0c,0x13,0xe5,0x25,0x01,0x0e,
+ 0x09,0x2c,0x09,0x07,0xe6,0x1c,0x04,0xe5,0xe7,0x43,0x04,0x06,0x02,0x16,0x19,0x13,
+ 0xe5,0x13,0x02,0x18,0x29,0x04,0x02,0x02,0x07,0xe5,0x0e,0x09,0x06,0x02,0x01,0xe8,
+ 0x2f,0x06,0x07,0xe5,0x01,0x06,0x02,0x0c,0x0c,0xe5,0x06,0xe6,0x02,0xe5,0x03,0x09,
+ 0x03,0x05,0x07,0x07,0x13,0x09,0x13,0xe5,0xe5,0x0f,0x09,0x02,0x05,0x0a,0x09,0x1d,
+ 0xe5,0xe8,0x3d,0x07,0x01,0xe5,0x14,0x06,0x0c,0x02,0x03,0xe5,0x01,0x05,0xe5,0xe5,
+ 0x05,0xe5,0x02,0x04,0x04,0x34,0x11,0x0a,0x02,0x18,0x0b,0x0b,0x08,0x03,0xe5,0x32,
+ 0x08,0x04,0x07,0x0f,0x0a,0x04,0x11,0x03,0x07,0x01,0x07,0x07,0x38,0x14,0x1c,0x29,
+ 0xe5,0xe7,0x50,0x08,0xe5,0xe5,0x03,0x21,0xe6,0x10,0x01,0x07,0x01,0x0a,0x08,0xe5,
+ 0x3a,0x01,0x02,0x04,0x05,0x03,0x08,0x09,0x0f,0x01,0x02,0x43,0x03,0x16,0x07,0x18,
+ 0x07,0x03,0x0d,0x01,0x09,0x05,0x01,0x02,0x07,0xe6,0x36,0x03,0x0b,0x09,0x06,0x09,
+ 0x11,0xe7,0x40,0x07,0x01,0x06,0x02,0x0d,0x05,0x04,0x04,0x04,0x09,0xe5,0x07,0x04,
+ 0x03,0xe5,0x33,0x28,0x13,0x27,0xe6,0x3f,0xe5,0x0c,0x04,0x02,0x10,0xe5,0x02,0x01,
+ 0x03,0x22,0x0c,0x0e,0x06,0x01,0x68,0x09,0x01,0x01,0x16,0x2a,0x27,0x07,0xe5,0x15,
+ 0x05,0x03,0x20,0x09,0x3b,0x0b,0x01,0x04,0x02,0x0b,0x04,0x01,0x0a,0xe5,0xe8,0x43,
+ 0xe5,0xe5,0x02,0xe7,0x04,0xe5,0x08,0x26,0x0d,0xe5,0x08,0xe5,0x05,0x09,0x09,0x09,
+ 0x02,0xe5,0x04,0x09,0x02,0xe5,0x04,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x04,0x0a,
+ 0x02,0xe7,0x01,0x01,0x40,0xe5,0x01,0xe6,0x03,0x01,0x0d,0x3f,0xe6,0x04,0x03,0xe5,
+ 0x03,0x03,0xe5,0x07,0x01,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,
+ 0xe5,0x04,0x09,0x09,0x09,0x09,0x02,0x01,0x04,0x07,0x02,0xe6,0x01,0xe5,0x03,0x37,
+ 0x01,0x0a,0x01,0x01,0x08,0xe5,0x0b,0xe5,0x06,0xe5,0x07,0xe5,0x21,0x01,0x1f,0x64,
+ 0x06,0x05,0x02,0x02,0x39,0x0c,0x01,0x08,0x01,0x0d,0xe5,0x06,0xe5,0x07,0xe5,0x1c,
+ 0x04,0x01,0x8d,0x04,0xe6,0x3c,0x03,0x06,0x05,0xe5,0x01,0x03,0x0b,0x09,0x09,0x09,
+ 0x04,0x06,0x01,0x02,0x02,0x01,0xe6,0x06,0x09,0x09,0x13,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x04,0x01,0x02,0x0a,0xe7,0xe5,0x01,0x3c,0x03,0x03,0x01,0x03,0x1e,
+ 0x09,0x09,0x06,0x01,0x02,0x01,0xe5,0x03,0x0a,0x7d,0x01,0x01,0x0a,0x03,0xe7,0x03,
+ 0xe5,0x45,0x0a,0x01,0x01,0x04,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x0b,0x02,0x06,
+ 0x01,0x01,0x02,0x24,0x09,0x0b,0xe5,0x19,0x02,0x01,0x0e,0x0c,0x02,0x01,0x01,0x10,
+ 0x01,0xe5,0x02,0x42,0x04,0x0b,0x07,0x01,0x01,0xe5,0xe5,0x01,0x04,0x01,0x02,0x04,
+ 0x01,0x02,0x06,0x03,0xe5,0x01,0x04,0x06,0x01,0x02,0x01,0xe5,0x04,0xe5,0x07,0xe5,
+ 0xe5,0xe5,0x04,0x09,0xe6,0x06,0x01,0x01,0x04,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0xe5,
+ 0x03,0xe5,0xe5,0xe5,0x04,0xe6,0x05,0xe5,0xe5,0xe5,0x04,0x01,0x01,0x04,0xe5,0xe6,
+ 0xe5,0xe5,0x01,0x0c,0x01,0xe5,0x44,0x13,0xe6,0x03,0x2a,0xe5,0x10,0x04,0x04,0x09,
+ 0x0c,0x06,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x04,0x0c,0xe6,0x01,0x46,
+ 0x01,0x11,0x05,0xe5,0x29,0x11,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x02,0x01,0x03,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x0b,0xe9,0x0d,0x09,0x09,0x09,0x09,0x06,0x02,0x02,0x02,0x03,0x02,0x01,
+ 0x01,0x02,0x05,0x03,0xe6,0x03,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x03,0x05,0x0b,
+ 0xe6,0x06,0xe5,0x07,0xe5,0x04,0x02,0x03,0x05,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x03,0x06,0x02,0x01,
+ 0x02,0x3a,0xe5,0x23,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x30,0x6d,0x02,0x08,0x02,
+ 0x3d,0x26,0x0a,0x08,0x08,0x27,0x09,0x09,0x1d,0x09,0x09,0x13,0x13,0x0d,0x09,0x01,
+ 0xe5,0xe5,0x46,0x01,0x07,0x03,0x08,0xe6,0x05,0x02,0x06,0x02,0x06,0x02,0x10,0x02,
+ 0x09,0xe6,0x06,0xe6,0x06,0xe6,0x08,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,
+ 0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x03,0x01,0xe7,0x0a,0xe5,0x01,0x42,
+ 0x05,0xe5,0xe7,0x03,0x03,0x0a,0x09,0x09,0x05,0x03,0x08,0x08,0x01,0x0b,0x09,0x09,
+ 0x04,0xe5,0x01,0xe5,0x08,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x01,0xe6,
+ 0x04,0x04,0x01,0x02,0xe5,0x3d,0xe5,0x08,0x01,0x0b,0x09,0x07,0x03,0x05,0x09,0x09,
+ 0x0e,0x07,0x3c,0x09,0x13,0x08,0x09,0x09,0x06,0x01,0x04,0x09,0x01,0x01,0x15,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x05,
+ 0xe7,0x05,0xe5,0xe5,0x05,0xe8,0x04,0xe5,0xe6,0x04,0xe5,0xe5,0x06,0xe6,0x07,0xe7,
+ 0x02,0x02,0xe7,0x02,0x02,0xe8,0x04,0xe7,0x02,0x02,0xe7,0x02,0x02,0xe7,0x05,0xe7,
+ 0x05,0xe7,0x02,0x02,0xe7,0x05,0xe7,0x05,0xe7,0x05,0xe7,0x05,0xe8,0xe6,0x01,0xe8,
+ 0x03,0x02,0xe7,0x48,0x02,0x06,0x0c,0x08,0x09,0x14,0x08,0x16,0xe5,0x07,0xe5,0x07,
+ 0x09,0xe5,0x07,0xe5,0x1b,0xe5,0x07,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x0d,0xe6,
+ 0xe5,0x48,0x02,0x16,0x02,0x06,0x02,0x07,0x01,0x06,0x02,0x03,0x02,0x02,0x02,0x06,
+ 0x0b,0x06,0x02,0x06,0x02,0xe5,0x01,0x02,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0x08,
+ 0x02,0x3f,0x09,0x16,0x03,0xe5,0x02,0x04,0xe6,0x01,0x03,0x01,0xe5,0x06,0xe7,0xe5,
+ 0x03,0xe6,0x06,0xe6,0xe5,0x05,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0x03,0x49,0x02,0x01,0x13,0xe5,0xe6,0x04,0xe5,0x07,0xe7,0x05,0xe5,0x02,
+ 0x01,0xe5,0x01,0xe5,0x06,0x02,0x08,0x01,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x06,0xe5,0xe6,0x42,0x08,0x5d,0x83,0xe8,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0xe6,0x03,0xe5,0xe5,
+ 0xe5,0x03,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0xe5,0x04,0xe6,0x05,0xe5,0xe5,0x03,0x04,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x02,0x04,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x0a,0x01,0xe6,
+ 0x48,0x15,0xe5,0x14,0x08,0xe5,0x0c,0x04,0x01,0x22,0x0c,0x03,0x06,0x08,0x03,0x06,
+ 0x02,0x05,0x0a,0x08,0x03,0x06,0x02,0x05,0x0a,0x0d,0x03,0xe5,0x3c,0x04,0x13,0x03,
+ 0x02,0x11,0x18,0x08,0x02,0xe5,0x09,0x2a,0xe5,0x10,0xe6,0x12,0x13,0x08,0x09,0xe5,
+ 0x02,0x0b,0x01,0x02,0x4f,0x07,0x07,0x29,0x01,0x0a,0x01,0xe5,0x1a,0x0e,0x13,0x13,
+ 0x13,0x13,0x0e,0x0d,0xe5,0x41,0xe5,0xe5,0x01,0x02,0x18,0x16,0xe5,0x07,0xe6,0x15,
+ 0x09,0x10,0x10,0x08,0x49,0x01,0x04,0x08,0xe7,0xe5,0x48,0x3b,0x03,0x0f,0xe5,0x06,
+ 0x08,0x10,0x40,0x1e,0x01,0x01,0x0e,0xe7,0x40,0x03,0x0b,0x03,0xe5,0x09,0x0b,0xe5,
+ 0x13,0x0c,0xe5,0x06,0x02,0xe6,0x12,0x01,0x14,0x09,0x13,0x13,0x1f,0x11,0xe6,0xe6,
+ 0x2f,0x0c,0x01,0x13,0xe5,0x14,0x02,0x10,0x0e,0x01,0x04,0x04,0x01,0x03,0x19,0x0c,
+ 0x13,0x13,0x05,0x0d,0x13,0x17,0x01,0xe6,0x3e,0x02,0x10,0x06,0x0a,0x05,0x09,0x19,
+ 0x09,0x01,0x04,0x18,0x75,0xe5,0xe5,0x4c,0x22,0x06,0x02,0x09,0xe5,0x04,0x02,0x06,
+ 0x01,0x01,0xe8,0x06,0xe5,0x07,0xe5,0x02,0x09,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x02,0x0b,
+ 0xe7,0x42,0xe6,0x1e,0x11,0x0d,0x10,0x02,0x03,0x09,0x02,0x06,0x13,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x08,0x10,0x01,0xe5,0x3b,0x04,0x05,0x0b,0x01,0x0d,0x14,
+ 0x09,0x04,0x03,0xe5,0x03,0x0b,0x03,0xe5,0x02,0x09,0x13,0x06,0x02,0x09,0x09,0x09,
+ 0x07,0x01,0x09,0x07,0x01,0x09,0x1b,0xe7,0xe5,0x3d,0x0a,0x1d,0x09,0x11,0xe5,0x07,
+ 0x01,0x03,0x05,0x0c,0x01,0x82,0x01,0xe6,0x3b,0x02,0x01,0x0b,0x38,0x11,0x65,0x2f,
+ 0xe5,0x01,0xe6,0x3c,0x02,0x01,0x0b,0xe5,0x03,0xe5,0x08,0x0f,0x03,0x09,0xe5,0x06,
+ 0xe5,0x01,0xe5,0xe5,0x02,0xe5,0x09,0xe5,0xe6,0x04,0x01,0xe5,0x05,0x08,0xe5,0x08,
+ 0x02,0xe5,0x04,0x09,0x02,0xe5,0x04,0x09,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x14,0x02,0x01,0xe5,0x01,0x01,0x3a,0xe6,0x0d,0xe5,0x07,0x01,
+ 0x0a,0x06,0x01,0xe5,0x05,0xe5,0xe5,0x05,0x01,0x01,0x05,0xe5,0xe5,0x0d,0x03,0xe5,
+ 0x03,0x09,0x03,0x01,0x07,0xe5,0x03,0x09,0x03,0x01,0x03,0x09,0x03,0x01,0x03,0x09,
+ 0x09,0x09,0x03,0xe5,0x03,0x03,0xe5,0x0c,0x02,0x04,0xe5,0x03,0x36,0xe5,0x01,0x01,
+ 0x0e,0xe5,0x04,0x09,0x0f,0x03,0x09,0x07,0x01,0x05,0x03,0x11,0x01,0x0e,0xe5,0x04,
+ 0x6b,0x04,0xe5,0x01,0x02,0x39,0xe5,0xe5,0x0f,0x16,0x09,0x09,0x13,0x11,0xe5,0x01,
+ 0x01,0x0e,0xe5,0x6b,0xe5,0x04,0x02,0xe5,0xe6,0x3e,0x01,0x04,0x01,0x08,0x0a,0x05,
+ 0x09,0xe5,0x01,0xe5,0x03,0x09,0xe5,0x01,0x02,0x04,0x01,0x05,0x08,0x02,0x01,0x01,
+ 0x05,0x09,0x07,0x05,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x05,
+ 0xe5,0x01,0xe5,0x01,0x3c,0x01,0x01,0x02,0x01,0x0e,0x01,0x01,0xe5,0x09,0x04,0x03,
+ 0xe5,0x02,0x05,0x04,0x03,0x04,0x0a,0x06,0x04,0xe5,0x01,0x04,0x16,0xe6,0x68,0x01,
+ 0xe5,0xe7,0x3d,0x01,0x04,0x0c,0x06,0x01,0x04,0x0c,0xe5,0xe5,0x02,0x0d,0x03,0x15,
+ 0x07,0x01,0x0d,0xe5,0x08,0x06,0x09,0x27,0x20,0x06,0x01,0xe5,0x08,0xe5,0x01,0x3f,
+ 0x01,0x04,0xe5,0x0c,0x04,0x07,0x04,0x04,0x02,0x01,0x04,0x01,0x02,0x04,0x13,0x06,
+ 0x04,0x04,0x01,0x01,0xe5,0x07,0xe5,0xe5,0x03,0x04,0xe5,0x05,0x01,0x01,0x05,0xe6,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x07,0xe8,0x05,0x01,0x0a,
+ 0x02,0x47,0x11,0x01,0xe5,0x02,0x13,0x04,0x07,0x13,0xe5,0x10,0x09,0x04,0x09,0x04,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x07,0x01,0x01,0xe5,0x45,0x19,
+ 0xe5,0x11,0xe5,0x01,0x0b,0x23,0xe5,0x07,0xe5,0x01,0x09,0x05,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0d,
+ 0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x05,0x03,0x09,0x09,0xe6,0x06,0x09,0xe6,0x02,
+ 0x03,0x09,0x09,0x04,0x01,0x04,0x09,0xe5,0x07,0xe5,0x03,0x03,0x03,0x05,0xe6,0x06,
+ 0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe6,0x03,0x06,0x01,0x02,0x02,0x63,0x1d,0x13,0x8c,0x08,0x01,0x01,0x63,0x1d,0x15,
+ 0x11,0x09,0x27,0x09,0x09,0x13,0x09,0x09,0x16,0x03,0x01,0x3f,0x11,0x01,0x0a,0xe6,
+ 0x05,0x02,0x04,0x01,0xe7,0xe5,0x01,0x01,0x02,0x0e,0x04,0x01,0x06,0x02,0x07,0xe6,
+ 0x03,0x01,0xe7,0x06,0x09,0xe6,0x06,0xe6,0x06,0x01,0x07,0x01,0x07,0xe6,0x06,0xe6,
+ 0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x0b,0xe5,0xe5,0x40,0xe5,0x0f,0x01,0xe5,
+ 0x09,0x05,0x03,0x04,0xe5,0xe7,0x04,0x01,0x01,0x08,0x03,0x02,0x03,0x0b,0x09,0x05,
+ 0x01,0xe6,0x12,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x01,0xe5,0x3d,
+ 0xe5,0xe5,0x10,0x0c,0x08,0x0b,0x16,0x10,0x71,0x10,0x0f,0x01,0x15,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0xe5,0x02,0x01,0xe5,0x05,
+ 0xe8,0x04,0xe6,0x06,0xe6,0x07,0xe5,0x06,0xe6,0x08,0x0a,0xe6,0x02,0x02,0xe7,0x02,
+ 0x02,0xe7,0x05,0xe7,0x02,0x02,0xe7,0x02,0x02,0xe7,0x05,0xe7,0x05,0xe7,0x02,0x02,
+ 0xe7,0x02,0x02,0xe7,0x02,0x02,0xe7,0x02,0x03,0xe6,0x02,0x02,0xe7,0x05,0xe7,0x01,
+ 0x05,0x01,0xe5,0x3e,0x01,0x11,0x01,0xe6,0x07,0x0e,0x01,0x01,0xe5,0x02,0x0c,0x01,
+ 0xe5,0x03,0x01,0x0d,0x0a,0x06,0x01,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x1b,0x09,
+ 0x09,0x09,0x09,0xe5,0x15,0x01,0x01,0x3f,0x01,0x11,0x01,0x05,0x07,0x02,0x06,0x02,
+ 0xe5,0xe6,0x01,0x02,0x09,0xe5,0x01,0x05,0xe5,0x07,0x0b,0x06,0x02,0xe5,0xe5,0x02,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x07,0x01,0x06,0x02,0x06,0x02,0x08,0x02,0x3f,0x01,0x11,0x05,0x06,0x03,0xe5,
+ 0x07,0xe5,0x08,0x08,0x02,0x01,0x03,0xe6,0x08,0x02,0x02,0x04,0xe5,0x03,0x03,0xe5,
+ 0x07,0xe5,0xe5,0xe5,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,
+ 0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x03,0x0d,0xe5,0x07,0xe5,0x07,0x01,0xe6,0x3e,
+ 0x01,0x11,0x01,0xe5,0x0a,0xe5,0xe6,0x04,0xe5,0x07,0xe5,0xe5,0x05,0x04,0x02,0x02,
+ 0x08,0x01,0xe5,0x07,0xe8,0x04,0xe5,0xe6,0x04,0xe5,0xe7,0xe6,0x01,0x01,0xe5,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0x01,0x01,0x05,0xe5,0xe6,0x04,0xe5,0xe6,0x06,0x02,0xe5,
+ 0x3c,0x03,0xe5,0x23,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x04,0x01,0x09,
+ 0x16,0x12,0x2b,0x06,0x09,0x03,0x05,0x09,0x22,0x01,0x01,0x0f,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,
+ 0xe5,0x02,0x02,0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x01,0x07,0x01,
+ 0x02,0x01,0x04,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0xe6,0x06,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0xe6,0x06,0x01,0x07,0x01,0x07,
+ 0x01,0x0b,0x01,0xe5,0x1f,0x2d,0x08,0x08,0x2e,0x05,0x11,0xe5,0x0f,0x0f,0x02,0x0c,
+ 0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x01,0x1c,0x03,
+ 0xe5,0x28,0x12,0x0a,0x08,0x05,0x02,0x02,0x08,0x09,0x06,0x02,0x0e,0x02,0x19,0x0c,
+ 0x09,0x1a,0x07,0x01,0xe5,0x06,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x1a,0x01,0xe7,
+ 0x32,0x0a,0x04,0x04,0x05,0x1b,0x05,0x09,0x09,0x06,0x02,0x07,0x01,0xe6,0x06,0x04,
+ 0x17,0xe5,0x17,0x13,0x09,0x05,0xe5,0x01,0x09,0x22,0x01,0xe6,0x41,0x09,0x04,0x05,
+ 0x0c,0x02,0x13,0x05,0x03,0xe6,0x09,0x0b,0x09,0x10,0x10,0x2f,0x11,0x20,0xe6,0x01,
+ 0x6a,0x02,0x10,0x03,0x01,0xe5,0x02,0x01,0x01,0x07,0x01,0x01,0xe5,0x05,0x15,0x03,
+ 0x0f,0x28,0x26,0x12,0xe8,0x2d,0x15,0x0a,0x0a,0x05,0x14,0x1d,0x05,0x02,0xe5,0x08,
+ 0x08,0xe5,0x08,0x03,0x13,0x13,0x09,0x09,0x09,0x09,0x09,0x07,0x0b,0xe5,0xe7,0x42,
+ 0x0a,0x1e,0x03,0x04,0x09,0x03,0x12,0x01,0x07,0x03,0xe5,0xe5,0x0a,0x04,0xe5,0x1f,
+ 0x50,0x01,0x02,0xe5,0x70,0x1b,0x0b,0x0d,0x13,0x02,0x08,0x13,0x01,0x16,0x39,0xe8,
+ 0x3f,0x01,0x0b,0x0b,0x20,0xe5,0x06,0xe6,0x06,0xe6,0x05,0x01,0x06,0x2c,0xe6,0x06,
+ 0xe5,0x07,0xe6,0x1a,0xe5,0x07,0x01,0x22,0xe8,0x40,0x02,0x39,0x09,0x09,0x05,0xe5,
+ 0x22,0x12,0x06,0xe5,0x09,0x1b,0xe5,0x05,0x26,0x01,0xe6,0x0a,0x3f,0x07,0x01,0x14,
+ 0x01,0x0f,0xe6,0x06,0x04,0xe5,0x02,0x03,0xe5,0x18,0x01,0x07,0x01,0x09,0x02,0x06,
+ 0x14,0x09,0x08,0x14,0x1c,0x07,0xe6,0x48,0x0a,0x10,0x21,0x28,0x09,0x11,0x01,0x25,
+ 0x01,0x03,0x35,0xe5,0x53,0x0f,0x06,0x0f,0x34,0x0a,0x07,0x09,0x04,0x22,0x38,0x01,
+ 0x01,0x01,0x6c,0xe5,0x04,0x09,0x09,0x09,0xe5,0x08,0xe5,0x04,0x18,0x0a,0xe5,0x05,
+ 0x09,0xe5,0x07,0xe5,0xe5,0xe5,0x03,0x09,0x09,0xe5,0x07,0xe5,0x0a,0xe5,0xe5,0x01,
+ 0xe5,0x09,0xe7,0x01,0x02,0x01,0x3b,0x2c,0xe5,0x02,0xe5,0x09,0x06,0x02,0x09,0x0c,
+ 0x07,0x08,0x09,0x16,0x09,0x09,0x01,0xe5,0x05,0x09,0x09,0x09,0x05,0xe5,0x04,0x01,
+ 0xe5,0x0a,0x01,0x03,0xe7,0x03,0x36,0xe5,0x06,0x04,0x0c,0x17,0xe5,0x02,0x01,0x05,
+ 0x10,0x01,0x02,0x03,0xe5,0x09,0xe5,0x08,0x09,0x0c,0x01,0x4f,0x07,0x03,0x07,0x04,
+ 0x01,0x01,0xe5,0xe5,0x38,0x09,0x0d,0x19,0x04,0x03,0xe5,0x01,0x09,0x06,0xe5,0xe5,
+ 0x16,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0xe5,0xe5,0xe5,0x4c,0x09,0x0d,0x03,0xe5,
+ 0xe6,0x3b,0x03,0x04,0xe6,0x05,0x02,0x03,0xe5,0x0e,0x04,0x02,0x03,0x0c,0x09,0x03,
+ 0x05,0x03,0x02,0x01,0x0c,0x01,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x0f,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x06,0x07,0x13,0xe6,0xe5,0x3f,0x02,0x01,0x04,0x04,0x03,0x10,
+ 0x04,0x06,0x01,0x0a,0x04,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x01,0x01,0x04,0x01,0x05,
+ 0x03,0x05,0x01,0x01,0x05,0x08,0x4b,0x03,0x01,0x02,0xe5,0x02,0x09,0x06,0xe5,0x47,
+ 0x07,0x04,0x03,0x09,0x01,0xe5,0x05,0x02,0x01,0x07,0x15,0x0b,0x02,0x09,0x02,0x15,
+ 0x01,0x0b,0x0c,0x10,0x02,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x07,0x07,0x0f,0x01,
+ 0xe8,0x58,0xe5,0x07,0x01,0xe5,0x03,0x02,0x01,0x01,0x07,0x04,0x04,0x04,0x04,0x04,
+ 0x06,0x01,0x25,0x01,0x03,0xe5,0x06,0x08,0xe8,0x04,0xe5,0xe5,0x06,0xe7,0x05,0xe7,
+ 0x05,0xe7,0x05,0x01,0x02,0x09,0x11,0x01,0xe5,0x44,0xe5,0x07,0xe5,0x09,0x2f,0xe5,
+ 0x07,0x02,0x0c,0x09,0x05,0x03,0x05,0x09,0x06,0x09,0x09,0x04,0x04,0x09,0x09,0x09,
+ 0x04,0x1c,0x02,0xe5,0x45,0x0f,0x0a,0x13,0x16,0xe5,0x07,0xe5,0x06,0x15,0xe5,0x07,
+ 0xe5,0x03,0x03,0xe5,0x04,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x06,0xe6,0x1e,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x03,0x02,0x02,
+ 0x06,0x02,0xe5,0x04,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x02,0x06,0x09,0x06,0x02,
+ 0x06,0x04,0x06,0x02,0x04,0x01,0xe5,0xe5,0x06,0x01,0x06,0x02,0x09,0xe6,0x06,0xe5,
+ 0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0x04,0x01,0x02,0x02,0x0a,
+ 0xe7,0xe5,0x01,0x3b,0x06,0x02,0x06,0x0b,0xe5,0x08,0x09,0x1c,0x09,0x09,0x0c,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x02,0x11,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x09,0x0e,0x03,
+ 0xe5,0xe5,0x3b,0x09,0x14,0x05,0x01,0x0b,0x05,0x35,0x06,0x04,0x04,0x1e,0x09,0x29,
+ 0x09,0x18,0x49,0x01,0x0a,0x0b,0x06,0x02,0x01,0x01,0x02,0x02,0x06,0x02,0x04,0x01,
+ 0x02,0x06,0x02,0x06,0x01,0x09,0x22,0x04,0xe7,0x06,0xe6,0xe5,0x04,0xe6,0x06,0xe6,
+ 0xe5,0x03,0xe7,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x03,0x09,0x0c,0x01,0xe6,0xe5,
+ 0x41,0x06,0x01,0xe5,0x08,0x09,0xe5,0x04,0x03,0x04,0xe5,0x01,0xe5,0x06,0x01,0x05,
+ 0x01,0x01,0x05,0x03,0x07,0x01,0xe6,0xe5,0x02,0x02,0xe5,0x08,0x02,0x06,0x09,0x02,
+ 0x04,0xe6,0x08,0x09,0x09,0x02,0x04,0xe6,0x01,0x06,0x09,0x05,0x02,0x06,0x02,0x11,
+ 0x3e,0xe5,0x08,0x10,0x01,0x0c,0x09,0x09,0x0d,0x0f,0x01,0x06,0x02,0x07,0x05,0x03,
+ 0x15,0x03,0x06,0x02,0xe5,0x05,0x01,0xe5,0x07,0x05,0xe5,0x01,0xe5,0x04,0x02,0xe5,
+ 0x05,0x01,0x05,0x09,0x10,0xe6,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe6,0xe5,0x03,0xe6,0x07,0xe5,0x07,0xe6,0x04,0xe5,0xe6,0x06,0xe5,0x01,
+ 0x03,0xe5,0xe5,0x05,0xe5,0xe5,0x06,0xe6,0x01,0x01,0x05,0xe6,0x06,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x05,0xe7,0x01,0xe5,0x01,0xe7,0x05,0xe7,0x05,0xe7,0x02,0x02,0xe7,0x01,
+ 0x03,0xe7,0x05,0xe7,0x05,0xe8,0x04,0xe8,0x04,0xe7,0x06,0x01,0x01,0x42,0x06,0x01,
+ 0x04,0x01,0xe5,0xe5,0x08,0xe5,0x0f,0x01,0xe5,0x1b,0x0b,0x07,0x01,0x07,0x09,0x09,
+ 0x02,0xe5,0xe5,0x04,0xe5,0x08,0xe5,0x07,0x09,0xe5,0x06,0xe6,0x07,0xe5,0x07,0x08,
+ 0xe5,0x01,0xe5,0x03,0x04,0x0a,0x02,0x42,0x06,0x01,0x09,0x07,0x08,0x06,0x02,0xe5,
+ 0xe5,0x05,0x06,0x02,0x09,0xe5,0x07,0x02,0x08,0xe5,0xe5,0x05,0x09,0x09,0x07,0x01,
+ 0x02,0xe5,0x01,0x02,0x06,0x02,0x03,0x02,0x02,0x07,0x01,0x02,0x03,0x02,0x07,0x01,
+ 0x03,0x02,0x02,0xe5,0x07,0xe5,0x07,0x08,0x01,0xe5,0x0b,0x3c,0x09,0x01,0x09,0xe5,
+ 0x03,0x08,0xe7,0xe6,0x04,0x07,0xe6,0x05,0xe7,0x06,0xe6,0xe5,0x01,0x05,0x01,0x01,
+ 0x05,0x09,0x09,0x09,0x03,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x01,0x03,0x04,0xe5,
+ 0x06,0x01,0x08,0xe5,0x02,0xe5,0x03,0x03,0x03,0x01,0x08,0xe5,0x01,0x42,0x06,0x01,
+ 0x09,0x07,0x04,0x02,0xe5,0x04,0xe5,0x02,0x01,0x02,0x01,0x07,0xe5,0x07,0x01,0x07,
+ 0x02,0x03,0x04,0x02,0xe6,0xe5,0x01,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,0x01,
+ 0xe5,0xe5,0xe7,0x01,0x02,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0x01,0xe6,
+ 0x01,0x02,0xe5,0xe6,0x04,0x01,0xe6,0x04,0xe5,0xe7,0x01,0x03,0xe7,0x05,0xe6,0x06,
+ 0xe6,0xe5,0x09,0x36,0xe5,0x03,0x04,0x26,0xe5,0x07,0xe5,0x05,0x03,0x0a,0x08,0xe5,
+ 0x08,0x06,0x09,0x01,0xe5,0x0d,0x12,0x14,0x29,0x01,0xe5,0x0f,0xe5,0xe5,0x0e,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0xe5,0x04,0xe5,0xe6,0xe5,0x02,0xe5,0xe5,0xe5,0x04,0x01,0x02,0x04,0x01,0x07,0x01,
+ 0xe5,0x02,0x04,0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x01,0xe5,0xe5,0x01,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x02,0x04,0x01,0x08,0x03,0xe6,0x39,0x08,0x05,0x15,0x06,0x04,0x07,0xe5,0x0b,
+ 0x04,0x02,0x01,0x07,0x02,0x06,0x04,0x02,0x29,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe6,
+ 0x06,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x06,0x0f,0xe5,0x01,0xe5,0x4b,0x02,0x12,
+ 0x0e,0x0e,0x0b,0x0a,0x01,0x04,0x09,0x27,0x32,0x28,0xe5,0xe5,0xe5,0x41,0x0b,0x0d,
+ 0x02,0x06,0x0c,0x03,0x1a,0x01,0x04,0x03,0x03,0x13,0x17,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x05,0x01,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x18,0x02,0xe5,0x0a,0x33,
+ 0x01,0x01,0x0f,0x01,0x04,0x02,0x01,0x07,0x01,0x06,0xe5,0xe5,0xe5,0x04,0xe6,0x03,
+ 0x02,0x01,0x04,0xe5,0x0b,0x02,0x09,0xe5,0x07,0x09,0x07,0x05,0xe5,0x2c,0x04,0x30,
+ 0x03,0x02,0x27,0x14,0x02,0x11,0x01,0x07,0x01,0x09,0x02,0x03,0x02,0x02,0x0b,0x04,
+ 0x03,0x08,0x03,0x01,0x07,0x01,0x09,0x03,0x04,0xe5,0x04,0x05,0x35,0x32,0xe6,0xe5,
+ 0x2d,0x1c,0x0a,0x03,0x0c,0x0a,0xe5,0x03,0x02,0x02,0x06,0xe6,0x0e,0x01,0x02,0xe5,
+ 0x2a,0x06,0x13,0x2a,0x0b,0x14,0xe6,0x25,0x04,0x13,0x04,0x04,0xe5,0x05,0x10,0x04,
+ 0x01,0x03,0xe6,0xe5,0x03,0x0e,0x04,0x0e,0x01,0x01,0xe5,0x01,0x2f,0x60,0x2b,0x13,
+ 0x0b,0x0e,0x16,0x0d,0x05,0x06,0x06,0x02,0x02,0x39,0x5a,0x03,0x4e,0x05,0x02,0x05,
+ 0xe5,0x08,0x07,0x01,0x07,0xe6,0x02,0x03,0x01,0x07,0x0a,0x16,0x1c,0xe5,0x07,0x02,
+ 0x03,0x02,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x01,0x02,0x02,0xe5,0x04,0x02,0x09,0xe6,
+ 0x06,0xe6,0x0e,0x02,0x46,0x0e,0x07,0xe5,0x09,0x09,0x07,0xe5,0x0a,0x0c,0x01,0x01,
+ 0x06,0x03,0x0c,0x1b,0xe5,0x07,0x09,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x02,
+ 0x04,0x04,0x06,0x08,0x0f,0x02,0xe5,0x25,0x06,0x07,0x01,0x07,0x01,0x09,0x15,0x03,
+ 0xe5,0x0b,0xe5,0x07,0x0c,0xe6,0x06,0x08,0x03,0x19,0x1f,0x13,0x09,0x13,0x09,0x19,
+ 0xe6,0x07,0x22,0x0a,0x02,0x06,0x02,0x06,0x0c,0x07,0x01,0x02,0x01,0x01,0x02,0x05,
+ 0x0a,0x06,0x0d,0x01,0x01,0x05,0x0d,0x0f,0x0f,0x62,0x01,0x01,0xe5,0x2f,0x06,0x02,
+ 0x06,0x01,0x05,0xe5,0x03,0x2b,0xe5,0x01,0x16,0x03,0x04,0x13,0x09,0x04,0x18,0x0b,
+ 0x07,0x01,0x13,0x07,0x01,0x1e,0xe5,0x01,0x01,0x1f,0x09,0x13,0x09,0x06,0xe5,0x04,
+ 0x02,0x01,0x04,0x09,0x05,0x02,0xe5,0x08,0x09,0x02,0x01,0x0c,0x02,0xe5,0x01,0xe5,
+ 0x04,0x01,0xe5,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x04,
+ 0x09,0x0a,0xe8,0xe5,0x01,0x01,0x1d,0xe5,0x06,0xe5,0x11,0xe6,0x06,0xe5,0x04,0xe5,
+ 0x07,0xe5,0x07,0x01,0x0a,0x01,0xe5,0x02,0x01,0x04,0x08,0x02,0xe5,0x06,0x06,0x03,
+ 0xe7,0x05,0x09,0x09,0x02,0xe5,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x07,0x01,0x02,0xe5,0x01,0x04,0x19,0x01,0xe5,0x03,0x04,0x01,
+ 0x0d,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x0b,0x09,0x08,0xe5,0x01,0xe5,0xe5,0xe5,
+ 0x03,0xe5,0xe5,0xe5,0x10,0x01,0x04,0xe5,0x02,0x8d,0x04,0x01,0x01,0xe5,0xe5,0x1d,
+ 0x01,0x04,0xe5,0xe5,0xe5,0x0d,0x02,0x06,0x02,0x01,0x1c,0x02,0x02,0xe5,0xe5,0xe5,
+ 0x03,0x02,0x01,0x0e,0x02,0x01,0x09,0x8f,0x02,0x03,0xe5,0x03,0x1b,0x01,0x06,0xe5,
+ 0xe5,0x0e,0x01,0x01,0x04,0xe7,0xe5,0x02,0x02,0x05,0x09,0x04,0x02,0x06,0x01,0x03,
+ 0x01,0xe5,0x04,0x04,0x07,0xe5,0x0b,0x06,0x01,0x05,0x09,0x13,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x0c,0xe8,0xe5,0x1f,0x01,0x03,0x01,0x01,0x04,0x01,0x0a,
+ 0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0x18,0x02,0x06,0x01,0x01,0x09,0x07,0x05,0x05,
+ 0x07,0x01,0x01,0x02,0x01,0x86,0x05,0xe6,0x1f,0x09,0x01,0x11,0x01,0x07,0x01,0x0b,
+ 0x09,0x02,0x02,0x02,0x06,0x01,0x07,0x01,0x07,0x09,0x01,0x09,0x06,0x1d,0x06,0x09,
+ 0x27,0x13,0x13,0x0b,0x02,0x01,0xe5,0x1f,0x01,0x07,0x01,0x11,0x01,0x07,0x01,0x0c,
+ 0x09,0x02,0x01,0x02,0x06,0x01,0x07,0x01,0x01,0xe5,0x05,0x02,0x04,0x01,0x09,0x05,
+ 0xe6,0x04,0xe5,0x07,0xe5,0x08,0x01,0xe6,0x04,0x01,0x01,0x05,0xe6,0x05,0xe7,0x05,
+ 0xe7,0x05,0xe7,0x06,0xe6,0x05,0xe7,0x06,0xe6,0x05,0xe5,0x08,0x08,0xe5,0xe5,0xe5,
+ 0xe5,0x26,0x13,0x02,0x06,0x02,0x17,0x16,0xe5,0x04,0x0c,0x1c,0x09,0x0c,0xe5,0x04,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x11,0x28,0x01,0x04,0x02,0x09,0x23,
+ 0xe5,0x08,0x12,0xe5,0x08,0x02,0x01,0x07,0xe5,0x0f,0xe5,0x07,0xe5,0x08,0x02,0x05,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x0b,0xe5,0x01,0xe5,0x0d,0x09,0x09,0x04,0xe6,0x01,0xe6,0x02,0x03,
+ 0x03,0x05,0x02,0x06,0x02,0x06,0x09,0xe6,0x06,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,
+ 0x05,0x04,0xe6,0x01,0x06,0x04,0x06,0x02,0xe5,0x07,0xe5,0x04,0x02,0x03,0x05,0xe6,
+ 0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe5,
+ 0x07,0xe6,0x0a,0xe7,0xe5,0x01,0x1d,0x13,0x13,0x3b,0x09,0x08,0xe5,0x07,0x15,0xe5,
+ 0x71,0x02,0xe5,0x01,0x1d,0x15,0x13,0x37,0x03,0x09,0x07,0x13,0x09,0x03,0x05,0x1d,
+ 0x09,0x09,0x13,0x13,0x17,0xe7,0x20,0x01,0x04,0x04,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x14,0xe6,0x03,0x01,0xe7,0x02,0xe5,0xe5,0x08,0xe7,0xe5,0x06,0x01,0x0e,0x08,0x02,
+ 0xe7,0x06,0xe6,0x03,0x04,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,
+ 0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x08,0x01,0xe6,0xe5,0x20,0x01,0xe5,
+ 0x05,0x01,0xe6,0x04,0x02,0x06,0x01,0xe5,0x05,0x02,0x0a,0x09,0x02,0x02,0x02,0xe5,
+ 0xe5,0x02,0x01,0xe5,0x07,0xe6,0x08,0x01,0x06,0xe5,0x08,0xe5,0x05,0x02,0xe5,0x08,
+ 0x04,0x02,0xe6,0x08,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe7,0x20,
+ 0x0b,0x09,0x07,0x09,0x01,0x0d,0x06,0x06,0x01,0xe5,0x05,0x01,0x09,0x09,0x06,0x0c,
+ 0x0b,0xe5,0x26,0x0a,0x09,0x08,0x09,0x09,0x09,0x13,0x0d,0xe5,0x01,0x15,0xe5,0x07,
+ 0xe5,0x01,0x05,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x05,0xe8,
+ 0x06,0xe6,0xe5,0x04,0xe5,0x01,0xe5,0x01,0x01,0xe6,0x06,0xe5,0x07,0xe5,0x03,0x03,
+ 0xe8,0x04,0xe7,0x02,0x02,0xe7,0x01,0x03,0xe7,0x02,0x02,0xe7,0x05,0xe7,0x05,0xe7,
+ 0x05,0xe7,0x05,0xe7,0x05,0xe7,0x05,0xe7,0x05,0xe7,0x02,0x02,0xe7,0x05,0xe7,0x06,
+ 0x01,0xe6,0x20,0x01,0x09,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0x09,0xe5,0x04,0x01,
+ 0x07,0x01,0x09,0xe5,0x01,0x01,0x0d,0x0c,0xe5,0x06,0x0a,0x09,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0x09,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x1a,0xe5,0x20,0x01,
+ 0x09,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0x0c,0x02,0xe5,0x08,0x01,0x09,0xe5,0x0f,
+ 0x0d,0x04,0x01,0xe5,0x04,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,
+ 0x06,0x02,0x07,0xe6,0xe5,0x20,0x15,0x07,0x01,0x07,0x01,0x18,0xe5,0xe5,0xe5,0x08,
+ 0x05,0x03,0x05,0x03,0x0f,0x02,0x06,0x01,0x03,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe8,0x22,0x0c,0x04,0x01,0x07,0x01,0x07,0x01,0x0c,0x09,0xe5,
+ 0xe7,0x03,0x04,0x01,0x03,0x01,0x03,0x02,0x04,0x04,0x07,0x01,0x02,0x05,0xe5,0x02,
+ 0xe7,0x03,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,
+ 0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x04,
+ 0xe5,0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe6,0x06,0x03,0x21,0x09,0x02,0x04,0x0b,0x02,
+ 0x1e,0x05,0x35,0xe5,0x09,0x09,0x09,0x73,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x04,0x02,
+ 0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,
+ 0x04,0x01,0x06,0xe5,0xe5,0x06,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x04,0x04,0x01,
+ 0x02,0x04,0xe6,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0x02,0xe5,0x03,
+ 0x26,0x01,0x11,0xe5,0x26,0xe6,0x04,0x07,0x04,0xe5,0x02,0x06,0x01,0x0c,0x04,0x09,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0c,0xe5,0x01,0xe5,0x1d,0x08,0x04,
+ 0x06,0x0e,0x08,0x01,0x0c,0x0c,0xe5,0x09,0x08,0x01,0x02,0x0a,0x11,0x01,0x01,0x03,
+ 0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x04,0x24,
+ 0x13,0xe5,0x08,0x37,0x02,0x0f,0x03,0x01,0x01,0x01,0xe5,0x01,0x08,0x05,0x03,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x10,0xe8,0x2a,0x01,0x06,0xe5,
+ 0x01,0x0c,0x05,0x0a,0x03,0x06,0x0f,0x01,0x0f,0x08,0x0d,0xe5,0xe6,0x03,0x15,0x74,
+ 0xe5,0xe6,0x28,0x04,0x09,0x04,0x0c,0x23,0x02,0x01,0x25,0x04,0x0a,0x01,0x0a,0xe5,
+ 0x03,0x71,0xe8,0x17,0xe5,0x0d,0x02,0x05,0x01,0x21,0x0a,0x0c,0x05,0x02,0x01,0x0d,
+ 0xe5,0xe5,0x06,0x07,0x01,0x0d,0x07,0x09,0x16,0x5b,0x01,0xe6,0x1b,0x09,0x04,0x01,
+ 0x25,0xe5,0x07,0x01,0x01,0x0f,0x01,0x0e,0xe5,0xe5,0x01,0x06,0x01,0xe5,0x02,0x02,
+ 0xe6,0x05,0x02,0x0a,0x04,0x03,0x04,0x6f,0xe6,0xe5,0x25,0x2c,0x1a,0x05,0x0e,0x01,
+ 0x04,0x07,0xe5,0x04,0x03,0x09,0x0b,0x04,0xe5,0x01,0x71,0x01,0xe6,0x2f,0x11,0x04,
+ 0x05,0x05,0x01,0x12,0x07,0x04,0x04,0x07,0x01,0x06,0xe5,0xe5,0x04,0x01,0x01,0xe5,
+ 0x06,0x02,0x06,0x02,0xe7,0x04,0x76,0x03,0x25,0x09,0x09,0x0c,0x13,0x0d,0x02,0x14,
+ 0x12,0xe5,0x03,0xe5,0x16,0x7e,0xe5,0x2c,0x25,0x01,0x01,0x03,0x01,0x01,0x13,0x04,
+ 0x06,0x04,0x02,0x09,0x1a,0x0a,0x7a,0xe5,0x1f,0x01,0x02,0x06,0x01,0x07,0x0b,0x0a,
+ 0x0b,0x13,0x02,0x01,0x02,0x0f,0x02,0xe5,0xe5,0x01,0x01,0x15,0x13,0x0e,0x13,0x4e,
+ 0x01,0x02,0x2a,0xe6,0x09,0x0c,0x1f,0x0c,0x0d,0x0f,0x17,0x04,0x0d,0x05,0x6b,0x05,
+ 0xe6,0x32,0x24,0xe5,0x04,0x01,0xe5,0x05,0x14,0x04,0x0d,0x0b,0xe5,0x0d,0x03,0xe5,
+ 0x06,0xe5,0x6d,0x01,0xe5,0x01,0x02,0x01,0x1c,0x0b,0x08,0xe5,0x0b,0x13,0xe6,0x05,
+ 0x02,0x01,0x03,0x06,0xe5,0x1b,0xe5,0x01,0x0b,0x05,0xe5,0x07,0xe5,0xe5,0x09,0x6b,
+ 0x02,0x01,0xe5,0x01,0x04,0x18,0xe5,0x01,0x01,0x0e,0xe5,0x06,0xe5,0x01,0x1a,0xe5,
+ 0xe5,0x14,0x0e,0x01,0xe5,0xe5,0x08,0x15,0x04,0xe5,0xe5,0xe5,0x01,0x6e,0xe5,0x03,
+ 0x04,0x01,0xe6,0x01,0x11,0xe5,0x07,0xe5,0x02,0x04,0x09,0x02,0x06,0x34,0x13,0x01,
+ 0x07,0x15,0x06,0x02,0x01,0x71,0xe5,0x05,0x02,0x03,0x29,0xe5,0x07,0x01,0x01,0x05,
+ 0x08,0x01,0x0a,0x08,0xe5,0xe5,0x01,0x01,0x01,0x13,0x05,0x0a,0x02,0x0c,0x04,0x0b,
+ 0xe7,0xe5,0x02,0x02,0x02,0x06,0x6a,0x03,0xe5,0x01,0x18,0x04,0xe5,0x02,0x03,0x03,
+ 0x01,0x04,0x02,0x01,0x04,0x04,0x02,0x01,0x0e,0x01,0x01,0xe6,0xe5,0xe5,0x01,0x01,
+ 0x11,0xe6,0x0d,0x0c,0x01,0x04,0x02,0x03,0x07,0x01,0xe5,0xe5,0xe5,0x01,0x01,0xe5,
+ 0x06,0x6a,0x03,0x01,0xe5,0x1d,0x01,0x01,0x07,0x07,0x09,0x01,0x13,0x09,0x01,0x01,
+ 0x16,0x06,0x02,0x01,0xe5,0xe5,0x12,0x07,0x08,0x02,0x01,0x02,0x06,0x73,0xe7,0x16,
+ 0x0b,0x09,0x07,0x27,0x01,0x02,0x13,0x02,0x0b,0x01,0x0c,0x08,0x02,0x09,0x02,0x01,
+ 0x01,0x02,0x01,0x01,0xe5,0x73,0x02,0xe5,0x1c,0x02,0x06,0x09,0x02,0x06,0x02,0x06,
+ 0xe5,0x1b,0xe5,0x18,0x22,0x02,0x10,0x09,0x6d,0xe6,0xe6,0x1d,0xe5,0x07,0x01,0x07,
+ 0x13,0x1a,0xe5,0xe5,0x05,0x09,0x08,0xe5,0x12,0x0e,0xe5,0x04,0x09,0x04,0x04,0x02,
+ 0x01,0x6f,0xe5,0x0d,0x04,0x01,0x02,0x02,0x03,0x02,0x02,0x01,0xe6,0x01,0x05,0x03,
+ 0x04,0x01,0x02,0x02,0xe5,0x04,0x09,0x06,0x02,0x03,0x05,0x09,0x09,0xe6,0x06,0x06,
+ 0x02,0x0b,0x09,0x09,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x06,0x06,0xe5,0x02,0x02,0x13,0x06,0x02,0x09,0x13,0x13,0x08,0xe5,0x03,0x2b,0xe5,
+ 0x23,0x71,0x08,0xe8,0x12,0x0a,0x0a,0x12,0x14,0x07,0x07,0x09,0x21,0x25,0x7a,0xe6,
+ 0xe5,0xe5,0x16,0x07,0x01,0x09,0x07,0x1d,0x01,0x0c,0x09,0x04,0x04,0x07,0xe5,0x04,
+ 0x0e,0x0b,0x09,0x04,0x01,0x02,0x09,0x4a,0x01,0x25,0xe5,0x16,0x02,0x06,0x01,0xe5,
+ 0x08,0x08,0xe5,0x08,0x10,0x02,0x09,0xe5,0x08,0x05,0x03,0x01,0x07,0x05,0x02,0x06,
+ 0x03,0x01,0xe5,0x07,0x02,0x02,0x03,0x01,0x03,0x01,0x01,0x02,0x05,0xe5,0xe5,0x48,
+ 0x01,0xe5,0x20,0x01,0xe6,0x22,0x11,0x1d,0x01,0x09,0x04,0x09,0x02,0x05,0xe5,0x05,
+ 0x02,0x02,0x06,0x09,0x04,0x01,0x04,0x0c,0x01,0x03,0xe5,0x03,0x4d,0x01,0x22,0xe8,
+ 0x14,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,
+ 0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe5,0x01,0x01,0x05,
+ 0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,
+ 0xe6,0x18,0x07,0x01,0x11,0x1d,0x01,0xe5,0x26,0x09,0xe5,0x24,0x01,0xe6,0x79,0x02,
+ 0xe5,0x16,0x09,0x01,0x13,0x1b,0x02,0x38,0x15,0x09,0x01,0x80,0x19,0x09,0x11,0x09,
+ 0x13,0x01,0x09,0x1e,0x1b,0x20,0x74,0x01,0x17,0x09,0x15,0x09,0x11,0x02,0x0b,0x09,
+ 0x09,0x09,0x07,0x06,0x04,0x0b,0x04,0x04,0x09,0x06,0x02,0x6f,0xe6,0xe5,0x19,0xe5,
+ 0x04,0x09,0x02,0x07,0x01,0x06,0x13,0x01,0xe5,0xe5,0x03,0xe5,0xe5,0x20,0x02,0x01,
+ 0xe5,0x09,0x1d,0xe6,0x02,0x06,0x15,0x32,0x1c,0x09,0x03,0x01,0x0f,0x01,0x07,0x01,
+ 0x01,0xe5,0xe5,0x01,0x01,0x04,0x02,0x01,0x01,0xe5,0x03,0x01,0x03,0x03,0x01,0x07,
+ 0x01,0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x01,0x03,
+ 0x01,0xe6,0x04,0x01,0xe5,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x0b,0xe7,0x16,0x13,0x12,0x12,0x02,0x02,0x07,0x15,0x1b,0xe6,0x03,
+ 0x04,0xe5,0x04,0x09,0x0c,0xe5,0x66,0x09,0x01,0x01,0xe5,0x13,0x05,0x16,0x13,0x09,
+ 0x0e,0x0f,0x09,0x09,0x0c,0xe5,0x03,0x05,0xe5,0x0d,0x05,0x06,0x01,0x0e,0x42,0x1f,
+ 0x03,0xe5,0x33,0x04,0x1f,0x2e,0x0b,0x04,0xe5,0x16,0x17,0x10,0x03,0xe5,0x4c,0xe6,
+ 0xe5,0x18,0xe5,0x07,0x04,0x0a,0x01,0x07,0x01,0x01,0x31,0x0d,0x03,0x01,0x10,0x02,
+ 0x01,0x11,0x01,0x01,0x04,0x03,0xe5,0x0b,0x13,0x2a,0xe6,0x20,0xe5,0xe7,0x16,0x0a,
+ 0x04,0x10,0x08,0x15,0x03,0x2a,0xe5,0x02,0x02,0x05,0x04,0x01,0x02,0x10,0x02,0x05,
+ 0x75,0x01,0x01,0x2d,0x09,0x07,0x16,0x1a,0x0b,0x04,0x09,0x0c,0x16,0xe5,0x07,0xe5,
+ 0x01,0x06,0x2a,0x18,0x05,0x0c,0x04,0x0b,0xe5,0x02,0x0d,0x0c,0x11,0x09,0x0c,0x19,
+ 0x0c,0x10,0xe5,0x07,0x06,0x0c,0x07,0x17,0x09,0xe5,0x0b,0x08,0x53,0x02,0xe5,0x04,
+ 0x09,0x4f,0x04,0x14,0x03,0x09,0x02,0x0e,0x05,0x0b,0x08,0x04,0x09,0x6d,0xe5,0x04,
+ 0x07,0xe6,0x07,0x09,0x02,0x13,0x09,0x03,0x01,0x0f,0x07,0x10,0x09,0x03,0x03,0x06,
+ 0x02,0x01,0x07,0xe6,0x02,0x02,0x02,0x09,0x0e,0x68,0x03,0x03,0x03,0x05,0x0a,0x08,
+ 0x09,0x06,0x04,0xe5,0x17,0x0d,0x1b,0x05,0x03,0x0b,0x08,0x01,0x04,0x13,0x08,0x01,
+ 0x75,0x03,0x0b,0x06,0x04,0x01,0x13,0x06,0x02,0x04,0x05,0x0a,0x0e,0xe5,0xe5,0x23,
+ 0x18,0x13,0x07,0x01,0x07,0x01,0x05,0x01,0x01,0x39,0x01,0x23,0xe8,0x0d,0x09,0x02,
+ 0x0f,0xe5,0x07,0xe5,0x0b,0x1a,0xe7,0x01,0x06,0x09,0x01,0x0e,0x09,0x01,0x09,0x12,
+ 0x03,0x1a,0x03,0x35,0x01,0x10,0x07,0xe5,0x08,0x01,0xe5,0x0e,0x09,0x12,0x09,0x05,
+ 0x1a,0x07,0x26,0x0a,0x09,0x01,0x10,0x04,0x0c,0x0d,0x62,0xe7,0x18,0x09,0xe5,0x03,
+ 0x0f,0xe5,0x04,0xe5,0x15,0xe5,0x04,0x01,0xe5,0x08,0xe5,0x04,0x02,0x01,0x04,0x02,
+ 0xe5,0xe5,0x02,0x09,0x0b,0x13,0x19,0x03,0x13,0x46,0x01,0x02,0xe5,0x01,0x01,0x08,
+ 0x0c,0x06,0x02,0x06,0xe5,0x07,0xe5,0x04,0x01,0x1b,0xe5,0x07,0x01,0x07,0x01,0x03,
+ 0x03,0x01,0x03,0x02,0xe5,0x01,0xe5,0x01,0x05,0xe5,0xe5,0x0b,0x02,0x01,0x0a,0x02,
+ 0x06,0xe5,0x0e,0xe5,0xe7,0x14,0x43,0x02,0x01,0x01,0xe6,0x03,0x05,0xe5,0x14,0x09,
+ 0x01,0x03,0xe5,0x03,0x0b,0x16,0xe5,0xe5,0x02,0x1f,0xe5,0x03,0x02,0x06,0x1a,0xe5,
+ 0x07,0x01,0x02,0x04,0xe5,0x02,0x04,0x01,0x04,0x51,0xe5,0x03,0x04,0xe8,0x01,0x07,
+ 0xe5,0x01,0x0f,0x02,0x09,0x09,0x4b,0xe5,0x01,0x09,0x1c,0xe5,0xe5,0x05,0x02,0x05,
+ 0xe5,0x01,0x01,0x04,0xe5,0x07,0x04,0x49,0xe5,0x05,0x02,0xe5,0xe6,0x0e,0xe5,0x0d,
+ 0x06,0x01,0x01,0xe5,0xe5,0x08,0x04,0x01,0x1e,0x01,0x04,0x01,0x05,0x09,0x04,0x01,
+ 0x02,0x04,0x01,0x06,0x02,0x04,0x01,0x1e,0x01,0x01,0x03,0x02,0xe5,0xe5,0x06,0x01,
+ 0x05,0x04,0x52,0xe9,0x01,0x0a,0x02,0xe5,0x03,0x0a,0x04,0xe5,0x01,0x04,0x04,0xe5,
+ 0x02,0x23,0x01,0x01,0x02,0x01,0x14,0x01,0x01,0x05,0x01,0x01,0x02,0xe7,0x02,0x01,
+ 0x02,0x16,0x03,0x01,0x02,0xe5,0x02,0x04,0xe5,0xe5,0xe5,0x01,0x01,0xe5,0xe5,0x0f,
+ 0x4b,0x03,0xe7,0x12,0xe5,0x0a,0x09,0x01,0x05,0x01,0x01,0x25,0x01,0x02,0x08,0x0c,
+ 0x01,0xe5,0xe5,0xe5,0x04,0x01,0x09,0x04,0x0b,0x01,0x0a,0x01,0x07,0x01,0x04,0xe7,
+ 0xe5,0x18,0x50,0x01,0x13,0xe6,0x05,0xe6,0x01,0x04,0x36,0x01,0x02,0x09,0xe6,0x05,
+ 0xe7,0x01,0x01,0x02,0x04,0x01,0x07,0x04,0x01,0xe6,0x06,0x01,0x08,0xe5,0x01,0x01,
+ 0x02,0x04,0x01,0x04,0x01,0xe5,0xe5,0x6a,0xe5,0x0f,0x02,0x09,0x02,0x10,0x02,0x2e,
+ 0xe5,0x0e,0x09,0x0c,0x02,0x14,0x11,0x09,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x4c,
+ 0xe9,0x13,0x01,0x07,0xe5,0x07,0x09,0xe5,0x07,0xe5,0x25,0x0f,0xe6,0x06,0xe6,0x07,
+ 0x02,0x06,0x0b,0xe5,0x07,0x0c,0x01,0x04,0x02,0xe5,0x07,0x06,0x02,0xe5,0x58,0xe8,
+ 0x08,0x01,0x02,0x02,0x02,0x03,0x06,0x02,0x04,0xe6,0x01,0x02,0x06,0x09,0x09,0x09,
+ 0x06,0x02,0x03,0x05,0x09,0xe5,0x07,0xe6,0x03,0x02,0x03,0x02,0x02,0x06,0x04,0x09,
+ 0x09,0x03,0x05,0x06,0x02,0x02,0xe5,0x04,0x06,0x02,0x06,0x02,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x06,0x06,0xe9,0x01,0x09,0x09,0x08,0xe5,0x12,0x26,0xe5,0x17,0x09,0x03,
+ 0x09,0xe5,0x05,0x02,0x1f,0x06,0x02,0x12,0xe5,0x07,0x45,0x08,0x01,0x01,0x0b,0x09,
+ 0x09,0x11,0x27,0x1b,0x13,0x03,0x05,0x03,0x07,0x09,0x0d,0x05,0x02,0x14,0x5c,0x01,
+ 0x0e,0xe5,0x01,0x02,0x01,0x0c,0x03,0x02,0x07,0x27,0x01,0x14,0xe6,0x06,0x01,0x04,
+ 0x01,0x02,0x06,0x02,0x08,0x02,0x09,0x06,0x04,0x04,0x02,0x03,0xe5,0x08,0x01,0x02,
+ 0x07,0x03,0x07,0x24,0x23,0xe7,0x0c,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x01,0x08,
+ 0x05,0x03,0x23,0xe5,0xe7,0x08,0x09,0x09,0x05,0x01,0xe6,0x04,0x03,0x02,0x08,0x02,
+ 0x06,0x07,0xe6,0x01,0x01,0xe5,0xe7,0x04,0x02,0x03,0x04,0xe6,0xe5,0x01,0x0e,0x25,
+ 0xe5,0x1d,0x02,0xe8,0x0e,0x01,0x07,0x04,0x08,0x03,0x01,0x18,0x16,0x10,0x06,0x01,
+ 0x09,0x03,0x01,0x04,0x04,0x03,0x07,0x03,0xe5,0x0a,0x0c,0x07,0x0b,0x06,0x34,0x22,
+ 0xe5,0x01,0x0f,0x05,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x05,0xe7,0x06,0xe6,0x05,0x01,0xe6,0xe5,
+ 0x02,0x01,0xe6,0x05,0xe6,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x03,0x02,
+ 0x08,0xe5,0x07,0xe5,0x06,0x01,0x01,0x0f,0x09,0xe6,0x1a,0x14,0x10,0x01,0x10,0x09,
+ 0x06,0x02,0xe5,0xe5,0x05,0x02,0xe6,0x03,0x04,0xe6,0x1a,0xe5,0x05,0x0b,0x09,0x07,
+ 0x29,0x03,0x1c,0x01,0xe6,0xe5,0x0e,0x09,0x07,0x01,0x09,0x09,0x14,0x10,0x01,0x0f,
+ 0xe5,0x08,0x08,0xe6,0xe5,0x04,0xe6,0xe5,0x05,0x20,0x01,0x13,0x07,0x0b,0x27,0x22,
+ 0x03,0x0f,0x09,0x11,0x31,0x0f,0xe6,0x07,0x0a,0x03,0x03,0x01,0x03,0x04,0x03,0x02,
+ 0x1d,0xe5,0x05,0x0b,0x11,0x29,0x05,0x1c,0x01,0x01,0x0f,0x09,0xe5,0xe5,0x08,0x06,
+ 0x1e,0x10,0x01,0x02,0x09,0xe5,0x07,0x01,0x07,0x04,0x01,0x02,0x01,0x02,0x01,0x02,
+ 0x01,0x09,0x09,0x09,0x06,0x02,0x10,0x02,0x10,0x02,0x24,0x03,0x1f,0x02,0x0d,0x02,
+ 0x0a,0x05,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x02,0x24,0x02,0x1e,0x05,0x02,0x21,
+ 0x04,0x0a,0x01,0x06,0x01,0xe5,0x02,0x0c,0x01,0xe5,0x09,0x0a,0x3e,0xe7,0xe5,0x06,
+ 0x03,0x03,0x01,0x07,0x01,0xe5,0x02,0x02,0xe6,0x03,0x02,0x01,0x07,0x01,0x02,0x04,
+ 0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0xe5,
+ 0x02,0x02,0x01,0x07,0x01,0x04,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x03,0x03,
+ 0x01,0x06,0xe5,0xe5,0x03,0x02,0x01,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe5,0x01,0x0d,0x17,0x04,0x05,0x04,0xe5,0x25,
+ 0xe5,0x1d,0x01,0x05,0x01,0xe5,0x14,0x03,0xe5,0x0b,0x0a,0x20,0x06,0x01,0x44,0x06,
+ 0xe6,0x1e,0x13,0x05,0x1f,0x05,0x0c,0x09,0xe5,0x14,0x06,0x05,0x05,0x0a,0x13,0x14,
+ 0x07,0x09,0x45,0x03,0xe5,0x14,0x1a,0x25,0xe5,0x24,0x07,0x01,0xe5,0x04,0x09,0xe5,
+ 0x10,0x0e,0x27,0x4c,0x01,0xe5,0x0c,0x09,0x01,0x05,0x03,0x01,0x01,0x03,0x01,0x01,
+ 0xe5,0x05,0x01,0x21,0x0e,0x09,0x09,0x10,0x01,0x11,0x05,0x05,0x05,0xe5,0x0b,0x01,
+ 0x07,0x01,0x07,0x01,0x09,0x49,0x01,0x01,0xe5,0x0a,0x04,0x06,0x02,0xe5,0x02,0x01,
+ 0x05,0xe5,0x03,0x02,0x3e,0x20,0x01,0x04,0x01,0x09,0x05,0x07,0x04,0x08,0x05,0x08,
+ 0xe5,0x01,0x07,0x53,0xe5,0x01,0x1d,0x04,0xe5,0x06,0xe6,0x06,0xe6,0x1c,0x12,0xe5,
+ 0x14,0x11,0xe6,0x03,0xe5,0x02,0x02,0x05,0xe5,0x01,0xe5,0x16,0x0f,0x03,0x06,0x02,
+ 0xe6,0x08,0x3f,0x02,0x01,0x17,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x03,0x17,
+ 0xe6,0x0a,0x05,0x01,0x02,0x04,0x04,0x07,0x10,0xe5,0x04,0x02,0x01,0xe5,0x01,0x12,
+ 0x01,0x1b,0x02,0x08,0x04,0x01,0x07,0xe6,0x43,0x12,0x08,0x2b,0x26,0x04,0x15,0xe6,
+ 0x04,0x07,0x03,0x36,0x01,0x04,0x40,0x11,0xe5,0xe6,0x10,0x10,0x36,0x0a,0x1b,0x05,
+ 0x05,0x0c,0x0a,0x0b,0x0c,0x0e,0x03,0x06,0xe5,0x38,0x1b,0xe6,0xe5,0x08,0x13,0x04,
+ 0x0e,0x4e,0x06,0x01,0x0f,0x17,0x0f,0x0f,0x05,0xe5,0x58,0x17,0x01,0x09,0x06,0x26,
+ 0x22,0x02,0x09,0x07,0x1d,0xe5,0x19,0x01,0x05,0x05,0x07,0x09,0xe5,0x07,0x44,0xe5,
+ 0x10,0x06,0x0a,0x05,0x10,0x19,0x20,0x11,0x1e,0x09,0x02,0x10,0x05,0x14,0x02,0x4b,
+ 0x01,0xe5,0x0b,0x0b,0x08,0x08,0x13,0x16,0x20,0x2e,0x01,0x09,0x13,0x11,0x09,0xe5,
+ 0x01,0x05,0x45,0xe7,0x10,0xe5,0x05,0xe5,0x49,0x03,0x0f,0x03,0x09,0x1b,0x02,0xe5,
+ 0x08,0x02,0xe5,0x07,0x01,0x18,0x02,0xe5,0x04,0xe5,0x24,0x1d,0x01,0x02,0x01,0xe5,
+ 0x01,0x01,0x0e,0xe5,0x0b,0xe5,0x2f,0x1d,0x0b,0x0a,0x06,0x0b,0xe5,0x09,0x01,0x08,
+ 0x03,0xe5,0x07,0xe5,0x18,0x02,0x01,0x4b,0x01,0x02,0xe5,0x03,0x0f,0xe5,0xe5,0xe5,
+ 0xe5,0x06,0xe5,0x02,0x01,0x06,0xe5,0x1c,0xe5,0x02,0x11,0x03,0x0f,0x03,0x1b,0x06,
+ 0xe5,0xe5,0xe5,0x2b,0x01,0x0e,0x49,0x02,0x02,0x11,0xe5,0xe5,0x08,0xe5,0x04,0xe5,
+ 0x25,0xe5,0xe5,0x1c,0x0b,0x11,0x06,0x04,0x06,0x34,0x10,0xe5,0x02,0x3a,0x02,0x01,
+ 0x02,0xe6,0x16,0x01,0x02,0x04,0x01,0xe6,0x01,0x01,0x07,0x01,0x1e,0x13,0x01,0x09,
+ 0x02,0x01,0x01,0xe5,0xe5,0x0b,0x04,0x06,0xe6,0x01,0x04,0x01,0xe6,0x01,0x04,0x01,
+ 0x0f,0x09,0x10,0x02,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x02,0x02,0x38,
+ 0xe5,0xe5,0xe5,0x01,0x02,0x11,0x04,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x04,0x09,0x02,
+ 0x01,0x18,0x04,0x0a,0x05,0x02,0xe5,0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x02,0x02,0x0a,
+ 0x01,0x03,0x02,0x04,0x02,0x03,0xe5,0x02,0x02,0x01,0x28,0x04,0x03,0x05,0x04,0x01,
+ 0x01,0x04,0x37,0xe8,0xe6,0x1a,0x04,0x01,0x2f,0x07,0x0b,0x01,0x09,0x03,0xe5,0x01,
+ 0x01,0x0d,0xe5,0x01,0x04,0x01,0x04,0x06,0xe7,0xe5,0x15,0xe6,0x08,0x0e,0x05,0x01,
+ 0x01,0x07,0x01,0x05,0x3a,0xe6,0xe5,0x1b,0x0a,0xe5,0x01,0x09,0x1f,0x11,0x04,0x04,
+ 0x01,0x02,0x01,0x02,0x01,0x02,0x08,0xe5,0xe5,0x01,0x01,0x02,0x02,0x03,0x04,0x01,
+ 0x01,0x06,0xe5,0x06,0x08,0xe5,0x07,0xe5,0xe6,0x0f,0x09,0x04,0x01,0x21,0xe5,0x1b,
+ 0xe7,0xe5,0x23,0x16,0x02,0x17,0x16,0x02,0x08,0x07,0x02,0x03,0x04,0x13,0x02,0x10,
+ 0x06,0x09,0x04,0x0e,0x02,0x02,0x10,0x02,0x3a,0xe7,0x1d,0x09,0x13,0x1a,0x02,0x10,
+ 0xe5,0x08,0x08,0xe5,0x06,0xe6,0x07,0xe5,0xe5,0x0a,0x09,0x09,0xe6,0x02,0xe5,0x07,
+ 0xe5,0x12,0x02,0x13,0xe5,0x3b,0xe7,0x0d,0x09,0x03,0x05,0x05,0xe5,0x01,0x04,0x01,
+ 0x02,0x03,0x05,0x09,0x06,0x02,0x01,0x03,0x03,0x09,0x06,0x02,0x09,0x09,0xe5,0x07,
+ 0x05,0xe5,0x03,0x04,0xe6,0x01,0x04,0xe6,0x01,0x09,0xe5,0x04,0x02,0xe5,0x07,0x06,
+ 0x02,0x01,0x03,0x03,0x04,0x01,0x02,0x02,0x06,0x09,0x09,0x09,0x09,0x0d,0xe5,0xe5,
+ 0xe5,0x01,0x26,0x27,0xe5,0x12,0x04,0x03,0xe5,0x03,0x09,0x09,0x04,0x04,0x01,0x0e,
+ 0x09,0x12,0xe5,0x11,0xe5,0x12,0x43,0x01,0xe6,0x50,0x13,0x09,0x19,0x03,0x13,0x0a,
+ 0x10,0x03,0x05,0x0d,0x11,0x46,0x01,0x01,0x01,0x12,0x07,0x01,0x02,0x02,0x08,0x09,
+ 0x18,0x04,0xe5,0x0c,0x02,0x01,0x02,0x06,0x02,0x04,0x01,0x02,0x04,0x01,0xe5,0xe5,
+ 0xe5,0x01,0x01,0x02,0x06,0x01,0x04,0x04,0x0e,0x05,0xe6,0x03,0x02,0xe6,0x10,0xe6,
+ 0xe5,0x06,0x04,0x01,0x40,0xe5,0x01,0x14,0x06,0x05,0x01,0x06,0xe5,0x01,0x06,0x02,
+ 0x17,0x05,0xe5,0x0e,0x01,0x01,0x01,0x03,0x03,0x02,0x02,0x01,0x01,0x01,0x03,0x01,
+ 0xe6,0x04,0x01,0x01,0x01,0x05,0x01,0xe6,0x03,0x02,0xe5,0x09,0x09,0x08,0xe5,0x0e,
+ 0x01,0x01,0x09,0x05,0x01,0xe5,0x42,0x20,0x02,0x09,0x06,0xe5,0x1b,0x16,0x03,0x05,
+ 0x09,0x04,0x02,0x01,0x09,0x09,0x01,0x03,0x05,0x07,0x01,0x03,0x09,0xe5,0xe6,0x04,
+ 0x0a,0x04,0xe5,0x0e,0xe5,0xe5,0x41,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe6,0x06,
+ 0xe6,0xe5,0x04,0xe6,0x06,0xe5,0x01,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,
+ 0xe5,0x02,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,0x17,0x01,0x07,0x01,0xe5,
+ 0x11,0x3b,0x14,0xe5,0x10,0x01,0x0a,0xe5,0x11,0x06,0x01,0xe5,0x11,0x09,0x09,0x43,
+ 0xe5,0x16,0x01,0x07,0x01,0xe5,0x0f,0x3d,0x27,0x01,0x25,0x13,0x0b,0x07,0x01,0x40,
+ 0xe5,0xe6,0x18,0x1b,0x33,0x09,0x09,0x13,0x08,0x02,0x09,0x07,0x01,0x0a,0x06,0x01,
+ 0xe5,0x11,0x09,0x09,0x21,0x01,0x1c,0xe6,0xe5,0x0b,0x0c,0x02,0x07,0x12,0x20,0x0e,
+ 0x04,0x06,0x02,0x04,0x04,0x09,0x04,0x04,0x0b,0x07,0x0b,0x09,0x04,0x04,0x0e,0x04,
+ 0x06,0x02,0x04,0x25,0x1c,0xe5,0x01,0xe5,0x22,0x09,0x06,0x01,0xe5,0x19,0x13,0x02,
+ 0x06,0x01,0xe5,0x19,0x0b,0xe5,0xe5,0x08,0x04,0x29,0x02,0x06,0x02,0x06,0xe5,0xe5,
+ 0x3e,0xe6,0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0xe6,0x06,0x01,0x07,0x01,0x07,
+ 0x01,0x04,0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x04,0x02,0x01,0x07,0x01,0x02,0x03,
+ 0xe5,0xe7,0xe5,0x02,0x01,0xe5,0x02,0xe5,0x02,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe6,0xe5,0x1a,0x05,0x01,0x07,0x0a,
+ 0x11,0x0c,0xe5,0x0f,0x1f,0x02,0x02,0x0a,0x0c,0x01,0xe5,0x01,0x0f,0x06,0x03,0x05,
+ 0x07,0x02,0xe5,0xe5,0x05,0xe5,0x01,0x49,0xe5,0xe6,0x1b,0x01,0x07,0xe5,0x09,0x23,
+ 0x22,0x0d,0xe5,0x07,0x02,0xe5,0x08,0xe5,0x02,0x01,0x03,0xe5,0x0a,0x05,0x04,0x08,
+ 0x03,0x07,0x04,0x0a,0x44,0x03,0xe5,0x21,0x06,0x12,0x16,0x01,0x03,0x08,0x13,0x10,
+ 0x10,0xe5,0x1f,0x0c,0x13,0x52,0x01,0xe6,0x18,0x0f,0x03,0x0b,0x19,0x01,0x11,0xe6,
+ 0x01,0x04,0x02,0x06,0x01,0xe6,0x04,0x09,0x01,0x09,0x04,0x01,0xe5,0x02,0xe5,0x0a,
+ 0x01,0x06,0x05,0xe6,0xe5,0x02,0x0d,0xe5,0x02,0xe5,0x02,0xe6,0x04,0x3c,0xe5,0x04,
+ 0x02,0x17,0x3d,0x0c,0x05,0x06,0x04,0x01,0x04,0x01,0x03,0x02,0x03,0x06,0x01,0x01,
+ 0x03,0x01,0x03,0x07,0x05,0x0c,0x0b,0x28,0x3a,0x01,0x02,0xe7,0xe5,0x09,0x01,0x17,
+ 0x04,0x01,0x03,0x07,0x06,0x02,0x11,0x05,0x19,0x0e,0x16,0x03,0x1d,0xe5,0x06,0xe5,
+ 0x05,0x0a,0x01,0x07,0x4b,0x01,0x02,0x09,0x11,0x05,0x01,0x11,0x34,0x10,0x01,0x02,
+ 0x04,0x04,0x07,0x06,0x01,0x02,0x06,0x04,0xe5,0x05,0x06,0xe5,0x07,0x03,0x02,0x0c,
+ 0xe5,0x07,0x46,0x04,0xe6,0xe6,0x1e,0x17,0xe5,0x08,0x31,0x0b,0x06,0x11,0x01,0x02,
+ 0x08,0x0b,0x07,0x09,0x11,0x09,0x4c,0x01,0xe6,0x19,0x03,0x06,0x18,0x0a,0xe5,0x04,
+ 0x02,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x03,0x08,0x01,0xe6,0x06,0x01,
+ 0x04,0x02,0x02,0x02,0x05,0xe6,0x16,0x0d,0xe6,0x33,0x28,0x01,0xe5,0xe5,0x2e,0x04,
+ 0x17,0x09,0x05,0x03,0x09,0x09,0x02,0x0c,0x01,0x05,0x0a,0xe6,0x02,0x06,0x02,0x28,
+ 0x5e,0x01,0xe5,0x1a,0x13,0x19,0xe6,0x07,0x05,0x03,0x05,0x03,0x03,0xe6,0x02,0x06,
+ 0x17,0x0b,0x13,0x09,0x47,0x2a,0xe5,0x01,0xe5,0x19,0x07,0x02,0x03,0x09,0x07,0x0c,
+ 0x01,0x0e,0x19,0xe5,0x10,0x02,0x05,0x05,0x10,0x09,0x08,0x0a,0xe5,0x11,0x07,0x01,
+ 0x4a,0x01,0x01,0x1b,0x07,0x04,0x5e,0x0c,0x05,0xe5,0x0a,0x06,0xe6,0x12,0x07,0x0c,
+ 0x0c,0x48,0x01,0xe7,0x1b,0x01,0x2c,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x02,
+ 0x01,0xe5,0x02,0x01,0xe5,0x05,0x09,0x07,0x02,0xe5,0x01,0xe5,0x0e,0x05,0x09,0x0d,
+ 0xe5,0x03,0x13,0x3e,0x01,0x01,0x01,0x01,0x02,0x01,0x12,0xe5,0x04,0xe5,0xe5,0x17,
+ 0x10,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x08,0xe5,0x01,0xe5,0x01,0xe5,0xe5,0x01,
+ 0xe5,0x05,0x09,0x07,0xe5,0xe5,0x02,0xe5,0xe6,0x02,0xe6,0x0b,0xe5,0x07,0xe5,0x04,
+ 0xe5,0x03,0x06,0x14,0xe5,0x3d,0x02,0x01,0xe5,0x03,0x14,0x03,0xe5,0x03,0xe5,0x0c,
+ 0xe5,0x07,0x01,0x11,0x09,0x09,0x09,0xe5,0xe5,0x08,0x01,0x04,0x01,0x05,0x0b,0xe5,
+ 0x02,0x01,0x02,0x04,0x01,0x04,0xe5,0x04,0x02,0x01,0xe5,0xe5,0x06,0x01,0x0d,0xe5,
+ 0x08,0xe5,0x07,0x01,0x02,0x02,0x3d,0xe5,0x01,0x02,0x14,0x06,0x02,0xe5,0x01,0x0b,
+ 0xe5,0x01,0x15,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x09,0x02,0x01,
+ 0x04,0x13,0xe5,0x02,0x01,0x07,0x06,0xe5,0x0a,0x01,0x03,0xe5,0x01,0x01,0x0e,0xe5,
+ 0x07,0xe5,0x0a,0x01,0x3a,0x02,0x01,0x01,0xe5,0xe5,0x18,0x04,0xe6,0x02,0x05,0x0a,
+ 0x01,0x10,0x05,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,
+ 0xe6,0x01,0x03,0x01,0xe6,0xe5,0x01,0x02,0xe6,0x03,0x03,0x05,0x06,0x01,0xe5,0x05,
+ 0x01,0x02,0xe5,0x01,0x0a,0x01,0xe5,0x02,0x01,0xe5,0xe6,0x02,0x01,0x05,0x0b,0x01,
+ 0x0a,0x01,0x06,0x38,0xe6,0x01,0x02,0x14,0x03,0x01,0x02,0x03,0xe5,0xe5,0xe6,0x09,
+ 0x01,0x01,0x04,0x04,0x01,0x01,0xe5,0x01,0x02,0x09,0x09,0x09,0x08,0x05,0x01,0x01,
+ 0x02,0xe6,0x01,0x01,0x02,0xe6,0x0b,0x01,0xe5,0x01,0x02,0xe5,0x02,0x04,0x0a,0x01,
+ 0xe5,0x01,0x02,0xe5,0xe6,0x01,0x02,0x0a,0x03,0x01,0x02,0x04,0x07,0x01,0x01,0x01,
+ 0xe5,0x35,0x01,0x01,0x02,0xe5,0x17,0x1b,0x01,0x05,0x3d,0x01,0x01,0x09,0x09,0x01,
+ 0xe5,0x03,0x01,0x02,0x04,0x01,0x03,0xe6,0xe5,0xe5,0x06,0x01,0x07,0x01,0x0b,0xe7,
+ 0x17,0x3f,0x01,0x02,0x17,0x1f,0x07,0x0b,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x04,
+ 0x09,0x01,0x02,0x09,0x09,0x01,0x01,0x02,0x01,0xe5,0x05,0x03,0xe5,0x03,0x01,0x02,
+ 0x04,0x01,0xe5,0x05,0x01,0xe5,0x0a,0x01,0x0c,0x09,0x01,0x3f,0xe5,0x02,0x24,0x02,
+ 0x02,0x10,0x02,0x06,0x03,0x09,0x05,0x03,0x05,0x03,0x05,0x09,0x06,0x02,0x06,0x02,
+ 0x06,0x0b,0x09,0x02,0x02,0x06,0xe5,0x04,0x02,0x02,0x03,0x02,0x06,0x04,0x07,0x02,
+ 0x06,0x02,0x43,0x03,0x28,0x13,0xe5,0x09,0x10,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,
+ 0xe5,0x04,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x03,0xe5,0x13,0xe5,0x01,0xe5,0x04,
+ 0x02,0xe5,0x07,0x09,0x01,0x03,0xe5,0x15,0x45,0x01,0xe7,0x0d,0x09,0x04,0x01,0x02,
+ 0x02,0x02,0x03,0x06,0x02,0x02,0x06,0x02,0x06,0x07,0x01,0x06,0xe5,0xe5,0x06,0x01,
+ 0x09,0x06,0x02,0xe6,0xe5,0x01,0x02,0xe6,0xe5,0x04,0xe6,0x08,0xe5,0x07,0xe5,0xe5,
+ 0x02,0x02,0x04,0x01,0x02,0xe5,0x03,0x03,0xe5,0x01,0x05,0xe6,0x03,0x02,0x09,0x03,
+ 0x05,0x02,0x06,0x09,0x09,0x09,0x09,0x0d,0x01,0x01,0xe5,0x01,0x1d,0x10,0x02,0x09,
+ 0x13,0xe5,0xe5,0x02,0x03,0x01,0x06,0xe5,0xe5,0x05,0x08,0xe5,0x07,0xe5,0x27,0xe5,
+ 0x08,0x09,0x12,0xe5,0x12,0x43,0x03,0x1e,0x13,0x08,0x15,0x04,0x09,0x04,0x04,0x04,
+ 0x09,0x09,0x25,0x03,0x09,0x07,0x15,0x11,0x47,0x02,0x01,0x1f,0x02,0xe5,0x1a,0x09,
+ 0x0c,0x09,0x09,0x01,0x07,0x04,0x01,0xe5,0xe5,0x06,0xe6,0x03,0x02,0xe6,0x05,0x01,
+ 0xe5,0x02,0x01,0xe5,0xe8,0x03,0x01,0x02,0x04,0x01,0xe5,0x05,0x01,0xe5,0x08,0xe6,
+ 0x03,0x08,0x02,0x07,0x01,0x44,0x21,0x01,0x14,0x06,0x02,0x08,0xe6,0x08,0x09,0x09,
+ 0x09,0x02,0x02,0x01,0xe6,0x07,0xe5,0x01,0x02,0x01,0xe6,0x06,0x01,0x06,0xe5,0xe7,
+ 0x04,0x01,0x01,0x01,0x03,0x01,0x07,0x01,0x0b,0x07,0xe5,0x07,0xe5,0x04,0xe5,0xe6,
+ 0x3e,0xe5,0xe6,0x20,0x01,0x1b,0x0b,0x07,0x09,0x05,0x03,0x10,0x01,0xe5,0xe5,0x02,
+ 0xe5,0xe5,0x01,0x03,0x03,0x02,0x08,0x01,0x09,0x03,0x03,0x01,0x07,0x01,0x07,0x01,
+ 0x0b,0x07,0x07,0x01,0x07,0x01,0x42,0xe6,0x14,0xe5,0x07,0xe6,0xe6,0x01,0x01,0xe5,
+ 0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x06,0xe7,0xe5,0x02,0xe7,0x02,0x02,0x01,0xe6,0xe5,0x03,0xe6,
+ 0x01,0x01,0x05,0xe5,0x01,0xe5,0x03,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe6,0xe5,0x04,
+ 0xe5,0x07,0xe6,0x06,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0x22,0x03,0x0f,0x09,0x09,0x07,0x09,0x09,
+ 0x09,0x07,0x01,0x0c,0x06,0x02,0xe5,0x08,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,
+ 0x01,0x25,0x44,0xe6,0x28,0x0d,0x07,0x0b,0x09,0x09,0x09,0x06,0x02,0x06,0x02,0x03,
+ 0x02,0x03,0x05,0xe5,0xe5,0x05,0x04,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x13,0x13,0x42,0xe6,0x3e,0x0b,0x23,0x03,0x04,0xe5,0x07,0xe5,0x06,0x01,0x01,0x06,
+ 0x03,0x02,0x13,0x09,0x09,0x13,0x11,0x46,0x41,0x09,0x02,0x09,0x09,0x09,0xe9,0x03,
+ 0x01,0x01,0x05,0xe5,0xe6,0x04,0x01,0xe7,0xe5,0x01,0x03,0x04,0x0c,0x09,0x04,0x01,
+ 0x07,0x01,0x0c,0x1a,0x42,0x01,0x24,0x1d,0x06,0x09,0x01,0xe5,0x05,0x09,0x01,0xe5,
+ 0xe5,0x03,0x02,0x01,0x04,0xe5,0xe6,0x1a,0x01,0xe5,0x06,0x01,0x13,0x01,0x04,0x02,
+ 0x13,0x06,0x0c,0x40,0x01,0xe5,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x04,0x02,0x01,0x01,0xe5,0xe5,
+ 0x01,0x01,0xe5,0x05,0x01,0xe5,0x01,0x03,0x01,0xe5,0x05,0x01,0x02,0x04,0x01,0xe5,
+ 0x02,0x01,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x04,0x02,0x01,0x07,0xe6,0xe5,0x04,0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,
+ 0x01,0x08,0x02,0xe5,0xe5,0x20,0x02,0x0e,0x0b,0x12,0x04,0x09,0x0f,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x02,0x04,0xe5,0x18,0x08,0x03,0x09,0xe5,0x0b,0x05,0x0e,0x04,0x46,0xe5,
+ 0x1f,0x41,0x08,0x0d,0x0c,0x09,0xe5,0x15,0x02,0x01,0x05,0xe5,0x12,0x0a,0x09,0x01,
+ 0x09,0x09,0x38,0xe6,0xe6,0x79,0xe5,0xe5,0xe5,0x04,0x05,0xe5,0x01,0x09,0x1c,0x0a,
+ 0x08,0x63,0x01,0xe6,0x22,0x0c,0x04,0x01,0x04,0x12,0x05,0x04,0x04,0x09,0x07,0x09,
+ 0xe6,0x06,0xe6,0x0d,0x06,0xe5,0x01,0x03,0xe6,0xe5,0x04,0x07,0x01,0x01,0x06,0xe5,
+ 0xe5,0x04,0x0d,0x01,0x05,0x08,0x02,0x0b,0x34,0x03,0x21,0x0d,0x01,0x03,0x01,0x2f,
+ 0x07,0x03,0x08,0x06,0x02,0x06,0x0b,0x01,0x06,0x02,0x08,0x02,0x07,0x01,0x0a,0x10,
+ 0x0b,0x03,0x01,0x01,0x45,0xe5,0x22,0x03,0x05,0x02,0x05,0xe5,0x02,0x09,0x0d,0x09,
+ 0x17,0xe5,0x1b,0x05,0x06,0x03,0x06,0x04,0xe5,0x07,0xe5,0xe5,0x04,0x0c,0x01,0x05,
+ 0xe5,0x04,0x04,0x03,0x08,0x08,0x33,0xe5,0xe6,0x1b,0x03,0xe5,0x07,0xe6,0x07,0x12,
+ 0x0e,0x23,0x02,0x09,0x09,0x06,0x0e,0xe5,0x04,0x01,0x02,0x04,0x13,0x01,0x03,0x02,
+ 0x03,0x06,0x4e,0xe6,0x04,0x04,0xe5,0x16,0xe5,0x07,0x09,0x45,0x0e,0x0b,0xe5,0x04,
+ 0x03,0x08,0x07,0x04,0x03,0x04,0x04,0x02,0x06,0x11,0x0e,0x3b,0xe8,0x04,0x22,0x1a,
+ 0x22,0x01,0x2a,0x01,0x03,0x04,0x04,0x08,0x02,0x01,0x1b,0xe5,0xe5,0x5d,0xe5,0xe5,
+ 0x04,0x1f,0x13,0x13,0x0a,0x02,0x0e,0x05,0x12,0x12,0x02,0x14,0x0f,0x01,0x0c,0xe5,
+ 0x0b,0x52,0x01,0xe6,0x16,0x01,0x02,0x06,0x01,0x04,0xe5,0xe5,0x03,0x02,0x01,0x02,
+ 0x1e,0x0f,0x04,0x08,0x01,0x03,0x03,0x06,0x02,0x06,0x02,0x07,0x13,0x04,0x04,0x07,
+ 0x01,0x04,0x05,0x08,0x05,0x01,0x01,0x09,0x09,0x04,0x09,0x27,0xe9,0x17,0x08,0xe5,
+ 0x04,0x03,0x09,0x03,0x03,0x01,0x14,0x0b,0x02,0x01,0xe6,0x01,0x04,0x01,0x09,0x0a,
+ 0x0b,0x0e,0x0c,0x07,0x0c,0x02,0x03,0x04,0x07,0x09,0x11,0x01,0x35,0xe5,0x01,0xe5,
+ 0x17,0x0a,0x09,0x09,0x33,0x04,0x07,0x02,0x01,0x06,0x16,0x17,0x05,0x0a,0x12,0x01,
+ 0x08,0x08,0x09,0x05,0x14,0x1d,0x01,0xe8,0x18,0xe5,0x03,0x05,0xe5,0x01,0x3f,0x02,
+ 0x01,0x04,0x02,0x01,0x06,0xe5,0x01,0x03,0x01,0xe5,0x05,0x01,0xe5,0x07,0x05,0x0d,
+ 0x09,0x0a,0x01,0xe5,0x04,0x0f,0x06,0xe5,0x04,0x3c,0xe6,0xe7,0x01,0x01,0x16,0x05,
+ 0x06,0x01,0xe7,0x08,0x02,0x30,0x02,0xe5,0x06,0xe5,0x07,0xe5,0x01,0x03,0x02,0x01,
+ 0x06,0xe5,0x07,0x05,0xe5,0x04,0x01,0x0a,0x03,0x0c,0xe5,0xe5,0x08,0x09,0xe5,0x12,
+ 0xe5,0x30,0x01,0x02,0x02,0xe5,0x03,0x19,0x01,0xe5,0x05,0x01,0x02,0x02,0x04,0x3f,
+ 0x0f,0x0d,0x02,0xe5,0x02,0x05,0xe5,0x03,0x04,0xe5,0xe5,0x02,0xe5,0xe5,0xe6,0x0f,
+ 0x01,0x04,0x02,0xe5,0x02,0xe5,0x05,0x01,0x0b,0x02,0x01,0x34,0x04,0x01,0x01,0x02,
+ 0x1b,0x02,0x0b,0x03,0xe5,0x03,0x4d,0x10,0x0a,0xe5,0x01,0x06,0xe5,0xe5,0x05,0x02,
+ 0x10,0x02,0x05,0xe5,0x01,0xe5,0x01,0x02,0xe5,0xe5,0xe5,0x0d,0x02,0x01,0x33,0x02,
+ 0xe8,0x1e,0x01,0x19,0x02,0x2d,0x09,0x04,0x01,0x02,0x04,0x04,0x09,0x02,0x08,0x01,
+ 0x01,0xe5,0xe5,0x08,0x02,0xe5,0xe7,0x03,0x03,0xe5,0x06,0x07,0x02,0x03,0x06,0x01,
+ 0x0f,0x03,0x03,0x02,0x2f,0x01,0xe6,0x01,0x02,0x1b,0x03,0x09,0x09,0x41,0x01,0x01,
+ 0x05,0x03,0x15,0x05,0x03,0x04,0xe5,0x02,0x05,0x04,0xe5,0xe7,0x08,0x03,0x02,0x01,
+ 0x03,0xe5,0xe5,0x01,0xe5,0xe5,0x03,0x01,0x0c,0x01,0x02,0x01,0x2c,0x03,0x01,0xe6,
+ 0x21,0x04,0x02,0x09,0x37,0xe5,0x05,0xe5,0xe5,0x01,0x01,0x01,0x02,0x01,0xe5,0x1b,
+ 0x01,0x02,0x05,0x01,0x01,0x01,0x05,0x09,0x06,0x02,0x01,0x0e,0x02,0x01,0x44,0x04,
+ 0x01,0x02,0x1c,0x06,0x04,0xe5,0xe5,0x3e,0xe5,0xe5,0xe5,0x04,0x01,0xe7,0xe5,0x01,
+ 0x01,0x02,0x03,0xe5,0x07,0xe5,0x09,0xe5,0xe5,0x01,0x09,0x04,0x01,0x01,0xe5,0x03,
+ 0x04,0x04,0x01,0xe5,0xe5,0xe5,0x01,0x0b,0xe5,0xe5,0xe5,0x10,0x01,0x36,0xe6,0xe5,
+ 0x08,0x13,0x02,0x06,0x01,0xe5,0x05,0x02,0x10,0x02,0x21,0x09,0x02,0x06,0x04,0x04,
+ 0x09,0x0b,0x04,0x07,0x06,0x02,0x02,0x06,0x02,0x08,0x0e,0x02,0x01,0xe5,0x05,0xe5,
+ 0x3e,0x07,0xe6,0x09,0xe6,0x10,0xe5,0x1b,0x09,0xe5,0x21,0xe6,0xe5,0x04,0xe5,0x03,
+ 0x03,0xe5,0x01,0x05,0xe5,0x07,0xe6,0x08,0xe6,0x0c,0x03,0xe5,0x01,0xe5,0x0e,0x09,
+ 0x0c,0x06,0x02,0xe5,0x07,0xe5,0x07,0x31,0x02,0xe6,0x0d,0x04,0x01,0x02,0x06,0x02,
+ 0x02,0x06,0x04,0x01,0x02,0x03,0xe5,0xe5,0x01,0x09,0x09,0x09,0x06,0x02,0xe5,0x01,
+ 0xe5,0xe5,0x01,0xe6,0x03,0x02,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5,0xe5,0x02,
+ 0x02,0x04,0x01,0x02,0xe6,0x03,0x02,0x04,0x01,0x02,0x06,0x02,0x09,0x04,0xe6,0x01,
+ 0xe6,0x03,0x02,0x06,0x02,0x03,0x05,0x09,0x09,0x09,0x04,0x01,0x06,0x01,0x02,0x02,
+ 0x13,0x08,0xe5,0x08,0x09,0x09,0x24,0x02,0x04,0x09,0x01,0x1b,0x04,0x06,0x01,0x02,
+ 0x09,0x06,0x02,0x09,0x08,0xe5,0x08,0x09,0x08,0xe5,0x05,0x02,0x31,0x04,0x02,0x01,
+ 0x01,0x13,0x09,0x0b,0x09,0x07,0x29,0x05,0x1d,0x09,0x03,0x07,0x03,0x09,0x08,0x08,
+ 0x0b,0x05,0x02,0x0a,0x07,0x0a,0x31,0x0a,0x01,0xe5,0xe5,0x14,0x01,0x07,0x01,0x13,
+ 0x09,0x27,0xe7,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x06,0xe6,0x05,0xe7,0xe5,0x03,0x02,
+ 0xe6,0x05,0x07,0x01,0xe7,0x05,0x04,0x07,0x06,0x02,0x04,0x02,0xe5,0x06,0x04,0x02,
+ 0x01,0x02,0x04,0x36,0x04,0xe5,0x01,0x14,0x01,0x01,0x05,0x01,0xe5,0x08,0x09,0x08,
+ 0xe5,0x26,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x08,0x05,0x02,0xe5,0x09,0xe5,0x07,0x03,
+ 0x02,0x01,0xe6,0x04,0x01,0xe6,0x01,0x06,0x01,0x03,0x03,0x05,0x01,0x04,0x02,0x01,
+ 0xe6,0x04,0x01,0x01,0x07,0xe5,0x35,0x02,0x19,0x03,0xe5,0x03,0x07,0x01,0x06,0x0a,
+ 0x01,0x28,0x02,0x0a,0x01,0x11,0x04,0x01,0x04,0x06,0x07,0x09,0x01,0x01,0x05,0x0e,
+ 0x04,0x03,0x03,0x01,0x01,0x07,0x09,0x06,0xe5,0x37,0xe8,0x14,0xe5,0x01,0x05,0xe6,
+ 0xe5,0x04,0xe6,0x06,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,
+ 0x04,0xe8,0x05,0xe7,0x04,0xe7,0x02,0x02,0xe8,0x05,0xe6,0x09,0xe5,0x07,0xe6,0x06,
+ 0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x08,0xe6,0xe5,0x14,0x01,
+ 0x07,0x01,0xe6,0x1a,0x28,0xe5,0x07,0xe5,0x11,0xe5,0xe5,0x04,0xe5,0x07,0x09,0x01,
+ 0x07,0x01,0xe5,0x05,0x01,0x14,0x08,0x09,0x09,0x07,0x38,0x01,0x01,0x17,0x01,0x07,
+ 0x01,0x1b,0x01,0x27,0x04,0x01,0x02,0x04,0x01,0x02,0x03,0x02,0x09,0xe5,0x07,0x0c,
+ 0x01,0x07,0x01,0xe5,0x05,0x01,0x09,0x0a,0x10,0x09,0x01,0x09,0x36,0x03,0x19,0x09,
+ 0x07,0x01,0x13,0x25,0x05,0x01,0x01,0x09,0x06,0xe5,0x07,0xe5,0x02,0xe5,0x02,0x03,
+ 0x0c,0x09,0x09,0x31,0x07,0x39,0xe7,0x1b,0x06,0xe5,0x05,0x01,0xe5,0x0f,0x01,0x2a,
+ 0x01,0xe6,0x04,0x01,0x01,0x05,0xe5,0xe6,0x04,0x02,0xe6,0x03,0x01,0x01,0x07,0x0e,
+ 0x01,0x02,0x04,0x01,0x02,0x06,0x02,0x09,0x13,0x06,0x02,0x06,0x36,0xe5,0x01,0xe5,
+ 0x19,0x05,0x09,0x01,0xe5,0x05,0xe5,0xe5,0x32,0x18,0xe5,0xe5,0x11,0xe5,0xe5,0x05,
+ 0x09,0x09,0x02,0x06,0x09,0x01,0xe5,0x05,0x01,0xe5,0x08,0x10,0xe5,0xe5,0x33,0x03,
+ 0xe5,0x10,0x01,0x07,0x01,0x02,0xe5,0x02,0x01,0x04,0x02,0x01,0x03,0x03,0x01,0x02,
+ 0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe6,0x02,
+ 0x02,0x01,0x07,0x01,0x04,0x04,0x01,0x03,0x03,0x01,0xe5,0x02,0x02,0x01,0xe5,0x01,
+ 0x03,0x01,0xe5,0x05,0x01,0x02,0xe5,0x02,0x01,0x01,0x02,0x02,0x01,0x01,0x05,0x01,
+ 0x02,0x04,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0b,0x02,
+ 0x03,0x16,0x0f,0x04,0x01,0x0c,0x08,0x10,0x10,0x09,0x09,0xe5,0x04,0x02,0x01,0x07,
+ 0xe5,0x04,0x03,0x1c,0x01,0xe5,0x01,0x04,0x14,0xe5,0x05,0x02,0x49,0x01,0x01,0xe5,
+ 0x15,0x2b,0x0c,0x12,0x05,0x0a,0x04,0x07,0x05,0xe5,0x02,0x04,0x01,0x18,0xe5,0x0a,
+ 0x01,0x04,0x0b,0x0a,0x01,0x01,0x04,0x01,0x07,0x05,0x3c,0x04,0x25,0x29,0x0a,0x18,
+ 0xe5,0x04,0xe5,0xe5,0x10,0x09,0x1d,0x05,0x2c,0x04,0x3e,0xe5,0x01,0xe5,0x10,0x06,
+ 0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x02,0x04,0x18,0x0c,0xe5,0x07,0xe5,0x09,
+ 0xe5,0x04,0x11,0x0b,0x02,0x01,0x01,0x07,0x07,0xe5,0x07,0x01,0x03,0x03,0xe6,0xe5,
+ 0x01,0x02,0x02,0x05,0xe5,0x01,0x03,0x02,0x01,0x07,0xe6,0x34,0xe5,0xe7,0x17,0x07,
+ 0xe5,0x08,0x02,0x06,0x09,0x0d,0x16,0x01,0x12,0x01,0x1d,0x05,0x08,0x04,0x01,0x05,
+ 0xe5,0x0c,0xe5,0x01,0x05,0x07,0x03,0x09,0x04,0x01,0x02,0x07,0x38,0x01,0xe6,0x0d,
+ 0x09,0x09,0xe5,0x11,0x1e,0x09,0x07,0xe5,0x03,0x03,0xe5,0x24,0xe5,0x01,0xe5,0x05,
+ 0x18,0x1a,0x04,0x07,0x06,0x02,0xe5,0x3a,0x02,0x01,0x10,0x06,0xe5,0x07,0x04,0x09,
+ 0x04,0xe5,0xe5,0x2d,0x09,0x02,0x0d,0x01,0x0a,0x01,0x07,0x01,0xe6,0x05,0xe5,0xe5,
+ 0x06,0x09,0x01,0x02,0x04,0x09,0x01,0x02,0xe5,0x0c,0x09,0x01,0x42,0x01,0x05,0x04,
+ 0x05,0x06,0x09,0x02,0x05,0x0c,0x2f,0x07,0x01,0x03,0x09,0x15,0xe5,0x01,0x12,0x01,
+ 0xe5,0x03,0x03,0x0a,0x06,0x01,0x0d,0x06,0x03,0x08,0x03,0x3d,0xe6,0x04,0x08,0x07,
+ 0xe5,0x07,0x06,0x06,0x0c,0x30,0x02,0x02,0x03,0x04,0xe5,0x02,0x01,0x16,0x07,0x06,
+ 0xe5,0x03,0x04,0x03,0x05,0x0f,0xe6,0x05,0xe8,0x04,0x04,0xe5,0x02,0x47,0x05,0x08,
+ 0x05,0x02,0x0d,0x09,0x3b,0x08,0x09,0x0b,0x09,0x04,0x1b,0x19,0x05,0x02,0x1b,0x3a,
+ 0xe8,0x0e,0x06,0x01,0x04,0x07,0x06,0x04,0x2f,0x10,0x01,0x06,0x0a,0x03,0x0a,0xe5,
+ 0x09,0x04,0x04,0x05,0x08,0x16,0x0d,0x03,0x06,0x01,0x09,0x35,0x02,0x01,0x20,0x0c,
+ 0x01,0x07,0x32,0x09,0x06,0x01,0x0a,0x0a,0x13,0x13,0x02,0x27,0x06,0x07,0x01,0x36,
+ 0x02,0xe5,0x1c,0x09,0x03,0xe5,0x08,0x37,0x02,0x06,0x01,0x07,0x02,0x0e,0x0b,0x04,
+ 0x01,0x11,0x01,0x31,0x01,0x05,0x38,0xe5,0x01,0xe6,0x0e,0x09,0xe5,0x17,0x04,0x01,
+ 0x01,0x04,0xe5,0x07,0xe5,0x08,0x01,0x01,0x04,0xe5,0xe5,0xe5,0x03,0x01,0xe5,0x05,
+ 0x02,0x01,0x07,0x01,0x04,0x09,0x1f,0x05,0x72,0xea,0x01,0x01,0x0b,0x06,0x02,0x03,
+ 0x01,0x0a,0xe5,0x07,0xe5,0x04,0x01,0x02,0x08,0x02,0x06,0x05,0x01,0x01,0x05,0x01,
+ 0x02,0x04,0x01,0x04,0x01,0xe5,0x08,0xe5,0x05,0x01,0xe5,0x17,0xe5,0x03,0xe5,0x0a,
+ 0x0a,0x08,0xe5,0x07,0xe5,0x13,0x3b,0x01,0x02,0x01,0xe6,0x03,0x05,0xe5,0xe5,0xe5,
+ 0x10,0x01,0xe5,0x02,0xe5,0xe5,0xe5,0x06,0x01,0x0b,0x02,0x09,0x09,0x06,0x07,0x01,
+ 0xe5,0x0d,0x01,0x03,0xe5,0x01,0x01,0x01,0x09,0x0e,0x01,0x07,0x01,0x04,0x01,0xe5,
+ 0x06,0x10,0x04,0xe5,0x02,0x02,0x06,0x04,0xe5,0x3e,0x04,0x02,0xe5,0x01,0x07,0xe5,
+ 0xe5,0x08,0x06,0xe5,0xe8,0x02,0x04,0x07,0x01,0x09,0x04,0x01,0x02,0x04,0x01,0x02,
+ 0x04,0x01,0x02,0x04,0x13,0x02,0x01,0x04,0x02,0x01,0x1a,0xe5,0x10,0xe5,0x08,0xe5,
+ 0x0a,0x09,0xe5,0x07,0x06,0xe5,0x40,0x06,0x0d,0x01,0x02,0x01,0x01,0x02,0x02,0x06,
+ 0xe5,0x03,0x03,0x04,0x01,0xe5,0xe5,0x01,0x01,0x01,0x05,0xe5,0x01,0x02,0x02,0xe5,
+ 0x01,0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0xe7,0x04,0x02,0xe5,0xe5,0x01,0x02,0x06,
+ 0x02,0x06,0x04,0x01,0x02,0x06,0x01,0x13,0x04,0x01,0x0a,0x01,0xe5,0x04,0xe5,0xe5,
+ 0x05,0x02,0xe5,0x0e,0x06,0x02,0x3c,0xe5,0x01,0x0a,0x04,0x03,0xe5,0x03,0x01,0x01,
+ 0xe5,0x01,0xe5,0x04,0x03,0x01,0x02,0xe5,0xe5,0x02,0x02,0x02,0x02,0x09,0x09,0x09,
+ 0x01,0x01,0x04,0x05,0x01,0x01,0x09,0x09,0x05,0x01,0x01,0x07,0x01,0x01,0x09,0x05,
+ 0x0d,0x05,0x01,0xe5,0x01,0x01,0xe5,0x01,0x01,0x01,0x01,0xe6,0x01,0xe5,0x01,0x01,
+ 0x08,0xe5,0x01,0x01,0x02,0x01,0x36,0x02,0xe6,0xe6,0x13,0x03,0x07,0x09,0x01,0x07,
+ 0x01,0x03,0xe5,0x1c,0x01,0x14,0x01,0x07,0x01,0x04,0x01,0xe5,0xe5,0xe6,0x03,0x01,
+ 0x01,0x01,0xe5,0x03,0x01,0x11,0x01,0x11,0x01,0x04,0x02,0x01,0x07,0x06,0x02,0x01,
+ 0x04,0xe5,0x02,0x3f,0x02,0xe6,0x11,0x04,0x04,0x06,0x09,0x07,0x01,0x01,0x07,0x02,
+ 0x06,0x02,0x06,0x02,0x01,0x01,0x02,0x02,0x04,0x09,0x01,0x01,0xe5,0x03,0x01,0x01,
+ 0xe5,0xe5,0x01,0x01,0x02,0x04,0x01,0x02,0x01,0x01,0x02,0x01,0x11,0x04,0x0e,0x01,
+ 0xe5,0x01,0xe6,0x02,0x09,0x03,0xe6,0xe5,0xe5,0x01,0x01,0xe5,0x02,0x40,0xe5,0x01,
+ 0x1d,0x02,0x03,0x02,0xe5,0x07,0x02,0x06,0x03,0x09,0x05,0x03,0x05,0x03,0x05,0x09,
+ 0x06,0x02,0xe5,0x04,0x02,0x01,0xe5,0x02,0x09,0x22,0x10,0x0c,0x06,0x02,0x02,0x06,
+ 0xe6,0x43,0xe8,0x13,0xe5,0x07,0xe5,0x07,0x09,0x0b,0x10,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x03,0x03,0xe5,0x04,0xe6,0xe6,0x03,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x1e,0x02,0x01,
+ 0x0e,0x02,0xe5,0x07,0xe6,0x06,0x06,0x0c,0x09,0x32,0xe8,0x0d,0x06,0x02,0x04,0x01,
+ 0x02,0x03,0xe5,0xe5,0x01,0x04,0xe6,0x01,0xe5,0x07,0x04,0x01,0xe5,0xe5,0x06,0x01,
+ 0x06,0xe5,0xe5,0x08,0x09,0xe5,0x04,0x02,0xe5,0xe5,0x05,0xe8,0x01,0x02,0xe6,0x08,
+ 0x02,0x03,0x02,0x06,0x02,0x03,0x05,0x02,0x03,0x02,0xe6,0x06,0x09,0x04,0xe6,0x01,
+ 0x06,0x02,0x04,0xe6,0x01,0x03,0x05,0x09,0x09,0x09,0x0d,0xe6,0x01,0x02,0x12,0xe5,
+ 0x08,0x09,0x09,0x13,0xe5,0xe5,0x05,0xe5,0xe5,0x02,0x03,0x01,0x06,0x09,0x04,0x03,
+ 0xe5,0x0d,0x03,0xe5,0x13,0x09,0xe5,0x0f,0x02,0x09,0x13,0x06,0x02,0x09,0x36,0x02,
+ 0xe8,0x14,0x07,0x0a,0x08,0x13,0x06,0x04,0x04,0x09,0x04,0x09,0x05,0x03,0x05,0x0b,
+ 0x21,0x12,0x0a,0x11,0x09,0x09,0x3c,0x03,0x01,0x0b,0x04,0x04,0x04,0x07,0x08,0x09,
+ 0x01,0x14,0x09,0x09,0x01,0x07,0x01,0x04,0xe7,0x05,0xe7,0x02,0x02,0xe7,0x05,0xe5,
+ 0xe5,0x16,0x04,0x02,0x03,0xe5,0xe5,0x09,0x01,0x01,0x04,0x06,0x03,0xe5,0x01,0x07,
+ 0x03,0x02,0x07,0x01,0x34,0x01,0x01,0x01,0x0a,0x04,0x01,0x07,0x01,0x05,0x01,0x07,
+ 0x02,0x06,0x01,0xe6,0x08,0x09,0x09,0x09,0x02,0x06,0x08,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe5,0x04,0x02,0xe5,0x10,0x02,0x06,0x03,0x01,0x03,0x01,0xe5,0x09,0x07,0xe5,0x05,
+ 0x01,0x04,0x02,0x01,0x01,0x01,0x06,0x06,0x01,0xe5,0x34,0xe8,0x09,0x02,0x06,0x08,
+ 0x05,0x07,0x08,0x02,0x01,0x0f,0x05,0x03,0x05,0x03,0x05,0x0c,0x03,0x03,0x01,0x03,
+ 0x0a,0x02,0x04,0x03,0x23,0x01,0x04,0x04,0x07,0x0b,0x01,0x0b,0x0d,0x38,0xe5,0xe6,
+ 0x0e,0x05,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x01,0x05,0xe6,0x06,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x06,0x01,0x02,0x04,0xe6,0x01,0x03,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x05,0xe6,0x09,0xe6,0x06,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe6,0x06,0xe6,0x06,0xe6,0xe5,0x04,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x06,0x01,0xe6,0x0c,0x0b,0x09,0x07,0x0b,0x11,0x09,0x09,0x09,
+ 0x10,0x0f,0x08,0xe6,0x1c,0x07,0x13,0x02,0x08,0x1b,0x01,0x36,0xe6,0xe5,0x0e,0x07,
+ 0x09,0x15,0x13,0x09,0x09,0x09,0x06,0xe5,0x07,0xe5,0x05,0x01,0x02,0x06,0xe5,0x07,
+ 0x16,0x09,0x16,0x06,0x09,0x01,0x11,0x01,0x37,0xe7,0x18,0x09,0x07,0x3d,0x04,0xe7,
+ 0x07,0xe5,0x04,0x01,0xe6,0x01,0x02,0xe7,0x01,0x04,0x01,0x01,0x1e,0x0b,0x07,0x0b,
+ 0x1d,0x37,0xe7,0x11,0x09,0x04,0x18,0x09,0x09,0x09,0x09,0x04,0x04,0xe6,0x06,0x09,
+ 0x01,0x07,0x01,0x02,0x04,0x1f,0x04,0x0e,0x07,0x06,0x0e,0x0e,0x38,0x03,0x0d,0xe5,
+ 0xe5,0x08,0x11,0x01,0x08,0xe5,0x05,0x01,0xe5,0x05,0x09,0x01,0xe5,0x05,0x47,0x01,
+ 0xe5,0x05,0x09,0x09,0x01,0xe5,0x05,0xe5,0xe5,0x09,0x09,0x03,0x01,0x42,0xe5,0xe6,
+ 0xe5,0x0a,0x03,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x04,0x02,
+ 0x01,0x02,0x01,0x02,0x01,0xe5,0x02,0x02,0xe6,0xe5,0x01,0x02,0x01,0x01,0x05,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x04,0x04,0x01,0x01,0x05,0x01,0xe6,
+ 0x04,0x01,0xe6,0x04,0x01,0x01,0x02,0x01,0xe5,0xe5,0xe5,0xe5,0x02,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x08,0x04,0xe5,0x16,0x08,0x03,0x26,0xe5,0xe5,0x0a,0x06,0x0c,0x04,0xe5,0x01,
+ 0x10,0x04,0x03,0xe5,0x04,0x0d,0x09,0x09,0x73,0x02,0xe6,0x1f,0x03,0x09,0x1a,0x05,
+ 0xe6,0x1a,0x04,0x05,0x0a,0x01,0x03,0x05,0x0d,0x0a,0x0e,0x31,0x07,0x06,0x02,0x30,
+ 0x01,0xe5,0xe5,0x4a,0x0c,0x18,0x10,0x0b,0x01,0x07,0xe6,0x06,0x01,0x30,0x11,0x0c,
+ 0x04,0x37,0xe5,0x0c,0xe6,0x06,0x01,0x01,0x05,0xe6,0x06,0xe7,0x07,0x01,0x01,0x0d,
+ 0xe5,0x09,0x09,0x07,0x09,0x01,0x05,0x03,0xe5,0x04,0xe5,0x0f,0x03,0x0a,0x01,0xe5,
+ 0x0f,0x01,0x11,0xe6,0x08,0x04,0x01,0x02,0x07,0x01,0xe5,0x05,0x03,0x36,0xe6,0x0d,
+ 0x0a,0x07,0x09,0x0a,0x1c,0x16,0x06,0x02,0x05,0x01,0x0a,0x02,0x0e,0x0c,0x01,0x13,
+ 0x11,0x08,0x05,0x04,0x0b,0xe5,0x07,0x02,0x32,0x02,0xe5,0x0f,0x06,0x01,0x09,0x03,
+ 0x05,0x14,0x12,0x07,0x02,0x01,0x27,0x0c,0x01,0x11,0x01,0x03,0x01,0x05,0x2c,0x01,
+ 0xe5,0xe5,0x0a,0x37,0xe7,0x0f,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0x06,0x08,0x1d,0xe5,
+ 0x14,0x09,0x02,0x0a,0x06,0x05,0x04,0x04,0x05,0x03,0x04,0x06,0xe5,0x0a,0x13,0x06,
+ 0x05,0x03,0x01,0x02,0x04,0x08,0xe6,0x37,0x01,0xe5,0x13,0x04,0x02,0x04,0x08,0x09,
+ 0xe5,0x1e,0x18,0xe5,0x05,0x09,0x0b,0x04,0x07,0x12,0x02,0x04,0x20,0x03,0x0c,0x06,
+ 0x09,0x39,0xe5,0x1f,0x03,0xe5,0xe5,0x13,0x16,0xe5,0x10,0x09,0xe7,0x05,0xe7,0x05,
+ 0xe5,0x07,0x08,0x01,0x10,0x16,0x04,0x09,0xe5,0x01,0x06,0xe5,0x06,0x06,0xe6,0x3f,
+ 0xe5,0x01,0x29,0x0f,0x0a,0xe5,0x0c,0x01,0x1c,0x09,0x08,0x04,0x08,0x05,0x41,0x03,
+ 0x0e,0x40,0xe7,0x16,0x01,0x06,0xe5,0xe5,0x08,0x18,0x09,0xe5,0x02,0x0a,0x0b,0xe6,
+ 0x01,0x01,0x04,0x02,0x01,0x0d,0x05,0x0b,0x13,0x09,0x0b,0x1c,0x0f,0xe5,0xe5,0x35,
+ 0xe6,0xe6,0x14,0x02,0x0c,0x05,0xe5,0x01,0x1b,0x01,0x06,0x01,0xe5,0xe5,0x06,0x04,
+ 0x01,0x07,0x01,0xe5,0x07,0x14,0xe6,0x05,0x01,0x02,0x0f,0x28,0x01,0x05,0x01,0xe5,
+ 0x03,0x03,0x09,0x35,0x01,0xe7,0x10,0x07,0x12,0x26,0x01,0x01,0x09,0x1b,0x11,0x0a,
+ 0xe5,0x0d,0x0e,0x05,0x19,0x06,0x0c,0x09,0x38,0xe8,0x28,0x2d,0xe5,0x04,0xe5,0x01,
+ 0x01,0x04,0x09,0x02,0x01,0x04,0x02,0xe5,0xe5,0x02,0x0a,0x1a,0x03,0xe5,0x24,0x13,
+ 0xe5,0x3b,0xe5,0x01,0xe6,0x01,0x01,0x17,0x09,0x04,0xe6,0x24,0x06,0x01,0x06,0xe5,
+ 0x0f,0x01,0xe5,0x04,0x03,0x01,0xe5,0x25,0x01,0x0a,0xe5,0x2f,0xe5,0xe5,0x05,0xe5,
+ 0x31,0x01,0x02,0x03,0x04,0x0f,0x01,0x07,0x01,0x06,0xe5,0x01,0x01,0x22,0xe5,0x02,
+ 0x0b,0x09,0x19,0x03,0x01,0xe5,0x21,0x03,0x07,0x22,0xe5,0xe5,0xe5,0x08,0x04,0xe5,
+ 0x02,0x31,0x04,0xe5,0xe6,0x01,0x11,0x08,0xe5,0x08,0xe5,0xe5,0xe5,0x21,0x02,0x31,
+ 0x33,0x1a,0x09,0x02,0x06,0xe5,0xe5,0x05,0x02,0x35,0x02,0xe5,0x01,0x15,0x08,0x01,
+ 0x0c,0x07,0x01,0x19,0x01,0x05,0x02,0x0f,0x09,0x09,0x04,0x04,0x09,0xe5,0x01,0x1f,
+ 0xe5,0xe5,0x18,0x09,0x01,0x01,0x02,0xe5,0x01,0x02,0x05,0x03,0x36,0xe8,0x01,0x18,
+ 0x01,0x02,0x04,0x04,0x02,0x01,0x05,0x01,0x01,0x1d,0x2d,0x03,0x09,0x23,0x01,0x01,
+ 0x01,0x01,0x02,0x18,0x01,0x02,0xe5,0x03,0x04,0x03,0x05,0x03,0x04,0x2c,0x02,0x03,
+ 0xe5,0x27,0x01,0x09,0x01,0x1b,0x17,0x01,0xe5,0x05,0xe5,0x07,0x05,0x10,0x01,0x20,
+ 0x01,0x22,0x09,0x02,0x01,0x02,0x04,0x07,0x2f,0xe6,0x01,0x17,0x09,0x09,0x09,0x01,
+ 0x1d,0x16,0x01,0x01,0x05,0x09,0x04,0x03,0xe5,0x03,0x03,0x02,0x01,0x1b,0x04,0x01,
+ 0x1b,0x06,0xe5,0x05,0xe7,0x0c,0x39,0xe5,0x1c,0x02,0x35,0x02,0x10,0x09,0x09,0x09,
+ 0x09,0x02,0x02,0x26,0x02,0x1a,0x01,0xe5,0x05,0x09,0x02,0x3a,0xe7,0x1d,0x09,0x2e,
+ 0x02,0x01,0x0d,0xe6,0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x28,0x34,0xe6,
+ 0x43,0xe8,0x0d,0x09,0x05,0x03,0x03,0x02,0x02,0x02,0x06,0x09,0x09,0x04,0x01,0x02,
+ 0x01,0x01,0x05,0x09,0xe6,0xe6,0xe5,0x01,0xe6,0xe5,0x01,0x02,0xe6,0xe5,0x04,0xe5,
+ 0x07,0x0b,0x09,0x09,0x04,0x01,0x02,0x02,0x06,0x09,0x09,0x09,0x04,0x01,0x02,0x02,
+ 0x06,0x09,0x09,0x09,0x09,0x0d,0xe7,0xe5,0x01,0x24,0x02,0x3b,0x04,0x09,0x01,0x16,
+ 0x29,0x27,0x09,0x09,0x36,0x03,0x01,0xe5,0x26,0x3d,0x23,0x03,0x29,0x27,0x07,0x0b,
+ 0x3d,0xe5,0xe5,0x16,0x09,0x07,0x01,0x22,0x04,0xe6,0x0b,0x02,0x01,0xe5,0xe5,0x05,
+ 0xe7,0x02,0x02,0xe5,0xe5,0x06,0xe6,0x05,0xe6,0x08,0x13,0x02,0x24,0x04,0x02,0x04,
+ 0x03,0x0a,0x01,0x34,0x04,0xe5,0x15,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x20,0x05,0xe5,
+ 0x0d,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x08,0xe5,0x11,0x01,0x01,0x06,
+ 0x1c,0xe5,0x07,0x01,0x08,0x09,0x35,0xe8,0x29,0xe5,0xe5,0x23,0x03,0x16,0xe5,0xe5,
+ 0x03,0x0b,0xe5,0x04,0x02,0x02,0x04,0x01,0x07,0x0e,0x04,0x06,0x02,0x31,0x06,0xe5,
+ 0xe5,0x35,0x03,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe8,0x05,0xe7,0x04,0xe7,0x05,0xe7,0x06,0xe6,
+ 0x03,0x05,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,
+ 0xe5,0x01,0x19,0x07,0x01,0x07,0x01,0x3c,0xe5,0x07,0x13,0xe5,0xe5,0x10,0x3b,0x07,
+ 0x13,0x01,0x36,0x01,0xe6,0x18,0x07,0x01,0x09,0x3f,0x02,0x02,0xe5,0x02,0x01,0x02,
+ 0x03,0x02,0x09,0x09,0x04,0x3b,0x09,0x09,0x40,0xe8,0x2a,0x01,0x39,0x01,0x04,0xe5,
+ 0xe5,0x08,0x06,0xe5,0x07,0xe5,0x07,0x03,0x02,0x1d,0x31,0x07,0x01,0x36,0x02,0xe5,
+ 0x03,0x28,0x2a,0x13,0xe5,0xe6,0x04,0x01,0x01,0x05,0xe5,0xe6,0x04,0x02,0xe5,0x04,
+ 0x01,0x01,0x04,0x16,0x2e,0x02,0x48,0x02,0x04,0x12,0x07,0x01,0xe5,0xe5,0x05,0x02,
+ 0x25,0x01,0x2e,0xe5,0xe5,0x08,0x19,0x04,0xe5,0x21,0x01,0x01,0xe5,0x05,0xe5,0xe5,
+ 0x05,0x42,0xe8,0xe5,0xe5,0x0c,0x01,0x03,0x03,0x01,0x03,0x03,0x01,0x03,0x03,0x01,
+ 0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,
+ 0x06,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x02,0x01,0x04,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x02,0x02,0x20,0x0a,0x3d,0x06,
+ 0x03,0x02,0x05,0xe6,0x0e,0x06,0x41,0x07,0x08,0xe5,0x42,0x02,0xe6,0x23,0x31,0xe5,
+ 0x0f,0x08,0x01,0x02,0x22,0x40,0x08,0x48,0x01,0xe7,0x69,0x05,0x0a,0x01,0x1b,0x94,
+ 0x01,0x01,0x21,0xe6,0x2e,0x01,0x11,0x01,0x07,0xe6,0x04,0x01,0xe7,0x0f,0x01,0x19,
+ 0x05,0x32,0x06,0x46,0x22,0x04,0x11,0x1b,0x12,0x01,0x07,0x09,0x0e,0x03,0x01,0x07,
+ 0x15,0x0f,0x1d,0x10,0x0c,0x33,0xe5,0xe5,0x41,0x09,0x06,0x02,0x35,0x04,0x03,0x03,
+ 0x98,0x43,0x1c,0x04,0x04,0x0b,0x09,0x0e,0x09,0x4b,0x3d,0x0c,0x01,0x1c,0xe5,0x01,
+ 0x37,0x0d,0x05,0x13,0x0c,0x03,0xe5,0x05,0x95,0xe7,0x5b,0x32,0xe5,0x07,0x18,0x7d,
+ 0xe6,0x56,0x32,0x04,0x01,0x01,0x05,0xe5,0x03,0x3b,0xe5,0x1b,0x34,0x01,0x01,0x27,
+ 0x01,0x44,0x1c,0x59,0x49,0xe8,0x41,0x44,0x0a,0x19,0x7f,0x02,0xe6,0x44,0x32,0x1b,
+ 0x9a,0xe5,0xe7,0x24,0xe5,0x39,0xe5,0x05,0xe5,0x07,0x01,0xe5,0x05,0xe5,0x08,0x08,
+ 0x98,0xe5,0x02,0xe5,0x01,0x01,0x23,0x01,0x38,0xe5,0x03,0x08,0x02,0x01,0xe5,0x02,
+ 0x09,0x0a,0xe5,0x95,0x01,0x05,0xe5,0x03,0x37,0x01,0xe5,0xe5,0x28,0x02,0x09,0x06,
+ 0x02,0x09,0x01,0xe5,0x98,0x05,0xe7,0x01,0x3c,0x01,0x27,0x04,0x01,0x02,0x04,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x9e,0x03,0x01,0xe5,0x6b,0xe5,0x01,0x02,0x02,0xe5,0x01,
+ 0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0xe6,0x01,0x03,0x02,0x96,0x02,0x02,0x40,0x25,
+ 0x02,0x09,0x01,0x01,0x05,0x09,0x08,0x97,0x02,0x01,0x01,0xe5,0x3d,0x01,0x4a,0x01,
+ 0x9e,0xe5,0xe7,0x3e,0x01,0x27,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x01,0x01,0xe5,
+ 0x9f,0xe6,0x66,0x09,0x05,0x03,0x05,0x03,0x05,0x09,0x98,0xe8,0x76,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x03,0x03,0xe5,0x98,0x01,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x04,0x01,0xe5,0xe5,0x05,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x05,0x02,0x0b,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,
+ 0xe5,0x01,0x6d,0xe5,0xe5,0x04,0xe6,0xe5,0x05,0xe5,0xe5,0x04,0xe5,0x9b,0x02,0x01,
+ 0x01,0x6d,0x06,0x04,0x04,0x02,0x06,0x04,0xa0,0x03,0x01,0x74,0x01,0x07,0x01,0x07,
+ 0x09,0x97,0x01,0x02,0xe5,0x27,0x42,0x09,0x09,0x09,0x09,0x9a,0x03,0x71,0x05,0x03,
+ 0x09,0x06,0xa1,0xe6,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x06,0xe5,0x01,0x71,0x09,0x09,0x09,0x9e,0xe8,0x72,0x09,0x09,0x09,0x9c,0x03,0x91,
+ 0x08,0x93,0x02,0xe5,0x2d,0x3d,0x09,0x09,0x09,0x04,0x04,0x9a,0xe5,0xe5,0x66,0x01,
+ 0xe5,0x05,0x09,0x01,0xe5,0x05,0x09,0x12,0x8b,0xe5,0xe6,0xe5,0x0e,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0x06,0x01,0x04,
+ 0x02,0x01,0x04,0x02,0xe8,0x01,0x02,0x01,0xe5,0x02,0x02,0x01,0x02,0xe5,0x02,0x01,
+ 0x04,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x08,0x01,0xe6,0xe5,0x3c,0x35,0x01,0x09,0x0e,0x9f,0x01,0xe7,0x36,0xe3,0x12,0xe5,
+ 0xe7,0x46,0x13,0x17,0x25,0x8a,0x0a,0xe5,0xe5,0x1c,0x48,0x0c,0x09,0x07,0xe5,0x07,
+ 0xa0,0xe6,0x47,0x1b,0x12,0x0c,0x0d,0x06,0x3c,0x5b,0x5c,0x03,0x0f,0xe5,0x08,0x0a,
+ 0xe5,0x10,0x16,0xe5,0x05,0x6d,0x07,0xe5,0x01,0x63,0x21,0x13,0x15,0x7e,0x02,0xe5,
+ 0x61,0x13,0x01,0x0c,0x13,0x11,0x05,0x7d,0xe5,0xe5,0x91,0x06,0x94,0xe5,0x01,0x8a,
+ 0x0d,0xe5,0x93,0x02,0xe5,0x61,0x24,0x12,0x06,0x05,0x27,0x09,0x57,0xe6,0x37,0x32,
+ 0x1b,0x1d,0xe5,0x24,0x01,0x08,0x54,0xe5,0x01,0xe5,0x3a,0x49,0x21,0x25,0x60,0xe5,
+ 0xe6,0x02,0x09,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x03,0xe5,0x01,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe7,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x09,0xe5,0x01,
+ 0xe5,0x0d,0x01,0x09,0x09,0x09,0x09,0x02,0x06,0x02,0x06,0x07,0x01,0x09,0x07,0x01,
+ 0x05,0x03,0x09,0x09,0x07,0x01,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x02,0x0a,0x03,0x0f,0x05,0x03,0x09,0x09,0x09,0x04,0x04,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x0a,0x11,0x02,0xe5,0x11,0xe5,0x03,0x03,0x09,0x1d,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x11,0xe5,0x97,0x8b,0x09,0x01,0xe6,0x0e,0x05,0x03,0x09,
+ 0x09,0x09,0x09,0x04,0x04,0x09,0x09,0x04,0x04,0x09,0x06,0x02,0x09,0x09,0x06,0x01,
+ 0x02,0x09,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,
+ 0xe5,0x01,0x0d,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0x07,0xe5,0x09,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x10,0xe6,0x02,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x08,0xe5,0x08,0x03,0x05,0x09,0x03,0x05,0x09,0x01,
+ 0x07,0x0b,0x01,0x07,0x09,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x0b,0x05,0xe5,0xe5,0x0d,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0x02,0x08,0xe5,0x07,0x02,
+ 0x06,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x02,0x06,0x02,0x06,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x0b,0x01,0x01,0x0e,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0f,0xe6,0xe5,0x86,0x09,0x15,0x27,0x09,0x4e,0x05,0xe5,0x01,0x0e,0x09,0x09,0x09,
+ 0x09,0x13,0x13,0x05,0x03,0x09,0x09,0x09,0x09,0x08,0x02,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0xe6,0x3f,0x13,0x10,0x33,0x1d,
+ 0x76,0x03,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,
+ 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0e,0xe7,0x03,0x37,0x03,0x05,0x0d,0x0f,0xe5,0x33,0x1c,0x72,0x03,0xe6,0xe5,0x37,
+ 0x09,0x13,0x42,0xe5,0x8e,0x04,0xe7,0x3f,0x13,0x44,0x90,0x03,0xe6,0xe5,0x8f,0x9d,
+ 0x03,0x13,0x09,0x09,0x09,0x1d,0x09,0x0c,0x06,0x09,0x09,0x36,0x06,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x15,0x01,0xe5,0x35,0x05,0x03,0x05,0x0d,0x0f,0x2a,
+ 0x97,0x06,0x02,0xe5,0x98,0x8e,0x05,0x03,0xe3,0x50,0x14,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x04,0xe6,0x01,0xe5,0x04,0x09,0xe8,
+ 0x04,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x0f,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x08,0xe5,0x06,0xe6,
+ 0x05,0xe5,0xe7,0x07,0xe5,0x05,0xe7,0x08,0x09,0x08,0xe5,0x07,0xe5,0x08,0x07,0xe6,
+ 0x08,0x09,0x09,0x09,0x09,0x0f,0x01,0xe5,0x38,0x09,0x13,0x0a,0x36,0x95,0x02,0x0d,
+ 0x09,0x09,0x09,0x09,0x04,0x04,0x03,0xe5,0x03,0x09,0x03,0x05,0x04,0x04,0x09,0x09,
+ 0x11,0x09,0x0b,0x09,0x09,0x01,0x09,0x1d,0x0b,0x07,0x09,0x09,0x09,0x09,0x0f,0x01,
+ 0xe7,0x0a,0x02,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x03,0x02,0x02,0x03,0x01,0xe5,
+ 0x01,0x01,0x07,0x03,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x02,0x04,
+ 0x15,0x04,0x0e,0x03,0x07,0x01,0x07,0x02,0x06,0x02,0x06,0x01,0x07,0x09,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x05,0xe6,0xe5,0xe5,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
diff --git a/u-boot/board/esd/dasa_sim/Makefile b/u-boot/board/esd/dasa_sim/Makefile
new file mode 100644
index 0000000..f1cadb1
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/Makefile
@@ -0,0 +1,54 @@
+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/dasa_sim/cmd_dasa_sim.c b/u-boot/board/esd/dasa_sim/cmd_dasa_sim.c
new file mode 100644
index 0000000..4946538
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#define OK 0
+#define ERROR (-1)
+
+#define TRUE 1
+#define FALSE 0
+
+
+extern u_long pci9054_iobase;
+
+
+/***************************************************************************
+ *
+ * Routines for PLX PCI9054 eeprom access
+ *
+ */
+
+static unsigned int PciEepromReadLongVPD (int offs)
+{
+	unsigned int value;
+	unsigned int ret;
+	int count;
+
+	pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
+				(offs << 16) | 0x0003);
+	count = 0;
+
+	for (;;) {
+		udelay (10 * 1000);
+		pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
+		if ((ret & 0x80000000) != 0) {
+			break;
+		} else {
+			count++;
+			if (count > 10) {
+				printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
+				break;
+			}
+		}
+	}
+
+	pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
+
+	return value;
+}
+
+
+static int PciEepromWriteLongVPD (int offs, unsigned int value)
+{
+	unsigned int ret;
+	int count;
+
+	pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
+	pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
+				(offs << 16) | 0x80000003);
+	count = 0;
+
+	for (;;) {
+		udelay (10 * 1000);
+		pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
+		if ((ret & 0x80000000) == 0) {
+			break;
+		} else {
+			count++;
+			if (count > 10) {
+				printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
+				break;
+			}
+		}
+	}
+
+	return TRUE;
+}
+
+
+static void showPci9054 (void)
+{
+	int val;
+	int l, i;
+
+	/* read 9054-values */
+	for (l = 0; l < 6; l++) {
+		printf ("%02x: ", l * 0x10);
+		for (i = 0; i < 4; i++) {
+			pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
+						l * 16 + i * 4,
+						(unsigned int *)&val);
+			printf ("%08x ", val);
+		}
+		printf ("\n");
+	}
+	printf ("\n");
+
+	for (l = 0; l < 7; l++) {
+		printf ("%02x: ", l * 0x10);
+		for (i = 0; i < 4; i++)
+			printf ("%08x ",
+				PciEepromReadLongVPD ((i + l * 4) * 4));
+		printf ("\n");
+	}
+	printf ("\n");
+}
+
+
+static void updatePci9054 (void)
+{
+	int val;
+
+	/*
+	 * Set EEPROM write-protect register to 0
+	 */
+	out_be32 ((void *)(pci9054_iobase + 0x0c),
+		  in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
+
+	/* Long Serial EEPROM Load Registers... */
+	val = PciEepromWriteLongVPD (0x00, 0x905410b5);
+	val = PciEepromWriteLongVPD (0x04, 0x09800001);	/* other input controller */
+	val = PciEepromWriteLongVPD (0x08, 0x28140100);
+
+	val = PciEepromWriteLongVPD (0x0c, 0x00000000);	/* MBOX0... */
+	val = PciEepromWriteLongVPD (0x10, 0x00000000);
+
+	/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
+	val = PciEepromWriteLongVPD (0x14, 0xfffc0000);	/* LAS0RR... */
+	val = PciEepromWriteLongVPD (0x18, 0x00000001);	/* LAS0BA */
+
+	val = PciEepromWriteLongVPD (0x1c, 0x00200000);	/* MARBR... */
+	val = PciEepromWriteLongVPD (0x20, 0x00300500);	/* LMISC/BIGEND */
+
+	val = PciEepromWriteLongVPD (0x24, 0x00000000);	/* EROMRR... */
+	val = PciEepromWriteLongVPD (0x28, 0x00000000);	/* EROMBA */
+
+	val = PciEepromWriteLongVPD (0x2c, 0x43030000);	/* LBRD0... */
+
+	val = PciEepromWriteLongVPD (0x30, 0x00000000);	/* DMRR... */
+	val = PciEepromWriteLongVPD (0x34, 0x00000000);
+	val = PciEepromWriteLongVPD (0x38, 0x00000000);
+
+	val = PciEepromWriteLongVPD (0x3c, 0x00000000);	/* DMPBAM... */
+	val = PciEepromWriteLongVPD (0x40, 0x00000000);
+
+	/* Extra Long Serial EEPROM Load Registers... */
+	val = PciEepromWriteLongVPD (0x44, 0x010212fe);	/* PCISID... */
+
+	/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
+	/* Offset to LAS1: Group 1: 0x00040000                 */
+	/*                 Group 2: 0x00080000                 */
+	/*                 Group 3: 0x000c0000                 */
+	val = PciEepromWriteLongVPD (0x48, 0xffe00000);	/* LAS1RR */
+	val = PciEepromWriteLongVPD (0x4c, 0x00040001);	/* LAS1BA */
+	val = PciEepromWriteLongVPD (0x50, 0x00000208);	/* LBRD1 */ /* so wars bisher */
+
+	val = PciEepromWriteLongVPD (0x54, 0x00004c06);	/* HotSwap... */
+
+	printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
+}
+
+
+static void clearPci9054 (void)
+{
+	int val;
+
+	/*
+	 * Set EEPROM write-protect register to 0
+	 */
+	out_be32 ((void *)(pci9054_iobase + 0x0c),
+		  in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
+
+	/* Long Serial EEPROM Load Registers... */
+	val = PciEepromWriteLongVPD (0x00, 0xffffffff);
+	val = PciEepromWriteLongVPD (0x04, 0xffffffff);	/* other input controller */
+
+	printf ("Finished clearing PLX PCI9054 EEPROM!\n");
+}
+
+
+/* ------------------------------------------------------------------------- */
+int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
+				char * const argv[])
+{
+	if (strcmp (argv[1], "info") == 0) {
+		showPci9054 ();
+		return 0;
+	}
+
+	if (strcmp (argv[1], "update") == 0) {
+		updatePci9054 ();
+		return 0;
+	}
+
+	if (strcmp (argv[1], "clear") == 0) {
+		clearPci9054 ();
+		return 0;
+	}
+
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	pci9054, 3, 1, do_pci9054,
+	"PLX PCI9054 EEPROM access",
+	"pci9054 info - print EEPROM values\n"
+	"pci9054 update - updates EEPROM with default values"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/esd/dasa_sim/dasa_sim.c b/u-boot/board/esd/dasa_sim/dasa_sim.c
new file mode 100644
index 0000000..e7f754c
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/dasa_sim.c
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include "dasa_sim.h"
+
+/* ------------------------------------------------------------------------- */
+
+#undef FPGA_DEBUG
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* ------------------------------------------------------------------------- */
+
+/* fpga configuration data - generated by bit2inc */
+static unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+#define FPGA_PRG_SLEEP         32	/* fpga program sleep-time */
+#define LOAD_LONG(a)           a
+
+
+/******************************************************************************
+ *
+ * sysFpgaBoot - Load fpga-image into fpga
+ *
+ */
+static int fpgaBoot (void)
+{
+	int i, j, index, len;
+	unsigned char b;
+	int imageSize;
+
+	imageSize = sizeof (fpgadata);
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		index += len + 3;
+	}
+
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < imageSize - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+			&& ((fpgadata[index + 1] & 0xf0) == 0x20))
+			break;
+	}
+
+	/* enable cs1 instead of user0... */
+	*(unsigned long *) 0x50000084 &= ~0x00000002;
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
+		"NOT DONE" : "DONE");
+#endif
+
+	/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
+	*(unsigned long *) 0x50000084 &= ~0x00000400;
+	udelay (FPGA_PRG_SLEEP * 1000);
+
+	*(unsigned long *) 0x50000084 |= 0x00000400;
+	udelay (FPGA_PRG_SLEEP * 1000);
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
+		"NOT DONE" : "DONE");
+#endif
+
+	/* cs1: disable burst, disable ready */
+	*(unsigned long *) 0x50000114 &= ~0x00000300;
+
+	/* cs1: set write timing */
+	*(unsigned long *) 0x50000118 |= 0x00010900;
+
+	/* write configuration-data into fpga... */
+	for (i = index; i < imageSize; i++) {
+		b = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			*(unsigned long *) 0x30000000 =
+				((b & 0x80) == 0x80)
+				? LOAD_LONG (0x03030101)
+				: LOAD_LONG (0x02020000);
+			b <<= 1;
+		}
+	}
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
+		"NOT DONE" : "DONE");
+#endif
+
+	/* set cs1 to 32 bit data-width, disable burst, enable ready */
+	*(unsigned long *) 0x50000114 |= 0x00000202;
+	*(unsigned long *) 0x50000114 &= ~0x00000100;
+
+	/* cs1: set iop access to little endian */
+	*(unsigned long *) 0x50000114 &= ~0x00000010;
+
+	/* cs1: set read and write timing */
+	*(unsigned long *) 0x50000118 = 0x00010000;
+	*(unsigned long *) 0x5000011c = 0x00010001;
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
+		"NOT DONE" : "DONE");
+#endif
+
+	/* wait for 30 ms... */
+	udelay (30 * 1000);
+	/* check if fpga's DONE signal - correctly booted ? */
+	if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
+		return -1;
+
+	return 0;
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * Init pci regs
+	 */
+	*(unsigned long *) 0x50000304 = 0x02900007;	/* enable mem/io/master bits */
+	*(unsigned long *) 0x500001b4 = 0x00000000;	/* disable pci interrupt output enable */
+	*(unsigned long *) 0x50000354 = 0x00c05800;	/* disable emun interrupt output enable */
+	*(unsigned long *) 0x50000344 = 0x00000000;	/* disable pme interrupt output enable */
+	*(unsigned long *) 0x50000310 = 0x00000000;	/* pcibar0 */
+	*(unsigned long *) 0x50000314 = 0x00000000;	/* pcibar1 */
+	*(unsigned long *) 0x50000318 = 0x00000000;	/* pcibar2 */
+
+	return 0;
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+	int fpga;
+	unsigned short val;
+
+	puts ("Board: ");
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	fpga = fpgaBoot ();
+
+	if (!i || strncmp (str, "DASA_SIM", 8)) {
+		puts ("### No HW ID - assuming DASA_SIM");
+	}
+
+	puts (str);
+
+	if (fpga == 0) {
+		val = *(unsigned short *) 0x30000202;
+		printf (" (Id=%d Version=%d Revision=%d)",
+			(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
+
+		puts ("\nFPGA:  ");
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("%s ", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+	} else {
+		puts ("\nFPGA:  Booting failed!");
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
diff --git a/u-boot/board/esd/dasa_sim/dasa_sim.h b/u-boot/board/esd/dasa_sim/dasa_sim.h
new file mode 100644
index 0000000..5fc313a
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/dasa_sim.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/dasa_sim/eeprom.c b/u-boot/board/esd/dasa_sim/eeprom.c
new file mode 100644
index 0000000..aa6f52c
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/eeprom.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#define EEPROM_CAP              0x50000358
+#define EEPROM_DATA             0x5000035c
+
+
+unsigned int eepromReadLong(int offs)
+{
+  unsigned int value;
+  unsigned short ret;
+  int count;
+
+  out_be16((void *)EEPROM_CAP, offs);
+
+  count = 0;
+
+  for (;;)
+    {
+      count++;
+      ret = in_be16((void *)EEPROM_CAP);
+
+      if ((ret & 0x8000) != 0)
+	break;
+    }
+
+  value = in_be32((void *)EEPROM_DATA);
+
+  return value;
+}
+
+
+unsigned char eepromReadByte(int offs)
+{
+  unsigned int valueLong;
+  unsigned char *ptr;
+
+  valueLong = eepromReadLong(offs & ~3);
+  ptr = (unsigned char *)&valueLong;
+
+  return ptr[offs & 3];
+}
+
+
+void eepromWriteLong(int offs, unsigned int value)
+{
+  unsigned short ret;
+  int count;
+
+  count = 0;
+
+  out_be32((void *)EEPROM_DATA, value);
+  out_be16((void *)EEPROM_CAP, 0x8000 + offs);
+
+  for (;;)
+    {
+      count++;
+      ret = in_be16((void *)EEPROM_CAP);
+
+      if ((ret & 0x8000) == 0)
+	break;
+    }
+}
+
+
+void eepromWriteByte(int offs, unsigned char valueByte)
+{
+  unsigned int valueLong;
+  unsigned char *ptr;
+
+  valueLong = eepromReadLong(offs & ~3);
+  ptr = (unsigned char *)&valueLong;
+
+  ptr[offs & 3] = valueByte;
+
+  eepromWriteLong(offs & ~3, valueLong);
+}
+
+
+void i2c_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+  int i;
+  int len2, ptr;
+
+  /*  printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
+
+  ptr = *(short *)addr;
+
+  /*
+   * Read till lword boundary
+   */
+  len2 = 4 - (*(short *)addr & 0x0003);
+  for (i=0; i<len2; i++)
+    {
+      *buffer++ = eepromReadByte(ptr++);
+    }
+
+  /*
+   * Read all lwords
+   */
+  len2 = (len - len2) >> 2;
+  for (i=0; i<len2; i++)
+    {
+      *(unsigned int *)buffer = eepromReadLong(ptr);
+      buffer += 4;
+      ptr += 4;
+    }
+
+  /*
+   * Read last bytes
+   */
+  len2 = (*(short *)addr + len) & 0x0003;
+  for (i=0; i<len2; i++)
+    {
+      *buffer++ = eepromReadByte(ptr++);
+    }
+}
+
+void i2c_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+  int i;
+  int len2, ptr;
+
+  /*  printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
+
+  ptr = *(short *)addr;
+
+  /*
+   * Write till lword boundary
+   */
+  len2 = 4 - (*(short *)addr & 0x0003);
+  for (i=0; i<len2; i++)
+    {
+      eepromWriteByte(ptr++, *buffer++);
+    }
+
+  /*
+   * Write all lwords
+   */
+  len2 = (len - len2) >> 2;
+  for (i=0; i<len2; i++)
+    {
+      eepromWriteLong(ptr, *(unsigned int *)buffer);
+      buffer += 4;
+      ptr += 4;
+    }
+
+  /*
+   * Write last bytes
+   */
+  len2 = (*(short *)addr + len) & 0x0003;
+  for (i=0; i<len2; i++)
+    {
+      eepromWriteByte(ptr++, *buffer++);
+    }
+}
diff --git a/u-boot/board/esd/dasa_sim/flash.c b/u-boot/board/esd/dasa_sim/flash.c
new file mode 100644
index 0000000..d6a7737
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/flash.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	base_b0 = -size_b0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/dasa_sim/fpgadata.c b/u-boot/board/esd/dasa_sim/fpgadata.c
new file mode 100644
index 0000000..1106d32
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/fpgadata.c
@@ -0,0 +1,1952 @@
+  0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+  0x61,0x63,0x6d,0x30,0x30,0x30,0x35,0x64,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+  0x73,0x33,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30,
+  0x30,0x30,0x2f,0x30,0x37,0x2f,0x31,0x30,0x00,0x64,0x00,0x09,0x31,0x39,0x3a,0x32,
+  0x37,0x3a,0x33,0x38,0x00,0x65,0x00,0x00,0x79,0xaa,0xff,0x20,0x3c,0xd4,0x9f,0x5b,
+  0xff,0x7e,0xde,0xee,0xbd,0xaa,0xfe,0xbf,0x9e,0xff,0xfb,0xfe,0x5f,0xbf,0xed,0xab,
+  0xdb,0xbe,0xe5,0xfb,0xfe,0xfb,0x9f,0xeb,0xfa,0xfe,0x5f,0xb6,0xef,0xfb,0xfe,0xfe,
+  0xaf,0xff,0xff,0xff,0xfb,0xfe,0xef,0xbf,0xef,0xff,0xba,0xff,0xbb,0xfe,0xfb,0xbe,
+  0xff,0xee,0xeb,0xff,0xef,0xbb,0xef,0xff,0xbe,0xff,0xbf,0xff,0xfb,0xfe,0xff,0xbb,
+  0xff,0xe1,0xff,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,0xff,0xff,0xbc,0xff,0xbf,0xff,
+  0xfb,0xfd,0xff,0xdf,0xf7,0xff,0xff,0xbf,0xdf,0xff,0xff,0xff,0xff,0xdf,0xf7,0xfd,
+  0xff,0xff,0xfe,0x3f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xe3,0xf6,0xff,0xbf,
+  0xef,0xfb,0xfe,0xff,0xef,0xdb,0xfe,0xff,0xbf,0xef,0xe3,0xfe,0xff,0xbf,0xef,0xfb,
+  0xfe,0xfe,0x3f,0xff,0xf7,0xff,0xef,0xbb,0xe7,0xf9,0xbe,0x7f,0xbf,0xec,0xf8,0xfe,
+  0xff,0xbb,0xef,0xfb,0xbe,0x7b,0xe3,0xfb,0xbe,0xff,0xbf,0xec,0xfb,0xfe,0xff,0xbb,
+  0xee,0xfb,0xfe,0xcf,0xbf,0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x17,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0x93,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0x7f,0xff,0xf7,0xff,0xff,0xdf,
+  0xf7,0xf5,0xfd,0xff,0xdf,0xf7,0xff,0xfd,0xff,0xdf,0xf5,0xff,0x7f,0xff,0xdf,0xfd,
+  0xff,0xff,0x7f,0xd7,0xf7,0xfd,0x7f,0xdf,0xd7,0xf7,0xff,0x6f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xbf,0xfd,0xff,0xff,0xff,0xff,0xef,0xff,0xfe,0xdf,0xff,0xcd,0x7f,0xff,0xff,
+  0xff,0xff,0x4f,0xdf,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xfd,0xff,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0x7f,0xff,0xff,0xfb,0x3f,0xff,
+  0xff,0xff,0xff,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xfc,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x57,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xdf,0xff,0xfe,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,
+  0xec,0xff,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x3f,0xdf,0xf7,0xfd,0x7f,0x7f,0xcf,0xf3,
+  0xfc,0xff,0xdf,0x73,0xdd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xcf,0xf7,0xfd,0xff,
+  0x7f,0xfc,0x9f,0xff,0xef,0xbb,0xfe,0xbf,0xdf,0xef,0xbb,0xfe,0xfb,0xbf,0xef,0xfa,
+  0xee,0xff,0xff,0xfb,0xfe,0xff,0xbf,0xef,0xfa,0xee,0xff,0xbe,0xef,0xbb,0xfe,0xff,
+  0xbf,0xef,0xf7,0xeb,0xff,0xe7,0xf9,0xfe,0x7a,0x9d,0xe7,0xf9,0x7c,0x7e,0x9e,0xe7,
+  0x59,0xf6,0x7e,0x9f,0xe9,0x22,0x7f,0x9b,0xe6,0xb9,0xfe,0x4f,0x9f,0xe6,0xf9,0xfe,
+  0x7b,0x9d,0xe6,0xfe,0xfe,0x7e,0xff,0xbf,0xef,0xfb,0xee,0xff,0xbf,0xe7,0xf9,0xfe,
+  0xff,0x9f,0xef,0xfb,0xfe,0xfd,0xdf,0xfb,0xee,0xfb,0xbf,0xef,0xfb,0xee,0xf7,0xbf,
+  0xef,0xf7,0xfe,0xff,0x7f,0x5f,0x0f,0x9f,0x9b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,
+  0xfe,0x7f,0x9f,0x66,0xf9,0xfe,0x7f,0xe7,0xf9,0xee,0x77,0x9f,0xe7,0xf9,0xde,0x7d,
+  0x9d,0xe7,0xf9,0xee,0x7f,0x9f,0xed,0xc9,0xff,0xfd,0xff,0x7f,0xdf,0xfd,0xfd,0xff,
+  0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xfd,0xff,0xdf,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xfd,0xff,0x7f,0xff,0xf7,0xff,0xff,0xfc,0xb7,0xfe,0xff,0xbf,0xef,0xfa,0xfe,
+  0xff,0xbf,0xef,0xfb,0xfc,0xfd,0xbd,0x6f,0xba,0xee,0xb5,0xef,0xfb,0xfe,0xff,0xbf,
+  0xef,0xfb,0xfa,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xff,0x65,0xaf,0xdb,0xd6,0xfd,0xbf,
+  0x7f,0xdb,0xf6,0xfd,0xbf,0x6f,0xfb,0xf6,0xf9,0xae,0xf7,0xd4,0x79,0xbf,0x6f,0xdb,
+  0xb6,0x7d,0xbf,0x6f,0xdb,0xf6,0xfd,0xbd,0x6f,0xdb,0xf7,0xe8,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xe7,0xfb,0xf7,0x7c,0xfd,0xff,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0x9d,0x9e,0xff,0xff,
+  0xff,0xbf,0x7f,0xff,0xfb,0xff,0xff,0x9f,0xfe,0xff,0xff,0xff,0xfb,0xbb,0xff,0xfd,
+  0xff,0xff,0xfb,0xff,0x7f,0xdb,0xe7,0xff,0xbe,0xff,0xff,0xff,0xfb,0xfe,0xe3,0xff,
+  0xff,0xff,0xdf,0xfb,0xef,0xff,0xf7,0xfd,0xff,0xff,0xef,0xff,0xff,0xff,0xcf,0x77,
+  0xdf,0xff,0xff,0xdf,0xd7,0xff,0xff,0xff,0xff,0xdf,0xf7,0xf4,0x7f,0xff,0xff,0xfd,
+  0x7b,0xff,0xff,0xfc,0xff,0xfb,0xff,0xff,0xff,0xef,0xff,0xf7,0xff,0xbf,0xf7,0xff,
+  0x4f,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0x7f,0xff,0xfe,
+  0xfe,0xad,0xff,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,
+  0x79,0xdf,0x5d,0xff,0x7d,0xdf,0xf7,0xfc,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xff,0xed,0xff,0xbf,0xff,0xff,0x2f,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0xdb,0xff,0xfb,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+  0xff,0xff,0xf7,0xfd,0xbf,0xff,0xff,0xff,0xf7,0xfd,0xbf,0xfe,0xff,0xff,0xef,0xfb,
+  0xff,0xff,0xfe,0xfb,0xdb,0xfb,0xbf,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,
+  0xff,0xff,0xff,0xff,0xf7,0x97,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xef,0xff,0xef,0x7f,0xff,0xcf,0xdb,0xfd,0xff,0xef,0xff,0xfe,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xea,0xff,0xff,0xf7,0xff,0xfd,0xff,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xfd,0xfb,0x7d,0xf5,0xff,0x7f,0xdf,0xff,0xf7,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0xdf,0xff,0x7e,0xdf,0x7f,0xfe,0xff,0xdf,0xdf,0xff,0xff,0xff,0xdf,
+  0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,0xff,0xb3,0xff,0xe3,0xf9,0xff,0xff,0xaf,
+  0xff,0xff,0xff,0xfd,0xfd,0xfd,0xfa,0x7f,0xfd,0xab,0xfa,0x7d,0xfe,0x9f,0x7f,0xbf,
+  0xff,0xfe,0xff,0xff,0xfa,0xfe,0xbf,0xff,0xfd,0xff,0xf7,0x7f,0xfe,0xff,0xff,0xff,
+  0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xdf,0xff,0xf6,0xfe,0xdd,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0x7f,0xbf,0xff,0xee,0xfb,0xff,0xff,0xff,0xfe,0x8f,0xff,0xff,0xff,
+  0xff,0x77,0xef,0xfd,0xff,0xff,0xef,0x3f,0xfe,0xad,0x7f,0xfb,0xff,0xcf,0xf7,0xff,
+  0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xef,0x7b,0xfd,0xff,0xff,0xff,0xd1,0xff,0xff,
+  0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xfb,0xfe,0xff,0xff,0xed,0xfb,0xff,0xef,
+  0xef,0xfb,0xfe,0xff,0xdf,0xff,0xfb,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xf9,0x3f,
+  0xff,0xff,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xfe,0xff,0xd7,
+  0x7f,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,
+  0x46,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xf8,0x7e,
+  0xbf,0xff,0xff,0xfd,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe2,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xfd,0xf7,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x9f,0xf3,0xfc,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0xbf,0xff,0xfd,
+  0xff,0xff,0xbb,0xf1,0xf3,0xbf,0xff,0xff,0xf7,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbb,0xff,0xff,0xff,0xfe,0x3d,0xcd,0xff,0x7f,0xdf,0xff,0xfd,
+  0xff,0xff,0xef,0xef,0xff,0xfa,0xff,0xf7,0xfb,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xf5,0x7f,0xef,0xff,0xff,0xff,0xfb,0x5f,0xff,0xff,0xfc,
+  0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0x7f,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc3,0xff,0xff,0xfc,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xf7,0xfd,0xff,0x3f,0xf9,0xfc,0xff,0xff,0xcc,0xf5,0xff,0xcf,0xe7,
+  0xff,0xff,0x3f,0xff,0x7f,0xff,0xbf,0xff,0x29,0xaf,0xff,0xff,0xdf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x2f,0xff,0x9f,0xff,0xff,0xff,0xff,0xfc,0xef,
+  0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x5f,0x3d,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xaf,0xfb,0xca,0xff,0xfb,0x2b,0xd2,0xbf,0xff,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xef,0xa6,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xfd,0xff,0x5f,0xff,0xe5,0x7f,0x5f,
+  0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0x74,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,0xef,0x5f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xbd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0x5b,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x5f,0xff,0xfd,0xf7,0x7f,0xdf,0xff,
+  0xff,0x7f,0xdf,0xff,0xdd,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xfd,0x89,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xff,0xd2,0xc7,0xbf,0xaf,
+  0xff,0xfe,0xbf,0xaf,0xff,0xd6,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xef,0xff,
+  0xe0,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xfb,0x5f,0xdf,
+  0xf5,0xff,0xff,0xd7,0xf5,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xfd,
+  0xff,0xf2,0x6f,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xbf,
+  0x9f,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,
+  0xff,0xff,0xff,0xed,0xff,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xff,0xff,0xf8,0x1f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,
+  0xfb,0xbf,0xef,0xfb,0xfe,0xff,0xef,0xfb,0x7e,0xff,0xbf,0xef,0xfb,0xf6,0xff,0xbf,
+  0xee,0xfb,0xfe,0xff,0xb7,0xfe,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7c,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x57,0xff,0xff,0xff,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xfd,0x7f,0xff,0xd7,0xe5,0xff,0xff,0xf7,0xf5,0xff,0xfb,0xff,0xd7,
+  0xff,0xef,0x7f,0xff,0xd7,0xff,0xff,0xff,0x5f,0xfe,0x9b,0xff,0xff,0xff,0xff,0x9f,
+  0xe7,0xff,0xff,0xff,0xff,0xa7,0xff,0xfa,0x7e,0x9f,0xff,0xde,0x7e,0x9d,0xff,0xff,
+  0xfa,0x77,0xff,0xb7,0xff,0xfa,0x7f,0xff,0xff,0xe9,0xff,0xff,0x7f,0xff,0xff,0xff,
+  0xb7,0xfd,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xd7,0xff,0xef,0xdf,0xff,0xff,
+  0xdf,0xff,0x5f,0xff,0xfd,0xff,0xfb,0xff,0xff,0xff,0xfd,0x7f,0xfe,0x8f,0xff,0xff,
+  0x9f,0xe6,0xe9,0xbc,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xc2,0xf9,0xfe,0x7b,0xe7,
+  0xf9,0xfe,0x7f,0x8b,0xe7,0xf8,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x2f,0x9f,0xe1,0xff,
+  0xff,0xff,0xff,0xdf,0xf7,0xaf,0xff,0xff,0xff,0xd3,0xff,0xfd,0x7a,0xff,0xfb,0xff,
+  0x3f,0x5f,0xfb,0xff,0xff,0xff,0xff,0xf7,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,0xfd,
+  0x3f,0xff,0xff,0xff,0xfb,0xee,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xaf,0xff,0xff,
+  0x7f,0xef,0xeb,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xaf,0xff,0xff,0xff,0xff,
+  0xff,0xc7,0xff,0xff,0xff,0xff,0x77,0xdf,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xfc,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xe4,0xff,0xff,0xff,0xff,0xee,0xfb,0xdf,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xfd,0xff,0x9f,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xed,0xff,0xff,0xdf,0xff,
+  0xff,0xff,0xff,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xbf,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0x2f,0xff,0x8b,0xff,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xbf,0xa7,0xe9,
+  0xfa,0xfe,0xbf,0xa7,0xc8,0xfa,0x7f,0xa3,0xe9,0xfa,0xbe,0xbf,0xab,0xea,0xfa,0xbe,
+  0xaf,0xad,0xeb,0xfa,0xfe,0xbf,0xd5,0x7b,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfc,0xff,0xff,0xff,0xff,0x7f,0xfb,0xcd,0xff,0xfc,0xcf,0xfe,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0x47,0xff,0xff,0xfb,0xf7,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x77,0xff,0xbf,0xff,0xfd,0xff,0xef,0xbf,0xba,0xbf,0xff,0xff,0xff,
+  0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0xff,0xdf,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xaf,0xef,0xfb,0xff,0xf7,0xff,0xf6,0xff,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,0xff,0xfe,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xdf,0xf7,0x5d,0xff,0x7e,0x76,0xff,0xff,0xff,
+  0xff,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x3f,0xff,0x17,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xfd,
+  0xff,0x7f,0xf7,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xdd,0xff,0xea,0x7f,0xff,
+  0xff,0xef,0xfe,0xff,0xff,0xf7,0xff,0xff,0xfd,0xff,0xfd,0xd7,0xfd,0xff,0xf9,0xfb,
+  0xfe,0xff,0xff,0xff,0xfb,0xff,0xff,0xef,0xfd,0xff,0x7f,0xff,0xbf,0xff,0xfe,0x1f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xbe,0xff,0xff,0xef,0xff,0xbf,0xff,0xbf,
+  0x7b,0xfe,0xfd,0xaf,0xed,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xbb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xdf,0xef,0xff,
+  0x7f,0xe7,0xdf,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xf7,0xff,0xff,0xff,
+  0xff,0xf7,0x7f,0xff,0xff,0xfd,0xff,0xfe,0xff,0xff,0xff,0xff,0xbf,0x7f,0xef,0xff,
+  0xff,0x76,0xfd,0xff,0xc7,0x3f,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xc7,0xff,
+  0xff,0xdf,0xfe,0x4f,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xfe,0x7f,0xfe,0xff,0x9f,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xd5,0xff,0xdf,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xdf,0xfd,
+  0x3f,0x4f,0xff,0xfd,0xff,0xff,0xf7,0xf9,0xf7,0x7f,0xdf,0xdf,0xff,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xff,0x7f,0xf8,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0x9f,0x7f,0x7f,0xff,0xff,0xfe,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xa7,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,
+  0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x6e,0x0f,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xc1,0xb3,0xff,0xff,0x3f,0xc7,0xf1,0xfc,0xff,0xfd,0x31,0x5c,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xf2,0x5b,0xff,0x7f,0xff,0xff,0xff,
+  0xff,0xfe,0x7f,0x97,0x3f,0xff,0xf7,0xfd,0xf3,0x7c,0xaf,0xff,0x97,0xe7,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3b,0xf5,0x9b,0x7f,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbe,0xf7,0xff,0x2b,0x4a,0xdf,0xbf,0xef,0x3a,0xfe,0xed,0x6a,
+  0x6b,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xfe,0xf4,0x2d,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xed,0x73,0x5f,0xdf,0xf7,0xcf,0x5f,0xdf,
+  0xf7,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xf7,0x23,0xff,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,0xff,0xff,0xfe,0xf5,0xbd,0x7f,
+  0xfb,0xfe,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x5f,0xd8,
+  0xbf,0xf7,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xff,0xff,0x7f,0xdf,0x77,0x9d,
+  0x6f,0xdf,0x77,0xdd,0xef,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0x6b,
+  0xd9,0x37,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xf6,0xb9,0xaf,0xfb,
+  0xc6,0xff,0xaf,0xef,0xfa,0xda,0xb5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xb5,0x7e,0xf3,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xfc,0x57,0xa5,
+  0xfd,0xfb,0x7e,0xb5,0xfd,0xff,0x7f,0xd7,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xdf,0x3f,0xe8,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xbf,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x8f,0xff,0xfa,0xff,0xff,0xf9,0xff,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xfe,0xfd,0xbf,0x6f,0xfe,0xd5,0xb7,0xef,0xbb,0xf6,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xbf,0xef,0xbb,0xff,0xee,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xbf,0x6f,0xff,0xff,0xff,0xef,0xff,0xf6,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0xff,0xff,0xff,0xef,0xff,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xde,0xff,0xe5,0xf9,0x7f,0xdf,0xf7,0xfd,0x7b,0xdf,0xd7,0xf5,
+  0xeb,0x7f,0xff,0xff,0xff,0xfd,0x7f,0xff,0xd7,0xff,0xef,0xf9,0x3f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x79,0xf7,0x7e,0x9f,0xa7,0x6d,0xd3,0x77,0xa7,0xed,0xf2,
+  0x7e,0x9f,0xb7,0xff,0xff,0xff,0xff,0xa7,0x7f,0xfa,0x7f,0xff,0xff,0x33,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xfe,0xd7,0x75,0xfb,0x7f,0xdd,0xf5,0xff,
+  0x7f,0xdf,0xd7,0x7d,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xc4,0xff,
+  0xff,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x6f,0x9f,0xe2,0xf8,0xbe,0x3f,0x8f,0xe6,
+  0xbe,0x3f,0x9f,0xe2,0xf8,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xff,
+  0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x9f,0xe7,0xff,0xfc,0x7f,
+  0x1f,0xfb,0xfc,0xff,0x3f,0xff,0xf3,0xff,0xff,0xff,0xff,0xd7,0xfe,0xfd,0x7f,0xff,
+  0xff,0xe3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xfe,
+  0xff,0xbf,0xff,0x7e,0xdf,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xfa,0xff,0xdf,0xaf,
+  0xff,0xff,0xfd,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,
+  0xff,0xf7,0xfd,0xff,0xff,0xf7,0xfc,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfe,0x4f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x7f,0xdf,
+  0xf7,0xff,0xfb,0x7e,0xdf,0xfd,0xfb,0x7f,0xdf,0xff,0xed,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x7f,0xff,0xff,0xff,0xe5,0xdf,0xf4,0xff,0xdf,0xff,0xff,0xdf,0xff,0xff,0xef,
+  0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0x2b,0xc9,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0x3f,0xfe,0xeb,0xfa,0xfe,0xaf,0xaf,0xeb,0xfa,
+  0xfe,0xaf,0x25,0xe8,0xfa,0x3e,0xaf,0x2b,0xfa,0xf6,0xaf,0xab,0xeb,0xfa,0xfe,0xaf,
+  0xaf,0xea,0xfa,0xfe,0xbf,0xaf,0xeb,0xfd,0x87,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0x3f,0xff,0xf3,0xfd,0xdf,0xb7,0xff,0xff,0xdf,0xff,0x87,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x4f,0x7f,0xff,0xff,0x7f,0xff,
+  0xff,0xf7,0xff,0x6f,0xdf,0xbe,0xff,0xbb,0x56,0xdf,0xb7,0xe9,0xff,0xf3,0xf7,0x37,
+  0xff,0xff,0xdf,0xff,0xfd,0xff,0xff,0xff,0xff,0xfd,0xfa,0x5f,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x76,0xfb,0xec,0x6f,0xff,0x7f,0xff,0xf5,0x7f,0xee,0xdf,0xf7,
+  0xfb,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf1,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xfd,0xdf,0xff,0xed,0xff,0xef,0xde,0xf7,0xfe,0xff,0xea,0x7f,0xde,
+  0x8f,0xab,0xff,0x3f,0xff,0x7f,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfc,0x7f,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xbf,0xbf,0xdf,0xfd,0xdb,
+  0xff,0xa7,0xfa,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xdf,0xfe,0x47,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xef,0xef,0xff,0xfe,0xfb,0xfc,0xaf,0xbb,
+  0x8b,0xde,0x1f,0xbb,0xee,0xfd,0x7f,0xff,0xaf,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xe5,0xff,0xff,0xff,0xfe,0x2f,0xff,0xfe,0xff,0xff,0xff,0xfb,0xf6,0xfc,0xbb,0xef,
+  0xcf,0xf7,0xbf,0xff,0xcb,0xf2,0xff,0xff,0xff,0xcf,0xff,0xfd,0xf7,0xff,0xff,0xff,
+  0x7f,0xf8,0xbf,0xff,0xf7,0xff,0xfb,0xff,0xff,0xff,0xfd,0x7f,0x7f,0xd6,0xf5,0xec,
+  0xfe,0x5e,0xcc,0x75,0x7d,0xdb,0xdf,0xbf,0xff,0xff,0xfe,0xff,0xff,0xef,0x7f,0xff,
+  0xfb,0xff,0xff,0xe7,0x7f,0xff,0xff,0xdc,0xff,0xff,0xff,0xf1,0xfe,0xff,0xf7,0xaf,
+  0xf7,0xca,0xfe,0x7f,0xdb,0xf9,0xff,0xbf,0xdf,0xf1,0xfd,0x7f,0xfd,0xcf,0xff,0xff,
+  0xff,0xff,0x7f,0xff,0xe4,0xef,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xdf,0xf3,0xfe,
+  0xfd,0xfe,0xff,0xdf,0xef,0x59,0x7f,0x3b,0xf7,0xe3,0xef,0xbf,0xff,0xff,0xfe,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xfd,0x9f,0x7f,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,
+  0xeb,0xff,0xcf,0xb3,0xed,0xeb,0x7f,0xff,0xbf,0xfb,0xff,0xef,0xd7,0xff,0xff,0xfd,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xb9,0xf5,0xff,0xff,0xfe,0xaf,0xff,0xff,0xff,
+  0xff,0xff,0xf9,0xe3,0xf8,0xfe,0x3e,0x8f,0xda,0xda,0x96,0xad,0xeb,0xfe,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xea,0x7d,0xff,0xef,0xff,0xdf,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0xff,0xff,0xbf,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x41,0xff,0xff,0xfc,0xff,0x3f,
+  0xff,0xff,0xfc,0xfb,0xff,0xcf,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xdf,0xf9,0xff,
+  0xef,0xff,0xff,0xff,0xf1,0xff,0xff,0xff,0xf9,0xf3,0xff,0x1d,0xaf,0xff,0xff,0xdf,
+  0xef,0xff,0xf3,0xfc,0xcf,0x7f,0xfd,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,
+  0x3f,0xfd,0xff,0xff,0xff,0xfe,0xff,0xff,0x3b,0xff,0xaf,0xff,0x5f,0x35,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbf,0xef,0xef,0xfb,0xf5,0x79,0xdf,0x37,0xcd,0xff,0xdf,0x57,
+  0xd5,0xff,0x7f,0xbf,0xff,0xff,0xff,0xff,0xff,0xfb,0xd2,0xff,0xef,0xef,0x86,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0xfd,0xf3,0x7e,0xff,0x9f,0xe7,0xf9,0xfe,0xff,
+  0xe7,0xf9,0xfe,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x5f,0xff,0xff,0x60,
+  0x3f,0xb7,0xff,0xff,0xaf,0xff,0xfe,0xff,0xbf,0xbf,0xfb,0xa7,0xed,0xf5,0x7f,0x5f,
+  0xef,0xf7,0xfd,0x5f,0x47,0xfe,0xff,0xff,0xeb,0xff,0xfe,0xbf,0xef,0x5f,0xff,0xff,
+  0xfd,0x5b,0xff,0xff,0xff,0xf5,0x7f,0xff,0x77,0xdd,0xa7,0x7d,0xda,0xff,0xbe,0xff,
+  0xff,0xff,0xfe,0xff,0xbb,0xee,0xff,0xdd,0xff,0xfd,0x5f,0xff,0xd5,0xf7,0x6b,0xdf,
+  0xff,0xfd,0x8b,0x7f,0xff,0xff,0xfe,0xbf,0xff,0xfb,0xfe,0xde,0xff,0xaf,0x77,0xed,
+  0xff,0x7d,0xdc,0x7d,0xff,0x7e,0xdf,0xb7,0xfb,0xff,0xff,0xaf,0xff,0xfa,0xff,0xbf,
+  0xaf,0xff,0x7f,0xec,0x7f,0xff,0xff,0xff,0xd7,0xff,0xfd,0xff,0x7f,0xdf,0xf7,0xc7,
+  0xff,0xff,0xff,0x1f,0xeb,0xfc,0xff,0xff,0xff,0xff,0x7f,0xff,0xf5,0xff,0xff,0x5f,
+  0xdf,0xf5,0xff,0xff,0xfe,0x87,0xfb,0x7f,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xe7,
+  0xfb,0x6f,0xfb,0xbe,0xe7,0xbf,0xfb,0xb6,0xef,0xbb,0xee,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xd1,0xff,0x9f,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,
+  0xfe,0xff,0xff,0x6f,0xfa,0xf6,0xfd,0xff,0xfb,0xfe,0xbf,0x8f,0x63,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0x1f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xb3,
+  0xef,0xfb,0xb6,0xfd,0xbc,0x6f,0x1b,0xb6,0xfd,0xee,0xdb,0xe6,0xfd,0xbf,0xef,0xfb,
+  0xfe,0xdf,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xfe,0xa7,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xfb,0xf7,0xff,0x7f,0xf3,0xfc,0xfd,0xbf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x78,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf7,0xbd,0xef,0xfb,0xff,0xbb,0xee,0xfb,0xbe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x1f,0xff,0xff,0xff,
+  0xfd,0xff,0xff,0x5f,0xd7,0xf5,0xef,0x7f,0xff,0xff,0xff,0xef,0xfb,0xff,0xbf,0xff,
+  0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x8b,0xff,0xff,
+  0xff,0xff,0x9f,0xff,0xe9,0xf2,0x7e,0x9f,0xa7,0xfe,0x9f,0xbf,0xeb,0xfa,0xff,0xbf,
+  0xef,0xfb,0x7e,0xb6,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0x7f,
+  0xff,0xff,0xff,0xf7,0x7f,0xfb,0xff,0x5f,0xff,0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xbf,0xff,0xff,0xde,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xfe,
+  0x67,0xff,0xff,0x9f,0xe6,0xf1,0xfe,0x7f,0x8b,0xe7,0xf9,0xbe,0x7f,0x9f,0xe7,0xf9,
+  0xfe,0x7f,0xe7,0xf9,0xfe,0x7f,0x9b,0xe7,0xf9,0xfe,0x7f,0x9f,0xc7,0xf9,0xfe,0x7f,
+  0x9f,0xe9,0xff,0xff,0xff,0xff,0xde,0xbf,0xf5,0xff,0xbf,0x4f,0xf1,0xfe,0xff,0xff,
+  0xe7,0xf9,0xff,0x9f,0xef,0xff,0xff,0xff,0x3f,0xef,0xff,0xff,0xff,0xfa,0xff,0xff,
+  0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0xfb,0xff,0xfe,0xbf,0xf7,0xe9,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x57,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfb,0xff,0xff,0xff,0xff,0xef,0xff,0xbf,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xc4,0xff,0xff,0xff,0xff,0xef,0x7f,0xff,0xff,0xdf,0xf7,
+  0xfd,0xff,0xdf,0xf7,0xfd,0xff,0x7f,0xf7,0xfd,0xff,0x7f,0xdf,0x9f,0xf7,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xdc,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xf5,0xef,0x7b,0xdf,0xf2,0xfc,0xbf,0xcb,0xf2,0xfd,0x2f,0x7f,0xf2,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,
+  0xbf,0xaf,0xea,0xda,0xbc,0x97,0xab,0x6a,0xda,0xb5,0xab,0x69,0xda,0x76,0xaf,0x2f,
+  0xea,0xfa,0xfe,0xb7,0xaf,0xeb,0xfa,0xfe,0xaf,0xf5,0x7f,0xff,0xff,0xcf,0xff,0xff,
+  0xff,0xff,0xcf,0xee,0xfe,0xfa,0x3f,0xbd,0xfd,0x7f,0xff,0xfd,0xf3,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x07,0xff,0xff,0xeb,0xf7,
+  0xf7,0xff,0xff,0xab,0xff,0xfc,0xcb,0xe6,0xbd,0xf7,0xef,0xfb,0x7f,0xb5,0xe5,0xfd,
+  0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0x89,0x7f,0xff,0xff,
+  0xff,0xf7,0xbf,0xcf,0xff,0xdf,0xf7,0xbf,0xe7,0xeb,0xf6,0xfb,0xff,0xb7,0xef,0xdf,
+  0xff,0x7e,0x7b,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x1f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x8f,0xdf,0xfe,0xf6,0xbf,0xaf,0x49,0xba,0x7b,0xa7,
+  0x89,0xda,0xfd,0xb7,0xf7,0xdf,0xff,0xff,0xfb,0xff,0x7f,0xff,0xff,0xff,0xff,0xe7,
+  0xff,0x7f,0xff,0x7f,0xff,0xfb,0xff,0xfb,0xff,0xff,0x7b,0xd7,0xd5,0xfd,0x7a,0x5b,
+  0x95,0xed,0x5d,0x5f,0xef,0xff,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xff,0xff,0xfe,0xff,
+  0xec,0x7f,0xff,0xff,0xff,0xfe,0xff,0xfe,0xff,0xfc,0xfe,0xf3,0xfc,0xdf,0x3b,0xce,
+  0xf3,0xfb,0x3f,0xce,0xf3,0xff,0xef,0xfb,0xfd,0xfd,0x7f,0xff,0xf7,0xff,0xff,0xbf,
+  0xff,0xfd,0x5f,0xff,0xff,0xff,0xff,0xff,0xcf,0x5b,0xfe,0xef,0xfd,0x7f,0x5f,0xd3,
+  0xf6,0xfd,0xb7,0x5b,0xd6,0xfd,0xbf,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0xff,0xe2,0xff,0xff,0x7f,0xff,0xff,0xff,0xfd,0xff,0xcf,0xff,0xff,0xff,
+  0xdf,0xd6,0xed,0xef,0x46,0xd7,0xb7,0xbf,0xfe,0xff,0xdf,0xfe,0xff,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xfe,0x7e,0xff,0xff,0xfd,0xff,0xff,0xde,0xff,0xbf,0xfc,0xff,
+  0xf9,0x7e,0x7f,0xbf,0xee,0xdd,0x3d,0xc7,0xf3,0xfb,0xf6,0x1f,0x3f,0xcf,0xdb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xae,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0xd7,
+  0xf9,0xf5,0xff,0xef,0xff,0xff,0xf7,0xbb,0xfd,0xfe,0xdf,0xff,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,
+  0xbf,0xec,0xff,0x7f,0xcb,0xf2,0xfc,0xbf,0x3e,0xf3,0xfe,0xbe,0xa5,0xe7,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x1f,0xff,0xff,0xff,0xff,0xdf,0xf7,
+  0xfd,0xff,0xff,0xde,0xf6,0xbf,0xad,0xeb,0x6a,0xff,0x2d,0x6b,0x7a,0xff,0xb7,0xff,
+  0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x77,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xaf,0x7f,0xde,0xbf,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+  0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0x3f,0xff,0x1f,0xd7,
+  0xff,0xff,0xff,0x3e,0xdf,0xf7,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7f,0x3f,0xcf,0xff,0x3c,0x7f,0x3f,0xff,0xff,0xff,0xff,0xff,0xf1,0x5a,0xff,0xf7,
+  0xff,0xff,0xfc,0xef,0xef,0xdf,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,0xff,0xff,0x3f,
+  0xff,0xf9,0xff,0xcb,0xff,0xe7,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xf5,0xe3,0xdf,
+  0xff,0xff,0xf2,0xbf,0xef,0xff,0xfb,0xff,0xf1,0xd6,0x75,0xfd,0x67,0x5f,0xd6,0x7d,
+  0x67,0x5d,0x57,0xfe,0xfe,0xe6,0xbf,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf6,
+  0x6f,0xff,0xff,0xff,0xd7,0xf7,0xff,0xff,0x7f,0xff,0x3f,0x7f,0xd3,0xf4,0xfb,0x3f,
+  0x7f,0xff,0xfb,0xbf,0x7f,0xff,0x7c,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf6,0xcf,0xff,0xff,0xff,0xff,0xff,0xbb,0x2f,0xef,0xff,0xff,0xfb,0x7c,0xdf,0xff,
+  0xd5,0xfb,0x7e,0xb7,0xf1,0xff,0xff,0xfb,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xcd,0xbf,0xff,0xff,0xff,0xf7,0xdd,0xf5,0x7d,0xdf,0xf7,0xff,0xef,0xbb,
+  0xfa,0xfb,0xff,0xef,0xfe,0xfd,0xbf,0xaf,0x7d,0xdc,0xf7,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xde,0x1f,0xff,0xfd,0xfd,0x4b,0xfe,0xfe,0xb7,0xbe,0x7f,0x55,0xf1,
+  0x76,0xdd,0xf7,0xfd,0xf1,0xde,0x37,0x7d,0xff,0xff,0xed,0x0b,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0x17,0xff,0xff,0x1f,0xcd,0x7f,0x7f,0xd7,0xf7,0xef,0xfb,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xf7,0xe9,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xea,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xff,0xbb,0xfe,0xff,0xbb,0xee,0x7b,0xef,0xbb,0x6e,0xfb,0xbf,0xff,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xff,0xff,0xff,0xff,0x7d,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xfd,0xaf,0xef,0xdf,0xfd,0xbf,0x6b,0xd8,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xbf,0xff,0xff,0xff,0xff,0xfd,0xc0,0xff,0xfb,0xfe,0xff,0xbf,0xef,
+  0xfb,0x7e,0xff,0xb7,0x6f,0xdb,0xd6,0xf1,0xbb,0xef,0xde,0xed,0xbe,0x6f,0xfb,0xfe,
+  0xdf,0xbf,0x6f,0xfb,0xee,0xff,0xbf,0xef,0xfb,0xf7,0xe5,0x6f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0xfe,0xff,0xbf,0xef,0xf7,0xff,0x3f,0xcf,0xff,
+  0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xf7,0xcf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0x7b,0xde,0xef,0xbf,0xfb,0xbe,0xef,
+  0xbf,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xe9,0x7f,0xbf,
+  0xff,0xff,0xff,0xff,0xf5,0xfd,0x7f,0x5f,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xfb,
+  0xff,0xff,0xad,0xf9,0x7f,0x5f,0xf7,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0x37,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0x9f,0xa7,0xe9,0xff,0xaf,0xef,0xfa,0xfe,0xff,0xaf,
+  0xfa,0xfe,0x9f,0xaf,0x9d,0xa7,0xe9,0xfb,0x7e,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x27,0xff,0xff,0xff,0xff,0xff,0xff,0xd7,0xf5,0xe9,0x7f,0xff,0xff,0xff,0xef,0xfb,
+  0xfd,0xff,0xdf,0xff,0xff,0xf7,0xf5,0xfd,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xf9,0xfe,0x7f,0x9f,0xe2,0xf8,0xbe,0x2f,0x9f,0xe7,0xf9,0xfe,
+  0x7f,0x9f,0xe7,0xfe,0x7f,0x9f,0xe6,0xf8,0xbe,0x2f,0x8f,0xe7,0xf9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xfe,0x57,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xfb,0xfe,0xff,0x9f,0xef,
+  0xfb,0xfe,0xff,0x9f,0xfb,0xfe,0xff,0xbf,0xcf,0xf9,0xff,0xff,0x7f,0x5f,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,
+  0xfd,0xff,0x7f,0xff,0xff,0xff,0x7f,0xdf,0xf7,0xfb,0xff,0xff,0xff,0xbf,0xeb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,0x3f,0xff,0xff,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xaf,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xfd,
+  0xff,0x7f,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0x7f,0xdf,0xf7,0xe7,0xfd,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7c,0x8f,0xfb,0xfa,0xf2,0xff,0xbf,0x2f,0xfa,0xfc,0xbf,0xef,0xca,0xff,0xff,0xff,
+  0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xdf,0xef,0xf3,0x2f,0xff,0xeb,0xfa,0xfe,0x9f,
+  0xa7,0xeb,0xfa,0xde,0xbf,0xae,0xca,0xfa,0x6c,0x1f,0xaf,0x38,0xbe,0xbb,0xa3,0xe8,
+  0xfa,0x3e,0x9f,0xaf,0xeb,0x7a,0xbe,0xbf,0xab,0xeb,0xff,0x56,0x7f,0xf3,0xff,0xff,
+  0xfd,0xfb,0xff,0xfb,0xff,0x3e,0x57,0xfb,0xf5,0xdf,0xaf,0x7f,0xff,0xfd,0xff,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x7f,0xff,0xff,
+  0xff,0x7f,0xbf,0xf7,0xed,0xda,0xff,0x7f,0xdb,0xdf,0xff,0x37,0x7f,0xef,0xff,0xff,
+  0xbd,0xff,0xfd,0xf7,0xf8,0xbf,0xeb,0xff,0xff,0xff,0xdf,0xff,0xdd,0xfa,0x9f,0xff,
+  0x5f,0xff,0xff,0xff,0xef,0xfa,0xff,0x35,0xba,0xff,0xff,0xef,0xff,0xfb,0xba,0x7f,
+  0x6e,0xeb,0xbf,0xdb,0xfb,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x8b,
+  0xff,0xff,0xff,0xef,0xfd,0xf7,0x69,0xfb,0xfe,0x5f,0xa7,0xcb,0xfa,0xf6,0xb5,0xa7,
+  0xfa,0xfe,0xbf,0xaf,0x3d,0xdf,0xb6,0x3f,0xfe,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,
+  0xac,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0x79,0xee,0xff,0x95,0xad,0x7d,0x5d,0xd5,
+  0xdd,0xf5,0xde,0xf6,0xfd,0xbf,0xff,0xff,0x5f,0xdf,0xf7,0xff,0xf7,0x7f,0xff,0xff,
+  0xff,0xfe,0x8f,0xff,0xfd,0xff,0xff,0xef,0xff,0x8e,0xf3,0x6c,0xff,0xb7,0xee,0x7b,
+  0xee,0xee,0xbb,0x8b,0xbb,0xf6,0xbf,0xce,0xff,0xff,0xfd,0xf7,0xfe,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0x99,0xff,0x7f,0xff,0xff,0xff,0xff,0xf5,0xfd,0x7f,0x4f,0x9e,0xf6,
+  0xfd,0xff,0x6f,0xdb,0xf4,0x3f,0x4f,0xaf,0xfe,0xff,0xe7,0xef,0x7f,0xbf,0xff,0xff,
+  0xff,0xff,0xff,0x7f,0xfe,0x3f,0xff,0xff,0xff,0xfe,0xff,0xdf,0xfe,0xff,0xff,0x7e,
+  0x3f,0x95,0x65,0xd9,0x7e,0x3e,0xfe,0x7f,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,
+  0xff,0x7f,0xff,0xff,0xff,0xff,0x25,0xff,0xff,0xff,0xdf,0xff,0xff,0xcc,0xc3,0x38,
+  0xf7,0x38,0x4f,0x73,0xdc,0xff,0xbd,0x9e,0xf8,0x3e,0xff,0xff,0x73,0xdf,0xff,0x3d,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,
+  0xb7,0xef,0xbb,0x76,0xff,0xbf,0x9f,0xfd,0xfb,0xff,0xef,0xff,0xdf,0xfe,0xaf,0xff,
+  0xe6,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfc,0xd5,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0x9f,0xa7,0xe8,0xde,0x77,0x8c,0xe5,0x9d,0xfb,0x63,0xf7,0xfd,0x1b,0xbe,0xda,0xff,
+  0xbe,0xef,0xff,0xf7,0x7f,0xff,0xff,0xff,0xff,0xff,0x21,0xff,0xff,0xdf,0xff,0xff,
+  0xfb,0xe9,0xea,0xfe,0xb7,0xaf,0xeb,0x72,0x7e,0xbf,0xaf,0xfe,0xe7,0xbf,0xfd,0xfb,
+  0xff,0xdf,0xe7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xf0,0x7f,0xff,0xff,0xff,
+  0xbf,0xff,0xfd,0xdf,0x77,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0x5e,0xd7,0xff,
+  0xfc,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,
+  0xff,0xff,0x3f,0xd9,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xff,0xfc,0x7f,
+  0xff,0xcf,0xff,0xfc,0xfb,0x3f,0xcf,0xff,0x3f,0xff,0xfe,0xff,0xff,0xff,0x31,0xaf,
+  0xff,0xff,0xff,0xf6,0xbf,0x3f,0xe7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,0x9f,
+  0xef,0x7e,0xbd,0xff,0xff,0xdf,0x77,0xcb,0xff,0xbf,0xff,0xff,0xdf,0xff,0xff,0x5a,
+  0x3d,0xff,0xff,0xff,0xff,0xff,0xc7,0x79,0xdf,0xf7,0x9d,0xf3,0x7f,0xde,0x75,0xfd,
+  0x75,0xbb,0x3f,0x1f,0xf3,0xf5,0x2f,0xef,0x7e,0xe6,0xbf,0xff,0xff,0xfb,0xff,0xff,
+  0xef,0xa6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xe7,0xf3,0xfe,0x7f,0x3f,0xcf,
+  0xf3,0xef,0xf7,0xcd,0xff,0x7e,0x77,0xb5,0xfd,0xff,0x7e,0x57,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0x6c,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xfb,0x7e,0xdf,0xff,0xf5,
+  0xfd,0x7b,0x5f,0x57,0xbf,0xff,0xf9,0xf7,0x71,0xff,0xbf,0xfb,0xff,0xff,0xff,0xff,
+  0xef,0xff,0xff,0x7f,0x9b,0xff,0xff,0xff,0xff,0xff,0xdf,0xfb,0xff,0xef,0xfb,0xff,
+  0xff,0xbf,0xef,0xdb,0xee,0xdd,0xa7,0x6b,0x38,0xef,0xbd,0xf7,0x7d,0xdf,0xf7,0xff,
+  0xff,0xfd,0xdf,0xff,0xfd,0x89,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xfd,0xfb,0x7e,
+  0xdf,0xf7,0xcd,0xfb,0x7d,0xdf,0xba,0xfe,0xbf,0xff,0xff,0xea,0xde,0xff,0xef,0xeb,
+  0xdf,0xff,0xff,0xbf,0xff,0xff,0xe2,0x7f,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xfc,0xff,0x8f,0xff,0x7e,0xd7,0xff,0xeb,0xff,0x5f,0xdf,0xf7,
+  0xfd,0x79,0xff,0xff,0xf7,0xff,0xff,0xf7,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xee,
+  0x7b,0xfe,0xff,0xbf,0xef,0xfb,0xbe,0xe7,0xbf,0xff,0xaf,0xff,0xdf,0xf7,0xff,0xff,
+  0xff,0xf9,0xff,0xbf,0xff,0xff,0xff,0xff,0xfe,0xed,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe7,0xdf,0xf6,0xfd,0xff,0x7f,0xda,0xf6,0xff,0xff,0xfe,0xfe,0xff,0xff,0xe7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x1f,0xff,0xbf,0xef,0xfb,
+  0xfe,0xdd,0xbf,0xef,0xdb,0xee,0xfd,0xbd,0x6f,0x1b,0xbe,0xfd,0xef,0xfb,0xe6,0x5f,
+  0x9f,0xef,0xfb,0xfe,0xdf,0xbf,0xef,0xfb,0xfe,0xdf,0xbf,0xfe,0x66,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x7f,0xff,0xf7,0xff,0xfd,0xff,0xef,0xfb,0xfe,0xff,0x3f,0xfb,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x72,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xf7,0xbd,0xef,0xbb,0xdf,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x97,
+  0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xf5,0xff,0x9f,0xef,0xd7,0xfd,0xed,0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xcb,0xff,0xff,0xff,0xfe,0x9f,0xff,0x7e,0xff,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,
+  0xfb,0xfa,0x7e,0x9f,0xff,0xff,0xfa,0x7f,0x9f,0x27,0xe9,0xdf,0xff,0xff,0xff,0xff,
+  0xff,0xfc,0x7f,0xff,0xff,0xff,0xd7,0xff,0xdf,0xfb,0xff,0xff,0xff,0xff,0xff,0xfc,
+  0xff,0x7f,0xef,0xde,0xb7,0xbf,0xff,0x7a,0x5f,0xb7,0xff,0xfd,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x6f,0xff,0xff,0x9f,0xe2,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,
+  0x9f,0xe7,0xf9,0xfe,0x6f,0xe7,0xf9,0xde,0x6f,0x0b,0xe6,0xe9,0xfe,0x2f,0x9f,0xe7,
+  0xf9,0xfe,0x7f,0x9f,0xd5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,
+  0xfe,0x7f,0x9f,0xef,0xfb,0xff,0x1f,0xcf,0xd9,0xf5,0xfb,0xbf,0xdf,0xd3,0xfe,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xfd,0xfe,0xfe,0xbf,0xf7,0xfb,0xaa,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x17,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0x7f,0x7f,0xff,0xbf,0xff,0x7f,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,
+  0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xf9,0xff,0xf7,0xdf,
+  0xe6,0xfd,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0xfc,0xdf,0xff,0xff,0xff,0xff,0xbf,
+  0xef,0xab,0xeb,0xfa,0xfe,0xbf,0xaf,0xe9,0xfa,0xfe,0xaf,0xdb,0xd7,0xf5,0xff,0x2f,
+  0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0xfc,0x9f,0xff,0xff,0xba,0xff,0xfe,0xbf,0xaf,
+  0xe9,0xfa,0x7e,0x0f,0xa3,0xe8,0xfa,0xfe,0xb7,0xab,0xeb,0xfa,0xf7,0xaf,0x63,0xfa,
+  0x76,0xaf,0xab,0xea,0xfa,0xbe,0xbf,0xab,0xea,0xfa,0xfe,0xbf,0x5f,0x7f,0xef,0xed,
+  0xff,0xf3,0xef,0x7f,0xff,0xfb,0xfd,0xff,0xdf,0xef,0xf5,0xff,0x6f,0x7f,0x3f,0xff,
+  0xba,0xff,0x33,0xcf,0xf3,0x7d,0xbf,0xdc,0xff,0xff,0xfb,0xff,0xff,0xde,0xa7,0xff,
+  0xff,0xdf,0xb2,0xff,0xfa,0xff,0xff,0xf7,0x7d,0xff,0x7d,0xbf,0x77,0xff,0xf7,0x7e,
+  0xdf,0xf4,0xdf,0x5e,0xcf,0xff,0xfd,0xff,0xff,0x7f,0x7f,0xfd,0xff,0xff,0x7f,0x85,
+  0x5f,0xff,0xff,0xff,0xff,0xfe,0xff,0xbb,0xff,0xff,0xfe,0xef,0xfb,0xfe,0xff,0xbb,
+  0xf3,0xaf,0xff,0xfb,0x6b,0xfa,0xfe,0x5f,0xb7,0xef,0xdb,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0x3f,0xff,0xfd,0xf7,0xf8,0xd7,0x76,0x9d,0xa6,0x4b,0xda,0x76,0x9d,0xa7,0x69,
+  0xda,0xdb,0xbf,0xad,0xfa,0xfe,0xb7,0xa7,0x7d,0xff,0x7e,0x3f,0xff,0x3f,0xff,0xff,
+  0xff,0xff,0xc7,0xff,0x7f,0xff,0xf5,0xdf,0xff,0xa7,0xd9,0xfe,0x7e,0x9f,0x67,0xd9,
+  0xf6,0x7f,0x9f,0xde,0xbf,0x7f,0xeb,0x7b,0x7e,0x57,0xfd,0xff,0x5f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xff,0xfe,0xff,0xfe,0xef,0xab,0xef,0xfa,0xfe,
+  0x3f,0xbf,0xef,0xfe,0xfb,0xb9,0xe9,0xa8,0xfa,0xfe,0xbf,0xee,0xfb,0xfe,0xff,0xfb,
+  0xef,0xff,0x7f,0xff,0xed,0x9f,0xef,0xfd,0xfb,0xde,0x7d,0x3f,0x6f,0xdb,0xe6,0xfd,
+  0xbf,0x7f,0xdb,0xd6,0xf9,0x3d,0x6b,0xfb,0xfe,0xff,0xbb,0xee,0xfa,0xfe,0xbf,0xb7,
+  0xfb,0xf5,0xff,0xff,0xff,0xff,0xbb,0xbf,0xff,0xff,0xfb,0xfb,0xfd,0xf9,0x9e,0x77,
+  0x9f,0xe3,0xf9,0xde,0x57,0x9d,0xfe,0xef,0xef,0xf6,0xff,0x5f,0xdf,0x9f,0xff,0x7f,
+  0x7f,0xff,0xf7,0xdf,0xff,0xff,0xff,0xf3,0x7f,0xff,0xff,0x7c,0xcd,0xff,0xfd,0xf7,
+  0xf8,0xd7,0xf1,0x9f,0xe7,0x1f,0xc7,0xfe,0xf5,0x3f,0xcf,0x71,0xdc,0x36,0x3d,0x8f,
+  0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x8f,0xff,0xff,0xef,0xfa,0xff,0xff,
+  0xbd,0xff,0xff,0xd7,0xbf,0xff,0xfd,0xfe,0xfb,0xff,0xbb,0x5e,0xff,0xdf,0xf7,0xfb,
+  0xfe,0xff,0xf7,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xc1,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xfd,0x7f,0x36,0xdd,0xf7,0x3c,0xcf,0x7b,0xda,0xff,0xfa,0x7e,0x9c,0xb3,0x3d,
+  0xbe,0x7d,0x9f,0xf7,0xed,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x9f,0xff,0xff,0xff,
+  0xfe,0x7a,0x5e,0xbf,0x2f,0xeb,0xaa,0xdc,0xbf,0xae,0xab,0xff,0xff,0xaf,0xab,0x7a,
+  0xdc,0xbf,0xad,0xeb,0x7a,0xfe,0xb7,0xff,0xff,0xff,0xff,0xff,0xfa,0x67,0xdf,0xff,
+  0xff,0xff,0xff,0x7f,0xdf,0xf7,0xfd,0xf7,0x77,0xdf,0xf7,0xfd,0xff,0xff,0xf7,0xf9,
+  0xdf,0x7f,0xdf,0x77,0xfd,0xff,0x7f,0xdf,0xef,0xbf,0xff,0xff,0xff,0xff,0xe8,0xbf,
+  0xff,0xff,0xff,0xfe,0x7f,0xff,0xdf,0xfc,0xfd,0xff,0xd7,0xff,0xff,0xff,0xed,0x9f,
+  0xf7,0xff,0xff,0xff,0xdf,0xff,0xfd,0xff,0x9f,0xff,0xff,0xff,0xfd,0xff,0xff,0xf1,
+  0xca,0xff,0xff,0xff,0xff,0xab,0xff,0xff,0xff,0x9f,0xff,0xf9,0xfe,0x7f,0xff,0xfd,
+  0xe3,0xff,0xff,0xcf,0xf3,0xff,0xff,0xff,0xff,0xfa,0xff,0xce,0xff,0xff,0xff,0xff,
+  0xf5,0xab,0xdf,0xff,0xff,0xff,0xfc,0xd6,0x75,0x9d,0x7f,0x59,0xd7,0x35,0xfd,0xe7,
+  0x79,0xaf,0x5d,0xf5,0x7c,0xd7,0x55,0xd5,0xff,0x7d,0x57,0xf5,0xfe,0xff,0xff,0xff,
+  0xff,0xfe,0xf0,0x6f,0xff,0xff,0xff,0xff,0x9f,0x7f,0xd3,0xfe,0xfb,0x3f,0xe7,0xf9,
+  0xfc,0xff,0x35,0xe7,0xfe,0x7f,0xbe,0xe7,0xbb,0xfe,0xff,0x3f,0x6f,0xbf,0x7f,0xff,
+  0xff,0xff,0xff,0xf7,0x47,0xff,0xff,0xff,0xff,0xff,0xf5,0x7f,0xde,0xe7,0xd5,0xe3,
+  0x7a,0xdf,0xff,0xfc,0xbf,0x7f,0xff,0xf9,0xff,0x7c,0x9f,0xef,0xcd,0xf6,0x7f,0xfb,
+  0xf2,0xff,0xff,0xff,0xff,0xd1,0xbf,0xff,0xff,0xff,0xf7,0xfe,0xff,0xe3,0xf4,0xfa,
+  0xbe,0xff,0xff,0xfe,0xfd,0x1d,0x4f,0xfa,0xfd,0x3f,0x4f,0xab,0xfa,0xfb,0xbe,0x4f,
+  0xe9,0xdc,0x57,0xff,0xff,0xff,0xd8,0x9f,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,
+  0x77,0xfd,0xf7,0x7d,0xdf,0xb7,0xd2,0xf7,0xdf,0xf7,0x7d,0xff,0x7f,0xdf,0xf7,0xc5,
+  0xf7,0x77,0xef,0xab,0xff,0xf5,0xfd,0x7e,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe7,0xff,0xfe,0x7f,0x1f,0xff,0xf3,0x5e,0x7f,0xff,0xfa,0xff,0xff,0xff,0xeb,
+  0xfb,0xfe,0x7f,0xf7,0xfd,0x7f,0xff,0xff,0xff,0xe6,0x5f,0xff,0xff,0xff,0xff,0xfb,
+  0x9e,0xe7,0xbe,0xee,0xdb,0xee,0xff,0xbb,0xee,0x7f,0xef,0xbf,0xee,0xfb,0xbe,0xef,
+  0xb9,0xef,0xbb,0xee,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0x1b,0xff,0xff,0xff,0xff,
+  0xff,0xf9,0xf6,0x7d,0xff,0xef,0xff,0xf7,0xfd,0xaf,0x6f,0xf9,0xfd,0xff,0x6b,0xd8,
+  0xfe,0x3d,0xff,0xef,0xff,0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xb1,0xff,0xfb,0xfe,
+  0xff,0xbf,0x6f,0xdb,0xfe,0xfd,0xbb,0x6f,0xdb,0xd6,0xf1,0xbb,0x6f,0xfe,0xfd,0xbe,
+  0x6f,0xdb,0xf6,0xfd,0xbe,0x6f,0xdb,0xee,0xff,0xbf,0xef,0xfb,0xff,0xe5,0x6f,0xff,
+  0xff,0xff,0xff,0xdf,0xf7,0xff,0xff,0x7f,0x6f,0xdf,0xfe,0xff,0xbf,0x6f,0xff,0xff,
+  0x3f,0xcf,0xdb,0xfd,0xfd,0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x8f,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0xfb,0xfe,0xf7,0xbf,0xef,0x7b,0xde,0xfb,0xff,
+  0xfb,0xbe,0xef,0xbb,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xf5,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
+  0xff,0xeb,0xbf,0xfc,0x9f,0xff,0xe9,0xff,0xbf,0xeb,0xfa,0x7e,0xff,0xbf,0xeb,0xfa,
+  0x7e,0xba,0x7f,0xfa,0xfe,0x9f,0xaf,0xed,0xfa,0xfe,0xff,0xbf,0xeb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xb3,0xff,0xd7,0xff,0xfd,0x7f,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0xdd,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xf8,0xff,0xfa,0xf9,0xfe,0x2f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xfe,0x7f,0x8b,0xc7,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xc7,0xf9,
+  0xfe,0x7f,0x1f,0xe7,0xf9,0xff,0x9f,0xff,0xff,0xfb,0xfe,0xff,0xff,0xef,0xfb,0xfe,
+  0xff,0xbf,0xff,0xff,0xfe,0x7d,0x7a,0xff,0xfe,0x7f,0xbf,0xef,0xf9,0xfe,0x7f,0x9e,
+  0xef,0xff,0xff,0xeb,0xff,0xe7,0xff,0x83,0xff,0xff,0xff,0x7f,0xdf,0xff,0xfd,0xff,
+  0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0xaf,0xff,0xff,0xff,0xf7,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x7f,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xef,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xfd,0xff,0x7f,
+  0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xde,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,
+  0xff,0x7f,0xdf,0xf7,0xfd,0xff,0xff,0xff,0xff,0xf7,0xff,0xd1,0xff,0xff,0xff,0xef,
+  0xff,0xd3,0xf4,0xfd,0x1f,0x4f,0xd3,0xf4,0xfd,0x3f,0x4f,0xd8,0xfd,0x3f,0x4f,0xd1,
+  0xf4,0xfd,0x3f,0x47,0x53,0xf4,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xaf,0xff,0xe3,
+  0xfa,0xfe,0xbb,0xa4,0xe9,0xba,0xce,0xab,0xae,0xeb,0x3a,0xce,0xb3,0x2b,0x7a,0xfe,
+  0xbf,0xa3,0xeb,0xfa,0x3e,0x9f,0x8f,0xeb,0x7a,0xbe,0xaf,0xad,0xeb,0x7b,0x07,0xff,
+  0xff,0xff,0x7f,0xfe,0xc7,0xf2,0xfd,0x5f,0xff,0xfd,0xff,0x7f,0xdf,0xf7,0x7f,0xfb,
+  0xee,0xef,0xbf,0xef,0x7b,0xae,0xfb,0x9a,0xe1,0xff,0xff,0xff,0xff,0xff,0xff,0xf2,
+  0x7f,0xff,0xff,0xff,0x79,0xf7,0xfa,0x7d,0xff,0xff,0xdf,0x9f,0xeb,0xfb,0xfe,0xff,
+  0xf7,0xfb,0x7d,0xbf,0xbf,0xdb,0xff,0x7e,0xbf,0xda,0xff,0xff,0xff,0xdf,0xff,0xff,
+  0xfa,0x5f,0xff,0xff,0xff,0xfe,0xfb,0x7f,0xf5,0xb7,0x3f,0xef,0xf7,0xff,0xff,0xaf,
+  0x7f,0xbb,0x7e,0xff,0xff,0xff,0xfe,0xfe,0xff,0xfb,0x7f,0xff,0xff,0xbf,0xff,0xff,
+  0xff,0xff,0xfb,0xff,0xeb,0xff,0xee,0x3f,0x8d,0xe3,0xf8,0xfc,0x37,0x0f,0x63,0xc8,
+  0xfe,0x1d,0xa7,0xf8,0x7c,0x3f,0x83,0x23,0xf8,0xdc,0x1f,0x87,0xe3,0xff,0xef,0xff,
+  0xff,0xff,0xfe,0x70,0x7f,0xf6,0x7f,0xff,0xdf,0xf7,0xf5,0xff,0x77,0x9f,0x37,0xf9,
+  0xff,0x7f,0xdf,0xfe,0xed,0x7f,0xdf,0x77,0xdd,0xef,0x7f,0xdf,0x97,0xf5,0xf7,0xff,
+  0xff,0xff,0xff,0xdf,0xf0,0x0f,0xff,0xfe,0xff,0xef,0xef,0xd7,0xf7,0xfb,0xff,0xff,
+  0x1f,0xee,0xf3,0xbe,0xbe,0xf2,0xbb,0xbf,0xf9,0xbf,0xfe,0xbb,0xfc,0x5f,0xff,0xff,
+  0xff,0xbf,0xff,0xff,0xff,0x7f,0x09,0xff,0x7f,0xff,0xdf,0xff,0xdf,0xff,0xff,0xbf,
+  0x7f,0xd7,0xe5,0xfd,0xbf,0x3b,0xdf,0xf4,0x3b,0x5d,0xcf,0xfe,0xfc,0x7f,0x7f,0x3b,
+  0xff,0xff,0x9f,0xff,0xfb,0xff,0xff,0xf0,0xbf,0xff,0xff,0xff,0xff,0xbe,0xdf,0xf5,
+  0x73,0xdb,0x5f,0xbf,0xdd,0xbd,0xef,0x7b,0xee,0x7f,0xff,0x7b,0xff,0xff,0xfb,0xef,
+  0xff,0xff,0xff,0xfd,0x7e,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0x1f,
+  0xcf,0xf1,0xff,0xff,0xff,0xef,0xfb,0xf3,0xfe,0xfe,0xde,0xfc,0xfa,0xbf,0x3f,0x6f,
+  0xff,0xbf,0x1f,0xd7,0xff,0xfc,0x7f,0xff,0xff,0xff,0xd6,0xef,0xff,0xff,0xf7,0xff,
+  0xf7,0xfb,0x7f,0xd7,0xfe,0xff,0xfd,0xef,0xdf,0xff,0xff,0xf3,0xff,0xb7,0xfb,0xff,
+  0xf7,0xff,0xff,0xfb,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xfd,0xdf,0xff,0xff,0xff,
+  0xff,0xaf,0x7b,0xfc,0xff,0xbf,0xed,0x72,0xff,0xf3,0x7d,0xdf,0xff,0xf7,0xed,0xf9,
+  0x7e,0xdd,0x7b,0xfd,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x11,0x7f,0xff,
+  0xff,0xff,0xef,0xec,0xfd,0x7f,0xfa,0xbf,0xef,0xf9,0xfe,0xff,0xff,0xed,0xf0,0xfb,
+  0xbf,0xed,0xf9,0xff,0xaf,0x6e,0xfb,0xfe,0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0x7f,
+  0xff,0xff,0xff,0xfc,0xf5,0xff,0xff,0xff,0xff,0xfd,0x7e,0xff,0x5f,0xdf,0xfb,0xef,
+  0xf7,0xcf,0xfb,0xf8,0xef,0xff,0xfd,0x7f,0x9f,0xf7,0xff,0xff,0xff,0xff,0xff,0xf6,
+  0xc3,0xff,0xbf,0xfc,0xff,0xf5,0xcc,0xf7,0x3c,0xff,0xfe,0xcf,0xf2,0x6c,0xcf,0xdf,
+  0xcf,0xec,0x7f,0x3f,0xff,0xbf,0xff,0xfb,0x75,0xcf,0xb3,0xff,0xff,0xe7,0xff,0xff,
+  0xff,0x35,0xaf,0xf7,0xbf,0xdf,0xff,0xff,0xa3,0xe5,0xff,0x3f,0xdd,0xfe,0xa9,0xef,
+  0x7e,0x7f,0xfc,0x5a,0x3b,0xdf,0xf7,0xff,0xff,0xfe,0xbb,0xf6,0xff,0xff,0xfe,0xbf,
+  0xff,0xff,0x58,0xbd,0xfe,0xff,0xff,0x2b,0xff,0x9f,0x9d,0x73,0x2b,0xfa,0xe7,0xbf,
+  0xab,0x5d,0xcb,0x9f,0xac,0x6a,0x9f,0x7e,0x9f,0xf7,0xef,0x7f,0xfe,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xef,0x86,0xff,0xdf,0xff,0xed,0x7f,0xff,0xcd,0x93,0x65,0x79,0x7e,
+  0xdf,0x37,0xed,0xd3,0x7f,0xf5,0xe5,0x7f,0x76,0xdd,0xff,0x7f,0xff,0xff,0xdf,0xff,
+  0xff,0xdf,0xff,0xff,0xff,0x78,0xff,0xfb,0xff,0xfe,0xff,0xeb,0xfe,0x7d,0xdd,0x2f,
+  0xcb,0xc3,0xfe,0xbe,0x7c,0xdb,0xff,0xff,0x2f,0xff,0x22,0xdf,0xf7,0xff,0xeb,0xfb,
+  0xff,0xff,0xfd,0xff,0xff,0xff,0xfc,0xdb,0xff,0x77,0xff,0xff,0x7d,0x5f,0x77,0x1d,
+  0xf7,0x51,0x5e,0x77,0x95,0x87,0x7d,0xde,0xdd,0x87,0x79,0xdf,0x7b,0xdd,0xff,0x79,
+  0x5f,0x77,0xff,0xff,0xff,0xff,0xff,0xfd,0x99,0xff,0xef,0xff,0xfe,0xbf,0xad,0xfb,
+  0xca,0xfe,0xbf,0xaf,0xab,0x42,0xfe,0xad,0x2f,0x3f,0xfe,0xbe,0xaf,0x4b,0xfe,0xdf,
+  0xfe,0xaf,0xef,0x9f,0xf7,0xed,0xff,0xff,0xff,0xe3,0x7f,0xfd,0xff,0xff,0xd7,0xf5,
+  0xfd,0xb8,0x4f,0xd7,0xf5,0xfd,0xfa,0x5f,0xd6,0xf7,0xc6,0x7f,0xd7,0xf5,0x6d,0xff,
+  0x76,0xff,0x35,0xfd,0xf3,0xfe,0x7f,0x9f,0xff,0xff,0xff,0x4f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf6,0xfd,0xbf,0xed,0xff,0xfe,0xdf,0xbf,0xcd,0xfb,0x7f,0xbf,0xed,0xd0,
+  0xfc,0xfd,0x27,0xed,0xff,0xff,0xff,0xef,0x5b,0xff,0xff,0xff,0xf1,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xe3,0xfe,0xfe,0xff,0x9f,0xe7,0xfa,0xfe,0xff,0xfb,0xfa,0xfe,
+  0xf9,0xff,0xfb,0x9b,0xfe,0x7f,0xff,0xff,0xff,0xe7,0xff,0xff,0xff,0xf9,0x1f,0xff,
+  0xbf,0xef,0xfb,0xfe,0xfd,0x9f,0x67,0xdb,0x36,0xdf,0xbf,0xee,0xdb,0xbe,0xfd,0xee,
+  0xdb,0xee,0x75,0xbf,0x67,0xbb,0xfe,0xff,0xbf,0xef,0xf8,0xfe,0xff,0xbf,0xfe,0x56,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xbf,0x6f,0xdb,0xfc,0xff,0xff,0xef,0xf3,0xfe,0xfd,
+  0xbf,0xdb,0xff,0xfb,0xbe,0xdf,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,
+  0x76,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xf7,0xfd,0xfe,0xff,0xff,0xf7,0xfe,0xff,
+  0xbf,0xbf,0xfb,0xff,0xfe,0xdf,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0x17,0xfe,0x5f,0xff,0xff,0xff,0x7f,0x47,0xd1,0xf5,0xfd,0x7f,0xdf,0xd7,
+  0xf5,0xef,0x7f,0xd7,0xb5,0xfb,0x1b,0x5e,0xf9,0xff,0xff,0xff,0xfe,0xff,0xfe,0x7f,
+  0xff,0xfe,0xff,0x8b,0xff,0xe9,0xff,0xff,0xff,0xe7,0xeb,0xfa,0xfe,0x9f,0xa7,0xe9,
+  0xfa,0x7e,0x8f,0xa7,0xfb,0x76,0x9f,0xe3,0xea,0xd7,0x3f,0xdf,0xff,0xff,0xff,0xff,
+  0xef,0xff,0xff,0xff,0xb0,0x7b,0xfd,0x7f,0xfd,0xff,0xfd,0xfb,0x37,0x4f,0xf7,0xe5,
+  0xef,0x7f,0x5f,0xf7,0xbd,0xef,0x7f,0xf7,0x3e,0xff,0x77,0x5c,0xf7,0xbf,0xdf,0xf7,
+  0xfe,0xfb,0xbf,0xff,0xff,0xfd,0x2f,0xff,0xaf,0x9f,0xe7,0xf9,0xbe,0x3f,0x8b,0xc2,
+  0xf8,0xbe,0x3f,0x8b,0xa7,0xf9,0xbe,0x6f,0xe2,0xf9,0xfe,0x2f,0x89,0xe6,0xf9,0xfe,
+  0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xdd,0xff,0xff,0xff,0xff,0xff,0xf3,0xf5,0xff,
+  0x7a,0x5f,0xf7,0xfc,0x7f,0x37,0xdf,0xf1,0xfd,0x1f,0x4f,0xf1,0xf5,0xff,0x1f,0xef,
+  0xff,0xfe,0x7f,0x9f,0xe7,0xff,0xff,0xff,0xeb,0x3f,0xdf,0xff,0xff,0xff,0xfe,0x7e,
+  0xbf,0xbf,0xeb,0xfa,0xff,0xbf,0xa7,0xbf,0xfb,0xff,0xbf,0xe9,0xfe,0xfe,0xbf,0xbf,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x13,0xff,0xff,0xff,0xff,0xff,
+  0xdf,0xff,0xff,0xff,0x7f,0xdf,0xff,0xfd,0xff,0x7f,0xff,0xe7,0xff,0x7f,0xff,0xff,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe6,0xdf,0xff,0xff,0xff,
+  0xff,0xf9,0xff,0x7f,0xff,0xbf,0xef,0xff,0x7e,0xdb,0xfd,0xfd,0xfe,0xdf,0xb7,0xff,
+  0x7f,0xdf,0xb7,0xf7,0xfd,0xff,0x7f,0xdf,0xfd,0xfd,0xff,0xff,0xfd,0x9f,0xf7,0x7f,
+  0xff,0xff,0xff,0xff,0xf7,0xdf,0xf7,0xfd,0xbf,0xee,0xdf,0xf6,0xfd,0xad,0xff,0xff,
+  0xfd,0xaf,0x27,0xde,0xf2,0xff,0xff,0xab,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0xff,
+  0xf6,0xbf,0xa7,0xe9,0xfa,0xde,0xbb,0xaf,0xea,0xb8,0xfc,0x33,0xaf,0xe9,0xfa,0xf7,
+  0xaf,0xe3,0xba,0xf6,0xbb,0xa7,0x69,0xfa,0x7e,0xbf,0xaf,0xeb,0xfa,0xfe,0xbb,0xf3,
+  0x7f,0xdf,0xff,0xcd,0xff,0xff,0xdf,0x17,0xcd,0xae,0xf6,0xbd,0xef,0xf5,0xc3,0x73,
+  0xef,0xff,0xfe,0xe4,0x7f,0x3f,0xc7,0xff,0x6f,0xdf,0xfd,0xff,0xb3,0xff,0xff,0xff,
+  0xee,0xa7,0xff,0xff,0xdf,0xef,0xff,0xef,0xbe,0x93,0xdf,0xfd,0x7f,0x7b,0xff,0xff,
+  0xe7,0xef,0xff,0x5f,0xf7,0xfd,0xff,0xdf,0xff,0xe7,0xfb,0xff,0x7f,0xff,0xff,0xfd,
+  0xf7,0xff,0x95,0xef,0xff,0xfc,0xff,0xff,0xff,0xed,0xaf,0xcd,0xf2,0xff,0xbf,0x3f,
+  0xfe,0x3f,0xff,0xe7,0xbb,0xfb,0xcf,0xb3,0xe8,0xf6,0xff,0xfd,0x7f,0xff,0xff,0x3f,
+  0xff,0xff,0xff,0xe9,0xbf,0xfa,0xbf,0xff,0xff,0xff,0x7e,0x9a,0xb7,0xc9,0xf9,0xfd,
+  0x9f,0x6f,0x79,0xce,0xdf,0xff,0xaa,0xff,0xfe,0x9f,0x8f,0xf9,0xef,0x7b,0xdf,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0xd5,0xff,0xff,0xff,0xff,0xe7,0xfd,0xef,0xbb,
+  0xfd,0xdf,0xbb,0xff,0xff,0xfd,0xff,0xad,0x7f,0xfc,0x57,0xbf,0xf6,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0xff,0xfe,0xfd,0xff,0xf7,0xff,0xbf,0xff,0xff,
+  0xae,0xff,0xff,0xef,0x3d,0xab,0xee,0xdb,0xfb,0xff,0x73,0xfc,0xfe,0xff,0xcf,0xff,
+  0xf7,0xff,0xfb,0xff,0xfd,0xff,0xff,0xff,0x1f,0xff,0x37,0xfb,0xef,0xf7,0xbf,0xef,
+  0xfb,0xf4,0xed,0x7f,0xff,0x7b,0xf3,0xdf,0xff,0x59,0xff,0xff,0xfa,0xeb,0xdb,0xf5,
+  0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9a,0x7f,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xdf,0xff,0xd7,0xff,0x7f,0xff,0xfe,0xff,0xff,0xab,0xff,0xed,0xff,0xdf,0xfe,
+  0xff,0xfd,0xff,0xff,0xff,0xdf,0xfe,0xff,0xff,0xff,0xd0,0x7f,0xfd,0xff,0xff,0x7b,
+  0xfe,0xff,0xff,0x37,0x7d,0xf3,0xfc,0xfb,0xac,0x87,0xd1,0xd9,0xfe,0xa9,0x6f,0xbf,
+  0xf7,0xff,0x4d,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xff,0xbf,0xff,
+  0xdf,0xff,0xff,0xfe,0xe7,0xff,0xfe,0xbe,0xb6,0xbb,0xde,0xa9,0x7d,0xbe,0xff,0x7f,
+  0xf7,0xff,0xff,0xc1,0xbd,0xfe,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xc5,0xff,0xbf,
+  0xff,0xff,0xfb,0x7f,0xff,0xaf,0x7b,0xf7,0xd7,0x75,0xff,0xf7,0xfb,0xff,0x6f,0xfe,
+  0xfe,0xd5,0x7d,0xef,0xef,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x9d,
+  0xfb,0xf7,0xfd,0xfe,0xff,0x7b,0xef,0x4f,0xff,0xbf,0xff,0xbf,0xfb,0xfb,0xbe,0xdf,
+  0xef,0xff,0xfe,0x7f,0x75,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0x56,0xfb,0xff,0xff,0xdf,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xf7,0xff,0xfe,0xff,
+  0xdf,0xed,0xff,0xff,0xbf,0xff,0xfd,0xbe,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfa,0x1f,0xff,0x35,0xcf,0xf1,0x2f,0x7f,0x33,0xcf,0xf7,0x5c,0x53,0x5e,0xd7,
+  0xb1,0xec,0xcf,0xff,0xf3,0x5f,0xff,0x3f,0xcf,0xf1,0xef,0xff,0xe7,0xc7,0xff,0xff,
+  0xff,0xff,0xf1,0xda,0xff,0xe8,0xff,0x33,0xff,0xf9,0xf4,0xff,0xaf,0xe7,0xaa,0x7c,
+  0xdf,0x97,0xbf,0xfa,0xcf,0xaf,0x65,0xef,0xeb,0xfc,0x97,0xbd,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xf5,0xe3,0x5f,0xff,0xff,0xbf,0xad,0x77,0x4b,0xd2,0x3f,0x9f,0xf7,
+  0xed,0xd2,0x7e,0x8f,0xbb,0x5a,0x7e,0xbf,0xff,0xfb,0xfe,0xfe,0xef,0xbf,0xff,0xff,
+  0xbf,0xff,0xff,0xff,0xfe,0xfa,0x6f,0xff,0xff,0xff,0xdf,0xff,0x7d,0x7b,0x16,0x4b,
+  0xfb,0xfc,0xb9,0x37,0xcd,0xff,0xe7,0x17,0xc7,0xb7,0xe5,0xff,0x7f,0xd7,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x83,0xfb,0x2f,0xff,0xfe,0xfc,0x97,0x7f,0xbd,
+  0xfb,0x6c,0x8f,0xb7,0xe9,0xf2,0x7c,0xfb,0x69,0xff,0x7b,0xff,0x3e,0xcf,0xb3,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd1,0xbf,0xf5,0x7f,0xff,0x77,0x1b,0x8f,
+  0x7f,0xdf,0x77,0xd5,0xf7,0x7d,0x58,0x55,0x3d,0xfd,0xd6,0xf7,0xdd,0x87,0x69,0xdf,
+  0xd7,0xdd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0x37,0xfe,0xbf,0xff,0x7b,0x8f,
+  0xfe,0xbf,0xaf,0xeb,0x52,0xf4,0xff,0xaf,0x6b,0x9b,0xff,0x2f,0xeb,0xda,0xfe,0xbf,
+  0xaf,0x4f,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xde,0x97,0xff,0xd7,0xff,0xe5,
+  0xfa,0xf7,0xd7,0xf4,0xcd,0xba,0x4e,0x9b,0xb4,0xc5,0x33,0xff,0xf4,0xfd,0x3d,0x5f,
+  0xdf,0xf7,0xcf,0x7f,0x7e,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x7f,0xff,0xff,
+  0xfe,0xff,0xfd,0x3f,0xff,0xd9,0xf6,0xdd,0xff,0x7b,0xdb,0xf7,0xff,0xb7,0xdf,0xf7,
+  0xff,0xff,0xff,0xf9,0xfe,0xdf,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xdf,0xfb,
+  0xff,0xff,0xff,0xef,0xfa,0xff,0xff,0xbf,0xef,0xfb,0xff,0xff,0xef,0xef,0xf9,0xff,
+  0xff,0xe7,0xfb,0xfe,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x91,
+  0x7f,0xbb,0xfe,0xff,0xbe,0x66,0xfb,0xfe,0x6d,0x9e,0xe7,0x99,0xf6,0x7f,0x9b,0xed,
+  0xd6,0x7d,0x9f,0x6f,0xbb,0xb6,0xfd,0xbe,0xee,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,
+  0xed,0x7f,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0x3f,0xff,0xdb,0xfc,0xff,0xff,
+  0xff,0xf7,0xff,0x7f,0x6f,0xfb,0xf7,0xfd,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0xf7,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xfb,0xfe,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xef,0xfd,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfe,0xff,0xd1,0xff,0xff,0xff,0xfe,0x5f,0xf1,0xff,0xed,0x1b,0x47,0xd3,0xfc,
+  0x7d,0x1b,0x46,0xdf,0xff,0x1f,0x47,0xd7,0xfd,0xfd,0x7f,0xdf,0x9f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfb,0xe9,0x3f,0xff,0xff,0xff,0x49,0xfb,0xbf,0xff,0xaf,0xeb,0xfa,
+  0xfe,0xbf,0x2f,0xcb,0xfb,0x7f,0x2f,0xeb,0xfa,0x7e,0x9f,0x27,0xe9,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x33,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xfc,0xdf,
+  0x3f,0xdf,0xf3,0xf4,0xfd,0x3f,0xfd,0xfd,0xff,0x7f,0xde,0xf7,0xfd,0xdf,0xf6,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0xff,0xbf,0xf9,0xfe,0x7f,0x9d,0xe7,0xf9,
+  0xbe,0x3f,0x9b,0xe2,0xf8,0xbe,0x2f,0x9f,0xe6,0x9c,0x37,0x9f,0xe3,0xf9,0xfe,0x7f,
+  0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfd,0x5f,0xff,0xff,0xf9,0xf4,0x7f,0x7f,
+  0xff,0xf1,0xf4,0xfd,0x7f,0xcf,0xf7,0xfc,0x7f,0xbf,0xf7,0xac,0x7f,0x7f,0xcf,0xf1,
+  0xfe,0xfd,0x9f,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xa3,0xfd,0xff,0xff,0xfe,0xbf,
+  0xbf,0xff,0xfe,0xfe,0xbf,0xaf,0xef,0xfb,0xff,0xbf,0xf7,0xfb,0xfe,0xff,0xff,0xfb,
+  0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0x3f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xdf,0xfb,0xff,0xff,0x3f,0xff,0xff,0xff,0xfe,0xdf,0xf7,0xfd,
+  0xff,0xbf,0xdf,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfe,0xae,0xff,0xff,
+  0xfd,0xff,0x7f,0xf7,0xf7,0xf9,0xff,0x7f,0xdf,0xb7,0xfd,0xff,0x7f,0xdf,0xef,0xfb,
+  0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xe5,0xff,
+  0xdf,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0x7f,0xff,0xf4,0x7d,0xbb,0x7f,0xcb,0xfd,
+  0xff,0xfe,0xcb,0xfe,0xbd,0xbf,0x6f,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb2,
+  0xbf,0xff,0xeb,0xfa,0xfe,0xaf,0xad,0xe9,0xf2,0xfe,0xbf,0xa6,0xe8,0xba,0x76,0x9d,
+  0xaf,0x7a,0xbe,0xbb,0xa3,0xeb,0xda,0xce,0xbb,0xad,0xe2,0xfa,0xfe,0xb7,0xaf,0xeb,
+  0xff,0xc7,0xff,0xff,0xff,0x5f,0xfb,0xdd,0xf1,0x7c,0xda,0x37,0xcd,0xb3,0xf4,0x37,
+  0x37,0xfc,0xb8,0xdf,0x13,0xf5,0xd3,0x84,0x7d,0xd7,0xfc,0xf5,0xff,0xff,0xff,0xff,
+  0xff,0xff,0x74,0x7f,0xff,0xf7,0xfa,0xff,0x7f,0xff,0x67,0xf9,0xdf,0x77,0xdf,0xdf,
+  0xfd,0xfc,0xdf,0xbf,0xf3,0xcb,0x7f,0xbf,0xff,0x5f,0xfb,0xdf,0x7e,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xf8,0x97,0xff,0xfb,0xff,0x6f,0x7e,0xfa,0x5f,0x94,0xbb,0xfe,0xff,
+  0x3f,0x97,0xe5,0xff,0xef,0x57,0xff,0xbf,0xf7,0x4b,0xef,0xef,0xfb,0xfe,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0x99,0xfd,0xfd,0xff,0xb7,0xfe,0xfd,0xfe,0xfa,0x7e,0xbd,
+  0x27,0x6b,0xb9,0xf6,0xff,0x67,0xf3,0xfe,0x1f,0x8f,0xfb,0xdb,0xff,0xbd,0xfb,0xff,
+  0xbf,0xff,0xff,0xff,0xff,0xdf,0xef,0x7f,0xff,0xee,0xff,0x7f,0xff,0xff,0xff,0x9e,
+  0xfb,0xf9,0xfe,0x7d,0xff,0xf7,0xfb,0xf5,0xee,0xfd,0xfb,0xf5,0xff,0xef,0x7f,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xa7,0xff,0xfe,0xfd,0x77,0xff,0xbf,0xee,
+  0xfd,0xeb,0xef,0x3a,0xf7,0xff,0xff,0x5f,0xff,0xb3,0xf8,0xf7,0x3b,0xef,0xfb,0xf3,
+  0xed,0x3b,0xfe,0xff,0xbf,0xff,0xff,0xff,0xff,0x89,0xff,0xff,0xff,0xff,0xfb,0xde,
+  0xf6,0xfd,0xff,0xff,0xdf,0xff,0xfd,0xcf,0x7f,0xdf,0xe5,0xff,0x7e,0xdb,0x7a,0xfe,
+  0xaf,0xef,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xff,0xfb,0xff,0xbf,
+  0xfb,0x7e,0xd7,0xed,0xfe,0xfe,0x9f,0xff,0x3f,0xef,0xdb,0xff,0xef,0xda,0xee,0xe7,
+  0xff,0xff,0x7f,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xa7,0xfd,0xcf,0xf3,
+  0xde,0xff,0xad,0xcf,0xef,0xfb,0xfe,0xfd,0x2d,0xff,0xff,0xff,0xfb,0xbf,0xbf,0xf7,
+  0x33,0xff,0xef,0xff,0xbc,0x1f,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xfc,0xef,0xfe,
+  0xff,0x7e,0xf7,0xd7,0xdb,0x7f,0xeb,0xfb,0xfe,0xff,0x7f,0xf7,0xff,0xfe,0x79,0xeb,
+  0xff,0x9b,0x67,0xb7,0xff,0xff,0xfa,0xdf,0xff,0xff,0x7f,0xff,0xff,0xff,0xfc,0x9d,
+  0xef,0xbf,0xef,0x5f,0xdf,0x77,0x5f,0xbd,0xfd,0xdb,0xff,0x5a,0xf7,0xad,0x8b,0x3a,
+  0xf7,0xbf,0xde,0x7f,0xfd,0xb3,0xac,0xd9,0x7f,0xff,0xbf,0xdf,0xfd,0x7f,0xff,0xff,
+  0x19,0xff,0xff,0x7f,0xdf,0xf7,0xdf,0xff,0xbf,0xdf,0xb5,0xed,0x79,0xee,0xd7,0x37,
+  0xce,0xfe,0xf3,0xbf,0xef,0xbb,0x7e,0xdb,0xff,0xf7,0xff,0xff,0xff,0xff,0xaf,0xff,
+  0xff,0xff,0x77,0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,0xcf,0xfb,0x7f,0x7f,0x3f,
+  0xb7,0xfd,0xff,0x5f,0xf7,0xf5,0xff,0x7f,0x5f,0xdf,0xef,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0x63,0xff,0xf1,0xfc,0xcb,0x3f,0xdd,0x72,0x7d,0xcf,0x1f,0xdf,0xb3,
+  0x3f,0x7f,0xff,0xfd,0x7f,0xff,0xe7,0xf9,0xff,0xff,0x9f,0x3f,0xff,0xf3,0xff,0xcf,
+  0x3f,0xff,0xff,0xff,0x35,0xaf,0xff,0x7c,0xb9,0x6f,0xff,0x3e,0xff,0xfa,0xfb,0xff,
+  0xa7,0xff,0xff,0xff,0xff,0xaf,0xff,0xfc,0xff,0x9f,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xf3,0xff,0xff,0xff,0xff,0x5c,0xbd,0xff,0xff,0xef,0xef,0xd6,0xff,0xff,0xbf,0x4e,
+  0xcb,0xfe,0xe9,0xd6,0x75,0x9d,0x73,0xd7,0x55,0xd5,0x75,0x5d,0x57,0xfe,0xfe,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xff,0xef,0xa6,0xff,0xff,0xf7,0xfd,0xff,0xff,0xff,0x97,
+  0xed,0xf9,0x7f,0xdf,0x9f,0x4f,0xb3,0xfc,0xfe,0xff,0xf9,0xef,0xff,0x9f,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x6a,0xff,0xff,0xff,0xbf,0x3f,0xf9,0xfa,
+  0xfe,0x9e,0xee,0xdb,0xd3,0xff,0xf7,0xfc,0xde,0xb7,0xf5,0x78,0xdf,0x57,0x9d,0xe5,
+  0x7f,0xe9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x1b,0xff,0xff,0xdd,0xc7,0x7f,
+  0x3f,0x57,0xd3,0xf7,0x79,0xde,0x77,0xfe,0x6f,0xbf,0xff,0xfe,0xff,0x9b,0xef,0xfb,
+  0x7e,0xef,0xfd,0x36,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xd9,0xff,0xff,0xfe,0xda,
+  0xf7,0xed,0x6b,0x7a,0xe6,0xbe,0xae,0x2f,0xfd,0xff,0x77,0xdf,0x5d,0xdf,0x7f,0xdf,
+  0xf7,0x7d,0xfb,0xff,0xaf,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xe5,0x7f,0xff,0xff,
+  0x7f,0xdf,0xff,0xc5,0x7f,0x5e,0xdf,0xf7,0xcd,0xff,0xff,0xff,0xff,0xeb,0xfe,0xbf,
+  0xff,0xff,0xff,0xff,0xff,0xf5,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,
+  0xff,0xff,0xff,0xef,0xdb,0xff,0xfd,0xa7,0xe7,0xff,0xfe,0xdb,0xbe,0xe7,0xbb,0xfb,
+  0xbe,0xef,0xbb,0xee,0xfb,0xff,0xe7,0xde,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,
+  0xff,0xff,0xff,0xff,0xfe,0x3d,0xaf,0xff,0xfb,0xff,0xff,0xbf,0xff,0xfa,0xfe,0xfd,
+  0xef,0xfe,0xfe,0xbf,0x8f,0xe3,0xfb,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xee,0x9f,0xff,0xbf,0xef,0xfb,0xfe,0x39,0xbf,0x67,0x9b,0xf6,0xf9,0xb5,0x6f,0x1b,
+  0xbe,0xfd,0xef,0xdb,0xe6,0xfd,0xbf,0x6f,0x1b,0xfe,0x7d,0xbf,0xef,0xfb,0xfe,0xff,
+  0xbf,0xfe,0x16,0xff,0xff,0xff,0xff,0xff,0xfb,0x3f,0xdf,0xdb,0xfc,0xfd,0xbf,0xef,
+  0xfb,0xfe,0xfd,0xff,0xf3,0xfc,0xfd,0xbf,0xcf,0xfb,0xfe,0xff,0x3f,0xef,0xff,0xff,
+  0xff,0xff,0xff,0x74,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xfd,0xff,0xbf,0xef,
+  0xf7,0xbd,0xee,0xfb,0xff,0xbb,0xee,0xfb,0xbe,0xfb,0xbb,0xfe,0xff,0xbf,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x17,0xff,0xff,0xff,0xf5,0xff,0x3f,0xff,0xfb,0xf5,0xff,
+  0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xf5,0xff,0x9f,0xdf,
+  0xf7,0xff,0xff,0x7f,0xff,0xff,0xbb,0xff,0xff,0xff,0xfe,0x9d,0xeb,0xfd,0xd7,0x7e,
+  0x9f,0xa7,0xe9,0xff,0xbf,0xed,0xfa,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbc,0x9f,0xf7,
+  0xed,0xfb,0x7f,0xff,0xe7,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xef,0xff,
+  0xfd,0xf7,0xad,0xff,0x7b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xf7,
+  0xff,0x7b,0x7f,0xdf,0xff,0x6d,0xff,0xff,0xfe,0xcf,0xf7,0xff,0x9f,0xe7,0xf9,0xfe,
+  0x7f,0x9f,0xe7,0xe9,0xba,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0xe7,0xf9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xfe,0x3f,0x8f,0xe7,0xf9,0xbc,0x7f,0x9f,0x99,0xff,0xfe,0xff,0xff,0x5f,
+  0xf7,0xff,0xff,0xff,0xcd,0xf3,0x7c,0xff,0xff,0xef,0xfb,0xff,0x9f,0xef,0xfb,0xff,
+  0xff,0xbf,0xdf,0xdb,0xfd,0xff,0x7f,0xff,0xf7,0xef,0xff,0xfd,0x3f,0xdf,0xdf,0xff,
+  0xeb,0xfe,0xff,0xbf,0xff,0xff,0xeb,0xfb,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0x7e,0xff,0xbf,0xff,0xfe,0xff,0xff,0xff,0x27,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x3f,0xef,0xf7,0xff,0xff,0xbf,0xef,0xef,0xff,
+  0xbf,0xff,0xff,0xfe,0xff,0x7f,0x7f,0xf7,0xfd,0xff,0xff,0xde,0xff,0xff,0xd2,0xff,
+  0xff,0x7f,0xff,0xf7,0xff,0x7e,0x7f,0x9f,0xf6,0xfd,0xff,0x7f,0xf7,0xfd,0xff,0x7f,
+  0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0xfd,0xfb,0xfe,0xff,0xff,0xfb,0xdf,0xff,0xff,
+  0xdb,0xff,0xff,0xff,0xf7,0xfd,0xff,0xff,0xdf,0xf2,0xfd,0xff,0x6f,0xd3,0xf4,0x75,
+  0x3f,0xd1,0xf4,0xfd,0x3f,0x4f,0xd3,0xff,0xff,0xff,0xff,0xfd,0xff,0xe7,0xff,0xff,
+  0xff,0xd2,0xff,0xbe,0xaf,0xad,0xea,0xd8,0x7e,0xbd,0x8e,0xe9,0xba,0x56,0x9b,0x86,
+  0xe1,0xba,0x33,0x8e,0xc0,0xb8,0x2c,0xbb,0x0b,0xe3,0xfa,0xbe,0xbf,0xaf,0xeb,0xfa,
+  0xfe,0xbf,0xf6,0x7f,0xff,0x1f,0xfd,0xef,0x7c,0xfb,0xfa,0xff,0xf7,0xec,0xdd,0xfe,
+  0xcf,0xb1,0xed,0xdf,0xf3,0xb6,0xff,0xbf,0xd6,0xc3,0xff,0xff,0xff,0x3f,0xff,0xff,
+  0xff,0xff,0xfe,0xfe,0x25,0xff,0xcf,0xdf,0xff,0x7c,0xfd,0xff,0x7f,0xf7,0xf6,0xfb,
+  0xfa,0x77,0x54,0xff,0xff,0x7f,0x7f,0xf7,0xdf,0x7f,0xd3,0xff,0xfb,0xff,0x3f,0xfe,
+  0xff,0xff,0xef,0x7f,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x3b,0xff,0xbf,
+  0xec,0xff,0xfa,0xff,0xfb,0xef,0xf7,0xff,0xbb,0xbf,0xff,0xd7,0xee,0xfd,0xff,0xfd,
+  0xff,0xf7,0xff,0xff,0xff,0xfe,0xdf,0x3f,0xff,0xfb,0xff,0x7f,0xef,0x7c,0x8f,0xa7,
+  0x3b,0x5a,0x7e,0x37,0x8f,0xc3,0xf1,0x77,0x1f,0xdf,0xff,0xf3,0xff,0xbf,0xfb,0xcf,
+  0xfb,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0x15,0xff,0xff,0xdf,0xfb,0xfa,0xfd,0xf7,
+  0x9e,0xfe,0xfe,0xdd,0xef,0xdf,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xee,0xf6,
+  0xf7,0xff,0xff,0xff,0xd7,0xdf,0xff,0xff,0xef,0x64,0xff,0xbf,0xef,0xfb,0xfb,0xf3,
+  0xf3,0xfc,0xf7,0xee,0xef,0xff,0x7e,0xfe,0xb5,0xfd,0x6b,0xfd,0xff,0x7d,0xe7,0xf7,
+  0xff,0xcf,0xff,0xbf,0xdf,0xff,0xff,0xfe,0xff,0xff,0xfc,0x1f,0xff,0xff,0xff,0xbf,
+  0xed,0x7f,0xef,0xff,0xf2,0x7d,0x6b,0x7f,0xd3,0xb7,0xfd,0x7f,0x5b,0xf5,0x3d,0xff,
+  0x4b,0xdb,0xf5,0xf7,0xb7,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0x93,0x7f,0xff,0xff,
+  0xff,0xff,0xfe,0xdf,0x7f,0xcf,0xaf,0xfd,0xfb,0x2f,0xef,0xb7,0xfd,0x6e,0xd7,0xfd,
+  0xef,0xff,0xfb,0xbf,0xff,0x7f,0xff,0x7f,0xff,0xff,0xff,0xff,0x7f,0xf1,0x7f,0xdf,
+  0xff,0xfd,0xbd,0x6b,0xff,0xff,0xfe,0xaf,0xe7,0xfc,0xf6,0x3b,0x9f,0x33,0xf8,0x3f,
+  0xcf,0xf3,0xb4,0xef,0xbd,0x7f,0xff,0x77,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xaf,
+  0xff,0xff,0xff,0xff,0xff,0x7f,0xfb,0xff,0xfe,0xee,0xff,0xf7,0x4d,0x7b,0xff,0xdf,
+  0x9d,0xf7,0x7f,0xd6,0x77,0xfb,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xfe,
+  0xd1,0xff,0xfe,0xaf,0xbf,0xfd,0xb7,0xff,0xdf,0x3e,0x5e,0x97,0x79,0xff,0xfe,0xdf,
+  0xa3,0x1e,0x7b,0x9c,0xa3,0x78,0xdb,0xa7,0xd9,0xff,0x7f,0xdb,0xf7,0xff,0xff,0xff,
+  0xf7,0xbe,0x9f,0xff,0xef,0xfd,0xf8,0xff,0xf9,0xff,0xef,0xf9,0x7e,0xdd,0xd7,0xaf,
+  0x3f,0x6f,0xdf,0xfd,0xb3,0x7c,0xff,0x3f,0xf9,0xda,0x7f,0xbf,0xff,0xff,0xff,0xff,
+  0xef,0xff,0xfe,0x87,0xef,0xff,0xff,0xff,0x7f,0x7f,0xfd,0xf3,0xff,0x5f,0xbf,0x9f,
+  0xff,0xfd,0xff,0x7f,0xf7,0xff,0x5e,0xdf,0xf7,0xff,0xfc,0xff,0xf7,0xff,0xff,0xdf,
+  0xff,0xff,0xff,0xbe,0xe4,0xbf,0xff,0x35,0xc9,0xf5,0xfd,0x1f,0x35,0xcf,0xf3,0xfd,
+  0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0x1f,
+  0xdf,0xff,0xff,0xff,0xff,0xf1,0x0a,0xff,0xf7,0xff,0x3f,0xfe,0xf9,0xfe,0xac,0xfe,
+  0xfd,0xff,0xff,0xff,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xf7,0xff,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xff,0xf5,0xcb,0xdf,0x4b,0xd2,0xa6,0xbc,0xff,0x3e,0xd7,
+  0xfe,0xff,0xfe,0x77,0x9d,0x73,0x5f,0xde,0x7d,0xf5,0x7d,0x5f,0x57,0xce,0xf5,0xff,
+  0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf9,0x6f,0xfd,0x79,0x5e,0x57,0x9f,0xcf,
+  0xf9,0xff,0xdf,0x37,0xcf,0xf3,0xfe,0x7b,0x9f,0xcf,0xfe,0x7f,0x9f,0xcf,0xfb,0x3e,
+  0x5f,0x95,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xa7,0xff,0xff,0xff,0xff,0xff,
+  0x9f,0xef,0xfd,0xfe,0xed,0xff,0xfe,0xde,0x7f,0xcd,0xfb,0x7f,0xd7,0xdf,0xfd,0x7d,
+  0xad,0xb7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc5,0xbf,0xff,0x7f,0xdf,
+  0xf7,0xfb,0xfd,0x7f,0xba,0x77,0x9d,0xaf,0xff,0xee,0xfb,0xff,0xff,0xfe,0xfb,0xbf,
+  0xef,0xa9,0xde,0x76,0x3d,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0x9f,0xfe,0xbd,
+  0xaf,0xeb,0xfb,0xf5,0xff,0xff,0x4b,0x8a,0xf7,0x7d,0xdd,0x17,0xfd,0xff,0xdf,0xb7,
+  0xed,0xe3,0x7d,0x2f,0x2b,0x9a,0xe7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x47,0xff,
+  0xd7,0x85,0xfd,0x73,0xfe,0xbf,0xff,0xed,0xfb,0x5c,0x7f,0x9f,0xeb,0xff,0xff,0xff,
+  0xff,0xff,0xfc,0xff,0xa6,0xe5,0x7a,0x5c,0xff,0xff,0xeb,0xff,0xff,0xff,0xff,0x6c,
+  0x7f,0xff,0xff,0xff,0xff,0xfd,0xb7,0xff,0xde,0xff,0xbf,0x9e,0xeb,0xbb,0xee,0x7b,
+  0xbf,0xbb,0xee,0xfb,0xbe,0xef,0xda,0x7e,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xec,0x9f,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xf9,0xf7,0xbf,0xaf,
+  0xef,0xde,0xfd,0xef,0xeb,0xd8,0xfe,0x3f,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0xc9,0xff,0x5b,0xfe,0xdf,0xbf,0xe6,0xdb,0xf6,0x75,0xbd,0x6f,0x5b,0xd6,
+  0xf1,0xbb,0xef,0xde,0xfd,0xbe,0x6f,0xdb,0xd6,0x7f,0xbf,0xef,0xfb,0xfe,0xff,0xbf,
+  0xef,0xfb,0xff,0xea,0x6f,0xff,0xff,0xff,0xff,0xff,0xf3,0xfc,0xff,0xbf,0xef,0xfb,
+  0xfe,0xff,0xbf,0xef,0xf3,0xff,0x3f,0xcf,0xdb,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xf7,0x8f,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xfb,
+  0xfe,0xef,0x7b,0xde,0xfb,0xbb,0xfb,0xbe,0xef,0xbb,0xef,0xbf,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xc5,0xff,0xfd,0xfd,0x7f,0xdf,0xf9,0xbf,0xfd,0x9f,
+  0xdf,0xf7,0xff,0xff,0xfb,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xfd,0x1b,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0x3f,0xfe,0xdf,0xa7,0xd9,0xff,0xf6,0xdf,
+  0xef,0xe9,0xf2,0x7f,0xeb,0xfb,0xfe,0xff,0xa7,0xfa,0x7e,0xff,0xaf,0xef,0xaf,0xe9,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xf7,0xf5,0xff,0x7f,0x6f,
+  0xff,0x77,0xfb,0x7f,0xde,0xff,0x7f,0xff,0xff,0xff,0xef,0xff,0xfb,0xff,0xff,0xbd,
+  0x7f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xfb,0xf8,0xbe,0x6f,
+  0x8f,0xe3,0xf9,0x9e,0x3f,0x1b,0xc7,0xf9,0xfe,0x7f,0x9f,0xe7,0xfe,0x7f,0x9f,0xe7,
+  0xf8,0xfa,0x6f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xff,0xdf,0xff,0xc7,0xff,
+  0xfd,0xff,0xff,0xef,0xf1,0xfc,0x6b,0x3e,0xe7,0xfb,0xfe,0xff,0xbf,0xff,0xfe,0xfb,
+  0x9f,0xe7,0xf7,0x7c,0x7f,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xef,
+  0xef,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xb7,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfb,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf2,0x7f,
+  0xff,0x7f,0xff,0xf7,0xf7,0xff,0xbf,0xdf,0xff,0xff,0xef,0xff,0xff,0xff,0xfe,0xfe,
+  0xff,0xfb,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x6f,0xff,0xb6,0xff,0xfe,0x7e,0xff,0xf7,0xfd,0xff,0x7f,0xdf,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xff,0x7f,0xd7,0xf7,0xfd,0xed,0xbf,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0xff,0xff,0xff,0xff,0xfe,0xdd,0xf4,0x7d,0xff,0xcf,0xdb,0xfe,0xfc,0xbf,
+  0xcf,0xf3,0xfe,0xbf,0xaf,0xeb,0xbc,0xfd,0x3f,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xaf,0xff,0xe9,0xfa,0xbe,0xaf,0xa7,0x6b,0xb8,0xfe,0x9b,0xa7,0xe9,
+  0xba,0xfe,0xbf,0xab,0x78,0xfe,0xaf,0xa7,0xe8,0xb8,0xae,0xbf,0xad,0xeb,0xfa,0xfe,
+  0xbf,0xaf,0xeb,0xfd,0x27,0xff,0xf3,0xff,0xf7,0xf7,0xbf,0xf3,0xed,0xfb,0xdf,0x7f,
+  0x9f,0xff,0xf7,0xff,0xe7,0xff,0xbb,0x3f,0xfd,0xff,0x7e,0xbd,0xff,0xf7,0xfb,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xf2,0x7f,0xee,0xfd,0xff,0x7e,0xfe,0xba,0xef,0xfd,0xff,
+  0x7d,0x9f,0xed,0xf1,0xfe,0xef,0x7d,0xdf,0xff,0xdf,0x57,0xfd,0x7f,0xfa,0xdf,0xfd,
+  0xff,0xff,0xfd,0xdf,0xf7,0xff,0xfb,0x57,0xff,0x7f,0xbb,0xef,0xfb,0xfe,0xfb,0xf7,
+  0xbe,0xff,0xff,0xfb,0xff,0xff,0xbf,0xba,0x7f,0x64,0xbf,0xf5,0xf7,0xfe,0xff,0xbf,
+  0xfe,0xff,0xfc,0xff,0xff,0xff,0xff,0xff,0x93,0xff,0xff,0xdb,0xd7,0xf5,0xff,0x6f,
+  0xf2,0xd2,0x9c,0xaf,0xe9,0xea,0xfe,0x9f,0xaf,0xfa,0xfe,0x9e,0xaf,0x6b,0xfe,0xb6,
+  0xbf,0xfe,0x7f,0xff,0xfb,0xff,0xff,0xff,0xdf,0xf7,0x7f,0xfb,0xff,0xef,0x7f,0xff,
+  0xff,0xbf,0xde,0xdb,0x75,0xae,0xbf,0xaf,0x6b,0x9a,0x6f,0xae,0xeb,0xfa,0xfe,0xbe,
+  0xff,0xf7,0xaf,0xff,0xff,0xf7,0x7f,0xff,0xff,0xff,0xfe,0xaf,0xff,0xfe,0xff,0x7e,
+  0xff,0xfb,0x4f,0xad,0x7c,0xff,0xfb,0xef,0xff,0x9f,0xef,0xff,0x9a,0x3f,0xf7,0x3f,
+  0xff,0xe3,0xfb,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xfb,0xff,0xc1,0xff,0xfe,0xff,
+  0xff,0x2e,0xdb,0xf6,0xfb,0xfe,0x5c,0xd3,0xf5,0xbf,0xfb,0x7f,0xff,0xf4,0xfe,0xfb,
+  0xd6,0xf7,0x7d,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xfc,0xb7,0xff,
+  0xf7,0xf9,0xef,0x7b,0xff,0xb5,0xfe,0xdf,0xff,0xed,0xdf,0xfc,0xfb,0xcf,0xbe,0xbd,
+  0xff,0xff,0xff,0xbd,0xf9,0x7f,0xff,0xdf,0xff,0xff,0xff,0xff,0xfb,0xf7,0xff,0x57,
+  0xfd,0xcf,0xf3,0x48,0xf3,0x2d,0xcd,0xf3,0xff,0xbf,0x4f,0xcf,0xef,0xe8,0xf7,0xff,
+  0x5b,0xff,0xbf,0xaf,0xef,0x7a,0xdf,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xe6,0xef,0x7d,0xbf,0x7f,0xdf,0x97,0xe5,0xfd,0x7f,0xff,0xff,0xff,0x7f,0xff,0xdf,
+  0xff,0xdb,0xbf,0xfe,0xfb,0x8d,0xf9,0xbf,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0x5f,0xfe,0xb7,0xef,0xe1,0xd6,0xf3,0xbe,0xef,0xbd,0xbf,0x2b,0x9e,0xb7,
+  0xe8,0xcb,0x7f,0xd7,0xad,0xeb,0x6f,0xfc,0xff,0x25,0xfe,0xff,0xff,0xbf,0xff,0xff,
+  0xfd,0xff,0xfb,0xd9,0xff,0xfe,0x77,0xff,0xff,0xff,0xff,0x67,0x5b,0x7e,0xe7,0xd7,
+  0x3f,0xfe,0x37,0xde,0xff,0xdf,0xbf,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xa2,0x7f,0xff,0xd7,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xf5,
+  0xff,0xff,0x73,0xbe,0xbf,0xff,0xff,0xcf,0xf3,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xef,0x41,0xff,0xbf,0x3f,0xd7,0xff,0xfc,0xf3,0xff,0xff,
+  0x7e,0xc9,0xb3,0xfc,0xff,0xf3,0xcc,0xfc,0x4f,0x3f,0xcd,0x7f,0x3c,0xff,0x27,0xc7,
+  0xff,0x2c,0x7f,0xff,0xff,0xf1,0xff,0x65,0xaf,0x97,0xff,0xfa,0xff,0xff,0x97,0x7f,
+  0xff,0xff,0xc3,0x37,0x3e,0xcf,0xff,0xff,0xff,0xf3,0xff,0xf5,0x9f,0xe7,0xda,0x3f,
+  0xff,0xf3,0x8d,0xff,0xff,0xff,0xff,0x7f,0x59,0x35,0xfe,0xff,0xff,0x3f,0xff,0xf3,
+  0xf9,0xef,0xff,0x7a,0xd2,0xbd,0x6f,0x5f,0xcf,0x9f,0xe1,0xfe,0xff,0xf2,0xd9,0xef,
+  0xfe,0x7f,0xbf,0xbf,0xbb,0xff,0xff,0xff,0xf9,0xef,0x36,0xff,0xdf,0xff,0xcf,0xff,
+  0xfe,0xff,0x3d,0xed,0xff,0x5f,0xc7,0xbd,0xcd,0xf9,0xfe,0xf3,0xff,0xff,0xde,0xdb,
+  0xb3,0xef,0xff,0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0x9f,0x7a,0x3f,0xfb,0xdf,0xf7,
+  0xb6,0xd9,0x26,0x7d,0x9c,0x7f,0x5f,0xf2,0x71,0xfd,0x75,0xff,0xee,0xcf,0xff,0xff,
+  0xea,0x5a,0xda,0x6f,0x5f,0xfe,0xfe,0xff,0xff,0xff,0xff,0xff,0xf9,0x5b,0xfa,0x77,
+  0xff,0xf6,0xff,0xbf,0x4d,0x3b,0xff,0x7d,0xd4,0x75,0xbd,0x66,0xdb,0xdf,0xdd,0x6f,
+  0xff,0xda,0x4f,0xdd,0xf7,0x5b,0xff,0x77,0x9d,0xff,0xff,0xff,0xff,0xfd,0xa3,0x7f,
+  0xef,0xff,0xff,0xbf,0xaf,0x7f,0xfe,0xfe,0xf7,0xff,0xeb,0xd7,0xd5,0xff,0xaf,0x7a,
+  0xf7,0xfd,0x7d,0xea,0xfa,0xfe,0xf7,0xff,0xfb,0xeb,0xff,0xff,0xff,0xff,0xff,0xee,
+  0x7f,0xfd,0xdf,0xf7,0xdf,0xf7,0x77,0xff,0xff,0xdf,0x37,0xfd,0x3a,0xfe,0x99,0xf5,
+  0xf6,0x6e,0x7f,0xff,0xfd,0x7f,0x6e,0xf7,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0x07,0xfb,0x75,0xfd,0x7f,0x7f,0xd3,0xf6,0x7d,0xff,0xed,0xfb,0xf7,0xff,0xb7,
+  0x47,0xfb,0xdd,0xaf,0xe7,0xfb,0x74,0x7d,0xa7,0xff,0xf9,0xff,0xff,0xb7,0xff,0xff,
+  0xff,0xff,0x9d,0xbf,0x9e,0x7f,0x9f,0xf7,0xff,0xaf,0x7f,0xdf,0xfe,0x7f,0xef,0xff,
+  0xf9,0xfe,0x7f,0xaf,0xfa,0xfe,0x7f,0xbf,0x67,0xfb,0xfe,0xff,0x9f,0xff,0xf9,0xff,
+  0xff,0xff,0xff,0xfe,0x1f,0xff,0x9f,0xe7,0xf8,0xfe,0x6f,0x8f,0x63,0xdb,0xf6,0xfd,
+  0x9f,0x6f,0xd9,0xd6,0xe5,0xe7,0xbb,0xfe,0xef,0x9f,0xe6,0xdb,0xee,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xbf,0xfa,0xe7,0xff,0xfe,0xff,0xbb,0xef,0xff,0xfe,0x6f,0xb3,0xfc,
+  0xfd,0xff,0xcf,0xdb,0xfe,0xff,0xbf,0xfb,0xff,0xff,0xfe,0xff,0xdb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x6a,0xff,0xff,0xbf,0xed,0xff,0xff,0xff,0xf7,0xfd,
+  0xff,0xbf,0xff,0xfb,0xfe,0xfe,0xff,0xef,0xfb,0xff,0xff,0xff,0xbf,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x5f,0xff,0xe7,0xfb,0xb6,0x7f,0x9f,0x47,
+  0xf3,0xfd,0xfd,0x7f,0x47,0xd7,0xfc,0xff,0x7f,0xb3,0xfd,0xfd,0xfe,0xe7,0xd1,0xfd,
+  0xf9,0x7e,0x5f,0xd7,0xff,0xff,0xff,0xff,0xff,0xb3,0xfd,0xfe,0xff,0xbf,0xef,0xfb,
+  0xea,0xdb,0xbe,0x9f,0x37,0xeb,0xfb,0x7e,0xaf,0xa7,0xda,0xf6,0x9f,0xb7,0x5c,0xfa,
+  0xfe,0xdf,0xa7,0xe9,0xfa,0x7f,0xff,0xff,0xff,0xff,0xf2,0x3f,0xdf,0xff,0xff,0xdf,
+  0xff,0x6f,0xff,0xdf,0xff,0xf7,0xfd,0x7b,0x7e,0xf7,0xbd,0xfe,0xdf,0xf7,0x6f,0xff,
+  0xb7,0xd7,0xff,0xbf,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xaf,0xff,0xf7,0x1f,
+  0xa7,0x79,0xfe,0x77,0x8f,0xe7,0xf8,0xfe,0x27,0x0f,0xe2,0xf9,0xbe,0x6f,0xe6,0xe9,
+  0xfe,0x7f,0x9b,0xc7,0xf1,0xfe,0x2f,0x9f,0xa7,0xf9,0xfe,0x7f,0x9f,0xf9,0xfe,0xfe,
+  0xfb,0xff,0x7f,0xfb,0xff,0xff,0xff,0xff,0xd3,0xfc,0x79,0x1f,0xcf,0xf1,0xff,0x3f,
+  0xc5,0xfb,0xfe,0xff,0x7a,0xde,0x93,0xff,0xfd,0x3f,0xff,0xff,0xff,0xff,0xfd,0xbf,
+  0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xbf,0xeb,0xfb,0xff,
+  0xa7,0xeb,0xef,0x7f,0xff,0xef,0xff,0xfa,0x7f,0xff,0xae,0xbf,0xff,0xff,0xff,0xff,
+  0x77,0xff,0xfb,0xbf,0xdd,0xff,0x4f,0xff,0xff,0xff,0xff,0x6f,0xf7,0xb7,0xff,0x3f,
+  0xff,0xed,0xff,0x7f,0xff,0xf3,0xfd,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,
+  0xff,0xf2,0xd7,0xff,0xdf,0xf3,0xfd,0xe9,0x7f,0xdf,0xf7,0xff,0xed,0xff,0x7e,0xdf,
+  0xb5,0xfd,0xfe,0xdf,0xe6,0xfd,0xfb,0xdf,0x9d,0xff,0x7d,0xff,0xff,0xdb,0xff,0xff,
+  0xff,0xff,0xfc,0x4a,0xff,0x4f,0xff,0xbc,0xfd,0x3f,0xef,0xd1,0xfe,0xfc,0xbf,0x7f,
+  0xd3,0xfc,0xff,0xff,0xc8,0xff,0xff,0x9f,0xcf,0xdb,0xff,0xff,0xdf,0xff,0xd1,0xff,
+  0xff,0xff,0xff,0xff,0xab,0xbf,0xde,0xbf,0xa5,0xe9,0xda,0xfe,0x8d,0xab,0xea,0xfa,
+  0xae,0x8d,0xa3,0xe3,0xfa,0xf7,0xaf,0xe8,0xfa,0xfc,0x8d,0xa7,0xea,0xfa,0xfe,0xad,
+  0xaf,0xeb,0xfa,0xde,0xbf,0xf0,0x7f,0xbe,0x3e,0xcb,0xff,0xed,0xbd,0x3f,0xce,0xdf,
+  0x78,0xcf,0x1f,0xef,0xfb,0xff,0xff,0xbf,0xff,0x74,0xdf,0x3f,0x5f,0xbf,0xdf,0xdb,
+  0xff,0xdf,0xff,0xff,0xff,0x3f,0xff,0x07,0xff,0xde,0xef,0x7f,0xc7,0xff,0x4e,0xcb,
+  0xbf,0xec,0xff,0x4e,0xd6,0xbb,0xf5,0xdf,0x7f,0xf7,0x74,0xad,0xff,0xdd,0xff,0xfd,
+  0xff,0xff,0x7f,0xef,0xff,0xff,0xff,0xff,0xa5,0xff,0xfb,0xea,0xff,0xff,0xef,0xbf,
+  0xbf,0xef,0xfb,0xef,0xff,0x3f,0xee,0xfa,0xbb,0xe7,0xef,0xfd,0xfe,0xe3,0xdb,0x77,
+  0xfd,0xbf,0x7f,0xff,0x7d,0xf7,0x7d,0xd5,0x7f,0xf8,0x9f,0xff,0xfb,0xff,0xbe,0xdb,
+  0xff,0xbf,0xaf,0xf9,0xdf,0x7e,0x9d,0xff,0xe7,0xfa,0xff,0x77,0x3f,0xde,0xde,0x37,
+  0xad,0x67,0xff,0xfc,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0x05,0xff,0xff,0xff,0xff,
+  0xfd,0xee,0xdf,0xfe,0xdd,0xff,0xff,0xb6,0xff,0xff,0xff,0xef,0xff,0xff,0xfe,0x7e,
+  0xef,0xd5,0xff,0xf9,0xff,0xfd,0x7f,0xf7,0xef,0xff,0x7f,0xff,0xd0,0x7f,0xff,0xef,
+  0xd7,0xed,0xf3,0xff,0xfe,0xfd,0xef,0xfb,0xb0,0xdf,0x3b,0xff,0xef,0xff,0xff,0x7e,
+  0xff,0xff,0xef,0xfa,0xee,0xfd,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xfb,0xdf,0xff,
+  0x7f,0xff,0xf3,0xed,0x7f,0xff,0xde,0xe3,0xfc,0xbf,0xf7,0xff,0xff,0xdd,0x3f,0x56,
+  0xe5,0xfd,0xbf,0x4f,0xdb,0xf2,0xfd,0xff,0x56,0xdf,0x7f,0xff,0xff,0xfb,0xff,0x02,
+  0xff,0xfb,0xff,0xde,0xff,0xfe,0x7f,0xfb,0xf6,0xe7,0xeb,0xdf,0xdf,0xdf,0xfb,0xfb,
+  0xaf,0xff,0xff,0xed,0xfe,0x1e,0xea,0xff,0x6f,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,
+  0x74,0x7f,0x9f,0xff,0x5d,0xff,0x30,0xfe,0xfe,0xff,0x8f,0xe3,0xee,0xdd,0xff,0xce,
+  0xfa,0x75,0x3f,0x4f,0xf3,0x7c,0xff,0x3f,0xcf,0xf3,0xfc,0xff,0x3f,0xff,0xff,0xff,
+  0xf7,0xf4,0xef,0xff,0xff,0xbf,0xff,0xf9,0xbf,0x5f,0x7f,0xbd,0xbf,0x7f,0xef,0xbf,
+  0xe3,0x7f,0xdd,0xb7,0xde,0xff,0xbf,0xef,0xfb,0xfe,0xe7,0xbf,0xef,0xfa,0xff,0xff,
+  0xff,0xff,0xff,0xd5,0xff,0xed,0xbf,0xb2,0xed,0xff,0xbf,0xd3,0x7b,0x1c,0xa7,0x7f,
+  0xdd,0x77,0xdf,0xbf,0xfe,0x67,0x9f,0xa7,0xe9,0xfa,0x6a,0x8f,0xe7,0x39,0xfa,0x7f,
+  0xff,0xff,0xff,0xf7,0xb8,0x1f,0xff,0x7f,0xfd,0xff,0x7f,0xfb,0xb7,0xcf,0xfb,0xfc,
+  0xfd,0xbf,0xef,0xff,0xff,0xfb,0xef,0x73,0x3c,0x4f,0x37,0xc7,0xf3,0x7c,0xdf,0x37,
+  0xcf,0xff,0xff,0xff,0xff,0xf7,0xa7,0xff,0xfd,0xef,0x7f,0xff,0xf7,0xee,0xfd,0xff,
+  0x7f,0xd5,0xef,0xfb,0x7d,0xff,0xff,0xf3,0x7e,0xf7,0xbf,0xef,0xfb,0xfe,0xfb,0xbf,
+  0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xea,0xb7,0xff,0xff,0xcd,0x77,0x5c,0xcf,0x27,
+  0xcf,0xff,0xfc,0x7b,0x1f,0xcf,0xf3,0xfd,0xfe,0xcf,0xff,0xff,0xff,0xff,0xf7,0xff,
+  0x3f,0xff,0xdf,0xff,0xbf,0xef,0xfb,0xff,0xf1,0x1b,0xff,0xff,0xfd,0xaf,0xff,0xb3,
+  0xfe,0x7e,0xf3,0xeb,0xff,0x3f,0xfc,0xf9,0x7f,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xcf,0xff,0xff,0xff,0xf7,0xfd,0xff,0x7f,0xf5,0xd3,0xff,0xff,0x52,0xd3,0xfc,
+  0xff,0xfe,0xcf,0xbe,0xbd,0x7b,0x3e,0xce,0xe6,0xb5,0x7d,0xff,0xe7,0x79,0xdf,0x37,
+  0x9d,0xe7,0x7d,0x5f,0x57,0x9d,0xfe,0xff,0xbf,0xef,0xfe,0xfa,0x2d,0xff,0xff,0x5c,
+  0xdf,0xb7,0xff,0xfb,0xfc,0xdf,0x3f,0xef,0xfb,0x7c,0xd7,0xf7,0xcf,0xfc,0xff,0x3f,
+  0xef,0xf3,0xfc,0xff,0x3f,0xef,0xf3,0xff,0xdf,0xf7,0xfd,0xff,0xf6,0x47,0xff,0xaf,
+  0xff,0xff,0xf1,0xdf,0xff,0xbf,0xfa,0xdd,0xde,0x7f,0x8f,0xb6,0xfd,0xff,0x6d,0xff,
+  0xff,0xfc,0x7f,0x5f,0xd7,0xd5,0xf6,0xff,0xff,0x7b,0xfe,0xff,0xbf,0xff,0xc8,0xbf,
+  0xf5,0x7f,0xdf,0xf7,0xff,0xef,0xff,0xdf,0x7b,0x5b,0xdf,0x51,0xda,0x55,0x3d,0x4f,
+  0x3f,0xff,0xbf,0xef,0xfb,0xfe,0xfb,0xbe,0xef,0xfb,0xea,0x77,0xdd,0xf7,0x7f,0xd9,
+  0x1f,0xfe,0xbf,0xaf,0xef,0xff,0xfb,0xff,0xaf,0x6b,0xfb,0xff,0xff,0xaf,0x6b,0xfb,
+  0xf7,0xfd,0xf7,0x6d,0xfb,0x7e,0xdf,0x37,0xed,0xfb,0x7e,0xdf,0xef,0xfb,0xfe,0xff,
+  0xfe,0xf3,0xff,0xd7,0x35,0xfd,0xf3,0xff,0xff,0xf5,0xc5,0xff,0x6f,0xff,0xf7,0xe1,
+  0x7f,0x7f,0x7e,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,
+  0xdf,0xff,0xe4,0xff,0xb7,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xfd,0xfd,0xb7,0xff,
+  0xfb,0x7e,0x7f,0xff,0xdf,0xee,0xfb,0xbe,0xef,0xbb,0xee,0x7b,0xfe,0xe7,0xbb,0xff,
+  0xff,0xff,0xff,0xfd,0xdf,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xdb,
+  0xff,0xff,0xbf,0xff,0xfb,0xfd,0xbf,0x6b,0xd8,0xf6,0x3d,0xef,0xe7,0xff,0xf6,0x7f,
+  0xef,0xe7,0xff,0xff,0xff,0xe0,0xff,0xfb,0xfe,0xfd,0xbf,0xef,0x5b,0xfe,0xf5,0xbe,
+  0xe2,0xfb,0xd6,0xf9,0xbd,0x6f,0x1e,0x2d,0xbe,0x6f,0xdb,0xd6,0xff,0xbf,0x6f,0xdb,
+  0xf6,0xff,0xbf,0xef,0xfb,0xff,0xed,0x6f,0xff,0xff,0xff,0x3f,0xff,0xfb,0xfe,0xff,
+  0xbe,0xff,0xbb,0xfe,0xfd,0xbf,0xef,0xff,0xfb,0x3f,0xcf,0xdb,0xfe,0xff,0xbf,0xcf,
+  0xdf,0xf6,0xff,0xff,0xff,0xff,0xff,0xf7,0xcf,0xff,0xff,0xff,0xbf,0xff,0xfe,0xff,
+  0xbf,0xef,0xff,0xfe,0xff,0xbf,0xef,0xfb,0xff,0xff,0xbe,0xef,0xbb,0xee,0xfb,0xee,
+  0xef,0xbf,0xef,0x7b,0xff,0xff,0xff,0xff,0xff,0xcd,0xff,0xfd,0xff,0xfe,0x7f,0xd3,
+  0xfd,0xfd,0x7f,0x5f,0xd3,0xf5,0xed,0x7f,0xdf,0x9f,0xf9,0x3f,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0x5f,0xff,0xff,0xff,0xef,0xbf,0xff,0x9f,0xff,0xf9,
+  0xfa,0xff,0xdd,0xa7,0x6a,0xfa,0xbf,0x9f,0xa7,0xe9,0xde,0x7f,0xab,0xfe,0x9f,0xaf,
+  0xeb,0xfa,0xfe,0xdf,0xb7,0xeb,0xfb,0xe9,0xff,0xff,0xff,0xff,0x07,0xfe,0xf7,0xff,
+  0xed,0xff,0xfd,0xff,0x75,0xff,0x7f,0xdf,0xd7,0xfd,0xcd,0x77,0x5f,0xed,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xf8,0xff,0xfe,
+  0xf9,0xfe,0x6f,0x9f,0xe7,0xf8,0xbe,0x2f,0x8f,0xe6,0xf9,0xfe,0x2f,0x0b,0xe6,0xfe,
+  0x7f,0x9f,0xa7,0xf9,0xfe,0x7f,0x9f,0xa7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x9f,
+  0xff,0xc7,0xfb,0xf5,0xff,0xff,0xef,0xf1,0xfd,0xfd,0x7f,0x6f,0xf1,0xfc,0xf9,0xbf,
+  0xf7,0xfe,0xff,0xbf,0xe7,0xf9,0xfe,0xff,0xff,0xef,0xfb,0xf5,0xff,0xff,0xff,0xff,
+  0xfb,0xff,0xfb,0xff,0x7e,0xbf,0xff,0xfd,0xff,0xff,0xbf,0xaf,0xf9,0xff,0xfe,0xdf,
+  0xe7,0xfa,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xff,0xfe,0xbf,0xff,0xff,
+  0xff,0xf0,0x7f,0xfb,0x7f,0xff,0xd7,0xff,0xff,0xff,0xdf,0xf7,0xfd,0xfd,0xff,0xdf,
+  0xd7,0xb5,0xfe,0xdf,0xfb,0xfe,0xdf,0xff,0xff,0xfb,0xff,0xdf,0xbf,0xef,0xff,0xff,
+  0xff,0xff,0xff,0x4f,0xff,0xe7,0xfd,0xfa,0x7f,0xdf,0xf7,0xfd,0xfe,0xdf,0xf7,0xe7,
+  0xfd,0xfa,0x76,0x9f,0xef,0x7f,0xdf,0xf3,0xfd,0xff,0x7f,0xdf,0xf3,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xe5,0xff,0xff,0xff,0xff,0x2f,0xdf,0xff,0xff,0xef,0x27,0xeb,
+  0xf2,0xfd,0xbf,0xa7,0xf3,0xfd,0xff,0x4f,0xd3,0xf4,0xf5,0x3d,0x4f,0xd3,0xf4,0xf5,
+  0x3d,0x6f,0xdb,0xf7,0xff,0xfb,0x37,0xf3,0xeb,0xfa,0x2e,0xb5,0xaf,0xe8,0xfa,0xfe,
+  0xbf,0x8f,0x6b,0xba,0xbe,0xbf,0xa7,0x3a,0xee,0xbb,0xae,0xeb,0xba,0xee,0x8b,0xa6,
+  0xeb,0x3a,0xbe,0xb3,0xad,0xeb,0xfd,0x27,0xff,0xff,0x7f,0xff,0xff,0xf5,0x3f,0xff,
+  0xee,0xf3,0xfb,0xfe,0xf4,0xff,0xb6,0xff,0xbc,0xdf,0x17,0xcd,0x3f,0xff,0xeb,0x15,
+  0xfd,0xff,0x7d,0xfc,0xff,0x7f,0xef,0xdf,0xee,0x6f,0xbf,0xff,0xff,0x7f,0xff,0xaf,
+  0xed,0xff,0x7f,0xdf,0x7f,0xfb,0x7b,0xbe,0xbf,0x9d,0xfd,0x2e,0x6b,0x9f,0xe7,0xff,
+  0xde,0xdf,0xbf,0xcb,0xbb,0x7f,0xff,0xff,0xff,0xf8,0x9f,0xff,0xff,0xff,0xff,0xef,
+  0xd3,0xfb,0x7e,0xff,0xbf,0xff,0xff,0xee,0xef,0xbb,0xf6,0x57,0xef,0xeb,0xfb,0xff,
+  0xff,0xfd,0xf7,0xff,0xff,0x7f,0x7f,0xdf,0xdf,0xf7,0xfe,0xe1,0xff,0xff,0xff,0x9e,
+  0x9e,0xff,0xe4,0xf8,0x7a,0x9f,0xaf,0xf9,0xde,0x7e,0x9f,0xff,0xf8,0xfe,0xbf,0xaf,
+  0xc8,0xfa,0x9e,0xa5,0xad,0xcb,0xfa,0xed,0xff,0xff,0xbf,0x6f,0xf1,0x6f,0xff,0xf9,
+  0xfd,0xfb,0xff,0xcb,0xff,0xbf,0xf7,0xd5,0xbf,0xff,0xb7,0x57,0xdf,0xff,0xbe,0xeb,
+  0xfa,0xee,0xb9,0xad,0x6b,0xfa,0xde,0xbb,0xaf,0xfd,0x7f,0xff,0xfb,0xfe,0x47,0xff,
+  0xff,0xff,0xfa,0x7f,0xff,0xef,0xff,0x98,0x77,0xab,0xbe,0xfb,0xbf,0xff,0xfb,0xbb,
+  0xbe,0xff,0xfb,0xfe,0xfb,0xff,0xef,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xc9,
+  0x7e,0xff,0xff,0xed,0x7f,0xff,0xdf,0xbf,0xfd,0x7d,0xff,0xe7,0xfc,0xff,0x6e,0xdb,
+  0xf5,0xfe,0x5f,0xff,0xfe,0xfe,0xf7,0xef,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x6f,
+  0xf8,0xbf,0xfb,0xf7,0xfb,0xed,0xdf,0xd7,0xdd,0xff,0x6f,0x7f,0x37,0xbf,0xef,0x7b,
+  0xd6,0xee,0xe7,0xfd,0xff,0xdf,0xfd,0x7b,0x7f,0xf7,0xff,0xff,0x7d,0x7f,0xef,0xff,
+  0xff,0xf7,0x07,0xfb,0xcf,0xf3,0xd5,0x7e,0x17,0xbf,0x72,0x7c,0xff,0x3d,0xce,0xf1,
+  0xfc,0xef,0x2b,0xd3,0x9c,0xef,0x3f,0xae,0x73,0xfd,0xfd,0x3c,0xfe,0x7f,0xff,0xed,
+  0xff,0xff,0xff,0xfc,0xff,0xdd,0xbf,0x75,0xff,0xfd,0xbf,0xbb,0x7b,0xdf,0x97,0x7d,
+  0xbd,0x63,0xd9,0xeb,0xfa,0x73,0xf7,0xed,0xde,0xee,0x7b,0xbf,0xf7,0xf7,0xdf,0xff,
+  0xfe,0xff,0xff,0xff,0xfe,0x99,0xfe,0xbe,0xee,0x7f,0xfb,0x7d,0xff,0xeb,0xf1,0xde,
+  0x7a,0xae,0xd7,0xfb,0xff,0xfa,0xf5,0xe9,0xeb,0xfe,0x5e,0xff,0xae,0xbe,0xdb,0xed,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xc3,0xbf,0x6b,0x7a,0xfd,0xf6,0xce,0xff,0xff,0xff,
+  0xbf,0xe7,0xf9,0xee,0xb9,0xbf,0xef,0xda,0xf3,0x2b,0xff,0xfb,0xff,0xef,0xfb,0xff,
+  0xfa,0xff,0x9b,0xef,0xff,0xff,0xff,0xe4,0x7f,0xbf,0xff,0xf7,0xff,0xfd,0xff,0xdf,
+  0xff,0xf7,0xf3,0xff,0x7f,0xdf,0xf7,0xfb,0xff,0x76,0xef,0xef,0xff,0x5f,0xff,0xff,
+  0xff,0xff,0x6f,0xff,0xff,0xff,0xff,0xf7,0xfe,0x8f,0x8d,0xd5,0xfd,0x7f,0xff,0xff,
+  0xa7,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xdf,0xff,0xff,0xff,0xff,0xbf,0xff,0xef,
+  0xff,0xbf,0xff,0xdf,0xfb,0xfb,0xbf,0xef,0xfd,0xff,0xe9,0xfe,0xde,0xff,0xbf,0x7f,
+  0xfd,0xff,0x7e,0xff,0xef,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xf9,0xfe,
+  0xff,0xff,0xff,0xfd,0xfe,0xfd,0x9f,0xf7,0xd9,0xfe,0xdc,0xee,0x0f,0xff,0xd4,0xff,
+  0xfc,0xfb,0x3f,0xcf,0xbf,0x3f,0xff,0xff,0xfc,0xf3,0x5f,0xff,0x35,0xf1,0xfc,0xff,
+  0xfe,0xff,0xf3,0xfd,0xff,0xdf,0xdf,0xf1,0xff,0xff,0xfe,0xff,0xfc,0x96,0xbf,0xff,
+  0xaf,0xff,0x3f,0xcb,0xfd,0xf3,0xeb,0xef,0x7c,0xff,0xf9,0xcf,0xff,0xfc,0xfe,0xff,
+  0xbf,0xfe,0x9f,0xfe,0xfc,0xff,0x7f,0xfe,0xf3,0xff,0xff,0xff,0xdf,0xfd,0x78,0xf7,
+  0xff,0xe6,0xb9,0xfd,0x5f,0xcb,0xd4,0xbf,0xfe,0x6b,0x9e,0xd3,0xad,0x6f,0x2e,0xcf,
+  0x9f,0xbf,0xfd,0xfb,0xf2,0xbf,0xef,0xfb,0xd2,0xff,0xa9,0xae,0x6b,0xfb,0xff,0xbf,
+  0x9b,0xff,0xfc,0xd7,0xff,0xff,0xf3,0xde,0x57,0xb7,0xcd,0x7b,0x7e,0x57,0xf7,0xcd,
+  0xff,0xcf,0x97,0xfe,0xff,0x3c,0xd7,0xf7,0xef,0x7f,0x5f,0xdf,0xb5,0xe5,0x7f,0x7f,
+  0xfd,0xfb,0xe7,0xfd,0xff,0x5f,0xfd,0x3e,0xcf,0xd2,0xe9,0xf7,0xbf,0x0f,0x52,0xfc,
+  0xf7,0xef,0x5b,0x3f,0x9f,0x73,0xed,0xff,0xff,0xbe,0x7c,0xdf,0xfe,0xf9,0xff,0xff,
+  0xef,0xff,0xf6,0x6f,0xff,0xff,0xf7,0xfd,0xad,0x5b,0x56,0x7f,0xfd,0xe7,0xf9,0xd6,
+  0x56,0x1d,0xa7,0x6b,0x75,0x9b,0xcf,0xfd,0xdf,0xf7,0xdd,0xc7,0x6b,0xdf,0x77,0x3d,
+  0xff,0x7d,0xdf,0xf6,0xc7,0xff,0xfe,0x6b,0xff,0xff,0xf7,0xff,0xeb,0xfe,0xba,0xbe,
+  0xab,0xeb,0xfa,0xbe,0xbf,0xeb,0x5a,0xe3,0xfd,0xbf,0x7f,0xfe,0xf1,0xad,0x2f,0x5b,
+  0xea,0xfe,0xbf,0xbf,0xff,0xb1,0xff,0xfe,0xe9,0x1f,0xff,0xff,0xff,0xfd,0x7f,0x7f,
+  0xd7,0xf7,0xfd,0x7f,0x7f,0xdf,0xfd,0xb9,0x7e,0xbb,0xd6,0xc7,0xff,0x7c,0xf7,0xa5,
+  0xcd,0xff,0x5f,0xd7,0xf7,0xff,0xf9,0xbf,0xed,0xdf,0xf4,0x7f,0x9f,0xe7,0xfb,0xfc,
+  0x7f,0x3f,0xcf,0xd3,0x7e,0x7d,0x37,0xed,0xf6,0xbd,0xbf,0x6f,0xdf,0xff,0xff,0xff,
+  0x47,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xa5,0xfe,0x79,0xbe,0xa7,0xff,0xfe,0xff,
+  0xaf,0x7f,0xf8,0xf6,0xb9,0x9f,0xe7,0x9b,0xfe,0xff,0xe3,0xfa,0xff,0xbf,0xff,0xff,
+  0xff,0xe7,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xee,0x7f,0xd6,0x25,0x9f,0x6f,0x5b,
+  0xee,0xef,0xbf,0xef,0x5b,0xc6,0x35,0xbf,0x62,0xfb,0x37,0x9f,0xe6,0x59,0x76,0x7f,
+  0xbf,0xef,0xd8,0x7e,0xff,0xbb,0xef,0xfb,0xfe,0xff,0xf8,0x9b,0xff,0xf3,0xbf,0xcf,
+  0xfb,0xfe,0xff,0xfc,0xef,0xbf,0xee,0xfb,0xbf,0xcf,0xbb,0xf6,0xff,0xff,0xfb,0xfd,
+  0xff,0xbf,0xff,0xdb,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xf3,0xff,0xff,0xbf,
+  0xfb,0xfe,0xff,0x7f,0xff,0xf7,0xff,0xff,0x7f,0xef,0xf7,0xfb,0xff,0x7f,0xff,0xfe,
+  0xff,0xff,0xdf,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x5f,0xed,
+  0x3f,0xc7,0xff,0xef,0xff,0xff,0x5e,0xff,0xf5,0xff,0x3e,0x5f,0xd3,0xfd,0xfe,0xc7,
+  0xd1,0xf4,0xfd,0x1f,0xff,0xd7,0xfe,0x6b,0x7e,0x5f,0xff,0xff,0xff,0xfb,0xff,0x2f,
+  0xff,0xab,0xea,0xff,0x7f,0xdf,0xf7,0xea,0x9b,0xbe,0xab,0x23,0x69,0xf2,0x3e,0x9f,
+  0xeb,0xfe,0x7e,0xbd,0xaf,0xfd,0xf2,0x7f,0x8f,0xe7,0x69,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xf5,0xed,0x7f,0xfd,0xff,0xff,0xdd,0x7f,0xff,0xf7,0xfd,0xfd,0x7f,0xde,
+  0xf7,0xfb,0x7e,0x74,0xd7,0xf5,0xff,0xff,0x5e,0xfd,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xf1,0x3d,0xff,0xbe,0x27,0x9f,0xc7,0xf9,0xfc,0x2f,0x9f,0xa2,0xf9,0xba,0x6e,
+  0x9f,0xc6,0xf1,0xb7,0x0b,0xe2,0xf8,0x9e,0x7e,0x8b,0xe6,0xf9,0xbe,0x7f,0x9f,0xe7,
+  0xf9,0xfe,0x7f,0x97,0xfb,0xd7,0xf5,0xff,0xfa,0xef,0xdf,0xe5,0xff,0x7f,0xdf,0xf7,
+  0xf4,0xff,0x7a,0xcf,0xbd,0xe9,0xbf,0xcf,0xf1,0xfc,0xff,0xbf,0x4f,0xf3,0xf4,0xff,
+  0xff,0xff,0xff,0xff,0xf0,0xff,0xfe,0xff,0xbf,0xff,0xff,0xfa,0xfe,0xbf,0xbf,0xaf,
+  0xfb,0xeb,0x9e,0xff,0xed,0xfe,0xbf,0xaf,0xed,0xff,0xfe,0xfa,0xf7,0xeb,0xfe,0xfe,
+  0xbf,0xff,0xff,0xff,0xff,0xfd,0xdf,0xff,0x5f,0xd7,0xf7,0xfd,0xbf,0xfe,0xff,0xff,
+  0xdf,0x7f,0xff,0xd7,0x7d,0xff,0xfb,0xb7,0xf4,0xff,0xff,0xdf,0xf3,0xff,0xff,0x3f,
+  0xcf,0xfb,0xff,0xff,0xff,0xff,0xff,0xc3,0xff,0xeb,0x7a,0x5f,0xbf,0xf7,0xff,0xdf,
+  0xdf,0xf3,0xbd,0xff,0x3e,0x7f,0xf7,0xf7,0xfb,0xfe,0x9f,0xf7,0xfd,0xfb,0x6f,0xdf,
+  0xbd,0xf9,0xff,0x7f,0xff,0xff,0xff,0xff,0xfe,0x7f,0xf7,0xff,0xfb,0xdb,0xff,0xf7,
+  0xff,0xcf,0xda,0xb7,0xf5,0xab,0xcf,0xfb,0xd7,0xff,0x77,0xd3,0xff,0xf5,0x3d,0xff,
+  0xfe,0xf2,0xff,0xff,0xfe,0xff,0xbf,0xfc,0xbf,0xfe,0x0e,0xfa,0xfa,0xfe,0xad,0xab,
+  0xe1,0xfa,0x7e,0xbb,0xaa,0xeb,0xba,0xfe,0x1f,0x22,0xe9,0x5e,0x3d,0xab,0xeb,0xfa,
+  0xde,0xbf,0xac,0xeb,0xf8,0xde,0xbf,0xab,0xeb,0xfa,0xdf,0x71,0xbe,0xff,0xdf,0xf7,
+  0x7c,0x71,0xfc,0xdb,0xfd,0x7f,0xff,0x64,0xff,0xdf,0x55,0xff,0xfe,0xfb,0xc5,0xff,
+  0x7b,0xff,0x7f,0xf7,0xf9,0x7c,0xff,0x3f,0xff,0xff,0xfb,0xfb,0xfb,0x9f,0xff,0xfa,
+  0x7f,0xff,0xf5,0xfd,0x77,0xf7,0xfd,0xf7,0xe6,0xff,0x7f,0xfb,0xf7,0xeb,0x73,0x97,
+  0xbf,0xed,0xee,0xff,0xff,0x6b,0xae,0xf7,0xcf,0xdf,0x6f,0xff,0xff,0x7e,0x67,0xff,
+  0xff,0xff,0xff,0xf6,0xbf,0xb7,0xfe,0xff,0xfe,0xff,0xb7,0xef,0xef,0xf7,0xfb,0xdf,
+  0xfa,0xfa,0xff,0xbf,0xfb,0xbf,0xbe,0xfb,0xb7,0xef,0xbf,0xff,0xff,0xbe,0xef,0x78,
+  0x5f,0xdf,0xd2,0x5f,0xfb,0xeb,0xdb,0xd5,0xbd,0xbf,0xf9,0xfa,0xbe,0x9e,0xeb,0xe9,
+  0xef,0xff,0xaf,0xfb,0xfe,0xd4,0x3d,0x6f,0x61,0xbf,0xdf,0xde,0xff,0xff,0xff,0xf7,
+  0xfe,0x5f,0xef,0xff,0x7f,0xff,0xff,0x7f,0xdf,0xef,0xfe,0xf7,0xdb,0xdf,0xfb,0xff,
+  0xff,0x7f,0xfe,0xde,0xc7,0xff,0xff,0xdf,0xf7,0xde,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xf5,0xfd,0xa1,0xff,0xf3,0xbc,0x17,0x9f,0xbe,0xff,0xfe,0xef,0xfb,0x8e,0xeb,0x7a,
+  0xbe,0xfb,0xbf,0xef,0x9e,0xff,0xb5,0xee,0xef,0xeb,0xbf,0xef,0xff,0xff,0xef,0xff,
+  0xff,0xff,0xff,0xfe,0x6f,0xfd,0xff,0xff,0xff,0xf6,0xff,0xef,0xed,0x5f,0xbe,0xfc,
+  0xbe,0x4f,0xd3,0xdf,0x7d,0xef,0xbf,0xff,0xff,0xef,0xfb,0x97,0xf7,0xf7,0x9f,0xfd,
+  0x93,0xdf,0xff,0xfe,0xfe,0xef,0xff,0xef,0xff,0xdf,0x56,0xed,0xff,0xfd,0x7b,0xdf,
+  0xed,0xeb,0x5d,0xff,0xdd,0xff,0x9f,0xff,0xd7,0xef,0xfd,0xff,0xff,0x7b,0x9f,0xff,
+  0xff,0xbf,0xff,0xff,0xff,0xfd,0xe1,0xff,0xdf,0xcf,0xbe,0xf7,0x8d,0xeb,0x48,0xfb,
+  0x3f,0xcf,0xf3,0x9c,0xfd,0xf7,0xcc,0x65,0xfa,0xb7,0xff,0xff,0xf4,0xd7,0x4f,0xaf,
+  0x63,0xfa,0xfe,0x3f,0xff,0xf3,0xff,0xfd,0xbf,0xef,0xff,0xff,0xfe,0xfd,0xdf,0x7f,
+  0xdf,0xb7,0xfd,0xfd,0x7e,0xf7,0xdf,0xbd,0xda,0xbf,0xfb,0xf7,0xdf,0xff,0x77,0x7f,
+  0xfd,0xff,0x77,0xef,0xf7,0x7f,0xff,0x7f,0xff,0x15,0x7f,0xb7,0x75,0x8b,0xfe,0x9f,
+  0xbf,0x78,0xfe,0xba,0x1f,0xe7,0xf1,0xbf,0x3d,0x9d,0xfd,0xfb,0x7e,0xdc,0xbf,0x6b,
+  0xdf,0x77,0xfd,0xaf,0x7f,0xf6,0x3f,0xff,0xe9,0xff,0xea,0xff,0xfd,0xdd,0xbf,0xfe,
+  0xfb,0xff,0xff,0xf3,0xef,0xf9,0xef,0xdf,0xff,0x8f,0xfb,0xff,0x7e,0xaf,0x73,0xff,
+  0xff,0xf7,0x2b,0xff,0xff,0xff,0xff,0xee,0xff,0x77,0xff,0xf8,0x1f,0xee,0xff,0xef,
+  0xff,0xdd,0x7f,0xff,0xdd,0xbd,0xbe,0xf7,0x7b,0xff,0x7f,0xec,0xff,0xfe,0xe7,0xde,
+  0xf7,0xfb,0xff,0xf7,0xfb,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xda,0xff,0xfc,
+  0xff,0xff,0xd7,0xfc,0x7c,0xcf,0xff,0xcf,0xff,0x5f,0xd3,0x3f,0xcf,0xbf,0xff,0x3f,
+  0xcc,0xf7,0xfc,0x9f,0x3f,0xd7,0xf6,0x7f,0xff,0xfe,0xff,0xff,0xff,0xff,0xf6,0x6b,
+  0xe7,0x4f,0xff,0xf7,0xff,0xfd,0xf3,0xf8,0xff,0xff,0xe7,0xf9,0x3f,0xfc,0xff,0xff,
+  0xef,0xda,0xab,0x8e,0xff,0xfb,0xff,0xff,0x8f,0xff,0x3f,0xdf,0xff,0xff,0xff,0xdf,
+  0x4f,0x79,0xff,0x3f,0x1f,0xff,0xf7,0xfb,0x5f,0xcb,0xb5,0xb9,0xbf,0xea,0xcf,0xf5,
+  0xff,0xeb,0x7a,0xff,0xbf,0xe9,0xfe,0xcf,0xff,0xff,0xff,0xfb,0xfb,0xff,0xff,0xff,
+  0xfb,0xd1,0xbf,0xff,0xcf,0xf3,0xff,0xff,0xbf,0xe7,0xf3,0x7e,0xdf,0xb7,0xec,0xf9,
+  0xfe,0x7f,0x3d,0x7f,0x5f,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0xfd,0xff,0x7f,0xff,
+  0xff,0xcf,0xd9,0x17,0xed,0xfd,0x7f,0x5f,0xd7,0xfb,0xdb,0x6c,0xdd,0xc3,0xdb,0xb6,
+  0x26,0xdd,0xfb,0x6d,0xff,0xfd,0xd6,0xf5,0xbf,0xf7,0xff,0xfa,0xff,0xf7,0xef,0xcb,
+  0xff,0xff,0xf7,0xfe,0xc6,0xfe,0xbd,0x6d,0x7b,0xdf,0xf5,0x9f,0xe5,0x6b,0xba,0x75,
+  0x9d,0xc7,0x6b,0xdf,0xce,0xbf,0x7d,0xb6,0xf7,0xbd,0xff,0xff,0xda,0x57,0xff,0xf7,
+  0x71,0x7f,0xff,0xff,0xff,0x74,0xdf,0xff,0xdf,0xfc,0x7e,0x7f,0xff,0xdb,0xe7,0xaf,
+  0xea,0x9a,0xba,0xb7,0xef,0xff,0xfe,0xb9,0xaf,0x5b,0xce,0xdf,0xf7,0xff,0x4b,0x57,
+  0x9f,0xbe,0xaf,0xff,0xff,0xff,0xfb,0xdf,0xff,0xff,0xff,0xbf,0xfd,0xff,0xff,0xf7,
+  0xf7,0xfd,0xfa,0x7f,0xd3,0xfe,0xff,0xbf,0x97,0xb5,0xcf,0xf8,0xfc,0xfb,0xf7,0xe9,
+  0x7b,0xfc,0xdf,0xf5,0xff,0xff,0xf7,0xff,0xe9,0xfe,0xff,0xff,0xe9,0xff,0xfd,0xff,
+  0xbf,0x5f,0xdf,0xf4,0xdd,0x7f,0x67,0xdb,0x76,0x7f,0xe9,0xdb,0x7e,0xdf,0xff,0xe7,
+  0xfb,0x7f,0xbd,0x37,0xff,0xf7,0xff,0xfd,0x7f,0xe4,0x5f,0xfb,0xfb,0xfe,0x7f,0xff,
+  0x7f,0xfe,0xe6,0xfd,0xfe,0x6f,0x9b,0xff,0xfb,0xbf,0x67,0xfe,0xff,0xbf,0xef,0xff,
+  0xfe,0x7f,0xbf,0xff,0x9f,0xff,0xfc,0xff,0xff,0x8f,0xfa,0xc7,0xff,0x6f,0x1b,0xd6,
+  0xfd,0xbf,0xef,0xf8,0xb6,0x3d,0x81,0x62,0xf9,0xf6,0x71,0x8f,0xfb,0xbe,0x6f,0xbb,
+  0xef,0xdb,0xfe,0xef,0xbf,0xe3,0xfb,0x7e,0xff,0xbf,0xe7,0xff,0xb9,0xbf,0x6f,0xfb,
+  0xfe,0xfd,0xfe,0xff,0xff,0xec,0xfb,0x3e,0xef,0xbf,0xfc,0xff,0xfe,0xfb,0xff,0xff,
+  0xff,0xff,0xf3,0xfe,0xff,0xff,0xff,0xbb,0xff,0xf3,0xff,0xff,0x3f,0xf9,0xbf,0xfb,
+  0xfe,0xfe,0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0xf7,0xff,0xff,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfe,0xff,0x7f,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xef,0xff,0xc7,
+  0xff,0xd7,0xb5,0xfd,0x7f,0xdf,0xbb,0xf4,0xff,0x3f,0xc7,0xf3,0xf4,0xfd,0x1f,0x4f,
+  0xef,0xff,0x9b,0xff,0xbf,0xff,0x6b,0xff,0xfe,0xd1,0xfd,0xfd,0x7f,0xff,0xfb,0xff,
+  0xe2,0xff,0xfa,0x7e,0x9f,0xa7,0x7c,0xbf,0xf6,0x8f,0x23,0xe8,0xda,0x3e,0xbd,0xaf,
+  0x6a,0xff,0xdf,0xb7,0xdd,0xff,0x77,0xdf,0xe7,0xff,0xfa,0x3e,0xdd,0xaa,0xff,0xff,
+  0xbf,0xff,0x9f,0xff,0xdf,0xd7,0xe5,0xff,0xff,0xfe,0xd7,0xfd,0xff,0x5f,0xdf,0xf7,
+  0xe5,0xff,0x7f,0xb7,0xef,0x5f,0x7b,0xff,0xbb,0xff,0xef,0xff,0xf6,0xb7,0xf5,0xff,
+  0xff,0xff,0xff,0x93,0xff,0xeb,0xe3,0xe8,0xbe,0x7f,0x9f,0xe2,0xf8,0xbe,0x3f,0x0f,
+  0xe6,0xf0,0x9e,0x2f,0x9e,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe3,0xf8,
+  0xbe,0x7f,0x9f,0xe7,0xf2,0x7f,0xfd,0x7f,0x45,0xf7,0xff,0xff,0xbf,0xdf,0xff,0xfd,
+  0xeb,0x7f,0x46,0x91,0xf5,0xff,0xe7,0xff,0xff,0xff,0x1f,0x6f,0xfb,0xfe,0xfd,0x7f,
+  0xcf,0xf7,0xff,0xff,0x9f,0xfe,0xaf,0xff,0xaf,0xeb,0xea,0xff,0xff,0xf7,0xfb,0xff,
+  0xff,0xbf,0xef,0xeb,0xfa,0xfe,0xbf,0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0x7b,0xdf,
+  0xaf,0xed,0xfe,0xff,0xff,0xff,0xff,0xf1,0xfe,0xfd,0xfd,0x7f,0xdf,0xff,0xf7,0xfd,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xbf,0xff,
+  0xff,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xf9,0x3f,0xfe,0x9f,0xa7,0xeb,0xff,0xde,
+  0xdf,0xad,0xff,0x7f,0xdf,0xf7,0xf7,0xf9,0xff,0xdf,0xe7,0xff,0xff,0x7f,0xdf,0xf7,
+  0xfd,0xbf,0x7f,0xf7,0xb7,0xfb,0x7f,0xff,0xf7,0xff,0x93,0xff,0xdb,0xf7,0x6d,0x9f,
+  0x2f,0xd1,0xdf,0xff,0x3f,0x27,0xdb,0xfe,0x3f,0xbf,0x6f,0xff,0xbf,0xbf,0xaf,0xeb,
+  0xff,0xfe,0xbf,0xff,0xff,0xff,0xfd,0xbf,0xff,0xfd,0xff,0xe2,0xff,0xfd,0x85,0xe9,
+  0xfa,0xee,0xbf,0xad,0xe8,0xfa,0xee,0x3f,0xad,0xe8,0xfa,0xb6,0xbd,0xeb,0xfa,0xbe,
+  0x1f,0xaf,0xe9,0xf8,0xbe,0xbf,0xab,0xeb,0x5a,0xbe,0xbf,0xaf,0xf4,0x9f,0xfe,0x5f,
+  0xef,0xf3,0xbf,0xff,0xbf,0xfd,0xfc,0xff,0xef,0x0d,0xd3,0xf4,0xbd,0xf6,0xff,0xf7,
+  0xdf,0xef,0xff,0xb3,0x7f,0xbf,0xf7,0xff,0xff,0xf7,0xff,0xff,0xc7,0xff,0x99,0x7d,
+  0x7b,0xff,0x3d,0xfb,0x7a,0xdf,0xaf,0x7c,0xfe,0xf9,0xde,0xfc,0xfd,0xff,0xf7,0x7f,
+  0xf7,0xeb,0xf7,0xdf,0xbd,0xad,0xff,0x7f,0xbf,0xff,0xdf,0xff,0xff,0xef,0xff,0xe6,
+  0x67,0xff,0xff,0xff,0xff,0x5f,0x7f,0xca,0xfd,0xb2,0xff,0x6d,0x7f,0xff,0x8e,0xef,
+  0xfd,0xff,0xff,0xff,0xfb,0xfa,0xbf,0xff,0xff,0xff,0xff,0xfe,0xff,0xef,0xfa,0xff,
+  0xff,0x45,0xfc,0xff,0x2f,0xda,0xfe,0xbf,0x1f,0xeb,0xfe,0xfd,0xb7,0xaf,0xfb,0xfa,
+  0xe7,0xbf,0xfd,0xf0,0xe4,0xad,0x83,0xef,0xe8,0xff,0xff,0xfd,0xff,0xfe,0xff,0xff,
+  0xff,0x7f,0xcd,0xff,0xff,0x7b,0xbf,0xec,0x7b,0xbf,0xff,0xbf,0xbf,0xdf,0xfe,0xff,
+  0xff,0x9f,0xff,0xef,0xff,0x7f,0xe7,0xd7,0xef,0x7f,0x7f,0xff,0xdf,0xff,0xf7,0x77,
+  0xff,0xff,0xff,0xf9,0x9f,0xff,0xbb,0xce,0xe3,0xfb,0xaf,0xef,0xbe,0xff,0xef,0xfe,
+  0x3f,0x8e,0xff,0xfb,0xee,0xfe,0xff,0x7e,0xff,0xaf,0xef,0xff,0xbe,0xef,0xfb,0xff,
+  0xff,0xff,0xdf,0x3f,0xff,0x15,0xfb,0xec,0x36,0xfd,0xee,0x7f,0xdf,0xfe,0xff,0xff,
+  0xfb,0xff,0xd7,0xfd,0xef,0xef,0xff,0x7f,0xfd,0x6d,0xdb,0xf6,0xef,0xbf,0x6f,0xff,
+  0xff,0xff,0xff,0xff,0x57,0xef,0xe0,0xff,0xdf,0xbe,0xf5,0x6e,0xef,0x76,0xff,0xf7,
+  0xfb,0xff,0xff,0xdf,0xbd,0xbb,0xff,0x8b,0xff,0xfd,0x6d,0xf6,0x76,0xde,0xfd,0xed,
+  0x5f,0xf7,0xff,0xfb,0xff,0xff,0xdf,0xfc,0x5f,0xf7,0x23,0x8f,0xf3,0x3b,0xfd,0xff,
+  0xfd,0xd3,0xff,0xff,0x5f,0x8d,0xf1,0xbe,0xff,0x4e,0xe1,0xd9,0xdd,0x2f,0xcf,0xfb,
+  0xf4,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0x7f,0x93,0xb7,0xf7,0xfd,0xff,0x7f,0xff,
+  0xff,0xdf,0xff,0x77,0xfe,0xff,0xba,0xfb,0xba,0x6f,0xe9,0xbf,0x7f,0xbf,0xf7,0xfd,
+  0xff,0x7d,0xdf,0xfe,0xff,0xff,0x7f,0xff,0xff,0xff,0xfa,0x77,0xfa,0x3f,0x1e,0xe3,
+  0x25,0xd5,0x76,0xfd,0xe7,0xed,0xfb,0xbf,0xd7,0xff,0xfe,0xdf,0xdf,0xb7,0xfd,0x38,
+  0x76,0x9f,0xff,0xf9,0xfb,0xff,0xff,0x6f,0xff,0xfb,0xff,0xff,0xc6,0xff,0xf7,0xbf,
+  0xb6,0xff,0xff,0xef,0xff,0x7e,0x7e,0x33,0xae,0xfb,0xff,0xff,0xa7,0x61,0xfe,0xff,
+  0xff,0xa7,0xf3,0xfe,0xff,0xb7,0xaf,0xff,0xff,0xff,0xef,0xff,0x7f,0x89,0xff,0xf7,
+  0xff,0xf7,0x5f,0xfe,0xfd,0x7f,0xff,0x5f,0xfd,0xff,0xfd,0x5f,0xff,0xef,0xff,0xff,
+  0x3f,0xdf,0xef,0xff,0x7f,0xbf,0xce,0xff,0xff,0xff,0xff,0xff,0x7f,0xdf,0xe8,0x0f,
+  0xf2,0xff,0xbf,0x5f,0xfb,0x7e,0xdf,0xbf,0xff,0x57,0x3e,0xdf,0xbd,0xfd,0xd3,0x3f,
+  0xf5,0x5c,0xff,0x3e,0xf7,0xfd,0x5c,0xfb,0xfe,0xff,0xff,0xef,0xfb,0xfe,0xdf,0xfc,
+  0xe6,0xbe,0x97,0xf3,0xe5,0xff,0x1b,0xcf,0xf7,0xff,0xfa,0x7f,0xcf,0xf7,0xfe,0xf9,
+  0x74,0xff,0xab,0xdf,0xaf,0xce,0xf3,0xcf,0xff,0x3f,0xdf,0xff,0xfc,0xff,0x7f,0xc7,
+  0xfd,0x7c,0xf7,0xfb,0xfe,0xbc,0xaf,0x2b,0xfa,0xf2,0xdf,0xfe,0x7a,0xcf,0xc6,0x9f,
+  0xed,0xed,0xff,0xff,0xff,0xfb,0xfa,0xfe,0xbf,0xfb,0xeb,0xca,0x7f,0xff,0xaf,0xef,
+  0xca,0x7f,0xbe,0x9b,0xff,0x5c,0xd7,0x35,0xcd,0x7f,0x7e,0x55,0x9f,0xcf,0x7b,0xfe,
+  0xd5,0xff,0xfc,0xff,0xef,0xfb,0xff,0xff,0x5e,0x57,0xff,0xed,0x7b,0x57,0xff,0xf7,
+  0xfd,0xf3,0x57,0xfd,0x93,0xff,0xed,0x32,0x4c,0x93,0x27,0xcb,0xfb,0x6d,0xff,0xff,
+  0x8b,0xa2,0x5e,0xbf,0x33,0xff,0x7f,0xdf,0xf6,0xcb,0xf7,0xdf,0xde,0xa5,0x0f,0xff,
+  0xfe,0xb7,0xbf,0xeb,0xff,0xf0,0x6f,0xfd,0xfe,0x5f,0xdd,0xec,0xf5,0x5a,0x7e,0xbf,
+  0xe7,0x51,0xdf,0x4f,0xfd,0x87,0x7f,0xf7,0xff,0xfe,0x79,0x58,0x7b,0xff,0xf5,0xf9,
+  0xff,0xff,0xde,0x67,0x7d,0x76,0xf6,0x27,0xff,0xbf,0xab,0xfa,0xda,0xb7,0xae,0x6f,
+  0xd6,0xfb,0xbf,0xbf,0x6a,0xfa,0xe6,0xfd,0xff,0xff,0xf5,0xde,0xad,0xeb,0xff,0xfe,
+  0xbe,0xad,0xff,0xfa,0xde,0xff,0xef,0x5f,0xb9,0xff,0xf7,0x69,0x5f,0x46,0xd3,0x35,
+  0xfd,0x3b,0x7f,0xf7,0xfd,0xe5,0x6a,0xff,0xdb,0xdb,0xb3,0xee,0xfb,0xb5,0xfd,0x7f,
+  0xef,0xd1,0xf5,0xff,0xff,0x7f,0xdf,0xf5,0xcf,0xff,0xbf,0xff,0xd7,0xfc,0xdd,0x2f,
+  0x6d,0xfb,0x76,0x9f,0x1f,0xed,0xf8,0xfd,0xff,0xff,0x6d,0xf7,0xfd,0x8f,0x7b,0xf3,
+  0xfd,0xff,0xb7,0x4f,0xf3,0xff,0xff,0x37,0xff,0xfb,0x7f,0xf7,0xfe,0x79,0xff,0xaf,
+  0x9e,0xff,0xff,0xbe,0x6f,0xdf,0xfe,0xff,0xfe,0x7f,0xff,0xfe,0xef,0xe7,0xff,0xfe,
+  0xfc,0xaf,0xff,0xfb,0xe6,0xbd,0xaf,0xff,0xef,0xff,0xfd,0xff,0xf8,0x5f,0xfe,0x75,
+  0xbb,0x65,0xd9,0xd6,0xef,0x99,0x6f,0xdb,0xb6,0xff,0x8f,0x6f,0xf9,0xbf,0x9f,0xe7,
+  0xfb,0x16,0xe5,0xbf,0x6f,0x99,0xb6,0xef,0xbf,0xef,0xfb,0xfe,0xff,0xf8,0x5b,0xff,
+  0xfb,0xff,0x6f,0xb3,0xff,0xff,0xfe,0xef,0x9b,0xfd,0xff,0xfe,0x7f,0xff,0xff,0xff,
+  0xff,0xfb,0xff,0xf3,0xbf,0x7f,0xf7,0xed,0xfb,0xff,0xff,0x3f,0xff,0xf3,0xfd,0xab,
+  0xff,0xfe,0xff,0xfb,0xed,0xff,0xff,0xff,0xef,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0x5f,0xbf,0x1f,0xcf,0xf1,0xf4,0xf9,0xff,0x47,0xd7,0xf7,0xff,0xff,0xe7,0xdf,
+  0xf4,0x7e,0x47,0xd1,0xf4,0x7d,0x7e,0x5f,0xf5,0xf4,0x7d,0x7f,0xff,0xd7,0xff,0xfb,
+  0xff,0xfa,0xaf,0xfd,0xe3,0x7a,0xfe,0xbe,0xbf,0xb7,0x6a,0xbe,0xad,0x9f,0x77,0xcc,
+  0xfe,0x76,0xbf,0xeb,0xfa,0xf4,0xbf,0xa2,0xec,0xf7,0xfe,0xa9,0xaa,0xff,0xda,0xbf,
+  0xff,0xf2,0xff,0xfd,0xff,0xfd,0xfd,0x7b,0xfd,0xd7,0xff,0xfd,0x5b,0xde,0xff,0xfd,
+  0xeb,0xfb,0x7f,0xd7,0xb9,0x7f,0x55,0xd5,0x75,0xfd,0x7f,0xcd,0xd7,0x75,0xff,0xff,
+  0x5f,0xff,0xbf,0xff,0xf8,0xbf,0xff,0x9e,0x2f,0x9d,0xe2,0xf8,0xfe,0x2f,0x9b,0xe7,
+  0xf8,0xfe,0x37,0x9b,0xe2,0x69,0xa7,0x8b,0xa2,0xf8,0xbe,0x3f,0x8f,0xe2,0x78,0xfe,
+  0x7f,0x8b,0xe7,0xf9,0xfe,0x7f,0xe7,0xff,0xf1,0xfc,0xff,0x1f,0xdf,0xf7,0xf5,0xfd,
+  0x7f,0xcf,0xd3,0xfe,0xfd,0x3f,0xcd,0xfc,0xff,0x77,0x4f,0xd7,0xf5,0xff,0xff,0x5f,
+  0xd7,0xff,0xfd,0x7f,0xff,0xff,0xff,0xe0,0xff,0xfe,0xff,0xbf,0xef,0xeb,0xfe,0xfa,
+  0xbf,0xef,0xe9,0xfa,0x7e,0xdf,0xa7,0xf9,0xef,0xbf,0xef,0xab,0xfa,0xfe,0xff,0xff,
+  0xeb,0xfa,0xff,0xff,0xaf,0xbf,0xff,0xff,0xfd,0x1f,0xff,0xdf,0xf3,0xff,0xfd,0x7f,
+  0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xff,0xf5,0xff,0xff,0xbb,0xff,0xff,0x3f,0x5f,0xd7,
+  0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0x5f,0xff,0x93,0xff,0xfb,0x7a,0x5f,0xb7,
+  0xaf,0xff,0xbb,0xdf,0xb7,0xa7,0xf9,0xff,0xde,0x9f,0xf6,0xff,0x7f,0xdb,0xa7,0xfb,
+  0x7b,0xdf,0xff,0xad,0xef,0x7f,0xff,0xf3,0xff,0xeb,0x7f,0xf8,0x3f,0xbe,0xbf,0xef,
+  0xfd,0xf7,0x7d,0xbf,0x6e,0xff,0xf2,0xfd,0x3f,0x6f,0xfb,0xfc,0xff,0xf7,0xff,0xf4,
+  0xfd,0x3f,0xef,0xff,0xf2,0xec,0xbf,0xff,0xd3,0xf4,0xfd,0x3d,0xfe,0x2f,0xff,0xfa,
+  0x7e,0xbf,0xaf,0x6b,0xfa,0x7e,0x8f,0xae,0xeb,0x5a,0xb6,0xaf,0xa7,0xeb,0x5e,0xbf,
+  0xad,0x6b,0xba,0xbe,0x3f,0xaa,0xe1,0x3a,0xde,0xbd,0xa7,0xeb,0xd2,0xff,0x61,0xff,
+  0xff,0xd9,0x7b,0xff,0xff,0x73,0xfc,0x3f,0xf7,0xff,0x7f,0x7d,0x37,0x7f,0xb3,0x7f,
+  0xfb,0xdd,0xf1,0xff,0x7d,0xff,0xfc,0xfd,0xdc,0xff,0xff,0xff,0x6f,0xbc,0xff,0xfa,
+  0x17,0xf7,0xfe,0xfe,0x7f,0xf7,0xf9,0xf1,0xf6,0xff,0xf7,0xdf,0xfa,0xfc,0xdc,0xbb,
+  0xeb,0xff,0xfb,0xbc,0xbd,0xdb,0xfc,0xff,0xf7,0xdf,0xff,0xff,0xdf,0xff,0xf7,0xed,
+  0xfe,0xb7,0xfb,0xfa,0xfd,0xff,0xfa,0xfb,0xbd,0xf3,0xff,0xef,0xfe,0xfc,0xe3,0xff,
+  0xff,0xdf,0x9e,0xbf,0xf7,0xfd,0xff,0xff,0xff,0xef,0xff,0xcf,0xff,0xff,0xff,0xff,
+  0xcf,0xff,0xe4,0x5f,0x9f,0xbe,0x3f,0xef,0xf9,0xf8,0xff,0xff,0xf7,0x63,0xfe,0xde,
+  0xaf,0xef,0x65,0xff,0x9f,0xaf,0x69,0xfb,0xff,0xf3,0xe3,0xeb,0xda,0xf7,0xff,0x8d,
+  0xff,0xfb,0x7f,0xff,0x5f,0xff,0xff,0xef,0xff,0xd6,0xde,0xff,0xbf,0xdf,0xfe,0xfd,
+  0x7f,0x57,0xf7,0xff,0xe7,0xff,0xdd,0xf7,0xbe,0xdf,0xff,0x7f,0xff,0xbf,0x6e,0xff,
+  0xeb,0x7f,0xff,0xdf,0xfe,0xb9,0xff,0xff,0xbf,0xfa,0xbf,0xff,0xed,0xbf,0xef,0xd6,
+  0xfe,0xff,0x7e,0xe7,0xba,0xff,0xeb,0xde,0xfb,0x3f,0xff,0xbf,0xf6,0x1f,0xbd,0xfb,
+  0x7f,0x7f,0xff,0xff,0xff,0xff,0xfa,0x7f,0xfb,0xff,0x6e,0xef,0xf5,0xfd,0x7f,0xfb,
+  0xff,0xbe,0x7d,0xf7,0x2f,0xdf,0xfe,0xfc,0xff,0xbb,0xfe,0xff,0xbf,0xff,0xdf,0xff,
+  0xfc,0xff,0xff,0x7b,0xff,0xdf,0xbf,0xfe,0xaf,0xfb,0xfd,0x7b,0xbf,0xff,0xf7,0xff,
+  0x5f,0xff,0x9b,0xff,0xbb,0xef,0xfb,0x5f,0xef,0xbe,0xf7,0xff,0xf7,0x7d,0x7f,0xde,
+  0xdd,0xf7,0xbf,0xbf,0xff,0xff,0xfd,0xff,0xed,0xd5,0x7f,0xfb,0x5c,0xfa,0x2e,0xbf,
+  0xef,0xdc,0x9e,0x3f,0xcf,0xa3,0xf3,0xb6,0xbe,0xcf,0x74,0xf5,0x2f,0xff,0xf1,0x58,
+  0xfe,0xff,0x7f,0xd3,0xff,0xef,0xff,0xff,0xff,0xff,0xfe,0xaf,0xfb,0x7f,0x5f,0xf7,
+  0xff,0xbf,0xff,0xdf,0xf7,0x33,0x7f,0x79,0xff,0xfb,0xeb,0x7e,0xdb,0xfd,0xff,0xff,
+  0x7f,0xdf,0xff,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0x13,0x7a,0xf7,0xba,
+  0xfe,0x67,0xde,0x7e,0xfb,0xde,0xff,0xdd,0xe7,0xef,0xcd,0x37,0xfe,0xf8,0xde,0xfe,
+  0xff,0xd3,0xeb,0xff,0xf7,0xff,0xeb,0xff,0xf7,0xff,0xfb,0xff,0xff,0xee,0xef,0xff,
+  0x7f,0xf7,0xef,0xff,0x3a,0xbf,0xfd,0xee,0xf7,0x7e,0xee,0xbf,0xfd,0xff,0x7f,0x77,
+  0x2e,0xff,0xff,0xde,0xbf,0xab,0xfe,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xfb,0x1f,
+  0xff,0x7f,0xff,0xf3,0xfd,0xff,0xff,0xff,0xfb,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,
+  0xff,0xef,0x6f,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0x7f,0xff,0xfb,0xff,
+  0x80,0xff,0x5c,0xcb,0xdf,0xf7,0xb3,0xfc,0xfb,0xde,0xfd,0x33,0x2f,0xff,0xff,0xdf,
+  0xb6,0x7f,0x93,0xcc,0xf1,0xec,0xfb,0xfe,0xdf,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xcf,0x6b,0xe7,0xfa,0x1a,0x8f,0xf7,0x7f,0xdf,0x7b,0xdf,0x3f,0xbd,0xff,0xff,
+  0xdf,0xf7,0xeb,0xff,0xff,0xaf,0xbd,0xbf,0xdf,0xdf,0xf7,0xfc,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xd6,0x4f,0x7f,0xa9,0x5f,0xd2,0xf4,0xfd,0x7f,0x4f,0x9a,0xfe,0xed,0x3f,
+  0x5f,0x9b,0xde,0xff,0xfe,0x7f,0x3e,0xaf,0xbf,0xef,0x1f,0xfe,0xf9,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xfb,0xcd,0xbf,0x95,0xcd,0xff,0x5e,0xdf,0xff,0xe5,0x73,0x5f,0xff,
+  0xf5,0xef,0xff,0x7f,0xdf,0xff,0xff,0xbe,0x57,0xf7,0xff,0x79,0xff,0xdf,0x97,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdb,0x3f,0xff,0xff,0xac,0xdd,0xe3,0x7d,0xfd,0x35,0x4f,
+  0xfb,0xfe,0x92,0x2f,0xdb,0xfb,0xff,0xff,0xfc,0xff,0xfe,0xff,0xb6,0xcb,0xfb,0xfe,
+  0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0x16,0xff,0xfd,0xf5,0x7f,0xfd,0x6f,0x75,0xe7,
+  0x59,0xff,0xf7,0xd5,0xfd,0x61,0xdf,0x77,0xfe,0xff,0xff,0xf7,0xdd,0xfd,0xe9,0x5f,
+  0x77,0xdc,0xaf,0xff,0xff,0xff,0xff,0xff,0x70,0x7f,0xfa,0xde,0xbf,0xfd,0xef,0xdf,
+  0xd2,0xfd,0x2f,0xef,0xfa,0xfe,0xfd,0xaf,0xef,0xff,0xdf,0xfd,0x6b,0xfb,0xfe,0xff,
+  0xaf,0xef,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0x13,0xff,0x5f,0xd5,0xfb,0xff,
+  0xb8,0xfc,0x51,0xa5,0xff,0xff,0x47,0xf7,0x15,0xcd,0xfa,0xfe,0xfe,0xe1,0x7f,0x7f,
+  0xf3,0xf5,0xfd,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0x9b,0xfe,0xdf,0xff,0x47,
+  0xd3,0x77,0xff,0xff,0x47,0xf3,0x7e,0xdd,0x7f,0x6f,0xfb,0x7f,0xff,0xdf,0xdf,0xff,
+  0xff,0xb7,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xef,0xff,
+  0xe7,0xf8,0xbf,0xff,0xf9,0xee,0x7d,0xbf,0xe7,0xbb,0xfe,0xbf,0xbf,0xef,0xfb,0xff,
+  0xff,0xff,0xf9,0xf7,0xff,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xfe,0x87,0xfb,
+  0xef,0x59,0xfe,0x39,0x9f,0x6f,0xd9,0xfe,0xf9,0xbf,0x67,0x9b,0xbe,0xfb,0xb3,0x7b,
+  0xfe,0x7f,0xbf,0xed,0xdb,0xf6,0xff,0xbf,0x6d,0xfb,0xfe,0xff,0xbf,0x6f,0xff,0xa1,
+  0xbf,0xff,0xfb,0xef,0xf1,0xbf,0xcf,0xf7,0xfe,0xf9,0xbf,0x6f,0xf3,0xfe,0xff,0xff,
+  0xcf,0xfe,0xff,0xff,0xef,0xf3,0xe6,0xff,0xff,0x6f,0xbf,0xff,0xff,0xff,0xcf,0xff,
+  0xdc,0x3f,0xff,0xfe,0xfb,0xff,0xdf,0xfb,0xff,0xff,0x7f,0xdf,0xfb,0xfe,0xfe,0xff,
+  0xff,0xfb,0xff,0x7f,0xff,0xf7,0xfe,0xff,0x7f,0xff,0xef,0xff,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xe5,0xff,0xf7,0xfe,0x7f,0x9f,0xcf,0xf7,0xb4,0xed,0x7f,0xdf,0xd1,0xec,
+  0x7f,0x7f,0x5f,0xe5,0x7b,0x1f,0xff,0xd7,0xf7,0xff,0xff,0xfe,0xd7,0xff,0xfd,0x7f,
+  0xff,0xb7,0xff,0xf4,0xff,0xfe,0x77,0xcf,0xfb,0xcb,0xfe,0x7e,0xaf,0xaa,0x49,0xfa,
+  0xbf,0xbf,0xe7,0xc9,0xf6,0x8f,0xaf,0xff,0xfa,0x7d,0xcb,0x67,0xff,0xfa,0x3f,0xff,
+  0xa7,0xff,0xfb,0x7f,0xff,0x1f,0xff,0xdf,0xdf,0xbf,0xff,0x7b,0xdf,0xd7,0xb5,0xff,
+  0x77,0x5e,0xff,0xf5,0xff,0xff,0x95,0xfc,0xff,0xff,0xfe,0xdf,0xff,0xdf,0xff,0x5f,
+  0xff,0xe5,0xff,0xff,0xdf,0xff,0x0b,0xff,0xfb,0xe6,0x71,0xda,0x2f,0x9b,0xe2,0xe8,
+  0xfe,0x2f,0x89,0xe7,0x78,0xbe,0x7f,0x9a,0xe8,0xbe,0x7f,0x9f,0xe7,0xf9,0xbe,0x7f,
+  0x8b,0xe7,0xf8,0xbe,0x7f,0x8f,0xe7,0xf9,0x7f,0xff,0x3f,0xef,0xb3,0xfc,0x7f,0x1f,
+  0x47,0xd7,0xf4,0xfd,0x3f,0xc7,0xd3,0xf4,0xff,0x5d,0xf7,0xfe,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0x7f,0xfe,0x8f,0xff,0xe7,0xff,0xfa,0xfa,0xbf,
+  0xef,0xeb,0xea,0xfe,0x9f,0xaf,0xff,0xfe,0x7e,0x9f,0xef,0xeb,0xff,0xff,0xaf,0xff,
+  0xfe,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xff,0xd4,0xff,0xfd,0xff,0xbb,0xed,
+  0xf7,0xff,0xff,0x77,0xdf,0xf7,0xfc,0xff,0xff,0x5f,0xff,0xf9,0x7f,0xdf,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xf8,0xbf,0xff,0x9f,0xfd,
+  0xff,0x7a,0x7f,0x9f,0xa4,0xef,0x7e,0x7e,0x97,0xf7,0xe9,0xff,0x7f,0xbd,0xef,0xff,
+  0x7f,0xff,0xfd,0xfb,0xff,0xff,0xf7,0xff,0xff,0xff,0xfe,0xff,0xff,0x47,0xff,0xfe,
+  0xf6,0xbf,0xff,0xcf,0xfc,0xf6,0xfd,0xff,0x76,0xdf,0xf6,0xfd,0xbf,0x2f,0xff,0x7f,
+  0xff,0xff,0xfd,0xbf,0xfd,0xff,0x6f,0xcb,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,
+  0xef,0xaf,0xea,0xfa,0xbe,0xbf,0xae,0xe9,0xda,0xae,0x8f,0xae,0xeb,0xb2,0xf6,0xbd,
+  0xeb,0xfa,0x7e,0x8f,0xa7,0xeb,0x3a,0xfe,0x9d,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xf6,
+  0x1f,0xef,0xf7,0xc1,0xff,0xfb,0x1f,0xcf,0xdb,0x7f,0xff,0xf7,0x8f,0xdf,0xe7,0x7f,
+  0xf6,0xff,0x6f,0xff,0x9f,0xff,0xf3,0xff,0xdc,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xc9,0xff,0xdf,0xea,0xfd,0xf2,0xdf,0xcb,0xfd,0xf7,0xff,0xff,0xd3,0xf7,0xdf,
+  0xee,0xff,0xff,0x7f,0xfd,0xbf,0xde,0xff,0xdf,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xeb,0x7d,0xff,0xf7,0xff,0x7e,0xfa,0xfb,0xea,0xfd,0xfe,0xff,0xff,0xef,
+  0xef,0xbb,0xef,0x3d,0xff,0xfb,0x6f,0xbf,0xfc,0x4f,0xfe,0xff,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xfe,0x25,0xbd,0xff,0xab,0xfe,0xbd,0xdf,0xa7,0xeb,0xaa,0xf6,0x27,
+  0xa7,0xe7,0x79,0x97,0xff,0xe3,0xd8,0xf7,0xfe,0xb7,0xeb,0xdf,0xdf,0xdd,0xaf,0x3f,
+  0xf8,0xff,0xfb,0xff,0xff,0xf5,0xff,0x5f,0xf7,0xbd,0xff,0xff,0xf5,0xf7,0x7f,0xeb,
+  0x6f,0xde,0xff,0xff,0xff,0xff,0xfd,0xfe,0xff,0xff,0xed,0xfd,0x97,0xff,0xbf,0xed,
+  0xff,0xff,0xbe,0xff,0xff,0xbf,0xfa,0x9f,0xff,0x37,0x3e,0xef,0x6c,0xef,0xaf,0x87,
+  0xef,0xb6,0x7e,0xf2,0xff,0x7f,0xfc,0xfe,0x7e,0xef,0xfe,0xff,0xfd,0xef,0xff,0xde,
+  0xfe,0x3f,0xfd,0xff,0xff,0xef,0xff,0xff,0x14,0xfb,0x9b,0x77,0xfd,0x3f,0x7f,0xcf,
+  0xa7,0xff,0xff,0x3f,0xdf,0xff,0xff,0xff,0x5f,0xde,0xfb,0xe3,0xe7,0xfb,0xf3,0xbd,
+  0xbf,0x3f,0xfb,0xff,0xff,0xff,0xff,0xfe,0xff,0xf6,0xff,0xfb,0xc7,0xb7,0xff,0xfb,
+  0x7b,0xfe,0xeb,0x7f,0xfb,0xfe,0xdf,0xff,0xff,0xff,0xd9,0xf5,0x7f,0xfd,0xff,0xfb,
+  0xaf,0xbf,0xfb,0xff,0xff,0xf7,0xfb,0xff,0xdf,0xff,0xfc,0x1f,0xff,0x3f,0xff,0x7f,
+  0xf4,0x7f,0x37,0xce,0xd6,0xf7,0xf7,0x3f,0xcf,0x73,0xff,0xf6,0x4f,0x7f,0xbf,0xff,
+  0xfd,0xcf,0xb3,0xfc,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xfd,0xd3,0xff,0xf6,0xe7,
+  0xbf,0xff,0xef,0xf7,0x3d,0xf6,0xf7,0x7f,0xf7,0xfd,0xef,0x7d,0xff,0xed,0xdf,0xfe,
+  0xff,0x7f,0x7d,0xff,0x7f,0xdd,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xf8,0x3b,0xee,
+  0xfb,0xcc,0xd7,0xf5,0xfe,0xbf,0x9f,0xfb,0xfe,0xc8,0x3c,0xbb,0xe5,0xfe,0xeb,0xbe,
+  0xd7,0xff,0xdb,0xff,0x9b,0xab,0xb9,0xef,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xed,
+  0xff,0xff,0xff,0xff,0xff,0xb6,0x6f,0xdf,0xfa,0xee,0xaf,0xee,0xff,0xef,0xf7,0xff,
+  0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xb5,0xff,0xff,0xfd,0xff,0xff,0xaf,0xfb,0xfd,0xff,0xff,0xff,0xfd,0x5f,0xff,0x7f,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xfb,0xff,0xf7,0xef,0xff,0xff,0xff,0xff,
+  0xfe,0xfe,0x8f,0xf5,0xff,0xb3,0xef,0xff,0x3f,0xef,0xbe,0x7c,0xff,0x7e,0xff,0xfd,
+  0xff,0x9b,0x27,0xbf,0xfc,0xff,0xff,0xcf,0xff,0xef,0x7b,0xc7,0xcf,0xff,0xfc,0xff,
+  0xff,0xff,0xfd,0x44,0xac,0xff,0xff,0x7c,0xf9,0xee,0x7f,0xf7,0xcf,0x3f,0x3f,0xde,
+  0x3f,0xfc,0xf9,0xde,0xb7,0xe6,0xcf,0xfe,0xbd,0xff,0xfd,0xff,0xfc,0xcf,0xff,0xff,
+  0xdf,0xff,0xff,0xfd,0x44,0xd5,0xff,0xf3,0xff,0xaf,0xff,0x1f,0xb5,0xfc,0xff,0xfb,
+  0xfb,0xff,0xff,0xef,0xee,0xfe,0xff,0xef,0xff,0xff,0xf5,0xfd,0x2f,0x2b,0x9e,0xbf,
+  0xff,0xff,0xff,0xff,0xe7,0xbc,0x5b,0xf9,0xfe,0x7f,0xf5,0xe7,0xf9,0xff,0xff,0x3f,
+  0xcd,0xf9,0x5f,0xff,0xf7,0xff,0x7f,0xdf,0x37,0xff,0xff,0xfe,0x7f,0x95,0xe5,0x7b,
+  0x7f,0xff,0xff,0xff,0xff,0xfe,0xfd,0xf1,0x7f,0xdf,0x7f,0x6c,0xbd,0x7f,0xff,0x7a,
+  0xff,0xff,0x3f,0xcb,0xb7,0xdf,0x93,0x2f,0xfb,0x5f,0xbb,0x2f,0xff,0xff,0xed,0xff,
+  0xaf,0x8f,0xb7,0xff,0xff,0xff,0xff,0xef,0xea,0x6d,0xe3,0xe6,0xff,0xd5,0xef,0x7b,
+  0xff,0x5f,0xff,0x87,0x61,0xdf,0xff,0xdd,0xe5,0x7b,0x7f,0xfd,0xe7,0x7f,0xff,0xff,
+  0xff,0xf5,0x51,0xda,0xff,0xff,0xff,0xff,0xff,0xf7,0xcd,0xff,0xfd,0xff,0xda,0xfb,
+  0xfe,0xbf,0xeb,0xff,0xf6,0xbd,0x2f,0xfe,0xfe,0xd0,0xbe,0xcf,0xff,0xda,0xbf,0xff,
+  0xfb,0xfa,0xde,0xbf,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0xbf,0xfd,0xff,0xfd,
+  0x5e,0x9f,0xf7,0x7d,0x7f,0xfc,0x57,0xa5,0xff,0xff,0x66,0xd7,0xfd,0xdf,0xff,0xdf,
+  0xff,0xfd,0xff,0x5f,0xd7,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x17,0xe7,0xf3,
+  0x7f,0xff,0xb7,0xed,0xf7,0xfc,0xdf,0x9f,0xe7,0xf1,0xf5,0xfd,0x27,0xed,0xf4,0x7f,
+  0x9f,0xed,0xf9,0xfc,0x7f,0x37,0xcd,0xfb,0xfe,0xff,0xff,0xff,0xff,0xfe,0x77,0xff,
+  0xff,0xff,0xff,0xf9,0xfe,0x7b,0x9f,0x7f,0xff,0xff,0xfd,0xfe,0x7f,0xaf,0xfe,0x7e,
+  0xa7,0xf9,0xfe,0xff,0xbf,0x7f,0xdb,0xfe,0xff,0x8f,0xfb,0xff,0xff,0xff,0xff,0xac,
+  0x7f,0xfe,0xf5,0xb5,0x6f,0xfb,0xfe,0x7d,0xbf,0x6f,0xfb,0xfe,0xff,0x8d,0x67,0xfb,
+  0x57,0x9d,0x6f,0xfb,0x66,0xe5,0xbf,0x6f,0x1b,0x46,0xd5,0xbf,0xef,0xfb,0xfe,0xff,
+  0xfb,0x9f,0xfe,0xff,0xbf,0xff,0xfb,0xff,0xf1,0xbe,0x6f,0xff,0xfe,0xfb,0xfe,0xef,
+  0xff,0xfe,0xbf,0xef,0xff,0xf6,0xff,0xbe,0x6f,0xbb,0xfe,0xff,0xbf,0xff,0xff,0xff,
+  0xff,0xfd,0x8b,0xff,0x7f,0xef,0xff,0xfd,0xff,0xff,0xdf,0xfb,0xff,0xff,0xbf,0xff,
+  0xef,0xff,0xfe,0xff,0xfb,0xff,0xff,0x7f,0xbf,0xef,0xfb,0xfe,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xf3,0x7f,0xff,0xff,0xef,0xff,0xbd,0xed,0x2f,0x7f,0xf9,0xbf,0xff,
+  0x7f,0xe7,0xd3,0xff,0xfe,0xe7,0xf7,0xff,0xff,0x7f,0xde,0xff,0xf5,0xfb,0x7f,0xdf,
+  0xff,0xff,0xff,0xff,0xff,0x4f,0xff,0xf3,0xfb,0xf7,0x7f,0xdd,0xab,0x7a,0xbf,0xff,
+  0xdd,0xa2,0x7e,0xfa,0xbf,0xdf,0xfe,0xfa,0x7d,0xdd,0x37,0x6e,0xbe,0xae,0xaf,0xa7,
+  0xcd,0xff,0xff,0xff,0xff,0xff,0xd0,0xff,0xff,0xef,0xfb,0x7f,0xff,0x3d,0xfd,0x77,
+  0xf7,0xff,0xf5,0xff,0xff,0x5f,0xd7,0xf9,0x7f,0xfe,0xff,0xf5,0xef,0x77,0xff,0xd7,
+  0xf5,0xff,0x7f,0xff,0xff,0xff,0xff,0xf7,0xbf,0xfe,0xfe,0x6f,0x9f,0xe7,0xe9,0xbe,
+  0x6f,0x9f,0xe7,0xf8,0xbe,0x77,0x8f,0xe2,0xf9,0xa7,0x9f,0xc7,0xf8,0xbe,0x2f,0x9b,
+  0xc2,0xf8,0xba,0x3f,0x9f,0xe7,0xf9,0xfe,0x7f,0x67,0xff,0xff,0xfe,0x7f,0x9f,0xfd,
+  0xd7,0xff,0xff,0xff,0xcf,0xf7,0xfe,0xfd,0x1f,0xef,0xfe,0xff,0x7e,0x6f,0xf7,0xfd,
+  0xfd,0x7e,0x5f,0xf7,0xf5,0xff,0xff,0xff,0xff,0xef,0xf8,0xff,0xbf,0xff,0xbf,0xff,
+  0xff,0xea,0xff,0xff,0xff,0xfb,0xfa,0xff,0xff,0xbf,0xff,0xff,0xff,0xaf,0x6d,0xfb,
+  0xfe,0xff,0xaf,0xeb,0xfa,0xfa,0xbf,0xff,0xff,0xff,0xff,0xfd,0x8f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x5f,0xf7,0xf7,0xff,0xbf,0xdf,0xfb,0xf5,0xfd,0x3f,0xb3,0xff,0xfd,
+  0x7f,0x5f,0xf7,0xff,0xef,0x7f,0xdd,0xf7,0xff,0xff,0xff,0xff,0xff,0x93,0xbf,0xfd,
+  0x7e,0x7f,0xdf,0xf7,0xeb,0x7e,0xdf,0xdf,0xf7,0xfb,0x7f,0xde,0x97,0xa7,0xfb,0x5f,
+  0xdd,0xa7,0xe9,0xfa,0xdf,0xb7,0xad,0xef,0xfb,0xff,0xff,0xff,0xff,0xdf,0xf1,0x7f,
+  0xfd,0xff,0x4f,0x73,0xb6,0x7d,0xaf,0x6f,0xd9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x67,0xfd,0xf7,0xff,0xff,0xff,0x5b,0xf7,0x7c,0x9f,0xff,0xff,0xff,0xff,0xff,0xee,
+  0x2f,0xff,0xba,0xf6,0xbf,0xaf,0x6a,0xda,0xfe,0x37,0xa7,0xcb,0x72,0x7e,0xbf,0xab,
+  0xeb,0x56,0xbf,0xae,0xeb,0x7a,0xfe,0xb7,0x8e,0xeb,0xba,0xfc,0xbf,0xaf,0xeb,0xfa,
+  0xff,0x49,0xff,0xff,0xdb,0x3f,0xfb,0xdf,0x74,0xf8,0xdf,0x37,0xfb,0x3f,0xff,0x6e,
+  0xcd,0xf3,0xfd,0x16,0xdd,0xff,0xfc,0xf7,0xff,0x37,0xbf,0xff,0xef,0xff,0xcf,0xff,
+  0xff,0xff,0xfe,0x9f,0xfd,0xff,0xbf,0xfd,0xff,0xef,0x7f,0xff,0xbe,0xed,0xdf,0xff,
+  0x7f,0xef,0xb5,0x3b,0xdf,0x7f,0xff,0x7f,0xff,0x7d,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0xf7,0x7e,0x64,0xff,0xff,0xbc,0xfb,0xcf,0xf7,0x6b,0x6f,0xbb,0xdf,0xff,
+  0xfe,0xfd,0xaf,0x5f,0xc7,0x9b,0xfe,0xfe,0xfb,0x8d,0xff,0xfb,0xfa,0xff,0xfe,0x7f,
+  0xfc,0xff,0xff,0xff,0xff,0xee,0x7f,0x78,0xbf,0xf7,0x8f,0xe5,0xfa,0xfe,0xbf,0xa7,
+  0x6f,0xfe,0xff,0xff,0xad,0xdf,0xfe,0x3c,0xff,0xe3,0xff,0xf7,0xfd,0xa6,0xe9,0xfa,
+  0xfe,0xbf,0xff,0x7f,0xff,0xff,0xef,0x5f,0xfd,0x7f,0xbf,0xd7,0xdf,0xf5,0x6f,0xfb,
+  0x75,0xff,0xbf,0x7f,0xff,0xf6,0x7f,0xfb,0xdf,0xef,0xfe,0xff,0xfb,0xff,0xf5,0xd7,
+  0x7d,0xdf,0xfb,0xbf,0x7f,0xff,0xff,0xff,0xc9,0xff,0xff,0xbc,0x57,0x3f,0xef,0xfd,
+  0x5a,0xf7,0x9a,0xcf,0x7b,0xbe,0x7f,0xdf,0xcb,0xec,0xff,0xff,0xed,0xfb,0xaf,0x5f,
+  0xff,0xbf,0x6f,0x7b,0xff,0xff,0xfd,0xff,0xff,0xfb,0x7f,0xff,0x9f,0x7f,0xdf,0xff,
+  0xbf,0xfe,0xbf,0xcf,0xff,0xbc,0xff,0x7f,0xd7,0xf5,0xe9,0x77,0xfb,0xf3,0xb8,0xbf,
+  0x5f,0xdf,0xfe,0xff,0xff,0xef,0xff,0x7f,0xff,0xff,0xff,0x4e,0xbf,0xfd,0xda,0xde,
+  0xbf,0xd7,0x7f,0xff,0xf6,0xff,0xef,0x6f,0xcc,0xff,0xbf,0xff,0x9b,0xff,0xdd,0xbf,
+  0xbf,0xff,0xfe,0xff,0xef,0xfd,0xff,0xdf,0xff,0xfe,0xff,0xff,0xc1,0x76,0xff,0x7c,
+  0xfb,0x3f,0xfd,0xd3,0xd8,0xfd,0xaf,0xcc,0xf3,0x7c,0xf6,0x3b,0x9f,0xf4,0xbb,0x37,
+  0xff,0xef,0xd0,0x7f,0x3f,0xff,0xb3,0xff,0xef,0xff,0xff,0xff,0xff,0xfc,0x3e,0xff,
+  0xff,0xdc,0xe7,0xdf,0xef,0x7d,0xf7,0x77,0xed,0xf7,0x79,0xdf,0xf7,0xfb,0xff,0xdf,
+  0xf7,0xdf,0xff,0xff,0xde,0x0d,0xff,0xfd,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0x07,
+  0xff,0xbb,0xfb,0xff,0xe6,0xdf,0x46,0x6b,0xff,0xfb,0x9f,0xef,0xfb,0xce,0x73,0xcb,
+  0xb9,0xde,0xff,0xfe,0xbf,0xfd,0xf7,0x7e,0xdf,0xef,0xbf,0x7f,0xff,0xff,0xff,0xfe,
+  0xee,0x7f,0xff,0x4e,0xbb,0xef,0x73,0x96,0xfe,0xb2,0xff,0xf3,0xbf,0xd5,0xbf,0xef,
+  0xfd,0xff,0x3f,0x2e,0x7f,0xdf,0xff,0xbf,0xd7,0xf7,0xf2,0xff,0xef,0xff,0xff,0xff,
+  0xff,0xdb,0x97,0xff,0xff,0xff,0xfb,0xfe,0xff,0xd3,0xff,0xff,0xff,0x7f,0xff,0xef,
+  0xf5,0x7d,0xff,0xef,0xff,0xff,0xff,0xff,0xd7,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xa8,0xff,0xfd,0xfb,0xff,0xdd,0x73,0xff,0x1f,0x35,0xcf,0xbf,0xff,
+  0xfb,0xff,0xcc,0xf3,0xff,0xff,0xfc,0xb1,0xff,0xff,0xff,0xc7,0xf7,0xec,0xfb,0xff,
+  0xdf,0xff,0xff,0xff,0xc4,0x4b,0xfc,0xff,0xbf,0xff,0xa7,0xfd,0xff,0xff,0xe7,0xf7,
+  0xfc,0xf3,0x3f,0xf5,0x9e,0xff,0xff,0xff,0x91,0xff,0xff,0x9f,0xfb,0xff,0xff,0x39,
+  0x7f,0xff,0xff,0xff,0xff,0xd7,0x4d,0x7f,0xef,0xeb,0xd7,0xc7,0xef,0xae,0x7e,0x1e,
+  0x32,0xff,0xef,0xeb,0x4f,0xfe,0xff,0xff,0xff,0xff,0xad,0x7f,0x5f,0x7b,0xff,0xf9,
+  0xfd,0xef,0xff,0xff,0xff,0xff,0xfb,0xed,0xbf,0xf7,0xcd,0x7b,0xff,0xff,0xf5,0xff,
+  0xf3,0x96,0x5f,0xf7,0xcd,0x79,0xfe,0x5f,0x3f,0xff,0xfc,0xdf,0x9f,0xe7,0xff,0xff,
+  0xff,0xbf,0xfd,0xff,0xff,0xff,0xff,0xff,0xdf,0x9f,0xff,0xbf,0xad,0x9f,0xff,0xff,
+  0xff,0xbe,0xdd,0xfb,0xfe,0xbf,0xa7,0xfd,0xff,0x7f,0xa5,0xff,0xfa,0xff,0xff,0xff,
+  0xff,0xf7,0xfa,0xfb,0x3f,0xff,0xff,0xff,0xff,0xff,0xb6,0xff,0x9d,0xe5,0x93,0xda,
+  0xf6,0x9f,0xef,0x7f,0x1f,0x7f,0xdf,0xe4,0x7f,0xde,0xff,0xf5,0xbf,0xff,0x56,0xbd,
+  0xef,0x7f,0xf4,0xff,0xf5,0xa7,0x7f,0xff,0xff,0xff,0xff,0x7c,0x7f,0xee,0xf2,0xb7,
+  0xff,0xff,0xda,0xfb,0xff,0xf7,0xeb,0xfa,0xda,0xbd,0xff,0xbf,0xfe,0xbf,0xff,0xeb,
+  0x9f,0xe3,0xff,0xff,0xff,0x9f,0xfe,0xff,0xfd,0x5f,0xff,0xff,0xf9,0x93,0xff,0x7e,
+  0x57,0xf7,0xff,0xfd,0x5f,0xff,0xfe,0xfd,0x7f,0x7f,0xc3,0x1e,0xff,0xff,0xdb,0xaf,
+  0xfd,0x7b,0x7e,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,
+  0xff,0xef,0xdf,0xf9,0xfe,0xff,0x37,0xef,0xd9,0xfd,0xff,0x7f,0x5f,0xdb,0x7e,0xdf,
+  0x47,0xf3,0x7f,0xbf,0xa7,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,
+  0x7f,0xff,0xff,0xfb,0xff,0xbf,0xfb,0xdb,0xfe,0xbf,0xff,0x7f,0xc9,0xee,0xf9,0x9f,
+  0xe7,0xe6,0x7d,0xbf,0xef,0xf9,0xfe,0xbf,0xbf,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0xe7,0xff,0xef,0xdb,0xfe,0xf9,0xbd,0x6e,0xdb,0xbe,0xf5,0xbd,0x6f,0x59,0x36,
+  0x3f,0xbf,0x78,0xfe,0xe5,0xb3,0x6d,0xfb,0x96,0xed,0xbd,0x6e,0xfb,0x7e,0xff,0xbf,
+  0xef,0xdf,0x99,0xff,0xff,0xdb,0xfe,0xfd,0xff,0xef,0x9b,0xff,0xff,0xbe,0xef,0xbb,
+  0xf6,0xf3,0xff,0x6f,0xef,0xfb,0xbf,0x7f,0xff,0xfe,0xff,0x3f,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xdb,0xdd,0x3f,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xfd,0xff,0xff,0xbf,0xfb,
+  0xfe,0xff,0x7f,0xff,0xf7,0xff,0xfe,0xef,0xff,0xff,0xfe,0xff,0xef,0xf7,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0x57,0xfe,0xff,0xfd,0xff,0x7f,0xff,0xdf,0xbf,0xff,0xdf,
+  0x5f,0xd7,0xfe,0x7f,0x1f,0xef,0xe4,0x6f,0x7f,0x5e,0xdf,0xf5,0xff,0xbf,0x5f,0x9f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0xff,0xff,0xff,0xcf,0xf7,0xdd,0xfe,0xad,0xdf,
+  0xff,0x7a,0x9a,0xaf,0xef,0xab,0xff,0xfe,0xaf,0xeb,0xe9,0xfe,0x7c,0x9f,0x7f,0xe9,
+  0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xfd,0x4f,0xff,0xff,0xff,0xef,0xff,0xff,0xfc,
+  0xff,0x7e,0xfd,0x77,0x5f,0xff,0xb5,0x6f,0xff,0x9d,0xbd,0xfd,0x7f,0xff,0xf7,0xff,
+  0xed,0x7f,0x7e,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xfe,0xff,0xe7,0xf9,0xfe,0x7f,
+  0x1f,0xe7,0xf9,0xfe,0x6f,0x8b,0xe7,0x78,0xfe,0x7f,0x9f,0xf9,0xbe,0x2f,0x9f,0xe6,
+  0xf9,0xfe,0x2f,0x8f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xe2,0x7f,0xff,0xbf,0xff,0xfb,
+  0xfe,0x79,0x7f,0x4f,0xff,0xfd,0xff,0x7f,0xe7,0xd7,0xff,0xff,0xff,0xf3,0xf4,0x7d,
+  0x1f,0x4f,0xff,0xfc,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x0f,0xff,0xff,0xff,
+  0xff,0x7f,0xbf,0xef,0xe9,0xff,0xff,0xbf,0xaf,0xfb,0xfa,0xff,0xff,0xff,0xfe,0xfe,
+  0xbf,0xaf,0xe9,0xff,0xfe,0xbf,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xc4,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xbd,0xff,0x7f,0x7f,0xf7,0xfd,0xff,0xff,0x5f,0xdf,0xfb,0xff,
+  0xcf,0xdf,0xff,0xff,0x7f,0xff,0xf3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0xbf,
+  0xff,0xdf,0xfd,0xfd,0xff,0x77,0xb7,0xa7,0xfb,0xfe,0xde,0xf7,0xfd,0xeb,0x7b,0x7f,
+  0xfd,0xff,0x7e,0x7f,0xdf,0xe7,0xef,0xfa,0x7e,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,
+  0x77,0xff,0xff,0xf4,0xfd,0x3f,0xcf,0xda,0xf7,0xff,0x3d,0x7f,0xdb,0xf2,0x7d,0xff,
+  0xff,0x7a,0xbf,0xff,0xff,0xdf,0xf7,0xbd,0xbb,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,
+  0xff,0xe0,0xff,0xff,0xaf,0x6a,0xda,0xde,0x97,0xaf,0xe2,0xfa,0x6e,0x1f,0xae,0xe8,
+  0xba,0xfe,0xad,0xeb,0xf8,0xfe,0x9b,0xaf,0xeb,0xfa,0xde,0xbf,0x8b,0xcb,0xfa,0xfe,
+  0xbf,0xaf,0xff,0x5d,0xff,0xcd,0xff,0xbf,0xfb,0xff,0x36,0xaf,0xbe,0xbf,0xef,0x36,
+  0xfe,0xdd,0xdf,0xef,0xfd,0xfc,0x7f,0xff,0xfe,0xed,0xb2,0xff,0x3d,0xff,0xef,0xff,
+  0xff,0xff,0xff,0xfd,0xa1,0xef,0xff,0xff,0xfd,0xef,0x7e,0xbf,0xff,0x7d,0x6f,0x7f,
+  0xdf,0x77,0xff,0xba,0xfe,0xdf,0xfc,0xff,0xff,0xff,0xef,0xff,0x7b,0xae,0xbf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xea,0x5b,0xbd,0x5f,0xff,0xfe,0xff,0xfb,0xff,0xfd,0xff,
+  0xef,0xdf,0xff,0xfb,0xff,0xff,0xed,0xf7,0x37,0xff,0x7f,0xff,0xff,0xfd,0xff,0x7f,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xfe,0xef,0xff,0xff,0xef,0xfb,0x7c,0xd9,0xa7,0xcf,
+  0xf3,0xf6,0x3c,0x8f,0xe2,0xfa,0x7c,0x8f,0x7b,0xde,0xf6,0xbb,0xaf,0x5f,0xda,0xfe,
+  0xbe,0xef,0xfe,0xdf,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,0xf7,0x7f,0xef,0xfb,0xfd,
+  0xff,0xbd,0xed,0x5e,0x7f,0xde,0xdf,0x5f,0xf7,0xff,0xf7,0x77,0xfb,0xfd,0xff,0xf5,
+  0x99,0x67,0x7b,0xff,0xfb,0xff,0xff,0xff,0xff,0xfa,0x3f,0xfb,0xf7,0xfe,0x3b,0xef,
+  0xfe,0xfa,0xc6,0xfb,0xff,0xfe,0xbd,0xeb,0xbf,0xea,0xee,0x3f,0xfb,0xaa,0xfa,0xff,
+  0xcf,0xfb,0xfc,0xf7,0xfb,0xfd,0xff,0xff,0xef,0xff,0xfe,0xc7,0xff,0xbf,0xff,0xfd,
+  0xff,0xff,0xdb,0xf7,0xff,0xef,0x5b,0xce,0xf7,0xdf,0xbf,0xef,0xdf,0xfd,0xff,0xfb,
+  0xf9,0xff,0xfd,0xff,0x7c,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xf6,0xff,0xff,0xff,
+  0xff,0xb1,0xfe,0xbe,0xff,0xbd,0xf5,0xff,0xfb,0xd4,0xdd,0x7d,0xbd,0xdb,0xed,0xb5,
+  0xfd,0xff,0xff,0xff,0xe7,0xfb,0xff,0x9b,0xff,0xff,0xff,0xff,0xff,0xfd,0x9b,0xed,
+  0xff,0xfd,0x41,0xf0,0xfc,0x0d,0xcb,0xf3,0xff,0xed,0x3f,0xcc,0xf1,0xf8,0xfe,0x47,
+  0xf3,0xf7,0xee,0x3f,0xcf,0xde,0xff,0xf7,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,
+  0xff,0xff,0xdf,0xff,0xdd,0xdf,0xfb,0xf9,0xef,0x7f,0xff,0xed,0xfd,0xff,0xbd,0xde,
+  0xef,0x7d,0x7b,0x7a,0x36,0xfd,0xef,0xfb,0xfb,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf8,0x7f,0xfb,0xff,0xf7,0xbf,0x79,0xf3,0xef,0x5c,0xe1,0x2c,0xff,0x7f,0x8e,0xd7,
+  0xf8,0xfb,0xfd,0xe3,0xff,0xfe,0xf2,0x1b,0xf7,0xaf,0xfc,0x3f,0xdf,0xff,0xff,0xff,
+  0xff,0xfe,0x07,0xff,0xff,0xcb,0xfe,0x7f,0xb7,0xf7,0xfa,0xff,0xde,0x1f,0x8f,0xdb,
+  0xfe,0xbd,0xbf,0xfb,0xfc,0xfe,0x9f,0xff,0xfb,0xba,0xff,0xff,0xef,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xe5,0x7b,0x7f,0xff,0xff,0xbf,0xcd,0xff,0x7f,0x7f,0x7f,0xff,0xff,
+  0xfd,0x7f,0xbf,0xcf,0xff,0x5f,0xdf,0xff,0xef,0xff,0x7f,0x7e,0xff,0xfb,0xfd,0x7f,
+  0xff,0xff,0xff,0xfe,0xfa,0xaf,0xff,0xff,0xbf,0xfd,0xff,0xde,0xc7,0xbf,0xff,0xff,
+  0x3f,0xfc,0xbf,0xfc,0xcf,0xff,0xf7,0xff,0x9f,0xfe,0xff,0xff,0xff,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xc2,0xbf,0xcf,0xf3,0xff,0xff,0xff,0xca,0xf3,0xff,
+  0xff,0xd7,0xfe,0xa1,0xfe,0xa3,0xdf,0xfd,0xbc,0xf3,0xff,0xf6,0xf7,0xff,0x73,0x3f,
+  0xcf,0xff,0xff,0xff,0xff,0xff,0xfd,0x44,0xf7,0xfe,0xf4,0xbd,0x7d,0xeb,0xd2,0xfe,
+  0xb9,0xaf,0x3f,0xff,0xf2,0xbf,0xff,0xff,0xcf,0xf9,0xfe,0x7f,0x7f,0xff,0xf9,0xfe,
+  0x6b,0xca,0xff,0xff,0xff,0xff,0xff,0xe7,0xbd,0x5b,0xff,0x7e,0x57,0x9f,0xcd,0x7b,
+  0x5e,0xd7,0xf5,0xe7,0xff,0xfe,0x57,0xff,0xff,0x7b,0xff,0xbf,0xcf,0xfb,0xff,0xdf,
+  0x3f,0xed,0x79,0x7f,0xff,0xff,0xff,0xff,0xfc,0xfd,0xe9,0xff,0xdb,0xfa,0x7e,0xfd,
+  0x3d,0xa9,0xa2,0x7d,0xb5,0x77,0x4b,0xfb,0xcd,0xff,0xfd,0xbf,0xfa,0xb5,0x7f,0xad,
+  0xf2,0xcd,0xdc,0x27,0xfb,0xf7,0x7f,0xff,0xff,0xff,0xff,0xe5,0x6f,0xd1,0xde,0x4d,
+  0xbd,0xe7,0xbd,0x3e,0x4e,0x1e,0x6f,0xd9,0x5f,0x76,0xbd,0xef,0x5b,0xf7,0xd6,0xef,
+  0x6b,0x54,0x5a,0xbf,0xa4,0xf9,0xf8,0xff,0xff,0xff,0xff,0xff,0xf7,0xa7,0xff,0xef,
+  0xab,0xff,0xf2,0xbf,0xaf,0xab,0xfa,0xdf,0xff,0xaf,0xeb,0xff,0xfb,0xed,0xff,0xda,
+  0xdb,0xff,0xf7,0x4b,0xff,0xfe,0xbe,0xad,0xff,0xff,0xff,0xff,0xff,0xff,0x85,0xff,
+  0xf7,0xfd,0x3f,0xfc,0x57,0xf4,0xfd,0x3f,0x5f,0xff,0xf5,0xfd,0xdf,0xff,0xff,0x9f,
+  0xf1,0x5f,0xf7,0xfa,0xe9,0x7f,0xff,0xd3,0xf7,0xff,0xbf,0xff,0xff,0xff,0xff,0xfd,
+  0x9f,0xff,0xf9,0xf6,0xdf,0xff,0xcf,0xdf,0xf6,0x7f,0x7f,0xe7,0xff,0xf4,0xdf,0xff,
+  0x49,0xfe,0xff,0x37,0xed,0xdf,0xfc,0x7f,0xbf,0x7f,0xf7,0xf6,0xdf,0xff,0xff,0xff,
+  0xfe,0xb7,0xfe,0x7f,0x9f,0xef,0xf9,0xfe,0xbf,0xff,0xff,0xfb,0xfe,0x7f,0xfe,0x67,
+  0xf9,0xe7,0xff,0xfb,0xfb,0xfe,0xf9,0xff,0xff,0xfa,0xfe,0xfd,0x9e,0xef,0xff,0xff,
+  0xff,0xff,0xe6,0x7f,0xfe,0xff,0x93,0x6f,0xdb,0x96,0x7f,0x9d,0x6f,0x9b,0xfe,0xff,
+  0x9d,0x6f,0xf8,0x77,0xbf,0x6e,0xdb,0xb6,0x35,0xbd,0x6e,0x59,0xb6,0xff,0x9b,0xef,
+  0xfb,0xfe,0xff,0xfa,0xdb,0xff,0xff,0xff,0xdf,0xf3,0xee,0xff,0xff,0xff,0x9b,0xff,
+  0xff,0xfe,0xef,0xfb,0xec,0xff,0x6f,0xb3,0xf6,0xf3,0xfc,0xef,0xfb,0xf6,0xfb,0xbf,
+  0xff,0xff,0xff,0xff,0xfd,0x83,0xff,0xff,0xff,0xff,0xfe,0xff,0xbf,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xbb,0xfd,0xff,0xbf,0xfb,0xfe,0xff,0x7f,0xff,0xef,0xfb,0xff,0x7f,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xf1,0x7f,0xfd,0x7f,0x4f,0xff,0xff,0xfd,0x3f,0x4e,
+  0xdf,0xfe,0xfd,0x7f,0xe7,0xd7,0xe4,0x7a,0xff,0xf7,0xbf,0xff,0x1b,0x5f,0xfb,0xb4,
+  0xed,0xff,0x4f,0xff,0xff,0xff,0xff,0xff,0x6f,0xff,0xa7,0xeb,0xf7,0x7f,0xef,0xaf,
+  0x6b,0xfb,0xbf,0xfd,0xa7,0x7c,0xfa,0x76,0x8f,0xfd,0xff,0x3f,0xdf,0xb3,0x6a,0xff,
+  0xfe,0xbd,0xaa,0xeb,0xff,0xff,0xff,0xff,0xff,0xe0,0xff,0xef,0xfd,0x7b,0xfc,0xf7,
+  0xf5,0xfd,0x7f,0x5f,0xbf,0xfd,0xed,0xf7,0x5d,0xf7,0xfb,0xff,0xff,0xff,0xbd,0x6d,
+  0x77,0xff,0xd7,0xf7,0xfd,0x7f,0xff,0xff,0xff,0xff,0xf7,0xbf,0xff,0xfe,0x2f,0x9b,
+  0xe3,0xf8,0xbe,0x2f,0x8f,0xe7,0xf9,0xbe,0x37,0x8f,0xe2,0x79,0xff,0x9f,0xe7,0xf8,
+  0xfe,0x2f,0x9f,0xe2,0xf9,0xbe,0x2f,0x9f,0xe7,0xf9,0xfe,0x7f,0x27,0xff,0xd7,0xf5,
+  0xff,0xbf,0xdf,0xf7,0xf4,0xff,0xff,0xff,0xd3,0xfe,0xfd,0x7f,0xc7,0xfe,0xff,0xff,
+  0x7f,0xf3,0xfd,0xff,0xff,0x5f,0xdf,0xf5,0xff,0xff,0xff,0xff,0xff,0xe6,0xff,0xfa,
+  0xfe,0xbf,0xf7,0xfb,0xfb,0xfe,0x9f,0xff,0xff,0xfa,0x7f,0xff,0xaf,0xeb,0xff,0xdf,
+  0xff,0xff,0xfb,0xfe,0xbf,0xff,0xeb,0xfb,0xfe,0xbf,0xff,0xff,0xff,0xff,0xfd,0xcf,
+  0xf7,0xff,0xf7,0xff,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0xff,0xdf,0xfb,0xf5,0xff,0x7f,
+  0x9f,0xff,0xff,0xff,0xcf,0xf7,0xf7,0xff,0x7f,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,
+  0xc3,0xff,0xff,0xfa,0xff,0xdf,0xad,0xef,0xfe,0x7e,0xf7,0xef,0xf9,0xff,0xde,0xbf,
+  0xed,0xff,0x7f,0xf7,0xf7,0xef,0x7b,0xdf,0xff,0xb7,0xff,0x7a,0xff,0xff,0xff,0xff,
+  0xfe,0xfb,0x77,0xff,0xff,0x7f,0xd3,0xff,0xfd,0xff,0x67,0xff,0xf2,0xff,0xff,0x47,
+  0xff,0xf6,0xff,0x67,0xfe,0xf7,0xff,0xff,0x2e,0xdf,0xff,0xff,0xbf,0xf7,0xff,0xff,
+  0xff,0xff,0xdf,0x6f,0xff,0xfa,0xf6,0x9d,0x8f,0xeb,0xfa,0xf4,0xbf,0x2f,0x6b,0xfa,
+  0xf6,0xb7,0xab,0xe9,0xde,0xbf,0xaf,0xeb,0xf8,0xae,0x3b,0xaf,0xeb,0x7a,0xfe,0xbf,
+  0xaf,0xeb,0xfa,0xfd,0x59,0xbf,0xff,0xff,0xff,0xfb,0xff,0xfb,0xfd,0xf7,0xf4,0xf7,
+  0x7f,0xff,0x7f,0xfd,0xcd,0x6c,0xdf,0xff,0xef,0xfc,0xbf,0xfb,0xff,0xff,0xf7,0xff,
+  0x3f,0xff,0xff,0xff,0xff,0xff,0x1f,0xff,0xff,0x7f,0x7f,0xff,0xe3,0xfb,0x7f,0xfd,
+  0xf7,0xff,0xfe,0xef,0xff,0xf7,0xff,0xff,0xde,0xb7,0xf7,0x2f,0xff,0xff,0x77,0xfb,
+  0xff,0x3f,0xff,0xff,0xfd,0xff,0x7e,0x37,0xbf,0xff,0xff,0x7f,0xdf,0xff,0xfd,0xff,
+  0xff,0xef,0xbf,0xff,0xbf,0xef,0xef,0xff,0xde,0xeb,0xfb,0xe5,0xff,0xff,0xfb,0xdb,
+  0xf7,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xe4,0x1f,0xff,0xf7,0xff,0xaf,0xeb,0xb8,
+  0xff,0xbd,0x6f,0xe7,0xdf,0xfe,0x7f,0xef,0x3b,0xde,0xff,0xb6,0xcb,0xff,0x7f,0xa7,
+  0xbf,0xeb,0xfb,0xfe,0xbc,0xff,0xff,0xff,0xff,0xfe,0x9f,0xff,0xff,0xff,0xfa,0xfd,
+  0x77,0xbf,0xdf,0xdf,0xff,0xed,0xff,0xff,0x67,0xff,0xf7,0xfb,0x7e,0xfe,0x77,0xf9,
+  0xef,0xde,0x5f,0x75,0xef,0xb7,0xff,0xff,0xff,0xff,0xbd,0x99,0xfe,0xff,0xbc,0xfb,
+  0x3e,0xef,0xbf,0xfc,0x7e,0xfb,0xff,0xff,0xbf,0xff,0x3b,0xbf,0x8f,0xff,0xfe,0xcf,
+  0xfb,0xfc,0xdf,0xbe,0x3f,0xf3,0xb2,0xdf,0xff,0xfe,0xfe,0xff,0xfd,0x7f,0xfb,0xff,
+  0x7b,0xd7,0xd3,0xff,0xbf,0x5f,0xfd,0xff,0xdf,0xff,0x7e,0xff,0xff,0xfd,0x7f,0xfe,
+  0xe7,0xfd,0xdf,0x6f,0xc7,0xfe,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,0xfe,0x0d,0xff,
+  0xff,0x5a,0xdf,0xff,0xbf,0xfb,0xff,0xdf,0x9d,0xff,0xfd,0x7a,0x6f,0x97,0xff,0xaf,
+  0xff,0xff,0xbf,0xe7,0xee,0xff,0xff,0xfd,0xfd,0xbb,0xff,0xff,0xff,0xff,0xff,0xc5,
+  0xde,0xef,0xff,0xff,0xff,0xff,0xbf,0xfc,0xf7,0xff,0xcf,0xe3,0x7f,0xff,0x3f,0xcf,
+  0xf4,0xfd,0x3f,0xfd,0xff,0xbc,0xff,0xff,0xef,0x67,0xf0,0xff,0xff,0xff,0xff,0xff,
+  0xfa,0xbb,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xdf,0xff,0xfd,0xdf,0x7f,0xfb,0xf6,
+  0xbd,0xfe,0xdf,0xeb,0xef,0xdd,0xfe,0x5f,0x7f,0xfd,0xfc,0xff,0xdf,0xff,0xff,0xff,
+  0xff,0xff,0x33,0xff,0xbf,0xdd,0xff,0x7f,0x5f,0x97,0xf9,0xff,0xff,0xbd,0xeb,0xed,
+  0xdc,0x7b,0x8c,0xa9,0xdf,0x6f,0xdb,0xf7,0xfb,0xdf,0x7a,0x5f,0xd7,0xf1,0xff,0xff,
+  0xff,0xff,0xff,0xea,0xff,0xef,0xff,0x3b,0xff,0xfb,0xfe,0xbf,0xbf,0x76,0xdf,0xff,
+  0xef,0x3f,0xee,0xdf,0xbf,0xf7,0xcd,0xfb,0xbe,0xff,0xff,0x0e,0xdb,0xfe,0xbf,0xbf,
+  0xff,0xff,0xff,0xff,0xfa,0x1f,0xff,0xff,0xf7,0xf7,0xff,0x5b,0xdf,0xd7,0xff,0xff,
+  0xff,0xff,0xf7,0xfd,0xfd,0xdf,0x9f,0xfd,0x7c,0xff,0x57,0xfd,0xff,0xff,0x77,0xbf,
+  0xf7,0xff,0xff,0xff,0xff,0xbf,0xc2,0xff,0xef,0xd7,0x1f,0xff,0xff,0x3c,0xff,0xe7,
+  0xcf,0xff,0xff,0xff,0x3e,0xff,0xb7,0xfb,0xdf,0xff,0xf3,0xef,0xff,0xff,0xff,0xbf,
+  0x3f,0xfb,0xdf,0xff,0xff,0xff,0xff,0xca,0x2e,0xfd,0xf9,0xfb,0xff,0xff,0xbf,0xdf,
+  0xff,0xcd,0xff,0xff,0xff,0xf7,0xcf,0xf7,0xff,0x7f,0xff,0xf7,0x7c,0xff,0xff,0xff,
+  0xf3,0xeb,0xff,0x7f,0xff,0xff,0xff,0xff,0xd7,0x8e,0x5f,0xbf,0x5e,0xff,0xd3,0xff,
+  0xaf,0x5b,0xfe,0xdf,0xff,0xff,0x3f,0xca,0xfe,0xfc,0xff,0xff,0xff,0xbf,0xaf,0xff,
+  0x9f,0xf2,0x9c,0xf7,0xef,0xff,0xff,0xff,0xff,0xfb,0xc4,0xbf,0xf7,0xef,0xf3,0xfe,
+  0xff,0x95,0xfd,0xff,0x7f,0xff,0xff,0xcf,0xfb,0x5f,0xdf,0x3f,0xff,0xff,0xff,0x35,
+  0xe7,0xf3,0xfe,0xc7,0x3a,0xfd,0xff,0xff,0xff,0xff,0xff,0xd8,0x9f,0xfe,0xfe,0xff,
+  0xdf,0xa6,0xf5,0xdf,0xae,0xd9,0xff,0xdf,0xf7,0xf6,0x89,0x73,0x7f,0xbf,0xff,0xfb,
+  0xfe,0x9f,0x75,0xfb,0xa2,0x3e,0xdf,0xac,0xdf,0xff,0xff,0xff,0xff,0x22,0xdf,0xdd,
+  0xff,0x53,0xd6,0xf5,0xbd,0xf5,0xf9,0xdf,0xff,0xff,0xfd,0xe9,0x78,0x7f,0xf7,0xff,
+  0xff,0x77,0xd3,0xde,0x1b,0xd6,0x77,0x9d,0xf7,0xbf,0xff,0xff,0xff,0xff,0x6c,0x7f,
+  0xfb,0xff,0xff,0xff,0xff,0xfa,0xfe,0xbe,0xef,0xff,0xff,0xe7,0xff,0xaf,0xef,0xd6,
+  0xf7,0xff,0xfb,0xfa,0xff,0xff,0xff,0xeb,0xca,0xfe,0xbf,0xff,0xff,0xff,0xff,0xf9,
+  0x4f,0xff,0x7f,0xdf,0xf7,0xff,0xff,0x4f,0xd7,0xf6,0xff,0xdf,0xf7,0xff,0xf5,0x7d,
+  0xff,0xdf,0xff,0xff,0x7f,0x4f,0xdb,0xff,0xfd,0x31,0x4f,0xdf,0xff,0xff,0xff,0xff,
+  0xff,0xb3,0xff,0xff,0xff,0xe7,0xfb,0x7e,0xfd,0xb7,0xcd,0xd9,0xf5,0xfd,0x7f,0xed,
+  0xf3,0x77,0xff,0xcd,0xfb,0xff,0xfd,0xff,0x5f,0xff,0xf6,0xfd,0xb7,0xdf,0xff,0xff,
+  0xff,0xff,0xf3,0x7f,0xff,0xff,0xff,0xff,0xbf,0xeb,0xbf,0xf6,0x7b,0xfe,0x7f,0x9f,
+  0xff,0xfe,0xbe,0x6f,0xf2,0xff,0xaf,0xef,0xfb,0xf6,0x7f,0xbf,0xfb,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x67,0xff,0xed,0xfb,0xf6,0xf9,0xbb,0x67,0xfb,0xfe,0x7f,0x9f,
+  0xe7,0xfb,0xd6,0xfb,0x8e,0xfb,0xe6,0xed,0xbe,0x67,0x18,0xf6,0xed,0x9f,0xe6,0xfb,
+  0xfe,0xff,0xbf,0xef,0xfe,0x91,0xbf,0xff,0xfb,0xfc,0xfd,0xbf,0xcf,0xfb,0xef,0xff,
+  0xfe,0xff,0xbf,0xff,0xff,0xfe,0xff,0xe6,0xfd,0xff,0x7f,0xff,0xe6,0xff,0x3f,0xef,
+  0xfb,0xef,0xff,0xff,0xff,0xff,0xdc,0xbf,0xff,0xfd,0xff,0xbf,0xdf,0xfb,0xfb,0xff,
+  0xff,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xa7,0xff,0xff,0xed,0xff,0x7f,0xff,0xd1,
+  0xf7,0xfd,0x1f,0xee,0xf9,0xfe,0xff,0x3f,0xcf,0xe7,0xff,0x7f,0x7f,0xd3,0xb4,0xff,
+  0xff,0xc7,0xf1,0xb7,0xff,0xff,0xff,0xff,0xff,0xae,0xff,0xff,0xff,0xdf,0xf7,0xdd,
+  0xf2,0xff,0xab,0xaf,0xfe,0xff,0xbf,0xff,0xeb,0xfa,0xfe,0xe9,0xf7,0xfd,0xfa,0xfc,
+  0x8f,0xf7,0xfb,0xfe,0xfe,0xef,0xff,0xff,0xff,0xff,0xfc,0x9f,0xff,0xff,0xff,0xef,
+  0xff,0xff,0x5f,0xd7,0xf5,0xff,0xf7,0xff,0xf7,0xf5,0xff,0x7b,0xbf,0xff,0xff,0xf7,
+  0x5f,0xf7,0xef,0xff,0x3f,0xcf,0xd7,0xff,0xff,0xff,0xff,0xff,0xd1,0xff,0xff,0xe7,
+  0xf9,0xfe,0x7f,0x89,0xe6,0xf8,0x9e,0x7f,0x9d,0xe6,0xf8,0xbe,0x6f,0x9f,0xf9,0xfe,
+  0x7f,0x8b,0xe2,0xf9,0xfe,0x6f,0x9b,0xe3,0xf9,0xfe,0x7f,0x9f,0xe7,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xd7,0xfe,0x7f,0x9f,0xff,0xf7,0xfd,0xff,0xff,
+  0xfb,0xf7,0xfd,0x7f,0x5f,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xcf,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xaf,0xff,0xfa,0xff,0xff,0xff,0xff,0xfe,0xfb,0xbf,
+  0xef,0xff,0x7f,0xbf,0xaf,0xeb,0xfe,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xcd,0xff,0x7f,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,0xff,0xff,0xff,0x7f,0xdf,
+  0xd7,0xfb,0xff,0xff,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xfd,0xff,0x7f,0xff,0xff,0xff,
+  0xff,0xfe,0x3f,0xfd,0xff,0xff,0xff,0xff,0xfe,0xbf,0xed,0xeb,0xff,0xdf,0xf7,0xef,
+  0xeb,0x3a,0xdf,0xfd,0xfd,0xff,0xfe,0xbf,0xad,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,
+  0xff,0xff,0xff,0x77,0xff,0xeb,0xb6,0xff,0xfb,0x77,0xff,0xff,0xff,0xdf,0xff,0xff,
+  0xf2,0xff,0x3f,0x67,0xf2,0xbf,0xff,0x2f,0xcb,0xf6,0xfc,0xbf,0x2f,0xfb,0xfa,0xff,
+  0xff,0xfe,0xff,0xff,0xfe,0xbf,0xff,0xaf,0x69,0xfa,0x3e,0xb7,0xa7,0xe1,0xfa,0xfe,
+  0x3f,0xa4,0xe9,0xfa,0xee,0x3d,0xea,0xfa,0xee,0xbd,0xab,0xeb,0x72,0xae,0xb7,0xa5,
+  0xeb,0xfa,0xfe,0xbf,0xaf,0xf7,0xdf,0xff,0xff,0x9f,0xff,0xfe,0xff,0xdf,0xbc,0xfd,
+  0xff,0x3f,0xff,0xfb,0x7f,0xdd,0x7f,0xed,0xff,0xef,0x3f,0xfb,0xce,0xfb,0xfb,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xd1,0x7d,0xdf,0xff,0xfd,0xff,0xff,0xbf,0xdf,
+  0xfd,0xf3,0xdf,0xff,0xfb,0xfd,0xff,0xff,0xdf,0x7f,0xf5,0xaf,0xbf,0x7f,0xfb,0xdb,
+  0xfa,0xbf,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0x5f,0xff,0xff,0xf7,0xff,0xff,0xee,
+  0xff,0xfe,0xef,0xfb,0xdf,0xff,0xff,0xfe,0xed,0xe9,0xfb,0xbf,0xef,0xfb,0xde,0xff,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,0xcf,0xff,0xff,0xeb,0xf9,0xfe,
+  0xbf,0x8d,0xfd,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0xef,0xba,0xfe,0x3f,0x9f,
+  0xff,0xe8,0xff,0xbf,0xbf,0xe3,0xdf,0xff,0xff,0xff,0xff,0xdd,0xff,0xff,0xf5,0x7f,
+  0xfd,0xfb,0xfb,0xfb,0xf5,0x7f,0xfe,0xdf,0xff,0xfd,0xff,0xff,0xff,0x99,0x6f,0x6e,
+  0xff,0xdf,0xff,0xff,0xdf,0xfe,0xf6,0xff,0xff,0xff,0xff,0xff,0xf8,0xbf,0xff,0xfd,
+  0xfe,0xdb,0xfb,0x5f,0xfb,0xcf,0xfb,0xbf,0xed,0xfb,0xff,0xff,0xbc,0xee,0xce,0xf3,
+  0xbf,0xff,0x2f,0xc3,0xeb,0xbf,0xe3,0x3b,0xce,0xff,0xff,0xef,0xff,0xff,0xd7,0xff,
+  0xfe,0xfe,0xfd,0xef,0x57,0xdf,0xf5,0xbd,0xfb,0xfb,0xff,0xff,0xfd,0xb7,0x5f,0xd6,
+  0x7d,0xbf,0xfb,0xbe,0xf5,0xfc,0xef,0xef,0xdf,0xb5,0xff,0xff,0xff,0xff,0xff,0xe0,
+  0xff,0xff,0xff,0xff,0xe7,0xbf,0xde,0xff,0xf9,0xe3,0xff,0x7f,0xd7,0xfd,0xef,0xff,
+  0xdb,0xbf,0xe9,0x3e,0xdf,0xff,0xfd,0xed,0xff,0xfb,0xdf,0xef,0xff,0xff,0xff,0xff,
+  0xff,0x1f,0xef,0xff,0xbf,0x03,0x7c,0xff,0xff,0xcf,0x73,0xbc,0x7f,0xfd,0xfc,0xff,
+  0xcc,0xef,0x4e,0xff,0xfc,0xdf,0xf1,0xcf,0xf3,0xec,0x77,0xf7,0xcf,0x7f,0xff,0xff,
+  0xff,0xff,0xeb,0xfe,0xbf,0xff,0xbf,0x7f,0xdf,0xff,0xf9,0xff,0x6f,0xf7,0xff,0xff,
+  0xdf,0xf7,0xdf,0xed,0xff,0xef,0xae,0xff,0x7d,0xfb,0x7f,0xf7,0xdf,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0x7f,0xff,0xfe,0x5f,0xeb,0xf9,0xfd,0x7f,0x5f,0xa7,0xff,0xd7,
+  0xf7,0xfd,0xff,0xf9,0xfa,0x15,0xb7,0xfd,0xf7,0xfb,0x9f,0xeb,0xef,0xef,0xff,0x8f,
+  0xff,0xff,0xdf,0xff,0xee,0x27,0xff,0xff,0xfb,0xfe,0xde,0x37,0xed,0xff,0x7c,0xff,
+  0xdf,0xff,0xff,0xfe,0xff,0x8e,0xe9,0xa8,0xdf,0xbf,0xef,0xfa,0x5e,0xdf,0xf7,0xff,
+  0xd7,0xdf,0xff,0xff,0xff,0xbd,0xa1,0xff,0xff,0xfe,0xff,0xdf,0xff,0xfd,0xff,0xff,
+  0xdd,0xff,0xff,0xff,0xff,0xdf,0xcd,0xff,0xff,0xff,0xd7,0xfb,0xfc,0xff,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x8f,0xff,0xff,0xff,0xff,0xff,0xfe,0xf9,
+  0xb1,0xff,0xff,0xfe,0xff,0xff,0xff,0xd7,0xdf,0xbd,0x5c,0xcf,0x3e,0xcf,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x36,0xbf,0xff,0xf7,0xff,0xff,0x3f,
+  0xcf,0x93,0xfc,0xff,0xff,0xdf,0xff,0xff,0x69,0xbf,0xf3,0xcd,0xea,0xfb,0xcb,0xff,
+  0xff,0xff,0xfb,0xcf,0xff,0xff,0xff,0xff,0xff,0xfd,0x7c,0xf7,0xff,0xff,0xf9,0xaf,
+  0xfb,0xca,0xde,0xaf,0xef,0xff,0xfb,0xf4,0xbc,0xff,0xfb,0x56,0xb9,0xfa,0x7e,0xd2,
+  0xf3,0xf7,0xef,0xff,0xd2,0xf5,0xbf,0xff,0xff,0xff,0xff,0xbc,0x9b,0xff,0xfe,0x7f,
+  0x95,0xfd,0xf3,0x5f,0xcf,0xf7,0xff,0xff,0x7e,0xd7,0x9f,0xff,0xf9,0xd7,0xff,0xcf,
+  0xf9,0x5e,0x7f,0xb7,0xff,0xf9,0x5e,0xdf,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,
+  0xff,0xf4,0xff,0xac,0xc9,0xd2,0x6c,0xbb,0x7f,0xef,0xef,0xff,0xff,0x7d,0x5b,0xdd,
+  0xff,0xff,0xe9,0xff,0xf0,0xb3,0x77,0xe9,0xe2,0xf5,0xff,0xff,0xff,0xff,0xf7,0x6f,
+  0xff,0xff,0xf5,0x9f,0xf7,0xa9,0x3e,0x47,0x9f,0xff,0xfd,0xdf,0xf7,0xfd,0x4d,0x7f,
+  0x5a,0x3d,0x6f,0x79,0x3e,0xf7,0x96,0xaf,0xfd,0x34,0x5d,0xbf,0xff,0xff,0xff,0xf7,
+  0xe7,0xff,0xff,0xff,0xfa,0xfe,0xb7,0xaf,0xa9,0xea,0xdf,0xff,0xbf,0xeb,0xff,0xff,
+  0xff,0xeb,0xff,0xff,0xfe,0xaf,0xbf,0xea,0xff,0xfd,0x2f,0xeb,0xff,0xff,0xff,0xff,
+  0xfe,0xe9,0xbf,0xff,0xff,0xff,0x5f,0xdf,0xf4,0xfd,0x3b,0x7f,0xff,0xf7,0xfd,0x7f,
+  0xff,0xf5,0xfd,0x7f,0xff,0xdf,0xf4,0xfd,0xff,0x5f,0xfb,0xa4,0xfd,0x7f,0xff,0xff,
+  0xff,0xff,0xf9,0x2e,0xff,0xff,0xff,0xff,0x7f,0xc7,0xdf,0xf7,0xbf,0x7f,0xff,0xfb,
+  0x7f,0xff,0xbf,0x5f,0xfc,0xff,0x9f,0xef,0xdb,0x7e,0xdf,0x7f,0x6f,0xdb,0x7d,0xff,
+  0xff,0xff,0xff,0xdf,0x17,0xfe,0xff,0xff,0xef,0xdb,0xfe,0xff,0xff,0xef,0xdb,0xff,
+  0xff,0xff,0xff,0xfe,0xe7,0xff,0x2b,0xff,0xff,0xbf,0xff,0xff,0xff,0xee,0xbf,0xbf,
+  0x6f,0xff,0xff,0xff,0xff,0xe6,0x7f,0xee,0xfd,0xbc,0x6e,0xdb,0xb6,0x7f,0xb3,0x6f,
+  0xbb,0xfe,0xdf,0xb7,0xed,0xf9,0xd7,0xbb,0xef,0xdb,0xd6,0x7f,0xbf,0x6f,0xf9,0xbe,
+  0x6f,0xbe,0xef,0xfb,0xfe,0xfd,0xfa,0x9b,0xff,0xff,0x7f,0xef,0x9b,0xe6,0xff,0xff,
+  0xdf,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0xfc,0xef,0xf7,0xfe,0xff,0xff,0x6f,0xbb,
+  0xfe,0xff,0xbe,0xff,0xff,0xff,0xfd,0xbd,0x9b,0xff,0xff,0xff,0xfb,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xf7,0xef,0xff,0xff,0xbf,0xff,0xf7,
+  0xfe,0xfe,0xff,0xdf,0xff,0xff,0xff,0xff,0xef,0xfa,0x5f,0xff,0xfb,0x7f,0xdf,0xff,
+  0xfd,0x3f,0xff,0xdf,0xff,0xfd,0x7f,0xff,0xd7,0xb4,0x6f,0xdf,0xf7,0xfd,0xfd,0x3f,
+  0xdf,0xff,0xf4,0x7d,0x3b,0xff,0xff,0xff,0xff,0xfa,0xff,0x6f,0xff,0xff,0xdd,0xfe,
+  0xae,0xef,0xaf,0x7f,0xde,0xaf,0xff,0xa7,0xff,0xfa,0x7e,0x8f,0xfc,0xb3,0x7f,0xdf,
+  0xaf,0xfd,0xfe,0xb6,0xbf,0xaf,0xfe,0xbf,0xff,0xff,0xff,0xff,0xd1,0xff,0xff,0xff,
+  0xff,0xfd,0xd7,0xf5,0xfb,0xff,0x5e,0xff,0xff,0xff,0xfe,0x5e,0xb7,0xfb,0xff,0xde,
+  0xff,0xf5,0xdb,0xfb,0x5d,0xd3,0xf5,0xef,0x7f,0xff,0xff,0xff,0xff,0xf7,0x3f,0xff,
+  0xfe,0x7f,0x9f,0xe2,0xf8,0xbe,0x7f,0x9b,0xe7,0xf9,0xfc,0x7f,0x8b,0xe6,0x79,0xff,
+  0x8b,0xe7,0xf8,0xbe,0x7f,0x8b,0xe2,0xf8,0xbe,0x6f,0x9f,0xe7,0xf9,0xfe,0x7f,0xb7,
+  0xff,0xff,0xfe,0xfd,0x7f,0xff,0xf7,0xfe,0x7f,0xff,0xef,0xd7,0xef,0xfd,0x3f,0x4f,
+  0xff,0xff,0x7f,0xef,0xd7,0xfe,0xff,0xff,0x47,0xd7,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xea,0xff,0xff,0xff,0xff,0xef,0xef,0xfa,0xff,0xff,0xff,0xfd,0xfa,0xff,0xff,0xa7,
+  0xeb,0xff,0xff,0xbf,0xfd,0xfa,0xff,0xdf,0xef,0xeb,0xfa,0xfe,0xff,0xff,0xff,0xff,
+  0xff,0xf6,0xdf,0xfe,0xff,0xfb,0xfd,0xff,0xff,0xdf,0xdf,0xfd,0xff,0xff,0xfe,0xff,
+  0xfd,0xff,0x3f,0xbf,0xfd,0xff,0xff,0xdf,0xff,0xff,0xff,0x7f,0xdf,0xf7,0xff,0xff,
+  0xff,0xff,0xff,0x9b,0xff,0xff,0xff,0x7f,0xb7,0xbd,0xeb,0xfb,0x7f,0xb7,0xf7,0xff,
+  0xdf,0xff,0x9f,0xed,0xff,0xde,0xff,0xf7,0xeb,0xff,0x7f,0xb7,0xa7,0xef,0xfa,0xdf,
+  0xff,0xff,0xff,0xff,0xfb,0x2f,0xff,0xff,0xaf,0xfb,0xff,0xfc,0xbf,0x7f,0xd9,0xff,
+  0x7d,0x1f,0xff,0xdf,0xfc,0xff,0x2f,0xd3,0xf6,0xbc,0xbf,0x6f,0xff,0xff,0xfc,0x9d,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xef,0xfb,0xfa,0xfe,0xbf,0xaf,0xeb,0xba,0xb6,0xbf,
+  0xaf,0xeb,0xda,0xfe,0xad,0x8b,0xe3,0x4e,0xb7,0xad,0xeb,0x58,0xd6,0xbf,0xab,0xeb,
+  0xba,0xfe,0xbf,0xaf,0xeb,0xfa,0xff,0xc9,0xff,0xff,0xff,0x3f,0x7f,0xff,0xef,0xfb,
+  0x3e,0x37,0xbf,0xff,0xff,0xf7,0xf7,0xf3,0xbf,0xf7,0xbf,0xcf,0xff,0xfd,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xf9,0x1f,0xff,0xfd,0xbf,0x7f,0xff,0x7f,
+  0xff,0xaf,0xff,0x7f,0xff,0xff,0xff,0xfe,0x7a,0xfb,0xfe,0xbf,0xb7,0xaf,0xfe,0xff,
+  0x7f,0xff,0xff,0xff,0x7f,0xff,0xff,0xfd,0xff,0xde,0x85,0xfb,0xff,0xfd,0xff,0xff,
+  0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xdd,0xef,0xbf,0x3f,0xff,0xf3,0xff,
+  0xff,0x2f,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xbf,0xec,0x7f,0xff,0xff,0xbf,
+  0xaf,0xeb,0xfe,0xfe,0x79,0xef,0xff,0xff,0xff,0xff,0xbf,0x7f,0xfe,0x3d,0xaf,0x68,
+  0xcb,0x3a,0x5f,0xee,0xab,0xfb,0xfa,0x7f,0xff,0xff,0xff,0xff,0xf8,0x9f,0xff,0xff,
+  0x5f,0xf5,0xdf,0x77,0xbf,0xff,0xfb,0xff,0xf7,0xff,0xff,0xfd,0xff,0xdf,0x1f,0xdd,
+  0xdf,0x76,0xed,0xff,0xef,0xfd,0x7e,0xdd,0xfe,0xff,0xff,0xff,0xff,0xff,0x91,0xff,
+  0xff,0xbf,0xff,0xdf,0xbf,0xf3,0xfe,0xef,0xbb,0xfb,0xff,0xff,0x7f,0xbf,0xcd,0xee,
+  0xfe,0x3f,0x8f,0xfb,0xfe,0xee,0xbb,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xe3,
+  0x7f,0xff,0xff,0xff,0xff,0xb6,0xfd,0xbf,0x3f,0xcf,0xff,0xff,0xff,0xff,0xdb,0xf7,
+  0xfd,0x7d,0xff,0xf5,0xfc,0xff,0x17,0xce,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x6f,0xbf,0xff,0xff,0xbf,0xff,0xbd,0xef,0xfb,0xf6,0xff,0xf3,0xff,0xff,0x5e,
+  0x6f,0xad,0xb9,0xbf,0xff,0xff,0xef,0xff,0xbb,0xfd,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xd5,0xf7,0xff,0xfc,0xbf,0xff,0xdf,0xff,0xf8,0xfb,0xff,0xff,0xfe,0x5f,
+  0xff,0xfb,0xfb,0xf7,0xce,0x1f,0xfb,0xe2,0xdf,0xef,0xb9,0xfe,0xfe,0x7f,0xf7,0xff,
+  0xff,0xff,0xff,0xfd,0xbe,0xff,0xff,0xdf,0xff,0xfb,0xf9,0xff,0x9f,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xff,0xfa,0xff,0xfb,0xff,0xe7,0xdf,0x7f,0x77,0xff,0xfb,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x83,0xbf,0xff,0xfb,0xff,0xf7,0xfd,0x33,0xff,0xfd,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0x7f,0xdb,0xc7,0x5d,0x7f,0x1b,0xf7,0xf3,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xbf,0xff,0xdf,0xff,0xff,0xfe,0xfa,0xff,0xf9,
+  0xeb,0xff,0xff,0xdf,0xf7,0xff,0xfb,0xff,0xf7,0xcd,0x79,0xee,0xf6,0x3f,0xf7,0xff,
+  0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x5f,0xef,0xff,0xff,0xff,0x7f,0xd7,0x7f,
+  0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xfd,0xfd,0xfc,0xdf,0xdd,0xfd,0xf7,
+  0xff,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xd8,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x3f,0xff,0xff,0xdf,0xf3,0xfd,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x3f,0xff,0xbf,0x3f,0xfb,0xff,0xff,0xff,0xff,0xff,0xc9,0x6b,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0x9f,0xbf,0xff,0xfe,0xff,0xff,
+  0xff,0xef,0xdf,0xf3,0xfc,0xff,0x7f,0xff,0xff,0xff,0xff,0xd7,0x6f,0x7f,0xff,0xff,
+  0xff,0xff,0xfc,0xb7,0xff,0xff,0xf4,0xbf,0xff,0xff,0xff,0xff,0xef,0xff,0x9f,0xe7,
+  0xff,0xff,0x5b,0xff,0xfe,0xbd,0x27,0xef,0xff,0xff,0xff,0xff,0xfb,0xd1,0xbf,0xff,
+  0xff,0xff,0xff,0xff,0x36,0xff,0xff,0xfe,0xd7,0xff,0xff,0xff,0xfc,0xff,0xff,0xff,
+  0xfc,0xff,0xff,0xef,0xff,0x7e,0xd7,0xb6,0xfd,0xff,0xff,0xff,0xff,0xff,0xd9,0xb7,
+  0xff,0xff,0xff,0xff,0xfa,0xfe,0xb7,0xaf,0xeb,0xef,0xff,0xff,0xff,0xeb,0xff,0x7f,
+  0xaf,0xfb,0xff,0xf5,0xfe,0x7f,0xeb,0x42,0x79,0xbb,0x3f,0xff,0xff,0xff,0xff,0xff,
+  0x46,0xff,0xff,0xff,0xff,0xff,0x57,0xd6,0xf5,0x7d,0x5f,0xf7,0xff,0xff,0xfd,0x5f,
+  0x7e,0xb5,0x7f,0xde,0xf7,0xfd,0x8f,0x69,0x6e,0x4d,0x1f,0xf7,0x7f,0xff,0xff,0xff,
+  0xff,0x7a,0xdf,0xff,0xff,0xff,0xff,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xff,0xf5,0xff,
+  0xaf,0xff,0xde,0xbf,0xff,0xbf,0xff,0xff,0xf7,0xad,0xab,0xfa,0xfe,0xff,0xff,0xff,
+  0xff,0xff,0xfa,0x1f,0xff,0xff,0xff,0xff,0xfd,0x7f,0x5f,0xd7,0xf5,0xe9,0x7f,0xff,
+  0xff,0xf5,0xff,0xf1,0xd7,0xff,0xfd,0xff,0x7f,0xff,0xa5,0xfd,0x3f,0x7f,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xf3,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0xdf,0xe7,0xff,0xff,0xff,0xbf,0xef,0xf7,0xf7,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0x7f,0xbf,0xff,0xfa,0xff,0xbf,0xbf,0xff,
+  0xdf,0xff,0xff,0xff,0xff,0xff,0xfe,0x87,0xff,0xef,0xfb,0xfe,0xff,0xbf,0x6f,0xfb,
+  0x7e,0xff,0xb7,0xef,0xfb,0xfe,0xff,0xbc,0x7b,0xf6,0xef,0xbf,0xee,0xdb,0xf6,0xf9,
+  0x9f,0xef,0xfb,0x7e,0xff,0xbf,0xef,0xff,0x89,0xbf,0xff,0xff,0xff,0xff,0xff,0xcf,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfc,0xff,0xbf,0xef,0xf3,0xfc,
+  0xf9,0xff,0xef,0xbf,0xff,0xff,0xff,0xff,0xff,0xda,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xbf,0xdf,0xf7,0xfe,
+  0xff,0xbf,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x25,0xff,0xff,0xbf,0xff,
+  0xff,0xfe,0xff,0xff,0xef,0x7f,0xff,0xff,0xff,0xff,0xfe,0xcf,0xef,0xff,0xfb,0xde,
+  0xb7,0xff,0xff,0xff,0x4f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbe,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdb,0xbf,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xfb,0xf7,0xdf,0xf7,
+  0xfd,0xdf,0x7d,0xdf,0xbb,0xeb,0xdf,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,
+  0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,
+  0xaf,0xff,0xfe,0xff,0xff,0xbf,0xfd,0x7b,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xa3,
+  0xff,0xff,0xe7,0xf9,0xfe,0x7f,0x8f,0xe7,0xf9,0xbe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,
+  0x9e,0xf9,0xfe,0x7f,0x9f,0xe7,0xf8,0xfe,0x2f,0x1b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,
+  0xf5,0x7f,0xff,0xff,0xef,0xff,0xfe,0xfd,0x7f,0xef,0xf3,0xff,0xff,0xff,0xff,0xfb,
+  0xfc,0x7f,0xff,0xfb,0xfe,0x7f,0xbf,0xe7,0xd7,0xfd,0xeb,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0xde,0x6f,0xff,0xff,0xfd,0xff,0xff,0xdf,0xaf,0xfd,0xfe,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xbf,0xff,0xff,0x7f,0xff,0xf7,0xef,0xfa,0xfe,0xff,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xcd,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcf,0xff,0xff,
+  0xff,0xff,0xef,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xf7,0xff,0xff,0x7e,0xf7,0xf7,0xf9,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xed,0xff,0x7f,0xdf,0xf7,0xef,0x7b,0xf6,0xb7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0xff,0xfd,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x6f,0xff,0xfd,0xaf,0x7f,0xdf,0xf6,0x7c,0xbf,0x73,
+  0xdb,0xf4,0xff,0xff,0xff,0xff,0xff,0xec,0xfd,0xff,0xab,0xeb,0xfa,0xbe,0xbf,0xaf,
+  0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xad,0xeb,0x7a,0xde,0xbd,0xae,0xcb,0x32,
+  0xf4,0xb7,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xf5,0x1b,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfd,0xff,0x3f,0xff,0xff,0xfc,0x78,0xdf,0xff,0xf3,0xfe,0xff,0xff,0x9d,
+  0xff,0xff,0xff,0x3f,0xef,0xff,0xff,0xff,0xff,0xfd,0xc9,0xfd,0xff,0xf7,0xfd,0xff,
+  0xff,0xff,0xf7,0xff,0xaf,0xff,0xff,0xff,0xfe,0xbf,0xf9,0xdf,0x7f,0xff,0xff,0xff,
+  0xff,0xef,0xf9,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe2,0x5f,0xff,0xfd,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xff,0xef,0xff,0xff,0xdc,0xef,0xbf,0xbe,
+  0xbf,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xa7,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xa7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,
+  0xfe,0xaf,0xef,0xa7,0xf8,0xfe,0x3f,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xe1,0xff,
+  0xff,0xf7,0xff,0xff,0xff,0xf5,0xdf,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xfd,0x7b,
+  0xf5,0xbd,0xfb,0x7f,0xbf,0xff,0xbf,0xef,0x7f,0xdf,0xff,0xff,0xff,0xff,0xfb,0xfe,
+  0x1f,0xdf,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,
+  0xfa,0xff,0xff,0xfa,0xfe,0xbf,0xef,0x7a,0xff,0xbe,0xef,0xfb,0xff,0xff,0xef,0xff,
+  0xff,0x96,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xfb,
+  0xff,0xfb,0xdf,0x77,0xff,0x6f,0x9e,0xf3,0xfc,0xef,0x5f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf4,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xab,0xf7,0xff,0xed,0xfb,0x6f,0xbf,0xeb,0xff,0xff,0xdf,0xff,0xff,
+  0xff,0xff,0xf3,0xfd,0x5f,0x7f,0xff,0xff,0xff,0xef,0xff,0x3f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xbf,0x8f,0x7f,0xbf,0xff,0xff,0xfd,0x4f,0xf3,0xfc,0xfd,0x3f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xbb,0xef,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xff,0xef,0xbf,0xff,0xfb,0xff,0xfd,0xff,0x7d,0xdd,0xf7,
+  0xff,0xff,0xff,0xff,0x7f,0xff,0xf0,0x7f,0xff,0xff,0xff,0xff,0xff,0xee,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5d,0xff,0xaf,0xe3,0xff,0x1f,0xc7,0xf9,
+  0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0x07,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xca,0xbf,0xfb,0xbf,0xef,0xfb,0xfe,
+  0xff,0x3b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb1,0xfb,0xff,0xff,0xff,0xff,0xfd,
+  0xbf,0xff,0xdf,0xff,0xff,0xff,0xff,0xfe,0xf7,0xff,0xff,0xf7,0xff,0xef,0xfb,0xfe,
+  0xdf,0xd7,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0x0b,0xff,0xff,0xbf,0xff,
+  0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,
+  0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xd4,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xe6,0xd7,0xff,
+  0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,
+  0xff,0xff,0x9f,0xff,0xbc,0xaf,0x4b,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xbe,0xcb,
+  0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,
+  0xd7,0xff,0xff,0xff,0xfe,0x5f,0xb5,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0x7d,
+  0xd9,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbf,0x4f,0xd2,0xc9,0xbd,0x3d,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xea,0x2d,0xff,0xff,0x77,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xf7,0xff,0xff,0x7b,0xdf,0x5a,0x9f,0xa7,0xbf,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0x4d,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xfe,0xff,0xeb,0xfa,0xde,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x80,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xfd,0x7f,0x5f,0xd7,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfc,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0x3f,0xc7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x07,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x7f,0xff,0xfb,0xde,
+  0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0x7f,0xfe,0xff,0xbf,0xef,0xfb,0xfe,
+  0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,0xbf,0xef,0x5b,0xf6,0xfd,0xbf,
+  0x6f,0xdb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xfb,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,
+  0xfe,0xdf,0x9b,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd3,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,
+  0xff,0xff,0xff,0x7f,0xdf,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xaf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x9f,0xff,0xff,0xff,0xff,0xff,0xf9,
+  0xff,0xfd,0xdd,0x77,0x6a,0xfb,0xae,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xec,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,
+  0xef,0x7f,0xff,0xff,0xff,0xfd,0xf3,0xfd,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf3,0x3f,0xff,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe2,0xe9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xef,0x9f,0xe6,0xe9,0xbe,0x6f,0x1f,0xe2,0xe9,0xfe,0x7f,0x9f,0xe7,0xf9,
+  0xfe,0x7f,0x67,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xf7,0xf9,0x7f,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xe8,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xef,0xfe,0xfd,0xbf,0xef,0xef,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xf7,0xff,0xff,0xfd,0xff,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x3b,0xfe,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xfe,0xfd,0xff,0xd6,0xf7,0xbd,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0x3f,0xff,0xff,0x4f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0xff,0xf2,0xfd,0xff,0xff,0xff,
+  0xf2,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0x8f,0xff,0xfa,0xfe,0xbf,0xab,0xeb,
+  0xfa,0xbe,0xbf,0xab,0xcb,0xfa,0xbe,0xbf,0xaf,0xeb,0xde,0xaf,0xaf,0xeb,0xda,0xde,
+  0xaf,0xae,0xea,0xfa,0xde,0xbf,0xaf,0xeb,0xfa,0xff,0xc5,0xff,0xff,0xfa,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xef,0xef,
+  0xff,0xdd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xf8,0x9f,0xff,0xff,0xff,
+  0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7e,0x65,0xff,0xff,
+  0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xdf,0xff,
+  0xff,0xfd,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xf2,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,0xfe,0xfd,0xff,0x7f,
+  0xdf,0xf7,0xe3,0xfe,0x7f,0x9f,0xae,0xed,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x9f,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0x7d,0xdf,0xdd,0xff,0xbf,0x7f,0xea,0xff,0xbf,0xff,0xff,0xff,0xbf,0xff,0xff,
+  0xff,0xe1,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe7,0xef,0xff,0xff,0xff,0xff,0xfb,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xff,0xff,0xf1,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xff,0xd7,0xfb,0x7d,0xff,0xfd,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,
+  0xff,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfb,0x9f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xd5,0xff,0xbf,0xbf,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0xff,0xff,0xc7,0xdf,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xef,0xfd,0xbf,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xfe,0xf7,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xbf,0xf7,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xeb,0xff,0xff,0xff,0xfd,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xef,0xf7,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfb,0xff,0xff,0xf7,0xfa,0xdf,0xef,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xdf,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xb0,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,0xf9,0xff,0xff,0xf5,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xc6,0x6b,0xfc,
+  0xff,0x3b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,0xaf,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xd7,0xcf,
+  0x7f,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xfb,
+  0xfd,0xbf,0xf7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,
+  0xff,0xdb,0x37,0xff,0xbd,0x6f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xeb,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xef,0xff,
+  0xff,0xff,0xbf,0xa6,0xff,0xdd,0xa7,0x77,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0x5f,0x57,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0x7d,
+  0xdf,0xff,0xff,0xff,0x7a,0xdf,0xfe,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xaf,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xbf,0xbf,0xff,0xff,0xff,0xf8,0xdf,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xf5,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xd7,0xf7,0xff,0xff,0xff,0xff,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x7e,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xf5,0x7f,0xef,0xf9,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xeb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbe,0x07,0xfe,0xed,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xb7,0xfb,0xfe,0xff,0xbe,0xef,
+  0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xb1,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xde,0xbf,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd5,0xff,
+  0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xed,0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xff,0xf4,
+  0xff,0xfa,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xa7,0xe9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,0xff,0xff,
+  0xff,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,
+  0xff,0xff,0xeb,0xff,0xff,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,
+  0xf9,0xfe,0x7f,0x9f,0xf9,0xfe,0x7f,0x1f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xe9,0xfe,
+  0x2f,0x9f,0xe7,0xe3,0x7f,0xfd,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xef,0xd7,0xf4,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xff,0xfe,0x4f,0xff,0xaf,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xfa,0xfe,0x9d,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xff,0xff,0xff,0xed,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x3f,0xfd,0xff,0xff,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xf7,0xfd,0xff,0x77,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x83,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xef,0xfb,0xf7,0xff,0xff,0xf9,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xc0,0xdd,0xff,0xad,0xeb,0x7a,
+  0xfe,0xbf,0xad,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0x8f,0xe9,0x7a,0xbe,0xaf,
+  0xaf,0xea,0xfa,0xfe,0xbf,0x2b,0xeb,0xda,0xfe,0xbf,0xaf,0xfd,0x5f,0xfd,0xff,0xff,
+  0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xa9,0x5f,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x7f,0xf7,0xff,0xff,0xff,0xff,0xfd,
+  0xfb,0xff,0xff,0xdf,0xff,0xf7,0xbf,0xef,0xf3,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,
+  0x47,0xfd,0xf7,0xfd,0xff,0xff,0xf7,0xfe,0xff,0xff,0xff,0xdf,0xff,0xdf,0xff,0xff,
+  0xff,0xbf,0xaf,0xbf,0xff,0xfd,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xfe,0xbf,0xff,
+  0xff,0xc1,0xff,0xff,0xe7,0xf5,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf3,0xff,0xff,0xff,0xff,0xbf,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,
+  0xff,0xfb,0xdf,0x1f,0xfd,0xdf,0xff,0xf3,0xff,0xff,0xff,0xef,0xf3,0xfc,0xff,0xfb,
+  0xff,0xfb,0xf6,0xfe,0xef,0xff,0xff,0xff,0xfd,0x7f,0x5b,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x7f,0xff,0xff,0x97,0xff,0xd7,0x75,0x7d,0xbf,0x7f,0xfb,0xfb,0xfd,0xff,0xff,
+  0xd3,0xff,0xfd,0xbf,0x2f,0xc4,0xff,0xbf,0xff,0xfb,0x7f,0xbc,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xbe,0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xff,0xff,0xe7,0x6f,0xf9,0xdf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x5f,0xf7,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0x7f,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xdf,0xfb,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xef,0xff,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0x7d,0xff,0x5f,0x5f,0xd7,0xff,
+  0xff,0xff,0xff,0xd6,0x75,0x5f,0xf7,0xde,0xff,0xff,0xff,0xdf,0xfd,0x3f,0xdf,0xf7,
+  0x5d,0xf7,0xdd,0xff,0xff,0x5f,0xff,0xff,0x7f,0xff,0xde,0xe7,0xdf,0x8f,0xfb,0xff,
+  0x7f,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xeb,0xfe,0xdf,0xbf,0xf7,0xfe,0xff,0xbf,
+  0xff,0xff,0xfc,0xff,0xbf,0xff,0xfb,0xff,0xff,0xbf,0xff,0xff,0x95,0xf7,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xfd,0xfb,0xb3,0xf7,0x6f,0xff,0xbf,
+  0xf7,0xbf,0xff,0xff,0xdf,0xd7,0xff,0xff,0x77,0xff,0xef,0xbf,0xfb,0xfc,0xbb,0xff,
+  0x8f,0xe7,0xf9,0x7e,0x7f,0x9b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0xe7,
+  0xf9,0xf6,0x5f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xfc,0x16,
+  0xff,0xf3,0xfa,0xff,0xb7,0xed,0xfb,0x7e,0xff,0xbf,0xcf,0xfb,0x7a,0xfe,0xbf,0xcf,
+  0xfe,0xfe,0xbd,0xcf,0xfb,0xfe,0xff,0xbf,0xcf,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,
+  0xa4,0xcf,0xfe,0x7f,0x9d,0xe7,0xfb,0xfe,0xff,0xbf,0xe7,0xb9,0xfe,0xff,0xbf,0xe7,
+  0x78,0xfd,0x9f,0x67,0xfb,0xf8,0xf5,0xaf,0x67,0xdb,0xfe,0xff,0xbf,0xef,0xeb,0xac,
+  0xff,0xfe,0x9f,0xff,0xdf,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xff,0xff,0xef,0xff,0xff,0xbf,0xf7,0x7f,0xff,0xff,0xbf,0xbf,0xff,0xff,0xff,0xfd,
+  0xfd,0xff,0xfd,0xc3,0xff,0xfb,0xde,0xf7,0xbf,0xef,0xfb,0xbe,0xff,0xae,0xe7,0xfb,
+  0xfe,0xff,0xbd,0xe7,0xfe,0xbd,0xbf,0xe7,0xfb,0xfe,0xef,0xbd,0xef,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xff,0xfa,0x7f,0xfc,0xff,0x37,0xcf,0xf3,0xfc,0xff,0x3f,0xcf,0xd3,
+  0x7c,0xff,0x3f,0xcf,0xf3,0xff,0x3f,0xcf,0xf3,0xfe,0xef,0x3f,0xcf,0xf3,0xfc,0xff,
+  0x3f,0xcf,0xfb,0xf6,0xef,0xfe,0x0f,0xff,0xb7,0xed,0xfb,0x7e,0xff,0xbf,0x6f,0xfb,
+  0x7e,0xdb,0xbf,0xef,0xfb,0x7a,0xdf,0xed,0xeb,0x7e,0xff,0xbe,0xef,0xdb,0x7e,0xff,
+  0xbf,0xcf,0xfb,0xfe,0xff,0xbf,0xfb,0xe5,0xff,0xfb,0xfe,0xff,0xbf,0xe5,0xf9,0x7e,
+  0x5f,0xbf,0xef,0xf9,0x7e,0x5f,0xbf,0xef,0xfa,0xff,0xbf,0xe5,0xf9,0x7e,0xdf,0xbf,
+  0xe5,0xf9,0x7e,0x5f,0x97,0xed,0xf9,0x7f,0xf9,0xbf,0xff,0x5b,0xd7,0xf5,0xfd,0xff,
+  0x7d,0xdf,0xf5,0xfd,0x7f,0x7f,0xdb,0xf5,0xfd,0x37,0xd7,0xf5,0x7d,0xf7,0x7f,0xd7,
+  0xf5,0xfd,0xef,0x7b,0xdf,0xf7,0xfd,0x7f,0x7f,0xff,0x97,0xff,0xf7,0xfd,0xff,0x7f,
+  0xff,0xff,0xbf,0xff,0x7f,0xdf,0xff,0xff,0xff,0x7f,0xdf,0xbd,0xff,0x7f,0xff,0xff,
+  0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xfb,0xf0,0xff,0xed,0xff,0x6f,
+  0xdb,0xf6,0xfd,0xb7,0xed,0xdf,0xf7,0xfd,0xff,0x7f,0xde,0xf5,0xfb,0x6f,0xdb,0xf7,
+  0xfd,0xbf,0x7d,0xdb,0xf7,0xff,0xff,0x6f,0xfb,0xf7,0xfd,0xff,0x7e,0xdf,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xdf,0xfb,0xff,0xff,0xff,0xff,0x7f,0xff,
+  0xfb,0xff,0xff,0xbf,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0xfd,
+  0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xd7,0xf7,0xfd,0xff,0x7d,0xdf,0xf7,0xff,
+  0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0xf5,
+  0x7b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xfe,0xff,0xff,0xdf,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xfc,0xff,0xff,0xdf,0xff,0xff,0xff,
+  0xff,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xf7,
+  0xfb,0xff,0xb7,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,
+  0xff,0xff,0x7f,0xf4,0xff,0xff,0xef,0xff,0xff,0xfe,0xff,0xef,0xff,0xfe,0xff,0xff,
+  0xcf,0xfb,0xff,0xbe,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x57,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,0xff,0xfd,0xff,
+  0x7f,0xdf,0xf7,0xff,0xff,0xff,0xee,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xfe,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x8b,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0x7f,0xff,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfe,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xcf,0xff,0xcf,0xf3,
+  0xfc,0xff,0xbf,0xef,0xfb,0xfc,0xff,0x3f,0xef,0xf3,0xfc,0xff,0x3f,0xb3,0xfc,0xff,
+  0x3f,0xef,0xf3,0xfc,0xff,0x3f,0xef,0xf3,0xfe,0xff,0x3f,0xef,0xff,0xfd,0xff,0xff,
+  0xbf,0xef,0xff,0xff,0xef,0xff,0xfe,0xff,0xff,0xff,0xfb,0xff,0xfb,0xff,0xf7,0xff,
+  0xfb,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x3f,
+  0xfe,0xfe,0xbb,0xaf,0xeb,0xfa,0xff,0xbf,0xae,0xeb,0xba,0xfe,0xfb,0xee,0xeb,0xfb,
+  0xbb,0xae,0xef,0xbe,0xff,0xbb,0xee,0xef,0xbe,0xff,0xfb,0xef,0xfb,0xbe,0xef,0xff,
+  0x17,0xff,0x75,0xad,0xab,0x4a,0xba,0xef,0xeb,0xaf,0x6a,0xda,0xae,0xb5,0xfb,0x7a,
+  0xd2,0xbd,0xab,0x7a,0x5f,0xaf,0xed,0x7b,0x7a,0x5f,0xaf,0xe5,0xfa,0xfe,0xdb,0xbf,
+  0xe2,0xd4,0xff,0xff,
diff --git a/u-boot/board/esd/dasa_sim/u-boot.lds b/u-boot/board/esd/dasa_sim/u-boot.lds
new file mode 100644
index 0000000..3349fe8
--- /dev/null
+++ b/u-boot/board/esd/dasa_sim/u-boot.lds
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    KEEP(*(.resetvec))
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/esd/dp405/Makefile b/u-boot/board/esd/dp405/Makefile
new file mode 100644
index 0000000..d4012b0
--- /dev/null
+++ b/u-boot/board/esd/dp405/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/dp405/dp405.c b/u-boot/board/esd/dp405/dp405.c
new file mode 100644
index 0000000..5878092
--- /dev/null
+++ b/u-boot/board/esd/dp405/dp405.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO13 (CS4) pin
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+	unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
+				   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+	unsigned char id1, id2, rev;
+
+	puts ("Board: ");
+
+	if (i == -1)
+		puts ("### No HW ID - assuming DP405");
+	else
+		puts(str);
+
+	id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
+	id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
+
+	rev = in_8((void *)0xf0001000);
+	if (rev & 0x10) /* old DP405 compatibility */
+		rev = in_8((void *)0xf0000800);
+
+	switch (rev & 0xc0) {
+	case 0x00:
+		puts(" (HW=DP405");
+		break;
+	case 0x80:
+		puts(" (HW=DP405/CO");
+		break;
+	case 0xc0:
+		puts(" (HW=DN405");
+		break;
+	}
+	printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
+
+	if ((rev & 0xc0) == 0xc0) {
+		printf(", C5V=%s",
+		       in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
+	}
+	puts(")\n");
+
+	return 0;
+}
diff --git a/u-boot/board/esd/dp405/flash.c b/u-boot/board/esd/dp405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/dp405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/du405/Makefile b/u-boot/board/esd/du405/Makefile
new file mode 100644
index 0000000..bd08253
--- /dev/null
+++ b/u-boot/board/esd/du405/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/du405/du405.c b/u-boot/board/esd/du405/du405.c
new file mode 100644
index 0000000..c32d333
--- /dev/null
+++ b/u-boot/board/esd/du405/du405.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "du405.h"
+#include <asm/processor.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
+	 * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
+	 * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFFB1);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 100 us
+	 */
+	mtebc (EBC0_CFG, 0xb8400000);
+
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/*
+	 * Setup UART1 handshaking: use CTS instead of DSR
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming DU405");
+	} else {
+		puts (str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Reset external DUART via FPGA
+	 */
+	out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
+	out_8((void *)FPGA_MODE_REG, 0x00); /* low again */
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_LXT971_NO_SLEEP)
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/u-boot/board/esd/du405/du405.h b/u-boot/board/esd/du405/du405.h
new file mode 100644
index 0000000..768e843
--- /dev/null
+++ b/u-boot/board/esd/du405/du405.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/du405/flash.c b/u-boot/board/esd/du405/flash.c
new file mode 100644
index 0000000..c30886e
--- /dev/null
+++ b/u-boot/board/esd/du405/flash.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*          printf("PB1CR = %x\n", pbcr); */
+	}
+
+	if (size_b0) {
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*            printf("PB0CR = %x\n", pbcr); */
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/u-boot/board/esd/du405/fpgadata.c b/u-boot/board/esd/du405/fpgadata.c
new file mode 100644
index 0000000..fd80d2c
--- /dev/null
+++ b/u-boot/board/esd/du405/fpgadata.c
@@ -0,0 +1,703 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x64,0x75,0x72,0x61,0x67,0x34,0x30,0x35,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x32,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x32,0x2f,0x30,0x32,0x2f,0x32,0x31,0x00,0x64,0x00,0x09,0x31,0x32,0x3a,0x35,
+ 0x31,0x3a,0x30,0x38,0x00,0x65,0xe2,0x01,0x00,0x00,0x2b,0x98,0xff,0x30,0xe6,0xe5,
+ 0xe5,0x02,0x04,0x01,0xe6,0x04,0x01,0x0d,0x04,0x04,0x02,0x01,0x04,0x04,0x03,0x07,
+ 0x01,0x03,0x01,0x04,0x11,0x01,0x06,0x02,0x15,0x09,0x02,0x05,0x07,0x02,0x02,0x01,
+ 0x09,0x03,0x07,0x01,0x03,0x01,0x0b,0x05,0x03,0x01,0x07,0x08,0xe5,0xe5,0x24,0x05,
+ 0x09,0x11,0x01,0x03,0x03,0x05,0x0d,0x09,0x0b,0x09,0x01,0x1d,0x09,0x13,0x03,0x05,
+ 0x12,0xe6,0x11,0x01,0x03,0x02,0x02,0x03,0x03,0x01,0x15,0x01,0x02,0x28,0x01,0x05,
+ 0x02,0xe5,0xe5,0x02,0x02,0x02,0x0d,0x02,0x02,0x03,0x02,0xe5,0xe5,0x14,0x01,0x02,
+ 0xe5,0x12,0x0b,0x03,0x0f,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x06,0x02,0x09,
+ 0x06,0xe7,0x05,0x04,0x06,0x02,0x06,0x02,0x09,0x07,0xe6,0x08,0x09,0x07,0xe6,0x08,
+ 0x09,0x0e,0xe5,0xe6,0x0d,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0x09,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0x03,0x05,0xe8,0x04,0xe6,0x02,0x05,0xe6,0xe5,
+ 0x04,0xe6,0x06,0x03,0x05,0xe5,0xe6,0x04,0xe5,0x07,0x09,0xe5,0xe6,0x04,0x09,0x09,
+ 0x09,0xe8,0x46,0x09,0x14,0xe5,0x06,0x0b,0x09,0x15,0x1d,0x24,0x02,0xe5,0xe5,0x45,
+ 0x08,0x15,0x33,0x1d,0x28,0x70,0xe5,0x09,0x09,0x14,0x42,0x02,0xe5,0x30,0x27,0x01,
+ 0x15,0x1b,0x1d,0x32,0x01,0x01,0x5b,0x0c,0x51,0x24,0x01,0xe5,0xe5,0x28,0xe5,0x1c,
+ 0x25,0x53,0x19,0xe5,0x01,0x2b,0x45,0x6c,0xe5,0xe6,0x35,0x09,0x07,0x01,0x09,0x09,
+ 0x12,0x63,0x09,0x02,0x03,0x0c,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x01,
+ 0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0xe5,0x02,0x0c,
+ 0x09,0x09,0x09,0x06,0x02,0x05,0xe5,0x01,0x07,0x01,0x05,0x03,0x07,0x01,0x09,0x0b,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,0x05,0x07,0xe5,0x05,
+ 0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x03,0x05,0xe5,0x07,0x09,0xe5,0x07,0x09,0xe5,
+ 0x07,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x04,0x02,0xe5,0x12,0x04,0x0b,0x05,0x02,0xe5,0x07,0xe5,0x08,0x09,
+ 0x08,0xe5,0x08,0x09,0x09,0x09,0x06,0x03,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,
+ 0x08,0x09,0x04,0x03,0xe5,0x08,0x09,0x0d,0x01,0xe6,0x05,0x06,0xe5,0x07,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x01,0x03,0xe5,0x14,0x06,0x09,0x13,0xe5,0x09,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0x07,0xe5,0x07,0xe5,0xe5,
+ 0x05,0xe5,0x07,0xe5,0x07,0x02,0x03,0xe8,0x0e,0x01,0x09,0x09,0x07,0x08,0xe5,0x07,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x01,0x0b,0x09,0x07,0x0b,0x09,0x07,0x09,0x13,
+ 0x09,0x0e,0x02,0xe5,0x0c,0x09,0x03,0x05,0x09,0x12,0x09,0xe5,0x08,0x13,0x09,0x01,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x10,0xe8,0x03,0x08,0x02,0x03,
+ 0x02,0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x09,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x06,0x02,0x04,0x01,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0x06,
+ 0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x0d,0x01,0x01,0x03,0xe5,0x09,
+ 0x09,0x09,0xe5,0x0f,0xe5,0x25,0x0b,0x04,0xe5,0x01,0x02,0x06,0x02,0x13,0x09,0x36,
+ 0x0d,0x23,0x35,0x82,0x01,0x03,0x10,0x09,0x02,0x06,0x11,0x09,0x1c,0xe5,0x0a,0x03,
+ 0xe6,0xe5,0x02,0x03,0x05,0x0d,0x05,0x03,0x05,0x17,0x27,0x02,0xe5,0x29,0x50,0x27,
+ 0x11,0x28,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x04,0x04,0xe5,0x07,0xe5,0x07,0x09,
+ 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0xe7,0x0e,0xe5,0x02,
+ 0x02,0x02,0x06,0x02,0x10,0xe5,0xe5,0x38,0x1e,0x06,0x02,0x13,0x01,0xe5,0x2c,0xe6,
+ 0x17,0x09,0x06,0x09,0x01,0x10,0x19,0x24,0x13,0x13,0x02,0x11,0x16,0x05,0x02,0x03,
+ 0x01,0x10,0xe5,0x08,0x70,0x09,0x3f,0x01,0x02,0xe5,0x02,0x26,0x11,0x09,0x28,0x02,
+ 0x6c,0xe5,0xe5,0x13,0xca,0x02,0x0d,0x01,0x07,0x01,0x07,0x1d,0x01,0x04,0x0e,0x07,
+ 0x01,0x13,0x01,0x07,0xe6,0x10,0xe5,0x03,0x46,0x01,0x01,0x0d,0x01,0x07,0x02,0x03,
+ 0x05,0x1d,0x10,0x09,0x02,0x0e,0x02,0xe5,0x01,0x07,0x35,0x29,0xe6,0xe5,0x18,0x12,
+ 0xe5,0x10,0x08,0x1a,0x2c,0x09,0x43,0xe5,0xe6,0x14,0x01,0xe6,0x04,0x04,0x23,0x04,
+ 0x12,0x0b,0x09,0x63,0x03,0x02,0xe5,0x71,0x30,0x3c,0x01,0x17,0xe5,0xe5,0x29,0x35,
+ 0x5e,0x03,0x03,0x09,0x0f,0x0b,0x20,0x27,0x71,0x01,0x0f,0x04,0x03,0x05,0x02,0x01,
+ 0x04,0x09,0x09,0x32,0x02,0x65,0x01,0x03,0x01,0xe6,0x0d,0xe5,0x10,0x01,0x27,0x02,
+ 0x09,0x89,0x0e,0x03,0x33,0x03,0x03,0x29,0x03,0x04,0x2c,0x2f,0xe6,0xe7,0xd9,0xe7,
+ 0xe6,0x01,0x01,0x23,0xe5,0xae,0x01,0x03,0x02,0x04,0xd4,0x08,0x02,0xd8,0x03,0x01,
+ 0xe5,0x16,0x01,0x11,0x01,0xb2,0x01,0x01,0x15,0x01,0x01,0x0f,0x01,0x01,0xab,0x06,
+ 0x17,0x01,0x11,0x01,0xaf,0xe5,0xe5,0xe5,0x16,0x01,0x11,0x01,0xb1,0x02,0x4f,0xe5,
+ 0x86,0x06,0x01,0xe5,0x4f,0xe5,0x8b,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x06,
+ 0x02,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,
+ 0xe6,0x01,0x44,0xe5,0x91,0x03,0x01,0xe5,0x44,0x9a,0x01,0x0f,0x13,0x24,0xe5,0xe5,
+ 0x91,0xe5,0x01,0x0f,0xe5,0x11,0xe5,0x23,0x01,0xe5,0x92,0xe7,0x0d,0x13,0x25,0x01,
+ 0x91,0xe6,0x01,0x09,0x05,0x03,0xe7,0x05,0xe7,0x01,0x04,0xe6,0x05,0xe7,0x07,0xe5,
+ 0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0x01,0xe5,0x0e,0x04,0x05,0x03,0x04,0x04,0x08,0x17,0x01,0x92,0x02,0xe5,0x0e,0x06,
+ 0x03,0x02,0x02,0x02,0x06,0x07,0x01,0x16,0x8b,0x05,0xe5,0x01,0xe6,0x0d,0x03,0x01,
+ 0x09,0x03,0x05,0x09,0x15,0x28,0x64,0x04,0xe7,0x01,0x03,0x0b,0x03,0xe7,0x02,0x02,
+ 0x01,0xe5,0x01,0x03,0xe7,0x02,0x03,0xe6,0x13,0x01,0x90,0x04,0xe5,0xd9,0x03,0xe5,
+ 0xe6,0x10,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x04,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,
+ 0x0b,0xe7,0x4e,0x8e,0xe6,0xe6,0x12,0x3c,0x1e,0x0b,0x13,0x09,0x19,0x16,0x11,0xe9,
+ 0x03,0x19,0x32,0x0a,0x09,0x09,0xe5,0x4f,0x09,0x08,0xe5,0x01,0x08,0xe6,0x46,0x01,
+ 0x26,0x08,0x5d,0x08,0x4a,0xe5,0x01,0x22,0x37,0x03,0x0a,0x21,0x04,0xe5,0xe6,0x08,
+ 0x0b,0x03,0x15,0x40,0x3f,0x2d,0x02,0x0c,0x36,0x2d,0xe5,0x08,0x32,0xe5,0x2f,0xe5,
+ 0x45,0x28,0x01,0x3d,0x30,0xe6,0x04,0x04,0x66,0x01,0xe5,0x05,0x62,0xe8,0x70,0x03,
+ 0x68,0x03,0x72,0x01,0x3a,0x01,0x2c,0x01,0x01,0xb3,0x20,0x08,0xe5,0x02,0x05,0x6c,
+ 0x06,0x0c,0x2e,0x28,0x01,0xe6,0xe5,0xd9,0xe6,0xe5,0xe5,0xe5,0x01,0xd4,0x01,0x02,
+ 0x01,0x01,0x04,0xa7,0xe5,0x2a,0x04,0xe5,0xe6,0x01,0xa9,0xe5,0xe5,0x2a,0x02,0x02,
+ 0xe6,0x0a,0xa2,0x01,0x25,0x06,0x02,0xe5,0xe5,0x07,0xe6,0xa1,0x01,0x01,0x02,0x01,
+ 0x23,0x04,0xe5,0x4f,0x01,0x5c,0x01,0x2c,0x01,0x01,0xaf,0x01,0x2d,0xe8,0xe0,0xe0,
+ 0x01,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x06,0xe5,0xe5,0xe5,0xd2,0x02,0x04,0x05,0xe5,
+ 0xd4,0x09,0x02,0x46,0x6a,0x2c,0x02,0xe5,0xae,0x01,0xe5,0x2a,0x01,0x01,0xe5,0xaf,
+ 0x2d,0xe5,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe5,0xe7,
+ 0x4b,0xe5,0x27,0x3a,0x2c,0xe8,0x75,0x38,0x01,0x2d,0x01,0xe6,0xaf,0x2c,0x02,0xe5,
+ 0x02,0x48,0x29,0x38,0x01,0x2c,0xe5,0x01,0xaf,0x2d,0xe6,0xe6,0x09,0x06,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x02,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x03,0x07,0x02,0x4f,0x8f,
+ 0xe5,0xe6,0x12,0x15,0x13,0x08,0x08,0x57,0x0a,0x24,0x04,0x02,0x01,0x04,0xe5,0x04,
+ 0xe5,0x40,0x22,0x09,0x66,0x02,0xe6,0x02,0x68,0x13,0x4e,0x08,0xe7,0xe6,0xe5,0x6d,
+ 0x6f,0xe6,0x0a,0x23,0x32,0x09,0x03,0x10,0x5a,0x02,0xe7,0x08,0x0f,0x56,0x62,0x04,
+ 0x04,0xe5,0xe6,0x45,0x2a,0x6d,0x01,0xe6,0x6f,0x61,0x0a,0xe5,0x01,0x71,0x46,0x11,
+ 0x15,0x01,0x51,0x8c,0x03,0xe1,0xe5,0x0b,0x6a,0x67,0xe7,0xe5,0x4c,0xe5,0x8a,0x02,
+ 0x02,0x01,0x02,0x4b,0xe5,0x61,0x24,0x02,0x03,0xe6,0x03,0xa6,0xe5,0x01,0x01,0x22,
+ 0x01,0x02,0x06,0x01,0x02,0xa9,0xe5,0xe5,0xe5,0x21,0x06,0x06,0xe5,0x03,0xcf,0x02,
+ 0x04,0x01,0x01,0xe5,0xe5,0x02,0x04,0x01,0xa6,0x28,0x02,0xe5,0xe5,0x4f,0x5e,0x01,
+ 0x2f,0xe5,0x4f,0xe5,0x5c,0x01,0x2c,0x01,0xe7,0x03,0x4b,0x8b,0xe9,0xdd,0x01,0xe7,
+ 0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x06,0x06,0x01,0xe7,0xd4,0x08,0x01,0x01,0xdf,0x02,0xdf,0x01,
+ 0xe5,0x4f,0x8a,0x02,0x01,0xe7,0xdd,0x01,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x05,0xe7,0xe5,0x4b,0xe5,0x8d,0x02,0xe7,0xdd,0x02,0xe6,0xdb,0x01,0xe7,
+ 0x02,0x48,0x09,0x87,0x01,0xe7,0x26,0xb6,0xe5,0xe5,0x10,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x02,0x06,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0x0d,0x04,0x21,0x28,0x8a,0x03,
+ 0x02,0xe6,0x14,0x11,0x32,0x09,0x09,0x0b,0x50,0x10,0xe5,0xe7,0xe5,0x38,0x12,0x22,
+ 0xe5,0x64,0x06,0x02,0x04,0x03,0x68,0x6b,0x01,0xe8,0x01,0x6d,0x6e,0x01,0xe5,0x1a,
+ 0x14,0x3f,0x5d,0x0d,0xe5,0x01,0xe6,0x19,0x0b,0x49,0x32,0x0e,0x19,0x01,0x0f,0x02,
+ 0x0a,0x12,0x28,0x2a,0x30,0x27,0x05,0x01,0x0c,0xe8,0x33,0x01,0x39,0xe5,0x5f,0x0b,
+ 0x01,0xe5,0x2f,0x14,0x2b,0x6c,0x02,0xe5,0x2c,0x0b,0x38,0x45,0x26,0xe5,0xe5,0xe5,
+ 0x2a,0x1e,0x84,0x0c,0x01,0x01,0x2b,0xe5,0xa5,0x0b,0xe9,0x5a,0x7e,0x01,0x01,0x01,
+ 0x02,0x01,0x49,0x0e,0x7b,0x01,0x03,0xe5,0xe5,0x03,0x33,0x0b,0x18,0x01,0x74,0x01,
+ 0x02,0x04,0x02,0xe5,0x01,0x36,0x20,0xe5,0xe5,0xe5,0x73,0x06,0x02,0x03,0x5d,0x6f,
+ 0x01,0x05,0x07,0xe5,0x02,0x02,0x3f,0x09,0x10,0x03,0x6b,0x01,0x01,0x09,0x03,0xe5,
+ 0xe6,0x3a,0x01,0x03,0x09,0x10,0x01,0x6d,0x01,0x0d,0xe6,0xe6,0x3b,0x01,0x1e,0x01,
+ 0x6d,0x01,0x0f,0xe7,0x44,0x09,0x09,0x83,0xe5,0x02,0x39,0x08,0x03,0x01,0x03,0x03,
+ 0x01,0x09,0x81,0x02,0xe6,0x0d,0x09,0x09,0x04,0x01,0x02,0x09,0x09,0xe5,0x01,0x05,
+ 0xe5,0x01,0x02,0x02,0x04,0x01,0x02,0x02,0x06,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x0d,0x01,0xe5,0xe5,0x01,0x27,0x0e,0xe5,0x13,0x0c,0x7e,0x02,0xe5,
+ 0x01,0x27,0x11,0x1f,0x86,0xe6,0xe5,0x27,0x02,0x0c,0x03,0x16,0x07,0x01,0x7e,0x02,
+ 0xe5,0x2c,0xe5,0x09,0x08,0x09,0x05,0xe5,0x01,0x06,0x01,0xe5,0x7c,0x02,0xe5,0x2c,
+ 0x1a,0x0a,0x01,0x07,0x01,0x7e,0xe8,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x06,0xe6,0xe5,0x2c,0x0a,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x82,0x01,
+ 0x2b,0x0c,0x06,0x01,0x07,0x01,0x07,0x01,0x09,0x7e,0x03,0x2d,0x27,0x07,0x14,0x6b,
+ 0x02,0xe5,0x2a,0x0e,0x18,0x0b,0x12,0x6b,0x01,0xe6,0x2e,0x27,0x08,0x04,0x7a,0xe6,
+ 0xe5,0x0e,0x01,0x01,0x05,0x01,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0xe6,0xe5,
+ 0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x02,0x02,0x27,
+ 0x02,0x0c,0xe5,0x0c,0x07,0x01,0x0c,0x82,0x01,0xe5,0x14,0x08,0x08,0x0c,0x01,0x02,
+ 0x03,0x09,0x09,0x0e,0x7b,0xe5,0x01,0xe5,0x08,0x20,0x06,0x1a,0x24,0x6f,0xe5,0x04,
+ 0x0a,0x09,0x09,0x06,0x01,0xe5,0x04,0x20,0x09,0xe5,0x0f,0x6d,0x01,0xe5,0x04,0x28,
+ 0x0b,0x03,0x09,0x14,0x13,0x6d,0x01,0xe5,0x01,0x06,0x21,0x05,0x08,0x18,0x19,0x15,
+ 0x5a,0x01,0xe6,0x04,0x0d,0x0d,0x2e,0x07,0x18,0x5a,0x11,0xe6,0xe5,0x09,0xe5,0x16,
+ 0x01,0x1d,0x02,0x06,0x0c,0x16,0x30,0x2f,0x0b,0xe5,0xe6,0x0c,0xe6,0x06,0xe6,0x05,
+ 0xe6,0x07,0x09,0x01,0x07,0xe5,0x03,0x2b,0xe5,0x5f,0xe5,0x04,0x04,0xe7,0x0e,0x0a,
+ 0x02,0x03,0x02,0x02,0x02,0xe5,0x12,0xe5,0x2f,0x6d,0x02,0x09,0x19,0x0d,0x05,0x1a,
+ 0x1f,0x45,0x26,0xe8,0x13,0xe5,0x0a,0x06,0x0d,0xe5,0x15,0x84,0x08,0xe9,0x34,0x01,
+ 0x17,0x8e,0x01,0x01,0xe6,0x07,0x01,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5,
+ 0x04,0x09,0x09,0x09,0x08,0xe5,0x11,0xe5,0x6f,0xe5,0x01,0x01,0x02,0x01,0x05,0xe5,
+ 0x03,0x02,0xe5,0x04,0x03,0xe5,0x06,0xe5,0x05,0x09,0x08,0x09,0x0a,0x13,0x06,0x66,
+ 0x01,0x02,0xe5,0xe6,0x03,0x0b,0x09,0x02,0xe5,0x03,0x01,0x08,0x06,0x01,0xe5,0x02,
+ 0xe5,0xe5,0xe6,0x02,0xe5,0xe5,0xe6,0x8b,0x04,0xe5,0xe6,0x01,0x17,0x02,0xe5,0x01,
+ 0x0c,0x03,0x02,0x01,0x04,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0xe5,0x8e,0x03,0x02,0x11,
+ 0xe5,0x08,0x04,0x04,0x09,0x02,0x05,0x05,0x01,0x01,0xe5,0x03,0x01,0x01,0xe5,0x22,
+ 0x6c,0x02,0x02,0x1e,0x01,0x01,0x02,0x01,0x0e,0x05,0x01,0x02,0x04,0x01,0x02,0x8c,
+ 0x03,0xe5,0xe6,0x0f,0x02,0x0c,0x06,0x08,0xe5,0x01,0x01,0x0e,0x01,0x11,0x09,0x78,
+ 0xe5,0xe5,0xe5,0x11,0x02,0x05,0xe7,0x01,0x01,0x01,0xe5,0xe6,0x04,0xe5,0xe5,0xe6,
+ 0xe5,0x02,0xe5,0x06,0x01,0x01,0x05,0xe6,0x08,0xe5,0x07,0xe5,0x77,0xe5,0x01,0x05,
+ 0x03,0x02,0x03,0x01,0x07,0x01,0xe5,0x05,0x01,0x02,0x04,0x01,0x13,0x09,0x0c,0x09,
+ 0x7a,0xe6,0x09,0xe5,0x03,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0x07,0xe5,0x08,0xa4,
+ 0x03,0xe5,0x0d,0xe6,0x06,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0xe5,0x05,0xe5,0x07,0x09,
+ 0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x05,
+ 0xe6,0x02,0x02,0x0f,0x09,0x03,0x05,0x09,0x08,0xe5,0x08,0x09,0x86,0x05,0x04,0xe6,
+ 0xe5,0x18,0x01,0x07,0x09,0x09,0xa7,0xe5,0x0f,0xe6,0x02,0xe5,0x01,0x01,0x03,0x03,
+ 0x01,0x07,0xe6,0x05,0x02,0x04,0x04,0x04,0x04,0x04,0x01,0x07,0x01,0x7c,0x01,0xe6,
+ 0xe5,0x10,0x02,0x04,0xe6,0x01,0x02,0x02,0xe5,0x01,0x06,0x02,0x04,0xe6,0x01,0x04,
+ 0x01,0x02,0x04,0x01,0x05,0x01,0xe5,0x05,0x01,0xe5,0x7d,0xe5,0xe6,0x07,0x09,0x09,
+ 0x10,0x08,0x07,0x09,0x09,0x01,0x07,0x01,0x0d,0x70,0x01,0xe6,0x0f,0x02,0xe5,0xe5,
+ 0x05,0xe5,0xe6,0x04,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x04,0x01,
+ 0x02,0x04,0xe7,0xe5,0x03,0xe7,0xe5,0x02,0xe5,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x06,0x01,0x01,0x10,0x06,0x01,0xe6,0x04,0x02,0xe5,0x07,0xe5,0x06,0xe5,0x01,0xe5,
+ 0x01,0x09,0x0c,0xe5,0x01,0x05,0xe5,0xe5,0x7a,0xe5,0xe5,0x12,0x02,0xe5,0xe5,0x02,
+ 0x02,0x02,0x04,0x01,0x06,0x02,0x02,0xe5,0x04,0x02,0x06,0x02,0x06,0x09,0x07,0x01,
+ 0x77,0xe5,0xe6,0x0f,0xe5,0x01,0xe6,0x01,0x01,0x02,0xe7,0xe5,0xe5,0xe5,0xe6,0x03,
+ 0x02,0xe6,0x01,0x05,0xe6,0x05,0xe7,0x05,0x01,0x09,0x08,0xe5,0x0a,0x6b,0x01,0xe6,
+ 0x12,0x03,0x05,0x03,0x01,0x04,0x08,0x05,0x02,0x01,0x04,0x02,0xe6,0x03,0x02,0x01,
+ 0x05,0x03,0x05,0x02,0xe5,0x0c,0x6c,0xe8,0x1f,0x02,0x0a,0xa5,0x07,0x02,0x01,0x0b,
+ 0x05,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0xe5,0x05,0x01,0x02,0x04,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x03,0x08,0x01,0x0f,0xe5,0xe5,0x05,0xe5,0x04,0xe5,0xe5,0x02,0x05,0x09,0xe5,0x15,
+ 0x05,0xe5,0x03,0x0d,0xe5,0x72,0xe5,0xe7,0x0b,0x01,0x06,0xe5,0xe5,0x02,0x0a,0x0c,
+ 0x01,0x04,0x17,0x05,0x71,0x10,0xe5,0x02,0x22,0x07,0x01,0x03,0x09,0x02,0x05,0x02,
+ 0x06,0x07,0x11,0x01,0x07,0x6d,0x02,0xe5,0xe5,0x13,0x01,0x07,0xe5,0x0b,0x03,0x0e,
+ 0x09,0x05,0xe5,0x01,0x06,0x14,0x65,0x04,0x01,0x02,0x17,0x01,0x02,0x02,0x09,0x25,
+ 0x06,0x09,0x10,0x08,0x65,0xe7,0x1b,0x04,0xe5,0x0b,0x07,0x08,0x09,0x03,0x06,0x01,
+ 0x12,0xe5,0x32,0x30,0x0b,0x01,0xe7,0x10,0xe5,0x0d,0x01,0x1b,0xe5,0x06,0xe5,0x11,
+ 0x05,0x0e,0xe5,0x02,0x13,0x55,0x01,0x3f,0x03,0x02,0x04,0xe5,0x23,0x30,0x2f,0x0b,
+ 0xe5,0x01,0x05,0x10,0x09,0x05,0x03,0x13,0x09,0x07,0x01,0x09,0x10,0x03,0x6c,0x02,
+ 0xe5,0x33,0x1c,0x1f,0x6c,0xe6,0xe6,0x14,0x23,0x04,0x01,0x01,0x0b,0x03,0x01,0x05,
+ 0x5c,0x21,0x02,0xe5,0x01,0xe5,0x16,0x01,0x01,0xe5,0x06,0x20,0x05,0x09,0xe6,0x15,
+ 0x71,0xe6,0x4a,0x09,0x84,0x05,0x01,0x01,0x15,0x09,0x0c,0x0a,0xe5,0xe6,0xe5,0x01,
+ 0xe5,0x01,0xe5,0x0a,0x02,0x01,0x1a,0x06,0x01,0x03,0xe5,0x59,0x05,0x01,0x1f,0x09,
+ 0xe5,0x0b,0x02,0xe5,0xe7,0x03,0xe5,0x01,0xe5,0x06,0xe6,0x1c,0x05,0xe5,0x5d,0x02,
+ 0x03,0xe6,0x02,0xe5,0x11,0x01,0x04,0xe5,0x05,0x06,0x0a,0x02,0xe5,0x01,0x03,0x02,
+ 0xe5,0x02,0x03,0xe5,0x01,0x01,0x1d,0x0d,0x52,0x01,0x02,0x05,0x02,0xe5,0xe5,0x13,
+ 0x06,0x0c,0x13,0x09,0x01,0x07,0x1f,0x60,0x06,0x03,0xe8,0x15,0x02,0x04,0x01,0x02,
+ 0x08,0x04,0x01,0x04,0xe5,0x03,0x01,0x09,0x03,0x02,0xe5,0xe5,0x1c,0x61,0x07,0x04,
+ 0xe6,0x1b,0x01,0xe5,0x08,0x03,0x01,0x02,0x0a,0x01,0x01,0x07,0x01,0x04,0xe5,0xe5,
+ 0xe5,0xe5,0x01,0x16,0x03,0x64,0x02,0x01,0xe5,0x16,0x01,0x07,0x01,0x04,0x04,0x0b,
+ 0x05,0x01,0x07,0x01,0x05,0x01,0x01,0x03,0xe5,0x07,0xe5,0x0d,0x64,0x05,0x01,0xe7,
+ 0x15,0x02,0x02,0xe5,0x01,0x01,0xe5,0x02,0xe7,0x05,0x01,0x05,0x01,0x01,0xe5,0xe5,
+ 0x08,0x07,0x05,0xe5,0x07,0xe5,0x0d,0x6b,0xe7,0x04,0x17,0x02,0x06,0xe5,0x10,0x0a,
+ 0x13,0x02,0x06,0x02,0x76,0xe5,0x02,0x1e,0x1b,0x0b,0xe6,0x06,0xe5,0x11,0xe5,0x1d,
+ 0x59,0x01,0xe7,0x0d,0x09,0xe5,0x01,0x05,0xe5,0x07,0x09,0x06,0x02,0x09,0x06,0x02,
+ 0x09,0x09,0x0b,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x06,
+ 0x04,0x20,0x1a,0x13,0x86,0x07,0xe8,0x1e,0xb5,0x08,0xe8,0x16,0x01,0xe6,0x04,0x01,
+ 0xe6,0x18,0x01,0x07,0x01,0x09,0x26,0x61,0x01,0xe6,0x16,0x01,0x07,0x01,0x15,0x04,
+ 0xe5,0xe6,0x05,0x01,0xe5,0x08,0x03,0x05,0x1f,0x5d,0xe5,0x01,0xe5,0x17,0x01,0x07,
+ 0x01,0x19,0x01,0x07,0x09,0x08,0x20,0x01,0x5d,0xe9,0x08,0x0b,0xe5,0x01,0x05,0xe6,
+ 0x06,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe6,0x04,0x01,0xe5,0x07,0xe5,
+ 0x05,0xe6,0x09,0xe5,0xe5,0xe5,0x03,0xe5,0x08,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,0xe5,0x20,0x1d,0x01,
+ 0x07,0x01,0x05,0x01,0x01,0x05,0x04,0xe5,0x0c,0x0a,0x02,0x01,0x19,0x09,0x3a,0x01,
+ 0x01,0x23,0x1b,0x01,0x07,0x01,0x07,0x01,0x1a,0x0b,0xe5,0xe5,0x05,0x57,0xe8,0x18,
+ 0x25,0x01,0x09,0x05,0x07,0x01,0x01,0x01,0x0d,0xe6,0x01,0x0a,0x01,0x04,0x12,0x01,
+ 0x07,0x01,0x3b,0xe7,0x18,0x20,0x04,0x0b,0xe5,0x01,0x09,0x03,0x01,0xe5,0x0b,0xe5,
+ 0x02,0x0a,0x01,0x17,0x09,0x3c,0x03,0xe5,0x01,0x15,0xe5,0x02,0x04,0xe5,0x19,0x09,
+ 0x01,0xe5,0x08,0x1c,0x69,0x01,0xe7,0x0b,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0xe5,0xe6,0x02,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,
+ 0x06,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x0b,0xe5,0xe5,0x12,0x08,0x0d,0x0c,0xe5,0x15,0x01,0xe6,
+ 0x8d,0xe5,0x14,0x06,0x15,0x02,0x05,0x1d,0x01,0x31,0x28,0x25,0x03,0xe5,0x1b,0x1a,
+ 0x0b,0x0a,0x03,0x09,0x09,0x09,0xe5,0x09,0x09,0x09,0x09,0x44,0xe7,0x03,0xe5,0x12,
+ 0x09,0x1b,0x04,0x04,0x02,0x04,0x03,0x03,0x03,0x01,0x0e,0x02,0x0b,0x3f,0x1f,0x01,
+ 0xe8,0x03,0x2a,0x09,0x03,0x02,0x0a,0x01,0x04,0x05,0x05,0x11,0x0e,0x5d,0x01,0xe7,
+ 0x01,0x05,0x06,0x06,0x09,0x01,0x01,0xe5,0x0a,0x08,0x0e,0xe5,0x10,0x0b,0x08,0x0d,
+ 0x1b,0xe5,0x1c,0x21,0xe5,0xe8,0x03,0x1b,0x1d,0x01,0x07,0x1d,0x09,0x22,0x24,0x25,
+ 0x02,0x23,0xe5,0xe5,0x16,0x04,0x02,0x04,0x15,0x07,0xe5,0x05,0x47,0x02,0x23,0x01,
+ 0xe5,0x1a,0x0a,0x25,0x23,0x31,0x31,0x02,0x05,0x03,0x15,0x1d,0x23,0x09,0x0f,0xe5,
+ 0x1a,0x27,0x13,0x13,0xe8,0x19,0x26,0x09,0x01,0x11,0xe5,0x39,0x01,0x1a,0x07,0x21,
+ 0x1c,0x02,0x08,0x18,0x08,0xe6,0x1f,0x2f,0x41,0x02,0x3f,0x01,0x09,0x0e,0x02,0x10,
+ 0x2d,0x2d,0x13,0xea,0x17,0xe5,0x0b,0x01,0x14,0x02,0xe5,0x01,0x01,0x05,0x0e,0x3d,
+ 0x19,0xe5,0x24,0x01,0x02,0xe5,0x01,0x01,0x16,0x0b,0xe5,0x10,0x01,0x01,0x01,0xe5,
+ 0x02,0xe5,0x02,0xe5,0x11,0x03,0x09,0x2e,0xe6,0x17,0x01,0x20,0x02,0x03,0xe6,0x03,
+ 0x36,0xe5,0x01,0x01,0x01,0x07,0xe5,0x12,0x3a,0x01,0x1e,0x17,0x01,0x02,0x04,0x01,
+ 0x01,0x02,0x3c,0x01,0x09,0x01,0x0c,0xe5,0x3e,0x01,0x1f,0x16,0x06,0x02,0x01,0xe6,
+ 0x20,0x01,0x1b,0x01,0x06,0xe5,0xe6,0xe5,0x0d,0x01,0xe8,0x01,0xe5,0xe5,0x32,0x1b,
+ 0x1b,0x07,0x01,0x01,0xe5,0xe5,0x1e,0x01,0x01,0x12,0x06,0x01,0x01,0x03,0xe6,0xe6,
+ 0xe5,0x11,0xe5,0xe5,0xe6,0xe5,0xe5,0x30,0x01,0x19,0x03,0x1a,0x03,0x01,0x01,0xe6,
+ 0x20,0x01,0x14,0x06,0x01,0x05,0x01,0x01,0xe5,0x16,0x01,0xe5,0xe5,0x32,0x1b,0x06,
+ 0x01,0x1c,0x02,0x21,0x01,0x1b,0x01,0x07,0x01,0xe5,0x12,0x03,0x01,0xe5,0xe5,0x32,
+ 0x1b,0xe5,0x03,0xe5,0x1e,0xe6,0x04,0x17,0x02,0x2d,0x13,0xe5,0x01,0x57,0x1e,0x01,
+ 0x02,0x38,0x0d,0xe5,0x03,0xe6,0x11,0x02,0x59,0x1f,0xe5,0x01,0xe5,0x0d,0x09,0x09,
+ 0x02,0x06,0x09,0xe5,0x04,0x02,0x09,0xe5,0xe5,0x05,0x09,0x01,0x03,0x03,0x0b,0x09,
+ 0x09,0x09,0x09,0x02,0x06,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x02,0x3a,0xe5,0x0d,
+ 0xe5,0x0c,0x05,0x73,0x08,0xe7,0x3a,0x11,0x0b,0x79,0x0a,0x01,0x01,0x21,0x01,0x07,
+ 0x01,0x06,0xe5,0x08,0x09,0x01,0x01,0x0f,0x3c,0xe5,0x1c,0x01,0xe6,0x1f,0xe5,0x01,
+ 0x1a,0x06,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x08,0x06,0x01,0xe6,0x0b,0x04,0x01,
+ 0x39,0x02,0x19,0xe5,0xe5,0xe5,0x20,0x01,0xe5,0x16,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x08,0x09,0xe5,0xe5,0x16,0x37,0x1d,0x01,0x03,0x1d,0xe5,0xe8,0x13,0x01,0x01,0x03,
+ 0xe6,0xe5,0xe5,0x02,0x01,0x01,0x01,0x03,0xe6,0x02,0x05,0xe5,0x07,0xe6,0xe6,0x03,
+ 0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6,
+ 0x06,0xe5,0x07,0xe5,0x07,0xe6,0xe6,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,0xe5,
+ 0x14,0x07,0x01,0x07,0x01,0x07,0x01,0x17,0xe5,0x0f,0x3d,0x1f,0xe6,0x20,0xe7,0x08,
+ 0x0c,0x09,0x09,0x07,0x01,0x16,0xe5,0x11,0x3b,0x1d,0x28,0xe5,0x13,0x01,0x01,0x04,
+ 0xe5,0x08,0x09,0x17,0x11,0x14,0x28,0x1f,0x23,0x02,0x03,0x0f,0x03,0x01,0x03,0xe5,
+ 0x07,0x06,0x02,0xe5,0x17,0x02,0x0e,0x01,0x02,0x38,0x1d,0x04,0x1f,0x01,0x01,0xe5,
+ 0x3d,0xe5,0xe5,0x05,0x02,0x10,0x02,0xe5,0x38,0x01,0xe5,0x19,0x01,0xe5,0x1f,0x04,
+ 0x0a,0x06,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02,
+ 0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x04,0x04,0x01,0x07,0x01,
+ 0x07,0x01,0xe5,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x04,0x02,0x01,
+ 0x07,0x01,0x02,0x04,0x01,0x0a,0x02,0xe5,0x12,0x05,0xe5,0x01,0x20,0x0a,0xe8,0xe5,
+ 0x0a,0x01,0x01,0xe6,0x35,0x1b,0x06,0xe5,0x21,0xe5,0xe6,0x09,0x0a,0x09,0x3c,0x14,
+ 0x4c,0xe5,0x1b,0x04,0x03,0x12,0xe5,0xe5,0x01,0x03,0x09,0x05,0x03,0x14,0x01,0x02,
+ 0x0d,0x01,0x12,0x41,0x05,0x01,0x22,0xe5,0x01,0x04,0x1c,0xe6,0x03,0x02,0x09,0x01,
+ 0x05,0x01,0x02,0x08,0xe5,0x08,0x0d,0x09,0x03,0x44,0x01,0x1e,0x04,0xe5,0xe8,0x01,
+ 0x0f,0x0e,0x0a,0x05,0x04,0x02,0x06,0x07,0x10,0x07,0x0d,0x4a,0x1b,0x05,0xe5,0x01,
+ 0xe5,0x07,0x13,0x09,0x06,0x06,0x02,0x1d,0x08,0x0d,0x03,0x12,0x2b,0xe5,0x0b,0x05,
+ 0xe5,0x15,0xeb,0x10,0x08,0x22,0x0d,0x04,0x0a,0x05,0x0e,0x04,0x0c,0x06,0x05,0x0d,
+ 0x13,0x10,0x01,0xe5,0x04,0x0b,0x05,0xe5,0x01,0x1c,0x09,0x12,0x0c,0x19,0x05,0x0a,
+ 0x44,0x1d,0x0d,0xe5,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x0e,0x04,0x01,0x1c,0x02,
+ 0xe5,0x03,0x09,0x03,0xe5,0x4f,0xe5,0x19,0xe7,0x0f,0x02,0x06,0x09,0x11,0x0c,0x0a,
+ 0x11,0x10,0xe5,0x52,0x18,0xe5,0xe5,0x01,0x0b,0x09,0x09,0x0a,0x29,0x06,0x01,0x14,
+ 0x2d,0x0b,0x01,0x12,0x1a,0x02,0x2b,0xe6,0x21,0x0f,0x03,0x0d,0xe5,0xe5,0x2b,0x0e,
+ 0x09,0x23,0xe5,0xe5,0x3a,0x25,0x01,0x02,0x0c,0x3c,0x0a,0x22,0x01,0x01,0xe6,0x07,
+ 0xe5,0x05,0x09,0x04,0x04,0x04,0x24,0xe5,0x89,0xe6,0x01,0xe5,0x01,0x01,0x04,0xe5,
+ 0x0b,0xe5,0x07,0x09,0x46,0x3c,0xe6,0x10,0xe5,0x11,0x01,0x01,0x02,0xe8,0x03,0x0f,
+ 0x02,0x06,0x04,0x07,0x06,0xe5,0xe5,0xe5,0x21,0xe5,0x02,0x02,0x4c,0x04,0x06,0x02,
+ 0x06,0x11,0x01,0x07,0xe5,0x01,0x11,0x01,0x02,0x04,0x01,0x02,0x07,0x06,0xe5,0xe5,
+ 0xe5,0x21,0xe5,0x4f,0x02,0x06,0x0c,0x17,0x02,0x02,0xe5,0x11,0x01,0x01,0x02,0x02,
+ 0xe5,0x01,0xe5,0x03,0x04,0x09,0x01,0x02,0x24,0x02,0x01,0x01,0x0b,0x3a,0x08,0xe6,
+ 0x05,0x02,0xe5,0xe5,0x01,0x01,0x01,0x12,0x01,0xe5,0x01,0x13,0xe5,0x03,0x04,0x04,
+ 0x04,0x03,0x05,0x01,0x02,0x24,0x01,0xe6,0x01,0x48,0x01,0x01,0x01,0x02,0x04,0x05,
+ 0x01,0x02,0x01,0x01,0x0b,0x02,0x03,0xe8,0x03,0x0b,0xe5,0x01,0x01,0x0b,0x07,0x0f,
+ 0xe5,0x71,0x01,0x09,0x07,0x01,0x17,0xe6,0xe6,0x18,0x09,0x07,0x0e,0x24,0x4f,0x13,
+ 0x01,0x18,0x02,0xe5,0x0c,0x04,0x04,0x04,0xe5,0x07,0xe5,0x11,0x27,0x65,0xe6,0x0c,
+ 0x07,0xe6,0x09,0x12,0xe5,0x07,0xe5,0x3a,0x51,0x09,0x07,0x01,0x14,0xe5,0xe6,0x09,
+ 0x03,0x07,0x01,0x07,0x01,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,0x0b,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x05,0xe5,0x01,0x03,0x05,0x03,0x05,0x06,0x06,0x02,0x01,0x02,
+ 0x14,0x01,0x02,0x04,0x01,0x02,0x13,0x27,0x54,0xe5,0x1b,0xe5,0x03,0x02,0x01,0xe6,
+ 0x19,0x09,0x92,0x1c,0x0a,0x01,0xe5,0xe5,0x2a,0x07,0x04,0x04,0x01,0x07,0x01,0x0e,
+ 0x1a,0x39,0x01,0x06,0x0a,0x01,0x16,0x03,0x01,0x0c,0x03,0xe5,0x08,0x09,0x07,0xe5,
+ 0x02,0x04,0x01,0x05,0x01,0xe5,0x05,0x01,0xe5,0x12,0xe5,0x12,0xe5,0x37,0x01,0xe5,
+ 0x08,0x06,0x01,0xe6,0x17,0x01,0x17,0x01,0x07,0x01,0x09,0x07,0x09,0x01,0x07,0x01,
+ 0x10,0xe5,0x11,0x04,0x38,0x02,0x09,0x07,0x01,0x03,0x14,0xe5,0x01,0x13,0x01,0x01,
+ 0x01,0x03,0x01,0x01,0x01,0x04,0xe5,0x02,0x03,0xe6,0x02,0x04,0x01,0xe5,0xe5,0x02,
+ 0xe5,0xe6,0xe5,0x03,0xe6,0x06,0xe6,0x08,0x08,0xe5,0x03,0x05,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe5,0x06,0xe5,0xe6,0x0c,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x03,0x03,0xe6,
+ 0xe5,0x0f,0x09,0x0e,0x15,0x39,0x01,0x11,0x01,0x18,0xe5,0xe6,0x0c,0x01,0x06,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0x02,0x06,0x02,0x06,0x09,0x09,0x07,0x01,0x09,0x0e,0x39,
+ 0x01,0x11,0x01,0x1b,0xe5,0x0c,0x01,0x03,0x01,0x07,0x01,0x08,0xe5,0x02,0x05,0x01,
+ 0x06,0xe6,0x05,0x01,0xe5,0x08,0x09,0x04,0x03,0xe5,0x0a,0x02,0x3b,0x15,0x18,0x01,
+ 0x04,0x08,0x01,0x02,0xe6,0x06,0xe6,0x06,0xe6,0x03,0x03,0x05,0x02,0xe6,0x07,0xe5,
+ 0x08,0x05,0x03,0x08,0xe5,0x0c,0x02,0x3b,0x29,0x03,0x02,0xe5,0x02,0x1e,0xe5,0x06,
+ 0x01,0x2e,0x02,0x4e,0x01,0xe5,0x05,0x03,0x1f,0xe5,0x02,0x03,0x05,0x07,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,
+ 0x05,0x01,0x07,0x01,0x04,0x02,0x01,0x02,0xe5,0x02,0xe6,0x06,0x01,0x07,0x01,0x0e,
+ 0x08,0x12,0x09,0x02,0x26,0x01,0x0b,0xe5,0x01,0x01,0x72,0x07,0x03,0xe5,0x14,0x05,
+ 0x02,0x09,0x0a,0x13,0x47,0x1b,0x0a,0x25,0x01,0xe5,0xe5,0xe5,0x0d,0xe5,0x03,0x03,
+ 0x05,0x09,0x05,0x1c,0xe5,0x21,0x27,0x05,0x3f,0xe5,0xe6,0x0b,0x01,0x07,0xe5,0x09,
+ 0x1b,0x02,0x06,0x02,0x03,0x01,0x05,0xe5,0x04,0x0e,0x33,0x13,0x02,0x09,0xe6,0x16,
+ 0xe5,0x02,0x0a,0x02,0x02,0x01,0x08,0x25,0x09,0x0c,0x0b,0xe5,0x0a,0x31,0x18,0x21,
+ 0xe9,0x07,0x17,0x02,0x16,0x05,0x09,0x02,0x07,0x06,0x1a,0x32,0x09,0x06,0x06,0x0e,
+ 0x0a,0x02,0x01,0x04,0x07,0x2b,0x06,0xe5,0x03,0x03,0x13,0x02,0x10,0x3d,0x01,0x30,
+ 0x39,0x05,0x09,0x02,0x0b,0x06,0x11,0xe5,0x4a,0x15,0x09,0x02,0xe5,0x07,0x01,0x05,
+ 0x02,0x10,0x19,0x07,0x01,0x01,0x07,0x09,0x0a,0xe5,0x03,0x03,0x3d,0xe6,0x14,0xe5,
+ 0x15,0x01,0xe5,0x13,0x13,0x08,0x1a,0x0c,0x0f,0x07,0x40,0x2c,0xe8,0x0d,0x22,0x09,
+ 0x02,0x01,0x1b,0x01,0x08,0x03,0x0a,0x39,0x09,0xe5,0x1f,0x03,0xe5,0x0e,0x0a,0x0c,
+ 0x2a,0x0c,0x03,0x0e,0x3e,0x06,0x02,0x22,0x02,0xe5,0x0c,0x01,0x4f,0x01,0x4d,0x01,
+ 0x07,0xe5,0x1c,0x08,0xe5,0xe5,0x0a,0x10,0xe5,0x0d,0x03,0x01,0x03,0xe5,0x07,0xe5,
+ 0x01,0xe5,0xe5,0x01,0xe6,0x1a,0xe6,0xe5,0xe5,0x44,0x01,0x04,0x1e,0x01,0x03,0x01,
+ 0x02,0x08,0x22,0x01,0xe5,0x0a,0xe6,0xe5,0x04,0xe6,0x17,0x01,0x03,0x03,0x01,0x45,
+ 0xe5,0x20,0x02,0x02,0xe7,0x03,0x08,0x1d,0x01,0x0b,0x02,0x01,0x06,0xe5,0x01,0x01,
+ 0x01,0x0c,0xe5,0x3b,0x01,0xe5,0xe5,0x03,0x01,0x07,0xe5,0xe5,0xe5,0x09,0xe5,0x1a,
+ 0x07,0xe5,0x01,0x0a,0x1a,0xe5,0xe5,0xe5,0x10,0x01,0x09,0x0e,0x3d,0xe5,0xe5,0xe5,
+ 0x08,0x04,0x02,0x0d,0x15,0xe5,0x05,0x02,0xe5,0xe7,0x08,0x01,0xe5,0x30,0x01,0x07,
+ 0x01,0x04,0x01,0x08,0x03,0xe5,0x46,0x02,0x01,0xe6,0xe6,0x04,0x24,0x01,0x02,0x02,
+ 0x0a,0x03,0x1d,0x0f,0x01,0x01,0x01,0x02,0x02,0x01,0x04,0x13,0x38,0x0c,0x01,0xe5,
+ 0x05,0xe6,0x21,0x02,0xe9,0x0b,0x05,0xe5,0x15,0x01,0x04,0x01,0x0a,0x01,0x02,0x04,
+ 0x01,0x05,0x08,0x01,0x08,0x35,0x01,0x11,0x01,0x2b,0xe7,0xe5,0x0c,0x06,0x16,0x01,
+ 0x11,0x01,0x07,0x01,0x4f,0x01,0x09,0xe5,0x05,0x02,0x0b,0x1f,0xe5,0x01,0xe5,0x13,
+ 0x39,0x13,0x02,0x41,0x09,0x02,0x02,0x05,0x18,0xe5,0x03,0x02,0x01,0x50,0x01,0x11,
+ 0x47,0x09,0x21,0x05,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x02,0x06,0x05,0x03,
+ 0x06,0x02,0x03,0x05,0x0b,0x09,0x09,0x09,0x09,0x09,0xe5,0x03,0x03,0xe5,0x01,0xe5,
+ 0xe5,0x01,0x09,0x09,0x0b,0x01,0x01,0x01,0xe5,0x58,0x02,0x47,0x09,0x0f,0x1f,0xe5,
+ 0x01,0x5b,0x45,0x0b,0x30,0xe5,0x01,0x0f,0x07,0x01,0x25,0x01,0x06,0xe5,0xe5,0x13,
+ 0x05,0xe5,0xe5,0x30,0x01,0x07,0x02,0x09,0xe5,0x01,0x02,0x01,0x02,0x22,0xe5,0x0e,
+ 0xe5,0x05,0x01,0xe5,0x22,0xe5,0xe6,0x05,0x01,0xe5,0x19,0x01,0xe5,0x2f,0x01,0xe5,
+ 0x07,0x0e,0x02,0x01,0x01,0x21,0x01,0xe5,0x0e,0x07,0x01,0x17,0x0d,0x01,0x25,0x01,
+ 0x31,0x01,0x14,0x06,0x01,0x03,0x1d,0x03,0xe6,0x0d,0x03,0xe8,0xe5,0x02,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x05,0x01,0xe5,0x07,0xe5,
+ 0x01,0x05,0xe6,0xe5,0x02,0xe6,0x09,0xe5,0x07,0xe5,0x08,0xe5,0x06,0xe7,0xe5,0x02,
+ 0x01,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x02,0x0f,
+ 0xe6,0x01,0x09,0x13,0x0c,0x09,0x01,0xe5,0x03,0x04,0xe5,0x02,0x13,0x29,0xe5,0x05,
+ 0x01,0x15,0x01,0x23,0x02,0x0f,0x03,0x02,0x09,0x07,0x01,0x09,0x0a,0x09,0x01,0xe5,
+ 0x1f,0x02,0x09,0x01,0x09,0x34,0x22,0xe8,0x0e,0x05,0x07,0x01,0xe5,0x05,0x01,0xe5,
+ 0x05,0x01,0xe5,0x09,0x09,0x01,0x03,0x01,0x09,0x12,0xe5,0x01,0x11,0x13,0xe5,0x08,
+ 0x0b,0x09,0x01,0x23,0x01,0xe5,0x0b,0x02,0xe5,0x01,0xe7,0x05,0xe5,0x04,0x02,0xe5,
+ 0x07,0x0d,0x09,0x01,0xe5,0x01,0x06,0x02,0x10,0x02,0x08,0x03,0x09,0x12,0xe5,0x07,
+ 0x19,0x02,0x1f,0x03,0xe5,0x0b,0xe5,0xe5,0x27,0x05,0x06,0x02,0x13,0x02,0x44,0x01,
+ 0xe5,0x06,0x01,0x04,0x05,0x21,0x01,0xe5,0x10,0x01,0x02,0x04,0x01,0x07,0x01,0x07,
+ 0x01,0x01,0x05,0x01,0x03,0x03,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0xe6,
+ 0x06,0x01,0x01,0x02,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0x07,
+ 0x01,0xe5,0x02,0x02,0x01,0xe6,0x04,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01,
+ 0x0a,0xe5,0x01,0x0e,0x11,0x20,0x08,0x04,0x0d,0xe5,0x38,0x09,0x04,0xe5,0x0b,0x05,
+ 0xe5,0x20,0x02,0xe6,0x0a,0x1c,0x04,0x0e,0x05,0x04,0x27,0x01,0x11,0x14,0x05,0x0d,
+ 0x0a,0x01,0x07,0x1a,0x01,0xe7,0x01,0x19,0x23,0x02,0x0e,0x09,0x09,0x09,0xe5,0x09,
+ 0x09,0x09,0x09,0x0a,0x01,0x01,0x11,0x22,0x01,0x01,0x0a,0x0c,0xe6,0x1f,0x09,0x06,
+ 0x04,0xe5,0x0c,0x07,0xe6,0xe5,0x2e,0x02,0x06,0x02,0x06,0xe7,0x05,0x01,0x0d,0x15,
+ 0x01,0xe5,0x07,0x0e,0x21,0x10,0x12,0x09,0x09,0x2b,0x0a,0x06,0x0b,0x21,0x01,0x01,
+ 0xe5,0x08,0x09,0x09,0x09,0x1d,0x0e,0xe5,0x0c,0x09,0xe5,0x01,0x06,0x23,0xe5,0x03,
+ 0xe5,0x03,0x08,0x04,0x02,0x04,0xe5,0x08,0x13,0xe7,0xe5,0x08,0x0c,0x03,0x13,0x0b,
+ 0x07,0x09,0xe5,0x09,0x07,0x10,0x24,0x04,0x04,0x04,0x0e,0x04,0x01,0x0a,0x16,0x01,
+ 0xe7,0x3d,0x0e,0xe6,0x06,0x15,0x03,0xe5,0x29,0x09,0x0a,0x05,0x05,0x13,0x01,0x03,
+ 0x09,0x06,0x01,0x0a,0x0c,0x08,0xe5,0x07,0xe5,0x1e,0x0c,0x0f,0x29,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x05,0x20,0x04,0x02,0xe6,0x02,0x1a,0x09,0x09,0x15,0x0b,0x03,0x0b,0x0c,
+ 0x29,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x01,0x24,0x06,0x02,0x35,0x01,0x1a,0xe5,
+ 0xe5,0x04,0x1d,0x09,0x09,0x0b,0x03,0x02,0xe5,0x06,0x01,0x09,0x05,0x1e,0x06,0xe6,
+ 0x19,0x1d,0x0d,0x04,0xe5,0x02,0x03,0xe5,0x16,0x2d,0xe5,0x08,0x10,0x02,0xe5,0x22,
+ 0xe6,0x53,0x18,0x2f,0x09,0x11,0x01,0x1e,0x03,0xe5,0x01,0x01,0x26,0xe5,0x03,0xe5,
+ 0x01,0xe5,0x03,0x03,0x01,0x0a,0x02,0x09,0xe5,0x0e,0x37,0xe5,0x03,0x09,0x06,0x01,
+ 0x04,0xe5,0x19,0x02,0x03,0xe7,0xe5,0xe5,0x22,0x01,0x07,0xe5,0xe5,0x05,0x01,0xe7,
+ 0x06,0x06,0x01,0xe5,0x12,0x33,0x03,0xe5,0x04,0x08,0xe6,0x03,0x01,0x02,0x01,0x1d,
+ 0x02,0x01,0xe6,0x03,0x0f,0x01,0xe5,0xe5,0x14,0x0c,0xe5,0xe5,0x08,0x0d,0x0f,0x30,
+ 0x01,0x02,0x18,0x01,0xe5,0x01,0x24,0xe5,0x01,0x14,0x01,0x1b,0x06,0x02,0x01,0x07,
+ 0x05,0xe5,0x01,0x13,0x44,0x02,0x06,0x04,0xe5,0x1a,0x02,0x01,0xe5,0xe5,0xe6,0x07,
+ 0x02,0x2b,0x02,0x01,0xe5,0x01,0x07,0x10,0x01,0x0a,0x40,0x01,0x02,0x01,0x01,0x02,
+ 0x02,0xe6,0xe5,0x03,0x01,0x1a,0xe6,0xe6,0xe5,0x02,0x15,0x19,0x06,0x01,0xe5,0xe5,
+ 0xe5,0x03,0xe5,0x02,0x05,0x03,0x04,0x0a,0x03,0x2f,0x02,0xe5,0xe5,0x01,0x04,0xe5,
+ 0x02,0xe5,0xe5,0x01,0xe5,0xe6,0x01,0x03,0x02,0x18,0x01,0x01,0xe7,0x16,0x01,0x04,
+ 0x13,0x09,0x01,0xe5,0x06,0x01,0x06,0x02,0x07,0x0b,0x36,0x0e,0x01,0x01,0x0c,0x1e,
+ 0xe6,0xe6,0x16,0x01,0x03,0xe6,0x10,0xe6,0xe5,0x01,0x06,0x01,0x07,0x05,0xe6,0xe5,
+ 0x12,0x40,0x06,0x01,0x0c,0x1e,0xe6,0x01,0xe5,0x36,0x0c,0x02,0x57,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x07,0x1f,0x02,0xe5,0x3b,0x09,0xe5,0x55,0xe6,0x0a,0xe5,0x05,
+ 0x03,0x04,0x02,0x20,0xe6,0x0d,0x09,0x09,0x09,0x06,0x02,0xe5,0x01,0x05,0x02,0x06,
+ 0x09,0x02,0x06,0x09,0x0b,0x09,0x09,0x09,0x09,0xe6,0x01,0x01,0x02,0x06,0x02,0x09,
+ 0x05,0x03,0x09,0x0d,0x03,0xe5,0x01,0x2e,0x0c,0x5b,0x05,0x0a,0x02,0x0f,0x1c,0x03,
+ 0x01,0xe5,0x3c,0x59,0x14,0x32,0xe7,0x16,0x01,0x1d,0xe6,0x18,0x01,0x42,0x04,0x02,
+ 0x10,0x04,0x07,0x23,0x17,0x01,0xe5,0x18,0xe5,0xe5,0x05,0x03,0x0f,0xe5,0xe6,0x40,
+ 0x04,0xe6,0x08,0x05,0x02,0xe5,0x01,0x06,0x01,0x1e,0xe5,0x01,0x17,0x01,0x1d,0x1b,
+ 0x01,0x47,0x06,0xe5,0x04,0x09,0xe5,0x01,0x05,0x16,0x07,0x03,0x13,0x01,0xe6,0xe5,
+ 0x02,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x07,0xe6,
+ 0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,0xe5,0x15,
+ 0x03,0xe5,0x01,0x0f,0xe5,0x06,0x07,0x15,0xe5,0x43,0x1d,0x24,0x03,0x15,0xe5,0x05,
+ 0x02,0x09,0x06,0x02,0xe5,0x0a,0x13,0xe5,0x43,0x01,0x41,0x02,0x13,0x01,0x09,0xe5,
+ 0x05,0x01,0xe5,0x06,0xe6,0x01,0x1d,0x1c,0x28,0x01,0x41,0x02,0x0c,0x06,0xe5,0x04,
+ 0x02,0xe5,0x07,0xe5,0x04,0x02,0x10,0x12,0xe5,0x43,0x01,0x02,0x09,0x04,0x04,0x04,
+ 0x04,0x1f,0xe5,0xe7,0x30,0x05,0x03,0x02,0x09,0x04,0x02,0x01,0xe5,0xe5,0xe5,0x0d,
+ 0xe5,0xe5,0x2f,0x02,0xe5,0x04,0x01,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x1f,0xe6,
+ 0x01,0x11,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0x02,0x04,0x01,0x07,0x01,0x01,
+ 0x05,0x01,0xe5,0x02,0x02,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x04,0x04,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0xe6,0x03,0x02,0x01,0x04,0x02,0x01,0x02,
+ 0xe5,0x02,0x01,0x07,0x01,0x07,0x01,0x0d,0xe5,0x34,0x0a,0x02,0x04,0x0e,0x10,0x27,
+ 0x09,0xe5,0xe7,0x03,0x02,0xe5,0x04,0x06,0x07,0x23,0xe6,0x03,0x10,0x12,0x14,0x06,
+ 0x10,0x03,0x0b,0x07,0x2d,0xe5,0x0d,0x08,0x02,0x05,0x1e,0xe6,0xe6,0x08,0x0b,0x06,
+ 0x02,0x05,0x01,0x08,0x13,0x07,0x0c,0x09,0x0d,0x32,0xe5,0xe5,0x05,0x0f,0x1f,0x01,
+ 0x01,0xe5,0x03,0x0b,0x05,0x01,0x01,0x04,0x16,0x04,0x02,0x01,0x0e,0x02,0x01,0x18,
+ 0x2c,0x06,0x02,0x0b,0xe6,0x01,0x01,0xe7,0x0f,0x12,0x02,0x02,0x02,0x11,0x02,0x0e,
+ 0x07,0x03,0x04,0x03,0x03,0x01,0xe5,0x0d,0xe5,0x04,0x06,0x0e,0x2c,0x09,0x02,0x04,
+ 0x09,0x23,0xe5,0xe7,0x07,0xe5,0x14,0x06,0xe5,0xe5,0x0b,0x03,0x03,0x02,0x09,0x0c,
+ 0x09,0x05,0x07,0x04,0x22,0x0c,0xe5,0x07,0xe6,0x07,0x03,0x13,0x0c,0x01,0x04,0xe5,
+ 0x0d,0x07,0x18,0xe6,0x03,0xe5,0x04,0x1c,0x06,0x09,0x18,0x1d,0x0b,0x04,0xe5,0x05,
+ 0x1e,0x01,0x1e,0x09,0x0a,0xe5,0x17,0x16,0x02,0x02,0x06,0x2f,0x16,0x02,0x16,0x01,
+ 0x03,0x07,0xe6,0x12,0x08,0x03,0x09,0x18,0x0b,0x12,0x0e,0x02,0x38,0x01,0xe5,0x07,
+ 0xe5,0xe5,0x1a,0x07,0x01,0x47,0x29,0x02,0x2a,0x04,0x06,0xe5,0x01,0xe5,0x01,0x05,
+ 0xe5,0x1c,0x05,0x03,0x09,0x07,0x01,0x09,0x08,0xe6,0x05,0x02,0x04,0x06,0x02,0x0a,
+ 0x01,0x1f,0x06,0x31,0x09,0x03,0xe5,0x13,0x12,0xe6,0xe5,0x07,0x2d,0xe5,0x0a,0xe5,
+ 0x03,0x01,0x07,0x01,0x02,0x06,0x14,0xe5,0x27,0x07,0xe5,0xe5,0x03,0xe5,0xe5,0x06,
+ 0x01,0x01,0x1f,0xe5,0x02,0x37,0x07,0x05,0x19,0x14,0x05,0x24,0x07,0x07,0x0d,0x20,
+ 0xe8,0x35,0x01,0x09,0x10,0x02,0x07,0x6f,0xe5,0xe5,0x0c,0x01,0xe5,0x01,0x01,0xe5,
+ 0x03,0xe5,0x29,0x1d,0x89,0x03,0xe6,0x25,0xe5,0x0d,0xe5,0x01,0x01,0xe5,0x01,0xe5,
+ 0x18,0x09,0x36,0x1a,0x05,0xe5,0x1a,0xe6,0xe7,0x01,0x01,0x05,0x01,0x14,0xe5,0x15,
+ 0x02,0x01,0xe7,0x11,0xe5,0x06,0x09,0xe6,0x37,0xe5,0xe5,0x03,0x04,0xe6,0x0d,0x01,
+ 0x16,0x01,0x03,0x02,0x04,0x04,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x09,0x07,0x01,
+ 0x0e,0x01,0xe5,0xe5,0xe5,0x07,0x02,0xe5,0x01,0x01,0x07,0x01,0x07,0x01,0xe5,0x36,
+ 0xe5,0xe5,0x05,0xe5,0x03,0x01,0x24,0x04,0x01,0xe6,0x01,0x07,0x02,0x01,0x04,0x02,
+ 0x01,0x07,0x06,0x02,0x01,0x13,0x11,0x01,0x07,0x01,0x07,0x01,0x38,0x02,0x06,0x02,
+ 0x01,0x04,0xe5,0xe5,0x20,0x05,0xe5,0x0a,0x09,0x0d,0x05,0x0b,0x01,0x07,0x05,0x02,
+ 0x04,0x07,0x07,0x02,0x06,0x03,0xe5,0x35,0x01,0x02,0x04,0xe6,0xe5,0xe5,0x07,0x02,
+ 0x02,0x1b,0x01,0x01,0x01,0x03,0x0b,0x09,0x05,0x03,0x04,0x04,0x05,0x01,0x01,0x05,
+ 0x01,0x01,0x11,0x01,0x05,0x02,0x06,0x04,0x38,0x02,0x02,0x01,0xe6,0xe5,0xe5,0x03,
+ 0x04,0x02,0x01,0x18,0x02,0xe8,0x0c,0x01,0x07,0x01,0x03,0xe5,0x03,0x03,0xe6,0xe5,
+ 0xe5,0x06,0x01,0x04,0x01,0xe5,0x05,0x01,0x05,0x01,0x01,0xe5,0xe5,0x06,0x01,0x07,
+ 0x06,0x1f,0x01,0x10,0xe5,0x01,0x09,0x01,0x04,0xe6,0x1e,0x04,0x01,0xe7,0x01,0x0a,
+ 0x01,0x07,0x01,0x04,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x06,0x01,0x03,0xe5,0x01,0x01,
+ 0x03,0xe5,0x08,0x01,0xe5,0xe5,0x06,0x01,0xe5,0x05,0x06,0xe5,0x1c,0xe5,0x12,0x01,
+ 0xe5,0x01,0x06,0x01,0x04,0x01,0x03,0x23,0xe6,0x01,0x02,0x03,0x3b,0x02,0x05,0xe6,
+ 0x0e,0x02,0xe5,0x06,0x02,0x38,0x02,0xe5,0x04,0x02,0x02,0x26,0x01,0xe5,0x09,0x01,
+ 0x39,0xe5,0x07,0xe5,0x19,0x3b,0x0a,0x0c,0x1e,0xe5,0xe6,0x07,0x05,0x09,0x09,0x09,
+ 0x09,0x09,0x06,0x02,0x09,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x0b,0x09,0x09,0x09,
+ 0x09,0x04,0x01,0x02,0xe5,0x07,0x09,0x03,0x05,0x09,0x0d,0xe7,0xe5,0x01,0x3b,0x06,
+ 0x08,0x03,0x10,0x40,0x09,0x04,0xe5,0x25,0x03,0xe7,0x3a,0x13,0x51,0x09,0x32,0x03,
+ 0x17,0x01,0x04,0x13,0x04,0x06,0x0a,0x01,0x09,0x07,0x01,0xe6,0x04,0x01,0x0b,0x0e,
+ 0x22,0xe6,0x07,0xe5,0x04,0x01,0x01,0x02,0x1b,0x01,0x03,0x17,0x01,0xe5,0x1b,0xe5,
+ 0x08,0x03,0x02,0x01,0x01,0x08,0x06,0x01,0x07,0x01,0xe6,0x08,0xe5,0x2c,0xe5,0x07,
+ 0x04,0x01,0x05,0x24,0x01,0x14,0x02,0x01,0x1a,0x02,0x04,0x08,0x03,0x01,0x09,0x09,
+ 0x07,0x01,0x03,0x02,0x04,0x31,0x0a,0x08,0xe5,0x20,0x02,0xe6,0x12,0xe7,0xe5,0x02,
+ 0x01,0xe5,0x07,0xe5,0x05,0xe7,0x01,0x03,0xe7,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x07,
+ 0xe6,0x01,0x03,0xe7,0xe5,0x04,0xe5,0x03,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe6,0x01,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,
+ 0x01,0x1a,0xe5,0xe5,0x05,0xe5,0x0a,0x05,0xe6,0x01,0x05,0xe5,0x04,0x01,0x13,0x07,
+ 0x0d,0xe5,0x12,0xe5,0x1a,0x36,0x03,0x14,0x01,0x1b,0x01,0x02,0x06,0x0a,0x01,0x09,
+ 0x09,0x06,0x02,0x0b,0xe5,0x2d,0x38,0x02,0xe6,0x1d,0x13,0x03,0x03,0x01,0x0d,0x13,
+ 0x04,0xe5,0xe5,0x09,0x02,0x31,0x07,0x2e,0x01,0x01,0x10,0x03,0x01,0x03,0x02,0x01,
+ 0x04,0x09,0x03,0xe6,0x01,0xe5,0x03,0xe5,0x02,0x0b,0x06,0x0d,0xe7,0x01,0x02,0x08,
+ 0xe5,0x12,0x26,0x02,0x11,0x1b,0xe5,0x3d,0x03,0x09,0x03,0x01,0x07,0x01,0x01,0xe5,
+ 0x08,0x3a,0x09,0x09,0xe5,0xe5,0x1f,0xe5,0x01,0xe5,0x10,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x03,0x02,0xe5,0xe5,0xe5,
+ 0xe5,0x02,0x01,0xe5,0x05,0x01,0x04,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0x05,0x01,0x07,0x01,0x02,
+ 0x09,0xe6,0x07,0x02,0x09,0x13,0x0d,0x08,0x03,0x08,0x19,0x06,0x37,0x0f,0x27,0x01,
+ 0x01,0xe5,0x0a,0x09,0x05,0x07,0x19,0x05,0x02,0x0a,0x03,0xe5,0x12,0x52,0x1e,0x04,
+ 0x05,0x2a,0x05,0x03,0x28,0x09,0x03,0x43,0x28,0x01,0x01,0xe5,0x06,0x0e,0xe6,0x0d,
+ 0xe5,0x14,0x09,0x01,0x01,0x02,0x02,0x01,0x07,0x0b,0x38,0x02,0xe7,0x05,0x01,0x07,
+ 0x24,0x03,0x18,0x06,0x1d,0x03,0x05,0x04,0x02,0x05,0x0a,0x06,0x03,0x01,0x03,0x07,
+ 0x2c,0x0a,0x04,0x04,0x24,0x01,0xe5,0x0f,0x01,0x09,0x1d,0xe5,0x03,0x03,0xe5,0x01,
+ 0xe6,0x06,0x07,0x03,0x11,0xe5,0x0e,0x11,0x16,0x03,0x19,0x08,0x0b,0x01,0xe6,0x1e,
+ 0x06,0xe5,0x07,0x07,0x06,0xe5,0xe5,0x04,0xe5,0x0d,0x02,0x02,0x07,0x0a,0x4a,0x19,
+ 0x09,0x01,0x26,0x18,0x03,0x07,0x02,0x09,0x18,0x37,0x31,0x02,0xe5,0x01,0x08,0x16,
+ 0x09,0x15,0xe6,0x03,0x01,0x06,0x02,0x18,0x05,0xe5,0x3a,0xe6,0x0b,0x22,0x01,0x01,
+ 0x1a,0x1e,0x06,0x01,0x0b,0x06,0x0a,0x0e,0x38,0x04,0x01,0x20,0xe5,0x0c,0xe5,0x3d,
+ 0x03,0x02,0x05,0x59,0x01,0xe5,0x2f,0x04,0x02,0xe5,0xe5,0x07,0x1b,0x09,0x09,0x0f,
+ 0xe6,0x17,0x4e,0x28,0x01,0xe5,0xe5,0xe5,0x02,0x18,0x09,0x1b,0x06,0x02,0xe5,0x08,
+ 0x1d,0x3b,0x2a,0x03,0x01,0x01,0x3b,0x04,0x04,0x02,0x55,0x01,0x0f,0x27,0x01,0xe5,
+ 0xe6,0xe5,0x3c,0xe5,0x07,0xe6,0x15,0x3f,0x01,0x0a,0xe5,0x27,0x01,0x02,0x01,0xe6,
+ 0x03,0x37,0xe5,0xe5,0xe5,0x06,0x01,0x56,0xe5,0x03,0x03,0x01,0xe5,0x28,0x04,0xe9,
+ 0xe5,0x37,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x56,0x04,0xe5,0x02,0x04,0x22,0xe5,
+ 0x04,0x02,0xe6,0xe6,0x3d,0x01,0x02,0x01,0x01,0x02,0x11,0x01,0x43,0x06,0x02,0xe5,
+ 0x01,0x02,0x01,0x01,0x24,0x02,0xe8,0x02,0x39,0x04,0xe5,0x01,0x02,0x01,0x0f,0x01,
+ 0x01,0x48,0xe5,0xe7,0x03,0x03,0x22,0x03,0x02,0x05,0x39,0x01,0x02,0x04,0x01,0x04,
+ 0x01,0x0a,0x01,0x4f,0x04,0x02,0x25,0xe7,0xe6,0x26,0x01,0x14,0x09,0x01,0x04,0x01,
+ 0x0a,0x01,0x47,0x09,0x2c,0xe8,0x04,0x03,0x3a,0xe5,0x01,0x06,0x02,0x57,0xe5,0x07,
+ 0xe6,0x25,0xe5,0xe7,0x09,0x01,0xa1,0x2f,0x01,0x01,0xe5,0x07,0x05,0x09,0x09,0x09,
+ 0x09,0x06,0x02,0x04,0x01,0x02,0x02,0x06,0x09,0x02,0x06,0x0b,0x09,0x09,0x09,0x09,
+ 0x09,0x06,0x02,0x09,0x09,0x09,0x06,0x06,0x02,0x01,0x3b,0x02,0x05,0x03,0x61,0x02,
+ 0xe5,0x04,0x1e,0x02,0x04,0x03,0x01,0xe5,0x3c,0x09,0x65,0x26,0x0d,0x3c,0x0b,0x66,
+ 0x2e,0x01,0xe6,0x1d,0x24,0x05,0x01,0xe5,0x5b,0x07,0x01,0x2a,0x02,0xe6,0xaa,0x33,
+ 0xe6,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x01,0x01,0x09,0x1a,0xe5,
+ 0x7e,0x09,0x32,0x41,0x07,0x01,0x59,0x0b,0x2e,0xe6,0x3e,0x32,0x3c,0x2e,0xe6,0xe5,
+ 0x23,0x1c,0x02,0x65,0x06,0x02,0x2b,0x01,0xe5,0x3d,0x09,0xe5,0xe5,0x57,0xe5,0xe5,
+ 0x09,0x2a,0x01,0x01,0x11,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x02,0x04,
+ 0x01,0x07,0xe6,0x02,0x03,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x01,
+ 0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x0a,0x02,0xe5,0x3d,0x01,0x24,0x3e,0x39,0x01,0x01,0xe5,
+ 0x09,0x0a,0x13,0x1c,0xe5,0x12,0x03,0x05,0x4d,0x28,0xe5,0x01,0xe5,0x2f,0x09,0x09,
+ 0x2c,0x6d,0x02,0xe5,0x3a,0x02,0xe5,0x09,0x59,0x02,0x06,0x01,0x04,0x26,0x02,0x01,
+ 0x1d,0x09,0x08,0x0a,0x01,0x08,0xe5,0xe5,0x16,0x0f,0x36,0x08,0x2d,0x02,0xe5,0x3e,
+ 0xe5,0x0c,0x06,0x16,0x03,0x2c,0x0b,0x04,0xe6,0x03,0x1a,0x0b,0x01,0xe7,0x07,0x09,
+ 0x13,0x13,0x03,0xe5,0xe5,0x01,0x03,0x09,0x17,0x06,0xe5,0x0c,0x13,0x49,0x02,0xe5,
+ 0x3b,0x07,0x09,0x09,0x18,0x42,0x2a,0xe7,0x46,0x07,0x21,0x47,0xe5,0x22,0xe6,0xe5,
+ 0x70,0x47,0x01,0x23,0xe7,0x3e,0x01,0x6d,0x01,0xe5,0x05,0x01,0x22,0xe5,0xe6,0x40,
+ 0xe5,0x6d,0x09,0x23,0xe7,0x3f,0x02,0x01,0x63,0x06,0x02,0x07,0x23,0x01,0xe7,0x10,
+ 0xe5,0x29,0x7d,0x1e,0xe6,0xe5,0xe5,0x01,0x01,0x0f,0x01,0x2a,0x02,0x71,0xe5,0x20,
+ 0x01,0x02,0xe6,0xe5,0x03,0x19,0xe5,0xe5,0xe5,0x1a,0x6c,0x01,0x02,0xe5,0x09,0x1b,
+ 0x04,0xe8,0x01,0x1e,0x01,0x18,0xe5,0x02,0x6a,0x02,0x2b,0x02,0x01,0x01,0x46,0x01,
+ 0x64,0x03,0x01,0xe6,0x01,0x05,0x1f,0x01,0x01,0x02,0x22,0x1d,0x04,0x66,0x04,0x26,
+ 0x03,0xe5,0xe6,0x1f,0x01,0x1d,0x05,0x1c,0x01,0x48,0x04,0x01,0x01,0x04,0x1f,0x01,
+ 0x01,0xe5,0x20,0x01,0x1b,0x23,0xe5,0x4b,0x04,0x01,0x29,0x45,0x02,0x6b,0x09,0x20,
+ 0xe7,0x45,0x6c,0x0a,0x1f,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x06,0x02,0x03,0x05,
+ 0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x06,0x02,0x06,0x02,0x09,0x09,0x0d,
+ 0xe6,0xe6,0x01,0x3a,0x6f,0xe5,0x04,0xe5,0x07,0x1c,0x02,0x02,0xe5,0xac,0x31,0x02,
+ 0x01,0x1f,0x01,0x11,0x01,0x07,0x01,0x11,0x01,0x07,0x01,0x4f,0x0e,0x1d,0x01,0x01,
+ 0x01,0x21,0x01,0xe5,0x0f,0x01,0xe5,0x07,0xe5,0x0f,0x01,0xe5,0x05,0x01,0xe5,0x50,
+ 0xe5,0xe5,0x06,0x1d,0x02,0xe5,0x01,0x21,0x01,0x11,0x01,0x06,0xe5,0xe5,0x10,0x01,
+ 0x07,0x01,0x4c,0x02,0x0f,0x21,0xe5,0x14,0xe5,0x05,0xe8,0xe5,0x02,0xe7,0x05,0x01,
+ 0xe6,0xe5,0x03,0xe7,0xe5,0x02,0x01,0xe5,0x07,0xe6,0xe5,0x02,0x01,0xe6,0xe5,0x02,
+ 0xe7,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,0x16,0x09,0x06,0xe5,0xe5,0x08,
+ 0x07,0x01,0xe5,0xe6,0x04,0x10,0x06,0xe5,0x03,0x48,0x09,0x02,0x1f,0x03,0xe6,0x14,
+ 0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x03,0x01,0xe5,0x07,0x09,0x08,
+ 0xe6,0x76,0x02,0xe5,0x14,0x09,0x09,0x07,0x01,0x09,0x01,0x01,0xe5,0x03,0x09,0x09,
+ 0x07,0x01,0x0c,0x3c,0x09,0x02,0x25,0x1a,0x02,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x01,
+ 0x01,0xe5,0x01,0xe5,0x07,0x09,0x06,0x02,0xe5,0x4e,0x09,0x23,0xde,0x02,0xe5,0xe5,
+ 0x0e,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0x02,
+ 0x04,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01,0x04,0x04,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,
+ 0x01,0xe6,0xe5,0x15,0x1c,0x0d,0xe5,0x21,0x55,0xe6,0x1b,0x04,0x01,0xe6,0x0a,0x08,
+ 0x29,0x01,0x0e,0x0f,0xe5,0x01,0x54,0x23,0xe5,0xe5,0xe5,0x39,0x36,0x48,0x23,0x03,
+ 0x05,0x1b,0x01,0x0a,0x08,0x0a,0x03,0x05,0x06,0x02,0x06,0x01,0x59,0x01,0x22,0xe8,
+ 0x04,0x02,0x18,0x01,0x03,0x09,0x03,0x07,0x06,0x02,0x0e,0x02,0xe5,0x01,0x01,0x11,
+ 0x43,0x03,0x02,0x21,0xe8,0x12,0x09,0x1d,0x09,0x2b,0x0e,0x27,0x01,0x1b,0x18,0x02,
+ 0x02,0x02,0x0a,0x09,0x27,0xe5,0x04,0x27,0xe5,0x20,0x27,0x13,0x0f,0xe6,0x02,0x02,
+ 0x35,0x06,0x05,0x04,0x02,0x06,0x18,0x6c,0x01,0x01,0x3f,0xe6,0xe6,0x09,0x01,0x1f,
+ 0x6c,0xe6,0xe5,0x02,0x3e,0x01,0x12,0x19,0x41,0xe5,0x28,0xe5,0x01,0x28,0x18,0x22,
+ 0x09,0x6c,0x02,0x03,0xe5,0x3f,0x07,0x01,0x01,0x8f,0xe7,0xe5,0x31,0x0c,0x01,0x38,
+ 0x63,0x02,0xe5,0xe5,0x35,0x06,0x02,0xe5,0x14,0xe5,0x04,0xe5,0x76,0x02,0x05,0x01,
+ 0x02,0x3c,0xe5,0x06,0xe5,0x0c,0xe5,0x7f,0x02,0x01,0xe6,0x03,0x26,0x01,0x0d,0xe5,
+ 0x08,0xe5,0xe5,0xe5,0x01,0x12,0x7c,0x01,0xe6,0x01,0x25,0x02,0x01,0x18,0xe5,0xe5,
+ 0xe5,0x8b,0x02,0x01,0x02,0xe7,0x08,0x01,0x1c,0x15,0x09,0x93,0x02,0xe6,0xe5,0x06,
+ 0x02,0x22,0x11,0x01,0x01,0x02,0xe5,0x02,0x8d,0x01,0x01,0xe5,0xe5,0x2a,0x01,0x0d,
+ 0xe5,0x07,0xe5,0x01,0x01,0x91,0xe7,0xe5,0xe6,0x27,0x01,0x0e,0x01,0x07,0x02,0x01,
+ 0x91,0x01,0xe8,0x07,0x02,0x38,0x01,0xe5,0x19,0x7b,0xe7,0x63,0x01,0x77,0xe9,0x0d,
+ 0x09,0x09,0x09,0x09,0x09,0x02,0x06,0x09,0x09,0x05,0x03,0x0b,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x06,0x06,0xe6,0xe6,0x3d,0x94,0x02,0x04,0x04,0x01,0x3d,
+ 0x96,0x09,0xe5,0xe6,0x3e,0x01,0x06,0xe5,0x11,0xe5,0xe5,0x7f,0xe6,0x3e,0x01,0xe5,
+ 0x05,0x02,0x10,0x01,0xe5,0x7d,0xe8,0x3f,0x07,0x94,0xe6,0xe5,0x13,0xe6,0x07,0xe5,
+ 0x07,0xe5,0x06,0xe6,0x05,0xe7,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x09,0xe5,0x31,0x0c,0x01,0xe6,0x18,0x01,0x7f,0xe7,0x15,0x1d,
+ 0x09,0xe5,0xe5,0x1a,0x01,0x06,0x77,0x03,0xe5,0x12,0x0a,0x13,0x07,0xe6,0xe5,0xe5,
+ 0x20,0xe6,0x77,0x03,0x03,0x10,0x01,0x06,0x01,0x11,0x01,0xe5,0x05,0x01,0xe6,0xe6,
+ 0x1f,0x01,0xe5,0x71,0x05,0xe7,0x48,0xe5,0xe5,0x8b,0x04,0xe5,0xe6,0x10,0x01,0xe6,
+ 0x04,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x01,0x07,
+ 0x01,0x07,0x01,0x02,0x04,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0x04,0xe5,0xe5,0x4e,0x8f,
+ 0xe8,0x14,0x2c,0x18,0x80,0xe5,0x01,0xe5,0x44,0x06,0x24,0x6c,0xe5,0xe7,0x3d,0xe5,
+ 0x06,0xe7,0x0a,0x19,0x6b,0x01,0xe7,0x26,0x1b,0x06,0x22,0x03,0x61,0x02,0x08,0x01,
+ 0xe6,0xe5,0x0f,0x23,0xe5,0x03,0x0c,0xe5,0x02,0x04,0xe5,0x1a,0x39,0x10,0x20,0xe6,
+ 0xe6,0x0f,0x25,0x12,0x09,0x01,0x02,0x18,0x63,0x0b,0xe5,0x05,0x0a,0x13,0x25,0x02,
+ 0x22,0x6c,0xe5,0x01,0x05,0x37,0x14,0x1e,0x6d,0x02,0x44,0x2c,0x6c,0x03,0x09,0x68,
+ 0x62,0x09,0xe7,0x01,0x1b,0x23,0x05,0xe5,0xe5,0x02,0x22,0x6b,0xe8,0xe5,0x09,0x57,
+ 0x79,0xe8,0xe5,0x07,0x01,0x03,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0xb5,0x04,0xe5,
+ 0xe5,0x01,0x04,0xe5,0x12,0xe5,0x2d,0x8a,0x01,0x03,0xe7,0x03,0x0c,0x09,0x09,0x15,
+ 0xe5,0x01,0x01,0x04,0xe5,0x90,0x04,0x03,0x02,0x39,0x02,0x01,0x04,0xe5,0xe5,0x05,
+ 0xe5,0x88,0x01,0x02,0x01,0xe5,0x07,0x02,0x28,0x01,0x05,0x11,0x02,0x06,0x02,0x80,
+ 0xe5,0xe5,0xe5,0x01,0x06,0x02,0x28,0x01,0x01,0x09,0x09,0x02,0x01,0x04,0x02,0x01,
+ 0x7e,0x02,0xe9,0x33,0x01,0x07,0x01,0x09,0x91,0x03,0xe5,0x34,0x01,0x07,0x01,0x07,
+ 0x09,0x87,0x01,0xea,0x03,0xe5,0x01,0x02,0xcf,0x01,0x01,0xe6,0x04,0x04,0x45,0x8c,
+ 0xe6,0xe7,0x07,0x05,0x09,0x09,0x09,0x09,0x02,0x06,0x09,0x03,0xe5,0xe5,0x01,0x09,
+ 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x04,0xdb,0x02,0xe5,
+ 0xe6,0xdd,0xe8,0x4a,0x09,0x88,0xe5,0x01,0x48,0x03,0x09,0x87,0x01,0x01,0xe5,0x50,
+ 0x02,0x88,0xe5,0x01,0x13,0x01,0xe5,0x06,0xe6,0x06,0xe6,0x07,0xe5,0x07,0xe5,0x05,
+ 0xe7,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0a,
+ 0x46,0x0e,0x88,0x01,0x01,0x20,0x09,0x1d,0x95,0xe8,0x12,0x01,0x08,0x09,0xe5,0x1a,
+ 0x01,0x07,0x01,0x03,0x03,0x01,0x82,0x01,0xe6,0x12,0x01,0x0a,0x06,0x01,0xe5,0x19,
+ 0x01,0xe5,0x05,0x01,0x07,0x01,0x84,0xe6,0x4a,0xe5,0x07,0xe5,0x87,0xe5,0xe5,0x10,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe6,0xe5,0x51,0x13,0x78,0x02,0xe5,0x0a,
+ 0x09,0x36,0x16,0x15,0x62,0x01,0xe7,0x1d,0x52,0x6b,0xe5,0x01,0xe6,0x42,0x04,0x01,
+ 0x25,0x6e,0x01,0x43,0x05,0x02,0x24,0x6b,0x01,0x02,0xe5,0x11,0x31,0x2b,0x36,0x15,
+ 0x12,0x0b,0xe6,0xe6,0x4c,0x0e,0x14,0xe5,0x68,0xe6,0xe5,0xe5,0x70,0x61,0x0a,0x03,
+ 0x4c,0x0e,0x15,0x6d,0x02,0x01,0x6f,0x70,0x0a,0xd6,0xe5,0xde,0x02,0x46,0x09,0x07,
+ 0x82,0x03,0xe9,0xd9,0xe5,0x01,0xe6,0x01,0x01,0xd4,0x01,0x02,0x03,0x04,0xd4,0x07,
+ 0xe5,0x01,0xd8,0x02,0x01,0x01,0xe1,0xe5,0x01,0xd8,0x02,0x03,0xe5,0xdb,0xe5,0x02,
+ 0x02,0xdb,0xe5,0xe6,0xe5,0x4c,0x02,0x8d,0x01,0x50,0xe5,0x8c,0x01,0xe6,0x0d,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x0d,0xe6,0xe6,0x01,0xd8,0x03,0xe7,0xdd,0xe6,0xe5,0xe5,0x46,0x01,0x90,
+ 0x01,0x02,0xe5,0x48,0x01,0xe5,0x92,0x01,0xe3,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x08,0x01,0x49,0x01,0x92,0xe8,0x48,0x01,0x94,0x01,0xde,0xe5,0xe6,0xda,
+ 0x03,0xe7,0xdd,0xe5,0xe6,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,
+ 0x01,0xe6,0xe5,0x5b,0x81,0x02,0xe6,0x50,0x31,0x50,0x07,0xe5,0x01,0xe5,0xe5,0x6e,
+ 0x6e,0xe6,0x70,0x6c,0x01,0xe6,0x70,0x6c,0xe6,0xe5,0x12,0x5d,0x36,0x15,0x21,0xe6,
+ 0x70,0x6c,0x02,0xe5,0x70,0x6c,0x01,0xe6,0x4c,0x23,0x6e,0xe6,0x02,0x6d,0x6c,0x03,
+ 0x4d,0x91,0x02,0xe5,0xdb,0xe9,0x01,0xdb,0xe5,0x01,0xe6,0xd9,0xe6,0x01,0xe5,0x01,
+ 0x01,0xd4,0x01,0x05,0xe5,0x03,0xd4,0x04,0xe8,0x01,0xd8,0x02,0xe6,0xe5,0xdf,0xe6,
+ 0x01,0xd8,0x05,0xe6,0xdb,0x03,0xe5,0xdd,0xe5,0x01,0xde,0x01,0xe6,0xdd,0xe6,0xe6,
+ 0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x0d,0xe6,0x01,0x02,0xd8,0x03,0x01,0xe5,0xde,0xe5,0xe5,0xe5,
+ 0xd9,0x01,0xe6,0xe5,0xdd,0x01,0xe6,0xde,0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x08,0x01,0xdf,0x02,0xe1,0xe5,0xdd,0xe8,0xdd,0x01,0xe6,0x02,0xdb,0xe7,
+ 0xe5,0x09,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0xe6,0xe5,0x51,
+ 0x13,0x79,0x01,0xe5,0x14,0x4d,0x17,0x11,0x4e,0xe6,0x01,0x71,0x6c,0x01,0xe6,0x70,
+ 0x6c,0x01,0xe6,0x70,0x6c,0xe6,0xe5,0x12,0x31,0x2b,0x4a,0x15,0x0f,0x31,0x3f,0x6d,
+ 0xe7,0x70,0x68,0x03,0xe5,0xe6,0xe5,0x6e,0x6c,0xe8,0x70,0x6e,0x01,0x02,0xdf,0xe5,
+ 0x08,0xd2,0x01,0x01,0xe5,0xdf,0x01,0xe6,0xd9,0x01,0xe6,0xe5,0x01,0x01,0xd4,0x01,
+ 0x03,0x02,0x04,0xce,0xe5,0x03,0x05,0xe7,0xd3,0x06,0x02,0x03,0xd5,0x07,0xe5,0xe7,
+ 0xda,0x03,0x01,0xe5,0xdc,0xe9,0xdd,0x02,0xe5,0x08,0xd3,0x04,0x0a,0x01,0xd1,0xe5,
+ 0xe7,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe6,0xe6,0x01,0xd3,0x04,0x02,0x03,0xd5,0x08,
+ 0x01,0x01,0xe0,0x01,0xde,0xe5,0xe6,0xdf,0x01,0xe5,0x13,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x09,0xe5,0xdd,0x03,0xe0,0x01,0xe5,0xdc,0xe8,0xdf,0x01,0xdf,0xe5,0xe5,
+ 0x10,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0c,0xe6,0xdd,0xe9,0x50,
+ 0x33,0x56,0x01,0x02,0x01,0x03,0x2c,0x3e,0x6c,0xe5,0xe7,0x6f,0x6b,0x01,0xe5,0xe5,
+ 0x12,0x5d,0x6e,0xe7,0x08,0x1f,0x09,0x3c,0x4a,0x15,0x0a,0xe9,0x70,0x6c,0x02,0xe5,
+ 0x05,0x6a,0x6c,0xe6,0xe5,0x70,0x6e,0xe6,0x70,0x6d,0xe7,0x09,0x09,0x09,0xbf,0x01,
+ 0x01,0xde,0xe5,0xe6,0x26,0xba,0xdc,0x01,0x01,0xe6,0x01,0x01,0xd4,0x01,0x03,0xe7,
+ 0x03,0xcf,0xe5,0x02,0x04,0x02,0xe5,0xe6,0xd7,0x03,0x01,0xe6,0xe5,0x06,0x01,0xd0,
+ 0x02,0xe6,0xda,0x02,0xe5,0x01,0xdd,0xe6,0xe6,0xda,0xe5,0x02,0xe7,0x07,0xd3,0x01,
+ 0xe7,0x09,0x01,0xd5,0xe5,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x06,0xe9,0xd5,0x04,
+ 0x05,0xe5,0xd2,0x0a,0x02,0xe5,0xdf,0x01,0xdf,0xe8,0xdd,0x01,0xe5,0x14,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0xd8,0x05,0xe7,0xde,0xe5,0xe6,0xdc,0x02,
+ 0xe5,0x02,0x08,0xd3,0x01,0x32,0xab,0xe6,0xe5,0x10,0x01,0x02,0x04,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x0a,0x02,0xe5,0xde,0x02,0xe5,0x64,0x15,0x13,0x4c,0x02,0xe6,0x70,0x6d,
+ 0xe5,0xe6,0x6f,0x6b,0x02,0x01,0x13,0x5d,0x64,0x07,0xe5,0xe7,0x43,0x2b,0x61,0x09,
+ 0xe5,0x02,0x25,0x4b,0x6e,0x01,0x06,0x20,0x49,0x6d,0xe5,0xe5,0x70,0x6c,0x03,0x03,
+ 0x6d,0x6e,0xe6,0xe1,0xdc,0x01,0xe5,0x01,0xe3,0xe7,0xd9,0x03,0xe6,0x01,0x01,0xd4,
+ 0x01,0x02,0x01,0x01,0x04,0xd4,0x06,0x01,0xd4,0xe5,0x04,0x02,0x01,0xe6,0xdc,0x01,
+ 0x02,0x02,0xd8,0x03,0x02,0x01,0xdb,0x01,0xe5,0xe5,0xdd,0xe5,0x01,0xdd,0x01,0xe7,
+ 0xdf,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x02,0xd8,0x04,0xe6,0xdd,0x02,0xe5,
+ 0xdd,0x01,0xe6,0xdd,0xe5,0x01,0xe5,0xde,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x06,0x01,0x01,0xde,0x01,0x01,0xe3,0xe6,0xdc,0xe5,0x01,0xdf,0xe7,0x3b,0x10,
+ 0x92,0xe6,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x0d,
+ 0xe5,0x50,0x34,0x58,0x02,0xe5,0x50,0x8a,0xe9,0xe5,0x02,0x5f,0x0a,0xe5,0x09,0x12,
+ 0x51,0xe5,0x03,0x49,0x22,0x14,0x13,0x42,0xe5,0x01,0xe6,0x01,0x6d,0x6f,0xe6,0x2b,
+ 0x24,0x1e,0x52,0xe5,0x0b,0x0a,0xe5,0x01,0xe6,0x23,0x05,0x01,0x3f,0x03,0x6c,0xe5,
+ 0xe6,0x26,0x06,0x42,0x6c,0x01,0xe7,0x6f,0x6d,0xe7,0x70,0x6d,0x01,0xe5,0x30,0x3d,
+ 0x5f,0x0e,0x01,0x01,0x2d,0x97,0x08,0xe5,0x0d,0xe5,0x01,0x09,0x23,0x44,0x52,0x08,
+ 0x11,0xe6,0x02,0x0b,0xe5,0x01,0x06,0x06,0xe7,0x07,0xe5,0x05,0xe7,0x05,0xe7,0x05,
+ 0xe7,0xe5,0x05,0xe5,0x08,0x08,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0x02,0xe6,0x0d,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x02,0x01,
+ 0x01,0x08,0xe5,0x0d,0x02,0x01,0x0b,0x09,0x09,0x09,0x07,0x01,0x01,0xe5,0x05,0x09,
+ 0x09,0x02,0x06,0x09,0x0d,0x02,0xe5,0x0f,0x08,0x13,0x09,0x1d,0x09,0x04,0x04,0x08,
+ 0x02,0x04,0x04,0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x02,0x14,0x41,
+ 0x87,0x01,0xe6,0x18,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x13,0x0b,0x09,0x04,0x04,
+ 0x09,0x04,0x04,0x02,0x06,0x09,0x09,0x09,0x09,0x0e,0x01,0x01,0x0d,0xe5,0x07,0xe6,
+ 0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0xe8,0x02,0x05,0x03,0x09,0x01,0x04,0x02,0x01,
+ 0x07,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x07,0x01,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x14,0x0e,0x09,0x09,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,
+ 0x09,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x0f,0x0e,0x09,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x01,0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe6,0x47,
+ 0x11,0x76,0x0c,0x01,0x01,0x0e,0x05,0x03,0x05,0x03,0x09,0x05,0x03,0x09,0x09,0x09,
+ 0x09,0x09,0x06,0x01,0x02,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,
+ 0xe8,0x0f,0x13,0x1d,0x09,0x24,0x70,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0x01,0xe5,0x46,
+ 0x96,0x02,0xe5,0x70,0x6e,0x01,0x22,0x1d,0x09,0x13,0x11,0xe5,0x67,0x06,0xe5,0x06,
+ 0x06,0x06,0x02,0x06,0x02,0x06,0x16,0x06,0x02,0x13,0x06,0x79,0xe5,0xe5,0x3a,0x1d,
+ 0x33,0x1d,0x09,0x2a,0xe6,0x06,0x05,0x08,0xe5,0x07,0xe5,0x07,0x14,0x08,0xe5,0x12,
+ 0x08,0x0a,0x65,0x06,0x03,0x71,0x66,0x05,0xe5,0xe6,0xdd,0xe5,0xe6,0x0c,0xe5,0x04,
+ 0xe8,0x04,0xe8,0x04,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04,
+ 0xe6,0x06,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x01,0xe6,0x0c,
+ 0xe6,0x05,0xe7,0x05,0xe7,0x05,0x01,0xe5,0x08,0x07,0xe6,0x05,0xe7,0x08,0x07,0xe6,
+ 0x05,0x02,0x07,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x08,0xe5,0x07,0xe5,0x0e,
+ 0xe5,0xe5,0x33,0x2d,0x0e,0x10,0x13,0x48,0x02,0x11,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x01,0x0d,0x03,0x05,0x03,0x01,0x0d,0x03,0x01,0x03,0x07,0x09,0x09,0x09,0x09,
+ 0x03,0x05,0x09,0x09,0x11,0x13,0x01,0xe5,0x0a,0x06,0x09,0x09,0x04,0x01,0x02,0x01,
+ 0x03,0x07,0x05,0x09,0x01,0x03,0x07,0x0e,0xe5,0x02,0x06,0xe5,0x02,0x04,0x04,0x01,
+ 0x07,0x04,0x04,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x02,0x04,0x04,0x06,
+ 0x01,0x03,0xe5,0xe5,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,
diff --git a/u-boot/board/esd/du440/Makefile b/u-boot/board/esd/du440/Makefile
new file mode 100644
index 0000000..06824c7
--- /dev/null
+++ b/u-boot/board/esd/du440/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/du440/config.mk b/u-boot/board/esd/du440/config.mk
new file mode 100644
index 0000000..24f74e1
--- /dev/null
+++ b/u-boot/board/esd/du440/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/esd/du440/du440.c b/u-boot/board/esd/du440/du440.c
new file mode 100644
index 0000000..426321e
--- /dev/null
+++ b/u-boot/board/esd/du440/du440.c
@@ -0,0 +1,897 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+	/*
+	 * Setup the GPIO pins
+	 */
+	out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_OSRL, 0x50055400);
+	out_be32((void*)GPIO0_OSRH, 0x55005000);
+	out_be32((void*)GPIO0_TSRL, 0x50055400);
+	out_be32((void*)GPIO0_TSRH, 0x55005000);
+	out_be32((void*)GPIO0_ISR1L, 0x50000000);
+	out_be32((void*)GPIO0_ISR1H, 0x00000000);
+	out_be32((void*)GPIO0_ISR2L, 0x00000000);
+	out_be32((void*)GPIO0_ISR2H, 0x00000000);
+	out_be32((void*)GPIO0_ISR3L, 0x00000000);
+	out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+	out_be32((void*)GPIO1_OR, 0x00000000);
+	out_be32((void*)GPIO1_TCR, 0xc2000000 |
+		 CONFIG_SYS_GPIO1_IORSTN |
+		 CONFIG_SYS_GPIO1_IORST2N |
+		 CONFIG_SYS_GPIO1_LEDUSR1 |
+		 CONFIG_SYS_GPIO1_LEDUSR2 |
+		 CONFIG_SYS_GPIO1_LEDPOST |
+		 CONFIG_SYS_GPIO1_LEDDU);
+	out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
+	out_be32((void*)GPIO1_OSRL, 0x0c280000);
+	out_be32((void*)GPIO1_OSRH, 0x00000000);
+	out_be32((void*)GPIO1_TSRL, 0xcc000000);
+	out_be32((void*)GPIO1_TSRH, 0x00000000);
+	out_be32((void*)GPIO1_ISR1L, 0x00005550);
+	out_be32((void*)GPIO1_ISR1H, 0x00000000);
+	out_be32((void*)GPIO1_ISR2L, 0x00050000);
+	out_be32((void*)GPIO1_ISR2H, 0x00000000);
+	out_be32((void*)GPIO1_ISR3L, 0x01400000);
+	out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * UIC1:
+	 *  bit30: ext. Irq 1: PLD : int 32+30
+	 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xfffffffd);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * UIC2
+	 *  bit3: ext. Irq 2: DCF77 : int 64+3
+	 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+	/* setup EMAC bridge interface */
+	if (board_revision() == 0) {
+		/* 1 x MII */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+			SDR0_PFC1_SELECT_CONFIG_1_2;
+		sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+			SDR0_PFC2_SELECT_CONFIG_1_2;
+	} else {
+		/* 2 x SMII */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+			SDR0_PFC1_SELECT_CONFIG_6;
+		sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+			SDR0_PFC2_SELECT_CONFIG_6;
+	}
+
+	/* enable 2nd IIC */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* PCI arbiter enabled */
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
+		(0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val = 0;
+	u32 reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_srst0, sdr0_srst1;
+	int i, j;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+	/*
+	 * USB suff...
+	 */
+	/* SDR Setting */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_USB0, usb2d0cr);
+	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+	/* An 8-bit/60MHz interface is the only possible alternative
+	   when connecting the Device to the PHY */
+	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+	/* To enable the USB 2.0 Device function through the UTMI interface */
+	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+	mtsdr(SDR0_USB0, usb2d0cr);
+	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	/*
+	 * Take USB out of reset:
+	 * -Initial status = all cores are in reset
+	 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+	 * -wait 1 ms
+	 * -deassert reset to PHY
+	 * -wait 1 ms
+	 * -deassert  reset to HOST
+	 * -wait 4 ms
+	 * -deassert all other resets
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |		\
+			SDR0_SRST1_P4OPB0 |		\
+			SDR0_SRST1_OPBA2 |		\
+			SDR0_SRST1_PLB42OPB1 |		\
+			SDR0_SRST1_OPB2PLB40);
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+	udelay(1000);
+
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+	udelay(1000);
+
+	mfsdr(SDR0_SRST0, sdr0_srst0);
+	sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+	mtsdr(SDR0_SRST0, sdr0_srst0);
+	udelay(4000);
+
+	/* finally all the other resets */
+	mtsdr(SDR0_SRST1, 0x00000000);
+	mtsdr(SDR0_SRST0, 0x00000000);
+
+	printf("USB:   Host(int phy)\n");
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+	/*
+	 * release IO-RST#
+	 * We have to wait at least 560ms until we may call usbhub_init
+	 */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
+		 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
+
+	/*
+	 * flash USR1/2 LEDs (600ms)
+	 * This results in the necessary delay from IORST# until
+	 * calling usbhub_init will succeed
+	 */
+	for (j = 0; j < 3; j++) {
+		out_be32((void*)GPIO1_OR,
+			 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
+			 CONFIG_SYS_GPIO1_LEDUSR1);
+
+		for (i = 0; i < 100; i++)
+			udelay(1000);
+
+		out_be32((void*)GPIO1_OR,
+			 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
+			 CONFIG_SYS_GPIO1_LEDUSR2);
+
+		for (i = 0; i < 100; i++)
+			udelay(1000);
+	}
+
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+		 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
+
+	if (usbhub_init())
+		du440_post_errors++;
+
+	if (dvi_init())
+		du440_post_errors++;
+
+	return 0;
+}
+
+int pld_revision(void)
+{
+	out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
+	return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+	int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
+			  >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
+
+	return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+		((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#if defined(CONFIG_SHOW_ACTIVITY)
+void board_show_activity (ulong timestamp)
+{
+	if ((timestamp % 100) == 0)
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+	if (board_revision() == 0)
+		return devnum;
+
+	return devnum + 1;
+}
+
+int checkboard(void)
+{
+	char serno[32];
+
+	puts("Board: DU440");
+
+	if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
+		puts(", serial# ");
+		puts(serno);
+	}
+
+	printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+	       board_revision(), pld_revision());
+	return (0);
+}
+
+int last_stage_init(void)
+{
+	int e, i;
+
+	/* everyting is ok: turn on POST-LED */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
+
+	/* slowly blink on errors and finally keep LED off */
+	for (e = 0; e < du440_post_errors; e++) {
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
+
+		for (i = 0; i < 500; i++)
+			udelay(1000);
+
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
+
+		for (i = 0; i < 500; i++)
+			udelay(1000);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+	unsigned int oldbus;
+	uchar u[2];
+	int mv;
+
+	oldbus = I2C_GET_BUS();
+	I2C_SET_BUS(1);
+
+	if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+		I2C_SET_BUS(oldbus);
+		return -1;
+	}
+
+	mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+	I2C_SET_BUS(oldbus);
+	return mv;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int mv;
+	u32 pin, pinold;
+	unsigned long long t1, t2;
+	bd_t *bd = gd->bd;
+
+	printf("DCF77: ");
+	mv = dcf77_status();
+	if (mv > 0)
+		printf("signal=%d mV\n", mv);
+	else
+		printf("ERROR - no signal\n");
+
+	t1 = t2 = 0;
+	pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
+	while (!ctrlc()) {
+		pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
+		if (pin && !pinold) { /* bit start */
+			t1 = get_ticks();
+			if (t2 && ((unsigned int)(t1 - t2) /
+				   (bd->bi_procfreq / 1000) >= 1800))
+				printf("Start of minute\n");
+
+			t2 = t1;
+		}
+		if (t1 && !pin && pinold) { /* bit end */
+			printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+			       (bd->bi_procfreq / 1000));
+		}
+		pinold = pin;
+	}
+
+	printf("Abort\n");
+	return 0;
+}
+U_BOOT_CMD(
+	dcf77, 1, 1, do_dcf77,
+	"Check DCF77 receiver",
+	""
+);
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+	int reg;
+	int ret = 0;
+	unsigned int oldbus;
+	uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+		     0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+		     0x32};
+	uchar stcd;
+
+	printf("Hub:   ");
+
+	oldbus = I2C_GET_BUS();
+	I2C_SET_BUS(1);
+
+	for (reg = 0; reg < sizeof(u); reg++)
+		if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+			ret = -1;
+			break;
+		}
+
+	if (ret == 0) {
+		stcd = 0x03;
+		if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+			ret = -1;
+	}
+
+	if (ret == 0)
+		printf("initialized\n");
+	else
+		printf("failed - cannot initialize USB hub\n");
+
+	I2C_SET_BUS(oldbus);
+	return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	usbhub_init();
+	return 0;
+}
+U_BOOT_CMD(
+	hubinit, 1, 1, do_hubinit,
+	"Initialize USB hub",
+	""
+);
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+		       unsigned offset,
+		       uchar *buffer,
+		       unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 1);
+#endif
+	/*
+	 * Write data until done or would cross a write page boundary.
+	 * We must write the address again when changing pages
+	 * because the address counter only increments within a page.
+	 */
+
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen = 2;
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+		/*
+		 * For a FRAM device there is no limit on the number of the
+		 * bytes that can be ccessed with the single read or write
+		 * operation.
+		 */
+#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define	BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+		maxlen = BOOT_EEPROM_PAGE_SIZE -
+			BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+		maxlen = 0x100 - blk_off;
+#endif
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+			rcode = 1;
+
+		buffer += len;
+		offset += len;
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+	}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 0);
+#endif
+	return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong sdsdp[4];
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "533")) {
+			printf("Bootstrapping for 533MHz\n");
+			sdsdp[0] = 0x87788252;
+			/* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+			sdsdp[1] = 0x095fa030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "533-66")) {
+			printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+			sdsdp[0] = 0x87788252;
+			/* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+			sdsdp[1] = 0x0957a030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "667")) {
+			printf("Bootstrapping for 667MHz\n");
+			sdsdp[0] = 0x8778a256;
+			/* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+			sdsdp[1] = 0x0947a030;
+			/* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+			 * -> not working when overclocking 533MHz chips
+			 * -> untested on 667MHz chips */
+			/* sdsdp[1]=0x095fa030; */
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "667-166")) {
+			printf("Bootstrapping for 667-166MHz\n");
+			sdsdp[0] = 0x8778a252;
+			sdsdp[1] = 0x09d7a030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		}
+	} else {
+		printf("Bootstrapping for 533MHz (default)\n");
+		sdsdp[0] = 0x87788252;
+		/* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+		sdsdp[1] = 0x095fa030;
+		sdsdp[2] = 0x40082350;
+		sdsdp[3] = 0x0d050000;
+	}
+
+	printf("Writing boot EEPROM ...\n");
+	if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+			      0, (uchar*)sdsdp, 16) != 0)
+		printf("boot_eeprom_write failed\n");
+	else
+		printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	sbe, 2, 0, do_setup_boot_eeprom,
+	"setup boot eeprom",
+	""
+);
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/*
+ * Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *                      0: disable write
+ *                      1: enable write
+ * Returns:            -1: wrong device address
+ *                      0: dis-/en- able done
+ *                    0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
+		return -1;
+	else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void*)GPIO0_OR) &
+				       CONFIG_SYS_GPIO0_EP_EEP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0)
+			puts ("Query of write access state failed.\n");
+		else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0)
+			puts ("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+	int rc = -1; /* not for us */
+	u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
+
+	/* check for PLD interrupt */
+	if (status & PWR_INT_FLAG) {
+		/* reset this int */
+		out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
+		rc = 0;
+		got_pldirq = 1; /* trigger backend */
+	}
+
+	return rc;
+}
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	got_pldirq = 0;
+
+	/* clear any pending interrupt */
+	out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
+
+	irq_install_handler(CPLD_IRQ,
+			    (interrupt_handler_t *)pld_interrupt, 0);
+
+	printf("Waiting ...\n");
+	while(!got_pldirq) {
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			break;
+		}
+	}
+	if (got_pldirq) {
+		printf("Got interrupt!\n");
+		printf("Power %sready!\n",
+		       in_8((void *)CONFIG_SYS_CPLD_BASE) &
+		       PWR_RDY ? "":"NOT ");
+	}
+
+	irq_free_handler(CPLD_IRQ);
+	return 0;
+}
+U_BOOT_CMD(
+	wpi,	1,	1,	do_waitpwrirq,
+	"Wait for power change interrupt",
+	""
+);
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+	int i;
+	int ret = 0;
+	unsigned int oldbus;
+	uchar u[] = {0x08, 0x34,
+		     0x09, 0x20,
+		     0x0a, 0x90,
+		     0x0c, 0x89,
+		     0x08, 0x35};
+
+	printf("DVI:   ");
+
+	oldbus = I2C_GET_BUS();
+	I2C_SET_BUS(0);
+
+	for (i = 0; i < sizeof(u); i += 2)
+		if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+			ret = -1;
+			break;
+		}
+
+	if (ret == 0)
+		printf("initialized\n");
+	else
+		printf("failed - cannot initialize DVI transmitter\n");
+
+	I2C_SET_BUS(oldbus);
+	return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	dvi_init();
+	return 0;
+}
+U_BOOT_CMD(
+	dviinit, 1, 1, do_dviinit,
+	"Initialize DVI Panellink transmitter",
+	""
+);
+
+/*
+ * TODO: 'time' command might be useful for others as well.
+ *       Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long long start, end;
+	char c, cmd[CONFIG_SYS_CBSIZE];
+	char *p, *d = cmd;
+	int ret, i;
+	ulong us;
+
+	for (i = 1; i < argc; i++) {
+		p = argv[i];
+
+		if (i > 1)
+			*d++ = ' ';
+
+		while ((c = *p++) != '\0') {
+			*d++ = c;
+		}
+	}
+	*d = '\0';
+
+	start = get_ticks();
+	ret = run_command (cmd, 0);
+	end = get_ticks();
+
+	printf("ticks=%ld\n", (ulong)(end - start));
+	us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+	printf("usec=%ld\n", us);
+
+	return ret;
+}
+U_BOOT_CMD(
+	time,	CONFIG_SYS_MAXARGS,	1,	do_time,
+	"run command and output execution time",
+	""
+);
+
+extern void video_hw_rectfill (
+	unsigned int bpp,		/* bytes per pixel */
+	unsigned int dst_x,		/* dest pos x */
+	unsigned int dst_y,		/* dest pos y */
+	unsigned int dim_x,		/* frame width */
+	unsigned int dim_y,		/* frame height */
+	unsigned int color		/* fill color */
+	);
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+	if (r == 0 || r == 1 || r == -1)
+		r = rprime; /* keep from getting stuck */
+
+	r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+	Y = (r >> 16) % max; /* choose upper bits and reduce */
+	return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int color;
+	unsigned int x, y, dx, dy;
+
+	while (!ctrlc()) {
+		x = prng(1280 - 1);
+		y = prng(1024 - 1);
+		dx = prng(1280- x - 1);
+		dy = prng(1024 - y - 1);
+		color = prng(0x10000);
+		video_hw_rectfill(2, x, y, dx, dy, color);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	gfxdemo,	CONFIG_SYS_MAXARGS,	1,	do_gfxdemo,
+	"demo",
+	""
+);
diff --git a/u-boot/board/esd/du440/du440.h b/u-boot/board/esd/du440/du440.h
new file mode 100644
index 0000000..37697ec
--- /dev/null
+++ b/u-boot/board/esd/du440/du440.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDR0_USB0		0x0320     /* USB Control Register */
+
+#define CONFIG_SYS_GPIO0_EP_EEP	(0x80000000 >> 23)       /* GPIO0_23 */
+#define CONFIG_SYS_GPIO1_DCF77		(0x80000000 >> (42-32))  /* GPIO1_42 */
+
+#define CONFIG_SYS_GPIO1_IORSTN	(0x80000000 >> (55-32))  /* GPIO1_55 */
+#define CONFIG_SYS_GPIO1_IORST2N	(0x80000000 >> (47-32))  /* GPIO1_47 */
+
+#define CONFIG_SYS_GPIO1_HWVER_MASK	0x000000f0 /* GPIO1_56-59 */
+#define CONFIG_SYS_GPIO1_HWVER_SHIFT	4
+#define CONFIG_SYS_GPIO1_LEDUSR1	0x00000008 /* GPIO1_60 */
+#define CONFIG_SYS_GPIO1_LEDUSR2	0x00000004 /* GPIO1_61 */
+#define CONFIG_SYS_GPIO1_LEDPOST	0x00000002 /* GPIO1_62 */
+#define CONFIG_SYS_GPIO1_LEDDU		0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK	0x0f
+#define PWR_INT_FLAG		0x80
+#define PWR_RDY			0x10
+
+#define CPLD_IRQ		(32+30)
diff --git a/u-boot/board/esd/du440/init.S b/u-boot/board/esd/du440/init.S
new file mode 100644
index 0000000..88565d9
--- /dev/null
+++ b/u-boot/board/esd/du440/init.S
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M,  CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+	/* TLB-entry for PCI IO */
+	tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
+
+	/* TLB-entries for EBC:	 CPLD, DUMEM, DUIO */
+	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for NAND */
+	tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
+
+	/* TLB-entry PCI registers */
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	tlbtab_end
diff --git a/u-boot/board/esd/hh405/Makefile b/u-boot/board/esd/hh405/Makefile
new file mode 100644
index 0000000..090005f
--- /dev/null
+++ b/u-boot/board/esd/hh405/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/hh405/flash.c b/u-boot/board/esd/hh405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/hh405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/hh405/fpgadata.c b/u-boot/board/esd/hh405/fpgadata.c
new file mode 100644
index 0000000..64bca46
--- /dev/null
+++ b/u-boot/board/esd/hh405/fpgadata.c
@@ -0,0 +1,2517 @@
+  0x1f,0x8b,0x08,0x08,0x7a,0x8e,0xc6,0x43,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f,
+  0x31,0x5f,0x30,0x36,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x7f,0x7c,0x14,0x55,0x9a,
+  0x2f,0x8e,0x3f,0x75,0xaa,0x12,0x4e,0xba,0x3a,0xe9,0x22,0x09,0x4e,0x54,0xc4,0x4a,
+  0x27,0x30,0x4d,0xec,0x84,0xa6,0x83,0x21,0x42,0x48,0x2a,0x9d,0xe8,0x44,0x40,0xe9,
+  0x71,0xdc,0x59,0x76,0xae,0x77,0xb6,0x65,0x98,0xbd,0x99,0xb9,0xe8,0x46,0xc7,0xbb,
+  0x97,0xf1,0xce,0x8f,0x93,0x4e,0x80,0x4e,0x82,0xd0,0x20,0x33,0x46,0x87,0x71,0x9b,
+  0x10,0x35,0x2a,0x33,0xdb,0x04,0x94,0xf0,0x63,0xb0,0x12,0xa3,0x36,0x10,0x20,0x32,
+  0xdc,0x19,0x54,0x46,0x1b,0x8c,0x4c,0xd4,0xe8,0x04,0x44,0x4d,0xf8,0xf9,0x7d,0x4e,
+  0x75,0xa7,0xbb,0x1a,0x77,0xf7,0xce,0xfd,0xdc,0xd7,0xf7,0xf3,0xda,0xd7,0xeb,0x73,
+  0xb3,0x7f,0xec,0x99,0xea,0x43,0x59,0x75,0xea,0x9c,0xe7,0x79,0x3f,0xbf,0xde,0x0f,
+  0x64,0xd8,0x46,0x63,0xff,0x07,0x20,0xdc,0x0f,0xb6,0xfa,0xfa,0x39,0xae,0x5b,0xff,
+  0x7e,0xf6,0xdf,0xbb,0xca,0x4a,0x1e,0xfc,0xde,0x72,0x58,0x06,0xb2,0xfb,0x47,0xb7,
+  0xba,0xbe,0xff,0xc8,0x43,0xb3,0xe7,0xcc,0x81,0xef,0xe1,0xff,0x72,0xb9,0xca,0x66,
+  0xb9,0x66,0xcf,0x9a,0xed,0x86,0xe5,0x90,0x31,0xbb,0x7c,0xde,0xec,0x39,0xf3,0x4a,
+  0x6f,0x85,0xef,0x83,0x50,0xda,0x79,0x15,0xff,0x5e,0x78,0xf2,0x6f,0xfe,0xc1,0x05,
+  0x4c,0x00,0x80,0x49,0x2e,0xc1,0xc7,0xff,0xbf,0xec,0x12,0x54,0x01,0x58,0x55,0xb1,
+  0x0b,0x74,0xfe,0xbf,0x21,0xfe,0x7b,0x86,0x0b,0x54,0xf3,0xff,0x16,0x5c,0xa0,0x81,
+  0x17,0xb4,0xb5,0x6a,0x36,0xfc,0x15,0x7f,0x92,0xc4,0x26,0x86,0x7f,0xd5,0x7c,0x48,
+  0xcc,0xbf,0x7a,0x90,0xfd,0x9b,0x93,0x92,0x7f,0x55,0xe7,0x42,0xf1,0x91,0x4a,0x5c,
+  0xff,0xeb,0xe9,0x42,0x2d,0x4c,0xdc,0xf5,0xbd,0xb7,0xff,0x9a,0xfb,0xcf,0xff,0x62,
+  0xe2,0xfe,0xff,0xbb,0xf3,0x41,0xf9,0x2b,0xa6,0xe3,0xfb,0x4e,0x0c,0xde,0x53,0x04,
+  0x1f,0xe4,0xc1,0x75,0x90,0xc6,0x80,0x0f,0xd2,0x41,0xf8,0x57,0x06,0xf3,0xfb,0x27,
+  0xe6,0xeb,0x8d,0xfb,0xe0,0x08,0x2b,0x55,0xad,0x11,0xd1,0x0d,0xef,0xe5,0x57,0x45,
+  0x96,0x9c,0xcb,0xd9,0xd7,0x7c,0xf5,0x7b,0x73,0x23,0xb6,0x73,0x62,0x39,0x3b,0x09,
+  0x3f,0x1a,0xb5,0x8e,0xe5,0x8c,0x4a,0x0d,0x13,0xf3,0xe9,0x08,0x6d,0x65,0xee,0x7c,
+  0x1a,0x90,0xed,0x70,0x48,0x29,0x19,0x92,0x1b,0x49,0xd1,0xd2,0x3d,0xd9,0x25,0x47,
+  0x6c,0xfb,0x48,0x97,0x16,0x90,0xca,0x22,0x96,0x1e,0x31,0x2c,0x4d,0xac,0x62,0x44,
+  0x5a,0xbb,0xa5,0x55,0x98,0xa1,0x65,0x30,0xbb,0x0f,0x1e,0x17,0x9c,0xda,0x8d,0x2e,
+  0xb2,0x56,0xda,0xa1,0x3a,0x41,0xce,0x25,0x54,0xd9,0x20,0x86,0x74,0xea,0x22,0xe7,
+  0x84,0xc4,0xfd,0xa5,0x6d,0xe9,0xad,0xcc,0xae,0x65,0x04,0x48,0x3e,0x6b,0xcb,0x2b,
+  0xd1,0x64,0xd6,0xba,0x0d,0xf6,0x92,0x12,0x62,0x09,0xf6,0x75,0x41,0x06,0xfb,0x07,
+  0xdd,0x12,0xf6,0x8c,0x4a,0xbe,0xf8,0xfc,0xea,0x29,0x2b,0x20,0xd2,0x38,0x67,0x4e,
+  0x71,0xab,0x28,0xc2,0xdb,0x5a,0xa5,0xbe,0x64,0x8e,0xfc,0x5b,0xed,0x62,0xb0,0x64,
+  0xb0,0x26,0x5c,0x9a,0x05,0xdf,0x09,0xd9,0x7b,0xad,0xe1,0x82,0x41,0x98,0xb8,0x7f,
+  0x48,0xd8,0x0c,0x97,0x68,0x15,0xcb,0xd2,0x73,0xba,0xe1,0x8a,0x50,0xa5,0x2f,0x89,
+  0x36,0xd5,0xc3,0x05,0xa8,0xd4,0xd7,0x87,0x0b,0x46,0xd8,0x85,0x8c,0xaa,0xb3,0xb6,
+  0x51,0xb1,0x0b,0x26,0xee,0xdf,0xaf,0x6c,0x83,0x71,0xbf,0xdb,0x63,0x63,0xe2,0x29,
+  0x38,0xa8,0xb9,0xf5,0x69,0x3b,0x73,0xb6,0xd1,0x43,0xe0,0xde,0x60,0xdd,0x29,0x3a,
+  0xe1,0x10,0x2b,0xd3,0x97,0x84,0x6b,0x46,0x41,0x8d,0xcf,0x3f,0x91,0x56,0x21,0x6c,
+  0xd7,0xec,0x63,0x8b,0x24,0x32,0xcc,0x5a,0xc1,0x1d,0x99,0xda,0x49,0x9c,0xd0,0x26,
+  0xd9,0x19,0x2d,0xc7,0xc1,0x3b,0x7e,0xbb,0x2e,0x87,0xc9,0x17,0xb8,0xfb,0x27,0xde,
+  0x77,0xb1,0xb5,0x5b,0xdb,0x16,0x92,0x67,0xa4,0xbf,0xaa,0x36,0x0a,0x85,0xa1,0x0c,
+  0x17,0x59,0x0d,0x1b,0x24,0x9f,0x6e,0x71,0x10,0x02,0xcf,0xd7,0xe2,0x7c,0x17,0x19,
+  0xc3,0xb3,0x12,0xfb,0x1b,0x85,0xef,0xb2,0x97,0x59,0xf1,0x29,0xd9,0x97,0x7e,0x4c,
+  0x12,0x98,0x1a,0xa5,0x27,0x48,0xb6,0xba,0x69,0x63,0x7e,0xd4,0x52,0x8f,0x83,0x5d,
+  0x41,0x21,0x2a,0xaf,0xd4,0xae,0x24,0xee,0x5f,0x07,0x8b,0xb5,0x6e,0xa8,0x60,0xb6,
+  0x7c,0x51,0xef,0xeb,0x85,0x39,0x8a,0x1c,0x16,0x9b,0xc9,0x9b,0x10,0xd6,0x4a,0x94,
+  0x36,0x20,0xef,0x87,0x82,0xba,0xcd,0x25,0x1e,0x23,0x13,0xfb,0x41,0xbb,0x69,0xdf,
+  0xd0,0x17,0x50,0xaa,0xdb,0xb6,0x88,0x83,0xda,0x65,0xe5,0x95,0xda,0x59,0x1b,0xc4,
+  0xf3,0xf0,0x3c,0x54,0xd5,0x66,0x0e,0x0a,0xe7,0x16,0x1f,0x82,0xf9,0xfd,0xeb,0xc3,
+  0xe2,0x60,0xfa,0xc4,0xfa,0x50,0x69,0x1b,0xf4,0x41,0xf7,0x54,0x1b,0x2b,0x50,0xe1,
+  0x22,0x71,0x33,0x67,0x38,0xc7,0x09,0x17,0xc1,0xad,0x5b,0x43,0xe2,0xc8,0xe4,0xcf,
+  0x04,0x1c,0x84,0xc5,0x8f,0x94,0x89,0xf5,0x8f,0xe4,0x6d,0x66,0xab,0xe1,0xd6,0x81,
+  0x2c,0x8d,0x04,0x95,0x1d,0xe9,0x2a,0xff,0xfa,0x79,0xb0,0x1f,0x1c,0x3a,0xf5,0x91,
+  0x93,0xf0,0x12,0xb9,0x55,0xa7,0x0d,0xe4,0x5c,0xe2,0xfb,0xaa,0x30,0x0d,0x1e,0x63,
+  0xf9,0x2e,0x39,0x42,0x1e,0xa7,0xcf,0xb1,0xfc,0x10,0x5d,0x49,0x9e,0x86,0x57,0x58,
+  0x7e,0x14,0x07,0xef,0xc2,0xef,0x9a,0xbf,0x7e,0x9a,0xae,0xcc,0x8e,0x26,0xd6,0xbf,
+  0x5e,0x5a,0x0b,0x4d,0x9a,0x53,0xb7,0xe4,0x2d,0x4b,0x63,0x3b,0x74,0x5c,0x9f,0x72,
+  0x92,0xa5,0xed,0x08,0x3a,0x86,0xe8,0x6d,0xf0,0xa9,0xb6,0x7d,0xe3,0x0c,0x1f,0xfe,
+  0x17,0x8f,0x25,0xf6,0xe7,0xf0,0x94,0x7a,0xfa,0x3a,0xb8,0x99,0x6d,0x79,0xd3,0x1e,
+  0xeb,0x47,0x1d,0xdd,0x5d,0xd6,0x17,0xe4,0x2e,0xdc,0x0f,0x6e,0xd6,0x15,0x12,0x87,
+  0xe1,0x0a,0xcc,0x60,0xce,0x50,0xc1,0x85,0xc4,0xf3,0xd4,0x55,0x87,0xc8,0x98,0x5a,
+  0xa6,0xd8,0x98,0xff,0x14,0x8c,0x41,0x25,0xe0,0xc6,0x88,0xc2,0xa8,0x50,0x81,0x83,
+  0x9c,0x51,0x35,0x76,0xa5,0xe6,0x18,0x4c,0xdc,0x9f,0x2a,0xcf,0x06,0x0e,0x40,0x91,
+  0x36,0x29,0x98,0xf3,0x0c,0x6c,0xa7,0x2e,0xcd,0xaa,0x88,0x85,0x30,0x0e,0x6e,0xcd,
+  0x1a,0x14,0x87,0xf2,0x7a,0x83,0xc6,0xa0,0x2f,0xf1,0x3c,0x4c,0xfa,0x07,0x68,0xd1,
+  0x7e,0x78,0x42,0xde,0x44,0x9e,0x81,0xdd,0x60,0xd7,0xe8,0x26,0x9c,0xbf,0x1b,0x88,
+  0x46,0xdb,0xed,0x1f,0x40,0x8b,0x5e,0xa4,0xd1,0x20,0x89,0x26,0xc4,0x42,0x79,0x9a,
+  0x04,0x2d,0xaf,0xe3,0x26,0x09,0x6a,0xcb,0xa5,0x27,0xe1,0x96,0x5a,0x3a,0xe8,0x9f,
+  0xa3,0xfd,0x0e,0x44,0x6d,0xe6,0x31,0x72,0x3e,0xd4,0xa2,0xd9,0xb5,0xfa,0xa0,0xfd,
+  0xf5,0xc4,0x7e,0x50,0x73,0x25,0xad,0x05,0x1c,0xda,0x8d,0x0a,0xe9,0x87,0x5b,0xb5,
+  0x7c,0x8d,0xde,0x4b,0x72,0xe1,0x25,0x2d,0xdf,0x4b,0xbd,0xe4,0x7f,0x42,0xa3,0xe6,
+  0xf0,0x52,0x85,0xf4,0x4d,0x9e,0xd8,0x0f,0x2b,0xad,0x42,0x47,0x44,0xb0,0x83,0x2d,
+  0x54,0x33,0x0c,0x4b,0xa1,0x1b,0x9c,0x4c,0x56,0xf1,0xc5,0xbb,0x21,0x93,0x89,0xa3,
+  0x24,0x22,0xb9,0xf1,0x8a,0x78,0x44,0x9c,0xd8,0x9f,0xed,0x69,0x43,0xec,0xa7,0x50,
+  0xa9,0x2d,0x69,0xc8,0xd9,0x09,0xbb,0x3d,0x95,0x5e,0xdb,0x26,0xf9,0x19,0x18,0xd7,
+  0xf8,0x40,0xfc,0x00,0xae,0xd6,0xfe,0x4e,0xb3,0x05,0xc5,0x33,0xe9,0x13,0xfb,0x21,
+  0x6f,0xca,0xe7,0xec,0x28,0xae,0x86,0x6d,0x50,0xcc,0x85,0x71,0x5f,0xa9,0x66,0x1d,
+  0x6c,0xda,0xe9,0x38,0x30,0x7b,0xde,0x3d,0xeb,0x8f,0x89,0x73,0xd8,0x61,0xcd,0x5d,
+  0x6b,0xf5,0x8a,0xe9,0x89,0xf3,0x5b,0xae,0x9c,0x62,0x01,0xb0,0x83,0xcc,0xec,0x21,
+  0x29,0x90,0x66,0x57,0xa8,0xbf,0x49,0x85,0x80,0xd6,0xd1,0xee,0x58,0x65,0x51,0x03,
+  0x01,0x4f,0x99,0x40,0x99,0x65,0x5d,0x62,0x3d,0xeb,0x60,0x15,0xb4,0x08,0x21,0x4d,
+  0x0e,0xa6,0x17,0xc2,0x86,0xfb,0x43,0xde,0x3c,0x85,0x34,0x4b,0x8d,0x3e,0x47,0x1d,
+  0x55,0xb2,0xd3,0xd4,0x36,0x9f,0xaf,0xce,0xa1,0xcc,0xc8,0x4e,0xc8,0x9f,0x76,0xa9,
+  0x33,0xab,0x45,0xb1,0x57,0x2f,0x0a,0xe2,0xfa,0x37,0xe2,0xfa,0x3b,0x82,0x96,0x4e,
+  0xa1,0x85,0xd8,0x35,0x08,0x92,0x42,0xc8,0x50,0x0a,0xf9,0xfa,0xaf,0x4e,0xec,0x87,
+  0x50,0xda,0x10,0x3d,0x50,0xe7,0xbe,0x47,0xde,0x64,0xff,0xba,0x77,0x1c,0xba,0xf1,
+  0xfb,0xe6,0x74,0xfa,0x0f,0xe4,0xcf,0xf3,0x91,0x8d,0x62,0x21,0x39,0xa0,0xbb,0x35,
+  0xa7,0x52,0xe3,0x48,0xc8,0xcf,0x88,0xd0,0x09,0xe3,0xac,0x92,0x2f,0xc2,0x90,0x3a,
+  0x0e,0x95,0xcb,0xe5,0x60,0x8d,0x84,0xfb,0xa1,0xe2,0x07,0xd3,0xb2,0xc5,0x7e,0x8a,
+  0x3f,0xd5,0xe3,0x4f,0x17,0x12,0xf2,0x87,0x42,0x08,0x22,0x3e,0xb7,0x62,0x6b,0x2e,
+  0xb8,0x1f,0x4e,0x80,0x1b,0xd6,0xb2,0xa6,0x7c,0x88,0x68,0x6e,0xc8,0x6c,0x16,0x55,
+  0x75,0x8c,0xcc,0x03,0x2b,0x13,0x2d,0xd2,0xc4,0xfe,0x77,0x4c,0xe9,0x82,0xd5,0x5a,
+  0x47,0xb0,0x6d,0x88,0x5c,0xef,0x68,0x25,0x6a,0x23,0x1d,0xf1,0x38,0xa0,0x55,0x2a,
+  0x62,0x96,0xae,0xec,0x72,0x78,0x19,0x05,0x51,0x20,0x5a,0xb3,0x30,0xb1,0x1f,0x1c,
+  0xd2,0x83,0x10,0x64,0x8e,0x63,0xf2,0x3f,0x7b,0x96,0xc0,0xe3,0x50,0x18,0xbd,0x7e,
+  0x0e,0x59,0x47,0x7f,0x05,0x85,0xba,0xa5,0x9c,0x58,0xaa,0x51,0x50,0xeb,0x54,0x25,
+  0x0b,0x13,0xf2,0x87,0x29,0x7f,0xa2,0x4f,0x6b,0x33,0x75,0x79,0xd0,0x52,0x01,0x6b,
+  0xa0,0xd0,0x9b,0xf1,0x08,0xd9,0xac,0x3e,0xe1,0x2e,0xd6,0x2d,0x0d,0xfe,0x3c,0x78,
+  0x45,0x7c,0x20,0x42,0x7d,0x30,0x3c,0xb1,0x7d,0x20,0x10,0xf8,0x27,0x72,0x9c,0xdd,
+  0x76,0xda,0xb6,0xb4,0xe6,0xbb,0xf0,0xde,0xf0,0x2f,0xa2,0xc5,0xe5,0xf2,0x3a,0xf2,
+  0x7b,0xf6,0x5c,0x64,0x4d,0xb9,0x3c,0x0d,0xae,0xb2,0xaa,0x31,0x67,0x3d,0xfc,0x30,
+  0x21,0x7f,0x68,0xda,0x33,0xf8,0xee,0x65,0xed,0x36,0xc5,0xb6,0x4d,0xba,0xa8,0xcd,
+  0xd3,0xd7,0x85,0xc5,0x15,0xf0,0x31,0xb8,0xfb,0x32,0xc3,0xe2,0x08,0xdd,0x0b,0xee,
+  0xc1,0x25,0x21,0xd1,0x33,0x69,0xe2,0x7d,0x41,0x7a,0x4e,0x3b,0xc8,0xaa,0x42,0xb6,
+  0x88,0xfc,0x36,0xfd,0x4b,0x70,0x7e,0x74,0xc9,0xd8,0x8d,0x95,0xd2,0xd1,0xbe,0xaa,
+  0xd3,0x4b,0x7a,0xc4,0x32,0xed,0xa7,0x6c,0xc7,0xa8,0xb5,0x3e,0x87,0xe3,0x8d,0xd8,
+  0x5f,0x6b,0xde,0x2f,0x61,0x75,0xb8,0x58,0x97,0xbf,0x23,0xde,0xe7,0x59,0xe3,0xca,
+  0x8f,0xc8,0x63,0xe2,0x66,0xeb,0x9a,0x50,0x81,0x9e,0xf1,0x28,0xe4,0xc2,0x0e,0x96,
+  0xaf,0xd3,0x1f,0x0a,0x2f,0x24,0xd6,0x13,0xe0,0xe9,0x60,0xb3,0x5a,0xcc,0xe4,0x6f,
+  0x92,0x7d,0xf0,0x9c,0x30,0x53,0xbf,0xf1,0x11,0xb2,0x18,0xd6,0xa8,0xf8,0xbe,0x6e,
+  0xa2,0x08,0x2f,0xc1,0x74,0x9d,0x2e,0x4b,0xd7,0x12,0xf2,0x47,0x95,0xd6,0x4a,0x8d,
+  0xe0,0xec,0x94,0x15,0xff,0x61,0xad,0x0d,0xd4,0x08,0x4a,0xef,0xc7,0xa0,0xa9,0x96,
+  0x72,0x41,0x27,0xab,0x3b,0xa0,0xb0,0xdf,0xa1,0x5a,0x22,0xd2,0xc4,0xf9,0xed,0x9a,
+  0x32,0x42,0x0e,0x36,0x57,0x8e,0xda,0x94,0x82,0xd5,0xf0,0x2f,0x30,0x6f,0xd0,0xb6,
+  0x4f,0xbc,0x0b,0x8e,0xde,0xfe,0xf7,0xa8,0x8f,0x64,0x07,0xdb,0xc1,0xe6,0x72,0x41,
+  0xfa,0xc3,0xc4,0x7e,0x63,0xc2,0x36,0xe5,0x82,0x77,0x9a,0xb6,0x7e,0x93,0xbc,0x02,
+  0xc5,0x6c,0xa5,0x8e,0xf3,0x47,0xe8,0x45,0x69,0x86,0x6e,0x0b,0xa3,0xbc,0xba,0xd8,
+  0x38,0x4f,0xb7,0x85,0xc4,0x50,0x42,0xfe,0xe4,0x2b,0x3b,0xe1,0x12,0xec,0x3d,0x6d,
+  0x7b,0xb3,0xe0,0x27,0xea,0x21,0xd8,0x11,0x91,0x47,0xc5,0x9f,0x84,0xd6,0xd0,0xb9,
+  0xbd,0xd6,0x73,0xe2,0x15,0xf8,0x29,0x94,0xf6,0x66,0x45,0x45,0xbd,0x76,0x62,0xfe,
+  0x16,0x69,0xb9,0x12,0xd6,0xf1,0x7c,0x3d,0x45,0xfe,0x25,0x70,0x08,0xec,0xa7,0x6c,
+  0xa8,0xb6,0x50,0x53,0xd8,0xf5,0xcc,0x1e,0x72,0x46,0xda,0x3d,0x50,0xa4,0xd3,0x10,
+  0x89,0x2a,0x4a,0xe2,0x79,0x0a,0x61,0x4f,0xc0,0x1e,0xb8,0x31,0x7c,0x5d,0x09,0xf0,
+  0x69,0x8b,0x36,0x93,0x6d,0xf0,0x22,0xa8,0x7a,0x46,0xd8,0x3e,0xc4,0x76,0x37,0x3a,
+  0x7a,0x2d,0x21,0x35,0x9a,0xd8,0x6f,0x54,0x92,0xe8,0x1e,0xb5,0x5e,0xbb,0x31,0x4c,
+  0xd6,0x92,0xc7,0x71,0xda,0x8d,0xc4,0xb2,0x16,0xb6,0x42,0x48,0xbf,0xd3,0x8d,0x12,
+  0x69,0xaf,0xaf,0x5e,0xaf,0x53,0xb5,0x3e,0x21,0xb1,0xfc,0xd6,0xa9,0x52,0x8f,0x1d,
+  0xe5,0x73,0x58,0x74,0xd2,0xf5,0x82,0xbb,0xd7,0xb6,0xb1,0xad,0x93,0xfc,0x19,0x35,
+  0x94,0x14,0x46,0xc1,0x3b,0x5e,0x77,0x9b,0x9e,0x15,0x22,0x7a,0x42,0xfe,0x3c,0x7b,
+  0xd3,0x25,0xed,0x92,0x32,0x17,0x6c,0xb3,0x73,0x2e,0xc1,0x5f,0xa0,0x4a,0xcf,0x0a,
+  0x8a,0x3f,0x81,0x77,0xb4,0xf9,0xba,0xed,0xb8,0x38,0x8a,0x62,0xa4,0x0a,0x55,0xdb,
+  0xd7,0xea,0x13,0xf2,0x47,0x9f,0x72,0x49,0xbf,0x42,0x4b,0x07,0x6c,0xdb,0xc5,0x4b,
+  0x7e,0x04,0x42,0x51,0xdb,0x58,0xc1,0x15,0xb8,0xaa,0xe2,0xa0,0x4b,0xfc,0xae,0x77,
+  0x40,0xd9,0xa5,0x5b,0xe7,0x7c,0xaf,0x21,0xb1,0x7f,0x58,0xde,0x27,0xf0,0x91,0x66,
+  0x3f,0x2c,0x7f,0x41,0xae,0x68,0xad,0x60,0x8f,0xca,0x3d,0xe4,0x53,0x78,0x25,0x58,
+  0x14,0x95,0x43,0x7e,0x27,0x8b,0xa8,0xf6,0x68,0x66,0x30,0x5b,0x4d,0xca,0xff,0xb4,
+  0xc3,0x28,0x2b,0x55,0x5d,0x9e,0x6d,0x1f,0x00,0x3f,0x1f,0xb8,0xc8,0x00,0xec,0x40,
+  0x7d,0x27,0xdb,0xc9,0x62,0xf6,0x94,0x5a,0xa2,0xd7,0xd9,0x09,0x49,0xdc,0x5f,0x4f,
+  0xdb,0x46,0x5f,0xc0,0x65,0x6c,0x0b,0x93,0x11,0xf0,0x07,0x0c,0xb4,0x30,0x02,0x7b,
+  0xa1,0x48,0x97,0x1d,0xab,0x8b,0xa1,0x9d,0xbd,0x10,0xba,0x93,0x59,0x5c,0x89,0xfd,
+  0x00,0xb9,0xdb,0xe0,0x5c,0x5e,0x37,0xff,0xfa,0x23,0x88,0x4f,0xe2,0x83,0x8b,0x80,
+  0xdb,0x60,0x9b,0xf8,0x5f,0x73,0x23,0xac,0xd2,0x65,0xdd,0xd9,0xa4,0x24,0xe4,0xcf,
+  0x29,0xc4,0x7b,0x57,0x48,0xa5,0x7e,0xf3,0x68,0xc1,0x25,0xd4,0x6e,0x55,0xfa,0xfa,
+  0x51,0xf1,0x92,0x72,0x95,0x2f,0x4b,0x54,0xbe,0xe0,0xfd,0x98,0xe2,0xd2,0x0d,0x89,
+  0x63,0x09,0xf9,0xa3,0x23,0xfe,0xb9,0x40,0xf7,0xa0,0x12,0x97,0x9d,0x70,0x10,0xd5,
+  0xba,0x71,0xff,0xcf,0xf8,0xc6,0xeb,0x14,0xdf,0x87,0xb7,0x01,0xe5,0xcf,0x46,0xd1,
+  0x95,0x38,0x2f,0x07,0xd3,0x2a,0x60,0x0f,0x14,0xf4,0xd2,0x51,0x32,0x15,0xf8,0x8b,
+  0x18,0xcf,0xff,0x0a,0x94,0xe8,0xf2,0x8b,0x64,0x0b,0x34,0xf9,0x10,0x41,0xfa,0x6b,
+  0x1e,0x4e,0xec,0x87,0xd3,0x69,0x8b,0x71,0x7d,0xba,0x74,0x84,0x3d,0x56,0x5c,0x9f,
+  0xd0,0xc4,0xfa,0x38,0x75,0x19,0x2c,0x5d,0x69,0x41,0xdd,0xd1,0x49,0xc3,0x9e,0xf2,
+  0x84,0xfc,0xf1,0x09,0xd3,0x60,0x7f,0x28,0x7f,0x24,0x63,0x25,0xb1,0xea,0xcf,0xb2,
+  0xfc,0x61,0x99,0xc3,0x80,0x5d,0xac,0x38,0x2a,0xd7,0x59,0xf6,0x6a,0xcd,0xac,0x20,
+  0x4a,0x7f,0x68,0x5f,0x9a,0xc4,0x3f,0xd4,0xaa,0x9d,0x0b,0x95,0x0f,0x67,0xee,0x11,
+  0xb3,0xf0,0xf9,0x5d,0x51,0x44,0x3b,0x03,0xf8,0xfc,0x78,0xff,0x2e,0x31,0xa0,0x0d,
+  0x42,0x39,0xb3,0xde,0x20,0x27,0x8d,0x0a,0xc4,0x3f,0xea,0x79,0xa8,0xea,0x5f,0x77,
+  0x4e,0xbc,0x3c,0x9b,0xaf,0xcf,0x24,0x5c,0x1f,0xed,0x2a,0xc5,0xf5,0x79,0x7f,0x51,
+  0x8f,0x36,0x06,0x0b,0xd8,0x2c,0x5d,0x0c,0x26,0xf0,0x4f,0x57,0xda,0x25,0x8e,0x16,
+  0xfa,0xad,0x2f,0xb7,0x39,0xd9,0x85,0x89,0xf5,0xb9,0xe8,0xc0,0xf5,0x61,0xa2,0x43,
+  0x42,0x68,0xc4,0xf1,0x4f,0x51,0x42,0x7f,0x45,0x26,0x6f,0x46,0xb4,0x93,0x3f,0x4c,
+  0x1f,0x21,0x53,0xd9,0xcb,0x30,0x53,0xcf,0x6a,0x40,0xd8,0xb3,0x0b,0xe5,0x89,0xac,
+  0x89,0x2b,0xe1,0x8f,0xb0,0x85,0x65,0x46,0x89,0x3b,0xf1,0x7d,0x75,0x78,0x9a,0xed,
+  0x62,0xd1,0x28,0x7d,0xd4,0x33,0x2d,0xc0,0x61,0x4f,0xf2,0x7d,0xeb,0x2d,0x37,0xc0,
+  0xba,0x80,0x7a,0x9a,0x2e,0x45,0x9b,0x65,0x62,0xfd,0xeb,0x72,0x47,0x70,0x3d,0x7d,
+  0x3a,0x0d,0x5f,0x67,0x85,0xed,0xb8,0xcd,0x2c,0x89,0xf5,0x74,0xf9,0xeb,0xb4,0x5f,
+  0x1d,0x50,0x07,0x33,0xac,0xad,0xd9,0x26,0xfc,0x33,0x0c,0x2f,0xbb,0xba,0x99,0x35,
+  0x64,0x71,0xc0,0x15,0x0d,0x0f,0x1a,0x87,0x3d,0x88,0x87,0x99,0x6d,0x48,0x9e,0x9f,
+  0x7d,0x44,0x9f,0x1d,0xb2,0x7e,0x4a,0xe6,0x25,0xf1,0x0f,0xea,0x23,0x0e,0x72,0x66,
+  0xb1,0x49,0x51,0x18,0xb3,0x54,0x42,0x96,0x31,0x10,0x38,0xec,0x91,0x4f,0xa9,0x63,
+  0xda,0x7e,0x82,0x2f,0x6e,0xc6,0x3f,0x43,0x70,0x00,0x2a,0x38,0xc8,0x91,0xc8,0x01,
+  0xae,0xe8,0x51,0xf1,0xc1,0x5b,0x88,0x10,0x6c,0xed,0x08,0x6c,0x3e,0xd4,0xbf,0xd0,
+  0xac,0x93,0x45,0x92,0x78,0x9e,0x90,0xb4,0x1c,0x41,0x0e,0xc2,0x9e,0xa0,0xa5,0x90,
+  0x72,0xfd,0x2b,0x07,0xc9,0x10,0xe2,0x1f,0x34,0x04,0x14,0x32,0x89,0x19,0x3f,0x6d,
+  0x12,0x7d,0x26,0xfc,0x53,0x08,0x2d,0xf7,0x96,0xe0,0x7c,0x4f,0x21,0x3c,0x29,0xf0,
+  0xf9,0xf6,0xce,0xd8,0xfc,0x0d,0x96,0x42,0xed,0x79,0xcd,0xae,0x3b,0x82,0xfe,0x74,
+  0x93,0xfc,0x41,0x3c,0xc0,0x41,0x4e,0x2e,0x91,0xe0,0x7a,0x4d,0xd5,0x32,0x38,0x10,
+  0xda,0x0e,0x4e,0x0d,0x11,0xd7,0x74,0xc4,0x3f,0x78,0xff,0x5c,0xe2,0x49,0xc8,0x9f,
+  0x76,0xaa,0x42,0x04,0xdf,0xd7,0x0a,0x35,0x2a,0xea,0xdf,0xee,0x18,0xde,0x3b,0x01,
+  0x25,0x60,0x03,0x51,0x45,0x45,0x57,0x26,0x2c,0x66,0x62,0x49,0x12,0xff,0xdc,0xf4,
+  0xc1,0xa4,0xcb,0x5a,0x99,0xf7,0x39,0x8e,0x76,0x3e,0xe0,0xaf,0x19,0x2c,0x18,0xe2,
+  0xf8,0x87,0x23,0x9c,0xf3,0x70,0x59,0xab,0xf2,0xce,0x3a,0x3e,0x29,0x89,0x7f,0x38,
+  0x5e,0xfa,0xdc,0xe1,0x5e,0x6c,0x0d,0xe6,0xcc,0xa1,0x17,0xb5,0xf8,0xfa,0x8c,0xd3,
+  0x9f,0x69,0xb6,0x37,0x27,0xcd,0x81,0x4f,0x1c,0xbb,0xea,0xac,0xc7,0x9e,0x98,0x91,
+  0x38,0xbf,0x79,0x4a,0x34,0x14,0x29,0xec,0xb0,0x52,0xa9,0xed,0x7e,0x3c,0x68,0x1d,
+  0x08,0x84,0x50,0x1a,0xf7,0xe0,0x13,0xca,0x4c,0xf0,0x85,0x02,0xaa,0x5b,0xb2,0x3e,
+  0x4b,0xb2,0xd2,0x13,0x56,0x6c,0x5a,0x7f,0x64,0x8b,0x23,0x5a,0x67,0xc9,0x29,0x4a,
+  0x83,0xdd,0xaa,0xaa,0x59,0x12,0xef,0x8b,0x78,0x86,0x3d,0xef,0x98,0xa1,0x51,0xc5,
+  0x4f,0x84,0x89,0xe7,0xcf,0x9b,0xd2,0x09,0x6d,0x94,0xaf,0x3f,0x59,0x6e,0xe0,0xcf,
+  0xf8,0xfa,0x17,0xf1,0xc1,0x72,0x68,0x53,0xed,0xb5,0x75,0x41,0xcf,0x1d,0x09,0xf9,
+  0xd0,0xa1,0x74,0x0a,0x1f,0x22,0x88,0x75,0x06,0x51,0x11,0x6c,0xd7,0x89,0x96,0x65,
+  0x3c,0x3f,0xae,0xbf,0xed,0x29,0x5c,0xe1,0xe7,0xa1,0xcc,0xe3,0xfc,0x75,0x86,0x23,
+  0x21,0x1f,0x02,0xd0,0x09,0xa7,0xd8,0x3e,0xc4,0xc3,0x22,0x02,0x21,0xb5,0x32,0xfe,
+  0xbe,0x7c,0xa1,0x36,0x35,0xfd,0x19,0xc6,0x03,0xf3,0xee,0xcf,0x0a,0x36,0xbd,0x90,
+  0xd8,0xcf,0x45,0x4a,0x88,0x8e,0xe9,0x6e,0xbe,0xcd,0x70,0xe3,0x69,0xf1,0xf5,0xe7,
+  0x3b,0xf0,0xee,0x66,0xd1,0xd7,0x3c,0x0c,0x6e,0xc5,0xca,0x72,0x0e,0x26,0xf1,0x4f,
+  0xad,0x03,0x3e,0x0d,0xd8,0x59,0x5d,0x48,0xac,0xc7,0xf5,0xb1,0x33,0x39,0x44,0x86,
+  0x71,0xf0,0x33,0x26,0xaf,0xf0,0xf4,0xc0,0xea,0x5a,0x95,0x59,0x86,0xc4,0x83,0x89,
+  0xf3,0xee,0x48,0x5b,0x21,0xec,0xe0,0x68,0x07,0xf5,0x91,0x62,0x88,0x65,0xe3,0xbc,
+  0x88,0x4e,0x7e,0x70,0xee,0xd2,0xb6,0xb2,0x68,0x3f,0xdd,0x77,0xcf,0xc1,0x84,0xfc,
+  0xc9,0x17,0xa6,0x0a,0x2f,0x93,0xe9,0x11,0x34,0x52,0x36,0xe3,0xb1,0x45,0x3c,0x60,
+  0x9c,0x5f,0x3c,0xc8,0x72,0x83,0x7f,0x13,0xac,0xd1,0x0a,0xb4,0xa7,0x1a,0xfc,0x91,
+  0x24,0xbe,0xa2,0x37,0x07,0xbe,0x64,0xbb,0x3e,0xcc,0xfa,0x19,0x9a,0x2d,0x57,0xdf,
+  0xbc,0x2d,0xba,0x7e,0xa5,0xf8,0x2e,0x7c,0x89,0xe7,0x37,0x6b,0x4c,0x7c,0x94,0xfc,
+  0x85,0xcd,0x8e,0x3a,0xeb,0xc5,0x83,0x49,0xfc,0x73,0xe7,0x6f,0xe1,0x23,0x98,0xd7,
+  0x6f,0xeb,0x7e,0x15,0xf5,0xbb,0x56,0x66,0xc8,0x13,0x6a,0x28,0xfa,0xb0,0x38,0x44,
+  0x2e,0xe0,0x51,0xc2,0x13,0xea,0x4f,0xc8,0x1f,0x6d,0xca,0x15,0xf8,0x04,0xd5,0x96,
+  0x75,0x4c,0xac,0x60,0x57,0x71,0x90,0x39,0x86,0x6a,0xfd,0xa2,0xa1,0xc8,0xc4,0xfd,
+  0x70,0xb4,0x71,0x76,0xd4,0xda,0x83,0x5f,0x77,0x62,0xff,0x74,0xa1,0xfc,0x61,0x79,
+  0xaa,0xee,0x68,0x58,0x68,0xc5,0xc7,0x56,0x87,0x65,0x7c,0x7e,0xba,0x8b,0xdd,0xaa,
+  0xcb,0xfa,0xe4,0x47,0x1a,0xdf,0xa3,0xb7,0xd6,0x65,0xd6,0xdf,0xf2,0x42,0xe2,0xfb,
+  0x06,0x61,0x33,0x3c,0x07,0xf9,0xfd,0x28,0x9f,0xa7,0x6a,0xbb,0x00,0xf1,0x52,0xec,
+  0x7d,0xf3,0xf1,0x7d,0xc9,0x26,0xba,0x09,0xf1,0xcf,0xf5,0x2e,0x7b,0x33,0x9b,0x58,
+  0x7f,0x9f,0x34,0x00,0xad,0xb5,0x45,0x31,0x79,0xbe,0x23,0x98,0xd0,0x77,0x85,0xfa,
+  0xa2,0x19,0x44,0xa5,0x7e,0xad,0xd0,0x77,0x7d,0x21,0x69,0x4f,0x9c,0x77,0x47,0xda,
+  0x3e,0xf8,0xa8,0xbf,0x54,0xcf,0x1c,0x45,0xeb,0x78,0x2e,0x74,0x4c,0xe8,0x2f,0x2e,
+  0x48,0x49,0x17,0xd9,0xe8,0x9d,0x73,0x36,0xb3,0x67,0x92,0x45,0x4a,0x3e,0xcf,0x08,
+  0x5c,0xc0,0x65,0xc9,0x0a,0xe7,0x8c,0xc4,0xf0,0x4f,0x58,0x48,0xae,0x8f,0x84,0x83,
+  0xd7,0x8f,0x36,0xe1,0x56,0x9c,0xb8,0xff,0x06,0xb6,0x82,0x5e,0xa4,0xdd,0x68,0x54,
+  0x7a,0x2a,0x50,0x0d,0xa1,0x61,0x8b,0xf2,0x1c,0xff,0xe1,0xcd,0xba,0xed,0xbc,0x5c,
+  0x9e,0xf6,0x29,0xda,0xb3,0x74,0x54,0x8c,0xd6,0x4e,0xc8,0x93,0xde,0xdc,0x15,0x7c,
+  0xdb,0xe8,0x8e,0x30,0xc2,0x98,0xbd,0x90,0xd0,0xbf,0x0f,0xea,0x72,0x8f,0xfd,0x39,
+  0xb5,0x95,0xbd,0xa0,0x77,0xb1,0x82,0x21,0x2d,0x81,0x7f,0xd2,0x9c,0xfc,0x98,0xf4,
+  0xde,0x70,0xcd,0x7c,0xd4,0x77,0x0a,0xf9,0x07,0x61,0x6f,0xe3,0x0b,0xda,0x0d,0xdb,
+  0x57,0x47,0x13,0xfb,0x87,0x4a,0x56,0x08,0x23,0x0c,0xb0,0x70,0x58,0xb8,0x17,0x42,
+  0x6f,0xc5,0xd6,0x07,0x61,0xb6,0x2c,0x10,0x26,0xb5,0xe0,0x41,0xb3,0xa8,0xa4,0x2f,
+  0x6d,0x62,0x3f,0xb0,0x0c,0xbe,0x0d,0xdc,0xfa,0xdd,0x67,0x0b,0x7e,0x43,0xbf,0x04,
+  0xf7,0xdb,0x71,0xfd,0x82,0xf7,0x0f,0x8a,0xcb,0xa5,0x31,0x98,0xa7,0x65,0x3d,0xd1,
+  0x94,0xb4,0x07,0x43,0x99,0xa8,0xd6,0x9d,0xaf,0xf4,0xdd,0x85,0xaf,0xc9,0xae,0x42,
+  0x65,0xc4,0x78,0x5f,0x43,0xbf,0xa3,0x2a,0x23,0x97,0xa0,0xaa,0xfa,0xae,0x3e,0xb1,
+  0x2b,0x2d,0x89,0x37,0x46,0xd8,0x21,0x1f,0x82,0xcc,0x73,0xe2,0xc9,0x8e,0xa3,0xf6,
+  0xf9,0xf8,0x21,0xc4,0x8a,0xd0,0x51,0x75,0x7e,0x24,0xb3,0xbb,0x60,0x5f,0x33,0x02,
+  0x21,0x7d,0xed,0x69,0x03,0x38,0xc5,0xe7,0x2b,0xa7,0xb4,0xd6,0x06,0xfb,0x1c,0xba,
+  0x2f,0x67,0x16,0xb4,0x29,0x68,0x7f,0xfd,0xda,0xf3,0x75,0xe8,0xca,0xb5,0x0f,0xd2,
+  0xed,0x24,0xa4,0x7d,0x18,0xb4,0x9f,0xb5,0x6c,0x23,0xa3,0x89,0xf5,0x8f,0xa4,0x0d,
+  0x90,0x46,0xfc,0xfa,0x01,0x89,0x04,0x50,0x5a,0x39,0x06,0xf1,0x7d,0xad,0x92,0x48,
+  0x0a,0x07,0xa9,0xb1,0x43,0x88,0xaa,0xd4,0x4d,0x4e,0x37,0xf9,0x7f,0x26,0x77,0x49,
+  0x68,0xdf,0x11,0xca,0xfa,0xba,0xd4,0x17,0xa8,0x9d,0x58,0x82,0x7e,0x14,0xe3,0x60,
+  0xef,0xa3,0xe1,0xec,0x90,0xf0,0x3c,0xb5,0x03,0x09,0x92,0xa4,0xff,0xa7,0x76,0xca,
+  0x27,0x70,0x08,0x5e,0x1e,0x74,0xce,0x11,0x7f,0x23,0xbd,0xef,0x41,0xfc,0xbc,0x53,
+  0x2e,0x92,0x0e,0xc1,0x05,0x65,0xed,0xf6,0xad,0xbf,0x65,0x17,0xab,0xdd,0xbd,0xd6,
+  0xd0,0xa4,0xc1,0x84,0xfc,0x0c,0x09,0x61,0xbe,0x6d,0xd8,0x92,0xb0,0xf8,0x5d,0xff,
+  0x3b,0xa1,0x4a,0x76,0x57,0x58,0xec,0x53,0x2e,0xc0,0x65,0x98,0x15,0x2e,0x38,0x5d,
+  0xfb,0xb1,0x54,0xd1,0x67,0x0b,0xe1,0xd6,0x9a,0xb8,0xff,0xa0,0xf2,0x18,0xbc,0x2f,
+  0x95,0x9d,0xb0,0x76,0x4e,0x9a,0x89,0xf8,0xca,0x35,0x68,0x9d,0x23,0x3e,0x48,0x0e,
+  0x41,0x59,0x30,0xd3,0xd5,0xe4,0x94,0x3e,0xbe,0xdf,0xad,0xaf,0x0d,0x17,0x84,0x13,
+  0xf2,0x27,0x92,0xe6,0x60,0x6d,0x01,0x35,0x80,0x20,0xd9,0x01,0x6f,0x7b,0xed,0x3d,
+  0x81,0x30,0x9a,0x8d,0x2f,0x7e,0xd3,0xce,0x68,0x98,0xe4,0x4b,0x4d,0xba,0xbd,0x97,
+  0x76,0x93,0xb2,0x84,0x7c,0x88,0x22,0xfe,0xd9,0xaa,0xaa,0x83,0x68,0x6d,0x49,0x6a,
+  0x23,0x38,0x22,0xf8,0xf5,0x17,0xc3,0x8b,0x4c,0xd5,0x5b,0x80,0x64,0x0d,0x76,0xf7,
+  0xab,0x9f,0x5b,0x54,0xbf,0xc9,0xff,0x23,0xa4,0x6b,0xab,0x9f,0xb9,0xbf,0x3e,0xb0,
+  0x92,0x7c,0x1b,0x7e,0xc1,0xf2,0x7d,0x96,0x85,0xf6,0x69,0xd0,0xd9,0xae,0x46,0x69,
+  0x9d,0x65,0x1a,0xec,0x6c,0x37,0x1c,0x41,0x3f,0x31,0xe1,0x9f,0xac,0xe0,0xa9,0x50,
+  0x58,0x2f,0xc9,0x6b,0xb3,0xb2,0x5e,0xe8,0xd1,0x4b,0x1c,0xe2,0x62,0x78,0x35,0xbc,
+  0x53,0xcf,0xcc,0x93,0xad,0xec,0xb3,0x70,0x18,0x4a,0xf2,0x84,0x63,0x13,0xdb,0x0d,
+  0xb4,0xcc,0x7d,0xb9,0x97,0x94,0xf9,0x75,0xb6,0x37,0x6b,0xf6,0xc1,0x65,0xa5,0xaa,
+  0x36,0x53,0xc7,0xfd,0xf3,0x27,0xf8,0x79,0xbf,0xed,0x4d,0x1c,0x1c,0x86,0x2a,0x29,
+  0xf3,0x44,0x0a,0xfe,0x19,0x81,0x8f,0x05,0xbe,0x08,0x39,0x85,0xca,0x21,0xee,0xf6,
+  0x09,0x17,0xfc,0x10,0xbf,0x88,0x5b,0xcb,0x0c,0x89,0x88,0x18,0x99,0x5b,0xc7,0xc1,
+  0x47,0x26,0xfc,0x83,0x42,0x12,0xb8,0xdb,0x87,0x4a,0xd0,0x44,0x0c,0xff,0x4f,0x00,
+  0x9e,0x05,0x87,0x96,0xe9,0x43,0xc4,0xe8,0x17,0x0c,0x47,0xd0,0xb9,0xc4,0xfa,0x33,
+  0xf8,0x2d,0x3c,0xc7,0x1a,0xb9,0xb7,0x67,0x1a,0x3c,0xc1,0xa6,0xc7,0x06,0x5b,0x63,
+  0xfe,0x9f,0xbb,0x61,0x0d,0x0a,0x52,0x84,0x82,0x51,0x13,0xfe,0x19,0x80,0xb6,0xa0,
+  0x3a,0x44,0x6f,0xf3,0x58,0xe1,0x57,0xc1,0xc2,0x21,0x5a,0x4e,0x1e,0x53,0xb7,0x06,
+  0x1d,0x7d,0x19,0xbb,0x71,0x61,0x9b,0x82,0xce,0x4b,0x79,0xa9,0xfe,0x9f,0x2e,0xc4,
+  0xf3,0x6e,0xb6,0x4d,0x95,0x29,0x79,0x1b,0x5e,0x66,0x8e,0xdf,0x8a,0x33,0x51,0x02,
+  0xbb,0xc3,0xce,0x90,0x5c,0x4f,0x0e,0xc2,0x83,0xc1,0xcc,0x17,0x44,0x93,0xff,0x07,
+  0x7c,0xca,0xd8,0xc2,0x0a,0xb4,0xc7,0x6b,0x4e,0x29,0xc3,0x88,0x7e,0x6d,0xac,0x29,
+  0x04,0xa8,0x7f,0xa5,0x2c,0x26,0x32,0x18,0xab,0xa6,0xca,0xcd,0xfd,0x29,0xf8,0xa7,
+  0x1f,0x0e,0xe8,0x95,0xbe,0xcc,0x76,0xf1,0x59,0x18,0xd7,0xc3,0xdc,0xff,0xb3,0x1c,
+  0xc6,0x37,0xba,0xb4,0xcc,0x20,0xe2,0x9f,0x03,0x50,0xf9,0x90,0x75,0x43,0x8a,0xff,
+  0xe7,0xfb,0xd0,0x02,0x1d,0xb5,0x74,0x13,0x99,0xd1,0xd7,0xa2,0x77,0x78,0x2d,0xdc,
+  0xed,0xb0,0x9b,0x75,0x78,0x69,0xd0,0x5e,0x28,0xb5,0x68,0x25,0xdf,0xc4,0x9f,0x92,
+  0xe7,0x3d,0x2f,0x6d,0x01,0x3c,0x06,0x05,0x1e,0xf9,0x4d,0xb2,0x13,0x7e,0xa7,0x15,
+  0x78,0xe9,0x20,0xd9,0x29,0x3d,0x23,0x18,0x83,0x39,0xf0,0x98,0xef,0x1f,0x35,0x7a,
+  0x9c,0xbc,0x6e,0xc2,0x3f,0xb9,0x9e,0x55,0xb5,0xf9,0x5a,0x5d,0x03,0xc9,0x85,0x34,
+  0x2d,0xdf,0x4b,0xbc,0xe9,0x31,0xff,0x8f,0xe3,0x5e,0x32,0x05,0x56,0xc1,0x03,0x3a,
+  0xf5,0x92,0xa4,0xfd,0x55,0x9e,0x79,0x3f,0x87,0xfd,0x5c,0xed,0x86,0x60,0x25,0x0e,
+  0xac,0x4c,0xe6,0xfa,0xd7,0x0d,0x77,0x81,0xac,0x12,0x0e,0x8d,0x9c,0x7a,0xc1,0x11,
+  0xc1,0x84,0x7f,0xd8,0x59,0xed,0x65,0xee,0xed,0xf9,0x3e,0xc2,0x9e,0xfd,0xde,0xf5,
+  0x1c,0x08,0x4d,0xf8,0x7f,0x68,0x7c,0x60,0xf2,0xff,0xa4,0x7d,0x1e,0x3a,0x5c,0x58,
+  0x5a,0x67,0x1d,0x6c,0x3a,0x2f,0x1d,0x56,0x4a,0xb5,0xcc,0x8d,0xe2,0x79,0x76,0x58,
+  0xa9,0xf4,0x5a,0x7f,0x29,0x4e,0x67,0x87,0x0d,0xc4,0xe8,0x37,0xfb,0x7f,0x7a,0x37,
+  0x06,0x1c,0x76,0xa0,0xcd,0xe2,0x16,0x4d,0xf5,0x86,0xf2,0x1c,0xcc,0x73,0x0a,0x02,
+  0xdf,0x2c,0x9a,0x5a,0xb4,0x9a,0xcc,0x6e,0x0e,0x40,0x99,0x22,0xf7,0x5b,0xb2,0x12,
+  0xf6,0x75,0x5d,0x5a,0x3f,0x82,0x3a,0xd5,0x1b,0xe0,0xb0,0xa7,0x51,0x55,0xef,0x41,
+  0x74,0xd7,0xaf,0x35,0xaa,0xd3,0xb5,0x3a,0x7c,0x5f,0x65,0xcb,0xed,0x33,0xbd,0x8b,
+  0xbc,0x64,0x63,0x42,0xfe,0x20,0xfe,0x61,0x2d,0x6a,0x87,0x86,0xa7,0xb5,0x93,0x6e,
+  0x05,0x1f,0x07,0x42,0x43,0xf8,0x45,0x66,0x72,0x47,0xd9,0x1c,0x61,0x26,0xcc,0xf2,
+  0xdc,0x38,0x68,0xf6,0xff,0x4c,0x19,0x22,0x07,0x98,0x4b,0x73,0x3e,0x7d,0xcf,0x99,
+  0xe0,0x01,0x35,0xe6,0xd6,0x6b,0x3a,0xa0,0x96,0xf9,0x16,0x07,0xe5,0x42,0xf2,0xa1,
+  0x7d,0x5e,0x83,0xed,0x09,0xb1,0x2b,0x21,0x7f,0x86,0x85,0x4e,0x38,0x4b,0x11,0xed,
+  0x3c,0x55,0x30,0xd4,0x81,0xb0,0xc7,0x63,0xe0,0x9f,0x1f,0x43,0x65,0xdd,0xcd,0x7c,
+  0xf0,0x26,0x94,0xd5,0xda,0x94,0xa6,0x47,0x13,0xfb,0xdf,0xa1,0x84,0x10,0x7f,0xce,
+  0x83,0xc7,0x56,0x15,0x44,0x35,0xee,0x76,0xcb,0xe2,0x8e,0xe8,0xc8,0x20,0x7e,0x88,
+  0x66,0x51,0x31,0x1c,0x41,0xb6,0x55,0x05,0x26,0xfc,0x93,0x56,0x0e,0xeb,0xd4,0x02,
+  0x46,0x87,0x71,0x37,0xaf,0xd3,0x70,0x10,0x22,0x11,0xb5,0xb5,0xba,0x8c,0x39,0x42,
+  0x76,0x07,0x94,0xac,0xb5,0x37,0x23,0x22,0x3a,0x98,0xc4,0x27,0x69,0xcb,0x09,0xae,
+  0x4f,0x6d,0x86,0x4a,0x5e,0x83,0x1d,0x2d,0x85,0x67,0xf1,0x3c,0xbe,0x0e,0x2d,0x04,
+  0x0c,0xc7,0x69,0x7e,0xf7,0x16,0x90,0x64,0x0a,0x49,0xfc,0x13,0x12,0xa6,0x52,0x3c,
+  0xbf,0x1a,0x1e,0xd2,0x41,0xb2,0x46,0x9b,0x3e,0x88,0x40,0xe8,0xb8,0xb4,0x1a,0x70,
+  0xb0,0xdc,0x7e,0x13,0xbc,0x14,0x03,0x06,0xc3,0x89,0xfb,0x77,0xd1,0x6c,0x78,0xad,
+  0x79,0x76,0x34,0x73,0x25,0x39,0x06,0x9f,0xb3,0x97,0xa2,0xce,0x95,0xe2,0xeb,0xe4,
+  0x55,0xb6,0x23,0xe4,0x1c,0x93,0x2b,0xc9,0x67,0x6c,0x7b,0xd4,0xb6,0x52,0xfc,0x28,
+  0x89,0x7f,0x6e,0xea,0x52,0x3e,0x4b,0xff,0xad,0xbe,0x3e,0x2c,0xea,0xca,0x38,0xcc,
+  0xe3,0x86,0xff,0x10,0x5c,0x10,0x2b,0xb9,0x61,0x32,0x82,0x82,0x65,0x1a,0xbf,0xd2,
+  0x97,0x90,0x3f,0x90,0xf6,0x05,0x9c,0x64,0x93,0x7c,0x4b,0x3e,0x14,0xbb,0xe1,0xa4,
+  0x3e,0xdf,0x97,0xc5,0xf1,0xcf,0x97,0xac,0x6a,0x85,0xf5,0x84,0xe8,0x66,0xff,0x23,
+  0x58,0x35,0x64,0x1b,0x17,0xf5,0xc4,0xfa,0x77,0x09,0x53,0x61,0x35,0xdc,0xba,0x54,
+  0xce,0x27,0x5e,0xed,0xb8,0x82,0xeb,0xe3,0x22,0xc7,0xb5,0x1d,0xca,0xad,0xb5,0x54,
+  0x23,0x8a,0xb4,0x7d,0x7b,0x31,0x57,0xc4,0x1f,0x25,0xed,0x6b,0x25,0x08,0xbf,0x54,
+  0xa6,0xe3,0x4b,0x79,0x06,0x51,0x71,0xcf,0xd4,0x66,0xc6,0xf1,0x0f,0xcd,0x98,0x4c,
+  0xb2,0x57,0xed,0xca,0x2f,0xd6,0xe4,0x86,0x74,0x3d,0xe9,0xff,0xc9,0x8d,0xd4,0xb5,
+  0xfa,0x0a,0xcf,0xa1,0xf6,0xd7,0x70,0xbe,0xbd,0x19,0x81,0x50,0x3f,0xec,0x28,0x9c,
+  0x01,0x19,0x40,0x54,0x6d,0x87,0x84,0x8a,0xbe,0x1c,0x8f,0xcd,0xc4,0x79,0xdf,0x36,
+  0x65,0x1b,0xbc,0xa5,0x95,0x55,0xe3,0xf9,0xea,0x44,0xb3,0x6b,0x9e,0x9e,0xd9,0x23,
+  0x9e,0x81,0xcf,0xa2,0x38,0x08,0x5b,0x9c,0x08,0xe4,0x0c,0x0f,0xcf,0x47,0x26,0x79,
+  0x38,0xe2,0xb8,0x58,0x5d,0x59,0x6b,0x6b,0x16,0x99,0xf2,0x8e,0x56,0xd5,0x77,0xf7,
+  0x76,0x71,0x48,0xbb,0x00,0x7b,0xf4,0xac,0xd0,0xa4,0x11,0xc7,0xb8,0x82,0x5b,0x6b,
+  0x07,0x22,0xe4,0x89,0xfb,0x0b,0xca,0x88,0x78,0x18,0x61,0xcf,0xfa,0x80,0xd8,0x23,
+  0xbc,0x11,0x42,0x45,0x3f,0x8a,0x66,0xc8,0xcf,0xd5,0xb9,0xfd,0x38,0xb8,0x24,0xad,
+  0x27,0x55,0x11,0xab,0x5e,0xa3,0x6b,0x49,0xf9,0xf3,0xa0,0xb7,0xd5,0x83,0x9b,0x64,
+  0x2d,0x2e,0xc2,0x8b,0x9a,0x9d,0xad,0x0d,0xe3,0xfe,0xdf,0xc3,0xec,0xc7,0x96,0x84,
+  0xec,0x23,0xd2,0x3b,0xcd,0xf3,0x74,0x54,0xf4,0x49,0xf9,0xc3,0xd2,0xac,0x6a,0x40,
+  0x2b,0xea,0x95,0xfd,0xe9,0x51,0x16,0x80,0x19,0x1a,0x02,0xa1,0x21,0x8d,0xe3,0x1f,
+  0x1a,0xcc,0x8e,0x4a,0xcf,0xeb,0xce,0x20,0xdd,0x49,0xa2,0xd2,0xc4,0x7e,0x40,0xfc,
+  0x43,0xfc,0x92,0x43,0xc3,0x45,0xd6,0x71,0x6b,0xab,0x6c,0xe1,0xec,0xf4,0x7e,0x69,
+  0x87,0xf2,0x43,0xdd,0x22,0x65,0xeb,0xc2,0x76,0x5f,0x91,0xee,0x98,0x63,0x92,0x3f,
+  0x90,0xf6,0x80,0xa7,0xf5,0x9b,0xf3,0x74,0x43,0xfe,0x58,0x85,0x32,0xad,0x28,0xec,
+  0x19,0x42,0x0d,0x5e,0x81,0xf7,0x2f,0x88,0x4a,0x1f,0xd6,0x57,0xea,0xd6,0x9d,0xa2,
+  0x2e,0x4e,0x4c,0x0f,0x4d,0xb9,0x04,0x5f,0xe4,0xef,0x12,0x6c,0x7d,0xe2,0x20,0x20,
+  0xda,0x69,0x44,0x60,0x73,0x1e,0xae,0xaa,0xbb,0x74,0x5b,0xdf,0xa4,0x51,0xf8,0x93,
+  0x3a,0x1f,0xd6,0xeb,0xe2,0xf0,0xa4,0x04,0xde,0x48,0xbb,0x02,0xaf,0xb3,0xb9,0xfd,
+  0x8b,0x1b,0x6a,0x7e,0x4a,0x8e,0x82,0x9b,0xc3,0x66,0xc4,0x4b,0x52,0x15,0x1f,0x8c,
+  0xfe,0x62,0xc4,0x55,0x9a,0x6e,0xed,0x15,0x5d,0x09,0xf9,0xc3,0x94,0x4f,0xa1,0x15,
+  0x61,0x1e,0x0d,0x7b,0x16,0x68,0xeb,0xa1,0xa3,0x4f,0xee,0x21,0x57,0xb5,0x57,0x06,
+  0x4b,0xa2,0x88,0x0f,0xcf,0x68,0xbb,0x5d,0x88,0x88,0xd6,0x10,0x35,0x21,0xcf,0x69,
+  0xda,0x30,0xc2,0x1e,0x3b,0xc7,0x7b,0x6b,0x59,0x13,0xea,0x77,0x8e,0xf7,0xd0,0xd0,
+  0x58,0x61,0x00,0x63,0xbe,0x02,0xa8,0x31,0x3c,0xfe,0x24,0xfe,0x99,0xd2,0x15,0x7a,
+  0xa1,0xc5,0xee,0xb3,0xb4,0x23,0x3e,0x6f,0x83,0x22,0x5d,0x4c,0xe0,0xc9,0x30,0xf9,
+  0x14,0xf6,0xf4,0x77,0x6c,0xa7,0x9b,0x49,0x38,0xb1,0x3f,0xb5,0x29,0x9f,0x4a,0x1f,
+  0x37,0x97,0x8d,0x96,0x94,0xd7,0xac,0x80,0x43,0x64,0xde,0x04,0x7e,0x36,0xf0,0xf0,
+  0xa7,0xc2,0x30,0x73,0xab,0xd6,0x80,0x1c,0x4c,0xec,0xff,0xa8,0xb0,0x8f,0xbc,0x47,
+  0x5e,0x41,0x98,0x67,0xc1,0xd5,0x81,0xb9,0xdc,0xbf,0x31,0x42,0x0d,0x7c,0xc8,0xf7,
+  0xc3,0x38,0xad,0xf4,0xcc,0x6a,0x10,0x57,0x9a,0xfc,0x3f,0x5d,0xea,0xc7,0x93,0xcb,
+  0x06,0xb3,0x7a,0x26,0x39,0xe1,0x7d,0xe8,0x46,0xe0,0x6d,0x1c,0xc3,0xb8,0xa3,0xe3,
+  0xad,0xbf,0x75,0x7b,0xad,0xcd,0x35,0xa3,0x26,0xfc,0x63,0x61,0x6d,0x83,0xa8,0xd6,
+  0x7f,0x43,0x2a,0x60,0x7d,0x0c,0x0f,0x5f,0x82,0xf7,0xa0,0x0c,0x07,0xf6,0x11,0x34,
+  0xbd,0xed,0xf7,0xd0,0x5f,0xa3,0x7e,0x9f,0xd8,0x0f,0xd1,0xb4,0x3b,0xe1,0x05,0x44,
+  0x3b,0x84,0xa3,0xc1,0xad,0x13,0xfe,0xb1,0x26,0x44,0x8c,0x38,0x88,0x40,0x6b,0x23,
+  0x02,0x27,0x35,0xbd,0xc7,0xe4,0xff,0xb9,0x01,0x56,0x1b,0x61,0x20,0x4b,0x56,0x5d,
+  0x53,0x63,0xdc,0x1f,0xf2,0x78,0xf3,0xf7,0xf9,0xe0,0xca,0x3d,0xc6,0x4f,0xdf,0xd9,
+  0x78,0x42,0x99,0xb8,0x7f,0x1d,0xa5,0x10,0x55,0xdd,0x11,0x8b,0x1b,0xef,0xff,0xbe,
+  0xe0,0xfa,0x24,0x8b,0xfb,0x7f,0x5e,0x65,0xb9,0xba,0x6d,0xb6,0x38,0x40,0xf8,0x99,
+  0x76,0x5a,0xc4,0x8d,0xa6,0xf8,0x57,0x3b,0x1e,0xc3,0xbd,0x6c,0xc9,0xe8,0xa4,0x4b,
+  0xea,0x55,0xad,0xd2,0x58,0x16,0x5f,0x6c,0x7d,0x6a,0x4e,0x2a,0x57,0xe0,0x15,0x86,
+  0x40,0x68,0xd0,0x84,0x7f,0x86,0xe1,0x6d,0x5c,0x8d,0xc5,0x61,0xd1,0xc9,0x0e,0x55,
+  0x77,0xf7,0xde,0x1c,0x16,0x3f,0x51,0xdf,0x71,0xf1,0x78,0x22,0xae,0xcf,0x9f,0xfc,
+  0xa5,0xd5,0xb6,0x68,0x8a,0xff,0xa7,0x1d,0xd6,0x91,0xad,0x3c,0xc8,0x55,0x61,0x5f,
+  0xaf,0x1a,0xd2,0xf2,0x24,0xdb,0xe5,0x28,0xd6,0x17,0x71,0xc1,0xf2,0x98,0x90,0xaf,
+  0xb5,0x8d,0x16,0x99,0xfd,0x3f,0xdd,0xf0,0x4b,0xee,0xf6,0x29,0xf7,0x3c,0xcd,0x9e,
+  0x0b,0x26,0xfd,0x3f,0xa7,0x70,0x70,0x04,0x11,0xe0,0xfd,0x3e,0xb9,0x8e,0x34,0x98,
+  0xf0,0x4f,0x44,0xf3,0x07,0xd4,0x51,0x4b,0x97,0x79,0x3d,0x63,0xfe,0x1f,0xfb,0x80,
+  0xd6,0xa8,0x75,0x34,0xc8,0xbf,0xb0,0x98,0xfd,0x3f,0x7b,0xe0,0x5d,0xa9,0x74,0xe7,
+  0xac,0x11,0xb9,0x0b,0x5e,0x80,0xb8,0xff,0xe7,0x6d,0x30,0xe4,0xed,0xdb,0xf0,0x2e,
+  0x2d,0xed,0xb0,0x0d,0x8b,0x8f,0x9a,0xf0,0x0f,0x6a,0x7f,0x65,0xbf,0x94,0xb9,0xca,
+  0x70,0x83,0x70,0xb7,0x0f,0x9e,0xee,0x98,0xff,0x47,0x3c,0x2d,0x8d,0xd1,0xca,0x6c,
+  0xdb,0xea,0x14,0xfc,0x73,0x86,0x1d,0xc8,0xee,0xae,0xce,0x0a,0x6e,0x95,0xc8,0x87,
+  0xd0,0x6d,0xd8,0xfb,0x92,0x61,0xef,0x73,0x7d,0x77,0x40,0xad,0xd4,0x9c,0x1b,0x44,
+  0x8f,0x09,0xff,0xdc,0x01,0x8d,0xcc,0xae,0xd1,0x8d,0xa4,0x90,0xb6,0x4c,0xf8,0x1f,
+  0x6e,0xe3,0xfe,0x1c,0x43,0x11,0x7b,0x4a,0x1e,0xa1,0x4f,0x5b,0x54,0x13,0xfe,0x29,
+  0x44,0xed,0x8c,0xf6,0xd4,0x06,0xb2,0x1c,0xb6,0xa4,0x9b,0xfd,0x45,0xc6,0xfc,0x0c,
+  0xee,0x1a,0x22,0x66,0xff,0x8f,0x84,0x9b,0x50,0xf5,0xd2,0x5c,0xcb,0xed,0x06,0x30,
+  0x90,0x15,0x77,0xdc,0x1f,0xa2,0xe0,0xfc,0x46,0xcd,0x39,0x08,0xb9,0xd9,0xc4,0x84,
+  0x7f,0x7c,0xb8,0x0d,0xdd,0xc2,0xdd,0xac,0xc6,0x47,0x87,0x05,0x37,0xac,0x9f,0xf0,
+  0x3f,0x18,0x8e,0x08,0x8e,0x7f,0x16,0x33,0x31,0xcb,0xe4,0xff,0x39,0x49,0x7f,0x07,
+  0x55,0x5e,0xdb,0x79,0xf1,0x99,0x98,0xdb,0x27,0x18,0xc3,0x3f,0x7c,0xf0,0x39,0xb9,
+  0x5c,0x8b,0x3f,0x1d,0xaf,0x79,0xd6,0x84,0x7f,0x8e,0xa3,0xed,0xe1,0xae,0xcd,0xf2,
+  0xca,0x08,0x0b,0x35,0xb7,0xd7,0x16,0xac,0x19,0x32,0xe2,0x83,0x7c,0x7d,0xd8,0x9f,
+  0x7c,0xa5,0x8b,0xac,0xc7,0x9a,0x5e,0x37,0xe1,0x9f,0x28,0x84,0x55,0xfb,0x94,0xba,
+  0x55,0x44,0x45,0x79,0x5b,0xc6,0xfd,0x3f,0xa7,0xa0,0xc7,0x1b,0x1f,0x04,0x7c,0xf6,
+  0x3c,0xfa,0x2c,0x39,0x62,0x92,0x3f,0xfd,0xb0,0x3b,0xd3,0x59,0x67,0x51,0xfc,0xb7,
+  0xbb,0x36,0x68,0x6a,0x35,0xbe,0xe6,0x6b,0xf8,0xbe,0x2a,0x7f,0xdf,0x37,0x60,0x83,
+  0xae,0x7a,0xea,0x14,0x7f,0x9f,0x19,0xff,0x18,0xab,0x47,0x37,0x66,0xe1,0x42,0xa1,
+  0x3c,0x8f,0xaf,0x67,0x7c,0xd0,0x22,0xd8,0x3d,0x34,0xe8,0x79,0xdd,0x84,0x7f,0xce,
+  0xc0,0x59,0xa8,0xac,0xbe,0x7b,0x73,0xc1,0x72,0x78,0x2b,0xfe,0xd8,0xd2,0x38,0x79,
+  0x38,0xee,0xe8,0x63,0x28,0x1f,0x36,0x8b,0xc3,0x26,0xfd,0xdb,0xc9,0xc6,0x83,0xe1,
+  0x7a,0x9b,0x92,0x13,0x77,0x03,0xf2,0x69,0x67,0x63,0x83,0x7e,0xed,0xac,0xba,0x6f,
+  0xe1,0xac,0xcd,0x26,0x7d,0x87,0xf8,0x87,0x0d,0x53,0x03,0xed,0xf8,0x70,0xb5,0x39,
+  0xfe,0x14,0x63,0xf8,0x33,0xe6,0x88,0x63,0x6e,0x65,0x31,0xdb,0xda,0x6a,0xc2,0x3f,
+  0xb7,0xb9,0xd6,0x69,0x7e,0x46,0xa3,0x68,0x7f,0xbd,0x00,0x76,0x96,0x16,0xf3,0xff,
+  0xcc,0x8b,0x39,0x82,0xd6,0xa5,0xa1,0xc6,0x1f,0x21,0xad,0x26,0xfc,0x73,0x97,0x71,
+  0x4c,0x68,0x79,0xba,0x95,0xb4,0xf1,0xb0,0xc5,0x84,0xbf,0x82,0x1f,0x1c,0xb2,0x81,
+  0xa9,0x0d,0x54,0x49,0x6f,0x35,0xe1,0x9f,0x4a,0x58,0xad,0xe1,0xfc,0x06,0xff,0x54,
+  0xb6,0x55,0x99,0x39,0x7c,0x7d,0xd2,0xff,0x83,0x82,0x6e,0x0d,0x0f,0xa4,0x5a,0x49,
+  0x57,0xe2,0xfe,0xdb,0xe8,0x34,0xb4,0x5f,0x66,0x23,0xec,0xb1,0x64,0xa9,0x6f,0x84,
+  0x76,0x8c,0x64,0x72,0xff,0xcf,0x67,0xec,0x56,0x0e,0x7b,0xde,0x55,0x4e,0x72,0x20,
+  0xb4,0xb4,0xe6,0x05,0x13,0xfe,0xd9,0xc6,0xbd,0xaf,0x7f,0xc0,0xd3,0xb7,0x4d,0x7f,
+  0xa7,0xbe,0xcc,0xe4,0xcf,0x0f,0x8b,0x03,0x93,0xae,0x40,0x15,0xb3,0xe9,0xa2,0xc7,
+  0x84,0x7f,0xae,0x48,0x3f,0x67,0xf3,0xa3,0xb6,0xdd,0xa5,0x3f,0xa3,0x47,0x59,0xe9,
+  0x69,0x1b,0xc7,0x3f,0x57,0xf9,0x95,0x1e,0x1c,0xfc,0x69,0x53,0xd5,0x72,0x5b,0x4f,
+  0x8d,0x6e,0xf2,0xff,0xe4,0xb1,0x57,0x82,0xf9,0x43,0x6d,0x17,0x3c,0x95,0x6c,0x0d,
+  0xe4,0x1b,0xfe,0x1f,0x6d,0x07,0x7f,0xfe,0x47,0x71,0xb0,0xaa,0xbc,0xf8,0x6e,0x79,
+  0x66,0x8e,0x09,0xff,0xc0,0xe6,0xb4,0x5d,0xf0,0xbc,0xde,0xd6,0x40,0xee,0xf3,0xaf,
+  0x49,0xfa,0x7f,0x70,0xfe,0xc3,0xf8,0xbe,0xcd,0x88,0x88,0x65,0xaf,0x3d,0x05,0xff,
+  0x20,0x9a,0x42,0xb1,0xa3,0xfa,0xad,0x28,0xc6,0x93,0xf1,0x8e,0x5e,0x1c,0x1c,0x66,
+  0x7e,0xea,0x6c,0x91,0xe7,0x90,0x48,0x62,0x7f,0x76,0x4d,0xf9,0x2d,0x82,0x9c,0xf9,
+  0xba,0x6d,0x4f,0xc1,0x4f,0xe0,0xa8,0x50,0x1a,0x13,0x9b,0xb1,0xf7,0x15,0x06,0xa0,
+  0x85,0x55,0x36,0xd8,0x7e,0xbd,0x35,0xf9,0x3c,0x8c,0xfb,0x7f,0xa0,0xf2,0xb4,0x2d,
+  0x5c,0x33,0x20,0xc5,0xd5,0xdc,0x40,0x2c,0x1e,0xc1,0x1d,0x65,0x1f,0xf3,0x83,0xc6,
+  0x4c,0xf1,0x2f,0x01,0x45,0xf6,0x55,0x68,0xd2,0x9d,0x0d,0xe2,0x3e,0xcb,0x22,0x04,
+  0x42,0x1c,0xf6,0xa0,0xfe,0x9a,0x8b,0xf2,0xbc,0xe0,0x12,0x0c,0xf0,0xf5,0xf4,0x8a,
+  0x90,0x88,0x7f,0x35,0x4a,0x0f,0x42,0xb8,0x19,0xf5,0x3b,0x23,0x4e,0x90,0xb9,0xe2,
+  0xe6,0xfa,0xf7,0x45,0xc9,0x1d,0x73,0xec,0x74,0xbd,0x5e,0xe2,0x96,0x03,0x08,0xe4,
+  0x4c,0xfe,0x1f,0xb6,0x97,0x39,0xf4,0xba,0x6e,0xcf,0x36,0x5a,0x80,0xef,0x9b,0xc7,
+  0xa7,0xb5,0xc1,0x8c,0xd8,0xfc,0xdd,0xbd,0x25,0x3e,0xb9,0xa7,0x43,0x35,0xc9,0x1f,
+  0x0a,0x7b,0xa9,0x1a,0xe1,0xde,0x0f,0x86,0x1b,0x6f,0x90,0xfb,0xe7,0x25,0x43,0x50,
+  0xbb,0x71,0x7e,0x08,0xf0,0xbf,0x9a,0x9e,0x9e,0x94,0x3f,0x90,0xb9,0x1c,0x57,0x63,
+  0xbe,0xbe,0xb8,0xdb,0xb3,0x4f,0xfd,0x0b,0x94,0x0e,0x5a,0x0d,0xfd,0xab,0xe0,0xc6,
+  0xe8,0x6e,0x1a,0x99,0x8c,0x82,0xb4,0xda,0xb6,0xba,0x0d,0x12,0xf2,0x27,0x94,0x39,
+  0x86,0xf3,0xf7,0x0f,0xda,0x86,0x70,0xda,0x7b,0x50,0xd9,0x2f,0x4f,0xf8,0x7f,0x96,
+  0x8c,0x8a,0x27,0x15,0xae,0xf3,0x71,0xff,0x0c,0x27,0xe3,0x5f,0x69,0xfc,0xd7,0x52,
+  0xbd,0x78,0x54,0xae,0xe4,0xdb,0x26,0x92,0xf9,0xd9,0xab,0x3f,0x83,0xab,0xae,0xb9,
+  0x3e,0x9b,0x2e,0x8c,0xe2,0x89,0x2b,0x05,0x6b,0x5f,0x93,0x19,0xff,0x7c,0xa2,0xed,
+  0x69,0x42,0xf9,0x3c,0x46,0x4a,0x60,0xaf,0x5a,0xf4,0x7b,0x7a,0x1e,0x07,0xaf,0xf8,
+  0xe6,0x68,0xf2,0x6a,0x32,0x4b,0x0b,0xe8,0xf6,0xa0,0xe5,0x59,0xbb,0x19,0xff,0x0c,
+  0x48,0x3b,0x04,0x55,0x6f,0x51,0xb8,0xb7,0x87,0x3a,0x06,0x32,0xdc,0x68,0x86,0xef,
+  0x50,0x0a,0x35,0x39,0xd7,0xaf,0x01,0xab,0x56,0x95,0x3c,0x78,0x99,0x98,0xf0,0xcf,
+  0x36,0xd8,0xdb,0xbc,0xac,0x16,0x85,0xb6,0xd3,0x08,0x7b,0xa1,0x21,0xe6,0xa4,0x37,
+  0xc2,0x0c,0x9f,0xbc,0x89,0x94,0x08,0xad,0xcd,0xcb,0x1a,0xb3,0xbb,0x56,0xa7,0xc4,
+  0xbf,0xa4,0x8b,0x2c,0xac,0x65,0xf6,0xc8,0x4e,0x63,0xdb,0x64,0xf2,0x78,0xf1,0x45,
+  0x28,0xd3,0x6c,0x9b,0xe4,0xef,0x91,0x43,0xba,0x7b,0xbb,0xb5,0x5d,0x84,0x64,0xfc,
+  0x0b,0xf6,0xc5,0xd0,0xd1,0x6e,0x63,0x59,0xf6,0xf7,0xc6,0xfd,0x81,0x55,0x1a,0x22,
+  0x46,0xbe,0x91,0xf6,0x6f,0xb0,0x35,0xc8,0xa9,0xf1,0xaf,0x8f,0x89,0x9b,0x9b,0xed,
+  0xfc,0xfe,0x65,0xfa,0x5d,0xae,0x1a,0x1e,0xff,0x9a,0xa7,0x65,0xb9,0x26,0x7d,0x08,
+  0xef,0xf8,0xf6,0x04,0x9d,0x3b,0x45,0x13,0xfe,0x91,0x2a,0x59,0x93,0xb7,0xe3,0x34,
+  0x5a,0xeb,0x4e,0xdc,0xf6,0x05,0xbd,0x75,0xa3,0x46,0xfc,0x0b,0x57,0xac,0x3b,0xfb,
+  0x53,0xd6,0xba,0xd0,0x1e,0xa0,0x7b,0x6a,0xba,0x4d,0xf8,0xe7,0x2e,0xb6,0x95,0x15,
+  0x7a,0x8a,0x14,0xbe,0x2c,0xec,0x59,0x3d,0x2f,0x7e,0x5e,0x34,0x44,0x2c,0x01,0xc1,
+  0xdf,0x5b,0x42,0x64,0xbb,0x29,0xff,0xc7,0x87,0xf2,0xe7,0x97,0xa1,0xe9,0xcb,0xe9,
+  0x52,0xcf,0x34,0xd8,0x15,0x88,0xa7,0xc1,0xec,0x62,0xf9,0x3e,0x5a,0xef,0x79,0x97,
+  0x6e,0x0a,0x4d,0xbf,0xff,0xc6,0x1f,0xa4,0xb7,0x27,0xfd,0x3f,0x75,0xce,0xe6,0xf7,
+  0x2d,0x73,0x6a,0x71,0xdb,0x5a,0xe9,0x67,0x30,0x47,0x2f,0x46,0xfc,0xa3,0x7d,0x86,
+  0xe7,0x31,0xcb,0x25,0xf4,0x92,0x63,0x7a,0x45,0x70,0x3d,0xa4,0xe4,0xff,0xe0,0xfb,
+  0xaa,0xf3,0x6b,0x27,0x8d,0xe5,0x5c,0x82,0x2f,0xf9,0x42,0x9d,0xe5,0xf1,0x2f,0x8e,
+  0x7f,0x76,0x8a,0x63,0xf0,0x17,0xdc,0x8a,0x78,0x82,0x4c,0xf8,0x67,0xca,0xa7,0xda,
+  0xef,0x71,0x59,0xd6,0x05,0xd7,0xac,0xc0,0x65,0x71,0xf3,0x83,0x8c,0x0b,0x85,0x86,
+  0x30,0xce,0xaf,0xe7,0x8e,0x5c,0x6e,0xaf,0x99,0xf1,0xcf,0x3e,0xb6,0x0a,0x0a,0xf4,
+  0x3a,0x6f,0xf6,0x54,0x09,0x05,0x4b,0x44,0x3e,0xbf,0x71,0x2a,0xec,0x72,0xdc,0x5a,
+  0x2d,0x47,0xc5,0xfb,0x94,0x5d,0xb0,0x45,0x97,0x7d,0xa9,0xf1,0x2f,0x54,0xb9,0xd3,
+  0x11,0xff,0x90,0x69,0x14,0x5f,0x73,0xe8,0xc9,0x47,0xc9,0x34,0xd8,0xf1,0xcb,0x7c,
+  0x9f,0xbc,0x72,0xf5,0x34,0xfe,0xe2,0xef,0x2f,0x2a,0x4f,0x77,0xa5,0xf8,0x7f,0x9a,
+  0x34,0xfb,0x50,0xcc,0xff,0x6c,0xf8,0xf3,0x2d,0x56,0xdc,0x48,0xcb,0x7d,0x72,0x37,
+  0xb9,0xab,0x7a,0x87,0x57,0x1d,0x95,0xe7,0x98,0xe3,0x5f,0x88,0xdf,0x5e,0xa7,0x65,
+  0x88,0x76,0x6c,0x75,0x70,0x0e,0xdc,0x8d,0x99,0x21,0xd1,0xc1,0x23,0x7a,0x5d,0xeb,
+  0x43,0xe2,0x3c,0xf8,0x82,0x95,0x06,0x6d,0x23,0x93,0x52,0xe2,0x5f,0x64,0xf8,0xce,
+  0x4a,0xc8,0x02,0x31,0x94,0x84,0x01,0x7c,0xb0,0xa4,0x59,0x8c,0xaa,0x88,0x7f,0xc0,
+  0xd6,0x68,0xc6,0x3f,0x70,0x26,0x63,0xbc,0xba,0xc3,0xdb,0x15,0x94,0xb9,0xb7,0xc7,
+  0x8e,0x6a,0xee,0x5b,0x43,0x78,0x6c,0xcb,0x34,0x67,0x58,0x9c,0xc1,0xc6,0x25,0xf7,
+  0x42,0x5b,0x9e,0x29,0xfe,0xc5,0x6a,0xff,0x2c,0xec,0xf6,0xd9,0x1f,0xc6,0xfd,0x5f,
+  0xa8,0x3c,0xaf,0xd9,0xb5,0x2c,0x43,0xff,0x0a,0x68,0x71,0x6f,0xcc,0xee,0xa4,0xbb,
+  0x49,0xc7,0x43,0x59,0x9b,0x89,0x09,0xff,0x48,0xcf,0x34,0xf3,0xe8,0x8c,0x25,0x98,
+  0x5e,0xa8,0xb5,0x68,0x2f,0x24,0xf1,0x0f,0xe5,0x19,0x2f,0xbb,0xab,0x11,0x11,0xfd,
+  0x32,0x05,0xff,0xa4,0xe1,0xaf,0x0e,0xef,0x0d,0x4a,0xba,0x04,0x5b,0x34,0xea,0xb5,
+  0xe4,0xf2,0x78,0x50,0x6d,0x11,0x22,0xa2,0xf4,0xe6,0x8c,0xed,0x82,0xca,0xaf,0x98,
+  0xf0,0x4f,0x86,0x0f,0x7a,0x60,0x9e,0x25,0x8b,0xa7,0xd9,0x70,0x47,0x84,0x81,0x7f,
+  0x78,0xbc,0x09,0x15,0xb1,0x4a,0x57,0x42,0x37,0x5b,0xc2,0xe4,0x94,0xf8,0x97,0x74,
+  0xb9,0x7a,0xae,0x96,0x36,0x68,0x84,0x75,0xca,0xbc,0xeb,0x36,0xf1,0x81,0x36,0x17,
+  0xcf,0xa3,0xf8,0x39,0xfd,0x5c,0xab,0xf2,0x66,0x1d,0x37,0xfb,0x7f,0x84,0xf3,0x70,
+  0xd8,0x31,0xf7,0xef,0x96,0x6c,0xac,0x39,0x9f,0x7b,0xb9,0x16,0xb7,0xcd,0x2f,0x79,
+  0x60,0xc8,0x37,0x4f,0xb3,0xfd,0x41,0xd8,0x09,0x87,0xd5,0xd2,0xc5,0xf0,0x7b,0x71,
+  0x86,0x39,0xff,0xc7,0x1e,0x20,0x76,0x2a,0xaf,0x42,0x23,0x74,0xa7,0xda,0x41,0x65,
+  0x3f,0xae,0x46,0x8f,0xcf,0x6e,0xb1,0x3d,0x6b,0xc9,0xc7,0x27,0xec,0xd8,0x5c,0xb7,
+  0xc6,0x92,0x95,0x58,0x4f,0xb8,0xbd,0xbf,0xbf,0x05,0x9c,0x4b,0x65,0xc5,0xc3,0x61,
+  0x9e,0xea,0x91,0x73,0x49,0x33,0x6c,0xd7,0xd0,0x02,0xcd,0x4d,0x4f,0x83,0xc6,0x5a,
+  0x5c,0x58,0x85,0x10,0x33,0xfe,0x11,0x5a,0xaa,0xf9,0x32,0xa2,0x99,0xb9,0x1d,0xec,
+  0xd5,0x3c,0x4c,0x06,0xdb,0x85,0x65,0xda,0x22,0x1e,0x61,0xcc,0xc0,0x2f,0xa8,0x6c,
+  0x20,0xe9,0x49,0xfc,0xa3,0x74,0xe6,0x1e,0x60,0x3f,0xd3,0x96,0x24,0x61,0x5b,0x01,
+  0x3e,0xbf,0x34,0xef,0xf6,0x45,0x9b,0xc5,0x19,0xfa,0x81,0x90,0xbb,0xa1,0xf0,0x69,
+  0x31,0x99,0xff,0xf3,0x02,0xe0,0xaf,0xed,0x28,0x9d,0x9e,0x2a,0x8d,0x87,0xbd,0x94,
+  0x9a,0xd8,0x20,0xeb,0x49,0x71,0xc8,0xf2,0xa1,0xbd,0xa2,0x76,0x52,0x7b,0x4e,0x0a,
+  0xfe,0x51,0x23,0x9a,0x1b,0x8d,0x47,0x91,0xc7,0x1f,0xdd,0x42,0x7c,0xbf,0x95,0x41,
+  0x66,0xba,0x98,0x2f,0x8d,0x79,0xdc,0xd4,0xda,0x68,0xf6,0xff,0x48,0xb7,0xb9,0x5e,
+  0xd7,0x9a,0x98,0x25,0x54,0x5a,0x04,0xad,0xac,0xac,0x51,0x0e,0xb9,0x87,0x63,0x81,
+  0xb0,0x21,0xd2,0x1a,0x7c,0x19,0xb6,0x32,0x3a,0x64,0xf6,0xff,0x34,0xaf,0x90,0x1e,
+  0xd7,0x0d,0x37,0xec,0x1d,0xf0,0x78,0x48,0x35,0xcc,0x04,0x69,0x87,0x84,0xf8,0x47,
+  0xc5,0x2b,0x3b,0xd4,0xc2,0x7b,0x17,0xed,0xf4,0x9b,0xe2,0x5f,0xd5,0x14,0x9a,0x68,
+  0xfe,0x69,0xcb,0x4a,0x72,0x9d,0xba,0x8a,0x4e,0xe7,0x30,0x00,0xf1,0x00,0x99,0x8e,
+  0xc0,0xc0,0xcf,0x81,0x01,0xfe,0xc3,0x06,0x18,0x36,0xc5,0xbf,0xee,0x81,0x3f,0x22,
+  0xc8,0xb1,0x96,0xcb,0xdf,0x85,0x3f,0x04,0x66,0x47,0x6d,0x3f,0x46,0xfc,0x73,0x35,
+  0x70,0xeb,0x70,0xe6,0xb0,0xf8,0x5d,0xe9,0x4b,0x36,0xc5,0x37,0xab,0xde,0xec,0xff,
+  0xb9,0x3e,0x9c,0x77,0x51,0xd8,0xcf,0xfd,0xf3,0x03,0x30,0xa6,0x55,0xf6,0xdb,0x5e,
+  0xe2,0x78,0xc0,0x3b,0xef,0x24,0x47,0x44,0x5c,0xf0,0xf6,0x6e,0x36,0xfb,0x7f,0xb4,
+  0xb4,0x0b,0xda,0x55,0x56,0x15,0xb5,0xf6,0x88,0xd7,0xc1,0x07,0x71,0xd8,0xa3,0x5d,
+  0x64,0xa5,0xa3,0xd6,0x61,0x52,0xa9,0x1d,0xda,0x38,0xb9,0xf0,0xbe,0x1e,0x53,0xfe,
+  0x67,0xd7,0xe4,0xa7,0x60,0x57,0xa8,0x38,0x80,0x30,0x2c,0x17,0xfe,0xa7,0x92,0xdf,
+  0xdf,0xb6,0xd2,0x8e,0x8f,0x1d,0x9e,0xdb,0x9f,0xb9,0x10,0xa6,0xde,0xb3,0xa6,0x33,
+  0x7f,0x60,0xe9,0x22,0x62,0xc6,0x1b,0x41,0x6d,0x97,0x5a,0xec,0x47,0x7b,0xed,0x5e,
+  0x78,0xc6,0x80,0x79,0xd9,0x27,0x15,0x1e,0xff,0xa2,0xf6,0xac,0xa9,0xda,0x13,0xe4,
+  0x7d,0xed,0xb6,0xef,0xe1,0x09,0x9a,0x58,0x7f,0x5f,0xae,0x8f,0xe7,0x56,0x36,0x66,
+  0xb8,0xdc,0x12,0xcf,0x1f,0x8b,0xe3,0x1f,0xa1,0x50,0xcf,0x90,0xd2,0x6d,0xbe,0xc7,
+  0xeb,0xd4,0xc1,0xeb,0xb7,0x5d,0xf7,0x76,0xc2,0x3f,0xc9,0xf3,0xb5,0xc6,0xa5,0x4a,
+  0xcd,0x1a,0xbe,0x65,0x39,0x02,0xd1,0xf9,0xdc,0xde,0x1c,0x31,0x34,0xb2,0xb5,0x53,
+  0x2c,0x81,0xdf,0xab,0x6e,0x5f,0x46,0x8f,0x78,0xd0,0xf4,0x3c,0x51,0x18,0xf7,0x56,
+  0x2a,0x86,0x5b,0x0c,0xb7,0x4d,0x2f,0x87,0x3d,0x4a,0x1c,0x08,0x8d,0x28,0x1f,0x42,
+  0x65,0xf4,0xee,0x5d,0xf8,0x53,0x12,0xff,0x8c,0xc2,0x6b,0x74,0x7e,0x48,0x0a,0x4f,
+  0x3a,0xaf,0x5d,0xd1,0x0d,0xfc,0xb3,0x0f,0x7e,0x6e,0xe4,0x7b,0x34,0x3d,0x20,0x5c,
+  0x15,0x4a,0xfb,0x6c,0xa3,0x72,0x28,0x71,0x5e,0x7a,0x61,0x19,0x69,0x61,0x76,0xd5,
+  0xc1,0xa3,0x69,0x3d,0xd0,0x81,0xfa,0xd4,0x50,0xc4,0x3f,0xc3,0xfd,0x60,0x71,0xd2,
+  0xdd,0x8d,0xf6,0x21,0x79,0x8f,0x18,0x32,0xe1,0x1f,0xbb,0xd0,0xa2,0xff,0xf0,0x84,
+  0x25,0x9c,0x3d,0x64,0xc4,0xbf,0x22,0x2e,0xb2,0x4d,0xda,0x9b,0x56,0xa2,0x23,0xde,
+  0x76,0x66,0xbc,0xd8,0x6b,0x57,0x6e,0xec,0x9a,0x11,0x32,0xc9,0x1f,0x42,0x1b,0x55,
+  0x95,0xa1,0x76,0x6b,0xe6,0xe7,0x51,0xbf,0xde,0x85,0x40,0x71,0x87,0xea,0xd0,0x45,
+  0x42,0xac,0xc2,0x76,0x97,0x0a,0xbf,0x22,0x66,0xfc,0x63,0x55,0x03,0x2d,0xea,0x3c,
+  0x96,0x15,0xf6,0x73,0xb7,0x4f,0x37,0x7f,0xfe,0x6d,0xf0,0xa5,0x63,0x16,0x4f,0x73,
+  0x72,0xc2,0xc7,0x3c,0x22,0xec,0x6f,0x0a,0x25,0xf1,0xcf,0x4d,0xd1,0xda,0x71,0x65,
+  0x01,0x7b,0x60,0xb4,0xe0,0xbc,0x74,0x19,0xaa,0x7a,0x93,0xf1,0xaf,0x46,0xf1,0x92,
+  0x74,0x5e,0xe3,0xf8,0xb9,0xa0,0xcb,0x84,0x7f,0x2e,0xc0,0x09,0xa9,0x72,0xd0,0x79,
+  0x3e,0x67,0x85,0xf4,0xde,0x86,0xb2,0x53,0xeb,0x7f,0x2c,0xba,0xc9,0xd1,0x6c,0x23,
+  0x7e,0x7a,0x3e,0x34,0xe0,0x2e,0xc8,0x5f,0xfc,0x6a,0x8e,0xcb,0x14,0xff,0xfa,0x08,
+  0x41,0xe9,0xac,0x41,0xfa,0x85,0x7d,0x41,0xf3,0x8b,0x50,0x14,0xcd,0xea,0x26,0x33,
+  0x60,0x7d,0x03,0x4f,0x04,0xf2,0x7c,0x10,0x6e,0x7f,0xc4,0x1e,0xa2,0xab,0x89,0x2b,
+  0x11,0x7f,0x8f,0xa0,0xfd,0xc5,0xc0,0x79,0x82,0xce,0x21,0x77,0xa9,0x4d,0xaa,0x11,
+  0x5f,0x1e,0xca,0x6d,0x52,0x63,0xf6,0x45,0x63,0x50,0xb0,0x03,0x15,0x88,0xdb,0x14,
+  0xff,0xfa,0x17,0xd2,0xe2,0x2f,0x41,0xd8,0x63,0x5f,0x81,0xfb,0xa1,0xa8,0x17,0xf1,
+  0xe7,0x19,0x04,0xd2,0x06,0x9e,0xfc,0x94,0x3c,0xc5,0xec,0x8c,0xb6,0x13,0x57,0x32,
+  0x3f,0x79,0xf2,0x47,0x10,0x89,0x54,0xea,0x8b,0xc3,0xf2,0x0a,0x84,0xb5,0x65,0xb8,
+  0x1f,0x6a,0x1e,0xe4,0x03,0x7d,0x52,0x58,0xfc,0xb3,0xe3,0x40,0x9f,0x2b,0x7b,0xf1,
+  0x66,0x51,0x31,0xc5,0xbf,0x7a,0xd4,0x71,0xbe,0x2c,0x61,0xdc,0x06,0x7c,0x59,0xe4,
+  0xf3,0xa4,0x02,0x07,0x7b,0x39,0x3e,0x1c,0xc2,0xcd,0xf5,0x4a,0x64,0x89,0x26,0x0f,
+  0x9b,0xe2,0x5f,0xdb,0xb8,0x76,0xd3,0xd7,0x86,0xc5,0xb5,0xf4,0x1d,0x63,0x9b,0xdd,
+  0xe8,0x94,0x0e,0x49,0x71,0xff,0xcf,0x30,0x5f,0xff,0xb0,0x19,0xff,0xa4,0x65,0xb1,
+  0xdd,0x6a,0x81,0x4e,0x47,0xc5,0x9f,0xe0,0x7c,0xdc,0x06,0x3d,0xa8,0x88,0xd7,0x4b,
+  0x86,0x23,0xe8,0xe3,0xbe,0xc0,0x52,0x1c,0xfc,0xda,0x94,0xff,0x8c,0xf8,0x07,0xc2,
+  0x43,0x33,0x38,0xcc,0x5b,0x8b,0xaf,0xe9,0xd4,0x33,0xb6,0x27,0x1d,0x17,0x51,0xd4,
+  0x2e,0x68,0x98,0x3b,0x96,0x9d,0x4d,0xe8,0xbb,0x51,0x01,0x95,0xbe,0xdf,0x37,0x44,
+  0x1f,0x25,0xdf,0x5d,0xf5,0x04,0x4f,0x83,0x59,0x49,0x2a,0xd1,0xc2,0x9a,0xce,0x07,
+  0x6f,0x6b,0xbf,0x60,0xd3,0x55,0xb9,0x8e,0x5c,0x49,0x9c,0xaf,0x3b,0xa9,0x55,0x1a,
+  0x0d,0x3f,0x32,0xb2,0xb8,0x5c,0xfe,0x2d,0xbc,0x2a,0x54,0x8c,0xac,0x77,0x89,0x56,
+  0xf8,0x18,0xc2,0xba,0x6d,0xbe,0x18,0x81,0xcf,0xb4,0x39,0x77,0xd8,0x2a,0x9a,0x7e,
+  0x4f,0x26,0xe6,0x6b,0x37,0xf1,0x65,0xb1,0x45,0xe4,0xd1,0xa6,0xd8,0xfa,0xe0,0xfe,
+  0x39,0x49,0xde,0xa1,0xf3,0x0c,0x47,0x10,0x41,0xfc,0x03,0xb6,0x0d,0xe2,0x60,0xe2,
+  0x3c,0xf2,0xf8,0xd7,0x25,0xa8,0x7c,0x0b,0x61,0xf9,0x8a,0xc8,0xa1,0xd8,0x31,0x74,
+  0xc2,0xa1,0xe5,0x95,0xb1,0x7c,0xbc,0xdf,0x08,0x25,0x7f,0xc4,0xfd,0x46,0x92,0xf9,
+  0x9f,0x1b,0x36,0xa3,0xb4,0x2c,0x3e,0x1e,0x98,0x5d,0x64,0x55,0xd7,0x40,0x31,0xca,
+  0x13,0x71,0x2a,0x59,0xe3,0xb8,0x8d,0xfb,0x7f,0x4e,0xc0,0x2a,0x7e,0x45,0xb7,0xb8,
+  0x4d,0xfe,0xde,0xa7,0x1d,0xbb,0xf4,0x99,0xc3,0x1c,0xe6,0x65,0x3c,0x67,0xbc,0xaf,
+  0xe5,0x0a,0xc4,0x5f,0xfc,0xa0,0xb2,0x6a,0x75,0x71,0xb4,0x6d,0x25,0xc9,0x33,0xe1,
+  0x9f,0x23,0x46,0xf6,0x42,0x1d,0x1e,0x43,0x61,0x2f,0x77,0xfb,0xb4,0x13,0x5b,0xe1,
+  0xe3,0xb1,0xc4,0x86,0x61,0x7f,0x8b,0xb6,0x62,0x50,0xde,0x40,0x6e,0x48,0xf1,0xff,
+  0x5c,0x61,0xf3,0x78,0x92,0xf3,0x30,0xf9,0x28,0xe6,0xf6,0x59,0xa9,0xc6,0xfd,0x3f,
+  0xe3,0xec,0xc8,0xd2,0xca,0x6e,0xdb,0x08,0x02,0xa1,0x89,0xe7,0x37,0xfc,0x3f,0xbd,
+  0x3c,0xdb,0x59,0xf0,0x49,0xdc,0xfb,0xb1,0xa4,0x11,0x81,0x50,0x2c,0x10,0x26,0x46,
+  0x09,0x4a,0x6c,0x6a,0xf8,0x7f,0x26,0x9e,0x9f,0x2a,0x67,0xb4,0x03,0xfe,0x79,0x5a,
+  0x49,0xf0,0xc6,0xc2,0xb8,0x7e,0x34,0x80,0x90,0x1b,0x35,0xac,0xf8,0x67,0x38,0xc0,
+  0xdc,0xb5,0xb6,0x8d,0x84,0x24,0x9e,0x9f,0xfb,0x7f,0x5a,0xee,0xcc,0xd2,0x78,0xb4,
+  0x0b,0x5a,0x24,0x44,0x2f,0x9b,0xb2,0x25,0x69,0xc2,0x11,0x64,0x6f,0xf1,0x76,0xe8,
+  0xf2,0x53,0x29,0xfe,0x9f,0xe9,0xd0,0xa2,0x20,0xfe,0x51,0xee,0x29,0x84,0xe7,0xb9,
+  0x9b,0x62,0x23,0xca,0x2b,0x9e,0x38,0x64,0x09,0x92,0x4e,0xee,0xc1,0xf0,0xe0,0x3f,
+  0x5c,0x97,0xd8,0x6f,0x20,0x15,0xe2,0xaf,0xce,0x6f,0xd2,0x5c,0x82,0xda,0x5f,0x0b,
+  0x55,0xcb,0x53,0xef,0x28,0xe4,0x8e,0x20,0xcd,0x70,0x8c,0x34,0xd6,0x2c,0xd7,0x0e,
+  0xe5,0x66,0xb7,0x26,0xe2,0xef,0xe5,0x99,0x3e,0x88,0x08,0xe5,0x50,0xc2,0x64,0x55,
+  0x19,0x8e,0xb9,0x1d,0x78,0xd8,0xcb,0x08,0xc4,0x44,0xe1,0xa0,0x54,0xc6,0xaf,0xac,
+  0x4b,0xc4,0xbf,0x4e,0xdc,0x74,0xde,0x72,0xb9,0xba,0xd2,0xbb,0xc4,0x08,0x7b,0x71,
+  0xfd,0xee,0x15,0x8f,0x73,0xff,0x4f,0xb5,0x2d,0x28,0x5e,0x86,0xcb,0x1a,0x02,0x9b,
+  0xe3,0xe2,0x3f,0x24,0xf3,0x79,0xd2,0x76,0xc2,0x65,0x07,0x0f,0x1b,0xb5,0x15,0xaa,
+  0x07,0xf8,0xfc,0x41,0x59,0x82,0xb7,0xc0,0xf0,0x9f,0xec,0xd4,0x0e,0xf3,0x2b,0xbf,
+  0x8f,0xa6,0x27,0xe6,0xaf,0x54,0x10,0x7d,0x79,0xec,0x53,0xeb,0x9a,0x49,0x3e,0x04,
+  0xa0,0x44,0x90,0x99,0x47,0xcd,0x38,0x11,0xf7,0xff,0x68,0x01,0x5f,0x09,0xc8,0xcd,
+  0x24,0x2b,0x71,0x1e,0xa9,0x84,0xb0,0x87,0xa9,0x9e,0xfa,0xec,0x3e,0x29,0xd4,0xe8,
+  0xc0,0xd3,0x94,0xbd,0x11,0xdf,0xb7,0xc8,0x78,0xdf,0x7e,0xd6,0x78,0xa7,0xb3,0x5a,
+  0xce,0x26,0xd9,0xc2,0xc4,0xfc,0xbc,0x29,0xcf,0x48,0xbb,0x55,0x23,0xff,0x87,0x3b,
+  0xd6,0x4a,0x34,0x3c,0xb6,0xcb,0xe1,0x49,0x5c,0xd8,0x1b,0x71,0xfd,0x2d,0x6d,0x86,
+  0x63,0xad,0x23,0x3d,0x71,0xff,0xd0,0x64,0xee,0xdd,0x72,0x57,0x5b,0x83,0x62,0x21,
+  0x35,0x9e,0x3f,0x4f,0x4c,0x6b,0x8a,0x01,0xdd,0x9c,0x3f,0xd7,0xb6,0x6c,0xc1,0x2b,
+  0x9b,0xff,0x8b,0xc3,0x14,0xff,0x7a,0x56,0x3b,0x0b,0xfb,0xf8,0x36,0x18,0x22,0xc6,
+  0xfa,0x6c,0x24,0x9d,0x19,0xa7,0x62,0xfe,0x9f,0xd7,0xe9,0xb8,0x13,0x07,0xd9,0xf2,
+  0x39,0x13,0xfe,0xd9,0xa2,0x8d,0x4d,0x9e,0x07,0x25,0x50,0x83,0xeb,0x2f,0x54,0x0a,
+  0x7f,0xcf,0x81,0x10,0x5a,0x59,0xb0,0x8e,0x89,0xa7,0xd4,0x08,0xb8,0x33,0x70,0xfd,
+  0x89,0x39,0xfe,0xa5,0xed,0xf7,0xdb,0x1b,0x29,0xcf,0xff,0x69,0xc5,0xcf,0xb6,0x84,
+  0x3b,0x82,0x5a,0x63,0x89,0x40,0x63,0x70,0x44,0xb3,0x07,0xdb,0x3e,0x20,0x16,0x93,
+  0xff,0xe7,0x1b,0xc2,0x76,0x9f,0x43,0x2f,0x72,0xa5,0x3b,0x63,0xf6,0x42,0x39,0xb1,
+  0x8a,0x4d,0xb1,0xc4,0xb9,0x37,0xa0,0x91,0xf9,0x74,0x39,0x0f,0xe7,0x27,0xfd,0x3f,
+  0x79,0xc2,0x76,0x92,0xff,0x1a,0x37,0x63,0xf5,0x27,0xf8,0x69,0xbd,0x97,0x54,0xd0,
+  0xa6,0x98,0x23,0xf7,0x2d,0xd8,0xd4,0x97,0xaf,0xc9,0xb5,0x44,0x4d,0xc4,0x3b,0xba,
+  0x02,0xd7,0xa5,0xbd,0xc4,0xe6,0x8f,0x94,0xfc,0x4c,0x9c,0x06,0x5f,0x86,0x17,0x44,
+  0xe5,0x31,0x79,0x1a,0xbc,0x31,0xbc,0x20,0x9a,0xb5,0x52,0xfc,0x82,0x1c,0x65,0xdb,
+  0x4f,0xdb,0xc6,0xd0,0xc2,0x9b,0xd8,0x6f,0xf4,0xa6,0x2e,0xbe,0x6d,0x06,0xb3,0x76,
+  0xa2,0x74,0xfd,0x18,0xe5,0x49,0x96,0xc9,0x9f,0x3f,0xa6,0x7c,0xca,0x07,0x51,0xb1,
+  0x2f,0x69,0xff,0xfe,0xe2,0x0b,0xe5,0x32,0xab,0x3a,0x65,0xbd,0x64,0xab,0xd4,0x8e,
+  0x06,0x2a,0xb9,0xda,0xaa,0x84,0xa3,0xec,0x96,0x21,0x1c,0x7c,0x01,0xbf,0xe1,0x89,
+  0x40,0x6f,0x89,0x90,0x38,0x5f,0x3c,0xff,0xe7,0x25,0xa5,0x98,0xe3,0xbd,0xcd,0xfa,
+  0x73,0x80,0x62,0xe4,0x9b,0x6d,0x28,0x7f,0x82,0x5b,0xb8,0x7c,0x18,0xd4,0x8e,0xab,
+  0xf9,0x5a,0x5b,0xc6,0x3d,0x45,0xe9,0x13,0xf3,0x11,0xd1,0x23,0xa8,0x2b,0xee,0x77,
+  0xcc,0x26,0x3c,0xf0,0x37,0x5d,0x6f,0xf5,0x5a,0x2a,0xe0,0x71,0xb8,0x9f,0x7b,0x84,
+  0xee,0x25,0xab,0xa4,0x7c,0x26,0xdf,0x63,0x49,0xe6,0x3f,0x17,0x4a,0x07,0xa5,0xed,
+  0x28,0x76,0xf0,0xfe,0x6b,0x95,0xad,0x5c,0xfe,0xe4,0x91,0x4c,0xf8,0x55,0x4c,0x9e,
+  0x1f,0x80,0xa7,0x42,0x2a,0x93,0x0b,0x49,0x5d,0xf2,0x79,0xd2,0x3a,0x83,0xe3,0xbd,
+  0x55,0xfa,0xe2,0xd1,0x9c,0x0a,0x38,0x1a,0x7b,0xcd,0x62,0x78,0x2f,0x16,0x5f,0xf8,
+  0x00,0x0e,0x44,0xdd,0x41,0xb9,0xbd,0xe9,0x87,0x66,0xfc,0xa3,0x8c,0x77,0xc6,0xdd,
+  0x3e,0xb8,0x2c,0xbd,0x4b,0x76,0x8a,0xdb,0xa4,0x8f,0x63,0xff,0xf0,0x23,0x36,0x06,
+  0xfb,0xed,0x72,0xf3,0xf7,0x4c,0xfe,0x1f,0x78,0x04,0x0f,0xdd,0x02,0xae,0x8f,0x46,
+  0x28,0xb7,0x5e,0x6d,0x51,0xb9,0x42,0x3d,0x1a,0x4b,0x04,0xaa,0x45,0x69,0x5e,0x5a,
+  0x2b,0x87,0xb7,0x44,0x4c,0xfe,0x9f,0x65,0xb0,0x3b,0xc0,0xf5,0xaf,0x36,0x02,0x32,
+  0xd7,0x5f,0x4e,0xd4,0x47,0xef,0xf0,0xfc,0x5b,0x54,0xc4,0xca,0xf3,0xfd,0xf6,0x7b,
+  0x50,0xa2,0x0e,0x27,0xf1,0xcf,0x94,0x19,0xd0,0x23,0xcc,0xd0,0x49,0x98,0xac,0x80,
+  0x17,0xa1,0xa4,0xb7,0xad,0x3d,0x7b,0x85,0x10,0x4f,0x04,0x3a,0x83,0x50,0x61,0x06,
+  0xb3,0x6c,0x26,0xa1,0x14,0xff,0x33,0x5f,0x9f,0xa2,0x58,0x98,0xc3,0xfa,0x16,0x1e,
+  0xc3,0x15,0x62,0x3c,0xf1,0xac,0x0f,0x8d,0x4b,0x15,0x64,0x21,0xbd,0x6f,0x55,0x62,
+  0xf9,0x51,0xfe,0x8c,0x57,0xdf,0x3a,0x58,0x74,0x56,0xfc,0x04,0xad,0xef,0x79,0x11,
+  0xdc,0xed,0x2b,0xe0,0x2f,0xd4,0x58,0x1f,0x9e,0x68,0xcf,0x25,0x52,0x23,0x4b,0xe0,
+  0x9f,0x2d,0x37,0x8d,0xc2,0x02,0x87,0xed,0xe0,0x5d,0xe7,0x0a,0x2e,0x85,0x50,0x7f,
+  0x9d,0xb0,0x69,0xe2,0x66,0x38,0x24,0xa1,0x22,0x3b,0xd7,0x34,0x8a,0xaa,0xea,0x15,
+  0xe1,0x66,0x26,0x0e,0xd7,0x26,0xfd,0x2d,0xa3,0xf0,0x27,0x69,0x2e,0x58,0x41,0xdc,
+  0x08,0x87,0xd9,0x5c,0x75,0x5a,0x40,0xac,0x94,0x06,0x89,0x81,0x7f,0x2e,0xb1,0x0b,
+  0x4a,0xa9,0x86,0xd0,0x7a,0xd4,0xe4,0xff,0xf9,0x02,0xbf,0x81,0xc8,0x1c,0x8c,0xd8,
+  0x11,0x28,0x16,0xe5,0xd3,0x00,0x31,0x22,0x62,0x3c,0x11,0xfa,0x92,0x8e,0x2f,0xfe,
+  0x2d,0x6b,0x98,0x44,0x4d,0xfe,0x1f,0x9d,0x34,0x82,0x84,0x76,0x70,0x3a,0x43,0xc1,
+  0x3b,0x03,0xbe,0x03,0xcb,0xd6,0x5a,0x37,0x4a,0xaa,0xbe,0xc8,0xe5,0x19,0x50,0xc3,
+  0x6a,0xe1,0xc0,0x22,0x97,0x3d,0xe9,0x7f,0xd6,0xd3,0x50,0x68,0x07,0x10,0x44,0x35,
+  0x72,0x7b,0x16,0x8a,0xa8,0x25,0x40,0xb6,0x41,0xab,0xd2,0xa1,0xdf,0x18,0x26,0x23,
+  0xca,0x0e,0xa9,0x23,0x8a,0x88,0x28,0x99,0xff,0xa3,0x09,0x9f,0xc2,0xab,0x7a,0x99,
+  0xdd,0x5a,0xd8,0xd4,0x84,0xda,0xa4,0x8c,0x5a,0xac,0x05,0xdb,0xe0,0x1d,0xe6,0xd6,
+  0x6f,0x0e,0xe7,0x8c,0x48,0x17,0xde,0x76,0x8f,0xe2,0x42,0x0d,0x9a,0xe2,0x5f,0xeb,
+  0x5a,0x0d,0x27,0x6a,0x54,0x1c,0x83,0xcb,0xc1,0xaa,0xd0,0x63,0xfa,0xa4,0x4b,0xea,
+  0x95,0x40,0x3c,0xfe,0x75,0x89,0x55,0xfa,0x8b,0x47,0xcd,0xf9,0xcf,0xb0,0x0d,0x0e,
+  0xdd,0x13,0x96,0xac,0x21,0x31,0x9f,0x46,0x94,0x79,0x92,0xb5,0x39,0x67,0x04,0x0e,
+  0x22,0x10,0x35,0x1c,0x95,0x28,0xd8,0x83,0xce,0x54,0xfc,0xe3,0x94,0xda,0x98,0x7d,
+  0x93,0x23,0x24,0x3e,0xa0,0x37,0x82,0xfa,0x0b,0xf1,0x31,0xb0,0xc1,0x0b,0x01,0xbe,
+  0x7f,0xe0,0x12,0x45,0xc3,0x7c,0x23,0x84,0xcd,0xf1,0xaf,0x29,0x1a,0x2e,0x8b,0x0a,
+  0xd4,0xe2,0xc1,0xc1,0x16,0x07,0x64,0x58,0xa5,0x23,0x5a,0x2b,0xab,0x8f,0x25,0xee,
+  0x76,0xc3,0x83,0x0d,0xe0,0x4a,0xf1,0xff,0x5c,0x07,0xab,0x98,0xda,0xe9,0xf8,0x8e,
+  0xff,0x1e,0xf2,0x6b,0x96,0xaf,0x2e,0xfa,0x3b,0x32,0x0d,0x9e,0x65,0x3f,0x30,0x02,
+  0x43,0xd6,0x97,0x43,0xc5,0x68,0x94,0x13,0x73,0xfc,0x8b,0x40,0x6f,0xc8,0x05,0x56,
+  0x8b,0x58,0x8d,0xe0,0xbe,0xbc,0xf6,0xa6,0xcc,0xa6,0x01,0xad,0xcf,0x5f,0xae,0xdb,
+  0xca,0xc5,0x81,0xdc,0xcf,0x42,0x15,0x41,0xeb,0xfc,0x14,0xff,0xcf,0x4e,0xed,0x32,
+  0xec,0x65,0x69,0x83,0x05,0xa3,0xda,0x9f,0x95,0x2a,0xcd,0xa6,0x15,0x9c,0x54,0x2e,
+  0xc0,0xdc,0x7e,0xdb,0x59,0xf1,0x32,0xbd,0xa8,0x54,0x81,0x2d,0xc5,0xff,0x83,0xf8,
+  0x67,0x9c,0xd8,0x17,0x5a,0x55,0xbb,0xce,0xfd,0xff,0x5c,0x1b,0x6e,0x83,0x8b,0xcc,
+  0x48,0x44,0xff,0x54,0x8f,0xe0,0x41,0x58,0x12,0xae,0x31,0xe5,0xff,0x08,0x9b,0xd4,
+  0x57,0x10,0xdf,0xd1,0x06,0xc8,0x23,0xab,0x20,0x1f,0xda,0x78,0x22,0xe5,0xcb,0xb1,
+  0xb4,0x81,0x4b,0xd0,0x0c,0x33,0x41,0x6e,0xf0,0x24,0xeb,0xbf,0x74,0xe5,0x9f,0xb9,
+  0x93,0x47,0xa5,0x11,0xf7,0x31,0xb5,0x93,0xa3,0x3b,0xdd,0xff,0xb4,0xd4,0xcd,0x66,
+  0x1a,0xef,0xbb,0x61,0x83,0xff,0xfe,0xd0,0xa1,0x95,0xf6,0x64,0xfd,0x5d,0x9d,0x72,
+  0x18,0x76,0x04,0x7d,0x5d,0xb4,0x1c,0x41,0xc5,0xd6,0x85,0x85,0x85,0x32,0x2d,0x5a,
+  0x4b,0xbb,0xb5,0x98,0x23,0x5a,0x78,0xb2,0xdd,0xa1,0xc8,0xa9,0xf9,0x3f,0xbb,0xb5,
+  0x2f,0xd8,0x8f,0x98,0xf5,0xa3,0xef,0x8d,0xe1,0x46,0x9e,0xcb,0x96,0x0c,0x93,0x2e,
+  0xeb,0x15,0x57,0x51,0x2c,0x10,0xf6,0x2e,0x2b,0xdd,0x88,0x83,0x0b,0x09,0x79,0x6e,
+  0xe0,0x1f,0xad,0x42,0x9a,0xc5,0x26,0x9f,0x02,0xaa,0xed,0xc9,0xb6,0x35,0x73,0x7b,
+  0x1c,0x51,0xa9,0x81,0x7f,0x86,0x63,0x1e,0xa1,0xd4,0xfc,0xe7,0xf1,0x90,0x9b,0xa7,
+  0xb5,0x0c,0xc1,0x81,0x66,0x77,0x9d,0x75,0x93,0xd8,0xa9,0x8d,0x37,0xfe,0x4c,0x5b,
+  0x1f,0x4b,0x7c,0x75,0xff,0xd0,0xd6,0x9e,0x92,0xff,0xb3,0x9c,0xee,0xa6,0xff,0xa4,
+  0xd1,0x1b,0x48,0xb3,0xd6,0xa8,0xab,0x3e,0x7a,0x9d,0xb8,0x1c,0x76,0xb7,0xcf,0xd3,
+  0x32,0x0c,0xc7,0x8e,0x54,0xb4,0x4c,0x6e,0x47,0xc4,0x65,0x8e,0x7f,0xed,0x26,0x45,
+  0xdf,0xb8,0xd3,0x40,0x3b,0xca,0xe9,0x18,0xec,0x49,0xc4,0xbf,0x76,0x73,0x0f,0xc6,
+  0xc6,0x94,0xfc,0x1f,0x09,0x76,0x6b,0x2a,0xe2,0x1f,0x7b,0xb3,0xd0,0x04,0xaa,0x56,
+  0xa4,0x78,0x6a,0xe9,0x76,0xcd,0xa9,0x65,0x28,0xf6,0xd7,0x84,0xed,0x1a,0xf5,0xca,
+  0xb9,0xc4,0x9f,0xf4,0xff,0xa4,0xf9,0x10,0xff,0x17,0x09,0x99,0x8c,0x74,0x21,0xde,
+  0xeb,0x66,0x77,0x33,0xc3,0xf1,0x55,0x12,0x77,0x7c,0x09,0xd9,0x7c,0x60,0xaa,0xff,
+  0x9a,0xf2,0xb9,0xf4,0x53,0xed,0x15,0x2f,0x82,0x9c,0x9d,0xe4,0x8f,0x50,0xa5,0xad,
+  0xf2,0x8a,0x9d,0x0a,0x87,0x3d,0x93,0x78,0x20,0xec,0xb2,0x76,0xb3,0x97,0xd7,0x7f,
+  0x91,0x24,0xfe,0x19,0x0a,0xfd,0x49,0xab,0xf2,0x5a,0x8f,0xcb,0x9b,0xe0,0x03,0x98,
+  0xab,0x4d,0xf3,0x8a,0x73,0xe0,0xb2,0x52,0xc2,0xe7,0xe3,0xfa,0xf8,0xe6,0xd7,0xd9,
+  0x06,0xc5,0xd5,0x66,0xff,0x0f,0x04,0x08,0x1a,0x4d,0x6b,0xec,0x2a,0xc4,0x0a,0xc1,
+  0xbe,0xa7,0x42,0x8f,0xf7,0x41,0x03,0xff,0x84,0x7a,0xf2,0x4b,0xa8,0xec,0xf7,0x9b,
+  0xe2,0x5f,0xb7,0x0f,0xc1,0x06,0xad,0xcb,0x4b,0xb3,0x4b,0xfa,0x11,0x1f,0x2e,0x47,
+  0xa0,0x68,0xa9,0x85,0xed,0xaa,0x33,0x1e,0x08,0xf3,0xad,0xb8,0x67,0x91,0x92,0x9d,
+  0x1a,0xff,0x6a,0xa9,0xe1,0xf1,0xc7,0x2c,0x2e,0x7f,0x96,0xd5,0xe0,0xea,0x15,0x26,
+  0xd6,0x53,0xd9,0xad,0x3c,0xe8,0xc5,0x81,0x29,0xfe,0x35,0xf9,0x0c,0xbc,0xa5,0xcd,
+  0x7b,0xd8,0x19,0x2c,0xe8,0x6f,0xbe,0x9f,0x95,0x79,0xd3,0x6f,0x98,0x8e,0xdf,0x4b,
+  0x2d,0x89,0x27,0x36,0xd7,0xcd,0xf3,0xad,0x0f,0x4e,0xea,0x4a,0x8d,0x7f,0x75,0xcd,
+  0x5b,0x6e,0x53,0x6a,0x9e,0x85,0xf1,0xcd,0x3c,0x0d,0xfe,0x55,0x9c,0xa6,0xfe,0x2c,
+  0x3e,0x5f,0xfa,0x59,0x1d,0x02,0xa7,0x8f,0x52,0xf3,0x7f,0x48,0x19,0x38,0xd9,0xab,
+  0x3e,0x38,0x51,0x5b,0xa6,0x64,0x35,0x17,0xc4,0xc2,0x8e,0x36,0x56,0xc0,0xb7,0x62,
+  0x59,0x9e,0xb5,0x51,0x34,0xe7,0xff,0x50,0x44,0x46,0x05,0x9b,0xe8,0x69,0x71,0x65,
+  0x60,0x5d,0x60,0x2b,0x93,0x47,0x48,0x79,0x60,0x9d,0xab,0xa4,0x91,0xc7,0xbf,0xe8,
+  0x9e,0xb4,0x5b,0x3a,0x68,0x57,0xb6,0x39,0xff,0x67,0x31,0xb4,0x09,0x33,0x36,0xd1,
+  0x0a,0xcb,0x42,0xd8,0xa1,0xab,0xf5,0xb2,0x74,0x87,0xae,0x36,0x49,0xf5,0x13,0x81,
+  0x1b,0x55,0x41,0x55,0x9e,0x92,0xff,0x23,0x20,0x6c,0x66,0x01,0x8d,0xdc,0x27,0x3c,
+  0x07,0xf9,0xe4,0x46,0x8d,0x1d,0x23,0x6b,0x84,0x62,0xfd,0xc6,0x06,0xcf,0xc9,0xc6,
+  0x5d,0x9b,0x66,0xaa,0xd4,0x9c,0xff,0xb3,0x8d,0x66,0xc1,0x1b,0xc1,0x5b,0x55,0xeb,
+  0x98,0xfc,0x5d,0xeb,0x97,0x4d,0xb3,0x43,0x77,0xd7,0xe1,0xe9,0x78,0x83,0x2d,0x88,
+  0x4e,0x5a,0x29,0xbe,0x07,0x9f,0x85,0x4a,0x55,0x67,0x6a,0xfe,0xcf,0xb6,0xec,0x8b,
+  0xf9,0x95,0x60,0x48,0xd7,0x77,0x0c,0xb3,0x42,0x06,0x03,0xff,0x18,0xf5,0x5f,0x17,
+  0xef,0xc0,0x2b,0xe1,0x82,0x3e,0x32,0xb1,0x3e,0x90,0x76,0x85,0xbc,0xde,0x58,0xaa,
+  0x5a,0x97,0xc2,0xa3,0xf0,0x65,0xb0,0xb4,0xf0,0xa6,0x3a,0xf1,0x29,0xfa,0x06,0xc2,
+  0x9e,0x25,0x63,0xe2,0x15,0xe9,0xe8,0xe8,0xac,0xce,0xf5,0x63,0x44,0x33,0xf9,0x7f,
+  0xd6,0x6a,0x7e,0x4f,0x7e,0x00,0xee,0xe9,0xf8,0xcf,0xc1,0x35,0xae,0x5b,0x21,0xef,
+  0x0e,0x4b,0x10,0xbe,0x80,0x05,0xfc,0x7d,0x4f,0xc2,0x9a,0x40,0xf1,0x51,0xf9,0x2c,
+  0x29,0x32,0xc5,0xbf,0xd6,0xc2,0xba,0x3c,0x94,0xcf,0x83,0xb4,0x62,0xce,0xbf,0x64,
+  0x14,0xe0,0x99,0x3f,0x18,0x84,0xf5,0x1a,0xca,0xab,0x87,0x70,0x7d,0xd6,0xa8,0x0f,
+  0xb0,0x36,0x2f,0x31,0xc7,0xbf,0x8e,0xd2,0x56,0x4d,0x9d,0x5a,0x97,0x97,0xbe,0x84,
+  0xf9,0xf5,0x42,0xa0,0xb9,0xcf,0xb2,0x78,0xfc,0x9d,0x0c,0x48,0x4d,0xcc,0xe9,0xc1,
+  0x8d,0x17,0x30,0xc5,0xbf,0x66,0xb1,0x03,0x7d,0xee,0x51,0xe7,0x4e,0xd9,0x06,0xef,
+  0x33,0xd7,0x70,0xa6,0x44,0x98,0xf4,0xaa,0x6e,0xe8,0xf7,0x4b,0xc4,0xd6,0x5b,0x19,
+  0xe6,0xc0,0xc6,0x1c,0xff,0x52,0xc6,0x7d,0x15,0x41,0xdb,0xce,0xa6,0xdf,0x70,0x7c,
+  0x08,0x59,0x9d,0xb8,0x0d,0x2e,0x7a,0x2b,0xe3,0x81,0x42,0x5a,0x19,0x34,0x80,0x41,
+  0xd2,0xff,0x73,0x32,0x7f,0x40,0xcf,0x01,0xeb,0x98,0xf8,0x13,0xf8,0x4b,0xa4,0x34,
+  0x60,0x3d,0x28,0x36,0x40,0x1c,0xff,0x9c,0xc4,0xc1,0x02,0xee,0x51,0xd1,0x4d,0xf8,
+  0x67,0x85,0x25,0xc0,0x3a,0xca,0xe9,0x6c,0x54,0xbb,0x6d,0x60,0x57,0xf1,0x74,0x2f,
+  0x63,0x2f,0xb2,0xa2,0x58,0x3c,0x0b,0xf1,0x7f,0xbd,0x23,0xec,0x89,0xa6,0xe4,0x3f,
+  0x07,0xa0,0x28,0x54,0xb4,0x33,0x7d,0x1b,0xc3,0xf9,0x50,0xc7,0x3c,0x67,0xa4,0x36,
+  0xdd,0xc8,0x57,0x19,0x21,0x88,0x88,0x42,0x74,0x23,0x31,0xd7,0x7f,0x59,0x81,0x09,
+  0x21,0x66,0x99,0x83,0xf7,0x47,0xf9,0x03,0xbf,0x12,0x50,0x71,0xbc,0x08,0x9d,0xfa,
+  0xa2,0x39,0x1c,0x11,0xe5,0x59,0x75,0x5e,0x7f,0x6a,0x8a,0x7f,0x3d,0xa0,0xad,0xbd,
+  0xb7,0x08,0x10,0x06,0x77,0xf2,0xb4,0x13,0xee,0x76,0x1e,0x82,0x43,0xf1,0xc4,0x78,
+  0x03,0x31,0x5a,0x7f,0x51,0xa0,0x9b,0xe2,0x5f,0x97,0xe0,0x12,0x99,0x0b,0x8f,0x71,
+  0xb3,0xfd,0x12,0xfc,0x0e,0xee,0xee,0xc3,0xf7,0xbd,0xec,0x40,0xe0,0x77,0x4e,0xbc,
+  0x44,0x2f,0xda,0x51,0xa3,0x1d,0x4b,0x89,0x7f,0x7d,0x01,0xaf,0xb3,0xd9,0xbe,0xc7,
+  0xa2,0x62,0x8f,0x76,0x94,0x55,0x45,0x33,0x23,0xe2,0x39,0x1e,0x91,0x8c,0xa2,0xbe,
+  0x73,0x85,0x06,0xd4,0x52,0x6a,0x6b,0x4a,0xc1,0x3f,0x67,0xa0,0x95,0xd9,0x7d,0xb4,
+  0x8b,0x38,0x68,0x1b,0x73,0x1e,0xa0,0x3d,0xea,0xa7,0x74,0xaf,0x03,0xf1,0xcf,0x17,
+  0x24,0x9f,0xb5,0xe4,0xd9,0x97,0xcb,0x6b,0x52,0xf0,0x4f,0x14,0x5a,0x89,0x43,0xcb,
+  0x50,0x89,0x93,0x3d,0x0e,0xce,0x3e,0x6a,0xd4,0xbf,0x23,0xfe,0x91,0xcb,0x88,0xee,
+  0x62,0x6a,0x3d,0xc8,0x8a,0x19,0xff,0x4c,0x79,0x96,0xb6,0x42,0x91,0x2f,0xb0,0xa5,
+  0xb5,0x18,0x61,0x73,0x89,0x5e,0x1f,0x44,0xd8,0xb3,0x57,0xe1,0x78,0x32,0x7d,0x86,
+  0xda,0xc2,0x96,0xd9,0xe5,0xf6,0x74,0x13,0xfe,0x99,0x72,0x06,0x0e,0xb1,0xf2,0xb1,
+  0xcc,0x2e,0xb1,0x88,0xbc,0x23,0xe1,0x31,0xd9,0x2d,0x8e,0xd4,0x7e,0xc6,0xe6,0x71,
+  0x0f,0xcf,0x19,0x1a,0x89,0xcc,0x9b,0xfd,0x8d,0x40,0x0a,0xfe,0xd9,0x07,0x57,0x36,
+  0xed,0xd2,0x27,0xf5,0x88,0x17,0x8d,0xfa,0x38,0x04,0x42,0xa3,0x70,0x95,0xcd,0xea,
+  0x5d,0x34,0x2a,0x2f,0x57,0x46,0xc9,0x7e,0x1d,0x05,0x91,0x39,0xfe,0xf5,0x2c,0x5c,
+  0x94,0xdc,0x91,0xb5,0x8d,0xe2,0x6f,0xfc,0xdc,0xbf,0x61,0x0d,0x17,0xcc,0x82,0x8b,
+  0x19,0x95,0xfa,0x92,0xed,0x72,0xbd,0x8a,0x5f,0xc4,0x6b,0xdd,0x62,0xaa,0xff,0x8a,
+  0xa4,0xa5,0xd3,0xee,0x41,0x7b,0x1f,0xa5,0xc4,0xa6,0xb6,0xf1,0x34,0xb0,0x1d,0x76,
+  0x27,0xe2,0x09,0xdc,0x0f,0x9f,0x93,0xe9,0xac,0xa5,0xdd,0xee,0xab,0x0b,0x12,0xb7,
+  0xc9,0xff,0x53,0x0b,0x1b,0x05,0xd5,0x15,0xa8,0xd8,0xd8,0x82,0xfb,0xa1,0x44,0xb7,
+  0x54,0x10,0xab,0xb4,0x83,0x39,0xb9,0xe3,0xe8,0x87,0xd0,0x01,0x85,0x21,0x4b,0x11,
+  0x59,0x69,0xae,0xff,0xf2,0xbe,0xdc,0x51,0x30,0x54,0xbf,0x32,0x7b,0x9a,0x91,0xfd,
+  0x6b,0x59,0x79,0xc3,0x34,0xd8,0xd5,0x53,0xcc,0x23,0x44,0xd7,0x01,0x22,0x84,0xf2,
+  0xef,0xfc,0x5d,0xb6,0xb9,0xfe,0x0b,0xe0,0x1c,0x75,0xf5,0x5b,0x5d,0xe2,0x36,0xf6,
+  0x2a,0x54,0x0c,0x67,0x4d,0x17,0x41,0xfa,0x2c,0x7c,0x1f,0x2f,0x7b,0xd7,0xe0,0x14,
+  0xec,0x24,0xce,0x12,0xf1,0x1e,0x73,0xfd,0xbb,0x74,0xa9,0xb0,0xaa,0xdf,0xb6,0x25,
+  0xe6,0x36,0xec,0x2f,0x6e,0xa8,0xb9,0x54,0x7b,0x55,0xc1,0x2b,0xdb,0x1f,0xdf,0x09,
+  0x7f,0x9a,0x3c,0x9f,0x66,0x06,0x53,0xf2,0x9f,0xfb,0x71,0xfd,0xdd,0x4c,0x2a,0x2f,
+  0x28,0x04,0xee,0x1f,0x43,0x45,0x70,0xc4,0xf0,0xbf,0x2d,0x09,0xe7,0x94,0x93,0x23,
+  0x50,0x1a,0xb5,0xea,0xdf,0x4b,0xad,0xff,0x5a,0x2d,0x6d,0xd1,0xeb,0xbc,0x84,0xd7,
+  0xcf,0xce,0xe2,0x89,0x40,0x27,0xa5,0xf5,0x88,0x7f,0xda,0xdc,0xfe,0x4d,0xb0,0x56,
+  0xc8,0xd7,0xe9,0xa0,0xc5,0x1c,0xff,0x7a,0x02,0xfe,0xd9,0x7f,0x4b,0x88,0x9e,0x58,
+  0x3d,0xcd,0x70,0xfb,0x64,0x20,0xec,0xc9,0x5d,0xb3,0x7a,0x7a,0x54,0x7e,0x94,0x58,
+  0x84,0x27,0x98,0xea,0xfb,0x41,0x7d,0x4a,0xfd,0xd7,0x11,0xd8,0xa8,0x3b,0xde,0xa2,
+  0x84,0x14,0x33,0xc3,0x9f,0x26,0x2c,0xeb,0xa5,0xcf,0x73,0xfb,0x2b,0xcc,0x81,0x41,
+  0x30,0xe4,0x45,0x20,0x71,0x4d,0xfe,0x8f,0x3e,0xbf,0xdb,0x1a,0xfd,0xda,0x3c,0xc2,
+  0xdd,0x3e,0x99,0x5d,0x05,0xc3,0x9e,0x83,0x21,0x1e,0x11,0xb3,0xcc,0x67,0xef,0x0a,
+  0xa5,0x2c,0xf3,0x8c,0x68,0x8e,0x7f,0x9d,0xb2,0x0f,0xcf,0x2e,0x83,0x7f,0x69,0x96,
+  0x4f,0x69,0x3c,0xec,0x95,0x15,0xe0,0x69,0x18,0x1e,0x03,0xf6,0x9c,0x92,0x02,0xac,
+  0x32,0x3d,0xab,0xf9,0xf1,0x6b,0xf2,0x7f,0x82,0x95,0xda,0xe2,0x0d,0x05,0x67,0xd8,
+  0x87,0x68,0xe6,0x5b,0x6f,0xe0,0xf5,0xef,0xd5,0x8f,0x6a,0x4b,0x36,0x8a,0x33,0x7c,
+  0x07,0x1a,0xdd,0x5e,0xdb,0x53,0x82,0x29,0xfe,0x05,0x77,0xa0,0xd1,0xe4,0x6c,0xa0,
+  0x4f,0x7f,0xe3,0x0c,0xe1,0xfe,0x07,0xda,0xee,0x41,0xfd,0x8b,0x88,0x48,0xde,0xdc,
+  0x8a,0xfb,0x67,0xb0,0xc3,0x2b,0x6f,0x16,0x53,0xf2,0x7f,0x14,0x9c,0x56,0xeb,0x08,
+  0xba,0x87,0xf0,0x35,0x9d,0x5a,0xde,0x20,0xa9,0x84,0xdd,0xa2,0x51,0xaf,0x34,0x24,
+  0xb4,0x50,0x3b,0xf7,0xff,0xac,0x36,0xcb,0x1f,0xb4,0x47,0x4a,0xb8,0x90,0x79,0xcc,
+  0x70,0x04,0xe5,0x9d,0x20,0xb9,0xb0,0x9d,0xfb,0x7f,0x72,0xc9,0x2a,0x85,0x3b,0x82,
+  0x6e,0x9c,0x63,0xc6,0x3f,0x99,0x3e,0x1a,0x11,0x78,0xb4,0x0b,0x85,0xd8,0xb0,0x11,
+  0xf6,0x92,0x5d,0x1c,0x11,0xc5,0xf0,0x5e,0xc4,0x40,0xbc,0xf2,0x3a,0x53,0xfc,0xeb,
+  0x3c,0xfd,0x5c,0x58,0xc0,0x9d,0x3c,0x9f,0x1b,0xfe,0x9f,0x59,0x5c,0xad,0xff,0x94,
+  0x87,0xe9,0x37,0x89,0xff,0xcd,0xa8,0xff,0xc2,0x9f,0x66,0x5c,0x93,0xff,0x53,0xaa,
+  0xdd,0x75,0xac,0xe0,0x7c,0xd7,0x01,0x7c,0x11,0x3a,0x58,0x73,0x09,0xa7,0xb9,0x35,
+  0xdb,0xef,0xc5,0x39,0xda,0x61,0xab,0xdb,0xb3,0xe2,0x4d,0x30,0xe7,0x3f,0x0f,0x43,
+  0x0f,0x8a,0x59,0x8a,0xda,0x9c,0x75,0x21,0x0c,0xa3,0xcc,0x1e,0x85,0x1e,0xbb,0x1d,
+  0x6c,0xab,0xc9,0x16,0x0f,0x47,0x44,0x74,0xd5,0x3d,0x59,0xe6,0xfc,0x9f,0x8c,0xdd,
+  0x92,0xea,0x93,0x27,0x93,0xe6,0x50,0x23,0xac,0xa8,0x2b,0xcf,0x23,0xfd,0x12,0x5e,
+  0xc1,0xf7,0xb5,0x4b,0x6c,0x0b,0x55,0x35,0x9a,0x6d,0x49,0x89,0x7f,0x29,0xbb,0x05,
+  0x7b,0x5d,0x2b,0x8a,0x1d,0xc4,0x4b,0x3c,0x11,0xc8,0xf3,0x81,0xb6,0x9b,0xd9,0x35,
+  0x94,0x3f,0xdb,0xb4,0xe7,0x61,0x99,0x97,0x06,0x67,0x98,0xe2,0x5f,0x53,0xfe,0xac,
+  0x9d,0x6d,0x74,0x35,0xcc,0xda,0x2c,0x3e,0xc7,0xb3,0xd9,0x79,0xfe,0xf3,0x07,0xd2,
+  0x59,0xe8,0xd6,0x96,0x04,0xe5,0xe9,0x8e,0x0f,0xa3,0x6e,0x6d,0xf1,0x53,0x93,0x1c,
+  0x66,0xfc,0x83,0x68,0x67,0xbf,0x76,0xd7,0xa6,0x9a,0x21,0x3f,0xcf,0x5e,0x58,0x82,
+  0x68,0xd0,0xc8,0x07,0xbb,0x4e,0x11,0x5f,0x87,0xb7,0x42,0xfb,0x86,0x6d,0x93,0x53,
+  0xf2,0x7f,0xb6,0x48,0x91,0x8c,0xca,0xfc,0xb5,0xcd,0x62,0xbe,0x91,0x6d,0x6e,0xe3,
+  0xfb,0x6d,0x2c,0xc8,0x97,0xdd,0x88,0x48,0x56,0xce,0x41,0xf9,0x6c,0x31,0xfb,0x7f,
+  0x94,0x75,0x74,0x16,0x0b,0x9c,0x22,0xe5,0xd0,0x2a,0x94,0xb0,0xef,0x9e,0xb6,0x0f,
+  0xab,0xfb,0x63,0xf1,0xaf,0xdb,0xb4,0xbb,0xbf,0x59,0xc2,0xe4,0x68,0xba,0xd9,0xff,
+  0x53,0xab,0x6d,0x00,0x67,0x14,0x66,0x93,0x19,0x4a,0x93,0x80,0x62,0xca,0x81,0x68,
+  0xd9,0x90,0xcf,0x53,0xc9,0x37,0xd2,0x9e,0x6c,0x76,0x46,0x17,0xe5,0xa6,0xf8,0x7f,
+  0xca,0xa4,0x4d,0xc2,0x2c,0xaf,0xa3,0x3c,0x6b,0x32,0x1e,0xcd,0xe2,0xde,0x85,0xde,
+  0xec,0x93,0xc0,0xcb,0xc0,0xe5,0xe5,0xe4,0x3f,0xd3,0x55,0x5a,0x71,0xa3,0xec,0x25,
+  0xf5,0xa6,0xfc,0xe7,0xeb,0xf0,0xd8,0x2e,0x88,0x5a,0x97,0x8a,0x65,0x06,0xec,0x91,
+  0x57,0x8a,0xef,0x4a,0x57,0x79,0xda,0xf3,0x09,0xf9,0x61,0x72,0xbc,0x69,0xc1,0x69,
+  0x1c,0x14,0x99,0xf1,0x4f,0xfa,0x47,0x78,0x6c,0x51,0x08,0x0f,0x73,0xfd,0xde,0x67,
+  0xa8,0xb9,0xdd,0x3c,0x1f,0x26,0x5a,0xd0,0xc3,0x5d,0xcd,0x75,0x4b,0x06,0x4d,0xf5,
+  0x5f,0x90,0xf6,0x07,0x38,0xd1,0x5c,0x31,0x64,0xfd,0x50,0x3c,0x03,0x47,0x83,0x95,
+  0xa7,0x9d,0x46,0xfd,0x72,0x33,0xda,0xef,0x27,0xc4,0x32,0x76,0x95,0x55,0xf9,0xac,
+  0x1f,0x0a,0x66,0xfc,0xb3,0xb9,0xa3,0xf9,0x5c,0xf1,0x30,0xfd,0x0e,0x39,0x16,0xf9,
+  0x23,0x38,0x87,0x2c,0x5e,0x5e,0xff,0x25,0xe4,0xf7,0xcb,0x77,0x92,0x5c,0xf5,0x25,
+  0xa1,0x18,0x32,0x7f,0x90,0x6d,0xc6,0x3f,0x3b,0xa5,0xd5,0x6e,0x14,0x53,0x5a,0xfa,
+  0xf1,0xc6,0x35,0xf0,0xc0,0x6b,0x34,0x16,0xe6,0x43,0xfc,0x73,0x0f,0x51,0x9e,0x7c,
+  0x59,0x29,0x5e,0x4d,0x3d,0x59,0x60,0xc2,0x3f,0xb5,0xe0,0xf7,0x38,0x75,0x9a,0x99,
+  0x1e,0x0d,0xa2,0xbe,0xe3,0x34,0x02,0x87,0xd5,0x1d,0x5c,0xfe,0xa8,0xc4,0xb2,0xa1,
+  0xdb,0xe5,0x74,0x65,0x38,0x08,0x4d,0xec,0xcf,0x6d,0x53,0x56,0x41,0x9f,0xaf,0xc2,
+  0x6f,0x0d,0xda,0x3f,0x60,0x87,0x50,0x1e,0x5a,0x7b,0x0c,0x7f,0x17,0xda,0x8f,0xc1,
+  0x82,0xaf,0x4b,0xe3,0xac,0xf2,0xbc,0xb5,0xbd,0xa0,0xc8,0x84,0x7f,0x3e,0x81,0x61,
+  0x5a,0xd9,0x37,0x2b,0x38,0x29,0x1a,0xcb,0xff,0x09,0x8a,0x23,0xda,0x38,0x33,0xea,
+  0x91,0x3f,0xc9,0xdd,0x5d,0x9d,0xc5,0x6c,0xbf,0xd8,0x6a,0xce,0xff,0x19,0x55,0x3f,
+  0x15,0x4a,0xf5,0x80,0x17,0x2f,0x1a,0xfa,0x6e,0x74,0x2b,0x9e,0x2f,0xf8,0xb9,0x6e,
+  0x53,0x44,0x17,0x9c,0x97,0x4a,0xf9,0x7f,0xc8,0x84,0x7f,0xe0,0x7b,0x52,0xab,0xd7,
+  0xae,0xd3,0xcd,0x4d,0x45,0xc0,0xe3,0x17,0x8b,0xf6,0xf9,0x71,0xfd,0x1b,0x1f,0xd4,
+  0xe5,0xcd,0xd9,0x05,0xd0,0xb3,0x05,0x0f,0xc2,0xda,0x26,0x53,0xfc,0x4b,0x28,0xf4,
+  0x75,0xc1,0x32,0xee,0xfd,0x78,0x96,0xfb,0x7f,0xb8,0xbf,0x7d,0x44,0xdb,0xdb,0x68,
+  0x0c,0xfe,0x21,0xe3,0x45,0x3c,0x38,0x37,0x76,0xa5,0x9b,0xf1,0x8f,0x13,0x98,0xba,
+  0x6c,0x78,0xa1,0xe2,0xaf,0x03,0x5c,0x9f,0x08,0xa2,0x41,0x84,0xd9,0x5c,0xdf,0x81,
+  0x1f,0x84,0x30,0x84,0xe0,0x46,0x65,0xb5,0x3f,0xc1,0xbf,0xc1,0xfd,0x3f,0x1f,0x11,
+  0xb7,0x9e,0xe5,0x47,0xb3,0xeb,0x63,0x58,0x30,0xc0,0xdf,0x17,0xc6,0xef,0x29,0xd1,
+  0x97,0xf8,0xe5,0x42,0xf8,0x90,0xe7,0x57,0xac,0x31,0xe3,0x9f,0x9b,0x46,0xe1,0x4a,
+  0x35,0xaa,0x2d,0x26,0xec,0xe6,0xfa,0xeb,0x04,0xee,0x96,0x4b,0xf4,0xbc,0x5a,0xc5,
+  0x33,0xa8,0xb9,0xff,0x67,0x01,0x2c,0xf1,0x8b,0x0e,0x13,0xfe,0xb9,0x42,0x0e,0xc3,
+  0xdc,0xa8,0x6d,0x18,0x61,0xd2,0x5f,0xf8,0x6e,0x19,0x45,0xf9,0xc3,0x81,0x90,0x6d,
+  0x0c,0x81,0xd0,0x49,0x4e,0x0d,0x74,0x02,0x7f,0x4a,0xe2,0x9f,0x91,0x50,0x0b,0x8a,
+  0x1c,0xb9,0x0b,0x8d,0xb0,0x36,0x56,0xe2,0x0b,0xf4,0x20,0xcc,0x42,0x45,0xcf,0x57,
+  0x20,0x8a,0x50,0x10,0xa1,0x72,0x30,0x25,0xff,0x79,0x80,0xf9,0xfd,0x2a,0x8f,0x06,
+  0xd6,0xa1,0xd9,0xef,0xd4,0x1c,0xdc,0xac,0xd8,0x4a,0x0c,0x3c,0xac,0x43,0x90,0xcf,
+  0x57,0x88,0xc7,0x14,0xff,0x42,0xd8,0xc9,0x66,0xe8,0x72,0x07,0x71,0x6a,0xdc,0xdb,
+  0x1c,0x08,0xc3,0x08,0x69,0x83,0x07,0x7b,0x51,0x7f,0x45,0x0d,0x8b,0x0f,0xef,0x9f,
+  0xcc,0xff,0xd1,0x26,0xc7,0xb3,0x91,0x9d,0xe2,0xf7,0x70,0x7d,0x2a,0xfa,0x79,0x7e,
+  0x94,0xf4,0xb1,0x60,0x04,0x46,0xd1,0x34,0x63,0xdd,0xb5,0x4e,0x41,0xf4,0xa6,0xe0,
+  0x1f,0x1e,0xed,0xb2,0xe9,0x1c,0xf6,0x00,0xbe,0x26,0xcf,0x4f,0x8e,0xe7,0x47,0x7d,
+  0xa1,0x5d,0x0e,0x56,0xf9,0x6c,0x91,0xd4,0xfa,0x77,0xe1,0x9c,0x8a,0xbb,0x6b,0x6b,
+  0xec,0x3c,0x9e,0xb6,0x85,0x73,0xac,0x4a,0x3c,0x1f,0xef,0x8c,0x8a,0x1b,0xcf,0x67,
+  0x6d,0x6c,0x72,0xa5,0xf8,0x7f,0xf6,0xd6,0x72,0xf4,0x2b,0x2e,0xd1,0x70,0xff,0x0c,
+  0x66,0x8e,0xa2,0xa2,0x8f,0xe7,0x6f,0x9f,0x81,0xdd,0xac,0x64,0x39,0x0d,0xa4,0xe0,
+  0x9f,0x15,0xb0,0x43,0x73,0xf6,0xca,0x4e,0xd2,0x17,0x5f,0x16,0xcb,0xda,0x78,0xe2,
+  0x0a,0xf9,0x10,0x5e,0x28,0x2c,0x09,0x3a,0x5c,0x96,0xd4,0xfa,0xf7,0x5d,0x41,0x5e,
+  0xfd,0x4d,0xbc,0x1c,0x0f,0x0c,0x5d,0xcf,0xf9,0x70,0x76,0xc5,0xe2,0x41,0x6f,0x0b,
+  0x2f,0x37,0x17,0x87,0xe8,0xca,0xf4,0x3c,0x93,0xff,0x87,0xa7,0xc1,0x54,0xbc,0x66,
+  0x2b,0x14,0x7b,0x7d,0xef,0xf3,0xea,0x51,0x97,0xb8,0x16,0x3e,0x0b,0x97,0x23,0xfe,
+  0x29,0x88,0xb0,0x73,0xac,0xa2,0x45,0x0a,0x8b,0xd9,0x66,0xfc,0x03,0x57,0x85,0xaa,
+  0x5e,0x9b,0x2a,0x0e,0xe2,0xb2,0x2c,0xa8,0xc6,0xd7,0xfc,0x29,0x5c,0x24,0x86,0x7f,
+  0x6c,0x0c,0x2e,0xb8,0xaa,0x98,0x6d,0xf7,0x35,0xfe,0x1f,0x9e,0x16,0x85,0xf3,0x83,
+  0xf8,0x21,0x2a,0xb4,0x8c,0x1e,0xb9,0x78,0xc2,0x5f,0x1d,0xfb,0x34,0x0f,0x74,0x5d,
+  0x53,0xff,0xbe,0x4b,0xda,0xc0,0x93,0x7c,0x14,0xfa,0xb7,0x50,0xcc,0xf1,0xcf,0xaf,
+  0xd9,0x2e,0xb4,0x1f,0x33,0x78,0x21,0xea,0x1a,0x1e,0x58,0x8f,0xa6,0xe4,0x3f,0x4f,
+  0x83,0x1d,0xcd,0xf9,0xd1,0x45,0xf5,0xe9,0x1b,0x11,0xef,0x4d,0x5f,0x96,0x71,0x5b,
+  0x36,0x4f,0x04,0x9a,0x7e,0xaa,0x8d,0x27,0x3e,0xad,0x61,0x33,0xa3,0x19,0xa9,0xf8,
+  0x87,0x9f,0x26,0x95,0x8b,0x71,0x50,0xf0,0x7c,0x45,0x39,0xde,0x36,0xec,0xaf,0xeb,
+  0x5d,0xe4,0x93,0xb5,0x4d,0x50,0xaf,0xd3,0x42,0xbf,0x19,0xff,0x74,0xc1,0x15,0x2b,
+  0x1e,0x22,0x9f,0xd8,0x0e,0x07,0xa1,0x32,0x14,0xcf,0xff,0xa9,0x6c,0xb4,0x85,0xc4,
+  0x0f,0xc9,0x41,0x6d,0x4f,0x10,0xaf,0x98,0xf1,0x4f,0x14,0x46,0x11,0x61,0xd8,0x9a,
+  0x0a,0x0c,0xfe,0x1f,0xc5,0xc6,0x6a,0x26,0xea,0xdf,0xc5,0xa8,0x34,0x46,0x67,0x10,
+  0xdc,0x5a,0xd7,0xf8,0x7f,0x78,0xda,0x73,0x7b,0xac,0xda,0xcb,0x8b,0xfa,0xb1,0xdf,
+  0x50,0x94,0xdc,0x0d,0xa2,0xb5,0xb0,0x79,0xf7,0x5f,0xc3,0xff,0xb3,0x1c,0x76,0xfb,
+  0xec,0xd5,0xf2,0x66,0x52,0xa8,0xbe,0x85,0xf8,0xc4,0xc2,0xdd,0x0e,0xcf,0xc7,0xfc,
+  0x0f,0x1f,0x40,0x8b,0xd7,0xde,0x40,0x37,0x9b,0xeb,0xbf,0x04,0x5e,0x1d,0x66,0xd7,
+  0x16,0x6d,0x68,0x2d,0x54,0x9e,0xc4,0x69,0x0b,0x83,0x9e,0x21,0xda,0x02,0x59,0x31,
+  0xff,0xcf,0x33,0x30,0xb3,0x96,0x9e,0x4c,0xf1,0xff,0xa4,0xc5,0xb2,0x7f,0x79,0x7c,
+  0x67,0x03,0xc7,0xdb,0xdc,0x0d,0xb2,0x45,0xe3,0xf9,0xcf,0xd9,0x7f,0x84,0x67,0xf4,
+  0xfc,0x06,0x7a,0x6f,0x4a,0xfd,0x97,0x6f,0x22,0xdb,0x96,0xe7,0x9f,0x4c,0x8b,0x85,
+  0xbd,0x62,0xfe,0x07,0x51,0xc7,0x07,0x29,0x07,0xab,0x6e,0xf6,0xff,0xdc,0x34,0x84,
+  0xe8,0xc5,0xa8,0x76,0xff,0x1c,0x7e,0xcc,0xd3,0xea,0x12,0x81,0xb0,0x89,0xc2,0xff,
+  0x7f,0x4c,0xe1,0xff,0x49,0x1b,0x82,0xc3,0xd4,0x08,0x93,0xcd,0x81,0x4f,0xa4,0x05,
+  0x88,0x1f,0x5e,0x1d,0x92,0xc6,0x73,0x8d,0xf9,0xe7,0xb5,0x07,0xa4,0x52,0x2d,0x73,
+  0x30,0x85,0xff,0x27,0x1a,0x38,0xa1,0x95,0x80,0x1c,0x12,0x7f,0x00,0x11,0x52,0x02,
+  0x99,0xcd,0xd9,0xa7,0xb4,0x1e,0x04,0x42,0x32,0x43,0x79,0xd2,0xa3,0xda,0x29,0xf5,
+  0x5b,0x52,0xf0,0x8f,0xda,0x18,0xab,0x76,0x4f,0x83,0x2d,0x46,0x9a,0xb7,0xa7,0x3f,
+  0xb4,0x5d,0x75,0xc6,0xe2,0x5f,0x5b,0x2c,0x3e,0x4f,0x06,0xaf,0x7f,0x4f,0xe2,0x9f,
+  0xe6,0xdc,0x5f,0xf9,0x8c,0xd5,0x5e,0xae,0xb5,0x90,0x12,0x6d,0x51,0x10,0x92,0xf9,
+  0xe4,0x94,0x67,0x04,0xf1,0x7c,0x72,0x73,0xfd,0x17,0x1c,0x90,0x78,0x1a,0x8f,0xf8,
+  0x75,0x94,0xc6,0x25,0x3e,0x5b,0xa2,0xfe,0x9d,0x0f,0x78,0xc6,0x3b,0xda,0x0b,0xd7,
+  0xe0,0x1f,0xce,0xff,0xb3,0xa1,0xe9,0x75,0x15,0xf1,0xf0,0xc3,0x19,0x89,0xfa,0xf7,
+  0x98,0xff,0x87,0x0f,0x9a,0x52,0xfd,0x3f,0x63,0x3e,0x23,0xc8,0x98,0x0f,0x0e,0x5c,
+  0xf6,0x4c,0x5c,0x7f,0x25,0x02,0xc6,0x95,0xa8,0xce,0x03,0xaf,0x68,0x11,0x9b,0xf3,
+  0x9f,0x1d,0xb0,0x5f,0x42,0xb4,0x33,0xec,0x2f,0x87,0x3d,0x50,0x1c,0xe6,0xf9,0x6a,
+  0x84,0x07,0xc2,0x16,0x85,0xc8,0x05,0x58,0x17,0x28,0x68,0x76,0x0c,0xa7,0xc4,0xbf,
+  0x38,0xff,0x46,0xa1,0xbe,0xa8,0x70,0x61,0x06,0x97,0xcf,0xb5,0x8d,0xae,0x74,0x1e,
+  0x98,0x30,0xea,0x53,0x0e,0xc3,0x56,0xb5,0xe4,0x38,0xdd,0x46,0xcc,0xf9,0xcf,0x53,
+  0xb5,0x5d,0x2c,0x9f,0x47,0xab,0xbd,0x3c,0x30,0x04,0x79,0x0d,0xe4,0x5d,0x6d,0x8d,
+  0xc2,0x03,0xd9,0xe4,0x0f,0xb0,0x4a,0x9a,0xae,0x21,0x42,0x70,0x98,0xf0,0xcf,0xb4,
+  0xd0,0x97,0xb1,0x6c,0xe7,0x69,0xf0,0x67,0xb6,0xc0,0x97,0xb9,0x52,0xbc,0xa2,0xbe,
+  0x11,0xbb,0xf2,0x36,0xf9,0x94,0x55,0x85,0x50,0xbf,0xa4,0xe4,0x3f,0xb3,0xcf,0x24,
+  0x43,0x7a,0x84,0xb8,0x18,0xd1,0x0c,0x31,0x72,0x95,0xc5,0xe4,0x49,0xee,0x05,0x61,
+  0x1e,0x5f,0x28,0x73,0xfd,0xd7,0xa7,0xda,0x55,0x36,0x97,0xa7,0x15,0xed,0x21,0x6f,
+  0xa0,0x21,0x5f,0x1c,0xcb,0x7f,0xae,0x8a,0xe5,0x3f,0xbf,0x87,0x86,0xfc,0x92,0x71,
+  0xd1,0x9c,0xff,0xfc,0x74,0xf3,0xae,0xc9,0x88,0x5e,0x7e,0xda,0xad,0xa0,0xfd,0x75,
+  0xab,0x27,0xe3,0x7f,0x88,0x9b,0x61,0x07,0x67,0x04,0x7a,0x94,0x9c,0x00,0x7f,0xf0,
+  0xb6,0x88,0xbc,0x94,0xa4,0xe4,0x3f,0x33,0x03,0xed,0x3c,0x4c,0xda,0x79,0x21,0xbc,
+  0x46,0x63,0xf9,0x4e,0x0f,0xf0,0x2b,0x27,0x10,0x01,0xce,0xd4,0x70,0x60,0xf6,0xff,
+  0xf0,0x6c,0x1f,0xe0,0xd5,0xdf,0x80,0xf6,0x57,0xa1,0x4f,0xe0,0xf2,0x67,0x6f,0xcc,
+  0xff,0x33,0x0c,0xad,0x9c,0x48,0x61,0xaa,0xdf,0x9c,0xff,0xbc,0x0f,0xbf,0x7e,0x36,
+  0x2f,0xf2,0x62,0x9c,0xe6,0x48,0x43,0xfd,0xc5,0xf9,0x58,0xf8,0xfb,0x7e,0x6b,0x44,
+  0x7a,0x87,0x2b,0x9a,0xee,0x94,0x7c,0xa4,0x11,0x3a,0x5e,0xcd,0x2f,0x72,0xb7,0x0f,
+  0x4f,0x1b,0x4b,0x16,0xc2,0xe3,0x41,0x1b,0xd3,0x2a,0x19,0xae,0x8f,0xb9,0xfe,0xeb,
+  0x12,0x7c,0x49,0x11,0xe4,0x8c,0xd9,0x54,0xae,0xe6,0x34,0x2b,0x2f,0x02,0xe7,0xfe,
+  0x9f,0xac,0x51,0x3c,0x5f,0x87,0x95,0x52,0xc5,0x3a,0x96,0xea,0xff,0x51,0xf6,0xf6,
+  0xdb,0x75,0x79,0x81,0xc5,0xce,0xde,0xc1,0xfd,0xe0,0x30,0xf2,0x9f,0x8d,0xfa,0x1d,
+  0xf2,0x81,0x1a,0xa8,0xb3,0x4f,0xa6,0xed,0xc4,0xe4,0xff,0x11,0x9c,0x88,0x8e,0xec,
+  0x5c,0x3b,0xdb,0xb9,0x9a,0xf3,0x5a,0xc2,0xd9,0x03,0xb4,0x2d,0x96,0x38,0x1d,0x85,
+  0x16,0xb0,0x07,0x69,0xb7,0x3f,0xd5,0xff,0xb3,0x5d,0xf0,0xf5,0xca,0x2e,0xbf,0x4a,
+  0x1e,0x47,0x1d,0x6f,0x71,0xdb,0x07,0x94,0xad,0x79,0xb8,0x03,0xdd,0x44,0x27,0x2c,
+  0x23,0xc4,0xae,0xf1,0xff,0xfc,0x24,0xc6,0x06,0xd0,0x4d,0x54,0xe3,0x35,0xb3,0xc2,
+  0x3c,0x7f,0x5b,0x75,0xf3,0x81,0x0e,0x07,0x34,0x37,0x58,0xbb,0x9b,0xcc,0xf8,0xe7,
+  0x52,0xed,0x97,0x1c,0xe6,0x85,0x63,0xfa,0x5d,0x2b,0xde,0xc9,0xf3,0x7b,0x39,0xfe,
+  0x39,0x8f,0x57,0xc6,0x1c,0x55,0x80,0xf2,0xc7,0xe4,0xff,0x99,0x72,0x05,0x61,0xf9,
+  0xdc,0x83,0x59,0x67,0xc5,0x8a,0xf0,0x49,0xa8,0x2a,0xb4,0x1e,0x10,0xdd,0xd2,0x61,
+  0x8e,0x9f,0x7b,0x6a,0xce,0xc1,0x97,0x6c,0xae,0x8a,0x78,0xc0,0xec,0xff,0xf9,0x94,
+  0xb4,0xb1,0x82,0xb3,0xf4,0x2c,0x59,0x20,0x05,0x06,0x9d,0x94,0x6e,0xc4,0x07,0x6b,
+  0x34,0xe2,0x5f,0xf6,0xd3,0xbc,0x50,0x4e,0x45,0xe0,0x67,0xf6,0xff,0x8c,0xd0,0x17,
+  0x49,0x21,0x8f,0x87,0xe2,0x41,0x33,0xc0,0x1f,0x81,0xae,0x46,0x87,0x11,0x8f,0x78,
+  0x3d,0x63,0x2f,0x14,0x82,0x0c,0xc4,0x1c,0xff,0xfa,0xad,0xf4,0x22,0x2c,0xc3,0xf9,
+  0xca,0x0a,0x78,0x9e,0xa2,0x7d,0x17,0xc6,0xfb,0xb7,0x18,0xf1,0xc4,0xec,0x68,0xf5,
+  0x5e,0xb0,0xe7,0xa3,0xa0,0x33,0xf9,0x7f,0xd2,0xfe,0xa2,0xbe,0x8a,0x5f,0x67,0x71,
+  0x98,0xac,0xc8,0xc5,0xaf,0x5f,0xeb,0x64,0x93,0x66,0x90,0x88,0x62,0xc4,0x5f,0x3e,
+  0x82,0xf1,0xf4,0xb2,0x3a,0xdb,0xf3,0xd7,0xf8,0x7f,0xde,0x0d,0x2d,0xd0,0x8b,0x47,
+  0x17,0xe1,0x00,0x66,0xf9,0x6c,0x83,0xb7,0x7c,0xa1,0x5d,0x62,0x06,0x11,0xd0,0x18,
+  0xbc,0x17,0x42,0x89,0x3d,0x66,0xae,0xff,0x82,0x90,0xf6,0xb1,0x64,0xac,0xf6,0x00,
+  0x6a,0x43,0x44,0x3b,0x21,0x71,0x06,0xd7,0x08,0xb1,0x7c,0xfb,0x0f,0xa1,0x8c,0x5d,
+  0x93,0xff,0x63,0x85,0x36,0xbd,0xe0,0x04,0x8c,0xda,0x2b,0x78,0xfc,0xf4,0x11,0xda,
+  0xd3,0xfa,0x75,0xad,0xa7,0xc1,0x88,0x87,0x7e,0x08,0x3b,0xa6,0x76,0xf8,0xe5,0xb0,
+  0xdf,0x1c,0xff,0xba,0xdb,0x55,0xc0,0xd4,0x13,0x16,0x0e,0x7b,0xd0,0x30,0xe7,0x81,
+  0x45,0x07,0x27,0x46,0x30,0xf0,0xa1,0xba,0x15,0x0a,0x43,0x87,0xe8,0x75,0x63,0x29,
+  0xfe,0x9f,0xf5,0x83,0xea,0x70,0xdd,0x4a,0xfb,0x3a,0xd6,0xcc,0x10,0xed,0x9c,0x20,
+  0x37,0x70,0x89,0xc4,0xeb,0xa1,0xfe,0xa0,0xbd,0xcc,0xf2,0x43,0xf2,0xdf,0xa5,0x9f,
+  0x30,0xf3,0xff,0xc0,0xfb,0x81,0xf0,0x70,0x56,0x58,0x5e,0x07,0xaf,0xaa,0x15,0x9d,
+  0xd6,0x7c,0x91,0x6a,0x9f,0x81,0x4b,0xff,0xfb,0xf9,0x35,0x03,0xf0,0x3e,0xcc,0xd1,
+  0x6c,0xf9,0x29,0xf1,0xaf,0xcd,0x70,0x59,0x99,0xdf,0x6f,0x1b,0x2d,0x58,0x80,0x66,
+  0x02,0xc2,0x80,0x87,0xc4,0x31,0x9e,0x61,0x68,0xc4,0x07,0xd5,0xbd,0xbc,0xb4,0xe7,
+  0x54,0x4e,0x2a,0xfe,0xf9,0xbd,0xdf,0x75,0x6c,0x6d,0x58,0x7c,0x40,0x7f,0x12,0xf7,
+  0xe7,0xcd,0x8c,0x13,0x31,0x19,0xe7,0x31,0xe7,0xfd,0x19,0x87,0xa0,0x2c,0x72,0xf3,
+  0xda,0xa6,0x6b,0xfc,0x3f,0x90,0x7f,0xc2,0x31,0xc7,0x3f,0x15,0x9e,0x45,0xfc,0x93,
+  0x85,0xf6,0x17,0x5e,0x31,0xe4,0xe7,0x71,0x58,0x23,0xbd,0xa4,0xa3,0xfd,0x68,0xc6,
+  0x3f,0xfb,0xe1,0x9f,0xd9,0x96,0x61,0xcb,0x4a,0x72,0x77,0x23,0x87,0x79,0x87,0xea,
+  0x11,0xf6,0xac,0x66,0x46,0xda,0xcf,0x15,0x8e,0x88,0x46,0xe4,0x8b,0xd9,0x29,0xf8,
+  0x47,0x6a,0xd2,0x54,0x7d,0x21,0xdf,0x6f,0x3c,0xfe,0x6e,0x84,0x11,0xfd,0x71,0xff,
+  0xb3,0xd6,0xa4,0x17,0x9e,0x90,0xcb,0xaf,0x33,0xe3,0x9f,0x1e,0x78,0x57,0x73,0x31,
+  0x6b,0xa8,0xa6,0x1e,0xde,0x55,0x2b,0x83,0x71,0xd8,0x63,0xe4,0xff,0x7c,0x04,0xaf,
+  0x9f,0x78,0xb9,0xcb,0xf6,0x82,0x9c,0xe2,0xff,0x61,0x63,0xae,0x4a,0x25,0x2d,0x56,
+  0x0f,0x5e,0x49,0xf0,0x7d,0xa3,0xea,0x25,0x1a,0xf3,0xff,0xc0,0x58,0xad,0x61,0xa1,
+  0xa7,0xe0,0x1f,0x72,0x80,0x55,0x36,0x58,0x15,0xb9,0xd9,0x72,0x00,0xa6,0x69,0x8b,
+  0x83,0xc2,0x19,0x76,0x40,0x99,0x20,0xba,0xd1,0x63,0xf2,0xdc,0x84,0x7f,0x6e,0x57,
+  0x5a,0x58,0x49,0xfd,0x44,0xfe,0x49,0x43,0x71,0xbb,0xfd,0xcf,0xa4,0x45,0x7f,0x19,
+  0x15,0x31,0xf9,0x24,0xf0,0xa1,0x6e,0xd7,0xdb,0x7a,0x4c,0xfc,0x63,0x79,0x69,0x85,
+  0xa4,0x65,0xf2,0x0c,0xcd,0xc1,0x69,0x7f,0x5a,0x24,0x67,0x1d,0xee,0x87,0xe3,0xb0,
+  0x0a,0x96,0xf1,0x0c,0xde,0x33,0x9c,0xb8,0xa6,0xfa,0xd0,0x46,0x4f,0x6a,0xfc,0x8b,
+  0xe3,0x81,0x58,0xfe,0x0f,0x14,0x37,0x5c,0x7f,0x2f,0xf9,0x23,0xac,0xd2,0x0b,0x0d,
+  0x60,0xc0,0x13,0xcf,0x7c,0x6d,0xae,0x14,0xfc,0x53,0x0f,0xbc,0xcc,0xca,0xca,0x08,
+  0x0f,0xc4,0x54,0x02,0x45,0xd8,0x03,0x03,0x88,0x88,0x26,0xb1,0x1c,0x9e,0x88,0xbb,
+  0xe7,0x9a,0xf8,0xd7,0x4d,0xc7,0xc9,0x65,0x14,0x83,0xb6,0x4d,0x05,0x1f,0x50,0x0e,
+  0x84,0xe2,0x7c,0x38,0xc6,0x6b,0xf6,0x53,0xce,0x08,0xb4,0x5e,0x29,0x30,0xe3,0x9f,
+  0x93,0xf0,0x27,0x61,0xee,0x9d,0xce,0xc7,0xc5,0xe5,0x08,0x0b,0x67,0x79,0xad,0x6f,
+  0x22,0x70,0x3a,0xac,0x95,0x6a,0x03,0xfc,0x1f,0x5e,0x36,0x1c,0x29,0x62,0x6a,0xfd,
+  0x57,0x80,0x27,0x0d,0xae,0x11,0xf3,0x23,0x5d,0x50,0x82,0x68,0x07,0xc5,0x2c,0xe3,
+  0x66,0x11,0x5b,0x16,0xcd,0xeb,0x21,0x3c,0x22,0x46,0x8e,0x98,0xf8,0xc7,0x06,0x60,
+  0xbb,0xa4,0x7e,0x13,0x85,0x6a,0x6d,0x7e,0x23,0xc2,0x3c,0x07,0xc2,0x1e,0x7f,0x93,
+  0x6a,0xa4,0x3d,0x0f,0xa0,0x8d,0xc8,0x13,0x81,0x3c,0xa6,0xf8,0xd7,0xe4,0x67,0xc8,
+  0xf3,0xbe,0x8e,0x58,0xf6,0xf8,0xf3,0x3c,0x91,0x23,0x48,0xfa,0xb9,0xfc,0xe1,0x19,
+  0x41,0x1f,0xc0,0x6e,0xcd,0xae,0x1f,0x4a,0x89,0x7f,0x4d,0x79,0x43,0x1b,0xd7,0xdd,
+  0xda,0xda,0xa0,0xb8,0x3c,0xef,0x40,0x61,0xa5,0x66,0x6d,0xe7,0x81,0x4e,0x7c,0x6c,
+  0x67,0x50,0xfc,0xa0,0xf6,0xac,0xd6,0x5d,0x67,0x6b,0x6f,0x4a,0xa9,0xff,0x22,0x6f,
+  0x19,0xfc,0x87,0xf2,0x10,0xfc,0x58,0xe7,0xf9,0x3f,0xa9,0xf8,0x67,0xff,0x42,0xbc,
+  0x72,0x4d,0xfe,0xb3,0x54,0x4e,0xb2,0x40,0xd4,0x29,0xe2,0x6d,0x62,0x35,0xf2,0x7f,
+  0x54,0x77,0x7c,0xbf,0x79,0x8d,0x81,0x39,0xfe,0x75,0x1b,0xa4,0x6b,0x05,0x41,0x1a,
+  0xca,0xe6,0x34,0x56,0x36,0x1c,0x90,0xdb,0x60,0x9d,0xb6,0x85,0xc9,0xd1,0xec,0x61,
+  0xba,0xbf,0xb9,0x23,0x2c,0x87,0x3c,0x29,0xf1,0x2f,0xd2,0x74,0x50,0x0d,0xc7,0x68,
+  0xb2,0x24,0x2b,0x2f,0x7b,0xb7,0xb1,0x16,0x50,0x99,0xac,0x1a,0xf1,0xaf,0xd0,0xa8,
+  0xec,0x4e,0xa9,0x7f,0xaf,0xe0,0xd1,0x1f,0x3f,0x87,0x01,0x08,0x0c,0x8a,0xbd,0xf4,
+  0x27,0xf6,0x29,0xb0,0x86,0xe4,0x37,0xa2,0x45,0x73,0x02,0x5e,0x81,0xfc,0x3e,0x5e,
+  0xff,0x9e,0xcc,0xff,0xa1,0xd3,0xd2,0xdf,0x60,0xae,0x50,0xd6,0xca,0xa6,0x77,0x03,
+  0x5f,0x22,0xda,0x71,0x9e,0x90,0xe7,0x91,0xd7,0xd9,0xf6,0x90,0xad,0x5e,0xfc,0x83,
+  0xfa,0xa5,0x7f,0x76,0xa7,0xed,0x07,0xf8,0xbe,0x13,0x7f,0xbc,0xfe,0xeb,0x2c,0xec,
+  0x67,0xeb,0x5f,0x16,0x47,0x34,0xb4,0x37,0xd9,0x2c,0x9e,0x46,0x38,0x06,0x3f,0xc3,
+  0xf3,0x58,0xf0,0x01,0xfb,0x0c,0x7f,0xc2,0xf7,0x35,0xe5,0xff,0xa4,0xbd,0x6d,0xa4,
+  0x6d,0x3c,0x36,0xde,0x54,0xc9,0xd1,0xce,0x90,0x95,0xfb,0x7f,0x0e,0xac,0x72,0x77,
+  0x5a,0x87,0x73,0xae,0xd4,0x7e,0xce,0x76,0x9c,0xb2,0xf6,0xa4,0xe0,0x9f,0xcd,0xb5,
+  0x8d,0x4a,0x88,0x39,0xce,0x5a,0xac,0xd9,0x6b,0xc0,0xee,0xa0,0x5e,0x32,0x08,0xeb,
+  0xba,0xf2,0x3b,0xa9,0x4f,0x3c,0x81,0x88,0x6e,0x4b,0x2d,0xfd,0x1f,0xa9,0xf8,0x87,
+  0x87,0xe9,0x59,0xc6,0x43,0xe9,0x9b,0xb5,0x26,0x4e,0x83,0xe0,0xc5,0xf3,0xf5,0x84,
+  0x3a,0x3d,0x90,0xe1,0x23,0xf7,0x0a,0xbb,0x94,0x02,0x9d,0xa6,0xe2,0x9f,0xc3,0x7a,
+  0xa3,0x56,0xc8,0xa8,0x2b,0x7d,0x1b,0x3c,0xae,0xa9,0xe0,0x08,0xfa,0xa3,0xb4,0x1d,
+  0x0a,0x59,0x86,0x4a,0xfa,0xd3,0x76,0x68,0x21,0x8d,0x66,0xa7,0xd4,0x7f,0x3d,0x06,
+  0x07,0x6a,0xe7,0x30,0x34,0x93,0xf7,0xd1,0x77,0xd4,0x79,0xba,0x75,0xe7,0x37,0x46,
+  0xe0,0x2d,0x14,0xe4,0xc5,0x21,0xf1,0x13,0xb8,0x18,0xc5,0xad,0xb5,0x29,0x25,0xfe,
+  0xf5,0x09,0x8c,0x1f,0xe4,0xb4,0x00,0x84,0xd3,0x42,0xa2,0x7c,0x0e,0x8b,0x1f,0xd2,
+  0x8f,0xb4,0x79,0x2c,0x2b,0x24,0x76,0xa9,0x17,0x39,0xbf,0x44,0xf8,0x1a,0xfc,0x73,
+  0x18,0xba,0x19,0x4f,0x1b,0xce,0x7d,0xc3,0xca,0xeb,0xdf,0x0b,0x2a,0xe0,0x28,0x2d,
+  0xe5,0x19,0x20,0x7b,0xd8,0x15,0xcb,0x5c,0x90,0xf5,0x14,0xfc,0xf3,0x8f,0xb0,0x85,
+  0xd9,0x43,0x34,0x6c,0x77,0xc2,0x3b,0xc4,0x1e,0x76,0xf4,0x90,0x5b,0x68,0x60,0xd0,
+  0xce,0xf7,0x83,0x83,0xee,0xa8,0x76,0xcf,0xe1,0x8c,0x5b,0x26,0xfc,0x53,0x62,0x6f,
+  0xd1,0xff,0x61,0x2b,0x75,0x79,0x78,0xbc,0xac,0xb0,0x2e,0x63,0x03,0x99,0xce,0x5e,
+  0xa4,0x46,0xbe,0x59,0x27,0x3c,0xaf,0xe1,0xc0,0x9f,0xe2,0xff,0x29,0x84,0x10,0xf8,
+  0x82,0x06,0xfb,0xcd,0xe3,0xa0,0x0a,0x78,0x0c,0x71,0x57,0x41,0xc8,0xbf,0xa8,0xd0,
+  0x43,0xa4,0xbd,0xb8,0x90,0x68,0xba,0x9a,0xf1,0xcf,0x0a,0x38,0xe0,0x75,0x0f,0x5a,
+  0x47,0x73,0x7e,0xc3,0x69,0x67,0x16,0x5b,0x83,0x44,0xe2,0x40,0x91,0x19,0x34,0x8f,
+  0x17,0xf0,0xd5,0xb8,0x21,0x96,0x90,0x3f,0x9d,0x37,0x9d,0x87,0xf3,0x50,0x15,0x98,
+  0x85,0xda,0x2a,0x84,0x30,0x32,0x13,0x0d,0xb1,0x51,0x7a,0x52,0x59,0xc0,0x6c,0xa7,
+  0x51,0x4d,0x5f,0x15,0x6e,0x03,0x5b,0x7f,0x0a,0xfe,0xf9,0x14,0xd1,0xf2,0xdc,0x50,
+  0xd6,0x58,0xcd,0xdb,0x30,0x80,0x6a,0x0e,0x17,0x6a,0x4c,0xc5,0x8d,0xdf,0x9f,0xd5,
+  0x23,0x5e,0x62,0x97,0xdd,0x55,0x0b,0xad,0x63,0xb2,0x2b,0x21,0x1f,0x18,0x7c,0x0a,
+  0x7b,0x79,0x12,0x72,0x37,0xf9,0x14,0xde,0xf6,0xcf,0x3a,0x41,0xbf,0xf4,0x9f,0x22,
+  0x81,0xfa,0x82,0x13,0xb8,0x50,0x57,0xb4,0xbd,0xca,0x83,0x75,0xb8,0xdf,0x5c,0x89,
+  0xf5,0x77,0xa4,0x71,0xf4,0x1b,0x62,0x16,0x57,0xc7,0x41,0xd8,0x20,0x38,0x8f,0x19,
+  0xf5,0x4d,0xad,0x4a,0xac,0xf0,0x0d,0x76,0xd8,0x1d,0x07,0x71,0x29,0xdc,0x89,0xf9,
+  0x3a,0xea,0x53,0xbc,0x7f,0x3b,0x0d,0x67,0x7f,0x04,0x4f,0xa2,0xfc,0x09,0x84,0xc9,
+  0x90,0xda,0x4a,0x79,0xc5,0x3d,0x2f,0x84,0x67,0x25,0xe1,0x8c,0xb0,0xc9,0xff,0x03,
+  0xd2,0x36,0xeb,0xf6,0xba,0xb2,0xd1,0x2c,0x8e,0x76,0x22,0x81,0x4a,0xdd,0xc9,0xbf,
+  0xfe,0x41,0xcd,0xdd,0x6b,0x24,0xce,0xed,0x0e,0x4d,0x8b,0x3a,0xc2,0xa2,0x92,0xd8,
+  0xff,0x5b,0xc0,0x48,0xeb,0x0d,0x71,0xb4,0x23,0x5d,0xd1,0xb8,0x5a,0x47,0xb0,0x72,
+  0x85,0xeb,0xeb,0xd1,0x82,0x11,0xb8,0x42,0x2b,0x39,0x30,0x1e,0x36,0xe9,0xdf,0x6d,
+  0xca,0x78,0x34,0x96,0xcd,0xab,0xdd,0xa9,0xf2,0xf8,0x57,0x4d,0x3e,0x1c,0x24,0x2e,
+  0xdd,0x28,0xc4,0x3b,0xe8,0x9d,0xd7,0x8e,0x83,0xb3,0x49,0xfc,0x73,0xbb,0x13,0xf6,
+  0x6a,0x25,0x51,0x44,0x3b,0x07,0xe1,0xf9,0xc0,0x2c,0xfd,0xae,0x51,0xd2,0x85,0xfa,
+  0xf7,0xbf,0xf6,0x1a,0x8e,0xa6,0x56,0x36,0x23,0x40,0x5d,0xe2,0xcb,0x49,0xfe,0xe7,
+  0x5c,0xee,0x9f,0x29,0xe9,0x96,0x5d,0xe9,0x11,0x95,0xe9,0x4e,0x5e,0x7f,0x9a,0xc1,
+  0x18,0x14,0xf6,0x52,0xbe,0x3e,0x8d,0x8d,0x25,0x0d,0x38,0x18,0x4d,0xd8,0xfb,0x3e,
+  0x98,0xc6,0x10,0x06,0x84,0xd0,0x5a,0xb9,0x00,0xcf,0xb2,0xe2,0xa1,0x8c,0x47,0xd3,
+  0x37,0x6a,0xcd,0xc1,0xe2,0xa8,0xe5,0x51,0xf2,0x2e,0x59,0x1d,0x9e,0xae,0xd2,0x47,
+  0xf1,0x3f,0x34,0xf1,0x57,0x97,0x97,0x25,0xed,0x10,0x2a,0xfc,0xeb,0x6f,0x13,0x23,
+  0xb5,0x7e,0x52,0xf9,0x5a,0xe6,0x9e,0x1a,0x07,0x59,0x18,0x44,0x44,0x3a,0x4f,0x1c,
+  0x90,0xfa,0xfc,0x3f,0x89,0x38,0xe7,0x89,0xc7,0xd2,0x27,0xe6,0x6b,0x8b,0x0d,0xff,
+  0x0f,0x4f,0xf2,0x19,0xc5,0xd5,0xa8,0x7a,0xcd,0x36,0xda,0x84,0x03,0x32,0x7f,0x70,
+  0xfd,0x59,0x04,0xd2,0x57,0xa4,0x9f,0xf3,0x9f,0x82,0x64,0xe2,0x7d,0x11,0xdf,0xc2,
+  0x67,0xcc,0x28,0xf2,0xaa,0x87,0x71,0xb5,0xec,0xb2,0xf5,0x65,0x31,0x4a,0x0f,0xc1,
+  0x9e,0xf3,0xd6,0x30,0xf9,0x0b,0x3b,0x10,0xfb,0xa9,0x2f,0xb1,0xfe,0xc3,0xc2,0x66,
+  0xee,0x3d,0x66,0x32,0xcf,0x76,0xde,0x65,0x29,0xee,0x43,0x6b,0x71,0x8c,0x3e,0x07,
+  0x6a,0x24,0xb3,0x81,0x1c,0xee,0xe8,0x87,0x7c,0x90,0xcd,0xfc,0xcf,0x00,0x9c,0xed,
+  0x79,0x7a,0x48,0x5e,0x79,0xc7,0xdb,0xf0,0x04,0x73,0x0e,0x67,0x3c,0x4a,0xfe,0x40,
+  0xfc,0xac,0x78,0x98,0xae,0x4c,0x7f,0x97,0x06,0xf5,0xfc,0xd0,0x8d,0x2b,0xd1,0x34,
+  0x9b,0x78,0x1e,0xee,0xff,0xe9,0x66,0x85,0x5d,0x72,0xf8,0xba,0x83,0xea,0x8e,0x3a,
+  0xa7,0xde,0xe2,0x22,0x47,0x7c,0x1d,0x11,0x5e,0xd8,0x6b,0x1f,0x40,0xf4,0x1d,0xe2,
+  0xf9,0x3f,0x6f,0x9b,0xea,0xbf,0xba,0xf0,0x35,0xe7,0x76,0xa1,0x74,0xfd,0x4f,0x8d,
+  0x17,0x84,0x32,0x36,0x33,0x84,0x30,0xf8,0x48,0xff,0xcf,0x10,0x11,0xa1,0xbd,0xf6,
+  0xb4,0x56,0xea,0x97,0x43,0xe2,0x1e,0x61,0xe2,0x79,0xea,0x14,0x15,0xc6,0x7a,0xb9,
+  0xd2,0xcf,0x89,0x95,0x7d,0x19,0xfe,0x90,0xb1,0xc9,0xfb,0xe3,0xfe,0x1f,0xad,0x92,
+  0x4c,0x62,0xe2,0xb1,0x64,0xfe,0xad,0xd2,0xa9,0xa0,0xbd,0xdf,0x30,0x29,0x28,0x4e,
+  0x07,0xce,0x06,0x6c,0x53,0x20,0x1d,0xee,0xe4,0xf5,0x89,0x86,0xbe,0xd3,0x2a,0xeb,
+  0x96,0x04,0x73,0x4c,0xf8,0xa7,0xb6,0x13,0x76,0xaf,0x2d,0xe1,0x41,0xab,0x42,0x69,
+  0x2b,0x23,0x5a,0x5b,0xd0,0x33,0x03,0x15,0x31,0xcf,0x7f,0xce,0x1e,0x82,0x27,0xfb,
+  0x1e,0xf4,0xb6,0x71,0xfe,0xe7,0x89,0x3f,0x23,0xff,0x27,0xbf,0x44,0xab,0x09,0xc2,
+  0xf2,0xc2,0x16,0x6a,0xd4,0x2b,0x75,0xd6,0x6d,0xc7,0xf9,0x6d,0x38,0x9f,0xee,0x16,
+  0x4a,0x8c,0x7c,0x95,0xd4,0xfc,0x43,0xc9,0xe9,0x95,0x73,0x8b,0x24,0x3a,0x13,0x42,
+  0x3c,0xdb,0x67,0x15,0x6c,0xd7,0xc0,0x2b,0x2b,0x4a,0x3f,0x6c,0xd0,0xf0,0x27,0xb3,
+  0xfd,0x55,0x3e,0xd5,0x37,0x51,0xe6,0xa6,0x2a,0x11,0x92,0x1d,0x23,0x02,0xe2,0x1e,
+  0xa1,0x35,0xac,0x34,0x0a,0x17,0x84,0x12,0x58,0xc2,0x26,0x7d,0x9a,0x90,0x3f,0x3d,
+  0x99,0x9d,0x08,0x5a,0xaa,0x0c,0xef,0x0d,0xda,0x6b,0x1c,0x08,0x2d,0xfa,0x6f,0xd2,
+  0x27,0xda,0x7e,0xaf,0x51,0x08,0x7f,0xd9,0x33,0x17,0x07,0x93,0x3e,0x4d,0xc8,0x9f,
+  0xf2,0xbf,0xe9,0xa4,0x9f,0xc3,0xfc,0x5a,0xba,0xa9,0xe6,0x3c,0x87,0x01,0x0b,0x79,
+  0xda,0x33,0xc7,0x87,0x8b,0xac,0xdc,0x7f,0x75,0x19,0x4a,0xbf,0x63,0x1d,0x14,0x3f,
+  0x4d,0xec,0x9f,0x3c,0x9e,0xff,0x0c,0x76,0xea,0x60,0xd9,0x51,0xda,0x23,0xcd,0xcb,
+  0x93,0xfd,0x1b,0x01,0x02,0xde,0x8e,0xbc,0x4c,0x46,0x4e,0x79,0x7b,0xd4,0x0e,0x05,
+  0x2d,0x88,0xd7,0x13,0xf2,0x44,0xe3,0xf9,0x4e,0xe0,0xe0,0x4a,0xa7,0x9f,0xbb,0x01,
+  0x3d,0x72,0xae,0xe5,0x19,0x4e,0x04,0xe4,0xc9,0x33,0x88,0x10,0x23,0xaa,0x76,0x83,
+  0x42,0x8e,0x25,0xf6,0x4f,0x9e,0xc4,0xb3,0xa7,0x78,0x91,0xbb,0x7d,0xc8,0x17,0xa7,
+  0x3d,0x2c,0xa4,0x8d,0x3e,0x7b,0x3c,0xff,0x0a,0xec,0xd5,0x16,0x5e,0xff,0x3e,0x31,
+  0x3f,0xc4,0xe7,0xd3,0x72,0x0d,0x9f,0xf6,0x8c,0x32,0x3e,0x58,0xc9,0xd1,0x5a,0xa7,
+  0x7a,0x00,0x3a,0x34,0x89,0xcf,0x1f,0x97,0xec,0xf5,0x16,0x1e,0xca,0x99,0x98,0xff,
+  0x11,0xaf,0xff,0x82,0xfd,0x75,0xeb,0x11,0x06,0x73,0x7e,0x1b,0x44,0x83,0x39,0x43,
+  0x64,0x9c,0x55,0xc4,0xf2,0xc1,0xce,0x7a,0x2a,0x97,0x67,0x06,0xc5,0x0b,0x49,0x3c,
+  0xc3,0xf9,0x36,0x95,0x79,0x0a,0xa7,0xfd,0x51,0xe2,0x6e,0xb7,0x7c,0x3d,0x52,0xed,
+  0x16,0x16,0x1b,0xf9,0x3f,0xe0,0x56,0xad,0x66,0xfc,0x43,0x25,0x07,0x9c,0x01,0x83,
+  0xf6,0xe7,0xa2,0x91,0xff,0x8c,0x6a,0xe8,0x57,0xf0,0xb6,0x60,0x67,0x16,0xbe,0x9f,
+  0xf7,0xeb,0x5b,0x99,0x35,0x4a,0xfa,0x12,0xfb,0x87,0xfe,0x82,0x97,0x9d,0x3a,0x74,
+  0x87,0x8b,0x1c,0x62,0x5b,0x63,0x66,0x82,0x8d,0x26,0x0a,0xb7,0xc3,0xd1,0x19,0xaa,
+  0xa0,0xe2,0xfc,0x89,0xef,0x9b,0x3f,0x79,0x2a,0x5a,0x24,0x05,0xcc,0xd2,0x60,0xbf,
+  0x10,0xab,0x5f,0x70,0x5b,0x36,0x2b,0x4f,0x28,0x31,0x22,0x0b,0xd8,0xa9,0xa9,0x0a,
+  0xe5,0x8c,0x09,0x13,0xfb,0xcd,0x51,0x37,0x4d,0xf9,0x9c,0xdd,0x16,0xb5,0xfc,0x44,
+  0x7c,0x17,0xfe,0x1c,0xb8,0x69,0x74,0xc9,0x4f,0xda,0xa6,0xc1,0x7a,0xb6,0xc3,0xa8,
+  0x7f,0x87,0x2b,0xec,0xd6,0x10,0xe7,0x3f,0x4c,0xc8,0x1f,0x3a,0x79,0x1b,0x7c,0x08,
+  0x15,0x2c,0xb3,0x47,0x8c,0xa0,0x84,0xab,0x3c,0xc1,0xcd,0x4c,0xe9,0x62,0x5d,0x65,
+  0xdf,0x44,0x22,0x34,0x2a,0x7a,0x53,0xfe,0x8f,0x4f,0xda,0x8f,0xfa,0xab,0x34,0x62,
+  0x1d,0xff,0xde,0xdb,0xca,0xd1,0xe6,0xaa,0x51,0xeb,0x98,0xe8,0xe6,0x57,0x4e,0x5b,
+  0xb9,0x23,0x68,0x2c,0x58,0xa5,0xae,0x1f,0x36,0xd5,0x47,0x04,0x60,0xaa,0xf6,0x72,
+  0xde,0xad,0x7e,0x3a,0xdb,0x3d,0x28,0xad,0xc9,0x2b,0xd6,0xeb,0x66,0x67,0x2b,0xf0,
+  0xb1,0x5a,0x10,0xcd,0xe4,0xfe,0xe7,0x70,0xe8,0x01,0x2a,0xe7,0x93,0xa2,0xc4,0x7a,
+  0x32,0xd8,0x0c,0x2f,0x01,0x82,0x9c,0x87,0xd2,0xc7,0xd4,0x55,0x1c,0x0f,0x37,0x90,
+  0x3c,0x6d,0x97,0x50,0x60,0x04,0xee,0xe1,0x65,0xb5,0xf8,0xd8,0x8d,0x3e,0x8b,0x94,
+  0xe0,0x3f,0xd4,0x72,0xd7,0xe2,0x69,0x2a,0xec,0xa2,0x2e,0xfb,0x41,0xc2,0x8c,0x44,
+  0x68,0x0b,0xe5,0x69,0x54,0x31,0x62,0x81,0xdd,0xed,0x4e,0xdf,0x8d,0x2a,0xc9,0x36,
+  0xe1,0xd5,0x6d,0x5c,0x7e,0x8e,0x5a,0x47,0x85,0x03,0x70,0x20,0xa6,0x7f,0x4b,0x50,
+  0x43,0x15,0xa0,0x7e,0x41,0x7d,0xb7,0x47,0x2b,0x09,0xe1,0x17,0xa4,0x09,0x3c,0x1c,
+  0x52,0x46,0x60,0xdc,0x6e,0xd4,0x7f,0x0d,0xab,0xdc,0x1f,0xb2,0xde,0x25,0x7e,0xa8,
+  0x7d,0x3c,0xe1,0x6f,0xbf,0x40,0x2a,0x79,0x61,0xd4,0xb0,0x64,0xc6,0x3f,0x57,0x59,
+  0x41,0xad,0x51,0xf6,0x7e,0x54,0x37,0xcc,0xd8,0x39,0xec,0xe8,0x44,0x21,0xfc,0x15,
+  0x28,0x65,0x59,0x51,0x31,0x9a,0xc0,0x3f,0xbd,0xd2,0x0a,0x69,0xf7,0xdb,0x8e,0x41,
+  0xd4,0xb6,0x1f,0x71,0xb7,0x61,0x6f,0x5b,0x98,0x14,0xf0,0xc4,0x1e,0xce,0x88,0x38,
+  0x42,0xf7,0xf2,0xd0,0x4f,0xc8,0x6e,0xc2,0x3f,0x92,0x51,0xa6,0xdd,0x87,0x4a,0xf9,
+  0x23,0x6e,0xaf,0x71,0x37,0x85,0x64,0x14,0xfe,0xc7,0xf4,0xb5,0x6e,0xef,0xc0,0x8d,
+  0x67,0xe2,0x3f,0x84,0x4c,0x4e,0xb3,0x09,0x19,0x73,0x70,0x93,0x34,0x09,0xb8,0xdf,
+  0xe6,0x10,0x48,0xc7,0xf9,0x11,0x3a,0x1b,0xd7,0x67,0xbb,0x1a,0xd2,0x10,0x68,0xf5,
+  0x25,0xfa,0x59,0x40,0xde,0x03,0xbc,0xac,0x5b,0x2b,0xde,0x59,0x30,0x0c,0x07,0x78,
+  0x18,0xe2,0x11,0xb9,0x10,0x8e,0x4e,0xfe,0x91,0xbe,0x38,0x5c,0x83,0xfb,0x21,0xd7,
+  0xad,0x67,0x6d,0x11,0xa3,0x89,0xfa,0x9d,0x50,0xe6,0x25,0xf6,0x25,0x2c,0xd0,0xb3,
+  0xce,0x15,0x8c,0x71,0xfe,0x1f,0x7d,0xfd,0xb9,0x9a,0x51,0x8a,0x40,0xa8,0x9f,0xe7,
+  0xff,0xc0,0x65,0x17,0x8a,0xa6,0x65,0xe2,0x70,0x73,0x02,0xff,0x08,0xc7,0xa0,0x9f,
+  0xcd,0x8e,0x2e,0x1e,0xcd,0xf9,0x29,0x9c,0x64,0x06,0xff,0x0f,0xe7,0x8f,0x2a,0x1d,
+  0x28,0x79,0x5d,0x74,0xb1,0xf7,0x58,0xa9,0x68,0xed,0x37,0xf3,0xff,0xc0,0x19,0x25,
+  0x03,0xf1,0x61,0xdd,0xcb,0xd9,0xc5,0x7d,0x01,0xd5,0x1e,0xcd,0xe0,0xfc,0xcf,0x7b,
+  0x0b,0xdd,0x4a,0x71,0x30,0x5b,0x0d,0xb5,0x51,0x37,0xe7,0x9f,0x4f,0xd6,0x7f,0xd1,
+  0xb4,0x21,0x34,0x33,0x1d,0x3a,0x9d,0xf3,0xec,0x00,0x04,0x68,0xfc,0x58,0xed,0xa5,
+  0xea,0xa0,0x9c,0x4e,0x40,0x7f,0x11,0xba,0x08,0x95,0xcc,0xf5,0x5f,0x53,0x9e,0x81,
+  0x16,0x56,0x84,0xf8,0x13,0xf1,0x24,0x77,0xfb,0x64,0xc4,0x60,0xcf,0x0c,0x2d,0xa3,
+  0xdd,0x6f,0x87,0x36,0xc5,0xa2,0xd2,0xcd,0x5a,0xb2,0xfe,0x0b,0xd2,0xce,0xc0,0x81,
+  0xd0,0x9e,0x90,0x35,0x8c,0xe8,0x65,0x10,0xba,0x7b,0xe3,0xfc,0xcc,0x6e,0x32,0x8b,
+  0xca,0x5f,0x27,0x1f,0xea,0x37,0x34,0x38,0x37,0x9b,0xea,0xdf,0x43,0x93,0x77,0x91,
+  0xcb,0x64,0x2e,0xc3,0x6d,0x70,0x9f,0xc1,0xff,0xcc,0xf9,0xc0,0xe1,0xaa,0x34,0xef,
+  0x03,0xdc,0x36,0xba,0xf2,0x27,0xdc,0x38,0x36,0x9f,0x38,0x6c,0x8a,0x7f,0x3d,0xc3,
+  0xd3,0x7a,0xd7,0x3e,0xc6,0x6f,0x3b,0xa6,0x4d,0xa4,0x99,0xb1,0x0a,0x4e,0xe3,0x36,
+  0x93,0x1c,0xa2,0xdd,0x9b,0x9c,0xbf,0x14,0x1b,0x4c,0xfe,0x1f,0x89,0x4b,0x57,0x46,
+  0x47,0x55,0x1e,0xf6,0x9a,0x37,0xc1,0x87,0x69,0x8f,0xa0,0xfd,0x58,0xa0,0x89,0x5a,
+  0x11,0xd0,0xa7,0x97,0x99,0xfb,0x5f,0x48,0xd2,0xe3,0x8c,0x8d,0xce,0x0c,0x5b,0xac,
+  0x10,0xc4,0xf3,0x22,0xc6,0xf9,0x6a,0xd8,0x7f,0x55,0x09,0x62,0xe3,0x60,0xb4,0x85,
+  0xaa,0xe4,0x9c,0x09,0xff,0x94,0x49,0x4f,0xa0,0xd2,0xa7,0x3f,0xbe,0x6e,0x9a,0xb4,
+  0x33,0x9e,0xf6,0x0c,0xbb,0x42,0x5b,0x42,0xb4,0x9e,0x5c,0x87,0x82,0xe5,0x07,0x3e,
+  0x7a,0x27,0xb9,0x94,0xe4,0x7f,0x03,0x09,0x7e,0x0f,0x2e,0x3d,0x73,0xbb,0x68,0x15,
+  0x06,0xd5,0x8a,0x11,0x9b,0xab,0x60,0x00,0x4f,0x5c,0x45,0xd4,0xa6,0x88,0x69,0x6a,
+  0x9f,0xe6,0xf2,0x5a,0x6f,0x10,0xef,0x49,0xd6,0x7f,0x4d,0xdd,0x49,0x3e,0xe4,0xd5,
+  0x4f,0x67,0xc5,0x6d,0xc2,0x65,0x88,0xf1,0xff,0x18,0xf5,0xef,0xb3,0x06,0xe5,0xf3,
+  0xf0,0x25,0x57,0x6d,0x83,0xa6,0xfa,0x2f,0x3a,0x65,0x08,0xde,0x49,0xab,0x60,0x88,
+  0x96,0x4b,0xb4,0x13,0x6c,0x82,0xff,0x19,0x5f,0xbc,0x58,0x2f,0xa8,0xa0,0x9f,0xc1,
+  0xdc,0xa8,0x35,0x2a,0x93,0xa4,0xff,0x27,0x83,0xf3,0x1f,0x16,0xb3,0x00,0x2f,0xbb,
+  0x5b,0x23,0xc5,0xc5,0x26,0x2f,0x7b,0x47,0x04,0x97,0x0b,0xbb,0x48,0xa9,0x46,0xa3,
+  0xa4,0x34,0xe1,0x5f,0x52,0xe1,0x97,0x3c,0xcd,0xc9,0xee,0x78,0x34,0xeb,0x67,0xb0,
+  0x2f,0x9e,0xf6,0x0c,0xbb,0x98,0x23,0x9a,0xb1,0x94,0x4c,0xe3,0xd0,0x28,0x4a,0x97,
+  0x92,0x3c,0x65,0x62,0xfd,0xeb,0xa5,0xc3,0xd0,0x74,0xc8,0x19,0x42,0xf9,0xb3,0x18,
+  0x78,0x61,0xaf,0xb1,0xdf,0x50,0x6d,0x0d,0xe1,0xfe,0x99,0xee,0xdb,0xa1,0xab,0xb5,
+  0x8e,0x5c,0x72,0x63,0x42,0x3f,0x0e,0xe7,0xee,0x51,0x8f,0x84,0x8a,0x43,0xbc,0x5e,
+  0x86,0x5e,0x09,0x77,0xc7,0xf9,0x9f,0xd9,0xfc,0x70,0xe6,0x90,0x38,0x0f,0xae,0xe4,
+  0xcd,0x0d,0x59,0x3f,0x16,0xe7,0x25,0xf6,0x4f,0x1d,0x6c,0xf1,0x0f,0x8b,0x95,0x54,
+  0xe0,0x30,0x60,0xd8,0x08,0x7b,0x4d,0x42,0x35,0xe4,0xad,0x24,0xb3,0x38,0x23,0xd0,
+  0x98,0xb6,0x7f,0xb2,0xad,0xf9,0x5b,0xc7,0x4c,0xf6,0x7b,0xa7,0x11,0xf4,0x29,0x36,
+  0x87,0x39,0xa4,0xb7,0x04,0xb7,0x96,0xb9,0x59,0x2e,0x64,0x77,0x42,0xf7,0x1d,0xb6,
+  0x1b,0x4c,0xf5,0x3b,0x21,0x48,0x1f,0x6c,0xd1,0x4b,0xbc,0x14,0xd5,0x28,0x4d,0xa6,
+  0x31,0x6b,0xbc,0x11,0x83,0xe7,0x39,0xd2,0x38,0x58,0xd4,0x20,0xa7,0xd4,0xbf,0xa7,
+  0x15,0x0a,0x4f,0xaa,0x45,0xdf,0xa0,0x41,0x69,0x88,0xe7,0xcb,0xc5,0xe6,0x3f,0x89,
+  0x6a,0x3a,0x23,0x98,0x5d,0xe8,0x68,0xe1,0x8e,0xa0,0x4d,0x37,0x64,0x99,0xed,0x2f,
+  0xa1,0x71,0xb5,0xe1,0xff,0xe1,0xb0,0x27,0x16,0x06,0xc2,0x41,0xc8,0x4b,0xe7,0x10,
+  0x4e,0x0d,0x5d,0xcf,0x11,0x91,0x25,0x51,0xff,0x95,0x77,0x93,0x0f,0x4e,0xc0,0x3c,
+  0x61,0xaa,0x99,0xf6,0x27,0xf7,0x6d,0xc4,0x3f,0x99,0x2c,0x47,0xa5,0x07,0xd1,0x10,
+  0x5b,0x82,0x36,0xa0,0xd9,0xff,0x83,0xa0,0xe5,0x1f,0xb5,0xbb,0x37,0xd5,0x3c,0x23,
+  0x7d,0x3e,0xe1,0xd6,0xf8,0x1c,0xaa,0xbc,0xb3,0xce,0x8b,0x9f,0xe3,0x4f,0xaf,0x70,
+  0x6a,0xa0,0x33,0x89,0xf5,0x2c,0x9f,0x72,0x1e,0x3e,0x91,0x6e,0xd5,0xac,0xbf,0x14,
+  0x6f,0x5d,0xfb,0x56,0x9c,0x1f,0x09,0x2e,0x6b,0x3b,0xbc,0xff,0x78,0x8f,0x78,0x6b,
+  0x10,0xf1,0x52,0xb5,0xf5,0x58,0x4d,0xb2,0xfe,0x3d,0x0f,0x42,0xd6,0x00,0x94,0x80,
+  0x75,0x75,0x4e,0x3e,0xeb,0x32,0xf2,0x9f,0x89,0x81,0x88,0xa6,0x16,0x37,0x93,0x7c,
+  0xd6,0xa3,0x16,0xdd,0x54,0xb7,0xba,0x35,0xc9,0xff,0x5c,0x27,0x3d,0x0b,0x5b,0x61,
+  0x86,0x76,0x4b,0x2e,0xb9,0x1d,0x9e,0xa7,0xdc,0xdb,0x93,0xce,0x0b,0xe1,0xeb,0xf9,
+  0x15,0x4e,0x05,0xd0,0xe9,0xa1,0x93,0xd5,0xec,0x24,0xfe,0xc9,0xe5,0x69,0xe4,0x25,
+  0xb7,0xc7,0x68,0x27,0x35,0x7b,0x8c,0xf6,0x79,0xb7,0xdd,0xc1,0xf1,0x4f,0x21,0xec,
+  0xcd,0x2d,0x8a,0xd0,0x8d,0x24,0x3d,0x31,0x3f,0x94,0xbb,0x1a,0x3e,0xb4,0xce,0xf1,
+  0xdd,0x1d,0xcc,0x58,0x0e,0x0f,0x69,0x46,0x59,0x9f,0xe1,0xef,0xaa,0x9b,0x75,0x5c,
+  0x9c,0xee,0x3b,0x0b,0xd7,0xd5,0x39,0x82,0xe6,0xfe,0x17,0xd0,0xd9,0xcc,0x83,0x5c,
+  0xc5,0x8a,0x11,0x1d,0x4b,0xb8,0x7d,0xca,0xb4,0x59,0xd9,0x6d,0x67,0x60,0x5c,0x2c,
+  0xe3,0x15,0x64,0xe6,0xfa,0xaf,0x0e,0x88,0xe8,0x31,0xb6,0x81,0x44,0x99,0x21,0x7e,
+  0x88,0x79,0x9c,0xff,0x39,0x1f,0x22,0xab,0xdd,0x24,0xa5,0xfe,0x8b,0x4a,0xe5,0xb0,
+  0x8e,0xcc,0xe2,0xf8,0x67,0x3e,0xe3,0x65,0x5f,0x8b,0x42,0x62,0x17,0xf0,0xfc,0x1f,
+  0x3a,0x44,0xca,0xb5,0x75,0xb0,0xb5,0x43,0x8e,0x7a,0x92,0xfc,0x3f,0x34,0x6d,0xb1,
+  0x51,0x76,0xaa,0xba,0x6e,0xf8,0x17,0xbf,0x88,0x82,0xba,0x8d,0x9f,0x97,0x3d,0xdc,
+  0x71,0x0a,0x64,0x12,0x6c,0x98,0x8c,0x08,0xf0,0x06,0x53,0xfe,0x8f,0x2a,0x54,0xa8,
+  0xcd,0xe9,0xc5,0x0c,0xb5,0xd5,0xda,0x8c,0xe7,0x5c,0x46,0x20,0x8c,0xd7,0x2f,0x4c,
+  0xd7,0xa9,0x87,0x7c,0x0b,0x9e,0x90,0x66,0x82,0xfc,0x08,0x09,0x25,0xfc,0x3f,0x8e,
+  0xbc,0xeb,0x50,0xbf,0x14,0x6f,0xb1,0x3e,0x9a,0xf3,0xb4,0x70,0x14,0x81,0xd0,0xa4,
+  0x18,0xec,0xa9,0x8a,0xae,0xfb,0x89,0x5c,0x49,0x4e,0xb2,0xdb,0x7c,0xb6,0x13,0x29,
+  0xf5,0x5f,0xcd,0x64,0x0c,0xa6,0xf1,0xa2,0xda,0x15,0xc2,0x3b,0x6c,0x42,0xad,0xc3,
+  0x9e,0xb7,0x67,0xf5,0x88,0x3d,0xa8,0xfc,0xe7,0x72,0xfb,0xcb,0x93,0x90,0x3f,0x3e,
+  0xe9,0x65,0xb8,0x1c,0x5c,0x30,0x64,0xa8,0xad,0x25,0xf1,0xb4,0x67,0xbc,0xff,0xfc,
+  0x53,0x59,0x2d,0x05,0x65,0xc2,0xe1,0xe0,0xdc,0xa1,0xb5,0x27,0xc4,0x41,0x13,0xfe,
+  0xd9,0x54,0xb7,0xf3,0x77,0xc5,0x5d,0x75,0x0d,0xd9,0xdf,0x95,0xfe,0x18,0xe7,0xff,
+  0x81,0x6e,0xa9,0x43,0xa7,0x75,0xfe,0xc9,0xe1,0x3f,0xce,0xce,0x6f,0xa6,0xd9,0xf0,
+  0x91,0xa9,0xfe,0x6b,0x13,0xec,0x54,0x67,0xae,0xbe,0xe5,0x21,0x44,0x47,0xaf,0x4c,
+  0xf0,0xff,0xbc,0x4c,0x67,0xf6,0x5b,0x7e,0x44,0x36,0x29,0xfb,0x60,0xfa,0x1d,0x75,
+  0x5e,0x4f,0x73,0xe2,0xfe,0x5a,0xee,0x2a,0x25,0xac,0x3b,0x55,0x34,0xdb,0x39,0xcd,
+  0x4b,0x9c,0xcf,0xbf,0x9b,0x21,0x1e,0x70,0x5b,0x7e,0xcb,0x5e,0x04,0x7b,0x37,0xdd,
+  0xe6,0x3f,0x61,0xf6,0x0f,0x68,0xb8,0x5b,0x3a,0x6d,0xa3,0x68,0x4f,0x7d,0xa9,0x71,
+  0xf9,0x39,0x89,0xeb,0x97,0xf2,0xfa,0xbb,0x03,0xe2,0xb3,0xb0,0xdb,0x5b,0xe6,0xb5,
+  0xae,0xdd,0x15,0x31,0xf1,0x2d,0x8c,0x68,0x63,0xc2,0x34,0xc4,0x3f,0x35,0x51,0xf8,
+  0x4f,0x34,0xbe,0x3e,0x88,0xa8,0xfb,0x6c,0xcd,0xc2,0xfd,0xca,0x3b,0x50,0x29,0xa0,
+  0x04,0x3b,0x65,0xf2,0xff,0x9c,0x87,0x81,0xc0,0x7c,0xe6,0x1c,0xcd,0xe9,0x46,0x18,
+  0x90,0x13,0xe3,0x7f,0xbe,0xa2,0xcd,0xd5,0xac,0x4f,0xe6,0x8c,0x28,0x56,0x34,0x94,
+  0xac,0x3a,0xee,0xcf,0xa4,0xff,0x67,0x39,0x0b,0x44,0x9d,0xae,0x3a,0x84,0x3d,0xea,
+  0x5e,0xe8,0x30,0xf4,0x97,0x14,0xce,0x78,0x41,0x77,0x6c,0x26,0xa7,0xa1,0x4b,0xef,
+  0x68,0xa8,0x5b,0x8b,0xa7,0x21,0x99,0xff,0xbc,0x1c,0x02,0x6a,0x56,0x07,0xa2,0x9d,
+  0x6d,0xcd,0x7b,0xa1,0x68,0x42,0xdf,0xcd,0xb8,0x33,0xc0,0x36,0x9e,0x49,0x7b,0xbe,
+  0xf1,0x85,0x28,0x5d,0x7b,0x8f,0x89,0xff,0x07,0xf5,0x11,0xa3,0x4e,0x12,0x70,0x11,
+  0x2b,0xde,0x3f,0xc6,0x07,0x68,0x10,0xf5,0x53,0x42,0x74,0x81,0x21,0x34,0xa2,0xe0,
+  0x21,0x09,0xf9,0x03,0x79,0x9c,0xf6,0xaa,0x32,0x60,0x0d,0xe7,0xac,0xe5,0x6a,0xe5,
+  0xf5,0xd8,0x7e,0x50,0x76,0x79,0xad,0x7e,0x31,0x9a,0x61,0xc4,0x7f,0x37,0x08,0x6a,
+  0x4a,0xfe,0xcf,0x4a,0xbe,0x08,0x9c,0x46,0xe0,0x4b,0x28,0x8b,0xf1,0x3f,0x9f,0x57,
+  0x5f,0x39,0x68,0xeb,0x45,0x8b,0xfe,0x3c,0xdf,0x3f,0xfa,0xa4,0x24,0xfe,0x01,0x20,
+  0xcd,0xb0,0x85,0xd3,0xcd,0x28,0xff,0xce,0x00,0xcc,0x7f,0x12,0xa0,0x75,0xa8,0xa1,
+  0x04,0xfe,0x77,0x06,0xe6,0xbf,0x66,0xb4,0xe9,0x39,0xb9,0xe6,0xbf,0x37,0xf8,0x3f,
+  0xb9,0x3f,0xe3,0x39,0x44,0x40,0xfe,0xdd,0x81,0xe9,0xef,0xdf,0x9f,0x18,0x1b,0xfc,
+  0x9f,0xdc,0xff,0x7f,0xf7,0xef,0x3f,0xd8,0xfa,0x2b,0xbc,0x97,0xdf,0x00,0xfc,0x08,
+  0xa6,0xea,0xff,0xce,0x40,0xfa,0x7f,0x7c,0xff,0xff,0x3f,0xaf,0xbf,0xa4,0xb0,0xbf,
+  0x62,0xcd,0x05,0x53,0x7f,0x9f,0xff,0xbd,0xbf,0x8a,0x8a,0xbf,0x66,0x96,0xcd,0xf6,
+  0xff,0xf0,0xf6,0xff,0x2f,0xfc,0x55,0x5d,0xbd,0x7a,0x55,0xff,0x5f,0x0c,0xfe,0xbf,
+  0x3c,0xff,0x3f,0xd8,0x79,0xfc,0xbf,0xf2,0xf0,0xff,0xca,0xc3,0xff,0x83,0xf5,0xff,
+  0xbf,0xf2,0xf0,0x7f,0xf5,0xf7,0x1f,0x4d,0xfe,0xfc,0xc7,0x9a,0xcf,0xf9,0x21,0x8f,
+  0x2a,0xb3,0xf5,0xac,0x51,0xb9,0x0c,0xfe,0x02,0xa5,0xaa,0x4d,0x17,0xcb,0xc9,0x7a,
+  0xb5,0xca,0x67,0x5b,0x29,0x56,0xc0,0x81,0xfe,0xd9,0x43,0xd6,0xb1,0x49,0xe6,0xfc,
+  0xa8,0xa8,0xda,0xa2,0xd9,0xcf,0xd3,0xcd,0xd9,0x85,0x6c,0x7d,0x6f,0x91,0x2a,0x8b,
+  0x7d,0xbf,0x91,0xd6,0x07,0x4b,0x7c,0x8b,0x7a,0xb2,0x7f,0xa7,0xb6,0xa9,0x65,0x11,
+  0xca,0xf9,0x04,0x92,0xfe,0xb1,0x6d,0x5a,0xe3,0xe4,0x90,0x6e,0x99,0x4d,0x9e,0x55,
+  0xb7,0x56,0xab,0xea,0x0d,0x1b,0xd3,0x1d,0x5a,0x53,0x7a,0x21,0x27,0x1e,0xc9,0x64,
+  0x4d,0x85,0xf6,0x6b,0xfa,0xc3,0x4e,0x19,0x22,0x9c,0x56,0x8b,0xf3,0x03,0xb3,0x36,
+  0x20,0x5a,0x4e,0xc0,0xce,0x03,0xaf,0x25,0x20,0xf7,0x90,0x6d,0xa4,0x89,0xf1,0x40,
+  0x61,0x76,0x32,0x3f,0x4a,0xc8,0x7d,0x96,0x1d,0xd4,0xed,0x7a,0x96,0xd1,0x86,0x03,
+  0x1e,0x66,0xb6,0xb5,0x4d,0xf9,0x81,0x43,0xe4,0x9f,0x34,0xb9,0x47,0x74,0xc2,0x9d,
+  0x21,0x35,0x6a,0x0d,0x93,0x41,0x53,0x7c,0xf0,0x59,0xed,0x72,0xf0,0x77,0xba,0xed,
+  0x84,0xf0,0x05,0xa7,0xc5,0x4e,0xb7,0xe9,0x35,0x97,0x94,0x8b,0xf0,0x73,0x2f,0x07,
+  0xd2,0xf4,0x15,0xa1,0x6a,0xd4,0x36,0x5a,0xd0,0x65,0xaa,0x4f,0xef,0x14,0x0e,0x68,
+  0xee,0x88,0x75,0xbb,0xd8,0x09,0xef,0xd1,0xca,0xe6,0xcc,0xa0,0xa8,0xa6,0x1d,0x62,
+  0x2f,0x6b,0x06,0x43,0xc5,0x21,0xcd,0x48,0x9d,0x32,0xe5,0x47,0x41,0xba,0xda,0x42,
+  0x6f,0x39,0x96,0xc9,0x69,0xf7,0xd6,0xf4,0x96,0x34,0xa4,0x03,0xc9,0xda,0xb0,0x9e,
+  0xa7,0x6d,0x4c,0x23,0x15,0xf8,0x22,0x2f,0x9c,0xb4,0x86,0x53,0xf8,0x91,0x6a,0xa1,
+  0x31,0xa2,0x0e,0xd2,0x6c,0x14,0x7e,0x8f,0x6b,0x4e,0x6f,0x0e,0x90,0x03,0x81,0x26,
+  0x5e,0xbf,0x53,0x6e,0x19,0x10,0xb6,0xf2,0xfc,0x0d,0x1e,0x1f,0x9c,0xf8,0xe3,0xf9,
+  0xe1,0xeb,0x79,0x52,0xf4,0xca,0xeb,0xce,0x19,0xf5,0x71,0x37,0xfc,0xc0,0xf3,0xb6,
+  0xb4,0x26,0x28,0x0c,0x8b,0x3f,0xb1,0x4c,0x2b,0xfc,0x97,0xc6,0x5b,0x7c,0x94,0x27,
+  0x0e,0x4d,0xfc,0xd5,0xf1,0x36,0x1c,0xe0,0xea,0xb5,0x2a,0xe2,0x5a,0xf8,0x3d,0xad,
+  0xa0,0x37,0x09,0x72,0xbd,0xd4,0x24,0xe4,0xd6,0xaf,0x9f,0x23,0x8e,0x90,0xf7,0x83,
+  0xae,0x08,0xef,0x0f,0x9b,0x8c,0x0f,0xde,0xb4,0xcd,0xf3,0x99,0xc2,0xdd,0x86,0x93,
+  0x8e,0x6b,0x7f,0xaf,0x55,0xe9,0x37,0xf7,0xe2,0x7e,0xf8,0x79,0x6d,0x15,0xe3,0x1d,
+  0xf4,0xe0,0x8f,0x02,0x27,0x56,0x15,0x07,0x13,0xf1,0x41,0x87,0xb4,0x0d,0x0e,0x08,
+  0xbc,0xc8,0xa2,0xa6,0x13,0xde,0x71,0x55,0x9e,0xc0,0xfd,0x13,0x52,0x7e,0xcf,0xdc,
+  0x5a,0x5b,0x58,0x74,0x7a,0x0e,0x91,0x69,0x3c,0x90,0x9a,0x8c,0x0f,0x46,0x94,0xcd,
+  0xb0,0x06,0xf2,0xa3,0x4d,0x0d,0xf6,0x5c,0xfa,0x47,0xa1,0xf8,0xd8,0x22,0xdd,0x33,
+  0x95,0x3e,0xa7,0x19,0xfc,0xba,0x53,0xb5,0x35,0xb1,0x8c,0x71,0x73,0x7c,0x30,0x0b,
+  0xb6,0xb2,0xe7,0xa3,0x8b,0xf2,0xbc,0xbf,0x74,0xad,0x09,0x15,0x77,0xc8,0x75,0x64,
+  0x23,0xac,0x09,0xe5,0xfb,0xe4,0xfa,0xec,0x69,0xb0,0x9a,0xcd,0xf2,0x05,0x56,0x92,
+  0x13,0xa6,0xf8,0xe0,0x6f,0xa0,0x29,0xc3,0x30,0x4b,0x57,0xb1,0xc7,0x89,0x33,0x2a,
+  0x0b,0x64,0x16,0x6c,0x85,0x2e,0x26,0x3b,0x8a,0x9c,0xb0,0x11,0x4a,0x78,0x7f,0x58,
+  0x53,0x7c,0x70,0xca,0xde,0xbe,0x23,0x42,0x07,0x93,0x43,0x39,0x7b,0xe9,0x41,0xa8,
+  0x64,0x47,0x87,0x6f,0xd9,0xcb,0x0e,0xc2,0x43,0xcc,0x76,0xe6,0x1b,0x0e,0xfa,0x3a,
+  0x94,0x74,0x39,0x43,0xe2,0x85,0xe4,0xfd,0x61,0xc2,0x4d,0x04,0x3e,0x83,0x1f,0x7b,
+  0x12,0xa7,0xa9,0x19,0x8e,0xe7,0xeb,0xc2,0xb0,0x1a,0xe3,0x07,0x30,0xc5,0x07,0x87,
+  0x0c,0x36,0xa4,0x9b,0x83,0xe2,0x72,0x7a,0x00,0xca,0x7c,0x4b,0x94,0x58,0xa2,0xb8,
+  0x66,0x6d,0x6f,0x8a,0x11,0x25,0x19,0xf9,0xe1,0x13,0xf3,0x99,0xb4,0x9c,0x34,0x56,
+  0x93,0x6a,0xf9,0x3a,0xbb,0xd1,0x1f,0x4d,0x6f,0xe1,0x81,0xc5,0xb7,0xa4,0x2c,0xcd,
+  0x92,0x6b,0x9f,0x4e,0x5b,0x88,0xbd,0xc1,0xc1,0xf3,0x3f,0x27,0xfe,0xf2,0xa4,0x42,
+  0xd2,0x96,0x61,0xaf,0x95,0x83,0xa4,0x5f,0x68,0x01,0x7b,0x9d,0x11,0xcf,0x6a,0x61,
+  0x33,0x34,0xcb,0x06,0xcb,0xf4,0x34,0x7e,0x85,0x9a,0xe3,0x83,0x20,0xa5,0x91,0x38,
+  0x1b,0x52,0x9a,0x75,0x0b,0x7e,0xef,0x0c,0xee,0x26,0xda,0x20,0x65,0x55,0x2f,0x74,
+  0x91,0x34,0xa1,0x45,0x63,0x0d,0x29,0xf9,0x99,0x2b,0x33,0xb8,0x7d,0xda,0xd1,0x78,
+  0x23,0x4f,0x8b,0x8a,0xa7,0x25,0x53,0x12,0xc1,0xf3,0x98,0x15,0x23,0x4a,0x32,0x2a,
+  0x76,0x3f,0x35,0xf9,0xc7,0x3e,0x27,0x57,0xb5,0x12,0x5e,0x04,0xf7,0x08,0x79,0xab,
+  0xfa,0x69,0x4d,0x38,0x2e,0xbf,0x04,0xe3,0x5a,0x95,0x76,0xb4,0x41,0x7c,0x2d,0xed,
+  0x32,0x2f,0x9d,0x0b,0x8a,0xbf,0x35,0xe5,0x47,0x7d,0x11,0x3a,0xdc,0x3f,0x77,0x99,
+  0xed,0x98,0x38,0x24,0x1d,0xe6,0xf5,0x0b,0x9b,0x26,0xed,0x84,0xc3,0x24,0xd6,0x4f,
+  0x4d,0x1b,0xf7,0x14,0x70,0x62,0xa5,0x4f,0x4d,0xf9,0x51,0xa7,0xfd,0x01,0x56,0xa6,
+  0x88,0x8c,0x0c,0x33,0x7c,0x1e,0x26,0x83,0x78,0xbf,0xb7,0xeb,0xde,0x12,0x66,0xf0,
+  0x23,0xf5,0x48,0x65,0x54,0x4e,0x89,0x0f,0xa6,0xf5,0x77,0x34,0xc6,0xaa,0xff,0x3a,
+  0xd5,0x0d,0x38,0xf8,0xd5,0x26,0xde,0x1f,0x36,0xc6,0x07,0xde,0xdf,0xb8,0x1b,0x54,
+  0xcf,0x22,0x73,0x7c,0xb0,0x7d,0xca,0x2a,0x83,0x16,0x7b,0x51,0xac,0x2d,0xc8,0x8c,
+  0x5e,0x5c,0xcf,0x5a,0x2b,0xcf,0xcf,0x17,0x63,0x8e,0xca,0x19,0xb7,0x1b,0xfc,0x00,
+  0x13,0xf3,0x3b,0x50,0x5e,0xf5,0xea,0x46,0xb6,0xdb,0xeb,0x9e,0xb7,0x78,0x1a,0xd8,
+  0x66,0x7f,0x27,0x9e,0x88,0x9f,0xf1,0x7a,0x40,0x1e,0xff,0xed,0xd0,0x6c,0xe6,0xf8,
+  0xe0,0xb0,0x50,0x98,0x68,0x8b,0xa6,0x8c,0xd3,0x58,0x7e,0x54,0x2e,0x77,0x9c,0xae,
+  0x37,0x12,0xa5,0x72,0x8c,0x44,0x32,0x53,0x7c,0x50,0x51,0x8d,0x26,0x20,0x95,0xac,
+  0xc9,0x07,0x83,0xb8,0xda,0x59,0xcd,0xa2,0x8f,0x8e,0x15,0x96,0x29,0xab,0x9b,0x45,
+  0xa3,0x3e,0x8e,0xa6,0xe6,0x47,0x09,0x0e,0x58,0xa7,0x14,0xb0,0xcc,0x11,0x82,0x03,
+  0x56,0xc4,0xa8,0x9a,0x53,0xae,0xee,0x67,0xcb,0x58,0xc6,0xb0,0xf8,0x63,0xf0,0x93,
+  0x59,0x41,0x39,0x64,0x8a,0x0f,0x3a,0x24,0x2b,0x69,0xd2,0xba,0x4e,0x65,0xcc,0x21,
+  0x8b,0x33,0x1e,0xd7,0xd5,0xa8,0xec,0x4a,0x5f,0x2c,0xec,0x18,0x2c,0xd4,0x2d,0xf3,
+  0x88,0xcc,0x1e,0x87,0x15,0x85,0x3c,0x5f,0x2e,0x19,0x1f,0x84,0x5c,0x58,0x05,0xcf,
+  0x9f,0xce,0xc8,0xf3,0x57,0x80,0x48,0xff,0xeb,0xb2,0x8c,0x87,0xc8,0x54,0xd8,0xd5,
+  0x9c,0xaf,0x67,0xac,0xf4,0xff,0x27,0x78,0xc2,0xf5,0x00,0x8f,0xef,0xd7,0x25,0xe3,
+  0x83,0x01,0xce,0x56,0x34,0xf3,0x94,0x75,0xe5,0xdc,0xef,0xce,0xf9,0x63,0xa3,0xc0,
+  0xc3,0x82,0xdf,0x81,0xcf,0xd8,0x4b,0xd1,0x75,0x2b,0x85,0x4a,0xf2,0x47,0xff,0x4f,
+  0x43,0xb6,0x95,0x5f,0x37,0xc5,0x07,0xad,0xcf,0xc0,0x98,0x36,0x47,0xcf,0x0c,0x7e,
+  0xe3,0x30,0xbb,0x08,0x95,0x6f,0x67,0xbd,0xcc,0xdb,0x9e,0x72,0x47,0xbd,0xca,0x19,
+  0x93,0x28,0x27,0x0a,0xf8,0x86,0x89,0x1f,0x72,0xd5,0xd5,0xc0,0x51,0xbd,0x34,0x6a,
+  0x7b,0xd2,0x56,0x19,0xba,0xcc,0x4a,0x4f,0x2d,0xde,0x57,0xb3,0x1f,0x3e,0xf6,0x7f,
+  0x2d,0x7a,0xf7,0x78,0x41,0x99,0x72,0xc8,0x3f,0x57,0xb5,0xee,0x16,0x93,0xf2,0xa1,
+  0x6b,0xf2,0x2f,0xa3,0xab,0xe8,0x96,0x7e,0xf9,0xd1,0xd5,0x53,0xd5,0x33,0x70,0x4b,
+  0x5d,0xe6,0xff,0x20,0xb9,0xca,0x9a,0x90,0xa3,0x8f,0x8e,0x91,0x4d,0x64,0x4d,0x30,
+  0x5f,0x72,0xac,0x14,0x3f,0x32,0xc5,0x07,0x9f,0xae,0x5b,0xc3,0xf2,0x35,0xb9,0x9a,
+  0x4c,0x6d,0x7f,0x09,0x0a,0x7a,0xaf,0x6f,0xf0,0xb7,0xe3,0x6b,0xde,0xa2,0x5b,0xce,
+  0x91,0x5c,0xf8,0x67,0xf2,0x75,0x96,0xf1,0x30,0x79,0x5d,0x9b,0x98,0xef,0xcb,0x7d,
+  0x03,0x02,0x3a,0x70,0xa1,0x3d,0x0b,0x3a,0x40,0x3d,0x96,0x31,0xc7,0x4e,0xc8,0xe3,
+  0x50,0x3f,0x4a,0x15,0x4f,0x33,0xfc,0x8a,0xd9,0xb5,0x0c,0x17,0x09,0x26,0xbf,0x57,
+  0xee,0xb3,0xe4,0x80,0xbf,0x9b,0xd9,0xda,0x49,0x25,0xcf,0xf6,0x39,0x97,0x79,0x9e,
+  0x3c,0xc7,0x4e,0x80,0x7b,0x28,0xeb,0x29,0xd1,0x81,0x1a,0xa7,0x8c,0x65,0x86,0xc9,
+  0x11,0xe6,0x4b,0x3c,0xcf,0x36,0xf5,0xe2,0x22,0x23,0x09,0x7c,0x45,0xf3,0x29,0xa8,
+  0x0c,0xda,0xba,0xc5,0x0f,0xe1,0x23,0xcf,0x31,0x7d,0x09,0x8a,0x05,0x81,0x67,0x94,
+  0x65,0x85,0x27,0x99,0xe3,0x83,0xbf,0xd4,0x0e,0x43,0x69,0x08,0x4f,0xd3,0x4f,0xe0,
+  0xa0,0x32,0x97,0x97,0x45,0xa7,0x87,0x0e,0x0a,0x55,0x3a,0x5e,0x59,0xc1,0xae,0x42,
+  0x01,0x4f,0x9d,0x52,0x4d,0xf1,0xc1,0x12,0x68,0x6d,0xef,0xe8,0x47,0x6d,0xe5,0x54,
+  0x9e,0xaf,0xb3,0x87,0xe4,0xb0,0xa5,0x08,0x5e,0x60,0x0f,0xea,0x87,0xa6,0xa6,0x3f,
+  0xcb,0x03,0x3d,0x51,0xd4,0xbf,0x66,0x7e,0x00,0x9e,0xc6,0x69,0x6f,0x5a,0xd4,0xee,
+  0x59,0xc1,0xab,0xb7,0x6a,0x2d,0x61,0x32,0x1d,0xda,0xfa,0x7e,0x18,0x6b,0x14,0xbb,
+  0x17,0x8a,0x4e,0xd3,0xb0,0x39,0x3e,0x28,0x59,0xed,0x22,0x84,0x98,0x9c,0xed,0xb1,
+  0x42,0x08,0x54,0x41,0x76,0x3d,0x05,0x74,0xab,0xea,0xec,0xc7,0x63,0xd5,0x0c,0x3b,
+  0x7c,0x54,0xa3,0x6e,0xd2,0xd7,0x9c,0xd8,0xa0,0x99,0xf7,0xc2,0x6b,0xbc,0x2d,0xe3,
+  0xc6,0xa6,0x9f,0x28,0x11,0xe8,0xd6,0xb2,0xce,0x7d,0xa3,0x10,0x0e,0x39,0xe6,0x0d,
+  0x1a,0x85,0x72,0x57,0x79,0x46,0x59,0x58,0xf4,0x25,0xe3,0x83,0x37,0x8d,0xc4,0xd8,
+  0x2f,0xbd,0x39,0x97,0x88,0xc1,0x86,0x3d,0x6a,0x24,0x8a,0x2f,0x88,0xac,0xdf,0x20,
+  0x9e,0xa7,0x5f,0xfa,0x5e,0xd2,0x6c,0xe7,0x73,0x4c,0xfc,0x48,0x69,0x5f,0xc0,0x38,
+  0x73,0x83,0x6d,0x4c,0x5c,0xa6,0x1d,0xe5,0xcb,0x3e,0x26,0x8e,0x86,0x2e,0x3b,0xe6,
+  0x46,0x33,0x07,0xc5,0x2b,0x70,0xd2,0x35,0x37,0xcf,0xaa,0xdf,0xe8,0x4a,0xf0,0x99,
+  0xe8,0x01,0x5e,0xe4,0x65,0x77,0xf1,0x6a,0xb8,0x60,0x9b,0x6e,0x47,0xb4,0x43,0xde,
+  0x87,0xdd,0x7c,0xb0,0x8f,0x8c,0xb0,0x40,0x83,0x5d,0xa1,0xab,0xd3,0x93,0xf9,0x51,
+  0x11,0xb4,0x09,0xb6,0x0b,0x0e,0x09,0x6f,0xa1,0x41,0x53,0xb5,0x1a,0x69,0xe5,0x6d,
+  0x2f,0x76,0x40,0x61,0x1f,0x0a,0xde,0x11,0x15,0x37,0x82,0xd5,0x22,0xf9,0x93,0xf1,
+  0xc1,0xa8,0xd4,0xa9,0xe0,0xfd,0x19,0xa2,0xa3,0x57,0x2d,0x32,0xd8,0x7b,0x71,0xf5,
+  0x3e,0x81,0xbd,0x0c,0x70,0x90,0x3e,0x62,0x69,0xd1,0x79,0xeb,0x10,0x53,0x7e,0x94,
+  0x90,0x76,0x46,0x39,0x1b,0xea,0xce,0x46,0x34,0xf2,0x3d,0xa3,0x1a,0x2b,0xcb,0xc8,
+  0x27,0xec,0x2d,0xd3,0xef,0x0a,0x8b,0x07,0xf2,0xde,0xd2,0x5f,0x6e,0xc8,0x6a,0x6f,
+  0x4a,0xe6,0x47,0x85,0x26,0xef,0xd4,0x2e,0x93,0xca,0xe5,0x4b,0x2e,0xe5,0x8c,0x25,
+  0xcb,0xbe,0x2e,0x73,0xfe,0xa8,0x28,0x19,0xeb,0xf8,0x5c,0x58,0xc0,0x32,0xf5,0x9a,
+  0x24,0xfe,0x39,0xae,0x74,0x6a,0xe3,0x3e,0xb7,0x62,0xe5,0x69,0x57,0x3c,0x51,0x1c,
+  0x07,0x1f,0xc2,0x21,0x56,0xd9,0x87,0x83,0x4f,0xe0,0xed,0x3b,0x2b,0x97,0xda,0x76,
+  0x9a,0xf3,0xa3,0xd2,0x66,0xf0,0x68,0x54,0x07,0x0d,0x7b,0xa2,0xa8,0xe8,0x63,0x69,
+  0x5d,0xac,0x09,0x1e,0x3c,0x41,0x43,0x64,0xc4,0xde,0xb2,0xb8,0xc4,0x27,0x6e,0x10,
+  0xcd,0xf1,0xc1,0x74,0x36,0x5b,0x57,0x59,0xc6,0x1c,0xbf,0x0e,0x5b,0x25,0xbb,0x9e,
+  0xe1,0xca,0x7e,0x9d,0x67,0xf0,0x0e,0xd6,0x29,0xe4,0x48,0xce,0x46,0xe6,0x0c,0xb6,
+  0x3d,0x6f,0x4f,0xe2,0x9f,0x51,0xe5,0x3a,0xfa,0xbb,0x70,0x7e,0xe8,0xce,0x95,0xe4,
+  0x61,0xed,0x39,0x96,0x3f,0x74,0xcb,0x4a,0x94,0xf6,0xab,0x9a,0x8b,0xa3,0xf4,0xd1,
+  0xec,0x2b,0x91,0xb4,0x8e,0xe2,0x90,0x7c,0x67,0x7a,0x32,0x3f,0xaa,0x3e,0xcf,0x0a,
+  0xa3,0x3d,0x2e,0x5f,0xa6,0x0b,0x41,0xc8,0xfb,0x92,0x7b,0x38,0xd3,0xe8,0x0f,0x22,
+  0x94,0xe8,0xce,0x1b,0x26,0x0d,0xb0,0xc1,0xc9,0x15,0xf7,0xa0,0x46,0x36,0xf5,0x47,
+  0x9b,0xb2,0x0f,0x3e,0xc7,0xd5,0x28,0x41,0x90,0xa3,0xbd,0x87,0x40,0xc8,0xc9,0x69,
+  0x21,0x0d,0xf9,0x73,0xb6,0xe0,0x64,0xe0,0xf2,0xad,0x3f,0x47,0xf9,0xfc,0x8d,0x60,
+  0x62,0x7d,0x1c,0x52,0x27,0x9c,0x65,0xf3,0x98,0xb5,0x3c,0x27,0x0b,0xde,0x31,0xfa,
+  0xa3,0xe5,0x8c,0x28,0x47,0x25,0xa3,0x3f,0xc8,0x90,0x74,0x04,0x4a,0xc1,0x19,0x15,
+  0x3d,0x89,0xf5,0x1f,0xa1,0x9b,0xe0,0x73,0x1e,0x3d,0x6f,0x10,0xef,0x83,0x35,0x7a,
+  0x2c,0xcd,0x80,0xae,0xf1,0x17,0xeb,0xb2,0x2f,0x9b,0x27,0x36,0x6f,0x61,0x54,0x13,
+  0x93,0xfc,0x90,0x3c,0x3f,0x6a,0x17,0x9b,0xe9,0xcb,0x58,0x69,0x9f,0x0b,0x3b,0x42,
+  0x06,0x1f,0xf8,0x11,0x58,0xc3,0x2b,0x04,0x57,0xce,0xb8,0x02,0xdd,0x7e,0xd5,0x77,
+  0x67,0xb9,0x29,0xff,0x61,0xb1,0xb4,0x16,0x76,0x44,0xd4,0x37,0x33,0x14,0xcf,0x1d,
+  0x88,0x1e,0x3b,0x38,0xba,0x3e,0x82,0x12,0xde,0xa9,0xcb,0xd3,0xc9,0xe1,0xc5,0x19,
+  0x5e,0x7b,0x43,0xc6,0x54,0x8b,0x89,0x1f,0x52,0xea,0x82,0x2b,0xda,0x6d,0xcd,0x99,
+  0x5d,0x8f,0x97,0x73,0x5a,0x6c,0x66,0x45,0xb4,0xc3,0x8e,0xf0,0x08,0x69,0x54,0xbc,
+  0x48,0xee,0x66,0xa5,0xa1,0xcc,0x8f,0xc4,0x79,0x26,0xfe,0xa5,0x90,0x30,0xac,0x54,
+  0x42,0x09,0xcb,0x39,0x05,0x4b,0x8d,0x46,0xb1,0x08,0x0c,0x0c,0x7e,0x6c,0xd6,0x14,
+  0x2d,0x1c,0x93,0x2b,0xd3,0xb3,0x58,0xd3,0x46,0x73,0x7e,0x14,0x8c,0x4f,0xae,0xf4,
+  0xf1,0xb6,0x59,0xea,0x43,0xc4,0xcd,0xab,0xa5,0x86,0xb4,0x03,0x01,0xa3,0x90,0xfc,
+  0x8c,0x72,0xa0,0xc3,0x5d,0x6f,0x9d,0x4a,0x88,0x09,0xff,0xfc,0x17,0x3c,0x4d,0x25,
+  0x1e,0xcb,0x66,0xf2,0x01,0xdb,0x0d,0x65,0x9c,0xef,0xe8,0x0c,0x3c,0xe6,0x77,0x6a,
+  0x8e,0x20,0x79,0xc3,0xd7,0xc2,0xec,0xf5,0x46,0x45,0xc6,0xc4,0x79,0x2f,0x4f,0xfb,
+  0x3a,0x2a,0xe5,0xac,0xda,0xbc,0xcd,0x64,0x48,0xe3,0xfd,0x4c,0x8d,0x34,0x9e,0xb6,
+  0xfc,0x07,0xef,0x47,0xd8,0xb3,0x0d,0x78,0xc6,0x14,0x35,0xf3,0x03,0xa8,0xb9,0x12,
+  0x6c,0x27,0xce,0x6a,0x8b,0x72,0x0f,0x6f,0x93,0x51,0xe8,0x35,0xe2,0x83,0x8d,0xf0,
+  0x20,0x87,0x3d,0x1f,0x18,0x1d,0x43,0xf2,0xcc,0xfc,0x48,0x2b,0x6f,0x8a,0xe5,0x47,
+  0x59,0x63,0xf9,0x60,0x46,0x58,0xd0,0xa8,0x8f,0x13,0xac,0x3c,0x42,0xca,0x89,0x22,
+  0x9d,0x4c,0xfe,0xed,0xa4,0x44,0x7e,0xd4,0xe4,0xf3,0x3c,0x3f,0xea,0x9b,0x1c,0xbd,
+  0x48,0xe3,0xb1,0xfc,0xf0,0xcf,0xc9,0x65,0xc4,0x3f,0xb6,0xe3,0x39,0xc7,0x49,0x8c,
+  0x1f,0xe0,0x6b,0x0f,0x26,0xf3,0xa3,0xa6,0xf0,0xf9,0xf3,0xeb,0xac,0x83,0x93,0x70,
+  0xa0,0x1a,0x40,0xe2,0xbc,0x7a,0x94,0x17,0xf2,0x04,0xc5,0x5b,0x39,0x3f,0xb6,0xc7,
+  0x7a,0xec,0xf5,0x4f,0x93,0xf9,0xdb,0x88,0x3f,0x7b,0x24,0xbb,0x54,0xc7,0x48,0x54,
+  0x1d,0x53,0xca,0x2c,0x94,0xc7,0x07,0x03,0xd2,0x3c,0x52,0xd7,0x28,0xd6,0xb3,0x88,
+  0xda,0x01,0x8e,0x66,0x13,0xfe,0xa9,0x43,0xf9,0xb3,0x1b,0x1c,0x3e,0xaa,0x64,0xf7,
+  0x2b,0xdb,0x41,0xad,0xb3,0xf0,0x34,0xf8,0x46,0xe6,0xac,0xc6,0xf7,0x2d,0x64,0xdb,
+  0x7f,0xa0,0x2e,0x8c,0x64,0xfb,0x8f,0x25,0xf2,0xdf,0xda,0x73,0x8d,0xfc,0x28,0x4e,
+  0xe2,0x31,0x42,0x39,0xdf,0x26,0x2e,0xfb,0x10,0x69,0x91,0x68,0x35,0x0e,0x56,0x68,
+  0x6d,0xd5,0xf6,0x85,0xf4,0x17,0x8a,0x29,0x3f,0x4a,0x79,0x96,0x9e,0xf5,0x95,0x6b,
+  0xce,0x60,0xf6,0x19,0xef,0x6d,0x88,0x66,0x79,0x3e,0xbc,0x7e,0x00,0xf1,0x12,0x3e,
+  0xff,0x8c,0xc9,0xe3,0x9c,0x3f,0xa4,0x5d,0x4d,0xe2,0x9f,0x08,0x74,0x06,0x38,0xfe,
+  0x59,0xb2,0xc1,0x7e,0x46,0xe2,0x6d,0x41,0x62,0xf9,0xf3,0xfa,0xa3,0x1e,0x9b,0x22,
+  0x0e,0xc9,0xbb,0x95,0x4a,0x5f,0x0a,0xfe,0xa1,0xbc,0x3e,0x4e,0x43,0x50,0xed,0xc7,
+  0x65,0x1f,0x26,0x7c,0xfd,0x0b,0x4e,0x41,0x24,0xe3,0x67,0xb8,0xec,0x46,0xc5,0xa2,
+  0x9b,0x2e,0x5e,0x95,0xd3,0x6a,0x8a,0x0f,0xce,0xaf,0xde,0xaf,0xcf,0x0a,0xb6,0x45,
+  0x27,0xf5,0xb0,0x56,0x7f,0x51,0x63,0x16,0xef,0x86,0xb6,0x2e,0xfa,0x73,0x96,0x19,
+  0x22,0x79,0x64,0x9d,0xaf,0x20,0x44,0x87,0x26,0x79,0x12,0xa7,0x8b,0x4a,0x77,0xe1,
+  0xb1,0x72,0x6e,0x93,0x55,0xf7,0x80,0xb2,0x05,0xad,0xcb,0xeb,0x5d,0x33,0xfa,0x01,
+  0xcf,0x0b,0xef,0x5f,0x99,0xd6,0xfb,0xbc,0xaf,0xa3,0x81,0x4e,0x4b,0x4f,0xe2,0x1f,
+  0x50,0xbe,0x09,0xbb,0x68,0x31,0x3b,0xd4,0x40,0xf6,0xc3,0x16,0x3a,0x93,0xc7,0xcb,
+  0x0e,0xe3,0xb1,0x9d,0xa9,0xd3,0x51,0x54,0x42,0xab,0x20,0xdf,0x53,0xe7,0x4d,0x4f,
+  0xe2,0x1f,0xda,0xfe,0x6d,0x78,0x99,0x2d,0x40,0xd8,0x83,0x20,0xf3,0x19,0x56,0x7a,
+  0xfa,0xa6,0x95,0xe2,0xbb,0xe4,0xb5,0xe6,0x59,0xd1,0xba,0x95,0x72,0x25,0xfc,0x89,
+  0xfd,0xc8,0xe7,0x5c,0x2a,0xb6,0x26,0xf1,0xcf,0x94,0x90,0x70,0x21,0x96,0xed,0xc3,
+  0xf9,0xd6,0x2a,0x23,0x3c,0x0d,0x95,0x18,0x44,0xd0,0x2e,0x71,0x94,0x5c,0x86,0x9f,
+  0x6b,0xeb,0xcd,0xfc,0x00,0xbe,0xdc,0x97,0xe1,0x8f,0x46,0x37,0xd8,0x9a,0xfd,0xf4,
+  0x28,0x73,0x9f,0x36,0xfa,0xa3,0x0d,0x18,0x8d,0x62,0x49,0x99,0x7e,0x94,0x55,0x85,
+  0xe8,0x98,0xb8,0x34,0xb1,0xfe,0xcf,0xd3,0x0d,0xb0,0x2b,0x3b,0xbf,0x5f,0x6e,0x10,
+  0x37,0xc3,0x1f,0xd5,0x5b,0x87,0xbb,0x78,0xbc,0xaf,0x79,0x72,0x7e,0x33,0x75,0x89,
+  0x0d,0x1e,0xb4,0xc8,0x02,0xf4,0x3b,0xa4,0x28,0x31,0x9f,0x77,0x64,0xdd,0x17,0xcb,
+  0xe7,0x1c,0xd5,0x9e,0x83,0xfb,0x79,0x63,0xdc,0x01,0xdc,0x53,0xd3,0xb9,0xe0,0x9a,
+  0xca,0x56,0x41,0xb1,0xd0,0xf5,0xf0,0x31,0x29,0x19,0x1f,0x94,0x18,0x74,0xab,0x6a,
+  0x50,0x2e,0x27,0x1d,0xb0,0x43,0x98,0xc1,0xe5,0xcf,0x61,0x3f,0xd3,0x50,0x11,0x54,
+  0x90,0xc5,0x74,0xa3,0x8e,0x0b,0xbb,0xcd,0x63,0xca,0x8f,0x9a,0xa2,0x4b,0x9f,0x69,
+  0xee,0xe7,0x11,0xc6,0x8c,0xb0,0x8f,0x85,0x02,0xae,0xbf,0x3e,0x81,0x48,0x75,0x99,
+  0x6e,0xdd,0xd7,0x24,0x09,0x91,0x87,0x2a,0xeb,0x07,0x02,0x45,0xb6,0x64,0x7e,0x94,
+  0xb0,0x05,0xe6,0x7b,0x2a,0x79,0x7e,0xf8,0x27,0x70,0xe3,0x44,0x7f,0x90,0xb1,0xea,
+  0x79,0x7a,0x49,0x58,0x3c,0x95,0x31,0x0c,0x95,0x75,0x36,0xbf,0xd8,0x95,0x90,0x6f,
+  0xf9,0x4a,0x18,0xde,0x85,0xd2,0xd7,0xf1,0x3c,0x5e,0xa5,0xaf,0x2a,0xbc,0x11,0xad,
+  0x78,0x15,0x22,0xb4,0x6a,0xd8,0x1a,0x6e,0xba,0x44,0x8e,0x4f,0x72,0xf3,0x7e,0x22,
+  0xf9,0xcb,0x27,0xe6,0x6f,0x91,0x96,0x41,0x6b,0xc8,0xde,0x2b,0x6f,0xf6,0xfc,0x05,
+  0x5e,0x94,0x62,0xfa,0x4b,0x09,0xf4,0x97,0xf0,0x8e,0x81,0xa7,0x15,0x34,0x3d,0xca,
+  0xe5,0xcd,0x7f,0x36,0xf3,0x63,0x2f,0x53,0x9e,0x52,0x3a,0x74,0xb9,0xc7,0x3f,0xc4,
+  0xf9,0x94,0x8c,0x7c,0x1e,0x12,0xd0,0x4b,0xf4,0xf6,0x30,0x39,0x23,0xec,0x69,0x26,
+  0x21,0xb9,0xeb,0x3a,0x35,0x89,0x7f,0xf0,0x1f,0xfe,0xca,0x30,0xea,0x3d,0xfd,0x8b,
+  0xb7,0x42,0x28,0x02,0x3c,0x3e,0xc8,0x60,0x05,0xcb,0xe3,0x7c,0xc8,0x1b,0x78,0xbd,
+  0x18,0x31,0xe1,0x73,0x1e,0x1f,0x3c,0xa1,0xb8,0x9b,0x8d,0x30,0xfa,0x21,0x98,0x3d,
+  0x98,0xc9,0xe3,0x8f,0x11,0xb2,0x42,0x77,0x6e,0x37,0x3a,0x34,0x71,0x7e,0xec,0x36,
+  0x35,0x3d,0x81,0x7f,0x7e,0x31,0x0a,0x23,0x85,0x55,0x8d,0xf8,0xbe,0xc7,0x11,0xdd,
+  0x55,0xbd,0x6d,0xc4,0x07,0x2f,0xf1,0xb4,0x16,0x0e,0x84,0x46,0x38,0xbf,0x31,0xcb,
+  0xe9,0x5a,0x9d,0xc4,0x3f,0xf1,0x6a,0xca,0x80,0xf8,0x85,0x72,0x84,0x55,0x45,0xd6,
+  0x76,0x17,0xb8,0x39,0x3f,0x92,0x7a,0x77,0x44,0x1c,0x27,0x07,0x58,0x29,0x35,0xf2,
+  0xbd,0x13,0xf3,0xdb,0x79,0x7e,0x78,0x8c,0x0d,0x80,0xb5,0xb1,0x59,0x43,0xf4,0x12,
+  0xb1,0x2b,0x78,0x45,0xa5,0xed,0xe4,0xc3,0x46,0x94,0xcf,0x85,0xb4,0x87,0x03,0xbb,
+  0x89,0xf3,0x9e,0xb6,0x36,0xde,0xed,0x9d,0x0c,0xa1,0x6c,0x72,0xea,0x96,0xd9,0x37,
+  0x30,0x69,0x07,0x94,0x34,0x2e,0x84,0xec,0x68,0x6d,0x8b,0xa4,0x6e,0xc1,0x1d,0x42,
+  0x84,0x89,0xf9,0xba,0xb4,0x2d,0x5e,0x4d,0xef,0x1f,0x51,0xdb,0x7c,0x25,0x7a,0x7d,
+  0x98,0x84,0xf8,0x7f,0xf1,0x0e,0x5e,0x96,0xc8,0x5b,0x67,0xaa,0xf8,0x21,0xc2,0x89,
+  0x7c,0x83,0xea,0x29,0x71,0x76,0xf4,0xb5,0x64,0x80,0xf3,0x1b,0xf7,0x2e,0x0e,0x17,
+  0xbc,0xa0,0x5e,0xd4,0xf3,0xd4,0xac,0x9e,0xff,0x32,0xcc,0x5a,0xb2,0xdd,0x3e,0x67,
+  0x58,0x54,0x12,0x78,0x2f,0x24,0xc4,0x69,0x9f,0x4f,0x89,0x97,0x24,0x5e,0xf6,0xd5,
+  0x36,0x2a,0xfe,0x44,0xbb,0x4a,0x7e,0x0e,0xb8,0x31,0x3e,0x62,0x57,0xfd,0x15,0x7c,
+  0xa1,0x52,0xf8,0xb1,0x63,0xf7,0x5f,0x25,0x3e,0x03,0x17,0xb4,0x0a,0xdd,0xea,0xca,
+  0x99,0xa9,0x5d,0xe4,0x8d,0x0b,0x11,0x6f,0x6b,0x11,0xde,0x5a,0xbd,0x7b,0x52,0x0a,
+  0x3f,0x64,0xec,0xf9,0xbb,0x78,0x98,0x38,0x30,0x2b,0x92,0x39,0x8a,0x86,0xc0,0x6e,
+  0x6f,0x49,0x35,0xbe,0xd1,0x21,0xed,0x4d,0x86,0xfa,0xa8,0xcc,0xc4,0x0f,0xa9,0x4b,
+  0x8b,0x63,0xeb,0x43,0xd3,0xfb,0xa5,0xb0,0xe4,0xe0,0xf5,0xec,0xcd,0xea,0x8e,0x6a,
+  0xa7,0x26,0x3a,0x10,0x28,0x36,0xea,0x0e,0x8d,0xba,0xec,0xc9,0xfe,0x68,0x63,0xca,
+  0x77,0x99,0xc1,0x06,0xb0,0x94,0xfc,0x01,0x76,0x32,0x67,0xb4,0x7e,0xfe,0x0d,0x4f,
+  0x4d,0x36,0x32,0xc6,0xff,0x87,0xe7,0x5d,0xe9,0x17,0xe1,0x99,0x3e,0xca,0x0b,0x5d,
+  0x27,0xee,0x5f,0x47,0xef,0xe6,0xfc,0x00,0xfd,0x36,0x59,0xec,0x87,0x73,0x50,0x11,
+  0xa1,0xf3,0xe5,0x66,0xf8,0x4c,0xaf,0xe8,0x9f,0x54,0x24,0xea,0xe4,0xd5,0x50,0x39,
+  0x73,0xce,0x37,0xfb,0x7f,0xa6,0xc4,0xd7,0xe7,0x18,0x0f,0xa3,0xd3,0xaa,0x41,0xdb,
+  0xf6,0x9a,0x7a,0xb8,0xc8,0xf9,0x91,0xce,0x8a,0xe7,0x61,0xbb,0x34,0x97,0x77,0x0c,
+  0x49,0xd6,0xc7,0x51,0xfc,0x5e,0xc6,0xfa,0xec,0x79,0x6e,0x31,0xef,0xf6,0x35,0x60,
+  0xdb,0x25,0x76,0x06,0x1e,0x66,0xee,0x7b,0x6c,0xe5,0x39,0xe5,0x70,0x96,0x27,0x42,
+  0x87,0xc5,0x83,0xc9,0xfd,0x90,0xc7,0xf3,0xc3,0x11,0xed,0xfc,0x93,0x7b,0xaa,0xb4,
+  0x2a,0xab,0x58,0xcf,0x98,0x2d,0x4e,0x0d,0xbd,0x0c,0xb7,0xb6,0x2f,0xe2,0x88,0xe8,
+  0x25,0xc8,0xaf,0x36,0xf2,0xc3,0x27,0xe6,0xab,0xf0,0x34,0x9d,0xcb,0x1e,0x88,0xca,
+  0x57,0xc8,0x3f,0x49,0x4f,0x6c,0x29,0x9e,0x28,0x03,0x9c,0x39,0x2c,0xff,0x84,0xdc,
+  0x00,0xfb,0x74,0x9e,0x3a,0x6e,0xaa,0x4f,0xa9,0x97,0x8c,0xfd,0xd6,0x2b,0xcf,0xf1,
+  0x97,0xb0,0xc7,0x11,0xf6,0xdc,0xe9,0x22,0x6b,0xb5,0xee,0x66,0x5c,0xe1,0x0a,0xff,
+  0xdd,0xda,0x76,0x9e,0x98,0xc7,0xf9,0x21,0x27,0xe6,0x0f,0x4f,0xe1,0x65,0x44,0x28,
+  0x4f,0xb6,0x89,0x8f,0xb2,0xb7,0x8d,0xb2,0x38,0x79,0x18,0xae,0xe8,0xf3,0x58,0xdb,
+  0x70,0x41,0xb9,0xf4,0x45,0xed,0x7f,0x67,0x06,0x3f,0xe4,0xc4,0xfb,0xd6,0x09,0xc9,
+  0xb6,0x20,0x64,0x98,0x56,0x2a,0x99,0xcd,0xa8,0x3b,0xc7,0xf2,0x66,0x20,0xfe,0x89,
+  0x65,0x10,0x11,0x5b,0x73,0x4a,0x7d,0x5c,0x67,0x2c,0x2d,0xea,0x29,0x5e,0x1d,0x8f,
+  0xfa,0x7d,0xf1,0x0d,0xe2,0x72,0x75,0x5c,0xa8,0xf4,0xa6,0x3d,0xc9,0x15,0x1f,0xdb,
+  0xc3,0x2b,0xe8,0xaf,0xe1,0x07,0x00,0xdc,0x2d,0x3d,0x08,0x63,0x9a,0x54,0xd5,0x1b,
+  0xd8,0x2c,0xae,0x80,0xdd,0xd5,0x25,0xfa,0x9d,0x86,0xff,0x21,0xdb,0xe8,0xf7,0x11,
+  0x35,0xe1,0x9f,0x42,0xd8,0x2d,0xf0,0x32,0xf6,0xec,0x21,0x4e,0xa3,0xed,0xa1,0xc1,
+  0x8d,0xc6,0x1d,0x38,0x0d,0xd4,0x10,0x22,0xa8,0x22,0x5f,0x4a,0x7e,0xb8,0x81,0x7f,
+  0x62,0xde,0x8f,0xd7,0x84,0x16,0x08,0x71,0x18,0x50,0x0b,0xdb,0x19,0xe7,0x87,0x24,
+  0xaf,0xd1,0xdd,0xa0,0xfa,0xf0,0x27,0x3d,0x89,0x7f,0x0c,0x7e,0x80,0x12,0x83,0x8d,
+  0x90,0x44,0x24,0xc3,0xdb,0xe3,0xe3,0x85,0x5a,0x70,0x93,0x41,0x8c,0x00,0xf3,0xf8,
+  0x8b,0xbf,0x6b,0xe2,0x87,0x8c,0xa5,0x81,0x21,0xa8,0x36,0xf2,0xbd,0xbd,0xff,0xb2,
+  0xc9,0x28,0x73,0x8b,0x33,0x06,0xa0,0xa1,0xe1,0xc5,0x41,0x2a,0x3f,0x40,0x3c,0x6d,
+  0x6c,0xb9,0x36,0x1e,0xcb,0xbe,0x93,0xe8,0x65,0x04,0x8a,0x1c,0x41,0xa9,0x08,0xa5,
+  0x38,0x3f,0xa4,0x89,0x1f,0x20,0x8f,0x67,0x43,0x19,0x6c,0x00,0x51,0x12,0x80,0x92,
+  0x5c,0x79,0x15,0xef,0x0f,0x02,0xa4,0x51,0xe6,0x8d,0x62,0x7b,0x48,0x89,0xb2,0x88,
+  0x59,0xd6,0x99,0xf1,0x4f,0xc6,0x44,0xf7,0x37,0xc6,0x89,0x79,0x71,0xc0,0x57,0xa0,
+  0xcb,0xf0,0xff,0x74,0xe2,0x8b,0xf3,0xfc,0xf9,0xec,0x04,0xbe,0x6a,0x97,0x12,0xec,
+  0x9a,0x1f,0x68,0x2d,0x86,0xdb,0xc7,0x82,0x2b,0xac,0x16,0xc5,0x13,0xd5,0x9a,0x4b,
+  0xf8,0x7a,0x3e,0x6b,0xe2,0x87,0x9c,0x78,0xfe,0x7b,0xbe,0xcf,0xd9,0x6c,0xb4,0xa3,
+  0x4a,0x4e,0x21,0x6e,0x7b,0xc3,0x8d,0x33,0x24,0x8c,0x43,0x49,0x3d,0x2e,0x85,0x29,
+  0x3f,0x4a,0x88,0xef,0x07,0x4e,0x3b,0x90,0x74,0x04,0x05,0xca,0x78,0xbe,0xe5,0x9f,
+  0x05,0x9e,0x3a,0xb5,0x1e,0xf1,0x8f,0x89,0x5f,0x3d,0xb9,0xdf,0xa4,0x13,0x42,0x25,
+  0x59,0xcc,0xda,0x78,0xa2,0x54,0x25,0xb5,0x35,0x8a,0x51,0x65,0xac,0x19,0xbf,0x48,
+  0x20,0xa5,0x3e,0xce,0x01,0x7b,0x78,0x5a,0x78,0xa7,0x18,0x80,0x56,0x36,0x2b,0x68,
+  0x1d,0x26,0xcf,0xc3,0x3a,0x7f,0x56,0x40,0xee,0xb2,0x8f,0xa9,0xfb,0x59,0x01,0x0b,
+  0x9c,0x36,0xf7,0x07,0x91,0x16,0x0b,0x86,0xfc,0x71,0x73,0x76,0xbe,0x51,0xe7,0xa0,
+  0xe3,0x56,0xb2,0x9e,0x6d,0x55,0x8c,0x85,0x42,0x43,0x55,0x08,0x45,0x03,0x9c,0x1f,
+  0x32,0xa1,0xef,0x94,0xfb,0x62,0xe7,0xf7,0x91,0x3b,0x36,0xa3,0xf6,0x77,0x46,0x2d,
+  0x08,0x84,0xd4,0x35,0xf0,0x80,0x2e,0x22,0x90,0x50,0x5e,0x09,0xa8,0xa3,0x11,0x8d,
+  0x0c,0x27,0xe6,0x07,0x02,0xdf,0x45,0xfb,0x05,0xf1,0xcf,0xd2,0x9c,0xab,0x9e,0x37,
+  0xd8,0x02,0xde,0x28,0xe4,0x69,0xf8,0xb3,0xff,0x26,0xbc,0x52,0x70,0x0c,0xbe,0x34,
+  0x5a,0xa7,0x89,0x1f,0xcd,0x98,0x98,0x4f,0xa7,0xc4,0xe5,0xc9,0x2f,0x39,0x1e,0xf0,
+  0x55,0x32,0x4e,0x0b,0xc9,0x2e,0x0a,0x86,0xa2,0x3f,0x1f,0x6b,0x04,0x16,0xcc,0x31,
+  0xf1,0x03,0x48,0xfb,0x8d,0xfe,0x20,0xb6,0x4b,0xdf,0xb8,0x92,0x7b,0x55,0xc7,0xc1,
+  0x52,0xf1,0x15,0xb8,0x1a,0xfc,0xf9,0xf9,0x25,0x27,0x6a,0xe6,0xc1,0x1b,0x7e,0x83,
+  0x28,0x09,0x12,0xfb,0xe7,0x85,0xbc,0xb5,0xda,0x2e,0xce,0x06,0x89,0xf8,0x27,0x80,
+  0x2f,0xc2,0xeb,0xdd,0x14,0xf5,0x89,0x1e,0xbc,0xa2,0x88,0x8f,0x78,0x57,0x6f,0xcf,
+  0xef,0x5f,0xe4,0x25,0x45,0xcd,0x89,0xfb,0xc3,0xe6,0x3a,0xe3,0x7d,0xff,0x1b,0x9a,
+  0x69,0x2f,0xe3,0xc0,0xa2,0x11,0x94,0x60,0x85,0xc5,0x20,0x0f,0xfa,0x15,0x58,0xef,
+  0xb9,0x9f,0xd7,0xf3,0x9a,0xf8,0x91,0xa4,0x18,0xbb,0x4b,0x9b,0x8b,0x3c,0xa6,0x76,
+  0x6b,0x4e,0x8d,0x02,0x5a,0x37,0x8f,0x83,0x73,0xb2,0xac,0xf8,0xbf,0x0f,0x7e,0x09,
+  0xe5,0x8f,0x62,0xe2,0x47,0xea,0x9a,0xc2,0xb3,0x49,0x4b,0x74,0x5b,0x8f,0x78,0x99,
+  0xee,0x85,0x0a,0x2d,0x2b,0x54,0xf0,0x9c,0x36,0xc6,0x4a,0x1c,0x6b,0xda,0xc5,0x62,
+  0xcf,0x21,0xf6,0xf0,0x25,0xdc,0x21,0x45,0x89,0xfd,0xc3,0x84,0xf8,0xfa,0x6c,0x10,
+  0x7f,0xcb,0x37,0x92,0x9e,0xa5,0xd6,0x8c,0xd0,0xb7,0xc8,0xbc,0xbc,0xf5,0xc1,0x9c,
+  0x0f,0xb4,0x71,0x65,0x3f,0x6f,0xe4,0x14,0x4d,0xec,0x9f,0x7c,0x25,0x2e,0xcf,0x2f,
+  0x88,0xfb,0xa4,0xa3,0x28,0xaf,0xac,0x83,0xe2,0x3f,0x29,0x97,0x60,0x16,0x6f,0x1c,
+  0x76,0x1e,0x0e,0xf3,0xfe,0x5f,0x83,0x22,0xd4,0x4e,0x3c,0xff,0x16,0x69,0x85,0xa1,
+  0xbf,0xda,0x36,0x93,0x91,0xbc,0x43,0xc1,0x12,0x46,0x7f,0x75,0xdd,0x36,0xe8,0x61,
+  0x25,0xfa,0xa2,0x1e,0xf2,0x67,0xd2,0xc8,0x54,0xa0,0xb9,0xe6,0xfe,0x68,0x42,0x5c,
+  0xdf,0x75,0xe2,0xfe,0xc1,0xf3,0x02,0x8e,0x90,0xbd,0xb0,0x79,0x0f,0x2b,0x51,0xe4,
+  0x0d,0xe4,0x53,0xb5,0xad,0xd1,0xee,0xa3,0x9b,0x3d,0xe6,0xfe,0x68,0xd6,0x38,0x1e,
+  0xf0,0x0c,0x20,0xda,0x71,0xaa,0x54,0x25,0x8c,0xb7,0x81,0x00,0xc3,0x10,0x0b,0xdc,
+  0xaf,0xfa,0x1c,0xe6,0xfe,0x44,0x24,0x73,0xc5,0x52,0xe3,0x7d,0x9f,0x11,0xf7,0xc5,
+  0xba,0x31,0xae,0x92,0x0b,0xa5,0x0b,0x0f,0xe3,0x89,0x78,0x49,0x1c,0xa2,0x87,0x7c,
+  0x68,0xb1,0x6e,0x12,0x93,0xfd,0xd1,0xb6,0xdc,0x74,0xc9,0x6a,0xbc,0x6f,0x9f,0x78,
+  0x89,0x8e,0xc0,0xcd,0x60,0xd3,0x73,0x46,0xe9,0x05,0xad,0x0a,0x6c,0x0f,0xe3,0xfb,
+  0x5e,0x50,0x8c,0x7e,0x70,0xc3,0x49,0x7f,0x8e,0x70,0x05,0xfe,0xb4,0xaa,0x34,0xc3,
+  0xa6,0x17,0x9c,0xd7,0xbf,0x64,0xb1,0xb6,0x20,0xea,0x51,0x1c,0xf0,0xfa,0x02,0x7a,
+  0x72,0x66,0x69,0xbe,0x55,0x4f,0xed,0x0f,0x2b,0xf5,0xb0,0x19,0x0b,0xe5,0x76,0xcf,
+  0x29,0xcd,0xc8,0x96,0xef,0x41,0x43,0x95,0x27,0x8a,0xd3,0x1e,0x32,0xd2,0x1c,0xf0,
+  0xd9,0x55,0xda,0x64,0x49,0xe1,0x47,0x42,0x04,0xbd,0xdc,0xba,0x48,0xe0,0xde,0xad,
+  0x58,0xd9,0x7b,0x24,0x56,0xef,0xe6,0x22,0x23,0xea,0x06,0x8b,0x9d,0x51,0x33,0x3f,
+  0x09,0xe7,0x47,0xda,0x4d,0xce,0xf8,0xe4,0x76,0x78,0x1f,0xe2,0x34,0xe3,0x9f,0x92,
+  0xd6,0xec,0x8e,0x5e,0x23,0xdf,0xbe,0xc5,0x7f,0xda,0xe8,0x0f,0x92,0x8c,0x8f,0xe0,
+  0xfe,0x41,0x23,0xe8,0x21,0xdb,0xda,0xad,0x23,0xd2,0xc5,0x58,0xd9,0xfe,0xfb,0xfe,
+  0x48,0xc4,0x7d,0x0c,0x61,0xcf,0x80,0xef,0x44,0x28,0xfc,0xed,0xc5,0x6b,0x0b,0x94,
+  0x14,0x7e,0x80,0x9f,0x06,0xe7,0x73,0xb1,0x33,0x3a,0xd1,0xff,0xa2,0x5f,0xba,0xcc,
+  0xaa,0x8e,0xd9,0x46,0x6b,0xae,0xd0,0xcf,0xb9,0xc7,0xcc,0xdb,0x94,0xda,0x1f,0xed,
+  0x00,0x45,0x6d,0xfe,0x78,0xc1,0x03,0x08,0x03,0x8c,0xfb,0x7f,0x02,0x07,0x95,0x6e,
+  0xdd,0xf0,0xff,0x7c,0x04,0xee,0xde,0x25,0xcf,0xa4,0xf0,0x43,0x3a,0x81,0x44,0xec,
+  0xdf,0x14,0x37,0x93,0x7c,0xed,0xfd,0x18,0xad,0xc4,0xa7,0xcc,0xcf,0xe6,0x9c,0xa3,
+  0xdd,0xe4,0x2f,0xb5,0x2d,0x5e,0xfb,0x26,0x79,0x73,0xcd,0xc3,0xa6,0xf8,0xd7,0x62,
+  0x60,0xba,0x1a,0x5c,0xe4,0x82,0x66,0x61,0xc7,0x80,0x91,0xcf,0xdc,0xcb,0x18,0x53,
+  0x83,0x94,0xd7,0x73,0x75,0x28,0x85,0xb0,0x48,0x25,0xa9,0xfc,0x48,0x8f,0x05,0xbf,
+  0xef,0x93,0x97,0x5a,0x9e,0x16,0xe2,0x6d,0x41,0xde,0xd5,0x9a,0x07,0xb7,0x86,0x78,
+  0xd8,0x4b,0x5a,0x15,0xc4,0x2b,0x6f,0x11,0x33,0x3f,0xa4,0x15,0x7a,0xc1,0x35,0xb8,
+  0xc4,0x9d,0xdd,0xcc,0x3e,0x03,0x57,0x14,0xcd,0xa8,0x08,0x39,0x34,0x59,0xd5,0x9d,
+  0x2e,0xb1,0x5f,0x1d,0x56,0xe6,0x08,0xa8,0xaf,0xcd,0xfc,0x48,0x9b,0xc9,0x79,0x98,
+  0xaf,0x2f,0x19,0x14,0x2b,0x62,0xeb,0x63,0x94,0xc5,0x29,0x0b,0xfa,0xf1,0xc5,0x4f,
+  0x48,0x97,0x95,0xbd,0xaf,0xe3,0xd2,0xa5,0xf0,0x03,0x08,0xe3,0x7e,0xce,0x46,0x2e,
+  0x6e,0x83,0x43,0x13,0x65,0x1a,0x3a,0xb8,0x86,0x8d,0xfa,0xc1,0x23,0x68,0xff,0x5e,
+  0xd3,0x1f,0x76,0x73,0xda,0xcb,0x52,0xbe,0x66,0xa4,0x59,0x7e,0x19,0xa3,0x05,0x38,
+  0xc9,0xf3,0x06,0x6a,0x51,0x90,0x9e,0x24,0x8f,0xa5,0xe5,0x0f,0xc8,0x5e,0x4b,0x6a,
+  0x7f,0xb4,0x7d,0xfe,0x99,0x1c,0xef,0x1d,0x31,0xe2,0x7d,0x46,0x5b,0xd8,0x75,0xac,
+  0x80,0xbf,0xef,0x17,0xb0,0x9a,0xfd,0xc0,0x27,0x5f,0xc3,0x8f,0x24,0xec,0x18,0x74,
+  0x9c,0x90,0xa7,0xa4,0x8f,0x68,0x8f,0xc7,0xea,0x7d,0x0e,0x6b,0x6d,0x4c,0xb5,0x52,
+  0xce,0x4f,0xd2,0xe2,0xad,0x1f,0x94,0x37,0x91,0x6b,0xf8,0x91,0x94,0xf9,0xc1,0x25,
+  0xc3,0xe2,0x18,0xa7,0x35,0x30,0xd0,0x0e,0x1c,0x19,0x75,0x07,0x9d,0x46,0xa1,0x9c,
+  0xbe,0xa7,0xd9,0xf6,0x61,0x53,0x2a,0x3f,0xd2,0x98,0xf0,0x4b,0x58,0xbf,0x1a,0x4e,
+  0xc5,0x15,0x53,0x41,0xd4,0x3e,0x26,0xec,0x57,0xb8,0x86,0xa2,0x63,0xf6,0x19,0xc2,
+  0x35,0xf8,0xc7,0xd0,0x8f,0xcb,0x6d,0x1b,0x72,0x86,0xb4,0x03,0x8c,0xd7,0x4f,0x15,
+  0xbc,0x46,0x0e,0x4c,0x76,0x47,0x71,0x19,0x9f,0xe5,0xfd,0x41,0xaa,0x11,0x1a,0x11,
+  0x33,0xfe,0x91,0x38,0x7a,0x91,0x37,0x93,0x33,0xec,0xf9,0xc0,0x44,0x9b,0x57,0x66,
+  0x5f,0x89,0xf2,0x61,0x86,0xbd,0x85,0x9b,0x5a,0x4f,0xa5,0xe6,0x87,0xc3,0x5e,0xca,
+  0x8b,0xe0,0x3c,0x38,0x4d,0x9d,0x98,0x0f,0x46,0x44,0xac,0x53,0x8b,0x0f,0x52,0xfb,
+  0xc3,0x1a,0xf5,0x71,0x88,0x76,0xa4,0x2d,0x71,0x20,0x04,0x8d,0xb5,0x21,0x23,0x22,
+  0x86,0x86,0x3f,0xe2,0x9f,0x5c,0x7b,0xd2,0x1e,0x31,0xf8,0x91,0x38,0x1f,0x54,0x08,
+  0xdf,0x2e,0x92,0x6c,0x0b,0xeb,0x8e,0x15,0xca,0xc5,0xf9,0x21,0xcd,0xf9,0xe1,0x43,
+  0xf8,0x59,0x67,0x79,0x97,0x4c,0xf0,0x43,0xda,0x82,0xc2,0xe7,0xbc,0x11,0x21,0x0e,
+  0x6a,0x8e,0xc7,0xa8,0x93,0x1e,0x49,0xc1,0x3f,0xe7,0xe1,0xf3,0xf4,0x4a,0x4f,0xd6,
+  0x60,0x13,0x0e,0x62,0x40,0xe8,0x73,0xc6,0x19,0x23,0x51,0x2c,0xff,0x37,0xf8,0x93,
+  0x03,0x81,0xd0,0xb1,0xa6,0x19,0x29,0xfc,0x00,0x3d,0x42,0x49,0x3b,0x6d,0x26,0x28,
+  0x71,0x62,0x40,0xe8,0x14,0x84,0xa1,0x43,0xa0,0x8c,0xa8,0x81,0x56,0x9f,0x1d,0xe4,
+  0xd5,0x24,0x85,0x1f,0x89,0xe3,0x3d,0xcf,0x42,0x25,0xfd,0xb5,0xd0,0x8e,0x78,0xd8,
+  0x4b,0x47,0x18,0xac,0xd5,0xf1,0xc4,0xef,0x0d,0x46,0xc6,0xb8,0x3f,0xb5,0x3f,0xda,
+  0x6e,0xc5,0xa9,0x59,0xda,0x3d,0x43,0xd2,0x04,0x10,0x0a,0x6c,0x57,0x3b,0xbc,0x34,
+  0x98,0x3d,0xbd,0xf9,0xc9,0x6c,0x94,0x78,0x1b,0xcd,0xfc,0x48,0xb9,0xbc,0x1b,0x5a,
+  0xa5,0x2f,0xeb,0xa9,0x94,0x32,0x7f,0xdd,0xcd,0xf9,0x01,0xfe,0x0b,0xbc,0xa5,0xb9,
+  0x11,0xcf,0xc8,0x8e,0x84,0x7c,0xe8,0x02,0x83,0x1f,0x29,0xf2,0x58,0x0a,0x8d,0x12,
+  0xe2,0xe1,0xd8,0xe0,0x14,0xdd,0xcf,0xa9,0x96,0x3e,0x4a,0xec,0x67,0x83,0x1f,0x09,
+  0x8d,0xdc,0x25,0x2c,0x27,0x2a,0x45,0x48,0x9c,0x16,0x20,0xa2,0x75,0x23,0x10,0x6d,
+  0xc2,0x2f,0xa2,0x55,0xc2,0x12,0x7f,0x8d,0x89,0x1f,0x52,0x72,0xc0,0xfe,0x46,0xe2,
+  0x37,0xba,0x8f,0xac,0x53,0x62,0x6d,0x41,0xf4,0x75,0x90,0x1f,0xa4,0x51,0xf2,0xce,
+  0x0f,0xd7,0x31,0x84,0x46,0x1f,0x11,0xcb,0xc4,0x71,0x07,0x27,0xca,0x9f,0x1d,0x42,
+  0x61,0x44,0x94,0xc9,0x51,0xe6,0xd7,0x0c,0x5a,0xb6,0x23,0xd0,0x14,0x50,0x23,0xb8,
+  0x9e,0xaf,0x91,0x46,0xdd,0x19,0x95,0xa7,0xa6,0xe4,0x87,0x4f,0x85,0x97,0x02,0xd3,
+  0xf5,0x36,0x1f,0x79,0x87,0x36,0x33,0xa3,0xbe,0xe3,0x5d,0xb2,0x86,0xe6,0x33,0x5a,
+  0x4b,0x4e,0xd0,0x66,0x4b,0x71,0x1f,0xe2,0x01,0x9a,0xc4,0x57,0x74,0x1a,0x7c,0xd1,
+  0x78,0x6b,0xa7,0xad,0xae,0xe0,0x20,0xbc,0xc6,0x76,0xf3,0xf8,0xd7,0x15,0x78,0xa3,
+  0x71,0xb6,0xea,0xac,0x13,0xbf,0xc0,0x2b,0x0b,0x78,0x7e,0xb8,0xc5,0xcc,0x8f,0x94,
+  0x87,0xa0,0x3a,0x60,0x94,0x69,0x8c,0x4d,0xc8,0x93,0x8b,0x02,0xef,0xc8,0x63,0xf0,
+  0xfb,0x55,0x2a,0x88,0x87,0x4d,0xf1,0xaf,0x29,0x57,0xf8,0x7a,0x0e,0xad,0x39,0x31,
+  0xe9,0x8c,0xf6,0x09,0xcb,0x8e,0x25,0x8a,0x1f,0xf5,0xcf,0x0e,0x59,0xc7,0xf1,0xfe,
+  0xef,0xb1,0xaa,0xd1,0x25,0x11,0x53,0x7d,0x74,0xd7,0xf5,0x9b,0xe1,0xa5,0x9d,0xc5,
+  0xfb,0xf0,0xb1,0x8f,0xa9,0x3b,0xc1,0x11,0x5d,0xd4,0x40,0xc6,0x60,0xb5,0x94,0x1f,
+  0xa1,0xdf,0x24,0x6f,0x41,0xbf,0xc4,0xfb,0x13,0xa5,0xf0,0x63,0x6f,0x86,0x9d,0xf0,
+  0x00,0xc5,0x97,0x3a,0x41,0x9f,0x89,0xe7,0x87,0xab,0x6b,0x94,0x7c,0xa8,0x6b,0x20,
+  0xe7,0xb5,0x27,0xf2,0x8a,0x5f,0x97,0x35,0x53,0xbd,0x80,0x4f,0x1a,0x90,0xc2,0xb0,
+  0x82,0xde,0x98,0x9d,0x1e,0xc1,0x6d,0xe9,0x88,0xb5,0x79,0x62,0x83,0x06,0x0d,0xe0,
+  0xd1,0xa0,0x9f,0x39,0x83,0x72,0xda,0x3d,0x79,0x89,0xfd,0xe9,0x40,0xbc,0x87,0xdb,
+  0x46,0x59,0xb2,0x96,0x77,0x77,0x8d,0xe9,0xaf,0x4f,0xc8,0x21,0x70,0x0f,0x3b,0x15,
+  0x71,0x88,0xbd,0xa5,0x57,0x86,0x6c,0x3d,0xb2,0x25,0xa5,0x3f,0xec,0x18,0xab,0xcc,
+  0xb5,0x75,0x09,0xc3,0x2c,0xbe,0x3e,0xc3,0xdc,0x3f,0x0f,0x47,0x37,0x89,0xc3,0x74,
+  0xf8,0xfe,0xca,0x41,0x5b,0xf8,0x71,0x73,0x7f,0xb4,0x4b,0x70,0x89,0xfe,0x58,0xb5,
+  0x72,0x92,0x9f,0xcb,0x31,0x5a,0xec,0xf3,0xf6,0xc3,0x33,0x0d,0xd8,0x33,0x87,0x1c,
+  0x86,0x2a,0x8b,0xed,0xef,0x44,0x35,0xe1,0xff,0x69,0x44,0xfc,0x83,0xc7,0xaa,0xd0,
+  0xb1,0x4d,0x7b,0x5f,0x0a,0x1b,0xb4,0xcc,0xe4,0x34,0x20,0xec,0xe1,0xfe,0x8d,0x26,
+  0xa5,0x45,0x2f,0x71,0xc9,0x6b,0xfd,0xe6,0xfe,0xb0,0x2b,0xb8,0xbf,0x9a,0xd1,0x5f,
+  0xc2,0x69,0x75,0x42,0x5f,0xab,0x6d,0x60,0x0f,0xd1,0x5f,0x7a,0x66,0x40,0x9b,0xce,
+  0xa9,0xcc,0x88,0xc9,0xff,0x03,0x56,0x08,0x17,0x3a,0x5b,0x28,0x78,0xf4,0xe6,0xb0,
+  0x5f,0x35,0xf2,0xc3,0x49,0x2b,0x18,0x7c,0x1d,0x21,0xde,0x4a,0x0c,0xcf,0x63,0x91,
+  0x29,0xc3,0x8b,0xae,0x80,0x31,0xc7,0x3c,0x6a,0xb4,0x45,0x1e,0x87,0xee,0xb7,0x8d,
+  0xc6,0x70,0xaf,0x72,0x43,0x2c,0x18,0x8b,0xff,0xa2,0x68,0x2a,0x50,0x4d,0xf1,0x2f,
+  0xc3,0xdb,0x23,0x4d,0xd2,0xc5,0x51,0xed,0x3c,0x54,0x1d,0xe4,0xef,0x1b,0x0b,0x84,
+  0x0d,0x8a,0x83,0xf4,0x12,0xe1,0xfd,0x61,0xbf,0x65,0xe6,0xc7,0x8e,0xfb,0x7f,0xc6,
+  0x73,0x2a,0xc8,0xd3,0xbe,0xd2,0xc8,0x4d,0x11,0xe1,0x3e,0x6d,0x80,0xdd,0xac,0x4e,
+  0x3a,0x27,0x56,0x44,0xae,0x2a,0xf9,0xaa,0xf5,0x64,0x0a,0xfe,0x19,0x09,0x19,0x6c,
+  0xcf,0x61,0xb2,0xc0,0x1b,0xa8,0x2e,0x88,0x5a,0xba,0xec,0x97,0xf5,0x00,0x7b,0x30,
+  0x24,0xff,0xc9,0x52,0x51,0xbb,0xf7,0x9b,0x76,0x4a,0xb3,0x53,0xf9,0x21,0x63,0x78,
+  0x2f,0x48,0xac,0xc0,0x5c,0xa1,0x41,0x4e,0x4b,0xa2,0xe0,0x6b,0x56,0x1f,0x52,0x97,
+  0x59,0x9b,0xbb,0xd5,0x65,0x96,0xba,0xec,0xf4,0x6b,0xfa,0xc3,0x42,0x49,0xaf,0x1c,
+  0xb6,0x38,0xa1,0xd5,0x6a,0xd7,0x2d,0xdd,0xfe,0x11,0x12,0x60,0x25,0xfd,0x62,0x17,
+  0x71,0x22,0x10,0xb5,0x2b,0x88,0x3f,0xcd,0xf8,0x67,0x45,0x0c,0x0f,0x97,0x8b,0x56,
+  0x23,0x1b,0x07,0xad,0xa1,0x91,0x8c,0x43,0x7a,0x89,0xdb,0x66,0x74,0x8c,0x0d,0xb9,
+  0x14,0xe7,0x06,0x53,0x7d,0x5c,0x34,0xee,0xff,0x59,0x7f,0x8e,0x77,0x37,0x83,0x05,
+  0xbd,0xb6,0x48,0x13,0xe7,0x87,0xfc,0xb9,0x6a,0xf3,0x71,0xfe,0x79,0x5a,0x95,0x8d,
+  0xf6,0x42,0x2a,0xfe,0x89,0xb3,0xd3,0x3b,0xd9,0x01,0xad,0x2c,0x82,0x68,0x73,0x84,
+  0xff,0x87,0x34,0x23,0x03,0xff,0xa0,0x72,0x4e,0x75,0x6e,0x4a,0xc5,0x3f,0x0a,0xc7,
+  0xc3,0x88,0xd6,0x2a,0xa0,0x15,0x0a,0x06,0xeb,0x36,0xfb,0x2f,0x6b,0x2f,0x0e,0xda,
+  0xff,0x49,0x0e,0xa5,0x5f,0x92,0x5a,0xf5,0x32,0x17,0x6e,0x24,0x33,0x3f,0xe4,0x62,
+  0xca,0xd7,0x27,0xc3,0x45,0xee,0x92,0x5a,0xa1,0x70,0x90,0x52,0xcf,0xa7,0xd0,0xa8,
+  0xab,0x2e,0xdc,0x18,0x8f,0x31,0x54,0xdc,0x6f,0xde,0xe9,0x58,0x68,0xe2,0xc7,0xae,
+  0x9e,0x66,0xb0,0x41,0xd2,0x1f,0x93,0x69,0x34,0x97,0xa9,0xa7,0xf2,0x7e,0x48,0xde,
+  0x3d,0xf5,0x4c,0x20,0xbf,0xf3,0xc6,0xbf,0xf3,0xbc,0xab,0xad,0x09,0x3f,0x13,0xcd,
+  0x58,0x71,0x0d,0xfe,0x41,0xa3,0xa9,0x1f,0x9f,0xdf,0xca,0x74,0x61,0x4e,0xc4,0x6a,
+  0x21,0x47,0x58,0x6f,0xb6,0x0b,0x6c,0x20,0x0e,0x80,0xde,0xe9,0xd2,0xff,0xb3,0xfa,
+  0x6a,0x0a,0x3f,0x36,0x5f,0x9f,0x5e,0xdb,0xa8,0xe7,0x32,0x7c,0xa4,0x54,0x71,0xe0,
+  0x3d,0x02,0x9f,0x2b,0x95,0x8d,0xb6,0xfe,0x9c,0x4b,0x64,0x6c,0xce,0x2b,0xfd,0x59,
+  0x1f,0xa6,0xf0,0x63,0x7f,0x8a,0xa7,0xb5,0xb2,0xd7,0xd6,0x63,0xfb,0x49,0xa4,0x95,
+  0x97,0x61,0xee,0x28,0x18,0xd1,0x5b,0xa0,0xf2,0x9c,0xf5,0x92,0xb8,0xc2,0xb7,0x90,
+  0xd8,0xf5,0xbb,0x42,0x35,0x66,0xfc,0xc3,0x69,0xb1,0x39,0xec,0x99,0x61,0x85,0xd7,
+  0x84,0xe2,0x7e,0xf9,0x61,0x32,0xe0,0x58,0x03,0xb3,0x7a,0x33,0x7d,0xb8,0x43,0x9e,
+  0x85,0x02,0xdd,0x71,0x6d,0x7f,0x58,0x03,0xf6,0x8c,0x91,0xa7,0xdb,0x9b,0xfd,0xc5,
+  0xa7,0xc4,0x47,0xc9,0xbb,0xfe,0x27,0x1a,0x67,0x9d,0xa7,0x79,0xfe,0x69,0xcd,0xcd,
+  0xbd,0xf9,0x5f,0xe5,0x87,0xe4,0xf5,0x3e,0x8b,0x6e,0x23,0x6b,0x49,0x1b,0x0e,0x6e,
+  0xbc,0x8d,0x8c,0xa4,0x23,0x10,0x1a,0xce,0xa0,0xad,0x4e,0xa1,0x8b,0x17,0xaa,0xa8,
+  0xd7,0xe0,0x9f,0x38,0xec,0x19,0x96,0xee,0xe6,0xfe,0x9f,0x4e,0x1c,0xfc,0xa1,0xb3,
+  0x24,0xb4,0x36,0x9a,0xee,0x80,0x23,0xac,0x9b,0x65,0x86,0xe4,0x6b,0xf0,0x8f,0x01,
+  0x03,0x2c,0x9a,0x32,0x4c,0xb3,0x62,0xfa,0x88,0xa7,0xfd,0x2c,0x31,0x0a,0xe7,0x9b,
+  0xf7,0x73,0xfe,0x8d,0xaf,0xe0,0x9f,0x58,0x59,0xdc,0x01,0x28,0x5b,0xbe,0x24,0xf8,
+  0xea,0x07,0xf0,0x96,0xdf,0x08,0xf4,0x7c,0x00,0x07,0x54,0x77,0xfd,0xdd,0x41,0x99,
+  0x5c,0xeb,0xff,0x89,0xc3,0x18,0xc9,0xee,0xe3,0xb4,0x6c,0xd0,0x12,0xb4,0xf3,0x13,
+  0x34,0x64,0x7d,0x8b,0xa9,0x3e,0xfa,0xcb,0x6b,0xf0,0x4f,0x7c,0xfe,0x19,0xee,0x1d,
+  0xd5,0x10,0xdd,0xf1,0x42,0x39,0x5e,0xd8,0x95,0xfe,0x01,0xbf,0xe2,0xfd,0xe1,0xd2,
+  0x6b,0xfa,0xc3,0x22,0x1e,0xe0,0x45,0x70,0x6f,0x10,0x61,0xa2,0x2d,0x5a,0x1b,0x44,
+  0x71,0x60,0x7f,0x0d,0x36,0xe8,0xf9,0x5e,0x7a,0xaf,0x25,0x69,0x7f,0xf5,0x58,0x13,
+  0xfc,0x00,0x51,0xa5,0x0e,0xca,0xa0,0x8d,0xa1,0x98,0x3d,0x61,0x28,0xe2,0x1c,0x8e,
+  0x88,0xba,0xe1,0x6e,0x4d,0x34,0xe1,0x9f,0xcc,0xce,0x89,0xb6,0x68,0xbc,0x1b,0x48,
+  0x65,0x9c,0x16,0x80,0x5f,0x39,0x2e,0x7e,0x20,0x7d,0x5e,0x1d,0x23,0xc6,0x4c,0xc8,
+  0x9f,0xf6,0xb4,0x4e,0x85,0xbb,0x89,0xb2,0x36,0x89,0x9f,0x4b,0x07,0xd4,0x2a,0xde,
+  0x88,0xf9,0x73,0xf5,0x70,0xac,0x7f,0xdc,0xad,0xf0,0xb9,0x6b,0x47,0x6d,0x66,0x30,
+  0xa5,0x3f,0x6c,0x94,0xf5,0x70,0x5a,0x24,0x0e,0x7b,0xba,0x1c,0x31,0x7e,0x6c,0xa9,
+  0x0b,0x3a,0x0c,0x31,0x2b,0xf4,0x3c,0x82,0xf2,0x87,0x90,0x75,0x49,0xf9,0x23,0xf5,
+  0xab,0xf8,0xbe,0x75,0x96,0x6c,0xf2,0x1a,0x6b,0xd4,0x56,0xa0,0xfc,0xf1,0xd4,0xf2,
+  0x8e,0x3c,0xb8,0x50,0x96,0x18,0x55,0xe6,0x35,0xfc,0x90,0xdc,0xff,0x83,0xf8,0x67,
+  0x43,0x36,0xa7,0xe5,0x7c,0x90,0x87,0xbd,0x86,0x0c,0x7e,0x86,0x1b,0x79,0x62,0xd5,
+  0x6e,0xb5,0x83,0x0b,0xea,0xd5,0x29,0xfc,0x90,0x46,0x77,0xd7,0x18,0x2d,0x52,0x85,
+  0x66,0x0d,0x36,0x2d,0x87,0xde,0x46,0x77,0x5d,0x8d,0x52,0x5a,0x28,0xed,0xa6,0x6e,
+  0xed,0x3f,0x73,0xfc,0x93,0xd0,0xbf,0x71,0xff,0x0f,0x0f,0x83,0xaa,0xdc,0xff,0x73,
+  0x94,0xf3,0x85,0x8e,0xeb,0x95,0xd5,0x31,0xa2,0x24,0xb6,0xdf,0xf3,0x4a,0x58,0xbc,
+  0x86,0x1f,0x72,0x62,0xfd,0x71,0x20,0xac,0x6f,0x6e,0x52,0xa5,0x13,0xf1,0xfe,0x74,
+  0xca,0xd8,0x9d,0x6e,0x1e,0x81,0xb5,0x7c,0xc5,0xff,0x23,0x86,0xb4,0x0b,0x38,0x98,
+  0xc5,0xd0,0x30,0x9f,0xc7,0xd6,0x4d,0xb6,0xaf,0x31,0x80,0xd0,0xfe,0xc5,0x05,0xc1,
+  0xbc,0x90,0xb8,0x30,0x85,0x1f,0x92,0xcb,0x9f,0x1b,0x5d,0xe4,0x2f,0xdc,0x71,0x71,
+  0x4c,0x9e,0x43,0x32,0xfd,0x1b,0xfa,0xd4,0x68,0xab,0x2b,0xfd,0x88,0xb0,0x47,0x5a,
+  0xa6,0x17,0xcd,0x4f,0xe1,0xc7,0x9e,0xaa,0xf1,0x7e,0x61,0x6d,0x1c,0x06,0x18,0x8e,
+  0x91,0xb1,0x8d,0x53,0x85,0xc7,0x68,0xac,0xd0,0x55,0x30,0x1a,0xa7,0xfa,0x52,0xf8,
+  0xb1,0xa7,0xb1,0x2f,0xd9,0x82,0xd3,0x9c,0x0d,0x40,0xf9,0xb2,0x8b,0x07,0xc2,0x9a,
+  0xb2,0xa4,0xbf,0x61,0xf9,0xa7,0xb3,0x78,0xa1,0xdc,0x97,0x8d,0xa5,0xa1,0x59,0x4b,
+  0xc5,0x14,0x7e,0x6c,0xee,0x0f,0x89,0xd8,0x8c,0xb4,0x1f,0x4f,0x89,0x51,0xed,0xce,
+  0x25,0xd8,0x09,0xa3,0x63,0xc8,0x5e,0xb2,0x9f,0xa1,0x7d,0x61,0xee,0x0f,0xfb,0x69,
+  0xdc,0xff,0xd3,0xe4,0x86,0xa3,0xed,0xff,0x7d,0xc8,0x7a,0x40,0xbc,0x62,0xfd,0x4b,
+  0x68,0xee,0x72,0xdb,0x6e,0xb1,0x12,0x7f,0x2a,0xdd,0x76,0xd7,0xe5,0x02,0x13,0xfe,
+  0x99,0xfc,0x34,0xa7,0x75,0xd2,0x6d,0x0d,0xf6,0x5c,0x6d,0x4d,0xe0,0x56,0x66,0x29,
+  0x27,0x07,0xd9,0xea,0x40,0x7e,0x48,0x5e,0x29,0xde,0xa4,0x84,0x83,0x5b,0x9a,0x1d,
+  0xdf,0xf3,0x27,0xf1,0x8f,0x62,0xf0,0x43,0x1a,0x66,0x9a,0x02,0x6b,0x54,0xdc,0x2d,
+  0x1a,0x39,0xa9,0xff,0x76,0xf2,0x96,0x3a,0xd1,0x9d,0x7d,0xaf,0x84,0xef,0x1b,0xb8,
+  0x73,0x30,0x3b,0x19,0xff,0xf2,0xe5,0xc6,0xf4,0x9d,0xc5,0x85,0x87,0xb4,0x49,0x2b,
+  0x04,0x19,0x95,0x34,0xf5,0x73,0xbe,0xa9,0x72,0x3f,0xa7,0xaa,0x40,0x7b,0x3f,0x9d,
+  0x98,0xf1,0x0f,0xef,0x57,0x5e,0x85,0xcb,0x88,0xda,0x6d,0x8d,0xe6,0x82,0xcc,0xae,
+  0xd9,0x23,0xe4,0xe3,0x46,0x7b,0xa3,0xbc,0xbf,0x66,0x39,0x5c,0x58,0xdb,0xcd,0x6e,
+  0xea,0x42,0xfc,0x33,0xb1,0x9e,0x41,0x88,0xb1,0x41,0xae,0xdf,0x2e,0xf3,0x36,0xb2,
+  0xfb,0xe1,0xee,0x5f,0x18,0xf9,0x51,0xf3,0x1a,0x6e,0xe6,0xfc,0x90,0xf8,0x93,0x32,
+  0x2b,0x84,0x83,0x84,0x3c,0x51,0x62,0xec,0xc7,0x59,0xa3,0xe2,0x72,0x38,0x4a,0x77,
+  0xb0,0xcc,0xa8,0x78,0x92,0xbe,0x97,0x56,0xca,0x16,0xf3,0x78,0xd0,0x45,0x44,0x44,
+  0xce,0x13,0x62,0x52,0x5f,0x6f,0x88,0xfb,0x7f,0x64,0xfe,0xfc,0x08,0x63,0xc2,0x74,
+  0x35,0xf9,0x0b,0x6b,0xf2,0xab,0xcb,0x1d,0x61,0xcf,0x3f,0x70,0xea,0x9e,0x10,0x6d,
+  0x4e,0xc1,0x3f,0x71,0xff,0x4f,0x38,0xbb,0x9e,0xa1,0xd8,0xb9,0xe3,0xfa,0x46,0x32,
+  0xa2,0xb5,0xae,0xfe,0x07,0x85,0xf2,0x7e,0x6a,0x38,0x3f,0x4c,0xed,0x24,0xc5,0xff,
+  0xc3,0x0c,0x3c,0x10,0x26,0x56,0xd2,0xa6,0xaa,0x50,0x97,0x4d,0x22,0x7e,0x7f,0x00,
+  0x8f,0xad,0xcb,0x5f,0x2b,0x74,0xe7,0x85,0x10,0x22,0x99,0xe4,0x0f,0xcb,0x5c,0x11,
+  0xe2,0xeb,0x63,0x6b,0x10,0x7d,0xca,0x1f,0xf1,0x34,0xdd,0xd5,0x5c,0xf3,0x49,0xf3,
+  0xdb,0xea,0xcb,0x60,0xed,0xe6,0xe7,0x45,0x75,0x33,0x5e,0x3a,0x6a,0xe6,0x87,0xe4,
+  0xfe,0x9f,0xde,0x9b,0x47,0xf3,0x47,0x95,0x8b,0x1c,0xf6,0x34,0x35,0xe9,0xd1,0x73,
+  0x50,0x29,0xdd,0xcc,0xfd,0x5d,0xe3,0xea,0x02,0x66,0xd3,0xcc,0xfc,0x48,0xab,0xae,
+  0xc0,0x25,0x75,0x3e,0x0b,0xd4,0xd5,0x9c,0x0d,0x19,0x1b,0x69,0x14,0xf7,0xcf,0x25,
+  0x69,0x6e,0xf4,0xae,0x57,0x73,0x5c,0xfe,0x81,0xa6,0x52,0xd7,0x92,0xfe,0x9a,0x24,
+  0xfe,0xe9,0xcb,0xfb,0x14,0x76,0xd7,0xdb,0x7d,0x34,0x80,0xf2,0x27,0x1e,0x08,0xfb,
+  0x94,0xd3,0x20,0x44,0xe5,0x26,0xbb,0xaa,0x07,0x1a,0xed,0x54,0x6e,0x36,0xf5,0x87,
+  0x3d,0x08,0x03,0xd0,0xad,0x38,0x42,0xf5,0x90,0xae,0xb3,0x38,0xed,0xf3,0x00,0x67,
+  0x4f,0xd3,0x33,0xb2,0x09,0x14,0x06,0xc0,0x51,0x27,0xa7,0x93,0xee,0x64,0xfe,0x4f,
+  0xda,0x36,0xe8,0xc9,0xb3,0x47,0xe9,0x36,0x14,0x3b,0xf3,0x63,0xb4,0xd2,0x9c,0x1f,
+  0xa0,0xa8,0x57,0x0e,0x58,0x66,0xa0,0x3c,0x6f,0xd5,0xe4,0x76,0xd2,0x93,0x90,0x0f,
+  0xd5,0x53,0x78,0x7f,0xd2,0x79,0xdc,0x09,0x7c,0xfa,0xef,0x12,0xb4,0xcc,0x17,0x19,
+  0x22,0x96,0x56,0xd1,0xbe,0xb6,0x6f,0xc3,0x0d,0x4e,0xdb,0x66,0x79,0x93,0xa9,0x3f,
+  0xec,0x3e,0x8e,0x9f,0x61,0xfd,0x20,0x82,0x1c,0xbe,0x31,0x32,0xc3,0x05,0x97,0xe8,
+  0x55,0x98,0x6b,0xf4,0x1f,0x44,0x41,0xf3,0x35,0xbe,0x3e,0xf5,0xc9,0xfe,0xb3,0xbc,
+  0x3f,0xac,0xe2,0x6e,0xb1,0x36,0x8b,0x21,0x76,0x71,0xa2,0xff,0xa9,0x31,0xd8,0x24,
+  0x16,0xb2,0x61,0x09,0x45,0xd3,0x2e,0xf1,0x7c,0x42,0xfe,0xe8,0xb8,0x1f,0x7a,0x26,
+  0xab,0x7d,0xf4,0x77,0x1b,0xbf,0xce,0x8c,0x8d,0x31,0x4a,0x78,0xe3,0xc5,0x2c,0x5d,
+  0x6e,0x6f,0x9d,0xce,0x55,0xd5,0x26,0x54,0x55,0xa9,0xf1,0xaf,0x1e,0x2d,0x14,0xa6,
+  0x79,0x44,0x9b,0x68,0xa3,0x63,0xc5,0x15,0xb3,0xea,0x72,0xa7,0xbf,0xa4,0x76,0xcb,
+  0xaf,0xad,0x9d,0x72,0xa1,0x96,0xe4,0x47,0x1a,0x55,0xb8,0x3f,0x39,0x3f,0xea,0x88,
+  0x58,0xee,0x61,0x71,0x5a,0x6c,0xce,0x17,0x8d,0x83,0x3b,0x49,0xb6,0xf2,0x12,0x0f,
+  0x84,0xd5,0x99,0xf9,0x01,0xe8,0xe2,0x8c,0xcf,0xc0,0xb5,0xcd,0xa9,0xe4,0x2c,0x6c,
+  0xfc,0x0c,0x38,0x3f,0x00,0x02,0xc5,0x73,0x50,0xa1,0xdb,0xa0,0x46,0xd2,0x4f,0xf3,
+  0x81,0x22,0x1e,0x4b,0xf2,0x03,0xc4,0xe2,0x5f,0xec,0x1f,0x7b,0x79,0xff,0x5c,0x05,
+  0x81,0xcd,0xa8,0x8c,0x27,0x88,0x03,0x21,0x5d,0x3c,0x5f,0x6b,0x04,0xc2,0x10,0x48,
+  0x27,0xe5,0x73,0x2c,0xfe,0xc5,0x6c,0x79,0x62,0x61,0x6c,0x59,0x46,0x8d,0x7e,0xcd,
+  0xdd,0x7c,0x50,0x0e,0x17,0xf3,0x2b,0x17,0xda,0xa2,0xe2,0xc1,0x24,0xfe,0x89,0xc5,
+  0xbf,0x98,0xec,0xcd,0x9e,0x2a,0xc4,0x02,0x61,0x24,0xce,0xb7,0xdf,0xe0,0xc9,0x93,
+  0x76,0x29,0xc5,0xbd,0x68,0x4f,0x9d,0x4b,0xf0,0x9f,0xc4,0xf2,0x7f,0xf0,0xa5,0x96,
+  0x92,0x1b,0x27,0x68,0xc0,0xdf,0x85,0x1d,0xb8,0x02,0x72,0x1e,0xb9,0x0e,0x5e,0x0e,
+  0x3f,0xe0,0xc3,0x2b,0x83,0xa6,0xf8,0xd7,0x80,0xb4,0x63,0x33,0x1a,0x59,0xd9,0x64,
+  0x56,0xa2,0x2d,0x11,0xec,0x08,0xa8,0xfa,0x8d,0x9b,0x88,0xa4,0xee,0xe0,0x3b,0x76,
+  0x8a,0xff,0xed,0x24,0x3f,0xc0,0x94,0x61,0x4e,0x13,0xd1,0x25,0x47,0x6f,0x28,0x8f,
+  0x05,0xc2,0xb8,0xbc,0xbd,0xa2,0xbb,0xd9,0xfa,0x4f,0xc5,0x79,0xec,0x42,0xa8,0x32,
+  0x6c,0x1b,0x16,0x2f,0x24,0xf9,0x01,0x62,0xf1,0x2f,0x5e,0x94,0xcd,0x15,0x71,0xdc,
+  0x1f,0xd2,0xa3,0xe0,0x60,0xb5,0x6c,0x34,0x8e,0xbf,0xce,0xf0,0xff,0x4c,0x3c,0x3f,
+  0x8f,0x7f,0x9d,0x55,0xdc,0xf5,0x3c,0xff,0xa7,0xf6,0xad,0x09,0xff,0xc0,0x59,0xa3,
+  0x51,0xac,0x98,0x26,0x1d,0x10,0x2a,0x7b,0xad,0xd9,0xa2,0x39,0xff,0x07,0xf1,0x8f,
+  0x47,0xfd,0x11,0x82,0x1c,0xae,0x4f,0x93,0x6d,0xce,0xb8,0xbe,0x2e,0xe4,0x1d,0x67,
+  0x6a,0x1d,0x66,0xff,0x4f,0xb9,0xc0,0xbb,0x87,0xd8,0xb5,0xfa,0x0d,0x9e,0x11,0xf5,
+  0xc9,0xe4,0xfc,0x0e,0x7e,0x4c,0x0a,0x09,0x67,0x98,0x47,0x41,0x94,0x95,0x1a,0xff,
+  0xd2,0x0c,0x6b,0xeb,0x35,0x88,0xa5,0x01,0x1b,0xf5,0xf2,0x46,0x86,0x30,0x67,0x8c,
+  0x74,0x7a,0x69,0xae,0x25,0xc9,0x0f,0xb0,0x32,0xce,0x8f,0x6d,0xd8,0x5f,0x27,0x26,
+  0xde,0xd7,0x60,0xcc,0x0e,0xa1,0xd8,0x44,0xfb,0x8b,0xcb,0x9f,0xac,0x44,0x7f,0x58,
+  0x1e,0xff,0xba,0xac,0xbd,0xe2,0xfd,0xfb,0xc1,0xaf,0x7d,0x4e,0x8d,0xfa,0x77,0x23,
+  0xfe,0xc5,0xdd,0x3e,0xc7,0x73,0x3e,0x37,0x1a,0x61,0xd8,0x8e,0xd7,0x9c,0xc9,0x35,
+  0xc7,0xbf,0x2e,0x53,0xee,0xed,0xa9,0x99,0x13,0x4a,0xf8,0x4f,0x2e,0x5b,0xdc,0x5a,
+  0xe6,0x1f,0xc4,0x39,0xda,0x01,0xa8,0xaa,0xb5,0x1d,0xbb,0x36,0xfe,0xa5,0xd9,0x39,
+  0x09,0x52,0x3e,0x33,0xfc,0x3f,0xcd,0x1e,0xee,0x11,0x2a,0x03,0xf9,0x59,0x4b,0xbe,
+  0x27,0x22,0x95,0x40,0xdb,0x6a,0x7f,0x56,0xa2,0xbe,0x9b,0xe7,0xff,0x6c,0x77,0x14,
+  0x7a,0xdb,0x15,0x52,0xab,0x1a,0x81,0x30,0x5e,0x98,0xc0,0x07,0x19,0xb9,0x44,0x62,
+  0x1b,0xc0,0x51,0x7f,0xe3,0x64,0x53,0x7f,0xd8,0x76,0x89,0xd3,0x32,0xcc,0xe0,0xf6,
+  0x8b,0x09,0x88,0xf2,0xc1,0x8d,0x1b,0x49,0xb1,0xd7,0x20,0x1e,0xdf,0x64,0xe6,0x07,
+  0xe0,0xf8,0x27,0xea,0xfe,0x27,0x6b,0x9e,0xbc,0x9c,0x25,0x80,0xae,0x81,0x70,0xda,
+  0x6b,0x66,0x28,0x6f,0x45,0x6f,0xd0,0x6c,0xed,0xf2,0x35,0xf1,0xaf,0x50,0x8f,0x66,
+  0x7b,0x2a,0xe7,0xd9,0xc4,0x7c,0xe5,0xac,0x32,0x83,0xbb,0x7d,0x5e,0xa7,0xe3,0x21,
+  0xbc,0xf2,0x64,0xcd,0xb9,0x94,0xf8,0xd7,0x28,0xb8,0xa9,0x8d,0x35,0xe5,0xab,0x27,
+  0x12,0x7c,0x5c,0xb1,0x44,0xe8,0xfc,0xba,0x13,0x9c,0x1f,0xd8,0x9f,0xd2,0x1f,0xd6,
+  0x01,0xfb,0xeb,0x4a,0x39,0x1b,0x64,0xb9,0x12,0xe7,0x47,0x1a,0x86,0x3d,0x6a,0x07,
+  0x5b,0xf4,0x91,0x65,0xbe,0xd4,0x1a,0x2a,0xe5,0x44,0x01,0x26,0x7e,0x6c,0x40,0xfc,
+  0x53,0xa7,0x9e,0x97,0x6f,0x25,0x56,0xe9,0x71,0xb0,0x4e,0xb4,0x45,0x03,0xdd,0xa2,
+  0xf8,0x25,0x7f,0x53,0xa8,0x70,0x59,0x46,0x7b,0x76,0x12,0xff,0xf0,0xf8,0x57,0x37,
+  0x3f,0xad,0xa3,0x64,0x1a,0x18,0xfd,0x61,0x1b,0xd2,0x4f,0xe2,0x7a,0xe6,0xeb,0x37,
+  0x7a,0x49,0xae,0xf5,0x31,0xf6,0x83,0x70,0xc6,0x23,0xe9,0xc9,0xfe,0xb0,0x3c,0xfe,
+  0xf5,0x05,0x9b,0x8d,0xb0,0x27,0xa7,0x12,0xfe,0xc8,0x78,0x5b,0xd8,0xf4,0x77,0x8d,
+  0xb0,0x57,0x56,0x44,0x2c,0x83,0xf7,0x5a,0x4b,0x7d,0xc5,0x29,0xfc,0x00,0x46,0xfc,
+  0x6b,0x8f,0xb6,0xc4,0x75,0xcb,0x18,0x24,0x68,0x7f,0xc6,0x79,0xfc,0x0b,0xe5,0x8f,
+  0x32,0xae,0xce,0x65,0xa8,0xca,0x4d,0xfc,0x90,0xd2,0x7e,0xed,0x12,0xde,0xf6,0xee,
+  0xb1,0x1a,0xce,0x0f,0x59,0x15,0xe3,0xb7,0xb9,0xc8,0x4a,0x63,0x8e,0xa0,0x2c,0x69,
+  0x81,0xcf,0x7a,0xc2,0xd4,0x1f,0xf6,0x05,0x94,0x3f,0x2f,0x4d,0x76,0xfa,0xe9,0x32,
+  0x32,0xc0,0xd6,0xa0,0x59,0xc4,0x61,0x9b,0xb6,0x6b,0x67,0x3e,0x0f,0x63,0x1d,0x87,
+  0x35,0xae,0xe2,0x8c,0xcc,0x7b,0x88,0xb9,0x3f,0xec,0x66,0xe5,0x25,0x98,0xa5,0x5b,
+  0x1a,0xfc,0xbc,0x70,0xa3,0x38,0x12,0xe7,0x33,0xc9,0xef,0x95,0x7d,0xfe,0x93,0xf0,
+  0xec,0xe4,0x59,0x9e,0x3a,0x73,0xfc,0xab,0x50,0x5a,0xab,0x74,0xdb,0x9d,0x90,0x37,
+  0x87,0x1c,0x30,0x0c,0x31,0x83,0x6f,0x61,0x07,0xef,0xcf,0x58,0x41,0x86,0x1f,0x6a,
+  0xd2,0x4a,0x42,0x19,0x9d,0x33,0x68,0x32,0x1f,0x7b,0xca,0x88,0xc2,0xd3,0x2a,0xb2,
+  0x42,0xe2,0xac,0xb8,0xff,0x9c,0x8c,0xc4,0x18,0xa1,0xdb,0xc5,0xf7,0xc9,0x21,0xce,
+  0x48,0xec,0x97,0x4d,0xfd,0x41,0x84,0x6d,0xf0,0x99,0x82,0xd3,0x9e,0x15,0xde,0x30,
+  0xad,0x0f,0xea,0xbb,0xf5,0xc1,0x26,0x83,0xa8,0x3f,0x68,0xeb,0x30,0xf1,0x43,0xf2,
+  0xf8,0xd7,0x5f,0x60,0xee,0xb3,0x08,0x7b,0x3e,0x55,0x8f,0xc2,0x2d,0xbd,0x69,0x3c,
+  0x1f,0xe6,0x62,0xc0,0x90,0xe7,0x51,0x44,0x44,0x68,0x71,0x30,0xb1,0x2e,0x91,0xff,
+  0xcc,0xe3,0x5f,0xfb,0x58,0x87,0x82,0xfa,0xfd,0x23,0xc6,0xfb,0x7d,0x2c,0x0a,0xdb,
+  0x47,0x60,0x77,0x10,0x15,0xd9,0x3a,0xb4,0xb0,0x02,0x3c,0xd1,0x25,0x40,0x1c,0x29,
+  0xf8,0x87,0xf3,0xf3,0x67,0x04,0x48,0x3d,0xe3,0xfd,0xb0,0x32,0xc2,0x64,0x1b,0x3f,
+  0x2f,0xbd,0x08,0x0c,0x3e,0xa2,0x01,0x47,0xd1,0x32,0x1a,0xf0,0x9b,0xf0,0x4f,0xae,
+  0x15,0xc2,0x6c,0x06,0x50,0xd5,0xde,0x0b,0x5b,0x61,0x85,0xe1,0xff,0x49,0xdb,0x2e,
+  0x58,0x79,0x86,0x8c,0x2e,0x31,0xc1,0xa9,0x05,0xc0,0xe2,0x37,0xf5,0x87,0x5d,0x61,
+  0x34,0x81,0xcd,0x44,0xb3,0x0b,0xd7,0x67,0xde,0xc9,0xbb,0x38,0x5f,0xd6,0xb8,0x3a,
+  0x4d,0x8f,0x3b,0xa2,0x2b,0xb9,0x23,0xc8,0x14,0xff,0x9a,0xc2,0xbb,0x9f,0xcc,0xe7,
+  0x4d,0x0a,0xc6,0xd8,0x55,0x52,0x39,0x60,0x1b,0x9d,0x84,0x57,0x62,0xfa,0x6b,0xd4,
+  0x70,0x04,0xad,0xd7,0xc5,0x7a,0x53,0xfe,0x33,0xe7,0x87,0x2c,0x8e,0x5a,0xf5,0x49,
+  0x2e,0x58,0xab,0xcc,0xd7,0xad,0x1f,0x8a,0x15,0xbe,0xa3,0x50,0x15,0x58,0x1b,0x10,
+  0xe7,0x04,0x0e,0xb3,0x02,0xe0,0xfc,0x90,0xe6,0xf8,0x17,0xec,0xe5,0xfd,0xeb,0x03,
+  0xbc,0x3f,0xa3,0x7a,0xcb,0xc9,0x4c,0x95,0x2c,0x80,0xb6,0xc7,0x4b,0x3a,0x1d,0x2a,
+  0x29,0xd2,0x9e,0xb7,0xdb,0x97,0x5a,0x7a,0xfe,0x15,0xff,0x0f,0x85,0x74,0x89,0x30,
+  0x70,0xbc,0x6a,0xe9,0xb0,0x5b,0x59,0x93,0xe4,0x64,0x14,0x6e,0xb0,0x0a,0x3b,0xa8,
+  0x7a,0x8f,0x83,0xe7,0xff,0x98,0xfc,0x3f,0xb9,0x08,0x1b,0xfa,0x21,0x7c,0xc7,0x24,
+  0xf0,0x43,0x91,0x3e,0xb9,0xab,0x75,0x71,0x76,0x9b,0x54,0x12,0xa2,0x15,0xf6,0x99,
+  0xda,0x5e,0x62,0xd7,0x2c,0xe1,0x6b,0xfa,0x83,0x70,0xb5,0xeb,0x0c,0xdb,0x54,0x8a,
+  0xeb,0xa3,0x67,0x39,0x10,0x9f,0x2c,0x82,0x69,0x5d,0x8b,0xb7,0xd5,0x14,0xc3,0x59,
+  0xda,0x1d,0xa2,0xae,0xd4,0xf8,0x17,0x35,0xc2,0x3a,0x83,0x08,0xea,0x0c,0x47,0x47,
+  0x34,0x87,0x6b,0x7c,0x9e,0xef,0x9a,0x73,0x02,0xfe,0xb2,0xb5,0xaa,0x73,0x49,0x4a,
+  0x7f,0x58,0x05,0xd1,0x0e,0x9e,0x3e,0x29,0x5f,0x7e,0xa0,0x79,0xac,0x76,0x81,0x9e,
+  0xb9,0xf3,0x6f,0x9d,0xd2,0xc7,0x90,0x1d,0xb4,0x6e,0x13,0x9d,0xca,0xa1,0xba,0x0a,
+  0xfd,0xda,0xfe,0xb0,0x1c,0x0f,0x9f,0xa1,0xe1,0x9a,0x12,0x6e,0x7f,0xf5,0x66,0x71,
+  0x47,0xd0,0x7a,0xc4,0xff,0x75,0x21,0x52,0xd4,0xd7,0xa6,0xcf,0xeb,0xb3,0xa4,0xf4,
+  0x87,0x35,0xec,0xaf,0x12,0xdd,0x42,0xaf,0x93,0x21,0xcc,0x1d,0x41,0x2a,0xe2,0x9f,
+  0x26,0xc9,0x51,0x47,0x01,0xd5,0x56,0xf6,0x31,0x27,0xd0,0xd4,0xfe,0xb0,0xd3,0x0c,
+  0x9a,0xe8,0xa2,0xba,0xec,0x69,0xd2,0xce,0x4e,0xc4,0x03,0x3f,0xc8,0x9e,0xb6,0x7a,
+  0x0d,0x9b,0x69,0xa7,0x0f,0x90,0x79,0xda,0x2f,0x43,0x33,0x7d,0x96,0x95,0x29,0xf9,
+  0x3f,0x59,0x08,0x3b,0xf1,0x7c,0x81,0x48,0x43,0x67,0xa3,0x15,0xfa,0xaf,0x67,0x5a,
+  0x9c,0xf0,0x6a,0x63,0x79,0xbf,0x53,0x96,0xad,0xf0,0xfb,0x70,0xa5,0xd7,0xea,0x32,
+  0xf3,0x63,0x67,0xc6,0xfc,0x63,0x3f,0x68,0x10,0x0c,0xc3,0xa1,0x2f,0x2b,0x2a,0x5e,
+  0x0a,0xff,0x11,0xbe,0xd6,0x6c,0xd3,0x2d,0x27,0x94,0xbf,0xa0,0x3e,0xca,0xbc,0xb6,
+  0x3f,0x2c,0x5f,0xff,0x92,0x70,0x8e,0x8a,0xfb,0xb3,0xea,0x84,0xd4,0x25,0xae,0x50,
+  0x3f,0x36,0xdc,0x92,0xb2,0x53,0x3a,0x40,0x0d,0xc6,0xce,0x8f,0xcc,0xf1,0x2f,0x23,
+  0x7f,0x80,0x7a,0x49,0xb3,0x84,0xf2,0xe4,0x20,0xd5,0x2c,0x53,0xfd,0x6b,0x7c,0xd3,
+  0x41,0xf6,0x71,0x06,0x7e,0x32,0x2b,0xb5,0xfe,0x4b,0x8f,0xe1,0x9f,0xa8,0xc5,0x31,
+  0x78,0x83,0xb2,0x8a,0x39,0xa3,0x74,0xd8,0x3e,0x8d,0xad,0x61,0xc5,0xaa,0x5c,0x67,
+  0xff,0x2e,0x59,0x13,0x28,0xe6,0x19,0xd1,0xa3,0x29,0xfe,0x1f,0xdc,0x6f,0xb7,0xd7,
+  0xcd,0x59,0x58,0x42,0x9a,0x98,0x53,0xaf,0xc7,0xf5,0x94,0x9a,0xa0,0xb0,0x03,0xcf,
+  0xd7,0x61,0x78,0x91,0x39,0xef,0xa5,0xa9,0xfd,0x61,0xbb,0x38,0xec,0x09,0x65,0x45,
+  0x73,0xe6,0x91,0x23,0x37,0xa0,0x36,0x3f,0x23,0x3a,0xe0,0x23,0xa8,0xea,0xb1,0x0d,
+  0x6f,0xfd,0x71,0xe1,0xc1,0x37,0xab,0x76,0x5a,0x53,0xf2,0x7f,0x12,0xfe,0x9f,0xa6,
+  0x28,0xc2,0xd2,0x4a,0x81,0x0f,0x8c,0x2b,0x32,0x6b,0xda,0xe2,0x30,0x42,0x45,0x5f,
+  0xe9,0x0f,0xcb,0xab,0xbd,0x26,0x1b,0x65,0x5f,0xf3,0xb4,0x69,0xc1,0x9c,0x7e,0x89,
+  0x37,0x0a,0x59,0xdf,0xae,0x49,0x70,0xa8,0xd3,0x55,0xf7,0xd5,0xfe,0x20,0x1c,0x84,
+  0xb4,0x5b,0xa6,0xc3,0x01,0x81,0x13,0x35,0x93,0x21,0xa9,0xc5,0xa0,0x79,0xb4,0x7c,
+  0x1d,0xde,0x62,0x76,0x5f,0x66,0xf0,0xda,0xfe,0x20,0xa8,0x9d,0x39,0x3f,0x36,0x69,
+  0xe1,0x6e,0x64,0x4e,0x23,0xd9,0xc2,0x23,0x68,0x93,0x5b,0x3b,0x7d,0x2d,0x82,0x41,
+  0xec,0x7c,0x0d,0x3f,0x24,0xac,0xe0,0xd9,0xce,0x99,0x46,0xb6,0x33,0xcd,0x25,0xaf,
+  0x11,0x41,0xe0,0xc0,0x20,0xbd,0x19,0x36,0xe0,0x95,0x7c,0xe5,0x2b,0xfd,0x41,0x2a,
+  0xc0,0x3a,0x11,0xed,0x72,0xf0,0x7c,0xef,0x00,0x7f,0x4d,0xc0,0x2b,0x07,0x81,0x07,
+  0x62,0xae,0xe9,0x0f,0xc2,0xdb,0x82,0xcc,0x3a,0x2e,0x5e,0x86,0x4f,0x6a,0xcb,0xbc,
+  0x93,0xbc,0x05,0x1f,0x28,0x3f,0xe6,0x6d,0x61,0x07,0x6b,0xfe,0x86,0x8e,0x93,0x2a,
+  0xaf,0xed,0xda,0xfe,0x20,0xe3,0xb0,0xa0,0x36,0x6b,0x10,0xad,0xb3,0x03,0xb4,0x68,
+  0xe1,0x02,0xee,0x18,0x39,0x8c,0x62,0x39,0x3d,0x98,0x33,0x87,0xbd,0x06,0x55,0x8b,
+  0xe9,0xb5,0xfc,0xd8,0x86,0xff,0xa7,0x99,0xdc,0x4f,0x02,0x0e,0x7b,0x1e,0x0d,0x11,
+  0xde,0x2f,0xa3,0x84,0xa7,0x4d,0x86,0x68,0x97,0x5a,0xb2,0xb6,0x28,0x95,0x1f,0xbb,
+  0xdf,0x8a,0xef,0xab,0x59,0xf0,0x35,0xd5,0x46,0xa8,0xf7,0xa0,0x5a,0x37,0x3a,0x86,
+  0xdc,0xbe,0x08,0xf5,0xbb,0x67,0x43,0xd7,0x8a,0x48,0x06,0xbe,0x6f,0x9a,0xc9,0xff,
+  0xa3,0xe0,0xfa,0xfb,0xe8,0xe6,0xf4,0xd7,0x85,0x16,0x2f,0xd1,0x2c,0xc1,0xf4,0x21,
+  0xe9,0x7a,0x09,0x81,0xd0,0xe4,0x8e,0x67,0xe1,0x79,0x56,0x52,0x27,0x07,0xd3,0x5f,
+  0xff,0xaa,0xff,0x87,0xc3,0x98,0x03,0xd5,0xf3,0xb4,0xac,0xcd,0x1c,0xb8,0x8a,0x95,
+  0xda,0xb4,0xcd,0xe2,0x8c,0x99,0x88,0x6f,0xb5,0xe2,0xe0,0xb7,0x86,0xbf,0xe2,0xff,
+  0xe1,0xf9,0x4e,0x12,0xa7,0x85,0xcc,0x7c,0xb2,0x60,0x88,0x7c,0x08,0x3f,0xf3,0xae,
+  0xef,0xe1,0x8d,0x62,0xa9,0x71,0xab,0xaf,0xfa,0x7f,0x50,0xfe,0x6f,0x81,0x88,0x86,
+  0x86,0x5e,0x73,0x8d,0x1e,0x8b,0x48,0x36,0xe7,0xa8,0x6a,0xbc,0xfe,0x2e,0x25,0xff,
+  0x47,0x41,0xb1,0xb3,0x9a,0x76,0x90,0x0b,0xd0,0x0a,0x2f,0xf0,0xb4,0x67,0xc4,0x3f,
+  0x85,0xff,0xc8,0xfb,0x83,0x5c,0x4f,0xd6,0xe9,0x76,0x46,0xa3,0x62,0xeb,0xb5,0xfe,
+  0x9f,0x68,0x46,0x1e,0xf7,0x97,0x0a,0xcb,0x7b,0x05,0x57,0xfa,0x40,0xee,0x8e,0x26,
+  0xc3,0x70,0x10,0xa0,0xa9,0x77,0x06,0xf7,0x97,0xa6,0xf4,0x87,0x35,0xda,0x82,0x04,
+  0x1a,0xd2,0x0f,0xc0,0x13,0xea,0x03,0x91,0x8c,0x1f,0xd9,0x4f,0xf2,0xfe,0x3e,0x9a,
+  0xfc,0x48,0x76,0x5e,0xce,0x1a,0x7d,0x3a,0xf7,0xff,0x74,0x99,0xfd,0x3f,0xb0,0xab,
+  0x71,0x41,0xf4,0xae,0x95,0xe2,0xd3,0xf0,0x6a,0x68,0xee,0x98,0xf5,0xd1,0x57,0xdf,
+  0x0b,0x7d,0x89,0x16,0xcd,0xfa,0x95,0x6d,0x37,0x40,0x3f,0xdb,0x15,0x75,0xd6,0x5f,
+  0xc3,0x8f,0xbd,0x97,0x9f,0x2f,0x5e,0xc6,0xf2,0xb1,0xd7,0x3d,0x68,0xeb,0xce,0x19,
+  0x11,0xf6,0x4a,0x59,0xc2,0x92,0x67,0x49,0x84,0xe7,0x9b,0x71,0x8f,0x90,0x99,0x1f,
+  0x3b,0x16,0xbf,0xc8,0x1a,0xcb,0xf9,0x27,0x58,0xa2,0xff,0x68,0xf4,0xe9,0x71,0xf1,
+  0x8a,0xf6,0xd8,0x86,0xd2,0xe8,0x63,0x63,0x19,0xd9,0x10,0xf1,0x97,0x46,0x9d,0xc3,
+  0x66,0x7e,0x6c,0x83,0x9f,0xb6,0x18,0x78,0x7f,0x6a,0xd6,0xa6,0xde,0x1a,0x91,0x67,
+  0xfb,0x2f,0x69,0x8d,0xca,0x4c,0xaf,0xec,0xf1,0xe4,0x41,0x20,0x94,0x5f,0x83,0xcf,
+  0x6f,0xe2,0xc7,0x56,0x62,0xf2,0xca,0x32,0x87,0x4c,0x91,0xd6,0x08,0x31,0x37,0x97,
+  0xf4,0x0b,0xc8,0xf7,0xa3,0xbc,0xba,0x4f,0x5b,0xa3,0x1a,0xfe,0x2e,0x33,0x3f,0xb6,
+  0xe1,0xcf,0x57,0xe9,0x6d,0x16,0x87,0xd0,0x24,0x15,0x22,0x7e,0x30,0x12,0x5d,0x1c,
+  0xd0,0xa6,0x5a,0xee,0xa4,0x4d,0x7e,0xb5,0x01,0x15,0xa5,0x99,0x1f,0x1b,0xf1,0x9e,
+  0x54,0x19,0x4d,0x47,0xb3,0x9a,0x1c,0x85,0x02,0x7d,0x1a,0xc7,0x27,0x4f,0x12,0x7b,
+  0xa7,0x2d,0xfc,0x8d,0x3a,0xa2,0x0b,0xdd,0x83,0x8b,0x43,0xa9,0xfd,0x61,0xb9,0xbc,
+  0xdd,0x34,0x8b,0xf7,0x4b,0xbd,0x88,0x40,0xe8,0x66,0x9e,0x1f,0x8e,0x86,0x86,0xd7,
+  0xf6,0x6e,0xcd,0xb3,0x8e,0x8b,0xf7,0x54,0x44,0x78,0xa8,0x3a,0x25,0xfe,0xc5,0xe5,
+  0xb9,0x75,0x6c,0xd2,0x30,0x7b,0x03,0xef,0xbf,0x7e,0x54,0xae,0x80,0x5e,0x98,0x8d,
+  0xdf,0x3c,0xa7,0x1c,0x0e,0xb3,0x6c,0xdd,0x1a,0x4d,0xed,0x0f,0xc2,0xbb,0x99,0x70,
+  0x5a,0xec,0x28,0x69,0x8b,0xc5,0xb3,0x9c,0x28,0x4f,0xca,0x5c,0x01,0xe7,0xc6,0x99,
+  0xac,0x15,0x0d,0x2b,0x7e,0xe2,0x52,0xf0,0x0f,0xc2,0xa4,0x65,0x96,0xed,0xd9,0x43,
+  0x46,0x3f,0xd0,0x36,0xee,0xd8,0x79,0x92,0x33,0x1c,0xfa,0x89,0x63,0x63,0xe0,0x9b,
+  0x45,0x11,0x3e,0xdf,0xec,0xff,0xe1,0xeb,0x03,0x16,0x17,0x9a,0x21,0x4d,0x31,0x7f,
+  0x88,0x55,0x68,0x84,0x42,0x2d,0xc0,0x50,0x09,0xb5,0x51,0x87,0x8e,0xeb,0x63,0xe2,
+  0xc7,0x4e,0x5b,0xa1,0x19,0x6d,0x70,0x79,0x3d,0xd1,0x51,0xef,0xcf,0x75,0xdb,0xe7,
+  0x62,0x05,0xbc,0x75,0x0f,0x6e,0x7b,0x90,0x1d,0xf4,0x80,0x30,0x4f,0x77,0x86,0x4c,
+  0xfc,0xd8,0xa1,0x29,0x97,0xd8,0x55,0x58,0x00,0xc5,0xa3,0x9c,0x0d,0x5b,0xdd,0xc5,
+  0xdb,0x5e,0x70,0x44,0x84,0xb0,0xa7,0xaf,0x69,0x8c,0x53,0x01,0x6b,0x68,0x8f,0xa7,
+  0xc6,0xbf,0x3e,0xe7,0xfc,0xa2,0x67,0xc5,0x13,0xec,0xaa,0x56,0x5a,0x6b,0x1d,0x13,
+  0x1f,0x81,0xf7,0x54,0x1e,0x11,0xbb,0xc5,0xd5,0x3f,0xe0,0xaf,0x92,0x96,0xf4,0xa5,
+  0xe6,0xff,0xc0,0xee,0xa2,0x82,0x41,0xfa,0xdf,0xc8,0x27,0xec,0x57,0x12,0x4a,0xd7,
+  0x1e,0x52,0x08,0xeb,0x83,0x68,0x56,0x77,0x93,0xe9,0x3a,0xe2,0xc3,0xa5,0x72,0x8b,
+  0x3d,0x15,0xff,0xec,0x56,0xd5,0x7e,0x54,0x3a,0x75,0xbe,0xbd,0x21,0xf5,0x4e,0x8b,
+  0x2b,0xbb,0x56,0x79,0x3c,0xe6,0x01,0x03,0xa9,0xb1,0x79,0xc5,0xf5,0x32,0xa4,0x93,
+  0xc9,0x29,0xf9,0x3f,0x31,0x36,0xce,0x0f,0x78,0xa2,0x78,0x5d,0x11,0x2f,0x6c,0x6f,
+  0x8b,0x39,0x82,0x8a,0xf2,0x03,0xea,0x83,0xaa,0xdc,0x93,0x6e,0xc2,0x3f,0x53,0x10,
+  0xfd,0xea,0xb3,0xf5,0xc5,0xa3,0x39,0x0f,0xc3,0x15,0x56,0x5a,0x97,0x15,0x16,0xef,
+  0x30,0x1a,0x95,0xe2,0x09,0x2a,0x10,0x0e,0xb2,0xca,0xd9,0x4b,0x5a,0x6b,0x52,0xf3,
+  0x7f,0x2e,0x57,0x57,0xe9,0xb3,0x46,0xe1,0x61,0xed,0x42,0xb0,0x2a,0x8a,0xda,0xfc,
+  0x0b,0xaf,0x81,0x88,0xc6,0x5f,0xed,0x4f,0xbf,0xc4,0x2a,0xfd,0xeb,0x35,0x39,0x35,
+  0xfe,0x35,0xe6,0x75,0xf7,0x2d,0x0e,0xcb,0xd3,0x21,0xc2,0xd0,0x2c,0x0d,0x8b,0x43,
+  0x9a,0xd1,0x28,0x96,0xa1,0x46,0xc3,0x81,0xe2,0xdc,0x74,0x0d,0xfe,0xd9,0xae,0x17,
+  0xe8,0xf5,0x9f,0xf7,0x15,0xc2,0x20,0x18,0x69,0x4e,0x67,0xe0,0xbd,0x58,0x47,0xce,
+  0xaf,0x73,0x6a,0x3b,0x07,0x6a,0xa8,0x6b,0xf0,0x4f,0x44,0x1d,0xa5,0xe5,0x68,0x94,
+  0x89,0xa0,0x72,0xf6,0x81,0xd7,0xfc,0xbc,0x3f,0x51,0xc6,0xad,0x24,0x43,0x0d,0x82,
+  0x93,0x05,0xae,0xc1,0x3f,0xf0,0x3b,0x96,0x3f,0x44,0x57,0x7a,0x6e,0x24,0x4f,0x34,
+  0x7f,0x2f,0x6a,0x59,0xe9,0x7f,0x57,0x7b,0x62,0x8b,0xd1,0x38,0x35,0xdb,0xe8,0xa0,
+  0x4a,0x17,0x92,0xd4,0xfe,0x20,0x67,0xc1,0xdd,0x47,0xdd,0xa2,0x35,0xf4,0xaa,0x1a,
+  0xee,0xb7,0xb9,0xc4,0x21,0xcf,0xab,0x6c,0xaa,0x9e,0xd9,0x2d,0xd2,0x65,0x6f,0x4e,
+  0xaa,0xf0,0x2e,0x2e,0x4f,0xe9,0x0f,0xb2,0x0f,0x7e,0x07,0x25,0x7d,0x46,0x74,0xef,
+  0x2a,0x54,0xf4,0xde,0x64,0xf0,0x43,0x5a,0x16,0xe8,0x25,0xa3,0xf2,0x98,0xc6,0xf1,
+  0x8f,0xed,0xab,0xf8,0xc7,0x7d,0x2c,0xeb,0x65,0x34,0x72,0x0f,0x05,0x8d,0xf8,0x35,
+  0x4f,0xd4,0x7f,0x54,0xb7,0xf5,0xd4,0xcc,0x91,0xf6,0x04,0xd0,0xb4,0xd7,0xaf,0xc1,
+  0x3f,0x2f,0xc1,0x16,0xdd,0xe1,0x6e,0xa5,0xbc,0xdf,0x10,0x2f,0xac,0x38,0x49,0x9a,
+  0x1c,0x5c,0xb0,0x88,0x86,0x3f,0x59,0xa7,0xda,0x35,0xf8,0xe7,0x25,0x56,0x38,0xcc,
+  0xe3,0x7d,0xc2,0xe3,0xb1,0x7c,0xa7,0xd7,0x61,0x4d,0x68,0x66,0x54,0x1e,0x26,0xd7,
+  0x09,0xff,0xbc,0x41,0xbd,0x3f,0xb0,0x34,0x15,0xff,0x48,0xbb,0xc1,0xe8,0x47,0x63,
+  0x53,0x77,0x44,0x0a,0x43,0xb2,0x2b,0x7b,0xc4,0xe0,0x6b,0x95,0x6f,0x23,0xb7,0xa7,
+  0xed,0x60,0x1d,0x3e,0x7a,0xfd,0x35,0xf8,0xe7,0x8a,0x56,0xd6,0x88,0x20,0x67,0x3e,
+  0x79,0x57,0x7f,0x29,0x6c,0xf8,0x7f,0x0e,0x42,0x39,0xb3,0x7d,0x22,0x96,0xb3,0xa7,
+  0x58,0xe9,0x46,0xe7,0xd0,0xb5,0xf8,0x47,0x2a,0x47,0xed,0x23,0x9e,0xd2,0x86,0x95,
+  0x79,0xe9,0x71,0x7f,0x48,0xac,0x3f,0x48,0xe1,0x98,0xb7,0x32,0x7b,0x3d,0x6b,0xba,
+  0x06,0xff,0x74,0x95,0xf9,0xac,0x9b,0x6f,0x94,0x08,0x2f,0x7b,0x77,0x6e,0x10,0x3f,
+  0x40,0xf9,0x63,0x94,0xbd,0x7f,0xc0,0xed,0x7d,0x9f,0x35,0x08,0xd7,0xe2,0x1f,0xbb,
+  0xcf,0xb1,0x99,0x4c,0x87,0xc3,0x46,0x7f,0x58,0x3c,0x08,0x6f,0x01,0xd1,0xe8,0x3f,
+  0x93,0x0f,0xd8,0xde,0x42,0x4e,0x1d,0x39,0x29,0x94,0x82,0x7f,0xf6,0xd2,0x33,0xb5,
+  0x08,0x63,0xa6,0x57,0xb7,0x4c,0x7e,0xb0,0xda,0x68,0x63,0x11,0xef,0x67,0x31,0x24,
+  0x3c,0x0f,0x25,0xf7,0xd2,0xd4,0xfe,0xb0,0xdc,0xff,0xe3,0xf3,0x3a,0x0c,0x6f,0x8f,
+  0x86,0x77,0xe3,0x8e,0xa0,0xc9,0x08,0x9c,0xf0,0xca,0x6b,0x46,0x68,0xcc,0xa1,0x5c,
+  0x97,0xd2,0x1f,0x16,0x46,0xa1,0x8c,0xb7,0x05,0x89,0x45,0xdb,0xb9,0x23,0x48,0x8a,
+  0x40,0x87,0x31,0x10,0x62,0x1d,0x63,0x85,0x75,0x29,0xf8,0xe7,0x32,0x4c,0xf3,0x2e,
+  0xd9,0x24,0x5e,0xce,0xfe,0x84,0x57,0x7b,0x05,0x0b,0x3e,0xe7,0x34,0xe0,0xda,0x7a,
+  0x6f,0xc1,0xe7,0xc2,0x67,0x60,0xf4,0x87,0x7d,0x36,0x05,0xff,0x5c,0x86,0x1d,0xb5,
+  0xb6,0x63,0x72,0x6e,0xe8,0xb0,0xcb,0xed,0xb5,0x0e,0xd6,0x9c,0xd7,0x0f,0xa8,0xa5,
+  0x9a,0xed,0x4d,0x4e,0x94,0x8d,0xf8,0xc7,0x7a,0x4d,0x7f,0x34,0xe8,0x91,0xed,0x92,
+  0xec,0xf7,0xab,0x78,0x32,0xec,0x37,0x51,0x46,0xde,0xf7,0x07,0x34,0x83,0x28,0x52,
+  0x0d,0xe1,0xf9,0xda,0x4c,0x9f,0xf9,0x4a,0xfe,0x8f,0xaa,0xc9,0x39,0x44,0x0a,0x71,
+  0xf6,0x5d,0xaa,0x64,0xf3,0x40,0x98,0xd1,0x21,0xae,0xf9,0x20,0xf7,0x80,0xd5,0x2b,
+  0x77,0x98,0xe2,0x5f,0x93,0x3b,0x71,0x7d,0x8c,0xe8,0x61,0x21,0x6e,0xa4,0x90,0x56,
+  0x1e,0xcf,0xa7,0xd2,0xe4,0x97,0x16,0x16,0xc2,0xf3,0xa4,0xa4,0x0e,0x52,0xfa,0xa3,
+  0xf1,0xfc,0x67,0xaf,0x9b,0x17,0xe9,0xcf,0x90,0xc6,0xa5,0x52,0xcd,0x19,0xac,0x89,
+  0xf5,0x07,0xb9,0x39,0x57,0x7c,0x4e,0x3d,0xa0,0x55,0x7a,0x6b,0x37,0xa7,0xc6,0xbf,
+  0xa4,0xf1,0x00,0xc7,0x3f,0x39,0x43,0xfe,0x5e,0xdd,0x00,0x42,0xfd,0x70,0x36,0x9e,
+  0xff,0xc3,0xde,0x82,0x8a,0x65,0xb6,0xec,0x54,0xfc,0x23,0x8c,0x81,0x5b,0xba,0x8f,
+  0xd9,0xf2,0xb5,0x48,0x0c,0x6d,0x72,0xb3,0xf7,0xe1,0x58,0xc7,0xba,0x88,0x54,0xa9,
+  0x58,0x9b,0xe5,0xd4,0xf8,0xd7,0x7e,0xb6,0x95,0x39,0x4e,0xd5,0xfc,0x18,0xbe,0x03,
+  0x76,0x4e,0xf3,0x3e,0x06,0x6f,0x83,0x9b,0xc9,0x1f,0x90,0xf9,0x5a,0xeb,0x37,0x67,
+  0xa1,0x21,0x56,0x93,0xda,0x1f,0x6d,0x07,0xf3,0x45,0xe9,0x4e,0xb2,0xc2,0xd1,0xa4,
+  0xa8,0xfa,0xf5,0x3c,0xed,0x19,0xed,0x05,0x5d,0x9e,0x6a,0xf9,0x3a,0x6d,0xd2,0x9c,
+  0x0d,0x16,0x57,0x2a,0xfe,0x11,0x76,0xd1,0xfc,0x28,0x5d,0x4e,0x96,0xc2,0xe3,0xf0,
+  0x3d,0x5e,0x0f,0xc5,0xdb,0x84,0xe1,0xf9,0xbd,0x97,0x58,0xf3,0xd7,0xd0,0xe2,0x37,
+  0x71,0x7e,0x4a,0x7f,0x34,0x78,0x85,0x95,0xfa,0xea,0x4e,0x58,0xbe,0xcb,0xfb,0x97,
+  0x8d,0x66,0x2e,0x15,0xaf,0xc0,0xab,0xec,0x99,0xa8,0x6d,0x4c,0xbe,0x0e,0xde,0x08,
+  0x54,0xf9,0x4a,0x56,0x8a,0x1f,0x25,0xfd,0x3f,0x99,0xdb,0x0c,0x7b,0xf3,0x66,0x96,
+  0x33,0x8c,0x40,0x71,0x9f,0x3e,0xcb,0x20,0x5a,0x27,0x31,0xa2,0x5a,0xc2,0x1b,0x5d,
+  0x3d,0x16,0x4e,0xe9,0x8f,0x76,0x05,0x78,0xd9,0xfb,0x63,0x63,0xa2,0x5b,0x3b,0x1c,
+  0x2e,0x1d,0xb2,0x9e,0xf8,0xd6,0x05,0xe5,0x28,0xab,0x1a,0xb2,0xdd,0x20,0xbe,0xcc,
+  0x3b,0x3e,0xa8,0x37,0xaf,0x14,0xc0,0x14,0xff,0x32,0xf8,0xae,0x23,0x8e,0x65,0x35,
+  0x6e,0xed,0x25,0xe5,0xd6,0x61,0x7c,0xfe,0x31,0xd2,0xc4,0xfb,0xbb,0xfd,0x1d,0x99,
+  0x03,0xcd,0x50,0x2c,0xc9,0xee,0xd6,0xd4,0xfc,0x9f,0x97,0x94,0x7c,0xad,0xce,0x5b,
+  0xa6,0x84,0x7e,0xa1,0xde,0x1f,0x45,0xc3,0xed,0xa4,0x41,0x0c,0xbe,0x68,0x90,0x6c,
+  0x32,0xa0,0x14,0x4a,0x30,0x73,0x7f,0xd8,0x01,0xfc,0x48,0x2a,0xda,0xfb,0xa4,0x1a,
+  0x0f,0x72,0xe1,0x71,0x3c,0x5f,0x67,0x0c,0x47,0x90,0x5c,0x48,0x8a,0x60,0x87,0x52,
+  0xd2,0x2c,0x97,0x5f,0x67,0xee,0x0f,0xbb,0x0d,0x2e,0x68,0x3c,0x9b,0x54,0x76,0xa2,
+  0x5a,0x71,0x8d,0xa2,0xb5,0xf8,0x69,0xcc,0x11,0x94,0x26,0x76,0xbc,0x7a,0x91,0x03,
+  0x9b,0xdf,0x89,0x45,0x29,0xf8,0xe7,0x82,0x5e,0x19,0xcc,0xea,0x14,0xbb,0xb8,0xff,
+  0xa7,0xd7,0x16,0x9e,0x14,0xe7,0x07,0xe0,0x1e,0x12,0xd9,0x52,0x19,0xf9,0x4a,0x7f,
+  0x90,0x2b,0x74,0x87,0xb6,0x62,0xa9,0x5c,0xee,0x3f,0x10,0x74,0xf7,0x65,0x5e,0xc8,
+  0xb9,0x44,0xde,0x80,0x1f,0xf1,0xc6,0xe8,0x2e,0x18,0x68,0xac,0xaa,0x5e,0x3b,0x7a,
+  0x0d,0xfe,0xd9,0xf7,0x50,0xfe,0x36,0xfa,0xa6,0x5f,0xf1,0x3f,0xc6,0xe6,0xea,0x68,
+  0x7d,0x9c,0x65,0x6d,0x70,0xba,0xb7,0x2d,0x40,0xb6,0xaa,0x81,0xd3,0x25,0x6a,0x5d,
+  0x58,0x0c,0xa5,0xe0,0x9f,0x30,0x6f,0x1a,0x38,0xd1,0xc6,0x2b,0x23,0x9c,0x3d,0x22,
+  0xb5,0x09,0x08,0x9c,0x02,0xc4,0xae,0x04,0xd4,0x12,0xbb,0xd1,0x28,0x6d,0x62,0x3f,
+  0x18,0xfd,0xd1,0x70,0xb7,0x96,0x03,0x01,0xd6,0x08,0x33,0x5e,0x45,0x41,0x1d,0x91,
+  0x9a,0x04,0x94,0xcf,0x7e,0xd2,0x2c,0x30,0x30,0xec,0xfd,0xa4,0xfc,0xe1,0xfe,0x9f,
+  0x51,0x4e,0x62,0xa9,0x8a,0x8e,0xd0,0x01,0x28,0xe5,0x89,0x28,0x23,0x70,0xc8,0x6b,
+  0xe7,0x8d,0x71,0x39,0xff,0x46,0xa5,0x56,0xb2,0xdd,0xdc,0x1f,0xf6,0x7a,0x9e,0xff,
+  0x63,0x63,0x86,0x77,0xcb,0xe0,0x37,0x1e,0x14,0xc3,0xb1,0x44,0xd6,0x5e,0x79,0x94,
+  0x1a,0x89,0x40,0xe7,0xc4,0x2e,0x13,0xfe,0x79,0xd7,0xc0,0xcf,0xd6,0x95,0xe2,0xcd,
+  0x60,0xa4,0x3d,0x0f,0x8b,0x15,0xf4,0xb0,0x63,0x07,0xb3,0x72,0xff,0xe4,0x40,0xf3,
+  0x6c,0xd7,0xe2,0xa5,0x05,0x49,0xfe,0x1f,0x5d,0x39,0xcd,0xb3,0xc1,0x81,0x67,0x1b,
+  0x2a,0x01,0xc6,0xdb,0x12,0xf9,0xab,0x48,0x8b,0x6e,0x0f,0x5b,0xda,0xc9,0x6f,0xa1,
+  0xad,0xd1,0x2e,0xa0,0xc4,0x1e,0x4d,0xc4,0xbf,0x22,0x13,0xfe,0x9f,0xb0,0xdd,0x89,
+  0xcb,0xa8,0xf2,0xc6,0xaf,0x56,0x4f,0x23,0x51,0x9b,0xeb,0x18,0xb1,0x22,0x30,0xb6,
+  0x53,0xdc,0x21,0xe7,0x12,0xf5,0xa7,0xfa,0x94,0x90,0xd2,0xc3,0x17,0x01,0xef,0xcf,
+  0xf9,0x04,0x84,0x5b,0xd8,0x32,0x27,0xcf,0xff,0x0c,0x59,0x82,0xfe,0xdf,0xaa,0xbf,
+  0x62,0x46,0x7f,0xd8,0x51,0x93,0xbf,0x28,0xe6,0x7f,0xb0,0xf2,0xb0,0xd4,0x21,0x1e,
+  0x76,0xe9,0x6c,0x73,0xd2,0x03,0xcc,0xd5,0x65,0xcd,0x10,0xbf,0x0e,0x6f,0x32,0x97,
+  0xc3,0xda,0x62,0xea,0x8f,0x16,0x12,0xc2,0x60,0x2c,0x82,0x6e,0x64,0xd3,0x55,0x81,
+  0x55,0xff,0x16,0xe2,0xc3,0x8c,0x4a,0xb6,0x7e,0x50,0x1c,0xb5,0xfc,0x25,0xa3,0x4a,
+  0xc2,0x9f,0x86,0x53,0xf0,0x0f,0x47,0x53,0xd6,0xed,0x4d,0xfc,0xfe,0x95,0xfd,0xa8,
+  0x28,0xd7,0x2a,0xe3,0xe0,0x6e,0xcf,0x6a,0x9e,0x34,0x9d,0xf7,0xa7,0x53,0xd7,0x32,
+  0x71,0xb6,0x09,0xff,0xf0,0xc7,0x46,0x90,0x83,0xdf,0x57,0x62,0xde,0x12,0x15,0x07,
+  0x15,0xb0,0xdd,0x83,0x66,0xd7,0x1e,0x8f,0x14,0x6c,0x0b,0xd9,0x55,0x7c,0x71,0x57,
+  0x0a,0xfe,0xe1,0x68,0x90,0xce,0xc9,0x5e,0x0c,0x4d,0x7a,0xc9,0x58,0xac,0x9f,0xa9,
+  0xa6,0x2a,0x16,0xf0,0x58,0x0d,0xc5,0xed,0x70,0x59,0x5c,0x09,0x7d,0x17,0x15,0xdc,
+  0xd0,0xcc,0x8a,0x55,0x1a,0x49,0x7f,0x18,0x9a,0x03,0xb3,0x54,0xba,0x94,0x4c,0x93,
+  0x76,0xf8,0xf3,0x55,0x5a,0x87,0x46,0xe1,0x9a,0xe0,0x96,0x51,0x3a,0x46,0x2a,0x12,
+  0xf1,0xaf,0x3b,0x11,0xff,0xfc,0x5e,0xaa,0xd4,0x9d,0xb3,0xc5,0xc5,0xf0,0x2a,0x54,
+  0xf0,0xb2,0xc1,0xb5,0x70,0xd6,0xe5,0xa2,0xeb,0x88,0xc7,0x4a,0x5f,0xd5,0x5c,0xba,
+  0xd5,0x25,0x66,0x27,0xe3,0x5f,0x37,0x25,0xd6,0x27,0xac,0x5d,0x52,0x16,0x80,0xed,
+  0x4d,0xe1,0x32,0xfc,0x44,0xc1,0x2b,0x9a,0x78,0x52,0xfb,0x52,0xaa,0xea,0xb7,0x8d,
+  0x99,0xf8,0xb1,0xe3,0xfe,0x9f,0xa8,0x91,0xed,0xfc,0x31,0x8b,0xe7,0x87,0x5f,0x84,
+  0x8a,0x53,0xd6,0x80,0xe8,0x94,0x3e,0x23,0x6e,0xdd,0xda,0x65,0xe6,0xc7,0xde,0x10,
+  0x84,0x9d,0x28,0x34,0x22,0x1a,0x19,0x44,0x55,0x9c,0x0f,0x32,0xca,0x93,0xdc,0x5d,
+  0x90,0xc9,0x79,0xd3,0xa6,0x1a,0x44,0xd9,0x68,0x4f,0x75,0x27,0xe4,0x1b,0x83,0xa7,
+  0x95,0x5d,0x6c,0x16,0x77,0xf2,0xbc,0x0b,0xff,0xc2,0xc3,0x5e,0x3c,0xdf,0xfb,0x25,
+  0x56,0xdc,0x91,0x11,0xf1,0x4f,0x33,0x42,0x81,0x19,0xf5,0x84,0x9a,0xf0,0x8f,0x0e,
+  0xf1,0xfd,0x13,0x05,0x26,0xa8,0x20,0x2b,0xe9,0x03,0xb0,0xdd,0xb7,0xa2,0xf1,0x4e,
+  0xb8,0x27,0x53,0xdd,0xa1,0xd9,0xb9,0x87,0xed,0x29,0x53,0xfc,0x2b,0x00,0x17,0xa0,
+  0x84,0x97,0xbd,0x0f,0x4b,0x2f,0x90,0x38,0x3f,0xf6,0x15,0xa8,0xe2,0xa1,0xb6,0xdb,
+  0xe0,0x0b,0xcd,0xcd,0x8a,0x3b,0x53,0xf8,0xb1,0x63,0xdb,0x66,0x56,0x3f,0x19,0x9d,
+  0x58,0xa8,0x28,0xaf,0x87,0xca,0x5e,0xcb,0x33,0x54,0xc7,0x6e,0x47,0x53,0x45,0x6f,
+  0x32,0xc7,0xbf,0x62,0xfc,0x3f,0x78,0x5a,0x0b,0xf3,0x0e,0x28,0xbc,0xec,0xdd,0xd3,
+  0x09,0xe3,0x8d,0x65,0xf1,0xc6,0x58,0xed,0x5f,0xe5,0xff,0x89,0xa5,0xf1,0x3c,0x6d,
+  0xff,0xba,0xef,0x00,0x2b,0xd1,0x8c,0x46,0x69,0xbb,0x83,0x25,0xf7,0xb4,0x6d,0xbe,
+  0xe7,0x0c,0xdd,0xad,0x95,0x69,0x81,0x6b,0xfd,0x3f,0x8f,0x09,0xdf,0xbb,0x5f,0x7e,
+  0xd3,0x32,0x07,0x1e,0x8b,0xd5,0xb3,0x74,0x72,0x0f,0xa4,0x76,0x63,0xd0,0xf3,0xac,
+  0xc4,0x03,0x67,0x74,0x90,0x1c,0x31,0xf1,0xff,0xf0,0x69,0xf9,0x0d,0xa8,0xad,0xa6,
+  0xc0,0x2f,0x58,0xb1,0x97,0xde,0x4b,0x9a,0x73,0x79,0x3c,0xe8,0xc6,0xbc,0xec,0x7e,
+  0x94,0xd8,0xcf,0x34,0x38,0xbc,0xe4,0x60,0x22,0xfe,0xc5,0xf1,0x4f,0x3c,0xdb,0xd9,
+  0x90,0x36,0xb8,0x55,0x09,0xf7,0x48,0x70,0x22,0xa0,0x9a,0x10,0xbd,0x20,0xb8,0x05,
+  0xab,0x5e,0x90,0xf4,0xff,0x9c,0xb8,0x89,0x27,0xde,0x56,0x18,0x6a,0x5d,0x3a,0xc5,
+  0x0b,0xc1,0x82,0xe4,0xfb,0xd2,0x65,0xad,0xea,0x4d,0x9b,0x37,0xe7,0x3c,0x5c,0x16,
+  0x2a,0x78,0xa0,0x27,0xc9,0x8f,0x9d,0x27,0x18,0x4d,0x40,0x6a,0x11,0xe4,0xe4,0x0a,
+  0x87,0x79,0xd9,0xbb,0x22,0x0c,0xb1,0xcf,0x11,0xff,0x38,0x07,0x6b,0x2a,0x38,0xb1,
+  0xb6,0x66,0x1d,0x2c,0x48,0xe2,0x9f,0x95,0xf1,0xfe,0x20,0xd4,0xc0,0x3f,0xf1,0x44,
+  0x20,0xad,0x87,0xd3,0xce,0x33,0x34,0xbb,0x7a,0x88,0x71,0x25,0xc9,0x8f,0x8d,0xf8,
+  0x47,0xda,0x2d,0x15,0xf2,0x78,0x9f,0xe4,0x6a,0x14,0x9c,0x9e,0x40,0xb6,0x9f,0xf3,
+  0x81,0xab,0xb7,0x53,0x9e,0x91,0xc8,0x3b,0x86,0x38,0x14,0x62,0xe2,0xc7,0x9e,0xd2,
+  0x39,0x75,0x37,0x74,0xf2,0xf9,0xdc,0x9f,0xe6,0xac,0xae,0xe7,0xfd,0x79,0x77,0x6b,
+  0x45,0xdc,0xb1,0x36,0x1d,0x76,0xd7,0x94,0xf0,0x8e,0x69,0x29,0xf1,0xaf,0xbc,0xed,
+  0x50,0x86,0xb0,0xc7,0x22,0xe1,0x87,0xab,0xc4,0x69,0x46,0x62,0xb3,0xdb,0x67,0xdd,
+  0x20,0xce,0xd0,0x38,0xf0,0x73,0x9a,0xfb,0xc3,0x0e,0x73,0xff,0x8f,0x64,0x54,0x87,
+  0x2d,0xe7,0xde,0x1e,0x4f,0x2c,0xff,0xb9,0xbd,0x62,0xb9,0x2d,0x28,0x9f,0xe1,0xae,
+  0xa1,0x1a,0x1c,0x9c,0xbb,0xc6,0xff,0xc3,0x9d,0x3c,0x3c,0x91,0x04,0x0f,0xff,0x7a,
+  0xfc,0x10,0x92,0x0e,0xf3,0x14,0x5b,0xc0,0xc8,0x48,0x77,0x0b,0x46,0xbf,0xb0,0x89,
+  0xe7,0x41,0xfc,0x23,0xec,0xe1,0xfd,0x41,0xa2,0x64,0x1e,0x59,0xc7,0xe6,0x06,0xb3,
+  0x42,0x77,0x38,0x60,0x9d,0x56,0x10,0x90,0xeb,0xc9,0x30,0xbc,0xab,0xcc,0x65,0xb2,
+  0x2f,0xd5,0xff,0xa3,0xec,0xe0,0xdd,0x19,0x5c,0xf8,0x52,0x7e,0xa6,0x0e,0xb6,0xb8,
+  0xec,0x28,0x76,0x14,0xc7,0xc3,0xf2,0x64,0xd2,0xaf,0x34,0x49,0xf6,0xe3,0xf2,0xb5,
+  0xfe,0x9f,0x57,0xa0,0x40,0xcf,0x6b,0x20,0xb9,0xae,0x35,0x81,0xe9,0x44,0xbe,0x40,
+  0xb2,0x60,0x0d,0xdc,0x5f,0x7d,0xa3,0x97,0x7c,0x01,0xff,0xdc,0x38,0x1d,0xef,0x6f,
+  0xe2,0xc7,0x36,0xfc,0x3f,0x6c,0x36,0x57,0x2b,0x88,0x76,0x70,0x90,0xf1,0x63,0xcb,
+  0x34,0xf2,0x1a,0xcb,0xf0,0x2d,0x59,0x9a,0xf3,0x07,0x8a,0x57,0x78,0xa3,0xb4,0xd3,
+  0xe6,0xfc,0x1f,0xfa,0x19,0xec,0xd3,0x66,0x31,0x5c,0x96,0xcf,0x84,0x4a,0xb8,0x7b,
+  0x47,0x2c,0xfe,0xc5,0xcb,0x48,0xfb,0xa5,0x8b,0xb1,0x08,0xb5,0xc9,0xff,0xb3,0xea,
+  0x8a,0x37,0x5e,0xb6,0x53,0xc6,0xdb,0x9a,0x0f,0xdd,0xbc,0x9b,0x5c,0xc9,0x43,0x8d,
+  0xf6,0xc1,0xda,0xb7,0x72,0xca,0xea,0x2e,0x06,0x4b,0x3b,0xd7,0xd6,0xcb,0x49,0x7c,
+  0x62,0xe4,0xff,0x38,0x78,0x13,0x37,0x7b,0x2e,0xac,0x91,0x8a,0x3d,0x59,0x8f,0x92,
+  0x93,0xc1,0x97,0x97,0x67,0x1e,0x7f,0xe1,0x9b,0x1b,0x73,0x23,0xbb,0x42,0xb7,0x34,
+  0xd3,0xfb,0xfd,0x2f,0x98,0xe3,0x5f,0x28,0x94,0xee,0xe7,0x2f,0x35,0xd5,0xf7,0x04,
+  0x14,0xf7,0xca,0x0d,0x7d,0x27,0xa5,0x5d,0x5a,0xb1,0x9f,0xea,0xf6,0xbf,0x51,0x5e,
+  0xa9,0xce,0x6f,0xce,0xf0,0x5d,0x83,0x7f,0x76,0x80,0x3d,0x4f,0xb6,0x12,0x1b,0x79,
+  0xdc,0xeb,0xf4,0x59,0xca,0xb3,0x07,0x94,0x6e,0xe2,0x1c,0xb6,0x48,0x9e,0x3b,0xb4,
+  0xed,0xcd,0x45,0x6c,0xa6,0x9d,0x04,0x4c,0xf1,0xaf,0xdf,0x96,0x7f,0x06,0xdd,0x8a,
+  0xed,0x49,0xd4,0x56,0x6f,0x1d,0x2f,0x39,0x6f,0xbb,0x64,0x1f,0x51,0x2e,0x70,0x8f,
+  0x71,0x8f,0xb8,0x02,0x3e,0x0b,0xd9,0x59,0xe6,0x36,0xb9,0xe8,0x5a,0xff,0x8f,0x62,
+  0xdb,0x22,0x7f,0xc0,0x3e,0xae,0xad,0x0c,0x1a,0x7c,0xda,0x17,0x08,0x6f,0x8b,0xf6,
+  0x9f,0xb6,0x49,0x08,0x1d,0x95,0xac,0x6b,0xfc,0x3f,0xea,0x55,0x3a,0x37,0x6a,0x3d,
+  0x11,0xab,0xf7,0xe9,0xb7,0x8e,0x36,0x71,0x84,0x80,0xf6,0x45,0xb4,0xe9,0x11,0xbc,
+  0xf2,0x23,0x7d,0x71,0x54,0x8c,0x24,0xf0,0x0f,0x33,0xfc,0x3f,0x76,0x5f,0xdd,0x5a,
+  0x7f,0xb4,0x79,0xef,0x01,0xe7,0xc6,0x3a,0x1e,0xff,0x0a,0x43,0xc7,0xfd,0xb2,0x13,
+  0xb1,0xff,0x6e,0xcd,0xee,0xe2,0x1e,0xc5,0x6b,0xf2,0x7f,0x66,0xe4,0xd1,0x8d,0x9e,
+  0x4e,0xb6,0x97,0x19,0xfd,0x4c,0x47,0x60,0xb7,0x6a,0xf7,0xc9,0xed,0x7e,0xfc,0x29,
+  0x30,0x63,0xcb,0xb5,0xfe,0x1f,0xb6,0x83,0xb3,0x58,0xaa,0x1e,0xde,0xaf,0xa7,0x44,
+  0xa0,0x6e,0xfb,0x80,0xd4,0x83,0x16,0xca,0xa2,0x60,0x3a,0x9e,0x47,0x55,0xe5,0x8d,
+  0xe4,0xfa,0x92,0xfc,0xd8,0x99,0x3c,0xbf,0xb7,0x8c,0x59,0x15,0x31,0x44,0x79,0x9a,
+  0xb7,0x73,0xf4,0x71,0xbc,0x3f,0x4a,0xd4,0x25,0x8c,0xe7,0xf7,0xe6,0x1b,0xa6,0xab,
+  0xde,0x94,0xcc,0xff,0xf9,0x84,0xbf,0x26,0xcc,0xd2,0x73,0x06,0xe9,0x55,0x81,0x77,
+  0xb3,0xaa,0xe6,0xef,0xbb,0xa0,0x7a,0x92,0x26,0x5e,0x82,0x2f,0x94,0x57,0x38,0xb1,
+  0x89,0x99,0xff,0xe7,0x2a,0x77,0x9b,0xf0,0xfc,0xf0,0x15,0x70,0x14,0xdc,0x51,0xeb,
+  0x69,0x84,0x85,0xb8,0x3e,0x14,0xcd,0xf6,0x39,0xd5,0x03,0xb7,0x23,0x42,0xe8,0x25,
+  0x29,0xf9,0xcf,0x6c,0x0f,0xb3,0xd3,0xba,0xf6,0xfc,0x4f,0x69,0x2b,0xf8,0xa3,0x34,
+  0xe4,0xb1,0x43,0x4f,0xb0,0xc8,0x45,0x1f,0x23,0xcf,0xe8,0x81,0xea,0x92,0xa9,0x74,
+  0xf5,0x35,0xf1,0xaf,0x3d,0xa0,0x12,0xca,0x2c,0x5c,0x9b,0xdb,0x75,0x9a,0x4f,0x40,
+  0xc3,0xf7,0x6d,0xa6,0x90,0x2d,0x01,0x82,0x1b,0x91,0x0a,0xa9,0xf1,0x2f,0xd8,0x13,
+  0xb0,0x8b,0x68,0x8f,0x8c,0xb0,0x56,0x84,0x91,0x34,0xe4,0x57,0xd5,0x1e,0x5a,0xe4,
+  0x77,0xb0,0xbe,0xce,0x82,0x17,0x59,0xc9,0x29,0xda,0x05,0x49,0xff,0x8f,0x3a,0x79,
+  0x04,0xce,0xe9,0xdd,0x5e,0x6b,0x9a,0x78,0x2b,0x0c,0x84,0xc2,0xba,0x75,0x48,0x9c,
+  0x5d,0x77,0xc9,0x5b,0xaa,0x58,0x5f,0x13,0x17,0x40,0x40,0xaf,0xac,0xb7,0x6e,0x16,
+  0xf2,0x52,0xfc,0x3f,0xa8,0xdd,0x1c,0xb6,0x13,0x4d,0x73,0xc8,0x15,0xbd,0xaa,0x6f,
+  0x56,0x54,0x3c,0x0d,0x63,0xac,0x8a,0xb7,0xf5,0x1c,0x51,0xfe,0x44,0x2b,0x61,0x16,
+  0x5c,0xe3,0xff,0xb9,0xc0,0xd3,0x38,0x9b,0x51,0x2d,0x1e,0xa0,0xa8,0xdf,0x3b,0x39,
+  0x2d,0xbf,0xe6,0x0e,0x5a,0x9b,0xc5,0x62,0xfd,0x84,0x56,0xe9,0x41,0xfb,0x2b,0xb5,
+  0xfe,0x6b,0x0f,0xf7,0xc6,0xef,0x13,0x03,0xd0,0xd6,0x6c,0x1f,0x44,0xbc,0x97,0xaf,
+  0xe1,0x7e,0x67,0x99,0x94,0x14,0x2b,0x19,0x91,0x92,0x06,0x5c,0xa8,0x64,0xfe,0xb3,
+  0xce,0xed,0x2f,0x1f,0xce,0xbf,0x95,0x1c,0xd1,0x5a,0xfc,0x6a,0xbf,0x1c,0x26,0x59,
+  0xa4,0x0d,0x42,0x3e,0x5a,0x6e,0xb1,0xe3,0x8a,0x95,0x84,0xa9,0x83,0x84,0x53,0xfc,
+  0x3f,0x3b,0x1b,0x8d,0xfa,0xf7,0x75,0xad,0xab,0x59,0xfe,0x70,0xdb,0x4a,0x32,0x4d,
+  0x5d,0xe3,0xcf,0x5f,0x96,0xf1,0x63,0x14,0xe3,0xab,0xb6,0x14,0x87,0x10,0x11,0xb5,
+  0x27,0xee,0x5f,0x8f,0xf8,0xe7,0x9c,0x5a,0x01,0x36,0xd7,0x37,0x8e,0x40,0xcb,0xcc,
+  0xf0,0x90,0x2d,0x2c,0x5b,0xe1,0x55,0xd5,0x15,0xb1,0xce,0x6f,0x02,0xd2,0xe7,0xad,
+  0xf0,0x58,0xcb,0x9a,0x9e,0x4a,0xf1,0xff,0xec,0xe7,0x4e,0x9e,0xb3,0xe2,0x25,0x3a,
+  0x51,0xff,0xa5,0x5d,0x84,0x05,0xdc,0xfe,0x3a,0x57,0xfb,0x97,0xd9,0x46,0xeb,0x61,
+  0x6f,0x8a,0xff,0xc7,0x38,0xad,0xe1,0x49,0x03,0x42,0x44,0xe8,0xee,0xb5,0xf5,0x18,
+  0x40,0xd4,0x68,0xf4,0x5c,0x04,0x03,0xb1,0xfa,0xca,0xd4,0xfe,0xb0,0x2f,0xa3,0x9a,
+  0x8e,0x78,0xb3,0x4f,0x12,0xc6,0xcd,0x46,0x9e,0xef,0xd4,0xc4,0x03,0x37,0x2e,0x42,
+  0x95,0xc7,0xa0,0x00,0xa8,0xf7,0x9a,0xfc,0xe7,0x97,0xf5,0x62,0x4e,0xea,0xf8,0x2e,
+  0x5d,0xa5,0x1b,0xf8,0x67,0x1a,0x3c,0xc1,0x0c,0x22,0xa0,0x1b,0xf2,0x9a,0x59,0xfe,
+  0xb2,0xc0,0x54,0x73,0xfe,0xb3,0x82,0xf6,0x97,0xea,0x5c,0x46,0x8d,0x6e,0xb0,0x88,
+  0x1e,0x17,0xc5,0x1b,0x11,0x72,0x8f,0x50,0xab,0xb7,0x51,0x08,0x35,0x38,0x36,0x5f,
+  0x5b,0xff,0xa5,0xfd,0x9c,0x39,0x7d,0xe2,0x45,0x38,0xa2,0xf3,0xb6,0x83,0xb2,0x83,
+  0x1c,0xe3,0x15,0x99,0xaa,0x5c,0x4e,0x8e,0x44,0x4a,0x43,0xd6,0xa1,0x6b,0xf3,0x9f,
+  0xb5,0x4a,0x09,0xf7,0x43,0x54,0x1d,0x8d,0xb1,0x1d,0xea,0xa8,0xd5,0x8c,0xfa,0x94,
+  0x87,0x60,0x8c,0xf2,0xfa,0xf7,0xc7,0xaf,0xf1,0xff,0x30,0x54,0x82,0x9b,0x0b,0x24,
+  0x38,0x90,0xeb,0xae,0xe5,0xb4,0x3f,0x2c,0x4e,0x7b,0x58,0x08,0x67,0xed,0x2e,0x9f,
+  0x14,0x14,0xaf,0xc9,0x7f,0xc6,0xf9,0x68,0x44,0x14,0x42,0x8b,0xae,0x1a,0xfe,0x1c,
+  0x3f,0xe2,0x7f,0xbc,0x22,0xfe,0x03,0xef,0x58,0xe1,0xa5,0x4f,0x5f,0x9b,0xff,0x9c,
+  0xe7,0xe4,0x30,0xc9,0x49,0x5a,0xaa,0x8d,0x78,0xd9,0x79,0x78,0x4c,0x2d,0xd0,0x1c,
+  0xc7,0xc8,0x1c,0x6d,0x37,0x25,0x0b,0x2d,0x1b,0xfe,0x95,0xfc,0x67,0x8e,0x07,0xa0,
+  0x51,0xb3,0x73,0xb7,0xcf,0x71,0x61,0x15,0x6f,0xfc,0xed,0x25,0xff,0x19,0x81,0x7a,
+  0xc8,0xfb,0x91,0xb9,0xfe,0x34,0x11,0xff,0x0a,0xdd,0x82,0xfa,0x97,0xd8,0x27,0xfc,
+  0x0f,0xdc,0x11,0x21,0xbb,0x10,0x6a,0xbb,0x61,0xdd,0x35,0xf5,0x5f,0xf4,0x32,0xcc,
+  0x8f,0x55,0xbb,0x5f,0xf5,0x54,0x69,0xb3,0x36,0xd5,0x7c,0x00,0xe3,0xbc,0x3f,0xda,
+  0x26,0xf1,0x03,0x7a,0x55,0xab,0xf2,0xde,0x75,0xbc,0x26,0x25,0xfe,0xa5,0x5d,0x86,
+  0x0a,0xaf,0x6d,0x30,0x67,0x8e,0x83,0x27,0x02,0xd9,0xde,0x16,0xcb,0xd4,0xc3,0x81,
+  0xd2,0x7a,0xeb,0x89,0xa6,0xb9,0x80,0x88,0xc8,0x6b,0x7d,0xb3,0xe9,0x8c,0x92,0xf4,
+  0xff,0x9c,0x66,0x7b,0x84,0x12,0x4e,0x72,0x98,0xaf,0xf4,0xa8,0x1d,0x80,0x66,0x63,
+  0x3e,0x04,0xb4,0x0e,0xa0,0xcd,0x16,0x1c,0xa8,0x28,0x81,0x3b,0xc9,0x11,0xb3,0xff,
+  0x87,0x19,0x69,0x3f,0x41,0x5e,0xe6,0xcf,0xab,0xbd,0x72,0xfd,0xbc,0x43,0xae,0xca,
+  0x57,0x20,0x0d,0x1a,0xeb,0x70,0x29,0xb2,0x4d,0xfd,0xa9,0x8d,0xfc,0xe7,0xe6,0x92,
+  0x3a,0x79,0xa3,0x7d,0x79,0xe7,0x6e,0x81,0x3b,0x82,0xec,0x85,0x34,0xee,0x4f,0x2b,
+  0x14,0xda,0xd4,0x92,0x41,0x9a,0xd2,0x1f,0x36,0xd7,0x88,0x67,0xf9,0x6c,0xfc,0xeb,
+  0x8c,0x73,0xa0,0x3b,0x88,0x86,0x3e,0x7e,0x5f,0x1f,0xc2,0x1e,0x1c,0xdc,0x5e,0xb9,
+  0xdc,0xda,0x8e,0xd0,0x7a,0x62,0x7f,0x1a,0xf5,0x5f,0x50,0x59,0xbd,0xa4,0x5d,0xee,
+  0x84,0xb3,0xfa,0xfe,0x89,0x7c,0xb0,0x8a,0x06,0x84,0x85,0xfd,0xf8,0x53,0x85,0x6f,
+  0xd6,0xc6,0x82,0x6b,0xea,0xbf,0xa8,0x11,0xe4,0x3a,0x05,0x63,0x8d,0x0f,0x1b,0xb4,
+  0x3f,0x2c,0x16,0xf6,0xca,0x51,0x03,0x11,0x1f,0xff,0x10,0x05,0xd7,0xd4,0x7f,0x05,
+  0xca,0x1a,0x69,0xbd,0x7f,0x98,0x37,0x32,0xf3,0xa3,0xf6,0xb9,0x01,0x5a,0x25,0xb4,
+  0xbf,0x42,0xe2,0x3c,0x78,0x57,0x2f,0x08,0xd2,0xa8,0x27,0xc9,0x30,0xed,0x10,0x16,
+  0xa3,0x76,0x53,0x63,0xdd,0x18,0x51,0x31,0x9d,0x0e,0x84,0x49,0x26,0x6d,0xf2,0xfb,
+  0x50,0xfe,0x90,0x3b,0xd0,0x3e,0x55,0x1f,0xa6,0x79,0xfe,0xd4,0xfa,0xaf,0x9d,0xfe,
+  0xaf,0x0f,0x53,0xce,0xd6,0xf5,0x12,0xe0,0x31,0xf4,0xfa,0x33,0x61,0x8d,0x96,0xef,
+  0xa1,0x8f,0x90,0x5c,0xf5,0x89,0x40,0xbe,0x97,0xde,0x77,0x6d,0xfd,0x17,0x7b,0x68,
+  0xcc,0xc9,0xb3,0x9d,0xaf,0xb2,0x2d,0x51,0x5a,0x21,0x4e,0x23,0xaf,0xb2,0xed,0x3e,
+  0x67,0xb9,0x7c,0x37,0x9c,0x6c,0x2e,0x0d,0x39,0x87,0x53,0xeb,0xbf,0xe0,0x1c,0x54,
+  0x46,0xf0,0x34,0x0d,0xa1,0xb5,0x5e,0x81,0x66,0xbe,0xcc,0x35,0x7e,0x85,0xb6,0x3e,
+  0x6c,0xf4,0xf3,0xaa,0xe2,0xfa,0xcb,0x9c,0xff,0x7c,0x05,0x2e,0x07,0x77,0x8d,0x4e,
+  0x7d,0x4b,0xac,0xac,0x3e,0x12,0x2c,0xf5,0x65,0x1a,0xf5,0x5f,0xc1,0x2a,0x9f,0xf5,
+  0x82,0xf8,0x05,0x1c,0xc6,0x2b,0x36,0xde,0x1f,0xc4,0xec,0xff,0xd9,0xe9,0x2a,0xd0,
+  0x03,0xf7,0xe7,0xdc,0x0b,0x6b,0xcb,0xf3,0xbd,0x75,0x0d,0x9e,0x93,0xd2,0x9a,0x50,
+  0x31,0x97,0x3f,0xe7,0xd9,0x2a,0x57,0xfe,0x1d,0xf2,0x77,0x52,0xfb,0xc3,0xc2,0xcb,
+  0x24,0x5f,0x77,0x78,0xed,0xd6,0x8c,0xd5,0xfc,0x98,0xf0,0xfc,0x9f,0x55,0xdc,0xd0,
+  0x78,0xd8,0x7e,0x7c,0x3a,0x27,0xbc,0x96,0x3d,0xa4,0x9f,0x4d,0xac,0xbf,0x2f,0x77,
+  0xc4,0xda,0xad,0x15,0x0e,0x52,0x2b,0xa9,0x55,0xda,0x21,0xa4,0x39,0xc2,0xbc,0xcd,
+  0x25,0xee,0x40,0x87,0x8b,0x7c,0x28,0xf8,0x75,0xb5,0x5d,0xfe,0xad,0x89,0x7f,0x95,
+  0xe7,0x3f,0x8f,0x45,0x6f,0xed,0xb7,0x86,0x9b,0x0a,0xe1,0x10,0x33,0xf8,0xe5,0x46,
+  0xc8,0xab,0x3c,0x91,0x3e,0x8c,0xb0,0x10,0x35,0x8e,0xcf,0xf6,0x94,0x78,0x30,0xb5,
+  0xfe,0x8b,0xce,0x7b,0xcd,0xb6,0x13,0x77,0xcb,0x30,0xad,0x7c,0x33,0x2b,0x68,0xd8,
+  0x9b,0x06,0x3e,0x8c,0x36,0x5e,0xbc,0xb3,0x32,0xd6,0x68,0xcf,0x84,0x7f,0xd0,0xfa,
+  0x29,0xd5,0xad,0xd1,0xa6,0xf3,0xda,0x9f,0xb8,0xff,0x64,0x34,0xa7,0x02,0x8e,0xaa,
+  0xee,0xda,0x15,0xe7,0xc4,0x31,0x18,0x04,0xa3,0x51,0xac,0x6a,0xf2,0xff,0xfc,0x04,
+  0xfc,0x8d,0x5b,0x75,0x4b,0xf3,0xc6,0x21,0xe5,0xa4,0xee,0x68,0xa0,0x27,0x88,0x0d,
+  0xda,0x58,0x19,0x0f,0xf4,0x9c,0x91,0x02,0xba,0xbd,0xa1,0x6d,0xed,0x46,0x73,0xfd,
+  0xfb,0x0a,0x08,0xb0,0x19,0x68,0x14,0xc0,0x10,0xb4,0xea,0x76,0x5f,0xc6,0x76,0x32,
+  0x0b,0xda,0xf0,0xe0,0xd0,0x30,0x9c,0x56,0x51,0x70,0x21,0x10,0xba,0xa6,0xfe,0x8b,
+  0xb1,0x65,0xba,0xc5,0xe5,0xe9,0x9f,0x14,0x84,0x22,0x25,0x4f,0xe1,0xc0,0x40,0x35,
+  0x3c,0xf6,0x3a,0x6a,0x84,0x10,0xc8,0xa8,0x00,0x13,0xab,0xcf,0xeb,0xbf,0x22,0x30,
+  0x57,0x5f,0xcb,0xc8,0x50,0x75,0x84,0x18,0xf1,0x17,0xd4,0x2f,0x0e,0x94,0x9f,0x1b,
+  0x50,0x10,0x1d,0xe0,0x16,0xc1,0x46,0x31,0xa5,0xfe,0x4b,0x39,0xcf,0xd5,0x96,0x26,
+  0x9e,0x67,0x23,0xb0,0xc0,0x28,0xfb,0x22,0x3c,0x83,0x7a,0xc9,0xb9,0xb8,0xc7,0xc3,
+  0xd6,0xf8,0x3d,0x53,0xfc,0x2b,0x93,0xc7,0x4f,0xe7,0x46,0x6d,0x0d,0xe2,0x20,0x1d,
+  0x81,0x2a,0x8a,0x62,0xf9,0x13,0xb6,0xbe,0xbf,0x52,0xb4,0xae,0x2c,0xa8,0x84,0x48,
+  0x6f,0xe9,0xd9,0xcd,0x63,0x66,0xfe,0x9f,0xc0,0x6f,0xf3,0xe2,0x69,0xcf,0x1f,0xe7,
+  0x06,0x06,0x4b,0x6e,0x40,0x43,0xec,0x92,0xde,0xaa,0x3a,0x07,0x2d,0x68,0x7b,0x19,
+  0x08,0x27,0x2f,0x4c,0x4c,0xfc,0x87,0xd2,0x00,0xc4,0xd3,0x9e,0x5f,0x95,0x3a,0xc0,
+  0x29,0xdd,0x09,0xd9,0x8b,0xa5,0x46,0xe2,0x5c,0xe8,0x70,0x79,0xac,0xb0,0x31,0xbf,
+  0xf0,0x80,0xc5,0xbd,0xda,0xd4,0x1f,0x2d,0x6d,0x82,0xff,0x87,0x7c,0x0a,0xad,0x7d,
+  0x25,0xae,0x3b,0x03,0x88,0x27,0x79,0xfc,0xcb,0xc2,0x03,0x61,0xbf,0x62,0x2a,0x0e,
+  0xec,0x26,0xfe,0x43,0x89,0xf3,0xf3,0xcc,0xd3,0x8d,0x26,0xa4,0x5d,0xac,0x32,0x54,
+  0xbc,0x0f,0xf7,0xcf,0x21,0xa1,0xf2,0x36,0x09,0x17,0x4a,0x7d,0x0b,0x77,0x54,0x51,
+  0x98,0x24,0xf3,0xff,0x37,0x40,0x9c,0x0f,0x61,0xb4,0xe0,0x92,0x51,0x5f,0x99,0x15,
+  0xce,0x19,0xa1,0x57,0xab,0xab,0x46,0x79,0xa0,0xd0,0xfb,0x89,0xf4,0x0a,0xee,0x10,
+  0x39,0xd9,0x1f,0x76,0x14,0xe2,0x7c,0x0b,0x61,0x51,0x55,0x3f,0xf2,0x3d,0xdc,0xbe,
+  0x36,0x54,0xb0,0x18,0xf5,0xbb,0xeb,0x38,0xae,0xff,0x4c,0x0d,0x15,0x7d,0x24,0x33,
+  0x5c,0xf3,0x48,0x92,0x4f,0x46,0x8a,0xe7,0xc3,0x8f,0x66,0x3b,0xa0,0x15,0x96,0x05,
+  0x69,0x07,0xcf,0x8f,0xaa,0xb3,0x47,0x33,0x15,0xf1,0x6e,0xa5,0x89,0x75,0x0c,0xd2,
+  0x9d,0x1d,0x26,0xfc,0x33,0xc1,0x87,0xe0,0xba,0x87,0x82,0x7f,0xd0,0x8e,0x68,0x27,
+  0x7d,0xc0,0xde,0x14,0x50,0x0f,0xe0,0x0e,0xc9,0x64,0x8d,0x93,0x43,0x83,0xd0,0xe3,
+  0x9f,0x58,0x4d,0xc0,0x0d,0x1b,0xab,0xff,0x92,0x7f,0x8c,0x62,0x6d,0x55,0x30,0x5f,
+  0xa5,0x8f,0x66,0x3f,0x0d,0xab,0x83,0xf9,0x51,0x71,0x8c,0xfc,0x8c,0xae,0x09,0x1a,
+  0xc0,0xa0,0x32,0x31,0xbf,0x0e,0xb2,0xf4,0xcf,0xb8,0x18,0x71,0x89,0xc0,0xfc,0x4a,
+  0xc8,0xe2,0xac,0x10,0x8f,0xf0,0xe7,0x8f,0x66,0xb9,0x44,0x2b,0x7b,0x75,0xb0,0x5b,
+  0x77,0x6e,0x97,0xb3,0x93,0xfc,0x3f,0x13,0x7c,0x3e,0xe1,0x45,0xc3,0xe4,0x6d,0x9e,
+  0xd6,0x1b,0xce,0x46,0x04,0x9e,0x6e,0x54,0xc0,0x0d,0xc0,0x45,0x95,0xaf,0x98,0x18,
+  0x4c,0xd8,0x47,0x71,0xfe,0x9f,0x28,0x5e,0x0c,0x81,0x2e,0x18,0xfc,0x93,0xc5,0xec,
+  0x10,0xcc,0xd3,0xa6,0x72,0x20,0xd4,0x1b,0xab,0xe8,0x4c,0xe5,0x7f,0xe6,0xf1,0xf4,
+  0x48,0x03,0xc9,0x83,0x66,0xc9,0x88,0x7f,0xdd,0xe4,0x59,0x8f,0x40,0xa8,0xb8,0x81,
+  0x6c,0x26,0x6b,0xe0,0x79,0x1e,0x61,0x4f,0xda,0xbf,0xf1,0xfc,0x67,0x0e,0x7b,0xfc,
+  0xb0,0x1a,0xe1,0x8b,0x65,0x65,0xeb,0x34,0xb6,0x9e,0x15,0x9f,0xca,0x38,0xc1,0xfd,
+  0x5d,0xb1,0x88,0x98,0x99,0xff,0x39,0xc6,0x37,0x95,0xe1,0x22,0x16,0xb4,0x67,0xed,
+  0x21,0x79,0x3f,0xc7,0x57,0x5e,0x3c,0xa1,0x4a,0xf6,0x3a,0xad,0x69,0xb0,0x84,0x23,
+  0xa2,0xa4,0xfc,0x89,0x48,0x5d,0x13,0x69,0xcf,0x7b,0xc8,0xeb,0xfa,0x8e,0x9e,0xac,
+  0x21,0xd1,0x01,0xaf,0x6b,0x3f,0x7f,0x3e,0xa3,0xa3,0xe0,0x06,0x58,0x27,0xfd,0x53,
+  0xac,0x22,0x3e,0x71,0x7f,0x88,0xe5,0x63,0x64,0x21,0xfe,0xf1,0x8d,0xe5,0x5d,0x21,
+  0x36,0x56,0xd0,0xcb,0x25,0x92,0x62,0x63,0x35,0x51,0x36,0x26,0xcd,0xe3,0x16,0xba,
+  0x89,0xff,0x19,0xe2,0xf5,0x3e,0x8a,0x51,0x1f,0x64,0xd7,0xaa,0x83,0x39,0xcb,0xc9,
+  0x01,0xd6,0xbd,0x3c,0xf3,0x29,0xf1,0xcc,0xda,0x03,0x8e,0xaf,0xf8,0x7f,0x12,0xf5,
+  0x5c,0xdc,0x9f,0x60,0xaf,0xab,0x33,0x80,0x90,0x66,0xbf,0x3f,0xb0,0x99,0x9c,0x81,
+  0x46,0x66,0x28,0xe2,0x68,0x62,0x75,0xf2,0xa4,0x42,0x69,0xb7,0x54,0xa2,0x65,0x04,
+  0xfd,0x9d,0xd0,0x22,0xbc,0x50,0x2b,0x6f,0x20,0xcb,0xd5,0x16,0xf5,0xb4,0x07,0x82,
+  0x9e,0x21,0xf5,0x79,0x1e,0xaf,0x0f,0xda,0xcd,0xfc,0xcf,0x09,0xfe,0x9f,0x18,0x0c,
+  0xb0,0x6c,0x22,0x69,0xd6,0x36,0xcd,0xc0,0x03,0xfd,0x96,0x17,0x8d,0xd0,0x18,0x24,
+  0xe3,0xef,0x4b,0x33,0xa2,0x13,0xf9,0x27,0xf1,0x6a,0x77,0x10,0x35,0x88,0x08,0x2e,
+  0x70,0x86,0x38,0x23,0x5f,0x9c,0xff,0x79,0x92,0x09,0xff,0x80,0xe1,0xff,0xc9,0x35,
+  0x68,0x0f,0xe7,0x7a,0x33,0x8f,0x8b,0x1f,0xc0,0xef,0x48,0x95,0xf7,0x46,0xaf,0x78,
+  0x12,0xfe,0x14,0x4b,0x7d,0x49,0xf6,0x87,0xcd,0xcb,0x4c,0xf2,0xff,0xb0,0x0f,0xd5,
+  0xb9,0x8b,0xad,0xbf,0xaf,0x29,0x1c,0x1c,0xd7,0xaa,0xfe,0x6e,0xea,0xa0,0x38,0x07,
+  0x0e,0x6b,0x88,0x18,0x37,0x88,0xd7,0xf0,0x1f,0xc6,0xca,0xde,0xf3,0x61,0xad,0x17,
+  0xad,0xad,0x49,0xa8,0x9d,0xf6,0xa9,0x25,0x79,0x79,0xcc,0xc3,0x33,0x12,0x55,0x4a,
+  0xfb,0x10,0x9f,0x4c,0x7c,0x5f,0x1f,0xcf,0x7f,0x26,0xc6,0xfb,0x7e,0x5b,0x7b,0x86,
+  0x19,0x8e,0xa0,0x5c,0xe5,0x25,0x70,0x7e,0x93,0xf3,0x1f,0x42,0x8b,0xca,0x43,0x1b,
+  0x24,0xc9,0x7f,0xd8,0x93,0xdb,0x69,0x8d,0xaf,0xff,0x1c,0xfa,0x18,0x94,0xd4,0xd1,
+  0xa0,0x65,0x0e,0x2c,0x10,0x4a,0xbc,0x74,0x03,0x4f,0x84,0x68,0xdc,0xa2,0xd3,0x41,
+  0x92,0xda,0x1f,0x36,0xfe,0xfc,0xff,0x05,0x3e,0xd4,0x66,0x78,0x9c,0x1b,0x63,0x0c,
+  0xcf,0x8f,0x38,0xda,0xc5,0x19,0x9e,0x5e,0xc6,0xbf,0x6f,0x4e,0x0a,0xff,0x61,0x6c,
+  0xbe,0x82,0xcb,0x62,0x64,0x3b,0x1b,0xfc,0x3f,0x3a,0xae,0x58,0xfb,0xa2,0xd8,0x52,
+  0xcc,0x0a,0x12,0x13,0xff,0x21,0x84,0x92,0xeb,0xbf,0x96,0x94,0x11,0xa7,0x5f,0x54,
+  0xbd,0x03,0x86,0xdb,0x27,0xe7,0x14,0x44,0x18,0xf7,0xc8,0x99,0xea,0xbf,0x68,0xb3,
+  0x83,0x1a,0x65,0x5f,0xbc,0xa9,0x68,0x2b,0x14,0x84,0xa8,0x4a,0x8a,0x24,0x1c,0xf4,
+  0xd8,0x56,0xe0,0xb6,0x6f,0xd5,0x4a,0x10,0x08,0x79,0x92,0xfa,0x25,0xce,0xc7,0xc2,
+  0x32,0xb8,0xdb,0xd9,0x0f,0x33,0x7c,0x34,0x97,0xac,0x25,0x5b,0x99,0x1a,0x91,0x15,
+  0xff,0x00,0x6b,0x14,0x9c,0xa7,0x10,0x08,0x91,0x84,0xfe,0x12,0xc0,0xc8,0xff,0x61,
+  0x6d,0x2e,0x3c,0xbf,0x68,0x7f,0x79,0xa8,0xf7,0x8e,0xa7,0x26,0x3f,0xa7,0xe7,0xeb,
+  0x16,0xaf,0xff,0x92,0xba,0x86,0x16,0xf7,0xd1,0x9f,0x78,0x68,0xc2,0xff,0x43,0xd9,
+  0xd3,0xf0,0x25,0x5b,0x10,0xca,0xac,0x17,0x9f,0x4e,0x5f,0xcd,0xe6,0xfa,0xac,0x4b,
+  0xf1,0x44,0x7e,0x8a,0xf8,0x47,0x5e,0x99,0xf3,0x07,0xf2,0x7a,0xf3,0x82,0xa8,0x75,
+  0xcc,0x84,0x7f,0x12,0xf5,0x14,0x21,0x31,0x22,0x9d,0x8b,0x2d,0xec,0x0a,0x78,0x3b,
+  0xa6,0xdf,0xfb,0x21,0x4e,0x8d,0x98,0xf4,0xff,0x68,0xd2,0x7e,0xef,0x55,0x56,0x15,
+  0xb2,0x8d,0x15,0x4c,0x83,0x77,0x79,0x20,0x23,0x22,0xee,0xcf,0x38,0xec,0xaf,0x8a,
+  0x66,0x9e,0x10,0xde,0x85,0x37,0x58,0x29,0xcf,0x7f,0x4e,0xca,0x87,0x17,0x60,0x6d,
+  0xac,0xfe,0xa2,0xc1,0x82,0xcf,0xef,0x98,0x15,0xa1,0x0b,0xc9,0x0d,0x7d,0xff,0x53,
+  0x9d,0x05,0x16,0x2f,0x39,0xe9,0x59,0xa3,0xe4,0x6b,0x8e,0x6f,0x92,0x24,0xfe,0x0c,
+  0x29,0x9b,0x15,0x63,0xbe,0x8f,0x4c,0x45,0xf9,0x53,0xac,0xd3,0x6a,0xc4,0x3f,0xab,
+  0x5b,0x71,0xf0,0x10,0x1a,0x1a,0xab,0xe9,0x33,0xb5,0x19,0x4b,0x49,0x7f,0x92,0xff,
+  0x30,0x26,0x7f,0x78,0x37,0x79,0x94,0xe7,0xcc,0xb9,0x9d,0x12,0xb2,0x02,0xfc,0x21,
+  0x67,0xde,0x42,0x17,0x39,0xaa,0xf8,0x99,0xc1,0x50,0x3a,0x68,0xfa,0xbe,0x46,0xbd,
+  0x1b,0x6f,0xa2,0x3d,0x89,0xa7,0x05,0x7e,0xdb,0xc9,0xd1,0x4b,0x1b,0xab,0x3c,0x46,
+  0xc3,0xe2,0xc1,0x3b,0x5e,0x65,0x6e,0x96,0x19,0x42,0x89,0x3d,0xf1,0xbe,0x0c,0xe2,
+  0xeb,0xc3,0xd1,0xd1,0x87,0x3e,0xbe,0x3e,0x93,0x42,0x70,0x51,0xac,0xf4,0x66,0x05,
+  0x6b,0x3e,0xd1,0x2e,0x6a,0x95,0x83,0xd3,0x3a,0x0b,0x3e,0x4c,0xf2,0x3f,0x1b,0xfa,
+  0x6e,0x3e,0x07,0x39,0x73,0xd5,0xc3,0xbd,0x55,0x9a,0xed,0x06,0xf1,0xfb,0xf4,0x5d,
+  0x98,0xdd,0x25,0x45,0x11,0x4f,0x1e,0xa1,0x3b,0x42,0xd6,0xe1,0x02,0x33,0xff,0xb3,
+  0x51,0xbf,0xcc,0xb2,0x54,0x1e,0xcf,0xf2,0x95,0x9c,0x5a,0xd4,0xe3,0x2f,0x04,0x3f,
+  0xb1,0x97,0x67,0x76,0xf9,0xff,0xa2,0xb4,0xe6,0xdb,0x07,0x11,0x51,0xab,0xbe,0x04,
+  0xfe,0x89,0xcf,0xb7,0x84,0x2d,0x78,0x9a,0x84,0x92,0xd3,0x72,0x30,0x7d,0x85,0xf4,
+  0x24,0xc2,0x80,0x85,0x46,0x3c,0x48,0xb1,0x07,0xea,0x9e,0x4d,0xc1,0x3f,0x99,0xc6,
+  0xfa,0x58,0x5c,0xf8,0xc9,0x1b,0xf9,0x42,0x4d,0x26,0x0e,0xd6,0xc2,0x61,0x8f,0xcb,
+  0x33,0x92,0xde,0x56,0xcd,0xeb,0x73,0x6f,0x30,0x77,0x38,0x59,0x11,0x6f,0x0a,0x2c,
+  0xf2,0xfb,0xf3,0xb2,0xa3,0x9c,0x07,0xaa,0xdf,0x06,0xf7,0xf1,0x69,0x3c,0x03,0x0a,
+  0x15,0x19,0x73,0x86,0xc4,0x24,0xff,0x21,0xfb,0x05,0xcf,0xff,0xa9,0x62,0x59,0x3e,
+  0x83,0x2d,0x13,0x15,0xfd,0x0e,0x32,0xa2,0x21,0x6c,0x06,0x04,0x7e,0x97,0xe2,0x19,
+  0xbf,0xe2,0xf0,0x8c,0x04,0xde,0x10,0x8c,0xfc,0xb1,0x08,0x8f,0xfe,0x04,0xfe,0xc4,
+  0xe7,0xfb,0x44,0x17,0x8b,0x38,0x4a,0x79,0x7d,0xf7,0x97,0xc2,0x80,0xef,0xe7,0x2a,
+  0x9a,0xba,0xd7,0xe4,0x3f,0xab,0xb3,0x3e,0x90,0x7b,0xee,0x89,0x6a,0x2d,0x3a,0x2a,
+  0xfa,0x10,0xb7,0xbf,0x74,0xfb,0x23,0xbc,0x50,0xab,0x31,0x80,0x2b,0x26,0xaf,0x36,
+  0xe1,0x1f,0x23,0xff,0x39,0xc3,0xd9,0x8b,0xf8,0x47,0x4f,0x67,0xda,0x0a,0x5d,0xce,
+  0x27,0x19,0x92,0x1f,0x1c,0xf8,0xbe,0x08,0x6c,0x98,0x07,0x07,0x42,0x4a,0x7f,0xd8,
+  0x38,0xfe,0xd9,0xc7,0x69,0x5d,0x01,0x81,0x56,0xa8,0xd5,0xa1,0xb6,0xd2,0xd3,0xc0,
+  0xef,0x4f,0xda,0x78,0xe9,0xfd,0xbe,0x85,0xa6,0xfa,0xf7,0x5c,0xee,0xf4,0xab,0xea,
+  0x5d,0x72,0xa2,0x66,0x54,0x3f,0x0a,0x55,0xf5,0xb6,0xa1,0x9c,0xd9,0x68,0xfa,0xef,
+  0xd0,0x97,0xec,0xac,0x19,0x81,0x8c,0x96,0x79,0x74,0xc9,0xda,0x6f,0x25,0xf1,0xcf,
+  0x29,0x16,0xc7,0x3f,0x83,0x1b,0x4f,0xc3,0x8b,0xfc,0x34,0x45,0x63,0xb4,0x12,0xb1,
+  0xc6,0x79,0x97,0xe9,0xcd,0x11,0x9b,0x97,0x24,0xf1,0x8f,0x51,0xff,0x3e,0xa9,0xf2,
+  0xd5,0xc5,0xc1,0x9a,0xa8,0x74,0x10,0xba,0xfb,0xad,0x85,0xe2,0x4c,0x38,0x58,0xed,
+  0x66,0xce,0x55,0xb2,0x93,0x45,0x3c,0x06,0xff,0xbc,0x89,0xff,0x59,0x72,0x4a,0x7b,
+  0x61,0xd6,0xa8,0x65,0x63,0xf6,0xfb,0x5a,0x2b,0xb8,0xcf,0xd3,0x17,0x48,0x11,0xf1,
+  0x9f,0x28,0x63,0x74,0x95,0x25,0x83,0xb4,0x0c,0xe0,0xf3,0xff,0xda,0xf3,0x45,0xaa,
+  0xff,0x07,0x50,0xc8,0x80,0x32,0x92,0xdd,0x08,0x85,0x51,0x5a,0x99,0xfd,0x75,0xd6,
+  0x88,0x82,0x3a,0xa3,0x1c,0xcd,0xf6,0x0e,0xb6,0x42,0x91,0xcb,0x53,0xfb,0x5f,0x28,
+  0xbb,0x1a,0x8b,0xa3,0xdf,0xf9,0x71,0xf6,0xbb,0xb0,0xaa,0x31,0xbf,0xcb,0xb1,0x92,
+  0x5c,0xe7,0x5b,0x15,0x9a,0xee,0xa3,0xb7,0x91,0x4a,0xdf,0x33,0x9b,0x1e,0x50,0xe5,
+  0xbf,0x23,0x97,0x12,0xf6,0x5d,0xbd,0x51,0xff,0x5e,0xd1,0x37,0x30,0x7b,0xc6,0x80,
+  0xaa,0xc3,0xce,0x11,0xab,0x4b,0x74,0x6a,0xaf,0xb2,0x39,0xe0,0x9c,0x2e,0x5a,0xe1,
+  0x74,0x2e,0x1a,0x56,0x45,0x4d,0xe6,0xfe,0x17,0x7c,0x7d,0x16,0x1c,0xb3,0x9d,0xfd,
+  0xc6,0x25,0xb8,0xc4,0xaa,0x9a,0x6d,0x67,0xe5,0x4b,0xda,0x97,0x50,0x55,0x68,0xdb,
+  0x22,0x9e,0x94,0xde,0xcb,0xae,0xf2,0xd8,0x46,0x6b,0x06,0x13,0xf8,0xa7,0x2b,0x0d,
+  0xd1,0x94,0xe0,0x1e,0x5e,0x1c,0xcc,0x71,0x4a,0x87,0x84,0x6e,0x01,0x0f,0xa6,0xd1,
+  0xd6,0x41,0xaf,0x08,0x8b,0xdb,0xc8,0x00,0x7b,0x38,0xb0,0x44,0x37,0xc7,0xbf,0x26,
+  0x23,0xc8,0x91,0x6e,0x8d,0xdc,0xd5,0x90,0x3d,0x95,0xae,0xe1,0xd6,0x93,0xcb,0x50,
+  0xc4,0xf9,0x3c,0xed,0xb9,0x02,0x0d,0xab,0xfb,0x9b,0x65,0x2f,0x49,0xf2,0x3f,0xeb,
+  0xf0,0x34,0x59,0x6f,0x78,0x7b,0xfc,0xd3,0xe0,0x59,0x96,0xaf,0x22,0xda,0xf9,0x2e,
+  0x87,0x3d,0x21,0xba,0x14,0x81,0x5f,0x88,0x47,0xc4,0x28,0x49,0xf2,0xbb,0xd6,0xe7,
+  0x0e,0x20,0x5a,0x2e,0xec,0x6d,0x29,0xf7,0x5b,0xc1,0x1f,0x54,0xcb,0xf1,0xfe,0xbc,
+  0x03,0x66,0x61,0x27,0xfd,0x25,0x1e,0xb4,0xc6,0x7c,0x35,0x2a,0x07,0x3d,0xdf,0xb9,
+  0xa6,0xfe,0xdd,0xcd,0xac,0x43,0xb2,0xc3,0x7a,0x84,0x94,0x76,0xdb,0x42,0x72,0x3d,
+  0x39,0x88,0x98,0x8b,0x7e,0x24,0xf6,0xb0,0x23,0x01,0x77,0x17,0xee,0x90,0x47,0xff,
+  0x95,0xfe,0x17,0x05,0x3a,0xb9,0x64,0x0c,0x6e,0xd9,0x42,0x46,0xab,0x6f,0x83,0x9b,
+  0x59,0xac,0x3f,0x2c,0xd8,0x56,0x35,0x6d,0x4c,0xfa,0x1f,0x94,0x58,0x34,0xc4,0xc6,
+  0xdb,0x5e,0xf4,0x72,0x36,0xa4,0x20,0x99,0x6e,0x44,0xc4,0x16,0x6f,0x12,0x67,0xb0,
+  0x03,0x52,0xa5,0x36,0x29,0x68,0xe2,0x7f,0x0e,0xc5,0xf2,0x7f,0x38,0x69,0x4f,0x21,
+  0x31,0xd2,0x4e,0x14,0x92,0xc6,0x5a,0x96,0x75,0x68,0x81,0xa0,0x65,0x86,0xf0,0x96,
+  0xb7,0xa4,0x7f,0x51,0xbb,0x45,0x15,0x26,0x3e,0x70,0xb9,0x81,0x97,0x78,0xd9,0xbb,
+  0x65,0xba,0xf4,0x6b,0xb0,0x73,0x36,0xbf,0x9d,0x86,0xff,0xa7,0x2e,0x98,0x6d,0x48,
+  0x24,0x4d,0xde,0xe0,0xbf,0x36,0xff,0xc7,0x28,0x7b,0x9f,0x82,0xab,0x1d,0xe2,0x85,
+  0xf0,0xbf,0x20,0x86,0xff,0x27,0xdb,0x3f,0x09,0x1a,0x35,0xa7,0xd6,0x66,0xe6,0x7f,
+  0xee,0xa1,0x6a,0xac,0xda,0x8b,0xc7,0xbf,0x06,0xd0,0xda,0x92,0x51,0xb5,0xa2,0x16,
+  0x2f,0x05,0xa7,0xbf,0x46,0x25,0xad,0xbc,0xfe,0x91,0xd5,0xfc,0x36,0x05,0xff,0x7c,
+  0x0e,0x15,0xde,0xf5,0xf7,0xd6,0xbc,0x06,0x67,0x79,0xfe,0xcf,0x26,0xf1,0xfb,0x30,
+  0xee,0xa9,0xf0,0xde,0x7c,0x4f,0xd3,0xf9,0xf4,0x58,0x21,0x58,0x41,0x92,0xff,0xb9,
+  0x3d,0xed,0x3c,0x39,0x00,0x55,0x1e,0xa7,0xb7,0xa9,0x2c,0x74,0xb8,0xab,0x74,0xa1,
+  0x75,0xa9,0x58,0xc6,0x5e,0x63,0x55,0xf5,0xd6,0xe3,0x4d,0xb7,0xe2,0x79,0x44,0xfc,
+  0xf0,0xa6,0x58,0x92,0x92,0xff,0x13,0x20,0x3c,0xfe,0x9e,0x9d,0xaf,0xb4,0x6a,0x45,
+  0x79,0x56,0x46,0x42,0x10,0x50,0x50,0xad,0x77,0x58,0x54,0xd6,0xa3,0xd9,0x21,0xf3,
+  0x19,0x3c,0x38,0x09,0x8b,0x21,0xad,0x5f,0x6a,0xcc,0xe0,0x6c,0xcf,0x45,0x92,0x8a,
+  0x78,0xcf,0x43,0xaf,0xf3,0xa7,0xf1,0xfc,0xe7,0xda,0x99,0x8a,0x05,0x97,0xc2,0xf1,
+  0x02,0xbe,0x78,0x6a,0xfc,0x0b,0x5a,0x48,0x89,0xee,0x08,0xfa,0x79,0xda,0x67,0x51,
+  0xf5,0x9d,0x41,0xd2,0xc9,0x38,0x11,0x62,0x46,0xd0,0x52,0x58,0xb8,0xdb,0xf7,0x43,
+  0x6f,0x46,0xd0,0x93,0x9e,0xfc,0x5e,0xb9,0x9d,0xb1,0x6e,0x26,0x41,0x79,0x0e,0x39,
+  0xe0,0x31,0x68,0x7f,0x0a,0x11,0xdf,0x56,0x7a,0x33,0x37,0x89,0x5f,0x87,0x71,0xad,
+  0x5c,0xb3,0xfe,0x5a,0x76,0x24,0xee,0xdf,0x6a,0xe0,0x1f,0x3c,0x74,0xd9,0x22,0x4f,
+  0x14,0xdf,0xb7,0x1c,0xed,0xf7,0x33,0xbc,0xfe,0x5d,0xcb,0xba,0x41,0x3c,0xa3,0x9d,
+  0x45,0x43,0xfb,0x9a,0xfe,0x17,0x06,0xfe,0x51,0x17,0x37,0xcb,0xc0,0x22,0x5a,0x37,
+  0xb1,0x05,0x44,0x1f,0x44,0xa8,0x5b,0x71,0xae,0x96,0xf3,0x61,0x4c,0x35,0x3e,0x8d,
+  0xc9,0xff,0xd3,0x4c,0x8d,0xb2,0x77,0xfa,0xa1,0x7f,0x3e,0xac,0x86,0x82,0xa0,0xfc,
+  0x11,0x6f,0x0b,0x1b,0xca,0x37,0xfa,0xc3,0xc2,0x7e,0xcd,0x1f,0x90,0xa3,0x24,0xa9,
+  0x5f,0x26,0xf2,0x9f,0x03,0x4a,0xb6,0xa5,0xd6,0x0f,0xaa,0x2a,0x77,0x91,0x07,0x35,
+  0x56,0xab,0x32,0xb4,0xc7,0x25,0xc7,0x76,0x56,0x18,0x91,0xdb,0x37,0x26,0xf1,0x4f,
+  0xbe,0x30,0x95,0xee,0x52,0x8b,0x07,0x03,0xde,0xec,0x3c,0xb6,0x1a,0xf2,0x15,0xde,
+  0xb6,0x86,0x03,0xa1,0x46,0x3c,0xbf,0xb9,0x85,0x2f,0x69,0xd3,0x75,0xb9,0xf6,0x1a,
+  0xff,0xcf,0x97,0xd1,0x8a,0xa8,0x73,0xa9,0x38,0x0f,0xfa,0xd8,0x6c,0x9f,0xad,0x5e,
+  0x7c,0x98,0xf4,0xb3,0x70,0xc8,0xca,0xf3,0x7f,0xae,0xb0,0x97,0x78,0x22,0x90,0x25,
+  0xc9,0xff,0x7c,0x53,0xcc,0xfe,0x9a,0x14,0x14,0x87,0x3d,0x7b,0x50,0xf1,0xdd,0xcc,
+  0xf3,0x09,0x71,0x05,0xd8,0xdf,0x73,0xfe,0xc3,0x2b,0x30,0x6f,0xd0,0x16,0x2d,0x48,
+  0xf5,0xff,0x5c,0x65,0x95,0x85,0xd6,0x95,0x35,0x2f,0x2c,0x3c,0xd2,0x58,0xb9,0xdc,
+  0x39,0x26,0xfe,0x0c,0x06,0x98,0xa1,0xd6,0xa7,0x69,0x9f,0xb0,0x1f,0x9d,0xb7,0x9d,
+  0x98,0x94,0x67,0x8a,0x7f,0x19,0xf6,0x97,0xc3,0xe1,0xf5,0xdc,0xc0,0x56,0xe7,0x95,
+  0xd4,0xd3,0x51,0xf2,0x0b,0xce,0x3f,0xd6,0x4c,0x1f,0xc5,0x17,0xf9,0x9f,0x90,0xdf,
+  0x28,0x6b,0xe9,0x49,0xfe,0xe7,0x0d,0x46,0xfc,0xcb,0x49,0x11,0xed,0xb4,0x6b,0xab,
+  0xa1,0x38,0x92,0x81,0xaf,0x89,0xf3,0x55,0x96,0x61,0xcf,0x9e,0xa3,0x36,0xc3,0x74,
+  0xad,0xcd,0x4b,0xfa,0x4d,0xfd,0x2f,0x06,0x14,0x5c,0x4f,0x81,0x0a,0xa4,0x8b,0xf8,
+  0xf3,0x9d,0xbc,0x91,0x41,0x33,0xa2,0x96,0xd0,0xda,0x8c,0xb0,0x85,0xc2,0x53,0xac,
+  0x10,0xe4,0x22,0x13,0xfe,0x71,0x4c,0xd9,0xa6,0x5c,0xc5,0xf7,0x5d,0xbc,0x29,0xa7,
+  0x8b,0x1c,0xec,0xaf,0x1c,0xcc,0x0c,0x15,0x38,0x89,0x0e,0xee,0x60,0x31,0x5a,0xdc,
+  0xf0,0x61,0xe0,0x65,0xc5,0xb6,0x59,0x4e,0xe2,0x9f,0xe0,0x44,0xfc,0x2b,0x28,0xfc,
+  0x80,0x3b,0xca,0xd2,0xd1,0xcc,0xff,0x0d,0x19,0x33,0xda,0x5e,0x88,0x51,0x65,0xbc,
+  0x6e,0x9e,0xba,0xa4,0x91,0x24,0xfb,0xbd,0x6e,0x88,0xe5,0x3f,0x37,0xd8,0x06,0xb7,
+  0xd6,0xc3,0x11,0x69,0xb6,0x4e,0x4f,0x8b,0xcb,0xd1,0x7e,0x99,0xcd,0xa6,0xbe,0x25,
+  0xba,0xd4,0xb7,0x61,0x6e,0xba,0x2d,0x4c,0xa2,0x26,0xfc,0xb3,0x02,0x5e,0x41,0xfb,
+  0xa2,0x6d,0x9a,0x67,0x9e,0xd2,0xca,0x69,0x7c,0xc6,0xc8,0xd7,0x20,0x10,0xe9,0x60,
+  0xb4,0xa7,0x48,0x24,0x5d,0xcc,0x9e,0xd7,0xb6,0xd6,0x3f,0xa4,0x99,0xf0,0x4f,0x4c,
+  0x5f,0xb7,0x93,0x92,0xf4,0xa7,0xc0,0xbe,0xcc,0x12,0xc6,0xd3,0x19,0xe0,0x8d,0x57,
+  0x42,0xe4,0x16,0xe9,0xc9,0x80,0x1d,0x7f,0x4a,0x8f,0xa6,0xf8,0x7f,0x70,0x7d,0x08,
+  0xca,0x1f,0x28,0xf4,0x43,0xc8,0x52,0xc4,0x8f,0x21,0x53,0x1c,0xcc,0xe1,0x46,0x7b,
+  0x24,0xc4,0x89,0x02,0x72,0x3d,0x49,0xfb,0x8b,0x51,0x03,0xff,0xd4,0xd9,0x82,0xb2,
+  0xc3,0x7f,0x90,0xb8,0x4f,0x64,0x85,0x73,0x9c,0x24,0xa2,0xcd,0x63,0x14,0x0d,0x01,
+  0xe9,0x2d,0xce,0xaf,0x8b,0x82,0x37,0x3d,0x19,0xff,0xba,0xa4,0xf0,0xf8,0xd7,0x12,
+  0xc4,0x33,0x28,0x9d,0xab,0x5a,0x33,0x79,0x61,0xc5,0x65,0x75,0x2e,0xb3,0xed,0xe4,
+  0x8a,0x9e,0xbc,0x02,0x36,0xbd,0x60,0xf8,0x1b,0x13,0xf2,0xc4,0xdc,0x8f,0x6f,0x8d,
+  0xeb,0x3f,0x40,0x3f,0x3e,0xd3,0xfd,0x27,0xb9,0xfe,0x9a,0xfb,0x4f,0x64,0x0a,0x59,
+  0x23,0xc6,0xa0,0xd4,0x9e,0xb8,0x02,0xb4,0xc9,0xad,0x0e,0xf0,0x9f,0x74,0xd3,0xfc,
+  0xff,0xb7,0xfa,0x21,0xc6,0xff,0xa3,0xa5,0xe6,0x6b,0x3c,0xe3,0xec,0xda,0x79,0xff,
+  0x4a,0x1b,0xc4,0xaf,0x7c,0x88,0xff,0x17,0xd7,0xff,0xdf,0xe8,0x87,0x08,0xc9,0x2b,
+  0xda,0x57,0xfb,0x21,0x0e,0xf0,0xe4,0x1d,0x7d,0x8d,0x2b,0x3e,0x30,0xdf,0x3f,0x76,
+  0x25,0x75,0xfd,0x1b,0xc1,0xa0,0x03,0x93,0x26,0x06,0xa6,0x85,0x8c,0x5d,0xb9,0x66,
+  0xfd,0xf3,0xf9,0x6f,0xf1,0xa7,0xe5,0x03,0xd3,0xfa,0xc7,0xaf,0x24,0x17,0xc7,0xe8,
+  0x87,0x38,0x60,0xac,0x7f,0x7c,0xb5,0x53,0xbe,0x7e,0xec,0xef,0xff,0xf6,0x43,0xfc,
+  0xf7,0x07,0xff,0x5f,0x9e,0x4f,0x9a,0xa5,0xd8,0xa1,0xf3,0xa4,0x1e,0xcc,0x1f,0xfd,
+  0x5b,0xe7,0x31,0x0d,0x0f,0x5d,0x5a,0x35,0x28,0xec,0xaf,0x3c,0x8f,0xab,0xf9,0xa6,
+  0xf5,0x88,0x5f,0x39,0x86,0xf6,0x7f,0x4b,0x1e,0x5a,0x05,0x20,0x78,0x13,0x2d,0xf5,
+  0xb6,0x3f,0xfa,0x37,0xe5,0xa1,0x85,0x97,0x28,0xdb,0x51,0x09,0x4d,0x88,0xc1,0xaf,
+  0x0c,0x52,0xde,0xd7,0x70,0x3a,0x0a,0x54,0xf3,0x7f,0x55,0xb0,0x11,0x85,0x35,0x7f,
+  0x55,0x1e,0x4a,0x2a,0xa5,0x44,0x04,0xfd,0xab,0x62,0xd0,0xaf,0xf0,0xbc,0x86,0xaf,
+  0xca,0xc3,0xf8,0xac,0xaf,0xfc,0xfd,0x6b,0xf2,0x30,0x7b,0x8d,0x73,0x0b,0x0f,0x87,
+  0x4f,0xed,0xc3,0xd5,0x1e,0x98,0x58,0xff,0x01,0xb3,0x3c,0x4c,0x91,0x27,0x30,0x49,
+  0xc1,0xf5,0xf7,0xfc,0xf5,0xf2,0x70,0x8d,0x9a,0x0f,0xd6,0xea,0x49,0x7f,0xbd,0x3c,
+  0x74,0x26,0x84,0xde,0x5f,0xd3,0x1f,0x56,0x45,0x63,0x02,0xac,0x35,0xa2,0x97,0xfd,
+  0x75,0xfa,0x2e,0x9b,0xf0,0xf5,0x23,0x19,0xe0,0xf9,0xeb,0xf4,0x91,0xc2,0x45,0xa4,
+  0x55,0x14,0x81,0xfd,0x95,0xfd,0x61,0x05,0xfe,0x70,0xe2,0xbf,0xba,0xfe,0x13,0x7f,
+  0x66,0x79,0xc8,0x73,0x09,0xb4,0x7f,0x7b,0xea,0x35,0x7f,0x15,0x15,0x28,0x70,0x19,
+  0x5c,0xb3,0xc4,0xd7,0xfe,0x99,0xe5,0x21,0x59,0x4a,0xfe,0xfa,0xdb,0xf3,0x3f,0x7c,
+  0x21,0xf6,0xbf,0x31,0x3d,0x57,0xc8,0xce,0x77,0xfd,0xaf,0xa7,0x25,0xfe,0xfe,0xa3,
+  0xc9,0x9f,0xff,0x60,0xf3,0x5f,0xab,0x16,0x1b,0xb4,0x93,0xca,0x5c,0xc8,0xec,0x35,
+  0x06,0xff,0x3d,0x37,0xf3,0x35,0xf1,0xa1,0xea,0xfb,0xbc,0x73,0x8d,0x81,0x36,0xb5,
+  0xe1,0x6b,0xd2,0x64,0x7d,0x76,0x62,0xfe,0xed,0xb5,0x69,0x0f,0x09,0xf7,0x69,0x7f,
+  0xab,0x40,0xbf,0x31,0xf0,0x2a,0x53,0x8c,0x81,0xef,0x6f,0x71,0x20,0xe4,0x1b,0x3f,
+  0xa5,0xe9,0xb3,0x27,0xf0,0x2a,0x34,0x7b,0x04,0x95,0xd5,0xa9,0xd9,0x14,0xfa,0x62,
+  0x83,0x3c,0xc9,0x1f,0xbf,0x22,0xad,0x16,0xf2,0x63,0x03,0x96,0xfc,0xa0,0x0c,0x04,
+  0x1f,0x2c,0x85,0xeb,0xe0,0x7f,0x32,0x63,0x70,0x2f,0x4d,0x5b,0x2d,0xdc,0xcf,0x96,
+  0x6a,0xd7,0x29,0x69,0x78,0x45,0x58,0xaa,0x7d,0x1b,0xd2,0x12,0xe1,0x68,0x7c,0xfe,
+  0xa5,0x69,0x65,0xc2,0x5d,0xec,0x5b,0xd5,0x52,0x20,0xed,0x61,0xe1,0x3e,0xfd,0x6f,
+  0xd5,0x29,0x91,0xb4,0x87,0xe1,0x3e,0xf6,0xb7,0xce,0x29,0x07,0x85,0x7b,0x84,0xfb,
+  0xd8,0xb7,0xd4,0x5c,0xd3,0xf3,0xbc,0xa6,0x69,0xaa,0x42,0x25,0x22,0x00,0xef,0xf0,
+  0x99,0x07,0xe9,0x20,0x30,0x25,0x3e,0x58,0x25,0xf9,0x58,0xec,0x4a,0xf2,0x7d,0x5f,
+  0xab,0x93,0x96,0x09,0x79,0xec,0x0e,0x80,0x80,0x64,0x17,0x28,0xf3,0xa8,0x4a,0x40,
+  0xc2,0x53,0xce,0x07,0xcd,0x92,0x2a,0x50,0x3c,0xd7,0x8a,0x79,0xfe,0xc2,0xb4,0x7b,
+  0x1a,0xef,0x0d,0xfd,0x0d,0x95,0x68,0x9a,0xa7,0xd1,0x3b,0x2a,0x39,0xa6,0x58,0xd2,
+  0xb4,0x46,0x6f,0xe8,0xde,0xf2,0x29,0x62,0x9a,0xc6,0xbc,0xea,0x94,0xa9,0x53,0xb4,
+  0xe4,0xf3,0xb0,0xa9,0xc2,0xdf,0xc2,0xdf,0xe8,0x53,0xbc,0xa8,0x06,0xf8,0x60,0x72,
+  0x43,0xda,0x7d,0xc2,0xb7,0xd8,0xbd,0xfa,0x14,0x17,0x0e,0x44,0xc0,0x41,0xb9,0x94,
+  0x30,0xbf,0x70,0x3e,0xae,0x1d,0x64,0x83,0x14,0x02,0xee,0xf4,0x50,0x34,0x81,0x8b,
+  0xc0,0x1a,0x2e,0x0b,0x15,0x41,0x42,0xa8,0x85,0x6a,0x4a,0x81,0x6a,0xd3,0xfa,0xf8,
+  0xb8,0xa3,0x1a,0xcd,0x0e,0x30,0x3c,0xd6,0x80,0x86,0xb2,0x1a,0xbf,0x42,0xd5,0xf4,
+  0xf8,0x4f,0xd5,0xa6,0xf5,0xf1,0x66,0x2c,0x17,0xfe,0x0e,0xbe,0xad,0x15,0xb2,0xb4,
+  0xe5,0x69,0x7c,0x30,0x25,0x98,0xe6,0x23,0x27,0xe0,0xdb,0x80,0x03,0x55,0x38,0x01,
+  0xff,0x04,0x0b,0xcc,0xef,0xab,0x89,0xbc,0x51,0x6a,0x99,0x2a,0xb1,0xd8,0x80,0x87,
+  0x32,0x96,0xe1,0x60,0x86,0x31,0x10,0x96,0xb2,0xeb,0xf0,0x7b,0x99,0xf6,0x8f,0x47,
+  0x72,0xf5,0x5a,0xd5,0x1a,0x9a,0xe7,0x97,0x5c,0x8d,0x7c,0xa0,0xf4,0x49,0x2e,0xdd,
+  0xaa,0x56,0x53,0xe5,0x55,0x88,0x5d,0xc9,0xd3,0x27,0x27,0x9e,0x07,0xb8,0xc4,0xb2,
+  0xc6,0xe4,0x5b,0x7c,0xa0,0x4f,0x0c,0x22,0xb1,0x81,0xaa,0x99,0x36,0x35,0x23,0x82,
+  0x4b,0x5f,0xac,0xe6,0x50,0xdc,0x66,0x2e,0xc6,0x07,0xb5,0x7d,0x82,0xab,0xd1,0xb8,
+  0x72,0x90,0xff,0xe4,0xfa,0x96,0x53,0xd2,0x4d,0xeb,0xe3,0x49,0xf3,0x35,0x2e,0x55,
+  0xbf,0x8d,0xf3,0xe3,0x83,0x29,0x38,0xe8,0x35,0x06,0x4d,0x82,0xda,0xbb,0xd4,0xf5,
+  0x6d,0xeb,0x14,0xf3,0xfe,0xf1,0x18,0x2b,0x97,0x58,0xc2,0xf8,0x40,0x32,0x06,0x92,
+  0xca,0xac,0xaa,0x48,0x85,0xd4,0xf7,0xf5,0x35,0xe6,0xa9,0x77,0xe0,0x47,0xc3,0xc1,
+  0xf5,0xea,0x1d,0x74,0xb2,0x5f,0x5a,0x8e,0xaf,0x79,0x47,0xdd,0xe4,0x8d,0x92,0xca,
+  0xdf,0xb7,0x2e,0x65,0xff,0xf8,0xd2,0x96,0x0a,0xdf,0x86,0xbf,0x61,0x69,0x3e,0x29,
+  0x36,0x98,0x82,0x57,0xa4,0x3b,0xe0,0x76,0x3e,0xa0,0xc2,0x1d,0x30,0x99,0x49,0xa6,
+  0xfd,0xd3,0x9b,0x2e,0x3c,0xc4,0xee,0xf5,0x4d,0x69,0x4f,0xbb,0x43,0xa8,0x66,0x5e,
+  0x5f,0x6e,0x9e,0x90,0x8e,0x03,0x65,0x62,0xc0,0xaf,0xa4,0x25,0xcc,0x7d,0x3c,0x8f,
+  0x5c,0x8d,0x50,0x54,0x01,0x4a,0x36,0x1e,0x81,0xea,0xd8,0x59,0x90,0x18,0x1e,0x8a,
+  0x3a,0x89,0x5f,0xe1,0x83,0xdc,0xa4,0x7b,0x09,0x5e,0xbb,0x83,0x4c,0x66,0xcd,0xbe,
+  0x7c,0x85,0xde,0x21,0x7e,0x93,0x1d,0xf7,0xdd,0x9a,0x97,0xc9,0x07,0xf7,0x1a,0x83,
+  0x49,0xf1,0x2b,0xa6,0xe7,0x79,0x2d,0x3d,0xed,0xa1,0x46,0x94,0x06,0x79,0x53,0x5e,
+  0x97,0x62,0x83,0xb4,0xd7,0x13,0x57,0x70,0x70,0xd2,0xf7,0xdf,0xf3,0xa6,0x98,0xe5,
+  0xc9,0x1d,0xe2,0x43,0x6c,0xb3,0x6f,0x2e,0x4e,0x23,0x7c,0xf0,0xdf,0xf3,0x32,0x5e,
+  0xc7,0x2b,0xf7,0xe1,0x95,0xcc,0xd7,0x27,0x3d,0xc4,0xa6,0xfa,0xbe,0x86,0xf3,0x27,
+  0x9b,0xe6,0xc7,0xee,0xb6,0x94,0xa6,0xdc,0xd6,0x6a,0x0c,0x94,0xd9,0x38,0xa8,0xe1,
+  0xf3,0x4d,0xfb,0x47,0x50,0x81,0x9f,0x98,0xb4,0x84,0xd8,0xe1,0x83,0xfb,0x8c,0x01,
+  0xf0,0xc1,0xd7,0x50,0xfe,0x98,0x76,0x5b,0xfa,0x64,0x94,0x36,0xbe,0xeb,0xf2,0x62,
+  0x62,0xc7,0xf7,0x6d,0x63,0xd0,0x18,0xbb,0x92,0x96,0xdf,0xc8,0xaf,0x4c,0x31,0xcd,
+  0xbf,0x5d,0x4b,0x73,0x09,0x8b,0xc9,0xb7,0x40,0x62,0x69,0x0d,0xc2,0x7d,0xf0,0x35,
+  0xc8,0xd5,0x8d,0xc1,0xdf,0xc2,0x14,0x1d,0x7f,0x8a,0x0d,0x92,0xcf,0x73,0xbb,0x69,
+  0xff,0xa0,0xb4,0x51,0xa5,0x89,0x41,0x3a,0x15,0xf8,0xf3,0x18,0x03,0x66,0x7a,0xdf,
+  0xf8,0xfe,0x31,0x76,0x57,0x23,0xff,0x87,0x93,0x63,0x03,0x0f,0x55,0xfc,0xf8,0x13,
+  0x1f,0x78,0xcd,0xf3,0x6b,0xd2,0xbc,0xbd,0xf7,0xba,0xfe,0x86,0xae,0x22,0x5c,0xec,
+  0xa8,0xb9,0xd6,0x29,0x1e,0x49,0x6b,0xf6,0xaa,0xf7,0xd2,0x29,0xa2,0xe0,0x45,0xf9,
+  0x93,0x4b,0xd3,0xc0,0xb4,0x3e,0x62,0xbe,0x37,0x72,0xaf,0x6b,0x0a,0x95,0xf0,0x57,
+  0xfd,0x5e,0x75,0x8a,0x35,0xad,0x86,0x0f,0x5c,0x38,0xf0,0xc4,0x06,0x34,0x4d,0x33,
+  0xad,0x0f,0x68,0x9a,0xa2,0x48,0x92,0xa0,0xc4,0x24,0x1f,0x82,0xa6,0xf8,0x40,0x45,
+  0x41,0x14,0x1b,0x4c,0x36,0xcd,0xbe,0x7d,0x21,0x21,0x8c,0x85,0xd4,0xba,0x76,0x3f,
+  0x02,0x21,0xa6,0xaa,0x0e,0x4a,0x62,0x03,0x04,0x99,0xe9,0xf1,0x81,0xe9,0x79,0x6e,
+  0xd7,0xb8,0x90,0x47,0x69,0x93,0x8b,0x27,0x40,0xe0,0x8a,0x60,0x0a,0x0e,0xc0,0x90,
+  0x3f,0xfc,0x0a,0x97,0x3f,0x53,0x4c,0xef,0xbb,0x4a,0x13,0xf9,0xaf,0xd7,0xc1,0x49,
+  0x26,0xc6,0xe4,0x4f,0x1a,0xcb,0xf6,0x49,0xf7,0xc5,0x04,0x91,0x0f,0x8c,0x2f,0x62,
+  0xfe,0xbe,0x90,0xeb,0x12,0xb8,0xf4,0x60,0x4c,0xe2,0x03,0x14,0x9d,0x3a,0x0e,0xf2,
+  0x8c,0x81,0xa2,0xe2,0xe0,0x8e,0x54,0x28,0x25,0xc5,0x84,0x8c,0x86,0x17,0x67,0x83,
+  0x55,0xc3,0xc1,0x71,0x98,0x03,0x19,0x60,0x0c,0x0a,0x71,0x40,0xb4,0x94,0xf9,0x69,
+  0xc2,0x6c,0x6d,0xb1,0x37,0x27,0xb8,0x69,0x15,0x1f,0x68,0x62,0xae,0xf4,0x9a,0x30,
+  0xfb,0x76,0xbc,0x92,0x2b,0xbd,0x2e,0xcc,0xae,0x5e,0xec,0xfd,0x96,0x52,0x6b,0x9e,
+  0xff,0xf5,0xb4,0xfa,0xde,0xef,0xb8,0xbe,0x1d,0x48,0xdb,0x8a,0x83,0x1b,0x5c,0xf7,
+  0xac,0x9d,0xf2,0x5c,0xec,0xca,0xda,0x29,0x5b,0x85,0xf8,0xc0,0x3c,0x3f,0x23,0x06,
+  0xf4,0xf9,0x7f,0xd4,0x48,0x6a,0xf4,0x19,0x4d,0xc5,0x8c,0xc7,0xd8,0x24,0xfd,0x2b,
+  0xcf,0x03,0xcb,0x7d,0x93,0xf3,0xa4,0x3b,0x04,0x08,0xd4,0x72,0x45,0xe6,0x11,0x26,
+  0x07,0xa4,0x65,0x93,0xf3,0x9a,0xef,0xc8,0x9f,0xcc,0x6a,0x27,0x06,0xe6,0xf9,0xb7,
+  0x7b,0x27,0xdf,0x2b,0xdd,0x8e,0xa8,0x32,0xcd,0x3b,0x39,0x57,0xfa,0x1b,0x61,0x8a,
+  0x76,0xbb,0x17,0xee,0x95,0xfe,0x06,0x26,0x6b,0x1f,0x78,0x5d,0xf7,0x4a,0x53,0xf0,
+  0x8a,0x69,0x3a,0xcd,0xe7,0x7b,0x59,0xc1,0x2d,0xc9,0x83,0xc5,0xfe,0x5c,0x35,0xad,
+  0x4e,0xf0,0x38,0x14,0x96,0x8b,0xba,0x31,0xff,0x1e,0xea,0x6d,0xcd,0x55,0x57,0x99,
+  0x6f,0x6f,0x11,0x78,0x16,0x94,0xd7,0x21,0xf1,0x81,0x16,0x52,0x1c,0xca,0xc4,0x60,
+  0xe2,0x8a,0xd3,0xec,0x7d,0x00,0x2b,0x9e,0xad,0x66,0xfd,0xfb,0xae,0xeb,0x17,0x8b,
+  0xdf,0x82,0xe3,0x7d,0xb7,0xba,0xa8,0x31,0xd0,0x6f,0x75,0x65,0x2e,0x4e,0xcf,0x31,
+  0x06,0x29,0xfb,0x33,0x23,0xed,0xe1,0xea,0xfb,0x82,0x1c,0x06,0x48,0x88,0x07,0xd8,
+  0x37,0x62,0x78,0xe0,0x24,0xe3,0x57,0xa6,0x2f,0x13,0x4e,0xb2,0xff,0x5e,0xf8,0xa4,
+  0x6e,0x9a,0x2f,0x7f,0xc7,0xf3,0x87,0xe0,0x4b,0x9d,0xc5,0x19,0xb7,0x2c,0xc4,0xc1,
+  0xce,0xce,0xe2,0x3b,0xe5,0x7b,0x16,0x0e,0x6e,0x7c,0xa9,0xf0,0x37,0x19,0xb2,0x67,
+  0xe1,0x71,0x63,0x60,0x7e,0x9e,0xf9,0x57,0xef,0xbe,0xfa,0xfb,0x57,0xce,0x7f,0x32,
+  0x5e,0xf5,0x73,0x1c,0xec,0x3a,0xff,0x97,0xf1,0xf9,0x57,0x96,0xbc,0xf7,0xf8,0xd5,
+  0xa1,0xcb,0xe3,0xf3,0x7f,0xb6,0xe4,0xaa,0x31,0x80,0xff,0x83,0xbf,0xca,0x27,0x33,
+  0x66,0x78,0xee,0x0c,0x6e,0x5c,0x3e,0x7d,0xdc,0xf6,0x6c,0xcd,0xd5,0xe0,0xc6,0x9f,
+  0x56,0xfe,0xf3,0x9d,0x3f,0x3f,0x76,0xe7,0xf9,0x27,0x2e,0x57,0x5d,0xbd,0xf3,0xeb,
+  0x7c,0x30,0x64,0x9e,0x5f,0xf5,0xb3,0xbb,0xdf,0x7b,0x7c,0xd7,0xd0,0x27,0x13,0x8f,
+  0xf1,0xc9,0xe5,0x89,0x07,0xc3,0xf9,0x77,0xbf,0x67,0x3c,0xa1,0x79,0x7e,0xc1,0xcf,
+  0xea,0xde,0xdb,0x38,0x77,0x68,0xed,0xfd,0xf3,0xf9,0x3f,0xdc,0x3e,0xf4,0x18,0x3e,
+  0xf6,0xdd,0xef,0xe6,0xf0,0x3b,0x14,0xe4,0xf1,0x41,0xf3,0xc8,0xfd,0xe6,0xf9,0x82,
+  0xa7,0x41,0xdb,0xac,0x7c,0x3d,0x3b,0x43,0x8f,0x0d,0x72,0x33,0x5e,0x4b,0x6f,0xd0,
+  0xa7,0x2a,0x93,0xa4,0x8c,0xd7,0x08,0xe2,0x43,0xbc,0x22,0x98,0xd7,0x53,0x8a,0xe1,
+  0xc3,0xa9,0x71,0x7c,0xc8,0x61,0xe1,0xa4,0x87,0xe0,0x3e,0xed,0x6b,0x0a,0x17,0xd4,
+  0x38,0xa8,0x41,0x7c,0x68,0x9a,0x2f,0x4e,0xe0,0x43,0x43,0x3e,0xbb,0x10,0xda,0xb0,
+  0x24,0x3e,0xe4,0x83,0xaf,0x95,0xa7,0x9e,0xdf,0x18,0x6c,0x53,0x58,0x1c,0xbf,0x71,
+  0xb1,0x79,0xbf,0x71,0x45,0x60,0x70,0xbf,0x94,0x47,0xd2,0x55,0xc1,0x3c,0x9b,0xfe,
+  0xff,0xda,0x39,0xbf,0xd8,0x28,0x8a,0x38,0x8e,0xff,0xe6,0x6e,0xef,0xd8,0x2b,0x77,
+  0x65,0xb7,0xbd,0xc2,0x15,0x9b,0x66,0x8f,0x2b,0x47,0xfd,0x13,0xdc,0x22,0xc5,0x1a,
+  0x4c,0x3b,0xed,0xed,0xb5,0x47,0xd3,0xc2,0x81,0x80,0x40,0x8c,0xb9,0x2a,0x21,0xc6,
+  0x27,0xd0,0x17,0xa3,0x41,0xf6,0xca,0x41,0x8c,0xd1,0xa4,0xa9,0x35,0x96,0x04,0xf5,
+  0x30,0x6a,0x8c,0x81,0xf8,0xe0,0x9f,0x90,0x18,0x93,0x05,0x8d,0x48,0x34,0x29,0x0f,
+  0xf0,0xa2,0x26,0x42,0xe4,0xc5,0xc4,0x84,0x3e,0x90,0x18,0x1f,0xea,0xf9,0x9b,0x99,
+  0xbd,0xee,0x1e,0x44,0x88,0xc8,0xbe,0x98,0xf9,0x3e,0x7d,0xbb,0x37,0x37,0x3b,0x37,
+  0xf3,0xbb,0xdf,0x7c,0x7e,0xdb,0xdd,0xb3,0x9e,0x23,0xf1,0xc9,0x5c,0x18,0xce,0x5b,
+  0xeb,0x48,0x47,0x65,0xc4,0xd0,0xd9,0x43,0x35,0x1d,0x18,0x18,0xfa,0x0f,0x18,0x21,
+  0x68,0x54,0xdd,0x69,0xec,0x3f,0xa5,0x56,0x42,0x7c,0x2b,0x84,0x94,0xc6,0x68,0xd0,
+  0x32,0xc4,0x89,0xca,0xee,0xa9,0x89,0x7f,0x3c,0x2a,0x62,0x21,0x26,0x0d,0x0b,0xf9,
+  0xf0,0x29,0xc6,0x87,0x25,0x6d,0x56,0xd9,0x27,0xcc,0x71,0x25,0x5b,0x8e,0x31,0xe3,
+  0x6f,0xff,0xa0,0x32,0x5a,0x5e,0x5e,0xcd,0xdb,0xda,0x5a,0x65,0x4f,0xb9,0xa5,0x6a,
+  0x7d,0xa4,0xdf,0x07,0x7b,0xce,0xa0,0x39,0xad,0xdf,0x8f,0x2f,0xa1,0x99,0xf5,0xe5,
+  0x4f,0xd5,0x49,0x40,0x2b,0xdb,0x52,0x3e,0x83,0x31,0x4c,0x5a,0xc9,0x0b,0xb0,0x9e,
+  0x8c,0x01,0xee,0x36,0x4e,0xa4,0x8f,0x8c,0x91,0x56,0x58,0xce,0x36,0x19,0xea,0xbd,
+  0xc1,0x89,0x22,0x0b,0x22,0x0d,0x6e,0x85,0x0a,0x05,0xf6,0x98,0x20,0x25,0x1a,0x58,
+  0x98,0xc5,0x94,0x22,0xd1,0xb4,0xa4,0xa2,0x33,0xe3,0xed,0xef,0xaa,0xc3,0xca,0x55,
+  0xcc,0xc2,0x5d,0xe2,0x4a,0x81,0xc6,0x36,0xa4,0x10,0xcb,0x7a,0xac,0x30,0x6b,0x61,
+  0x65,0x9f,0x01,0xd0,0xd0,0x5e,0x29,0x11,0x06,0xc9,0x3c,0xe3,0xa7,0xc8,0x10,0xe3,
+  0x91,0x12,0x99,0x85,0x7d,0x68,0x22,0xcc,0x0c,0x43,0x8f,0xc7,0xf3,0x1a,0xa1,0x98,
+  0xa1,0x66,0x21,0x6b,0x20,0x99,0x71,0x03,0x31,0x61,0xd6,0xa1,0x01,0x66,0xd6,0x00,
+  0xae,0x60,0x5d,0x94,0xf1,0x21,0x87,0x22,0x38,0xec,0xe3,0x43,0xd7,0x70,0x3e,0x1c,
+  0x56,0x1d,0x47,0x5f,0x7c,0x9e,0x11,0xfe,0x89,0x0f,0x43,0x7e,0xa3,0xd5,0x67,0x88,
+  0x2a,0x43,0x60,0x72,0x48,0x83,0xaf,0xeb,0xe6,0xec,0xa2,0xd1,0x84,0xa1,0x1e,0x6f,
+  0xd0,0xfa,0xfe,0x1b,0x87,0x49,0x77,0x23,0xd6,0x3d,0x13,0xe1,0x06,0x3f,0xf8,0xe2,
+  0xfe,0x45,0x09,0xdf,0xdf,0xd3,0x37,0xf2,0xe1,0xe2,0x8e,0xcf,0x8d,0x17,0x0f,0x45,
+  0x72,0xab,0xfe,0x71,0xa3,0xe7,0xc6,0x6b,0x4f,0xf3,0x14,0xd7,0x2f,0x09,0x79,0x28,
+  0xd6,0x8d,0x7e,0xb3,0x19,0x5a,0x1c,0x4f,0x01,0x57,0x6a,0xd0,0x4e,0x96,0x96,0xb0,
+  0x25,0xdb,0x8a,0x58,0xa8,0x20,0x16,0x7a,0x66,0x50,0x18,0x2f,0x7c,0x0a,0xec,0x96,
+  0x12,0xbb,0xce,0x8b,0x36,0x56,0x18,0xa2,0x56,0x72,0x8b,0x26,0x43,0x18,0xf0,0x8d,
+  0x67,0x27,0xd2,0x20,0xf2,0x61,0x11,0x76,0x22,0x28,0x5e,0xe2,0x58,0x18,0x22,0x2e,
+  0x28,0x12,0xe4,0x43,0xda,0x9b,0x8a,0x50,0x6f,0x7f,0x27,0xc3,0x88,0x85,0x1d,0xa5,
+  0x91,0x54,0xfb,0xb7,0xae,0xd1,0x3d,0x13,0xe5,0x66,0x57,0xbb,0xe3,0xf5,0x4f,0x86,
+  0x39,0x16,0xae,0x41,0xba,0x23,0xc2,0xc4,0x58,0xb3,0x9f,0x27,0x98,0x01,0x71,0x24,
+  0xe9,0x2c,0x5e,0x9e,0x28,0xd6,0xf9,0x30,0x05,0x47,0x49,0x4f,0xf9,0x89,0x09,0x86,
+  0x85,0x4b,0x0e,0x94,0xc7,0x38,0x1f,0xb6,0x09,0x74,0xb4,0xce,0x7a,0xeb,0x05,0xec,
+  0xb7,0x31,0x91,0x0f,0xa9,0x32,0x45,0x4a,0xf6,0x26,0x5e,0x8d,0x92,0x2e,0x7b,0x97,
+  0xd1,0x52,0x50,0xa6,0x45,0x22,0x2a,0xe0,0x91,0xc5,0xf8,0xc1,0x00,0x9e,0xb0,0x53,
+  0xa5,0xe8,0x6c,0xf1,0x43,0x34,0x2b,0x4b,0xd1,0x14,0x39,0x2a,0x8e,0xb8,0x66,0x22,
+  0x9a,0xc2,0xf5,0xaa,0xb7,0x87,0x7c,0x49,0x79,0x21,0xdd,0xac,0xe6,0x70,0xcf,0x53,
+  0xfa,0x48,0x27,0xe4,0x6c,0xed,0xb2,0xd2,0x07,0x9d,0x30,0x62,0xeb,0x97,0xf9,0x91,
+  0x11,0x9b,0x38,0xbe,0xf8,0xd9,0x06,0xa5,0xcb,0x6a,0x5f,0x68,0x0c,0xde,0xc0,0x52,
+  0xaf,0x5d,0x84,0x4d,0x17,0xc3,0xc2,0x02,0x99,0x16,0x7c,0x58,0xf0,0xe5,0x1f,0x1a,
+  0x09,0x29,0xc6,0x09,0xce,0x87,0xaf,0x56,0x90,0x06,0xab,0x22,0x7e,0xec,0x06,0x3e,
+  0xf4,0xc5,0x1b,0xcd,0x87,0x14,0x5a,0x4e,0x1a,0x79,0xfc,0x5e,0x28,0xc5,0xb2,0x86,
+  0x46,0xcf,0x41,0xf1,0x88,0x66,0x58,0xaa,0x1e,0xe6,0x47,0x2c,0x95,0x80,0x6f,0x7e,
+  0xb0,0xa4,0x74,0x92,0x66,0x24,0x6e,0x8f,0x1a,0xe0,0x24,0xab,0x24,0x4e,0xb0,0xbd,
+  0xcd,0x8e,0x30,0xc3,0x5f,0x22,0xd4,0xfb,0xbe,0x60,0xd6,0x30,0x05,0x1f,0x02,0x0d,
+  0x61,0xfe,0xe1,0xf5,0xa9,0xcb,0x87,0x6a,0x52,0x98,0x41,0x7f,0xfc,0x0c,0xad,0x6a,
+  0x61,0x7c,0x98,0xb0,0x43,0x59,0xcc,0x43,0xab,0xd2,0xdd,0x6a,0x53,0x9d,0x0f,0xeb,
+  0xc6,0xf6,0x8d,0x87,0xd0,0x0a,0xcf,0x3f,0x24,0x6d,0x1f,0x45,0xa3,0xf2,0x7a,0x88,
+  0xa5,0x65,0x61,0xd8,0x4b,0xa1,0xdd,0xbe,0xcf,0x4b,0xe8,0x7b,0x7b,0xe1,0x18,0x64,
+  0x07,0x63,0x53,0x93,0x25,0x38,0xd6,0x94,0x65,0xf7,0x67,0xb9,0x89,0xc8,0x35,0xa1,
+  0x98,0xb7,0x5e,0x14,0xd7,0xab,0x8f,0x34,0xe3,0x32,0xd9,0x55,0xd7,0xb0,0xf5,0x6a,
+  0x30,0x65,0xcd,0x5b,0xaf,0x22,0x7e,0xbc,0x47,0x9c,0xe6,0xfd,0xe1,0xe3,0xf6,0x07,
+  0x86,0xc9,0x7e,0xdd,0x5e,0x81,0x2b,0xe0,0x9a,0x33,0x75,0xe3,0xcb,0x3f,0x98,0x59,
+  0x7b,0x69,0xa2,0x18,0x2e,0x22,0x3d,0xf6,0xd0,0x04,0x0d,0x6f,0x87,0x4b,0x0c,0x2c,
+  0x8b,0xe1,0x24,0x33,0x94,0x9b,0xb3,0xbe,0xf9,0xc9,0x29,0xa5,0xc1,0xd4,0x7e,0x5c,
+  0xdf,0xc3,0x4a,0xe9,0x4c,0xca,0x1c,0x8e,0xeb,0x37,0x9b,0x86,0xf9,0x11,0x7c,0xc8,
+  0x2e,0x46,0xf2,0x8b,0x85,0xec,0x8a,0x70,0xc3,0xe5,0xc3,0x86,0x4b,0x85,0x94,0x14,
+  0x2c,0xc1,0x87,0x36,0xa7,0x41,0x34,0x3e,0x2c,0x64,0x66,0x26,0x97,0x6e,0xcc,0x3f,
+  0xd6,0xf6,0xf6,0xb6,0x68,0x3e,0xa7,0x25,0xf7,0x32,0x3e,0xcc,0x63,0xc6,0xb1,0xb8,
+  0xe1,0xf9,0x07,0xcd,0x20,0x1a,0x5f,0xfc,0xf0,0x48,0x0c,0xb9,0x29,0x50,0x9b,0x8c,
+  0x18,0xa4,0xc0,0x62,0x6a,0x92,0x5f,0x3b,0xd9,0x26,0x0c,0xf8,0x84,0x10,0xe8,0x40,
+  0x15,0xba,0xa1,0x09,0xf8,0xed,0xf2,0xc2,0xf8,0xf9,0xb0,0xbb,0x21,0xff,0x8c,0x87,
+  0x1f,0xa3,0x95,0x0b,0xe9,0xf5,0xf6,0xf8,0xaa,0x56,0xfa,0x0d,0x1a,0x75,0x3c,0xd4,
+  0x4a,0x2f,0x5e,0xe8,0x5d,0x9f,0x18,0x0f,0x85,0xb9,0x89,0xfb,0xc6,0x43,0x0a,0x15,
+  0xdc,0xf4,0xa7,0x70,0xf7,0x3f,0xcf,0xf8,0x10,0x5c,0xc3,0x79,0xe0,0x3b,0xd7,0x24,
+  0x1d,0xdf,0x78,0x38,0x16,0x32,0x3e,0x5c,0x3a,0x3a,0xea,0xe7,0xc3,0xf7,0xeb,0x7c,
+  0xb8,0xb7,0x91,0x0f,0x39,0x7d,0x31,0x3e,0xdc,0x78,0x68,0x8b,0x9f,0x0f,0xaf,0xdf,
+  0x25,0x3e,0xe4,0x58,0xf8,0xdb,0x54,0x6d,0x61,0xe0,0x4f,0x01,0x8a,0x07,0xbb,0xde,
+  0x65,0x58,0x38,0xf5,0xd6,0xc2,0xea,0x9a,0x6b,0xfc,0xed,0xf9,0xd9,0xff,0xb8,0x8a,
+  0xed,0xff,0x12,0xa0,0xb8,0xb0,0xf1,0x10,0xc3,0xc2,0xab,0xd7,0x16,0x36,0xd6,0x5c,
+  0xd3,0xd0,0xbe,0xd3,0xe5,0xc3,0x4c,0xe7,0xe6,0x5f,0xa6,0x7b,0x90,0x0f,0x33,0x2f,
+  0x6f,0x3e,0xc7,0x09,0x33,0xc3,0x51,0xb3,0x72,0xed,0x3f,0x8c,0xdf,0x04,0x83,0xb0,
+  0xdb,0x33,0x4c,0xc8,0xc5,0xef,0xbc,0x17,0x29,0x29,0x29,0x29,0x29,0x29,0x29,0x29,
+  0x29,0x29,0xa9,0xff,0xbb,0x78,0xed,0xa0,0xc8,0xda,0x41,0x4a,0x4a,0x4a,0x4a,0x4a,
+  0x4a,0x4a,0x4a,0x4a,0x4a,0xea,0xd6,0xe2,0xb5,0x43,0x54,0xd6,0x0e,0x52,0x52,0x52,
+  0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xb7,0x16,0xaf,0x1d,0x54,0x5e,0x3b,0xe0,
+  0x5f,0x91,0xbe,0x27,0x77,0xd3,0x81,0xfe,0x97,0x76,0x07,0x74,0xb6,0xee,0x73,0xf0,
+  0x00,0xcd,0x58,0xd0,0x70,0x13,0xda,0x5d,0x94,0xd2,0xf4,0xcc,0x31,0x7b,0x69,0xdb,
+  0x97,0x85,0x60,0xba,0x87,0x81,0x39,0x36,0x7e,0x0a,0x03,0x4e,0x30,0xfd,0x2b,0xc6,
+  0xcc,0x09,0x67,0xe5,0xc5,0xd7,0x5f,0x09,0xa6,0x7b,0x30,0xe7,0xcc,0xdf,0x69,0x66,
+  0xbf,0x63,0x3a,0xc1,0xf4,0x9f,0x78,0xf8,0xe0,0x11,0xa7,0xe3,0x93,0xa7,0xb7,0x04,
+  0xd3,0x3d,0xce,0xbf,0x18,0x7f,0x50,0xf3,0x1f,0x5f,0x73,0xdc,0x86,0x47,0x57,0x54,
+  0x83,0x9b,0xff,0x65,0x18,0x3f,0x5b,0x20,0xa8,0xf9,0x6f,0xce,0x9e,0x9e,0x87,0x7b,
+  0x76,0x7c,0xbe,0x29,0x98,0xee,0x71,0xfe,0xc5,0xf8,0x03,0x8b,0xff,0xb5,0x6d,0x1f,
+  0xd3,0xa5,0xcf,0xcf,0xa8,0xb7,0x6f,0x7a,0x47,0x32,0xe7,0x06,0x30,0x7e,0x0e,0x05,
+  0x17,0xff,0x1a,0xd9,0x00,0xab,0x63,0xf7,0x06,0x17,0xff,0x62,0xfc,0x41,0xcd,0x7f,
+  0x22,0x6d,0x0d,0xc3,0xba,0xeb,0xd9,0xa0,0xe2,0xc7,0xac,0x39,0x2c,0x7f,0x9a,0xf3,
+  0x4e,0x30,0xfd,0x2b,0xea,0x81,0x37,0x9d,0x0d,0x9f,0xce,0x04,0x96,0xff,0xdd,0xf1,
+  0xdf,0xfc,0xcb,0x04,0x77,0x47,0x4a,0x66,0xe6,0x94,0x93,0x59,0x31,0x1d,0x58,0xfe,
+  0xa9,0xcd,0xb3,0xfc,0x39,0x1f,0xd4,0xfc,0x2f,0xeb,0xff,0xf5,0x9a,0xd3,0xfb,0xe3,
+  0xe3,0x73,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,0xd8,0xfc,0xf7,0xbf,0xf6,0x8e,0xfd,
+  0xd0,0x8a,0x93,0xb1,0xdb,0x37,0xbd,0x23,0x99,0xb5,0x39,0x96,0x3f,0x03,0x8b,0xff,
+  0x68,0xe7,0xa9,0x67,0xed,0xec,0x57,0x3f,0x59,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,
+  0xd8,0xfc,0xaf,0xde,0xf1,0x05,0x18,0x6d,0x6f,0x07,0x97,0x7f,0x6a,0x2c,0x7f,0x06,
+  0x17,0xff,0x2b,0x23,0x69,0xda,0x7f,0x32,0xf1,0x7d,0x30,0xdd,0xb3,0x1f,0x39,0xe1,
+  0xe3,0x0f,0x66,0xfe,0x4d,0xf6,0x7c,0x1c,0xbc,0xd8,0x6a,0x82,0xcd,0x9e,0x5a,0x09,
+  0x9b,0x40,0xff,0xf5,0xff,0x13,0xdc,0xf7,0x46,0x4c,0xa8,0x12,0xaf,0xcf,0x2b,0x7b,
+  0x6e,0x6c,0xf7,0x37,0xea,0xe7,0xba,0x8f,0xf0,0x33,0x01,0x00,
diff --git a/u-boot/board/esd/hh405/hh405.c b/u-boot/board/esd/hh405/hh405.c
new file mode 100644
index 0000000..e9d2d36
--- /dev/null
+++ b/u-boot/board/esd/hh405/hh405.c
@@ -0,0 +1,911 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006-2007
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <sm501.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* FPGA internal regs */
+#define FPGA_CTRL	((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
+#define FPGA_STATUS	((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
+#define FPGA_CTR	((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
+#define FPGA_BL		((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
+
+/* FPGA Control Reg */
+#define FPGA_CTRL_REV0      0x0001
+#define FPGA_CTRL_REV1      0x0002
+#define FPGA_CTRL_VGA0_BL   0x0004
+#define FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define FPGA_CTRL_CF_RESET  0x0040
+#define FPGA_CTRL_PS2_PWR   0x0080
+#define FPGA_CTRL_CF_PWRN   0x0100      /* low active */
+#define FPGA_CTRL_CF_BUS_EN 0x0200
+#define FPGA_CTRL_LCD_CLK   0x7000      /* mask for lcd clock */
+#define FPGA_CTRL_OW_ENABLE 0x8000
+
+#define FPGA_STATUS_CF_DETECT 0x8000
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define SWAP32(x)	 ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+			  (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#define BPP	16
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 1 /* test-only */
+	{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+	{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+	{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+	{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+	{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+	{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+#define BPP	32
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 0 /* test-only */
+	{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+	{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+	{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+	{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+	{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+	{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_320_8bpp[] =
+{
+#include "logo_320_240_8bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+unsigned char logo_bmp_1024[] =
+{
+#include "logo_1024_768_8bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13705_320_240_8bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#include "../common/s1d13806_1024_768_8bpp.h"
+
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+	{"hh405/preinst.img", 0, -1, AU_SCRIPT},
+	{"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
+	{"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
+	{"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
+	{"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
+	{"hh405/postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
+/*
+ * Get version of HH405 board from GPIO's
+ */
+int board_revision(void)
+{
+	unsigned long osrh_reg;
+	unsigned long isr1h_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
+	 */
+	osrh_reg = in_be32((void *)GPIO0_OSRH);
+	isr1h_reg = in_be32((void *)GPIO0_ISR1H);
+	tcr_reg = in_be32((void *)GPIO0_TCR);
+	out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in_be32((void *)GPIO0_IR) & 0x80400000;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out_be32((void *)GPIO0_OSRH, osrh_reg);                   /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1h_reg);                 /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x80000000) {
+		/* Revision 1.0 or 1.1 detected */
+		return 1;
+	} else {
+		if (value & 0x00400000) {
+			/* unused */
+			return 3;
+		} else {
+			return 2;
+		}
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int cf_enable(void)
+{
+	int i;
+
+	if (gd->board_type >= 2) {
+		if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
+			if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
+				out_be16(FPGA_CTRL,
+					 in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
+
+				for (i=0; i<300; i++)
+					udelay(1000);
+
+				out_be16(FPGA_CTRL,
+					 in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
+
+				for (i=0; i<20; i++)
+					udelay(1000);
+			}
+		} else {
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
+		}
+	}
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	char *str;
+	unsigned long contrast0 = 0xffffffff;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_INIT pin
+	 */
+	/* setup FPGA_INIT as output */
+	out_be32((void *)GPIO0_TCR,
+		 in_be32((void *)GPIO0_TCR) | FPGA_INIT);
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | FPGA_INIT);   /* reset high */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Write Board revision into FPGA
+	 */
+	out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
+
+	/*
+	 * Setup and enable EEPROM write protection
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Reset touch-screen controller
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
+	udelay(1000);
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
+	for (i=0;i<500;i++)
+		udelay(1000);
+	out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
+
+	/*
+	 * Get contrast value from environment variable
+	 */
+	str = getenv("contrast0");
+	if (str) {
+		contrast0 = simple_strtol(str, NULL, 16);
+		if (contrast0 > 255) {
+			printf("ERROR: contrast0 value too high (0x%lx)!\n",
+			       contrast0);
+			contrast0 = 0xffffffff;
+		}
+	}
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc230") == 0) {
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
+		out_be16(FPGA_BL, 0x0000);
+
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_1024_768_8bpp,
+			 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
+			 logo_bmp_1024, sizeof(logo_bmp_1024));
+	} else if (strcmp(str, "ppc220") == 0) {
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
+		out_be16(FPGA_BL, 0x0000);
+
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_640_480_16bpp,
+			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+			 logo_bmp_640, sizeof(logo_bmp_640));
+	} else if (strcmp(str, "ppc215") == 0) {
+		/*
+		 * Set default display contrast voltage
+		 */
+		if (contrast0 == 0xffffffff) {
+			out_be16(FPGA_CTR, 0x0082);
+		} else {
+			out_be16(FPGA_CTR, contrast0);
+		}
+		out_be16(FPGA_BL, 0xffff);
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) |
+			 FPGA_CTRL_VGA0_BL |
+			 FPGA_CTRL_VGA0_BL_MODE);
+		/*
+		 * Set lcd clock (small epson)
+		 */
+		out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
+		udelay(100);               /* wait for 100 us */
+
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13705_320_240_8bpp,
+			 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
+			 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
+	} else if (strcmp(str, "ppc210") == 0) {
+		/*
+		 * Set default display contrast voltage
+		 */
+		if (contrast0 == 0xffffffff) {
+			out_be16(FPGA_CTR, 0x0060);
+		} else {
+			out_be16(FPGA_CTR, contrast0);
+		}
+		out_be16(FPGA_BL, 0xffff);
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) |
+			 FPGA_CTRL_VGA0_BL |
+			 FPGA_CTRL_VGA0_BL_MODE);
+		/*
+		 * Set lcd clock (small epson), enable 1-wire interface
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) |
+			 LCD_CLK_08330 |
+			 FPGA_CTRL_OW_ENABLE);
+
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+#ifdef CONFIG_VIDEO_SM501
+	} else {
+		pci_dev_t devbusfn;
+
+		/*
+		 * Is SM501 connected (ppc221/ppc231)?
+		 */
+		devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+		if (devbusfn != -1) {
+			puts("VGA:   SM501 with 8 MB ");
+			if (strcmp(str, "ppc221") == 0) {
+				printf("(800*600, %dbpp)\n", BPP);
+				out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
+			} else if (strcmp(str, "ppc231") == 0) {
+				printf("(1024*768, %dbpp)\n", BPP);
+				out_be16(FPGA_BL, 0x0000);
+			} else {
+				printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+				return 0;
+			}
+		} else {
+			printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+			return 0;
+		}
+#endif /* CONFIG_VIDEO_SM501 */
+	}
+
+	cf_enable();
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HH405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev %ld.x)\n", gd->board_type);
+
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	if (((gd->board_type >= 2) &&
+	     (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
+	    (gd->board_type < 2)) {
+		/*
+		 * Assert or deassert CompactFlash Reset Pin
+		 */
+		if (on) {		/* assert RESET */
+			cf_enable();
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) &
+				 ~FPGA_CTRL_CF_RESET);
+		} else {		/* release RESET */
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) |
+				 FPGA_CTRL_CF_RESET);
+		}
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+
+#ifdef CONFIG_VIDEO_SM501
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	char str[64];
+	char str2[64];
+	int i = getenv_f("serial#", str2, sizeof(str));
+
+	if (line_number == 1) {
+		sprintf(str, " Board: ");
+
+		if (i == -1) {
+			strcat(str, "### No HW ID - assuming HH405");
+		} else {
+			strcat(str, str2);
+		}
+
+		if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
+			strcat(str, " (");
+			strcat(str, str2);
+		} else {
+			strcat(str, " (Missing bd_type!");
+		}
+
+		sprintf(str2, ", Rev %ld.x)", gd->board_type);
+		strcat(str, str2);
+		strcpy(info, str);
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+/*
+ * Returns SM501 register base address. First thing called in the driver.
+ */
+unsigned int board_video_init (void)
+{
+	pci_dev_t devbusfn;
+	u32 addr;
+
+	/*
+	 * Is SM501 connected (ppc221/ppc231)?
+	 */
+	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+	if (devbusfn != -1) {
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
+		return (addr & 0xfffffffe);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	pci_dev_t devbusfn;
+	u32 addr;
+
+	/*
+	 * Is SM501 connected (ppc221/ppc231)?
+	 */
+	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+	if (devbusfn != -1) {
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
+		addr &= 0xfffffffe;
+#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
+		addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
+#endif
+		return addr;
+	}
+
+	return 0;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return init_regs_800x600;
+	} else {
+		return init_regs_1024x768;
+	}
+}
+
+int board_get_width (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return 800;
+	} else {
+		return 1024;
+	}
+}
+
+int board_get_height (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return 600;
+	} else {
+		return 768;
+	}
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/u-boot/board/esd/hh405/logo_1024_768_8bpp.c b/u-boot/board/esd/hh405/logo_1024_768_8bpp.c
new file mode 100644
index 0000000..2195547
--- /dev/null
+++ b/u-boot/board/esd/hh405/logo_1024_768_8bpp.c
@@ -0,0 +1,2544 @@
+  0x1f,0x8b,0x08,0x08,0x20,0xb5,0x06,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48,
+  0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x31,0x30,0x32,0x34,0x78,0x37,0x36,
+  0x38,0x5f,0x32,0x35,0x36,0x2e,0x62,0x6d,0x70,0x00,0xec,0xbd,0x0b,0x74,0x23,0xd7,
+  0x79,0xa0,0x59,0x14,0x0d,0x1d,0x71,0xb6,0xc9,0x43,0x37,0xe4,0xe4,0xa8,0xa2,0x0c,
+  0x80,0x58,0xeb,0x14,0x48,0x77,0x7a,0xe2,0xb4,0x2c,0xcb,0x56,0x4b,0xed,0xb6,0x8e,
+  0xc2,0x84,0x4e,0x6d,0x83,0x05,0x80,0x8b,0x09,0x0c,0xec,0x28,0x1c,0xc3,0x69,0x39,
+  0x41,0x4f,0xec,0xc4,0xde,0x44,0xc1,0x60,0x6d,0xb5,0xdb,0x8c,0x9b,0x09,0x99,0x75,
+  0xbc,0xd3,0xed,0xce,0x64,0xc6,0x36,0xd0,0x72,0xa4,0x90,0x9d,0x50,0x4b,0xb5,0x12,
+  0xef,0x78,0x26,0xb6,0x3c,0x93,0x2c,0x8f,0x93,0x33,0x50,0x9e,0x92,0x10,0xc2,0xe3,
+  0xcd,0x61,0x98,0xd6,0x63,0x77,0x04,0xd2,0x40,0x09,0x38,0x7b,0xef,0xad,0xd7,0x7d,
+  0x15,0x50,0x20,0xd9,0x0f,0xa9,0xff,0x0f,0x20,0x88,0x47,0xbd,0xeb,0xfe,0x8f,0xfb,
+  0xdf,0xff,0xde,0x7b,0xfc,0xa7,0xde,0xfd,0x96,0x03,0x0a,0xe6,0xdd,0x6f,0x51,0x14,
+  0x0d,0xbf,0x41,0xff,0x95,0x61,0x45,0x19,0x52,0x6e,0x53,0x1c,0xde,0xfe,0x23,0xd6,
+  0x9f,0xc3,0x5b,0x6e,0x79,0x8b,0xf2,0xe8,0xa7,0x1e,0x55,0xee,0x3c,0xfe,0x98,0xf2,
+  0xf5,0x3f,0xfe,0x9a,0xf2,0x53,0x8f,0xfd,0x89,0xf2,0xfe,0x0f,0x3c,0xa8,0xdc,0x35,
+  0xf7,0x5f,0x94,0xf2,0x97,0xd6,0x95,0xb7,0xfe,0xd0,0x43,0xca,0x0b,0xdf,0x79,0x41,
+  0x79,0xf0,0xe1,0xc7,0x94,0x7f,0xf7,0xcd,0x2d,0x25,0xfb,0xf0,0x9c,0x72,0xe1,0x4b,
+  0x17,0x94,0x3b,0x7f,0xe8,0x4e,0xe5,0xe4,0x57,0xbe,0xab,0x1c,0xf9,0xd4,0x15,0xe5,
+  0x87,0x3e,0x50,0x50,0xde,0xf6,0xae,0x82,0xf2,0x8e,0x5f,0xfc,0xae,0x72,0xd7,0xcc,
+  0x57,0x94,0x8f,0x3e,0xf6,0xb8,0xf2,0xcd,0x3f,0xfb,0x7b,0xe5,0x9f,0xcd,0x3d,0xae,
+  0xfc,0x6f,0xab,0xff,0xa0,0xdc,0xfa,0xd6,0xbb,0x94,0xff,0xfe,0xda,0x6b,0xca,0x4f,
+  0xfe,0xef,0x57,0x94,0x77,0x7f,0xec,0x4f,0x94,0xd8,0xcc,0xbc,0x72,0xd7,0x91,0x1f,
+  0x57,0xfe,0xbc,0xf6,0x9c,0xf2,0x63,0x3f,0x76,0x44,0x39,0xfb,0x9b,0x9f,0x57,0x7e,
+  0x74,0xe6,0x51,0xe5,0xc4,0xa3,0x8f,0x2b,0x3f,0xfb,0x85,0xff,0xac,0xac,0xd4,0xfe,
+  0xbb,0x72,0xe1,0xc9,0xff,0xa2,0x7c,0xf3,0x3b,0xaf,0x2b,0x2b,0xab,0x4f,0x29,0xb7,
+  0xdf,0x7e,0xbb,0x72,0xc2,0x48,0x2a,0x1f,0xfd,0x85,0x8f,0x2b,0xbf,0xfa,0xd4,0x6b,
+  0xca,0x0f,0xff,0xc2,0xf3,0xca,0xcf,0x7c,0xe5,0x35,0xe5,0x07,0x3f,0xf0,0xcb,0xca,
+  0xe3,0x7f,0xfc,0x82,0xb2,0xf4,0xc7,0x3b,0x4a,0xf8,0xed,0xef,0x51,0xee,0xfb,0xb5,
+  0x2b,0xca,0x1d,0xef,0xfb,0x59,0xe5,0xae,0x87,0xff,0x48,0x31,0xce,0x5f,0x51,0x3e,
+  0x79,0xfa,0x8b,0x4a,0xed,0x85,0x4d,0xe5,0x6d,0x93,0x3f,0xa9,0x9c,0xf9,0xc2,0x13,
+  0x4a,0xf6,0xc3,0x8f,0x29,0x5f,0xf8,0xf2,0x53,0xca,0xdb,0x67,0xce,0x2b,0xb1,0xe9,
+  0x79,0xe5,0x03,0x9f,0xfe,0x1b,0xe5,0x7f,0xfc,0xe9,0x27,0x94,0xb1,0x1f,0xd0,0xd0,
+  0xf1,0xff,0xb4,0xf2,0xc2,0xdf,0xb7,0x94,0xd0,0xc8,0xdb,0x94,0x7b,0x7e,0x3c,0xa3,
+  0xdc,0x75,0xf2,0x39,0x25,0xf9,0x2f,0x7f,0x59,0x79,0xbd,0xfb,0xba,0x72,0x71,0xed,
+  0x4f,0x94,0x5f,0xfc,0xea,0xa6,0xf2,0xc3,0xbf,0x7c,0x45,0xf9,0xd0,0xe7,0xff,0x5a,
+  0xf9,0xfc,0xa5,0x3f,0x57,0xfe,0xe6,0xf9,0x17,0x94,0x7f,0xbf,0xfe,0xba,0x72,0xe7,
+  0x7d,0x9f,0x54,0x7e,0xed,0x73,0x67,0x95,0x6f,0xfe,0xe9,0xba,0xf2,0x8f,0x57,0xae,
+  0x28,0xef,0x7c,0xe7,0x3b,0x95,0x7b,0xdf,0x77,0x9f,0xf2,0x03,0x77,0xde,0xa9,0x1c,
+  0xf9,0x95,0xbf,0x55,0xfe,0xd3,0x8b,0xaf,0x2b,0x5f,0x7d,0xe2,0x49,0xe5,0xc7,0x3e,
+  0xfd,0x9a,0x72,0xf6,0xff,0xdc,0x52,0xbe,0xf0,0xc5,0x0b,0xca,0x8f,0x4e,0xfd,0x92,
+  0x92,0xf9,0xe9,0xac,0xf2,0xf1,0x5f,0xfc,0xa4,0xf2,0xe9,0x3f,0x7a,0x4d,0x29,0x7d,
+  0xfe,0x19,0xe5,0xae,0xec,0x65,0xe5,0x77,0x9e,0xf9,0x2b,0x65,0xee,0x67,0xfe,0xa5,
+  0x72,0xef,0x47,0x9f,0x50,0xde,0xf7,0xf1,0x3f,0x54,0x9e,0xf9,0xa3,0xaf,0x29,0x3f,
+  0xf6,0xc8,0x33,0x4a,0xfa,0xc2,0x6b,0xca,0xdb,0xde,0xf9,0x3f,0x2b,0x6f,0xff,0xe0,
+  0xbf,0x51,0xa6,0x3f,0xf7,0x37,0x8a,0xfa,0xbe,0xac,0xf2,0x33,0x5f,0xfc,0x1b,0x65,
+  0x7a,0xfa,0x83,0x8a,0xf6,0xc8,0x9f,0x2a,0xef,0xf9,0xa9,0x93,0xca,0x07,0x7f,0xeb,
+  0x35,0xe5,0x81,0x5f,0xf9,0x13,0xe5,0x83,0xa9,0x39,0xe5,0xa9,0xbf,0x7d,0x5d,0x39,
+  0x92,0xfe,0xbc,0x32,0xf6,0x83,0xf7,0x28,0x87,0x4b,0xaf,0x29,0xbf,0xf0,0x95,0xe7,
+  0x95,0xcd,0xff,0xef,0x75,0xe5,0x03,0x9f,0x7b,0x4d,0x99,0xfb,0xa5,0xc7,0x94,0xfa,
+  0x95,0xd7,0x95,0x03,0xff,0xc3,0x01,0xe5,0x7f,0x2a,0x9e,0x53,0x9e,0xfb,0xcb,0x17,
+  0x94,0x1f,0xfd,0x99,0x0b,0x8a,0xfe,0xa1,0x47,0x95,0xe2,0xaf,0xfe,0x1b,0xe5,0xc7,
+  0x3f,0x74,0x46,0xf9,0xbf,0xff,0xf4,0x39,0xe5,0x17,0x3e,0xf7,0xbb,0xca,0xd1,0xfb,
+  0x1f,0x54,0x0e,0xff,0xc8,0x11,0xe5,0xa3,0x3f,0xff,0x71,0xe5,0x6b,0x7f,0xd1,0x56,
+  0x2e,0xfc,0xc1,0x5f,0x2b,0x9f,0xfa,0xdc,0x17,0x94,0x27,0x97,0x9f,0x52,0x96,0x7e,
+  0xfb,0x19,0xe5,0x27,0x1f,0xfd,0x43,0xe5,0x8b,0x17,0xbe,0xa2,0x7c,0xed,0xff,0xfa,
+  0xa6,0xf2,0x2f,0x7e,0x7e,0x5e,0x29,0x7c,0xee,0x29,0xc5,0xf8,0xb5,0x75,0xe5,0xf7,
+  0xd6,0xff,0x51,0x39,0x92,0x9d,0x57,0x1e,0xf8,0xe9,0xff,0x55,0xf9,0xf9,0x27,0x5f,
+  0x53,0xb2,0xb9,0x39,0x25,0xfc,0x8e,0xa4,0x52,0xfa,0xed,0x6f,0x29,0x1f,0xd4,0x93,
+  0xca,0x67,0x2e,0xbd,0xa0,0x5c,0xfe,0x0f,0x7f,0xad,0x9c,0xbe,0xf8,0x57,0xca,0x07,
+  0x3f,0xfc,0x79,0xe5,0x67,0x9f,0xb8,0xa2,0xdc,0xf9,0x23,0xf7,0x29,0xf1,0xec,0x17,
+  0x95,0xa5,0xaf,0x6d,0x29,0x9f,0xfc,0x95,0x47,0x95,0x47,0x1e,0xf9,0xa8,0xf2,0xb5,
+  0x3f,0x5e,0x57,0x9e,0xff,0x6f,0xe8,0x9e,0xbe,0xfd,0x9d,0x4a,0xf2,0x17,0x1e,0x55,
+  0xa2,0x0f,0x7d,0x5e,0xb9,0xf3,0xdd,0x1f,0x57,0x6e,0xfb,0xbe,0x23,0xca,0xa3,0xa5,
+  0xc7,0x94,0xc7,0x3e,0x73,0x56,0x79,0xf0,0xa1,0x0f,0x2a,0x27,0x7e,0xe6,0x33,0xca,
+  0x07,0x1f,0xfe,0xa8,0xf2,0xe5,0xca,0x93,0xca,0x3d,0xef,0xbe,0x4f,0xf9,0xfd,0xbf,
+  0x78,0x5d,0x79,0x6a,0xed,0x6b,0xca,0xdb,0xbe,0xef,0x4e,0x25,0x95,0xce,0x2a,0xff,
+  0xf4,0x9f,0xde,0xa5,0x2c,0xfe,0xee,0xba,0xf2,0xdc,0xd6,0xeb,0xca,0xd7,0xfe,0xf4,
+  0x05,0xe5,0x7f,0x39,0xf5,0x79,0xe5,0xa3,0x9f,0x79,0x0a,0x1d,0xd3,0x07,0x95,0x3f,
+  0xfe,0xcb,0x4d,0xe5,0xb1,0x3f,0xbc,0xa2,0xdc,0xf5,0xde,0x0f,0x2a,0x8f,0xff,0xc1,
+  0x37,0x95,0xd8,0x4f,0x3e,0xaa,0xbc,0x75,0xec,0x76,0xe5,0x41,0x3d,0xab,0xfc,0xca,
+  0xf2,0xa6,0xf2,0xa3,0xfa,0x27,0x94,0xc7,0xd1,0xb1,0xde,0x9b,0x3b,0xaf,0x3c,0xfa,
+  0xbb,0x2f,0x28,0xeb,0xdf,0x7e,0x4e,0x59,0xfe,0xd6,0x77,0x95,0xfb,0x3e,0x73,0x45,
+  0xf9,0xd1,0x07,0x0b,0xca,0xb1,0x0f,0x3f,0xae,0xa4,0x7e,0xeb,0x1f,0x94,0x43,0xc6,
+  0x19,0xe5,0xf3,0xbf,0x75,0x4e,0x39,0x66,0xfc,0xa2,0x92,0x7b,0xb4,0xaa,0x7c,0xfb,
+  0xff,0x79,0x5d,0xf9,0xc3,0x6f,0xfc,0xa5,0x72,0xe1,0x5b,0x6d,0xe5,0xc1,0xb3,0x57,
+  0x94,0x1f,0x3e,0xfa,0xb3,0xca,0xa1,0xb9,0xcb,0x4a,0xee,0xb7,0xb7,0x94,0xb3,0x9f,
+  0xf9,0xbc,0xf2,0x42,0xfd,0xbb,0xca,0x7b,0x72,0x5f,0x51,0x8e,0x94,0xfe,0x51,0x59,
+  0x5f,0x5f,0x57,0x8e,0xfe,0xea,0xdf,0x2a,0x0b,0x5f,0x6b,0x2a,0x53,0x3f,0xff,0x15,
+  0x25,0xf5,0xeb,0x7f,0xad,0x68,0xef,0xfb,0x69,0xe5,0xe7,0xfe,0xed,0x0b,0xca,0x4b,
+  0x2f,0xbf,0xa6,0xfc,0xeb,0x5f,0xff,0xaa,0x72,0xf6,0xd7,0x3f,0xaf,0xcc,0x2d,0xfc,
+  0x67,0xe5,0xce,0x87,0x3e,0xa7,0xfc,0xc0,0xbb,0x1f,0x51,0xee,0x4a,0x3f,0xa1,0xfc,
+  0x93,0xef,0xfb,0x61,0xe5,0xae,0x9f,0xff,0x6b,0x65,0xf1,0x4b,0xdf,0x54,0xee,0x3b,
+  0x79,0x41,0x59,0x5c,0x7b,0x41,0x39,0x7a,0xfa,0x35,0x65,0x67,0xfb,0x75,0xe5,0x9b,
+  0xdf,0x5a,0x57,0xbe,0xfb,0xf7,0x57,0x94,0x77,0xbc,0xe3,0x9d,0xca,0xa7,0x3e,0xfd,
+  0x98,0xf2,0x9f,0xbe,0xf1,0x4d,0xa5,0xf1,0xdf,0xd0,0x71,0xcf,0x9d,0x55,0xfe,0xfd,
+  0x97,0xbf,0xa2,0xbc,0xfd,0xed,0x77,0x29,0x73,0x5f,0xbe,0xa2,0x4c,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x37,0x34,0x85,
+  0x09,0x8f,0xec,0x54,0xf3,0x7a,0x1f,0x0e,0x00,0x00,0xd7,0x90,0x9a,0xe2,0x31,0x77,
+  0xbd,0x0f,0x06,0x00,0x80,0x6b,0x0a,0x2d,0xff,0xd5,0xeb,0x7d,0x30,0x00,0x00,0x5c,
+  0x53,0xc0,0xfe,0x03,0xc0,0xcd,0x4b,0x8c,0xb6,0xff,0xea,0xf5,0x3e,0x1a,0x00,0x00,
+  0xae,0x25,0x60,0xff,0x01,0xe0,0xe6,0x05,0xe4,0x1f,0x00,0x6e,0x5e,0x40,0xfe,0x01,
+  0xe0,0xe6,0x85,0xa9,0xff,0x5f,0xef,0x83,0x01,0x00,0xe0,0x9a,0x02,0xf6,0x1f,0x00,
+  0x6e,0x5e,0x40,0xfe,0x01,0xe0,0xe6,0x05,0xf2,0x7f,0x00,0xe0,0xe6,0x05,0xec,0x3f,
+  0x00,0xdc,0xbc,0x40,0xfe,0x0f,0x00,0xdc,0xbc,0x80,0xfd,0x07,0x80,0x9b,0x97,0x18,
+  0xc8,0x3f,0x00,0xdc,0xb4,0x80,0xfc,0x03,0xc0,0x9b,0x10,0x55,0x35,0x4c,0x53,0xd7,
+  0x4d,0xc3,0xe8,0x59,0xab,0x97,0xc7,0xff,0x55,0x63,0x07,0xaf,0x1a,0x3c,0x1e,0x40,
+  0x76,0x36,0xd2,0x6f,0x67,0xfb,0x86,0x8a,0xf6,0x66,0x1a,0xd7,0x64,0x57,0x03,0xa1,
+  0x1a,0x86,0x3e,0x12,0xf8,0x1a,0xb8,0x77,0x28,0xe8,0xf2,0x2a,0x59,0x1e,0xdd,0x97,
+  0x37,0x40,0xa0,0x06,0x5d,0x8a,0x00,0xc5,0x0f,0xb8,0x0a,0x18,0xba,0x96,0xa8,0x4e,
+  0xa4,0x92,0xdd,0x6e,0x3a,0x9d,0xee,0x26,0x53,0x13,0xd5,0xec,0xb0,0xe9,0xb3,0xac,
+  0xa4,0xfe,0x6f,0x66,0xf2,0xc5,0xe8,0x18,0x5e,0x33,0x34,0x97,0x6d,0xf4,0xbd,0x7d,
+  0xaa,0xae,0xb5,0x72,0xc5,0x28,0xd9,0x57,0x37,0x55,0x3c,0xd0,0xd2,0x74,0x7e,0x9d,
+  0x1d,0x13,0x95,0xf4,0x9e,0x18,0xb4,0x14,0x18,0xde,0xe2,0x92,0xd2,0xa3,0x46,0xb2,
+  0x73,0xa1,0xe4,0x18,0x3a,0xbc,0x62,0x45,0x73,0x4f,0xcb,0x40,0xc5,0xcd,0x5a,0x8d,
+  0x96,0x26,0x73,0xc7,0xdd,0x03,0xb3,0x21,0x6a,0x07,0xbc,0xf0,0xa9,0xf8,0xb7,0x1d,
+  0x72,0x44,0x26,0xbf,0x73,0x63,0xc7,0x3b,0x5e,0xf1,0x42,0xe8,0x5a,0x85,0x5c,0x86,
+  0x64,0x6a,0x6e,0x34,0xe2,0x6e,0xce,0x3e,0x2c,0xc3,0xdc,0x61,0x76,0x32,0xdc,0xa9,
+  0xe4,0x42,0xd1,0xe4,0x98,0x75,0x83,0x2a,0x99,0x48,0x9f,0xeb,0xac,0x46,0x3a,0xf9,
+  0x89,0x54,0x17,0x2f,0x3f,0xd6,0x8d,0x16,0x73,0xad,0x4c,0xc3,0x3d,0xf2,0x3e,0xd7,
+  0x6b,0xc7,0x3d,0x66,0xe6,0x64,0x55,0xeb,0x3b,0xf1,0x22,0x18,0xf6,0x0f,0x86,0x29,
+  0x53,0xb1,0x86,0xfb,0xa3,0xbf,0x02,0xd6,0x0b,0xb1,0x39,0x74,0x29,0xba,0xb8,0x44,
+  0x44,0x43,0x39,0xf9,0xd9,0xb9,0x17,0xc6,0x67,0x37,0xce,0x39,0xed,0xf8,0x15,0x5d,
+  0x40,0xc2,0x4e,0x23,0x3b,0x97,0x8a,0x97,0x14,0x8e,0x52,0x37,0x37,0xaa,0xcb,0x96,
+  0x17,0xe4,0x5f,0x6f,0x25,0xe9,0xb5,0xe3,0xa1,0x6c,0xcf,0xeb,0x5f,0x8e,0x15,0xc7,
+  0xf8,0x9d,0xa5,0x43,0x2d,0x46,0x6d,0x44,0x92,0xa8,0xcc,0xf6,0x79,0xa6,0xbb,0x29,
+  0xb7,0x14,0xe4,0xbc,0xaf,0xbb,0xc3,0xdc,0xfe,0x8c,0x4c,0x31,0x4d,0x9d,0x56,0xb4,
+  0x62,0x9d,0x95,0x3a,0xd7,0xc5,0x82,0x81,0x57,0x2a,0x7a,0xbb,0x6e,0x50,0x3b,0x9e,
+  0xa0,0x8e,0xc8,0xef,0x7b,0x4c,0xcc,0x3d,0xa0,0xb1,0xee,0x28,0xfb,0x93,0x5a,0xf4,
+  0x8e,0xf8,0xb3,0x11,0xee,0xb7,0x46,0x35,0x49,0x5f,0x82,0x5c,0xc1,0xda,0x6e,0xa7,
+  0x6b,0x6d,0xaa,0x3b,0x96,0x74,0x4e,0xa5,0xde,0xa9,0x86,0xc6,0xf8,0x3b,0x14,0x0f,
+  0x25,0xb8,0x2d,0xd2,0xe8,0x89,0x50,0x5a,0xe1,0xd7,0x48,0x25,0xec,0x5f,0x27,0xa9,
+  0xeb,0x95,0x11,0xd6,0x6d,0x91,0xef,0xad,0x53,0xca,0x52,0xdf,0x2f,0x74,0xc9,0xa1,
+  0x91,0x15,0xe7,0xa9,0xef,0xd7,0xf1,0xc5,0x19,0x7b,0x86,0xac,0x70,0x40,0xd8,0x9a,
+  0x19,0x25,0xab,0x91,0xbd,0x85,0xa4,0x0a,0xc0,0xec,0xe4,0xba,0xc2,0xd9,0x45,0x27,
+  0x0b,0xdc,0xc2,0xe6,0x99,0x31,0xeb,0xc2,0x60,0xab,0x21,0x14,0x31,0xb5,0x68,0x5f,
+  0x35,0xf4,0x8c,0xf6,0xb8,0x30,0x00,0xcb,0x68,0x34,0xce,0x97,0x13,0x97,0xee,0xa4,
+  0xe4,0x42,0x72,0xf2,0xaf,0x8e,0x26,0x85,0xf5,0x52,0x19,0x5f,0xdb,0xd4,0xa8,0x0a,
+  0xc2,0x6f,0xdf,0xf0,0x62,0xc7,0xbb,0xdf,0x6d,0xff,0x63,0xa2,0x48,0x3b,0x85,0x40,
+  0x0d,0x79,0x5f,0x96,0x0a,0xcc,0xfe,0xd4,0x42,0x88,0x5f,0xad,0x9b,0xc0,0x3b,0x32,
+  0xa2,0xde,0xe1,0x7a,0x47,0x5b,0xa0,0xca,0x61,0x88,0x3a,0x89,0x36,0xf5,0x7d,0x8a,
+  0x3b,0xb9,0x21,0x6a,0xdb,0x31,0xf6,0x27,0x83,0xba,0x36,0xf1,0x06,0xf3,0x53,0xa4,
+  0xca,0x9f,0x63,0x3c,0x47,0xae,0x76,0xc5,0x3b,0x95,0xb6,0x64,0x0f,0x34,0x63,0xb2,
+  0xfb,0x43,0x36,0x9e,0x97,0x5f,0x65,0x47,0xd3,0x4d,0x50,0xdf,0x75,0x84,0xb5,0x27,
+  0xa9,0x5f,0x13,0xd4,0xf7,0xa3,0xd4,0xf7,0x39,0xea,0xfb,0x61,0xea,0xe2,0x14,0x85,
+  0x3b,0x1f,0xa1,0xce,0x33,0x29,0x73,0x82,0x5a,0x62,0x01,0xb2,0x4e,0x3f,0x15,0x63,
+  0x0c,0x90,0x4e,0x9d,0x53,0x5a,0x30,0x4d,0xcc,0xa5,0x06,0xf9,0x0f,0x4c,0xcb,0xa7,
+  0x6c,0xd9,0xd7,0x39,0x2f,0x5c,0x68,0xb6,0xfe,0x6f,0xe4,0x05,0xcf,0x01,0xdf,0xba,
+  0xaa,0xdc,0x05,0x30,0x87,0x04,0xa3,0x44,0x11,0x72,0xca,0xfb,0x54,0x23,0x90,0xfc,
+  0x8f,0xc9,0xe4,0x5f,0x61,0xe4,0xdf,0x68,0xc9,0xb6,0x54,0x44,0xa2,0x68,0x76,0xbd,
+  0xfd,0x7a,0x65,0x96,0x2e,0xca,0x29,0xca,0xfe,0xb4,0x7d,0xbe,0xe7,0xaf,0x60,0x82,
+  0xfd,0x89,0x52,0x32,0x4a,0x89,0x91,0x7f,0x8d,0xfa,0xc5,0xa5,0x8b,0x65,0x71,0xce,
+  0xfd,0xe8,0x6a,0x8c,0x84,0xef,0x25,0xe8,0xd6,0x24,0x16,0x55,0xcd,0xfa,0x48,0x94,
+  0x32,0x61,0x2f,0x91,0xa3,0xbe,0x1b,0x15,0xd6,0xcf,0x53,0xbf,0xb6,0xa8,0xef,0x3b,
+  0x92,0x2d,0x61,0xb6,0xa9,0x6b,0x1c,0x12,0xe5,0x9f,0xba,0xe5,0x5d,0xd1,0x6c,0xfb,
+  0x1e,0x2b,0x26,0x49,0x1f,0x9c,0xee,0xdd,0x31,0x99,0xfc,0x47,0xbd,0x5f,0xd9,0x4b,
+  0x0d,0xf4,0x22,0xdb,0xe3,0xf2,0x63,0x52,0x05,0x6e,0x05,0xc6,0xfe,0x9b,0x55,0x9f,
+  0xd5,0x8a,0xb2,0xba,0x43,0x3b,0xd5,0x7b,0x5f,0xae,0xf4,0x34,0x64,0x4a,0x45,0x20,
+  0xed,0x54,0x90,0x9b,0x7e,0xf2,0x6f,0xcc,0xc9,0xd7,0x8c,0x16,0xa6,0x74,0xaf,0x58,
+  0x52,0x65,0x79,0xc9,0xc7,0xce,0xd3,0xf2,0x1f,0xe5,0x8a,0xf8,0xb2,0xec,0x0c,0xec,
+  0xfd,0x47,0xbd,0x9f,0xe2,0x33,0xde,0xf7,0xcd,0xac,0x5c,0xc1,0xc5,0x13,0x2a,0x65,
+  0x9b,0xd3,0x8e,0x19,0xeb,0x71,0x8f,0x4a,0x55,0x41,0x01,0x98,0x73,0xbe,0x57,0xcf,
+  0x69,0xaf,0xd9,0x5f,0xf9,0x6f,0xfb,0x38,0x4d,0x16,0x3a,0x75,0xaa,0x82,0xfc,0xeb,
+  0xf4,0x91,0x48,0xc8,0x51,0xe3,0x4b,0x07,0x97,0xff,0x38,0xc8,0x7f,0x60,0xb4,0x7e,
+  0xa2,0x16,0x1f,0x65,0x6f,0x29,0x2d,0xff,0x39,0x1f,0xf9,0x42,0x14,0x47,0x84,0x5d,
+  0xad,0xf6,0x32,0xfe,0x18,0xd7,0x7b,0x0e,0xe6,0xff,0x4b,0xed,0x3f,0xed,0xff,0xab,
+  0x7e,0xda,0x49,0x89,0x46,0x28,0x17,0x83,0xaa,0xb3,0x0e,0x07,0x90,0xff,0x7d,0xf0,
+  0xff,0x33,0x7e,0xe7,0x17,0xcf,0x1a,0x45,0xf7,0x43,0xd7,0x29,0xe4,0x1d,0x9f,0xa5,
+  0xad,0xa3,0xe7,0x14,0x80,0x5e,0xf4,0x5f,0xd6,0x6e,0xaf,0x69,0xd2,0x52,0x27,0xfa,
+  0xff,0xf3,0xd4,0xaf,0xb4,0x42,0x5b,0xa4,0xbe,0xa7,0xfd,0xff,0xf6,0xae,0xfd,0xff,
+  0x7e,0x06,0x81,0xd9,0x0d,0x2d,0xff,0x63,0xbd,0xfd,0x7f,0x90,0xff,0xc0,0xb4,0xfb,
+  0x9a,0xda,0x78,0x96,0x59,0x81,0x6e,0xff,0xef,0x25,0xa6,0x7c,0xb9,0x54,0x33,0xfd,
+  0xc4,0x9f,0xb2,0xff,0x81,0xe4,0xff,0x99,0x7e,0xfe,0x7f,0xcd,0xff,0xdc,0x42,0x9a,
+  0xb7,0x0b,0xaa,0x17,0x93,0x9f,0x9c,0xd3,0x0a,0x69,0xef,0xfe,0x7f,0xc4,0xdf,0xe7,
+  0x8d,0x6b,0xde,0xb9,0xb8,0xd2,0xb2,0xd6,0xf3,0x1e,0x55,0xd8,0x86,0x8a,0x1e,0xe2,
+  0xaf,0x54,0xec,0x85,0x68,0xf9,0x67,0xef,0x2e,0x26,0x88,0xfd,0xa7,0x05,0x33,0xb8,
+  0xff,0xcf,0xc9,0x7f,0xa3,0x97,0xef,0x2f,0xec,0xa6,0xde,0xdb,0xfe,0x53,0xdb,0x02,
+  0xff,0x3f,0x38,0x91,0xbe,0x52,0xa9,0xa4,0x99,0x2a,0x40,0xad,0xef,0xf2,0xf6,0x4d,
+  0xa8,0xb1,0x3b,0x2a,0xf4,0xdf,0x91,0x67,0xff,0x03,0xf9,0xff,0xfd,0xec,0x3f,0x6d,
+  0x30,0x04,0x8a,0xde,0x2e,0x2a,0xde,0x41,0x06,0xf1,0xff,0x79,0xfb,0xdf,0xcb,0xff,
+  0x97,0x1a,0x25,0xd5,0xdf,0x6b,0x42,0x9e,0x89,0x77,0xd0,0x51,0x47,0xd1,0xf4,0x76,
+  0x87,0xe2,0x74,0x04,0xdf,0xe8,0xe9,0x50,0x3b,0x87,0x17,0xdc,0xfe,0x07,0x91,0x7f,
+  0xc6,0xff,0x17,0xb6,0x16,0xf1,0xf5,0xff,0x23,0xd1,0x5e,0xc7,0x2a,0xec,0x86,0x8e,
+  0xff,0x75,0xc1,0xfe,0xef,0x13,0x66,0x2f,0x21,0xb1,0x89,0xd2,0x57,0x3b,0xa8,0xfc,
+  0x2b,0x5d,0x26,0x0a,0xab,0xf3,0x37,0xbb,0x94,0x4e,0xa6,0x52,0x4f,0x25,0xd3,0x54,
+  0xe1,0x19,0xd0,0xfe,0xa7,0x5d,0x43,0x2c,0xb7,0xff,0x5c,0x68,0x33,0xde,0x8d,0xa6,
+  0xa2,0x42,0x33,0x9a,0xc2,0x94,0xf1,0x40,0xfe,0x3f,0x67,0xff,0x7b,0xf9,0xff,0xd4,
+  0x49,0x7b,0x85,0xb2,0xcd,0x6a,0xc2,0x12,0x3a,0xae,0x54,0x57,0x72,0xc6,0xae,0xfc,
+  0x3b,0x97,0xa3,0x14,0x4f,0xa2,0x45,0x93,0xfc,0xa2,0x74,0xab,0x9a,0x7f,0xa8,0x90,
+  0x3e,0xbc,0xde,0xf1,0x7f,0xda,0xfe,0xd3,0x0a,0x6d,0x77,0xf5,0xff,0xb2,0x9f,0xfd,
+  0x37,0xe8,0xa3,0x20,0xa7,0x87,0x4b,0x44,0x2a,0x49,0xb7,0x05,0xe6,0xa8,0xcd,0xf5,
+  0xa9,0xff,0x83,0xfc,0xef,0x0a,0xaa,0x88,0x96,0xe2,0x63,0xc9,0x68,0xf2,0x19,0x89,
+  0x84,0x50,0x16,0x92,0xf1,0xff,0x9d,0xbb,0x31,0xd1,0x1a,0x5d,0x4c,0xe4,0x78,0x4d,
+  0x32,0x49,0xad,0xc5,0xd9,0xbc,0x52,0xaa,0x35,0x5c,0x36,0x54,0xd5,0xd8,0x29,0x17,
+  0x62,0x39,0x27,0x7f,0xc0,0x2d,0x6c,0xc1,0xec,0x7f,0xb7,0xb7,0xff,0x4f,0x0b,0x1f,
+  0x12,0xa6,0x44,0xdb,0x54,0x37,0x8d,0xba,0x56,0x15,0xfc,0x10,0xaa,0x8c,0x07,0xb2,
+  0xff,0x9c,0xfc,0xf7,0xb2,0xff,0x9f,0xa5,0x4e,0xd9,0x2d,0x94,0x15,0x6a,0x05,0x25,
+  0x3d,0xa7,0xe9,0x86,0xba,0x69,0x36,0x12,0x42,0x5d,0xd8,0x95,0x25,0x52,0xf2,0xd3,
+  0xc5,0x56,0x26,0x62,0xe2,0x45,0x23,0xa3,0x45,0xe6,0xfa,0x94,0x34,0x77,0x87,0xdb,
+  0x7c,0xbb,0x5f,0x3c,0x54,0xdd,0xea,0x2c,0xc6,0xf2,0x45,0x72,0x8d,0x1d,0x59,0xbf,
+  0x4c,0x2d,0x21,0xc6,0xff,0xe8,0xf6,0xbf,0xab,0x68,0xff,0x13,0xec,0x4d,0x8e,0xe6,
+  0x33,0x65,0x53,0x45,0xa7,0xa7,0xb7,0x47,0xab,0x4e,0x89,0x80,0xfa,0xff,0xd5,0xc6,
+  0x96,0x9d,0x52,0x32,0x97,0x28,0x44,0xea,0xc6,0x8e,0xa9,0x37,0x6a,0x13,0xbc,0x88,
+  0xd0,0xa6,0x5c,0x90,0xff,0xf8,0x64,0xc3,0x8a,0xd2,0x96,0x2b,0xec,0x7a,0x69,0x6a,
+  0x2d,0x36,0xcc,0x18,0xca,0x6c,0x52,0x87,0xd0,0x34,0x33,0xe7,0xc8,0x9a,0xae,0xf5,
+  0x5c,0x67,0x37,0xd4,0x8d,0x65,0x6b,0xb5,0x6c,0x2d,0xcb,0xd1,0x71,0xe4,0xa3,0x29,
+  0xf5,0xff,0x19,0x25,0x32,0xe7,0x15,0x98,0x46,0x8e,0xd3,0x2e,0x54,0x0d,0x78,0xaf,
+  0xf1,0xbf,0x20,0xfe,0x3f,0xa3,0xad,0xa2,0x9e,0xbb,0x62,0x26,0xb8,0xcb,0xee,0xca,
+  0x7f,0xbd,0xfb,0x6c,0x28,0x41,0x67,0xc4,0x6d,0x76,0x18,0x5d,0xeb,0x76,0xc3,0x50,
+  0x39,0xef,0x3f,0x5d,0xdd,0x36,0x9c,0x6b,0x3c,0xdc,0x4a,0xb9,0x35,0x85,0xde,0xfe,
+  0xbf,0x5f,0xfb,0x7f,0x10,0xf9,0x97,0xc4,0xff,0x7c,0xda,0xff,0xca,0xcc,0x29,0x24,
+  0x6b,0xb4,0x6a,0x68,0x1a,0x85,0x49,0xe2,0x06,0xec,0xce,0xfe,0x43,0xfd,0x7f,0x00,
+  0x70,0x59,0x88,0xe6,0x0b,0xcc,0xe5,0x6f,0xe4,0x39,0x1f,0x93,0x2a,0x06,0xbc,0xff,
+  0xdf,0xed,0x78,0x6d,0x34,0x19,0xd6,0x05,0x18,0x72,0x7f,0x50,0xe9,0xa8,0x54,0xa9,
+  0x22,0x36,0x5a,0xaf,0xe3,0x2c,0x10,0x77,0x2f,0x5c,0xe0,0xbe,0x94,0x10,0x96,0x67,
+  0x90,0xdb,0x7f,0xba,0xb8,0x16,0x99,0x3c,0xd6,0x21,0x56,0x01,0x50,0xf2,0xbf,0xdf,
+  0xf6,0x3f,0xea,0xfd,0xe4,0xca,0x3f,0x53,0x8e,0x99,0xd0,0x8a,0xf6,0x3d,0xe6,0xb8,
+  0x5c,0x59,0xda,0x1c,0xd2,0x36,0xb9,0x53,0x66,0x5a,0x10,0xdc,0x8a,0xc2,0x30,0x7b,
+  0xdb,0xbc,0x84,0x0a,0xeb,0x68,0x96,0x9c,0x9b,0x4c,0x7b,0xde,0xbb,0x6b,0xff,0xf3,
+  0xb5,0xff,0x81,0xe3,0x7f,0xb4,0x96,0x51,0x72,0x62,0x73,0x71,0x3d,0x9b,0x2a,0xf9,
+  0xda,0x7f,0xa8,0xff,0xef,0x1b,0x93,0xa5,0x50,0x47,0xcc,0xd6,0x59,0x8b,0xd2,0xb7,
+  0x87,0xae,0x62,0x72,0xf2,0xcf,0x44,0x9f,0xa6,0x16,0x98,0x02,0xe8,0x65,0x69,0xd2,
+  0xe6,0xbf,0x94,0x90,0x66,0x07,0xd6,0x13,0x49,0xaf,0xf6,0xbc,0xc3,0xd6,0x0d,0xe3,
+  0xab,0x3d,0x4f,0x41,0x2e,0xff,0x74,0xf5,0x5f,0x63,0x97,0xcf,0x33,0x5b,0xa7,0x24,
+  0x60,0xbf,0xeb,0xff,0x32,0xa3,0x44,0x07,0x37,0xe6,0xd8,0x4b,0xb1,0xc0,0x78,0x00,
+  0x13,0x53,0xfe,0x30,0x4d,0x78,0x8e,0xa3,0xc5,0x99,0xff,0x09,0x69,0xfe,0x36,0x86,
+  0xf6,0xff,0xf7,0xd7,0xfe,0x07,0xf6,0xff,0xe9,0x68,0x9e,0x32,0x27,0xcd,0x0b,0xde,
+  0xe9,0xa4,0xe8,0x0e,0xa6,0xf4,0x1a,0x7d,0xfc,0x7f,0xc8,0xff,0x0b,0xce,0xda,0x82,
+  0x54,0x1c,0x1b,0x51,0xba,0x28,0x51,0x57,0x94,0x93,0xff,0x16,0xb3,0x96,0xca,0xa4,
+  0xaa,0x7a,0xbe,0x38,0x5d,0xfb,0x9f,0xf4,0x4b,0x0e,0xd6,0xa9,0x9b,0xaa,0xb3,0x69,
+  0xbb,0x63,0x6d,0x9f,0x75,0xac,0xbd,0x4a,0xe5,0x9f,0xb2,0xcb,0xbc,0xbb,0x68,0x30,
+  0x5b,0xa7,0x34,0xd8,0x7e,0xc7,0xff,0xa9,0x8b,0xe8,0x1a,0x25,0x7a,0x5b,0x7c,0xe3,
+  0x1b,0x13,0xbe,0xe3,0x3b,0x1a,0x30,0x30,0x39,0x41,0xf6,0xd5,0x61,0x64,0x4a,0x49,
+  0xf9,0x8a,0x7f,0x1f,0xff,0x7f,0xe0,0xfc,0x9f,0xdd,0xb4,0xff,0xd1,0xc5,0x48,0xde,
+  0x2d,0x60,0x0a,0xf7,0x4d,0xa1,0x3e,0x80,0xff,0x7f,0x4d,0xe9,0x30,0x4e,0xb2,0x57,
+  0x4a,0xd8,0xfa,0x3f,0xdf,0x11,0xc3,0x8c,0xd2,0xbf,0x3a,0xa5,0x47,0xa7,0x6e,0x4e,
+  0x8f,0x62,0x49,0xc3,0xb5,0x0d,0xf7,0xec,0xd2,0x21,0x97,0x7f,0x4a,0x15,0x09,0x79,
+  0xe7,0x4c,0x38,0x42,0xf3,0xbe,0xdf,0xab,0xfd,0xef,0x51,0xff,0x2f,0x49,0xe4,0xbf,
+  0xc4,0x0b,0x1f,0x73,0xf9,0x72,0x53,0x3d,0xa0,0x85,0xd1,0xe9,0x28,0xc0,0xa8,0xe6,
+  0x38,0x9f,0xb8,0x49,0x11,0xdc,0xff,0x1f,0xb8,0xfe,0x2f,0x6c,0x4d,0x6e,0xff,0xe9,
+  0x5b,0x16,0xd0,0x5d,0xa7,0xe5,0xff,0x19,0xf0,0xff,0xaf,0x36,0x9b,0x8c,0x8d,0xf4,
+  0xaa,0xf2,0xac,0xfd,0x17,0xb2,0x47,0x98,0x46,0x37,0xa7,0x06,0xab,0xf5,0x30,0x79,
+  0x7e,0x70,0xf9,0x02,0x92,0x7c,0x42,0x17,0x79,0xfe,0x2f,0x65,0x4b,0x05,0x73,0xc1,
+  0x68,0x0c,0xcd,0xfb,0x7e,0x37,0xf5,0xff,0x80,0xf9,0x3f,0x6e,0xa1,0x6c,0x50,0x27,
+  0xc6,0xe5,0x48,0xb0,0x0e,0x40,0xae,0x97,0xfd,0xa7,0x17,0xb4,0xfd,0x2c,0x95,0xa9,
+  0x34,0xf5,0x1a,0x9b,0x31,0xb8,0xff,0xbf,0xf7,0xfa,0xbf,0x2e,0x8d,0xff,0xd1,0x5e,
+  0x41,0xc0,0x51,0xa4,0xfb,0xc4,0xff,0xa9,0x4b,0x0d,0xf6,0x7f,0x3f,0x60,0x9a,0xa9,
+  0xbc,0xd2,0xc4,0xc8,0xbf,0x18,0x87,0x61,0x42,0xf7,0x8e,0xdd,0xad,0xf4,0x5a,0xc3,
+  0x8f,0x0e,0x1b,0xcc,0x9a,0xf3,0x2f,0xcf,0xf2,0xfc,0x9f,0x55,0x6a,0x65,0xc1,0x16,
+  0xd2,0xe2,0xa3,0x79,0x5f,0xef,0xb7,0xfd,0x97,0xb5,0xff,0x99,0x94,0xa5,0x12,0x8a,
+  0x3e,0xad,0x1c,0x7a,0x8d,0xae,0x64,0xd2,0x0a,0xcc,0xb6,0xff,0xf4,0x86,0x95,0x78,
+  0xaf,0x1a,0x53,0xf0,0xfc,0xff,0x40,0xf6,0x9f,0xba,0x51,0x41,0xf3,0x7f,0x33,0xc2,
+  0xd1,0xf7,0x05,0xda,0xff,0xaf,0x2d,0x74,0x77,0x4f,0xaa,0xbe,0xc7,0xc8,0xbf,0x58,
+  0x44,0xd5,0x4b,0x62,0x21,0xa4,0xa3,0xff,0x3d,0x9d,0x5a,0x76,0x4b,0x5c,0x03,0xf1,
+  0x90,0xbf,0x02,0x90,0xda,0xff,0x1e,0x71,0x36,0x56,0xd0,0x29,0xe5,0x70,0x2d,0xe2,
+  0xff,0xb4,0x63,0x95,0xe4,0xab,0x35,0x06,0x95,0x05,0xd0,0xc3,0x2e,0x1a,0x4c,0x04,
+  0xd3,0x8e,0xce,0x30,0x69,0x82,0xa2,0x20,0x52,0xec,0xdd,0xfe,0x0f,0xd0,0xff,0x47,
+  0x6a,0xff,0x29,0x8b,0x10,0xf5,0xab,0xfd,0xf3,0x1b,0x82,0xf6,0xff,0x6b,0x0a,0x13,
+  0x61,0x2a,0xca,0xed,0xbf,0x58,0x78,0xd8,0xce,0xea,0x1a,0xf9,0x8a,0xbe,0x37,0x31,
+  0x71,0x0d,0x3f,0x54,0xa6,0x89,0x48,0x29,0xf9,0xd6,0x1c,0x7c,0xf2,0x7f,0xe8,0x12,
+  0xc1,0x8f,0x72,0x51,0xf7,0x4a,0x25,0xdd,0x63,0xe8,0x2a,0xd6,0xff,0xbd,0x42,0x49,
+  0xcb,0x2e,0xdf,0x7d,0x8f,0x8e,0xeb,0xfb,0xca,0xbf,0x5a,0x60,0x93,0xfc,0xa3,0x96,
+  0x58,0xd1,0xfd,0x73,0x94,0x15,0xbf,0x95,0x31,0x7b,0xef,0xff,0xb7,0xc7,0xf8,0x7f,
+  0x93,0xaa,0xaa,0xf4,0x70,0xec,0x18,0xc0,0xfe,0x5f,0x5b,0x18,0xe9,0x93,0xcb,0xbf,
+  0xec,0x42,0x67,0xe8,0xd5,0x2c,0x69,0xa7,0x2a,0x7b,0x38,0x57,0x4d,0x45,0x0f,0xf2,
+  0xc2,0x3f,0xac,0x17,0x0f,0x2e,0x99,0x3d,0xad,0xf9,0x1c,0xa9,0x3c,0xff,0x87,0xc9,
+  0x63,0xef,0x6a,0x6c,0x29,0xa3,0xd3,0x1e,0x29,0xff,0xf3,0x2a,0xda,0x7f,0xaf,0x52,
+  0x4a,0x0f,0x32,0x22,0xe4,0x42,0x50,0x86,0x51,0x2e,0xff,0x6a,0x24,0x5b,0xe4,0xb2,
+  0x33,0x6c,0x2f,0x8c,0x56,0x44,0x25,0x7e,0x18,0x24,0x86,0xab,0xd7,0xfe,0xd7,0x3b,
+  0xff,0xc7,0xf5,0xff,0x55,0xea,0xc2,0xb4,0xa6,0xc8,0xad,0x97,0x15,0x08,0xa6,0x3c,
+  0x40,0xfb,0xff,0x35,0xa5,0x4e,0xdd,0x22,0xfa,0x7e,0xd3,0xf2,0x2f,0x8e,0xe7,0xc0,
+  0xe5,0xee,0x5b,0x89,0xc3,0x4c,0x03,0x51,0x6e,0x22,0x97,0x23,0x7f,0x3c,0xe4,0x3b,
+  0xb6,0x33,0x5b,0x9d,0x6d,0x05,0xec,0xfa,0xdc,0x57,0x9f,0xfe,0x7f,0xcc,0x91,0xc4,
+  0xab,0xcc,0x08,0x63,0xd4,0x2a,0x03,0xdb,0x7f,0xae,0x88,0xf7,0x8a,0xff,0x49,0x0b,
+  0xe5,0x26,0x63,0xbd,0x8b,0x19,0x46,0x03,0x50,0x81,0x09,0x89,0xfc,0x1b,0xed,0x84,
+  0x90,0x9c,0xe9,0xb6,0x22,0xd0,0x8d,0xac,0xa2,0x81,0xa4,0xb9,0x8a,0xf6,0xbf,0x67,
+  0xfe,0xbf,0x5b,0x5e,0xe8,0x5e,0x27,0xa9,0x09,0x79,0x79,0xb0,0x99,0x74,0x2e,0x0f,
+  0xb4,0xff,0x5d,0x4b,0xd8,0x96,0x7c,0x2a,0x97,0x9f,0x6e,0xff,0xe3,0x45,0x01,0x43,
+  0xd7,0xf7,0xec,0x22,0xdc,0x77,0x8c,0x01,0xdf,0xf2,0xc3,0x75,0x11,0xf3,0x69,0x3b,
+  0xf4,0xb1,0xff,0x4d,0xb6,0xcf,0x41,0xba,0x18,0x1b,0xd6,0x0d,0x43,0x25,0x50,0xdd,
+  0xec,0x69,0x53,0x79,0x2d,0xea,0xff,0x7c,0xf7,0xff,0x52,0xaa,0xa2,0xe1,0xc4,0x7e,
+  0x8b,0x1e,0xf2,0xaf,0xb6,0x2b,0x29,0x59,0xc7,0x28,0xbb,0xf9,0x9c,0xc9,0xb1,0xec,
+  0x5d,0xa9,0xbe,0xa6,0xf6,0x5f,0x16,0xff,0xd3,0xfb,0x77,0x06,0x75,0x70,0x75,0x06,
+  0xd4,0xff,0xaf,0x25,0xdc,0x08,0x35,0x5e,0xb5,0x9d,0xb6,0xff,0xb2,0x20,0x13,0x13,
+  0x85,0xb6,0x3c,0xd3,0xdd,0xcb,0xff,0xd4,0x12,0xdb,0xa1,0x65,0x42,0x3a,0xae,0x98,
+  0x5f,0xff,0x7f,0x9d,0xef,0x5f,0x8e,0x7b,0x98,0x15,0x09,0x21,0xef,0xf4,0x68,0xfb,
+  0x5f,0xb8,0x7a,0xf5,0x7f,0xca,0x28,0x89,0xe3,0x92,0xc4,0x93,0xa9,0x90,0x75,0x60,
+  0xbe,0x8d,0x03,0x86,0xc6,0xbb,0xfd,0xce,0xba,0x0b,0x92,0xab,0x20,0xda,0x61,0x9a,
+  0x6b,0x5a,0xff,0x97,0xd9,0xff,0x72,0x70,0xf9,0x77,0x4d,0x3d,0xd4,0xff,0xaf,0x1d,
+  0x66,0x85,0x2d,0x6b,0x94,0x8c,0xd0,0xf6,0x5f,0x96,0xa1,0xca,0x74,0xbb,0xb3,0x8a,
+  0x49,0xcf,0xf1,0x6b,0x58,0x84,0x72,0xbb,0xca,0x1e,0x88,0xbc,0x55,0xdb,0x6f,0xfc,
+  0xcf,0xb5,0x20,0xc5,0x6c,0xaf,0xf1,0xbf,0x41,0xdb,0xff,0xf1,0xe5,0xbd,0x10,0xe4,
+  0x5a,0x30,0xf2,0xdf,0x98,0xf0,0x51,0xa2,0x25,0x47,0x44,0x19,0xf9,0xef,0x19,0xfe,
+  0xdf,0x07,0xfb,0x1f,0x3c,0xfe,0x2f,0xad,0xff,0x07,0xeb,0xe0,0x6d,0xad,0x23,0x93,
+  0x7f,0x49,0xfd,0x3f,0xea,0xfd,0x0a,0xf2,0xbf,0x37,0xd4,0x4c,0x8a,0x2b,0x6c,0x3e,
+  0x89,0x9b,0xb2,0x0c,0x55,0x89,0xfc,0x67,0x82,0xdb,0x7f,0x71,0x8b,0x5b,0x6c,0x5f,
+  0xd7,0x96,0xb0,0xc3,0x5e,0xe3,0x7f,0x6a,0x01,0x46,0x37,0x28,0xed,0xb1,0xfd,0x8f,
+  0xb6,0xff,0x15,0xf6,0x27,0x5f,0xa3,0xa4,0xf3,0x7d,0xdf,0x65,0x54,0xa9,0xc1,0xef,
+  0x56,0xfd,0x86,0xca,0x29,0xb9,0xcd,0xa2,0x03,0xc8,0xff,0xde,0xf3,0x7f,0xfd,0xec,
+  0xbf,0x58,0x23,0x94,0xda,0xff,0x41,0xe4,0x5f,0xe6,0xff,0x83,0xfd,0xbf,0x7a,0x98,
+  0x99,0x90,0x70,0x77,0x28,0x53,0xc4,0xd8,0x7f,0x99,0xff,0x1f,0xa5,0x16,0xb0,0x86,
+  0xd6,0x5b,0x08,0x7c,0xb3,0x25,0xe9,0x01,0x4d,0x76,0x84,0xe1,0xb8,0xe8,0xaf,0xfa,
+  0x8f,0xff,0x39,0x35,0xb5,0x5d,0xec,0xab,0x7b,0xe8,0xf8,0x7f,0x10,0xfb,0xdf,0x6b,
+  0xfc,0x4f,0x5e,0xfe,0xa9,0x6b,0xc1,0x16,0xca,0x1d,0xbe,0x87,0xa5,0x04,0xea,0xa2,
+  0x77,0xfc,0x1c,0x99,0xee,0xa8,0xab,0x24,0x76,0x69,0xff,0xc5,0x56,0xd5,0xbd,0xd8,
+  0x7f,0x31,0xee,0x20,0x8d,0xff,0x95,0x83,0xcb,0xbf,0x7b,0xb9,0x69,0xf9,0x8f,0x43,
+  0xfc,0xef,0xea,0xa0,0x46,0x86,0xa2,0xa2,0xc4,0xd0,0xc9,0x64,0x4c,0xc7,0x0d,0x99,
+  0xfc,0xd3,0x26,0xd7,0xaa,0xff,0x17,0x82,0xdb,0xff,0x49,0x71,0x83,0x9b,0x5c,0x18,
+  0x4f,0xcc,0x6b,0xf7,0xb7,0xff,0xa8,0x5c,0xd4,0xa2,0x7d,0x76,0x39,0xa8,0xfd,0xe7,
+  0x3b,0x13,0xd0,0xf6,0x9f,0x0b,0xd9,0xf5,0x28,0x94,0x6a,0xc1,0xcf,0xa1,0x97,0x6c,
+  0xcc,0x6f,0xc0,0xc0,0x74,0x95,0xca,0x1f,0x62,0x32,0xaf,0x64,0x91,0x59,0x0f,0xda,
+  0xfe,0x0f,0x09,0xbf,0xee,0xc5,0xfe,0x8b,0x2d,0x42,0xf2,0xf8,0x9f,0xcf,0x2c,0x10,
+  0x12,0x42,0x52,0xf9,0x17,0x72,0x06,0xc1,0xfe,0xef,0x03,0xa6,0x96,0x93,0x1a,0x1a,
+  0x3a,0x45,0x83,0xb6,0xff,0xb2,0xf9,0x1c,0x18,0xd7,0x2e,0x2f,0x7e,0xd5,0x1b,0x59,
+  0x4f,0x7f,0x6e,0x48,0x4b,0xb1,0x2b,0x90,0x4f,0xfc,0xdf,0x59,0xbd,0x53,0xec,0x59,
+  0x0b,0xa0,0xe3,0xff,0x41,0xec,0x3f,0xef,0x7b,0xd2,0xf5,0x7f,0x2e,0x65,0xbf,0x67,
+  0xa5,0x74,0x73,0xb8,0x9a,0xec,0xa9,0x02,0x5c,0xf9,0x97,0x0f,0x18,0x58,0x4a,0xe6,
+  0x1b,0x4d,0x7a,0x83,0xb4,0x54,0xf7,0x4e,0xb3,0xa6,0xed,0xbf,0x98,0xc2,0xb9,0x97,
+  0xf8,0xbf,0xd8,0xf5,0x56,0xea,0xff,0xef,0xf4,0x1d,0xf9,0x53,0xdc,0x13,0x33,0x9c,
+  0xa3,0xc6,0xef,0x06,0xec,0xff,0x9e,0x89,0x24,0x24,0xa6,0x1f,0xc3,0x64,0xa9,0xf6,
+  0xcb,0xff,0x61,0x06,0xab,0xb5,0x8a,0x0f,0xad,0xed,0x8b,0xd5,0x39,0xf2,0xb0,0xff,
+  0x91,0x37,0xd4,0xcf,0xe2,0x6c,0x54,0xf8,0xc0,0x9e,0x62,0x0e,0x27,0xc4,0x77,0x05,
+  0xea,0x65,0xff,0x31,0xcd,0x48,0x67,0x32,0x94,0x4c,0x97,0xe4,0x67,0x37,0xa8,0xfd,
+  0xe7,0x4f,0x9a,0x96,0x7f,0xce,0x21,0xea,0x53,0x28,0x9b,0x66,0xa1,0x35,0x11,0x4d,
+  0x8b,0x93,0xaf,0x59,0xb8,0xf2,0xbf,0x2d,0x2a,0xe5,0x52,0x72,0x2e,0xc3,0x2b,0x5f,
+  0xda,0x6e,0xf7,0x36,0x81,0xb4,0xa6,0x10,0x7d,0xb8,0xbd,0x8c,0xff,0x29,0x5e,0xfe,
+  0x86,0x2c,0xff,0x4f,0xa5,0xd2,0x9c,0x53,0xb8,0x18,0xcc,0x79,0xe5,0x01,0x97,0x88,
+  0xa8,0xf7,0xb3,0x5b,0xa5,0x62,0xe4,0x5f,0xb0,0x13,0xd0,0xff,0x7f,0x8f,0x34,0x26,
+  0xfd,0x7c,0xb2,0x34,0x13,0x22,0x62,0xfa,0xff,0x4a,0x52,0x72,0x99,0x2e,0xec,0xd6,
+  0x9a,0x3b,0xd4,0xed,0x14,0x04,0xbc,0x49,0xe7,0xc3,0xf8,0xf4,0x05,0x69,0xb3,0x06,
+  0x9c,0x1f,0x5a,0xdc,0x67,0xfc,0x4f,0x76,0x37,0x66,0x64,0x38,0xb3,0x18,0x4b,0x24,
+  0x2a,0xf9,0x4a,0xa5,0x92,0xcf,0x7b,0x5b,0x1c,0xd4,0xfe,0x97,0xb8,0x53,0xa0,0xc5,
+  0x2e,0xc9,0xaa,0xa6,0x00,0x41,0xe9,0xa6,0xa1,0xb7,0xb5,0x4e,0x2d,0x91,0x18,0xc2,
+  0x87,0x55,0xa9,0x50,0xbe,0x8e,0x5b,0x17,0xe2,0x07,0xf5,0x2c,0x45,0xf3,0x9a,0xd9,
+  0x14,0x36,0xc5,0x64,0x66,0xf7,0xec,0x66,0x49,0xcb,0x7f,0x52,0xf0,0x14,0xe8,0x5f,
+  0x07,0xb5,0xff,0xa2,0x60,0xb6,0xa5,0xfd,0x7f,0xa8,0x7d,0x54,0xa6,0xb8,0x53,0x69,
+  0x4e,0x35,0xa9,0x6b,0xea,0x9e,0x08,0x23,0xff,0x42,0x9c,0x88,0x1e,0x1d,0x1c,0xec,
+  0xff,0xc0,0xe8,0x15,0xdf,0xa6,0xb2,0x67,0xd9,0x94,0x7d,0xa6,0x94,0x1d,0x10,0xab,
+  0x99,0x74,0xe9,0x71,0x44,0x8b,0x8a,0x76,0x4b,0x1c,0x7c,0x4a,0x4a,0xc6,0xea,0xf2,
+  0xc3,0xe3,0xe6,0x0e,0x60,0xb3,0x04,0xfb,0xda,0x7f,0x09,0xaa,0x5c,0xe7,0xf8,0xda,
+  0x7f,0xba,0x06,0xc3,0x35,0x41,0xd0,0xee,0x32,0x27,0xe4,0xbb,0x70,0x4a,0x29,0xf5,
+  0xea,0x58,0xbe,0x26,0x37,0x18,0x52,0x4e,0xdb,0x91,0xae,0xca,0x84,0x59,0x7a,0x0e,
+  0x1e,0xc2,0x6c,0x50,0xb8,0x60,0x74,0x75,0x2b,0x90,0xfd,0xa7,0x2f,0x8e,0xb0,0xdf,
+  0x35,0xea,0x47,0x2f,0x3a,0xb0,0x22,0xdf,0x94,0x83,0x57,0x88,0xbc,0xc1,0x4d,0x19,
+  0xf9,0x17,0x6a,0x9e,0x74,0x46,0x11,0xd4,0xff,0x07,0x44,0xed,0xf8,0xd7,0xc7,0xd2,
+  0xa3,0xac,0x7a,0xee,0xd3,0xff,0x97,0xb9,0x4b,0x4e,0x55,0x99,0xba,0xdb,0x92,0x94,
+  0x01,0xaa,0x86,0xe8,0x1b,0xb6,0x62,0xa7,0xf2,0xe0,0xe6,0x16,0xe8,0x5d,0xff,0x97,
+  0xb2,0x19,0x95,0x96,0x96,0x20,0xf6,0x9f,0x3f,0x05,0xa6,0x72,0xce,0x9a,0x5d,0x73,
+  0x70,0xf9,0xa7,0x6a,0x13,0x4e,0x64,0x8e,0x1b,0xc8,0x58,0xf3,0x5b,0x95,0xbd,0xf4,
+  0xbd,0x76,0xc7,0xf4,0xab,0xe0,0x43,0xae,0x9b,0xf4,0xee,0x06,0x8d,0xff,0x33,0x83,
+  0xbe,0x12,0xe8,0x6e,0xa4,0x9e,0xd4,0x52,0x29,0x61,0x51,0x31,0x88,0x44,0x9d,0xb1,
+  0x17,0x6d,0x61,0x4e,0x8f,0x1a,0xf3,0xd8,0x3e,0x08,0x4a,0x09,0x81,0xfc,0x0f,0x86,
+  0x39,0xe9,0x1f,0xa0,0x4b,0x69,0xdc,0xc2,0xec,0xf8,0x1f,0x42,0x77,0x3e,0x66,0xd8,
+  0x20,0xa7,0xa9,0x9c,0xb2,0x4c,0x62,0xe6,0x26,0x5d,0xae,0x24,0xe1,0x7f,0x8b,0x26,
+  0x3b,0x66,0x27,0xdb,0x9f,0x6f,0x17,0xf6,0xdf,0xf4,0x2a,0x3b,0x74,0x3c,0x2f,0x48,
+  0xfd,0x5f,0x19,0x63,0x8a,0x38,0x3b,0xea,0x06,0x1b,0x00,0xa4,0x63,0x5f,0x82,0x60,
+  0xc8,0xa1,0xb4,0x89,0xa3,0xe4,0x46,0x18,0xb9,0xf6,0xef,0x2d,0xcf,0x1e,0x49,0xbe,
+  0xc7,0x4e,0xe8,0xf8,0x1f,0x5f,0x67,0x61,0x63,0xf3,0xb4,0x3e,0x0b,0xe4,0xff,0x0b,
+  0x25,0x82,0x76,0x8f,0xbc,0xd6,0x41,0x4a,0x98,0x25,0x1a,0x9b,0x8a,0x19,0x78,0xe1,
+  0x09,0x76,0x3a,0x17,0x3e,0x6c,0x49,0xab,0x99,0x80,0x97,0x1a,0xb0,0xe8,0x31,0x09,
+  0x63,0xba,0x22,0x28,0x67,0x76,0xfc,0xaf,0x28,0x57,0x78,0xd8,0x91,0xf5,0x1c,0x71,
+  0xa6,0xed,0xa0,0x30,0xe4,0x0d,0x5d,0x6c,0xa5,0xe1,0x3f,0x6b,0x29,0x36,0x06,0xde,
+  0xa5,0xc5,0xa0,0x47,0xfb,0xbf,0x1f,0x94,0x46,0x4a,0x52,0xd1,0x84,0x40,0xf6,0x9f,
+  0x35,0xf2,0x06,0xe3,0x3a,0xb1,0xba,0x81,0xf6,0xc8,0x83,0x0d,0x7c,0x42,0xf7,0xff,
+  0xd7,0xec,0xef,0xe8,0xaa,0x2d,0x3d,0x59,0xa1,0x00,0x73,0x6b,0x7a,0x28,0x0a,0xd6,
+  0xfe,0xf3,0x12,0xcb,0x74,0xe0,0xd4,0xa8,0x1f,0x82,0xc9,0x3f,0x97,0x01,0xb0,0x49,
+  0x4f,0x6b,0xe0,0x65,0x25,0xd0,0x75,0x1a,0x31,0xa7,0x93,0x72,0x82,0xbc,0x8c,0x0a,
+  0x56,0xfe,0x79,0xff,0x86,0x2e,0x1e,0xb2,0x66,0x29,0xc0,0x0f,0xff,0x29,0xa3,0xe2,
+  0x73,0xed,0x3e,0x51,0x26,0x64,0x66,0xd8,0x9b,0x97,0x65,0xca,0x82,0x1b,0x38,0xa4,
+  0x42,0xca,0x51,0x5e,0x0e,0x28,0xcf,0x6d,0xac,0xec,0x7f,0x98,0x26,0x5b,0x0b,0xa6,
+  0x5b,0x01,0xfd,0xe6,0xff,0x44,0xe8,0x9a,0x7c,0x6b,0x54,0x37,0x5b,0x5a,0xce,0x03,
+  0xd9,0x7f,0x76,0xd0,0x43,0xae,0x71,0x93,0xc9,0x00,0xa2,0x9b,0x06,0xd8,0x42,0xa9,
+  0x4a,0xc6,0x5c,0xe6,0x2e,0x86,0xdb,0xc6,0xcd,0x14,0x7c,0x5f,0x0f,0x69,0x8a,0x9f,
+  0xcb,0x4d,0x68,0x26,0xf1,0x60,0xec,0x3f,0x37,0x51,0x13,0x23,0x49,0x4c,0xa5,0x25,
+  0x90,0xff,0xcf,0x87,0x47,0x98,0xe0,0x00,0xa5,0x35,0x28,0x7b,0x1d,0xe7,0xfb,0x2a,
+  0x53,0x29,0x64,0x94,0x9f,0xcf,0x4d,0xe7,0xc6,0x7a,0x5a,0x4c,0x57,0x8f,0xa0,0x23,
+  0x8a,0x00,0x53,0x53,0x4c,0xac,0x95,0x21,0x5d,0x6d,0xcb,0x6a,0xe3,0xdc,0xfc,0x1f,
+  0xec,0xec,0xa0,0xec,0xa8,0x9d,0x9e,0xc9,0xa3,0x0d,0x21,0xa7,0x31,0xe8,0x69,0xa0,
+  0x7a,0x0e,0x0e,0xa4,0xb3,0x13,0xe4,0xd0,0x5d,0x81,0xfc,0xed,0x7f,0x21,0x5d,0x95,
+  0xd9,0x5d,0xdd,0xa7,0x9b,0x4d,0x30,0xfb,0x4f,0xd7,0x8a,0xf9,0xcb,0x97,0xa6,0x0a,
+  0xb3,0x49,0x1f,0x31,0xdb,0xce,0x66,0xa4,0x8a,0x05,0xc9,0xd5,0xa5,0xbd,0x1c,0x57,
+  0x61,0x30,0x3d,0xaa,0x7a,0x0d,0x0a,0xd8,0x64,0x35,0xb9,0xd0,0x4c,0xe2,0xc2,0x69,
+  0xfc,0x1c,0xbd,0x20,0x23,0xb0,0x4c,0x3a,0x4f,0xa0,0xf8,0x1f,0x37,0xf0,0x28,0x3b,
+  0x24,0x39,0x75,0xdd,0x68,0x69,0x2e,0xb2,0x07,0xaa,0xd2,0x83,0x03,0x99,0xd2,0x35,
+  0x10,0xa5,0x18,0x7d,0x25,0x98,0x26,0x92,0x5e,0x03,0xa7,0x01,0x1c,0xf2,0xb9,0xa8,
+  0x4b,0xa9,0xc4,0xba,0xbc,0xa4,0xf1,0xf3,0x7f,0xc4,0xb3,0xde,0x72,0x0d,0xb6,0xbf,
+  0xbe,0x77,0x1f,0xa8,0xee,0xb6,0xdc,0xf8,0xff,0x6a,0xc5,0x13,0x2d,0xbe,0x65,0x8d,
+  0xa3,0xcd,0x06,0x29,0x3d,0xb7,0xb1,0x47,0xfd,0x5f,0x2b,0x29,0xc9,0x84,0x60,0x08,
+  0x19,0x97,0x87,0x4e,0x28,0x0e,0x66,0xff,0x95,0xb8,0xd7,0x22,0x3a,0xcc,0xb7,0x9b,
+  0xa4,0x5c,0x6b,0xaa,0x32,0x63,0xa1,0xb2,0x85,0xd2,0xe8,0xe2,0x11,0x09,0xf8,0xe3,
+  0x52,0x47,0xa9,0x9b,0xe1,0x46,0xd2,0xe9,0xc6,0x72,0x25,0x3e,0xd3,0xe3,0x0a,0xad,
+  0xb1,0xf7,0x72,0x82,0x4b,0x39,0x74,0xdf,0xb1,0xf6,0x1f,0x5d,0x4a,0x4f,0xca,0x46,
+  0x98,0x64,0x2b,0x46,0x69,0x05,0xf3,0xff,0xf1,0x58,0x2b,0xde,0x6f,0xac,0x3f,0x48,
+  0xdf,0x1b,0x3a,0x2e,0xc0,0x8e,0x82,0x44,0x0f,0xfc,0x48,0x65,0x27,0xf2,0xd3,0xb9,
+  0xc6,0x29,0x05,0xc0,0x0e,0x16,0xdb,0x67,0xba,0x18,0x80,0x82,0xad,0xb0,0x3b,0x77,
+  0x70,0x4e,0xf3,0xb5,0x1d,0xc2,0xfc,0x9f,0xa5,0xaa,0x3d,0x35,0x95,0x31,0xca,0x0a,
+  0x68,0x5c,0xf3,0xd6,0x5a,0xa5,0x1b,0xd0,0x27,0x3d,0x93,0x3c,0x42,0x67,0xf7,0x7b,
+  0x7e,0x9b,0xa1,0x65,0x6c,0xe8,0x37,0xdc,0x1c,0x82,0x6e,0x05,0xb7,0x47,0xfd,0x9f,
+  0x54,0x66,0xa3,0x43,0x0d,0x36,0x2c,0x47,0x8b,0x3f,0x93,0x2c,0x12,0xd0,0xfe,0x2b,
+  0xf1,0x84,0x69,0x1f,0xa7,0xd8,0x70,0x12,0xb5,0x87,0x1a,0x32,0x13,0x8c,0x34,0xb2,
+  0x71,0x0f,0x62,0xd3,0xd3,0xdc,0x65,0x36,0x62,0x74,0x31,0xf6,0x4a,0x31,0x33,0x12,
+  0x53,0x88,0xf1,0xd6,0x8d,0x46,0x82,0xae,0x08,0x71,0x86,0x3d,0xd9,0xd2,0x5d,0x25,
+  0x12,0xc9,0xce,0xc9,0x5a,0xdf,0xed,0x8d,0xda,0xc7,0xac,0x36,0xd8,0x5c,0xcb,0x65,
+  0x7a,0x5f,0x01,0xfd,0x7f,0x74,0x75,0x5a,0xf6,0x0d,0x1e,0x61,0x2f,0x01,0x93,0x6a,
+  0x10,0x79,0x86,0xde,0x9c,0xa7,0xa9,0x8c,0x1a,0xb5,0x0e,0x1d,0xc9,0x13,0xa6,0x73,
+  0x2e,0x39,0x0a,0x54,0xcd,0x30,0x77,0x41,0xa8,0x4f,0x00,0xfe,0x88,0x7d,0xf3,0x4a,
+  0xa1,0x58,0x8f,0x6a,0xb8,0x74,0xfe,0xcf,0x5c,0x2c,0x53,0x18,0xad,0xf0,0x9d,0x06,
+  0xe9,0x3e,0x28,0x6c,0x6c,0x3a,0xda,0x9a,0x31,0xf1,0x20,0x1c,0x91,0x1a,0x6d,0xda,
+  0xa8,0x01,0xfe,0x1a,0x38,0x27,0xce,0x7a,0xe2,0x97,0x92,0xfb,0x9e,0x5e,0xdc,0x95,
+  0xf4,0x1e,0xf6,0xdf,0x0e,0x66,0xc5,0x8b,0xad,0x82,0x6e,0x0d,0xb1,0xa1,0x17,0xf2,
+  0x4c,0x69,0x61,0x7a,0xca,0x04,0xb4,0xff,0xf8,0x14,0x26,0x47,0x0b,0x99,0xd8,0x84,
+  0xcc,0x79,0x8a,0x17,0x13,0x99,0x42,0xa7,0xc2,0x56,0x57,0xb8,0x8c,0x75,0xbb,0x97,
+  0x44,0x29,0x35,0x99,0x89,0x18,0xc6,0x14,0x3a,0xae,0x91,0x46,0x8d,0x51,0xc5,0xf4,
+  0x78,0x21,0xcc,0xde,0x93,0xad,0x06,0x39,0x13,0xc3,0x6c,0x64,0x26,0x53,0xf1,0x12,
+  0xed,0xbf,0xb4,0x79,0x19,0x19,0xcb,0xb5,0x32,0x85,0x42,0xa6,0x36,0x59,0x4c,0x53,
+  0xc2,0xc4,0xdb,0x7f,0x7c,0xd3,0x2b,0x9d,0x82,0x16,0xe3,0xd2,0xbf,0x59,0x49,0x0a,
+  0xe8,0xff,0x93,0x63,0x3c,0x50,0xd3,0x84,0x4b,0xc0,0x56,0xef,0x9a,0xcc,0x00,0x33,
+  0x63,0x93,0x05,0x93,0xdc,0x9d,0x0e,0xd3,0x61,0x6b,0x92,0x8a,0x3f,0x49,0xa6,0x73,
+  0x4f,0x4f,0xa0,0x82,0x97,0x69,0x85,0xd8,0xbb,0xc3,0x77,0xd0,0x04,0x7a,0xc0,0x9b,
+  0x82,0xd2,0x44,0xa6,0xf7,0xe5,0xf3,0x99,0xff,0x5b,0xd2,0x69,0x48,0xa3,0x57,0x6b,
+  0x3f,0xc3,0xfe,0x98,0x2c,0x4e,0x14,0xb9,0xd1,0x6c,0xa8,0x6a,0xe0,0x76,0x80,0x1e,
+  0x03,0x54,0xa4,0x8f,0x2e,0x67,0xac,0xfc,0x7b,0x63,0x62,0x96,0xd2,0xd1,0xd0,0xc4,
+  0x44,0x31,0xca,0xe5,0xdc,0xb3,0x53,0x70,0x04,0xb5,0xff,0x3e,0xa7,0xdc,0xe3,0x37,
+  0x6e,0x8e,0x1b,0xdd,0xbd,0x1c,0xa5,0x78,0x32,0x84,0xaf,0x05,0x3f,0xad,0x37,0x55,
+  0xd1,0x37,0x39,0x39,0x8a,0x47,0x8b,0x13,0x13,0x21,0x67,0xce,0x70,0x26,0x7c,0x2f,
+  0x9b,0xff,0xdb,0x39,0x16,0x2f,0xd1,0x51,0x1e,0xf1,0x15,0xcf,0x27,0xb4,0x49,0x6f,
+  0x3b,0xa8,0xff,0xef,0xb7,0x35,0xae,0xcd,0x9e,0x3b,0xab,0x78,0x37,0x84,0xae,0x02,
+  0x9b,0x83,0xfa,0x3d,0xda,0xd7,0x91,0xc8,0xbf,0x7c,0x3f,0xb2,0x2e,0xe2,0x80,0x1c,
+  0x7e,0x88,0x9c,0xd4,0x6a,0xbf,0xd1,0x58,0x29,0xfb,0x5f,0xea,0x39,0xbc,0x46,0x95,
+  0xcb,0x1b,0xea,0xd7,0xdd,0x8d,0x6e,0xb0,0x92,0x98,0x14,0x11,0xa9,0xfd,0xe7,0xe2,
+  0xff,0x3e,0xda,0xca,0x83,0x35,0x16,0x01,0xec,0x7f,0xc9,0xff,0xd0,0xd2,0x3d,0x7a,
+  0xf5,0x73,0x75,0xd2,0x48,0xbf,0x0e,0x70,0x4c,0x14,0x2d,0xdb,0xeb,0xda,0x31,0x2d,
+  0x0e,0xfe,0x8d,0x39,0x0a,0xd5,0x98,0x47,0xdb,0xff,0x1e,0x9b,0xe6,0xa6,0x27,0x0a,
+  0x22,0xff,0xbd,0x0e,0x94,0x9f,0xe6,0x6b,0xad,0xdf,0x4d,0x66,0x5c,0x1b,0x26,0x2f,
+  0xa1,0xd7,0x6e,0x82,0xcf,0x30,0x01,0x30,0x05,0x1e,0x71,0xa0,0xff,0xb5,0xa3,0x24,
+  0x2a,0xdd,0xea,0x71,0x07,0xf9,0xb1,0xfa,0xb8,0xd1,0xbc,0xc5,0x9b,0x4d,0x57,0x90,
+  0x83,0xf4,0x18,0x0c,0xe4,0xff,0x4b,0x6a,0x2b,0x0c,0xac,0x93,0x12,0xc4,0xfe,0xa7,
+  0x13,0xbe,0xc7,0x96,0xe7,0x9a,0x28,0x28,0xf8,0x42,0x19,0xe9,0x77,0x82,0xcc,0x2c,
+  0x89,0x46,0xaf,0xe1,0x42,0xd8,0xc0,0x62,0x5d,0x16,0xcf,0xb1,0x71,0x75,0x10,0xad,
+  0x24,0xaa,0x72,0xb3,0x8a,0xe1,0xe2,0xf2,0x01,0xea,0xff,0xa5,0x8a,0xff,0x79,0x09,
+  0x29,0x7b,0xbd,0xd5,0x9a,0xc2,0x27,0x06,0xd0,0xf6,0x7f,0xd2,0x3f,0x5f,0x55,0x3a,
+  0x42,0x0c,0xe0,0x03,0x33,0xc8,0xbf,0xcf,0xf0,0x7a,0x2c,0x94,0xfc,0x8f,0xad,0x0f,
+  0xf9,0xde,0xc1,0x6e,0x9b,0x5f,0xd1,0x98,0xeb,0xe9,0x30,0x33,0x39,0xfd,0x8d,0x7e,
+  0xce,0x82,0xe2,0x27,0xff,0x9c,0xfd,0x5f,0xf6,0x5f,0x9f,0xd0,0x62,0x9d,0x94,0x00,
+  0xf6,0x7f,0x2c,0xd2,0xf2,0x39,0xb8,0xa8,0x3e,0x55,0xf0,0x13,0x26,0x3e,0x2b,0xae,
+  0x9f,0x82,0x0b,0xb1,0x77,0x62,0x3d,0xea,0xbf,0x28,0xd7,0x68,0x5a,0x2e,0xfa,0x2e,
+  0xe9,0x7a,0x0a,0xcc,0xf8,0x1f,0x1d,0xbf,0x43,0xe1,0x33,0x88,0x02,0xd8,0xff,0x52,
+  0x3b,0xe6,0x7b,0xe7,0xc4,0x79,0x5f,0x9b,0x7e,0x57,0xd2,0xde,0x07,0x57,0x65,0xa2,
+  0xbc,0xcd,0x8e,0xe6,0xeb,0x7a,0x16,0xa1,0xf6,0x3f,0x00,0x4c,0x13,0x55,0xaf,0x94,
+  0x31,0x17,0xda,0xfe,0xeb,0x86,0x5f,0xf2,0x40,0x52,0x13,0xd7,0x34,0xf2,0xfe,0xb7,
+  0x3b,0xde,0x62,0x4a,0xc7,0x76,0x00,0xf9,0x57,0xdc,0xea,0x6c,0x0f,0xfb,0x3f,0xe4,
+  0xbb,0x36,0xa6,0xc4,0xa7,0x9e,0x05,0xb0,0xff,0x5d,0x9d,0x6e,0xb2,0xa4,0x48,0xaf,
+  0xa1,0x05,0x57,0xe5,0xe5,0x32,0xc7,0x17,0xca,0x3e,0x01,0x8e,0x14,0x9f,0xc1,0xda,
+  0x88,0xfa,0x2e,0xcb,0x77,0xe0,0xad,0xe7,0xfc,0x2e,0x9e,0x2b,0xb4,0xb4,0xfd,0xef,
+  0x34,0x47,0xe5,0xc7,0x2c,0x8c,0xb4,0x14,0x40,0xfe,0xe3,0x6d,0xd5,0xcf,0x3d,0x2a,
+  0x4a,0x6c,0x8b,0x5a,0xf3,0xaf,0x41,0x96,0xe6,0xb8,0x15,0x68,0xfb,0x3f,0x3a,0xb5,
+  0xea,0x53,0x81,0xfa,0x2c,0xe4,0xfe,0x0f,0x02,0x33,0xc9,0x5f,0xcf,0x3e,0x63,0x0e,
+  0x8c,0xfc,0x4f,0x19,0x72,0x87,0x2f,0x24,0xd5,0x24,0x6a,0xd6,0xcf,0x3c,0x26,0x3b,
+  0xac,0x1d,0x1e,0xcc,0xff,0x9f,0x3a,0x43,0x7d,0xcd,0xca,0x7f,0xb6,0x57,0x88,0x22,
+  0xdd,0xe2,0x4f,0x38,0x88,0xfd,0xd7,0xa7,0xd4,0x84,0x64,0xab,0xe9,0x55,0xb2,0xa4,
+  0xa4,0x41,0x10,0x95,0x7d,0xa1,0x5a,0x15,0x89,0xf6,0x3a,0xb3,0x09,0xb1,0x01,0xa6,
+  0xec,0x2b,0xd5,0x42,0xb6,0x9b,0xb1,0xe5,0x73,0x99,0xdd,0xa6,0x0e,0x2e,0xfd,0x41,
+  0x93,0x1d,0x4c,0x3a,0xc6,0xe7,0x7e,0x06,0xf1,0xff,0xdb,0x53,0xea,0xa2,0x74,0xef,
+  0x13,0xf2,0x9a,0xe5,0x9a,0x5f,0x8d,0x29,0xdd,0xda,0xe4,0x16,0xa5,0xe5,0xbf,0x83,
+  0xd6,0x94,0x1d,0xb4,0x12,0x0d,0x62,0xc2,0x00,0x17,0xc6,0x7e,0xf7,0xea,0x32,0xe2,
+  0x42,0xd5,0xa8,0x71,0x5f,0x9e,0x66,0x46,0xbc,0x0f,0x92,0x5e,0x03,0x36,0x91,0x39,
+  0x99,0x60,0xa7,0xab,0x7c,0x79,0x0f,0x12,0xff,0x0b,0x54,0xff,0x6f,0x36,0x96,0xf9,
+  0x66,0x49,0x77,0xfd,0xa2,0xd8,0x55,0xc0,0xd7,0xfe,0x53,0x39,0xca,0x75,0xb4,0xd5,
+  0xc2,0x19,0x7e,0xa3,0x29,0x67,0x63,0xe2,0x29,0x96,0xe6,0x24,0x65,0xbf,0x3e,0x7a,
+  0xc1,0x6f,0xdc,0x8f,0x68,0x4c,0xe6,0xc2,0x1a,0x8b,0x3e,0x27,0x22,0xc9,0x76,0x6f,
+  0x54,0xa5,0x6a,0xcf,0xd5,0x14,0xfc,0xfc,0xdf,0xe5,0xaa,0x70,0xbd,0x25,0xdd,0x0c,
+  0x03,0xb4,0xff,0x91,0x9c,0x8c,0x6d,0x71,0x64,0xb3,0xf8,0xa4,0x5f,0x89,0xa8,0x0f,
+  0x3d,0xc3,0x2f,0x8c,0x97,0xcf,0x89,0x72,0xcc,0xc9,0xff,0x94,0x2e,0x1e,0x74,0x29,
+  0x07,0x3d,0x7f,0x06,0x83,0xb1,0xff,0x81,0xe4,0xbf,0x93,0x76,0xb1,0x52,0xf9,0x75,
+  0x76,0xd8,0xa0,0x52,0x72,0xb2,0x21,0xf6,0x1a,0x70,0x50,0xb7,0xe9,0xb1,0x5d,0xc8,
+  0xad,0x8e,0x0e,0x89,0x2e,0xdb,0x7a,0x32,0xdd,0x17,0x2a,0xc2,0x30,0x41,0x7d,0x2b,
+  0x24,0x7f,0x18,0x4b,0xad,0x62,0x57,0x48,0x1e,0x48,0x9e,0xd3,0x24,0xde,0x8e,0x9f,
+  0xfd,0x6f,0x74,0xdd,0x1d,0xa4,0x48,0x36,0xe1,0x4e,0xed,0x29,0x7a,0x93,0x9f,0x6d,
+  0x79,0x03,0x17,0xa8,0x6b,0x4c,0x2b,0x7a,0x29,0xd4,0x91,0xbb,0x55,0x6a,0xa4,0x96,
+  0x8b,0x0a,0xba,0x22,0x1d,0xaa,0xf9,0x8c,0x81,0x30,0x65,0x2e,0x16,0xd3,0x42,0xaa,
+  0x4d,0xb7,0xd8,0x92,0x68,0x0b,0xb5,0x91,0xff,0xac,0x70,0xca,0xdd,0x39,0x67,0x49,
+  0x21,0xfd,0x51,0x6d,0xcf,0x31,0x1a,0x23,0xda,0x92,0x1c,0x44,0x86,0xba,0xf8,0x74,
+  0xd2,0x34,0x75,0x71,0xac,0x19,0x9a,0xd4,0x0c,0x3b,0x49,0x51,0x7a,0x62,0xd8,0xbf,
+  0x44,0x4c,0x45,0x5a,0xdc,0x55,0x28,0x25,0xab,0xb2,0xdc,0x68,0x33,0xea,0xed,0x9e,
+  0x24,0x8a,0xaa,0x4b,0x73,0x4c,0x25,0x20,0x1e,0xea,0xdb,0x78,0x05,0x70,0xf4,0x48,
+  0x51,0xf5,0xc1,0x28,0x47,0x30,0xf8,0x55,0xb7,0xef,0xaa,0xa9,0xe5,0x2f,0x25,0xc7,
+  0xe2,0xa5,0x74,0x3a,0x59,0xac,0x66,0xfa,0x35,0x21,0xd4,0xb5,0xa1,0x62,0xb4,0x9b,
+  0x8e,0x3f,0x8b,0x16,0x4f,0xcd,0x25,0xda,0xb2,0xc1,0x2c,0x54,0x6b,0x27,0xbd,0x28,
+  0x47,0xbc,0x9b,0xad,0x97,0xad,0x03,0xc2,0x7f,0xb2,0x92,0xa6,0xea,0x6b,0x89,0xea,
+  0x25,0xbc,0xd3,0x52,0x1c,0xef,0x35,0xd7,0xd2,0xe4,0x47,0xe9,0x67,0xff,0xa9,0xe3,
+  0x71,0x56,0x34,0xb4,0x7c,0xe8,0x7b,0xe9,0x78,0x1c,0x6d,0xae,0xca,0x0d,0xc5,0xd5,
+  0x6c,0x20,0xc9,0xee,0x92,0xdf,0x8a,0xf9,0x42,0x8f,0x78,0x54,0xd3,0x6c,0x2f,0xe6,
+  0x27,0x52,0xdd,0xb1,0x34,0x3e,0xae,0x6e,0xaa,0x98,0xef,0x34,0x7a,0x15,0x61,0x35,
+  0xb2,0x58,0x2d,0x26,0xf1,0x69,0xa0,0xa5,0xa3,0xa9,0xcb,0x95,0xd1,0xed,0xba,0xdf,
+  0xf2,0xe6,0xf0,0x0a,0xda,0x32,0x3a,0x08,0x7c,0xc6,0xd1,0xd0,0x5c,0x42,0xf3,0x16,
+  0x95,0x8c,0xff,0xdf,0x8c,0x74,0xce,0xa5,0x92,0xf8,0x98,0xbb,0x21,0xfe,0x7c,0x9c,
+  0x33,0x2e,0x3b,0x37,0x3e,0x52,0xa6,0x17,0x50,0xa9,0x12,0x61,0xef,0x42,0x6d,0xd4,
+  0xe6,0xc8,0xd6,0xe2,0xdd,0xe8,0xc4,0x56,0xcf,0x73,0x42,0xec,0xe0,0x43,0x4d,0x92,
+  0xb3,0xfa,0x5e,0x6a,0xa2,0xa5,0xf9,0xf8,0x0a,0xde,0x3d,0x28,0xdb,0xd7,0xb4,0xa9,
+  0x77,0xaa,0x67,0xc8,0x6e,0xc6,0x92,0xc5,0xa1,0x25,0x88,0xfc,0x0d,0x0c,0x13,0xff,
+  0xdf,0x43,0xe2,0x94,0x6a,0x96,0x23,0x8d,0x75,0xdd,0xd8,0x0c,0xb4,0x74,0xd3,0xd0,
+  0x23,0x8d,0x06,0x2a,0x45,0xea,0x35,0x54,0xd8,0x2a,0xda,0xe9,0x7a,0x03,0x95,0x51,
+  0xd3,0x7f,0xa7,0x7e,0xf6,0xdf,0x67,0x8b,0x26,0x3a,0xe7,0x88,0x7c,0x73,0x46,0x3d,
+  0x42,0x4e,0xb0,0xff,0x71,0x35,0xc9,0xb5,0xc3,0x0b,0x1b,0x41,0xae,0x86,0xba,0x43,
+  0xae,0x5d,0xa4,0x1e,0x60,0xdb,0xe8,0x20,0xf0,0xb2,0x7a,0x9d,0xdb,0x32,0x6d,0xff,
+  0xa9,0xfe,0x5b,0x9b,0x78,0xcb,0xbd,0x2e,0xcf,0x20,0x34,0x0d,0xb3,0x8c,0xf7,0x1d,
+  0xe8,0xa4,0x48,0x89,0xc0,0x37,0xc7,0x54,0x7b,0x78,0x0a,0x52,0xec,0x92,0x27,0x19,
+  0x0f,0x0d,0xe8,0x0f,0x6d,0xf0,0xd8,0x9c,0x93,0x9b,0x12,0x3f,0xfb,0xff,0x26,0xa3,
+  0xf7,0xfc,0x3f,0xc0,0xcd,0x03,0x3b,0x11,0x5b,0xaf,0xce,0xa5,0x37,0x05,0x83,0xd9,
+  0xff,0x37,0x2c,0x39,0x90,0x7f,0x80,0xc0,0x4c,0x1a,0xcb,0x75,0xcd,0xb5,0x97,0xb8,
+  0x99,0x6a,0x55,0x37,0x89,0xfd,0xf7,0xeb,0xfe,0x0c,0xdc,0x74,0xb0,0x1d,0x46,0xe2,
+  0x7c,0x30,0x79,0x44,0xab,0x8a,0x8d,0xd7,0x6f,0x5e,0x6e,0x12,0xfb,0x4f,0xb7,0xff,
+  0x81,0xfd,0xbf,0xa9,0x59,0xe7,0xf2,0xa8,0x42,0xa3,0x6e,0x0c,0xb7,0xde,0xc8,0x56,
+  0xa3,0xa5,0x9b,0x6a,0x34,0xd5,0x9b,0xd0,0xfe,0x83,0xfc,0xdf,0xdc,0x08,0x73,0x4b,
+  0x8d,0x15,0xab,0x43,0xad,0xa1,0xc9,0x5c,0xc8,0xee,0x91,0x1a,0x70,0x44,0xed,0xeb,
+  0x8a,0x3a,0xa5,0x5a,0x4c,0xed,0x4d,0x68,0x6f,0x12,0xfb,0x4f,0xc7,0xff,0x06,0xf1,
+  0xff,0xc9,0x05,0xc6,0xd7,0xf8,0xcd,0x7b,0x69,0x6e,0x3a,0xd6,0xfd,0xfb,0x7f,0xbd,
+  0x51,0x2c,0x44,0xb3,0x95,0xf3,0xd8,0x53,0x06,0x18,0xd8,0xff,0x1e,0xb4,0x9d,0x4b,
+  0x3c,0x91,0xcb,0x09,0xa3,0x38,0x03,0x6f,0x54,0xfc,0x7b,0x6c,0xd9,0xdc,0xf0,0xc3,
+  0xa9,0xed,0x62,0xfc,0x7f,0x1f,0x6e,0x42,0xfb,0x1f,0x5c,0xfe,0x17,0xa9,0xb5,0x7a,
+  0x8e,0xd4,0x0a,0xbc,0x91,0x50,0xab,0x7d,0xe4,0xbf,0xd7,0x90,0xd3,0x37,0x06,0x54,
+  0x27,0x92,0xbd,0xd5,0x56,0xc0,0xfe,0xf7,0xc0,0x2f,0xff,0x1f,0x78,0x63,0x63,0xf6,
+  0x1a,0x33,0x46,0x91,0x4e,0xd9,0x75,0x63,0x01,0xf6,0x7f,0x40,0x76,0x57,0xff,0xf7,
+  0xeb,0xff,0x07,0xbc,0xc1,0xd9,0x11,0x7b,0x52,0xd1,0x88,0x33,0x44,0xdf,0x60,0xec,
+  0x62,0xfe,0x1f,0x1f,0xc0,0xfe,0xf7,0x00,0xec,0xff,0x9b,0x15,0xb5,0xd6,0x2b,0x08,
+  0x98,0xbc,0xe1,0x33,0x80,0xc0,0xfe,0x0f,0xc6,0xde,0xed,0x3f,0xc8,0xff,0x9b,0x8b,
+  0x75,0x79,0x8f,0x71,0xc2,0x0d,0x3f,0xa0,0xe2,0xfe,0xf9,0xff,0x60,0xff,0x7b,0x00,
+  0xf2,0xff,0x26,0xa6,0xd9,0xc8,0x47,0x65,0x0d,0x01,0xa5,0x6e,0x6e,0xf4,0x46,0x17,
+  0x04,0x66,0xfc,0x3f,0x6d,0x2f,0x5b,0xba,0x49,0xec,0xff,0xee,0xf2,0x7f,0xa1,0xfe,
+  0xff,0xe6,0xc6,0x5c,0xab,0x14,0x93,0xce,0xa0,0x34,0xa5,0x52,0x29,0x9d,0x3c,0x33,
+  0x17,0x2b,0xec,0x53,0x77,0xd0,0xab,0x0a,0xd8,0xff,0xc1,0xd8,0x5d,0xfe,0x2f,0xd8,
+  0xff,0x37,0x3d,0x4d,0xb3,0x51,0x58,0xad,0x25,0x12,0xb1,0x6c,0x47,0x6b,0xfb,0xf4,
+  0x6c,0xbf,0xf1,0xe8,0x31,0xfe,0xef,0x80,0xd0,0xf2,0xcf,0x0f,0x57,0xff,0xe6,0xa1,
+  0x09,0xfe,0x3f,0xf0,0x26,0x62,0xff,0xea,0xff,0xed,0x9b,0xc3,0xfe,0x83,0xff,0x0f,
+  0xbc,0x89,0x68,0x56,0xa3,0x2e,0xa9,0xed,0xbd,0x6c,0x89,0xae,0xff,0xdf,0xf0,0xcd,
+  0x9e,0xbb,0x67,0x77,0xf6,0x5f,0xf3,0xae,0x72,0x74,0xa8,0xff,0xe2,0x00,0x70,0x8d,
+  0x50,0x37,0x55,0x43,0xdd,0x34,0x54,0xfc,0xd8,0xd3,0x86,0xda,0xc9,0x6e,0x3a,0x3d,
+  0x86,0x9f,0x63,0xe9,0x40,0xa3,0xa1,0xbf,0x31,0x99,0x4f,0x8f,0x3d,0x83,0x4f,0x33,
+  0xdd,0x4d,0x77,0x7b,0xcf,0xb9,0xce,0x60,0xe0,0xeb,0x4c,0x2e,0xf3,0xe6,0x9b,0xf7,
+  0xda,0x00,0x37,0x31,0x4d,0x3d,0xa2,0xeb,0x65,0xfc,0x2c,0x97,0x03,0xcc,0x85,0xf4,
+  0x46,0x65,0xc7,0x3e,0x4d,0xfc,0x02,0x92,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x4d,
+  0x85,0xaa,0x1a,0x23,0x91,0x76,0x41,0xc3,0x14,0xe0,0x79,0xd3,0x5f,0x87,0x5d,0x9c,
+  0xbf,0xfd,0x1f,0xb1,0xd4,0xbe,0xd8,0xbe,0x48,0xb0,0xff,0x79,0xfc,0x95,0xe4,0x9d,
+  0x0f,0x7d,0x17,0xb8,0x86,0xac,0xbf,0xe7,0x71,0xa3,0xd9,0x6c,0x5e,0x6f,0x29,0xdd,
+  0x77,0x88,0xd4,0x6b,0xd9,0x44,0x35,0x17,0x8a,0x76,0xd3,0x25,0x00,0xd8,0x3b,0xf1,
+  0x67,0x9f,0x7e,0xe5,0x13,0xef,0xba,0xed,0xde,0x93,0x27,0x4f,0x1e,0x27,0x0f,0xeb,
+  0xc5,0x1f,0xb2,0x04,0xf5,0x9f,0xfd,0xc9,0xfe,0x9a,0xfe,0x51,0xfa,0xd1,0x5d,0x9e,
+  0xdd,0xce,0xf1,0x93,0xec,0x92,0xf4,0xcf,0xb2,0xbd,0x49,0xd6,0x42,0x6f,0x7f,0xee,
+  0xcf,0x9e,0xfb,0xd4,0x6f,0xde,0xf3,0xde,0x77,0x14,0x4e,0xbf,0xc7,0xdc,0x7c,0x93,
+  0xcc,0x80,0x6e,0x14,0x86,0x90,0xd4,0xc7,0x4b,0x0a,0x00,0x5c,0x05,0x9e,0xbd,0xe3,
+  0xf7,0x3e,0x71,0xdb,0xd7,0xcf,0x9f,0x47,0xcf,0xdb,0xd0,0x83,0xbc,0x7c,0x1d,0x3d,
+  0xbf,0x8e,0x9e,0xe8,0x05,0xbd,0xb3,0xdf,0x5b,0x9f,0xbd,0xff,0xf7,0x9e,0x77,0xff,
+  0x39,0xdf,0x93,0xb7,0xee,0xc2,0xee,0x4a,0x5f,0xc7,0xdb,0xb0,0x36,0x69,0x3d,0x98,
+  0xed,0xd8,0xdf,0xdf,0x4b,0x76,0x46,0x7d,0x6f,0xaf,0xe7,0x7c,0xbe,0xd7,0x5a,0x84,
+  0xfa,0xfd,0xfc,0xbd,0xe8,0x89,0xbf,0xb0,0x0e,0xfc,0xeb,0xd6,0x4e,0xf0,0x89,0x60,
+  0x4d,0xf0,0xaf,0x7e,0xff,0x1f,0x2e,0x1a,0x6f,0x74,0x5f,0x40,0xcf,0x54,0xa3,0x20,
+  0xf9,0xc0,0x55,0xe6,0xc1,0x3b,0x5e,0xb9,0x0d,0xc9,0xce,0xf9,0x93,0x44,0xe4,0x4e,
+  0x7e,0x9d,0xbc,0xb1,0x44,0xe9,0xde,0xf3,0x44,0x35,0xa0,0xef,0x2c,0x9c,0xff,0xec,
+  0x5b,0x11,0xe6,0xc7,0x7b,0xed,0xbf,0xf3,0xde,0xff,0x7b,0xe9,0xe5,0xa8,0xdf,0xee,
+  0x3d,0xcf,0xc2,0xef,0x44,0xd8,0xa9,0xb5,0x0e,0xd6,0x43,0xf6,0xb1,0x92,0xc3,0xc6,
+  0x8a,0xe1,0xfc,0xf1,0x0f,0x7d,0xfa,0x27,0xcc,0x37,0xac,0x0a,0x30,0x22,0xd9,0x5c,
+  0xf7,0x7a,0x97,0x0c,0xe0,0x66,0xe1,0x41,0xe2,0x05,0x60,0x41,0xc7,0x56,0xf5,0xfc,
+  0x49,0xf4,0xc0,0x4f,0xcc,0x49,0x4f,0xda,0x4e,0x52,0xff,0x99,0x5f,0xa9,0x65,0x24,
+  0x1f,0x99,0xf5,0x7a,0x2d,0xe7,0xb7,0xbc,0xdf,0x7f,0xe7,0x93,0xf3,0xf9,0xde,0xf3,
+  0xb6,0x06,0x23,0x9e,0xc2,0xbd,0xe7,0x4f,0xbe,0xf5,0x37,0xef,0x7b,0xcf,0x1b,0xb0,
+  0x26,0x60,0xb4,0x13,0xa1,0xf4,0xf5,0x2e,0x12,0xc0,0xcd,0xc5,0x1d,0x9f,0xb8,0xed,
+  0xa4,0x25,0x4c,0xae,0xf4,0x9f,0xdc,0x8f,0x87,0xbd,0xb5,0x93,0xf4,0x16,0xed,0xaf,
+  0xa9,0x5f,0xa9,0xa5,0x82,0x3f,0x5c,0x2d,0x45,0x7f,0xa4,0x74,0x17,0x76,0x09,0x7e,
+  0xee,0xc7,0xdf,0xfb,0x57,0x6f,0x2c,0x15,0x10,0xc9,0xa7,0xc0,0xeb,0x07,0xae,0x3d,
+  0x0f,0xbe,0x72,0x9b,0x17,0x4e,0x3b,0x7f,0xb0,0x57,0x38,0x70,0x60,0xce,0xe3,0x17,
+  0x9f,0x4d,0x1e,0x64,0xfe,0x0d,0xc0,0xc1,0xf3,0xf8,0x79,0xd2,0xd2,0x25,0xee,0x9e,
+  0x78,0xe5,0x70,0xfe,0xe7,0x9e,0xbb,0xa7,0x7c,0xbd,0x85,0x3a,0x30,0x7a,0x65,0xec,
+  0x7a,0x97,0x03,0xe0,0x66,0xa5,0x74,0xc7,0x6d,0xbe,0xc2,0xb6,0x07,0x0e,0xee,0x46,
+  0xb8,0x07,0xdd,0xbe,0xf5,0xa0,0xf6,0x84,0x9d,0x0a,0xa7,0xb2,0xf0,0xd6,0x7b,0xea,
+  0xd7,0x5b,0xb0,0x03,0x31,0x92,0x48,0x5e,0xef,0x32,0x00,0xdc,0xd4,0x20,0x0d,0x70,
+  0x10,0xcb,0xd3,0x71,0x22,0x4d,0x07,0x8f,0x1f,0x1f,0xfc,0x69,0x3f,0xac,0x95,0xf1,
+  0x2b,0x81,0xbc,0xb1,0x17,0x39,0x69,0xff,0x80,0x97,0x71,0x9f,0xcc,0x12,0x81,0x9e,
+  0x94,0xd4,0xf3,0xfa,0xc0,0x53,0x02,0xb6,0x23,0xf0,0xaf,0xfe,0xc1,0xbc,0xde,0xc2,
+  0xdd,0x17,0xa3,0x16,0xbd,0xde,0xb7,0x1f,0xb8,0xe9,0x79,0xe5,0xeb,0x58,0x03,0x1c,
+  0x44,0x12,0x7c,0x4d,0x78,0x69,0x9f,0xb7,0x67,0xe9,0x05,0x41,0x09,0x9c,0x3f,0xff,
+  0xdc,0xe2,0xce,0xf5,0x16,0xf0,0x9e,0x18,0xa3,0x50,0xef,0x07,0x6e,0x00,0x4a,0xbf,
+  0x77,0x12,0x4b,0xe5,0x4b,0x7b,0x15,0xcd,0x97,0xdc,0x57,0xbf,0x3f,0xd9,0x37,0x83,
+  0xf0,0xa4,0xbb,0x15,0xf6,0x3f,0x86,0x71,0x0d,0xac,0x98,0xc0,0x73,0xef,0xb8,0x71,
+  0x73,0x02,0x8c,0x4c,0x11,0xa4,0x1f,0xb8,0x31,0x28,0xdd,0x76,0xf0,0xc4,0x91,0x97,
+  0x9e,0x7c,0xe9,0xa5,0x27,0x91,0x88,0x3d,0xf9,0xd2,0xc1,0x27,0x07,0x7c,0xbc,0x84,
+  0x56,0x21,0x7f,0xfd,0x56,0x7e,0xc9,0xfe,0xdb,0xdd,0xe3,0xa5,0x83,0x47,0x5e,0xb2,
+  0x0e,0xf0,0x04,0x3a,0x52,0xfc,0x87,0x3e,0x1d,0xc1,0x7b,0xb7,0xf5,0xc0,0x71,0xc7,
+  0x15,0x20,0x79,0x82,0xe7,0xcf,0x1f,0xff,0xd4,0x37,0x36,0x6f,0x48,0x0d,0xa0,0x16,
+  0x26,0xe2,0xd7,0xfb,0xa6,0x03,0x80,0xcb,0x1d,0x27,0x9f,0x3c,0xb1,0x4f,0x3c,0x49,
+  0xbf,0xdd,0xb7,0xad,0xb2,0x1b,0x7f,0xd2,0x7d,0x12,0xb0,0x0a,0x78,0xe9,0xa5,0x97,
+  0x5e,0x72,0x1c,0x01,0xaf,0x16,0x70,0xfc,0x7d,0x17,0x6f,0x40,0x05,0x60,0x4c,0x82,
+  0xf4,0x03,0x37,0x14,0xa5,0xdb,0x90,0x34,0x1d,0x46,0xcf,0xc3,0xe8,0xf5,0xf0,0x80,
+  0xcf,0x5b,0xf0,0x8b,0xf5,0x06,0xbd,0x92,0x2d,0x58,0x8f,0xc3,0xe4,0xfb,0x13,0xee,
+  0x57,0xc2,0xef,0x03,0xef,0x87,0x3c,0xbc,0xa7,0x07,0xf6,0x06,0x90,0x0b,0x63,0x57,
+  0x06,0x9c,0xba,0xc0,0xf9,0xf3,0x2f,0x3d,0xfa,0x81,0xeb,0x2d,0xee,0x3c,0x91,0xe2,
+  0xf5,0xbe,0xdb,0x00,0xc0,0xf3,0xca,0x4b,0xb7,0xdc,0x72,0xe5,0x96,0xdd,0xb3,0x97,
+  0x75,0x07,0xe6,0xb0,0xf5,0x77,0x18,0x3d,0x4e,0x58,0x2a,0x01,0x7b,0x05,0x4f,0x3a,
+  0x6e,0xc0,0x4b,0x07,0x8f,0x7b,0x11,0xc1,0x4f,0x7d,0xdf,0xf5,0x16,0x78,0x96,0x42,
+  0x54,0x81,0xaa,0x3f,0x70,0xc3,0xf1,0xec,0xf1,0x2b,0xb7,0x5c,0xb9,0xff,0xca,0xd5,
+  0xe0,0x96,0xab,0xb2,0xd5,0x2b,0x57,0xee,0xbf,0x05,0x6f,0xdb,0x52,0x08,0x27,0xb0,
+  0x77,0x81,0x95,0xc0,0xc1,0x83,0x47,0x6c,0x27,0x00,0xab,0x80,0xf3,0xe7,0x4f,0xfe,
+  0xd9,0x4f,0x5c,0x6f,0x91,0xa7,0x50,0x6b,0xe9,0x92,0x52,0x02,0x0d,0x00,0xdc,0x78,
+  0xdc,0x7b,0xe5,0x91,0x27,0xd0,0xe3,0x11,0xf2,0x3a,0xe8,0x03,0xad,0xe5,0xac,0x4c,
+  0xfe,0x59,0xff,0x9d,0xdf,0x9c,0x4f,0xde,0xc7,0xdd,0x3d,0xbc,0xcd,0x5a,0x5c,0x79,
+  0xc2,0xd5,0x31,0x96,0x12,0xb0,0x55,0x80,0xd5,0x34,0x60,0xab,0x80,0xbf,0x7d,0xef,
+  0x0d,0x93,0x12,0xbc,0x53,0x89,0x83,0xec,0x03,0x37,0x28,0x9f,0xb8,0x72,0x14,0x0b,
+  0xe7,0x23,0xb7,0xef,0xe2,0x71,0xf4,0x91,0xa3,0xce,0x1b,0xf7,0xcb,0xa3,0xd2,0x05,
+  0x77,0xb3,0x75,0x6f,0x2f,0x64,0x4f,0x8f,0xb8,0x58,0x8a,0xe7,0x09,0xe2,0xb8,0xdc,
+  0x8f,0x75,0xc0,0x61,0x5b,0x05,0x3c,0x49,0x69,0x80,0x83,0x9f,0xbe,0x41,0x5a,0x02,
+  0xcb,0xb9,0x12,0x48,0x3f,0x70,0xc3,0xf2,0xca,0x2d,0x2f,0xbf,0x7c,0xfb,0xd5,0x67,
+  0xbf,0xf6,0xf1,0x08,0xfe,0x3b,0x7a,0xd4,0xf1,0x27,0x1c,0x37,0x80,0x68,0x80,0x23,
+  0x76,0x8a,0x81,0xd5,0x16,0xf0,0xfb,0xe5,0xa9,0x1b,0x40,0x03,0x0c,0x87,0x4a,0x25,
+  0xf0,0xfe,0x81,0x1b,0x97,0x3b,0x4e,0x1c,0x3b,0xf6,0x30,0x92,0xcf,0x97,0x6f,0x3f,
+  0x86,0x5e,0x5e,0x26,0x6f,0x6e,0x47,0xcf,0x63,0xf8,0x3f,0xfe,0xa3,0xde,0xba,0xff,
+  0xf0,0xc2,0xf6,0x0a,0xb7,0x93,0x17,0xfc,0x03,0xfe,0x85,0xbc,0x7f,0xf9,0x65,0x67,
+  0x1b,0xe4,0xf1,0xb2,0x25,0xfd,0xc7,0x6e,0xf7,0xb6,0x60,0xbd,0xbe,0xcc,0x6c,0x93,
+  0x7a,0x58,0xdf,0x91,0x05,0xad,0xed,0x59,0x4f,0xeb,0x4b,0x57,0x15,0x20,0x2d,0x70,
+  0x14,0x79,0x02,0xf7,0x13,0x15,0x40,0x62,0x01,0x4e,0x6b,0x00,0x51,0x01,0x1f,0xba,
+  0x78,0xbd,0x85,0x7f,0x4a,0xcd,0x74,0x2d,0xf1,0x47,0x80,0x06,0x00,0x6e,0x48,0xee,
+  0x38,0x7c,0xec,0x61,0x82,0xfd,0x2f,0x08,0xc7,0x84,0x37,0xb2,0x1f,0xf7,0x8f,0x63,
+  0xce,0x66,0x8f,0xe1,0xe7,0xcb,0x0f,0x5b,0xfa,0x06,0xe9,0x00,0xe2,0x08,0x5c,0x79,
+  0x02,0x57,0x04,0x0e,0x5b,0xf9,0x07,0x24,0x16,0x78,0xf2,0xf8,0xc9,0x83,0xe7,0xff,
+  0xf6,0xbe,0xeb,0x1c,0x04,0x50,0x13,0xe9,0x38,0x19,0x8d,0xed,0x7a,0xdf,0x62,0x00,
+  0xf0,0xe7,0xc1,0x5b,0xee,0x7e,0xf8,0x6e,0x24,0x5b,0xb7,0x92,0x57,0xcc,0xdd,0xbe,
+  0x82,0x78,0x9d,0xb8,0x55,0xfc,0x0a,0xa9,0x01,0xcb,0xb1,0x78,0xe4,0x76,0x12,0x0e,
+  0xc0,0x5e,0xc0,0x61,0xab,0x49,0xd0,0x49,0x08,0x38,0xfe,0xb6,0xeb,0x9a,0x09,0xa0,
+  0xe6,0xe3,0x96,0xf8,0x63,0xf9,0x07,0x1d,0x00,0xdc,0xa8,0x3c,0x7b,0xcb,0xad,0x98,
+  0x87,0xd1,0xdf,0xdd,0xe4,0xdd,0xdd,0xe4,0xef,0x6e,0xf7,0x9d,0xfd,0xf5,0xad,0xd4,
+  0x1b,0xea,0x1d,0xff,0xc1,0xfd,0x78,0xb7,0xf8,0x8b,0xfb,0xeb,0xdd,0xec,0x62,0xe2,
+  0xd2,0x77,0xf3,0x6b,0x90,0xff,0x0f,0xdf,0x7a,0x37,0xad,0x9c,0x48,0xad,0xe0,0xf6,
+  0xdb,0x8f,0x12,0x2f,0xc0,0xd6,0x00,0x27,0x9e,0xb4,0xf2,0x02,0x71,0x1d,0xe0,0x51,
+  0xe3,0xfa,0x89,0x7f,0x33,0x86,0xc4,0x3f,0x6e,0x89,0x3f,0x48,0x3f,0x70,0x03,0xf3,
+  0xec,0xfd,0xb7,0xde,0x7a,0xea,0xd6,0x87,0x44,0x51,0xc5,0x9c,0x72,0x5f,0x7a,0xd0,
+  0xef,0x77,0xd9,0x0a,0x3d,0xd6,0x39,0xc5,0x2e,0x46,0x9e,0xec,0xe2,0xae,0x1a,0x38,
+  0x66,0x85,0x04,0xb0,0x0a,0x78,0x02,0x6b,0x00,0x92,0x1a,0x78,0xf0,0x84,0xed,0x03,
+  0xdc,0x73,0xfd,0xaa,0x00,0x99,0x6e,0xdc,0xb6,0xff,0x0a,0x38,0x00,0xc0,0x0d,0xcd,
+  0x1d,0x8f,0x9c,0x7a,0x08,0xc9,0xff,0x43,0x84,0x5b,0xed,0x3f,0xfa,0xed,0xad,0xce,
+  0x53,0xf6,0xce,0x7a,0x9e,0x22,0x4f,0xe6,0x37,0xd9,0x62,0x92,0xaf,0xa4,0x4b,0x3b,
+  0x1f,0xc9,0x66,0xc9,0x57,0xf8,0x41,0xb4,0xd4,0x29,0x5e,0x09,0x10,0x27,0x00,0xc7,
+  0x02,0xae,0xd8,0x1a,0xc0,0x8e,0x02,0x1c,0x3c,0xf9,0xd2,0xaf,0x5f,0x2f,0x05,0xd0,
+  0x8e,0xc6,0xe3,0xae,0x03,0x00,0xc2,0x0f,0xdc,0xd0,0xbc,0xf2,0xf2,0xab,0xaf,0x3e,
+  0xf4,0xd0,0xab,0xf8,0x85,0xf0,0x2a,0x79,0x50,0xbc,0x4a,0x7e,0xf4,0x9e,0xd6,0xe3,
+  0xd5,0x57,0xb9,0x05,0x5f,0x75,0xb7,0x41,0x7e,0xb1,0x9e,0xec,0x9a,0xaf,0xca,0xb7,
+  0xe9,0xec,0xd2,0xde,0x1c,0xb3,0x2c,0x77,0x2c,0x96,0x2e,0x70,0x74,0x80,0xe5,0x05,
+  0xe0,0x36,0x07,0x1c,0x0c,0x74,0x35,0x00,0xc9,0x07,0x3a,0x79,0xf2,0xad,0xd7,0x29,
+  0x15,0x50,0x0f,0xa5,0xe3,0x4f,0x5b,0x0a,0x00,0xa4,0x1f,0xb8,0xe1,0x79,0xff,0xc3,
+  0xaf,0x86,0x5f,0x25,0xd8,0xff,0xdc,0xf7,0x61,0xf6,0x2b,0x29,0x61,0x67,0x49,0x6a,
+  0xbd,0x9e,0x8b,0xf7,0x5e,0x24,0x2c,0x7d,0xeb,0x62,0xeb,0x85,0x53,0x8e,0x1f,0x40,
+  0x69,0x80,0xdb,0x71,0x1c,0x00,0x87,0x01,0x9e,0x7c,0xf2,0x88,0xa5,0x00,0x3e,0xf4,
+  0x57,0xd7,0x43,0xfc,0xcd,0x1c,0x92,0xfd,0xb4,0xe3,0x00,0x80,0x06,0x00,0x6e,0x74,
+  0xee,0x3d,0xf5,0xea,0xab,0x87,0x0e,0xd9,0xa2,0x19,0x76,0xc5,0xde,0x53,0x0a,0xec,
+  0x93,0xfb,0x82,0xd1,0x15,0xee,0xbb,0xb0,0xb8,0x20,0xb5,0x59,0xf9,0x06,0xc9,0xbb,
+  0x43,0xaf,0x7a,0xfb,0xa6,0x37,0xc8,0x68,0x01,0xdb,0x13,0x38,0xe5,0x38,0x01,0x2f,
+  0x63,0x0d,0x80,0xe3,0x00,0x57,0x48,0x62,0x30,0x19,0x37,0xe0,0xe0,0xf1,0x83,0xcf,
+  0x5d,0x87,0x91,0x01,0x8d,0x4a,0x1a,0x61,0x39,0x00,0x90,0x00,0x04,0xbc,0x11,0x38,
+  0x78,0x28,0x1c,0x46,0x1a,0x20,0xfc,0x2a,0xf5,0xb0,0x3e,0xa1,0x7f,0xec,0xd7,0xec,
+  0x83,0x2c,0x77,0x88,0xff,0x6a,0xf0,0x07,0xbd,0xde,0x21,0x67,0xa7,0xce,0x57,0xf6,
+  0x5e,0x0e,0x61,0xe5,0x10,0x66,0x74,0x00,0x12,0xff,0x87,0x6c,0x27,0xc0,0x6e,0x0c,
+  0x78,0xe2,0x91,0xfb,0x89,0x06,0xb0,0x9a,0x01,0x0e,0xbe,0xef,0x9a,0x0f,0x0b,0xa6,
+  0x6e,0x75,0x9f,0x7e,0x3a,0x9d,0x7e,0x3a,0x1d,0xb7,0x14,0xc0,0xf5,0xbe,0xb5,0x00,
+  0xd0,0x9f,0xfb,0x91,0xd0,0x85,0x2d,0xb9,0xbb,0x31,0x71,0x8e,0xeb,0x55,0x5b,0xd9,
+  0xb8,0x4a,0xc0,0x8e,0x06,0x60,0x15,0x70,0xbb,0x13,0x06,0xb0,0x9a,0x02,0x0f,0x3e,
+  0x89,0x3c,0x80,0x4f,0x6f,0x5e,0x63,0xf9,0x5f,0x4d,0x62,0xf3,0xff,0x34,0xf1,0x00,
+  0x4a,0xa0,0x00,0x80,0x37,0x04,0x77,0x3c,0x7c,0x5d,0xa5,0x7b,0x30,0x88,0x77,0xe0,
+  0x78,0x02,0x96,0x17,0x60,0x35,0x07,0x1c,0x23,0x95,0x00,0xa2,0x00,0x0e,0xe3,0x96,
+  0x40,0x5c,0x07,0x78,0xef,0xb5,0xed,0x09,0xd0,0x4e,0xa5,0x9f,0x49,0x77,0x49,0x0d,
+  0xc0,0xab,0x00,0xdc,0xe0,0xc4,0xd3,0xd1,0xe2,0x5c,0xa5,0xb5,0xb2,0x95,0x68,0xe5,
+  0xe7,0x8a,0x4f,0x8d,0xc1,0x78,0x45,0x37,0x1f,0x9f,0x78,0x28,0x3c,0x8d,0x44,0x0b,
+  0xff,0xa1,0x17,0xf2,0xcf,0x7e,0xb5,0xbf,0x98,0x66,0x7f,0x9f,0xf6,0x16,0x98,0x76,
+  0x57,0xa1,0xbf,0x76,0x5e,0xa6,0xc3,0xee,0x8a,0xce,0xa7,0x69,0xe6,0x17,0x77,0x77,
+  0xde,0x1e,0xb9,0xcf,0xee,0x47,0x4e,0x0b,0xbc,0x7a,0xc8,0xd5,0x00,0x0f,0xe1,0x14,
+  0x26,0xa2,0x01,0x6e,0x77,0x34,0x00,0xf6,0x00,0x90,0x02,0x38,0xb2,0x70,0x2d,0xc5,
+  0x5f,0xbf,0x14,0x1f,0x1b,0x1b,0xeb,0x76,0xbf,0x6a,0xd7,0x00,0x6c,0xf9,0xbf,0x71,
+  0x55,0x40,0xa9,0x7b,0x39,0xb1,0xa4,0x1b,0xaa,0xa3,0x25,0x9b,0xaa,0xa1,0x2f,0xc5,
+  0x2e,0x77,0x6f,0xdc,0x23,0x06,0xae,0x0a,0x47,0xb0,0xa0,0x4d,0x53,0xd2,0xc8,0x0b,
+  0xa5,0x27,0xea,0xf2,0xef,0x99,0xf5,0x28,0xe9,0x17,0xde,0x49,0x56,0x65,0x75,0xca,
+  0x34,0xa5,0x71,0xa6,0x25,0xd2,0x3f,0xed,0x28,0x80,0x43,0x76,0x4d,0xc0,0xd6,0x00,
+  0x77,0xdb,0x61,0x00,0x4f,0x01,0xe0,0x28,0xc0,0x5b,0xff,0xed,0xb5,0x13,0x7f,0xb5,
+  0x8a,0x44,0xbf,0xfb,0xd5,0xb1,0xee,0x58,0x37,0xed,0xb4,0x00,0x58,0x97,0xf7,0xc6,
+  0x94,0xa7,0xe4,0x5c,0x47,0x17,0x92,0x24,0x90,0x2a,0x50,0xeb,0x99,0x2a,0x4c,0x56,
+  0x72,0x53,0xf1,0xe0,0xcb,0x8e,0x59,0x9e,0xa5,0xe4,0x6c,0x9a,0x12,0xce,0x69,0x1f,
+  0x59,0x95,0x6a,0x00,0x66,0x61,0x46,0xe2,0xa7,0xd9,0x6d,0xb0,0x4a,0x85,0x11,0xf6,
+  0x69,0xc9,0xc2,0x9c,0x76,0x42,0x3a,0xc0,0x89,0x03,0x38,0x6d,0x01,0x24,0x1f,0x88,
+  0xe4,0x02,0xd8,0x1e,0xc0,0xff,0xf1,0xf8,0x35,0x93,0xff,0x42,0x12,0xd9,0xfe,0x6e,
+  0x37,0x89,0x55,0x40,0x3a,0xcd,0xe4,0x00,0x06,0xa0,0x74,0x20,0x91,0x68,0xa1,0xc7,
+  0xca,0x4a,0xc2,0x7a,0x38,0x9c,0xf3,0x59,0x21,0xd9,0x22,0x3f,0xaf,0xe0,0x55,0xdc,
+  0xe5,0xd1,0xbf,0x95,0x54,0x90,0xdd,0xc5,0x43,0x59,0xdd,0xbf,0x72,0xd4,0x34,0x3b,
+  0x17,0xfa,0x57,0x04,0x8a,0x78,0x8f,0x2d,0xee,0x70,0xe9,0xb7,0x3c,0x15,0x67,0xee,
+  0xd3,0x68,0xc2,0x5a,0xa7,0xb5,0xe2,0xad,0xc1,0xaf,0xb7,0xc2,0x7d,0xf0,0xce,0x30,
+  0x91,0x1f,0xb8,0x92,0x12,0x6d,0xe1,0x35,0xf1,0x15,0x5b,0x61,0xb6,0xdb,0x8a,0xfa,
+  0xac,0x90,0x23,0x37,0x43,0x64,0x4e,0xbc,0x9d,0xe9,0x8a,0xb5,0xa9,0x44,0x62,0x65,
+  0x45,0x7a,0xf6,0x2b,0xd4,0x3b,0xea,0x7d,0x4b,0xb8,0x51,0xb9,0x96,0x64,0x1d,0x44,
+  0xd5,0xa7,0x0c,0x15,0x49,0x91,0x59,0x61,0xce,0x09,0x95,0x87,0x44,0x65,0xe0,0xeb,
+  0xf3,0xae,0x57,0xa7,0x89,0x9c,0xb9,0xcc,0x62,0x7f,0xc0,0x7e,0xe3,0x3c,0x66,0xbd,
+  0x8f,0xd4,0x02,0xe8,0x6b,0xe7,0xb3,0xfd,0x7e,0xd6,0x5a,0x64,0x76,0x9a,0x5a,0x94,
+  0x5a,0xd2,0xdb,0x86,0xfd,0x93,0xb3,0xaa,0xb5,0xb0,0xfd,0x9c,0x0d,0x7b,0xeb,0x61,
+  0xc8,0x1a,0xbc,0x33,0xe0,0xf9,0x00,0xa7,0xec,0x38,0xe0,0x31,0x92,0x11,0x8c,0xbb,
+  0x05,0xda,0xfd,0x01,0xee,0xbb,0x56,0xe2,0xaf,0xe6,0x88,0xf0,0x27,0xf1,0xcb,0x18,
+  0x09,0x01,0x0c,0xd4,0x03,0x30,0xdd,0x30,0x75,0xdd,0x34,0x54,0xc1,0x22,0x47,0x7c,
+  0x66,0x0b,0xaf,0x1a,0xba,0x5e,0x37,0x55,0x55,0x90,0xe2,0x5a,0xff,0x9d,0xc5,0x27,
+  0xb4,0xcd,0x7e,0xa7,0x53,0x98,0xeb,0x53,0x8a,0x4a,0x9a,0x51,0x46,0x47,0x6c,0x04,
+  0x4f,0xb4,0x6c,0xe6,0xec,0x55,0x5b,0xf8,0xd8,0x07,0x59,0x93,0x65,0xf3,0x52,0xe0,
+  0xcb,0x6a,0x53,0x51,0x23,0x65,0x73,0xc7,0x68,0x0a,0x7b,0x5c,0xf6,0xb9,0x40,0x05,
+  0x13,0x9f,0xdb,0xa6,0xb0,0xbc,0x2e,0x7a,0x46,0x45,0x43,0x47,0xcb,0x6e,0x8a,0x37,
+  0xa2,0x1f,0x09,0x61,0xa7,0x3b,0x11,0x6b,0xa7,0xdc,0xa6,0xcc,0xa8,0xf4,0x20,0xd3,
+  0x11,0x43,0x52,0x5e,0xd0,0xca,0x6a,0x68,0xd0,0xeb,0xa3,0x9c,0x38,0x34,0xed,0x0a,
+  0x34,0xcf,0xac,0xfb,0x32,0xcd,0xbe,0xe3,0xbe,0x12,0x17,0xe1,0xff,0x4b,0xde,0x30,
+  0x1f,0x85,0x4d,0x5b,0x5a,0xc6,0x39,0xb2,0xb0,0xa5,0x07,0x68,0x05,0x40,0xda,0x05,
+  0xdd,0x40,0xe0,0xc3,0x96,0x0b,0x80,0xf3,0x81,0x6f,0x39,0x7c,0x0b,0xe9,0x12,0xf8,
+  0xdc,0x7f,0x1c,0xf4,0xb6,0xec,0x92,0x4c,0xb2,0xfb,0xbd,0xef,0x75,0x93,0x08,0xa4,
+  0x07,0xc6,0xe8,0x00,0x60,0x20,0x25,0x10,0x6f,0x17,0x5a,0x5b,0xab,0x85,0x88,0xc9,
+  0x97,0x23,0x49,0x89,0x23,0x1c,0x30,0x13,0x2b,0xd9,0x85,0xb6,0x2e,0x48,0xd1,0x68,
+  0xbf,0x5d,0x95,0x8a,0x0b,0x41,0xba,0x47,0xa9,0x4b,0xb9,0x9e,0x47,0x5e,0xca,0xb4,
+  0x5b,0x89,0x8e,0xe4,0x88,0xfd,0xa9,0xda,0xab,0x56,0xf4,0x56,0x62,0x71,0xa1,0x51,
+  0x17,0xe5,0x2b,0x10,0xea,0x44,0x90,0x2b,0x4a,0x53,0x19,0x49,0x24,0xb2,0x5a,0xa3,
+  0x2e,0x5c,0x2c,0x5e,0x06,0x6d,0xe2,0xc3,0x1a,0xba,0x1b,0x4b,0x91,0x1d,0xfe,0x42,
+  0x99,0x12,0xf9,0x37,0x6b,0x2b,0xb5,0x85,0x6d,0xf1,0x46,0xf4,0x23,0xcb,0x5f,0xd0,
+  0xf6,0xd2,0xd0,0x59,0x72,0x41,0xb9,0x05,0x37,0xe5,0x2e,0xdd,0x84,0xda,0x46,0x47,
+  0xb8,0xc9,0x2e,0xdb,0x9c,0x32,0x54,0x7d,0xf0,0x39,0xe6,0x9f,0xbd,0xdb,0x15,0xaf,
+  0x69,0xfb,0x39,0x6b,0x5b,0x6a,0x4f,0x2e,0xc3,0xac,0xc5,0x77,0x2d,0xfd,0x34,0x25,
+  0x9c,0x8e,0x1d,0x9f,0x76,0xcd,0xb9,0x2d,0xba,0xee,0xb6,0xdc,0x5f,0xad,0x6f,0x1c,
+  0x11,0x0f,0x3b,0x0b,0x7a,0xde,0x81,0x77,0x20,0x5e,0x3d,0xc2,0xde,0x83,0x57,0x11,
+  0xc0,0xb5,0x80,0xb0,0x5b,0x09,0xb0,0xda,0x01,0x70,0x97,0x20,0xd2,0x0e,0x88,0xaa,
+  0x00,0xff,0x70,0x6d,0xda,0x00,0xcc,0x62,0x97,0x08,0xbf,0xa5,0x00,0xbe,0x3a,0x96,
+  0x1e,0xb0,0x05,0x20,0x5e,0x28,0x2c,0x27,0x16,0x0b,0xeb,0x26,0xaf,0xd1,0x7d,0x94,
+  0xbf,0x32,0x61,0x6e,0x2d,0xc7,0x32,0x17,0xa9,0xf0,0x9d,0x4d,0xa6,0xcf,0x1e,0x93,
+  0xd9,0xa0,0x9d,0x23,0x37,0x33,0xbd,0xea,0x12,0xa5,0x4c,0xa3,0xf2,0xe2,0xa2,0xb6,
+  0x5e,0x97,0xd8,0x20,0x1f,0xe6,0xed,0x55,0xab,0x23,0x2b,0x2d,0x22,0x32,0xbb,0xbb,
+  0x37,0xcd,0x03,0xc1,0xae,0xa9,0xc7,0x7c,0xbd,0x85,0x76,0x78,0x51,0xdc,0xe1,0x96,
+  0xcf,0xb9,0x0d,0x6b,0xcb,0x52,0xdd,0x26,0x11,0xc5,0x90,0x11,0x5b,0xae,0xad,0x4a,
+  0x14,0x71,0x3f,0x16,0xf9,0x2d,0x0d,0xb7,0x2b,0x67,0x3b,0x6b,0x62,0x11,0x68,0xca,
+  0x87,0x91,0xcf,0x18,0xda,0x76,0x59,0xb8,0xfd,0xaa,0x11,0xc4,0x03,0x14,0x38,0x79,
+  0x28,0xec,0x48,0xac,0x2b,0x89,0xd3,0xb4,0x14,0x7a,0x4e,0x7a,0x78,0xda,0xfb,0x79,
+  0xd6,0x15,0xd9,0x69,0x6a,0x71,0x47,0xca,0x69,0xc3,0x4d,0xfd,0xc8,0x2e,0x4f,0x43,
+  0x2f,0x18,0xf6,0xfe,0xcd,0xf2,0x55,0x11,0xc6,0x0d,0xb0,0xe3,0x00,0x96,0x06,0xf0,
+  0x82,0x00,0x76,0x15,0xe0,0x70,0xf9,0x9a,0x28,0x80,0x2c,0x76,0xfd,0x93,0x9f,0x8d,
+  0x7e,0xc9,0x56,0x00,0x71,0x77,0x08,0x90,0x60,0x2a,0xa0,0x54,0x28,0x54,0x2c,0xf9,
+  0xe7,0x36,0xbc,0xe3,0x23,0x83,0x45,0x3d,0xd6,0xaa,0x65,0x24,0xc5,0x4e,0xeb,0xbd,
+  0xbb,0xb9,0xc6,0x54,0xf0,0x01,0xd2,0xea,0xbd,0xaa,0xda,0xa3,0xeb,0x43,0x2b,0xc8,
+  0x8a,0x9b,0xc1,0xad,0x78,0xc5,0x39,0x86,0x91,0x04,0x12,0xc7,0x36,0x16,0xc7,0x5d,
+  0xdd,0x9c,0xaa,0xff,0x41,0xf9,0x9c,0x74,0x3d,0x81,0x6c,0x74,0x5b,0xb4,0xff,0x3e,
+  0xce,0x52,0x49,0x2b,0xc8,0x45,0x51,0x22,0xff,0x29,0xb3,0x36,0x14,0x43,0x37,0x62,
+  0x67,0x50,0xf9,0xe7,0x15,0x75,0x49,0x6b,0x54,0x56,0x16,0xd7,0x1a,0xc2,0x4e,0xa7,
+  0xa4,0xf2,0xdf,0xad,0x47,0xd6,0xd6,0x85,0x33,0x6a,0xaa,0xea,0xe6,0x6e,0x66,0x9d,
+  0x78,0xf0,0xe8,0x74,0x98,0xd2,0x00,0x9e,0x39,0x77,0x45,0x72,0x36,0xec,0x49,0x3d,
+  0x25,0x9b,0xae,0x1e,0xa0,0x3e,0xb2,0xb5,0x7e,0x6f,0xe1,0x30,0xa5,0x13,0x6c,0xdb,
+  0xef,0xca,0x33,0x13,0x57,0x70,0xa3,0x08,0xb3,0xd3,0xd3,0x8c,0x0e,0x99,0xf5,0x8e,
+  0x8c,0x52,0x01,0x87,0xec,0x28,0x80,0xdd,0x2f,0x88,0x54,0x01,0x1e,0x21,0x1e,0xc0,
+  0x91,0x83,0x2f,0x7d,0x7a,0xf0,0x9a,0xd9,0xe0,0xe8,0x21,0x64,0xfd,0xbf,0x14,0xc5,
+  0x7c,0x29,0x4a,0x6a,0x00,0x4f,0x33,0xf6,0xbf,0xaf,0x0a,0x20,0x37,0x3f,0x2b,0xb9,
+  0xf9,0x7e,0x95,0xb9,0x94,0x5e,0x5b,0x8e,0xad,0xb6,0x23,0x82,0x01,0x58,0xea,0x55,
+  0x6f,0x1f,0xab,0x19,0x53,0xcd,0x01,0xae,0x47,0x33,0xe3,0xdf,0x14,0x90,0x8d,0x2c,
+  0xa3,0x23,0xde,0xae,0x07,0x75,0x27,0x9a,0x53,0x2d,0x7b,0xcd,0x9c,0x99,0x58,0xae,
+  0x11,0xdf,0x25,0xf8,0x91,0xd0,0xe4,0xfb,0x5d,0x4d,0x9e,0x09,0xa2,0x70,0x2e,0x8a,
+  0x0a,0x67,0x55,0x7e,0x63,0x4a,0x9d,0xe1,0x65,0x24,0x8a,0xeb,0x82,0xfd,0x97,0xdc,
+  0x8d,0xa8,0x99,0x5d,0xc6,0x75,0x05,0xe1,0x46,0xf4,0x63,0x8d,0xdf,0xf7,0x28,0x2e,
+  0x02,0xda,0x69,0x93,0xbf,0xa0,0x6e,0xdc,0x84,0xa1,0xaa,0x0e,0x2f,0x95,0x05,0x73,
+  0xa1,0x1a,0x6a,0x63,0x57,0x39,0x1c,0xef,0x3a,0x34,0xcd,0x8a,0xba,0x23,0x7d,0xe4,
+  0x93,0x6b,0xcf,0x67,0x29,0x6f,0xc0,0x5e,0x86,0x96,0x58,0x46,0x4f,0xb8,0xda,0x63,
+  0xd6,0xae,0x0a,0x50,0x51,0x42,0x4f,0x75,0x38,0x72,0x2d,0x84,0x0f,0xbc,0xbd,0xbb,
+  0x1a,0x80,0xab,0x24,0x78,0x2a,0xe0,0x50,0xd8,0x4d,0x0a,0xc6,0xed,0x00,0x58,0x01,
+  0xe0,0xc1,0xc1,0x0e,0x9f,0x78,0xf2,0xe0,0x35,0x19,0x0f,0x30,0xd1,0xfd,0x5e,0x32,
+  0x6a,0x43,0x1c,0x80,0xb1,0x78,0x3a,0x3e,0x48,0x17,0xa0,0x52,0xa7,0x81,0xfc,0x7f,
+  0x6d,0x5d,0xb0,0xa6,0xaa,0x8f,0x36,0x4f,0x59,0xc5,0xae,0x2c,0xc8,0x50,0xaf,0xdb,
+  0x1f,0x2d,0xa8,0x53,0x03,0xca,0xdc,0xba,0xaf,0x35,0x49,0x44,0x5a,0x2b,0x59,0x54,
+  0x8b,0x0f,0xee,0xc5,0x3b,0x8e,0xe9,0x84,0x91,0x68,0xc5,0x16,0xda,0xe2,0xb1,0x07,
+  0xa2,0x39,0x35,0x14,0xec,0x9a,0x7a,0x14,0xcd,0x04,0x76,0x96,0xc4,0x1d,0xfa,0x39,
+  0x4b,0xd9,0x06,0xf2,0xc6,0x90,0x28,0x0a,0x77,0x43,0x0c,0x3d,0x24,0xeb,0xa3,0xe8,
+  0x46,0x14,0x06,0x3f,0x99,0x36,0xbf,0xef,0x5a,0x04,0xdb,0xff,0x19,0xd1,0xa1,0x9a,
+  0x93,0x1c,0x61,0x49,0x33,0xd7,0x24,0x41,0x07,0x75,0xb3,0xd9,0x92,0x2c,0x1d,0x80,
+  0xa3,0x61,0xda,0xe0,0x0b,0x0e,0xbc,0x6b,0x8d,0x5d,0x15,0xe1,0x85,0x03,0x1c,0x7b,
+  0xee,0x48,0xf4,0xec,0x34,0xad,0x21,0xc2,0xd3,0xb4,0xec,0x3a,0xba,0x40,0xf0,0xe9,
+  0xc3,0x94,0x3b,0x30,0x4b,0xad,0x45,0x1d,0x8e,0xa7,0x8e,0x9c,0x8d,0x7b,0x2e,0x00,
+  0x69,0x09,0x20,0x83,0x04,0xdc,0x8d,0x83,0x00,0x76,0x7f,0x20,0x5c,0x05,0xf8,0xd7,
+  0x57,0x7f,0x28,0x80,0x46,0x0a,0x09,0x7d,0x34,0x9a,0xc2,0x20,0x0f,0x00,0x57,0x00,
+  0xdc,0x3e,0x00,0x01,0x23,0x80,0xd9,0xc6,0x72,0x6b,0x14,0x4b,0x13,0x7f,0x43,0x7d,
+  0x82,0x5d,0x51,0xdd,0x2a,0x76,0x82,0xc3,0x10,0xf1,0x8f,0xfe,0x14,0x1b,0x53,0x92,
+  0x06,0x83,0x29,0xec,0x35,0xe2,0x07,0x7a,0x4e,0x35,0xa7,0x78,0x13,0x69,0xfa,0x35,
+  0x3f,0x55,0x74,0x5c,0xa9,0x6e,0xe8,0x72,0xff,0x5f,0xb6,0x9b,0x8e,0xbd,0xa6,0x57,
+  0x65,0x1e,0xdc,0x35,0xc3,0x6b,0xf8,0x44,0xed,0xfc,0x09,0x99,0xc8,0x59,0xca,0x2c,
+  0xe9,0x82,0xb9,0x6c,0xfb,0x28,0xcb,0x44,0x03,0xdb,0xff,0x86,0x10,0xdb,0x90,0x98,
+  0xe2,0xb1,0x48,0x67,0x79,0xab,0xb3,0x14,0xd9,0x19,0xf4,0x64,0x04,0x45,0x9d,0xd0,
+  0x97,0x57,0x6a,0xda,0xb6,0xa8,0x50,0x65,0xfe,0x4e,0x74,0x27,0x82,0xac,0x05,0xbf,
+  0x68,0x53,0xdd,0x34,0x02,0x35,0x00,0x8b,0x7c,0xe2,0x55,0x56,0x64,0xd9,0x00,0x9e,
+  0xf7,0x8b,0x2b,0xf8,0xb3,0xfc,0x37,0xb3,0x9c,0x08,0x33,0x91,0x40,0xea,0x0d,0x5d,
+  0x05,0x90,0x35,0x27,0xb8,0xbf,0xda,0x7b,0x98,0xf5,0x5c,0x7e,0x26,0x1a,0xc1,0xb6,
+  0x09,0x1e,0x3a,0xe4,0xd4,0x01,0x88,0x02,0xb0,0x5b,0x01,0x4e,0x9c,0x78,0xe9,0xc4,
+  0x37,0x06,0xbb,0x2f,0x83,0xd3,0xac,0xb8,0xe2,0x7f,0x06,0xfd,0x11,0x07,0x20,0xfd,
+  0xf4,0x60,0x19,0x00,0x09,0xe4,0x4d,0xbf,0x57,0x9b,0xd1,0x05,0xff,0x5f,0xea,0xfc,
+  0x29,0xca,0xf7,0xf4,0x4e,0xc5,0x2a,0x76,0xdc,0xc1,0x94,0xc7,0xfc,0x76,0x91,0xd3,
+  0xa7,0x24,0x12,0xd7,0x44,0x3a,0x41,0x55,0x0d,0x1b,0x55,0x94,0x66,0xa3,0xf2,0xac,
+  0x74,0x73,0x93,0x7a,0xcb,0x0a,0x7c,0xfb,0x5c,0x14,0xe4,0x69,0x60,0x8d,0x62,0xfd,
+  0xe1,0x0f,0x6e,0x8d,0x17,0x55,0x99,0x91,0xee,0xea,0x61,0xff,0x55,0x6b,0x5d,0x55,
+  0xb5,0xf4,0x92,0x6a,0x29,0x27,0x02,0x3a,0xda,0xc1,0x03,0x5c,0x78,0x87,0x31,0xd9,
+  0x0e,0xfd,0x9c,0xa5,0xa1,0x08,0xae,0x8d,0x6d,0x0b,0xae,0xb8,0x24,0xf4,0x90,0x8e,
+  0x64,0xe4,0x37,0xc2,0xbe,0x0c,0xaa,0x7d,0x3a,0xce,0xa3,0x49,0xce,0x0c,0xbd,0x13,
+  0x14,0x35,0x52,0xa8,0xd6,0x4e,0xf9,0x7b,0x24,0x6b,0xa5,0xac,0xa8,0x05,0x51,0xe7,
+  0x34,0x91,0xfb,0x3f,0xbc,0xdb,0x74,0xb3,0x47,0x68,0x33,0x4f,0x07,0x01,0x9d,0x0a,
+  0x00,0x6d,0xee,0x3d,0x19,0xa7,0x7d,0x00,0x46,0x84,0x5d,0xb1,0x9d,0xa6,0xb4,0x01,
+  0x15,0xdb,0xa7,0x43,0x0c,0x61,0xf7,0x2d,0xd3,0x4c,0x40,0x2d,0x3d,0xeb,0x56,0x30,
+  0x5c,0xd3,0x3f,0xcd,0x06,0x02,0x3d,0x05,0x70,0x2b,0xc9,0x05,0xc4,0xa9,0x80,0x44,
+  0x01,0xfc,0x93,0xab,0xdd,0x11,0xb0,0xfd,0xd4,0xf7,0xbe,0x94,0x24,0xc2,0x1f,0x3a,
+  0x43,0x3c,0x00,0x2c,0xff,0xe9,0xb8,0x3b,0x08,0x70,0x10,0x17,0xa0,0x85,0xa5,0x09,
+  0x2b,0x7f,0xde,0xe2,0xf8,0x04,0xbb,0xc6,0x22,0x19,0x6c,0x76,0xd6,0x85,0x26,0x2a,
+  0xbf,0x06,0x43,0x65,0x4e,0x6f,0x4a,0x04,0x0e,0x95,0xc4,0x4d,0x63,0xc7,0xac,0xd7,
+  0x75,0xbd,0xac,0xd7,0xeb,0xb8,0x41,0xdf,0x52,0x41,0x5e,0xc9,0x52,0x87,0xa4,0x47,
+  0x3f,0x67,0xae,0x58,0x95,0x6a,0x89,0xe1,0xc3,0xc2,0xba,0xb9,0x69,0xe0,0x07,0x52,
+  0x2d,0xa8,0x54,0xe2,0xff,0xcd,0x82,0xbd,0x1d,0x5c,0x65,0x8e,0xe1,0xe6,0x35,0x69,
+  0xd3,0x01,0x11,0x79,0xa2,0x8c,0x36,0x0d,0xfa,0x9f,0xa3,0xa1,0x8c,0x66,0x47,0x76,
+  0x38,0xbd,0xc0,0xce,0x12,0xda,0x61,0x59,0xb0,0xd1,0x0d,0x1f,0x67,0xa9,0xa2,0x57,
+  0xac,0xba,0x0d,0x7f,0x80,0xa2,0x29,0x8e,0x37,0xb4,0x8a,0xd5,0x6c,0x27,0xc9,0xa6,
+  0x54,0xad,0xeb,0xe0,0x5d,0x03,0xfc,0x44,0x7f,0xe8,0xad,0x1a,0x79,0x86,0xdb,0x52,
+  0xde,0xb4,0x15,0x2a,0x7f,0x3d,0x63,0xe2,0x01,0xc6,0xdb,0x75,0x59,0x7b,0x26,0xba,
+  0x38,0x03,0x07,0x47,0x1c,0xde,0xf5,0x2a,0x65,0xaf,0x67,0xa7,0x69,0x01,0xf6,0x6c,
+  0x39,0x1b,0x13,0xa4,0x65,0x97,0x8e,0xe4,0x51,0x3f,0xcf,0x7a,0x6b,0xb2,0x75,0x0b,
+  0xc6,0xa9,0xe7,0x32,0x03,0x3c,0xff,0x62,0x96,0x51,0x45,0xb3,0x9e,0xba,0xa0,0xdc,
+  0x0f,0xfc,0x24,0x1d,0x87,0xc3,0xac,0x02,0x40,0x55,0x00,0x5c,0x03,0x38,0x72,0xe2,
+  0xd7,0x25,0xa5,0x6c,0x1f,0x51,0xab,0xdd,0x64,0xf4,0xa9,0x54,0x2a,0x44,0x20,0xf2,
+  0x8f,0x15,0x80,0xeb,0xff,0x07,0x52,0xc8,0xf9,0x11,0xeb,0xe6,0x0b,0xa5,0xc8,0xe7,
+  0x7e,0xa6,0x1b,0x99,0xe5,0x17,0x3b,0x85,0x75,0xc1,0xec,0x48,0x9a,0xa8,0x09,0x39,
+  0x1d,0x15,0x3b,0x51,0x52,0x51,0x79,0x34,0xeb,0x91,0xf5,0xc6,0xf6,0xc5,0xf6,0xc5,
+  0xed,0xed,0x46,0xa4,0x5c,0x7f,0xdc,0xe0,0x93,0x59,0x36,0xa5,0x19,0x65,0x38,0x8a,
+  0x17,0xb3,0xa2,0xf8,0xc2,0x46,0xd1,0x56,0x77,0x4c,0xd3,0x1c,0x31,0xeb,0x23,0x75,
+  0xac,0x5b,0xea,0xba,0x89,0x54,0x8b,0x23,0xff,0x49,0x7d,0xb4,0x82,0x8f,0xbd,0xbe,
+  0x29,0x56,0x13,0x9a,0x58,0x1f,0xa1,0x55,0xb1,0x42,0xaa,0x63,0xd0,0xba,0x75,0x07,
+  0xfc,0x4e,0xd7,0xd5,0x85,0x41,0x4d,0x5c,0xd2,0xad,0x2c,0x71,0x7b,0xf3,0xab,0x2c,
+  0xe5,0x75,0x12,0xdb,0xd0,0x85,0x0b,0x26,0x9a,0xe2,0xf8,0x8c,0x36,0xb4,0xd2,0x59,
+  0x93,0xc9,0x3f,0x3e,0x15,0xeb,0x5c,0xd0,0x45,0xd0,0x4d,0xdd,0x7a,0x43,0xde,0xd7,
+  0xeb,0x86,0xce,0x67,0x76,0x55,0xcd,0x56,0x2b,0x8b,0x8a,0x80,0xe0,0x82,0x49,0xfc,
+  0x9d,0x90,0xd1,0x40,0xbb,0xe4,0xe5,0x1f,0x69,0x1b,0xbf,0xdb,0x1f,0x80,0x63,0x61,
+  0x4e,0xd8,0x59,0x7b,0x4e,0x09,0xac,0x63,0x7a,0xe9,0x25,0xa9,0xa8,0xdd,0x2c,0xa3,
+  0x25,0xc2,0x94,0x1d,0xa7,0xf4,0x05,0xb5,0x29,0xa6,0xfa,0x4f,0xbb,0xfb,0x9e,0xa8,
+  0xd3,0xaa,0xc8,0xab,0x0a,0xb8,0x4b,0xda,0x6e,0x80,0x13,0x04,0x20,0x55,0x00,0xdc,
+  0x0a,0x78,0x3f,0xce,0x04,0x3e,0xf1,0x5f,0x47,0x84,0x3b,0xb3,0x9f,0x14,0xa2,0xc4,
+  0xf9,0x0f,0x85,0x2e,0x5d,0xba,0x84,0x14,0xc0,0x99,0x14,0x92,0x7f,0x2f,0x03,0x20,
+  0xe0,0x2c,0x20,0xe8,0xe6,0xaf,0xc4,0x2c,0xe5,0xcf,0x96,0x39,0x9f,0x70,0x4e,0xbc,
+  0xad,0x0d,0x25,0x16,0x91,0xd9,0xe1,0x4b,0x8b,0x4f,0x83,0x61,0x11,0x89,0xbf,0xc1,
+  0x8b,0x1b,0x36,0xb4,0x66,0x7d,0x7d,0x66,0xa9,0xb0,0xb6,0x90,0x41,0x8f,0x85,0xb5,
+  0x42,0xfb,0x74,0xa4,0x6e,0xe7,0x21,0x52,0x1e,0x40,0x5e,0x72,0x02,0x13,0x46,0x02,
+  0x1d,0xf1,0x92,0x24,0x8a,0xaf,0x36,0x8d,0x1d,0xbd,0xbc,0xde,0x68,0x9c,0x9e,0x99,
+  0x39,0xbd,0xdd,0xd8,0x6e,0x9c,0x6e,0xe0,0xff,0xa6,0x53,0xdb,0x1e,0xd3,0x3b,0xa8,
+  0x7a,0xad,0x9d,0x96,0x36,0x00,0xe0,0x43,0x2a,0x97,0xd7,0xf1,0x9a,0x48,0x1f,0x6d,
+  0xcf,0x34,0xf0,0xff,0x19,0xe7,0x89,0xd9,0x19,0xd8,0xc5,0x7d,0xc6,0xf6,0xd1,0x85,
+  0x7c,0x39,0x41,0x06,0x6d,0xe6,0x48,0x6c,0x43,0xf4,0xc6,0x24,0xa1,0x87,0x52,0x7b,
+  0x98,0xb4,0x15,0x3e,0xbe,0x29,0x3b,0x95,0x11,0x3d,0xb2,0xbe,0x8e,0x4e,0x03,0x1d,
+  0x3c,0xba,0x18,0xe8,0x6c,0x66,0xf0,0x39,0x9d,0x46,0x57,0x46,0xdf,0x89,0x72,0x5b,
+  0xca,0x19,0x2b,0x56,0xb3,0x28,0xbf,0x53,0x89,0xbf,0x93,0x50,0xd7,0x24,0xd5,0x99,
+  0xa6,0xd1,0x37,0xfd,0xa3,0x07,0xf7,0x86,0x05,0xb9,0xa4,0x7c,0x78,0xc7,0x85,0x0f,
+  0xbb,0x96,0x98,0x56,0x0b,0x64,0x71,0x2a,0x28,0x48,0x6f,0xc3,0x5d,0x9d,0x72,0x0c,
+  0x3c,0x01,0xef,0x4b,0x98,0xf6,0x1d,0xbc,0x30,0x64,0xd8,0x0b,0x33,0x7a,0x95,0x00,
+  0x41,0x01,0x90,0x18,0xe0,0x91,0x7f,0x21,0x16,0xb3,0x7d,0x04,0xd5,0xfe,0x2d,0xf1,
+  0x2f,0x16,0x2f,0x14,0x2f,0x5d,0x3a,0x83,0x23,0x00,0x5d,0xb7,0x0f,0x80,0x12,0x6c,
+  0x1c,0xe0,0x39,0x1c,0xa2,0x5e,0x95,0x44,0x74,0xfd,0x52,0xd4,0x0a,0x05,0x64,0x43,
+  0x25,0x4d,0x54,0x86,0xb4,0xc1,0x30,0x1a,0x51,0x4d,0xd1,0x51,0x47,0xf6,0x49,0x2f,
+  0x37,0x96,0x16,0x56,0x3b,0x8b,0x35,0xc2,0x62,0x67,0x41,0x5b,0xda,0x2e,0xd7,0x91,
+  0xaa,0x60,0x8e,0xc3,0x90,0x84,0xa0,0x8b,0x23,0xb1,0xe5,0x98,0x2c,0x03,0x01,0xf9,
+  0x14,0x3b,0xfa,0x7a,0xbb,0xb0,0xa6,0x69,0x6b,0x0b,0xe4,0x6f,0x81,0xfc,0x45,0x1c,
+  0x6f,0x3b,0xad,0x77,0x2a,0xe8,0x64,0xdb,0x65,0x49,0xee,0x40,0x53,0xdd,0x34,0xcb,
+  0x78,0x65,0xb4,0x86,0xb6,0x40,0xd0,0xd0,0xff,0x35,0xf2,0x24,0x9f,0x16,0x74,0x21,
+  0x72,0xde,0x0f,0xe4,0x2c,0x55,0x62,0xa8,0xb2,0x24,0xd8,0x7f,0x7f,0x67,0x09,0x7b,
+  0x63,0x92,0x16,0x4a,0xd1,0x14,0x97,0xb4,0x36,0xce,0x83,0x12,0x15,0x31,0xe9,0x4f,
+  0x59,0xde,0x5e,0xc2,0x97,0x01,0x3f,0xc8,0xa5,0x40,0x0f,0xf2,0xaa,0xad,0xb5,0x85,
+  0xcc,0xae,0x09,0x73,0xab,0x55,0xcb,0x5c,0x7c,0x8f,0xb0,0xd3,0x8c,0xe4,0x84,0xf4,
+  0x35,0xa4,0x3e,0xf9,0xa6,0xdc,0x4d,0x55,0x95,0xb5,0x15,0x04,0xe4,0xc1,0xbb,0x3d,
+  0x01,0x77,0x83,0xfd,0x54,0x62,0xbf,0xf3,0xe5,0xac,0x53,0x43,0xa0,0xd5,0x02,0x23,
+  0xb0,0xac,0x89,0x67,0x72,0x02,0xdd,0x60,0xe1,0xb4,0xd3,0x0c,0x40,0xfb,0x04,0x52,
+  0x17,0x80,0x51,0x34,0xee,0x0e,0xec,0x2f,0xbc,0x16,0x04,0x4b,0x01,0x38,0xdd,0x01,
+  0x48,0x1e,0x00,0xee,0x0b,0x80,0x15,0xc0,0x63,0x9b,0x7c,0x31,0xdb,0x47,0x8c,0x22,
+  0x36,0xff,0x44,0xfa,0x11,0x45,0xe4,0x02,0x20,0x07,0xe0,0x7b,0x56,0x00,0x20,0x78,
+  0x0d,0x20,0xa7,0x93,0x9c,0x18,0x51,0xa7,0xfb,0x04,0xbb,0x4a,0x85,0x76,0x85,0x34,
+  0x51,0xf3,0xee,0xb7,0xb4,0xc1,0x70,0xac,0xa0,0xea,0x82,0xf1,0x6b,0x12,0x39,0x5d,
+  0xd2,0x56,0x17,0x6b,0x67,0x13,0x2b,0x2b,0xcb,0xad,0x95,0x95,0x95,0xad,0xd8,0x62,
+  0x66,0xad,0xbd,0xae,0xf3,0xae,0x65,0x5d,0xdc,0x6a,0xca,0xac,0xb5,0x62,0x19,0x49,
+  0x1b,0x34,0x2e,0xf7,0xeb,0x85,0x85,0xd5,0xc5,0xc5,0xc5,0x6c,0x36,0x8b,0xff,0x30,
+  0x8b,0xb5,0x25,0xc7,0xdb,0x8e,0x47,0x32,0xf9,0xe5,0xad,0x8e,0xd6,0xb0,0x8e,0x89,
+  0x3d,0x01,0xd5,0xa8,0x97,0xdb,0x6b,0x99,0x55,0xb4,0x42,0xb6,0x96,0x45,0xcf,0x9a,
+  0x0b,0xf9,0x5c,0xcb,0x36,0xfc,0xa2,0xf6,0xbe,0x90,0x3a,0x3a,0x72,0x96,0x1e,0xe7,
+  0xfd,0x79,0xc1,0x06,0xdb,0x14,0xf5,0xc4,0x32,0xbe,0x1b,0x42,0x5a,0xbf,0x90,0xb4,
+  0x87,0x5b,0x6e,0xad,0xb4,0x9d,0x4d,0xbe,0x60,0x34,0x55,0x13,0x9d,0x09,0xd2,0xad,
+  0xce,0x25,0x60,0x58,0x10,0x02,0xf5,0xb8,0x95,0xd2,0x6a,0x16,0xe5,0x76,0x2a,0xb6,
+  0x52,0x4e,0xa8,0x6d,0x49,0xc4,0x41,0x35,0x54,0xdd,0x37,0xfa,0x1b,0x80,0x23,0x61,
+  0x2f,0x2e,0xef,0xb9,0xdb,0x8e,0xe5,0x0e,0xd3,0x5f,0x92,0x77,0xae,0x5f,0x3e,0x4b,
+  0xfb,0xe5,0x7c,0x74,0xc0,0x75,0xe2,0xa9,0xf8,0x21,0xab,0x22,0xe8,0xaa,0x83,0x67,
+  0xf1,0xa9,0x0c,0x00,0xcf,0xd7,0x70,0x74,0x13,0xa5,0x75,0xc2,0x82,0x07,0x80,0x47,
+  0x0e,0xbf,0xd5,0x6e,0x04,0x20,0x35,0x80,0xc3,0xa7,0xf9,0x7b,0xb3,0x8f,0xb4,0x91,
+  0xfb,0x8f,0xad,0xff,0x85,0x09,0xcc,0x85,0x22,0x91,0x7f,0xdc,0x09,0x88,0xee,0x03,
+  0xd8,0x57,0x03,0xd8,0xd6,0x54,0xbc,0xf9,0x1d,0x9f,0x14,0x15,0xad,0x3d,0xb4,0x42,
+  0x12,0x06,0xf8,0xe3,0x91,0x34,0x18,0x96,0x62,0xaa,0x29,0x36,0x2b,0x21,0x4b,0xab,
+  0x6f,0x17,0x32,0x8b,0xb1,0x44,0x6b,0x39,0x4f,0xa8,0x54,0x96,0x57,0x56,0x6a,0x8b,
+  0x99,0x42,0x03,0xb7,0x2b,0x32,0xa5,0xab,0xf1,0x3d,0x7e,0xa3,0x51,0x12,0x54,0xc7,
+  0x19,0x08,0x42,0xc2,0x3a,0x2a,0xf7,0x0b,0x8b,0x35,0xdc,0x23,0x8e,0x46,0x33,0x6d,
+  0x6f,0x3b,0xbe,0xad,0x4d,0xe6,0x57,0x6a,0xab,0x05,0x31,0x7f,0x0d,0x2b,0x0f,0x73,
+  0x7d,0x69,0xa1,0x53,0xdb,0x4a,0xac,0x60,0x85,0xd4,0xb2,0x57,0x6e,0x79,0x9f,0xb4,
+  0x1e,0x4d,0x9c,0x72,0xe2,0xed,0xb5,0x4a,0x82,0xd4,0xd1,0xb9,0xbd,0xc9,0x9d,0x25,
+  0x54,0xbd,0xd6,0x13,0x72,0x57,0x5c,0xe2,0x5e,0x93,0x3c,0xa8,0x85,0xd3,0x42,0x65,
+  0x1c,0x9d,0x49,0xbd,0xb1,0xb6,0x9a,0xdd,0x5a,0xa1,0xae,0x83,0xf7,0x36,0x2b,0x28,
+  0xea,0x94,0x11,0x6b,0x91,0x22,0xc0,0xdf,0xd2,0x25,0x61,0xa7,0xa3,0x86,0xcc,0xfd,
+  0x57,0x0d,0xa1,0x53,0xc1,0x40,0xbc,0xff,0x10,0x25,0x5d,0x5e,0xa4,0x9f,0x16,0x36,
+  0x4a,0xb2,0xa7,0x3d,0xf1,0x73,0x7f,0x9d,0x9d,0xf6,0x7c,0x7b,0x5a,0xb4,0x6d,0x8f,
+  0x21,0xcc,0xaf,0xec,0x1a,0x79,0xaf,0xa2,0x41,0x39,0x1c,0x61,0xaa,0xd6,0xe0,0x55,
+  0x44,0xa6,0xdd,0xdf,0xdd,0x1d,0x91,0x3f,0xba,0x0a,0x60,0x75,0x08,0xb6,0x5a,0x01,
+  0xb1,0x03,0x70,0x35,0x2b,0x00,0x2d,0x62,0xfe,0x8b,0xc5,0x89,0x6f,0xe5,0x72,0x97,
+  0x2f,0x63,0x05,0x60,0xb7,0x00,0x3c,0x3d,0x48,0x1f,0x80,0x10,0xb6,0xa6,0xb2,0x7c,
+  0x1e,0xbf,0x0a,0xdd,0x68,0x03,0xa7,0xdf,0x89,0x9d,0x68,0x64,0x0d,0x86,0x07,0x50,
+  0x95,0x9a,0x17,0x53,0x54,0xf7,0x37,0xcb,0xdb,0xa8,0x7c,0x9e,0x45,0xd2,0x3f,0x39,
+  0x39,0x59,0xad,0xce,0x23,0xf2,0xf9,0xe5,0x95,0xb3,0xd9,0xd5,0xb5,0x8b,0xc4,0xba,
+  0xd0,0x1a,0xa3,0xc3,0x1b,0x5d,0x12,0x54,0x93,0x35,0x7c,0x21,0xbb,0x17,0x59,0x5a,
+  0xad,0x25,0x96,0x2b,0xf9,0x4a,0xde,0x7a,0x56,0xf0,0xdb,0x8e,0xd3,0x34,0x51,0x1a,
+  0x5e,0x9b,0xcc,0x57,0x12,0xd9,0x85,0xa5,0x88,0x24,0x81,0xd5,0x30,0x23,0x48,0x7b,
+  0xc4,0x56,0x5a,0x68,0x25,0x01,0xfc,0x55,0x26,0x32,0xa8,0x91,0x2b,0x0d,0x93,0x7c,
+  0x3e,0x49,0x76,0xa5,0x4f,0x57,0xc2,0x14,0x49,0x18,0xba,0x18,0x11,0xee,0x86,0x24,
+  0xf4,0x90,0x88,0x0c,0x91,0x1b,0x21,0x56,0x83,0x76,0xf4,0xed,0x85,0x45,0xa2,0x5c,
+  0x2b,0xf6,0xc3,0x3e,0x07,0xfc,0x48,0x98,0xbc,0xa2,0xb6,0x14,0x6a,0x5b,0xdc,0xa9,
+  0xd0,0x4a,0xd9,0xd5,0x75,0x49,0xe3,0xff,0x14,0xba,0xc5,0xbb,0xc9,0xfd,0xf5,0x38,
+  0x3a,0x3d,0xed,0xba,0x00,0x9c,0xc0,0xb1,0xf9,0xf7,0x94,0xec,0x3a,0xd2,0xef,0x75,
+  0xe4,0x71,0x7b,0xf0,0x52,0x71,0x3d,0x4f,0x03,0xd0,0x61,0x04,0x46,0xa9,0x84,0xd9,
+  0xf7,0x54,0x5a,0x11,0x95,0x82,0x38,0x4b,0x39,0x14,0x54,0x4c,0x91,0xaa,0x3d,0x84,
+  0xc9,0xd8,0x40,0xa7,0x48,0x5f,0x00,0x3b,0x04,0x70,0xf8,0xc4,0xbf,0xdb,0xe4,0x6f,
+  0xce,0xbe,0x61,0x4c,0x58,0xde,0xff,0xc4,0xe5,0xcb,0xe7,0x2c,0x05,0x40,0x22,0x80,
+  0x76,0x06,0x40,0xdc,0x69,0x01,0xec,0xe7,0x03,0x44,0x47,0x6a,0x2d,0x69,0x9b,0xb8,
+  0x5f,0x8a,0x1a,0xce,0x16,0x93,0x66,0x8b,0x8a,0x35,0xc0,0xcf,0x46,0x0c,0x49,0xac,
+  0x78,0x13,0x15,0xcf,0xb5,0x4e,0x6d,0x65,0x19,0x4b,0x28,0x96,0x7f,0xa4,0x01,0xb0,
+  0x0e,0x40,0x1a,0xa0,0xd6,0x59,0xbb,0xc8,0x67,0x16,0xa9,0x7c,0x43,0x64,0x57,0xef,
+  0x2c,0x27,0x56,0x65,0xf2,0x8f,0x2c,0xb8,0xd6,0xd9,0x42,0xc5,0xbe,0x3a,0x39,0x6f,
+  0x31,0x89,0x37,0x5c,0x73,0x6a,0xbc,0x25,0x6d,0xb8,0x8a,0x76,0x73,0x76,0x51,0x6b,
+  0x47,0x1e,0x17,0x15,0x00,0x3e,0xae,0xd5,0xda,0x4a,0x05,0x1d,0x14,0x5e,0xb7,0x3a,
+  0xef,0x32,0x49,0x3e,0x75,0x7c,0x9b,0x38,0xfd,0x28,0x65,0xda,0xcb,0xc4,0x59,0xe2,
+  0x23,0xa0,0x7e,0xf2,0x12,0x1d,0x41,0xa6,0x58,0x96,0xa1,0x24,0x09,0x3d,0x24,0xf4,
+  0x21,0x79,0x5b,0x21,0xaa,0x06,0x5d,0x5c,0x40,0xe7,0x91,0x9f,0x97,0xb1,0x6c,0xf2,
+  0x8a,0x3a,0x69,0x35,0x8b,0x96,0x85,0x66,0x1a,0xc1,0xdf,0x99,0xc3,0x8d,0xff,0xbc,
+  0x32,0x6b,0xaa,0x9b,0xea,0xc0,0x9e,0x11,0xcb,0xc9,0xb0,0x6b,0xa1,0x67,0xbd,0xea,
+  0xbe,0x17,0x7d,0x9b,0xa5,0xdc,0x77,0xe7,0x9b,0x30,0x25,0x83,0x94,0x62,0x60,0x71,
+  0xd3,0x09,0xbd,0x58,0x80,0x97,0xde,0xeb,0x55,0x05,0xbc,0xf4,0x21,0x5a,0x3f,0x84,
+  0xe9,0xad,0x78,0xe1,0x3f,0xc7,0x3f,0x70,0xf7,0x68,0xb7,0x02,0x90,0x4e,0xc1,0x76,
+  0x08,0xe0,0xd8,0xed,0x47,0x49,0x1a,0xd0,0x37,0xd7,0xa7,0xae,0x16,0x8d,0x68,0x32,
+  0x85,0xcc,0xff,0xc4,0xe5,0xdc,0xb9,0x73,0x73,0x07,0xce,0xe5,0x26,0x8a,0x97,0xac,
+  0x0a,0x80,0x37,0x0a,0x50,0x10,0xfb,0x1f,0x1d,0x59,0x24,0xf9,0xbc,0x26,0xdf,0xfd,
+  0x7b,0xdb,0x2f,0x45,0x8d,0xa4,0xdf,0x6e,0x8b,0x29,0x6a,0x42,0x83,0x61,0x69,0x74,
+  0x33,0x52,0xe6,0xe3,0x84,0xb8,0x92,0xbe,0x5d,0x40,0x6e,0x76,0x2c,0x33,0xdc,0xd0,
+  0x75,0x3d,0xd2,0xd0,0x62,0x15,0xa2,0x03,0xe6,0xf3,0x95,0x95,0xd8,0xaa,0xb6,0xcd,
+  0x37,0xcf,0x97,0xa3,0xec,0x66,0xd3,0xba,0x93,0xf8,0x22,0xb4,0x2a,0xd4,0xd7,0xd7,
+  0x16,0x13,0x95,0xc9,0xf9,0xaa,0x07,0x7a,0xbf,0x55,0x77,0x6a,0xbc,0x99,0x36,0xfa,
+  0x22,0xdf,0xda,0x5a,0xd4,0x2e,0x0a,0x8a,0xc9,0x72,0x00,0x34,0x64,0x37,0xf3,0x93,
+  0x78,0xad,0x79,0x67,0xfd,0x79,0x67,0x3b,0x35,0xbf,0x3e,0x91,0xbe,0x94,0x46,0x1b,
+  0xc8,0xdd,0xc0,0xc1,0x12,0xee,0xe6,0xa9,0x97,0xe5,0x2b,0x24,0xf5,0xac,0xdc,0x14,
+  0x4b,0x42,0x0f,0x43,0xf5,0x65,0x54,0x57,0x98,0xd1,0x85,0xd6,0x15,0xd5,0x88,0xb4,
+  0x57,0x6b,0xf8,0x34,0xbc,0x6b,0xe0,0x51,0x31,0x79,0x45,0x9d,0x34,0x3b,0x15,0xdc,
+  0x07,0x5c,0xd8,0x29,0xdf,0xa1,0xd7,0xce,0xfd,0x15,0xea,0x73,0x86,0x5f,0x63,0x51,
+  0x50,0xde,0x7f,0x8a,0xe4,0xd5,0x78,0x52,0x47,0x39,0xff,0x52,0xbb,0x4b,0x35,0xf4,
+  0xb9,0xe1,0x01,0xcf,0x81,0x60,0xea,0xff,0x5e,0xf8,0xc0,0x11,0x7a,0x77,0x43,0xd3,
+  0xb4,0x5e,0xf0,0x92,0x83,0xbd,0x1a,0x03,0x5b,0x01,0x61,0xe2,0x01,0xd3,0xee,0xca,
+  0x61,0x37,0x0c,0x70,0xc8,0x76,0x00,0x6e,0xc5,0x35,0x00,0xac,0x00,0x4e,0xdc,0xf2,
+  0xff,0x4e,0x5d,0x2d,0x62,0xc4,0xfc,0x4f,0x4c,0xe4,0xce,0xfd,0xc1,0xdc,0x1f,0x1c,
+  0x98,0x3b,0x77,0x19,0x29,0x00,0x52,0x01,0x48,0xa7,0x07,0x99,0x06,0x20,0xe9,0x97,
+  0xcf,0xe7,0x9b,0xa2,0x46,0x42,0xd4,0x12,0xb3,0x23,0x64,0xc7,0x4f,0x18,0x65,0x71,
+  0x31,0x2c,0x65,0x4b,0x9d,0xce,0x42,0xc4,0x30,0x1b,0x99,0xc4,0x50,0xab,0xa6,0x45,
+  0x8c,0x91,0xe1,0xc4,0xfc,0x1c,0x2a,0x9a,0xbf,0x89,0xa3,0xf3,0xa8,0x84,0x71,0x0a,
+  0x60,0x91,0x3d,0x8b,0xf4,0x7a,0xa6,0x92,0x58,0x5d,0x93,0x0c,0x00,0x40,0x24,0x78,
+  0x2d,0x93,0xe9,0xb0,0x68,0x6e,0xc4,0x6b,0xb4,0x81,0xab,0x1b,0x95,0x95,0x84,0xc4,
+  0xcf,0xb0,0xd6,0xd7,0xd7,0x1b,0x85,0xc2,0x5a,0x46,0x5b,0xc0,0xad,0x92,0xe4,0x05,
+  0xb7,0x4f,0x66,0x32,0x5a,0x66,0x41,0x1b,0x36,0xa2,0x83,0x16,0xec,0x2c,0xe9,0x5d,
+  0x71,0x5a,0x94,0x19,0x9f,0x70,0x79,0x57,0xcf,0x5a,0x03,0x00,0xf0,0xe7,0x26,0x31,
+  0xb0,0x93,0x5e,0x6f,0x66,0x5e,0x01,0x98,0x7a,0xa3,0xa0,0x65,0x3a,0xab,0xdc,0x85,
+  0xe8,0x8c,0xa2,0x67,0xc6,0xe0,0x15,0x75,0xb7,0x8c,0x1d,0xaa,0x82,0xa0,0xaa,0x85,
+  0x56,0xca,0xe4,0x88,0xbc,0xeb,0x9f,0xb1,0x8b,0x91,0x3f,0x58,0x8e,0xba,0x22,0x46,
+  0x49,0x18,0x67,0xdb,0x59,0xd1,0xa3,0x24,0x92,0xce,0xcc,0xa7,0xa0,0x43,0x00,0xee,
+  0x3f,0xb6,0x23,0x9f,0xa7,0x23,0x98,0x0a,0x3f,0x5b,0x63,0xf0,0x16,0x75,0xfb,0x06,
+  0x86,0x3d,0xcf,0xc2,0xaa,0x67,0x38,0x83,0x02,0xbc,0x4a,0x62,0x00,0xcf,0x5b,0x35,
+  0x00,0xdc,0x15,0xf0,0x5f,0x5f,0xad,0x4e,0x80,0x6a,0x0e,0x99,0xff,0x4b,0xc5,0x6f,
+  0xe5,0xce,0x1d,0x98,0xab,0xce,0xcd,0xff,0x01,0x52,0x00,0x56,0x04,0xb0,0xeb,0xb5,
+  0x00,0x04,0x69,0xff,0xeb,0x46,0x56,0x97,0x5f,0xec,0x2c,0x89,0x21,0x2a,0xdf,0x14,
+  0x95,0x11,0x9f,0x6c,0x11,0x3e,0x5b,0x2c,0x5d,0xd8,0x69,0x0b,0x42,0x8a,0x2b,0xff,
+  0x4b,0xda,0x9a,0x6e,0xb4,0x2b,0x29,0x4b,0xc1,0x94,0xd2,0xc5,0x58,0xc4,0x68,0x27,
+  0x88,0x0b,0xb0,0x8c,0x3c,0x00,0x21,0x3a,0x67,0xb0,0x15,0xd6,0x78,0xbb,0x80,0x83,
+  0xea,0xeb,0x62,0x16,0x9f,0x19,0x89,0xe8,0xe2,0x43,0x8f,0x0c,0x3b,0x7e,0xfb,0xf2,
+  0x4e,0x0d,0xef,0x05,0xf9,0x19,0x9d,0xc2,0xb6,0xce,0x28,0x00,0xb3,0xbd,0xdd,0x6e,
+  0x37,0xda,0x3d,0xc9,0xf8,0xb4,0xda,0xfb,0x83,0xeb,0xe8,0xb5,0xb5,0x99,0xfa,0x26,
+  0x77,0xa4,0xcd,0x79,0xf9,0xf2,0xe9,0x06,0x31,0xc5,0x62,0xdb,0x46,0x59,0xbc,0x1b,
+  0x73,0xa6,0x4f,0x5b,0xe1,0xa6,0x7d,0xda,0xcc,0x35,0x70,0x5f,0xf4,0x06,0x5f,0xff,
+  0x8f,0xfb,0x65,0x12,0x9b,0x5c,0xec,0xb5,0xa2,0xae,0x2d,0x49,0x7a,0xfe,0x6f,0xaa,
+  0x03,0x37,0x8c,0xf2,0x1c,0x77,0x7d,0x71,0xa6,0x99,0xdf,0x92,0xae,0x59,0xef,0x17,
+  0xde,0x51,0xa7,0xcd,0xb7,0x27,0xd3,0x54,0x58,0x8f,0x1a,0xe9,0xcb,0xab,0x1f,0xf4,
+  0x88,0x29,0x7a,0xdb,0xb4,0x1b,0x09,0x29,0xef,0xc0,0x79,0x75,0xf4,0x02,0xdd,0x5a,
+  0x68,0x57,0x01,0xc2,0x76,0x2b,0xa0,0xd5,0x08,0x78,0xff,0x95,0x5b,0xfe,0x6b,0x79,
+  0xea,0xea,0x10,0x49,0xe1,0xe0,0xdf,0x85,0xcb,0xe7,0xe6,0x48,0x45,0x15,0xd5,0x00,
+  0x90,0x03,0x80,0xe5,0xff,0xab,0x48,0xfe,0x9f,0x8e,0x3f,0x6b,0xb7,0x00,0xf4,0xcd,
+  0x02,0x4a,0x37,0x16,0x96,0xb1,0x35,0x15,0xa4,0x49,0x52,0xe2,0x08,0x55,0xbf,0x6c,
+  0x51,0xbe,0xc1,0x30,0xa7,0x36,0xf8,0x71,0x22,0x9a,0xb8,0x95,0xad,0x31,0xdc,0x30,
+  0x1a,0x55,0x66,0xeb,0xdd,0x8a,0x6e,0x66,0xe6,0x2d,0xd1,0xac,0x2d,0x2c,0xa1,0xca,
+  0x39,0xb3,0xf1,0x02,0xe3,0x8a,0x90,0x21,0x0b,0x48,0x06,0x02,0x77,0x00,0xc6,0x04,
+  0xd2,0x7c,0xe8,0x41,0x5e,0xe2,0xee,0x5b,0xf4,0x74,0x56,0x8d,0x67,0x8c,0x98,0xad,
+  0x00,0x78,0x3f,0x43,0x2f,0x92,0x5a,0x13,0x7a,0x3e,0x5b,0xb2,0x66,0x52,0x7d,0xd6,
+  0xfe,0xc3,0xba,0x14,0xbd,0x21,0x53,0x2b,0x0e,0x4a,0x02,0x39,0x4b,0x8b,0x92,0xec,
+  0x6a,0xbf,0xae,0x84,0x38,0xbb,0x72,0xab,0x53,0x28,0x0b,0x77,0x43,0x92,0x30,0x94,
+  0xf3,0xcb,0xdc,0xc8,0x74,0x85,0xeb,0x40,0x7f,0x14,0xfc,0xba,0x78,0x43,0x5b,0x3e,
+  0x4b,0xb2,0x14,0x7a,0xb7,0x52,0xc6,0x0b,0xe6,0x9a,0x98,0x76,0x89,0xcc,0xbf,0x3b,
+  0xc0,0xc2,0xae,0xf9,0xbd,0x57,0xc3,0xb6,0x3d,0x75,0x24,0x8c,0x1e,0xe3,0x87,0xb3,
+  0xf1,0x54,0x37,0x3f,0xd7,0x25,0x77,0x8c,0xbb,0xe7,0x07,0x84,0xa9,0x35,0xb9,0xfa,
+  0x01,0x9b,0x3e,0x4c,0x8b,0x34,0x93,0x36,0xec,0xec,0x8d,0x5e,0x38,0xcc,0x6e,0xdc,
+  0x0d,0x5b,0xb8,0xad,0x00,0x56,0x08,0xe0,0x79,0x52,0x03,0x40,0xf2,0x7f,0xcb,0x3b,
+  0xa6,0xae,0x0e,0x8b,0x24,0xf8,0x3f,0x81,0xac,0x3f,0xaa,0x38,0xe3,0x68,0xd5,0xb9,
+  0xdc,0xe5,0x22,0x15,0x00,0x78,0x36,0xa0,0xff,0x9f,0x1e,0xc6,0x37,0x5f,0x32,0x00,
+  0x88,0xef,0x00,0x60,0x23,0x2f,0x92,0x26,0x2a,0xc1,0xfe,0xf3,0x6e,0xfa,0xf0,0x4e,
+  0x41,0xe8,0xa4,0x8b,0x43,0xf4,0xa8,0xc4,0xd6,0x84,0x40,0x7a,0x32,0x8b,0x3c,0x82,
+  0x2a,0x89,0xce,0x65,0x49,0xfb,0x3c,0xbd,0x16,0xdb,0xb4,0x50,0xd2,0x48,0x50,0x5d,
+  0xd2,0x49,0xb6,0x7f,0x10,0x7a,0x6c,0xcd,0x6c,0xa1,0xbd,0x4c,0x56,0x12,0xb5,0xcc,
+  0xd2,0x69,0x46,0x01,0x2c,0x0d,0x6c,0xdc,0x03,0x50,0x31,0xed,0xca,0x12,0x7f,0xfb,
+  0xfc,0xb2,0xab,0xda,0x99,0xe5,0x18,0xf1,0xc6,0xfa,0x27,0x0c,0x14,0x0d,0x27,0x73,
+  0xa3,0x6f,0xb3,0x7d,0x6f,0x4a,0x6d,0x67,0x0c,0x18,0xfe,0x82,0xb2,0x99,0x02,0x29,
+  0xa3,0x81,0x73,0xa7,0x79,0xf7,0x7f,0xd3,0xf0,0xcb,0x66,0x18,0xe0,0x10,0xee,0xa6,
+  0x42,0x7b,0xae,0x7d,0xa5,0x05,0xd3,0x91,0x5d,0xaa,0xf6,0x4f,0xa5,0xe6,0xb9,0x4b,
+  0x52,0x95,0x7f,0x26,0x83,0x80,0xef,0xc6,0xe3,0x56,0xfe,0x3d,0xbf,0x83,0x0b,0x39,
+  0xd0,0x6e,0x3f,0x0d,0xb5,0x6d,0x4a,0x45,0xb9,0x11,0x00,0x1c,0x02,0xb8,0xf5,0x94,
+  0xdd,0x06,0xf0,0xc8,0x2d,0xb7,0xfc,0xc5,0xd5,0xa9,0x00,0xa8,0xd5,0x64,0x34,0x74,
+  0xe9,0x42,0x0e,0x99,0xff,0x49,0xdc,0xb2,0x33,0x89,0x14,0xc0,0xe5,0x62,0x31,0x95,
+  0x22,0x01,0x80,0xa7,0xbd,0x0a,0x40,0x3f,0x1d,0x10,0x2f,0x14,0x86,0xc8,0xcd,0xe7,
+  0xef,0xab,0x5f,0x8a,0xda,0x84,0x19,0x4b,0x64,0x65,0x29,0xaa,0x5c,0x83,0xe1,0x39,
+  0x63,0x5b,0x2c,0x52,0xc8,0xfc,0xaf,0x1b,0xe6,0xa4,0xe4,0x90,0xe2,0x55,0xbd,0x51,
+  0xa9,0x4e,0x56,0x49,0xfb,0x7c,0x84,0x0b,0x98,0x33,0x0e,0x00,0x1e,0x00,0x8c,0x0c,
+  0x59,0xc2,0x87,0xab,0xe5,0xe3,0x55,0xb0,0x24,0x67,0xf4,0x65,0x54,0xd3,0xc0,0x6d,
+  0x0d,0x0b,0x05,0xdc,0x0a,0xe8,0x6d,0x43,0xdb,0x5b,0x0c,0x5b,0x4a,0xd5,0x4c,0x6c,
+  0x2d,0xca,0x82,0x25,0x92,0xae,0x35,0x98,0x92,0x35,0x1c,0xa3,0xe8,0xff,0x4b,0x42,
+  0x0f,0x21,0xd3,0x6e,0xb6,0xe7,0x97,0x2d,0x0c,0x2a,0xff,0xc3,0x6d,0xf9,0x18,0x50,
+  0x9c,0x42,0x6d,0x59,0xee,0x3f,0xbf,0x90,0x31,0xb0,0xc2,0x91,0x70,0x8b,0x5b,0xa7,
+  0xa6,0x4d,0x2b,0x5b,0x03,0xe7,0x84,0xd7,0x5d,0x4a,0xd0,0x13,0xb4,0x1d,0xf7,0xec,
+  0x79,0xd8,0xa9,0xbf,0xd3,0xed,0x89,0x5e,0xd7,0xa0,0xd9,0x30,0xbb,0x19,0x37,0x13,
+  0x91,0x8f,0x28,0x7a,0x2d,0x09,0x4e,0xd5,0xc4,0xa9,0x03,0x84,0x9d,0x46,0x40,0xec,
+  0x00,0x3c,0x7c,0x3b,0x09,0x01,0x7e,0xe1,0x3d,0x53,0x57,0x03,0xfd,0x0c,0x31,0xff,
+  0xb9,0x03,0x48,0xfc,0x2b,0x95,0x47,0x91,0x02,0xa8,0x1e,0x38,0x77,0xc1,0x75,0x00,
+  0xdc,0x51,0x80,0xfa,0x0e,0x03,0x54,0x2a,0x38,0x4d,0xd4,0xdc,0x1e,0xfc,0xfa,0x73,
+  0x17,0x47,0x16,0xb7,0x16,0x65,0x7d,0xc0,0xd8,0x52,0x10,0xd7,0x4c,0x4d,0xb0,0x4d,
+  0x4d,0x75,0xa7,0x6c,0xd4,0x7d,0xc4,0x74,0x22,0x82,0x14,0x40,0x35,0x8f,0x8a,0xe2,
+  0xc2,0x36,0x37,0xaa,0xd5,0x26,0x53,0x65,0xed,0xa0,0x4a,0xf5,0x22,0xaa,0x54,0x07,
+  0xe8,0x24,0x2f,0x92,0x8a,0x44,0x2a,0x44,0x01,0x20,0x25,0x66,0x45,0x1a,0xdc,0x69,
+  0x48,0x46,0xf7,0x7f,0x12,0xa2,0x39,0xb3,0x16,0x43,0x55,0x95,0x91,0x4d,0xfe,0xfe,
+  0xf9,0x0d,0x00,0x56,0x68,0x9f,0xcd,0x2e,0x48,0x46,0x57,0x52,0x25,0x03,0x80,0x19,
+  0x31,0x9f,0xce,0xc5,0x83,0xca,0xbf,0x66,0xb7,0x52,0xf6,0x1e,0x00,0x10,0xe7,0xfe,
+  0x8a,0xb7,0x1d,0x47,0xff,0x06,0x1e,0x17,0x4d,0xe4,0x38,0x95,0x02,0x18,0x76,0x83,
+  0x6b,0x6c,0xb8,0x9e,0xd2,0x04,0x9c,0x00,0xb3,0xce,0x00,0x15,0xd6,0x63,0x84,0x9c,
+  0x92,0x69,0x5a,0x45,0x78,0x9e,0xbe,0x53,0x05,0xa1,0x0e,0x40,0xba,0x2a,0xdd,0xdf,
+  0xc0,0x89,0x0b,0x38,0x31,0x00,0xa7,0x11,0xf0,0x79,0xd2,0x06,0x88,0x6a,0x00,0x3f,
+  0xc1,0xdf,0xfa,0x7d,0x21,0x83,0xdc,0xff,0x4b,0xa8,0xf6,0x8f,0x3c,0xe6,0x47,0x97,
+  0x5b,0xcb,0xcb,0xf9,0xdf,0xad,0xce,0xe5,0xac,0x00,0x40,0xd7,0x6b,0x01,0x0c,0x50,
+  0x05,0xb0,0xbc,0x69,0xed,0xb4,0x38,0xe4,0x9c,0x5f,0x8a,0x9a,0x99,0x59,0x44,0xbe,
+  0xb3,0xd8,0x45,0x9d,0x35,0x3b,0x21,0x73,0x5b,0x0c,0x12,0x34,0x0d,0xd3,0x30,0x7c,
+  0x4b,0x4b,0x11,0x2b,0x00,0x54,0x03,0xa8,0xad,0x2e,0x45,0xb8,0xcd,0x33,0xc9,0x88,
+  0x24,0xf1,0x4d,0x13,0x07,0xc9,0x08,0x36,0x3e,0x5f,0x71,0xa4,0x9d,0xc7,0x75,0xa6,
+  0xe5,0xc4,0x62,0xa6,0xbd,0x4e,0xb7,0x02,0xaa,0x89,0x7d,0x9f,0x31,0x65,0xc2,0xe8,
+  0x2c,0x2e,0x2c,0x89,0xce,0x95,0xef,0x00,0x60,0x99,0x46,0xb6,0x43,0xc6,0xd7,0x09,
+  0x30,0x00,0x98,0x91,0x45,0x75,0x85,0x76,0x79,0x87,0x6f,0xb9,0x8d,0x0c,0xaa,0xc7,
+  0xb0,0x43,0x25,0x1b,0x03,0x8a,0x55,0xa8,0x45,0x6b,0xdc,0x5f,0xc1,0xfd,0x57,0xcd,
+  0x7d,0xa8,0x39,0xbd,0xff,0x90,0x63,0xcc,0xa9,0x9a,0xbd,0xd0,0x61,0x37,0xcc,0xfa,
+  0xe2,0xb3,0xac,0x00,0x3b,0x99,0x3a,0x5e,0xfa,0x00,0xdb,0x06,0x40,0x47,0xec,0x3d,
+  0x15,0xc1,0xb4,0xfe,0xb3,0x29,0x82,0xb4,0xef,0xc0,0x19,0x7c,0xca,0x25,0xf1,0xf4,
+  0x92,0x5b,0x05,0xb0,0xf3,0x80,0x89,0x02,0x78,0xdb,0x55,0xa9,0x00,0x54,0x3e,0x9b,
+  0x3a,0x83,0xcc,0xff,0xdc,0x7c,0xbe,0xd2,0xc2,0x2c,0xe7,0x49,0x05,0x20,0x74,0xc6,
+  0x6a,0x01,0xa4,0x73,0x80,0x7b,0x87,0x00,0x49,0x1a,0x79,0x76,0xed,0xb4,0x38,0x00,
+  0x90,0xef,0x00,0x60,0xc3,0x0b,0x6b,0x8d,0xb2,0x50,0x10,0xb8,0x06,0xc3,0x84,0xa1,
+  0x89,0xe3,0x58,0xe0,0x7e,0xe8,0x3d,0x84,0x2c,0x67,0x6a,0x93,0xd5,0xc9,0x65,0x49,
+  0xc4,0x8c,0x69,0x79,0x5f,0x41,0xf2,0x8f,0x7c,0x84,0x91,0x40,0xe3,0xd5,0x88,0x1c,
+  0x30,0x0b,0x93,0x24,0xd2,0xb0,0x85,0xf3,0x80,0xe8,0x42,0xbf,0x59,0xd9,0x6f,0x05,
+  0x50,0x34,0xd7,0x16,0x0a,0x0d,0xb1,0x0b,0x84,0x9f,0xcb,0x5c,0xea,0xe8,0xb8,0x1b,
+  0x84,0x24,0xa7,0x47,0x32,0x00,0x98,0xbe,0x58,0xb1,0x06,0x00,0xe4,0x96,0x1d,0x38,
+  0x19,0x27,0x8b,0x1d,0x2a,0x6d,0x46,0xa8,0x50,0xb1,0xad,0x94,0x59,0x63,0xa9,0x51,
+  0x17,0x14,0x53,0xd3,0xf0,0xcb,0x14,0x1f,0x88,0xd2,0xdd,0x94,0x24,0x7b,0xb5,0x6e,
+  0xb7,0xd3,0xbd,0x2b,0x6e,0xb4,0x81,0xa7,0x84,0x9a,0xaa,0xb8,0xbb,0xf5,0xff,0xf0,
+  0xb4,0xe7,0xed,0xf3,0xb6,0xde,0x4d,0xfa,0xa7,0x25,0x9e,0xdb,0x03,0x25,0xfb,0xd4,
+  0x00,0xc4,0xb4,0x42,0xb0,0xfe,0x8d,0xbb,0x9d,0x8f,0x5d,0xf9,0x77,0x42,0x80,0x48,
+  0xfe,0xff,0xf4,0x6a,0x8c,0x02,0xa2,0xce,0x25,0x91,0xfb,0x7f,0xf9,0xdc,0xdc,0x64,
+  0x7e,0xb9,0x95,0xb8,0x27,0x41,0x14,0xc0,0x81,0x8f,0x5f,0xb8,0x74,0xe6,0x29,0xd7,
+  0x01,0x08,0x38,0x0a,0x18,0xbe,0xf9,0x32,0x6b,0xda,0xf4,0x1b,0x00,0xcc,0x8c,0x2c,
+  0x35,0x22,0x75,0x71,0xe2,0x09,0xa6,0xd8,0xa5,0x1b,0x11,0xdc,0x44,0xcf,0x29,0x09,
+  0x24,0xfe,0xc3,0x3d,0x8c,0x45,0xa9,0x62,0x64,0x71,0x7e,0x0e,0xee,0xa2,0xc7,0x35,
+  0x46,0xd1,0xa2,0x3d,0x54,0x1e,0xc2,0x03,0x80,0xd5,0x37,0xf9,0x6e,0x68,0x3e,0xb3,
+  0x6a,0xf0,0xe4,0x8d,0x0c,0x49,0x37,0x5a,0x41,0x0a,0x60,0x9b,0x49,0x03,0x90,0x75,
+  0x37,0xdc,0x13,0x21,0xa3,0xd1,0x3e,0x5d,0xde,0x11,0xbb,0x2a,0xfa,0x75,0x25,0xce,
+  0x9a,0xed,0xed,0x88,0x28,0x65,0xb2,0xba,0x4d,0xd7,0xce,0xdc,0x10,0xdb,0x0a,0x07,
+  0x4d,0x53,0xb6,0x32,0x89,0x67,0x46,0x7a,0x3a,0x54,0x63,0x11,0x13,0x1f,0x99,0xd8,
+  0x93,0x7b,0xf0,0x69,0x11,0x64,0x1c,0xb5,0xbd,0xed,0xf0,0x74,0xd8,0x0b,0xcb,0xd1,
+  0x32,0xee,0x39,0xec,0xb3,0x9e,0x91,0x0f,0x3b,0x2d,0x03,0x5e,0x98,0x8f,0x91,0x65,
+  0x57,0xd8,0x3d,0xe3,0x1e,0xe6,0x1e,0x8e,0x47,0xc0,0x37,0x0e,0x3a,0xb5,0x00,0x6f,
+  0xa0,0xd1,0xe9,0x69,0x7b,0xba,0xc2,0x69,0xae,0x27,0x90,0xab,0x13,0x58,0x05,0x70,
+  0xec,0xd8,0x51,0xe4,0x00,0x1c,0xad,0xf3,0xf7,0x7e,0x1f,0x50,0x27,0x90,0xfb,0x5f,
+  0x44,0xb5,0x7f,0x24,0xfe,0xf7,0x24,0xb6,0xb6,0x48,0x2e,0xfd,0xdc,0x39,0xa7,0x02,
+  0xd0,0xb5,0x5b,0x00,0x82,0x54,0x00,0xf0,0x00,0x60,0x48,0xf9,0xd3,0x35,0x61,0x6b,
+  0x17,0x3e,0xb5,0xe9,0xa4,0x6e,0xba,0x3d,0xf5,0x19,0xca,0xb4,0x64,0x17,0x0d,0x8d,
+  0x8c,0x7b,0xc3,0x17,0x16,0xa3,0x67,0x61,0x49,0x6b,0x7a,0x6b,0x7e,0x72,0xf9,0xac,
+  0x38,0xac,0x05,0x1d,0x01,0x9c,0x1c,0xf1,0x69,0xf8,0x0e,0x38,0x3e,0x5f,0xa9,0x65,
+  0x74,0x70,0xb6,0x41,0x7e,0xe5,0xc5,0x55,0xa4,0x00,0x68,0xe9,0x34,0xf7,0x96,0xc7,
+  0x2e,0x90,0x32,0x74,0x5d,0x7f,0x5c,0x32,0x52,0x91,0x5f,0x76,0x55,0x4d,0x8d,0xc8,
+  0xa7,0x28,0x12,0x35,0x53,0xda,0x19,0x89,0x49,0x98,0xba,0x61,0xd0,0x34,0xe5,0xa1,
+  0xfa,0xb2,0x74,0x0c,0x28,0x46,0xa1,0xe6,0x54,0x5d,0xa6,0x98,0xd4,0xbd,0xe6,0xfe,
+  0xda,0x1c,0x0e,0x87,0x69,0x59,0x62,0xec,0xb4,0x13,0x12,0x70,0x84,0x98,0x6a,0xe7,
+  0x77,0x17,0x67,0xf2,0x71,0xbc,0x66,0x7f,0xb7,0x0a,0x4f,0x8d,0x29,0x3c,0x2d,0x67,
+  0x76,0x9a,0x56,0x26,0xdc,0x0f,0xde,0xd7,0x54,0x2f,0xa5,0xf0,0x38,0xbd,0x80,0xf5,
+  0x95,0xa7,0x00,0x9e,0x27,0x4d,0x00,0xf7,0xff,0xd2,0xf7,0x09,0xf7,0x72,0xef,0xec,
+  0x14,0xa3,0x67,0x2e,0x5d,0xc8,0xcd,0xfd,0x6e,0xbe,0xb5,0xb2,0xb5,0x15,0x8b,0x9d,
+  0x45,0x0a,0x60,0x12,0x55,0x00,0x2e,0x84,0xbc,0x51,0xc0,0xa8,0x08,0x40,0xaf,0x2a,
+  0x40,0x2b,0x82,0x07,0x00,0x9b,0x11,0x87,0x9c,0xf1,0xa9,0x4d,0x77,0x23,0x9b,0x78,
+  0xb0,0x2e,0x71,0x34,0x6f,0xa6,0x89,0x3a,0xb1,0xb3,0xda,0x59,0xd2,0xb9,0x34,0x36,
+  0x54,0x50,0x85,0xde,0x3c,0x2c,0xa1,0x11,0x6d,0x72,0x3e,0x9f,0x58,0x5c,0x38,0xcd,
+  0x59,0x1a,0x7a,0x74,0x11,0x77,0x00,0xb0,0x7e,0x19,0x08,0x7e,0xc4,0xb3,0xc8,0xcf,
+  0x20,0x69,0x00,0x5b,0x9d,0xb5,0x19,0xa6,0x15,0xb0,0x7c,0x26,0xe0,0x36,0x82,0x11,
+  0x35,0x0d,0xac,0x2a,0x45,0xf9,0xf7,0x13,0x9a,0x98,0x4a,0x46,0x42,0x13,0xeb,0x8c,
+  0xfe,0x03,0x80,0x3d,0xce,0x4b,0xed,0xc0,0xcd,0x71,0x76,0x4a,0x97,0xd8,0x4a,0x49,
+  0x4f,0x53,0x92,0x51,0x91,0x62,0x12,0x0a,0x49,0x73,0x17,0xa3,0x22,0x4a,0x39,0x19,
+  0xa6,0x0c,0xbe,0x37,0x92,0x0f,0x1d,0x82,0xe3,0xad,0xba,0x23,0xf0,0xd3,0xde,0x4a,
+  0xf4,0x42,0xae,0xdf,0xee,0x55,0x0a,0xc2,0xec,0x47,0xda,0x03,0x60,0xaa,0x15,0x4c,
+  0x2e,0x11,0xbd,0xc2,0xac,0xb7,0x51,0xc4,0x78,0x98,0x96,0xfd,0xf0,0x34,0x1d,0x01,
+  0x38,0xe5,0x46,0x00,0xae,0xc6,0x5c,0xc0,0x7a,0x0a,0x57,0xff,0xcf,0xe1,0x76,0xac,
+  0xb3,0x5b,0xb5,0x5a,0x2d,0xb6,0x95,0x40,0x15,0x80,0x73,0xb9,0x0b,0x5e,0x04,0x10,
+  0xe7,0x00,0x05,0xe9,0x06,0x98,0xb7,0x86,0xd3,0x0c,0x32,0xe4,0x1c,0x21,0xdd,0x50,
+  0x65,0x05,0x9a,0x35,0x3b,0xf1,0xe1,0x48,0x56,0xb4,0xd0,0x4d,0xd5,0xe8,0x67,0x5f,
+  0x13,0x46,0x02,0x57,0x00,0xc4,0x2e,0xb0,0x94,0x36,0x22,0x89,0x2f,0xd2,0x4e,0xb2,
+  0xc1,0x8a,0x1a,0xce,0x03,0x32,0x13,0xf3,0x56,0xb6,0xd1,0xea,0xda,0x4c,0xdd,0xa4,
+  0x86,0x1d,0x6a,0x44,0x83,0x6e,0x24,0x08,0x49,0xdd,0xe7,0x62,0xf9,0x4d,0xaf,0xd8,
+  0x9a,0xda,0x54,0xc5,0xe9,0x02,0xa7,0xa4,0x03,0x80,0x35,0x48,0x1e,0x14,0x92,0xff,
+  0xde,0xcd,0xf6,0xfd,0xc1,0x03,0x80,0xf5,0x4b,0xe9,0x4a,0x9a,0x9b,0xa8,0x36,0x27,
+  0x1b,0x37,0x69,0xaf,0xb9,0xbf,0x16,0x9f,0x38,0xe4,0xb5,0xaf,0x31,0x42,0xee,0xd5,
+  0xed,0xd9,0x66,0x01,0xce,0x63,0x67,0xeb,0xeb,0x7c,0xa2,0x0e,0x15,0x13,0x70,0x27,
+  0xff,0xa5,0xe4,0xdd,0xfd,0xc8,0xbc,0x9d,0xa6,0xdd,0x0b,0x6f,0x93,0xd3,0x9c,0x0b,
+  0x41,0x1d,0x2f,0x56,0x10,0xb3,0x96,0x02,0xb8,0x13,0x55,0x00,0x9e,0x27,0xf2,0x7f,
+  0x35,0x1a,0x00,0x1a,0xa9,0x54,0xe8,0xc2,0xe5,0x39,0x24,0x2a,0x89,0x58,0x6d,0x31,
+  0xbb,0x58,0x8b,0x9d,0x5d,0xa9,0xcc,0x57,0xad,0x16,0x80,0xcf,0x92,0x08,0xe0,0xd3,
+  0x5e,0x0d,0xa0,0x67,0x25,0x60,0xd2,0x6f,0x52,0x2c,0xbf,0x01,0xc0,0x1a,0x3e,0x13,
+  0x79,0xd0,0x66,0x27,0xaa,0xaf,0x49,0x2c,0xb4,0x3a,0xa5,0xf5,0x0b,0x4d,0x47,0x23,
+  0xc3,0x93,0x79,0xd2,0x1b,0x8d,0xab,0xd6,0x52,0x01,0x73,0x6b,0x18,0x7f,0xc9,0x00,
+  0x60,0xc1,0xdb,0xa1,0xbb,0x05,0x92,0x07,0x94,0x47,0x0a,0x20,0xc3,0x45,0xb5,0x0a,
+  0xfb,0x99,0x07,0x34,0xa6,0xfb,0x4c,0x7b,0x52,0xf6,0xd9,0x4b,0x5e,0xf5,0x59,0x41,
+  0x36,0x00,0x58,0x01,0xd5,0xdc,0x64,0xcd,0xf6,0x83,0x4a,0xe4,0x01,0xc3,0x9e,0xa6,
+  0x8c,0x6f,0x49,0xa0,0x06,0x00,0xab,0xe2,0x3c,0x5f,0xc9,0xe8,0xea,0xcd,0x81,0x07,
+  0x45,0x91,0xf3,0xca,0x43,0x61,0x46,0x6c,0x5d,0x0f,0x80,0xd1,0x00,0x4c,0x3c,0xc0,
+  0x8b,0xdf,0xd1,0x06,0xdc,0x5e,0xdd,0xf3,0x07,0x66,0x29,0xcd,0xe1,0xba,0xee,0x8e,
+  0xe0,0xd2,0x3b,0x65,0xf5,0x85,0xf5,0xbd,0x1b,0xef,0xf7,0x76,0x49,0x8d,0x1a,0x12,
+  0xa6,0xbe,0x76,0xf6,0x1a,0xde,0x38,0x64,0x3b,0x00,0x77,0x3f,0x7c,0x0c,0x29,0x80,
+  0xa3,0x5f,0x94,0xdd,0xce,0x3d,0x52,0x88,0x22,0xf9,0xcf,0x1d,0x98,0xac,0xac,0x9c,
+  0xad,0x65,0x17,0x47,0x17,0xb3,0xb5,0xd8,0x0a,0x76,0x00,0x70,0x05,0xc0,0x1b,0x05,
+  0x2c,0x5e,0x0a,0x30,0x17,0xd0,0x9c,0x89,0x87,0xd3,0x93,0xd4,0xa6,0x63,0xf2,0x15,
+  0xd2,0x6d,0x9f,0x63,0xa2,0xc7,0xb4,0x98,0x30,0x3a,0xd9,0x85,0x99,0x3a,0x9b,0xc5,
+  0xd3,0x6c,0x06,0x68,0x29,0x8e,0x99,0xad,0xbc,0xed,0xd6,0x32,0x07,0x44,0x39,0xcc,
+  0x21,0xd3,0x19,0xb2,0x84,0x3b,0x82,0x01,0xf2,0x50,0xa2,0x8d,0xf2,0x10,0x4e,0x04,
+  0x5c,0xc6,0x89,0x80,0xeb,0x4c,0x7b,0x5b,0x66,0xd7,0xf5,0xd9,0x92,0x30,0xe4,0x72,
+  0x37,0xe2,0x73,0xb1,0x48,0x83,0x86,0x70,0xb8,0x25,0x65,0xd2,0xef,0x8e,0x8b,0x09,
+  0x43,0x78,0x00,0xb0,0x04,0x19,0x00,0x28,0x78,0x1e,0xa4,0x3c,0x1c,0x3c,0x61,0x8d,
+  0x3a,0xd0,0x6b,0xd4,0x91,0x78,0xa1,0x29,0x93,0xfe,0xa9,0xa9,0xbd,0xe7,0xfe,0x5a,
+  0x3c,0xf8,0x11,0xaf,0x1a,0xcf,0x39,0xfc,0xd4,0xac,0xdc,0xb3,0x6e,0xf5,0xde,0x4b,
+  0xf3,0xb3,0xeb,0xf4,0xae,0xb0,0xd3,0xb2,0xee,0x05,0x10,0xc3,0x5e,0x1d,0x21,0xec,
+  0xfd,0xa3,0x5e,0xc3,0xae,0xc0,0xdb,0xff,0xe8,0x74,0xe3,0x69,0x4e,0x4d,0xb8,0xbd,
+  0x01,0x3c,0x0d,0xe0,0x84,0x2d,0xa9,0x8e,0x80,0x77,0x93,0x0a,0xc0,0xd5,0x18,0x03,
+  0x24,0x13,0x4d,0x5d,0x9a,0xc8,0xe1,0xb6,0xb2,0x58,0x76,0xb1,0x73,0x5f,0xa7,0x93,
+  0x8d,0x6d,0xb5,0x2a,0xf3,0x07,0xce,0x5d,0xb8,0x64,0x0d,0x02,0xf0,0x4c,0x9a,0x0e,
+  0x01,0xf6,0x72,0x00,0x7c,0xbd,0x69,0x3d,0x93,0xc9,0xac,0xb2,0x4f,0xf2,0xe7,0x37,
+  0xef,0x16,0x5d,0xec,0x5a,0x66,0xad,0xb6,0x26,0xd6,0x29,0xea,0xfd,0x23,0x53,0x29,
+  0x33,0x33,0x69,0x17,0x6b,0xa6,0xb8,0x51,0xe9,0x48,0x21,0x77,0x54,0xfd,0x41,0xa6,
+  0x20,0xe3,0xf7,0x13,0x59,0xcf,0xdb,0xf9,0xc6,0x19,0x76,0x38,0x90,0x66,0x6d,0x37,
+  0x16,0x2d,0xde,0xc2,0xfd,0x0e,0x33,0x9d,0xd5,0x4c,0x07,0x5d,0x25,0xf7,0x8a,0xc9,
+  0x5c,0x79,0xb2,0x93,0x42,0x86,0x5e,0xcc,0x79,0x76,0x1a,0x7e,0x77,0x7c,0x51,0x54,
+  0x16,0x99,0xed,0xe5,0xc4,0xa2,0xa4,0x73,0xf1,0x54,0x5b,0xd8,0xae,0xf3,0xc4,0xc7,
+  0xd6,0xc9,0xf2,0x0a,0xae,0x88,0x14,0xaa,0x74,0x0c,0x38,0x4f,0xa1,0x46,0x7d,0xef,
+  0xfa,0x2e,0xa7,0xfd,0x10,0xce,0xe6,0x61,0xc7,0xce,0xba,0x63,0x77,0xd3,0x75,0xfb,
+  0x69,0xf6,0x9d,0xf7,0xc9,0x79,0x15,0xcd,0x31,0x63,0xcc,0xa9,0x6f,0x19,0xa8,0x6e,
+  0x3d,0xb3,0xdc,0x97,0xcc,0x9b,0x30,0x6d,0xfa,0x85,0xd5,0x99,0xe6,0xc2,0x0d,0x3c,
+  0x33,0xa8,0xe5,0x00,0xe0,0x0a,0xc0,0xd1,0xff,0x70,0x15,0x12,0x00,0x6a,0xd1,0x33,
+  0xa1,0xcb,0xe7,0x90,0xfb,0x7f,0xb6,0xb6,0xd8,0x59,0x45,0xf7,0x74,0x31,0xbb,0xb5,
+  0x52,0x99,0xac,0x9e,0x9b,0xb8,0x60,0xa5,0x00,0x5a,0x5d,0x40,0x6c,0x07,0xa0,0x67,
+  0x00,0xb0,0x48,0xac,0xe9,0xc5,0xb2,0xe0,0xfc,0x0d,0x0a,0xd5,0x0e,0x54,0xca,0x44,
+  0x70,0xdb,0x1a,0x3f,0xec,0x45,0x33,0x80,0x81,0x2e,0x69,0x91,0x4a,0x85,0x24,0x24,
+  0xb1,0xa5,0x91,0x1a,0x5e,0xc4,0x1e,0xc6,0x5f,0x9c,0x55,0xc7,0x6f,0xc8,0x02,0x29,
+  0x13,0x23,0x6d,0x27,0x0d,0x60,0x81,0xcd,0x03,0x6a,0xb6,0x76,0xd1,0xa0,0x9d,0x34,
+  0xf5,0xf5,0xb2,0x69,0xe0,0x1a,0xcf,0x55,0x49,0xf8,0x90,0xc4,0x36,0xb2,0x78,0xde,
+  0x2e,0x6d,0x46,0x1c,0x8f,0xa7,0x0f,0x42,0xfd,0x80,0x64,0x12,0xcb,0x14,0x6a,0x63,
+  0xa2,0x58,0x2c,0x5e,0x42,0x8f,0x62,0xcd,0x6f,0x63,0xfb,0x90,0xfb,0x6b,0x41,0x77,
+  0x01,0xf6,0x9c,0x00,0xd7,0x96,0x7b,0xf5,0x7a,0xaa,0x7d,0x9e,0xf6,0xea,0xc3,0x8e,
+  0x20,0x52,0x4b,0xcc,0x3a,0xff,0x68,0x39,0x67,0x5e,0x7d,0x34,0x00,0x2f,0xe1,0xec,
+  0x17,0xcc,0xc2,0x4c,0x8a,0x91,0xd5,0x02,0x40,0x6a,0x00,0xa7,0x4e,0x9d,0x42,0xf2,
+  0x7f,0xec,0xd8,0xd1,0xab,0xd1,0x03,0xa0,0x15,0x3d,0x53,0xfc,0x16,0xaa,0xfe,0x63,
+  0xf3,0xbf,0x9a,0x59,0x58,0x5d,0xbd,0x2f,0x5b,0x3b,0xbb,0x8c,0x1c,0x80,0xcb,0x4e,
+  0x0a,0xc0,0x33,0x6e,0x0d,0x40,0xa1,0xda,0x00,0x3c,0xdc,0x8f,0xa1,0x11,0xcb,0x9a,
+  0x0a,0xd2,0x34,0x30,0x5e,0x83,0x61,0xbc,0xdd,0x4e,0xc8,0xda,0x14,0x83,0x4c,0xa0,
+  0x57,0x35,0x12,0x95,0x56,0x4d,0x9c,0xdf,0x73,0xc5,0x5d,0x22,0x89,0x3b,0xc9,0x77,
+  0x24,0xb3,0x6a,0x44,0x9e,0x1e,0xa4,0xc0,0xcd,0x99,0x85,0xaa,0x33,0x1c,0x48,0x9b,
+  0x19,0x77,0x50,0x9d,0x1f,0xbc,0x50,0xe3,0x51,0x89,0x6a,0x1d,0x49,0xe6,0xfe,0x3e,
+  0x21,0x49,0xea,0xf7,0x46,0x62,0x1a,0xac,0x84,0x09,0x99,0x1d,0x51,0xb3,0xd6,0xda,
+  0x92,0x55,0xa8,0xec,0xb9,0x8f,0x36,0xe5,0xb3,0xb7,0x11,0x7c,0x3a,0x32,0x0f,0xce,
+  0xfd,0xd3,0xb4,0x8f,0x3d,0x1b,0xf6,0x9e,0xb4,0x11,0xa6,0x05,0xcf,0xa9,0xd7,0xdb,
+  0xa6,0x7f,0x96,0x75,0x0f,0x9c,0x6f,0x39,0x41,0xa6,0x64,0x57,0x3e,0x66,0xc0,0x2c,
+  0xfb,0x46,0xbe,0x20,0xed,0x59,0xd8,0x87,0x30,0x4b,0x1a,0x03,0x37,0xec,0x34,0x20,
+  0x24,0xff,0x87,0xac,0x26,0xc0,0xa3,0xdf,0xdd,0xdc,0xc5,0xed,0xee,0xc3,0x64,0x2a,
+  0x54,0x3c,0x77,0x60,0x7e,0xf9,0x9e,0x18,0x12,0x7f,0x3c,0x5a,0xc5,0x6a,0xa7,0x86,
+  0x23,0x80,0x73,0xe7,0x26,0x2e,0xb9,0x0e,0x80,0x55,0x03,0x70,0x67,0x03,0xe5,0xeb,
+  0x7e,0xce,0xa4,0x58,0x7a,0x16,0x4f,0x8a,0xb7,0xcb,0x49,0x31,0x29,0x28,0x0b,0xdd,
+  0x8d,0x68,0x78,0xd8,0x8b,0x3a,0xdf,0xf9,0xdf,0x67,0xd4,0x1b,0x86,0x94,0xd9,0xc1,
+  0xc5,0x7a,0x9b,0xef,0x68,0xe6,0x19,0x40,0x2c,0x6a,0x67,0x65,0xa2,0x36,0xe0,0x20,
+  0xb4,0x15,0x83,0xf4,0x39,0xce,0x7b,0xc3,0x81,0x38,0x87,0x6b,0x04,0xe9,0x49,0xc0,
+  0x92,0x8e,0xac,0x0e,0xbd,0xb8,0x9b,0xe9,0xf8,0x02,0x22,0xe9,0x62,0xdf,0xd2,0xf1,
+  0x00,0xa0,0x33,0x03,0x4c,0x84,0x6a,0x21,0xe4,0x12,0x45,0x8d,0x6c,0x05,0xcf,0x8b,
+  0x24,0x9b,0xa7,0xa5,0x0f,0xea,0xe4,0x7e,0x75,0x9a,0x38,0x1c,0x1e,0x77,0x84,0x99,
+  0x97,0xb7,0x59,0x4e,0x8c,0xf9,0xcf,0xd3,0x8c,0x35,0xe6,0x4d,0xb9,0x5f,0x7b,0x3f,
+  0xaf,0x07,0x7a,0xc9,0xbb,0xbb,0x61,0x4a,0xc7,0x6c,0x50,0x31,0xc6,0x0d,0x7a,0x73,
+  0x48,0xfc,0x67,0x67,0x89,0x03,0x80,0x73,0x80,0x6e,0xff,0xf3,0xfd,0x4f,0x00,0x6c,
+  0xce,0x45,0x43,0xc5,0xdc,0x5c,0x7e,0x39,0x51,0x5b,0x44,0xe2,0x8f,0x58,0xe8,0x2c,
+  0xd6,0x12,0xcb,0x79,0x2b,0x05,0x80,0x44,0x00,0xc6,0x48,0x1b,0xa0,0xa7,0x00,0xfc,
+  0x4c,0x5a,0x6a,0x64,0xd4,0x8e,0xb7,0xef,0xb1,0xe0,0x52,0x03,0x80,0x45,0x47,0x3a,
+  0xd6,0x8c,0x72,0x5c,0xfa,0x5f,0x34,0x40,0x39,0x88,0x6f,0xb7,0x2b,0xb2,0xe9,0x28,
+  0xbd,0x0c,0x20,0x32,0x00,0xd8,0xaa,0x38,0x10,0xdd,0xa0,0x89,0x2f,0xa5,0x84,0x31,
+  0x8a,0x63,0x80,0x79,0x9c,0x06,0x80,0xf3,0x80,0xbc,0x2d,0x49,0x86,0x1d,0xef,0x43,
+  0xba,0xa1,0x55,0xb6,0x16,0x0b,0x91,0x9d,0x41,0xad,0x71,0x40,0x24,0x09,0x43,0x43,
+  0x26,0xee,0xc5,0x38,0x23,0xb6,0xdc,0xf6,0x41,0x18,0xa9,0xb1,0x6b,0x76,0x96,0xa5,
+  0x99,0xc4,0x01,0x50,0x97,0x72,0xfb,0x53,0x03,0x60,0x12,0x80,0x7c,0x65,0x35,0xd0,
+  0x22,0x9e,0x40,0x5b,0xef,0xc6,0xd9,0xc0,0xc0,0xac,0xb0,0xa8,0xcf,0xb6,0x25,0x95,
+  0x02,0x67,0x5d,0x3a,0xf8,0x60,0x2f,0xb2,0x81,0x9f,0xe8,0xed,0x06,0xf2,0xff,0xc3,
+  0x56,0x05,0xe0,0xf9,0xbb,0xbf,0xff,0xd8,0xed,0x7f,0xb7,0xff,0x3d,0x00,0x8d,0x09,
+  0x1c,0xfe,0xaf,0x4e,0x2e,0x6f,0xd5,0x3a,0x99,0x85,0x6f,0x68,0x6b,0xda,0x42,0xa6,
+  0x53,0xdb,0x5a,0x21,0x29,0x00,0x9e,0x03,0x80,0x07,0x02,0xb6,0x47,0x02,0xf1,0xe4,
+  0x9f,0xbf,0x5b,0x49,0x64,0x4d,0x63,0xbb,0xbc,0xf9,0x2c,0x9e,0x77,0x9f,0x32,0xb3,
+  0x96,0x08,0xb3,0xb2,0xe0,0x37,0xeb,0x0d,0xcb,0x68,0xd9,0x1e,0xd7,0x92,0x5d,0x79,
+  0xdd,0x8d,0x5a,0xe1,0xc4,0x37,0x6b,0xc8,0x12,0xee,0x00,0x76,0x06,0x4c,0x7c,0x8b,
+  0x67,0x8d,0x1a,0x19,0x0d,0xc0,0x1a,0x0f,0x88,0xc9,0x03,0x1a,0x34,0xac,0x85,0x07,
+  0xd1,0x48,0xc8,0xc6,0x51,0xd8,0x27,0xd6,0x65,0x03,0x80,0xd9,0x99,0x1b,0x83,0x2a,
+  0x1c,0x3e,0xb3,0x63,0x8c,0x64,0x12,0x17,0xc4,0x0a,0x55,0x20,0xd4,0xcc,0x53,0x03,
+  0x5e,0x2b,0x29,0x07,0x39,0xa1,0xa3,0x9f,0x32,0x61,0xe5,0x5d,0xf5,0x5e,0xfa,0x81,
+  0xdf,0x90,0x5c,0xae,0x59,0xf5,0xc0,0x56,0x14,0x58,0x55,0x40,0x27,0x23,0xda,0xc2,
+  0x3f,0x8b,0xfb,0x01,0x90,0x3f,0x1c,0x02,0x9c,0x3d,0x44,0x1c,0x00,0x1c,0x01,0xfc,
+  0xf2,0xdf,0xed,0x7f,0x02,0xa0,0x59,0x8c,0x5e,0xba,0x90,0xc3,0x19,0xec,0xd9,0xd5,
+  0xcc,0x5a,0xa1,0x50,0x40,0x0a,0x60,0x75,0x31,0x96,0x58,0xb6,0x22,0x80,0xa4,0x13,
+  0x50,0xd7,0x4e,0x02,0xa0,0x1a,0x01,0xa5,0x4e,0x40,0xd7,0x1e,0x4e,0x53,0x36,0x8f,
+  0x9c,0x43,0x93,0xfd,0xf3,0x29,0x25,0x5e,0xb6,0xd8,0x84,0x19,0x93,0x25,0x94,0x4a,
+  0xca,0xb0,0x84,0xbc,0xb9,0x82,0xb3,0xd1,0xf9,0x95,0x3d,0xe5,0x81,0x07,0x00,0xb3,
+  0x44,0x8d,0x9f,0x82,0x68,0xd0,0x82,0x98,0xd6,0x8c,0x44,0x75,0x7e,0x7e,0x72,0x19,
+  0x0f,0x3a,0xd0,0x60,0x14,0xc0,0xf6,0x67,0x07,0xdb,0x14,0x19,0x95,0x8c,0x8c,0x4a,
+  0xa4,0x3a,0xd7,0x6c,0x5f,0xfd,0x00,0xc9,0xd8,0xe3,0x56,0x1e,0xa4,0x24,0x73,0xc3,
+  0xa3,0xe9,0xdc,0x2e,0xe7,0x68,0xc8,0x2b,0x1f,0x86,0x41,0xbe,0xcb,0xf2,0x56,0xe7,
+  0x27,0xc4,0x9e,0x04,0xfc,0xc6,0x7c,0x4e,0x49,0xf7,0x9b,0xaa,0x7d,0x10,0x8e,0x4f,
+  0x87,0xc7,0xd9,0x0a,0xbe,0x44,0x56,0xf9,0xa0,0x9b,0x4f,0x40,0x9e,0x16,0xf7,0x59,
+  0xc9,0x02,0x4c,0xfb,0xc0,0xac,0xe4,0x97,0x40,0xe0,0x65,0x37,0x88,0xeb,0x3f,0x4e,
+  0xed,0x72,0xc3,0xea,0x0b,0x8c,0x1c,0x80,0x3b,0x4f,0x7d,0x04,0x47,0x00,0xbf,0xbc,
+  0xff,0x09,0x80,0x7a,0x28,0x75,0xe9,0xc2,0x39,0x3c,0x56,0xc6,0xe2,0xaa,0xa6,0x15,
+  0x96,0x0a,0x4b,0x6b,0xc8,0x01,0xc8,0x6e,0xb5,0xf2,0xf3,0x73,0x97,0x89,0x03,0x10,
+  0x75,0x23,0x00,0x8e,0x03,0xe0,0x57,0x03,0x18,0x23,0xd6,0x74,0x49,0x9c,0xd0,0x93,
+  0xbf,0xf7,0xee,0x9f,0x1f,0x5e,0xb6,0x18,0x69,0x50,0x16,0x73,0x0a,0x82,0xa5,0x8a,
+  0xe4,0x8c,0x58,0x62,0x51,0x6b,0xf0,0xd2,0xed,0x75,0x01,0x2c,0x15,0x0a,0xcb,0x09,
+  0x5a,0xd4,0x1c,0x06,0x9f,0x82,0xbe,0x3b,0xac,0xb7,0xec,0xe1,0x40,0xd0,0x25,0xa8,
+  0xd3,0x69,0xcd,0xda,0x60,0x79,0x40,0x78,0x1c,0x85,0x84,0x3b,0x2f,0x92,0xab,0x03,
+  0x54,0xe7,0xea,0xf9,0x5e,0xb8,0x26,0x59,0xba,0x69,0xbf,0xf1,0xbd,0x09,0x75,0x9f,
+  0x01,0xc0,0x32,0xdb,0x62,0xda,0x8e,0xb7,0x65,0xf6,0x9d,0xa3,0x02,0xf8,0x5c,0x82,
+  0xf8,0x8c,0x86,0xed,0x7f,0xe4,0x71,0xbf,0x46,0x3e,0x6a,0x63,0x4d,0xe6,0x93,0x8d,
+  0x9a,0xd8,0x7b,0x14,0x80,0x8c,0x00,0xe0,0x2b,0x7e,0x81,0xe4,0x52,0x74,0xe6,0x65,
+  0xc2,0x3f,0xc8,0x36,0xd9,0xac,0x42,0x37,0xd6,0x47,0xe2,0xfc,0xde,0x52,0x1b,0x61,
+  0x5b,0x05,0xb8,0x81,0x80,0xb0,0xe3,0x00,0xe0,0x16,0x80,0xfd,0x4f,0x00,0x8c,0x9c,
+  0x49,0x85,0x26,0xce,0x91,0x71,0x2c,0x33,0xdf,0x28,0x2c,0x2d,0xb5,0xf1,0x44,0x9a,
+  0xc8,0x01,0x58,0x59,0x9e,0xb7,0x9b,0x00,0xf1,0x4c,0x60,0x9e,0x02,0xa0,0x67,0x04,
+  0xe7,0x49,0xb7,0xb5,0x21,0x9f,0x79,0xa4,0xc9,0xad,0x75,0x1e,0xde,0x0b,0x79,0x48,
+  0x4a,0xdc,0xa8,0xbb,0xf5,0x1c,0xc9,0x29,0x12,0x72,0x0a,0x82,0xb5,0xcf,0x87,0x46,
+  0x16,0x65,0xcd,0xda,0x94,0xfc,0x5b,0x89,0x2f,0x92,0x51,0xb5,0x07,0xef,0xbd,0x93,
+  0x6a,0x44,0x2a,0x64,0xee,0x81,0xb3,0xd9,0x4c,0x21,0xc2,0xe4,0x01,0x75,0x06,0xcb,
+  0x03,0xb2,0x86,0xfa,0x47,0xd2,0x48,0xd2,0xf7,0x55,0x72,0xb1,0xec,0x6b,0xe5,0x8f,
+  0x73,0x2d,0x55,0x7b,0x05,0xdf,0x6b,0x2b,0xab,0xdb,0x20,0x2d,0xbb,0x52,0xbb,0x4f,
+  0x36,0x11,0xa2,0xb7,0xed,0x26,0x75,0xe7,0xf0,0x93,0x1c,0x0e,0x9f,0xb1,0x1f,0x1f,
+  0x2e,0x60,0xf9,0x17,0x15,0xaa,0xbb,0x21,0x6b,0x13,0x4d,0xef,0x10,0x39,0x9a,0x03,
+  0x5e,0x2c,0x09,0xc7,0x37,0x38,0x21,0xf6,0xf5,0xfe,0x05,0xb7,0x9f,0xf7,0xed,0x45,
+  0xa9,0x67,0x72,0x03,0xbd,0x57,0x7a,0x16,0x01,0x26,0x57,0x88,0x6e,0x4f,0xa0,0x16,
+  0xa2,0x46,0x09,0x22,0xe1,0xfe,0x71,0xbc,0xa7,0x71,0xdc,0x0f,0x08,0xd7,0xfb,0xd1,
+  0x3b,0xec,0x0e,0xa0,0x2f,0x91,0x2a,0x9b,0x25,0x11,0x00,0xe4,0x00,0xfc,0xdd,0xb1,
+  0x3f,0xec,0x51,0x00,0x76,0x87,0x1e,0x3a,0x73,0x69,0xe2,0x5c,0xb5,0x82,0x6e,0x7f,
+  0x46,0x2b,0xb4,0x2f,0xb6,0x91,0x02,0xd0,0x70,0x04,0xc0,0xca,0x01,0x74,0x1c,0x00,
+  0xa7,0x11,0xd0,0x0d,0x01,0xc8,0xea,0x00,0xe8,0xe6,0x2f,0x4b,0xbd,0xe9,0xa9,0x29,
+  0x6b,0x1a,0x79,0xc3,0x20,0x4f,0x6b,0x2e,0x79,0xc3,0x20,0xf3,0xc8,0xab,0xb2,0x42,
+  0xea,0xa5,0xe8,0x56,0xf1,0x8c,0x72,0xa4,0x4d,0x91,0x59,0x2a,0x98,0xfd,0x8f,0xea,
+  0x19,0x6b,0x7a,0x0f,0xb6,0x94,0x79,0x3d,0x80,0xf0,0x00,0x60,0x44,0xfe,0x85,0xb1,
+  0x28,0x76,0xd1,0x13,0xb5,0xa8,0x37,0xf2,0xd5,0xea,0x64,0xa5,0x75,0x76,0x71,0x61,
+  0x29,0x32,0xb2,0xa9,0x7a,0xd6,0xb2,0xf6,0xec,0x00,0xdb,0xc1,0x43,0xfd,0xaf,0xd4,
+  0x32,0x6d,0x3c,0x87,0xa9,0x7b,0xb9,0xf0,0x9b,0x4d,0x55,0x9a,0x36,0x4f,0xd2,0x21,
+  0xc9,0xd5,0xa5,0x2f,0x2e,0xb9,0xbe,0xaa,0x6c,0x79,0xd9,0x00,0x60,0x78,0x00,0x40,
+  0x59,0xb3,0xdd,0x94,0xd5,0x72,0xb7,0xb9,0x69,0x58,0xdb,0xdc,0x74,0x8f,0x07,0xbf,
+  0x37,0x54,0x7e,0x5e,0x5f,0xec,0xbb,0xe0,0x11,0x95,0xc5,0x4c,0x22,0xab,0x0c,0x6c,
+  0xaa,0xf6,0x31,0x3a,0xe7,0xa4,0x8a,0xf7,0x7f,0x71,0xaf,0x0a,0xe0,0xb8,0x6f,0xfc,
+  0x4f,0xf0,0xfe,0xfd,0x9a,0xee,0xb8,0x65,0xdd,0xf7,0x61,0xcf,0x66,0x87,0x9d,0x4a,
+  0xfb,0xac,0x97,0xd7,0xef,0xa9,0x00,0xbb,0x0a,0xe0,0xfc,0x1a,0x96,0x56,0x11,0x1c,
+  0x23,0x4f,0xfe,0x8f,0x5b,0x95,0x00,0xf7,0x2b,0xcb,0x0d,0xd8,0xc0,0x0e,0xc0,0xa1,
+  0x3b,0xef,0x44,0x0a,0xe0,0xf9,0x63,0x7f,0xf7,0x39,0xd9,0xdd,0xdf,0x13,0x66,0x31,
+  0x75,0x69,0x62,0x6e,0x7e,0x39,0x51,0xeb,0x2c,0xac,0x2d,0xb5,0xb7,0xdb,0x8d,0x8b,
+  0x4b,0xd8,0x01,0xa8,0xe1,0x4e,0x00,0xc4,0x01,0xb0,0x42,0x80,0x63,0x69,0x3a,0x0f,
+  0x58,0xee,0x00,0xc4,0x5d,0xc7,0x55,0x28,0x43,0x78,0x22,0xe9,0x1d,0x3c,0x8d,0xbc,
+  0xee,0x3c,0x74,0xfc,0xbe,0x5e,0x37,0x65,0xfd,0x7f,0xa7,0x34,0x57,0x5e,0x72,0x23,
+  0x89,0x4a,0x4c,0x1c,0xc6,0x2e,0x58,0x4f,0xd1,0xa8,0xbe,0x6a,0xe7,0x23,0x31,0x07,
+  0xe3,0x39,0xf7,0xa5,0x4e,0xc3,0x1a,0xaf,0x42,0x38,0x86,0x73,0x83,0x17,0xbb,0x92,
+  0x95,0x07,0x34,0x89,0xd3,0x00,0x16,0xda,0xcc,0xac,0x20,0xea,0x40,0x79,0x40,0xd9,
+  0x48,0xa5,0x85,0x47,0x15,0x8e,0x94,0xeb,0xf8,0x3a,0x59,0x97,0x4b,0xaf,0x8f,0xd4,
+  0x4d,0x24,0x31,0x32,0x05,0x80,0xe4,0x8a,0x5c,0x5c,0xef,0xea,0x92,0xf5,0x4c,0xf3,
+  0x71,0x43,0xe2,0xd1,0x4b,0x92,0xfa,0x53,0x46,0x6d,0x88,0xb4,0xdc,0x8a,0x1d,0x86,
+  0x90,0x80,0xe2,0x6d,0xeb,0xe2,0xc3,0xd4,0xeb,0x2a,0x9f,0x4b,0x54,0xd2,0x6c,0x85,
+  0x2a,0x6a,0x12,0x32,0x53,0xfb,0x8e,0x8e,0x57,0xd3,0xed,0x23,0x35,0x31,0xe2,0xfd,
+  0xaf,0xed,0x31,0x06,0x70,0x3c,0xbc,0xc1,0x8d,0xd9,0x23,0xd1,0x00,0x3d,0xd5,0x83,
+  0xe8,0xff,0x0b,0x5d,0x79,0x65,0xb5,0x03,0xff,0xfa,0xff,0xac,0xf5,0x71,0x43,0x58,
+  0x2c,0x6c,0x7d,0xc7,0xfc,0x80,0x8c,0xff,0x86,0x15,0x0f,0xc0,0xe7,0x61,0x47,0x00,
+  0x3f,0xf2,0x91,0xe7,0x9f,0xff,0xfe,0x7f,0x26,0xb9,0xf9,0x7b,0x43,0xcd,0xa5,0x2e,
+  0x5d,0x9e,0x9b,0xaf,0x9c,0xcd,0xae,0x22,0xf9,0xdf,0x9e,0x69,0x6c,0x23,0x0f,0x40,
+  0xcb,0x2c,0x5a,0x4d,0x00,0x38,0x07,0x28,0xf5,0x54,0xd2,0x76,0x00,0x9e,0xc6,0x8d,
+  0x80,0x4e,0x0c,0x80,0xcb,0x50,0x27,0x1a,0x41,0x6b,0xb7,0xce,0xca,0x6a,0xd3,0xd6,
+  0x34,0xdd,0xfa,0xfa,0x7a,0xa3,0x7d,0xba,0x81,0xa7,0x92,0x27,0x2f,0xdb,0x8d,0xc6,
+  0xf6,0x0c,0x2a,0xe3,0x92,0xc5,0xbd,0x16,0xba,0x9c,0xd9,0x5a,0xde,0x12,0xb7,0x19,
+  0x2c,0xfe,0x8f,0xec,0x3f,0x9e,0x5f,0xa0,0x87,0xfc,0x93,0x01,0xc0,0xf0,0x3c,0xd4,
+  0xfc,0x11,0xec,0x66,0x20,0xba,0x52,0xd5,0xd0,0x26,0x71,0x23,0x00,0x92,0xde,0x85,
+  0x8b,0xb8,0xfd,0xce,0xdd,0xf1,0xe6,0x20,0x71,0xad,0x58,0x64,0x19,0x57,0x22,0xb0,
+  0x3a,0x9e,0x69,0x9c,0x26,0x17,0x0b,0x5f,0xb3,0xd3,0xeb,0xb8,0x43,0xbf,0x44,0x01,
+  0xe0,0xf9,0x86,0xca,0xe5,0xf5,0x19,0x44,0xc3,0x59,0x1a,0xaf,0xb6,0xbe,0x5e,0xd6,
+  0x85,0xc9,0xc9,0x38,0xf9,0xb7,0x0e,0x2b,0x6a,0x2e,0xb6,0xe4,0x99,0x5b,0x78,0x86,
+  0xe5,0x7a,0xf9,0x34,0x3a,0x8c,0x19,0xfb,0xbe,0x59,0xff,0x4e,0x6f,0xe3,0x1b,0xb8,
+  0xc3,0xf7,0xc2,0x42,0x0a,0x75,0x19,0x4f,0x53,0xa4,0x8b,0x2e,0x20,0xd2,0x23,0x75,
+  0x3d,0x72,0xfa,0xf4,0xb6,0xb5,0x05,0xfc,0x77,0x7a,0x66,0x3d,0x52,0xc6,0xd5,0x1c,
+  0x2e,0xb9,0x23,0xd8,0xe8,0x4b,0xf2,0x7b,0x80,0xfe,0x8e,0x58,0x62,0xe4,0x64,0xd3,
+  0x58,0x4f,0x2f,0x24,0x60,0x3b,0xde,0x6c,0x54,0xde,0x9b,0x2d,0x5c,0x9a,0x1b,0xec,
+  0xac,0xe7,0xd5,0x13,0xc6,0xa7,0xed,0x46,0x3a,0x4b,0x62,0xed,0xd7,0x59,0xf7,0x03,
+  0x85,0xb5,0x28,0xa5,0x01,0xb0,0x7f,0x1f,0xde,0x20,0xc3,0xfd,0x6c,0x38,0x3f,0xb9,
+  0x51,0xff,0x71,0xcb,0x0b,0xb0,0xc4,0x1f,0x37,0x01,0x62,0x0f,0xe0,0x4e,0xe4,0x01,
+  0x7c,0xe4,0xfb,0xbf,0xff,0x3f,0x0a,0xf7,0x7e,0xaf,0xa8,0x73,0xa9,0x22,0xaa,0xff,
+  0xb7,0x90,0xfc,0x6b,0x85,0x8b,0xdb,0x33,0xeb,0x48,0x28,0x97,0x0a,0x0b,0xab,0xd9,
+  0xad,0x44,0x85,0x0c,0x03,0x70,0x29,0x95,0xa2,0xda,0x00,0xac,0x44,0xe0,0x67,0xa9,
+  0xc1,0x00,0xa8,0x72,0x8d,0xbc,0x69,0xc7,0xfe,0x8b,0x23,0xbb,0xd7,0x23,0xdb,0x85,
+  0xb5,0xb5,0x85,0x85,0x05,0x6d,0xc1,0x42,0xd3,0x16,0x70,0xc0,0x51,0x3a,0x46,0xcd,
+  0xb6,0x6b,0xde,0x27,0xf4,0xad,0x0a,0x19,0xa2,0x93,0xeb,0xc4,0x1f,0x0d,0x52,0x18,
+  0x52,0xba,0xb6,0x28,0x19,0x68,0x92,0x1a,0x02,0x2c,0x51,0x5e,0x26,0x2d,0x04,0x82,
+  0x0a,0xda,0x55,0x11,0x2c,0x91,0x3c,0x20,0xa2,0x00,0x70,0x1a,0x00,0x5d,0xab,0xd8,
+  0x19,0xa0,0x6d,0x3b,0xa1,0x57,0x2a,0xa4,0x3d,0x66,0xc1,0x41,0xc3,0x4f,0x7c,0xb1,
+  0xca,0xa6,0x64,0x04,0x10,0x3c,0x0b,0xf2,0x0c,0x8e,0xdb,0x2c,0xb8,0x97,0x57,0xc3,
+  0x8f,0x35,0x3c,0x0d,0xba,0x98,0x45,0xc0,0xd5,0x6d,0xf0,0x71,0x25,0x47,0x16,0xe5,
+  0x03,0x80,0x22,0x65,0xb9,0xa3,0x37,0xda,0x68,0xdb,0x9a,0xb7,0x75,0xfb,0x0e,0xa2,
+  0xef,0xca,0x7c,0x2e,0x11,0x56,0xa8,0xa8,0x08,0x48,0x1c,0x2a,0xbb,0x08,0x14,0x34,
+  0xfa,0x9c,0xb4,0x42,0xe1,0x62,0x43,0x1f,0xe1,0x2b,0x68,0x7e,0x73,0x1a,0x07,0xe4,
+  0x70,0x98,0x88,0xce,0x38,0x2d,0x80,0xe3,0xec,0x7b,0x52,0xe7,0x76,0x85,0x7f,0xdc,
+  0x4e,0xb9,0xb3,0xc4,0x7a,0x9c,0x89,0x19,0x8c,0xcf,0xba,0x52,0x3d,0xee,0x1a,0x6a,
+  0xd7,0x49,0xa7,0xcc,0xf6,0xac,0xf8,0xc1,0x8b,0x3b,0x58,0x62,0x8f,0x95,0xcc,0xc6,
+  0xac,0xbb,0xa3,0x0d,0xa7,0xa6,0x30,0xee,0x38,0xfb,0x8e,0xd5,0xdf,0xc0,0xf2,0x3f,
+  0x8e,0x75,0xc0,0xc6,0x2c,0x09,0x01,0xde,0x89,0x1c,0x80,0xe7,0x9f,0xff,0xc8,0x55,
+  0x18,0x00,0x28,0x9f,0x0a,0x5d,0xc6,0xfe,0x3f,0xb2,0xff,0x85,0xf6,0x4c,0x03,0xd9,
+  0xe8,0x06,0x76,0x00,0x3a,0xb5,0x17,0x71,0x13,0x80,0xd5,0x0d,0xd8,0x52,0x00,0x63,
+  0xe9,0xa7,0xdd,0x2a,0x80,0xa8,0x01,0x4a,0xe4,0xe6,0xb7,0x70,0xbc,0x5d,0x18,0xd8,
+  0x1d,0x8f,0xd6,0x19,0xc1,0xf3,0xc8,0x67,0x17,0xb3,0xe8,0x49,0x1e,0x35,0xf4,0x40,
+  0x64,0xd6,0xda,0xe2,0xc4,0x9e,0x94,0x7b,0x1f,0x32,0x63,0x15,0x6b,0x92,0x10,0x66,
+  0x19,0xbf,0x21,0x85,0x58,0x42,0x46,0x26,0x23,0x8c,0x6a,0xd5,0xa4,0x93,0x7b,0x86,
+  0xf4,0x15,0x3c,0xf3,0xb5,0x38,0x05,0x41,0xc0,0x01,0xc0,0x38,0xe2,0x31,0x63,0xd1,
+  0xee,0x0c,0x4c,0x66,0x05,0xa1,0x64,0x4f,0x0f,0x1e,0x51,0xac,0xe8,0xcb,0x93,0xcb,
+  0xcb,0x89,0xad,0x5a,0xcd,0xbe,0x5a,0x8b,0xe4,0xba,0x2d,0x76,0x70,0x9d,0x40,0x2a,
+  0x59,0xfa,0xe9,0xc2,0x42,0xa7,0x63,0x5f,0x57,0xbc,0x42,0x0d,0xaf,0xd0,0x41,0xb7,
+  0xf4,0xb4,0x18,0xd3,0x93,0x5c,0xbb,0xae,0xde,0xc1,0x53,0x37,0x8b,0x53,0xb7,0x90,
+  0x59,0x56,0x96,0x50,0x7d,0xd0,0xbb,0x71,0x78,0x17,0xe4,0x78,0xd0,0x1d,0x6c,0x08,
+  0xb9,0x44,0xd6,0x34,0x25,0x33,0xe2,0x00,0x20,0x4d,0x32,0x57,0x73,0xa6,0xb3,0x38,
+  0xea,0x6c,0x29,0x8b,0xcf,0x69,0x35,0x53,0xb8,0xb8,0x2e,0x58,0x80,0xf6,0x9e,0x42,
+  0x00,0x87,0x5d,0x09,0x1c,0x0f,0xd3,0x4a,0x40,0x68,0xb8,0x67,0x35,0xc3,0x34,0x35,
+  0x06,0xcf,0x06,0xab,0x31,0xd8,0xc6,0xc0,0x0d,0xdb,0x0b,0x40,0xff,0xb1,0x07,0xb0,
+  0xd1,0xe3,0xd5,0x7a,0x71,0x96,0xb5,0xd5,0xc6,0x86,0xe3,0x05,0x90,0x18,0x9f,0xad,
+  0x1d,0xc8,0x91,0xd8,0x7a,0x6b,0xdc,0x0a,0x00,0x8e,0x63,0xeb,0x3f,0x6d,0x2b,0x00,
+  0x6c,0xff,0x7f,0xe3,0x03,0xfc,0x55,0xdd,0x3b,0x2b,0x56,0xfd,0x7f,0x6b,0x31,0xa3,
+  0x15,0x90,0xf9,0x5f,0x8f,0xac,0xaf,0x6f,0xe3,0x08,0x40,0xb6,0xb6,0x62,0xe5,0x00,
+  0x58,0x93,0x81,0x27,0xbb,0x63,0x5d,0xab,0x06,0x80,0x83,0x80,0x74,0x26,0x90,0x57,
+  0x0b,0x28,0x25,0x88,0xfc,0x9f,0x96,0xcd,0x23,0x5b,0x6f,0x14,0x90,0x4f,0x71,0x76,
+  0x25,0xf1,0xe2,0x0a,0x45,0xa2,0x86,0xe5,0x44,0x74,0x00,0x3c,0xf7,0x3e,0x3a,0x92,
+  0xb5,0x46,0xf1,0xe3,0xa4,0x38,0x90,0x7c,0xe6,0x8c,0x8c,0x26,0x8e,0x80,0xab,0x8e,
+  0x78,0x95,0x87,0x49,0xbd,0x95,0x90,0x54,0x11,0x02,0x0f,0x00,0xc6,0x13,0xef,0x18,
+  0xb1,0x79,0xac,0x00,0x12,0xb5,0xd5,0x82,0x35,0x2b,0x88,0xb3,0xf3,0x48,0xe0,0x26,
+  0xc5,0xaa,0x3e,0x84,0x7c,0x88,0xe5,0xd6,0x0a,0x4b,0x02,0xb9,0x04,0x85,0xd3,0x92,
+  0x49,0xfa,0x36,0xcd,0x72,0x7b,0x01,0x67,0x6d,0xf3,0x2b,0xd4,0xf0,0xec,0xa4,0xa2,
+  0x4c,0x8b,0x75,0x1b,0xdc,0x72,0x6b,0x4f,0x16,0xc0,0x5d,0x2b,0xd5,0x28,0xb7,0xd7,
+  0x3a,0xb5,0x2d,0xf6,0xbe,0x59,0x9b,0x5f,0x59,0x29,0x08,0x71,0x98,0x21,0x1d,0x17,
+  0x01,0x21,0x5f,0x93,0x14,0x81,0xd3,0x56,0x11,0x78,0x11,0xaf,0xb9,0xb2,0x82,0x0f,
+  0x37,0x81,0xcf,0x09,0x77,0x99,0xe0,0xf4,0x6f,0x73,0x72,0x77,0x97,0xdf,0xe2,0x07,
+  0x37,0xc2,0xe3,0xae,0xf5,0x65,0x82,0xff,0x1b,0x9e,0x35,0x1e,0x9f,0x9d,0x66,0x6c,
+  0xb6,0x25,0xd9,0x74,0x35,0xdd,0x15,0x5f,0x5b,0x9e,0xa9,0x56,0x7a,0x5b,0x76,0xdd,
+  0x85,0x5c,0xd9,0xb6,0xff,0x5b,0xea,0xc3,0x59,0xdf,0xd9,0x88,0xf7,0x9e,0x71,0x20,
+  0x36,0xdc,0xbf,0x0d,0x4b,0xf6,0x37,0x1c,0x55,0x80,0xd4,0xd7,0xc6,0x06,0xf6,0xff,
+  0x49,0x05,0xe0,0x23,0x1f,0xf9,0x8d,0xcd,0xa9,0x7d,0x27,0x8b,0xe4,0xff,0x1c,0xb1,
+  0xff,0xa8,0xfa,0x8f,0xaa,0x63,0x91,0xc8,0x3a,0xaa,0x01,0x68,0x0b,0x38,0x07,0xc0,
+  0x0e,0x01,0xe2,0x7e,0xc0,0x6e,0x0c,0x10,0xc7,0x00,0xe2,0x25,0x2f,0x11,0x80,0x1e,
+  0x11,0x20,0xa1,0x5b,0xf6,0x5f,0x98,0xd0,0x1b,0xcf,0xd4,0xbb,0xb0,0xb8,0xd5,0x5a,
+  0x26,0x33,0xc8,0x2f,0xe7,0x2b,0x95,0x0a,0x7a,0xcd,0x2f,0x23,0x2b,0xb7,0xb8,0x20,
+  0x8c,0xd0,0x49,0xcf,0x18,0x94,0x8c,0x64,0xf2,0x38,0x00,0x10,0x31,0x37,0x99,0xb6,
+  0xa2,0x40,0x9d,0xc5,0x2a,0xc6,0x42,0x61,0x7d,0x87,0x1f,0x39,0x9c,0xb6,0x2e,0x55,
+  0x2b,0xf1,0xe5,0x3d,0x42,0xe2,0x4b,0x76,0x97,0x65,0x6f,0x4c,0x1b,0xd9,0xc2,0x0a,
+  0x00,0x55,0x2b,0x56,0x97,0x1a,0x75,0x3a,0x13,0x78,0x29,0x68,0x4e,0xe1,0x81,0x91,
+  0xd6,0xfc,0xe4,0x64,0x1e,0x4f,0xc6,0x52,0xb1,0x9e,0xe4,0xdd,0x32,0xaa,0xa4,0xe1,
+  0x49,0x7a,0x25,0xce,0xd5,0x7a,0x61,0x35,0xb6,0xd2,0xb2,0x2f,0x2b,0xf9,0xab,0xe0,
+  0x8b,0xbb,0x12,0xcb,0xe0,0x09,0x50,0xfa,0x0f,0x6e,0x1c,0x27,0x69,0x3b,0x92,0xc9,
+  0x82,0xb0,0xd5,0x5e,0xca,0xd4,0xce,0xe2,0x3b,0xb7,0x4c,0x8e,0x63,0xd9,0x7e,0x90,
+  0xf7,0x19,0x21,0x97,0x08,0x4f,0x53,0xb4,0x28,0xe9,0x49,0x80,0xdd,0xff,0x86,0x86,
+  0x8b,0x80,0x73,0x7c,0x64,0x53,0x48,0xc9,0xd5,0xf0,0xc0,0x69,0xfc,0x49,0xf9,0x0d,
+  0x6a,0x14,0x88,0x2f,0x4f,0x0b,0x02,0x49,0x9c,0xed,0x0d,0x4a,0x03,0x84,0x3d,0xc3,
+  0x3e,0x4e,0x2f,0xe6,0xfa,0xea,0xcc,0x9a,0x94,0x84,0x4e,0xd3,0x1e,0x03,0x53,0x0d,
+  0x10,0x3e,0xd2,0x8c,0x7b,0x5a,0xc0,0x5e,0x6c,0xdc,0xd6,0x11,0xd8,0xc9,0x1f,0x77,
+  0x9d,0x01,0xdb,0xfe,0x5b,0x15,0x00,0xe2,0xb3,0xcc,0x6e,0xcc,0x22,0xf9,0x9f,0xc5,
+  0xf2,0xff,0x8f,0x57,0x21,0x1f,0x3c,0x63,0xcb,0x3f,0xb2,0xff,0x4b,0xed,0x48,0x24,
+  0x52,0x2e,0x23,0x05,0xd0,0x5e,0xd3,0x56,0x71,0x2f,0x00,0x1c,0x01,0xc0,0x35,0x00,
+  0x3b,0x04,0x60,0xc5,0x00,0xbc,0x4c,0x40,0x47,0x01,0x38,0xf6,0xbf,0xa2,0x27,0x48,
+  0xc3,0xb5,0xe0,0x4d,0xab,0x3b,0x48,0xfe,0x91,0x43,0x91,0xcf,0x4f,0x5a,0xcc,0x93,
+  0x67,0x1e,0x8f,0x3a,0x40,0xdc,0x4e,0xce,0xec,0xe8,0x51,0xb7,0x64,0xce,0x14,0x48,
+  0x27,0xfe,0x19,0x2e,0x37,0x2d,0x50,0x00,0x70,0x74,0x67,0xad,0xcd,0x8f,0x1c,0x38,
+  0xa5,0x36,0xa9,0x0e,0x70,0x07,0x46,0x12,0x2b,0xf2,0x01,0xc0,0x76,0x1b,0x83,0x8e,
+  0x0e,0x23,0xeb,0x3d,0x3f,0x99,0x5f,0x7e,0xd1,0x9e,0x15,0xc4,0xcb,0xd8,0x09,0x9a,
+  0x07,0x34,0x61,0xb6,0xf0,0x64,0xe1,0x93,0x14,0xf9,0x79,0x74,0xe5,0x96,0x71,0xab,
+  0xa0,0xd8,0x57,0x19,0xc9,0xe8,0x7a,0xa1,0xb3,0xd5,0xca,0xbb,0x57,0xd7,0x5e,0x87,
+  0xf4,0x47,0x94,0xb4,0xc6,0x88,0xc3,0x31,0xe1,0x01,0xc0,0xa4,0x69,0x7b,0x58,0xfe,
+  0xb1,0x6e,0x41,0x9b,0x66,0x37,0x3e,0x49,0x3e,0x2f,0x0a,0xb7,0x81,0xcc,0xe9,0xa8,
+  0x49,0x7a,0x12,0x20,0x47,0x62,0x7b,0x21,0x7b,0x16,0x15,0x81,0x79,0xf6,0x18,0xf1,
+  0xb8,0x49,0xa2,0x93,0xb2,0x87,0xce,0x80,0xa5,0xbb,0x69,0x49,0x73,0xe5,0xd6,0x0a,
+  0xa6,0x39,0x1a,0x60,0xc3,0xd1,0x08,0x58,0xba,0x39,0xf3,0x8c,0x7f,0x70,0xdb,0xef,
+  0xdd,0x3a,0x39,0x5d,0xf5,0x1f,0x77,0x6b,0x0e,0xce,0x3b,0xf7,0xe3,0xb8,0xfb,0x81,
+  0xf9,0x4f,0x29,0x08,0x2c,0xf5,0x1b,0x6e,0x38,0xc1,0xaa,0x01,0x58,0x31,0x7f,0xe2,
+  0xf4,0x6f,0x7c,0xd2,0xfe,0x4f,0xfe,0xb0,0xfd,0x1f,0x47,0x0a,0x80,0xd8,0xff,0xbb,
+  0xf8,0x3b,0xb9,0x0f,0xb4,0x89,0xfc,0x57,0x90,0xfd,0xd7,0x88,0xfd,0xd7,0x91,0x02,
+  0x38,0x8d,0x6b,0x00,0x1d,0xac,0xac,0xe7,0xab,0x56,0x12,0xc0,0x53,0x51,0xab,0x23,
+  0xc0,0x33,0x4e,0x22,0x10,0x35,0x1e,0x80,0xa7,0x04,0xf2,0x23,0x89,0x44,0x76,0x41,
+  0xec,0xac,0x8b,0xe5,0xbf,0x8d,0xe4,0xbf,0x32,0x89,0x8b,0xf5,0x3c,0xa6,0x3a,0x89,
+  0xff,0x26,0xf3,0x2d,0xd2,0xb8,0xc7,0x2b,0x0c,0xba,0x85,0x3e,0x82,0xac,0x04,0x6e,
+  0x9b,0x66,0xe5,0x58,0x0d,0x30,0xbe,0x76,0xba,0xa1,0x0f,0xaf,0x8f,0x08,0x23,0x07,
+  0xd2,0x33,0xe6,0xe4,0x0c,0x22,0xff,0x65,0x61,0x0c,0xf2,0xdd,0x77,0x46,0x0f,0x45,
+  0x22,0x43,0x38,0x06,0x88,0x47,0x03,0x58,0x5a,0x67,0xe2,0x75,0x7d,0x86,0x2c,0x75,
+  0x28,0x5a,0x43,0x0a,0xce,0xcf,0x4f,0x5a,0xd7,0xc9,0xfe,0x9f,0xb7,0x2e,0x96,0xd0,
+  0x5e,0x86,0x64,0xf4,0xf4,0x5a,0x67,0x6b,0x19,0x09,0xe4,0xbc,0x0b,0xe9,0x8d,0x54,
+  0xb1,0xba,0x4e,0xf3,0x56,0x43,0xac,0xdb,0xc4,0x87,0x0b,0x2d,0x79,0xda,0xce,0xa6,
+  0x19,0x59,0x5a,0x8d,0xb5,0x98,0x6d,0x5b,0xf7,0x0f,0x1f,0x61,0x56,0xe8,0x27,0x75,
+  0x00,0x5d,0x50,0xe9,0x9c,0x6e,0x4d,0xec,0x02,0x66,0x57,0x90,0xfb,0x47,0xce,0xac,
+  0x6a,0x95,0x01,0x54,0x02,0xb0,0x77,0xc7,0x8f,0xd1,0x1a,0x34,0xc1,0x43,0xca,0xb3,
+  0xa7,0xc2,0x94,0x71,0x75,0x23,0x6a,0x76,0x8d,0xda,0xf7,0xc1,0xfe,0xc3,0x06,0x98,
+  0xc0,0x6f,0xc4,0xd9,0x32,0xed,0xf6,0x6f,0x78,0x6a,0x81,0xfd,0xc2,0xb5,0xf6,0xce,
+  0xee,0xa7,0xbd,0xc8,0xa4,0x65,0xe9,0xad,0xad,0x62,0x7d,0x60,0x45,0xfe,0xed,0xaf,
+  0x36,0xec,0x20,0xc0,0xf8,0xc6,0x2c,0x52,0x00,0x1b,0x44,0x01,0x7c,0xec,0x23,0xbf,
+  0x73,0x15,0xec,0x7f,0x23,0x14,0x22,0xf6,0xbf,0x46,0xfc,0xff,0x72,0x04,0xc9,0x7f,
+  0x39,0xd2,0xd8,0x2e,0x68,0xb8,0x1f,0x30,0x09,0x01,0x5e,0x2e,0xe2,0x91,0x80,0xa2,
+  0x4e,0x2b,0x20,0x51,0x00,0x4f,0x13,0xf1,0xa7,0xc2,0x00,0xe4,0x59,0x35,0x63,0x64,
+  0x42,0x6f,0x31,0x8d,0xbc,0xb9,0x53,0x8f,0x6c,0x2f,0xd9,0x61,0x64,0x8d,0x74,0x33,
+  0xd4,0xd0,0x07,0x6d,0xcb,0xca,0x16,0xdd,0xe4,0x16,0xa7,0xd2,0x6f,0x5b,0x23,0xad,
+  0x3c,0x9e,0xca,0x9b,0x0f,0x7c,0x05,0x98,0x2a,0x22,0x64,0x34,0xf8,0xe9,0xbf,0x48,
+  0x7b,0x36,0x35,0xce,0x14,0xe9,0x5e,0xb0,0xd0,0x7e,0xcf,0x5e,0x06,0x00,0xe3,0x29,
+  0xea,0x0d,0x54,0x71,0x9a,0xac,0x90,0x49,0x01,0x98,0xe0,0x66,0x33,0x16,0x2c,0x6d,
+  0xd1,0x18,0x5e,0x20,0x57,0xc8,0x8e,0xb5,0x93,0x60,0x3e,0xfa,0x9c,0x20,0x13,0xfa,
+  0x09,0x95,0xa5,0xa6,0x8a,0xd4,0x6b,0xa4,0x5d,0x58,0xd3,0xac,0x05,0xad,0xeb,0x8b,
+  0x58,0x24,0x93,0x9b,0x88,0xbe,0x8d,0x38,0xcc,0x6e,0xa9,0xd0,0x46,0xea,0x0a,0x4f,
+  0xdd,0x28,0x0e,0xca,0xbd,0xa3,0xaf,0xb7,0x97,0xd6,0xec,0xcd,0xae,0x59,0x07,0xb3,
+  0x60,0xef,0xa4,0xcd,0xcc,0xa6,0x82,0xb1,0x14,0xaa,0x64,0xa7,0x2a,0x8e,0xff,0x37,
+  0x96,0xec,0x43,0x23,0x85,0x60,0x35,0x86,0xae,0x13,0xce,0x97,0x94,0xb4,0xd1,0xec,
+  0xa1,0x09,0xe0,0xfd,0x87,0xac,0xba,0x33,0x91,0xce,0x0d,0x1c,0x0b,0x60,0xed,0x7b,
+  0xd0,0x87,0x6b,0xb3,0xe9,0xfa,0xfb,0x74,0xcf,0xcd,0xf8,0x7f,0x69,0x2b,0x88,0x0d,
+  0x4b,0x15,0x58,0xb2,0x6d,0xeb,0x04,0xfc,0xfa,0x49,0xf2,0xdb,0xf8,0xc6,0x3f,0xc7,
+  0x2a,0x60,0x63,0x7c,0xfc,0x93,0x64,0x21,0xcb,0x07,0x18,0x9f,0x7d,0x60,0x76,0xf6,
+  0x63,0xb3,0x77,0x7e,0xf8,0x23,0xfb,0x9f,0xfe,0x83,0x13,0x00,0x43,0xb8,0xff,0x0f,
+  0x8e,0xc3,0x2c,0x35,0x70,0x0b,0xb3,0xae,0xa3,0x1a,0x00,0x72,0x00,0x34,0xd2,0x0d,
+  0x88,0xb4,0x01,0x5c,0x08,0x59,0x31,0x40,0x32,0x18,0xc8,0x18,0x89,0x02,0x3e,0x6d,
+  0x45,0x01,0xe2,0x94,0x0f,0x80,0x1b,0xeb,0x63,0x2b,0xd2,0x68,0x9a,0x39,0xdc,0x1e,
+  0x1e,0x76,0xfe,0xda,0xc3,0xed,0x36,0x7e,0x41,0xef,0x8c,0x42,0x4b,0x32,0x42,0x3f,
+  0x33,0x00,0x50,0xce,0x88,0x4d,0x2e,0x6f,0x65,0xd7,0xf8,0xad,0xd6,0xf9,0x92,0x27,
+  0x52,0xd9,0x8c,0x44,0xf8,0xda,0xff,0x14,0x3b,0xcb,0x44,0xc8,0xac,0xa1,0xfa,0xff,
+  0x92,0x38,0x4b,0xd6,0x1e,0xec,0x4f,0xe9,0x80,0x59,0xa8,0xe0,0xb9,0x54,0x57,0xb6,
+  0x3a,0x58,0x01,0x50,0xce,0x8d,0xba,0x1c,0x44,0xad,0x24,0x33,0xc3,0xec,0xf5,0xc2,
+  0x57,0xab,0x30,0x6c,0x68,0xcb,0x56,0x5f,0x65,0x5e,0x46,0x1b,0xee,0x72,0xc3,0xce,
+  0xd5,0x45,0x7f,0xc3,0x11,0x33,0x91,0x88,0x2d,0xcc,0x88,0xba,0x4d,0x54,0x9d,0xa5,
+  0x4c,0xa3,0x25,0xed,0x07,0x31,0x15,0xc1,0x9b,0xb4,0x8e,0xc0,0x7e,0xd8,0xef,0xd1,
+  0x01,0xa1,0xf7,0xa3,0xe2,0x00,0x60,0x35,0x6b,0x0c,0x38,0x7e,0xec,0x51,0xa3,0x6d,
+  0x1d,0xdf,0x70,0xc1,0xd9,0x0e,0x5a,0x48,0x1f,0xad,0x10,0x27,0xe5,0xb4,0x2e,0xec,
+  0x78,0x85,0x3f,0xc6,0xc0,0xbc,0xcb,0xaa,0xd3,0x6f,0x8c,0xdb,0x8d,0xe8,0x96,0x85,
+  0x75,0x85,0x6d,0x7c,0xda,0x8a,0xb1,0xb9,0xe2,0xe7,0xbc,0x30,0x82,0x69,0x89,0x1f,
+  0x79,0x10,0xdf,0x7c,0xc3,0x5a,0x60,0xdc,0xb1,0xd0,0xe3,0x8c,0x4f,0xe1,0xfe,0x6d,
+  0x50,0x32,0x6d,0x7f,0x61,0x6f,0xd1,0x6e,0xcf,0x9b,0xf6,0x0e,0xc9,0x72,0x25,0xb0,
+  0xc4,0x7f,0x12,0x3d,0xad,0x1d,0x20,0xc3,0x4f,0xaa,0xff,0xe3,0x88,0x0d,0xeb,0x6f,
+  0xf6,0xdb,0x1b,0x48,0x01,0x7c,0xe7,0x63,0x77,0x7e,0xec,0xc3,0xfb,0x9f,0xfe,0x83,
+  0x5c,0xed,0x89,0x10,0xee,0xff,0x73,0x4f,0x0d,0xc9,0xff,0xcc,0x7a,0xa4,0x6e,0x29,
+  0x00,0xe4,0x00,0xac,0x91,0x6e,0x40,0x43,0xf3,0xd5,0xdc,0xe5,0x0b,0x76,0x08,0x20,
+  0xd9,0xb5,0xfa,0x02,0x59,0xdd,0x81,0xa9,0x38,0xa0,0x9d,0x0e,0x3c,0x61,0xd6,0xc8,
+  0x74,0x1a,0x82,0x89,0xca,0x8c,0xc5,0x49,0xb5,0xc1,0x7e,0x8d,0xdb,0xef,0xc7,0x0a,
+  0x33,0x2d,0x92,0xdc,0xb3,0xc9,0x2d,0xef,0x88,0x68,0x89,0xe4,0xf0,0x20,0x49,0xc2,
+  0x15,0x00,0xae,0x70,0x26,0xec,0x05,0xe8,0x04,0x04,0xf7,0x3f,0x7e,0x17,0x6f,0x1b,
+  0x65,0xa1,0x69,0x01,0x19,0x4b,0xdb,0x66,0x91,0x85,0x52,0x23,0x59,0xdc,0x5f,0x47,
+  0xd4,0x58,0x8d,0xa7,0xb9,0x8d,0x97,0x64,0x4f,0x6f,0xb7,0x25,0x7a,0xa1,0x49,0x43,
+  0x43,0x15,0xe6,0xca,0xf2,0x4a,0x0c,0xc7,0xb6,0x98,0xe1,0x40,0xaa,0x25,0xf7,0xf8,
+  0x58,0x09,0xa4,0x37,0x19,0x67,0xae,0x92,0x7d,0xd1,0x92,0xed,0xc2,0x32,0x76,0x96,
+  0x84,0xae,0xb5,0x6a,0x31,0xed,0x2d,0x4b,0x61,0xbb,0xe2,0xd2,0xd8,0x06,0x93,0xb9,
+  0x51,0xb2,0x9a,0xed,0x3b,0x92,0xcc,0xcd,0x66,0x95,0xdd,0x26,0xb5,0x13,0xfc,0x3f,
+  0x4d,0xcd,0x0a,0x6b,0x1d,0x7e,0x71,0xc4,0xa7,0x08,0xb4,0xbb,0xf6,0xa9,0xb8,0x1b,
+  0x4c,0x27,0x73,0x9a,0xa1,0x55,0x90,0x53,0xb3,0xd6,0x10,0xdb,0x0b,0x0a,0x25,0x7a,
+  0xb3,0x72,0xb5,0xc9,0xfd,0x60,0xbf,0x3f,0x1e,0xc6,0xf2,0x35,0xee,0x54,0xc6,0x37,
+  0x88,0x49,0xa5,0x64,0x72,0xc3,0x09,0xbb,0x09,0x41,0x39,0x2f,0x0a,0x4f,0xd9,0x7f,
+  0xc7,0x79,0xb7,0x1d,0x74,0x4a,0x41,0xd0,0x72,0x3e,0xed,0x68,0x1b,0x5e,0x37,0xd8,
+  0x1f,0x9d,0x03,0xd8,0xa0,0x35,0xc4,0x86,0xe3,0xfc,0x6f,0x58,0x0e,0x3f,0x11,0x78,
+  0xfc,0x1b,0x31,0xfd,0xe3,0x0e,0x0f,0x8c,0x7f,0xe7,0x3b,0xdf,0xf9,0xd8,0xc7,0x3e,
+  0xf6,0xe1,0xab,0x31,0xff,0xc7,0xe6,0x81,0x54,0x31,0x47,0xe6,0xca,0x5e,0x28,0x6c,
+  0xa3,0xea,0x7f,0xbd,0x6e,0xd6,0xb1,0x02,0x68,0x17,0x70,0x08,0xf0,0x2c,0x69,0x03,
+  0xc0,0x0a,0x20,0xe4,0x54,0x01,0x48,0x33,0x00,0x19,0x12,0x10,0x27,0x03,0x32,0x71,
+  0xc0,0xa2,0x99,0x4d,0x58,0xd1,0x34,0xae,0x88,0xd2,0xd1,0x34,0xfa,0xed,0x28,0x32,
+  0x3b,0x24,0xfd,0x9e,0x8f,0x16,0x1f,0x70,0x17,0x89,0x0f,0xb7,0x2b,0x56,0x20,0x8b,
+  0x2b,0xc8,0xe5,0x28,0xbb,0xc9,0x12,0xbf,0xf5,0x09,0xc3,0x94,0xcc,0x7e,0x69,0xa8,
+  0xc3,0x94,0xcd,0x8a,0xe2,0x86,0xef,0x05,0x49,0xe2,0x9b,0x1b,0xd8,0xf6,0x2d,0x7c,
+  0x8a,0xff,0x0f,0xf1,0x21,0x03,0x29,0xad,0x4a,0x65,0x05,0xf7,0x04,0x60,0x23,0x10,
+  0x3b,0x13,0xa5,0x3e,0x6b,0xd3,0xbf,0xd3,0xea,0x27,0x3e,0x3c,0x8c,0xc7,0x2a,0x13,
+  0x6d,0x34,0xdd,0x57,0x89,0xde,0x66,0xd1,0xc0,0x75,0x9b,0x6d,0x71,0x2c,0xbe,0x82,
+  0x70,0x37,0x4a,0xb5,0xc8,0x4a,0x82,0xc4,0x0a,0x79,0xdf,0x62,0x5e,0x61,0x75,0x05,
+  0xb7,0x13,0xe1,0xea,0xa4,0x8c,0xac,0xdd,0x93,0x80,0x3b,0x4a,0xe9,0x34,0x45,0xe9,
+  0x96,0xa1,0xe1,0x61,0x93,0xcb,0x82,0x05,0x98,0xaa,0x73,0x2d,0x0b,0xbd,0x6e,0x02,
+  0x7b,0x40,0x87,0xc7,0x6d,0x41,0xb4,0xa4,0x16,0x0b,0x19,0x19,0x44,0xeb,0xd0,0x2c,
+  0x7a,0x33,0xee,0x35,0xb0,0x3b,0xe6,0x5f,0x78,0x88,0xdf,0x4f,0x8f,0x5b,0x5b,0xdb,
+  0xf0,0xc4,0x5b,0x0c,0x2b,0xb0,0x3a,0x81,0x0e,0x37,0xb8,0xff,0xdd,0x8f,0xae,0xde,
+  0xb0,0x57,0xb1,0x7c,0x0b,0xeb,0xb0,0x88,0x36,0x70,0xf8,0xf6,0x03,0xdf,0x7e,0x00,
+  0x29,0x80,0x07,0x1e,0x40,0xf2,0xff,0x1b,0x57,0x63,0x02,0x70,0xb5,0x7a,0xa6,0x78,
+  0x19,0xc9,0x7f,0xac,0x83,0xe4,0x1f,0xd9,0xff,0x3a,0xce,0x23,0xc7,0x6d,0x00,0x24,
+  0x0b,0x10,0x27,0x01,0xcc,0xcf,0xe1,0xa1,0x80,0xb0,0x07,0xf0,0x59,0xa2,0x00,0xc6,
+  0x9c,0x20,0x80,0xdd,0x21,0x30,0xee,0x36,0x06,0x86,0xf4,0xc5,0x15,0xf9,0xe8,0xaf,
+  0x71,0xe1,0x16,0x92,0x52,0x95,0x8d,0xd8,0x21,0x6a,0x7e,0x85,0x39,0xf7,0xbe,0x96,
+  0xc8,0x30,0xde,0x89,0xf7,0x66,0x2e,0xf2,0x53,0x59,0xd3,0x95,0x69,0x51,0xbf,0x94,
+  0x4a,0x19,0xd5,0x14,0xb2,0x65,0x9b,0xaa,0xc1,0xa4,0x97,0x27,0xf5,0x4c,0xab,0x46,
+  0x86,0x2c,0xe1,0x16,0x64,0x03,0xdb,0xfd,0x0a,0x5f,0x89,0x7d,0x8b,0x87,0x03,0xe9,
+  0xe0,0xf6,0xb7,0x04,0xf2,0xaa,0x1a,0x65,0x26,0xb8,0xad,0x17,0xf9,0xb5,0xe5,0x1a,
+  0x46,0xf8,0x2a,0xae,0xb5,0x71,0x8c,0x2e,0x22,0x73,0x96,0x28,0x11,0xf5,0xb6,0x16,
+  0x32,0x6a,0xf2,0xb6,0x8d,0xb6,0x38,0x8e,0x7b,0x42,0x6f,0x9d,0xc5,0xa9,0x92,0x82,
+  0x1b,0xee,0x76,0xf0,0x67,0x0e,0x54,0x18,0x05,0xca,0xfd,0x10,0x35,0xb2,0xd8,0xfe,
+  0x8b,0x4a,0xc7,0xcb,0x14,0x70,0x37,0x53,0xc2,0xd3,0xa7,0x18,0x9d,0xce,0x9a,0x64,
+  0x32,0xd0,0xa9,0xcd,0x14,0x7f,0x19,0xfc,0xdc,0x2f,0x67,0x31,0xe7,0xd8,0xbe,0x6c,
+  0x3b,0xec,0x96,0xdb,0xbd,0x71,0xe8,0xd4,0xd1,0x23,0x5f,0xff,0xc4,0x2b,0x77,0xbc,
+  0x72,0xdb,0xc9,0xc3,0x2f,0x1f,0xb2,0x7c,0xf4,0xf0,0x38,0x15,0xaa,0x97,0x35,0xd6,
+  0xf1,0x5f,0x6f,0x4c,0xdb,0xf9,0x39,0x8e,0x43,0xcf,0xd4,0x17,0xdc,0x76,0x7b,0x89,
+  0x07,0xb0,0xc1,0x54,0x30,0x48,0x7d,0xde,0xaa,0x49,0x38,0x9a,0x85,0xc8,0xbb,0xe5,
+  0x05,0x8c,0xb3,0xfc,0xf3,0xf1,0x6f,0x63,0x0d,0x80,0x55,0xc0,0x03,0x0f,0xbc,0x05,
+  0xc9,0xff,0xe3,0x53,0x57,0x81,0x56,0xaa,0x78,0x79,0x6e,0x92,0xc8,0xff,0xc5,0x75,
+  0xcb,0xfe,0x63,0x05,0x80,0xdb,0x00,0x32,0xab,0xd9,0x2d,0x9c,0x05,0x84,0x43,0x00,
+  0x97,0xec,0x2a,0x40,0x72,0xac,0x6b,0xd7,0x01,0x9e,0x76,0x7c,0x80,0x92,0xa3,0x02,
+  0x52,0x66,0x87,0xc8,0xbf,0x60,0x4d,0x9d,0x16,0x77,0x2e,0x69,0xb8,0x14,0xc3,0x09,
+  0x43,0xe8,0xf6,0x6f,0x72,0xed,0x05,0xcd,0xbc,0x77,0x77,0x27,0x8c,0x6c,0x1e,0x27,
+  0xd4,0x16,0xf8,0xbc,0x22,0xb3,0x28,0xfa,0xb1,0x54,0x69,0x9c,0x30,0x0c,0x59,0x16,
+  0x8a,0xe1,0xa4,0xbf,0x91,0x85,0x2c,0xf9,0x97,0x64,0x20,0x98,0x49,0xca,0xa9,0xa0,
+  0x8b,0xad,0xf7,0xe7,0xa7,0x14,0xf0,0x82,0x69,0xcd,0xe8,0x24,0xb6,0x12,0xb5,0xc5,
+  0xd5,0xb5,0x8b,0x24,0x06,0xe1,0x9d,0x5f,0x23,0xa5,0x48,0x57,0xa7,0x1a,0x52,0x4a,
+  0xe2,0x97,0x56,0x1d,0x5d,0xda,0xbb,0xc2,0xcb,0xe7,0x63,0x6a,0x2b,0xd8,0x14,0xa3,
+  0x7a,0x93,0xd0,0xfd,0x09,0x1d,0x41,0x9a,0xd9,0x09,0xde,0xe5,0x90,0xb9,0x42,0x32,
+  0xb7,0x84,0x96,0xdb,0x15,0xb9,0xac,0xd1,0xef,0x98,0x2a,0x40,0xd2,0x5c,0xc5,0xf6,
+  0x5f,0x68,0x75,0xc5,0x23,0x2a,0xb2,0x57,0xd4,0xfa,0x54,0x34,0xb6,0xd1,0x15,0x12,
+  0x67,0x35,0x9f,0x9a,0x62,0x1c,0x25,0x5f,0xff,0x9f,0xf3,0x4e,0xb0,0x4a,0x39,0x45,
+  0x24,0xc9,0x12,0xb4,0xe9,0x43,0xc7,0x8e,0xdf,0xe1,0xad,0xf0,0xe0,0x2b,0x27,0xee,
+  0x26,0x06,0x16,0x8b,0x97,0x6d,0x7c,0x65,0x48,0xbe,0xb5,0x6a,0xe6,0x96,0x97,0xbe,
+  0xb1,0x61,0x59,0xec,0x0d,0xf6,0x85,0xfc,0x64,0x3d,0x37,0xdc,0xf7,0x4e,0x26,0xaf,
+  0x67,0xe2,0x2d,0x23,0xef,0x46,0x19,0x36,0x78,0xb1,0xc7,0x82,0x8f,0x9f,0x48,0xf4,
+  0x91,0xf0,0x7f,0x7b,0xfc,0x81,0x1f,0x7b,0xe0,0x81,0x8f,0x62,0x07,0xe0,0x1f,0x37,
+  0x85,0x8b,0xb4,0x0f,0x68,0x56,0x07,0x80,0x2d,0x9c,0x8a,0x8b,0xe3,0x7f,0xa6,0xb9,
+  0x63,0x62,0x05,0xd0,0xd8,0x5e,0x23,0x1d,0x81,0x57,0x2a,0xf9,0xea,0x39,0xab,0x11,
+  0xc0,0x0e,0x02,0x22,0x15,0x40,0xb9,0x00,0xf1,0x67,0xf1,0xfc,0xc0,0x24,0x27,0x38,
+  0x6a,0x66,0x56,0xa4,0xd1,0x34,0x54,0xe2,0xa8,0x9b,0xe8,0xa9,0xf0,0x96,0x9e,0x38,
+  0x9b,0x5d,0x9b,0x11,0xe5,0xb4,0xe5,0x2c,0x56,0x52,0xc6,0x1a,0xed,0x7c,0x05,0xe7,
+  0x27,0xb4,0xcb,0xdc,0x44,0x1e,0x4b,0x5d,0xef,0xfe,0x53,0x26,0xcd,0xfa,0x26,0xbd,
+  0xd6,0x14,0x7b,0x96,0xa9,0x48,0xfe,0xf5,0x24,0xa5,0x84,0xd2,0x11,0x6d,0x65,0x4b,
+  0x96,0xf8,0xea,0xce,0xaa,0xe1,0xb5,0x6e,0xb2,0xd2,0x4f,0x9f,0x88,0xf7,0xe2,0x7e,
+  0x18,0x1b,0x36,0xb4,0x6c,0x67,0x71,0x55,0x2b,0x34,0x70,0xf3,0x26,0x7d,0x3d,0x96,
+  0x92,0xa5,0x92,0x22,0xae,0xcf,0x95,0x6a,0xfc,0x1d,0x55,0xae,0x71,0x1d,0xbd,0x91,
+  0xb0,0xea,0xe8,0x7c,0x65,0xa9,0xca,0x1d,0x81,0xb5,0x85,0x12,0x1e,0x3a,0xb1,0x26,
+  0x9b,0xdc,0xc8,0x35,0xc5,0xde,0x7e,0x2b,0x66,0x82,0xb4,0x15,0x0a,0x72,0x58,0xe3,
+  0x4e,0x95,0xba,0x26,0xde,0x55,0xf7,0xae,0x67,0xa9,0xab,0x67,0x56,0x62,0xc8,0xa1,
+  0x17,0xae,0xbd,0xd9,0x65,0x16,0x77,0x6e,0x5b,0xbc,0x61,0x92,0x36,0x12,0xde,0xfc,
+  0x37,0x2d,0x17,0xd0,0xbb,0xec,0xd2,0xa7,0x77,0x2f,0xbc,0x8b,0xf8,0x89,0x59,0x22,
+  0x68,0xdf,0x26,0x42,0x76,0xec,0x5e,0x5e,0x73,0xdc,0x71,0xe4,0xd4,0xb4,0x55,0xcd,
+  0xb6,0xa5,0x7c,0x5a,0xf2,0xa0,0x05,0xd4,0xfd,0xce,0xf1,0xd6,0xc7,0x9d,0xf5,0xd9,
+  0x97,0x0d,0xda,0xc8,0x8f,0xbb,0xee,0xfc,0xb7,0x3d,0x65,0x34,0x4e,0xef,0x74,0x83,
+  0x11,0x77,0xee,0x8d,0x2b,0xfc,0x98,0xbf,0xf9,0xf6,0x47,0x91,0x06,0x78,0xcb,0x03,
+  0xbf,0xf1,0x3b,0xbf,0x3c,0x75,0x15,0xd0,0x8b,0x64,0x00,0x10,0xdc,0xe1,0xac,0xdd,
+  0x40,0xf6,0xdf,0x7c,0xdc,0x34,0x49,0x08,0x60,0xbb,0x5d,0xc0,0x1d,0x81,0xb7,0x56,
+  0xf2,0x58,0x01,0x50,0x1e,0x40,0xd7,0x69,0x08,0x24,0xd9,0x80,0xd8,0x05,0x78,0x96,
+  0xf4,0x09,0x2a,0x45,0xcb,0x19,0x54,0xff,0x17,0x26,0xeb,0x45,0x25,0xee,0x19,0x6f,
+  0xc8,0x00,0xaf,0xe8,0x94,0x4a,0xa4,0xd8,0xe1,0xd1,0x3d,0xf9,0xdb,0xbf,0xe5,0x2d,
+  0x5a,0xaa,0x8d,0x24,0xf2,0x95,0x95,0xd8,0x2a,0x49,0x13,0x63,0xb6,0x8c,0x6a,0x00,
+  0xec,0x16,0xa9,0x37,0x43,0x4d,0x71,0xba,0x3c,0xdc,0x51,0x6e,0x6a,0xd4,0x6b,0xb0,
+  0x28,0x95,0xd2,0x33,0x05,0x92,0xf8,0x2e,0xcc,0x7c,0x69,0xa4,0xa4,0x62,0xed,0xf3,
+  0xa0,0x7f,0xb7,0x0b,0x65,0xb4,0x61,0x16,0xd6,0xb4,0x25,0x54,0xa7,0xd2,0x77,0xb8,
+  0x94,0xdd,0x85,0xae,0xe2,0xbb,0xb6,0x75,0xca,0x5e,0xa1,0xa7,0xba,0x59,0xd4,0xf4,
+  0x56,0x0c,0x77,0xad,0xd9,0xe4,0xef,0xe0,0x3c,0x23,0x51,0xee,0x4b,0x72,0xc4,0xf2,
+  0xc6,0x04,0xdd,0x56,0xee,0xb2,0x7b,0x42,0x2f,0xd5,0x91,0x2d,0x67,0x98,0x75,0x96,
+  0xd1,0x12,0x7f,0x74,0x8e,0xbc,0x89,0xa7,0x40,0xb4,0x75,0x64,0x81,0xd4,0xff,0x77,
+  0xf8,0x48,0x22,0x52,0xa8,0xac,0xa0,0xda,0x17,0x56,0x33,0xca,0xa6,0x6c,0xb4,0x60,
+  0xb5,0xc2,0x5c,0x54,0xff,0x6b,0x4f,0x2f,0x83,0xff,0x1f,0x1f,0x1f,0x77,0xe4,0xfb,
+  0x63,0x27,0xac,0x7e,0xe4,0xcf,0xbe,0xff,0xb6,0x7b,0xef,0xbd,0xf7,0x13,0xaf,0x58,
+  0x1a,0xe0,0xfd,0xb7,0xff,0xff,0xb4,0x5d,0x5d,0x6c,0x1b,0x57,0x76,0xd6,0x56,0x21,
+  0xb0,0x46,0x77,0x1d,0xba,0x7d,0x48,0x32,0x74,0x3a,0xe4,0x3e,0x71,0x28,0xaf,0x03,
+  0x84,0xae,0x90,0x05,0xd6,0xf6,0x26,0x70,0x01,0xd6,0x09,0x06,0x25,0x87,0xa4,0x4a,
+  0x86,0x90,0xf2,0xa0,0x84,0xf1,0xc2,0x09,0x5d,0x06,0xd8,0x20,0x25,0xca,0x32,0x0f,
+  0x42,0xe2,0xc2,0x02,0x48,0x20,0x05,0x6c,0x40,0x41,0x81,0x75,0x49,0x79,0x1f,0x2a,
+  0x19,0xa0,0x41,0xd9,0x4f,0x8b,0x05,0x96,0x30,0xd0,0xaa,0x04,0x0c,0x3e,0x11,0xf1,
+  0xb2,0x61,0x0d,0xd7,0x06,0xf7,0x61,0x1f,0x1a,0x89,0x16,0x07,0xa4,0x7b,0xce,0xb9,
+  0x77,0x7e,0x38,0x73,0x65,0xd1,0x8b,0xea,0xcc,0x90,0x73,0x67,0xe6,0xfe,0xcd,0xbd,
+  0xf7,0x3b,0xe7,0xdc,0x7f,0x52,0xba,0x59,0x1b,0x9b,0x50,0xfe,0x33,0xd5,0x5c,0xa0,
+  0x13,0x70,0x6d,0x9d,0xc9,0xf7,0xc9,0x63,0x3f,0x1f,0xde,0xf6,0x8a,0x54,0x7b,0xaf,
+  0x57,0xf4,0xc8,0xe4,0x00,0x80,0x7d,0x6f,0x1a,0xb1,0x1f,0x06,0xea,0x5c,0xf4,0x5d,
+  0xbc,0x78,0xf1,0xec,0x0b,0x2f,0xfc,0xa7,0x2b,0x91,0xfe,0x3f,0x48,0x9a,0xf3,0xac,
+  0x5d,0xbb,0xbc,0xb4,0x99,0x19,0x35,0x2a,0x34,0x1d,0x77,0x30,0x00,0x15,0xe0,0x08,
+  0xeb,0x04,0x5c,0x1d,0x61,0x27,0x20,0xb6,0x01,0xda,0x19,0x00,0x28,0x00,0x47,0xd9,
+  0x58,0x20,0xac,0x03,0xf0,0xc5,0xc1,0xe1,0x8c,0xcb,0x8d,0x4d,0xd6,0xf8,0xe3,0xc8,
+  0xcf,0x52,0x9c,0x0b,0x91,0xe2,0x64,0x7e,0x2d,0x91,0xd8,0x01,0xfd,0xdf,0x35,0xfc,
+  0xd6,0x66,0x31,0xa4,0xa7,0x96,0xaa,0xd5,0x28,0x8d,0xa6,0x99,0x94,0xa4,0x52,0x55,
+  0xb1,0x95,0x0c,0xe3,0xc2,0x1d,0x09,0x56,0x9a,0xdf,0x91,0x74,0x5d,0x5a,0xb4,0x39,
+  0x98,0x51,0x66,0x2b,0xa0,0xff,0x67,0xdd,0xf2,0x5f,0xf3,0xb8,0x3d,0x16,0x95,0x77,
+  0xce,0x47,0x5c,0xe1,0x17,0x8b,0x1e,0x55,0xeb,0xf5,0x56,0x64,0xb9,0xeb,0xde,0xec,
+  0xb2,0x9c,0xb4,0x00,0x5b,0x9c,0x74,0x3d,0xe9,0xfb,0x04,0x53,0x88,0xaa,0x51,0x6a,
+  0xa3,0x73,0xc9,0xe8,0xbd,0xa2,0xe5,0x91,0x0d,0xd5,0x71,0x79,0x75,0x13,0xea,0x36,
+  0xee,0xd1,0x95,0xdd,0xb8,0x15,0x00,0xbf,0x2e,0xeb,0x81,0x4d,0xa1,0xfc,0xaf,0xdb,
+  0xbe,0x69,0x22,0x10,0x11,0x2c,0x11,0xff,0xbd,0x2c,0xc9,0x7f,0x57,0x15,0x50,0xf3,
+  0x9b,0xd1,0xb3,0xfb,0xa4,0xcc,0xee,0x0c,0x44,0x2b,0x40,0x48,0x91,0xaa,0x19,0xbd,
+  0x29,0xc1,0xcf,0xfd,0x3f,0xd3,0x32,0xf0,0x75,0xe9,0xd7,0xa4,0xf3,0x7f,0xff,0xb5,
+  0x6f,0x2e,0x2d,0x78,0x17,0xde,0x5e,0xb8,0xf4,0xb3,0x53,0xc4,0x02,0xce,0xbd,0xf6,
+  0xe7,0x22,0xec,0x4d,0x4b,0x69,0x87,0xa0,0x9e,0xce,0x89,0x9b,0x44,0x1a,0x80,0xed,
+  0x01,0xa0,0x3f,0x1d,0x2e,0x00,0xfc,0x3b,0x9d,0x8b,0x17,0xef,0x9d,0xfd,0xea,0x85,
+  0xdf,0x1f,0xc2,0xec,0x1f,0xa4,0x11,0x6b,0x00,0x6c,0xff,0x34,0x55,0xd9,0x25,0xfd,
+  0x1f,0x57,0xea,0x18,0x50,0x0d,0xa0,0x42,0x8b,0x81,0x5e,0xd9,0x58,0xb2,0x18,0xc0,
+  0x2d,0x62,0x00,0xd8,0x11,0x68,0x6b,0x07,0xa4,0x49,0x01,0xcd,0xe6,0x18,0x32,0x1f,
+  0xe4,0xbf,0x7b,0x39,0x5d,0xd5,0x6f,0xf6,0x12,0x58,0x08,0x99,0xc1,0x01,0x43,0x28,
+  0x76,0x04,0xa3,0xc5,0x46,0xca,0x8c,0xb9,0xd2,0x90,0x92,0x55,0xab,0xac,0x2f,0x6d,
+  0x97,0x55,0x2b,0xad,0xd2,0xac,0x5d,0x56,0xcc,0xf2,0x49,0x38,0x34,0x4a,0x96,0x47,
+  0x16,0xac,0x9a,0x89,0x43,0x50,0x1e,0xf7,0xc6,0x2c,0x0a,0x86,0xdf,0xc3,0x28,0xc8,
+  0x7f,0xf7,0x92,0x45,0x52,0xce,0x8e,0xa6,0xa2,0xed,0xc2,0x5d,0xdb,0xa1,0xeb,0x2c,
+  0xd8,0x06,0xdf,0xd2,0x40,0x91,0xa2,0x4d,0xb8,0x1d,0x11,0xd9,0x89,0x6e,0x39,0x1d,
+  0x1a,0x71,0xda,0x87,0xd0,0xc2,0x9e,0x1e,0xc5,0x4d,0xc6,0xdd,0xca,0x52,0xb4,0x58,
+  0x2c,0xda,0x7d,0xe3,0xe7,0x1d,0xa8,0xdb,0xb4,0x49,0x15,0x77,0x38,0x18,0xf8,0x27,
+  0xbe,0x04,0x29,0x34,0x68,0x47,0x69,0xac,0x90,0x33,0xd1,0x82,0x8a,0xe0,0xcb,0x26,
+  0xbf,0xdc,0xfe,0x57,0x54,0x62,0xd9,0x4d,0xe1,0x4c,0x42,0xc9,0xe3,0x60,0x67,0xcc,
+  0x07,0xbf,0x2a,0xde,0xd5,0x58,0x8a,0x2c,0x59,0xb9,0x34,0x0d,0x19,0xfe,0x2a,0xdf,
+  0xb4,0x38,0x80,0x2e,0x7d,0x8a,0x60,0x7f,0xfd,0xfa,0xc2,0xdb,0xd8,0x8e,0xc6,0x20,
+  0x76,0xfc,0x4f,0x90,0x03,0x14,0x8f,0x2d,0x88,0xc5,0xef,0xb3,0x10,0xdc,0x72,0x21,
+  0xd4,0x7e,0x1e,0x84,0xfd,0x74,0x8b,0xfd,0xa5,0x5b,0x22,0x1b,0xfc,0x39,0x58,0x0d,
+  0xc3,0x01,0xd0,0x87,0x33,0xcc,0x84,0x7f,0xa7,0xe3,0xeb,0xbc,0xd3,0x79,0xf8,0xf0,
+  0xe2,0x57,0x87,0x31,0xfa,0x0f,0x49,0xbe,0x99,0xbb,0xbd,0xbc,0xb4,0xd7,0xe7,0x1d,
+  0x00,0x28,0xff,0xe1,0xe8,0x76,0x4b,0xd8,0x07,0xd0,0xc0,0x89,0x40,0x57,0x2c,0x0d,
+  0xe0,0x0b,0x5b,0x1d,0x80,0x31,0x00,0xde,0x17,0x88,0x34,0x1e,0x56,0x58,0x6f,0x8e,
+  0x33,0xf3,0xbb,0x09,0x71,0xa6,0x5d,0xd3,0xdb,0x0c,0xff,0xce,0xd1,0x22,0x29,0xdb,
+  0xd0,0x82,0x62,0x4d,0x2b,0x57,0x97,0x70,0x86,0x52,0x76,0xdb,0x59,0x03,0xd0,0x36,
+  0x92,0x22,0xac,0xe4,0x7a,0x3b,0xee,0x95,0x6c,0x50,0xfb,0x57,0xa5,0xbd,0x09,0xbb,
+  0x4a,0xaa,0x87,0x53,0x75,0x05,0x03,0xdf,0x17,0x0f,0x2a,0x6e,0x07,0x92,0x52,0xa3,
+  0xe5,0xcd,0x24,0xc9,0xbd,0x0d,0x2f,0x28,0x2e,0x07,0xbb,0x77,0xd2,0xd2,0x91,0x7e,
+  0xbf,0x2c,0xc2,0x7f,0x5b,0x6c,0x3f,0xc9,0xb5,0x31,0xd7,0xb7,0x3d,0x76,0xe7,0x46,
+  0x88,0x65,0x84,0xbb,0xad,0xa0,0x72,0x70,0x44,0x27,0x92,0x42,0x19,0xee,0x1a,0x53,
+  0x3a,0x26,0x59,0x09,0x32,0x54,0x81,0xb3,0x8d,0x88,0x7b,0x09,0x40,0xb4,0x2d,0x45,
+  0x6a,0x4e,0xaf,0xa7,0xa3,0xd7,0x17,0x5a,0x04,0xed,0xd6,0xf1,0xef,0x93,0xa8,0xff,
+  0x71,0xeb,0xdb,0x96,0x97,0x35,0xa4,0x13,0xd8,0x3e,0xfc,0x39,0x72,0x85,0xd7,0x18,
+  0xf2,0x5a,0x5e,0x31,0x78,0xdd,0x20,0x7d,0x5e,0x89,0xbf,0x0f,0x23,0xb0,0xaa,0xfa,
+  0x14,0xa9,0x74,0x2b,0xed,0x35,0x23,0x17,0xc6,0xb3,0xe5,0x65,0xd5,0xfe,0x02,0xa0,
+  0xbf,0x10,0x06,0xec,0xfb,0x7c,0x9d,0x7b,0xf7,0xde,0x79,0xf8,0xf0,0xe1,0x57,0x87,
+  0xa3,0xfe,0x63,0x0f,0x20,0xcd,0x00,0xc2,0x06,0xc0,0xf5,0xed,0x52,0xb7,0x3b,0xd0,
+  0x06,0x9a,0x8e,0x6b,0x3e,0x95,0x56,0x70,0x14,0x00,0xeb,0x04,0x58,0x9a,0xa3,0x46,
+  0xc0,0x1c,0xf5,0x03,0x62,0x47,0x20,0x70,0x00,0x3e,0x25,0xd0,0xe2,0x00,0xe3,0xd9,
+  0xe1,0x15,0xc4,0xbf,0x4b,0xe3,0xd4,0x3c,0x94,0x37,0x4d,0x73,0xc8,0x30,0xa7,0xdb,
+  0x47,0x32,0x57,0x32,0xa2,0x62,0x17,0xb4,0xc3,0x3a,0xde,0xeb,0x6d,0x2c,0x6d,0x50,
+  0x67,0xba,0xab,0xa9,0x48,0x1a,0xdd,0x72,0x96,0x50,0x45,0x59,0x2e,0x09,0xbf,0x53,
+  0xd2,0x4b,0x83,0x23,0x93,0x65,0x5f,0x49,0xc9,0x38,0xb8,0xd8,0xdd,0xa8,0xbe,0x53,
+  0x33,0x6c,0x88,0x8b,0xd9,0x34,0xf8,0x55,0xaa,0x84,0x7e,0xd1,0x22,0x9c,0x5a,0xcd,
+  0xe6,0xc1,0x94,0xbc,0x60,0x4e,0x0f,0xf4,0x47,0xa2,0xa1,0x72,0x65,0xbb,0x07,0x96,
+  0x39,0xd9,0xab,0x6c,0x52,0xdf,0xa6,0x6b,0x57,0x5f,0x8f,0xcb,0xef,0x9c,0x96,0x89,
+  0x0a,0xc7,0x0a,0xf7,0x92,0x4d,0x97,0x65,0xe7,0x67,0x4e,0xdc,0x64,0xb7,0x71,0x05,
+  0x74,0xf7,0x94,0x0e,0x21,0x43,0x6d,0x86,0xba,0xc2,0x25,0x4a,0xb1,0xed,0x26,0xf4,
+  0x7c,0x2c,0x92,0xdb,0x56,0x4e,0x71,0x34,0x2d,0xbc,0x85,0x8d,0x7d,0xd7,0xb9,0x98,
+  0x0f,0x33,0xe8,0x61,0xbd,0x7a,0xe1,0x6f,0x90,0x2f,0x9c,0x6e,0x71,0x9c,0xb7,0x0c,
+  0xb1,0x3c,0x71,0xf2,0x57,0xec,0xe0,0x00,0x45,0xa1,0xec,0xe5,0xa2,0x3a,0x6d,0x3c,
+  0xe7,0x27,0xf3,0xdc,0x10,0xf2,0xad,0xb4,0xe1,0x71,0xcb,0x16,0x06,0x37,0x18,0x66,
+  0x66,0x9f,0x6c,0xa4,0xcd,0x70,0xf0,0x2f,0xdc,0xe2,0xc2,0xbf,0x03,0xd2,0xdf,0xe7,
+  0xbb,0x07,0xf4,0xce,0xbd,0x87,0xbf,0x7f,0xe7,0x90,0xd4,0x7f,0x90,0x1f,0x34,0x02,
+  0xf8,0x0a,0x8d,0x00,0x86,0x0a,0xc0,0x00,0x08,0xeb,0x00,0x5d,0xb5,0xb4,0xbd,0x3b,
+  0x6c,0xac,0xa6,0xca,0xc4,0x00,0x50,0x03,0x60,0x03,0x81,0x68,0x41,0x90,0x38,0x2e,
+  0x0b,0xcc,0xe7,0x04,0x12,0x03,0x00,0x16,0x30,0xce,0xf6,0x50,0xfe,0xbb,0x87,0xa8,
+  0x22,0xf3,0x57,0xec,0x59,0xc5,0x4e,0x10,0x3b,0x65,0xb1,0xd8,0x19,0xde,0xb1,0xac,
+  0x29,0xca,0x9c,0x36,0xaa,0xe2,0xc2,0xda,0xb4,0xa8,0x8e,0xb3,0xf8,0xcb,0xb5,0x31,
+  0x1f,0x89,0x4c,0x25,0x55,0x51,0x6e,0xb5,0x35,0xf7,0x22,0xd9,0x3b,0x34,0x92,0x5d,
+  0x95,0xda,0xc9,0x89,0x88,0x28,0x23,0x39,0xda,0xaf,0x0b,0x16,0x00,0x8d,0x2c,0x59,
+  0xf6,0xac,0xf8,0x5a,0x17,0xeb,0x7b,0x14,0xeb,0xbd,0x19,0x63,0x6e,0x2b,0x19,0xd8,
+  0x37,0xcd,0xf5,0x45,0xa5,0xa8,0x58,0x5d,0xa7,0x07,0x95,0x75,0x6c,0x5f,0xfd,0x81,
+  0x9e,0x89,0x96,0xdd,0xbb,0x19,0x90,0xb2,0x64,0x8f,0x98,0x61,0x4a,0xce,0x0e,0x37,
+  0xdb,0xee,0xf5,0x4f,0x20,0x37,0xd6,0x8a,0x4e,0x07,0x9e,0xc1,0xe8,0x0a,0x1b,0x2b,
+  0xe8,0xec,0xb6,0x1f,0x63,0x92,0xd2,0x29,0x3c,0x9c,0xe9,0xc1,0x18,0xaa,0x20,0xd0,
+  0xc8,0x35,0xb7,0xeb,0xf1,0x65,0x55,0x9c,0x3a,0xb8,0x4e,0x68,0x02,0x33,0xd4,0x3e,
+  0xbe,0xe4,0x59,0xb0,0x37,0xa7,0xa3,0x28,0xff,0xd5,0x22,0xed,0xd9,0x7b,0x06,0xaa,
+  0x1b,0xaf,0x7c,0xfe,0xad,0xf7,0xf8,0xab,0xa7,0x7f,0xf1,0x0d,0x13,0xaa,0xde,0x85,
+  0xd3,0xa7,0x4f,0xbf,0xfa,0xe1,0xc2,0x6b,0xc0,0x00,0xfe,0x70,0xa9,0xc5,0xd4,0x6c,
+  0xaf,0xe8,0x08,0xd3,0x73,0xd4,0xc4,0x51,0x24,0xf3,0x67,0xc4,0x18,0x40,0x3f,0x47,
+  0xa3,0xf9,0x67,0x9e,0xde,0x82,0x97,0xfe,0xc2,0x4c,0x87,0x0f,0x33,0x9b,0x69,0xf6,
+  0x96,0xbc,0xb1,0x3c,0x32,0x7d,0x68,0x71,0x7b,0x2c,0xce,0x9c,0xd2,0xf0,0x8c,0x49,
+  0xff,0x8e,0x2f,0xcf,0xf1,0xff,0xf1,0x3b,0x0f,0x0f,0x4b,0xfd,0x07,0x1e,0x9f,0xcb,
+  0xd1,0x0e,0x00,0xf5,0x60,0x36,0x26,0x97,0xd4,0xc1,0x00,0x97,0x76,0x1d,0x20,0x03,
+  0xa0,0x61,0x40,0xc1,0x3a,0x54,0x01,0x36,0xf7,0x88,0x01,0x2c,0xae,0xe5,0xb0,0x11,
+  0x80,0x37,0x03,0x8e,0xe3,0x16,0x07,0xd8,0x02,0x0e,0x90,0x0c,0xca,0xd1,0xb6,0x68,
+  0x88,0xba,0x74,0xbb,0xd9,0x34,0x73,0xd3,0x40,0x09,0xdc,0x79,0xf4,0x3a,0x17,0x3b,
+  0xce,0x0e,0xc3,0x31,0x5a,0xa0,0x13,0xfe,0xe2,0x31,0x79,0xaf,0x5a,0xdd,0xdc,0xcc,
+  0xd4,0x1b,0xb1,0xd2,0xc0,0xb5,0x9e,0x47,0xa5,0xe6,0x4f,0xd2,0x48,0x44,0xa5,0xa9,
+  0x24,0x13,0x7b,0xb2,0xf0,0x23,0x77,0x1e,0x6b,0xaa,0xac,0xab,0x1e,0x5b,0x34,0xd0,
+  0xfb,0x80,0x8a,0x33,0x9f,0x04,0x03,0xdf,0xab,0x64,0xab,0x59,0x74,0x17,0x77,0x8a,
+  0xb9,0x52,0xbc,0xb3,0x58,0x23,0x5a,0x86,0x83,0xfe,0x26,0x0f,0x7c,0x56,0xab,0xee,
+  0x53,0xbe,0x23,0xd8,0xed,0xd2,0xe4,0xb8,0x66,0xc1,0x3c,0xfb,0xc4,0x58,0x2f,0x02,
+  0xfe,0x47,0x41,0xc1,0xec,0xaa,0x46,0x92,0xfb,0xa2,0x58,0xff,0x80,0x06,0x25,0x1b,
+  0x8b,0x92,0x28,0x76,0x75,0x83,0x2c,0x2a,0x66,0x1a,0x90,0xf7,0xc5,0x66,0x02,0x32,
+  0x22,0x23,0x1a,0x2b,0x34,0xd8,0xc3,0x15,0x1b,0xf6,0xa1,0xea,0x52,0x35,0x44,0x79,
+  0x64,0xa5,0x10,0x32,0x54,0xc2,0xbf,0xbb,0x25,0xd1,0xe9,0x7a,0xa3,0xdd,0x13,0xa9,
+  0xfe,0x40,0x7f,0x2f,0x69,0x8f,0xd5,0x78,0x93,0x25,0x8f,0x2d,0x19,0x9a,0x93,0x86,
+  0x26,0xcb,0xca,0xa6,0xf1,0x21,0xc8,0xa9,0xde,0x5c,0x20,0x98,0xa5,0x8f,0xbf,0x02,
+  0xd5,0xfc,0x33,0x00,0xb1,0x33,0x00,0xf6,0x3f,0x6b,0x21,0xd0,0x18,0x4f,0x38,0xf7,
+  0xb3,0x16,0xa9,0x06,0x6f,0xa1,0xbd,0x30,0x80,0xad,0xd5,0x6a,0x4d,0x22,0xb9,0xc5,
+  0x60,0x89,0x52,0xb9,0x80,0xb2,0xb9,0x65,0x81,0x98,0x1e,0x85,0x5b,0x84,0x75,0xf6,
+  0x82,0xec,0xe1,0xd9,0xe2,0x30,0x66,0x3c,0x00,0x19,0x48,0x81,0x9e,0xf0,0x0b,0xe2,
+  0x3b,0x6d,0xb0,0x8a,0x30,0xf7,0x8b,0x18,0x05,0x5a,0xa0,0x58,0x80,0x27,0xcc,0x40,
+  0xe0,0x07,0xe9,0x8f,0xe8,0x9f,0x9f,0x9f,0xbf,0x0f,0x04,0x0c,0xe0,0xb0,0xd4,0x7f,
+  0x9c,0x4b,0x7b,0x33,0xb4,0x3c,0xb7,0x11,0x28,0xd3,0x08,0xa0,0xae,0x0e,0xf8,0x1f,
+  0x3c,0x06,0x06,0xd0,0xed,0x96,0x4a,0x2b,0x96,0x06,0xb0,0x71,0xb9,0xb6,0xbc,0x78,
+  0x1b,0x1b,0x01,0x4c,0x15,0x80,0xe1,0x7f,0x4c,0x6b,0x03,0x21,0xa5,0xe4,0x40,0x3b,
+  0x95,0x75,0x8f,0xe6,0x94,0x96,0xa9,0x81,0x50,0xe1,0x65,0x1d,0x87,0x0c,0x60,0x9f,
+  0xa1,0xf2,0x05,0xc7,0xbf,0xbb,0xc3,0x30,0xde,0x6c,0xb2,0x7e,0x45,0x12,0x3e,0x35,
+  0x2d,0x85,0x4d,0x80,0x7d,0x9c,0x52,0xaf,0x0a,0x16,0xa9,0x2a,0x8d,0x6a,0x6b,0xb7,
+  0xbe,0xf4,0x27,0x42,0x4b,0xab,0xfb,0x2c,0x91,0x86,0x6d,0x7f,0xdb,0xb2,0x14,0x50,
+  0x78,0xf8,0x45,0x1a,0xbc,0xac,0x28,0x51,0xb5,0x1f,0x18,0x35,0xb6,0xdd,0xeb,0x55,
+  0xed,0x51,0xf0,0xcd,0x49,0x52,0xf8,0x89,0x9e,0xe4,0x70,0x7c,0x11,0x35,0xee,0xed,
+  0x60,0x0d,0xdf,0x79,0x60,0x15,0xc8,0xdd,0x06,0x61,0xa3,0xa8,0x62,0xf3,0x5e,0x39,
+  0xe8,0x80,0x08,0x83,0xb2,0x14,0x00,0x65,0xe9,0x0d,0x17,0xb3,0xac,0x8c,0x5d,0x11,
+  0x45,0x27,0x5b,0x20,0x8a,0xdb,0x75,0xd1,0x80,0xe1,0x65,0x7b,0xc0,0x98,0x12,0x8a,
+  0x5f,0x0d,0x82,0xfc,0x5f,0x17,0xee,0xdb,0xb5,0xff,0x96,0x23,0xf0,0x85,0xbd,0x24,
+  0xf9,0x60,0x7a,0xa8,0x64,0x90,0xa1,0x8a,0xd7,0x80,0x9f,0x5a,0x80,0x49,0x9a,0x2e,
+  0x05,0xb7,0x8a,0x46,0x6a,0xbb,0xd3,0xc8,0xba,0x70,0x53,0x91,0x0a,0x14,0xfc,0x8e,
+  0x01,0xe0,0x10,0x6d,0xa7,0x00,0xe2,0xa7,0x10,0x79,0xbf,0x05,0xc3,0x47,0xa4,0x53,
+  0xb7,0x8e,0xbf,0x09,0xe6,0x9f,0x83,0x82,0x7d,0x09,0x0c,0xc5,0xbf,0xe4,0x32,0x97,
+  0x41,0xce,0x41,0x5e,0x2e,0x95,0x6d,0x0f,0x00,0x96,0xec,0x99,0xd0,0x01,0xb1,0x80,
+  0x34,0x86,0x13,0x36,0xd8,0x86,0x69,0x93,0xf1,0x08,0x06,0xf1,0xb0,0xd7,0xf2,0x10,
+  0x0f,0x23,0x18,0xcb,0x6b,0xd6,0xe6,0x0f,0x2c,0xc0,0x07,0x74,0x81,0xe0,0xff,0xf4,
+  0x11,0x30,0x80,0xc3,0x18,0xfc,0xcb,0xa9,0xef,0x09,0x5d,0xab,0xd1,0x12,0x40,0xc3,
+  0x58,0x49,0xd5,0x41,0x01,0x40,0x42,0x0d,0x00,0x3b,0x01,0x70,0x26,0x40,0x3d,0x83,
+  0xeb,0xcb,0xd0,0x50,0x60,0x5c,0x11,0x8c,0x35,0x03,0x32,0x0e,0xc0,0xaa,0x01,0x47,
+  0xb1,0x25,0xe0,0x4e,0xa6,0x14,0x68,0x8b,0x98,0xbf,0x54,0x73,0xce,0x22,0x61,0x94,
+  0x38,0x92,0xea,0x0b,0xc5,0x8e,0xea,0x6f,0x9a,0x83,0x8b,0x80,0x9e,0x04,0x8f,0x04,
+  0xaa,0x1b,0xb4,0x47,0x69,0x05,0xfb,0xd3,0xd1,0xba,0x73,0x7e,0x99,0xae,0xaa,0xee,
+  0xae,0x71,0x4e,0x3b,0x6c,0xf6,0xa9,0xd6,0xf3,0x5b,0x63,0x96,0x98,0xcf,0x55,0xbd,
+  0x8d,0xfa,0xbf,0x73,0x7f,0x61,0xa8,0x14,0x59,0xa1,0x8b,0x29,0xa4,0xa7,0x32,0xa9,
+  0x8a,0x68,0xa5,0xeb,0xe9,0xa8,0xbc,0xf5,0x0c,0xcf,0x45,0x94,0xd3,0x46,0xe2,0xca,
+  0x52,0x6f,0x2c,0x8e,0xe8,0x88,0xa0,0x58,0xea,0x3a,0x53,0x65,0x67,0xc9,0x6e,0x8b,
+  0x9c,0xfa,0x71,0x9b,0x65,0x51,0x46,0x1c,0x44,0xf2,0x13,0x5b,0x36,0x21,0x45,0xf5,
+  0x7e,0xa0,0x9e,0x5d,0x79,0xd6,0x1e,0x70,0xcf,0x26,0xc8,0xab,0xc7,0x7a,0x37,0x52,
+  0x7d,0xce,0xd4,0x61,0xd1,0xb8,0xf3,0x12,0xa1,0x29,0x8c,0xe2,0xff,0x95,0xe3,0x20,
+  0xa5,0x5b,0x5c,0xfe,0x23,0xee,0x50,0xef,0x6f,0x7e,0x88,0x92,0xf7,0x34,0x32,0x85,
+  0x6f,0xc3,0xac,0xae,0xcd,0x40,0x3b,0x71,0x32,0x9a,0xb8,0x65,0xaa,0x81,0x71,0x9f,
+  0xb6,0xdb,0x33,0x4c,0xe1,0x96,0xa1,0x0b,0xd8,0xd8,0x82,0x69,0x2b,0x6d,0x59,0xb6,
+  0x33,0x90,0xf0,0xa4,0x81,0x49,0xfe,0x02,0xd4,0xfb,0x41,0xfa,0xcf,0xcf,0x5f,0xb8,
+  0x7f,0xe1,0xe9,0xfd,0x47,0xf7,0x1f,0x7d,0xfc,0xf1,0x7f,0x1c,0xca,0xe0,0x1f,0x46,
+  0xc3,0x1c,0xeb,0x01,0xac,0xe3,0x12,0x40,0x6a,0xf7,0x06,0xdf,0xa7,0x03,0xbb,0xaf,
+  0x64,0x1c,0x06,0x10,0xc4,0xc5,0x00,0x70,0x2e,0xd0,0xd2,0xe5,0xe5,0x65,0x6c,0x04,
+  0xa0,0x3a,0xc0,0xad,0x49,0x0e,0x30,0x4e,0x8e,0xc7,0x81,0x6e,0x3b,0x83,0x53,0xf5,
+  0x9d,0xdd,0x48,0x54,0xe2,0xa0,0xbc,0xd3,0xc4,0x41,0xfe,0xc3,0x4b,0x82,0x15,0x3b,
+  0xf7,0x68,0xb1,0x6e,0x82,0x65,0xa8,0x61,0x3f,0xa4,0xc6,0xf6,0xaa,0x7b,0x7b,0x9b,
+  0x26,0x03,0x78,0xae,0xca,0x10,0x4e,0xfa,0xd3,0xe5,0xf5,0x92,0x36,0x97,0xb4,0xf9,
+  0x89,0x71,0xd8,0x9a,0xd3,0xdb,0xed,0x91,0x68,0xfe,0x59,0x39,0xa9,0x58,0xf1,0xe4,
+  0xd7,0x2d,0xeb,0x81,0x82,0x75,0x97,0x7e,0x39,0xf8,0x47,0x40,0x86,0x53,0x2a,0x89,
+  0xe1,0x4f,0x5d,0xb4,0xb7,0x14,0x8f,0x36,0xea,0x0b,0xf1,0x2f,0xc7,0x15,0x91,0x3f,
+  0x5b,0x19,0xb5,0xdf,0xa6,0x85,0x13,0x9c,0x89,0xb5,0x61,0xda,0xdf,0xe2,0xf3,0xf1,
+  0xe2,0x72,0x16,0xe4,0xbf,0x60,0xac,0xd0,0x41,0xa4,0x7e,0x49,0x7e,0x19,0x89,0xa5,
+  0x28,0x7b,0x7a,0xa0,0xfd,0xd3,0xac,0xa0,0x41,0x65,0x6a,0x82,0xcc,0x02,0x19,0xe4,
+  0x21,0x0f,0xa7,0x48,0x1f,0x23,0x3b,0xc9,0xfc,0xcb,0x05,0xc0,0xd0,0x77,0x2d,0x42,
+  0xfd,0x6b,0xd8,0x8a,0x4e,0xa6,0x8f,0xbc,0xdf,0x01,0xbc,0x90,0x27,0xcc,0x9c,0x42,
+  0xa9,0xeb,0x5d,0x78,0x1d,0xd9,0x83,0x01,0xcf,0xb4,0xeb,0x34,0x11,0xcb,0xcf,0xb0,
+  0x01,0xd3,0xef,0xcc,0xd7,0x96,0xfa,0x1f,0x36,0xe5,0xbc,0x43,0x1f,0x48,0x0b,0x38,
+  0x00,0xab,0x06,0xa4,0xbf,0x6b,0xb1,0x7a,0x3e,0x36,0xf3,0xe3,0xf9,0x1d,0xeb,0xed,
+  0x43,0xf4,0x17,0x3a,0xd8,0xe7,0x07,0xf0,0x9f,0xbf,0x70,0xe1,0xc2,0xc9,0xfb,0x4f,
+  0x81,0x5e,0xfc,0xec,0xd1,0xc7,0x87,0x31,0xf7,0xd7,0x20,0xed,0x5a,0xee,0xf6,0x0f,
+  0xa8,0x07,0x00,0x2a,0x00,0xd4,0x03,0xa8,0xd1,0x6e,0x32,0xd4,0x09,0x20,0x63,0x23,
+  0x20,0xf6,0x02,0x04,0x90,0x01,0xcc,0xd5,0xae,0x91,0x0a,0xc0,0x7b,0x02,0x19,0x07,
+  0xe0,0x0c,0x60,0x3c,0x8e,0x02,0x9a,0xea,0x15,0x41,0xe6,0x6f,0xe0,0xba,0x61,0x40,
+  0x54,0xe2,0xb7,0x78,0xa9,0xdb,0x02,0xb1,0x93,0x05,0xf9,0x8f,0x53,0xd4,0x1c,0x0c,
+  0x43,0xf7,0x60,0xde,0xb3,0x05,0xc7,0xd1,0x80,0x13,0xc5,0x40,0x01,0xd8,0xbc,0xd2,
+  0xae,0xaf,0x56,0x7a,0xb8,0x64,0xfc,0xf4,0x5f,0xb7,0x83,0xbb,0x0f,0x74,0xb7,0x87,
+  0xbb,0x52,0x2a,0xce,0xc2,0x57,0x58,0x7b,0x25,0x06,0x51,0xd3,0xda,0xed,0xb2,0x60,
+  0xfd,0x99,0xc8,0x2a,0x0b,0x7c,0x4b,0x7c,0x82,0x37,0x1e,0x3d,0x85,0x70,0x74,0xf3,
+  0xae,0x29,0x29,0x38,0xa6,0x08,0x4c,0x79,0x40,0xa8,0x1e,0x75,0x15,0x13,0xcb,0x3d,
+  0x9f,0xbf,0xe4,0x57,0x84,0x8e,0x02,0x7a,0x5f,0x9c,0x1b,0x51,0xcb,0x4e,0x92,0xf2,
+  0x62,0x6b,0x2c,0x57,0xa0,0xfe,0x2f,0x18,0x2b,0x70,0x10,0x11,0xa3,0xde,0xe2,0x58,
+  0xc5,0xfc,0xad,0x6a,0x01,0x60,0xa8,0xb2,0xbb,0x42,0x35,0x1d,0x41,0x66,0x69,0x83,
+  0x92,0x2c,0x65,0xc7,0x2c,0x7e,0x82,0xcf,0x4a,0xda,0xfe,0x9d,0xc7,0x8f,0x00,0x46,
+  0xe9,0x70,0xc7,0xfb,0x4b,0x5c,0x06,0x08,0x51,0x9b,0x46,0xfd,0xff,0x2d,0x04,0x99,
+  0x97,0x9a,0xfd,0x3e,0x69,0x11,0xe6,0x90,0x2b,0xfc,0xa2,0xc5,0x54,0xf0,0xb0,0x9b,
+  0x38,0x2c,0x2d,0x4a,0x17,0x5a,0x05,0xb2,0xcb,0x14,0xf9,0x70,0x78,0x42,0x86,0x03,
+  0x96,0x0b,0x4c,0x84,0xb3,0xb6,0xfb,0x34,0x73,0x84,0xf7,0x05,0x8a,0x10,0x56,0xec,
+  0x0d,0x9f,0x99,0xa8,0x2f,0xf0,0xa0,0xd9,0x7b,0xb8,0x16,0x08,0xfb,0xd8,0xdf,0xdf,
+  0x29,0x74,0xf2,0xbe,0x7c,0x1e,0x85,0xff,0xd3,0xa7,0x27,0x4f,0x9e,0xbf,0xfa,0xf4,
+  0xc5,0x17,0x1f,0x3d,0x3a,0xb4,0xd6,0x7f,0xa4,0x4d,0xec,0x01,0xa8,0x52,0x0f,0x40,
+  0x0c,0x7b,0x00,0x70,0x6b,0x26,0x89,0x18,0x00,0xcd,0x05,0xc4,0x1d,0x01,0x52,0xa3,
+  0x72,0xfb,0x77,0xd4,0x0d,0x00,0x75,0x80,0xdb,0x6b,0x6b,0x37,0x71,0x3e,0x80,0xc9,
+  0x01,0x40,0x09,0xc0,0xb6,0x80,0x4d,0x3d,0x03,0xf5,0x7f,0xc1,0x92,0x73,0x7d,0xde,
+  0x46,0x68,0x10,0x33,0x6d,0xf9,0x7b,0x95,0x7e,0x39,0x25,0x98,0x7e,0x33,0xc8,0xa1,
+  0x1d,0xb0,0xf5,0x26,0xb7,0x1d,0x0f,0xea,0x19,0x54,0x00,0x70,0x9f,0xa2,0xca,0x4a,
+  0x49,0xb8,0x6b,0xd0,0x7e,0xf4,0xf8,0xf1,0x40,0x95,0xd7,0x2b,0x7a,0xc9,0x63,0x06,
+  0xaf,0x18,0x51,0xa8,0x0d,0x32,0x38,0xb2,0xd8,0x3d,0xf0,0xad,0x71,0x94,0xac,0x4c,
+  0x9e,0xd6,0x91,0x4c,0x26,0xf4,0xd5,0xfe,0x48,0x24,0x8e,0xa7,0xa4,0xca,0xd8,0x4c,
+  0x90,0xad,0xa9,0x8e,0x84,0x1a,0x24,0xf9,0xef,0xaa,0xa3,0x77,0x13,0x49,0x51,0x44,
+  0x93,0xc4,0x8d,0x45,0xb9,0xd1,0xb6,0xe5,0x03,0x1c,0x5b,0x5b,0xc9,0x78,0x6c,0x57,
+  0xac,0x88,0x1d,0x44,0x37,0x3c,0xec,0x2b,0xcc,0xac,0x5d,0xd2,0x70,0x4d,0xe7,0x9e,
+  0x63,0xb9,0xd6,0x69,0x49,0x8a,0x68,0xb8,0xe1,0x80,0x2a,0xd5,0xec,0xe5,0x64,0x32,
+  0x91,0xec,0xa7,0xf5,0x98,0xe8,0x57,0x1f,0x20,0x8a,0xc2,0xe1,0x1f,0xff,0x61,0x66,
+  0xe6,0x27,0x67,0x09,0x50,0x67,0x08,0xff,0x80,0xde,0x0f,0xce,0x81,0xe9,0x55,0x14,
+  0xb9,0x00,0xb5,0x4b,0x4d,0xe2,0x0a,0x4c,0xe0,0x0a,0x18,0x40,0xb8,0x20,0x7a,0x5c,
+  0x98,0xb8,0xb8,0xde,0x15,0x1c,0x76,0x0a,0xb6,0x77,0xec,0x7d,0x61,0xc2,0x63,0x66,
+  0x48,0xdb,0x1c,0x81,0xe6,0xef,0x2b,0xa0,0xe6,0x4f,0xc2,0xff,0xfe,0xc9,0xa7,0x57,
+  0x9f,0x9e,0xbf,0x7a,0xfe,0xfc,0xf9,0x17,0x1f,0x1d,0xce,0xd8,0x7f,0x83,0x86,0xd8,
+  0x03,0x70,0x99,0xcf,0x01,0x56,0xb1,0x05,0x90,0x76,0x69,0xc3,0x6e,0x00,0x9c,0x09,
+  0xb0,0xc2,0x34,0x80,0x1f,0xb6,0xfb,0xd1,0x0d,0xea,0x08,0x64,0x2a,0xc0,0xcd,0x2f,
+  0x0c,0x1d,0xe0,0x4b,0xde,0x1b,0xf0,0x3d,0xbd,0x8c,0xa3,0x74,0xdc,0x12,0x27,0x33,
+  0x4e,0x8a,0x28,0xbe,0x3b,0xc4,0xbd,0xb2,0xdc,0x9d,0x7a,0x5a,0xc8,0x61,0x73,0xec,
+  0x91,0x55,0x08,0x7c,0x73,0xb3,0x8f,0x0c,0x00,0xf7,0xc1,0x98,0x46,0x54,0xa1,0x0d,
+  0xa8,0xfa,0xdf,0x50,0xb7,0x87,0x59,0x55,0xaf,0x61,0x24,0x68,0xcc,0xd2,0x1d,0xd3,
+  0xdf,0x65,0xad,0xdc,0x1e,0x09,0xd6,0x9f,0x8a,0x0c,0x9f,0x4c,0x5a,0x74,0x51,0x42,
+  0x6d,0x04,0xca,0x82,0xe5,0xc5,0xa7,0xa5,0x5e,0x7c,0x7f,0xbf,0xc5,0x01,0xca,0x59,
+  0xc8,0x20,0x41,0x85,0xa3,0x7b,0x53,0xec,0xa0,0xca,0xf1,0xef,0xca,0x8d,0xb2,0x95,
+  0x1b,0xfc,0x03,0xc7,0xb3,0xb1,0x3e,0xc9,0x7f,0x2d,0xf2,0xec,0x3d,0x86,0x9d,0xa4,
+  0xe5,0xd0,0xb9,0x0d,0xa6,0x35,0x2d,0xd3,0x1e,0xe1,0xc2,0xa7,0xcf,0x99,0x2a,0x94,
+  0x55,0xa4,0xa9,0xc9,0xbd,0x75,0x2d,0x36,0x65,0xe2,0x98,0x01,0xbf,0x49,0xdf,0x72,
+  0x8c,0x35,0x9d,0x87,0x3f,0x44,0xf5,0x9f,0x44,0x6a,0xe7,0x0c,0x29,0xfd,0x85,0x30,
+  0xb5,0x08,0x7e,0xff,0x2c,0xd6,0xae,0xc3,0x9d,0xc2,0xd9,0x7f,0x9b,0x99,0xf9,0xb4,
+  0x05,0x70,0x2b,0x74,0xc0,0x96,0x80,0xc2,0xae,0xc7,0x61,0xfe,0x14,0x9d,0xd3,0xdb,
+  0xc9,0xd3,0xe4,0x01,0x78,0xd3,0x29,0x98,0x60,0x67,0xa6,0x8e,0x93,0x1f,0xf0,0x87,
+  0x1d,0xce,0x37,0xf0,0xbd,0x0f,0x6e,0xf3,0x1d,0x42,0xff,0xbd,0x0b,0xf3,0xf3,0x4f,
+  0x4f,0x82,0xf0,0xbf,0x0a,0x74,0xf7,0xfc,0xf9,0x7f,0x79,0x74,0x78,0xad,0xff,0x48,
+  0x52,0xd5,0x13,0xba,0x36,0xb7,0x61,0x28,0x00,0xd4,0x02,0x48,0xf0,0xd7,0x06,0x37,
+  0x78,0x15,0x80,0x86,0x02,0x67,0xfa,0x51,0x6c,0x04,0x00,0x06,0xb0,0x68,0x71,0x00,
+  0x6c,0x07,0xe0,0x5a,0xc0,0x92,0x56,0x2e,0xd7,0x69,0xd5,0xdb,0x89,0x12,0xb4,0x13,
+  0x19,0x19,0x2d,0x04,0xe3,0x3b,0x47,0xe1,0x72,0x94,0xfe,0xc7,0xc9,0xf8,0xb0,0x17,
+  0xc0,0x6a,0xa7,0x63,0xfa,0x0d,0x28,0x81,0xd7,0xd0,0x22,0xfe,0xd0,0x22,0x3a,0x18,
+  0x2f,0x1f,0xe9,0x45,0x71,0x4d,0xfc,0x7e,0xa6,0x8c,0x2b,0x95,0x74,0x07,0x9a,0x60,
+  0x60,0x9d,0x93,0x76,0x68,0xfb,0x3a,0x75,0xa5,0x12,0xec,0x69,0xed,0x78,0x92,0xfc,
+  0x42,0xef,0x78,0x7d,0xe5,0xce,0xd1,0x45,0xbd,0x4e,0xf2,0xdf,0xdd,0x03,0x49,0x4b,
+  0x1d,0x8c,0xf7,0xa3,0xe4,0xd8,0xaf,0x56,0x68,0x81,0xbf,0x3f,0x56,0xfe,0xf7,0xfc,
+  0x18,0x97,0x3b,0xfb,0x86,0xe0,0x0a,0xf1,0x16,0xe0,0x1f,0x19,0x8e,0x9b,0x59,0xe6,
+  0x04,0xd6,0x21,0xea,0x4b,0x00,0x45,0xc8,0x0d,0xe7,0x0a,0xa8,0x91,0x48,0xdd,0x08,
+  0xf7,0x28,0xff,0x25,0x9f,0x64,0xe5,0x00,0x6e,0x5a,0x28,0x6a,0xff,0x7f,0x06,0x41,
+  0x46,0x2d,0x52,0x1e,0x99,0x27,0x31,0x54,0x61,0x82,0x4e,0xe1,0x1b,0x4e,0xcf,0xec,
+  0x96,0x76,0xb3,0xb2,0x54,0xc3,0x14,0x4e,0x26,0xa7,0x48,0x16,0x23,0x60,0x28,0x52,
+  0x77,0x7e,0xf5,0x3e,0x87,0xd5,0x75,0xc0,0xfa,0x4b,0x0c,0x68,0xaf,0xa2,0xfc,0x5f,
+  0x38,0xfb,0xed,0xfb,0x20,0xfe,0x8b,0xd7,0x5b,0x34,0xaa,0x06,0xde,0xbc,0x85,0x0d,
+  0x00,0x85,0x0e,0x47,0x65,0x87,0xc6,0xda,0x84,0x59,0xc3,0x3b,0x5e,0x09,0x90,0xcc,
+  0x40,0x0c,0xa3,0xc3,0x9d,0x75,0x38,0xf8,0x99,0x0b,0xfb,0x81,0xe1,0x1a,0x2f,0x0a,
+  0xdc,0x41,0x81,0xdc,0xa2,0x4e,0x4f,0xa2,0x1d,0x1e,0xf8,0x38,0x47,0xe8,0x30,0x16,
+  0x01,0xa7,0x0f,0x71,0x1f,0x46,0xf4,0x77,0x68,0xb4,0x1f,0xc0,0xff,0x02,0x08,0xff,
+  0x93,0x27,0x39,0xf8,0xaf,0xde,0xbd,0x7b,0xfe,0xee,0x67,0x77,0x0f,0x55,0xfd,0x8f,
+  0x44,0x76,0x73,0x21,0x63,0x11,0x20,0xde,0x05,0x48,0x0a,0x00,0xd6,0x01,0x74,0x63,
+  0x39,0x10,0xea,0x07,0x6c,0xf7,0x37,0x37,0x4c,0x0e,0x90,0xcb,0xb1,0xae,0x80,0x84,
+  0xc1,0x01,0xe6,0xb0,0x4d,0xfc,0xaf,0x51,0x9a,0x4a,0xb4,0xd2,0xae,0x44,0x5d,0x60,
+  0x50,0x10,0x52,0x71,0x61,0xe6,0xc5,0x67,0x7b,0x6d,0x3e,0xaa,0x8f,0xed,0x56,0xbd,
+  0xc3,0x87,0x83,0x62,0x01,0x70,0xda,0xad,0x6a,0xb3,0xd1,0xcd,0xcd,0xe8,0x95,0x00,
+  0x6e,0x55,0x3a,0x8c,0xa9,0x5d,0xb6,0x3f,0x36,0x95,0x1c,0x77,0x59,0xa2,0x53,0xc2,
+  0x3d,0x27,0x55,0x79,0x37,0x1b,0x1c,0x3e,0x4e,0xf9,0x45,0x31,0x08,0xe9,0xa9,0x76,
+  0x9d,0xa4,0xb8,0xb4,0x13,0x31,0xe2,0x80,0xd7,0x6d,0xa1,0x75,0x1b,0xf9,0xe5,0x21,
+  0xc0,0x71,0x9d,0x46,0xba,0xd1,0x3e,0xd6,0x6c,0xf7,0x6d,0x6b,0x9b,0x73,0x63,0x3b,
+  0x6e,0xfe,0x2f,0x39,0xcc,0x72,0x62,0x8a,0xd2,0x3d,0x11,0x60,0x6f,0x68,0x6e,0xe8,
+  0x61,0xdb,0x3c,0x5b,0x8a,0x3c,0x0e,0x09,0xed,0x1f,0xad,0x69,0xa0,0x8d,0x61,0xdb,
+  0x86,0x24,0x49,0xf6,0xd8,0x45,0x82,0xae,0xdc,0x78,0x92,0x92,0xdb,0x99,0x54,0x45,
+  0x66,0x39,0xe7,0xfc,0x8c,0xc9,0xc8,0x5b,0x06,0xb4,0xb9,0xe8,0xf0,0x69,0x51,0x1b,
+  0xb5,0x8d,0xa9,0x9a,0x3b,0x96,0x0b,0xee,0x68,0xc7,0x91,0x50,0x11,0xea,0x3c,0x65,
+  0x7b,0x82,0x63,0x83,0x73,0x57,0x96,0x87,0x0d,0xc8,0x2b,0x71,0x71,0x79,0x16,0x21,
+  0x1b,0xfb,0xab,0xb3,0x88,0x36,0x5f,0x07,0x85,0x7e,0xf1,0xc3,0xb0,0x0f,0xa1,0x87,
+  0xf2,0xbf,0xf9,0xe9,0xeb,0x6c,0xf2,0xdf,0x4f,0x8e,0xbd,0xe4,0x45,0x88,0xfb,0xc2,
+  0xc7,0x66,0x66,0xce,0x1d,0xa7,0x01,0x76,0xe0,0xc0,0x40,0xb9,0x8f,0x80,0x88,0xa7,
+  0x0f,0xbb,0xdf,0xf1,0x81,0x0f,0xa1,0xec,0x0b,0xb3,0x46,0xf9,0x4e,0xc7,0x40,0xb6,
+  0x71,0x74,0xf8,0xbd,0x79,0xe5,0xaf,0x39,0xf7,0x30,0xd8,0x06,0x31,0x92,0x4e,0x87,
+  0xb3,0x03,0xae,0x09,0xf0,0x1b,0x1c,0xe5,0x1b,0xce,0x63,0x98,0x28,0xf9,0x7d,0xa0,
+  0xf7,0x43,0xc5,0x9f,0xc3,0xff,0xe5,0xab,0x27,0x4e,0xdc,0x3d,0x71,0xf7,0xfc,0x67,
+  0xff,0x7c,0xb8,0xf0,0x8f,0x44,0xf6,0x72,0xb4,0x0b,0x90,0xd9,0x05,0x48,0x0d,0x00,
+  0x6c,0x8f,0x6e,0x6c,0x04,0x2c,0x6d,0xe3,0xbe,0xc0,0x41,0x6c,0x04,0x08,0x44,0xf7,
+  0x36,0x96,0xe6,0x0c,0x0e,0xb0,0x76,0xd3,0x43,0xe3,0x01,0x12,0x7e,0x54,0x03,0x6a,
+  0x83,0x14,0xc8,0xff,0x18,0x62,0x82,0x46,0xbe,0x9b,0x94,0x75,0xa2,0x89,0x65,0xb0,
+  0x3f,0x08,0x62,0x27,0x55,0xd9,0xc6,0x3d,0x40,0x69,0x87,0x70,0xd3,0xc1,0x92,0xa0,
+  0xfc,0x47,0xb5,0x6c,0x14,0x15,0x80,0x40,0xbb,0x5e,0x6f,0x54,0x30,0x9a,0xc8,0xa2,
+  0xf6,0xef,0x9c,0x26,0xf4,0xeb,0xa5,0xed,0x61,0x63,0xb5,0xa2,0xcd,0x7e,0x01,0x41,
+  0x52,0x43,0xe5,0x93,0xf1,0xd8,0x6c,0xb0,0x1c,0x87,0xba,0xab,0x6d,0xda,0x81,0x46,
+  0x9b,0x8c,0xf1,0xce,0x81,0xf0,0xf4,0xf7,0x76,0x03,0xc8,0xbb,0x70,0x4b,0xce,0xe7,
+  0x26,0xe0,0x19,0xaa,0x67,0x6c,0x8f,0xc8,0xc1,0x74,0xab,0x87,0xcc,0x72,0xb8,0xdd,
+  0xd5,0x9c,0xbe,0x2d,0x8b,0x1d,0xd4,0x08,0x8a,0x3d,0x6a,0x2c,0xb1,0xa7,0x6f,0x64,
+  0x18,0x77,0xe2,0x2b,0x9e,0x52,0xa9,0x6b,0x85,0x78,0xea,0x54,0xf1,0x47,0x42,0x8c,
+  0x2f,0x3b,0xbc,0x0a,0x69,0x75,0xd0,0x22,0x77,0x6d,0x81,0x3e,0x93,0x34,0xe3,0x82,
+  0x8d,0x4d,0x2a,0xb0,0xea,0x4a,0x30,0xa8,0xab,0xa4,0xd0,0x18,0xc3,0xcb,0xa6,0x23,
+  0x1c,0x8f,0xfe,0x12,0xa2,0x19,0x65,0xeb,0x6f,0x19,0xba,0xb9,0xd1,0x4e,0xc5,0x8f,
+  0xfe,0x1b,0x65,0x2f,0xb2,0x85,0x73,0x1f,0xc0,0xb5,0x43,0xa8,0x46,0x00,0x76,0xf2,
+  0x28,0x9f,0x41,0x03,0x2f,0xf8,0x8c,0xc7,0xfc,0x2c,0xe0,0x73,0x78,0x8d,0xef,0xc3,
+  0x93,0xcf,0xad,0x1b,0x46,0x86,0x91,0x14,0x08,0x88,0x0d,0x3a,0xe0,0x21,0x58,0x3c,
+  0x80,0x98,0x0b,0x3c,0xc5,0x40,0x59,0xd8,0x06,0xf8,0xb1,0xde,0x3f,0x7f,0xe1,0x29,
+  0x97,0xfd,0x27,0x80,0xde,0x3d,0xf1,0xf2,0xcb,0x77,0xcf,0xff,0xef,0x3f,0x1c,0x36,
+  0xfe,0xe5,0xd0,0xda,0x35,0x63,0x15,0x40,0xea,0x02,0x60,0x9b,0xb3,0x33,0x0d,0x00,
+  0x47,0x02,0xe2,0x6c,0xc0,0x2c,0xd5,0x01,0x40,0x05,0x30,0x38,0xc0,0x6d,0xa8,0x05,
+  0xe0,0x78,0x20,0xae,0x05,0x24,0x6a,0x7a,0x30,0x93,0x6a,0xac,0xcb,0x6c,0x12,0xa1,
+  0x86,0x33,0x09,0x34,0xbc,0x48,0x43,0x56,0x3f,0xc0,0x46,0x82,0x89,0x2b,0x16,0xbb,
+  0x7a,0x76,0xa5,0x64,0x39,0xa0,0xa1,0xc7,0xda,0xce,0xf7,0xe2,0x6e,0xf2,0xb7,0xb5,
+  0xd9,0x3e,0x28,0x00,0xd1,0x00,0x38,0x5a,0xa5,0xd5,0x4a,0x74,0x4d,0xb4,0x83,0x7c,
+  0x84,0x84,0x0b,0xa1,0x1f,0x85,0x7f,0x23,0x95,0xd5,0x86,0x39,0x33,0xcc,0x27,0x76,
+  0x3f,0x73,0x7a,0x03,0x1b,0x14,0xb6,0x55,0x5d,0x1f,0x50,0xf0,0x74,0x82,0x59,0xf7,
+  0x08,0x62,0x30,0x11,0x9b,0xe1,0x36,0x40,0x06,0x98,0x5d,0x17,0x62,0x8c,0x73,0xa6,
+  0xe8,0x03,0x28,0xfe,0xe8,0x09,0xbb,0xb5,0x9f,0xe4,0x35,0x37,0x62,0xba,0xe4,0x0e,
+  0x08,0xc0,0x15,0xe0,0x2c,0x05,0xc8,0x13,0x8b,0x05,0x81,0xc1,0x6a,0x52,0x4d,0xec,
+  0x60,0x59,0xab,0xb7,0x47,0xc1,0xf5,0x6d,0x95,0x5b,0xd5,0xd8,0x17,0xea,0x52,0x2f,
+  0x31,0x76,0xda,0xcd,0xe8,0x98,0x11,0xbb,0x25,0x55,0xbb,0x31,0x60,0xa4,0xd9,0xbe,
+  0xc4,0x1e,0xf3,0x81,0x99,0xb5,0x78,0x23,0x55,0xe3,0x56,0xa6,0x22,0x85,0x34,0x64,
+  0xa8,0x15,0x6a,0x45,0xd6,0x79,0x24,0xd1,0x8d,0x3e,0xe0,0xf7,0x46,0x6a,0x98,0x19,
+  0x0e,0xb9,0x84,0xd3,0x4d,0x54,0x1c,0x6e,0x0e,0xb5,0xcc,0x94,0xaa,0xcd,0x91,0x4f,
+  0xae,0x38,0x3e,0x8b,0x90,0x5b,0xfc,0xcf,0x59,0x6a,0x3c,0x03,0x05,0x80,0xd0,0x4d,
+  0x26,0xdf,0x19,0x63,0xe6,0xf9,0xcc,0x39,0xc6,0x01,0x8e,0x61,0x2d,0xbb,0xf3,0x23,
+  0xd4,0x10,0x18,0xd8,0xf1,0xe8,0x98,0x3f,0x3a,0xf8,0xc3,0x3c,0x36,0xc5,0xd3,0x41,
+  0xb8,0xce,0x23,0x5a,0xf1,0x04,0x6e,0xe0,0xe3,0x17,0xeb,0xcf,0x78,0x80,0x76,0xf3,
+  0x78,0x63,0xd9,0x60,0x46,0x84,0x39,0xfc,0x00,0xf0,0x05,0x54,0x2c,0x38,0x53,0xe1,
+  0x3a,0xbf,0x6f,0xde,0x77,0x81,0x64,0xff,0xfd,0x93,0x17,0x2c,0xf4,0x9f,0x78,0x00,
+  0x1c,0xe0,0xe5,0xaf,0xbf,0xfe,0xa7,0xc3,0x86,0x7f,0x24,0xd2,0x06,0x05,0x60,0xc9,
+  0x6a,0x01,0xd0,0x09,0x59,0x08,0x7f,0x89,0x0f,0x05,0xc6,0x6e,0x00,0xdc,0x18,0x10,
+  0x54,0x80,0x7e,0x94,0x2a,0x01,0x97,0x97,0x91,0x03,0xac,0x85,0xd6,0x72,0xb9,0x9b,
+  0xc8,0x01,0x3c,0x89,0x65,0x3d,0x58,0x1e,0xe1,0x3e,0x22,0xa5,0x92,0xfa,0x06,0xee,
+  0x59,0xaf,0xca,0x2a,0x92,0x26,0x27,0x38,0x03,0xf0,0xd3,0x69,0x16,0xe9,0x91,0x9a,
+  0x21,0x07,0x32,0x38,0x28,0xbd,0x81,0x9b,0x8f,0xa0,0xbb,0x92,0x2e,0x45,0x27,0x4a,
+  0x3e,0xbf,0x26,0xda,0x5a,0x2c,0x10,0xbd,0xd2,0xc7,0x9d,0x31,0xa1,0x0e,0x40,0xeb,
+  0x95,0xe2,0x68,0x45,0x10,0xd7,0x5c,0xdb,0x8c,0x30,0x8d,0x13,0xab,0xfd,0xc8,0xb7,
+  0x4a,0x25,0xea,0xba,0x18,0x6a,0xc3,0x90,0xdf,0x1e,0xae,0x45,0x39,0x75,0xb6,0x8d,
+  0xe3,0x1e,0x7b,0x2c,0xa2,0x10,0x83,0x2e,0x1c,0x38,0x0b,0xfa,0x20,0x78,0x12,0x1c,
+  0x57,0x71,0xca,0x04,0xc6,0x9d,0x1c,0x33,0xa7,0x25,0x95,0x6e,0xc9,0x64,0x3b,0xd9,
+  0x63,0xb4,0x01,0xdf,0xd9,0x05,0xce,0x15,0x7a,0x9e,0xf2,0x8d,0x01,0x66,0x65,0x4c,
+  0x2c,0xd0,0xcf,0xb8,0x5f,0xfc,0xaf,0x4b,0x18,0x14,0xd0,0xa2,0x96,0x2a,0x97,0x83,
+  0xc8,0xcf,0x29,0x86,0x14,0x31,0x19,0xd2,0xd7,0xca,0x0d,0x33,0x75,0xbf,0x6c,0x03,
+  0xfe,0x47,0xb4,0x02,0x34,0xff,0x12,0xd5,0xfe,0x25,0x3c,0xe2,0x5d,0x16,0x1e,0x19,
+  0xc8,0x08,0x61,0xef,0xc5,0x27,0x72,0x34,0x1e,0x1a,0x04,0x31,0x41,0x87,0x58,0x04,
+  0x54,0xd3,0x0b,0xc3,0xb1,0x65,0x2e,0x19,0xde,0xb0,0xc7,0xb8,0xed,0xe4,0x10,0x8a,
+  0x57,0x2a,0x15,0xd3,0xa2,0xc2,0x9c,0x3a,0x30,0x79,0xfc,0xff,0x98,0x67,0x98,0xea,
+  0x74,0x5e,0x45,0x74,0x13,0xe6,0x48,0xfe,0xbf,0xfe,0xf9,0xbf,0x5f,0xff,0xfc,0xfa,
+  0xf5,0xeb,0xc7,0xb0,0x12,0xf0,0xca,0x27,0xc0,0x17,0xf2,0xa7,0x80,0x43,0x7c,0x02,
+  0xc8,0xc3,0xf9,0x75,0x04,0xc1,0x09,0xca,0x77,0xf8,0x1b,0x1f,0x7b,0xcd,0x2d,0xe0,
+  0x78,0x7c,0xe6,0x80,0x58,0x0b,0xfe,0x17,0xf8,0x3f,0xb3,0x54,0xc8,0x9b,0x36,0xe9,
+  0x71,0x1e,0xf9,0x11,0x59,0x61,0x3c,0xa0,0x80,0x82,0x1e,0x19,0x0a,0xf1,0x11,0x1e,
+  0x16,0xb6,0xf6,0xe7,0x7d,0xf3,0x88,0x7d,0x5e,0xef,0x3f,0xc9,0xc0,0xff,0xde,0x7b,
+  0x0f,0xde,0xfb,0xcd,0x6f,0xde,0x7d,0xf9,0xee,0xbf,0x1e,0x6a,0xe3,0x3f,0xa3,0xee,
+  0x22,0xb6,0x00,0x44,0x03,0xb8,0x0d,0xf0,0x4a,0x49,0xbd,0x61,0x29,0x00,0xc4,0x00,
+  0xa8,0x15,0xb0,0xb7,0x9b,0xcd,0x36,0x98,0x0a,0x10,0xc5,0xcd,0xbc,0xa8,0x33,0xf0,
+  0xda,0xed,0x50,0x88,0x58,0xc0,0xcd,0x2f,0x3c,0xcb,0x5a,0x36,0x53,0x4f,0x05,0xb3,
+  0x43,0xdc,0x80,0x3e,0x06,0x27,0xfd,0x62,0x31,0x5d,0xf6,0xf8,0xdd,0x04,0x59,0xf6,
+  0xc3,0x2e,0x14,0x69,0x40,0xf2,0x3a,0x5a,0xdb,0x85,0x63,0x85,0xfe,0xb7,0xb5,0x8c,
+  0xc0,0xbe,0xdf,0x9f,0x68,0xeb,0x72,0x39,0xda,0xbf,0x02,0x0c,0x00,0x77,0xb7,0x6d,
+  0x54,0xa0,0x98,0x91,0xe4,0xd6,0x26,0x2a,0x1c,0xd4,0x70,0x89,0xcd,0x16,0xb1,0x61,
+  0xa3,0x51,0x4f,0xed,0x22,0xfc,0x19,0x7d,0xe9,0xf4,0x31,0xa7,0x56,0x48,0x99,0xa8,
+  0xac,0xef,0x62,0xc0,0x10,0x89,0xde,0x2e,0xfe,0x54,0x6d,0x51,0x18,0x03,0x1b,0x05,
+  0x41,0x77,0x19,0x61,0x1c,0xd6,0xc1,0x09,0x45,0xdb,0x3c,0x56,0xe8,0x7f,0xf2,0x5c,
+  0xc1,0x34,0xb1,0xee,0xe5,0x83,0x03,0x70,0x7e,0x7c,0xaa,0x84,0x51,0xcd,0x42,0x80,
+  0xcc,0xfb,0x15,0x16,0xd2,0xb6,0xb4,0x27,0x76,0xb0,0x88,0x50,0xc4,0x6d,0xdd,0xd7,
+  0xe1,0x83,0x7a,0x2c,0x62,0x2b,0x10,0xd3,0x6e,0xc9,0x9d,0x1b,0x6d,0x7d,0x04,0x2c,
+  0x35,0xc8,0xfc,0x06,0x4b,0xb1,0x15,0x7b,0x18,0x2b,0xae,0xcf,0xe1,0x79,0xbb,0x2d,
+  0x45,0x1d,0x1e,0x85,0x8e,0x64,0x79,0x2c,0x8d,0x64,0x88,0xd9,0x5d,0x99,0x66,0x96,
+  0x62,0x90,0xdf,0xe8,0xf7,0x70,0xb7,0x42,0xfb,0x97,0xa4,0xea,0x75,0x59,0xca,0x24,
+  0x9e,0x33,0x61,0x38,0xfd,0x1d,0x4d,0x97,0x41,0x3d,0x3a,0xff,0x39,0xe0,0xfc,0x7a,
+  0x9e,0xcc,0xd8,0xfe,0x77,0x8a,0x50,0x06,0x77,0xef,0x37,0x81,0x31,0xbc,0x0f,0x37,
+  0x9d,0xbf,0x98,0x99,0x79,0xf3,0x6c,0x9e,0x3f,0xcf,0xfb,0x8c,0x83,0xdb,0x63,0xda,
+  0x38,0x37,0xb3,0xe7,0x82,0xd3,0x79,0x47,0xee,0xf2,0x79,0xcb,0xbd,0x79,0xcd,0x1b,
+  0x61,0xb0,0xab,0xcf,0x0a,0x04,0x80,0xef,0x9b,0xc7,0xde,0x3e,0xec,0xef,0x37,0x5a,
+  0xfd,0x18,0xf8,0xdf,0x7b,0xf0,0xe0,0xc1,0x9f,0x3e,0x78,0xf0,0xee,0xbb,0x5f,0xff,
+  0xed,0xe1,0xc3,0x3f,0x12,0x19,0xe5,0x6e,0xd7,0x2e,0x33,0x05,0x80,0xcb,0x55,0xc4,
+  0x3e,0x0d,0x03,0x78,0x0c,0xda,0x5b,0xf7,0x08,0x36,0x02,0x50,0x1d,0x80,0x73,0x80,
+  0x3d,0xdc,0xce,0xef,0x72,0x0d,0xaa,0x01,0xc8,0x02,0xd6,0xd6,0x72,0x6b,0x37,0x97,
+  0xf5,0x0a,0xe2,0x32,0xd8,0x68,0x64,0x91,0xf0,0xbf,0x92,0x85,0x9b,0x92,0xba,0x76,
+  0x0b,0x47,0x0c,0x62,0x1d,0x01,0x4f,0x32,0x22,0x65,0xf4,0x72,0xa6,0x5c,0x4f,0x35,
+  0xd0,0x05,0x1e,0x74,0x56,0x1a,0x59,0x6d,0x94,0xe0,0x16,0xfd,0xec,0xc7,0x9c,0xfb,
+  0x3d,0x51,0xfd,0xc8,0x6a,0xa0,0xdd,0x86,0x1a,0x40,0x66,0x54,0x4f,0x21,0xfa,0x62,
+  0x20,0x69,0xba,0xc4,0x03,0x34,0x8a,0x2a,0x1b,0xb6,0xc4,0x36,0x31,0x01,0xd5,0x3f,
+  0x95,0xda,0xd6,0x82,0x21,0xc3,0x27,0x46,0x7e,0xf3,0xe7,0xcf,0xc9,0xbb,0x99,0xcc,
+  0x28,0xb5,0xba,0x8a,0x11,0x30,0x62,0x00,0xbf,0x15,0x6d,0x39,0xe1,0x20,0xbf,0xe3,
+  0x26,0xd8,0xcd,0x60,0xdc,0x21,0xea,0xec,0x3b,0x27,0xa8,0xe2,0x7a,0xe2,0x78,0x1f,
+  0xd3,0x6a,0xf6,0xa8,0x98,0x09,0x33,0x19,0x8c,0x49,0xf0,0xed,0x8e,0x00,0x4d,0x9f,
+  0x2a,0xda,0xef,0xdc,0x31,0x44,0x63,0x68,0xd0,0x00,0x0e,0x95,0x5a,0x9d,0x74,0x80,
+  0xb9,0x11,0xb2,0x25,0x01,0xfb,0x45,0xb5,0x72,0x19,0xb8,0x19,0x5a,0xa5,0x54,0xb0,
+  0xdb,0xff,0xbf,0xf6,0xce,0x2e,0x34,0xae,0x24,0xbb,0xe3,0x6b,0x14,0x13,0x36,0x9e,
+  0x61,0xc9,0x4b,0x18,0xda,0xb0,0x8d,0x92,0x6d,0xd4,0x2b,0x1b,0x13,0xed,0x83,0x76,
+  0x13,0xe6,0x65,0x50,0x96,0xf5,0x86,0xa4,0x45,0xeb,0xb2,0x41,0xcd,0x2a,0x2d,0x2d,
+  0x51,0xd2,0x08,0x26,0x63,0xd6,0x44,0x84,0x35,0xd1,0xae,0x48,0xf0,0x4e,0xa4,0xb8,
+  0x33,0xea,0x64,0xbc,0xb1,0x89,0x97,0x30,0x61,0x24,0x7b,0xf2,0xd0,0x3d,0x44,0xa8,
+  0xc7,0xac,0x5e,0xf2,0x01,0xf9,0x20,0xca,0x43,0xd2,0xc4,0xe8,0xc1,0x16,0x34,0x7a,
+  0xd8,0x8e,0x5e,0x16,0x12,0x46,0xa2,0xbb,0xd3,0x71,0xea,0x9c,0xfa,0xae,0x7b,0x5b,
+  0x1f,0x1e,0x4b,0xf6,0x86,0xff,0xef,0xde,0xbe,0xb7,0x6e,0xd5,0xa9,0x53,0xa7,0xea,
+  0x76,0xd5,0xad,0xfb,0x55,0x57,0x2f,0xe2,0x99,0x28,0x95,0xa2,0x57,0xe9,0xea,0xaf,
+  0x63,0xe7,0xb5,0x5c,0x47,0xd4,0x7f,0xfb,0x1f,0x88,0x47,0x89,0x21,0x92,0xe4,0x0f,
+  0x0b,0xad,0xaf,0xaf,0x88,0xce,0x7f,0x23,0x31,0xff,0xe1,0xae,0xb3,0xe5,0xa2,0xcb,
+  0xee,0xfc,0x3b,0x17,0x2f,0xce,0x51,0xf5,0x13,0x1d,0xe9,0xdf,0xfa,0xf6,0xa7,0x3e,
+  0xf5,0xeb,0xa2,0x5e,0x99,0xfa,0x7f,0x9d,0xba,0xd7,0xd7,0x2f,0xbe,0x49,0x63,0x02,
+  0xfc,0xe6,0xf5,0xeb,0xa3,0x6f,0xbe,0x21,0x7a,0x05,0x17,0x59,0xf6,0xe2,0xf5,0x39,
+  0x55,0x3f,0xaf,0x73,0xed,0x55,0x55,0x75,0xd4,0xd4,0xdb,0xd1,0xeb,0xb6,0x82,0x3b,
+  0x0e,0xcf,0xe9,0x54,0xf3,0x8b,0x36,0xd4,0xb4,0x01,0xa4,0x63,0x94,0x8c,0x90,0xdb,
+  0xa3,0x2a,0x85,0x51,0x32,0x6b,0x74,0xee,0xfa,0x9c,0x3a,0xe9,0x57,0xb5,0xff,0x8e,
+  0x3c,0xf4,0x8f,0x8c,0x8c,0x50,0xf5,0x7f,0xff,0xeb,0x17,0x4e,0xed,0xcd,0x3f,0x97,
+  0x83,0x35,0xfe,0x0e,0xc0,0x60,0xaf,0x50,0xef,0x4c,0xa4,0xbf,0x94,0x7b,0x40,0xe7,
+  0xed,0xea,0x70,0xda,0x92,0xe7,0x00,0xfc,0x24,0x00,0xb5,0x00,0x05,0xdd,0x07,0xa0,
+  0xcf,0xb9,0xad,0x51,0x27,0x80,0x2e,0x05,0x0c,0xdf,0x9b,0xed,0xde,0x5f,0xe9,0x51,
+  0xbd,0x14,0xa8,0x45,0x81,0xd6,0xcd,0x5c,0xf1,0xfc,0xdb,0x3c,0x9d,0xff,0x1a,0xcd,
+  0x66,0x6a,0x44,0xbd,0x29,0x8e,0x21,0x20,0xd1,0x82,0x8c,0x51,0x38,0xc8,0x6a,0xc1,
+  0xb7,0xdd,0x18,0x82,0xe9,0x74,0xd4,0x59,0x11,0xd5,0xbf,0x21,0xfe,0xae,0xeb,0x54,
+  0x19,0x44,0x67,0xa3,0xc9,0x3d,0xdc,0x1d,0xf9,0xed,0x02,0xea,0x4e,0x0a,0x43,0x9b,
+  0x1d,0xba,0x63,0xb1,0xbe,0x5e,0xef,0x46,0xbd,0x61,0x19,0xf9,0x6b,0x9e,0x4e,0xa9,
+  0xee,0x5a,0x73,0xab,0x21,0x2c,0x58,0x57,0xc9,0x2b,0x0b,0xca,0x85,0x4a,0xb4,0xe4,
+  0xa6,0xab,0x16,0xae,0x45,0xe7,0x0b,0xd4,0x76,0x91,0x0d,0x6c,0xb3,0x8d,0xaa,0x36,
+  0x43,0x2f,0xa5,0x5c,0x2f,0x4a,0xd1,0xaa,0x56,0x29,0xb5,0xbf,0x7d,0xde,0xaa,0xf7,
+  0x0b,0x49,0x79,0x9f,0xef,0xc9,0x04,0x1d,0xbd,0x9c,0x52,0x36,0x7a,0xd5,0x35,0xd3,
+  0xaa,0x1c,0xee,0x56,0x1a,0x3a,0x42,0xd9,0xc9,0x5f,0xb3,0x5b,0x3c,0xef,0x25,0x2d,
+  0x16,0xed,0x68,0xbd,0xc1,0x99,0x31,0xc6,0x97,0x8f,0x9c,0x48,0x28,0x2a,0x70,0x31,
+  0x4a,0xb3,0xe9,0x37,0xbc,0x48,0x0d,0x2a,0x6b,0x8a,0x67,0xbe,0x9c,0xa0,0x57,0x79,
+  0xae,0xaf,0xf7,0x7a,0xbd,0x52,0xd4,0xcd,0xf3,0x1b,0xe6,0x09,0xd9,0xd7,0xff,0x80,
+  0xaf,0x9d,0x77,0x0b,0xe7,0xfc,0xdb,0x6f,0xab,0x8c,0xfc,0xbe,0x38,0x7d,0xa6,0xda,
+  0x44,0x47,0x53,0xae,0xde,0x6f,0x52,0xb5,0x1a,0xfd,0x77,0x7a,0xfe,0x97,0xae,0xaa,
+  0x51,0xd8,0xc5,0x5f,0xa0,0xe3,0xff,0xbf,0xc9,0x06,0xe2,0xa7,0x2f,0x4a,0x61,0xfe,
+  0xc9,0xa8,0x73,0xe4,0x45,0x35,0x92,0xe7,0x51,0xa9,0xf0,0xa2,0xf6,0x1a,0xe5,0x33,
+  0x74,0x25,0xa8,0x43,0x47,0x9d,0xa5,0x74,0x71,0x44,0x0e,0xbd,0x4e,0x5e,0x9c,0x8a,
+  0x4c,0x46,0xeb,0xe0,0xb5,0xdc,0x1a,0xe5,0xab,0xfd,0x8f,0x4d,0xe5,0xe7,0x83,0xbf,
+  0xa8,0xfd,0x23,0x92,0xed,0xf7,0xc5,0xf1,0xff,0x94,0xef,0xfd,0x69,0xb2,0xf7,0x1e,
+  0xde,0x5d,0xaa,0xf2,0x25,0x40,0x1e,0x08,0x58,0x9d,0x01,0xa8,0x8b,0x80,0xd4,0x00,
+  0xa8,0x2e,0x40,0xa5,0x9e,0xe5,0xcb,0x00,0xb2,0x05,0xa0,0x0b,0x01,0x6b,0x6b,0xaf,
+  0x70,0x1b,0xb0,0x96,0x6b,0xae,0xf7,0xd6,0x7b,0x85,0xc2,0x3a,0xcd,0x62,0x92,0x73,
+  0x6f,0xbf,0x3b,0x7b,0xed,0xfc,0xb5,0xf3,0x1f,0x7e,0xf8,0xe1,0xf9,0x6b,0xce,0x74,
+  0xfe,0xda,0x60,0xb4,0x2e,0xfe,0xa1,0xe2,0x8f,0xd7,0x63,0xd1,0x5e,0x41,0xce,0x85,
+  0x6e,0xe9,0xda,0xb5,0xf3,0xd7,0x02,0x61,0x5a,0x7c,0x78,0x6d,0xad,0x14,0xe5,0xca,
+  0x2b,0x0d,0x71,0x28,0xa4,0x16,0x80,0x8f,0xdc,0x15,0xd1,0x7b,0x6f,0x36,0xb7,0xb6,
+  0xd2,0x5b,0x69,0x71,0x1e,0xb9,0xd5,0x6c,0xde,0xef,0xb0,0x91,0xe2,0x7f,0xd5,0x6c,
+  0xe5,0xf2,0x1c,0xf7,0x7c,0x82,0x3e,0x31,0x0f,0x37,0xd3,0xa4,0x87,0x0d,0x60,0x7a,
+  0x3c,0xad,0x97,0xa2,0x73,0x1f,0x9e,0xf7,0xd3,0x76,0x27,0xca,0x47,0xa1,0x2b,0xdb,
+  0x2e,0x1d,0x53,0x45,0x75,0x3c,0xa4,0x97,0xe3,0xdb,0x5b,0x37,0x8b,0x7a,0xd4,0x96,
+  0x6a,0x92,0xa7,0x04,0xaf,0x0f,0x7b,0x51,0x4f,0xd8,0xba,0xbe,0xe2,0x98,0x49,0xa5,
+  0x56,0x88,0xd6,0x63,0x71,0x59,0x71,0xb1,0xdb,0xe1,0x32,0xd2,0x76,0xb0,0xb4,0x28,
+  0xdf,0x4e,0x34,0xab,0x13,0x36,0x06,0xb4,0xa3,0xf2,0x14,0xcb,0xf6,0x1c,0xdb,0x79,
+  0x2e,0xac,0xbb,0x79,0x30,0x79,0x51,0x89,0x47,0x59,0xba,0x07,0xec,0x24,0x3e,0x9c,
+  0xde,0x9a,0x52,0x89,0xae,0x9b,0x98,0x56,0x83,0x53,0x4c,0x72,0x55,0x50,0x5e,0x82,
+  0x72,0xae,0x95,0x9e,0x66,0x6d,0xfd,0x4a,0xa5,0xdf,0x24,0xb2,0xf1,0xf0,0x4d,0x7a,
+  0x59,0x66,0x8e,0x7e,0x8f,0xe7,0x46,0x7f,0x5b,0x9c,0xde,0xbf,0x33,0x3a,0xfa,0x78,
+  0x74,0xee,0x67,0xe9,0x92,0xdf,0x63,0x7e,0x9c,0x6e,0x6e,0xf4,0x27,0x3e,0xa2,0xd3,
+  0xfe,0xb9,0xc7,0xa3,0xbf,0x4e,0xed,0xc0,0xe8,0x63,0x2d,0x2e,0x7e,0x8f,0x65,0xbd,
+  0x95,0x2e,0xe5,0x3b,0x2a,0x83,0xd5,0x82,0xb6,0x84,0x4a,0x19,0x22,0x9d,0xde,0x6c,
+  0x84,0xe7,0xf4,0xa6,0xf2,0x14,0x8b,0xc7,0xba,0x55,0x18,0x9d,0x53,0xc2,0x32,0xfc,
+  0xf1,0xdc,0x53,0xe7,0xc8,0xaf,0x7b,0xfe,0xbb,0x54,0xfd,0x2f,0x6c,0x6f,0x8b,0xe3,
+  0xff,0xc8,0xfb,0x5f,0x3f,0xf5,0x7b,0x7f,0x8a,0xd6,0xb4,0xe8,0x00,0x2c,0xb5,0xf7,
+  0xe4,0x97,0x80,0xed,0x4d,0x40,0xdb,0x02,0xec,0x70,0xb7,0x9a,0x4e,0x02,0xea,0x74,
+  0x68,0x15,0x7d,0x80,0xc1,0x5b,0xb5,0x5a,0x95,0x7b,0x01,0xd4,0x0d,0x98,0x5d,0xca,
+  0x6d,0xad,0x3b,0xc8,0x1d,0x2c,0xf6,0x74,0xe5,0xe0,0xd2,0xb5,0xe1,0x7b,0xc3,0xf4,
+  0x13,0x8b,0x6b,0x74,0xbd,0x60,0x98,0x57,0x7b,0x51,0x99,0xaa,0x7f,0x4f,0xfd,0x03,
+  0xcc,0x9f,0x25,0xd7,0x29,0x0a,0xd1,0x7b,0x2c,0x7c,0x8f,0xa3,0xc9,0x88,0xf7,0x84,
+  0xd7,0xec,0x54,0x37,0x6a,0x16,0x74,0xa5,0xa5,0x63,0x88,0xe8,0x04,0x88,0x6e,0xb0,
+  0x38,0x77,0x15,0xd3,0x7e,0x47,0x1c,0xf8,0x85,0x7d,0xe2,0x34,0xa5,0x50,0xa8,0x74,
+  0xa3,0xca,0x25,0x19,0x97,0x74,0x49,0x15,0xfc,0x13,0x8a,0x68,0xba,0x56,0xec,0xe4,
+  0x28,0xfd,0x15,0xf5,0xa7,0xec,0xe9,0x75,0xb6,0x95,0x57,0x62,0xd7,0xa4,0xa0,0x36,
+  0x86,0x97,0xac,0x6a,0x25,0x5a,0xa7,0x88,0x14,0xc5,0xb1,0x5e,0x67,0x45,0xb2,0x2e,
+  0x03,0xad,0x72,0xb3,0xc8,0x46,0x7b,0x52,0xcd,0x3d,0x47,0xab,0xdd,0x0a,0x7f,0xb4,
+  0x7c,0xf5,0x60,0x9d,0xd3,0xf3,0x12,0x12,0x05,0xdc,0xcd,0x0e,0xcb,0x42,0xba,0xa6,
+  0xed,0xa5,0xa2,0xbd,0x77,0xaf,0x98,0x6b,0x8a,0xc2,0x5d,0x5f,0xf1,0x8d,0x5a,0x17,
+  0x47,0xd9,0x69,0xca,0x99,0x14,0x53,0xd1,0x44,0xfd,0xf7,0x75,0xeb,0x6c,0x19,0x97,
+  0x3f,0x29,0xbf,0xf5,0x4f,0x97,0xec,0xce,0x61,0x2b,0x8b,0xe9,0x34,0xed,0xd1,0x15,
+  0x47,0xc1,0xba,0xa3,0xc1,0x4d,0xc1,0xd5,0x25,0x8e,0xfd,0xe9,0x54,0xb7,0x30,0xab,
+  0x76,0x4b,0x72,0x01,0xf0,0x7f,0xe1,0xda,0xb0,0xb3,0x63,0xb4,0xff,0xf0,0xf0,0x77,
+  0xae,0x5c,0x11,0x35,0x49,0x1c,0x4a,0xe9,0xa5,0x99,0x2b,0xff,0x45,0xb5,0x7e,0xf4,
+  0xca,0xdc,0x95,0xb9,0xef,0xd1,0xf3,0x3f,0xef,0xbe,0xf9,0xee,0xbb,0xef,0xbe,0xf9,
+  0x5b,0xff,0xf5,0x0b,0x74,0x31,0xf0,0x57,0xe6,0x1e,0x53,0xff,0xe0,0x8d,0x37,0x45,
+  0x30,0xd5,0xbf,0xb9,0x2b,0x4f,0xb9,0x16,0xd2,0x61,0xf8,0xa9,0x88,0x21,0x9c,0xa4,
+  0x82,0xea,0xa5,0x58,0x3e,0x56,0x42,0x14,0x42,0xd7,0xe6,0x85,0x38,0xbb,0x95,0xd3,
+  0x99,0x59,0x92,0xd7,0x4f,0xd5,0xe6,0x9c,0x8c,0x28,0xa2,0x89,0x6d,0xd1,0xc5,0x1f,
+  0xbd,0xc2,0x2f,0xf4,0xcd,0x49,0x55,0xaa,0xde,0xcb,0x0b,0x7e,0xfa,0x82,0xff,0x0c,
+  0x1f,0xfb,0xb7,0x05,0xe3,0xdb,0x17,0xc6,0xb7,0x47,0xde,0x7f,0xff,0xeb,0xa7,0x7e,
+  0xef,0x4f,0xd3,0x19,0x1e,0xbe,0x2b,0xbf,0x04,0x54,0xa7,0xab,0xda,0x3b,0xdd,0x83,
+  0x96,0xb9,0xb7,0x2d,0xdf,0x08,0xee,0xaa,0x16,0x80,0xfa,0xd6,0x59,0xd9,0x02,0x50,
+  0x27,0xa0,0x4d,0xbd,0x80,0x4b,0xe2,0x4c,0x60,0x7a,0x31,0x57,0x28,0x73,0x67,0x5e,
+  0x1d,0xfe,0x55,0x3b,0x30,0x10,0xb5,0x8b,0x0f,0x69,0xfa,0x9d,0x87,0x82,0x62,0x91,
+  0x66,0xb1,0x1e,0x2e,0xe6,0xa3,0xba,0x3d,0x4e,0xd2,0x8a,0x5a,0x8b,0x42,0xaf,0xb0,
+  0xd8,0x9c,0x25,0x01,0x31,0xe9,0x85,0x8a,0x47,0xeb,0xbb,0xab,0xa5,0x56,0xb4,0x5f,
+  0xa0,0x3f,0x0e,0x1d,0x82,0xe8,0x4c,0x23,0x2b,0x4f,0x5c,0xe9,0x54,0x92,0xc8,0x66,
+  0xc9,0xb3,0xd4,0x4d,0xe5,0xa6,0x66,0x8b,0x32,0xae,0x52,0xa4,0x94,0x15,0xd5,0xf4,
+  0xb0,0xb8,0xbf,0xa3,0x8e,0xcc,0xde,0xd1,0x49,0x54,0xcf,0xa9,0x87,0x0f,0x8d,0x50,
+  0x18,0x4d,0x38,0x87,0x8b,0xaf,0x46,0x05,0x7d,0xb8,0xec,0x05,0xc7,0xc8,0xe0,0xf8,
+  0x5f,0x88,0x1f,0xff,0xd7,0xcb,0xa9,0x57,0x13,0x54,0xfb,0x59,0xb6,0xc9,0x71,0xd6,
+  0xa7,0xa2,0xac,0x31,0xd2,0x4d,0xa8,0xdb,0x29,0xda,0xd8,0x45,0x53,0x4c,0xc5,0xd9,
+  0x9d,0xb4,0x96,0x2a,0xb8,0x56,0x95,0x52,0x55,0x99,0xb7,0x61,0x1b,0xad,0x9d,0xca,
+  0xda,0x12,0x70,0xb3,0x14,0xcb,0x9b,0x3f,0xe5,0x9a,0x77,0x79,0x47,0x2a,0x0b,0x8a,
+  0xc3,0xaf,0xa4,0x73,0xa6,0x7b,0xe0,0x76,0x81,0xfa,0x1c,0xff,0x65,0x2f,0xa2,0x4c,
+  0x2f,0x0c,0x74,0x4b,0xab,0x45,0x95,0xef,0x62,0x42,0x09,0xf8,0x7b,0xc3,0xf1,0xe4,
+  0x7f,0xd2,0x9f,0x8c,0x9a,0xea,0x24,0x6a,0xdf,0xd3,0x5f,0xf9,0xdd,0x4f,0x7d,0xea,
+  0xf3,0xef,0xd0,0x06,0xd5,0xff,0x6f,0xff,0xe8,0xa3,0x1f,0xbd,0xf1,0xc6,0x47,0x3c,
+  0x18,0xf8,0xb7,0xbf,0xf7,0xf4,0xca,0x53,0xea,0x14,0xfc,0x93,0x13,0xc1,0xc2,0x4f,
+  0xdd,0x3e,0x95,0x2b,0x2f,0x40,0x6d,0x78,0x5e,0x49,0x3c,0xbd,0x62,0xa2,0xfa,0x7a,
+  0xe3,0x72,0xa6,0xe6,0xfb,0x95,0x7f,0x64,0x7b,0x64,0x7c,0x7b,0x9c,0xe7,0x0b,0xe2,
+  0xf0,0x9f,0x39,0xab,0xea,0x7f,0x35,0x55,0xe3,0x87,0x80,0x6a,0x8d,0x5e,0xb6,0xde,
+  0xb9,0x99,0x36,0xef,0x01,0x98,0x16,0xa0,0xa5,0xae,0xac,0xf1,0xf3,0xc0,0xb2,0x05,
+  0x10,0x5d,0xe0,0xc6,0xa0,0xe8,0x05,0xb4,0xdb,0xd5,0xea,0xf4,0x74,0x35,0xdd,0x6d,
+  0xd2,0x11,0x98,0xb9,0xcf,0xdf,0xa1,0xed,0x54,0xc4,0x2f,0x9d,0x6a,0xcf,0x4a,0xc4,
+  0x79,0x02,0x4d,0x02,0xb1,0x7a,0x65,0xf6,0x56,0xd4,0x1c,0xa8,0x74,0x2a,0x2c,0xa4,
+  0x21,0xf7,0x4e,0x7a,0x4d,0x84,0xcf,0x4a,0x31,0x9a,0x8a,0x14,0xb9,0xa8,0x22,0xcf,
+  0x2e,0xed,0x35,0x53,0xd1,0xcd,0x92,0x3a,0xa1,0x2c,0xab,0x6f,0x8a,0xd3,0x55,0xc4,
+  0x6c,0xbd,0xcc,0xdf,0xa8,0x2e,0x94,0x3a,0xb9,0x54,0xb7,0x3c,0x3d,0xfb,0xca,0x5d,
+  0x95,0xa0,0x56,0xa6,0x66,0x65,0xc4,0x6c,0x27,0x52,0x49,0xfa,0x34,0x53,0x3d,0x13,
+  0x4d,0x99,0xe0,0x29,0x12,0xb6,0xaf,0xa4,0xf6,0x4d,0x44,0x4f,0x41,0x4c,0x9b,0xf2,
+  0x18,0x70,0x16,0x03,0xfb,0xa9,0xf5,0x59,0x5d,0x0e,0x4e,0x91,0x98,0xf4,0xe4,0x7c,
+  0x57,0xc1,0x69,0x4e,0x45,0xcd,0xca,0x80,0xd5,0x5e,0x91,0x8a,0x3a,0x9d,0x83,0xce,
+  0x9a,0xb1,0x52,0x8b,0x93,0xee,0xb5,0x74,0x57,0x48,0x54,0x94,0x6c,0x85,0xa4,0x39,
+  0xfe,0x56,0x2a,0x4f,0xf6,0x7b,0x05,0xdc,0x4e,0xa5,0x79,0x47,0x28,0xf3,0x2a,0xa1,
+  0xed,0x7d,0xb2,0xd4,0xe9,0xa6,0xd7,0xdc,0x54,0x85,0xca,0x66,0xd7,0xa6,0x79,0x34,
+  0x03,0x03,0x9d,0x66,0x3a,0x27,0xfe,0x65,0x8b,0x85,0xea,0x1a,0x17,0xec,0x5d,0x5b,
+  0x2c,0x5e,0xfe,0x9d,0x7d,0x37,0x7b,0xf7,0x15,0x31,0xd1,0x82,0xb8,0xfb,0xca,0xec,
+  0x2b,0x5f,0xf9,0xdc,0x9d,0x2b,0x3c,0xbd,0xc7,0xcb,0x3b,0x57,0xfe,0x47,0xd4,0xf0,
+  0xcf,0xbe,0x25,0xdc,0xdf,0xf3,0x9f,0xff,0xf9,0xfc,0x37,0x1f,0x5f,0xb9,0xf3,0x8e,
+  0x38,0x0d,0xf8,0xd1,0xbb,0x4f,0xa9,0xde,0x91,0xec,0x9d,0xf7,0xae,0xdc,0x79,0xaa,
+  0x26,0xda,0x7e,0x8f,0x7f,0xe4,0x27,0xd6,0x57,0x94,0x42,0xde,0x96,0x4b,0x39,0xbd,
+  0x27,0x64,0xe2,0x4b,0x11,0x4f,0x49,0xab,0x88,0x4f,0xb5,0x53,0x2b,0x72,0x2a,0xfd,
+  0x1d,0x75,0xb5,0x4f,0x76,0xfb,0x77,0x65,0xdd,0x17,0x07,0xfe,0xf1,0xcc,0xb8,0x98,
+  0x6f,0x73,0xfd,0xbf,0x70,0x06,0xf7,0xfe,0x34,0xb9,0xb5,0x7b,0xe2,0x0c,0xa0,0x46,
+  0xf7,0x00,0xf8,0x8e,0xb8,0x7a,0x11,0xd0,0x3c,0xab,0x45,0x37,0x02,0xf8,0x69,0x40,
+  0xd1,0x05,0x50,0x67,0x01,0x74,0x14,0xe6,0x5e,0x80,0xe8,0x06,0x88,0x53,0x81,0x7d,
+  0xba,0x65,0xd0,0x12,0x33,0x9f,0x31,0xa4,0xe4,0x38,0x02,0x62,0xea,0xe6,0x97,0xd6,
+  0x96,0xc4,0x39,0x02,0x2f,0x1d,0x6a,0x5d,0x7e,0xc2,0x20,0x4a,0xc9,0x2b,0xf7,0x6a,
+  0xdc,0x01,0x11,0xbb,0x79,0x49,0x4b,0xae,0x39,0x4b,0xb9,0x5e,0x13,0x8b,0xd5,0xa9,
+  0x66,0xaa,0x95,0x6b,0xd6,0x65,0xdd,0x17,0x86,0xc8,0xea,0x2f,0x7e,0xf4,0x75,0xf9,
+  0x3a,0x7d,0xd1,0xaf,0x5b,0xaa,0x4d,0x7b,0x3a,0x94,0x73,0x4d,0x69,0x91,0x9b,0x65,
+  0x4a,0x96,0x2e,0x71,0xb6,0xa4,0x05,0xea,0x1e,0x42,0x14,0xf5,0x9c,0xb4,0x55,0x14,
+  0x47,0x8f,0x70,0x0d,0x72,0xd6,0xf4,0x42,0x47,0x34,0x1b,0x8e,0xb2,0x94,0x74,0xb4,
+  0xdc,0x45,0x2a,0xea,0x69,0x95,0x6b,0x4b,0x7e,0x5e,0xe3,0xc5,0x24,0xc5,0x06,0x23,
+  0xcf,0x44,0xf9,0xa3,0x92,0x1b,0x30,0x22,0x46,0x9c,0x37,0x3a,0xa6,0xfc,0x75,0xb9,
+  0xaa,0x82,0xce,0xab,0x24,0xac,0x05,0xd5,0x9c,0x2c,0x85,0x48,0x16,0x44,0xcb,0xb1,
+  0xdf,0xe6,0xaa,0xe5,0xa5,0x2c,0xa7,0x66,0x68,0x67,0x29,0xe5,0x14,0x89,0x96,0x76,
+  0xca,0xd5,0x57,0x43,0x06,0x75,0x73,0x9d,0x42,0x7e,0xd5,0xec,0x95,0x35,0x27,0xcf,
+  0x61,0x11,0x04,0xe5,0x23,0x1c,0x32,0xa7,0xdf,0x7d,0xef,0x8e,0xcf,0x5b,0x5f,0xa0,
+  0x43,0xbc,0xa8,0x8f,0xdf,0xf9,0x82,0xe0,0x83,0x2f,0x7c,0xf0,0x01,0x2d,0x3f,0xfb,
+  0xcd,0x9f,0x13,0x95,0xfa,0x73,0x7f,0x29,0xc2,0xfe,0xec,0xca,0x9d,0x24,0x42,0x3d,
+  0xa7,0x89,0xad,0xfa,0x33,0x54,0xfb,0xa9,0xfa,0x8f,0x8f,0x8c,0x4b,0x32,0xe3,0x1b,
+  0x5c,0xfd,0xff,0xfb,0x4c,0xee,0xfd,0x69,0xf6,0x8b,0x7c,0x06,0xb0,0xb7,0x52,0x28,
+  0x57,0xe8,0x1a,0x20,0x3d,0x5f,0xe7,0xf4,0x00,0x5a,0xf2,0x3a,0x20,0xb5,0x00,0x8b,
+  0xdc,0x02,0x0c,0xd0,0x79,0xb6,0xe8,0x05,0xaf,0x70,0x13,0x30,0xb8,0xb7,0xd7,0x10,
+  0xae,0x29,0xe1,0x9e,0x12,0x93,0x60,0x70,0x50,0xcc,0xcc,0x2a,0x0f,0x23,0xb7,0xaa,
+  0x07,0x93,0x33,0x9b,0x4f,0x28,0xb0,0x21,0xc5,0x1a,0x4a,0x98,0x54,0xd5,0x58,0x62,
+  0x95,0x7e,0x4e,0x84,0x69,0xe3,0x3b,0xbd,0x5a,0x9d,0xea,0x88,0xc6,0xa3,0x9b,0xee,
+  0x0c,0x94,0xe4,0x4d,0xab,0xba,0xba,0x87,0x58,0x69,0x2e,0x8a,0xbf,0x72,0x3a,0x9b,
+  0x37,0xc3,0xd4,0xad,0x6a,0x1d,0x62,0xae,0xb2,0x0e,0xe1,0xac,0x4a,0xd5,0xf4,0x38,
+  0x71,0x23,0x2f,0x2c,0xd8,0x13,0xa9,0xef,0x49,0x53,0xf6,0x84,0x0d,0x7b,0x24,0x58,
+  0x95,0x56,0xea,0x38,0xab,0xc6,0x6e,0x36,0x60,0xcf,0x58,0x3e,0x68,0xb3,0xca,0x0e,
+  0xa1,0xcc,0x4c,0x83,0x7b,0xac,0x4f,0x06,0x52,0x22,0x62,0xc9,0x11,0xaa,0x46,0x77,
+  0x55,0x9a,0x46,0x8e,0x69,0xb7,0x94,0x94,0x5b,0x26,0x27,0x42,0xf7,0x54,0x5c,0x9b,
+  0xcc,0x20,0x2b,0xac,0xad,0x4e,0xbb,0xf6,0xa9,0x42,0x5b,0x5d,0xa5,0xbc,0xed,0xa9,
+  0x1d,0x20,0x92,0x6e,0x0c,0x2a,0x05,0xf9,0xea,0xb4,0x91,0x53,0xd3,0x6a,0x9e,0x43,
+  0xa5,0x7e,0xf1,0x23,0xbd,0x0d,0x55,0x2a,0x7a,0x0f,0x35,0x54,0x0e,0x1a,0x52,0x90,
+  0x33,0xd7,0x68,0x3b,0x5a,0x98,0x5a,0xbe,0xa1,0x22,0x88,0x83,0x82,0x13,0x51,0x2a,
+  0x6f,0xe8,0x02,0x50,0x1a,0xc4,0x76,0x3e,0x5f,0x5d,0x5d,0x9d,0x76,0x4c,0xd7,0x3b,
+  0xbd,0xea,0xe4,0x7f,0x55,0xfe,0x17,0xec,0x9f,0xc0,0xfa,0x8a,0xe9,0x8b,0xef,0x5d,
+  0x96,0xdc,0x31,0xf3,0x3b,0x74,0xab,0xff,0x7f,0x7e,0xf9,0xf2,0x2f,0xff,0xf0,0x87,
+  0x6f,0x7d,0xe6,0xad,0x1f,0x3e,0x16,0xab,0x1f,0x7e,0xe6,0x33,0x54,0xdd,0xde,0xfa,
+  0x6d,0xee,0x1b,0xb0,0xf4,0x9d,0xcb,0x47,0xcc,0x97,0xad,0x62,0x82,0x1e,0xc8,0x97,
+  0xee,0x64,0xe9,0x3b,0x8e,0x6c,0xe0,0xbc,0xac,0x13,0xf4,0x98,0x91,0xf7,0xf9,0xf9,
+  0x5a,0x3f,0x75,0xf9,0x05,0x1b,0x99,0x0d,0x31,0x8b,0x26,0x60,0x7b,0xfb,0xc2,0xee,
+  0x99,0x56,0xff,0xab,0x57,0xb3,0x0f,0xc5,0x19,0xc0,0x6a,0x6d,0x70,0x45,0x1c,0x42,
+  0xe9,0x1a,0xe0,0x0e,0x37,0x00,0xba,0x0b,0xd0,0x32,0x77,0x02,0x72,0xd4,0x02,0xdc,
+  0xdc,0xdf,0xe7,0xeb,0xec,0x74,0xa1,0x5d,0x75,0x03,0xa8,0x23,0xb0,0x77,0x2b,0x9f,
+  0xa7,0xce,0x80,0xa4,0xdd,0x6e,0xd3,0xcf,0x2c,0x6a,0x3c,0xc9,0x8d,0x9a,0xf2,0xd1,
+  0xc1,0xee,0xba,0xea,0x47,0xf3,0x02,0x55,0x78,0xad,0x51,0x6e,0x1e,0xf0,0x68,0x51,
+  0xf4,0x74,0xf2,0x7e,0x53,0x40,0x4f,0x04,0x0b,0x9f,0xdc,0xc0,0xca,0x9e,0x14,0x57,
+  0x51,0x6a,0xb5,0x20,0xbe,0x9b,0x4c,0xad,0xea,0x24,0xa0,0x23,0x05,0xb2,0x35,0x2f,
+  0x92,0x6f,0x50,0xad,0x1d,0xdb,0xac,0x39,0x3a,0x6a,0x6e,0xb6,0x3d,0xb5,0xb5,0xb8,
+  0x5b,0x47,0xd6,0x45,0x63,0x8b,0x4d,0xfb,0xdb,0xd0,0x43,0xcc,0x65,0x99,0x6a,0x10,
+  0xdf,0x4a,0x56,0xdd,0xa2,0x77,0xa2,0x54,0x13,0x8a,0xc8,0xec,0xaf,0x24,0x4c,0xb1,
+  0x3a,0xe9,0x78,0x76,0x27,0xe4,0xd5,0x0f,0x72,0xf2,0x11,0xb7,0xd3,0x13,0xb6,0x26,
+  0xd7,0x82,0xd0,0x5b,0xff,0x32,0x73,0x39,0xe4,0xb5,0x9f,0xa2,0x93,0xfd,0x3f,0xfb,
+  0x8c,0xaa,0x63,0x7c,0x8c,0xe5,0xe9,0x73,0x9f,0x15,0x01,0x1f,0xfd,0x29,0x6f,0xc4,
+  0xa3,0xf5,0x25,0x14,0x9d,0x49,0x9a,0xe5,0x6a,0xc6,0x4a,0xcf,0x84,0x91,0x9c,0x49,
+  0xa4,0xbe,0x4b,0x75,0x9f,0xbb,0xfd,0x74,0xc1,0x8f,0x0e,0xfb,0x1b,0x1b,0xb2,0xfa,
+  0x67,0xc6,0x33,0xb7,0xb7,0x2f,0xbc,0x9f,0x39,0x93,0x5b,0xff,0x96,0x8f,0xa7,0x86,
+  0x8b,0xb3,0x3c,0xd4,0x76,0xa1,0x5e,0xda,0x6f,0x2e,0x2e,0xca,0x53,0x00,0xe7,0x1c,
+  0x80,0xfb,0xb2,0x0f,0xf8,0x42,0xa0,0x38,0x0d,0xa0,0xdb,0xec,0x15,0xbe,0xda,0x4e,
+  0x97,0xfc,0xe8,0xf2,0xb4,0x38,0xfe,0x37,0x56,0xa8,0x59,0xe7,0x03,0x07,0x1f,0xfd,
+  0x08,0xeb,0x32,0xe4,0xf7,0xf6,0x9e,0xb0,0xe3,0x89,0xf6,0x79,0xe2,0x86,0x1d,0x83,
+  0x27,0x7b,0x83,0x53,0xeb,0xe6,0x0d,0x1c,0xb9,0x38,0xc8,0xed,0xd7,0x57,0x1a,0xa1,
+  0x64,0x7e,0x30,0x29,0x7e,0xa2,0xca,0x44,0x7b,0xfa,0x0b,0xc7,0xb6,0x93,0x23,0x29,
+  0xbd,0x4f,0x62,0xbe,0x49,0x89,0x25,0xe5,0xfe,0x09,0xe7,0x60,0xd0,0x4b,0xe6,0xf0,
+  0xf2,0x8a,0x65,0x39,0x48,0xdc,0x8f,0xf3,0x24,0x3f,0xd8,0xa7,0x8c,0xac,0xdc,0x2d,
+  0x67,0x19,0xb7,0xcd,0x13,0xf6,0xb2,0x75,0xcb,0xf1,0x92,0xb2,0x56,0xe7,0x93,0x3c,
+  0x05,0x1c,0x67,0x7f,0xe7,0x63,0x36,0xdf,0xe2,0xcd,0xc1,0xc1,0x1f,0x50,0x35,0xe2,
+  0xaa,0x64,0x99,0xf9,0xc7,0xdf,0xa1,0xf3,0xfd,0x2f,0x7f,0x8e,0x0e,0xb0,0x33,0x2a,
+  0x70,0xe6,0xf2,0x6b,0xdf,0xa1,0xce,0xff,0x47,0xff,0x31,0x13,0x8b,0xd0,0x8f,0x50,
+  0xaf,0x5e,0xce,0xb8,0xce,0x5d,0xab,0xcf,0xac,0x66,0xd4,0xd2,0x4e,0xbe,0x36,0x7d,
+  0x8b,0x5f,0x5e,0xec,0x17,0x55,0x7f,0x9c,0x2a,0x7f,0x66,0x79,0x7e,0x39,0x33,0x2f,
+  0xd6,0xd4,0xfd,0xbf,0x7d,0x86,0x27,0xff,0x92,0x54,0x7e,0x98,0x2e,0x01,0xd4,0xe8,
+  0xf9,0xfa,0x0a,0xbd,0x09,0xa4,0x07,0x03,0xb2,0x17,0x01,0xd4,0x4b,0x81,0xea,0x4a,
+  0xe0,0x96,0x38,0xf2,0x56,0x54,0x1b,0x50,0xa6,0x73,0x01,0xbe,0xac,0xbb,0x42,0x77,
+  0xaa,0xc5,0xb9,0x80,0x98,0x78,0xa1,0x1c,0xb4,0x66,0xb4,0xe7,0x14,0xdd,0xc8,0x57,
+  0xae,0x29,0x19,0xb8,0xa2,0xb6,0xcd,0x52,0xfb,0xe9,0x10,0x8e,0xa5,0x82,0xe8,0x74,
+  0x63,0xa5,0xd7,0x2b,0x67,0x4b,0xa5,0x81,0x81,0x52,0x29,0x5b,0x28,0xf4,0x56,0x5e,
+  0xd5,0x51,0x8d,0x16,0xa3,0xc9,0xd1,0x60,0xbc,0xa7,0x6c,0x02,0x76,0x8b,0x5b,0x31,
+  0xad,0xc4,0x11,0x77,0x32,0xe0,0x84,0xba,0x86,0x9a,0x84,0x9d,0x85,0x93,0x8a,0x6b,
+  0xc6,0xd4,0x94,0x67,0x88,0xcc,0x94,0xab,0x63,0x65,0xca,0xd7,0x3e,0x15,0x2a,0xd3,
+  0x45,0xe8,0x18,0x67,0xb3,0xd8,0x50,0xc5,0xbb,0x12,0xa4,0x4e,0x8b,0xc6,0x54,0x58,
+  0x0e,0x2b,0x3a,0xfd,0x84,0x62,0xb2,0x16,0xab,0xdd,0xe5,0xef,0x90,0x70,0x27,0x79,
+  0x65,0x6a,0xa3,0xd9,0xe2,0x8b,0xed,0xef,0x86,0x36,0xe3,0x55,0x27,0x41,0x27,0x71,
+  0x6f,0x0f,0x78,0x7b,0x83,0x16,0x3f,0x18,0x19,0xd1,0x95,0xc9,0xb0,0xbb,0x3d,0xf2,
+  0xfd,0x6f,0xd2,0x07,0x04,0x3f,0xfa,0xeb,0x3f,0x9f,0x61,0x0f,0x9a,0x5f,0xfb,0xee,
+  0x97,0x7f,0x49,0x56,0x7f,0xe5,0x75,0x0c,0xb6,0x77,0x8f,0x2d,0x7a,0x02,0xb6,0x69,
+  0xe2,0x9a,0x7f,0x5b,0x9e,0xed,0xf3,0x81,0x7f,0x79,0x7e,0x9e,0x67,0x3a,0xfe,0x8b,
+  0xc3,0xff,0xf6,0x99,0x57,0x7f,0xfa,0xa2,0xd6,0xf0,0xdd,0xb5,0x4b,0xed,0x5b,0xf4,
+  0x92,0x7d,0x65,0x82,0x7a,0x00,0xfc,0x2a,0x80,0xf7,0xce,0xa6,0xbc,0x17,0xc8,0x77,
+  0x03,0xb9,0x0d,0x68,0x36,0xf9,0x4c,0x60,0x40,0x3e,0xc8,0x59,0x2e,0xeb,0x1b,0x80,
+  0x9f,0x8c,0xde,0x31,0x7c,0xfb,0xa5,0x91,0x1c,0xf7,0x39,0xd0,0x4b,0x74,0x3e,0x27,
+  0x8d,0x9f,0x58,0xca,0xc8,0x3e,0x93,0x6d,0xa7,0x56,0x68,0x9f,0x20,0xed,0x5e,0x62,
+  0xa0,0xb9,0x45,0x49,0xbf,0xbf,0x1f,0x19,0x17,0x95,0x85,0x8f,0xa1,0xde,0xb4,0xfd,
+  0xfe,0x57,0xf8,0x8e,0xdf,0x47,0x5f,0xfe,0x93,0x6f,0x7c,0xeb,0xbf,0xbf,0xff,0xfd,
+  0x9f,0xfc,0xd3,0xaf,0xfc,0xe5,0xe7,0xc9,0xe3,0x83,0xef,0x52,0x28,0x8b,0x48,0xd1,
+  0x30,0xa6,0xa3,0xc3,0x48,0x6c,0x5b,0x41,0x76,0x6f,0x4b,0x1d,0x76,0xad,0x7f,0x4a,
+  0xf7,0xf8,0xb8,0xeb,0x39,0x2e,0x2b,0xbb,0x42,0xea,0xd1,0xc8,0x1e,0xff,0xb2,0xa8,
+  0xfc,0x93,0x93,0x62,0x9e,0xa4,0x16,0x40,0x74,0xff,0x45,0xfb,0x70,0x46,0x0f,0xfe,
+  0xf9,0xe4,0xd6,0x86,0x67,0xd7,0xa6,0xdb,0xb7,0xa6,0xd6,0x0b,0xa2,0x07,0x20,0x9f,
+  0x03,0x70,0x2e,0x02,0x9a,0x93,0x00,0xba,0x19,0x48,0x6f,0x6d,0xf2,0x79,0x00,0xf5,
+  0x02,0xe8,0xbe,0x9f,0x68,0x04,0x2a,0xf2,0x5a,0x5c,0x56,0x5e,0x92,0x2f,0x8b,0x5e,
+  0x01,0xb5,0x09,0xb4,0x12,0x1e,0xe5,0xac,0x72,0xd1,0x8a,0xb7,0x79,0x6d,0xdc,0x75,
+  0xe9,0x2e,0x93,0xab,0x6e,0x5c,0x1c,0x85,0xb6,0xe5,0xdd,0x3d,0xbe,0xc1,0x57,0xd7,
+  0xf1,0xca,0xf2,0x86,0x9f,0x54,0x4b,0xbe,0xf2,0xc7,0x4e,0xa5,0x57,0x2b,0x95,0x0e,
+  0xed,0xd4,0xa9,0xd6,0xb3,0x3a,0xba,0x4c,0x81,0x6e,0x25,0x2a,0x47,0xd9,0x58,0xae,
+  0x75,0xd5,0xcb,0x3a,0x29,0x65,0x97,0x34,0x4c,0x7b,0xb0,0x09,0xd2,0xc0,0xb2,0x2b,
+  0x56,0x37,0xfa,0x74,0xfe,0xb2,0x32,0x9d,0xba,0x4d,0x42,0x9a,0xa7,0xe2,0xd6,0x95,
+  0x89,0xca,0x47,0xfe,0xca,0xda,0x48,0xb3,0x50,0xc5,0x9b,0x75,0xf3,0x5a,0x77,0xec,
+  0x55,0x92,0xb2,0xb4,0xf4,0x0e,0x90,0xdb,0x59,0x5d,0x2c,0x65,0x9d,0xc1,0xba,0x63,
+  0x88,0x0a,0x52,0x06,0x94,0xb5,0xc1,0x75,0x93,0x6b,0x93,0x4d,0xbb,0x37,0xcb,0xaa,
+  0x10,0xeb,0xd6,0x4f,0xe5,0x57,0xa6,0x67,0x0b,0x39,0xab,0xf7,0x5d,0xdd,0x96,0x83,
+  0xab,0x46,0x97,0x19,0x4b,0x1b,0xb3,0xf4,0x5c,0x2f,0x9b,0xb2,0x14,0xbf,0xaf,0xde,
+  0x56,0x17,0xcc,0xe3,0x5c,0xf8,0xee,0x1f,0xaa,0xbb,0x7e,0xbf,0xf6,0xc6,0x07,0xff,
+  0xfb,0xd1,0xb7,0xe5,0xc7,0xc0,0xbf,0xfc,0x03,0xbe,0xc1,0x66,0x7e,0x87,0x92,0x09,
+  0x1c,0x4e,0xc4,0xcc,0xb8,0x5d,0x67,0x62,0x02,0x41,0x64,0x72,0xde,0x76,0xbc,0x45,
+  0x67,0x9f,0x4f,0xf6,0x09,0x51,0xe1,0x27,0x2d,0xf3,0x54,0xfd,0x37,0x32,0xdb,0x17,
+  0x2e,0x3c,0x7a,0x11,0xd5,0xff,0xea,0xd5,0x9b,0xb3,0x0f,0xef,0x2e,0xad,0xb6,0xf7,
+  0xf8,0x14,0x80,0x9f,0x04,0xee,0x3e,0x88,0x82,0x16,0xa0,0x95,0xd2,0x9f,0x08,0xa0,
+  0xf3,0x00,0x6a,0x02,0xb8,0x11,0xe0,0x56,0x80,0x9e,0xc0,0x13,0x0d,0x81,0x68,0x09,
+  0x4a,0xa5,0xca,0x80,0x98,0xed,0x82,0x66,0xc7,0xa5,0xc2,0xe9,0xad,0x10,0x21,0x5c,
+  0xe1,0x9f,0x11,0x75,0x5e,0xa3,0xa1,0x10,0x9a,0xad,0x1f,0x39,0x49,0xac,0xc4,0xf2,
+  0xe4,0x57,0xe1,0x57,0x61,0x64,0x10,0xfd,0x06,0xd8,0x63,0x40,0x29,0x60,0xfd,0xa5,
+  0x8a,0x4a,0x5f,0xb9,0x59,0x66,0xa0,0x2e,0x23,0x0e,0x68,0xbd,0x52,0x95,0x8c,0xae,
+  0x6c,0xb2,0xf1,0xb4,0x58,0x45,0x5b,0x32,0xe0,0x98,0xa0,0x23,0x57,0xb4,0x6d,0x15,
+  0x6d,0xa8,0xb6,0x42,0x65,0x4f,0x59,0x4b,0xc9,0xc8,0x5f,0xc5,0xa6,0x67,0xf2,0xac,
+  0xed,0xb5,0x6f,0xcc,0xa8,0x72,0x19,0xa8,0xe8,0xf0,0x01,0x55,0x76,0xf5,0xd0,0x3e,
+  0xb3,0x5d,0x1f,0x90,0xc9,0xeb,0x04,0x28,0xa4,0xae,0x82,0x4b,0x7a,0x47,0x68,0x63,
+  0x75,0x99,0x56,0xb8,0x20,0x07,0x6c,0xb1,0x57,0x6c,0x2e,0xb5,0xa8,0x7a,0xbf,0x49,
+  0xca,0xeb,0xcc,0x4a,0x83,0x8c,0x0d,0x32,0xf2,0x80,0xde,0xaf,0x32,0xbf,0x03,0xa6,
+  0x4c,0x4d,0x31,0xe8,0xc2,0xac,0xa8,0x02,0xad,0x38,0x89,0x18,0x5d,0xee,0xda,0x7d,
+  0x97,0xa8,0x72,0x7b,0x23,0x09,0x55,0xb7,0xfe,0xe8,0xaf,0x3e,0x08,0xc6,0xff,0xf8,
+  0xbb,0x2f,0xea,0x08,0xcb,0x99,0xc4,0x98,0xfd,0x59,0x3e,0xa1,0x7c,0x8c,0xf1,0x65,
+  0x6d,0x17,0xf5,0xf5,0x37,0x44,0x47,0x9f,0xab,0xbe,0xae,0xfd,0x8f,0xe4,0x6a,0x59,
+  0x1c,0xfd,0x37,0xc4,0xc9,0xff,0x19,0x5f,0xfa,0xb7,0x94,0x8a,0xa2,0x01,0x98,0xae,
+  0x71,0x03,0x50,0xba,0x7f,0x33,0xad,0x3e,0x09,0xe2,0x8f,0xe9,0x23,0x6f,0x3d,0xab,
+  0xb1,0x1b,0xe8,0x44,0x80,0x6f,0x09,0x2c,0x36,0xc5,0xd9,0xc0,0xcd,0xe6,0xfe,0xcd,
+  0x26,0xbd,0x71,0x2a,0xe6,0x0e,0x3f,0x0f,0xc4,0x7d,0x03,0xbd,0x26,0x97,0xdc,0x6e,
+  0xaa,0x2d,0x29,0xd3,0x71,0x7e,0x2c,0xdb,0xec,0x34,0xf7,0x95,0xb0,0x5a,0x93,0x20,
+  0xb7,0x30,0x1c,0x57,0xba,0x45,0x90,0x7c,0xe6,0xa8,0xa9,0x34,0x9a,0x74,0x38,0x66,
+  0xd3,0x68,0x50,0xfe,0x4a,0xbf,0x9e,0xb4,0xdb,0x11,0xd4,0xf6,0x68,0xcf,0xc0,0x2e,
+  0x19,0xd8,0xd4,0x76,0xab,0xdf,0xbe,0x13,0xd1,0x78,0x39,0x32,0xfb,0xd6,0xbf,0x63,
+  0xf3,0xe0,0xe8,0xb1,0x89,0xdb,0x4c,0xea,0xa8,0x6e,0x39,0x72,0x86,0x6d,0xb8,0x13,
+  0xdf,0xda,0x67,0xe5,0x3a,0xa6,0x48,0x94,0xb7,0x8c,0xe1,0xc9,0xeb,0x75,0xd3,0xc8,
+  0x37,0x3b,0x5e,0xde,0x3a,0x89,0xfa,0x9d,0xe2,0x30,0x65,0x27,0x7f,0x5e,0x7e,0x9c,
+  0xe8,0xde,0x7e,0x76,0xec,0x6e,0x1a,0x9b,0x92,0xf6,0x8f,0xc9,0x7f,0x53,0xea,0xa6,
+  0xd5,0x3e,0x17,0xc1,0x84,0x70,0x64,0xe6,0x97,0x45,0x8f,0x99,0x3a,0xcd,0xc1,0x6f,
+  0x79,0x79,0x52,0x04,0x65,0x7e,0xe3,0x0f,0xde,0x7e,0xc3,0x3c,0xfc,0xf3,0xc1,0xc3,
+  0xff,0xbc,0x2d,0x42,0x39,0x58,0x2c,0xe7,0x13,0x23,0x7a,0xbf,0x65,0x29,0x43,0x4e,
+  0x3a,0x30,0x4f,0xea,0x2d,0x15,0xee,0x6c,0xc8,0x69,0x59,0xea,0xa6,0xca,0xad,0xb6,
+  0x85,0x21,0xac,0x84,0x27,0x0d,0x6f,0xb9,0x3c,0xe2,0xda,0xcf,0x2d,0x80,0x68,0x66,
+  0x32,0x54,0xfd,0xcf,0xf8,0xd2,0xbf,0x43,0x61,0xb8,0x38,0x2b,0x1a,0x80,0x5b,0x0d,
+  0x3a,0x05,0xe8,0xd0,0x37,0x01,0x77,0x78,0x74,0x9c,0x60,0xa0,0x2b,0x7e,0x86,0xa3,
+  0xc5,0x97,0x02,0x76,0xa8,0x09,0xd8,0xa1,0xd1,0x1c,0xa8,0x27,0xb0,0x48,0x6f,0xe2,
+  0xf0,0xeb,0x38,0xf4,0x52,0x4e,0x93,0x5e,0xc9,0xd9,0x3a,0x9c,0xa3,0xc2,0xfb,0xcb,
+  0x9e,0x24,0xe6,0xf3,0x49,0xff,0x74,0x14,0x9c,0x40,0x5f,0x93,0xa7,0x67,0x51,0x71,
+  0x64,0xac,0xe3,0x64,0xa3,0x99,0xe8,0x7c,0x36,0x9a,0x87,0x6e,0xfa,0xfe,0x4e,0xb6,
+  0xf9,0x2f,0xd5,0xa4,0xbf,0xd8,0xe4,0xd1,0xfc,0xcc,0x6f,0xfc,0xe2,0xef,0xfd,0xf5,
+  0x3f,0xdc,0xfb,0x87,0xaf,0xfc,0xc1,0x1f,0xff,0xfc,0xf2,0x31,0xe4,0x9f,0x0b,0x8f,
+  0x0e,0x0f,0x1e,0xe2,0x89,0xab,0xbd,0x64,0xf2,0x91,0x6a,0x02,0xe6,0xe7,0x37,0x32,
+  0xb7,0xc7,0xb7,0x47,0xce,0xfa,0xce,0x9f,0xcb,0x8d,0xa9,0xe1,0xe2,0x5d,0x6e,0x00,
+  0xe8,0xca,0x3a,0x0d,0x0a,0xb3,0x43,0x63,0x4e,0x45,0xc1,0x75,0x40,0x7d,0x16,0xa0,
+  0x3e,0x17,0x2a,0x1a,0x01,0xd1,0x0a,0xe8,0x66,0x40,0xb6,0x05,0xdc,0x1e,0x88,0x5f,
+  0x7a,0xf1,0xf0,0x69,0xf1,0x88,0xf0,0xfe,0xb2,0x27,0x89,0xf9,0x7c,0xd2,0x3f,0x2d,
+  0x0d,0xc7,0xd7,0x27,0x79,0x16,0x0d,0x47,0xc5,0x3a,0x4e,0x2e,0x16,0x4f,0x28,0x7f,
+  0x92,0xf4,0xfa,0xe9,0x5b,0x74,0x72,0xad,0x66,0x76,0x7f,0x69,0x88,0x78,0x34,0x39,
+  0xd4,0x8f,0x47,0x4a,0x40,0xf0,0x60,0x48,0x56,0xb2,0xbe,0xb2,0xcf,0xc6,0x24,0xa7,
+  0x3f,0x39,0x64,0x67,0xf2,0x24,0xaf,0x47,0x93,0x32,0xc0,0xb3,0xef,0x91,0x5e,0x8a,
+  0x4a,0x4f,0x3f,0xb9,0xd0,0x6d,0x80,0x3c,0xfa,0x8f,0x8f,0x8c,0xdc,0x7e,0x81,0xd5,
+  0xff,0xea,0xd5,0xd4,0x4a,0xb1,0x48,0xcf,0x01,0xd1,0x07,0xf7,0xb2,0xf2,0x1c,0x60,
+  0x67,0x47,0x7e,0x17,0x30,0x36,0xd8,0xa5,0xbc,0x18,0xa8,0xee,0x09,0x10,0xd4,0x17,
+  0xe0,0x76,0x40,0x2f,0xa5,0xeb,0x50,0x8e,0x21,0xd2,0x47,0xf6,0x24,0x31,0x9f,0x4f,
+  0xfa,0xa7,0xa7,0xe2,0xd8,0xfa,0x72,0xc7,0x49,0x2e,0x51,0xe2,0x88,0x68,0xc7,0xc9,
+  0x44,0xae,0xef,0xc6,0xc9,0x89,0x45,0xef,0xa7,0x4f,0xfd,0x8f,0x74,0xc6,0x69,0xb0,
+  0x87,0x5c,0xae,0x3b,0xf6,0xe8,0xf8,0x0c,0xc5,0xea,0xdb,0xf3,0x60,0xf3,0xd0,0x04,
+  0x13,0x85,0x37,0xd5,0xa4,0x3c,0x16,0x8c,0x12,0x3a,0xfa,0x2f,0xd3,0xd1,0x7f,0xe4,
+  0x42,0xe6,0xcc,0x5e,0xfa,0x4b,0xe6,0xe3,0xfa,0x6c,0x71,0x76,0x6d,0xba,0x56,0x93,
+  0x83,0x63,0xd1,0x20,0x3b,0x39,0xdd,0x00,0x84,0x03,0xbb,0x46,0x29,0xf7,0x29,0x6f,
+  0x39,0x28,0x25,0xcf,0x0f,0x44,0x53,0xf0,0x40,0xb4,0x07,0xb2,0x59,0x38,0x94,0x63,
+  0x88,0xf4,0x91,0x3d,0x49,0xcc,0xe7,0x93,0xfe,0xe9,0xa9,0x38,0xb6,0x3e,0xd1,0xd5,
+  0xa2,0xde,0xd6,0x11,0x0a,0x92,0x24,0x8e,0xb0,0x32,0x29,0x4e,0xe8,0xe5,0xc9,0x1c,
+  0x6d,0xc6,0xe1,0xe9,0x1d,0xc7,0x00,0x2d,0xf8,0x80,0x67,0xcd,0x83,0xee,0x83,0xb1,
+  0x05,0xc1,0x26,0x2d,0xd8,0x95,0xc8,0x66,0xdf,0x90,0x67,0x61,0x93,0xf4,0x6d,0xba,
+  0xdb,0x0b,0xca,0xc7,0xf7,0x74,0x3c,0x28,0xca,0xa6,0xc5,0x73,0x3f,0x12,0x5b,0x8f,
+  0x36,0xc7,0x36,0x75,0xf5,0x9f,0x5c,0xce,0x64,0xc4,0xd1,0x7f,0xfb,0x05,0x9e,0xfb,
+  0x6b,0x9a,0xd3,0xd4,0x00,0x54,0xf3,0x7b,0x3c,0x2a,0x54,0x87,0x6e,0x04,0x1e,0xd2,
+  0x02,0xa8,0xaf,0x85,0x58,0x78,0x60,0xd7,0x48,0x8e,0xfe,0x7b,0x00,0xc0,0x73,0x44,
+  0x8e,0x22,0x7c,0x70,0xf0,0x5c,0x6b,0xf6,0xf1,0xb8,0x21,0x26,0x9a,0xed,0xf6,0x09,
+  0x88,0x35,0x45,0x9b,0xb2,0x75,0x10,0xc7,0xff,0x31,0x59,0xfd,0xe9,0x1e,0xc1,0xed,
+  0x91,0xed,0x07,0x2f,0xbe,0xfa,0x5f,0xbd,0xda,0x6d,0x8b,0x06,0xe0,0x52,0x95,0x6e,
+  0x03,0xf0,0x39,0xc0,0xc4,0x16,0xb5,0x00,0x0f,0x64,0xb5,0xa6,0x77,0xfc,0x54,0xd5,
+  0xd7,0x4d,0x40,0x2a,0xd2,0x1f,0x0c,0x08,0xdf,0xfb,0x72,0x5e,0x7b,0xd3,0x93,0xf7,
+  0x3a,0x59,0xec,0x45,0xb3,0x96,0x8d,0xa2,0xa3,0xb9,0xaf,0x07,0x7a,0xeb,0xd0,0x33,
+  0x31,0x0d,0xf3,0x7a,0x9e,0x11,0xf0,0x12,0x38,0x4e,0xfa,0xfe,0x2b,0x70,0xad,0xd0,
+  0x1d,0xaa,0x88,0xa2,0xd0,0x80,0x96,0x93,0x92,0xb3,0x65,0xac,0x0d,0xf2,0xe9,0xd9,
+  0xeb,0xe4,0x29,0x7c,0x9d,0xce,0x8b,0x9f,0x94,0x25,0x27,0x69,0x3f,0x7e,0x60,0x8a,
+  0xf3,0x76,0x9e,0x5b,0x82,0x6e,0x3e,0xfd,0x8c,0xfa,0xb9,0x76,0x4d,0xf4,0x33,0x1c,
+  0xec,0x7c,0xaf,0xf8,0xbc,0x7d,0xe8,0x67,0xc8,0xdb,0x8d,0xae,0x7d,0x72,0xa4,0xc7,
+  0x56,0x4b,0xd4,0x3e,0xaa,0x8e,0x37,0x0e,0x63,0x41,0xfe,0x62,0x42,0x87,0xc7,0x4a,
+  0x56,0xb4,0x70,0xc3,0x54,0xff,0x1b,0x66,0x5a,0x58,0xd0,0x89,0xf8,0x01,0x2a,0x52,
+  0x6c,0x52,0x8d,0x86,0x69,0x37,0x36,0xc7,0x16,0xb8,0xfb,0x3f,0x34,0x44,0x0f,0xfe,
+  0x6c,0x64,0xe8,0x49,0xa1,0x17,0xdc,0xf7,0xd7,0xb4,0x5e,0xbd,0x5b,0x5c,0xbb,0xb4,
+  0x5a,0xbb,0x45,0xc3,0xdc,0xd2,0x98,0xbe,0x13,0x3c,0xca,0x5e,0xf7,0x81,0xda,0x01,
+  0x51,0x42,0x27,0x40,0x2f,0xe4,0xee,0xd5,0x4d,0x02,0xef,0x48,0xf3,0xa2,0xaf,0x16,
+  0x90,0xef,0x89,0xa6,0x28,0xa4,0xa5,0x3d,0x64,0xb0,0x0d,0x57,0xb7,0x19,0x53,0x52,
+  0x41,0x4b,0x46,0x96,0x52,0x6a,0xa9,0x13,0x35,0xfa,0x65,0x7c,0xeb,0x63,0xa4,0xb5,
+  0x3e,0xcf,0xcc,0x94,0x36,0xee,0xa8,0xf4,0xad,0xe1,0x8e,0xfd,0xa1,0xd3,0x28,0xd6,
+  0x93,0x8a,0xa0,0xdf,0x70,0xd6,0x59,0x6d,0x85,0x46,0xb7,0x6c,0x92,0x8e,0xa5,0xae,
+  0x7e,0x9b,0x29,0x25,0xa2,0x0b,0x2e,0x2c,0x52,0xed,0x6f,0x2c,0x69,0x59,0xb5,0x4e,
+  0x76,0x53,0xc6,0xc7,0x14,0xae,0x55,0xeb,0xe6,0xd9,0x7a,0xb5,0xa2,0x40,0xb1,0xd9,
+  0x6c,0x79,0x91,0x74,0xbc,0xc8,0x4d,0xc3,0xdf,0xfd,0xd6,0x10,0xfd,0x1f,0xb1,0xe2,
+  0x36,0xb3,0x66,0x4f,0xe9,0xfd,0xe3,0xe6,0xe1,0xa4,0x35,0xf8,0x6c,0x59,0x48,0xda,
+  0x74,0x1a,0x11,0x53,0xff,0xf9,0xd8,0x2f,0x2f,0xfc,0xd3,0x53,0x42,0x17,0x46,0x32,
+  0x2f,0xe0,0xa1,0xdf,0x64,0x3e,0xce,0xce,0xde,0xe5,0x73,0x80,0xc1,0x95,0x15,0xbe,
+  0x13,0xd8,0xd9,0x4a,0xa7,0x73,0x39,0x7d,0x2f,0x80,0xfe,0x0f,0xfa,0x99,0x80,0x16,
+  0x0f,0x15,0xec,0x76,0x04,0xe4,0x7e,0xe3,0x46,0xdb,0xfe,0x1d,0xdc,0x7d,0xea,0x54,
+  0x11,0x5f,0x22,0x15,0x6e,0x7a,0x51,0xf8,0xcf,0x62,0xfe,0xd7,0x81,0x96,0x20,0xaa,
+  0x17,0xd6,0x0a,0x43,0xe3,0xe6,0x1c,0x9a,0xbe,0x0d,0x74,0xea,0x85,0x53,0x19,0x3c,
+  0x53,0x12,0xcc,0x4b,0x85,0x3a,0xfd,0x76,0x25,0x15,0x57,0x95,0x60,0x9b,0x2b,0xd2,
+  0xaf,0x48,0x6d,0x76,0xfd,0xb8,0x47,0xfa,0xc4,0xd5,0xb6,0x4c,0xcd,0xb4,0xba,0x83,
+  0x48,0x2d,0x5f,0x65,0xac,0xac,0xe2,0x7a,0xbd,0x12,0x69,0x45,0x4e,0x29,0x26,0xab,
+  0xf3,0xf2,0xa6,0x7c,0x5a,0xa9,0xb3,0xaf,0xd2,0xcf,0xc2,0xc7,0x71,0x2f,0xbf,0x05,
+  0x10,0xbd,0x7f,0x71,0xf0,0x9f,0x1c,0xa2,0x2b,0x7f,0xe3,0x74,0xe1,0x7f,0xfe,0x65,
+  0xe8,0xfb,0x6b,0x9a,0x97,0xf8,0x1c,0xa0,0xbd,0xd7,0xe0,0x71,0xa7,0x2b,0x9d,0x89,
+  0x9b,0x69,0xbe,0x15,0xd0,0x95,0x4f,0x04,0x45,0x72,0xb4,0x88,0x94,0x19,0x28,0x98,
+  0x1a,0x81,0xc8,0x99,0x38,0x44,0x35,0x09,0xee,0x1c,0xf9,0x62,0xce,0x66,0xcb,0x6e,
+  0x86,0xeb,0x20,0x58,0x6f,0x44,0xc1,0x56,0x2b,0x14,0x70,0xc5,0x62,0xd6,0x85,0xe6,
+  0x24,0xa7,0x1f,0x9a,0x91,0x64,0x7b,0xdf,0xf4,0xe3,0xa6,0x7a,0x0a,0x82,0x90,0xd0,
+  0xbc,0x84,0x42,0x38,0x2a,0x0f,0x09,0x0a,0x12,0xf2,0xe0,0x9b,0x95,0xa4,0x50,0xee,
+  0x58,0x57,0xae,0x8f,0x9a,0x84,0xe2,0x39,0x34,0x3c,0x9c,0x5a,0xf1,0x40,0x3b,0x87,
+  0xde,0x34,0xc2,0xcc,0xd9,0xd7,0xe4,0xe7,0x89,0xa9,0xfe,0x9b,0xa6,0xeb,0x2f,0xce,
+  0xfc,0x6f,0x8f,0x6f,0xef,0x6e,0x8f,0xbd,0x4c,0xd5,0xff,0xea,0xd5,0x9d,0x76,0xf1,
+  0xee,0xda,0x12,0x5d,0x06,0xe4,0x61,0xfa,0xf9,0x43,0x1d,0xa2,0x05,0xc8,0xd1,0x07,
+  0x72,0xba,0xea,0x12,0x5f,0x64,0x47,0x98,0x49,0x99,0x2e,0x5c,0xca,0x74,0xad,0xc3,
+  0x13,0xd9,0xf8,0x6c,0x4f,0x35,0xc3,0x13,0xe1,0xe0,0x7c,0xd1,0x39,0x1d,0x4f,0x56,
+  0xe9,0x68,0x48,0x39,0x91,0xc2,0x53,0xcf,0xf0,0x0a,0x41,0x28,0x74,0x1a,0xe9,0xfb,
+  0x09,0x87,0xd1,0x93,0xd4,0x84,0x25,0xd4,0xd2,0x43,0xf3,0xc4,0xdc,0x09,0xd1,0x93,
+  0x13,0x71,0xb2,0xa0,0x34,0xf8,0x99,0x76,0x4f,0xf6,0x53,0x6e,0x8e,0x3d,0xb9,0x98,
+  0x59,0x8e,0x6f,0x2a,0xc9,0x00,0x2f,0xef,0x89,0x81,0x3a,0x72,0x4c,0x4c,0x4f,0x29,
+  0xa9,0x59,0x7a,0xa7,0x5e,0x74,0x05,0xfe,0x04,0xd8,0x43,0xff,0xa3,0x05,0xd1,0xf5,
+  0xa7,0x67,0x05,0x44,0xdf,0x3f,0xc3,0xcf,0xfc,0xec,0x66,0x5e,0xb2,0xea,0x7f,0xf5,
+  0x6a,0x34,0x35,0x2b,0x2f,0x03,0xe6,0x1b,0xa2,0x05,0x28,0x53,0x1f,0x60,0x7f,0x62,
+  0x4b,0x7d,0xdc,0x49,0x75,0x03,0x6c,0x2b,0xe0,0xd3,0x52,0xd7,0x6b,0x5a,0xea,0xc7,
+  0x32,0x07,0xce,0xcf,0xfc,0x23,0x79,0x33,0x72,0x9d,0x32,0xe8,0xc0,0xc4,0x77,0xea,
+  0x63,0xe4,0x44,0x8e,0x02,0x45,0x56,0xc3,0x81,0x0a,0x8d,0x7c,0x7f,0xe3,0xe1,0x59,
+  0x13,0x05,0x52,0xb1,0xf4,0x6d,0x8c,0x67,0x49,0x5f,0xbb,0x3c,0x43,0xbc,0xf8,0x61,
+  0xbb,0xa4,0x17,0xd6,0x40,0x2f,0x7e,0x14,0x25,0xc8,0x78,0x5a,0x83,0xb8,0xb1,0x2c,
+  0xd8,0x7d,0xa4,0x2c,0x8a,0x42,0x65,0x91,0x31,0x2f,0x0a,0xcd,0x72,0x4b,0xad,0xe5,
+  0xfb,0x1d,0x98,0x62,0x0b,0x72,0xe4,0xee,0x89,0x58,0x73,0x60,0x92,0xb4,0x49,0x18,
+  0x6b,0x4c,0x76,0x23,0xdd,0x3a,0xdd,0x78,0x86,0xeb,0x77,0x9f,0xac,0xca,0x7e,0x12,
+  0xec,0x29,0x80,0x77,0xc3,0x80,0xee,0xfb,0xd3,0x73,0x41,0xa2,0xf2,0x6f,0xf0,0xeb,
+  0x41,0xdb,0x23,0xef,0xbf,0xe8,0xbb,0xfe,0x89,0x6c,0xd5,0x66,0xb9,0x0b,0xc0,0x2d,
+  0x00,0x8d,0xb5,0x5d,0x11,0xa7,0x01,0x13,0xfc,0xc5,0x0d,0x7e,0x14,0x43,0xde,0xec,
+  0x97,0x5f,0x89,0xd4,0x6d,0x81,0xc2,0xdb,0xb0,0xfb,0x31,0x46,0x2b,0xfe,0xd7,0x3e,
+  0xf0,0x82,0x9c,0xea,0xe9,0xab,0xf1,0x55,0xaa,0x7f,0x8d,0x17,0xc1,0xd6,0xca,0x28,
+  0x1e,0xe0,0xc5,0x3c,0xbd,0xf4,0x8d,0xab,0x15,0xc6,0x69,0xb9,0x31,0x43,0x45,0x07,
+  0xbe,0x9c,0x1b,0xdf,0xb8,0x83,0x22,0x4e,0xb4,0xca,0xd5,0x71,0x10,0x99,0xd8,0xad,
+  0xd0,0xd6,0x78,0x66,0x5a,0x9e,0x02,0x2f,0x7f,0x7e,0x40,0xe8,0x15,0xda,0xe5,0xb5,
+  0x00,0x31,0x9b,0xc3,0x52,0x90,0xf6,0xf8,0x62,0x07,0x72,0xfb,0x80,0xae,0xfb,0x3b,
+  0x57,0xe2,0xcf,0x82,0x1b,0x0b,0x0b,0xe1,0x55,0xfc,0xf0,0x36,0x40,0x10,0x18,0x33,
+  0xcc,0xf7,0xe2,0x6e,0x3f,0xf5,0xfb,0xa9,0xe7,0x4f,0xef,0xfa,0x8f,0x8f,0xd3,0x90,
+  0x00,0x43,0x2f,0xba,0xaa,0x27,0x93,0xda,0x6f,0xcf,0xce,0xae,0x2d,0xad,0x56,0x6b,
+  0x7b,0x83,0x74,0x16,0x50,0xae,0x97,0x2a,0x95,0x7d,0xd1,0x0b,0x48,0xcb,0x36,0x80,
+  0x5a,0x01,0xf9,0x74,0x86,0x68,0x08,0x1e,0xd0,0xb8,0x00,0xdc,0x24,0xc8,0x2d,0xfd,
+  0x2c,0x90,0xf6,0x51,0xab,0xc4,0xa9,0x1b,0xca,0xf4,0x13,0xe8,0x3f,0x9d,0x30,0xe2,
+  0x59,0xa5,0x6f,0xa2,0x1f,0x19,0xd3,0xdb,0x0c,0xbc,0xdd,0xf8,0xc6,0x7d,0x10,0x14,
+  0x70,0xa0,0xe4,0x30,0x4b,0x7c,0x7b,0xd4,0x56,0x52,0xb4,0xbe,0xf9,0x3b,0x56,0x56,
+  0x12,0x05,0x1e,0x24,0x5b,0x2a,0x30,0x21,0x07,0xae,0x22,0x89,0x48,0xb0,0xf5,0xe8,
+  0x6c,0x2a,0xfd,0x69,0x21,0xfa,0xfc,0x63,0xba,0xf2,0xcf,0xcf,0xcf,0x67,0xe6,0x33,
+  0x34,0x7a,0xc1,0xc8,0x85,0xed,0xa1,0x97,0xad,0xeb,0x6f,0x49,0x55,0xce,0xcd,0xce,
+  0x2e,0x2d,0x4d,0xb7,0x6b,0x7b,0x8d,0x06,0x7d,0x72,0x23,0x5b,0x97,0x5f,0xa1,0x6c,
+  0x8a,0x36,0x80,0x1e,0xc5,0xce,0xed,0x2c,0xca,0x47,0x32,0x77,0x3e,0x4d,0x8d,0x01,
+  0x3d,0x01,0x4c,0xb3,0x71,0xa8,0xd9,0xae,0x13,0xfc,0x0f,0x0b,0x39,0xd4,0xa7,0xaf,
+  0xda,0x30,0x62,0x77,0x27,0xb0,0xc2,0x8b,0x76,0x94,0x76,0x57,0xcb,0xb3,0xa5,0x9f,
+  0x98,0x8d,0xe4,0x28,0x7d,0x8a,0xab,0x5f,0x92,0xf1,0x2c,0x1d,0xd7,0xc0,0x3e,0x19,
+  0x3f,0xb2,0x1c,0xe2,0x16,0x74,0xe5,0xfe,0x3e,0x34,0x33,0x87,0x5b,0x18,0xfb,0xbf,
+  0x78,0x19,0xfc,0xb4,0x98,0x1e,0x8c,0x8d,0x89,0xea,0xff,0x68,0x93,0x9e,0x9a,0x3b,
+  0x4d,0xc4,0x11,0x7a,0x8c,0x1e,0xcb,0xa3,0x07,0xf4,0xa8,0xa7,0x2e,0x16,0x63,0x63,
+  0xe2,0x27,0x66,0xf6,0x1e,0xa3,0xdb,0xf6,0x0b,0xb4,0x16,0x95,0x79,0xc1,0xfb,0x91,
+  0x34,0x4d,0x6c,0xe1,0xd8,0x26,0xe9,0xd8,0x54,0xcf,0xfb,0xaa,0xc7,0x7c,0xe5,0x29,
+  0x3f,0xbd,0x7c,0x28,0x4e,0xfb,0x79,0x98,0x90,0xdd,0x97,0xe2,0x89,0xbf,0xc3,0x68,
+  0xd5,0x57,0x67,0xd7,0xd6,0x96,0xaa,0xe2,0x2c,0x60,0xaf,0xc1,0x9f,0xdd,0xca,0xd2,
+  0x67,0xb7,0x2a,0xf7,0xe9,0x93,0xb2,0xcd,0x74,0x3a,0xad,0x5f,0x4b,0xc9,0xd1,0x2b,
+  0x3f,0xb4,0xa6,0x39,0x9d,0x53,0x0e,0xf9,0x9d,0x67,0xbd,0xca,0x2d,0x26,0xf9,0x3b,
+  0xde,0x9e,0x98,0x23,0xeb,0x2a,0x71,0x25,0x93,0x74,0x86,0x21,0xb9,0xc5,0xc5,0xc5,
+  0x20,0x11,0x37,0x20,0x6e,0x44,0x3c,0x0d,0x16,0x4d,0xb2,0xf4,0x98,0xe9,0xf7,0xcd,
+  0xb2,0x9f,0x23,0xb3,0x61,0x43,0x62,0x32,0xa1,0x55,0x89,0x3a,0x92,0xc4,0x42,0xaf,
+  0x30,0xf7,0x81,0x5f,0x62,0xc2,0x09,0xaa,0x83,0xc2,0x89,0x67,0x26,0x56,0x42,0x09,
+  0xfa,0x17,0x43,0x2b,0x5c,0x69,0xfa,0x4e,0xf8,0x97,0xc6,0x86,0x9e,0xf7,0xf3,0xfb,
+  0xc7,0x65,0xc8,0xbc,0x40,0x30,0xf4,0xc8,0x73,0x1e,0x5f,0x83,0x7c,0x59,0x88,0x5f,
+  0xff,0x9b,0x9f,0xdf,0x98,0xdf,0xd8,0x90,0x95,0x7f,0x64,0x77,0x77,0x64,0xf2,0xa5,
+  0xb9,0xe7,0xdf,0x97,0x28,0x3b,0x4d,0x2d,0xc0,0x74,0xb5,0x56,0xdb,0x6b,0xc8,0x2f,
+  0xef,0x65,0xb3,0x34,0x94,0x44,0xa7,0x73,0xff,0xfe,0xfe,0x7e,0x73,0x42,0xb4,0x03,
+  0xfa,0x75,0xcd,0x34,0xbf,0xfe,0x4b,0x7d,0x03,0xf9,0x49,0x3e,0xb9,0xe6,0x17,0x82,
+  0xbd,0x95,0x72,0xa5,0xdd,0x85,0xf6,0x73,0x42,0x7c,0x71,0xa5,0x3b,0x41,0xaa,0x6f,
+  0x7c,0xe5,0xf6,0x94,0x39,0x86,0x79,0xe9,0x7b,0xea,0x1c,0x03,0xd4,0xec,0x67,0xe5,
+  0x98,0xe9,0xbb,0xe5,0xe0,0x05,0x6f,0x05,0x4e,0xdf,0xcb,0x3a,0x02,0x2b,0xb6,0x82,
+  0xed,0xb4,0xa3,0xe3,0x30,0xd5,0xe9,0x78,0x4c,0x2f,0xf7,0xbe,0x95,0xae,0x77,0xb2,
+  0x5d,0xb1,0x88,0xfd,0x83,0xb6,0xb6,0x7c,0xe5,0x89,0xc5,0x98,0x56,0xf6,0x84,0xb9,
+  0x4d,0x37,0xd3,0xcd,0xe6,0xe2,0xdf,0x4c,0x4e,0xda,0x1a,0x34,0xf4,0xfc,0x5f,0xd9,
+  0x4d,0x7e,0x43,0xd7,0xbc,0xd2,0xa7,0xeb,0xef,0x90,0x7a,0xd9,0x4f,0x86,0x0f,0x25,
+  0x4f,0x43,0xea,0x5d,0xc0,0x98,0xa5,0xd4,0xe5,0xdf,0x90,0xe3,0x7b,0x66,0xa8,0xf2,
+  0xd3,0xd0,0x82,0x3f,0x06,0xb5,0x9f,0x38,0x28,0x2c,0xdd,0x9d,0x15,0x2d,0xc0,0xaa,
+  0xe8,0x04,0xe4,0x1b,0xa2,0x0d,0xe0,0xaf,0xc5,0x66,0xf9,0xe3,0x7b,0xa5,0x0a,0x7f,
+  0x61,0x66,0x5f,0x9c,0x14,0x08,0xee,0xd3,0x08,0x11,0xfb,0x3c,0x22,0x18,0x7d,0xdc,
+  0x7d,0xc2,0x6c,0x9b,0xf5,0x3e,0x7f,0x05,0x7e,0x9f,0x02,0xf7,0xd5,0x40,0x0e,0x36,
+  0xbc,0xa3,0x42,0x1d,0x6f,0xe3,0xa2,0x40,0xbb,0xe1,0xea,0x63,0x77,0x27,0x90,0x31,
+  0xe1,0xf7,0x79,0x63,0x62,0xc2,0x28,0x97,0x5a,0x3b,0x81,0xfa,0x8e,0x1b,0xfd,0xf9,
+  0xa5,0xdf,0x49,0x8e,0xc1,0x62,0x13,0xd6,0x73,0xc2,0x8a,0x4f,0xb8,0xf6,0xb9,0xe9,
+  0xc7,0x92,0x24,0x59,0x0a,0xf7,0x32,0x31,0xb1,0x2f,0x7d,0x8c,0xe7,0x7d,0x99,0xb3,
+  0x09,0x47,0x51,0x42,0xe6,0x4c,0xfe,0x3b,0x61,0xf9,0xa9,0xad,0x89,0x30,0x82,0xca,
+  0x84,0xb7,0x7f,0x9d,0x22,0x0e,0xb4,0x38,0xc5,0x3d,0x91,0x18,0xde,0x99,0xe8,0xc8,
+  0x8d,0xfb,0x26,0x84,0xa4,0x27,0x26,0x6e,0xfe,0xcc,0xdf,0xcc,0x4f,0xda,0xf1,0x33,
+  0xce,0x94,0xd8,0xc0,0x1d,0xd6,0x11,0x9f,0x28,0xc4,0x19,0xec,0xc3,0xc4,0xdc,0x98,
+  0xcf,0xd8,0x41,0x84,0xe4,0xe8,0x80,0x54,0xf9,0x77,0x77,0x37,0x5e,0xc6,0x8b,0xfe,
+  0xc9,0x3c,0x28,0x9f,0x5b,0x13,0x9d,0x80,0x69,0xea,0x04,0x88,0xf3,0x00,0xf5,0x09,
+  0x6e,0xfa,0x00,0x97,0xfc,0xf8,0x8e,0xfa,0xe4,0x3b,0x0d,0xd2,0x54,0x57,0xc3,0x48,
+  0x55,0x4a,0x5f,0x2d,0x69,0x17,0x0f,0xcf,0xa5,0xc7,0xde,0x92,0xd3,0x57,0x4b,0xfe,
+  0xb6,0x95,0x2b,0xd9,0xd1,0xa1,0xe2,0x02,0xfd,0x27,0x3f,0x7e,0x2c,0x50,0xc7,0x97,
+  0xdb,0xb1,0xd4,0x4f,0x39,0xfd,0x78,0xfc,0x58,0xd8,0x91,0xf1,0x8f,0x33,0x25,0xc5,
+  0x0f,0x12,0x7f,0x26,0xfb,0xbd,0x72,0x39,0x5e,0xfc,0xe4,0xcc,0x97,0xc2,0x50,0x99,
+  0x77,0xfe,0xa9,0xd8,0x4a,0x48,0x6e,0xde,0xff,0xd7,0x4c,0x26,0x43,0xa3,0xe2,0x7f,
+  0xd2,0x11,0xb8,0x4e,0x80,0x1a,0x8a,0x3f,0xd1,0xff,0x28,0x43,0x32,0x74,0x5d,0x6f,
+  0xde,0x0a,0x6a,0x71,0x35,0x22,0x20,0x8d,0x07,0xca,0x75,0x7f,0x77,0xe4,0xc7,0xa8,
+  0xf6,0x13,0xa9,0x5c,0x36,0x3f,0x4d,0xa7,0x01,0xd3,0xf4,0xfd,0x8d,0xfc,0xde,0x60,
+  0x43,0x7e,0x86,0xdb,0x7c,0xef,0x3d,0x11,0x33,0x48,0x64,0xd6,0x19,0xe5,0xd1,0x8c,
+  0x3e,0x99,0xf5,0xc4,0xcc,0xa8,0x93,0x59,0x3d,0x34,0xa5,0xe3,0x63,0x06,0xba,0x74,
+  0xc7,0x9d,0x2c,0x7b,0xc1,0x59,0x47,0x77,0xd6,0x55,0x6a,0x13,0xf1,0x2d,0x0a,0xcc,
+  0xf4,0x2c,0x2e,0x07,0x91,0xad,0xe4,0x71,0xd3,0x0f,0x92,0x8f,0x67,0xc5,0x37,0x31,
+  0x96,0x5b,0xcf,0x20,0x5f,0xd8,0x2d,0xbb,0x20,0x2c,0x30,0xdf,0x19,0xc2,0xd4,0x75,
+  0x79,0x39,0x8f,0xe7,0x20,0x29,0x53,0x59,0x37,0xe5,0x6c,0x98,0x7e,0x90,0xb6,0x27,
+  0xe7,0x8c,0x11,0xaa,0x2d,0x73,0x06,0x49,0x75,0x34,0x14,0xd8,0xbb,0x90,0xd5,0x83,
+  0x84,0x96,0xeb,0xff,0xfc,0xaf,0xb7,0xf9,0x7b,0x58,0x6a,0x20,0xcd,0xb3,0x99,0xa8,
+  0xae,0x66,0x36,0xd4,0xc8,0x9d,0xbc,0xb5,0xa1,0x8c,0x38,0x7c,0xdc,0xd0,0x8c,0x36,
+  0x75,0xdc,0x8e,0x10,0xaa,0x90,0xc3,0x03,0xcb,0x91,0xc7,0xe9,0x6b,0x7f,0xdb,0xf3,
+  0x0b,0x2f,0xf7,0x55,0xbf,0x44,0x3e,0xee,0x76,0xa6,0x56,0xd7,0x96,0xd6,0x2e,0x89,
+  0x13,0x01,0x3a,0x13,0xa0,0x46,0xa0,0x41,0x03,0xb8,0x53,0x43,0x40,0x1f,0x00,0xd1,
+  0x9f,0xf3,0xb6,0x5f,0x78,0x5e,0x31,0xdf,0x8b,0xf5,0xbe,0xfd,0xea,0x7e,0x06,0xb6,
+  0x97,0xb0,0x72,0xc3,0xfa,0xc4,0xf3,0x57,0x61,0x58,0xbf,0x38,0x7d,0xd2,0x38,0xcd,
+  0xf4,0xfb,0xe7,0xdb,0x93,0xed,0xf5,0x89,0xd9,0x4f,0x55,0xbf,0x8c,0xf6,0x13,0x89,
+  0x25,0xdb,0xc7,0xb8,0x23,0xca,0xef,0xf5,0xbe,0x85,0x15,0xfb,0x52,0x78,0xa2,0xe6,
+  0xd7,0xe3,0x5f,0x01,0x37,0x2b,0x11,0xf6,0x7a,0x6f,0xe5,0xf5,0xf5,0x95,0xd7,0x29,
+  0x99,0xf2,0xdf,0xff,0xb3,0x1a,0x3a,0x7b,0x64,0x44,0x1e,0x38,0xb7,0xcf,0x04,0x99,
+  0xce,0x08,0x8d,0xde,0x4d,0x1f,0xe5,0xa3,0x6f,0xf2,0x8e,0x48,0x97,0x72,0x5b,0x46,
+  0xdc,0xc5,0x38,0x8f,0xeb,0x2f,0x05,0x59,0x8f,0x5c,0x8c,0xd3,0x88,0xff,0xf2,0xc3,
+  0x04,0x23,0xf2,0x23,0x20,0xe3,0x93,0x3f,0x5e,0x47,0x7e,0x8f,0x68,0xab,0xd0,0x5e,
+  0xe2,0x36,0x40,0x34,0x02,0xf4,0x75,0xad,0x7c,0x8d,0xbe,0xc5,0x22,0xbf,0x9f,0xd7,
+  0xe0,0x6f,0xc4,0x81,0x97,0x93,0x97,0x7c,0xcf,0x38,0xe6,0x4d,0xad,0xbc,0xfe,0x83,
+  0x5f,0xfd,0x5b,0xea,0x24,0xef,0xea,0x9a,0xf3,0xfc,0xbf,0xc3,0xd1,0x87,0x5d,0xf3,
+  0xc9,0x8f,0x5d,0xb3,0x18,0x09,0x5c,0xbb,0x7e,0xb0,0x2f,0xa8,0x14,0x28,0x21,0xce,
+  0x03,0x7d,0x86,0x88,0x3e,0xfa,0x75,0x79,0x66,0x24,0xf3,0x92,0xdf,0xee,0x3b,0x06,
+  0xa9,0x5c,0x7d,0xb0,0x4d,0x5f,0x68,0xbc,0x24,0x3f,0x63,0x29,0xda,0x01,0x31,0xd1,
+  0xa7,0xf1,0x78,0x62,0xe8,0x2b,0x80,0x6d,0xfb,0x29,0xc0,0x38,0x22,0x4c,0x8a,0xba,
+  0x4b,0xbb,0xe6,0xc8,0x71,0x81,0xbc,0x27,0x9b,0x3f,0x56,0x7c,0x47,0x36,0x31,0xbe,
+  0xef,0x97,0x90,0xbe,0x23,0x70,0x82,0xf4,0x6b,0x49,0xf1,0xad,0x4c,0xde,0xf7,0x0b,
+  0xe1,0xe4,0x63,0xfa,0xbd,0xa5,0x5b,0xba,0x31,0x4d,0xed,0xb8,0x7e,0x93,0xdb,0x78,
+  0xbe,0x13,0x0c,0x69,0xd7,0xe2,0x36,0x93,0x0e,0xb7,0x5c,0xdb,0xb5,0xbc,0x93,0x9a,
+  0x15,0xcc,0xc7,0x8c,0xb5,0x36,0xc4,0xfe,0x14,0xc6,0x0c,0x55,0xc2,0xb7,0x06,0xbf,
+  0xf1,0xc7,0x7f,0xf1,0x8f,0xaf,0xe9,0x6f,0xf4,0x9d,0xe0,0x3b,0x7d,0xa7,0xc2,0x4c,
+  0x82,0xeb,0xf2,0x6e,0xc2,0xc2,0x95,0x9b,0xb1,0xbe,0xc2,0xf9,0x75,0xfe,0xfa,0x9f,
+  0x38,0xf2,0x6f,0x6f,0xfc,0x38,0xf6,0xfa,0x13,0xa1,0xaf,0xed,0xa5,0xf7,0x4b,0x85,
+  0x5e,0x63,0x2f,0xdf,0xa6,0x2f,0xb1,0x12,0xd5,0xea,0xea,0xb9,0xaa,0x58,0xb7,0x69,
+  0x12,0xcd,0x42,0xb5,0x2d,0xb6,0xab,0xe7,0xc4,0x44,0xdb,0xf4,0x23,0xb7,0x58,0x55,
+  0xcf,0x59,0x8f,0xf6,0x39,0x13,0x22,0xd7,0x9e,0xb8,0xb7,0x14,0x61,0xa4,0x97,0xc3,
+  0xce,0x55,0x7d,0xf1,0xfe,0xf1,0xcf,0xc9,0x75,0x75,0x35,0x39,0xbe,0x95,0xd3,0xa6,
+  0x48,0x8f,0x78,0xe2,0x27,0x4c,0x3f,0x6e,0xbc,0x51,0x4f,0xf9,0x57,0x92,0xe7,0xaa,
+  0xee,0x64,0x93,0x0f,0x4b,0x20,0x49,0x8f,0x1f,0x2f,0x8c,0xaf,0xc5,0x0f,0xd7,0x6b,
+  0x97,0x81,0xfa,0x23,0xf7,0x0b,0xaf,0x57,0xdb,0x26,0xbe,0x0a,0xa8,0xea,0x94,0x7d,
+  0x7f,0x37,0xbe,0xa7,0xe1,0x1c,0xfd,0x47,0xaa,0x74,0x4d,0xa9,0xf6,0xc5,0xff,0xfc,
+  0xc6,0x9f,0x7f,0xeb,0x5b,0xa2,0xee,0xbb,0x1f,0xcb,0x0d,0x3f,0x9b,0xfb,0xc2,0x78,
+  0xcd,0x3a,0xef,0x24,0x2c,0x3c,0xf8,0x9b,0xc0,0x14,0x61,0x46,0x9c,0xeb,0x8f,0x6f,
+  0x2c,0x0f,0x8d,0x2d,0x7c,0x7c,0xe3,0xff,0x4b,0xdd,0xf7,0xf9,0x38,0x8a,0xe8,0x13,
+  0x00,0x06,0x6f,0xe3,0x25,0xe2,0x65,0xb5,0x4b,0xf3,0xac,0xf6,0xbd,0xec,0xf9,0x3a,
+  0x1e,0x3b,0x3b,0xf4,0x84,0xdf,0x18,0x0d,0xe7,0x47,0x4f,0xd8,0x09,0xc6,0x36,0x79,
+  0x83,0xde,0x93,0x97,0x7e,0x67,0x35,0x6d,0x06,0x3f,0x3d,0xf1,0x53,0x7f,0xbc,0x1e,
+  0xdb,0x4c,0x5a,0x6c,0xca,0x30,0xf9,0x90,0xa0,0x7c,0x78,0x70,0x61,0xe1,0xc6,0xc7,
+  0xff,0x3f,0x6b,0x3d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x4e,0xc4,0xff,0x01,0x76,0x49,0x09,0x1b,0x36,0x04,
+  0x0c,0x00,
diff --git a/u-boot/board/esd/hh405/logo_320_240_4bpp.c b/u-boot/board/esd/hh405/logo_320_240_4bpp.c
new file mode 100644
index 0000000..ddf0d0b
--- /dev/null
+++ b/u-boot/board/esd/hh405/logo_320_240_4bpp.c
@@ -0,0 +1,227 @@
+  0x1f,0x8b,0x08,0x08,0x9c,0x03,0x94,0x3f,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x48,0x65,
+  0x72,0x5f,0x4c,0x6f,0x67,0x6f,0x5f,0x33,0x32,0x30,0x78,0x32,0x34,0x30,0x5f,0x6d,
+  0x69,0x74,0x74,0x65,0x5f,0x31,0x36,0x67,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9c,0xfd,
+  0x6b,0x1b,0x47,0x1a,0xc7,0x9f,0xae,0xa2,0xe8,0x8c,0x4b,0x42,0xff,0x03,0xb1,0x26,
+  0x2f,0x26,0xa5,0x67,0x2c,0x52,0xd7,0xf8,0xb8,0x1e,0xb1,0xfb,0x62,0xc2,0x81,0xa9,
+  0xa3,0xe6,0x42,0x43,0x02,0x21,0xf1,0x35,0x57,0x38,0x4c,0x8a,0xbd,0x71,0x1d,0xe2,
+  0xa3,0x70,0x89,0x4c,0x8f,0x62,0xdc,0x4b,0xed,0x8d,0x84,0xfd,0xd3,0x71,0x77,0x0e,
+  0x94,0x90,0x50,0x7c,0x3a,0x09,0x29,0xb4,0xe4,0x87,0x9c,0x85,0xfc,0x17,0x14,0x42,
+  0x8a,0x31,0xc5,0x62,0xd7,0xb4,0x04,0x63,0x24,0x76,0xee,0x79,0x66,0x66,0x57,0x2b,
+  0xeb,0xd5,0x24,0x75,0x0b,0x9d,0x2f,0x28,0xfb,0x36,0x3b,0xf3,0xd9,0x67,0xe6,0x79,
+  0x66,0x76,0x66,0x9d,0x13,0xbf,0x1f,0xff,0x1c,0xb8,0xc6,0xf1,0x77,0x14,0x7f,0xbf,
+  0x7b,0x01,0x60,0x13,0xb7,0x2f,0xc0,0x3e,0x70,0x15,0x6b,0x17,0x3f,0xbf,0x5e,0x7a,
+  0xe9,0x25,0xd0,0x75,0x1d,0x22,0x91,0x08,0x0c,0x0c,0x0c,0x40,0x34,0x1a,0x85,0x91,
+  0x91,0x11,0x30,0x0c,0x03,0x62,0xb1,0x18,0x98,0xa6,0x09,0x4b,0x4b,0x4b,0x90,0x4a,
+  0xa5,0x20,0x97,0xcb,0xc1,0x37,0xdf,0x7c,0x03,0x96,0x65,0x01,0x63,0x8c,0x7e,0x4a,
+  0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,
+  0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,
+  0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0xbf,0x6c,0x95,0x72,
+  0xf9,0x9f,0x1a,0xa1,0xa1,0xbe,0x87,0xd0,0x4f,0x8d,0xd0,0x50,0x9b,0x8a,0xef,0x99,
+  0xa4,0xf8,0xb8,0x9c,0xdd,0xdf,0xe1,0xd8,0xb4,0x21,0x3e,0xb1,0x87,0xb2,0xaa,0x53,
+  0xd9,0x55,0xa7,0x76,0xc8,0xb2,0x5b,0x48,0xe9,0xd8,0x56,0xd3,0x8c,0x2a,0xf5,0x34,
+  0x0c,0x10,0xc8,0x72,0xbe,0xfb,0x00,0xbf,0xa1,0x3c,0x70,0x0b,0x93,0xec,0x07,0x9d,
+  0x6b,0x75,0x5b,0x3f,0xc6,0x9c,0xaf,0x00,0x12,0xf7,0xf4,0x29,0xa7,0x5b,0xb7,0xd9,
+  0x6c,0x47,0x96,0x6d,0x77,0x77,0x32,0xf6,0xad,0x7e,0x8e,0x15,0xaf,0x80,0xb6,0x3a,
+  0x7b,0x88,0x3d,0x04,0x71,0xf3,0xc6,0x10,0x40,0x90,0xe9,0x3a,0xe6,0xf8,0x8e,0x3e,
+  0xc5,0x66,0x71,0xe7,0x89,0xfe,0x3a,0x63,0x9f,0xe9,0xbf,0xc6,0x47,0xc0,0x8b,0x81,
+  0x38,0x2b,0xe9,0x47,0xb0,0x14,0xbd,0xa3,0x25,0x52,0xfa,0x93,0x1d,0x02,0xdc,0x84,
+  0x20,0xee,0x68,0x98,0xef,0x53,0xfe,0x67,0x3a,0x18,0x70,0xb8,0xec,0x2d,0x68,0x67,
+  0x5b,0xf4,0x10,0x33,0x30,0xe5,0xe0,0x31,0x9b,0xd1,0x16,0xd9,0x76,0xb8,0x8d,0xb1,
+  0x27,0x70,0x0e,0x7f,0x00,0x47,0x46,0x83,0xec,0x01,0xdd,0x7c,0x9d,0xb1,0x2e,0x20,
+  0x3e,0x00,0xcc,0x67,0x08,0xce,0xb3,0x19,0x58,0xc4,0x9c,0x11,0x6d,0x16,0x0e,0x32,
+  0xe7,0x0a,0x2f,0x8b,0x95,0x20,0x68,0x33,0x07,0xb4,0x16,0xf9,0x0e,0x75,0x03,0x1c,
+  0x20,0x4e,0x2d,0x1a,0xc6,0xbc,0xb1,0x88,0x4e,0x73,0x8c,0xf3,0x91,0xfd,0xec,0x6d,
+  0xe4,0xdb,0x84,0x80,0x89,0x25,0x2f,0x56,0xf1,0x39,0x43,0xd0,0x33,0x07,0xd8,0x34,
+  0x1e,0xf7,0x24,0x47,0xf1,0x66,0x7c,0xb6,0xd0,0x87,0x15,0x7c,0x59,0xf6,0xd8,0xe5,
+  0x2b,0x02,0x4c,0xcc,0x0d,0x69,0xc4,0xc7,0x5a,0xe7,0xeb,0x4d,0x27,0xc3,0xf0,0x22,
+  0xf1,0xf5,0x59,0x33,0xa0,0x61,0x2e,0x58,0x7e,0x61,0x88,0xfd,0x80,0xb9,0x99,0xa6,
+  0xc9,0xf9,0x1e,0x40,0x1f,0xbb,0x5f,0x93,0xaf,0x0b,0x32,0xf8,0x0b,0xb1,0xb5,0x3c,
+  0xde,0xa0,0xb1,0xaf,0x20,0x30,0x55,0x34,0xed,0xda,0x7c,0x6b,0x64,0xb7,0xf5,0x8e,
+  0xdd,0xf1,0x15,0x31,0xd5,0xd7,0x10,0xb2,0x91,0x8f,0x8a,0x00,0xcc,0xa5,0x1d,0xef,
+  0x2e,0xb0,0x62,0x17,0xbc,0x4c,0x09,0x88,0xef,0x2e,0x16,0x83,0x6c,0x8b,0xac,0x8a,
+  0x2f,0x0c,0x96,0xbd,0x4e,0xae,0x45,0x09,0xc1,0x19,0xc5,0x27,0x45,0x27,0xa8,0xcd,
+  0x77,0x17,0xae,0x3b,0xcc,0xd9,0xd8,0x1d,0x9f,0x40,0x08,0xac,0x6e,0xe2,0xd3,0xb3,
+  0x52,0x17,0xac,0x8e,0x52,0x76,0xa4,0xef,0x09,0x46,0xf0,0x3d,0x80,0x29,0xaa,0xf7,
+  0x6c,0x2d,0xfb,0x61,0x53,0xea,0xe2,0xa1,0x89,0x1e,0x2e,0x8c,0x4c,0xa8,0x1d,0x7c,
+  0x07,0x05,0xdf,0x90,0xfc,0xfb,0xb1,0x12,0x85,0xb2,0xdd,0xf0,0x6d,0x71,0xbe,0x00,
+  0xde,0x34,0x04,0xd9,0x51,0x78,0xdd,0xe2,0x61,0x60,0x9b,0x0c,0x26,0xf8,0x1e,0x63,
+  0xfd,0x62,0xf6,0xd5,0x7c,0x74,0x12,0xc9,0x89,0xaf,0x70,0x17,0x9f,0x10,0xe8,0x41,
+  0xea,0xf0,0x61,0x85,0x60,0xbe,0x8e,0x6d,0xef,0x9a,0x0f,0x5b,0xb6,0x2d,0xe2,0x33,
+  0xfa,0xdb,0x90,0xf0,0xdb,0x73,0x0c,0x63,0x86,0x26,0xf9,0xc8,0x7f,0x23,0xc0,0xf9,
+  0x58,0x25,0xdf,0x63,0x74,0xab,0x48,0x18,0xeb,0xf7,0x1d,0xbc,0xe7,0x98,0x00,0xab,
+  0xe2,0x13,0xf5,0xbb,0x1d,0x16,0x39,0x4f,0xb9,0xf5,0xdb,0x2a,0xde,0x32,0x70,0x17,
+  0xad,0xe2,0x73,0x78,0x31,0xc4,0xe7,0xdc,0xe5,0xe7,0x6a,0xd8,0xaf,0xc8,0x93,0x87,
+  0xc8,0xd8,0x10,0xca,0xd4,0xe1,0x93,0xf6,0x93,0x7c,0x8b,0xbb,0x6b,0x7f,0x5b,0x14,
+  0xb2,0xce,0x33,0x5e,0xbf,0x16,0xaf,0xdf,0xdf,0x5a,0xd6,0x77,0xbc,0x9e,0xbe,0x86,
+  0xe0,0x2a,0xe7,0x63,0x8e,0x95,0x5b,0xa1,0xaa,0xe4,0x7c,0x78,0x6d,0x1b,0x2d,0x6e,
+  0x7d,0x4b,0x0f,0xc1,0xac,0x95,0xd4,0x50,0x08,0xdb,0x7e,0xe0,0xba,0xcd,0xca,0xf5,
+  0x3b,0x45,0xed,0xd5,0xc7,0x37,0x03,0x07,0x4b,0x43,0xf4,0x77,0x8c,0x8f,0x21,0x5b,
+  0x22,0xb4,0x96,0xf9,0xee,0x8a,0xb0,0xbc,0x49,0x55,0x87,0x4d,0x64,0x75,0x06,0x5e,
+  0xa1,0x16,0xb9,0xc8,0xab,0x96,0xa3,0xb4,0x8b,0x84,0x5e,0xfb,0x43,0x2c,0xf2,0x28,
+  0x6e,0x3f,0x92,0xc3,0xf9,0x8e,0x51,0x71,0x5d,0xf0,0xba,0xe0,0x3b,0xcf,0xb8,0xaf,
+  0x08,0xbe,0x03,0xd4,0x84,0x0e,0xa2,0x73,0xe3,0xa5,0x07,0x80,0xed,0x0f,0x56,0x5b,
+  0x8f,0x2f,0x64,0xf5,0x04,0xef,0x47,0x6c,0x8c,0x2d,0x60,0x3f,0xa4,0xec,0xee,0x63,
+  0x0e,0xbc,0x9c,0x03,0x82,0x8f,0xb2,0x0a,0xc3,0xaa,0xe4,0x7b,0x19,0xf9,0xb1,0x92,
+  0xc9,0xab,0xa9,0xb7,0x75,0xb0,0xb2,0x67,0x84,0xe1,0x46,0xe9,0x66,0x7e,0x9f,0xcd,
+  0x8d,0x48,0x7c,0x9b,0xd0,0x46,0x0f,0x47,0xf1,0x25,0xc3,0x9c,0x19,0x40,0xff,0xc5,
+  0x2b,0x25,0x08,0xb4,0xda,0xbf,0xf5,0xd8,0x62,0x1b,0x9c,0x18,0xc2,0x46,0xeb,0x74,
+  0x69,0xd7,0x1e,0xe1,0x76,0x3b,0x1a,0x1d,0xee,0xc2,0x6a,0xe4,0x7c,0x57,0x4e,0xe7,
+  0x6e,0xe1,0xbe,0xe4,0x03,0xea,0x4c,0x42,0x26,0xc0,0x02,0xdb,0xd2,0x26,0xb1,0xe2,
+  0x0f,0x60,0x60,0x0e,0x26,0x96,0xcf,0xb2,0x6f,0x01,0x7a,0xe7,0xce,0x22,0x9a,0x76,
+  0x66,0x8c,0xac,0x24,0xec,0x07,0x3d,0xb7,0x00,0x0d,0xbb,0x05,0xc1,0xdc,0x3d,0xde,
+  0xbf,0x61,0x51,0x5d,0x44,0xdd,0x82,0x1e,0x43,0x20,0x23,0x38,0x35,0xd1,0xd2,0xc9,
+  0x9b,0xbb,0xb1,0x05,0x6f,0xf1,0xc6,0x1c,0x14,0xf6,0x1b,0x85,0xe3,0x80,0x19,0x4a,
+  0xbe,0x30,0x26,0xd5,0x00,0x0d,0x9f,0x21,0x43,0x0e,0x03,0xda,0x06,0x83,0xdf,0xa1,
+  0xae,0x17,0xb9,0x9b,0x84,0xdb,0x91,0x8f,0x92,0x04,0x6c,0x97,0x8f,0xbb,0x2d,0x71,
+  0x1d,0xc7,0xce,0x13,0xb7,0x1a,0x15,0xd6,0xd7,0x12,0xdf,0x03,0x19,0x8e,0x37,0xa1,
+  0x13,0x8d,0x82,0x1d,0x10,0x0f,0x26,0x98,0xad,0xe4,0xe3,0xf6,0xc3,0x5a,0x41,0xa2,
+  0xf3,0x92,0x2f,0xb4,0x8e,0x07,0x0b,0x33,0x3c,0x35,0x0f,0x1a,0x21,0x6c,0x0c,0x14,
+  0x5f,0xf0,0x41,0x3e,0x03,0x7a,0x0e,0x00,0x1a,0x03,0x65,0xe8,0xb9,0x16,0x91,0xef,
+  0x74,0x58,0xd0,0x7c,0x49,0x69,0x2d,0xe4,0x6b,0xc3,0x9b,0x5b,0x74,0x0f,0x97,0x6f,
+  0xcb,0xb8,0xf6,0xdd,0x3b,0x87,0xa6,0x70,0xcf,0x59,0xeb,0xee,0x98,0xb4,0xd8,0xb6,
+  0x41,0x9a,0x60,0x45,0x63,0x12,0x87,0x4d,0x63,0xdd,0x91,0x04,0xf7,0x4f,0x9b,0x2d,
+  0x4f,0xd8,0x63,0x1d,0x7d,0xf6,0xf6,0x70,0x07,0x02,0x38,0x1b,0x51,0xfd,0x38,0x8e,
+  0x5b,0x58,0x61,0x58,0xef,0xa1,0xed,0x97,0xdd,0xc7,0x27,0x31,0x59,0xe6,0xbe,0x7e,
+  0x1a,0x8f,0x96,0x8d,0x55,0xb6,0x6e,0x2c,0x2c,0x77,0x1f,0xa7,0x21,0xa5,0x3d,0xa6,
+  0x1f,0x5f,0xc0,0xad,0x31,0x59,0xfc,0x50,0xbf,0xd6,0x1a,0x1f,0xf7,0x7e,0xa9,0x62,
+  0x5a,0x6c,0x93,0xa9,0xea,0x74,0xfc,0x9c,0x23,0xba,0x3c,0x56,0x8a,0x67,0x91,0x59,
+  0xa4,0x2e,0xa5,0x56,0xc5,0xcd,0xa9,0x2c,0x3f,0x4c,0x66,0xc9,0x35,0xb2,0xee,0x69,
+  0xc6,0x47,0xac,0xa9,0x2c,0x1f,0xb6,0xf2,0xfb,0x48,0x76,0xb1,0x46,0x11,0x75,0xf8,
+  0xda,0x1c,0x7b,0x25,0xdb,0x5a,0x62,0xde,0x7f,0xb4,0x20,0x19,0xa6,0x9f,0x87,0x70,
+  0x14,0xd0,0x31,0x2c,0x7a,0xf5,0xda,0x2a,0x9a,0x09,0x6f,0xdf,0xb5,0x5f,0x33,0x79,
+  0x7c,0x49,0x73,0xb5,0x61,0xc2,0xe6,0xc2,0xa8,0x09,0x20,0xa2,0x6a,0x6d,0x79,0xf1,
+  0x59,0x14,0xbc,0x3b,0xbe,0x51,0x1e,0xe7,0x9f,0x49,0x3f,0x70,0xbe,0xfa,0xc5,0x6e,
+  0xf9,0xf8,0x76,0x6d,0xbf,0x99,0x67,0xe7,0x73,0x96,0x87,0x8f,0x4f,0x34,0xa8,0x05,
+  0xbf,0xfd,0x70,0x38,0xba,0xe7,0xf6,0x6b,0x2a,0x9f,0xf3,0x38,0x63,0xd1,0x96,0xf8,
+  0xa2,0x51,0xf9,0xc0,0x85,0xdc,0x2e,0x5f,0x27,0x9f,0x51,0xcd,0x5f,0x83,0xb9,0xac,
+  0xea,0x17,0x68,0x25,0x25,0x25,0xa5,0x5f,0x9e,0xf6,0x36,0x42,0x3f,0x77,0xd5,0x9e,
+  0x51,0x75,0x0a,0x49,0xe3,0x47,0xd7,0x55,0xb3,0xb9,0xe2,0x59,0xab,0xba,0x53,0x2a,
+  0xde,0x82,0x3d,0x92,0x3e,0x10,0x69,0xa6,0xee,0x23,0xf1,0x1d,0x80,0xc5,0xa1,0xbd,
+  0xc2,0x23,0xc0,0xa6,0x8a,0x44,0xae,0x55,0xe0,0xf1,0x19,0x8d,0x3d,0x93,0xf6,0xe6,
+  0x48,0x63,0x5d,0x42,0xc2,0x41,0xff,0xb4,0xf9,0x95,0xbd,0xc4,0x03,0x38,0x6c,0x18,
+  0x7f,0x6c,0xd0,0x48,0x47,0x46,0x2e,0x0e,0xf4,0xeb,0x9f,0x96,0xf9,0xd6,0xf7,0x16,
+  0x0f,0xb4,0xf7,0x63,0x8d,0x74,0x13,0x09,0x07,0x22,0x9d,0xde,0x88,0xac,0xa8,0xef,
+  0x31,0x1f,0xec,0x6f,0xc8,0x87,0x32,0x46,0x06,0xfa,0x5f,0x76,0x0d,0xf8,0xf5,0x9e,
+  0xf3,0x35,0x31,0x20,0x6a,0xfc,0x52,0xff,0xab,0x72,0xc4,0xed,0xe8,0xe1,0xbd,0xe6,
+  0x6b,0x6e,0xc0,0x98,0x71,0xb1,0x5f,0xce,0x7a,0xaf,0x77,0xef,0x3d,0x9f,0x76,0xb9,
+  0x19,0xdf,0xcd,0xf1,0x8b,0xaf,0xf1,0x16,0xb8,0x1d,0xe9,0x6e,0x94,0x53,0xcf,0x84,
+  0x11,0xfe,0x31,0x00,0xe7,0x9b,0x03,0xf6,0x0f,0x12,0xdf,0x53,0x1f,0x1f,0xfd,0x2f,
+  0x73,0x74,0x33,0x6e,0x25,0x54,0x67,0x96,0xb1,0xe5,0x2e,0xef,0xaa,0xce,0xaf,0x68,
+  0xba,0xee,0xed,0xbb,0xe5,0xc9,0x03,0xff,0xd6,0x4d,0xe1,0x65,0xe7,0xbf,0xa1,0x69,
+  0x05,0xc7,0xc6,0xfb,0x5f,0x25,0x0f,0x59,0x1b,0xf6,0xf8,0xda,0x32,0x16,0x2d,0xd8,
+  0x41,0x5b,0x9a,0x66,0x85,0x49,0x21,0xee,0x43,0xeb,0x3c,0xd7,0x5e,0xbc,0x4a,0x7a,
+  0x02,0x67,0xf2,0x96,0xd4,0x9a,0x7b,0x6b,0x2f,0x9e,0x7a,0x40,0xcf,0xb3,0x60,0x59,
+  0x5b,0x88,0x34,0xe9,0xa6,0x98,0x11,0xd9,0xd2,0x74,0x5c,0x27,0x1e,0x6e,0xba,0x37,
+  0x34,0xad,0xe0,0xd8,0x8d,0x8b,0x27,0xc8,0x3b,0x6e,0x95,0xf9,0xda,0xb3,0xf4,0xfe,
+  0x4c,0x19,0xca,0x55,0xc2,0x3e,0xe9,0xe2,0x7c,0xca,0xb7,0x37,0x2b,0x0e,0xbe,0x87,
+  0x5e,0x2f,0x74,0x3e,0x2d,0xf3,0x31,0x3e,0xed,0x18,0x5a,0xa0,0xf9,0x05,0xd0,0xbc,
+  0xb9,0x32,0xe2,0xcb,0x8a,0x39,0xed,0x84,0x38,0x14,0x6a,0xee,0x21,0xb1,0xf1,0x81,
+  0x4f,0xb1,0xe8,0xb1,0x53,0x7a,0x5d,0xbe,0x45,0x46,0x6f,0xae,0xb6,0xc8,0xb6,0x37,
+  0xe3,0xf1,0x49,0xc7,0xb7,0xec,0x2d,0xf7,0xd6,0xd7,0x7c,0x7c,0xdb,0x64,0xbf,0x6a,
+  0x3e,0x2d,0xed,0xce,0xed,0x90,0xf6,0xb5,0xc0,0x77,0xea,0x24,0x3e,0xec,0x78,0x99,
+  0x8f,0x32,0x9a,0xf1,0xf1,0x75,0x62,0x21,0x85,0x54,0x3c,0xed,0xf0,0x49,0x51,0xce,
+  0xb7,0x92,0x4a,0xdd,0x13,0x7b,0x56,0x0a,0xf5,0xa5,0x7b,0xeb,0x91,0x4a,0x3e,0x78,
+  0x8f,0x66,0xc9,0x31,0x71,0xaa,0xcc,0x17,0xca,0x33,0xe6,0x3d,0x4f,0x2b,0x0d,0xf0,
+  0xc6,0xc8,0x80,0x5d,0x9b,0x2f,0xcd,0x67,0xd9,0x00,0xcb,0x72,0xb6,0x71,0x44,0x96,
+  0xe1,0xcb,0x31,0x3d,0x44,0x95,0x34,0xcd,0x59,0xe8,0xa1,0x79,0x48,0x8b,0xc6,0x6a,
+  0xb7,0x1a,0xf1,0x95,0x30,0xb1,0x39,0x2a,0xb2,0xc5,0xb6,0xd9,0x6e,0x33,0x77,0x09,
+  0xb9,0x35,0xbe,0x9b,0x23,0xfd,0xd8,0xf6,0x8d,0x53,0xe1,0x7a,0x7c,0x18,0x7f,0x9c,
+  0xa4,0x11,0x33,0x13,0xb6,0xb3,0x56,0xc1,0xc7,0x87,0x67,0x54,0xfa,0x5f,0x77,0xf2,
+  0xed,0xf7,0xf1,0x15,0x2a,0xf9,0x5e,0xb4,0x65,0xab,0x11,0x6a,0xee,0x20,0xe8,0xc1,
+  0x36,0x4b,0xce,0xf9,0xf8,0x32,0xb4,0xec,0x84,0x46,0x48,0xf3,0x49,0xb6,0x10,0xf2,
+  0xad,0x63,0x6c,0x39,0x1d,0xe7,0x6b,0xa9,0x47,0xf0,0xaa,0xf0,0xd7,0x80,0x99,0xb1,
+  0x7d,0x35,0xc5,0x9b,0x7b,0x46,0xf0,0x05,0x91,0xaf,0x88,0xdb,0x93,0x7c,0x6a,0xba,
+  0xfc,0xd8,0x78,0xed,0x15,0xc6,0x31,0xbd,0x27,0x6a,0xc1,0x80,0x17,0x17,0x1c,0x73,
+  0x07,0x1f,0x4d,0xb3,0xff,0x4a,0xf0,0xd1,0xfa,0x0f,0x95,0x19,0x98,0xc8,0xd0,0x5a,
+  0x0c,0xf1,0x49,0x7f,0x9d,0x88,0x5b,0x4e,0xe5,0x98,0x2c,0x98,0x17,0xc6,0x09,0x66,
+  0x04,0x5f,0x5f,0x35,0xdf,0x39,0xbf,0xfb,0xe2,0x13,0x4d,0xb7,0xc0,0xf7,0xe7,0x9a,
+  0x7c,0xed,0x16,0x27,0xc1,0x31,0xac,0xc3,0x43,0x73,0x5b,0x82,0xec,0x7a,0xe4,0x0b,
+  0xaf,0x7d,0x07,0xd1,0x80,0x4e,0x05,0x5f,0x48,0x56,0x1e,0xd9,0xbc,0x24,0xf9,0xdc,
+  0x7c,0x89,0xef,0x09,0x2d,0xdc,0x95,0x4f,0xa1,0xb4,0xe6,0xf6,0x8b,0x8d,0x9c,0x2c,
+  0x99,0x73,0xd1,0xb2,0x7f,0x64,0x68,0x05,0x50,0xb4,0xe4,0xa7,0x10,0x48,0x08,0x53,
+  0x60,0xa1,0x09,0x9b,0x3d,0xe4,0x55,0x27,0xf9,0x34,0x03,0xcf,0x54,0xbc,0x12,0xd0,
+  0x52,0xe7,0xa6,0xe4,0x74,0x6a,0xf2,0xb5,0xd9,0x6e,0x76,0xbb,0xe0,0xeb,0x2b,0xc5,
+  0xe7,0x2e,0xf9,0xfa,0x0f,0xc6,0x36,0xb0,0x4d,0xd3,0x8a,0xc4,0x16,0x04,0xd3,0x72,
+  0xaa,0x17,0x02,0x9f,0xd0,0xda,0x74,0x50,0x36,0x7d,0x52,0x0f,0x56,0xf9,0xb6,0x57,
+  0xd2,0x19,0x93,0xcf,0x98,0x93,0xab,0xc7,0x25,0xdf,0x31,0x4b,0x38,0x90,0xf9,0x19,
+  0x5f,0x65,0x65,0x6b,0x3a,0x35,0xbf,0xfb,0xfe,0x47,0x6a,0x81,0x6f,0x7c,0xb0,0x94,
+  0xfa,0xcf,0x58,0x05,0x9f,0xf7,0x4a,0xc2,0xbd,0x44,0xc4,0x03,0x8a,0xb6,0xa5,0x0a,
+  0x3e,0x6d,0x22,0x61,0x39,0xae,0x7d,0xb4,0x1d,0x0b,0x2b,0x2e,0x1f,0xd7,0x9a,0xe0,
+  0x73,0x28,0xca,0x3b,0xbb,0xe7,0x2b,0xa6,0x92,0x8d,0xf8,0x64,0x3c,0x78,0x8f,0x56,
+  0x67,0xfd,0x7c,0xd0,0x1b,0x77,0xec,0x2b,0xbb,0xe0,0x13,0x17,0x36,0x86,0x76,0xc9,
+  0x77,0x79,0x23,0x95,0x34,0x3c,0xbe,0xd0,0x17,0x8c,0x7f,0x70,0xe4,0x58,0x44,0x12,
+  0x8a,0x7b,0x7c,0x7d,0xc4,0x17,0xf0,0xf3,0x05,0x27,0xd2,0x9e,0x87,0x68,0x93,0xf2,
+  0x23,0x25,0xc7,0xe2,0x9d,0x21,0x9d,0x6f,0xcb,0xcb,0xe3,0x2d,0x11,0x73,0x28,0x5b,
+  0xca,0xb5,0x6b,0x57,0x7c,0xc6,0xe5,0x52,0x2a,0x79,0x33,0xe2,0xf1,0x51,0x46,0x05,
+  0xec,0x94,0xf2,0x3b,0xf8,0xce,0x52,0xb4,0x08,0x2c,0xd8,0xbe,0x06,0xde,0x63,0x5a,
+  0x6c,0xd4,0xe5,0x13,0xb7,0xf0,0x2e,0x2f,0x63,0x7b,0x7c,0x4e,0x11,0x8f,0x1f,0x4a,
+  0x3e,0xca,0xd6,0x12,0xe3,0x84,0xd6,0xf9,0x6e,0x5e,0x2e,0xa5,0x57,0xe6,0x87,0xc3,
+  0x7e,0xbe,0x47,0xa2,0x95,0x17,0xc3,0xc1,0xdb,0xb6,0x1b,0xef,0xae,0x93,0xeb,0x55,
+  0xf2,0x05,0xe7,0xd2,0x76,0x49,0x56,0xd7,0x1f,0xa8,0x0f,0x24,0xf7,0x94,0x0e,0xe2,
+  0xf2,0x3d,0x12,0x3d,0x20,0xe7,0x23,0xbf,0x4b,0xf8,0x06,0x3c,0xad,0xf1,0x7d,0xe0,
+  0xa4,0x57,0xcc,0x61,0xdd,0xc7,0xe7,0xd0,0x2c,0x0c,0xf1,0x75,0x05,0x4d,0x5b,0xc6,
+  0x13,0x8d,0x77,0x0a,0x5a,0x05,0x9f,0x46,0x89,0xa4,0x35,0x4e,0xe3,0x2d,0x69,0x5b,
+  0xdc,0xfa,0x49,0x99,0xaf,0xb0,0x8c,0xc7,0x63,0x82,0xcf,0x79,0x64,0x18,0x57,0xe3,
+  0xbe,0x06,0xd2,0x52,0x7c,0xe1,0x7c,0xc9,0x31,0x3f,0x1f,0x11,0x04,0x38,0x5f,0xc0,
+  0xcc,0xb3,0x12,0x37,0x2d,0x85,0xd6,0x2d,0xd0,0x12,0x36,0x0f,0xbd,0x52,0x87,0xcc,
+  0xbc,0x0c,0x3f,0xbc,0xb4,0xb4,0x7c,0x98,0xf7,0xca,0x7c,0xb3,0xf2,0xda,0x3e,0x6a,
+  0xb8,0x98,0x51,0x47,0xc2,0x1f,0x01,0x91,0x6f,0x7a,0xde,0x6c,0x02,0xf8,0x01,0x4b,
+  0x17,0x52,0x63,0x11,0x59,0xc1,0x6e,0xe7,0xa9,0x21,0x1f,0xd6,0xdd,0x60,0x5a,0xb6,
+  0x17,0xfa,0x82,0x60,0x96,0xf3,0xf9,0x3b,0x8d,0x78,0xde,0xdf,0x5f,0x25,0xaa,0xf9,
+  0xdc,0x8b,0x01,0xc9,0x07,0x79,0xbe,0xde,0xe4,0x52,0xc7,0x3e,0xd7,0xbb,0xb5,0xcb,
+  0x8d,0xdf,0x43,0xae,0xb3,0x5c,0x21,0x35,0xe7,0xe7,0x2b,0x49,0x3e,0x67,0x08,0x63,
+  0x08,0xe3,0x5f,0xcb,0xd1,0x7a,0x35,0x1e,0xc2,0x0e,0xbe,0xb3,0x16,0x73,0x57,0xea,
+  0x7d,0x7c,0xb2,0xe3,0xa5,0x50,0xe5,0xfa,0x02,0x6f,0xb8,0x54,0x84,0xed,0xe7,0xdb,
+  0x3f,0x3d,0x7b,0x24,0x76,0xe1,0x68,0x63,0xfb,0x7d,0xca,0x0a,0x56,0xce,0x8c,0xca,
+  0x37,0x4c,0xde,0x50,0xb8,0x69,0x6c,0x1a,0xe9,0x06,0xb1,0x06,0x69,0xe0,0x77,0x86,
+  0x5c,0x13,0xcf,0x5e,0xf3,0xf5,0xf9,0x20,0x96,0xe3,0x4b,0x5e,0x40,0x4b,0xd8,0xa2,
+  0x6d,0xc9,0x8e,0x8d,0xf8,0xee,0xf9,0xf9,0x30,0xb0,0x1c,0x62,0xcc,0xd7,0x40,0xde,
+  0xbe,0x81,0x6c,0x23,0x17,0x1a,0xc0,0x99,0xf3,0xb1,0x3c,0xf2,0x15,0x92,0x6e,0x05,
+  0x7b,0x7c,0xe8,0xb9,0x14,0x3c,0xae,0x62,0xa3,0x2a,0x1a,0xa7,0xe9,0xb1,0xbf,0xab,
+  0xe0,0x8b,0xe7,0x50,0x2b,0x14,0x72,0x3d,0x03,0xde,0xa9,0xe6,0x2b,0xe0,0x3b,0x53,
+  0x6e,0x05,0xb8,0x63,0x61,0x28,0xcc,0x53,0xc8,0x2e,0xfb,0xc7,0xd5,0x8f,0x8f,0xbe,
+  0x39,0xaf,0xff,0xbd,0xfe,0x30,0x70,0xda,0x34,0x63,0xd8,0xce,0x2c,0x2b,0x65,0x48,
+  0x0f,0xa6,0x11,0x01,0xe7,0xfb,0x48,0xf2,0xc5,0x99,0x5c,0x60,0x73,0x1e,0x56,0xf0,
+  0xa5,0xbd,0xbe,0xc2,0xe3,0x8b,0x57,0xf3,0xb9,0x9d,0x09,0xf1,0xb9,0xf2,0x5e,0xf8,
+  0x20,0x76,0xe1,0xed,0x37,0xcd,0x7d,0x9f,0xbf,0x5d,0xdf,0x7c,0xa6,0x79,0x13,0x0d,
+  0x9e,0xb7,0x56,0x4c,0x69,0xc0,0x80,0xdb,0xc2,0x3e,0x12,0xaf,0x44,0xc1,0xe9,0x84,
+  0xc8,0xd9,0x79,0x44,0x71,0x7f,0xd2,0xe3,0x4b,0xd4,0xe4,0xe3,0xbe,0x79,0x6c,0x95,
+  0x7f,0xd2,0xd9,0x96,0x2e,0xf3,0x41,0xc2,0xe5,0x73,0x0a,0x5e,0x7c,0xd6,0x62,0x27,
+  0x62,0x03,0x17,0xde,0x32,0x0f,0xd7,0x73,0x10,0xd3,0xbc,0xbd,0x34,0x8d,0xb7,0xe4,
+  0xb1,0x82,0x0d,0xf1,0x8e,0x19,0xc0,0x61,0xa7,0x4d,0x3b,0x13,0x79,0xc7,0x26,0xef,
+  0x9b,0x30,0x33,0x54,0x29,0x4e,0x91,0x37,0xa5,0xc9,0xbc,0xb8,0x4a,0x30,0xf4,0xc1,
+  0x1d,0xfd,0xbc,0x01,0x7b,0x7c,0xd5,0xda,0xa0,0x6d,0x27,0x26,0x22,0xbe,0x94,0x4d,
+  0x9d,0x9d,0xc8,0xef,0x6f,0x16,0xef,0x34,0x2d,0xab,0x94,0xf4,0xda,0xeb,0xfe,0xf9,
+  0xfe,0xd8,0x89,0xee,0xf0,0x74,0x3d,0x3e,0xb4,0xde,0xd2,0x12,0x05,0x76,0xac,0x60,
+  0x34,0x20,0x07,0xd4,0xe8,0xf3,0x4d,0xce,0x87,0xfd,0x00,0x75,0x5e,0x01,0xc3,0xa4,
+  0xa6,0x96,0xfa,0x07,0x37,0xef,0x19,0x79,0x15,0xa0,0x3c,0x99,0xed,0x05,0x18,0x53,
+  0x5e,0x6c,0xc3,0x2d,0xff,0x96,0xc8,0x95,0xc8,0x4e,0xea,0x2f,0x5e,0xf5,0x0e,0xc6,
+  0x2e,0xbc,0xff,0x96,0xf9,0x71,0xec,0xe8,0x7c,0x6c,0xc7,0xfc,0xb8,0x68,0x7a,0xe6,
+  0xed,0x3b,0xa9,0xa4,0x2d,0xf8,0x72,0xc9,0xb9,0xe1,0x88,0xee,0xe3,0x3b,0x23,0x5e,
+  0x6c,0x00,0x8e,0x4e,0x9b,0xd8,0x6f,0x9a,0x62,0xa4,0xf2,0xec,0x7c,0x63,0xe5,0xe1,
+  0xc1,0xc4,0xf4,0xc7,0x83,0x51,0xe3,0xc4,0x8d,0xc1,0xf9,0xe9,0xda,0xd3,0xf8,0x4b,
+  0xa9,0x54,0x92,0x37,0x0a,0xb4,0xfb,0x4a,0x72,0x2e,0x1a,0xd1,0xc3,0xf4,0x81,0x12,
+  0xff,0xa6,0x09,0xff,0x91,0x7d,0x4a,0x10,0xf3,0x36,0x64,0xae,0x9a,0xbc,0x0a,0x10,
+  0xf6,0x8a,0x09,0x97,0x77,0x34,0x37,0x91,0xd8,0x96,0xd3,0xf8,0x92,0x7b,0xda,0x67,
+  0x9a,0xff,0xc4,0xf8,0x32,0x7d,0xe1,0xdf,0x75,0xe9,0x52,0xff,0xcd,0xb8,0x7c,0x85,
+  0x95,0x79,0x23,0x1a,0xe9,0xf6,0xa6,0x7d,0x08,0x4e,0xcc,0xea,0x84,0x03,0x11,0xf4,
+  0x1d,0xbd,0x4a,0x6e,0x91,0xd5,0x57,0xe4,0x75,0x7f,0x0a,0x77,0xb7,0x3c,0xaf,0x04,
+  0x97,0x6f,0x9b,0x4b,0x57,0xfe,0x74,0xe7,0x5f,0x87,0x97,0xb0,0x99,0xd5,0x10,0xbd,
+  0xfc,0xa7,0xa4,0x73,0x0a,0x03,0x8e,0x9d,0x8a,0x44,0xea,0x95,0xf6,0xdc,0xd5,0x11,
+  0x5f,0x4a,0xdd,0xb9,0x7f,0xd8,0x38,0x31,0x78,0xa7,0x1e,0x5c,0x7a,0x25,0x23,0xdd,
+  0x9e,0xa6,0x99,0x56,0x52,0xa6,0x71,0x29,0x1a,0x8d,0x9e,0xda,0xb1,0x12,0xf1,0xc6,
+  0x40,0x74,0x20,0xfa,0x46,0xf3,0x15,0x8b,0x5d,0xea,0x24,0x47,0x48,0xc6,0x52,0x75,
+  0x94,0xcb,0x61,0x64,0x77,0x3f,0x21,0x71,0x78,0x0d,0x23,0xa0,0x61,0x8c,0x10,0x23,
+  0xca,0x5b,0x8a,0x88,0xbe,0x1b,0x8d,0x5e,0x92,0x27,0xbd,0x2b,0xb8,0x79,0x57,0xae,
+  0x54,0xb8,0x2b,0x16,0xd1,0x2a,0xbd,0xeb,0xe6,0x50,0xb1,0x2b,0xee,0x7f,0x3f,0x4d,
+  0x1d,0xd0,0xff,0x72,0xf5,0x85,0xdd,0x5a,0xda,0x8b,0xea,0x18,0xa8,0x1c,0x22,0x4c,
+  0xd6,0x6e,0xab,0xcf,0x5f,0x19,0xab,0xb9,0x7c,0xdf,0xa1,0x38,0xc4,0x67,0xe5,0xea,
+  0x19,0xfb,0xf9,0xab,0x05,0xbc,0x42,0xa6,0xcc,0xc7,0x24,0x31,0x75,0xfa,0x3f,0x3e,
+  0x5c,0x2e,0x97,0x6f,0x48,0x56,0x65,0x3e,0xd9,0x04,0x7f,0x4e,0x2a,0xec,0xfc,0xd3,
+  0xb6,0x9f,0x1b,0x60,0xf5,0x12,0x3b,0x75,0xf8,0x96,0xe8,0xc8,0x6d,0xb7,0x3f,0x77,
+  0xc4,0x38,0xc0,0xf2,0x6f,0x7c,0xe7,0x9d,0xca,0xf3,0x4d,0x2f,0x57,0xca,0xa9,0x95,
+  0xab,0xd8,0x54,0xc1,0xb9,0x88,0x75,0x2e,0x3c,0x2f,0x59,0xf4,0xed,0x01,0xfe,0x53,
+  0x63,0x81,0x5c,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,
+  0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,
+  0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,
+  0xe9,0x67,0xac,0xff,0x03,0xdc,0x41,0xd4,0x19,0x76,0x96,0x00,0x00,
diff --git a/u-boot/board/esd/hh405/logo_320_240_8bpp.c b/u-boot/board/esd/hh405/logo_320_240_8bpp.c
new file mode 100644
index 0000000..c2c59c6
--- /dev/null
+++ b/u-boot/board/esd/hh405/logo_320_240_8bpp.c
@@ -0,0 +1,521 @@
+  0x1f,0x8b,0x08,0x08,0x72,0xd1,0xe2,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48,
+  0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x33,0x32,0x30,0x78,0x32,0x34,0x30,
+  0x5f,0x38,0x62,0x70,0x70,0x2e,0x62,0x6d,0x70,0x00,0xec,0x5d,0x0f,0x6c,0x1b,0xd7,
+  0x79,0xff,0x12,0x09,0xc5,0xc4,0xd2,0x01,0x26,0x0a,0x03,0x56,0x88,0x1e,0x59,0xa9,
+  0x14,0x43,0xa8,0xb6,0x10,0x08,0x72,0x4d,0x10,0xf4,0xe6,0x28,0x09,0x90,0x2a,0x02,
+  0x1c,0x69,0xe2,0x98,0x6a,0xbc,0xcd,0xa3,0x38,0x33,0x64,0x4c,0xd7,0x54,0xe4,0x36,
+  0xd3,0x6c,0xd4,0x70,0x9a,0xc0,0xf0,0xcc,0xce,0x73,0xb3,0x2d,0xd1,0x42,0x25,0xd0,
+  0x1c,0x29,0x11,0x27,0x42,0x15,0x25,0x81,0xf3,0x5a,0x36,0x54,0x77,0x66,0xa8,0x0e,
+  0x72,0xed,0x25,0x59,0x24,0xb4,0x69,0xfe,0xac,0x68,0xa7,0x85,0x4a,0x42,0xbb,0x89,
+  0x77,0x20,0xf6,0xbd,0x3f,0x47,0x1e,0x29,0xc9,0x8a,0x5d,0x2b,0x8e,0x8b,0xf7,0x3b,
+  0xfe,0xb9,0xf7,0xee,0xbd,0xef,0xde,0xfb,0xbd,0xdf,0xfb,0xbe,0x77,0xf4,0x9d,0xbc,
+  0xfb,0x81,0xb6,0x96,0xdb,0x80,0xa0,0xad,0x1a,0xc0,0x8a,0xdf,0x7f,0x88,0xc9,0x15,
+  0xfc,0xbe,0x0d,0x7e,0x87,0xe6,0x43,0xf3,0x6d,0xd0,0xb0,0x0d,0xe8,0x1b,0x58,0x51,
+  0xa8,0xbe,0xbd,0x1a,0x5a,0x8f,0x2e,0x43,0xfd,0xee,0x41,0x18,0x7a,0xfa,0x9f,0xa0,
+  0xfb,0xc1,0x6e,0x18,0xf9,0x8f,0x2b,0xd0,0xbc,0x77,0x04,0xbc,0x67,0x3e,0x84,0xba,
+  0x2f,0xee,0x84,0xc1,0xa3,0xc7,0xe0,0xe2,0xc5,0x57,0x61,0x64,0x7a,0x1e,0x9a,0xef,
+  0x6c,0x86,0xfa,0x7b,0x9e,0x84,0xc6,0xbd,0x73,0xd0,0xf1,0xd4,0x7b,0x70,0xf1,0x57,
+  0x0a,0x34,0x1e,0xbc,0x08,0x75,0x4d,0x3d,0x70,0xf6,0xdf,0x52,0xa0,0xaf,0x33,0x43,
+  0xf7,0xc1,0x13,0xd0,0xdc,0xf5,0x04,0x1c,0x4b,0xe6,0xa1,0xfd,0x1b,0x67,0xa1,0xfb,
+  0xe8,0x1c,0xcc,0x2d,0x2c,0x41,0xf0,0xd9,0x25,0x70,0xdc,0x7d,0x2f,0x34,0x3e,0xfa,
+  0x36,0xd4,0x7f,0xc5,0x0b,0x43,0x2f,0x9e,0x85,0xe5,0xf7,0x72,0x50,0xff,0x85,0x7a,
+  0x38,0x36,0x7a,0x11,0x96,0x7e,0xfe,0x36,0x0c,0xfd,0xeb,0xcf,0xa0,0xe3,0xe4,0x12,
+  0x9c,0xf8,0x9b,0x53,0xd0,0xfb,0xe7,0x7b,0xa1,0xb5,0x6d,0x07,0xe8,0x7f,0x7f,0x3b,
+  0x04,0x1f,0x09,0xc1,0xd9,0x9f,0x2a,0xd0,0xf1,0xe0,0x1f,0x43,0xfd,0x17,0x9b,0xe0,
+  0xec,0xbf,0x5f,0x84,0xc6,0x9e,0x97,0xa0,0xf1,0xb1,0x65,0xe8,0x9f,0xcc,0x43,0xfd,
+  0xfd,0x27,0xa0,0xf7,0x1f,0xde,0x84,0xe5,0xcb,0x1f,0x43,0xfb,0xe3,0xff,0x05,0x8d,
+  0x0f,0xcf,0x43,0xf5,0xe7,0x6b,0xa1,0xdd,0x77,0x02,0xea,0xda,0x82,0xf0,0xce,0xbb,
+  0xef,0xc2,0xd0,0xb9,0x8f,0xa1,0xff,0xd0,0x37,0xe1,0xec,0x1b,0x0a,0x8c,0xbf,0x14,
+  0x83,0xa1,0xe7,0x47,0xa0,0x7f,0xf4,0x2d,0xe8,0x3f,0x79,0x16,0xea,0xb6,0xf5,0x42,
+  0xfb,0xfd,0x5f,0x85,0xba,0x2f,0x98,0xe0,0xc4,0xcb,0x79,0xe8,0xf6,0x61,0x1f,0xbf,
+  0x36,0x0e,0xcd,0x9d,0xc7,0xc0,0x71,0x7c,0x19,0xa6,0x5e,0x55,0xa0,0x75,0xff,0x14,
+  0x9c,0x7d,0x79,0x0e,0x2e,0xbe,0xfb,0x31,0x38,0xec,0x0e,0xa8,0xb7,0x39,0xa0,0xf5,
+  0xaf,0xdf,0xc4,0x73,0x9f,0x06,0xef,0xb3,0x6f,0x42,0xdd,0x1d,0x75,0x30,0xfe,0xca,
+  0x0a,0xb4,0x3e,0x18,0x84,0xee,0x1e,0x17,0x34,0x6f,0xdb,0x06,0xad,0x07,0xd1,0xb6,
+  0xa1,0x0e,0xbc,0x78,0x8e,0xf9,0x57,0xb1,0x5f,0xa7,0xfe,0x0e,0x7a,0x7d,0x41,0x50,
+  0x0a,0x0a,0xe8,0xf5,0x7a,0x70,0x1c,0xfd,0x29,0x4c,0xfd,0xe4,0x23,0x70,0x3c,0x3c,
+  0x0e,0x75,0xb6,0x76,0x38,0xf6,0xed,0xe3,0x70,0xf1,0x8d,0x45,0x98,0x9a,0x49,0x42,
+  0x73,0xdf,0x59,0x78,0xe7,0x57,0xbf,0x84,0xf9,0x85,0xf3,0x70,0xec,0x29,0x6c,0xcb,
+  0xc0,0xcf,0x61,0xf9,0x83,0x0f,0x40,0xbf,0x75,0x07,0x34,0xda,0xb6,0xc1,0xfc,0x2b,
+  0x3f,0x86,0xc6,0x47,0xfe,0x13,0xea,0x9d,0x21,0x18,0x79,0xe5,0xff,0x60,0xf0,0xf0,
+  0xb7,0x60,0x7c,0x72,0x0a,0x86,0xce,0x4c,0x41,0xdd,0x5d,0x5e,0x68,0xfc,0xd3,0x59,
+  0xe8,0x8d,0x7e,0x08,0xcd,0xbb,0xbd,0xd0,0x8a,0xf6,0x83,0xff,0x92,0x07,0xbd,0xa5,
+  0x1d,0xba,0x9f,0xcd,0x43,0x63,0xd7,0x3f,0x42,0xc7,0xbd,0x1d,0xd0,0xe8,0xfc,0x13,
+  0xe8,0xde,0x3f,0x04,0xed,0x78,0xfc,0xd8,0x74,0x1e,0x8e,0x3d,0x3f,0x0f,0x8e,0x07,
+  0x07,0xa1,0xfb,0x3b,0x6f,0x82,0xf7,0xe1,0x20,0x78,0x8f,0x4e,0xc1,0xe0,0x53,0x67,
+  0xa1,0xfd,0xa1,0x7e,0x70,0x1c,0x5e,0x82,0x66,0x67,0x37,0xb4,0x23,0x1f,0xc7,0xbe,
+  0x33,0x0a,0xa7,0xff,0xfe,0x69,0x98,0x7f,0x5b,0x81,0xd3,0x67,0xe6,0x60,0xf0,0xf8,
+  0x10,0x0c,0x4d,0xce,0x41,0xeb,0xfd,0xdf,0x80,0xd3,0x49,0x1c,0x13,0x3c,0x57,0xeb,
+  0x63,0x17,0xe1,0x9d,0x0f,0x14,0xac,0x37,0x0f,0x43,0x2f,0x2f,0x43,0xf0,0x60,0x3f,
+  0x74,0x1c,0x47,0x1b,0x7d,0x53,0xd0,0x7e,0x12,0x35,0xb7,0xf5,0x0f,0xc0,0xe1,0x74,
+  0x42,0xff,0xd1,0x21,0xe8,0x3e,0x7e,0x11,0xba,0x07,0xc6,0xe1,0x9d,0xf7,0x50,0x4f,
+  0xbb,0x83,0x30,0x3e,0x3d,0x07,0x8d,0xf7,0x9e,0x00,0xef,0x5e,0x2f,0xcc,0x9d,0x7b,
+  0x05,0x3a,0x8e,0xa2,0xf6,0x02,0x3f,0x80,0x8e,0xbd,0x83,0xd0,0xd1,0xf1,0x00,0x9c,
+  0x4e,0x7f,0x08,0xbd,0x0f,0xf5,0x42,0xeb,0x5d,0xad,0xd0,0x7b,0xea,0x22,0x1c,0x3b,
+  0x7e,0x02,0xda,0x0f,0x4e,0xc1,0xc8,0x8b,0xe3,0x30,0xf7,0xf2,0x8f,0xe0,0xf4,0xa9,
+  0xef,0xc2,0xd2,0x1b,0x4b,0x90,0xff,0x20,0x0f,0x75,0x5b,0xb7,0x83,0xfe,0x73,0x7a,
+  0x18,0x3f,0x7f,0x05,0x82,0x2f,0xe2,0xd8,0x3e,0x8d,0x9c,0x84,0xcf,0xe3,0xf8,0x61,
+  0x5f,0xee,0xb9,0x07,0x1a,0xed,0x7f,0x06,0x23,0xc9,0x25,0x68,0xfc,0xd2,0x97,0xa0,
+  0xf9,0xaf,0x96,0x61,0xf0,0x7b,0x39,0x68,0x7c,0xe0,0x49,0xc8,0x7f,0x74,0x19,0x75,
+  0x7a,0x00,0x06,0x1f,0x1b,0x84,0xb9,0x37,0xf2,0x30,0x32,0x32,0x02,0xf5,0x77,0xf5,
+  0x42,0xb3,0x67,0x14,0x1c,0x07,0xc7,0x61,0xe9,0xbf,0x91,0xc7,0xaf,0x7e,0x17,0x46,
+  0xce,0x8c,0x83,0xf7,0xb9,0xf7,0xa1,0xae,0xf1,0x7e,0xe8,0xf0,0x0c,0x42,0xab,0x6f,
+  0x1c,0x3a,0x4e,0xfd,0x2f,0xd4,0xdf,0x7b,0x1a,0x1a,0x7d,0xf3,0xb0,0x84,0x73,0xe4,
+  0xc4,0x59,0x2c,0x3b,0xb0,0x0c,0x4b,0x6f,0x2d,0xc3,0xdc,0xcf,0x14,0xe8,0x7f,0x11,
+  0xfb,0xbf,0xad,0x03,0x5a,0x0f,0x2f,0x43,0x6b,0x0f,0xf2,0xfd,0x90,0x17,0xf5,0x82,
+  0x7a,0x7a,0x74,0x1e,0xea,0x7e,0xaf,0x11,0xbc,0xa7,0xe6,0x41,0x7f,0x47,0x3d,0x38,
+  0xbe,0xbd,0x0c,0xf3,0x3f,0x59,0x82,0x63,0xa7,0xa6,0x90,0x8f,0x41,0x68,0xde,0x3f,
+  0x0f,0xa7,0x7f,0x84,0x5a,0xdc,0x3b,0x04,0x5e,0x9f,0x0f,0xa6,0x26,0x13,0xd8,0xa6,
+  0x20,0x9c,0x98,0x5e,0x86,0xf6,0x07,0xfb,0xa1,0x1f,0x39,0x6e,0xdc,0xda,0x08,0xed,
+  0xce,0x76,0xd4,0xea,0x3c,0x6a,0xe9,0x1d,0xd4,0x8c,0x82,0x1a,0x19,0x84,0x11,0x1c,
+  0x9f,0xea,0xcf,0xe1,0x7c,0x47,0x9b,0x43,0xcf,0x3e,0x0f,0x5e,0xe4,0xc2,0x23,0x20,
+  0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
+  0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
+  0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
+  0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
+  0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
+  0x20,0x20,0x20,0x20,0x20,0x20,0x20,0xf0,0x19,0xc2,0x58,0x2c,0x16,0x73,0xde,0xec,
+  0x46,0xdc,0xc2,0x70,0x02,0x40,0xef,0xcd,0x6e,0xc4,0x2d,0x0c,0xc2,0xdf,0xf4,0xcd,
+  0x6e,0xc4,0x2d,0x8c,0x7e,0xe4,0xcf,0x72,0xb3,0x1b,0x71,0x0b,0x43,0xcc,0xdf,0x6b,
+  0x46,0x70,0xc6,0xef,0xd7,0xed,0xe3,0x09,0x36,0x7f,0xe5,0x86,0x90,0xce,0x54,0x2a,
+  0x21,0x37,0x60,0x09,0x9e,0x96,0x65,0xf5,0x45,0x53,0xec,0x0b,0x77,0xfa,0x42,0x0d,
+  0x6c,0x47,0x9b,0x2d,0xab,0x47,0x3d,0x95,0x3b,0x26,0x9d,0xdf,0x54,0x2c,0x8e,0xa9,
+  0x90,0xdf,0xae,0x39,0x5f,0x5f,0xc8,0x3f,0x63,0xd2,0x16,0x57,0x2d,0x69,0x0c,0x55,
+  0x18,0xf4,0x78,0x66,0x49,0xad,0x75,0x4f,0xb8,0x59,0xc8,0xa6,0x2e,0x49,0xa0,0x48,
+  0xee,0x54,0x81,0x9e,0x88,0xce,0x5f,0x43,0xa7,0xa4,0x48,0xd1,0x3c,0xe7,0x74,0x9f,
+  0x57,0xdf,0x95,0x04,0xc9,0x1c,0x9b,0xc2,0x36,0x5a,0xf5,0x69,0x75,0x1b,0x96,0x3d,
+  0x3a,0x57,0x5a,0xef,0x25,0xad,0xac,0xd2,0x4b,0x49,0x69,0xd8,0x20,0xc7,0xf5,0x69,
+  0xa7,0xc7,0xa3,0xd3,0xb3,0x6c,0x9b,0x3e,0x1d,0x27,0xb4,0x98,0xac,0x7a,0x7d,0x8e,
+  0x98,0x72,0x62,0xb5,0x15,0xfc,0xb6,0x8f,0xba,0x93,0x8a,0x39,0x67,0x5f,0x49,0xeb,
+  0xad,0x41,0x8f,0xc1,0xea,0xc6,0xf3,0x75,0x75,0xb2,0x16,0x78,0xec,0xf9,0xb4,0xa4,
+  0x28,0x92,0xb9,0xe0,0x99,0x71,0xe9,0xd3,0x19,0x9a,0xd7,0xa4,0xd7,0x5b,0x4d,0xc4,
+  0xb0,0x3e,0x4d,0x0c,0x67,0xd2,0x7a,0x17,0x1d,0x2e,0xbf,0x5e,0xaf,0x9f,0xa4,0x25,
+  0xfc,0xa3,0x51,0x29,0xa9,0x48,0xe9,0xd1,0x10,0x39,0x0f,0x36,0xc0,0x49,0xb3,0xe3,
+  0x69,0x7d,0xcf,0xa6,0xf2,0x67,0x03,0x15,0x29,0xd2,0x55,0xa2,0xbf,0x94,0xc4,0x32,
+  0xe2,0x54,0x21,0xa1,0xb4,0x5a,0x40,0xb2,0x7b,0x82,0xee,0x62,0x71,0x30,0xcb,0x1e,
+  0x7f,0x12,0xc0,0x46,0x8c,0x28,0xac,0x40,0x04,0x6b,0x62,0xbb,0xfd,0x0a,0xcb,0xae,
+  0xc6,0x2c,0xd2,0x4d,0x3b,0xd6,0x8a,0x11,0x5b,0x11,0x2c,0x94,0xc5,0xf4,0x7e,0x66,
+  0xc1,0x95,0xa1,0x56,0xb2,0xaa,0xc5,0x51,0x59,0x7b,0xbe,0x69,0x8f,0x0e,0xcd,0x8f,
+  0xd2,0x56,0xa6,0x00,0xdc,0xd8,0x3c,0x3f,0x30,0xc3,0xa3,0x68,0x78,0x86,0xe4,0x8f,
+  0xe1,0x99,0xf2,0x64,0xa7,0x4a,0x52,0x8d,0x0c,0x63,0x6a,0x17,0x7e,0x17,0x48,0xb6,
+  0x8c,0x67,0xee,0xdc,0x54,0xfe,0xbc,0xd8,0x14,0xb3,0x39,0x49,0xce,0x1c,0xc3,0xe6,
+  0x3b,0x29,0x13,0xee,0xcb,0x7a,0xf2,0x3d,0x41,0xfa,0x6e,0xc6,0x9d,0x74,0x93,0xad,
+  0x3a,0x4d,0xb8,0x30,0x11,0xfe,0x14,0xe9,0x17,0x12,0x22,0x2d,0x7b,0x42,0x8c,0xa8,
+  0x04,0x56,0x97,0xaa,0x6d,0xc3,0x49,0x62,0xc6,0x87,0x14,0x00,0xeb,0x15,0xf2,0xd7,
+  0x55,0xc6,0x5f,0x15,0xe3,0x6f,0x94,0x98,0x1c,0x1d,0x45,0x8b,0xf8,0x2d,0x7b,0x7c,
+  0x49,0x7d,0x93,0x8d,0x0e,0x5a,0x15,0x96,0x25,0xf4,0x25,0xf5,0x29,0xbd,0x54,0xf0,
+  0xe8,0xd0,0x7c,0xae,0xc8,0x1f,0x4e,0x07,0x1d,0xe7,0xaf,0x09,0xcf,0xa7,0xa3,0xfc,
+  0xf1,0x33,0x91,0x66,0x27,0xad,0x39,0x5b,0xca,0x4d,0xf9,0x2b,0x14,0xf9,0xeb,0x42,
+  0xfe,0x36,0x75,0x06,0x67,0x63,0x59,0xbb,0x2c,0xeb,0x72,0x84,0xb6,0x04,0xd3,0x1f,
+  0x51,0xa2,0x6c,0x49,0xb2,0x36,0xa2,0x3e,0x95,0xcc,0x2c,0x69,0x8a,0xa1,0xda,0x4e,
+  0x29,0x01,0xf3,0x98,0x9d,0x02,0x89,0x62,0xfa,0xab,0xc1,0x4c,0x32,0x2d,0x0b,0x84,
+  0x83,0x0e,0x8f,0x4a,0xab,0xa7,0x99,0x6a,0x76,0x95,0xfe,0x64,0x3d,0x80,0x1e,0xb5,
+  0x6d,0x22,0xc6,0xf4,0x78,0x38,0xe1,0xe1,0x7d,0xc6,0x42,0x0e,0x72,0x02,0x03,0x76,
+  0x79,0xa6,0xc1,0xe3,0x97,0xb4,0xfc,0xad,0xa5,0x3f,0x32,0x72,0xc8,0x9f,0x8c,0xa4,
+  0xbb,0xfb,0x49,0x86,0xa9,0x2a,0xa7,0xe5,0xcf,0x23,0x6d,0xb6,0xfe,0xd4,0xc1,0x39,
+  0x82,0xa7,0xac,0x61,0x03,0xe9,0xd6,0xa9,0x19,0x16,0x8f,0xc9,0xcc,0x74,0xa9,0x16,
+  0x35,0xc5,0x31,0xfb,0x72,0x90,0x57,0xe2,0x13,0x35,0xc3,0xe7,0xa9,0x67,0x02,0x0f,
+  0x8e,0xb1,0x6e,0x72,0xfd,0x49,0x6b,0xe8,0x4f,0xbe,0x04,0xd0,0x4c,0x92,0x0d,0x6e,
+  0xca,0x1f,0x03,0xd1,0x56,0x5c,0x9e,0x4d,0xf3,0xb1,0xa0,0x59,0x65,0xf3,0x57,0xa3,
+  0x3f,0xc2,0x5f,0x1f,0xc9,0xe7,0xf3,0xd7,0xc7,0xb4,0x5b,0x44,0x99,0xfe,0xac,0x37,
+  0x92,0xae,0x75,0x11,0x06,0x3a,0xd6,0x4e,0xe0,0x5d,0xa5,0x6d,0x68,0xa2,0x0d,0xcc,
+  0x6a,0xcb,0xcd,0xa4,0xf9,0xc4,0x26,0xe0,0xfa,0xcb,0xaa,0x8b,0x6e,0xb2,0xe3,0x2f,
+  0x66,0xaf,0x9e,0xbf,0xdc,0xff,0x21,0x1b,0x66,0x2a,0x9f,0x18,0x52,0xc6,0x2c,0xc9,
+  0xba,0x18,0x3d,0x33,0x61,0x28,0xad,0x8e,0x69,0xf9,0xfc,0x35,0x95,0xf4,0xd7,0xa4,
+  0xf5,0x7f,0x0e,0xda,0x78,0x77,0x83,0xa6,0x91,0xbb,0xe0,0x53,0x9b,0xbf,0x1c,0xb3,
+  0x2e,0xa6,0x19,0x12,0x7f,0x59,0xc8,0x4b,0x60,0xd3,0x52,0x94,0x4f,0x0c,0x76,0x2e,
+  0x3d,0xd9,0xe2,0xa4,0x8d,0x63,0xc4,0x05,0x86,0x59,0x2d,0xae,0x3f,0x13,0x0a,0x2a,
+  0xd9,0x93,0x35,0x24,0x08,0x3f,0xa1,0x52,0x37,0x9b,0xd7,0xd6,0x9f,0x27,0x8b,0xd5,
+  0xa2,0x19,0x67,0xa2,0xe3,0x08,0xe7,0x6f,0x26,0x6c,0xa5,0xfe,0xbf,0x8a,0x2a,0x49,
+  0x1d,0x1d,0x8f,0x4e,0xaa,0x88,0x1f,0x5a,0xfd,0x31,0xff,0xc7,0xe6,0xef,0x28,0x71,
+  0x99,0x2e,0xde,0xcc,0x89,0x4a,0xff,0xf7,0x29,0xb0,0x67,0xb0,0x92,0x78,0xe1,0x64,
+  0xfa,0x9b,0x2c,0x36,0x7e,0xb8,0x14,0x1b,0x69,0x7c,0xa5,0x63,0xee,0xc4,0x03,0x49,
+  0xda,0xba,0xa2,0xd0,0x12,0xe9,0x52,0x21,0x3f,0xf3,0x7f,0xea,0xfc,0x5d,0xc3,0xff,
+  0xa1,0x5e,0x08,0x5b,0x2c,0x66,0x13,0xfe,0x22,0x2c,0x78,0x4a,0x36,0xd9,0x43,0xfe,
+  0x77,0xbc,0xd1,0x22,0x7f,0x4a,0xc5,0xfc,0xd5,0xea,0x8f,0xf2,0x97,0x60,0xa3,0xde,
+  0xa3,0x6d,0x65,0x67,0xa5,0xff,0xdb,0x6c,0xfd,0xd9,0x2d,0x71,0x7a,0x62,0x57,0x90,
+  0xf1,0x47,0x17,0x04,0x1e,0x03,0xee,0x1d,0xf1,0xf8,0xb0,0x0b,0xf1,0xcb,0x29,0xdc,
+  0xd2,0xac,0x0b,0x88,0x5e,0x64,0xcd,0x6d,0x20,0x7b,0xea,0x42,0xc5,0xb3,0xcf,0x12,
+  0x4b,0xbb,0xdd,0x6e,0x6c,0xad,0x12,0x2a,0xc5,0x0f,0xe4,0x4f,0x21,0xdd,0xdc,0xa7,
+  0xae,0x22,0xb8,0xfe,0xb0,0x84,0xcd,0x1a,0xc5,0xf2,0x49,0xca,0xdf,0x18,0xa5,0xcf,
+  0xdc,0x64,0xe0,0x67,0x8d,0x15,0xf9,0x93,0xd4,0xc4,0x6a,0xfd,0x91,0x38,0xc5,0x26,
+  0x49,0x9e,0x06,0xb9,0xe4,0x30,0x36,0x32,0x75,0xb9,0x8b,0xd6,0x28,0x30,0x67,0xfe,
+  0xa9,0xe8,0x6f,0xd6,0x62,0x66,0xe3,0x96,0x46,0xe5,0x50,0xfe,0xe2,0x74,0xc0,0x2c,
+  0xb8,0xf7,0x84,0x67,0x46,0x52,0x47,0x12,0xdb,0xe8,0x62,0x35,0xe4,0x3c,0x1e,0x8a,
+  0x12,0x62,0x54,0xfd,0xd1,0x5c,0x93,0xdd,0x8e,0xb5,0x93,0xfe,0x92,0x4c,0xaa,0x99,
+  0xa6,0x3d,0x0d,0x68,0xc4,0x4c,0x16,0x93,0xaa,0xfe,0x08,0x4c,0x58,0xbe,0x99,0xf6,
+  0x8e,0x84,0x6f,0xbd,0x93,0x5d,0xdf,0x60,0x51,0xc5,0xad,0x5e,0xfa,0x10,0xfd,0x45,
+  0x69,0x22,0x5e,0xee,0xff,0x08,0x7f,0x64,0x1d,0x4d,0xa7,0x3b,0xfa,0xbf,0x69,0xee,
+  0x68,0x3d,0x9e,0x34,0x4d,0x17,0xd4,0x51,0x30,0x6d,0xba,0xfe,0xe4,0x1e,0x36,0x8f,
+  0xdc,0x36,0x7a,0x01,0x45,0xe2,0xaf,0x42,0xfa,0x6c,0x72,0xb1,0x39,0x80,0x5f,0x29,
+  0xd2,0x80,0xa0,0x5e,0xf5,0xe5,0xa4,0x0e,0x51,0xab,0x49,0xa3,0x3f,0x1d,0x3b,0x30,
+  0xc9,0x26,0xac,0x3a,0x7f,0x91,0x1e,0x20,0xab,0xff,0x84,0x6a,0x94,0x2c,0xd6,0x71,
+  0x7d,0xe8,0xb1,0xb3,0x8b,0x35,0x19,0x69,0xa9,0xf6,0x78,0xc8,0x70,0x44,0x54,0xd3,
+  0x9d,0x25,0xef,0x4a,0xe3,0x2f,0x3d,0x42,0x02,0xf5,0xa5,0x60,0xd9,0xfa,0x8f,0xae,
+  0x80,0xe8,0x6a,0xc7,0xc2,0x88,0xa6,0xbf,0x7a,0x24,0x24,0x7a,0x82,0x02,0x56,0x4c,
+  0x92,0x0b,0x11,0x9f,0x56,0xce,0x9b,0x82,0x08,0xa5,0x4f,0xef,0xe5,0xe1,0x8b,0xae,
+  0xff,0xdc,0x91,0x19,0x3f,0x5d,0xe8,0xd9,0xe9,0xd0,0x02,0x52,0x6b,0xc7,0x26,0x27,
+  0x71,0x9d,0xe6,0x8b,0x44,0x22,0x55,0x11,0xaf,0xc4,0xa2,0xb5,0xaa,0xbf,0xa0,0xbe,
+  0xc7,0x30,0x2b,0xcb,0x2b,0x66,0x26,0x5e,0xad,0xfe,0x94,0xf0,0x8c,0xff,0x32,0x31,
+  0x1a,0x75,0xda,0x9d,0x24,0xf4,0x90,0x75,0xc7,0x4a,0xd4,0x8b,0x57,0xaa,0xf6,0x3c,
+  0xeb,0x3d,0x39,0x05,0x59,0x72,0xce,0x38,0x65,0x16,0xc2,0x93,0x39,0xbf,0xdd,0x5f,
+  0x25,0x53,0x5a,0xc0,0x3d,0xdd,0x40,0x63,0xf3,0x11,0x4f,0xb9,0xfe,0x20,0x95,0xb0,
+  0x67,0xd1,0xa0,0x42,0xa6,0x3d,0x16,0xe8,0x2a,0xcc,0xca,0x21,0x17,0xe3,0xb5,0x40,
+  0xe7,0x93,0xd3,0x9e,0xd0,0xab,0x42,0xdd,0x2c,0xd0,0xf1,0x8e,0x3a,0x8b,0x12,0x27,
+  0xfa,0x8b,0xaa,0xbe,0x9d,0x9e,0x99,0x74,0x3e,0xd9,0x9e,0xe4,0x7e,0x5d,0xe3,0xa9,
+  0x63,0x25,0xfd,0xcd,0x46,0xc9,0x55,0x0c,0x75,0x63,0x64,0x1d,0xa3,0x89,0x1f,0xee,
+  0x2e,0x66,0x2b,0x39,0xcc,0x6b,0xd1,0xd5,0xd8,0x14,0xe1,0x85,0x5e,0xf4,0x10,0xaf,
+  0xd6,0x40,0x1c,0x88,0x62,0xee,0x52,0xc8,0x1c,0x97,0x27,0xd4,0x60,0xb5,0x8f,0xfa,
+  0x3f,0x37,0x6b,0x0a,0xd3,0xaf,0x36,0xfe,0x76,0xf1,0x72,0xd4,0xdb,0xe8,0xc8,0xc8,
+  0x48,0xc4,0x4e,0x12,0xaf,0xd2,0x29,0x7f,0xdc,0x2b,0x41,0x97,0x6e,0x33,0xf9,0x23,
+  0xeb,0xe3,0xa4,0xaf,0x94,0x26,0xfa,0xcb,0xb2,0xbe,0x26,0xd9,0x74,0xdd,0x17,0x63,
+  0x3d,0x48,0x4e,0x04,0x19,0x25,0x1a,0xfe,0x8a,0xfa,0x73,0xf1,0xbc,0x64,0x8e,0x5e,
+  0xc2,0x26,0x8b,0xeb,0x97,0x78,0x96,0x5e,0x31,0x2b,0x36,0x13,0x33,0xe3,0xa6,0xd7,
+  0x1a,0x2b,0xea,0xd5,0x6a,0x3b,0x5d,0x2a,0x1b,0xa2,0x9c,0x32,0x32,0xad,0x83,0xa3,
+  0x3c,0x1a,0xeb,0xa8,0xfe,0x9a,0x32,0x2c,0x49,0x0d,0x6b,0xe2,0x6f,0xd4,0xc9,0x08,
+  0x32,0x53,0x83,0x9e,0xc4,0x7e,0xd6,0xca,0x2e,0xba,0x0e,0x25,0xfc,0xf5,0xb3,0xa0,
+  0x28,0x45,0x3c,0x9b,0x09,0xca,0x9f,0x66,0x84,0x74,0xe1,0x4c,0xb8,0x6f,0x76,0x3a,
+  0xe6,0xea,0xa4,0xe1,0x90,0x40,0x5e,0x69,0xea,0x74,0x75,0xda,0x18,0xc9,0xd9,0x4c,
+  0x26,0xe3,0x08,0x67,0x08,0x30,0x10,0x34,0xe0,0x1e,0x65,0xc0,0xe4,0xcc,0xa7,0xe2,
+  0xae,0x94,0x8d,0xd5,0x51,0xf5,0x97,0xcd,0x38,0x22,0x1e,0xbf,0xad,0x33,0x1e,0xc3,
+  0xb2,0x72,0xb6,0x3a,0x6e,0xcd,0x85,0xf8,0x69,0x22,0x13,0x9d,0x2e,0x6b,0xcc,0x3b,
+  0xc3,0x92,0x76,0x4b,0x2c,0xee,0x1a,0x9e,0xb0,0xb0,0xc0,0x31,0x66,0x1b,0x8e,0xc7,
+  0x53,0x79,0x3b,0x5f,0xff,0x19,0x46,0xad,0xf1,0x6a,0x16,0x75,0xec,0xe1,0x8c,0x83,
+  0x9c,0xcf,0x99,0xc9,0x4c,0xca,0x0d,0xe1,0x94,0xab,0x33,0xdf,0xa7,0x76,0x64,0x3a,
+  0x86,0x95,0x6a,0x58,0x57,0xfc,0xd8,0x3c,0xbb,0x29,0x82,0x39,0xc5,0x5e,0x6c,0x12,
+  0x88,0x0b,0x57,0xd6,0xf8,0xc1,0x59,0x2e,0x0f,0x5a,0x9f,0x24,0x84,0x95,0xaa,0xa8,
+  0x32,0xa9,0xac,0x5d,0x6e,0xb4,0xc2,0x66,0xf9,0x31,0x9a,0x2a,0xae,0xff,0xd6,0x3b,
+  0x7d,0x45,0x23,0x57,0x15,0xfb,0x14,0xae,0x3c,0x32,0x44,0xe3,0xe1,0x90,0xce,0x60,
+  0x49,0x5d,0x8f,0xa3,0x58,0xb3,0x85,0xaa,0xfe,0x7e,0x53,0x94,0xae,0x7f,0x3f,0xbb,
+  0xb0,0x97,0x2e,0x1d,0xae,0x5d,0xea,0xfe,0x74,0x34,0x1a,0x5e,0x23,0xbb,0x42,0x7f,
+  0xd7,0x8b,0xd2,0xf5,0x87,0x9a,0x11,0x5d,0xf3,0x7c,0x37,0x15,0x7e,0xab,0xca,0x5f,
+  0xd5,0xc6,0x85,0x2b,0xeb,0x26,0xd7,0x24,0xea,0x86,0xe9,0x4f,0xaa,0xe4,0xef,0x06,
+  0x0d,0xcc,0x0d,0xc5,0x6c,0xb6,0xda,0x15,0xbd,0xe4,0x4a,0x65,0xfa,0x36,0x2e,0x5b,
+  0x01,0xf5,0x42,0xad,0x02,0x37,0x52,0x7f,0x39,0x6d,0xc6,0x8d,0x32,0x7c,0xa3,0x21,
+  0x9b,0x82,0xd7,0xe5,0x6a,0x67,0xaa,0x63,0xb1,0x35,0xd6,0x07,0x7e,0x49,0x92,0x6e,
+  0x8c,0xfe,0x24,0xa9,0x8c,0xbf,0x99,0xd8,0x9a,0xe7,0xfb,0x6d,0x83,0x6c,0xb7,0xdb,
+  0x4d,0x1b,0x17,0xfb,0xd4,0xec,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+  0x5c,0x37,0x82,0xf6,0x90,0xcf,0xe9,0x9c,0x2a,0x7f,0xa9,0xd0,0x66,0x4c,0xad,0xca,
+  0x9c,0x52,0x13,0xb8,0x4d,0xb1,0x2f,0x6d,0x4d,0x35,0x67,0xbd,0x97,0x73,0x8d,0x9c,
+  0xf5,0x8a,0xac,0x55,0xbd,0x7f,0xe5,0x8c,0xef,0x8c,0x8a,0xd2,0x5e,0x65,0xce,0xea,
+  0x23,0xc5,0x12,0xdb,0x3e,0xda,0xf7,0x1b,0xfd,0xa4,0x15,0x5c,0xc9,0xa5,0xdd,0x92,
+  0xa2,0xd0,0x1f,0xe8,0x8b,0x2f,0x2d,0x2a,0x92,0xab,0xa1,0x68,0xb6,0x0d,0x4a,0xf3,
+  0x42,0x1b,0x64,0x5c,0xc5,0x48,0x45,0x69,0x50,0x94,0xba,0x3b,0x2f,0x5c,0xa8,0xfd,
+  0x0b,0xba,0xd5,0x5e,0xa8,0x25,0xfb,0x17,0x6a,0xd9,0x86,0x19,0xf8,0xbe,0xc0,0xde,
+  0x9a,0xd7,0x05,0x56,0xb4,0x96,0x16,0xa8,0xfd,0xc1,0xfc,0x0f,0x1f,0x3f,0xf9,0xcb,
+  0xeb,0x64,0xcf,0x17,0x73,0xaf,0xd3,0xd0,0x5b,0x09,0x75,0x8f,0xd4,0xee,0x26,0x1b,
+  0xa2,0x76,0xf7,0x7c,0x71,0x4f,0xcd,0xac,0xad,0x48,0x14,0xf7,0x6a,0xe9,0x17,0x25,
+  0xf2,0x9b,0xcf,0x5d,0xfb,0x4f,0x25,0x9e,0x44,0x6a,0x43,0x6d,0xdd,0x22,0xa8,0xbb,
+  0x30,0xf0,0xfe,0xc0,0xc0,0xfc,0xc0,0xc0,0xd6,0x01,0xc4,0xce,0x79,0xdc,0xdd,0x49,
+  0xf6,0x71,0x6f,0x60,0x7e,0x27,0x49,0xe1,0x8b,0x95,0xa0,0xaf,0xad,0xb4,0xe4,0xb9,
+  0x81,0x81,0xdd,0x58,0x6e,0x9e,0xb2,0x38,0xff,0xdc,0xd2,0xb5,0xb1,0xd7,0xd0,0x23,
+  0x6d,0xdc,0xb0,0x5b,0x06,0x77,0x9e,0xbb,0x82,0xa0,0x1f,0x57,0xbe,0x4e,0xdf,0x6c,
+  0xbf,0x98,0x49,0x73,0xaf,0x68,0xf2,0x68,0x89,0x73,0x57,0xce,0x91,0x17,0x92,0xbe,
+  0xbb,0xf6,0x87,0x27,0xaf,0xc5,0x13,0x1a,0xf4,0x37,0xbb,0xcb,0x37,0x14,0xca,0x8e,
+  0x73,0x0b,0x5b,0x16,0xf6,0xec,0x79,0x61,0xcf,0x0b,0x0b,0xaf,0xd1,0x6d,0x0f,0x49,
+  0x63,0x72,0x0f,0xfb,0xc4,0xed,0x2e,0x9a,0xfd,0x1a,0x49,0xd3,0x4c,0x5a,0x60,0x61,
+  0xcb,0x96,0x2d,0x84,0x50,0x54,0x65,0xed,0xbd,0xf6,0x8d,0x79,0xe3,0xd8,0x65,0xde,
+  0xb8,0x4d,0xb7,0x16,0x76,0x7c,0x7d,0xfb,0x75,0xe1,0xf0,0xf6,0x05,0xa4,0xf1,0xf6,
+  0x2b,0x57,0x50,0x83,0xa7,0x3f,0x69,0x20,0xf1,0x76,0x49,0xbf,0x2d,0xbe,0xaf,0x08,
+  0x65,0xcb,0x1d,0xd7,0x85,0x43,0x77,0x1c,0xba,0x6f,0xfb,0xc2,0x0b,0x5b,0x6e,0xc7,
+  0x79,0xbc,0xf5,0xd7,0x9f,0x88,0xbe,0x6c,0x7b,0x97,0x04,0xc9,0x9b,0xdd,0xe1,0x1b,
+  0x8d,0x1d,0x7b,0x0e,0x70,0xb4,0xe1,0x76,0x55,0xb4,0x95,0x76,0xda,0x5e,0x7f,0xfd,
+  0x75,0x24,0x71,0xfb,0xf6,0x17,0x5e,0xc3,0x59,0xfc,0xcf,0x9f,0xe4,0x9f,0x1c,0x3b,
+  0xd2,0x66,0xf7,0x6f,0x9f,0xfe,0x00,0x7e,0x71,0x87,0xf1,0x77,0x8d,0x15,0x08,0x94,
+  0x27,0xbf,0x6f,0xac,0x2c,0xb2,0x78,0xc0,0x88,0x34,0xbe,0x8e,0x0c,0x1e,0x7e,0xed,
+  0xf6,0x73,0x3b,0x1f,0xdf,0xd8,0x07,0x36,0x74,0x46,0xa3,0xf4,0x4e,0xbb,0x6b,0x83,
+  0x3b,0x66,0x71,0xfa,0x7c,0x85,0x7c,0xfc,0xb3,0xcb,0xfc,0x23,0xc6,0xc0,0x62,0x00,
+  0x29,0xc3,0xcf,0x45,0xfa,0x69,0x5c,0x34,0x92,0xdd,0x45,0x9e,0x63,0x5c,0xe4,0x7b,
+  0xa5,0xcd,0x48,0x8a,0x20,0x83,0x07,0x08,0x83,0x0b,0x5b,0xae,0xbc,0xff,0x95,0x0d,
+  0xa3,0xb0,0x2d,0xad,0xff,0xb2,0x59,0x2a,0x13,0x60,0x57,0x76,0x2a,0x11,0x1a,0x0b,
+  0x85,0xa6,0x59,0x52,0x9a,0xce,0x76,0x8c,0x8d,0x85,0xc6,0x7c,0xa5,0x25,0x4e,0xd4,
+  0xa2,0x0e,0x8c,0x1c,0x6a,0x2a,0x72,0x9f,0xda,0xb5,0x42,0xaa,0xe1,0x8b,0xa1,0x13,
+  0xd2,0x59,0x67,0xc2,0x8f,0x55,0xfd,0xc5,0xbc,0x50,0x28,0x52,0xd1,0x4d,0x62,0x1d,
+  0xb3,0x55,0xeb,0xf9,0x82,0x81,0x24,0xd9,0x2d,0xab,0x5d,0x05,0x67,0x82,0x55,0x25,
+  0x16,0x88,0x19,0xda,0x26,0x73,0x81,0x9a,0x55,0x1b,0x98,0xee,0xa7,0x85,0xc6,0x2c,
+  0x15,0x96,0xb7,0x2c,0xb6,0xcc,0x2d,0xb6,0x04,0x16,0xe7,0x8c,0x73,0x8b,0xb8,0x05,
+  0x5a,0x02,0x01,0x7c,0x2f,0x06,0xe6,0x16,0x49,0xb2,0x25,0x30,0x47,0x3e,0xf9,0x41,
+  0xfc,0xa4,0xc7,0x28,0xd3,0x28,0xc3,0x36,0x46,0xe0,0xb9,0x47,0x37,0xa0,0x6f,0x8c,
+  0xdc,0x15,0xfc,0x65,0xb7,0xa4,0x15,0xa0,0x7b,0x17,0xbb,0x5b,0x71,0x8c,0x91,0xaa,
+  0x44,0x0a,0x94,0x2d,0x93,0x7a,0x4b,0x93,0x94,0x2b,0xfb,0x57,0x9b,0xb1,0x38,0xcf,
+  0x8f,0x45,0x12,0x65,0xc3,0xd5,0x03,0x97,0x76,0xf9,0x56,0xfd,0x03,0x8f,0xbf,0xa2,
+  0x97,0xaa,0x75,0xbe,0x06,0x08,0x4f,0xb3,0xc5,0x7f,0x5c,0xdb,0x12,0xcd,0xc9,0x38,
+  0x7f,0x34,0x3b,0xc1,0x29,0x0f,0xcd,0xd2,0xa1,0xb4,0x55,0x58,0x96,0xda,0x16,0x91,
+  0xa2,0x16,0xca,0x8e,0x71,0xae,0xa5,0x05,0xc9,0x6a,0x09,0xb4,0x50,0xe2,0x8c,0xc8,
+  0x26,0x39,0x64,0x2c,0x52,0x48,0x8f,0x52,0x2a,0x17,0x89,0x0e,0x8d,0x28,0xc1,0xfb,
+  0x16,0x5e,0xbb,0x72,0x7a,0xe4,0xea,0xfc,0x35,0xb9,0x3a,0xad,0xae,0x74,0xbb,0x94,
+  0xd4,0x10,0x28,0x15,0xce,0xd3,0x2e,0xe9,0x58,0x5e,0xb2,0xb7,0x8a,0xde,0xfd,0x37,
+  0xdb,0xae,0xea,0x91,0xb3,0x34,0x1b,0x9c,0xa5,0x7b,0x26,0x7e,0xd7,0x5a,0x2a,0x62,
+  0x98,0xe5,0x66,0xe9,0x03,0x70,0x39,0xc5,0x9d,0xed,0x2f,0xf6,0x5f,0xe6,0x98,0xa9,
+  0xd4,0x5f,0x84,0xde,0x25,0x34,0xcb,0x6f,0xb2,0x72,0x58,0x74,0xd4,0xe8,0x30,0x6b,
+  0xc9,0x14,0x17,0xba,0xcc,0x5f,0x7e,0x7a,0x57,0x5b,0x61,0x8a,0xde,0x2a,0xac,0x63,
+  0xed,0x71,0xf6,0xb1,0x66,0x5c,0xaa,0xb0,0x0c,0x3b,0xe7,0x5a,0x8c,0x84,0xab,0x16,
+  0x26,0xb7,0x45,0xc2,0x18,0x61,0xd0,0x48,0xb8,0x63,0x94,0x19,0x8b,0x6f,0xb6,0x51,
+  0x0a,0x71,0xa6,0x07,0x08,0x81,0x87,0x50,0x81,0x27,0xaf,0x4a,0x9f,0xc1,0x35,0x9c,
+  0x4a,0x59,0xf7,0x63,0x04,0xd1,0x5c,0x8b,0x4b,0x55,0xbb,0x68,0xab,0x67,0xf8,0x94,
+  0xb2,0xb0,0x1e,0xca,0x69,0x7e,0x94,0x91,0x64,0xea,0x4b,0xf8,0x0c,0x63,0x0d,0xf4,
+  0xd9,0x19,0x46,0x60,0x67,0x95,0xa1,0x95,0x1d,0x9a,0xd1,0x7d,0x4d,0xa7,0xd3,0xd9,
+  0xa0,0x6b,0x2a,0xcb,0xfb,0x6f,0xea,0xd3,0xf9,0xd9,0xe6,0xaf,0xf0,0x98,0x96,0x48,
+  0x83,0x5c,0xb2,0x0e,0x79,0xce,0x1f,0xb9,0x27,0x12,0x94,0x02,0xaf,0x2f,0xdb,0x69,
+  0x65,0x9d,0x8e,0xdc,0x41,0x5a,0x1c,0xe0,0x06,0x5a,0x23,0xce,0x9e,0x2d,0x94,0x9d,
+  0xab,0x5c,0xb1,0xd4,0x46,0xb9,0xe2,0x1c,0x51,0x95,0x2d,0x32,0x32,0x71,0xe3,0x74,
+  0xd1,0xcf,0x40,0x0b,0xd7,0x1f,0x27,0x31,0x40,0xdd,0x60,0x1b,0x2a,0x70,0xcb,0xff,
+  0x5c,0x35,0x84,0xe4,0xad,0xb1,0xe6,0x58,0xca,0x15,0xc5,0x08,0x5c,0x12,0x60,0x92,
+  0x4f,0x29,0x3b,0xe7,0xcf,0x1b,0x61,0x71,0x9c,0x5d,0xa4,0x64,0x98,0xc1,0x7d,0x89,
+  0x2a,0x6f,0x26,0xec,0xcd,0xfa,0x09,0x81,0x26,0x72,0x9b,0x25,0xb8,0x0a,0x3e,0xfa,
+  0xe4,0x8c,0xac,0xcb,0xf6,0x5a,0x2c,0x96,0xde,0x3c,0x24,0x77,0x59,0xc6,0xf8,0x8d,
+  0xcb,0x2b,0x11,0x0b,0x83,0xb3,0xe2,0x4a,0xd1,0xdb,0xcb,0xac,0x73,0x2f,0x90,0xb3,
+  0xf8,0x29,0x7f,0x6c,0x48,0xaa,0x76,0xb1,0x1b,0x5f,0xed,0xfd,0xd3,0xac,0xf6,0x14,
+  0xe5,0xaf,0x8a,0xd1,0x6a,0xa2,0x8c,0xd5,0x84,0xd8,0x43,0x9d,0x13,0xb0,0x0a,0x5b,
+  0x02,0x8c,0x3d,0x42,0x10,0x9b,0xa8,0xb8,0x17,0x50,0x69,0x22,0x07,0x56,0xeb,0x8f,
+  0x6d,0xc4,0x0d,0x22,0x81,0xdb,0x17,0x6e,0xff,0xdb,0xab,0xd0,0x67,0x4a,0xa5,0x7a,
+  0x9a,0xde,0x4a,0xc5,0xd3,0x65,0x0e,0x50,0x99,0x66,0x13,0x56,0x7d,0x1a,0x10,0x5d,
+  0x92,0x5c,0xec,0xa1,0xb5,0x8f,0xca,0xcf,0x94,0x38,0x3f,0x15,0xd9,0x65,0xb1,0x39,
+  0x22,0x21,0xc2,0x99,0x9f,0xf8,0xc6,0x74,0x61,0x85,0x91,0xe5,0x8f,0xd4,0x84,0xc3,
+  0x61,0xaf,0x03,0xa0,0x90,0xaf,0xf2,0xb3,0xf2,0x63,0x11,0x6f,0x4d,0x8d,0x37,0x5c,
+  0xe3,0x75,0x56,0xfc,0xca,0x13,0xe6,0xfc,0x75,0xb2,0x64,0x93,0x85,0xd1,0x41,0x9f,
+  0x18,0x83,0x08,0x6b,0x89,0xa7,0xc1,0x59,0x43,0x4c,0x86,0xc3,0xf4,0x52,0x49,0x1d,
+  0xe0,0x20,0x21,0x33,0x69,0xe0,0x45,0xd6,0xb8,0x88,0x7a,0xc4,0x48,0xb9,0x33,0x6a,
+  0x94,0x85,0x19,0x8c,0xc1,0x16,0x23,0xe1,0x72,0x4e,0xa5,0x93,0xd2,0xd6,0xc2,0x4a,
+  0x2d,0x92,0x32,0x18,0x9c,0x0f,0xb4,0x1d,0xda,0xbe,0xe5,0x5b,0x57,0xe1,0xcf,0xd0,
+  0xd9,0x3c,0x6a,0xcb,0xf5,0x58,0xd3,0x18,0x81,0x93,0x45,0xf9,0x2b,0x7c,0xc2,0xce,
+  0xf2,0x16,0x65,0x78,0x0f,0x53,0xe4,0x98,0x93,0x3e,0x43,0x2b,0xf7,0xf9,0x7a,0x70,
+  0xd1,0x9d,0xaa,0x0a,0x3b,0x0a,0xf4,0x20,0xb9,0x53,0x3b,0xca,0xbd,0xbd,0x2e,0xc6,
+  0x80,0x7a,0xcd,0x84,0x1d,0xbb,0xc8,0x7c,0x6c,0xa8,0x4e,0x11,0x5c,0x26,0xef,0x8a,
+  0x69,0x86,0xd6,0x65,0xd5,0x3a,0xa2,0x7a,0x7a,0x8c,0x26,0xf3,0x34,0xa5,0xba,0x8e,
+  0x1c,0x37,0x19,0xa3,0xbf,0x12,0x29,0xdc,0x23,0x93,0xc7,0x27,0x21,0x15,0x62,0x4f,
+  0x0a,0x57,0xad,0xa6,0x0f,0x94,0xb6,0x80,0x51,0x9d,0xaa,0x34,0x82,0x90,0x8f,0x40,
+  0x31,0x8a,0x68,0xf4,0x47,0x75,0xc9,0xb2,0xb0,0xc8,0x22,0x0d,0x2f,0x24,0x88,0xdc,
+  0x77,0x78,0xe1,0x2a,0x13,0x38,0x9c,0x6a,0x7a,0x26,0xf3,0xcc,0x44,0xbd,0xde,0x5c,
+  0x36,0x81,0x2d,0x11,0x1a,0x03,0x55,0x97,0xf4,0x4c,0x96,0xf1,0x47,0x5c,0xd2,0x70,
+  0x82,0x7a,0xee,0x59,0x1f,0xe3,0x56,0xca,0x84,0x6b,0x0c,0xa4,0xfd,0x33,0xee,0x52,
+  0x58,0x0c,0x95,0x3a,0x20,0x4d,0x66,0x1c,0xe7,0x09,0xe3,0xd9,0x75,0x57,0x98,0x36,
+  0x6e,0x9d,0x07,0xa1,0xbb,0xb3,0x6c,0xfe,0x86,0xcb,0x5a,0x52,0xf1,0xfb,0x46,0x6f,
+  0x84,0x69,0x8e,0x34,0x62,0x9a,0x95,0x9f,0x3d,0xb2,0x96,0xf1,0x3d,0x45,0xfd,0x51,
+  0x95,0xb5,0xd0,0x65,0x8c,0xaa,0xbf,0xa2,0x22,0x55,0xfd,0x19,0x79,0x1e,0x9d,0xe3,
+  0x64,0x2d,0x73,0x60,0x19,0x67,0xf0,0xe7,0xd7,0xe7,0xef,0xad,0x98,0xad,0x66,0x32,
+  0x9c,0xbb,0x3b,0x8e,0x2b,0x18,0xcd,0x0c,0x0e,0x47,0x98,0x24,0xf8,0x6d,0xcb,0x79,
+  0xf6,0x2c,0x38,0x7d,0xfc,0xcf,0x6b,0xa0,0x2e,0xce,0xae,0xae,0x59,0x92,0x11,0x47,
+  0xd5,0x0c,0xef,0x7e,0x17,0x8f,0x96,0x3a,0x4d,0x07,0xdc,0xd3,0x8e,0xb0,0x93,0x04,
+  0x88,0xca,0xc5,0x59,0x89,0x3f,0xfe,0x70,0xfb,0x28,0x4b,0xa6,0x74,0x6c,0xbc,0x59,
+  0x79,0xd5,0x75,0x58,0xcb,0xeb,0xa8,0x1e,0x99,0x3c,0xb4,0xc3,0x9f,0x4c,0xd7,0xad,
+  0xf9,0x03,0xdc,0x4e,0xad,0x77,0x6b,0x99,0x53,0x43,0x09,0xe5,0x4c,0x13,0x7b,0x35,
+  0x25,0xd4,0xa0,0xdc,0x42,0xa3,0x08,0xce,0xe0,0x85,0x3f,0x5a,0x97,0x3e,0x39,0x56,
+  0xed,0xb0,0x44,0x2c,0xcf,0x54,0x5b,0xd3,0x18,0x41,0xa4,0xe2,0xef,0xe1,0x99,0x72,
+  0x97,0x94,0xe3,0xeb,0x95,0x27,0x50,0x4f,0xd9,0x0e,0x9a,0x28,0x2d,0x82,0xf5,0x85,
+  0x49,0x2a,0x80,0x42,0xc9,0xad,0xdb,0xb5,0x33,0xd4,0x5c,0xf5,0x8c,0x77,0xc5,0x2e,
+  0xb3,0xa7,0x6a,0xd6,0x42,0x13,0xb7,0xce,0x1f,0xb2,0xb6,0xf2,0x24,0x9b,0x8e,0x61,
+  0x4b,0xc9,0x75,0x68,0x50,0x33,0x5d,0x8c,0x39,0x13,0x7c,0x81,0xb4,0xf6,0xf8,0x5c,
+  0xd0,0x04,0x57,0x1e,0x39,0x5a,0x68,0x28,0x61,0x81,0x39,0xc0,0xdf,0xc6,0x62,0x58,
+  0x69,0x09,0x18,0x35,0x14,0x06,0x02,0x6d,0x7f,0xb9,0xfd,0xc9,0x75,0xf9,0x33,0xa5,
+  0x9a,0x6a,0x0a,0xe7,0x23,0xe1,0x89,0x94,0x8b,0x0a,0x50,0x55,0x60,0xbe,0x97,0xcd,
+  0x89,0x19,0x1d,0x85,0xea,0x00,0x32,0xe4,0xa1,0x89,0x31,0x1a,0x0e,0x2e,0x17,0x5b,
+  0xa8,0x58,0xbc,0x09,0x92,0x85,0x8b,0x45,0x29,0xc2,0xd6,0x3d,0xa6,0xb2,0xb9,0x9a,
+  0x2e,0xd8,0xbc,0x06,0xfb,0x1a,0xf1,0xb1,0x33,0x6b,0xf0,0x6b,0xac,0xdb,0xd9,0xc9,
+  0xf8,0x2d,0xe3,0xfc,0xc9,0x3a,0x07,0x8f,0xc6,0x0d,0x3a,0x15,0x74,0x4c,0x1d,0x7c,
+  0x82,0x78,0x73,0xa3,0x09,0x5e,0xbe,0x42,0xa1,0x1c,0x77,0x2e,0xf2,0x90,0x1b,0x60,
+  0x34,0x1a,0xf9,0x64,0xe5,0xe1,0x57,0x15,0x5c,0xf1,0x7b,0xae,0x18,0x80,0x89,0x33,
+  0x9c,0x23,0x21,0xe4,0xc7,0xdf,0x5b,0x97,0xbf,0x99,0x54,0xce,0x72,0xfe,0xcc,0x79,
+  0x4b,0xee,0x6e,0x8c,0x20,0xee,0x2e,0x45,0x0d,0x21,0x36,0xde,0xea,0x0a,0xd4,0x60,
+  0x9f,0x0b,0xd4,0xbb,0xcb,0x9a,0x18,0x3a,0xd1,0x4b,0x25,0x69,0x72,0x93,0x0b,0x15,
+  0xe6,0xd6,0xcb,0xa7,0x92,0xb5,0xca,0x36,0x49,0x7c,0xa4,0xa9,0x42,0x44,0xc3,0xa5,
+  0xe5,0xf6,0x1a,0xf0,0xad,0xd3,0x12,0xba,0x2e,0xcc,0x5b,0xfc,0x15,0xc5,0xe5,0xe9,
+  0x35,0x7f,0xc3,0xac,0x0b,0xb4,0xa8,0xdc,0xb4,0x14,0x99,0x2a,0xb1,0x56,0xcc,0x53,
+  0xbf,0xf0,0x13,0x6b,0xb0,0x17,0xa5,0x33,0xb0,0x7c,0xe8,0xe8,0xba,0xd7,0xc0,0xfe,
+  0xd4,0x13,0xd3,0xfd,0x06,0x5f,0xc4,0x31,0x31,0xec,0xba,0xd4,0x4e,0x66,0x30,0x53,
+  0x4e,0xd3,0x74,0x48,0xf3,0x07,0x2c,0x8a,0x7f,0xa3,0x02,0x2f,0x37,0x8f,0x44,0x7e,
+  0x4d,0xd7,0x7b,0x1a,0x85,0x75,0x66,0xa9,0x24,0x65,0xbc,0x7e,0xb0,0xf0,0xb0,0x58,
+  0xd1,0x95,0x58,0x24,0xdf,0x9b,0x30,0x69,0x9c,0x26,0x43,0x3c,0xb2,0x62,0x22,0xe6,
+  0x4b,0xcd,0xd3,0x9e,0xcc,0x40,0xcb,0x8c,0x5a,0xd4,0x96,0xd0,0xbf,0xea,0x81,0x1f,
+  0xe4,0xd9,0x2c,0xc8,0x45,0x8a,0xd9,0xac,0x92,0x87,0xfc,0x10,0xb2,0x06,0x7f,0x3b,
+  0xbe,0xaf,0xa5,0x2e,0xc0,0xc3,0xeb,0x9c,0x3a,0xa1,0x99,0x36,0xcb,0x3c,0xa0,0xb1,
+  0x85,0xd1,0xca,0x60,0x0c,0x2c,0xbf,0xb4,0x37,0xe8,0x59,0x07,0x7d,0x29,0x5b,0xc4,
+  0x37,0x96,0x40,0x01,0xc6,0xd0,0x03,0x9a,0xdd,0xea,0x22,0xa6,0x27,0x32,0xc6,0xff,
+  0xd6,0x85,0x0e,0xaf,0x17,0xc8,0x1f,0x27,0xa1,0x49,0x74,0x71,0xa9,0x69,0xdf,0xff,
+  0xb7,0x73,0xfe,0x31,0x6d,0x5c,0x77,0x00,0x2f,0x23,0x2c,0xcd,0x0d,0x29,0x6c,0x66,
+  0x4d,0xd5,0x45,0xaa,0xa9,0x5b,0x9b,0x90,0x46,0x4a,0x9b,0x55,0x48,0x07,0x9c,0xab,
+  0x35,0x5b,0x07,0x0d,0x14,0x95,0x0e,0xea,0x0a,0xe1,0x4c,0xb3,0xbc,0x5a,0x49,0x6b,
+  0x05,0x7b,0x5a,0xb4,0x2d,0xd5,0xa4,0xfc,0x31,0x6d,0x19,0x71,0xb4,0x69,0x6b,0x94,
+  0x36,0x26,0xaa,0x32,0xc9,0x57,0x8d,0x06,0x31,0x1b,0xbb,0x06,0x2a,0x36,0xa0,0x56,
+  0x7a,0xaa,0x2a,0x57,0x1b,0x12,0x95,0xe9,0xb6,0x2e,0x51,0x40,0x5a,0x16,0xab,0x62,
+  0x33,0xd1,0xc0,0xdb,0xf7,0xfb,0x7e,0x9c,0xcf,0x10,0x08,0x99,0xba,0xfe,0xf5,0xfd,
+  0xbc,0x77,0xef,0xee,0x7d,0xdf,0xf7,0x7d,0xef,0xf9,0xeb,0xf7,0xee,0xde,0x3b,0xff,
+  0x60,0xfe,0xb3,0xf4,0xb0,0x6a,0x8d,0xf5,0x05,0xbc,0x59,0x8b,0xd9,0x46,0xdf,0xda,
+  0x85,0x94,0xcb,0x09,0xd3,0xc4,0x94,0xf8,0x71,0xb5,0xc9,0x4b,0x95,0x6e,0x1d,0x6c,
+  0x07,0x92,0x72,0x89,0x92,0x0c,0xb0,0x93,0xa9,0xec,0x64,0x6c,0xa1,0x76,0xd7,0x25,
+  0x27,0xbf,0x5e,0xf4,0xa9,0x58,0x08,0xad,0x51,0x62,0xfc,0x0d,0xd6,0xe5,0x3f,0x9b,
+  0xa0,0x38,0xc9,0xaa,0xa8,0xb7,0xf8,0x10,0xa2,0x56,0xdc,0x26,0xe4,0x3c,0x1a,0x73,
+  0x3c,0xc3,0xaf,0x6f,0xd3,0x72,0xd0,0x4e,0x97,0x7c,0x86,0xd2,0x69,0x51,0x30,0x7d,
+  0xe4,0xed,0xbf,0xff,0xee,0xe6,0x46,0xfe,0x53,0x1f,0x6e,0xa8,0x2c,0x2c,0x06,0xfd,
+  0x95,0xcd,0xdd,0x30,0x87,0x1e,0xf4,0xf0,0x6b,0x60,0x7a,0x65,0x28,0xc2,0x2e,0x69,
+  0x7d,0xa9,0x40,0x11,0xe7,0xfc,0xa3,0x95,0xfc,0x45,0x68,0x30,0xe6,0x7a,0xf9,0xca,
+  0xc9,0xd2,0xd4,0x0e,0x3e,0x7f,0xc5,0xc9,0xa2,0xbc,0x2d,0xf6,0xac,0x7d,0x19,0x0d,
+  0xbe,0xe6,0x22,0xce,0xa3,0x75,0xeb,0xdc,0x79,0x30,0x12,0x62,0x4b,0x8a,0x88,0x70,
+  0x91,0x62,0xc0,0x1a,0x63,0xd4,0x59,0x69,0xe3,0x93,0x48,0xfe,0x9f,0x15,0xe2,0x91,
+  0x44,0x06,0x5a,0xc2,0x56,0x20,0x11,0xf6,0x90,0x60,0x9b,0x78,0x83,0x53,0x41,0x26,
+  0x8e,0xf8,0x59,0xa3,0x6c,0xeb,0x9f,0xa5,0xed,0x39,0xb2,0x7f,0xba,0xe4,0x18,0xcb,
+  0xe8,0x45,0x2f,0x09,0xef,0x1d,0xd9,0x2f,0x9d,0xc6,0xae,0x79,0xa5,0x0a,0x15,0xd3,
+  0xd3,0x9d,0x9d,0x47,0x9e,0x7b,0x63,0x23,0xf7,0xf5,0xa5,0xba,0x1b,0x22,0x05,0x45,
+  0xd1,0xef,0x77,0x36,0x0c,0x5d,0xe8,0x81,0x4b,0x20,0x38,0xd0,0xbb,0xb2,0x92,0x9e,
+  0x2c,0xda,0x78,0xab,0x83,0x11,0x1f,0x83,0xaf,0x2b,0xe0,0x92,0x54,0x1d,0xe1,0x13,
+  0xb2,0x1b,0xa5,0x26,0xc6,0xf8,0x02,0x03,0x7f,0x84,0x2a,0xe7,0x3d,0xeb,0x46,0x92,
+  0xd7,0x17,0xba,0x9c,0xc5,0x99,0x88,0xe5,0x19,0xd8,0x5d,0x75,0xc6,0x0e,0xab,0xf5,
+  0x8c,0xe2,0xe6,0x59,0xb1,0xb6,0x65,0x9a,0xf2,0x91,0x44,0x4a,0xb6,0x04,0x17,0x35,
+  0xcc,0xad,0x5c,0x0c,0xab,0x1a,0xdf,0x8e,0xd0,0x92,0x18,0xe5,0x17,0xd6,0xf9,0xef,
+  0xc5,0xe9,0x4d,0xd8,0x5f,0xb1,0x7f,0xbd,0x4c,0x38,0xae,0xa2,0x02,0x52,0x4c,0x3a,
+  0xaf,0x6c,0x32,0x7f,0x71,0xdd,0xa8,0xb4,0x2d,0x27,0x95,0x44,0x71,0xc7,0x8d,0xa1,
+  0x8e,0x1e,0x1c,0xc2,0x5d,0xe0,0x41,0xb8,0x4b,0xf0,0x56,0x87,0xd9,0xa2,0x61,0xb2,
+  0x3b,0xcb,0x9f,0xa2,0xe8,0xb8,0x72,0xf7,0xe1,0x95,0xac,0x2f,0x68,0xfa,0x61,0x25,
+  0xce,0x06,0x4f,0xc6,0x96,0x66,0xb7,0x45,0x66,0x77,0x68,0xdd,0xeb,0xf0,0xf6,0x86,
+  0x7c,0x1a,0xf6,0xd3,0xa2,0xac,0x08,0x93,0xa5,0x0b,0xcc,0xfa,0xb6,0x38,0x9f,0x75,
+  0x27,0x87,0xf8,0xd9,0x0c,0xb1,0xb6,0x65,0x5d,0xb5,0xde,0xcd,0x5b,0xe2,0x9f,0x94,
+  0xb0,0x4b,0xc0,0x64,0x65,0x81,0x8f,0x08,0x26,0x72,0xb9,0x7b,0xb9,0xff,0x46,0xd7,
+  0x9e,0x76,0xe5,0x6b,0x7f,0x01,0x77,0xbc,0x72,0xe4,0x8b,0x47,0x3a,0x65,0x97,0xea,
+  0x14,0xfe,0x61,0x61,0x83,0x23,0xb9,0x03,0x0e,0x9f,0x3a,0xf5,0xc0,0x86,0xfe,0xeb,
+  0x6b,0x8e,0xf5,0xda,0x94,0x5c,0x32,0xe8,0x8f,0x5c,0x76,0x4d,0x82,0x03,0xf7,0x41,
+  0x17,0x04,0x0f,0x0e,0x67,0xd9,0x55,0x0e,0xe6,0x10,0x6c,0x44,0xc8,0x75,0x85,0x02,
+  0xb7,0x17,0x5f,0xc8,0x60,0xc3,0x35,0x06,0xc7,0x2c,0x76,0xf0,0x6b,0x63,0x2a,0x04,
+  0xba,0x4b,0x11,0xb9,0xf6,0x4f,0x63,0x19,0x06,0x54,0xc1,0xbb,0x92,0xc7,0x88,0x64,
+  0x15,0x34,0xea,0x83,0xec,0x0a,0x93,0xa5,0xb9,0x75,0x8f,0xa1,0xf1,0x87,0x51,0xdc,
+  0xb3,0x69,0x39,0x09,0xaa,0x43,0x23,0xd5,0x59,0xfe,0x48,0x42,0xe3,0x73,0xd3,0x15,
+  0xfc,0x9c,0x06,0xae,0xd1,0xf2,0x0d,0x76,0xa3,0x30,0x7d,0xd7,0xa4,0xce,0x2f,0xa1,
+  0x7e,0x2c,0xe3,0x01,0xcf,0x01,0xbb,0x77,0xc0,0x05,0x4f,0xfe,0xa8,0xd6,0x5b,0xfb,
+  0xa5,0xf3,0xe8,0x0d,0xe6,0x92,0x8a,0x0a,0xd1,0xbb,0xa6,0x6f,0x71,0xc4,0x54,0xa6,
+  0x57,0x2b,0x2a,0x56,0x51,0x71,0x61,0x61,0xe1,0xb1,0xc7,0x36,0x59,0x7f,0x64,0x2f,
+  0xf9,0xfc,0x8a,0xaa,0x2e,0xeb,0x5a,0xef,0x92,0xeb,0x89,0xfa,0xe1,0x29,0xe8,0x82,
+  0x57,0x3d,0x9e,0x9e,0x2c,0xbf,0x06,0x69,0xde,0x34,0x06,0x8f,0x11,0x16,0x43,0x2a,
+  0xed,0x9d,0x8c,0xc0,0x5c,0x24,0x83,0x93,0x91,0x34,0xfe,0x1f,0x52,0x7a,0x90,0xff,
+  0xe2,0x2f,0xa3,0xd6,0x43,0x21,0xdc,0x16,0x59,0x2e,0x06,0x37,0xf2,0x34,0xaf,0x0b,
+  0x2a,0x69,0x4c,0xbc,0x53,0x87,0xf8,0x8d,0x21,0xb3,0x04,0x6e,0x49,0xb3,0x72,0xae,
+  0xd2,0xe5,0x16,0xd6,0xbb,0x78,0x5e,0x4e,0x82,0xa6,0x40,0x27,0x3d,0xa5,0xf1,0x77,
+  0xd2,0xef,0xe5,0xfa,0x60,0x0a,0xab,0x0e,0xbb,0xf9,0x32,0x48,0x43,0x99,0xf9,0x1e,
+  0xf6,0x1d,0x82,0x42,0x50,0xe4,0x67,0x66,0xf1,0x7c,0xc5,0xf4,0xb1,0x6b,0x9f,0xfb,
+  0xee,0xdb,0xdf,0x3f,0xd6,0xf8,0x68,0x45,0x39,0xab,0xb7,0x38,0x2e,0x97,0xad,0x2e,
+  0xb4,0xb6,0x46,0x5f,0x7f,0xed,0xcc,0xc6,0xfe,0x73,0x74,0x87,0xee,0x0f,0xa8,0xe0,
+  0xc0,0x44,0xdc,0xb9,0xe4,0x1a,0xea,0x18,0xae,0x9e,0xda,0x07,0x83,0xb8,0x47,0xe3,
+  0x8f,0x8d,0x13,0x5e,0xc6,0x55,0xb1,0x2e,0xb3,0x43,0xd7,0xf4,0x14,0x43,0x95,0x8b,
+  0xec,0x16,0xdc,0x5c,0xe7,0xf5,0x76,0x4d,0x8a,0x79,0x98,0xaa,0xe1,0xc0,0x8f,0x15,
+  0xf9,0x38,0x6a,0xf6,0x76,0xf1,0x9a,0xde,0xae,0x29,0x93,0x6d,0xf2,0x1f,0xc6,0x2e,
+  0x79,0xcb,0xf0,0xb8,0xb9,0x75,0x15,0xec,0x5d,0x83,0xd8,0xcb,0xfd,0xd7,0x57,0x8d,
+  0x36,0x06,0x45,0x4b,0x82,0xd5,0x60,0xe1,0xa5,0xa9,0x29,0xd8,0x61,0x1d,0xf9,0x06,
+  0x1f,0x42,0x41,0x75,0x87,0xf8,0x65,0x59,0x46,0xf3,0xf2,0xbf,0x3e,0x32,0x79,0xab,
+  0x73,0xe1,0x9d,0xda,0xf3,0x4f,0x5e,0x59,0x7d,0xe5,0xe5,0x97,0x1b,0x3f,0xbf,0xba,
+  0xba,0x5a,0xc1,0x7a,0x16,0xee,0xf9,0xb6,0xb0,0x6a,0x61,0xa1,0x62,0x81,0xc9,0x17,
+  0x40,0xbc,0x80,0xb4,0x46,0x67,0x27,0x0e,0x7c,0x65,0x63,0xf7,0xc1,0xa2,0xa9,0xc1,
+  0x48,0xe4,0xec,0x76,0x55,0x29,0xc4,0x9d,0xcd,0xb1,0xa1,0xdd,0xf5,0x3d,0xd0,0xa0,
+  0x7f,0xf6,0xc4,0x79,0xab,0x03,0x1e,0x06,0x8c,0x5f,0xfe,0xb8,0x08,0x46,0xb7,0x67,
+  0x5b,0xd1,0x17,0x67,0x03,0xb1,0x4f,0xf5,0x1b,0x72,0x72,0xab,0x2a,0x93,0x50,0xd4,
+  0xe5,0x12,0xfe,0xf3,0x79,0x24,0x3d,0x36,0xdd,0x7e,0x34,0x95,0x4a,0xe1,0x26,0xe7,
+  0x79,0x01,0x4f,0x19,0x57,0xc5,0xc3,0xd0,0xa3,0x53,0x2c,0xdb,0x35,0x5a,0xe4,0xff,
+  0x92,0x76,0x01,0x73,0x83,0x61,0xf1,0x01,0x40,0x26,0x95,0xc1,0x98,0xc9,0xd8,0x50,
+  0x0c,0xc3,0xba,0x24,0x36,0x27,0x90,0xea,0x65,0xcf,0x1a,0x7e,0xb3,0xd0,0x79,0xed,
+  0xc9,0x57,0xbc,0xe7,0x17,0x8e,0xed,0x39,0xfc,0xe8,0x8b,0x87,0x17,0xee,0x04,0xe8,
+  0x7b,0xd1,0x9d,0x13,0xcf,0x3c,0xf3,0xe0,0x66,0xfe,0x33,0x5c,0x4e,0xff,0xb2,0x6a,
+  0xb7,0xe7,0x94,0x82,0xd6,0x7b,0xf9,0x27,0xdd,0x43,0x17,0xea,0xa1,0x0f,0x0e,0x8b,
+  0x77,0x3d,0x59,0x77,0xb0,0x0e,0xa3,0xe8,0x7f,0x99,0xea,0x83,0x90,0xc3,0x87,0x98,
+  0x4a,0xd9,0xa7,0x12,0x29,0x55,0x77,0xc2,0xb8,0xaf,0xab,0xfb,0xd8,0xe0,0xd3,0x8a,
+  0x48,0xdd,0x41,0x11,0x86,0x35,0xdb,0xba,0x0f,0x40,0x1c,0x75,0x75,0xac,0x4c,0x24,
+  0x83,0xd2,0xfa,0xf0,0x55,0x26,0x19,0x29,0xf2,0x49,0xe4,0x36,0xcc,0x0c,0x86,0xf3,
+  0x6b,0xea,0x2b,0x83,0x50,0x47,0x0e,0x90,0xb2,0x56,0xe4,0x94,0xfa,0x3a,0x8e,0x3c,
+  0xfb,0xe0,0x73,0xad,0xef,0xed,0x69,0x3d,0xd5,0x78,0xfe,0x4a,0xe3,0x7b,0xad,0x87,
+  0x1b,0xaf,0xb4,0x72,0x06,0x2c,0x29,0xee,0xc4,0x51,0x39,0x03,0xd1,0xd9,0x9d,0x13,
+  0x1f,0x8c,0x7f,0xf4,0x78,0xfb,0x66,0xfe,0xb3,0x5f,0x6a,0x36,0x82,0xd0,0x01,0xa1,
+  0x07,0x26,0xc2,0x11,0xdf,0x92,0x6b,0xdb,0xe4,0xee,0xfa,0xfa,0xfa,0x70,0x58,0xc5,
+  0x37,0xd6,0x21,0x86,0x9e,0x11,0x4f,0xb2,0xf7,0xb9,0x03,0x33,0x3d,0x06,0x38,0x50,
+  0x57,0xcd,0xee,0x94,0xb1,0x27,0x0b,0x5a,0x35,0xd3,0xeb,0xce,0x26,0xec,0xa0,0x96,
+  0x32,0xcc,0x41,0x3b,0x9c,0xf7,0xab,0x99,0x12,0xcc,0x8a,0xa3,0x7a,0xaa,0x8c,0x62,
+  0x96,0x5b,0xff,0x17,0xcf,0x8e,0x18,0x0a,0xcb,0xc6,0x58,0x2e,0xcf,0x5b,0x52,0x22,
+  0xd9,0x83,0x6d,0xd0,0x84,0xd9,0x94,0x48,0x52,0x29,0x55,0xd1,0x9d,0x53,0x6b,0xf8,
+  0xf9,0x40,0xf4,0x9d,0xef,0x44,0x4f,0x79,0xef,0xde,0x93,0x3e,0x76,0x38,0x5a,0xfb,
+  0xa7,0x81,0x81,0xe8,0x40,0x14,0x18,0x60,0x1b,0x0b,0x48,0x94,0x6d,0x66,0xca,0x75,
+  0xc0,0x7b,0xc7,0xc7,0x7f,0x3d,0x33,0xf3,0xc9,0x66,0xee,0xeb,0xeb,0x8b,0xdf,0x38,
+  0x0d,0x77,0x10,0x7b,0xca,0x9e,0x5b,0x0e,0xfa,0xb3,0xce,0x50,0x43,0xac,0x1b,0xe6,
+  0x11,0x79,0x4d,0x5f,0xc4,0x95,0x41,0xfd,0x70,0x0f,0x86,0xa2,0x51,0xc0,0x95,0x41,
+  0x72,0x88,0x65,0x77,0x1b,0x95,0xa3,0x86,0x3f,0x00,0x95,0xb0,0xed,0x6a,0x52,0xf7,
+  0xe7,0x77,0xb3,0x82,0xe1,0x6e,0x2d,0xaf,0xe3,0xe7,0x14,0x1a,0xcb,0x61,0xbc,0x10,
+  0xd6,0xf4,0x00,0x47,0x11,0x5b,0x40,0xe9,0x60,0x85,0x32,0x19,0xae,0x74,0x27,0x98,
+  0xf5,0x6e,0x2e,0xf2,0x15,0x6d,0x4c,0xab,0x99,0x15,0x6b,0xf1,0xc4,0x62,0xc0,0x82,
+  0x12,0xe8,0x00,0x69,0x7d,0x38,0xab,0x2b,0x8b,0x01,0xfe,0x89,0xca,0x22,0x46,0xdd,
+  0xe6,0x8f,0x77,0xf0,0xd6,0x4a,0xcb,0x3d,0xc3,0xf7,0x46,0x67,0xef,0xf9,0x73,0xf4,
+  0xb1,0xc6,0x7b,0x7e,0xf0,0x8f,0xda,0x6f,0xce,0xd6,0x3e,0x35,0x3b,0x1b,0xdd,0x39,
+  0x1b,0xc5,0x84,0xa5,0x6c,0xdb,0x69,0xee,0x67,0x4b,0xdb,0xce,0x89,0x89,0x13,0x1f,
+  0x8c,0x3f,0x32,0xb3,0xeb,0xc3,0x4f,0x36,0xed,0x7e,0xd0,0xeb,0x1b,0x9a,0x0d,0x3d,
+  0x69,0x07,0x07,0xaa,0xc9,0xc5,0x42,0xd8,0xed,0xdc,0xb1,0xd4,0xe0,0xfa,0x38,0x9f,
+  0x65,0x5f,0x96,0xd5,0xe5,0x94,0xac,0x98,0xcd,0x42,0xd6,0xd6,0xc0,0xb3,0x0f,0xbb,
+  0xfd,0x91,0xac,0xe6,0xd7,0x71,0x3d,0x15,0x2c,0xf8,0x6d,0x59,0xa1,0x36,0x19,0x0b,
+  0x1b,0xf1,0xac,0x06,0x75,0xcd,0xd9,0xda,0x90,0xdf,0x9d,0x15,0xdf,0xe0,0xcd,0x62,
+  0xc4,0xcc,0xa1,0xee,0xc9,0x32,0xdc,0xe5,0xd6,0x9d,0x06,0xcb,0xe6,0x7d,0x2c,0x97,
+  0x2f,0xf2,0x4a,0x26,0x36,0x7c,0x92,0xfd,0x84,0x10,0x67,0x35,0xb1,0x8b,0x67,0x4b,
+  0xad,0x30,0xf9,0xe3,0xc4,0x89,0x13,0xf7,0x36,0x1e,0x78,0xe8,0xda,0x53,0x07,0x1e,
+  0x7a,0xeb,0x9e,0x37,0xae,0xbd,0x36,0x31,0x71,0x1c,0xe2,0x89,0x13,0x13,0x98,0x4e,
+  0x40,0x80,0x23,0xcc,0xc0,0xfe,0x38,0x66,0x27,0x58,0x72,0xe2,0x38,0x30,0xfe,0xc3,
+  0x47,0x66,0x3e,0xbc,0x7e,0xfd,0x57,0xcf,0x6e,0xee,0x3e,0x58,0xf4,0xb8,0x7c,0xda,
+  0x7d,0x0e,0x7b,0x2a,0x05,0x17,0xc1,0x64,0xb0,0xa0,0x19,0x11,0x58,0x2b,0xe8,0x40,
+  0x42,0x4f,0x28,0x0d,0x31,0x57,0xcc,0xe5,0x72,0x69,0x98,0x49,0xe8,0x01,0x9f,0x0b,
+  0xf3,0xb1,0x58,0xcc,0x59,0x38,0xa4,0x85,0xc3,0x79,0xbf,0x3f,0x9f,0x4f,0xe8,0x4e,
+  0xa6,0x84,0xf1,0xd5,0xc5,0x84,0xce,0x02,0xd4,0xe1,0xb2,0x1b,0xac,0x66,0x81,0xc5,
+  0x04,0x33,0x92,0x00,0xab,0x52,0x9f,0x19,0x77,0x69,0x4c,0x45,0x0f,0x8e,0xb0,0x6c,
+  0x6c,0x14,0xaa,0x80,0xb6,0xee,0x66,0xc5,0x36,0x66,0xa0,0x84,0x1e,0x78,0x15,0xeb,
+  0x09,0x53,0x52,0xa8,0x27,0xfc,0x3e,0xb3,0x15,0xfc,0xdc,0xc0,0x33,0xe3,0xe3,0xdb,
+  0xb7,0xdf,0xfd,0xd7,0x03,0xb5,0x07,0xf7,0xd4,0x3e,0xfd,0xfc,0x8f,0x7f,0x3f,0xfe,
+  0x9f,0xf1,0xed,0x2c,0xa0,0x7c,0x9c,0xb3,0x7d,0x9c,0xe7,0x2d,0x61,0x1c,0x7d,0x07,
+  0xce,0x6b,0xaa,0xaa,0xea,0x7f,0xf3,0xec,0xed,0xfc,0xd7,0x17,0x69,0x70,0xe6,0x83,
+  0x49,0xfb,0x4d,0xb8,0x43,0xaa,0x0e,0x65,0xb1,0x90,0x0f,0x67,0x23,0x95,0x91,0xd1,
+  0xd3,0xbd,0x4e,0xe7,0x88,0x58,0x33,0xf9,0xd8,0x3a,0x75,0xc4,0x29,0x72,0xb8,0xec,
+  0x32,0x0a,0x4a,0x00,0x07,0x8e,0xee,0xf6,0xed,0xf0,0xf9,0xca,0xf4,0x2c,0xf5,0x4c,
+  0x09,0x70,0x1a,0x2d,0x58,0xcd,0xf8,0x42,0xa6,0x0e,0x2b,0x30,0xab,0x8c,0x58,0xb4,
+  0x30,0x33,0xc2,0x2a,0x4b,0x03,0x25,0x1d,0x96,0x9c,0x2e,0x09,0xd7,0xf0,0xc0,0x49,
+  0xe4,0xf9,0xda,0x6f,0x7c,0x34,0x33,0x33,0xf3,0xf8,0xb7,0x0e,0x3e,0x3e,0x73,0x52,
+  0x30,0x73,0x72,0x17,0x26,0x10,0x67,0xc4,0x9e,0xb1,0x0b,0xf7,0xbb,0x4e,0xee,0xda,
+  0xf5,0xe1,0x9b,0xe0,0xbc,0xb1,0xb6,0xb1,0xb1,0x73,0xb7,0x19,0xbd,0x48,0xc6,0xb7,
+  0x14,0xf1,0x2f,0x3a,0x60,0x08,0x43,0x1f,0x54,0x61,0x14,0x07,0x0b,0x05,0x7f,0x3e,
+  0xac,0x69,0xf1,0xfb,0xb5,0x78,0x3c,0x1b,0x8f,0xe3,0x18,0x89,0x23,0xb0,0x63,0x41,
+  0x63,0x49,0x56,0x03,0x25,0x5e,0xc8,0x02,0x26,0x71,0xbe,0x69,0x59,0x8c,0x9c,0x38,
+  0xaf,0xcb,0x6a,0x6b,0x62,0xcf,0x07,0x39,0xd3,0x81,0x2d,0xce,0xe5,0x68,0xa2,0x94,
+  0xc3,0x53,0xb3,0xb3,0xf0,0x63,0x8d,0xcb,0x85,0xd4,0x34,0x19,0xe7,0xdf,0xf3,0x67,
+  0x8a,0xbc,0x09,0xdc,0x24,0x6e,0x5f,0x68,0x42,0xaa,0x9a,0x7e,0xba,0xef,0xe9,0xdf,
+  0x7e,0xf9,0x67,0xfb,0xfe,0xf6,0x00,0x1c,0x5b,0xc0,0x4c,0x3f,0xa4,0x18,0x44,0x14,
+  0x0a,0x55,0x55,0x63,0x63,0x6d,0x2d,0x40,0x5b,0xff,0xfc,0xed,0xdd,0x87,0x33,0xe1,
+  0xa5,0x08,0xf4,0xc0,0x17,0xe0,0x7e,0x80,0xa3,0x18,0x5c,0xb8,0xac,0x2c,0x2e,0xe2,
+  0x97,0x4e,0x74,0x19,0xe4,0xce,0x14,0x94,0x95,0x95,0x44,0x96,0x02,0xab,0x8a,0x69,
+  0x44,0x96,0x94,0xb2,0x42,0x8d,0x7f,0x69,0x46,0x2f,0xb3,0x2c,0x4f,0x1c,0x2c,0x55,
+  0xb4,0x9c,0xbb,0xd4,0x9e,0xf2,0x56,0xc9,0xfd,0x7d,0x2d,0x7b,0x31,0xec,0x6d,0x69,
+  0x79,0xf6,0x17,0x0f,0xef,0xfe,0xf8,0xf4,0xb7,0x5b,0x78,0x76,0x2f,0xd0,0x32,0x0f,
+  0xc7,0x2c,0xd3,0x22,0xa5,0x98,0xe5,0x85,0x50,0x3a,0x3f,0x7f,0x06,0xb6,0xb6,0xaa,
+  0xb6,0xad,0xb8,0x0f,0xff,0x36,0x65,0xa9,0x37,0xac,0x2f,0xab,0x2f,0xe0,0x34,0xf7,
+  0x28,0x73,0xa1,0x9a,0x53,0x73,0x39,0x47,0x4e,0xa2,0xb2,0xd4,0xa1,0x62,0x44,0xb1,
+  0x03,0x82,0xa9,0xa0,0x8a,0xd4,0x54,0xe7,0x4a,0x0e,0x2e,0xc2,0x52,0x5e,0x43,0x15,
+  0xaa,0x2a,0x2b,0x74,0x70,0x3d,0x59,0x0b,0x04,0x0e,0x07,0x2f,0xc9,0x99,0x12,0xeb,
+  0x69,0x1d,0xaa,0x45,0xb5,0x74,0x6a,0x69,0xd7,0x61,0x36,0x43,0x18,0x7d,0xbf,0xa6,
+  0x7d,0xae,0x66,0xae,0xa6,0xbd,0x46,0x32,0x27,0xe2,0xfb,0xb8,0x13,0x39,0xa4,0x9d,
+  0xeb,0xb4,0xf3,0x80,0xc7,0xed,0xed,0xed,0x67,0xce,0xcc,0xb7,0x8d,0xb5,0x6c,0xf5,
+  0x2b,0xd0,0x19,0xb8,0x06,0x1a,0xfe,0x20,0x4e,0xa4,0x99,0x07,0x53,0x70,0x3b,0xde,
+  0x9c,0xdb,0x95,0xdf,0x46,0xef,0x16,0xe2,0xad,0x5a,0xdc,0x22,0x67,0xcf,0xde,0x84,
+  0xc0,0x92,0xa3,0x17,0x59,0x6a,0x4a,0xf8,0xc1,0xcd,0x8b,0x67,0x21,0xf0,0x1c,0x66,
+  0x70,0x8f,0xe9,0xc5,0x8b,0x73,0x73,0x73,0x35,0x67,0xf6,0xb6,0x55,0xbd,0xbb,0x45,
+  0xef,0x21,0xf9,0x86,0x50,0x24,0x6c,0x0b,0x2e,0x3b,0xd4,0xff,0xcb,0xab,0xf9,0xac,
+  0xb9,0x69,0x3a,0x8f,0x7b,0x4c,0x64,0xce,0x96,0x49,0x85,0xd2,0xcd,0xb3,0xd6,0x80,
+  0xee,0x43,0xef,0x8d,0x35,0xbd,0x70,0x7b,0xaf,0x59,0xc7,0x70,0x64,0xc9,0x17,0x81,
+  0x39,0x5d,0x50,0x59,0x4e,0xb2,0x41,0xe1,0x60,0x83,0x18,0x70,0xb0,0xc1,0x2c,0xf2,
+  0xa5,0xc0,0x4a,0x73,0xa6,0xd0,0xc4,0xac,0x67,0x26,0x0e,0xa1,0x9a,0x53,0x73,0x52,
+  0xd7,0x61,0x4a,0xf0,0x00,0xab,0x38,0x2c,0xd6,0xb8,0x80,0x1f,0x9a,0x96,0x73,0x66,
+  0x2b,0x54,0x8b,0x75,0xa6,0x21,0x54,0x1d,0x66,0x4b,0xde,0xc7,0x2e,0xc4,0x37,0x33,
+  0xe2,0x60,0x9e,0x9b,0x2b,0x15,0x48,0x6a,0x4a,0x7b,0x8c,0xed,0x35,0x30,0x72,0xdb,
+  0xaa,0x9a,0xe6,0xef,0xf8,0x87,0x5c,0xc9,0xde,0xa5,0x1d,0xce,0xa2,0x96,0xb7,0x15,
+  0x12,0x41,0xcb,0x97,0x20,0xb7,0x8c,0xbe,0xbe,0xd2,0x46,0x46,0xee,0xd0,0xf8,0x1d,
+  0xa9,0xeb,0xf7,0xbd,0x6b,0xde,0x27,0x24,0x2d,0xb7,0x08,0x82,0x79,0x79,0x34,0xcf,
+  0xf4,0xda,0xda,0xda,0xc6,0xaa,0x9a,0xae,0xb7,0x7c,0xf5,0x4e,0xbd,0xc7,0xfa,0x60,
+  0x21,0x12,0x0a,0x8d,0x38,0x2b,0x8b,0x45,0xb7,0x81,0x13,0x01,0x43,0xce,0x06,0x3e,
+  0x2d,0x8c,0x72,0x63,0x9f,0xa6,0x69,0xc1,0xbf,0xff,0xd0,0xdf,0xcf,0x26,0x21,0xfd,
+  0xa5,0xd8,0x6f,0x39,0x6a,0x12,0xbb,0xd2,0x6c,0x45,0x6a,0x0b,0xae,0x7f,0xfd,0xfa,
+  0x58,0xfb,0xff,0xfe,0x23,0xc2,0xd4,0x62,0xc2,0xaf,0xb9,0xc1,0x83,0x88,0xbb,0x28,
+  0x30,0x64,0x14,0x9b,0x9b,0x97,0xb9,0x65,0x21,0x1e,0x72,0x05,0x77,0x49,0xc0,0x0f,
+  0x4c,0x1b,0x5c,0x2c,0x8d,0x18,0x56,0xa9,0xd0,0x75,0x5b,0xaa,0x95,0xb4,0xdc,0xb2,
+  0xcc,0xd2,0x02,0xf7,0x9a,0x16,0x71,0xfd,0xef,0xfd,0xf2,0xc1,0x73,0x4d,0xe7,0x9a,
+  0xca,0x58,0x93,0x5d,0xc7,0x39,0x8c,0xe7,0xb8,0xde,0xb9,0xa6,0xfe,0xb6,0x96,0x33,
+  0x73,0x9f,0xc5,0xdf,0x19,0x13,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,
+  0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,
+  0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,
+  0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,
+  0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,
+  0x10,0x04,0x41,0x10,0x5b,0xe6,0xbf,0x9f,0xe5,0x54,0xe2,0x36,0x30,0x01,0x00,
diff --git a/u-boot/board/esd/hh405/logo_640_480_24bpp.c b/u-boot/board/esd/hh405/logo_640_480_24bpp.c
new file mode 100644
index 0000000..c042b6b
--- /dev/null
+++ b/u-boot/board/esd/hh405/logo_640_480_24bpp.c
@@ -0,0 +1,4209 @@
+  0x1f,0x8b,0x08,0x08,0xc2,0xbb,0x0b,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48,
+  0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x36,0x34,0x30,0x5f,0x34,0x38,0x30,
+  0x5f,0x32,0x34,0x62,0x70,0x70,0x2e,0x62,0x6d,0x70,0x32,0x00,0xec,0xdd,0x09,0x58,
+  0x56,0x55,0xfe,0xc0,0x71,0x67,0x46,0x4d,0x51,0x01,0xd9,0x71,0x21,0x0b,0x5c,0x73,
+  0xdf,0xcd,0xdd,0x4c,0x4d,0x65,0xb1,0x5c,0x13,0x97,0xd2,0x6a,0xfe,0x93,0xa2,0xa9,
+  0xa5,0x36,0x35,0x8d,0xe5,0x56,0xa9,0x65,0x8b,0xb2,0xa9,0x28,0x8b,0x0a,0x4e,0x69,
+  0x8a,0x1b,0x6e,0xa0,0xa0,0x36,0xb9,0x2f,0x61,0x66,0xa9,0x60,0x08,0x2e,0xec,0x28,
+  0x4b,0xff,0xe7,0xff,0x7b,0xa1,0xa1,0xd7,0x7b,0xee,0x7d,0x79,0xe1,0xdf,0xf2,0x3c,
+  0xcd,0xd7,0xe7,0x23,0x4f,0xca,0xb9,0xe7,0x9e,0x7b,0xee,0x39,0xf7,0x77,0x7e,0xe7,
+  0xbd,0xd8,0x00,0xef,0xae,0xf6,0xb6,0xd5,0x4c,0xbf,0xba,0xca,0xef,0x16,0xf2,0xfb,
+  0x9f,0x7f,0xae,0x56,0xed,0xea,0x9f,0xaa,0x55,0xfb,0x53,0x35,0xb7,0xd2,0xbf,0xaf,
+  0x26,0xdf,0xf7,0x6c,0x5b,0xad,0xf4,0xf7,0x7f,0x7e,0x95,0xfc,0x6f,0x09,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x54,0x7b,0xf7,0xed,0x5b,0xf9,0xf1,0xc7,0x1a,0x1b,0xa3,0xa3,0x73,0xf3,0xf3,0x8b,
+  0x4b,0x7e,0xff,0xe6,0x01,0x00,0xf0,0x87,0x34,0x71,0xe2,0x73,0xd5,0xff,0x5c,0x5d,
+  0xa3,0x6b,0xe7,0xae,0xe9,0xb7,0x32,0x7e,0xf7,0xb6,0x01,0x00,0xf0,0x47,0x35,0xc1,
+  0x28,0xfe,0x66,0xa4,0xff,0xee,0x6d,0x03,0x00,0xe0,0x8f,0xca,0x7f,0xc2,0x64,0x9d,
+  0xf8,0xdb,0xa5,0x5b,0xda,0xcd,0xb4,0xdf,0xbd,0x6d,0x00,0x00,0xfc,0x51,0xe9,0xee,
+  0x3f,0x77,0xee,0xd4,0x25,0xfd,0x16,0xf9,0x2f,0x00,0x00,0xbf,0x96,0xf1,0x13,0x26,
+  0xe9,0xe6,0xbf,0x19,0x7c,0xfe,0x0b,0x00,0xc0,0xaf,0x86,0xfc,0x17,0x00,0x80,0xdf,
+  0x9e,0xfe,0xfb,0xcf,0xe4,0xbf,0x00,0x00,0xfc,0x9a,0x78,0xff,0x0a,0x00,0x80,0xdf,
+  0x9e,0x6e,0xfc,0xed,0xd2,0xa9,0x0b,0x3f,0x7f,0x04,0x00,0xc0,0xaf,0x67,0x9c,0xff,
+  0x44,0x3e,0xff,0x05,0x00,0xc0,0x82,0xc2,0xe2,0xc2,0xdb,0x77,0xef,0x5c,0xbc,0x94,
+  0x7c,0x28,0x3e,0xfe,0xb3,0xad,0x5b,0xd7,0x85,0x85,0x05,0x06,0x05,0x7f,0xf4,0xf1,
+  0x27,0xc1,0x21,0xa1,0x11,0x91,0x91,0xb1,0xbb,0x76,0x1e,0xff,0xf2,0xf8,0xf7,0xd7,
+  0xaf,0x16,0xdc,0x2f,0xb0,0xbe,0xce,0x0a,0x3f,0xff,0x2d,0xfe,0xb1,0xf8,0x66,0x46,
+  0x7a,0xd2,0xb1,0x63,0x31,0x5b,0xb6,0xac,0x0a,0x0a,0xfe,0xf8,0x93,0x4f,0xe5,0xbc,
+  0xdb,0x63,0x63,0x4f,0x9d,0x39,0x9d,0x95,0x9d,0x25,0xdf,0xad,0xfa,0xe5,0x14,0x15,
+  0xa6,0x65,0xa4,0x7f,0x75,0xea,0xe4,0xee,0xbd,0x7b,0x36,0x84,0x87,0xaf,0x0e,0x0c,
+  0xfa,0x78,0xd5,0x27,0x21,0xa1,0xa1,0x91,0x1b,0x37,0xee,0x89,0xdb,0x7b,0xe2,0xd4,
+  0x49,0xf9,0xae,0x94,0xb1,0x50,0x43,0x5e,0x41,0x41,0x7e,0x41,0x7e,0x4e,0x5e,0x6e,
+  0xd5,0xc8,0xb1,0x79,0xf9,0x79,0xf7,0xee,0xdf,0x53,0xfb,0x59,0xfe,0x5e,0x68,0x0a,
+  0x17,0x95,0x14,0x59,0xbe,0xa2,0xfb,0x45,0xf7,0xaf,0xa5,0xa6,0xc4,0x27,0xc4,0x47,
+  0x44,0x45,0x7d,0x1a,0xb8,0x3a,0x28,0x38,0xe4,0xf3,0xad,0x9f,0x9f,0x3c,0x7d,0xea,
+  0xd6,0x9d,0xdb,0x9a,0x92,0x05,0xf7,0x0a,0x44,0x59,0xb5,0x65,0xf5,0xcb,0x1f,0xd5,
+  0x0a,0xe5,0x8c,0xb9,0xf9,0xda,0x0b,0x94,0x43,0x74,0xbb,0x5d,0x0a,0xab,0xbd,0x21,
+  0xd5,0x16,0x97,0x18,0xde,0x23,0xa9,0x27,0x4f,0x3a,0xc1,0x74,0x94,0x5c,0x6c,0x5e,
+  0xd9,0x55,0xcb,0x1f,0x2d,0x77,0x7b,0xc1,0xbd,0x7b,0xa5,0xe5,0x1f,0x68,0x52,0x85,
+  0xa3,0xae,0xa8,0xa4,0x58,0x6e,0xe8,0xb1,0x2f,0x8f,0xcb,0x40,0x92,0xbb,0xfc,0x69,
+  0xe0,0xaa,0x4d,0xd1,0xd1,0x49,0x47,0x93,0x6e,0xa4,0xdd,0xd0,0x76,0x63,0xe1,0xfd,
+  0xdc,0xd2,0x66,0xe4,0x96,0xdf,0xa6,0x02,0x9d,0xca,0xa5,0xf1,0xf2,0xad,0x6b,0xa9,
+  0xd7,0x4e,0x94,0x0e,0xa1,0xc8,0xa8,0xa8,0xa0,0xd0,0x10,0x99,0x0e,0xd2,0xed,0x51,
+  0x1b,0x37,0xee,0x3f,0x78,0xe0,0x62,0xf2,0xd7,0xd9,0xb9,0x39,0x55,0x1e,0xa2,0xd2,
+  0x80,0x6f,0xbf,0xfb,0xee,0x50,0x42,0xc2,0xe6,0x98,0x98,0xc0,0x10,0xd3,0x44,0x93,
+  0xe9,0x16,0xba,0x76,0xcd,0x96,0x7f,0xfd,0x2b,0x6e,0xff,0xbe,0xf3,0x17,0x2f,0xc8,
+  0xbc,0x90,0xa1,0xf2,0x8b,0x8c,0x1c,0xe9,0x70,0xf3,0x1b,0x2d,0x17,0x2e,0x67,0x97,
+  0x7b,0x57,0x54,0xac,0x73,0xa0,0x14,0x2e,0xaf,0xd9,0xfc,0x46,0xeb,0x16,0x2e,0xbb,
+  0xc5,0xe5,0xe5,0xcb,0x6a,0x96,0xee,0xd5,0x2d,0xfc,0xc0,0xfd,0x2a,0x96,0xb1,0x97,
+  0x57,0x7e,0x96,0xb2,0xaf,0x79,0x06,0x63,0xcf,0xc8,0xdd,0xac,0xcc,0xe4,0x6f,0x2f,
+  0xef,0x3f,0x70,0x60,0x73,0x74,0xf4,0x9a,0xb5,0xeb,0xe4,0xe9,0x21,0xd3,0x5c,0x26,
+  0xfb,0xe7,0xdb,0xb6,0x25,0x1e,0x4d,0xfa,0xfe,0xda,0x55,0xa9,0xb0,0xc2,0x4a,0x64,
+  0x86,0xfe,0xdc,0x80,0xfc,0xbc,0xb2,0x56,0xa9,0xd3,0x56,0x25,0x87,0x68,0x66,0x84,
+  0x74,0xf2,0xbd,0xc2,0xfb,0x55,0x1b,0x0f,0xf8,0xef,0x94,0x7f,0x2f,0xff,0xc4,0xa9,
+  0xd3,0x1b,0x22,0x23,0x67,0xcc,0x98,0xf9,0xc4,0xc0,0x81,0x8f,0xb5,0x6a,0xdd,0xb0,
+  0x41,0x23,0x87,0xfa,0x8e,0xf5,0xea,0xd6,0xab,0x6b,0x53,0xd7,0xa6,0xb6,0x4d,0x9d,
+  0xda,0x75,0x6c,0xeb,0xd9,0x3a,0x39,0x3a,0x37,0xf1,0x68,0xd2,0xb1,0x63,0xc7,0x89,
+  0x93,0x26,0x85,0xae,0x5b,0x73,0xf9,0xca,0xb7,0xf7,0x0a,0x2b,0x1e,0xa2,0x16,0xde,
+  0x7f,0x96,0x89,0x96,0x72,0x23,0x25,0x30,0x28,0x48,0x4e,0xda,0xe4,0xe1,0x47,0x1c,
+  0xec,0x1d,0x6c,0xe4,0x57,0x6d,0x1b,0x39,0xaf,0xb3,0xa3,0xb3,0x97,0x67,0x53,0x1f,
+  0x5f,0xdf,0x55,0x41,0x41,0x29,0x37,0x52,0x2b,0x7c,0xbc,0x98,0x93,0x6a,0x33,0xb3,
+  0x33,0x63,0x77,0xef,0x9d,0x35,0x67,0x4e,0xaf,0xde,0xbd,0x3d,0x1f,0xf1,0x74,0x75,
+  0x71,0xb3,0xab,0x67,0x27,0x57,0x21,0x95,0xcb,0x15,0xd9,0xd9,0xda,0xbb,0xb9,0xb8,
+  0x79,0x3e,0xea,0xd5,0xab,0x57,0xef,0xe9,0x01,0x33,0x24,0x84,0xfd,0x70,0x33,0x4d,
+  0x42,0x9b,0xa6,0x1e,0x09,0x6a,0x2f,0xbc,0xf8,0x92,0x8f,0x9f,0xb4,0xc2,0x6f,0xb8,
+  0x8f,0xb7,0xf9,0x57,0xf9,0x2b,0x6f,0x5f,0x9f,0xb2,0xaf,0xe5,0xff,0x21,0x5f,0x35,
+  0xc5,0xfc,0xfc,0x46,0x78,0x7b,0xfb,0xcc,0x98,0xf9,0x4a,0xfe,0x83,0xb1,0x4f,0x9e,
+  0xae,0x23,0x47,0x8d,0xf2,0xf1,0xf3,0x35,0x3f,0x76,0xc4,0x88,0xa7,0xaf,0x5c,0xbd,
+  0x62,0x74,0x51,0xd2,0xd5,0xc7,0x8e,0x1f,0x7f,0x6d,0xee,0xbc,0x6e,0xdd,0x7b,0xc8,
+  0xdd,0xb1,0xb7,0xb3,0x97,0xae,0x92,0x6b,0x71,0xa8,0xef,0xe0,0xe5,0xd5,0x74,0xd8,
+  0xb0,0xe1,0xe1,0x91,0x91,0x69,0xe9,0x69,0x65,0xcf,0x2e,0x79,0x02,0x04,0x04,0xcc,
+  0x90,0x4a,0x4d,0x35,0xfb,0xfd,0xd4,0xc8,0x79,0xf3,0xe7,0x6b,0x1e,0xe6,0xa6,0x96,
+  0xc4,0xc5,0x8d,0x78,0x7a,0xa4,0xe6,0x8a,0x26,0x4e,0x9a,0x7c,0x31,0x39,0x59,0x6d,
+  0x43,0xdc,0xbe,0xb8,0x67,0x9e,0xd1,0x2d,0xfc,0xb5,0x51,0xb3,0x2f,0x7f,0x77,0x65,
+  0xea,0x8b,0x2f,0x4a,0x1b,0xa4,0xb0,0x89,0x4f,0xe9,0x57,0x3f,0xdf,0x5d,0x71,0xbb,
+  0x8d,0x0e,0xb9,0x5f,0x54,0x38,0x77,0xde,0x3c,0xf3,0x53,0x94,0x1e,0xe2,0xf3,0xee,
+  0x7b,0xcb,0xf2,0x0a,0xf2,0x74,0x0f,0x91,0xeb,0xfa,0x3a,0x39,0x79,0xd9,0xf2,0xe5,
+  0xfd,0xfb,0x0f,0x28,0x1b,0x48,0x75,0x6c,0xea,0x08,0xe9,0x25,0x8f,0xc6,0x1e,0x3d,
+  0x7b,0xf5,0x5a,0xf1,0xe1,0x87,0x97,0x2e,0x5f,0x2e,0x1f,0x45,0xcb,0x56,0x7c,0x20,
+  0xb7,0xa6,0xac,0x7f,0xca,0xba,0xe8,0xf9,0x29,0x53,0x7e,0xb8,0x79,0xc3,0xac,0x0d,
+  0xf7,0x0f,0xc4,0x27,0xbc,0xf5,0xcf,0x05,0xa3,0xc6,0x8c,0xee,0xd4,0xa9,0x93,0x0c,
+  0x15,0x17,0x67,0x57,0x7b,0x5b,0xfb,0xba,0x75,0xea,0x96,0x0d,0x21,0xa9,0xd9,0xdd,
+  0xad,0x41,0xcb,0x16,0xad,0x7c,0xfd,0xfc,0x3e,0x5c,0xb9,0x32,0xf9,0xf2,0x25,0x6b,
+  0xe6,0x42,0x19,0x69,0x46,0x6a,0xda,0x8d,0xe8,0x98,0x98,0x67,0xc7,0xfb,0xb7,0x6f,
+  0xdf,0xa1,0x51,0xc3,0xc6,0xf5,0xed,0xea,0x4b,0x6b,0x4d,0x13,0xad,0xb4,0xd9,0xf2,
+  0x47,0x37,0x57,0xf7,0xe6,0xcd,0x5a,0xf4,0xed,0xdb,0x4f,0xda,0x90,0x95,0x93,0x55,
+  0x7e,0x6c,0x42,0x52,0xe2,0xe8,0x31,0x63,0x34,0x23,0x47,0xae,0xe5,0xdc,0x85,0x0b,
+  0x96,0x4f,0x1a,0xbd,0x65,0x8b,0x77,0xe9,0x2d,0x90,0xe2,0x3f,0x75,0xa9,0x8f,0xef,
+  0x8b,0x2f,0xfd,0xf5,0xca,0xd5,0xef,0xd5,0xc2,0x07,0x0e,0x25,0x48,0x31,0x53,0x49,
+  0x9f,0x9f,0x07,0xbf,0xff,0xa4,0x89,0x67,0xce,0x9d,0x53,0x0b,0x9f,0x3e,0x7b,0x6e,
+  0xe4,0x48,0xd3,0xa8,0x30,0x0d,0x0c,0x9f,0x11,0xc3,0x7d,0x4d,0xc3,0x7e,0xec,0xb8,
+  0x67,0x65,0xdd,0x6b,0xb9,0x49,0xdb,0x77,0xec,0x90,0xe1,0x54,0x76,0xa2,0xa1,0xde,
+  0xc3,0xe4,0x28,0xa9,0xc1,0x7f,0xc2,0xc4,0x6b,0xd7,0xaf,0x57,0xd8,0x87,0x32,0x12,
+  0xce,0x9e,0x3f,0x2f,0xb7,0x55,0xe6,0x57,0xeb,0xd6,0x6d,0x1b,0xb8,0x35,0x90,0x4e,
+  0xfb,0xe9,0x61,0x65,0x53,0xc7,0xb6,0xae,0xad,0xa3,0x83,0x53,0xe3,0x46,0x1e,0x1d,
+  0xda,0x77,0x94,0x53,0x7c,0x1a,0x14,0x24,0x85,0x73,0x0d,0x06,0x8f,0x04,0xe8,0xb7,
+  0x17,0x2e,0x32,0x8d,0x04,0x1f,0x9f,0xb2,0x39,0x3b,0xdc,0xdb,0x74,0xbd,0x0b,0xde,
+  0x7e,0xc7,0x72,0xec,0x96,0x59,0x36,0x65,0xca,0x54,0x39,0xca,0x7c,0xee,0xfb,0x8c,
+  0xf0,0x0b,0x59,0xb3,0x46,0x7d,0x98,0x00,0x46,0x76,0xc7,0xed,0x71,0x71,0x76,0xa9,
+  0x59,0xbd,0xa6,0x1a,0x28,0x8d,0x48,0xe1,0x66,0xcd,0x5b,0xbc,0xb5,0x60,0x41,0xf2,
+  0x37,0x97,0x2c,0x57,0x6e,0x94,0xff,0xde,0x4c,0xbf,0xf9,0xd5,0x89,0x13,0x7d,0xfa,
+  0xf6,0xa9,0xfd,0x50,0x6d,0x0b,0x27,0x7a,0xa8,0x66,0xad,0xde,0xbd,0xfb,0xc4,0xee,
+  0xdc,0x69,0xe5,0xaa,0x52,0xb2,0xa4,0xad,0xdb,0xb7,0xc9,0x83,0xa6,0x6e,0xdd,0xba,
+  0x56,0x5e,0x4b,0xed,0x5a,0xb5,0xbb,0x77,0xef,0x21,0x73,0xf9,0x6e,0xd6,0x5d,0xf3,
+  0xaa,0xae,0xa7,0x5c,0x6f,0xd6,0xac,0xb9,0xf5,0x7d,0x62,0xa4,0x5d,0xfb,0x76,0x99,
+  0xd9,0x3f,0x3f,0x42,0x25,0x44,0x06,0x87,0x86,0xca,0xb3,0x42,0x7b,0xa5,0x35,0x1e,
+  0x92,0xa7,0x84,0xee,0x45,0xa5,0xdd,0x4c,0x5b,0xb2,0x74,0xa9,0xab,0xab,0x9b,0x85,
+  0xb3,0xd8,0xd4,0xb2,0x79,0xf2,0xc9,0x41,0x87,0xe2,0x0f,0x49,0x30,0xba,0x9b,0x95,
+  0xd5,0xa8,0x51,0x63,0x4d,0x81,0x41,0x83,0x86,0xdc,0x57,0xfa,0x30,0x30,0x38,0x50,
+  0xce,0xab,0x29,0xe9,0xee,0xde,0xf0,0x48,0x52,0x92,0xda,0x8c,0x90,0xd0,0x35,0x6a,
+  0x61,0x89,0x14,0x87,0x13,0x13,0x8d,0x6e,0xc7,0x89,0xd3,0x27,0x3d,0x1f,0xf5,0x54,
+  0x5b,0xbb,0x2a,0x28,0xd8,0xe8,0x10,0x49,0x40,0x64,0x5d,0xa4,0x1e,0x32,0x66,0xcc,
+  0x18,0xf3,0x48,0x54,0x2e,0x37,0x3f,0x77,0x43,0x78,0x44,0x8b,0xe6,0x2d,0x2c,0x0c,
+  0x60,0x69,0xb6,0x44,0x3a,0x49,0x60,0x0b,0x4a,0x93,0x1a,0xe9,0x0a,0x4d,0x01,0x2f,
+  0x2f,0x2f,0xb9,0xdd,0xe5,0x75,0xde,0xc9,0xbc,0x33,0xf0,0xc9,0x81,0xd6,0xcf,0x05,
+  0xaf,0x66,0xcd,0x16,0x2d,0x59,0x9a,0x7a,0x43,0x9b,0x68,0xeb,0xb5,0x36,0x2f,0x62,
+  0x63,0x54,0x8f,0xc7,0x7b,0xca,0xa8,0xb3,0xa6,0xf2,0x96,0x2d,0x5b,0xa5,0xde,0x48,
+  0x2d,0x3f,0x7c,0x73,0x4c,0xb4,0x6d,0x3d,0x3b,0xb5,0x58,0x42,0xe2,0x61,0xcb,0xe7,
+  0x5d,0xbc,0xf4,0x5d,0xf5,0xa8,0xa6,0x9e,0x4d,0x4f,0x9f,0x39,0xa3,0x16,0x0e,0x8f,
+  0x8a,0x50,0x0b,0xcb,0x8d,0xde,0x7f,0xf0,0xa0,0x5a,0x78,0xef,0xbe,0x7d,0x12,0xf5,
+  0x34,0x85,0x65,0xfd,0xfc,0xc5,0xf6,0x1d,0x96,0x9b,0xf4,0xfe,0xf2,0x15,0x6a,0x27,
+  0xc8,0x83,0xe8,0xcc,0x59,0x9d,0x28,0x6f,0x3e,0x7d,0x64,0x51,0xf7,0xf2,0xb4,0x69,
+  0xb2,0xd0,0xb2,0xfe,0x06,0x79,0x78,0x34,0x91,0xc5,0xc6,0xa9,0xb3,0xa7,0xd4,0x0a,
+  0x65,0x6e,0x0e,0xf3,0x1e,0xae,0x1e,0x35,0xe4,0xa9,0xa7,0xcc,0xa7,0xad,0x2a,0x3b,
+  0x37,0xa7,0xc9,0xc3,0x4d,0xd4,0x73,0xcd,0x98,0x39,0xb3,0xc0,0x8a,0xdc,0x19,0x28,
+  0x73,0x30,0x21,0xa1,0xc6,0x5f,0x6a,0x58,0x39,0x98,0xcd,0xd5,0x7e,0xc8,0xa6,0x5d,
+  0xbb,0xf6,0xb1,0xbb,0x76,0x4a,0x06,0x6d,0x54,0xb9,0x6e,0xfc,0xed,0xd4,0xb1,0x73,
+  0x58,0xd8,0xfa,0xf6,0x6d,0x3b,0x58,0x73,0x5e,0x29,0xe3,0xd1,0xf8,0xe1,0x95,0x2b,
+  0x3f,0xba,0x57,0x54,0xc1,0xa8,0x4e,0xb9,0x91,0x3a,0x73,0xd6,0x2c,0x99,0xc2,0x55,
+  0xb8,0x9c,0x86,0xee,0x0d,0x8f,0x1e,0x3f,0xfe,0x40,0x6d,0xa9,0x29,0x5e,0x9e,0x5e,
+  0x55,0xe8,0x16,0x8d,0xb6,0xed,0xdb,0x67,0xe5,0xe4,0x96,0x57,0x5b,0xfc,0x63,0x49,
+  0x68,0xe8,0x3a,0x35,0xfe,0x4a,0x9b,0x75,0xe3,0xaf,0x3c,0x7e,0xc7,0x8d,0x7d,0x56,
+  0x92,0x77,0x6b,0x3a,0x4a,0x1a,0xbc,0x69,0xf3,0x66,0xc9,0x20,0x1c,0x1c,0x1c,0x34,
+  0xdf,0x7d,0x66,0xd4,0x68,0xb5,0xf2,0xa0,0xe0,0x10,0xdd,0x90,0x9a,0x68,0x75,0xfc,
+  0x75,0x71,0x71,0x3d,0x62,0x1c,0x7f,0x25,0x09,0x7a,0xf4,0x51,0x9d,0x3e,0x5c,0x15,
+  0x18,0x68,0x74,0x88,0xc4,0x5f,0x59,0x71,0xa9,0x87,0x8c,0x19,0x3b,0x56,0x7d,0x1e,
+  0x66,0x65,0xe7,0xcc,0x9d,0xff,0xba,0x24,0x3b,0xd6,0x74,0x8e,0xb3,0x93,0xf3,0xd2,
+  0x77,0xdf,0xbb,0x9b,0x95,0xd9,0xb9,0x4b,0x57,0xcd,0x77,0xdb,0xb4,0x69,0x9b,0x96,
+  0xfe,0xf3,0x0b,0x09,0x99,0x39,0x59,0x3e,0xbe,0x7e,0x95,0xba,0xcb,0x75,0xeb,0xd4,
+  0x1b,0x3c,0x68,0xc8,0xe5,0x2b,0x57,0x2c,0x6c,0x9f,0x5e,0xbd,0x76,0x2d,0x20,0x60,
+  0x86,0x43,0x7d,0x47,0xeb,0xc7,0xa7,0xe6,0x4d,0x09,0x49,0x63,0xed,0xf4,0xe2,0x6f,
+  0x7c,0x62,0xbc,0xe5,0xa9,0xb1,0x64,0xe9,0x7b,0xea,0x51,0x5e,0x9e,0x4d,0x4f,0x9d,
+  0x39,0xad,0x16,0x8e,0x88,0x88,0x52,0x0b,0xcb,0xa8,0xd8,0x77,0xf0,0x80,0x5a,0x78,
+  0x4f,0xdc,0x3e,0x75,0x09,0xed,0xe4,0xe8,0xbc,0xed,0x8b,0xed,0x96,0x9b,0xb4,0xe2,
+  0x83,0x0f,0x6b,0x3d,0x54,0x4b,0x73,0xa0,0xdc,0xa3,0xd3,0x67,0xcf,0x1a,0x1d,0x22,
+  0xcf,0x99,0xc8,0xa8,0x8d,0x6d,0xdb,0xb6,0x57,0xc7,0x61,0x85,0xe4,0x90,0x37,0xfe,
+  0xf1,0x96,0xfa,0xff,0x5c,0x93,0x41,0x25,0x49,0xb4,0x5a,0x7e,0xc8,0x50,0x6b,0xe2,
+  0xaf,0x76,0x0d,0x20,0xf1,0x77,0xa6,0x29,0xfe,0x56,0xe2,0x13,0x3a,0xfc,0x97,0x3b,
+  0x77,0xe1,0x82,0x95,0xab,0x71,0x5d,0x8f,0x3c,0xf2,0x48,0xe4,0xa6,0x8d,0x46,0x95,
+  0xeb,0xfe,0xfb,0x57,0xee,0xee,0x0d,0x9a,0x78,0x68,0x97,0x8e,0x96,0x99,0x56,0xd4,
+  0x3b,0x63,0x0b,0x8d,0x3f,0x54,0xba,0x91,0xf6,0xc3,0xd4,0x17,0x5e,0xb2,0x9c,0x4d,
+  0x5b,0xaa,0xdf,0xc9,0x59,0x93,0xf4,0x5d,0x4f,0x4d,0x69,0xfe,0x8b,0xe4,0xbf,0x1d,
+  0x3a,0x5a,0x93,0xff,0xca,0xcc,0x55,0xe3,0xaf,0x04,0xa3,0x39,0x73,0x5e,0x93,0xdc,
+  0xd6,0xfa,0xd3,0xb5,0x7e,0xac,0xcd,0xfa,0xf0,0x08,0xdb,0x7a,0xb6,0x9a,0xbf,0x9f,
+  0xfc,0xdc,0xf3,0x6a,0xa7,0x85,0x84,0xea,0xc7,0xdf,0xa4,0xa3,0x47,0xd5,0xc2,0xa1,
+  0x6b,0xd7,0xaa,0xe3,0xc4,0x94,0xff,0x1e,0x39,0x62,0x74,0x53,0x4e,0x1a,0xe6,0xbf,
+  0x41,0x46,0x87,0x18,0xe5,0xbf,0xa3,0x47,0x8d,0xd6,0xe4,0xbf,0x92,0xe9,0xaf,0x0d,
+  0x0b,0x73,0x74,0x70,0xb4,0xbe,0x73,0xdc,0xdc,0xdc,0x25,0xf4,0x4b,0xb4,0xd5,0xfc,
+  0x7d,0xd7,0xae,0xdd,0xee,0x64,0x66,0x96,0xd7,0x9c,0x93,0x97,0x3b,0xde,0x7f,0x62,
+  0x15,0x56,0x71,0x23,0x47,0x8f,0x91,0x61,0xa3,0x7b,0x5d,0xd9,0xb9,0xb9,0xfe,0xfe,
+  0x13,0xac,0x59,0x47,0x99,0x93,0xae,0xb8,0x75,0xe7,0x56,0x79,0x25,0xd1,0x31,0xfa,
+  0xf1,0x57,0x96,0xd0,0x96,0xe7,0xf8,0xe2,0x25,0x95,0x88,0xbf,0xe1,0x7a,0xf1,0xd7,
+  0xdd,0xad,0xc1,0xc1,0xf8,0x43,0x6a,0xe1,0xb8,0xfd,0x07,0xeb,0xd8,0x68,0x2f,0xca,
+  0xc9,0x94,0xff,0x56,0x10,0x7f,0x75,0xf3,0x5f,0x37,0x57,0x37,0xdd,0x5d,0xee,0x92,
+  0xd2,0x0f,0x05,0xd6,0x6f,0xd8,0xd0,0x58,0xd9,0xd8,0xb1,0xde,0xdc,0xf9,0xf3,0xd5,
+  0x6a,0xb3,0x72,0x72,0xbc,0xbd,0x7d,0xd5,0xc2,0xd6,0xc4,0x5f,0xb5,0x31,0x35,0xaa,
+  0xd7,0x08,0x98,0x1e,0x40,0xfc,0x85,0xf5,0x52,0xd3,0xd2,0x9c,0x9c,0x9c,0xab,0x3c,
+  0xaa,0x45,0xe3,0xc6,0x1e,0x71,0xfb,0xf7,0x17,0xe9,0xbd,0x87,0xa3,0x9b,0xff,0x56,
+  0x4d,0x9b,0x36,0xed,0x4e,0x9e,0xd2,0xd9,0x41,0x2a,0x29,0xfd,0x10,0x67,0xbc,0xff,
+  0x84,0x5a,0x35,0xb5,0xcb,0xe9,0x72,0x32,0xd3,0x1d,0xea,0x3b,0x48,0xb0,0x70,0x71,
+  0x76,0xb3,0xb3,0xb5,0x53,0xf7,0x2a,0x9d,0x9d,0x5c,0x8e,0x3c,0x18,0x74,0x24,0x8b,
+  0xd4,0x8d,0x1d,0x95,0xd5,0xae,0x43,0xbb,0xec,0x9c,0x9c,0xf2,0x6a,0x25,0xfe,0x4a,
+  0x20,0xd3,0xd9,0x7f,0xae,0xa9,0xb3,0xff,0x1c,0xbb,0x6b,0x97,0x1a,0x49,0xcb,0xd4,
+  0xac,0x51,0x53,0x2e,0xc4,0xd5,0xc5,0xcd,0xc9,0xd1,0x49,0xf3,0x1c,0x6b,0xf2,0x70,
+  0x13,0xa9,0x4d,0x53,0x3e,0x60,0xc6,0x4c,0xb5,0xdf,0x8c,0xf2,0x5f,0xdd,0xf8,0x6b,
+  0xb4,0xff,0x5c,0x51,0xfe,0x5b,0xf9,0xf8,0xdb,0xb3,0x97,0x7a,0xc8,0xb8,0x71,0xe3,
+  0x34,0xf1,0xf7,0xfc,0xc5,0x8b,0xcd,0x9b,0xea,0x2f,0x90,0x24,0x74,0x4a,0x9c,0x92,
+  0xce,0x71,0x71,0x76,0xad,0x5b,0xe7,0x81,0xae,0x36,0x7d,0x92,0x6b,0x57,0x5f,0x53,
+  0xbe,0x4f,0x9f,0xbe,0x72,0xde,0xf2,0x9a,0x25,0xcf,0x9a,0x3e,0x3d,0xc0,0x7c,0x90,
+  0xc8,0xba,0xce,0xb1,0xbe,0xe3,0x4f,0x15,0x2a,0xf7,0xae,0x9c,0x8c,0xc0,0x39,0xaf,
+  0xbe,0xaa,0x7e,0xce,0x9e,0x99,0x9d,0x29,0xfd,0x5f,0x85,0xc1,0x33,0x64,0xc8,0x50,
+  0xf3,0x8f,0x45,0x36,0xc7,0xc4,0xe8,0xee,0x3f,0x5b,0xf8,0x08,0xa0,0xcc,0xa2,0xc5,
+  0x3a,0xfb,0xcf,0x86,0xf9,0x6f,0x94,0x6e,0xfc,0x75,0x3f,0x70,0x48,0x67,0xff,0x79,
+  0x4f,0x5c,0x9c,0x9a,0xc6,0x3a,0x3a,0x38,0xed,0x88,0x8d,0xb5,0xdc,0xa4,0x65,0xcb,
+  0x3f,0x50,0x57,0xcb,0x32,0x0d,0x75,0xf3,0xdf,0xa2,0xe2,0xa2,0xa8,0x4d,0x9b,0x2c,
+  0xac,0xb5,0x64,0x64,0xda,0xdb,0xd9,0xcb,0x0d,0x92,0x01,0x29,0x33,0x5d,0x77,0x1d,
+  0xfe,0xda,0xbc,0x79,0xea,0xee,0x84,0x04,0xd9,0xa1,0xc3,0x87,0xa9,0x85,0x87,0x0d,
+  0x1b,0x5e,0x85,0xf8,0x4b,0xfe,0x8b,0xca,0xca,0xce,0xc9,0x36,0xdf,0x48,0x91,0x67,
+  0x48,0x7d,0xbb,0xfa,0x1e,0x8d,0x3d,0x1e,0x6b,0xd3,0xba,0xc7,0xe3,0x8f,0xf7,0x7c,
+  0xbc,0x67,0xab,0x56,0x6d,0xdc,0x5c,0xdc,0x2d,0x2c,0xdd,0x65,0xd4,0x0d,0x1b,0xe6,
+  0x9d,0x71,0xfb,0x96,0x5a,0xf9,0xb3,0x7a,0xf9,0xaf,0xf9,0x73,0x52,0x26,0x4b,0xdf,
+  0x7e,0xfd,0x67,0xcd,0x9e,0xbd,0x60,0xe1,0xa2,0x97,0xa7,0x4d,0xef,0xd6,0xad,0x47,
+  0xbd,0x3a,0xf5,0x8c,0xa6,0xd8,0x8c,0x59,0xb3,0xd5,0x77,0xb1,0xee,0x17,0x15,0x86,
+  0x87,0x47,0xe8,0x3e,0x15,0xe5,0x5a,0x9a,0x7a,0x35,0x9b,0x3c,0xf9,0xf9,0xb0,0x0d,
+  0xeb,0xf7,0xc6,0xed,0x93,0xb0,0x72,0xf0,0x50,0xc2,0xd6,0x2f,0x62,0x65,0xed,0xed,
+  0x3f,0x61,0x52,0xeb,0xc7,0x5a,0xdb,0xd9,0xda,0x97,0xa5,0x39,0x92,0x5f,0x6b,0x1e,
+  0x62,0xd7,0x52,0xae,0x1b,0xed,0x3f,0x97,0x3d,0xde,0xe5,0x51,0xec,0xe2,0xe4,0x6a,
+  0xfa,0x6a,0x51,0xff,0xfe,0x03,0x64,0xaa,0x96,0x57,0x6b,0x8a,0xbf,0x6b,0x74,0xe2,
+  0xaf,0xba,0xff,0x9c,0x7f,0xaf,0x60,0xea,0xd4,0x17,0x74,0xfb,0x41,0x5a,0xbe,0x68,
+  0xf1,0x92,0x6d,0x5f,0x6c,0x3f,0x7c,0x24,0x69,0xdf,0xfe,0x03,0xa1,0x6b,0xc3,0x7c,
+  0x7c,0x7c,0x25,0x85,0xb7,0x90,0xb2,0xcd,0x9d,0x3b,0x4f,0xbd,0x3b,0xbf,0x48,0xfc,
+  0x8d,0x3f,0x6c,0xf8,0xe1,0xa3,0x61,0xfc,0xb5,0xb8,0xff,0xdc,0xab,0xa7,0xce,0xfe,
+  0xb3,0x9a,0xff,0x7e,0xf4,0xc9,0x27,0xea,0x32,0x43,0x86,0xa2,0xac,0x06,0x5f,0x99,
+  0x35,0x5b,0x52,0x45,0x49,0xcc,0x0f,0x1e,0x3a,0x1c,0x1d,0x13,0x33,0x65,0xca,0x54,
+  0x8f,0xc6,0x0f,0x5b,0xf8,0x80,0x78,0xd0,0xa0,0xc1,0xe6,0xef,0xbb,0xde,0x2b,0xbc,
+  0xff,0xf7,0x37,0xde,0x94,0x01,0xef,0x60,0xef,0xd0,0xa3,0xc7,0xe3,0xd3,0xa6,0x4d,
+  0x0f,0x0e,0x09,0xdd,0xb5,0x67,0x8f,0x54,0x78,0xe0,0x60,0x42,0xd4,0xe6,0x4d,0x7f,
+  0xfd,0xdb,0xff,0xc8,0x04,0xd1,0xad,0xb0,0x79,0xb3,0x16,0x97,0x2e,0x7f,0xa3,0xb9,
+  0xa8,0x4d,0xd1,0x31,0x2e,0x2e,0x2e,0x46,0x73,0x47,0x6e,0x5c,0xcf,0x9e,0xbd,0x5e,
+  0x7e,0x79,0xfa,0x82,0xb7,0x17,0xbd,0xf9,0xd6,0xdb,0x53,0x5f,0x78,0xa9,0x7f,0xbf,
+  0x01,0x8d,0x1a,0x36,0x92,0x89,0xf0,0xf4,0xd3,0x23,0xb3,0x72,0xb2,0xcd,0xeb,0xd1,
+  0x8d,0xbf,0xf1,0x89,0x15,0xe4,0xbf,0x0b,0xf5,0x3e,0xff,0xad,0x64,0xfc,0x6d,0x60,
+  0x7d,0xfc,0x95,0x35,0xe1,0x8e,0x9d,0x3b,0x2d,0x37,0xc9,0x94,0xff,0xea,0xc4,0x5f,
+  0xfd,0xfd,0x67,0x99,0x1a,0xdd,0xba,0x75,0xd7,0x9d,0x89,0xf5,0xed,0x1c,0x64,0xf0,
+  0x2f,0x59,0xfa,0xde,0xb6,0xed,0xb1,0xb2,0x14,0x3c,0x92,0x78,0x54,0x4e,0xbd,0x66,
+  0xdd,0xba,0xd9,0x73,0x66,0xf7,0xe8,0xde,0xc3,0xd5,0xc5,0xb5,0x7c,0xd0,0x1a,0xc5,
+  0x5f,0xfd,0xfd,0xe7,0x61,0x55,0xc9,0x7f,0x89,0xbf,0xa8,0x2c,0x59,0x5b,0x76,0xec,
+  0xd8,0x59,0x06,0x8f,0x2c,0x20,0x07,0x0c,0x78,0xe2,0xf5,0xd7,0xff,0xbe,0x63,0x67,
+  0xec,0xc5,0x4b,0xc9,0xe9,0xb7,0x6f,0xe7,0xe4,0xe6,0x65,0x66,0xe7,0xdc,0xcc,0x48,
+  0xff,0xf7,0x57,0x27,0x96,0x2d,0x5f,0x21,0x53,0xc0,0xe8,0x93,0x17,0xc9,0x32,0x3e,
+  0xfb,0x7c,0xab,0x5a,0xb9,0xee,0xbf,0xbf,0x51,0xae,0x5d,0xdb,0x76,0xe1,0x11,0x1b,
+  0x33,0xb3,0x7e,0x1e,0xe7,0x69,0xe9,0x19,0x2b,0x56,0x7e,0xd8,0xc0,0xbd,0x81,0x6e,
+  0x79,0xc9,0xec,0xce,0x5c,0xd0,0x4e,0xcf,0x6f,0x2e,0x5f,0xee,0xdc,0xb9,0x8b,0x5a,
+  0x58,0x32,0xc7,0xbf,0x4d,0x9b,0x26,0x59,0x52,0x61,0xb1,0x4e,0x62,0x5e,0x58,0x54,
+  0x2c,0x11,0x36,0x3c,0x72,0xe3,0xa8,0xd1,0x63,0x65,0xbd,0x51,0x9a,0xff,0x3e,0xb0,
+  0xff,0x7c,0x37,0x2b,0x6b,0xf0,0x60,0xed,0x8b,0x3a,0xd5,0xff,0x13,0x01,0x9f,0x7e,
+  0x66,0x64,0x7c,0xe2,0x91,0x63,0x5f,0xfe,0xfb,0xf8,0x57,0x5f,0x99,0x9c,0x30,0x74,
+  0xee,0xc2,0x79,0xf3,0x35,0x43,0xf1,0x8f,0x12,0xc8,0xf4,0xf2,0x5f,0xe5,0xfd,0xab,
+  0xab,0xd7,0xaf,0x75,0xec,0xd0,0x49,0x3d,0xfb,0xc0,0x27,0x06,0x9e,0x55,0xf6,0xe8,
+  0x72,0xf3,0x73,0x25,0x39,0x6a,0xd6,0xbc,0x99,0x51,0x08,0xfe,0xc7,0x82,0xb7,0xd5,
+  0x4e,0x08,0x0a,0xf9,0x05,0xe2,0xaf,0x85,0xe4,0xcb,0x30,0xfe,0xae,0x5e,0x6d,0x74,
+  0x88,0xd1,0xfe,0xb3,0x26,0xff,0xcd,0x2b,0xc8,0x1f,0xf7,0xec,0x78,0xb5,0x58,0x8b,
+  0xe6,0x2d,0x63,0x77,0xed,0xd2,0xd4,0x29,0xf1,0x34,0xe1,0xc8,0x91,0xde,0x7d,0xfa,
+  0xd5,0xac,0xae,0x3f,0x7a,0x65,0xf5,0x68,0xfe,0x72,0x5a,0x61,0x71,0x51,0xc8,0x9a,
+  0xb5,0xd3,0xa6,0xcf,0xdc,0x1e,0x1b,0x7b,0x27,0xf3,0xae,0xfa,0xd0,0x2e,0x2c,0x2a,
+  0xda,0x1b,0x17,0xd7,0xb6,0x6d,0x3b,0xb5,0x2a,0x09,0x9a,0x61,0x61,0xeb,0xcd,0x0f,
+  0xb9,0x75,0x27,0xa3,0x6f,0xdf,0xbe,0xba,0xe7,0x95,0xf5,0xe1,0x53,0x43,0x87,0xee,
+  0xdc,0xbd,0xfb,0xce,0x5d,0xb3,0x77,0xff,0x7e,0x2c,0xc9,0xcd,0xcb,0x3f,0x7b,0xfe,
+  0x6c,0x60,0x70,0xf0,0xea,0xc0,0x60,0xf3,0x97,0xe7,0x7f,0x9b,0xf7,0xaf,0x8c,0xe2,
+  0xaf,0xee,0xfe,0xb3,0x6e,0xfc,0xb5,0xe6,0xfd,0xab,0x65,0x2b,0x3e,0x50,0x5f,0xdc,
+  0x32,0x7a,0xff,0x6a,0x5a,0xc0,0x2b,0xba,0xbb,0x5b,0x7d,0xfb,0xf6,0xfb,0x6c,0xeb,
+  0x56,0xdd,0x17,0x95,0x8b,0x4b,0x4a,0x32,0xb3,0x32,0x0f,0x27,0x25,0x05,0xcc,0x9c,
+  0xd5,0xb2,0x65,0xab,0x9a,0x35,0x6a,0xbe,0x36,0x77,0x9e,0xfa,0xb3,0x72,0x46,0xf1,
+  0x77,0x68,0x55,0xf3,0xdf,0x80,0x00,0xf6,0x9f,0x51,0x39,0xcf,0x4d,0x79,0xf1,0xb9,
+  0xe7,0xa7,0xc4,0xed,0xdf,0x2f,0x39,0xac,0xd1,0x4f,0x52,0x14,0x16,0x17,0x7e,0x77,
+  0xf5,0xea,0xdc,0xb9,0xf3,0x8d,0xf6,0xdf,0xa4,0x06,0x75,0x22,0x58,0xd8,0x7f,0xf6,
+  0xf0,0xf0,0x38,0x7a,0xfc,0x98,0xba,0x59,0x27,0x0d,0xf8,0x74,0x75,0x90,0xee,0x5e,
+  0x93,0x4d,0xed,0x3a,0x4b,0xdf,0x7b,0x5f,0xf3,0x7a,0xff,0xfb,0xcb,0x96,0xab,0x1f,
+  0x24,0xc9,0x5a,0xe2,0x9d,0x77,0x16,0x9a,0xe7,0x0e,0xba,0xe4,0x39,0x29,0x65,0xf6,
+  0xc4,0xed,0x9f,0x1e,0x10,0x70,0x52,0x79,0x16,0x1d,0x4e,0x4c,0xea,0xd4,0x49,0x27,
+  0xb2,0x0b,0x49,0xdb,0x57,0x07,0x85,0x54,0xe1,0x45,0x47,0xa3,0xcf,0x7f,0x85,0x26,
+  0xfe,0x9e,0x3a,0x73,0x46,0x32,0x14,0x4d,0x19,0xc9,0xf8,0xb6,0x7c,0xf6,0x99,0xee,
+  0x4b,0x3e,0xd2,0x93,0x3b,0x77,0xed,0x96,0x44,0x4f,0xb7,0xc1,0x0b,0x17,0x2f,0x52,
+  0x0f,0x09,0x0a,0x09,0xfe,0xff,0xc7,0xdf,0x04,0x4b,0xf9,0xef,0x09,0x83,0xfd,0x67,
+  0x8b,0xef,0x3f,0xeb,0xed,0x3f,0x6b,0xf2,0xdf,0x8c,0x5b,0x19,0xfd,0xfa,0xf5,0x53,
+  0x8b,0xbd,0xf1,0xe6,0x5b,0xba,0x3f,0xb9,0x29,0x3d,0x76,0xe6,0xdc,0xf9,0x6e,0xdd,
+  0x7b,0xe8,0x76,0x8e,0xac,0xa6,0x34,0x4f,0xe6,0xdc,0x82,0x3c,0x21,0x8b,0x25,0xa3,
+  0x76,0x4a,0x08,0x5e,0xb5,0x3a,0x48,0xad,0x4a,0xba,0x68,0xce,0xab,0xaf,0x95,0x4f,
+  0x22,0x59,0x7a,0x85,0x47,0x46,0xd8,0xdb,0xda,0xab,0x25,0x25,0xfb,0x9b,0xfc,0xdc,
+  0xf3,0xd7,0x53,0x53,0x8c,0x5e,0xd9,0x92,0x63,0x35,0x93,0x71,0x73,0xcc,0x16,0x83,
+  0xfd,0x67,0xc3,0x8f,0xe0,0xcb,0x2c,0xd2,0x8d,0xbf,0x5e,0x4d,0x4f,0x9f,0xad,0x44,
+  0xfc,0x35,0xca,0x7f,0xd5,0xd9,0x67,0xcd,0xfe,0xf3,0xfb,0xcb,0x97,0x5b,0xb9,0xff,
+  0x2c,0x8f,0x1d,0x17,0x57,0xed,0xee,0x81,0x44,0xba,0xc1,0x83,0x86,0x7c,0x9d,0x9c,
+  0x5c,0xe1,0xcf,0x0b,0xcb,0x02,0xe6,0x62,0xf2,0xa5,0x05,0xef,0x2c,0x0c,0xd2,0x1b,
+  0x75,0x46,0xfb,0xcf,0x4f,0x0d,0x1f,0x5a,0xb5,0xf8,0xfb,0xca,0x2b,0xb3,0x78,0xff,
+  0x19,0x95,0x72,0xf5,0x7a,0x4a,0x6e,0x5e,0xae,0x35,0x25,0xb3,0x73,0xb2,0x7d,0x7c,
+  0xfd,0x6a,0x54,0xd7,0x49,0xb2,0x3a,0x77,0xea,0x7c,0x2d,0x45,0xfb,0xb3,0x7b,0xba,
+  0xef,0x5f,0x55,0x2f,0x7d,0x5f,0x74,0xe1,0xe2,0x25,0x46,0x67,0xc9,0xb8,0x9d,0x31,
+  0xde,0xdf,0x5f,0xf7,0x40,0x5f,0x5f,0x3f,0xf3,0x79,0x21,0xb3,0x60,0xd0,0xa0,0xc1,
+  0x6a,0xb1,0x71,0xe3,0xfd,0xd3,0xd2,0x6f,0x5a,0xdf,0x03,0xa6,0x7f,0x61,0x40,0x59,
+  0xb5,0x4a,0x44,0xdb,0xb3,0x77,0xaf,0x93,0xc1,0xeb,0xb5,0x9e,0x9e,0x9e,0x3b,0x62,
+  0x2b,0xd8,0x64,0x53,0x59,0x1f,0x7f,0x75,0x83,0x97,0xb3,0x93,0xf3,0xa9,0xd3,0x3a,
+  0x7b,0x86,0xe5,0x0d,0x7e,0x75,0xee,0x5c,0xdd,0x7d,0xd1,0xe5,0x2b,0x3e,0x50,0xcb,
+  0xff,0x22,0xf1,0xd7,0xc2,0xfb,0x57,0x86,0xf1,0xd7,0x72,0xfe,0x6b,0x45,0xfc,0xfd,
+  0xe1,0x66,0x5a,0x77,0x25,0x98,0x4a,0xf3,0x36,0x44,0x46,0x5a,0xe8,0xfc,0xb0,0xf5,
+  0x1b,0xec,0x6c,0x75,0xe2,0xd7,0xe8,0x31,0x63,0x2d,0xfc,0x2b,0x22,0x46,0xe2,0x0f,
+  0x1f,0x56,0xab,0xaa,0xf1,0x97,0xff,0x63,0xef,0xba,0x83,0xa2,0x4a,0xb6,0xfe,0x3f,
+  0xc6,0x05,0x95,0x8c,0x84,0x25,0x09,0x0a,0x98,0x40,0x17,0x30,0xad,0x88,0x04,0x73,
+  0x76,0x15,0x31,0x3e,0x15,0x10,0x94,0xa4,0xae,0x6b,0x40,0x05,0xc3,0xaa,0x80,0xa8,
+  0xa0,0xa2,0x6b,0x06,0x23,0x62,0xc2,0x8c,0xa8,0xeb,0x02,0x4a,0x0e,0x2a,0xa0,0x32,
+  0x60,0x24,0x07,0x45,0xb2,0xb0,0x55,0xdf,0x19,0x46,0xe7,0x0d,0xb7,0x4f,0xdf,0x49,
+  0xb8,0xaf,0xde,0xf7,0xa6,0xea,0x57,0x16,0x33,0xf6,0xed,0xb9,0xb7,0x6f,0x77,0xff,
+  0xce,0x39,0x7d,0x42,0x47,0x67,0x17,0x57,0x7e,0x44,0x00,0xcc,0xab,0x05,0x0b,0x17,
+  0xa1,0xeb,0x05,0xd4,0xfc,0xdc,0x97,0x42,0xc2,0xf7,0x18,0x38,0x1f,0x19,0x89,0xfa,
+  0x03,0x08,0xb5,0x3f,0xef,0xdc,0x15,0x48,0x5e,0x25,0x26,0xff,0xe2,0xe7,0xbf,0x31,
+  0xf7,0xee,0x91,0xfe,0x81,0x30,0x4b,0x6f,0x11,0x56,0x08,0x06,0x44,0xe4,0x5f,0x58,
+  0x2f,0x87,0xfe,0x38,0x42,0xde,0x0f,0x70,0xdf,0x93,0xc4,0x44,0xd1,0x93,0x75,0x34,
+  0x7e,0x69,0xfa,0x84,0xf1,0x29,0x4d,0xff,0x1d,0x37,0x4e,0x42,0xfd,0xd7,0xcb,0xcb,
+  0x4b,0xa6,0xff,0xca,0xf0,0xfd,0x70,0x27,0x26,0x16,0x16,0x23,0x39,0x63,0xf5,0xf5,
+  0xf4,0x13,0x93,0x13,0x19,0x8d,0x69,0xfa,0xaf,0xa5,0xe5,0x90,0xd7,0xef,0xde,0xb2,
+  0xfc,0xca,0xa3,0xb8,0x78,0xd4,0xef,0xd7,0x40,0xdf,0xe0,0x15,0x87,0xc3,0x6f,0x96,
+  0x92,0x9e,0xae,0xa9,0xa1,0xc5,0x68,0x03,0xec,0x96,0x4a,0xf1,0xd4,0x92,0x00,0x27,
+  0xc3,0xc3,0x35,0x35,0x99,0x3f,0xc1,0x83,0x9e,0xae,0x5e,0x4a,0x5a,0x8a,0x58,0x19,
+  0x7b,0x68,0xf1,0x47,0xa4,0xff,0x73,0x76,0x6e,0xae,0x71,0x1f,0x13,0x46,0x33,0xb9,
+  0x1f,0xe4,0x59,0xce,0x5b,0x5b,0xb8,0xf9,0x10,0x9e,0x1a,0x19,0xf5,0x26,0x6f,0x35,
+  0x78,0xef,0x3e,0xb2,0x71,0xfb,0x9c,0xff,0xd2,0x9d,0x6f,0xa9,0xfe,0xcf,0xac,0xfc,
+  0x3b,0xf2,0x67,0xc4,0x5a,0xcb,0x88,0xff,0xad,0xfc,0x58,0x39,0x7e,0x02,0xa2,0xb6,
+  0x84,0x86,0x1e,0x60,0x19,0x9c,0xa2,0xe2,0x22,0x7b,0x7b,0x07,0xf2,0x2a,0x27,0xa7,
+  0xb9,0x2c,0xae,0xf5,0x28,0x40,0x39,0x85,0x89,0x41,0x76,0x05,0xfc,0xbb,0xd4,0xd9,
+  0x85,0x9f,0x2a,0x24,0x2f,0x9f,0x43,0x1a,0x31,0x3a,0xb4,0x5a,0x9e,0xaf,0xdf,0xbc,
+  0x29,0x6e,0xee,0xac,0x48,0x8a,0xfe,0x2b,0xd4,0xfe,0x8c,0xea,0xbf,0xe2,0x9e,0xff,
+  0xa2,0xf6,0x67,0x94,0x7f,0x45,0xf1,0x7f,0xde,0xb3,0x77,0x1f,0xa9,0x38,0x93,0xfc,
+  0x5b,0xf9,0xa9,0x6a,0xe6,0x2f,0xb3,0xc8,0x41,0x5e,0x8b,0x39,0x33,0x4b,0x00,0x69,
+  0xce,0x7f,0xc9,0xf8,0x5f,0x99,0xff,0xb3,0x0c,0xdf,0x1b,0xcf,0x73,0xb3,0x8d,0xfb,
+  0x18,0x63,0x2b,0x54,0x23,0xf6,0xfe,0x7d,0x46,0x63,0x1a,0xff,0xae,0x59,0xb3,0x96,
+  0xb4,0x3c,0x0b,0xa2,0xba,0xa6,0xc6,0xb4,0x6f,0x7f,0xf2,0x42,0x90,0xff,0x1f,0xfc,
+  0xf9,0x75,0x1f,0x80,0xed,0x2b,0xe2,0xcc,0x99,0xee,0xf2,0x4c,0x8d,0xc0,0xc2,0xc2,
+  0xaa,0x1d,0x4d,0x40,0x9f,0x6b,0x3e,0xef,0xd8,0xb1,0xb3,0x1b,0xf1,0x2b,0x3c,0x38,
+  0x38,0x38,0x64,0xe7,0x0a,0xc9,0x3e,0xc4,0xc0,0xb1,0x13,0x22,0xc5,0xff,0x96,0x94,
+  0x96,0x8e,0x1c,0x89,0x78,0x22,0xf9,0xfb,0x6f,0x61,0x59,0xe0,0x65,0x95,0x65,0x13,
+  0x30,0x7b,0x5a,0xe8,0x7e,0x84,0x98,0xbe,0x37,0xff,0x4a,0x76,0xfe,0x8b,0xc6,0xff,
+  0x3a,0x3a,0x3a,0x0a,0xf2,0x6f,0x7d,0x63,0xa3,0xb3,0xcb,0x32,0xb2,0xd9,0xac,0xd9,
+  0xb3,0x51,0x3f,0xc0,0x6f,0x57,0x35,0xac,0x5d,0xbb,0x8e,0xbc,0x6a,0xf1,0xe2,0x25,
+  0x62,0xbd,0xc1,0xc6,0x2f,0x8d,0x89,0x49,0x49,0x23,0x46,0x20,0xf7,0xd9,0xa9,0x63,
+  0xa7,0x95,0xab,0x57,0xf3,0xa7,0xdf,0xfd,0x07,0x0f,0x51,0x8d,0xb5,0x5f,0xbf,0xfe,
+  0xa8,0x3a,0xc6,0x8e,0xff,0x20,0xff,0xb6,0xe6,0xdf,0x40,0xe3,0x7f,0x11,0xfb,0xb3,
+  0x14,0xfc,0xcb,0xf4,0xbf,0xe2,0x14,0x14,0xf0,0xbc,0x53,0x18,0xfd,0xdf,0xbd,0x7b,
+  0x57,0xdc,0xd1,0x43,0x21,0xf3,0xbf,0x92,0xe1,0xbf,0x0b,0xe9,0x59,0x59,0xbd,0x30,
+  0x91,0x5e,0x4d,0x45,0x8d,0x3c,0xf4,0x41,0xf9,0xb7,0x4b,0xe7,0x2e,0xd7,0x6f,0x08,
+  0x71,0xcf,0x00,0xcc,0x5f,0x88,0xd4,0x6e,0x00,0x84,0x9f,0x3d,0xcb,0x6b,0xd0,0xf8,
+  0xa5,0xc9,0x7f,0xcb,0x16,0x86,0x63,0x06,0x10,0x99,0x8b,0x9b,0x7b,0x4b,0xab,0x5f,
+  0x19,0xd7,0xf1,0xe9,0x6f,0xee,0x1f,0xcd,0x2d,0xcd,0x00,0xf8,0xc8,0xfd,0x12,0xfd,
+  0xf8,0x37,0xf7,0x23,0xef,0x7b,0xf2,0x4e,0x60,0xab,0xf4,0xf4,0xf2,0xee,0x8a,0xe9,
+  0xe3,0xb0,0xe2,0x66,0xce,0x9a,0x5d,0x5a,0x21,0x6a,0x39,0x63,0xd1,0xfd,0xaf,0x40,
+  0x3e,0xf1,0xf0,0x44,0x82,0x56,0x0c,0xf4,0x0d,0xa2,0x2e,0x5f,0xa6,0xe5,0xd7,0x85,
+  0x9d,0x9f,0x0c,0x75,0x81,0xce,0x81,0x6a,0xc9,0xc6,0xed,0xe2,0x7f,0xd5,0xee,0xfc,
+  0x2b,0x62,0xfe,0xab,0xe3,0x27,0x4e,0x02,0xd9,0x31,0x9a,0x29,0x29,0x28,0xfd,0xbe,
+  0x63,0x07,0x35,0x79,0xef,0xdf,0x2d,0x27,0x4e,0x21,0x4a,0xeb,0x92,0x25,0x4b,0x45,
+  0x7c,0x7d,0xb0,0xeb,0xa6,0xa4,0xa7,0x6f,0xdd,0xb6,0x8d,0x16,0x1b,0xde,0x4d,0xae,
+  0xdb,0xf1,0xe3,0x27,0xf8,0xb1,0x78,0x61,0x87,0xff,0x20,0xdb,0xc0,0x14,0x5d,0xd6,
+  0x3a,0x45,0xc5,0x45,0x64,0x94,0x84,0xfc,0xfb,0xcf,0xfb,0x5f,0xdd,0x14,0xc5,0xff,
+  0x59,0x84,0xfc,0x57,0x49,0xc9,0xa9,0x5a,0x9a,0xda,0x8c,0x66,0x03,0xfa,0x0d,0xc8,
+  0x7d,0xf1,0x82,0xbf,0xba,0xbf,0xe2,0xdb,0xfa,0x65,0xff,0xc8,0xb8,0x8d,0x76,0xf7,
+  0xbf,0x92,0xf1,0xaf,0x0c,0xdf,0x0f,0xc0,0x53,0xc1,0xfb,0x42,0xd0,0x24,0x00,0x9a,
+  0x1a,0x5a,0x0f,0xff,0x62,0xe6,0xe1,0x99,0x3f,0x1f,0xe1,0x5f,0x58,0x65,0xa4,0x07,
+  0x2f,0x09,0xd8,0x48,0xc9,0xa5,0x0d,0x08,0x08,0x0a,0xe2,0x35,0xa8,0xad,0xaf,0x73,
+  0x73,0x5f,0x4e,0x1e,0x77,0x9a,0x9a,0xf6,0x9d,0x35,0xdb,0x11,0xe0,0x38,0xc7,0xe9,
+  0x17,0xd0,0x88,0x1c,0xe7,0xc0,0x1f,0x3c,0xc0,0xdf,0xe4,0xc7,0x5f,0xa0,0x71,0xeb,
+  0x97,0x8b,0x16,0x2f,0x79,0x9c,0xc8,0x34,0xa1,0xf3,0x50,0x5c,0x5a,0x36,0xc7,0x69,
+  0x2e,0x1a,0x57,0x28,0xd7,0x55,0xce,0xc3,0xd3,0xb3,0xb2,0xaa,0x52,0xc4,0x01,0x44,
+  0xf9,0x17,0xcd,0xbf,0x11,0x17,0x17,0xaf,0x4a,0x84,0x66,0xc3,0xee,0x0d,0x9b,0xa1,
+  0xaf,0xaf,0x6f,0x7c,0x42,0x42,0x71,0x69,0x71,0x6d,0x7d,0x2d,0xa8,0x63,0x5c,0x59,
+  0xa2,0x15,0x8d,0x4d,0x8d,0x5b,0xb7,0x6d,0x67,0x5c,0x02,0xbc,0x79,0x08,0x0b,0xb9,
+  0x6d,0x97,0xf3,0x5f,0x96,0xf8,0xdf,0xf4,0x8c,0x8c,0x5e,0x68,0xfe,0x2b,0xf1,0xcf,
+  0x7f,0x19,0xfa,0x2f,0x20,0xbf,0xe0,0xcd,0x20,0xf3,0x41,0xa4,0xbf,0x77,0x77,0xf9,
+  0xee,0xce,0xce,0x2e,0xb7,0xef,0xdc,0x79,0xf7,0xe1,0x3d,0x6c,0x92,0x0d,0x4d,0x0d,
+  0xfc,0xc1,0x01,0x80,0xe0,0x47,0x76,0xce,0xce,0xbf,0x20,0x08,0x7d,0x28,0x2a,0xbc,
+  0x77,0xff,0xfe,0xf6,0xdf,0x77,0xd8,0xda,0xd9,0x6b,0x6a,0x6a,0xb1,0x64,0x44,0xe9,
+  0x6d,0xd4,0xfb,0x79,0x4e,0x36,0xff,0x5d,0xc3,0x6b,0x42,0x26,0xcc,0x0f,0x72,0xfb,
+  0x0f,0x1e,0x94,0x60,0xf5,0xd1,0xf3,0x5f,0x09,0xcb,0xbf,0x21,0x56,0xfe,0x2b,0xa9,
+  0xf9,0x57,0x14,0xfd,0x77,0xf7,0x9e,0x7d,0xa4,0x40,0x4b,0xda,0x9f,0x6f,0xde,0xba,
+  0x4d,0x7a,0xaf,0xa9,0xa9,0xa9,0x4f,0x9c,0x34,0x99,0xbf,0xba,0xd1,0x45,0x4d,0xfb,
+  0x78,0xf4,0xc4,0x09,0x41,0x07,0x4e,0x7a,0xfe,0x2b,0x49,0xfc,0xaf,0x64,0xf6,0x67,
+  0x19,0xbe,0x2b,0x9e,0x66,0x67,0xf7,0xee,0x83,0x1c,0x2f,0x76,0xe0,0xfa,0x23,0x19,
+  0x91,0x2e,0xc4,0x68,0xfc,0x91,0xa1,0xa1,0xd1,0xeb,0xb7,0x6f,0x84,0xfe,0x16,0xa8,
+  0x6c,0x68,0x2c,0xb0,0x9f,0x9f,0x3f,0xaf,0xc1,0xe7,0xba,0x56,0xe7,0x16,0x89,0x92,
+  0x67,0xa2,0x50,0x56,0x52,0xb9,0x1a,0x1d,0x4d,0xbb,0x9f,0xec,0xdc,0x5c,0x6b,0x1b,
+  0x1b,0xf4,0x42,0xd0,0x4a,0xf6,0x86,0x84,0x8a,0xb2,0xee,0xc4,0xe2,0xdf,0xea,0xcf,
+  0x9f,0x81,0x4a,0xd0,0x98,0xaf,0xce,0x9d,0x3a,0xeb,0x68,0xeb,0xd8,0xda,0xd9,0x2d,
+  0x75,0x71,0x5e,0xb7,0x7e,0x7d,0x40,0x40,0x20,0x0f,0x3b,0x77,0xee,0x1a,0x3f,0x9e,
+  0x69,0x7f,0x86,0x1e,0xc2,0x0e,0x23,0x21,0xb7,0x61,0x87,0xda,0x81,0x7f,0x59,0xf5,
+  0xdf,0xef,0xe5,0x7f,0xd5,0xd2,0x1a,0x55,0xb4,0x2f,0x24,0x04,0x9d,0x21,0x30,0x25,
+  0xd4,0xd5,0x7a,0x0e,0x1b,0x36,0x62,0xfe,0x82,0x85,0x6b,0xd7,0xad,0xfb,0x7d,0xc7,
+  0x4e,0xfe,0xf8,0x38,0xbb,0xb8,0x90,0xed,0x59,0xf8,0xf7,0x7d,0x51,0xe1,0xfe,0x03,
+  0x07,0x6c,0x6d,0xed,0x7a,0xaa,0xf7,0x24,0xd5,0x6d,0x06,0xba,0x74,0xea,0xf2,0xeb,
+  0x9a,0x7f,0xd7,0xb9,0x68,0xfa,0xd2,0x04,0x7a,0x2e,0xd9,0x4c,0x49,0x51,0xf9,0xd2,
+  0xe5,0xcb,0x12,0xac,0xbe,0xff,0x22,0xfe,0xbd,0x75,0x5b,0x12,0xfd,0x97,0xe4,0xdf,
+  0xa8,0xcb,0x57,0xbb,0xc9,0xe3,0x09,0x01,0x24,0x83,0xb3,0xab,0xab,0x60,0x98,0x86,
+  0x34,0xf9,0x27,0x65,0xfa,0xaf,0x0c,0xff,0x18,0xca,0x2b,0x2b,0x0e,0x84,0x85,0xf5,
+  0xc1,0x4e,0x7e,0x79,0x18,0x6d,0x33,0xba,0xb4,0x9c,0x69,0x86,0x45,0xfd,0x9f,0x4d,
+  0xfb,0xf6,0x2b,0x2c,0x12,0x9e,0xac,0xfe,0xec,0xb9,0x73,0x68,0xe0,0x06,0x3f,0x8f,
+  0x5c,0x75,0x4d,0xf5,0xac,0x59,0xb3,0xdb,0x71,0x6d,0xc2,0xf2,0x67,0x37,0x8c,0xbf,
+  0xcc,0xcb,0xef,0xdb,0xb7,0x3f,0xca,0xf8,0xaa,0xca,0xaa,0xa8,0x8e,0x49,0x02,0x3d,
+  0xff,0x45,0xf3,0x5f,0xb5,0x70,0x1d,0x7d,0x4b,0xa6,0xcf,0x98,0x29,0x71,0x5e,0xcd,
+  0xaf,0x9d,0x77,0xec,0x7c,0x30,0x0c,0xe1,0xdf,0x76,0xd1,0x7f,0x25,0xf0,0xbf,0xda,
+  0x17,0x1a,0x4a,0xbb,0x44,0xc4,0xf8,0xdf,0xaf,0x8d,0xeb,0xeb,0xd6,0xac,0xdd,0x80,
+  0x52,0x92,0x58,0x00,0xfe,0x25,0x43,0x8d,0xa0,0xf3,0xa8,0x4b,0x97,0x40,0x56,0x44,
+  0xbd,0x97,0x49,0xc0,0xde,0xbb,0x78,0xe9,0x92,0x92,0xb2,0x7f,0xa7,0x6b,0x06,0xfe,
+  0x75,0x71,0x45,0x0e,0xa9,0xd1,0x93,0x1a,0x51,0x40,0x3b,0xff,0x15,0x9e,0xff,0x4a,
+  0xea,0xf8,0x23,0x96,0xf3,0x5f,0x2c,0xff,0x95,0xf2,0x95,0x6b,0xd7,0xd8,0x6f,0x09,
+  0x8d,0xff,0x55,0x57,0x53,0x67,0xe4,0x9f,0x3c,0x7d,0xfa,0x34,0xd9,0x4c,0x1a,0x78,
+  0x7a,0x79,0x89,0xc2,0xbf,0xa2,0xe4,0xbf,0x42,0xeb,0x2f,0xc8,0xf8,0x57,0x86,0x76,
+  0x04,0x08,0xf3,0xef,0x0a,0xdf,0x47,0x5d,0xba,0x3c,0x65,0xea,0x54,0x50,0x0f,0x69,
+  0xca,0x26,0x7c,0xbf,0x69,0xd3,0x66,0xd2,0x89,0x14,0xe5,0x5f,0x13,0xd3,0xbe,0xa2,
+  0x54,0x19,0x3b,0x15,0x1e,0xd1,0x03,0xe3,0xdf,0x75,0xbe,0x1b,0x79,0x0d,0x3e,0xd7,
+  0xd6,0x38,0x39,0xcd,0x6f,0xc7,0xb5,0xa9,0xa1,0x81,0x07,0x39,0x0a,0x22,0x3a,0xfa,
+  0x16,0xe9,0x96,0xcc,0x1b,0x01,0x5d,0x1d,0xdd,0xbf,0x12,0xfe,0x62,0xaf,0x96,0x48,
+  0xf3,0x7f,0xee,0x40,0xc4,0x1f,0xf1,0xf1,0x8a,0xc3,0xf1,0xf0,0xf4,0x06,0x7e,0x17,
+  0xab,0x46,0x95,0x20,0xb8,0xe7,0xbf,0x47,0xd0,0xf3,0x5f,0x69,0xf9,0x57,0x4d,0x55,
+  0x8d,0x35,0xfe,0x17,0x3f,0xff,0xdd,0x15,0x18,0x44,0xbb,0x84,0xc6,0xbf,0xa4,0xfd,
+  0x99,0x87,0x92,0xb2,0xb2,0x80,0xc0,0x60,0x6d,0x2d,0x6d,0x09,0x72,0xf2,0xf3,0xc1,
+  0xd5,0x7f,0xdb,0xf2,0x2f,0xbc,0xc4,0xb0,0xc3,0x87,0x75,0x45,0xcb,0x52,0x0e,0xef,
+  0xa5,0xa7,0x5a,0x4f,0x67,0x57,0xe7,0xc2,0xe2,0xe2,0x36,0x6b,0x87,0xcb,0xbf,0x6e,
+  0x64,0x7b,0xa1,0x62,0x1e,0x0d,0x34,0xfe,0x8d,0x15,0x36,0x69,0xff,0x61,0xfe,0x05,
+  0xb1,0xf9,0xdc,0xb9,0xf3,0xec,0xb7,0x14,0xbc,0x27,0x04,0x75,0x9c,0x66,0xe8,0xbf,
+  0x17,0x22,0xa3,0x7e,0xf8,0xa1,0x3d,0xf9,0x77,0xfd,0xfa,0x0d,0x82,0x9e,0x9f,0x34,
+  0xfe,0xb5,0xb3,0xb3,0xaf,0xfa,0xf4,0x91,0xe5,0xfe,0x65,0xf6,0x67,0x19,0xbe,0x2b,
+  0x60,0x16,0xa5,0x65,0x66,0xec,0x0c,0x08,0x18,0x3c,0x78,0x30,0x2d,0x27,0x24,0x1f,
+  0x7a,0xba,0xfa,0xa8,0x2d,0x0b,0xb5,0x3f,0xeb,0xfc,0xa8,0xf3,0xe2,0x15,0x33,0x47,
+  0x1f,0x89,0x7d,0x21,0x21,0xa8,0xe8,0xbb,0x75,0xeb,0xd7,0x54,0x12,0x75,0x0d,0x75,
+  0xee,0xee,0xee,0x12,0xb3,0x12,0x09,0x03,0xfd,0x5e,0xa9,0xe9,0x42,0xea,0x96,0x36,
+  0x35,0x37,0x9f,0x3f,0x1f,0x09,0xbc,0x83,0xf6,0x60,0x69,0x69,0x95,0xc6,0x1a,0xfa,
+  0x24,0xba,0xff,0x95,0x20,0x1a,0x1a,0x1b,0xae,0x45,0x5f,0x9f,0x3b,0x6f,0x3e,0x2d,
+  0xed,0x21,0x3b,0xb8,0xe7,0xbf,0x7f,0xa0,0xfa,0xaf,0xb4,0xfe,0x57,0x0a,0x3d,0x14,
+  0xae,0xdf,0xa0,0xaa,0x72,0xb4,0xfa,0x83,0xbe,0xbe,0x1b,0x69,0xf1,0xb6,0xe2,0xd6,
+  0x1f,0x6c,0x69,0x75,0xb4,0x4b,0x78,0xf2,0xc4,0xcb,0xdb,0xcb,0xb8,0x8f,0xb1,0x64,
+  0x95,0x44,0x98,0xf6,0xe7,0xbf,0x5b,0x92,0x92,0x53,0xd0,0x93,0x6b,0x06,0xe0,0x5d,
+  0x68,0xf4,0xd4,0x70,0x74,0x9c,0x73,0xfb,0xf6,0x5d,0x32,0xf9,0x0c,0x3c,0xa3,0xb7,
+  0xcf,0x2a,0xf2,0x2a,0x50,0xd8,0x4f,0x45,0x44,0x48,0xb0,0x24,0x69,0xfe,0x57,0x67,
+  0xce,0xb1,0x45,0x3d,0xb7,0xfc,0xe3,0xfe,0x57,0xb0,0x6c,0x43,0x42,0xf7,0xb3,0xdf,
+  0x92,0x88,0xfe,0x57,0x37,0x6e,0xdd,0x56,0x50,0x40,0x84,0x70,0x89,0xb1,0x7b,0xcf,
+  0x1e,0xc1,0xb0,0x2f,0x1a,0xff,0xc2,0x42,0x7e,0x2f,0x50,0xf9,0x91,0x84,0x2c,0xff,
+  0x95,0x0c,0xdf,0x09,0xc5,0xa5,0x25,0x57,0xae,0x5d,0x75,0x72,0x9a,0xab,0xa3,0xa3,
+  0x2b,0x4a,0xf1,0x1d,0xd8,0x84,0x77,0x05,0x06,0xa2,0xb3,0x0e,0xe5,0x5f,0x79,0x39,
+  0xf9,0x98,0xd8,0x7b,0x42,0x6f,0x03,0xf6,0x2e,0x94,0x6b,0x0e,0x7d,0xcb,0x63,0xd3,
+  0xf8,0xa5,0x71,0x93,0xbf,0x1f,0x99,0x98,0x6e,0xd8,0xd0,0x61,0xfe,0xfe,0x5b,0x00,
+  0x7e,0xfe,0xfe,0x7e,0x7e,0xfe,0x5b,0xb6,0x6e,0x85,0x7f,0xb9,0xf0,0xf7,0xff,0xfa,
+  0xbd,0xdf,0x96,0xd5,0xab,0x7f,0x55,0x55,0x65,0xba,0x36,0x0d,0x1c,0x60,0x56,0x80,
+  0x55,0x24,0x67,0xa0,0xb6,0xbe,0x76,0xcf,0xde,0x10,0x65,0x45,0x24,0x43,0x17,0xdc,
+  0xb0,0xbd,0xc3,0x18,0xce,0x9b,0x7c,0xda,0xb5,0xa2,0xe7,0x7f,0x26,0x2f,0x84,0x25,
+  0xff,0x3c,0x27,0xf7,0x64,0x44,0xc4,0xca,0xd5,0xbf,0x4e,0x9e,0x3a,0x75,0xf8,0xf0,
+  0xe1,0x03,0x06,0x98,0xf5,0xe9,0x6d,0xdc,0xdb,0xb0,0xb7,0xbe,0x9e,0x01,0x0f,0x20,
+  0x08,0x91,0x09,0x43,0x68,0xe7,0xbf,0xd2,0xc7,0x1f,0xc1,0xf4,0x38,0x71,0xf2,0x24,
+  0xed,0x9e,0xd3,0x32,0x70,0xfe,0x5d,0xb2,0xd4,0xb9,0x9e,0x92,0x66,0x4d,0xf4,0xf3,
+  0xdf,0xb6,0x83,0xc3,0x35,0x17,0x73,0xf2,0x5f,0x5f,0xb9,0x76,0xcd,0x77,0xd3,0xe6,
+  0x99,0x33,0x7f,0xb1,0x1e,0x35,0xca,0x6c,0xa0,0xb9,0x71,0x1f,0x13,0x18,0x1c,0x03,
+  0x7d,0x03,0xfe,0xf8,0x90,0xd1,0xe2,0xbc,0xfb,0x69,0xfb,0x7e,0xeb,0x3c,0x3c,0xbd,
+  0xc9,0xe4,0xd2,0x7c,0xc8,0x75,0x95,0x03,0x76,0x1e,0x3b,0x6e,0x5c,0x70,0xf0,0xde,
+  0x94,0xb4,0xd4,0xea,0x9a,0x6a,0x5a,0x24,0x6f,0x60,0x50,0x30,0x79,0x39,0xcc,0xd8,
+  0xcd,0x7e,0x7e,0x12,0x2c,0xcc,0x8b,0x94,0xf3,0x5f,0x98,0xe2,0xa0,0x6b,0xb3,0x5c,
+  0xe8,0xb7,0x65,0x1b,0x79,0xd5,0xf7,0x3b,0xff,0x85,0xc9,0xec,0xed,0xb3,0x92,0xfd,
+  0x59,0x50,0xef,0x4a,0x32,0xfe,0xe8,0x49,0x52,0x12,0x19,0x7d,0xaf,0xa5,0xa5,0xed,
+  0xb3,0x72,0x15,0xac,0xe8,0xcd,0x9b,0xfd,0x5a,0x97,0x73,0x9b,0xd5,0x0d,0xeb,0xdd,
+  0xdf,0x9f,0xbb,0xe4,0xad,0xac,0x90,0x74,0x67,0x51,0x57,0xae,0x08,0xf6,0x4f,0xe3,
+  0x5f,0xc3,0x5e,0x86,0xe9,0x99,0x6c,0x82,0xf4,0xc7,0xea,0x6a,0x6d,0x2d,0xa6,0x63,
+  0x36,0xd7,0xfe,0xec,0xe3,0x23,0xcb,0x7f,0x25,0x83,0x64,0x68,0x68,0x6a,0x78,0x14,
+  0x17,0x37,0x7e,0xc2,0x44,0x65,0x15,0xe1,0x35,0x55,0xbf,0xed,0xed,0x5d,0xe6,0x2d,
+  0x58,0x58,0x5e,0x59,0x81,0x76,0x48,0xcb,0xff,0xbc,0x7d,0x57,0x00,0xbb,0x9d,0x16,
+  0x60,0x87,0xa5,0x4a,0x00,0x0a,0xb8,0x16,0xfd,0x35,0xd1,0x74,0x6b,0x2d,0xa1,0x13,
+  0xf2,0x84,0x6e,0xbe,0x70,0xe1,0xbf,0xd8,0x7b,0x6e,0x6e,0x69,0x79,0x95,0xc7,0x21,
+  0xcb,0x77,0xda,0xda,0xdb,0x55,0x54,0xb1,0x19,0x9d,0xf8,0x00,0x2a,0x5c,0xe1,0xe1,
+  0x81,0x46,0x24,0x75,0xe9,0xdc,0x75,0xa9,0x8b,0x6b,0xe5,0xc7,0x2a,0xfc,0xa7,0x29,
+  0xf5,0x8f,0x3a,0xd0,0xed,0xcf,0xe8,0xfd,0x7f,0xfa,0x5c,0x5d,0x54,0x52,0x94,0xc7,
+  0xc9,0x7f,0x96,0x93,0x9d,0xf5,0xec,0x69,0x72,0x6a,0x2a,0x10,0x01,0x20,0x31,0x39,
+  0xd9,0x0b,0x8b,0x3f,0x3a,0x72,0x14,0xb3,0x3f,0x8b,0xc3,0xbf,0x68,0xfd,0x41,0xd8,
+  0x69,0x7d,0xbf,0x1d,0x07,0x90,0x78,0x92,0x9c,0xac,0xab,0x83,0xd4,0x49,0x1f,0x33,
+  0x66,0x4c,0x45,0x15,0x3e,0x61,0x24,0xe3,0x5f,0xc6,0xe0,0xd4,0xd4,0xd5,0x16,0x97,
+  0x95,0xe6,0xbf,0x2e,0xc8,0xce,0xcd,0x81,0xc1,0x49,0xcd,0xe0,0x8e,0x0c,0x6f,0x88,
+  0x0e,0x84,0x1d,0x22,0x3b,0x77,0x5b,0xbe,0x42,0xb0,0x87,0xe2,0x92,0x32,0x0b,0x0b,
+  0x2b,0x74,0xde,0x02,0x75,0x5a,0x58,0x5a,0x05,0x04,0x05,0x43,0x6f,0x30,0xe7,0xc9,
+  0x7a,0xb2,0x0c,0x5c,0xbc,0x74,0x19,0x35,0x8c,0xdb,0x39,0x8c,0x69,0x64,0x65,0x4c,
+  0x14,0xb4,0xfc,0x57,0xb3,0x66,0xcd,0x66,0x37,0x96,0xae,0x5c,0x89,0xa8,0xe1,0xed,
+  0x93,0x7f,0x23,0x36,0x96,0xac,0x3f,0x08,0xb0,0x19,0x6d,0xcb,0xfe,0x80,0xbf,0xad,
+  0xdd,0x80,0x96,0x21,0x63,0xf0,0xef,0x2b,0x0e,0x07,0x84,0x4c,0x46,0x33,0x63,0x63,
+  0xd3,0x9c,0x17,0xb9,0x2c,0xd9,0x41,0xe1,0xbd,0xc0,0xff,0x2e,0x58,0xc8,0x0c,0xbe,
+  0x00,0x99,0xea,0x71,0x72,0x9b,0x32,0xdf,0x34,0xfe,0x55,0x52,0x54,0x8e,0xbc,0x78,
+  0x91,0xe5,0xfe,0x8b,0x4b,0xcb,0xc8,0xb2,0x71,0xb2,0xfc,0x57,0x32,0x48,0x06,0xe0,
+  0x85,0x97,0x1c,0x0e,0x28,0x02,0x62,0x79,0x1b,0x2a,0xf6,0x50,0xf4,0xdd,0xbc,0xb1,
+  0xbc,0x92,0x1a,0x7a,0x43,0xcb,0xbf,0x31,0xd2,0x7a,0xd4,0x87,0xe2,0x22,0x96,0xfb,
+  0x79,0x99,0x97,0xa7,0xa4,0xc8,0x2c,0x22,0xcf,0x5d,0xa1,0xaa,0x6a,0x82,0x46,0xb3,
+  0xe4,0xd4,0x34,0xe0,0x0b,0xe6,0xf2,0x34,0x31,0x41,0x53,0xb2,0x0b,0xe2,0x4e,0xcc,
+  0x3d,0x39,0x82,0x04,0x3d,0xbd,0x7d,0x84,0x4a,0x05,0x7c,0xc0,0x53,0xbb,0x2e,0x73,
+  0x43,0x35,0x74,0xd8,0x72,0x7f,0x5b,0xbb,0x0e,0xcd,0x3e,0x4d,0x3b,0xff,0xa5,0xf9,
+  0x5f,0x89,0x8b,0x86,0xa6,0xa6,0x95,0xab,0x57,0x33,0x3a,0x87,0x1d,0xf2,0xfc,0x85,
+  0x0b,0x64,0x63,0xe9,0xcf,0x7f,0x01,0xf6,0x63,0x1c,0x68,0xa3,0xfd,0xf0,0xe1,0x43,
+  0x54,0xdf,0x04,0xe5,0x31,0x25,0x2d,0x0d,0xbd,0xa4,0xa2,0xaa,0x12,0xad,0xa6,0x31,
+  0xc7,0x71,0x4e,0xb5,0xb0,0x6c,0xde,0xa2,0xe0,0x42,0x64,0x24,0xd9,0xf9,0xea,0x35,
+  0xbf,0x0a,0xb6,0x79,0x9e,0x93,0x8d,0x66,0x78,0x03,0x65,0x3f,0x78,0xcf,0x5e,0xa1,
+  0x49,0xc5,0x05,0xf1,0x2c,0x3b,0x5b,0x1b,0x2b,0x59,0x0b,0xab,0x2c,0x29,0x39,0x45,
+  0xdc,0x9b,0xa7,0xf9,0x3f,0x1b,0xc0,0x78,0xa6,0xa7,0xd2,0xae,0xaa,0xad,0xab,0x9f,
+  0x39,0x8b,0x99,0x42,0xaa,0x43,0x6b,0xa9,0xa6,0x67,0xd9,0xc8,0x94,0x93,0xfe,0xfc,
+  0x97,0xf7,0x80,0x59,0xac,0xf3,0xd9,0x71,0xae,0x13,0x79,0x95,0xa6,0x86,0xe6,0xf3,
+  0xec,0x36,0xd9,0x6c,0x40,0x8e,0xfd,0x85,0xc8,0x7f,0xa5,0xd0,0x43,0x21,0xea,0x92,
+  0x10,0x07,0xf2,0xaa,0x8f,0x55,0x16,0x16,0x96,0x8c,0x0b,0xb5,0xb4,0xb5,0x2b,0xaa,
+  0xda,0x08,0xc6,0x34,0xfe,0xed,0xd8,0xa1,0xe3,0xc2,0x45,0x6c,0x62,0x7c,0xfa,0xd3,
+  0x4c,0xf2,0x74,0xac,0x53,0xc7,0x4e,0xab,0x56,0xad,0x92,0xf1,0xaf,0x0c,0x62,0x01,
+  0xc8,0x37,0xf3,0x69,0xd6,0x98,0xb1,0xe3,0x45,0x77,0x35,0x94,0xeb,0x2a,0x67,0x65,
+  0x35,0x04,0xd4,0x4f,0xf6,0xed,0x88,0x96,0xff,0x59,0x45,0x59,0xf5,0x64,0xc4,0x29,
+  0x9a,0xd5,0xae,0xbe,0xb1,0x61,0x57,0x60,0x20,0xea,0xeb,0x65,0x61,0x39,0x44,0x30,
+  0xb1,0x33,0x90,0x20,0x99,0x07,0x18,0x36,0x84,0xfb,0x0f,0x1e,0xb2,0x24,0xf7,0x6b,
+  0x68,0x6a,0x5c,0x43,0xe4,0x41,0x02,0x26,0x8d,0xf8,0x96,0xd9,0x43,0x44,0x7c,0x28,
+  0x2a,0x1c,0x65,0x6d,0x83,0xb2,0x92,0x9a,0xaa,0xda,0x9e,0xbd,0xfb,0xc8,0x1c,0x5f,
+  0x34,0xfe,0x65,0xb1,0x3f,0xc3,0x83,0xd4,0x36,0x08,0x11,0x27,0xf8,0x00,0xfe,0x9a,
+  0x3a,0x6d,0x1a,0xa3,0x73,0x90,0x64,0xee,0xc5,0xc6,0x92,0x8d,0xdb,0x85,0x7f,0x35,
+  0x35,0xb5,0x92,0x52,0xf1,0xcd,0xff,0xf4,0x99,0x33,0xa8,0x07,0x7b,0xb7,0x6e,0xdd,
+  0xf6,0x86,0x86,0xa0,0x97,0x80,0xbe,0xa3,0xaf,0x6f,0x40,0x5e,0xe2,0xe2,0xba,0xac,
+  0x46,0xa0,0x44,0xaf,0x20,0xea,0x1a,0xea,0x44,0x94,0x9a,0x1a,0x9b,0x1a,0x37,0xfb,
+  0xf9,0x93,0x23,0x1f,0x14,0x1c,0x2c,0xd8,0x2c,0x2d,0x23,0x53,0x45,0x19,0xb1,0xff,
+  0x0c,0xb2,0xb0,0xac,0xa9,0x13,0x29,0x4d,0xba,0xe0,0xeb,0x80,0x65,0x85,0x2e,0x01,
+  0x67,0x17,0xd7,0xf2,0x4a,0x6a,0xaa,0x2e,0x14,0x34,0xfe,0x05,0xad,0x7c,0x93,0xbf,
+  0x3f,0x6d,0x10,0x0a,0xde,0xbc,0x1e,0x34,0x08,0x29,0xa4,0xc5,0x3d,0x6d,0xc1,0xc2,
+  0x00,0xa5,0xb7,0x3f,0xf3,0x00,0x43,0x5d,0xdf,0x80,0x33,0x51,0x75,0x4d,0x1d,0x9a,
+  0xdd,0xae,0xb7,0x51,0xef,0xd7,0x6f,0xda,0xdc,0x52,0x53,0xf3,0x97,0xc0,0xdd,0x4c,
+  0x1b,0x3e,0x37,0x81,0xc9,0x32,0x37,0x5a,0xe7,0x3c,0xfc,0x15,0x17,0xa7,0xae,0xd6,
+  0x93,0x71,0xe1,0xb8,0xf1,0x13,0x18,0xdb,0x02,0x8d,0x7f,0x01,0xda,0xda,0xda,0x9c,
+  0x7c,0x0e,0xda,0x39,0x74,0x72,0xf2,0xd4,0x29,0xf2,0x92,0xae,0x9d,0xbb,0x6e,0xdb,
+  0xbe,0x5d,0x02,0xcb,0x86,0x0c,0xff,0xcb,0x28,0x78,0xfd,0x86,0x0c,0x1a,0xa5,0x01,
+  0xe6,0x18,0x68,0x28,0x41,0x41,0xbb,0x5f,0xbf,0x7d,0xcb,0x62,0x02,0xe2,0x81,0xa5,
+  0xfe,0x60,0xbf,0x7e,0xfd,0x05,0x33,0x39,0x0b,0xe2,0x71,0xe2,0x13,0x13,0xd3,0xbe,
+  0xe4,0x25,0x40,0x91,0x6e,0x6e,0xee,0x0c,0x6d,0x6b,0xe3,0x66,0x7f,0x52,0x09,0x9d,
+  0x3a,0x75,0xda,0x87,0x42,0x6a,0x88,0x53,0x6a,0x5a,0x9a,0x29,0xd1,0xbf,0x9e,0xbe,
+  0x5e,0xae,0x08,0x5e,0x61,0x0c,0xa4,0x65,0x64,0x0c,0x1d,0x3a,0x1c,0x7d,0x40,0x65,
+  0x25,0xe5,0x1b,0xb7,0x6e,0x33,0x29,0xf8,0xef,0x96,0x63,0x98,0xfd,0x99,0xc5,0xff,
+  0x0a,0xb6,0x08,0xd8,0x82,0x92,0x92,0x93,0x18,0x85,0x9f,0x50,0x3c,0x49,0x4a,0x24,
+  0xf9,0x4b,0x5f,0xcf,0x00,0xad,0xda,0x20,0xbd,0xff,0x15,0xf7,0xce,0x3b,0x75,0x59,
+  0xbe,0x7c,0x05,0x49,0x8e,0xcd,0x2d,0x2d,0xf0,0xb2,0x68,0xde,0x62,0x66,0x66,0xe6,
+  0xa5,0xe5,0xcc,0x02,0x19,0x5f,0x5a,0x9a,0xcf,0x9d,0x3f,0x8f,0x3a,0xbd,0xaf,0xf7,
+  0xf5,0x45,0x1f,0x1f,0x86,0xf7,0xf8,0x89,0x93,0x57,0xaf,0x45,0x0b,0x16,0x59,0xa6,
+  0x01,0xf6,0x76,0xeb,0x91,0xcc,0xe4,0xd2,0xc0,0x68,0xc0,0x6b,0x82,0xcd,0xd2,0x33,
+  0x33,0x51,0xff,0x3a,0x6b,0x1b,0x5b,0x5a,0xda,0x31,0x1a,0x80,0x3e,0xf6,0xec,0x0b,
+  0x41,0x6b,0x67,0x83,0x64,0xb2,0x6b,0x77,0x90,0x28,0xef,0x94,0x0f,0x9a,0xff,0x55,
+  0x87,0x56,0x07,0xc8,0x84,0xc7,0x8f,0x51,0x99,0x33,0x3c,0x22,0x02,0x35,0x25,0xd9,
+  0xdb,0x3b,0xa0,0x56,0x6b,0xba,0xfe,0x8b,0xd6,0x5f,0x88,0xa5,0x09,0xed,0xba,0x3a,
+  0xba,0xf7,0xee,0xc7,0x92,0x97,0xc0,0x4d,0xde,0xbc,0x7d,0x1b,0xf5,0x94,0x1b,0x3e,
+  0x7c,0x04,0x29,0x93,0x3c,0xcb,0x7d,0x4e,0x5a,0xdd,0x35,0x7a,0x6a,0xdc,0x7f,0x10,
+  0x4b,0x93,0xb1,0x3f,0x55,0x7f,0x22,0x03,0xe7,0xe1,0x2d,0x90,0x8e,0xf7,0x2c,0xfc,
+  0x0b,0x58,0xe6,0xe6,0x5e,0x5e,0x81,0x1c,0x94,0x94,0x95,0x97,0x4d,0x9f,0x3e,0x83,
+  0x6c,0x4f,0x56,0x9f,0x94,0x41,0x06,0x76,0x80,0xd8,0xec,0xbe,0x7c,0x85,0x50,0xcd,
+  0x17,0x64,0x6c,0x3d,0x5d,0xbd,0x29,0x53,0xa7,0x9d,0x3b,0x7f,0x01,0xf8,0x5a,0xc4,
+  0x7d,0x63,0x3e,0xbd,0xfe,0x20,0x08,0xb1,0x76,0xf6,0x0e,0x8f,0xe2,0xe2,0x04,0xcd,
+  0x35,0x0d,0x4d,0x0d,0x4f,0x92,0x9e,0xd8,0x8c,0xb6,0x45,0xf7,0x6d,0x6e,0x5d,0x6f,
+  0x22,0x70,0xf2,0x49,0x52,0x92,0x91,0x21,0x33,0x25,0x88,0xdc,0x0f,0xf2,0x40,0x0a,
+  0xef,0x0b,0x0b,0x19,0x6b,0x01,0x1e,0xf6,0xcd,0xbb,0xb7,0xe3,0x27,0x4c,0x64,0x78,
+  0x6d,0xc1,0xcf,0x2d,0x59,0xb2,0x94,0x51,0x04,0x0a,0x14,0xab,0x92,0xb2,0x52,0x50,
+  0xb7,0xf9,0x60,0x7c,0xe4,0x21,0xf2,0x62,0x14,0xe9,0x09,0xc9,0xc3,0x80,0x7e,0x03,
+  0x92,0x92,0x93,0x05,0xfb,0xe4,0xe6,0xdf,0xc0,0xfc,0xaf,0x3a,0xd0,0xcf,0x7f,0x4b,
+  0xcb,0xcb,0x40,0x6e,0xd7,0xd3,0xd1,0xf3,0xf2,0xf2,0x4e,0x4a,0x4b,0xfa,0xf4,0xf9,
+  0x13,0xba,0xc0,0xe1,0xcb,0xfc,0xd7,0x05,0x20,0x78,0x90,0x43,0x37,0xda,0xd6,0xb6,
+  0xa8,0x04,0xb1,0xf6,0x4b,0xef,0x7f,0xc5,0x83,0x92,0x82,0x52,0x48,0x68,0xa8,0xe0,
+  0x91,0x37,0x0c,0x5d,0xec,0x83,0x58,0x35,0x55,0x75,0xda,0xdb,0x87,0x9b,0x74,0x75,
+  0x73,0xe3,0x14,0x14,0xf0,0x9f,0x05,0xa8,0xea,0x79,0x76,0xb6,0xf5,0xc8,0x51,0xa8,
+  0xdd,0x23,0x3c,0x1c,0x77,0x18,0x6e,0x68,0x6a,0xf4,0xf6,0xf1,0x51,0x53,0x51,0x9b,
+  0x3b,0x77,0xde,0x83,0x87,0x0f,0xca,0x2a,0xca,0x69,0xbb,0x5f,0x69,0x45,0xf9,0x9a,
+  0x75,0xbf,0xc9,0xcb,0x31,0x47,0xde,0xd0,0xd0,0x28,0xbd,0xad,0xcb,0x3a,0x08,0x96,
+  0x86,0x58,0x0d,0x0b,0x45,0x05,0xc5,0xf8,0xc4,0x44,0xb4,0x52,0x03,0xfc,0x28,0xa8,
+  0xc6,0x45,0x25,0xc5,0xe4,0xff,0xbe,0xe2,0xe4,0xa3,0x95,0x82,0xb9,0xf3,0x59,0x45,
+  0x75,0xe3,0xa6,0xcd,0xf9,0x05,0xf9,0x0d,0x4d,0x8d,0x8c,0xde,0x40,0x71,0x7e,0x99,
+  0xf7,0x8a,0x21,0xbc,0xd1,0xe2,0x8f,0x78,0xab,0x69,0x88,0xd5,0xd0,0xd8,0x07,0x0f,
+  0xf8,0xa5,0x1f,0x5a,0x5a,0x1d,0x14,0x33,0x9f,0x65,0x0e,0x1c,0x68,0x86,0x0e,0xa9,
+  0x87,0xa7,0x37,0xea,0xb5,0x25,0x76,0xfd,0x41,0x4a,0x70,0x3a,0xfc,0xa8,0xb9,0xd9,
+  0xa0,0x3b,0x31,0x31,0x82,0x46,0x83,0xc6,0xe6,0xc6,0x94,0xb4,0x54,0x34,0xc5,0x37,
+  0xb7,0x74,0x94,0x40,0xe9,0x0a,0xc1,0x35,0x3b,0x7d,0xc6,0x2c,0xc6,0xac,0x86,0xc6,
+  0x56,0x96,0x43,0xe2,0x1f,0x27,0x90,0x1b,0x11,0x2c,0x90,0x7d,0x21,0xa1,0x8a,0x3d,
+  0x14,0x19,0xfd,0x9b,0x98,0x98,0x64,0x64,0x31,0x5d,0xaa,0xd8,0xf9,0xb7,0x47,0xf7,
+  0x1e,0x9e,0xde,0x3e,0x6f,0xdf,0xbf,0x13,0x9c,0x54,0xd5,0x35,0xd5,0x3b,0x03,0x02,
+  0x50,0xc3,0x4e,0x4f,0xf5,0x9e,0x89,0x49,0x78,0x02,0x3d,0x19,0x64,0x40,0xf1,0xe2,
+  0xe5,0x4b,0x5a,0x34,0x0d,0x7f,0xab,0x34,0x36,0x36,0x5d,0xb3,0x76,0x43,0x7c,0x42,
+  0x02,0xcd,0xad,0x88,0x06,0x9a,0xfd,0x99,0xbf,0x88,0x4c,0xfa,0x98,0xac,0xdb,0xb0,
+  0xe1,0x56,0x4c,0x0c,0x28,0x1d,0x77,0x62,0xef,0xfa,0x6d,0xd9,0xd2,0xb7,0x6f,0x5f,
+  0x9a,0xd2,0x34,0x72,0xa4,0x35,0xe9,0xe8,0xf5,0xb9,0xb6,0x66,0xe5,0xaa,0x5f,0xc9,
+  0xc6,0x20,0xee,0x4e,0x9e,0x32,0x2d,0xfa,0xc6,0xcd,0x0f,0xc5,0xc5,0xf5,0x8d,0x0d,
+  0x75,0x0d,0xf5,0xa5,0xe5,0xe5,0x57,0xae,0x5e,0x03,0x2e,0xc3,0x1c,0x3f,0x54,0x6f,
+  0xdc,0xba,0xc5,0xd8,0xba,0x63,0xee,0xdd,0x1b,0x3f,0x7e,0xc2,0x68,0x1b,0x5b,0xd0,
+  0x14,0x78,0xff,0xda,0xda,0xda,0xf3,0xfe,0xb0,0xb7,0x73,0xb0,0xb3,0xb5,0x07,0xd8,
+  0xdb,0x8f,0x19,0x65,0x6d,0x03,0xfb,0x3f,0x7a,0xc3,0xad,0x89,0x1f,0xdb,0x54,0x1d,
+  0xa5,0xe5,0xbf,0xea,0x40,0xe7,0x5f,0xa0,0x78,0xf8,0x51,0xde,0x8b,0x30,0xec,0x65,
+  0xb8,0x68,0xd1,0xbf,0x80,0x8c,0x5e,0x71,0x38,0xb0,0x75,0xc0,0x73,0xf1,0x00,0x94,
+  0x11,0x79,0xf1,0xd2,0x98,0x31,0x63,0xd1,0x32,0xe5,0x6b,0xd7,0xad,0x43,0xcb,0x3a,
+  0xb7,0x17,0xff,0x76,0x68,0x3d,0x50,0x98,0x3f,0x7f,0xc1,0xa5,0xe8,0xab,0xa9,0x19,
+  0xe9,0x0f,0xe3,0xe2,0xfc,0xb7,0x6e,0x33,0x31,0x31,0x65,0x79,0xf5,0xbc,0x17,0x34,
+  0x76,0xec,0x38,0xd0,0x17,0x12,0x93,0x93,0x93,0x52,0x52,0xc2,0x0e,0xff,0x61,0x63,
+  0x33,0x1a,0xf5,0x3a,0x06,0xe1,0x90,0x16,0xd5,0x05,0xaf,0x75,0x85,0x87,0x27,0x6f,
+  0x2e,0x69,0x69,0x68,0x81,0x56,0xb2,0x3f,0xec,0x50,0xd6,0xb3,0x67,0x30,0x51,0xe1,
+  0x91,0x81,0xd7,0x60,0x70,0x3e,0x94,0x7c,0xb8,0xff,0xe0,0xe1,0xbc,0xf9,0x0b,0x15,
+  0x7a,0x20,0x7b,0xe6,0xc4,0x89,0x13,0xcb,0xda,0xa6,0xef,0xfe,0x58,0xfd,0x91,0x5b,
+  0x64,0x13,0xe3,0xac,0xa1,0x43,0x86,0x9d,0x3e,0x73,0xa6,0xa4,0xb4,0x04,0x7e,0x17,
+  0x7a,0xae,0xad,0xaf,0x83,0x09,0xf9,0x2c,0xfb,0xf9,0xb1,0x53,0xa7,0x5c,0x5c,0x5d,
+  0x5d,0x97,0x2d,0x2b,0xad,0x28,0x65,0xdc,0x61,0x73,0x4b,0xf3,0xf6,0x1d,0x3b,0x48,
+  0x67,0x03,0x1e,0x60,0x26,0x80,0xd2,0xe7,0xbf,0x75,0xeb,0xdd,0x98,0x98,0xcc,0xa7,
+  0x4f,0xe1,0x31,0x6f,0xdd,0x8d,0x09,0x3d,0x70,0x70,0xfa,0x8c,0x99,0x13,0x26,0x4e,
+  0x2a,0x6d,0x5b,0x4b,0x82,0x85,0x7f,0x79,0x30,0xec,0x65,0xe4,0xe9,0xe5,0x7d,0xfd,
+  0xe6,0x4d,0x58,0x4d,0x8f,0x12,0x12,0x02,0x02,0x83,0x2c,0x29,0x8e,0x64,0xa0,0x7e,
+  0x5e,0xb8,0x88,0xb8,0x04,0xb4,0x88,0x5b,0x7f,0x90,0xe2,0x7f,0xc5,0x5f,0xe0,0xa0,
+  0x05,0xfb,0xac,0x5c,0x75,0xf9,0x6a,0x74,0x7a,0x56,0x56,0xfc,0xe3,0xc7,0x7b,0x43,
+  0x43,0x06,0x0f,0xfe,0x09,0xcd,0x24,0x06,0xca,0xe3,0xd1,0x63,0xc7,0xbe,0x60,0x81,
+  0x69,0xd1,0x37,0x6f,0x69,0x68,0x68,0x92,0x97,0xf4,0xef,0xdf,0x7f,0xd7,0xee,0xa0,
+  0xbc,0xfc,0xfc,0x9a,0xba,0x3a,0x78,0x1d,0xb0,0x15,0xc0,0x18,0xae,0x58,0xe1,0xa1,
+  0xae,0x86,0x08,0x7e,0xcb,0x3d,0xbd,0xeb,0xea,0x99,0x26,0x6b,0x76,0xfe,0xe5,0xcd,
+  0x52,0x3b,0x3b,0xfb,0xfd,0x07,0x0f,0x3e,0x8a,0x8f,0x87,0x51,0xbd,0x16,0x1d,0xed,
+  0xe2,0xe2,0x4a,0xdb,0x30,0xad,0x86,0x0c,0xa9,0x10,0xf3,0x4c,0x41,0x86,0xff,0x65,
+  0x80,0x80,0xbd,0x63,0xe7,0x4e,0xda,0xdc,0x6b,0x35,0x35,0x5b,0x46,0x9c,0x39,0x2b,
+  0x98,0xd5,0x47,0x2c,0xa0,0xf6,0x67,0xd8,0x4e,0xc9,0xcd,0x8d,0x25,0xdc,0x83,0x07,
+  0x98,0xf3,0x17,0x29,0x4e,0x17,0x85,0xc5,0x45,0xe6,0xe6,0x16,0xe8,0x86,0x09,0x94,
+  0x01,0x8b,0x71,0xd0,0xa0,0xc1,0x66,0x66,0xe6,0x9a,0x9a,0x5a,0x78,0x9b,0x4e,0x9d,
+  0x61,0xcd,0x92,0x0c,0x75,0xfc,0x64,0xb8,0x94,0xb9,0x77,0x80,0x31,0x0f,0x10,0xb9,
+  0x16,0x8f,0x1c,0x3d,0x4a,0x6e,0x59,0x68,0xfe,0x49,0x1e,0x40,0x8b,0x1f,0x31,0x9c,
+  0x69,0x35,0x95,0x97,0xef,0xa6,0xa3,0xab,0x37,0xd0,0xcc,0x7c,0xf0,0x4f,0x16,0x7d,
+  0xfa,0x18,0xc3,0xe0,0xd0,0xd2,0x34,0xa9,0x28,0xab,0x64,0xe7,0xe4,0xa0,0x3d,0x4b,
+  0x7f,0xfe,0xdb,0xa5,0x73,0x17,0x86,0x30,0xc3,0xfe,0x1e,0x79,0x99,0x21,0x99,0x25,
+  0x33,0x3a,0x74,0x64,0x0f,0x6a,0x1e,0x3e,0xe2,0xe7,0x3a,0xca,0x61,0x1f,0xe8,0x56,
+  0x8b,0x9d,0x99,0x29,0x25,0x61,0x78,0xb5,0x34,0xb5,0xfa,0x0f,0x18,0x08,0x5b,0xbd,
+  0x89,0x69,0x5f,0x98,0x00,0x34,0xc9,0x01,0xee,0x24,0x32,0xea,0x12,0x69,0x24,0x39,
+  0x7d,0xf6,0x1c,0x68,0xbb,0xb4,0x47,0x00,0x35,0x07,0x94,0xca,0x9f,0x2c,0x2c,0x8d,
+  0x4d,0x4c,0x35,0x34,0xb5,0xf8,0xa6,0xd4,0x9f,0x2c,0xac,0xd0,0x13,0xd5,0xd2,0xb2,
+  0x52,0x47,0xc7,0x39,0x42,0x67,0x0b,0x63,0xe8,0x74,0x7e,0xd4,0xc9,0xcb,0xcf,0x13,
+  0xec,0x87,0x76,0xfe,0x4b,0x8e,0x9e,0xd0,0xd5,0x64,0x69,0x39,0xe4,0x43,0x21,0xee,
+  0x00,0xd9,0x2e,0xf1,0x47,0x12,0x2c,0xf0,0x01,0x03,0x06,0xbe,0x7d,0xff,0x1e,0xbd,
+  0xa5,0xfa,0xc6,0x7a,0xdf,0x4d,0x7e,0xb4,0x1e,0x14,0x15,0x95,0x60,0x09,0x0c,0x1a,
+  0xfc,0x93,0x41,0xaf,0x5e,0xb4,0x64,0x1d,0xfd,0xfb,0x0f,0xcc,0x79,0xf1,0x82,0xec,
+  0x19,0xf8,0x77,0xc2,0xa4,0x89,0xa2,0x0c,0xa9,0xd0,0x47,0x80,0xdd,0x72,0x57,0x40,
+  0x60,0xfb,0xee,0xcf,0x32,0xfc,0xff,0x06,0xa8,0x09,0x33,0x67,0x20,0xbe,0x91,0xbc,
+  0xe9,0xe4,0xbc,0xcc,0xed,0x79,0x4e,0x8e,0x34,0xc7,0x19,0x64,0xfd,0x85,0x4e,0x1d,
+  0x3b,0xdb,0x3b,0x38,0x18,0x60,0x3e,0x36,0x6c,0x5b,0x53,0xc7,0xce,0x5e,0xde,0x3e,
+  0x95,0x55,0x54,0xed,0xfb,0x4a,0x74,0x34,0x08,0xff,0x12,0xe4,0x82,0x86,0x4b,0x46,
+  0x8d,0xb2,0x79,0x8e,0x31,0x54,0x78,0x44,0x84,0x28,0xe1,0xcf,0x2c,0x00,0x39,0x9f,
+  0x91,0xf8,0x11,0x06,0xf3,0x8f,0xa3,0x47,0x45,0xcc,0xff,0xcc,0xc3,0x9b,0xf7,0xef,
+  0xac,0xac,0x86,0x49,0x76,0x03,0x20,0xbd,0xaf,0xf0,0xf0,0xa2,0x79,0xe6,0x48,0xcf,
+  0xbf,0xc3,0x46,0x8c,0x30,0x37,0x33,0x17,0x7d,0xd8,0x55,0x95,0x55,0x41,0xb9,0xb3,
+  0xb6,0xb6,0x11,0x3d,0x8b,0x48,0x37,0xf9,0xee,0xbb,0x83,0xf7,0xd0,0xde,0x7b,0x75,
+  0xcd,0xe7,0x79,0x0b,0x24,0xcc,0x81,0x06,0xf7,0x60,0x67,0x3f,0x06,0x3d,0x03,0x2d,
+  0xab,0x28,0x9f,0x32,0x05,0xb1,0xe4,0xb3,0xc3,0xd4,0xd8,0x34,0xf7,0x25,0xb2,0xc9,
+  0xc3,0x4b,0x7f,0x9e,0xf3,0x62,0xe0,0x40,0x73,0xb1,0x3a,0x54,0x53,0x51,0x7b,0xd2,
+  0xd6,0x98,0x49,0xe3,0xdf,0xb1,0x63,0xc7,0xf5,0xe8,0x2e,0x46,0x12,0x4e,0xe8,0x24,
+  0x34,0x74,0x3f,0xed,0x08,0x49,0x7a,0xff,0x67,0x3d,0x3d,0xfd,0x61,0xc3,0x86,0x8b,
+  0xb5,0x18,0x41,0x64,0xfa,0x7d,0xe7,0x2e,0x16,0x3f,0xba,0x77,0x1f,0xde,0x4f,0x9e,
+  0x32,0x55,0xb2,0x2c,0x67,0xea,0xaa,0xea,0xa7,0xc2,0xc3,0xd1,0xe7,0xe5,0xf2,0xef,
+  0x44,0x84,0x7f,0x1d,0xc6,0x8e,0x23,0xdd,0xb7,0xd8,0x31,0x64,0xc8,0xd0,0xec,0x5c,
+  0x5c,0xd0,0x95,0x41,0x06,0x14,0x6f,0xde,0xbd,0x45,0xa3,0xd4,0x61,0xa3,0x98,0x34,
+  0x69,0x72,0x51,0x49,0xb1,0x94,0xfd,0x93,0xf1,0x47,0x20,0x43,0xae,0x5d,0xbf,0xfe,
+  0xc8,0xb1,0xa3,0x5a,0x58,0x64,0x0a,0x0a,0x90,0x04,0x26,0x4c,0x9c,0xc4,0x52,0xd7,
+  0xb5,0xa5,0x55,0x91,0xbf,0x7c,0xf9,0x0a,0x37,0x5b,0xaf,0x38,0xab,0x1e,0x1e,0xd3,
+  0xdc,0x7c,0x50,0x46,0x66,0x26,0x2a,0x63,0x9c,0x3c,0x19,0x2e,0x4d,0x56,0x43,0x5e,
+  0xff,0x61,0x87,0xdb,0xe8,0xbf,0x34,0xfe,0x65,0xf1,0xbf,0xe2,0xbc,0xce,0x37,0x37,
+  0x47,0xfc,0x57,0x85,0xff,0x7a,0xc7,0x4e,0x33,0xa6,0xcf,0x78,0xf7,0x9e,0x9a,0xc6,
+  0x47,0x7a,0xff,0xab,0xa5,0xae,0xce,0xd1,0x37,0x6e,0x18,0x19,0xf5,0x16,0x65,0xd8,
+  0xe1,0x3d,0xba,0x2f,0xf7,0xa8,0xad,0xaf,0x7d,0x14,0x17,0x07,0x64,0x24,0xe2,0x53,
+  0x4c,0x9a,0x34,0xe5,0x43,0x11,0x35,0x54,0x0d,0xf6,0x4f,0x51,0x54,0x4b,0x14,0xa0,
+  0x03,0x26,0xa5,0x50,0x83,0x80,0xd2,0x33,0xb3,0x46,0xdb,0x8c,0x16,0xab,0x43,0x5d,
+  0x5d,0xfd,0x74,0x7a,0xf6,0xb3,0xa4,0xe4,0x34,0x5b,0x3b,0x7b,0xa1,0x45,0x1c,0xf8,
+  0x50,0xec,0xa1,0x78,0xfd,0x66,0x9b,0x34,0x95,0x34,0xff,0xab,0xcb,0x57,0xa3,0x57,
+  0x78,0x7a,0x88,0x68,0xab,0x81,0x97,0xe8,0xe8,0x34,0xa7,0xea,0x13,0x55,0x94,0x95,
+  0x5e,0xff,0x1d,0x3e,0x7c,0xc4,0x9f,0x71,0xf1,0x5c,0x3b,0xb3,0xc8,0xf2,0x86,0xe3,
+  0x1c,0x27,0x96,0xb7,0xcc,0x43,0x5e,0x1e,0x07,0x26,0x83,0xb8,0xb9,0xd0,0x35,0x7a,
+  0x6a,0x04,0xef,0xd9,0x4b,0x13,0x36,0x60,0xfe,0x8c,0x9f,0x80,0xf0,0xef,0xe1,0xa3,
+  0x47,0x82,0x82,0xf7,0xca,0xcb,0xe3,0xa7,0x06,0x24,0x94,0x14,0x94,0xaf,0x5f,0xbf,
+  0x2e,0x7a,0xf4,0xa2,0x0c,0x32,0x00,0xf2,0xf2,0x39,0x66,0xd8,0x4e,0xd8,0x5d,0xbe,
+  0xfb,0xa9,0x88,0x08,0xf4,0x2c,0x46,0x2c,0x90,0xfa,0x2f,0xf0,0xef,0xfa,0x8d,0xbe,
+  0x30,0xed,0x23,0xa3,0x2e,0x19,0x1b,0x9b,0xb0,0x13,0x1c,0xec,0xea,0x6a,0xaa,0x6a,
+  0xde,0x2b,0x57,0xa1,0x66,0x3d,0x06,0x60,0x89,0xfd,0x95,0x90,0x30,0x6e,0xfc,0x04,
+  0xd4,0x35,0x82,0xec,0x59,0x45,0x59,0x65,0xd1,0xa2,0xc5,0x59,0x59,0xcf,0x68,0x0a,
+  0xfe,0xa9,0x70,0x69,0xf5,0x5f,0x6e,0xe2,0xa9,0x43,0xcc,0xc4,0x53,0x47,0x8f,0x9d,
+  0x40,0x4f,0x03,0x69,0xfc,0x5b,0x52,0x56,0xba,0xdc,0xc3,0x43,0x5b,0xeb,0x47,0xd1,
+  0x77,0x9e,0x56,0x33,0xaf,0xba,0x9b,0xbb,0xfb,0x1b,0xd6,0x71,0x13,0x2f,0xff,0xc6,
+  0xb1,0xe3,0xe4,0xe1,0xf2,0xd2,0x65,0xce,0x9f,0x3e,0x57,0x3f,0x78,0xf8,0xa7,0xf5,
+  0x28,0x1b,0xd4,0xcb,0x97,0x0f,0x79,0xb9,0x6e,0xae,0xcb,0xdc,0xdf,0xb6,0x0a,0x03,
+  0x4d,0xcd,0x5f,0x12,0x53,0x52,0x7e,0x1e,0xf1,0x33,0x7b,0x5e,0x53,0xf8,0x39,0x9b,
+  0x51,0xa3,0x69,0xd2,0x11,0x0f,0xc0,0xe6,0xbb,0x02,0x83,0x7a,0x19,0xf4,0x82,0x21,
+  0x15,0x5d,0xf4,0x52,0xe8,0xa1,0x38,0x71,0xf2,0x94,0xe4,0xd4,0x74,0x96,0x0d,0x13,
+  0x7e,0x34,0x2f,0xbf,0xc0,0xc9,0x69,0x1e,0xe8,0x41,0x22,0xf6,0x0c,0x1a,0xeb,0x43,
+  0xcc,0x49,0x58,0xa0,0xc3,0x7c,0x9f,0x95,0xab,0x75,0x7e,0xd4,0x15,0x85,0x85,0x61,
+  0xc4,0x8e,0x1d,0x3b,0x2e,0xf8,0xec,0x91,0x51,0x17,0x51,0xfe,0xfd,0x33,0xfe,0x51,
+  0x79,0x55,0xf9,0xd6,0xed,0xbf,0xeb,0xea,0xe8,0xb1,0x53,0x1e,0x08,0x7e,0x8b,0x16,
+  0x2f,0x79,0xc5,0xa1,0xe6,0x67,0x6b,0x11,0x5f,0xff,0x25,0x3d,0x99,0x87,0x0e,0x1d,
+  0x56,0x58,0x5c,0x94,0x9e,0x91,0xe5,0x38,0x67,0xae,0xd0,0xea,0x18,0xdd,0xe4,0xbb,
+  0x4f,0x9e,0x32,0xad,0x35,0x98,0x42,0xf8,0x6e,0x03,0x5a,0xb0,0xef,0x26,0x3f,0x0d,
+  0x0d,0x4d,0x51,0x98,0x5d,0x5e,0x4e,0x1e,0x64,0x80,0x2b,0x57,0xaf,0xd1,0x22,0xd7,
+  0x5a,0xe8,0xe7,0xbf,0xa7,0xcf,0x9e,0xa9,0x6b,0xa8,0xdf,0x17,0xb2,0xdf,0xd4,0xd8,
+  0x94,0xfd,0x65,0xc1,0xdc,0x30,0x32,0xea,0x73,0x30,0xec,0x90,0x58,0xae,0xec,0x32,
+  0xc8,0xd0,0xd2,0xca,0xbf,0xa8,0x26,0x02,0xe2,0xdc,0x9d,0x98,0x18,0xe9,0xfb,0x77,
+  0x71,0x73,0x57,0x52,0x52,0x16,0x84,0xaa,0xaa,0xda,0x96,0x6d,0xdb,0x60,0xae,0x36,
+  0xb7,0xb4,0xc4,0x3f,0x7e,0xbc,0x78,0xf1,0x92,0xff,0x63,0xef,0x3c,0xa0,0xa2,0x3a,
+  0xba,0x07,0x7e,0xce,0x5f,0x41,0x84,0x28,0x20,0xbb,0x2c,0x65,0x17,0x0b,0x6f,0x05,
+  0x2c,0x08,0x28,0x0a,0x24,0x46,0xc5,0x5e,0x40,0x50,0x54,0x96,0x2a,0xbd,0xaa,0x08,
+  0x46,0x45,0xfd,0x54,0x94,0x58,0x62,0x12,0x03,0x6a,0xa2,0x11,0x6b,0xc4,0x12,0x5b,
+  0x34,0xc6,0x12,0xfb,0x17,0x35,0x08,0x96,0x88,0x62,0x49,0xfc,0x8c,0x05,0x6c,0xa0,
+  0x91,0x26,0xb8,0xe8,0x39,0xff,0x3b,0xf3,0x76,0x97,0xc7,0x16,0x14,0x05,0x57,0xc8,
+  0xdd,0xf3,0x3b,0x73,0x66,0xee,0xdc,0x99,0xb9,0x33,0xaf,0xdc,0x37,0x6f,0xdf,0x9b,
+  0x07,0x12,0xb5,0xe7,0x37,0x63,0x23,0xe3,0x01,0x03,0x07,0x6f,0xdb,0xb6,0xbd,0xf6,
+  0x0f,0x91,0x28,0x01,0x47,0xe8,0xca,0x55,0x19,0xbd,0x7a,0xb9,0x68,0x7a,0xe2,0xa5,
+  0x39,0x5d,0xc4,0x63,0xb8,0xc7,0xf0,0xad,0xdb,0xb6,0x16,0x69,0xbe,0xa1,0x0d,0x64,
+  0x6e,0xd9,0x66,0x66,0x66,0xae,0x64,0x7f,0x9d,0x80,0x86,0xd6,0xac,0x5d,0xa7,0x54,
+  0xed,0xc6,0x4d,0x9b,0xe0,0x04,0xa2,0xaa,0x99,0x77,0x4d,0xc3,0x7a,0x05,0xaf,0x5e,
+  0x3e,0x2b,0x2e,0x3e,0x7e,0xf2,0x64,0x4a,0x4a,0xaa,0xbb,0x7b,0x7f,0x70,0xac,0xb5,
+  0x9c,0x7c,0x74,0x9a,0x93,0x2b,0x16,0x2f,0x6f,0x9f,0x6d,0xdb,0xb7,0xbf,0x76,0xc1,
+  0xa8,0x3a,0xf9,0xdf,0x4d,0x99,0x99,0xa6,0xa6,0x02,0x25,0xb3,0x27,0x4d,0x49,0x2c,
+  0xab,0x28,0xaf,0x7a,0xf5,0xf2,0xea,0xf5,0x1b,0x33,0x67,0xce,0xb1,0x30,0x17,0xaa,
+  0xfd,0x1b,0xda,0xce,0xb6,0xf3,0xfc,0xd4,0x85,0x45,0x35,0x3f,0x91,0xfc,0xe7,0xcd,
+  0xbf,0x52,0xe6,0x7d,0xde,0xb1,0xa3,0x8d,0xda,0xee,0xc0,0x80,0x84,0x47,0x44,0x5e,
+  0xbd,0x7e,0xed,0xb5,0x17,0x81,0x70,0x9e,0xcc,0xb9,0x70,0x6e,0x69,0x5a,0xba,0x87,
+  0xa7,0x57,0xdb,0xb6,0xed,0xd4,0x3e,0x81,0xa6,0x18,0x1c,0xc3,0xd6,0x86,0x9f,0x7e,
+  0xda,0x77,0xf9,0x8a,0x95,0xf9,0x0f,0xee,0xbf,0xc9,0x09,0xbf,0xb0,0xa8,0x68,0xeb,
+  0x8f,0xdb,0x87,0x0f,0xf7,0x84,0xab,0xb5,0x5a,0x86,0x1d,0x86,0x11,0x14,0xfa,0xf7,
+  0x1f,0x90,0x55,0xf3,0x71,0x77,0x55,0x4a,0xcb,0x4b,0x0f,0x1e,0x3a,0x18,0x1a,0x1a,
+  0x2e,0x30,0x35,0xaf,0xe5,0xcb,0x4a,0xd0,0x96,0xa5,0xa5,0x70,0xdd,0xba,0xf5,0xdc,
+  0x2b,0x04,0xd8,0xa6,0xea,0xfd,0xef,0xe9,0x13,0xec,0x38,0xec,0x3f,0x70,0xc0,0xd7,
+  0x57,0xa2,0x69,0x09,0x9d,0x4e,0x9d,0x3a,0xc3,0x80,0x3f,0x7e,0xdd,0x03,0x42,0xd0,
+  0x8a,0xea,0x9e,0x6c,0x63,0x63,0xfb,0xdb,0xe9,0x53,0xaa,0xca,0x27,0x4e,0x9e,0x50,
+  0x3d,0x46,0x06,0x0e,0x1c,0xf4,0x88,0x3e,0x31,0x72,0xff,0xe1,0xc3,0xf4,0xe5,0xcb,
+  0xbb,0xf7,0x70,0x56,0xbb,0x52,0x1c,0xf4,0xd1,0x9a,0x11,0x2f,0x5c,0xbc,0xf0,0xf6,
+  0x5d,0xf5,0x7f,0xfb,0x6a,0xda,0xdc,0xfb,0x0e,0xee,0xf7,0x0f,0x08,0x34,0x13,0x68,
+  0xbc,0x2e,0xd2,0x6f,0xa9,0xef,0xe8,0xe0,0x98,0xfa,0xf9,0x82,0xbc,0x6b,0xd7,0x6a,
+  0xaf,0xad,0xb8,0xb4,0x64,0xec,0xd8,0x71,0xaa,0xfd,0xdd,0x46,0x17,0xbf,0xaa,0x78,
+  0x51,0xf9,0xdb,0xe9,0xd3,0xc1,0xc1,0xa1,0x7c,0x53,0xe5,0xa5,0xae,0x58,0x60,0x77,
+  0x1a,0x36,0xdc,0xf3,0xc8,0xb1,0x63,0xb8,0xe6,0x06,0xf2,0x16,0xdc,0xbe,0x7b,0xbb,
+  0x67,0x4f,0x35,0x4f,0x48,0xc2,0xfc,0x37,0x73,0xf3,0xe6,0x77,0x7f,0x91,0x0d,0x1c,
+  0xdc,0xdd,0xfc,0xfc,0x3b,0xf7,0xee,0x01,0x77,0xf3,0xef,0xd3,0x30,0xff,0x59,0x71,
+  0x89,0xe2,0x73,0x33,0x70,0x7a,0xb9,0x79,0xeb,0xd6,0x0f,0x99,0x5b,0xa6,0x27,0xcf,
+  0x0c,0x0e,0x0d,0x19,0x37,0xce,0x17,0xae,0xcf,0xa7,0x4d,0x9b,0xbe,0x72,0xe5,0xaa,
+  0xcb,0x79,0x79,0x6a,0x9f,0xda,0x7d,0x13,0xe0,0x20,0xbd,0x98,0x9b,0x9b,0xb1,0x76,
+  0xcd,0xd4,0xa9,0xd3,0x43,0xc3,0xc3,0xe1,0xa4,0x14,0x18,0x14,0x1c,0x1d,0x1b,0x97,
+  0x9a,0xba,0x60,0xfb,0xf6,0x1d,0x7f,0xdf,0xb9,0x5b,0x29,0x7d,0xfd,0x9d,0xa2,0x92,
+  0xb2,0xb2,0xbb,0xf9,0x05,0xac,0xf1,0x6f,0x07,0x74,0xb9,0xa4,0x4c,0x79,0xc5,0x06,
+  0x38,0xe4,0xef,0x15,0x3c,0xe0,0x0c,0x08,0x84,0x64,0x88,0xa4,0x55,0xaf,0xef,0x17,
+  0xcc,0x1c,0xc1,0xa4,0xe3,0x27,0x4e,0x7e,0xb7,0x72,0x55,0xf2,0x8c,0x59,0x61,0x11,
+  0x11,0x12,0x89,0xbf,0xaf,0x44,0x32,0x3e,0x34,0x74,0x62,0x42,0xc2,0x92,0x2f,0xbf,
+  0xda,0xf7,0xcb,0x2f,0x37,0xff,0x7e,0xfd,0x12,0xd6,0x2c,0x75,0xfa,0xff,0x57,0xed,
+  0x68,0x3c,0x7d,0x56,0xc3,0xc5,0xdf,0xbb,0x5f,0xb0,0x63,0xe7,0xee,0xe9,0xc9,0xb3,
+  0x82,0x43,0x42,0x24,0x7e,0xfe,0x11,0x51,0x51,0x73,0x53,0x52,0x7e,0xd9,0xbf,0x5f,
+  0xd3,0xf2,0xa4,0xb0,0x1b,0x14,0x15,0x3d,0xd9,0x7f,0xe0,0xd0,0xfc,0xd4,0xcf,0x23,
+  0x22,0xa3,0xfd,0xfd,0xfd,0x83,0x82,0xc7,0x7f,0xf6,0xd9,0x54,0x98,0x6b,0xdf,0xba,
+  0xfd,0xb7,0xda,0x37,0x7d,0x6a,0x01,0xc6,0xef,0xe1,0xe3,0xc7,0x59,0xd9,0xe7,0xd7,
+  0xae,0xdb,0x30,0x37,0x65,0x7e,0x64,0x4c,0x74,0x60,0x50,0xd0,0xb8,0x71,0xe3,0x82,
+  0x43,0x42,0x63,0xe3,0xe2,0xa1,0x89,0x1f,0x77,0xec,0xbc,0x92,0x97,0xf7,0x16,0xcb,
+  0x23,0x80,0x25,0x30,0x17,0xde,0xb1,0x6b,0x77,0x4a,0xca,0xbc,0x98,0xd8,0xb8,0x80,
+  0xc0,0x40,0xd8,0x51,0xa1,0x8f,0x13,0x26,0x26,0xcc,0x99,0x9b,0xb2,0x6e,0xc3,0xc6,
+  0x53,0xbf,0x9f,0xbe,0x9b,0xff,0xa0,0x4e,0x35,0xdf,0xbb,0x9f,0xbf,0xff,0xd0,0xa1,
+  0x85,0x8b,0x16,0x47,0xc7,0xc6,0x83,0x9d,0x12,0x89,0x24,0x28,0x98,0xec,0xa2,0x33,
+  0x66,0xcc,0x5c,0xbe,0x7c,0xc5,0xb1,0xe3,0xc7,0x61,0x27,0x51,0x1a,0x01,0x4d,0xcf,
+  0x3f,0x9f,0xe4,0x7c,0x82,0x0a,0xf6,0xa2,0xab,0xd7,0xaf,0xaf,0xdb,0xb0,0xe9,0xb3,
+  0xa9,0xd3,0xc9,0x56,0x90,0x48,0x60,0x2b,0xa4,0xcc,0x9b,0x5f,0xdb,0x56,0x50,0xde,
+  0xd0,0xa5,0xec,0x9e,0xa9,0xd8,0x45,0x81,0x82,0x07,0x8f,0xd4,0xba,0x18,0x38,0xd0,
+  0x38,0xca,0x05,0xec,0xc1,0xfe,0xa8,0xb0,0x90,0x7b,0xd9,0x50,0x5c,0x5a,0x9c,0x75,
+  0x36,0x7b,0xe9,0xd2,0xf4,0xc9,0x89,0x49,0x70,0x18,0xfa,0xf9,0xf9,0x85,0x85,0x87,
+  0xcf,0x4d,0x99,0xb7,0xe7,0xe7,0x5f,0x6a,0x79,0x5f,0xac,0x76,0xe0,0xaa,0x0c,0xae,
+  0xb4,0x77,0xee,0xde,0x33,0x3f,0x75,0x41,0x74,0x4c,0x8c,0x9f,0x7f,0x80,0x9f,0x9f,
+  0x7f,0x68,0x78,0x04,0x9c,0x46,0x56,0x67,0xac,0x3d,0x9b,0x93,0xf3,0xda,0x15,0xf0,
+  0x14,0x3c,0x2a,0x2c,0xaa,0xfd,0xb0,0x85,0xfd,0xea,0xf6,0x9d,0xbb,0xbb,0x76,0xef,
+  0x9e,0x39,0x6b,0x76,0x58,0x44,0xa4,0x9f,0x3f,0x38,0xff,0xa0,0xb8,0x09,0xf1,0x2b,
+  0x57,0xad,0xba,0xf0,0xc7,0xa5,0xb7,0x3e,0x47,0x21,0x48,0xe1,0x93,0xc2,0x11,0x1e,
+  0x1e,0x6a,0xaf,0xe7,0xe3,0xe2,0xe3,0xeb,0xba,0xda,0xcf,0xbb,0x00,0x97,0x9a,0xb0,
+  0xcf,0x3f,0x2b,0x29,0x86,0x10,0xe2,0xf5,0xf3,0x0e,0xfb,0x2b,0x45,0xb5,0xcf,0xc0,
+  0xeb,0xc1,0x21,0x09,0x27,0xb4,0xa6,0xf1,0x76,0x3c,0xf4,0xa2,0x52,0xca,0x76,0xad,
+  0x04,0xce,0x6f,0x10,0x81,0x33,0x61,0x5d,0xbb,0x56,0x27,0xff,0xfb,0xe6,0x80,0x61,
+  0x30,0xda,0xb0,0x29,0x4b,0xcb,0xcb,0x54,0x57,0x00,0x53,0x0b,0x9c,0xae,0x4b,0xcb,
+  0xcb,0xd9,0xad,0xff,0xbc,0xb2,0xe2,0x5d,0xb7,0xd1,0x2b,0xf2,0x51,0x24,0xd8,0xdc,
+  0xd4,0x0c,0xd8,0xf4,0x64,0x70,0xde,0xd0,0x92,0xda,0x81,0x4a,0x68,0xb5,0xc5,0x60,
+  0x2a,0xdd,0xa3,0xde,0xb5,0x5a,0xe8,0x38,0xc7,0x4e,0xb2,0x8b,0x92,0x5b,0x43,0x1a,
+  0xba,0xaf,0xd1,0xff,0x9e,0x52,0x33,0x33,0x85,0x61,0x64,0xab,0xa5,0xbb,0xbd,0xf6,
+  0x57,0x64,0x92,0x56,0x55,0xc1,0x56,0x60,0x77,0x0c,0xd8,0xca,0xf5,0x65,0x12,0x1c,
+  0xd1,0xdc,0xa3,0x00,0x2e,0x81,0x5e,0xbb,0x28,0xd0,0x5b,0x03,0x95,0xc3,0x2e,0x0d,
+  0x0d,0xb1,0x5b,0xaa,0xe1,0x1a,0x42,0xfe,0x25,0xc0,0x41,0x0a,0xd7,0xc9,0x6a,0x6f,
+  0xad,0x08,0x2d,0x85,0x47,0x8e,0x1e,0xd5,0xf4,0x9d,0x38,0x05,0x15,0x95,0x15,0xf8,
+  0xd4,0x41,0x23,0xa5,0x4e,0xcf,0x5f,0x21,0x5a,0x67,0xfb,0x4e,0xf5,0xcf,0x3f,0xff,
+  0xf7,0xb4,0xc6,0x4f,0x30,0x23,0x08,0xf2,0x21,0xf3,0xeb,0xe1,0x23,0x6a,0x57,0x70,
+  0xd5,0x69,0xa6,0xe3,0xd0,0xcd,0x71,0x53,0x66,0xe6,0xe3,0xa2,0xc7,0xdc,0x8b,0x55,
+  0xb8,0x38,0x87,0xeb,0x58,0x10,0x5e,0xba,0x7c,0x69,0xed,0x86,0xf5,0x01,0x01,0x81,
+  0x47,0x8e,0xa9,0x79,0x30,0x03,0xf9,0xf0,0xa9,0xd3,0xff,0xbf,0x88,0xd6,0xd1,0xf4,
+  0xfd,0x23,0xb5,0xff,0xcc,0x22,0x08,0xf2,0xe1,0x53,0x5c,0x5a,0xda,0xcd,0x41,0xf9,
+  0x0b,0x5f,0x0a,0xda,0x18,0x9b,0x0c,0xf7,0x18,0x31,0x3f,0x35,0x75,0xcb,0x8f,0x5b,
+  0x76,0xef,0xd9,0xbd,0x79,0xfb,0xb6,0xa5,0x69,0x69,0x93,0x13,0x93,0x86,0x0d,0x1b,
+  0x6e,0xdb,0xd1,0xb6,0x95,0x41,0x2b,0xf0,0xdd,0xab,0x33,0xd6,0x68,0xbd,0x17,0x8d,
+  0x8b,0x4a,0xe9,0x0b,0x40,0xb1,0x7a,0x55,0xa5,0xb4,0x52,0x2b,0x6b,0xb6,0xa3,0xff,
+  0x6d,0x5c,0x68,0xbc,0xff,0x7c,0xfa,0xbf,0xf5,0xdb,0xd0,0x8b,0x2a,0xe9,0x73,0x7a,
+  0x5f,0x8b,0x0d,0x21,0x89,0xdf,0x14,0x40,0x90,0x06,0x62,0xcb,0xb6,0xed,0x02,0x41,
+  0xdd,0x5e,0x36,0xe7,0x32,0x37,0x25,0x45,0xeb,0x5d,0x68,0x2c,0x54,0xbd,0x7a,0xf9,
+  0xd3,0x4f,0x3f,0xf7,0xe9,0xdb,0xcf,0xd5,0xed,0x63,0x25,0xfe,0xba,0x55,0xdb,0x5b,
+  0x21,0x0d,0x41,0x03,0xfd,0xff,0x8b,0x34,0x10,0x9a,0xd6,0xdf,0xf8,0xed,0xf4,0xe9,
+  0x7a,0x6c,0x65,0xff,0x81,0x43,0xdc,0xdd,0xd2,0xc5,0xd5,0xad,0x97,0x8b,0xeb,0xb0,
+  0xe1,0x1e,0xe7,0x2f,0x5c,0xd0,0xfa,0x08,0x20,0x48,0xd3,0xe3,0x9f,0x92,0x67,0x53,
+  0xa7,0x4e,0x7b,0xeb,0x77,0x5d,0xa3,0x62,0x62,0xb5,0xde,0x85,0x46,0x84,0xda,0xf5,
+  0x27,0xeb,0xeb,0xfb,0xbf,0x75,0x02,0xfd,0x6f,0xe3,0x42,0xb3,0xff,0xad,0xcf,0xfb,
+  0xcf,0x9b,0x36,0xd5,0x61,0xfd,0x0d,0x04,0x41,0xde,0x9d,0x87,0x8f,0x1f,0xc7,0xc7,
+  0x4f,0x7c,0x93,0x95,0x2b,0x54,0xf1,0x1c,0xe9,0x85,0x8f,0x60,0xbd,0x21,0x30,0xff,
+  0xad,0xeb,0xf7,0x17,0x1a,0x0e,0x7c,0xfe,0xaa,0x71,0xa1,0x69,0xfd,0xab,0xfa,0x7d,
+  0xfe,0xaa,0x4e,0xdf,0x1f,0x44,0x10,0xa4,0x5e,0xf8,0xe7,0xd9,0xb3,0xf4,0x65,0xcb,
+  0xed,0xbb,0x76,0xab,0x65,0x05,0x03,0xb5,0xb8,0xb9,0xb9,0xa9,0xbe,0xe5,0x8a,0x68,
+  0x62,0xcd,0xba,0x75,0x1f,0x8a,0xff,0xc5,0xff,0x7f,0x1b,0x15,0xef,0xe7,0xff,0xdf,
+  0x3a,0xad,0x3f,0x89,0x20,0x48,0x7d,0x51,0x29,0xad,0xcc,0xcd,0xcd,0x4b,0x4c,0x4c,
+  0xb2,0xb5,0xed,0xf4,0x26,0x4b,0x1f,0xb7,0xd0,0x6d,0xc1,0x30,0xe2,0xc9,0x49,0x89,
+  0xb5,0xac,0xf0,0x86,0x70,0xd1,0xb8,0xfe,0xb3,0x6e,0x8b,0x0b,0x97,0x2e,0xbd,0x67,
+  0x63,0xd0,0xff,0x36,0x2e,0x34,0xbd,0x7f,0xf4,0x1e,0xfc,0xaf,0xa6,0xf5,0x27,0x11,
+  0x04,0xa9,0x77,0x8a,0x9e,0x3e,0x3d,0x7a,0xfc,0xc4,0xe2,0xc5,0x4b,0x42,0x43,0x43,
+  0x87,0x0c,0x19,0xf6,0xb1,0x5b,0xef,0x9e,0xce,0xbd,0x5c,0x5c,0xdc,0xfa,0xf5,0x73,
+  0x1f,0x31,0xc2,0x23,0x30,0x38,0x38,0x79,0xc6,0xac,0xf5,0x1b,0x36,0x66,0xe5,0xe4,
+  0xfc,0x53,0x5c,0xdc,0x34,0x56,0xb4,0x78,0x6f,0xa8,0x9d,0xff,0xd6,0xf2,0xfd,0xa3,
+  0x86,0xe3,0xfb,0x8c,0x95,0xaa,0xfe,0xd7,0xdc,0xdc,0xe2,0xf4,0x99,0x33,0x5a,0x1f,
+  0x25,0x44,0x95,0x2d,0xdb,0x34,0xbd,0x7f,0x54,0x9f,0xcf,0x5f,0xe1,0xfc,0x17,0x41,
+  0x3e,0x04,0xa4,0x55,0x55,0x25,0x65,0x25,0x8f,0x0a,0x0b,0xef,0x15,0xe4,0xdf,0xbe,
+  0x73,0xfb,0x0e,0x59,0x98,0xad,0xa0,0xf0,0x49,0x51,0x71,0x69,0x09,0x2e,0x36,0xfe,
+  0x76,0xc0,0xb5,0xca,0x9a,0xb5,0xeb,0xda,0x18,0xb5,0xd1,0xd7,0xd3,0xe7,0x02,0x1e,
+  0xf9,0x72,0x5e,0xde,0x7b,0x36,0x66,0x75,0x46,0x86,0x7a,0xff,0x8b,0xf3,0xdf,0x0f,
+  0x12,0x4d,0xcf,0x5f,0xd5,0xef,0xfc,0x77,0xf3,0xd6,0xad,0x4a,0x3b,0x27,0x60,0x25,
+  0xb2,0x42,0xff,0x8b,0x20,0x48,0x63,0x27,0x2f,0xef,0xea,0x8a,0x6f,0x57,0xa6,0xa5,
+  0xa7,0xa7,0x2f,0x5b,0xfe,0x4d,0x5a,0x3a,0x8d,0x2c,0x5b,0xb6,0x62,0x45,0xe1,0x93,
+  0x27,0x0d,0xdd,0xb4,0x12,0x6b,0xd7,0x6d,0x10,0x98,0x0a,0x8c,0x0c,0x8d,0x8c,0x8c,
+  0x8d,0x64,0xa1,0xb1,0x91,0xb8,0xa3,0x4d,0xb6,0xe6,0xaf,0xf2,0x21,0x5a,0xe4,0xa7,
+  0xbd,0x7b,0x2d,0x2c,0x2d,0x8d,0x8d,0x4d,0x8c,0xd8,0x9f,0xa1,0x91,0x49,0x1b,0x13,
+  0xe0,0x4c,0x56,0x56,0x3d,0xb6,0x72,0xed,0xc6,0x75,0xd8,0x27,0xd3,0xd2,0x97,0x43,
+  0xf8,0x4d,0xda,0x32,0xd8,0x39,0x21,0xf2,0x7d,0xc6,0x9a,0x7b,0x05,0x75,0xf8,0x4a,
+  0x02,0x82,0x20,0xc8,0x87,0x89,0xf4,0x65,0x95,0xf4,0x25,0x59,0x89,0x9a,0x0d,0x59,
+  0xde,0xbf,0x19,0x8f,0x0b,0x8b,0xb2,0xb2,0xb3,0xb3,0xcf,0x9d,0xcb,0xca,0x39,0xc7,
+  0x86,0xc0,0xf9,0x8b,0x97,0x4a,0xca,0x4a,0xb4,0x3e,0x44,0x88,0x2a,0x45,0x4f,0xff,
+  0xc9,0x39,0x7f,0x3e,0x2b,0x27,0xe7,0x6c,0xce,0xb9,0xb3,0xe7,0xc8,0x26,0xcb,0x3e,
+  0x77,0x1e,0x28,0x29,0xad,0xe7,0xa7,0x1f,0xe9,0x9e,0x49,0x76,0x4e,0x08,0xd9,0x9d,
+  0xf3,0xdd,0x3f,0x45,0x8a,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,
+  0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,
+  0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,
+  0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,
+  0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,
+  0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,
+  0x08,0x82,0x20,0x08,0x82,0xd4,0x17,0x55,0xaf,0xaa,0xa4,0x2f,0xa5,0x95,0xd2,0xca,
+  0xf2,0x8a,0xf2,0xd2,0xe7,0x65,0x25,0xe5,0xa5,0x40,0x29,0x0b,0x4d,0xd6,0x12,0x96,
+  0x2a,0x34,0x51,0xb9,0x71,0x2a,0xe3,0xe6,0x6e,0xda,0xca,0x0d,0xbe,0x7d,0x39,0xc9,
+  0xb2,0xe7,0x65,0x94,0xf2,0xf2,0x8a,0xe7,0x70,0x32,0x29,0xab,0x78,0xce,0x52,0x2e,
+  0x8f,0x68,0xa6,0xe2,0x0d,0x24,0x75,0xe2,0x1d,0x8b,0x37,0x05,0xca,0x2b,0x2b,0x2a,
+  0xa4,0xd2,0x17,0x2f,0xa5,0x55,0xaf,0xe0,0x24,0xaf,0x7d,0x47,0x83,0x00,0xe0,0x6a,
+  0x4b,0xcb,0x4a,0x1f,0x16,0x3d,0xbe,0x79,0xeb,0x7f,0xe7,0x2e,0x5e,0x38,0x72,0xf4,
+  0x48,0xe6,0x96,0x2d,0xcb,0x56,0xac,0x98,0x35,0xe7,0x3f,0xb1,0x71,0xf1,0x21,0x21,
+  0xa1,0x41,0xc1,0xe3,0x81,0xf1,0x21,0xa1,0xc1,0xe3,0x43,0x42,0xd8,0x30,0x34,0x0c,
+  0x24,0x4a,0xa1,0x22,0x17,0x12,0xa8,0xdc,0x78,0x95,0x71,0x73,0x37,0x6d,0xe5,0x86,
+  0xde,0xbe,0xdc,0x64,0x58,0x58,0x78,0x44,0x44,0x64,0x74,0x54,0x7c,0xd4,0x84,0xcf,
+  0xa2,0x12,0xe6,0x44,0x25,0x2e,0x88,0x99,0xf6,0x75,0xcc,0xb4,0xf4,0xd8,0xe4,0xb4,
+  0x98,0xe9,0xe9,0x31,0xd3,0x97,0xc5,0x24,0x2f,0x83,0x24,0x09,0xd9,0x88,0x9c,0xe8,
+  0xe9,0x2b,0xb8,0x49,0xb5,0x12,0x59,0x41,0x45,0xa8,0x9a,0x54,0x5b,0x9c,0xcd,0x85,
+  0xa6,0xb9,0xad,0xab,0x2d,0x95,0xbc,0x4c,0xa6,0xc6,0x52,0x4b,0xbb,0x5c,0x61,0xed,
+  0x15,0x2a,0x45,0x94,0x92,0x5c,0xab,0x54,0x73,0xd5,0xa2,0xa9,0x15,0x55,0x9b,0xa7,
+  0xa5,0x4f,0x98,0xb5,0x62,0xc6,0x57,0x3f,0x7c,0x93,0xb1,0x6b,0xf3,0xce,0xe3,0xfb,
+  0x8f,0xe6,0xfc,0xfe,0xc7,0x5f,0x7f,0xdd,0xba,0xfd,0xe0,0xf1,0xd3,0xe2,0xd2,0xd2,
+  0xca,0x17,0x2f,0xb4,0xee,0x89,0xfe,0x3d,0x80,0xcf,0x2d,0x7a,0xfa,0xe4,0xe2,0x1f,
+  0x17,0x57,0xaf,0x59,0xe3,0x1f,0x14,0xf0,0x49,0xef,0xde,0x5d,0xba,0x74,0xb1,0x12,
+  0x59,0x09,0x4c,0xcd,0x4c,0x8c,0x4d,0x0c,0x5b,0x19,0x1a,0xb4,0x34,0xd0,0xd3,0xd5,
+  0xd3,0x6d,0xae,0xab,0xd3,0x4c,0x07,0x41,0x10,0xe4,0xad,0x81,0xd3,0x88,0xae,0x8e,
+  0x9e,0x8e,0x8e,0xbe,0xae,0xee,0x47,0x2d,0xf5,0xdb,0xb4,0x34,0xee,0x60,0x20,0xb0,
+  0x37,0xb4,0xfa,0xc4,0xd8,0x7a,0xb0,0x89,0x8d,0x97,0x89,0x8d,0xb7,0x49,0x47,0x6f,
+  0x13,0x9b,0x51,0x26,0x1d,0xbd,0x48,0x84,0xc4,0xbd,0x64,0x72,0x9b,0x91,0x26,0x36,
+  0xa3,0x69,0x48,0x23,0x1d,0x3d,0x89,0x1a,0xc1,0x9b,0x67,0x4b,0xe5,0x24,0xf4,0x32,
+  0xb1,0xf5,0x92,0xa9,0xd5,0x48,0x7a,0xf1,0xec,0x46,0xb2,0xca,0x10,0xf2,0x6c,0x47,
+  0xf2,0x6a,0xe6,0x92,0xd0,0x56,0x11,0x82,0xdc,0xbb,0x5a,0x4e,0x9a,0xf3,0x96,0xd5,
+  0x26,0x13,0x12,0x78,0x32,0x1d,0x0f,0x5a,0xa7,0x17,0x55,0x18,0x4d,0xe3,0xde,0x8a,
+  0xda,0x78,0xb6,0x9e,0xca,0x56,0xb1,0xc6,0xd8,0x92,0x0a,0xa9,0x19,0xb4,0x20,0xe9,
+  0xcb,0x18,0xa2,0xac,0x30,0x40,0xd1,0x90,0xac,0xa0,0xbc,0xac,0x3c,0x97,0xed,0x02,
+  0xed,0x94,0x97,0x6a,0x2e,0x3b,0x62,0x3c,0xbb,0x51,0xd0,0x11,0x9e,0x1d,0xb4,0x05,
+  0x11,0x68,0xd4,0xc7,0x44,0x3c,0xb2,0x8d,0xd8,0x93,0xb5,0x13,0x6c,0xe0,0xdb,0x79,
+  0x99,0x75,0xf2,0xb1,0xb4,0x1f,0xd3,0xce,0xc9,0xd7,0xba,0xe7,0x78,0xbb,0xde,0x11,
+  0xf6,0x83,0xe3,0xdc,0x7d,0x12,0xc7,0x44,0xa6,0x2e,0x5c,0xfe,0xe3,0x89,0x33,0xb9,
+  0x77,0x0a,0x0a,0x2b,0x5e,0x54,0x6a,0xdd,0x43,0x35,0x55,0x4a,0xca,0x4a,0x2f,0xe6,
+  0xe6,0x2e,0x4d,0x4b,0xf3,0xf2,0xf2,0xb6,0x6e,0x6f,0xad,0xaf,0xa7,0xdf,0xfc,0xff,
+  0x9a,0x23,0x08,0x82,0xbc,0x57,0x74,0x0c,0x74,0x5b,0x1a,0xb7,0x34,0xea,0xd0,0x5a,
+  0xe4,0x66,0x22,0xf6,0xe0,0xd9,0xf8,0x80,0xe7,0xe5,0xd9,0x81,0x63,0x1a,0xc5,0x23,
+  0x9e,0x82,0x7a,0x1c,0x3b,0x1f,0x9e,0xdd,0x58,0x93,0x8e,0x24,0x62,0xd2,0xd1,0x87,
+  0x47,0x7c,0xb4,0x0f,0xf1,0x29,0x36,0x10,0x1f,0x03,0x9a,0x90,0x64,0xa1,0x6a,0x4a,
+  0x49,0xaa,0x66,0xeb,0xa3,0x2c,0x54,0x89,0x2b,0xa1,0x54,0x55,0x8d,0x2c,0xf0,0xe3,
+  0x90,0xcb,0x3a,0x47,0x85,0x32,0x27,0xa9,0x30,0x52,0xb5,0x2a,0xae,0xbc,0xba,0x2f,
+  0xca,0xca,0x1a,0xcd,0xa8,0x53,0x2e,0xed,0x3b,0xb1,0x8a,0x1a,0x3c,0x86,0x8c,0x1e,
+  0xbd,0x42,0x90,0x0f,0xa0,0x17,0xbd,0xd4,0x21,0xd0,0x81,0x85,0x01,0xf7,0x84,0xeb,
+  0x01,0x18,0x7c,0xc6,0x35,0x78,0xc0,0xb8,0x99,0xb3,0xbe,0xdc,0x70,0xf0,0xe4,0xb9,
+  0xa2,0xe2,0xb2,0xaa,0x57,0x55,0x5a,0x77,0x58,0x4d,0x83,0x82,0x07,0xf7,0xf7,0xed,
+  0xdf,0x3f,0x29,0x61,0x72,0xf7,0xee,0x3d,0x0c,0xf4,0x3f,0xd2,0xfe,0xd1,0x87,0x20,
+  0x08,0x42,0xd1,0x69,0xd1,0x5a,0x9f,0x67,0x63,0xd4,0xae,0x0f,0xf8,0x02,0x7e,0xe7,
+  0x71,0xfc,0x4e,0xe3,0x78,0x14,0x88,0xf3,0x6c,0xc7,0xf2,0x3a,0x4b,0x78,0xb6,0x34,
+  0xce,0x0a,0xa9,0x5c,0x0b,0xc9,0x2e,0xbe,0x3c,0xb9,0x61,0x60,0x15,0x9b,0xcb,0xeb,
+  0x24,0x51,0x52,0xa6,0xf8,0x72,0xcb,0x42,0x41,0xd2,0x23,0x3b,0x5f,0x7e,0x17,0x49,
+  0x75,0xb2,0x93,0xa4,0xe1,0x6c,0x26,0x56,0xd9,0xc9,0x43,0x18,0x40,0x00,0x22,0x76,
+  0x74,0x60,0xed,0xc6,0xb2,0xa3,0x4a,0x42,0x92,0x3b,0x86,0xe6,0x12,0x1d,0x7a,0x3d,
+  0x00,0x49,0x2f,0x1a,0x8e,0xe9,0xd4,0x37,0x2c,0x64,0xf2,0xd7,0x6b,0xb6,0xfd,0x7a,
+  0xfd,0xe6,0x9d,0x4a,0x29,0xde,0x9d,0x7e,0x1b,0xe0,0x02,0xa6,0xe8,0x9f,0x27,0x3b,
+  0x76,0xed,0x1a,0x38,0x64,0x90,0xc0,0xd4,0x4c,0xa7,0x99,0x8e,0xd6,0x8f,0x35,0x04,
+  0x41,0x10,0x65,0x9a,0xe9,0xe8,0xe8,0x1a,0x18,0xb4,0x69,0x6f,0xd8,0xb6,0x0f,0xaf,
+  0x93,0x0f,0x71,0x52,0x5d,0xfd,0x68,0x28,0xe1,0x77,0xf5,0x27,0x61,0x17,0x4a,0x57,
+  0x16,0xdf,0x5a,0x43,0x25,0xea,0xa4,0x5c,0x93,0x2e,0x2a,0x55,0x39,0x04,0x91,0xd0,
+  0x3e,0x48,0x56,0xdc,0xde,0x5f,0xb9,0xa1,0x2e,0x6a,0x9b,0xa0,0xdd,0x21,0x48,0x6a,
+  0x74,0x8a,0xc8,0xdf,0xdd,0x66,0x15,0x05,0xb0,0xaa,0x33,0xc4,0x03,0x64,0x83,0xd6,
+  0x2d,0x88,0xf8,0xe8,0xae,0x81,0x7c,0xfb,0x40,0x92,0x05,0x80,0x84,0x98,0x11,0x40,
+  0xc2,0xce,0xd4,0x24,0x12,0xa9,0xf6,0xce,0xec,0x9c,0x1a,0xbc,0xb0,0x65,0x37,0x3f,
+  0x17,0x8f,0xc9,0x9f,0xa7,0x6f,0xbe,0x75,0xf7,0x01,0x7a,0xe1,0x3a,0x51,0x51,0x59,
+  0xf1,0xd3,0xde,0xbd,0xde,0xa3,0x46,0xb5,0x6e,0xd5,0x5a,0xfb,0xc7,0x17,0x82,0x20,
+  0xc8,0x6b,0x69,0xa6,0xab,0xd7,0x5a,0x64,0xd4,0xa1,0x3f,0xf1,0x71,0xdd,0xc6,0x13,
+  0x9c,0xc2,0xf9,0x0e,0xc1,0x7c,0x87,0x30,0x82,0x53,0x18,0x49,0x3a,0x85,0xf2,0x9d,
+  0x22,0xf8,0x4e,0x21,0x2a,0x61,0x28,0xcd,0x0d,0xe3,0x50,0x57,0x65,0x36,0x12,0x41,
+  0x09,0x97,0xb7,0x18,0x46,0x94,0x1d,0xd9,0xaa,0x42,0x64,0x38,0x2a,0xaa,0xaa,0xd9,
+  0x90,0xc3,0x78,0x12,0x2a,0x72,0xa1,0x94,0x63,0x84,0x80,0x9b,0xe5,0x10,0x42,0x94,
+  0x1d,0x69,0x16,0x29,0xfe,0xee,0x36,0xab,0x28,0x43,0x43,0xa4,0x5d,0x0a,0x3b,0x6e,
+  0xec,0x48,0x2a,0x13,0x48,0x1c,0x31,0x00,0x7e,0x19,0xfc,0xaf,0x3d,0xeb,0xaf,0x7d,
+  0xd9,0x99,0xbe,0x6c,0x4e,0x4d,0x67,0xc7,0xa6,0x76,0x63,0x5d,0x86,0x4d,0xfa,0x6e,
+  0xdd,0x4f,0xf7,0xf2,0x1f,0x68,0xdd,0xaf,0x7d,0xf8,0x3c,0x2b,0x79,0x76,0xe8,0xf0,
+  0xaf,0xfe,0x81,0x01,0x7c,0x13,0xbe,0x6e,0x73,0x5d,0xed,0x1f,0x53,0x08,0x82,0x20,
+  0x6f,0x8c,0xae,0xae,0xbe,0xbe,0xb1,0xb5,0x89,0xad,0x97,0x59,0xf7,0x48,0x81,0x73,
+  0xac,0xb9,0x73,0x8c,0xb9,0x73,0x9c,0xa0,0x7b,0x8c,0xa9,0x53,0xb4,0x69,0xf7,0x18,
+  0x1a,0x89,0x82,0x88,0x0c,0x10,0x52,0x79,0x7d,0x25,0x05,0xdd,0xd9,0x30,0xc6,0xac,
+  0x07,0x10,0x6b,0xda,0x5d,0x16,0x17,0x50,0x1d,0x22,0x71,0x8a,0x86,0xf0,0x4d,0x92,
+  0x60,0x27,0x1b,0x17,0xf4,0xa8,0xce,0xa2,0x5d,0x88,0x65,0x93,0xf5,0x6b,0xb9,0x3c,
+  0x19,0x6d,0xe6,0x1c,0x6f,0xe6,0x1c,0xcb,0xca,0x89,0xf1,0x64,0x0c,0xe3,0x48,0xbb,
+  0xd4,0x18,0xe8,0x0b,0x4d,0xc2,0x18,0x46,0x09,0x9c,0x22,0xf9,0x4e,0x91,0xa6,0x10,
+  0x3a,0x84,0xca,0xe8,0x16,0x40,0xe7,0xf5,0x7e,0xb2,0xbb,0x10,0xf4,0x1f,0x01,0x40,
+  0xe8,0xe0,0xff,0x89,0x67,0xe2,0xda,0xed,0xc7,0xff,0xbe,0xfb,0x48,0x5a,0x85,0x7f,
+  0x0d,0xab,0x41,0xfa,0x52,0x9a,0x7b,0xe5,0x4a,0xdc,0x84,0x09,0x6d,0x45,0x6d,0xf1,
+  0x6e,0x33,0x82,0x20,0x8d,0x17,0x3d,0x3d,0xc3,0x56,0x42,0x37,0x0b,0xe7,0x58,0xa1,
+  0xdb,0x14,0xa1,0xdb,0x67,0x80,0x85,0xeb,0x14,0x4b,0x57,0x36,0x92,0x08,0x11,0x16,
+  0x10,0xb2,0xf2,0xfa,0x4a,0x0a,0xdd,0x92,0x2c,0x5c,0x93,0xa0,0x15,0x4b,0xb7,0x24,
+  0x2a,0x4f,0xb2,0x74,0xa3,0x61,0xaf,0x24,0x35,0x45,0x7a,0x25,0x02,0x9a,0x2b,0x4c,
+  0x84,0xaa,0x64,0x95,0x34,0x80,0xa9,0x1a,0x92,0x49,0x16,0x6e,0x89,0x96,0x2e,0x93,
+  0x59,0x39,0x19,0x2e,0x17,0x08,0xa7,0x58,0xba,0x24,0x09,0x3f,0x9e,0x2a,0x74,0x99,
+  0x62,0xee,0x92,0x68,0xd9,0x33,0xc9,0xa2,0x57,0x82,0x45,0xcf,0x04,0x61,0xcf,0xc9,
+  0x70,0xbd,0x01,0x83,0x2c,0x20,0x4e,0x19,0xdc,0x74,0x2c,0x99,0x56,0x3b,0xd2,0xf9,
+  0x3e,0xb9,0x53,0x1d,0x2c,0xbb,0x49,0x0e,0x93,0x62,0xbb,0x71,0x26,0xb6,0x63,0x84,
+  0x8e,0x01,0x23,0x82,0xe7,0xee,0x3d,0x78,0xa6,0xfc,0x39,0x3e,0x26,0x5d,0x83,0x92,
+  0xb2,0xd2,0x85,0x8b,0xbf,0xb0,0xb4,0x10,0x6a,0xfd,0xc0,0x41,0x10,0x04,0x79,0x77,
+  0x60,0x12,0x61,0x60,0x68,0x69,0xda,0x45,0x22,0xec,0x9d,0x2c,0x72,0x9f,0x2d,0xec,
+  0x33,0x5b,0xd4,0x7f,0xb6,0xb0,0xef,0x7f,0x00,0x36,0x52,0x23,0x74,0x9f,0x2d,0xea,
+  0x37,0x5b,0x16,0x2a,0x22,0xee,0x2a,0x6a,0xaf,0x53,0x16,0xf6,0x4b,0x61,0x93,0xc2,
+  0x7e,0x73,0xa8,0xf2,0x5c,0x61,0x9f,0x39,0x24,0x97,0x2d,0xd8,0x4f,0x56,0x44,0x61,
+  0x06,0x01,0x92,0x7d,0x38,0x56,0x55,0xeb,0xbc,0xa6,0x6c,0x03,0x76,0x81,0xd3,0x10,
+  0x65,0x26,0x35,0x72,0x96,0xc8,0x7d,0x96,0xf0,0x53,0x4a,0x9f,0x99,0xc2,0x4f,0x92,
+  0x85,0x9f,0x26,0x0b,0x7b,0x4f,0x27,0x50,0x07,0x0d,0x13,0x67,0xcb,0x9e,0x93,0x2c,
+  0x9c,0xe3,0xc1,0x1d,0x03,0x30,0x95,0x36,0x75,0x0c,0x37,0x05,0x2f,0x4c,0xee,0x54,
+  0x07,0xb3,0x93,0x62,0x70,0xc4,0x82,0xae,0x81,0x92,0xb8,0x45,0x17,0xaf,0xe5,0x6b,
+  0xdd,0xeb,0x7d,0x20,0xdc,0xcd,0xbf,0x97,0x3c,0x73,0x66,0x1b,0xa3,0x36,0xec,0x4b,
+  0xbb,0x5a,0x3f,0x70,0x10,0x04,0x41,0xea,0x85,0x96,0xfa,0x26,0x3c,0x9b,0xc1,0x96,
+  0xfd,0xe7,0x8b,0x06,0x7d,0xd1,0x76,0xf0,0x17,0xa2,0x81,0x5f,0x88,0x06,0x2d,0xa9,
+  0x66,0x60,0x4d,0x49,0x3d,0x26,0x07,0x7f,0x29,0x93,0x28,0xb5,0xa8,0x16,0x85,0xa6,
+  0x42,0xb9,0x96,0x52,0x0d,0x67,0xb3,0x6a,0x52,0x26,0x5c,0xac,0x88,0x58,0x0d,0x5a,
+  0x6c,0x35,0x70,0x01,0x44,0x84,0xee,0xa9,0xc2,0xfe,0xa9,0x42,0xf7,0x79,0x42,0x77,
+  0xb8,0xe4,0x98,0x23,0xfc,0x74,0xa6,0xf0,0xd3,0xd9,0xc2,0x8f,0xa7,0xc1,0x7c,0x5f,
+  0x08,0xb3,0xe9,0x9e,0x09,0xe4,0x8e,0x7a,0x4f,0x7a,0xb7,0xdf,0x29,0xdc,0xd4,0x21,
+  0x94,0x3c,0xb2,0x65,0x1f,0x48,0x6f,0x4a,0xfb,0x9a,0x75,0x91,0xf4,0x1d,0x3d,0xed,
+  0xd4,0x85,0x1b,0xff,0xf2,0xe7,0xb2,0xaa,0x5e,0x55,0x5d,0xce,0xbb,0x3a,0xd2,0xcb,
+  0xbb,0x75,0xab,0xd6,0xe4,0x55,0x77,0xf2,0xb6,0x3b,0xfe,0xe7,0x8b,0x20,0x48,0x93,
+  0xc2,0xa8,0x7d,0x6f,0xab,0x01,0x0b,0xac,0x47,0xac,0xec,0x30,0xec,0x3b,0x08,0xad,
+  0x47,0x7c,0xcf,0xd2,0x61,0xc4,0x6a,0xa0,0x21,0x92,0xd6,0x9e,0xab,0x3a,0x8c,0xf8,
+  0x8e,0x15,0x32,0x9e,0x20,0x5f,0x45,0xda,0xf5,0x58,0x0d,0xd0,0x24,0xab,0xb3,0xda,
+  0x9a,0x8d,0x0f,0x5f,0x05,0x30,0x9e,0x19,0x00,0x49,0x7a,0x50,0x09,0x55,0xa6,0x9a,
+  0x2b,0x89,0x9a,0x07,0x95,0x37,0xa4,0xcd,0x9c,0xe4,0x2a,0x6a,0xff,0x6a,0x12,0x0e,
+  0xff,0x0e,0xb0,0x86,0x70,0xe8,0xb7,0x0a,0xda,0x0d,0x59,0xd6,0x6e,0x68,0x3a,0x60,
+  0x35,0xe8,0x1b,0xab,0x41,0x4b,0xad,0x86,0x2c,0x11,0x0e,0x5c,0x24,0x1c,0xb0,0xc8,
+  0x6a,0xe0,0x7c,0x98,0xb6,0x8b,0xfa,0xce,0x12,0xf5,0x49,0x16,0xba,0x4d,0xb3,0x74,
+  0x99,0x62,0xee,0x3c,0xc9,0xbc,0x47,0xbc,0xb9,0xf3,0x04,0x41,0xf7,0x68,0x72,0x5f,
+  0x1a,0x26,0xc2,0xf6,0x01,0xfc,0xae,0xfe,0xbc,0xce,0x7e,0x0e,0x83,0x13,0x36,0x6c,
+  0x3f,0x5a,0x51,0xf9,0x2f,0xbd,0x17,0xfd,0xbc,0xf2,0xf9,0x81,0x43,0x87,0x5d,0x5d,
+  0xdd,0x3e,0x32,0xf8,0x48,0xb1,0x5c,0x95,0xd6,0x8f,0x14,0x04,0x41,0x90,0x7a,0xa6,
+  0x99,0xae,0x81,0xa0,0xb3,0xa8,0xff,0x02,0x66,0xcc,0x66,0xc6,0x67,0x0b,0x33,0x6a,
+  0x13,0x25,0x93,0x19,0x9d,0x29,0x8b,0x8c,0xa2,0x91,0xd1,0x14,0x36,0x17,0xb2,0x14,
+  0xc9,0xd1,0x0a,0x32,0x95,0xcb,0x2a,0x14,0x46,0x6d,0xaa,0x96,0x90,0xb2,0x3f,0xc8,
+  0x93,0xf2,0xca,0x95,0xea,0x1f,0xc5,0x29,0xe2,0x93,0x29,0xb3,0x61,0x74,0x66,0xcd,
+  0xe6,0x38,0x35,0xd7,0x68,0x2e,0x93,0xf1,0xfe,0x41,0xd9,0x36,0x25,0x33,0x46,0x71,
+  0xfb,0xc2,0xa9,0xa4,0x3a,0x57,0xa5,0x0b,0xd5,0x92,0xcc,0x6a,0x05,0x9f,0x9a,0x66,
+  0x7b,0x6f,0x60,0xbc,0x37,0x42,0xeb,0xd6,0x23,0x33,0xac,0xbd,0x33,0xd8,0x8b,0x04,
+  0x70,0xd0,0xed,0x87,0xad,0x68,0x3f,0x74,0x85,0xd5,0xd0,0xaf,0x45,0x83,0x60,0xe2,
+  0xbf,0x48,0xd8,0xff,0x73,0xd9,0xa4,0xf8,0x13,0xe2,0x88,0xcd,0x5d,0x27,0x9a,0xf5,
+  0x88,0x33,0xa3,0x37,0xa5,0xf9,0x8e,0x11,0xe4,0x01,0x75,0x98,0x0b,0x77,0xf6,0x65,
+  0x5c,0xc3,0xe6,0x2f,0xdd,0xf2,0xb0,0xf0,0x69,0xd5,0x4b,0xed,0x3b,0xc4,0xf7,0x09,
+  0x4c,0xfc,0xd7,0x6f,0xdc,0xd0,0xb5,0x6b,0x57,0x70,0xbe,0x7a,0x2d,0xf4,0xf4,0x74,
+  0xf5,0x88,0xff,0x6d,0xae,0xd3,0x42,0xa7,0x85,0xf6,0x0f,0x16,0x04,0x41,0x90,0xfa,
+  0xa5,0x99,0xae,0x3e,0xbf,0x53,0xdb,0x61,0x4b,0x98,0x80,0x9f,0x19,0xc9,0x5e,0x16,
+  0xb1,0xdf,0x2e,0x12,0xf1,0xfb,0x99,0xc0,0x0a,0xfd,0xe4,0xf8,0xff,0x2c,0x4b,0x42,
+  0xe8,0xcf,0x11,0xfa,0xc9,0xca,0x12,0xa1,0xef,0x1e,0x12,0xca,0xd4,0x48,0x5c,0x2c,
+  0xd9,0x49,0x75,0x68,0x59,0x88,0xf8,0xee,0x66,0xfc,0xf6,0xc8,0x6b,0xe6,0x94,0x65,
+  0x8b,0x40,0x71,0xaa,0x49,0xcc,0x90,0x15,0x91,0xd7,0xe9,0xcf,0xb1,0x84,0xd5,0x07,
+  0x39,0xd1,0x97,0x35,0x54,0xdd,0x34,0x5b,0x55,0xb5,0x19,0x9c,0x86,0xb8,0xa6,0x4a,
+  0xf6,0xc8,0xd4,0xb8,0x35,0x2b,0x75,0x01,0x0a,0xfa,0x73,0xfa,0x4e,0x3b,0x22,0xf6,
+  0xdf,0x45,0xc3,0xdd,0x72,0xcb,0x49,0x8f,0xc4,0xbe,0x3b,0x99,0x71,0xbb,0x08,0x3e,
+  0x9b,0x09,0xe0,0x9d,0xbd,0xd7,0x33,0x5e,0xeb,0xad,0x3d,0xc8,0x7c,0xb9,0xfd,0xd0,
+  0xe5,0x6d,0x87,0xa6,0x59,0x0d,0xfc,0x4a,0x34,0x68,0x91,0xc8,0x7d,0x9e,0xa8,0xdf,
+  0x1c,0xf2,0x1f,0xf1,0xc7,0xd3,0x2c,0x7b,0x4d,0x86,0xe9,0xb0,0xc0,0x39,0x9a,0xdf,
+  0x3d,0x8a,0xef,0x14,0xc5,0xb7,0x97,0xf0,0xed,0xfd,0x2c,0x9c,0x42,0x26,0xfe,0x67,
+  0xd5,0xed,0x82,0x87,0x5a,0xf7,0x89,0xef,0x8d,0xa2,0x27,0x4f,0x52,0x53,0x17,0xf0,
+  0x4d,0x4d,0x5b,0xb5,0x6a,0x05,0xfe,0x17,0x60,0xdd,0x2e,0xbe,0x70,0x84,0x20,0x48,
+  0x13,0x46,0xdf,0xa8,0x9d,0xd5,0xe0,0x2f,0x98,0x90,0xe3,0xcc,0xf8,0xe3,0x4c,0xf0,
+  0x31,0x66,0xfc,0x49,0x26,0x14,0x22,0x47,0x98,0xe0,0xa3,0x24,0x09,0x84,0x1c,0xa1,
+  0x91,0xa3,0x44,0x18,0x74,0x98,0xc6,0xe5,0xb9,0x6c,0x52,0x26,0x54,0xc0,0x29,0x2b,
+  0x83,0x96,0xad,0x21,0x91,0xa3,0x5c,0x56,0x53,0x96,0xbc,0x86,0x5a,0xf4,0x55,0x0b,
+  0xca,0x22,0x35,0x5b,0xaf,0x51,0x43,0xcd,0x8e,0xbc,0x89,0xcd,0xa0,0x19,0x7a,0xaa,
+  0x46,0x32,0xe8,0x08,0xe5,0x10,0x13,0x70,0x50,0xce,0x01,0x71,0xc0,0x3e,0xe2,0xdf,
+  0xc1,0x1d,0x8f,0xfd,0x91,0xdc,0x5e,0x20,0x13,0xe4,0x0d,0x1d,0x46,0xac,0x6a,0x3f,
+  0xe4,0xdb,0xb6,0x83,0xbf,0xb1,0x1a,0xfc,0xb5,0x70,0xc0,0x22,0x51,0xff,0x14,0xf2,
+  0xe0,0x96,0xdb,0x34,0x21,0x7d,0x52,0x4b,0xd0,0x23,0x86,0xb8,0x60,0xf6,0x6d,0x62,
+  0x7b,0xbf,0x5e,0x5e,0xd3,0xb3,0x73,0x6f,0x56,0xbd,0x6c,0xfa,0xaf,0x26,0x3d,0xaf,
+  0xa8,0x58,0xbc,0xe4,0x4b,0x91,0x48,0x64,0x64,0x68,0xc4,0xfa,0x5f,0x83,0x96,0x06,
+  0x30,0xf9,0x6d,0xa1,0xdb,0x02,0x6f,0x41,0x23,0x08,0xd2,0x84,0x81,0xf3,0x5b,0xeb,
+  0x36,0xed,0xda,0x8d,0x5e,0x2f,0x8e,0xf8,0xbd,0x63,0x54,0x36,0x13,0x99,0xc3,0x44,
+  0x9c,0x95,0x93,0xcd,0x84,0x9f,0x65,0xc2,0xb3,0xe4,0xc9,0x2c,0x1a,0x07,0xe1,0xef,
+  0x90,0x24,0xca,0x11,0x10,0xc9,0x16,0x47,0xfe,0x2e,0x8e,0xcc,0xae,0xd6,0xe7,0x16,
+  0xaf,0x8e,0x67,0xd1,0xac,0x6c,0x59,0x28,0xcf,0x65,0xcb,0x8a,0x69,0x52,0x1c,0xc1,
+  0x51,0xa8,0x6e,0x97,0x53,0x09,0x57,0x18,0xae,0x21,0x8c,0xa0,0x3a,0x34,0xde,0x31,
+  0x2a,0x4b,0x1e,0x9e,0x55,0xcd,0xa5,0xa1,0xbc,0x6b,0x35,0x84,0x50,0x84,0x55,0x96,
+  0x09,0x89,0x85,0x91,0x20,0xa4,0x61,0x34,0x11,0x42,0x9c,0x76,0xff,0x2c,0x19,0x0a,
+  0x52,0x16,0xc2,0x33,0x4c,0xd8,0x29,0xe2,0x9a,0x81,0x10,0x70,0xcd,0x87,0x99,0xc0,
+  0x5f,0x99,0xc0,0x43,0x8c,0xff,0x2f,0x8c,0xff,0x3e,0xb1,0xdf,0x0e,0xe2,0x88,0xc9,
+  0xa4,0x78,0xa3,0xf5,0xc8,0x8c,0x0e,0x23,0x56,0xb6,0x1d,0x92,0x6e,0x35,0x08,0xbc,
+  0xf0,0x02,0x61,0xbf,0x14,0x61,0xef,0x19,0x64,0x2e,0xec,0x9a,0x20,0x20,0x5e,0x38,
+  0x56,0xb6,0xe8,0x47,0x57,0x89,0x47,0xc8,0xfc,0xcb,0xd7,0xff,0xd6,0xba,0x7f,0x6c,
+  0x50,0x2a,0xa5,0x2f,0xb6,0x6c,0xdd,0xca,0x30,0x62,0x1e,0x8f,0x67,0x6c,0x6c,0x6c,
+  0xd8,0xda,0x90,0xf8,0x5f,0x7d,0x03,0xbd,0x16,0x7a,0x30,0x05,0x26,0x1f,0x1c,0xc1,
+  0xe7,0xaf,0x10,0x04,0x69,0xd2,0x7c,0x64,0xee,0xd8,0x61,0xec,0x56,0x26,0xee,0x32,
+  0x13,0x93,0xcb,0xc4,0x5e,0x66,0xe2,0xaf,0x32,0x71,0x79,0x4c,0xec,0x15,0x26,0xfa,
+  0x0f,0x12,0x82,0x04,0x00,0x09,0x57,0x18,0x73,0x89,0xca,0xaf,0x90,0x22,0x71,0xa0,
+  0x93,0xcb,0xc4,0xe7,0x11,0x21,0x94,0x05,0x61,0x1c,0x5b,0x84,0x53,0x96,0xa8,0xe5,
+  0x11,0x35,0x36,0x64,0xe5,0x20,0x8c,0xb9,0x2c,0x8e,0x23,0x49,0x71,0xdc,0x25,0xaa,
+  0xc6,0xd6,0x90,0x2b,0xab,0x99,0x94,0xa5,0xad,0xb0,0x59,0xb2,0xb2,0x57,0xaa,0xeb,
+  0xa9,0x51,0xe7,0x15,0x99,0x32,0x6b,0xa1,0xc2,0x4e,0xae,0x0e,0x54,0xce,0x5a,0x22,
+  0xb3,0x47,0x6e,0x5e,0xf4,0x25,0x99,0x90,0x2d,0x28,0xeb,0xac,0x5c,0x27,0x26,0x17,
+  0x8c,0x14,0x83,0x91,0xf1,0x97,0x69,0xc7,0x69,0xb5,0xa0,0x16,0xfd,0x87,0x38,0x36,
+  0x57,0x1c,0x7d,0x11,0x92,0xe2,0xe8,0x0b,0xe2,0xa8,0x1c,0x26,0xf2,0x1c,0x21,0x9c,
+  0x5e,0xab,0x10,0x8f,0x7c,0x92,0xdc,0x58,0x60,0x67,0xc7,0x7e,0xfb,0x18,0xdf,0x5d,
+  0xcc,0x98,0xad,0xe4,0x4f,0xe4,0x91,0x6b,0xac,0x89,0x17,0x4e,0x13,0x0d,0xfa,0x12,
+  0xe6,0xc2,0xc2,0xbe,0x73,0xc0,0x0b,0x5b,0xba,0x4c,0xb1,0x70,0x99,0x24,0x20,0x4b,
+  0x94,0x44,0xf1,0x1d,0xc3,0x4d,0xed,0x03,0x7c,0x27,0x7c,0x5d,0xf0,0xf8,0xa9,0xd6,
+  0xbd,0x64,0x03,0xf1,0xa2,0x4a,0x7a,0xe4,0xd8,0x71,0x47,0xa7,0xee,0xa6,0xa6,0x02,
+  0x3e,0x5f,0x00,0x2e,0xd8,0xd0,0xd0,0x10,0x66,0xc1,0x2d,0x5b,0xb4,0x04,0xe7,0x8b,
+  0x37,0x9f,0x11,0x04,0xf9,0x57,0xd0,0x4c,0xb7,0xb5,0xa8,0x87,0xf5,0xf8,0xc3,0xe2,
+  0x84,0x9b,0xe2,0x49,0x37,0x28,0x7f,0x42,0x9c,0x99,0xf4,0x27,0x33,0x91,0xc4,0x99,
+  0x89,0xd7,0x69,0x78,0x83,0x24,0x27,0xdf,0x94,0xe7,0x92,0xb8,0x4c,0x58,0xad,0xa3,
+  0x1c,0xaa,0xcf,0x9a,0x74,0x83,0x2d,0xce,0xd6,0x46,0x1a,0x4a,0xf8,0x4b,0x6d,0x43,
+  0xd5,0x95,0xb0,0x45,0xe4,0x91,0x5a,0xda,0xfd,0x7f,0xf6,0xae,0x04,0x28,0xaa,0x63,
+  0x6b,0x57,0xfd,0x7f,0xa2,0x68,0x54,0x04,0x15,0x95,0x1d,0x66,0x98,0x61,0x53,0x14,
+  0x17,0x10,0x71,0x21,0x8a,0x46,0x5f,0xf4,0x99,0xc4,0xbc,0x3f,0x31,0x9a,0xf8,0x34,
+  0x89,0xbe,0x24,0x3e,0x05,0x44,0x86,0x31,0xc6,0x0d,0x17,0x16,0x41,0x56,0x51,0x54,
+  0x44,0x11,0x10,0x45,0x40,0x01,0x51,0x41,0x10,0x14,0x35,0x88,0xca,0xa2,0x6c,0x82,
+  0x6c,0xb3,0x30,0x0c,0xfb,0x3a,0xa0,0x55,0xff,0xe9,0xee,0x3b,0x97,0x11,0x99,0x71,
+  0xa2,0x12,0x2b,0x29,0xca,0x53,0x63,0xdf,0xbe,0xdd,0xa7,0x4f,0x77,0xdf,0xdb,0x5f,
+  0x7f,0x7d,0xfa,0x36,0x94,0x55,0xd8,0xc8,0x57,0x12,0x14,0xd3,0xf2,0x92,0x2a,0x52,
+  0x65,0x9c,0xd7,0x68,0x33,0x95,0x5e,0x9a,0xb2,0x48,0xd6,0x12,0x1c,0x2f,0xab,0xaa,
+  0x88,0x92,0x4d,0x85,0x08,0xdc,0xe1,0x17,0xcf,0x52,0xd8,0x3f,0xe5,0x18,0x6d,0xcc,
+  0xc6,0x3c,0x1a,0xa8,0xfd,0x1d,0xc4,0x8b,0xbf,0x4d,0x61,0xae,0x49,0x06,0x46,0x8c,
+  0xbc,0xdb,0x88,0x0e,0x47,0x30,0x56,0x84,0x1a,0xfc,0x23,0x58,0x7f,0xa9,0x9f,0xce,
+  0x22,0x4f,0xed,0x8f,0xdd,0x74,0xec,0xb6,0x6b,0xdb,0x70,0x80,0x08,0xa3,0x23,0xb6,
+  0x80,0x08,0x4f,0x59,0xa7,0x35,0x7d,0xed,0xe6,0x9d,0xa7,0xc4,0x8d,0xcd,0xef,0x1d,
+  0x2b,0x07,0x42,0xf2,0x1e,0x17,0x2c,0xfd,0xf4,0xd3,0x09,0x13,0x27,0x82,0x68,0x68,
+  0x4c,0x00,0xfc,0x55,0x57,0x53,0x1f,0x35,0x72,0x14,0xf1,0xff,0x0e,0x53,0x19,0x36,
+  0x74,0xc8,0xe0,0xe6,0xab,0x41,0x19,0x94,0x41,0xf9,0xfb,0xcb,0x87,0x1f,0x0c,0x1d,
+  0x63,0xfe,0xa5,0xd1,0x2f,0x79,0x2c,0xa7,0x4a,0xa3,0x2d,0xc5,0x6c,0xc7,0x32,0x04,
+  0x5e,0x0e,0xe5,0x46,0x8e,0xcf,0xd0,0x2f,0x84,0x1d,0xcb,0xc9,0x25,0xcb,0xe1,0xa9,
+  0x34,0x06,0x85,0x59,0x90,0x00,0x49,0x39,0x95,0xde,0xa1,0xcc,0xc8,0xb1,0x82,0x84,
+  0x11,0xa4,0x42,0xb8,0xcf,0x25,0xd1,0x89,0x05,0x65,0x77,0x78,0x4a,0x15,0x01,0x19,
+  0x5f,0x2e,0x48,0x56,0x95,0x6c,0x2e,0x1c,0x53,0x46,0xe5,0x92,0x5b,0xae,0xd4,0xec,
+  0x3e,0xe5,0xd2,0x79,0xfb,0x15,0x9c,0x98,0xe5,0x54,0xce,0xda,0x5a,0xc9,0x72,0x2c,
+  0x83,0xaa,0x81,0x48,0x6b,0x41,0x8a,0xab,0xc0,0x97,0x95,0xa8,0x5c,0x7c,0x97,0xe5,
+  0x50,0x82,0x72,0xfd,0xb7,0x88,0xe5,0x50,0x0a,0xb7,0x5e,0x82,0x63,0x90,0xff,0xe4,
+  0x23,0x82,0xbf,0x31,0x07,0xd1,0xe1,0x0d,0x39,0xcc,0x75,0x99,0xc8,0xc3,0x2e,0xcb,
+  0x85,0x3f,0x0f,0x63,0xae,0x38,0x61,0xb0,0x34,0x48,0x7f,0xb1,0xaf,0xee,0x22,0xf4,
+  0xf9,0xb0,0xce,0xbc,0x5f,0x35,0xad,0x9d,0x26,0xce,0xf8,0x19,0xb9,0x83,0x2d,0xd7,
+  0xeb,0xcc,0xfc,0xe1,0x48,0xe8,0xe5,0x8e,0xbf,0xdd,0x47,0x49,0x35,0x3c,0xfe,0xb2,
+  0xe5,0x9f,0x4d,0xd4,0xd4,0x99,0xa8,0xa9,0x0d,0xa2,0xa9,0xa5,0x3d,0x76,0xec,0x38,
+  0x80,0xe0,0xd1,0xa3,0x47,0x03,0xfe,0x02,0x05,0x7e,0xef,0x6f,0xc4,0xa0,0x0c,0xca,
+  0xa0,0x0c,0xca,0x9f,0x29,0x13,0x6c,0x1d,0x11,0x26,0x3a,0xd7,0x80,0xb0,0x01,0x83,
+  0xb6,0x56,0x21,0xc1,0x97,0x83,0xf2,0x8a,0x54,0xbf,0xd4,0x38,0x10,0x76,0xc4,0xc0,
+  0xed,0x54,0xc1,0x72,0x7a,0x86,0x29,0x73,0xb1,0x11,0x8d,0xc8,0x40,0x8d,0x37,0x3e,
+  0x42,0xab,0xd6,0xc4,0xdd,0xbc,0xfe,0x16,0xb5,0x28,0xfd,0x55,0x2c,0xf3,0x5f,0xe7,
+  0x18,0x2b,0x4e,0x31,0x96,0x87,0xe8,0x2f,0xf6,0x47,0xc7,0x7a,0x2c,0xdc,0xab,0x3d,
+  0x9f,0xab,0x3d,0x87,0xa3,0x69,0xe5,0x30,0x61,0xc6,0x26,0x8d,0x69,0x3f,0x30,0xe6,
+  0x6e,0x3a,0x7a,0x36,0xf9,0xef,0xf4,0x45,0x52,0x5d,0x7d,0x9d,0xeb,0xf6,0x1d,0xba,
+  0xfa,0xfa,0xda,0xba,0xba,0x7a,0x7a,0xfa,0x9a,0xda,0x3a,0x5a,0xda,0xda,0x63,0xc7,
+  0x69,0x00,0x04,0xab,0x8d,0x56,0x23,0x5b,0xa0,0x87,0x7c,0x38,0x64,0xf0,0xfc,0x2b,
+  0x65,0x64,0xe8,0x87,0x43,0xd5,0x54,0xd5,0x0c,0x0d,0x19,0x33,0x67,0x5a,0xad,0x58,
+  0xf1,0xd9,0x86,0x0d,0xff,0x71,0x74,0x72,0x76,0xe1,0x6c,0x77,0x76,0xde,0xb6,0x61,
+  0xc3,0x4f,0x2b,0x57,0x7e,0x69,0x63,0x63,0x6b,0xc4,0x62,0xa9,0xab,0x8d,0x51,0x19,
+  0xa2,0xf2,0xde,0xad,0x1d,0x94,0x41,0x19,0x14,0x79,0xa2,0x32,0x4a,0x5b,0x67,0xc5,
+  0x09,0xd6,0x36,0x3e,0x6b,0x1b,0x0f,0x84,0xed,0x22,0x40,0x01,0xc0,0x62,0x17,0x01,
+  0x0a,0x3b,0xa3,0x30,0x15,0x2f,0x8b,0x44,0x38,0x86,0x4a,0x23,0x9b,0x57,0xe6,0x16,
+  0x8e,0xe7,0xf7,0xcd,0x2e,0x93,0xb8,0x6f,0x7a,0xd9,0x94,0x7d,0x02,0xd2,0x4b,0xca,
+  0x3c,0x10,0xfa,0x52,0xe6,0xb7,0xf7,0x2e,0x29,0x9a,0xca,0xd5,0x1b,0x23,0x63,0x06,
+  0xef,0xa5,0xbb,0x32,0x05,0x51,0x97,0x74,0x59,0xfd,0x56,0xff,0x55,0x5c,0x46,0xd0,
+  0x8c,0xd0,0x99,0xed,0x84,0x19,0xf7,0x96,0x12,0x6a,0xa5,0x1a,0xb9,0xb6,0xf3,0x99,
+  0x1b,0x1e,0x20,0x2e,0xfc,0x7d,0x16,0xb5,0x83,0x7a,0x75,0x22,0xfa,0x4a,0x6b,0xe5,
+  0x59,0xc6,0x8a,0x93,0x06,0x9f,0x06,0xa1,0x7d,0x59,0xf6,0xfb,0xd1,0xd1,0x97,0xb6,
+  0x2e,0x9a,0xe8,0x03,0xa5,0x9f,0x34,0x2c,0x37,0x18,0xdb,0x3b,0xdc,0xbd,0x9f,0xdf,
+  0xfd,0xb7,0xd8,0x0e,0xdd,0xfd,0xbc,0xdb,0xd7,0x2f,0xc0,0xc8,0x88,0xad,0xc3,0x60,
+  0x80,0x18,0x32,0x0c,0x75,0x0c,0x19,0x3a,0xba,0xba,0x13,0x26,0x6a,0x8d,0x1b,0x37,
+  0x4e,0x5d,0x5d,0x5d,0x55,0x55,0x95,0x3e,0x82,0x83,0xa0,0xf0,0xa0,0x2f,0xb8,0x5f,
+  0x19,0x35,0x72,0xd4,0xac,0x59,0x36,0x9b,0xb7,0x38,0xc4,0xc5,0x5f,0x2e,0x2a,0x29,
+  0x6d,0x6a,0x6e,0xea,0x92,0x48,0x7a,0x5e,0xc8,0xb4,0xf6,0x8b,0xe7,0x12,0x49,0x77,
+  0x53,0x73,0xf3,0xd3,0xf2,0x8a,0x84,0x2b,0xc9,0xdb,0x7f,0xdd,0x69,0x6f,0xbf,0x08,
+  0xc0,0xfa,0xbd,0x5b,0x3e,0x28,0x83,0x32,0x28,0xfd,0xca,0x47,0x1a,0x26,0xac,0x4d,
+  0x05,0x08,0x9e,0x38,0x42,0x82,0x62,0xa6,0xae,0x7c,0x63,0x97,0x5e,0x7c,0xa1,0xf1,
+  0x51,0x8a,0x89,0x04,0xcb,0xf8,0xb2,0x38,0x0b,0x79,0x09,0x58,0x4b,0x71,0x99,0x2f,
+  0x05,0x41,0x2a,0x31,0x05,0x82,0x94,0xc2,0x57,0xee,0xf6,0x29,0x08,0xb4,0x6d,0xe3,
+  0xcb,0x96,0x4b,0x03,0x3d,0xc9,0x8b,0x8b,0xab,0x91,0x01,0x53,0xbe,0x34,0x25,0xad,
+  0x53,0x40,0x83,0x66,0xef,0x24,0x41,0x9e,0xe6,0xbe,0x20,0x4e,0x9a,0x82,0x4f,0x27,
+  0x86,0xaa,0xf5,0xd6,0xd7,0xf9,0xa5,0x96,0x91,0x69,0x16,0x52,0x41,0x84,0xc5,0x6c,
+  0x67,0x4c,0x8d,0x1d,0xcb,0x7b,0xb9,0x30,0x46,0x61,0xa3,0x0d,0xf7,0x98,0xeb,0x33,
+  0x99,0x6b,0x53,0x99,0xab,0xaf,0xa0,0x4f,0x89,0xbf,0x88,0x64,0x7e,0x7e,0x8a,0xf1,
+  0xe9,0x31,0xdd,0x45,0x87,0xb5,0xed,0xdd,0xd1,0x07,0x4a,0xb6,0xae,0xda,0xd6,0x4e,
+  0xf8,0xcf,0x3f,0x6d,0x9c,0xbf,0x6a,0x57,0x5e,0x49,0xd5,0x7b,0x47,0xcf,0xb7,0x97,
+  0xdc,0xfc,0x7c,0xdb,0x39,0xb6,0x00,0xbb,0x4c,0x26,0x8b,0x09,0xc4,0x8c,0xc5,0xd2,
+  0x63,0xb2,0xf5,0x0d,0xf5,0x81,0x02,0x8f,0x1f,0x8f,0x76,0x61,0x11,0x17,0xf0,0xf0,
+  0x61,0xc3,0x01,0x76,0xdf,0xd5,0xf9,0x1b,0x13,0xc6,0x4f,0xfc,0x6d,0xf7,0x1e,0xaf,
+  0x43,0xde,0x20,0x87,0x0f,0xfb,0xfa,0xfa,0x05,0x06,0x04,0x1d,0x09,0x08,0x44,0x12,
+  0x18,0x84,0x24,0xe8,0x48,0xaf,0xf8,0xfa,0xf9,0xcf,0x99,0x33,0x5f,0x49,0xea,0x0d,
+  0x76,0xae,0x5b,0xb7,0xfe,0x90,0xb7,0x8f,0xb7,0xcf,0x61,0xc8,0x08,0x9a,0xfd,0x03,
+  0x40,0x8e,0xf8,0x05,0xf4,0xd5,0x0c,0x65,0xc1,0xef,0x7f,0x37,0x3b,0x8e,0xfc,0x68,
+  0xe4,0xdb,0xd4,0x05,0xda,0x84,0xc9,0x34,0x5a,0xbb,0xee,0xfb,0xc4,0xe4,0x64,0x3e,
+  0x5f,0xd8,0xde,0xd9,0xde,0xf3,0x42,0xa9,0x89,0x59,0xa7,0xa4,0xab,0x4e,0x5c,0x9f,
+  0x9e,0x91,0xe1,0xbc,0x8d,0x63,0x6e,0x66,0x3e,0x5c,0x65,0xf8,0x9b,0x19,0x00,0x2d,
+  0xf3,0xed,0x77,0x6b,0xbd,0x7d,0x7c,0xa1,0xca,0xde,0xf0,0x9f,0x5f,0x40,0x00,0xae,
+  0x29,0xa9,0x60,0x1f,0x09,0x08,0xea,0x27,0x52,0x81,0x40,0xeb,0x7d,0xba,0xfc,0x9f,
+  0xb2,0xc5,0x99,0x9a,0x98,0x41,0xcb,0x7a,0x7a,0x41,0x0b,0xfb,0xf9,0xf9,0x05,0xf8,
+  0xf9,0xfb,0xd3,0x05,0xc9,0x96,0xa8,0xb8,0x20,0x79,0x77,0x89,0x86,0x80,0x57,0xba,
+  0xc9,0xcf,0x3f,0x60,0xa1,0xfd,0xe2,0x81,0x1b,0x66,0x57,0xaf,0xf9,0x16,0x3f,0x8d,
+  0x87,0x7d,0x0e,0xa3,0x4a,0x05,0x06,0x06,0xf9,0x07,0xca,0x35,0xd2,0xd1,0x69,0xeb,
+  0x18,0xf5,0xb1,0x4a,0x6a,0x36,0x33,0x33,0x77,0xdb,0xb7,0xdf,0xc3,0xf3,0x10,0xe8,
+  0x87,0x5a,0x80,0x66,0x05,0xcd,0xe2,0xe1,0xe1,0x69,0x6a,0x62,0xaa,0x58,0xe1,0xd8,
+  0xb1,0xe3,0x7e,0xdd,0xf1,0x9b,0xd7,0x21,0xea,0x09,0x47,0xd6,0x06,0xf5,0xf3,0x78,
+  0xcb,0x6d,0xf9,0x57,0x9e,0x8a,0x7e,0x5f,0x3a,0xdc,0xe6,0x81,0xf3,0xe7,0xdb,0x29,
+  0xb0,0x44,0x4f,0x4f,0x7f,0xc7,0xce,0x5d,0x50,0x2f,0x6c,0x48,0x00,0xd8,0x41,0xf4,
+  0xf4,0x6b,0x06,0xbc,0xe6,0xb6,0xb3,0x6d,0x95,0x6c,0x34,0x7d,0x3d,0xfd,0x5d,0xbb,
+  0xf7,0xc0,0xb8,0x00,0x4f,0x17,0x98,0x41,0x2a,0xd8,0xcf,0xc3,0x09,0xdd,0x14,0x10,
+  0x08,0xcf,0xbb,0xfd,0xe2,0x01,0x7b,0x36,0xfe,0xf7,0xc3,0xf1,0x36,0x9b,0x58,0x8e,
+  0xcf,0xd8,0x2e,0x42,0x36,0x47,0x04,0xbf,0xc6,0xdc,0x3a,0x63,0xd7,0x3a,0xb6,0x54,
+  0x4c,0x5d,0x05,0xc6,0x1c,0x3e,0x04,0x58,0x9c,0x5a,0x12,0x63,0xee,0x0a,0x40,0x56,
+  0x6b,0xc2,0xe1,0xa3,0x18,0x8e,0xc8,0xc4,0x55,0x00,0x97,0xe6,0xdc,0x1a,0x3a,0xb1,
+  0x09,0x07,0xc5,0x20,0x6d,0xd2,0xc4,0x6c,0x57,0x11,0xb9,0x04,0x31,0xe3,0xf2,0x8d,
+  0x5d,0x6b,0x51,0x2e,0x5a,0x15,0x17,0x69,0x06,0x0d,0xa4,0x08,0x08,0x98,0xa0,0x12,
+  0x51,0x16,0x9c,0x58,0x84,0x2e,0x51,0x76,0xa2,0xb0,0x9a,0xe4,0x25,0x62,0xe2,0x2a,
+  0x84,0x42,0x71,0x7a,0x62,0x5b,0x35,0xa4,0x34,0x46,0x06,0x08,0xe9,0x34,0x28,0x92,
+  0xe4,0xe5,0x52,0xc5,0x81,0x4e,0xd0,0x0c,0x91,0x94,0x19,0xd8,0x78,0xfa,0x97,0x24,
+  0xa3,0x12,0xbb,0xf6,0xea,0xc1,0x22,0x02,0xf6,0x4d,0x6a,0xc7,0x72,0x11,0x62,0xcc,
+  0xed,0x65,0xcd,0xb2,0xa4,0x98,0xbd,0xb5,0x82,0xf8,0x94,0xf1,0xf6,0x2d,0x84,0xc2,
+  0xac,0x9f,0x1e,0xa1,0x2d,0xd3,0xdf,0xe3,0xdd,0x59,0x6b,0xae,0xa1,0xf3,0x3d,0xfe,
+  0x15,0xcd,0xfc,0x3c,0x8c,0xb1,0xec,0x98,0xfe,0x12,0x5f,0xdd,0xc5,0xee,0xda,0x76,
+  0x7b,0xb5,0xe7,0x72,0xb5,0xac,0x1c,0x35,0x67,0xfe,0x32,0x7e,0xfa,0x46,0xae,0x67,
+  0x78,0xbb,0xa4,0xfb,0xbd,0x03,0xe8,0xdb,0x08,0x80,0xc5,0xee,0x3d,0x7b,0xd9,0x6c,
+  0x13,0x23,0x23,0x13,0x36,0xdb,0xd8,0xcc,0xcc,0xcc,0xc4,0xc4,0x84,0xc5,0x62,0x1b,
+  0x30,0x0c,0x35,0x75,0x34,0x09,0xfe,0x8e,0x1c,0x81,0xbe,0x02,0xa6,0xf7,0x5f,0xbd,
+  0x93,0x5d,0x58,0xc6,0xc6,0xc6,0x77,0xee,0xde,0x3b,0x77,0xfe,0x42,0x42,0xd2,0xb5,
+  0xbc,0x82,0xc7,0x02,0x61,0x6d,0x17,0xb4,0xe4,0x8b,0xfe,0x8d,0x04,0x9c,0xda,0xb5,
+  0x7b,0xb7,0x92,0x3e,0xe8,0xd1,0xa3,0x46,0x87,0x47,0x44,0xc6,0xc6,0x5d,0xba,0x10,
+  0x7b,0xe9,0xee,0xbd,0xfb,0x95,0x55,0xd5,0xad,0x6d,0x8a,0x00,0x31,0xfb,0xc1,0xfd,
+  0xf1,0xe3,0xc6,0xbf,0x71,0x45,0xd4,0xd5,0xd4,0x57,0x7d,0xb3,0x26,0xe3,0xf6,0xad,
+  0xe6,0xd6,0xd6,0x37,0xee,0x85,0xce,0xae,0xce,0x47,0x79,0xb9,0x5b,0x9d,0x39,0x5a,
+  0x5a,0x6f,0xf2,0x17,0xa6,0x54,0x86,0xaa,0x84,0x9d,0x09,0xbf,0x9c,0x90,0x74,0x31,
+  0x2e,0xfe,0xde,0xef,0xd9,0x95,0xd5,0x35,0xed,0x1d,0x9d,0xef,0xcc,0x3f,0xf2,0xe2,
+  0xf9,0xf1,0x13,0x27,0x65,0x8b,0xfb,0xe7,0x8a,0xcf,0xa0,0x94,0xa8,0x73,0xe7,0x53,
+  0x52,0x33,0x8b,0x8b,0x4b,0x1b,0x1a,0x5b,0xfe,0x84,0x63,0xd2,0x25,0x3d,0xdd,0x1e,
+  0x5e,0xde,0x03,0x35,0xc6,0xfe,0xcf,0x07,0x61,0xe1,0x67,0x12,0xaf,0x5c,0xb9,0x10,
+  0x1b,0x9f,0x75,0x2f,0xbb,0xb2,0x92,0xd7,0xdc,0xd2,0xa2,0xe0,0x99,0x79,0x98,0x9b,
+  0xcb,0x64,0x18,0x29,0xa9,0xf9,0x8b,0x95,0x5f,0xa4,0xa6,0xa5,0x9d,0x8d,0x8c,0x4e,
+  0x4d,0xcb,0x7c,0x52,0x54,0x5a,0xdf,0xd0,0x04,0x75,0x91,0xa7,0xb9,0xb9,0xb5,0x65,
+  0xe5,0xca,0x95,0xaf,0x79,0x77,0xd8,0xc6,0xb7,0x6e,0x67,0x45,0x46,0xc5,0x24,0x26,
+  0x5d,0x7b,0x94,0x57,0x28,0x12,0x89,0xe1,0x05,0x19,0xa0,0x66,0x07,0xa0,0x57,0x60,
+  0xc9,0xac,0x59,0x36,0x59,0x77,0xef,0x87,0x9e,0x09,0x4f,0xba,0x7a,0xbd,0xe0,0x71,
+  0xa1,0xa8,0x4e,0x2c,0xe9,0x96,0x5b,0xb5,0x4e,0x89,0x84,0xbb,0x7d,0x87,0x92,0x8d,
+  0xb6,0xf6,0xdf,0xeb,0x8a,0x4b,0x4a,0x0b,0x1e,0x17,0x09,0x6b,0xc5,0x5d,0xf2,0xc7,
+  0xd8,0xee,0x1e,0x74,0x5e,0x01,0x74,0xd6,0xe6,0x2d,0x0e,0x03,0xf7,0x6c,0x0c,0x1f,
+  0x39,0xc1,0xe0,0xab,0x28,0x29,0xc2,0x8a,0x64,0xa4,0x8e,0x0e,0x98,0x6d,0x17,0x00,
+  0x2e,0x9b,0x6f,0xe7,0x41,0x1a,0x94,0x8c,0x2b,0x36,0xe5,0x0a,0xe1,0x92,0x04,0xe0,
+  0x97,0xc2,0x26,0xea,0x56,0x2d,0x44,0x82,0x90,0x4b,0x3a,0x6f,0xaf,0x66,0x3a,0x17,
+  0x17,0xe5,0xa2,0x52,0xba,0x8a,0x00,0x97,0x21,0x31,0xc6,0x71,0x3e,0xbe,0x8b,0x04,
+  0x6e,0x11,0x6d,0x18,0xa6,0x21,0x6f,0x1d,0xca,0x4b,0x12,0x03,0x7c,0x63,0x85,0x10,
+  0x03,0x45,0xa0,0x4b,0x50,0xc8,0x15,0x23,0x84,0xe5,0xa2,0x78,0x0c,0xa9,0xc8,0x2a,
+  0xfa,0x2e,0xd2,0xe6,0xca,0x27,0xb9,0x88,0x66,0x52,0x04,0x6d,0x1b,0xb1,0xb9,0xb7,
+  0x68,0x57,0x01,0x0b,0x43,0x39,0x41,0x67,0x84,0xb9,0x48,0x04,0x74,0x00,0x01,0x3d,
+  0x47,0x68,0xee,0x5a,0x05,0xa0,0xdc,0x97,0x1d,0x13,0x97,0x3a,0xa0,0xb0,0x43,0xa9,
+  0x91,0x43,0x19,0xde,0x2c,0x5d,0xc0,0xfc,0xf1,0x3e,0xfa,0xe2,0x98,0x1c,0xeb,0xb1,
+  0x3a,0xc9,0xe8,0xff,0xa2,0x99,0x2b,0x23,0x18,0xcb,0x43,0xf4,0x16,0xf9,0xa2,0x3f,
+  0xf4,0xb0,0x60,0xa7,0xf6,0x6c,0x8e,0xb6,0x8d,0xf3,0xf8,0x69,0x1b,0xa7,0x2c,0xd9,
+  0x76,0x2f,0xf7,0x99,0x3c,0xd4,0xf8,0x4b,0x48,0xc6,0xad,0xdb,0x53,0xa7,0x5a,0x02,
+  0xe0,0x02,0xf2,0x4e,0x9e,0x6c,0x61,0x32,0x69,0xaa,0xb9,0xb9,0x39,0x84,0x81,0xd0,
+  0x69,0x33,0x58,0x13,0xb5,0xb4,0x34,0x34,0x34,0xc8,0x16,0x2c,0xb2,0x0b,0x1a,0x86,
+  0xfa,0x77,0x72,0x0a,0x07,0x83,0xc1,0xb8,0x7a,0x3d,0xe5,0xc0,0x41,0xcf,0xc0,0xa0,
+  0x90,0xf4,0x8c,0xdb,0xe5,0x15,0x55,0xed,0x1d,0x1d,0xf2,0x46,0x3c,0x49,0x8f,0x04,
+  0x66,0xfb,0x40,0x6c,0x95,0xd1,0x3c,0x72,0xc4,0xa8,0xa0,0xe0,0xa3,0xfe,0x41,0xc7,
+  0xdc,0xbd,0x7c,0xe2,0x13,0xae,0x3c,0x2e,0x2c,0x6e,0x6c,0x6a,0x92,0x74,0xcb,0x1d,
+  0x4b,0x0b,0x9e,0x3c,0xd1,0xd5,0xd1,0x7d,0x83,0x2a,0xc0,0x7c,0xe0,0x93,0xc5,0x9f,
+  0xa4,0x65,0x64,0xbc,0xab,0x13,0xc2,0xbb,0x9f,0xf7,0x14,0x95,0x94,0x7e,0xb3,0xfa,
+  0x3b,0x75,0xb5,0x31,0x7f,0xc8,0x12,0xe8,0x97,0x90,0x13,0x27,0x8e,0x1e,0x0f,0x39,
+  0xec,0x1d,0x1c,0x13,0x9b,0xf0,0xb8,0xb0,0xb4,0xb1,0xa9,0x45,0xf2,0xee,0x30,0xf1,
+  0x6c,0xe4,0x39,0xd9,0xe2,0x16,0x7c,0xbc,0x20,0x25,0xfd,0xc6,0xbe,0x03,0xee,0xa7,
+  0x4e,0x47,0x66,0xdd,0xcd,0xae,0xe1,0xf3,0x25,0x92,0xe7,0x03,0xbd,0x1d,0xa2,0xe7,
+  0xc5,0xf3,0x90,0x13,0xa1,0x03,0x37,0xc6,0x06,0x04,0x1d,0x0b,0x39,0x7e,0x12,0xf8,
+  0xef,0xc5,0xb8,0x24,0x00,0xb5,0xc6,0xc6,0x66,0x05,0x87,0xed,0x14,0x14,0x3e,0x31,
+  0x66,0x9b,0x28,0xa9,0x79,0xd9,0xb2,0x65,0x30,0x2f,0xda,0xed,0xe6,0x7e,0x26,0x22,
+  0x0a,0x9a,0x4b,0x58,0x2b,0xea,0x90,0xff,0xe7,0x4d,0x3b,0xba,0x24,0xdf,0xfd,0x7b,
+  0xbd,0x62,0x85,0x06,0x06,0x8c,0x94,0x1b,0x69,0x7b,0x0f,0xb8,0x1f,0x0d,0x09,0x4d,
+  0x4d,0xbb,0x09,0xd3,0xad,0xb6,0xf6,0xf6,0x01,0x6a,0x76,0x20,0xee,0x0a,0x5e,0xf6,
+  0x69,0x96,0xd3,0x6e,0x66,0x64,0xfc,0xba,0xcb,0x2d,0xe4,0xc4,0x99,0xf4,0x8c,0x3b,
+  0xd5,0x3c,0x7e,0x6b,0x5b,0x9b,0x82,0x1e,0xf4,0x52,0x6e,0x06,0x35,0x5c,0x65,0x78,
+  0x5c,0xfc,0xe5,0xcc,0xac,0xbb,0x39,0x0f,0x61,0x66,0x2e,0xea,0xe8,0xec,0x92,0x37,
+  0xc6,0x76,0xf7,0xf4,0x00,0xf8,0x3e,0x29,0x2c,0x9e,0x62,0x31,0x75,0xe0,0x9e,0x0d,
+  0x10,0x55,0x03,0x3b,0xd6,0xe6,0xc7,0x08,0x41,0x5c,0x10,0xd6,0x00,0x78,0x01,0x0e,
+  0x9a,0x72,0x90,0xa7,0x15,0x63,0x2b,0x0d,0xc7,0x04,0x2e,0x05,0x14,0x58,0x13,0xe4,
+  0xe2,0x02,0x09,0x45,0x94,0x16,0x2e,0x09,0x48,0xf5,0x42,0x1b,0x86,0x4b,0x1a,0xda,
+  0xa4,0x18,0x5a,0x47,0x40,0x1c,0xa8,0x25,0xca,0x45,0x53,0x4b,0xba,0x20,0x29,0x28,
+  0x9b,0x70,0x78,0x00,0x7f,0xd2,0x52,0x08,0x10,0x03,0x75,0xa5,0x26,0x00,0x94,0x49,
+  0xbd,0xe6,0x91,0xcb,0x3a,0x5c,0x05,0x11,0xad,0x93,0x32,0xa3,0xd7,0x7e,0x12,0xdf,
+  0x1b,0xc6,0x6a,0x05,0x32,0x91,0xc0,0xbb,0x85,0x50,0x23,0xc2,0xb8,0xb1,0x91,0x54,
+  0x45,0x28,0x86,0x8e,0x27,0x1b,0x04,0xd9,0x81,0xec,0x4b,0xb9,0xb6,0x88,0x64,0x24,
+  0xab,0xd6,0xf4,0x62,0x3b,0x85,0xc5,0x5b,0x2b,0xd8,0x4e,0xe5,0xd4,0xee,0x2c,0xbc,
+  0x4d,0x9a,0x85,0x88,0xf0,0x5d,0xe6,0xda,0x74,0x74,0x6a,0xc7,0x57,0xb1,0xe8,0x1b,
+  0xe1,0x15,0xa7,0x0c,0x96,0x04,0xe9,0x2e,0xf2,0x42,0x7f,0x53,0x69,0x0e,0x47,0xcb,
+  0xda,0x51,0xd3,0xea,0xe7,0x1f,0xb8,0xc7,0x1b,0x1a,0x5b,0x7b,0xfe,0x9a,0x10,0xdc,
+  0xd8,0xdc,0x08,0xf3,0x46,0x63,0x63,0x13,0x53,0x73,0x0b,0x33,0x8b,0x69,0x96,0x96,
+  0xd3,0x2d,0x2c,0x67,0x98,0x4e,0x99,0x31,0xc9,0x62,0x2a,0x70,0x61,0x43,0x86,0x91,
+  0x96,0x9e,0x8e,0x86,0xc6,0x04,0x35,0x35,0xb5,0x57,0xf1,0x17,0xb9,0x83,0x3f,0x78,
+  0x73,0x14,0xd6,0xd3,0xd5,0x4b,0xb9,0x71,0x63,0xff,0x41,0x0f,0xdf,0x80,0xe0,0x1b,
+  0x69,0x99,0xe5,0x15,0x95,0x30,0x86,0xc8,0xc3,0x5f,0x00,0xa6,0xe0,0x63,0x21,0x23,
+  0x86,0x8f,0x50,0x46,0xf3,0x47,0xc3,0x47,0x78,0x79,0xfb,0x04,0x05,0x1f,0x3f,0xe8,
+  0xe9,0x13,0x1b,0x9f,0x98,0x9b,0xff,0x58,0x31,0xfe,0x3e,0x2d,0x7b,0xc6,0x64,0x30,
+  0xff,0xa8,0xfd,0x30,0x2d,0x71,0x70,0x74,0x2a,0x2b,0x2f,0xef,0xea,0xea,0x06,0xdd,
+  0xef,0xb0,0x53,0x6a,0x45,0xe2,0xc0,0x23,0xc1,0x86,0x06,0x86,0x7f,0x68,0x92,0xe3,
+  0x17,0x14,0x74,0x3c,0x34,0xcc,0xd3,0xdb,0x3f,0x26,0x2e,0x31,0xaf,0xa0,0xa8,0xbe,
+  0xb1,0x49,0xc9,0x35,0xf0,0xd7,0x0a,0xd4,0x2e,0x2e,0xfe,0x92,0x6c,0x59,0x36,0x36,
+  0xb6,0xe9,0x99,0x19,0x6e,0xfb,0xdc,0x43,0xc3,0xc2,0x33,0x6e,0x67,0xd7,0xf0,0xf8,
+  0x30,0x03,0x19,0xe8,0x57,0x00,0xf4,0x47,0x44,0x45,0x0d,0xdc,0x00,0x7b,0xc0,0xc3,
+  0xe3,0xe4,0xa9,0x53,0x18,0x7f,0x13,0x1f,0xe6,0x3d,0x01,0xfc,0x85,0xb1,0x5d,0xde,
+  0xa4,0xa2,0xb4,0xac,0x4c,0xf9,0x01,0x7f,0xa1,0xfd,0xa2,0xb8,0x4b,0xf1,0xbb,0xf6,
+  0x1e,0x0c,0x0d,0x8b,0xcc,0xbc,0x9d,0x2d,0x50,0x88,0xbf,0x5d,0xdd,0x92,0x1f,0x37,
+  0x6c,0x54,0xac,0x50,0x5b,0x4b,0x27,0xf9,0x5a,0xca,0x7e,0x77,0xcf,0xc0,0xe0,0x13,
+  0xd7,0xae,0xa7,0xc3,0xdc,0x15,0xad,0xf0,0x0c,0xcc,0xfc,0xc7,0x2f,0x20,0x48,0x81,
+  0xcb,0xc9,0xdc,0x7c,0x52,0xca,0x8d,0xd4,0x1d,0x3b,0xf7,0x04,0x1d,0x3d,0x71,0x23,
+  0xfd,0x16,0x5e,0x78,0x91,0x3b,0x13,0x80,0x1e,0x0c,0x08,0x08,0x52,0xa6,0xc5,0xa6,
+  0x4f,0x9b,0xfe,0x28,0x37,0x0f,0x86,0x85,0xa2,0x92,0xf2,0x86,0x26,0x45,0x4f,0x72,
+  0x7b,0x47,0x67,0x73,0x73,0xcb,0xd9,0xb3,0x91,0xaa,0x23,0x55,0x07,0xee,0xd9,0x00,
+  0x19,0xa2,0xa2,0xaa,0xbb,0xdc,0x17,0x3b,0x3d,0x6b,0x09,0x12,0x01,0x61,0x04,0xac,
+  0x34,0x77,0x45,0x88,0x43,0xb0,0x15,0x68,0x20,0x01,0x1d,0x7a,0xb9,0x98,0x60,0x31,
+  0x5a,0x70,0xc6,0x64,0xd3,0x18,0xd0,0x87,0x4b,0xc5,0x93,0x95,0x61,0xb6,0x34,0x2f,
+  0x0d,0x91,0x88,0xb4,0x72,0xf9,0x38,0xa5,0x98,0x5e,0x25,0xc6,0xb8,0x46,0x2d,0xf3,
+  0x22,0xfe,0xcb,0x01,0xc8,0xa3,0xd2,0x93,0xb2,0x30,0x93,0xad,0x46,0x3a,0x09,0xab,
+  0xc5,0x34,0x1c,0x2f,0x65,0xf3,0xa4,0x3c,0xb7,0x1a,0x2b,0x47,0xe9,0xb1,0x49,0xa4,
+  0x68,0x1a,0x40,0x45,0xc6,0x32,0xf8,0x8b,0xd6,0xab,0x5d,0x85,0x38,0x2f,0x21,0xd4,
+  0x62,0x52,0x0a,0x5a,0xca,0x86,0xbc,0xae,0x78,0x46,0xc1,0x15,0x99,0x63,0x72,0x4d,
+  0xda,0x01,0x13,0x6d,0x0c,0xd0,0xc8,0xb6,0x3a,0xc2,0xa3,0xe9,0x2a,0x60,0x1b,0x70,
+  0x0c,0x2e,0x17,0x4d,0x63,0x38,0x98,0x1a,0xcb,0xfa,0x8b,0xd1,0x06,0xad,0x4a,0xe4,
+  0x14,0xde,0x5c,0xdc,0xbb,0x2f,0xeb,0xfb,0xbb,0x46,0xeb,0x6f,0xa2,0xcf,0x84,0x57,
+  0x25,0x30,0x3f,0x0f,0x07,0x16,0x6c,0xb0,0x34,0x50,0x77,0x91,0x07,0xda,0x14,0x3d,
+  0x0f,0xed,0x88,0x36,0x5b,0xb8,0x35,0xe5,0xd6,0xa3,0xbf,0x28,0xfe,0x5e,0x4e,0x48,
+  0xb0,0xb2,0xb2,0x36,0x33,0x33,0xb7,0xb4,0x9c,0x36,0x63,0xa6,0xd5,0x4c,0x2b,0x6b,
+  0x90,0x19,0x33,0x66,0x4e,0x9a,0x62,0x69,0x62,0x6e,0xc1,0x60,0x30,0x75,0x0c,0x19,
+  0x13,0x26,0x4c,0x20,0xbb,0xb0,0xc8,0x12,0x34,0xc1,0xdf,0xb7,0xf7,0x02,0x6b,0x4e,
+  0xd4,0x4c,0x48,0x4a,0x72,0xf7,0xf0,0x0e,0x08,0x3a,0x72,0x35,0x25,0xed,0x69,0x79,
+  0x65,0x4b,0x6b,0x9b,0xbc,0x59,0x2e,0xbc,0x80,0x61,0xa7,0x4f,0x03,0xb1,0x55,0x46,
+  0xf3,0xf0,0x61,0x1f,0x79,0x78,0x7a,0x1d,0x0b,0x0d,0xdd,0x7f,0xd0,0xfb,0xc2,0xc5,
+  0x04,0xe0,0x32,0xf5,0x0d,0x0d,0x0a,0x16,0x48,0x79,0x02,0xbe,0xa9,0xe9,0x6b,0x3c,
+  0x6e,0x7d,0x44,0x6b,0xa2,0xd6,0xe9,0x33,0x67,0x1a,0x1a,0x1b,0x3b,0x3b,0x95,0xc2,
+  0x1d,0x40,0x7f,0x2c,0xdd,0x5d,0x12,0x09,0x04,0xd0,0xbf,0xe7,0x88,0x30,0x42,0xde,
+  0x7e,0xb3,0x4b,0x7a,0xba,0x53,0xd3,0xd2,0xad,0xad,0xac,0x95,0xdf,0xe7,0xb6,0xff,
+  0xa0,0x7b,0xd8,0x99,0x70,0x0f,0x2f,0x9f,0xe8,0x0b,0xf1,0x05,0x8f,0x9f,0x88,0xeb,
+  0x9b,0x24,0x3d,0x4a,0xe1,0xaf,0x32,0xe3,0x76,0xda,0xcd,0x0c,0xd9,0xb2,0x2c,0xa6,
+  0x4c,0xbd,0x73,0xef,0x77,0xb7,0x03,0xee,0xc7,0x43,0xc3,0x33,0x6f,0xdf,0x05,0xfc,
+  0xed,0xe8,0xe8,0x1c,0xd0,0x55,0x20,0xd2,0x5c,0x71,0x09,0xf1,0x03,0x37,0xc0,0xee,
+  0xda,0xb3,0xf7,0xf4,0x99,0xb3,0x07,0x3d,0xbd,0xcf,0xc7,0xc4,0x3e,0x78,0x94,0x5f,
+  0x57,0x5f,0xdf,0xfd,0x5c,0xee,0xb2,0x67,0x35,0xaf,0x66,0xd6,0x2c,0x1b,0x25,0x35,
+  0xcf,0xb2,0xb6,0xb9,0x9c,0x90,0xb8,0x7b,0xef,0xfe,0x93,0xa7,0x22,0x32,0x32,0xef,
+  0xf0,0x04,0xa2,0x56,0xf9,0x74,0x15,0x7a,0xcd,0x69,0xeb,0x36,0xc5,0x0a,0xc7,0x8e,
+  0x1b,0x7b,0x29,0x31,0xc9,0xdd,0xcb,0x27,0x20,0xe8,0x78,0xf2,0xd5,0xd4,0xb2,0x67,
+  0x18,0x7f,0x07,0xa6,0xfd,0x4f,0x85,0x85,0x29,0xf0,0xfb,0xb0,0x59,0xc6,0xd7,0x53,
+  0x6e,0xfc,0xb6,0x6b,0x5f,0x50,0xf0,0x89,0xeb,0x69,0x19,0xcf,0x2a,0x6b,0x5a,0x5a,
+  0x14,0x31,0xf1,0xd3,0x67,0xc2,0x5f,0xdb,0x5c,0x2a,0x43,0x54,0x9c,0xb7,0x71,0x72,
+  0x1e,0xe5,0x01,0xa1,0xae,0xaa,0xe1,0xb5,0xb6,0x75,0xc8,0x7d,0x2a,0x5e,0x3c,0x6f,
+  0x6b,0xef,0x68,0x6c,0x6a,0x5b,0xb5,0x6a,0xf5,0xc0,0x3d,0x18,0xb4,0xa8,0xea,0x58,
+  0x31,0x7f,0xc9,0x23,0x80,0x88,0xf8,0x2f,0x97,0x4f,0x13,0x5e,0xe2,0x2a,0xa5,0xe9,
+  0x21,0x75,0x89,0x91,0xab,0xf7,0x17,0xe2,0xb7,0xf3,0xd9,0xb2,0x54,0x54,0x26,0x31,
+  0xb5,0x50,0x4c,0xa7,0xe4,0xf2,0x64,0x16,0xb7,0x31,0x68,0xba,0xf2,0x41,0xb0,0x37,
+  0x56,0x44,0x80,0x15,0x63,0x9f,0xc8,0x94,0x53,0x43,0xad,0x06,0xcb,0x64,0xa7,0xa9,
+  0xae,0x6c,0x41,0x68,0x85,0x59,0x6a,0x33,0xc1,0x65,0x74,0x89,0xb3,0x98,0x62,0xfd,
+  0xb2,0x35,0x92,0x2d,0xb7,0x4f,0xa4,0xac,0x6d,0x78,0xc9,0x5a,0xfc,0x92,0x91,0xdc,
+  0x5a,0xa9,0x91,0xd2,0x16,0xe0,0x8a,0xf1,0x8c,0x42,0x40,0x99,0x8d,0x17,0xc0,0x49,
+  0x5b,0xf5,0xdd,0x2a,0x46,0x3e,0xf2,0x72,0x7a,0xc6,0xda,0x82,0x8f,0xf5,0x40,0x10,
+  0x9c,0x63,0xf4,0xe3,0x3d,0x74,0x6a,0xd6,0x9a,0xab,0xe8,0x4f,0x3c,0x7c,0x19,0xce,
+  0x04,0x08,0x5e,0x12,0xa0,0x6d,0xef,0xae,0x6d,0xb7,0x0b,0xfd,0xd5,0x06,0x6b,0x87,
+  0xaf,0x1d,0x8e,0xd5,0x35,0x34,0x0d,0xdc,0xe0,0x33,0x40,0xd2,0xdc,0xd2,0xfa,0xd5,
+  0xd7,0xdf,0x98,0x4e,0xb2,0x98,0x32,0x65,0xea,0xcc,0x99,0x56,0xb3,0x66,0xcf,0xb1,
+  0xb1,0x9d,0x63,0x3b,0xc7,0x6e,0xd6,0x6c,0xdb,0x19,0x56,0xd6,0x93,0x26,0x5b,0x18,
+  0x1b,0x1b,0x1b,0x18,0x32,0x27,0x6a,0xa2,0x0f,0x81,0x47,0xab,0x52,0x4b,0xd0,0xe8,
+  0x20,0xca,0x21,0xd4,0x59,0x58,0x6f,0xb3,0x0a,0x3d,0x6e,0xcc,0xb8,0x8b,0x71,0xf1,
+  0x1e,0x9e,0x87,0x3d,0x7c,0x43,0xae,0x5c,0x4f,0x2d,0x2a,0x29,0x6b,0x69,0x6d,0x95,
+  0x37,0xd1,0x85,0xf8,0xa8,0xe8,0xf3,0xaa,0xa3,0x94,0x9a,0xe2,0xaa,0x0c,0x1d,0xf6,
+  0xdb,0xae,0x3d,0xa1,0x61,0xa7,0xf7,0x1d,0xf0,0x3a,0x1f,0x13,0xf7,0xe0,0x61,0x7e,
+  0x9d,0xb8,0x51,0xc1,0x58,0x5a,0x5b,0x27,0x9e,0x62,0x39,0x45,0x79,0xcb,0x27,0x4f,
+  0x9a,0x7c,0xfe,0xc2,0xc5,0xe6,0x96,0x66,0x20,0xec,0x8a,0x99,0x2f,0x10,0x28,0xc0,
+  0x7d,0x98,0x57,0x34,0x35,0xb7,0x88,0xc4,0xf5,0x42,0x51,0x9d,0xb0,0xb6,0x16,0xe8,
+  0x0f,0x04,0x80,0x9f,0x36,0x35,0xb7,0x4a,0x00,0x93,0x69,0xc3,0x5e,0xf4,0xad,0x72,
+  0xce,0x83,0x07,0xcb,0x97,0xaf,0x50,0xb2,0x91,0xb7,0xef,0xd8,0x19,0x7e,0x36,0xd2,
+  0xdd,0xd3,0xe7,0xdc,0xf9,0xb8,0x07,0xb9,0x05,0xe2,0xfa,0x86,0xee,0xd7,0xe2,0xef,
+  0x0b,0xb4,0xb0,0xd0,0x25,0xe9,0xee,0xec,0x92,0x74,0x74,0x75,0xb6,0xb5,0x75,0xc0,
+  0x68,0x86,0x02,0x40,0x2a,0x24,0xf8,0x17,0xc7,0x43,0xdc,0xef,0xd9,0xf7,0xa1,0xdf,
+  0xe9,0xb2,0x8c,0x8c,0x58,0xb7,0xef,0xdc,0x73,0xdb,0xef,0x19,0x1c,0x12,0x76,0x33,
+  0xf3,0x4e,0x65,0x35,0xaf,0xbd,0xb3,0x43,0x99,0xf1,0x1f,0xc3,0x68,0x0f,0xd6,0xd9,
+  0x0e,0x59,0xa0,0xc4,0xd6,0xb6,0x36,0xe8,0x77,0x54,0x34,0x15,0x6e,0x03,0x28,0x81,
+  0x00,0x5c,0x42,0x18,0x6e,0x81,0xa0,0xdb,0x9d,0xc8,0x8c,0x94,0xd4,0xb4,0x81,0x1b,
+  0x5d,0x5d,0x5c,0xb9,0x67,0x23,0xcf,0xb9,0x1d,0xf4,0x8a,0x8a,0x8e,0xcd,0x79,0x98,
+  0x0f,0x0d,0xa8,0xc0,0x95,0x29,0xaa,0x13,0xd9,0xd9,0x29,0xda,0x98,0x24,0x2b,0x53,
+  0x2d,0x2d,0x2f,0x25,0x24,0xec,0xdc,0xbd,0x2f,0x24,0xf4,0x74,0xda,0xcd,0xdb,0x35,
+  0x7c,0x41,0x47,0xa7,0x5c,0x4c,0x01,0xd9,0xb3,0xd7,0xed,0x35,0x40,0xa0,0xaa,0x1a,
+  0x1b,0x7f,0xc9,0xf3,0x90,0x8f,0x7f,0x60,0xc8,0x95,0xab,0xa9,0x25,0x4f,0x9f,0x41,
+  0x13,0x29,0x5e,0xee,0xc0,0x33,0x3d,0x34,0xf1,0x83,0x0e,0x86,0x49,0x60,0x5b,0x07,
+  0xea,0xe2,0x8e,0x2e,0xd4,0xdd,0xd0,0xb6,0xf4,0x25,0xea,0x15,0xd4,0x3b,0x9d,0xd0,
+  0xf8,0x10,0xe8,0x94,0x74,0x45,0x45,0x47,0x8f,0x1c,0x21,0x77,0x77,0xa2,0x81,0x81,
+  0x61,0xd2,0xd5,0x6b,0x7b,0xdc,0x0e,0x04,0x04,0x87,0x5c,0x4f,0xcd,0x44,0x4c,0xbc,
+  0x45,0x51,0xd5,0x2e,0xc6,0x5f,0x7e,0x6d,0x73,0x69,0x8c,0x1b,0x7f,0xe5,0xea,0xb5,
+  0x9b,0x99,0xb7,0xb3,0x73,0x72,0x45,0xe2,0x86,0xce,0x2e,0xf9,0x0e,0xe5,0x4e,0x09,
+  0xbc,0x46,0xf9,0x05,0x05,0x06,0xfa,0x06,0x03,0xf7,0x60,0xd0,0xf2,0xe1,0x07,0x43,
+  0x75,0x97,0x1e,0x46,0xac,0x4d,0xea,0x08,0x36,0xe1,0x0a,0x09,0x3c,0x91,0xdd,0x50,
+  0x80,0x68,0x78,0xb9,0x58,0x44,0x31,0x44,0xc4,0x22,0x79,0x98,0xbd,0xf2,0x28,0xd6,
+  0x2c,0x75,0x19,0x03,0x0c,0xe1,0x3d,0x4e,0xb5,0xb4,0x2a,0xc8,0x0b,0xa4,0x15,0x40,
+  0xaa,0x97,0x0e,0x73,0xc5,0x14,0xe0,0x72,0x29,0x24,0xc5,0x2c,0x55,0x76,0xa7,0x53,
+  0x1d,0x1b,0xfb,0x6d,0xa5,0xa4,0x5b,0x88,0xb9,0x27,0x45,0x93,0x91,0xc3,0x17,0xac,
+  0xe2,0x52,0x5b,0xb0,0x28,0xbf,0x2d,0x6d,0xa4,0xd4,0x1f,0x8d,0xb3,0xd4,0xd2,0xd4,
+  0x5b,0xca,0xcd,0x45,0x24,0x0b,0x11,0xc2,0x9d,0x21,0xa6,0x77,0x83,0x19,0x46,0x7f,
+  0xec,0x44,0x46,0xf6,0xa3,0xea,0x03,0xd5,0x75,0xed,0xad,0x3e,0xae,0x20,0x22,0xcb,
+  0x64,0xdf,0x17,0x61,0xe5,0xf4,0x92,0xb8,0xb1,0x0b,0x0f,0xc1,0x2e,0x87,0x54,0x5f,
+  0xc8,0x76,0x11,0x52,0x1b,0xa4,0x09,0x0b,0x06,0x14,0x76,0x2c,0xc3,0x67,0x76,0x91,
+  0xcf,0x84,0x1f,0xe2,0x0f,0x84,0xb3,0xd0,0x8e,0xac,0xaf,0xe3,0x98,0x2b,0x23,0x19,
+  0x2b,0x8e,0x1b,0x2c,0x09,0x44,0xbe,0x60,0xbb,0x1d,0xda,0xb6,0x2e,0xac,0x05,0xce,
+  0x27,0x2f,0xa4,0xff,0x39,0xa0,0xf9,0xae,0x04,0x5e,0xc6,0xcb,0x89,0x89,0x66,0xa6,
+  0x93,0xcc,0x2c,0xa6,0x03,0xf6,0x02,0xf2,0xce,0xb3,0x5b,0x30,0xcf,0xee,0xe3,0xf9,
+  0x76,0x0b,0x6d,0xe7,0xce,0xb3,0x9e,0x65,0x33,0x6d,0xda,0x74,0xe2,0x05,0xd6,0xd5,
+  0xd5,0xa3,0xf9,0x2f,0x39,0x08,0x1a,0xc0,0x97,0x7c,0xb8,0xfa,0x36,0x5f,0x21,0x8d,
+  0x51,0x1b,0x13,0x1d,0x13,0x83,0xb7,0xec,0x06,0x24,0x25,0xa7,0x16,0x16,0x2b,0xc2,
+  0x5f,0x90,0xa4,0xa4,0x64,0xf5,0xd1,0xea,0xca,0x68,0x86,0xe9,0x81,0xb3,0xcb,0xb6,
+  0xd3,0xe1,0x11,0xfb,0xf7,0x79,0x47,0x5f,0xb8,0x98,0x9d,0x93,0x27,0x12,0x37,0x2a,
+  0xf0,0xe5,0xd5,0x37,0x36,0x5a,0x5b,0xcf,0x52,0xd2,0x6c,0x3d,0x5d,0xfd,0x8b,0xb1,
+  0x71,0xf5,0x0d,0xf0,0xde,0xb7,0x29,0xfe,0x63,0x1c,0x50,0x97,0x96,0xb6,0x56,0x71,
+  0x43,0x43,0x0d,0x4f,0x58,0x58,0xfc,0x34,0x2f,0xff,0xc9,0xef,0x39,0x05,0x77,0xb3,
+  0x1f,0xde,0xcb,0xc9,0x7b,0x98,0xfb,0xf8,0x49,0x51,0x49,0x45,0x25,0x8f,0x2f,0x02,
+  0x45,0x2d,0x00,0x73,0xfd,0x12,0x61,0xd0,0x50,0x58,0x52,0x62,0x65,0x3d,0x4b,0x99,
+  0xd5,0x06,0xa7,0xad,0xce,0xe7,0xce,0xc7,0xb8,0x1d,0xf0,0x8c,0x8c,0x8e,0xbd,0xff,
+  0x30,0x4f,0x2c,0xae,0x97,0x48,0x5e,0x83,0xbf,0x30,0xf0,0x36,0x35,0x37,0x8b,0xeb,
+  0x1b,0x05,0xc2,0x3a,0x1e,0x5f,0x58,0x2d,0xe0,0x57,0xf3,0x84,0x35,0x7c,0x7e,0x0d,
+  0x4f,0x50,0xc3,0xab,0xad,0xaa,0xe6,0x55,0xd7,0x08,0x78,0xfc,0x5a,0x61,0xad,0xe8,
+  0xc1,0xc3,0x47,0xc3,0x54,0x86,0xc9,0x34,0x82,0x5e,0x66,0x56,0x16,0xf0,0xdf,0x23,
+  0xc1,0x27,0x53,0x6e,0xdc,0x2c,0x2e,0xad,0x80,0xd1,0x5a,0xc1,0x0a,0x3f,0x92,0x17,
+  0x08,0x7c,0xdb,0xda,0x3b,0x9b,0x9a,0x5a,0x41,0x21,0x14,0x57,0x55,0x2d,0xa8,0xa8,
+  0xac,0xae,0xac,0x16,0x54,0x61,0xa9,0xac,0xe2,0x55,0x55,0xf3,0xb1,0x08,0x64,0xa5,
+  0xb2,0xaa,0x06,0x7e,0xab,0xc1,0x2c,0xbe,0xf0,0x76,0xd6,0xbd,0x81,0x3b,0x81,0x6d,
+  0xf3,0x96,0x2d,0x91,0x17,0xce,0xb9,0x1d,0xf0,0x8a,0x88,0xba,0xf8,0xfb,0xfd,0x5c,
+  0xa1,0x48,0xd1,0x56,0xa2,0xba,0x7a,0xb1,0xfd,0xa2,0x45,0x4a,0x6a,0xb6,0x98,0x3c,
+  0x25,0xf1,0x4a,0xf2,0xee,0xbd,0x07,0x8e,0x9e,0x38,0x95,0x7e,0x33,0xb3,0xb2,0x8a,
+  0xdf,0xd6,0xd6,0xa9,0xa0,0xad,0x3c,0x0f,0x1d,0x56,0xac,0x10,0xde,0xc4,0xf3,0x17,
+  0x63,0x7d,0xfc,0x7d,0xbd,0xfd,0x82,0x13,0x92,0xae,0x16,0x97,0x3e,0x6d,0x6e,0x79,
+  0x8d,0xbb,0x1f,0x1a,0xbf,0xb5,0xbd,0x03,0x9e,0xb6,0x3a,0x71,0x3d,0x5f,0x20,0x82,
+  0x67,0x12,0xba,0x18,0x3a,0x1a,0x1a,0x16,0xfa,0xa2,0x86,0x07,0x9d,0x5e,0x4b,0xba,
+  0x9b,0xfc,0xe2,0xde,0x47,0xf3,0xc4,0x0b,0x31,0xb1,0xaa,0xa3,0x46,0xcb,0x7d,0x1d,
+  0x74,0xf4,0x92,0x92,0xaf,0xee,0xd9,0xbb,0xcf,0x3f,0xe8,0x68,0xf2,0xb5,0xf4,0xd2,
+  0xb2,0x67,0x8a,0xf9,0xef,0xd5,0x94,0xd4,0xd7,0x36,0x97,0xcd,0x6c,0xdb,0xc2,0xa2,
+  0xe2,0xd4,0xf4,0xcc,0xe2,0xd2,0xb2,0x86,0x46,0x45,0x33,0x67,0x98,0x2c,0xc0,0x03,
+  0x1c,0x7c,0x34,0x64,0xc4,0xdb,0x7d,0xbf,0xa0,0xbc,0x8c,0x36,0x9c,0xc7,0xda,0x5c,
+  0x88,0x36,0x17,0xd1,0xbe,0x5d,0xe2,0xb7,0xc5,0xbb,0xa1,0x00,0xda,0x10,0x6c,0x51,
+  0x6c,0xb4,0x8e,0x46,0x1c,0x0a,0xb6,0xb8,0x62,0xe9,0xb2,0xb0,0x88,0x30,0x68,0x82,
+  0x68,0xb4,0x2a,0x16,0xd9,0x78,0x4c,0xbb,0x4a,0x65,0xb8,0xb0,0x74,0x71,0x58,0x84,
+  0x49,0x2b,0x8f,0xf6,0xb4,0x82,0x90,0xe5,0x68,0x0c,0xd6,0x02,0x44,0x87,0xb9,0xb5,
+  0x64,0xa5,0x9a,0xd2,0x2c,0xf5,0xf0,0xa2,0x6f,0xa6,0x08,0x4a,0x72,0x04,0xb2,0xe5,
+  0xca,0xd8,0x4c,0x79,0xa5,0x89,0x85,0x64,0x0b,0x16,0xbd,0x3b,0x0b,0x8a,0x00,0xcd,
+  0x34,0x3a,0xcb,0xa6,0x91,0x7a,0x87,0x31,0x52,0xbb,0x56,0x4b,0x9b,0x85,0x22,0xc8,
+  0xa6,0x1c,0x1e,0xde,0x01,0xce,0x27,0x2e,0x60,0xd2,0x74,0xa6,0x5c,0xaa,0xdd,0x88,
+  0x33,0x1d,0x7f,0xcd,0x24,0x24,0xbb,0xb3,0xd8,0x14,0x0a,0xa3,0x73,0x3c,0xd0,0xf1,
+  0x59,0x9b,0x4b,0x90,0x3b,0x98,0x82,0xe0,0x4c,0xe6,0x9a,0x64,0xa3,0x55,0xb1,0x64,
+  0x21,0x5a,0x7f,0xb1,0x8f,0x8e,0xfd,0x01,0xed,0xb9,0xbf,0x6a,0xd9,0x6e,0x9d,0xbb,
+  0xfa,0x50,0x53,0xeb,0x5f,0x89,0x02,0xf3,0x04,0xfc,0x55,0xdf,0xac,0xb6,0xb0,0xb0,
+  0x98,0x31,0xd3,0x6a,0xf6,0x9c,0xb9,0x76,0x0b,0x16,0xda,0x2f,0x5e,0xba,0xf8,0x93,
+  0x65,0xf6,0x8b,0x97,0x7c,0xbc,0x70,0xf1,0x9c,0xb9,0x1f,0xc3,0xb0,0x6f,0x6e,0x6e,
+  0x6e,0x60,0x64,0xa2,0xa3,0xa7,0x2b,0xfb,0x15,0x12,0x40,0x30,0x39,0x0b,0x9a,0x96,
+  0x37,0x7b,0x92,0xd5,0x54,0xd5,0xce,0x46,0x44,0x1e,0xf6,0xf5,0xf7,0xf4,0xf6,0xbd,
+  0x9c,0x78,0x1d,0xf0,0xa8,0xb9,0xb9,0x95,0x2c,0x33,0xf6,0x6b,0xf0,0xcd,0x8c,0x8c,
+  0xb1,0x63,0x94,0xfa,0xe2,0x03,0x4c,0xfa,0xcf,0x4f,0x3f,0x47,0x44,0x47,0xef,0xdb,
+  0x77,0x30,0xf2,0x5c,0x4c,0x76,0xce,0x23,0x18,0x4b,0xd1,0x16,0x0e,0x39,0x4d,0x01,
+  0x53,0xfd,0x05,0x0b,0x95,0x1a,0x4b,0x75,0x75,0xf4,0xe2,0xe2,0x2f,0xd5,0x01,0xb6,
+  0x35,0x34,0xc0,0xd8,0xac,0x80,0xf1,0xc1,0x00,0x0b,0x08,0x5d,0x51,0x55,0x93,0x5f,
+  0x50,0x9c,0x96,0x79,0xe7,0xd2,0xe5,0xe4,0xf3,0x31,0x97,0x4e,0x87,0x47,0x11,0x89,
+  0x88,0x8a,0x89,0xbb,0x94,0x90,0x7a,0x23,0x33,0xfb,0x7e,0x6e,0x71,0xe9,0x33,0x20,
+  0xe0,0x2d,0xad,0x2d,0x80,0xe6,0xfd,0x56,0xff,0x49,0x51,0x91,0xbd,0x12,0xe6,0xfd,
+  0xfc,0xcb,0xa6,0x98,0xb8,0xb8,0x7d,0xee,0x87,0x22,0xce,0x5d,0xb8,0x9f,0xf3,0x08,
+  0x8c,0x54,0x3c,0x20,0x03,0xbb,0x69,0x6c,0x6c,0xa9,0xac,0xe6,0xe7,0xe6,0x3f,0xc9,
+  0xba,0x93,0x9d,0x91,0x79,0x2b,0x3d,0xe3,0x4e,0xea,0xcd,0x5b,0x69,0xe9,0x59,0xff,
+  0xcf,0xdc,0x75,0x87,0x45,0x71,0x6e,0xfd,0x3f,0xbe,0x2f,0xc6,0x98,0x28,0x12,0xa3,
+  0xb1,0x80,0x1a,0xa5,0x69,0xe2,0x0d,0x26,0x96,0xe4,0xea,0x35,0xd6,0x60,0x01,0xb1,
+  0xd7,0xa8,0xd8,0xaf,0x0a,0xb8,0x34,0x69,0xd2,0x61,0xe9,0x4b,0x97,0xde,0x7b,0xef,
+  0xbd,0x2e,0x6d,0x01,0xe9,0x45,0xa4,0x08,0x48,0xef,0x4d,0x51,0x24,0xb9,0xdf,0xf3,
+  0x9d,0x77,0x66,0x76,0x76,0x21,0xcc,0x40,0x92,0x6b,0x12,0x9e,0xf3,0xf0,0xcc,0xcc,
+  0xee,0xbe,0xf3,0x4e,0x7b,0x7f,0xe7,0x77,0xde,0xdf,0x39,0x93,0x93,0x5b,0x90,0xcd,
+  0xce,0x63,0xe7,0x72,0xb2,0xd8,0xf9,0x59,0xd9,0x85,0x45,0xc5,0xa5,0x65,0x15,0x95,
+  0x4b,0x05,0x78,0x83,0xf0,0xb2,0xe5,0xcb,0xf2,0x0b,0x39,0x4c,0x33,0x4b,0x96,0x8d,
+  0x53,0x4c,0x5c,0x52,0x55,0x75,0x3d,0x8c,0xea,0x73,0x4a,0x70,0xdf,0x4e,0x4e,0x8e,
+  0x8c,0x8e,0xc1,0x39,0xa9,0xac,0xae,0x2f,0x2c,0x2e,0xcd,0x84,0xbd,0xe4,0x14,0x66,
+  0x64,0xe5,0x65,0x66,0xe7,0xc1,0xff,0x2c,0x76,0x5e,0x16,0xac,0x66,0xe7,0xa5,0xc3,
+  0x96,0x9c,0x82,0xf4,0x6c,0xd8,0x8e,0xfe,0x03,0xab,0x02,0x83,0x2f,0xe4,0x73,0x4a,
+  0x4b,0xcb,0xcb,0xf9,0xdd,0x80,0xff,0xae,0xc9,0xc9,0xdd,0x8c,0x88,0x8a,0x36,0x64,
+  0x9a,0x05,0x06,0x87,0x15,0x95,0x94,0x0f,0x0e,0x0d,0xc1,0x29,0xa2,0x3a,0x96,0xd1,
+  0xf1,0x31,0xd9,0x13,0x27,0xe7,0xd9,0xb2,0xb8,0xa8,0x78,0x4c,0x6c,0xbc,0x91,0x31,
+  0xd3,0xc5,0xd5,0x2b,0x35,0x23,0xef,0x65,0x47,0xd7,0x38,0xad,0x54,0xde,0xc5,0xd5,
+  0x8d,0xbe,0x41,0xf0,0x81,0x83,0x42,0x42,0x1c,0x9e,0x38,0xd9,0xd8,0xbb,0xc7,0xc6,
+  0x27,0x3f,0x6b,0x6c,0x1d,0x1e,0xa5,0xe5,0xbf,0xff,0x41,0xbe,0x16,0x1c,0x51,0x53,
+  0x6b,0x4b,0x59,0x45,0x75,0x5e,0xe1,0xd3,0x2c,0x76,0x01,0x5c,0x65,0x38,0xcf,0x99,
+  0xec,0x82,0x2c,0x36,0x27,0x83,0x8d,0xce,0x79,0x4e,0x1e,0xda,0x92,0x93,0x9b,0x9f,
+  0x91,0x93,0xcf,0xce,0x2d,0xca,0x61,0x73,0x38,0x4f,0xcb,0x12,0x93,0x52,0x57,0x7c,
+  0xb6,0x82,0xaa,0x27,0xab,0x56,0xae,0x8a,0x8d,0x8f,0x37,0x31,0xb5,0xb4,0x77,0x74,
+  0x4e,0x4c,0xc9,0x68,0x68,0x7e,0x09,0x80,0x48,0x73,0x68,0x05,0x1c,0x0e,0xfd,0xa1,
+  0x81,0x7f,0xc5,0x64,0x9a,0x56,0x54,0xd5,0x72,0x8a,0xcb,0x3a,0xba,0xba,0x81,0xe1,
+  0xd2,0xcc,0x6b,0x8c,0x8d,0x4f,0xf4,0xf5,0xf7,0x4b,0x4b,0xcb,0xfc,0x69,0x45,0x81,
+  0x3e,0xfc,0x48,0x50,0xf8,0x84,0x2b,0x02,0x29,0x7e,0xd9,0x15,0x2c,0x70,0x21,0x06,
+  0x57,0x55,0x11,0xb2,0x28,0x9c,0x54,0x6a,0x74,0x13,0xa0,0x89,0x01,0x10,0x57,0x52,
+  0x05,0x24,0xb1,0x17,0xcf,0xdc,0x41,0xc9,0x44,0x00,0x8e,0xfc,0x2a,0x2c,0x20,0xce,
+  0x28,0x8a,0xdb,0x45,0x22,0x1d,0x4e,0x42,0x49,0x70,0xe4,0x05,0x84,0xf9,0x65,0xd5,
+  0x24,0x5d,0xd5,0xee,0x42,0xa8,0x87,0x08,0x69,0x1f,0x29,0x69,0xe6,0xcf,0x0f,0xc2,
+  0x02,0xce,0x98,0x5e,0x5a,0x13,0x65,0x48,0xa1,0x2f,0x13,0x60,0x3a,0x40,0xe8,0xac,
+  0xa6,0xeb,0xaf,0xa6,0xfd,0x16,0x03,0x7a,0x22,0x86,0x3c,0x5d,0xb5,0x45,0x3a,0x12,
+  0xe4,0x7e,0x71,0x65,0x17,0x37,0x56,0xc0,0x0d,0x65,0x63,0x47,0xba,0x09,0x57,0x80,
+  0xa3,0xcc,0xac,0x1e,0xec,0x5c,0x61,0xaa,0x30,0x24,0xcd,0xe2,0xe5,0x41,0x8b,0xa9,
+  0xbe,0xc4,0x4b,0x59,0x62,0x10,0x5c,0x89,0x02,0xd1,0x37,0xb1,0x40,0xf4,0x45,0x24,
+  0xc7,0xc2,0xde,0x9a,0x64,0x2b,0x74,0x80,0x29,0xb4,0x47,0x67,0xcd,0x2e,0x65,0xaf,
+  0x88,0x82,0xff,0x96,0xe2,0xe5,0x4f,0x30,0x4e,0x51,0xd1,0xae,0x5d,0xbb,0xbe,0xf9,
+  0xe6,0xdb,0xef,0x77,0xed,0xde,0x77,0xe0,0xc7,0x23,0x47,0x8e,0x1d,0x93,0x39,0x21,
+  0x7d,0xfc,0xb4,0xf4,0xf1,0x53,0x52,0x47,0x64,0xf6,0xee,0x3f,0x04,0xa0,0xfc,0xf5,
+  0xd7,0x92,0xe2,0xe2,0x9b,0xd7,0xad,0x5f,0xbf,0x6a,0xf5,0x6a,0x54,0x88,0x12,0x7b,
+  0x1d,0x21,0xa2,0xc0,0x0b,0x16,0x82,0xfd,0xc1,0xd7,0x11,0x0a,0x2c,0x16,0x70,0xf7,
+  0xf4,0xb4,0x77,0x74,0xb2,0x62,0xd9,0xc5,0x25,0xa4,0xd6,0xd4,0x21,0x95,0x32,0x4d,
+  0x3d,0x93,0xa2,0xe2,0x92,0x79,0x66,0x09,0x41,0x97,0x6e,0xde,0xba,0x1d,0x19,0x1d,
+  0x63,0x60,0x68,0x1a,0x18,0x1c,0x59,0xf4,0xb4,0xb2,0xa7,0xaf,0x7f,0x92,0x26,0x8a,
+  0xf5,0x6e,0x52,0x46,0xe6,0xf8,0x9c,0xcd,0x0a,0x0a,0x0a,0x9a,0x5b,0x5a,0x76,0x02,
+  0x79,0x18,0x18,0xc0,0xc2,0x7d,0xb3,0xb7,0xf6,0x33,0x1a,0xeb,0x26,0xfb,0x06,0x86,
+  0x9a,0x5b,0xda,0x38,0x45,0x65,0x71,0x09,0x29,0x3e,0x7e,0xa1,0x76,0x8e,0x6e,0x96,
+  0xd6,0x76,0x4c,0x33,0x6b,0x23,0x63,0x73,0xa6,0xa9,0xa5,0xa9,0x39,0x8b,0x65,0xeb,
+  0xe4,0xe2,0xe1,0x13,0x11,0x15,0x97,0x95,0x93,0x57,0x53,0xf7,0xbc,0xbd,0x13,0x25,
+  0xbc,0xcc,0xea,0xea,0xc3,0x4d,0x05,0x43,0xe2,0x26,0x89,0xcd,0xf4,0xa7,0xfa,0x9a,
+  0x9c,0x5c,0x74,0x5c,0x82,0x89,0xa9,0x45,0x40,0x70,0x68,0x31,0x1c,0x72,0x6f,0xdf,
+  0xe4,0x14,0x25,0x20,0x42,0x27,0x27,0x26,0xde,0xc2,0xb1,0x00,0x13,0x4f,0x4a,0xc9,
+  0x00,0x7f,0xc0,0xcb,0x27,0xc8,0xc3,0x3b,0xc0,0xcd,0xcb,0xd7,0xc3,0xdb,0xdf,0xdd,
+  0xdb,0xcf,0xcd,0xcb,0x07,0x96,0xc1,0xdc,0xbd,0xfc,0x03,0x02,0xc3,0x4a,0x4a,0x2b,
+  0x96,0xf1,0x39,0x3f,0x02,0x02,0x02,0xb9,0xf9,0x05,0x86,0xc6,0xa6,0x26,0xa6,0x56,
+  0x7e,0x01,0xc1,0xb9,0x79,0x05,0xad,0x2f,0x3b,0x46,0x81,0x82,0xfd,0x8c,0x11,0x79,
+  0x0a,0x0f,0x0a,0xf0,0x17,0x3c,0x8d,0xfa,0x86,0x96,0xac,0x9c,0xfc,0xa8,0x98,0x38,
+  0x1f,0xff,0x10,0x0f,0x2f,0x7f,0x57,0x0f,0x6f,0x17,0x77,0x6f,0x20,0x86,0xae,0xee,
+  0xde,0x2e,0x6e,0x5e,0xae,0xee,0x5e,0x00,0x52,0xae,0x6e,0xde,0xf8,0x7f,0xec,0x53,
+  0x2f,0xf4,0xa9,0x9b,0x57,0x50,0x68,0x38,0xb8,0x02,0x70,0x07,0xbe,0xa7,0xa1,0xf5,
+  0xd2,0xa5,0x4b,0xd1,0xb1,0x71,0x7a,0xc6,0x66,0xbe,0x01,0xa1,0x9c,0xe2,0xd2,0xce,
+  0xde,0xa1,0xb7,0x6f,0x29,0xef,0x99,0x57,0x13,0x13,0x17,0xe7,0x3d,0xe7,0xb8,0x6e,
+  0xdd,0x7a,0x40,0x76,0x63,0x13,0x33,0x67,0x57,0xcf,0xd4,0xf4,0xec,0x96,0xb6,0x4e,
+  0x70,0xf9,0x68,0xa6,0xdd,0x7d,0x7d,0x03,0xe9,0xaf,0x35,0x3c,0x7d,0x6e,0x1e,0x9e,
+  0xce,0xae,0x6e,0x2c,0xd6,0x93,0xe8,0xd8,0xa4,0xfa,0x86,0xc6,0x91,0x51,0xba,0xd8,
+  0xd1,0xd4,0xcf,0xe0,0x10,0xbe,0x79,0xd1,0xda,0x5e,0x58,0x54,0x1a,0x1d,0x9b,0x0c,
+  0x1e,0xa0,0x97,0x4f,0xa0,0xbb,0xb7,0x2f,0x6e,0xd8,0xb5,0x46,0x97,0x1b,0x5b,0xe6,
+  0x37,0x9f,0xc0,0x90,0x88,0xe4,0x94,0xd4,0x95,0x9f,0xaf,0xa2,0xea,0x09,0x40,0x73,
+  0x68,0x78,0x84,0x99,0xb9,0xa5,0x8d,0xbd,0x23,0xdc,0x48,0xf5,0x8d,0xad,0xe0,0x62,
+  0xd1,0x4c,0xca,0x94,0x56,0x54,0xd0,0xd7,0x7c,0x83,0x73,0x95,0x99,0x95,0x0d,0xee,
+  0x1f,0xb8,0x85,0xe0,0x43,0xbe,0x9d,0xa4,0xf4,0x21,0xe1,0xf6,0x86,0x7d,0x15,0x3f,
+  0x7d,0xba,0x72,0xe5,0xca,0xf7,0x74,0x4b,0xcc,0x62,0xff,0xf3,0xc1,0xa7,0x9b,0xa5,
+  0x51,0x99,0x0b,0x9c,0x3c,0xa2,0xf8,0x2d,0x01,0x58,0x28,0xc4,0x8a,0x89,0x7b,0x31,
+  0x38,0x06,0x68,0xc3,0xd3,0x63,0x51,0x30,0x96,0x2f,0xce,0x8c,0x54,0x5b,0x38,0x10,
+  0xa3,0x38,0xb0,0x46,0x0f,0x01,0x46,0x58,0xb0,0xf7,0x2b,0x8d,0x76,0xf2,0xb7,0x5c,
+  0x3a,0xd9,0xc9,0x1f,0xb5,0x26,0xdb,0x97,0x20,0x76,0x4a,0xce,0x38,0x13,0x79,0x4f,
+  0xb8,0xd4,0x0a,0xe3,0xd1,0xfd,0x5c,0xfd,0x15,0xa6,0xbb,0xd6,0x24,0x34,0x63,0xb0,
+  0xca,0x8d,0x7b,0x93,0x41,0xe6,0x01,0x9c,0x0e,0x73,0x15,0x56,0x44,0x9e,0x32,0xae,
+  0x98,0xc2,0x40,0x93,0xc8,0xff,0xe5,0x6b,0xbc,0x0f,0xeb,0x39,0x26,0x72,0x46,0x84,
+  0x97,0xe8,0x09,0x9e,0x44,0x4c,0x92,0x6e,0x6e,0x9b,0xfd,0xbc,0x43,0xc0,0x52,0x86,
+  0xc9,0xdf,0x12,0x31,0x73,0xd4,0x0d,0x8c,0xb3,0xe3,0x67,0x06,0x7c,0x0c,0x7e,0x69,
+  0xb4,0xca,0x4b,0x94,0x97,0x04,0x2c,0x58,0xfe,0x99,0xf8,0xfd,0x72,0xf4,0xfa,0x86,
+  0xeb,0x39,0x22,0x3f,0x25,0x89,0x5c,0x08,0x17,0x39,0xe9,0xbd,0x51,0xda,0x79,0xed,
+  0x61,0x0b,0xa1,0x7d,0x86,0x42,0xbb,0x35,0x6f,0x69,0xf9,0x8c,0x8e,0xff,0xfe,0x0c,
+  0xd0,0x3f,0xd9,0xec,0xec,0xed,0x25,0x25,0x25,0x81,0xfc,0xee,0xdd,0x7f,0x40,0xea,
+  0xf0,0x51,0xe9,0x13,0x67,0x4e,0x9e,0xbd,0x70,0xe6,0xdc,0x85,0x53,0x67,0x2f,0xc8,
+  0xc8,0x9e,0xfa,0x51,0xea,0xf0,0xee,0x3d,0x3f,0x00,0x3a,0x03,0x05,0xde,0xb0,0x71,
+  0x03,0x56,0x0b,0x7a,0xc5,0xb2,0x65,0xcb,0xf0,0x44,0xe0,0x45,0x1f,0x2d,0xc2,0x69,
+  0xc8,0x1f,0x51,0x61,0x7d,0xf2,0xf1,0x62,0x07,0x27,0xc7,0x27,0xae,0xee,0xa6,0x56,
+  0xac,0xe8,0xd8,0xc4,0xea,0x9a,0xe7,0x08,0x7f,0xa9,0x63,0x98,0x55,0x35,0xd5,0xc2,
+  0x42,0xf3,0xca,0x12,0x82,0xb1,0xeb,0xfc,0xc5,0x0b,0x31,0x71,0x71,0x06,0xc6,0x66,
+  0x7e,0x81,0xa1,0x45,0x25,0x65,0xdd,0xbd,0x83,0x93,0xef,0x28,0x1f,0x64,0x40,0xbd,
+  0xb3,0xe7,0xce,0xcf,0xd9,0xec,0xdd,0xfb,0x0f,0x5e,0xb4,0xb6,0xb5,0xbd,0xec,0x84,
+  0xa7,0x9e,0x4a,0xda,0x04,0x03,0x0f,0xa0,0xcc,0xe0,0xd0,0x48,0x7d,0x43,0x73,0x36,
+  0xbb,0x30,0x38,0x2c,0xc2,0xc6,0xd1,0x0d,0x30,0x51,0x43,0x5b,0x47,0x49,0x4d,0x83,
+  0xa1,0xac,0xca,0x50,0x52,0x61,0x28,0x3f,0x52,0x56,0xd3,0x50,0xd7,0xd4,0xd1,0xd5,
+  0x37,0xb1,0x64,0x39,0xba,0x79,0xfa,0x26,0x26,0xa5,0x15,0x3d,0xad,0x6a,0xef,0x84,
+  0x61,0xf9,0x15,0x90,0xd6,0x5f,0x8f,0xcc,0x80,0x6b,0x01,0x81,0x41,0xcb,0xa9,0x69,
+  0x08,0xd8,0xb9,0x73,0xe7,0xe3,0x12,0x13,0x0d,0x4d,0x2c,0x7c,0xfc,0x82,0x39,0xc5,
+  0xe5,0xbd,0x7d,0x40,0xf9,0xa9,0x83,0x9c,0xff,0x41,0x0c,0xbd,0xa9,0xa5,0x8d,0x9d,
+  0xc7,0xf1,0xf1,0x0b,0xb1,0x66,0xd9,0x1b,0x1a,0x33,0x75,0xf4,0x8c,0x90,0xe9,0x1b,
+  0x3d,0xd6,0x35,0x84,0xff,0xb0,0xac,0x6b,0x60,0x0c,0x0b,0xa6,0x16,0xd6,0xc0,0x80,
+  0xd7,0xac,0x5e,0xc3,0x77,0xed,0x3e,0xc9,0xc8,0xca,0xd1,0x33,0x62,0x6a,0x6a,0xeb,
+  0xda,0xda,0x3b,0x85,0x47,0xc6,0x3e,0x2d,0xab,0x6e,0xef,0xe8,0x7e,0x3d,0x41,0xa3,
+  0xa0,0x03,0xc4,0x9f,0x04,0xd7,0xa5,0xee,0x79,0x63,0x4a,0x6a,0x96,0x8f,0x5f,0x90,
+  0x95,0x8d,0xa3,0x31,0xd3,0x4c,0x47,0xdf,0x10,0x76,0x87,0x4c,0x47,0x9f,0x58,0xe0,
+  0xae,0x6a,0xe3,0x5b,0x74,0x0c,0x74,0xf4,0xd0,0x16,0x33,0x0b,0x56,0x5e,0x21,0x67,
+  0xd9,0x67,0xbf,0x2d,0x33,0x6b,0xfe,0x76,0xea,0xf4,0xa9,0x84,0xa4,0x24,0x03,0x23,
+  0xa6,0xaf,0x7f,0x70,0x7e,0x61,0x71,0x6f,0x5f,0x3f,0x4d,0x5a,0x19,0xf8,0x6c,0x77,
+  0xee,0xde,0x9f,0x67,0xcb,0xab,0x56,0xad,0x09,0x8f,0x8c,0x62,0x9a,0x9a,0xb9,0xb8,
+  0x7a,0xa4,0xa4,0x67,0xc3,0x5d,0x44,0xcf,0x7f,0x63,0xe3,0x63,0xf9,0x67,0xdb,0x67,
+  0x35,0x1b,0x3b,0x7b,0x0f,0x6f,0x1f,0x4b,0x96,0x7d,0x64,0x74,0xc2,0xb3,0x67,0x80,
+  0xbf,0x74,0xd9,0x52,0xef,0xde,0x4d,0xc1,0x3d,0x59,0xfb,0xac,0x21,0x21,0x29,0x1d,
+  0x9c,0x1c,0xa6,0xb9,0x95,0x1e,0x5c,0x59,0xee,0xe5,0xc6,0x0d,0xce,0xb0,0x2e,0x76,
+  0x9e,0xf9,0xb7,0x33,0xcd,0x2d,0x53,0xd2,0xd2,0xd6,0xaf,0xa3,0x9c,0x5d,0x15,0x14,
+  0x10,0x0c,0x08,0x0a,0xb2,0xb0,0xb6,0xb5,0xb2,0x73,0x48,0x48,0x4a,0x79,0x86,0x92,
+  0xc1,0xe9,0xf8,0x6f,0x43,0x63,0x33,0xdc,0x3c,0x34,0xc7,0x75,0xfa,0xcc,0xe9,0xea,
+  0xba,0xba,0xcc,0xec,0xdc,0x17,0x2d,0x2f,0xc7,0xc6,0x29,0x53,0x99,0xc0,0x5e,0x4f,
+  0x4c,0xc0,0x69,0x34,0x61,0x9a,0xbe,0xa7,0xfb,0x81,0xca,0x3e,0x5c,0x24,0x20,0x76,
+  0xbf,0x14,0xc1,0x87,0x7a,0x37,0x46,0xe2,0x78,0xc4,0x73,0xc6,0x2a,0x4f,0x13,0x85,
+  0x2d,0xcc,0x90,0x54,0x71,0x67,0x69,0x31,0xb5,0x12,0x57,0x8f,0x34,0xf3,0xb7,0x38,
+  0x68,0x6a,0x63,0xb3,0xba,0xe4,0x74,0x30,0x26,0xd9,0xc2,0xf5,0xc6,0xd0,0x26,0x86,
+  0xb0,0x44,0x3e,0x11,0x2e,0xca,0xe2,0xed,0x08,0x6b,0x04,0x7e,0xb2,0x59,0x8b,0x97,
+  0x08,0xcc,0xe5,0xa1,0xfd,0xd3,0xf8,0x3b,0x85,0x2a,0x8c,0xb7,0x91,0xaf,0x1b,0xf8,
+  0x8e,0x50,0x40,0x5b,0x0b,0xa7,0xd2,0x7c,0x82,0x2b,0x24,0xb5,0xea,0xe2,0xe2,0xfe,
+  0xb4,0x5e,0x91,0x34,0x79,0x66,0x27,0x7f,0xad,0x37,0xe3,0xe6,0x28,0x11,0x05,0xb5,
+  0x80,0x05,0xab,0xb4,0xa1,0xda,0xd1,0x8a,0x75,0x62,0xf7,0x9e,0x22,0x16,0x7c,0x3d,
+  0x47,0xf4,0xa7,0x04,0xd1,0x73,0x21,0x22,0xb2,0xde,0x48,0x8b,0x75,0xd0,0x4c,0x78,
+  0x9f,0xce,0xce,0x33,0x16,0xd5,0x0d,0x9d,0x7f,0x2d,0xaa,0xce,0xd3,0xc6,0xc6,0xc7,
+  0x2e,0x5d,0xfe,0xe9,0xdb,0x6f,0xb7,0x01,0xc9,0x3d,0x24,0x75,0x44,0xf6,0xc4,0xa9,
+  0xb3,0xe7,0x2f,0x5f,0xbc,0x7c,0xfd,0xf2,0x95,0xab,0xe7,0x2f,0x5e,0x3d,0x7d,0xf6,
+  0xc2,0xd1,0x63,0xb2,0x7b,0xf7,0x1d,0xdc,0xb1,0xf3,0xbb,0x2d,0x5b,0xb6,0x88,0x88,
+  0x88,0xae,0x11,0x12,0x5e,0xbe,0xe2,0xf3,0x4f,0x3f,0xfd,0x74,0xe9,0xd2,0xa5,0x00,
+  0xc1,0x78,0x21,0x2c,0xdc,0xd0,0x4b,0x81,0xff,0xf7,0x83,0xdf,0x11,0x85,0x5e,0xb4,
+  0x70,0x91,0xb9,0x95,0x85,0x9b,0xbb,0x17,0x8c,0xab,0x51,0x31,0x89,0x55,0x35,0xcf,
+  0x87,0x47,0xb0,0x59,0x5a,0x8a,0x01,0xfc,0x79,0x53,0xd3,0xfa,0x79,0xab,0x2c,0xa4,
+  0x8f,0xc9,0xc4,0x27,0xc2,0x58,0x6a,0xea,0x1d,0x10,0x58,0x50,0x58,0xda,0xdd,0xdb,
+  0x4f,0xa3,0x7f,0x9e,0x9a,0xfa,0x45,0x4e,0xee,0x06,0x4d,0x6b,0x00,0xe8,0x5b,0xb6,
+  0x7c,0x5d,0xf3,0xac,0xbe,0xa1,0xe9,0x45,0x77,0x6f,0xdf,0xc4,0x1b,0x4a,0x85,0xc9,
+  0xe4,0xe4,0xbb,0x81,0xa1,0xd1,0xc6,0xe6,0xd6,0x8c,0xac,0x3c,0xff,0xc0,0x10,0x96,
+  0x9d,0x93,0xb9,0x95,0x8d,0xa5,0x35,0xb0,0x5d,0x7b,0x73,0x6b,0x1b,0x63,0x53,0x33,
+  0xed,0xc7,0x3a,0x00,0xc1,0xf2,0xf2,0x0c,0x05,0x05,0x65,0xc5,0x87,0x6a,0x6a,0x8f,
+  0x1e,0x03,0xbe,0x39,0xbb,0x78,0x44,0xc5,0x24,0x71,0x4a,0x2a,0x51,0x64,0xf2,0xf5,
+  0xeb,0x59,0x83,0x00,0x00,0x6d,0x8a,0x8a,0x0c,0x1a,0x25,0xaa,0xb4,0xb4,0x4c,0x72,
+  0x6a,0x1a,0x1c,0xb2,0x8f,0x6f,0x10,0xd0,0x9c,0xae,0x9e,0x01,0x1a,0x97,0x03,0x20,
+  0x1e,0x06,0xb7,0x86,0xa6,0x96,0xe4,0xd4,0x4c,0xd8,0xbb,0x8e,0xae,0x91,0x8a,0xaa,
+  0x86,0xbc,0x22,0x43,0xe1,0xa1,0x0a,0x32,0x45,0x15,0xee,0x02,0x6c,0x51,0x55,0xd7,
+  0xd0,0xc9,0x2b,0xe0,0x6c,0xf8,0x62,0x23,0xb9,0x2f,0xa0,0x30,0x89,0x29,0xc9,0xfa,
+  0x86,0x86,0x0c,0xa5,0x47,0x3a,0x7a,0x26,0xf6,0x4e,0x1e,0xf1,0x49,0x29,0x4f,0xcb,
+  0xab,0xdb,0xbb,0xfb,0x68,0x84,0x40,0xef,0xa6,0x7e,0x19,0x19,0x1d,0x6f,0x69,0x6b,
+  0x07,0xd0,0x0f,0x0e,0x8d,0x66,0xd9,0x38,0x3e,0xd6,0xd5,0x57,0x7a,0xa4,0xae,0xc0,
+  0x50,0x55,0x50,0x54,0x85,0x1d,0xc9,0x2b,0x30,0xd0,0xae,0x71,0x7b,0x88,0xb6,0xa0,
+  0x05,0x06,0xde,0x13,0x65,0x2d,0x6d,0xbd,0xfc,0x42,0x8e,0xb0,0xb0,0xf0,0x7b,0x1a,
+  0x57,0xa5,0xa4,0xa4,0x10,0xfe,0x1a,0x9a,0x7a,0x7a,0x07,0xe6,0xe6,0x17,0x77,0xf5,
+  0xf4,0x00,0xc8,0x52,0xb1,0x54,0x70,0x93,0x14,0x14,0x18,0xf3,0x6c,0x19,0x1c,0xa7,
+  0x90,0xf0,0x30,0x33,0x4b,0x6b,0x3b,0x27,0x57,0x20,0x89,0x2d,0x6d,0x08,0x7f,0x69,
+  0xf8,0x6f,0x6a,0x7a,0xfa,0x9c,0x61,0x76,0x4b,0x6b,0x6b,0x6f,0x7f,0x3f,0x4b,0x6b,
+  0x5b,0x70,0x7e,0x6a,0xea,0xea,0x07,0x87,0x87,0x69,0x6a,0x7a,0x80,0x87,0x39,0x34,
+  0x3c,0x52,0x5e,0x55,0x1b,0x11,0x9d,0x08,0xbe,0x16,0x78,0x83,0x0f,0x95,0xd4,0xb8,
+  0xe7,0x19,0x99,0x22,0x7e,0xaa,0xf9,0x0d,0xdb,0xae,0xa6,0xae,0x0d,0xcf,0x91,0xa8,
+  0x08,0x65,0xa5,0x91,0x25,0x8b,0x97,0x78,0x79,0x7b,0xb3,0x6c,0x1d,0x2d,0x6d,0x1c,
+  0x62,0x62,0x93,0x9f,0x3d,0x47,0xf8,0x4b,0xc3,0x7f,0xc1,0xc9,0x84,0x61,0x84,0xe6,
+  0x41,0xf3,0xf2,0xf2,0x29,0x2a,0x29,0xe5,0x14,0x97,0x75,0xf7,0xf4,0xd2,0x3d,0x68,
+  0xef,0xa6,0x80,0xf2,0xb7,0x77,0x76,0xec,0xdf,0x7f,0xe0,0x3d,0xdd,0x0f,0x34,0x26,
+  0x24,0x65,0x46,0x50,0x60,0x0c,0x71,0xbe,0xd2,0xea,0xc0,0x15,0x47,0xdc,0x40,0x31,
+  0x91,0x89,0xc3,0x9f,0x7f,0x84,0xf2,0x95,0x34,0x89,0x02,0x53,0x78,0x69,0xa9,0x4d,
+  0x5c,0x52,0x4c,0x84,0x67,0xb9,0xba,0x29,0xfe,0xa2,0x52,0xb8,0x86,0x0a,0x87,0x39,
+  0x7e,0x08,0x43,0xfc,0x54,0x83,0xa8,0xb0,0x81,0x7f,0x4a,0x56,0xde,0x40,0x1f,0x61,
+  0xf2,0x2a,0xee,0x84,0x2f,0x11,0x19,0xc6,0x65,0x57,0x5f,0x62,0x7a,0x30,0x42,0x5b,
+  0x85,0x61,0x25,0x29,0x03,0xc3,0x25,0x55,0xa4,0x86,0x8a,0xd7,0x25,0x74,0x20,0x1d,
+  0xc4,0x16,0xac,0xa2,0x17,0xbe,0x1d,0x7d,0x0d,0x0b,0x02,0x10,0x95,0xb5,0xb8,0x94,
+  0x16,0xdf,0x3b,0x4e,0x9f,0x79,0xac,0x9c,0x5b,0xfe,0x8b,0xa4,0xc3,0x78,0x92,0x32,
+  0x57,0x24,0x36,0x28,0x81,0x57,0x05,0xd1,0xc4,0xb3,0x93,0xa0,0xfd,0x3e,0x4c,0x1a,
+  0xdd,0x47,0x54,0xc5,0x54,0x69,0x15,0xc3,0x21,0x58,0xbe,0x56,0xfc,0x5e,0x09,0xaa,
+  0x14,0x2d,0x97,0x29,0x72,0x39,0x4e,0xe4,0x6c,0xd0,0x46,0x59,0xb7,0xb5,0x87,0x59,
+  0x42,0x07,0x4d,0xd7,0x1f,0x7a,0xec,0x1b,0x9d,0xff,0x97,0x63,0xeb,0x7c,0xac,0xb2,
+  0xa6,0x66,0xef,0xbe,0xfd,0x00,0xaf,0x7b,0xf7,0x1f,0x94,0x3e,0x2e,0x0b,0xb4,0xf7,
+  0xc2,0xd5,0x1b,0x97,0xaf,0xdf,0xbd,0x70,0xe3,0xee,0xb5,0xeb,0xb7,0xce,0x5f,0xbc,
+  0x22,0x23,0x7b,0xf2,0x90,0xd4,0xd1,0x9d,0xdf,0x7d,0x2f,0x29,0xb9,0x55,0x42,0x42,
+  0x42,0x48,0x58,0x98,0x98,0x02,0x86,0xbf,0xc5,0x4b,0x70,0xfe,0xfb,0x07,0xf3,0x7f,
+  0xa1,0x05,0x13,0x53,0xa6,0xa7,0x37,0x52,0x29,0x47,0x44,0xc6,0x55,0x54,0xd6,0x0d,
+  0x0c,0x8d,0x00,0xf4,0x50,0xc5,0x75,0x3b,0x3a,0x3b,0xc5,0xc5,0xc4,0xe7,0xd9,0xf8,
+  0x81,0x83,0x07,0x92,0x52,0x52,0x8d,0x4c,0xcc,0xbd,0x7c,0x02,0x80,0xcb,0x74,0xf5,
+  0xf4,0xd3,0xa7,0x25,0xca,0x2b,0x2a,0xd0,0xb4,0x26,0xb8,0x54,0xd0,0xc9,0xf9,0x49,
+  0x7d,0xc3,0x8b,0xe7,0x8d,0x2d,0x43,0x23,0x23,0x54,0xba,0x62,0x24,0xb8,0x1a,0x7f,
+  0xd5,0xde,0xd1,0xc9,0x29,0x2a,0x0b,0x0e,0x0d,0x0b,0x0c,0x0e,0xcf,0xce,0xcd,0x2f,
+  0x29,0x2d,0xcd,0xc8,0xcc,0x0c,0x0c,0x0e,0xf2,0x0f,0x0c,0x8c,0x4f,0x48,0x02,0x04,
+  0xc9,0x64,0x67,0x3b,0x38,0x3a,0x30,0x94,0x54,0xef,0xdd,0x93,0x07,0xc4,0x91,0x57,
+  0x06,0x9e,0x61,0x02,0x20,0x18,0x1b,0x9f,0x5a,0x5a,0x5e,0x0d,0x5d,0x7d,0xfd,0x66,
+  0xf6,0x3c,0xe8,0xaa,0xea,0xda,0xad,0x5b,0xbf,0xa5,0xea,0xe4,0x8f,0x52,0x87,0x53,
+  0xd2,0x32,0xf4,0x0c,0x8c,0xbc,0x7d,0x03,0xf3,0x0b,0x4b,0x3a,0xbb,0x7b,0xdf,0x4c,
+  0x50,0xcf,0xff,0x62,0x13,0x82,0x00,0xf7,0x45,0x25,0x65,0x11,0x91,0xb1,0xce,0x6e,
+  0xee,0x36,0xf6,0x8e,0xd6,0x2c,0x9b,0x59,0x0c,0x15,0xb3,0x74,0x2a,0x2d,0xaf,0x12,
+  0x9d,0x7e,0xf2,0x63,0xe2,0x63,0x8d,0x4c,0x98,0x0f,0xe4,0x15,0x95,0x55,0xd5,0xe1,
+  0x3c,0xbb,0xb8,0x79,0x26,0xa4,0x64,0x55,0x54,0xd7,0xf7,0x80,0x7f,0x42,0x21,0xee,
+  0x85,0xf3,0x0c,0x2e,0xc1,0xe8,0xd8,0xd8,0x8b,0xd6,0xd6,0x92,0xb2,0xf2,0xe4,0x94,
+  0xf4,0xc0,0xe0,0x10,0x77,0x6f,0x3f,0xac,0xf8,0xa1,0x9b,0x83,0x93,0x8b,0xa3,0x93,
+  0x2b,0x98,0x83,0xa3,0xb3,0xa3,0x93,0x8b,0x03,0x32,0xb4,0x8c,0x0a,0x36,0x3e,0x41,
+  0xab,0x1e,0x5e,0xde,0xd5,0xb5,0x35,0x5f,0x7c,0xb1,0xe1,0x3d,0x0d,0xaa,0xff,0xda,
+  0xf3,0x43,0x62,0x72,0xb2,0x91,0xb1,0xa9,0xa7,0x4f,0x00,0x3b,0xaf,0x18,0xae,0x23,
+  0x4d,0x96,0x2e,0x5c,0x20,0x2d,0xad,0xc7,0xf3,0x6c,0x19,0xee,0x9f,0x80,0xa0,0x60,
+  0x4b,0x96,0xad,0xad,0x83,0x4b,0x42,0x62,0x3a,0x78,0x71,0x63,0xe3,0x74,0xf8,0x9b,
+  0x93,0x97,0xb7,0x64,0x2e,0xa9,0xbf,0x9e,0xb1,0x91,0x7f,0x50,0xa8,0xb9,0x85,0x55,
+  0x68,0x78,0x4c,0x45,0x35,0x26,0x77,0x9f,0xfa,0x85,0x0a,0xf8,0xa0,0xb7,0xe0,0x17,
+  0xd5,0x37,0x34,0xe6,0xe4,0xe4,0x05,0x06,0x87,0x3a,0x3a,0xbb,0xb0,0x6c,0x1d,0x66,
+  0x5c,0xe5,0x19,0xd7,0x1d,0x2b,0x96,0xc9,0xb2,0x73,0xb0,0xcf,0xce,0x61,0x7f,0xf5,
+  0xe5,0x16,0xaa,0x6e,0x2c,0xfe,0x78,0xf1,0x13,0x67,0xb8,0x76,0xce,0x16,0x96,0x36,
+  0x51,0x31,0x09,0x40,0xb1,0x91,0x62,0x8a,0x1a,0x7f,0xbb,0x7b,0x7b,0x57,0x2c,0xa7,
+  0x0c,0xe3,0xc0,0x47,0x15,0x35,0xd5,0xd9,0xec,0xc2,0xea,0xda,0x06,0x24,0x20,0xa4,
+  0xf6,0x28,0x26,0x27,0xa7,0x60,0x47,0xe9,0x99,0x99,0xab,0x56,0xae,0x7e,0x4f,0xf7,
+  0x03,0x8d,0x2d,0xdb,0x24,0x2d,0xae,0xdc,0x4c,0xe2,0x2f,0x0f,0x19,0x49,0xe9,0xd1,
+  0x74,0x32,0x3b,0x7d,0xfa,0x75,0x96,0x1a,0x1d,0x98,0x44,0xaa,0x87,0xff,0x0b,0xe4,
+  0xa7,0xf8,0x6f,0xb9,0xd3,0xc1,0x03,0x3c,0x14,0xe3,0x56,0xa0,0xe2,0xb6,0xd6,0x4b,
+  0x4e,0x07,0xe3,0x22,0x28,0xfe,0xd9,0xe1,0x19,0xb3,0xb4,0xf8,0x97,0x31,0xc0,0x1d,
+  0xc0,0xe5,0x58,0x64,0x57,0x91,0x00,0x5b,0xa3,0x9b,0x8b,0xbf,0xdd,0xe4,0x4f,0x70,
+  0x74,0xc6,0x89,0x33,0x31,0xff,0x8b,0xc1,0x3d,0xde,0x1a,0xb7,0x7c,0xe5,0x8c,0xe3,
+  0x25,0x96,0xc9,0x39,0x6b,0xcc,0xb5,0xe8,0xe5,0x86,0xd6,0x09,0xa5,0x16,0x7f,0x55,
+  0x2e,0x82,0x98,0xe3,0xc5,0xb2,0xe0,0xb7,0xfc,0xaf,0x81,0x50,0x6d,0x17,0x53,0x6a,
+  0x14,0x51,0xac,0x17,0x53,0xa8,0x11,0xfb,0x77,0x89,0xc4,0xad,0x5c,0x54,0x1a,0xeb,
+  0x62,0x84,0xc8,0x29,0xbf,0x0d,0xd2,0x2e,0x08,0x82,0xf7,0xe9,0xdd,0x35,0x08,0xfd,
+  0xfb,0xbf,0x14,0x09,0xee,0x6a,0x37,0x0f,0x8f,0xed,0x3b,0x76,0x00,0xf9,0x3d,0x72,
+  0x54,0x46,0xfa,0xe4,0xc5,0x2b,0x57,0x6f,0xdc,0xbc,0x73,0xef,0xfe,0x7d,0xf9,0x7b,
+  0xf7,0x15,0x7f,0xba,0xfd,0xe0,0xda,0xf5,0xdb,0x67,0xce,0x5e,0x3a,0x7c,0xe4,0xe8,
+  0x9e,0xbd,0xfb,0xb6,0x6d,0xdb,0x2e,0x26,0xb1,0x19,0x06,0x3d,0xfc,0x75,0x48,0x4b,
+  0x05,0x04,0x05,0x96,0x08,0xe0,0x89,0x48,0x78,0x16,0x30,0x1e,0x82,0xfe,0x1d,0xfc,
+  0x17,0x38,0x94,0x86,0x86,0xa6,0xaf,0x7f,0xa8,0x89,0xb1,0x55,0x78,0x44,0x6c,0x59,
+  0x45,0xf5,0xc0,0xe0,0x30,0x8d,0x64,0xa8,0xa7,0xaf,0xff,0xab,0x2d,0x94,0xe3,0xc0,
+  0x0c,0xdb,0xf5,0xcf,0xdd,0xa9,0x19,0xe9,0x46,0xc6,0x4c,0x2f,0x5f,0x18,0x4b,0x8b,
+  0x3a,0x3a,0x7b,0x68,0xc6,0x52,0x30,0xad,0xc7,0x74,0x45,0xf6,0xce,0x9c,0x3d,0x5b,
+  0xff,0xbc,0x11,0xa0,0xaa,0xbd,0xa3,0x6b,0x62,0x62,0xf6,0x84,0x5f,0xb8,0xee,0xe0,
+  0xae,0xf7,0xf6,0x0d,0x94,0x57,0xd4,0xa4,0x67,0x66,0x97,0x95,0x57,0xa5,0xa5,0x67,
+  0xfc,0xfb,0xde,0x7d,0x11,0x51,0x31,0x72,0xc2,0x0b,0xce,0xd5,0xca,0x95,0xab,0x8e,
+  0x4a,0xcb,0xf8,0xfa,0x83,0x57,0x50,0xe8,0xec,0xe2,0xaa,0xf8,0x50,0x49,0x5e,0xfe,
+  0x21,0x43,0x59,0x43,0xcf,0xc0,0xc4,0xc1,0xd9,0x1d,0xc8,0x51,0x55,0xcd,0xf3,0xbe,
+  0xc1,0xe1,0x59,0xa9,0x2b,0x5c,0x38,0x00,0x2c,0xaa,0xe9,0xb3,0x5d,0xbb,0x76,0xa5,
+  0x67,0x66,0xe9,0x18,0x18,0xbb,0x79,0xfa,0xe7,0xe6,0x17,0x75,0x76,0x53,0xe2,0x20,
+  0xd6,0xdb,0x9f,0x39,0xc5,0xc5,0x56,0x58,0x89,0x6c,0x64,0xb6,0x68,0xf8,0xb5,0xb1,
+  0xb5,0x03,0x83,0x55,0x7c,0x04,0xb6,0xb5,0xb3,0x27,0x3f,0x35,0x66,0x1a,0x7f,0x36,
+  0xbd,0xdc,0xb1,0xa1,0xb1,0x59,0x42,0x62,0xb2,0x92,0x0a,0x90,0x56,0x25,0x25,0x15,
+  0x75,0x23,0x53,0x0b,0x00,0xc8,0x94,0xb4,0xac,0xea,0xda,0xfa,0x9e,0xbe,0x81,0x5f,
+  0x97,0x32,0x9b,0x9c,0x7a,0x07,0x27,0xc4,0xd8,0xc4,0x4c,0xdf,0xc0,0xd0,0xc8,0xc8,
+  0x08,0xfe,0xeb,0xe9,0x1b,0xe8,0xe9,0x19,0xc0,0x7f,0x58,0x26,0x56,0xf5,0x0d,0x75,
+  0xf5,0xf4,0xf5,0xf5,0x61,0x19,0x5f,0x45,0x06,0x5b,0x60,0x15,0xbe,0x00,0x0b,0x6a,
+  0x8f,0xd4,0x97,0xbe,0xb7,0x77,0x55,0xec,0xd8,0xbe,0x33,0x29,0x35,0xd5,0xc0,0x98,
+  0xe9,0xee,0xe9,0x97,0x99,0x5b,0xd0,0xde,0xd9,0x47,0x13,0xc0,0x87,0xcb,0xcd,0x34,
+  0xb3,0x98,0x67,0xcb,0x8b,0x3f,0x59,0xec,0xee,0xee,0x6e,0x63,0xe7,0x60,0x63,0xe7,
+  0x1c,0x13,0x97,0xd8,0xd0,0xd4,0x06,0x4e,0x08,0x4d,0xb8,0xb8,0xb8,0xa4,0x54,0x50,
+  0x70,0x0e,0xa9,0xbf,0x9a,0x9a,0x7a,0x48,0x68,0x98,0xb9,0xa5,0x4d,0x70,0x68,0x54,
+  0x69,0x65,0x2d,0xbd,0xdc,0x6e,0xfc,0xf5,0xab,0xc8,0xa8,0x18,0xfc,0x2a,0xdb,0xd9,
+  0x3b,0xcc,0x7a,0xb9,0x61,0xbb,0x35,0x76,0xb9,0xc9,0x05,0x1b,0x54,0x95,0xdd,0x41,
+  0x45,0x55,0x75,0x05,0xb5,0xee,0x62,0xe1,0x87,0x0b,0xcd,0x2d,0x2c,0x5c,0xdd,0x3d,
+  0xcd,0xac,0xec,0xa2,0x63,0x12,0xe0,0xea,0x0f,0x0d,0x8f,0xd2,0x8c,0x81,0x83,0xc3,
+  0x23,0x42,0x42,0xeb,0x66,0x6d,0x0a,0xc6,0x90,0xab,0xd7,0xe4,0xea,0x1b,0x9a,0xb2,
+  0x73,0x0a,0x5e,0xb6,0x77,0x4e,0x4c,0x50,0x16,0x50,0x85,0x07,0x10,0xe5,0xa6,0xbd,
+  0x9e,0x78,0x20,0xaf,0xf0,0x47,0x28,0xc0,0xef,0xb6,0x8f,0x96,0xae,0x5b,0x2f,0x97,
+  0x81,0x15,0x91,0x20,0xf0,0x51,0x02,0x43,0x2b,0xa2,0xb6,0x24,0xca,0x81,0xc5,0xca,
+  0x43,0x91,0xa0,0x86,0xe9,0x91,0x48,0x49,0x15,0x2e,0x43,0xc2,0x91,0x8e,0x20,0x80,
+  0x5c,0x39,0xd6,0xaf,0xeb,0x5b,0x12,0x45,0x1d,0x79,0xf5,0xac,0xfa,0x71,0xc1,0x33,
+  0x9f,0x68,0x8a,0xc0,0x38,0x6e,0x53,0x3c,0xe0,0x03,0xd0,0xc4,0xeb,0x6e,0x21,0x1e,
+  0xaa,0x4e,0x56,0x69,0xe6,0x17,0x6b,0x71,0x2b,0x71,0x11,0x90,0x3a,0x30,0xcd,0x9d,
+  0xd0,0xe4,0x95,0x0a,0xe1,0x09,0xae,0xf0,0x2a,0x5b,0x98,0xbe,0x0b,0x8b,0x6c,0xf7,
+  0x92,0x01,0x64,0xb2,0xfc,0x26,0xfc,0xc7,0xf6,0x4b,0xb4,0x43,0xc8,0xcf,0x88,0xca,
+  0x1e,0xdd,0x44,0xbc,0x9d,0xcb,0x85,0xb1,0x99,0xdf,0x41,0xd2,0xc1,0xe0,0x75,0x49,
+  0xa3,0x0b,0x97,0x63,0xf1,0xde,0x13,0xa1,0xda,0x86,0x0a,0x64,0x29,0xd4,0x8b,0x3e,
+  0xa8,0x16,0xbb,0x5b,0x2c,0x7a,0x23,0x57,0xf4,0xa7,0x24,0xf4,0xb2,0xc2,0x93,0x5e,
+  0x1b,0xa4,0x6d,0x84,0x0e,0x99,0xed,0xbc,0x68,0xd3,0xd2,0xde,0xf7,0x97,0x23,0x2c,
+  0xbd,0x8d,0x8e,0x8f,0x3d,0x90,0x7f,0xb8,0x7d,0xfb,0x8e,0x3d,0x7b,0xf7,0xcb,0x1c,
+  0x3f,0x71,0xe1,0xd2,0xb5,0xeb,0x37,0xef,0x3c,0x50,0x50,0x66,0x28,0x3d,0x52,0x64,
+  0xa8,0xdd,0x97,0x57,0xba,0x79,0xfb,0xdf,0x17,0x2e,0x5d,0x39,0x2e,0x7b,0xf2,0x87,
+  0x7d,0xfb,0xb7,0x6d,0xdf,0xb1,0xf9,0xab,0x2d,0x1b,0x36,0x6c,0xc4,0xf1,0x77,0xd9,
+  0xb2,0xcf,0x96,0x2c,0x16,0xf8,0x78,0xd1,0xc7,0x40,0x81,0x3f,0x5c,0x80,0xc0,0x17,
+  0x97,0x60,0xfd,0x0e,0x15,0x16,0xfc,0x56,0x91,0xa1,0x18,0x18,0x12,0x66,0x68,0x6a,
+  0x15,0x16,0x11,0x55,0x52,0x5a,0xd9,0x0f,0x1e,0x2f,0xf5,0x18,0x32,0x30,0x34,0x04,
+  0x7d,0x9e,0x67,0xe3,0x5b,0xbf,0xd9,0x96,0x9a,0x9e,0xc1,0x64,0x5a,0x78,0x7a,0xfb,
+  0x67,0xb3,0x0b,0x00,0x7f,0x27,0xde,0xd0,0x65,0x7c,0x00,0xeb,0x59,0xf0,0xc1,0xec,
+  0x2e,0x84,0xe0,0xd2,0x4f,0x43,0xc2,0x42,0x4b,0xcb,0x2b,0x2b,0xab,0xeb,0xfa,0xfa,
+  0x07,0xa9,0x92,0x7a,0xc0,0xe7,0x1f,0x7f,0xf5,0xaa,0xe9,0x45,0x6b,0x79,0x65,0x75,
+  0x4d,0x5d,0x9d,0xd6,0x63,0x6d,0x51,0x51,0x51,0xaa,0x64,0x19,0xc0,0x32,0x59,0xd9,
+  0x13,0x71,0x09,0x89,0xc1,0x21,0x61,0xaa,0x6a,0x8f,0x1e,0x28,0x30,0x54,0xd4,0x34,
+  0x0d,0x99,0x2c,0x2f,0xbf,0x20,0x76,0x5e,0x7e,0x6b,0x7b,0x27,0xd5,0xfc,0xe0,0xf0,
+  0xe8,0xc8,0xce,0x9d,0xdf,0xcd,0x7a,0xb6,0xc1,0x53,0x4a,0xcb,0x4c,0x07,0x1c,0x77,
+  0x73,0xf7,0xc9,0x61,0x17,0xb5,0x77,0x74,0xd3,0x14,0x2e,0x98,0xfa,0x79,0xca,0xca,
+  0xca,0x1a,0x8f,0x63,0x80,0x91,0x0b,0xfc,0x36,0x63,0xe3,0x8c,0xdd,0x09,0x09,0x09,
+  0x39,0xbb,0xba,0x87,0x84,0x85,0x33,0x18,0xca,0x00,0xc1,0xaa,0xea,0x9a,0xa6,0xe6,
+  0x56,0x3e,0xbe,0x81,0x59,0xd9,0x05,0x75,0xf5,0x4d,0x03,0x43,0x23,0x33,0xd0,0x1f,
+  0xe0,0xb8,0xbc,0xa2,0x6a,0xc7,0x8e,0xef,0x50,0x15,0x71,0xac,0x8a,0x1a,0x76,0xff,
+  0xa0,0xff,0xb0,0x4c,0xac,0x2e,0x58,0x88,0x3e,0xe2,0xaa,0xfb,0xf0,0xff,0xc8,0xc7,
+  0x5b,0x80,0x7d,0x81,0xeb,0xec,0xbd,0x27,0xdb,0x2a,0xf9,0x4d,0x7a,0x46,0xa6,0x31,
+  0xd3,0xdc,0xcd,0xc3,0x37,0x9b,0x9d,0xd7,0xde,0x31,0x47,0x96,0xae,0xe3,0x13,0xa7,
+  0x79,0xb6,0x0c,0x67,0x12,0xbd,0x0b,0xe3,0x89,0xab,0x8d,0xc3,0x93,0xd8,0xf8,0xe4,
+  0xe7,0x8d,0x2f,0x30,0x91,0x12,0x25,0xfe,0x56,0xd7,0x3e,0x5b,0xbd,0x6a,0x0e,0x5a,
+  0x77,0xff,0x81,0x7c,0x64,0x74,0x8c,0x99,0x85,0x55,0x70,0x68,0x64,0x69,0x79,0x55,
+  0xff,0xc0,0x20,0x92,0x0a,0x53,0x34,0xd8,0x37,0xd0,0x2f,0x23,0x73,0x9c,0xfe,0x72,
+  0x53,0x5d,0x77,0xfa,0x84,0x2f,0xb8,0x22,0xe0,0x30,0xf9,0xf8,0x07,0x98,0x5a,0x58,
+  0x47,0x44,0xc6,0x56,0x54,0xd5,0x0d,0x0e,0xcf,0xee,0x3d,0xe2,0xf6,0xfa,0xcd,0x1b,
+  0x31,0x8a,0x28,0x16,0x3c,0x68,0xbe,0x7e,0xfe,0x85,0x9c,0xe2,0xa2,0x92,0xf2,0xae,
+  0x9e,0x01,0x9a,0x84,0x85,0x29,0x34,0x91,0xf1,0x0a,0xdc,0xbc,0x4d,0x73,0xbd,0xa8,
+  0xe2,0x3d,0xd9,0x82,0x05,0x8b,0x84,0x65,0x9d,0xc5,0xb1,0x54,0x1a,0x09,0x0d,0x22,
+  0x48,0x8b,0xea,0x41,0x91,0x68,0xa5,0xd1,0x0b,0xab,0x78,0x02,0x2c,0x1f,0x7a,0x12,
+  0x88,0x83,0x2b,0x9d,0xd0,0x4b,0x1c,0x90,0x8c,0x8a,0x40,0x67,0x5c,0x8e,0x85,0x89,
+  0xb5,0x7a,0x79,0x60,0xad,0xc5,0x95,0x22,0xe3,0xca,0x2b,0x3e,0x32,0xbb,0x49,0xab,
+  0x0f,0x4f,0xbc,0x25,0xf3,0x8f,0x88,0xce,0x68,0xf1,0xe4,0x58,0x58,0xd0,0x9b,0xab,
+  0x40,0xd6,0xe2,0xbe,0x3d,0x41,0xb3,0x03,0x2f,0xae,0xc5,0x1f,0xac,0x86,0xae,0x4a,
+  0x68,0x12,0x99,0x4d,0x78,0x08,0x9d,0xac,0x58,0x85,0xff,0x56,0x9c,0x1b,0x97,0xc6,
+  0x8f,0x85,0x54,0x88,0x4d,0xd3,0x63,0x13,0x9d,0xec,0x27,0xdd,0x09,0x7e,0xa6,0xcc,
+  0xcf,0xfd,0xc5,0x79,0x51,0x6e,0x0c,0x9d,0x31,0xfe,0x8b,0x52,0x9b,0x35,0xb0,0x97,
+  0x43,0x61,0xbc,0x1e,0x8f,0xa8,0x4f,0xab,0x91,0x85,0x2a,0x45,0x37,0x8b,0x32,0x1a,
+  0x44,0x15,0x6a,0xc5,0xee,0x96,0x88,0xdf,0xe5,0x88,0x5e,0x4b,0x17,0xbd,0x1c,0x2b,
+  0x72,0x3a,0x70,0xa3,0xac,0xdb,0xba,0xc3,0x36,0x62,0xc7,0x2c,0xa2,0x32,0x6b,0xfe,
+  0xe6,0xb5,0xb0,0x1a,0x9a,0x9a,0xf6,0x1f,0x38,0xf8,0xdd,0xf7,0xff,0x3c,0x24,0x75,
+  0xe4,0xd4,0xd9,0xf3,0x57,0xe4,0x6e,0xde,0x07,0x0a,0xa3,0xa6,0xfe,0x48,0x43,0x4b,
+  0x49,0x53,0x17,0x16,0xe4,0x15,0x19,0x57,0xe4,0x6e,0x9d,0x3c,0x75,0xee,0x47,0xa9,
+  0xc3,0xdf,0xef,0xda,0x2d,0x29,0x29,0x29,0x26,0x2e,0x2e,0xbc,0x76,0xed,0xe7,0x2b,
+  0xd7,0xa0,0x42,0x1c,0xd8,0x14,0x30,0x5e,0x88,0x03,0xe5,0x02,0x7f,0x40,0xbc,0x11,
+  0xe9,0xb7,0x8e,0x8d,0xe0,0xee,0xde,0xbe,0x73,0x27,0x22,0x3a,0xd2,0x88,0x69,0x16,
+  0x14,0x1c,0x59,0xfc,0xb4,0x1c,0xd0,0x8d,0xe6,0xc9,0x1d,0x7b,0x35,0xbe,0x67,0xcf,
+  0x0f,0xf3,0x6c,0x1c,0x1e,0xcc,0xb4,0xac,0x4c,0x96,0x9d,0x93,0x6f,0x40,0x48,0x7e,
+  0x61,0x71,0x67,0x57,0xef,0x6b,0xea,0xf8,0x33,0x18,0x30,0x82,0x59,0xfb,0x0f,0x48,
+  0x77,0xe4,0xa8,0x74,0x45,0x55,0x4d,0x46,0x56,0xce,0xf3,0xc6,0x96,0xd1,0xb1,0x71,
+  0xaa,0x9c,0xd0,0xb7,0x93,0xef,0xfa,0xfa,0x87,0x1a,0x9b,0xdb,0xaa,0x6a,0xea,0xae,
+  0xca,0xdd,0x98,0xf3,0x6c,0x40,0xcb,0x1b,0xbe,0xd8,0xe0,0xe2,0xea,0x16,0x9f,0x98,
+  0xc8,0x50,0x56,0x91,0x57,0x78,0xa8,0xa9,0xad,0x6b,0x67,0xff,0x24,0x22,0x2a,0xae,
+  0xaa,0xf6,0x19,0x8c,0x2d,0x54,0x3b,0x02,0xd4,0xe3,0x4f,0x05,0x22,0xed,0xeb,0x7f,
+  0x48,0x66,0xb3,0xd9,0xba,0x86,0x86,0xce,0x6e,0xde,0x59,0xec,0xfc,0xb6,0xf6,0xae,
+  0x57,0xd4,0x49,0xa6,0xc0,0x2c,0x1c,0x9d,0x5c,0xfe,0xe0,0x28,0xb4,0x7e,0xdd,0x17,
+  0x61,0x91,0x51,0xde,0xbe,0x01,0x8a,0x8a,0x0f,0x15,0x14,0x14,0xd5,0x35,0x1f,0x9b,
+  0x99,0xb3,0xfc,0x83,0x42,0xb3,0x72,0x72,0x1b,0x9b,0x5f,0x0e,0x0d,0x8f,0xbc,0xc3,
+  0x0a,0x73,0xf2,0xef,0x37,0x2d,0x33,0x6b,0xf3,0x97,0x7f,0xcd,0x98,0x39,0xa7,0x6d,
+  0x96,0xd8,0x9c,0x9a,0x96,0xce,0xb2,0x75,0xf4,0xf1,0x0f,0xce,0xcd,0xe3,0xb4,0x77,
+  0x75,0xd3,0x09,0xd8,0xfe,0xef,0x17,0x0f,0x9f,0xf9,0x16,0xa3,0x86,0x9b,0x01,0x88,
+  0x24,0x34,0xeb,0xe4,0xea,0x99,0x98,0x9c,0xd6,0xd8,0xdc,0x82,0x5e,0xee,0x40,0x4d,
+  0x12,0x9b,0x9a,0x9b,0x85,0xe7,0x2a,0x48,0x2e,0x77,0xe3,0x66,0x54,0x5c,0x82,0xb1,
+  0xa9,0x05,0x9c,0xf0,0xa7,0x65,0x95,0xd8,0x8b,0x0f,0x28,0x9f,0x9d,0xe1,0xd1,0xe1,
+  0x93,0xf3,0xce,0x96,0xfa,0x4d,0x06,0x4f,0xb1,0xba,0xa6,0x46,0x50,0x68,0x38,0x13,
+  0xd5,0x2d,0x89,0x2a,0xaf,0x44,0xf8,0x3b,0x45,0x1b,0x37,0x96,0x94,0x9c,0xbd,0x6e,
+  0x27,0x38,0x90,0xe0,0xe4,0xa6,0x65,0xb0,0xeb,0xea,0x9b,0x47,0x68,0x6b,0x4e,0xbe,
+  0x7d,0x3b,0x09,0x5f,0x48,0x4c,0x4e,0x7e,0xaf,0xfe,0x18,0xbd,0xad,0xd8,0x76,0x0b,
+  0xd5,0xa2,0x44,0xd5,0x20,0x67,0x96,0xb4,0x22,0x51,0x8c,0x1f,0x6e,0x28,0x15,0x47,
+  0xd3,0xb3,0x78,0x66,0x6a,0xb4,0x90,0xc4,0xba,0x17,0x17,0x2d,0x23,0x0d,0x95,0x16,
+  0x2a,0xd0,0xc1,0xab,0x52,0xf5,0xab,0xba,0xd3,0x33,0x45,0x53,0x64,0x95,0x2a,0xed,
+  0x69,0x82,0x2b,0xb4,0xaa,0xd1,0x4b,0xaf,0x83,0xe2,0x2f,0xe1,0x85,0x2b,0xac,0xbe,
+  0xd4,0xee,0xc5,0x6b,0x70,0x71,0x03,0xec,0x98,0xb2,0x8b,0xaf,0xe0,0x15,0xa1,0xec,
+  0xc2,0xaa,0x5d,0x91,0x0d,0x92,0x9f,0x4e,0x2b,0xf0,0x85,0x5e,0x39,0x01,0x9e,0x43,
+  0x37,0x56,0xcc,0x84,0xa7,0x0a,0xe3,0x95,0xe1,0xe2,0x2a,0xc7,0x90,0xff,0xc0,0xcf,
+  0x82,0x55,0x3b,0xc4,0x95,0x5f,0x88,0xa0,0x89,0xe0,0x6a,0xd1,0xbb,0xc5,0x12,0xb7,
+  0xd8,0xe2,0x57,0x53,0x44,0x81,0x02,0x9f,0xf2,0xda,0x70,0xcc,0x61,0xed,0x61,0x0b,
+  0x15,0xab,0x98,0xd7,0xd4,0x9e,0xdb,0xdf,0xc1,0xc2,0x23,0xa3,0xb6,0x6d,0xdb,0xb1,
+  0x7b,0xcf,0xde,0xa3,0xd2,0x40,0x7e,0xaf,0xde,0xbd,0x27,0xaf,0xa4,0xa2,0xae,0xa2,
+  0x65,0xa8,0x6f,0x60,0xf4,0x58,0xd7,0x58,0x4d,0x53,0xe7,0x36,0x43,0xf5,0xe6,0xad,
+  0x3b,0x67,0xce,0x5d,0x94,0x3a,0x7c,0x64,0xd7,0xbf,0xf6,0x6c,0xdd,0xba,0x15,0x5c,
+  0xd6,0xb5,0xeb,0xd6,0xad,0x5a,0xbd,0x7a,0xf9,0xf2,0xe5,0x82,0x82,0x82,0xf8,0xeb,
+  0x80,0x17,0x2d,0x5c,0xf4,0xd1,0x87,0x1f,0x01,0x49,0x21,0x6b,0x61,0xfd,0x26,0x16,
+  0x0c,0x5f,0xbe,0x72,0xf5,0x5a,0x54,0xcc,0xff,0x33,0x77,0xdd,0x51,0x51,0x5c,0x5d,
+  0xfc,0x9f,0x2f,0x45,0x4d,0x62,0x47,0x9a,0x25,0xd4,0x05,0x14,0xa3,0x31,0x92,0xc4,
+  0x44,0x8c,0x1a,0x5b,0x62,0x10,0xe5,0x4b,0xfc,0x10,0x35,0x46,0x63,0x01,0x14,0x69,
+  0xd2,0x7b,0xef,0x45,0x7a,0x51,0x90,0xde,0xdb,0xb2,0x2c,0x48,0xef,0x28,0x76,0x50,
+  0x94,0x5e,0x64,0x97,0xa5,0x85,0x2a,0x96,0x9c,0xf3,0xbd,0x37,0x6f,0x76,0x18,0x16,
+  0x76,0x58,0x8d,0x68,0x38,0xf7,0xec,0x99,0x9d,0x9d,0x79,0xf3,0x66,0x98,0x99,0xdf,
+  0xfb,0xdd,0x77,0xef,0xef,0xa6,0xd9,0xd8,0x39,0x47,0xc5,0x24,0x56,0x55,0x03,0xfc,
+  0xed,0xa5,0xc8,0x21,0x1d,0x7b,0x36,0xb1,0x77,0xef,0x4f,0x02,0x36,0x2e,0x21,0x21,
+  0x55,0x54,0x5a,0x1a,0x15,0x93,0x90,0x49,0xcf,0xa9,0xbd,0xf5,0x80,0xc5,0xe6,0x4c,
+  0x50,0x66,0xa7,0x06,0x87,0x84,0xcc,0xe8,0xd7,0x85,0xa5,0x1c,0x02,0x83,0x8a,0xcb,
+  0xaa,0xf2,0x0b,0xcb,0xda,0x3a,0x3a,0x29,0x48,0xf4,0xf0,0xc8,0x18,0x8b,0xdd,0xd3,
+  0xda,0xd6,0x76,0x44,0x5d,0x83,0x3a,0xc3,0x82,0x6c,0xe2,0xa2,0xe2,0x6e,0xee,0x1e,
+  0xa9,0xe9,0xe9,0x7a,0x06,0x86,0x17,0xf5,0x2e,0x81,0x4b,0x11,0x16,0x1e,0x5d,0x5a,
+  0x5e,0x0d,0x15,0x05,0xc7,0x66,0x0e,0xfe,0x6c,0x6c,0x6e,0x06,0x14,0x78,0x7a,0x53,
+  0x34,0x59,0xb9,0xdc,0x82,0x42,0x2b,0x5b,0xc7,0x80,0xe0,0xf0,0xfc,0xc2,0x92,0xd6,
+  0x76,0x58,0xf5,0x89,0xe2,0x94,0x01,0xd7,0xf8,0x87,0xaf,0x20,0xf0,0x1f,0x54,0x90,
+  0x57,0x48,0xcd,0x4c,0x0f,0x0d,0xbb,0x72,0x4e,0xf3,0xfc,0x05,0x1d,0x7d,0x63,0x13,
+  0x4b,0x37,0x0f,0xef,0x6b,0xd1,0xf1,0x65,0x15,0xd5,0x8d,0xcd,0xad,0x50,0x76,0x7b,
+  0xea,0xab,0x18,0xfc,0x7f,0xe9,0x8c,0x1c,0x51,0x11,0xb1,0x77,0x96,0xb0,0x29,0xb8,
+  0x7d,0xbe,0x46,0x22,0xf7,0x7a,0x7e,0x64,0x54,0x7c,0x7a,0x66,0x4e,0xcd,0xcd,0xbb,
+  0xec,0x9e,0xde,0xd1,0x31,0x2a,0xfe,0x1b,0x9f,0x98,0x2c,0xe0,0x3f,0x1a,0xc0,0x84,
+  0xa3,0xb3,0x73,0x16,0x23,0x27,0x2e,0x31,0xa5,0xb8,0xb4,0xaa,0xad,0xbd,0x73,0x78,
+  0x64,0x84,0x62,0x92,0xb4,0xb5,0xbd,0x4d,0x4a,0x4a,0x86,0xba,0x4d,0x75,0x75,0x75,
+  0x7a,0x4e,0xae,0x8d,0x83,0x4b,0x44,0x54,0xec,0x8d,0xda,0x3b,0xec,0x1e,0x88,0xbf,
+  0xfc,0xda,0x04,0x63,0xd7,0x23,0x1a,0x73,0xa5,0xd0,0x78,0x4e,0x13,0x30,0xf1,0x34,
+  0x7b,0x27,0xb7,0x98,0xf8,0xe4,0xda,0x3b,0x0f,0x7a,0x7a,0x07,0x28,0xe2,0xc6,0xc1,
+  0xa0,0xf2,0xdb,0x6f,0xb7,0xcc,0xd8,0x8e,0xbe,0xbe,0xc1,0xfd,0xba,0xfa,0xaa,0xea,
+  0xda,0x8e,0x2e,0xd6,0xd0,0x30,0x5f,0x29,0x78,0xe8,0x7c,0x1e,0x7e,0xd6,0xdb,0xdf,
+  0x7f,0xe6,0xec,0xb9,0xf7,0x78,0xb7,0x2c,0x5c,0xbd,0x09,0x96,0x0c,0xe0,0x4e,0xf8,
+  0xe2,0x24,0x0e,0x8f,0x2c,0xc2,0x68,0x1d,0x06,0x1c,0x6b,0x4d,0x27,0x25,0xad,0x30,
+  0x75,0x29,0xf4,0x95,0x43,0x84,0x63,0xc9,0x4c,0x09,0x4c,0x9a,0x12,0x61,0x45,0x4c,
+  0xaa,0x4e,0x8a,0x6f,0xe0,0xed,0x70,0x48,0xde,0x5a,0x54,0x7f,0x10,0x9f,0x9f,0x45,
+  0x81,0xc7,0x28,0x25,0x0a,0x6a,0x4f,0xa1,0x6a,0x0e,0xa6,0xbd,0x44,0xea,0x10,0x69,
+  0x62,0x1a,0x75,0x80,0x83,0xdc,0xc5,0xdc,0x22,0x11,0x6c,0x1a,0x11,0x76,0x05,0x29,
+  0x7c,0x0f,0x6c,0xc1,0x84,0x54,0x95,0x09,0xd3,0x76,0xe6,0x46,0x94,0x71,0x05,0xaf,
+  0x48,0x73,0xc1,0x93,0xfd,0xe4,0x4e,0x1c,0x63,0x8c,0x1e,0xe7,0xb9,0x48,0x33,0x04,
+  0x75,0x15,0xcd,0xfc,0x62,0xd5,0x91,0x38,0x93,0x9e,0x7c,0x53,0x5c,0x58,0x7b,0x1d,
+  0x46,0xc0,0x61,0x30,0x39,0xe8,0x06,0x24,0xc5,0x6c,0xa2,0x82,0x21,0xbc,0xec,0x7a,
+  0x8d,0x80,0x05,0xcb,0x6a,0xd5,0x4a,0x9d,0xbe,0x21,0x73,0xa2,0x48,0x5a,0x23,0x4b,
+  0xea,0xd7,0x38,0x40,0x81,0xd7,0xec,0x73,0xdf,0x7e,0x2a,0xa4,0x8b,0x3d,0xf8,0xde,
+  0x41,0x96,0xef,0xfd,0xff,0xea,0x85,0x93,0x93,0xf3,0x97,0x9b,0x36,0x6f,0xdf,0xf1,
+  0xe3,0x01,0x55,0xb5,0x63,0xc7,0x4f,0x6a,0x5d,0xd0,0x35,0x36,0xb1,0xb0,0xb5,0x77,
+  0xb0,0x76,0xf4,0x72,0x70,0x74,0xb2,0xb6,0xb1,0x37,0x34,0x32,0x3f,0xa7,0xa5,0xa3,
+  0xa6,0xfe,0xc7,0xde,0x7d,0xbf,0x6c,0x55,0xde,0xf9,0xd5,0x26,0x25,0x05,0x05,0x05,
+  0x34,0x05,0x2c,0x24,0x24,0x04,0x13,0x81,0xb1,0x72,0x48,0xf3,0xe7,0xcd,0x47,0x5a,
+  0x58,0x84,0x73,0xf2,0x75,0x67,0x81,0x55,0x0f,0x1e,0xca,0xc2,0x32,0x3e,0x22,0xa2,
+  0x63,0xc1,0x73,0xd7,0xcd,0xa6,0xc2,0x5f,0xf0,0x72,0x51,0x55,0x3d,0x24,0x60,0xcb,
+  0x2b,0xc5,0x57,0x55,0x56,0x57,0x17,0x16,0x95,0x55,0xd7,0xdc,0x78,0xfc,0xa4,0x75,
+  0x60,0x70,0x84,0xc2,0x3b,0x07,0x2c,0x2e,0x3e,0x7e,0xc6,0xb4,0x08,0x49,0x09,0xc9,
+  0xaa,0xea,0x9a,0x8c,0x2c,0x66,0x59,0x45,0xcd,0x53,0x56,0xcf,0x28,0xff,0x80,0xcc,
+  0xfe,0x81,0x81,0xde,0xbe,0x3e,0x2f,0x6f,0xcf,0xd7,0xd5,0x81,0x17,0x13,0x15,0x07,
+  0x6f,0xe6,0x80,0xd0,0x50,0xed,0x0b,0x17,0x4d,0x4c,0x2d,0xbd,0x7d,0xfc,0x33,0xe9,
+  0xcc,0xba,0x87,0xb0,0x4a,0xdd,0x8c,0xaf,0xa0,0x89,0x17,0xcf,0x8d,0x8c,0x4c,0x66,
+  0xe8,0xaa,0xa4,0x14,0x3d,0x87,0x69,0x65,0x6b,0xeb,0x1f,0x10,0x72,0x3d,0xbf,0xb8,
+  0xa5,0xbd,0x63,0x64,0x64,0x82,0xe2,0x25,0x9f,0x98,0x9c,0xf6,0x56,0x5e,0x44,0xca,
+  0xdb,0xb6,0x97,0x96,0x57,0xd8,0x39,0x3a,0x69,0x69,0x9d,0xbf,0x70,0xd1,0xd0,0xd4,
+  0xcc,0xc6,0xd3,0x2b,0x20,0x31,0x25,0xbd,0xb2,0xa6,0xb6,0xad,0xfd,0xe9,0xf0,0xc8,
+  0x28,0x4f,0x52,0xf3,0xc4,0x8b,0x17,0x80,0x0c,0x2e,0x13,0xb8,0x78,0xee,0x3b,0x33,
+  0x71,0xf1,0x95,0x79,0xf9,0xf9,0x80,0xbc,0x57,0x56,0xd6,0x3e,0x69,0x6a,0x1b,0x18,
+  0x1c,0xa4,0x1e,0xb3,0xd1,0x19,0xf4,0x59,0xb3,0x84,0x90,0x81,0xc1,0x86,0xa5,0xb5,
+  0xcd,0xcd,0x5b,0xb7,0xc1,0x40,0xee,0x7e,0x5d,0x43,0x4f,0x6f,0xdf,0xd8,0x18,0x15,
+  0xb3,0xee,0xea,0xea,0x5e,0xb7,0x6e,0x3d,0x75,0x9b,0x2a,0x2a,0x07,0xb2,0x19,0xb9,
+  0xd6,0xb6,0x0e,0x11,0xd7,0x60,0xb8,0x7b,0x37,0x8b,0x4d,0x3d,0xff,0x7b,0xe2,0xd4,
+  0x2c,0x35,0x95,0xde,0xd8,0x8e,0x1c,0x39,0x9a,0x91,0x9d,0xe5,0xe0,0xec,0x0a,0xf0,
+  0xb7,0xfa,0xd6,0x6d,0x4e,0x5f,0xdf,0x04,0xff,0xa4,0x5d,0x60,0x3b,0x66,0x8a,0x58,
+  0xfe,0xe4,0x93,0x4f,0xd2,0xb3,0xe8,0x77,0xee,0xd6,0xd5,0xd5,0x37,0x40,0x3f,0xd8,
+  0x04,0xff,0x5c,0xaa,0x17,0x2f,0x47,0x46,0x46,0x1f,0xd4,0xd7,0x2b,0x2a,0xce,0x72,
+  0x89,0xe6,0xd4,0xe6,0x2f,0x14,0x95,0x3e,0x57,0x83,0x9c,0xb1,0x6b,0x8d,0xdb,0x27,
+  0xa7,0x5c,0x21,0x68,0xf6,0xa2,0x82,0x47,0xb2,0x48,0x67,0xc3,0xb8,0x9b,0x90,0xb4,
+  0xc2,0x93,0x67,0x51,0xd6,0x2d,0xee,0x9d,0xe6,0xfa,0x93,0x71,0x2e,0x09,0x95,0x37,
+  0x88,0xa2,0x09,0x93,0x9c,0x14,0xf3,0x18,0x83,0xc6,0xa7,0x48,0x4b,0x4d,0xce,0xa5,
+  0xce,0x98,0x43,0x04,0x21,0x4f,0x9e,0x5b,0x08,0x98,0xd8,0x77,0x12,0xbb,0x49,0x8a,
+  0x1f,0x48,0xe1,0x4a,0x0e,0x0f,0xaf,0xea,0xc6,0x05,0xaf,0x60,0x61,0x41,0xf2,0xcc,
+  0x32,0x69,0x62,0x1a,0x1d,0xce,0x78,0xf2,0x70,0xa8,0x93,0x5c,0x28,0xef,0xc3,0xa8,
+  0x3a,0xa1,0x37,0x42,0x38,0xcf,0x7b,0x91,0x7a,0x27,0x76,0x44,0xcc,0x67,0x6e,0xc4,
+  0xc2,0x87,0x19,0xd8,0xfc,0x32,0x9c,0xa4,0xc6,0x16,0x68,0x66,0x7d,0x72,0x66,0x78,
+  0x05,0x46,0x4c,0xd8,0x84,0x45,0x92,0x89,0x06,0x14,0xb8,0x49,0x46,0xf7,0x89,0xac,
+  0xf6,0x5d,0xd9,0xb3,0x35,0x32,0xa7,0x2a,0x68,0xbf,0x33,0xa4,0xd5,0x93,0x24,0x55,
+  0xc3,0x24,0xf6,0x5f,0x96,0x3e,0xe0,0x7b,0xf7,0x51,0xe7,0xfb,0x05,0x59,0x0a,0x1b,
+  0x9f,0x98,0x00,0x54,0x4b,0xe9,0xeb,0x6f,0x7f,0xdc,0xf5,0x93,0xda,0x7f,0x7f,0x3b,
+  0x71,0x46,0x4b,0xd7,0xd0,0xc4,0xc6,0xd6,0xd1,0xce,0xc5,0xcf,0xdd,0xcb,0xd7,0xd9,
+  0xd3,0xdf,0xd6,0xc9,0xc3,0xcc,0xdc,0x46,0xfb,0xa2,0xde,0xef,0x27,0x4e,0xab,0xa8,
+  0xaa,0xed,0xd8,0xb9,0x0b,0xcb,0x42,0x52,0x94,0x92,0x92,0x5e,0xb3,0xe6,0x73,0x61,
+  0x61,0x61,0x80,0xbf,0x8b,0x17,0x2e,0x41,0x5a,0x58,0x90,0xff,0x62,0x5e,0x68,0x54,
+  0x0e,0x09,0xdd,0x99,0x82,0xa3,0xf0,0xae,0x1f,0x77,0x67,0x66,0xe7,0xd8,0xda,0xbb,
+  0x00,0xd2,0x51,0x5a,0x05,0xbd,0xc4,0xe3,0xe3,0xcf,0xf8,0x41,0x06,0x60,0x52,0x1a,
+  0x1a,0x47,0x05,0x6c,0x79,0x85,0xd0,0x8a,0xf2,0xca,0xaa,0xa6,0x96,0xb6,0xce,0x2e,
+  0x16,0x40,0x46,0x18,0xcb,0x41,0x29,0x8d,0x92,0x9a,0x9e,0xb9,0x68,0x26,0x91,0x3d,
+  0x70,0x44,0x40,0x2e,0x12,0x93,0x33,0x6a,0x6f,0x3f,0xe0,0xf4,0x0e,0xf2,0xf3,0x09,
+  0x4f,0x4c,0xbc,0x18,0x1d,0x1f,0x03,0x88,0xbf,0x7a,0xf5,0x9a,0x37,0x78,0x96,0xb7,
+  0x2a,0x6f,0xcb,0x2f,0x2e,0xb2,0xb6,0x73,0xd0,0xd1,0x37,0xb2,0x71,0x70,0x8b,0x8d,
+  0x4b,0xae,0xb9,0x09,0x18,0x0d,0xdf,0x29,0xb0,0x92,0xb2,0xf2,0xa5,0xd3,0xa4,0xc0,
+  0x56,0xae,0x5c,0x9d,0xc9,0xc8,0xb6,0xb3,0x77,0xbe,0xec,0x17,0x44,0x67,0x16,0x63,
+  0x4e,0x4e,0xaa,0x24,0xd3,0x9c,0xdc,0xdc,0xb7,0xf2,0x22,0xfa,0xe0,0x3f,0x1f,0x6c,
+  0xd9,0xf2,0x1d,0x38,0x77,0x57,0x37,0x77,0x2d,0x2d,0xed,0xf3,0x3a,0x06,0xa6,0xe6,
+  0xd6,0x5e,0x9e,0x41,0x09,0x49,0xa9,0x95,0x35,0xb7,0xdb,0x3a,0xba,0xe1,0x5c,0xe7,
+  0x54,0x08,0x1e,0x9f,0x18,0xf7,0xf0,0xf4,0xa6,0x50,0x35,0x7c,0x2f,0xb6,0x42,0x48,
+  0x18,0xe0,0x6f,0x4b,0x5b,0x7b,0x7b,0xe7,0x53,0x4e,0xff,0x20,0x45,0xfc,0x0f,0xb2,
+  0xb2,0xf2,0x32,0xf0,0x14,0x08,0xd8,0xb8,0xa9,0xb9,0xe5,0x53,0x16,0xab,0xb5,0xbd,
+  0x83,0xd3,0xdb,0x37,0x34,0x34,0x4c,0xa1,0x33,0x03,0x8c,0xd3,0xc7,0x51,0xda,0x3c,
+  0x83,0x8b,0x83,0x6c,0x3b,0x76,0xee,0x04,0x6c,0xdd,0xda,0xce,0xe5,0x4a,0x64,0x74,
+  0x45,0xe5,0xcd,0xce,0xee,0x5e,0x8a,0x70,0xbb,0xf1,0x89,0x67,0x7a,0xfa,0x06,0x73,
+  0x74,0xdd,0xf6,0xab,0xfc,0x92,0x9b,0x5f,0x68,0xef,0xe8,0x7a,0x2d,0x3a,0xae,0xaa,
+  0xe6,0x0e,0x18,0xa6,0x52,0x17,0x83,0x3e,0x74,0xe8,0xf0,0xf4,0x46,0xb6,0x6e,0x55,
+  0x6e,0x6e,0x69,0x7d,0xf4,0xb8,0xb1,0x9b,0xc5,0x19,0x19,0x1d,0xa7,0xb8,0xf2,0x2f,
+  0x5e,0xbe,0x1c,0x1b,0x1f,0x0f,0x0a,0x0e,0x99,0xf7,0xb1,0x40,0xd5,0x48,0xe7,0xc8,
+  0x3e,0x9a,0xb7,0x78,0xcd,0xe1,0x04,0x98,0x23,0x43,0x84,0x27,0x21,0x87,0x30,0x14,
+  0xc7,0x40,0xa9,0xaf,0xbd,0x84,0xb4,0x23,0x2a,0xda,0xcb,0x8d,0x70,0xe6,0x4c,0x91,
+  0xa5,0xe2,0x55,0xa9,0x9a,0x04,0x44,0x5c,0x4a,0x0b,0x01,0xe8,0x54,0xa2,0x8d,0xb7,
+  0xcc,0xdd,0x18,0xc5,0x15,0x13,0xb9,0x3c,0x48,0x77,0x1a,0x57,0xc9,0x20,0xa2,0x8e,
+  0xb9,0xdd,0x20,0xb0,0x1b,0x05,0x6b,0x71,0xd9,0x77,0xef,0xf4,0x29,0xda,0x29,0xe1,
+  0x58,0xa6,0x44,0x38,0x56,0x2f,0x79,0x5f,0x80,0x98,0x04,0xc4,0xf3,0xa0,0x3f,0xe1,
+  0x8e,0xc6,0x3c,0xde,0xa8,0xe2,0x12,0x1b,0x0d,0x3f,0xc0,0x57,0x39,0xae,0xfc,0x17,
+  0x96,0x59,0x0c,0xcb,0x1f,0x43,0x7d,0x4b,0x73,0x0e,0x5a,0x40,0x5a,0x9d,0x28,0x2f,
+  0x09,0xa5,0x54,0xc3,0xaf,0xdc,0x74,0x24,0x19,0x83,0x0e,0x40,0x81,0x31,0x08,0xbe,
+  0x2d,0x73,0xb6,0x86,0xf6,0x47,0xa1,0xf4,0x91,0x2c,0x58,0x23,0x58,0x25,0x94,0xa6,
+  0xe2,0x5d,0x50,0xd5,0xf2,0x7e,0x41,0x96,0xc2,0x06,0x87,0x86,0x4e,0x9d,0x3e,0xb3,
+  0xe5,0x3b,0xe5,0xbd,0x3f,0xfd,0x72,0x58,0xfd,0xa8,0xe6,0xf9,0x8b,0xc6,0x66,0xd6,
+  0xf6,0x2e,0x5e,0x1e,0xde,0x01,0xbe,0xfe,0x41,0xde,0x7e,0x41,0xae,0x9e,0x7e,0xb6,
+  0xf6,0xce,0xfa,0x06,0xc6,0x27,0xff,0xd4,0x54,0xfb,0xf5,0x7f,0x7b,0xf7,0xfd,0xfc,
+  0xdd,0xf7,0x5b,0x37,0x6e,0xfc,0x52,0x56,0x96,0x06,0xf0,0x57,0x54,0x4c,0x6c,0xb9,
+  0x90,0x30,0x78,0xf9,0x83,0x97,0x27,0xf2,0x42,0x43,0x39,0x4a,0x2c,0x48,0x06,0xa6,
+  0x23,0x61,0x4e,0x45,0xc1,0x5d,0x8b,0x5b,0xbf,0xdf,0x86,0xb2,0x84,0xc2,0xaf,0x46,
+  0x95,0x94,0xe3,0xf8,0x4b,0xd1,0xf9,0x73,0xe7,0xb4,0x04,0x6c,0x79,0xd1,0xa2,0xc5,
+  0xc5,0x25,0xa5,0x7f,0x0d,0x41,0xf5,0xfe,0xf1,0x67,0x33,0x28,0x5a,0xf0,0x18,0x23,
+  0x87,0xb9,0x74,0x5a,0xc9,0xdd,0xf9,0x1f,0xcf,0xf7,0xf6,0xf5,0x66,0xe4,0xe6,0x27,
+  0xa7,0x65,0xdf,0xbe,0x57,0x8f,0x26,0x34,0x67,0xdc,0x1d,0xe0,0xef,0x5f,0x43,0x43,
+  0xfa,0xfa,0x06,0xfc,0x82,0xb8,0xa8,0x0d,0x1c,0xc8,0xdc,0xd2,0x32,0x83,0x4e,0xd7,
+  0x33,0x30,0xb6,0xb0,0xb4,0x09,0xbf,0x1a,0x5d,0x5c,0x52,0x09,0x63,0xad,0xf9,0xd0,
+  0xed,0x6e,0x16,0x6b,0xf3,0x57,0x4a,0x3c,0x8d,0x88,0x8a,0x88,0xa6,0x65,0x64,0x3a,
+  0x3a,0xb9,0xf8,0xfa,0x05,0x32,0x98,0x05,0x4f,0x9a,0x9a,0x87,0x86,0x87,0x29,0x4e,
+  0x19,0x20,0xe6,0xdb,0x72,0x02,0x83,0xff,0xfe,0xf1,0xdf,0x4f,0xe4,0xe5,0x17,0x58,
+  0x5a,0xd9,0x6a,0x9f,0xbf,0x08,0x58,0x30,0x0c,0xe7,0xf6,0x0f,0x4e,0xcd,0x60,0xdc,
+  0xbc,0x73,0xbf,0xa3,0xab,0x7b,0x64,0x0c,0x4f,0x6a,0x26,0x06,0x57,0x7d,0x03,0x03,
+  0xfa,0x06,0x86,0x9f,0xbe,0x2b,0xd9,0x5e,0x41,0x6c,0xe9,0x92,0xa5,0x99,0x74,0x3a,
+  0xb8,0x68,0xf0,0x9e,0x19,0x9f,0xa0,0x86,0x48,0x74,0x01,0xc1,0x2e,0x02,0x36,0xae,
+  0xa7,0x6f,0x38,0x32,0x3a,0x36,0x3c,0x3c,0x3a,0x3a,0x36,0x3e,0x6b,0xcb,0x7d,0x03,
+  0xfd,0xdb,0xb6,0xcd,0x92,0xd6,0xaa,0xac,0xac,0x5c,0x54,0x5c,0x6c,0x69,0x63,0x1f,
+  0x7e,0xf5,0x5a,0x59,0x45,0x75,0xdb,0x53,0x0e,0x05,0xfe,0x82,0xb1,0xab,0x85,0x95,
+  0xf5,0x1c,0x5d,0xb7,0x9d,0x3b,0x77,0x15,0x14,0x17,0xd9,0x3b,0x3a,0x45,0x46,0xc5,
+  0x81,0x11,0xd7,0xd3,0x6e,0xd6,0x8b,0x17,0x7c,0xb3,0x08,0x81,0x1d,0x3b,0x76,0x82,
+  0xa7,0x05,0x30,0x8c,0xb7,0xb6,0xb1,0x65,0x73,0xfa,0x59,0xec,0xbe,0xe1,0x91,0x51,
+  0x0a,0xd9,0xed,0x57,0x58,0xe8,0x02,0x18,0xeb,0xaa,0x1e,0x14,0xd4,0x15,0x36,0x47,
+  0xf6,0xc1,0x87,0x0b,0xc4,0xf6,0x7a,0x40,0x38,0x40,0x62,0xcb,0x18,0x71,0x23,0xd2,
+  0x5d,0x91,0xd3,0x15,0x5f,0x30,0xc5,0xbd,0xc7,0x08,0x6e,0x48,0x04,0x16,0xa6,0xdc,
+  0x92,0xd5,0xa2,0x88,0xf5,0x44,0x84,0x12,0x11,0x5c,0x4d,0x82,0x36,0xdc,0x23,0x4d,
+  0xae,0xa1,0x80,0xef,0x6b,0x4c,0x94,0x3f,0x80,0x65,0x1a,0x70,0xa1,0x2d,0xae,0xf3,
+  0x19,0x92,0x71,0x44,0xc3,0xf1,0x04,0x5b,0x8c,0x81,0x62,0x75,0x00,0x01,0x4c,0xcb,
+  0x18,0x61,0x71,0xd4,0x46,0x88,0xb3,0xf7,0x10,0x6e,0x61,0xe4,0x73,0x96,0xc1,0x0c,
+  0x2f,0x1a,0xc8,0x2d,0x20,0x28,0x8b,0x44,0x38,0x4d,0x7a,0xe4,0x8c,0x9e,0x72,0x57,
+  0xe2,0x83,0x01,0xe2,0x94,0x51,0xd5,0x09,0x54,0xa6,0x10,0xed,0x02,0xa3,0xce,0xf0,
+  0x88,0x2f,0x0e,0x5e,0x39,0x82,0x48,0xfe,0x35,0xc3,0x89,0xbc,0x9c,0x29,0x87,0x7b,
+  0x25,0x51,0x91,0x47,0x7c,0x24,0x40,0x33,0xea,0x06,0x64,0x59,0xc1,0xb8,0x83,0x76,
+  0xa9,0x53,0x56,0xbf,0x19,0x40,0xb0,0xec,0x85,0x7a,0x05,0x2d,0x40,0x81,0xcb,0xe5,
+  0x4f,0x30,0xa5,0x0f,0x27,0x48,0x1e,0x0c,0x97,0xd8,0xef,0x9b,0x94,0x77,0xf7,0xdd,
+  0x03,0xab,0x80,0xc6,0x62,0xb3,0xd4,0x8f,0x68,0x7c,0xaf,0xbc,0x6d,0xbf,0x8a,0xda,
+  0xd1,0xe3,0x7f,0x5c,0xd4,0xbf,0x64,0x6d,0xe7,0xe8,0xe6,0xed,0x17,0x10,0x1c,0x1e,
+  0x72,0xe5,0x6a,0x70,0x68,0x24,0x80,0x60,0x47,0x37,0x1f,0x13,0x33,0xab,0x0b,0x3a,
+  0x7a,0x00,0xa0,0x7f,0xfe,0x45,0x15,0x6c,0xbc,0xe9,0x2b,0xa5,0x75,0x6b,0x15,0x25,
+  0x24,0x24,0xc5,0x57,0xae,0x14,0x16,0x11,0x5d,0xb6,0x6c,0xf9,0xd2,0x25,0x50,0x0e,
+  0x1a,0x69,0x71,0x00,0xf8,0x40,0xb1,0xa9,0xaf,0x1b,0x88,0xb5,0x59,0xe9,0x9b,0xbc,
+  0xc2,0x02,0x07,0x27,0xd7,0xd0,0x2b,0xd7,0x0a,0x4b,0xaa,0x3b,0xba,0xa8,0x32,0x2e,
+  0x81,0x5d,0x32,0x36,0x11,0x90,0x5c,0x83,0xbe,0x15,0x16,0x15,0x81,0xe7,0x58,0xc0,
+  0xcb,0x52,0x54,0x5c,0x3a,0x5d,0x64,0x0f,0x7a,0x86,0xb3,0x19,0x11,0x51,0xb1,0xa9,
+  0x19,0x39,0xf7,0xea,0x1e,0x43,0xda,0x32,0x23,0x37,0xff,0xfb,0xd5,0xb3,0x67,0x2f,
+  0xee,0xde,0xbb,0xa7,0xa0,0xb0,0xf6,0x8d,0x1f,0x67,0x1a,0x4d,0xae,0xa8,0xac,0xd4,
+  0xc6,0xc1,0xd1,0xd8,0xd4,0xc2,0x27,0x10,0x16,0x95,0x6b,0x68,0x6a,0xc3,0x54,0x0a,
+  0x67,0xd2,0xe2,0x18,0x1f,0x3b,0x73,0x56,0x93,0xe7,0x52,0x2c,0x5f,0x26,0x94,0x94,
+  0x92,0xea,0xe4,0xea,0xee,0xe1,0xe3,0x97,0x9d,0x93,0xf7,0xb8,0xb1,0x99,0x5a,0x89,
+  0xb7,0xf6,0xce,0x9d,0xb7,0xa8,0xa5,0x0c,0xee,0x01,0x4d,0x4d,0x2d,0x40,0xcc,0x4d,
+  0xcc,0x4c,0xb5,0xb5,0x75,0x74,0x0d,0x8c,0x2c,0x6d,0x1c,0x02,0x83,0x42,0xb3,0x19,
+  0xb9,0xb7,0xef,0xd6,0xb3,0x7a,0x7a,0x46,0x47,0x79,0xe9,0x64,0xdf,0x40,0x1f,0x40,
+  0x6d,0x0a,0x45,0x91,0xb7,0x6b,0xe4,0x9b,0x73,0xc6,0x5b,0x74,0xe1,0x67,0x0b,0x53,
+  0xd2,0xd2,0xa0,0x04,0xb7,0x60,0xd5,0x9c,0x6f,0xdd,0xb9,0x27,0xbc,0x42,0x58,0x90,
+  0x1b,0x1e,0x6c,0x70,0xfa,0xac,0xe6,0x8b,0x57,0x30,0x1c,0x4d,0x90,0xe0,0xcc,0x81,
+  0xbf,0x06,0xf7,0xec,0xdd,0x37,0xcb,0xb3,0xb3,0x59,0xe9,0x7a,0x61,0x91,0x95,0xad,
+  0x43,0x48,0x68,0x64,0x69,0x59,0x25,0x18,0xe4,0x50,0x04,0x27,0xc0,0x59,0x27,0x67,
+  0x97,0xd7,0xba,0x5c,0x68,0x38,0x0d,0xc6,0x93,0xb3,0x0e,0xd2,0x94,0xbe,0xdd,0x52,
+  0x5a,0x5e,0xee,0xe0,0xe8,0x1c,0x11,0x19,0x53,0x52,0x79,0xab,0xab,0xbb,0x1b,0xd0,
+  0x6d,0x8a,0x11,0xaf,0xa6,0x96,0x36,0x4f,0x9b,0x62,0xa2,0x62,0x95,0x55,0xd5,0xa3,
+  0xb0,0x26,0x16,0x96,0xdc,0x37,0xdb,0x25,0xaa,0xbd,0x75,0x5b,0x5c,0x6c,0xae,0x64,
+  0x58,0x04,0xb4,0x0f,0xfe,0xf3,0x91,0xe8,0x56,0x7d,0xda,0x25,0x7c,0xea,0x56,0x01,
+  0x77,0xa2,0x72,0xeb,0xfb,0x90,0xaa,0x13,0x12,0x11,0x4d,0x72,0x28,0x8a,0x69,0x6a,
+  0x0c,0x15,0x1e,0xda,0xc4,0x55,0x8b,0x22,0x97,0x05,0x44,0x13,0xca,0xe8,0x2b,0x6a,
+  0x84,0x54,0x7f,0xb0,0x87,0x3b,0xdb,0x3b,0x25,0x86,0x0a,0x05,0x3e,0x21,0x57,0x36,
+  0xe1,0x61,0x9e,0xb6,0x2f,0x87,0xbc,0x2f,0x26,0x4a,0xf9,0x94,0x90,0xe1,0x22,0x89,
+  0x65,0xf5,0x4c,0x6f,0x8a,0xe0,0xb9,0x28,0x2a,0x8c,0x38,0x5f,0xbc,0x1b,0xdc,0x08,
+  0xab,0xc9,0x8a,0x8a,0x53,0x7c,0xe3,0xb8,0x8b,0x00,0x46,0x7f,0x71,0x3f,0xe1,0x71,
+  0xc1,0x09,0x9a,0xb1,0x61,0x16,0xb0,0xd9,0x64,0xc4,0x17,0x37,0x27,0x1a,0x45,0x9d,
+  0x75,0x63,0x64,0x99,0x85,0x76,0x91,0x35,0xea,0x56,0x00,0xec,0x1b,0xcd,0x02,0xeb,
+  0x34,0x40,0x0a,0x7c,0xa6,0x4a,0xea,0x44,0x81,0xb4,0x46,0x9a,0x94,0x5a,0x8c,0xa4,
+  0x6a,0x88,0x6f,0xc2,0x8d,0xb9,0x86,0xd1,0x37,0xb6,0xa6,0x96,0x66,0x55,0xd5,0x43,
+  0xca,0x3f,0xec,0x3c,0xa8,0xf6,0xeb,0xc9,0x3f,0xcf,0x18,0x18,0x9b,0xda,0x39,0x7a,
+  0xf8,0x06,0x86,0x00,0x06,0x1a,0x1e,0x95,0x1c,0x19,0x15,0x13,0x14,0x76,0xc5,0xc3,
+  0xc7,0xdf,0xc6,0xd6,0x41,0x57,0xdf,0xe8,0xd8,0x89,0x3f,0x0f,0x1c,0xfc,0x6d,0xfb,
+  0xce,0x3d,0x5f,0x7f,0xb3,0x45,0x51,0x71,0x3d,0xe6,0x82,0x86,0xb3,0xc0,0xcb,0xb1,
+  0xbf,0x45,0x9f,0x2d,0x26,0xbc,0xd0,0xc0,0x20,0x05,0xc6,0x62,0xa1,0x05,0x0f,0xc4,
+  0x52,0x5c,0xb7,0x1e,0x90,0x26,0xf0,0xe4,0x86,0x86,0x47,0x16,0x14,0x97,0x77,0x74,
+  0x76,0x61,0xd2,0x13,0x7c,0x3b,0x7f,0xaf,0xee,0x41,0x42,0x52,0x52,0x7c,0x22,0xb4,
+  0xb8,0x84,0x24,0xb0,0x3c,0xfd,0x13,0xfd,0x9a,0x94,0x92,0xc2,0x62,0xb3,0x05,0xbf,
+  0x2c,0x37,0x6e,0xde,0x5c,0xbd,0x8a,0x37,0x2d,0x11,0x70,0x4c,0x80,0xcb,0xfe,0x81,
+  0xa1,0x59,0xd9,0x79,0x75,0x0f,0x1b,0x07,0x87,0xf8,0x56,0xd4,0x05,0x38,0xef,0x1f,
+  0x10,0x2c,0xb8,0x37,0x72,0xba,0x2d,0x98,0xb7,0xc0,0xc9,0xc5,0x35,0x2a,0x36,0xce,
+  0xd0,0xc4,0xd4,0xdb,0x27,0x20,0x3d,0x2b,0xe7,0x61,0xc3,0x93,0x81,0x81,0xe1,0x19,
+  0xb3,0x54,0xc0,0xeb,0x34,0x20,0x20,0xe8,0x93,0xf9,0x53,0x26,0xac,0x01,0x7f,0x87,
+  0x22,0x0f,0x1e,0x3e,0x6e,0xde,0x97,0x33,0xe9,0xcc,0x47,0x8f,0x9b,0xa1,0x9e,0x27,
+  0x7f,0x28,0xa9,0x7b,0xf8,0xf8,0xed,0x6a,0x29,0x2f,0xfc,0x74,0xa1,0xb1,0x89,0x59,
+  0x16,0x83,0x69,0x68,0x64,0xa2,0xa5,0xad,0x03,0xb8,0xbc,0xb5,0x9d,0x6b,0x50,0xd8,
+  0x55,0x70,0xf5,0xee,0xd7,0x3f,0x62,0xb1,0x39,0xd3,0xc3,0x89,0x9b,0x9a,0x5b,0x0f,
+  0x1f,0x56,0x9f,0xd3,0x58,0x2c,0x70,0x43,0xaa,0x1e,0x3c,0x18,0x7e,0x25,0x22,0xec,
+  0x4a,0x44,0xc4,0xb5,0xa8,0x6b,0x51,0x31,0x71,0xf1,0x49,0xb1,0xf1,0x09,0xb1,0xf1,
+  0xbc,0x37,0x12,0xb8,0x67,0xda,0x3b,0x5f,0x63,0xe6,0xe8,0xaf,0xa1,0xe1,0x8c,0xac,
+  0x2c,0xac,0x91,0x64,0xa2,0x11,0xd4,0x26,0x4f,0xcb,0xf1,0x89,0x89,0xd5,0x35,0x35,
+  0xaf,0xd1,0xf2,0xf0,0xd0,0x21,0xb5,0xdf,0xa8,0x2f,0xcb,0x17,0x5f,0x6c,0xc8,0x2b,
+  0x28,0xb6,0xc6,0xf0,0xb7,0xa8,0xa4,0xb2,0x1d,0x3c,0x3b,0x94,0xd1,0x62,0x8f,0x1e,
+  0x37,0x50,0x77,0x92,0xe7,0x33,0x26,0x2e,0x11,0x74,0x1b,0x9c,0x5a,0x54,0x4c,0x8c,
+  0x8a,0xea,0x41,0x8a,0x9e,0xac,0x5f,0xff,0x45,0x49,0x79,0xa5,0xbd,0x93,0xeb,0x95,
+  0x88,0x98,0xd2,0x8a,0xea,0xce,0xae,0x59,0xe2,0xc6,0x2d,0x2c,0xad,0x84,0x85,0x84,
+  0x85,0x96,0x09,0x2d,0x5f,0x0a,0x0d,0x2c,0xa8,0xa8,0x1c,0x18,0x1e,0x85,0xfa,0xd5,
+  0x02,0x95,0xd2,0x7e,0xf9,0xdc,0xc3,0xd3,0x6b,0xfe,0xbc,0x05,0x73,0x77,0xcf,0x08,
+  0x62,0xe0,0xbf,0x23,0xbc,0xf1,0x98,0x8c,0x41,0x3b,0x21,0x22,0x21,0x3b,0xa9,0x53,
+  0xd1,0x4b,0x8e,0x74,0x22,0x18,0x2e,0x16,0xbc,0x44,0x44,0x67,0x71,0x48,0x9b,0x71,
+  0xb8,0x14,0xb5,0x97,0xf8,0x95,0x87,0x0e,0x73,0xb3,0x75,0x7a,0x70,0xa1,0x2d,0xae,
+  0xba,0x32,0x62,0x9a,0xe8,0x57,0x8c,0x4b,0x4e,0x1e,0x14,0x65,0x39,0x91,0xa9,0x37,
+  0x16,0x8b,0xd5,0x87,0x0a,0x1f,0x20,0xfa,0x89,0xb8,0x27,0x0d,0x5b,0xa6,0x99,0x90,
+  0x98,0x26,0xc6,0xe5,0xd1,0x36,0x18,0x4b,0x7d,0x8a,0xf6,0xc5,0x17,0xb8,0xdb,0xa0,
+  0x35,0xc4,0x32,0xbe,0x06,0xf3,0x1b,0x13,0xed,0x13,0x5e,0x71,0xb4,0x25,0xf1,0x2b,
+  0xb1,0x0d,0x8d,0xfb,0x15,0x73,0x35,0xa3,0xa0,0x2f,0x8e,0x2c,0x51,0x2b,0x0a,0xa7,
+  0xcc,0x78,0x4f,0x50,0xa5,0xa4,0xb5,0x26,0x2c,0x39,0xc3,0x0e,0x19,0xfd,0x56,0x48,
+  0x81,0xcf,0xdf,0x97,0xd5,0xbc,0x21,0x75,0xaa,0x58,0xee,0xf7,0x2c,0xa9,0x5f,0x63,
+  0xa5,0x0e,0x85,0x39,0x84,0x96,0x08,0x38,0x84,0x7e,0xf7,0x76,0xef,0xc1,0xfd,0x7d,
+  0xfb,0x7e,0xde,0xbe,0x63,0xb7,0x8a,0x9a,0xc6,0xd9,0x73,0x17,0x4c,0xcd,0x2c,0x9d,
+  0x3d,0x2f,0x07,0x85,0x46,0x5c,0x8b,0x4e,0x88,0x4f,0x4c,0x8b,0x8e,0x4d,0x0a,0x89,
+  0x48,0xf2,0x0b,0x0c,0xb1,0x73,0xf2,0x34,0x32,0x35,0x3f,0x7d,0x4e,0x5b,0xed,0xb7,
+  0x23,0x7b,0xf6,0xa9,0x6c,0xf9,0x6e,0xdb,0xc6,0x8d,0x9b,0xe4,0xe4,0xe4,0x24,0x24,
+  0xa4,0xc4,0x57,0xae,0x16,0x16,0x11,0x01,0xf8,0xbb,0x74,0xe9,0xd2,0x45,0x0b,0x17,
+  0x01,0xd6,0x80,0xf0,0x17,0xcf,0xe2,0xc4,0xe4,0x28,0x67,0x7c,0x75,0x20,0xbd,0x0e,
+  0xf2,0x1a,0x69,0x29,0x19,0xe6,0xf5,0x3c,0x7b,0x47,0x37,0xff,0x90,0xf0,0xeb,0x85,
+  0x65,0xcd,0x2d,0x1d,0xa3,0x63,0x54,0xba,0xf4,0x73,0x78,0x59,0xee,0xdf,0x93,0x94,
+  0x90,0xe2,0xe9,0xf0,0x81,0x03,0xaa,0xf9,0x85,0x45,0x97,0xfd,0x42,0x32,0x19,0xcc,
+  0xba,0x47,0x18,0xfe,0x42,0x38,0x9c,0x61,0x77,0xb0,0x52,0xe3,0xd8,0xd1,0x7f,0x88,
+  0x23,0xbb,0x76,0xed,0x2e,0x2c,0x2e,0x36,0xb7,0xb2,0x76,0x73,0xf7,0x4a,0x4d,0xcf,
+  0x7e,0x50,0xf7,0xa4,0x7f,0x60,0x80,0xdf,0xb4,0x75,0x6e,0x5e,0x01,0x8f,0xc3,0x1c,
+  0xd6,0xb3,0x08,0x0b,0xf7,0xf4,0xb9,0xec,0xee,0xe5,0x9b,0x96,0xc1,0x78,0xd8,0xd0,
+  0xd4,0x3f,0x40,0x85,0xbf,0x2d,0x6d,0xed,0x0b,0x3f,0x7b,0xcb,0x5a,0x16,0xa0,0x4b,
+  0x7e,0x01,0x01,0x19,0xd9,0x0c,0x2d,0x2d,0x6d,0xc0,0x82,0xf5,0x0d,0x4d,0x9d,0x9c,
+  0xdd,0x43,0xc3,0xa3,0xf3,0x0b,0x8b,0x1f,0x3e,0x6a,0xec,0xeb,0x1f,0x00,0xcc,0x68,
+  0xca,0x5c,0xf0,0xdf,0xaf,0x1a,0x9b,0x9a,0xbf,0xd8,0xb0,0x69,0xee,0x54,0x14,0xc0,
+  0x3d,0x69,0x63,0x6b,0x47,0x67,0x30,0x63,0xe2,0x92,0x8b,0x4b,0xcb,0x9e,0x34,0xc2,
+  0x24,0x32,0x01,0x5f,0xf5,0xef,0xcb,0x46,0xc6,0x46,0x8e,0x1d,0xff,0x9d,0xfa,0x76,
+  0xa2,0xc9,0xca,0xe7,0x15,0x14,0x5a,0x58,0xd9,0xc2,0x70,0xf7,0xa2,0xb2,0xb6,0x0e,
+  0x88,0xbf,0xd4,0xd5,0xa8,0xdf,0xcc,0x00,0x65,0x77,0x73,0xf7,0xa4,0xe8,0x09,0x78,
+  0x8a,0xcb,0x2a,0xaa,0x9c,0x5c,0xdc,0x42,0xc2,0x23,0xc0,0x42,0x07,0xc2,0x5f,0xfe,
+  0x97,0xb7,0xbe,0xfe,0x51,0x36,0x83,0x41,0xcf,0xce,0xce,0xa4,0x67,0xa7,0x67,0x64,
+  0x83,0x85,0xbb,0x77,0x1f,0x08,0xde,0x9f,0xfe,0xc1,0x81,0x5d,0xbb,0x67,0x71,0x0e,
+  0xbc,0x1b,0x5b,0x4a,0xdb,0x27,0x63,0x88,0x87,0x40,0x4f,0x82,0x2c,0xc6,0xf5,0xd6,
+  0xa2,0x60,0x24,0x2c,0x1d,0x18,0xaa,0x53,0x1a,0xb3,0x71,0x89,0x27,0xf2,0xf4,0x28,
+  0xb7,0x3a,0xf0,0xd4,0x68,0xe7,0x29,0xc2,0x17,0x44,0xd1,0x40,0x9c,0x87,0x72,0xdd,
+  0xd4,0xdc,0x5f,0x67,0x98,0x78,0xc5,0x8a,0x15,0x62,0x32,0x20,0xc6,0x4f,0x09,0xb0,
+  0x46,0x81,0x4c,0xe0,0x13,0xcd,0xb4,0xe2,0xb0,0x88,0x4f,0xbc,0x42,0x62,0x8e,0x60,
+  0x51,0x1e,0xd5,0x24,0x32,0x65,0x13,0xf4,0x13,0x6d,0x4c,0xb4,0x80,0x16,0x10,0x4a,
+  0x12,0x4d,0x11,0xa8,0x8a,0x3e,0x27,0x27,0x6d,0x49,0x6b,0x78,0x0c,0xb5,0xcc,0xd5,
+  0xee,0xe8,0x25,0x0e,0x84,0x0b,0x98,0x60,0x61,0xcf,0xe8,0x58,0xe8,0x40,0xeb,0xcc,
+  0xf1,0x91,0x83,0xa2,0x39,0x5b,0xc1,0xb8,0x53,0xd6,0x88,0x25,0x67,0xd4,0x0d,0x07,
+  0x3f,0xfa,0xcd,0x34,0x9d,0x07,0xb2,0x17,0xee,0xc9,0x9c,0xae,0x94,0x3f,0xc1,0x90,
+  0x3e,0x92,0x22,0xa5,0x16,0xa9,0xef,0xc9,0x9c,0x78,0x4e,0x35,0x85,0xf1,0x1e,0xad,
+  0xbc,0xa2,0xea,0xc7,0x5d,0x7b,0x76,0xed,0xde,0xa3,0xae,0x71,0xfc,0x9c,0x96,0x8e,
+  0x85,0x8d,0xab,0x87,0x4f,0x50,0xc4,0xb5,0xf8,0x84,0xa4,0x94,0xd4,0x8c,0xcc,0x94,
+  0x74,0x7a,0x5c,0x42,0x5a,0xd8,0x95,0x48,0x57,0x4f,0x7f,0x2b,0x1b,0x7b,0xed,0xf3,
+  0xba,0xc7,0x8e,0x9f,0xdc,0xaf,0x72,0x68,0xdb,0xf6,0x1d,0x4a,0x5f,0x7f,0xa3,0xa8,
+  0xa8,0x28,0x2d,0x2d,0xb3,0xfa,0xf3,0x35,0x80,0x02,0x43,0x39,0xca,0xe5,0x42,0x4b,
+  0x16,0xe3,0x10,0x0c,0xd3,0x81,0x31,0xf1,0x04,0xa2,0x34,0x30,0xbf,0xb4,0x7d,0xf2,
+  0xfa,0xd5,0xab,0xd7,0x64,0xe7,0x31,0x9d,0x5c,0x3d,0x82,0x42,0xae,0x5e,0x2f,0x28,
+  0x69,0x69,0x83,0x29,0x33,0xef,0xe5,0xc5,0x58,0x57,0xd7,0x20,0x2f,0xa7,0xc0,0xd3,
+  0x55,0x4d,0x2d,0xad,0x0c,0x3a,0xdd,0xe7,0x72,0x20,0x9d,0x71,0xfd,0xe1,0xa3,0x66,
+  0x7e,0xde,0x60,0x60,0x63,0xe3,0x63,0xeb,0x15,0x37,0xfe,0xc3,0xc7,0x59,0x78,0x85,
+  0x08,0x83,0x79,0xdd,0xdd,0xcb,0xdb,0xd5,0xc3,0x37,0x29,0x2d,0xe3,0xee,0xfd,0x86,
+  0xbe,0xfe,0x21,0x7e,0x12,0x7c,0x0f,0x1b,0x1e,0xf1,0x54,0xa3,0x58,0x30,0x7f,0x81,
+  0x9f,0x7f,0x80,0x7f,0x60,0xb0,0x93,0x9b,0x6f,0x6a,0x7a,0xd6,0x83,0xfa,0xc7,0x30,
+  0x13,0x93,0x7f,0xed,0x54,0x36,0x87,0xb3,0x42,0x44,0xa0,0x7a,0x52,0xaf,0x65,0x2b,
+  0x84,0x84,0x43,0x42,0xc3,0x12,0x92,0x92,0x2f,0xea,0xea,0x69,0x9f,0xbf,0x68,0x70,
+  0xc9,0xd4,0xde,0xd1,0x25,0x32,0x2a,0x36,0xb7,0xa0,0xac,0xfe,0x51,0x53,0x5f,0x3f,
+  0x0c,0x2a,0xe6,0x81,0x89,0x1b,0xb5,0xb7,0x36,0x7f,0x35,0x4b,0xb8,0xd1,0x1b,0x1b,
+  0xb8,0x27,0x0d,0x2f,0x19,0x5d,0x8b,0x8e,0x73,0x74,0x70,0x4b,0x4c,0x4a,0xbb,0x75,
+  0x17,0x16,0x83,0x9e,0x78,0xfe,0xaf,0xc6,0xdf,0xb1,0x67,0x63,0x9a,0x9a,0x5a,0xd4,
+  0x63,0x12,0x49,0x09,0xc9,0xbc,0xfc,0x7c,0x2b,0x1b,0x27,0x30,0x5a,0x66,0xe6,0x17,
+  0x37,0xb7,0x76,0x0e,0x53,0x56,0x2b,0x78,0x63,0x03,0xff,0xab,0xc0,0x40,0xaa,0x7a,
+  0x88,0xab,0x56,0xae,0xba,0x71,0xeb,0x16,0xe0,0xbf,0x60,0x18,0x5f,0x58,0x5c,0xd1,
+  0xde,0xd9,0x39,0x32,0xf2,0x6c,0xee,0x2e,0x2f,0xc0,0x5f,0x13,0x33,0x0b,0x30,0x5a,
+  0x7e,0xef,0x29,0x6c,0x8b,0x25,0x95,0x65,0x75,0x1b,0xf0,0x08,0x2b,0x0c,0xcb,0x28,
+  0x10,0x87,0x07,0xa7,0xc8,0xd0,0xc6,0xb3,0x2f,0x4f,0x0b,0xc4,0xaf,0xe4,0x16,0x08,
+  0x40,0x24,0x35,0x38,0xf9,0x15,0x41,0x2a,0xce,0x8e,0xd1,0xaf,0xe6,0x7d,0x64,0xbf,
+  0x2e,0xc2,0x32,0x1a,0xce,0x3a,0x39,0x88,0xdb,0x12,0x08,0x4b,0x6e,0x50,0x6e,0x2a,
+  0x22,0x4f,0x3f,0x3b,0x9e,0x35,0x33,0x62,0x37,0x3a,0x05,0xd4,0x14,0x1a,0x18,0x90,
+  0x8f,0x8b,0x3a,0xa6,0x68,0x4e,0x56,0xc5,0xe4,0xe0,0x40,0x8f,0x45,0x41,0xc3,0x65,
+  0x33,0xac,0x4b,0xdc,0x88,0xe8,0xf5,0xa6,0x9d,0x00,0x7f,0xe5,0x2e,0xb5,0x29,0x1a,
+  0x37,0x02,0x0a,0x4c,0xd3,0xae,0xa5,0x69,0xdd,0xa0,0x9d,0x2a,0x92,0x3b,0x9e,0x2a,
+  0xfd,0x5b,0xfc,0x1f,0x36,0xcc,0x21,0xfe,0xd2,0x43,0xef,0xd7,0xe8,0x74,0xc6,0xb6,
+  0x1f,0xb6,0xef,0xde,0xf3,0xf3,0x91,0xa3,0xc7,0xcf,0xeb,0xe8,0xd9,0xd9,0xbb,0xfa,
+  0xf9,0x07,0xc7,0xc4,0x25,0x24,0xa7,0x65,0xa7,0xd1,0x73,0x33,0xb3,0x99,0xc9,0x69,
+  0x59,0xd1,0xb1,0xf1,0x7e,0x01,0xc1,0x8e,0xce,0x1e,0x7a,0xfa,0x46,0x27,0x4e,0x9e,
+  0x39,0xf4,0xdf,0xff,0xed,0xdc,0xb5,0xef,0xbb,0xef,0x95,0x37,0x6c,0xd8,0x20,0x2f,
+  0x2f,0x2f,0x21,0x29,0x29,0xbe,0x6a,0xa5,0xb0,0xb0,0xd8,0xf2,0xe5,0x30,0x17,0x09,
+  0x40,0x30,0x51,0x17,0x78,0xc1,0xbc,0x05,0x28,0x16,0x9a,0x78,0x34,0x90,0x3b,0x9a,
+  0xdf,0x0d,0x2c,0x22,0x22,0xca,0xc8,0x65,0xba,0xba,0x7b,0xf9,0x07,0x87,0x33,0xf3,
+  0x8a,0x9b,0x5a,0xdb,0x28,0xea,0xfa,0xf1,0x7d,0x3f,0xfc,0xcd,0xf7,0xab,0xe0,0x4d,
+  0x35,0x36,0x37,0x6f,0xd8,0xc0,0x0b,0xa0,0xc6,0x66,0x66,0xf1,0x49,0xc9,0x1e,0x5e,
+  0x97,0xc1,0x65,0xa9,0x7b,0xd8,0xf8,0xd7,0xd0,0x10,0xbf,0x12,0xf3,0x00,0xcb,0x44,
+  0x66,0x13,0x2c,0x9a,0xd5,0x3e,0xfc,0xe0,0xc3,0x90,0xf0,0xf0,0xb0,0x88,0xab,0x6e,
+  0x9e,0xbe,0x49,0xa9,0x19,0x0f,0xea,0x1a,0xb0,0x88,0xaf,0x99,0x3b,0xdc,0xf9,0xb4,
+  0x5b,0x7e,0xea,0x74,0xf3,0xfc,0x8f,0xe7,0xbb,0x7b,0x7a,0x05,0x87,0x86,0xbb,0xba,
+  0x79,0xa6,0xa4,0x65,0x23,0x25,0x40,0x8a,0x50,0x9f,0xfe,0xc1,0xa1,0x55,0xb3,0x89,
+  0x3c,0xbc,0x81,0x81,0x7f,0xf7,0x9a,0x35,0x6b,0xd2,0x33,0x33,0xaf,0x46,0x44,0x9e,
+  0xbf,0xa0,0xa3,0xad,0x63,0x70,0xc9,0xc4,0xcc,0xc5,0xdd,0x07,0x20,0x60,0x71,0x69,
+  0xe5,0x93,0xa6,0x56,0x70,0x5c,0x9e,0x2c,0x33,0x30,0xc6,0xc8,0x61,0x5e,0x97,0x94,
+  0x94,0x9e,0x8b,0x37,0x2a,0xb8,0xaa,0xba,0xba,0xba,0xb1,0x09,0x49,0xf6,0x8e,0xae,
+  0x09,0x89,0x29,0x50,0x66,0xad,0xb7,0x0f,0x0a,0x44,0xfc,0x8b,0xf1,0x77,0x7c,0xe2,
+  0x99,0xbe,0xe1,0x25,0xea,0x69,0x65,0x30,0x76,0xa5,0xe7,0xe6,0xd8,0xda,0x3b,0x5d,
+  0xf6,0x0b,0x66,0x5e,0x07,0xf8,0xdb,0x41,0x5d,0xf8,0xfe,0x9f,0x3c,0x4a,0x31,0xb1,
+  0x71,0x14,0x3d,0x59,0x26,0xb4,0xac,0xa2,0xaa,0x1a,0xf0,0xdf,0x40,0x8c,0x89,0xb7,
+  0xb4,0x75,0x8d,0x8d,0xcf,0x21,0xfe,0xbe,0x82,0xfe,0x81,0xd1,0x92,0xd2,0x32,0x0d,
+  0x8d,0xe3,0xef,0x37,0x7e,0xef,0x33,0x71,0x25,0xe9,0x8b,0x4f,0x68,0xa6,0xc4,0xb4,
+  0x26,0x0b,0x39,0x54,0xc9,0xf4,0x90,0x0c,0xa9,0x44,0x40,0x2f,0xe1,0x80,0x05,0x6b,
+  0x90,0x03,0x96,0xfc,0x2b,0x0d,0x6b,0x0a,0xed,0xcb,0xf3,0x2b,0xfa,0x44,0xbf,0x12,
+  0x3e,0x5b,0x2e,0x9e,0x72,0xc8,0x8d,0x23,0x6f,0x2d,0xee,0xb3,0xc5,0x42,0x9b,0xd6,
+  0xc2,0xa8,0xe9,0x49,0x1c,0x24,0x6f,0x40,0x84,0x39,0xe1,0x94,0xd6,0xa4,0x77,0x7a,
+  0x83,0xe4,0xce,0xa3,0x8e,0x11,0xfd,0x21,0x9f,0xaf,0x1c,0x4c,0xda,0x9d,0xe2,0x43,
+  0x26,0x63,0x34,0xd9,0xf9,0xcc,0xf5,0x6c,0x73,0x85,0xa3,0xd1,0x57,0xe3,0x0e,0xec,
+  0xc4,0xf1,0xa6,0x68,0x66,0x7d,0xeb,0xcc,0x61,0xaf,0xd6,0x9a,0xf7,0x82,0x21,0x84,
+  0xbc,0x59,0xaf,0xa2,0x05,0x5c,0x09,0xeb,0x23,0x1b,0xb3,0xd7,0x9b,0x76,0xc9,0x1b,
+  0x36,0x29,0x18,0x36,0xd2,0x74,0xea,0xe4,0xb4,0x6e,0xc8,0x9e,0x2a,0x92,0xff,0x23,
+  0x5b,0x46,0x3d,0xe6,0xb0,0x69,0x16,0xbb,0xff,0x5f,0x5a,0x88,0x30,0x3a,0x36,0x0e,
+  0x20,0xe9,0x9e,0x7d,0x07,0x8e,0x1e,0x3f,0xa9,0xab,0x67,0xe8,0xe2,0xe6,0x1d,0x14,
+  0x7a,0x35,0x3e,0x31,0x35,0x8b,0xc1,0xcc,0xcb,0x2f,0xca,0xbd,0x5e,0x98,0x95,0x9d,
+  0x97,0x90,0x94,0x1e,0x76,0xf5,0x9a,0x87,0xcf,0x65,0x13,0x73,0x2b,0x40,0x61,0xd4,
+  0x8f,0x1c,0xff,0x69,0xff,0xc1,0x1f,0x76,0xec,0xfa,0x6a,0xb3,0x12,0xd4,0xc2,0x92,
+  0x91,0x41,0xb9,0xc0,0x22,0x22,0x50,0x0e,0x0b,0xab,0x0b,0x8c,0x4f,0x04,0xa3,0xa4,
+  0x60,0x48,0x81,0xb1,0xbc,0xe0,0x59,0x5f,0xa7,0x4b,0x96,0x2e,0xc9,0x62,0x30,0xdc,
+  0x3d,0x7d,0x00,0xdc,0x33,0x73,0x8b,0x1e,0x37,0xb6,0x50,0x70,0x4c,0xbe,0x2f,0x8d,
+  0x57,0x5c,0xfb,0xfb,0x15,0x2a,0x3e,0x4b,0x54,0xb1,0x17,0xdc,0x95,0x0d,0x06,0xed,
+  0xdf,0x7c,0xcd,0x2b,0x0b,0xe0,0xe8,0xe2,0x1a,0x11,0x15,0xed,0xee,0xe1,0x93,0x96,
+  0x09,0xe3,0xaf,0xa0,0xb0,0x3c,0x1f,0x3a,0xd9,0xd8,0xdc,0xb2,0x78,0xd1,0x5b,0xf0,
+  0xe5,0x9a,0x9a,0x59,0x00,0xe6,0xeb,0xe9,0xed,0x97,0x96,0x99,0x5d,0xf7,0xb0,0x61,
+  0x70,0x90,0x6f,0xa1,0x43,0xc0,0x02,0xbe,0x56,0xfa,0x86,0xbc,0xef,0x47,0x1f,0x7e,
+  0x64,0x6e,0x61,0x19,0x19,0x1d,0xeb,0xe2,0xe6,0x9e,0x9c,0x9a,0x8e,0x2b,0x01,0xf2,
+  0xaf,0x7a,0x3c,0x34,0x32,0x2c,0x2d,0x25,0x68,0x3d,0x8b,0xd7,0xb5,0x0d,0x1b,0xbf,
+  0x64,0x30,0x19,0xfe,0xfe,0x01,0xe7,0x2f,0xe8,0x6a,0x5f,0xb8,0x68,0x66,0x61,0xeb,
+  0xe6,0xe1,0x1b,0x13,0x97,0x5c,0x51,0x79,0xa3,0xb1,0xb9,0x63,0x68,0x78,0x78,0xe2,
+  0xf9,0x14,0x69,0xac,0xe7,0x2f,0x9f,0xc7,0x27,0x26,0x8b,0x89,0x89,0xbf,0xf5,0x9e,
+  0x80,0xfb,0xf0,0xcc,0xd9,0xb3,0xc9,0x69,0xa9,0xb6,0x8e,0x6e,0xb1,0xf1,0x29,0x50,
+  0x58,0x83,0xc3,0x41,0x89,0x5d,0x2f,0x61,0xb1,0x8f,0x97,0xe4,0x3b,0x87,0x2c,0xdc,
+  0xf4,0xba,0xb7,0x10,0xb1,0x31,0x6a,0x84,0xbc,0x3b,0x58,0x43,0x21,0x09,0x35,0xdd,
+  0xc0,0xf8,0xc4,0xcc,0xd2,0x92,0x5a,0xdc,0x43,0x4c,0x44,0x2c,0x3d,0x33,0xcb,0x01,
+  0x0b,0x77,0x67,0xe6,0x15,0x82,0x3b,0x70,0x68,0x78,0x54,0x90,0xe0,0x25,0x68,0x7f,
+  0x73,0x4f,0x19,0x15,0x6b,0xe6,0xf3,0xe0,0x10,0x9f,0x19,0x0c,0x3a,0x45,0x4f,0xc0,
+  0x9d,0x5f,0x54,0x5a,0xe6,0xea,0xe1,0x1d,0x18,0x1c,0xc6,0x28,0x28,0x7b,0xdc,0xdc,
+  0x3e,0x3a,0xf6,0xda,0x23,0x81,0xc9,0x6e,0x10,0xbd,0x42,0xeb,0xf9,0x9f,0x11,0xb8,
+  0x81,0x5d,0x5d,0xdd,0xc8,0x65,0x31,0xdf,0xb1,0x7d,0x2a,0xfa,0x85,0xb4,0x4e,0xbd,
+  0x82,0x19,0xcc,0xb2,0x21,0x26,0x34,0x91,0xdf,0x95,0xc2,0x90,0xee,0x13,0xd9,0x13,
+  0x8b,0xf6,0x15,0xe4,0x2b,0x4f,0x3b,0x3c,0x9f,0xb2,0xfc,0x43,0x9b,0x66,0xdc,0x1d,
+  0x83,0x63,0x36,0x79,0x47,0xfc,0x14,0x4c,0xba,0x79,0x8e,0x32,0xfd,0x2b,0xcf,0xfa,
+  0x29,0x46,0x88,0x45,0xff,0x9f,0xb9,0xeb,0x8e,0x8a,0xea,0xd8,0xff,0xff,0xc4,0xbc,
+  0xf7,0xce,0xcf,0x34,0x35,0x46,0x23,0x79,0xb1,0x25,0x20,0x6d,0x45,0xd0,0x24,0x26,
+  0xcf,0x18,0x93,0x98,0x68,0x62,0x34,0x9a,0x44,0x93,0x97,0x97,0x58,0xd2,0x5e,0x0c,
+  0x28,0xbd,0x6c,0x01,0xa4,0x77,0x56,0xfa,0xc2,0xd2,0x11,0x29,0x02,0x22,0xd2,0x61,
+  0xc1,0x65,0x97,0x2e,0x20,0x45,0x10,0xa5,0xee,0x2e,0x2c,0x4b,0x57,0x9a,0x9a,0x73,
+  0x7e,0xdf,0x99,0xb9,0x7b,0x25,0xab,0xbb,0x26,0xb1,0xe4,0x9d,0xf3,0x3d,0xf7,0xdc,
+  0x32,0x77,0x66,0xee,0xdc,0xef,0xcc,0x67,0x3e,0x33,0xdf,0xf9,0xce,0x9d,0xed,0x21,
+  0xe6,0x6d,0x18,0xa1,0x7c,0x3a,0x3f,0x93,0xda,0xf4,0xd6,0x8d,0xe8,0x3e,0x12,0x1d,
+  0xea,0x04,0xa1,0xad,0x1e,0xeb,0xce,0x77,0x91,0xa7,0xfa,0x4c,0x62,0xdf,0xd5,0xaf,
+  0x67,0xdb,0x03,0xf8,0xab,0x6b,0xd9,0xa1,0x67,0x56,0xaf,0xfb,0xd3,0x05,0xdd,0x23,
+  0x05,0xaf,0xfc,0x3b,0x6d,0x87,0x65,0x56,0x8f,0x74,0xf8,0x8f,0x6a,0xe0,0xe3,0x91,
+  0xa8,0xe8,0xd8,0xb7,0xb6,0xbc,0xb3,0xe3,0xa3,0x4f,0xbe,0x3d,0xf8,0xbd,0x95,0xb5,
+  0x9d,0xa7,0x4f,0x60,0x54,0x4c,0x62,0x6a,0xc6,0xf9,0xfc,0xc2,0x92,0xe2,0x52,0x91,
+  0xa0,0x5c,0x58,0x50,0x24,0xc8,0x3a,0x97,0x97,0x90,0x94,0x1a,0x14,0xc6,0x3b,0xe1,
+  0xea,0x65,0x6e,0x69,0x77,0xe4,0xbb,0x9f,0x3e,0xdd,0xb7,0xff,0xfd,0x0f,0x3e,0x7a,
+  0x63,0xf3,0x9b,0xc6,0xc6,0x26,0x7a,0x7a,0x06,0x40,0x55,0x5e,0x5e,0xb9,0x72,0x85,
+  0x16,0xb5,0x29,0xd2,0xe2,0x45,0x4b,0x9e,0x79,0x8a,0x5a,0x8e,0x44,0xfc,0x62,0xa1,
+  0x7d,0x09,0x9f,0xa4,0x56,0x24,0x69,0x40,0x61,0x78,0x25,0x25,0x3d,0x2d,0x30,0x38,
+  0x28,0x30,0x38,0x02,0xf0,0xbf,0xfd,0x0a,0xda,0x17,0x46,0xc3,0xa6,0x27,0x44,0x00,
+  0x04,0xa1,0xb9,0x9e,0x9e,0x9d,0xbd,0x31,0x3d,0x35,0x35,0x3d,0x3d,0x3d,0x03,0x32,
+  0x03,0xc4,0x19,0x4e,0x66,0x66,0xc9,0xc9,0xcc,0xd4,0xcc,0x34,0x3c,0x25,0x77,0x66,
+  0xd5,0xfb,0x05,0xa2,0x45,0x32,0x20,0xdd,0xf6,0xae,0xea,0x8a,0x0f,0xff,0x40,0x6e,
+  0x4c,0x6c,0xbc,0xa7,0x6f,0x40,0x7a,0xe6,0xb9,0x86,0xa6,0xe6,0x91,0xd1,0x51,0x75,
+  0x2b,0x23,0x5a,0x2f,0x77,0x3c,0x88,0xf1,0x15,0x2d,0x07,0x0f,0x1f,0x86,0x3f,0xc1,
+  0x3d,0x19,0x9a,0x9d,0x83,0x4a,0x63,0x6c,0x62,0x42,0xdd,0xfc,0x2f,0x3c,0xda,0xb2,
+  0x65,0xab,0x0a,0xd0,0x58,0x58,0x5a,0x25,0xa7,0xa4,0x7a,0x7a,0xf9,0x9c,0x4e,0xcd,
+  0xba,0xd8,0xd8,0x2a,0x1f,0x52,0x68,0x18,0x7f,0x86,0x02,0x54,0xe7,0x09,0xf0,0xa1,
+  0xa0,0xde,0x96,0x2d,0x6f,0x17,0x95,0x94,0xf8,0xfa,0x05,0x98,0x9a,0x59,0x1c,0x33,
+  0xb7,0x06,0x08,0xf6,0xe5,0x86,0xa7,0xa4,0x67,0x8a,0x2a,0x6b,0xba,0x7b,0x7b,0xc7,
+  0x27,0xae,0x53,0x83,0x09,0xca,0xd6,0x75,0xe6,0xe6,0x6c,0x70,0x48,0xd8,0xa3,0xd8,
+  0xce,0xe6,0xc0,0x81,0x2f,0x33,0xb2,0xce,0x3a,0xbb,0x78,0xc6,0x25,0x9c,0x2e,0x17,
+  0x56,0xf6,0xf4,0x49,0x46,0x47,0xc7,0xf0,0xc2,0xb4,0x59,0x40,0x8a,0x69,0xac,0x33,
+  0xa0,0x27,0xa0,0x33,0x53,0x48,0x73,0x40,0x69,0x66,0x40,0x09,0xef,0xbb,0x4a,0x88,
+  0x06,0x0e,0x08,0x39,0x3b,0x37,0x0b,0xe5,0x09,0xda,0x88,0xb4,0x6e,0x7a,0x0e,0x62,
+  0xa3,0x74,0x92,0x52,0x48,0xa4,0xa5,0x28,0xfe,0xe9,0x29,0xd4,0xf1,0xd0,0xb8,0x14,
+  0xfd,0x36,0x1e,0x10,0xf0,0xf2,0xf6,0xd5,0x6c,0x19,0xbe,0x74,0xe9,0x0b,0xc8,0xdc,
+  0xdd,0xcb,0x87,0x1b,0x14,0x9e,0x79,0xbe,0xe8,0xca,0xd5,0xfb,0x98,0xbb,0xdf,0x56,
+  0xc2,0x19,0xa8,0x04,0xaa,0x20,0xa8,0x6e,0xa0,0x1a,0x82,0x6a,0x0a,0x14,0xc2,0xcc,
+  0xcc,0x8d,0xa9,0x69,0xba,0x34,0xc8,0x11,0x04,0x4a,0x03,0x3a,0x03,0xc5,0xa5,0x02,
+  0x4d,0x30,0xb4,0xf0,0xa9,0x62,0x41,0x89,0x8f,0x7f,0x60,0x48,0x18,0xbf,0xa8,0x44,
+  0xd0,0x71,0xb5,0x9b,0x18,0x53,0xdd,0x2f,0x27,0xb7,0xe6,0x6e,0x42,0x41,0xcd,0x92,
+  0xf2,0x99,0x42,0x19,0x98,0x82,0xd3,0x69,0x9c,0x1f,0x54,0xaf,0xa1,0x0c,0x71,0x31,
+  0x22,0x1d,0x56,0x03,0xc1,0x10,0x2c,0x35,0x2d,0x7d,0xd5,0xaa,0x35,0x7f,0xc9,0x58,
+  0x34,0xe0,0xaf,0xae,0xf9,0x65,0x6d,0xe2,0xc9,0x59,0x49,0x4b,0xe7,0x13,0x3d,0xfa,
+  0xa8,0x9c,0x69,0x55,0xa8,0xd8,0x29,0xd1,0x4c,0x50,0x85,0x96,0xce,0xe7,0xce,0x77,
+  0x8f,0x4e,0xab,0x30,0x53,0x6d,0xa5,0xb9,0x14,0x0d,0xa0,0xf3,0x58,0x2d,0x35,0xd4,
+  0x8c,0x3c,0x56,0xd9,0x93,0x7d,0x06,0xd1,0x1e,0x82,0xda,0xd8,0x75,0xd5,0x1d,0xd3,
+  0x2c,0x07,0xca,0x19,0x35,0x8e,0x4d,0x41,0x16,0x52,0xad,0x23,0x7b,0x17,0x2a,0xed,
+  0xa0,0x88,0x1f,0xad,0x57,0xe9,0x0d,0x07,0x89,0x7f,0x48,0x07,0xe4,0x80,0x9a,0x5e,
+  0xe8,0x44,0x76,0x4e,0x54,0x82,0xec,0xfc,0x17,0xb1,0x45,0x34,0xd9,0x67,0xc1,0x4e,
+  0x46,0x26,0xaf,0x11,0xc3,0x45,0x8b,0xb3,0x10,0xcf,0x65,0xb0,0x65,0xc4,0xe1,0x06,
+  0x83,0x33,0xa8,0xc7,0x42,0x88,0xac,0xcf,0x06,0x92,0x2b,0xd7,0x67,0x2b,0x0c,0xa1,
+  0xf4,0x00,0x70,0x59,0x0a,0x74,0x07,0xe8,0x30,0x1b,0xc1,0xb1,0x21,0x1b,0x95,0x95,
+  0x9e,0x9d,0x44,0xd7,0x5e,0x6a,0x68,0xdb,0xa9,0x63,0x71,0x45,0xff,0x58,0x83,0xee,
+  0x51,0xb1,0xde,0x0f,0x45,0x8c,0x83,0x99,0xdb,0xcd,0xb3,0xdb,0x7a,0x14,0x8f,0x01,
+  0x4c,0xff,0x84,0x24,0x25,0x9f,0x7e,0x7b,0xeb,0xbb,0x3b,0x77,0xed,0x39,0x7c,0xf8,
+  0x07,0x6b,0x5b,0xa6,0x9f,0x3f,0x97,0x1f,0x97,0x9c,0x79,0xf6,0x7c,0x51,0x49,0x79,
+  0x79,0x45,0x75,0x85,0x48,0x2c,0xb8,0x50,0x95,0x57,0x50,0x92,0x9a,0x9e,0x15,0xc5,
+  0x4f,0xf0,0xf1,0x3d,0x69,0xe7,0xc0,0xf9,0xef,0xcf,0xc7,0x0e,0x7c,0x85,0x28,0xf0,
+  0x96,0xad,0xef,0xe0,0x1d,0x09,0xd7,0xeb,0xe8,0xe8,0xac,0x59,0xb3,0x56,0xeb,0xe5,
+  0x7f,0x22,0x8f,0x58,0x04,0x82,0x17,0xe3,0xe5,0x48,0x4f,0x3d,0x45,0x06,0xa2,0x89,
+  0x53,0x4a,0x72,0xd4,0xb0,0x62,0x08,0x02,0x27,0xa7,0x24,0x03,0xf9,0xe5,0x06,0x85,
+  0x9c,0x3b,0x5f,0x70,0xb9,0xe3,0x2a,0x46,0x1c,0x4d,0xad,0x07,0x34,0x77,0x50,0x61,
+  0xc7,0xc6,0xc7,0x07,0xe5,0x23,0x12,0xe9,0x40,0x9f,0x44,0xde,0xdb,0x27,0xe9,0xed,
+  0x93,0xf5,0x4b,0x64,0x7d,0xfd,0x70,0x1c,0xe8,0xed,0xeb,0xef,0xeb,0x87,0xa3,0x14,
+  0x2e,0x25,0x52,0xb9,0x6c,0x60,0x10,0x78,0x2b,0xd4,0x62,0xcd,0x0d,0xc2,0xe0,0x90,
+  0x7c,0xe7,0x8e,0x5d,0x2a,0xd9,0x0b,0xe0,0x72,0xf9,0x31,0x31,0xae,0x9e,0xde,0xa7,
+  0x52,0x32,0x6a,0xeb,0x9b,0x06,0xe5,0x43,0xea,0xf0,0xf7,0x5a,0x77,0xf7,0x43,0xe1,
+  0xbf,0xfb,0xf7,0x1f,0x28,0x28,0x2a,0x0d,0x8d,0x88,0x2c,0x2c,0xa9,0xc0,0xb3,0xe1,
+  0x6a,0xf6,0xd2,0xfd,0x15,0xed,0xde,0xbb,0xed,0xdd,0xf7,0x54,0x20,0xef,0xe8,0x2f,
+  0xa6,0x19,0x99,0x19,0xee,0x9e,0x40,0xf4,0x32,0x6a,0x1b,0x9a,0x14,0xc3,0xc8,0xde,
+  0x49,0x03,0x70,0xbc,0xf1,0xc6,0x5b,0x8f,0xae,0x75,0x82,0xbf,0xff,0xd9,0xe7,0x5f,
+  0x08,0x84,0xe5,0xce,0xae,0xee,0x47,0xd1,0x0e,0x0d,0x36,0x1c,0x27,0xd7,0xe0,0x90,
+  0xa8,0xf4,0x8c,0x9c,0xba,0x86,0x86,0x7e,0xa9,0xec,0x6e,0x93,0xd7,0xf1,0x89,0x49,
+  0x37,0x57,0x0f,0xcd,0x0e,0xff,0xff,0x84,0xec,0xd9,0xbb,0x37,0xfb,0xfc,0x79,0x47,
+  0x67,0x97,0xb0,0xc8,0xe8,0xdc,0xfc,0x92,0xc6,0x4b,0x6d,0xd7,0xba,0xfa,0x40,0x49,
+  0x7a,0x7a,0xfb,0xb1,0xce,0x80,0xe6,0x80,0xb6,0x48,0x7b,0x7a,0xfb,0xfa,0x24,0x03,
+  0x7d,0x52,0xd9,0xa0,0x5c,0x31,0x82,0x00,0x5a,0xad,0x0b,0xc4,0xf9,0x02,0x38,0x31,
+  0x31,0x39,0x25,0x1f,0x1a,0x91,0x0d,0x0c,0x41,0x9c,0x10,0x61,0x2f,0x3a,0xa2,0x08,
+  0x89,0x4e,0xa2,0x3b,0x7d,0x24,0x21,0xa9,0x74,0x00,0x02,0x8e,0x01,0xfd,0xbf,0x79,
+  0xfb,0xde,0x86,0x7c,0xca,0x5f,0x73,0x2b,0x34,0x2c,0xfc,0xff,0x34,0x9a,0xf8,0x2e,
+  0x7a,0x6e,0x71,0x4a,0x5a,0x9a,0x97,0x8f,0x2f,0xae,0x3b,0xc8,0xdc,0x7d,0x72,0xf2,
+  0x86,0x66,0xc7,0x17,0x00,0x64,0x00,0xb4,0x63,0xe3,0x93,0xf0,0x81,0x12,0xe9,0x10,
+  0x54,0x1c,0xc8,0x21,0xd4,0x14,0x54,0x6b,0x70,0x95,0xc1,0xe7,0x54,0x9e,0xe9,0x4f,
+  0x80,0xef,0x12,0x8a,0x44,0x1a,0x72,0xf2,0x8f,0xbf,0xff,0x03,0x3a,0x5a,0x01,0xdc,
+  0x20,0x6e,0x30,0x2f,0xbf,0x10,0x8d,0x62,0x8d,0x4d,0x68,0xf2,0xde,0x7c,0x1b,0xfb,
+  0xb0,0x02,0xe8,0x84,0x0e,0xed,0x80,0x7c,0xa4,0xaf,0x5f,0xa2,0xac,0xbc,0x32,0x5c,
+  0x73,0xa9,0x5c,0x49,0x65,0x03,0xf0,0x2b,0xa0,0xd2,0x69,0xae,0xbf,0xd0,0xf3,0x89,
+  0x8d,0x4b,0x58,0x72,0x97,0x3b,0x9a,0xc7,0x20,0x80,0xbf,0xaf,0x9a,0xb5,0xe8,0x52,
+  0x83,0xa8,0x77,0xc6,0x63,0xd5,0xc9,0x7c,0x4b,0x27,0x25,0xbd,0x1d,0x54,0x09,0x43,
+  0x4f,0xcb,0xaa,0xc8,0x6f,0xdf,0x92,0xd3,0x80,0x3b,0x7f,0xda,0x57,0x5b,0x69,0xf8,
+  0x44,0x27,0x44,0x6f,0x6e,0x48,0xb0,0x92,0xc4,0x4c,0x25,0x4a,0xdc,0x80,0x28,0xbd,
+  0x82,0x90,0xf9,0x62,0xcc,0x40,0xa9,0x35,0xb9,0x78,0x36,0x56,0x41,0x8c,0x96,0xb5,
+  0x95,0xdb,0x23,0xd2,0x89,0xd2,0x27,0x64,0xb4,0x59,0x47,0x69,0x38,0xad,0x6f,0xdf,
+  0x4f,0xf9,0x0c,0xc1,0x83,0xde,0xf4,0x8c,0xed,0x7c,0xbb,0x2f,0xfa,0x12,0x9e,0x22,
+  0x8b,0x71,0x16,0xd5,0x69,0x61,0xb0,0x31,0x2f,0x66,0x61,0x47,0x1c,0x78,0xb6,0x57,
+  0x1b,0xcf,0xfc,0xea,0x61,0xe4,0x25,0x4f,0x19,0x1c,0x85,0x1e,0x0b,0x47,0xcb,0x1c,
+  0x36,0x72,0xe8,0x61,0x38,0x48,0x00,0x7f,0x0d,0x6d,0x3a,0x0c,0x2c,0x5a,0xf4,0x8e,
+  0x8a,0x8d,0x7e,0x2e,0xd4,0x3f,0x92,0xfb,0x89,0x5d,0x6e,0xa7,0x74,0xfc,0x2f,0x87,
+  0xda,0x7b,0x4a,0x51,0x71,0xf1,0x7b,0xef,0x7f,0xb0,0x6b,0xf7,0xbe,0xc3,0x47,0x7e,
+  0xb4,0xb1,0x63,0x7a,0x73,0xc3,0xe3,0x12,0x53,0xb2,0x73,0xf2,0x4b,0xca,0x2a,0x2b,
+  0xaa,0xeb,0x6a,0x6a,0x2f,0x8a,0xc4,0x55,0x82,0x72,0x71,0x76,0x4e,0x5e,0x42,0x62,
+  0xea,0xc9,0xe0,0x70,0x77,0x0f,0x5f,0x73,0x2b,0xdb,0x43,0x87,0x7f,0xdc,0xfb,0xd9,
+  0x57,0xef,0x6d,0xff,0xf8,0xcd,0xb7,0xde,0x36,0x31,0xd9,0x64,0x60,0x60,0xb0,0x76,
+  0xed,0x2b,0xd8,0x16,0xfa,0x9f,0xcb,0x5f,0xd4,0x7a,0x7e,0xe9,0x8b,0x4b,0x97,0x2e,
+  0x5d,0xf4,0x2c,0x82,0x60,0xbc,0x28,0xf8,0x69,0x6a,0x20,0x7a,0xc1,0x93,0xd4,0xb6,
+  0x35,0x4f,0xaa,0x2e,0x4a,0x22,0x6d,0x2c,0x3c,0x8d,0x89,0x8b,0xe7,0x45,0xf2,0x03,
+  0x82,0x22,0xb2,0x73,0x10,0xfe,0xe2,0x39,0x56,0xf5,0xfc,0x17,0xef,0x5a,0x2b,0x57,
+  0x8c,0x76,0x74,0x5e,0x03,0x40,0x14,0x8a,0x6a,0x4a,0x4a,0xcb,0x05,0x65,0xe2,0xd2,
+  0x32,0x61,0xa9,0x40,0x58,0x5c,0x2a,0x2c,0x11,0x08,0xe1,0xbc,0x18,0x1f,0xcb,0x2e,
+  0x08,0x05,0x17,0x44,0x10,0xac,0xad,0xfd,0x1a,0xf1,0xe5,0xab,0x01,0xd9,0x87,0x47,
+  0x47,0x3f,0xff,0x62,0xbf,0x4a,0xfd,0x82,0xc6,0x2d,0x32,0x2a,0xe6,0x84,0xab,0x57,
+  0x3c,0xf0,0x26,0xb4,0x21,0xbb,0x7c,0x4a,0xcd,0x12,0x0f,0xb9,0x62,0x78,0xc5,0x8b,
+  0x0f,0x61,0xec,0xf4,0xc0,0x97,0x5f,0x15,0x0b,0xca,0x80,0xa6,0x09,0x45,0xd5,0xd0,
+  0x0a,0xa9,0xdd,0x33,0xe2,0x57,0x80,0xaa,0xeb,0x5b,0xdf,0xd9,0x36,0xff,0xdd,0x05,
+  0x4f,0x2c,0xf8,0xf6,0xe0,0x21,0xf8,0x95,0xae,0x1e,0xbe,0x49,0x29,0xe9,0x35,0x75,
+  0x97,0x06,0x06,0xe5,0x1a,0xf8,0x2f,0xc8,0xf6,0xed,0x1f,0x3e,0xd2,0x06,0x0a,0x7e,
+  0xfd,0x37,0xdf,0x7c,0x5b,0x21,0x16,0x3b,0xb0,0x1d,0x01,0x81,0x8f,0x5b,0xdb,0x3a,
+  0x9e,0x70,0x09,0x0a,0x8b,0xcc,0xc8,0xce,0xab,0xa9,0x6b,0xea,0x97,0x0e,0x5e,0x9f,
+  0x9a,0x56,0xf1,0x9a,0x38,0x3d,0x3b,0x67,0x76,0xcc,0xfc,0x99,0xfb,0xed,0x7e,0xfb,
+  0x87,0xe4,0xc3,0x1d,0x1f,0xe5,0xe4,0x15,0x30,0xd9,0xce,0x5e,0xfe,0x21,0xb1,0x09,
+  0x49,0xd9,0xe7,0x0a,0x0a,0x8a,0x04,0x45,0x02,0x61,0x59,0xb9,0xa8,0xa4,0xb4,0xa2,
+  0x14,0x6b,0x8b,0xa0,0x4c,0x58,0x54,0x2a,0x14,0x94,0x57,0x08,0x2b,0x6a,0x6a,0xeb,
+  0x1b,0x41,0x67,0xe0,0x9f,0xa2,0xd9,0x10,0x8d,0xc3,0xb9,0x80,0x23,0x00,0x67,0xbd,
+  0xfd,0x92,0xfa,0xc6,0x56,0x71,0x55,0x5d,0xc9,0x05,0x51,0x11,0xa8,0x62,0x39,0xd2,
+  0x43,0xa4,0x8a,0x44,0x1b,0x4b,0xe1,0x28,0x16,0x20,0x85,0xac,0x14,0x57,0xd5,0x37,
+  0x35,0x5f,0xee,0x96,0x0c,0x8e,0xdf,0xa7,0x9f,0x79,0x2b,0x3a,0x26,0x6e,0xe1,0xbd,
+  0x26,0x37,0xc9,0xb0,0xd2,0x13,0x78,0xb5,0x32,0x3f,0x36,0x86,0x7b,0x32,0xdc,0x17,
+  0x2f,0x37,0x6b,0x6b,0xbf,0x0a,0x38,0xa5,0xb9,0xee,0xdf,0xb8,0x31,0x0b,0x3d,0x8b,
+  0xce,0x6b,0xbd,0x75,0xf5,0x97,0x84,0x15,0x55,0x90,0xab,0x62,0x65,0xc5,0x41,0x35,
+  0xa8,0x8c,0xce,0x2d,0x16,0x81,0xb8,0xa8,0x04,0xbe,0x42,0x54,0x55,0x53,0x27,0xaa,
+  0xaa,0xbd,0xa7,0x77,0x56,0x22,0x80,0xbf,0x99,0xd9,0xd9,0xd0,0x56,0x70,0x83,0x42,
+  0x73,0xf3,0x4b,0x5b,0xdb,0xaf,0xdc,0x40,0x0e,0xac,0xd4,0xe2,0x2f,0x7c,0x38,0x54,
+  0x46,0xe8,0x88,0x40,0x9f,0xa1,0xb6,0xbe,0x41,0x28,0xac,0x21,0x7f,0x81,0x24,0x0d,
+  0x89,0x16,0xe3,0xa2,0x83,0x56,0xe8,0x82,0xa8,0xaa,0xba,0xae,0xa1,0xa5,0xad,0x5d,
+  0x3a,0x20,0x1b,0x1d,0x9f,0x54,0xe7,0xd6,0x72,0xee,0xd6,0x4d,0x6f,0x1f,0xdf,0xc7,
+  0x39,0x17,0x4c,0x9a,0xaf,0x67,0x57,0x6e,0xd6,0xb6,0xe8,0x24,0x28,0x43,0x4f,0xc8,
+  0xce,0x67,0xbe,0x0c,0x36,0x3e,0x32,0x11,0x3a,0xd3,0x00,0xb4,0x0e,0x11,0x3d,0x85,
+  0x01,0x53,0x42,0x66,0x8a,0x29,0xac,0xb9,0x0b,0x52,0xe1,0x5d,0xfa,0x29,0x8d,0xdd,
+  0x06,0xac,0x41,0x32,0x60,0x3b,0xdf,0xc2,0x8a,0xb6,0x25,0x5e,0xa7,0x5c,0x38,0x4c,
+  0x99,0x4e,0xcd,0x4b,0x88,0xc0,0x19,0x4d,0xa5,0x19,0xd8,0x22,0x8b,0x98,0x36,0x21,
+  0x6a,0x79,0xc7,0xa6,0x4b,0xae,0xcb,0x44,0x33,0xad,0x24,0x12,0x00,0x3e,0x1d,0x26,
+  0x61,0xdc,0xf2,0x75,0xcc,0x21,0xb8,0x54,0xe9,0x33,0xd0,0x66,0xd5,0x10,0x33,0x70,
+  0x52,0x1d,0x5c,0x14,0x10,0x21,0xba,0x64,0x21,0x37,0xd7,0xf0,0xc8,0x90,0x4d,0x8d,
+  0x72,0xc3,0x7d,0x06,0x1b,0x65,0xd2,0x80,0x35,0xa4,0x8b,0x27,0x76,0x21,0x66,0xb8,
+  0xa9,0x07,0x09,0xb1,0xe0,0x29,0xf9,0x3a,0x3c,0x95,0x8c,0x49,0x2e,0x46,0x5b,0x24,
+  0x10,0x18,0x22,0x81,0xdc,0x9a,0x70,0x14,0xfa,0xac,0xe1,0xf5,0x9c,0xe1,0xf5,0x6c,
+  0x84,0xdd,0x46,0xcc,0x01,0x06,0x53,0x66,0x60,0xd7,0xcd,0xb0,0xbb,0xba,0xde,0xb2,
+  0x71,0xbd,0x45,0xbd,0xe1,0x2f,0x15,0xeb,0x7f,0xc8,0x39,0xe0,0x52,0x3c,0x34,0xfe,
+  0x48,0x6c,0x11,0x1f,0x5c,0x2a,0xab,0xab,0x77,0xec,0xfc,0xf8,0xe3,0x5d,0x7b,0x8e,
+  0x1c,0xf9,0xd1,0xd6,0x9e,0xe3,0xcf,0x0d,0x89,0x4f,0x4a,0x39,0x97,0x9b,0x5f,0x56,
+  0x51,0x59,0x55,0x5b,0x5f,0x77,0xb1,0xb9,0xae,0xee,0xa2,0xa8,0xb2,0x1a,0x1a,0xa8,
+  0xb4,0x33,0x59,0xbc,0xa8,0x18,0x3f,0x9f,0x93,0x0e,0x4c,0xce,0xd1,0x5f,0x8e,0x7f,
+  0xfd,0x9f,0x83,0xbb,0x76,0x7f,0xba,0xed,0xdd,0xf7,0x81,0x02,0x1b,0x1b,0x9b,0x10,
+  0x08,0x5e,0xb9,0x7a,0x95,0xd6,0xcb,0x2f,0xbd,0xb0,0x4c,0xeb,0x85,0x17,0x90,0x5f,
+  0xca,0x45,0x8b,0x16,0x01,0x0d,0x7c,0x7a,0xe1,0xd3,0x4f,0x2f,0x7c,0x96,0xb0,0x60,
+  0x6a,0x69,0xd2,0x93,0x94,0x83,0x4a,0xda,0x1c,0x0b,0x0d,0x4d,0x3f,0xb1,0x00,0xf0,
+  0x37,0x24,0x3c,0x22,0x3a,0x36,0x2e,0x90,0x1b,0x92,0x71,0xf6,0x7c,0x6b,0xdb,0x95,
+  0xe1,0x51,0x4d,0xf8,0x0b,0x94,0x61,0x62,0xe2,0xfa,0xb5,0xee,0x1e,0x71,0x55,0x4d,
+  0xe6,0xd9,0xdc,0xf8,0xc4,0xd3,0x51,0x31,0x89,0x3c,0xb4,0xb4,0x33,0x21,0x32,0x3a,
+  0x81,0xc7,0x8f,0x07,0x89,0x8c,0x8a,0x8f,0xe4,0x23,0xe1,0xc7,0x24,0xc5,0xc5,0x9f,
+  0x06,0x6a,0x7f,0xa1,0xa2,0xb2,0xf3,0x5a,0x37,0x72,0xe7,0xab,0x3e,0xe6,0x89,0xeb,
+  0x93,0xdf,0x1e,0x52,0x75,0xcb,0xc3,0x76,0x72,0x8a,0x49,0x48,0x02,0xd6,0xc6,0x8b,
+  0x8c,0x85,0xc6,0x19,0xef,0x68,0x70,0xef,0xdf,0x3a,0x35,0x33,0xbd,0xe9,0x7e,0x0e,
+  0x03,0x7f,0x8f,0x7c,0xf7,0xfd,0x0f,0x17,0x84,0x15,0x19,0x59,0x39,0xf5,0x0d,0x4d,
+  0xd0,0xfe,0xab,0x1b,0x8a,0xbf,0x79,0x0b,0xb9,0x68,0x78,0xe3,0x8d,0xcd,0x2a,0xaf,
+  0xef,0xd9,0xfb,0x69,0x7e,0x61,0x89,0xbb,0x97,0x5f,0xfc,0xa9,0x94,0xea,0xda,0xa6,
+  0x81,0x41,0x85,0x06,0xfe,0x0b,0xb2,0x7b,0xf7,0x23,0x77,0x22,0x04,0x30,0x61,0x7a,
+  0xdc,0xbc,0xb8,0xb4,0xcc,0xde,0x81,0xfd,0x8b,0x99,0xb9,0xb5,0xad,0x83,0xb3,0xab,
+  0x47,0x14,0x3f,0x3e,0x27,0xb7,0x18,0x78,0xa8,0x74,0x00,0x79,0x4d,0x54,0x71,0x97,
+  0xd4,0xdb,0xdf,0x7f,0xf0,0xe0,0xe1,0xdf,0xbf,0x87,0xc5,0x7d,0x65,0xeb,0xd6,0x77,
+  0x72,0xf3,0x0b,0xad,0xec,0x1c,0x38,0x4e,0x6e,0x5e,0x3e,0xfe,0xc1,0xa1,0xbc,0x70,
+  0x5e,0x74,0x04,0x3f,0x36,0x12,0xab,0x0d,0x48,0x54,0x74,0x22,0x1c,0xe1,0x0e,0x9c,
+  0xc4,0x25,0x24,0xa7,0x9d,0x39,0x57,0x2e,0xac,0xba,0xd2,0x89,0x16,0x50,0xa3,0x2d,
+  0x9c,0xd4,0x01,0xe5,0xaf,0x88,0xfc,0x0e,0x0c,0x0e,0x5d,0x6a,0x6e,0xcf,0xcd,0x2f,
+  0x4e,0x4e,0x49,0x8f,0x89,0x4f,0xa6,0x94,0x10,0x09,0x15,0x33,0x2f,0x2a,0x0e,0x29,
+  0x67,0x74,0x5c,0x6c,0xfc,0xa9,0xe4,0x94,0x4c,0xf8,0x41,0x97,0x9a,0x3b,0x80,0xd6,
+  0x69,0xd8,0xea,0x0b,0xf0,0x37,0x39,0x25,0x55,0x9d,0x23,0x71,0x52,0x83,0x00,0x10,
+  0x43,0xc2,0xc2,0x42,0x42,0x23,0x00,0x7f,0xb3,0xb2,0xf3,0x5b,0xda,0xae,0x8c,0x8e,
+  0x4d,0x68,0xe0,0xbf,0x10,0x27,0xf0,0xee,0xee,0x1e,0x49,0x65,0x55,0x4d,0x56,0x36,
+  0xd4,0x9d,0x54,0x94,0x37,0x7e,0x9c,0xb2,0x04,0x12,0x54,0x72,0x4e,0xca,0x27,0x8a,
+  0x9f,0x70,0xea,0x74,0x5a,0x6d,0x6d,0x9d,0x86,0xa5,0xe2,0x90,0x9f,0xd3,0xa9,0x69,
+  0x61,0x11,0x91,0xd0,0x19,0xc8,0xce,0x2b,0x68,0x69,0xef,0x9c,0xbc,0x3e,0xa9,0x81,
+  0xff,0x82,0xf6,0x4e,0x4c,0x5e,0xbf,0xda,0xd5,0x57,0x21,0xae,0xcd,0x3c,0x9b,0x13,
+  0x97,0x98,0xcc,0x87,0x4e,0x38,0x3f,0xee,0x4e,0x2d,0x8e,0x89,0xc7,0xa9,0xc7,0xc5,
+  0xc4,0x41,0xe2,0x99,0xf9,0x45,0x25,0xd5,0x75,0x4d,0xdd,0xbd,0x52,0xe8,0xb4,0xdc,
+  0x54,0x63,0x00,0x29,0x95,0x49,0xf7,0xee,0xfb,0xfc,0x51,0x2b,0xb3,0x8a,0x3c,0xb7,
+  0x76,0xab,0xb6,0xe5,0x35,0x64,0xda,0xc4,0x1c,0xd4,0x65,0x62,0xe4,0xc2,0x74,0x4f,
+  0x9f,0x4d,0x0d,0x0e,0xc3,0x1d,0x72,0x84,0x3b,0x78,0x84,0x19,0xd0,0x50,0x0a,0x98,
+  0x48,0xc6,0x5a,0x91,0x00,0x7a,0x02,0x0e,0x12,0x5b,0x23,0x78,0x8a,0x29,0x9e,0x21,
+  0x7b,0x88,0xbc,0x85,0x9e,0x32,0xd1,0x18,0xb2,0x3e,0x82,0x1b,0xfa,0x52,0x61,0xc0,
+  0x1a,0x40,0xc0,0xca,0xa2,0x5e,0xd1,0x65,0x62,0xa3,0x2f,0x26,0x40,0x24,0x9a,0x30,
+  0xc5,0x6c,0x51,0x4e,0x27,0x44,0xc5,0x80,0xf1,0x17,0x6e,0x02,0xae,0x19,0xe0,0x73,
+  0x3d,0x02,0xee,0xf8,0x92,0x02,0x41,0xa6,0xdc,0x10,0x81,0xa0,0x82,0x04,0x30,0x60,
+  0xc9,0x11,0x2c,0x32,0xa5,0x70,0x07,0xa2,0x05,0x7c,0xc4,0xeb,0x80,0x14,0x0c,0x74,
+  0x82,0x02,0xc3,0xbb,0x10,0x1e,0x92,0x60,0xe0,0xb7,0x20,0x1b,0xe4,0x45,0x06,0x6b,
+  0x00,0x9e,0x1a,0x00,0x4b,0x45,0xb8,0x4f,0x72,0x25,0x27,0xa4,0x95,0x5c,0xae,0x43,
+  0x91,0xc3,0xf9,0x10,0xb1,0xaa,0x22,0x93,0xbc,0x80,0xb0,0xc8,0xc2,0x0a,0xf7,0x0a,
+  0xa0,0xb8,0xc8,0x38,0x33,0x70,0x5e,0x94,0x0a,0x46,0x61,0x84,0xbc,0x8e,0x28,0x18,
+  0x03,0x1d,0x87,0x0d,0x1c,0x06,0x8d,0xd8,0x43,0xd0,0xb7,0x31,0x74,0xe8,0x33,0xb0,
+  0xeb,0x32,0xb0,0x6e,0xdf,0x60,0x51,0xc7,0x30,0x15,0x19,0xfd,0x98,0xf3,0x13,0xb7,
+  0x72,0x62,0x4a,0xd3,0x40,0xd0,0x5f,0x28,0x97,0x5a,0x5b,0x77,0xef,0xfd,0x6c,0xe7,
+  0xae,0x3d,0x87,0x10,0xff,0xe5,0x04,0x06,0x85,0x26,0x26,0xa7,0xe5,0x15,0x14,0x57,
+  0x88,0xeb,0xea,0x1a,0x9a,0x1b,0x2f,0x5d,0xbe,0xd8,0xd4,0x52,0x53,0xd7,0x28,0x28,
+  0xaf,0x04,0x42,0x9a,0x78,0x2a,0x35,0x24,0x3c,0xd2,0xd5,0xdd,0xdb,0xc2,0xc6,0xee,
+  0xc7,0x9f,0x8e,0xee,0xfb,0xe2,0xcb,0x8f,0x76,0xed,0xd9,0xb2,0x75,0xdb,0xa6,0xd7,
+  0x5e,0x67,0x30,0x18,0x7a,0x7a,0x7a,0xab,0xd7,0xae,0x59,0xb9,0x6a,0xe5,0x8b,0x5a,
+  0x5a,0xcb,0x96,0x6b,0x2d,0x59,0xb2,0x14,0xf9,0xc5,0x7a,0x0e,0x99,0x63,0x11,0x0a,
+  0x4c,0x04,0xba,0xc7,0xc4,0x1c,0x8b,0x5a,0x97,0x34,0x6f,0x17,0x57,0x20,0xc8,0x7e,
+  0xfe,0x01,0x71,0x09,0x89,0x08,0x7f,0xb3,0x72,0x5a,0x5a,0x01,0x7f,0x47,0x35,0xf4,
+  0x9c,0xe7,0xe6,0x6e,0x02,0x8c,0xb6,0xb4,0x75,0xe4,0xe6,0x17,0x85,0x47,0xc6,0xba,
+  0x7b,0xfb,0x73,0x5c,0x3c,0x9c,0x9c,0x5c,0x39,0x8e,0xae,0xd0,0xb4,0xb2,0x1d,0x5d,
+  0x38,0xce,0xae,0x6c,0x27,0x17,0x47,0x67,0x77,0x16,0xe7,0x84,0xd3,0x09,0x0f,0x77,
+  0x4f,0xdf,0x90,0xd0,0xc8,0x8c,0xac,0xdc,0x8b,0x8d,0x2d,0xd0,0xdf,0x9e,0x51,0xef,
+  0x16,0xfe,0xfa,0xd4,0x8d,0x9f,0x8f,0xfe,0xa2,0x52,0xbf,0xcc,0x8e,0x1f,0x3b,0x9d,
+  0x96,0x0e,0xdd,0x8f,0x93,0xc1,0x40,0xcf,0xd1,0xb6,0xad,0xd0,0xc4,0xa9,0x9b,0x8d,
+  0x3a,0x74,0xf8,0xfb,0x07,0x9f,0x84,0x62,0x73,0x1c,0x85,0xa2,0xca,0xe2,0xd2,0xf2,
+  0xce,0x6b,0x3d,0xe3,0x13,0x93,0xea,0xfc,0x77,0x41,0x23,0x24,0x91,0x49,0x0c,0x19,
+  0xaa,0xfe,0xe7,0xdf,0xdf,0xfe,0x61,0x51,0x89,0xc0,0xc3,0xcb,0x1b,0x18,0xb4,0xb8,
+  0xba,0xa1,0x5f,0x36,0xa8,0xc1,0xfe,0x0a,0xe4,0xeb,0xff,0x7c,0xf3,0x18,0x9a,0x29,
+  0x50,0x00,0x4f,0x5f,0xef,0x73,0xf9,0xf9,0x56,0x36,0x0e,0xa6,0x66,0x16,0x56,0x36,
+  0xf6,0xf0,0x5f,0x22,0xa3,0xe3,0x0b,0x0a,0xcb,0x80,0xda,0x0c,0xca,0x47,0x6e,0x4c,
+  0x4d,0xa9,0x0c,0xc6,0x76,0xf5,0xf6,0xec,0xdc,0xf9,0xf1,0xc3,0xda,0x5d,0xce,0x64,
+  0xe3,0xa6,0xf3,0x05,0x79,0x96,0x36,0xf6,0x66,0x56,0x36,0xb6,0x0e,0x6c,0x16,0xdb,
+  0x09,0x94,0x84,0x08,0x74,0xae,0xe8,0x73,0xd0,0x1f,0xc7,0x13,0x6e,0x6e,0x1e,0xde,
+  0x81,0x21,0xbc,0xb4,0x33,0x67,0x2f,0x36,0xb6,0x92,0x19,0x07,0x0d,0x03,0xc5,0xd7,
+  0x6f,0x4c,0x77,0xf5,0xf4,0x57,0x88,0xab,0xe3,0x13,0x53,0xfc,0x03,0x43,0x1c,0x5d,
+  0x3c,0x41,0x03,0x91,0x40,0xb4,0x8e,0x94,0x2a,0x92,0xc8,0x1d,0x9d,0x3d,0x4e,0xb8,
+  0x7a,0xfa,0x05,0x04,0x27,0x9c,0x4a,0x11,0x56,0xd6,0xf4,0xa0,0x2d,0x9e,0x35,0x91,
+  0xeb,0xdc,0xbc,0xbc,0x45,0xcf,0x2e,0xd2,0x5c,0xaa,0xde,0xbe,0x68,0xc9,0xad,0x8f,
+  0x5f,0x50,0x66,0x56,0x4e,0x73,0x6b,0x3b,0x5a,0x6e,0x76,0x53,0xad,0xb5,0x12,0x68,
+  0xc2,0xe8,0xf8,0x38,0xd0,0x64,0xa8,0xec,0xbc,0xa8,0x58,0x2f,0x5f,0xae,0x8b,0xab,
+  0x27,0x55,0x71,0x94,0x45,0x81,0xc5,0x0d,0xf2,0x8c,0xb2,0xed,0x88,0x0b,0xc4,0xd9,
+  0xc5,0xd7,0xff,0x24,0xf4,0xcd,0x17,0x2f,0xd1,0xe4,0x69,0x33,0x26,0x21,0x3e,0x22,
+  0x32,0x8a,0x1b,0x14,0x7e,0x36,0x27,0xbf,0xb5,0xbd,0x73,0x0c,0x55,0x13,0xf5,0xbb,
+  0x07,0xce,0xce,0x29,0x86,0x47,0xa0,0xb2,0x43,0x9d,0x0a,0xe5,0x45,0xbb,0x7a,0xfa,
+  0x72,0x9c,0xdc,0x1d,0x9d,0xdc,0x9c,0x4e,0x50,0x65,0xc5,0x76,0x76,0x87,0x6c,0x40,
+  0x66,0x5c,0xdc,0x3c,0xbd,0x7c,0x03,0x20,0xb7,0xd9,0x39,0xb9,0x17,0x9b,0x5a,0x65,
+  0x83,0x43,0x6a,0xfb,0x93,0xbf,0xde,0x2e,0xaf,0x10,0x3d,0x14,0x1b,0x8c,0xdf,0x2f,
+  0xcf,0x1b,0x7c,0xa4,0x67,0xd3,0xa3,0x87,0xe0,0x09,0x61,0xa8,0x21,0x6b,0x90,0xd8,
+  0x5f,0x11,0x03,0x21,0x6c,0x29,0x84,0xd8,0xa8,0x21,0x53,0xb6,0x0e,0x39,0x40,0xa6,
+  0x46,0x4d,0xf1,0x42,0x1b,0x02,0x61,0xc8,0x94,0x48,0x17,0xf1,0x41,0x19,0x86,0x27,
+  0xf2,0xae,0x8c,0xb6,0x38,0xc2,0x4f,0xe5,0xd8,0x00,0x78,0x90,0x80,0x3b,0x36,0x9a,
+  0xa2,0x2c,0x94,0x68,0x53,0x25,0x94,0x1c,0x6b,0x98,0x8e,0x5f,0x0f,0xd9,0x5c,0x11,
+  0x23,0x25,0xe8,0x12,0xa0,0x77,0xf5,0x99,0x0a,0x3a,0x24,0xc4,0xac,0xc3,0x9c,0x17,
+  0x98,0xa9,0x1c,0x25,0xc6,0x27,0xb4,0xe1,0x93,0xb6,0xc3,0x6f,0x92,0xa0,0x2f,0xa9,
+  0xc0,0xac,0xdf,0x04,0xa6,0xdf,0xa5,0xe2,0x64,0x23,0xdc,0x24,0xb9,0x22,0xa3,0xca,
+  0xb4,0x49,0x15,0x15,0x21,0xe6,0xd1,0xd4,0x11,0x07,0x33,0x44,0x53,0xba,0x48,0x7e,
+  0x73,0xc9,0xa1,0x6e,0x12,0xd9,0xe0,0x88,0x21,0x98,0x5c,0x72,0x80,0x6e,0x2b,0x36,
+  0xb0,0x65,0xc6,0x6c,0xa9,0x11,0xb3,0xd7,0x98,0xd9,0xa9,0x6f,0xdd,0xb9,0xd1,0xa6,
+  0x61,0x93,0x45,0xa5,0xf1,0xd1,0x02,0x7b,0xfe,0xc5,0x59,0x35,0xfd,0xb4,0xbf,0x5c,
+  0xba,0x7a,0x7a,0xf6,0x7f,0xf9,0x6f,0xc0,0xdf,0x6f,0x0f,0xfd,0x60,0x6d,0xcb,0x0e,
+  0xe4,0x06,0x27,0x25,0xa7,0xe6,0xe6,0x97,0x88,0xc4,0x35,0x8d,0x97,0x5a,0x9a,0x5b,
+  0x3b,0xa0,0x23,0xdd,0xd0,0xd4,0x5a,0x5d,0x53,0x5f,0x58,0x5c,0x96,0x9e,0x79,0x0e,
+  0x58,0x24,0x84,0x61,0x72,0x4e,0x98,0x1e,0xb3,0xf8,0xfa,0x9b,0x23,0x9f,0xee,0xdb,
+  0xbf,0xfd,0x83,0x9d,0x6f,0xfe,0x6b,0xcb,0xc6,0x4d,0xaf,0x19,0x19,0x19,0x69,0x6b,
+  0xeb,0x20,0x16,0xbc,0x6a,0x95,0xd6,0x4b,0x2f,0x2d,0x7f,0x71,0xc5,0xd2,0xa5,0xcb,
+  0x9e,0x5f,0x82,0xa6,0x83,0x9f,0x79,0xe6,0x59,0x7a,0x9b,0x60,0x95,0x6d,0x1a,0x08,
+  0x16,0x3f,0xa1,0x74,0xc7,0xe1,0xe2,0xee,0x9e,0x9c,0x02,0x6d,0x57,0x30,0xa4,0x05,
+  0x84,0x68,0x78,0x64,0x7c,0xee,0xd6,0x9c,0xba,0x76,0x09,0xf8,0xe0,0xd0,0xf0,0x58,
+  0x53,0x73,0x2b,0x90,0x5f,0x68,0xca,0x98,0x6c,0x67,0x4b,0x2b,0x3b,0x53,0x73,0x2b,
+  0x53,0x0b,0x6b,0x33,0x0b,0x1b,0x74,0x34,0xb7,0x86,0x4b,0x33,0x73,0x1b,0x38,0x9a,
+  0x5b,0xd9,0xd9,0xd8,0xb3,0x3d,0x7d,0x02,0xa0,0xab,0x5f,0x59,0x5d,0x2f,0x95,0x0d,
+  0xcd,0xdc,0xb5,0xf2,0x94,0x96,0x1b,0xd3,0x53,0x96,0x56,0xd6,0x2a,0xf5,0xeb,0xf3,
+  0x2f,0xf6,0xe7,0xe4,0xe5,0x5b,0xdb,0x31,0xbd,0x7d,0x02,0x4e,0xa7,0xa2,0xa5,0xa3,
+  0x68,0x5b,0xde,0xb9,0x7b,0xff,0x59,0x5e,0x14,0xff,0x01,0x47,0x4d,0xff,0xf6,0xe4,
+  0xdf,0x62,0x13,0xe2,0x2b,0xab,0xeb,0x6a,0xeb,0x1b,0x24,0x32,0xf9,0xd4,0xf4,0xec,
+  0xbd,0xdb,0x52,0x34,0x08,0x3f,0xdb,0xd6,0xde,0x71,0xb7,0xc3,0xae,0xb7,0xfe,0xf5,
+  0xb6,0x40,0x58,0xee,0xe1,0xe5,0x17,0x1b,0x9f,0x8c,0x76,0x3d,0x96,0x0d,0xce,0x68,
+  0xdc,0x0a,0xd3,0xf4,0xd8,0xf1,0x3f,0xba,0x65,0xd5,0x9f,0x93,0xe5,0xcb,0x96,0xfb,
+  0x05,0xf8,0x65,0x64,0x9f,0xb5,0xb4,0xb1,0x43,0x6b,0x82,0xed,0xd8,0x1e,0x1e,0x01,
+  0x90,0xc9,0xa2,0x92,0xb2,0xe6,0xd6,0xce,0xe1,0x91,0x91,0xe9,0x99,0x39,0xf8,0x2e,
+  0xfa,0xef,0x00,0x7b,0x6a,0x6e,0x6b,0x05,0xde,0xfa,0x50,0xb2,0xa7,0xab,0xa7,0x9f,
+  0x57,0x58,0x68,0x65,0x6d,0x07,0x04,0xdc,0xf4,0x98,0x95,0xa9,0x39,0x68,0x0b,0x12,
+  0xa4,0x2a,0x16,0xd4,0xb9,0xb9,0xa5,0xed,0x31,0x73,0xeb,0xe3,0x96,0x36,0x36,0x76,
+  0x2c,0x77,0x54,0x80,0x49,0x55,0xb5,0x75,0x12,0xa9,0x6c,0x46,0xc3,0x04,0xfa,0xaf,
+  0xb7,0xa7,0xa6,0x66,0xbb,0x7a,0xfa,0xca,0xca,0x45,0x11,0x68,0x9e,0xc2,0x03,0xba,
+  0x16,0x16,0x56,0xb6,0x28,0x66,0x2c,0x38,0x66,0x1b,0x9c,0x90,0xa5,0x99,0xa5,0x0d,
+  0x74,0x3f,0x4e,0xb8,0xb8,0x87,0x85,0x47,0x17,0x96,0x96,0x5d,0xed,0xea,0x55,0x37,
+  0x96,0x42,0x44,0x50,0x5e,0xae,0x79,0x8b,0x28,0xa8,0x47,0x6e,0xee,0x6e,0x71,0x09,
+  0x49,0xde,0xbe,0xdc,0xd3,0x19,0xe7,0x1b,0x9a,0xdb,0xf0,0x72,0x6f,0xf5,0xac,0xf3,
+  0xe6,0xed,0xe1,0x91,0x51,0xa8,0xe0,0xa8,0xee,0x9c,0x0c,0x61,0xb2,0x9d,0xa0,0x82,
+  0x98,0x5b,0xda,0x90,0x1c,0xce,0xcb,0x33,0xb9,0x03,0xb5,0xc9,0xca,0xdc,0x12,0xdd,
+  0xb7,0xe7,0x38,0x43,0x9f,0x70,0xd9,0x32,0x55,0xef,0xac,0xf3,0x25,0x2c,0x02,0xd4,
+  0x3f,0x06,0xaa,0x64,0x56,0x4e,0x5e,0x73,0x5b,0xa7,0x86,0x95,0x02,0xb7,0xf1,0x06,
+  0x58,0x80,0xbf,0xd0,0xbd,0x49,0x3d,0x73,0xd6,0x27,0x30,0xcc,0x9e,0xe9,0x08,0xbf,
+  0xc6,0xcc,0x9c,0x2e,0x2b,0x2b,0x3a,0x3f,0x90,0x43,0x3b,0x07,0x96,0x9b,0xbb,0x4f,
+  0x74,0x6c,0x42,0x69,0x99,0x08,0x28,0x33,0x14,0x9a,0xba,0x6f,0x84,0x76,0xe3,0x93,
+  0xdd,0x7b,0x1f,0x9b,0x21,0x16,0x24,0xb4,0xfc,0xf5,0xef,0xd6,0xd9,0x4a,0xf4,0x31,
+  0xa2,0x01,0x1c,0xe8,0xd0,0x50,0x88,0x05,0x53,0x48,0x05,0x26,0x86,0x98,0xdc,0xe1,
+  0x11,0x57,0x32,0xf4,0x8a,0x2f,0x09,0x17,0x06,0xac,0xc1,0x8f,0x30,0x7d,0x46,0xe4,
+  0x14,0xd0,0x16,0x0d,0x02,0xa3,0x77,0xd7,0x29,0x63,0x33,0x60,0x0d,0xd3,0x91,0x60,
+  0xeb,0xa3,0xe1,0x75,0xf6,0x98,0x72,0xa2,0x09,0x5c,0x84,0xe0,0x7a,0x4c,0x74,0x4e,
+  0x02,0x93,0x08,0x11,0x8a,0x51,0x89,0x52,0x88,0x89,0xd7,0xf2,0x50,0x1c,0x13,0xd9,
+  0x32,0x61,0x0c,0x05,0x9a,0x49,0x11,0x52,0x0e,0xc6,0x50,0xcc,0x3a,0xe1,0x11,0x7d,
+  0x49,0x07,0x46,0x14,0x1e,0xd3,0x52,0xcc,0xc7,0x29,0x9c,0x55,0xb9,0xd4,0x57,0xc6,
+  0x46,0x60,0x9a,0x9e,0xa8,0xd5,0xc5,0x94,0x96,0xe2,0xb3,0xf8,0x84,0xc4,0x6c,0x88,
+  0xe9,0x2d,0x61,0xb8,0x78,0x88,0x60,0x18,0xb8,0xed,0x7a,0x84,0xad,0x28,0x03,0x10,
+  0x18,0x8e,0x46,0x00,0xbb,0xec,0x31,0xe0,0xbf,0x46,0xf8,0xd2,0xd8,0x11,0x3d,0x35,
+  0x72,0x02,0x38,0x56,0x18,0x73,0x06,0x4d,0x38,0x03,0x26,0x9c,0x7e,0x13,0x56,0x97,
+  0xb1,0xc3,0x95,0x8d,0xd6,0xf5,0x9b,0x2c,0xab,0x36,0x9a,0x16,0x79,0xa7,0xb7,0xfe,
+  0xcf,0xae,0xee,0x97,0x0f,0xc9,0x0f,0x1d,0xf9,0x6e,0xc7,0xc7,0x9f,0x60,0xfc,0x65,
+  0xf9,0x07,0x72,0xe3,0x12,0x53,0xf2,0x0a,0x04,0xa2,0x4a,0x80,0x97,0xcb,0xad,0x97,
+  0x3b,0x5a,0x2f,0x5f,0x6d,0x69,0xeb,0xac,0x6f,0x68,0xae,0x10,0xd7,0xe4,0xe4,0x16,
+  0x24,0x25,0xa7,0x85,0x47,0x44,0xbb,0x78,0xfa,0xd9,0xda,0xb1,0x7e,0xfa,0xaf,0xe9,
+  0x57,0x5f,0x7d,0xb3,0xeb,0x93,0x7d,0xdb,0xde,0xfb,0x60,0xf3,0x9b,0x5b,0x8c,0x8d,
+  0x4d,0x0c,0x0d,0x0d,0x75,0x74,0x74,0x56,0xaf,0x5e,0xf3,0xf2,0xcb,0x6b,0x56,0x68,
+  0x69,0xd1,0xe6,0x58,0x4b,0x16,0xbf,0x40,0xfb,0xe5,0x78,0x7a,0xe1,0x33,0x64,0x3a,
+  0x98,0xec,0x57,0x08,0xfd,0x76,0x62,0x1d,0x4d,0x88,0x30,0x30,0xbe,0xb4,0xcc,0x4c,
+  0x1f,0xff,0x00,0xa8,0x8c,0x0d,0x80,0xbf,0xc3,0xa3,0x37,0x6f,0xa9,0x35,0x4d,0x81,
+  0x66,0xf9,0xfa,0x8d,0x99,0xce,0x6b,0xbd,0xa2,0xca,0x9a,0x33,0x19,0x39,0xd0,0x48,
+  0x86,0x46,0x44,0x87,0x84,0xf1,0x82,0xc3,0xa2,0x42,0xc2,0xa3,0x42,0x23,0x90,0x84,
+  0x84,0xf3,0x42,0x23,0xf8,0x61,0xe1,0xfc,0x50,0x5e,0x94,0xb7,0x1f,0xf7,0x84,0x9b,
+  0x47,0x4c,0x7c,0x92,0xb8,0xaa,0xa6,0x47,0x32,0xa4,0xc1,0x41,0x2e,0x5a,0xf1,0xc1,
+  0xe6,0xa8,0x54,0xb1,0x37,0x37,0xbf,0x55,0x54,0x5a,0xec,0xc0,0x74,0x74,0x71,0xf7,
+  0xe1,0xc7,0x26,0x56,0x88,0xab,0x7a,0xfa,0xa4,0x78,0x1e,0xf9,0x1e,0x2d,0x40,0x43,
+  0x63,0xe3,0x3a,0x9d,0x75,0x0f,0x52,0xa3,0xb5,0x56,0xbc,0x24,0xae,0xac,0xac,0xaa,
+  0xa9,0xed,0xb8,0xda,0x35,0x32,0x36,0xa6,0x6e,0x1c,0x00,0x3a,0x21,0x40,0x18,0x4b,
+  0xcb,0xcb,0x96,0x2c,0x7e,0x5e,0x25,0x86,0x8d,0xaf,0xbd,0x0e,0x4d,0xa5,0xa7,0x37,
+  0x82,0x36,0xa1,0xb8,0xa6,0x5f,0xa6,0xd0,0xec,0x89,0xc8,0xc2,0xca,0xfa,0xf1,0xe0,
+  0x2f,0xc8,0xea,0x55,0xab,0x53,0xd3,0xd2,0x13,0x4f,0x25,0x1d,0x43,0x7d,0x24,0x0b,
+  0x7b,0x96,0xa3,0x9f,0x7f,0x48,0xe2,0xa9,0xf4,0xb2,0x0b,0x95,0x57,0xbb,0xba,0xef,
+  0x69,0x5b,0x5e,0x2a,0x28,0xd7,0x37,0x30,0x7c,0xf0,0xa4,0x5f,0x59,0xfb,0x6a,0x85,
+  0x58,0xc4,0x8f,0x89,0x0b,0x45,0xba,0x81,0x54,0x25,0x18,0x24,0x14,0xa9,0x0a,0xd1,
+  0x1c,0x24,0x61,0xa0,0x3c,0x3c,0xd0,0x19,0x3f,0xff,0x93,0x6e,0xee,0x9e,0x3c,0x7e,
+  0x82,0x50,0x54,0x25,0x91,0xca,0x35,0xb8,0x52,0x24,0xf8,0x2b,0x1f,0x1a,0x6e,0x6a,
+  0xbe,0x9c,0x5f,0x58,0x9c,0x78,0x2a,0x25,0x82,0x1f,0x0b,0x31,0x28,0x63,0xbb,0xa3,
+  0x93,0xa1,0xe1,0x11,0xa1,0x11,0x91,0xdc,0xe0,0x70,0xa0,0x78,0x41,0x21,0x91,0xb9,
+  0x05,0x25,0xd8,0xd4,0x41,0xd3,0x20,0xad,0xb8,0xaa,0x6a,0xe9,0x92,0xa5,0x1a,0x3e,
+  0x0a,0xea,0x0e,0x93,0xc5,0x3c,0x75,0x3a,0xd5,0xc7,0xef,0x64,0xda,0x19,0xb4,0xdc,
+  0x6c,0x48,0xa1,0x69,0xb9,0xd9,0x6d,0x64,0x33,0x3f,0xd9,0xdd,0x2b,0x11,0x57,0xd5,
+  0x9d,0xc9,0x3a,0x17,0x1b,0x77,0x2a,0x34,0xf2,0x4e,0x0e,0xc3,0x79,0x31,0x90,0xe7,
+  0x10,0xba,0x34,0xd0,0x27,0xf0,0x50,0x81,0x44,0x44,0xf1,0x63,0xe3,0x1b,0x9a,0x2e,
+  0xad,0xd4,0xb8,0xb1,0x57,0x60,0x50,0x70,0x7c,0x42,0xa2,0x5f,0x40,0x50,0xe6,0xd9,
+  0xbc,0x4b,0x2d,0xed,0x9a,0xf1,0x17,0x14,0x78,0x7c,0x62,0x02,0x7a,0x20,0x17,0x2a,
+  0x2a,0xcf,0x64,0x9e,0xe3,0xf1,0x63,0x22,0xa2,0xa2,0x95,0x95,0x97,0xa4,0x1b,0x75,
+  0x32,0x38,0x1c,0x6a,0xdd,0x31,0x40,0x64,0x73,0x0b,0x26,0xc7,0x25,0x30,0x84,0x97,
+  0x97,0x5f,0xd2,0x76,0xf9,0xea,0xd8,0x98,0xa6,0x25,0xed,0x91,0x7c,0xfe,0x63,0xdb,
+  0x54,0x6b,0xc1,0x82,0xbf,0xaf,0x78,0x97,0xa9,0x6f,0x3f,0xc0,0xe0,0x20,0x50,0xd3,
+  0xc7,0x43,0xac,0x04,0x62,0x10,0x70,0x38,0xc8,0x31,0x7d,0x53,0x50,0x63,0xad,0x6c,
+  0xc4,0xe9,0x08,0x86,0x1a,0x60,0x3c,0xc5,0x9c,0x4e,0xf1,0x7b,0x2e,0xf5,0x10,0x46,
+  0x53,0xd1,0x12,0x3c,0x55,0x09,0xac,0xaf,0x14,0x62,0xa4,0x64,0x88,0x5f,0x31,0xc0,
+  0xf0,0x4a,0x20,0x98,0x81,0x87,0x76,0x09,0x2c,0x1a,0x12,0x2b,0x62,0x14,0x1e,0xf5,
+  0x0d,0xee,0x50,0x4e,0x14,0x9b,0x62,0x3e,0xd6,0x93,0x4b,0x3c,0x33,0x4b,0xa5,0x8b,
+  0x9f,0x2a,0x68,0x58,0x9f,0x7f,0xa9,0x7f,0xa7,0xcb,0x71,0x27,0x5d,0xf8,0x6a,0x54,
+  0x38,0x38,0x03,0x7a,0x04,0x52,0x71,0x59,0x19,0x60,0x28,0x07,0xa8,0x85,0x4b,0x7d,
+  0x8c,0xda,0x50,0x56,0x00,0xbb,0x0c,0xf6,0x98,0x2e,0x35,0xc8,0x8c,0x06,0x9c,0x37,
+  0x38,0xe1,0x4b,0x8e,0x02,0x98,0x2f,0xa0,0xf0,0x06,0xc7,0x31,0x88,0x01,0x42,0xc2,
+  0xe5,0x06,0x8c,0xbf,0x0c,0xb6,0xdc,0xc4,0x71,0x08,0xf0,0x77,0xb3,0x63,0x97,0x09,
+  0xf3,0xca,0xff,0x33,0x77,0xe5,0x61,0x51,0xde,0x5a,0xff,0x8f,0xab,0x40,0x15,0x14,
+  0x10,0x14,0x2b,0x2e,0xe0,0x2e,0x9b,0xc8,0x6a,0x15,0xdc,0xb5,0xa8,0xb5,0x2e,0x55,
+  0x5b,0x6d,0xaf,0x5a,0xef,0x75,0x6f,0x2d,0x55,0xac,0x45,0x18,0x66,0x98,0x61,0xdf,
+  0x11,0x41,0x45,0x51,0x44,0x10,0x15,0x17,0x44,0x40,0x10,0x64,0x11,0x64,0x17,0x54,
+  0x14,0x41,0x16,0xd9,0xb7,0x19,0x86,0x45,0x5c,0xaa,0xf7,0x7b,0xbe,0x93,0xe4,0x9d,
+  0xf0,0x3a,0xc3,0x8c,0xbd,0xf7,0x9f,0x76,0x9e,0x3c,0x79,0x92,0x4c,0x72,0x72,0x92,
+  0x9c,0xe4,0x97,0x93,0x37,0xcb,0x5c,0xc7,0x47,0x56,0x0e,0x45,0xd6,0xf6,0xe9,0x91,
+  0x29,0x35,0x7f,0x5b,0xfc,0xed,0xee,0xed,0x3d,0xf0,0xf3,0xc1,0x15,0x76,0xab,0x7f,
+  0xd8,0xf6,0xa3,0xfd,0xaf,0x0e,0x3e,0x81,0xa7,0x00,0x7f,0x93,0xee,0xa4,0xe5,0x17,
+  0x96,0x94,0x3e,0x2a,0xaf,0xaa,0x7e,0x59,0x55,0x5d,0xf7,0xbc,0xaa,0xfa,0x71,0x79,
+  0x45,0x61,0x51,0x69,0x5a,0xfa,0xfd,0xf8,0x84,0xe4,0xc8,0xa8,0xd8,0xc0,0x90,0x30,
+  0xbe,0x9b,0x27,0x28,0x2f,0xbb,0x77,0xef,0xdb,0xf4,0xed,0x96,0x55,0x5f,0xad,0x5b,
+  0xb2,0x74,0x99,0xf5,0xdc,0x2f,0x08,0x04,0xcf,0x9a,0x35,0x0b,0xdd,0x8b,0x35,0x49,
+  0x5f,0x77,0x22,0x68,0xc1,0x00,0xc1,0xe8,0x5c,0xb0,0xb6,0xf6,0x98,0x51,0x9a,0x5a,
+  0x1a,0xea,0xe8,0xa5,0x42,0xf6,0xd1,0x24,0x02,0xc4,0xe4,0x5b,0x30,0xd8,0x07,0x7f,
+  0xf9,0xf5,0x7a,0x7c,0x82,0xb7,0x5f,0xf0,0xe5,0xb8,0xf8,0x92,0xb2,0x72,0xf4,0xd1,
+  0x53,0xfe,0x37,0xac,0xee,0xde,0x9e,0x88,0xc8,0x08,0x9e,0x2b,0x8f,0xeb,0xca,0xe1,
+  0xf2,0xb8,0x2e,0x3c,0x0e,0x8f,0xef,0x42,0x1c,0x60,0x73,0x79,0x3c,0x17,0x9e,0x0b,
+  0x71,0x40,0xf8,0xc9,0xf0,0x53,0x79,0x85,0x45,0x02,0x77,0xef,0xb3,0xe7,0xa3,0xb2,
+  0x73,0xf2,0x1b,0x9b,0x5b,0x14,0xbc,0xde,0x0b,0xc3,0x85,0x5f,0x40,0xe0,0x40,0xe7,
+  0xc2,0xbb,0xc5,0x40,0xc1,0xbc,0x9d,0x94,0xcc,0xf7,0xf0,0x76,0xe2,0xf0,0x83,0x42,
+  0xc2,0x92,0x53,0xd2,0xcb,0x9f,0x55,0x02,0x32,0x0e,0xca,0x61,0xff,0x9b,0xd7,0x07,
+  0x0f,0xda,0x93,0xe4,0x04,0xd4,0x06,0x85,0x36,0xa9,0x40,0xba,0x3f,0x1c,0xb2,0xfb,
+  0x7a,0xed,0x3a,0xa8,0x7c,0xc8,0xa2,0xa3,0x53,0xd4,0x2f,0xff,0xfb,0xc5,0x9b,0xb7,
+  0xef,0x7a,0xfb,0xfa,0x4e,0x85,0x87,0xd3,0xfd,0x39,0x94,0xc8,0x8c,0x99,0xb3,0xee,
+  0xe7,0x3d,0xf0,0xf6,0xf1,0x3f,0x77,0x3e,0x3a,0x2b,0x3b,0xbf,0xa9,0xa5,0x45,0xf1,
+  0x4d,0x08,0x7c,0x81,0x9b,0x8a,0xf2,0x67,0xf2,0xb8,0x25,0x95,0xc0,0xfe,0x57,0x9e,
+  0x2d,0x5b,0x3a,0xea,0x20,0x44,0x90,0x19,0x32,0x74,0xca,0xd4,0x69,0x71,0x37,0x6e,
+  0x46,0x5f,0x8a,0x85,0x71,0xd5,0xfe,0xf0,0x6f,0x4e,0xce,0xae,0xbe,0x01,0xc7,0x2f,
+  0x5e,0x8a,0xbd,0x8f,0x0e,0x05,0xd7,0x75,0x89,0x7b,0xa0,0x62,0xd9,0x53,0x2f,0x80,
+  0xa7,0x9c,0xdc,0x7c,0xbd,0x89,0x7a,0x74,0xcf,0xc0,0x27,0x67,0x0b,0x94,0x2b,0xf6,
+  0x7e,0x3f,0x8d,0x91,0x1a,0xfb,0xf6,0xef,0x77,0xe1,0x39,0x63,0x51,0x21,0x36,0x07,
+  0x1c,0x44,0x90,0x78,0x7c,0x1e,0x97,0xe7,0x02,0x92,0xc3,0x71,0xe1,0x06,0x04,0x05,
+  0xe4,0x15,0x16,0x7a,0x78,0xf9,0x9f,0x3e,0x13,0x89,0x1e,0x15,0x6a,0x68,0x62,0x5e,
+  0x04,0x90,0x53,0x81,0x45,0x45,0x45,0x6e,0xee,0x7c,0x4a,0x13,0x6c,0x10,0x3c,0xf0,
+  0xba,0x60,0x82,0x5c,0x9e,0x2b,0xb1,0x21,0x5c,0xe0,0xce,0xcf,0xcd,0x2f,0x38,0x11,
+  0x1a,0xe6,0x17,0x74,0x3c,0xf1,0x4e,0x7a,0x79,0x65,0x9d,0xb8,0x5b,0xd1,0x26,0xe1,
+  0xb2,0xc7,0x8f,0xc7,0xeb,0x8e,0x97,0xf7,0xa6,0x27,0xaa,0x8a,0xa1,0x4a,0xfb,0xf6,
+  0x1f,0x88,0xbf,0x95,0xe0,0xed,0xeb,0x07,0xf8,0x0b,0xea,0x24,0x7a,0x78,0x57,0xc1,
+  0xf7,0xdf,0x0f,0x00,0x4f,0x67,0x48,0xc7,0xc1,0x3d,0xc5,0x19,0x3b,0xb8,0x98,0x73,
+  0xc2,0x2d,0x57,0xd2,0x9b,0x24,0xcc,0x73,0x71,0x04,0x57,0x8e,0xfd,0xa1,0x5f,0xa0,
+  0x0b,0xb3,0x1b,0x54,0x4a,0x00,0xf8,0x02,0x41,0x74,0xcc,0x65,0x5f,0xbf,0xc0,0xeb,
+  0x37,0x13,0x4b,0x1f,0x97,0x8b,0xba,0x7a,0xe4,0x2d,0x13,0xe1,0x5e,0xdc,0x1d,0x7e,
+  0xe6,0x2c,0x54,0x3b,0x6a,0x02,0x5c,0x5d,0x1c,0x2e,0x3b,0x5f,0xc8,0x94,0xe3,0x1f,
+  0x10,0x98,0x74,0xe7,0x4e,0xe6,0xfd,0x2c,0x81,0x87,0xa7,0x13,0x87,0x7b,0x22,0x34,
+  0x3c,0x31,0x39,0xed,0x59,0x45,0x15,0xde,0x3a,0x2e,0x17,0xd9,0x2b,0x2a,0x2b,0x0d,
+  0x66,0x19,0x52,0xae,0x64,0x05,0xf8,0xcf,0x98,0x3f,0xd9,0x79,0x95,0x94,0x55,0xf5,
+  0xd7,0x05,0x1b,0x3a,0x75,0x18,0x73,0x18,0xfc,0x22,0x20,0x02,0x6e,0x80,0x95,0xd9,
+  0xce,0x08,0xbc,0xc0,0x06,0x4d,0x8d,0xfc,0x65,0x8c,0xb5,0x45,0x82,0x20,0x44,0xdd,
+  0x03,0x88,0x31,0x92,0x24,0x04,0x83,0xfe,0x75,0x62,0xfe,0x45,0x38,0x8e,0xe3,0x90,
+  0x7f,0xa5,0xbc,0x28,0x32,0x8e,0x4f,0xdc,0x78,0x93,0x52,0x27,0x36,0x12,0xe2,0x4e,
+  0x42,0x53,0x80,0x2d,0xbc,0x55,0x18,0xa0,0x0a,0x01,0x1f,0x80,0x9d,0x33,0x86,0x36,
+  0x92,0x11,0xb3,0xba,0xcb,0x68,0x9a,0x46,0x1c,0x19,0x26,0x49,0x71,0x9c,0x31,0x29,
+  0x97,0x4e,0x26,0x89,0x24,0x47,0x23,0x27,0x16,0x05,0xac,0x99,0x12,0x07,0x89,0x86,
+  0x72,0xc4,0xb6,0x09,0x0e,0x37,0x71,0x26,0xf5,0x83,0x15,0x58,0x56,0x11,0x88,0xda,
+  0x6b,0xc4,0xe9,0x32,0xe2,0x88,0x66,0x23,0xde,0xc4,0x10,0x01,0x40,0x16,0xea,0x70,
+  0x36,0x42,0xdb,0x4e,0xc8,0xd7,0x9c,0xdb,0x39,0x9b,0x8b,0xa2,0x99,0x71,0x3b,0xcd,
+  0x79,0x42,0x73,0x57,0x21,0xb2,0x19,0x47,0x27,0xd8,0x16,0xdc,0xe6,0x2f,0xf8,0x6d,
+  0xd6,0x2e,0x75,0xf3,0x38,0x55,0xb6,0x4e,0xe5,0xf3,0x8e,0x16,0xd8,0x1c,0xcd,0x4e,
+  0x2a,0x6c,0xf8,0xcb,0x71,0x56,0x9e,0x79,0xfd,0xf6,0xed,0x31,0x0e,0x6f,0xe9,0xb2,
+  0x15,0xdf,0xff,0xb0,0xdd,0xde,0xfe,0xb0,0xa7,0xef,0x71,0xd0,0x95,0x40,0xcf,0x85,
+  0x59,0x31,0x60,0x2e,0xe0,0x6f,0x4d,0x5d,0x63,0x4d,0x5d,0x43,0x45,0x65,0xcd,0xa3,
+  0x27,0x4f,0x1f,0xe4,0x17,0xa4,0xdc,0x4d,0xbf,0x12,0x77,0x03,0x86,0x23,0x2f,0xff,
+  0x10,0x67,0x17,0xee,0xcf,0xbf,0x1c,0xda,0xf1,0xe3,0xae,0x0d,0xdf,0x6c,0x59,0xb5,
+  0x6a,0xcd,0x82,0x45,0x8b,0xc9,0x89,0x60,0x43,0x43,0x23,0x72,0x22,0x49,0x4f,0x1f,
+  0x41,0x30,0xba,0x9a,0xe3,0xf3,0x71,0xa0,0x08,0x03,0x06,0xa3,0x4d,0x59,0xea,0x5a,
+  0xa0,0x02,0x83,0x3a,0x0c,0xf8,0x4b,0x56,0xa4,0xc9,0x72,0x34,0x51,0x84,0xf7,0xec,
+  0xdd,0x77,0x2b,0x31,0xd9,0xcf,0x3f,0xe8,0xf2,0x95,0x9b,0xc5,0x78,0xd3,0xd1,0x9b,
+  0x37,0x72,0xc7,0x90,0xb6,0x8e,0xb6,0x95,0xab,0x57,0x43,0x42,0x62,0x08,0x11,0xb0,
+  0xd1,0x5e,0x2f,0xbc,0xbe,0x4d,0x0c,0xf9,0xd7,0xdc,0xc2,0x3c,0xed,0xde,0x3d,0xfc,
+  0xb8,0xc3,0x85,0xcc,0xec,0xfc,0xfa,0xc6,0x96,0x57,0xaf,0xe4,0x2e,0xc6,0xc2,0xe8,
+  0x74,0x02,0x5f,0xb2,0x47,0x9f,0x50,0x04,0x03,0x3c,0x87,0x9e,0x0c,0x3d,0x13,0x71,
+  0xee,0xe8,0xef,0x4e,0x5e,0x3e,0xfe,0xd1,0xb1,0xd7,0xf2,0x0b,0x4b,0x9b,0x9a,0xe5,
+  0x6e,0x4b,0xce,0xbe,0x9f,0xab,0xab,0x3b,0x9e,0x4d,0x64,0x08,0x5e,0x55,0xa6,0x0e,
+  0xd9,0x40,0x3a,0x9a,0x8d,0x50,0x1d,0x11,0x76,0xea,0x54,0x3d,0x3e,0x8b,0xd1,0xf7,
+  0xaa,0x5f,0xde,0x3a,0xf9,0x7b,0x74,0xf2,0xa8,0x4f,0x28,0x12,0xd9,0x1f,0xb2,0x57,
+  0x96,0xec,0x50,0xa2,0x44,0xf4,0xf5,0x26,0xe7,0xe4,0xe5,0xf9,0xfa,0x05,0x9c,0x39,
+  0x77,0x11,0x94,0x8b,0xba,0x97,0x8d,0x8a,0x6f,0xc2,0xf7,0x0d,0x08,0x80,0xb9,0x10,
+  0xe5,0x84,0x6c,0x8a,0xa3,0x7b,0xe4,0x28,0x74,0x4a,0x95,0x48,0xca,0x96,0x2a,0x8b,
+  0x54,0xb9,0x06,0xf0,0x17,0x1b,0x1b,0x5b,0xdb,0xe4,0xd4,0x94,0x90,0xd0,0x93,0x47,
+  0x7e,0x3b,0xe6,0x08,0xd3,0x1a,0x0f,0xdf,0x90,0xb0,0xb3,0x09,0x89,0x77,0x8b,0x4b,
+  0x1f,0x37,0xb5,0xb6,0xc8,0x7e,0x08,0x86,0xc1,0x16,0x14,0xb0,0x49,0x13,0xf5,0xa4,
+  0x68,0xb2,0x99,0xa4,0xb6,0x54,0xf3,0xb1,0xab,0x5d,0x45,0x69,0x40,0x36,0x40,0x5a,
+  0xc0,0x86,0x82,0xb3,0x05,0x89,0x48,0x11,0xcc,0x24,0xef,0x65,0xa6,0xfb,0xf8,0x05,
+  0x9c,0x0a,0x8f,0x80,0x39,0x5b,0x5d,0x7d,0xa3,0xbc,0xe5,0x0e,0xdc,0x16,0xef,0xcf,
+  0x9f,0x8f,0xd4,0xd4,0xd0,0xa4,0x94,0x29,0x7d,0x76,0x08,0x31,0x1a,0xea,0x1a,0x67,
+  0x23,0xce,0x85,0x9d,0x3e,0x13,0x10,0x74,0x22,0x31,0x19,0x26,0x72,0x55,0x78,0x73,
+  0x97,0x5c,0x90,0xaa,0x7c,0xf1,0x62,0xe2,0x84,0x49,0x52,0xd3,0x18,0xb6,0x14,0xc1,
+  0x5f,0xdb,0x77,0xec,0x4c,0x48,0x4a,0xf1,0xf6,0x0d,0xb8,0x74,0xf9,0xfa,0xc3,0xb2,
+  0xf2,0xb6,0xf6,0x0e,0x79,0xdb,0x93,0x88,0xe4,0xd8,0xd9,0xad,0xa6,0xec,0x49,0x31,
+  0xc9,0x66,0x9e,0xba,0xe9,0x82,0x15,0x04,0x92,0x86,0x96,0x6a,0x05,0x6a,0x3b,0xbb,
+  0x70,0x62,0xaf,0xc6,0x01,0xfe,0x5e,0xbb,0x71,0x0b,0x66,0xd1,0xa2,0x2e,0xb1,0x02,
+  0xc1,0x6b,0xef,0xec,0x58,0xb2,0x64,0x89,0x54,0xbe,0xec,0xba,0x02,0x03,0x03,0x85,
+  0x9e,0x9e,0xfe,0x2f,0xf6,0xbf,0xe6,0x3c,0xc8,0x0b,0x39,0x11,0x76,0xee,0xfc,0xc5,
+  0x8c,0xac,0x07,0xa0,0x32,0xe3,0x43,0x61,0x72,0xe5,0x59,0x24,0xee,0x5e,0x61,0x67,
+  0x37,0xa8,0x18,0x50,0xf1,0x96,0x5a,0xa0,0x56,0x2c,0xd8,0xec,0xae,0xca,0xc6,0x5f,
+  0x08,0x54,0x19,0x3e,0x6a,0xda,0xf6,0x9b,0x00,0x73,0xc6,0x68,0x5b,0x2f,0x82,0x24,
+  0x40,0x1c,0xaa,0xcd,0x99,0x72,0x3a,0x0c,0x8e,0x36,0x1b,0x1d,0x46,0x0f,0xd4,0x4e,
+  0xdd,0x93,0x3b,0x75,0x6f,0x9e,0xc1,0xc1,0x87,0x06,0x0e,0x35,0x86,0x47,0x9b,0x4c,
+  0xf1,0x77,0x4c,0x13,0xb4,0xac,0x8a,0x50,0xc6,0xc0,0x89,0x49,0x42,0x00,0x14,0xdc,
+  0xb3,0xb1,0xc3,0x14,0xa9,0x87,0xc8,0x2d,0xeb,0x35,0x72,0x66,0x22,0x1b,0x38,0x31,
+  0x91,0x4d,0x58,0x28,0x6c,0x8a,0x41,0xd6,0xd8,0x05,0xb1,0x64,0x22,0x81,0xd4,0xd9,
+  0x14,0x07,0x25,0xd1,0x0c,0x25,0x90,0x4a,0xbd,0x86,0xc4,0x4b,0xd4,0x52,0x8c,0xb0,
+  0x14,0xd0,0x3f,0x82,0x6c,0x0e,0xc5,0x68,0x26,0x84,0x50,0x66,0x78,0xc0,0x0a,0x38,
+  0x49,0x0b,0x30,0x2a,0xc9,0x9a,0x01,0x77,0x02,0xcd,0xe4,0x5f,0xa8,0x3a,0x13,0x52,
+  0x28,0x2e,0x8a,0x09,0x6e,0x33,0x2e,0x0a,0x24,0x5e,0x33,0x1e,0x8e,0xc3,0x45,0xff,
+  0x42,0xb8,0x39,0x1b,0x7f,0x5d,0x45,0xc8,0xe1,0x2a,0x9c,0x27,0x68,0x03,0x33,0x9f,
+  0xdf,0x38,0xdf,0xb5,0xc1,0xd6,0xb5,0x76,0x31,0xf7,0xc9,0xc2,0x63,0x05,0x4b,0x8e,
+  0x65,0x17,0x56,0xb4,0xfe,0xe5,0x38,0x2b,0x1f,0x68,0xde,0x07,0x06,0x06,0x2d,0x59,
+  0xba,0xfc,0xbb,0xef,0x7e,0xf8,0xe9,0xa0,0xbd,0x87,0x4f,0xc0,0xd9,0xf3,0x17,0x12,
+  0x12,0xef,0x64,0xe7,0x16,0x97,0x3d,0xae,0x78,0x51,0xd3,0x50,0xfb,0xb2,0x09,0xcc,
+  0x8b,0x9a,0xc6,0xf2,0x0a,0xb4,0x0a,0x9d,0x9d,0x53,0x90,0x94,0x9c,0x16,0x7d,0x29,
+  0xee,0x64,0x78,0x84,0x9b,0x87,0xdf,0x11,0x47,0xce,0xbe,0x03,0x07,0xb7,0x6d,0xdf,
+  0xb9,0xee,0x9b,0xcd,0xcb,0xbf,0x5c,0x65,0xbb,0x70,0x31,0x68,0xc1,0xa6,0x73,0x24,
+  0x0b,0xd1,0x53,0xf4,0x01,0x82,0x27,0x4c,0x44,0x17,0x44,0x7f,0x3e,0x0e,0x7f,0x0e,
+  0xd6,0x06,0x1c,0x66,0x14,0x61,0xf4,0x5e,0xd2,0x08,0xf4,0x64,0x21,0xfb,0xb2,0xac,
+  0x6d,0x3b,0x7e,0x4c,0xba,0x73,0xd7,0xdb,0x17,0xf0,0xf7,0x46,0x51,0x49,0x59,0x2b,
+  0xda,0xf1,0x22,0x17,0x7f,0x3b,0x45,0xc2,0x6f,0x36,0x6e,0x62,0xfa,0xc2,0x50,0x25,
+  0xa2,0x10,0xd1,0x0d,0x5d,0xa4,0x8b,0xd1,0x7b,0xb7,0x0c,0x8d,0x8c,0xef,0xa4,0xdf,
+  0x73,0xf3,0xf0,0x3a,0x1d,0x7e,0x21,0x23,0x2b,0x07,0x2f,0x1d,0x4b,0x0f,0xef,0x03,
+  0xe6,0x3f,0x1f,0x22,0x23,0x2f,0x4a,0x3d,0xa1,0x08,0xa4,0xfe,0xb5,0x7b,0x4f,0x4a,
+  0x5a,0xda,0x51,0x47,0x27,0x1e,0x5f,0x10,0x12,0x1e,0x75,0xe7,0x6e,0x46,0x65,0x55,
+  0xad,0xb8,0x7b,0xf0,0x6b,0xa9,0xfa,0x5e,0xbf,0x3a,0x7c,0xe4,0x08,0x94,0x6b,0x80,
+  0x1f,0xfc,0x1c,0x30,0x7b,0xbf,0x19,0x55,0xe2,0xa4,0x32,0x82,0x6a,0xac,0xa9,0xad,
+  0x6d,0x46,0xa7,0x95,0x7b,0x14,0xdc,0x95,0x84,0x76,0xd1,0x88,0xc5,0xcd,0x2d,0xcd,
+  0x0b,0x17,0x2e,0x66,0x5f,0xf2,0x49,0x1c,0xa0,0x31,0xe5,0x15,0x14,0xfa,0x07,0x04,
+  0x9d,0x39,0x1b,0x95,0x99,0xfd,0x00,0x8a,0xdc,0xff,0x5a,0x2e,0x7c,0x80,0x39,0x75,
+  0x3a,0x1c,0xe6,0x18,0x52,0x44,0x68,0x4d,0xca,0x32,0xc9,0x40,0x80,0xc4,0x4b,0xb4,
+  0x30,0xa9,0x68,0xf2,0xd2,0x92,0xc8,0x30,0x70,0xd9,0x2e,0x5c,0x58,0x58,0x52,0x12,
+  0x7e,0xf6,0xbc,0xc0,0xdd,0xdb,0xcb,0xdb,0x1f,0x54,0x9b,0xcb,0x57,0xe3,0xb3,0x72,
+  0x0a,0x5e,0xd4,0x36,0x88,0xbb,0x7b,0xdf,0xc9,0x7c,0x7d,0x78,0xfd,0xf6,0x75,0x68,
+  0x58,0x18,0xc0,0x1c,0xe5,0x53,0xea,0x25,0x41,0xfa,0x4c,0x1e,0xcd,0x97,0x2d,0x1b,
+  0xe4,0x5f,0xa9,0x22,0x30,0xd1,0x28,0x57,0x92,0xb2,0xeb,0x4d,0xd2,0x4b,0x4d,0x4b,
+  0xf3,0xf5,0x0f,0x0a,0x0b,0x8f,0xc8,0xcc,0xce,0xad,0x7d,0xd9,0x80,0x1e,0x15,0x92,
+  0x33,0xe0,0x43,0xc5,0x5e,0x8c,0x89,0x19,0x39,0x42,0x5d,0x5e,0x5d,0x11,0xae,0x48,
+  0xc8,0xf0,0x61,0xaa,0x21,0xa1,0x30,0x97,0x8b,0xf4,0x0f,0x08,0x49,0x48,0x4c,0x29,
+  0x7f,0x56,0xa9,0x58,0xff,0x6d,0x68,0x6c,0x98,0x36,0x6d,0xfa,0xa0,0xcf,0x7a,0x52,
+  0xca,0x1b,0x37,0x6f,0xba,0x9b,0x9e,0xe1,0xe9,0x1b,0x04,0xf8,0x5b,0x52,0xf2,0xb8,
+  0xbd,0x43,0xd1,0x71,0x6f,0x30,0xeb,0x37,0x7c,0xc3,0xae,0x2b,0x59,0x26,0xd9,0xff,
+  0xca,0xcb,0x97,0x56,0x1d,0x5b,0x18,0x0e,0x3b,0x38,0xc4,0xdd,0xb8,0xe5,0xeb,0x17,
+  0x74,0xed,0x66,0xc2,0xc3,0x47,0x4f,0x85,0x22,0x31,0xba,0x36,0x43,0x2e,0x4a,0x8a,
+  0x57,0xd8,0x7d,0x49,0x5f,0x36,0xa4,0xad,0x20,0xd5,0x82,0xe0,0x85,0xae,0x74,0x31,
+  0x3a,0x26,0x33,0x3b,0xe7,0x56,0x62,0x6a,0xd9,0xe3,0xf2,0xd6,0x76,0x21,0x7a,0x1f,
+  0x5c,0x3e,0xfe,0x82,0xf0,0xec,0xdd,0x7f,0x80,0xbe,0xc1,0xcd,0xb4,0x85,0x9c,0x02,
+  0xca,0x16,0x5f,0x9e,0xb4,0x0f,0xda,0x9d,0xd5,0xc7,0xe8,0x19,0xfe,0x52,0x86,0x17,
+  0x42,0x91,0x31,0xc3,0x6b,0xa4,0x04,0xad,0x8c,0x0f,0x57,0xe9,0x6d,0x8a,0x1a,0x6d,
+  0xbe,0x73,0xe4,0x04,0xcb,0x61,0x9a,0xfa,0x4a,0xc3,0xb5,0x95,0x55,0xc7,0xa8,0x6a,
+  0xcf,0xd2,0x9c,0xba,0x4c,0xc7,0xc6,0x61,0xfa,0xce,0x0c,0x23,0xc7,0x16,0xb4,0xa0,
+  0x8a,0xb0,0x12,0xeb,0x8f,0x58,0xc5,0x33,0xa1,0xc9,0xff,0x84,0x01,0x54,0x52,0x1c,
+  0x1f,0x58,0x02,0x14,0x9b,0x8d,0x3f,0x95,0x1a,0x62,0xcd,0x17,0x19,0x0e,0x59,0xc8,
+  0x65,0xb6,0x33,0xc9,0x3a,0x4c,0xb1,0x9a,0x3c,0x90,0x16,0x27,0x99,0x8d,0x59,0x45,
+  0xff,0x72,0x18,0x22,0x24,0x89,0xa9,0x84,0x26,0x56,0x75,0xf1,0xbf,0x1c,0x26,0xfe,
+  0x6c,0x56,0x64,0x62,0x93,0x8f,0xb6,0x28,0x17,0x1e,0x2b,0x2d,0x36,0xe6,0x5c,0xc6,
+  0x20,0x37,0x0f,0xbb,0x09,0xd4,0xb2,0x0d,0x5f,0xcc,0xb2,0xbb,0xac,0x05,0x22,0x6b,
+  0x81,0x10,0xcc,0x5c,0x41,0xe7,0x42,0xf7,0xc6,0x45,0x6e,0xf5,0xcb,0xdd,0x2b,0x97,
+  0xf1,0x9f,0x2d,0x72,0x2e,0x5a,0xc5,0xcd,0x7d,0xde,0x20,0xfa,0xcb,0x71,0x56,0x81,
+  0x49,0x4e,0x4d,0x5d,0xba,0x74,0xd9,0x86,0x8d,0x9b,0x77,0xed,0xfd,0x19,0xc6,0xc0,
+  0x53,0xe1,0xe7,0xc9,0x21,0x9d,0xb2,0xc7,0x4f,0xab,0xaa,0xeb,0xea,0xea,0x9b,0xea,
+  0x9b,0xda,0x60,0xe8,0xae,0xae,0x6d,0x7c,0xf2,0xac,0xb2,0xf8,0x61,0x59,0x7a,0x46,
+  0xee,0xcd,0x5b,0xb7,0xa3,0x62,0x62,0x83,0x8f,0x9f,0x74,0xf7,0xf4,0xfb,0xed,0xf7,
+  0x63,0xfb,0xf6,0xff,0xb4,0xf5,0x87,0xed,0xeb,0xd6,0x6f,0x5a,0xfe,0xe5,0x6a,0x9b,
+  0x05,0x8b,0xc9,0x42,0xb4,0x91,0x91,0xd1,0x2c,0x83,0x59,0xd3,0xa7,0xcf,0xd0,0x9b,
+  0xac,0x37,0x69,0x12,0x7a,0x29,0xf8,0xf3,0x71,0xba,0x3a,0x63,0xc7,0x8e,0x1e,0x3d,
+  0x5a,0x0b,0x2b,0xc2,0x5a,0xa3,0x40,0x17,0x1e,0x45,0x56,0xa4,0x61,0xd8,0x47,0x40,
+  0xac,0x3a,0x72,0xcb,0x96,0xad,0x69,0xf7,0x32,0x7d,0x7c,0x83,0x62,0xaf,0xdc,0x28,
+  0x2c,0x2e,0x6b,0xef,0xe8,0x54,0xa0,0xff,0x76,0xf7,0x76,0xff,0x73,0xdb,0x76,0xf2,
+  0xed,0x18,0x9d,0x69,0x1a,0x32,0x94,0x76,0x25,0xe6,0xc6,0x0f,0xd6,0x16,0xaf,0x99,
+  0x33,0x66,0xa6,0xdc,0x4d,0xf3,0xf4,0xf6,0x0f,0x3b,0x7d,0x2e,0x3d,0x33,0x07,0x74,
+  0x19,0xd0,0x1c,0x15,0x4c,0x9e,0x6f,0xc6,0x27,0x90,0x65,0x52,0xf2,0x90,0x04,0x9a,
+  0xe2,0x2a,0xab,0x18,0x99,0x18,0x65,0xe7,0xe4,0xb8,0x0a,0xdc,0x1d,0x9d,0x5d,0x02,
+  0x82,0x42,0x62,0xaf,0x5c,0xcb,0x2f,0x2a,0xad,0x6f,0x6a,0x97,0x77,0x33,0x46,0x75,
+  0x4d,0xad,0xed,0x82,0x45,0x04,0x68,0x98,0xd7,0x28,0x24,0x2c,0x91,0x93,0x9b,0x0c,
+  0xb7,0x24,0x50,0x89,0xf9,0x6b,0xb4,0xf6,0xe8,0x88,0x73,0x51,0x3d,0x3d,0x7d,0xe8,
+  0x62,0x46,0xf9,0xd3,0x8f,0x77,0xef,0xff,0xe8,0xed,0xeb,0x83,0x49,0x48,0x56,0xce,
+  0x7d,0x9d,0x31,0x3a,0x74,0x4b,0x1b,0x19,0x22,0x80,0xac,0x96,0x96,0xf6,0xfd,0xbc,
+  0xfc,0xc0,0xe0,0xd0,0x93,0xe1,0x91,0x19,0x68,0xbf,0x4a,0x23,0x7e,0xcf,0x51,0xee,
+  0x20,0x7f,0x21,0xea,0xa2,0xa6,0xba,0x26,0x99,0xea,0x33,0x5f,0x04,0x86,0xa2,0x9a,
+  0x24,0x73,0x7e,0xba,0x6b,0x9d,0xba,0x65,0xbd,0x52,0x75,0xce,0x4e,0x4b,0x63,0xb2,
+  0x8b,0x8f,0x8e,0xa4,0xa9,0x7c,0xb6,0x79,0xcb,0xe6,0xfc,0x82,0xfc,0xab,0xd7,0x6f,
+  0x44,0x5e,0xbc,0x14,0x7d,0xe9,0xda,0xed,0xe4,0x94,0xfc,0x82,0x62,0xd0,0x6e,0x44,
+  0x5d,0x3d,0x6f,0xdf,0x0e,0xb2,0xdf,0xb8,0xbb,0xb7,0xc7,0xd5,0xd5,0x0d,0x6a,0x89,
+  0x66,0xca,0xa6,0x4c,0x38,0x67,0xaa,0x42,0x52,0xc9,0x74,0xed,0x91,0xde,0x86,0xca,
+  0x2e,0x02,0x89,0x2c,0x45,0x0d,0xd2,0xea,0x8e,0xd3,0xbd,0x9d,0x94,0x1c,0x04,0x82,
+  0x7e,0xfa,0x4c,0x5a,0x46,0x4e,0x4d,0x5d,0x7d,0x5f,0x5f,0xbf,0xdc,0x01,0xff,0x3f,
+  0x1f,0xe2,0xe3,0x6f,0x6b,0x8d,0xd2,0x1e,0x28,0xe3,0xc7,0x2d,0x4e,0x9b,0x18,0x28,
+  0x83,0xcc,0x7b,0xfa,0x78,0x45,0x46,0x45,0x03,0xfe,0xde,0xba,0x9d,0xfa,0xe4,0xe9,
+  0xf3,0xae,0xee,0x6e,0x05,0x4b,0xa9,0xad,0xed,0xed,0xc6,0xc6,0x26,0x6c,0xa4,0xa0,
+  0xa5,0x60,0x54,0xb9,0x7f,0x0c,0x5d,0xfd,0xd5,0x9a,0xcc,0xec,0xfb,0xa0,0x75,0x46,
+  0xc7,0xc6,0xe5,0x17,0x97,0xb5,0xb6,0x89,0x14,0xe3,0xef,0xb6,0x6d,0x3b,0x68,0x25,
+  0x0c,0xc1,0x3b,0xb8,0x68,0xc7,0x21,0x02,0xcf,0x4c,0x5a,0x94,0x94,0x89,0x61,0x84,
+  0x41,0xd2,0x17,0x48,0xbe,0x6c,0x49,0xa6,0x4d,0xbc,0x6b,0xcf,0x9e,0x9b,0xb7,0x12,
+  0xbd,0x7c,0x03,0xaf,0x5e,0xbb,0x51,0xfc,0xf0,0x49,0xa7,0xa8,0xeb,0xf5,0x1b,0xb9,
+  0xdf,0x7a,0x7a,0x5f,0xf5,0xad,0x5d,0xb7,0x9e,0x2d,0x2d,0xa4,0xa2,0xc8,0x44,0x68,
+  0x40,0x14,0x71,0x84,0xad,0x5b,0xb7,0x56,0x54,0x56,0x15,0x97,0x3e,0xa9,0x6f,0x6c,
+  0xee,0xee,0xe9,0x53,0xa0,0xe0,0x7f,0xc0,0xc7,0xb1,0xb9,0x5c,0x1e,0x61,0x52,0x4a,
+  0x3c,0x08,0x65,0x3a,0x6e,0x7c,0xd4,0x46,0x1f,0x0b,0x30,0x5b,0xbc,0xe9,0x4c,0x83,
+  0xca,0x33,0xbd,0xd6,0x6f,0xd4,0xd4,0x25,0xe6,0xce,0x4d,0x26,0x18,0x32,0x4c,0x88,
+  0xbe,0x06,0xb0,0xe2,0x58,0xa7,0xff,0x6d,0x8c,0x86,0xde,0x17,0x2a,0xc3,0x34,0x87,
+  0xfc,0x03,0x92,0x7f,0xa6,0xfc,0x99,0xa6,0x8a,0xea,0x68,0x15,0x55,0x6d,0x65,0x95,
+  0x91,0x10,0x32,0x74,0x88,0xb2,0xca,0x88,0x09,0x5a,0x73,0x7e,0x98,0xb6,0x2b,0xd3,
+  0xd4,0xa5,0xc3,0x9c,0x87,0x16,0xa8,0xe7,0x70,0x19,0xed,0x0f,0x88,0x98,0x62,0x37,
+  0xc0,0xab,0x29,0x97,0x71,0x0f,0xea,0x85,0x98,0x00,0xb2,0x00,0x46,0x8a,0x23,0x03,
+  0xd8,0x21,0x28,0xe4,0x32,0x90,0x3d,0x47,0xa2,0x5a,0x9a,0xb9,0x30,0xf9,0x9a,0x61,
+  0xdb,0x94,0xcb,0xe4,0x3e,0x1b,0xb3,0xc1,0x94,0x08,0xaf,0xfd,0x12,0x3d,0xd4,0x9c,
+  0xda,0xac,0xf2,0x22,0x5c,0xe6,0x76,0x92,0x8c,0x80,0x13,0x16,0x29,0xa4,0xd8,0x9a,
+  0xb9,0xe2,0xdc,0x25,0xcc,0x80,0x17,0x8c,0x31,0xc9,0x9d,0x87,0xbd,0xd8,0xc1,0x82,
+  0x57,0x11,0x1b,0x70,0xcd,0x3e,0x0e,0xb1,0x70,0x15,0x59,0x80,0xcd,0x17,0x59,0x09,
+  0x44,0x73,0xdd,0x84,0xf3,0xdd,0x85,0xf3,0x3d,0xb0,0xf1,0x14,0x2e,0xf6,0x6e,0x5f,
+  0xe1,0x53,0xbf,0xd4,0xa3,0x76,0x85,0xdb,0xd3,0x15,0xae,0x65,0xfb,0x4e,0x14,0x37,
+  0x77,0x29,0xea,0x05,0x7f,0xb9,0xa9,0xa9,0xab,0x5b,0xb7,0x61,0xe3,0xda,0xf5,0x9b,
+  0x76,0xed,0xf9,0xf9,0x98,0xb3,0x2b,0x8c,0x35,0x71,0xd7,0x6f,0x65,0x64,0xe5,0x3e,
+  0x7c,0xf4,0xe4,0x79,0x55,0x1d,0x20,0x6f,0x43,0x73,0x27,0x48,0x7b,0x7d,0x63,0xeb,
+  0xf3,0xea,0xea,0xb2,0x27,0xcf,0x1e,0xe4,0x97,0xa4,0xde,0xcd,0x8c,0xbb,0x7e,0x1b,
+  0xb4,0xaa,0x80,0xe0,0x50,0x9e,0xab,0xbb,0xc3,0x91,0xdf,0xf7,0xec,0x3d,0xf0,0xdd,
+  0xd6,0x7f,0xae,0x5d,0xbf,0x71,0xf9,0x97,0x5f,0xd9,0x2c,0x58,0x04,0x10,0x3c,0x67,
+  0x8e,0x19,0x40,0xb0,0x81,0x81,0xc1,0xf4,0xe9,0xd3,0xf5,0x27,0xeb,0x4f,0xd0,0x9b,
+  0x34,0x7e,0xfc,0x04,0xdd,0xf1,0x13,0x91,0x22,0x3c,0x06,0x74,0x61,0xf2,0x43,0xba,
+  0xb0,0xa6,0x86,0xd6,0xc8,0x11,0x23,0x41,0x1d,0x06,0xfb,0x9b,0x8d,0x1b,0xd3,0x33,
+  0xb2,0x7d,0xfc,0x60,0x0e,0x1f,0x07,0xf8,0xdb,0xd6,0xa1,0x68,0xfd,0x19,0x7a,0xee,
+  0x9e,0x3d,0xfb,0xd9,0x23,0x3f,0x5d,0xbc,0xa2,0x5e,0x02,0x22,0xc3,0x54,0x86,0x4d,
+  0xd6,0x9f,0x02,0xf8,0xeb,0xed,0xe3,0x7b,0x3a,0xfc,0x3c,0x64,0x01,0xf3,0x8a,0xbe,
+  0x3e,0x45,0x9b,0x81,0x53,0xd3,0xef,0x81,0x3e,0x4e,0x46,0x72,0xd2,0x4f,0xc1,0x31,
+  0x66,0xf4,0x98,0xe8,0xd8,0xd8,0xf0,0xb3,0x11,0x30,0xeb,0x70,0x75,0xf3,0x08,0x3f,
+  0x1b,0x95,0x9c,0x9a,0x01,0xca,0x4b,0xa7,0x50,0x2c,0xef,0xd3,0x2a,0x0c,0xe0,0x33,
+  0x66,0xcc,0x04,0x7e,0xc8,0x92,0x1a,0xe9,0xfb,0x74,0x79,0x8d,0x70,0x0b,0x21,0x64,
+  0x71,0x8f,0x98,0xbd,0xfb,0xf7,0xb7,0xb4,0xb6,0xf5,0xf7,0xbf,0x51,0x74,0xda,0xf4,
+  0xff,0x3e,0x80,0x4e,0xd1,0xd1,0x29,0x6c,0xef,0xec,0x74,0xf7,0xf2,0x84,0x02,0x32,
+  0xc9,0x95,0x54,0x08,0xa8,0x01,0x4d,0x7c,0x13,0x6f,0x76,0xf0,0xf1,0xd0,0xd3,0x67,
+  0x2f,0x40,0x91,0x5f,0x7c,0x0a,0x7f,0xaf,0xc4,0xc5,0x69,0x6b,0x8d,0x26,0x44,0x08,
+  0x05,0x30,0xc3,0x87,0x0d,0x27,0x03,0x2f,0xe2,0x56,0x99,0xb5,0x2a,0x88,0x33,0xa2,
+  0x23,0x1b,0x5d,0x33,0xa4,0x05,0x24,0xad,0x80,0x02,0x07,0x4b,0xcb,0xd4,0x00,0x1e,
+  0x72,0x41,0x99,0xdd,0x7f,0xe0,0xa7,0xaa,0xea,0x9a,0xdc,0xbc,0xfc,0x9c,0x9c,0xc2,
+  0x82,0xe2,0x92,0xa7,0x15,0x2f,0x9a,0x5a,0xda,0x61,0x06,0x02,0x73,0x8c,0x41,0xd7,
+  0x28,0x40,0x69,0xfa,0xf7,0xae,0xbd,0xaa,0xaa,0x6a,0x94,0x0d,0x3a,0x2a,0x32,0xc4,
+  0xd9,0x0e,0x59,0x9e,0x95,0x98,0xac,0x99,0xb4,0x43,0x86,0x4a,0x95,0x88,0x0c,0xb9,
+  0x08,0x7f,0x13,0x93,0x83,0x43,0x4e,0x9c,0x08,0x3b,0x93,0x9a,0x9e,0x05,0xf8,0xdb,
+  0xdb,0xa7,0x68,0x01,0xe1,0x6e,0x7a,0x3a,0x48,0x08,0xad,0x0d,0x54,0x0f,0xca,0x1f,
+  0xad,0xa3,0x12,0x2f,0x50,0x06,0x55,0x8e,0xc7,0x77,0x8d,0xbe,0x74,0x15,0xf0,0xf7,
+  0xe6,0xad,0x64,0x98,0xeb,0x0a,0x45,0xdd,0x6f,0xdf,0xbd,0x93,0xb7,0x20,0xd3,0x29,
+  0x12,0x5b,0x59,0x5a,0x4b,0x31,0x49,0xd5,0x61,0xe2,0x5d,0xb2,0x78,0x69,0x66,0x4e,
+  0x8e,0xb7,0x5f,0x10,0xe0,0x6f,0x5e,0x71,0x69,0x4b,0xab,0x50,0x31,0xfe,0x82,0x6e,
+  0x48,0xd2,0x92,0xb5,0x77,0xa9,0xe2,0x0f,0xb4,0x11,0x6b,0xb2,0x44,0x32,0xa5,0xb2,
+  0x41,0x04,0x98,0xa9,0x46,0xfc,0x2f,0x01,0xcd,0x6d,0x3b,0xb7,0xdd,0x4e,0x4a,0x61,
+  0xf0,0xb7,0xe4,0x09,0x3a,0x26,0xf0,0x5e,0x6e,0x2f,0x06,0x99,0xdc,0xba,0xf5,0x7b,
+  0x22,0x66,0x6c,0xca,0xb4,0x15,0x68,0x3b,0x82,0xbd,0x76,0xdd,0xda,0x86,0x86,0xe6,
+  0xc6,0xe6,0x36,0x71,0x77,0x8f,0x82,0xf3,0x83,0x4c,0x07,0x79,0xf7,0xd6,0xdb,0xd7,
+  0x57,0x45,0x72,0xf9,0x3c,0x25,0x28,0xc5,0xb3,0xac,0x3c,0x0f,0x2a,0x0c,0x84,0x37,
+  0x46,0x72,0x58,0x5d,0x03,0x6c,0x70,0xeb,0xda,0x1c,0xb0,0x12,0x30,0x2b,0xa2,0x00,
+  0x34,0x00,0x3a,0xc6,0x8e,0x0d,0x13,0x17,0x1e,0x1e,0xae,0xa6,0x83,0xd4,0x67,0x65,
+  0x75,0x75,0x3d,0xdb,0x49,0x4b,0x1c,0xa7,0x6c,0x0c,0x9f,0xb1,0xfd,0xea,0xe4,0xef,
+  0xaf,0xe8,0xaf,0x3f,0xa1,0x63,0xb5,0x6b,0xb8,0xce,0x4c,0xac,0x4a,0x2b,0xa9,0xe9,
+  0x98,0xe8,0x6f,0xb9,0x82,0x20,0x98,0x82,0x0e,0x06,0x23,0x80,0x2a,0x69,0xd5,0x6f,
+  0x50,0xc3,0x1b,0x4c,0x49,0x94,0x31,0x84,0x9a,0x19,0xe6,0x10,0xa7,0x12,0x99,0xf3,
+  0x30,0xae,0xf1,0xba,0xe4,0x92,0xfa,0x24,0x65,0x99,0x7f,0xe7,0x0c,0x20,0x29,0x20,
+  0x66,0x97,0xa2,0xb4,0x8a,0xb2,0x90,0x4d,0x3b,0xe0,0xb5,0xe0,0x83,0x11,0x5b,0xf2,
+  0x41,0xe7,0xed,0x02,0xf0,0xb5,0x76,0x17,0x2f,0xf0,0x16,0xcf,0xf7,0x16,0x2e,0xf4,
+  0x11,0x2e,0xf7,0x6d,0x5f,0xe5,0x57,0xf7,0x75,0x40,0x9d,0x9d,0xfb,0xb3,0xaf,0xdd,
+  0x8b,0x8e,0xdf,0xaa,0x79,0xfd,0x77,0x3d,0x7c,0x44,0x4c,0x5f,0x7f,0x9f,0xe3,0x31,
+  0x97,0xd5,0x5f,0x7d,0xbd,0x63,0xc7,0xbf,0x1c,0x8f,0x71,0x02,0x82,0x42,0x2f,0xc4,
+  0xde,0xb8,0x9b,0x9e,0x5d,0x54,0xf2,0xe8,0x79,0x55,0xcd,0xcb,0x86,0xa6,0xe6,0xd6,
+  0x8e,0xc6,0xe6,0x76,0x0c,0xc1,0xed,0x80,0xc8,0xa5,0x8f,0x9e,0xe4,0x3e,0x28,0x4c,
+  0x4a,0x49,0x03,0x08,0x8e,0x38,0x1f,0xed,0x13,0x14,0xea,0xcc,0xf3,0x3a,0xe4,0x80,
+  0x20,0x18,0x69,0xc1,0x1b,0x36,0xad,0xb0,0x5b,0x63,0xbb,0x70,0xf1,0x17,0xf3,0xd0,
+  0xa1,0x24,0x13,0x13,0x13,0x43,0x43,0x43,0x00,0x20,0x40,0xe1,0xc9,0x93,0x27,0x03,
+  0x0a,0x03,0x04,0xa3,0xe5,0xe8,0xcf,0x3f,0x1f,0x33,0x66,0x0c,0x81,0x60,0x2d,0xad,
+  0xd1,0xa3,0x46,0xa1,0x2b,0x2b,0x35,0xd5,0xb5,0x56,0xae,0x5c,0x95,0x91,0x75,0x1f,
+  0xe3,0xef,0xb5,0xbc,0x82,0x87,0x90,0xb5,0x82,0x13,0x1f,0xf8,0x94,0xd0,0x91,0x81,
+  0x93,0xc5,0xf8,0x72,0x0f,0xe2,0x20,0xf7,0x5e,0xa2,0x81,0x45,0x19,0x7d,0xae,0x02,
+  0x78,0x9a,0x38,0x61,0x52,0xc2,0xed,0x24,0xbf,0x80,0x60,0x50,0xf0,0x53,0xd3,0xd1,
+  0x03,0x6d,0x48,0xff,0x95,0x7f,0x96,0x33,0x37,0x2f,0x0f,0xe6,0x03,0x90,0x96,0x4d,
+  0x1f,0x94,0xf4,0xcd,0x9b,0xbf,0xcd,0xca,0xce,0x71,0xe6,0xba,0x3a,0x71,0xf8,0x3e,
+  0xfe,0x41,0x31,0xb1,0x71,0xf7,0x73,0x0b,0xf0,0xa7,0xa8,0x57,0xef,0xc8,0xf8,0xf9,
+  0x31,0x62,0x02,0x82,0xa4,0xa5,0x67,0x18,0x1a,0x1a,0xa3,0x9d,0x66,0x2a,0xc3,0x08,
+  0x41,0xc2,0x15,0xe9,0xc2,0x94,0x73,0x15,0xfc,0x59,0x10,0xe8,0xb7,0x77,0x08,0x19,
+  0xbd,0x4f,0x01,0xf8,0xbe,0x7d,0xdb,0x25,0x16,0x43,0xeb,0x54,0x3c,0x7f,0x61,0x6b,
+  0xbb,0x80,0x96,0x9a,0x6e,0x6c,0x03,0xca,0x1a,0x1a,0x1a,0xa9,0x77,0xd3,0x40,0x77,
+  0x3b,0x75,0x26,0x32,0x2d,0xfd,0x7e,0x55,0x75,0xad,0xe2,0xfd,0x57,0xc9,0x77,0x52,
+  0x60,0x8e,0x44,0xd2,0x02,0x35,0x60,0x98,0x54,0x1d,0x9b,0x67,0xf0,0x7e,0x54,0xc3,
+  0xd8,0x8b,0x9e,0x9b,0xc4,0xc3,0x38,0x78,0x69,0x13,0xb0,0x5b,0x81,0x31,0xf8,0x5f,
+  0x42,0x59,0xca,0x0b,0x05,0x3f,0xfa,0xbb,0x63,0x13,0xba,0x65,0xb0,0xad,0xa5,0xb5,
+  0x43,0xd4,0xd5,0xd5,0xdb,0xdb,0xa7,0xf8,0xb4,0x54,0x6b,0x5b,0xc7,0xee,0x3d,0xfb,
+  0x99,0xbd,0xf4,0x2c,0xae,0x10,0x41,0xc9,0xbe,0x3e,0x52,0x04,0x5a,0x2d,0x7f,0xde,
+  0x10,0x52,0x00,0xa6,0xd7,0xe3,0xe3,0x43,0xc3,0xc2,0x4f,0x9e,0x8a,0x48,0xbd,0x07,
+  0x13,0x98,0xba,0x9e,0x1e,0x45,0xa7,0x74,0x41,0x66,0x74,0x75,0xc7,0x13,0x96,0x68,
+  0xa5,0xc9,0x4a,0x26,0xd8,0x23,0xd4,0x46,0xfe,0x76,0xf4,0xd8,0x95,0xb8,0x9b,0x80,
+  0xbf,0xf1,0x09,0x89,0x30,0xd5,0xc5,0x1b,0xf9,0xe4,0x0e,0x14,0xbd,0xaf,0x5e,0x2f,
+  0x5a,0xbc,0x44,0x96,0x32,0xdb,0x58,0x59,0xcf,0xcd,0xcd,0x2b,0x0a,0x08,0x0c,0xbe,
+  0x18,0x13,0xf7,0xa0,0xa0,0xa4,0xa9,0xa5,0x45,0xf1,0xfc,0xed,0xa8,0xa3,0x93,0x9a,
+  0x9a,0x9a,0x82,0x46,0x61,0x7b,0x69,0xc5,0xb2,0x73,0x27,0x72,0xc2,0xae,0x31,0x62,
+  0x36,0x6d,0xfe,0x36,0x39,0x35,0xdd,0xd3,0x37,0x30,0xe6,0xf2,0x8d,0x82,0xa2,0x87,
+  0x1d,0x9d,0x62,0x98,0x09,0xc8,0x3d,0x45,0xf8,0xc7,0xbb,0xbd,0xfb,0xf6,0x93,0x09,
+  0xe4,0xa0,0xf9,0x12,0x2f,0x09,0xf7,0xf0,0xf4,0x86,0x59,0x37,0xba,0x53,0xfb,0x53,
+  0x83,0x2a,0xba,0xd7,0xfa,0xed,0x1b,0x0f,0x0f,0x4f,0xc2,0xb3,0xbc,0x4a,0xfb,0xdf,
+  0x8c,0x14,0x93,0x23,0x35,0xb4,0x0c,0xb6,0x46,0x5a,0x0b,0x28,0x3a,0x88,0xcd,0x7e,
+  0xaf,0xd2,0x9e,0xb3,0x6d,0xe8,0x10,0x95,0x21,0x43,0x54,0x34,0x67,0xae,0x34,0xd8,
+  0x79,0x6d,0x0e,0xa7,0x05,0x54,0x36,0x1c,0xa7,0xcb,0x9c,0x2f,0x02,0xec,0x40,0x31,
+  0x9d,0x6a,0xf5,0xbe,0xf2,0x57,0x1b,0x8b,0x4e,0xee,0xab,0xaa,0x8f,0x99,0xb2,0xd6,
+  0x87,0x22,0x11,0x86,0x18,0x69,0xdc,0x91,0x67,0x58,0x91,0xe5,0x1a,0x33,0x7e,0x8f,
+  0x95,0x40,0x41,0x84,0x2e,0x04,0x79,0x58,0xcd,0xc4,0xca,0xa6,0x90,0x6d,0xff,0xb7,
+  0x86,0x9d,0xca,0x42,0x20,0xc6,0xbc,0x75,0x61,0xc4,0xec,0x92,0x78,0x29,0xe7,0x10,
+  0x2e,0xc4,0xb5,0x01,0x75,0xc2,0x60,0x2e,0x8e,0x89,0xaa,0xc8,0x4a,0x80,0x40,0xd6,
+  0x52,0x80,0x34,0x62,0x88,0x36,0x17,0xa0,0xd6,0x0d,0x02,0x85,0xf3,0xdc,0x85,0xa0,
+  0xf6,0xda,0x7a,0x74,0xcd,0xf7,0x12,0xda,0x7a,0x75,0xd9,0x00,0xf2,0xfa,0x0a,0x97,
+  0xf9,0x09,0x97,0x07,0x08,0xed,0x02,0x85,0x1b,0x83,0xeb,0xd7,0xfb,0xd7,0x6c,0xf0,
+  0x7b,0xbe,0x25,0xf0,0x51,0xde,0x33,0xe1,0xdf,0xf9,0x69,0x33,0x22,0xa8,0x97,0xaf,
+  0xc4,0xad,0x5e,0xb3,0x1e,0x14,0xd8,0xc3,0x0e,0x8e,0xde,0xbe,0xc1,0x51,0xd1,0x97,
+  0x93,0xee,0xa4,0xe7,0x15,0xa2,0x6b,0xf7,0x6a,0x5f,0x36,0xb7,0xb4,0x09,0x9b,0x5b,
+  0x3b,0x9b,0x5a,0x5a,0x01,0x85,0x41,0x6d,0xac,0xa8,0xac,0x2d,0x2e,0x7e,0x9c,0x9d,
+  0xf3,0x20,0xf1,0x4e,0x6a,0xec,0xd5,0x6b,0xe1,0x11,0x17,0xbc,0xfd,0x43,0x5c,0x78,
+  0xee,0xf6,0x87,0x7e,0xdb,0xbd,0xf7,0xc0,0x96,0xef,0xb7,0xad,0xdf,0xb0,0x79,0xe5,
+  0xca,0xd5,0x0b,0x17,0x2f,0x9d,0x67,0x63,0x6b,0x69,0x65,0x6d,0x6a,0x3a,0xc7,0xd8,
+  0xc8,0x84,0x6c,0x8a,0x9e,0x3a,0x6d,0x9a,0xfe,0xe4,0x29,0x13,0xf5,0x26,0xea,0x8e,
+  0x1f,0x4f,0x3e,0x0a,0x8f,0x05,0x20,0xd6,0xd1,0xd1,0xc6,0x3f,0x2d,0x2d,0xad,0x2f,
+  0xed,0xec,0x32,0xb3,0xb3,0x7d,0x02,0x4e,0xc4,0xc4,0x5e,0xc9,0x2f,0x2c,0xc3,0xf8,
+  0x2b,0xf7,0x94,0x2e,0xcc,0x6f,0x5d,0x78,0xae,0x74,0x1f,0x17,0x39,0xd9,0x44,0x6c,
+  0x12,0xc2,0xb6,0x01,0x7f,0xaf,0x5e,0xbf,0x1e,0x18,0x72,0x32,0xf4,0x74,0x04,0xe0,
+  0x6f,0x75,0x4d,0x5d,0x4f,0x6f,0xaf,0x82,0xd1,0xa9,0xa4,0xb4,0x54,0x5b,0x4b,0x9b,
+  0x26,0xa7,0x06,0x66,0x11,0x89,0x49,0x49,0xa7,0xc3,0x41,0x05,0x76,0xe6,0xbb,0x79,
+  0x07,0x87,0x46,0xdc,0x44,0xd7,0x27,0x96,0x01,0x70,0xf4,0xf6,0xf5,0x0d,0xca,0x2a,
+  0xd4,0x70,0x6a,0x5a,0xfa,0x9a,0x35,0xeb,0x60,0xb6,0xc1,0xa6,0xa6,0x36,0x7c,0xc0,
+  0x3d,0x42,0x6d,0xc4,0xb8,0x71,0xba,0x3f,0xfd,0x74,0xf0,0x45,0x75,0xcd,0x1f,0xe8,
+  0xac,0x91,0xa2,0x9d,0x33,0x7f,0x7c,0x78,0xdf,0xf7,0xaa,0xbf,0xa1,0xb1,0xb9,0xae,
+  0xbe,0x39,0x2a,0xe6,0x22,0x24,0x94,0x62,0x92,0xb0,0x0d,0xf8,0x9b,0x9c,0x92,0x7a,
+  0x2a,0xfc,0x1c,0xe0,0x6f,0x6a,0x5a,0x26,0xe0,0x6f,0x5f,0x7f,0xbf,0x82,0xf3,0x1a,
+  0xd9,0x59,0xb9,0x93,0xf5,0xa7,0x50,0x52,0xe4,0x06,0x6f,0xd9,0x9a,0x94,0xcd,0x88,
+  0x89,0xfc,0xf1,0xbf,0xe0,0x95,0x4d,0x2b,0x65,0xd3,0x38,0x60,0x74,0x75,0x75,0x43,
+  0x42,0xc3,0x60,0x52,0xf1,0x0a,0x34,0xff,0x37,0xef,0x60,0x80,0xfd,0xe4,0x63,0x43,
+  0x2f,0x1b,0xea,0xed,0xec,0xec,0xc8,0xd1,0x72,0x76,0x65,0xc2,0xc4,0x89,0x4d,0xf9,
+  0x7f,0x30,0x24,0xad,0x8e,0xce,0xd8,0x98,0x2b,0x57,0xc3,0xc2,0x23,0x10,0xfe,0xa6,
+  0x65,0x31,0x0f,0x72,0xc9,0xd7,0x7f,0x8b,0x4b,0x4a,0xf5,0xf5,0x27,0xcb,0xd6,0x15,
+  0xbb,0x26,0xc9,0x5f,0x10,0x72,0xc8,0xe1,0xf0,0x8d,0xf8,0x24,0xc0,0x5f,0xb4,0x49,
+  0xf8,0x51,0x39,0x68,0xb8,0x52,0xef,0x30,0x4a,0x89,0xba,0xdd,0xca,0xd5,0x83,0x56,
+  0x23,0xa5,0x69,0x66,0x6e,0x51,0x58,0x5c,0x12,0x10,0x14,0x82,0xf0,0x37,0x1f,0xe1,
+  0xaf,0xe2,0xed,0x76,0x1e,0x9e,0x5e,0x1a,0xea,0xa3,0x68,0x2b,0x48,0x35,0x87,0x62,
+  0x2f,0x2d,0x05,0x3b,0x02,0xfd,0x6b,0xfd,0x86,0x0d,0xf7,0x32,0x73,0x7c,0xfc,0x82,
+  0x2f,0x5d,0xbe,0x5e,0x58,0x5c,0x0a,0xfa,0x6f,0xbf,0xfc,0x83,0x6f,0xd0,0xce,0x0e,
+  0x47,0x8e,0x2a,0xc8,0x17,0xa0,0x13,0x6c,0x4d,0x8d,0x51,0xf3,0x6d,0x16,0x54,0xd7,
+  0xbe,0x44,0xbd,0xe3,0xd3,0xaf,0x39,0x7c,0x78,0xd5,0xff,0xa6,0xaf,0xff,0xd5,0x61,
+  0x87,0x23,0xe4,0xd8,0xa3,0xea,0x30,0x55,0x59,0x3e,0xff,0x5b,0x79,0xf8,0x48,0xc0,
+  0xd4,0x06,0x44,0x4e,0x5b,0xcf,0x74,0x8e,0x7d,0xbe,0x25,0xc6,0x11,0x84,0x71,0x9c,
+  0xc6,0x89,0xcb,0x9c,0x94,0x94,0xd4,0x94,0x3e,0x53,0x1f,0x3b,0x77,0xa7,0x89,0x43,
+  0x85,0x99,0x73,0xbd,0xb9,0x73,0x83,0xb9,0x4b,0xab,0xb5,0xfb,0x80,0xee,0x66,0xc1,
+  0x6b,0x83,0x40,0x0b,0xa7,0x6a,0x83,0x9d,0x09,0xea,0x93,0x6c,0x86,0xfc,0x43,0x49,
+  0x65,0xe4,0x78,0xc3,0xdd,0x77,0x2d,0xf9,0x9d,0x16,0x98,0x0e,0x31,0x08,0x95,0xf8,
+  0x62,0x2b,0x01,0xb2,0x01,0xbe,0x2d,0x90,0x1b,0x81,0x1a,0x06,0x26,0xb1,0xa5,0x40,
+  0x64,0x85,0x10,0x4d,0x64,0x21,0xe8,0xc2,0x91,0x85,0xd4,0x26,0x9f,0x44,0x2d,0xf8,
+  0x04,0xf4,0x21,0x44,0x84,0x09,0xa2,0x05,0x5b,0x4b,0xb4,0x72,0x2b,0x94,0xa4,0x15,
+  0x12,0xca,0x00,0x6d,0x24,0x32,0xb5,0x09,0x29,0x4b,0x1c,0x87,0x24,0x81,0x7c,0x11,
+  0x27,0x78,0x89,0x18,0x51,0x73,0x13,0x59,0xb9,0x21,0x00,0x25,0x69,0xe1,0xdf,0xb9,
+  0x6e,0x22,0x36,0x11,0x88,0x69,0x29,0x10,0x93,0x7c,0x2d,0xb1,0x4d,0x81,0x1e,0x7d,
+  0xb4,0x45,0xa9,0x50,0x38,0x72,0x08,0xba,0x21,0xe4,0x0b,0xf7,0x2e,0x4b,0x3e,0x01,
+  0x59,0x94,0x0a,0x58,0xb5,0x46,0x7c,0x22,0x07,0x62,0x1b,0x3b,0xe6,0x7b,0x8a,0xe6,
+  0xb9,0x8b,0xe6,0x7b,0x0a,0x6d,0x3c,0x45,0x36,0xde,0xff,0xcf,0xdc,0x75,0xc7,0x45,
+  0x75,0x7c,0xfb,0x3f,0xde,0x4b,0xf2,0xcb,0xcf,0x42,0xef,0xbd,0x59,0x7e,0x1a,0x63,
+  0x07,0x96,0xb6,0x54,0x15,0x51,0xec,0x85,0x98,0xe8,0x4b,0x4c,0xd1,0xa8,0x3f,0x4d,
+  0x62,0x30,0x1a,0x4b,0x50,0xea,0x02,0x16,0xea,0xd2,0x51,0xa9,0x22,0x1a,0x0b,0x6a,
+  0x54,0x7a,0x13,0x3b,0x88,0x74,0x11,0xa4,0xed,0x72,0xb7,0x01,0x2a,0x3f,0xd0,0xcf,
+  0xe7,0x9d,0x33,0xb3,0xbb,0x20,0xca,0xa6,0x99,0xf7,0xb2,0x9f,0xc3,0x30,0x33,0xf7,
+  0xdc,0x33,0x67,0xce,0xcc,0x9d,0xef,0x9c,0x7b,0xe7,0xce,0x15,0xb0,0x39,0x02,0x74,
+  0x7b,0x43,0x05,0x0b,0x8e,0x31,0x4b,0xc2,0xbb,0x97,0x87,0xf3,0x57,0x47,0xb4,0xaf,
+  0x0d,0x6f,0x5e,0x1b,0xfa,0x60,0x5b,0x5c,0x4d,0x97,0x48,0xd1,0x1c,0xfe,0x6f,0x42,
+  0x0f,0x6b,0x6b,0x57,0xae,0x5a,0xbd,0x72,0xb5,0xd7,0xbf,0xb7,0x7f,0xeb,0xe3,0x17,
+  0x1c,0x97,0x78,0xf2,0xe7,0x0b,0x39,0x45,0x25,0xe5,0x55,0xd5,0x35,0x0d,0x4d,0x2d,
+  0x6d,0x1d,0x4c,0x17,0x4f,0x00,0x17,0x51,0x17,0x9f,0x01,0x08,0x6e,0x6a,0x6e,0xad,
+  0xae,0x6d,0xa8,0xb8,0x5d,0x59,0x50,0x54,0x72,0x3e,0xe7,0x0a,0x38,0x80,0x31,0xf1,
+  0x89,0x9c,0xd0,0xb0,0x7d,0x07,0x0e,0x7d,0xf3,0x9d,0x37,0xf5,0x82,0x41,0x94,0xfb,
+  0xc2,0x45,0xce,0xae,0xf3,0x10,0x82,0xad,0xac,0x67,0xcf,0x99,0x4b,0x1d,0xe1,0xc9,
+  0x93,0x09,0x0a,0x5b,0x4c,0x30,0x33,0x33,0x37,0x36,0x31,0x31,0x30,0x34,0x24,0xab,
+  0xa3,0x75,0x75,0x74,0xf4,0x74,0x74,0x70,0xd7,0x68,0x67,0x57,0xd7,0xe2,0xb2,0xb2,
+  0xd0,0xc3,0x47,0x4f,0xa6,0x66,0x96,0x96,0xdf,0x7a,0xd2,0xde,0xf1,0x6c,0xf4,0x57,
+  0x6f,0xf0,0x2d,0xa1,0xd0,0x23,0x4a,0xe3,0x94,0x95,0x95,0x94,0xc9,0x2e,0x97,0x4a,
+  0x70,0x5d,0xd0,0x4d,0xa7,0x61,0x4c,0x7e,0x25,0x1c,0x3b,0xde,0xd0,0xd0,0x88,0x6c,
+  0x8b,0x97,0xc0,0x8d,0x49,0xba,0x72,0x2d,0xbf,0xa1,0xe9,0x11,0x6e,0xba,0x3b,0xfa,
+  0x08,0xdf,0xd0,0xd8,0x08,0x5a,0x29,0x29,0xe1,0x52,0x6d,0xf8,0x29,0xa1,0x18,0xfc,
+  0xa9,0xaa,0xa8,0x7e,0xb5,0x79,0x4b,0x49,0x59,0xf9,0xee,0x1f,0xf7,0xed,0xde,0x7b,
+  0x20,0x20,0xe8,0x48,0x42,0xf2,0x89,0x9c,0xcb,0xb9,0x95,0xd5,0x75,0x5d,0x3c,0xa6,
+  0xef,0x69,0xdf,0x68,0xb3,0x85,0xf6,0xce,0x8e,0x23,0x47,0x8e,0x81,0xaf,0xaa,0xa3,
+  0xad,0x83,0xd2,0x88,0xce,0x28,0x5c,0x49,0x19,0x8c,0xb0,0xc0,0x7d,0x21,0x4c,0x39,
+  0x24,0x3d,0xf8,0xcd,0x1a,0xc5,0xb8,0x33,0x30,0xf0,0xa2,0xa7,0xf7,0x59,0x27,0x8f,
+  0x5f,0x5b,0xdf,0xf8,0xa4,0xbd,0x1d,0xec,0xac,0xac,0xa4,0x82,0x0f,0xd0,0x49,0xc5,
+  0xc1,0x02,0x68,0x84,0xf1,0x28,0x19,0x86,0xac,0xec,0x73,0xe7,0x13,0x12,0x93,0x62,
+  0xe2,0x8e,0x5f,0xfe,0x25,0x1f,0xe0,0x43,0xd2,0xd3,0xa7,0xe0,0x21,0x63,0xc5,0xad,
+  0x9b,0x93,0x27,0x4d,0xa1,0x46,0x03,0x0d,0xe5,0x96,0x04,0x23,0x00,0x94,0x4b,0x2d,
+  0x49,0x24,0xcb,0x6d,0x4b,0x92,0x2a,0xb4,0x50,0x30,0x97,0x95,0xa5,0x95,0xad,0x8d,
+  0xad,0x94,0x6c,0xed,0x90,0x48,0xc4,0x86,0x65,0x63,0x67,0x67,0xc7,0xb2,0x86,0x04,
+  0x84,0x2c,0x88,0x43,0x8e,0x94,0x81,0xf2,0x10,0xb6,0x65,0x2b,0x56,0x40,0xeb,0xff,
+  0xae,0xae,0x7b,0xf7,0xfe,0x7d,0x37,0xb7,0x79,0x44,0x25,0xd4,0x41,0x69,0x1c,0x74,
+  0x00,0xac,0xbe,0x12,0x31,0x2c,0x59,0x57,0x30,0x9e,0x1a,0x87,0xd6,0x08,0x43,0x5c,
+  0xf6,0x47,0xac,0x44,0x3b,0xcc,0x58,0x64,0x96,0xb2,0xc9,0x98,0xb1,0xd6,0xe3,0x94,
+  0x75,0xb4,0x74,0x13,0x92,0x8f,0xc7,0x25,0x25,0x47,0x45,0xc7,0x42,0x9f,0xa9,0xa9,
+  0x6f,0x22,0x6f,0xe9,0x2a,0xba,0x8e,0x26,0x4d,0x9a,0x4c,0xbf,0xbf,0x49,0x3a,0x8d,
+  0xb4,0xcf,0xd0,0x72,0xa9,0x25,0xa9,0xad,0x20,0xb9,0x79,0xcb,0xe6,0xf3,0x97,0x2e,
+  0x03,0x5c,0x66,0x9f,0xbd,0x70,0xe7,0xfe,0x03,0x3e,0xc3,0x28,0x78,0x9a,0x09,0x9e,
+  0xec,0xea,0x35,0x5e,0x64,0xa5,0x84,0x8a,0x12,0xd9,0xce,0x46,0xd6,0xb1,0x87,0xaa,
+  0x30,0x75,0xea,0xb4,0x9b,0xb7,0xef,0x1d,0x0e,0x8b,0x4e,0x4e,0x49,0x2f,0x2d,0xbf,
+  0x89,0xf8,0xab,0x70,0x79,0x52,0x5a,0x46,0x96,0xab,0xeb,0x3c,0x67,0x17,0x57,0x24,
+  0x67,0x29,0x39,0x39,0xbb,0x38,0x39,0x21,0x8d,0x96,0xa4,0xfc,0xe6,0x16,0x13,0xc0,
+  0xc6,0xf8,0x52,0xbf,0x92,0xf4,0xa2,0xa3,0x7d,0x83,0xd6,0xce,0x7d,0xa1,0xc7,0xb5,
+  0xbc,0xfc,0xa0,0x50,0xa9,0xff,0xdb,0xd9,0x85,0xb3,0x68,0x05,0x8d,0x18,0xc5,0x8d,
+  0x53,0x54,0xae,0x8b,0xab,0xc7,0xa2,0x25,0x3e,0x3e,0x07,0xab,0x6b,0x6a,0x7e,0x63,
+  0xaf,0xe8,0xeb,0x1f,0x10,0x89,0x7b,0xba,0x19,0xa1,0xd7,0x47,0xeb,0xd0,0x38,0xe3,
+  0x95,0xe5,0x44,0x4c,0xf7,0x6a,0xeb,0x8f,0x7b,0xb5,0xf5,0x49,0x8e,0xb4,0xab,0x8c,
+  0xc5,0xae,0x82,0xef,0x6b,0x28,0x93,0xeb,0x6b,0xac,0xb4,0x82,0x23,0xba,0x8a,0x91,
+  0x95,0x97,0xd5,0xfe,0x16,0x5b,0x3f,0x04,0x2c,0x96,0xaf,0x68,0xf2,0x27,0x99,0x63,
+  0x94,0xf5,0xde,0x7d,0xe7,0x5d,0x5d,0xd6,0x57,0x73,0xf7,0x35,0xcd,0xd8,0x59,0xa5,
+  0x63,0xf9,0x3f,0xda,0x53,0x16,0x4f,0x58,0x99,0x08,0x68,0xc2,0xf2,0x03,0x42,0xbc,
+  0x9b,0xe8,0x75,0x5c,0x73,0xea,0x52,0xf5,0xa9,0x9e,0x13,0xbd,0x12,0x67,0x6c,0x2f,
+  0x1b,0x6f,0x30,0x1b,0xd7,0x71,0x59,0xb8,0xce,0xf4,0x7e,0xc8,0x22,0x70,0x63,0x83,
+  0xee,0x9e,0x08,0x42,0x16,0x71,0xfa,0x58,0xc4,0xfb,0xa3,0x21,0x02,0x13,0x09,0x31,
+  0x49,0xf0,0xcb,0xc6,0x1f,0x99,0x59,0x7e,0x02,0x2b,0x3f,0x00,0x62,0x01,0xcb,0x57,
+  0x68,0xe5,0x2b,0x04,0x34,0x04,0x44,0xb3,0xf6,0x43,0xe8,0x24,0x0c,0x00,0x61,0x90,
+  0x04,0x06,0x31,0xe4,0xb3,0xfc,0xe1,0x28,0x38,0x95,0xc8,0x03,0x87,0xac,0xfc,0x44,
+  0x24,0x29,0xa2,0xa2,0x6c,0xfc,0x01,0x1f,0x85,0x18,0x1e,0x82,0x10,0x94,0x11,0xd1,
+  0x52,0xec,0xfc,0x45,0x96,0xbe,0x88,0xbc,0x2c,0x7f,0xa1,0x15,0xde,0xfb,0x85,0x4c,
+  0x94,0x09,0x49,0xd9,0x89,0xc8,0xcc,0xf2,0x47,0xb5,0xb1,0x22,0x44,0x7f,0x99,0x28,
+  0x54,0x18,0xe7,0x06,0x58,0x10,0x92,0x25,0x32,0x88,0x48,0xe9,0x0c,0x09,0xe5,0xa2,
+  0x04,0x20,0xd6,0x06,0x4a,0x24,0x55,0xb0,0xf5,0x47,0xa3,0xe1,0x13,0x5e,0x3f,0x2c,
+  0x97,0x15,0x20,0x72,0x08,0xc4,0x1b,0xce,0x8e,0x1c,0x91,0x53,0x08,0x33,0xff,0xa8,
+  0x68,0x61,0xb8,0xc8,0x33,0x8a,0x59,0x11,0xdd,0xed,0xc5,0xe5,0x7f,0xc4,0xed,0x5a,
+  0x1f,0xdd,0xf8,0x71,0x44,0x5d,0x64,0xce,0xe3,0xdf,0xf5,0xc1,0xd0,0xff,0x2f,0x7a,
+  0xd6,0xff,0xfc,0x9b,0x6f,0x77,0x2e,0xf2,0x5c,0xf6,0xe5,0x57,0x5f,0xef,0xd9,0xe7,
+  0x13,0x1e,0x15,0x9b,0x95,0x7d,0xfe,0x5a,0x7e,0xc9,0x9d,0xfb,0x0f,0xeb,0x1b,0x1f,
+  0x03,0xe6,0xf2,0xba,0x85,0x3c,0xbe,0xb0,0x9b,0x11,0x75,0xf2,0x98,0x96,0x27,0xbc,
+  0x86,0xa6,0xd6,0x07,0x0f,0x1b,0x6f,0x54,0xdc,0x2b,0x28,0x2a,0x3d,0x7f,0xf1,0x0a,
+  0x5c,0xc8,0x31,0xf1,0xc9,0x30,0xdd,0xdd,0xff,0x93,0xff,0xce,0xef,0xf7,0x6c,0xda,
+  0xbc,0x75,0xfd,0x86,0x4f,0x57,0xac,0xf2,0x5a,0xe4,0xb9,0xdc,0xd5,0x6d,0x81,0x83,
+  0xa3,0x13,0xcb,0xd6,0x6e,0xce,0x9c,0xb9,0x33,0x67,0xce,0x9a,0x36,0x6d,0x1a,0xb9,
+  0x1d,0x8d,0xdb,0x64,0x01,0xd1,0x77,0x94,0x4c,0x4c,0x4d,0xf4,0x0c,0xf5,0xe9,0x7e,
+  0x1d,0xf6,0x6c,0xc7,0x82,0xe2,0x92,0xc3,0x61,0x11,0x29,0xa9,0x99,0x65,0x37,0x6e,
+  0x3d,0x69,0xeb,0x7c,0x3a,0xfa,0x4d,0x48,0x80,0x92,0x18,0x6e,0x2c,0xae,0xe3,0x52,
+  0x51,0x53,0x53,0x81,0x50,0x15,0x08,0x21,0x52,0x59,0x0d,0xf0,0x42,0x4d,0x55,0x8d,
+  0x12,0x59,0xe5,0xa5,0x02,0xf8,0x7b,0x22,0x25,0x35,0x36,0x3e,0x99,0x1b,0x93,0x78,
+  0xf9,0x97,0x3c,0x70,0x06,0x45,0x62,0x45,0x9b,0xde,0xb7,0xb6,0xb5,0x99,0x9a,0x98,
+  0xa9,0x2a,0xe3,0xe7,0x14,0x69,0x08,0x43,0x9f,0x9a,0x1a,0x8a,0xfa,0xd7,0xbf,0xa6,
+  0x64,0x9f,0x39,0x9b,0x90,0x9c,0xbc,0x7b,0xef,0xfe,0x03,0x3e,0x01,0xa1,0x47,0xc3,
+  0x8f,0xa7,0x64,0x5e,0xcf,0x2f,0x82,0xd9,0x0a,0xaf,0x5b,0xd0,0xd7,0x27,0x7d,0xc6,
+  0xfa,0xba,0xf0,0xfe,0x81,0xfe,0xc7,0x2d,0xad,0x17,0x72,0x2e,0xed,0xd9,0xb3,0x6f,
+  0xc3,0x86,0x8d,0xab,0x57,0xaf,0xfd,0xf4,0xb3,0xcf,0x0f,0xfc,0x74,0xe8,0xea,0xf5,
+  0xfc,0x4e,0x5e,0x97,0xe2,0x8f,0x23,0xc8,0xaa,0x0c,0x9e,0x6f,0x1f,0x8f,0xcf,0x54,
+  0x3f,0xac,0xaf,0x6f,0x6c,0x4a,0xcd,0xc8,0xd4,0xd2,0xd2,0xa2,0x15,0xc4,0x9a,0xaa,
+  0x60,0x04,0xb4,0x45,0x55,0x55,0xd5,0xd4,0xd5,0xd5,0x53,0xd3,0x33,0x92,0x4f,0xa4,
+  0x45,0xc7,0x26,0x40,0x95,0x6b,0xea,0x1e,0xe1,0x26,0x4b,0xa3,0x57,0x19,0xb0,0x6c,
+  0xfa,0xf4,0x19,0x70,0x3a,0x08,0x54,0x55,0x51,0x57,0x51,0x52,0x03,0x22,0x49,0xa4,
+  0xa1,0x24,0x9a,0x1a,0x19,0x80,0x8d,0x3e,0xbe,0x47,0x66,0x65,0x15,0x0f,0x8f,0x45,
+  0xf7,0x2b,0x2b,0x8b,0x4b,0x4b,0xef,0xdc,0xbd,0x57,0x53,0x5b,0xf7,0xb8,0xa5,0xa5,
+  0xb3,0x8b,0xd7,0xde,0xd1,0xd9,0xd1,0xc1,0xe3,0xf1,0xf9,0x40,0x5d,0x3c,0x7e,0x57,
+  0x17,0x0f,0x68,0x44,0x12,0x03,0x3e,0x84,0x7c,0xe0,0x97,0xf4,0xf6,0xfc,0xae,0xae,
+  0x0b,0xa6,0x0e,0x8f,0x88,0x52,0x53,0xd5,0x50,0xc5,0x86,0x7e,0x45,0x67,0x6c,0x7d,
+  0xa2,0x2a,0x28,0x49,0x7a,0x82,0xb4,0x9f,0x90,0xa4,0x3a,0xd5,0x5c,0x8d,0x92,0xea,
+  0xeb,0xcc,0x50,0x41,0x55,0x5d,0x1d,0xdd,0x98,0xb8,0x78,0x30,0x60,0x64,0x74,0xfc,
+  0xa5,0x5f,0xf0,0x2d,0x5d,0xb1,0x58,0xa2,0xe0,0xce,0xe7,0xa3,0xe6,0x96,0x19,0x33,
+  0x66,0xbd,0xd1,0x74,0xf2,0x38,0x12,0x51,0x66,0xfd,0x86,0xcf,0xae,0x5c,0xcb,0x3d,
+  0x7c,0x24,0x1c,0xbf,0x00,0x75,0xa7,0x0a,0x5f,0xb5,0x1b,0x1d,0xa4,0x00,0x7f,0x37,
+  0x6e,0xfc,0x02,0xcd,0xfe,0x6a,0x73,0x60,0xb7,0x1c,0xaf,0xa2,0x46,0xda,0x02,0xa0,
+  0xbf,0xfc,0xe6,0xad,0x63,0x51,0x71,0xc7,0x53,0x32,0x0a,0x4b,0x6e,0xb6,0xb4,0xfe,
+  0xca,0xeb,0xde,0x4f,0x9f,0x3f,0xed,0x16,0x30,0xfc,0x6e,0x06,0xa0,0x1f,0x42,0x88,
+  0xff,0x16,0xe2,0xe1,0x92,0x03,0xc6,0xe7,0xe0,0x41,0x0d,0x0d,0x4d,0x15,0x25,0x55,
+  0x54,0x49,0x75,0x64,0x7d,0x5d,0xdc,0xdc,0xf2,0x0a,0x0a,0x43,0x8f,0x84,0xa5,0xa6,
+  0x67,0x97,0x94,0xdd,0x84,0xb9,0xe2,0xb3,0x67,0x8a,0xf0,0x17,0x1c,0x55,0x54,0x80,
+  0x19,0xb5,0x50,0xa1,0x58,0xa4,0xf8,0x59,0xf6,0xb0,0xfe,0x80,0xc3,0x82,0xb8,0xa7,
+  0xb7,0xad,0xa3,0xb3,0xb6,0xbe,0xde,0xc6,0xc6,0x1e,0x86,0x02,0xd2,0x51,0xd5,0xe4,
+  0xd7,0xf2,0x70,0x7a,0x43,0xeb,0xab,0xd1,0x4e,0x42,0xe2,0x43,0xbd,0x45,0x4d,0xd6,
+  0x85,0xb0,0xab,0x03,0x0b,0xed,0xfc,0x78,0x95,0xa9,0x6a,0x4d,0xfd,0x24,0xde,0xfa,
+  0x10,0x63,0x1f,0x80,0x58,0x69,0xf9,0x53,0xa7,0x8a,0x85,0x13,0x38,0xb3,0xaa,0x16,
+  0x8e,0x33,0xbc,0x1f,0xda,0x04,0x30,0x33,0xb6,0x17,0x8f,0x51,0x37,0x03,0x6c,0x35,
+  0x72,0xdd,0x05,0x5e,0x1b,0x81,0x27,0xc1,0xdc,0x5d,0x55,0xca,0x46,0xb3,0x20,0x53,
+  0x49,0x7b,0xea,0xb4,0xad,0xa5,0x90,0x39,0xf1,0xe3,0x8c,0xf7,0x95,0xf5,0xde,0x7b,
+  0xef,0x9f,0x26,0x8b,0x83,0x6d,0x08,0x48,0xd9,0x12,0x4e,0x40,0x34,0x3c,0xcb,0x8f,
+  0x26,0x65,0x0b,0x8d,0x46,0x10,0xb9,0x1f,0xcb,0x42,0xcc,0x82,0xa4,0x40,0xba,0x1e,
+  0x49,0x1a,0x0a,0xe8,0x89,0x04,0x28,0x09,0x0a,0xcb,0x8e,0x02,0xc6,0x59,0xfb,0x8b,
+  0xc8,0x51,0x8a,0xb0,0x94,0x13,0x4f,0xa7,0x21,0x3d,0xd7,0x16,0x01,0x54,0xc8,0x22,
+  0x71,0x8a,0xcb,0x38,0x25,0x00,0xec,0xf6,0x85,0x1c,0x11,0x99,0x0f,0x88,0x48,0x59,
+  0x00,0xfd,0x22,0x02,0x94,0x90,0x2f,0x40,0x1c,0x0f,0x10,0xd0,0x43,0x36,0xa8,0x12,
+  0xc0,0x28,0xb8,0xde,0x42,0xc4,0x65,0xbf,0x21,0xb5,0x59,0x44,0x6d,0x79,0x45,0xa4,
+  0xba,0xc9,0x72,0xac,0x65,0x55,0x00,0x7d,0x40,0x55,0x74,0x78,0x03,0x05,0x0e,0x41,
+  0x22,0x7b,0x8e,0xc0,0x25,0x58,0xc0,0x0e,0x66,0x5c,0x42,0x44,0xee,0x61,0x02,0x8f,
+  0x08,0xc1,0x32,0xae,0x78,0x65,0xac,0x60,0x5d,0x3c,0xb3,0x21,0x9e,0xb7,0x31,0xa9,
+  0x73,0x63,0x5c,0xeb,0x67,0x31,0x75,0xb9,0x55,0xfc,0xb7,0x8e,0x95,0x7f,0x11,0xc5,
+  0x27,0x26,0x2f,0xf4,0x58,0xb4,0x7e,0xc3,0xc6,0xef,0xbd,0xf7,0xc0,0x85,0x93,0x92,
+  0x76,0xfa,0xca,0xd5,0xbc,0xf2,0x9b,0xb7,0xc1,0xc9,0x7a,0xd4,0x0a,0xc3,0x23,0xc3,
+  0x08,0x44,0x78,0x81,0x30,0x22,0x88,0xb7,0x3c,0x69,0x07,0x08,0xbe,0x57,0x59,0x45,
+  0xb6,0x86,0x2e,0x39,0x7b,0xfe,0x22,0x5c,0x68,0xdc,0xb8,0xf8,0x90,0xc3,0xe1,0x07,
+  0x0e,0x06,0x7c,0xe7,0xfd,0xc3,0x96,0xad,0x3b,0x00,0x5f,0xd6,0xac,0xfd,0xc8,0x73,
+  0xc9,0xca,0x79,0xf3,0xdd,0x1d,0x9d,0xdd,0xc0,0xf5,0xb1,0xb4,0x62,0xcd,0x99,0x6d,
+  0x09,0x23,0x3c,0xa0,0xf0,0x94,0x29,0x53,0xc0,0x17,0x36,0x37,0x9f,0x68,0x66,0x86,
+  0x28,0x6c,0x6c,0x66,0x62,0x64,0x6c,0x0c,0x10,0x69,0x67,0xcf,0xce,0x2d,0x28,0x09,
+  0x8b,0xe4,0x02,0xa2,0x95,0x94,0x57,0xb4,0xb6,0xe1,0x5b,0x42,0xa3,0xbe,0xfd,0xfa,
+  0x62,0xf0,0xc4,0x89,0x54,0x5c,0x4a,0x4d,0xf6,0xf7,0xd0,0xc0,0xb7,0x9b,0x74,0xe4,
+  0x49,0xf2,0x6f,0x28,0x04,0x5f,0x3b,0x36,0x21,0x3e,0xe9,0xc4,0xc9,0xe8,0x98,0xc4,
+  0x4b,0x57,0xae,0xd5,0xa1,0x2f,0xa3,0x68,0x83,0x7a,0xf0,0xf7,0x01,0x67,0xd5,0x65,
+  0x3f,0xdc,0x3f,0x44,0x4d,0x2a,0x19,0xfc,0xf4,0xe5,0x2b,0x57,0x55,0xdc,0xbd,0x13,
+  0x14,0x12,0xba,0x77,0xbf,0x8f,0x1f,0x7e,0xf4,0x9c,0x9b,0x9a,0x9e,0x95,0x57,0x50,
+  0x5a,0x53,0xd7,0x04,0x5e,0x70,0x2f,0xf1,0x82,0x15,0x4c,0xbd,0x06,0x06,0x07,0x7a,
+  0xfb,0x7a,0x45,0x12,0x31,0x72,0xfe,0xb6,0x0f,0xcb,0xbe,0xc0,0x6f,0xab,0x0d,0x02,
+  0xb8,0x03,0x48,0xd5,0xd4,0x35,0xde,0xbc,0x5d,0x75,0xbf,0xea,0xc1,0x22,0x4f,0xcf,
+  0xe1,0xf5,0x55,0x57,0xa3,0x21,0x4d,0x42,0xa8,0x13,0x9b,0x90,0x94,0x96,0x9e,0x15,
+  0x13,0x0b,0x53,0x8e,0x5c,0x68,0x4a,0x89,0xa4,0x47,0x41,0x71,0x35,0xb5,0xf5,0x56,
+  0x56,0x2c,0x59,0x8d,0x87,0x4c,0x37,0xc2,0x92,0xc3,0x42,0x0d,0x39,0x03,0xfc,0x16,
+  0x7b,0x2e,0x29,0x2a,0x29,0x8f,0xe2,0x26,0x9c,0x3e,0x73,0xfe,0xce,0xbd,0xca,0x2e,
+  0x3e,0xbf,0x7f,0xf4,0x1b,0xaa,0x6f,0x91,0x32,0x32,0xb3,0xc8,0xf7,0x3e,0xb0,0xbe,
+  0xea,0x6f,0xf3,0xa7,0xa9,0xab,0xa7,0x1f,0xcd,0x8d,0x49,0x49,0x4b,0x8f,0x88,0x44,
+  0xfc,0x7d,0x58,0x5b,0xaf,0xf8,0x2d,0xa1,0x8e,0xce,0x4e,0x6b,0x6b,0x6b,0x69,0x2b,
+  0xfc,0xca,0x4f,0x63,0x8d,0xd7,0xba,0xdc,0xfc,0xc2,0xa3,0xc7,0x22,0x4f,0x9d,0x3e,
+  0x77,0xfb,0x2e,0x98,0x8b,0x51,0xb0,0x49,0x05,0xc0,0xca,0xf6,0x1d,0x3b,0x87,0x5b,
+  0x5b,0xde,0x10,0x64,0x05,0x05,0xfe,0x2c,0x2c,0x2c,0x4a,0x6f,0x54,0x84,0x45,0xc7,
+  0xc3,0xb5,0x53,0x5c,0x5a,0x0e,0xf8,0xab,0x78,0xb9,0xdd,0x9f,0xa1,0xc8,0xa8,0x18,
+  0x5d,0x5d,0xfd,0x11,0x0a,0xd0,0x2e,0x01,0x11,0x7b,0x07,0x87,0xbc,0xc2,0xa2,0xc3,
+  0x61,0x91,0xc9,0xe9,0x3f,0x97,0x94,0xde,0xec,0xe8,0xe2,0xf7,0xf6,0x8d,0xf2,0xe9,
+  0xae,0xb7,0x4d,0x03,0x83,0x38,0x41,0x6d,0xef,0xe0,0x3d,0x7a,0x0c,0x13,0xdd,0x2b,
+  0x60,0x13,0xaa,0xd8,0x08,0xd3,0xfd,0x81,0x9f,0x4c,0x82,0x06,0xd9,0xd9,0x7e,0x28,
+  0x5b,0xd7,0x78,0xf2,0xdc,0xdd,0xd5,0x00,0x25,0x76,0x80,0x3e,0x7e,0x82,0xe9,0x5f,
+  0x5f,0x7f,0xe7,0xdd,0xb1,0xef,0xfe,0x43,0x69,0xe2,0x9a,0x78,0x16,0xde,0x2c,0x15,
+  0xce,0xdc,0x5e,0x36,0x46,0xdd,0x02,0xdf,0x07,0x74,0xd9,0x65,0x03,0xf8,0x05,0x60,
+  0xea,0xcb,0x33,0xf7,0x0c,0x01,0x36,0xc8,0x34,0x5b,0xb0,0xdf,0xfa,0x50,0xa7,0x4d,
+  0x80,0x70,0xce,0xbe,0x56,0x1d,0xcb,0x0d,0xe8,0x02,0x9b,0x3b,0x58,0x1f,0x68,0x61,
+  0x91,0x65,0x45,0x80,0xbc,0xb6,0xd4,0x27,0xf5,0x23,0xe8,0x46,0x33,0x87,0x85,0x08,
+  0x4c,0x24,0x2e,0xa7,0x37,0x33,0x03,0xb0,0x4a,0xa1,0x1f,0x11,0x0d,0x7c,0x58,0xf9,
+  0x51,0x29,0xbc,0x82,0xb3,0xe9,0x37,0x0c,0x34,0x03,0x18,0x69,0xe8,0x2f,0x92,0x42,
+  0xb9,0x4c,0x32,0x30,0xd3,0x53,0xe4,0x25,0x42,0x1c,0xcf,0x45,0x57,0x1d,0x51,0x1b,
+  0xbd,0x69,0x99,0xe6,0x72,0x06,0xf9,0x51,0xf4,0xeb,0x09,0xee,0xdb,0x20,0x82,0x4b,
+  0x28,0xd6,0x43,0x12,0xd7,0x50,0x05,0x92,0xb3,0x02,0x71,0x19,0x33,0xde,0x5e,0xf6,
+  0x95,0x25,0x09,0xc1,0x51,0x72,0xb7,0x59,0xec,0x1c,0xcc,0x38,0x71,0x04,0xf3,0x0e,
+  0x0b,0xdc,0xc3,0x98,0x85,0xe1,0xe2,0xa5,0x88,0xbc,0x92,0x8f,0x12,0x7b,0x3f,0x49,
+  0x60,0x3e,0x3b,0x2e,0xf8,0x3c,0x99,0xb7,0x29,0xf9,0xc9,0x96,0xc4,0x06,0xef,0xd4,
+  0xfa,0x66,0xfe,0xdf,0xf4,0xb3,0x47,0xaf,0x13,0x0c,0xe6,0x2b,0x57,0xad,0x5d,0xb9,
+  0x66,0xdd,0xe6,0x2d,0x3b,0x7c,0x7c,0x39,0x31,0xf1,0xc7,0xcf,0x9e,0xbb,0x50,0x50,
+  0x72,0xeb,0x5e,0x55,0x75,0x53,0xf3,0x93,0xb6,0x8e,0x6e,0x98,0xa0,0x32,0x02,0xb1,
+  0x40,0x88,0x28,0xdc,0xd1,0x85,0x2b,0xa2,0xeb,0x1b,0x5b,0xab,0xaa,0xeb,0x6e,0xde,
+  0xae,0xcc,0x2f,0x2c,0xbd,0x78,0xe9,0x97,0xf4,0xcc,0xec,0xb8,0xc4,0xe3,0xa1,0x61,
+  0xdc,0x43,0x87,0x82,0x7e,0xd8,0xb3,0x7f,0xdb,0xf6,0x6f,0x37,0x7e,0xbe,0x69,0xdd,
+  0xc7,0x9f,0x2e,0x5b,0xb1,0x66,0xd1,0xe2,0x65,0xae,0xf3,0x3c,0xd8,0x8e,0x6e,0x2c,
+  0x5b,0x7c,0x22,0x3c,0x7b,0xf6,0x9c,0x99,0x33,0x67,0xca,0x96,0x66,0x4d,0x99,0x30,
+  0x01,0x51,0xd8,0xc2,0x02,0x42,0x73,0x5b,0x3b,0xfb,0xfc,0x82,0xa2,0x88,0xc8,0x98,
+  0x93,0x30,0x86,0xc0,0x1c,0xfe,0x49,0x7b,0x8f,0xc2,0x2b,0xf7,0xec,0xb9,0x8b,0x30,
+  0x48,0x6a,0x69,0xe9,0x68,0x69,0xeb,0x6b,0x6a,0x49,0x23,0x30,0x1a,0x6b,0x69,0xeb,
+  0x6a,0x69,0xeb,0x01,0x1e,0xd3,0x85,0x5e,0x90,0xd4,0x37,0x30,0x8a,0x88,0x88,0xcc,
+  0x38,0x75,0x26,0x0a,0xf1,0xf7,0x3a,0x38,0x83,0xe8,0xff,0xbe,0x78,0x83,0x97,0x4a,
+  0x89,0x11,0x8a,0x66,0xcf,0xb1,0x04,0x81,0x20,0x43,0x5b,0x47,0x0f,0x23,0xba,0x06,
+  0x54,0x14,0xa0,0x3c,0xb8,0xea,0x21,0xa1,0x87,0x61,0x90,0xd9,0xef,0xe3,0xbb,0xff,
+  0x27,0xdf,0x83,0x01,0x87,0x41,0xe7,0xb4,0x8c,0xec,0xdc,0xbc,0xe2,0x87,0x35,0xf5,
+  0xed,0x9d,0x5d,0x30,0x08,0x28,0x58,0xf3,0xf9,0xbb,0xe9,0x25,0x82,0xaf,0x58,0xd2,
+  0x07,0x43,0xd9,0xfd,0x07,0x75,0x45,0x25,0x37,0x1a,0x9a,0x1e,0xef,0xfa,0x61,0xb7,
+  0x81,0x81,0x81,0xbc,0xbe,0xda,0xda,0x3a,0x9a,0xa4,0xbe,0xda,0x3a,0xba,0x58,0x7d,
+  0x30,0x85,0x96,0x4e,0x4c,0x6c,0x5c,0xc6,0xa9,0x6c,0x98,0x72,0xe4,0x5c,0xce,0xab,
+  0xae,0x69,0x12,0x8b,0x7b,0x15,0x3c,0x59,0x6e,0x6e,0x69,0x65,0x3b,0x39,0xa3,0x28,
+  0x1d,0xba,0x3a,0x0e,0x42,0x6d,0x10,0x49,0x42,0xb0,0x83,0x0e,0x4d,0x6a,0x6a,0x62,
+  0x08,0xb6,0xd5,0xc4,0x0f,0x4d,0x6a,0x61,0x8e,0x16,0x96,0xb8,0xc0,0x7d,0x61,0x69,
+  0x79,0x45,0x78,0x64,0x6c,0x7a,0x56,0x36,0xf4,0x0a,0x98,0x27,0x28,0x7e,0xdd,0xf8,
+  0x6d,0xd1,0x85,0x9c,0xcb,0x06,0x06,0x86,0x52,0x35,0x48,0xad,0xb1,0x8d,0x34,0x09,
+  0x11,0xb5,0x89,0xce,0x7f,0x20,0x09,0x3d,0x4b,0x3f,0x98,0x6c,0x85,0x0a,0x95,0xca,
+  0xb9,0x7c,0xbd,0xaa,0xb6,0x59,0x28,0x12,0x0f,0xbc,0xe9,0x5d,0x6f,0x4a,0x7c,0x46,
+  0xe8,0xe4,0xec,0x82,0xa6,0x23,0xca,0x50,0x7d,0x34,0x34,0xa5,0xfa,0x40,0x08,0x71,
+  0x20,0x7a,0x68,0xe9,0xf2,0x15,0x85,0xc5,0xa5,0xc7,0xc2,0xa3,0xc1,0xff,0xad,0xb8,
+  0x45,0xbf,0x4e,0xa5,0x68,0xba,0xb2,0x6f,0xff,0x4f,0xb4,0x6a,0x52,0x22,0x92,0xc9,
+  0xfe,0x72,0xda,0x54,0xb2,0xb1,0x89,0x59,0x59,0xc5,0x6d,0x6e,0x0c,0xe2,0x6f,0x41,
+  0x51,0x79,0x6b,0x5b,0x87,0xe2,0x0f,0xff,0xfd,0x19,0x4a,0x3a,0x91,0x6e,0x6c,0x62,
+  0xa2,0x89,0x6f,0xf3,0x63,0x57,0xc1,0x3a,0x4a,0x75,0xc3,0x2b,0xc5,0xc6,0x96,0x5d,
+  0x54,0x5c,0x02,0x55,0x4b,0x49,0x3b,0x55,0x52,0x7a,0xe3,0x49,0x7b,0x17,0xcc,0xc4,
+  0xfe,0x22,0x4d,0xe4,0x04,0x6e,0x6f,0x7f,0xff,0x80,0xa4,0xa7,0xa7,0xad,0x83,0x57,
+  0x55,0x5d,0xdb,0xc9,0xe3,0x6d,0xdb,0xf6,0x6f,0x1d,0xb8,0x66,0x65,0xb6,0x92,0xf7,
+  0x8d,0xe1,0x06,0x94,0xb7,0x14,0x6d,0x1a,0xe8,0xf9,0x1a,0x9a,0x34,0x07,0x38,0x75,
+  0x64,0xf1,0x91,0x7d,0x63,0x98,0x28,0xfd,0xc9,0xae,0x5f,0x82,0x53,0x66,0x1b,0x24,
+  0xb0,0x0e,0x00,0xa8,0xea,0x36,0x72,0xf3,0x06,0x0c,0x55,0x33,0x9a,0x6d,0xbd,0xff,
+  0x31,0x5d,0x1d,0x34,0x0d,0xf1,0x17,0xfd,0x5f,0x03,0xa7,0xef,0x68,0xce,0xec,0xef,
+  0x6f,0x8f,0xd5,0xc6,0x8d,0xb9,0xc6,0x19,0xcc,0xb0,0xf1,0x79,0x6c,0x1f,0x28,0x62,
+  0x07,0x8a,0x01,0x5c,0xa6,0x6d,0xce,0x7d,0xef,0x9d,0x7f,0xbc,0x3f,0x46,0x6d,0xe6,
+  0xa6,0x1c,0x0a,0x3a,0xc0,0x8c,0x61,0x90,0xd0,0x36,0x88,0x51,0x40,0x70,0x2e,0x70,
+  0x02,0x1b,0xf2,0xbf,0x89,0xc1,0x2a,0x00,0x57,0x08,0xe3,0x22,0x61,0x99,0x4c,0x04,
+  0xd6,0x00,0x69,0x1c,0x79,0x02,0x87,0x80,0x6f,0x04,0x01,0x27,0x3b,0x48,0x0c,0xbe,
+  0xa7,0x7d,0x80,0x90,0xb2,0xa1,0x1f,0x1a,0x20,0x90,0x0a,0x09,0x92,0xaa,0x27,0x15,
+  0x05,0x40,0x49,0x96,0x22,0x83,0x35,0xec,0x02,0xb1,0x38,0xeb,0x00,0xac,0x1a,0xf0,
+  0x40,0x88,0x00,0x3a,0x5c,0x54,0x00,0x33,0x5c,0x25,0x38,0x0b,0x92,0xac,0x00,0x21,
+  0x5a,0x92,0x32,0x73,0x24,0x58,0x29,0x0e,0x28,0x00,0xca,0x0b,0x5d,0x43,0x90,0xdc,
+  0x0e,0x8b,0xe6,0x1f,0x11,0x03,0xf2,0x7a,0x46,0xf5,0x2c,0x8f,0x11,0xaf,0x8e,0x13,
+  0x6f,0x48,0x12,0x7e,0x99,0x22,0xfc,0x22,0x45,0xb2,0x3d,0x43,0xb8,0x2d,0x5d,0xb8,
+  0x35,0xa5,0x63,0x4b,0x52,0x73,0xc2,0xf5,0x8e,0xa7,0xff,0xf9,0x6b,0x47,0x9e,0xb7,
+  0x48,0xdd,0x02,0xe6,0x7b,0xef,0x1f,0x96,0x2c,0x5d,0xf1,0xc5,0x57,0x5f,0xff,0xf0,
+  0xa3,0xcf,0xd1,0x08,0x2e,0xe0,0xe9,0xf5,0xbc,0xc2,0x9b,0x77,0x2a,0xeb,0x1b,0x9b,
+  0x5b,0xdb,0x3a,0x79,0xc4,0x05,0x86,0xf1,0x47,0x28,0x02,0x08,0x16,0xf1,0xf8,0xdd,
+  0x8f,0x5b,0xbb,0xea,0x1a,0x9a,0x2b,0x1f,0xd4,0xde,0xa8,0xb8,0x5f,0x50,0x54,0x7a,
+  0xee,0xe2,0xe5,0x8c,0x53,0xa7,0x13,0x8f,0x9f,0x3c,0x16,0x16,0x1d,0x18,0x14,0xba,
+  0xe7,0x47,0xfc,0x1a,0xc2,0xa6,0xcd,0xdb,0x3e,0x5e,0xbf,0x71,0xd5,0x9a,0x4f,0x16,
+  0x2f,0x5d,0xb1,0x60,0xe1,0x62,0x67,0x57,0x77,0x7b,0x07,0x17,0x96,0x8d,0xbd,0xa5,
+  0xa5,0x35,0x41,0xe1,0x59,0xd3,0xa6,0x7d,0x38,0xed,0x03,0xfc,0x76,0x12,0x79,0x53,
+  0x69,0x92,0x8d,0xad,0xed,0xb5,0xbc,0x3c,0x6e,0x6c,0xd2,0xc9,0xd4,0x4c,0x70,0xa6,
+  0x5a,0x5a,0xdb,0x7b,0x7a,0x47,0x9d,0xc3,0x00,0x74,0x02,0x33,0x38,0xce,0xfa,0x06,
+  0x06,0x74,0x41,0x97,0x34,0x62,0x20,0x8d,0x00,0xe8,0x42,0x9c,0xe6,0x1b,0x19,0x9b,
+  0x84,0x84,0x1e,0x39,0x7d,0xf6,0x3c,0x37,0x36,0x39,0xe7,0xf2,0xd5,0xea,0x9a,0x46,
+  0x40,0xd8,0xd1,0xfc,0x5f,0xdc,0x57,0xaa,0xb7,0xd7,0xce,0xde,0x41,0x0f,0x24,0x50,
+  0x32,0xd0,0xd7,0x35,0x30,0x92,0x17,0x04,0x49,0x6b,0x6b,0x56,0x56,0xf6,0x99,0xac,
+  0xec,0xec,0x9f,0x7c,0xfc,0x7c,0x0e,0x06,0x04,0x06,0x1d,0x8e,0x88,0x8a,0x4d,0x3f,
+  0x75,0x26,0x37,0xaf,0xf4,0x5e,0x65,0x4d,0x7b,0x47,0x27,0xd9,0xf6,0xa7,0xff,0xcf,
+  0x3c,0x80,0x20,0x37,0xd3,0xf0,0x16,0xeb,0xb3,0xfe,0xe7,0x30,0x5b,0x68,0x6e,0xe3,
+  0x81,0xb5,0xf3,0x8b,0xf0,0xd5,0xb0,0xcc,0xac,0xec,0x19,0x33,0x66,0x92,0xaa,0x81,
+  0x56,0x86,0x44,0x31,0x43,0xd0,0x93,0xa8,0x67,0x20,0xb7,0x43,0x64,0x64,0xf4,0xe9,
+  0x33,0x17,0x62,0xe2,0x70,0xca,0x51,0x5d,0xd3,0x80,0x9b,0x2c,0x8d,0xbe,0x9b,0x47,
+  0x7b,0x67,0xa7,0xbb,0xc7,0x22,0x2a,0xc1,0xc0,0xd0,0x58,0x2a,0x47,0x1e,0x0e,0x8f,
+  0xc8,0xcc,0x32,0x2c,0xa9,0xef,0x3a,0x6f,0x7e,0xd9,0x8d,0xdb,0x11,0xdc,0xf8,0xf4,
+  0x53,0xd9,0xb7,0xee,0x54,0xc2,0x00,0x08,0xd5,0xff,0x3f,0x58,0x7c,0x58,0x50,0x58,
+  0x64,0x6e,0x6e,0x8e,0xa6,0xd0,0x1f,0x56,0xf7,0x91,0xea,0xfd,0x91,0x24,0x74,0x2d,
+  0xbf,0x80,0xc0,0xb3,0xe7,0x2f,0x44,0xc7,0x24,0x5c,0xc4,0x3e,0x53,0x47,0xf0,0x57,
+  0xc1,0x56,0x12,0x12,0x8f,0xc5,0x4b,0x5f,0x31,0x9a,0xac,0x39,0xe4,0xa1,0x9e,0x4c,
+  0x49,0x8f,0xc5,0x9e,0x85,0xc5,0x25,0xe1,0x11,0x5c,0xf0,0x7f,0x71,0xfd,0x9e,0x82,
+  0xaf,0xf9,0x10,0x0a,0x08,0x0c,0x31,0x34,0x32,0x92,0x57,0x50,0xda,0x4c,0x06,0xb8,
+  0xb9,0x8d,0x9e,0x9e,0x01,0x90,0xa9,0xa9,0x59,0x61,0x69,0x09,0xcc,0x81,0xa5,0xf8,
+  0xfb,0xa4,0xa3,0xa7,0x0f,0xdf,0x70,0xa7,0x0b,0xe9,0x47,0xbb,0x89,0xf4,0xc7,0xe8,
+  0xf4,0x99,0x9f,0x27,0x4e,0x9a,0x0c,0x0a,0xe8,0xe2,0x63,0xa3,0xa1,0x4b,0x8f,0x92,
+  0x35,0xcb,0x06,0x1a,0x25,0x22,0x3a,0x36,0x35,0xed,0x54,0x31,0xe0,0x6f,0x5b,0xd7,
+  0xd3,0x67,0xfd,0x7f,0xc5,0x4c,0x4c,0x3e,0x7f,0x7e,0xfe,0x9f,0xfe,0xa7,0xcf,0x9f,
+  0x09,0x45,0x92,0xc7,0xad,0xed,0xf7,0x2b,0x1f,0xdc,0xb9,0xf7,0xa0,0xb2,0xfa,0xe1,
+  0x87,0xd3,0xa7,0x53,0xc5,0xc8,0xb3,0x2d,0x83,0xe1,0x1a,0xca,0x0d,0xf8,0x7a,0xa3,
+  0xeb,0xe9,0x8d,0x0c,0x01,0xc4,0x87,0xc6,0x01,0x52,0x59,0x2d,0x7d,0x53,0x64,0x36,
+  0x34,0x32,0x98,0xf0,0xe1,0xac,0x4d,0x3f,0x03,0x52,0x38,0x70,0x10,0x65,0xac,0x7d,
+  0x5a,0x34,0x3e,0xf0,0x04,0x60,0xd5,0x63,0x7d,0xe9,0x14,0x24,0x06,0xec,0x70,0x08,
+  0x12,0xcf,0xf9,0xb6,0x6c,0x8c,0x06,0xfa,0xbf,0x86,0xae,0xbb,0x1d,0x70,0xed,0x10,
+  0xdf,0x74,0xa1,0x0f,0xae,0xb6,0xfa,0xa7,0xfa,0x94,0xd5,0xe1,0x36,0x81,0x02,0x47,
+  0x0e,0xc0,0x13,0x84,0x42,0xfb,0x83,0xad,0xef,0x2b,0x1b,0xbf,0xf3,0xee,0x18,0x8b,
+  0xe5,0x61,0x6c,0x00,0x23,0x8e,0xc8,0x89,0x23,0x76,0xe4,0x88,0x41,0x38,0x20,0x11,
+  0x90,0xa3,0x8c,0xd8,0xaf,0x46,0xd8,0x52,0x12,0x03,0x7e,0x0d,0x4b,0x0e,0x1d,0xa5,
+  0x21,0xe8,0x43,0x23,0x20,0x19,0x71,0x2d,0x48,0xc8,0xe6,0x08,0xd9,0x44,0x3e,0x89,
+  0x43,0x44,0xe4,0x20,0x0d,0x45,0x34,0xc9,0x96,0x1d,0xa2,0x18,0x4a,0x23,0x6c,0xd4,
+  0x47,0x7a,0xd4,0x91,0x30,0xd3,0x43,0x32,0x99,0x58,0x10,0x64,0x3a,0x22,0x1b,0x03,
+  0x49,0x7a,0x0a,0x41,0x52,0x01,0x95,0x43,0x18,0xc4,0xb8,0x6e,0x59,0x5a,0x3b,0x21,
+  0x91,0x29,0xb0,0xe7,0x08,0x01,0xb5,0xd9,0x1c,0xea,0xea,0x0a,0x50,0x32,0x47,0xe0,
+  0x12,0x0a,0xa2,0x84,0xf3,0x8e,0x88,0xd0,0xe7,0x3d,0x26,0xf2,0x08,0x17,0x2d,0x8e,
+  0x14,0x2f,0x8f,0x96,0xac,0x8c,0x15,0x7e,0x92,0x24,0xfe,0xf4,0x84,0x64,0x63,0x4a,
+  0xef,0xd7,0x19,0xbd,0xdb,0x32,0x25,0x3b,0xb2,0x24,0xbb,0x4e,0x75,0x79,0x67,0xb4,
+  0x7f,0x77,0xbc,0xa9,0xac,0x86,0xf9,0xdb,0x6e,0xfb,0xfc,0x86,0x9e,0xfc,0x72,0x30,
+  0xbf,0xb0,0x18,0x86,0x5f,0xaf,0x8f,0xd7,0x7f,0xb3,0xd3,0xdb,0x8f,0x73,0x34,0x21,
+  0x29,0xf5,0xfc,0xc5,0x2b,0x05,0x25,0x15,0x30,0x99,0x6c,0x6e,0x69,0x03,0x17,0x18,
+  0x3c,0x5f,0xe8,0xe1,0x30,0x04,0x09,0x84,0x42,0xa0,0x0e,0x1e,0xd3,0xd2,0xd6,0x01,
+  0x5e,0x70,0x65,0x75,0x6d,0x05,0x7e,0xc2,0xbb,0x0c,0x70,0x0d,0x26,0xf3,0xc9,0x27,
+  0xd2,0xc2,0xa3,0x63,0x83,0x43,0x8e,0x1c,0xf0,0xf1,0xdd,0xb9,0x6b,0xcf,0xd6,0x6d,
+  0x3b,0x36,0x7e,0xbe,0xd9,0x6b,0xdd,0x86,0x55,0xab,0xbd,0x00,0xdf,0x17,0xb8,0x2f,
+  0x72,0x9b,0xe7,0x6e,0xcf,0x76,0xb6,0xb1,0x63,0xe3,0x1d,0xe9,0xb9,0x96,0xb3,0x66,
+  0xcd,0x06,0x20,0x9e,0x3e,0x7d,0x3a,0xb8,0xc3,0x00,0x79,0xbf,0x5c,0xbf,0x9e,0x98,
+  0x9c,0x72,0x32,0x2d,0x2b,0xb7,0xa8,0xe2,0x51,0x73,0x9b,0x58,0x22,0xc1,0xb5,0xb0,
+  0x2f,0x5f,0x90,0x4f,0xbf,0x81,0xef,0x31,0x88,0x2b,0x63,0x5f,0xe2,0xe2,0x58,0xf8,
+  0x2b,0x2d,0x2f,0x27,0xee,0xb3,0x39,0x3e,0x4a,0x36,0x31,0x85,0xd0,0xd4,0xd4,0xdc,
+  0xc4,0x0c,0xf7,0xdd,0x82,0x04,0x64,0x60,0x9c,0xe4,0x03,0x05,0x06,0x05,0xe6,0x5c,
+  0xba,0xcc,0x8d,0x4b,0xca,0xb9,0x74,0xad,0xea,0x61,0x3d,0xaf,0x5b,0x40,0xa7,0xe5,
+  0x03,0x64,0x70,0xa2,0x40,0x49,0x47,0x57,0x88,0xc3,0x60,0xe8,0xe1,0xe1,0x69,0x62,
+  0x6a,0x6e,0x6a,0x86,0xa7,0x1b,0x13,0x81,0x44,0x26,0x0a,0x04,0xb1,0x50,0xd0,0x42,
+  0x0f,0x8f,0xa2,0xd2,0xe2,0x13,0x29,0x27,0x0f,0xfa,0x06,0xf8,0xfa,0x07,0x07,0x84,
+  0x84,0x45,0x44,0xc7,0xa5,0x67,0x9e,0xbe,0x72,0x35,0xff,0xd6,0x9d,0xfb,0x8d,0x8f,
+  0x5a,0xf9,0xdd,0x4c,0x4f,0xcf,0xd3,0xe7,0xfd,0xc3,0x50,0xf8,0xe5,0xa8,0x1e,0xf7,
+  0xf0,0x51,0x45,0x36,0xb6,0x0c,0x02,0x84,0xf5,0xf4,0xf6,0xc2,0xdc,0xa7,0xf1,0xd1,
+  0xe3,0xdb,0x77,0x2b,0xaf,0x5e,0x2b,0x00,0x1f,0xb3,0xb0,0xa8,0xd8,0xcd,0x6d,0x3e,
+  0xd5,0x04,0xd4,0x02,0x32,0x91,0xa9,0x47,0x6b,0x4a,0x09,0x74,0x0e,0x0a,0x0e,0x39,
+  0x77,0xe1,0x12,0xb8,0x44,0x17,0x2f,0x5f,0xab,0xac,0x06,0xf8,0x10,0xe1,0x0e,0xc6,
+  0x2f,0xb0,0x9a,0x40,0x83,0x44,0x19,0x79,0x12,0x4a,0x59,0xb9,0x6a,0x35,0xda,0xf0,
+  0x35,0x51,0xbf,0x4a,0xa0,0x89,0xb3,0x8b,0x6b,0xc5,0xad,0x3b,0x91,0xdc,0x04,0x98,
+  0xb9,0x95,0x55,0xdc,0x47,0xff,0xeb,0xe9,0x33,0xda,0x64,0x68,0x55,0xf2,0x60,0x8e,
+  0x96,0x45,0xed,0x4c,0x92,0xd2,0xa3,0xb2,0x24,0x99,0x72,0x50,0xdd,0xb0,0x45,0x46,
+  0x1c,0x1d,0x24,0x34,0xf2,0xdc,0xb2,0xf2,0xf2,0x0f,0x3e,0x98,0x26,0x6f,0xfd,0xdf,
+  0xa5,0xf6,0xaf,0x92,0xcf,0xc1,0x43,0xe0,0x5f,0x47,0x71,0x13,0x2f,0x5e,0xb9,0x5e,
+  0xf9,0xa0,0xa6,0x5b,0x20,0xc4,0x2f,0x14,0x0f,0xca,0x4a,0x7f,0x31,0x20,0x87,0x63,
+  0x88,0xf4,0x3d,0x7b,0xb6,0x7a,0xcd,0xda,0x5f,0x95,0x49,0xcd,0x3b,0xdf,0x7d,0x41,
+  0xd9,0x8d,0x8a,0xa8,0x98,0x78,0xc0,0xdf,0x1b,0x15,0xf7,0xda,0x3a,0x3a,0x7a,0xfb,
+  0xfa,0x68,0x87,0x94,0x57,0x53,0x6a,0x28,0x12,0x81,0xbe,0x65,0x61,0x31,0x41,0x5e,
+  0x41,0x79,0x1b,0x99,0x98,0xd1,0x8a,0x43,0x30,0xe9,0x7a,0x5e,0x7e,0x72,0x4a,0xda,
+  0xf1,0x94,0xf4,0x82,0xc2,0xd2,0xfa,0xc6,0x16,0x49,0x4f,0x2f,0xfd,0xac,0x30,0xb9,
+  0x5e,0x06,0x87,0xeb,0x3c,0xa2,0x0a,0xc3,0x93,0xb4,0x68,0x4c,0xbe,0x1c,0x1c,0xd1,
+  0x28,0xf2,0x0e,0x7c,0xe5,0xea,0xd5,0x0f,0xa7,0xcf,0x84,0xae,0x47,0x4b,0x97,0xea,
+  0x60,0x26,0xed,0x84,0x96,0x56,0x56,0xb9,0x79,0xf9,0xdc,0xd8,0xc4,0x94,0xb4,0xec,
+  0xdc,0xa2,0xd2,0x96,0x27,0xed,0xa0,0x09,0xfd,0x74,0xe3,0x50,0xb3,0x82,0xc8,0x61,
+  0x5a,0xc9,0x0a,0x7d,0xf1,0x7a,0xb9,0xb4,0xe7,0x48,0x2f,0xcc,0x97,0xf8,0xd5,0x51,
+  0x68,0x7e,0x0c,0x88,0x92,0x60,0xb1,0xde,0x3e,0x40,0x5e,0x31,0x4c,0x60,0x1a,0x9a,
+  0x9a,0x61,0xe2,0x07,0x5e,0x43,0x4d,0x5d,0xc3,0xde,0x7d,0xfb,0x68,0xb7,0x84,0x4b,
+  0x03,0x5c,0xf5,0x3f,0xd9,0x0d,0x68,0xbd,0x4c,0x65,0x95,0x35,0x36,0x33,0x31,0xc6,
+  0x85,0x2b,0xa6,0x1f,0x38,0xaf,0x77,0x38,0xd4,0x0c,0xf0,0xe1,0x18,0x2c,0x70,0x0b,
+  0x15,0xb2,0xf6,0x3e,0x54,0x36,0xb1,0xc6,0xdd,0x7e,0x56,0x84,0xb2,0x43,0x18,0x76,
+  0x30,0x80,0x88,0x70,0xf6,0x4e,0x29,0xfe,0x6a,0x4c,0x74,0x9b,0xb8,0x24,0xd0,0x64,
+  0x81,0xcf,0x58,0xe2,0x0e,0x8f,0xd3,0x34,0x9d,0xbc,0x36,0xc2,0x72,0x6f,0x8d,0x23,
+  0x79,0x71,0xd5,0x9e,0xc3,0x38,0x04,0x33,0x6a,0x13,0xec,0xff,0xfb,0xbf,0xde,0x33,
+  0x64,0x7f,0xeb,0x18,0xc8,0x87,0x4c,0xc7,0x10,0xc6,0x31,0x18,0x97,0x18,0xd9,0x23,
+  0x90,0x0d,0x11,0xe4,0x3b,0x70,0x90,0x1c,0xe9,0xa1,0x10,0x24,0x27,0x0e,0x80,0x9a,
+  0xc0,0x09,0x4f,0x41,0x51,0x4e,0xa1,0x8c,0xa3,0x8c,0x99,0xcd,0xa1,0xfc,0x02,0xa7,
+  0x60,0x40,0x3a,0xc6,0x39,0x18,0x40,0x13,0x43,0x36,0x9e,0x82,0x04,0x9c,0x94,0x19,
+  0xf2,0x9d,0x48,0xc4,0x29,0x78,0x28,0xe9,0x84,0x0c,0x78,0x2e,0xa0,0x2d,0x9c,0xe5,
+  0x44,0xf2,0x51,0x32,0x82,0x2c,0x8a,0x72,0xe4,0x50,0x0d,0x45,0xf4,0x14,0x59,0x12,
+  0x5c,0x63,0xcc,0x94,0x9d,0x2b,0x70,0x0e,0x15,0x92,0xa4,0x48,0x06,0xb8,0x42,0x72,
+  0x0a,0x26,0xed,0x11,0x70,0x45,0x58,0xdf,0x10,0x91,0x4b,0xa8,0xd0,0x31,0x44,0xe0,
+  0x18,0x8a,0x49,0xe7,0x50,0xd1,0xbc,0x23,0x8c,0x7b,0x98,0x08,0xc8,0x23,0x42,0xb8,
+  0x94,0xdb,0x0b,0x3e,0xef,0xaa,0x38,0xf1,0xba,0xc4,0x9e,0xcf,0x4e,0xf6,0x6d,0x4c,
+  0xe9,0xdb,0x92,0xd9,0xb7,0xe3,0x74,0xef,0x37,0xd9,0x3d,0xbb,0x7f,0x16,0xef,0x3e,
+  0xc3,0xec,0x3e,0xd3,0xed,0x9d,0xd9,0xee,0x7f,0xa1,0xad,0xe7,0xf9,0xdf,0xfa,0xb5,
+  0xdf,0xd7,0xa9,0x7f,0xa0,0xff,0x7b,0xef,0x5d,0xcb,0x56,0xac,0xfa,0x6a,0xd3,0xd6,
+  0xbd,0xfb,0x0f,0x85,0x45,0x72,0x33,0xb3,0xce,0x5d,0xcb,0x2b,0xbc,0x75,0xf7,0x41,
+  0x5d,0x43,0x53,0x6b,0x5b,0x17,0xa0,0x89,0x40,0x28,0xf9,0x5f,0xf6,0xbe,0x03,0xba,
+  0xad,0xe3,0x4a,0xf4,0x9c,0xbf,0xb6,0x9c,0xea,0x6c,0x36,0xbb,0xc9,0xa6,0x6f,0x49,
+  0xbc,0xb1,0x1d,0xa7,0x6c,0x62,0x27,0x9b,0x38,0x2e,0x92,0x2d,0xd9,0x6a,0xee,0x56,
+  0xb3,0x64,0x5b,0xb6,0x7a,0xb1,0x2d,0xc9,0xea,0x14,0x29,0x51,0xec,0x9d,0x94,0x28,
+  0xf6,0xde,0x2b,0x40,0x90,0x00,0x3b,0x89,0xca,0xde,0x7b,0x27,0xd8,0x2b,0x0a,0x09,
+  0x56,0xe0,0x9f,0xf3,0xef,0x9d,0x79,0xef,0xe1,0xa1,0x50,0x96,0x5c,0xe2,0x55,0x7e,
+  0x74,0xae,0xc7,0x77,0x66,0xee,0xdc,0x3e,0xb8,0x6f,0xc0,0x87,0xf7,0xe0,0x0c,0x05,
+  0x35,0x71,0x66,0x76,0x16,0x60,0x72,0x7a,0x7a,0x68,0x04,0xff,0x16,0x0c,0xc7,0x49,
+  0xa8,0x38,0x32,0x65,0x75,0x41,0x91,0x54,0x90,0x93,0x9b,0x98,0x9c,0x1a,0x1a,0x16,
+  0xeb,0x17,0x14,0xec,0xe6,0xe1,0x75,0xf9,0x8a,0xf3,0xe9,0xb3,0x17,0x8e,0x9d,0xf8,
+  0x68,0xff,0xfb,0x87,0xdf,0xda,0xf7,0xee,0x1b,0x3b,0x76,0xbf,0xf4,0xf2,0xab,0x9b,
+  0xb7,0xbe,0xfc,0xdc,0xc6,0xcd,0xeb,0x9f,0xdb,0x44,0xef,0xce,0xfa,0xe3,0xff,0xfc,
+  0xe9,0x89,0x27,0xfe,0x07,0x0a,0xf1,0xfa,0xf5,0x1b,0xa0,0x88,0x27,0x24,0xa7,0x42,
+  0xfd,0x2d,0x91,0x2a,0xdb,0x3a,0x7b,0xc7,0x27,0xa1,0xe8,0x6b,0xb5,0xfa,0x39,0x1d,
+  0xc0,0xdc,0x3c,0xc0,0xdc,0x1c,0x3e,0x18,0x0a,0x76,0x34,0x1c,0x8d,0x1b,0x9a,0x9a,
+  0xe0,0xb3,0x97,0xde,0x53,0x4d,0xe1,0x67,0x3f,0xfb,0x39,0xbf,0xfb,0x8b,0x5f,0xfc,
+  0x82,0x45,0x1e,0x76,0xba,0x76,0xad,0xa0,0xb8,0x24,0x2c,0x22,0x2e,0x27,0x37,0xbf,
+  0xbe,0xb1,0x0d,0x2e,0x2a,0xc0,0x16,0x60,0x05,0xff,0xe9,0xf5,0xf3,0x3a,0x3d,0x32,
+  0x07,0xd3,0xe0,0xe4,0x0b,0x83,0xf3,0x86,0x05,0xf8,0x2c,0xe5,0xb3,0xb2,0x05,0xe0,
+  0xb9,0x77,0xdf,0xdb,0x32,0xb9,0x3c,0x29,0x39,0xc5,0xc5,0xd5,0xd3,0xd5,0xc3,0xd7,
+  0xdb,0xff,0x46,0x70,0x48,0x44,0x5c,0x42,0x7a,0xae,0xb8,0x58,0xa6,0xac,0x6a,0x6d,
+  0xef,0x1e,0x1c,0x1a,0x02,0x47,0x69,0xb5,0x3a,0xf8,0xa0,0xa0,0xbf,0xc7,0xfc,0xc4,
+  0xfa,0xbb,0x0a,0xd7,0x18,0x2b,0x46,0xa8,0xda,0x50,0x79,0x61,0xed,0xe0,0xd0,0x30,
+  0xf0,0x51,0x56,0x54,0xe7,0x8a,0x8b,0x4a,0xcb,0x15,0x95,0xd5,0x55,0x7b,0xf6,0xee,
+  0x03,0xd1,0x3f,0xff,0xf9,0x7f,0x3d,0xf4,0x10,0xb5,0x0e,0x90,0x87,0xe1,0x3a,0x84,
+  0xed,0x9a,0xc1,0xc5,0xcd,0x03,0x4e,0xbe,0x11,0x91,0x71,0xc2,0x5c,0x09,0x7c,0x34,
+  0x8d,0x8c,0x8e,0xc1,0xa9,0x1c,0x8e,0xd2,0x3a,0xb0,0x9a,0xf8,0x90,0x02,0x78,0x00,
+  0x3c,0x3c,0x39,0x39,0xb3,0xef,0x9d,0x77,0x6f,0x6f,0xf2,0x6d,0x60,0xfd,0x86,0x0d,
+  0x95,0xd5,0xb5,0x21,0x11,0x31,0x49,0xc9,0x99,0x60,0x7b,0x57,0xef,0xc0,0xd4,0xb4,
+  0x86,0x08,0x9a,0xc7,0xf0,0x11,0x71,0x24,0x88,0x73,0x8c,0x9f,0x49,0x34,0xe9,0x2c,
+  0x13,0x05,0x42,0x40,0x70,0x3d,0x4b,0x8c,0x94,0xcc,0x5a,0x56,0x55,0xd2,0xc5,0x29,
+  0x8d,0x16,0xa2,0x84,0x39,0xf0,0xfb,0xc7,0x9f,0x00,0x05,0xc0,0x09,0x9f,0x5a,0x79,
+  0xbb,0xf0,0x5f,0xff,0xf5,0x0b,0x27,0xa7,0xab,0x25,0x25,0x65,0x21,0xa1,0x31,0xa2,
+  0xbc,0x7c,0xb8,0xc8,0x1c,0x1a,0x19,0xd7,0xd0,0x9c,0x61,0x95,0x67,0x70,0xa2,0x36,
+  0x24,0xcd,0x81,0x83,0x87,0xee,0x90,0xf9,0xa6,0x4d,0x2f,0x54,0x56,0x55,0x87,0x86,
+  0x47,0xa5,0xa6,0x0b,0x14,0xaa,0xea,0x6e,0x70,0xd7,0xcc,0xac,0x56,0xcf,0x59,0x8a,
+  0x11,0xd1,0xea,0x19,0x04,0x8a,0x7e,0x42,0x62,0xd2,0xa3,0xbf,0xfc,0xe5,0x6d,0x18,
+  0x3e,0xfc,0xf0,0x23,0xf9,0x45,0xc5,0x49,0x29,0xe9,0xb1,0xf1,0x29,0x25,0x65,0xf2,
+  0xd6,0xf6,0xde,0xc9,0xa9,0xa9,0x59,0x8c,0xf5,0x3c,0x4f,0x5b,0x46,0x55,0x9e,0xa0,
+  0x79,0x9a,0x0c,0xe6,0xa0,0x70,0x31,0x62,0xac,0x9b,0x83,0x28,0x32,0x09,0x33,0x3f,
+  0x3f,0x0b,0x7b,0x66,0x6e,0x5e,0x2e,0x97,0xff,0xe9,0x4f,0x7f,0xb2,0xdd,0x6e,0x14,
+  0x9e,0xf8,0xc3,0x1f,0x8b,0x4b,0x4a,0x23,0x63,0x12,0x12,0x93,0x33,0x8a,0x4a,0x65,
+  0xf0,0xe9,0x31,0x3e,0x39,0xc5,0x8a,0xe6,0x84,0xb2,0xdb,0xcd,0x1c,0x7a,0x73,0x4a,
+  0xe8,0x99,0xfc,0x9c,0xa3,0x1b,0x9f,0x9b,0xd5,0x90,0x1d,0x0b,0x18,0xfc,0x1f,0x3e,
+  0x17,0x20,0x97,0x27,0x26,0xa7,0xd4,0xc3,0x63,0x9d,0xdd,0xbd,0x8d,0xcd,0x6d,0xa5,
+  0xe5,0xca,0x5c,0x49,0x41,0x5d,0x43,0x53,0x4a,0x5a,0xfa,0xe3,0x4c,0x4a,0x60,0x10,
+  0x1f,0x7e,0xf8,0x73,0x4e,0x0c,0xf8,0x87,0xdb,0xff,0x91,0x5f,0xff,0xf1,0x68,0xc6,
+  0x46,0xbf,0xd9,0x0d,0x50,0x26,0x7c,0x66,0x9f,0xf7,0xd1,0xfe,0xf9,0x72,0xf3,0xb7,
+  0x7e,0xfc,0xbb,0xfb,0xef,0xff,0xda,0x63,0x7b,0x22,0x9e,0xf3,0x9d,0x85,0x3a,0xf8,
+  0x9c,0xb7,0xf6,0x8f,0x1f,0x33,0xf7,0x5f,0xad,0xbb,0xef,0x81,0x07,0x1e,0xf8,0xc6,
+  0xba,0x75,0x5f,0xbb,0x1f,0xd0,0x7f,0x58,0x77,0xff,0x3f,0xac,0x7b,0xe0,0xab,0xdf,
+  0xfa,0xa7,0x7f,0xff,0xfd,0x6f,0x0f,0x64,0xac,0xf7,0xd6,0x3e,0xe7,0x03,0xa5,0x4d,
+  0xf3,0xfd,0xdf,0xbc,0x06,0x53,0xff,0xf6,0xd4,0xe1,0x0d,0x1e,0x13,0xb0,0x16,0x78,
+  0xc2,0xf8,0x46,0xdf,0xd9,0xe7,0x7d,0x75,0xeb,0x41,0x84,0xbf,0x6e,0x83,0x8f,0xe6,
+  0x39,0x5f,0x1d,0x54,0xa8,0xe7,0x7d,0xb5,0x2c,0xe8,0x80,0xec,0x79,0x9f,0xd9,0xe7,
+  0x7c,0x74,0xd8,0x7a,0x43,0xab,0xd9,0xe0,0xcd,0xe0,0x38,0x48,0xc8,0x36,0x78,0xcf,
+  0x6c,0xf4,0xd3,0x3f,0xe3,0x0d,0x53,0x9a,0x8d,0xc0,0x0d,0x75,0x83,0x25,0xb8,0x70,
+  0x83,0x17,0xb3,0x9c,0xea,0x00,0xcb,0x9f,0xf3,0xd6,0xd0,0xd9,0xe7,0x90,0x09,0xb4,
+  0x33,0xcf,0xa3,0x81,0xf8,0x1b,0x5b,0x42,0x8c,0x2d,0x21,0x00,0x1b,0xb5,0xd4,0xcc,
+  0xf5,0xde,0xb3,0xcf,0xfb,0x41,0xd5,0xd6,0x42,0xbb,0x81,0x5b,0x0b,0x3c,0xfd,0xf0,
+  0xc7,0xb9,0x4f,0x33,0xb7,0x4b,0xa1,0x4f,0x80,0x72,0x03,0x0c,0x7a,0x69,0x40,0x87,
+  0xe7,0xfd,0x50,0x1f,0xb2,0x56,0x0b,0x3e,0x44,0xdd,0xfc,0x34,0x1b,0xfd,0xb5,0xcf,
+  0xf9,0x81,0xb1,0xf4,0x2f,0xbc,0x50,0x76,0x75,0xdb,0x82,0xe1,0xcc,0x3b,0xf7,0x7a,
+  0x98,0x66,0x47,0x24,0x54,0x5e,0xfd,0xfe,0xf8,0xf9,0x83,0x49,0x86,0x13,0xe9,0x86,
+  0x0f,0x33,0x0d,0xe7,0x84,0x86,0xcb,0x22,0x83,0x63,0x9e,0xc1,0x39,0x4f,0x77,0x55,
+  0x34,0xe3,0x24,0x9c,0xb8,0x2a,0x18,0x55,0xf4,0xe8,0xbf,0xf4,0x7a,0xfa,0x29,0x00,
+  0x0e,0x56,0x3b,0x77,0xbd,0xb5,0xef,0xed,0x77,0x3f,0x3e,0x7b,0xd1,0xc5,0x33,0x20,
+  0x3a,0x2e,0x19,0x3e,0xb7,0xe5,0xaa,0x9a,0xa6,0xd6,0xf6,0x7e,0x28,0x03,0xa3,0xe3,
+  0x53,0xd3,0xd3,0xb0,0x05,0x70,0x5f,0xe8,0xf0,0x14,0x0c,0xf9,0x3f,0x3e,0x09,0x25,
+  0x78,0xa2,0x6f,0x60,0xa8,0xb5,0xbd,0xa3,0xa1,0xb1,0x59,0x59,0x51,0x07,0x67,0x34,
+  0x51,0x5e,0x51,0x52,0x4a,0x56,0x64,0x4c,0xfc,0xcd,0xe0,0x08,0x4f,0x2f,0x7f,0x67,
+  0x17,0x8f,0x73,0x17,0x1d,0x3e,0x3a,0x7d,0xee,0xc8,0xb1,0x0f,0xdf,0x79,0xe7,0xc0,
+  0xae,0x3d,0xef,0xbe,0xf6,0xfa,0xae,0xed,0x2f,0xbd,0x01,0x55,0x78,0xd3,0x0b,0x9b,
+  0xc9,0x3d,0xd2,0x1b,0x9e,0x7c,0xea,0x99,0x3f,0x3f,0xf9,0x97,0xe7,0x37,0x6e,0x12,
+  0xe5,0x8a,0x93,0xd3,0x32,0xe3,0x13,0x53,0x24,0x85,0x65,0xd5,0xb5,0x4d,0xed,0x9d,
+  0x7d,0xbd,0x7d,0x83,0x3d,0x83,0xe3,0xfd,0x83,0xea,0x81,0xc1,0x61,0x28,0x9a,0xbd,
+  0xfd,0x03,0xfd,0x03,0x83,0x03,0xa0,0xcf,0xc8,0x68,0x67,0x77,0x37,0x7c,0xf6,0x3e,
+  0xf6,0xd8,0x63,0xbf,0x64,0xff,0x3d,0x46,0xfe,0xfd,0xea,0x57,0xbf,0xa6,0xdd,0x47,
+  0x1e,0x79,0x84,0x1b,0xbf,0x70,0xf1,0x12,0x9c,0xf1,0xa1,0xfe,0xa6,0x67,0x66,0xcb,
+  0xe4,0xd5,0x4d,0x2d,0x70,0x99,0x0c,0xac,0xd4,0x5d,0xfd,0xf8,0x74,0xcd,0xbe,0xfe,
+  0x21,0xb8,0x90,0xe8,0x1e,0x18,0x05,0xce,0x7d,0xfd,0x6a,0x28,0xf9,0xef,0x1f,0x7c,
+  0xff,0x97,0xf6,0xfe,0xd1,0xbf,0x5c,0xd3,0x7f,0xbf,0xfa,0xd5,0xaf,0x8e,0x9f,0xfc,
+  0xa0,0xae,0xbe,0x2e,0x36,0x29,0xd5,0xc3,0xdb,0xcf,0xcd,0xfb,0x86,0x6f,0xc0,0xcd,
+  0xe0,0x5b,0x11,0xd1,0x71,0x89,0x59,0x82,0x3c,0xb8,0x14,0xaf,0xae,0x6b,0xec,0xe8,
+  0xea,0x05,0x5d,0x27,0xa7,0xe0,0xa3,0x6b,0x6e,0x61,0x11,0x7f,0xd0,0x0c,0x87,0xeb,
+  0x55,0xe6,0x9a,0x9f,0x3d,0xea,0x42,0xcd,0x35,0xae,0xc2,0x69,0x65,0x69,0x79,0xc5,
+  0xb0,0xb8,0x00,0x9f,0x36,0x70,0xb1,0x03,0xd7,0x36,0xa0,0x61,0x55,0x4d,0x03,0x7c,
+  0x9c,0x66,0x0b,0xf3,0xca,0xa4,0xb2,0xd6,0xb6,0xf6,0xf7,0x0e,0x1c,0xfc,0xed,0x6f,
+  0x7f,0xcb,0x37,0x19,0xfe,0x3d,0xfa,0xa8,0x5d,0x4d,0x7f,0x79,0xf5,0x9a,0x73,0xa9,
+  0xb4,0x3c,0x34,0x2c,0x1a,0x94,0x29,0x93,0x57,0xb5,0xb4,0xb5,0xf5,0xf4,0x81,0xf3,
+  0x86,0x20,0x9a,0x70,0x3c,0x87,0xa8,0xf5,0x0f,0x8e,0x02,0xf4,0x92,0x07,0x7d,0x43,
+  0x75,0x3e,0x7a,0xec,0xb8,0x7d,0x46,0x77,0xf0,0x6f,0xc3,0x86,0x0d,0x70,0x36,0x8f,
+  0x8c,0x8a,0x87,0x4f,0xdd,0xfc,0xa2,0x92,0x5a,0x34,0xbc,0x8f,0x7a,0xb5,0x6f,0x40,
+  0x4d,0x00,0x90,0x61,0x10,0x47,0x9e,0x2b,0x3e,0x4c,0xba,0x2c,0xf4,0x33,0x23,0xd8,
+  0x72,0xf8,0x00,0xd3,0x02,0x3d,0xe8,0xdc,0x4b,0xdb,0x7e,0x80,0xe1,0x5e,0x60,0xd2,
+  0x8f,0xac,0xc0,0xb1,0x2d,0x6d,0xed,0x7f,0x79,0xea,0xe9,0x4f,0xad,0xf6,0x6d,0xfe,
+  0x81,0x93,0xcf,0x5d,0x38,0x5f,0x2a,0x95,0x87,0x86,0xc7,0xa6,0x65,0x64,0x4a,0xe5,
+  0xaa,0xa6,0xd6,0x2e,0x88,0x08,0x6b,0x0b,0x75,0x20,0x55,0x69,0x70,0x50,0x3d,0x3c,
+  0x3d,0xa3,0xf9,0xe8,0xf4,0xe9,0x3b,0x64,0xfe,0xfc,0xf3,0x1b,0x2b,0xab,0xab,0xa3,
+  0xa2,0x13,0x13,0x92,0xd3,0x0a,0x4a,0xca,0x6b,0xeb,0x5b,0x3a,0xbb,0xfb,0xbb,0x7b,
+  0xc1,0x5e,0x64,0x08,0x56,0x53,0x04,0xce,0x74,0xdd,0x83,0xe3,0xa3,0xe3,0xe3,0x99,
+  0xd9,0x82,0xff,0xfe,0xef,0xdf,0xd9,0x55,0x92,0x66,0xfb,0x63,0x8f,0xfd,0x3a,0x27,
+  0x57,0x9c,0x92,0x9a,0x19,0x1d,0x93,0x84,0xaf,0x50,0xa9,0xaa,0x6f,0x6d,0xef,0xea,
+  0xee,0x47,0x55,0x49,0xac,0xd1,0xed,0x9c,0x6f,0xa9,0xcf,0x2d,0x42,0xc0,0x73,0xb8,
+  0xe5,0x08,0x05,0xec,0xe2,0xd6,0x20,0x39,0x53,0x51,0x55,0xf5,0xec,0xb3,0xcf,0x52,
+  0xe9,0xb6,0x2a,0xfd,0xe9,0xcf,0x7f,0x2e,0x2c,0x2e,0x8b,0x8d,0x4f,0x8e,0x8d,0x4b,
+  0xcd,0xcb,0x2f,0xaa,0xa9,0x6b,0x80,0x5d,0x4c,0xb8,0x0d,0x0e,0xa8,0x47,0x7b,0xd8,
+  0x38,0xb2,0xe1,0x56,0x43,0xee,0xd1,0xd9,0xde,0x7e,0x6b,0xb9,0x64,0x84,0xa7,0x55,
+  0xff,0x10,0xc9,0x55,0x35,0xb8,0xa5,0xb7,0x5f,0xdd,0xd6,0xd9,0x0d,0xbb,0xb8,0xba,
+  0xb6,0x51,0x2a,0xab,0xcc,0x93,0x94,0xc0,0xbe,0x2e,0x2a,0x93,0x56,0xd5,0xd4,0x6c,
+  0x7f,0xf9,0x15,0x4e,0x99,0x47,0xd7,0xda,0x1b,0x9f,0xe1,0x1f,0x7c,0xaa,0x80,0xd7,
+  0xff,0xb8,0x71,0xf7,0x26,0xf7,0xfe,0xe7,0x7c,0xf4,0x2f,0x06,0xce,0x6c,0xf2,0xd3,
+  0xbe,0x10,0xa0,0x7d,0xd2,0xa1,0xe5,0x5b,0x3f,0x7d,0x62,0xdd,0xfd,0x5f,0x79,0x6c,
+  0xf7,0xcd,0x17,0x03,0x34,0x70,0x70,0x83,0x41,0xae,0xfe,0x7e,0xfb,0x27,0xbf,0xf9,
+  0xf9,0xd3,0xef,0xff,0xe4,0x2f,0xef,0xff,0xf8,0xc9,0xf7,0x7f,0xf4,0xe4,0xc1,0x7f,
+  0x7e,0xe8,0xc9,0x75,0x0f,0xe0,0x2d,0x58,0xdf,0xf9,0xaf,0xf5,0xcf,0x79,0x8e,0xbc,
+  0xe0,0xaf,0x7d,0x31,0x40,0xfb,0xbd,0x47,0x5f,0x80,0xba,0xfc,0x1f,0xcf,0x1c,0xdb,
+  0xe4,0x3b,0xf1,0x62,0xe0,0x2c,0x14,0xa3,0x17,0x90,0x0f,0x54,0xa5,0xd9,0x17,0xfc,
+  0x67,0x01,0x47,0xf0,0xd7,0xc0,0x14,0x74,0x61,0x1c,0x00,0xbb,0x40,0xe3,0xa7,0x23,
+  0xf4,0x30,0x0e,0x38,0x8e,0x43,0x77,0x13,0xe9,0xc2,0x12,0xe4,0xe3,0x3f,0x03,0x83,
+  0x9b,0x03,0xa1,0xf8,0xce,0xbc,0x18,0xa0,0xc7,0xae,0x1f,0xd1,0x10,0xc7,0xb5,0xb0,
+  0x10,0x88,0x37,0x11,0x1c,0x46,0x36,0xfa,0xe2,0x08,0x28,0x8f,0x83,0x84,0x8c,0xc8,
+  0x02,0x73,0xa0,0xab,0xdf,0xe4,0x87,0xab,0x88,0xdc,0x59,0x34,0x1c,0xc7,0x75,0xa8,
+  0xa4,0xaf,0x6e,0xa3,0xaf,0xfe,0xc5,0x80,0x99,0x17,0x03,0x75,0x30,0x4e,0x96,0x00,
+  0x9f,0x19,0x1c,0x87,0x59,0x50,0x38,0x40,0xf7,0x2c,0xfe,0x5c,0x08,0x2b,0x2c,0x0c,
+  0x6e,0xf2,0xd7,0x3f,0xef,0x0f,0x45,0x19,0x34,0x47,0xf5,0x36,0x07,0x69,0x36,0x05,
+  0x40,0xab,0x63,0x6b,0x2e,0xc0,0x0c,0x9c,0x76,0x01,0x76,0x46,0x68,0xdf,0x8c,0x30,
+  0xbc,0x1d,0x83,0x95,0x17,0xce,0xbc,0x87,0x92,0x0d,0x67,0xb2,0xd9,0xca,0x2b,0x36,
+  0x38,0xe7,0x1b,0xdc,0x0a,0x0d,0x57,0xf3,0xb5,0xee,0xe2,0x69,0x27,0xe1,0x78,0x94,
+  0x7c,0x4a,0xbb,0xf0,0xe5,0x17,0xd3,0x4f,0x01,0x70,0x99,0xed,0xed,0xeb,0xff,0xda,
+  0x1b,0x3b,0x8e,0x1e,0x3b,0x71,0xc5,0xf1,0x9a,0x7f,0x70,0x78,0x4a,0x5a,0x76,0x61,
+  0x49,0x59,0x75,0x0d,0xd4,0x41,0xd8,0x37,0xe3,0x50,0x6d,0xe9,0x5f,0x81,0xe1,0x68,
+  0x06,0x75,0x18,0xea,0x2f,0xb9,0x04,0xd5,0x40,0x69,0x1e,0x1c,0x1a,0x03,0x12,0xd8,
+  0x0e,0x35,0xb5,0x0d,0x52,0x99,0xaa,0xa0,0xa8,0x34,0x4b,0x98,0x97,0x90,0x84,0x0f,
+  0xe8,0x08,0xba,0x19,0xea,0xe5,0xe3,0x7f,0xcd,0xd9,0xfd,0xfc,0x05,0x87,0xd3,0x67,
+  0xce,0x9f,0xf8,0xe0,0xd4,0x81,0x83,0x47,0xdf,0xdd,0x7f,0x70,0xc7,0xce,0xbd,0xaf,
+  0xbf,0xb9,0xeb,0xe5,0x57,0xdf,0xd8,0xba,0xed,0xa5,0x17,0x36,0xbf,0xf4,0xfc,0xc6,
+  0x2d,0x5b,0xb6,0xbe,0x24,0x96,0xe4,0xe3,0x0b,0x49,0xe3,0x92,0xd3,0x33,0x05,0xe2,
+  0x02,0x10,0xae,0x90,0xc9,0x2b,0xa5,0xf2,0x0a,0x99,0xa2,0xaa,0x4c,0x56,0x51,0xae,
+  0x50,0xc9,0x15,0xd5,0xe5,0x8a,0x8a,0x52,0xb9,0xaa,0xa2,0xba,0xae,0xbd,0xab,0xe7,
+  0xe9,0x67,0x36,0x3c,0xfe,0xc4,0x1f,0x10,0x1e,0xc7,0xf6,0xf7,0xbf,0x7f,0x1c,0xdb,
+  0xc7,0x9f,0xe0,0x0f,0xfe,0x0e,0x07,0x9f,0x38,0x73,0xfe,0x2c,0x1c,0x34,0xc2,0x22,
+  0x62,0x13,0x92,0xd2,0x85,0x22,0x89,0xa4,0xa8,0xbc,0x54,0xaa,0x2a,0x53,0xa8,0xca,
+  0xe4,0x08,0xe5,0x72,0x95,0x54,0x5e,0x55,0x8e,0x48,0x25,0x9c,0x32,0xfb,0xfa,0x07,
+  0xcf,0x9c,0x3b,0xcf,0x67,0x85,0x08,0xc1,0xa9,0x08,0xca,0x19,0xda,0x27,0x9e,0xf8,
+  0x23,0x5c,0xb1,0x54,0xd6,0xd4,0xe6,0x17,0x95,0x06,0xde,0x08,0xf1,0xf2,0x0f,0xf6,
+  0x0f,0xba,0x75,0x2b,0x24,0x12,0x2e,0x3f,0x92,0x52,0x32,0x85,0x39,0x92,0xc2,0xa2,
+  0xf2,0xaa,0x9a,0x46,0xb8,0x86,0xe9,0xe9,0x1b,0x04,0x2f,0x8d,0x4d,0x80,0x13,0xb5,
+  0x33,0xb3,0x1a,0x3c,0xd9,0x11,0xa0,0x97,0xf7,0xe0,0x4f,0xa8,0xd1,0x30,0x3b,0x34,
+  0x32,0xd6,0xd5,0x33,0xd8,0xdc,0xda,0x0d,0x06,0x96,0x96,0xcb,0x05,0x39,0xe2,0xb4,
+  0x0c,0x81,0x52,0x55,0xad,0xac,0xa8,0x3c,0x70,0xf8,0x88,0x59,0x19,0xd4,0xe4,0x0f,
+  0x8c,0x99,0x7c,0xc3,0x59,0x25,0x01,0x1c,0x9d,0xae,0x96,0x4b,0x55,0xb7,0xc2,0xa0,
+  0x28,0xa6,0x65,0x0b,0xc5,0x92,0x42,0x69,0x49,0x39,0xb1,0x57,0xca,0x98,0x2c,0x63,
+  0x0c,0x47,0x00,0x93,0x2f,0x3b,0x38,0x70,0x0c,0xed,0x82,0xd9,0xb1,0x56,0xe3,0xbf,
+  0x7f,0xfc,0xb9,0x8d,0x9b,0x94,0x95,0xd5,0xd1,0xb1,0x09,0x91,0xd1,0xf1,0x19,0x59,
+  0x22,0x71,0x7e,0x71,0x51,0xa9,0x42,0x4a,0xf8,0x43,0xbc,0x10,0x28,0xce,0x03,0x0c,
+  0x2b,0x04,0x57,0x51,0x49,0x70,0x6c,0xcb,0x65,0x2a,0x73,0xcb,0x82,0x5c,0x51,0x05,
+  0x23,0x72,0x79,0x95,0xed,0xac,0x12,0x5f,0xd4,0xd5,0xba,0x65,0xeb,0x36,0x6b,0x27,
+  0xf0,0x42,0xc6,0xd7,0x99,0x89,0xdd,0x9d,0xc0,0xe3,0xb8,0xfc,0xd4,0xc7,0x67,0x41,
+  0xb1,0x10,0x74,0x60,0x86,0x50,0x24,0x2e,0x2c,0x2e,0x2f,0x2a,0x53,0x96,0xb1,0xd2,
+  0x65,0xf2,0x2a,0x30,0x01,0x35,0x04,0x84,0xdc,0x14,0xe7,0x78,0xe5,0x9a,0x95,0x5b,
+  0xec,0xfa,0x0a,0xda,0x8d,0x9b,0x5e,0x50,0x55,0xd6,0x82,0xbb,0xa2,0xa2,0x93,0xd2,
+  0xb3,0x20,0xd5,0x4b,0x0b,0x4b,0x31,0x0a,0x32,0x85,0x4a,0xca,0x19,0x2e,0xaf,0x02,
+  0xdb,0x41,0x5c,0x5d,0x43,0x2b,0x1c,0xc0,0x9f,0xfc,0xcb,0x53,0xd6,0x06,0x5a,0x76,
+  0x05,0x42,0x91,0x40,0x98,0x1b,0x11,0x15,0x97,0x92,0x9e,0x95,0x2b,0x2e,0x2c,0x2a,
+  0x95,0xd3,0x70,0x63,0x62,0x2b,0x80,0x73,0x25,0xd5,0x96,0xfa,0x10,0x98,0x97,0x11,
+  0x13,0x64,0xe8,0xf9,0x4a,0xb3,0xc3,0x65,0x76,0x5a,0x39,0xc3,0x01,0xec,0xad,0x92,
+  0xab,0xaa,0x6a,0xeb,0xeb,0xb6,0x6e,0xdf,0x0e,0x72,0xed,0x1a,0xf8,0xd4,0xd3,0xcf,
+  0xe6,0x4a,0xc4,0x29,0x69,0x19,0x11,0x91,0x89,0xc9,0xa9,0xd9,0x79,0x92,0xa2,0xa2,
+  0x12,0x69,0x19,0x31,0xc7,0x3a,0x07,0x78,0x52,0x98,0x64,0xe0,0x34,0xe1,0xa2,0xac,
+  0x30,0x23,0xe0,0x0d,0x74,0x88,0x4c,0x55,0x2a,0x55,0x16,0x97,0xc9,0x0a,0x0a,0xcb,
+  0xc5,0xf9,0x85,0xf0,0x39,0x93,0x9a,0x91,0x9d,0x98,0x94,0x0e,0xbb,0x1b,0xae,0x00,
+  0xdf,0xdc,0xb5,0x1b,0x0e,0xe0,0x77,0x1a,0x65,0xdb,0xed,0xb3,0x46,0x32,0x58,0x90,
+  0xfd,0xfe,0xf1,0x3f,0xfe,0x65,0xc3,0x86,0x73,0x85,0x5b,0x6e,0x68,0xb6,0x05,0xeb,
+  0xa1,0x5e,0x6c,0xb9,0x81,0xf5,0x62,0xa3,0xe7,0xc0,0xbf,0x3e,0xba,0x01,0x4a,0xea,
+  0x43,0x2f,0x9c,0xdb,0x7a,0x13,0x8b,0x08,0x4c,0x3d,0x79,0xb9,0xf6,0xeb,0xdf,0xc5,
+  0xef,0x9f,0xff,0x73,0xb3,0x03,0xd0,0x6f,0x0f,0xd6,0x6f,0xbb,0x89,0xf4,0x2f,0xf8,
+  0xa8,0xff,0xf3,0xcf,0x6f,0xc3,0xf8,0x83,0xdf,0xf9,0xd1,0x7a,0xa7,0xba,0x6d,0x37,
+  0xe7,0x37,0xfb,0x4f,0x7d,0xe7,0x47,0x0f,0xad,0x5b,0xf7,0xd5,0x47,0x5f,0x77,0xdb,
+  0x12,0xa4,0x83,0xd3,0xdf,0xf6,0x5b,0xf3,0x50,0x95,0xe0,0xe8,0xb7,0xf5,0x26,0x48,
+  0x01,0x6e,0x7a,0x52,0x9b,0xe6,0x08,0x0e,0x08,0xce,0x92,0xae,0x86,0xfc,0x0c,0x47,
+  0xcf,0x91,0x91,0x2e,0x8c,0xcf,0x82,0x56,0x30,0x02,0x5d,0x32,0xae,0xa1,0x0b,0xc9,
+  0x88,0x86,0x22,0xec,0xa0,0x86,0x32,0x27,0xa0,0xe7,0xd1,0xeb,0x59,0x02,0x1d,0xbb,
+  0x16,0x24,0xce,0xb3,0x5d,0x0d,0xa1,0xa4,0x42,0x51,0x0a,0xdb,0x65,0x38,0x6f,0xbd,
+  0x89,0xc4,0xd0,0x52,0xff,0x80,0x45,0x54,0x67,0xd2,0xe5,0x14,0xc0,0x2f,0x96,0xb7,
+  0x07,0xeb,0x00,0xb6,0xdd,0xd4,0xbd,0x1a,0x3a,0xfb,0xf2,0x2d,0xed,0x2b,0xa1,0x73,
+  0x6f,0x84,0xeb,0xde,0x0c,0x9f,0xdf,0x19,0xa9,0xdb,0x1d,0x3d,0xb7,0x37,0xc6,0xf0,
+  0x5e,0x02,0x96,0x5d,0x38,0xf3,0x7e,0x94,0x65,0xb8,0x24,0x32,0x5c,0x11,0x1b,0xae,
+  0x15,0x18,0x5c,0x8a,0x0c,0xde,0xa5,0x8b,0xfe,0xa5,0x0b,0xb7,0xca,0xb5,0x3e,0x45,
+  0x06,0xdf,0xfc,0x19,0x5f,0xc9,0x58,0xfb,0xd8,0xe7,0x77,0xe3,0xeb,0x5f,0x1d,0x9a,
+  0x5b,0xdb,0xf7,0xee,0x7d,0x1b,0x0a,0xca,0x47,0xa7,0xce,0xba,0x79,0x05,0x44,0xc6,
+  0xc4,0xc1,0xe7,0xbf,0x54,0xa1,0xaa,0x6b,0x6c,0xe9,0xe8,0x55,0xf7,0x0f,0x4f,0x4c,
+  0x4e,0x41,0xe9,0xd0,0xd2,0xaf,0x7f,0x49,0x15,0x9e,0x83,0x4a,0x32,0x35,0x3d,0x3b,
+  0x32,0x36,0x3d,0x88,0x37,0x45,0x0f,0x92,0xd7,0x34,0xb4,0xc0,0x66,0x87,0x4d,0x27,
+  0x12,0x17,0xa4,0x65,0x0a,0xe3,0x93,0xd2,0x42,0xc2,0xa2,0x03,0x6f,0xdc,0xf2,0xf4,
+  0xf2,0xbb,0x7a,0xcd,0xed,0xc2,0xa5,0x2b,0x50,0x85,0x4f,0x7e,0x70,0xfa,0xf0,0x91,
+  0xe3,0xfb,0xf7,0x1f,0xda,0xb3,0x77,0xff,0xce,0xdd,0xfb,0x5e,0x7f,0x63,0xf7,0x2b,
+  0xaf,0xbd,0xf1,0xea,0xeb,0x3b,0x73,0x44,0xb9,0xc2,0xdc,0xe2,0x98,0xb8,0xc4,0x84,
+  0xa4,0x34,0x28,0xc1,0x99,0xd9,0x79,0x70,0xf4,0xcb,0xcc,0xce,0x81,0x16,0x0e,0x71,
+  0x80,0x64,0x09,0x72,0x33,0xb3,0x85,0x80,0x8b,0x25,0x45,0x6d,0x1d,0x9d,0xdb,0x5f,
+  0x7e,0xf5,0xa9,0xa7,0xd7,0x43,0x15,0x7e,0xea,0xe9,0x0d,0x4f,0x3d,0xb3,0x01,0x8e,
+  0x42,0x4f,0x3d,0xf3,0x2c,0x6d,0x01,0x9e,0x7c,0xea,0x69,0x80,0xbf,0x3c,0xfd,0x0c,
+  0xc0,0xe9,0x8f,0xcf,0xd5,0x37,0x34,0x86,0x46,0x46,0x47,0xc7,0x24,0xc2,0xf9,0x3a,
+  0x35,0x3d,0x0b,0x2e,0x98,0x33,0xb2,0x84,0x99,0xd9,0x22,0xd2,0xe6,0x00,0x92,0x25,
+  0x40,0x1c,0xda,0xc6,0xe6,0xb6,0xeb,0x6e,0xee,0xb0,0xea,0xe9,0x67,0xd7,0x53,0x26,
+  0x4f,0x3d,0xb3,0x1e,0x00,0x46,0x9e,0x02,0x40,0x11,0xcf,0x50,0xce,0x4f,0x3f,0xb3,
+  0xfe,0x99,0xf5,0x1b,0xc0,0x96,0x82,0xe2,0xe2,0x8a,0xaa,0x1a,0xb8,0x72,0x80,0xeb,
+  0x8d,0x5b,0xa1,0xd1,0xa1,0xe1,0x31,0xf8,0x87,0xec,0xc4,0xf4,0xd4,0xf4,0xec,0x5c,
+  0xbc,0x92,0x80,0xcf,0x8f,0x9a,0xda,0xba,0x26,0xb8,0x44,0x81,0xe3,0x40,0x4f,0xef,
+  0x00,0xbd,0xfe,0x1f,0x1c,0x1a,0x81,0x16,0x0e,0xf5,0x70,0x49,0xdf,0xde,0xd9,0xdb,
+  0xdc,0xd6,0x59,0x57,0xd7,0xac,0x54,0x55,0x15,0x97,0xca,0x73,0xc5,0x45,0xe9,0x99,
+  0x22,0xa8,0x9b,0xb5,0xf5,0x8d,0xe5,0x52,0xf9,0xc1,0x23,0x47,0x41,0x99,0xbf,0x30,
+  0xd2,0x19,0x03,0x29,0xa0,0x81,0x4f,0xa1,0xb1,0x40,0x40,0xbb,0x4f,0x3f,0xf3,0x2c,
+  0x00,0xd4,0x53,0x65,0x45,0x75,0x70,0x68,0x44,0x54,0x74,0x02,0xf8,0x33,0x2d,0x23,
+  0x0b,0x2a,0x63,0x46,0x16,0x78,0x55,0x44,0x7c,0x2b,0x22,0x00,0x86,0x0b,0x33,0xb2,
+  0x72,0x1a,0x9b,0xda,0x5c,0xdd,0x3c,0x28,0x7f,0x86,0x27,0x01,0x4e,0x28,0x95,0xcb,
+  0xef,0x82,0xdb,0x09,0xc1,0x06,0x28,0x0d,0xdb,0x5e,0x7a,0x59,0x55,0x59,0x15,0x97,
+  0x98,0x1a,0x1a,0x11,0x0b,0xee,0x4d,0x4a,0xcd,0x04,0x9e,0x00,0xc0,0x9f,0xb8,0x97,
+  0xf1,0x30,0x01,0x73,0x97,0x28,0x23,0xa4,0x2d,0x0b,0x9c,0x56,0x39,0xdc,0x12,0xaa,
+  0x33,0x0f,0xa1,0x3c,0x45,0x39,0x79,0x92,0xc6,0xe6,0x96,0x5d,0x7b,0xde,0xa2,0x61,
+  0x7a,0x9a,0xda,0xce,0x86,0x0c,0xbd,0x01,0xb9,0x41,0x7c,0xc2,0x5a,0xf4,0x2c,0xa7,
+  0xbc,0x95,0x99,0xd6,0x56,0x43,0xb8,0x9f,0x7e,0xf6,0xd4,0x99,0xb3,0x95,0xd5,0x75,
+  0xa1,0x11,0xd1,0x91,0xd1,0x89,0x89,0xc9,0xe9,0x69,0x19,0x98,0x30,0xc4,0x28,0x11,
+  0x5f,0x0d,0xd0,0x2a,0x4b,0x90,0xd3,0xd0,0xd4,0xec,0xe3,0xe7,0xff,0x24,0x1b,0x1a,
+  0x73,0xaa,0xf0,0xdc,0x48,0x7d,0x05,0x34,0x2f,0x6e,0xd9,0xaa,0xaa,0xac,0x89,0x4f,
+  0x48,0x85,0x0b,0xc2,0xb8,0x84,0xe4,0x94,0x34,0xc8,0x46,0x01,0x44,0xc7,0xd2,0x4c,
+  0xc6,0xea,0x92,0xd2,0xf2,0xe2,0x92,0xb2,0x17,0x36,0x6f,0x7d,0xfa,0x19,0x26,0xca,
+  0xa4,0x65,0x58,0xd1,0x2e,0x30,0x4f,0xcf,0xc8,0x10,0xe5,0x15,0x84,0x86,0xc5,0xc4,
+  0xc6,0x27,0x25,0xa5,0x30,0x0c,0x81,0x15,0x41,0x04,0x9c,0xeb,0xf8,0x8e,0xa5,0xe1,
+  0xe0,0x5b,0x64,0x39,0x6b,0x1b,0x05,0xdc,0x1d,0xcd,0x2d,0x2d,0x3b,0x76,0xed,0xe2,
+  0x25,0x1b,0xbb,0x35,0x48,0x3e,0x3c,0xbf,0xf1,0x05,0xb8,0xbe,0x85,0xab,0xe8,0x30,
+  0xf8,0xf8,0x48,0x48,0x4a,0x4c,0xc9,0x82,0x0b,0x48,0x2e,0x82,0x34,0xdf,0x6c,0x22,
+  0xcb,0x09,0x12,0xf2,0x68,0xac,0x93,0x01,0x44,0xd3,0x41,0x62,0x51,0x0e,0x6c,0xe1,
+  0xa4,0x94,0x8c,0x04,0xf8,0x2f,0x4b,0x00,0xa7,0xec,0xe2,0xd2,0xf2,0xc3,0x64,0x8f,
+  0xd0,0x10,0xac,0x15,0x59,0x36,0xf4,0x1b,0xf8,0x5d,0x2e,0x73,0xec,0x12,0x63,0x9e,
+  0x3f,0xb5,0x9e,0x1d,0x7c,0x16,0x12,0x63,0xd3,0x9e,0xf3,0x2f,0xdd,0x98,0x7c,0x2d,
+  0x54,0xff,0x6a,0xe8,0x1c,0x69,0xb5,0xaf,0x84,0xe8,0x5e,0xb9,0x39,0xf5,0xb3,0xe7,
+  0x8e,0x40,0x49,0xfd,0xc1,0x2f,0x37,0xbe,0x1c,0x34,0xf6,0x5a,0x18,0xde,0xa0,0xbb,
+  0xc1,0xb1,0xf2,0x41,0x52,0x7f,0x1f,0xda,0x7a,0x9e,0x9c,0xe6,0x90,0x12,0x90,0x57,
+  0x6e,0xcd,0x3e,0xbc,0xcd,0x11,0xeb,0xef,0x3f,0xff,0x64,0xd3,0xb5,0x7a,0x60,0xf2,
+  0xdc,0xd5,0xda,0xaf,0x7e,0xed,0x9b,0x5f,0xf9,0xda,0xb7,0x9f,0x38,0x9a,0x02,0x0c,
+  0x09,0x4f,0x3d,0x50,0xbe,0x4a,0xf8,0xbf,0x86,0xdd,0xb9,0x57,0x42,0x61,0x04,0xbb,
+  0x2f,0xdd,0xd2,0xbf,0x16,0x0a,0x53,0xda,0xd7,0xb1,0xab,0x7f,0x39,0x04,0x08,0xe6,
+  0x5f,0x0d,0xd5,0x11,0x11,0x73,0x2f,0x07,0x6b,0x51,0x3a,0x10,0x84,0xe8,0x70,0x30,
+  0x14,0x2b,0xda,0x2b,0x21,0xda,0x57,0x81,0x5b,0x08,0x10,0x23,0x93,0x97,0x6e,0x51,
+  0x62,0x04,0xc0,0x29,0x2b,0x1c,0x04,0xd1,0xc8,0x53,0xf7,0x72,0x08,0xc1,0x43,0x75,
+  0x68,0x5a,0x28,0x43,0xf6,0x1a,0x22,0x7a,0xb2,0x4a,0x4f,0x96,0xcc,0xbd,0x8a,0x6a,
+  0x00,0x4f,0xdd,0xcb,0xb7,0xf4,0x94,0xe6,0xa5,0x60,0x0d,0x08,0x02,0x71,0xa0,0x24,
+  0x99,0x05,0x04,0xb9,0x11,0x1c,0x67,0x5f,0x0b,0x9b,0x67,0x4d,0xd3,0x51,0xfe,0x50,
+  0x6d,0x01,0x5e,0x0f,0xd7,0xbe,0x11,0xae,0xdd,0x15,0xa9,0x7f,0x3b,0x66,0x6e,0x5f,
+  0xac,0xfe,0x5d,0x72,0xda,0x05,0x38,0x9a,0x6a,0x38,0xce,0x7d,0xdb,0x9c,0x6b,0xb8,
+  0x96,0x6f,0x70,0x2f,0x5e,0xf0,0x2b,0x5f,0xf4,0x97,0x2e,0x06,0xca,0x97,0x82,0x64,
+  0x8b,0xc1,0xb2,0x45,0xbf,0x62,0xad,0x4f,0xfe,0x8c,0xb0,0x4e,0xb7,0xb8,0xf6,0xef,
+  0xf8,0xfe,0xf7,0xc3,0xe2,0xf2,0xd2,0xad,0xb0,0xc8,0x37,0xde,0xdc,0x75,0xf0,0xd0,
+  0xd1,0x8b,0x97,0xaf,0xfa,0x06,0xdc,0x84,0xa3,0x53,0x5e,0x7e,0xa1,0x52,0x55,0xdb,
+  0xd4,0xda,0x01,0x57,0xf8,0x63,0xe3,0xf8,0x77,0xe0,0x99,0x59,0x3c,0x02,0xcf,0xcd,
+  0xd3,0x3f,0xc5,0xce,0xc1,0x29,0x18,0x46,0xc7,0x27,0x67,0x86,0x46,0x26,0x7a,0x07,
+  0xd4,0x1d,0x5d,0xfd,0x0d,0x4d,0x6d,0x55,0x35,0x0d,0x50,0x85,0xf3,0x0b,0xcb,0x72,
+  0x72,0xf3,0xd3,0x32,0x84,0xb1,0xf1,0x29,0x61,0xe1,0xb1,0x01,0x70,0x42,0xf4,0x0d,
+  0x70,0xbc,0xee,0xe9,0xe0,0xe4,0x7c,0xf6,0xbc,0xc3,0xa9,0x33,0xe7,0x3e,0xfc,0xf0,
+  0xd4,0xc1,0xc3,0xc7,0x0f,0x1c,0x3c,0xb2,0xff,0xbd,0x43,0xef,0xee,0x3f,0x20,0xc8,
+  0xc9,0x2d,0x29,0x95,0xc7,0x25,0xa4,0x81,0x5c,0xb2,0xb9,0x32,0x68,0x9b,0x98,0x0c,
+  0x6d,0x1a,0x8c,0xc3,0xc7,0x20,0x00,0xa9,0x26,0x42,0x28,0x58,0x7b,0xdf,0x7e,0x77,
+  0xf3,0x96,0x6d,0x5b,0xb6,0x6e,0x7f,0x71,0xf3,0xb6,0x17,0xb7,0xbc,0xbc,0x65,0x1b,
+  0x20,0x5b,0x36,0x6f,0xd9,0xba,0x75,0xdb,0x76,0x38,0x4d,0x03,0x0e,0x87,0x23,0xe8,
+  0x6e,0xde,0xba,0xed,0xcc,0xb9,0x4b,0xcd,0x2d,0xed,0x91,0x31,0x89,0x51,0x31,0x09,
+  0x70,0xee,0x88,0x4b,0x48,0x85,0xcf,0xbd,0xf8,0xc4,0x54,0xd8,0xbf,0x71,0x09,0x29,
+  0xa4,0x4d,0x25,0x22,0x52,0x80,0x3f,0x7c,0xea,0xde,0xbc,0x15,0xb2,0x6d,0xfb,0x2b,
+  0xc0,0x67,0xf3,0x96,0xed,0x94,0x0f,0x91,0x82,0xac,0x36,0x6f,0xdd,0xbe,0x75,0xfb,
+  0x4b,0xf0,0x11,0xba,0x99,0xc0,0x0b,0x38,0xf8,0xf2,0xbe,0xb7,0xdf,0x49,0x49,0x4b,
+  0x6f,0xeb,0xe8,0x2a,0x29,0x91,0x46,0x46,0xc7,0x85,0x45,0xc6,0x12,0x41,0xc9,0xc0,
+  0x16,0x3e,0x5d,0xe1,0x93,0x10,0xae,0x64,0xc4,0xf9,0x25,0x85,0x25,0x72,0x38,0xe0,
+  0x28,0x94,0x55,0x70,0xfc,0x51,0x55,0x37,0x00,0x54,0xd5,0xd4,0x57,0x54,0xd5,0xc1,
+  0x79,0x5e,0x2a,0x57,0x16,0x95,0xca,0x24,0x05,0x65,0x42,0x51,0x01,0xf9,0x6c,0x17,
+  0x94,0x4b,0x95,0x5d,0xdd,0xbd,0xa9,0x19,0x59,0xc0,0x7c,0x33,0x31,0x04,0x64,0x6d,
+  0x41,0x95,0xb6,0xd2,0x2e,0x00,0x98,0xc9,0x74,0xb7,0x6e,0xdf,0x0c,0x26,0x53,0x6f,
+  0x6c,0xd9,0x06,0x3a,0x3b,0x5d,0xbd,0x56,0x53,0x5b,0x1f,0x19,0x95,0xc0,0x9a,0x8c,
+  0x36,0x82,0x63,0xe3,0x13,0xd3,0x09,0x6e,0x01,0x55,0x35,0x75,0xc1,0xa1,0x21,0x60,
+  0x20,0xac,0x05,0x93,0x29,0x5b,0xca,0x6a,0xcb,0xb6,0x97,0x88,0x57,0xb7,0x93,0x91,
+  0x6d,0xc4,0xa5,0x8c,0x9f,0x01,0x27,0xf4,0x5b,0xdf,0x78,0x73,0xa7,0x42,0x55,0x09,
+  0x1f,0x89,0x70,0xf0,0x27,0xb2,0x92,0x59,0x71,0x76,0x64,0x7d,0x5e,0x00,0x8e,0x85,
+  0xfa,0x7b,0xec,0xf8,0xc9,0x17,0x36,0x6f,0x79,0x71,0xeb,0x76,0x6b,0x6f,0xb0,0x01,
+  0xe2,0x3b,0x6a,0x0b,0x8e,0x53,0xd7,0xd1,0xb0,0x6e,0x27,0xb0,0xcd,0xaa,0x0b,0xf8,
+  0x8b,0x5b,0xb6,0x7f,0x7c,0xfe,0x7c,0x5d,0x43,0x73,0x4c,0x5c,0x52,0x44,0x54,0x42,
+  0x6c,0x7c,0x32,0x20,0x60,0x0e,0xb1,0x28,0x99,0x1a,0x08,0xce,0x24,0xc9,0x93,0x06,
+  0x50,0x59,0x5d,0x1d,0x16,0x11,0x4d,0xa2,0xb3,0x8d,0xf2,0xa1,0x4e,0xa3,0x72,0x31,
+  0x70,0xc4,0x99,0x9b,0xb1,0xdd,0xfe,0xda,0xeb,0x6f,0x56,0x54,0x55,0x67,0x64,0xe6,
+  0x44,0x46,0x27,0xc0,0x35,0x1b,0xec,0x0e,0x5b,0x47,0x91,0x9c,0x4c,0x06,0xce,0xb0,
+  0x29,0x54,0xaa,0x8a,0x37,0x77,0xbc,0x45,0xd7,0x6e,0xa1,0xa6,0x21,0xdb,0xed,0x4c,
+  0x50,0xb6,0x61,0xe8,0x53,0xd3,0xd2,0xe1,0x84,0x0e,0xe7,0x5f,0x08,0x37,0xcf,0xff,
+  0x69,0xac,0xce,0xd6,0xde,0xa3,0x99,0x7f,0xe7,0x40,0x58,0x81,0xa5,0x19,0xcd,0x6d,
+  0xad,0x87,0x8e,0x1c,0x25,0xe6,0x6c,0xc5,0x8d,0x00,0xbe,0x62,0x93,0x01,0x60,0xeb,
+  0xf6,0x57,0x84,0xb9,0x79,0xb9,0x92,0x42,0x30,0x2d,0x3a,0x06,0xac,0x4b,0x61,0x1d,
+  0x95,0xfa,0x19,0xc3,0x0d,0xd7,0x75,0xac,0x21,0xc0,0x0d,0x9c,0x96,0x90,0x91,0x95,
+  0xad,0x54,0x55,0x76,0x74,0xf5,0xc0,0x66,0xd9,0xb5,0x67,0x1f,0xb8,0x17,0xfc,0x8c,
+  0xdf,0xa7,0x81,0x42,0xdb,0x5e,0x62,0x76,0x0a,0x8d,0xac,0x55,0x77,0xab,0x45,0x8c,
+  0xcc,0x79,0xc2,0xee,0x23,0xbb,0xc4,0x34,0xcd,0x5e,0xde,0xf1,0xce,0x9b,0xde,0x75,
+  0xbb,0xa2,0xe6,0xde,0x8e,0xd1,0xec,0x89,0xd2,0xef,0x8d,0xd6,0xed,0x8c,0x98,0x7b,
+  0x2b,0x7a,0x6e,0x4f,0x94,0xf6,0x2f,0x1f,0xa6,0xe0,0xfb,0x25,0xff,0xf1,0x87,0xcf,
+  0x3b,0x94,0xed,0x8e,0xd2,0xee,0x89,0xd2,0xbd,0x78,0xad,0xfa,0x1f,0xbf,0xf7,0x33,
+  0x18,0xfc,0xc5,0xe6,0x33,0xaf,0x05,0x0d,0xbe,0x41,0xe0,0x25,0xdf,0xbe,0xf5,0xe7,
+  0xf3,0x7f,0xf8,0xf0,0x53,0x30,0xfe,0x4f,0x3f,0xfd,0xfd,0xab,0x81,0xc3,0xbb,0xc2,
+  0xa6,0xfe,0xfb,0x4d,0x37,0xfc,0x9a,0xfa,0x47,0x8f,0xbc,0xe4,0xdb,0x05,0x0b,0x81,
+  0x33,0x30,0xdc,0x19,0xc9,0x70,0xde,0x1b,0xad,0xd9,0x1d,0xa5,0xdf,0x17,0xa3,0x27,
+  0x53,0x9a,0xbd,0x31,0x73,0xbb,0xa3,0xe6,0x76,0xe1,0xac,0x6e,0x4f,0x34,0xde,0x8f,
+  0xb4,0x37,0x5a,0x0b,0x23,0x7b,0x63,0xb0,0xbb,0x2f,0x46,0x0b,0x2a,0xed,0x8e,0xd4,
+  0xed,0x8b,0x86,0x72,0x86,0xcb,0x61,0x2d,0xd4,0x35,0xd0,0x79,0x6f,0x94,0x66,0x27,
+  0x8e,0xe8,0x28,0x67,0x50,0x12,0x06,0x41,0xd6,0xce,0x48,0x3d,0x1d,0xdc,0x8d,0x42,
+  0xe7,0x61,0xed,0x2e,0xe4,0x4f,0x5b,0x3d,0x2c,0xdf,0x1d,0xa9,0x45,0xfa,0x48,0x2d,
+  0x35,0x96,0x2c,0xd7,0x33,0xc4,0x51,0x38,0x45,0xc8,0x70,0x76,0x0f,0x3a,0x44,0xc7,
+  0x10,0x47,0xce,0xef,0x88,0x00,0x26,0xc0,0x59,0xb7,0x23,0x12,0x7f,0x2e,0x04,0x83,
+  0xd0,0xdd,0xcd,0xca,0x02,0xf5,0xde,0x8e,0xd1,0xbd,0x13,0xab,0x47,0x88,0x9b,0x07,
+  0x78,0x3f,0x61,0x0e,0x8e,0xba,0x00,0x47,0x52,0x0c,0x27,0x33,0x0c,0x67,0x05,0x08,
+  0x17,0x45,0x06,0xa7,0x7c,0xc3,0xd5,0x02,0x83,0x07,0x1c,0x78,0xcb,0x97,0x82,0xe5,
+  0x2b,0xb7,0x14,0x2b,0x51,0x15,0x0b,0x91,0xaa,0xc5,0x70,0xd5,0xd2,0x4d,0xe9,0x42,
+  0x40,0xa9,0xe6,0x66,0xf1,0xb4,0x7a,0xf6,0x1e,0x78,0xe0,0xe4,0xed,0x61,0x40,0xad,
+  0x86,0xa3,0xd6,0x8e,0x5d,0x6f,0x9d,0x38,0xf9,0xa1,0xd3,0x35,0xf7,0x9b,0x21,0xe1,
+  0xe9,0x99,0xc2,0xfc,0xc2,0x72,0xb8,0xc2,0x6c,0x6d,0xef,0xee,0x1f,0x1c,0x19,0x1d,
+  0x9f,0x9e,0x9e,0xd1,0xc2,0xc9,0x17,0x4e,0xc1,0xf3,0x06,0x03,0x85,0x59,0x8d,0x06,
+  0xea,0x32,0x54,0x61,0x98,0x1d,0x50,0x8f,0xf4,0xf4,0xa9,0xdb,0x3a,0x7a,0x1a,0x9a,
+  0x5a,0xab,0x6a,0x6a,0xcb,0xa4,0xaa,0xfc,0xc2,0x52,0x61,0xae,0x24,0x35,0x5d,0x08,
+  0x1b,0x07,0x2e,0xf8,0x6f,0x04,0x87,0xf9,0x07,0x04,0xbb,0x7b,0xfa,0x5e,0x73,0x71,
+  0xbf,0x7c,0xc5,0xf9,0xfc,0xc5,0xcb,0xa7,0x3e,0x3e,0xff,0xd1,0xa9,0x73,0x27,0x3f,
+  0x38,0x05,0x45,0xaa,0xba,0xb6,0x1e,0x5a,0x72,0x1a,0x85,0x2b,0x5e,0xe6,0xd2,0x17,
+  0xea,0x17,0x5c,0xf4,0x42,0xcd,0x4d,0xcf,0xcc,0x49,0xcb,0xc8,0x81,0x56,0x90,0x23,
+  0xea,0xeb,0xef,0xff,0xe8,0xf4,0x99,0x5d,0xbb,0xf7,0x12,0x78,0xeb,0xf5,0x9d,0xef,
+  0xec,0xd8,0xb5,0x77,0xc7,0xce,0xb7,0x76,0x42,0x77,0xcf,0x5e,0xc4,0x77,0xbd,0x05,
+  0x2d,0xcc,0xbe,0xb9,0x6b,0xf7,0xb9,0x0b,0x0e,0x9d,0xdd,0x3d,0xc0,0x36,0x2d,0x5d,
+  0x98,0x8a,0x90,0x0d,0x97,0xe5,0x04,0x84,0x14,0x81,0x2d,0x0c,0x38,0x5c,0x57,0xc3,
+  0xb9,0xb8,0xb2,0xba,0x3e,0x31,0x29,0x69,0xcf,0x9e,0xb7,0xe9,0x72,0xe4,0xb3,0x13,
+  0x91,0x9d,0xbb,0x10,0x90,0x21,0x48,0xd9,0xb5,0x77,0x37,0x8e,0xec,0x01,0x71,0x30,
+  0xbb,0x73,0xe7,0xde,0x7d,0xef,0x1c,0x70,0xf3,0xf4,0x92,0x2b,0x2b,0xdb,0xda,0x3b,
+  0x8b,0x8a,0xcb,0x81,0x27,0x7c,0x78,0x26,0x26,0x67,0x26,0xa7,0x66,0x90,0x03,0x8e,
+  0x30,0x23,0x3b,0x37,0x3b,0x27,0x0f,0x4e,0x6d,0x70,0xb6,0xcd,0x93,0x14,0x4b,0x0a,
+  0x8b,0x25,0x05,0xa5,0x80,0x50,0xc8,0xc9,0x2b,0x10,0x88,0xf0,0x8c,0x0f,0xc7,0x87,
+  0xb2,0x72,0x79,0x67,0x57,0x0f,0xb8,0xc2,0xc5,0xdd,0xe3,0x9d,0xfd,0x07,0x76,0x11,
+  0x11,0xd4,0xb4,0x9d,0x68,0xd7,0x5e,0x46,0x28,0x51,0x8c,0xe2,0xbb,0x98,0x11,0x6a,
+  0x38,0x12,0x3b,0x5f,0x77,0x6d,0x6a,0xe9,0x64,0x2c,0x4d,0x07,0x33,0xb3,0x08,0x64,
+  0x83,0x26,0x9c,0xd5,0xd0,0x25,0x04,0xc2,0x9a,0xba,0xfa,0xc4,0xe4,0x54,0x8e,0x03,
+  0x0a,0xda,0xfd,0x16,0xc7,0x16,0xdc,0xbb,0x73,0x27,0x63,0x3e,0x43,0xb0,0x0b,0x95,
+  0x21,0x08,0x78,0x63,0xcf,0xbb,0xef,0xbd,0xaf,0xac,0xa8,0x10,0x4b,0x8a,0x88,0x6f,
+  0xb3,0xd8,0x48,0x09,0x52,0xd3,0x51,0x04,0x15,0x44,0x25,0x82,0x38,0x0a,0x44,0x07,
+  0x0b,0xe0,0x05,0x25,0x9b,0x84,0x43,0xc0,0x52,0x0a,0x2c,0x81,0xae,0x85,0xa3,0x53,
+  0x6e,0x47,0x57,0xf7,0x45,0x87,0x2b,0xa0,0xde,0x9b,0x3b,0x31,0x4c,0x3b,0xa9,0xc2,
+  0x8c,0x9e,0x6f,0xe1,0xc8,0x2e,0xd6,0x33,0x3c,0x8b,0x30,0x94,0x38,0xc2,0xcc,0xd2,
+  0x25,0x94,0x78,0x27,0xd3,0x45,0xfc,0xfc,0x25,0x87,0xe6,0xd6,0x36,0x38,0x73,0x81,
+  0x45,0xc4,0x10,0x21,0x5f,0x0d,0x9e,0x6e,0xa8,0x7c,0x45,0x55,0x6d,0x7a,0x66,0xd6,
+  0x9e,0xbd,0xfb,0xa8,0x0f,0x49,0xa4,0x18,0x86,0xc0,0x8d,0x26,0x24,0xe3,0x3d,0x48,
+  0x95,0xb7,0xf7,0xc3,0x75,0x57,0x41,0x51,0x31,0xe1,0x8c,0x7c,0xc0,0x5d,0x90,0x7b,
+  0x10,0x20,0xea,0x3d,0xc2,0x9f,0xb6,0x39,0xb9,0xe2,0xc2,0x86,0xc6,0xa6,0x43,0x87,
+  0x8e,0xef,0x60,0xb5,0x7d,0x73,0xe7,0x2e,0xea,0x7c,0x36,0x3a,0xc8,0x36,0x23,0x33,
+  0x4b,0x51,0x51,0xc9,0x31,0x64,0x15,0xcb,0xa6,0x4c,0x78,0x51,0xa0,0x99,0xc0,0x84,
+  0x89,0x06,0x82,0x5d,0x92,0x6d,0x69,0x1a,0xd7,0x65,0x32,0x87,0x76,0xdb,0x3a,0x3a,
+  0xce,0x5f,0x74,0xc0,0x84,0x04,0x7f,0x62,0xfe,0xa3,0x9f,0xd9,0x6d,0x88,0x5e,0xcd,
+  0x15,0xe7,0xcb,0x14,0x15,0xa9,0xe9,0x99,0x5c,0x32,0xc0,0x9e,0x65,0x53,0x42,0xc8,
+  0x72,0x36,0x8b,0xe6,0x38,0xb3,0x99,0x90,0x6d,0x19,0x77,0x73,0x02,0x40,0xea,0xc2,
+  0xd5,0x88,0x28,0xaf,0xb0,0xb4,0x5c,0xd1,0xd4,0xdc,0xd2,0xda,0xd6,0x55,0x58,0x54,
+  0xe2,0xe0,0x74,0x6d,0xdf,0x3b,0xfb,0x77,0xd2,0x10,0xef,0x62,0x74,0xa0,0x59,0xca,
+  0x86,0xfe,0xad,0x1d,0xdc,0xbe,0xc0,0xc1,0xb7,0x76,0xb0,0x1b,0x99,0x06,0x9a,0x64,
+  0xce,0x5b,0x5c,0x6e,0xb3,0xf9,0x4f,0x70,0x20,0x26,0xc8,0x9b,0x64,0xbb,0xbd,0xbe,
+  0x7b,0xdf,0x3e,0x67,0xe1,0xfe,0xd8,0x59,0x38,0x97,0x1d,0x48,0x84,0x03,0xda,0xfc,
+  0x81,0xa4,0xb9,0xf7,0x12,0xb0,0x6a,0xbc,0x13,0x37,0xf7,0x76,0x98,0xfa,0xdb,0x3f,
+  0x7a,0x6c,0xdd,0x7d,0x0f,0x3c,0xb2,0xfe,0xed,0x7d,0x11,0x63,0x40,0xf3,0x8a,0x7b,
+  0xd5,0x3f,0x7e,0x1f,0xcf,0xbf,0xdf,0xf8,0xf6,0x0f,0xbe,0xfb,0x6f,0xbf,0xf9,0xce,
+  0xbf,0xff,0xee,0x5f,0xfe,0xf3,0x77,0xdf,0xfd,0xd1,0x23,0x5f,0x7f,0xf0,0xbb,0xf7,
+  0xdf,0xf7,0xc0,0x37,0x1f,0xfc,0xa7,0x27,0x76,0xbb,0xbc,0x1f,0xaf,0x7b,0xd5,0x4d,
+  0xf5,0xcf,0x3f,0xfd,0x0d,0x8c,0xfc,0x7a,0xeb,0xa9,0xf7,0xe3,0xb5,0x07,0x08,0x73,
+  0x7a,0x8b,0x2f,0x70,0x7e,0x3f,0x11,0x60,0xde,0x8c,0x80,0x50,0xec,0xea,0x0f,0x24,
+  0xe8,0xdf,0x43,0x5c,0x8f,0x78,0xa2,0x0e,0xd4,0x38,0x80,0x5d,0xdd,0xfb,0x09,0x86,
+  0xf7,0x12,0x98,0x3b,0x84,0xa1,0x3d,0x40,0x5a,0xa0,0xa1,0x6b,0x09,0x4f,0x3d,0xea,
+  0x9c,0x48,0xe9,0x81,0x15,0xe2,0xef,0x31,0xb3,0x88,0x98,0xf1,0x04,0x82,0x27,0x30,
+  0x38,0x19,0x24,0x6b,0x51,0x22,0x8f,0x55,0xc2,0xdc,0x7b,0x3c,0x1a,0x22,0xce,0xb0,
+  0x9f,0x08,0xdd,0x9f,0x40,0x8f,0xb1,0xcc,0xf8,0xfe,0x78,0xb3,0x56,0x07,0x12,0xe7,
+  0x80,0xc9,0xc1,0x24,0x03,0x00,0x1c,0x72,0x01,0xa0,0xe0,0xc2,0x39,0xf7,0x83,0x0c,
+  0xe6,0x7b,0x66,0x87,0x3c,0xc3,0x55,0xb1,0xc1,0xa5,0x68,0xc1,0xb5,0x78,0xc1,0xbf,
+  0x6c,0x31,0x50,0xb6,0x14,0xa2,0x5c,0x09,0xab,0x58,0x89,0xa9,0x36,0xc6,0xd5,0x1a,
+  0x63,0xaa,0x57,0xe3,0x6a,0xa0,0x0a,0x2f,0xdd,0x92,0xcf,0x07,0x14,0x4d,0x49,0x5a,
+  0xe7,0x57,0xef,0x9d,0xdf,0x1c,0xad,0x05,0x46,0x93,0x31,0x3d,0x23,0xeb,0xf5,0x37,
+  0xf1,0xe9,0x88,0xa7,0xcf,0x5c,0x74,0xf3,0x0a,0x0c,0x8f,0x8e,0xcb,0x12,0xe4,0x96,
+  0x4a,0x95,0xe4,0xa6,0x9a,0x9e,0x01,0xf5,0xe8,0xc4,0xd4,0x0c,0x54,0xdb,0x59,0x8d,
+  0x9e,0xab,0xbf,0x00,0xf4,0x20,0x4c,0x9f,0x91,0x45,0xbe,0x56,0x1d,0x6a,0xef,0xec,
+  0x6b,0x6e,0xed,0xac,0xa9,0x6b,0xae,0xa8,0xac,0x92,0xca,0x54,0x92,0x82,0x12,0xa1,
+  0x28,0x3f,0x3d,0x53,0x04,0xd7,0xb1,0x70,0x89,0x1e,0x1a,0x1e,0x1d,0x10,0x1c,0xea,
+  0xeb,0x8f,0x85,0xd8,0xc5,0xcd,0xd3,0xe9,0x9a,0xdb,0x15,0x27,0x17,0xa8,0xb3,0xe3,
+  0x93,0x93,0x83,0xea,0xa1,0xfe,0x81,0x91,0x01,0x35,0xbd,0x4b,0x64,0xa0,0xb7,0x7f,
+  0xa0,0xbb,0x6f,0xa0,0x7f,0xb0,0xbf,0xb7,0x7f,0xb0,0xa7,0xaf,0xaf,0xa7,0x77,0x10,
+  0x90,0xbe,0x01,0x38,0x8c,0x4f,0x5e,0x76,0x70,0x3c,0x7c,0xe4,0xd8,0x91,0xa3,0x27,
+  0x8f,0x1c,0x3d,0x71,0xe4,0xc8,0xf1,0x43,0x47,0x8e,0x1d,0x3a,0x72,0xf2,0x30,0x81,
+  0x83,0x87,0x11,0x28,0x7e,0xe8,0xe8,0xc9,0x0b,0x0e,0xce,0xa3,0x63,0x63,0x7d,0xfd,
+  0x7d,0x7d,0xfd,0x83,0xdd,0xbd,0xfd,0x7d,0x84,0x15,0xc3,0x90,0x45,0x7a,0xfb,0x60,
+  0x0a,0xf1,0x91,0xb1,0x89,0xd4,0xf4,0x8c,0x23,0x47,0x8f,0xe3,0xf2,0xa3,0xc8,0x07,
+  0xd8,0x1e,0x3a,0x7c,0xec,0x30,0xc7,0xfc,0xd0,0x11,0x22,0x14,0x06,0x8f,0x73,0x53,
+  0x07,0x0f,0x1d,0x07,0x1d,0xce,0x9c,0xbd,0x9c,0x90,0x94,0xdc,0xdc,0xd2,0x32,0x30,
+  0x38,0x52,0x59,0x5d,0x2b,0xce,0x2f,0x86,0x0f,0x0d,0x80,0x4c,0x01,0x16,0x5f,0x38,
+  0xdb,0x66,0x09,0x73,0xb3,0x45,0x50,0x85,0xf3,0x73,0xf2,0x0a,0x73,0xc5,0xc5,0x70,
+  0x65,0x22,0x10,0x89,0x01,0xb2,0x84,0x79,0x50,0x85,0xab,0x6b,0xeb,0xfa,0x07,0x07,
+  0x3b,0x3a,0xbb,0x12,0x93,0xd2,0x2e,0x5c,0x74,0x44,0xe9,0xd4,0x84,0xc3,0x27,0x40,
+  0x16,0xb5,0x88,0xd1,0x07,0xc7,0x61,0xe4,0x38,0xea,0xc0,0xce,0x82,0x26,0x9c,0xe1,
+  0x2e,0x2e,0x6e,0x3d,0x7d,0xfd,0xc4,0xba,0x7e,0x72,0xef,0xca,0x40,0x5f,0xbf,0x9a,
+  0x58,0xda,0x4f,0xad,0x66,0x0d,0xc7,0x2e,0x38,0x27,0x33,0x5b,0x40,0xac,0x3b,0x01,
+  0x86,0x50,0xfe,0x87,0x18,0xe6,0xe0,0x87,0xe3,0x38,0x8e,0x6c,0x4f,0x10,0xa1,0x27,
+  0x39,0x4d,0x50,0xb7,0x23,0xc7,0x4e,0x7c,0x78,0xa6,0x5c,0xae,0xc4,0x4b,0xaf,0x5e,
+  0xc6,0xb1,0x0c,0xe7,0xde,0x41,0x4b,0x59,0xe0,0xe4,0x81,0x5e,0x94,0x68,0xa1,0x86,
+  0x99,0x86,0x99,0xed,0xeb,0xe3,0x85,0x06,0xf4,0xe7,0xa9,0x8a,0x69,0x40,0x68,0xfa,
+  0x21,0x29,0xd4,0xc3,0x23,0x2e,0xae,0xee,0x54,0x37,0x50,0x1b,0x10,0x9e,0xce,0x5c,
+  0x0e,0xa0,0xce,0xac,0xc7,0xd0,0x45,0x00,0x18,0xbb,0x23,0x27,0x69,0x7b,0x88,0xa5,
+  0xe4,0xec,0x3a,0x70,0x08,0xdc,0x78,0xe2,0xb2,0xa3,0x53,0x1f,0xba,0x4e,0xdd,0xd3,
+  0xdb,0xd3,0xdd,0x63,0x61,0x45,0x0f,0x63,0x02,0xf1,0xed,0x00,0xa8,0xd4,0x3f,0x3c,
+  0x32,0x2e,0xc8,0xc9,0x39,0x7a,0xec,0x03,0x2a,0x91,0x1f,0x14,0x0a,0x6c,0x9e,0x80,
+  0xf4,0x13,0x90,0xae,0x0a,0x55,0x85,0x7a,0x68,0xb4,0xa7,0xaf,0xb7,0xa7,0x77,0x80,
+  0x58,0x04,0x86,0x0f,0xd1,0xf4,0xa6,0x6c,0x41,0x22,0xe4,0x7c,0x77,0x4f,0x7f,0xff,
+  0xe0,0x30,0x54,0x9a,0x8f,0xcf,0x5e,0x00,0x3f,0x1f,0x3e,0x42,0x93,0x90,0x4b,0x06,
+  0xb3,0x20,0x38,0xcf,0xaa,0x87,0x60,0xcb,0xf4,0xf7,0xf6,0xa9,0xf1,0xae,0xc5,0xde,
+  0x1e,0x1a,0x6e,0xf4,0x1e,0x2f,0x0a,0x2c,0x0c,0x90,0xbb,0x98,0xcc,0xbb,0xc0,0xa2,
+  0x65,0xa3,0xc0,0xee,0xb8,0x81,0x5e,0x42,0x4c,0xa1,0x7f,0x60,0xe0,0xba,0x8b,0xfb,
+  0x61,0x1b,0xa7,0xb1,0x1e,0x3e,0x26,0x10,0x8a,0x46,0xc6,0xc6,0x30,0x52,0x7d,0xe6,
+  0x6d,0xc5,0x77,0x1d,0xb7,0xef,0xac,0x92,0xd0,0xaa,0xcb,0x53,0x89,0xa6,0x44,0x2f,
+  0x86,0x63,0x60,0x00,0x2e,0xba,0x2a,0xab,0x6a,0x93,0x53,0xd2,0xdc,0x3c,0x7c,0x3e,
+  0xf8,0xf0,0xf4,0x21,0x46,0x01,0xd8,0xfb,0xf8,0x21,0x60,0xf6,0x36,0x93,0xc0,0x27,
+  0x6c,0xe3,0xcb,0xb9,0x0e,0xa2,0x4c,0xf3,0x99,0xd9,0x56,0x87,0x8f,0x1d,0x80,0x1d,
+  0x74,0xe4,0x24,0x03,0x87,0x4f,0x1c,0x3c,0x72,0xfc,0xc0,0xe1,0x23,0x07,0x0e,0x1f,
+  0x3d,0x48,0xf2,0xfc,0xd0,0x59,0xf7,0x63,0x49,0x63,0xc7,0xd3,0xf0,0x1b,0xd1,0x13,
+  0x14,0x32,0xe6,0x68,0x17,0x6a,0x07,0x20,0xff,0xf3,0x96,0xf3,0xba,0x07,0xbe,0xf1,
+  0xb5,0x6f,0x7c,0x7b,0xe3,0x87,0xb1,0xc7,0xd2,0xe7,0x76,0xfb,0xd7,0xfd,0xf0,0xd1,
+  0x67,0xbf,0xf9,0xbd,0x9f,0x3f,0xf8,0xbd,0xff,0xfc,0xd6,0xf7,0xfe,0xe3,0xdb,0xdf,
+  0xfb,0x31,0x41,0xfe,0xfd,0x1f,0x7f,0xf0,0xd0,0xbf,0x3d,0xfa,0xe4,0x73,0x07,0x7d,
+  0xde,0x8b,0x1a,0x3e,0x96,0x30,0xf6,0xcb,0xe7,0xdf,0x5d,0x77,0xff,0x03,0xdf,0xf9,
+  0xc1,0xcf,0x5e,0x75,0x55,0x1c,0x4f,0x9f,0x07,0x56,0x94,0x1b,0xb6,0xe9,0x00,0x73,
+  0x20,0xe8,0x78,0xda,0x1c,0x42,0xfa,0xfc,0x09,0x02,0x47,0xd3,0xf4,0x30,0x7b,0x8c,
+  0x10,0x03,0x25,0xab,0x06,0xd3,0x3d,0x46,0x97,0xa4,0xb3,0x4c,0xd2,0x0c,0x74,0x96,
+  0xea,0x4c,0xba,0x66,0x56,0x88,0x67,0xcc,0x1d,0x63,0xbb,0xb0,0xf6,0x78,0x3a,0x99,
+  0xcd,0x98,0x3f,0x96,0x36,0x4f,0x38,0xcf,0xb1,0x38,0x76,0x8f,0xf1,0xcc,0x67,0x39,
+  0xb3,0xde,0xa0,0x0c,0xd9,0x71,0x18,0x39,0x96,0xca,0x9f,0x65,0xbe,0x4c,0xa6,0x5a,
+  0x51,0x38,0x9d,0x8d,0xd5,0xf6,0x9c,0x10,0xef,0xaa,0xba,0x90,0x63,0x70,0xc8,0x35,
+  0x38,0x88,0x99,0x1b,0xab,0x3c,0x8a,0x16,0xfc,0x4a,0x17,0x03,0x64,0x4b,0xb7,0x54,
+  0x2b,0x00,0x51,0xd5,0xc6,0x98,0x1a,0x53,0x5c,0x9d,0x31,0xbe,0xce,0x98,0xda,0xb8,
+  0x94,0xda,0x64,0x8c,0xab,0x5e,0x89,0x54,0xce,0x05,0x95,0xeb,0xa2,0xe4,0x93,0x63,
+  0xfa,0x4f,0x7e,0x84,0xef,0x3d,0x01,0xf3,0x0b,0x0b,0x91,0x31,0xb1,0xaf,0xbf,0xb9,
+  0xfb,0xc0,0xc1,0xc3,0x50,0x02,0xbc,0x7c,0x82,0xa2,0x62,0x12,0xa1,0x70,0x94,0x41,
+  0x09,0xae,0xc7,0xfb,0x86,0xfb,0x06,0xd4,0x93,0x53,0xcc,0x17,0xd1,0xfc,0x53,0x30,
+  0x94,0x60,0x28,0xca,0x70,0x16,0x86,0xb9,0xb1,0x89,0xe9,0xa1,0x91,0xf1,0xbe,0x81,
+  0x61,0x52,0x85,0xbb,0x1b,0x1a,0x5b,0xaa,0x6b,0x1a,0xa4,0xb2,0x8a,0xe2,0xd2,0x72,
+  0x71,0x7e,0x89,0x20,0x47,0x02,0x97,0xb5,0x70,0x36,0x8c,0x89,0x4b,0x0e,0x8b,0x8c,
+  0x09,0x09,0x8d,0x0c,0xb8,0x11,0xea,0x17,0x18,0x1c,0x78,0x23,0xe4,0x56,0x48,0x74,
+  0x50,0x70,0x58,0x00,0x9c,0x91,0x03,0x6f,0x06,0xdc,0xb8,0xe9,0x1b,0x70,0xd3,0xd7,
+  0xff,0xa6,0xaf,0xdf,0x0d,0x1f,0xbf,0x20,0x0f,0xdf,0x00,0x6f,0xdf,0x40,0x77,0x6f,
+  0x5f,0x0f,0x1f,0x7f,0x68,0x01,0x2e,0x39,0x38,0x02,0x5c,0xb8,0xe8,0x70,0xf1,0xd2,
+  0x95,0x4b,0x97,0x29,0x7e,0xe5,0xe2,0x25,0x47,0x80,0x4b,0x0e,0x57,0xf0,0x2d,0x09,
+  0x97,0xb0,0x7b,0xd9,0xc1,0x09,0xba,0x1e,0xee,0xfe,0x74,0xad,0x17,0x01,0xca,0x04,
+  0x10,0x6f,0x5f,0x7f,0x8e,0x27,0x76,0x01,0xf1,0xf2,0x85,0xeb,0x01,0xe4,0xe9,0xe0,
+  0x04,0xed,0xe5,0x2b,0x0c,0x43,0x22,0x08,0xc5,0x01,0xce,0x75,0x39,0x41,0x97,0x2e,
+  0x5f,0x61,0x95,0x71,0x72,0xbc,0xea,0x12,0x19,0x13,0xaf,0xaa,0xac,0xee,0xc5,0x3b,
+  0x8e,0x47,0xda,0x3b,0x3a,0x6b,0x1b,0xea,0xe5,0xca,0x6a,0xf0,0x61,0x49,0xa9,0xac,
+  0xa8,0x44,0x06,0x6d,0x69,0x99,0xac,0x4c,0xaa,0x50,0x56,0x54,0xd5,0xd4,0xd6,0xb7,
+  0x77,0x74,0x41,0xbd,0x1e,0x1a,0x1e,0x52,0x56,0xd4,0xc6,0x26,0x24,0x5e,0xbd,0xe6,
+  0x02,0x7c,0xcc,0xe2,0x2e,0xa3,0x0e,0x97,0x2e,0x3b,0x71,0x5d,0x2a,0x17,0x46,0xd0,
+  0x6a,0x94,0xcb,0xe8,0x73,0xf9,0xca,0x55,0xaa,0x1e,0xb1,0xfa,0x9a,0x9b,0xa7,0x9f,
+  0x97,0x6f,0x80,0x97,0xb7,0xbf,0x97,0xb7,0x9f,0xa7,0x8f,0x9f,0xa7,0xb7,0x9f,0x17,
+  0x9a,0xe9,0x07,0xe0,0x0d,0xe3,0xbe,0x01,0x68,0xb8,0x17,0x1a,0xee,0xed,0x13,0xe0,
+  0x74,0xcd,0x15,0x59,0x5d,0x76,0x74,0x70,0x44,0x26,0x17,0x2e,0x51,0xb9,0x57,0xa9,
+  0xa0,0x8b,0x97,0xaf,0x70,0x82,0x38,0xc7,0x5e,0xbc,0x8c,0x0e,0x47,0xb9,0x0e,0x8e,
+  0xce,0x2e,0x1e,0x94,0x2d,0x08,0xf2,0x40,0x60,0xfc,0x89,0xae,0x26,0x08,0x1d,0xa1,
+  0xb3,0x5e,0x84,0xcc,0xcb,0x3b,0x00,0xe4,0x7a,0xf9,0x50,0x0d,0x03,0x18,0xf5,0xbc,
+  0x7c,0x3d,0xbc,0xfd,0x19,0xad,0x7c,0x03,0x3d,0xc8,0x42,0x0f,0xa2,0x3c,0x8d,0x3e,
+  0xb2,0xf2,0xc2,0xe8,0xfb,0x80,0xfe,0x5e,0xbe,0x97,0x1d,0xae,0x5a,0x79,0x83,0xea,
+  0x0c,0x8a,0x61,0x7a,0x10,0x8b,0xcc,0xae,0x73,0xa0,0x34,0x8e,0xb4,0x4b,0x5a,0xa4,
+  0xa4,0x19,0x42,0x1d,0x4b,0x3c,0xec,0x04,0x0e,0xbf,0x7c,0x05,0x1c,0xe8,0xeb,0xee,
+  0xe3,0xe7,0xed,0x83,0x6a,0x80,0xce,0x68,0x82,0x0f,0xda,0x88,0x26,0x60,0xaa,0x04,
+  0x82,0x02,0xa0,0x39,0xb5,0xf7,0xda,0x75,0x77,0xe2,0x25,0x3b,0xbe,0x82,0x2e,0xfa,
+  0xd3,0x81,0x4b,0x4e,0x70,0x97,0x27,0xba,0xcb,0x27,0x90,0x66,0x32,0xe3,0x2e,0x5f,
+  0x74,0x02,0xd8,0xe5,0x41,0x62,0x44,0x42,0x86,0x31,0xba,0xee,0x0a,0x9c,0x9d,0x88,
+  0x15,0x4c,0x4e,0x02,0x07,0xe4,0xcc,0x13,0xe4,0x74,0xcd,0xd9,0x0b,0xd4,0xf0,0x06,
+  0x0d,0xfd,0xdd,0x30,0xa0,0x16,0xbe,0x02,0xb6,0x8c,0xce,0xbe,0x18,0x11,0xda,0xa5,
+  0xbe,0xc5,0xae,0x0f,0x33,0xeb,0x41,0x94,0xf1,0xe2,0xf6,0x08,0x5d,0x4b,0x33,0xc7,
+  0x9b,0xd9,0x35,0x1e,0x9e,0xde,0x0e,0x8e,0x4e,0xd4,0x0a,0x7e,0x6e,0x70,0x2e,0xbd,
+  0xea,0xec,0xea,0x45,0xf8,0x13,0x5f,0x05,0xb2,0xac,0x30,0xb2,0x14,0xa7,0x22,0x08,
+  0x67,0x10,0xcd,0x76,0xbd,0x30,0xa0,0x54,0x2b,0x26,0x0d,0x68,0xe6,0x78,0x33,0xca,
+  0xf8,0x40,0x32,0x78,0xfb,0xb9,0xb9,0x7b,0xc0,0xe6,0xe2,0xb6,0x24,0xb7,0x17,0x78,
+  0x5d,0x6e,0x1b,0x3a,0x92,0xdc,0xa0,0xf9,0x69,0x19,0x5f,0x07,0x92,0x1b,0xcc,0xee,
+  0x76,0xa2,0x39,0x70,0x89,0x8d,0x1d,0x6f,0xb3,0x63,0xf2,0xa0,0x2c,0x74,0xb2,0xd3,
+  0x25,0x17,0xff,0xb3,0x49,0x5d,0x58,0x20,0x58,0x80,0xaa,0x61,0xd5,0x1e,0x4f,0x18,
+  0xfd,0xf5,0xb3,0xbb,0xf1,0x9b,0xe4,0xef,0xfe,0x78,0xeb,0x47,0xa1,0xe7,0xb2,0x34,
+  0x67,0x52,0xc6,0x3f,0x4a,0x1e,0x39,0x95,0x3e,0x7e,0x3a,0x65,0xe4,0x64,0xf2,0xf4,
+  0x99,0x94,0x51,0xd2,0x9d,0x3c,0x93,0xa5,0xbb,0x22,0x36,0x9c,0x4a,0x1c,0xf8,0xf5,
+  0xb6,0x0f,0xd6,0x3d,0xf0,0xf5,0xaf,0x3c,0xf0,0xb5,0x97,0xcf,0x84,0x5f,0x14,0xe2,
+  0xe0,0x85,0x5c,0xc3,0xf9,0x1c,0x3b,0xfc,0x2f,0x8b,0xb0,0x42,0xc1,0xc1,0xf0,0x62,
+  0x0e,0xc2,0x25,0xd2,0x85,0x41,0x5b,0x35,0xac,0x00,0xb8,0x5d,0xc9,0x63,0x70,0x47,
+  0x91,0x8e,0xd2,0xd0,0xb5,0x80,0x5c,0x14,0x19,0x2e,0x91,0xf6,0x32,0x0c,0x92,0x11,
+  0xab,0xf6,0x32,0x99,0xe5,0x46,0x40,0x43,0x4a,0x0c,0x08,0x5f,0x0a,0x9d,0xb5,0x0b,
+  0x94,0xff,0x05,0x72,0xeb,0x14,0x42,0x1e,0x01,0x52,0x67,0x1d,0x25,0xf8,0x03,0xa2,
+  0xab,0x12,0x83,0x5b,0x11,0x82,0x57,0x09,0xd6,0xdc,0x20,0xd9,0xd2,0x4d,0xc5,0x72,
+  0xb0,0x72,0x39,0xa6,0xda,0x14,0x5d,0x6d,0x4c,0xa8,0x5f,0x4d,0x6e,0x30,0xa5,0x34,
+  0x9a,0x04,0xad,0xcb,0xc2,0x36,0xa3,0xa0,0x75,0x29,0xad,0x69,0x35,0xa9,0x7e,0x25,
+  0xb1,0x66,0x21,0x52,0x31,0x17,0xa6,0xd0,0x8d,0x68,0xbf,0xfc,0xba,0xf9,0x39,0x82,
+  0x46,0xab,0x87,0x6d,0xb4,0x67,0xef,0xbe,0x13,0x27,0x3e,0x84,0x63,0xa9,0x5f,0x40,
+  0x70,0x62,0x4a,0x9a,0x28,0xaf,0xb0,0x5c,0x56,0x51,0xdf,0xd0,0xdc,0xd6,0xd1,0x3b,
+  0x38,0x44,0x1f,0x8a,0x05,0xa7,0x60,0xe6,0x5e,0x2c,0x5a,0x82,0x29,0x0e,0x07,0x61,
+  0xf2,0x03,0x61,0xa8,0xc2,0x53,0x03,0x43,0x70,0x25,0x3c,0xd4,0xd5,0xd3,0xdf,0xd2,
+  0xd6,0x53,0xdf,0xd8,0x5a,0x5d,0xd3,0x04,0x15,0xa7,0xa4,0x54,0x51,0x50,0x54,0x26,
+  0xca,0x2b,0x82,0x73,0x5f,0x5a,0x86,0x20,0x25,0x0d,0xff,0xbc,0x0b,0xb5,0x38,0x32,
+  0x2a,0x2e,0x22,0x2a,0x2e,0x38,0x34,0x32,0xe8,0x56,0x78,0x70,0x48,0x44,0xe0,0x8d,
+  0x5b,0xfe,0x81,0xc1,0x20,0xdd,0xdb,0xff,0x06,0x82,0xdf,0x0d,0x2f,0xbf,0x20,0x2f,
+  0xbf,0x40,0x6f,0xdf,0x20,0x2f,0x9f,0x40,0xfc,0xdc,0xf6,0x0b,0x44,0xf0,0x25,0xe0,
+  0xc3,0x82,0xb9,0x4b,0x3e,0xdb,0xe1,0x33,0xc7,0x3b,0xc8,0xcb,0x0b,0x3e,0xea,0x83,
+  0xb0,0xeb,0x15,0xe8,0xe5,0xcd,0x92,0x51,0x1a,0x4f,0xd2,0x9a,0x97,0x04,0x7a,0xe2,
+  0x47,0x1f,0xe2,0x66,0x41,0xbe,0x41,0x0c,0x37,0x0e,0x21,0x94,0x96,0x82,0x08,0xe2,
+  0x0d,0x48,0x10,0x59,0x7b,0xc3,0xdf,0x2f,0x24,0x3c,0x2a,0x36,0x2b,0x27,0x4f,0x8e,
+  0x3f,0x07,0xee,0x82,0xf3,0x88,0x7a,0x68,0x44,0x3d,0x34,0x4c,0x61,0x68,0x78,0x58,
+  0x3d,0x3c,0x0c,0xa7,0xed,0xf6,0x8e,0x6e,0x55,0x65,0x4d,0xb6,0x40,0x1c,0x1d,0x9b,
+  0xe0,0x1f,0x18,0xe2,0xcd,0xd7,0x9f,0x11,0x47,0xba,0xf0,0x41,0xe4,0x17,0xc8,0xca,
+  0xb5,0x54,0x83,0xd5,0xdc,0x8c,0xfb,0x06,0xc1,0x47,0x37,0x75,0x85,0xa7,0x05,0x01,
+  0x4b,0xe6,0x49,0x5a,0xc6,0x2d,0x3c,0xef,0x79,0x06,0xda,0x61,0xcb,0x57,0x83,0xb3,
+  0xd7,0xcc,0x99,0x25,0xf3,0xb4,0x8c,0x82,0x95,0x67,0xbc,0x78,0x0e,0xf7,0xe5,0xac,
+  0xe3,0xd3,0xb3,0x94,0xbe,0x6c,0xd7,0x8b,0x20,0x74,0xa1,0xa7,0x45,0x8c,0x2c,0x34,
+  0x24,0xf1,0x45,0xf0,0x0e,0xb0,0xb1,0x25,0xd0,0xcc,0x93,0x71,0x8b,0x9f,0x59,0x3d,
+  0x36,0x6d,0xbc,0x39,0x03,0x09,0x19,0x26,0x0c,0x97,0x12,0x5c,0x82,0x79,0xb1,0xdc,
+  0xbc,0x69,0x0a,0x81,0xc4,0x20,0x36,0x49,0x68,0xd0,0x21,0x73,0x7c,0xbd,0xcd,0x46,
+  0x05,0x78,0x59,0xc4,0x28,0x80,0x21,0xb6,0x4a,0x57,0x9e,0x5c,0xb3,0xd5,0x36,0x6e,
+  0x21,0xd1,0xa4,0x82,0xfc,0x2d,0x6c,0xe4,0x04,0xa1,0x07,0xfc,0xbc,0xfd,0x83,0xd0,
+  0x46,0x9f,0xb5,0x7c,0xc5,0x1f,0x21,0xac,0x2c,0xc8,0x02,0xdd,0xe8,0xd6,0x80,0x6b,
+  0x21,0x1f,0xa8,0xfb,0x56,0xcb,0xf9,0x09,0xcf,0x3a,0xc4,0x37,0xc0,0x1c,0x38,0xa2,
+  0x9e,0xa7,0xb7,0xbf,0x05,0x99,0x97,0x65,0x0a,0xb1,0x31,0x42,0x41,0x5c,0xb0,0xbc,
+  0x38,0x13,0xcc,0x3b,0x11,0xc3,0x64,0x65,0x82,0x77,0xa0,0xa7,0x97,0x1f,0xcd,0x58,
+  0x44,0xd8,0x90,0x81,0x4b,0xbd,0x7d,0x03,0xbc,0x7d,0x83,0xac,0xdd,0xc2,0xcb,0x40,
+  0x5e,0x7c,0xf9,0x1b,0xc7,0x9f,0x11,0xc4,0x7a,0x86,0x61,0xc2,0x12,0xbb,0x99,0x3d,
+  0x10,0xe8,0x15,0x70,0xd3,0x33,0xb9,0xca,0xbd,0x68,0xce,0xb3,0x68,0xc1,0xb5,0xd0,
+  0x00,0xad,0x5d,0x70,0x2f,0x34,0x7c,0x18,0x5e,0xf3,0xd0,0x2f,0x9f,0x58,0x77,0xdf,
+  0x03,0x0f,0x7e,0xfb,0x7b,0x5b,0x8f,0xf9,0x9e,0x4d,0xee,0xb9,0x56,0xa0,0xf7,0x28,
+  0x59,0x70,0x29,0xc6,0x55,0x50,0x5f,0xbc,0x8a,0x17,0xdc,0x8b,0x16,0x1c,0x45,0x9a,
+  0x23,0x37,0x15,0xbf,0x7d,0xf1,0xdd,0xaf,0x7c,0xf5,0x9b,0x5f,0xff,0xfa,0xb7,0x9e,
+  0xdc,0x7e,0xc8,0x39,0x6f,0xca,0xb3,0x78,0xc1,0x8d,0xd0,0x00,0xb2,0x96,0x88,0x3b,
+  0x04,0x37,0x16,0xf1,0x28,0x24,0xdc,0x8a,0x2d,0xa6,0xdc,0x59,0x1c,0x6d,0x29,0x5e,
+  0x70,0x2d,0xc2,0x9b,0x9a,0xe0,0xbc,0xe9,0x45,0xc8,0xdc,0x88,0xaa,0x5c,0x0b,0xe3,
+  0xee,0x64,0x9c,0x9b,0xf5,0x62,0xbb,0x6e,0x45,0x0c,0xd0,0x71,0xae,0x0b,0x6c,0x01,
+  0xcc,0xb3,0x44,0x01,0xba,0xd0,0xab,0x98,0xe9,0x02,0xe2,0x0d,0xd5,0x56,0xba,0xe4,
+  0x5b,0xbe,0xe4,0x2f,0x5d,0x0a,0x90,0x2e,0x85,0x28,0x96,0xc2,0x94,0xab,0xe1,0xaa,
+  0x55,0xa8,0xb9,0x31,0xd5,0xc6,0xd4,0x86,0x65,0xa8,0xb9,0x19,0xcd,0x50,0x76,0xa1,
+  0xe6,0x2e,0x8a,0xdb,0x57,0xc5,0x1d,0xc6,0x9c,0xb6,0x25,0x61,0xbb,0x31,0xb3,0xd9,
+  0x90,0x54,0xbf,0x14,0x53,0x31,0x17,0xa9,0x9a,0xab,0x1e,0x5c,0xb8,0x87,0x9e,0x76,
+  0x75,0x87,0xa0,0x1e,0x1a,0xba,0x70,0xf9,0xca,0xde,0x7d,0xef,0x9c,0xfc,0xf0,0xb4,
+  0xe3,0x35,0x97,0xc0,0xe0,0xf0,0xc4,0xe4,0xb4,0x5c,0x71,0xb1,0x54,0x51,0x55,0xdb,
+  0xd0,0xd8,0xd9,0x3d,0xd8,0xaf,0x1e,0x1f,0x9b,0xc4,0x2f,0xa2,0xb5,0x3a,0xfa,0xcc,
+  0x0a,0xf3,0x77,0xd1,0xe4,0xd6,0x68,0x1d,0xf9,0xa3,0x30,0xbe,0xd9,0x64,0x74,0x7c,
+  0x42,0x3d,0x3c,0x36,0xa0,0x1e,0xe9,0xec,0x1e,0x68,0xeb,0xec,0x6e,0x6e,0xed,0xac,
+  0x6f,0x6c,0xae,0xaa,0x6d,0x54,0xaa,0xf0,0xe7,0x0f,0xa5,0xe5,0xf2,0x82,0x22,0xfc,
+  0x29,0x81,0x50,0x94,0x9f,0x2d,0x14,0xa7,0x65,0xe6,0xa4,0xa6,0x0b,0x53,0xd2,0xb2,
+  0x92,0x52,0xd2,0xc8,0x9d,0x2d,0x29,0x31,0x71,0x29,0xb1,0xf1,0x29,0xd1,0xb1,0xc9,
+  0x51,0x00,0x31,0x49,0xd1,0xb1,0x29,0x51,0xb1,0x49,0x80,0x20,0xc4,0x26,0x93,0x71,
+  0x32,0x48,0xba,0x91,0x31,0x09,0x14,0x28,0x31,0x19,0x64,0xc6,0x01,0x8f,0x8c,0x66,
+  0xa7,0xe8,0x08,0xaf,0xe5,0x77,0xcd,0x23,0xdc,0x20,0xb2,0x4a,0x24,0x48,0x22,0xc3,
+  0x16,0x90,0xd8,0x24,0xbc,0xa1,0x8b,0x21,0x48,0x24,0x5a,0x25,0x46,0x46,0xb3,0x23,
+  0x64,0x36,0x26,0x9e,0x72,0x4b,0x04,0x13,0xc0,0x9c,0xd4,0x74,0x41,0x96,0x20,0x57,
+  0x20,0xca,0x15,0xe4,0xe4,0x66,0x66,0x8b,0x92,0xd3,0xb2,0x12,0x93,0xd3,0xc1,0xc0,
+  0xe8,0xb8,0x04,0xc2,0x3f,0xde,0x5a,0x19,0x9e,0x09,0xec,0x14,0x23,0x88,0x55,0x83,
+  0x67,0x20,0x75,0x11,0xeb,0x1c,0xce,0x15,0xb6,0x96,0x5a,0x4d,0x31,0xe3,0x51,0x09,
+  0x1c,0x2b,0x76,0x9c,0x31,0xd0,0x46,0x8d,0x78,0xea,0x0d,0x4b,0x55,0xad,0x19,0x52,
+  0x25,0xad,0x3c,0x6c,0xe5,0x49,0xce,0x22,0x3e,0x2b,0xbb,0x4a,0xda,0x1a,0x62,0x25,
+  0x88,0x70,0x8b,0xb7,0xf6,0x55,0x34,0xdf,0x15,0x89,0x56,0x06,0xda,0xb4,0x68,0x2f,
+  0xdf,0x96,0xb5,0xc0,0x42,0x2e,0x89,0x2f,0x08,0x8a,0x64,0xbb,0xfc,0x28,0x30,0xa9,
+  0x12,0x63,0x11,0x5f,0x86,0x38,0x36,0x39,0x22,0x2a,0x9e,0x6f,0xfe,0x5a,0xde,0xa0,
+  0x94,0xb7,0x0f,0x37,0xe3,0x81,0xe8,0x04,0xce,0x5e,0x5b,0x5f,0xd9,0x06,0xd4,0x92,
+  0x80,0xaf,0x55,0x82,0x45,0x7a,0xaf,0xed,0x76,0x7b,0x39,0x99,0x68,0xe9,0x2e,0x7b,
+  0x19,0x4b,0x76,0x0a,0xab,0xa7,0x79,0x3b,0x5b,0xa7,0x90,0xdd,0x1d,0xca,0xc5,0x9a,
+  0xf5,0x46,0x74,0xbc,0x85,0x81,0xfc,0x80,0xb2,0x42,0x13,0x58,0x8b,0xe2,0xa3,0x2c,
+  0x37,0x8e,0x65,0x4e,0xf2,0xf5,0x64,0xb6,0x03,0xde,0xbe,0x18,0x97,0x12,0x92,0x5d,
+  0x15,0xa2,0x5c,0x8a,0x50,0x1a,0x6e,0x29,0xf0,0xe6,0x9f,0x10,0xd5,0x2a,0x03,0xca,
+  0x15,0x04,0xb6,0x1b,0x0a,0x53,0x8a,0xe5,0x4b,0x31,0x35,0x8f,0x3d,0xb1,0xfe,0x81,
+  0xfb,0x1e,0x78,0x60,0xdd,0x57,0x1f,0xfa,0xd5,0xe3,0xaf,0x9f,0xf4,0xbe,0x10,0x26,
+  0xbf,0x2e,0x18,0xf6,0x2d,0x9c,0xf2,0x92,0x4c,0x5e,0x4b,0xef,0x3d,0xe6,0x23,0x7a,
+  0xe1,0xad,0xd3,0xff,0xf2,0xfd,0xff,0xb8,0xef,0x1f,0xd6,0x7d,0xed,0xeb,0x0f,0x6e,
+  0xdd,0xfb,0xb1,0xa7,0x64,0x92,0xb2,0xa5,0xfc,0xf9,0x22,0x42,0xed,0x09,0xba,0x4d,
+  0x97,0x2e,0x8f,0xa8,0x40,0x84,0x8e,0x73,0x0c,0x43,0x2b,0x56,0xad,0xc8,0xf8,0x88,
+  0x15,0x31,0xd7,0xa5,0x34,0x76,0x67,0x81,0x21,0xf2,0xa4,0x04,0x96,0x3c,0xa1,0x0d,
+  0x92,0x2f,0x73,0xe6,0xf0,0x81,0xaa,0x01,0x1a,0x46,0x54,0x02,0x18,0xa3,0xab,0x10,
+  0xa0,0xe0,0x26,0xd5,0x2d,0xa5,0x36,0x99,0xd2,0x9a,0x56,0x32,0x9a,0x8d,0xa2,0xd6,
+  0x15,0x51,0x9b,0x29,0xaf,0x7d,0xb5,0xb0,0xcb,0x98,0xdf,0x6d,0x2a,0xe9,0x31,0x15,
+  0xf7,0x98,0xf2,0x3b,0x8d,0x79,0x9d,0xc6,0x9c,0x56,0xa8,0xcb,0xcb,0x09,0xd5,0x0b,
+  0xe1,0xca,0x45,0x55,0xef,0xea,0xf2,0xbd,0xf0,0x9e,0xc1,0xbb,0x05,0xe3,0xff,0x35,
+  0xb6,0xb6,0x77,0x1c,0x3f,0xfe,0xc1,0xbb,0xfb,0x0f,0x7c,0xf0,0xd1,0x99,0x6b,0x2e,
+  0x1e,0x81,0xb7,0xa0,0x04,0xa7,0xe7,0x8a,0x8b,0xe0,0x14,0x5c,0x5b,0xdf,0xd0,0xda,
+  0xde,0x83,0xcf,0x6d,0x18,0x9f,0x9a,0x9a,0x86,0x53,0x30,0x79,0x30,0xd0,0xfc,0x3c,
+  0xbf,0x0a,0x03,0x40,0x15,0xd6,0x68,0x75,0x70,0x16,0x9e,0x9a,0xd6,0x8e,0x8e,0x4f,
+  0x0e,0x8f,0x8e,0x91,0xd7,0x27,0xf5,0x77,0xf7,0xf6,0xc1,0x21,0xba,0xa9,0xa5,0xbd,
+  0xae,0xa1,0xad,0xa6,0xb6,0x5e,0x55,0x59,0xaf,0xac,0xa8,0x96,0x29,0x94,0x65,0xe5,
+  0xca,0x92,0x72,0x79,0x71,0xa9,0x54,0x52,0x50,0x9a,0x5f,0x50,0x2c,0x96,0x14,0xe7,
+  0x8a,0x0b,0xe1,0xdc,0x2d,0xcc,0x15,0x0b,0x73,0x25,0x39,0xb9,0xf9,0x82,0x9c,0xbc,
+  0xec,0x1c,0xb1,0x50,0x24,0x16,0xe5,0x61,0xb1,0x86,0x71,0x41,0x0e,0x82,0x30,0x97,
+  0x8e,0xe7,0x01,0xb0,0x23,0xe2,0x6c,0x82,0x64,0x0b,0xf3,0x04,0x22,0x32,0x4b,0x68,
+  0xb0,0x9b,0x23,0xce,0x12,0x88,0xe9,0x5f,0x5d,0x85,0xa4,0xcd,0xc9,0x2d,0xa0,0x9c,
+  0x05,0x84,0x09,0x19,0x97,0x08,0x72,0x24,0xd0,0x66,0x09,0xb0,0x4b,0x56,0x41,0x37,
+  0x9f,0xe0,0xb0,0x04,0xbb,0xa0,0x0f,0x8c,0x13,0xad,0x80,0x58,0x9c,0x93,0x57,0x80,
+  0x1c,0x44,0xa8,0x6a,0xb6,0x50,0x22,0x60,0xa4,0x8b,0x29,0x67,0x10,0x81,0xd2,0x09,
+  0x01,0x0c,0x66,0xe7,0x10,0x0e,0x79,0x05,0xa8,0x09,0x0a,0x45,0x73,0xa8,0x81,0x22,
+  0x1c,0xcc,0xa3,0xe3,0x84,0x3e,0x8f,0xf2,0xa1,0xea,0x31,0x20,0xa2,0x7c,0xf2,0xa8,
+  0x39,0xb4,0xcb,0x20,0x66,0x1a,0x9c,0x42,0x9e,0x38,0x2b,0x41,0x27,0x10,0x62,0xa1,
+  0xa8,0x80,0xf8,0x07,0x34,0xcc,0x47,0x07,0xd2,0x71,0x11,0xd5,0x30,0x8f,0xf5,0x86,
+  0x7d,0x41,0xe8,0x55,0x62,0x32,0x75,0x02,0x8d,0x05,0x99,0x25,0x1e,0x13,0x81,0x63,
+  0xf3,0x72,0xf2,0xc4,0xac,0x2d,0x12,0xc6,0x52,0xe4,0x99,0x9f,0xcd,0x06,0x85,0xf2,
+  0x67,0x14,0xa3,0x6e,0x27,0xac,0xd8,0x08,0xe6,0x53,0xd1,0xd4,0x63,0x8c,0x32,0x18,
+  0xf1,0x82,0x6c,0x7b,0x5a,0x51,0x13,0x04,0xf8,0xb7,0xf5,0x7c,0xe2,0x46,0x26,0xbe,
+  0x64,0x9c,0xcf,0x59,0x42,0xc3,0xc4,0x31,0xe7,0x3c,0x46,0xe5,0x42,0xc8,0x70,0x39,
+  0xe1,0x93,0x2d,0xcc,0x25,0x16,0x15,0xb0,0xa6,0x59,0x68,0xc5,0x86,0x8c,0xf1,0x12,
+  0x2c,0x01,0x1a,0x9a,0x90,0x34,0xc1,0xf8,0xbe,0x22,0x6b,0x25,0xd4,0x39,0xd6,0x9e,
+  0x44,0x59,0x12,0x22,0x17,0xf9,0xa0,0x81,0x42,0xd6,0x1b,0x42,0x92,0x45,0x9c,0xa5,
+  0x39,0xe2,0x5c,0x71,0x01,0xe1,0xc6,0xa4,0x28,0x97,0x57,0x44,0x07,0xde,0x2a,0x91,
+  0x84,0x4d,0x15,0x9a,0xf3,0x94,0x83,0x84,0x28,0x99,0xc7,0x0f,0x2b,0x3f,0x46,0xe8,
+  0x40,0xd4,0x13,0xe9,0x61,0x90,0xf8,0x2a,0x9f,0xba,0x4e,0xc0,0xd8,0x8e,0xb9,0x4a,
+  0x39,0xb3,0xd2,0x99,0x9d,0xc2,0xe8,0x6c,0x56,0x00,0xe9,0x99,0x0c,0x21,0x9e,0xcf,
+  0xe6,0xfb,0x1c,0xd3,0x9e,0x31,0x9f,0xda,0x0b,0xba,0x91,0x5d,0x4c,0x93,0x90,0xee,
+  0x26,0x76,0xf3,0xd2,0xbd,0xc6,0x25,0x83,0x90,0xb3,0x88,0xc4,0x5d,0x44,0xf3,0x87,
+  0x11,0x41,0x73,0x98,0x68,0x45,0xf7,0x29,0x7f,0xc3,0xd2,0x8c,0x35,0xef,0x5f,0x9a,
+  0x93,0x6c,0xcb,0x24,0x09,0xbb,0x91,0x25,0xac,0x21,0x6c,0x32,0xe4,0xe4,0xa5,0x17,
+  0xd6,0xa6,0xd4,0xce,0x27,0xd6,0x9b,0x92,0xea,0x8d,0xc9,0x8d,0xab,0x49,0x0d,0x46,
+  0xc0,0x29,0x24,0x10,0x30,0x77,0xeb,0x8c,0x09,0xa4,0x0d,0x12,0x75,0xec,0x78,0xff,
+  0xdc,0x3f,0x7d,0xef,0x87,0x70,0x10,0xfe,0xca,0x57,0xbe,0xfe,0x9d,0xef,0xfc,0xeb,
+  0x4f,0x7f,0xf6,0xe8,0x4f,0x1e,0xf9,0xc3,0xcf,0x1f,0xfd,0xdd,0x0f,0x7e,0xf2,0xd0,
+  0x37,0x1f,0xfc,0xce,0xba,0x75,0x5f,0xf9,0xca,0x57,0xbf,0xf1,0xd0,0x23,0xbf,0x3f,
+  0x7e,0x2d,0x22,0x42,0xaa,0x49,0x6b,0x5a,0x86,0x85,0xc0,0x39,0xbd,0x11,0x11,0xe8,
+  0x26,0xf2,0xd8,0xda,0x11,0xb4,0x76,0x97,0xbf,0x9c,0x0e,0x52,0x9d,0x93,0x2c,0x67,
+  0x53,0x1b,0x57,0x12,0x89,0x21,0xd8,0x6d,0x30,0xa6,0x36,0xad,0x24,0x70,0xb3,0x6c,
+  0x97,0x6a,0x45,0x5b,0x0a,0x9c,0xf9,0x74,0x90,0x53,0x80,0xf2,0xe4,0xd4,0x00,0x9a,
+  0x94,0xc6,0xd5,0x54,0x62,0x4b,0x4a,0xfd,0x52,0x7c,0xed,0x2a,0xe7,0x1c,0x90,0x0b,
+  0xb3,0x80,0xa4,0x37,0xc1,0x31,0x16,0xab,0xad,0xb0,0xd5,0x28,0x6c,0x35,0x09,0xda,
+  0x4c,0xa2,0x76,0x93,0xa4,0xc3,0x24,0xe9,0x36,0x42,0xa9,0x2d,0xeb,0x35,0x96,0xf5,
+  0x9a,0x64,0xfd,0x26,0x69,0x9f,0xa9,0xbc,0x0f,0xdb,0xa2,0x1e,0x93,0xa4,0xcb,0x94,
+  0xd7,0xb6,0x22,0x68,0x5d,0x49,0xac,0x5d,0x8c,0x52,0xe9,0x4b,0xba,0x16,0x0d,0xf7,
+  0xce,0x7b,0x16,0xee,0x16,0x56,0x4d,0xab,0x32,0xb9,0xe2,0x9d,0x77,0x0f,0xec,0x7b,
+  0xe7,0xe0,0x99,0xb3,0x17,0x5c,0xdc,0xbc,0x6f,0x86,0x86,0x27,0xa5,0x64,0xc0,0x29,
+  0xb8,0x54,0xaa,0xac,0xa9,0x6b,0x69,0xeb,0xec,0xe9,0x85,0x63,0xed,0xd8,0x14,0x7d,
+  0x41,0x03,0x3e,0xc5,0x51,0xaf,0xb7,0x2a,0xc1,0x70,0x30,0x26,0x8f,0xac,0xd4,0x92,
+  0xbb,0xb3,0x66,0xc9,0x1b,0x0c,0x47,0xa0,0x0a,0x0f,0x0e,0x8d,0xf6,0x0d,0xa8,0xbb,
+  0x7a,0xd4,0xed,0x9d,0xdd,0xed,0xf8,0x28,0x9b,0xae,0xc6,0xa6,0xb6,0xba,0x86,0xd6,
+  0xea,0xda,0xfa,0xaa,0x9a,0x86,0x4a,0xf2,0x93,0x1c,0xa5,0xaa,0x56,0xa5,0xc2,0x1f,
+  0xdd,0x2b,0x54,0x95,0x52,0x7c,0x14,0x43,0xa5,0x4c,0x21,0x97,0xca,0x95,0x00,0xe5,
+  0x72,0x39,0xfe,0x5a,0x5f,0x26,0x23,0xc0,0x74,0xcb,0x64,0x52,0x80,0x72,0x99,0x1c,
+  0x46,0xa4,0x0a,0x65,0x69,0x39,0x99,0x95,0x2b,0xe4,0x0a,0x45,0x99,0x54,0x8e,0xb3,
+  0x52,0x05,0xe9,0x2a,0x71,0x09,0x5d,0x28,0x83,0x71,0x98,0x55,0x92,0x85,0x2a,0x5c,
+  0xcb,0xb2,0x82,0x59,0xb9,0x42,0x25,0x95,0xc9,0x41,0x6e,0x69,0x39,0xce,0xc2,0x72,
+  0x20,0x96,0xe2,0x23,0x2c,0xa4,0xe4,0xb1,0x00,0x0a,0xa0,0x07,0x02,0x64,0x2b,0xa3,
+  0x3c,0x51,0xae,0x14,0x15,0x40,0x3d,0xc9,0x78,0x05,0x61,0x58,0x51,0x8e,0x7c,0x80,
+  0x40,0x05,0x5a,0x95,0x49,0x65,0x32,0x5c,0x5b,0x21,0x67,0x95,0x24,0x94,0x0c,0x67,
+  0x54,0x15,0x04,0x11,0x55,0xd1,0x52,0x62,0x0e,0x37,0x42,0x65,0x41,0x4b,0x95,0xa4,
+  0x04,0x44,0xab,0x4a,0x86,0x46,0x46,0xfc,0x83,0x34,0x52,0xb4,0x8b,0xd1,0xad,0xa2,
+  0x0c,0x69,0xa1,0xcb,0x39,0x87,0x5a,0x84,0x5a,0x11,0x1a,0x19,0x27,0x05,0xac,0xb6,
+  0x75,0x0e,0x27,0x08,0x57,0xc9,0x2c,0xbc,0x41,0xed,0xa5,0x0b,0x29,0x2b,0x30,0x90,
+  0xa8,0x2a,0x27,0x16,0xc1,0x94,0x92,0xf8,0x4a,0xc6,0x2a,0x46,0x65,0xc9,0xcd,0x6e,
+  0x67,0xec,0x52,0x41,0x7c,0xa9,0xbd,0x7c,0x7d,0x28,0x31,0xd0,0x80,0xaf,0xa4,0x0a,
+  0xbe,0xbd,0x72,0x6a,0x8e,0x4c,0x01,0x5d,0x05,0x55,0xc3,0x2a,0xbe,0x2c,0x07,0xd4,
+  0x99,0x58,0x2a,0xe7,0x22,0x45,0x81,0xb8,0x48,0xc9,0x59,0x04,0x1c,0x64,0x0a,0xc6,
+  0x22,0x7e,0x5e,0xb1,0x5e,0x85,0xd9,0x0a,0xf3,0x72,0x39,0x89,0x11,0xe6,0x80,0x92,
+  0x04,0x8b,0x11,0x64,0xdf,0x57,0x52,0x25,0x13,0x32,0x85,0x92,0xe4,0x30,0x2c,0x64,
+  0xb4,0xe2,0xfc,0xcc,0xc5,0x9a,0xa4,0x22,0xa6,0x4a,0xb9,0x9c,0x71,0x9a,0x14,0x95,
+  0xc7,0xac,0x23,0xae,0xe0,0xb4,0xe2,0x65,0x2c,0x99,0x95,0x11,0x7d,0x20,0x63,0x09,
+  0x67,0x42,0x0c,0x3a,0x93,0x18,0x49,0x15,0x66,0xc7,0xda,0xc4,0x48,0xca,0x85,0x9b,
+  0xd3,0x99,0x84,0x4c,0x49,0x93,0x84,0x78,0x89,0xea,0x86,0x3e,0x21,0xaa,0x82,0x4a,
+  0x72,0x2e,0x3f,0x69,0x8c,0xa4,0x0a,0xc6,0x57,0x5c,0x14,0x48,0x7a,0xf3,0xc2,0xc1,
+  0x73,0x0e,0xc7,0x0a,0x16,0xd2,0x08,0xf2,0xd5,0x20,0x22,0x50,0x49,0xa0,0x67,0x59,
+  0x99,0x33,0x56,0x46,0x77,0xb4,0x94,0x91,0x4b,0xd3,0x9b,0xef,0x1c,0xbe,0x27,0x49,
+  0xa2,0x32,0x51,0x90,0xe2,0xa6,0xae,0xa4,0x21,0x23,0x79,0x8e,0x41,0x91,0x92,0xdd,
+  0x2a,0x63,0xed,0x25,0x5d,0x15,0xb1,0x02,0xa3,0x50,0xac,0x6c,0x14,0xb5,0xe8,0x0b,
+  0x3b,0x4d,0x92,0x76,0x63,0x7e,0x97,0x49,0xdc,0x6e,0xcc,0xed,0x34,0x41,0x17,0x5a,
+  0x7b,0xdd,0x15,0x20,0x83,0x6e,0x1e,0x40,0xa3,0xe1,0x6a,0x54,0xee,0xb6,0x1d,0x87,
+  0xbf,0xff,0xe3,0x9f,0xdd,0x7f,0xdf,0x03,0xf7,0xfd,0x9f,0xfb,0x38,0x78,0xf0,0xc1,
+  0x6f,0x3f,0xfc,0xe8,0x6f,0xf6,0x9f,0x72,0x0d,0xcf,0x69,0xcc,0xe9,0x58,0xc9,0xeb,
+  0x32,0x15,0x74,0x18,0xf3,0x3a,0x4c,0x00,0x05,0x5d,0xab,0x79,0x04,0x47,0x9e,0x1d,
+  0x58,0x71,0x80,0xa1,0xa8,0xf3,0xee,0xba,0xa0,0x15,0x00,0xed,0x52,0x25,0x45,0x54,
+  0x25,0xc2,0x16,0xba,0x05,0x30,0x88,0xb2,0x4c,0x56,0x82,0x28,0x31,0x7f,0x56,0xdc,
+  0x85,0x00,0xb3,0xf9,0x5d,0x26,0xfe,0x2c,0x15,0x91,0xd3,0x8e,0xab,0xf8,0xb3,0xe8,
+  0x87,0x36,0xa3,0x84,0xcc,0x72,0x6b,0xd1,0xb4,0x4e,0x53,0x4e,0xc7,0x2a,0xa8,0x41,
+  0x01,0x88,0xf3,0x3a,0x57,0x0b,0xba,0xb0,0xd4,0x96,0xf6,0x18,0x01,0x8a,0x7b,0xb1,
+  0xce,0x96,0xb1,0xd5,0x56,0x35,0x88,0xa0,0x18,0x60,0x00,0xab,0x70,0xaf,0xa9,0xa0,
+  0xcd,0x98,0xdd,0xb2,0x92,0x54,0xbf,0x12,0xa1,0xd0,0x0b,0x9a,0x97,0x75,0x8b,0x5f,
+  0x7e,0x95,0xfc,0xa2,0x41,0x24,0x29,0xdc,0xf7,0xce,0xbb,0xfb,0xdf,0x3b,0xf4,0xe1,
+  0x47,0xe7,0xae,0xba,0x78,0xfb,0xdf,0x08,0x8f,0x4f,0x4c,0x11,0xe5,0x15,0x95,0x94,
+  0x49,0x2b,0x6a,0xea,0x9a,0x5b,0x3b,0xbb,0x7b,0x07,0xd5,0xc3,0xf8,0x64,0x27,0xf2,
+  0x74,0x0e,0x8b,0x3b,0xb2,0x2c,0x6f,0x90,0x36,0xc0,0x2c,0x79,0x76,0x34,0x3e,0x5f,
+  0x11,0x88,0xc7,0xc6,0xa7,0x47,0x46,0x27,0xd5,0xc3,0xe3,0xfd,0x83,0x50,0x8b,0x87,
+  0x7b,0xf0,0x3e,0xc9,0x81,0x8e,0xae,0x81,0xb6,0x8e,0x6e,0xa8,0xec,0x2d,0x6d,0xdd,
+  0xcd,0xad,0x1d,0x4d,0x2d,0x1d,0x8d,0x2d,0x1d,0x80,0x34,0x36,0xb7,0x37,0x35,0xb7,
+  0x34,0x34,0x01,0xd2,0xd6,0xd0,0x04,0xd0,0x5e,0xdf,0xd0,0x04,0x2d,0x85,0xfa,0xc6,
+  0x36,0x80,0x3b,0xef,0x36,0x34,0xb6,0x7e,0xea,0xb5,0x6b,0x77,0xdb,0xd6,0x98,0x65,
+  0x15,0xfe,0xdc,0x04,0xfd,0x2f,0xb1,0xf7,0xce,0xba,0x28,0xba,0xe3,0xcb,0x35,0xff,
+  0xf3,0xd1,0xaa,0xb1,0x85,0x09,0xe5,0xe7,0x60,0xd1,0x5a,0xa9,0xc2,0x75,0x5b,0x69,
+  0xce,0x7c,0xa9,0xe1,0xb6,0x55,0xf2,0x33,0x69,0xf5,0x85,0x25,0xf0,0x5d,0x69,0xc5,
+  0x27,0x26,0x6c,0x79,0x9c,0x89,0xc9,0xf8,0x21,0x03,0xb1,0x6e,0x22,0x9f,0x33,0x8d,
+  0xad,0xdd,0xb2,0x01,0x13,0x05,0xa8,0x02,0x70,0x1c,0xe3,0xba,0x77,0x02,0xca,0x41,
+  0x58,0xb2,0x5a,0xd0,0x30,0x15,0x2e,0xac,0x70,0x0a,0x4e,0xf9,0xf8,0x7a,0xf0,0x39,
+  0xd7,0x10,0xaf,0x88,0x9c,0xc4,0x82,0xb6,0xa2,0x36,0x03,0xad,0x2c,0x77,0xc5,0xf0,
+  0xaf,0x03,0xd2,0x7e,0xb3,0xbd,0x14,0x97,0x71,0x6d,0xbf,0x05,0x59,0xd5,0x10,0x8e,
+  0x00,0xa5,0xbc,0x1f,0x81,0x9b,0xb5,0xeb,0x2b,0x24,0x63,0x71,0xd5,0x90,0x49,0x0e,
+  0x15,0x56,0x6d,0xaa,0x18,0xc2,0xf1,0x9a,0x61,0x64,0x55,0x3b,0x62,0xaa,0x1f,0x65,
+  0x00,0xba,0x00,0x95,0x6a,0x6c,0xa1,0xf8,0x96,0xf4,0xe0,0x15,0x8e,0xa0,0x75,0x39,
+  0xa9,0xd6,0x10,0xaa,0x5a,0xc9,0x6c,0x34,0x68,0xe6,0xef,0xe1,0x47,0x6d,0xdc,0x39,
+  0xe8,0x0d,0x0b,0xd9,0xc2,0xbc,0x77,0xdf,0x3b,0xf0,0xfe,0xfb,0x87,0x4e,0x7f,0x7c,
+  0xc1,0xd9,0xd5,0x2b,0x30,0x28,0x38,0x2e,0x21,0x35,0x3b,0x27,0x37,0xbf,0xa8,0x4c,
+  0xa6,0xac,0x83,0x2c,0xed,0xec,0x1e,0xe8,0x1f,0x1c,0x1e,0x19,0x9b,0x1c,0x9f,0xa4,
+  0x3f,0x4d,0x82,0x2a,0x6c,0xa7,0x04,0xd3,0xbb,0xb3,0xe8,0x2f,0x95,0xc8,0x3d,0x5a,
+  0x1a,0x38,0x17,0x4f,0x4e,0xcf,0x4c,0x4e,0x4d,0x4f,0x4c,0x4d,0xc3,0x72,0x38,0x17,
+  0x93,0xa3,0xf1,0x48,0xff,0xe0,0x08,0x79,0xfe,0x2d,0x3e,0xfe,0x17,0xea,0x7b,0x4f,
+  0xff,0x70,0x37,0xfe,0x3a,0x43,0xdd,0xd5,0x0b,0x35,0x5a,0x8d,0x23,0x7d,0x4c,0x4b,
+  0x81,0x0c,0xaa,0xef,0xa6,0xfb,0x59,0xd6,0xda,0xef,0x76,0x33,0xba,0x59,0xcf,0x72,
+  0x83,0x9f,0x97,0xa0,0xff,0x25,0xf6,0xde,0x71,0x17,0x22,0x38,0xf0,0x65,0x9b,0xff,
+  0xf9,0x68,0xc5,0x8f,0xe9,0x17,0x91,0x2a,0xfc,0x2e,0xb9,0x6b,0x71,0xe0,0x53,0x87,
+  0x9b,0x27,0xeb,0x36,0x6a,0xdc,0xb5,0x92,0x54,0xab,0x2f,0x23,0x9f,0x6f,0x97,0xc0,
+  0x77,0xa5,0x15,0xeb,0x58,0xf2,0xc1,0x02,0x38,0xf3,0x61,0xd2,0x4f,0x08,0xf0,0x4e,
+  0x51,0x6a,0x38,0x20,0x3d,0x83,0x63,0xad,0x23,0x0b,0x50,0x0b,0xea,0x48,0x45,0x68,
+  0x00,0x84,0x57,0x20,0xee,0x04,0x1a,0xc6,0x58,0x84,0xb4,0xb0,0xbc,0x7a,0xd8,0xd4,
+  0x34,0xba,0x0a,0x2d,0x1d,0xac,0xb9,0x4b,0x86,0x9f,0x1d,0xea,0x58,0x73,0xea,0xd6,
+  0x98,0x6d,0x1c,0x47,0x3d,0xeb,0xa8,0xbd,0xa3,0x0c,0x6e,0x4b,0x46,0xcd,0x01,0x1a,
+  0x28,0x9a,0xfc,0xba,0x49,0xf9,0xe3,0x38,0x0f,0x1a,0xc6,0xb1,0x45,0x02,0x70,0xc8,
+  0x38,0x76,0x1b,0x27,0x10,0x07,0x04,0x5c,0x04,0xd0,0x44,0x90,0x96,0x09,0x53,0x23,
+  0xe0,0x13,0x66,0x6e,0x15,0x6a,0x2c,0xeb,0x45,0x3d,0xa6,0x82,0xf6,0x55,0x61,0xeb,
+  0x62,0x4a,0xfd,0x42,0x58,0xc5,0x52,0x7a,0xc3,0xfc,0x88,0xe6,0x6f,0xe4,0xd7,0x46,
+  0x77,0x02,0x46,0x93,0xa9,0x5c,0x2a,0x3f,0x75,0xfa,0xe3,0xf7,0xdf,0x3b,0x70,0xea,
+  0xd4,0xc7,0x8e,0x57,0x5d,0x03,0x02,0x83,0x23,0xa3,0x93,0x32,0xb2,0x72,0x24,0x05,
+  0x25,0xe5,0x72,0x25,0x9e,0x83,0xf1,0x21,0xd1,0x83,0x83,0x43,0xe3,0x63,0x13,0xd3,
+  0xdc,0xfb,0x82,0xf1,0x30,0x6c,0xef,0x2c,0xcc,0xfe,0x5e,0x58,0x4f,0xde,0xe3,0x00,
+  0x87,0x62,0x1d,0xbd,0x53,0x0b,0x60,0x6a,0x1a,0x61,0x62,0x72,0x66,0x7c,0x62,0x0a,
+  0xda,0xd1,0xf1,0xa9,0xd1,0xf1,0x99,0x61,0x6c,0x27,0xf1,0x3e,0xae,0xd1,0x89,0x91,
+  0x31,0x80,0xa9,0xe1,0xd1,0xc9,0xe1,0xd1,0x89,0x4f,0x0d,0x23,0x63,0xd3,0x9f,0x65,
+  0xb9,0x3d,0x98,0x24,0x5a,0xd9,0x9d,0xfa,0xac,0xda,0x7e,0x76,0xf8,0x02,0xec,0xbd,
+  0x67,0xa4,0x7f,0xae,0x5a,0x4d,0x0e,0x8d,0x40,0x34,0xa7,0xd4,0xc3,0x9f,0x25,0xa0,
+  0x94,0xc9,0x17,0xe8,0x37,0x58,0xa8,0x1e,0xfe,0x64,0xb2,0xa1,0x91,0x4f,0xa7,0xe4,
+  0xf4,0x6d,0x17,0x7e,0x59,0xc1,0xba,0x0b,0xad,0x28,0xb7,0x21,0xb2,0x31,0xd5,0xa3,
+  0x0c,0x67,0xf8,0x78,0x61,0xdd,0x32,0xae,0x1e,0x9d,0x1a,0x1c,0xd7,0xf4,0x4d,0xad,
+  0xf6,0xcf,0x98,0x00,0x7a,0xa6,0x4d,0x14,0xe9,0x9b,0x32,0x52,0xe4,0x0e,0xa1,0x17,
+  0x96,0xdc,0x0d,0xfd,0x5f,0x03,0x66,0x79,0x60,0x77,0x96,0xe8,0xdc,0xcb,0xb6,0x76,
+  0x4d,0xa0,0x83,0xd4,0x2d,0x9c,0x73,0x38,0x5f,0xd1,0x55,0x5d,0xd3,0x0c,0x74,0x4c,
+  0x9b,0x3a,0x09,0x02,0x53,0xdd,0xd3,0xe6,0x71,0x0e,0x3a,0xc9,0x54,0xfb,0x94,0xa9,
+  0x75,0xd2,0xd4,0x31,0x89,0x55,0xb8,0x79,0xcc,0x48,0x8f,0xc0,0x70,0xf2,0x2d,0xeb,
+  0x35,0xe5,0x77,0x18,0x33,0x5b,0x96,0xd3,0x1a,0xe6,0x43,0x54,0xab,0x65,0x9d,0x8b,
+  0x5a,0xc3,0x97,0x5f,0x13,0xff,0xca,0xb0,0x6a,0x5a,0xed,0xea,0xe9,0xb9,0x76,0xfd,
+  0xfa,0x81,0x83,0x87,0x8f,0x9f,0xfc,0xd0,0xc1,0xe9,0xba,0xa7,0x4f,0x60,0x68,0x64,
+  0x4c,0x72,0x6a,0x86,0x50,0x24,0x29,0x2c,0x91,0x2a,0x2a,0x6b,0xea,0x1a,0x5b,0xda,
+  0x3a,0x7a,0xe0,0xd2,0x71,0x60,0x18,0x8b,0xd1,0xe4,0xf4,0x2c,0xd4,0x53,0x38,0x0b,
+  0x6b,0x75,0x73,0x5a,0xdd,0x3c,0x77,0x77,0x16,0xf7,0x37,0x62,0xfa,0x10,0x4b,0xf2,
+  0x1a,0x82,0x39,0x72,0xa7,0x96,0x16,0xca,0x31,0x7d,0xb9,0x21,0x2c,0x24,0x88,0x0e,
+  0x6a,0xf1,0xf4,0x8c,0x66,0x7a,0x56,0xcb,0x8d,0xc3,0xf9,0x9a,0xb4,0xf8,0xac,0x8f,
+  0xe9,0x59,0xa8,0xdd,0x1a,0x7c,0xa3,0x81,0x46,0x47,0xde,0x6b,0x00,0x83,0x1a,0xac,
+  0xe6,0x58,0xd0,0x67,0x09,0x0d,0xe9,0xce,0xe0,0xe3,0xb9,0xe8,0x20,0xa1,0xc7,0x76,
+  0x6a,0x7a,0x96,0x2c,0xe7,0x06,0x81,0x1b,0x6d,0xad,0xd6,0x22,0x5b,0x1e,0x31,0x2a,
+  0xc3,0x48,0x27,0x64,0x53,0x48,0x46,0x89,0x11,0x61,0xbb,0x74,0x96,0x12,0xcf,0x52,
+  0xce,0x33,0xb3,0x0c,0xab,0x19,0xb6,0x4b,0x89,0x19,0x7a,0xaa,0x36,0xcb,0x8a,0x59,
+  0xc8,0x37,0x81,0x4c,0xd1,0x9f,0x5d,0xe3,0x20,0x79,0xf2,0x36,0xa7,0xd5,0x0c,0x23,
+  0x88,0xb1,0x88,0xb5,0x02,0x56,0xe9,0xa8,0xc4,0xcf,0x66,0xaf,0x86,0x21,0x63,0xa5,
+  0xb0,0x6a,0x50,0xdc,0x8e,0x9f,0xa7,0x67,0x74,0x66,0x1d,0xb0,0x9d,0x9d,0xe6,0xdc,
+  0xc2,0xf3,0x06,0x8f,0x9b,0xa5,0xeb,0xb8,0x20,0xb2,0x2d,0x35,0x81,0x68,0x6e,0x61,
+  0x02,0x67,0x11,0xb7,0x9c,0x24,0x83,0x8e,0xc7,0xc4,0x22,0x64,0xbc,0xe8,0xcc,0xb2,
+  0xb3,0x3a,0x1b,0x89,0x56,0x89,0xa4,0xb1,0xb1,0x45,0x33,0xcd,0xda,0x6b,0x91,0x75,
+  0x76,0x58,0xcd,0x12,0x7d,0x2c,0xe5,0x12,0x6f,0xd0,0x71,0x3e,0x0d,0x9b,0xcf,0x8c,
+  0x9f,0x69,0x14,0x78,0x72,0x35,0x5c,0x02,0xb3,0xe3,0x34,0x0a,0x1c,0x67,0x2b,0x25,
+  0x75,0x34,0x91,0x30,0x55,0xa8,0x73,0x18,0x9d,0x19,0xe7,0x5b,0x27,0x83,0x65,0x9a,
+  0x99,0x83,0x02,0xba,0xf1,0xec,0xa5,0xe6,0x53,0x7b,0x51,0x43,0xe2,0x1c,0x73,0x12,
+  0xb2,0x26,0x58,0xac,0x9d,0xd1,0xce,0x58,0x45,0x5f,0x63,0x76,0x14,0x2f,0x81,0xb5,
+  0xd3,0xfc,0xad,0xa1,0xd1,0xf1,0x13,0x98,0x6f,0x35,0x97,0x24,0x3c,0x13,0xb8,0x2e,
+  0x27,0x57,0x6b,0x4e,0x60,0x36,0x63,0xa7,0x78,0x7b,0xdf,0x1c,0x0b,0x70,0xf5,0x0c,
+  0xc9,0x79,0xa6,0xab,0x99,0xd2,0x2c,0xa8,0x35,0xc6,0x31,0xbd,0x69,0x58,0x6b,0x1a,
+  0xd5,0x99,0xc6,0x74,0xa6,0x71,0xfd,0x5d,0x03,0xac,0x85,0x16,0x98,0x8c,0x10,0x0e,
+  0xa3,0xb7,0x65,0x42,0x89,0xbf,0x20,0x00,0xe6,0x54,0x0d,0x40,0x46,0x88,0x45,0x43,
+  0x1a,0x6c,0xa1,0x4b,0x0d,0x04,0xe0,0x66,0xd5,0x1a,0xd4,0x16,0x75,0x66,0xd7,0xe2,
+  0xb8,0xe5,0x92,0x11,0x1d,0xb3,0x8a,0x33,0xca,0x96,0x95,0x5a,0x63,0xee,0x02,0x0e,
+  0x23,0x03,0xb3,0x08,0x74,0x6a,0x48,0x6b,0x2e,0xd9,0xb4,0xbe,0xb7,0x4f,0x1a,0xbb,
+  0x26,0x8d,0x2d,0xe4,0x20,0x0c,0x27,0x6b,0xa5,0x1a,0xff,0x10,0x5c,0xdc,0x65,0xcc,
+  0x69,0x37,0x66,0xb5,0x2c,0x47,0x57,0x2e,0x47,0x57,0x2f,0xa9,0x06,0x8c,0x0b,0xab,
+  0xff,0x5f,0x7c,0xed,0x6c,0x0b,0xc6,0xff,0x6b,0x1a,0x9b,0x98,0xf4,0xf1,0x0b,0x78,
+  0x77,0xff,0x81,0xa3,0xc7,0x4f,0x9e,0xbf,0x78,0xc5,0xd5,0xc3,0xf7,0xc6,0xad,0xf0,
+  0x98,0xb8,0x94,0xf4,0x4c,0x01,0x1c,0x84,0xa5,0xf2,0x0a,0x28,0xc2,0xe4,0x15,0x03,
+  0xdd,0xf8,0x9c,0x1c,0xf5,0xf8,0x08,0x9c,0x5a,0xf1,0x49,0x1d,0x58,0x86,0x49,0x21,
+  0xd6,0xeb,0xe7,0x0c,0xe4,0x65,0xa9,0xf3,0xdc,0x1f,0x85,0xc9,0x0b,0x0d,0xa1,0x04,
+  0x73,0xb5,0x58,0x4f,0xbf,0xa0,0xa6,0x6f,0x05,0xa2,0x07,0x64,0x52,0x9a,0xe1,0x40,
+  0x3d,0x4f,0xab,0x30,0xf9,0xee,0x5a,0x4b,0x66,0xb5,0x74,0x96,0xc2,0x2c,0xd2,0xea,
+  0x68,0x8b,0x2f,0x09,0x9d,0x65,0x10,0x42,0xa3,0xa3,0x53,0x50,0xeb,0x09,0x01,0xae,
+  0x25,0xef,0xc3,0xd5,0xb1,0x5d,0x0d,0xbd,0x06,0x20,0x0b,0xf1,0x66,0x32,0xab,0x29,
+  0x8e,0x33,0x3b,0x4b,0xc7,0xf5,0x3c,0xb9,0x5a,0xfa,0x5a,0x46,0x82,0xeb,0x88,0xbd,
+  0x0c,0x31,0xd8,0x42,0xc7,0x29,0x19,0xd5,0x99,0xd5,0x87,0x79,0x93,0x14,0x4b,0xcc,
+  0x57,0x92,0x92,0xe9,0x39,0xb9,0x64,0x9c,0xb1,0x88,0x95,0xc8,0x99,0xa0,0xe3,0xf8,
+  0x40,0x97,0x1d,0x47,0x59,0xf4,0xb5,0xbf,0x9f,0xc5,0x5e,0x90,0xcb,0xe9,0x46,0xa7,
+  0xa8,0x8d,0x40,0xcc,0xad,0x25,0x23,0x7a,0x2a,0x82,0xef,0x7c,0xfe,0x20,0x15,0x67,
+  0x13,0x2f,0x1d,0x5f,0x79,0x6a,0x1a,0xe7,0x0d,0x3a,0xc2,0x99,0x40,0x43,0xc9,0x76,
+  0xf9,0x7a,0x82,0x1b,0xf5,0x1c,0x67,0xee,0xfd,0x5c,0x94,0x1b,0x2f,0x64,0xe6,0x64,
+  0xa0,0x4a,0x72,0xa6,0xf1,0x75,0xa6,0x88,0xa5,0xdb,0x35,0xf4,0xfb,0x1c,0x9e,0xb6,
+  0x16,0xd1,0xe1,0xe5,0x86,0x6d,0xee,0xf1,0x89,0xcd,0xa9,0xc8,0x73,0x05,0x43,0xc3,
+  0xda,0xc5,0x77,0x3e,0x23,0x97,0x53,0x83,0xd3,0x81,0x17,0x11,0x7e,0x36,0x52,0xff,
+  0x58,0x65,0x3b,0xf3,0xc2,0x50,0xd6,0x76,0x3d,0x2f,0x51,0xf9,0xc9,0xa0,0xb3,0x49,
+  0x33,0x26,0x4c,0x24,0x4b,0xed,0x98,0x30,0x4b,0xde,0x48,0xca,0xcf,0x0d,0x2e,0x46,
+  0x96,0x6b,0xb5,0xac,0x2b,0xf4,0x6c,0xc2,0xeb,0x6c,0xac,0x30,0xfb,0x84,0xd2,0x70,
+  0x16,0x59,0xba,0x85,0x1a,0xa8,0xb1,0xf2,0x00,0xcf,0x69,0xfc,0x2d,0x69,0x26,0x63,
+  0x89,0x2d,0xf6,0x02,0x1d,0xe7,0x88,0xe9,0x87,0x8c,0x46,0x6f,0x98,0x9c,0x33,0x4e,
+  0xcc,0x99,0xfe,0x0e,0x9f,0x08,0x50,0xa3,0x39,0x5c,0x63,0x58,0x73,0x8a,0xe2,0xd0,
+  0x0e,0x69,0xd8,0x6a,0xae,0xb5,0x3e,0x53,0xc3,0xf9,0xb7,0x79,0xdc,0xd4,0x34,0x6a,
+  0xaa,0x1c,0x36,0x29,0x06,0x4d,0xa5,0xbd,0xf8,0x6b,0xa3,0x8c,0x16,0x7c,0xd4,0x55,
+  0x64,0xd5,0x4a,0x64,0xe5,0x42,0xf3,0xe8,0xea,0xca,0xdf,0xe2,0x4f,0x8d,0xee,0x0a,
+  0x16,0x16,0x17,0x84,0x79,0x62,0x38,0x05,0x03,0x7c,0x74,0xe6,0xfc,0x15,0x27,0x67,
+  0x6f,0xdf,0xc0,0x90,0xf0,0xd8,0xf8,0xc4,0xd4,0x2c,0x41,0x6e,0x41,0x61,0x79,0x99,
+  0x4c,0x51,0x59,0xdd,0x54,0xd7,0xd8,0xdc,0xde,0xd9,0x0b,0x67,0xe1,0xfe,0x41,0xb5,
+  0x7a,0x78,0x6c,0x64,0x6c,0x72,0x72,0x7a,0x7a,0x6a,0x1a,0xdf,0xd4,0x40,0xee,0xbf,
+  0xc2,0xeb,0x67,0x9a,0xff,0x50,0x82,0xe9,0x5b,0xb6,0xe1,0x83,0x9a,0x54,0xde,0x39,
+  0xfa,0xf3,0x61,0xba,0x7f,0xe9,0xd1,0x98,0x6e,0x5e,0x42,0x83,0xff,0xa3,0xe3,0xec,
+  0x27,0x8f,0x8e,0xfd,0x60,0xd4,0x10,0x02,0xda,0x6a,0x29,0x25,0xf7,0x69,0xc0,0x2b,
+  0xe5,0x3a,0x5e,0x2d,0x60,0x76,0x37,0xd9,0x8c,0xf3,0xdc,0xc7,0x17,0xe5,0x43,0xd8,
+  0xea,0x59,0x89,0x3a,0x8e,0x33,0xd7,0xa5,0x6c,0x89,0x9e,0x8c,0x20,0x4e,0x2b,0xf6,
+  0x23,0x68,0x8e,0xee,0x77,0xae,0x6a,0xb0,0xbb,0x1e,0xd4,0x9e,0x67,0xbb,0x80,0xcf,
+  0x91,0xda,0xa1,0x23,0x2f,0x19,0xe7,0xaa,0xc6,0x1c,0x8f,0x8f,0x9e,0x76,0xe9,0x12,
+  0xbe,0x15,0xdc,0xd5,0x05,0xcf,0x2e,0x8a,0xd0,0x0f,0xbd,0x39,0x6a,0x26,0xdb,0xfd,
+  0x34,0xf6,0xb2,0x4a,0xea,0x78,0x06,0x9a,0xe5,0xd2,0x4f,0x66,0xbe,0x6f,0x6d,0xd6,
+  0x7e,0x0a,0x7b,0x39,0x9d,0xf5,0x56,0xa6,0xf1,0x8c,0xe5,0x2c,0xd2,0xf2,0x56,0x99,
+  0xed,0xe5,0xae,0xdc,0x38,0x1a,0x2e,0x64,0x9c,0x27,0xb9,0x80,0xf2,0xbb,0x2c,0xa2,
+  0x21,0xea,0xe9,0x59,0x9d,0xf5,0x3c,0x0e,0x3a,0x22,0x48,0x67,0x45,0x6c,0xc3,0x8a,
+  0xaf,0x80,0x39,0xfa,0x3c,0x8b,0xcc,0x41,0xb1,0xea,0x72,0x51,0xe0,0x2e,0x3f,0xc8,
+  0x5a,0xba,0x17,0x68,0xb2,0xcd,0xf1,0x7d,0xc2,0x6a,0x6b,0xf6,0x15,0xe1,0x60,0x91,
+  0x03,0x5c,0xe1,0xa3,0x51,0x63,0x4b,0x2a,0xcd,0x2e,0xeb,0x80,0x52,0xcd,0xf9,0xdb,
+  0x8a,0xe7,0x3a,0xab,0x7d,0xc4,0x2c,0xe1,0x5d,0x86,0x31,0xd7,0x0c,0x3c,0x6e,0xd6,
+  0x51,0xe0,0x4c,0x63,0xcd,0xd4,0xdb,0xc6,0x77,0xed,0x08,0x32,0xa9,0xc2,0xca,0xb5,
+  0x93,0x21,0x34,0x10,0xfc,0x0d,0x4b,0xfd,0xc3,0xed,0x1a,0xde,0x27,0x80,0x79,0x83,
+  0x68,0x74,0x86,0x49,0xfd,0xea,0x97,0x5e,0xd4,0xfe,0x56,0x81,0x9e,0x94,0xa1,0xf8,
+  0x0e,0x6a,0x10,0xfa,0xd9,0x2f,0xb1,0xbb,0x26,0x4d,0xad,0x13,0xa6,0xea,0x11,0x53,
+  0xd5,0x08,0xde,0x94,0x05,0xc7,0xde,0x82,0x8e,0x15,0x41,0xcb,0x72,0x46,0xd3,0x4a,
+  0x6c,0xd5,0x62,0x88,0x62,0x29,0xad,0x6e,0x79,0x56,0x6f,0xfc,0xdb,0x7b,0xc8,0xc6,
+  0xa7,0x83,0xa5,0x95,0xe5,0xa2,0x92,0xd2,0x73,0xe7,0x2f,0x1d,0x38,0x70,0xf8,0xf8,
+  0x89,0x0f,0x2f,0x5c,0x72,0x74,0xf3,0xf0,0x09,0xbc,0x11,0x12,0x1e,0x15,0x97,0x9c,
+  0x92,0x95,0x9d,0x93,0x97,0x5f,0x88,0x77,0xfb,0xab,0xaa,0xeb,0x6a,0x1b,0x5a,0x9a,
+  0x5a,0x3b,0x3b,0xba,0xfa,0xf0,0x91,0xcb,0x03,0x43,0xea,0xe1,0xd1,0xa1,0x91,0xb1,
+  0xd1,0xf1,0x69,0x72,0xc3,0xd5,0x2c,0xf9,0x53,0xef,0x2c,0xad,0xc5,0xf4,0x7b,0x24,
+  0xfa,0x1e,0x07,0xee,0x5b,0x68,0x7a,0x69,0x4a,0x5a,0xfa,0x0d,0x15,0xfd,0x76,0x48,
+  0x07,0x75,0x1c,0x6f,0xdc,0x9a,0x62,0xbe,0x2f,0x9d,0x9c,0x66,0xbe,0x01,0x26,0xdf,
+  0xbf,0xe1,0x97,0x4e,0x64,0x4a,0x3b,0x85,0x5d,0x1d,0x61,0xae,0xe1,0xbe,0x70,0xa3,
+  0x4c,0x38,0x9a,0x19,0xde,0x17,0x98,0xf8,0xcd,0xd5,0x34,0x25,0xd6,0x4c,0x9b,0xbf,
+  0x19,0xe6,0xbe,0xfe,0x62,0x66,0x27,0xa7,0xb4,0x2c,0x43,0x8d,0xf9,0xbb,0x47,0x86,
+  0x03,0xa3,0x1b,0x65,0xcb,0x8e,0x33,0xaa,0xb2,0xc0,0x17,0x4a,0x6f,0x08,0xa7,0xf7,
+  0xa1,0xd1,0xaf,0xdd,0x38,0x87,0x68,0xd8,0x85,0x16,0x7a,0xf2,0x95,0x9f,0x62,0x74,
+  0x63,0x74,0xe6,0xba,0xc0,0x61,0x92,0x51,0x83,0xea,0xc3,0xb7,0xe8,0xae,0xed,0xa5,
+  0xab,0xf8,0x7e,0xfe,0xab,0xd8,0x4b,0xbf,0xc6,0x64,0xbc,0xcd,0x19,0x4e,0x97,0x93,
+  0xaf,0x1f,0x75,0x9c,0xce,0x66,0xe2,0x69,0x8b,0x2e,0x6f,0x96,0xaf,0xa4,0x86,0x33,
+  0x81,0xcb,0x3d,0x2a,0x05,0xec,0x9d,0xb6,0x30,0x41,0xc3,0x7e,0x95,0x6a,0x56,0x9b,
+  0xfb,0xfb,0x05,0x97,0x4b,0xf4,0x85,0xce,0xb8,0x76,0xc6,0x92,0xd5,0x8c,0x96,0xfb,
+  0x66,0x95,0x67,0xbe,0xc5,0x2c,0x97,0x84,0x96,0x16,0x51,0xc7,0xf2,0xff,0x28,0x30,
+  0xcb,0x7e,0x83,0xcd,0xb4,0x2c,0x37,0x9e,0x3f,0x59,0x85,0xd9,0xbf,0x83,0x50,0x7d,
+  0xd0,0xcf,0xec,0xd6,0xa0,0x5f,0xed,0x92,0x54,0x99,0xd6,0xb2,0xb8,0x96,0x73,0x02,
+  0x31,0x87,0xd2,0x98,0x63,0xc4,0xdb,0x56,0xb3,0x6c,0x1c,0xcd,0x16,0xb1,0x5f,0x7a,
+  0xf3,0x36,0xdd,0x34,0x33,0x4b,0xf5,0x59,0x3b,0x0a,0x9c,0x9f,0xf9,0x19,0xc5,0xfd,
+  0x09,0x89,0xef,0x3a,0x3b,0x11,0x64,0xf3,0x47,0x43,0x53,0xd4,0x2a,0x3d,0x88,0x74,
+  0x6e,0x84,0xa6,0x10,0x9d,0xe2,0xb6,0x3f,0xfd,0x63,0x16,0xdf,0x03,0xda,0x29,0xed,
+  0xe2,0xe4,0xdc,0x2a,0x54,0x07,0xae,0x58,0x70,0x25,0xe3,0x1e,0x85,0x51,0xf6,0x3b,
+  0x64,0xab,0x0a,0xc8,0xef,0x5a,0xb5,0x76,0x69,0xec,0x76,0xd7,0x12,0x3a,0x3b,0x6f,
+  0x4d,0x43,0xbf,0x7f,0x06,0x18,0xd1,0x9a,0x06,0xb9,0xbf,0x2f,0x4f,0x9b,0x3a,0xa7,
+  0x4c,0x9d,0x93,0xf8,0x6d,0x73,0xed,0x30,0xb9,0xcf,0x6a,0xd0,0x54,0xd6,0x87,0x3f,
+  0x59,0xca,0x6e,0x5d,0x4e,0x6b,0x5a,0x8a,0xaf,0x5d,0x8e,0xac,0x5c,0x09,0x96,0x1b,
+  0xc4,0xed,0x10,0x97,0xbf,0x17,0x5f,0x6b,0x18,0x1d,0x9f,0x48,0x49,0xcd,0x3c,0x75,
+  0xfa,0xec,0xe1,0xc3,0xc7,0x4f,0x9d,0x3a,0x7b,0xd9,0xd1,0xd9,0xdd,0xd3,0x37,0xe0,
+  0x66,0x48,0x44,0x74,0x6c,0x52,0x4a,0x16,0x9c,0x85,0xc5,0xf9,0xa5,0x25,0xe5,0xb2,
+  0x72,0x45,0x65,0x55,0x4d,0x63,0x6d,0x63,0x6b,0x4b,0x5b,0x67,0x7b,0x67,0x77,0x67,
+  0xf7,0x60,0x4f,0xdf,0x20,0x79,0xf5,0xed,0xd8,0x80,0x7a,0x8c,0xb9,0x65,0x62,0x7c,
+  0x1a,0xb8,0x41,0x5d,0x1e,0x9f,0x9c,0x1e,0x1e,0xc7,0x3b,0xaf,0xc6,0x27,0xa7,0xc6,
+  0x27,0x26,0xe9,0x5d,0x58,0xb4,0x3b,0x32,0x3e,0x33,0x06,0xdd,0xc9,0xe9,0x89,0x49,
+  0x20,0x9b,0xe2,0x6e,0xd0,0x62,0x5a,0x1c,0xe4,0x60,0x8a,0x5d,0xb5,0x46,0x97,0xb2,
+  0x35,0x77,0x29,0x62,0x66,0x38,0x8e,0xf7,0x7d,0x31,0xb3,0x13,0xbc,0x59,0xfb,0xc4,
+  0x2c,0x2b,0xab,0x2e,0x23,0xd7,0xac,0x9b,0xb5,0x1a,0x63,0x13,0x40,0x3f,0xc3,0xd2,
+  0x98,0x6d,0x21,0xe6,0x4c,0x8d,0x5b,0x77,0xc9,0x2a,0x96,0xd8,0xaa,0xcb,0x90,0x59,
+  0xb2,0xb2,0x52,0x83,0xb3,0xe8,0xde,0xb0,0xd7,0x92,0x15,0x0c,0x8e,0xdd,0x95,0x5c,
+  0xa0,0x1f,0xb7,0x34,0x81,0x4d,0x24,0x72,0x53,0x1f,0x43,0x4c,0x54,0xb2,0xc9,0x9c,
+  0xdb,0xcb,0xe5,0xf9,0x99,0x2f,0xc8,0x26,0x21,0x3f,0x21,0xeb,0x26,0xcc,0x42,0xad,
+  0x2d,0xb2,0x0d,0x8a,0x55,0x7a,0xf3,0xb5,0xe2,0xbb,0x8e,0x1f,0x23,0x6b,0x7d,0x18,
+  0x86,0xbc,0x54,0xb1,0x09,0xe8,0x5a,0x31,0xb2,0xde,0x29,0x3c,0x4f,0xf2,0x77,0xe8,
+  0xed,0xf3,0xea,0x36,0x21,0x03,0xa1,0x63,0x96,0x5d,0x1a,0x94,0x91,0x89,0x35,0xf7,
+  0x2f,0xdf,0xcf,0x54,0x67,0x0c,0xeb,0x84,0x45,0x22,0x61,0x68,0x70,0xdc,0x42,0x67,
+  0xd6,0x04,0x5c,0x42,0x67,0xc7,0x26,0x26,0xc6,0x27,0xb5,0x43,0xd3,0xcb,0x50,0x17,
+  0x06,0x66,0xb1,0x40,0xd0,0x62,0x01,0x5d,0xda,0xde,0xbb,0x00,0xfa,0x0f,0xb0,0x08,
+  0x85,0x41,0x9e,0x81,0x74,0x96,0x6f,0xa9,0x5d,0x1a,0xdb,0xee,0xc0,0xac,0x79,0xfc,
+  0xf6,0xd2,0x29,0x31,0xff,0xd6,0xac,0xee,0x49,0x63,0x37,0xb9,0xc3,0x0a,0xca,0x2e,
+  0x9c,0x76,0x2b,0x87,0x4c,0x0a,0xb5,0xa9,0xb8,0xcf,0x54,0xd4,0x67,0xca,0xef,0x5c,
+  0x11,0xb6,0x2e,0xa6,0x36,0xad,0x26,0xd6,0x2e,0x86,0x57,0xae,0x86,0xc8,0x0d,0x69,
+  0x8d,0xab,0x6d,0xe3,0xa6,0xbf,0x7f,0xe7,0xbc,0x16,0x2c,0xaf,0xae,0x0c,0x0c,0xaa,
+  0x93,0x52,0x52,0x4f,0x9f,0x3e,0x0b,0x07,0xe1,0x8f,0x4e,0x9d,0xbd,0xe2,0xe4,0xec,
+  0xe6,0xe9,0x17,0x18,0x74,0x2b,0x22,0x2a,0x3e,0x21,0x29,0x2d,0x3d,0x4b,0x28,0x14,
+  0x49,0xf2,0x0b,0xa1,0x10,0xcb,0xcb,0xe5,0xd5,0xca,0xca,0x1a,0xa8,0xc5,0xf5,0xcd,
+  0x2d,0x8d,0xcd,0xed,0x2d,0x6d,0xdd,0x6d,0x1d,0x3d,0x5d,0x3d,0xfd,0x1d,0x5d,0xfd,
+  0xdc,0x3d,0xff,0xf8,0xeb,0x80,0x01,0xfc,0x69,0x40,0xdf,0xc0,0x70,0x6f,0xff,0x50,
+  0x6f,0xff,0x30,0x9c,0x9a,0x7b,0xf1,0x2d,0x48,0x88,0x90,0xdf,0x08,0x0f,0x93,0x29,
+  0xda,0x0e,0x71,0x2d,0x9d,0x22,0xef,0xb2,0x1f,0x66,0x89,0x87,0x78,0xc4,0x43,0x2c,
+  0x31,0x33,0x0b,0x22,0x80,0x98,0x2e,0xa7,0x08,0x8f,0x06,0x46,0xcc,0x6b,0x79,0x64,
+  0x8c,0x20,0x4b,0x86,0x43,0x54,0x31,0xbe,0x5c,0x4b,0x0d,0xad,0xbb,0x1c,0x4f,0x8a,
+  0xf3,0x75,0xb3,0x94,0x6b,0x26,0x66,0xc9,0xcc,0xfc,0x39,0x35,0x38,0xfe,0x36,0x5d,
+  0x86,0x6c,0x2d,0x7b,0x79,0x16,0x59,0x38,0x87,0xb6,0x24,0x04,0x56,0xd2,0xb9,0xa0,
+  0x20,0xc2,0x99,0xf0,0x45,0xda,0xcb,0x59,0x3a,0xc4,0x6b,0xed,0x08,0xb2,0x55,0x83,
+  0xe5,0x3c,0xc4,0x33,0x6a,0x88,0xeb,0x72,0x89,0xc4,0x85,0x98,0xd7,0xe5,0xb3,0xb2,
+  0x23,0x97,0x70,0xe6,0x54,0x1d,0xb2,0xa4,0x19,0xe2,0x99,0x69,0x27,0xeb,0x6c,0xfd,
+  0x6c,0xcf,0xc3,0x76,0x12,0x18,0x04,0xf1,0x73,0x80,0x8b,0xaf,0x8d,0x37,0x86,0x2c,
+  0xd7,0x0e,0xf1,0xad,0xb8,0x4d,0x02,0xf3,0x77,0x0a,0xd9,0x47,0x7c,0x65,0xac,0xcc,
+  0xb7,0xe3,0x7c,0x8e,0x33,0x9d,0x5d,0x8b,0x33,0xd7,0x5d,0x2b,0x55,0xac,0x9d,0xc3,
+  0x9b,0xb5,0xb1,0x97,0xa6,0x28,0xa7,0xc0,0xf0,0x5a,0x9b,0x9d,0x6e,0x0d,0x7e,0x76,
+  0xd1,0xc1,0x9e,0x81,0xc1,0xde,0x41,0x75,0x8f,0x7a,0xbc,0x6b,0xd4,0xd0,0x31,0xb6,
+  0xd2,0x3e,0x61,0x6a,0x9b,0xc0,0xfb,0x6f,0x01,0x9a,0xc7,0x19,0xe4,0x9e,0x80,0x76,
+  0x0a,0x13,0x46,0x80,0x8e,0x09,0xbc,0x7f,0xa9,0x75,0x02,0x8f,0x96,0x1d,0x93,0x68,
+  0x11,0xd8,0x02,0x78,0xf3,0x98,0xb1,0x6b,0x7c,0x15,0xc7,0x81,0x60,0xc2,0x04,0x64,
+  0x6d,0xe3,0xc6,0xe6,0x09,0x3c,0x7e,0xb6,0x4d,0x18,0xbb,0xc8,0x20,0x10,0x77,0x10,
+  0x3e,0x2d,0x63,0xc6,0xd6,0x71,0xec,0xb6,0x8f,0x1b,0x81,0xb3,0x55,0xb7,0x71,0x0c,
+  0xc5,0x35,0x13,0xce,0xd4,0x51,0xb4,0x6d,0xa3,0x6b,0x27,0x98,0xd9,0x16,0x02,0x30,
+  0x05,0xf4,0x8d,0xe3,0xcc,0x8f,0x95,0x00,0xe0,0xa8,0xab,0x52,0xe3,0x9f,0x77,0xcb,
+  0xfa,0x4c,0x25,0xbd,0xa6,0xfc,0x6e,0x93,0xa4,0xd3,0x98,0xdd,0xbe,0x9a,0xd1,0xbc,
+  0x18,0x57,0x63,0x8c,0xae,0xc6,0x07,0x78,0x06,0xcb,0x17,0x53,0xea,0x57,0x41,0xd5,
+  0xbf,0xe1,0x67,0x5b,0x7d,0xae,0x55,0x78,0xb5,0xad,0xa3,0x23,0x2c,0x22,0xf2,0xf8,
+  0xf1,0x93,0x50,0x85,0x4f,0x9d,0x3e,0xef,0x70,0xc5,0xd9,0xd5,0xdd,0xc7,0xd7,0x3f,
+  0x38,0x34,0x2c,0x3a,0x3a,0x36,0x39,0x29,0x25,0x23,0x23,0x2b,0x27,0x27,0xb7,0x20,
+  0x2f,0xbf,0xa8,0xb0,0x44,0x51,0x2a,0x55,0x28,0x94,0x55,0x0a,0x55,0x8d,0xb2,0xaa,
+  0xa1,0xaa,0xa6,0xa1,0xae,0xa1,0xb1,0xb6,0xbe,0xb5,0x81,0xf9,0x8d,0x3c,0x3e,0x67,
+  0x03,0x00,0x10,0xf2,0xcc,0x0d,0x6c,0x29,0xde,0xd4,0xda,0xd6,0x44,0x1e,0xc4,0xc1,
+  0x01,0xd7,0x05,0x32,0x8a,0x43,0x8b,0xc0,0x22,0x1c,0x07,0x8e,0xc0,0xee,0x72,0x8e,
+  0x92,0xcf,0xc4,0x8a,0x8c,0xe1,0xcc,0xe2,0x94,0x98,0xbf,0x84,0x23,0xb6,0x56,0xc6,
+  0x9e,0x5c,0xfe,0xaa,0x3b,0x91,0x6b,0x6b,0x02,0x15,0xc4,0x67,0x68,0xa5,0xe1,0x5a,
+  0x0c,0x6d,0x67,0x39,0x56,0x4d,0xad,0x8c,0xeb,0x6e,0xa3,0x2d,0x9f,0x89,0x5d,0xfd,
+  0x3f,0x2f,0x7b,0x9b,0xed,0x69,0x62,0x35,0xc8,0x0f,0x37,0x63,0x82,0x8d,0xd3,0xac,
+  0x42,0x6c,0xe1,0x40,0x7b,0x6a,0xd8,0x8a,0xb0,0x6b,0xf5,0x6d,0x54,0xb2,0x52,0x8f,
+  0x6f,0x2f,0x5f,0xc9,0xdb,0xbb,0x71,0x2d,0x32,0xbb,0xb1,0xb0,0x82,0x46,0x4a,0xdc,
+  0x86,0x48,0x4b,0x9b,0x59,0xa8,0x55,0x86,0xf0,0xb7,0x8f,0xad,0x73,0xd6,0x8a,0x91,
+  0xfd,0xe5,0x6d,0x4c,0x97,0x8a,0xb3,0x4e,0x54,0xa2,0x86,0xdd,0xdc,0xe0,0x13,0xdb,
+  0xa6,0xae,0x15,0x6e,0xab,0x4c,0x23,0xdb,0xa5,0xfc,0x41,0x0d,0x8e,0xa7,0x99,0x5b,
+  0x9b,0x05,0xe7,0xe6,0xd6,0xf6,0xa6,0x96,0xb6,0xa6,0xe6,0xe6,0xe6,0xb6,0x9e,0x9a,
+  0xee,0xa9,0xea,0x81,0xc5,0x8a,0x61,0x7c,0x04,0x84,0x52,0xcd,0x3c,0x70,0x09,0x00,
+  0xba,0x1c,0x7e,0xaf,0x40,0x85,0x9a,0xc0,0x90,0x59,0xf9,0x4a,0x82,0x57,0x0e,0x23,
+  0xa8,0x08,0xa2,0x02,0x4b,0x87,0xd1,0x52,0x6a,0x2f,0x52,0xaa,0x99,0x11,0x95,0xda,
+  0xec,0x04,0xca,0x04,0x81,0xc7,0xd3,0x6e,0x97,0x32,0xa7,0x08,0x9d,0xb5,0xf5,0x9e,
+  0x9c,0xf7,0xb0,0x8e,0xc2,0x5e,0x53,0x41,0x8f,0x51,0xd2,0xb9,0x22,0xee,0x5c,0x16,
+  0x75,0x9a,0x04,0x6d,0x8b,0xe9,0x4d,0xab,0xe9,0xcd,0xcb,0xd1,0x55,0xc6,0xb0,0x8a,
+  0xd5,0x9b,0x8a,0xe5,0x80,0xf2,0xa5,0xe8,0xaa,0xe5,0xda,0xe1,0x55,0xed,0xd2,0x97,
+  0x5f,0xd7,0xee,0x2d,0x58,0x35,0x19,0x7b,0xfa,0xfa,0x6f,0x86,0x46,0x9d,0x3a,0x73,
+  0xf6,0xe8,0xb1,0x13,0x1f,0x7c,0x78,0xfa,0xec,0xf9,0x4b,0x8e,0x57,0x5d,0xdc,0xdc,
+  0xbd,0xfc,0xfc,0x6f,0xdc,0x08,0x8e,0x08,0x8f,0x88,0x8f,0x8d,0x4b,0x4d,0x4c,0x4e,
+  0x4d,0xcb,0x10,0x66,0x0a,0xa0,0x1c,0xe7,0xe7,0x89,0x0b,0xa1,0x22,0xe7,0x17,0x96,
+  0x17,0x95,0x94,0x17,0x15,0x4b,0x8b,0x4b,0x65,0xa5,0xe5,0xf2,0x92,0x72,0x7c,0xe6,
+  0x9b,0x54,0x5e,0x09,0x08,0x79,0x36,0x5d,0x45,0xb9,0xac,0x82,0x3c,0x50,0xae,0x82,
+  0x3c,0x7e,0xb0,0xb2,0x48,0x56,0x55,0x26,0x83,0x22,0x5e,0x49,0x1f,0xe8,0xc7,0x01,
+  0x79,0x92,0x5e,0x15,0x25,0xa6,0x80,0xcf,0x7e,0x54,0x30,0xdd,0x62,0x39,0xae,0x2a,
+  0x97,0x57,0x90,0x07,0xf7,0x29,0x99,0x59,0x96,0x98,0x63,0x55,0xce,0x4c,0xa9,0x40,
+  0x10,0xed,0xd2,0x67,0xd0,0xf1,0x78,0xaa,0xca,0xe5,0x4a,0x0b,0x11,0x0c,0x30,0x4b,
+  0x6c,0x39,0xf3,0xbb,0xbc,0x25,0x4a,0xbe,0x5c,0x46,0x96,0x25,0x13,0xfa,0x90,0x49,
+  0xfe,0x2a,0xb0,0xda,0xac,0x24,0x3e,0x3d,0xaf,0x82,0xd1,0x4d,0x51,0xc9,0x29,0x09,
+  0xb3,0x68,0x2c,0x4f,0xee,0x27,0xdb,0x2b,0x37,0xaf,0xfd,0x5f,0x63,0x2f,0xfb,0x6c,
+  0x40,0x5b,0xb9,0x72,0x3b,0x72,0x19,0x13,0x14,0xf6,0xd6,0x2a,0xac,0x56,0x29,0x2d,
+  0xe3,0x6b,0x23,0xd7,0xc6,0x5e,0x4e,0x73,0x1b,0xd3,0x78,0x82,0x14,0xe6,0xb5,0xe8,
+  0x70,0x85,0xa5,0x7a,0x76,0xfc,0x4c,0xe4,0x5a,0xfa,0xb0,0xa4,0x9c,0x51,0x95,0x3c,
+  0xb6,0x54,0x69,0x35,0x6b,0xdf,0xb1,0x72,0xa5,0xd4,0xc6,0x1b,0x56,0xf1,0xa5,0x4f,
+  0x86,0xbc,0x4d,0x5e,0x59,0x38,0xc7,0x5e,0x32,0xd8,0x71,0xbb,0xc2,0x4e,0xb8,0xd7,
+  0xda,0x47,0xb6,0x26,0x58,0xf9,0x93,0xcb,0x90,0xb5,0x92,0xd0,0x2a,0x16,0x64,0x84,
+  0x6e,0xf6,0x2a,0x62,0x91,0x1c,0xa2,0xcc,0xe7,0x59,0x2a,0xad,0xe2,0xb2,0x85,0x8c,
+  0x57,0x91,0xe8,0x80,0x3e,0x55,0xa5,0x95,0xcd,0x65,0x0d,0x23,0x85,0xad,0x1a,0x49,
+  0x97,0xb1,0xa0,0xcb,0x28,0xea,0x34,0x72,0x0f,0x45,0xbc,0xa7,0x81,0x7d,0xba,0xa3,
+  0xd9,0x22,0x49,0x17,0xf3,0xf4,0x48,0x2b,0xca,0x7c,0x7c,0x26,0xe4,0x2a,0xcc,0xe6,
+  0x92,0x55,0xd6,0x4f,0x98,0xbc,0x6d,0x57,0x44,0x9e,0xb4,0x89,0x8f,0x94,0xec,0x34,
+  0x8a,0xbb,0x8d,0xf9,0x5d,0xab,0x00,0xb9,0xac,0x08,0x60,0xcb,0x4a,0x41,0x35,0x72,
+  0x3a,0x80,0xbf,0x51,0x88,0x4f,0x6c,0x36,0x65,0xb5,0xac,0x66,0x35,0x9b,0x32,0x9b,
+  0x4d,0xe9,0xcd,0xa6,0xe4,0x7a,0x7c,0x93,0x6f,0x78,0xe5,0x6a,0xa8,0x72,0x25,0x48,
+  0xba,0xe4,0x5f,0xbe,0xe8,0x57,0xb6,0x18,0x5b,0xb9,0x5c,0x39,0x68,0x9c,0xff,0xfb,
+  0x99,0xf7,0x33,0xc0,0xdc,0xc2,0x42,0xdf,0x40,0x7f,0x7e,0x41,0x61,0xd0,0x8d,0xe0,
+  0xcb,0x0e,0x8e,0xa7,0x3f,0x3e,0xf7,0xf1,0xb9,0x4b,0x17,0xc8,0x2b,0x41,0xdd,0xdc,
+  0x7d,0x7c,0x7c,0x03,0xfd,0x82,0x6e,0xdd,0x0a,0x8b,0x0c,0x8f,0x8a,0x8b,0x8c,0x4e,
+  0x8c,0x4b,0x48,0x89,0x4f,0x4c,0x4d,0x4c,0xc9,0x4a,0x4d,0xcf,0x4a,0xcb,0xc8,0x86,
+  0x33,0x72,0x66,0x36,0x40,0x2e,0x00,0x79,0x01,0x41,0x5e,0xb6,0x40,0x9c,0x95,0x4d,
+  0x10,0xa1,0x18,0x71,0x82,0x64,0x64,0xe3,0x3b,0x11,0xe8,0x43,0xef,0xcd,0xef,0x1d,
+  0xc0,0x07,0xb0,0xe7,0xe2,0x5b,0x06,0xc8,0xd3,0xdd,0x81,0x98,0x79,0x40,0xbd,0x90,
+  0x79,0x79,0x41,0xa6,0x50,0x42,0x97,0x73,0xb3,0x54,0x04,0xf3,0x8a,0x04,0x91,0x65,
+  0x9b,0x83,0xa2,0x29,0xe7,0x2c,0x21,0x90,0xe5,0x66,0x33,0x6f,0x52,0xa0,0x2f,0x62,
+  0xc8,0xb3,0xec,0x9a,0x75,0x33,0x3f,0xfa,0x5e,0x68,0x7e,0x4d,0x40,0x96,0x9d,0x59,
+  0xf3,0x2b,0x15,0xe8,0x38,0xdb,0xcd,0xe5,0xba,0x40,0x46,0xcc,0xb4,0x94,0x2b,0x10,
+  0x33,0x80,0xfa,0xe7,0x92,0x87,0xe7,0xb3,0x83,0x64,0x2d,0xd5,0x39,0x43,0x28,0xc9,
+  0x66,0x38,0xf0,0xe9,0xad,0xed,0x35,0xc3,0x6d,0xed,0x35,0x2b,0xcf,0x30,0xf9,0x02,
+  0xed,0xe5,0x1e,0xb9,0x4f,0x1e,0xb6,0x6f,0x21,0x97,0xfa,0x99,0x89,0xaf,0x90,0x0a,
+  0x62,0x63,0x4d,0x25,0x0a,0x2c,0x7d,0xc5,0x99,0x29,0xb0,0x8d,0x6f,0xae,0xb9,0x9b,
+  0x23,0xe6,0xe4,0x72,0x06,0x62,0x57,0x40,0xa7,0xc4,0xf6,0xa3,0xc0,0x2d,0x64,0x15,
+  0xa0,0x3a,0x98,0x63,0x24,0xb4,0xb5,0x08,0x53,0x94,0x7b,0x1f,0x01,0xe5,0xcc,0x7b,
+  0xc5,0x00,0x25,0x96,0x70,0x1c,0x98,0x74,0x15,0x31,0x6b,0xa9,0x62,0x36,0xb1,0x60,
+  0x94,0xc9,0xce,0x61,0xa5,0x0b,0x59,0xe5,0xd7,0x90,0x7b,0x1b,0x3f,0x9b,0x83,0xc2,
+  0x86,0x29,0xdb,0x9c,0x84,0x16,0x6e,0xe7,0xf2,0xca,0xdc,0x15,0xb2,0xbe,0xe5,0x98,
+  0x8b,0xcc,0xf1,0xe5,0xbc,0x61,0xc5,0x0a,0x45,0xe7,0x98,0x23,0x6b,0x2d,0x57,0xc0,
+  0x99,0x9f,0xc7,0x4f,0x24,0x22,0x94,0x4d,0x7e,0xa1,0x84,0xe5,0x2f,0xc9,0x84,0x4f,
+  0x00,0x58,0x48,0xe8,0x33,0x61,0x4a,0x04,0x78,0x5e,0x16,0xb3,0x17,0x0a,0x04,0xb9,
+  0x25,0x59,0xc5,0xb5,0xd9,0xca,0x81,0x94,0x6a,0x5d,0x5a,0xe3,0x62,0x5a,0xe3,0x6a,
+  0x42,0xbd,0x31,0xb1,0xde,0x98,0xd6,0xb8,0x9c,0xd2,0xb0,0x9a,0xdc,0xb0,0x9a,0xda,
+  0xb8,0x92,0xd6,0xb4,0x0c,0x90,0xdc,0xb8,0x9a,0xdc,0x78,0x8f,0x75,0x53,0x1a,0x4d,
+  0xd4,0x84,0x8c,0x66,0x98,0x32,0xe2,0x20,0x79,0xf7,0x41,0x42,0x1d,0xe0,0x46,0x98,
+  0x02,0x1b,0x53,0x9b,0x4c,0xa9,0x8d,0x40,0x6c,0x24,0xaf,0x48,0x58,0x4d,0x69,0x5c,
+  0x49,0x20,0x2f,0xb2,0xe7,0xde,0xad,0x60,0x17,0xe2,0xe9,0x1b,0x25,0x58,0x84,0xfa,
+  0x2a,0x05,0xe5,0x1a,0x13,0xf1,0x35,0x0a,0xe0,0xc6,0xd5,0xc4,0x06,0xee,0x75,0x0c,
+  0x46,0xde,0x7b,0x19,0x8c,0x74,0x49,0x5c,0x8d,0x31,0xb6,0xc6,0x18,0x55,0x49,0x5e,
+  0xc9,0xa4,0x5c,0x81,0x73,0x6e,0xa0,0x6c,0xe9,0x86,0x6c,0xc9,0xab,0x74,0xe1,0xa6,
+  0x6c,0x11,0x0e,0xbc,0xf9,0x9d,0xab,0x9d,0xe3,0x46,0xcd,0xa2,0x69,0xf5,0xef,0x37,
+  0x59,0x7d,0x4e,0xb0,0xb2,0x6a,0x1c,0x9f,0x9c,0x50,0x55,0x55,0x25,0x24,0xa5,0x5c,
+  0x77,0x71,0xfb,0xe0,0xd4,0xc7,0x1f,0x9d,0xfe,0xf8,0xcc,0xd9,0x0b,0x17,0x2e,0x3b,
+  0x39,0x5d,0x75,0x76,0x76,0x71,0x77,0xf3,0xf4,0xf6,0xf2,0x0d,0xf4,0xf5,0x0b,0xf2,
+  0x0b,0x0c,0x09,0xb8,0x11,0x7a,0xe3,0x66,0xc4,0xcd,0x5b,0x11,0xb7,0xc2,0x22,0x42,
+  0xc2,0xa2,0x00,0xc2,0xc2,0xa3,0x43,0xc3,0xa2,0x42,0x23,0xa2,0x23,0x22,0xe3,0xc2,
+  0x23,0x62,0x22,0x22,0x63,0xa1,0x0d,0x8f,0x88,0x85,0x2e,0x81,0xd8,0xd0,0xb0,0x18,
+  0x32,0x15,0x4b,0x06,0x63,0x09,0x1e,0xcd,0xcd,0x92,0xc1,0x78,0xfe,0x2c,0x25,0x86,
+  0x41,0x7b,0xb3,0xf1,0x7c,0xce,0x1c,0xf1,0x6d,0x66,0xef,0x5c,0x10,0x47,0x60,0xbb,
+  0xf6,0xf6,0x82,0xd8,0xf1,0xbb,0x22,0x8e,0xff,0x1b,0xb3,0xf7,0x6e,0x03,0x6a,0xa9,
+  0x86,0x7d,0xce,0x6b,0x39,0xf6,0xae,0x7c,0xb5,0x06,0x31,0xdf,0xc0,0xf8,0xbb,0x95,
+  0x6b,0x4b,0x1c,0x1e,0x19,0x17,0x46,0x92,0x9f,0xb3,0xee,0x0e,0x1c,0xfb,0x09,0x72,
+  0xef,0x2a,0xaf,0xc2,0x22,0xe2,0x42,0x23,0xec,0x08,0xb2,0xab,0x33,0x3b,0x1b,0x7d,
+  0x5b,0xb9,0xf1,0x76,0x05,0x59,0x11,0x53,0xb9,0x36,0x8e,0x8d,0x5e,0x83,0x15,0xce,
+  0x86,0x46,0xc4,0xdc,0x8a,0x48,0x00,0x1a,0x68,0x43,0xc3,0xa2,0x43,0x22,0x92,0x42,
+  0xc3,0x63,0xc3,0x62,0x92,0x42,0x12,0x44,0xe1,0x69,0xc5,0xa1,0x79,0x6d,0x61,0xc5,
+  0x63,0x41,0xb2,0xe5,0x60,0x19,0xf3,0x46,0x3c,0x2c,0x01,0xe4,0xed,0x78,0x30,0x12,
+  0xac,0x5c,0x09,0xb6,0xf7,0x9a,0xbc,0x7b,0x05,0xa8,0x09,0x37,0x88,0x69,0x60,0xc8,
+  0x4d,0x39,0x8b,0xc0,0xa0,0x7c,0x39,0x48,0xbe,0x0c,0x23,0xc1,0x04,0xbf,0xa1,0x40,
+  0xb0,0xea,0x32,0x1c,0xe4,0x3c,0x6e,0x0a,0x9c,0xa5,0xbe,0x0a,0xb2,0x44,0x60,0x21,
+  0x2c,0xc7,0x59,0xa0,0x84,0xd3,0xab,0x8c,0xe1,0x40,0x17,0x9a,0xb5,0x92,0xaf,0x00,
+  0x43,0x7f,0xe9,0x12,0x10,0xf8,0x94,0x2d,0x7a,0x95,0x2d,0x7a,0x96,0x2d,0x7a,0x94,
+  0x2e,0xba,0x15,0x2d,0xba,0x15,0x2e,0xf8,0x49,0x17,0x12,0x6a,0x96,0x2a,0xfa,0x57,
+  0xfb,0x66,0x4d,0x0b,0xab,0x5f,0x7e,0xb5,0xfa,0x1b,0x86,0xe5,0xd5,0x65,0x8d,0x4e,
+  0xd3,0xde,0xd9,0x25,0xcc,0x15,0x87,0x47,0x46,0x07,0xde,0x08,0xf1,0xf1,0x0d,0x70,
+  0xf5,0xf4,0x71,0x71,0xf5,0x80,0x43,0xb1,0xa3,0x93,0xb3,0xe3,0x55,0x17,0x07,0x47,
+  0x67,0x47,0xa7,0xeb,0x8e,0x57,0xaf,0x3b,0x39,0xbb,0x39,0x5d,0x73,0x83,0xea,0xec,
+  0xec,0xe2,0x01,0xed,0x35,0x44,0x3c,0x5d,0x5c,0xbd,0x00,0xdc,0xdc,0xa1,0xf5,0x86,
+  0x71,0x82,0x78,0x5d,0x77,0xf3,0xba,0xee,0xea,0x8d,0xad,0x9b,0x97,0x8b,0x9b,0xf7,
+  0x75,0xa4,0xf1,0x26,0x94,0x64,0xd0,0x95,0x01,0xda,0x75,0x25,0x70,0xdd,0xd5,0xf3,
+  0x3a,0x70,0x73,0x23,0x04,0x2e,0x1e,0x74,0x21,0xb2,0x72,0x71,0xbf,0xee,0xea,0x65,
+  0xdd,0x45,0xf0,0x66,0x45,0x7b,0x62,0x97,0x2e,0x21,0x83,0xce,0x48,0xc3,0xcc,0x5e,
+  0x77,0xf5,0xc0,0x41,0x10,0xe1,0xce,0xa8,0x01,0x4a,0x12,0x04,0x18,0x52,0x3e,0x9e,
+  0xae,0x6e,0x8c,0x5c,0xe7,0xcf,0x26,0xd7,0xc5,0x8d,0xb1,0xc8,0xc5,0xd5,0x9d,0x32,
+  0xbf,0x43,0xb9,0xd7,0x19,0xbf,0x51,0xdc,0xdd,0x85,0x95,0x6b,0xee,0xf2,0x5c,0x87,
+  0x72,0xc9,0x12,0x32,0x4e,0x99,0xbb,0xbb,0xba,0x71,0x8e,0xfd,0xa2,0xec,0x75,0x71,
+  0xfd,0x04,0xb9,0x34,0xe2,0x5c,0xb8,0xa9,0x5c,0x1a,0x5f,0x17,0x92,0x09,0x9c,0x38,
+  0x3a,0xce,0x00,0x95,0x62,0x99,0x2a,0x9c,0xbd,0x44,0x84,0xb5,0xaf,0x78,0xde,0x70,
+  0x67,0x4c,0xe3,0x19,0x0e,0x59,0x04,0xf4,0x8c,0x14,0xea,0x58,0x1b,0x41,0x98,0x6c,
+  0x40,0x63,0x93,0xa2,0x36,0x72,0xcd,0xa9,0x68,0xab,0xa4,0x2b,0x26,0xc0,0x9a,0x4a,
+  0x5a,0x07,0xd4,0x95,0xe1,0xe6,0xc2,0x7a,0xcc,0x85,0xe7,0xae,0xdb,0xfb,0xd9,0x6e,
+  0x50,0xe8,0x46,0xb3,0x4d,0x42,0xda,0x75,0x75,0x47,0xc4,0x95,0x65,0xee,0xea,0xe6,
+  0x41,0x23,0x65,0xb9,0x07,0x3d,0xaf,0xd3,0x9d,0xeb,0xc6,0x68,0x62,0xb3,0x71,0xac,
+  0x37,0xac,0xb5,0x5c,0x57,0xf3,0x5a,0x7e,0xd7,0xcd,0xc3,0xcb,0xd9,0x95,0x38,0x07,
+  0x63,0x01,0xa9,0xe8,0xe3,0xe2,0xe6,0x79,0xdd,0x3d,0xc0,0xc5,0xeb,0x96,0x8b,0x5f,
+  0xe4,0xb5,0xa0,0x44,0xd7,0x30,0x91,0x7b,0xac,0xea,0x6a,0x5a,0x9f,0xa3,0x60,0xfc,
+  0x9a,0x58,0xe7,0x24,0x99,0x77,0x2e,0x30,0x38,0x89,0x11,0x1c,0xc5,0x0c,0x82,0x78,
+  0x1e,0x82,0x93,0xf8,0xde,0x06,0x6a,0x82,0x5d,0x43,0xae,0x4a,0x10,0xac,0x06,0x9d,
+  0xf3,0xe7,0x6c,0x29,0x9d,0x25,0x0b,0x9f,0x88,0xd8,0x8a,0xb8,0x96,0x4f,0x10,0x22,
+  0xc2,0x21,0xd7,0xe0,0x5a,0x60,0x1e,0x77,0x29,0x5c,0xf0,0x2a,0x32,0xf8,0x96,0x2c,
+  0x04,0x4a,0x17,0x6f,0xc9,0x17,0xa2,0xaa,0x16,0x13,0xaa,0x96,0xb2,0x9b,0x56,0x6a,
+  0x87,0x8d,0xd3,0xf3,0x46,0xc3,0xaa,0xe9,0xef,0x3f,0x29,0xfa,0x2b,0xc3,0xca,0xea,
+  0x8a,0x61,0x71,0x49,0xa3,0xd3,0x4e,0x4c,0x4d,0x0d,0x0e,0xa9,0xbb,0x7a,0xba,0x9b,
+  0x9a,0xdb,0x55,0x15,0x15,0x85,0xc5,0xa5,0xb9,0xe2,0xfc,0x3c,0x09,0x03,0xe2,0xfc,
+  0x42,0x84,0x82,0x02,0x49,0x41,0x31,0x74,0x25,0x05,0x85,0x00,0xe2,0x7c,0xe8,0x16,
+  0xe5,0x49,0x0a,0xfe,0x5f,0x7b,0x75,0xd0,0xda,0x36,0x0c,0x05,0x00,0xf8,0xff,0xff,
+  0x9d,0xb6,0x89,0x65,0x99,0x30,0x56,0x76,0x18,0x8c,0x41,0x21,0xb1,0xc7,0x0e,0xa3,
+  0xb0,0xc3,0x60,0x3b,0xb4,0x30,0x36,0x12,0xb7,0x39,0x4c,0xb6,0xec,0xd4,0x49,0x9b,
+  0xac,0x2b,0xec,0xb0,0xf1,0xc1,0x87,0x78,0xcf,0x96,0xf4,0x9e,0x8c,0x42,0xe6,0xa1,
+  0xea,0xd2,0xb2,0x0b,0xba,0xb1,0x9b,0x56,0xe5,0xb7,0xc3,0xcc,0x9d,0xfe,0xe1,0xbc,
+  0x7f,0xd8,0xab,0xc6,0x27,0x0f,0xe3,0x64,0xfe,0x41,0x1a,0xc7,0x85,0xd5,0x64,0x61,
+  0x9c,0x96,0x18,0xf6,0xcc,0x0b,0x63,0xdf,0x4f,0xd8,0x6f,0x26,0xe6,0x69,0x0f,0x75,
+  0x73,0xcf,0x2f,0xae,0x9b,0xaa,0x4c,0xd2,0x45,0xf7,0xf6,0x79,0x75,0x9f,0x3a,0x42,
+  0x5a,0x3b,0x49,0xc3,0x70,0xae,0xa1,0xee,0x7e,0x57,0xbb,0x53,0xe7,0x93,0xfe,0xc5,
+  0xf3,0x9e,0xac,0xbb,0xdb,0x6d,0x5a,0x77,0x3e,0xf6,0x3f,0x96,0x1b,0xda,0xc8,0x77,
+  0x63,0xd8,0x27,0x2e,0x0e,0xae,0xca,0x6f,0xee,0xc6,0xee,0x6d,0x7c,0x5e,0x1b,0xf1,
+  0x78,0xa1,0x93,0x75,0x0f,0x0a,0xbd,0xb0,0xc9,0xa7,0xee,0xe4,0xa3,0x9d,0x4f,0x7d,
+  0xe7,0x3f,0xbb,0xfc,0x63,0x9a,0x82,0xd0,0x5f,0xa1,0xfd,0xdf,0xc2,0xfe,0x45,0x0a,
+  0xe5,0x5e,0xcf,0x47,0x26,0x1f,0xab,0x7b,0x70,0xde,0xe9,0x27,0x9d,0x85,0xd0,0xf7,
+  0x50,0x85,0xf8,0xaa,0x5a,0x5c,0xc6,0xd7,0xef,0xc2,0x65,0x1d,0xdf,0x5e,0x97,0xef,
+  0xbf,0xce,0xae,0x6e,0x8b,0xe5,0x8f,0x62,0xb5,0x2e,0x9a,0x76,0x5e,0xb7,0x65,0xbd,
+  0x99,0x37,0x6d,0xfc,0xd0,0x05,0x5d,0x5c,0xb7,0x29,0xcd,0xf1,0x2c,0x8d,0xcd,0x26,
+  0xc7,0x65,0x8e,0xff,0xcd,0x34,0x9f,0xa8,0x48,0x67,0x4c,0xc1,0xa3,0xf4,0x60,0xf2,
+  0xc5,0x6a,0x7d,0xd1,0x7f,0x96,0x21,0xad,0xdb,0x62,0xd5,0x8d,0xf9,0xe1,0xf9,0x18,
+  0x9c,0xad,0xfa,0xa0,0xe9,0x82,0x59,0xdd,0x86,0x26,0x8d,0xc3,0xce,0x39,0x0d,0xcb,
+  0xf5,0x59,0x5a,0xdb,0xb4,0xe7,0xcb,0x4d,0x1a,0xfb,0x1d,0xd2,0x3e,0x9b,0xf4,0xa9,
+  0xdf,0x7c,0x6a,0xaf,0x3e,0xdf,0x7d,0xfc,0x76,0x7f,0x7d,0xb3,0xfd,0xf2,0x7d,0x7b,
+  0xfb,0xf3,0x7e,0x7d,0xb7,0x4d,0xb6,0xfe,0x73,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0xfe,0x6b,0xbf,0x00,0xff,0xcf,0xfd,0x4c,0x36,0x10,0x0e,
+  0x00,
diff --git a/u-boot/board/esd/hub405/Makefile b/u-boot/board/esd/hub405/Makefile
new file mode 100644
index 0000000..401622f
--- /dev/null
+++ b/u-boot/board/esd/hub405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/hub405/flash.c b/u-boot/board/esd/hub405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/hub405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/hub405/hub405.c b/u-boot/board/esd/hub405/hub405.c
new file mode 100644
index 0000000..d17c415
--- /dev/null
+++ b/u-boot/board/esd/hub405/hub405.c
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_revision(void)
+{
+	unsigned long osrl_reg;
+	unsigned long isr1l_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Get version of HUB405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pin(s) (IRQ6/GPIO23)
+	 */
+	osrl_reg = in_be32((void *)GPIO0_OSRH);
+	isr1l_reg = in_be32((void *)GPIO0_ISR1H);
+	tcr_reg = in_be32((void *)GPIO0_TCR);
+	out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000);     /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000);    /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in_be32((void *)GPIO0_IR) & 0x00000100;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out_be32((void *)GPIO0_OSRH, osrl_reg);                   /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1l_reg);                 /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x00000100) {
+		/* Revision 1.1 or 1.2 detected */
+		return 1;
+	}
+
+	/* Revision 1.0 */
+	return 0;
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+#define LED_REG (DUART0_BA + 0x20)
+int misc_init_r (void)
+{
+	unsigned long val;
+	int delay, flashcnt;
+	char *str;
+	char hw_rev[4];
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)(DUART0_BA + 4), 0x08);
+	out_8((void *)(DUART1_BA + 4), 0x08);
+	out_8((void *)(DUART2_BA + 4), 0x08);
+	out_8((void *)(DUART3_BA + 4), 0x08);
+
+	/*
+	 * Set RS232/RS422 control (RS232 = high on GPIO)
+	 */
+	val = in_be32((void *)GPIO0_OR);
+	val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 |
+		 CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
+
+	str = getenv("phys0");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART2_RS232;
+
+	str = getenv("phys1");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART3_RS232;
+
+	str = getenv("phys2");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART4_RS232;
+
+	str = getenv("phys3");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART5_RS232;
+
+	out_be32((void *)GPIO0_OR, val);
+
+	/*
+	 * check board type and setup AP power
+	 */
+	str = getenv("bd_type"); /* this is only set on non prototype hardware */
+	if (str != NULL) {
+		if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
+			unsigned char led_reg_default = 0;
+			str = getenv("ap_pwr");
+			if (!str || (str && (str[0] == '1')))
+				led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
+
+			/*
+			 * Flash LEDs
+			 */
+			for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+				/* LED_A..D off */
+				out_8((void *)LED_REG, led_reg_default);
+				for (delay = 0; delay < 100; delay++)
+					udelay(1000);
+				/* LED_A..D on */
+				out_8((void *)LED_REG, led_reg_default | 0xf0);
+				for (delay = 0; delay < 50; delay++)
+					udelay(1000);
+			}
+			out_8((void *)LED_REG, led_reg_default);
+		}
+	}
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Store hardware revision in environment for further processing
+	 */
+	sprintf(hw_rev, "1.%ld", gd->board_type);
+	setenv("hw_rev", hw_rev);
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HUB405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld)\n", gd->board_type);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
diff --git a/u-boot/board/esd/mecp5123/Makefile b/u-boot/board/esd/mecp5123/Makefile
new file mode 100644
index 0000000..30dba23
--- /dev/null
+++ b/u-boot/board/esd/mecp5123/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/mecp5123/mecp5123.c b/u-boot/board/esd/mecp5123/mecp5123.c
new file mode 100644
index 0000000..748ad7c
--- /dev/null
+++ b/u-boot/board/esd/mecp5123/mecp5123.c
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
+			 CLOCK_SCCR2_I2C_EN)
+
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
+		return -1;
+
+	if (state == 0)
+		setbits_be32(&im->gpio.gpdat, 0x00100000);
+	else
+		clrbits_be32(&im->gpio.gpdat, 0x00100000);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+	int i;
+
+	/*
+	 * Initialize Local Window for NOR FLASH access
+	 */
+	out_be32(&im->sysconf.lpcs0aw,
+		 CSAW_START(CONFIG_SYS_FLASH_BASE) |
+		 CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
+	sync_law(&im->sysconf.lpcs0aw);
+
+	/*
+	 * Initialize Local Window for boot access
+	 */
+	out_be32(&im->sysconf.lpbaw,
+		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
+	sync_law(&im->sysconf.lpbaw);
+
+	/*
+	 * Initialize Local Window for VPC3 access
+	 */
+	out_be32(&im->sysconf.lpcs1aw,
+		 CSAW_START(CONFIG_SYS_VPC3_BASE) |
+		 CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
+	sync_law(&im->sysconf.lpcs1aw);
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	/*
+	 * Configure VPC3 Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+	if (SVR_MJREV(spridr) >= 2)
+		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	/*
+	 * Configure MSCAN clocks
+	 */
+	for (i=0; i<4; ++i) {
+		out_be32(&im->clk.msccr[i], 0x00300000);
+		out_be32(&im->clk.msccr[i], 0x00310000);
+	}
+
+	/*
+	 * Configure GPIO's
+	 */
+	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
+	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
+	setbits_be32(&im->gpio.gpdir, 0x001000e0);
+	setbits_be32(&im->gpio.gpdat, 0x00100000);
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 val;
+
+	/*
+	 * Optimize access to profibus chip (VPC3) on the local bus
+	 */
+
+	/*
+	 * Select 1:1 for LPC_DIV
+	 */
+	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
+	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
+
+	/*
+	 * Configure LPC Chips Select Deadcycle Control Register
+	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
+	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
+
+	/*
+	 * Configure LPC Chips Select Holdcycle Control Register
+	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
+	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
+
+	return 0;
+}
+
+static iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SELECT LPC_CS1 */
+	{
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC7_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC9_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC11_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC0=SELECT IRQ0 */
+	{
+		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	puts("Board: MECP_5123\n");
+
+	/*
+	 * Initialize function mux & slew rate IO inter alia on IO
+	 * Pins
+	 */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	spridr = in_be32(&im->sysconf.spridr);
+	if (SVR_MJREV(spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/esd/mecp5200/Makefile b/u-boot/board/esd/mecp5200/Makefile
new file mode 100644
index 0000000..22ee984
--- /dev/null
+++ b/u-boot/board/esd/mecp5200/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/mecp5200/mecp5200.c b/u-boot/board/esd/mecp5200/mecp5200.c
new file mode 100644
index 0000000..3192450
--- /dev/null
+++ b/u-boot/board/esd/mecp5200/mecp5200.c
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPX CPU5200 (mecp5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == CONFIG_SYS_FLASH_SIZE) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset)
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	else
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/esd/mecp5200/mt46v16m16-75.h b/u-boot/board/esd/mecp5200/mt46v16m16-75.h
new file mode 100644
index 0000000..cf63806
--- /dev/null
+++ b/u-boot/board/esd/mecp5200/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/esd/meesc/Makefile b/u-boot/board/esd/meesc/Makefile
new file mode 100644
index 0000000..b414479
--- /dev/null
+++ b/u-boot/board/esd/meesc/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/meesc/config.mk b/u-boot/board/esd/meesc/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/u-boot/board/esd/meesc/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/u-boot/board/esd/meesc/meesc.c b/u-boot/board/esd/meesc/meesc.c
new file mode 100644
index 0000000..41fa3e1
--- /dev/null
+++ b/u-boot/board/esd/meesc/meesc.c
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void meesc_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void meesc_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	/* Enable clock */
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void meesc_ethercat_hw_init(void)
+{
+	at91_smc_t 	*smc1 	= (at91_smc_t *) AT91_SMC1_BASE;
+
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc1->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+		&smc1->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+		&smc1->cs[0].cycle);
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+	u_char hw_type;	/* hardware type */
+
+	/* read the "Type" register of the ET1100 controller */
+	hw_type = readb(CONFIG_ET1100_BASE);
+
+	switch (hw_type) {
+	case 0x11:
+	case 0x3F:
+		/* ET1100 present, arch number of MEESC-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_MEESC;
+		puts("Board: CAN-EtherCAT Gateway");
+		break;
+	case 0xFF:
+		/* no ET1100 present, arch number of EtherCAN/2-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+		puts("Board: EtherCAN/2 Gateway");
+		/* switch on LED1D */
+		at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
+		break;
+	default:
+		/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+		printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
+		puts("Board: EtherCAN/2 Gateway");
+		break;
+	}
+	if (getenv_f("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = getenv("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char		*str;
+	char		buf[32];
+	at91_pmc_t	*pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+	/*
+	 * Normally the processor clock has a divisor of 2.
+	 * In some cases this this needs to be set to 4.
+	 * Check the user has set environment mdiv to 4 to change the divisor.
+	 */
+	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
+		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
+			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
+		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+		serial_setbrg();
+		/* Notify the user that the clock is not default */
+		printf("Setting master clock to %s MHz\n",
+			strmhz(buf, get_mck_clk_rate()));
+	}
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Peripheral Clock Enable Register */
+	writel(1 << AT91SAM9263_ID_PIOA |
+		1 << AT91SAM9263_ID_PIOB |
+		1 << AT91SAM9263_ID_PIOCDE |
+		1 << AT91SAM9263_ID_UHP,
+		&pmc->pcer);
+
+	/* initialize ET1100 Controller */
+	meesc_ethercat_hw_init();
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	meesc_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	meesc_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
diff --git a/u-boot/board/esd/meesc/partition.c b/u-boot/board/esd/meesc/partition.c
new file mode 100644
index 0000000..df0e1db
--- /dev/null
+++ b/u-boot/board/esd/meesc/partition.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
diff --git a/u-boot/board/esd/ocrtc/Makefile b/u-boot/board/esd/ocrtc/Makefile
new file mode 100644
index 0000000..f9274b5
--- /dev/null
+++ b/u-boot/board/esd/ocrtc/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/ocrtc/cmd_ocrtc.c b/u-boot/board/esd/ocrtc/cmd_ocrtc.c
new file mode 100644
index 0000000..b59689b
--- /dev/null
+++ b/u-boot/board/esd/ocrtc/cmd_ocrtc.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <asm/4xx_pci.h>
+
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int idx = 1;	  /* start at 1 (skip device 0) */
+	pci_dev_t bdf = 0;
+	u32 addr;
+
+	while (bdf >= 0) {
+		if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
+			break;
+		}
+		printf("Found device nr %d at %x!\n", idx-1, bdf);
+		pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+		addr &= ~0xf;
+		*(u32 *)addr = (bdf & 0x0000f800) >> 11;
+		printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	setdevice,	1,	1,	do_setdevice,
+	"Set device number on pci adapter boards",
+	""
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 device;
+	char str[32];
+
+	device = *(u32 *)0x0;
+	device = 0x16 - device;      /* calculate vxworks bp slot id */
+	sprintf(str, "%d", device);
+	setenv("slot", str);
+	printf("Variabel slot set to %x\n", device);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getdevice,	1,	1,	do_getdevice,
+	"Get device number and set slot env variable",
+	""
+);
+
+#endif
diff --git a/u-boot/board/esd/ocrtc/flash.c b/u-boot/board/esd/ocrtc/flash.c
new file mode 100644
index 0000000..c83e594
--- /dev/null
+++ b/u-boot/board/esd/ocrtc/flash.c
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		base_b1 = -size_b1;
+		switch (size_b1) {
+		case 1 << 20:
+			size_val = 0;
+			break;
+		case 2 << 20:
+			size_val = 1;
+			break;
+		case 4 << 20:
+			size_val = 2;
+			break;
+		case 8 << 20:
+			size_val = 3;
+			break;
+		case 16 << 20:
+			size_val = 4;
+			break;
+		}
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*          printf("PB1CR = %x\n", pbcr); */
+	}
+
+	if (size_b0) {
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		base_b0 = base_b1 - size_b0;
+		switch (size_b1) {
+		case 1 << 20:
+			size_val = 0;
+			break;
+		case 2 << 20:
+			size_val = 1;
+			break;
+		case 4 << 20:
+			size_val = 2;
+			break;
+		case 8 << 20:
+			size_val = 3;
+			break;
+		case 16 << 20:
+			size_val = 4;
+			break;
+		}
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*            printf("PB0CR = %x\n", pbcr); */
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/u-boot/board/esd/ocrtc/ocrtc.c b/u-boot/board/esd/ocrtc/ocrtc.c
new file mode 100644
index 0000000..24c92e3
--- /dev/null
+++ b/u-boot/board/esd/ocrtc/ocrtc.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "ocrtc.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <command.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
+	 * transfers, set device-paced timeout to 256 cycles
+	 */
+	mtebc (EBC0_CFG, 0x20400000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+#ifdef CONFIG_OCRTC
+		puts ("### No HW ID - assuming OCRTC");
+#endif
+#ifdef CONFIG_ORSG
+		puts ("### No HW ID - assuming ORSG");
+#endif
+	} else {
+		puts (str);
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return (0);
+}
diff --git a/u-boot/board/esd/ocrtc/ocrtc.h b/u-boot/board/esd/ocrtc/ocrtc.h
new file mode 100644
index 0000000..b50d521
--- /dev/null
+++ b/u-boot/board/esd/ocrtc/ocrtc.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/u-boot/board/esd/otc570/Makefile b/u-boot/board/esd/otc570/Makefile
new file mode 100644
index 0000000..87657ff
--- /dev/null
+++ b/u-boot/board/esd/otc570/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y				+= $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH)	+= partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/otc570/config.mk b/u-boot/board/esd/otc570/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/u-boot/board/esd/otc570/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/u-boot/board/esd/otc570/otc570.c b/u-boot/board/esd/otc570/otc570.c
new file mode 100644
index 0000000..410d8b4
--- /dev/null
+++ b/u-boot/board/esd/otc570/otc570.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <atmel_lcdc.h>
+#include <lcd.h>
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void otc570_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_DBW_8 |
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void otc570_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	/* Enable clock */
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void otc570_ethercat_hw_init(void)
+{
+	at91_smc_t 	*smc1 	= (at91_smc_t *) AT91_SMC1_BASE;
+
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc1->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+		&smc1->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+		&smc1->cs[0].cycle);
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
+}
+
+#ifdef CONFIG_LCD
+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
+vidinfo_t panel_info = {
+	.vl_col =		640,
+	.vl_row =		480,
+	.vl_clk =		25175000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+
+	.vl_bpix =		3,	/* Bits per pixel, 0 = 1bit, 3 = 8bit */
+	.vl_tft =		1,	/* 0 = passive, 1 = TFT */
+	.vl_vsync_len =		1,	/* Length of vertical sync in NOL */
+	.vl_upper_margin =	35,	/* Idle lines at the frame start */
+	.vl_lower_margin =	5,	/* Idle lines at the end of the frame */
+	.vl_hsync_len =		5,	/* Width of the LCDHSYNC pulse */
+	.vl_left_margin =	112,	/* Idle cycles at the line beginning */
+	.vl_right_margin =	1,	/* Idle cycles at the end of the line */
+
+	.mmio =			AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power down */
+}
+
+static void otc570_lcd_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+	at91_set_pio_output(AT91_PIO_PORTA, 30, 1);	/* PCI */
+
+	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
+	gd->fb_base = CONFIG_OTC570_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	lcd_printf("\n%s\n", U_BOOT_VERSION);
+	lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME,
+					strmhz(temp, get_cpu_clk_rate()));
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+	lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
+	lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
+	lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+
+	puts("Board: esd ARM9 HMI Panel - OTC570");
+	if (getenv_f("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = getenv("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char		str[64];
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);	/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* RXD0 */
+	writel(1 << AT91SAM9263_ID_US0,	&pmc->pcer);
+	/* Set USART_MODE = 1 (RS485) */
+	writel(1, 0xFFF8C004);
+
+	printf("USART0: ");
+
+	if (getenv_f("usart0", str, sizeof(str)) == -1) {
+		printf("No entry - assuming 1-wire\n");
+		/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
+		at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+	} else {
+		if (strcmp(str, "1-wire") == 0) {
+			printf("%s\n", str);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+		} else if (strcmp(str, "rs485") == 0) {
+			printf("%s\n", str);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+		} else {
+			printf("Wrong entry - assuming 1-wire ");
+			printf("(valid values are '1-wire' or 'rs485')\n");
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+		}
+	}
+	printf("Display memory address: 0x%08lX\n", gd->fb_base);
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Peripheral Clock Enable Register */
+	writel(	1 << AT91SAM9263_ID_PIOA |
+		1 << AT91SAM9263_ID_PIOB |
+		1 << AT91SAM9263_ID_PIOCDE |
+		1 << AT91SAM9263_ID_TWI |
+		1 << AT91SAM9263_ID_SPI0 |
+		1 << AT91SAM9263_ID_LCDC |
+		1 << AT91SAM9263_ID_UHP,
+		&pmc->pcer);
+
+	/* arch number of OTC570-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OTC570;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	otc570_nand_hw_init();
+#endif
+	otc570_ethercat_hw_init();
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	otc570_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	otc570_lcd_hw_init();
+#endif
+	return 0;
+}
diff --git a/u-boot/board/esd/otc570/partition.c b/u-boot/board/esd/otc570/partition.c
new file mode 100644
index 0000000..df0e1db
--- /dev/null
+++ b/u-boot/board/esd/otc570/partition.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
diff --git a/u-boot/board/esd/pci405/Makefile b/u-boot/board/esd/pci405/Makefile
new file mode 100644
index 0000000..d551ec9
--- /dev/null
+++ b/u-boot/board/esd/pci405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o cmd_pci405.o
+SOBJS	= writeibm.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+#	$(call cmd_link_o_target, $(OBJS))
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/pci405/cmd_pci405.c b/u-boot/board/esd/pci405/cmd_pci405.c
new file mode 100644
index 0000000..13f9019
--- /dev/null
+++ b/u-boot/board/esd/pci405/cmd_pci405.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2002-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/processor.h>
+
+#include "pci405.h"
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int *ptr = 0;
+	int count = 0;
+	int count2 = 0;
+	int status;
+	int i;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+
+	/*
+	 * Mark sync address
+	 */
+	ptr = 0;
+	*ptr = 0xffffffff;
+	puts("\nWaiting for image from pci host -");
+
+	/*
+	 * Wait for host to write the start address
+	 */
+	while (*ptr == 0xffffffff) {
+		count++;
+		if (!(count % 100)) {
+			count2++;
+			putc(0x08); /* backspace */
+			putc(str[count2 % 4]);
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	if (*ptr == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Save own pci configuration in PRAM
+		 */
+		memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
+		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+		for (i=0; i<0x40; i+=4) {
+			pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
+		}
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		*ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+
+		printf("\nStoring PCI Configuration Regs...\n");
+	} else {
+		sprintf(addr, "%08x", *ptr);
+
+		/*
+		 * Boot image via bootm
+		 */
+		printf("\nBooting Image at addr 0x%s ...\n", addr);
+		setenv("loadaddr", addr);
+
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootm (cmdtp, 0, 1, local_args);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"Wait for pci-image and boot it",
+	""
+);
+#endif
diff --git a/u-boot/board/esd/pci405/flash.c b/u-boot/board/esd/pci405/flash.c
new file mode 100644
index 0000000..6ca6e4b
--- /dev/null
+++ b/u-boot/board/esd/pci405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/pci405/fpgadata.c b/u-boot/board/esd/pci405/fpgadata.c
new file mode 100644
index 0000000..c64ad95
--- /dev/null
+++ b/u-boot/board/esd/pci405/fpgadata.c
@@ -0,0 +1,746 @@
+  0x1f,0x8b,0x08,0x08,0xcd,0x78,0x61,0x3f,0x00,0x03,0x70,0x63,0x69,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xed,0x9c,0x7f,0x78,0x14,0xc7,
+  0x99,0xe7,0xdf,0xae,0xee,0x11,0x2d,0xcd,0x88,0x69,0x89,0x11,0x1e,0x3b,0x32,0xdb,
+  0x1a,0x09,0x3c,0xc1,0x23,0x69,0x18,0x61,0x85,0x60,0x79,0xd4,0x8c,0x04,0x19,0x1b,
+  0xd9,0x4c,0x6c,0x27,0x61,0xf3,0xf8,0xc9,0x8e,0x1d,0x92,0x23,0x59,0x92,0x47,0x90,
+  0xdc,0x2e,0x49,0x9c,0x6c,0x8d,0x24,0xd0,0x00,0xb2,0x19,0x30,0x97,0xb0,0x59,0xce,
+  0x3b,0x60,0x12,0x0b,0x9b,0x64,0x07,0x61,0x1b,0x61,0x88,0xdd,0x92,0x85,0x23,0x40,
+  0x06,0x85,0xf5,0x79,0xb1,0xcd,0xe2,0xc1,0x91,0xbd,0xb2,0x23,0x63,0x19,0xb3,0x8e,
+  0x00,0x19,0xdd,0x5b,0xdd,0x3d,0xdd,0x2d,0xe1,0xfd,0x71,0xb7,0xf7,0xdc,0xde,0xf3,
+  0x9c,0xdb,0x7f,0xb8,0x50,0xa9,0xba,0xab,0xab,0xde,0xfa,0xd4,0xf7,0x7d,0xdf,0x6a,
+  0x41,0xbe,0x7b,0x54,0xff,0x0f,0x80,0xbb,0x1f,0xa4,0xe6,0xaf,0x7f,0x6b,0x7e,0xf0,
+  0x96,0x3f,0x9b,0xf7,0x67,0xc1,0xf9,0x55,0xdf,0xfd,0xfa,0x0a,0x78,0x00,0x0a,0x42,
+  0xdf,0x9b,0x77,0xcb,0xf7,0x57,0xcf,0x9b,0x3f,0x1f,0xbe,0x0e,0xce,0x50,0x30,0x58,
+  0x53,0x1d,0x5c,0x50,0x1d,0xba,0x05,0x56,0x40,0xfe,0xbc,0x05,0x0b,0x83,0xb7,0x2c,
+  0x9c,0x57,0x03,0xdf,0x00,0x88,0x27,0x27,0xf0,0x7a,0xe2,0xaf,0xbf,0xf4,0xcd,0x20,
+  0x50,0x0e,0x00,0xa6,0x05,0xb9,0x38,0xfb,0x7f,0x5e,0x90,0x93,0x39,0xa0,0xf5,0x95,
+  0x41,0x50,0xd9,0xbf,0xc1,0xa8,0xcf,0x0f,0x82,0x6c,0xff,0x37,0x17,0x04,0x05,0x62,
+  0xe0,0xf9,0x0e,0x14,0x4b,0x30,0xe5,0xe2,0x14,0x81,0xea,0xa5,0x7f,0xad,0x8e,0x4c,
+  0xad,0x62,0xd7,0xbf,0xa3,0xae,0xf8,0x13,0xaa,0x84,0xff,0x58,0xdd,0x84,0x04,0x71,
+  0xf0,0x42,0x1e,0x70,0xd4,0x2c,0xd4,0xf7,0xe9,0x75,0xaa,0x63,0x5c,0x7e,0xbd,0x68,
+  0x46,0x9f,0xbb,0x9f,0x8c,0xd3,0x93,0x05,0x3e,0xa5,0x70,0x8c,0x0f,0x42,0xb3,0xde,
+  0x23,0xe9,0x3d,0xba,0x59,0x29,0xff,0x47,0x67,0x92,0x5c,0x8d,0x6c,0x96,0x7d,0x59,
+  0x31,0x58,0x20,0x0b,0x41,0xad,0x2e,0xe9,0x18,0x96,0x1f,0x89,0x77,0xf6,0x3b,0x81,
+  0x74,0xc0,0x63,0xa2,0x4f,0xc9,0x0f,0x92,0x5d,0x9c,0xde,0x4e,0x2d,0xe9,0x74,0x3c,
+  0x29,0xcc,0x55,0x9d,0x69,0x18,0x11,0x9e,0x04,0xd6,0x8e,0x64,0x84,0xb8,0xde,0xa7,
+  0x92,0x63,0xf0,0xba,0xb0,0x50,0x75,0xb7,0xf1,0x7b,0xe1,0x0f,0x10,0x6a,0x2e,0xcc,
+  0xf0,0x54,0xd0,0xdb,0x65,0xb9,0x27,0x94,0xd7,0xe1,0x73,0x3d,0xee,0x97,0x1b,0x46,
+  0xe0,0x1f,0xe0,0x79,0xd5,0x3d,0xca,0xaf,0x05,0xbd,0x9d,0x22,0xed,0x26,0xc7,0x21,
+  0xa4,0xba,0x93,0xfc,0x00,0x1c,0x87,0xae,0xd8,0xf4,0x0c,0x2f,0x09,0xb2,0x56,0xd7,
+  0xef,0xa8,0xfb,0xb6,0x9b,0x94,0xab,0xce,0xa7,0xc8,0x55,0x79,0x33,0xc8,0xaa,0x98,
+  0x21,0x21,0x9c,0x3f,0xed,0x9e,0x8e,0x3b,0xc9,0x26,0xfc,0x91,0x33,0xd8,0x32,0x00,
+  0x8f,0x80,0x4c,0x0b,0x82,0x64,0x01,0xce,0x2c,0xbb,0xe2,0xdc,0xac,0xb6,0x76,0x5a,
+  0x96,0x75,0xfe,0x29,0x39,0x0b,0x3f,0xa3,0xe5,0x9d,0xe2,0x5a,0xe2,0x35,0xda,0x45,
+  0x45,0x11,0x5e,0x68,0x09,0x1e,0x75,0xcf,0xe7,0x07,0x92,0xaf,0xd3,0xe0,0xf0,0x5d,
+  0x41,0x67,0xb1,0x31,0x6f,0xca,0x8d,0xdd,0xf4,0x7d,0x8e,0x75,0xaf,0x61,0x5c,0x7e,
+  0x1f,0x6e,0xa3,0xee,0x0f,0xf8,0xc1,0x3c,0xbd,0x9f,0x9d,0xdc,0xb0,0xe0,0xfc,0x76,
+  0x78,0x60,0x73,0x95,0x33,0x90,0xbe,0x22,0x97,0x52,0x57,0x86,0x7f,0xd7,0x18,0xcf,
+  0x68,0xd1,0xc6,0x64,0xbb,0x5c,0x39,0xe0,0x8c,0xb5,0x94,0xc2,0x81,0x95,0x95,0x54,
+  0x6c,0x26,0xa7,0x8c,0x71,0xa1,0xf0,0xa8,0xf2,0xf8,0xb6,0xca,0xec,0xa6,0xe1,0xbc,
+  0x59,0x70,0x80,0x56,0xa7,0xb1,0x2f,0x59,0x30,0xde,0x4f,0x3a,0x91,0x78,0x0c,0x56,
+  0xa9,0xce,0xd0,0xcc,0x26,0xd8,0x0f,0x81,0x14,0x8e,0xe7,0x05,0x63,0x1e,0x86,0x4b,
+  0x0e,0xb5,0xbc,0x0b,0x61,0xea,0x4e,0xf3,0x7e,0xb8,0x0c,0xf5,0x89,0x1d,0x69,0xfe,
+  0xb2,0x71,0xcf,0x28,0x8e,0xe8,0x69,0x78,0x10,0x70,0xac,0xd3,0x30,0x06,0x61,0x52,
+  0xdf,0xc6,0x9f,0x02,0xbd,0x9d,0x28,0x1d,0x81,0xa3,0x10,0x52,0x2a,0xbb,0xf8,0x21,
+  0xe1,0x28,0xd4,0xad,0x3c,0x91,0x2a,0xef,0x35,0xee,0x49,0x85,0x6f,0x8a,0xac,0x4e,
+  0xdc,0xe6,0xeb,0x53,0x36,0x40,0x55,0x5c,0xfc,0x29,0xf6,0x45,0xb7,0x75,0xaf,0xa3,
+  0x02,0xb6,0x80,0x6f,0x91,0xb8,0x2d,0x6f,0x08,0x36,0xc0,0x77,0x55,0x48,0x91,0x17,
+  0x8d,0x31,0x13,0x85,0x42,0x92,0x50,0xe4,0x2f,0x8a,0x52,0xde,0x8b,0x90,0x50,0x56,
+  0x2d,0x12,0x3d,0xa4,0x97,0xd3,0xc7,0xac,0xbb,0x30,0x4e,0xfa,0xb9,0x10,0xb8,0x28,
+  0x9f,0x25,0xfd,0x10,0x86,0x2a,0xca,0x9f,0xe7,0xf5,0x79,0xd8,0x7e,0xe3,0x3f,0xc3,
+  0x3b,0xca,0xb3,0x31,0x77,0x6a,0xc6,0x5b,0x70,0x49,0xa9,0xc7,0x02,0xff,0x76,0x9e,
+  0x3e,0x66,0xdb,0x1d,0xaf,0xc0,0xab,0x10,0x56,0x02,0x29,0x7e,0x08,0x2e,0x49,0xf5,
+  0x77,0xb8,0x07,0xf9,0x39,0xc6,0x78,0x2e,0x90,0x7e,0xff,0x66,0x52,0xae,0x12,0x45,
+  0x8a,0xdd,0xeb,0xf6,0x54,0x49,0xce,0x16,0x32,0xdd,0x78,0x07,0xd1,0xd1,0xe7,0xdc,
+  0x19,0x0d,0xdc,0x1d,0x95,0x48,0x9f,0xb2,0x8f,0x0b,0x64,0x9d,0x52,0x4b,0x8b,0x61,
+  0x9f,0xde,0x92,0x5f,0x90,0x3d,0x10,0x50,0xc4,0x54,0xde,0x08,0x77,0x10,0xaa,0x14,
+  0x67,0x8a,0xac,0x37,0xc6,0x2c,0x5d,0xf4,0xb6,0xe7,0x92,0x10,0x56,0x5c,0xf8,0x3c,
+  0xe9,0x12,0x84,0xb1,0x2f,0xce,0x4e,0xc3,0xce,0xfc,0xdc,0xe3,0x70,0x3d,0x84,0x17,
+  0xb9,0xbb,0xf8,0x11,0xc0,0x3a,0x65,0x5a,0x8a,0xbf,0xc3,0x98,0x23,0xbf,0x44,0xd9,
+  0x10,0x83,0xbb,0x85,0x97,0xe5,0x31,0xe8,0x02,0x57,0x92,0x3f,0x96,0x6b,0xe7,0x58,
+  0xa8,0x6c,0xe4,0xaa,0xa8,0x73,0x37,0xff,0x2d,0xcf,0xb3,0xe0,0xa3,0xe2,0x30,0x39,
+  0x66,0x2c,0x51,0xbf,0x63,0x19,0xd7,0x0a,0x01,0xb4,0x4f,0x52,0x88,0x73,0x2b,0x2b,
+  0x62,0x37,0xd6,0xe9,0xe3,0x92,0xe6,0x4a,0xe5,0xf6,0xda,0xca,0x7e,0xe7,0x18,0xb9,
+  0x0f,0x6d,0xa2,0x3c,0xee,0x6f,0x6e,0xe9,0x37,0xc6,0xba,0x53,0x9c,0x05,0xff,0x44,
+  0x7f,0x7c,0xd9,0x3d,0x7c,0xdd,0x2c,0xf8,0x50,0x9d,0x17,0x77,0xad,0xe5,0x8f,0x19,
+  0xf6,0x29,0x16,0xee,0x26,0x7f,0xa8,0x08,0x9f,0x76,0xaf,0xff,0xc2,0x5b,0xe9,0x2b,
+  0x2b,0xeb,0x14,0x77,0x86,0xef,0x35,0xec,0x53,0x71,0x5c,0x90,0x4e,0xaa,0x37,0x0f,
+  0x09,0xe3,0x0d,0x0b,0x61,0x82,0xd6,0xc7,0x5d,0x63,0xbc,0x64,0x8c,0x67,0x67,0x51,
+  0x86,0x6c,0xce,0x94,0xab,0xe2,0xb7,0xf8,0xe5,0xd8,0x97,0xca,0x95,0xe2,0xa8,0x6f,
+  0xae,0x31,0x2e,0xc5,0x90,0x8a,0xff,0x5d,0xf1,0xfd,0x6a,0xb4,0xb9,0xc5,0x0b,0x07,
+  0xa0,0xb2,0x49,0x8c,0x13,0x81,0xea,0xef,0x17,0x97,0xfa,0x0b,0x1e,0x83,0xb4,0xda,
+  0x29,0x10,0x45,0x44,0xfb,0x8c,0x8b,0x69,0xe2,0x6d,0xd3,0xe7,0xa1,0xb3,0xe4,0xd7,
+  0xe4,0x7d,0xa8,0x51,0x5d,0xdb,0xf8,0x0a,0x98,0xe0,0xea,0xd4,0x8e,0x94,0xb3,0xaa,
+  0x4d,0xbf,0x67,0x0a,0xde,0x83,0xbf,0x87,0x9f,0xa8,0x38,0xdd,0x23,0x70,0x05,0x66,
+  0x0d,0x60,0x21,0x6b,0xd8,0x67,0x42,0x1a,0x87,0x93,0x30,0x4f,0xed,0x18,0x69,0xbd,
+  0x40,0xeb,0xd1,0x18,0x5d,0x83,0xbc,0xdc,0xa8,0xd7,0xad,0x13,0x16,0x93,0x4d,0x42,
+  0x48,0xf5,0x27,0x23,0xbf,0x87,0x43,0xe0,0x8b,0x8b,0x29,0x52,0xa1,0xe8,0xf6,0x49,
+  0x1d,0x15,0xf2,0x26,0xf0,0xa9,0xf8,0xa3,0x21,0x7c,0x07,0x5f,0xa3,0xd8,0x45,0x64,
+  0x63,0x3c,0x45,0x01,0xa0,0x35,0x88,0x78,0x20,0x64,0x00,0xeb,0x1e,0x68,0xc2,0x75,
+  0x44,0x0c,0xfb,0xa4,0x85,0x71,0xf1,0xa4,0xbf,0x46,0x15,0xbb,0x5a,0xb3,0x30,0xa1,
+  0x74,0x29,0xae,0x34,0x2f,0x13,0x63,0x1e,0x6e,0x1c,0x13,0xae,0xc8,0xb7,0xaa,0x6e,
+  0xe0,0x47,0x61,0xc2,0x1f,0x5e,0xee,0xce,0xf2,0xc3,0xd3,0x0c,0xd6,0x39,0xc6,0xc9,
+  0x49,0x39,0x2c,0xbb,0x2f,0xf0,0x21,0xe5,0x64,0x4b,0x38,0x1b,0x18,0xc3,0x5f,0xca,
+  0xf1,0x73,0x42,0xd8,0x1c,0xac,0x2a,0x70,0x7e,0x44,0xfc,0x74,0x13,0xad,0xca,0xe2,
+  0xdc,0x66,0x4d,0x7e,0xbe,0x84,0xd8,0x5c,0x45,0x9d,0xf3,0x5a,0x28,0x7d,0x0c,0x0d,
+  0x00,0xfb,0xf2,0xa6,0xc9,0xcf,0xbd,0xf0,0x24,0x54,0x25,0x9d,0x19,0x5f,0x27,0x2b,
+  0x30,0x9e,0x8d,0x9a,0xfc,0x1c,0x41,0x6c,0xe2,0xf3,0x32,0xce,0x5f,0xf8,0xb0,0xa0,
+  0x22,0x5f,0x54,0x93,0x9f,0x87,0xe1,0x0d,0xa8,0x97,0x91,0x4b,0x3f,0x66,0x05,0xc6,
+  0xcf,0x31,0x93,0x9f,0x7b,0x71,0x88,0x71,0x18,0x33,0xb8,0x8e,0xae,0x40,0xb8,0x67,
+  0x73,0x86,0x1f,0x34,0xf9,0x59,0x2a,0xd4,0xc3,0x2e,0x05,0xa7,0x7b,0x04,0xc7,0x13,
+  0x8d,0x31,0x43,0x2e,0x98,0xfc,0x6c,0x12,0xf7,0x0b,0x15,0x8a,0x98,0x51,0xb2,0x8c,
+  0x3d,0xcc,0x50,0xc7,0x8c,0xf1,0x94,0x39,0x44,0xd5,0xb6,0x9b,0x56,0x46,0x7f,0x40,
+  0x5e,0x81,0x03,0xe9,0xca,0xac,0x73,0x2d,0xe9,0x37,0xf9,0x39,0x1d,0x1f,0x33,0x7f,
+  0xcc,0x15,0xe4,0x55,0xf8,0x30,0x5d,0x97,0x75,0x07,0xf9,0x53,0x26,0x3f,0x0f,0xc3,
+  0x44,0xf4,0xf3,0x7d,0xd5,0xa3,0x5a,0x5f,0xb4,0x7e,0x9a,0xfc,0x74,0x0c,0xc8,0xc7,
+  0x69,0xed,0x76,0xf7,0xf3,0x4b,0xfd,0xf4,0x0a,0xd4,0x65,0x27,0xf1,0x73,0x07,0xb4,
+  0x42,0x59,0xeb,0xd2,0xd5,0xa4,0x54,0xf9,0x19,0x54,0xa2,0x31,0xda,0xf9,0xa9,0x3e,
+  0x4e,0x59,0x17,0x8a,0xbf,0x5a,0x76,0x00,0x0b,0x76,0x7e,0x7a,0x06,0xb0,0x9d,0xff,
+  0x02,0x76,0xfd,0x2e,0xdc,0x03,0x02,0xaa,0xd7,0xce,0xcf,0x4e,0x62,0xf0,0xf3,0xcf,
+  0x91,0x9f,0x61,0x1a,0x98,0xc4,0x4f,0x61,0x0c,0x6a,0x05,0x37,0x9d,0x91,0x96,0xb5,
+  0xc5,0x4d,0x4d,0x7e,0x26,0xa5,0x3e,0xc6,0x25,0xb4,0x5d,0xa2,0xb3,0x00,0x6d,0xf7,
+  0x4d,0x93,0x9f,0x2b,0xc4,0x0d,0xa4,0x6a,0x91,0x33,0x55,0x3c,0x04,0x06,0x5f,0xec,
+  0xfc,0xfc,0x6b,0xfd,0x47,0x66,0x9d,0xc5,0x4f,0x01,0xb1,0x19,0x88,0x2d,0xf5,0x2c,
+  0x39,0x02,0xfb,0x10,0x50,0x4e,0xc9,0xce,0x4f,0x38,0xcd,0xba,0x00,0xb8,0x44,0x8c,
+  0xbe,0x58,0xfc,0x64,0xd8,0xac,0x52,0xdc,0xdb,0x18,0x23,0xf5,0xbe,0xe4,0xf8,0xe9,
+  0x75,0x5c,0x4c,0x5f,0x82,0xda,0x98,0x6b,0x8b,0x56,0x57,0xcf,0xea,0x5e,0x34,0xf9,
+  0x79,0xce,0x95,0x91,0x11,0x47,0xeb,0x8a,0xb3,0xb4,0x1b,0xef,0xb9,0x94,0x92,0x13,
+  0x16,0x3f,0x61,0x5f,0x14,0x6d,0xa2,0x98,0xf4,0x95,0x99,0x7d,0x31,0xee,0x59,0xb4,
+  0x5b,0x3a,0x88,0x7b,0x40,0x32,0x15,0x62,0xef,0x30,0x57,0x7b,0x87,0x1c,0x3f,0x4b,
+  0xf0,0x31,0x42,0x28,0xe6,0xd2,0x78,0x8d,0xef,0x87,0xcf,0x1b,0x36,0xec,0xd3,0xcf,
+  0xed,0x86,0x0f,0x20,0xbc,0xa2,0x3a,0x65,0xf5,0xf3,0x98,0x61,0x9f,0x7e,0x29,0x0d,
+  0xfd,0x10,0x92,0x02,0x74,0x46,0x16,0xfa,0xf5,0xf7,0xb3,0xf8,0xe9,0x27,0x4f,0xc0,
+  0xae,0x84,0x98,0x2e,0x1e,0x86,0xd7,0x70,0xe7,0x70,0xa6,0x91,0x91,0x8a,0x51,0xd7,
+  0x84,0x73,0xeb,0x63,0xcb,0x67,0x00,0x66,0xe8,0xf6,0x69,0xf1,0x33,0x0c,0xed,0xc1,
+  0xb2,0x01,0x71,0x0d,0xb9,0x4a,0x99,0xbd,0x38,0x9b,0xc9,0xb0,0xc9,0xcf,0x30,0xfc,
+  0xb6,0xf3,0x7b,0xef,0xba,0x7e,0xc0,0x5f,0x95,0xff,0x81,0xde,0x96,0x75,0xaf,0xe5,
+  0xdf,0xcd,0xf1,0xf3,0x46,0x5c,0x2b,0xf1,0x70,0xbf,0x7b,0x1f,0xff,0x9e,0x7a,0x85,
+  0x4d,0xb2,0xc5,0x4f,0x70,0x5c,0xa5,0x88,0xcd,0x21,0xd7,0x25,0x7e,0x16,0x9c,0xa4,
+  0xf5,0x59,0xf7,0x18,0x1a,0x78,0x8e,0x9f,0x0f,0x2b,0xed,0x50,0x39,0x2c,0xfe,0x30,
+  0x52,0x8a,0x9d,0xaa,0xec,0xc3,0xe7,0xbd,0x9b,0x5b,0xb7,0xd0,0xb1,0x08,0xbb,0xd0,
+  0x27,0xd6,0x90,0x3a,0x78,0x5c,0xef,0x8b,0x6a,0xd8,0xa7,0xec,0x19,0x10,0xd9,0x1e,
+  0xe0,0xc7,0x3d,0x80,0x1a,0x9b,0x41,0xbf,0x90,0xe3,0xe7,0x5e,0x6d,0x29,0xbb,0x46,
+  0xf9,0x3a,0xf2,0x07,0xbd,0x2f,0xef,0x9a,0x36,0x3f,0x02,0x7f,0xa3,0xff,0xe8,0x3c,
+  0xae,0x5b,0xad,0x90,0xe3,0x27,0x87,0xfc,0x9c,0xe0,0xea,0x7b,0xdc,0xcd,0x33,0xea,
+  0xe0,0x0d,0x4e,0x5b,0x63,0xaa,0xc1,0xcf,0x84,0xb0,0x4a,0x3c,0x04,0x55,0x3d,0xb8,
+  0xcc,0x03,0xa8,0xa5,0xaa,0xd8,0x7a,0xcf,0xe6,0xf8,0xc9,0x05,0xf0,0x56,0x73,0xd8,
+  0x8f,0x5c,0xb0,0xc9,0xa8,0xb3,0xf6,0x77,0xd8,0xcf,0xad,0xea,0xc7,0xee,0xb9,0xa0,
+  0x55,0x0a,0xf4,0x61,0x21,0x67,0x9f,0x50,0xb8,0x0a,0x26,0x84,0x5b,0x06,0xdc,0xa3,
+  0xce,0x3a,0xbc,0x67,0x78,0x10,0xfb,0xa2,0xf2,0x39,0x7e,0xbe,0x07,0x13,0xec,0x47,
+  0xfb,0xf8,0x71,0x78,0x5f,0xef,0xcb,0x70,0x5e,0x8e,0x9f,0x57,0x61,0x9c,0xd6,0xa8,
+  0x9b,0xc6,0xf8,0xab,0xf0,0x47,0x24,0xbd,0x6b,0xd8,0xd4,0x9f,0xaa,0x74,0x1e,0xba,
+  0xc5,0xf2,0x51,0x67,0x26,0x82,0xef,0x97,0xa8,0x92,0xc5,0x4e,0x12,0x34,0xde,0xaf,
+  0xdf,0x31,0x00,0x87,0x7c,0xfe,0x41,0x67,0x30,0xaf,0x83,0x71,0x89,0x8a,0x32,0x09,
+  0xd9,0xf8,0x89,0xdb,0x02,0x76,0x3d,0x8f,0xf1,0xac,0x2a,0x85,0xfb,0x51,0xd0,0xe2,
+  0xa7,0x30,0x46,0xbb,0x7a,0xb0,0x7b,0x7b,0xa5,0x1f,0x31,0x7e,0xa6,0x79,0x00,0x93,
+  0x9f,0xc2,0x78,0x8a,0x75,0xaf,0x15,0x07,0x0f,0x6e,0x53,0x91,0xf3,0x63,0x46,0xbb,
+  0x18,0xf2,0xf3,0x55,0x65,0x21,0x1b,0x62,0xb6,0x57,0x85,0x06,0x5d,0xbb,0xf8,0x12,
+  0x93,0x9f,0x01,0x61,0x83,0x50,0x3d,0x88,0xfa,0x93,0x3d,0xcf,0xd7,0x23,0xfa,0x5b,
+  0x72,0xfa,0x73,0x18,0xed,0x73,0x3b,0x17,0xe8,0x75,0xde,0x42,0x06,0x38,0xb6,0xbf,
+  0xe7,0xcb,0xc5,0x41,0x63,0xc8,0x46,0x91,0x9f,0x6d,0x88,0xcd,0x4d,0x6b,0x51,0x7f,
+  0x1e,0xa0,0x8f,0xad,0xfd,0xec,0x30,0x1a,0x87,0x7e,0x45,0x45,0x17,0x9c,0xca,0x2e,
+  0x50,0xdd,0x0b,0x50,0xef,0x7e,0x08,0xa1,0x6c,0xa1,0xcc,0x17,0xe7,0xe9,0x75,0xca,
+  0x8d,0x3b,0xe0,0x6a,0x10,0xa7,0xfb,0x83,0x69,0xe3,0x1a,0x3f,0xa7,0xcb,0xce,0xc1,
+  0x3c,0xbd,0x2f,0xc8,0x4f,0x38,0x4e,0xd7,0x5c,0x78,0x30,0xd3,0x10,0x60,0x9c,0xcf,
+  0xe2,0xfb,0xf5,0x1a,0xef,0xd7,0x5f,0xb4,0xc3,0xd3,0x2e,0x96,0xfd,0x4e,0x6c,0x2e,
+  0x46,0xfd,0xc9,0xf6,0x9c,0x38,0x72,0x3e,0x67,0x4b,0x8f,0x92,0xf6,0x64,0xd9,0x3b,
+  0xc9,0xb5,0xa1,0x59,0x22,0xe3,0xa7,0x7f,0x25,0xb2,0x5c,0xbf,0x67,0x94,0xf1,0x53,
+  0xd0,0x64,0xb5,0x4b,0xdb,0x03,0x70,0xac,0x5f,0x33,0xf9,0x99,0x84,0x63,0xd0,0x45,
+  0x5d,0x69,0xa7,0xa6,0x3f,0xa9,0x2b,0xcb,0x5f,0xce,0xb5,0x03,0x44,0x15,0x0d,0x4b,
+  0xb8,0x94,0x35,0x66,0xc9,0x8c,0x9f,0x39,0xbe,0x48,0x43,0xa8,0xe7,0xc3,0xcd,0xee,
+  0x9f,0xa3,0x2e,0x30,0x58,0x40,0x8c,0xf1,0x44,0x7e,0x02,0xf2,0x53,0xd9,0x84,0xdb,
+  0xba,0xce,0x48,0xa9,0x40,0xe6,0x2c,0x7e,0x6e,0xd0,0xb1,0x89,0x75,0x0a,0x2b,0xf8,
+  0xf2,0x72,0xf6,0xd9,0x88,0xfc,0x6c,0x44,0x54,0x79,0x88,0xa0,0xf3,0x73,0x7b,0x1e,
+  0xb1,0xf1,0x53,0x65,0x9c,0xa7,0x4e,0x19,0xba,0x75,0xbe,0x54,0x4d,0xcb,0xf1,0x93,
+  0xe1,0xa8,0x2e,0xe6,0x96,0x74,0x46,0xc6,0x50,0x63,0x9e,0x37,0xf5,0xe7,0x45,0xbd,
+  0x7b,0x83,0x3a,0xb3,0x98,0x58,0x39,0x6f,0xf2,0x13,0x65,0xa7,0x5c,0x05,0x4e,0x4d,
+  0x7f,0x72,0x55,0x9e,0xa5,0x2a,0xb2,0x5c,0x7f,0xbf,0x28,0xe3,0xa7,0x18,0x88,0x39,
+  0x8b,0xd3,0x7d,0xae,0x7d,0xf0,0x1d,0xc5,0x19,0x23,0xa7,0x8c,0x71,0xf1,0x96,0xec,
+  0xce,0xa1,0x9f,0xf1,0xb3,0x3a,0xee,0x1c,0x44,0x7e,0xea,0x75,0x69,0xcf,0xee,0xd2,
+  0x4b,0x85,0xa8,0x31,0x91,0x91,0x22,0x3e,0x2f,0xce,0xf8,0x69,0xb4,0x5b,0x09,0xd8,
+  0x2e,0xa5,0x75,0x81,0xb5,0x9b,0xc5,0xc6,0xec,0xb5,0x1c,0x23,0xa5,0xb4,0x38,0x06,
+  0x21,0x7c,0xad,0x06,0x36,0xd6,0xb5,0x38,0x4b,0xc8,0x4f,0xfd,0xdd,0xfd,0x82,0x1f,
+  0x9e,0x15,0x7c,0x4f,0x39,0xb3,0x91,0x61,0x09,0xf5,0x67,0xba,0x3f,0x4d,0x7a,0x0d,
+  0x3b,0xf3,0x3b,0xee,0x62,0xb2,0x73,0xd4,0x39,0x0f,0x98,0x26,0xaa,0x60,0x73,0xdb,
+  0x6b,0xee,0xef,0xa5,0x15,0xcf,0xa7,0xcb,0x5a,0x9c,0x71,0x72,0x06,0x9e,0xa7,0x15,
+  0xbb,0xc4,0x15,0xe6,0xfe,0xee,0x47,0xfd,0xf9,0xc7,0xd4,0x3c,0x86,0xcd,0xb3,0x70,
+  0x95,0xde,0x92,0x65,0xfa,0xd3,0xb0,0x4f,0xe4,0xa7,0xf4,0x61,0x71,0x78,0x2b,0xee,
+  0xa9,0x23,0x68,0x13,0x0b,0xe9,0x24,0xfd,0xf9,0x0a,0x4c,0xa4,0x34,0x7e,0x86,0xe1,
+  0x4a,0x1a,0xf5,0x67,0x3f,0xef,0x35,0xde,0xaf,0xb3,0x68,0x1b,0xb4,0xd2,0x4a,0x15,
+  0x97,0x2b,0xda,0x67,0x22,0x10,0x10,0xd5,0x82,0xb9,0x46,0x9d,0x04,0xdb,0x14,0x94,
+  0x9d,0x70,0x7b,0x73,0xde,0x0e,0x78,0x06,0xc7,0xd3,0x7f,0x1a,0x27,0x59,0xaf,0x8b,
+  0x7b,0xfa,0x60,0x93,0x10,0x80,0x7c,0x19,0x7d,0xd1,0x2e,0x08,0xa0,0x71,0x91,0xe2,
+  0x36,0xbd,0xae,0xbb,0xa4,0x43,0x98,0x40,0x3d,0x5f,0x89,0xeb,0x9d,0xad,0x07,0xb6,
+  0xde,0xfd,0x34,0x67,0xf3,0xb8,0x94,0xb9,0x3a,0xb8,0x2b,0x73,0xf3,0x2a,0xac,0x7b,
+  0x90,0x89,0x80,0x61,0xc3,0x3e,0x13,0xa9,0xf1,0xc6,0x93,0x10,0x1a,0x2e,0x1d,0xc5,
+  0x5f,0xb8,0x8a,0x6b,0xac,0x63,0x94,0xcf,0x9a,0xfa,0x73,0x15,0xa2,0xd1,0x97,0x10,
+  0x67,0x22,0x3f,0x9f,0xc5,0xfd,0x08,0x17,0x46,0x36,0x9e,0xd3,0x9f,0x58,0x27,0xe0,
+  0xbe,0xd9,0x45,0xf6,0x0a,0x87,0x84,0x2a,0x45,0x73,0x4e,0x0c,0xfd,0xd9,0x88,0xd8,
+  0x94,0x65,0xc5,0x2b,0x61,0x3f,0xf7,0xcf,0x0e,0x80,0x1f,0x48,0x6f,0x42,0x1f,0x33,
+  0x9a,0xbf,0x0a,0x4e,0x06,0x43,0xe0,0xdf,0xc7,0xef,0x15,0x2e,0x97,0x85,0xff,0x14,
+  0x37,0xd0,0xec,0x7a,0xbd,0xdd,0xce,0x1b,0xc7,0xf3,0xae,0x04,0xeb,0xc1,0x7d,0x8a,
+  0x7f,0x10,0xae,0x4a,0x75,0x37,0xa0,0x31,0x0e,0xdf,0x94,0xe3,0xe7,0x08,0x9c,0x9c,
+  0x8f,0x36,0x71,0x10,0xf9,0x39,0xae,0xd6,0xf7,0xe3,0x7e,0x14,0x14,0x72,0xfc,0x9c,
+  0x88,0x6c,0x2e,0xaa,0xbe,0xe8,0xec,0x22,0x08,0x52,0xa8,0xce,0x3a,0xbb,0x49,0x90,
+  0x98,0xfc,0x94,0x5a,0x67,0x6b,0x5b,0xcd,0x00,0xec,0x93,0x91,0xe5,0x19,0x3b,0x3f,
+  0x05,0x86,0xfe,0x4d,0x19,0xc6,0x33,0x89,0xed,0x01,0x05,0x41,0x83,0x13,0x12,0xea,
+  0xcf,0xe3,0xda,0x56,0x83,0x75,0x63,0x69,0x6d,0xcf,0x01,0x53,0x7f,0xea,0x43,0xbc,
+  0x6c,0x14,0x39,0x3f,0x4e,0x27,0xe9,0x4f,0xc6,0xcf,0xe3,0x24,0x84,0x72,0xd5,0x19,
+  0x40,0xb1,0xd2,0xc5,0xda,0xd9,0xf4,0x27,0x6c,0x16,0xca,0x5f,0x2e,0xc8,0x44,0xd8,
+  0xe6,0x53,0xce,0xf6,0x9c,0x8f,0x2c,0xfd,0x79,0x43,0x2b,0xc8,0x7d,0xb8,0xbf,0xbb,
+  0x84,0x2e,0xe6,0xc8,0x67,0x22,0x17,0x0c,0xdb,0x65,0xfc,0x6c,0xdf,0x57,0x36,0x52,
+  0xb0,0xd6,0x37,0x0b,0x9e,0x62,0x8e,0xfc,0x5a,0x32,0x6e,0xd4,0x31,0xfd,0xf9,0x82,
+  0x1c,0x1c,0x69,0x3a,0x34,0xcd,0x85,0x36,0x18,0x54,0xff,0x0c,0xf5,0xa7,0xc9,0xcf,
+  0xc3,0x70,0x65,0x85,0x16,0x5e,0x38,0x8c,0x73,0xab,0xbd,0x83,0xc5,0xcf,0x97,0x94,
+  0xe3,0x50,0x3b,0xd2,0x91,0x99,0x36,0x22,0x7d,0x48,0xbb,0x8e,0xa1,0x4e,0xb6,0xf1,
+  0x33,0xdd,0x0e,0xf2,0x31,0xb1,0xf9,0xcb,0x67,0xe0,0x69,0xb1,0x8c,0xed,0xe1,0x36,
+  0x7e,0x42,0xfb,0xd6,0xd9,0x4c,0x76,0x9e,0x15,0x9e,0x6f,0x29,0x1b,0xd1,0xb4,0xb0,
+  0x7e,0xcf,0xa8,0x67,0x04,0xfd,0x15,0x59,0x4d,0x06,0x35,0xbf,0x83,0x05,0x23,0x6c,
+  0xfc,0xec,0x44,0x7e,0xd6,0xa2,0xec,0x44,0x69,0x72,0x19,0x42,0xcc,0x06,0x27,0xf1,
+  0x53,0x47,0x95,0x06,0x52,0x4d,0x7f,0x1a,0x63,0x86,0xfc,0x14,0x98,0x8f,0xee,0x4e,
+  0x95,0x6b,0x7a,0x9e,0xb1,0xa0,0xd7,0xe4,0xe7,0x37,0x85,0x0d,0xc4,0x87,0x7c,0x89,
+  0xd8,0xf4,0xa7,0x7e,0x21,0x3f,0xe9,0x06,0xf0,0x45,0x36,0x7d,0xa2,0xfe,0xac,0x40,
+  0xfd,0x29,0x33,0x7e,0x22,0xbc,0x94,0xa9,0xfa,0x93,0xa8,0x24,0x04,0x39,0x96,0x6b,
+  0xfa,0xd3,0xe4,0xe7,0x5b,0xc2,0x25,0xe5,0x39,0x74,0x95,0x1b,0x34,0x46,0x32,0xff,
+  0xdd,0xc6,0xcf,0xdd,0x97,0x3e,0x3b,0x5f,0xd9,0x9c,0x9a,0x81,0x9c,0x57,0xc2,0x91,
+  0xbd,0x58,0xc7,0x99,0xfa,0x13,0xba,0x57,0xf8,0x90,0x9f,0x05,0x32,0x64,0xe4,0x85,
+  0x52,0x94,0x4e,0xe2,0xe7,0x41,0xb1,0x22,0xe6,0x94,0xb6,0x0a,0x12,0x63,0x39,0xae,
+  0xe9,0x53,0x9c,0x3e,0xd6,0x1a,0x3f,0x05,0x1f,0xeb,0xde,0x0a,0xfc,0xa5,0xb9,0xe8,
+  0xc8,0x5b,0xfc,0x64,0xfa,0x13,0x6a,0xd9,0x70,0xe8,0xfb,0x8a,0xcb,0xc6,0x4f,0xd4,
+  0x9f,0x3a,0xc2,0xcb,0xb1,0xa0,0x2e,0x9c,0xc2,0x4f,0x18,0x86,0x85,0x5a,0x7c,0x02,
+  0xc6,0x94,0x20,0x37,0x49,0x7f,0xce,0x95,0x37,0x82,0x6f,0x4f,0x12,0xe7,0x88,0xf1,
+  0x93,0xe9,0x4f,0x8b,0x9f,0x8d,0xe8,0xa2,0xf9,0x75,0xfd,0xb9,0x1f,0x9d,0x60,0xa6,
+  0x89,0x4c,0xfd,0x39,0x13,0xda,0xe5,0xb2,0x38,0xee,0xb7,0x67,0xd0,0x3f,0xd2,0xec,
+  0xc5,0xf2,0xdf,0x67,0xc2,0xef,0x33,0x9f,0xcf,0x8a,0x3f,0xe2,0xcf,0x4a,0x7f,0x4c,
+  0x6a,0x20,0xb5,0xf8,0xd9,0x06,0x57,0xe4,0xb0,0xb8,0x6c,0x5f,0x03,0x02,0xaa,0x79,
+  0x92,0xfe,0x54,0x1c,0x1f,0x29,0x27,0x93,0xe1,0x8b,0xee,0x4b,0xfc,0x55,0x65,0x22,
+  0x15,0x1e,0x42,0xff,0xfd,0xb4,0xc9,0xcf,0x9f,0x42,0x7b,0x51,0x65,0xdc,0xd9,0xdc,
+  0xb0,0x43,0x39,0x90,0xae,0x1e,0x12,0x51,0x7f,0x1a,0x75,0xc5,0xd0,0xd1,0xd2,0xae,
+  0xc9,0xce,0xe2,0x33,0xe2,0x01,0xb9,0xba,0x1f,0xeb,0x5e,0x34,0xf9,0xc9,0xf6,0xf7,
+  0x00,0x38,0x83,0xbe,0x0e,0x7d,0x7f,0x0f,0x92,0xdc,0xda,0xec,0xc4,0xb1,0x3e,0xc9,
+  0xf6,0xcd,0x51,0x64,0xf9,0x84,0xac,0xf9,0x9b,0xe7,0x0d,0x9b,0x4f,0x81,0x66,0x7a,
+  0x0c,0xef,0x9a,0xd6,0x50,0xab,0x33,0x16,0x3f,0xa5,0x8b,0x28,0xa1,0xea,0x47,0xb1,
+  0xdd,0xb8,0xc4,0xb4,0x14,0x0a,0xd8,0xec,0x0a,0xbd,0x6e,0x0b,0xee,0xef,0x28,0xcb,
+  0xb6,0x38,0x35,0xbe,0xe8,0xfe,0x6d,0x36,0x66,0xfa,0xef,0xcc,0xe5,0x25,0xa8,0xdd,
+  0x56,0x69,0x75,0xc9,0x8c,0xc5,0x4f,0xf4,0x8f,0xf6,0x93,0x00,0x71,0xce,0xcb,0xc3,
+  0xb1,0x96,0x03,0xfd,0x62,0xd0,0x9c,0x07,0x5a,0xb8,0x2a,0xfa,0x3e,0x84,0xa3,0xac,
+  0x9f,0x12,0xf6,0xb3,0x37,0x90,0x99,0x91,0x9d,0xa3,0xdf,0x73,0xd7,0x8d,0x23,0xca,
+  0xf3,0x50,0x4f,0xdc,0x17,0xca,0x51,0x2f,0x49,0x53,0xf4,0xe7,0xbb,0xae,0xe3,0xf7,
+  0x3f,0x5d,0xe6,0x4a,0xf2,0x3e,0xd4,0xf3,0xe8,0xa7,0x2e,0x37,0xfd,0x77,0x55,0x7a,
+  0x1b,0x1e,0x6a,0x08,0xa5,0x45,0x28,0xf0,0xc1,0x93,0x89,0xaa,0xac,0x73,0x3b,0x19,
+  0xcd,0xcb,0xf1,0x73,0x48,0x68,0x9d,0xef,0x03,0xc4,0x3b,0x00,0xd3,0xec,0x05,0x12,
+  0xb9,0x90,0xe3,0x67,0xd1,0x2f,0x51,0xa3,0xa0,0x5f,0xd5,0xd2,0x52,0x2e,0x3e,0xc9,
+  0x84,0xf6,0x56,0x32,0x6a,0x8c,0x19,0x94,0xf4,0xb2,0xf0,0x65,0x28,0xd0,0xc6,0x13,
+  0x0d,0xa4,0x0f,0xa7,0x6c,0xfe,0xfb,0x53,0x79,0x1f,0x7b,0x6f,0x3d,0xea,0x56,0xf9,
+  0x51,0x32,0xc1,0xfc,0xe2,0xd3,0x36,0xff,0x7d,0x37,0xfc,0x1e,0x9e,0x15,0xa7,0xb7,
+  0xf1,0xe7,0xe4,0x3f,0xcc,0xd7,0xe6,0x21,0x65,0xcc,0xd1,0x69,0xa6,0x89,0x16,0xc9,
+  0x59,0x51,0x24,0xb2,0x7c,0x85,0x6a,0xe3,0x19,0x34,0xf5,0x67,0x14,0x76,0x12,0xb9,
+  0xb9,0xc0,0x89,0x6b,0xfa,0x31,0x35,0x70,0x2a,0x2a,0x91,0x2e,0xc3,0x17,0x45,0x7e,
+  0x0e,0xb6,0x67,0xca,0xe4,0xe4,0x1d,0x64,0x26,0xda,0x4b,0xe5,0x88,0xf7,0x34,0xa9,
+  0x13,0xf4,0x3a,0xe4,0x27,0x7d,0x87,0x06,0xcf,0x4f,0x2f,0xe0,0x7b,0x07,0x7f,0x9f,
+  0xae,0x1b,0x09,0x78,0xf9,0xad,0x44,0xaf,0x53,0x6e,0xec,0x50,0xae,0xa4,0xff,0x8a,
+  0xba,0x53,0xce,0x41,0x98,0x90,0xea,0xfb,0x70,0x1d,0x0d,0x1a,0x3a,0xb9,0xd3,0xd1,
+  0x0f,0x47,0xe5,0x50,0xc4,0x4d,0xcb,0x2b,0xf2,0x5f,0x67,0xfa,0x33,0x65,0xe7,0x27,
+  0xd9,0x2c,0x96,0x29,0x4b,0xb3,0x3e,0x0f,0xd7,0x4e,0x70,0xa3,0x8f,0x91,0x0b,0x86,
+  0x5d,0x53,0xf8,0x5b,0xf8,0x6f,0x0c,0xe1,0x51,0x12,0x92,0x7e,0xc6,0xfc,0xf7,0xe5,
+  0x36,0x7e,0x9e,0x60,0xa1,0x5b,0xd5,0xe9,0x9d,0x5b,0x40,0x36,0xe1,0x58,0xef,0xb9,
+  0x9e,0xbc,0x06,0x39,0x7e,0xfe,0x1c,0x5e,0x13,0xba,0xda,0xdc,0x2b,0xf9,0x05,0xe8,
+  0x1b,0x86,0x51,0x88,0xa2,0xff,0x6e,0xc4,0x0b,0x90,0x9f,0xc3,0x80,0xfa,0x33,0xc1,
+  0x9f,0x53,0xc6,0xe0,0x27,0x30,0x9d,0xf9,0xef,0xfa,0xf3,0x90,0x9f,0x70,0x94,0x2e,
+  0x64,0x5a,0x6a,0x05,0xbc,0x23,0xd7,0x2a,0xcb,0x6c,0xfc,0x84,0x15,0x90,0x50,0x7d,
+  0xb7,0x3b,0x53,0xfc,0x62,0xd8,0x90,0xf5,0x4d,0xf1,0xdf,0xc9,0x86,0xf8,0xdc,0x45,
+  0x9f,0xd9,0x8e,0xec,0xd9,0x03,0x73,0x58,0xdd,0x09,0xcb,0x7f,0xe7,0x12,0x11,0xe4,
+  0xe7,0x0e,0xb2,0x4a,0xda,0xc0,0x3a,0x2c,0x91,0x63,0x0e,0x7d,0xda,0xbb,0x5d,0x32,
+  0xba,0xb5,0x0b,0x19,0x36,0xe3,0xd2,0x30,0xea,0x33,0xbb,0xff,0x5e,0x38,0x0e,0x1f,
+  0x2b,0x61,0x65,0xd9,0xe0,0x8c,0x97,0x99,0x10,0x65,0x62,0xf3,0x6d,0x21,0xc7,0xcf,
+  0x97,0xe1,0xe3,0x2c,0x72,0xfe,0x5e,0xde,0x23,0xfe,0x23,0xfa,0xef,0x1d,0xe8,0xdb,
+  0x9b,0xfc,0xc4,0xf7,0x4b,0xef,0xe2,0x9c,0x2c,0xa6,0xda,0x49,0xaa,0x98,0x31,0x9e,
+  0x30,0xec,0x33,0xba,0xb8,0x0f,0xb6,0xc4,0xe3,0x0a,0x9a,0x9e,0x20,0x3e,0x82,0xfc,
+  0xf4,0xdb,0xf8,0x59,0xb4,0x9b,0xee,0x11,0x7c,0x8b,0xb0,0xee,0x3d,0x7c,0x87,0xef,
+  0x2a,0xe2,0x76,0x93,0x05,0xe9,0xa2,0x7f,0x82,0x57,0xa1,0x2b,0xee,0x7e,0x94,0x73,
+  0x60,0xa1,0x4e,0xe3,0xa7,0xd1,0x97,0x95,0xdc,0x2f,0xe1,0x1d,0x40,0xbf,0x38,0xc5,
+  0xff,0x42,0x34,0x34,0xfb,0x29,0x9b,0xff,0x9e,0x95,0xbb,0xc0,0xdd,0x76,0xb3,0x0c,
+  0xc3,0x72,0x2d,0xd3,0xfa,0xbd,0x96,0xff,0x0e,0x0f,0x53,0x1f,0xfd,0xcc,0xf9,0x19,
+  0xb8,0x3b,0x2e,0x2e,0xef,0xdc,0x34,0xc9,0x7f,0x57,0x1e,0xeb,0xa9,0x50,0x9d,0xcf,
+  0x90,0x24,0xde,0xa2,0x82,0x6e,0x9a,0xec,0xbf,0xb7,0xe6,0x7f,0x43,0x75,0x8e,0x16,
+  0x5c,0x84,0x9f,0xd2,0xd9,0x09,0xe4,0x67,0x56,0xd0,0xdb,0xe9,0xf1,0xcf,0xa7,0x87,
+  0x96,0xae,0x75,0xfe,0x1c,0xde,0x46,0xfd,0x39,0x6d,0x2d,0xff,0xa6,0xe5,0xbf,0x0b,
+  0x87,0x60,0x2e,0xe3,0x52,0x1c,0x46,0x0d,0xfd,0x69,0xd8,0xa7,0x82,0xfe,0xe6,0xc7,
+  0xb4,0x26,0xeb,0xfe,0x01,0x3f,0x57,0x39,0x43,0xeb,0x57,0x04,0xc6,0xf8,0x41,0x93,
+  0x9f,0x8f,0x76,0xfe,0x86,0xca,0xc3,0xce,0x1f,0x92,0x99,0x74,0xd7,0xce,0xca,0x0a,
+  0xe4,0xcb,0xbb,0x86,0x2e,0x90,0x94,0x1d,0xf4,0x69,0x98,0xdd,0xef,0xbc,0x40,0x96,
+  0xd3,0x9f,0x49,0x95,0xa2,0xbf,0x19,0x17,0x94,0x5e,0xb7,0x52,0x3a,0x99,0xda,0xd7,
+  0x32,0x67,0x97,0x13,0x0a,0x14,0x48,0xa3,0xfe,0x44,0x47,0xfe,0x35,0xa3,0xee,0x89,
+  0x92,0x76,0x38,0x94,0xfc,0x28,0xe3,0x0e,0xb6,0xc6,0x0b,0x5e,0x83,0x3a,0x08,0x30,
+  0x46,0xea,0x7d,0x61,0xfc,0xbc,0x1c,0x59,0xe8,0x71,0x67,0x5a,0xd3,0xca,0x65,0xb6,
+  0xa7,0x5a,0xfe,0x7b,0x22,0xf5,0x91,0xf4,0xcf,0x52,0x0d,0xc3,0x66,0x08,0xde,0x97,
+  0x6b,0x04,0x2c,0x98,0x6c,0x45,0x7e,0x26,0x49,0x6d,0x45,0xc1,0xe1,0x02,0x50,0x06,
+  0x1d,0xbe,0x20,0xae,0xf7,0x61,0xcb,0x7f,0xa7,0x07,0x15,0x5f,0x4b,0xf4,0x99,0xe9,
+  0x32,0x74,0x82,0xaf,0x25,0x69,0xf9,0xef,0x05,0x82,0x8b,0x52,0xf9,0x97,0xde,0x82,
+  0xae,0x02,0x59,0x4e,0x65,0xe4,0x94,0x38,0x9f,0xf4,0x1a,0xf6,0x49,0x1f,0x5a,0x95,
+  0xbd,0x1c,0xec,0xea,0x77,0x75,0xf1,0x38,0x7f,0x62,0x68,0xbb,0xeb,0x29,0x3e,0xdb,
+  0x9a,0xf3,0xdf,0x47,0xe8,0xe5,0xe0,0x5c,0xaf,0x7b,0xdf,0x23,0x83,0xf2,0x58,0xd9,
+  0xe1,0x36,0xc6,0xcf,0x0a,0xdd,0x26,0x7a,0x8b,0x26,0xa4,0x37,0x3a,0x6b,0xc6,0x02,
+  0x97,0x51,0xcf,0x9f,0x84,0x9a,0x81,0x55,0xef,0x58,0xfe,0x3b,0xbc,0x4f,0x5a,0xd3,
+  0xe9,0x61,0x71,0x61,0x6f,0x55,0xf0,0xef,0xfa,0xca,0x87,0xc5,0x27,0xd0,0x0f,0x37,
+  0xf8,0x09,0x0f,0xb5,0x3c,0x36,0x37,0xbd,0x5c,0xac,0x61,0xb1,0x84,0xa8,0xfc,0x52,
+  0x81,0xaf,0xc0,0xd4,0x9f,0x9e,0xbd,0x79,0x9b,0x38,0x59,0x11,0x33,0x92,0x0b,0x1e,
+  0x83,0x5d,0x6a,0x81,0xe5,0xbf,0x73,0xc2,0x5e,0xe1,0x34,0x84,0xd2,0xae,0xc3,0x5c,
+  0x00,0x1d,0xc8,0x2e,0xb5,0x2a,0xdd,0x90,0xd3,0x9f,0x3d,0xd2,0xe1,0xbc,0x8b,0x72,
+  0xf5,0xee,0xea,0x71,0xe7,0x38,0x79,0x03,0x9e,0x57,0x0b,0xb3,0x24,0xc7,0xcf,0x66,
+  0xa9,0x03,0x5e,0x25,0x0b,0x23,0x81,0x67,0xf8,0x40,0x23,0xb6,0xeb,0xb5,0xf9,0xef,
+  0xc3,0x42,0x80,0xdb,0xa0,0xa0,0x8c,0x38,0x5c,0xf0,0xab,0xc8,0xe6,0x58,0xfd,0xef,
+  0x84,0x27,0xcc,0xfc,0x51,0xbf,0x20,0x42,0x6b,0x81,0x3c,0x88,0x4b,0x6b,0xba,0xc0,
+  0x02,0x4d,0xb7,0xa7,0x8b,0x73,0xf9,0xa3,0x53,0x52,0x01,0x69,0x4f,0x7d,0x36,0xeb,
+  0xfd,0x16,0x39,0xab,0xb4,0xd3,0x00,0xae,0x46,0x74,0x08,0xf4,0x76,0x51,0xc0,0x76,
+  0x5c,0xb0,0xdf,0x25,0xb5,0xb2,0x18,0x4b,0xb0,0x9f,0xf9,0xef,0xb9,0xf8,0xa7,0xa7,
+  0x5b,0x78,0x1f,0xaa,0x99,0x4e,0x3e,0x8c,0x9b,0xe4,0xe7,0xd4,0x65,0xe8,0x01,0x1a,
+  0x1c,0x14,0x3d,0x7b,0x51,0x0f,0x86,0x12,0x55,0x2d,0xac,0x9d,0x1c,0xea,0x0f,0xa4,
+  0xcd,0xf8,0x67,0x3f,0xec,0x80,0x57,0xe0,0x69,0x5a,0x28,0xdf,0x71,0x18,0x36,0x07,
+  0x76,0x1e,0xf3,0xa3,0xff,0x6e,0xc6,0x97,0x1e,0x85,0xc7,0x13,0x72,0x76,0xe3,0xf2,
+  0x99,0xb3,0xa4,0xf6,0xcc,0xec,0x11,0xe7,0x4a,0x33,0xfe,0x19,0xf5,0x74,0x08,0x8f,
+  0x0c,0xee,0x1e,0xcc,0x0f,0x92,0x0e,0xd2,0x8a,0x3e,0x1e,0xea,0x97,0x9c,0x1f,0xde,
+  0xef,0xd9,0x13,0xc3,0xe7,0x51,0x1c,0x46,0x3f,0x1c,0x73,0xd4,0x26,0xaa,0xb3,0xb6,
+  0xf8,0x67,0x1a,0x46,0xc5,0xc3,0xbc,0xae,0xf9,0x22,0x0b,0x39,0x81,0xda,0xf2,0x47,
+  0xbb,0xe1,0xa8,0x14,0x52,0x6e,0x4c,0x91,0x15,0xe4,0x28,0xcd,0x30,0x4e,0xf8,0xcc,
+  0xf8,0xe7,0x4d,0x64,0x0f,0xf8,0x50,0x96,0x15,0x20,0x2c,0x59,0x60,0x79,0x2b,0x91,
+  0x73,0xfc,0x14,0x5c,0xca,0x43,0x62,0xb9,0x72,0x73,0x73,0x71,0x1b,0x8a,0x84,0xb9,
+  0x8a,0x37,0x05,0x39,0xff,0x1d,0x04,0x07,0xfc,0x42,0xd9,0x19,0x9b,0xfb,0x7d,0xb2,
+  0x8e,0x25,0x92,0x62,0x0b,0x3c,0x91,0x9c,0xff,0x7e,0x1a,0x92,0x68,0x4f,0x21,0xd8,
+  0xac,0xf2,0x69,0x1c,0xa0,0x05,0xd0,0x48,0x9d,0x55,0x56,0xfc,0x53,0x3a,0xa8,0x84,
+  0x63,0x85,0xdb,0x1a,0x56,0xc0,0xa5,0x48,0x98,0xf9,0xef,0x66,0xfe,0x08,0xf5,0xe0,
+  0x51,0x12,0x8a,0xba,0x52,0x9b,0x56,0xc0,0x51,0x31,0xa4,0xb8,0xb6,0x98,0xf1,0x4f,
+  0xaf,0xb8,0x53,0x3e,0xbd,0xa6,0x16,0xc4,0x36,0x92,0xc6,0xcd,0xc6,0xe7,0x89,0xaa,
+  0x66,0xfc,0x53,0x69,0xdc,0x76,0x6c,0x9d,0x6b,0xe7,0x57,0xf3,0xef,0x6e,0xb9,0x57,
+  0x5e,0x27,0x96,0x45,0xc4,0xbb,0x23,0xa7,0x0c,0xfb,0xdc,0x2e,0x6c,0x83,0x5f,0x35,
+  0xce,0xbe,0x57,0x1c,0x94,0x9f,0x82,0x87,0x48,0xd9,0x22,0x71,0xd0,0x8a,0x7f,0xa2,
+  0x8f,0xbe,0x01,0xba,0x16,0x15,0x6e,0xe5,0xf0,0x79,0x5c,0x48,0x09,0xa4,0x1a,0x72,
+  0xfc,0xfc,0xb6,0xb4,0xbb,0x68,0x0b,0x62,0xb3,0x3a,0xe5,0x1c,0x92,0xdf,0xe1,0x9e,
+  0x43,0x7e,0x22,0x27,0xf4,0x76,0xc8,0x4f,0xbe,0x1f,0x6a,0x85,0xa6,0xb6,0x06,0x99,
+  0xa8,0xb8,0x51,0x34,0xa9,0xce,0x82,0x9c,0xd6,0x17,0xe6,0xc2,0x1d,0xd4,0x97,0xf1,
+  0x77,0xf2,0x7f,0x2e,0x6d,0xa4,0xbe,0x74,0xb4,0x93,0x14,0xe4,0xf6,0x9c,0x36,0x17,
+  0x3c,0x42,0x2b,0x2e,0x88,0xdd,0xd3,0x7f,0xa5,0xb4,0x26,0xfc,0xe7,0x56,0x2e,0xc0,
+  0x3a,0x7d,0x5c,0x38,0x28,0x2d,0x5b,0x2f,0xca,0x54,0x6c,0x6e,0x19,0xe4,0xd6,0x8b,
+  0x65,0xbd,0xb0,0xb6,0xc5,0x9f,0x6b,0x87,0xee,0xc4,0x0b,0xcc,0x6d,0xf7,0x3b,0x9f,
+  0x43,0xdd,0x73,0x6b,0xb6,0x69,0xd8,0x39,0xd7,0xb0,0x4f,0xbf,0x77,0x2f,0xf9,0x91,
+  0xa6,0xeb,0xa6,0xc5,0x05,0x2d,0xfe,0x99,0x36,0xf5,0x67,0xc4,0xf5,0x0c,0xf7,0x5e,
+  0xe2,0xc0,0x39,0xd7,0x69,0x3e,0x4c,0x5e,0xca,0xd4,0xac,0xc2,0x42,0x2e,0x7e,0xd6,
+  0x09,0xdb,0xa0,0x43,0xbe,0x45,0xf5,0x8f,0x92,0x3a,0xe8,0x90,0xca,0x1b,0x71,0x5c,
+  0x72,0xf9,0xa3,0x0c,0x3d,0x0c,0x8f,0x93,0x9d,0x7d,0xfe,0x45,0xe8,0xdb,0xb7,0x97,
+  0x95,0xdd,0x2e,0x46,0xf1,0x69,0xfa,0xfb,0x29,0xc2,0x5e,0xa9,0x55,0x98,0xa3,0x8a,
+  0x9f,0xc7,0xe5,0xd3,0x4a,0x70,0xe1,0x03,0x11,0x8d,0x79,0xd8,0x2e,0x74,0xba,0xfe,
+  0x40,0xba,0x14,0xcd,0x6f,0xc4,0x75,0x4b,0x03,0x19,0x67,0xee,0x9e,0x6d,0xb8,0x79,
+  0x5d,0x80,0x30,0xe7,0xce,0x94,0x67,0x59,0xec,0xde,0x1e,0xff,0x4c,0xd0,0xc3,0x05,
+  0x88,0x23,0xc5,0x15,0xcf,0x3f,0x0c,0xbf,0x85,0x9a,0xb4,0x6b,0xd8,0x09,0x86,0xff,
+  0xde,0xe3,0xa9,0x44,0x19,0x31,0xb7,0x62,0x6e,0x86,0xc8,0xe4,0x75,0xce,0x77,0xd1,
+  0xff,0x59,0xd3,0x3e,0x29,0xc8,0x72,0xbe,0xa0,0xe5,0x8f,0xf6,0xb2,0x3d,0x3c,0x85,
+  0x6c,0x95,0x73,0x63,0xa6,0xd5,0xfb,0xd5,0x82,0x60,0x41,0x07,0xc2,0x5b,0x0b,0x88,
+  0xe5,0xec,0xb3,0x05,0x9a,0xd8,0x32,0x57,0x03,0x94,0x47,0x47,0x17,0x17,0x54,0x47,
+  0x9a,0x07,0xc3,0x3e,0x13,0x25,0xe3,0xc5,0x9a,0x9c,0x1b,0x2d,0x7f,0x10,0xde,0x67,
+  0x85,0xac,0x4d,0x7f,0x9e,0x85,0x37,0xd4,0x7d,0x2b,0x5c,0x1f,0xa2,0xfe,0x7c,0x83,
+  0xab,0xc9,0xba,0xa2,0xe5,0xf6,0xf8,0xe7,0x26,0xa6,0x23,0xf7,0x11,0x99,0x6e,0x6a,
+  0xf3,0xb1,0x7d,0xda,0x1e,0xff,0xdc,0x2a,0xfb,0x92,0x2b,0xbb,0x50,0xf3,0xa1,0xdf,
+  0x81,0x9d,0x9b,0x14,0xff,0xdc,0x84,0xfb,0x6d,0x32,0x53,0x20,0xd3,0x3d,0xc5,0x3e,
+  0x19,0xe1,0x65,0xc6,0x3f,0x3d,0xbb,0x71,0x2d,0x85,0x4e,0xa1,0x7c,0x94,0x59,0x1c,
+  0x33,0x1b,0x00,0x5e,0x30,0x9e,0x77,0x0e,0x9e,0x62,0x9a,0x3d,0xb9,0x79,0x94,0xbf,
+  0x00,0x6f,0xd0,0xfa,0x9e,0x65,0xbd,0x66,0xfc,0x93,0xe5,0x8f,0xd0,0x3f,0xa2,0xae,
+  0x0c,0x37,0x0c,0xbf,0x17,0xbb,0x7a,0xf1,0x45,0xb7,0x19,0xf6,0xa9,0x0a,0x2e,0xd8,
+  0x44,0xe4,0x6d,0xe2,0x1a,0x72,0x3c,0x9e,0xaf,0xf8,0x62,0xe2,0x3a,0x5b,0xfe,0xbd,
+  0x29,0xb2,0x87,0xf8,0x15,0x71,0x7e,0x4b,0x2f,0x94,0xc7,0x7c,0x83,0x49,0x20,0x19,
+  0xbd,0x27,0xd0,0x8d,0xfb,0xfb,0xe6,0x54,0xf9,0x88,0xf8,0x43,0xf2,0x11,0x6d,0x4d,
+  0x97,0x0d,0x47,0x5f,0xb3,0xc5,0x3f,0xa7,0xa3,0xb6,0x59,0x30,0xec,0x5a,0xd0,0x70,
+  0x82,0x9e,0xcb,0x86,0xf6,0xb8,0x44,0x7e,0x6b,0xce,0x7f,0x2f,0xdc,0x3b,0x78,0xc5,
+  0x51,0xdf,0x53,0x3d,0xca,0x0f,0x28,0x57,0x83,0xcf,0x53,0x1c,0x4f,0xcb,0x7f,0x1f,
+  0xc2,0xa5,0xac,0xe5,0xb9,0x1a,0x91,0x9f,0x17,0x7a,0x06,0xa8,0x4d,0x7f,0x6e,0x83,
+  0x76,0x28,0x53,0xc5,0xe6,0x3c,0x8f,0x70,0x4a,0xfa,0xba,0x2a,0x2a,0x93,0xfc,0xf7,
+  0x6d,0xb4,0x3c,0xcb,0x2d,0x58,0x12,0x96,0x7f,0x91,0x2c,0x1f,0xbd,0x23,0x3a,0x29,
+  0xfe,0xf9,0x08,0xa4,0x87,0xf6,0x64,0x48,0x25,0xec,0x4b,0xec,0x1a,0x2b,0xf0,0xd9,
+  0xfc,0xf7,0x8d,0xf0,0x68,0xac,0x3c,0x9d,0x9f,0x75,0xfe,0x40,0x7a,0x97,0x7e,0x2f,
+  0x35,0x3d,0x6e,0xf7,0xdf,0x15,0x26,0xf5,0xa6,0xa3,0xde,0x10,0xbc,0xe2,0x73,0x50,
+  0x49,0x39,0xd3,0x7f,0x8f,0xa1,0xec,0x84,0x2e,0x25,0x2f,0xc5,0xcf,0x49,0x1f,0x57,
+  0xbb,0x94,0x8e,0xad,0x7c,0x8b,0x5d,0x7f,0x2a,0x3e,0xc5,0x9f,0xe2,0xff,0x0b,0x1a,
+  0xb2,0x96,0xdf,0x94,0x8d,0x71,0xf1,0xa2,0x8f,0xbe,0x47,0x94,0x99,0xcb,0x5b,0x09,
+  0x7b,0x14,0xad,0x6e,0xbd,0xa5,0x3f,0x85,0x0d,0x88,0x4d,0x71,0x1b,0x59,0x0c,0x3b,
+  0x41,0x5e,0x8d,0x3e,0x33,0xe1,0xf4,0x96,0xdd,0xa2,0x8c,0x6a,0x58,0xcb,0xbf,0xcb,
+  0x64,0x18,0x0b,0x1d,0xe9,0xa2,0x5f,0xe7,0xfc,0xf7,0x42,0xd4,0x98,0x70,0x9b,0x72,
+  0xe7,0x36,0xfe,0x22,0xbc,0xde,0x58,0xaf,0x54,0x5b,0xf1,0x4f,0xaf,0xe3,0x22,0x8f,
+  0x6e,0x4a,0xa3,0xfb,0xe7,0x0d,0x8d,0xf0,0x92,0x7c,0xeb,0xa2,0xa6,0x41,0x9b,0xff,
+  0x9e,0x85,0xa4,0xb8,0x90,0xc5,0x3f,0x83,0xa8,0xde,0x7c,0x2d,0xa2,0xe5,0xbf,0x2b,
+  0x8e,0x3e,0x71,0x1d,0x87,0xbe,0xe8,0x97,0x5b,0x3c,0x3b,0x13,0x5c,0xfa,0xf6,0x02,
+  0x9b,0xfe,0xfc,0xe2,0x6e,0x6e,0x03,0xdc,0x1c,0x75,0x0e,0x2e,0xf1,0xc8,0x1b,0xa6,
+  0x3d,0x70,0x7f,0x81,0xcd,0x7f,0xdf,0xb6,0x1e,0x36,0x7c,0xa3,0x2a,0xee,0x4e,0xe5,
+  0xdf,0x24,0x6d,0x50,0x42,0xb1,0xaf,0x6d,0xb5,0xc5,0x3f,0x1f,0x97,0x5e,0x85,0x85,
+  0x71,0xfd,0x9c,0x40,0xaa,0x56,0xa9,0xdc,0xda,0x3a,0xc9,0x7f,0x5f,0x1c,0x42,0xb7,
+  0xfd,0x9e,0x0f,0xe0,0xb4,0x58,0xeb,0x45,0xfb,0xdc,0x98,0xab,0x13,0x16,0x0a,0x1b,
+  0x13,0xa8,0x3f,0xd3,0xc5,0x63,0xf0,0x4a,0x23,0x4f,0xa3,0x6f,0x92,0xdc,0x11,0x1c,
+  0x16,0xff,0x2c,0xa7,0x15,0x2c,0xe4,0xd4,0x5f,0x4c,0xa5,0x39,0x83,0x20,0x90,0x16,
+  0x83,0x9f,0x65,0xdc,0xfc,0x8a,0xcd,0x1b,0xef,0xa7,0x4e,0x85,0x8c,0x71,0x8f,0xc2,
+  0x6c,0x35,0x7a,0x9a,0x88,0x66,0xfc,0x33,0x2c,0xbd,0x4d,0xff,0x6b,0xd6,0xb9,0x96,
+  0x7f,0x05,0x5e,0xa2,0x9f,0x8b,0xbb,0x96,0xf3,0x1b,0x73,0xfe,0xfb,0x9d,0xbb,0xe1,
+  0x4d,0x78,0x96,0xe2,0xbe,0x39,0xc4,0xe2,0x9f,0x8a,0x5b,0xb2,0xf9,0xef,0x57,0xe1,
+  0x1f,0xe9,0xfc,0x2c,0xba,0xed,0x0b,0x95,0xfe,0x74,0xcd,0x90,0xeb,0xa0,0xcd,0x7f,
+  0x7f,0x98,0x6e,0xd8,0x25,0xa7,0xc5,0x02,0xdf,0x0d,0x0a,0xed,0xf2,0x65,0xa3,0x0b,
+  0x4c,0xff,0x9d,0xc2,0x61,0x65,0x5b,0xb0,0x5c,0x8d,0xae,0xc9,0xab,0x6d,0xa3,0xc1,
+  0x77,0x9a,0xc4,0x25,0xa6,0xfe,0x44,0xff,0x5d,0xa4,0x51,0x1c,0x7e,0x20,0x0e,0xa0,
+  0x89,0xb9,0x8c,0x9f,0xa7,0x4c,0xff,0xbd,0x03,0x5e,0x5f,0xb7,0x6b,0x6d,0x20,0xb3,
+  0xf4,0xb3,0xa4,0x27,0xbe,0x70,0x91,0x6b,0x07,0x8e,0x67,0xce,0xe6,0xd1,0x7f,0x2f,
+  0x62,0x3e,0xc9,0x8c,0x61,0x72,0x59,0x9e,0x13,0xdf,0x9c,0x34,0x35,0x26,0x17,0x1b,
+  0x87,0xf3,0xb0,0xbf,0xb1,0x63,0x94,0x9f,0x2f,0x0f,0xa4,0xea,0xa1,0x63,0x70,0x46,
+  0x2e,0xfe,0xd9,0x83,0xfa,0xb3,0x05,0x98,0xef,0x7b,0x83,0x00,0xaf,0x29,0xbe,0xfb,
+  0xc5,0x0e,0x2b,0xfe,0x89,0xf2,0x57,0xdb,0xfb,0x83,0xc4,0x0f,0xc9,0xc6,0x5f,0x3f,
+  0x20,0x76,0x14,0x9b,0xfe,0x3b,0x5a,0xdf,0x06,0xbf,0x4c,0xfc,0x04,0xeb,0xb6,0x06,
+  0xd3,0x31,0x7f,0x9e,0xe9,0xbf,0x2b,0xe2,0xaa,0xce,0xe1,0xb2,0x35,0x5f,0x74,0xd5,
+  0xb6,0xce,0x56,0xfb,0x85,0xf0,0x72,0x9c,0x3f,0xcb,0x7f,0x1f,0x08,0x8e,0xf9,0xeb,
+  0x0b,0x96,0xb5,0x3c,0x72,0x84,0x8e,0xc7,0xc3,0xcb,0x37,0xf7,0xd9,0xf8,0x79,0x01,
+  0x50,0xc6,0xf7,0x3f,0x74,0x61,0x46,0x80,0x0e,0xd0,0x9a,0xa0,0x6b,0xcc,0xe6,0xbf,
+  0x67,0xdb,0x0e,0xfa,0xab,0x47,0x9d,0x1f,0x9e,0x3a,0xac,0x26,0x65,0xec,0x70,0x37,
+  0x19,0xcd,0xe9,0x1e,0x47,0x3f,0x7a,0x2b,0x81,0x41,0x96,0xcb,0xc2,0x1d,0x52,0x66,
+  0xb1,0x84,0x0b,0xd6,0xf9,0x25,0x38,0x28,0x68,0xa9,0xaf,0x0e,0x42,0x25,0xd9,0x9e,
+  0x7f,0x97,0x4a,0xb2,0xf4,0x34,0x6e,0x35,0x85,0x99,0xb2,0x00,0x1c,0x8b,0x6e,0x15,
+  0x03,0x99,0x06,0x5b,0xfe,0x5d,0x1c,0xdf,0xf6,0x27,0xaa,0xbb,0x19,0x39,0x7f,0x1b,
+  0xd4,0x53,0xf7,0x28,0xb1,0xe2,0x9f,0x69,0x0d,0xb7,0xae,0xcc,0xd7,0x03,0x70,0x19,
+  0xf1,0xd8,0x91,0xe1,0xff,0x87,0x95,0x3f,0x82,0x83,0x50,0xde,0x23,0xb2,0x7d,0xf3,
+  0x20,0x02,0xbf,0xd0,0x9e,0x7f,0x6f,0x84,0x0c,0xdb,0x6a,0x50,0xbb,0x89,0x5b,0xd8,
+  0x98,0x5a,0xf9,0xf7,0x51,0x6e,0x26,0x3c,0x4f,0xe5,0x6c,0x74,0x2d,0x79,0xb4,0xed,
+  0x99,0xf4,0xcd,0x7e,0x8e,0xc5,0x3f,0xf5,0x76,0xc8,0x4f,0xb5,0x8b,0x0b,0xf6,0xa1,
+  0xbb,0xf1,0x30,0xbd,0x94,0x5e,0x38,0x72,0x26,0x58,0x6e,0xcb,0xbf,0x0b,0x07,0xe0,
+  0x6a,0xaf,0x7b,0xb4,0xf5,0xc1,0xf8,0x55,0xa9,0xb6,0xe7,0x4f,0x6c,0xf9,0xf7,0x92,
+  0x73,0x28,0xff,0xc3,0x3d,0xee,0xa7,0xca,0xdf,0x73,0x1c,0xf7,0x85,0xa3,0x6e,0x2b,
+  0xff,0xde,0x7f,0xfd,0x0e,0xf9,0x19,0xa8,0x3c,0xe6,0x5c,0x4d,0x06,0x7a,0xda,0xa5,
+  0xca,0xbe,0xa5,0xcd,0xbe,0x0b,0x66,0x2e,0xf2,0x11,0x38,0x40,0xbf,0x33,0xec,0x5c,
+  0x5b,0x7c,0xb6,0xad,0x3d,0x51,0x19,0x5f,0x6a,0xe5,0xdf,0xa3,0xc2,0x00,0x1c,0x12,
+  0x8d,0x58,0x73,0xeb,0x9a,0x00,0x4b,0x20,0x9e,0x32,0xf9,0xf9,0xa4,0x96,0x76,0x67,
+  0xa1,0x77,0x38,0xa6,0x86,0xbb,0xdd,0x93,0xf2,0xef,0x34,0x17,0xff,0x24,0x53,0xf2,
+  0xef,0xa2,0xa4,0xa5,0xe1,0x98,0x0b,0xda,0xa7,0x07,0xa4,0x99,0xff,0x6e,0xe6,0xdf,
+  0x05,0x1c,0xc6,0x98,0x96,0x5f,0x61,0x89,0xa4,0x29,0xf9,0xf7,0x83,0x40,0xe2,0x7a,
+  0x9d,0x30,0x25,0xfe,0xe9,0x10,0xf6,0x35,0xa6,0x59,0xfc,0xf3,0x88,0x96,0x88,0x9f,
+  0x1c,0xff,0x94,0xc6,0x84,0x10,0xd5,0xb4,0x30,0xcb,0x4f,0x6f,0xb6,0xe7,0xdf,0x8d,
+  0xb0,0xe7,0xb6,0x86,0xb7,0xc8,0x94,0xfc,0xfb,0x76,0x07,0xea,0x4f,0x21,0x7c,0xc7,
+  0xe6,0xd4,0x63,0x43,0xe4,0xa8,0x1e,0x1b,0x7d,0xdb,0x96,0x3f,0x4a,0xca,0x55,0x92,
+  0x13,0xc8,0x39,0x48,0xfa,0xaa,0xec,0xf9,0xf7,0xa8,0xa3,0x6f,0x77,0x42,0x5c,0xa5,
+  0x38,0xa5,0xad,0x47,0xb0,0xa0,0xc5,0x62,0x4f,0x99,0xf9,0xf7,0x36,0xd8,0x10,0x60,
+  0x5d,0x7f,0x80,0x9d,0xc1,0xaa,0xc2,0x17,0x8d,0x98,0xfa,0xd3,0xb3,0x9b,0x3d,0x46,
+  0x59,0xc6,0xe2,0xc2,0xc6,0xf3,0x4c,0xff,0x1d,0x7e,0x19,0xfd,0x81,0x80,0x73,0x9b,
+  0xe2,0x87,0xb8,0x4b,0x04,0xe7,0x36,0xc5,0xdb,0xf4,0xa7,0xd4,0xaf,0x84,0x89,0x96,
+  0x1f,0x1b,0x9b,0x92,0x7f,0x17,0xfc,0xd2,0x46,0xa8,0x4a,0x2d,0x4d,0x13,0xbf,0x70,
+  0xf9,0x93,0xf2,0xef,0x6c,0x1d,0x3d,0x10,0xc8,0x9d,0x0f,0x39,0x66,0xe5,0x8f,0x8e,
+  0xb5,0x57,0x7c,0x47,0x59,0xfa,0x43,0x96,0xcf,0x81,0xca,0x7e,0x5b,0xfe,0x1d,0xf9,
+  0x29,0xff,0x36,0x7b,0xdb,0x39,0xf7,0x83,0xfc,0xac,0xc4,0x1f,0x53,0xb7,0x8d,0x4e,
+  0xca,0xbf,0xff,0x2a,0x75,0x85,0x84,0xbf,0x8a,0x7e,0xf1,0x48,0xd9,0x1f,0x82,0xe1,
+  0xde,0x49,0xf1,0xcf,0xb3,0xf4,0xa4,0x1a,0x4e,0x77,0x1c,0xe4,0xaf,0xca,0x2c,0x01,
+  0xe5,0x62,0xfe,0x7b,0x2e,0xff,0xde,0x41,0xff,0x01,0x2a,0x2b,0xfc,0x6b,0x23,0x67,
+  0x8a,0xf6,0x77,0xa6,0xfb,0xfc,0x56,0xfe,0x5d,0x82,0xc3,0xbf,0x63,0x26,0x8b,0x1a,
+  0xe5,0x0c,0x3c,0x0f,0xe5,0xaa,0x3d,0xfe,0x29,0x9d,0x80,0x47,0xd4,0xc0,0x22,0x31,
+  0xe8,0x1b,0x80,0xfd,0xaa,0x76,0x98,0xe0,0xb4,0x99,0x7f,0x3f,0x2c,0x9c,0x14,0xc3,
+  0xcc,0x0f,0x1f,0x87,0x89,0x96,0x1a,0x2d,0xfe,0x69,0xfa,0xef,0x23,0xca,0x15,0x61,
+  0xfa,0xa0,0x3b,0xc8,0x72,0xc2,0x42,0x38,0x6b,0xd3,0x9f,0x5b,0x52,0xe3,0xfe,0x89,
+  0xfc,0x79,0x32,0xcb,0xdb,0xc3,0x84,0xa8,0xe7,0x8f,0x4c,0xff,0x7d,0x95,0x74,0x2b,
+  0xd4,0xd6,0x89,0x2c,0xff,0x7e,0xab,0x16,0xff,0xf4,0xe5,0xec,0x93,0xe5,0x8f,0xf6,
+  0x83,0x2f,0x11,0xcd,0xf8,0x02,0x66,0x6c,0x34,0xe7,0xbf,0x03,0x4b,0xbf,0x56,0x50,
+  0x96,0x0b,0x61,0xe7,0xac,0xd8,0x81,0x81,0x9c,0x7d,0xd2,0xe4,0x8f,0x51,0xbb,0x21,
+  0xd1,0x46,0x9d,0x75,0x0a,0x8b,0xc9,0x61,0x3f,0xb3,0x66,0xfe,0x7d,0x7c,0xf7,0x04,
+  0xf7,0x79,0x61,0xf3,0x07,0x0d,0xd7,0xc6,0x3f,0x0b,0x47,0xe1,0xb7,0xf2,0x3c,0xb5,
+  0x29,0x8a,0x7a,0xbe,0x8f,0xd6,0xa8,0x85,0xb6,0xf3,0x4b,0xb8,0x8b,0x6d,0x5e,0x59,
+  0x7e,0x4a,0x4c,0x3a,0xbf,0x0b,0x49,0x8a,0xe3,0x62,0xf1,0x33,0x09,0xb4,0x38,0x51,
+  0xec,0x5f,0x2e,0xd2,0x3c,0x17,0x6c,0x04,0xb9,0xc7,0xce,0xcf,0xc6,0xb4,0xb8,0x07,
+  0x70,0x1b,0x4a,0xe6,0xad,0x82,0x64,0x4f,0x3a,0x2e,0x66,0x22,0xa3,0x96,0xff,0x4e,
+  0x8e,0xd3,0x85,0x4a,0x40,0xe4,0x03,0xa0,0xd2,0x90,0xfd,0xfc,0x52,0x0f,0xec,0x10,
+  0xde,0x48,0x3d,0xad,0xb8,0x55,0x7e,0x1c,0x41,0xa6,0xf5,0x73,0xdc,0xb0,0xcf,0x38,
+  0xec,0x45,0x7f,0xb3,0xab,0x0f,0xf5,0xcb,0x2a,0xb8,0x9c,0x0c,0xb5,0x05,0xac,0xfc,
+  0xd1,0xb0,0x27,0x50,0xb1,0x61,0x90,0x64,0xc5,0x87,0x88,0x0b,0xba,0x15,0x5f,0x5a,
+  0xb4,0xf2,0x47,0xaa,0xc0,0x53,0x94,0xf1,0x47,0xfd,0x37,0x22,0x7b,0x10,0xa4,0x3d,
+  0x7e,0x8b,0x9f,0x00,0xc5,0xea,0xba,0x44,0x59,0x56,0x3c,0x4d,0x1e,0xa5,0x87,0xdb,
+  0xd2,0xa3,0xe2,0xda,0x88,0xc9,0x4f,0x20,0xf4,0x05,0x1a,0x54,0x5c,0x25,0xfc,0x09,
+  0xfa,0x21,0x3a,0xf2,0x8d,0xb6,0xf3,0x4b,0x9e,0x14,0x99,0xc8,0xd4,0xc7,0xd1,0xcd,
+  0xac,0x43,0xe1,0xc4,0x38,0xcf,0x0f,0x12,0xbd,0x9f,0xa2,0xf0,0x50,0xe6,0x68,0x3c,
+  0xb4,0x1c,0xfb,0x79,0x9e,0x71,0xa9,0x7f,0x95,0xed,0xfc,0x92,0xb2,0x03,0x5d,0xde,
+  0x9d,0x11,0xbf,0x82,0x36,0xd8,0x0e,0x81,0x3e,0xb4,0x41,0xbb,0xff,0xde,0x8e,0x2c,
+  0x17,0x9b,0xc8,0xa3,0xb0,0x9e,0x56,0xda,0xcf,0x7f,0x46,0x3d,0x0f,0xa9,0xad,0xc2,
+  0xae,0x3e,0x7f,0x05,0x19,0xe0,0x5a,0x06,0x03,0xcc,0x00,0x4c,0xff,0x5d,0x78,0x12,
+  0x4e,0x40,0x57,0xda,0x35,0xc4,0x77,0xc2,0x09,0x29,0xdc,0x39,0xe9,0xfc,0x12,0xc5,
+  0x77,0x7d,0x8e,0x9d,0x49,0xd4,0xf8,0x29,0x57,0xdb,0xf8,0x89,0x7e,0x6a,0x0f,0xf2,
+  0x33,0xb0,0x95,0xe5,0xb5,0x53,0xb5,0x6a,0xc0,0xe2,0xa7,0x2a,0x54,0x44,0x36,0x28,
+  0xbb,0x62,0xe8,0x6e,0x0c,0x09,0xfb,0x34,0x47,0xde,0xe2,0xa7,0x30,0x1b,0x36,0x88,
+  0xbe,0x88,0x76,0xbe,0xee,0xa0,0x52,0xf1,0xa6,0x88,0xec,0xc9,0xf9,0xef,0xe0,0x41,
+  0x6c,0xa6,0x63,0x28,0x3b,0xfb,0x70,0x03,0x95,0x63,0x51,0x8b,0x9f,0xa7,0xbd,0x2c,
+  0xf7,0x11,0x32,0xf2,0x2b,0x2c,0x3f,0x4d,0x1b,0xec,0xe7,0x97,0x3e,0x56,0xb4,0xb4,
+  0x7b,0x1f,0x7c,0xcc,0x85,0x63,0xd5,0xb6,0xf3,0x4b,0x85,0x17,0xe1,0x63,0x75,0xff,
+  0x37,0x5c,0x31,0xe7,0x7c,0x38,0x02,0xe1,0x48,0xc0,0xe2,0xa7,0x17,0x3d,0x96,0xee,
+  0xf4,0xae,0xf9,0x28,0x3b,0x65,0x92,0x64,0x79,0x5f,0x8b,0x9f,0x71,0x68,0x8b,0x1d,
+  0x8c,0xcb,0xd1,0xe5,0x12,0x11,0xa4,0x9d,0x10,0x88,0x88,0x16,0x3f,0xbb,0x95,0xdd,
+  0x70,0x50,0xf6,0x35,0xb2,0x63,0x83,0xb0,0x47,0xae,0x6a,0x14,0x6d,0xe7,0x97,0xda,
+  0x58,0x8e,0x28,0x14,0x0f,0x78,0xf9,0x0a,0x78,0x27,0x59,0x15,0x0d,0x58,0xfc,0x8c,
+  0xc2,0x6e,0xe9,0x12,0x3c,0x17,0x77,0xff,0x35,0x8e,0xd9,0xab,0x22,0xae,0x77,0x8b,
+  0x9f,0x22,0xba,0x60,0x63,0x34,0x48,0x02,0x2d,0x3c,0x3b,0xc8,0x34,0x5f,0x0a,0x58,
+  0xfc,0x14,0x3d,0x0b,0x83,0x1f,0x41,0x79,0xda,0xff,0x6e,0xb1,0x57,0x3c,0x2b,0xa2,
+  0x7d,0x5a,0xfc,0x14,0xd1,0x77,0xaa,0xa1,0xd9,0xd1,0xfc,0x8a,0x82,0x24,0xfe,0xb3,
+  0xa2,0x4b,0xb4,0xf8,0x59,0x06,0xa5,0xb0,0x5f,0x29,0xeb,0xcd,0x6f,0x26,0x0b,0xe0,
+  0xa7,0xb4,0xac,0x45,0xb4,0xf1,0x93,0xce,0x82,0x3f,0xd2,0x4c,0xb6,0x70,0x25,0xff,
+  0x2c,0xbc,0x48,0x6f,0x91,0x03,0x36,0x7e,0x4a,0x9d,0xec,0x8c,0xa0,0x3a,0x3d,0x83,
+  0x7b,0x2a,0xce,0xfb,0x6b,0x76,0x7e,0x0a,0x0f,0x47,0x5e,0xa0,0xdf,0xcb,0xba,0x0e,
+  0x3a,0x6f,0x20,0x27,0xe8,0xad,0x69,0x57,0xb7,0xc9,0xcf,0x3d,0xd2,0xc3,0x89,0x44,
+  0xba,0x2c,0x8a,0xfe,0x58,0x81,0xba,0x1e,0x2a,0x7b,0xb0,0xf0,0xae,0xa9,0x15,0x77,
+  0xc0,0xdf,0xa2,0x14,0xba,0x7d,0xb4,0xc5,0x4b,0xdb,0x44,0x3f,0x45,0x90,0xe6,0xf4,
+  0xa7,0xe2,0x49,0xa2,0x9f,0xee,0x83,0x0d,0x0b,0x0a,0x44,0xa0,0x34,0x30,0x24,0x5a,
+  0xf9,0xcd,0xa4,0xb0,0x9b,0xc5,0x93,0x95,0x4a,0x3f,0xca,0xbe,0x5e,0xba,0x50,0xb5,
+  0xc5,0x3f,0x29,0xda,0xe0,0x3b,0xb8,0x57,0x4d,0x4f,0x39,0x87,0xe1,0xb2,0xa0,0xe5,
+  0x8f,0xcc,0xf3,0x4b,0xca,0x53,0xd2,0xc7,0x52,0x4d,0x63,0x65,0x96,0xef,0x86,0xf1,
+  0x74,0xcd,0x9b,0x01,0x8b,0x9f,0x3d,0xa8,0x3d,0x0f,0x46,0x7d,0x77,0x27,0xbb,0xf9,
+  0x95,0x52,0xf7,0xb9,0xda,0xc1,0x68,0xc6,0xb4,0x4f,0x2a,0xcc,0x81,0x6e,0xd0,0xa4,
+  0x1e,0x8a,0x38,0x90,0x5f,0xb6,0xf1,0x53,0x04,0x61,0x67,0x57,0x34,0x4d,0x17,0x04,
+  0x49,0x54,0xc9,0x40,0x05,0xb2,0xa0,0x25,0x17,0xff,0x54,0xc4,0x15,0x74,0x4c,0x41,
+  0x7e,0x76,0x39,0x3b,0x51,0x74,0x84,0xd4,0x40,0x17,0x9f,0xe5,0xf4,0x79,0xa0,0xd7,
+  0x8f,0xc9,0x57,0x65,0x5c,0xe6,0xdf,0xe7,0x3b,0xd5,0x71,0xe3,0xfc,0x52,0x2e,0xc7,
+  0xee,0xb8,0xea,0x99,0x98,0x59,0xa3,0x36,0x1d,0x2d,0x0f,0x7b,0xaf,0xe8,0xe7,0xc1,
+  0x46,0x6d,0xfe,0xfb,0xf3,0xf1,0xf2,0xd3,0x62,0x31,0xa9,0xf2,0x1e,0xa2,0x55,0x2c,
+  0xff,0x6e,0xe9,0x4f,0xdc,0x6a,0x24,0xf9,0x54,0x94,0xf1,0xd3,0xd8,0x37,0x2d,0xfd,
+  0xb9,0x57,0xda,0x4f,0xf4,0x18,0x84,0xb6,0x07,0x38,0x2d,0xfd,0x49,0x8b,0x98,0xee,
+  0x09,0xaa,0xae,0xb6,0x56,0x3d,0xe7,0x86,0x73,0xdb,0x67,0xe9,0x4f,0x89,0xc5,0x19,
+  0xaa,0x2f,0x2e,0x7d,0x10,0x26,0x3e,0xe1,0xfc,0xa7,0x23,0xd4,0x83,0xdb,0xba,0xde,
+  0x0e,0xb9,0xfb,0xb2,0x4d,0x7f,0x3e,0xcf,0x97,0xab,0xc7,0x59,0x1e,0xef,0x50,0xac,
+  0x4a,0x9d,0xa4,0x3f,0x9b,0x38,0x2d,0x65,0x9d,0x2e,0x6e,0x12,0x8d,0xdc,0x60,0x8e,
+  0x9f,0x59,0x6e,0x96,0xba,0x7f,0x27,0xcb,0xd9,0xe8,0x67,0xd6,0xb3,0xf9,0x93,0xf4,
+  0x67,0x72,0x7f,0x2a,0x38,0xec,0x5e,0xc8,0xdf,0xe5,0xf9,0x30,0x1d,0xee,0x73,0xd9,
+  0xf8,0xf9,0xdf,0x0f,0x2b,0xcf,0x37,0xd4,0xf7,0x6f,0xde,0x32,0x6d,0x9c,0xe5,0x8f,
+  0x26,0x9f,0xff,0x3c,0x5f,0x7c,0x5c,0x0e,0x0f,0xba,0xe6,0xb2,0x7e,0xe2,0xfe,0x60,
+  0xd7,0x9f,0x5b,0x0e,0x43,0xfb,0x0a,0xdc,0xc3,0xe3,0x2d,0xa5,0x28,0x60,0xf5,0xfc,
+  0xbb,0x31,0x2e,0x09,0xe4,0x5c,0x7b,0x7a,0xd5,0x50,0x74,0x6c,0x09,0xeb,0x8b,0x76,
+  0x16,0xc0,0xe4,0xe7,0xb6,0x01,0xa9,0x95,0x6d,0xa5,0x0b,0xb4,0xb1,0xd6,0xf2,0xef,
+  0x96,0xfe,0x64,0xf9,0xf7,0x30,0x75,0x3d,0xa1,0x9d,0x9f,0xd7,0xf3,0xef,0x96,0xfe,
+  0xd4,0xa4,0x50,0xb5,0x9e,0x13,0x9e,0xa2,0x3f,0x87,0x28,0x93,0x7a,0x4d,0x99,0x72,
+  0x76,0x2e,0xdd,0xc8,0xbf,0xe7,0xf4,0xe7,0x37,0xb5,0xd4,0x3a,0x63,0xa4,0x78,0x30,
+  0xae,0x9d,0x51,0x9a,0xac,0x3f,0xab,0x94,0xce,0x4f,0xc8,0xbf,0x03,0xb2,0x60,0x1f,
+  0xca,0x4e,0x51,0xcb,0xbf,0x5f,0x7b,0xfe,0x93,0xf5,0xc5,0x65,0xcf,0xbf,0x1b,0xfc,
+  0x3c,0x7d,0xe3,0x90,0x74,0x49,0x61,0x52,0x0f,0xfb,0xf2,0xc1,0x35,0xfa,0x53,0xba,
+  0x34,0x37,0x74,0x87,0x71,0x1e,0xb3,0x4b,0xd9,0x6c,0xf1,0x73,0xad,0x94,0xf5,0x74,
+  0xc7,0x7d,0xde,0xa4,0x76,0x7e,0x09,0x58,0x22,0xde,0xe4,0x27,0x68,0xe7,0x97,0xfc,
+  0x11,0xd1,0xfb,0x62,0x9f,0x0b,0xd7,0xd1,0x24,0xfd,0xc9,0xf2,0xef,0xdc,0xb7,0x17,
+  0x89,0xa9,0x3c,0xf6,0x0e,0xbe,0x49,0xe7,0x3f,0xb7,0xe0,0x63,0xb8,0x05,0x8a,0x2b,
+  0xd5,0x30,0x54,0x7a,0x89,0x84,0xec,0xe7,0x3f,0x57,0x72,0x7b,0xa5,0x0f,0xe0,0x19,
+  0xa5,0x3a,0x35,0xc3,0x3c,0xb3,0x60,0xd3,0x9f,0x2c,0x57,0xc7,0x64,0x75,0xf6,0x1a,
+  0xfd,0xe9,0xb8,0x19,0x9e,0x75,0x54,0xd3,0xa5,0x69,0xbe,0x53,0x7a,0x36,0x31,0x45,
+  0x7f,0xde,0xd9,0x53,0x03,0x2e,0x9c,0xd2,0x25,0xe8,0x64,0x78,0xa6,0x9c,0xff,0xd4,
+  0x64,0xe7,0xc0,0xa6,0x35,0x84,0x9d,0x19,0x9a,0x72,0xfe,0xf3,0x86,0xe0,0x3f,0x0d,
+  0xdf,0x36,0xe2,0xfe,0x49,0xeb,0x59,0x40,0xfd,0x39,0xf9,0xfc,0x67,0xa7,0xf7,0x8a,
+  0x1c,0xee,0xd7,0xce,0xf9,0x5f,0x8e,0x4f,0xca,0xbf,0xe3,0x7a,0x5f,0x74,0x32,0x15,
+  0x66,0xb2,0x93,0x25,0x92,0xb4,0xf5,0x6e,0xe9,0xcf,0x87,0x23,0xad,0xa9,0xc0,0x48,
+  0x32,0x18,0x19,0x70,0x3d,0x95,0xae,0x1c,0xb6,0x9f,0xff,0xa4,0x29,0xda,0x2e,0xe3,
+  0xf2,0xf9,0x7e,0xcb,0x19,0x38,0x20,0x6b,0x5a,0x38,0xa7,0x3f,0x65,0x8f,0x0a,0x2c,
+  0xad,0x89,0xcc,0x1a,0x60,0x12,0x8e,0xbd,0xc3,0x69,0xd3,0x3e,0x59,0xfe,0xbd,0x5e,
+  0xc5,0xe7,0x8d,0x88,0xc6,0x7a,0x3f,0x6f,0xf2,0x73,0x48,0x0f,0xcf,0x66,0x66,0x8c,
+  0xe4,0x58,0x90,0xe3,0xa7,0x2a,0x7d,0x84,0x08,0xd8,0x8f,0xba,0xd5,0x59,0x07,0x86,
+  0x96,0xca,0x9a,0xf6,0xf9,0x8d,0x18,0x3b,0x1f,0xa9,0xe9,0xcf,0xee,0x32,0xc6,0x17,
+  0x9b,0xfe,0xf4,0xcb,0x87,0xf4,0xd0,0x26,0x3a,0xa5,0x74,0xca,0xf9,0x4f,0x91,0xee,
+  0x97,0xe5,0x01,0xa6,0x3f,0xa5,0x7d,0xb2,0xe6,0xc7,0x99,0xfa,0xb3,0x30,0xae,0x4c,
+  0x04,0x51,0x1e,0x7f,0xc0,0x57,0xb2,0xb5,0xa2,0x6e,0xb6,0xeb,0x4f,0x55,0xbd,0x12,
+  0xac,0x3f,0xed,0xbe,0xc0,0x8f,0xa7,0xc7,0x56,0x86,0x07,0x27,0xe5,0xdf,0xdf,0xc6,
+  0xe9,0xae,0x89,0xbb,0xbb,0xf9,0x5a,0x54,0x52,0x28,0xaa,0xec,0xe7,0x3f,0x07,0x44,
+  0xc6,0x41,0xed,0x9c,0xea,0xdf,0x30,0x0e,0xa6,0x89,0x6c,0xe7,0xa7,0xbe,0x94,0x0d,
+  0x7e,0xca,0xc4,0x67,0x3f,0xff,0xd9,0xe2,0xeb,0x33,0xdb,0x7d,0x46,0xb6,0xc5,0x3f,
+  0x7f,0x0d,0x57,0x8e,0x22,0x07,0x33,0xce,0x2a,0x7d,0xcc,0xac,0xfc,0xd1,0x39,0xf8,
+  0x0d,0xfc,0x51,0x1b,0xaa,0x86,0xab,0x54,0x3b,0x3f,0x9f,0x75,0xda,0xf9,0x79,0x1c,
+  0xba,0x7a,0x10,0x9b,0x23,0x1e,0xe6,0x6f,0xba,0x76,0x59,0xdf,0x1f,0x09,0x81,0xb6,
+  0x4d,0x12,0x1b,0x4f,0xdf,0x08,0x3b,0x33,0xdb,0x2f,0x3e,0x61,0x8f,0x7f,0x92,0x56,
+  0xd8,0xcd,0xc6,0x93,0x1d,0x42,0x0f,0x28,0xf9,0xb2,0xf9,0xfd,0x51,0x86,0x0b,0xab,
+  0xed,0x99,0x9b,0xb2,0xe2,0x0f,0x7d,0x67,0x51,0xfc,0x55,0x66,0xf3,0x87,0xad,0xef,
+  0x8f,0xa2,0xd3,0x53,0x2f,0xd0,0xda,0xfe,0xa6,0xcf,0x37,0x9c,0x27,0x2f,0xc8,0x61,
+  0xb5,0xd2,0x96,0x3f,0xba,0x71,0xaf,0x74,0x05,0x6e,0x50,0xab,0xbb,0x1a,0xf4,0x79,
+  0xd7,0xce,0x7f,0xea,0xfd,0x44,0x7e,0xba,0xd8,0x77,0x52,0xae,0xee,0x72,0x16,0x2f,
+  0x0f,0xb1,0xd8,0xbd,0xc9,0xcf,0xa2,0xc3,0x9c,0x1e,0xff,0x44,0x7f,0xec,0xef,0x18,
+  0x3f,0xe3,0xf6,0xf3,0xf3,0xa4,0x95,0x3e,0xc6,0xce,0x2f,0x85,0xe1,0x67,0x8c,0x9f,
+  0xf6,0xfc,0x11,0x76,0x3d,0x2b,0xb3,0x6d,0x7d,0xba,0x82,0x83,0x3e,0x84,0x63,0x6d,
+  0x9d,0x9f,0xef,0x86,0x13,0xca,0xbc,0x74,0x20,0xed,0xf4,0xc2,0x6b,0xd0,0xc5,0x62,
+  0xb1,0x36,0x7e,0x2a,0x63,0x92,0x71,0x7e,0x69,0x78,0xaa,0xff,0xce,0x50,0xd5,0xa5,
+  0x7d,0x67,0xa3,0x7d,0x6c,0xe4,0x62,0xe7,0x3f,0xed,0xfe,0xfb,0x03,0x1a,0x3f,0xd9,
+  0x41,0x0a,0x2c,0xf0,0x71,0x53,0x7f,0x56,0x68,0xc8,0xd1,0xea,0x12,0xec,0x7b,0x19,
+  0x89,0x98,0xe7,0x3f,0xc1,0x81,0xfc,0xf4,0xc5,0xfc,0x1e,0xf2,0x16,0x61,0x42,0x14,
+  0x0b,0x91,0x1c,0x3f,0x45,0xc6,0x4f,0x1f,0x7a,0x50,0xcc,0x7f,0xe7,0x42,0x30,0x40,
+  0x79,0x2b,0x7f,0x84,0x1a,0x53,0xa9,0x64,0x38,0x7a,0x59,0x3f,0x23,0x3f,0x68,0x3b,
+  0x3f,0xff,0x16,0x1c,0x95,0x6b,0x95,0xc0,0x16,0x9e,0x1d,0xb2,0x7f,0x30,0xe6,0xda,
+  0x66,0xf9,0xef,0x90,0xa5,0x49,0xa6,0x35,0x5a,0x88,0x4a,0xbb,0xa1,0x0a,0x44,0x5b,
+  0xfe,0xc8,0xf1,0xf2,0xba,0x75,0x2b,0x67,0x47,0xc4,0xd8,0xcc,0x97,0xdb,0x9e,0x86,
+  0x4a,0x45,0x8c,0x59,0xe7,0xe7,0x4b,0x9e,0x12,0x1f,0x52,0xca,0x14,0x71,0x30,0x72,
+  0x11,0x7e,0x23,0x54,0x47,0xed,0xf9,0x23,0xcf,0xee,0xc8,0x51,0x5a,0x1b,0x77,0x31,
+  0x4c,0xb3,0xf3,0xf3,0x36,0xfd,0xf9,0x6d,0xf8,0x25,0x7c,0xa0,0x84,0xef,0x76,0xa7,
+  0x5a,0xdf,0x92,0x2f,0x89,0xe1,0xc8,0xb5,0xe7,0xe7,0xb5,0xf8,0x2e,0x2b,0x70,0xae,
+  0x5e,0x33,0x7f,0x84,0xfe,0xbb,0xe3,0x35,0xf0,0xa5,0xc4,0xdd,0xe4,0xb3,0xc2,0x46,
+  0xc5,0x97,0x2a,0x1c,0x36,0xf3,0x47,0xfe,0x75,0xab,0x84,0x47,0x40,0x1e,0xf4,0xd7,
+  0xf9,0xee,0x24,0xad,0xaa,0x6f,0x50,0xf4,0x9b,0xf9,0xa3,0xb2,0xa2,0xf9,0xf0,0x53,
+  0x0e,0xed,0xe5,0x41,0xf2,0x35,0x68,0x57,0xcb,0x17,0xe5,0xaf,0x34,0xf3,0x47,0x7e,
+  0xef,0x2c,0xf8,0x5b,0xba,0x1f,0x39,0xe8,0xfc,0x1a,0x9c,0xa4,0xfb,0xb2,0xae,0xe1,
+  0xf2,0x5c,0xfe,0x48,0x2c,0x6a,0x83,0x77,0x75,0x1c,0xed,0xd5,0x39,0x9f,0xb6,0xf9,
+  0xef,0xe7,0x95,0xe3,0x28,0x3b,0xc5,0x7e,0x7e,0x2e,0x8b,0xd7,0xa5,0x5d,0xa7,0xcb,
+  0xad,0xef,0x8f,0x7e,0x2a,0xac,0x4f,0xa3,0xcc,0x8d,0x90,0x82,0x6c,0x1b,0xca,0x5f,
+  0x71,0x30,0x6f,0xae,0x69,0x9f,0xb8,0xf7,0x4b,0x7b,0xa8,0xa8,0xa0,0x86,0xc6,0xba,
+  0x36,0x71,0xb9,0x99,0x3f,0x8a,0x7b,0x5e,0x54,0x36,0xaa,0x28,0xab,0x81,0xcc,0x95,
+  0x58,0x02,0x07,0xfd,0x0e,0xaf,0xe9,0xbf,0x77,0xc2,0xd1,0xe4,0xc2,0x78,0x20,0xe3,
+  0x9c,0xc3,0xf2,0xc5,0xc3,0x68,0xa8,0xd6,0x3d,0x99,0x5b,0xf4,0x1c,0xfb,0x3c,0x6a,
+  0x28,0xd7,0x4f,0xeb,0xfc,0xfc,0x18,0x1c,0xf5,0xd6,0x34,0xa2,0xff,0x7e,0x11,0x96,
+  0xe9,0x2c,0x90,0x4d,0xff,0xe8,0x7e,0x39,0xc9,0x6c,0x30,0x43,0xde,0x56,0x36,0xb1,
+  0x3d,0x5c,0x26,0x72,0x2e,0xff,0x2e,0x88,0xcc,0x64,0x41,0x3b,0xf6,0xd9,0xc9,0x62,
+  0x25,0x29,0x2b,0x7f,0x24,0x71,0x2d,0x34,0x98,0xc6,0xf9,0xb8,0xbb,0xa7,0x82,0x9d,
+  0x13,0xc0,0xba,0x5c,0xfe,0x48,0x11,0xbf,0x45,0x8e,0x46,0x83,0x9c,0x4b,0xe0,0x7b,
+  0x5a,0xb2,0x50,0x47,0x71,0x6e,0xe5,0x1c,0x3f,0x4b,0x06,0x15,0x44,0x38,0xe7,0xee,
+  0x45,0x69,0x79,0x06,0xea,0x81,0x9d,0xff,0x34,0xf9,0x39,0x9e,0x1d,0x4b,0xe0,0x36,
+  0x74,0x94,0xaf,0xa3,0x7f,0x35,0x59,0x7f,0x52,0xe9,0x63,0x86,0xf0,0xac,0x93,0xfa,
+  0xc2,0xca,0x21,0x59,0xd3,0x9f,0xd6,0xf7,0x47,0x03,0x29,0x6d,0xab,0x21,0xec,0xcc,
+  0x97,0x1e,0x9c,0xb3,0x7d,0x7f,0xc4,0x3d,0xcb,0xe2,0x9f,0xc2,0xb5,0xfa,0x13,0x50,
+  0x7f,0x8e,0xe5,0xe1,0xdc,0x6e,0x77,0x32,0x08,0x69,0x93,0xac,0x4e,0xd1,0x9f,0xee,
+  0xcb,0xfc,0x2a,0x61,0x82,0xbb,0x46,0x7f,0x8e,0x21,0xc6,0x98,0xfe,0x24,0xc7,0x85,
+  0xf0,0xe4,0xf3,0x9f,0x75,0xae,0x67,0x95,0xe9,0x88,0xf7,0x45,0x3f,0xc9,0x7d,0x73,
+  0x60,0xd7,0x9f,0x99,0x56,0x0d,0xef,0x2e,0xa1,0x55,0x98,0xfa,0xfd,0xd1,0xf2,0xa7,
+  0x77,0xe0,0x36,0x3b,0x7c,0xc7,0xd7,0xe4,0x76,0x3a,0xe5,0xfb,0x23,0x17,0x7c,0x98,
+  0xa9,0x1b,0x76,0xef,0x6b,0x98,0x0e,0x2f,0x40,0x9d,0x3a,0xe9,0xfb,0xa3,0xdf,0xcc,
+  0x9b,0x90,0xc2,0x7d,0xd8,0x85,0xc3,0xb9,0x78,0x88,0xc5,0xcf,0x91,0x36,0x55,0xc5,
+  0xfd,0x61,0xdb,0xb4,0x91,0xa4,0xf1,0x7e,0xd6,0xf7,0x47,0x87,0x93,0xd3,0x24,0x26,
+  0x3b,0xd7,0x9f,0x91,0x0f,0xe8,0x7a,0xc2,0xe2,0xe7,0x73,0xc9,0x42,0x15,0xb1,0xb9,
+  0x9c,0x9c,0xbd,0xf7,0x40,0x5b,0xa5,0x5d,0x7f,0x6a,0xdf,0x1f,0x51,0x59,0x8f,0x7f,
+  0xe6,0xb4,0xbe,0x5d,0x7f,0x52,0x94,0x9d,0x7b,0xf9,0xe1,0x5c,0x20,0xd4,0xc6,0xcf,
+  0x3c,0x4d,0x0a,0x25,0x5a,0x55,0x4d,0x13,0x15,0x4e,0xe6,0xe7,0x71,0x12,0xd6,0x6d,
+  0xf7,0xa8,0xae,0xb3,0x6c,0xdf,0x1f,0xc1,0x06,0xaa,0x9d,0x9f,0x1f,0x92,0x19,0x3f,
+  0x79,0x7b,0xfc,0x53,0x20,0x9b,0x64,0xe3,0xec,0x79,0xc2,0xd0,0x6e,0x56,0xfc,0x13,
+  0x7f,0xa4,0x9d,0x9f,0xef,0x23,0xda,0x41,0xd0,0xc9,0xfa,0xb3,0x5f,0x60,0xfa,0xac,
+  0x21,0x2b,0xf4,0xa3,0x4a,0x99,0xfa,0xfd,0x91,0x26,0xe7,0xe4,0xb7,0x84,0xa9,0xdf,
+  0x1f,0x95,0xbc,0x45,0x7b,0xd8,0x8f,0xb6,0xf1,0x43,0xc2,0xa5,0xc6,0xf0,0xa4,0xef,
+  0x8f,0xbc,0xe7,0x90,0x9f,0x55,0x80,0xdb,0x3a,0x3a,0xf2,0x30,0x87,0x73,0x4e,0xfa,
+  0xfe,0x48,0xdd,0xa9,0x4b,0xe0,0x23,0xec,0x7c,0xf2,0x22,0xfb,0xf7,0x47,0xdc,0x6e,
+  0xb2,0x61,0x63,0x95,0xf2,0x19,0x76,0x80,0xe6,0xa0,0x7e,0x06,0xcb,0xe4,0x27,0x3b,
+  0x97,0xa0,0x75,0x61,0x06,0x13,0xa2,0x2c,0x10,0x6a,0x7d,0x7f,0x04,0x6d,0xf0,0x23,
+  0x91,0xd5,0x35,0x8c,0x7c,0xd2,0xf7,0x47,0x63,0x4a,0x88,0x9b,0x8e,0x7b,0x95,0x3c,
+  0xf5,0xfb,0x23,0x76,0x7e,0x5e,0x65,0xc7,0x3e,0xf9,0x27,0xe9,0x6b,0x64,0x6a,0xfc,
+  0x93,0xdb,0x1f,0x93,0xd5,0x82,0x20,0x79,0x09,0xf7,0xf7,0x55,0x53,0xe2,0x9f,0x83,
+  0x07,0xe8,0xfd,0xaa,0x73,0x8d,0xef,0x39,0xf8,0x99,0x3c,0x49,0x7f,0xb2,0xf3,0xf3,
+  0xff,0x9c,0x9a,0x97,0x9d,0xbe,0x16,0x75,0xe4,0x6f,0x07,0xa7,0x7e,0x7f,0x44,0xaf,
+  0x54,0x84,0x55,0xe7,0x3e,0x16,0x57,0x54,0xa6,0x9c,0xff,0x9c,0xf0,0x9c,0x48,0xe1,
+  0x32,0x7f,0x90,0xbf,0xf5,0xda,0xef,0x8f,0x9e,0xa3,0xeb,0x68,0x80,0x3d,0xa6,0x45,
+  0xd0,0x0f,0x7b,0xda,0xbe,0x3f,0xda,0xa1,0xb6,0xb1,0x1f,0x8d,0x92,0x1d,0xb4,0x7d,
+  0xf2,0xf7,0x47,0xec,0xfc,0x67,0x42,0xd1,0x3e,0xfb,0x6b,0xd3,0x84,0xe8,0xa4,0xef,
+  0x8f,0x0e,0x13,0x2d,0xbc,0x3e,0xca,0x6b,0x07,0x41,0x27,0x7f,0x7f,0x34,0x20,0x5c,
+  0xee,0xc7,0x1f,0x75,0x17,0xbf,0xe5,0x9a,0xa2,0x3f,0x39,0x69,0x5c,0x78,0x09,0x59,
+  0xb0,0x6c,0xb4,0x21,0x24,0x4c,0x40,0xcd,0x94,0xef,0x8f,0x60,0xa3,0xbe,0xcc,0x7d,
+  0x54,0xff,0x50,0xc7,0xfa,0xfe,0xc8,0x81,0x75,0x8a,0x76,0xe4,0xdc,0x4f,0x0f,0x09,
+  0xbe,0x49,0xfa,0x13,0x77,0x37,0x5a,0x16,0xe8,0x5b,0x1a,0x2c,0x06,0xc5,0x10,0x7f,
+  0xe6,0xf7,0x47,0xe2,0x83,0xb4,0x3f,0x18,0x1e,0xdc,0x3c,0xca,0xfb,0x53,0x13,0xa0,
+  0x9d,0x2f,0xb7,0xbe,0x3f,0x1a,0x89,0xac,0x9d,0xc7,0x96,0xf9,0x0c,0xf5,0xb4,0xe1,
+  0x17,0xe7,0xf8,0x09,0x47,0x16,0x73,0xcd,0xca,0x7d,0xd2,0xe7,0x3c,0x8e,0x1e,0x2c,
+  0x9c,0x91,0xae,0x13,0x0a,0xd5,0x79,0xc6,0x3d,0x8f,0x28,0x79,0xf3,0xb8,0xfb,0x94,
+  0xaf,0x48,0x45,0x7d,0xd3,0x56,0x03,0x2b,0x94,0xa8,0xf3,0x8c,0xd8,0x21,0x25,0x5c,
+  0x33,0x8d,0xca,0xc5,0xa2,0xd0,0xc2,0xc9,0x7a,0xc1,0xf8,0x1c,0x96,0x0d,0xcc,0xce,
+  0x38,0xb7,0x1c,0x66,0x4a,0x0e,0x95,0x8b,0xc3,0x72,0xf8,0x32,0x38,0xcc,0xba,0x23,
+  0x51,0xc7,0x5f,0x2c,0x12,0xe9,0x75,0x72,0x49,0xbf,0x63,0x0d,0xdc,0x47,0xef,0x91,
+  0xad,0x7b,0x1e,0xb9,0x1b,0xe2,0x92,0x08,0x4b,0x44,0xf6,0xa1,0x3e,0xa7,0x7f,0xa8,
+  0x6f,0xf5,0x45,0x28,0xe3,0x44,0x88,0xc8,0x12,0x15,0x64,0xa3,0x60,0xd6,0xdd,0xc3,
+  0x29,0x54,0x91,0xef,0xf5,0x97,0xf0,0x9c,0x92,0x88,0xc9,0x25,0xfe,0x12,0x30,0xfb,
+  0xe9,0xe2,0xae,0x83,0x2f,0xa9,0xd2,0xf7,0xa1,0x14,0x0b,0x8a,0x5a,0xd2,0x2c,0xe0,
+  0xce,0x9a,0xeb,0x27,0x7c,0x46,0x66,0xe3,0x1e,0x03,0x36,0xdd,0x54,0xc0,0x79,0x33,
+  0xfb,0x19,0x47,0x9d,0xba,0x11,0xe4,0xb6,0xa8,0x4c,0xbc,0x5c,0x0b,0xc8,0x54,0xe4,
+  0xcc,0x7e,0xc6,0xa6,0xad,0xe0,0x5e,0x85,0xbb,0x15,0x4f,0xca,0xb1,0x82,0x8b,0xc2,
+  0x5f,0x28,0x1e,0x5b,0x3f,0xf3,0xd7,0xe0,0x2b,0xd7,0x22,0xac,0xf0,0xdd,0x4f,0xd3,
+  0x99,0x58,0x30,0xeb,0x22,0x79,0x72,0xc2,0x25,0xf3,0x62,0xac,0x37,0x4f,0xa2,0x2e,
+  0x79,0x91,0x28,0x59,0xe3,0x29,0x2a,0x41,0xa6,0x5e,0x40,0x97,0x31,0x80,0x05,0xd5,
+  0xec,0xa7,0x93,0x0b,0x26,0x9a,0x32,0x33,0x44,0xe1,0x38,0x17,0x52,0x9b,0x82,0xf7,
+  0x88,0x82,0x6a,0xf6,0xb3,0x61,0x76,0x73,0x62,0x79,0xb0,0x58,0x2c,0x69,0x15,0xe2,
+  0xea,0xf2,0xe0,0x97,0xc5,0x12,0x6a,0xf6,0x33,0x02,0x71,0x7c,0x4c,0x44,0xc4,0xfe,
+  0x37,0x27,0x44,0x7c,0x30,0x58,0x7d,0xb9,0x5b,0xa8,0x48,0x14,0xca,0x91,0xa8,0xb4,
+  0x15,0x0b,0x5e,0xb9,0x21,0x5a,0x64,0xd5,0xb1,0xc1,0x5f,0x02,0x31,0x5a,0x82,0x05,
+  0x2e,0x02,0x45,0xb4,0x44,0x31,0xfb,0x99,0xc7,0x2d,0xa2,0xf7,0xc6,0x4b,0xbc,0x8e,
+  0x3c,0xee,0x8b,0x34,0x16,0xf7,0x78,0x1d,0x60,0xce,0x7b,0x31,0x27,0xd0,0x7c,0x59,
+  0x8a,0x0a,0xc5,0x0e,0x01,0x27,0x04,0x0b,0xd6,0xbc,0x37,0xf2,0x5f,0xa4,0x6d,0xf1,
+  0x6f,0x78,0x5d,0x4b,0xc8,0x17,0x13,0x2f,0xc7,0x6f,0xf1,0x16,0x9a,0xf7,0x3c,0xb2,
+  0x64,0xda,0xea,0xc4,0x99,0xf8,0x57,0xbc,0x25,0xeb,0x1d,0xab,0x13,0xf7,0xc5,0xff,
+  0xd2,0x5b,0x62,0xda,0xe0,0xe2,0x25,0xdc,0x6a,0xba,0x3c,0x7e,0x9d,0xb7,0xf0,0x45,
+  0x2c,0x9c,0x61,0x05,0xb5,0xc8,0xac,0xcb,0x9b,0x47,0x5d,0xf1,0x7b,0xbc,0x9e,0x17,
+  0x67,0xce,0xa3,0xa5,0xf1,0x06,0x6c,0x57,0x94,0x8b,0x6d,0x03,0x0e,0x7f,0x93,0x4c,
+  0xc4,0xc5,0x2d,0x5c,0x1c,0x27,0xf1,0x3a,0xb4,0xcf,0x5c,0x8d,0x90,0xc7,0x95,0x25,
+  0x96,0xc7,0x67,0x7a,0x1d,0xeb,0xb9,0x32,0x1a,0x8d,0x7f,0xd9,0xeb,0xa0,0xb9,0x75,
+  0xb4,0x58,0x11,0x9a,0xb9,0x26,0x98,0x01,0x92,0xea,0x68,0x86,0x26,0xf8,0x0a,0x78,
+  0xcc,0x7b,0x2e,0x26,0x10,0x4f,0x8b,0x38,0x9e,0xd0,0x02,0x71,0x1c,0x4f,0xd4,0x3a,
+  0xd4,0xec,0x4b,0x44,0x90,0x77,0x7a,0xe5,0x25,0xfe,0xa2,0x16,0x41,0x4e,0x48,0x72,
+  0xc4,0x5f,0x64,0xab,0x2b,0x53,0x54,0x4f,0xf0,0x4b,0xae,0x92,0x08,0xa7,0xf4,0xdc,
+  0x5b,0xe6,0x71,0x95,0x28,0x66,0x3f,0x09,0x17,0xeb,0xbf,0x17,0x4d,0xd6,0x11,0xe1,
+  0x62,0xf4,0xde,0x20,0x16,0x94,0x5c,0x5f,0x70,0xc5,0xc7,0x8b,0x24,0x10,0x60,0x91,
+  0x28,0x28,0xe0,0x45,0xfb,0x34,0x6b,0x60,0xf1,0xdd,0x11,0x5f,0x82,0xca,0xb2,0x28,
+  0x12,0x22,0xeb,0x05,0x30,0xfb,0xa9,0x2c,0x63,0xeb,0xef,0x2f,0xa0,0x84,0x3a,0x72,
+  0x85,0x5c,0x5f,0x8e,0x28,0x8b,0x9a,0xd9,0x09,0x18,0x5c,0x92,0x0e,0xa6,0x94,0xaf,
+  0x83,0x3b,0xcd,0x71,0x01,0x98,0x13,0xe7,0x4a,0x81,0xe0,0xbb,0xcf,0x94,0xf1,0xe1,
+  0x4b,0xa0,0x48,0x35,0xab,0x24,0x98,0x0d,0xf9,0x40,0x14,0x78,0x05,0x2a,0x58,0xc1,
+  0xfc,0x8b,0x1d,0x78,0x55,0x70,0xf3,0xee,0x6f,0x52,0x8a,0x25,0xa1,0x8f,0x2b,0x83,
+  0x68,0xec,0x1e,0x49,0xb0,0xda,0xf9,0x1c,0xdf,0x3a,0xf7,0xd5,0xe0,0xcc,0x8e,0x92,
+  0xc7,0xb9,0x95,0xea,0xdd,0xc1,0x2f,0x77,0x94,0x50,0xdb,0x3d,0x6b,0xf1,0x56,0x11,
+  0x05,0x52,0x78,0x8b,0x29,0xf7,0x14,0x85,0x60,0x91,0x57,0x58,0xc2,0x15,0x25,0x95,
+  0x78,0x91,0xb7,0x0d,0x0b,0xb6,0x7e,0xf6,0x14,0x89,0xf7,0x0a,0x5f,0xe2,0x4b,0x94,
+  0xfb,0x63,0x45,0xf7,0x0a,0x25,0xdc,0x97,0x14,0xab,0x5d,0x59,0x44,0x54,0x5a,0x3c,
+  0xf2,0xba,0x28,0x16,0xee,0x65,0x05,0xab,0xae,0x60,0x31,0xa1,0xc0,0x04,0x68,0x81,
+  0x83,0x50,0x25,0x2d,0xf9,0xad,0x3b,0x82,0x8b,0xbf,0x07,0xda,0x7a,0x56,0x07,0x45,
+  0x2c,0x70,0xdb,0xd4,0x5b,0x82,0xa2,0xed,0x9e,0x8e,0x35,0xdc,0x7d,0xf4,0x2b,0xf2,
+  0xf5,0xfd,0x5a,0xe1,0x2f,0x91,0x59,0x66,0x1d,0x8f,0x50,0x91,0x82,0x82,0x8b,0x63,
+  0x85,0xa2,0x90,0xe0,0x2a,0xb2,0xee,0x59,0x3f,0xb1,0x6c,0xe2,0xef,0x27,0x2e,0x4e,
+  0x7c,0x6c,0x16,0xe0,0xdf,0x75,0x85,0xdf,0x58,0x76,0xb5,0xf7,0xa5,0xcc,0xfe,0x1f,
+  0x87,0x5f,0x77,0xd6,0xb2,0xc2,0x2a,0xdb,0x3d,0xeb,0x97,0x4d,0xcc,0xa8,0xe9,0x1b,
+  0xf8,0xb8,0xbe,0xae,0xe9,0x24,0x2b,0x7c,0x60,0xab,0xf3,0x46,0xcf,0x16,0xcf,0x6b,
+  0xeb,0xf8,0xc1,0xad,0xde,0xe8,0x8b,0x33,0x0e,0x60,0xc1,0xaa,0x9b,0x06,0xab,0x95,
+  0x1d,0xb1,0x9b,0x3c,0xf9,0x47,0x48,0xb3,0x52,0x2a,0xdd,0x24,0xe4,0x5b,0xef,0x20,
+  0x98,0x9c,0x77,0xac,0xe6,0x74,0xce,0x9b,0x75,0x1a,0xe7,0xe3,0xc5,0x5e,0x61,0xbd,
+  0xc9,0x79,0xab,0x5d,0xfc,0x7e,0xed,0xef,0xa9,0x08,0x16,0xaf,0xad,0x31,0x13,0xd6,
+  0x24,0x4a,0xd5,0x2f,0xc8,0x45,0xfd,0xc2,0x1a,0xae,0x94,0x62,0xc1,0xba,0x27,0x00,
+  0xb6,0x93,0xf3,0x44,0xdb,0x1f,0x64,0x31,0x6b,0x24,0x61,0x0e,0x97,0x4f,0x23,0xcd,
+  0xd2,0xcf,0x85,0xd9,0x9c,0x48,0x19,0xe7,0xcd,0xba,0x32,0x58,0x9a,0x28,0x4e,0x37,
+  0x76,0x16,0x55,0x09,0x51,0xaa,0x15,0xcc,0xa7,0xa9,0x55,0xb8,0x66,0x3d,0xd4,0x11,
+  0xe4,0xee,0x82,0x7b,0x70,0xcd,0x62,0xc1,0xd8,0x52,0xd9,0x81,0x5a,0xe1,0x16,0x28,
+  0x52,0x84,0xe5,0x9c,0x07,0xbe,0x40,0xd9,0x82,0xe2,0x8c,0x6d,0x1a,0xdb,0x29,0x44,
+  0x62,0xa7,0xde,0xd8,0x01,0x32,0x30,0x0a,0x56,0x9d,0xc0,0x00,0x88,0xcb,0x80,0x62,
+  0x61,0x3b,0x5b,0x0f,0xd4,0xa8,0x93,0x38,0x05,0x55,0xc7,0x76,0x98,0x03,0xf9,0x94,
+  0x3c,0x80,0xef,0x80,0x85,0x16,0xe3,0x71,0xca,0xe2,0xbb,0xf3,0xe2,0xc8,0xf9,0x06,
+  0x51,0xea,0x15,0x82,0x7a,0x21,0xc7,0x10,0x05,0x6f,0x2f,0x1b,0x78,0xc7,0xe7,0x18,
+  0x05,0xa3,0x1d,0x38,0x21,0x48,0xd9,0xfe,0x00,0xbd,0x10,0xec,0xd1,0x0a,0x66,0xdd,
+  0xe2,0x06,0xa1,0x19,0x31,0xbd,0x44,0x44,0xbe,0xc4,0x7b,0xb4,0x02,0xcd,0xdd,0x93,
+  0x63,0x9c,0x17,0x91,0x75,0xc0,0xf6,0x29,0x17,0x2b,0xe4,0xc6,0x2c,0xc6,0x21,0x97,
+  0xcc,0x76,0xd8,0x17,0xd6,0xce,0xbc,0xa7,0x82,0xef,0xe1,0x81,0xc5,0x6c,0x6c,0x70,
+  0x0b,0x64,0x85,0x88,0x71,0xcf,0x28,0x4e,0xca,0x22,0x2a,0xc5,0x05,0xaf,0x90,0x2b,
+  0x98,0xec,0x89,0x6a,0xe7,0x6c,0x10,0xef,0xa2,0x80,0xee,0x9b,0x5e,0x00,0xf3,0x9e,
+  0x8c,0xf3,0x0c,0xef,0xf9,0x4b,0x8c,0x42,0xa1,0xc9,0x3a,0x6e,0x89,0xb0,0x3a,0x51,
+  0x1a,0xff,0x82,0xb7,0xe8,0x45,0x61,0xf5,0xba,0x1d,0xac,0x60,0xbe,0x1f,0x8e,0xf2,
+  0x6a,0xba,0x23,0x7e,0x93,0x37,0xff,0x45,0xb2,0x9a,0xde,0xc7,0x0a,0xb9,0xba,0x18,
+  0xe3,0x3c,0x6e,0x0b,0xb8,0x3f,0xbc,0xe8,0x60,0x37,0xc0,0x42,0xaf,0x39,0x9e,0xc5,
+  0x50,0x41,0x6f,0x97,0x8b,0xa3,0xc2,0x56,0xae,0x82,0x36,0xd9,0xed,0x53,0xc1,0x77,
+  0x28,0xa3,0xde,0x78,0x9e,0x97,0x5b,0x0f,0xf7,0x27,0xb4,0x82,0x69,0x4b,0x8b,0xe3,
+  0x8e,0x05,0xdc,0x2c,0x34,0x87,0xa2,0xac,0xb0,0x56,0x2f,0x98,0x73,0xc4,0xdd,0x0d,
+  0x2b,0xe8,0xf5,0x72,0x5e,0x94,0xdb,0x8a,0x05,0xc3,0x50,0x73,0xfd,0x64,0xe3,0xc9,
+  0xf6,0x00,0xa9,0x25,0x57,0xb0,0xc6,0x33,0x02,0x31,0x44,0x7f,0xa3,0x58,0x44,0x04,
+  0x85,0x6a,0x05,0x30,0xfb,0x49,0x20,0x86,0x7b,0x80,0xc3,0xc5,0x35,0xe4,0x0a,0x8a,
+  0xd9,0x4f,0x51,0x78,0x00,0x72,0xba,0x46,0x2f,0x58,0xe3,0x19,0x21,0x40,0x0d,0xce,
+  0x1b,0x05,0xf3,0x9e,0x9c,0x52,0x11,0x77,0x78,0x61,0x92,0x7d,0x9a,0xfd,0x54,0x80,
+  0xfd,0xa5,0x85,0x39,0x4a,0x7e,0x8a,0xac,0x80,0x52,0xcd,0x50,0xcd,0x7b,0xc6,0xe7,
+  0xf8,0xb9,0xe9,0xd0,0x40,0xa5,0xac,0xb0,0x80,0xbb,0x81,0x15,0x72,0xef,0x1e,0xc3,
+  0xa5,0x51,0xa6,0xb8,0x62,0xbc,0x07,0x8e,0xd0,0x79,0x8a,0x28,0xf1,0x82,0xcd,0x3e,
+  0x05,0x98,0xad,0x14,0x4a,0xfc,0xbd,0xf0,0x3b,0x98,0xbf,0x48,0xfb,0xa5,0x5e,0xab,
+  0x9f,0xc2,0xfd,0x3d,0xde,0xe0,0x92,0xd2,0xa2,0x56,0x66,0x9f,0xc1,0x25,0x2e,0x9b,
+  0x7d,0x2a,0x68,0xea,0xb6,0xf5,0x65,0xe3,0xbc,0xc2,0x45,0x1b,0x43,0x0c,0xef,0x65,
+  0x45,0x1d,0x8d,0x0f,0x5c,0xaf,0x15,0x6c,0xf6,0xa9,0x4a,0x3f,0xf0,0xcc,0x5a,0x5c,
+  0xb4,0x45,0x69,0x8c,0xc5,0x3c,0xc2,0x62,0xae,0x48,0xb1,0xd6,0x11,0x1b,0x7a,0x22,
+  0x94,0x25,0xc4,0xb8,0xa2,0x4f,0x06,0x98,0x57,0x0e,0xef,0x42,0x01,0x67,0x14,0xac,
+  0xf1,0xbc,0x93,0xbf,0x47,0x79,0x79,0xf0,0x96,0xf9,0x85,0x66,0xc1,0xbc,0x27,0x17,
+  0xad,0x58,0x53,0x58,0x4a,0xbe,0x50,0x56,0xa4,0x36,0xae,0xc9,0xdf,0x31,0x99,0x59,
+  0x33,0x6c,0x9c,0xef,0x29,0x0a,0x35,0x36,0x6d,0xb1,0x9e,0xf7,0xbf,0xcb,0xf9,0x4a,
+  0x5b,0xbb,0xab,0x53,0x38,0x5f,0x63,0xbf,0xe7,0x14,0xce,0xdf,0xea,0xbd,0xeb,0x8d,
+  0x47,0x0e,0x0c,0xbd,0x77,0xe9,0xd6,0x9f,0xdc,0x75,0x76,0x06,0x2b,0x58,0x75,0xe8,
+  0xc3,0xec,0x04,0xbf,0x52,0x50,0xda,0x6b,0x14,0x24,0xab,0x4e,0x23,0x1f,0x8e,0x9d,
+  0x64,0x15,0xac,0x4b,0x8b,0x38,0x31,0x1a,0x9a,0x85,0x6b,0xda,0x95,0xaa,0xd7,0xb6,
+  0x63,0xd9,0x67,0x48,0xea,0x21,0x1f,0xbd,0x60,0xd6,0x4c,0x99,0x71,0xa3,0x60,0xd4,
+  0x5d,0xdb,0xce,0x56,0x77,0x4d,0x4b,0xeb,0x4f,0x86,0x15,0xb4,0x87,0x76,0x42,0xa7,
+  0x32,0x57,0x2a,0x68,0x23,0x5a,0xa1,0xb4,0xd7,0x6c,0xa7,0xf5,0x73,0x12,0x99,0xac,
+  0x7b,0x5e,0xfb,0x7e,0x66,0x9d,0xc4,0xfe,0x3e,0xda,0x40,0xee,0xfd,0x06,0xe0,0x7b,
+  0x50,0xda,0x6b,0x5a,0x8c,0xfe,0x27,0x34,0x14,0x52,0xaa,0x1a,0x05,0xc9,0xea,0x0b,
+  0x11,0x58,0x0c,0x96,0x7d,0x6f,0x6d,0x14,0xec,0x93,0xab,0x3d,0x06,0x72,0xcf,0xb3,
+  0xff,0xd1,0x33,0x89,0xf2,0x41,0x18,0xc8,0xfd,0x4b,0x2f,0x18,0xbe,0xf6,0xbf,0x76,
+  0xd5,0xd5,0x5d,0xfb,0x33,0xb7,0xfb,0xdf,0x6c,0xf6,0x1f,0xb8,0xea,0x27,0x26,0x26,
+  0xd4,0x49,0x85,0xff,0x37,0xeb,0x72,0x36,0x2f,0x91,0xff,0xf3,0x36,0xff,0x49,0xed,
+  0xa6,0xda,0xae,0x35,0xb7,0xff,0x97,0x6c,0xde,0x6e,0xd7,0xd6,0x26,0xfc,0xbf,0x6c,
+  0xf3,0x80,0xa6,0xae,0xbd,0xdf,0x54,0x9b,0xff,0x17,0xdb,0xc1,0x27,0xbc,0x9f,0xed,
+  0xfa,0x17,0xde,0x1c,0x98,0xcd,0xc3,0x35,0xd7,0xa7,0x36,0xff,0x1f,0xa8,0xfb,0x97,
+  0x2f,0xf6,0xb7,0x1c,0x89,0xf6,0xff,0x45,0xbf,0xfd,0xf7,0xb6,0xf9,0xf4,0xfa,0xf4,
+  0xfa,0xf4,0xfa,0xf4,0xfa,0xf4,0xfa,0xf4,0xfa,0xff,0xe5,0xd2,0xf6,0x49,0xa2,0xed,
+  0x93,0xea,0x7f,0x76,0x5f,0x3e,0xbd,0x3e,0xbd,0x3e,0xbd,0x3e,0xbd,0x3e,0xbd,0x3e,
+  0xbd,0xfe,0x33,0xae,0x20,0xfb,0x73,0x09,0x50,0xf9,0x6b,0xe3,0xef,0xff,0xf3,0x41,
+  0x50,0xa6,0xfd,0xeb,0xbf,0xaf,0xfd,0x9e,0x23,0x08,0x69,0xce,0x6a,0xbf,0x3b,0x35,
+  0xb5,0xaf,0xff,0x13,0x87,0x7b,0xf6,0xdd,0xd4,0x60,0x00,0x00,
diff --git a/u-boot/board/esd/pci405/pci405.c b/u-boot/board/esd/pci405/pci405.c
new file mode 100644
index 0000000..c1bac6a
--- /dev/null
+++ b/u-boot/board/esd/pci405/pci405.c
@@ -0,0 +1,382 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/io.h>
+
+#include "pci405.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Prototypes */
+unsigned long fpga_done_state(void);
+unsigned long fpga_init_state(void);
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here */
+#define FPGA_DONE_STATE (fpga_done_state())
+#define FPGA_INIT_STATE (fpga_init_state())
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
+
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
+
+
+int board_revision(void)
+{
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of PCI405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in_be32((void*)GPIO0_IR) & 0x00100200;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	switch (value) {
+	case 0x00100200:
+		/* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
+		return 1;
+	case 0x00000200:
+		/* CS2==0 && IRQ5==1 -> version 1.2 */
+		return 2;
+	case 0x00000000:
+		/* CS2==0 && IRQ5==0 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && IRQ5==0 -> version 1.4 */
+		return 4;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
+unsigned long fpga_done_state(void)
+{
+	if (gd->board_type < 2) {
+		return FPGA_DONE_STATE_V11;
+	} else {
+		return FPGA_DONE_STATE_V12;
+	}
+}
+
+
+unsigned long fpga_init_state(void)
+{
+	if (gd->board_type < 2) {
+		return FPGA_INIT_STATE_V11;
+	} else {
+		return FPGA_INIT_STATE_V12;
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+	 */
+	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
+	out_be32((void*)GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
+	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low            */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+
+	/*
+	 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned int *ptr;
+	unsigned int *magic;
+
+	/*
+	 * On PCI-405 the environment is saved in eeprom!
+	 * FPGA can be gzip compressed (malloc) and booted this late.
+	 */
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Check if magic for pci reconfig is written
+	 */
+	magic = (unsigned int *)0x00000004;
+	if (*magic == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Rewrite pci config regs (only after soft-reset with magic set)
+		 */
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+			puts("Restoring PCI Configurations Regs!\n");
+			ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+			for (i=0; i<0x40; i+=4) {
+				pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
+			}
+		}
+		mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+
+		*magic = 0;      /* clear pci reconfig magic again */
+	}
+
+	/*
+	 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
+	 */
+#define PCI0_BRDGOPT1 0x4a
+	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
+
+	/*
+	 * Enable fairness and high bus utilization
+	 */
+	mtdcr(PLB0_ACR, 0x98000000);
+
+	free(dst);
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PCI405");
+	} else {
+		puts (str);
+	}
+
+	gd->board_type = board_revision();
+	printf(" (Rev 1.%ld", gd->board_type);
+
+	if (gd->board_type >= 2) {
+		unsigned long CPC0_CR0Reg;
+		unsigned long value;
+
+		/*
+		 * Setup GPIO pins (Trace/GPIO1 to GPIO)
+		 */
+		CPC0_CR0Reg = mfdcr(CPC0_CR0);
+		mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
+		out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
+		out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
+		udelay(1000);                   /* wait some time before reading input */
+		value = in_be32((void*)GPIO0_IR) & 0x40000000;       /* get config bits */
+		if (value) {
+			puts(", 33 MHz PCI");
+		} else {
+			puts(", 66 MHz PCI");
+		}
+	}
+
+	puts(")\n");
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#define UART1_MCR 0xef600404
+int wpeeprom(int wp)
+{
+	int wp_state = wp;
+
+	if (wp == 1) {
+		out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
+	} else if (wp == 0) {
+		out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
+	} else {
+		if (in_8((void *)UART1_MCR) & 0x02) {
+			wp_state = 0;
+		} else {
+			wp_state = 1;
+		}
+	}
+	return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int wp = -1;
+	if (argc >= 2) {
+		if (argv[1][0] == '1') {
+			wp = 1;
+		} else if (argv[1][0] == '0') {
+			wp = 0;
+		}
+	}
+
+	wp = wpeeprom(wp);
+	printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+	return 0;
+}
+
+U_BOOT_CMD(
+	wpeeprom,	2,	1,	do_wpeeprom,
+	"Check/Enable/Disable I2C EEPROM write protection",
+	"wpeeprom\n"
+	"    - check I2C EEPROM write protection state\n"
+	"wpeeprom 1\n"
+	"    - enable I2C EEPROM write protection\n"
+	"wpeeprom 0\n"
+	"    - disable I2C EEPROM write protection"
+);
diff --git a/u-boot/board/esd/pci405/pci405.h b/u-boot/board/esd/pci405/pci405.h
new file mode 100644
index 0000000..c11a20f
--- /dev/null
+++ b/u-boot/board/esd/pci405/pci405.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCI405_H_
+#define _PCI405_H_
+
+#define PCI_REGS_LEN    0x100
+#define PCI_REGS_ADDR   ((unsigned long)0x01000000 - PCI_REGS_LEN)
+
+#define PCI_RECONFIG_MAGIC  0x07081967
+
+#endif /* _PCI405_H_ */
diff --git a/u-boot/board/esd/pci405/writeibm.S b/u-boot/board/esd/pci405/writeibm.S
new file mode 100644
index 0000000..5925bc6
--- /dev/null
+++ b/u-boot/board/esd/pci405/writeibm.S
@@ -0,0 +1,227 @@
+/*------------------------------------------------------------------------------+ */
+/* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------------- */
+
+/*----------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*	Bank 0 - Flash and SRAM */
+/*	Bank 1 - NVRAM/RTC */
+/*	Bank 2 - Keyboard/Mouse controller */
+/*	Bank 3 - IR controller */
+/*	Bank 4 - not used */
+/*	Bank 5 - not used */
+/*	Bank 6 - not used */
+/*	Bank 7 - FPGA registers */
+/*----------------------------------------------------------------------------- */
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	write_without_sync
+write_without_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start1:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+
+	b       start1
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_sync
+write_with_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start2:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+	sync
+
+	b       start2
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_less_sync
+write_with_less_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start2b:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+/*        sync */
+
+	b       start2b
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_more_sync
+write_with_more_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start3:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+	sync
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+	sync
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id (PCIC0_SBSYSVID)*/
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+	sync
+
+	b       start3
+
+	blr	/* never reached !!!! */
diff --git a/u-boot/board/esd/pf5200/Makefile b/u-boot/board/esd/pf5200/Makefile
new file mode 100644
index 0000000..2f42566
--- /dev/null
+++ b/u-boot/board/esd/pf5200/Makefile
@@ -0,0 +1,60 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+# ifneq ($(OBJTREE),$(SRCTREE))
+# $(shell mkdir -p $(obj)../common/xilinx_jtag)
+# endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+#	  ../common/xilinx_jtag/micro.o \
+#	  ../common/xilinx_jtag/ports.o
+
+# COBJS	= $(BOARD).o flash.o $(CPLD)
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/pf5200/flash.c b/u-boot/board/esd/pf5200/flash.c
new file mode 100644
index 0000000..9850445
--- /dev/null
+++ b/u-boot/board/esd/pf5200/flash.c
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK           0x00FF
+
+#define FPW                     FLASH_PORT_WIDTH
+#define FPWV                    FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1            0x0555
+#define FLASH_CYCLE2            0x0aaa
+#define FLASH_ID1               0x00
+#define FLASH_ID2               0x01
+#define FLASH_ID3               0x0E
+#define FLASH_ID4               0x0F
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_reset(flash_info_t * info);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(uint, ulong, ulong);
+
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+	flash_preinit();
+
+	/* There is only ONE FLASH device */
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
+	size += flash_info[i].size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef  CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t * info) {
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base) {
+	int i;
+	flash_info_t *info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		info = &flash_info[i];
+		if ((info->size) && (info->start[0] <= base)
+		    && (base <= info->start[0] + info->size - 1)) {
+			break;
+		}
+	}
+	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info(flash_info_t * info) {
+	int i;
+	char *fmt;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt);
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+	       info->sector_count);
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		ulong size;
+		int erased;
+		ulong *flash = (unsigned long *)info->start[i];
+
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+		    (i !=
+		     (info->sector_count - 1)) ? (info->start[i + 1] -
+						  info->start[i]) >> 2 : (info->
+									  start
+									  [0] +
+									  info->
+									  size -
+									  info->
+									  start
+									  [i])
+		    >> 2;
+
+		for (flash = (unsigned long *)info->start[i], erased = 1;
+		     (flash != (unsigned long *)info->start[i] + size)
+		     && erased; flash++) {
+			erased = *flash == ~0x0UL;
+		}
+		printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
+		       info->protect[i] ? "(RO)" : "    ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info) {
+	int i;
+
+	/* Write auto select command: read Manufacturer ID                     */
+	/* Write auto select command sequence and test FLASH answer            */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD        */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.         */
+	/* This works for any bus width and any FLASH device width.            */
+	udelay(100);
+	switch (addr[FLASH_ID1] & 0x00ff) {
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus.     */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch ((FPW) addr[FLASH_ID2]) {
+		case (FPW) AMD_ID_MIRROR:
+			/* MIRROR BIT FLASH, read more ID bytes */
+			if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
+			    && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
+				/* attention: only the first 16 MB will be used in u-boot */
+				info->flash_id += FLASH_AMLV256U;
+				info->sector_count = 512;
+				info->size = 0x02000000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] =
+					    (ulong) addr + 0x10000 * i;
+				}
+				break;
+			}
+			/* fall thru to here ! */
+		default:
+			printf("unknown AMD device=%x %x %x",
+			       (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
+			       (FPW) addr[FLASH_ID4]);
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0x800000;
+			break;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+	}
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last) {
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	last = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+		if (info->protect[sect] != 0) {	/* protected, skip it */
+			continue;
+		}
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel. */
+		/* Let's wait 1 ms.                            */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {
+				/* every second */
+				putc('.');
+				last = get_timer(0);
+			}
+		}
+		/* show that we're waiting */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {
+			/* every second */
+			putc('.');
+			last = get_timer(0);
+		}
+		flash_reset(info);	/* reset to read mode */
+	}
+	printf(" done\n");
+	return (rcode);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+	return (res);
+}
diff --git a/u-boot/board/esd/pf5200/mt46v16m16-75.h b/u-boot/board/esd/pf5200/mt46v16m16-75.h
new file mode 100644
index 0000000..cf63806
--- /dev/null
+++ b/u-boot/board/esd/pf5200/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/esd/pf5200/pf5200.c b/u-boot/board/esd/pf5200/pf5200.c
new file mode 100644
index 0000000..83dbfcb
--- /dev/null
+++ b/u-boot/board/esd/pf5200/pf5200.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd ParaFinder (pf5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+	}
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+	*(vu_char *) CONFIG_SYS_CS1_START = 0x02;	/* Red Power LED on */
+	__asm__ volatile ("sync");
+
+	*(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
+	__asm__ volatile ("sync");
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void power_set_reset(int power)
+{
+	debug("ide_set_reset(%d)\n", power);
+
+	if (power) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
+		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
+		    0) {
+			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
+			    GPIO_USB0;
+		}
+
+	}
+}
+
+int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	power_set_reset(1);
+	return (0);
+}
+
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
+
+int phypower(int flag)
+{
+	u32 addr;
+	vu_long *reg;
+	int status;
+	pci_dev_t dev;
+
+	dev = PCI_BDF(0, 0x18, 0);
+	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
+	if (status == 0) {
+		reg = (vu_long *) (addr + 0x00000040);
+		*reg |= 0x40000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x001000c);
+		*reg |= 0x20000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x0010004);
+		if (flag != 0) {
+			*reg &= ~0x20000000;
+		} else {
+			*reg |= 0x20000000;
+		}
+		__asm__ volatile ("sync");
+	}
+	return (status);
+}
+
+int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	int status;
+
+	if (argv[1][0] == '0') {
+		status = phypower(0);
+	} else {
+		status = phypower(1);
+	}
+	return (0);
+}
+
+U_BOOT_CMD(phypower, 2, 2, do_phypower,
+	   "Switch power of ethernet phy", "");
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	"Write some data to pcibus",
+	"<addr> <size>\n"
+	""
+);
diff --git a/u-boot/board/esd/plu405/Makefile b/u-boot/board/esd/plu405/Makefile
new file mode 100644
index 0000000..401622f
--- /dev/null
+++ b/u-boot/board/esd/plu405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/plu405/flash.c b/u-boot/board/esd/plu405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/plu405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/plu405/fpgadata.c b/u-boot/board/esd/plu405/fpgadata.c
new file mode 100644
index 0000000..dc8c88b
--- /dev/null
+++ b/u-boot/board/esd/plu405/fpgadata.c
@@ -0,0 +1,1179 @@
+  0x1f,0x8b,0x08,0x08,0x04,0x44,0x9f,0x46,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x31,0x2e,0x62,0x69,0x74,0x00,0x94,0x9a,0x0f,0x70,0x14,0x55,0x9e,
+  0xc7,0x7f,0xfd,0xba,0x93,0x74,0xa6,0x3b,0xe9,0x36,0x7f,0x30,0xb7,0x08,0xd7,0x19,
+  0x07,0x76,0xc4,0x61,0x18,0x42,0x80,0x98,0x0d,0x49,0x33,0xa4,0xac,0x71,0xc9,0x1e,
+  0xf1,0xce,0xbb,0xe2,0xf6,0xbc,0xdd,0x11,0x71,0x8f,0xbb,0xe2,0x2c,0xd6,0xdd,0xb3,
+  0xb8,0x3b,0x4b,0x5f,0x66,0xa2,0x04,0x92,0x92,0x01,0x39,0x37,0xba,0xac,0x35,0x40,
+  0x6e,0x8d,0x4a,0x59,0x11,0x75,0x8d,0x82,0xbb,0x4d,0x0c,0x3a,0x60,0xd4,0xb9,0x94,
+  0x7b,0x8b,0x7f,0x8e,0x6d,0xd8,0xc0,0x46,0x89,0x3a,0xcb,0xa2,0x06,0x65,0xcd,0xbd,
+  0xd7,0x3d,0xdd,0xd3,0x99,0x9e,0x04,0x37,0x5a,0xc5,0x2f,0xaf,0x1f,0x8f,0xf7,0xfb,
+  0xcd,0xef,0xfd,0x7e,0x9f,0xfe,0xbe,0x81,0x52,0x29,0x63,0xfe,0x07,0xc0,0xdc,0x06,
+  0xd2,0x96,0xcd,0xff,0x56,0x1f,0x5a,0xfe,0xfd,0xa5,0xdf,0x5f,0x1a,0xbc,0xf3,0xf6,
+  0x8d,0xb0,0x01,0x84,0xba,0x1f,0x2d,0x0f,0xdd,0xf1,0xe3,0x1f,0x2e,0xad,0xaf,0x87,
+  0xdb,0xc9,0x6f,0xa1,0xd0,0xca,0x25,0xe4,0xff,0xa5,0x37,0xc0,0x46,0x28,0x5d,0x5a,
+  0xd7,0xb8,0xfc,0x86,0xc6,0xa5,0x2b,0xe1,0x0e,0x60,0x96,0xf5,0x4d,0x91,0x9f,0x27,
+  0x1f,0xf9,0xdb,0x1f,0x84,0x00,0x33,0x00,0x50,0x12,0x62,0xa2,0xf4,0x4f,0x21,0xc4,
+  0x28,0x0c,0xe0,0x96,0xc5,0x21,0xd0,0xe8,0xef,0x90,0x7d,0x5e,0x1a,0x02,0xc5,0xf9,
+  0x3b,0x13,0x02,0x15,0xda,0x41,0xed,0x81,0x0a,0x19,0xae,0xf8,0xc3,0xa8,0x1c,0xb6,
+  0xec,0x3f,0x73,0xfe,0xd4,0x09,0x3c,0xe3,0xb4,0xdc,0x4f,0xcb,0x85,0xa4,0x65,0xa2,
+  0xd0,0xd7,0x59,0x1f,0xec,0xf5,0xdf,0xfd,0x5a,0xeb,0x7f,0x66,0xad,0xff,0xe7,0xce,
+  0x87,0x8a,0xaf,0x31,0x1d,0x80,0xb3,0xf7,0x63,0x86,0x87,0x03,0x06,0x43,0x14,0x64,
+  0x28,0xa6,0x86,0x42,0x46,0x10,0x80,0x69,0x18,0xeb,0x0f,0x5b,0xf3,0x87,0x8a,0xbe,
+  0x82,0x29,0xdc,0xa2,0x8a,0x1a,0x5b,0x8f,0x76,0xe2,0x16,0x5d,0x4a,0xb1,0x75,0xf0,
+  0x16,0x35,0x26,0x59,0xe3,0x11,0x35,0x32,0xb0,0xc5,0x9a,0x5f,0xf3,0x31,0x1c,0xc6,
+  0x4b,0xa2,0x91,0x2e,0x4f,0x33,0xbc,0x17,0x0b,0xea,0x42,0x17,0xda,0x0f,0x4f,0x61,
+  0x62,0x0c,0x22,0xfa,0xc8,0x30,0x32,0x9c,0x15,0xc5,0x13,0x45,0x3d,0xdc,0x01,0x10,
+  0x55,0xbf,0xec,0xe9,0x84,0x18,0x04,0x34,0x41,0xae,0x68,0x85,0x38,0x35,0x42,0x68,
+  0x04,0x9e,0x35,0x8d,0x43,0x8c,0xb5,0xbe,0xc6,0x1d,0x84,0xc3,0x10,0x8c,0x96,0xf6,
+  0xc6,0xbe,0x89,0x1e,0x85,0xe0,0x51,0xa1,0x17,0xfd,0x1e,0x9e,0x82,0xa0,0x26,0x0c,
+  0xa0,0x09,0xfa,0x88,0x18,0xde,0x0c,0x17,0xcd,0xce,0x5f,0x7d,0xd5,0x04,0x9c,0x87,
+  0xe6,0x0d,0xa2,0xcc,0x2e,0x14,0x53,0xbb,0x9a,0xef,0x28,0xe9,0x89,0x6f,0x80,0xd7,
+  0xa1,0x59,0x93,0x06,0xd8,0x09,0xf8,0xd2,0x34,0xd2,0x9c,0xb5,0x7e,0x92,0x39,0x02,
+  0x53,0xd0,0xb4,0xba,0x3c,0x73,0xed,0x08,0x4c,0xf1,0xf7,0xa9,0x25,0x1a,0x3b,0x40,
+  0x46,0x5a,0x34,0x29,0xc3,0x5e,0xb6,0x8c,0x71,0xb0,0xd6,0xd7,0xe4,0x83,0x74,0x91,
+  0xa8,0xf8,0x73,0x76,0x81,0x7a,0x02,0x35,0xab,0x52,0x62,0xcd,0x59,0x6b,0x59,0x7b,
+  0xfd,0x8b,0x9c,0x15,0xd9,0x93,0x45,0x01,0x63,0x93,0xfc,0x41,0xf6,0x9f,0xa0,0x3b,
+  0x19,0x8c,0xfc,0x43,0x05,0x7a,0x4d,0x3b,0x6c,0xed,0xff,0xbc,0x69,0x5c,0x20,0xd9,
+  0x6f,0xfe,0xa4,0xb8,0x36,0x1a,0x04,0x58,0xc4,0xdd,0x05,0x38,0xce,0x04,0x46,0x05,
+  0x40,0x47,0xad,0xb0,0xd8,0xf1,0x99,0x24,0x67,0xc5,0xfc,0xc9,0xc8,0xdf,0x83,0x17,
+  0xf0,0xe2,0xa8,0xff,0x9f,0xd1,0x77,0x61,0x5b,0xc7,0x62,0x5d,0x88,0xa0,0x77,0xe9,
+  0x88,0x2e,0x6c,0x45,0xa7,0xe0,0x71,0xd3,0xf8,0xca,0x5e,0x3f,0xc2,0xb7,0xc1,0x1f,
+  0xa1,0x49,0x2d,0x67,0x1e,0x82,0xd8,0x10,0x34,0x91,0xd5,0x58,0x8d,0x8e,0x68,0x52,
+  0x88,0x1d,0x31,0x8d,0xa5,0xec,0x28,0xb2,0x12,0x49,0xad,0xa6,0xf1,0x69,0x51,0xa5,
+  0x9b,0xd9,0x0c,0x59,0x86,0x44,0x23,0xcd,0x4e,0xaa,0xf9,0xf1,0x49,0x17,0x5b,0xf1,
+  0xe1,0x39,0x23,0x3e,0x29,0x31,0xc6,0xfa,0xb0,0x16,0xa9,0xd3,0x24,0xcc,0x7a,0x5d,
+  0xf1,0xff,0xd0,0xce,0x9f,0x54,0xcd,0x5e,0x78,0x01,0x02,0x61,0x3e,0xb4,0x5b,0x54,
+  0xee,0x67,0x6a,0x35,0x41,0x0d,0xcb,0xb0,0x0d,0x16,0x6b,0xc2,0x16,0xf4,0x3e,0x79,
+  0x64,0x18,0x17,0xec,0xcf,0x57,0x81,0xc7,0x0c,0xef,0xf8,0x4d,0x9e,0x0a,0x78,0x00,
+  0xd7,0xea,0x82,0x1e,0x5b,0x01,0xdb,0x2c,0x7f,0xb3,0x8e,0xeb,0x76,0x66,0x6f,0xe2,
+  0x7a,0x68,0xd0,0x46,0xfb,0x15,0x54,0x96,0x88,0x47,0xf4,0x31,0xa1,0x7e,0x7f,0x19,
+  0xce,0xcf,0xb7,0x51,0x3b,0x3f,0xc7,0xab,0xc7,0xe1,0x0b,0x68,0xc1,0x62,0x92,0xbd,
+  0xa1,0xf8,0x44,0xa4,0x0e,0x4b,0x3a,0x6a,0x44,0x27,0xa0,0x19,0x4b,0x49,0x96,0x3e,
+  0x32,0x8c,0x2f,0xec,0xfd,0x44,0x98,0x24,0x4c,0x42,0x33,0x48,0xbc,0x70,0x5a,0x9d,
+  0x54,0x89,0x81,0x59,0x5d,0x35,0x46,0x88,0x01,0x59,0x63,0x14,0xac,0xf5,0x79,0xb9,
+  0x0f,0x2e,0x91,0xf8,0x8b,0xcf,0x55,0x2e,0x0c,0xbf,0x0e,0x75,0xaa,0xb4,0xbb,0x64,
+  0x4c,0xbd,0x04,0x34,0x91,0xd8,0x31,0xc8,0x1a,0x43,0xf6,0x7e,0x30,0xb7,0x11,0x5e,
+  0x84,0x60,0x7b,0x57,0xc2,0x53,0x02,0x1d,0x09,0xaf,0x4a,0xf2,0xff,0x2c,0x26,0x23,
+  0xaa,0x90,0x40,0x63,0xe4,0x51,0x23,0x35,0x74,0xb0,0xaa,0x60,0x43,0x91,0x8f,0xce,
+  0x0f,0xfb,0xf7,0x78,0x7c,0xb0,0x1d,0xbc,0xe1,0xb5,0xe6,0x34,0x7b,0xbe,0x61,0xbc,
+  0x6a,0xe7,0x83,0x52,0xc5,0xc1,0x33,0x10,0x50,0x79,0x19,0xf9,0xc8,0x31,0x54,0x54,
+  0x41,0x46,0xc3,0xc6,0x48,0xd6,0xf0,0x53,0x63,0x88,0xb1,0xf2,0x61,0x6b,0x59,0xd4,
+  0x70,0x4a,0xc4,0x82,0x1f,0x52,0x50,0x47,0xbc,0x43,0xb6,0x9b,0xb6,0xf1,0x26,0x6b,
+  0xe5,0x67,0x6f,0x11,0x75,0xaa,0xa5,0x7d,0xc9,0x1e,0xf6,0x53,0x62,0xfc,0x4a,0x95,
+  0xda,0xd9,0xf7,0x2d,0x37,0x37,0x12,0xa3,0x91,0x1a,0xe7,0x8a,0xad,0x7c,0xa8,0x21,
+  0xf3,0xdf,0x81,0x55,0x43,0x62,0x26,0x5e,0xcf,0xbc,0x41,0x13,0x2f,0x5d,0x72,0x11,
+  0xf2,0xe3,0xf3,0xaa,0x5d,0x1f,0x1a,0x6a,0x74,0x18,0x84,0xa0,0x1c,0xe9,0x44,0xb5,
+  0x6a,0x17,0x17,0x04,0x81,0xee,0x87,0x8c,0x4c,0x33,0xde,0xe4,0xac,0xf8,0x44,0xa0,
+  0x93,0x38,0x15,0x54,0xf9,0x10,0xf1,0xb7,0x03,0x7c,0xea,0x5a,0xc3,0x4d,0x26,0xa0,
+  0xb2,0x0e,0xc7,0x73,0x9f,0x57,0x2f,0xd7,0x07,0x2f,0x32,0xc1,0x28,0xbf,0x47,0x09,
+  0x90,0x78,0x92,0xe8,0x3d,0x5c,0x28,0x9e,0x76,0x3e,0x24,0xab,0xc7,0xc4,0x77,0xb8,
+  0xa6,0x4d,0x81,0x44,0x69,0xb1,0x77,0xbb,0xde,0xac,0xae,0x4b,0xa0,0xb3,0xf0,0xef,
+  0x79,0xfb,0x1f,0xb7,0xeb,0x4f,0x8a,0xe9,0x83,0x1b,0xe8,0xe0,0x23,0xc2,0x39,0xf5,
+  0x52,0xc2,0x78,0xfa,0x7b,0x97,0xbf,0x5f,0xd8,0xf5,0x87,0x97,0x8d,0x7c,0x93,0x45,
+  0xb4,0xa6,0x16,0xa5,0xd4,0xe6,0x52,0xa9,0x93,0x3d,0xed,0x8a,0xff,0x09,0xbb,0xfe,
+  0xf8,0x8b,0xfc,0xf0,0x12,0x2c,0xe9,0xe7,0x75,0xf4,0x2d,0xfc,0xe0,0xea,0x25,0x0f,
+  0x09,0xfb,0xd1,0x97,0xa1,0x97,0x20,0x88,0xe7,0x26,0xd1,0x38,0x50,0x43,0x48,0x92,
+  0xfc,0xb6,0xf2,0xc1,0x6f,0xd6,0x9f,0x49,0x8f,0x0f,0x49,0x4a,0xbc,0x8b,0x9c,0x8e,
+  0x06,0xf4,0x86,0xef,0x59,0x66,0xfa,0x79,0x39,0x61,0xd7,0x1f,0x2c,0xdf,0x6a,0x1c,
+  0x52,0xcf,0x16,0x6f,0x0f,0x6c,0x53,0x17,0x63,0xd6,0x71,0x6c,0x6d,0x63,0xdc,0x5e,
+  0xbf,0xab,0xeb,0x94,0xfc,0x39,0x5e,0xa5,0x07,0x1b,0x84,0x39,0xf0,0x1a,0x31,0xa4,
+  0xf5,0xe4,0x74,0xd0,0x11,0x61,0x2b,0x7b,0xca,0x30,0xa4,0xad,0xec,0x87,0x76,0xfd,
+  0xe1,0xab,0x8d,0x7a,0xa2,0x95,0x0d,0x54,0x6e,0xa4,0x06,0x76,0x96,0x11,0xdb,0x18,
+  0xb2,0xeb,0x0f,0x14,0xfd,0x92,0x36,0xa9,0x64,0xf9,0x49,0x76,0xbe,0xfc,0x5a,0x82,
+  0x11,0xdb,0xde,0x59,0xf3,0x99,0x3a,0x95,0x98,0xde,0xbf,0x34,0xbb,0xfe,0xf4,0xd7,
+  0xec,0x55,0xc9,0x26,0x3b,0xcb,0x6e,0x66,0x6f,0xc5,0xdb,0xa0,0x76,0x8f,0xa7,0x1d,
+  0xbd,0x9d,0xbf,0x7f,0xf6,0x49,0xfb,0xf3,0x05,0xbc,0xd7,0xf4,0x57,0x46,0xff,0xe8,
+  0x7b,0x90,0xaf,0x6d,0x2d,0x6d,0x7f,0xf5,0x6d,0xee,0x05,0xf8,0xd7,0x69,0xfe,0x6a,
+  0x76,0xfd,0x51,0xcc,0xfa,0x93,0xb9,0x49,0x42,0x6d,0xc5,0x31,0x55,0xc1,0xc2,0x7c,
+  0x78,0x55,0xcd,0xaf,0xe7,0x5d,0xf6,0x79,0xef,0xaf,0x9e,0xe0,0x89,0x53,0x99,0xf2,
+  0xe7,0xd8,0xdb,0xe1,0x75,0xed,0x10,0x33,0xef,0x08,0xf9,0x58,0xbf,0x84,0x7b,0xa7,
+  0xd7,0x4f,0x7b,0x3f,0x98,0x31,0xe2,0xd3,0xb6,0xae,0xaa,0x92,0x3c,0x8d,0x34,0x43,
+  0xf9,0x00,0xc9,0x87,0xfc,0xf8,0xe4,0xea,0x61,0xad,0x6c,0xf4,0x3b,0x4d,0xcc,0xb0,
+  0x7f,0x87,0xdf,0xc0,0x12,0xf4,0xa4,0x49,0x37,0xcf,0xaf,0xe7,0x5a,0xab,0xb5,0x9f,
+  0x7d,0xdc,0x66,0xf8,0x29,0x04,0xb7,0xf6,0x1f,0x79,0xe9,0x71,0xe8,0xd7,0x03,0x0a,
+  0x3f,0x80,0x7e,0x07,0x87,0xa7,0xf7,0x5f,0xa4,0xdb,0xf5,0x01,0x93,0x7e,0x47,0xba,
+  0xb3,0xce,0xef,0x42,0x3e,0xb9,0x5b,0x09,0x2a,0xa5,0x89,0x8a,0x33,0x8a,0x6b,0xbe,
+  0x9d,0x0f,0x7c,0x95,0x68,0x04,0x81,0x07,0xd4,0x03,0xfb,0xc8,0x69,0x2d,0x95,0x49,
+  0xf4,0xf2,0xe3,0x93,0xab,0x3f,0x50,0xb6,0x99,0xf6,0x77,0x4d,0xc4,0x95,0x3e,0x44,
+  0xda,0x0a,0x94,0x25,0x8c,0xf8,0x64,0xfd,0x3d,0x6c,0x1a,0x9a,0x5d,0x7f,0xf6,0x15,
+  0x5d,0x86,0xdf,0x12,0xa7,0x96,0x68,0xc4,0xbb,0xcb,0xd0,0x02,0x4f,0x17,0xf2,0xf7,
+  0x03,0xbb,0xfe,0x68,0x45,0xd9,0x24,0xd1,0x2b,0x9b,0xe1,0x32,0x5e,0x59,0xdb,0x93,
+  0x62,0x2f,0xc0,0x6f,0x67,0xe4,0x1f,0x2c,0x53,0xc8,0x69,0x4c,0x76,0x77,0xb1,0x01,
+  0xf8,0x00,0x7b,0xc1,0xd3,0x85,0xf4,0x64,0x77,0x1e,0xff,0xe8,0xb9,0xfa,0x5f,0xd4,
+  0x96,0x75,0xaa,0xb8,0x8d,0x56,0x27,0x95,0x38,0x3e,0xec,0xea,0x47,0x43,0x39,0xfe,
+  0xa9,0xa6,0xfc,0xb3,0x08,0x93,0xa0,0x05,0xe0,0x09,0x6d,0xd1,0x06,0x4f,0x4f,0xc5,
+  0x39,0xa5,0x3b,0x2f,0x9e,0x39,0xfe,0x81,0xaa,0x00,0x8d,0x46,0x72,0xe7,0x13,0xc2,
+  0x66,0xc8,0x68,0x4d,0x21,0xbe,0x8b,0xfd,0x9d,0xab,0xff,0x6a,0x76,0xfd,0x39,0x0d,
+  0x46,0x7f,0xdf,0x25,0xe9,0xec,0x11,0xf8,0x13,0xac,0x04,0x49,0xab,0x74,0xc7,0x67,
+  0xd2,0xc9,0x3f,0xf2,0x7b,0xd0,0x3c,0x22,0xfa,0x0e,0x4c,0xa0,0x14,0x5e,0xa1,0x92,
+  0xfa,0x73,0x16,0xd6,0x9a,0xcb,0x6e,0xb6,0xd6,0xcf,0xd8,0xf5,0x27,0xd5,0x6a,0xf0,
+  0x4f,0x82,0x1f,0x24,0xbb,0x25,0xfd,0x48,0x2d,0xc7,0x68,0x8c,0x99,0xb6,0xff,0x72,
+  0x27,0xff,0x9c,0x31,0xe3,0x93,0xf6,0x28,0xe1,0x11,0x02,0xa8,0x3e,0x20,0xf5,0x59,
+  0x97,0x69,0x7c,0x3c,0x05,0xf9,0x67,0x03,0x33,0x9f,0x36,0xfd,0xa4,0x27,0x52,0x7c,
+  0x4a,0x2e,0xc2,0xb5,0x8a,0xb0,0x9e,0xf0,0xcf,0x34,0x1e,0xf0,0x6c,0x45,0x27,0x1d,
+  0xfc,0x43,0xf3,0xad,0x29,0x5d,0xce,0x6d,0x9b,0x80,0x30,0x54,0x69,0x52,0x05,0x29,
+  0xb3,0x71,0x72,0x22,0xca,0x43,0x6c,0x9b,0x05,0x42,0xa3,0x76,0xba,0xa9,0xf3,0x68,
+  0x7c,0x56,0xa5,0x17,0xff,0x9a,0x44,0xe3,0x22,0x01,0x83,0x72,0x92,0x3f,0xea,0x94,
+  0x3c,0x13,0xff,0xf4,0x17,0x19,0x41,0x96,0x49,0x58,0x48,0xfc,0xa1,0x99,0x21,0xd1,
+  0x38,0x33,0x1b,0xff,0x5c,0x65,0xd4,0x13,0x2c,0x00,0x7b,0x2b,0xf7,0x3c,0xda,0x07,
+  0x82,0x4a,0x76,0xfb,0xf8,0x8c,0xfc,0xa3,0x99,0xfc,0xb3,0x81,0x60,0xde,0x7c,0xf8,
+  0x85,0xb6,0xf8,0xb6,0xb9,0x5b,0xd1,0x67,0x2e,0xfe,0xc9,0xd8,0xe7,0x3d,0x52,0x65,
+  0x04,0x2d,0xd3,0x7d,0x0d,0x6a,0xe3,0x9f,0x55,0x95,0xb4,0x50,0x1f,0x7b,0x13,0x0e,
+  0xcc,0xc2,0x3f,0xfd,0x14,0x72,0x12,0xd2,0x41,0xd6,0xcf,0x7f,0x06,0xf7,0xc5,0x05,
+  0x1d,0x5d,0x52,0xf2,0xf8,0x07,0x39,0xf8,0x07,0x8c,0xa6,0x23,0xb3,0x45,0xb4,0xfb,
+  0xdc,0x64,0xb6,0xa1,0xce,0xd9,0xf8,0xc7,0x68,0x6a,0x43,0x65,0x03,0x71,0x1f,0x73,
+  0x09,0xd7,0x85,0xa5,0xc4,0xed,0xb4,0x8d,0xce,0xcc,0x3f,0x46,0x93,0x6d,0x17,0xf6,
+  0xee,0xf0,0x95,0xbe,0xb8,0x9e,0xf0,0x4f,0xc2,0x6b,0xb6,0x5d,0xc9,0xd1,0x7f,0x73,
+  0xfc,0x53,0x93,0xe5,0x1f,0x61,0x37,0xda,0x28,0xbf,0x08,0xfb,0x57,0xcf,0x4d,0xa0,
+  0x3e,0x63,0xda,0xdc,0x82,0xfc,0xc3,0x03,0x97,0x6d,0xfa,0x75,0x45,0xc4,0x50,0xda,
+  0xe7,0xca,0xe8,0x18,0x47,0x47,0x3c,0x0e,0x1e,0xc8,0xd5,0x9f,0x41,0x3e,0x6a,0x39,
+  0x15,0x85,0x41,0xa6,0x02,0x76,0x62,0xd6,0x24,0x40,0xc1,0xe1,0xef,0xc7,0xac,0xb5,
+  0x9f,0xde,0x79,0x59,0xa7,0xf6,0x10,0xef,0xfe,0x44,0x78,0x66,0x67,0xfa,0x6f,0xde,
+  0xaf,0xc9,0xef,0xef,0xe7,0x4a,0xac,0x78,0xf6,0x56,0x1b,0xbc,0xa4,0x8a,0xe9,0x6d,
+  0x63,0xf0,0x29,0x1c,0x6a,0xaf,0x19,0x60,0x17,0xb8,0x78,0xe0,0x9c,0x9d,0x3f,0x0d,
+  0x72,0x94,0xa3,0x90,0xe3,0xef,0x44,0x7a,0x62,0x12,0xbc,0x50,0x86,0x11,0x2e,0xc0,
+  0x3f,0xb9,0xb7,0xd8,0x56,0xe2,0x9d,0xa8,0xf2,0x35,0x68,0x58,0x79,0x86,0xe9,0x57,
+  0xf9,0x04,0xe2,0x18,0x07,0xef,0x65,0xfd,0xcd,0xf1,0x98,0x11,0x3d,0x0d,0x76,0x91,
+  0xe8,0x3d,0xc1,0xfb,0xd5,0xed,0x89,0x70,0x9f,0xea,0x8a,0x67,0x8e,0x7f,0x38,0xca,
+  0xb7,0xcd,0x61,0x6e,0x2f,0x79,0xfa,0x4c,0xc5,0xbf,0xac,0xe7,0xe7,0xd8,0xfb,0x5f,
+  0x53,0x80,0x7f,0xfa,0xc1,0x98,0xbf,0x3a,0xeb,0xdd,0xdd,0x11,0xe9,0x51,0xe2,0x5d,
+  0xbe,0xbf,0x1f,0xda,0xf5,0xc7,0x0f,0x26,0xff,0x48,0x78,0x8d,0x22,0xa6,0xda,0x56,
+  0x80,0xd4,0xb9,0x46,0x87,0x14,0x9a,0x91,0x7f,0x38,0xca,0x3f,0x8b,0x7b,0x05,0x7d,
+  0x87,0xbf,0xf8,0xc1,0xa3,0x5e,0x4a,0x3b,0xe3,0xf0,0x2e,0x49,0x63,0x21,0xc7,0x3f,
+  0xec,0x8e,0x1c,0xff,0xfc,0x97,0x51,0x7f,0x06,0x05,0x2f,0x12,0x21,0xae,0xb6,0x1e,
+  0xa5,0xc7,0x84,0xbc,0x2b,0x05,0xb4,0x52,0x67,0x7d,0xb6,0xeb,0x4f,0x2d,0x73,0x8d,
+  0x79,0x7e,0x37,0xa1,0xf9,0x91,0x6d,0x7c,0x6d,0x6a,0xee,0x16,0x74,0xaa,0xe3,0x27,
+  0x70,0xdd,0xb4,0xf3,0x9b,0xcc,0xad,0xcf,0xcf,0x97,0x3f,0xef,0x58,0xb5,0x4f,0xf0,
+  0x7b,0x9b,0xf1,0x8d,0x78,0xf9,0x05,0x89,0x62,0xcf,0x6f,0xc8,0xb1,0x95,0x4c,0xfe,
+  0x99,0x97,0xc7,0x3f,0x65,0x26,0xff,0x90,0xd3,0x37,0x41,0x4e,0xdf,0x2f,0x53,0xd2,
+  0xc0,0x9a,0x8f,0xe4,0x99,0xf9,0x47,0x35,0xfb,0x57,0xb2,0x2c,0xc5,0xde,0x03,0xaf,
+  0xe2,0x65,0xfa,0xba,0x49,0x76,0x4a,0x99,0x72,0xf6,0xaf,0x75,0x93,0x95,0xe9,0x1c,
+  0xff,0x5c,0x65,0xf0,0x0f,0xe6,0x55,0xd4,0xa4,0xfe,0xaf,0x72,0xdd,0x90,0x44,0xb6,
+  0xad,0xe6,0xf3,0x5b,0x8e,0x37,0x12,0x60,0xd4,0xab,0x4e,0x7e,0x0b,0xba,0x06,0x1e,
+  0xe6,0x6e,0x33,0xa6,0x29,0xf9,0xf3,0x87,0xed,0xfa,0x13,0xad,0x1a,0xe1,0x49,0xd0,
+  0x74,0x1e,0x76,0x04,0x60,0xb7,0xb8,0x28,0x13,0x5b,0x8e,0xde,0x72,0xf5,0xf7,0x93,
+  0x76,0x7e,0xfa,0x0d,0xde,0x6b,0x92,0xc5,0x27,0xd9,0x26,0xc2,0x3f,0x3f,0xba,0x28,
+  0xbc,0xcc,0x4e,0xa9,0xf9,0xfe,0x9e,0x70,0xec,0xc7,0x18,0xdc,0xf3,0xa0,0xc2,0x1e,
+  0x64,0xbe,0xc4,0xd3,0xa7,0xd9,0xc6,0x98,0x5d,0x1f,0x76,0xc9,0x97,0x19,0x52,0xb4,
+  0xef,0x12,0xf5,0xca,0x26,0xfe,0x14,0xb3,0x4c,0xbb,0x26,0x53,0x69,0x96,0xf1,0x32,
+  0x47,0x3d,0xd7,0xed,0xfd,0x1c,0xed,0xdc,0x4c,0x9b,0x54,0x9a,0xef,0x47,0x07,0x8b,
+  0x63,0x8c,0x97,0x74,0x2b,0x30,0xdb,0x96,0xe4,0x78,0x7f,0x3f,0xad,0x5a,0xeb,0x13,
+  0xfe,0x91,0xc9,0x53,0xcc,0xf7,0x17,0x07,0x60,0x87,0xe2,0x3d,0xca,0x0f,0x78,0x27,
+  0xdc,0xbc,0x94,0xab,0x3f,0x1c,0xed,0x47,0x41,0x1c,0x81,0xf2,0x1e,0x88,0x81,0xa2,
+  0xad,0x0d,0x15,0x9b,0x61,0x31,0xfa,0xdd,0x81,0x7c,0xfe,0xc1,0x22,0xed,0xa7,0xcd,
+  0x58,0x1c,0x20,0xbc,0xb1,0x83,0x59,0x76,0xf4,0xe4,0x00,0xd9,0x3f,0x75,0x53,0x70,
+  0xf8,0x3b,0x6e,0xd7,0x9f,0xe4,0xbc,0xcb,0x32,0xe9,0x5f,0x5a,0x99,0x4a,0xbc,0x9b,
+  0x80,0x5f,0x69,0xdf,0x73,0xb8,0x79,0x19,0x3e,0xc9,0xfa,0xcb,0x5a,0xf1,0xd4,0xb2,
+  0xfc,0x2c,0x9d,0x61,0xeb,0x60,0x18,0xaf,0xc4,0xa2,0x86,0x1a,0xe1,0x93,0x19,0xf9,
+  0x47,0x33,0xf8,0x27,0x98,0x14,0x0e,0x22,0x45,0xee,0xc2,0xde,0x24,0xdf,0x8b,0x9e,
+  0x86,0x7c,0xfe,0xc9,0xe9,0x3f,0x29,0x6e,0x84,0x7b,0x16,0x44,0x10,0xfa,0xc2,0x1b,
+  0xa1,0x0b,0x6d,0xec,0x28,0x0d,0x55,0xf0,0xae,0x7e,0x74,0x21,0x8f,0x7f,0x8c,0x97,
+  0x94,0x3b,0xe9,0xfa,0x89,0xeb,0xe8,0xfa,0x4f,0xcd,0xc8,0x3f,0x6a,0xb5,0x11,0x84,
+  0xb0,0x74,0x2d,0x0a,0xc7,0xb4,0xd4,0x8a,0x8e,0xb2,0x9e,0xf8,0xb5,0xca,0xf9,0x2b,
+  0xe8,0x3f,0x2d,0x37,0x4a,0xe3,0x95,0x83,0x84,0x0f,0xef,0xd1,0xca,0x35,0xf6,0xa2,
+  0x41,0x8c,0xce,0xfe,0x3e,0xe1,0xd2,0x7f,0x48,0x91,0xe9,0x83,0x94,0x6c,0x7c,0x10,
+  0x63,0xf8,0x8a,0xfa,0xcf,0x6d,0x42,0x27,0xe1,0xb7,0x6e,0xec,0x1d,0x27,0x85,0xf7,
+  0x98,0x2b,0x1f,0x72,0xfc,0x33,0x6e,0xf1,0xe1,0xf5,0x28,0x06,0xb1,0xa4,0xff,0x03,
+  0xbe,0xd4,0x3b,0xab,0xfe,0x93,0xe5,0x1f,0x61,0x3c,0xdc,0x08,0x0f,0x24,0xf6,0x25,
+  0xf9,0x4d,0xde,0xd1,0x9c,0xfe,0x93,0x35,0x2e,0x4f,0xe3,0x1f,0x02,0x39,0x20,0xc9,
+  0x6c,0xa7,0x77,0x48,0x6e,0xd0,0x02,0x4a,0xbe,0xfe,0x53,0x12,0x72,0xea,0x3f,0x06,
+  0xff,0xb4,0x80,0xd4,0x5e,0x79,0x12,0xbe,0x92,0xbf,0xd5,0x29,0xfd,0xa1,0x00,0x3f,
+  0xbb,0xf8,0x27,0x42,0x82,0xa0,0xc0,0x93,0x50,0xa7,0xf5,0x60,0xd2,0x94,0xf2,0xe2,
+  0xbf,0xc6,0xc5,0x3f,0x43,0xc2,0x16,0x4f,0x0d,0x3c,0x00,0xfb,0x34,0x3e,0x8a,0x12,
+  0x6e,0xfd,0xc7,0x8e,0x3f,0x36,0xf9,0x27,0x2a,0xac,0x8f,0xcd,0xe1,0x7f,0x8e,0x95,
+  0x8f,0x78,0x3f,0xba,0x5b,0x7e,0x3c,0x5f,0xff,0xb1,0xe3,0x9f,0xe5,0x9f,0xbf,0x16,
+  0xe4,0x0a,0x0f,0xc4,0x38,0x25,0xed,0xaf,0x8f,0x1d,0x53,0x66,0xd3,0x7f,0xfa,0x4d,
+  0xc8,0x89,0xb2,0x8d,0xf2,0xc7,0x5b,0xea,0x70,0x60,0x4c,0xf8,0x4f,0xfc,0xe1,0xcc,
+  0xfa,0x0f,0xd8,0x4d,0xe7,0x74,0x78,0x52,0x6d,0xae,0x20,0xc6,0x3e,0xee,0x8a,0xfc,
+  0xa3,0x49,0x7b,0xe3,0x0b,0xe1,0x78,0xc7,0x40,0xab,0xf8,0x0d,0x02,0xb9,0x57,0xd4,
+  0x7f,0x56,0x0b,0xbd,0xe1,0x05,0xd0,0xa1,0x79,0x27,0x3d,0x89,0x8a,0x6f,0x1a,0xfa,
+  0x4f,0xf9,0x6c,0xfc,0x43,0x06,0x3d,0x9c,0xba,0xbd,0xd6,0x4b,0xfa,0xbb,0xa7,0x0f,
+  0xe7,0xe9,0x15,0x15,0x0e,0xfe,0xe1,0x0c,0xfe,0x89,0x0a,0x35,0xa8,0x08,0x3a,0x40,
+  0x21,0xd8,0x53,0xde,0x09,0x33,0xf3,0x4f,0x43,0x99,0xcd,0x3f,0xa4,0xa4,0x33,0x75,
+  0x54,0x08,0x4a,0x4e,0xd7,0x1f,0x4a,0x30,0xfb,0x26,0x63,0xeb,0x3f,0xf3,0xb2,0xfe,
+  0xde,0xc2,0x5e,0x44,0xcf,0x43,0x73,0xbb,0xf4,0xb6,0x70,0x8b,0xe1,0x66,0xb9,0x93,
+  0x67,0xb8,0x1c,0x6f,0x18,0xfc,0xa3,0x49,0xe9,0xb8,0x0f,0x8e,0x41,0x5d,0x44,0x4c,
+  0xb3,0xf5,0x6e,0xfd,0xc7,0xc1,0x3f,0x59,0xc8,0x49,0x22,0x1e,0x4e,0x92,0x54,0xe3,
+  0xef,0x27,0xdd,0x76,0x66,0xfe,0x89,0x14,0xd9,0x4e,0xb5,0xd6,0x6e,0x47,0x4a,0xbb,
+  0x47,0x0e,0x73,0x90,0xcf,0x3f,0xa3,0x39,0xfe,0xa9,0xee,0xb3,0x82,0xdc,0xba,0xfa,
+  0xa7,0xb2,0x57,0xf5,0x3c,0x8c,0xfe,0x7b,0x76,0xfd,0x87,0x6e,0xf2,0x87,0x52,0x42,
+  0xf8,0x01,0x3a,0x7e,0xa6,0x4e,0x5d,0x94,0x60,0x1d,0x9f,0xef,0x8b,0xf9,0xfc,0x33,
+  0xce,0xf4,0x71,0x97,0xe8,0x79,0xf9,0x06,0x7b,0x10,0x2e,0xc5,0x8e,0xa8,0x65,0x35,
+  0x39,0x37,0x0b,0xe8,0x3f,0x7e,0xd9,0xe2,0x9f,0x78,0x2d,0x9c,0xe4,0xe7,0x90,0xf8,
+  0xb3,0x8a,0x72,0x45,0xfd,0x67,0x0f,0xc1,0xf8,0x45,0xe4,0x7c,0x79,0x71,0x38,0x59,
+  0xb9,0xd5,0x92,0x7d,0x0a,0xe9,0x3f,0xd9,0xf7,0x2f,0x81,0x41,0x25,0xc3,0x0f,0x81,
+  0x6f,0x12,0x42,0xc5,0xa5,0xae,0xfa,0x93,0xd3,0x7f,0x92,0x26,0xff,0xa8,0x64,0xf0,
+  0x1a,0xe6,0x27,0xbc,0x82,0x3c,0xa1,0xe2,0x5b,0x99,0x99,0xf5,0x9f,0x7e,0x7e,0x3e,
+  0x81,0x1c,0x42,0x3b,0x11,0x61,0x0e,0xfc,0x1a,0x2f,0xf7,0x8a,0xeb,0xd9,0x0a,0x4b,
+  0xf6,0x29,0xa4,0xff,0xcc,0x33,0xea,0xad,0x4a,0xaa,0xc7,0xd9,0xe2,0xa7,0x4c,0x63,
+  0x0c,0xde,0x9b,0x45,0xff,0xa1,0x4d,0x6a,0x55,0x5f,0xf9,0xf8,0x9a,0x6f,0xc1,0xb1,
+  0x7d,0xcb,0xa2,0x81,0x49,0xb6,0x19,0xa6,0xf2,0xfa,0x97,0xe6,0xe4,0x1f,0xba,0xc9,
+  0x39,0xfc,0x86,0xf0,0x55,0xf8,0x7e,0xe5,0x3a,0xd5,0x00,0x9b,0x99,0xf9,0x07,0x4c,
+  0xfe,0x39,0xfa,0x5d,0x0d,0xd5,0x54,0xdd,0xdf,0x74,0x1b,0xe6,0x6f,0x41,0x55,0xae,
+  0xf9,0x0e,0xfd,0xc7,0xac,0x3f,0x54,0x6f,0xf4,0x40,0x07,0xf6,0x03,0xdf,0x40,0x0e,
+  0x5a,0x7e,0x3c,0x53,0x0e,0xfd,0xc7,0xec,0x2f,0xe4,0x74,0x5f,0xef,0x3d,0x9e,0xa8,
+  0x6b,0x0f,0x0c,0x74,0xd7,0xba,0x78,0xe6,0x7c,0x4e,0xff,0x31,0xf9,0x07,0x49,0x49,
+  0xe1,0x03,0xb8,0xa4,0x12,0x83,0xa6,0x8d,0x5b,0xff,0xb1,0xd6,0x67,0xe4,0xcb,0xa6,
+  0x9e,0xaf,0xb1,0x17,0x94,0x11,0xa6,0x1e,0x44,0x99,0x0d,0x29,0x33,0xeb,0x3f,0x18,
+  0x0c,0xfe,0x89,0xde,0xd4,0xf7,0x4a,0x12,0x25,0x87,0xbc,0xbc,0x3f,0x81,0x16,0x16,
+  0xe0,0x19,0x07,0xff,0x30,0x74,0x3e,0x19,0x4c,0xe1,0xed,0x38,0x78,0x13,0xff,0x4c,
+  0x85,0xb7,0xf6,0x4a,0xfc,0x13,0x80,0x52,0x85,0x04,0xad,0x1f,0xfc,0x54,0x88,0xe6,
+  0xae,0xa0,0xff,0x18,0xf9,0x80,0x49,0xb7,0x4a,0x31,0xcd,0x10,0xa0,0xe7,0x2b,0xdf,
+  0xdf,0x9c,0xfe,0x43,0xf8,0xc7,0xf0,0xb7,0x2c,0xca,0x1e,0x21,0xfd,0xfd,0x05,0x58,
+  0x92,0x26,0xfd,0xdd,0x75,0xbf,0x83,0x6c,0xde,0xb8,0xea,0x2b,0x94,0xbd,0xed,0xda,
+  0x0d,0x13,0x78,0x99,0xd2,0x33,0xc2,0x36,0xe1,0x4f,0xf0,0xaa,0x94,0x78,0x31,0x97,
+  0x48,0x19,0xbb,0x3e,0x60,0xf8,0xd8,0xa2,0x9d,0x0d,0xd0,0x85,0x57,0x28,0x04,0xdb,
+  0x5a,0x54,0x32,0x92,0x21,0x85,0x28,0x68,0xeb,0x3f,0xf6,0x79,0xe4,0x8b,0x46,0x20,
+  0x0e,0x7e,0xea,0x14,0x86,0x43,0xb0,0x08,0x78,0x44,0x5e,0x34,0x08,0xff,0xa4,0xf9,
+  0x43,0x48,0xcc,0xf9,0x6b,0xc5,0x9f,0xf2,0x4f,0x56,0x2d,0xd9,0xc0,0x3f,0x8a,0xef,
+  0xf4,0xee,0x48,0x90,0x68,0xd1,0x11,0xff,0x2e,0x14,0x28,0xc0,0x3f,0xa4,0xff,0x66,
+  0xd5,0x86,0x03,0x90,0xc1,0x0d,0xb5,0xe2,0xcf,0x4a,0x03,0x70,0x1e,0xdd,0xa3,0x89,
+  0x8f,0x0a,0x01,0x37,0xff,0xe8,0x26,0xff,0xd0,0x20,0x64,0x48,0x2a,0xad,0x84,0x5c,
+  0x58,0x26,0x0b,0xea,0x3f,0x70,0xd0,0x3a,0x7d,0xfb,0xd4,0x13,0x77,0xd5,0x55,0x49,
+  0x7d,0xac,0xb9,0xac,0x98,0x10,0x82,0xd6,0x3f,0xed,0xd0,0x7f,0x8a,0x44,0x35,0xbb,
+  0x49,0x0d,0x76,0x84,0xe7,0x28,0x6b,0x07,0xd0,0xcf,0xf0,0x61,0x58,0x32,0x5a,0x13,
+  0xf2,0x04,0x2c,0xd7,0x72,0xfc,0xa3,0x17,0x7d,0xc7,0x0a,0x42,0x4c,0xc1,0x9a,0x2f,
+  0xba,0x36,0x89,0xa4,0xc0,0x43,0x4c,0x60,0x92,0x24,0x86,0x88,0xe2,0xf9,0xfc,0x13,
+  0x35,0xf9,0x87,0x36,0xfd,0x51,0xb5,0x13,0x2f,0x20,0x86,0xd7,0xbc,0x21,0xf2,0xff,
+  0x3d,0x7a,0xcc,0x12,0x46,0x1c,0xfa,0x0f,0x88,0x16,0xed,0x60,0xd0,0xd4,0xfa,0x56,
+  0xa9,0x9e,0x35,0x47,0xf8,0x5d,0x82,0x08,0xaf,0x64,0xf5,0x9f,0x69,0xfc,0x73,0x5f,
+  0x36,0x3e,0x1e,0xaa,0xff,0xec,0xb4,0xe3,0xf3,0x3f,0xec,0xad,0x33,0xf2,0x8f,0x01,
+  0xe1,0x48,0x67,0x56,0xa8,0x3b,0x07,0xd8,0x8f,0x92,0xaf,0x13,0x02,0x37,0x88,0x7d,
+  0x26,0xfd,0x87,0x16,0x8d,0x93,0x70,0x3f,0xaa,0x55,0x89,0xf1,0x7f,0x98,0xf0,0x8f,
+  0xee,0x2c,0x44,0x2e,0xfd,0xc7,0xa4,0x9d,0xa7,0xf1,0x82,0x28,0x31,0xde,0x34,0xdc,
+  0x24,0x85,0xc5,0x0e,0x85,0x4b,0xff,0x31,0x8a,0xb6,0x12,0x8b,0x24,0xff,0x20,0xac,
+  0x40,0x23,0x46,0x18,0xf9,0x7a,0x8f,0x38,0x0b,0xff,0x24,0xd9,0x4b,0xf8,0x5c,0x74,
+  0xe5,0x11,0xe9,0x1c,0xc1,0x9e,0x13,0xd0,0x84,0xc5,0x71,0xc1,0x5f,0x88,0x7f,0xf2,
+  0x6e,0x1f,0x76,0x62,0xf6,0xa8,0xd1,0xa1,0x96,0x74,0xc4,0x67,0xe6,0x1f,0xda,0xd4,
+  0xce,0xc2,0xf1,0x64,0x5d,0x54,0x4a,0x20,0x1f,0x7c,0x00,0xcd,0xad,0x62,0x15,0xbb,
+  0x10,0xcf,0xc4,0x3f,0xb4,0xc9,0x0e,0x2b,0x4f,0x84,0x57,0xb4,0x0a,0xb4,0xfe,0x6c,
+  0x27,0x15,0x86,0x4f,0x78,0x17,0xce,0xc6,0x3f,0x59,0xbd,0x91,0x74,0xf3,0x3e,0xfc,
+  0x04,0x15,0x5a,0xe9,0x3f,0xe4,0xd6,0x7f,0xb8,0x5c,0xf7,0x17,0x0f,0x80,0x4f,0x15,
+  0xaa,0x2a,0x44,0x02,0x42,0xa4,0x62,0x57,0x79,0xb8,0x42,0xfc,0xb3,0x29,0xe7,0xaf,
+  0x79,0xff,0x45,0xf8,0x67,0x9c,0x84,0x25,0x40,0x1a,0x71,0x81,0xfb,0xaf,0xbf,0xb0,
+  0xfd,0x7d,0xdb,0xd0,0x7f,0xa4,0x34,0x71,0xfc,0x92,0x01,0x42,0x0e,0xfe,0x71,0xdc,
+  0x7f,0x5d,0x84,0x77,0xac,0xf9,0x6f,0xc0,0xd5,0x86,0x81,0x8f,0x43,0x4b,0x54,0x7a,
+  0x9f,0xad,0x47,0xc7,0x0b,0xf0,0x0f,0xd7,0x65,0x42,0xce,0xb8,0xc1,0x3f,0x42,0x0c,
+  0xe9,0xc8,0x18,0xe1,0x91,0x02,0x5d,0xf9,0xfc,0xc3,0x13,0xfe,0xd9,0x65,0xd1,0xce,
+  0x76,0xc6,0xa7,0xce,0x95,0x63,0xc7,0xa8,0xbf,0xed,0x42,0x15,0x29,0xbc,0x1d,0x2e,
+  0xfd,0x87,0xf0,0xcf,0x76,0x8b,0x76,0x1e,0x01,0xef,0x8d,0xc2,0xc3,0x46,0x60,0x83,
+  0x74,0x9a,0xcf,0x7a,0xe4,0xe4,0x9f,0x61,0x6b,0xff,0xc7,0xe0,0x68,0x64,0x85,0x89,
+  0x31,0xc6,0xb6,0x1f,0x16,0x7c,0x70,0xdc,0xa5,0xff,0x30,0x7d,0x0e,0xda,0xe9,0xa5,
+  0xf7,0x65,0xec,0x70,0x76,0x44,0x28,0xa4,0xff,0xc8,0x36,0x6d,0x9e,0x96,0x53,0xd0,
+  0x08,0x7f,0x49,0xef,0x97,0x53,0xc6,0x8d,0x64,0x2e,0xfe,0x4e,0xfe,0x69,0x50,0xb2,
+  0x90,0x33,0xc9,0x3d,0xa8,0x53,0xfd,0xc7,0xd3,0x80,0x76,0xc0,0x92,0x1e,0x0f,0x25,
+  0xc6,0x0f,0xdd,0xfc,0xf3,0x57,0x4a,0xf6,0x50,0xbc,0x11,0x8d,0x0f,0x19,0x85,0x5a,
+  0xa4,0xdf,0x4f,0xd0,0xc9,0x5f,0x13,0x67,0xe4,0x1f,0x7a,0x48,0xd3,0x68,0x27,0x57,
+  0xab,0x91,0xd3,0x57,0x45,0xde,0x5f,0xc8,0xfc,0x1f,0xa3,0x79,0x96,0x90,0x9b,0xcf,
+  0x3f,0x06,0xe4,0x8c,0xc2,0x6b,0xf8,0x86,0xa8,0x70,0x89,0x9d,0x0f,0xaf,0x75,0xac,
+  0x4a,0x06,0xd6,0x0b,0xf3,0x0b,0xf1,0x4f,0x7f,0xae,0x89,0xff,0x91,0x23,0xc6,0x33,
+  0x66,0x7f,0xc7,0x65,0x7b,0x0a,0xf2,0x4f,0xf5,0x17,0xc6,0xb7,0x35,0xc8,0xb2,0x17,
+  0xc8,0x6b,0xfb,0x52,0xbd,0x6d,0x2b,0x6d,0x5b,0xf4,0xfe,0xeb,0xfd,0x5c,0xff,0x72,
+  0xf2,0x4f,0xaf,0xfa,0x1b,0xb2,0xc9,0x72,0xb2,0x7f,0x52,0x76,0x96,0x6b,0x9e,0x2d,
+  0x16,0xcf,0xdc,0x1c,0xab,0x2a,0xc4,0x3f,0xbd,0xd9,0xb7,0xb3,0x8a,0x0c,0x3c,0x2e,
+  0xd7,0x86,0xf9,0x0c,0x2d,0x53,0xdc,0x62,0x5c,0xba,0x35,0x57,0xaf,0x9c,0xfc,0x93,
+  0x82,0x87,0x4c,0x35,0xe3,0x28,0xc4,0xa3,0xbe,0x34,0x09,0x63,0xb6,0xbf,0xd7,0xe7,
+  0x1a,0xbd,0x83,0x7f,0x8a,0xfa,0xad,0x26,0xa2,0xc3,0x7e,0xb5,0x4e,0x17,0x3f,0x5b,
+  0x9b,0x2d,0x9b,0x83,0xb9,0xfe,0xe5,0xb8,0xff,0x22,0xb5,0xc3,0x1c,0xbc,0xf6,0xb4,
+  0xf2,0xa5,0xfa,0x1f,0x61,0x69,0x20,0x3e,0x9e,0x1d,0x89,0x17,0xe2,0x1f,0x92,0x22,
+  0x9f,0x58,0xfd,0xee,0x2d,0x58,0x16,0x25,0x46,0x3d,0x2d,0xe3,0x03,0x65,0xed,0x6c,
+  0x33,0x9e,0x82,0xab,0xa7,0xf3,0x4f,0x07,0xf7,0xed,0x70,0xb6,0x49,0xbd,0xc2,0x75,
+  0x6b,0xde,0x8d,0x02,0xbd,0x38,0x36,0x14,0x89,0x44,0xae,0xff,0xea,0x0e,0xfd,0x47,
+  0x51,0xb2,0xea,0xc4,0x19,0xa5,0x7b,0xbb,0x97,0x1a,0x4f,0xd3,0x69,0x6a,0x76,0xfe,
+  0xc2,0x7c,0xfe,0x01,0x43,0xfd,0x98,0x1b,0x22,0x41,0xa3,0xef,0x5f,0xa4,0x3f,0x76,
+  0x19,0xc4,0x28,0xc8,0xdf,0xe6,0x0a,0xf0,0x8f,0x18,0x95,0xcf,0x5b,0x4e,0xbd,0x0e,
+  0x87,0xd4,0x75,0x99,0x35,0x49,0xea,0x26,0x94,0x6d,0x31,0xfa,0xcb,0x8a,0x3c,0xfe,
+  0xf9,0x4e,0xc2,0x52,0x33,0xd2,0x9e,0xcf,0x09,0x9a,0x10,0x63,0x8b,0x9b,0x7f,0xdc,
+  0xf7,0x5f,0x93,0xec,0xbd,0x70,0x39,0xb6,0x4c,0x27,0xa0,0x78,0xaf,0x8b,0x9f,0xf3,
+  0xef,0xbf,0x82,0xa7,0x09,0xe4,0x04,0x61,0x10,0x7b,0xe9,0xf7,0x7f,0x6c,0xec,0xc9,
+  0xdd,0x7f,0x39,0xea,0x8f,0xdd,0x8f,0xda,0x60,0x10,0x91,0xf3,0x05,0xa8,0xad,0x00,
+  0xef,0xe5,0xe9,0x3f,0x24,0x68,0xc5,0x01,0x18,0x1c,0x5e,0xa4,0x91,0xf5,0x03,0x2e,
+  0xfe,0x74,0xdc,0x7f,0x55,0x67,0x3f,0xf4,0xd0,0xd5,0x9b,0xe5,0x0c,0x6e,0xd4,0xa4,
+  0xbe,0x92,0xcd,0xd3,0xf9,0x50,0x28,0x70,0xff,0x65,0x44,0x83,0xa0,0xf1,0x0b,0x9a,
+  0x84,0x4b,0x2e,0xcf,0x7e,0xff,0x45,0x16,0x69,0xa4,0xc7,0x70,0x02,0xc6,0x55,0x62,
+  0x3c,0x97,0x4b,0x4b,0x3b,0xdf,0x1c,0xfc,0xc3,0x99,0xbb,0x5d,0xfb,0x32,0x9a,0xa8,
+  0x1a,0xd4,0x48,0x3e,0xcc,0x29,0xb0,0x7f,0x27,0xff,0xd0,0x68,0x90,0xb0,0x34,0x91,
+  0x68,0x24,0x65,0x5e,0x13,0x50,0xb6,0xec,0x14,0xbe,0xff,0x72,0xf0,0xcf,0x29,0xe6,
+  0xf9,0x74,0xad,0xde,0x1d,0xc9,0x61,0x80,0xad,0x87,0x9c,0xcc,0xd3,0x7f,0x1a,0x4c,
+  0xb5,0x47,0xa7,0x86,0x8f,0x15,0xf3,0xbe,0xff,0x53,0x40,0xff,0xd1,0x0c,0xec,0xf9,
+  0x94,0x46,0xe3,0x34,0xeb,0x8e,0x4f,0x41,0xfe,0x99,0x80,0x0c,0xcd,0x46,0xcc,0xba,
+  0xe3,0x53,0x90,0x7f,0xe8,0xdb,0x13,0xfd,0xfe,0x0f,0xda,0xeb,0x7a,0x9f,0x2a,0xc4,
+  0x3f,0xc5,0xa7,0xe0,0x17,0xda,0x02,0xdd,0x53,0x53,0xc0,0xdf,0x82,0xfc,0x33,0xc2,
+  0x3f,0x8b,0x15,0x4d,0x08,0xc4,0x7a,0x5c,0xf9,0x56,0x90,0x7f,0xc6,0xe1,0x33,0x7c,
+  0x37,0x2e,0x1f,0x43,0xfe,0xdc,0xc8,0xcc,0xfa,0x4f,0xa7,0xf5,0xf6,0xdd,0xc1,0xba,
+  0xbf,0x0f,0xe3,0xe6,0x1f,0xa6,0x97,0xf6,0x3b,0x8d,0xf4,0x47,0xf9,0xfa,0xd9,0xf5,
+  0x9f,0xac,0xc8,0xb0,0xcb,0x50,0x1b,0xbc,0x6a,0xb7,0x03,0x63,0x0a,0xe9,0x3f,0x9c,
+  0xf9,0xb4,0xd4,0x78,0xca,0x2f,0xa4,0x7f,0xd1,0xc7,0xcc,0xfc,0xfd,0x1f,0x3e,0xfb,
+  0xfd,0x1f,0x52,0x7f,0xa8,0xfa,0x01,0xaa,0x50,0xe3,0x71,0xeb,0x21,0x0e,0xfe,0x29,
+  0x35,0xf5,0x9f,0x32,0xd3,0xbb,0x15,0xcc,0x4e,0x2c,0x28,0x2e,0x7f,0x3f,0xce,0xf1,
+  0x4f,0xb5,0x43,0xcd,0x78,0x99,0x18,0x3b,0xdf,0x2e,0xa0,0x6f,0x38,0xf9,0x27,0xcb,
+  0x03,0x69,0x96,0xde,0x7f,0x11,0x63,0x34,0xee,0x73,0xeb,0x45,0x6e,0xfd,0xc7,0x50,
+  0x7b,0x48,0xe9,0x11,0x3a,0x67,0xd5,0x7f,0x80,0x1b,0x76,0x79,0xd7,0x5a,0x40,0xef,
+  0x2a,0xa0,0xff,0x64,0xa3,0xb7,0x7b,0xd6,0xef,0xff,0xec,0xaf,0xea,0x9b,0xee,0xdd,
+  0xba,0x3d,0xdd,0x1b,0x0d,0xd9,0xc7,0xb1,0x7f,0xe4,0xba,0xff,0xca,0xce,0xef,0x27,
+  0x86,0xcc,0xf6,0xb9,0xe2,0x53,0x90,0x7f,0x68,0xb4,0x1b,0x41,0x8a,0xb3,0x49,0x57,
+  0xfc,0xf3,0xef,0xbf,0x48,0xb7,0xd2,0x09,0x84,0x3c,0xa6,0x12,0xfe,0x19,0x47,0xfe,
+  0x2b,0xeb,0x3f,0x9a,0xf0,0xff,0xec,0x5d,0x6f,0x70,0x1c,0x45,0x76,0xef,0x9d,0x1d,
+  0xcb,0x63,0x69,0xa5,0x1d,0xdb,0x12,0x25,0x62,0xe3,0x5b,0xaf,0x05,0xa7,0xa3,0xd6,
+  0x6b,0x59,0x0a,0x3e,0xfe,0x08,0x69,0x2c,0xa8,0x94,0x8c,0x55,0xe5,0x2d,0xc2,0x07,
+  0x92,0xa2,0xa8,0x2d,0xca,0x1f,0x9c,0x2a,0x1d,0x51,0x25,0xf9,0xe0,0xba,0x23,0x66,
+  0x2c,0x0b,0x22,0x63,0x5d,0xd0,0x01,0x97,0x38,0x09,0xa1,0xd6,0x2e,0x7f,0x30,0x57,
+  0xae,0x8a,0x64,0x63,0x63,0xd9,0x17,0xdd,0x58,0x08,0x4e,0x18,0x63,0x94,0x40,0x11,
+  0x03,0x2e,0x6e,0x21,0x22,0x27,0x40,0xe7,0x08,0x63,0x1b,0xdb,0xc8,0x76,0xba,0x7b,
+  0xa6,0xbb,0x5f,0xcf,0xf4,0xec,0x8e,0x8f,0x4a,0x8a,0xaa,0xa0,0x4f,0xaf,0x76,0xbb,
+  0xd6,0xd3,0xcf,0x33,0xef,0xfd,0xe6,0xf7,0x7e,0xef,0x75,0x0a,0x3f,0x1d,0x43,0x0e,
+  0x0e,0x44,0x4b,0xb5,0xe0,0xf3,0x72,0xdc,0x5f,0xff,0x72,0xfe,0x89,0x3c,0xad,0x3f,
+  0x77,0xf0,0xf3,0xeb,0x28,0xf8,0x93,0x69,0x58,0xff,0x72,0x41,0x4e,0x67,0xfc,0x43,
+  0xfd,0xbc,0x7d,0x07,0x36,0x16,0xbf,0x60,0x96,0xe5,0x7f,0xdc,0xfa,0xd7,0x8d,0x31,
+  0x6c,0x20,0x95,0xfe,0x47,0x63,0xfe,0xb1,0xe6,0x5d,0xb5,0x68,0x92,0xda,0x14,0x6b,
+  0xb3,0xae,0xd8,0x3f,0x9c,0x4a,0x9e,0x52,0xf0,0x3f,0x93,0xb5,0x3e,0xfe,0x87,0x5c,
+  0xe4,0x52,0x74,0x90,0xc4,0x9f,0xfc,0xb6,0x87,0x4a,0xd4,0xbf,0x6c,0xf4,0xbc,0x49,
+  0x3f,0xb4,0xb4,0xa5,0xb1,0x83,0xe8,0x66,0x67,0xc9,0x03,0x8a,0x78,0x25,0xd5,0xbf,
+  0x3c,0x7f,0x56,0x24,0xd0,0xb0,0x91,0x72,0x96,0xd4,0x0b,0x37,0x72,0xe3,0x3d,0x5f,
+  0xfd,0x8b,0xee,0x37,0x83,0x2e,0xd9,0x38,0x7e,0xf6,0xc5,0xf7,0x05,0xf4,0x2d,0xc7,
+  0x01,0x1f,0xee,0x39,0x61,0x0f,0xfe,0xf6,0x52,0x0e,0x1b,0x83,0x55,0xdd,0x01,0xff,
+  0x4c,0xf9,0xf9,0x1f,0x22,0xe3,0x9c,0x23,0xef,0x23,0xc4,0x9f,0xad,0x81,0x78,0x2e,
+  0xf0,0xd2,0x31,0xbd,0xdb,0x4d,0x52,0x7b,0x7a,0x67,0xf4,0x11,0x1b,0x27,0xb2,0x81,
+  0xa7,0x82,0xf9,0x0b,0xd4,0xbf,0xbc,0x7c,0x87,0x6f,0xaa,0x19,0x34,0xd2,0x8f,0x8d,
+  0xbd,0x8a,0x7c,0x17,0xe0,0x7f,0xdc,0xfb,0x0d,0x1b,0xc7,0x28,0xde,0x2e,0xc1,0xff,
+  0x18,0x5e,0x36,0x19,0x24,0xfb,0xd5,0xa8,0x91,0x09,0xd4,0x43,0x8b,0x7e,0xfe,0xc7,
+  0x49,0x16,0xe3,0x73,0xc6,0x79,0xb6,0xf1,0x48,0xf8,0xe7,0x2a,0xc2,0xf7,0x4f,0x11,
+  0x7f,0xcb,0xef,0x9f,0xb9,0xd4,0x5b,0x21,0xf5,0x2f,0x02,0x72,0x66,0xec,0x11,0x82,
+  0x7f,0xae,0x70,0xfc,0xb3,0xe8,0x4d,0xed,0x0d,0xaf,0xfe,0x55,0xc1,0xeb,0x5f,0xf3,
+  0xba,0x0c,0xb6,0x3b,0xfc,0xa2,0xd1,0xe0,0xc0,0xfd,0x8e,0xef,0x7e,0x36,0xa4,0xfe,
+  0xe5,0x7a,0x0f,0xff,0xbe,0x43,0x85,0x40,0xde,0x27,0x53,0x69,0x0f,0x9a,0xce,0x0a,
+  0x7c,0x52,0x07,0xf3,0xaf,0x4d,0xd1,0x60,0x26,0xc6,0xdc,0x62,0x7d,0x10,0x52,0xff,
+  0x92,0xbc,0xc1,0x8d,0x0b,0x5a,0x98,0xfe,0xd9,0xa9,0xe1,0xde,0x6e,0xda,0x26,0xf2,
+  0x7b,0xca,0x83,0xee,0x5f,0x48,0xf5,0xaf,0xcf,0xf9,0xff,0xbe,0x99,0x75,0x76,0xcc,
+  0x8a,0xeb,0x3f,0xc3,0xf8,0x9f,0x0b,0x81,0xfa,0x97,0x8b,0x76,0x2c,0xec,0x8d,0xdb,
+  0x84,0x7f,0x3e,0x61,0xfc,0xcf,0x2c,0xcf,0x77,0xa4,0xfe,0x25,0x57,0x7f,0x00,0x0d,
+  0xf2,0x2e,0xe3,0x7f,0xe6,0xb8,0xfe,0x73,0x9d,0x91,0xb0,0xbe,0x74,0xd5,0x3e,0x04,
+  0xed,0x2c,0x25,0x68,0x87,0xe1,0x9f,0x7b,0xc6,0x53,0x9c,0xff,0x61,0xeb,0xad,0x1b,
+  0x81,0x7f,0x08,0x90,0x7e,0xfa,0xfc,0x0e,0xee,0x1f,0x4e,0x24,0x4e,0xf2,0xf8,0xf0,
+  0x0b,0x88,0x7f,0x2e,0xa3,0xe6,0x63,0xc9,0xfd,0xf1,0x19,0x71,0x7f,0x7a,0xfe,0x19,
+  0x13,0xf8,0xe7,0x67,0x52,0xb4,0x3c,0x28,0x85,0x91,0xd3,0xf8,0x55,0xeb,0x0e,0x8a,
+  0x7f,0x38,0xbe,0xb2,0xad,0x17,0x0c,0x80,0x76,0x96,0x17,0xab,0x7e,0x5c,0xc1,0x61,
+  0xcf,0x49,0xcd,0xdb,0xef,0x84,0x0a,0xff,0xcc,0xa0,0x03,0x76,0x83,0x78,0xac,0x76,
+  0x60,0x23,0xed,0x51,0x91,0xef,0x23,0x35,0xfe,0x31,0x9b,0x25,0xd8,0x73,0x09,0x1d,
+  0x67,0xf8,0x87,0x5d,0x3f,0xa8,0x7f,0x61,0x23,0x27,0xa7,0x21,0x22,0x84,0xbe,0xd3,
+  0xc5,0x3f,0xec,0xfa,0x01,0xff,0x43,0x68,0x81,0x66,0x2b,0xf9,0x07,0xb4,0x3e,0x02,
+  0x89,0x02,0x82,0x7f,0xd8,0xf5,0x03,0xfe,0x67,0x0a,0x6d,0x37,0x88,0xfe,0xb9,0x43,
+  0xe0,0x9f,0xd4,0xf6,0x12,0xfc,0xcf,0x14,0xe5,0x7f,0xd6,0x03,0xbc,0x34,0x6e,0x7a,
+  0xeb,0x4f,0xf2,0xfb,0x0d,0x09,0xfe,0xe7,0x55,0xfc,0x72,0x48,0xf5,0xcf,0xe2,0x13,
+  0xcd,0xe3,0x43,0x8e,0xcf,0x63,0xcb,0x41,0xfd,0x8b,0xf3,0x3f,0x04,0xff,0xac,0x61,
+  0x9f,0xf8,0xf8,0x9f,0x53,0x37,0x89,0xfd,0x6a,0xe7,0xd1,0x28,0xc6,0x03,0x22,0xad,
+  0x9f,0xf7,0x8c,0xc5,0xfe,0xfa,0x97,0xa7,0x8e,0x3e,0x4f,0xd4,0xd1,0x93,0xdb,0xf8,
+  0x27,0xef,0xa2,0x00,0xff,0xb3,0xd9,0x2c,0xea,0x00,0xed,0xec,0x26,0xf8,0x87,0xc3,
+  0x9e,0xff,0xb4,0x19,0xff,0xc3,0xe3,0x8f,0x01,0xea,0x5f,0xa9,0x11,0xbb,0x51,0x02,
+  0x42,0xaf,0xa6,0xb6,0x32,0xfd,0x33,0xf3,0xbf,0x84,0x7f,0x8e,0x12,0x3e,0x8d,0x18,
+  0x77,0xb8,0x08,0x93,0xfb,0xf3,0x35,0xbe,0xbe,0x50,0x07,0xae,0x9f,0xa8,0xbb,0xe7,
+  0x03,0x18,0xf3,0x5b,0x27,0xc0,0xff,0x4c,0x4b,0xfc,0x8f,0xc3,0x8c,0x98,0xe7,0x31,
+  0xef,0xab,0xb3,0x21,0xf8,0xc7,0x6e,0x8e,0x6d,0x80,0xf7,0x9b,0xed,0xf9,0x7f,0xcc,
+  0x57,0xff,0xf2,0xd0,0xce,0x21,0xb4,0xdb,0x05,0x42,0xde,0x27,0x97,0xd0,0x53,0xa1,
+  0xf8,0xa7,0xc9,0x3c,0xa1,0xef,0x27,0xef,0x0b,0xb7,0xf7,0xf2,0x27,0xe8,0x24,0x6b,
+  0x54,0x79,0x43,0xc5,0xff,0x9c,0xb6,0x47,0x0d,0x82,0x1f,0x7a,0xc9,0xf3,0x5b,0x4d,
+  0x19,0xa1,0x94,0x57,0xc8,0x2e,0xf2,0xf8,0xb0,0xb7,0x7f,0x19,0x43,0x3b,0xbf,0xb1,
+  0x2f,0xd8,0xab,0x89,0xfe,0x99,0xcb,0x7e,0x3e,0xb4,0x7e,0xed,0x7e,0xf5,0x71,0x50,
+  0xff,0xe3,0xc6,0x93,0x36,0xe7,0xe9,0x02,0x12,0x69,0x4e,0x63,0xf8,0x47,0xbc,0xff,
+  0x32,0xfc,0x83,0xf3,0x97,0x79,0xce,0x6e,0x29,0x56,0xfd,0x49,0x95,0x9b,0xbf,0xde,
+  0xba,0xb8,0xe2,0x02,0x6b,0xe4,0x11,0xfc,0x8c,0xa7,0xff,0x71,0xa3,0xcd,0x41,0x13,
+  0x5f,0x7f,0x2e,0xce,0x77,0x74,0xca,0xf2,0xae,0xff,0xb3,0x0a,0xb6,0x1e,0x39,0x4b,
+  0x0d,0xbe,0xfe,0x97,0x68,0x17,0x5e,0x2f,0xf0,0xde,0xbb,0xac,0x70,0x1f,0xa8,0x7f,
+  0xb9,0x61,0x67,0x88,0xf8,0xd3,0x04,0xf9,0x9d,0xc5,0x73,0x11,0xaf,0xf6,0xd6,0xf1,
+  0xfd,0xce,0xa1,0xb3,0x6e,0xff,0x08,0xcf,0x2f,0x6f,0xb2,0xf8,0xf9,0x99,0xbf,0xfe,
+  0xe5,0xf9,0x27,0x35,0x4a,0xd6,0x0b,0xff,0x30,0x61,0x86,0x54,0xff,0x32,0x78,0x3c,
+  0xbf,0x8a,0x7e,0xe8,0x24,0x1d,0x28,0xf3,0x78,0xcb,0x35,0x26,0x00,0xff,0xd3,0x2d,
+  0xf2,0xef,0x11,0xfb,0x56,0x67,0xc7,0x40,0x2f,0xd7,0xff,0x14,0xd1,0x8e,0x79,0xf4,
+  0xab,0x69,0xa8,0xff,0x81,0xeb,0x6f,0x71,0x76,0xf4,0x6b,0x33,0x31,0x96,0xaf,0xcd,
+  0x1d,0xa1,0xf8,0x87,0xf8,0xe7,0x08,0x89,0xc6,0x68,0x11,0xd7,0xff,0x4c,0x33,0xff,
+  0x8c,0xf1,0xf8,0x83,0x7e,0x0a,0xd0,0xdd,0x11,0x74,0x83,0xf3,0x34,0xdb,0x6f,0xd5,
+  0x10,0xce,0x47,0xc4,0x3f,0x1b,0x86,0x16,0x3b,0x42,0xff,0x53,0x0d,0xd2,0x3a,0xed,
+  0xdf,0x71,0x54,0xf8,0x67,0x2b,0xf3,0x27,0xc7,0x3f,0x13,0xf1,0xab,0xfa,0xb5,0x86,
+  0x16,0x09,0x36,0x87,0xf3,0x3f,0x84,0xf6,0x39,0x83,0x0e,0x4f,0xa6,0x25,0xda,0x27,
+  0x9c,0xff,0xb1,0xaa,0x1a,0xb5,0x13,0xd8,0x2d,0x29,0x09,0xe6,0x85,0xf3,0x3f,0x39,
+  0x82,0xaf,0xf0,0x6b,0x6c,0x5a,0x82,0x91,0xe1,0xfa,0x9f,0x9e,0x64,0x3f,0x71,0x4b,
+  0x47,0xb3,0x04,0x0b,0x39,0x7e,0x0e,0xd4,0xbf,0x72,0x14,0x16,0xce,0x99,0xbf,0x52,
+  0x03,0x21,0x3f,0xff,0x83,0x83,0x12,0xfe,0x7d,0xfd,0x27,0x56,0x88,0xde,0x0c,0xd6,
+  0xbf,0x32,0x2e,0xfb,0xb7,0x13,0xdf,0xa8,0xc3,0xbe,0xcb,0x0e,0xe5,0x7f,0x48,0x5b,
+  0x9c,0xc2,0x2d,0xa5,0xf8,0x9f,0x07,0x31,0x1e,0x38,0xe8,0xa3,0x41,0x42,0xf9,0x1f,
+  0x0c,0x72,0x4c,0x82,0x7f,0xac,0xd6,0x09,0x48,0xfb,0x84,0xf3,0x3f,0xc8,0x85,0xcd,
+  0x66,0x08,0x50,0x0c,0xf0,0x3f,0xc5,0xc4,0xa0,0xc2,0x2d,0x25,0xf8,0x1f,0x23,0x47,
+  0xe2,0x8f,0xef,0x35,0x2a,0x94,0xff,0x59,0x55,0x34,0x1e,0xec,0x08,0x6e,0x33,0x9c,
+  0xff,0xb9,0xdf,0xb8,0x01,0x7b,0x6f,0xd8,0x0e,0xf1,0xa7,0x9f,0xff,0x69,0x2f,0x24,
+  0x66,0x30,0xec,0xb9,0x9a,0xc8,0xda,0x4f,0x03,0xfc,0x43,0x8c,0xac,0x92,0xff,0xd1,
+  0xff,0xc5,0xa5,0x7d,0x6a,0x64,0xfc,0x53,0xa2,0xfe,0xf5,0x0c,0x4e,0x73,0x5f,0xe8,
+  0xcd,0x6b,0xe1,0x6b,0x7e,0xb8,0xfe,0x87,0xb1,0x0d,0xbb,0x25,0xda,0xa1,0xa4,0xfe,
+  0xa7,0xd4,0x7a,0x75,0xfd,0x0b,0x0d,0xc7,0x82,0xfd,0x5f,0xe1,0xfa,0x1f,0xb2,0xbb,
+  0x66,0xf5,0x7e,0x41,0xfd,0x8b,0xe2,0x9f,0xbb,0x29,0x9f,0xa3,0x5f,0xb3,0xe4,0x6d,
+  0x2a,0xf9,0x1f,0xd2,0xff,0xd5,0xb6,0x36,0x81,0xd7,0x9b,0x97,0x8c,0x66,0xf5,0xfa,
+  0xa0,0xfe,0xc7,0x20,0x32,0x6c,0x8a,0x7f,0xd4,0xfd,0x5f,0x72,0xfd,0x2b,0x4b,0x64,
+  0x06,0x64,0x77,0xa1,0xfb,0xf5,0xf1,0x3f,0x1d,0x8d,0xae,0x8c,0x3c,0xbd,0x56,0xed,
+  0x4f,0x49,0xff,0x83,0xaf,0x3f,0x97,0x78,0x8e,0xc0,0x36,0x2b,0xe4,0xfa,0x03,0xf5,
+  0xaf,0x75,0xee,0xfd,0x50,0x08,0xf1,0x4f,0x80,0xff,0x31,0x5d,0x6f,0x5b,0x21,0xfe,
+  0xf7,0xeb,0x7f,0x32,0x6e,0x91,0xf2,0x08,0xc1,0x3f,0x80,0xf6,0x29,0xc5,0xff,0xb8,
+  0x34,0x45,0xea,0x98,0xf2,0x79,0x51,0xe1,0x1f,0x0c,0x7b,0x0e,0xa0,0xe5,0x4e,0x99,
+  0xfe,0x2f,0x5e,0xff,0xc2,0xb0,0xc7,0xf8,0x8a,0xe0,0x1f,0x40,0xfb,0x94,0xe2,0x7f,
+  0x4a,0xc6,0x13,0xbf,0xfe,0xa7,0x7d,0x2a,0x79,0x4a,0xdb,0x62,0xfd,0x6a,0xf0,0x80,
+  0x3a,0x7f,0x05,0xf4,0x3f,0x04,0xf6,0x3c,0x84,0x5e,0x6e,0x5a,0xad,0x8e,0x3f,0xb2,
+  0xfe,0x87,0x14,0xf5,0x96,0x4c,0x6a,0x18,0x08,0x69,0x37,0xb3,0x65,0xb2,0xde,0x3b,
+  0x80,0x7f,0xce,0x2e,0xa9,0xad,0xe8,0xd2,0x0f,0x0c,0x86,0xe4,0x3b,0x59,0xff,0xf3,
+  0x39,0x6a,0x1b,0x4b,0xd6,0x12,0xd8,0x63,0x91,0xf7,0x77,0x6d,0xc6,0xad,0x38,0xa8,
+  0xfb,0xbf,0x20,0xfe,0xf9,0x3a,0x15,0xe2,0x9f,0x80,0xfe,0x87,0xe8,0xeb,0x5a,0x71,
+  0xb4,0x6f,0x51,0xc7,0x73,0x27,0x88,0x7f,0x06,0x35,0x92,0x88,0x49,0xfe,0xed,0x50,
+  0xe8,0x99,0x03,0xf8,0xa7,0xd2,0xad,0x76,0x85,0xe4,0x6b,0x05,0xfe,0x31,0x29,0xcd,
+  0x58,0x0c,0xc3,0x03,0xdc,0xfd,0xae,0xfe,0xc7,0xa9,0x19,0xa4,0xb0,0xd0,0x9f,0xdf,
+  0xc3,0xf4,0x3f,0x4e,0x32,0xa7,0xd8,0x66,0x39,0xfe,0xe7,0x1a,0xe1,0x7f,0x88,0x0c,
+  0x86,0xf7,0x7f,0x05,0xf8,0x1f,0xdb,0x0c,0xa0,0x9d,0x8e,0x6b,0x96,0xab,0x08,0x4a,
+  0xcf,0xd8,0xa4,0x11,0xbe,0x26,0xa4,0xfe,0xc5,0x8d,0x81,0xd8,0xb3,0x8c,0x11,0xda,
+  0x16,0x82,0x7f,0x7c,0x6e,0xac,0xf2,0x0c,0x93,0x94,0x1a,0x2b,0x15,0xf8,0x87,0x79,
+  0x63,0x8d,0x6b,0x30,0xbd,0x9c,0xf9,0x46,0x09,0xfd,0x0f,0xf1,0xc6,0xf7,0x22,0xe2,
+  0x1f,0xc9,0xdb,0x99,0xd4,0x07,0x5a,0x19,0xfc,0x03,0xae,0x7f,0x3f,0x7e,0x5f,0x88,
+  0x80,0x7f,0x80,0x7f,0x12,0xe8,0x59,0xce,0x60,0x94,0xaa,0x7f,0xa1,0x97,0xfb,0x56,
+  0x7e,0x8c,0x8d,0x65,0x56,0x04,0xfc,0x83,0xd1,0x8e,0xfe,0xa5,0xd6,0x3a,0x9e,0x6c,
+  0x5a,0x91,0xb0,0xde,0x2e,0x5b,0xff,0x12,0xde,0xe8,0x89,0x5f,0xb9,0xf7,0x1a,0x5a,
+  0x15,0xa5,0xfe,0x75,0x14,0x6d,0xc1,0x68,0x5c,0xd0,0x3e,0x65,0xeb,0x5f,0x31,0xda,
+  0x6d,0xfa,0xd3,0x12,0xfd,0xef,0x92,0xfe,0xe7,0xe5,0xde,0x95,0xc5,0x1d,0x9b,0x6f,
+  0xf9,0xd0,0xfe,0x9b,0xbe,0xf2,0xf5,0x2f,0xaf,0xad,0x60,0x09,0xbe,0xdf,0xfc,0xf3,
+  0x16,0x6e,0x09,0xa9,0x7f,0x31,0xa3,0x54,0xff,0xbb,0xc4,0xff,0xc4,0x68,0x21,0x2c,
+  0x58,0x8f,0x50,0xea,0x7f,0xa6,0x5c,0x19,0x0c,0x11,0x8a,0xbc,0x1e,0x11,0xff,0xc4,
+  0x68,0xff,0xf5,0x27,0xc6,0x7b,0x51,0xf1,0xcf,0xa3,0x6e,0xe1,0x6c,0x7b,0x44,0xfc,
+  0xe3,0x1a,0x27,0x98,0x42,0xe6,0xd5,0x70,0xfc,0xc3,0xbb,0xbd,0x28,0xff,0xe0,0xef,
+  0x3f,0xf2,0xe3,0x1f,0x79,0x77,0x9f,0x94,0xc1,0x3f,0xe0,0x5b,0xaa,0x17,0x3a,0x57,
+  0x78,0x1d,0x5f,0x76,0x35,0xc4,0x3f,0xba,0x1f,0xff,0xb8,0x68,0x27,0x46,0x8d,0x8f,
+  0xd0,0x29,0xf7,0x93,0x8f,0x6d,0xf7,0xab,0xd8,0xdf,0x4a,0xf8,0x87,0xed,0x77,0x01,
+  0x35,0x9a,0xd2,0xe3,0x68,0x6b,0x2c,0x63,0x2d,0x30,0x49,0x47,0x58,0x78,0xfd,0xab,
+  0xc2,0xf3,0xa7,0x2b,0x04,0x92,0xfd,0xf9,0x24,0x8f,0x0f,0x80,0xff,0x99,0xd2,0x2f,
+  0x69,0x9e,0x9e,0xe7,0x75,0xb4,0x45,0xba,0xfe,0x69,0xe4,0xc3,0x3f,0x6c,0xbf,0xcb,
+  0x98,0xb1,0xa5,0x7c,0xfd,0xab,0xe0,0x0d,0x22,0x10,0xb4,0x8f,0xc0,0x3f,0xfc,0xfe,
+  0x97,0xf8,0x9f,0x23,0x5a,0xb6,0x70,0x1f,0xe9,0x67,0x7c,0xaa,0x3c,0xfe,0x69,0x72,
+  0xcb,0x5e,0xe3,0x37,0x36,0xf5,0x72,0x9a,0x42,0xd4,0xbf,0x74,0x15,0xff,0x43,0x8c,
+  0x62,0x55,0x8e,0xd2,0xb6,0x65,0xf1,0xcf,0xe6,0xf8,0x0b,0xd4,0xa8,0xde,0x14,0x3f,
+  0x89,0x7e,0x5d,0x1e,0xff,0xd0,0xe8,0xa1,0xb5,0x3a,0x35,0x80,0xdf,0xb8,0x1a,0x8a,
+  0x7f,0x00,0xda,0x39,0xb5,0xf8,0x02,0x7a,0xbc,0x3c,0xfe,0xa1,0x57,0xbb,0xf0,0x47,
+  0x13,0x55,0x0f,0x78,0xfd,0xef,0x0b,0xc8,0x27,0xbf,0x75,0xbf,0xfa,0x5c,0xc2,0x3f,
+  0x12,0x3a,0x5a,0x92,0x0f,0xf6,0xcb,0x87,0xf1,0x3f,0xd4,0x40,0x5e,0x7f,0xf7,0x02,
+  0xd0,0xdf,0x14,0xd0,0x3f,0x83,0x68,0x09,0xf6,0x3b,0x57,0x0e,0xff,0x10,0xa3,0x6f,
+  0x3e,0xf8,0xe4,0x73,0x35,0xfe,0xb9,0x8b,0x47,0xef,0x7c,0xd2,0x89,0x9f,0x67,0x61,
+  0xfc,0xb1,0x12,0xf8,0xc7,0xcb,0x56,0x56,0xcd,0x80,0x36,0x65,0x97,0xc3,0x3f,0xb7,
+  0x12,0xbd,0x0a,0xfd,0x76,0xa2,0x6a,0x27,0xfe,0xdf,0x8f,0x80,0x7f,0x3c,0xff,0x58,
+  0x95,0xe6,0xa2,0x89,0x32,0xf8,0xe7,0xa8,0x84,0x06,0x6d,0xa1,0xf7,0xee,0x2e,0x81,
+  0x7f,0xbc,0xfd,0x5a,0x35,0x4e,0x2c,0xd8,0xbf,0x03,0xf0,0x4f,0x9d,0x54,0xff,0xba,
+  0xab,0x73,0x40,0xc9,0xff,0xc4,0xb8,0xff,0x21,0xfe,0x39,0x6c,0xa7,0xbb,0x8c,0x28,
+  0xfc,0x4f,0xa3,0xbb,0xbb,0xfd,0xe8,0xd6,0x8e,0x46,0x35,0xde,0xe3,0xfa,0xe7,0x79,
+  0x00,0xff,0x1c,0x46,0xe9,0xbc,0x51,0x86,0xff,0x81,0xf9,0xf7,0x52,0xae,0x31,0x9f,
+  0x50,0xe1,0xc3,0x30,0xfc,0x63,0xb7,0xa3,0x72,0xf8,0x07,0x81,0xfb,0xf3,0xe2,0xbd,
+  0x6d,0x56,0x02,0xe2,0x2b,0x05,0xfe,0xa9,0x03,0xf8,0x67,0xc8,0xc9,0x76,0x36,0x46,
+  0xe4,0x7f,0x28,0x5f,0xea,0x36,0x0e,0x9c,0x60,0xf8,0xa7,0x8c,0xfe,0x07,0x1d,0x1a,
+  0x5b,0xb9,0xa9,0x33,0x22,0xff,0x43,0xd0,0xce,0x6c,0x67,0x9b,0x95,0x21,0xc6,0xdb,
+  0xee,0x20,0x20,0x15,0xfe,0xa9,0x16,0xfe,0x21,0xc4,0x69,0x67,0x34,0xfe,0xc7,0xf3,
+  0x3f,0x8e,0xde,0x88,0xb9,0xa5,0xa6,0x3c,0xfe,0x79,0x09,0xad,0x44,0x46,0x14,0xfe,
+  0xc7,0xdb,0xdd,0x41,0x7b,0x55,0xde,0x88,0xc4,0xff,0x78,0xfe,0xec,0xc8,0x9e,0x33,
+  0xa2,0xf0,0x3f,0x1e,0xda,0xb9,0x5a,0x68,0x1f,0xcc,0xf8,0xf8,0x9f,0x10,0xfc,0xe3,
+  0x96,0x21,0x3a,0xda,0xb4,0x0d,0x11,0xf9,0x1f,0x9a,0xdd,0x1a,0xb1,0xff,0xaf,0x87,
+  0xff,0x69,0xa0,0x32,0xe6,0xeb,0xe0,0x7f,0xb2,0x9d,0xca,0xf5,0xa1,0xfc,0x4f,0x26,
+  0xd7,0x78,0x5d,0xfc,0x4f,0x1b,0x1a,0x88,0xc2,0xff,0x78,0xbb,0xbb,0x12,0xbb,0x3b,
+  0x17,0x81,0xff,0x11,0xeb,0x51,0x7b,0xce,0x88,0xc6,0xff,0x54,0x11,0x3c,0x30,0x4d,
+  0x1a,0xe1,0xcb,0xf3,0x3f,0xee,0xa6,0x3a,0x88,0x91,0xcd,0x19,0x91,0xf8,0x1f,0xe2,
+  0xb4,0x3d,0xb1,0x17,0x53,0xd9,0x0e,0xb5,0x3f,0xfd,0xfd,0x5f,0xee,0xd5,0x8e,0xac,
+  0x6b,0xcd,0x25,0x22,0xf1,0x3f,0xde,0xb7,0xbd,0x6d,0x7f,0x11,0x8d,0xff,0xf1,0xbc,
+  0x6d,0xb5,0x99,0x35,0x51,0xf8,0x9f,0xac,0xbd,0x83,0xa0,0x9d,0x51,0xb4,0xaa,0xdf,
+  0x88,0xc8,0xff,0x90,0xa7,0x63,0xd8,0xc8,0xe4,0x2a,0x55,0xcf,0x8b,0x52,0xff,0x7c,
+  0x1a,0x1d,0xd4,0x57,0x3a,0xca,0xe7,0x57,0x89,0x7f,0x3e,0x44,0xe7,0xed,0xd6,0x7c,
+  0x4d,0x44,0xfe,0x87,0xc6,0x13,0x9d,0xf6,0x7f,0x95,0xe4,0x7f,0x40,0xfe,0xd2,0x5b,
+  0x9f,0x59,0x9d,0xe2,0xf9,0xab,0x3a,0x14,0xff,0x7c,0xc5,0xaf,0x3f,0x77,0x9b,0xa1,
+  0xba,0x7e,0x14,0xe8,0xff,0xf2,0xd6,0xc7,0xbf,0xaf,0x8e,0x57,0x70,0xfe,0x0f,0x05,
+  0x39,0x2e,0x8d,0x36,0x6c,0x35,0x20,0x65,0xbe,0x83,0xfa,0xe7,0x7d,0xb4,0x48,0xe1,
+  0x76,0x73,0x9f,0xba,0xa5,0x4f,0x99,0xbf,0x42,0xf0,0x0f,0xbe,0x5b,0x86,0xca,0xf1,
+  0x3f,0xc8,0x0d,0xda,0x35,0xb3,0x54,0xff,0xd3,0x62,0x27,0xca,0xf0,0x3f,0xb5,0x02,
+  0xff,0xe8,0xc3,0x63,0x8d,0x7b,0xfd,0xf9,0xeb,0x16,0x35,0xff,0xe3,0x7e,0x6b,0x3f,
+  0x52,0xec,0x57,0xf2,0x45,0x12,0xfe,0xe1,0xd9,0x6d,0x44,0xbf,0xd5,0xf1,0xc7,0xe7,
+  0x06,0x35,0xff,0xe3,0xed,0xb7,0xd9,0xc9,0x94,0xe1,0x7f,0x40,0xfd,0x4b,0x3f,0x7f,
+  0x1d,0xfc,0xcf,0x29,0x57,0xf6,0x9c,0x4a,0x74,0xc6,0xdb,0xcc,0x08,0xf8,0x67,0x67,
+  0x3c,0x8b,0x8e,0xf6,0x66,0x53,0x95,0x7b,0xa3,0xe9,0x9f,0x07,0xb5,0x2e,0x7c,0x63,
+  0x64,0x71,0x42,0x50,0xe8,0xeb,0xe4,0xfe,0x2f,0x8f,0x7f,0xa3,0x8e,0x6d,0xaa,0x7c,
+  0x4e,0x0b,0x30,0x42,0x1d,0x0a,0xfe,0xc7,0x8c,0x93,0x41,0x49,0xad,0xa9,0x2e,0x57,
+  0x3f,0xb6,0x45,0x9a,0x0f,0xa0,0xc0,0x3f,0x9e,0x2c,0x0a,0x25,0x8b,0x02,0x06,0x87,
+  0xf0,0x3f,0x1f,0xb8,0x7c,0x2c,0x7d,0x30,0x73,0x4a,0x7d,0x6f,0x38,0xff,0x63,0x55,
+  0xa5,0x62,0xdd,0x62,0x7e,0x42,0xa9,0xfa,0x17,0x75,0x8b,0x8d,0xdf,0x17,0x82,0x7a,
+  0xb0,0x90,0xfa,0x17,0x6d,0x84,0x9f,0xa9,0xa0,0x13,0x11,0xc9,0xd8,0x9f,0x50,0xfc,
+  0x93,0x21,0xfe,0xc1,0xbf,0xaf,0x3d,0x86,0x36,0x98,0x71,0x57,0x11,0x14,0x82,0x7f,
+  0x6e,0x82,0xfe,0x89,0x3d,0x6e,0x27,0xff,0x2d,0x1a,0xfe,0xf1,0xf8,0x6a,0x3b,0xd9,
+  0x5f,0x5a,0xff,0x1c,0x63,0xfc,0x33,0x89,0x1e,0xda,0x4a,0xbb,0x2a,0xaf,0xd0,0x4f,
+  0x02,0xfc,0x63,0xbe,0x20,0xed,0x97,0xcc,0x3b,0x8a,0xaa,0x7f,0xc6,0x46,0xf7,0x44,
+  0x55,0xab,0xc2,0x9f,0xa1,0xfc,0x4f,0xbb,0x9d,0x2c,0xee,0x88,0xa4,0x7f,0x16,0xb2,
+  0xe7,0x6d,0x45,0xb4,0x39,0x32,0xff,0x63,0x25,0x77,0x5e,0x4f,0xfd,0x8b,0x14,0x52,
+  0xaf,0x0b,0xff,0x84,0xcc,0xeb,0x2b,0xc9,0xff,0x94,0xc4,0x3f,0xf3,0xf2,0x81,0x6c,
+  0x5b,0x12,0xff,0x30,0x3c,0x30,0x19,0xf7,0x1a,0xdb,0x73,0x51,0xf1,0x0f,0x95,0x3d,
+  0xaf,0xdd,0x30,0x49,0x85,0x34,0xe5,0xf1,0x8f,0x96,0xa2,0x46,0x0d,0x33,0x28,0xfe,
+  0x99,0x0e,0xc5,0x3f,0x83,0x9e,0xec,0x59,0x18,0xe5,0xf0,0x8f,0xfb,0x1f,0x51,0x29,
+  0xe9,0xcf,0x5f,0xa4,0x46,0x87,0x02,0xff,0xd4,0xbb,0x97,0x9d,0xab,0xfa,0x3b,0xc5,
+  0xf5,0x2b,0xf0,0xcf,0xf3,0xae,0xec,0xb9,0x93,0x16,0xc2,0x22,0xeb,0x9f,0x43,0x8c,
+  0x20,0xfe,0xf1,0xd0,0x4e,0x0d,0x19,0xd4,0x13,0x19,0xff,0x50,0x03,0xe8,0x7f,0x4a,
+  0xe1,0x9f,0xcd,0xec,0x69,0xdd,0x18,0x0d,0xff,0xf4,0x28,0x60,0x4f,0x59,0xfe,0x87,
+  0xf1,0xf9,0x65,0xeb,0x5f,0x24,0x49,0xb5,0xb1,0x44,0xa6,0xa8,0x7f,0xe9,0x10,0xff,
+  0x78,0x43,0x0e,0x1f,0x22,0x6d,0x5c,0x44,0xd8,0x5c,0xba,0xfe,0xe5,0xed,0x77,0x56,
+  0x11,0xa6,0x4a,0xf1,0x3f,0xb7,0xbb,0x6d,0x3e,0xef,0xa8,0xeb,0x5f,0x3c,0x3e,0x70,
+  0xfe,0xe7,0x30,0x93,0x95,0x16,0x14,0xfa,0x8d,0xcf,0x83,0xfa,0x67,0xee,0x8d,0xbd,
+  0x8b,0x5d,0x63,0xbe,0xfb,0x49,0x56,0x5d,0xff,0x9a,0xef,0x45,0xef,0x31,0x22,0x0c,
+  0x96,0xe3,0xf9,0x86,0xd9,0x15,0x8e,0xe5,0xe7,0x7f,0xd6,0xf1,0x6c,0x55,0xe8,0x8d,
+  0x52,0xff,0xa2,0xdf,0xd2,0x46,0xb0,0xc1,0x8a,0x19,0x23,0xb0,0x5e,0x67,0xf7,0x03,
+  0xe3,0x7f,0xc4,0x74,0x29,0x44,0x0c,0xbd,0x5c,0xfd,0x0b,0xb2,0x5b,0x91,0xf0,0x4f,
+  0x8f,0xaa,0xfe,0x15,0x2b,0x51,0xff,0x9a,0xbf,0x05,0xcd,0x99,0x2d,0x4d,0x89,0x88,
+  0xfa,0x1f,0xca,0xff,0x58,0x69,0x5b,0xc9,0xff,0xcc,0x72,0xff,0x37,0xc2,0xfa,0xd7,
+  0x90,0x99,0x36,0x94,0xef,0xe3,0xa1,0xfa,0xe7,0xdd,0x05,0x54,0x9a,0xff,0x41,0x74,
+  0xfe,0xb0,0x87,0x2e,0x46,0xec,0xa6,0x66,0x5d,0xe9,0x1f,0x7e,0xfd,0xbb,0x4c,0xc0,
+  0xff,0xe0,0xf8,0x6c,0xaf,0x52,0xe2,0x43,0x90,0x7f,0xc5,0xf3,0xa8,0x5f,0x4a,0xdc,
+  0x99,0x52,0xe2,0x73,0xa1,0x7f,0x66,0xfd,0x5f,0x2e,0x7f,0x95,0x48,0xf7,0x29,0xf9,
+  0x2b,0xa1,0x7f,0x76,0x20,0x1f,0x78,0xc4,0x4e,0x2d,0x54,0xbe,0x7f,0xcd,0xf2,0xdb,
+  0x21,0x8f,0x20,0xff,0x63,0xaf,0x28,0x54,0xaa,0xf8,0x90,0x39,0xbe,0x5e,0xe2,0x7f,
+  0xce,0xa2,0xc3,0x7a,0x8d,0x52,0xff,0x53,0xc1,0xd6,0x5b,0x4b,0x21,0x3f,0x66,0xfe,
+  0xeb,0x13,0xd5,0x5f,0x28,0xf1,0x0f,0xdb,0xaf,0x01,0xf9,0x9f,0xaf,0xed,0x66,0xa4,
+  0x8e,0x57,0x42,0xff,0x09,0xf9,0x1f,0xda,0x7f,0x51,0x9a,0xff,0x41,0x90,0xff,0x39,
+  0xd0,0xbf,0xbc,0x49,0xa9,0xff,0x81,0xfa,0x67,0x10,0xcf,0xf7,0x5b,0xe9,0x07,0x95,
+  0xf1,0xe7,0x7d,0x81,0x7f,0x74,0x86,0x7f,0x70,0xd0,0xbe,0x8a,0xbe,0x1c,0x4a,0x2a,
+  0xf9,0x1f,0xf1,0xfb,0x52,0x3e,0xea,0x0c,0xc9,0x47,0x42,0x4f,0xeb,0xce,0x7f,0x16,
+  0x7a,0xd7,0xdc,0x09,0x25,0xff,0xc3,0xd7,0xdb,0xba,0xc8,0xb6,0xe6,0x88,0x1d,0xc6,
+  0xff,0xb0,0xf0,0xc3,0xfb,0xbf,0xf8,0x74,0xbe,0xfe,0x32,0xfc,0x4f,0x2d,0xc4,0x3f,
+  0x56,0x26,0x8c,0x0f,0x61,0xbf,0xcf,0xfa,0xbf,0xe8,0xee,0x2e,0xa3,0x65,0xa4,0xed,
+  0x3d,0xb8,0x5f,0xd1,0xff,0x75,0x18,0xf2,0x21,0xd7,0xac,0x76,0xeb,0x69,0xd5,0x7e,
+  0xcf,0xf0,0xf8,0x73,0x7b,0x1d,0xf0,0xcf,0x5f,0x1b,0x2d,0x6a,0x3d,0xcc,0x19,0xfe,
+  0xfc,0xd6,0x23,0xa0,0x7f,0xbe,0x88,0xd2,0xc6,0x12,0x15,0xff,0x23,0xf4,0xc9,0x96,
+  0xde,0x07,0x76,0x67,0x14,0x3a,0x94,0x78,0xef,0xdf,0x63,0x6c,0x7d,0xbd,0xbe,0x07,
+  0xa2,0x9d,0x74,0x88,0x9e,0x8a,0x3f,0xef,0xde,0xfc,0x43,0x8f,0xff,0x19,0x6c,0xc6,
+  0xdf,0xaa,0xf8,0x1f,0x7e,0x3d,0xd3,0x52,0xff,0x97,0xdd,0xd6,0xa3,0xdc,0xef,0x65,
+  0x81,0x67,0x10,0xb8,0xdf,0xa6,0xad,0x66,0xc4,0xfd,0x5f,0xad,0xc4,0x3f,0x86,0x0e,
+  0xf0,0xcf,0xe8,0xe4,0x8a,0x5d,0x4a,0xfe,0x67,0x8c,0x3f,0x5d,0xc6,0xcf,0xc1,0xf3,
+  0x32,0x82,0x52,0x5b,0x79,0x7c,0x86,0x81,0x28,0xd8,0xff,0x45,0x9f,0xd6,0x43,0xc6,
+  0xf2,0x47,0x42,0xf8,0x10,0x76,0xbf,0x35,0xd6,0x73,0xfd,0xf3,0x87,0xfa,0xdc,0x93,
+  0x2d,0x1f,0x25,0x18,0xec,0xa9,0x06,0xf8,0xe7,0x38,0x8f,0x3f,0x92,0xfe,0xf9,0x22,
+  0x1a,0x2d,0xc7,0xff,0xe4,0xf5,0x51,0x91,0xad,0xe6,0xec,0x96,0x86,0xe4,0x25,0x45,
+  0xfe,0x9a,0x14,0x7a,0x63,0x04,0xf4,0xcf,0x2f,0xd5,0x2f,0xef,0x52,0xc5,0x9f,0x45,
+  0x9f,0x89,0xe7,0x51,0xf0,0x3f,0xcf,0xa3,0xe7,0xd0,0x72,0x6b,0x7d,0x4f,0x45,0x70,
+  0xbf,0xaf,0x59,0xfc,0x7e,0xab,0x75,0xdf,0xee,0xe3,0x34,0xdf,0x39,0xa9,0x9e,0x1d,
+  0xaa,0xf8,0x33,0x09,0xf0,0xaa,0xbb,0xdf,0xef,0x0d,0xc5,0xf6,0xa1,0x23,0x83,0xcd,
+  0x7f,0x15,0x57,0xed,0xf7,0xa4,0xa8,0xb7,0x2e,0x84,0xdd,0x5e,0xd6,0xe8,0x03,0x4a,
+  0xff,0x4c,0xeb,0x02,0xff,0x80,0x78,0xfe,0x35,0x35,0xb4,0xe0,0xfb,0xfe,0x34,0xe7,
+  0x7f,0x8e,0x49,0xf5,0x2f,0x27,0xdb,0xa3,0xd2,0xf3,0xa4,0x8b,0xc1,0xfe,0x2f,0xfa,
+  0x6d,0x7f,0x76,0x16,0x1b,0xdd,0x0a,0xfe,0x87,0xdd,0x3f,0x86,0xe9,0xab,0x7f,0xa9,
+  0xe2,0x73,0x87,0xb8,0x3f,0x51,0xbd,0xdc,0xdd,0x66,0xc1,0xb2,0x97,0xe0,0xbb,0x2a,
+  0xb8,0xfe,0xb9,0xce,0x57,0xff,0x52,0xf3,0x3f,0x7f,0x14,0xa2,0xff,0x69,0x77,0x12,
+  0xeb,0x14,0xfd,0x83,0x00,0xff,0xd4,0x4b,0x68,0x67,0xd5,0x69,0xa3,0x77,0x51,0x90,
+  0xff,0x11,0xf8,0x47,0xd6,0xff,0xe8,0xdd,0xaf,0x18,0x2a,0x7e,0x03,0x9c,0x7f,0x01,
+  0xeb,0x5f,0x47,0xb5,0x47,0x1d,0xa3,0x74,0xff,0xbb,0x4f,0xff,0xd3,0x96,0xef,0x1a,
+  0xb8,0x27,0xc8,0x3f,0x8c,0xf3,0xeb,0xf7,0xf5,0x7f,0xb5,0x6d,0x54,0xeb,0xc3,0x95,
+  0xf8,0x07,0x1b,0xad,0x6b,0xbb,0xfa,0xe2,0x99,0x80,0xbe,0xe5,0x5c,0x38,0xff,0x63,
+  0xd8,0xf1,0x47,0x6d,0xff,0xfc,0xea,0xb3,0x00,0xff,0x74,0x49,0x78,0x18,0xaf,0xd7,
+  0x6a,0x02,0xe7,0x83,0x00,0xfc,0xe3,0x9e,0x7f,0xc1,0xb3,0x7f,0xde,0x38,0xa5,0x3d,
+  0x1c,0x98,0x87,0x0c,0xf1,0x4f,0x97,0xcb,0xff,0x50,0xb4,0x63,0xb6,0x5a,0x89,0x86,
+  0x78,0x42,0x7b,0x05,0xc9,0x42,0x68,0x80,0x7f,0xea,0xa0,0x7f,0xf4,0xf6,0x8d,0xd8,
+  0x38,0x5d,0x0a,0xff,0xd4,0xc9,0x6a,0xbd,0x89,0x84,0x8a,0xff,0x19,0x0b,0xeb,0x7f,
+  0xcf,0x8c,0x19,0x4e,0xfc,0xa1,0x20,0xfe,0xe1,0xcf,0x7b,0x0a,0xe2,0x1f,0x7a,0x10,
+  0x46,0xa7,0xf6,0x70,0x09,0xfc,0xb3,0x89,0xf3,0x3f,0x1d,0xd4,0x28,0xf6,0xdf,0xa6,
+  0x98,0xb7,0xf0,0xbe,0x82,0xff,0x99,0x4f,0xd1,0xce,0xde,0xcc,0x74,0x7c,0x53,0x29,
+  0xfc,0x13,0x0b,0x64,0x7f,0x3a,0xf6,0x27,0x2b,0xe3,0x1f,0x91,0x8f,0x24,0xfc,0x43,
+  0x0e,0xc2,0x60,0x69,0x0e,0x02,0x83,0x90,0xfe,0xaf,0x11,0x04,0xf0,0xcf,0x32,0x91,
+  0x7f,0xd3,0x45,0xfe,0xff,0x7b,0xbb,0x9f,0xff,0x31,0xa8,0x70,0x25,0x16,0x86,0x7f,
+  0x1a,0x6b,0x65,0xfe,0x27,0x67,0xd4,0x7a,0x30,0xa0,0x52,0x8d,0x7f,0x60,0xfd,0xeb,
+  0x30,0x36,0x78,0xfe,0x95,0xe6,0x3f,0xcf,0x67,0xeb,0x77,0xfa,0xf4,0x3c,0xb9,0xe4,
+  0xec,0x3d,0x0a,0x3c,0x13,0x57,0xf6,0x7f,0x61,0x63,0x23,0xf6,0x4f,0xf0,0xfc,0x8b,
+  0x33,0xe0,0xfc,0x0b,0xd0,0xed,0x8e,0xdd,0xfe,0x87,0x9e,0x10,0xda,0x8f,0x7f,0xd8,
+  0xff,0x6f,0xa7,0x84,0x7f,0x50,0xa6,0xd3,0x58,0xd4,0x1b,0xc4,0x3f,0x6f,0x73,0x7e,
+  0xbb,0x1e,0xf9,0xfd,0xb9,0xd3,0x9d,0xa7,0xbd,0x36,0x04,0xff,0xc8,0xfd,0x5f,0x5b,
+  0xac,0x06,0x25,0xfe,0x89,0xb1,0xf5,0x13,0xa2,0xfe,0xb5,0x91,0x8c,0x81,0xb2,0xde,
+  0x1a,0x54,0xf4,0xbf,0x5f,0x06,0xf7,0x8f,0xc4,0xff,0xb4,0xc6,0x36,0xf4,0x45,0xe7,
+  0x7f,0x3e,0x83,0xb0,0x27,0xa9,0xc4,0x3f,0x80,0xff,0x71,0x0d,0x3e,0x8f,0x57,0x7a,
+  0x1f,0x17,0xe7,0x5f,0x2c,0x04,0xf8,0xc7,0x9b,0xf6,0xf3,0x0e,0xed,0xff,0xaa,0x04,
+  0xcf,0xef,0x84,0x38,0xff,0x02,0xd6,0xbf,0x5e,0xf6,0xda,0xbe,0xc4,0xf9,0x17,0x2f,
+  0x07,0xf0,0x0f,0x8e,0xff,0x3f,0x11,0xef,0xfb,0x38,0xfb,0x1c,0x8a,0x07,0xe7,0xfb,
+  0xc1,0xfa,0xd7,0xa8,0x94,0xad,0x26,0xde,0xba,0xb2,0x2d,0x98,0xbf,0x4e,0x09,0xfc,
+  0x63,0xc2,0xf8,0xa3,0x53,0xa3,0xd6,0x13,0x22,0x8a,0xeb,0xff,0x98,0xaf,0xf7,0xeb,
+  0x7f,0xc6,0xab,0x7a,0x5e,0x0b,0xc6,0xab,0xd7,0x6c,0xb6,0x3e,0x55,0x2b,0x55,0x37,
+  0xb2,0x84,0x08,0xba,0xb7,0x04,0xfe,0xf1,0xe9,0x7f,0x68,0x74,0x0d,0xe6,0xf7,0x89,
+  0x12,0xfc,0xcf,0x50,0x7c,0x9f,0xff,0x93,0x7b,0x04,0xfe,0x59,0x6e,0xfa,0xb2,0x5b,
+  0x62,0x76,0x5b,0x9b,0x15,0xe8,0x7f,0x97,0xce,0xbf,0x80,0xf9,0xeb,0x58,0xe5,0x90,
+  0x57,0x7f,0x49,0xaa,0xf1,0x8f,0x2f,0xdf,0x91,0x44,0xa6,0xea,0x7f,0xe7,0xf8,0xa7,
+  0x36,0x90,0xfd,0x2b,0x06,0x02,0x78,0x3b,0x84,0xff,0x21,0x6c,0x98,0x37,0xf6,0x47,
+  0x9e,0xff,0x5c,0xac,0xe0,0xfc,0x8f,0x0f,0xff,0xb8,0x85,0xbf,0x40,0x7e,0xff,0x7e,
+  0x0f,0xff,0x07,0xb4,0x3e,0xb4,0x0b,0x35,0x92,0xf0,0x17,0x6e,0x20,0xf8,0xa7,0x23,
+  0x7c,0x75,0x16,0x32,0x4b,0x19,0xf0,0xaf,0x0f,0x2d,0x47,0x86,0xa5,0x99,0xa5,0x8c,
+  0x6f,0xf2,0xfb,0xe4,0x58,0x33,0x83,0x9d,0x6f,0x16,0x62,0x80,0xbf,0xd2,0x0b,0x5d,
+  0xe3,0x9b,0xfc,0xfe,0xf5,0xfe,0x7d,0xcb,0xfc,0x6f,0x92,0xb3,0xfc,0x4e,0xa0,0xbf,
+  0x44,0x4b,0x9d,0x12,0x86,0xfe,0x7b,0xff,0xfe,0xff,0xb2,0xff,0x75,0xd3,0x8e,0xe0,
+  0xf3,0x18,0x8f,0x3f,0xd7,0xfb,0xd7,0xda,0x1a,0x65,0x55,0x32,0xf9,0x7b,0xfe,0xfc,
+  0xff,0xc1,0x5f,0xfb,0xb5,0x6b,0xd7,0x9c,0x32,0xc6,0xff,0xe7,0xf5,0xdf,0xb2,0xe7,
+  0xf1,0xbb,0x78,0xf8,0x5d,0x3c,0xfc,0x06,0xfe,0xff,0x2e,0x1e,0x96,0xfb,0xfb,0xb6,
+  0xc5,0x9f,0x6f,0xd7,0x7a,0xc8,0x8f,0xc5,0xae,0xd9,0x2d,0xbb,0x12,0x17,0x5d,0xe1,
+  0x74,0x84,0xfa,0xe0,0x82,0xa3,0xf6,0xee,0x62,0xf5,0x90,0x76,0xb5,0x14,0x3f,0x86,
+  0x06,0x12,0x07,0x62,0x19,0xd6,0x76,0x9a,0xf6,0xf4,0x60,0xb1,0x50,0x7e,0xac,0x4e,
+  0x62,0x23,0xd3,0xce,0x02,0x05,0x3f,0x09,0xf4,0x51,0xb1,0x5a,0xf0,0x76,0x70,0x20,
+  0xd6,0xf4,0x8e,0xb2,0x7e,0xb7,0x35,0x96,0xf2,0xd6,0xef,0x42,0x90,0xff,0xa9,0x6c,
+  0xcf,0x7b,0xb0,0xf9,0xf1,0x32,0xfc,0x58,0x0d,0x7d,0x0d,0x89,0xb5,0x4d,0x56,0xe3,
+  0x9f,0x75,0xfc,0xbf,0x7f,0x4e,0x5d,0x1f,0x3c,0x6a,0x65,0x7b,0xb1,0x31,0x17,0x4d,
+  0x1f,0x4e,0x8c,0x6e,0x84,0x8d,0x37,0x4b,0xd5,0x07,0xa5,0xfe,0x38,0xfb,0x47,0x96,
+  0xb2,0x5e,0x26,0xd5,0x07,0xd9,0x7c,0xa4,0x01,0xc2,0x86,0x4d,0x56,0xc3,0xfa,0xa0,
+  0x7e,0x20,0xd6,0xea,0x6c,0x68,0x5a,0x0c,0xf8,0x31,0x5f,0x7f,0x1c,0xd5,0x87,0x07,
+  0xe6,0xc9,0x0b,0x7e,0x8c,0xf0,0xdb,0x1f,0xa0,0x35,0x4e,0xb5,0xeb,0x8d,0xdb,0x89,
+  0x3e,0xff,0x77,0x29,0x3f,0x7f,0x08,0xf8,0x31,0xe9,0xfd,0x14,0xdd,0x86,0xdf,0x77,
+  0xb4,0x13,0x76,0xf8,0xf9,0x68,0x48,0xe6,0xc7,0x56,0x2c,0xa7,0xfa,0x70,0x3f,0x1f,
+  0x08,0xeb,0x83,0xd2,0xfb,0x69,0x43,0x02,0xb6,0xa5,0x84,0xf0,0x63,0xef,0xa3,0x35,
+  0x76,0xb5,0xcb,0x86,0xdd,0x55,0x18,0x28,0xd0,0xf9,0xd8,0x84,0x16,0x8b,0xa9,0xf8,
+  0x31,0xa9,0x3f,0xce,0x0a,0xab,0x0f,0x02,0x7e,0x03,0xb0,0x25,0x77,0x14,0xbc,0xfe,
+  0xf1,0xed,0x01,0x7d,0x14,0x5b,0xcf,0xe7,0x43,0x0e,0x6a,0x53,0xfa,0x70,0x7f,0x7a,
+  0x23,0x65,0xb7,0x5e,0x2c,0x3b,0x1f,0x12,0xcc,0x07,0x48,0x4f,0xd9,0xfe,0xf5,0x82,
+  0x1f,0x23,0xe9,0x54,0x3e,0x0d,0xb6,0x36,0x3d,0x8e,0x9f,0x0a,0x5f,0x7d,0x90,0xcf,
+  0x27,0xd9,0x6c,0xe4,0xe1,0xee,0x9a,0xc9,0x69,0x20,0x44,0x86,0x14,0x3a,0x1f,0x12,
+  0xea,0xc3,0xbf,0x70,0xe7,0x5d,0x07,0xfb,0xe3,0xce,0x48,0xf3,0x91,0xde,0x13,0xfa,
+  0xf0,0xbb,0xac,0xe4,0xcf,0xe2,0xe7,0x52,0xfe,0xfe,0xc1,0x33,0xd2,0x7c,0x6c,0xc0,
+  0x86,0xa5,0xed,0xf5,0x76,0x7c,0x97,0xd6,0x1f,0xca,0x8f,0x59,0xf3,0xc6,0x7d,0xfb,
+  0x5d,0xd4,0x31,0xce,0xc6,0x62,0x83,0xf3,0x61,0x99,0xff,0x77,0xca,0xf3,0x21,0xe9,
+  0xf9,0x74,0x7b,0xd0,0x82,0xf0,0xfa,0x60,0x1d,0xb8,0xfe,0x2f,0xd0,0x9d,0x54,0x0f,
+  0xaf,0xaf,0xd3,0xe4,0x7e,0x37,0x50,0x1f,0x8c,0xed,0x91,0x4e,0x8f,0xfd,0xb3,0xa4,
+  0x98,0x8f,0xcd,0xd7,0xcf,0x07,0xf5,0x41,0xa9,0x3f,0x2e,0x45,0x8d,0xe0,0x7c,0x4e,
+  0xc8,0x8f,0xed,0x05,0xf5,0xc1,0x42,0xd6,0x5e,0x5f,0xd0,0xee,0x4a,0x85,0xd7,0x07,
+  0x1b,0xfb,0xb8,0x5e,0x37,0x41,0xe6,0xb3,0xe5,0xb1,0x91,0xb4,0x79,0x47,0x4f,0x80,
+  0x1f,0x5b,0x8e,0x64,0x99,0x50,0x2e,0xfe,0x63,0x85,0x70,0x48,0xf0,0x63,0x8d,0x62,
+  0x3e,0xd2,0x0b,0x3a,0x19,0x8b,0x34,0xff,0xe2,0xb6,0x1b,0x02,0xfa,0x28,0xc0,0x8f,
+  0x2d,0x05,0xf1,0xfc,0x32,0xf1,0xc6,0xf0,0xfa,0x52,0xf5,0x41,0x0b,0xd6,0x77,0xce,
+  0xdb,0xab,0xf3,0x03,0x17,0xef,0x29,0xc9,0x8f,0x49,0xf3,0x91,0x2c,0x1a,0x7f,0x4c,
+  0x7c,0xd9,0x77,0xb8,0x9f,0x7c,0xc5,0xf4,0x51,0xfc,0x79,0xb4,0x25,0x3d,0xc3,0xcd,
+  0xe3,0x0b,0x7a,0x14,0xe7,0x83,0x8c,0xf3,0xfa,0x20,0x99,0x0f,0xd9,0xc2,0xa2,0xcd,
+  0x6a,0xb4,0xb1,0x07,0xc7,0x1f,0x84,0xfc,0xfe,0x04,0xf5,0x41,0x2f,0x7f,0x55,0x91,
+  0x63,0xc8,0x2e,0xa3,0x35,0xf9,0xea,0xd9,0x2a,0xc3,0xbf,0x5f,0x0d,0xce,0x87,0x14,
+  0xfe,0x21,0x07,0xcb,0x76,0x61,0xe3,0x53,0xb1,0x9e,0x29,0x88,0x02,0xf5,0xc1,0x9a,
+  0x59,0x7a,0x1e,0x68,0xcb,0xbd,0xd5,0xee,0xa0,0x6c,0x39,0x9e,0x4f,0x81,0xfa,0x20,
+  0xc8,0x5f,0xc3,0x76,0xca,0x32,0x86,0xb4,0x4f,0x03,0xe7,0x73,0x85,0xf1,0x63,0x5b,
+  0x1f,0x71,0x6e,0x1c,0xd2,0x7e,0x87,0xfc,0xf5,0x20,0xc0,0x8f,0x41,0x3d,0xcc,0x01,
+  0xed,0x11,0x6b,0x27,0x19,0x94,0xed,0x8b,0xcf,0xb0,0x3e,0xe8,0xd7,0x87,0x57,0xf7,
+  0xe0,0xc7,0xc4,0x9f,0x5f,0x8a,0x1c,0x72,0x4b,0xfd,0x71,0xf4,0x7c,0xc6,0xd9,0xe0,
+  0xf9,0x56,0xf3,0x45,0x7d,0x70,0x0c,0xde,0x3f,0x5f,0xd9,0xed,0x4e,0xa6,0x93,0xd6,
+  0x07,0x6f,0x7b,0x5d,0xc2,0x3f,0xfc,0x3c,0x91,0x31,0x43,0x56,0x43,0xf5,0x54,0xf7,
+  0x57,0x66,0x0a,0x47,0xed,0x15,0xb3,0x6a,0xfc,0x33,0x81,0xa4,0x7c,0xd4,0x78,0x2f,
+  0xa9,0x0f,0xe2,0xe7,0xab,0x61,0x32,0x44,0x1f,0xa5,0xb3,0xfa,0x20,0x39,0x66,0x4e,
+  0xcb,0x76,0x78,0xf5,0xc1,0x74,0x48,0x7d,0x70,0xa1,0xa4,0xcf,0x41,0xad,0xa6,0x31,
+  0x20,0xc6,0x86,0x2b,0xf4,0x51,0x85,0x85,0xfc,0xfc,0x0b,0x5a,0x1f,0x84,0xf3,0xa3,
+  0xb4,0x92,0xf5,0x41,0x6d,0x46,0x27,0xf3,0x19,0xa8,0xfe,0xfc,0x0d,0xa3,0xed,0x15,
+  0x08,0xb4,0xe4,0xf9,0x90,0xa0,0x5f,0x20,0x3d,0x61,0x2c,0xc0,0xd7,0xbf,0xa2,0x73,
+  0xd5,0xa9,0x6a,0xa5,0x3e,0xaa,0x28,0xdd,0x0f,0xa8,0xc1,0xe9,0x6c,0xc4,0xc6,0x62,
+  0x27,0x83,0x81,0xe2,0xa2,0xae,0x20,0xfe,0x99,0x35,0x21,0xfe,0xe9,0xdf,0x95,0x37,
+  0xa6,0x9f,0x74,0xeb,0x65,0x0b,0x94,0xf8,0x67,0x53,0xbd,0xa7,0x8f,0x5a,0x8d,0x61,
+  0xcf,0x01,0xb3,0xc9,0xca,0x34,0xe0,0xcb,0x26,0xfd,0x71,0x09,0x01,0x84,0x34,0x70,
+  0x3e,0x6c,0xad,0x8c,0x7f,0x2c,0x7a,0x90,0xee,0x7f,0xa3,0xf6,0x71,0x09,0xff,0xcc,
+  0x63,0xfb,0x35,0x74,0x89,0x9d,0x7e,0xcc,0x62,0x83,0x92,0x26,0x13,0x4a,0xfc,0x73,
+  0xc2,0xf0,0xf5,0xdb,0x26,0xac,0x38,0xf9,0x24,0x73,0xc2,0xe8,0xe9,0x60,0xf1,0x24,
+  0xbe,0x1f,0xd6,0x07,0x4d,0x88,0xee,0x66,0xd7,0x6d,0x4e,0x53,0x63,0xca,0x50,0xe2,
+  0x9f,0x2e,0x5d,0xee,0x3e,0x98,0x6c,0x6c,0xd5,0xf6,0xd1,0x4f,0x0c,0x35,0xfe,0xd1,
+  0x65,0x7d,0x78,0xa1,0xfa,0x23,0x6a,0xb4,0xda,0x99,0x08,0xfa,0x28,0x72,0x50,0xd1,
+  0x56,0x05,0x10,0x7a,0x46,0x5d,0x1f,0xfc,0x14,0xb5,0x6e,0xca,0xfc,0x43,0xdc,0x1d,
+  0x0b,0x59,0x13,0xa9,0x3e,0x98,0x33,0x76,0x6a,0x53,0xc6,0x76,0x74,0xe7,0xfd,0x86,
+  0x84,0x7f,0xd8,0x1f,0xab,0x0f,0xba,0xf3,0xb1,0x2d,0xbc,0x9e,0x0e,0x8a,0x5c,0x4b,
+  0x85,0xcd,0x0a,0xfc,0x93,0x82,0xf5,0x41,0x32,0x16,0xc0,0x20,0x63,0x01,0xb6,0x22,
+  0x7a,0x50,0x91,0xa2,0x3e,0xb8,0xf9,0x26,0xb6,0x29,0xaa,0xbe,0x5e,0x46,0xfb,0xd3,
+  0xe9,0x7c,0x00,0xd8,0xa8,0x75,0x66,0xbe,0x52,0x1f,0x75,0xc9,0x1d,0x44,0x46,0xc7,
+  0x1e,0xc2,0x46,0xb9,0xc5,0x50,0x1f,0x45,0x3e,0x5c,0xe3,0x76,0xd3,0xe3,0xf8,0xfc,
+  0x48,0x82,0x08,0xcb,0xdf,0x44,0xed,0xf7,0x25,0x94,0xf8,0xa7,0x1e,0x81,0xfe,0xb8,
+  0x8b,0x68,0x8d,0x99,0x29,0x68,0x45,0x32,0x16,0xd2,0x34,0xd4,0xf5,0x41,0x24,0xd5,
+  0x07,0x53,0x79,0x7c,0x1b,0x8c,0xd3,0xb1,0x90,0x86,0x1a,0xff,0xd4,0x8a,0xfe,0x38,
+  0x0c,0x3b,0x2b,0xf2,0xd8,0x9f,0xe3,0xda,0x76,0x24,0x0b,0xd5,0x64,0x7d,0xd4,0x08,
+  0xbd,0x48,0xfa,0x6d,0xb3,0xd5,0xba,0xd3,0xfb,0xff,0xcd,0x28,0xf1,0xcf,0x84,0xbf,
+  0x5e,0x5c,0xf3,0x8f,0x9e,0x11,0x5e,0x1f,0x9c,0x66,0xf8,0x67,0x1a,0xe3,0x9f,0x95,
+  0xb4,0x3e,0x68,0xb4,0x19,0x19,0x25,0xfe,0x91,0xf4,0x51,0x87,0x9c,0x55,0xcf,0x19,
+  0x64,0x3e,0xe4,0x68,0x6a,0xd5,0xa0,0xa1,0xd6,0x47,0xe9,0x72,0xf5,0xbc,0x68,0x34,
+  0x3d,0x89,0x0d,0x87,0x18,0xde,0x8b,0xc3,0xfa,0xa6,0xb4,0xc0,0x3f,0xc8,0x04,0xd5,
+  0xb1,0x83,0xd6,0xca,0x31,0x23,0x97,0x3a,0x6d,0x1f,0x44,0x2b,0x7b,0x81,0x50,0x6a,
+  0x91,0xc0,0x3f,0xc6,0xce,0x87,0x05,0xda,0xf9,0x2f,0x57,0x16,0xf5,0x1b,0xe7,0x82,
+  0xdd,0x5a,0x4c,0xa8,0xf1,0x4f,0xdd,0x3e,0x31,0x5d,0xf6,0x22,0x89,0x4e,0x83,0xd4,
+  0x58,0x63,0x87,0xe8,0xa3,0xfa,0x46,0x4d,0x6f,0x9a,0x0d,0xed,0x6f,0x2a,0x24,0x26,
+  0x68,0xda,0x6a,0x29,0xe8,0x6e,0xfe,0xba,0x8b,0xe2,0x1f,0x51,0x8f,0xf3,0xc5,0x1f,
+  0xbb,0x3a,0x47,0x81,0xcd,0x0f,0x4c,0x03,0x54,0x0c,0x85,0x3e,0xca,0x5f,0x1f,0x1c,
+  0x34,0xf2,0x9a,0x3b,0xd8,0x7f,0x81,0xb2,0x3e,0x68,0xf9,0xe2,0x8f,0xdd,0x48,0x07,
+  0xb5,0xa1,0x46,0xf4,0x83,0x10,0x7d,0x14,0x17,0x75,0xd3,0xfc,0xe5,0x18,0x36,0x0e,
+  0xb3,0x97,0xf1,0x8d,0xe4,0xbd,0x51,0x52,0xe9,0xc5,0x84,0xe8,0x47,0x58,0x08,0xfb,
+  0x07,0xc9,0xc1,0x9d,0x7d,0x54,0x28,0x85,0xe3,0xc9,0x50,0x4c,0xd4,0x07,0xf9,0xfd,
+  0xbf,0x9c,0xe2,0x1f,0x6f,0x3e,0x00,0x99,0x97,0x98,0x20,0xf9,0xee,0xa4,0xdd,0x96,
+  0x8f,0x50,0x1f,0x24,0xe7,0xb9,0x37,0x3e,0x85,0x8d,0x5f,0xe4,0xb3,0x79,0x50,0x1f,
+  0x5c,0x04,0xf1,0x4f,0xb7,0x09,0xdf,0xee,0x0b,0xf7,0xf5,0x6b,0x03,0xa8,0x3f,0x95,
+  0xed,0x8f,0xa4,0x8f,0xca,0xa6,0xfa,0x51,0xc5,0x09,0xf2,0xfe,0x85,0xfe,0x54,0x5d,
+  0x1f,0x84,0xfa,0x28,0x52,0x1f,0xac,0x20,0xfe,0x99,0x08,0xaf,0x0f,0xfe,0x5c,0xaa,
+  0x06,0xde,0xed,0x54,0x93,0xfd,0x9e,0xf7,0x09,0xa5,0x44,0x7d,0xd0,0x79,0x42,0xd6,
+  0x47,0xa5,0xca,0xcc,0x87,0x1c,0x93,0xf5,0x51,0xd9,0x14,0x19,0xe4,0x18,0xe4,0x7f,
+  0xf8,0x7c,0xda,0xe3,0x68,0xc0,0x84,0xf7,0x03,0x52,0xea,0x75,0x05,0xfe,0x29,0x72,
+  0xfc,0xe3,0x7a,0x0f,0xa9,0xe7,0x43,0xf2,0xfc,0xb8,0xd6,0xa7,0x8f,0xba,0x41,0xa9,
+  0x97,0x0b,0x9f,0x8f,0x6d,0xab,0xf5,0x63,0xa1,0xf3,0x91,0x72,0xca,0xdf,0x0f,0xc3,
+  0x3f,0x66,0xc8,0x7c,0x48,0x81,0x7f,0x26,0xa4,0xf8,0x63,0xca,0x6e,0x01,0xfd,0x71,
+  0xec,0x7e,0x9b,0x95,0xf4,0x51,0x4f,0xc8,0x34,0x88,0xc0,0x3f,0x7c,0x3e,0x76,0xa7,
+  0xd1,0x65,0x09,0x35,0x78,0xaa,0xd5,0x56,0xce,0x87,0x7c,0x5f,0xcc,0xc7,0xae,0xfb,
+  0xa5,0x59,0xde,0x3f,0x62,0x3e,0x76,0x23,0xc4,0x3f,0x5f,0xda,0x4d,0x84,0xff,0x39,
+  0x13,0xc0,0xe7,0x80,0xff,0xa9,0x0f,0xf2,0x3f,0x73,0xe8,0x3f,0xfc,0xfc,0x8f,0xd0,
+  0x3f,0xf8,0xf8,0x9f,0x7c,0x19,0xfe,0x67,0x93,0x1c,0x7f,0x1a,0x66,0x29,0xff,0xe3,
+  0x9f,0xb7,0x20,0xfa,0xd7,0xa6,0xeb,0x24,0x35,0x78,0xcb,0x9e,0x84,0xe0,0x7f,0x60,
+  0x7f,0x1c,0xbb,0xfe,0xce,0x98,0x8c,0x7f,0xf4,0x10,0x7d,0x38,0xbb,0x7e,0xbf,0x3e,
+  0x5c,0xad,0x7f,0x0e,0xc3,0x3f,0x76,0x56,0xad,0x4f,0x16,0xfc,0x4f,0x40,0x1f,0xa5,
+  0x34,0x4e,0xaa,0xf1,0xcf,0xb0,0x2d,0x8f,0x45,0xe2,0x78,0x40,0xcc,0xc7,0xde,0xec,
+  0x9f,0x0f,0x10,0xb5,0x3f,0x8e,0xd0,0x20,0xb4,0x3f,0x4e,0xb1,0xdf,0x15,0xca,0xf9,
+  0xd8,0x04,0xff,0x78,0x86,0x9f,0xff,0x01,0xfd,0x71,0xf5,0x41,0x35,0x78,0x91,0xcd,
+  0x47,0x12,0xf3,0x01,0x2a,0x42,0xf0,0x8f,0x6b,0x14,0x4a,0xf0,0x3f,0xfa,0x1e,0xbf,
+  0xf7,0xd2,0xe3,0x81,0xf9,0x48,0xd2,0x7c,0x6c,0x43,0xe8,0xc3,0xf9,0xf5,0xfb,0xf9,
+  0x1f,0xbe,0x5f,0xa2,0x8f,0x1a,0x41,0x21,0xb7,0x01,0xe7,0x7f,0xce,0x82,0xfb,0x07,
+  0xf0,0x3f,0xd3,0x7c,0x50,0xa4,0xcf,0xff,0x21,0xf3,0xb1,0x47,0x7d,0xb4,0x0f,0x33,
+  0xee,0x07,0xfd,0x71,0x22,0xfe,0x0c,0xa0,0x5d,0x34,0xfe,0x54,0xb8,0x13,0x5d,0x3c,
+  0xbd,0x4a,0xb7,0x23,0xe9,0xc3,0x6d,0x88,0x7f,0x5e,0xa2,0x46,0xfa,0xb4,0xfd,0xf7,
+  0xbe,0xe7,0x57,0xf4,0x43,0xf5,0xf7,0x3f,0xcc,0xf9,0x1f,0xf4,0x09,0x1b,0x94,0xed,
+  0xe7,0x7f,0xc0,0x7c,0xec,0x3a,0x39,0xbf,0x93,0x6c,0x0e,0xe2,0xed,0x07,0xac,0xdf,
+  0x84,0xc7,0x07,0xa8,0x0f,0xbf,0x32,0xd8,0x5e,0xac,0xb9,0x18,0xbf,0x06,0xf3,0xd7,
+  0xaa,0xa9,0xe4,0x25,0x38,0x1f,0xdb,0x00,0xfc,0xcf,0x21,0xb4,0xf2,0x35,0x02,0x7b,
+  0x82,0xe7,0x83,0x88,0xf9,0xd8,0x82,0xff,0x79,0x1e,0xc3,0xa4,0x3f,0x97,0x64,0x60,
+  0xae,0xb1,0xbe,0x27,0x0d,0xe7,0x03,0x80,0xf8,0x33,0xec,0x7b,0xed,0x02,0xfd,0x71,
+  0xfc,0x7a,0x44,0xfe,0xda,0x47,0xf6,0x5b,0xac,0x01,0x63,0x91,0x54,0xf3,0x01,0x62,
+  0x92,0x7e,0x3e,0xa4,0x5f,0xac,0xe8,0xc3,0x3f,0x5e,0xf4,0x9e,0x0b,0x9b,0x0f,0x29,
+  0xe6,0x63,0xef,0x42,0x0c,0xff,0xe0,0xeb,0x19,0xb2,0x6e,0x55,0xe7,0xaf,0x90,0xf9,
+  0xd8,0x23,0x46,0xd9,0xf9,0x90,0x95,0x3a,0xe8,0x8f,0xdb,0xef,0xa3,0xc5,0x04,0xfe,
+  0x11,0xf3,0xb1,0x6f,0xea,0x86,0xfb,0xa5,0xf3,0x21,0x83,0xfe,0x71,0x56,0x70,0xfc,
+  0xf3,0xcf,0x7c,0x53,0xe4,0x7c,0xd8,0xbb,0x95,0xfb,0xfd,0x63,0xf1,0x3c,0xfe,0x0f,
+  0x7b,0xd7,0x1e,0x1c,0xc5,0x71,0xe6,0x7b,0x1e,0x2b,0x8d,0xb4,0x2b,0x34,0x7a,0x2c,
+  0xac,0x1d,0x20,0xa3,0x07,0xa0,0x73,0x84,0x58,0x0b,0xbf,0x72,0x70,0x30,0x5a,0x01,
+  0x11,0x8f,0x98,0x8d,0xc1,0xa0,0xa4,0x54,0x57,0x63,0x17,0x55,0xf1,0x1f,0x9c,0x4b,
+  0x38,0x57,0x17,0xe7,0x1e,0x76,0xaf,0x1e,0x80,0x2d,0xe7,0xbc,0xc1,0x9c,0xad,0x3b,
+  0x53,0x75,0x22,0x21,0x39,0xd7,0x95,0xcf,0x07,0xc4,0x0f,0xce,0x76,0xd9,0x23,0x59,
+  0x38,0x32,0xa7,0xc3,0x9c,0x8f,0x72,0x11,0x9b,0x32,0xb2,0x8b,0x4a,0x54,0x65,0xfb,
+  0xac,0xe3,0xc8,0x19,0x12,0x1b,0xae,0x7b,0x5e,0xdd,0x33,0xd3,0xbd,0x3b,0x6b,0xec,
+  0x4b,0x72,0xf6,0xfe,0xf5,0x63,0xb6,0x19,0x75,0x7f,0xdb,0xf3,0xf5,0x6f,0xbe,0xa7,
+  0x59,0x15,0x66,0x3b,0x05,0xf3,0xe3,0xc0,0x13,0x72,0x90,0xed,0x14,0xac,0x8f,0x24,
+  0x4f,0x86,0xac,0x7f,0x36,0x78,0xd4,0xc7,0xf7,0x98,0xf9,0x71,0x5c,0xe0,0xeb,0x8f,
+  0xa6,0x04,0xa4,0xd1,0xe4,0x02,0x52,0x38,0xcb,0xf4,0xd5,0x07,0x78,0xd1,0x2f,0x0d,
+  0x31,0xbc,0x1f,0x0a,0xd7,0x87,0x0c,0x83,0x42,0xf5,0x21,0x83,0x60,0xb4,0x50,0x7d,
+  0x48,0x47,0x50,0xc4,0x22,0xed,0xf2,0x1f,0xf7,0xf7,0x0d,0xf8,0xbf,0x58,0xe0,0x4b,
+  0x9c,0xfe,0xb0,0x7e,0xda,0x33,0xce,0xa9,0x0f,0x99,0x7c,0x3e,0x24,0x0d,0xaa,0xc2,
+  0x7c,0xe1,0xfa,0x48,0xb8,0x2c,0xc3,0x2e,0x96,0x7c,0xb8,0xfd,0xd1,0x22,0xd6,0xc7,
+  0xa6,0x56,0xb7,0xde,0xb2,0xff,0x44,0xa8,0x0f,0xc9,0x78,0xac,0x8a,0xd7,0x07,0xe0,
+  0x00,0x5e,0x7d,0x48,0x1e,0x28,0x54,0x1f,0x80,0xcd,0x7f,0xdc,0xf1,0xe1,0xfa,0x00,
+  0xa5,0xd5,0x47,0x2a,0xad,0x3e,0x76,0x84,0xfa,0x00,0x91,0xf8,0x0f,0xc7,0xff,0xc5,
+  0x03,0x9d,0xdc,0xfa,0x90,0x14,0xa0,0xeb,0x2b,0xf2,0xfa,0xa3,0xf1,0x00,0xab,0x3e,
+  0x92,0xb3,0xba,0x47,0xd9,0xeb,0xf5,0xe6,0x13,0xea,0x8f,0x16,0x00,0xb3,0x02,0xf5,
+  0x91,0x82,0xfd,0xd1,0x82,0xf3,0x9f,0x6f,0xf3,0x1f,0x77,0x7f,0xfa,0xfb,0xa3,0xf1,
+  0x00,0xb1,0x3f,0x14,0xad,0x0f,0x70,0x03,0xa7,0x3f,0x1a,0x2b,0x2d,0x8e,0xaa,0x0f,
+  0xe0,0x7e,0xc2,0xf5,0x01,0x02,0xc0,0xaa,0x57,0x43,0xea,0x63,0x6b,0x42,0xd8,0xdb,
+  0x15,0x06,0x94,0xff,0x4b,0x99,0x5f,0xc1,0x2d,0x0b,0x80,0xc1,0xf5,0x08,0x34,0x1d,
+  0xe3,0xd5,0x07,0xb8,0x87,0xad,0x6f,0x29,0xff,0x57,0x32,0xca,0xf9,0x75,0x82,0xd4,
+  0x47,0xba,0x8a,0xd2,0x3f,0xbf,0xa4,0x0a,0xd5,0x8e,0xf3,0xeb,0x63,0x17,0x5f,0x2f,
+  0xe5,0xff,0x92,0x29,0xe9,0x05,0xdd,0xee,0x93,0x4e,0x04,0x3e,0x65,0x7f,0x6e,0x09,
+  0xd5,0x87,0x0c,0x82,0xd1,0x8d,0x07,0xeb,0x8e,0xb1,0xeb,0x23,0xf9,0xf2,0xe5,0x37,
+  0x52,0xff,0x91,0xd1,0x1f,0x2d,0x44,0x03,0xbe,0x4c,0xae,0xd4,0x11,0xfb,0x0f,0xae,
+  0x0f,0xb0,0x8c,0x79,0x7e,0x49,0x1c,0xff,0xd7,0x76,0xf0,0x68,0xa1,0xf3,0x6e,0x56,
+  0xc0,0xfe,0x03,0xc2,0xd9,0x61,0x0c,0xfe,0x43,0xec,0x3f,0x4a,0x38,0x5a,0xfe,0xbd,
+  0x70,0x7c,0xb8,0xe8,0xf1,0x9f,0x79,0xbc,0xf5,0x7a,0xe0,0xc1,0x19,0x69,0xba,0x9c,
+  0x97,0x1f,0x17,0xb9,0x3f,0x48,0x54,0xfe,0xc3,0xa8,0x8f,0xcd,0x5a,0xef,0x15,0xf0,
+  0x9f,0x08,0xfc,0x64,0x82,0x57,0x1f,0x9b,0x03,0x3e,0x4b,0xfe,0x53,0xa0,0x3e,0x24,
+  0x17,0xcc,0x94,0xc2,0x7f,0xf8,0xf5,0x21,0xb9,0xe0,0x8d,0x02,0xf5,0xb1,0x99,0xf6,
+  0x1f,0x9a,0xff,0x84,0xba,0xf5,0x7d,0x9a,0xfc,0x67,0x14,0x44,0x59,0x2f,0xc5,0x7f,
+  0xf6,0x7e,0xbe,0xf9,0x0f,0xa7,0x9f,0xc5,0x27,0xe6,0x3f,0x47,0xfc,0xfc,0x67,0xfe,
+  0xa7,0xc2,0x7f,0xa8,0xfa,0x48,0xc3,0x5c,0xfe,0x53,0xfd,0xa9,0xf0,0x1f,0x10,0xe4,
+  0x3f,0xc5,0xfa,0x83,0xd4,0x14,0xe1,0x3f,0xc1,0xfe,0xb0,0xc9,0x28,0xf3,0xa7,0xf8,
+  0x8f,0xf0,0x29,0xf3,0x9f,0xc8,0xf9,0x71,0x9f,0x90,0xff,0xb4,0xfa,0xed,0x3f,0xfb,
+  0x69,0xfe,0x13,0x0c,0xdb,0x63,0xf0,0x1f,0x5f,0x7d,0x48,0x2e,0xe0,0xf2,0x1f,0x0e,
+  0x20,0xfc,0xc7,0xa4,0xfa,0xa3,0x45,0xe2,0x3f,0x91,0xf4,0x0f,0xe1,0x3f,0xaa,0xdb,
+  0x1f,0xb6,0x30,0xff,0xf1,0x7e,0x2f,0x23,0xd2,0xfb,0x17,0xe1,0x3f,0x46,0x98,0xff,
+  0x88,0xe1,0xf5,0x1e,0xf7,0xe6,0x33,0xc0,0xc8,0x8f,0xa3,0x81,0x1c,0xb0,0xff,0x98,
+  0x5c,0xfe,0xe3,0xf3,0x7f,0x6d,0xa3,0xf9,0x4f,0xf1,0xf3,0xab,0x40,0x7e,0x5c,0x18,
+  0xac,0x3f,0x58,0xcb,0x8b,0xff,0xe1,0xf2,0x01,0x6f,0x7f,0xc2,0x2a,0x1e,0xff,0x89,
+  0x10,0xff,0xc3,0x03,0x75,0xd3,0x22,0xc5,0x7f,0x14,0x7b,0x93,0x74,0xd2,0x81,0x40,
+  0xda,0xd2,0xf1,0x04,0x93,0xff,0x8c,0x0d,0x33,0x69,0x8f,0xd9,0x74,0x42,0xe1,0xf9,
+  0xbf,0x58,0xcb,0xd4,0xb5,0x6e,0xda,0x30,0xc8,0x8a,0xff,0xf1,0x8b,0xf1,0x87,0x3a,
+  0x5d,0x68,0x88,0xef,0xff,0xb2,0xc1,0x7f,0x83,0x5e,0x9d,0x2e,0xa4,0xf9,0xef,0x45,
+  0xfb,0xc3,0xae,0xf0,0xfb,0x07,0x8b,0xf2,0x9f,0x76,0x93,0x8e,0x6f,0x99,0x09,0xf9,
+  0xbf,0x24,0xdf,0xfc,0x5f,0x1c,0x69,0x7f,0x9d,0x9e,0x3f,0x5d,0x1f,0x89,0xa9,0x7f,
+  0xa0,0x36,0x45,0xcb,0x87,0xf4,0x87,0xbd,0x10,0xa8,0x0f,0xe0,0x82,0xfd,0x53,0x74,
+  0x3c,0x8c,0xcf,0xff,0xe5,0x06,0xf9,0xf8,0x68,0x4f,0xda,0x2e,0x94,0xed,0xd9,0x7f,
+  0x28,0xff,0x17,0x53,0x3e,0xcb,0x7c,0xfe,0x62,0xe2,0xff,0x0a,0xc4,0xff,0x38,0xe0,
+  0x43,0xd0,0xde,0xed,0xd3,0x57,0x5e,0xfd,0xcf,0xc9,0x14,0x53,0xff,0xc0,0x86,0x8c,
+  0xdf,0xff,0xe5,0xca,0x33,0x54,0x1f,0x80,0x34,0x8a,0x65,0xfa,0xbf,0xb6,0xcb,0xcc,
+  0xfd,0x06,0x1a,0xcf,0xfa,0xf4,0x0f,0xcf,0xff,0xe5,0x80,0x73,0x80,0x34,0x8a,0xcd,
+  0x15,0xf4,0x7f,0xb9,0xe0,0x85,0x48,0xfe,0x2f,0x0f,0xe4,0xdb,0x75,0x2a,0xbe,0xa5,
+  0xbc,0x40,0x7d,0x00,0x07,0x88,0x77,0xb7,0x94,0xe2,0xff,0xd2,0x17,0xfa,0x0a,0x65,
+  0xf3,0xfc,0x5f,0x04,0x34,0x3b,0x85,0xb2,0x25,0xab,0x94,0x74,0x71,0xff,0xd7,0xd3,
+  0x76,0x20,0x90,0x13,0x1a,0xc4,0xf6,0x7f,0x51,0x40,0x5f,0xe6,0x2b,0x94,0x4d,0xf9,
+  0xbf,0xa8,0xf1,0x2a,0x71,0x84,0xc1,0x95,0xbd,0x74,0xfc,0x0f,0xb3,0x3e,0xa4,0xe1,
+  0xa3,0x3d,0x5a,0x4b,0x74,0xff,0x17,0x38,0x14,0x28,0x0c,0xc5,0x8c,0xff,0xf1,0xff,
+  0x10,0xe3,0x0a,0xdb,0xff,0xc5,0xe3,0x6f,0x86,0x2f,0xfe,0x87,0xf8,0xbf,0x6a,0xd8,
+  0xfc,0x67,0xf9,0xed,0x4b,0xa8,0x2b,0x4c,0xff,0x57,0x80,0xf6,0xd0,0xf1,0x3f,0x2c,
+  0xff,0x17,0xa0,0x68,0xcf,0x0b,0xea,0x92,0x7c,0x0b,0xbb,0x3e,0xa4,0xa7,0x7f,0x74,
+  0x9f,0x7e,0x6e,0x9d,0xa1,0xf5,0x0f,0xc7,0xff,0x45,0x80,0xb2,0x38,0xdb,0xc2,0xf3,
+  0x7f,0x31,0x69,0xcf,0xf2,0xa9,0x56,0xae,0xff,0xeb,0x2f,0x02,0xa7,0xb9,0xa5,0x46,
+  0x74,0x9f,0x3e,0x21,0xef,0xbf,0x7b,0x5f,0x08,0x55,0x33,0xbe,0x04,0x2e,0xc1,0x9f,
+  0x4e,0xd1,0xe7,0x97,0x49,0xf8,0xa7,0x9d,0x7f,0x31,0xea,0x9f,0xff,0xd3,0xa0,0x69,
+  0x55,0x8b,0x8f,0xff,0xb8,0xe3,0xd9,0xf6,0x9f,0xa7,0x41,0x83,0x4e,0x17,0x86,0xa2,
+  0xeb,0x43,0xb2,0xf4,0xcf,0x61,0x2f,0xf1,0xc7,0xbe,0xf2,0x0a,0x55,0x1f,0x20,0xe4,
+  0xbf,0x60,0x9c,0x2f,0x1c,0xff,0x17,0xed,0x28,0xf4,0x05,0x66,0x70,0xfc,0x5f,0xa4,
+  0x50,0x92,0x89,0x0b,0x05,0x30,0xfd,0x5f,0x4c,0xfe,0xf3,0x2f,0x46,0x5b,0x96,0x3e,
+  0xbf,0x38,0xfe,0x2f,0x0f,0xa0,0x6d,0x66,0xd2,0xe3,0xa9,0xfa,0xd8,0xe1,0xfa,0x00,
+  0x96,0x7c,0x5a,0x75,0xaa,0x90,0x78,0x86,0xf2,0x7f,0xf1,0xf8,0x0f,0xa0,0xe5,0x43,
+  0xea,0x43,0xee,0x0f,0xd6,0x07,0xb0,0x03,0xa1,0x85,0x60,0x3d,0x28,0x86,0xfd,0xe7,
+  0x9e,0xdf,0x47,0xfb,0x4f,0xb0,0x3e,0x12,0x1b,0x70,0xfb,0xa3,0xfd,0x5f,0xd9,0x7f,
+  0xe4,0x2b,0xb3,0xff,0x14,0xf7,0x7f,0x55,0x5d,0x91,0xfd,0xa7,0x50,0x7f,0xb4,0xa2,
+  0xf6,0x9f,0x08,0xf2,0xf9,0x14,0xfd,0x5f,0xd1,0xfa,0xc3,0x7e,0x6e,0xed,0x3f,0xbf,
+  0x1d,0xff,0x57,0xe1,0xfe,0x68,0x85,0xec,0x3f,0x7c,0xff,0x17,0x27,0xfe,0xe7,0x4a,
+  0xfd,0x5f,0xd1,0xfa,0xc3,0x46,0xb6,0xff,0x90,0xfa,0x48,0x62,0x41,0xfb,0x8f,0x67,
+  0x7f,0x88,0x68,0xff,0x71,0xef,0x7f,0x85,0xf5,0xb1,0xb9,0xf6,0x1f,0xdd,0x1b,0x5f,
+  0x9a,0xfd,0x27,0xd8,0x1f,0x8d,0x0d,0x38,0xfd,0x41,0x4a,0xaf,0x8f,0x5d,0xd4,0xfe,
+  0x13,0xee,0x8f,0x16,0xb1,0x3f,0x6c,0x44,0xfb,0x0f,0x9b,0xff,0x04,0xe3,0x9d,0x0a,
+  0xf5,0x47,0x63,0x01,0x56,0x7f,0x34,0x91,0x0a,0x84,0x7e,0x33,0xa8,0x3f,0x0b,0xf4,
+  0x47,0x23,0xa0,0x9c,0xc1,0x7f,0x28,0xff,0x57,0x81,0xc0,0x06,0x7e,0x7f,0xb4,0x12,
+  0xed,0x3f,0x9c,0x78,0x21,0x7e,0x7f,0x34,0xdc,0xbf,0x32,0x20,0x1f,0x89,0x5b,0x1f,
+  0x29,0xd8,0x36,0x97,0xc1,0x7f,0x22,0xd9,0x7f,0xf8,0xfd,0x61,0x09,0xd8,0x96,0x38,
+  0x4f,0x0a,0x45,0x06,0xf9,0xcf,0x2c,0x1f,0xdb,0xb9,0x13,0x3c,0xd7,0x77,0x27,0x54,
+  0x7e,0x4c,0x1a,0x85,0x14,0xe3,0x3f,0x3f,0xc2,0xf9,0x14,0xb5,0x5e,0xa3,0x90,0x4c,
+  0x61,0xfe,0x63,0xfd,0x22,0x3b,0x5b,0xf2,0xa4,0x51,0x48,0x71,0xfe,0xd3,0x06,0x13,
+  0x0f,0xc5,0xbd,0x47,0xa9,0x28,0xff,0x91,0x57,0xc2,0xea,0xee,0xf8,0x5f,0x96,0xc0,
+  0x7f,0x54,0xc4,0x3f,0x5b,0xd5,0xa8,0xfc,0x07,0xbd,0xad,0x29,0x07,0x2b,0xed,0xaf,
+  0x86,0xa2,0xf1,0x1f,0x45,0xad,0x2c,0x21,0xfe,0x67,0xc9,0x54,0xcb,0x37,0x49,0xe3,
+  0x8c,0x53,0xaa,0x7b,0x7f,0x3e,0xff,0x49,0x1c,0x8c,0x27,0xa2,0xf3,0x1f,0x7f,0x20,
+  0x59,0x14,0xfe,0x93,0xc8,0xc7,0x5b,0x4b,0xe1,0x3f,0x4a,0xd6,0x4b,0xa4,0x6d,0x64,
+  0xf3,0x9f,0x94,0x6f,0xbd,0x95,0xcb,0xc9,0x7a,0x23,0xf0,0x9f,0x93,0x95,0xd7,0x91,
+  0x78,0xaa,0xe2,0xfc,0x67,0xc9,0xc8,0xac,0x69,0xa9,0x85,0xd8,0x7f,0xdc,0xf9,0x70,
+  0xf8,0x8f,0xb8,0x02,0x2c,0x86,0xfd,0xa5,0xf0,0x9f,0x4c,0x62,0x6f,0xbc,0x39,0x3a,
+  0xff,0x69,0xc5,0xf9,0x47,0xcd,0xa5,0xf0,0x1f,0x45,0x25,0xe3,0x8b,0xf3,0x1f,0xf4,
+  0x7e,0x57,0x5f,0x89,0xbe,0x12,0x23,0xf3,0x9f,0x56,0x2a,0x11,0xbb,0x38,0xff,0xf9,
+  0x2b,0xbd,0xfa,0x64,0x49,0xfc,0x27,0x5b,0x7d,0x5a,0x6a,0x2e,0x81,0xff,0x68,0xf1,
+  0xdd,0xa4,0x51,0x48,0x24,0xfe,0x53,0x2f,0xca,0x25,0xf0,0x9f,0xae,0x38,0x2d,0xcf,
+  0x20,0xff,0xe9,0x78,0x30,0x4c,0x63,0x86,0x87,0x9a,0x4b,0xe2,0x3f,0x7b,0x4a,0xe4,
+  0x3f,0x03,0x44,0xfe,0x2c,0xfe,0x93,0x09,0xd3,0x9e,0x96,0x92,0xf8,0xcf,0x4d,0xe4,
+  0x79,0x89,0xc4,0x7f,0x66,0xfa,0xe6,0xba,0xa6,0x95,0x48,0xfc,0xa7,0x3b,0x6e,0x7f,
+  0xb5,0xf1,0xee,0x4e,0x1e,0xff,0x21,0xf6,0x1f,0x74,0x0c,0xd5,0x97,0xc8,0x7f,0x4e,
+  0x7b,0xe7,0x57,0x53,0x24,0xfe,0xe3,0xe8,0x9f,0xf1,0xf8,0x8e,0x28,0xf1,0x3f,0x63,
+  0x48,0xed,0xcc,0x8d,0xce,0x7f,0xd0,0x41,0xd0,0x6e,0xc9,0x73,0x3b,0x8f,0xff,0xf8,
+  0xf5,0x27,0x52,0xb3,0x4f,0x5a,0xfa,0xf3,0x1e,0x7c,0xe5,0xdd,0x48,0xfc,0x87,0x65,
+  0xff,0x61,0xc5,0xff,0x58,0x1a,0x7e,0x2c,0x91,0x95,0x96,0x83,0x12,0xf8,0x4f,0x65,
+  0x9e,0x14,0x7e,0x8c,0xe2,0xff,0x52,0xe8,0xf1,0x7c,0xfe,0xe3,0x81,0x4a,0xea,0xbc,
+  0xe3,0xf2,0x1f,0x0b,0xd8,0x12,0x4b,0xf4,0x92,0x42,0xc4,0x2c,0xfe,0xd3,0xe9,0x3f,
+  0xdf,0xf9,0xfc,0x47,0xbd,0x0c,0x6f,0x8c,0x1c,0xff,0x63,0x62,0xfe,0x03,0x1a,0x8b,
+  0xd9,0x7f,0x3c,0xfb,0xf3,0x44,0xcc,0x0b,0xa2,0x8b,0x6a,0xff,0x11,0x82,0xd9,0xee,
+  0x04,0xb8,0xa9,0x76,0xc4,0xff,0x65,0xf1,0x1f,0x91,0xd3,0x46,0x87,0x61,0xff,0xe1,
+  0xf9,0xbf,0xa2,0xe6,0x7f,0x15,0xb3,0xff,0x9c,0x62,0xef,0x87,0x82,0xf6,0x9f,0xe7,
+  0x8a,0xbe,0x2f,0x50,0xfe,0xaf,0x68,0xf1,0x3f,0x94,0xff,0x2b,0x9a,0xfd,0xc7,0xf3,
+  0x7f,0x05,0xfa,0xc3,0x72,0xec,0x3f,0xde,0xf3,0x18,0xcd,0xfe,0xc3,0xad,0x8f,0xcd,
+  0xb3,0xff,0x78,0xfa,0x0d,0xfa,0xed,0x3f,0x7f,0x62,0x81,0x8a,0x42,0xfd,0x41,0x22,
+  0xf9,0xdf,0x41,0x31,0xfe,0xc3,0xcd,0xff,0x8a,0x68,0xff,0x71,0xe7,0x1f,0xd5,0xfe,
+  0xe3,0xce,0xff,0xb3,0xb1,0xff,0x1c,0xf7,0xf3,0x1f,0xbd,0x98,0x3d,0x84,0xf8,0xbf,
+  0x3e,0x23,0xfb,0x8f,0x3f,0xff,0x4b,0x0f,0x0c,0x53,0xbc,0x0c,0xa9,0xef,0x7d,0x42,
+  0xfb,0x0f,0xf1,0x7f,0x61,0xfe,0xa3,0x05,0x96,0x59,0x11,0xea,0x0f,0xe2,0xed,0x9f,
+  0xc2,0xf6,0x1f,0x85,0x95,0xff,0x45,0xec,0x3f,0xdc,0xc4,0x2e,0xc2,0x7f,0xa6,0x23,
+  0xd9,0x7f,0xce,0x95,0x68,0xff,0xe1,0xe4,0x7f,0x7d,0x36,0xf6,0x1f,0xa5,0xf8,0xf3,
+  0x4b,0xfc,0x5f,0xd1,0xec,0x3f,0xef,0xd0,0xfc,0x47,0xf9,0x8d,0x5a,0x54,0x9f,0x10,
+  0x7e,0x12,0xbb,0x24,0x5c,0xfe,0xc1,0xca,0xa9,0xf2,0x22,0xf6,0x1f,0x57,0x3e,0xbe,
+  0xfe,0xb0,0x7c,0xfb,0x0f,0xc9,0xff,0xf2,0xf3,0x9f,0x05,0xec,0xf1,0x3e,0xfe,0xa3,
+  0x50,0x61,0xcf,0x09,0x8e,0xfd,0x87,0xca,0xff,0x7a,0x5c,0x59,0x49,0x56,0xb7,0x90,
+  0x63,0x3f,0x27,0xfc,0x47,0xbf,0x72,0xfe,0x53,0x28,0xff,0x0b,0x46,0xb2,0xff,0x14,
+  0xf3,0x7f,0xb9,0x40,0x29,0xce,0x7f,0xd6,0x87,0xe4,0xb3,0x3e,0xc0,0x7f,0x98,0xfe,
+  0x41,0x0c,0xbc,0x7c,0x7f,0x9a,0xff,0x7c,0xfd,0xa3,0x9a,0x52,0xed,0x3f,0x97,0xe0,
+  0xd2,0xe6,0xc4,0x64,0x79,0x3b,0x98,0x84,0xd7,0x6a,0x55,0x93,0xd2,0xec,0x22,0xfe,
+  0xaf,0x67,0x61,0x23,0x50,0xfa,0x44,0x6d,0x64,0xb7,0x82,0x00,0xc8,0x2c,0xb4,0x68,
+  0xcf,0x2c,0xae,0xff,0xeb,0x59,0xc1,0x50,0x94,0x5a,0x51,0x86,0x10,0x34,0x6a,0x0a,
+  0xa8,0x95,0x83,0xfb,0x21,0x60,0xff,0x79,0x56,0x46,0xb7,0x55,0xc5,0x55,0x60,0x37,
+  0x40,0x00,0xa2,0xd7,0xae,0x82,0xf1,0xcf,0xea,0x6f,0x40,0xbb,0xd1,0xba,0x5b,0x6a,
+  0x04,0xaf,0xc0,0xc3,0x30,0x71,0xb0,0xba,0x25,0x6c,0x1f,0x0b,0xe4,0x7f,0xbd,0xb8,
+  0xaa,0x7a,0x54,0x3a,0xa8,0x7f,0xac,0xae,0x84,0xb3,0x66,0xe6,0x5c,0x08,0x15,0x12,
+  0x0f,0xda,0x7f,0xfe,0xdc,0x48,0x0c,0x4b,0x0b,0xd5,0x57,0x60,0x3b,0x4c,0x1c,0x91,
+  0x5a,0x42,0xf9,0xdd,0x7e,0xfb,0x0f,0x62,0xfb,0x86,0x32,0x8c,0xa6,0x7d,0x1f,0xd4,
+  0xa0,0x72,0xa4,0xb6,0xc5,0x5f,0x0f,0x2a,0x64,0xff,0x39,0x0c,0xae,0x81,0x8a,0x26,
+  0x2a,0xe0,0x7e,0xa0,0xe1,0xfe,0x20,0xb2,0x2a,0x59,0x62,0x51,0x27,0xdd,0xd2,0x01,
+  0x7e,0xfb,0xcf,0xd3,0x70,0xf1,0x88,0x72,0x87,0xf8,0x25,0xb0,0x13,0xe7,0x83,0x77,
+  0x89,0x37,0x84,0xf2,0xc1,0xfd,0xfe,0xaf,0x73,0xe0,0x0f,0x91,0x58,0xca,0x5b,0xc1,
+  0x31,0x90,0xd6,0x13,0x20,0x2e,0xe3,0xfe,0x20,0x05,0xfc,0x5f,0x97,0x9c,0xb6,0x71,
+  0xc2,0x25,0x5c,0x36,0xc1,0x94,0xfe,0xa7,0xb8,0xff,0x6b,0x2a,0xf1,0x58,0x27,0x12,
+  0x0b,0xb4,0xf2,0x13,0x8f,0x89,0x41,0xf9,0x84,0xed,0x3f,0x2d,0x46,0x65,0x4a,0xdc,
+  0x05,0xf6,0x63,0xed,0x71,0x0a,0xec,0x2a,0xea,0xff,0x52,0xee,0x16,0xe7,0x83,0x47,
+  0xec,0xb0,0x9f,0x37,0x42,0xeb,0x0d,0xd8,0x7f,0xf4,0x56,0xb3,0x0b,0x67,0xcf,0x3d,
+  0x84,0x89,0xf4,0x57,0x6b,0x5f,0x31,0x83,0xfd,0x56,0x02,0xf6,0x1f,0x75,0x45,0x3e,
+  0x31,0x22,0x29,0xe0,0x0d,0xbd,0x1d,0x56,0x1f,0x90,0xde,0x65,0xe4,0xbf,0xbb,0xf3,
+  0x41,0xfc,0x47,0xb5,0xca,0xfe,0x58,0x65,0x00,0x15,0xab,0x3f,0xc8,0x4c,0x34,0xff,
+  0xd7,0x2f,0x20,0x4e,0xeb,0x4e,0xb0,0xf9,0x8f,0xdf,0xfe,0x73,0x67,0x36,0xbe,0x57,
+  0xfc,0x25,0xb8,0x4f,0x6f,0xd3,0x2b,0xf7,0xd6,0x15,0xe7,0x3f,0x4b,0xf4,0xf8,0x09,
+  0xf1,0x3c,0xf8,0x3e,0x02,0x0a,0x06,0xc5,0xfc,0x5f,0x8b,0x7b,0xe3,0x3d,0xe2,0x87,
+  0x60,0xd0,0x5c,0x9c,0xad,0xec,0x11,0x4f,0x16,0xf5,0x7f,0xb5,0x82,0x6a,0xd0,0x64,
+  0x22,0x35,0xbf,0x02,0x87,0xfd,0x84,0xd7,0x5b,0x38,0xfe,0x39,0x7c,0xe2,0x07,0xed,
+  0x3f,0x2b,0xf5,0xc4,0x49,0xe9,0x57,0xb8,0xfe,0x8f,0x99,0x38,0x21,0x5d,0xe7,0x1f,
+  0xbf,0x8b,0x11,0xff,0xac,0xe0,0x6a,0x36,0xea,0x11,0xa4,0x1f,0xaa,0xa0,0x18,0xea,
+  0x0f,0xd2,0x18,0xb2,0xff,0x64,0x70,0xb4,0x0f,0x3c,0x34,0x4b,0x43,0xa0,0x2f,0x6c,
+  0x01,0x0b,0xda,0x7f,0x5a,0xed,0x6a,0x3f,0x87,0x40,0xa3,0x5e,0x91,0x16,0xc3,0x8c,
+  0x28,0x9c,0xff,0x95,0xd8,0x6b,0x95,0x79,0x3c,0x8c,0x7f,0xdf,0x66,0x06,0xff,0x71,
+  0xf7,0xa7,0x93,0xff,0x95,0x59,0x52,0x90,0xff,0x30,0xe2,0x9f,0x07,0xe2,0x0d,0xe8,
+  0xd8,0x64,0xd7,0x3f,0xec,0x0c,0xe6,0x7f,0x2d,0xf9,0x61,0x7c,0x4a,0xbc,0x09,0xfc,
+  0x35,0x68,0x43,0x40,0xba,0x3b,0xd0,0x31,0x96,0x19,0xff,0x7c,0x5d,0x5f,0x02,0xf4,
+  0x83,0xb6,0xa9,0xf5,0xe9,0x5a,0xa5,0x00,0xff,0x71,0xf2,0xbf,0x74,0xdc,0xa6,0xb9,
+  0x66,0xd0,0x36,0x9b,0x74,0x17,0xce,0xff,0x42,0x24,0x67,0xf1,0x48,0xf5,0xb4,0xd4,
+  0x0e,0x5e,0xc6,0x6c,0x67,0x5a,0xba,0xba,0x78,0xfc,0x33,0x5e,0xdd,0x7b,0xb8,0xed,
+  0xb2,0x89,0xc0,0x74,0x01,0xff,0x17,0xce,0xff,0x3a,0x43,0x9f,0x56,0xb3,0x2e,0x48,
+  0xbf,0x0e,0x9d,0x5f,0xa1,0xfc,0xaf,0x71,0xdc,0x9f,0x5a,0x7f,0x0a,0x2c,0x19,0x55,
+  0xb2,0x48,0xff,0x78,0xf3,0xf7,0xea,0x1f,0xba,0xf7,0xc7,0xfc,0xc7,0xf1,0x76,0x9d,
+  0xc0,0xf9,0xf2,0x66,0xa5,0x21,0xfe,0xbc,0x50,0xfc,0xb3,0x9b,0xff,0xa5,0x22,0xe9,
+  0x1d,0xc4,0x66,0x10,0x80,0xa4,0x41,0xe4,0x69,0x37,0x42,0x3d,0xe5,0xcb,0xff,0x7a,
+  0x93,0xf8,0xbf,0xac,0x42,0xbb,0xef,0x42,0x7e,0xfc,0xb3,0x63,0xff,0xd1,0xed,0x6f,
+  0x75,0xeb,0x5b,0x4a,0x3e,0x76,0x46,0x58,0xd3,0xdb,0x41,0xfe,0x03,0xab,0xa7,0x84,
+  0x19,0x2c,0x8d,0xe9,0xaa,0xf3,0x12,0x3e,0xef,0x96,0xf8,0xf4,0x39,0x95,0xff,0x65,
+  0xe7,0xbf,0x83,0xf5,0xb8,0x4d,0xed,0x73,0x23,0x56,0x18,0xcf,0x74,0xd8,0x9f,0x65,
+  0x10,0xfe,0xb3,0x5d,0xb0,0x2e,0x1e,0xc2,0xdf,0x6a,0x6d,0x7a,0x05,0x73,0x3c,0x33,
+  0xfe,0x59,0x45,0xd2,0xd0,0x95,0xb4,0x25,0x9f,0xed,0xb6,0x7c,0x96,0x86,0xec,0x3f,
+  0x8a,0x6b,0xe4,0x29,0x9f,0xb2,0x16,0x5e,0xe5,0xae,0xb7,0x58,0xfe,0x57,0xe7,0xf3,
+  0x76,0xfd,0xba,0x19,0xe9,0x42,0x98,0xff,0x90,0xfc,0xaf,0xef,0x5f,0x00,0xaf,0x82,
+  0xa5,0xf4,0x6e,0xe9,0x2c,0x68,0xff,0x41,0xf2,0x1f,0x2a,0x6e,0xff,0xf1,0x7e,0xdf,
+  0x09,0xf0,0x80,0xda,0x2f,0x97,0x60,0xff,0x91,0x9f,0xa8,0x1d,0xd2,0x16,0x72,0xed,
+  0x3f,0x62,0xb0,0xfe,0xa1,0xfc,0x04,0x62,0x23,0x4f,0x47,0xb6,0xff,0xe4,0xc0,0x93,
+  0x68,0x51,0xcb,0x3c,0x69,0x8c,0x62,0xa0,0xb9,0xf2,0x49,0x85,0xf9,0x0f,0xc0,0xf7,
+  0x6f,0x77,0xef,0xc6,0x30,0x34,0x8d,0xfa,0xf8,0xcf,0x85,0xfa,0x85,0xd9,0xa1,0xe1,
+  0x90,0xfd,0x8a,0x6b,0xff,0x31,0xe5,0xc5,0x60,0xc8,0xd4,0x7c,0xd2,0x38,0x5e,0x20,
+  0xfe,0x67,0x06,0xcc,0x17,0x73,0x81,0xe8,0xdf,0xb7,0x34,0x7e,0xfe,0xd7,0x1d,0x60,
+  0x31,0x18,0x03,0x07,0x5d,0xb6,0x73,0x5d,0xd0,0xfe,0xa3,0x06,0xf9,0x4f,0xfd,0xe3,
+  0xfc,0xb2,0x12,0x44,0x9e,0x9e,0xfe,0x51,0xe4,0x03,0x89,0x63,0x44,0x3e,0x45,0xe3,
+  0x7f,0xa6,0xd5,0x7d,0xe8,0x19,0xe6,0xb4,0x85,0x65,0xd6,0x7f,0x7e,0x58,0xde,0xd5,
+  0xb7,0xbf,0x84,0xf8,0x9f,0x7f,0x06,0x39,0x5d,0x2b,0xb2,0xdf,0x08,0xff,0x99,0x90,
+  0x9f,0x85,0xc7,0xa9,0x68,0x67,0x07,0x88,0x7c,0xfe,0x33,0x22,0x06,0xdb,0xc2,0xbe,
+  0xad,0x14,0xe0,0x3f,0xe0,0x27,0xc6,0x28,0x68,0xf7,0x9f,0xfe,0x05,0xf9,0xcf,0x02,
+  0x78,0xdf,0x54,0xa3,0xd3,0x1f,0xd6,0x39,0x76,0x61,0x01,0xfe,0x23,0x37,0x8b,0x43,
+  0x6a,0xa0,0x8d,0xa9,0xfe,0x55,0x91,0x5f,0xff,0x39,0x26,0xe6,0xf4,0x91,0xc8,0xf1,
+  0x3f,0xdd,0x8a,0x89,0xf4,0x53,0x3b,0xc3,0xdf,0xc7,0xb3,0xff,0x20,0x1a,0x13,0xb4,
+  0xe7,0x84,0xf9,0x8f,0x97,0x7f,0x91,0xaa,0xfa,0x55,0xdf,0xbf,0x19,0x7e,0xf9,0x84,
+  0xfb,0xa3,0xbd,0x4c,0xd5,0x3f,0x9c,0x80,0xbb,0xb5,0x46,0xbf,0xd9,0x47,0xe6,0xc7,
+  0xff,0x18,0x60,0x10,0xe6,0x0c,0x2d,0x72,0xfc,0xcf,0x11,0xc4,0x67,0xee,0xd3,0x39,
+  0x6d,0x61,0x59,0xfc,0x47,0xfe,0x31,0x78,0x05,0xd1,0x1e,0x6b,0xb6,0x11,0xec,0x3f,
+  0x13,0x60,0xa0,0xac,0x94,0xf8,0x1f,0x05,0xec,0x6f,0x34,0xc3,0xf2,0xe7,0xc6,0xff,
+  0x28,0x03,0x5f,0x45,0xb4,0xa7,0xd1,0x67,0xed,0xb9,0xa8,0xf3,0xed,0x3f,0x8a,0x5c,
+  0x0d,0xfa,0x60,0xb1,0xe7,0x85,0xf0,0x1f,0x01,0xcc,0x5d,0xb8,0x53,0x2f,0xf6,0xfc,
+  0x12,0xff,0x97,0x02,0xaf,0x46,0xaf,0xd5,0x87,0x7c,0x6c,0xe7,0xf5,0x02,0xf1,0x3f,
+  0x2d,0xf2,0x01,0x86,0x35,0xc3,0xbd,0xa2,0x86,0xf9,0x8f,0xfc,0x42,0xd7,0x24,0xf4,
+  0x9d,0x5f,0xd2,0x1b,0xe0,0x83,0x3e,0x5e,0xfc,0xcf,0x3f,0x82,0xe7,0xdf,0xd9,0x69,
+  0xbf,0x76,0x79,0xb3,0x3d,0xa5,0xbb,0xef,0x5f,0x72,0x28,0xfe,0x67,0x04,0x0c,0xab,
+  0x3b,0x03,0xfa,0xea,0x64,0x28,0xf1,0x8d,0xd8,0x7f,0x70,0x7f,0xd8,0xfe,0x80,0x3c,
+  0xcd,0x50,0xbf,0x4b,0xe2,0xff,0x52,0xd0,0xf9,0x75,0x6c,0x77,0x50,0x7f,0x06,0x1b,
+  0xc1,0xd3,0xf1,0x3f,0x8f,0x63,0xa5,0xe4,0x7c,0x2b,0x58,0x20,0xd0,0x3f,0xee,0xcb,
+  0x3e,0xfb,0x0f,0x38,0xd2,0x72,0x2e,0x54,0xf6,0xe7,0x4c,0x80,0x0f,0x10,0xff,0xd7,
+  0xa8,0xbc,0x20,0xff,0x1c,0xf4,0x9f,0x5f,0x63,0xce,0xfb,0x7b,0xa3,0x7b,0xa5,0x9d,
+  0xee,0x0f,0xdb,0x02,0x8e,0x04,0xc6,0x4f,0xeb,0x81,0x8c,0xf8,0x0c,0x65,0xff,0x51,
+  0x13,0xe8,0x7d,0x7f,0xa4,0x88,0x7c,0x28,0xfe,0x33,0xbc,0x1d,0x6d,0xf2,0xc3,0x01,
+  0xf9,0xbc,0x49,0xef,0x87,0x72,0xda,0xfe,0x03,0xc3,0xf1,0xcf,0x9d,0x81,0xfa,0xcf,
+  0x0f,0x32,0xe2,0x7f,0x26,0xac,0xdd,0xf2,0x2a,0x06,0x33,0xc5,0xe3,0x9f,0xfb,0xda,
+  0xb6,0x59,0x6c,0x67,0x08,0xb6,0xcd,0xc4,0x9f,0x67,0xf0,0x9f,0x50,0x7f,0xd8,0x51,
+  0xdc,0xaf,0x53,0xe9,0x17,0x5a,0x4f,0xc4,0x9b,0x19,0xcf,0xd7,0xb9,0x60,0xfc,0x8f,
+  0x8e,0xa5,0x9d,0x41,0x62,0x9f,0xb0,0x89,0x25,0xdf,0xfe,0x43,0xfa,0x5f,0x58,0x65,
+  0xf7,0x5e,0xab,0x3e,0xd2,0x14,0x3e,0x7f,0x47,0xbd,0xf9,0xbf,0x8d,0xfb,0x5f,0x88,
+  0xf7,0x9a,0xf6,0x32,0xb1,0x5b,0xf9,0x20,0xcb,0x3e,0xc6,0xee,0x0f,0x6b,0x99,0x35,
+  0x46,0x3c,0xb7,0x63,0x8d,0x17,0xba,0x4f,0xf8,0xcf,0x31,0xb9,0xd5,0x2a,0x53,0x39,
+  0x74,0xb8,0xf6,0xb8,0xb3,0x6d,0x32,0xad,0x2a,0xe1,0x6f,0xc1,0xfc,0xaf,0x77,0x04,
+  0xcf,0xfe,0xfc,0x2a,0xec,0xcf,0xe1,0xfa,0x90,0x99,0xb0,0x87,0x74,0xc6,0xdb,0x0e,
+  0xb7,0x0b,0xf3,0x65,0xdc,0x16,0x16,0x9f,0xfe,0x99,0x5d,0x36,0x08,0x7b,0xc4,0x7c,
+  0xfd,0x2f,0x9c,0xfa,0xcf,0x9d,0x93,0xc6,0x4b,0xca,0x72,0x58,0xad,0x79,0x61,0x3f,
+  0x9d,0xac,0xfe,0xb0,0x56,0xfc,0xcf,0x32,0x4c,0x9b,0x4f,0xeb,0x97,0xd5,0x95,0xe3,
+  0xd5,0xff,0x45,0xc9,0x47,0xf7,0xec,0x3f,0xee,0x7a,0x9d,0xfa,0x5d,0x53,0xe8,0xb5,
+  0x65,0x12,0xbc,0x04,0x91,0xa2,0xce,0xb3,0xfa,0xc3,0x12,0xfd,0xef,0xd4,0xdf,0x50,
+  0xb0,0x1a,0xd9,0x05,0x1a,0xf0,0xe9,0x13,0x8e,0x28,0x38,0x47,0xf1,0x4f,0x6c,0xff,
+  0x69,0x9d,0xaa,0xb4,0xcb,0x1e,0x36,0x8c,0xc4,0xbb,0x18,0xeb,0xa5,0xfc,0x5f,0xf6,
+  0xfb,0xd7,0xb8,0x95,0x6d,0xd1,0x0f,0x90,0x22,0xba,0x4a,0xa4,0xdf,0x38,0x1c,0xff,
+  0x57,0x30,0xfe,0x67,0xa4,0x4c,0x43,0x2f,0xa1,0xc7,0xc4,0x9f,0xa2,0x17,0xa5,0xb8,
+  0x15,0xf6,0x03,0xcb,0x7d,0xfc,0xc7,0xbb,0xbf,0xe3,0xff,0x7a,0x10,0xd1,0x1e,0xfd,
+  0x02,0x58,0xce,0xf3,0x7f,0xb9,0xe3,0x3d,0xfb,0xcf,0xdf,0x49,0xcd,0xe8,0xa0,0x6c,
+  0xd3,0x37,0xa8,0x94,0x7d,0x40,0xf5,0xf8,0x8f,0x3b,0x9e,0xf2,0x7f,0x2d,0x02,0xb8,
+  0xec,0x70,0x55,0xbe,0x32,0xec,0xe1,0x9a,0xf6,0x7e,0x5f,0xd2,0xff,0xe2,0xea,0x85,
+  0xc0,0x29,0x53,0x1c,0x1e,0x4f,0xf9,0xbf,0x80,0x6b,0xfd,0x28,0x93,0x6b,0x71,0x19,
+  0xc0,0x0a,0x55,0x0c,0xd9,0x43,0x1a,0xa9,0xfc,0x77,0xc5,0xb0,0xda,0xc2,0xa2,0x45,
+  0xb5,0xe0,0xb2,0xab,0xd8,0xfe,0x13,0xee,0xbf,0x40,0xea,0x3f,0xdb,0xf6,0x9f,0x95,
+  0xd9,0xea,0x7c,0xd3,0x79,0x1b,0x90,0xb0,0x9f,0x3a,0x56,0xfe,0xbb,0xed,0x3f,0xca,
+  0x54,0x9f,0x90,0xfe,0x14,0xbc,0x8f,0x41,0xbe,0x3f,0xcc,0x07,0xa8,0xfe,0x17,0x4e,
+  0xfd,0xc3,0x21,0xc4,0x76,0x70,0xdb,0x0b,0x35,0x3e,0xc0,0xf2,0x7f,0x91,0xfa,0xbd,
+  0x6e,0xfc,0x4f,0x5a,0x0c,0xb7,0xf9,0xb0,0xc1,0x7a,0x35,0xf3,0x9a,0xe0,0x8e,0x4f,
+  0xc5,0x6c,0x6b,0xcf,0x50,0x5e,0xfc,0x05,0x96,0xa7,0x21,0xe5,0x81,0x2b,0xc6,0x5a,
+  0x4e,0xfd,0x67,0x67,0x92,0x76,0xbf,0xd7,0xf2,0x87,0x05,0x06,0xff,0x21,0xfe,0x0e,
+  0x2f,0x1f,0x50,0xd8,0x56,0xc0,0xff,0xc5,0xe8,0x7f,0x51,0x37,0xd5,0x88,0xe4,0x2f,
+  0x4c,0x52,0x61,0x3f,0x96,0x29,0x32,0x10,0xff,0x33,0xe0,0xf9,0xbf,0x7e,0x0e,0xef,
+  0xd7,0xda,0xa0,0x32,0x22,0xdd,0x41,0xd9,0x7f,0xc4,0x36,0x5e,0x7f,0xd8,0xc6,0xe3,
+  0x42,0x3f,0xb4,0xda,0x74,0x86,0x33,0x98,0xa8,0xfe,0x17,0x5e,0xfc,0xcf,0x5d,0xa7,
+  0xd1,0xf3,0x8b,0x1e,0xcc,0x9b,0x18,0xfc,0x27,0x64,0xff,0x99,0xda,0x78,0xf7,0xa6,
+  0xb7,0xc0,0xcf,0x72,0x7f,0x34,0xd5,0x86,0x0b,0x21,0x7e,0xe8,0x34,0x8a,0x55,0xc3,
+  0xf5,0x9f,0xe7,0xb9,0xf9,0x5f,0x4d,0x93,0x22,0xd6,0x1e,0x55,0xac,0x7e,0xe8,0xbe,
+  0xfe,0x17,0x56,0xfe,0x57,0xe2,0xc2,0xa6,0xb7,0x6a,0x5f,0xed,0xc3,0xc0,0x09,0xfb,
+  0xd9,0x78,0xa1,0xee,0x92,0x9b,0x1a,0xe6,0xeb,0x7f,0xe1,0xea,0x9f,0xd3,0x70,0xd0,
+  0x06,0x44,0xff,0xb8,0x85,0x10,0x89,0xfd,0xed,0x07,0xb6,0xff,0x6b,0x4c,0xd9,0x21,
+  0x9e,0x56,0x10,0x4d,0x3a,0x81,0x14,0x4b,0x58,0x5f,0x11,0xfb,0x8f,0xd5,0x9f,0x5a,
+  0xc0,0xf6,0xe7,0xda,0x49,0xdc,0x66,0x65,0x54,0x49,0xdf,0xef,0xea,0x9f,0x5a,0x57,
+  0x9e,0x8d,0x54,0xfd,0xe7,0xe4,0xe3,0xf8,0x10,0x99,0x6a,0x45,0xfa,0xd3,0x32,0x9b,
+  0xe3,0xb0,0xd2,0xd0,0x7a,0x8f,0x7b,0xfa,0x30,0x0f,0xde,0x4b,0xd8,0x17,0x9b,0x3e,
+  0x00,0xb8,0x5e,0x34,0xeb,0x7d,0xb3,0x89,0xf4,0x87,0xcd,0xa9,0x1f,0x29,0x97,0xcb,
+  0xd0,0xc5,0x99,0xba,0x8f,0xc0,0xab,0xf8,0xfe,0x0c,0x7f,0x50,0xf9,0x01,0x8a,0xff,
+  0x6c,0x77,0x8a,0xd4,0x65,0x3e,0x90,0x87,0x02,0x69,0x5c,0x2c,0xfb,0x0f,0x3e,0xef,
+  0xf0,0xdb,0xfd,0xb0,0xf8,0x9f,0x1a,0xe2,0x03,0x9c,0xf1,0xcc,0xfa,0x3f,0x65,0x98,
+  0xf6,0x30,0xeb,0x43,0x52,0xf9,0xef,0x74,0xfd,0x9f,0x7f,0x95,0x57,0x98,0xcc,0xfe,
+  0x56,0x23,0x65,0xee,0x7c,0x2c,0xfb,0x8f,0x68,0xd3,0x1e,0x95,0xef,0xff,0x5a,0xd8,
+  0xeb,0xfd,0x05,0xbb,0xe9,0xde,0x77,0x2a,0xe7,0x8e,0x21,0x30,0xd9,0xb2,0xb4,0xf2,
+  0x77,0xa2,0x1f,0xa2,0xdd,0x74,0x4f,0x98,0x2c,0x7e,0x7f,0x05,0x8a,0x74,0x77,0xbc,
+  0xa5,0xd8,0x65,0xf6,0x45,0x3f,0xc4,0x4f,0x2c,0xff,0x70,0x3f,0x44,0x56,0x87,0x44,
+  0xb9,0xc0,0xfd,0xe7,0x9a,0xa5,0xf5,0x43,0x54,0x4b,0x94,0xbf,0x5a,0x48,0xfe,0x8c,
+  0x7e,0x88,0x09,0x33,0x24,0xf3,0x2f,0xfa,0x21,0x16,0x06,0x9f,0xe7,0xf1,0xbf,0x63,
+  0xcf,0xe3,0x27,0xeb,0x0f,0xeb,0x44,0x0e,0x04,0xc0,0xef,0x8d,0x3e,0x9c,0x24,0xd2,
+  0xfe,0x4e,0x40,0xfe,0x93,0xbf,0x2d,0x7d,0x68,0xdd,0xed,0x8b,0xfe,0xb0,0x81,0xcf,
+  0x17,0xfa,0xf0,0xff,0xf9,0xf8,0xa3,0x1d,0x52,0xaf,0x7e,0x5a,0xbd,0x11,0x54,0x8d,
+  0x5a,0x60,0x91,0x1c,0xfb,0x99,0xb4,0xc3,0xec,0x51,0xe7,0xd4,0x57,0x1d,0xc5,0x20,
+  0x3b,0x47,0xae,0x32,0xaf,0xf5,0xc6,0xaf,0x5e,0x25,0xef,0x10,0x7a,0xf4,0xad,0x2a,
+  0x18,0x8f,0xd9,0x20,0x49,0x80,0xe0,0x00,0xf3,0x5a,0x97,0x0f,0x03,0x28,0x0a,0x1a,
+  0xec,0xd2,0x6a,0x15,0xd0,0xe7,0x00,0x99,0x02,0x0d,0xb0,0xcb,0x40,0xc0,0x6b,0x2f,
+  0x83,0xb7,0xb8,0xd0,0x0b,0xba,0xc1,0x6c,0x30,0x08,0x05,0xc3,0x02,0xc9,0x01,0xe1,
+  0x36,0xa1,0x1b,0x6c,0x49,0xc5,0x76,0x0a,0x06,0x06,0x20,0x46,0x8d,0x3f,0xda,0x1d,
+  0xbb,0x41,0xf8,0x3a,0xdc,0xd4,0x21,0xef,0x8e,0xdd,0x25,0xf4,0xc0,0xad,0x5a,0x72,
+  0xc2,0x03,0x02,0x02,0x23,0x08,0x50,0xf3,0x39,0xaa,0xeb,0x5a,0x56,0x91,0xc5,0x18,
+  0xfa,0x4b,0x06,0x48,0x81,0x32,0x20,0x10,0x20,0xbb,0x80,0xac,0xf7,0x68,0x97,0x7c,
+  0xbb,0x90,0x82,0x6b,0x34,0x70,0x9f,0xdc,0x28,0x28,0xf9,0x0c,0x50,0x77,0xcb,0x0d,
+  0x82,0x02,0x32,0x9a,0x3a,0x20,0x6b,0x36,0xa0,0xc7,0xaf,0x8b,0xdd,0x32,0xba,0x79,
+  0xe4,0xd6,0xd6,0xfa,0x59,0xb1,0x4c,0x2e,0x9b,0xdf,0xac,0xc4,0x2a,0x63,0x3a,0xcc,
+  0x6a,0xf5,0x2d,0x49,0xd1,0x06,0xcb,0x93,0x80,0x92,0xcf,0x5c,0xa1,0x1c,0xdc,0x6a,
+  0x26,0xb3,0x72,0x42,0xd8,0x8a,0x40,0x4d,0x6f,0xac,0x47,0xd8,0x04,0x36,0x9b,0xc9,
+  0x74,0xec,0x8f,0x05,0x09,0x83,0x9b,0x64,0xaf,0xfc,0x2a,0x1a,0xaf,0xe9,0x0a,0xa8,
+  0x05,0x32,0x44,0xca,0x06,0x69,0x3e,0x5d,0xd0,0x90,0x0a,0xec,0x84,0x2a,0x94,0x55,
+  0x41,0x46,0xaa,0x01,0x03,0xd0,0x41,0xc9,0xc7,0x10,0x91,0xe8,0x81,0x86,0x54,0x87,
+  0x05,0x1a,0xec,0x50,0x2c,0x7c,0x45,0xd1,0xca,0x1c,0xd0,0x41,0xc9,0x27,0x1b,0x6b,
+  0x16,0xbe,0x09,0xb6,0xe8,0xf5,0x30,0xb6,0xcd,0x02,0xf3,0xf2,0x31,0x43,0x38,0x05,
+  0xfe,0x0c,0x24,0xf3,0x31,0xcd,0x06,0xf4,0x7a,0xf5,0xb8,0x01,0x4e,0x81,0x1b,0xb0,
+  0xe1,0xc4,0xfa,0xbd,0xb4,0x24,0x94,0x6e,0x07,0xdd,0x70,0x36,0xa8,0x22,0x80,0xda,
+  0x3f,0x9d,0x72,0x3a,0x97,0xd0,0x3a,0xd1,0x5f,0x96,0xd3,0x30,0xa1,0x49,0x8a,0x3a,
+  0x56,0x9f,0x1e,0xc5,0x57,0xd4,0x97,0x80,0x03,0xa8,0xdf,0x0b,0x7d,0xd2,0xe8,0x9d,
+  0x4a,0xc2,0x3b,0xc3,0x01,0xa6,0x0b,0x26,0xbc,0x2b,0x94,0x7c,0x24,0x21,0x0d,0x37,
+  0x68,0x75,0x78,0x77,0x59,0x20,0x51,0x3f,0x26,0xa4,0x73,0x1b,0xd2,0x9b,0x14,0xf9,
+  0x98,0x0b,0xa8,0xf1,0x47,0x33,0x31,0x23,0xd7,0xad,0x6d,0x41,0xe3,0x1d,0x10,0x43,
+  0x60,0x14,0x83,0x64,0xbf,0xa0,0xd9,0x00,0x52,0xf2,0xc9,0x58,0x92,0xf3,0x44,0x88,
+  0xc0,0x18,0x02,0x78,0x21,0x68,0x45,0x0e,0xa0,0xd7,0x7b,0x8b,0x6c,0xe4,0x52,0xda,
+  0x9a,0x2e,0xb0,0x07,0x81,0xab,0xb4,0x35,0x09,0x30,0x26,0x6f,0xcb,0x25,0xd2,0x9d,
+  0x5d,0x35,0x7b,0x64,0xcd,0x06,0xb4,0x3c,0x8d,0x58,0xb7,0xb0,0x05,0xdc,0x0a,0xeb,
+  0x35,0x07,0xc8,0xe8,0x0a,0x58,0x03,0x6a,0x60,0xd2,0x88,0xa5,0x6c,0xa0,0x53,0xfb,
+  0xa7,0x4c,0xf8,0x06,0xec,0x31,0x92,0xc3,0xb1,0x32,0xa1,0x03,0xaa,0x86,0x9c,0x8a,
+  0x95,0x81,0x0e,0x98,0x35,0xea,0x53,0xd6,0x15,0x0b,0x10,0x73,0x11,0x30,0x6b,0xad,
+  0xbd,0x50,0xab,0xcb,0xb5,0x02,0x80,0x1d,0x9a,0x8a,0x9e,0x85,0x1a,0x79,0x40,0xd7,
+  0xd4,0x2e,0xeb,0x8a,0x05,0xd0,0x31,0xe6,0xcd,0x67,0x8d,0x58,0x03,0x07,0x8c,0x05,
+  0xaa,0xb0,0x46,0xfa,0x06,0xdc,0x6c,0x24,0x53,0x55,0x18,0x9c,0x34,0xae,0x47,0xa0,
+  0xdc,0x01,0xd4,0x7c,0xc6,0xd7,0xc4,0x76,0xf4,0xf5,0x18,0x5b,0x53,0xc9,0x97,0x63,
+  0x3b,0x72,0xfb,0x8c,0x6f,0xa7,0xe6,0x61,0x70,0xda,0xf8,0xae,0x7d,0xc5,0x02,0xb4,
+  0x3e,0x59,0x23,0xec,0x80,0xa7,0x8d,0x1b,0x53,0x55,0x2f,0x4b,0x36,0x10,0x30,0xe8,
+  0x31,0xe6,0xd8,0x57,0x2c,0x60,0xd6,0x50,0xe3,0xd1,0x4d,0xd0,0xfd,0xbb,0xc1,0xcb,
+  0x36,0x48,0xa9,0x18,0x24,0x8c,0x4e,0x74,0x7f,0xd0,0x60,0x03,0xb3,0x86,0xda,0x3f,
+  0x82,0x06,0xba,0xd0,0x13,0xe3,0xe9,0x9f,0xd8,0x18,0x02,0x3d,0xda,0x1c,0x5b,0x11,
+  0x59,0x00,0x52,0xbb,0xad,0x4c,0xb8,0x0d,0x76,0x1b,0xb3,0x53,0xc9,0x9d,0x1e,0x00,
+  0xb7,0xe5,0xba,0x0d,0x4b,0xff,0x34,0xd8,0x80,0x1a,0xbf,0x5a,0x4f,0xa6,0x85,0x0d,
+  0x60,0x13,0x90,0x61,0xac,0x57,0xe8,0x01,0x5b,0x41,0xd2,0xf4,0x80,0x90,0x76,0x00,
+  0x99,0xcf,0x6a,0xb4,0x7f,0x46,0x94,0x16,0xb1,0x12,0xed,0x1f,0x03,0xa6,0xd0,0x23,
+  0x28,0x78,0xa0,0x1f,0xed,0x1f,0x0b,0x40,0x6a,0xbd,0xeb,0x64,0x63,0x3f,0xda,0x3f,
+  0x95,0x78,0x77,0xe5,0x14,0x3b,0xc0,0xcb,0x03,0x86,0x0d,0xe8,0xf1,0x9d,0x0b,0xb2,
+  0xa3,0x9b,0xdb,0x6f,0x55,0x06,0x91,0xb6,0xc9,0x65,0x35,0xa4,0x7f,0x10,0x18,0x40,
+  0x6a,0x47,0x41,0xfa,0x27,0x0b,0x2d,0x00,0x28,0xf9,0x54,0x0a,0xd9,0x89,0xcd,0xe9,
+  0xa4,0x22,0x77,0x0a,0x59,0x13,0x81,0x44,0x2c,0x0c,0x74,0x4a,0x3e,0x40,0x37,0x54,
+  0x55,0x96,0x05,0xc4,0x38,0x33,0x58,0xdb,0x58,0x2a,0xd0,0x06,0x80,0x00,0x32,0x9f,
+  0x8c,0xd8,0x08,0xe1,0x88,0xd6,0x35,0x2c,0x8a,0x00,0xc2,0xb4,0xa6,0x28,0x16,0xd0,
+  0x10,0x90,0xca,0x2c,0x90,0x50,0xa8,0xf9,0xac,0xd6,0xcb,0x2d,0x25,0x2f,0x25,0x61,
+  0xcc,0xd6,0xf6,0xf3,0xa0,0xab,0x7f,0x08,0x20,0xeb,0x1d,0xd4,0xe7,0x58,0xfa,0x47,
+  0x1a,0x84,0x12,0x06,0xe8,0x74,0x30,0x25,0x43,0xee,0x01,0x73,0x90,0xda,0xa9,0xd1,
+  0x80,0x0d,0xe8,0xf9,0xcb,0x69,0x21,0x01,0x3a,0xd1,0x5f,0xb6,0x80,0x84,0x9e,0x27,
+  0x39,0x0d,0xf0,0x83,0xa5,0x9a,0x40,0x13,0x1c,0x40,0x0d,0xb7,0x95,0x8c,0x8e,0xf4,
+  0xcf,0xb5,0x30,0x61,0x48,0xdd,0x60,0x2f,0xb8,0x0e,0x54,0x00,0x51,0x07,0x27,0xf5,
+  0x66,0x0c,0xb0,0x46,0xa2,0xc6,0xcb,0xd7,0xea,0x1b,0xb2,0x75,0xf9,0xbd,0x47,0x05,
+  0x04,0x3a,0x36,0xd5,0xd7,0x23,0xd0,0xb1,0x21,0xbb,0xa9,0x5e,0x1e,0xcf,0x35,0x60,
+  0xa0,0xca,0xf4,0xf8,0x45,0xb1,0x3b,0x46,0xbf,0x95,0xde,0xb2,0x3b,0xf6,0x23,0x0b,
+  0xcc,0xde,0x97,0xb4,0xc1,0x96,0x07,0x92,0xff,0x90,0x73,0x80,0x6f,0xfe,0x36,0xe3,
+  0xc7,0xf3,0xb1,0xc8,0xa6,0x8e,0xe6,0xd3,0x6c,0xcf,0x27,0x2f,0x3b,0xf3,0xf1,0x8d,
+  0xdf,0x66,0xd4,0xa4,0xe4,0x35,0xe8,0xf7,0x5a,0x85,0x0f,0xb2,0x32,0xad,0x66,0xb7,
+  0x7c,0x7b,0x4d,0x6a,0x60,0x4d,0x43,0xcd,0xc0,0x2a,0x07,0xd0,0xe3,0xe5,0x8e,0x6c,
+  0xcd,0x66,0xf9,0x56,0x74,0x98,0xc4,0x10,0x88,0x25,0x85,0xd8,0xaa,0xd5,0x59,0xb0,
+  0x59,0x4e,0x82,0xa4,0xbe,0x3a,0xab,0x6e,0x4e,0x24,0x85,0x24,0xbd,0x1f,0x94,0x06,
+  0x51,0xd1,0xfb,0x54,0x6d,0x50,0x69,0xc8,0x28,0xd9,0xbe,0x7a,0x04,0x84,0x4c,0x0a,
+  0x83,0x98,0x72,0xdb,0x2d,0xf6,0x15,0x7a,0x3a,0x95,0x40,0x84,0x60,0x04,0xb4,0xa0,
+  0x8d,0x27,0x42,0x7d,0x44,0x6d,0x91,0x11,0xc8,0xdb,0xc0,0x14,0x87,0xf5,0x03,0xea,
+  0x35,0x34,0xdb,0x06,0x09,0xb1,0x0e,0x0c,0x98,0x0d,0xe9,0xd4,0x06,0x69,0x13,0x38,
+  0x39,0x96,0x4c,0x57,0x21,0xa0,0x6e,0x36,0xaf,0x47,0xc0,0xac,0x53,0x4f,0x9a,0xd7,
+  0xb7,0x57,0xd1,0xf3,0xa9,0x10,0xee,0xea,0xe8,0xc9,0x6f,0xd5,0xe6,0x61,0x1a,0x30,
+  0x17,0x7e,0xdb,0x06,0xfb,0xe0,0x77,0x11,0x1f,0x58,0x73,0x97,0x70,0x1a,0x81,0xbf,
+  0xa1,0xe5,0x1f,0x5f,0x97,0x79,0x3d,0xff,0xd4,0x81,0xc5,0x15,0x5f,0xc1,0xe0,0xc9,
+  0x03,0x8b,0xd7,0xc6,0x6f,0x59,0x77,0x62,0xcf,0x53,0xcd,0xff,0x54,0x11,0xcf,0xac,
+  0x3b,0x89,0xc1,0x1f,0xd0,0xf3,0x59,0x76,0xef,0xcd,0x97,0xff,0xe3,0xc5,0xf3,0xef,
+  0x5f,0x5c,0x89,0xc1,0x33,0xe7,0x3f,0xb8,0xb8,0xec,0xd2,0xc6,0x33,0x0f,0x5d,0x3e,
+  0xfb,0xf1,0xc5,0x65,0xf7,0x6c,0xbc,0x8c,0xc1,0xc7,0xe0,0x0a,0x3e,0x2b,0xfe,0xb6,
+  0x62,0x61,0x66,0x6d,0x7e,0xcf,0xb6,0x05,0x17,0xab,0x7f,0xd2,0x79,0x39,0xff,0xeb,
+  0x6d,0x2b,0xfe,0x7e,0xed,0xbd,0xaf,0xad,0xcd,0x3f,0xf2,0xf1,0xca,0xcb,0x6b,0x17,
+  0xbd,0xb6,0xf6,0xfc,0x23,0x67,0xe9,0xf1,0x2b,0xef,0xb9,0xf9,0xcc,0x43,0xcf,0x9c,
+  0x7d,0x9f,0x4c,0xc3,0x9e,0xd8,0xd9,0x0f,0xd0,0xf8,0x9b,0xcf,0x58,0x33,0xa4,0xc7,
+  0x37,0xcd,0xef,0x3a,0xb3,0xe7,0xc6,0xb3,0x0f,0xdc,0xb6,0x0c,0xff,0xc7,0x43,0x67,
+  0xdf,0x7f,0x1b,0x81,0xb7,0xea,0x9e,0x19,0x78,0xff,0x62,0x53,0xca,0x02,0xef,0x7d,
+  0xcf,0x37,0xa1,0xbe,0x5e,0x7d,0x9f,0xba,0x48,0xbd,0x6f,0xb4,0x11,0x01,0x70,0xa3,
+  0x5c,0x71,0x54,0xec,0xd5,0xe7,0xaa,0x8b,0xea,0x2d,0x80,0xbe,0x9a,0x5b,0x41,0xcb,
+  0x53,0x1e,0xdc,0x01,0x10,0x09,0xac,0x05,0xe3,0x83,0x98,0x0d,0x6e,0xb2,0xf8,0x21,
+  0x38,0xed,0x23,0x8a,0xf4,0x78,0x87,0x1f,0x5e,0x05,0xfa,0x73,0x18,0xcc,0x56,0xe4,
+  0x9d,0x2e,0x3f,0xf4,0x00,0xf4,0x4d,0xc8,0x26,0x69,0xb9,0x20,0x7f,0x53,0x69,0x40,
+  0x3e,0xca,0xaa,0xbb,0x84,0x04,0xec,0x8c,0xc3,0x89,0x6d,0xed,0xc2,0xdc,0x81,0xaf,
+  0x69,0x35,0xc7,0x64,0xbc,0x31,0xbe,0x76,0x53,0xcd,0x84,0x0d,0xb4,0x1a,0xd3,0x7f,
+  0x7f,0x55,0x29,0x43,0xfc,0x70,0x10,0xb1,0x2e,0xef,0xfe,0x0a,0x06,0x7d,0xe4,0x2f,
+  0x92,0x4f,0x15,0xa2,0x85,0x88,0x1f,0x1a,0x00,0x3d,0x56,0x82,0x02,0x11,0x1b,0x1c,
+  0x96,0x9b,0xd1,0x95,0x4c,0xaf,0xba,0x0f,0x33,0x46,0x98,0x31,0x7c,0xef,0x68,0x5f,
+  0x91,0xd7,0x0d,0xce,0x7e,0x6c,0xf5,0x11,0x75,0xc9,0xc0,0xb7,0x72,0xb5,0x23,0xab,
+  0x1e,0xab,0xb9,0x46,0xee,0x32,0x6f,0xb1,0xc1,0x3a,0xfb,0x0a,0x35,0x7b,0xb3,0x0a,
+  0xd4,0x81,0xfa,0x89,0xd8,0xc3,0x60,0x12,0x4a,0xa0,0x1e,0x71,0x1f,0xfb,0xb4,0x31,
+  0x63,0x36,0xa8,0xc7,0x40,0x27,0xff,0x01,0xbd,0xaa,0xaa,0x2a,0x7a,0x97,0xed,0x06,
+  0xf8,0x29,0xc2,0x6f,0xa2,0x82,0x0a,0x56,0xa1,0x7f,0xc8,0x59,0x61,0xb6,0x6a,0xbd,
+  0x34,0xeb,0x82,0xe7,0xbe,0x46,0xf7,0xb7,0x5f,0x57,0x35,0xd9,0xff,0xa6,0x2a,0xfb,
+  0x5f,0x39,0xe9,0xf1,0xb2,0x61,0x2b,0x49,0xac,0xe8,0x53,0x48,0xe3,0x23,0xfd,0x69,
+  0x08,0xc3,0x16,0x31,0x71,0xbe,0xaa,0x81,0xde,0x78,0x55,0xd0,0x45,0x03,0x0c,0x83,
+  0xff,0x6d,0xdf,0x7c,0x5e,0xa4,0xb8,0x82,0x38,0x5e,0x6f,0xe6,0xed,0xa4,0xc5,0xd9,
+  0xa5,0x7b,0x33,0x0b,0xad,0x2c,0x32,0xa3,0xab,0x1e,0xbc,0xf4,0x2c,0x0a,0x8a,0x07,
+  0x9f,0xbb,0x33,0xeb,0xac,0xb0,0xda,0x44,0x54,0x08,0x39,0xb4,0xc1,0x8b,0xb7,0xec,
+  0xcd,0x4b,0xe2,0x9b,0xcd,0x45,0xc4,0xc3,0xa2,0x22,0x0a,0x82,0x7b,0xd0,0xdc,0x84,
+  0xfc,0x09,0x33,0x0b,0x19,0x48,0x4e,0x42,0x62,0x6e,0x21,0x1b,0xc8,0xc5,0xbb,0x10,
+  0x72,0x90,0xb5,0xea,0xbd,0xfe,0xf1,0x7a,0xc7,0x08,0x7a,0x88,0x20,0xf5,0xbd,0xec,
+  0x97,0xda,0x37,0x4d,0x75,0xbf,0x9a,0xea,0x4f,0xf5,0xcc,0x1c,0xa2,0x9e,0x65,0xcd,
+  0x2e,0x32,0x61,0x66,0x4c,0x64,0x2d,0x4f,0x5f,0x75,0x17,0x2c,0x1f,0xf6,0x88,0x0f,
+  0x0d,0x28,0xfa,0x9b,0x68,0x6e,0x67,0xc6,0xf2,0x61,0x7e,0xbf,0xa0,0x33,0x1f,0xe7,
+  0xc3,0xf9,0xd4,0xa8,0x3c,0xa2,0xf2,0xf5,0x15,0xb0,0xd8,0x89,0xd8,0x96,0x9b,0xf9,
+  0x41,0x39,0x32,0x28,0xe5,0x63,0xf8,0xad,0x0e,0x6b,0xd6,0x78,0x01,0x9a,0xe1,0x57,
+  0xa9,0xb1,0x11,0x5d,0xe4,0x23,0xc6,0xf9,0x70,0xdc,0x14,0xf5,0x10,0x8b,0xb7,0x1e,
+  0x1f,0x4f,0xb3,0x74,0x7c,0x27,0x1f,0x85,0x1b,0xd9,0x80,0x2e,0xa2,0x7f,0x6a,0x02,
+  0x34,0xb8,0x5f,0x64,0xe6,0xd2,0xc8,0x42,0x9e,0x4f,0x4f,0x11,0x0d,0xce,0x26,0x9f,
+  0x85,0xa2,0x06,0xab,0x86,0x0f,0x05,0x45,0xca,0xa6,0x28,0x9f,0x1e,0x7d,0xa5,0x44,
+  0x67,0xf3,0x86,0xc6,0x7a,0x41,0x3e,0x14,0xf4,0x95,0x3b,0x6b,0xb4,0x31,0xe0,0xe4,
+  0x73,0x09,0x69,0x50,0x27,0xad,0x18,0x2e,0x21,0x28,0xbe,0x30,0x58,0x98,0xf3,0x61,
+  0x66,0x54,0x71,0x7f,0x17,0x4b,0x72,0xb5,0x3f,0x9b,0x9c,0x09,0x83,0xd1,0x7f,0x1b,
+  0xe7,0xfa,0x23,0x76,0xae,0xea,0x47,0xc9,0x61,0x4b,0x83,0x64,0x76,0x8d,0xf0,0x44,
+  0x66,0x8d,0xa9,0xa4,0x91,0x62,0x7d,0x8c,0x7c,0xd8,0x36,0x58,0x28,0x46,0xa9,0x99,
+  0x19,0x89,0xd5,0xfe,0x6d,0x34,0x17,0x33,0x62,0x9c,0xd9,0x74,0xea,0x67,0x1a,0xc7,
+  0x4c,0xe4,0x43,0x25,0xd7,0x45,0xa2,0x97,0xed,0x58,0x3a,0x87,0xdb,0x34,0xdd,0xc3,
+  0x08,0xf5,0x1f,0xdf,0xed,0x3f,0x0a,0xcb,0xf5,0x8a,0x0e,0x93,0xda,0x03,0xf8,0x01,
+  0xcd,0xde,0xa4,0x16,0x0a,0xe4,0x43,0xed,0x65,0x26,0x24,0x53,0xac,0x87,0x6e,0x22,
+  0xaf,0xb7,0xa6,0xbc,0xc5,0x35,0xd8,0x90,0xc7,0xc5,0x3e,0x1c,0xd5,0x82,0x2d,0x79,
+  0x1d,0xcd,0x19,0xc7,0x38,0xf5,0x2c,0xbe,0x40,0x1a,0xf4,0xa2,0x0a,0xce,0x0b,0x58,
+  0x2d,0x7b,0xb0,0x5a,0xb0,0xed,0x5c,0x25,0x2c,0xec,0x89,0x3b,0x19,0x28,0x3a,0xf9,
+  0x60,0xfd,0x34,0x4d,0x91,0xc0,0x2d,0xa2,0xc1,0x8d,0xa5,0x12,0x1f,0xa6,0xc6,0xad,
+  0x9f,0x05,0xa9,0x86,0x8d,0x66,0xd7,0xf3,0x2b,0x32,0xee,0xfb,0x68,0x82,0x8a,0x54,
+  0xda,0x6f,0x76,0x8c,0xe9,0x1b,0x03,0xce,0xf5,0xc1,0xf7,0xcb,0xa0,0x11,0x4d,0x78,
+  0xf0,0x4b,0x13,0x06,0x8d,0x1f,0x45,0x5d,0x2c,0x42,0xac,0x31,0x82,0xa6,0x19,0x0f,
+  0x8c,0x51,0xce,0xf5,0xf1,0xa8,0xff,0x10,0x1f,0x82,0xc2,0x69,0x14,0x70,0x3e,0xf5,
+  0xe4,0x82,0xb0,0xa0,0xa8,0xc6,0xf8,0x10,0xf3,0xd9,0x3f,0x4d,0x7c,0x88,0xcd,0x60,
+  0x3f,0x32,0xd9,0x7c,0x0b,0xf9,0x10,0x52,0x3e,0xcc,0x41,0xd1,0xc9,0x47,0xec,0xe8,
+  0x3f,0xa5,0xb6,0x93,0x1b,0xe7,0xfa,0xa8,0xca,0x55,0x78,0x08,0x35,0xfa,0xe2,0x40,
+  0x32,0xf1,0x30,0x6b,0x3b,0x1e,0x99,0xf5,0xbc,0x23,0x39,0xf9,0x24,0xb8,0x4d,0x53,
+  0xb8,0x4d,0x9a,0xf6,0x0b,0x37,0x4e,0xfb,0x5b,0x70,0x5c,0xdc,0xc2,0x48,0xbc,0x95,
+  0xfe,0xcb,0xe9,0x3f,0x31,0x9e,0xe0,0x09,0x35,0xf5,0x4d,0xf5,0x91,0x7e,0xba,0x11,
+  0xa9,0xba,0x5f,0x95,0x30,0x84,0x48,0x79,0x64,0x7e,0x82,0x34,0xe2,0xd4,0x33,0xbe,
+  0x53,0x8f,0xa9,0xc9,0xb8,0x1a,0xcb,0xfb,0xd0,0x3e,0x3d,0xa9,0xaa,0x0d,0x5c,0xd6,
+  0x06,0x2f,0x46,0xf3,0x02,0xda,0xaa,0x4e,0x66,0xd3,0xc9,0x67,0x51,0x5e,0x19,0x86,
+  0xd1,0x52,0x08,0xdf,0xcb,0x64,0x80,0xa6,0x1e,0xa0,0x19,0x1a,0x73,0x37,0x33,0x6e,
+  0xff,0x51,0xc4,0x87,0x83,0x0a,0x3d,0xa7,0xdc,0xf9,0xd4,0xd0,0x89,0x14,0xd7,0xa7,
+  0xd7,0x49,0xf6,0x84,0xb5,0x25,0xa1,0x75,0xe7,0x6b,0x1f,0x41,0xb1,0x15,0xdc,0xcc,
+  0xb0,0xf0,0x81,0x1c,0xe3,0x43,0xec,0x3f,0x9d,0x8b,0xc1,0x8c,0xec,0x9e,0xf6,0xfd,
+  0x4e,0xec,0x37,0x64,0x57,0x04,0xca,0x1a,0x08,0x3a,0x32,0x0e,0x6c,0xc4,0xa9,0x1f,
+  0x2a,0xc0,0xfc,0xb9,0x83,0xbf,0x36,0x81,0x25,0x09,0xb6,0x36,0x45,0x6e,0x8a,0x7a,
+  0x00,0x69,0xb1,0x50,0x95,0xf9,0xb0,0x9f,0x19,0x1b,0x71,0xeb,0x67,0xa5,0x7a,0x41,
+  0xdd,0x7b,0xde,0x3a,0xaa,0x57,0x2a,0x55,0xf5,0xdb,0xf3,0x83,0x47,0x27,0x57,0xc4,
+  0x05,0x34,0xc7,0xd0,0x54,0x53,0xe3,0xe4,0x23,0x90,0x07,0x90,0x0f,0xf1,0xa6,0xff,
+  0xf3,0x1c,0xdd,0xfd,0x2f,0x37,0x0b,0x0c,0x78,0x2b,0x0f,0x1c,0xc9,0xf8,0x70,0xf7,
+  0xd9,0xb3,0xc4,0x87,0xcf,0xae,0x1d,0x31,0x7c,0xf8,0xc4,0xf0,0xe1,0xef,0x64,0x96,
+  0x9d,0xe5,0x70,0x2a,0xe3,0xc3,0x93,0x37,0xce,0x13,0x1f,0x6e,0xbf,0x3e,0x65,0xc0,
+  0xec,0x95,0xe5,0xc3,0x5f,0xb7,0x5f,0x6d,0x97,0x78,0xec,0x7d,0x65,0xb0,0xf0,0xe5,
+  0x3a,0x1e,0xf6,0xdf,0x14,0x14,0xe7,0x1e,0x2f,0x93,0x31,0x7c,0x68,0x22,0xdf,0xba,
+  0xeb,0x0d,0x16,0xfe,0xf3,0x37,0xa5,0x91,0x81,0xe2,0x0d,0x63,0x2c,0x1f,0x52,0xa4,
+  0xc4,0xab,0x27,0x33,0x3e,0x3c,0xb0,0xef,0xdc,0x9f,0x77,0xda,0xb4,0xfe,0xbb,0x73,
+  0xa3,0xcf,0xe9,0x85,0x39,0x6a,0x7e,0x78,0xf6,0x11,0x8e,0x58,0xf8,0xb6,0xc6,0xbf,
+  0x8b,0xf5,0x0f,0x3f,0x0a,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0xfa,0xd4,
+  0x65,0x66,0x07,0xc9,0xb3,0x03,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x7a,
+  0xb7,0xcc,0xec,0x50,0xe3,0xd9,0x81,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62,
+  0xbd,0x5b,0x66,0x76,0xf0,0xcc,0xec,0xf0,0xb1,0x53,0x61,0xb1,0x58,0x2c,0x16,0x8b,
+  0xc5,0x62,0xb1,0x58,0xff,0xa3,0x22,0xfa,0x7d,0x1c,0x3c,0xfb,0x23,0x02,0x4d,0xbf,
+  0x5a,0xa9,0x46,0xa0,0xde,0xfb,0xf3,0x84,0xf4,0xb5,0x13,0x11,0x6c,0x88,0xe2,0x98,
+  0x7f,0x7d,0xb9,0x73,0xdd,0x1b,0x3b,0x1c,0x29,0xc2,0xf0,0x33,0x01,0x00,
diff --git a/u-boot/board/esd/plu405/plu405.c b/u-boot/board/esd/plu405/plu405.c
new file mode 100644
index 0000000..109d2dc
--- /dev/null
+++ b/u-boot/board/esd/plu405/plu405.c
@@ -0,0 +1,361 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+#undef FPGA_DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to
+	 * 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	unsigned char *dst;
+	unsigned char fctr;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+		   (uchar *)fpgadata, &len) != 0) {
+		printf("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low "
+			       "after asserting PROGRAM*)\n");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high "
+			       "after deasserting PROGRAM*)\n");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high "
+			       "after programming FPGA)\n");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10);
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000);
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) &
+		 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Setup EEPROM write protection
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR,
+		 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)DUART0_BA + 4, 0x08);
+	out_8((void *)DUART1_BA + 4, 0x08);
+
+	/*
+	 * Enable auto RS485 mode in 2nd external uart
+	 */
+	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+	fctr |= 0x08;                       /* enable RS485 mode */
+	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
+	/*
+	 * Init magnetic couplers
+	 */
+	if (!getenv("noinitcoupler")) {
+		init_coupler(CAN0_BA);
+		init_coupler(CAN1_BA);
+	}
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts("Board: ");
+
+	if (i == -1)
+		puts("### No HW ID - assuming PLU405");
+	else
+		puts(str);
+
+	putc('\n');
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		out_be16((void *)FPGA_CTRL,
+			 in_be16((void *)FPGA_CTRL) &
+			 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		out_be16((void *)FPGA_CTRL,
+			 in_be16((void *)FPGA_CTRL) |
+			 CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *	       <state> -1: deliver current state
+ *			0: disable write
+ *			1: enable write
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
+ *		      0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) &
+				 ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) |
+				 CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = ((in_be32((void*)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP) == 0);
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR,
+			       state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if (argv[1][0] == '0') {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+						    0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+						    1);
+		}
+		if (state < 0)
+			puts("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/u-boot/board/esd/pmc405/Makefile b/u-boot/board/esd/pmc405/Makefile
new file mode 100644
index 0000000..36707f4
--- /dev/null
+++ b/u-boot/board/esd/pmc405/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+COBJS	= $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/pmc405/pmc405.c b/u-boot/board/esd/pmc405/pmc405.c
new file mode 100644
index 0000000..03143fe
--- /dev/null
+++ b/u-boot/board/esd/pmc405/pmc405.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2005-2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+	/*
+	 * EBC Configuration Register:
+	 * set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000);
+
+	/*
+	 * Setup GPIO pins
+	 */
+	mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
+					CONFIG_SYS_FPGA_DONE |
+					CONFIG_SYS_XEREADY |
+					CONFIG_SYS_NONMONARCH |
+					CONFIG_SYS_REV1_2) << 5));
+
+	if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
+		/* rev 1.2 boards */
+		mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
+						CONFIG_SYS_SELF_RST) << 5));
+	}
+
+	out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
+	/* setup for output */
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
+		 CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
+
+	/*
+	 * - check if rev1_2 is low, then:
+	 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
+	 *   in TCR to assert INTA# or SELFRST#
+	 */
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* deassert EREADY# */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
+	return (0);
+}
+
+ushort pmc405_pci_subsys_deviceid(void)
+{
+	ulong val;
+
+	val = in_be32((void *)GPIO0_IR);
+	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+		/* check monarch# signal */
+		if (val & CONFIG_SYS_NONMONARCH)
+			return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
+		return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
+	}
+	return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	ulong val;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1)
+		puts ("### No HW ID - assuming PMC405");
+	else
+		puts(str);
+
+	val = in_be32((void *)GPIO0_IR);
+	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+		puts(" rev1.2 (");
+		if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
+			puts("non-");
+		puts("monarch)");
+	} else
+		puts(" <=rev1.1");
+
+	putc ('\n');
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/u-boot/board/esd/pmc405de/Makefile b/u-boot/board/esd/pmc405de/Makefile
new file mode 100644
index 0000000..2833844
--- /dev/null
+++ b/u-boot/board/esd/pmc405de/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+COBJS-y += ../common/cmd_loadpci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/pmc405de/chip_config.c b/u-boot/board/esd/pmc405de/chip_config.c
new file mode 100644
index 0000000..e93a32c
--- /dev/null
+++ b/u-boot/board/esd/pmc405de/chip_config.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"133",
+		"CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+		{
+			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
+		}
+	},
+	{
+		"266",
+		"CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+		{
+			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
+		}
+	},
+	{
+		"333",
+		"CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
+		{
+			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/esd/pmc405de/pmc405de.c b/u-boot/board/esd/pmc405de/pmc405de.c
new file mode 100644
index 0000000..c266ebe
--- /dev/null
+++ b/u-boot/board/esd/pmc405de/pmc405de.c
@@ -0,0 +1,521 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pci.h>
+#include <command.h>
+#include <malloc.h>
+
+/*
+ * PMC405-DE cpld registers
+ * - all registers are 8 bit
+ * - all registers are on 32 bit addesses
+ */
+struct pmc405de_cpld {
+	/* cpld design version */
+	u8 version;
+	u8 reserved0[3];
+
+	/* misc. status lines */
+	u8 status;
+	u8 reserved1[3];
+
+	/*
+	 * gated control flags
+	 * gate bit(s) must be written with '1' to
+	 * access control flag
+	 */
+	u8 control;
+	u8 reserved2[3];
+};
+
+#define CPLD_VERSION_MASK		0x0f
+#define CPLD_CONTROL_POSTLED_N		0x01
+#define CPLD_CONTROL_POSTLED_GATE	0x02
+#define CPLD_CONTROL_RESETOUT_N		0x40
+#define CPLD_CONTROL_RESETOUT_N_GATE	0x80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+extern void pll_write(u32 a, u32 b);
+
+static int wait_for_pci_ready_done;
+
+static int is_monarch(void);
+static int pci_is_66mhz(void);
+static int board_revision(void);
+static int cpld_revision(void);
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
+
+int board_early_init_f(void)
+{
+	u32 pllmr0, pllmr1;
+
+	/*
+	 * check M66EN and patch PLB:PCI divider for 66MHz PCI
+	 *
+	 * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
+	 * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
+	 * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
+	 * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
+	 *
+	 * calling upd_plb_pci_div() may end in calling pll_write() which will
+	 * do a chip reset and never return.
+	 */
+	pllmr0 = mfdcr(CPC0_PLLMR0);
+	pllmr1 = mfdcr(CPC0_PLLMR1);
+
+	if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
+		/* fCPU=333MHz, fPLB=111MHz */
+		if (pci_is_66mhz())
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
+		else
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+	} else {
+		/* fCPU=133|266MHz, fPLB=133MHz */
+		if (pci_is_66mhz())
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+		else
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
+	}
+
+	/*
+	 * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0, INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register:
+	 * - set ready timeout to 512 ebc-clks -> ca. 15 us
+	 * - EBC lines are always driven
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);
+
+	return 0;
+}
+
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
+{
+	if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
+		pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
+}
+
+int misc_init_r(void)
+{
+	int i;
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	struct pmc405de_cpld *cpld =
+		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+	if (!is_monarch()) {
+		/* PCI configuration done: release EREADY */
+		setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
+		setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
+	}
+
+	/* turn off POST LED */
+	out_8(&cpld->control,
+	      CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
+
+	/* turn on LEDs: RUN, A, B */
+	clrbits_be32(&gpio0->or,
+		     CONFIG_SYS_GPIO_LEDRUN_N |
+		     CONFIG_SYS_GPIO_LEDA_N |
+		     CONFIG_SYS_GPIO_LEDB_N);
+
+	for (i=0; i < 200; i++)
+		udelay(1000);
+
+	/* turn off LEDs: A, B */
+	setbits_be32(&gpio0->or,
+		     CONFIG_SYS_GPIO_LEDA_N |
+		     CONFIG_SYS_GPIO_LEDB_N);
+
+	return (0);
+}
+
+static int is_monarch(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
+}
+
+static int pci_is_66mhz(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
+}
+
+static int board_revision(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
+		CONFIG_SYS_GPIO_HWREV_SHIFT);
+}
+
+static int cpld_revision(void)
+{
+	struct pmc405de_cpld *cpld =
+		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+	return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	puts("Board: esd GmbH - PMC-CPU/405-DE");
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld, ", gd->board_type);
+
+	if (!is_monarch())
+		puts("non-");
+
+	printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
+	       pci_is_66mhz() ? "66" : "33", cpld_revision());
+
+	return 0;
+}
+
+
+static void wait_for_pci_ready(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	int i;
+	char *s = getenv("pcidelay");
+
+	/* only wait once */
+	if (wait_for_pci_ready_done)
+		return;
+
+	/*
+	 * We have our own handling of the pcidelay variable.
+	 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+	 * and adapter devices. For adapter devices we do not
+	 * want this.
+	 */
+	if (s) {
+		int ms = simple_strtoul(s, NULL, 10);
+		printf("PCI:   Waiting for %d ms\n", ms);
+		for (i=0; i<ms; i++)
+			udelay(1000);
+	}
+
+	if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
+		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
+		while (1) {
+			if (ctrlc()) {
+				puts("abort\n");
+				break;
+			}
+			if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
+				printf("done\n");
+				break;
+			}
+		}
+	}
+
+	wait_for_pci_ready_done = 1;
+}
+
+/*
+ * Overwrite weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+	char *s;
+
+	if (!is_monarch()) {
+		/*
+		 * Overwrite PCI identification when running in
+		 * non-monarch mode
+		 * This should be moved into pci_target_init()
+		 * when it is sometimes available for 405 CPUs
+		 */
+		pci_write_config_word(PCIDEVID_405GP,
+				      PCI_SUBSYSTEM_ID,
+				      CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+		pci_write_config_word(PCIDEVID_405GP,
+				      PCI_CLASS_SUB_CODE,
+				      CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+	}
+
+	s = getenv("pciscan");
+	if (s == NULL) {
+		if (is_monarch()) {
+			wait_for_pci_ready();
+			return 1;
+		} else {
+			return 0;
+		}
+	} else {
+		if (!strcmp(s, "yes"))
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Overwrite weak pci_pre_init()
+ *
+ * The default implementation enables the 405EP
+ * internal PCI arbiter. We do not want that
+ * on a PMC module.
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+	return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in non-monarch mode.
+	 */
+	if (!is_monarch()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *                      0: disable write
+ *                      1: enable write
+ * Returns:            -1: wrong device address
+ *                      0: dis-/en- able done
+ *                    0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32(&gpio0->or) &
+				       CONFIG_SYS_GPIO_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR,
+				state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable(
+				CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(
+				CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0)
+			puts ("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+extern env_t *env_ptr;
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 pram, nextbase, base;
+	char *v;
+	u32 param;
+	ulong *lptr;
+
+	v = getenv("pram");
+	if (v)
+		pram = simple_strtoul(v, NULL, 10);
+	else {
+		printf("Error: pram undefined. Please define pram in KiB\n");
+		return 1;
+	}
+
+	base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+	/*
+	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
+	 */
+	param = base - (pram << 10);
+	printf("PARAM: @%08x\n", param);
+	debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+
+	/* clear entire PA ram */
+	memset((void*)param, 0, (pram << 10));
+
+	/* reserve 4k for pointer field */
+	nextbase = base - 4096;
+	lptr = (ulong*)(base);
+
+	/*
+	 * *(--lptr) = item_size;
+	 * *(--lptr) = base - item_base = distance from field top;
+	 */
+
+	/* env is first (4k aligned) */
+	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+	memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
+	*(--lptr) = base - nextbase;  /* offset | type=0 */
+
+	/* free section */
+	*(--lptr) = nextbase - param; /* size */
+	*(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+	/* terminate pointer field */
+	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+	*(--lptr) = 0;                /* offset=0 -> terminator */
+	return 0;
+}
+U_BOOT_CMD(
+	painit,	1,	1,	do_painit,
+	"prepare PciAccess system",
+	""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
+	return 0;
+}
+U_BOOT_CMD(
+	selfreset,	1,	1,	do_selfreset,
+	"assert self-reset# signal",
+	""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct pmc405de_cpld *cpld =
+		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+	if (argc > 1) {
+		if (argv[1][0] == '0') {
+			/* assert */
+			printf("PMC-RESETOUT# asserted\n");
+			out_8(&cpld->control,
+			      CPLD_CONTROL_RESETOUT_N_GATE);
+		} else {
+			/* deassert */
+			printf("PMC-RESETOUT# deasserted\n");
+			out_8(&cpld->control,
+			      CPLD_CONTROL_RESETOUT_N |
+			      CPLD_CONTROL_RESETOUT_N_GATE);
+		}
+	} else {
+		printf("PMC-RESETOUT# is %s\n",
+		       (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
+		       "inactive" : "active");
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	resetout,	2,	1,	do_resetout,
+	"assert PMC-RESETOUT# signal",
+	""
+);
diff --git a/u-boot/board/esd/pmc440/Makefile b/u-boot/board/esd/pmc440/Makefile
new file mode 100644
index 0000000..f640d1e
--- /dev/null
+++ b/u-boot/board/esd/pmc440/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
+	../common/cmd_loadpci.o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/pmc440/cmd_pmc440.c b/u-boot/board/esd/pmc440/cmd_pmc440.c
new file mode 100644
index 0000000..200d7ee
--- /dev/null
+++ b/u-boot/board/esd/pmc440/cmd_pmc440.c
@@ -0,0 +1,557 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#if defined(CONFIG_LOGBUFFER)
+#include <logbuff.h>
+#endif
+
+#include "pmc440.h"
+
+int is_monarch(void);
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt);
+int eeprom_write_enable(unsigned dev_addr, int state);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_BSP)
+
+static int got_fifoirq;
+static int got_hcirq;
+
+int fpga_interrupt(u32 arg)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
+	int rc = -1; /* not for us */
+	u32 status = FPGA_IN32(&fpga->status);
+
+	/* check for interrupt from fifo module */
+	if (status & STATUS_FIFO_ISF) {
+		/* disable this int source */
+		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+		rc = 0;
+		got_fifoirq = 1; /* trigger backend */
+	}
+
+	if (status & STATUS_HOST_ISF) {
+		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+		rc = 0;
+		got_hcirq = 1;
+	}
+
+	return rc;
+}
+
+int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	got_hcirq = 0;
+
+	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+
+	irq_install_handler(IRQ0_FPGA,
+			    (interrupt_handler_t *)fpga_interrupt,
+			    fpga);
+
+	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
+
+	while (!got_hcirq) {
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			break;
+		}
+	}
+	if (got_hcirq)
+		printf("Got interrupt!\n");
+
+	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+	irq_free_handler(IRQ0_FPGA);
+	return 0;
+}
+U_BOOT_CMD(
+	waithci,	1,	1,	do_waithci,
+	"Wait for host control interrupt",
+	""
+);
+
+void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
+{
+	u32 ctrl;
+
+	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
+		printf("%5d  %d    %3d  %08x",
+		       (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+		       FPGA_IN32(&fpga->fifo[f].data));
+		if (ctrl & FIFO_OVERFLOW) {
+			printf(" OVERFLOW\n");
+			FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
+		} else
+			printf("\n");
+	}
+}
+
+int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+	int i;
+	int n = 0;
+	u32 ctrl, data, f;
+	char str[] = "\\|/-";
+	int abort = 0;
+	int count = 0;
+	int count2 = 0;
+
+	switch (argc) {
+	case 1:
+		/* print all fifos status information */
+		printf("fifo level status\n");
+		printf("______________________________\n");
+		for (i=0; i<FIFO_COUNT; i++) {
+			ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
+			printf(" %d    %3d  %s%s%s %s\n",
+			       i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+			       ctrl & FIFO_FULL ? "FULL     " : "",
+			       ctrl & FIFO_EMPTY ? "EMPTY    " : "",
+			       ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
+			       ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
+		}
+		break;
+
+	case 2:
+		/* completely read out fifo 'n' */
+		if (!strcmp(argv[1],"read")) {
+			printf("  #   fifo level data\n");
+			printf("______________________________\n");
+
+			for (i=0; i<FIFO_COUNT; i++)
+				dump_fifo(fpga, i, &n);
+
+		} else if (!strcmp(argv[1],"wait")) {
+			got_fifoirq = 0;
+
+			irq_install_handler(IRQ0_FPGA,
+					    (interrupt_handler_t *)fpga_interrupt,
+					    fpga);
+
+			printf("  #   fifo level data\n");
+			printf("______________________________\n");
+
+			/* enable all fifo interrupts */
+			FPGA_OUT32(&fpga->hostctrl,
+				   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+			for (i=0; i<FIFO_COUNT; i++) {
+				/* enable interrupts from all fifos */
+				FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+			}
+
+			while (1) {
+				/* wait loop */
+				while (!got_fifoirq) {
+					count++;
+					if (!(count % 100)) {
+						count2++;
+						putc(0x08); /* backspace */
+						putc(str[count2 % 4]);
+					}
+
+					/* Abort if ctrl-c was pressed */
+					if ((abort = ctrlc())) {
+						puts("\nAbort\n");
+						break;
+					}
+					udelay(1000);
+				}
+				if (abort)
+					break;
+
+				/* simple fifo backend */
+				if (got_fifoirq) {
+					for (i=0; i<FIFO_COUNT; i++)
+						dump_fifo(fpga, i, &n);
+
+					got_fifoirq = 0;
+					/* unmask global fifo irq */
+					FPGA_OUT32(&fpga->hostctrl,
+						   HOSTCTRL_FIFOIE_GATE |
+						   HOSTCTRL_FIFOIE_FLAG);
+				}
+			}
+
+			/* disable all fifo interrupts */
+			FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+			for (i=0; i<FIFO_COUNT; i++)
+				FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+
+			irq_free_handler(IRQ0_FPGA);
+
+		} else {
+			printf("Usage:\nfifo %s\n", cmdtp->help);
+			return 1;
+		}
+		break;
+
+	case 4:
+	case 5:
+		if (!strcmp(argv[1],"write")) {
+			/* get fifo number or fifo address */
+			f = simple_strtoul(argv[2], NULL, 16);
+
+			/* data paramter */
+			data = simple_strtoul(argv[3], NULL, 16);
+
+			/* get optional count parameter */
+			n = 1;
+			if (argc >= 5)
+				n = (int)simple_strtoul(argv[4], NULL, 10);
+
+			if (f < FIFO_COUNT) {
+				printf("writing %d x %08x to fifo %d\n",
+				       n, data, f);
+				for (i=0; i<n; i++)
+					FPGA_OUT32(&fpga->fifo[f].data, data);
+			} else {
+				printf("writing %d x %08x to fifo port at "
+				       "address %08x\n",
+				       n, data, f);
+				for (i=0; i<n; i++)
+					out_be32((void *)f, data);
+			}
+		} else {
+			printf("Usage:\nfifo %s\n", cmdtp->help);
+			return 1;
+		}
+		break;
+
+	default:
+		printf("Usage:\nfifo %s\n", cmdtp->help);
+		return 1;
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	fifo,	5,	1,	do_fifo,
+	"Fifo module operations",
+	"wait\nfifo read\n"
+	"fifo write fifo(0..3) data [cnt=1]\n"
+	"fifo write address(>=4) data [cnt=1]\n"
+	"  - without arguments: print all fifo's status\n"
+	"  - with 'wait' argument: interrupt driven read from all fifos\n"
+	"  - with 'read' argument: read current contents from all fifos\n"
+	"  - with 'write' argument: write 'data' 'cnt' times to "
+	"'fifo' or 'address'"
+);
+
+int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong sdsdp[5];
+	ulong delay;
+	int count=16;
+
+	if (argc < 2) {
+		printf("Usage:\nsbe %s\n", cmdtp->help);
+		return -1;
+	}
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "400")) {
+			/* PLB=133MHz, PLB/PCI=3 */
+			printf("Bootstrapping for 400MHz\n");
+			sdsdp[0]=0x8678624e;
+			sdsdp[1]=0x095fa030;
+			sdsdp[2]=0x40082350;
+			sdsdp[3]=0x0d050000;
+		} else if (!strcmp(argv[1], "533")) {
+			/* PLB=133MHz, PLB/PCI=3 */
+			printf("Bootstrapping for 533MHz\n");
+			sdsdp[0]=0x87788252;
+			sdsdp[1]=0x095fa030;
+			sdsdp[2]=0x40082350;
+			sdsdp[3]=0x0d050000;
+		} else if (!strcmp(argv[1], "667")) {
+			/* PLB=133MHz, PLB/PCI=3 */
+			printf("Bootstrapping for 667MHz\n");
+			sdsdp[0]=0x8778a256;
+			sdsdp[1]=0x095fa030;
+			sdsdp[2]=0x40082350;
+			sdsdp[3]=0x0d050000;
+		} else {
+			printf("Usage:\nsbe %s\n", cmdtp->help);
+			return -1;
+		}
+	}
+
+	if (argc > 2) {
+		sdsdp[4] = 0;
+		if (argv[2][0]=='1')
+			sdsdp[4]=0x19750100;
+		else if (argv[2][0]=='0')
+			sdsdp[4]=0x19750000;
+		if (sdsdp[4])
+			count += 4;
+	}
+
+	if (argc > 3) {
+		delay = simple_strtoul(argv[3], NULL, 10);
+		if (delay > 20)
+			delay = 20;
+		sdsdp[4] |= delay;
+	}
+
+	printf("Writing boot EEPROM ...\n");
+	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+				   0, (uchar*)sdsdp, count) != 0)
+		printf("bootstrap_eeprom_write failed\n");
+	else
+		printf("done (dump via 'i2c md 52 0.1 14')\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	sbe, 4, 0, do_setup_bootstrap_eeprom,
+	"setup bootstrap eeprom",
+	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
+);
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+extern env_t *env_ptr;
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 pram, nextbase, base;
+	char *v;
+	u32 param;
+	ulong *lptr;
+
+	v = getenv("pram");
+	if (v)
+		pram = simple_strtoul(v, NULL, 10);
+	else {
+		printf("Error: pram undefined. Please define pram in KiB\n");
+		return 1;
+	}
+
+	base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+	/*
+	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
+	 */
+	param = base - (pram << 10);
+	printf("PARAM: @%08x\n", param);
+	debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+
+	/* clear entire PA ram */
+	memset((void*)param, 0, (pram << 10));
+
+	/* reserve 4k for pointer field */
+	nextbase = base - 4096;
+	lptr = (ulong*)(base);
+
+	/*
+	 * *(--lptr) = item_size;
+	 * *(--lptr) = base - item_base = distance from field top;
+	 */
+
+	/* env is first (4k aligned) */
+	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+	memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
+	*(--lptr) = base - nextbase;  /* offset | type=0 */
+
+	/* free section */
+	*(--lptr) = nextbase - param; /* size */
+	*(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+	/* terminate pointer field */
+	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+	*(--lptr) = 0;                /* offset=0 -> terminator */
+	return 0;
+}
+U_BOOT_CMD(
+	painit,	1,	1,	do_painit,
+	"prepare PciAccess system",
+	""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	in_be32((void*)CONFIG_SYS_RESET_BASE);
+	return 0;
+}
+U_BOOT_CMD(
+	selfreset,	1,	1,	do_selfreset,
+	"assert self-reset# signal",
+	""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	/* requiers bootet FPGA and PLD_IOEN_N active */
+	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
+		printf("Error: resetout requires a bootet FPGA\n");
+		return -1;
+	}
+
+	if (argc > 1) {
+		if (argv[1][0] == '0') {
+			/* assert */
+			printf("PMC-RESETOUT# asserted\n");
+			FPGA_OUT32(&fpga->hostctrl,
+				   HOSTCTRL_PMCRSTOUT_GATE);
+		} else {
+			/* deassert */
+			printf("PMC-RESETOUT# deasserted\n");
+			FPGA_OUT32(&fpga->hostctrl,
+				   HOSTCTRL_PMCRSTOUT_GATE |
+				   HOSTCTRL_PMCRSTOUT_FLAG);
+		}
+	} else {
+		printf("PMC-RESETOUT# is %s\n",
+		       FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
+		       "inactive" : "active");
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	resetout,	2,	1,	do_resetout,
+	"assert PMC-RESETOUT# signal",
+	""
+);
+
+int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (is_monarch()) {
+		printf("This command is only supported in non-monarch mode\n");
+		return -1;
+	}
+
+	if (argc > 1) {
+		if (argv[1][0] == '0') {
+			/* assert */
+			printf("inta# asserted\n");
+			out_be32((void*)GPIO1_TCR,
+				 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
+		} else {
+			/* deassert */
+			printf("inta# deasserted\n");
+			out_be32((void*)GPIO1_TCR,
+				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
+		}
+	} else {
+		printf("inta# is %s\n",
+		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
+		       "active" : "inactive");
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	inta,	2,	1,	do_inta,
+	"Assert/Deassert or query INTA# state in non-monarch mode",
+	""
+);
+
+/* test-only */
+int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong pciaddr;
+
+	if (argc > 1) {
+		pciaddr = simple_strtoul(argv[1], NULL, 16);
+
+		pciaddr &= 0xf0000000;
+
+		/* map PCI address at 0xc0000000 in PLB space */
+
+		/* PMM1 Mask/Attribute - disabled b4 setting */
+		out32r(PCIL0_PMM1MA, 0x00000000);
+		/* PMM1 Local Address */
+		out32r(PCIL0_PMM1LA, 0xc0000000);
+		/* PMM1 PCI Low Address */
+		out32r(PCIL0_PMM1PCILA, pciaddr);
+		/* PMM1 PCI High Address */
+		out32r(PCIL0_PMM1PCIHA, 0x00000000);
+		/* 256MB + No prefetching, and enable region */
+		out32r(PCIL0_PMM1MA, 0xf0000001);
+	} else {
+		printf("Usage:\npmm %s\n", cmdtp->help);
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	pmm,	2,	1,	do_pmm,
+	"Setup pmm[1] registers",
+	"<pciaddr> (pciaddr will be aligned to 256MB)"
+);
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#endif /* CONFIG_CMD_BSP */
diff --git a/u-boot/board/esd/pmc440/config.mk b/u-boot/board/esd/pmc440/config.mk
new file mode 100644
index 0000000..24f74e1
--- /dev/null
+++ b/u-boot/board/esd/pmc440/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/esd/pmc440/fpga.c b/u-boot/board/esd/pmc440/fpga.c
new file mode 100644
index 0000000..f92bbff
--- /dev/null
+++ b/u-boot/board/esd/pmc440/fpga.c
@@ -0,0 +1,462 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spartan2.h>
+#include <spartan3.h>
+#include <command.h>
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#define USE_SP_CODE
+
+#ifdef USE_SP_CODE
+Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_init_fn,
+	NULL, /* err */
+	fpga_done_fn,
+	fpga_clk_fn,
+	fpga_cs_fn,
+	fpga_wr_fn,
+	NULL, /* rdata */
+	fpga_wdata_fn,
+	fpga_busy_fn,
+	fpga_abort_fn,
+	fpga_post_config_fn,
+};
+#else
+Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_post_config_fn,
+};
+#endif
+
+Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+	ngcc_fpga_pre_config_fn,
+	ngcc_fpga_pgm_fn,
+	ngcc_fpga_clk_fn,
+	ngcc_fpga_init_fn,
+	ngcc_fpga_done_fn,
+	ngcc_fpga_wr_fn,
+	ngcc_fpga_post_config_fn
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	XILINX_XC3S1200E_DESC(
+#ifdef USE_SP_CODE
+		slave_parallel,
+#else
+		slave_serial,
+#endif
+		(void *)&pmc440_fpga_fns,
+		0),
+	XILINX_XC2S200_DESC(
+		slave_serial,
+		(void *)&ngcc_fpga_fns,
+		0)
+};
+
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void fpga_reset(int assert)
+{
+	debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	if (assert) {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+		debug("asserted\n");
+	} else {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+		debug("deasserted\n");
+	}
+}
+
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void fpga_serialslave_init(void)
+{
+	debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
+	      __LINE__);
+	fpga_pgm_fn(FALSE, FALSE, 0);	/* make sure program pin is inactive */
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	debug("%s:%d: FPGA PROGRAM ",
+	      __FUNCTION__, __LINE__);
+
+	if (assert) {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
+		debug("asserted\n");
+	} else {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
+		debug("deasserted\n");
+	}
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
+		return 0;
+	else
+		return 1;
+}
+
+#ifdef USE_SP_CODE
+int fpga_abort_fn(int cookie)
+{
+	return 0;
+}
+
+
+int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+	return assert_cs;
+}
+
+
+int fpga_busy_fn(int cookie)
+{
+	return 1;
+}
+#endif
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
+		return 1;
+	else
+		return 0;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int fpga_pre_config_fn(int cookie)
+{
+	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset(TRUE);
+
+	/* release init# */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
+	/* disable PLD IOs */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int fpga_post_config_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+	int rc=0;
+	char *s;
+
+	debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+	/* enable PLD0..7 pins */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
+
+	fpga_reset(TRUE);
+	udelay (100);
+	fpga_reset(FALSE);
+	udelay (100);
+
+	FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
+
+	/* NGCC/CANDES only: enable ledlink */
+	if ((s = getenv("bd_type")) &&
+	    ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
+		FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+	return rc;
+}
+
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	if (assert_clk)
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
+	else
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
+
+	return assert_clk;
+}
+
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	if (assert_write)
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+	else
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+
+	return assert_write;
+}
+
+#ifdef USE_SP_CODE
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+	uchar val = data;
+	ulong or = in_be32((void*)GPIO1_OR);
+	int i = 7;
+	do {
+		/* Write data */
+		if (val & 0x80)
+			or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+		else
+			or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+		out_be32((void*)GPIO1_OR, or);
+
+		/* Assert the clock */
+		or |= GPIO1_FPGA_CLK;
+		out_be32((void*)GPIO1_OR, or);
+		val <<= 1;
+		i --;
+	} while (i > 0);
+
+	/* Write last data bit (the 8th clock comes from the sp_load() code */
+	if (val & 0x80)
+		or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+	else
+		or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+	out_be32((void*)GPIO1_OR, or);
+
+	return 0;
+}
+#endif
+
+#define NGCC_FPGA_PRG  CLOCK_EN
+#define NGCC_FPGA_DATA RESET_OUT
+#define NGCC_FPGA_DONE CLOCK_IN
+#define NGCC_FPGA_INIT IRIGB_R_IN
+#define NGCC_FPGA_CLK  CLOCK_OUT
+
+void ngcc_fpga_serialslave_init(void)
+{
+	debug("%s:%d: Initialize serial slave interface\n",
+	      __FUNCTION__, __LINE__);
+
+	/* make sure program pin is inactive */
+	ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
+}
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void ngcc_fpga_reset(int assert)
+{
+	debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+		debug("asserted\n");
+	} else {
+		FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+		debug("deasserted\n");
+	}
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+		debug("asserted\n");
+	} else {
+		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+		debug("deasserted\n");
+	}
+
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int ngcc_fpga_init_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
+		debug("high\n");
+		return 0;
+	} else {
+		debug("low\n");
+		return 1;
+	}
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int ngcc_fpga_done_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
+		debug("DONE high\n");
+		return 1;
+	} else {
+		debug("low\n");
+		return 0;
+	}
+}
+
+
+/*
+ * FPGA pre-configuration function.
+ */
+int ngcc_fpga_pre_config_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+
+	ngcc_fpga_reset(TRUE);
+	FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
+
+	ngcc_fpga_reset(TRUE);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int ngcc_fpga_post_config_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+	udelay (100);
+	ngcc_fpga_reset(FALSE);
+
+	FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+	return 0;
+}
+
+
+int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	if (assert_clk)
+		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+	else
+		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+
+	return assert_clk;
+}
+
+
+int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	if (assert_write)
+		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+	else
+		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+
+	return assert_write;
+}
+
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int pmc440_init_fpga(void)
+{
+	char *s;
+
+	debug("%s:%d: Initialize FPGA interface\n",
+	      __FUNCTION__, __LINE__);
+	fpga_init();
+
+	fpga_serialslave_init ();
+	debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
+	fpga_add (fpga_xilinx, &fpga[0]);
+
+	/* NGCC only */
+	if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
+		ngcc_fpga_serialslave_init ();
+		debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
+		fpga_add (fpga_xilinx, &fpga[1]);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_FPGA */
diff --git a/u-boot/board/esd/pmc440/fpga.h b/u-boot/board/esd/pmc440/fpga.h
new file mode 100644
index 0000000..d61a3cf
--- /dev/null
+++ b/u-boot/board/esd/pmc440/fpga.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern int pmc440_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_wdata_fn (uchar data, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
+
+extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int ngcc_fpga_init_fn(int cookie);
+extern int ngcc_fpga_done_fn(int cookie);
+extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int ngcc_fpga_pre_config_fn(int cookie );
+extern int ngcc_fpga_post_config_fn(int cookie );
diff --git a/u-boot/board/esd/pmc440/init.S b/u-boot/board/esd/pmc440/init.S
new file mode 100644
index 0000000..b99a8e9
--- /dev/null
+++ b/u-boot/board/esd/pmc440/init.S
@@ -0,0 +1,118 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ */
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+#ifndef CONFIG_NAND_SPL
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+#else
+	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
+#endif
+
+	/* TLB entries for DDR2 SDRAM are generated dynamically */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+	/* TLB-entries for EBC */
+	/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
+	 * tlb entry.
+	 * This dummy entry is only for convinience in order not to modify the
+	 * amount of entries. Currently OS/9 relies on this :-)
+	 */
+	tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for NAND */
+	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
+
+	/*TLB-entry PCI registers*/
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	/* TLB-entry PCI IO space */
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
+
+	/* TODO:  what about high IO space */
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
+#define TLB02	TLB2(AC_RWX | SA_IG)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/u-boot/board/esd/pmc440/pmc440.c b/u-boot/board/esd/pmc440/pmc440.c
new file mode 100644
index 0000000..5236f44
--- /dev/null
+++ b/u-boot/board/esd/pmc440/pmc440.c
@@ -0,0 +1,904 @@
+/*
+ * (Cg) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ * Based on board/amcc/sequoia/sequoia.c
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#ifdef CONFIG_RESET_PHY_R
+#include <miiphy.h>
+#endif
+#include <serial.h>
+#include <asm/4xx_pci.h>
+
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+ulong flash_get_size(ulong base, int banknum);
+int pci_is_66mhz(void);
+int is_monarch(void);
+int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+			  uchar *buffer, unsigned cnt);
+
+struct serial_device *default_serial_console(void)
+{
+	uchar buf[4];
+	ulong delay;
+	int i;
+	ulong val;
+
+	/*
+	 * Use default console on P4 when strapping jumper
+	 * is installed (bootstrap option != 'H').
+	 */
+	mfsdr(SDR0_PINSTP, val);
+	if (((val & 0xf0000000) >> 29) != 7)
+		return &eserial2_device;
+
+	ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
+	if (!(scratchreg & 0x80)) {
+		/* mark scratchreg valid */
+		scratchreg = (scratchreg & 0xffffff00) | 0x80;
+
+		i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+					  0x10, buf, 4);
+		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
+			scratchreg |= buf[2];
+
+			/* bringup delay for console */
+			for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
+				udelay(1000);
+			}
+		} else
+			scratchreg |= 0x01;
+		out_be32((void*)GPIO0_ISR3L, scratchreg);
+	}
+
+	if (scratchreg & 0x01)
+		return &eserial2_device;
+	else
+		return &eserial1_device;
+}
+
+int board_early_init_f(void)
+{
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	/* general EBC configuration (disable EBC timeouts) */
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xf8400000);
+
+	/*
+	 * Setup the GPIO pins
+	 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
+	 */
+	out_be32((void *)GPIO0_OR,    0x40000102);
+	out_be32((void *)GPIO0_TCR,   0x4c90011f);
+	out_be32((void *)GPIO0_OSRL,  0x28051400);
+	out_be32((void *)GPIO0_OSRH,  0x55005000);
+	out_be32((void *)GPIO0_TSRL,  0x08051400);
+	out_be32((void *)GPIO0_TSRH,  0x55005000);
+	out_be32((void *)GPIO0_ISR1L, 0x54000000);
+	out_be32((void *)GPIO0_ISR1H, 0x00000000);
+	out_be32((void *)GPIO0_ISR2L, 0x44000000);
+	out_be32((void *)GPIO0_ISR2H, 0x00000100);
+	out_be32((void *)GPIO0_ISR3L, 0x00000000);
+	out_be32((void *)GPIO0_ISR3H, 0x00000000);
+
+	out_be32((void *)GPIO1_OR,    0x80002408);
+	out_be32((void *)GPIO1_TCR,   0xd6003c08);
+	out_be32((void *)GPIO1_OSRL,  0x0a5a0000);
+	out_be32((void *)GPIO1_OSRH,  0x00000000);
+	out_be32((void *)GPIO1_TSRL,  0x00000000);
+	out_be32((void *)GPIO1_TSRH,  0x00000000);
+	out_be32((void *)GPIO1_ISR1L, 0x00005555);
+	out_be32((void *)GPIO1_ISR1H, 0x40000000);
+	out_be32((void *)GPIO1_ISR2L, 0x04010000);
+	out_be32((void *)GPIO1_ISR2H, 0x00000000);
+	out_be32((void *)GPIO1_ISR3L, 0x01400000);
+	out_be32((void *)GPIO1_ISR3H, 0x00000000);
+
+	/* patch PLB:PCI divider for 66MHz PCI */
+	mfcpr(CPR0_SPCID, reg);
+	if (pci_is_66mhz() && (reg != 0x02000000)) {
+		mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
+
+		mfcpr(CPR0_ICFG, reg);
+		reg |= CPR0_ICFG_RLI_MASK;
+		mtcpr(CPR0_ICFG, reg);
+
+		mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
+	}
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ef);
+	mtdcr(UIC0TR, 0x00000000);
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffc7f5);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0x27ffffff);
+	mtdcr(UIC2TR, 0x00000000);
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_4;
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_4;
+
+	/* enable 2nd IIC */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_F)
+int misc_init_f(void)
+{
+	struct pci_controller hose;
+	hose.first_busno = 0;
+	hose.last_busno = 0;
+	hose.region_count = 0;
+
+	if (getenv("pciearly") && (!is_monarch())) {
+		printf("PCI:   early target init\n");
+		pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
+		pci_target_init(&hose);
+	}
+	return 0;
+}
+#endif
+
+/*
+ * misc_init_r.
+ */
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val = 0;
+	u32 reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_srst0, sdr0_srst1;
+	char *act = getenv("usbact");
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtdcr(EBC0_CFGADDR, PB2CR);
+#else
+	mtdcr(EBC0_CFGADDR, PB0CR);
+#endif
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtdcr(EBC0_CFGADDR, PB2CR);
+#else
+	mtdcr(EBC0_CFGADDR, PB0CR);
+#endif
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+#endif
+
+	/*
+	 * USB suff...
+	 */
+	if ((act == NULL || strcmp(act, "host") == 0) &&
+	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
+		/* SDR Setting */
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+		/*
+		 * An 8-bit/60MHz interface is the only possible alternative
+		 * when connecting the Device to the PHY
+		 */
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		/*
+		 * Take USB out of reset:
+		 * -Initial status = all cores are in reset
+		 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+		 * -wait 1 ms
+		 * -deassert reset to PHY
+		 * -wait 1 ms
+		 * -deassert  reset to HOST
+		 * -wait 4 ms
+		 * -deassert all other resets
+		 */
+		mfsdr(SDR0_SRST1, sdr0_srst1);
+		sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |	\
+				SDR0_SRST1_P4OPB0 |	\
+				SDR0_SRST1_OPBA2 |	\
+				SDR0_SRST1_PLB42OPB1 |	\
+				SDR0_SRST1_OPB2PLB40);
+		mtsdr(SDR0_SRST1, sdr0_srst1);
+		udelay(1000);
+
+		mfsdr(SDR0_SRST1, sdr0_srst1);
+		sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+		mtsdr(SDR0_SRST1, sdr0_srst1);
+		udelay(1000);
+
+		mfsdr(SDR0_SRST0, sdr0_srst0);
+		sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+		mtsdr(SDR0_SRST0, sdr0_srst0);
+		udelay(4000);
+
+		/* finally all the other resets */
+		mtsdr(SDR0_SRST1, 0x00000000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+			/* enable power on USB socket */
+			out_be32((void*)GPIO1_OR,
+				 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+		}
+
+		printf("USB:   Host\n");
+
+	} else if ((strcmp(act, "dev") == 0) ||
+		   (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x672c6000);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000080);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60206000);
+
+		*(unsigned int *)(0xe0000350) = 0x00000001;
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60306000);
+
+		/* SDR Setting */
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+		/*clear resets*/
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay(1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Device\n");
+	}
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+#ifdef CONFIG_FPGA
+	pmc440_init_fpga();
+#endif
+
+	/* turn off POST LED */
+	out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
+	/* turn on RUN LED */
+	out_be32((void*)GPIO0_OR,  in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
+	return 0;
+}
+
+int is_monarch(void)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
+		return 0;
+
+	return 1;
+}
+
+int pci_is_66mhz(void)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
+		return 1;
+	return 0;
+}
+
+int board_revision(void)
+{
+	return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd GmbH - PMC440");
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld, ", gd->board_type);
+
+	if (!is_monarch()) {
+		puts("non-");
+	}
+
+	printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
+	return (0);
+}
+
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices. Some OSs rely on this.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+				   int_line[PCI_DEV(dev) & 0x03]);
+}
+#endif
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	char *ptmla_str, *ptmms_str;
+
+	/*
+	 * Set up Direct MMIO registers
+	 */
+	/*
+	 * PowerPC440EPX PCI Master configuration.
+	 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	 * PLB address 0x80000000-0xBFFFFFFF
+	 *     ==> PCI address 0x80000000-0xBFFFFFFF
+	 * Use byte reversed out routines to handle endianess.
+	 * Make this region non-prefetchable.
+	 */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+						/* - disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
+						/* and enable region */
+
+	if (!is_monarch()) {
+		ptmla_str = getenv("ptm1la");
+		ptmms_str = getenv("ptm1ms");
+		if(NULL != ptmla_str && NULL != ptmms_str ) {
+			out32r(PCIL0_PTM1MS,
+			       simple_strtoul(ptmms_str, NULL, 16));
+			out32r(PCIL0_PTM1LA,
+			       simple_strtoul(ptmla_str, NULL, 16));
+		} else {
+			/* BAR1: default top 64MB of RAM */
+			out32r(PCIL0_PTM1MS, 0xfc000001);
+			out32r(PCIL0_PTM1LA, 0x0c000000);
+		}
+	} else {
+		/* BAR1: default: complete 256MB RAM */
+		out32r(PCIL0_PTM1MS, 0xf0000001);
+		out32r(PCIL0_PTM1LA, 0x00000000);
+	}
+
+	ptmla_str = getenv("ptm2la");		/* Local Addr. Reg */
+	ptmms_str = getenv("ptm2ms");		/* Memory Size/Attribute */
+	if(NULL != ptmla_str && NULL != ptmms_str ) {
+		out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+		out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+	} else {
+		/* BAR2: default: 4MB FPGA */
+		out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+		out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+	}
+
+	if (is_monarch()) {
+		/* BAR2: map FPGA registers behind system memory at 1GB */
+		pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
+	}
+
+	/*
+	 * Set up Configuration registers
+	 */
+
+	/* Program the board's vendor id */
+	pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
+				   CONFIG_SYS_PCI_SUBSYS_VENDORID);
+
+	/* disabled for PMC405 backward compatibility */
+	/* Configure command register as bus master */
+	/* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
+
+
+	/* 240nS PCI clock */
+	pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+	if (!is_monarch()) {
+		/* Program the board's subsystem id/classcode */
+		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+					   CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+					   CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+
+		/* PCI configuration done: release ERREADY */
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
+		out_be32((void*)GPIO1_TCR,
+			 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
+	} else {
+		/* Program the board's subsystem id/classcode */
+		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+					   CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+					   CONFIG_SYS_PCI_CLASSCODE_MONARCH);
+	}
+
+	/* enable host configuration */
+	pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+/*
+ * Override weak default pci_master_init()
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	/*
+	 * Only configure the master in monach mode
+	 */
+	if (is_monarch())
+		__pci_master_init(hose);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
+
+static void wait_for_pci_ready(void)
+{
+	int i;
+	char *s = getenv("pcidelay");
+	/*
+	 * We have our own handling of the pcidelay variable.
+	 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+	 * and adapter devices. For adapter devices we do not
+	 * want this.
+	 */
+	if (s) {
+		int ms = simple_strtoul(s, NULL, 10);
+		printf("PCI:   Waiting for %d ms\n", ms);
+		for (i=0; i<ms; i++)
+			udelay(1000);
+	}
+
+	if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
+		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
+		while (1) {
+			if (ctrlc()) {
+				puts("abort\n");
+				break;
+			}
+			if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
+				printf("done\n");
+				break;
+			}
+		}
+	}
+}
+
+/*
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	char *s = getenv("pciscan");
+	if (s == NULL)
+		if (is_monarch()) {
+			wait_for_pci_ready();
+			return 1;
+		} else
+			return 0;
+	else if (!strcmp(s, "yes"))
+		return 1;
+
+	return 0;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+	char *s;
+	unsigned short val_method, val_behavior;
+
+	/* special LED setup for NGCC/CANDES */
+	if ((s = getenv("bd_type")) &&
+	    ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
+		val_method   = 0x0e0a;
+		val_behavior = 0x0cf2;
+	} else {
+		/* PMC440 standard type */
+		val_method   = 0x0e10;
+		val_behavior = 0x0cf0;
+	}
+
+	if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
+	}
+
+	if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
+	}
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/*
+ *  Input: <dev_addr> I2C address of EEPROM device to enable.
+ *         <state>    -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:          -1: wrong device address
+ *                     0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+			      in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR)
+				       & GPIO0_EP_EEP));
+			break;
+		}
+	}
+	return state;
+}
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 1);
+#endif
+	/*
+	 * Write data until done or would cross a write page boundary.
+	 * We must write the address again when changing pages
+	 * because the address counter only increments within a page.
+	 */
+
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen	= 2;
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+#define	BOOT_EEPROM_PAGE_SIZE	   (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define	BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+		maxlen = BOOT_EEPROM_PAGE_SIZE -
+			BOOT_EEPROM_PAGE_OFFSET(blk_off);
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+			rcode = 1;
+
+		buffer += len;
+		offset += len;
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+	}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 0);
+#endif
+	return rcode;
+}
+
+int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+	/*
+	 * Read data until done or would cross a page boundary.
+	 * We must write the address again when changing pages
+	 * because the next page may be in a different device.
+	 */
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen	= 2;
+
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+		maxlen = 0x100 - blk_off;
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+			rcode = 1;
+		buffer += len;
+		offset += len;
+	}
+
+	return rcode;
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+	char *act = getenv("usbact");
+	int i;
+
+	if ((act == NULL || strcmp(act, "host") == 0) &&
+	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
+		/* enable power on USB socket */
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+
+	for (i=0; i<1000; i++)
+		udelay(1000);
+
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	/* disable power on USB socket */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
+	return 0;
+}
+
+int usb_board_init_fail(void)
+{
+	usb_board_stop();
+	return 0;
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in non-monarch mode.
+	 */
+	if (!is_monarch()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/esd/pmc440/pmc440.h b/u-boot/board/esd/pmc440/pmc440.h
new file mode 100644
index 0000000..295cec1
--- /dev/null
+++ b/u-boot/board/esd/pmc440/pmc440.h
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PMC440_H__
+#define __PMC440_H__
+
+/*
+ * GPIOs
+ */
+#define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
+#define GPIO1_NONMONARCH          (0x80000000 >> (63-32)) /* GPIO63 I */
+#define GPIO1_PPC_EREADY          (0x80000000 >> (62-32)) /* GPIO62 I/O */
+#define GPIO1_M66EN               (0x80000000 >> (61-32)) /* GPIO61 I */
+#define GPIO1_POST_N              (0x80000000 >> (60-32)) /* GPIO60 O */
+#define GPIO1_IOEN_N              (0x80000000 >> (50-32)) /* GPIO50 O */
+#define GPIO1_HWID_MASK           (0xf0000000 >> (56-32)) /* GPIO56..59 I */
+
+#define GPIO1_USB_PWR_N           (0x80000000 >> (32-32)) /* GPIO32 I */
+#define GPIO0_LED_RUN_N           (0x80000000 >> 30)      /* GPIO30 O */
+#define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
+#define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
+#define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
+
+/*
+ * FPGA programming pin configuration
+ */
+#define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
+#define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
+#define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
+#define GPIO1_FPGA_DONE           (0x80000000 >> (55-32)) /* FPGA done pin (ppc input)     */
+#define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
+#define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
+
+/*
+ * FPGA interface
+ */
+#define FPGA_BA CONFIG_SYS_FPGA_BASE0
+#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
+#define FPGA_IN32(p) in_be32((void*)(p))
+#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
+#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
+
+struct pmc440_fifo_s {
+	u32 data;
+	u32 ctrl;
+};
+
+/* fifo ctrl register */
+#define FIFO_IE              (1 << 15)
+#define FIFO_OVERFLOW        (1 << 10)
+#define FIFO_EMPTY           (1 <<  9)
+#define FIFO_FULL            (1 <<  8)
+#define FIFO_LEVEL_MASK      0x000000ff
+
+#define FIFO_COUNT           4
+
+struct pmc440_fpga_s {
+	u32 ctrla;
+	u32 status;
+	u32 ctrlb;
+	u32 pad1[0x40 / sizeof(u32) - 3];
+	u32 irig_time;                  /* offset: 0x0040 */
+	u32 irig_tod;
+	u32 irig_cf;
+	u32 pad2;
+	u32 irig_rx_time;               /* offset: 0x0050 */
+	u32 pad3[3];
+	u32 hostctrl;                   /* offset: 0x0060 */
+	u32 pad4[0x20 / sizeof(u32) - 1];
+	struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
+};
+
+typedef struct pmc440_fpga_s pmc440_fpga_t;
+
+/* ctrl register */
+#define CTRL_HOST_IE         (1 <<  8)
+
+/* outputs */
+#define RESET_EN    (1 << 31)
+#define CLOCK_EN    (1 << 30)
+#define RESET_OUT   (1 << 19)
+#define CLOCK_OUT   (1 << 22)
+#define RESET_OUT   (1 << 19)
+#define IRIGB_R_OUT (1 << 14)
+
+/* status register */
+#define STATUS_VERSION_SHIFT 24
+#define STATUS_VERSION_MASK  0xff000000
+#define STATUS_HWREV_SHIFT   20
+#define STATUS_HWREV_MASK    0x00f00000
+
+#define STATUS_CAN_ISF       (1 << 11)
+#define STATUS_CSTM_ISF      (1 << 10)
+#define STATUS_FIFO_ISF      (1 <<  9)
+#define STATUS_HOST_ISF      (1 <<  8)
+
+/* inputs */
+#define RESET_IN    (1 << 0)
+#define CLOCK_IN    (1 << 1)
+#define IRIGB_R_IN  (1 << 5)
+
+/* hostctrl register */
+#define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
+#define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
+#define HOSTCTRL_CSTM1IE_GATE (1 <<  7)
+#define HOSTCTRL_CSTM1IW_FLAG (1 <<  6)
+#define HOSTCTRL_CSTM0IE_GATE (1 <<  5)
+#define HOSTCTRL_CSTM0IW_FLAG (1 <<  4)
+#define HOSTCTRL_FIFOIE_GATE (1 <<  3)
+#define HOSTCTRL_FIFOIE_FLAG (1 <<  2)
+#define HOSTCTRL_HCINT_GATE  (1 <<  1)
+#define HOSTCTRL_HCINT_FLAG  (1 <<  0)
+
+#define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_FPGARST_N    (1 <<  2)
+
+/*
+ * FPGA to PPC interrupt
+ */
+#define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */
+#define IRQ1_FPGA            (32+30) /* UIC1 - custom module */
+#define IRQ2_FPGA            (64+ 3) /* UIC2 - custom module / CAN */
+#define IRQ_ETH0             (64+ 4) /* UIC2 */
+#define IRQ_ETH1             (   27) /* UIC0 */
+#define IRQ_RTC              (64+ 0) /* UIC2 */
+#define IRQ_PCIA             (64+ 1) /* UIC2 */
+#define IRQ_PCIB             (32+18) /* UIC1 */
+#define IRQ_PCIC             (32+19) /* UIC1 */
+#define IRQ_PCID             (32+20) /* UIC1 */
+
+#endif /* __PMC440_H__ */
diff --git a/u-boot/board/esd/pmc440/sdram.c b/u-boot/board/esd/pmc440/sdram.c
new file mode 100644
index 0000000..34ff402
--- /dev/null
+++ b/u-boot/board/esd/pmc440/sdram.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
+ *
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/ppc440.h>
+
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+
+struct sdram_conf_s {
+	ulong size;
+	int rows;
+	int banks;
+};
+
+struct sdram_conf_s sdram_conf[] = {
+	{(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
+	{(512 << 20),  13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
+	{(256 << 20),  13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
+};
+
+/*
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ */
+int initdram_by_rb(int rows, int banks)
+{
+	ulong speed = get_bus_freq(0);
+
+	mtsdram(DDR0_02, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030602);
+	mtsdram(DDR0_04, 0x0A020200);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0102C812);
+	mtsdram(DDR0_07, 0x000D0100);
+	mtsdram(DDR0_08, 0x02430001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000100);
+	mtsdram(DDR0_11, 0x0027C800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x19000000);
+	mtsdram(DDR0_18, 0x19191919);
+	mtsdram(DDR0_19, 0x19191919);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+	mtsdram(DDR0_22, 0x00267F0B);
+	mtsdram(DDR0_23, 0x00000000);
+	mtsdram(DDR0_24, 0x01010002);
+	if (speed > 133333334)
+		mtsdram(DDR0_26, 0x5B26050C);
+	else
+		mtsdram(DDR0_26, 0x5B260408);
+	mtsdram(DDR0_27, 0x0000682B);
+	mtsdram(DDR0_28, 0x00000000);
+	mtsdram(DDR0_31, 0x00000000);
+
+	mtsdram(DDR0_42,
+		DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+		0x00000006);
+	mtsdram(DDR0_43,
+		DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
+		0x030A0200);
+
+	mtsdram(DDR0_44, 0x00000003);
+	mtsdram(DDR0_02, 0x00000001);
+
+	denali_wait_for_dlllock();
+
+#ifdef CONFIG_DDR_DATA_EYE
+	/*
+	 * Perform data eye search if requested.
+	 */
+	denali_core_search_data_eye();
+#endif
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t size;
+	int n;
+
+	/* go through supported memory configurations */
+	for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
+		size = sdram_conf[n].size;
+
+		/* program TLB entries */
+		program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
+			    TLB_WORD2_I_ENABLE);
+
+		/*
+		 * setup denali core
+		 */
+		initdram_by_rb(sdram_conf[n].rows,
+			       sdram_conf[n].banks);
+
+		/* check for suitable configuration */
+		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
+			return size;
+
+		/* delete TLB entries */
+		remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/esd/pmc440/u-boot-nand.lds b/u-boot/board/esd/pmc440/u-boot-nand.lds
new file mode 100644
index 0000000..cf4229a
--- /dev/null
+++ b/u-boot/board/esd/pmc440/u-boot-nand.lds
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/env_embedded.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/esd/tasreg/Makefile b/u-boot/board/esd/tasreg/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/esd/tasreg/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/tasreg/config.mk b/u-boot/board/esd/tasreg/config.mk
new file mode 100644
index 0000000..7ee4777
--- /dev/null
+++ b/u-boot/board/esd/tasreg/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
diff --git a/u-boot/board/esd/tasreg/flash.c b/u-boot/board/esd/tasreg/flash.c
new file mode 100644
index 0000000..fe120aa
--- /dev/null
+++ b/u-boot/board/esd/tasreg/flash.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <asm/ppc4xx.h>*/
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* test-only: todo: Re-do sizing to get full correct info */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/tasreg/fpgadata.c b/u-boot/board/esd/tasreg/fpgadata.c
new file mode 100644
index 0000000..611b521
--- /dev/null
+++ b/u-boot/board/esd/tasreg/fpgadata.c
@@ -0,0 +1,5331 @@
+  0x1f,0x8b,0x08,0x08,0x5a,0x90,0xc1,0x41,0x00,0x03,0x72,0x61,0x73,0x72,0x65,0x67,
+  0x2e,0x62,0x69,0x74,0x00,0xac,0xfd,0x7d,0x78,0x14,0xd7,0x95,0x2e,0x8a,0xaf,0xde,
+  0xd5,0x88,0x52,0x57,0x4b,0x5d,0x96,0x48,0x0e,0xb1,0x19,0x5c,0x6a,0x09,0xd2,0xe0,
+  0x96,0xd4,0x6e,0xb0,0x90,0x65,0xd1,0x2a,0x04,0x33,0xa3,0x00,0x13,0x34,0x9e,0xdc,
+  0xf3,0x78,0xe6,0xe4,0xe6,0xd7,0xf6,0x90,0x0c,0x93,0x43,0x3c,0xc4,0xf1,0x9d,0x4b,
+  0x1c,0x1f,0x67,0xab,0x5b,0x36,0x02,0x61,0xd3,0x60,0x32,0xc1,0x89,0x27,0xd3,0x7c,
+  0x24,0x66,0x6c,0x92,0x69,0x24,0x6c,0xc4,0x47,0xec,0x92,0xac,0x38,0xe2,0xc3,0xa0,
+  0x38,0x3e,0x09,0xb6,0x19,0xa7,0xf1,0xc8,0x8e,0x6c,0xcb,0xb6,0xf8,0x48,0x2c,0x21,
+  0x01,0x77,0xad,0xbd,0xab,0xba,0xab,0x05,0x73,0x7e,0x7f,0x9c,0xe3,0x3c,0x8f,0xb3,
+  0xbc,0xab,0xba,0xd4,0xbd,0x77,0xed,0xbd,0xd7,0xbb,0xdf,0xb5,0xde,0x05,0xc5,0x81,
+  0x51,0xf9,0x3f,0x00,0xcf,0xbd,0xa0,0x3d,0x70,0xef,0xb7,0x1e,0xf8,0xea,0xdf,0xd5,
+  0xdc,0xff,0xb7,0xab,0xe1,0x3e,0xd0,0xa2,0xdf,0x8a,0x46,0x22,0x5f,0xfb,0xbb,0x85,
+  0x77,0xd4,0xc1,0xdf,0xe2,0x7f,0x45,0x22,0x0b,0x6b,0x6f,0x8f,0xd6,0xde,0x5e,0x07,
+  0xab,0xa1,0xf8,0xf6,0x85,0x0d,0x0b,0x23,0x0d,0x0b,0xa3,0xf0,0x55,0x60,0x9b,0x97,
+  0x5d,0xc3,0x7f,0x9e,0x7d,0xea,0xff,0xfa,0x5a,0x04,0xb8,0x07,0x00,0xa6,0x47,0x3c,
+  0x71,0xfa,0xff,0x9b,0x22,0x1e,0xc3,0x03,0xbc,0xa9,0x3a,0x02,0x16,0xfd,0x37,0xd8,
+  0xd7,0x8b,0x23,0x60,0xb8,0xff,0xdb,0x13,0x01,0x13,0x5a,0xe1,0xa9,0x57,0xa0,0xcc,
+  0x80,0xff,0x9d,0x7f,0x3c,0xe0,0xe5,0xc2,0xf8,0x3f,0xf5,0x1c,0xf6,0xbf,0xf5,0x18,
+  0xfa,0x27,0xf5,0x7f,0xe8,0x39,0xfc,0xff,0xe8,0x73,0xca,0xff,0xb7,0x9f,0x63,0x89,
+  0x7f,0x97,0xfd,0xef,0x3e,0xc6,0xcb,0xe9,0xdf,0xd7,0xca,0xc0,0x07,0xf7,0x71,0x3d,
+  0x5d,0x14,0xf2,0xfc,0x00,0xbe,0xc6,0x3f,0x97,0x2e,0x5a,0x63,0x1b,0xde,0x35,0xee,
+  0x96,0x22,0xfe,0xb9,0xac,0x77,0x0d,0xcc,0x86,0x3f,0xe7,0x9e,0x34,0xac,0x97,0x46,
+  0xd6,0xbb,0xbe,0xa9,0x5f,0x3c,0xc7,0x9a,0x76,0x15,0x2e,0xf3,0x5a,0xcb,0xcf,0x15,
+  0x03,0x26,0x21,0x06,0x81,0xbe,0x64,0x26,0x35,0x64,0xdc,0xa5,0x96,0x0e,0x2a,0x55,
+  0xcb,0x5e,0x6f,0x6f,0xca,0x06,0x2e,0x24,0x47,0xf9,0x30,0xc4,0xfa,0xfc,0xa3,0x4a,
+  0x38,0x7d,0xda,0x88,0x0e,0xa0,0xd1,0x08,0xbd,0x6a,0xd4,0xf2,0x72,0x25,0x02,0xeb,
+  0xe8,0x39,0x5c,0xff,0x18,0x0e,0x43,0x8d,0x05,0x19,0x08,0xf3,0xbb,0x78,0xcd,0xb9,
+  0xce,0xa3,0xbe,0x9f,0x99,0xcf,0x59,0xf3,0x47,0x97,0xef,0x63,0xe1,0xc1,0x4e,0xa8,
+  0xc9,0x6a,0x93,0xec,0x63,0xe8,0xe4,0x35,0xd0,0xd2,0xce,0x0c,0xe8,0x80,0x20,0xa8,
+  0xdc,0x67,0x98,0x9b,0xcc,0x79,0x83,0x6a,0x07,0x33,0xbc,0x11,0x7a,0x4e,0xc7,0xb4,
+  0x93,0xd0,0x05,0x61,0x53,0x8d,0x30,0x30,0xba,0xf1,0x59,0x1a,0x30,0x0e,0x69,0x33,
+  0xa4,0xfb,0xb6,0x32,0x3f,0x7f,0x12,0xc2,0xd6,0x8a,0x08,0x3b,0x69,0xee,0xd6,0xc3,
+  0xd0,0xe1,0xc5,0xc1,0xe5,0x66,0xc8,0x3b,0xdf,0x43,0x06,0x18,0xfd,0xaa,0xde,0x1c,
+  0xf4,0x88,0xef,0x63,0x7d,0x66,0x1f,0x7d,0x9f,0xde,0x0e,0x68,0x0e,0xeb,0x3d,0x50,
+  0x63,0x6a,0x99,0xe0,0x3e,0x78,0x0e,0xe6,0x5b,0x2c,0xad,0x86,0x41,0x83,0x52,0x4b,
+  0xcb,0xb0,0x8f,0xa0,0x73,0x59,0x0d,0x84,0xf0,0xe3,0xad,0x1c,0x9e,0x85,0xe5,0xf4,
+  0xb6,0x74,0xc0,0xb3,0xd6,0xde,0x1d,0x2c,0xe2,0x8d,0x8b,0xee,0xfe,0xcc,0x08,0x5c,
+  0x6e,0x89,0x59,0xf8,0x45,0x42,0xc6,0x18,0xc4,0x58,0x80,0x2b,0x69,0x18,0x86,0x06,
+  0xf8,0xa2,0xbe,0xb4,0xc6,0x7c,0x0b,0x2f,0x05,0x32,0xca,0x30,0x7c,0x00,0x31,0x33,
+  0xdc,0xa3,0xd5,0xb0,0x01,0xfa,0xb3,0x19,0xa5,0xb6,0xef,0x98,0x11,0xb5,0xfc,0x9b,
+  0x14,0xf0,0x8a,0xef,0x93,0xf5,0x1c,0x55,0xaf,0x06,0x9b,0x86,0xf0,0xe6,0x4b,0x70,
+  0x0d,0x9a,0xac,0xc0,0x3a,0x65,0x12,0x8d,0xc5,0x56,0x20,0xab,0x9c,0x85,0x6b,0x56,
+  0x93,0x75,0xeb,0xa8,0x32,0x04,0x57,0xa0,0x89,0x07,0x06,0x94,0x0b,0x78,0xa9,0xce,
+  0x2a,0xe9,0x53,0x2e,0x78,0xaf,0xd2,0xcd,0x90,0x1c,0x03,0xf1,0x7d,0x4c,0x7d,0x1f,
+  0x5c,0x4e,0xff,0xa3,0x19,0xe8,0x2a,0x0f,0x15,0x9f,0x80,0x18,0xc7,0xef,0x03,0xfa,
+  0x20,0xd4,0x41,0x49,0x4a,0x09,0xc3,0x5b,0xd0,0x45,0xdf,0x67,0x99,0xe7,0x18,0x5e,
+  0xf2,0xf3,0xce,0xb4,0x72,0x02,0x70,0xbc,0x78,0x79,0x05,0xb3,0xf4,0xe8,0x40,0x4d,
+  0x87,0xa2,0x7b,0x0d,0x7a,0xce,0xc0,0xb4,0xb0,0x7a,0xc4,0xc2,0x41,0xe1,0x89,0x2a,
+  0xfc,0xc9,0xd4,0x3f,0xca,0x5a,0xe8,0x84,0xa0,0x55,0x92,0x66,0x61,0x2f,0x19,0xda,
+  0xa8,0xaf,0x0a,0x36,0xb2,0x9a,0x94,0xca,0xa7,0xc7,0xef,0xeb,0x4c,0xed,0x3a,0x53,
+  0xb2,0x91,0x55,0x40,0x47,0xeb,0xa2,0xd7,0x4a,0xb6,0xfb,0xa2,0xb8,0x00,0xd1,0xef,
+  0x9a,0xb6,0x12,0xc7,0xab,0x26,0xdd,0xe9,0x65,0x5e,0xe0,0x2c,0x6c,0xe2,0x78,0x99,
+  0xde,0x14,0xab,0x02,0x4d,0x67,0x27,0xa1,0x1b,0xd6,0x58,0x5a,0xa4,0xc8,0x0b,0x6d,
+  0x50,0x93,0x50,0xa9,0x7b,0x93,0xd6,0x5c,0x4b,0x85,0xe5,0xcd,0x09,0xce,0x83,0xe7,
+  0x7c,0xde,0xe6,0x7a,0x5c,0xc6,0xf0,0x9f,0xb8,0x67,0xb6,0xfa,0x42,0xa2,0x3a,0xad,
+  0xad,0x63,0x37,0xf3,0x0d,0xbc,0x7a,0xaf,0x76,0xe7,0xcd,0x8f,0xc0,0x16,0x6e,0x64,
+  0xb5,0x61,0xf6,0xb6,0xe7,0xdf,0xf8,0xbc,0xac,0x56,0xcf,0xfe,0x06,0x1e,0x4b,0x57,
+  0x7f,0x6d,0xe6,0x7a,0x36,0xdb,0x6a,0xf7,0xff,0xd8,0x28,0x5e,0x5f,0xf4,0x45,0x63,
+  0x0b,0x9f,0x33,0x34,0x6f,0x39,0x9b,0x29,0xbf,0x4f,0x8b,0xea,0x87,0x0b,0x89,0xf0,
+  0x6f,0x02,0x77,0x2a,0x73,0x21,0x09,0x8d,0xc3,0x01,0x50,0x4c,0x18,0x84,0x85,0x10,
+  0xd0,0x95,0x8f,0xe1,0x22,0x84,0xac,0xc0,0xed,0x8a,0x0a,0x09,0x1e,0x7b,0x30,0x7c,
+  0x20,0x51,0xdb,0xd7,0xa1,0x1f,0x30,0xfc,0x07,0x92,0x2b,0xa1,0xb7,0x2d,0x32,0x5c,
+  0x73,0xcb,0xd2,0x32,0xb9,0x60,0x98,0x7f,0x72,0x14,0x2e,0xeb,0xd8,0xf3,0x2f,0x2b,
+  0x63,0xe6,0x51,0x88,0x79,0x03,0xa3,0xda,0x59,0x98,0x80,0x98,0x55,0xb2,0x46,0x6b,
+  0x84,0xdf,0xc1,0x22,0xec,0xe7,0xf2,0x1e,0x76,0x15,0xc7,0x3d,0x70,0x5e,0x7b,0xd8,
+  0x9c,0x84,0xbb,0x60,0x7a,0x46,0xd9,0x07,0xe3,0xbc,0x69,0xb0,0x36,0xa5,0x0c,0x16,
+  0x89,0xf1,0xda,0x3b,0x6d,0x44,0x7c,0x6a,0x3a,0xc7,0xd1,0x39,0xc3,0xa3,0x71,0x3f,
+  0x28,0x69,0x75,0x0c,0x7a,0x8c,0x40,0x4a,0x0b,0x8b,0x4b,0x81,0x17,0x14,0xbc,0xc7,
+  0x13,0xf3,0xd0,0x1c,0x64,0x67,0x20,0xea,0x09,0xd3,0x64,0x1c,0x80,0x58,0xbf,0x9f,
+  0x57,0x7e,0x20,0xe7,0x57,0xcb,0x4d,0x4f,0xc3,0x41,0x6f,0xb5,0xa5,0x44,0x7c,0x50,
+  0x96,0x84,0x34,0x0f,0xad,0x63,0xb3,0x60,0x37,0x54,0x58,0x25,0x06,0x1a,0x07,0xa1,
+  0xda,0xd2,0xfe,0x31,0x31,0x08,0x07,0xd0,0x08,0x8d,0xb2,0x59,0xfa,0x06,0xbc,0xa4,
+  0xae,0x63,0x4f,0xc3,0x06,0xa8,0x1d,0x68,0x89,0xb3,0xd7,0xe4,0xfb,0x6c,0xc1,0x8f,
+  0xe0,0xf9,0x8e,0xea,0xac,0x86,0x7d,0x08,0x1b,0x78,0x45,0xb6,0x78,0x80,0xf5,0xc1,
+  0x1e,0x7e,0x9b,0xe1,0xbb,0xc7,0xf8,0x0a,0x1c,0xb4,0xc4,0xa5,0x6d,0x91,0x03,0x78,
+  0x4f,0xf1,0xfa,0xb2,0xd9,0x7a,0x12,0xef,0x51,0xeb,0xd9,0x57,0xe0,0x51,0x5e,0x9d,
+  0x55,0xef,0x61,0xa3,0x20,0xde,0x9f,0x96,0x19,0x27,0x8b,0xf7,0x2f,0x5f,0x6b,0x69,
+  0x20,0xa7,0x1e,0xee,0x50,0x6c,0x25,0x7e,0x1f,0xc3,0x2a,0x36,0xd8,0x17,0xa1,0x9b,
+  0x87,0x71,0xdc,0xd9,0x6b,0x70,0x80,0xcf,0x79,0xb7,0x98,0xbe,0xea,0x86,0xc1,0x8a,
+  0xd7,0xf1,0xfb,0x9c,0x65,0x8f,0xe2,0x14,0x0e,0x2d,0x4c,0xbc,0x26,0xe7,0xfb,0xf0,
+  0x67,0xf6,0xc2,0x1f,0xcd,0xa6,0x54,0x20,0xad,0xcc,0x87,0xe3,0x10,0xe5,0x25,0x69,
+  0x31,0x9b,0x1a,0x78,0x69,0x5a,0xf9,0x3a,0x5c,0x35,0xf1,0x0d,0x4f,0x2b,0x7b,0xe1,
+  0x32,0xbe,0xcf,0x25,0x69,0x2d,0xc4,0xf0,0x9e,0xb4,0x3f,0xad,0xac,0xc1,0x9b,0xf1,
+  0x0d,0x1f,0x52,0x2e,0xcb,0xdf,0xd5,0x02,0x59,0x10,0xd3,0xd3,0x9a,0x3e,0x6a,0x8e,
+  0x40,0x13,0xce,0x6f,0x25,0x05,0xc2,0x30,0x95,0xb4,0x39,0xa6,0xe2,0xca,0xc6,0x95,
+  0x51,0x5c,0xe2,0x9a,0x74,0xbc,0x34,0x0a,0x43,0x66,0x93,0x1e,0x30,0x95,0x8c,0x58,
+  0xf4,0x6a,0xdb,0xcb,0x5f,0x03,0xf1,0x7d,0x54,0x7d,0x08,0xc6,0xf5,0x88,0xe9,0xd7,
+  0xb5,0x2a,0xf5,0x0d,0x78,0xc4,0xc4,0xd7,0xa6,0x0a,0x7e,0x05,0x51,0x33,0x90,0x52,
+  0xf6,0xc0,0x46,0x98,0x4d,0xc6,0x10,0x9c,0x87,0x07,0xf0,0x1e,0xc5,0x6b,0x1e,0x6b,
+  0x89,0x7c,0xcd,0xbf,0x43,0xf1,0xc2,0xb1,0x54,0x74,0x99,0x7f,0xbb,0xd2,0x27,0x7f,
+  0x17,0xc7,0x2d,0xff,0x90,0x15,0x34,0x43,0xdf,0x5b,0xba,0x1a,0x3f,0x85,0xf3,0x8b,
+  0x3e,0xf5,0xaf,0x50,0x47,0xc6,0x6a,0xb6,0x11,0x5f,0x9b,0x15,0x29,0x36,0x04,0x87,
+  0x20,0xf8,0xa0,0xfa,0xcf,0x49,0xbc,0xc7,0xac,0x5b,0xa7,0x3e,0x95,0xfc,0x3b,0x73,
+  0xa3,0xb5,0x6b,0x5d,0xc9,0x3f,0xb1,0x2c,0xe8,0xf4,0x9c,0x99,0xd3,0xaa,0xf0,0x9e,
+  0x5d,0x66,0xcb,0x76,0xf6,0x25,0xf8,0x67,0xa8,0xc5,0x8f,0xb3,0x85,0xf0,0xcf,0x9e,
+  0xcf,0x9b,0x9d,0x83,0x6c,0x19,0x3e,0x90,0x9e,0x8c,0xcf,0xf9,0x39,0x54,0xb4,0x76,
+  0x0c,0xe2,0xa5,0xc7,0xd5,0xcf,0x37,0xab,0x83,0x45,0x0f,0x1a,0x6d,0x60,0x98,0x6a,
+  0x8a,0xbd,0x22,0xe7,0x85,0xea,0xf5,0xc2,0x21,0x6e,0x2c,0x57,0xef,0x4e,0xcc,0x78,
+  0xf7,0xd1,0x50,0xf5,0x72,0xed,0xee,0xc4,0xf6,0xf4,0x8f,0x43,0x73,0xd0,0x78,0x6c,
+  0x59,0xb6,0x0d,0x54,0x13,0x27,0xec,0xeb,0xe9,0xe7,0x43,0x3b,0x97,0xcf,0xbc,0x7b,
+  0xd3,0x97,0x77,0x3d,0x8a,0x97,0x42,0x77,0x6f,0xfa,0xd2,0xae,0x0d,0xa1,0xf4,0x40,
+  0x71,0x59,0xa2,0x4f,0xb8,0x1f,0xd0,0x53,0x12,0xc7,0x7e,0x0e,0xaa,0xfe,0x04,0xbb,
+  0x97,0x9f,0x31,0x6a,0xd5,0x40,0x82,0x19,0x68,0xd4,0xa9,0x81,0x3e,0xe5,0x5e,0xdc,
+  0x26,0x6a,0x20,0x90,0xd8,0x95,0xe5,0x63,0x15,0x86,0x1a,0x4e,0x28,0xc0,0x3b,0x8c,
+  0x85,0x78,0xb3,0x62,0xf2,0x93,0x15,0x51,0xc0,0x96,0x8f,0x15,0x31,0xdf,0x77,0xfc,
+  0x09,0xae,0x75,0xa1,0x97,0x96,0x07,0xba,0x92,0x43,0x7c,0x9c,0x26,0x11,0xf6,0x0f,
+  0x93,0xc6,0x5f,0x5d,0xe2,0x57,0x42,0xb2,0x05,0xc6,0xa7,0xc5,0x96,0x07,0xb6,0x25,
+  0x87,0xd2,0xe3,0xf3,0xa5,0xb1,0x07,0x2f,0x7d,0x31,0x30,0xa8,0xbc,0x57,0x24,0xe6,
+  0xc5,0x8e,0x69,0xb4,0x66,0x2e,0x30,0xb1,0x65,0x08,0x8e,0xc9,0xe7,0x54,0xc1,0xfb,
+  0x38,0x5e,0xa5,0x34,0x5e,0xc7,0xe4,0xc0,0x55,0xe9,0xe3,0x78,0x8f,0x9f,0x96,0x81,
+  0x57,0x3d,0x0b,0x70,0x3d,0x50,0x16,0x7a,0x7f,0x81,0x0b,0x03,0x6e,0x64,0x73,0xe5,
+  0xfc,0xaa,0xd7,0xb3,0x6a,0x0f,0xbe,0xcb,0x1a,0xc7,0x9e,0xdf,0x8b,0xbf,0x02,0x0d,
+  0x5a,0xe7,0x83,0xe0,0x47,0x83,0x3d,0x0b,0xf3,0xa1,0x94,0xe3,0x5b,0x77,0x18,0xe6,
+  0x73,0x1f,0x5d,0x7a,0x16,0x82,0x5c,0xe5,0x2c,0x24,0x36,0xb2,0x10,0x67,0xa5,0x72,
+  0xdc,0xd5,0x69,0xfd,0xb0,0x9f,0x1b,0xd8,0x99,0x65,0xfd,0x6a,0x1b,0x6e,0x64,0x9a,
+  0x8e,0xab,0xe8,0x4e,0xdc,0xc1,0x7c,0x3a,0x6b,0xc7,0x37,0x81,0x2e,0xb1,0xf6,0x19,
+  0xb7,0xd3,0xe8,0xe8,0x8c,0x16,0xc6,0xb8,0x63,0x18,0x4b,0x42,0x33,0x9b,0x99,0xdc,
+  0xbf,0x66,0x7e,0x66,0x8f,0x18,0x77,0x6d,0x5b,0xb0,0xdf,0xfb,0xaf,0x66,0x4d,0x4b,
+  0x31,0xad,0xa9,0x1b,0x21,0xb8,0x44,0xb5,0x0d,0x1a,0x5c,0x7c,0x7f,0x8c,0xf9,0xa6,
+  0x6f,0x1b,0xdb,0xc3,0x77,0x42,0xb0,0x45,0xdd,0x8e,0x5b,0xa4,0xb8,0x27,0xc3,0x8a,
+  0xe4,0xbc,0x48,0x7f,0x06,0xfb,0x10,0xa2,0x2d,0x81,0xed,0xd4,0x3f,0x56,0x2c,0x8e,
+  0xbd,0xe1,0xcd,0xf5,0x8f,0x79,0x6c,0x70,0x9b,0x39,0x3d,0xa5,0xfc,0x18,0xc6,0xcd,
+  0x07,0x5a,0xfd,0xdb,0x94,0x2a,0x7e,0xcc,0xec,0x6a,0x0d,0xa7,0xb4,0x2a,0x76,0xac,
+  0xa5,0xcb,0xf4,0x6f,0xd7,0x42,0x72,0xff,0x0a,0x79,0xf6,0xc0,0xf8,0xb6,0xd8,0x6a,
+  0x39,0x28,0xf4,0x1c,0x1d,0x8d,0x73,0xd8,0xe1,0x35,0xba,0xf2,0x1e,0xd0,0xc0,0x95,
+  0xea,0xca,0xdf,0x91,0xb1,0x4c,0xde,0xa3,0xc7,0xcc,0x92,0xad,0x49,0x34,0x8c,0x58,
+  0xf3,0xbf,0xe9,0xca,0x71,0xb9,0x7f,0x85,0xf4,0x34,0x8c,0x71,0x9c,0x8c,0xed,0x4a,
+  0x56,0x1f,0xc0,0x6d,0x0b,0x17,0xbd,0x38,0x9c,0xc1,0x81,0x29,0x21,0x63,0x8c,0x3c,
+  0x10,0x3e,0x1d,0x77,0x2b,0x33,0xa3,0x37,0x16,0x55,0x7a,0x5a,0x06,0xcc,0x3f,0x96,
+  0xd1,0x7a,0x18,0x1f,0x80,0x28,0xdd,0x7c,0x5c,0xee,0x5f,0xa1,0x69,0x21,0x78,0x11,
+  0x6a,0xf6,0x6a,0x43,0x6c,0x58,0xdd,0xc4,0x70,0x2c,0xd2,0x38,0x16,0x9b,0x40,0x18,
+  0x7b,0x71,0x4b,0x9a,0xcb,0xb5,0x34,0x7e,0xeb,0x4d,0xac,0xb2,0x4b,0x7d,0x8f,0xdd,
+  0xe5,0x7d,0xe2,0x8d,0x05,0xe9,0x92,0xec,0xdd,0x0d,0xf0,0x76,0xa6,0x32,0xa5,0x66,
+  0x9b,0x8f,0xcb,0x79,0x11,0xc2,0xfd,0xeb,0x08,0x0d,0xd3,0xe2,0xc4,0x49,0x86,0xeb,
+  0xaa,0x35,0x2f,0xe2,0x5b,0xc9,0x9e,0x84,0x2a,0x34,0xd8,0x88,0xa7,0x1b,0xd6,0x5a,
+  0xff,0x2d,0x52,0xe6,0x87,0x27,0xc1,0x78,0x07,0x97,0x41,0xbf,0x91,0x34,0x83,0x43,
+  0x6a,0x0f,0x2b,0x41,0x4f,0x26,0x38,0xa8,0x46,0x71,0x3d,0x12,0xef,0x73,0x7a,0xc9,
+  0x2c,0x78,0x9e,0x16,0xe1,0x75,0xc1,0x93,0x3c,0x89,0xdb,0x16,0x2e,0x7a,0x7e,0xdc,
+  0x80,0x0c,0x6b,0xe6,0xba,0xa2,0xb3,0x9e,0x83,0xfa,0x1c,0xeb,0x96,0x08,0x2e,0xb9,
+  0xdf,0x87,0x0a,0x3e,0xb3,0x95,0xd6,0x43,0xa8,0x30,0x8b,0x1f,0xc4,0x7b,0x9e,0x86,
+  0x8a,0x3e,0xf5,0x41,0x36,0x2c,0xbf,0xcf,0x5e,0x75,0x36,0xfc,0x91,0x2f,0x8e,0x07,
+  0xd6,0x2b,0x6f,0xa7,0x7f,0xc9,0x6f,0xcf,0x3e,0x5e,0xaf,0x7c,0x05,0x7e,0xcb,0xef,
+  0xc8,0x96,0xa0,0x61,0x7e,0x7a,0x60,0x71,0x76,0xfa,0x7a,0x56,0x0a,0x4f,0xf2,0x08,
+  0x2e,0xcb,0x5a,0x11,0xeb,0x45,0xc3,0x3f,0xac,0x95,0xc1,0x2f,0x79,0x26,0xeb,0x5f,
+  0xaf,0x7c,0x20,0xf7,0x2f,0xf5,0x4f,0x70,0x27,0xf2,0xce,0xc6,0x4d,0x8a,0x7d,0x64,
+  0x4e,0x78,0x66,0x5b,0xa5,0x19,0x65,0xc4,0xfb,0x1d,0x10,0xee,0x4a,0xd8,0x9c,0x30,
+  0xc9,0x58,0x3a,0x02,0x1f,0x92,0x0b,0x41,0x2f,0xd2,0xb8,0xa7,0xc1,0xc4,0x95,0x96,
+  0x56,0xd1,0x17,0xf9,0x96,0xcc,0xd2,0x3e,0xb9,0x7f,0x99,0xe8,0x1f,0x5e,0xe3,0x4d,
+  0xab,0xfd,0x63,0xca,0x55,0xf8,0x84,0xa3,0x37,0x38,0xa6,0xc4,0xb0,0x65,0x01,0x19,
+  0x57,0xcd,0x0f,0xd1,0x58,0x35,0x3e,0xfd,0x2a,0x9c,0x36,0x9a,0xe2,0xd5,0xc3,0xe5,
+  0xb1,0xe2,0xcb,0xbc,0x6b,0xc8,0x7f,0x46,0x8b,0x35,0x9f,0xe6,0xd1,0x21,0xfc,0xd4,
+  0xa0,0x9c,0x5f,0x7b,0x71,0xff,0x7a,0x3e,0x5d,0x6d,0xe1,0x2f,0x9d,0xf4,0x4e,0x07,
+  0xdc,0x65,0x70,0x53,0x30,0x36,0xf0,0x3b,0xde,0xf3,0x3d,0x80,0xc6,0x96,0x5d,0x15,
+  0x16,0xee,0x3b,0x67,0xf9,0x06,0xbd,0xda,0xf0,0x99,0x6c,0x96,0xfa,0x35,0x5e,0xb1,
+  0x46,0xfd,0x12,0x8b,0xe1,0xa4,0xa9,0xd8,0x33,0xff,0xdb,0xec,0x03,0xf9,0x3e,0xeb,
+  0xd8,0x5f,0x07,0xe3,0xe1,0xe6,0x0e,0xdc,0x4a,0xe0,0x19,0xb5,0xba,0x8f,0x9e,0x03,
+  0xcf,0xe0,0x66,0xb7,0x7c,0x5d,0xd9,0xd3,0xb0,0xa8,0x7e,0x0e,0x0e,0x01,0x3b,0xab,
+  0x6e,0x50,0xab,0x97,0xa8,0x71,0x36,0x03,0x37,0x44,0xdc,0x07,0x4d,0xa6,0x73,0x7b,
+  0x43,0xec,0x97,0xfb,0x57,0x7c,0xc6,0x49,0xd8,0x0f,0xe1,0xac,0xba,0x7f,0xdb,0xc9,
+  0x78,0xf2,0x9d,0xf0,0x98,0x76,0x87,0x0f,0xbd,0xac,0x48,0x55,0x56,0x6d,0xc0,0x41,
+  0x79,0xd2,0xac,0xa2,0xfd,0xeb,0x34,0x54,0x5a,0xe1,0x1d,0xbe,0x52,0x5f,0xb1,0xb1,
+  0xcb,0x30,0xea,0xd5,0x20,0x0b,0xf1,0x8d,0x59,0xa3,0xd7,0xb7,0x90,0xbd,0x29,0xe7,
+  0x7b,0x0f,0xfa,0x99,0xb8,0x89,0xc7,0xfd,0x07,0x94,0x6b,0xf0,0x21,0x8f,0x65,0x03,
+  0x07,0x94,0x1a,0xf8,0x8f,0xe6,0xe8,0xe8,0x13,0x47,0x93,0x47,0xd5,0x6b,0xa9,0x3a,
+  0xea,0xf0,0x4f,0x8c,0x4e,0x2b,0x76,0xc6,0xff,0xe2,0x8a,0x50,0x6a,0xc2,0x78,0xa0,
+  0x27,0xdc,0xa5,0x84,0xf9,0x09,0xb3,0xab,0x37,0xbc,0x5f,0xf9,0x58,0xfe,0x2e,0x8e,
+  0x7b,0xd5,0x38,0x8d,0x4e,0x5a,0x91,0x0e,0x43,0xa0,0x4b,0x39,0x69,0xe0,0xe8,0x0c,
+  0x94,0x92,0x53,0xf1,0x21,0x3c,0xd4,0x1b,0x88,0x28,0x23,0xec,0x2d,0x88,0xa5,0x4a,
+  0xb7,0xe3,0x16,0x39,0x41,0x33,0xe5,0x80,0xf2,0x11,0x8c,0xe9,0x31,0x6b,0xcb,0x51,
+  0x1c,0x38,0xb9,0xef,0xe8,0xe4,0x55,0xde,0xbe,0xc6,0x3f,0x8e,0x2e,0xfa,0x35,0xf8,
+  0x2e,0xfd,0xf5,0xb5,0x9e,0x13,0xe4,0x4c,0x46,0x18,0xb5,0x54,0xa2,0x5f,0xe7,0xf1,
+  0x1b,0xbf,0x54,0xeb,0xb2,0x34,0x3a,0xfc,0x18,0x6f,0xda,0xeb,0xdf,0xb5,0x34,0xaa,
+  0x9f,0xb6,0x6e,0x5f,0xe7,0x5f,0xa7,0xd8,0x7e,0xf8,0x56,0xef,0x5a,0xe8,0x6e,0x0f,
+  0x5a,0xea,0x01,0x16,0xc6,0x09,0x52,0x83,0xbd,0xd1,0x1c,0x46,0xff,0xd0,0xb0,0x54,
+  0x72,0x14,0x5f,0x22,0x47,0x31,0x53,0xb4,0x8f,0x3c,0xc6,0xa0,0xba,0x33,0xf1,0x1f,
+  0xea,0x19,0xde,0x90,0x52,0x37,0xb3,0xb9,0xb0,0xa9,0x65,0x17,0x84,0x8e,0x06,0x0d,
+  0x53,0xec,0x5f,0x7c,0x1a,0x7e,0x9c,0xef,0xc2,0x4f,0xd9,0xcf,0xb9,0x25,0xc3,0x46,
+  0xf0,0x53,0x73,0xad,0xe2,0x0c,0xdb,0x87,0xf3,0x6b,0x3e,0xf9,0xe1,0xd8,0xe2,0xa9,
+  0x5a,0x36,0x33,0xcd,0xde,0x87,0x4d,0xb8,0xfa,0xe0,0x52,0x19,0x6e,0x26,0x17,0x54,
+  0xed,0x29,0x8b,0x3b,0xfb,0x97,0x1f,0xf6,0x67,0xf0,0xaf,0x2f,0x44,0x37,0x03,0x71,
+  0xc1,0x00,0x7e,0xca,0xcf,0x3a,0xd5,0xb9,0x7d,0x10,0x69,0x46,0x3f,0xd3,0x88,0xf7,
+  0xaa,0x91,0xc4,0x49,0x48,0xea,0x55,0xf7,0x84,0x80,0xfd,0x02,0xb6,0x56,0x85,0xf4,
+  0x10,0x62,0x24,0x8e,0xce,0x89,0xaa,0x96,0xb1,0x66,0xb9,0x7f,0xf1,0x92,0xb5,0x30,
+  0x11,0x8a,0x5a,0x9b,0xb7,0x6b,0x8d,0xe6,0x04,0xd4,0x9c,0xc4,0xfe,0xc1,0xbf,0x6e,
+  0xd4,0x0d,0x94,0x64,0xb4,0xa7,0xcd,0x6b,0xa1,0x06,0x4b,0xeb,0x62,0x23,0xec,0x84,
+  0xa7,0xee,0x16,0xdc,0xdf,0xcf,0xc1,0x80,0xa7,0xf1,0x1e,0x7f,0x4a,0x33,0xc0,0x6a,
+  0xcd,0xdc,0xe3,0x3f,0x58,0x1e,0x97,0xfb,0x57,0xfa,0x4f,0x26,0x61,0xc2,0x40,0xff,
+  0x70,0x54,0x39,0xca,0xaf,0x41,0xec,0x24,0x1a,0x0f,0xe3,0xa0,0x34,0x50,0xcb,0xc3,
+  0xd8,0x52,0x4b,0x3d,0x7f,0xd4,0x73,0xcd,0x68,0x80,0x00,0xfa,0x1b,0x7c,0x52,0x6f,
+  0xf2,0x06,0xac,0xca,0x73,0xe4,0x81,0x9c,0x0a,0xec,0x56,0xf6,0xca,0xfd,0x8b,0xf0,
+  0xd7,0x04,0xe0,0x6c,0x1a,0x15,0x70,0x40,0x3c,0x10,0x5b,0x8c,0x06,0xab,0x94,0x66,
+  0xdc,0x35,0x63,0x11,0x0f,0x65,0xc4,0xa5,0x98,0x95,0xbf,0x27,0xf3,0x57,0x23,0xa9,
+  0x31,0x7d,0xc1,0x71,0x74,0x3c,0x5c,0xf8,0xeb,0x25,0x1e,0xcc,0xe2,0x97,0xcf,0x42,
+  0x0f,0xaf,0x31,0xb4,0x0e,0x44,0x5b,0x47,0xf8,0x7c,0xdc,0xd6,0xd0,0x78,0xc9,0xaa,
+  0x41,0xaf,0x9b,0x09,0x78,0x06,0x2b,0x1c,0x43,0xbb,0x82,0xfe,0xeb,0x61,0xa8,0xec,
+  0x0d,0x65,0x10,0xfe,0xe7,0xf0,0x57,0x37,0x8e,0xb2,0x86,0x9d,0x99,0xde,0x2f,0xf6,
+  0x2f,0x72,0xe3,0xcd,0x90,0xe9,0x43,0xd8,0x05,0x4f,0xea,0x61,0xae,0x46,0xe4,0x10,
+  0x70,0x2d,0x22,0x3c,0xfc,0x2a,0x5c,0x21,0xd9,0xab,0xb0,0xd3,0x88,0xd3,0x28,0xbb,
+  0xf0,0xd7,0x11,0x1c,0x41,0x1c,0xee,0x73,0x70,0xd8,0xac,0x49,0x69,0x7b,0x70,0x94,
+  0x8f,0xc0,0x7c,0xb3,0x23,0x23,0x8c,0xb0,0xa5,0xb6,0xb1,0xac,0x59,0x3f,0xa3,0x66,
+  0x99,0x46,0x46,0x8f,0x5e,0xe3,0x15,0x6f,0xc2,0x11,0x9d,0xc6,0xdd,0xc1,0x5f,0x26,
+  0xe2,0xaf,0x6b,0x10,0xc5,0x9f,0x5c,0x39,0x24,0xe7,0x45,0x46,0x4c,0x90,0x06,0x93,
+  0x16,0x34,0xc4,0x3b,0xe8,0x04,0xee,0x55,0x3e,0x40,0x0c,0x8b,0x53,0xcf,0x36,0xd2,
+  0xe2,0x9e,0x31,0x84,0x42,0x2b,0x19,0xe2,0x1d,0x07,0x7f,0xc1,0xa7,0xb2,0x7b,0xc7,
+  0x68,0x08,0x68,0x50,0x26,0xb1,0xe5,0x0e,0x57,0xaf,0x9e,0x51,0xfe,0x08,0x57,0x78,
+  0x93,0xe1,0x18,0xf1,0xc0,0xa8,0x67,0x04,0xfe,0x88,0x9d,0x17,0x18,0x64,0x2e,0xfc,
+  0x35,0x21,0xbe,0x8f,0xf2,0x55,0xdc,0x34,0x63,0xad,0xb8,0xb1,0xee,0xb3,0xbf,0xd8,
+  0x52,0x31,0x73,0xb9,0x5f,0xba,0xa9,0x5d,0x3c,0x9c,0x33,0xe8,0xfb,0x1c,0x83,0x86,
+  0x7e,0x1c,0xaf,0x3c,0xfe,0x12,0x93,0x08,0x7f,0xf2,0x30,0x21,0x46,0xdc,0xad,0xf0,
+  0xb7,0xbf,0x24,0x80,0x98,0x34,0x2c,0x9f,0x6b,0xa3,0x97,0x06,0x8c,0xb2,0x49,0x9c,
+  0x3b,0xb5,0xa3,0x6a,0xaa,0xd9,0x85,0xbf,0xe4,0x78,0x21,0xf2,0xec,0xa2,0x41,0x31,
+  0xd8,0x66,0x1a,0x1d,0xcb,0x1e,0x1d,0x1c,0x2f,0x1d,0x17,0xbd,0x9d,0xe8,0x6f,0xf8,
+  0x6c,0x37,0x83,0xc0,0xf5,0x49,0x48,0xc3,0xfc,0x0b,0xf8,0x4a,0xd8,0xf8,0xcb,0xf0,
+  0xcc,0x86,0xee,0x74,0x05,0x3a,0xff,0xc1,0xdf,0xc0,0xf3,0xbc,0x3a,0xae,0xdd,0x53,
+  0xf6,0x36,0x1c,0xe4,0x02,0x0e,0xa0,0xa1,0x57,0x67,0x7d,0x6b,0xd8,0x9b,0xf0,0x18,
+  0xaf,0x48,0xb3,0x35,0xec,0x66,0x04,0x62,0x15,0x7b,0x8b,0xf1,0x12,0xdf,0x93,0xc6,
+  0x55,0xf4,0x2b,0x4c,0xf5,0xe6,0xf0,0xd7,0x45,0x1e,0xb1,0x02,0x51,0x65,0xc0,0x3b,
+  0x0a,0x8d,0x80,0xf8,0x6b,0x33,0x5c,0x4c,0x37,0xae,0x5d,0x15,0x29,0x3f,0xa9,0x5e,
+  0xdc,0x83,0xfd,0x73,0x8b,0xd2,0x0f,0xe7,0xbc,0x91,0x70,0x69,0x19,0xba,0x22,0xbd,
+  0xe9,0xc8,0x6a,0x7f,0x83,0x72,0x0a,0xb2,0xd9,0xfa,0x7e,0xff,0xcd,0x8a,0x7d,0x3e,
+  0x42,0xf8,0xcb,0x9e,0x0e,0x36,0x5e,0x1e,0xa3,0x61,0x9a,0xd9,0x64,0x96,0x9c,0x57,
+  0x26,0xcd,0x6b,0x91,0x26,0x02,0xce,0xf5,0x40,0xe8,0xb8,0x24,0xab,0x8c,0x79,0xaf,
+  0xea,0x4d,0xbc,0xf4,0x79,0x65,0xe4,0xde,0xb3,0xd0,0xf4,0x72,0x6d,0xab,0x32,0x38,
+  0x23,0x8f,0xbf,0x24,0x48,0x37,0x08,0xa4,0x73,0xb9,0xc0,0x72,0x74,0x0b,0xc5,0x8b,
+  0x34,0x10,0x45,0x98,0x2c,0x76,0x3d,0x74,0x1d,0x6d,0x63,0x66,0xe0,0x90,0x52,0xc3,
+  0x11,0x5c,0xf7,0x05,0x78,0xe5,0x7c,0x17,0xfe,0x32,0x71,0x7f,0x1f,0x0d,0x36,0xaa,
+  0xff,0x93,0x55,0x9b,0x9d,0xad,0xec,0xcb,0x08,0xbb,0x2a,0x10,0xc8,0xe3,0x4e,0xd4,
+  0x1d,0x47,0x20,0x46,0x06,0x02,0x31,0xae,0xd9,0x46,0x9f,0x16,0x65,0xfe,0xf4,0x06,
+  0xa8,0x1e,0x58,0xd1,0xca,0xca,0xf2,0xf8,0x8b,0x7a,0x75,0xc5,0xfa,0x60,0x19,0xc2,
+  0xae,0x6a,0x43,0x6b,0xc1,0xee,0x95,0x3d,0x4f,0xfd,0x9c,0xae,0x48,0xab,0x2d,0x02,
+  0x37,0x55,0x1b,0xb7,0x48,0xe3,0x1b,0x06,0x5e,0xfa,0x11,0x82,0x35,0x1c,0x8b,0x7b,
+  0x58,0x24,0x87,0xbf,0xec,0x51,0x0e,0x96,0xa2,0x9b,0x21,0x86,0x5b,0xbc,0x09,0xa6,
+  0x3d,0xee,0x08,0xc4,0x5e,0x60,0x1f,0x75,0x1c,0x89,0x87,0x7b,0x35,0x34,0xda,0xef,
+  0x8a,0xd7,0x9c,0x41,0x0f,0x64,0x73,0x71,0xb2,0x15,0x17,0x73,0xfd,0xe6,0xb2,0x3c,
+  0xfe,0xba,0x2c,0xba,0x45,0x9b,0x8f,0x3e,0xad,0xe8,0x9f,0x61,0x6c,0x29,0xdb,0x25,
+  0x0d,0x6f,0xb4,0xcd,0xbf,0x67,0xe9,0xfb,0x70,0x99,0x80,0xd8,0x1e,0xe5,0x7d,0x78,
+  0x08,0xe7,0xb2,0x40,0x64,0xa7,0x2c,0x6c,0xc9,0x2a,0x0d,0x05,0xf8,0x4b,0x80,0x2c,
+  0x53,0xce,0xaf,0xa5,0xd2,0x9d,0x2b,0x95,0xbd,0x2a,0x66,0x9c,0xc0,0x5f,0xa0,0xa1,
+  0xe1,0x15,0xf7,0xa0,0xcb,0xc7,0x08,0x9a,0x6d,0xe9,0x50,0xdc,0xf8,0x4b,0xb8,0xf1,
+  0xd3,0xab,0xc0,0xc1,0x05,0xb6,0xb1,0x74,0x48,0x1f,0xf7,0xc6,0x4c,0x7f,0x6a,0x69,
+  0x95,0xed,0xd8,0xdb,0x86,0x5f,0xde,0x13,0x35,0xc3,0x29,0x85,0xd9,0xf8,0xcb,0x8b,
+  0xf8,0x4b,0x80,0xa3,0x9b,0x69,0xee,0x34,0x08,0x94,0xe4,0x39,0x84,0xcf,0xd1,0x24,
+  0xec,0xaa,0x31,0xab,0x09,0x29,0x6c,0xf4,0x04,0xa9,0xa5,0x0a,0x91,0x94,0xe3,0x51,
+  0x43,0xb0,0xb9,0x23,0xd5,0x6c,0xb8,0xf1,0x57,0x8d,0xd9,0xa9,0xa3,0x2f,0x21,0xf0,
+  0xd7,0xa0,0xfd,0x71,0xfb,0x39,0x61,0x53,0x15,0xb0,0x0b,0x3e,0x4f,0x97,0xc8,0xa8,
+  0xc4,0xe7,0x94,0x0d,0x79,0xf7,0xc3,0xdc,0xb8,0x3a,0x93,0x15,0xe5,0xf0,0x97,0xbe,
+  0x3f,0x14,0x36,0x6f,0x29,0x4f,0xcc,0xc8,0x3e,0x1a,0x9a,0x47,0xf8,0x0b,0x91,0x02,
+  0x18,0xcb,0x35,0x9a,0x9e,0xfb,0x59,0xf5,0xf2,0x8d,0x08,0xcd,0xd2,0x8f,0x0a,0x44,
+  0x26,0x8c,0x8a,0xe5,0xb8,0x6d,0xf5,0xf3,0xfd,0xc6,0x9e,0x96,0x90,0xee,0x63,0x2e,
+  0xfc,0x65,0x60,0x3f,0x3f,0xc6,0x2a,0xb6,0x9e,0x31,0x62,0x04,0xbb,0x70,0xc1,0x0f,
+  0xd5,0xa8,0xf2,0xed,0x0d,0x35,0x22,0xda,0xd2,0x8c,0xc4,0x80,0xf1,0x82,0xba,0x45,
+  0x1a,0xdd,0x6a,0x58,0x5c,0xfa,0x52,0xdd,0x0c,0x3f,0x68,0x35,0x36,0xfe,0xfa,0x9c,
+  0xec,0xd5,0x55,0xdb,0x96,0x0e,0xf1,0x6f,0xe7,0xfb,0xb9,0xc9,0xdc,0x92,0xaa,0x1c,
+  0x52,0xf1,0xd2,0xf2,0x2d,0xdb,0x92,0x7b,0xd2,0xe3,0xa1,0x06,0x1b,0x7f,0x85,0x10,
+  0x7f,0x6d,0x55,0x86,0xcc,0x2b,0x7a,0xc3,0xb2,0xc0,0x6b,0x49,0x1b,0x7f,0xcd,0x9c,
+  0xe6,0x8c,0x8e,0x40,0xc7,0x51,0xd3,0x4b,0xbd,0xea,0x1a,0x38,0x1a,0x9d,0xf2,0x3d,
+  0x5e,0x7b,0x98,0x10,0x9a,0x79,0xea,0x9c,0xf1,0xea,0x26,0xfc,0x55,0x94,0xc3,0x5f,
+  0xd0,0x23,0x61,0x97,0x73,0x36,0x88,0x86,0xdd,0x82,0x97,0x58,0x9d,0x6c,0xe9,0x90,
+  0xb0,0x2b,0x77,0x0f,0x7d,0x2a,0x88,0xff,0x51,0xf6,0x84,0x0b,0x7f,0x79,0xc2,0x34,
+  0x5e,0xed,0x62,0xad,0x9b,0x49,0x8b,0xde,0x7e,0xa8,0x32,0x65,0x3f,0xe7,0x61,0x17,
+  0xad,0x87,0x65,0x5e,0xef,0x56,0x06,0xa6,0x9a,0xbb,0x34,0xd3,0x57,0x80,0xbf,0x68,
+  0x94,0x9b,0xe5,0xda,0x3b,0x93,0x5e,0x12,0x6c,0x69,0xb1,0xc7,0x7d,0x6e,0x7e,0x59,
+  0xbe,0x99,0x8c,0xa7,0xc4,0xfb,0x53,0x44,0x97,0xc4,0x9f,0x78,0xcc,0x8d,0xbf,0xa8,
+  0x37,0xd8,0x1e,0xfb,0x5d,0x5d,0x2a,0xfa,0x27,0x9e,0xeb,0x9f,0x10,0xee,0x8d,0x74,
+  0xa9,0xb5,0x94,0x2e,0xbd,0xc1,0x9c,0xf7,0x39,0x8e,0xef,0xf3,0x0e,0xc5,0x8d,0xbf,
+  0x64,0xaf,0xf6,0xfb,0xce,0x07,0x8f,0xb6,0xfc,0xb4,0x4c,0x1b,0xca,0xf7,0xf3,0x79,
+  0x68,0x34,0x03,0x7a,0x65,0x3f,0x3b,0x0f,0x47,0xcd,0x6a,0x5d,0xeb,0x67,0xbd,0xec,
+  0xa8,0x59,0x9b,0x9b,0x3b,0x4f,0x23,0xfe,0x92,0xb8,0x89,0xf0,0x17,0xce,0x4a,0x0d,
+  0xe8,0x88,0xc9,0x13,0x83,0x55,0xf6,0xa2,0x07,0xce,0xea,0x07,0xe2,0x28,0x18,0x0d,
+  0x5d,0xbe,0x36,0x4c,0x5c,0x32,0x60,0x94,0xf0,0x57,0x42,0xf3,0xe5,0xf1,0x97,0xbd,
+  0x6d,0x21,0xec,0xf2,0xd4,0xf0,0xd2,0x74,0x7e,0x23,0x93,0x86,0x40,0x64,0x64,0x74,
+  0xa4,0x83,0xc3,0x33,0x0f,0x7b,0xe9,0x52,0x59,0x08,0x17,0xe1,0x4a,0xae,0x0e,0x6b,
+  0xcb,0xe5,0xfb,0x1c,0x12,0xfb,0x97,0x58,0xbe,0xfc,0xce,0x3a,0x76,0xb2,0x60,0xff,
+  0xb2,0x42,0x11,0x9f,0xbf,0xb0,0x85,0xd6,0x3a,0x74,0x1d,0x8d,0xac,0xba,0xd0,0xe7,
+  0xb3,0xf1,0x97,0xc7,0x3e,0x04,0x7b,0xa0,0x68,0x16,0xba,0xfa,0xd5,0x96,0xcf,0x5e,
+  0x84,0x7b,0xe5,0x6a,0xec,0xad,0xb6,0x3a,0xa2,0x74,0x50,0xa6,0xd3,0x3d,0xd4,0x12,
+  0x41,0x63,0x2c,0xf8,0x65,0x78,0xc6,0x30,0xfa,0xd4,0x78,0x62,0x4d,0x1e,0x7f,0x1d,
+  0x4c,0x2c,0xce,0x06,0x26,0x94,0x98,0xf1,0x4b,0x8e,0x06,0x02,0x31,0xf8,0x34,0x6f,
+  0x34,0x8e,0x86,0x1f,0x49,0xce,0x36,0x3e,0xed,0x68,0xca,0x6a,0x0f,0x2b,0xbf,0x33,
+  0x3e,0xdd,0x5b,0xf2,0x0e,0xee,0x4d,0x5f,0x81,0x6b,0x83,0x15,0x88,0xbf,0xb4,0xf9,
+  0x79,0xfc,0x25,0xbd,0x02,0x66,0xfb,0xf3,0x99,0xca,0x11,0xb7,0x03,0x13,0x7b,0x33,
+  0x90,0xf9,0x5b,0x61,0xbc,0xe2,0x27,0x37,0x1e,0x8d,0xde,0x40,0xa6,0x1c,0xbd,0xa6,
+  0x38,0x0e,0x4a,0x5a,0xb1,0xf1,0x17,0x90,0x7f,0x98,0x42,0xd8,0x75,0x28,0xf9,0xf1,
+  0xda,0xd3,0x12,0x7f,0x5d,0x35,0xaf,0x51,0xcb,0x58,0xe5,0xc7,0x26,0x01,0xb1,0xcd,
+  0xd8,0x12,0x9f,0x20,0xff,0x67,0x52,0xa1,0x96,0xd8,0xef,0x71,0xd3,0x8c,0xc1,0x77,
+  0x52,0x75,0xab,0xfd,0x3d,0x0a,0xe4,0xf1,0x17,0xee,0x3b,0xd6,0x52,0xdc,0x65,0x56,
+  0x3f,0x33,0xb3,0xfa,0x15,0xed,0x9b,0x09,0xd1,0x3f,0xaf,0x60,0xff,0xbc,0xcd,0xbb,
+  0xf5,0x0a,0xec,0xb1,0xc4,0x97,0xe3,0x07,0x77,0x54,0x7f,0x80,0x97,0xde,0xce,0x76,
+  0xcf,0xf4,0xbf,0xa7,0x7d,0x5b,0xc1,0xde,0xa0,0x03,0xc0,0xbf,0x4e,0x3c,0x6b,0x9f,
+  0x87,0x13,0xfe,0x32,0xaa,0x05,0xc8,0x82,0x0d,0x20,0x0d,0x75,0x11,0x2b,0xb1,0xec,
+  0x5d,0xaf,0xc2,0x42,0xaf,0xe0,0xcb,0x5e,0x7c,0xf2,0x49,0x6a,0xe1,0x68,0x0c,0x68,
+  0xdf,0xa2,0xbd,0x52,0xdd,0xb9,0x0c,0xf1,0x17,0xc8,0xf7,0xd0,0x98,0x71,0xd2,0x63,
+  0x0f,0xe5,0xab,0xb0,0xdb,0x0c,0x0f,0x6a,0x0b,0xc9,0xbd,0x44,0x44,0x66,0x8f,0x72,
+  0x70,0x50,0x6b,0x64,0x7f,0x81,0x6b,0x84,0xb8,0xf4,0x2a,0x74,0x2f,0x43,0x83,0x5e,
+  0x12,0x1c,0x77,0x8f,0xda,0xc8,0x3a,0xbc,0x62,0x7d,0xde,0xfb,0x19,0xbb,0x9f,0x47,
+  0xcb,0xaf,0xea,0x27,0xa8,0x13,0x7a,0x64,0xf7,0x9e,0xa3,0x7e,0xd6,0x27,0xbc,0xdd,
+  0x83,0x25,0x63,0x4b,0x1f,0x41,0xdf,0x58,0x76,0x9d,0x34,0x08,0xc2,0x5c,0xe3,0xd1,
+  0xb6,0xc6,0x3b,0xb5,0xf9,0x79,0xfc,0x25,0x87,0x00,0x61,0xd7,0x45,0xb5,0xb1,0x2f,
+  0x10,0x49,0xba,0xc6,0xeb,0x22,0x01,0xb1,0x48,0x72,0xa5,0x73,0xe9,0x64,0x95,0x30,
+  0xe8,0x4f,0x5c,0x24,0x9f,0x3f,0x5d,0x6e,0xe3,0x2f,0x8f,0x9e,0x73,0xe3,0x1b,0xe1,
+  0x34,0xdc,0x65,0x09,0xae,0xc4,0x6e,0x99,0x14,0xae,0xa3,0x9f,0x90,0xc2,0x69,0x58,
+  0x64,0xa9,0x78,0xc9,0x73,0x1a,0x16,0x20,0x92,0xa2,0x4b,0xde,0x6e,0x5e,0x32,0xaa,
+  0xc0,0x32,0xf1,0x9c,0x36,0xc4,0x5f,0x02,0x76,0x65,0x04,0xec,0x0a,0x0a,0x00,0xe5,
+  0x91,0x2d,0xd2,0x91,0xa6,0x57,0x8b,0x2e,0x45,0xe9,0x92,0x00,0x62,0x96,0x5f,0x5e,
+  0x0a,0x96,0xe3,0xd4,0x73,0xe3,0x2f,0x01,0xdf,0x58,0xee,0x39,0x6b,0xd5,0x23,0x0e,
+  0xec,0x22,0x17,0x3d,0x44,0xcf,0x79,0x0e,0x0d,0x1f,0x5e,0x82,0x1f,0xca,0x7b,0xe8,
+  0x52,0x1c,0xd0,0x48,0xe7,0xf1,0x17,0x8e,0x05,0x3e,0x67,0x93,0x3f,0x41,0xe7,0x24,
+  0x38,0x2b,0xe5,0xcc,0x5d,0x11,0x09,0x9e,0xec,0xe8,0x5e,0x12,0xb2,0xb4,0x85,0x3e,
+  0x3f,0x1d,0xa1,0x0c,0x3c,0x14,0xf1,0x9d,0x4c,0x24,0x4d,0xde,0x1f,0x8a,0x26,0x5e,
+  0xe5,0xdd,0x0d,0xe9,0x01,0x75,0x2b,0xb3,0xf7,0x2f,0x20,0xfc,0x45,0x87,0x0f,0x17,
+  0x94,0x59,0xc6,0x09,0xea,0x0d,0x1a,0x8b,0x23,0x7a,0xc3,0x20,0xcd,0x14,0x63,0xc2,
+  0x5c,0x20,0xfb,0x67,0x0b,0x2c,0x38,0x59,0x4a,0x48,0xea,0x77,0xb0,0xe0,0x4d,0x7f,
+  0x17,0x0e,0xc1,0xb5,0x78,0x44,0xad,0x8e,0x24,0x21,0x8f,0xbf,0xae,0xe9,0xb7,0x5a,
+  0x6e,0xdc,0x84,0x1e,0xa3,0xd1,0x74,0x1c,0x9d,0xf6,0x49,0x32,0xe8,0x4f,0xd0,0x3d,
+  0x77,0x9d,0x7c,0x7c,0x54,0x59,0x7c,0x13,0xb5,0x94,0x76,0x25,0x3f,0xe2,0x68,0xe8,
+  0x1b,0x46,0x95,0x61,0x1b,0x7f,0xe1,0xcd,0xa7,0x43,0x88,0xa4,0x2e,0x24,0x1b,0xf9,
+  0xe9,0x50,0xd3,0x2f,0xfc,0x17,0x08,0x76,0xe1,0x03,0xfd,0x63,0x5a,0xac,0xec,0x2d,
+  0xab,0x29,0x1b,0x46,0x03,0xfe,0x00,0x8b,0xfa,0xfd,0x63,0x08,0x97,0xc4,0x3b,0x86,
+  0x2f,0x52,0xd1,0x69,0xd6,0x60,0xae,0x32,0x97,0xe6,0xf0,0xd7,0x15,0xd8,0x62,0x56,
+  0x0e,0xaa,0x93,0x77,0xc7,0x5a,0xb7,0xf4,0xd7,0x9e,0x2c,0x99,0x6c,0x46,0xd8,0xd5,
+  0x5e,0x53,0x21,0x76,0x2b,0x6e,0xd4,0xd0,0x6e,0x15,0x4e,0x1d,0xe1,0xf3,0xce,0x22,
+  0xba,0x19,0x21,0x22,0x2c,0xab,0x91,0xb1,0x05,0x82,0x71,0x34,0xd2,0x39,0xfe,0xcb,
+  0xa4,0x53,0xf4,0x10,0xba,0x6a,0x62,0x3d,0x54,0x6f,0xb7,0x17,0x3d,0x55,0xac,0x90,
+  0xf2,0x5c,0xdd,0x6f,0xe0,0x6e,0x35,0x80,0x2d,0x23,0x34,0x65,0xa8,0x65,0x84,0xce,
+  0x9a,0xce,0x69,0x91,0xa2,0x3c,0xfe,0x2a,0xa3,0x31,0x6d,0xc9,0x94,0x85,0xbd,0x9d,
+  0xde,0x9a,0x5e,0x7b,0x4c,0xf1,0x6b,0x48,0x92,0x2b,0x4c,0x46,0xd8,0x8b,0x08,0x51,
+  0x0e,0xf7,0x0f,0x11,0x92,0x4b,0x24,0x0e,0xbb,0xd2,0x5a,0xcf,0x2b,0x99,0x3c,0xfe,
+  0xfa,0x50,0x0c,0x93,0xb6,0x8f,0x9d,0x60,0x31,0xcb,0xa0,0x73,0xa4,0x97,0xd0,0x51,
+  0x5c,0xd9,0x55,0x19,0xe6,0xc7,0x70,0x5e,0xac,0xec,0x2a,0x0f,0xeb,0x47,0x3a,0xc4,
+  0x50,0x9e,0xf4,0x9c,0x90,0x53,0xe6,0x24,0xe0,0xe0,0xc6,0x71,0xdf,0xc9,0xf1,0x5f,
+  0xfb,0xe0,0x2d,0x0f,0xd1,0x5e,0x7f,0x75,0xd6,0x3b,0xc1,0x9a,0x72,0x03,0xd7,0x5a,
+  0xdb,0x5b,0x39,0x6a,0x7e,0x0c,0x88,0x8e,0x7b,0xb1,0xe5,0x8f,0xfe,0xc5,0xbd,0xff,
+  0x86,0x97,0xd8,0x27,0x62,0x4c,0x2b,0xf1,0x1e,0x6f,0x1d,0x04,0xd6,0x29,0x39,0xfc,
+  0xb5,0x19,0x5e,0x86,0x68,0xd6,0x2f,0x57,0xd1,0x88,0x9c,0x9e,0x1f,0x42,0x23,0x17,
+  0x93,0x7a,0x5c,0x42,0x33,0xbc,0x54,0x24,0xbe,0x8f,0x38,0xe0,0x12,0x2d,0xe6,0x87,
+  0x38,0x4f,0xfd,0xfb,0xf3,0xf8,0xab,0x11,0xb6,0xb4,0x56,0x5a,0xea,0xa7,0x08,0xa9,
+  0x5e,0xc2,0xc9,0xa8,0x8d,0x3a,0xf8,0x8b,0x9c,0x8a,0xc3,0xe8,0x54,0xa0,0x81,0x3d,
+  0xc6,0x76,0xe3,0xf4,0x64,0x23,0xbc,0xd3,0x99,0x7a,0x38,0x5e,0x1d,0x2d,0x3f,0x67,
+  0x2e,0xfc,0x95,0x5c,0x86,0x53,0xa6,0x9e,0x39,0xc0,0x19,0x8d,0xdd,0x20,0x88,0x30,
+  0x0b,0x11,0x99,0x01,0x3e,0x28,0xa2,0xb3,0xa6,0x35,0x34,0x82,0xa7,0xe8,0x12,0xdd,
+  0x73,0x0a,0x67,0x5c,0xc8,0xc4,0x75,0x6c,0x7d,0x0e,0x7f,0xb1,0x0d,0x69,0x23,0x3b,
+  0x73,0x7d,0xd9,0xdb,0xde,0x83,0x7c,0x0e,0xc2,0x81,0x66,0x84,0x03,0x6d,0xd5,0x7b,
+  0x05,0x2e,0x78,0x7e,0xa7,0x0d,0x10,0x9e,0xdf,0xf1,0xf7,0x43,0x04,0xbb,0x60,0x43,
+  0x1a,0xe1,0xc0,0x43,0xec,0x6d,0x73,0x43,0xba,0xa2,0x5e,0x5d,0xcf,0xee,0xc9,0xf3,
+  0x5f,0x2f,0x23,0xfe,0xf2,0x47,0xa6,0x9f,0xc4,0x55,0x2b,0x32,0x1c,0x88,0xe0,0x58,
+  0xfc,0x07,0x6f,0x5c,0x83,0x40,0x0c,0xbf,0x4f,0x22,0x02,0x5b,0x54,0x6c,0x39,0x0f,
+  0xf5,0xc3,0xfe,0x08,0xf6,0xcf,0xdf,0x26,0x1a,0x87,0x03,0xf5,0xca,0xc7,0xfc,0xc3,
+  0xf4,0xfa,0x35,0xd8,0x72,0x77,0x9e,0xff,0x9a,0x80,0xa6,0xc1,0x5a,0xea,0xc3,0x6b,
+  0x10,0xeb,0x97,0xe3,0xd5,0xda,0xd4,0x8e,0xc6,0x08,0x5c,0x21,0x6a,0x6c,0xac,0x9c,
+  0x16,0xb4,0x3a,0xeb,0x4f,0x47,0xf3,0xf7,0x60,0xcf,0xeb,0x31,0xc0,0x4f,0xa5,0x1c,
+  0xfe,0xeb,0x23,0xf3,0xc4,0x60,0x5d,0x7f,0xe0,0x40,0x72,0x84,0x4f,0x44,0x62,0xa7,
+  0xfc,0x99,0xe4,0x88,0x3a,0xd1,0x1a,0xb5,0xfd,0x0d,0x7e,0x98,0x00,0xc2,0xc7,0x74,
+  0x22,0x7d,0x01,0x97,0xc1,0x8f,0xe1,0x84,0xa7,0x31,0xbb,0x99,0xfa,0xf9,0x04,0x9d,
+  0xaa,0x65,0x94,0x3c,0xff,0x95,0xde,0xa2,0x56,0x88,0xbd,0x3b,0x4d,0x9b,0xb8,0xfa,
+  0xa0,0xd8,0x6e,0xee,0xc8,0xef,0x3b,0x68,0x4c,0xc2,0xa3,0x70,0xdb,0x19,0xd5,0xd9,
+  0x9b,0x54,0x6a,0x41,0x03,0xd0,0xc8,0xf1,0x5f,0x4f,0x24,0x36,0x50,0xf7,0x7e,0x9b,
+  0xbd,0xdd,0x4a,0x40,0x4c,0x5d,0x2f,0xf1,0x17,0x01,0x31,0x42,0x5b,0x15,0x86,0x0f,
+  0x11,0x99,0xfa,0x0c,0x51,0x63,0xeb,0x83,0x5f,0x61,0x1b,0x9c,0x7b,0x36,0xf0,0x70,
+  0x1c,0x8d,0x3c,0xff,0x25,0x4e,0x77,0x3b,0xc5,0xe9,0x93,0x9c,0x9e,0xe2,0x05,0x38,
+  0x93,0xc3,0x5f,0x5a,0x04,0xe8,0x9e,0x50,0xaf,0xb8,0x44,0x73,0xb9,0x03,0x0d,0x15,
+  0x0d,0x1d,0x67,0xb7,0x8b,0xff,0x3a,0x0e,0x75,0x0e,0xec,0xa2,0xd3,0x03,0x61,0x04,
+  0x53,0x76,0x4b,0x94,0x88,0xb0,0x61,0xf8,0xd8,0x8c,0xb6,0xfd,0x09,0x79,0x56,0x44,
+  0x7b,0xa9,0xd4,0x72,0x1c,0x9a,0x52,0xfe,0x6c,0x9e,0xff,0xb2,0xd8,0x98,0x89,0x9e,
+  0x03,0xb8,0xdd,0xb9,0x51,0x7c,0xa3,0x73,0xb0,0x0b,0x8d,0xac,0x3a,0x76,0xcf,0x14,
+  0x97,0x0f,0x7f,0x50,0x8c,0x05,0xdc,0xf8,0x8b,0x09,0x1a,0x65,0x07,0xfa,0xea,0xe7,
+  0x21,0xba,0xc4,0xaf,0x0b,0x7f,0x3e,0x5a,0x08,0xc4,0xe0,0x3c,0x77,0xb5,0x68,0x29,
+  0xe5,0x3d,0x5c,0x0a,0xa2,0xeb,0x02,0xba,0x92,0xc8,0xe3,0xaf,0x8d,0xab,0x6b,0x96,
+  0x68,0x3b,0x7c,0x55,0x5e,0x84,0x54,0xe6,0x72,0xe9,0x3f,0x07,0xf3,0xf8,0x4b,0x1a,
+  0x03,0xc4,0x88,0xb1,0xdf,0x7b,0xed,0x96,0xdf,0xc3,0x1b,0x10,0x6c,0x45,0xc3,0x85,
+  0xbf,0x36,0x42,0x4d,0x7c,0xc5,0xb6,0xe6,0x2a,0xe9,0x5a,0xcb,0xe7,0xec,0x22,0xb4,
+  0x75,0x09,0x7e,0x9a,0x43,0x64,0xba,0x78,0xf2,0xbb,0xad,0x02,0xac,0xa5,0x58,0xbf,
+  0x17,0x3d,0xf3,0x66,0x6d,0x2b,0x7b,0x2c,0x87,0xbf,0xd2,0x6d,0xa1,0xf0,0x0a,0xad,
+  0x2c,0xe1,0x4d,0xef,0x0f,0x19,0x5f,0xf4,0xa1,0x81,0x88,0xac,0x62,0xb9,0xd6,0xca,
+  0x5e,0x87,0xe7,0xf5,0x6a,0x53,0x6b,0x2d,0xea,0x37,0xf7,0x87,0xaa,0x96,0xd9,0x48,
+  0x21,0x6c,0x2a,0x74,0xf6,0xb5,0x15,0xd2,0xcb,0xb5,0x9b,0x13,0x79,0xfc,0xc5,0x07,
+  0x08,0x76,0xed,0x52,0x0c,0x3e,0x66,0x64,0x66,0x12,0xda,0x82,0xb1,0xe0,0x03,0x88,
+  0xbf,0x70,0xdd,0xc8,0xe2,0x10,0x60,0x3f,0x9f,0x43,0x8c,0x16,0xbd,0x59,0xe3,0x9e,
+  0x5e,0xd3,0xf6,0x9f,0xb3,0x6c,0x60,0x5e,0x14,0x11,0x99,0xf2,0xb3,0x1c,0xff,0x25,
+  0x21,0x95,0xe8,0x43,0x4f,0xac,0x25,0xdf,0xbd,0x88,0xb6,0xf6,0x8d,0x1b,0xb1,0x15,
+  0x1a,0x1a,0xfc,0x0f,0x20,0x2e,0x5d,0x72,0x5c,0xfd,0x4b,0xf8,0xa9,0x26,0x33,0xcf,
+  0x7f,0x11,0xfe,0x7a,0x15,0x16,0x99,0xfe,0xc1,0xa5,0xce,0x30,0x05,0xe5,0x73,0x42,
+  0x44,0x7b,0xe1,0x24,0x12,0xb0,0x4b,0xfd,0x08,0xca,0xcc,0xcd,0xf4,0x9c,0x63,0x20,
+  0x3e,0x4e,0x06,0x11,0x61,0xf0,0xb5,0x3c,0xfe,0xea,0xf0,0x12,0x93,0x55,0x66,0xe8,
+  0x3d,0x72,0xf5,0x93,0x88,0xcc,0x46,0x5b,0x73,0xd1,0x08,0x1a,0x9e,0x4d,0xd0,0x88,
+  0x13,0x96,0x65,0x59,0x87,0x03,0xcd,0xce,0x00,0x42,0xb3,0x34,0x2b,0x85,0x1c,0xfe,
+  0x6a,0x03,0xef,0x12,0x55,0xc2,0x2e,0xc3,0x5c,0xa1,0x83,0xec,0x4c,0x1b,0x76,0x55,
+  0x99,0x1d,0x64,0xec,0x04,0x83,0xee,0xe9,0x9f,0xd6,0xe6,0x09,0x4b,0x68,0xd6,0x06,
+  0xab,0xe3,0xd8,0xd2,0x3c,0x2d,0x87,0xbf,0x08,0x5b,0xb5,0x88,0xe1,0xf6,0x88,0xc1,
+  0x5d,0xed,0xa1,0xc1,0xb5,0x61,0x97,0xc0,0x5f,0x5e,0x9b,0x5a,0xc5,0x8f,0xe7,0x8c,
+  0xa7,0xc8,0x81,0x49,0xb9,0xf9,0xaf,0x63,0x50,0x67,0xae,0x4c,0x69,0x44,0x02,0x76,
+  0xd9,0x2f,0xad,0x38,0x46,0x20,0x92,0x0b,0x2f,0x09,0xb6,0x6b,0xa7,0x69,0xc3,0xae,
+  0x63,0x0e,0xa4,0x3a,0x06,0x3f,0x69,0x6d,0x4c,0x29,0x6b,0x72,0xf8,0x8b,0xe1,0x30,
+  0x21,0x3a,0x56,0x86,0xdc,0xf0,0xb6,0x71,0x89,0x6d,0xd4,0xc9,0x79,0x31,0xbe,0xb7,
+  0x91,0x98,0x35,0xf7,0x3d,0x9e,0xc6,0xd5,0x81,0xb2,0x3c,0xff,0xc5,0x8b,0x06,0xd4,
+  0x18,0x94,0x70,0x3a,0x52,0xc6,0x39,0x18,0xe6,0x95,0xce,0x64,0xfc,0x5b,0x9c,0x9e,
+  0x68,0x6c,0x91,0x2d,0x51,0x78,0x1c,0x5f,0x1b,0x63,0x58,0xce,0x53,0xc3,0xc0,0x7e,
+  0xf6,0xfa,0xdb,0x2b,0xf3,0xf8,0x4b,0x7d,0xa2,0x0d,0x41,0xd6,0x1a,0x41,0x7b,0xd5,
+  0xb4,0x0d,0x14,0xe2,0x2f,0x44,0x64,0xc5,0x68,0xa8,0x2f,0xa6,0x83,0x6d,0x38,0x3a,
+  0x97,0xed,0x4b,0xf7,0xdd,0x85,0x37,0x57,0x6e,0x6f,0x79,0x97,0xf9,0xf2,0xfc,0x57,
+  0xa7,0x59,0x63,0x15,0xcf,0x6b,0x26,0xfc,0xb5,0xd6,0x59,0xc7,0xc2,0x72,0xb3,0xeb,
+  0x96,0xbb,0xde,0x49,0xc8,0xfc,0x99,0x61,0x6d,0x74,0xed,0x5f,0xab,0xcc,0x1f,0x82,
+  0x31,0x1a,0x8a,0x14,0xe5,0xf1,0x17,0x7f,0x4c,0xad,0x36,0xd5,0x75,0x65,0xa5,0xb8,
+  0xe4,0x86,0x87,0xd1,0x38,0x2b,0x11,0x19,0xae,0xc6,0x04,0x07,0x06,0xbe,0x40,0xcb,
+  0x72,0x46,0xb2,0x30,0x67,0x8d,0x83,0xf0,0x8d,0x5e,0x6d,0x7d,0xd1,0x97,0x20,0xa9,
+  0x93,0xb7,0x93,0x08,0x39,0xf8,0xab,0x09,0x5e,0xe1,0x4d,0xf1,0x92,0xf5,0xca,0x6c,
+  0x86,0xf8,0x6b,0xc8,0x5f,0x88,0xbf,0xf6,0x2e,0x1e,0x0d,0x3c,0x94,0x7c,0xbb,0xe3,
+  0x0f,0x7c,0x7f,0xb6,0x64,0xbd,0xe7,0x4d,0xf8,0x3d,0x27,0x46,0x4c,0xf9,0x47,0xf8,
+  0x6d,0xfa,0xf6,0xec,0x4a,0xc4,0x5f,0x90,0xc3,0x5f,0x97,0x69,0x08,0x68,0x8f,0xfb,
+  0x0e,0x7a,0x29,0x0e,0xec,0xb2,0x70,0x27,0xfa,0x88,0x5c,0xd0,0xd7,0x4a,0x5e,0x60,
+  0x1f,0x51,0x48,0xcf,0x20,0x05,0xf0,0x20,0x52,0x78,0xc4,0xc2,0x9b,0xf7,0xc0,0x04,
+  0x43,0x7f,0x9e,0x2b,0x7d,0xde,0x1c,0xfe,0x3a,0x95,0xea,0xce,0xfa,0xdf,0x27,0xd8,
+  0xc5,0x17,0xbc,0x23,0x88,0xb0,0x6b,0x02,0x4d,0x24,0xaf,0xc5,0xaf,0x75,0x10,0x11,
+  0x96,0xbc,0x6a,0x5c,0x4a,0x55,0x5e,0xf0,0x8e,0x29,0x7f,0x6c,0x11,0x97,0x0e,0xe1,
+  0x46,0x76,0x2d,0xb5,0x60,0x28,0xe0,0xe2,0xbf,0x8e,0x9a,0xc9,0x74,0x85,0xd9,0xf1,
+  0x50,0xd9,0xdb,0x88,0x89,0xe6,0x67,0xb1,0x13,0xbe,0x2c,0xfb,0x99,0xf0,0xd7,0x35,
+  0xda,0xbf,0x22,0xd8,0x3f,0x07,0xda,0x17,0x66,0x11,0xba,0xfe,0x91,0xff,0x12,0xaa,
+  0x47,0xb4,0x7a,0x76,0x9a,0x4f,0xf0,0x8a,0x93,0xda,0x03,0xc1,0x0f,0xf2,0xf8,0xeb,
+  0xb1,0xa0,0xc7,0x54,0xbf,0x45,0xa7,0x8e,0x30,0x67,0x40,0xb5,0x71,0xae,0xe8,0x67,
+  0x13,0xf7,0xc1,0x3e,0xb1,0x21,0x1e,0x40,0xff,0xb0,0x63,0x1d,0x1b,0x6c,0xb3,0x31,
+  0xda,0x20,0xfe,0xd1,0x8a,0x54,0xe7,0xba,0xc7,0xfa,0x73,0xf8,0x8b,0x25,0xe8,0xc8,
+  0x02,0x37,0x29,0xbd,0xdb,0x5b,0x43,0x7b,0x93,0xf0,0xe7,0xcf,0x68,0x31,0x1c,0xe5,
+  0x23,0x26,0x6e,0x64,0x0b,0x13,0x23,0x90,0x79,0x7a,0xae,0xe5,0x8b,0x30,0xcb,0x63,
+  0x63,0xf3,0x2c,0xec,0xf6,0x18,0x5c,0xf3,0xb3,0x33,0x72,0x9d,0xdf,0xfb,0x99,0xa3,
+  0x14,0xb6,0x61,0xad,0x4c,0x89,0xd3,0xef,0x45,0x96,0xdf,0xe9,0x67,0xed,0xb2,0x72,
+  0xc5,0xb8,0x96,0xee,0x1e,0x0d,0x4c,0xe2,0xf6,0x33,0x6a,0x2d,0x10,0x97,0x98,0xf4,
+  0x0f,0xff,0x9c,0x7c,0xad,0xae,0x5f,0x91,0xe3,0x91,0xc7,0x5f,0x17,0x70,0xbc,0x6a,
+  0x33,0x95,0x27,0xe9,0x78,0x9f,0xd8,0xae,0xb5,0xf4,0x9c,0x7e,0x1a,0x38,0xfe,0xa1,
+  0x8a,0x9f,0xda,0x5f,0x39,0xe2,0x1d,0x73,0x21,0x68,0x32,0xde,0x25,0x63,0x30,0x70,
+  0x40,0xc9,0xe3,0x2f,0x15,0x37,0x4d,0x13,0x91,0xd4,0xa4,0x7a,0x1a,0x1d,0xce,0xbf,
+  0x18,0x2d,0x6f,0xf4,0x3a,0xf8,0x4b,0xbf,0x06,0x0b,0x7a,0x85,0x57,0x79,0xf2,0xa6,
+  0x45,0x04,0x34,0x72,0xd8,0xe1,0x12,0x3f,0x0d,0x8b,0x07,0xfc,0x97,0x93,0x36,0xff,
+  0x45,0xf8,0xeb,0x70,0x3b,0xf6,0xcf,0xd1,0x04,0xb9,0xc4,0x35,0x04,0x8e,0x6c,0x24,
+  0x45,0x87,0xf0,0x47,0x04,0x8f,0x56,0x36,0x02,0x1d,0xd6,0x7c,0xf2,0x0f,0x87,0x6c,
+  0xb0,0xc6,0x7e,0xcf,0x9e,0x83,0x9a,0x41,0x75,0x13,0xab,0xca,0xe3,0xaf,0x9e,0x8e,
+  0xa0,0x55,0x8c,0xae,0xbe,0x4e,0xcf,0x29,0xce,0x3d,0xc7,0xc1,0x5f,0x5a,0xa6,0x68,
+  0x04,0x36,0x99,0x73,0xc9,0x0f,0xff,0x20,0x7f,0x89,0x6e,0x0e,0x65,0x82,0x46,0x1e,
+  0x7f,0x65,0xaa,0xd2,0x38,0x5e,0x65,0xe4,0x4b,0xac,0x3d,0xa9,0xda,0xa7,0x22,0xfd,
+  0x14,0x0e,0x87,0xf8,0x3d,0x6d,0x69,0x88,0x14,0x18,0x37,0x42,0x03,0x5f,0x88,0xb0,
+  0x3e,0x6c,0x09,0x9f,0xe9,0x8c,0xb2,0x7e,0x2b,0xf9,0xb9,0x2a,0x9a,0xd4,0x2e,0xfc,
+  0x35,0x16,0xc1,0xfe,0xc1,0x3e,0x4c,0x9c,0xa0,0xc3,0xf3,0x8c,0x62,0x87,0x21,0x61,
+  0x6f,0x18,0x2f,0x21,0xfe,0x0a,0x8c,0xfe,0x97,0x49,0x18,0x80,0x45,0xaf,0xe3,0x78,
+  0x65,0x0d,0xbc,0xf4,0x5a,0xa0,0x3b,0x39,0x04,0xe8,0xfc,0xeb,0xde,0x8c,0x66,0xe4,
+  0xf1,0xd7,0x58,0xa4,0xc9,0xd4,0xf6,0x97,0x7f,0x84,0x43,0x19,0x3b,0x43,0x1f,0xf7,
+  0x5e,0x53,0x9b,0x06,0x02,0xa3,0xf8,0x26,0x5c,0xf3,0x36,0xf5,0x06,0x2e,0x78,0x26,
+  0xbd,0xe8,0x93,0x0c,0xe2,0xa5,0x2c,0x22,0x32,0xf1,0x27,0xfe,0xc0,0x27,0x8c,0xa6,
+  0x13,0x81,0x3c,0xfe,0x22,0x7e,0x19,0x08,0xf4,0x25,0xd1,0x08,0x35,0x0d,0x95,0x8e,
+  0x2f,0x45,0x23,0xd5,0x74,0xac,0x94,0x00,0xdd,0xef,0xb9,0xa0,0xc6,0x8e,0x9a,0x43,
+  0xbc,0x69,0xa0,0x64,0x54,0x50,0xcf,0x4d,0xd9,0x55,0x99,0xca,0x30,0x9c,0x36,0x16,
+  0xd0,0xc9,0xff,0xba,0x3c,0xff,0xd5,0x03,0xbb,0x2c,0x75,0x52,0xb0,0x5d,0xe1,0x01,
+  0xb5,0x8b,0xf8,0x2f,0xa3,0x66,0x48,0xed,0x60,0x41,0xe8,0xe0,0xbb,0x0c,0xad,0x43,
+  0x89,0x43,0x47,0x7b,0x2d,0x62,0x22,0x56,0x03,0x47,0x08,0x7f,0xfd,0xa1,0xec,0x9f,
+  0x4d,0x81,0xda,0x32,0xda,0xba,0x7c,0xfc,0x21,0x6e,0x5b,0x3c,0xb7,0x0c,0xfa,0xa2,
+  0xe4,0xcf,0x1b,0x68,0x00,0x22,0x32,0xdc,0xb6,0xac,0x9b,0x0d,0xb6,0xb9,0x2d,0x0d,
+  0x6b,0x07,0x8b,0x11,0x88,0x79,0x76,0x03,0x22,0xdf,0x48,0xd9,0x4a,0xd6,0xad,0x87,
+  0xfa,0x11,0x52,0x45,0xdd,0xf1,0x87,0xf8,0x1c,0x1b,0x76,0x59,0x6e,0x23,0x4d,0x81,
+  0x0a,0x20,0x9c,0x9c,0x0e,0xb8,0xdf,0x05,0xed,0x11,0xf4,0xa9,0xbb,0x11,0x9b,0xe3,
+  0xfe,0xb5,0x2e,0x8f,0xbf,0xf0,0x7d,0x86,0xb0,0xf3,0xce,0x97,0x3a,0xa0,0x06,0x8d,
+  0x1f,0xc3,0x07,0x10,0x6d,0x2f,0x4d,0x51,0xa4,0xca,0x60,0x4c,0x0c,0xa5,0x47,0xe2,
+  0x9d,0xf2,0x30,0x9b,0x80,0xc3,0x96,0x7f,0xaf,0xa2,0x4f,0x33,0x24,0xfe,0x3a,0x8a,
+  0x18,0xb6,0x29,0xe4,0xc6,0xcb,0x34,0x1d,0x16,0x5b,0xe8,0xae,0xdc,0x43,0x61,0x87,
+  0x71,0x11,0x88,0x78,0xd5,0xbe,0xe4,0xc5,0x11,0xb4,0x4e,0x8f,0x26,0x27,0xe1,0x77,
+  0xea,0x1d,0x7d,0xb5,0xe3,0x8a,0x8b,0xff,0x22,0xae,0xc4,0x9e,0xe6,0x8f,0x38,0x20,
+  0x0b,0x61,0x17,0x28,0x73,0xf4,0x61,0x23,0xca,0x4b,0xc8,0x05,0x1d,0xc0,0x96,0xcd,
+  0x22,0xd2,0x40,0x7e,0x1f,0x7c,0xd9,0x3c,0x88,0xbf,0x82,0x6e,0xfe,0x0b,0x47,0xc7,
+  0x54,0x6d,0xd8,0xe5,0xf4,0x0f,0x4e,0xab,0x8c,0xb2,0x06,0x92,0xb4,0xe3,0x53,0x4b,
+  0x07,0x2c,0x3a,0x5b,0xf2,0x29,0xfb,0x37,0x93,0xfa,0x67,0xc5,0xa8,0xf2,0x73,0xd8,
+  0x62,0x55,0x5e,0x08,0x1d,0x08,0xd6,0xe5,0xf1,0xd7,0x93,0x3c,0x6c,0xda,0xe3,0x85,
+  0xf3,0x4b,0xe2,0x2f,0x1a,0x14,0xa6,0x92,0x21,0x2f,0x71,0x10,0xf3,0x2b,0x20,0xf1,
+  0x72,0xa3,0x00,0xd7,0x86,0xa5,0x1a,0xac,0x21,0xcf,0x7f,0x1d,0x48,0x57,0xc7,0x85,
+  0xab,0x4f,0x07,0x65,0x02,0x64,0x1d,0x84,0x79,0x59,0xc4,0x71,0x5e,0xde,0xce,0xe7,
+  0xa5,0xb5,0x96,0xa2,0xd7,0xe0,0xe9,0xf4,0x6a,0x04,0x62,0x65,0x3f,0x32,0xf1,0x9e,
+  0x61,0xed,0xdb,0x89,0x1f,0x99,0x1b,0x3a,0x2a,0xde,0xc5,0x5d,0x38,0x9c,0xc7,0x5f,
+  0xe7,0x33,0x31,0x35,0xdc,0xa0,0x10,0xfe,0x0a,0xf7,0x97,0x10,0xfe,0xfa,0x50,0xaf,
+  0xb7,0x02,0x1e,0xa6,0x59,0x15,0x6a,0x8f,0x59,0x62,0x2c,0x1d,0x61,0x56,0xba,0x6a,
+  0xd8,0x9f,0x29,0x2f,0x6d,0xff,0xb5,0xb7,0x31,0x1b,0x68,0x50,0x9e,0x40,0x80,0x89,
+  0xe3,0x95,0xd6,0x5c,0xf1,0x87,0x57,0xbd,0xe8,0xb4,0x9f,0x97,0xe3,0x35,0x50,0x2a,
+  0x0c,0x63,0x51,0x5f,0xe0,0x02,0x2e,0x56,0x97,0x3d,0x8b,0x38,0x7a,0x71,0x17,0xe0,
+  0x23,0xbd,0xa9,0xbf,0x44,0x52,0xcf,0xd8,0xcf,0x7f,0x58,0xfa,0x53,0xf3,0x1a,0xad,
+  0x87,0xe7,0xdd,0xf1,0x87,0xb8,0x0f,0xa6,0xfd,0x3d,0x4a,0x58,0x9d,0x50,0x11,0x38,
+  0xf7,0x38,0xf3,0x3d,0xa3,0xbc,0x03,0xef,0xe0,0xef,0x5f,0x95,0xf2,0x64,0x29,0xa2,
+  0x75,0x00,0xd1,0xf1,0x29,0x20,0x98,0x1c,0x38,0xaa,0x94,0xc0,0x09,0x35,0xda,0x1f,
+  0x4e,0x57,0xce,0xf7,0x88,0x79,0x81,0xf8,0xcb,0xfb,0xbc,0xa7,0x84,0xab,0x0f,0x24,
+  0x66,0xc1,0x41,0xf3,0x36,0xcb,0x37,0xca,0x9e,0x06,0x71,0xb8,0x67,0xe2,0x76,0xf3,
+  0x3f,0x69,0xff,0x8a,0xa3,0xd1,0x8e,0x3f,0x39,0x87,0xbf,0x10,0xac,0xcd,0x6a,0xdb,
+  0x62,0x1a,0x03,0xd8,0xcf,0x51,0x39,0xee,0x16,0xfc,0x68,0xc6,0x81,0xf6,0xb5,0xd9,
+  0xe2,0xbb,0xd8,0x6c,0xe8,0x46,0x20,0x56,0x4c,0x81,0x88,0x82,0x67,0x6c,0x11,0x81,
+  0x88,0xf3,0x24,0xed,0xb5,0x87,0x57,0x0f,0xa9,0xeb,0x8b,0x68,0x2c,0xe6,0x65,0x6f,
+  0xb9,0x93,0x3d,0x42,0x38,0x37,0x8b,0xfd,0x9c,0x76,0xf1,0x5f,0xf1,0xf0,0x50,0x71,
+  0x24,0x48,0xcb,0xa0,0x18,0xee,0xcd,0xd0,0xcd,0xd6,0x4a,0x70,0x9d,0x5c,0x69,0x9c,
+  0xb9,0x05,0x77,0x4f,0xe0,0x3c,0x6c,0xcd,0x8c,0xc8,0xa3,0x45,0x8a,0xc0,0xa1,0x43,
+  0x30,0x5c,0x25,0xee,0x64,0xdb,0xf2,0xf8,0x0b,0xdf,0xf9,0x54,0x75,0x5a,0x09,0x61,
+  0x47,0xd5,0x51,0xfc,0x21,0x9d,0x5a,0x4b,0x22,0xcc,0xd8,0x05,0x0d,0x08,0xc4,0x92,
+  0x1f,0xf0,0x8f,0x77,0x34,0x38,0xd0,0xac,0x81,0x2e,0xd5,0x8b,0x60,0x45,0x7f,0x76,
+  0xc5,0xe1,0xc2,0xf8,0x43,0xc1,0x76,0x8d,0x7a,0x73,0xb4,0x57,0xcc,0xc6,0x5f,0xa6,
+  0xe4,0xbf,0x22,0x39,0x68,0x36,0xec,0x3e,0x72,0x0f,0x80,0xe7,0xee,0xa9,0xfc,0x97,
+  0xcd,0x0e,0x04,0x52,0x95,0x76,0x8b,0xae,0xac,0x86,0x71,0x53,0xc0,0xae,0xd5,0xc2,
+  0x4d,0x45,0x68,0x36,0xd7,0xb9,0xf9,0x5d,0x76,0x4c,0xef,0x22,0x0f,0xd6,0x85,0xbf,
+  0x0e,0xe9,0x39,0x96,0xaa,0xce,0x31,0x1a,0x24,0xdb,0x75,0xe8,0xd8,0x7c,0xd9,0x82,
+  0x6e,0xf3,0xea,0x50,0xca,0x37,0xc7,0x14,0xf8,0x6b,0x3b,0xc3,0x27,0x9b,0xc1,0xd6,
+  0xd0,0x76,0x5f,0x01,0xff,0x35,0xdf,0xbc,0x45,0xd2,0x67,0x41,0xc2,0x56,0x39,0xf8,
+  0xf6,0x20,0xfc,0x1c,0x2a,0x09,0x7f,0x7d,0x89,0x4e,0x33,0x5a,0x8b,0xf1,0x92,0x21,
+  0x2e,0x3d,0x8d,0xf7,0x3c,0xa5,0x06,0x5b,0x71,0xc6,0xe5,0xf1,0x17,0xec,0x0f,0x85,
+  0x6d,0xb6,0x0b,0xaa,0x96,0xdd,0x72,0x13,0x19,0x7a,0xc8,0xd4,0xee,0x4e,0x7c,0x29,
+  0xfd,0x3c,0xcc,0x23,0xe3,0xf5,0xec,0x4e,0x44,0x0a,0xc5,0x65,0x36,0xfe,0xc2,0xc9,
+  0xb0,0x92,0xb7,0x19,0x46,0x8b,0x7a,0xf3,0xa6,0x02,0xfe,0xab,0x41,0x0d,0x24,0x12,
+  0x59,0xef,0xd8,0xfc,0xa8,0x4e,0x81,0x64,0x80,0xbb,0x8c,0x2f,0x90,0x50,0xe2,0x9c,
+  0xdc,0x66,0x34,0xfe,0x32,0x81,0xdd,0x3b,0xbb,0xf8,0x51,0xbb,0x7b,0xa7,0x3f,0xaa,
+  0x9c,0x6b,0x3d,0xd3,0x1a,0x9d,0xe1,0x4f,0xb0,0x9f,0xe5,0xf9,0xaf,0x2b,0xa1,0xa6,
+  0xe5,0x5a,0x6a,0x89,0xe8,0xde,0x2f,0x04,0xb6,0x51,0x87,0x1b,0x0d,0x92,0xc9,0x72,
+  0x86,0x80,0xff,0x3b,0x05,0xb6,0x6d,0x75,0x28,0x2d,0xe2,0xbf,0xc6,0xf5,0xd8,0x14,
+  0xfe,0xeb,0x0a,0xc4,0x96,0xb8,0xd0,0xb1,0xfd,0xf1,0xe9,0xd4,0xf2,0x87,0x3c,0x70,
+  0x6e,0x42,0x8c,0xa6,0xcc,0x90,0xf8,0x62,0x50,0x59,0x88,0xa8,0x8d,0x22,0x12,0x6f,
+  0xc0,0x7f,0x39,0x46,0x33,0xc5,0x1f,0xd6,0xc0,0xad,0xb2,0xe5,0x59,0xb0,0x0f,0xa6,
+  0x6c,0x44,0x76,0x06,0x1a,0xb0,0x05,0x87,0x89,0x23,0xfe,0x0a,0xf1,0xe5,0xee,0xf8,
+  0x43,0x08,0x2f,0xc9,0x61,0x58,0x8a,0x36,0x74,0x0c,0x41,0x72,0xe5,0x2f,0x49,0x44,
+  0x86,0xf8,0x6b,0x85,0x5e,0xe6,0x65,0x6d,0x40,0xde,0x05,0xbb,0xdb,0xc5,0x7f,0xf1,
+  0xfb,0x5b,0xdd,0x68,0xbd,0x4a,0x84,0x9b,0xb2,0xad,0xa2,0xc5,0x7e,0x7f,0x0e,0x19,
+  0x61,0x81,0xc8,0x7c,0x4f,0x51,0x8b,0x8e,0xf7,0x10,0xc4,0x53,0xb7,0x17,0x39,0xf8,
+  0xeb,0x26,0xd1,0x2d,0x7f,0xb9,0x4a,0x80,0x23,0x57,0xff,0x2c,0xd1,0x7e,0x80,0xdd,
+  0x72,0x28,0x85,0xfd,0xb3,0x1d,0xbd,0x8b,0x43,0x66,0x4c,0x00,0xb1,0x5c,0x0c,0x27,
+  0x13,0x64,0xd9,0x0e,0x17,0xfe,0x9a,0x4a,0x07,0xa3,0xf1,0xbe,0x3c,0xa9,0xc0,0x96,
+  0x0e,0xf7,0x25,0x5d,0x19,0x32,0x5c,0x31,0xa5,0x38,0xa6,0xdb,0x94,0x37,0x5d,0xf1,
+  0x87,0x10,0xd3,0x6d,0x92,0xab,0xce,0x99,0x83,0x51,0xf0,0xb7,0xdb,0x86,0x7c,0xa3,
+  0x96,0x44,0xa7,0x89,0xc0,0x80,0x33,0x5e,0x9b,0xff,0xc2,0x1d,0x8d,0xe1,0xab,0xb5,
+  0xdc,0xc5,0x7f,0x19,0x44,0x72,0x89,0xa0,0xd0,0x20,0xc1,0x2e,0x69,0xa8,0x84,0xbf,
+  0x5e,0xe8,0x98,0x8f,0x2d,0x41,0x42,0x64,0xb7,0x71,0xf5,0x03,0xf6,0x86,0xb1,0x89,
+  0xf8,0xaf,0x6c,0x73,0x03,0x3c,0x01,0x0b,0xd2,0xda,0x10,0x73,0xc5,0x1f,0xee,0xe7,
+  0xf6,0xe9,0x2e,0xc5,0xd2,0x08,0xb4,0x45,0xc7,0x47,0x22,0xde,0x66,0x3f,0x37,0x1c,
+  0xda,0xcb,0xe8,0xc3,0x7b,0x5e,0x76,0xce,0x7b,0xc3,0x66,0x12,0xaa,0x06,0xf1,0x95,
+  0xc8,0xe3,0x2f,0x0f,0xae,0xc6,0xb8,0x66,0x12,0xd5,0xc2,0x2b,0xec,0x63,0xb1,0xb4,
+  0x91,0x15,0xab,0xf1,0x01,0x36,0x4f,0xb6,0xbc,0xc4,0x43,0x5c,0x8d,0xb3,0x41,0xb9,
+  0x3e,0xc7,0x8b,0x66,0xc2,0x06,0xb5,0xa2,0x15,0xd7,0xf0,0xbd,0x79,0xfe,0xeb,0x53,
+  0xde,0xf8,0x4e,0xb8,0x5e,0x99,0x0d,0x17,0x13,0x77,0x4c,0x06,0x1e,0x46,0xd8,0x75,
+  0x0d,0xb1,0x55,0x29,0xe1,0xaf,0x4b,0xfc,0x76,0x01,0xc4,0xac,0x4f,0xf9,0xed,0xf1,
+  0x95,0xeb,0x71,0xa1,0xfe,0x2d,0x41,0x33,0x55,0x29,0x85,0x5f,0xf0,0x3b,0xd2,0x81,
+  0x33,0xca,0xd7,0x0b,0xf8,0xaf,0x33,0x82,0xf6,0x3a,0x22,0xb7,0x1b,0xe1,0xcf,0xa3,
+  0x03,0x2c,0x82,0x73,0xec,0x80,0x99,0x8b,0x34,0x4c,0x14,0x76,0x28,0xb6,0x24,0xfe,
+  0xe7,0x23,0x04,0x55,0x97,0x94,0xa4,0x5c,0xfc,0x97,0x39,0x61,0x10,0xc8,0x62,0x31,
+  0xc4,0x56,0x77,0x65,0x05,0xfe,0x9a,0xd8,0x11,0x1b,0x12,0x6c,0xce,0x25,0x8a,0x3f,
+  0xec,0xf1,0x5c,0x35,0xae,0xf1,0xba,0x21,0xff,0x19,0xe5,0x6e,0xf8,0x24,0x65,0xe3,
+  0xaf,0x13,0x89,0x05,0xd9,0xf0,0x80,0x9b,0xff,0x3a,0x82,0xdd,0xb2,0x22,0xe2,0x9b,
+  0x25,0x4e,0x0b,0x25,0x3f,0x48,0xfb,0xce,0xba,0xc4,0x49,0x38,0x90,0x99,0xd7,0x17,
+  0xf8,0x8e,0x80,0x54,0x46,0xda,0x17,0xc7,0xdf,0xb0,0x21,0xdd,0x68,0x69,0x6b,0xd8,
+  0x9b,0xe6,0xa3,0xe9,0x45,0x5c,0x35,0x95,0xaf,0xe7,0xf0,0x97,0x77,0x91,0x29,0xba,
+  0x77,0x96,0x8a,0xee,0x81,0x55,0x80,0xbf,0xe0,0x05,0xb0,0x7b,0xfe,0x25,0x98,0x03,
+  0xea,0x5f,0x32,0x1d,0x9e,0xa1,0x4b,0x26,0x7b,0x1d,0xd7,0xb1,0x0a,0x0a,0xc5,0xc9,
+  0xf3,0x5f,0xce,0x71,0xb1,0x5f,0xcd,0x0d,0x37,0x39,0x9c,0xb7,0xd4,0x27,0x5e,0x35,
+  0x32,0x2d,0x7b,0xdf,0xf1,0x45,0x12,0x9f,0x40,0xf7,0x40,0x10,0x98,0xc1,0x54,0x96,
+  0xa4,0x3d,0x8e,0xe3,0xcc,0xe5,0x50,0xc5,0xd5,0xed,0xac,0xc5,0xc1,0x5f,0xd8,0xcf,
+  0xe8,0x09,0x07,0xa4,0x1b,0x2f,0xf8,0xa6,0x11,0x19,0x2d,0x76,0x00,0x3b,0x61,0x9c,
+  0x47,0x2d,0xed,0x80,0x72,0xcd,0xb8,0x98,0xad,0xb3,0x38,0x7a,0xef,0xb8,0xbf,0xd7,
+  0x58,0x62,0xa6,0x1c,0x67,0x51,0xcb,0xdf,0xa6,0xb8,0xf8,0xaf,0x8b,0xf4,0xa9,0x48,
+  0x0e,0x5b,0x2d,0xcd,0xf3,0x5f,0x26,0x05,0x19,0x06,0xf6,0xcb,0x4b,0x74,0xd2,0xbe,
+  0x53,0x5c,0xba,0x35,0xa3,0x9c,0x23,0x28,0x6d,0x8a,0x13,0x45,0xc3,0xc6,0x5f,0x70,
+  0x4d,0xff,0x16,0x7d,0xaa,0x91,0x0e,0x90,0xd1,0x99,0x5c,0x9a,0x77,0x38,0x11,0x08,
+  0x2e,0x92,0x40,0xe3,0x77,0x50,0x97,0x45,0xbf,0x25,0x02,0xa7,0xf1,0xd2,0x2a,0x4b,
+  0xb9,0x0d,0x7f,0xd9,0x82,0x34,0xae,0x87,0xa6,0x9b,0xff,0xaa,0xb4,0x56,0xe4,0xe1,
+  0x92,0xb2,0x36,0xcf,0x7f,0x65,0xa0,0xce,0x7a,0x42,0xa0,0x24,0x36,0x3f,0xee,0x3b,
+  0xc0,0x14,0xdc,0x80,0xf0,0xd2,0xbf,0x34,0x3f,0x87,0x48,0x6a,0x7e,0x3c,0xb4,0x83,
+  0x19,0x76,0xbc,0x9f,0xe0,0xbf,0x04,0xb5,0xb1,0xd6,0x0d,0xbb,0x6c,0xa3,0xc7,0x61,
+  0x3d,0x10,0x88,0xf5,0xcf,0xd7,0x13,0x55,0x71,0x71,0xce,0x9f,0x62,0xed,0xc6,0x0f,
+  0xd4,0xaa,0x16,0x75,0x2f,0xcb,0xe3,0x2f,0x7f,0xb7,0xb1,0x87,0x40,0x56,0x8e,0xb0,
+  0x16,0x71,0x56,0xc7,0x3b,0x11,0x41,0x9b,0x19,0x56,0x25,0xe7,0x69,0xa7,0x19,0x02,
+  0x84,0x66,0x40,0xe7,0x24,0xfd,0x5a,0x94,0xb5,0xf1,0xad,0x6a,0x18,0xd4,0xfa,0x02,
+  0xfe,0x2b,0xfe,0x79,0x1c,0x1d,0x8d,0xa6,0xc3,0x62,0x49,0x10,0x1f,0x91,0x07,0x14,
+  0x1f,0xc1,0x65,0xe3,0x05,0xf2,0x96,0x27,0xe1,0x2d,0x88,0x4e,0x9b,0xa5,0x2b,0x86,
+  0x79,0x82,0xdc,0xb9,0xa4,0xb6,0x93,0xef,0x30,0xea,0x00,0x9d,0x6d,0x37,0xff,0x55,
+  0x7f,0x97,0x4d,0x7b,0x51,0x1f,0x92,0x13,0x78,0xcd,0xb4,0xfb,0x79,0x4c,0x6f,0xb2,
+  0x4a,0x2f,0x21,0x50,0xfd,0xd4,0xb8,0xcb,0x5b,0x3a,0x5a,0x3e,0xca,0x27,0xe8,0xc4,
+  0xfe,0xd7,0x0a,0x25,0x47,0xdc,0x05,0x78,0xcf,0x5e,0x37,0xfe,0x6a,0x4a,0x94,0x58,
+  0x95,0xf8,0xf5,0x8d,0x6e,0xff,0xda,0x0b,0x74,0xd0,0x01,0x4d,0xbd,0xd3,0x71,0x7e,
+  0xb1,0xd3,0xbc,0x3b,0x5b,0x35,0x36,0x3d,0xe6,0x7d,0x9e,0x37,0x01,0x8e,0x8e,0x18,
+  0x2f,0xa3,0xb4,0x47,0xa9,0x81,0xd3,0xbc,0xc9,0xc4,0xe7,0x8c,0xe6,0xf0,0x97,0x8e,
+  0xbd,0x9a,0x52,0x7f,0x0e,0xd5,0xd9,0xce,0xfe,0xe0,0x49,0x75,0x63,0xd1,0x08,0x7f,
+  0xc9,0xb0,0x77,0x34,0x3b,0x5a,0x23,0x9c,0x3a,0xc4,0xd1,0xe7,0xdf,0x81,0xb3,0xa0,
+  0x93,0xd7,0x18,0x25,0x11,0x5f,0x18,0x92,0x0c,0x37,0x97,0x31,0xf4,0x99,0x5c,0xf1,
+  0x87,0x94,0xf6,0x55,0x06,0xbc,0x4d,0x37,0x00,0x5d,0xc7,0x93,0xde,0x6e,0xd5,0x66,
+  0xff,0x85,0xd3,0xae,0x0b,0xfe,0x0b,0x7b,0x55,0x67,0x1c,0x5b,0x6a,0x00,0xe7,0xce,
+  0x66,0x26,0x38,0x97,0x08,0xbb,0x90,0xc3,0x5f,0xf4,0x7d,0xb8,0x2f,0xd3,0x1c,0xe6,
+  0x9b,0xe4,0x91,0x20,0xf5,0xf3,0x5c,0x58,0xc1,0xcb,0x2c,0xa0,0x1d,0x14,0x9f,0x3c,
+  0x82,0xfb,0x57,0x4d,0xb3,0xda,0xc3,0x42,0x04,0xb7,0x67,0x16,0xd3,0x98,0x76,0x42,
+  0x69,0x1c,0x5f,0x89,0xd1,0x7c,0xfe,0xd7,0x84,0x1c,0x9d,0x2a,0x71,0xd0,0x21,0x38,
+  0xd6,0x6b,0x34,0x0b,0x0e,0x2b,0x23,0xfc,0x04,0x65,0xc3,0x75,0xe1,0xd4,0x1b,0xa7,
+  0xa3,0xfb,0xa3,0xda,0x5c,0xc4,0xd4,0x31,0x60,0x14,0xb2,0x7b,0x02,0x6a,0x42,0x81,
+  0x8c,0xc7,0xca,0xc7,0x1f,0xd2,0x74,0x28,0x01,0xed,0x38,0xfc,0xc1,0xbb,0x58,0xc4,
+  0x1f,0x7a,0xae,0xb1,0xa6,0xd6,0xc0,0x31,0x8a,0x98,0x12,0xd1,0xa1,0x5a,0x23,0x22,
+  0xb2,0xc6,0xa1,0xda,0x75,0xca,0xd5,0x65,0x38,0x04,0x86,0x88,0x29,0x6d,0xa2,0x15,
+  0x92,0xc6,0x34,0x87,0xbf,0x88,0xf6,0x2a,0xa1,0xef,0x73,0x82,0xf0,0x97,0x0c,0x18,
+  0x46,0x5f,0x34,0x33,0x7d,0x44,0x9d,0x98,0x16,0xb3,0xa6,0xa7,0x96,0x8e,0x78,0x8f,
+  0x79,0xa3,0x29,0xe2,0xe3,0xb6,0x9f,0xf0,0xc4,0xf4,0x2d,0xb8,0x38,0xb4,0x4f,0x40,
+  0x17,0xbd,0x3f,0xaf,0x17,0xc6,0x1f,0x9a,0x32,0x85,0xe1,0x7e,0x50,0x53,0xf8,0x9d,
+  0x5f,0x82,0xf9,0x2d,0x2a,0xcd,0x65,0xe1,0x81,0xd0,0x93,0x3b,0xe1,0xb3,0x96,0xfa,
+  0x63,0xf6,0x11,0x6c,0xa1,0x48,0xc2,0x03,0x89,0x6a,0x38,0xd2,0x1a,0x34,0xd5,0xcb,
+  0xec,0x82,0x3b,0xfe,0x30,0x6d,0x15,0xc3,0xcd,0x2a,0x2e,0x22,0x6b,0xc1,0xe1,0x41,
+  0x4c,0x0a,0x37,0xf5,0x88,0x28,0x53,0x1c,0x41,0x8a,0xb7,0xa1,0xf1,0x5a,0x82,0xc8,
+  0x2e,0x0c,0x9b,0x1a,0x37,0xd1,0x66,0xb7,0x86,0xfc,0x8d,0xb1,0x5c,0xfe,0x17,0x05,
+  0xbf,0x65,0x43,0x0f,0xb1,0xcf,0xc2,0x86,0xc4,0xda,0x6c,0x47,0x8b,0xc0,0x5f,0xb8,
+  0x66,0xae,0x67,0x3f,0xe2,0xdf,0x6f,0xab,0xce,0x16,0xdf,0x83,0x2d,0x8f,0xb7,0xcd,
+  0x09,0xa9,0xf7,0xb0,0xd7,0xf8,0x06,0x5e,0x1b,0xf2,0x21,0x76,0xd0,0x0f,0xb6,0xfd,
+  0x3d,0xa1,0xb6,0x91,0x3c,0xfe,0xba,0xc8,0x83,0x56,0x89,0x4f,0xf1,0x25,0x7a,0x21,
+  0x1c,0xf2,0x1b,0xca,0x49,0xff,0x44,0x59,0xf0,0x4f,0xfd,0xc0,0xfa,0xf8,0xa8,0x4e,
+  0x11,0x89,0xb8,0x25,0xf5,0xa6,0x22,0x59,0xff,0x0c,0xc4,0x3b,0x2f,0x43,0x63,0xa8,
+  0xb4,0x41,0x29,0x4d,0x5d,0x4c,0xd7,0x0f,0x23,0x6a,0x7b,0x2d,0x8f,0xbf,0x68,0x5a,
+  0xd5,0x9e,0x57,0x2e,0x99,0x08,0x10,0xfa,0xab,0x07,0x25,0xbf,0xdc,0x41,0x88,0xcc,
+  0x9c,0x90,0x11,0x89,0x47,0xd9,0x15,0x6f,0x53,0xbf,0x08,0x25,0x9d,0x80,0x46,0x28,
+  0x39,0xaf,0x8d,0x98,0xd7,0xf4,0xba,0xfe,0x42,0xfc,0x45,0x6b,0x66,0x49,0x46,0x0b,
+  0xe3,0xfb,0xd3,0x90,0x15,0x5c,0xf6,0xc4,0x3d,0x0d,0x10,0xa0,0xe3,0x88,0x33,0xe4,
+  0xfc,0x53,0x3f,0x8f,0x53,0xfe,0x57,0x0a,0x7b,0xbe,0x13,0xbf,0x21,0x01,0x79,0xfd,
+  0x04,0x08,0xb0,0x96,0xc7,0x5f,0x08,0xbb,0x6a,0x71,0x27,0x62,0x11,0xfd,0x51,0xa8,
+  0x05,0xd5,0x4c,0xe4,0x68,0x2f,0x3b,0xf4,0xa5,0xf5,0xbf,0x3c,0x0d,0xcf,0xd3,0xa5,
+  0x56,0x36,0xaa,0x6f,0x30,0x04,0xed,0xd5,0x08,0x22,0xee,0x3d,0xe2,0xc2,0x5f,0xd8,
+  0xcf,0xd5,0x69,0x5c,0x91,0x28,0xff,0xab,0xfa,0xdc,0xa6,0x35,0xc4,0x7f,0x71,0xc1,
+  0x7f,0x95,0x89,0xb0,0x43,0x11,0x91,0xf8,0x3c,0x5e,0xa2,0x0e,0xf7,0x6c,0x48,0xd6,
+  0xc6,0x37,0x3a,0xc9,0x62,0xd8,0xcf,0x86,0x3b,0xfe,0xb0,0x66,0x87,0x5a,0x5a,0xe6,
+  0xe1,0x08,0xb2,0x3e,0xeb,0xd3,0xc5,0x71,0x71,0xe8,0xcc,0x7f,0x93,0x9e,0x8c,0x40,
+  0x5b,0x9b,0xd1,0xc3,0x47,0x48,0x3e,0x8d,0x9d,0xec,0x4d,0x42,0x58,0x45,0x38,0xe0,
+  0xa7,0x18,0xf2,0x21,0xfc,0x3e,0x85,0xf1,0x87,0x29,0xff,0x3e,0x65,0x1e,0x1c,0x57,
+  0x63,0x99,0xd2,0xb4,0x47,0xc4,0x1f,0x22,0xec,0xd2,0x42,0x76,0x68,0x22,0x3a,0x54,
+  0x97,0x79,0x13,0xf7,0x0c,0x97,0x5f,0x46,0xbf,0xa9,0xb6,0x43,0x60,0xb4,0x4d,0xb0,
+  0x20,0x85,0x2f,0xff,0x94,0xf8,0xc3,0x9a,0x5e,0x9b,0xed,0x2a,0xb1,0x04,0xff,0x75,
+  0x90,0x26,0x5a,0xc6,0xe6,0xbf,0xca,0x85,0xef,0xe7,0xfd,0x19,0x4f,0x5a,0xe2,0xe6,
+  0x5a,0x4e,0x4c,0x8d,0x4c,0xea,0x9c,0x12,0x7f,0xe8,0xd7,0x35,0x2f,0x11,0x61,0x4b,
+  0xb6,0x48,0x2e,0x20,0xe8,0xf6,0x3c,0x99,0xf4,0x45,0x4b,0x77,0x08,0xda,0x2b,0x66,
+  0xa2,0xbb,0xf2,0x13,0x27,0xd5,0xa8,0xcf,0x85,0xbf,0xd0,0x5b,0x9e,0x29,0xd9,0x8a,
+  0x06,0xf3,0x04,0x7a,0xcb,0xfa,0x1b,0x39,0xfe,0xcb,0x53,0x63,0x9e,0x4e,0x35,0xa3,
+  0xa1,0xe0,0x7a,0xb8,0x9d,0xbd,0x07,0x1b,0x3d,0x7e,0x74,0xa4,0x77,0x55,0xb1,0x37,
+  0x88,0xdb,0x4a,0x15,0x65,0x0b,0xe3,0x0f,0x67,0xca,0xd8,0xc2,0x5a,0x07,0xb5,0xfd,
+  0x4c,0xf2,0x5f,0x3f,0x77,0x47,0x24,0x36,0x7c,0x8f,0x2e,0xe1,0x72,0xda,0x81,0xfb,
+  0x97,0xb9,0x51,0x30,0x62,0x65,0xaf,0x14,0xe2,0x2f,0xca,0xff,0xca,0x3e,0x1a,0xaa,
+  0xfe,0x22,0xa2,0xad,0x65,0xad,0x5b,0xeb,0xe7,0x2c,0x2f,0x6e,0x2d,0x7a,0x9d,0x52,
+  0x57,0x4c,0xad,0x15,0xfa,0x4d,0xc2,0x05,0x66,0x59,0xa2,0x3f,0xd1,0x66,0xdc,0x2f,
+  0x01,0xc2,0x56,0x19,0xa3,0xe8,0xce,0xff,0x32,0x62,0x6a,0x28,0x51,0x5e,0x41,0x44,
+  0xd8,0xcc,0x40,0x1f,0xf6,0x61,0x47,0x3c,0xa6,0x06,0x1c,0xe6,0x71,0x95,0xf5,0x79,
+  0xec,0xd5,0x69,0xb1,0xd9,0x9b,0x12,0xe5,0xe7,0xcc,0x01,0xe2,0x38,0xa6,0x55,0xfe,
+  0x6b,0x73,0x5f,0x6b,0x94,0x50,0xdb,0xc7,0xae,0xf8,0x43,0xc9,0x7f,0xad,0xe6,0xe8,
+  0xa2,0xb7,0x4c,0x1f,0x44,0xb4,0x85,0xf8,0x2b,0x1f,0x6d,0x58,0x8a,0x46,0xfb,0x15,
+  0x9b,0xae,0x42,0xd8,0xd5,0x24,0x89,0x95,0x2b,0xb0,0x98,0x3e,0xe5,0xca,0xff,0x22,
+  0x34,0xe1,0xb7,0xd3,0xbe,0xa4,0x41,0x68,0xab,0x94,0x8c,0x63,0x1e,0xbb,0xe5,0x1c,
+  0x9d,0x09,0x13,0xec,0x3a,0x06,0x8d,0x04,0xbb,0x16,0xc2,0xff,0x84,0x88,0xe9,0x6f,
+  0x55,0x5e,0x29,0xc4,0x5f,0x44,0x72,0xe1,0xab,0x65,0x40,0x89,0x13,0x7f,0xe8,0x8a,
+  0x36,0x44,0x14,0xd0,0xc1,0xe6,0xf3,0x6a,0x82,0x5d,0x1d,0x32,0x94,0x82,0x3b,0x5b,
+  0xdb,0xa9,0x02,0xfc,0x25,0xc3,0x0e,0x29,0xed,0x4b,0xb0,0x54,0x2e,0xfe,0x4b,0x66,
+  0x7b,0xe9,0x1b,0x99,0x61,0x16,0xcf,0xa4,0x96,0xa2,0x1a,0xa7,0x9f,0xab,0xc8,0x78,
+  0xcd,0xc6,0x5f,0x37,0xc9,0xf8,0x43,0xb5,0x20,0x08,0x9c,0x5a,0xdc,0x61,0xe1,0x5e,
+  0xb6,0xd1,0x3b,0xdf,0x2c,0xde,0xc6,0xe6,0x70,0x04,0xf2,0xf7,0x84,0xf4,0xe0,0x1e,
+  0xdc,0x10,0xe7,0x2e,0xa3,0xbc,0xbf,0xc2,0xf8,0xc3,0xb0,0xe8,0x1f,0x33,0x6a,0xaa,
+  0x33,0x3a,0x25,0x98,0xad,0x91,0xfc,0x57,0x97,0x19,0xde,0xa1,0x89,0xfe,0x59,0x57,
+  0xb2,0xdd,0x43,0x2d,0x8d,0xad,0x7e,0xfa,0x13,0x6f,0x08,0x6a,0x4c,0x19,0xb6,0xf1,
+  0x4e,0x0e,0x7f,0x69,0x43,0xb0,0x9f,0x35,0x3a,0xb1,0x85,0x8d,0xf4,0xf2,0x3b,0xc4,
+  0xe5,0x52,0x71,0x4f,0x8b,0xe6,0x64,0x84,0xd9,0x53,0xe6,0x70,0xfc,0x74,0xaa,0x10,
+  0x7f,0x45,0xc0,0xef,0xc4,0x1f,0xb6,0x3b,0x6c,0x57,0xfe,0x30,0x84,0x97,0x67,0x19,
+  0xa2,0x2d,0xbd,0xa6,0x43,0xf2,0x5f,0x7a,0x09,0x25,0xc6,0x0e,0xc0,0x03,0x14,0x9a,
+  0xe8,0xe2,0xbf,0x0e,0x3b,0x69,0x5f,0xc7,0x69,0xa3,0x17,0xf8,0xcb,0x1b,0xdc,0xa9,
+  0xe5,0x89,0xb0,0xfb,0x86,0x45,0x46,0xd8,0xe3,0x59,0x04,0x81,0x9b,0x18,0xde,0x93,
+  0x4d,0x20,0xfe,0xe2,0x95,0x5c,0xcd,0x32,0x9f,0xc7,0x94,0xcf,0x91,0xfb,0xd7,0x3c,
+  0x74,0x45,0xd8,0x93,0x2e,0x1e,0x3f,0xee,0x76,0x14,0xc9,0xf1,0x08,0xf6,0xaa,0x15,
+  0xb8,0x0f,0x12,0xff,0x55,0x1c,0x29,0xab,0xd1,0x93,0x70,0x1f,0xb9,0x22,0xae,0xf8,
+  0x43,0x5c,0x45,0x7f,0x41,0x69,0x5f,0x14,0x7f,0x48,0xbc,0xcc,0x97,0x4d,0xdc,0xd1,
+  0xfa,0xb4,0x6f,0xb1,0xb3,0xed,0x07,0xf5,0xea,0x01,0x0a,0x5d,0x68,0xd9,0x02,0x3b,
+  0x8f,0xe1,0x3d,0x27,0x29,0x2d,0xd7,0x9a,0xdf,0xca,0x66,0x1a,0x5b,0x9a,0xef,0xb5,
+  0x70,0x47,0x53,0x5d,0xf8,0x2b,0x13,0xa1,0x6c,0xaf,0xd9,0x84,0xad,0x86,0xfc,0xeb,
+  0x97,0x0a,0xfc,0x15,0x0f,0x3c,0x84,0xb0,0xeb,0x60,0x7a,0xf1,0xe8,0xbf,0x7c,0x57,
+  0xb9,0xba,0xe7,0x97,0x3c,0x32,0x8a,0x88,0xec,0x37,0x82,0xff,0x2a,0x59,0x83,0x37,
+  0xff,0x12,0xd7,0x67,0xff,0x3d,0x8a,0xaf,0x30,0xfe,0xb0,0x34,0xcf,0x95,0xa0,0x03,
+  0x3c,0xe1,0x79,0xc4,0xe6,0xbf,0x5a,0x62,0xaf,0x4d,0x77,0x2e,0xa1,0x7b,0x30,0x04,
+  0x22,0x35,0x2c,0xa5,0x88,0xd3,0xc2,0x7e,0x5a,0xc7,0x98,0xf4,0x37,0x28,0xfe,0xb0,
+  0x63,0x01,0xc1,0xae,0x98,0x71,0x9a,0x47,0xdf,0x2b,0xb5,0xf1,0x57,0x9c,0x80,0x18,
+  0xc2,0xae,0x5b,0xb3,0x7f,0x4e,0x2d,0xa7,0xdb,0xeb,0x86,0x4a,0xc7,0x3d,0x0d,0x70,
+  0x3a,0x75,0xfb,0x10,0xe2,0xaf,0xb9,0xb8,0xe0,0x2d,0x18,0xda,0xf2,0x39,0x45,0xcf,
+  0xe3,0xaf,0xee,0x74,0x45,0x7f,0xf5,0xed,0x3e,0xbf,0xb1,0x81,0x92,0xe9,0x1c,0xfc,
+  0xa5,0x52,0x6f,0x48,0x00,0x95,0x7c,0x1a,0x51,0x6d,0x90,0x5a,0xfc,0xb0,0x61,0x17,
+  0x42,0xd7,0x33,0xbe,0x28,0x74,0xa6,0xc2,0x59,0x6d,0xa6,0x6f,0xbe,0x2b,0xff,0xcb,
+  0x30,0x68,0x98,0x56,0x22,0x26,0xfa,0x71,0xbf,0x4f,0xc6,0x31,0xe2,0xfc,0xca,0x45,
+  0xdd,0x7f,0x13,0x8d,0x2d,0x74,0xe9,0xc1,0x84,0x1e,0xdf,0x60,0x54,0x1e,0xd7,0xe2,
+  0xb8,0x45,0x3e,0x0a,0x73,0x7a,0x3b,0x5b,0x1d,0xfc,0x15,0x9f,0x71,0x52,0x27,0xf2,
+  0x45,0x5d,0xc8,0x56,0x41,0xb2,0x75,0x6e,0x5f,0xc7,0xc2,0xe6,0x11,0x19,0xc8,0x71,
+  0x27,0x3b,0xd5,0xda,0xdd,0x1a,0x3e,0xb3,0x74,0x61,0x62,0xb3,0x17,0x51,0xb6,0xe5,
+  0xab,0xc7,0xe9,0x89,0x9e,0xe7,0x28,0x4e,0xab,0x30,0x85,0x4e,0x59,0xb8,0x1e,0xce,
+  0x94,0xf3,0x3d,0xfd,0x19,0xf2,0x9a,0x16,0x58,0xea,0x8b,0xec,0x11,0x38,0xe1,0x59,
+  0x74,0x1e,0x7d,0x63,0xc2,0x3b,0x35,0xaf,0x87,0x2f,0x11,0x51,0x68,0x35,0x8d,0x4e,
+  0x9f,0xf4,0x4c,0xb2,0x13,0x7c,0xd1,0xaf,0x7c,0x7b,0x95,0x30,0x3b,0xe1,0xe9,0xca,
+  0x22,0xb6,0x0a,0xe3,0xfb,0x5c,0x89,0x1d,0xbe,0xd4,0xfe,0x5d,0xed,0x60,0x0f,0x53,
+  0x54,0xd9,0x6c,0x5c,0x54,0x1b,0xac,0x5b,0x23,0xc9,0x11,0xcf,0x04,0x65,0x53,0xe2,
+  0x30,0x55,0xe4,0x03,0x47,0xf5,0x06,0x89,0xa0,0x45,0x4b,0x5a,0x1b,0x86,0x31,0xb3,
+  0x81,0x02,0x11,0x5d,0xf9,0x5f,0x9f,0x50,0x48,0xe1,0xa8,0x46,0x41,0x86,0x64,0x2c,
+  0x6d,0xf4,0xa2,0xd3,0xde,0x1f,0x18,0x4d,0x0a,0x82,0xa6,0x17,0xe1,0x00,0x7d,0xc3,
+  0xfd,0x2f,0xfb,0x75,0x74,0xe3,0x2f,0x82,0xd2,0x57,0x32,0xa2,0x44,0xcd,0xd3,0x70,
+  0x93,0xe5,0xff,0x4b,0x77,0xfc,0xe1,0x4b,0x22,0x7e,0x2c,0xb8,0x0f,0x3a,0x3d,0x32,
+  0xfe,0x90,0x9c,0x64,0x53,0xf0,0x5f,0x2f,0xe1,0xdb,0x4b,0x11,0x53,0x7a,0x37,0x43,
+  0x5f,0x6b,0x07,0xf1,0x29,0xe4,0x99,0xef,0x49,0xe0,0xe2,0x39,0x38,0x5f,0x72,0x1c,
+  0xae,0xf8,0xc3,0x20,0x7a,0x82,0xf7,0x85,0xe1,0x87,0x38,0x65,0x04,0xff,0xa5,0x79,
+  0x28,0xcf,0xa5,0x6c,0xc4,0x5b,0x40,0x84,0x91,0x1f,0x6e,0x52,0x68,0xe2,0x3c,0x5c,
+  0x7f,0x8c,0x0e,0xc9,0x83,0xc4,0xe5,0xfc,0x12,0xf1,0x87,0x2d,0x34,0xee,0x9f,0xf5,
+  0xfb,0x9e,0x84,0xac,0xe4,0xbf,0x92,0x6a,0x78,0x20,0x17,0x15,0x2c,0x4e,0xfe,0x8f,
+  0x40,0x9c,0xf8,0x2f,0xbf,0xde,0xad,0xce,0xb7,0x5a,0x18,0x83,0x3e,0x6e,0xc4,0x07,
+  0xd4,0xc8,0xb6,0x3e,0x09,0xbf,0x28,0xff,0xeb,0x53,0x33,0x6a,0x95,0x1c,0x98,0x5e,
+  0x6d,0xbe,0x05,0xb7,0x0f,0x3c,0x4e,0xc0,0xf9,0x84,0x11,0x6b,0x11,0x3e,0x76,0x13,
+  0xfa,0x75,0xa5,0xa3,0xca,0x59,0xec,0xe7,0xe8,0x99,0xa7,0x33,0xca,0x3c,0x73,0xc2,
+  0x38,0x7c,0xa6,0xba,0x5d,0x33,0x32,0xc7,0x42,0x87,0x07,0xfc,0xff,0xa4,0x98,0x4c,
+  0xb7,0xf1,0x97,0x47,0xa0,0xda,0x0b,0xc9,0xa3,0xfc,0x13,0x68,0x3a,0x79,0x9a,0x82,
+  0xd6,0xb0,0xe5,0x17,0x02,0xde,0xe6,0x00,0xef,0xa7,0xde,0xa6,0xd3,0x76,0xe4,0x67,
+  0xdd,0xa9,0xe9,0xaf,0x24,0x47,0xf9,0x64,0xe8,0x91,0x57,0x6a,0x2f,0x24,0x73,0xf8,
+  0xeb,0x32,0x9c,0x4c,0xdd,0x19,0x0f,0x5f,0x50,0x2e,0xa5,0x9d,0xf8,0x5e,0x9b,0x5f,
+  0xa6,0x89,0x56,0xd0,0x42,0x6c,0xd7,0x30,0xdc,0x25,0xe0,0x80,0x89,0x2d,0x03,0xfe,
+  0xd1,0x05,0x76,0xfc,0xa1,0xa5,0x0f,0x1b,0x38,0x77,0x98,0x7a,0x94,0x7d,0xf2,0x19,
+  0x19,0x5b,0xa8,0xfc,0x4c,0x92,0x5c,0x94,0xff,0x75,0xa4,0x5d,0xb4,0x7c,0x2c,0x5b,
+  0xd2,0xbe,0x1a,0x78,0x8e,0x07,0xd3,0x76,0xcf,0xd7,0xf6,0x23,0x80,0x8a,0xc8,0xf7,
+  0x79,0x60,0xda,0x48,0x19,0xf6,0x7c,0x4b,0xcb,0xc2,0xb2,0xfe,0xc2,0x78,0xec,0x4e,
+  0xdb,0xe8,0xcd,0x87,0x61,0x1b,0x38,0x3a,0x7b,0x21,0x44,0xb0,0x6b,0x33,0x27,0xf2,
+  0x05,0x9f,0x93,0xe7,0xbf,0xcc,0x4e,0x78,0x96,0xab,0x99,0xe6,0x11,0xc3,0x8e,0x9d,
+  0xdb,0x77,0x1d,0x00,0x17,0x18,0xcd,0xc2,0x15,0x5b,0xc4,0xa6,0x72,0xba,0xc4,0xef,
+  0x92,0x64,0x6b,0x4e,0x7f,0xe3,0x38,0xfa,0xac,0xf5,0xc4,0x37,0x7d,0xd4,0xac,0xb1,
+  0x1c,0xf9,0x5b,0x43,0x87,0x0f,0xce,0xf2,0xe5,0x84,0x58,0x8f,0x2a,0xad,0xea,0x10,
+  0xdc,0xb5,0x84,0xa0,0x34,0xff,0x8e,0x5c,0xfd,0x72,0xf1,0x87,0x87,0xf1,0x9d,0x5f,
+  0xc4,0x03,0x07,0xec,0xf0,0x4e,0x37,0x70,0x76,0x1d,0x50,0xb8,0x0d,0xbe,0xe2,0x12,
+  0x25,0x82,0xf5,0xc7,0x2c,0x77,0xfc,0xe1,0x4f,0xd8,0x30,0x3f,0x4c,0x91,0x69,0xf3,
+  0xe0,0xc4,0x14,0x32,0x7a,0xaa,0xb1,0x5f,0xca,0x38,0xd0,0x97,0x7f,0x9f,0x5a,0xc8,
+  0xf9,0xb7,0xf9,0xaf,0x33,0x9e,0x1a,0xbd,0x93,0x3f,0x9b,0x2e,0x91,0x2e,0xb1,0x9d,
+  0x17,0x79,0xc4,0x23,0xfb,0x47,0xff,0x50,0x71,0x77,0x54,0x8f,0x9c,0x7a,0x6d,0xea,
+  0xf3,0x65,0x62,0xbc,0x5e,0x67,0x57,0x99,0xcd,0x7f,0x0d,0x4f,0x6b,0x81,0x34,0xec,
+  0x45,0x24,0x75,0xb3,0xbf,0xa8,0xdb,0x73,0xa3,0xf8,0xf9,0xbc,0xb1,0x57,0x68,0x35,
+  0x54,0x49,0x12,0x19,0xc7,0xab,0x17,0x57,0x3f,0x3b,0xff,0x2b,0xe3,0xb9,0x19,0x36,
+  0xa4,0x6e,0x33,0x8a,0x29,0xb9,0xf8,0x99,0x5c,0xda,0x57,0xda,0x36,0x44,0xcb,0x43,
+  0x8c,0x42,0x13,0xab,0x87,0xb5,0x10,0xc1,0x8a,0x74,0x6d,0x3a,0xf4,0xd7,0xcd,0x82,
+  0x2c,0x1b,0x62,0xeb,0x71,0x05,0xb0,0xf1,0x57,0x18,0xb2,0xa9,0x1e,0xe2,0x26,0x10,
+  0x88,0xe9,0x8d,0xf8,0xd7,0x89,0x08,0x4b,0x37,0x8e,0x88,0x40,0xc4,0x8b,0x99,0x46,
+  0x6b,0x55,0xc3,0xd2,0x93,0xea,0x45,0x92,0xe6,0x30,0x34,0xc3,0xb4,0xd2,0xe8,0x8f,
+  0x89,0x4b,0xd0,0x68,0xa1,0x91,0xe7,0xbf,0xd8,0x84,0xd1,0x24,0x52,0xf9,0xcc,0xdf,
+  0x79,0xb1,0x33,0xcf,0xe7,0x47,0x67,0x44,0x1a,0xe7,0xc5,0xb4,0x9a,0xdd,0x8f,0xf3,
+  0x62,0x84,0x5f,0xd3,0x1f,0x4e,0x0b,0xea,0x19,0xfb,0xf9,0x65,0xfc,0x54,0x0e,0x7f,
+  0x0d,0xb3,0x01,0x6f,0x24,0xcf,0x57,0x96,0xfe,0x2f,0xc6,0xab,0x5e,0xd9,0x45,0xbc,
+  0x0c,0xa5,0x86,0x85,0x55,0x3a,0xbd,0xc4,0x4f,0xd9,0xf9,0x5f,0x03,0x37,0xf5,0xc0,
+  0xef,0xe0,0x0e,0xae,0x3a,0xd9,0x04,0x9a,0xfb,0xdc,0x6f,0x5a,0xee,0x00,0xd0,0x36,
+  0x28,0xbf,0xfb,0x1b,0x1c,0x57,0xc8,0x59,0xde,0x83,0xf0,0x0f,0x27,0xf1,0x53,0x51,
+  0xe7,0x9c,0xed,0x47,0x46,0x3b,0xdf,0x1d,0x6f,0x59,0x1f,0x94,0xe9,0x75,0x9b,0x6c,
+  0xc2,0xd1,0xee,0x70,0xee,0xee,0xf0,0x31,0xd6,0x45,0x44,0x58,0x5c,0x5b,0x97,0x90,
+  0x1c,0x99,0x7a,0xa7,0x2f,0x87,0xbf,0x3e,0xf6,0x3e,0x09,0x73,0xdb,0x11,0xc7,0xbd,
+  0x6a,0xfe,0x27,0xc3,0x1d,0x29,0xb2,0x8d,0x85,0x32,0xb7,0x82,0x6b,0xf5,0xc1,0x6a,
+  0xe8,0xd6,0x29,0xa5,0x22,0x87,0xbf,0x66,0xec,0x85,0x3e,0x88,0xf2,0x2f,0x3f,0x8b,
+  0x6f,0x38,0xa1,0xad,0x52,0x27,0x10,0x31,0x50,0x60,0xd8,0xa9,0x73,0x7b,0xe1,0x1d,
+  0x7c,0xce,0xaa,0xb4,0x52,0x6f,0xd0,0xa5,0x95,0x05,0xf8,0x4b,0x6c,0x0b,0xe8,0xc5,
+  0xb5,0x3b,0x5e,0x9c,0x2b,0xaf,0x84,0xc5,0x3c,0x5b,0xf2,0x0e,0x5e,0xd2,0x8e,0x48,
+  0x6c,0x47,0x07,0x6f,0xcc,0x23,0x80,0x58,0x0e,0x7f,0xed,0xe1,0x14,0x94,0x85,0x4e,
+  0xfb,0x7b,0x66,0x2e,0xda,0x70,0xdc,0x01,0x62,0xd7,0x53,0x00,0x14,0x79,0xe5,0x27,
+  0xde,0x41,0x30,0x62,0x37,0x69,0xb9,0xfc,0xaf,0xaf,0xc1,0x46,0x33,0x68,0xce,0x4f,
+  0x21,0xb6,0x42,0xb7,0x79,0x89,0x9b,0xff,0x42,0xc3,0x4b,0x8c,0x46,0xd1,0x90,0x0c,
+  0x3b,0xfc,0x9e,0xcd,0x91,0xb5,0x7c,0xdf,0x47,0x7e,0x6f,0x4d,0x6b,0x68,0x87,0x3b,
+  0xff,0xeb,0x71,0xcf,0x4f,0x96,0xa8,0x85,0x51,0x8b,0x6e,0x63,0x85,0xc0,0x71,0x92,
+  0x3e,0x23,0x44,0xb6,0x9b,0x5c,0xf4,0x3d,0x08,0xe8,0xc2,0xcd,0x14,0x87,0x96,0xc7,
+  0x5f,0x8f,0xf3,0x0a,0xd3,0x87,0xd8,0x6a,0xa7,0x8b,0x8e,0x09,0x99,0x6e,0xa6,0x46,
+  0x1a,0xb7,0x94,0xb1,0xd7,0xf9,0xcf,0x8d,0xbf,0x6b,0xf1,0x95,0xb1,0x76,0xbe,0xd5,
+  0x1b,0x6e,0x51,0xcb,0x5c,0xf1,0x87,0x14,0x9b,0xe1,0xd9,0x9c,0x08,0x66,0x79,0x41,
+  0xda,0x8e,0xcb,0x60,0x32,0x6d,0x47,0x93,0xfc,0xd7,0x02,0x28,0x7d,0x54,0xd9,0x89,
+  0x40,0x6c,0xf6,0x0c,0x7f,0x42,0x71,0xf2,0xbf,0xfe,0xe4,0xd2,0xb3,0xe3,0xa1,0xa6,
+  0xe5,0x81,0xc1,0x4a,0x19,0x5b,0xb8,0xca,0x0e,0x44,0xcc,0x07,0xc8,0xe5,0xfb,0x79,
+  0xab,0xd2,0x8f,0xf8,0xab,0x61,0x59,0xf5,0xaf,0x94,0x07,0xcd,0x2b,0x21,0xf4,0x49,
+  0xb6,0xe5,0xf9,0xaf,0x3f,0xc0,0xab,0xe6,0x7e,0x73,0xed,0x0f,0x9e,0xfc,0x8d,0x7e,
+  0xcc,0x3d,0x3a,0x5f,0xbc,0x7e,0xbc,0xce,0x20,0x4c,0x7e,0x3f,0x1d,0xfb,0xba,0x2d,
+  0xd6,0x21,0xf9,0x2f,0x8f,0x8d,0xbf,0x3e,0x80,0x8e,0xf6,0x60,0x48,0x6d,0x67,0xef,
+  0x9b,0x84,0xad,0x02,0x79,0x22,0x4c,0xe4,0x7f,0x91,0x51,0xe6,0xb4,0xf8,0x0c,0xbc,
+  0x87,0xf8,0x2f,0x74,0xf5,0xf7,0xc2,0x7c,0xc2,0x5f,0xa5,0xf6,0xbc,0x98,0xd6,0xcf,
+  0xdb,0x8c,0x74,0x33,0x7a,0xe6,0x43,0xd0,0xe6,0xee,0x55,0x1f,0x1a,0xde,0xfd,0x5e,
+  0x57,0x8b,0x76,0x3b,0xbe,0x36,0x3b,0x6f,0x12,0xfc,0xd7,0x90,0x4c,0x8c,0xd5,0x59,
+  0xd9,0xb4,0x88,0x83,0xbf,0xda,0x9c,0x94,0xc0,0x8d,0x12,0x76,0xfd,0x67,0x2f,0x00,
+  0xd1,0x5e,0x6c,0x23,0xf1,0x5f,0xdb,0xb0,0xe5,0x5f,0x8d,0x90,0xe9,0x8a,0x3f,0x9c,
+  0xf1,0x63,0x13,0x41,0xa8,0x19,0x7e,0xaa,0xbc,0x5f,0x04,0xd6,0x6a,0x4e,0x6f,0xe4,
+  0xa2,0x04,0x65,0xcf,0xe3,0x73,0x6c,0xe9,0x12,0x9b,0x3a,0x3c,0x26,0xf3,0x19,0x43,
+  0x72,0xbf,0x58,0x03,0x3f,0x41,0x10,0xf3,0xe2,0xb2,0x29,0x2f,0x7f,0xc1,0x30,0xa5,
+  0x40,0xce,0x94,0x40,0x2a,0xe9,0x18,0xce,0x24,0xd2,0xb5,0x37,0x9d,0xfc,0xaf,0x9d,
+  0x6c,0x60,0xa6,0x50,0xd2,0xa0,0x20,0x8d,0x1b,0xbf,0x3f,0x6e,0xc3,0x96,0xdd,0x10,
+  0xfc,0x97,0xba,0x92,0xe7,0xf2,0xbf,0xbc,0x21,0x78,0xc2,0xb4,0xd9,0xae,0x37,0x73,
+  0x61,0x87,0x5e,0x57,0xfe,0x57,0xde,0x18,0x62,0x2d,0xb0,0xc9,0x1b,0x24,0xd8,0x15,
+  0xc2,0x9b,0x6f,0xcb,0x84,0x10,0x7f,0x49,0x7f,0x2c,0x34,0x6d,0x2d,0x4b,0xb6,0xbf,
+  0x63,0xe5,0x62,0xa4,0xff,0x57,0xfb,0xd7,0x42,0x26,0x35,0x3a,0xe6,0x37,0x88,0x84,
+  0x17,0x81,0x02,0x7c,0x4e,0xfc,0xc6,0x0c,0xf4,0xf0,0xff,0x76,0x89,0x08,0xf9,0xfe,
+  0xfe,0x94,0xd5,0xf8,0x46,0x86,0x38,0xce,0x7a,0x98,0x6d,0xb6,0xbe,0x5f,0xf1,0xf7,
+  0x29,0xb5,0xd5,0xc1,0x5f,0x21,0x35,0x06,0xa7,0xf8,0xfe,0x6c,0x98,0xd8,0xae,0x29,
+  0xf9,0x5f,0xd3,0x85,0x71,0x2e,0xd7,0xa2,0xb5,0xd0,0xf9,0x21,0x5f,0x97,0xf5,0x8d,
+  0x69,0x3f,0x32,0x4f,0xf3,0x48,0xd6,0x3b,0xa6,0xd8,0xbf,0x8b,0xf0,0xd7,0x18,0xbc,
+  0x68,0xfe,0xaf,0xdc,0x83,0xcc,0xd2,0x11,0xef,0x04,0xb9,0x34,0x5c,0x59,0x8b,0xdb,
+  0xcd,0x6c,0xab,0x24,0xbd,0x74,0x2d,0x9f,0xe0,0xa4,0xc8,0xe1,0xc4,0x1f,0x0a,0xfd,
+  0x8d,0xd4,0x82,0x73,0xfe,0xf1,0x4a,0x04,0x59,0xfc,0xae,0xa1,0x42,0xff,0x50,0x18,
+  0xa3,0xb6,0x71,0xeb,0x38,0x1a,0x9f,0xf2,0xef,0x0c,0xf9,0x07,0xd0,0xd3,0x3b,0xdd,
+  0xd1,0x94,0x5d,0xe9,0x8a,0x3f,0xdc,0x1e,0x3f,0x92,0x5e,0x64,0xaa,0xeb,0x65,0x6c,
+  0x46,0x56,0x74,0x42,0x37,0xd4,0x8b,0xf8,0x43,0x0b,0xbb,0xa5,0x5f,0xc4,0x1f,0x7e,
+  0x9f,0x87,0x87,0x65,0x47,0x19,0x15,0xc3,0xaa,0x49,0x71,0xef,0x50,0x6d,0xfa,0xbe,
+  0xc4,0x5c,0xf1,0x87,0x07,0x23,0x3b,0x5f,0x99,0xf7,0x80,0x0c,0xad,0x1f,0xf8,0xcf,
+  0xfb,0x79,0x60,0x45,0x3c,0x78,0x16,0x5e,0xf2,0xdc,0x26,0xb8,0x36,0x02,0xc5,0x5c,
+  0xfd,0x26,0xb3,0x72,0xf8,0xcb,0x7b,0xa4,0x75,0x6e,0x6b,0x31,0xee,0x5f,0xee,0x71,
+  0x0f,0xd9,0x7e,0x26,0xb3,0x5b,0x04,0xdd,0x09,0xec,0x74,0x4b,0xf7,0xa0,0x71,0xc9,
+  0x17,0x62,0xa7,0x21,0xc9,0x6b,0x00,0x27,0x63,0x2e,0xfe,0x70,0x33,0x9d,0x7e,0x5f,
+  0xfa,0x46,0xcf,0xd2,0x53,0xc1,0x13,0x14,0xbb,0x72,0xe3,0x0e,0x27,0x3f,0x4a,0x30,
+  0x2c,0x13,0x66,0xc3,0x60,0xe9,0x8e,0x27,0x7f,0x87,0x60,0x16,0xf7,0x0b,0xae,0x7c,
+  0xe0,0xec,0xcb,0x38,0x65,0x54,0xf4,0x18,0xf7,0xa3,0x2f,0x41,0x7e,0x82,0xfc,0xb8,
+  0x32,0xf5,0x81,0x6f,0xd9,0x06,0x9f,0x30,0x62,0x03,0xf3,0x52,0x76,0xbe,0x43,0x20,
+  0xe5,0x8a,0x3f,0x84,0xb7,0xa1,0x7b,0x20,0x3c,0x5a,0x7e,0xc9,0x43,0xdc,0xd6,0x96,
+  0x1b,0xbb,0x97,0x94,0xde,0xb2,0xea,0x57,0xca,0x2c,0xf8,0x25,0xdc,0x6e,0xe1,0x32,
+  0xd8,0x68,0xac,0xc2,0xf5,0x70,0xf3,0x39,0x05,0xbe,0x64,0xef,0x5f,0x6b,0xe9,0x64,
+  0xe9,0x1c,0x7a,0xc2,0x43,0xcd,0x6f,0xb9,0xdd,0xe6,0x5b,0x9d,0x9f,0x23,0x5a,0x3e,
+  0x94,0x74,0x95,0x9d,0xdb,0xa5,0x36,0xef,0xa3,0x93,0x8a,0x39,0xea,0x76,0x27,0x7e,
+  0x9e,0x7b,0xd6,0xda,0xb0,0xab,0x48,0x86,0x14,0x16,0xf2,0x5f,0x85,0x86,0xe1,0x3c,
+  0xa7,0xc3,0xce,0x08,0x2b,0xe6,0x79,0xfc,0x55,0xe5,0x4d,0xfa,0xd3,0x96,0x16,0x9d,
+  0x2b,0xe6,0xa9,0x80,0x5d,0x22,0x83,0x8f,0x88,0xcb,0x76,0x72,0x2a,0x44,0x06,0x5f,
+  0xb7,0x51,0x65,0x69,0x2a,0x25,0x82,0xdd,0x94,0x3e,0x16,0x02,0xb6,0x2f,0xf8,0x1c,
+  0xae,0xab,0xc5,0xba,0xaf,0x59,0xbe,0x3d,0x50,0xbc,0x16,0xde,0xd2,0xa3,0x56,0x35,
+  0x9d,0x39,0xe0,0xf7,0xc9,0xc7,0xe5,0x6a,0xc2,0x30,0x05,0x71,0x89,0x46,0x48,0xcc,
+  0x8b,0x30,0x88,0x1c,0xb1,0x54,0xf9,0x2c,0xfe,0x21,0x64,0x78,0x75,0xda,0x85,0xbf,
+  0x60,0xc2,0xd3,0x44,0xe3,0xf5,0xba,0x2e,0x73,0x4f,0x88,0x67,0x54,0x9b,0xfa,0xb0,
+  0x7b,0x7f,0x0a,0x42,0x7f,0xe3,0x82,0x32,0xe9,0xf9,0x90,0xc5,0x5e,0x13,0xe7,0xf3,
+  0xd7,0x8c,0xc6,0xfe,0x80,0x85,0x2f,0xed,0xef,0x3c,0x4d,0x50,0x3a,0x58,0x59,0xa8,
+  0xbf,0x61,0xd9,0x61,0xbd,0x31,0x1b,0x76,0x59,0x75,0x64,0x3c,0x82,0x5e,0xca,0x82,
+  0x6c,0xc9,0x76,0x11,0x76,0x18,0x35,0xf7,0x49,0xe9,0x9b,0x26,0xc3,0x9f,0x56,0x1e,
+  0x61,0x27,0x48,0xb5,0xa3,0xc7,0xad,0xbf,0x71,0x04,0x76,0x71,0xa1,0xb6,0x81,0x20,
+  0x0b,0x9d,0xf6,0xf2,0x91,0x74,0xb7,0x31,0x9f,0xbc,0xf7,0x1a,0x11,0x9a,0xa8,0x95,
+  0x11,0xfe,0x82,0x60,0x5c,0x15,0xf1,0x87,0xac,0xc6,0x28,0xd9,0x8b,0xfd,0x9c,0xf4,
+  0xc6,0xb2,0x38,0x04,0x2e,0xfd,0x43,0xd2,0x8f,0x6a,0xa1,0xe4,0x11,0xa2,0x17,0x35,
+  0x11,0xde,0x69,0x50,0xa6,0x09,0x23,0xa9,0x3d,0xa3,0x97,0x54,0x05,0xe8,0xcc,0x8a,
+  0xdb,0x31,0x03,0xf3,0x89,0x58,0x59,0x49,0x07,0x14,0x04,0xcd,0x5c,0xfa,0x1b,0x87,
+  0x88,0x73,0x71,0xa3,0x2d,0x34,0x9e,0x25,0x23,0x8c,0xcf,0x09,0x5a,0x5a,0x7d,0x42,
+  0x68,0x74,0xa4,0xd5,0x88,0xe4,0x58,0xf5,0xcf,0xfd,0x13,0x0b,0xeb,0x9d,0xde,0x9f,
+  0xd1,0xd4,0x73,0xe9,0x6f,0x8c,0xb9,0xe3,0x0f,0xed,0x84,0xd6,0xa8,0x24,0xf4,0xc7,
+  0x2d,0x84,0xd2,0x47,0x19,0x51,0xcf,0x65,0xeb,0xfc,0x92,0x83,0x6e,0x34,0xd0,0x2d,
+  0x5c,0x2b,0x06,0x6e,0x55,0x46,0x73,0xe9,0x6f,0x5c,0x82,0x26,0x73,0x2a,0xc8,0xba,
+  0x4b,0x1a,0xe3,0x96,0xd3,0xc2,0x16,0x9b,0x74,0x52,0x41,0xf7,0x54,0x05,0x42,0x42,
+  0xa3,0xe3,0xa0,0x54,0xed,0xb0,0xf1,0xd7,0x3e,0xb8,0xec,0x9d,0xcd,0xfd,0x53,0xa6,
+  0xf9,0x03,0x24,0x98,0x83,0x7f,0x1d,0xa1,0x3d,0xba,0xa9,0x68,0xa8,0x51,0x8e,0xa3,
+  0x23,0x42,0x0e,0x48,0xa3,0x23,0x2c,0xde,0x3a,0xc2,0x05,0x36,0xff,0xe5,0x09,0xc3,
+  0xe1,0x74,0x8d,0xe5,0xa7,0x79,0xe1,0x9a,0x05,0x75,0x96,0xd6,0x48,0x09,0x89,0xf8,
+  0xe5,0x35,0xfa,0x39,0x47,0x38,0xc2,0x52,0xa1,0x81,0xb3,0x4e,0x2c,0x3b,0x61,0xd8,
+  0xd2,0x8a,0x43,0xb9,0x3f,0xe1,0xe2,0xbf,0xba,0x78,0xd8,0xfa,0x42,0xc1,0x6e,0x75,
+  0xc4,0x66,0xf6,0x21,0x43,0x86,0x8e,0xc6,0x11,0x33,0xb4,0x7a,0x05,0xf9,0xe1,0xdd,
+  0x9e,0x2a,0xf8,0x1c,0xe0,0x73,0x9e,0x14,0xa1,0x1d,0x45,0x63,0xf9,0xf8,0xc3,0x17,
+  0xf0,0xfd,0x56,0xa7,0xc0,0x01,0x4a,0x04,0x63,0x5f,0xd1,0x0f,0xa4,0x2a,0xfa,0xb5,
+  0x7b,0xd8,0x57,0xb0,0xe5,0x5f,0xd7,0x08,0xed,0xbe,0x83,0xe9,0xda,0x90,0xd6,0x42,
+  0xbc,0x4c,0xa6,0x82,0xb2,0x99,0x06,0xf2,0xfc,0xd7,0x68,0x26,0x66,0x56,0xd3,0xd7,
+  0xb8,0x08,0xe1,0xe1,0x80,0x30,0xd2,0x06,0xe2,0xaf,0xa4,0x1f,0xce,0xa7,0x33,0xfd,
+  0x81,0x9b,0x15,0xbf,0x39,0xa1,0xd6,0x87,0x10,0x91,0xf9,0x09,0x9a,0x19,0xd5,0xaa,
+  0x16,0x86,0x5f,0xa7,0x23,0x56,0xa0,0x80,0xff,0x9a,0xa4,0xa4,0x3c,0x7b,0xbc,0xec,
+  0xfc,0x2f,0x22,0x91,0xd7,0x55,0x4e,0xb6,0xfc,0x7c,0x06,0xe1,0x2f,0xed,0xa8,0x79,
+  0xcd,0xb3,0xc8,0x2b,0xa5,0x2c,0xf5,0xc5,0x50,0xba,0x95,0xce,0x40,0x54,0x31,0x94,
+  0x2e,0xfe,0x6b,0x9c,0x92,0xca,0xe5,0x30,0x35,0xd8,0xf1,0xe1,0x1c,0xc7,0xa2,0x1e,
+  0x3b,0xe1,0x59,0x16,0xa5,0x53,0xc7,0xb0,0x77,0x22,0x11,0x05,0x7b,0x28,0xeb,0xe0,
+  0x56,0xc1,0x69,0x7a,0xa2,0x74,0x32,0xe9,0xd2,0xdf,0x20,0x92,0x22,0x17,0x6e,0x61,
+  0x1b,0x42,0xee,0xe9,0x69,0x19,0x77,0x81,0x68,0x0b,0x11,0x48,0x05,0xd0,0x06,0xa4,
+  0xa3,0xe1,0xa9,0x8e,0x8b,0x8d,0x8c,0x72,0xc4,0xa0,0x40,0x7f,0x23,0x9c,0xef,0x67,
+  0x34,0xbe,0x82,0xbb,0xde,0x1c,0xa9,0x88,0xb8,0x1b,0xbd,0x02,0xec,0x67,0x91,0xf5,
+  0x1c,0x5f,0x21,0xef,0xf9,0x7c,0x66,0xfe,0x9a,0xb2,0xb7,0x45,0xb0,0x22,0xde,0x53,
+  0xa8,0xbf,0x31,0x94,0x8b,0x3b,0xb5,0x0d,0x21,0x86,0xb3,0x19,0x70,0xb7,0xa2,0xf9,
+  0x25,0xb2,0x95,0x67,0xca,0xad,0x8d,0x19,0x65,0xc5,0x77,0x8a,0x77,0x8c,0x82,0x7c,
+  0x7c,0x2e,0xfe,0xeb,0x45,0xa8,0x4d,0x85,0x5d,0xf9,0x5f,0x6b,0xd0,0x47,0x8a,0x12,
+  0xda,0x0a,0x15,0x7f,0x6c,0xa2,0xf1,0x9e,0x08,0x4d,0x5c,0xe0,0x64,0x84,0xdd,0x91,
+  0x2e,0xcd,0x92,0xc1,0xc4,0x3d,0x6e,0xfe,0x4b,0x6d,0x64,0x53,0xbd,0xb8,0x06,0xdb,
+  0x30,0x72,0x88,0xec,0xc5,0x1b,0x7b,0x7a,0x53,0xf9,0x2f,0xc7,0xab,0xcc,0x1d,0xef,
+  0x4f,0xdf,0xce,0x86,0xf4,0xf3,0x44,0x72,0xe9,0x42,0x4f,0xaf,0x31,0xee,0xa7,0x40,
+  0xc4,0x71,0x9e,0x4b,0x9c,0x11,0x1c,0x19,0x2b,0x8c,0x3f,0xcc,0xe1,0x26,0x35,0x07,
+  0xbb,0x7e,0x94,0x8b,0x1f,0x5b,0x8a,0xf7,0xf0,0x9a,0xd5,0x92,0xda,0xb0,0x76,0x09,
+  0x1f,0xdb,0xbb,0x91,0xf8,0xaf,0xed,0x6c,0x8a,0xfe,0x46,0xb1,0xf3,0x9c,0xe2,0x02,
+  0xf7,0xfb,0x08,0xd8,0xf2,0x1d,0x87,0x0c,0x1c,0x02,0xbd,0x79,0x35,0xec,0x27,0x7a,
+  0x3a,0x55,0x36,0x54,0x24,0x1c,0xf2,0x54,0xa2,0xa8,0x90,0xff,0x9a,0x67,0x3b,0xff,
+  0xcb,0x28,0xf9,0xc8,0xdc,0xaf,0xbb,0x81,0x58,0x79,0x62,0x19,0x5d,0x5a,0xae,0xce,
+  0x64,0x64,0x04,0x11,0xac,0xe1,0xa5,0x64,0x28,0x4d,0x22,0x7e,0x85,0xfa,0x1b,0x6a,
+  0x89,0xec,0xba,0x46,0xe2,0x26,0xce,0xc1,0xa8,0x59,0x63,0x77,0x66,0x08,0x5f,0xe3,
+  0xc7,0xa4,0x7e,0x82,0x2a,0xa4,0xed,0xc6,0x5a,0xa3,0x9e,0xcd,0x78,0x8f,0x39,0xf0,
+  0x20,0x8e,0xc5,0xb4,0x3c,0xfe,0x92,0xf1,0x87,0x0e,0x0a,0x10,0xf9,0x5f,0xfc,0x50,
+  0x95,0x9d,0x11,0x76,0x85,0xa8,0xb1,0x0b,0xe5,0xc4,0x91,0x35,0x99,0xb5,0xdb,0x92,
+  0x7b,0x10,0x9a,0xe1,0xc2,0x78,0x3e,0xef,0xfc,0xbb,0xe2,0x0f,0xaf,0x5d,0x0f,0x8a,
+  0x09,0x17,0x0c,0x96,0xe3,0xe8,0x88,0x41,0x29,0xaf,0x82,0x8f,0xa4,0x46,0x62,0x15,
+  0x5c,0x81,0x75,0x62,0xbc,0xd4,0x8f,0x64,0x20,0xa2,0xc3,0x7f,0xc1,0x94,0xf8,0x43,
+  0x37,0xfe,0x32,0xd0,0x8d,0xaf,0x93,0x8a,0x88,0x3d,0x2c,0x48,0xfa,0x51,0x86,0x90,
+  0xdd,0x10,0xfa,0x1b,0x5c,0xde,0xe3,0xf0,0x5f,0x7f,0xda,0xaf,0x16,0x80,0x59,0xb7,
+  0xb1,0xcc,0xbb,0xdf,0x43,0x19,0x61,0xcd,0x5e,0xef,0x4e,0x88,0x53,0x20,0xa2,0x57,
+  0xf4,0xb3,0xaa,0x97,0xf5,0x7b,0x29,0xf2,0xb3,0x93,0x78,0xc6,0x29,0xfa,0x1b,0x72,
+  0xb8,0x97,0x2c,0x77,0xc6,0xfd,0x16,0x49,0x84,0xcd,0x35,0x6f,0xd9,0xca,0x84,0x46,
+  0x62,0x5c,0x84,0x1d,0xe2,0x73,0xbe,0x14,0xda,0x66,0x83,0x35,0xad,0x90,0xff,0x4a,
+  0xe5,0xd4,0x36,0x5c,0xf8,0x4b,0x84,0xd1,0x8e,0x0f,0x52,0xfc,0xa1,0x52,0xa5,0xbe,
+  0x0f,0xd1,0x35,0xab,0x28,0xfe,0x70,0x1c,0xd2,0x71,0xff,0xd3,0x14,0x5b,0xc8,0xc4,
+  0x3d,0xc3,0x05,0xf1,0x87,0x6b,0xa6,0x1e,0x3e,0xe4,0x0f,0x28,0xdc,0x86,0xbc,0x14,
+  0x97,0xa1,0x89,0xa2,0x25,0x79,0xbc,0x20,0xfe,0xd0,0x99,0x7a,0x8f,0x80,0xdf,0x35,
+  0x07,0x0d,0x7c,0x91,0xba,0xe8,0x54,0x04,0xef,0x99,0xd9,0xf0,0x99,0xcd,0x6d,0xe2,
+  0x45,0x8a,0xde,0x24,0x42,0x13,0xcf,0x18,0x82,0x23,0xf3,0x15,0xc6,0x1f,0x6a,0xe9,
+  0x66,0x01,0xb2,0xda,0xfc,0x0e,0xda,0xba,0x65,0x4d,0x2e,0x22,0x71,0x7a,0x08,0x3e,
+  0x36,0x6b,0xd2,0x02,0x76,0xbd,0x98,0xee,0x42,0xb0,0x86,0x37,0xff,0xac,0x17,0x2f,
+  0x65,0xdd,0xf9,0x5f,0xfb,0xb9,0x0b,0x64,0x15,0x4b,0x63,0x6d,0xaf,0x16,0x2b,0xf3,
+  0x7b,0xbb,0x3d,0x06,0x85,0x60,0x9d,0xa4,0xfd,0x2b,0xab,0x1a,0x52,0x7e,0x01,0xd7,
+  0xba,0xb2,0x7d,0xfa,0x93,0x78,0xa9,0xb3,0xb1,0x68,0x93,0xcd,0x7f,0xdd,0x64,0x07,
+  0x21,0xac,0x2b,0x12,0xeb,0x73,0xb6,0x58,0x88,0x3f,0x30,0x6c,0x79,0x90,0x7d,0xd9,
+  0x73,0x50,0xe6,0x37,0x91,0x46,0x62,0x38,0x2e,0xf4,0x0f,0x5f,0x80,0xcf,0x5b,0x21,
+  0xd2,0x83,0xfd,0xb1,0x55,0x61,0xdd,0xf2,0x30,0x73,0xf2,0xbf,0x80,0xd6,0xde,0x1c,
+  0xec,0xaa,0xfd,0xa0,0x64,0x7d,0xf9,0xdb,0xfc,0xd3,0x8e,0xea,0x4b,0xda,0x7a,0x8a,
+  0x48,0xe4,0xb7,0x8f,0x06,0x1e,0x4e,0xbc,0xad,0x7e,0xca,0xef,0x44,0x8c,0xa6,0xcd,
+  0x86,0x2b,0xfc,0x76,0x92,0x3d,0xbc,0x0a,0xbf,0xa1,0xd0,0xc4,0x61,0xed,0x59,0x9b,
+  0xff,0x92,0xba,0x10,0xaf,0x3b,0xee,0xe5,0x20,0x9d,0xfb,0x99,0x13,0x71,0x3b,0xc2,
+  0xed,0x48,0x9c,0x42,0x13,0xd1,0x78,0x5f,0x9e,0x78,0xa0,0x93,0xe3,0x91,0xae,0x3e,
+  0xb3,0x33,0x8c,0xdc,0xfa,0x1b,0x91,0x05,0xa3,0xe8,0x4b,0x08,0x6d,0x8d,0xf7,0x02,
+  0x63,0x9e,0xab,0x02,0x5b,0x6d,0x1e,0x50,0x6a,0xcc,0x6b,0x03,0xe5,0xa3,0x5e,0xf2,
+  0x18,0xc7,0x79,0x6c,0xd8,0x3f,0x2c,0xfc,0xc3,0xfa,0x6c,0x78,0x5c,0x89,0x55,0x7c,
+  0xb8,0x2d,0x3a,0x14,0x78,0xca,0x39,0x7f,0x26,0xfe,0xeb,0xa5,0x36,0xec,0x84,0xef,
+  0x30,0xca,0xff,0x12,0xf8,0x6b,0x12,0x9e,0x41,0x37,0x55,0x7d,0x50,0xf9,0x0a,0xef,
+  0x86,0x4a,0x4b,0x64,0x84,0xbd,0x90,0xbe,0x33,0x8e,0x28,0x69,0x16,0x7a,0x68,0x6b,
+  0xb3,0x25,0x0f,0x29,0x8f,0xf0,0xc7,0x78,0xc5,0x70,0xe7,0x1a,0x36,0xdf,0xad,0xbf,
+  0x51,0x31,0x15,0xcc,0x3a,0x1b,0x62,0xb7,0x9d,0x5e,0x47,0x3a,0x27,0xcb,0x84,0x44,
+  0xf0,0xf3,0xf4,0x27,0xa2,0x6c,0x16,0x7f,0xc6,0x53,0x61,0x75,0x9a,0xb9,0xf8,0x43,
+  0x5d,0xc6,0x94,0x2a,0xce,0xb8,0xaf,0x20,0x0d,0x81,0xdd,0x82,0x00,0xf5,0x49,0x07,
+  0x46,0x5d,0x5c,0xb4,0x12,0xa7,0x79,0xe8,0x9e,0x62,0xe9,0xc9,0x84,0x47,0x8b,0x17,
+  0xc2,0x5a,0x22,0xc7,0x09,0x29,0xa8,0xae,0xf8,0x43,0x6f,0xe5,0xa0,0xdd,0xcf,0xa4,
+  0x4d,0x87,0x7e,0xf8,0x69,0xfc,0xa3,0xb4,0xd1,0x7b,0xae,0x41,0xb7,0xe5,0x1f,0x9d,
+  0x2e,0xb5,0x0d,0xfd,0x19,0xa1,0x78,0xbc,0x7e,0xc0,0xff,0x7c,0x79,0xa3,0xfa,0xa1,
+  0x90,0xaa,0xd6,0xe6,0x83,0x8d,0xbf,0x28,0xfe,0xf0,0x91,0x1b,0xc1,0xb7,0x03,0x6c,
+  0xad,0xdd,0x32,0x7d,0xad,0x78,0x4e,0xe9,0x76,0x79,0x96,0x3b,0x20,0x86,0x72,0xdc,
+  0x2b,0x88,0x4b,0xb7,0xfe,0x86,0xbe,0xc8,0x71,0x26,0x9b,0x2c,0x4a,0x04,0x83,0xdf,
+  0xe5,0x85,0x38,0x16,0x58,0x25,0xeb,0x92,0x0f,0xeb,0x57,0x20,0x32,0xb4,0xf2,0x3c,
+  0xb6,0x5c,0x85,0xa6,0xde,0xcd,0x74,0xe9,0x14,0x5e,0x0a,0x64,0x99,0x65,0xba,0xe2,
+  0x0f,0x17,0xe4,0xc1,0x11,0x39,0xd2,0xea,0x09,0x05,0x3b,0x73,0x61,0x90,0x28,0xbf,
+  0x4a,0x4a,0x23,0x0a,0xe3,0xfe,0x35,0xdf,0x52,0xb7,0xa1,0xd1,0x23,0xef,0x09,0xc3,
+  0x5e,0xbe,0xcb,0x5a,0x91,0x62,0x59,0xb7,0xfe,0x46,0xd0,0x79,0x4e,0x98,0xf8,0x2f,
+  0x12,0x5b,0xc0,0x7e,0xee,0x12,0x5e,0x77,0x95,0xfc,0xd4,0x21,0x1e,0xec,0x0d,0x09,
+  0x3f,0x9c,0xd7,0x48,0x45,0x8e,0x8d,0xc6,0xdc,0xde,0xce,0x6d,0xb8,0xc0,0xda,0xfb,
+  0x17,0x4e,0x3d,0x75,0x0f,0xe2,0x2f,0x82,0x03,0x10,0x3e,0xd3,0xe1,0x1c,0x98,0xa8,
+  0x32,0x10,0x91,0x92,0xbc,0x7c,0x38,0x4c,0x86,0x31,0x30,0x53,0x47,0x63,0x7f,0x7b,
+  0xcd,0x49,0x1c,0x77,0xbf,0x91,0xfe,0xdb,0xaa,0x97,0x35,0x28,0xeb,0x73,0xc7,0x1f,
+  0xe2,0xef,0xea,0x4a,0x8a,0xf1,0x1a,0xa0,0x44,0x30,0xf8,0x5d,0x6b,0x93,0xb5,0x12,
+  0x47,0xa7,0xfd,0x5a,0xeb,0x22,0xab,0xe4,0x0f,0x52,0x48,0x61,0xd9,0xe6,0x08,0x3a,
+  0xc0,0x63,0x77,0xe3,0xc0,0xed,0xd7,0xc2,0xbc,0xd7,0xac,0x1b,0x08,0x14,0x29,0x96,
+  0x2b,0xfe,0x30,0x24,0xbd,0x77,0xf3,0x1a,0xdc,0x7a,0x46,0x76,0xb8,0x81,0xf8,0x0b,
+  0xbd,0x41,0xf3,0x25,0xe3,0x2e,0xa9,0xbf,0x31,0x79,0xd3,0x4b,0xcb,0x70,0x97,0x41,
+  0xa3,0xaa,0xe9,0x24,0x21,0x3b,0xef,0xa4,0x89,0x97,0x5e,0x4e,0xe6,0xf2,0xbf,0x26,
+  0x11,0x29,0xc8,0xdc,0xc0,0x0e,0x9c,0x5f,0x74,0xbe,0x31,0x99,0x3e,0x6d,0x35,0x91,
+  0xf1,0x09,0xfc,0x9e,0x40,0xd6,0xc0,0xf4,0x46,0xf8,0x90,0x37,0x65,0xa5,0x22,0x22,
+  0xd4,0x99,0xa5,0xd6,0x6d,0x8b,0xf9,0x27,0xc6,0x02,0x8a,0x48,0xcc,0xe5,0x7f,0x4d,
+  0xea,0x22,0xb3,0xe3,0x28,0xbb,0x6a,0x62,0x1f,0x0e,0xfc,0xb7,0x1e,0xe5,0x25,0x78,
+  0xce,0x10,0xec,0xc9,0x49,0xfe,0x6f,0x56,0x30,0xab,0xf1,0x4d,0x35,0x14,0x76,0x68,
+  0xf9,0x08,0xa3,0x61,0x87,0x5b,0x7f,0xc1,0x59,0x23,0x7f,0x06,0xa2,0x06,0x7a,0x20,
+  0x2e,0xfc,0xc5,0x11,0xb1,0xc2,0x42,0xb7,0x3f,0x8f,0xfd,0x7c,0x4c,0x0a,0x3b,0xe8,
+  0xb8,0xe8,0x25,0x70,0x3a,0xec,0xb6,0x91,0x2f,0xce,0x8b,0x2a,0x40,0x9c,0x5b,0xbd,
+  0x35,0xa9,0x57,0x51,0xcc,0xdb,0x7d,0x0e,0xfe,0xda,0x0c,0x1d,0xb8,0xd9,0x49,0xfc,
+  0xc5,0x6c,0x7c,0xf1,0x5c,0x3e,0xb9,0x2f,0x48,0xd1,0xbc,0x82,0xd6,0x91,0xa9,0x4f,
+  0xb8,0x9f,0xb6,0x15,0x1b,0x89,0xb0,0x67,0x37,0x6d,0x88,0x3b,0xf3,0xf8,0x6b,0x12,
+  0x06,0x18,0xe1,0x2f,0xe6,0x82,0xc9,0x27,0x24,0x6b,0x4f,0xf0,0x1f,0x27,0xd1,0xce,
+  0x44,0xd8,0xc9,0x08,0x1b,0x21,0xe8,0x1a,0x2a,0x6d,0xc7,0x89,0xf6,0xe1,0xb4,0xba,
+  0x90,0xff,0x07,0x9e,0xd6,0x9c,0xfe,0x06,0xbb,0x84,0xc8,0x37,0x20,0xc8,0x5f,0x8f,
+  0x70,0xd1,0x9f,0x9e,0x72,0x2e,0x91,0x55,0x4e,0xda,0x2d,0x9e,0x49,0x18,0x4b,0x35,
+  0x76,0xac,0xea,0x15,0x97,0x7a,0xbc,0xb5,0x33,0xcb,0xf3,0xf8,0x4b,0xc5,0xbf,0x9e,
+  0xda,0xe2,0x4c,0xcf,0x3f,0xcf,0x94,0x8f,0x80,0x2d,0xe4,0x82,0x3f,0x10,0x57,0x51,
+  0x85,0x8b,0xe8,0x35,0xfb,0xfb,0xe0,0x8e,0xe6,0x2d,0xd9,0x2e,0x80,0x7c,0x17,0xf7,
+  0x73,0x2d,0xaf,0xbf,0x41,0xe9,0x90,0xdc,0xce,0xa6,0x14,0xdd,0x42,0xda,0x86,0xb6,
+  0x1a,0xc9,0x33,0x9e,0x20,0x1d,0xfb,0x34,0x8a,0x23,0x02,0xd1,0x72,0x88,0x80,0x6a,
+  0xa6,0x81,0x54,0x3b,0x82,0x3c,0xc4,0x0b,0xf4,0x37,0x78,0x98,0xaf,0x88,0x14,0x8e,
+  0x97,0x38,0x1b,0x1c,0x11,0x89,0x60,0x9d,0x20,0xb2,0xbd,0x6a,0xe4,0x78,0x75,0x61,
+  0x4b,0x31,0x4d,0xb4,0x27,0xc1,0xe0,0x2d,0x7a,0x73,0x4f,0x1e,0x7f,0x6d,0x08,0x55,
+  0xa7,0x73,0x2c,0x4c,0xf1,0xfa,0xb2,0x53,0x32,0x76,0x8e,0x44,0x0e,0x85,0x52,0x7a,
+  0x0b,0x7b,0xda,0x4b,0x21,0x73,0x02,0x3b,0x3c,0x9f,0x9e,0x37,0xac,0xde,0xc9,0x4a,
+  0xf9,0xf7,0xf9,0xbc,0xb4,0x7a,0x4f,0x59,0x87,0x9c,0x5e,0x84,0xbf,0xac,0x54,0xe3,
+  0x4c,0x44,0x52,0xa7,0xf8,0xc5,0xcf,0x34,0x0e,0x6f,0x21,0x6e,0xeb,0x84,0x1e,0xed,
+  0xf7,0x47,0x94,0x53,0xd6,0x7f,0xa8,0xf5,0xfd,0xab,0xb8,0xb6,0xd9,0x7c,0x39,0x85,
+  0xfd,0x23,0x68,0x2f,0xb3,0x7e,0xef,0xe3,0x1e,0xad,0x14,0x7e,0x0d,0x91,0x7e,0xbf,
+  0xce,0xb6,0xe5,0xf9,0xaf,0x31,0x91,0xff,0x95,0x9c,0x8c,0xd3,0xf9,0x06,0xd1,0x94,
+  0x6c,0xc2,0x98,0x3d,0x40,0xb4,0x97,0x2e,0x80,0x18,0x9f,0xfe,0xb0,0x75,0xcd,0x6b,
+  0xeb,0x82,0x5e,0x35,0x16,0xb5,0x07,0x76,0x0a,0x9d,0x13,0x92,0xa6,0x57,0x5a,0xa7,
+  0x1b,0x36,0xfe,0xe2,0x63,0xe4,0xa2,0x67,0x94,0x6a,0xe3,0x04,0x51,0x90,0xe2,0xf0,
+  0x2a,0x4f,0xa4,0x22,0x48,0xe7,0x4b,0xc3,0x36,0x95,0xb9,0x74,0x1f,0x1c,0x46,0x68,
+  0x16,0xce,0xdc,0x52,0x3d,0x70,0x42,0x15,0xf1,0x6c,0xcf,0xe6,0xf5,0x37,0x8e,0x32,
+  0x8f,0xd9,0xf2,0x00,0x23,0x7d,0xad,0x5a,0xb1,0xcb,0xa4,0x6d,0xfc,0x45,0x6a,0x5a,
+  0xf3,0x2c,0xad,0x55,0xf9,0xb2,0xd8,0x89,0x4a,0x45,0xc6,0x81,0x67,0x01,0xed,0xef,
+  0x8d,0xe6,0x6f,0x83,0x15,0xa6,0xd6,0xca,0x5e,0x03,0x07,0x7f,0x99,0x07,0xb9,0x41,
+  0x92,0xf2,0xa5,0x9c,0x48,0x2e,0xdf,0x7a,0x78,0xdb,0xcc,0x03,0xde,0x14,0xe2,0xaf,
+  0x81,0x44,0xa9,0xb9,0x41,0xb6,0xfc,0x08,0xba,0xdb,0xe6,0x64,0xd1,0x21,0x9f,0xcd,
+  0x37,0xa4,0xe6,0x10,0x34,0x73,0xe9,0x6f,0x74,0x0f,0x89,0xcc,0x56,0xca,0xc1,0xa4,
+  0x65,0x10,0x84,0x92,0xb3,0xed,0xc9,0xd0,0xf9,0xe1,0x2c,0x71,0x2a,0x62,0xcf,0xd3,
+  0x6e,0x33,0x3e,0xa8,0x12,0x00,0xff,0x21,0xec,0xe9,0xd7,0x22,0xcd,0x2e,0xfd,0x8d,
+  0xab,0x89,0x05,0x3d,0x61,0x0a,0x29,0xfc,0xe0,0x06,0xfc,0x17,0x82,0xac,0x21,0x11,
+  0x62,0x64,0xf3,0x5f,0x57,0xcd,0x83,0x29,0x7f,0x56,0xa3,0x96,0x45,0x99,0xc0,0x07,
+  0x2e,0xfd,0x0d,0x18,0xbb,0xa9,0x9e,0xf0,0x97,0x05,0xf7,0xe4,0x1d,0x3c,0x04,0xb3,
+  0xc2,0xf0,0x10,0x10,0x4b,0x66,0x59,0xde,0xf7,0x33,0x1e,0x81,0x80,0xb7,0x93,0x72,
+  0x97,0x1a,0x58,0x00,0xf2,0xf8,0xeb,0x3d,0x7e,0x8c,0x89,0xdc,0x2e,0xa2,0xa2,0x72,
+  0xb4,0x17,0x23,0x37,0x7e,0xc8,0x7b,0x3e,0x45,0x3a,0x03,0xca,0x32,0xef,0x31,0xf4,
+  0x45,0x6d,0x8c,0xd6,0xf8,0x75,0xa9,0x3f,0xcf,0x33,0xe4,0xd8,0x3b,0xf8,0x0b,0xbe,
+  0x0a,0x1b,0xf5,0x9a,0x25,0xaa,0x4c,0x16,0xab,0x11,0xf1,0x87,0x38,0x89,0xbe,0x6e,
+  0x7b,0xd4,0x88,0xb6,0x34,0x5d,0x59,0xad,0xbf,0x01,0x35,0xeb,0x72,0xd4,0x46,0xc9,
+  0x3f,0xe3,0x62,0xf6,0x06,0x5e,0x52,0x53,0xb9,0xfc,0x2f,0x4f,0x95,0x87,0x3c,0xea,
+  0x96,0x54,0x59,0x95,0xe3,0x5a,0xe3,0xcd,0x2c,0xe7,0x99,0x4b,0x65,0x06,0x78,0xca,
+  0x13,0x76,0x61,0xbd,0xed,0x54,0x39,0x22,0x2e,0x24,0x1a,0xf2,0xf8,0x6b,0x7f,0x1b,
+  0xc5,0x1f,0x22,0x0a,0x60,0x6d,0x88,0xbf,0x08,0x0e,0x00,0xe2,0xaf,0x65,0xc5,0x02,
+  0x88,0x91,0x70,0xe5,0x56,0xb6,0x2c,0x8d,0x97,0xac,0x9b,0x05,0x64,0x30,0xc2,0x2d,
+  0xc5,0x65,0xcc,0xcb,0xb7,0x1a,0x55,0x2d,0x21,0x17,0xff,0xb5,0x46,0xe8,0x6f,0x84,
+  0x13,0x49,0x23,0x3d,0x00,0x31,0x9d,0x3a,0x33,0x3d,0x66,0xd6,0xe8,0x1a,0x01,0xb1,
+  0xcb,0x84,0xbf,0xda,0x3f,0x1f,0xe7,0x3b,0x3c,0x31,0x50,0x6d,0xd7,0x7a,0x86,0xff,
+  0x51,0xa5,0x62,0x99,0xd5,0x5a,0x07,0xc4,0x7f,0x79,0x1c,0xfc,0xf5,0x13,0xc2,0x5f,
+  0xe4,0xab,0xeb,0x84,0xbf,0x04,0xe7,0x32,0x6e,0x34,0x48,0x20,0x76,0x9e,0x92,0x86,
+  0xee,0xae,0x14,0x8a,0xf4,0x36,0x22,0x2b,0x6b,0xea,0x0f,0xfc,0x4a,0xe4,0x7f,0xdd,
+  0x55,0x90,0xff,0x75,0x89,0xf2,0xbf,0x1c,0xc9,0x88,0x98,0x18,0x26,0x61,0x14,0x61,
+  0x8b,0xf7,0x17,0x60,0xe7,0xeb,0xbd,0x4f,0xf9,0x5f,0x8e,0xec,0x61,0x89,0x04,0x62,
+  0x02,0x65,0x17,0x79,0x9d,0xf8,0x43,0x6f,0x8f,0xc7,0xc6,0x5f,0x21,0x08,0x13,0xfe,
+  0x8a,0x43,0x1a,0xb1,0x55,0x31,0xb6,0xa8,0x7b,0x11,0x6d,0x75,0xca,0x88,0xc4,0x70,
+  0x5e,0xf6,0x50,0x05,0x25,0xee,0xc4,0x28,0x16,0xe6,0x7f,0x91,0x74,0x49,0xbf,0xcd,
+  0x7f,0x05,0xfb,0xf3,0x44,0x18,0x91,0x5c,0xb7,0x20,0xfe,0x22,0x8c,0xb6,0x84,0x60,
+  0x17,0xde,0x1c,0x37,0x8b,0xf5,0xa0,0x1d,0xa3,0x38,0x93,0xe5,0xf5,0x0f,0xbd,0x87,
+  0x96,0x12,0x6d,0x5a,0x34,0xa4,0xfe,0xab,0x83,0xdf,0xc9,0xf8,0x02,0x89,0x6c,0x90,
+  0x5a,0xa6,0x56,0xf6,0x75,0x02,0x62,0x61,0x4b,0x8e,0xbb,0x2e,0xc8,0x32,0x11,0xf5,
+  0xda,0xaa,0x6e,0x75,0xe9,0x6f,0xa8,0x88,0xbf,0xf2,0xdd,0x42,0xf8,0x4b,0x77,0x89,
+  0x6c,0x74,0x99,0x81,0x1d,0x5a,0x95,0x13,0xa3,0x88,0xfd,0x93,0x8e,0xb6,0x56,0xff,
+  0x73,0x52,0x6a,0x24,0x86,0x53,0x38,0xd1,0x1c,0xfc,0x55,0x35,0xce,0x04,0xfe,0xea,
+  0x77,0xd0,0xd6,0x6a,0xfb,0x80,0x62,0xe9,0x90,0xe7,0xbc,0x37,0x9f,0x59,0xd6,0x1c,
+  0x48,0x4d,0xcf,0xc1,0x2e,0x1b,0x5c,0xef,0x28,0xd0,0x9f,0x67,0x42,0xe4,0x30,0x3b,
+  0x83,0xa8,0x67,0x2f,0xa7,0x99,0x0b,0x36,0x23,0x36,0xa6,0xd2,0x3c,0x65,0x86,0x4b,
+  0x42,0xc7,0x6c,0x84,0x12,0x0f,0x01,0x31,0x23,0x42,0x2d,0x8e,0x8e,0xe2,0xb4,0x7a,
+  0x43,0xe6,0x7f,0x21,0xec,0xfa,0x01,0x6e,0x64,0xcb,0x25,0xff,0x25,0x19,0x31,0xef,
+  0x8b,0xf7,0x06,0xa5,0x34,0xe2,0x61,0xa8,0x4d,0xab,0xb4,0x6e,0x1c,0xf6,0xd4,0xa4,
+  0x5b,0x46,0x08,0x88,0xc9,0x64,0xb1,0x5c,0xfe,0xd7,0x17,0x9d,0xfc,0xaf,0x02,0xfc,
+  0x65,0xd8,0x2d,0x66,0xc8,0xb2,0x55,0xef,0xd0,0xfd,0xb6,0x09,0x91,0x6c,0x31,0xad,
+  0x63,0xbb,0x79,0x9c,0xa4,0x03,0x8e,0xe7,0xe3,0x0f,0x0f,0x7a,0xaa,0x47,0x84,0xf3,
+  0xff,0x7d,0xa8,0x1e,0x96,0x28,0x20,0x55,0x31,0x44,0x06,0x7f,0x9e,0xf0,0xd7,0xb7,
+  0x64,0xa0,0x78,0xb3,0x28,0x0b,0x72,0x10,0xc2,0x64,0xcc,0xe2,0x07,0x11,0x7f,0x69,
+  0xdf,0x2c,0x72,0xe9,0xcf,0x7f,0xca,0x9b,0xde,0x09,0xdb,0x24,0xd7,0x50,0x89,0x30,
+  0x3a,0x16,0x0c,0x93,0x10,0x07,0xff,0x94,0xcf,0xcb,0x06,0x2e,0x27,0x67,0xbb,0x14,
+  0x39,0xda,0x17,0xc7,0x4b,0xd6,0x28,0xb7,0xf2,0x6b,0x7c,0x7f,0x36,0xf0,0x90,0x4b,
+  0x7f,0xde,0x3b,0x01,0xb3,0x7b,0xc5,0x71,0xf1,0x7f,0xb3,0xfd,0x79,0x55,0xe0,0x2f,
+  0xb1,0x01,0x09,0xc7,0x5e,0x46,0x6b,0x10,0x47,0x46,0x20,0x82,0x12,0xc1,0xb4,0x8f,
+  0x68,0xed,0x2d,0xc0,0x5f,0x7f,0x04,0x77,0x58,0xd4,0x7b,0xc2,0x38,0x2d,0xb5,0x35,
+  0xae,0x19,0xc7,0x49,0x1f,0xe0,0xdb,0x8a,0x50,0x0c,0xb0,0x53,0xc3,0xd0,0x28,0x3d,
+  0xa3,0x34,0xc1,0x24,0x17,0x51,0x8b,0x96,0xc3,0x7f,0x1d,0x30,0x7f,0x9b,0xa9,0xa6,
+  0x48,0x1e,0xfa,0xed,0xb5,0x43,0x22,0xff,0x6b,0x0b,0xa2,0x48,0x01,0xc4,0x7e,0xc2,
+  0x85,0xfe,0xbc,0xe8,0x9f,0xb8,0x14,0xf2,0x4d,0x57,0x5b,0xf7,0xbc,0xce,0xfc,0xe6,
+  0x01,0xb8,0xc3,0x42,0x44,0x96,0xe3,0xbf,0x76,0xc0,0xf7,0x83,0x0e,0xc9,0xa5,0xdb,
+  0x3a,0x93,0x1b,0xbc,0xf6,0x3e,0xf8,0xa4,0x21,0xce,0x21,0xf1,0x4f,0x4c,0x73,0x8e,
+  0x28,0xeb,0xab,0x4d,0xdf,0xbd,0xbe,0x2f,0x4b,0x17,0x7d,0x9d,0xc3,0x7f,0x19,0x33,
+  0x06,0xca,0x70,0x6f,0xea,0xf5,0xd9,0x69,0x44,0x0e,0x01,0x1a,0x72,0x90,0x78,0xda,
+  0x52,0x16,0x6e,0xf2,0x4f,0xeb,0xa6,0x23,0x2f,0xd1,0x42,0x49,0xee,0x86,0xa0,0x00,
+  0xc4,0xae,0x37,0x90,0xc7,0x5f,0x3f,0x44,0x98,0x43,0xd1,0x74,0x2a,0xe1,0x2f,0xe1,
+  0x74,0x9d,0x66,0xc2,0x07,0x98,0x44,0xa7,0x22,0x6a,0x05,0x1e,0x94,0x0a,0xd5,0x76,
+  0x0c,0x0c,0x02,0xd5,0x9a,0xc3,0xda,0xc3,0x30,0xc1,0xea,0x08,0x13,0x7d,0x30,0x25,
+  0xff,0x4b,0x7a,0x05,0xa5,0xe2,0x39,0x6c,0xc2,0x26,0xd4,0x3c,0x1f,0xe6,0x79,0x34,
+  0x31,0x5e,0x23,0x3a,0x3d,0xb0,0x36,0x22,0x9e,0xdc,0x68,0x21,0x3a,0x76,0xe1,0xaf,
+  0x4f,0xf4,0x05,0x79,0xaf,0xb2,0x84,0xd0,0x5f,0xde,0xcf,0x4c,0x89,0x4b,0x0f,0x93,
+  0x0b,0x0a,0x9b,0x45,0x8b,0xda,0x68,0x96,0xbc,0x51,0xde,0x08,0xbf,0x48,0x29,0xf4,
+  0x7d,0x2c,0x3b,0xfe,0x10,0xd6,0xda,0x6a,0x00,0xd3,0xd7,0xba,0xf5,0x13,0x62,0xae,
+  0x83,0x7a,0x7a,0xa3,0xf0,0xd2,0x42,0x87,0xe3,0xa0,0x7d,0x87,0xf0,0xd7,0x7c,0x02,
+  0x50,0x39,0xfc,0x55,0x65,0xe3,0xaf,0xa0,0x0b,0x7f,0xe5,0x84,0xe8,0x0f,0x4b,0x68,
+  0x16,0x16,0x71,0x68,0x3e,0xe1,0xa2,0xa3,0xaf,0xbe,0x91,0x97,0xf9,0xf5,0x0e,0xe9,
+  0x8b,0xe6,0xf0,0x97,0xd7,0xd3,0x6d,0xa4,0xa5,0x44,0x03,0x8e,0x57,0x9f,0x9c,0x9e,
+  0xaa,0x3d,0x5e,0x51,0xb5,0xca,0x2a,0xee,0x92,0x53,0xb8,0xc5,0x49,0xe5,0x1b,0x2c,
+  0x06,0x56,0xa2,0xa6,0xa5,0xf2,0x5b,0x0e,0x7f,0xad,0x11,0xf8,0x0b,0x51,0xed,0x88,
+  0xc8,0x22,0x29,0x11,0xf9,0x44,0xc1,0x9a,0x3e,0x31,0x5e,0xc2,0x1f,0x1b,0x9d,0x8e,
+  0x30,0xb9,0xb5,0xd1,0x0c,0x4b,0x0f,0x7f,0x76,0x6b,0x09,0xaf,0x6c,0x24,0xfd,0x70,
+  0xf2,0xb1,0x73,0xf8,0x6b,0x0c,0x26,0xd6,0x52,0xfc,0x61,0xdb,0xc3,0xfc,0x9a,0x27,
+  0xd6,0x67,0x07,0x19,0x4a,0x6f,0x70,0xaf,0xe8,0xf0,0x03,0xca,0xa4,0x7a,0xcd,0x88,
+  0xb5,0x96,0xd8,0x47,0xf7,0x66,0x8d,0xa5,0x4c,0xf2,0x49,0x39,0x16,0x2e,0xfd,0x0d,
+  0x11,0x64,0xd8,0x43,0x31,0x54,0x3c,0x36,0x20,0x40,0xd6,0x08,0x61,0xe1,0x31,0xe5,
+  0x63,0xf6,0x89,0x28,0xf4,0x10,0x68,0x4c,0xe3,0x6b,0x73,0x4e,0xc1,0x16,0x38,0x89,
+  0x3d,0x5f,0x3a,0xa6,0xf9,0xe0,0x55,0x62,0x85,0x52,0x05,0xfc,0x97,0x8c,0x36,0xbc,
+  0x86,0x46,0xed,0x25,0x01,0xb2,0x0e,0xab,0x24,0x24,0x05,0x54,0x51,0x25,0x68,0xe0,
+  0x06,0xfd,0x5d,0xbc,0x54,0x35,0x20,0x64,0x0f,0x3b,0x28,0xd0,0x37,0xc2,0x42,0xea,
+  0x4e,0xbc,0x84,0x5e,0x41,0xa4,0x20,0xff,0xcb,0x12,0xba,0xa0,0x0e,0xbd,0x08,0x3b,
+  0x0d,0x23,0x2b,0xfa,0x19,0xf7,0xaf,0x6c,0x67,0xe4,0x6e,0x3a,0x98,0x0a,0xf7,0x09,
+  0xa6,0x38,0x4d,0x01,0xba,0x11,0x84,0x6f,0x49,0x6f,0x9c,0x23,0xfe,0xea,0x72,0xe9,
+  0xcf,0x7b,0x6b,0x0a,0xf1,0x3b,0x45,0xfc,0xd2,0x0e,0x6b,0x41,0x82,0x0c,0xb0,0x53,
+  0x0b,0xbf,0x80,0x97,0x58,0x87,0x10,0x88,0x80,0xd0,0x8e,0xdd,0x1d,0xef,0x80,0xaa,
+  0xb2,0x4c,0x41,0xfe,0x97,0x3d,0x2f,0x3c,0x31,0xeb,0x8b,0x94,0xd0,0x3a,0x6c,0x44,
+  0x29,0xa7,0x78,0x84,0x7f,0x40,0xfb,0x57,0x17,0x0b,0x3b,0xe9,0x90,0x78,0x29,0x8b,
+  0xfd,0x93,0xf1,0xcc,0x83,0x81,0xfe,0x68,0xcb,0xe6,0xc3,0x3e,0x9e,0xe7,0xbf,0x5c,
+  0x68,0x6b,0xb1,0x34,0x46,0xe1,0x25,0x7e,0x6b,0x56,0x19,0x35,0xa9,0xec,0xd7,0xad,
+  0x02,0x6d,0x79,0x17,0xc9,0x88,0xc4,0x4b,0xa9,0x6f,0x5b,0xb6,0x58,0xfd,0xe2,0x65,
+  0x68,0xac,0xcf,0xf3,0x5f,0x0e,0x07,0x2d,0x0c,0x81,0xdf,0x3f,0x90,0x6e,0xc6,0x08,
+  0x1d,0x4d,0xe3,0xf4,0xfc,0x2b,0xca,0x3e,0x8b,0xf5,0x6e,0xa6,0x14,0xce,0x13,0x66,
+  0x94,0x44,0x4d,0x43,0xfc,0xb8,0xd9,0x45,0xd2,0xf4,0x6e,0xfd,0x8d,0x3c,0xec,0xaa,
+  0x95,0xf3,0xeb,0x30,0xcc,0x4f,0x77,0xa6,0xf1,0x9d,0x3f,0xe2,0x41,0x68,0xc6,0xc5,
+  0x25,0x7b,0xea,0x6d,0xfc,0x4b,0x9c,0x8c,0xcf,0x97,0x21,0x88,0x4e,0x05,0xef,0x54,
+  0xff,0x0d,0x5c,0xfa,0x1b,0x39,0xd8,0xf5,0xa4,0xb3,0x7f,0x61,0x3f,0xa6,0x35,0x03,
+  0xfb,0x79,0xb7,0x29,0x2a,0xb8,0x9d,0x04,0x05,0x48,0x87,0x01,0x5f,0xac,0x36,0xd3,
+  0xb0,0xb4,0x43,0x2c,0x81,0x46,0x95,0x82,0xe3,0x5e,0xef,0xca,0xff,0x42,0x9f,0x7f,
+  0xc5,0x43,0xec,0x14,0x49,0xed,0x49,0x91,0xc3,0x17,0xf8,0xbc,0xb8,0x76,0x4f,0xd1,
+  0xdb,0x94,0x97,0x14,0xc7,0xf5,0xf9,0x14,0xc9,0x1e,0x8e,0x80,0x94,0xe3,0xab,0xa0,
+  0x9b,0x1b,0xac,0x47,0x3b,0xaa,0xd2,0xf0,0xd7,0x6c,0xbe,0x3b,0xff,0xab,0xd1,0x12,
+  0xf8,0xeb,0xd7,0xd0,0x38,0x5c,0x12,0x59,0x2a,0xd4,0x0e,0x13,0x01,0x43,0xe9,0x23,
+  0x9d,0xe4,0x76,0x74,0xb6,0x4f,0x36,0xbf,0x9c,0x6e,0xcc,0x22,0x22,0xfb,0x18,0x4e,
+  0x18,0x91,0x6c,0xa0,0x5e,0x49,0xf0,0x5e,0x58,0x98,0xf5,0xdf,0xe2,0x8a,0x3f,0x14,
+  0xfc,0xb2,0xc8,0xf6,0x22,0xfc,0x55,0x6a,0xcf,0x2f,0x13,0x9d,0xc0,0x49,0x3a,0x35,
+  0x32,0x71,0xca,0x4c,0x4a,0xea,0xf9,0xbc,0x0c,0xfd,0xa5,0x9b,0xc7,0x9a,0xaf,0xe8,
+  0x77,0x59,0xff,0xc6,0xa7,0xd6,0xff,0x12,0xb1,0x07,0x38,0x28,0xc3,0x62,0x11,0x1e,
+  0x97,0xf9,0x0e,0x71,0xb8,0xcc,0x85,0x31,0x92,0x9e,0xb0,0xa1,0x19,0x21,0x0e,0xba,
+  0x79,0x3e,0x3a,0xff,0x51,0x73,0x56,0x6a,0xa9,0x5b,0x7f,0x5e,0x1e,0xf7,0xfd,0x3b,
+  0x49,0xca,0xbf,0x29,0x36,0x97,0x8f,0xc0,0x4e,0xeb,0xfe,0x03,0xec,0x44,0xa3,0xf9,
+  0xdf,0x69,0x6b,0xb3,0x36,0xd9,0x99,0xc8,0x14,0x9b,0x71,0x14,0xda,0x19,0x62,0xd8,
+  0x56,0x27,0xfe,0xd0,0xd1,0x9f,0xef,0x5c,0x2f,0xfb,0x39,0x6b,0x13,0x61,0x15,0x86,
+  0xb6,0x92,0xdd,0x2d,0xf4,0x0f,0x45,0xfe,0x57,0x5e,0x1a,0x91,0x57,0x0c,0x61,0xcf,
+  0xdf,0x0c,0x29,0x0a,0x98,0x51,0xe7,0x17,0xe4,0x7f,0xd9,0xb2,0xf3,0x8e,0xb6,0x21,
+  0xa9,0x40,0x88,0x37,0x41,0xdf,0x0d,0xb9,0xbc,0x75,0x07,0x7f,0x65,0x0d,0x7a,0xd9,
+  0x36,0x72,0xbe,0xdc,0x38,0x83,0xf3,0xeb,0x3a,0xfd,0x79,0x45,0x6a,0x1b,0x0a,0x91,
+  0x8d,0xab,0x67,0x10,0x76,0xed,0x15,0xe7,0xd8,0xd1,0x29,0xd2,0x88,0x57,0xe3,0x5d,
+  0xd4,0x72,0x27,0xa2,0xc6,0xee,0xd4,0xe6,0x8f,0x6f,0xa0,0x3f,0xef,0x32,0x86,0xa1,
+  0x09,0x6e,0x15,0x6a,0xf3,0x96,0xd0,0xdf,0x90,0x69,0x5f,0xb7,0x3a,0xf7,0xdc,0x6a,
+  0x6b,0x47,0x40,0x6d,0x7b,0xf2,0x3a,0xfd,0x79,0xf4,0x33,0xdf,0x28,0x14,0xe2,0xd0,
+  0x88,0x26,0xb0,0x19,0x04,0xe7,0x92,0x4a,0x97,0x56,0x89,0x9c,0x23,0x23,0xb2,0x6c,
+  0x65,0xaa,0xf2,0x3a,0xfd,0xf9,0x3c,0x25,0x91,0x83,0x4b,0xc4,0x76,0xdd,0xf0,0xd2,
+  0xf6,0x4d,0x55,0xea,0x21,0x2b,0x7a,0x8f,0xfa,0xb4,0x6f,0x0a,0xff,0x25,0xee,0x79,
+  0x2a,0x7f,0xf3,0x2e,0xc2,0xd4,0x0b,0xe1,0xe7,0x71,0x3b,0xff,0x2b,0x77,0x69,0x3f,
+  0xfa,0xe1,0x3f,0x24,0x9e,0x5a,0x10,0x2b,0x37,0xb9,0xe3,0x0f,0xf7,0xe7,0x51,0x80,
+  0xc3,0xcb,0xe8,0x42,0xff,0x70,0x86,0xad,0x7f,0x28,0x2f,0xd9,0xfa,0x87,0x86,0xb1,
+  0xfc,0x16,0x41,0xd0,0x54,0xa5,0x5b,0xd4,0xe8,0x7d,0x6e,0xfe,0xcb,0xee,0xde,0xf4,
+  0x19,0x88,0xf9,0x64,0x87,0xaf,0x89,0xaa,0x36,0x7f,0x21,0x04,0x4f,0xc4,0x25,0x84,
+  0x66,0xec,0x9c,0x39,0xd6,0xda,0xa5,0x06,0xa6,0x21,0xfe,0xba,0xdc,0xda,0x05,0xe1,
+  0x47,0x5d,0xfc,0x97,0xf7,0x90,0xdd,0x87,0x7a,0x8e,0x34,0xb9,0x62,0x08,0xd9,0xf9,
+  0xa1,0xf4,0x38,0xad,0x63,0xdb,0x12,0x79,0x6a,0x0c,0xfe,0xc7,0x0c,0xa9,0x7f,0x08,
+  0x57,0xf4,0x3b,0x97,0xe1,0x1c,0x2c,0xcc,0xff,0xba,0x8e,0xff,0x5a,0x60,0x89,0xea,
+  0x00,0xaf,0x12,0x8f,0x6f,0x2b,0xae,0x4b,0xfc,0x75,0x85,0x6a,0xba,0x0d,0xa2,0x07,
+  0x72,0x65,0xda,0x02,0x73,0xe5,0xff,0x4a,0x7f,0xc3,0x06,0x59,0x01,0x99,0xff,0x55,
+  0x27,0x89,0x30,0xba,0xe4,0x13,0x01,0x96,0x9e,0xfb,0x49,0x44,0x9d,0xf0,0x97,0x50,
+  0xa4,0x9f,0x82,0xbf,0x5c,0xb4,0x57,0x50,0x6a,0xcb,0x6b,0x8e,0xec,0xbc,0x86,0xf8,
+  0xcb,0xc9,0x08,0xcb,0x89,0x75,0xac,0x14,0x51,0x1f,0x88,0xbf,0xca,0x6e,0xcc,0x7f,
+  0xe5,0x5f,0x12,0x91,0xff,0xd5,0x06,0x73,0xed,0x17,0x89,0x22,0x1b,0x05,0x34,0xfb,
+  0x9c,0xb8,0xe7,0x6b,0xe2,0xdd,0x28,0xd4,0x3f,0x74,0xf7,0x8f,0x14,0x2a,0x39,0x94,
+  0xee,0xc2,0x9b,0x29,0xff,0x8b,0xcb,0x17,0xdb,0x93,0xeb,0x1f,0x4a,0xd0,0x96,0x49,
+  0x79,0xe6,0xae,0x07,0xc3,0x54,0xff,0x4b,0xe2,0x9d,0x1b,0xea,0x6f,0x88,0x61,0x72,
+  0x1b,0xde,0xfc,0x25,0x6e,0x23,0xb2,0xf3,0x29,0x51,0x2c,0xec,0xcd,0x1b,0xf2,0x5f,
+  0x04,0xc4,0x58,0x56,0x68,0xcb,0x93,0xda,0xbc,0x2a,0x13,0xc1,0x2a,0x25,0x73,0x6d,
+  0x53,0x63,0x2f,0x90,0xa2,0x4b,0x85,0x31,0x06,0x0f,0x02,0x6f,0xbb,0x81,0xfe,0xbc,
+  0xa4,0xbd,0x5a,0x48,0xed,0xf0,0x30,0x1d,0x12,0x52,0xcb,0x8b,0x3c,0xc8,0x3b,0x5d,
+  0x42,0xf4,0xc3,0xfa,0x8b,0x3a,0xc2,0xae,0x91,0x6d,0x77,0xaa,0x2f,0xb6,0x56,0xee,
+  0x53,0x47,0x0a,0xf3,0xbf,0x44,0x1d,0x8d,0x42,0x1d,0x57,0x53,0x38,0x8a,0xdd,0x1d,
+  0x86,0xa3,0xc8,0x11,0xb2,0xa1,0x19,0xed,0x5f,0x54,0xff,0x8b,0x8c,0x96,0xc6,0x5d,
+  0x53,0xf5,0xe7,0x6d,0x5e,0x26,0x2b,0xe9,0x18,0x5d,0x26,0x3a,0x99,0x07,0xd5,0x3c,
+  0x65,0xf3,0x2a,0x51,0x63,0x6d,0x2f,0x10,0xe2,0x68,0x2d,0x9b,0x85,0x3e,0xa4,0xc0,
+  0x7a,0xee,0xfc,0x2f,0x97,0xda,0x7c,0xd6,0xd6,0x3f,0xbc,0x3d,0xfe,0x27,0xdf,0x46,
+  0xe3,0x2a,0x91,0x5c,0xdf,0x11,0x2d,0x77,0x0d,0xff,0xc5,0xfa,0xf2,0xdf,0xb5,0x5f,
+  0x4c,0x08,0x45,0x8e,0xd9,0xfa,0xa7,0x7c,0x27,0xdd,0x3c,0x25,0xff,0x6b,0x0a,0x9f,
+  0x62,0x9f,0xfb,0x19,0x6e,0x69,0x7a,0xaa,0x30,0xb5,0x96,0x74,0x8d,0xac,0x00,0xbf,
+  0x6d,0x44,0x8a,0xef,0x71,0x25,0x5f,0xff,0x4b,0x97,0x6a,0xf3,0x04,0xbb,0x78,0x93,
+  0x1d,0x7f,0x98,0x5a,0x90,0x2d,0x1d,0x4b,0x5e,0x85,0x71,0x34,0x02,0xe3,0x49,0x51,
+  0x1a,0xec,0x52,0x60,0xac,0x9c,0xf0,0x97,0x10,0x4b,0x8c,0x79,0xaf,0x25,0x62,0x54,
+  0xff,0xcb,0x95,0xff,0x85,0x90,0x4a,0xaa,0xf1,0x3f,0xe3,0xc4,0x1f,0x1e,0xe4,0x8b,
+  0xe2,0xea,0xba,0xc4,0x59,0x38,0x8a,0xbd,0x11,0x10,0xa1,0x89,0x7a,0xf5,0x90,0x2d,
+  0x5d,0x72,0x87,0xd5,0x12,0x62,0x37,0xc7,0x5f,0xc8,0x56,0x53,0x56,0xb8,0x9b,0xff,
+  0x92,0xfd,0x7c,0x32,0xa7,0x3f,0x8f,0x7d,0x68,0x0b,0x7a,0x1c,0xa0,0x0d,0xf1,0x81,
+  0x44,0x5e,0x9a,0x1e,0x76,0xeb,0x82,0x11,0xfb,0x13,0x38,0x68,0xe0,0xe0,0xde,0xe7,
+  0xca,0xff,0xca,0xfb,0x2d,0xbb,0x73,0xc7,0x86,0x89,0x2a,0x53,0x8d,0xa1,0xe7,0xd9,
+  0xd3,0x62,0x0c,0xfb,0x1c,0x86,0x45,0x70,0x64,0x0b,0x52,0x24,0x17,0xe6,0x53,0xd1,
+  0xe1,0xf3,0x0f,0xa9,0x75,0x4e,0xfe,0x97,0xa3,0x3f,0xbf,0xca,0x39,0x96,0x17,0xfd,
+  0x4c,0xd1,0x62,0x5f,0xbc,0x84,0xee,0xc1,0x04,0x1c,0x1e,0xd6,0x2e,0x21,0x92,0xfa,
+  0x10,0xf7,0x21,0xf2,0xf0,0x71,0x07,0x21,0x9d,0x76,0x8f,0xdf,0x3b,0x61,0x86,0x71,
+  0xc7,0x77,0x7e,0x57,0xca,0xc9,0xff,0xca,0x78,0x0a,0x64,0xe7,0x1b,0xff,0x8c,0xc4,
+  0xd3,0x2c,0x74,0xbf,0xa7,0x0c,0x25,0xd1,0x94,0xb7,0xa2,0xcb,0x87,0xcf,0xc1,0x95,
+  0xb6,0x20,0xff,0xeb,0x46,0xc9,0x2c,0x0b,0x96,0xf9,0xa5,0xfe,0x06,0xe1,0xaf,0xe4,
+  0x49,0xf8,0x5d,0xee,0xd2,0xb6,0x88,0xb5,0x92,0xf8,0xaf,0x5f,0xaa,0x0b,0xb2,0x9b,
+  0x33,0x4e,0xfe,0xd7,0xa3,0x39,0xfd,0xf9,0xc2,0x28,0xc1,0x5d,0xa4,0xd8,0x36,0x29,
+  0x68,0x2f,0x6d,0x54,0x71,0x85,0x14,0x1e,0x4e,0x50,0xdc,0xe0,0xfc,0x5a,0x78,0xd6,
+  0x0a,0xde,0x83,0x1e,0xa3,0xe1,0xce,0xff,0xba,0xfe,0x39,0x8e,0xc8,0xbc,0x3e,0x7f,
+  0xca,0xa5,0xfd,0x74,0xc9,0xc3,0x3e,0x0f,0x9d,0x7a,0x70,0x40,0xad,0xc7,0xe7,0xe4,
+  0xf3,0xbf,0xaa,0xc2,0x42,0xe4,0xd0,0xec,0x06,0x27,0xed,0x2b,0x28,0x94,0xd2,0x4f,
+  0x2e,0xe9,0x22,0x20,0x26,0x94,0xfa,0xca,0xaa,0xfa,0x04,0x17,0xb0,0x1f,0x11,0xb4,
+  0xc9,0xa2,0xd5,0xc6,0x2e,0xd5,0x68,0x51,0x1b,0x98,0x5d,0x07,0x5a,0xd4,0xff,0xaa,
+  0xcf,0x77,0xa6,0xac,0xff,0x35,0x11,0x0a,0x1e,0x13,0xfd,0x33,0x06,0x0d,0x32,0xc1,
+  0x04,0xa1,0x19,0x11,0xc4,0x1f,0xf9,0x27,0x8c,0xe8,0xeb,0xfe,0xcf,0x28,0x73,0x52,
+  0x27,0x8c,0x2e,0x2b,0xfc,0xbc,0x02,0xae,0xf8,0xc3,0xe0,0xad,0x82,0xe4,0x72,0xea,
+  0x7f,0x4d,0x4a,0xbd,0xca,0x51,0x07,0x64,0xed,0x57,0x8e,0xc2,0xef,0x8c,0xd8,0x71,
+  0x89,0xc8,0xf4,0xa6,0x81,0x40,0x9b,0xf0,0xfd,0xbe,0xfb,0x4a,0x60,0xff,0xd2,0x1c,
+  0xfe,0xba,0x54,0x2c,0xb9,0xad,0xe9,0x93,0xde,0x3f,0xf2,0xc3,0xfd,0x5b,0x64,0xda,
+  0x57,0xd4,0x3e,0xf1,0x30,0x16,0x0c,0xf8,0xf7,0x2e,0x6d,0xc0,0xa9,0xf7,0x08,0xb6,
+  0x2c,0x7d,0x44,0x54,0x9e,0xdd,0x4c,0x1c,0xd9,0x49,0x59,0x35,0x6c,0xd4,0xc9,0xff,
+  0x7a,0x4f,0x70,0x5b,0x2a,0x95,0xa4,0x3d,0xc2,0x82,0x67,0x03,0x84,0xbf,0x3e,0x44,
+  0x90,0x55,0x8c,0xc6,0xb4,0x97,0xac,0xca,0x51,0x35,0x9d,0x78,0x16,0xde,0x42,0x8c,
+  0xb6,0xa2,0x07,0xb1,0xf0,0x73,0x6d,0xc1,0x38,0xde,0x7c,0x05,0x3a,0x8c,0xe0,0x39,
+  0xa1,0x77,0x61,0xe7,0x7f,0xb5,0xc3,0x4e,0xe9,0xb3,0xbd,0x8a,0x83,0x12,0x1a,0xd8,
+  0x28,0x1c,0x7b,0xd5,0xb0,0xe3,0x72,0x4d,0x63,0xf0,0xe6,0x20,0x45,0x2d,0xda,0xbe,
+  0xdf,0x4d,0x19,0xa8,0x32,0x8b,0x23,0x45,0x27,0xa7,0xa5,0xfd,0xa2,0xc5,0xd1,0xdf,
+  0x98,0xf1,0x13,0xef,0xbf,0xd2,0xb9,0x96,0xc8,0xf2,0xeb,0x08,0xda,0xe0,0x5a,0xd9,
+  0x25,0x46,0x59,0xa5,0x17,0xc0,0xb7,0x37,0xf8,0xac,0xf1,0x43,0xc4,0x68,0x2b,0xe8,
+  0xd2,0xde,0x9b,0x82,0x4b,0x8a,0x69,0xa5,0xdd,0xa8,0x12,0x36,0x87,0x9c,0xfe,0xc6,
+  0x7b,0xfc,0x39,0x4e,0x5c,0x12,0xde,0x33,0xc6,0x1b,0xec,0x30,0x51,0x47,0xe6,0x9d,
+  0xe2,0xf4,0xbe,0xd8,0xf3,0xb2,0x46,0x6a,0x1b,0x22,0x22,0xd1,0x3b,0x3e,0x50,0x47,
+  0xc1,0xa5,0x23,0x6c,0xc0,0x7c,0x91,0x5a,0x72,0xfa,0x1b,0xdb,0xe1,0x6d,0x66,0x4b,
+  0xca,0x5f,0x01,0x57,0x31,0xb5,0x92,0x51,0xcf,0xc3,0xf0,0x29,0xfc,0xdc,0xaa,0xce,
+  0x22,0xda,0xba,0xe6,0x48,0xd6,0x8c,0xb5,0x37,0x9a,0xc2,0xe7,0xff,0xa3,0x90,0xc4,
+  0xcc,0xc7,0x1f,0xfe,0xd8,0x95,0x57,0xdb,0x4b,0x5c,0x49,0x3e,0x2a,0x78,0xad,0x40,
+  0x88,0x25,0x7b,0x64,0x39,0x0f,0x5c,0x13,0xd8,0x88,0x71,0xce,0x7c,0x81,0xee,0xd9,
+  0x87,0xdf,0x07,0x5f,0xad,0xee,0xca,0x5f,0xd9,0xf9,0x5f,0xd3,0xe6,0x9a,0x87,0x67,
+  0xd6,0x5c,0x52,0x09,0x7f,0x75,0x0f,0x56,0xe6,0xf5,0x21,0xc5,0x2f,0x7d,0x49,0xa9,
+  0xb5,0x14,0xda,0xbf,0xa8,0x45,0xa1,0x42,0xd5,0x3b,0x44,0x32,0xa6,0x40,0x64,0x41,
+  0x4b,0xbb,0xc4,0xfe,0xe8,0xe0,0xaf,0x65,0x22,0x0e,0xcd,0x3e,0x73,0x08,0xe1,0x56,
+  0x52,0xb4,0x52,0xf0,0xcb,0x76,0x41,0xa8,0x30,0xf1,0x8c,0x96,0xda,0x0d,0x55,0xbd,
+  0xb8,0x8e,0x7d,0x04,0xdb,0xa4,0xd6,0xd0,0x66,0xe2,0xbf,0x2c,0xad,0xde,0xd1,0xdf,
+  0x18,0xf3,0x94,0xc1,0xc1,0x76,0xdb,0xe7,0x7f,0x09,0x7d,0x7e,0x89,0x0b,0x52,0x44,
+  0xd0,0x34,0xbf,0x0d,0x8b,0x10,0x0e,0x28,0x7f,0x5f,0xf6,0x9a,0x13,0x9a,0x78,0x16,
+  0xfe,0x29,0x5d,0x11,0xf7,0xd1,0x3d,0x29,0xee,0xc9,0xde,0xb2,0x1e,0x9f,0x23,0xbe,
+  0x4f,0x8b,0xea,0x35,0xce,0xdb,0xdc,0x16,0xef,0x96,0x22,0xf3,0x2b,0xe1,0xd7,0x32,
+  0xff,0x6b,0xa5,0x79,0x31,0x8d,0xd0,0xec,0x36,0x65,0x00,0x2e,0xea,0x0b,0xb3,0xab,
+  0x6e,0x57,0x46,0xcc,0x73,0x3b,0x23,0x4b,0x4a,0xe9,0x1c,0xe9,0xd7,0x50,0x4f,0xb1,
+  0x19,0xb9,0xf8,0xc3,0x03,0xae,0xe5,0x4b,0x5f,0x94,0x8f,0x3f,0x14,0x83,0xf2,0x5d,
+  0xe2,0xbf,0xce,0x29,0x63,0xcb,0x48,0xa6,0x92,0xf0,0x17,0xff,0x48,0xbf,0xcb,0x2c,
+  0xa1,0x99,0xfb,0x91,0xfe,0x92,0x3b,0xfe,0xd0,0x93,0x2b,0x1b,0xf7,0x09,0x7f,0x19,
+  0xba,0x6c,0xbd,0x4a,0x1e,0xb5,0x0f,0x24,0xf7,0x46,0x87,0x11,0x56,0x18,0xce,0x3d,
+  0x1f,0x13,0x06,0x11,0x97,0x12,0xc4,0x69,0x6e,0xe9,0x51,0xbe,0xee,0xe4,0x7f,0x6d,
+  0x47,0x47,0x44,0xec,0x29,0xaf,0xa6,0x9f,0x81,0x8a,0x41,0x3b,0xfe,0xd0,0xd6,0x9f,
+  0x47,0x87,0xe1,0x78,0x28,0xdb,0xac,0xdb,0x7b,0x13,0x4e,0x7c,0x0a,0x9b,0x0f,0xac,
+  0x63,0x57,0xcc,0xc7,0xe8,0xe8,0xf5,0x42,0x3e,0xff,0xeb,0x9f,0x0c,0x59,0xff,0xab,
+  0xec,0x6d,0xef,0x16,0x7e,0xef,0xb0,0x83,0xbf,0x08,0x91,0x51,0x87,0xcf,0x19,0x52,
+  0xd7,0xb0,0x1f,0x60,0xcb,0x37,0x24,0x23,0xf6,0x98,0x4d,0x8d,0x71,0x2a,0xc4,0xac,
+  0x7d,0x9b,0x65,0x1d,0xfc,0x75,0x4a,0xef,0xb2,0x55,0x71,0xd4,0xe7,0xe4,0x91,0xa0,
+  0x3c,0x37,0xee,0x74,0x02,0x11,0xd5,0x10,0xeb,0x10,0x2f,0x80,0x42,0xf2,0x38,0xc9,
+  0x99,0xe1,0x7e,0xc9,0x8d,0xea,0x02,0x9a,0xe5,0xf4,0x0f,0x0f,0x79,0xae,0x66,0x6d,
+  0xfc,0x75,0x8a,0x64,0x64,0x64,0xb6,0x57,0xd0,0x96,0xdd,0x80,0xb9,0x7c,0x66,0x5c,
+  0xd9,0x21,0xf0,0x97,0x78,0x21,0xbf,0xc8,0x63,0xe9,0x55,0xe9,0x4a,0xbc,0x99,0x0b,
+  0x20,0x76,0xd9,0xae,0xfb,0x86,0x33,0x6c,0xcc,0xa6,0x63,0x3c,0xf9,0xb0,0xc3,0x9c,
+  0xa7,0xe7,0x69,0x80,0x5b,0xdb,0x2a,0xe3,0x85,0xbe,0x9f,0x14,0x4b,0x94,0x29,0x4b,
+  0x79,0xfd,0x43,0x63,0xdc,0x94,0x3e,0xe4,0xb4,0x71,0xc8,0xe4,0x03,0x11,0x6f,0xcd,
+  0x7b,0x9e,0x17,0x05,0x35,0x86,0xb0,0xab,0x32,0xa7,0x33,0xf0,0xde,0x75,0xfa,0x1b,
+  0x5f,0xa3,0x9c,0x1a,0x5b,0xbf,0xce,0xdc,0x65,0x96,0xa0,0xa1,0xbe,0xef,0x25,0xe7,
+  0x36,0xef,0x51,0xef,0x61,0x6f,0x38,0xb2,0xf3,0x39,0xfd,0xf9,0x8d,0x02,0x88,0xe5,
+  0xea,0x2f,0x7b,0xab,0x38,0x5e,0x5a,0x66,0x3f,0x27,0x98,0xe7,0x41,0x6c,0x87,0xfc,
+  0x7e,0xe9,0x87,0x3b,0xf8,0x2b,0x6d,0x3f,0xe7,0xd1,0x66,0x7a,0xce,0x2d,0xdb,0x5d,
+  0xf5,0x97,0xd3,0x3b,0x5d,0x2a,0x7c,0xcb,0x8a,0xf5,0xa2,0x7e,0xd8,0xa9,0x53,0x5e,
+  0x52,0x11,0xb5,0xac,0x25,0xfe,0x6b,0x0f,0xdb,0x9a,0xbb,0xc7,0x08,0xb7,0x90,0x41,
+  0xd9,0x4c,0xa6,0x96,0xaf,0xbf,0x5c,0x1c,0xe7,0x3d,0x38,0x16,0x1a,0xe1,0xaf,0x1e,
+  0x88,0xdc,0x2c,0x9c,0xe4,0x6c,0xf3,0x23,0xa0,0xc9,0xf8,0x43,0x44,0x64,0xed,0x8a,
+  0x21,0x85,0x65,0x28,0xec,0xd0,0xee,0xf0,0x9d,0xe6,0x40,0xab,0x90,0x46,0xcc,0xd5,
+  0x5f,0x26,0xde,0x6a,0xf6,0x72,0xe2,0x65,0xf4,0x2b,0x21,0x47,0x7f,0xde,0x70,0x7b,
+  0xf8,0xaf,0xe5,0x64,0xe7,0xa7,0x0f,0x51,0xc5,0x07,0x91,0x7c,0x64,0x5e,0xd1,0x6b,
+  0xcc,0x7c,0xfe,0xd7,0x0e,0xc1,0x7f,0x35,0xc9,0x4f,0x7d,0x82,0x43,0xf0,0x76,0x01,
+  0xd0,0x18,0x17,0x85,0x86,0xff,0xca,0x9b,0x93,0xaf,0xcf,0x1b,0xc7,0xbc,0x51,0x02,
+  0x62,0x73,0x6f,0x80,0xbf,0x0e,0xc3,0x2e,0x98,0x79,0x1d,0x10,0x53,0x81,0x11,0x76,
+  0xa8,0x91,0x27,0x78,0x87,0x05,0x59,0xf6,0x59,0x12,0xa2,0x27,0x68,0xe6,0xb3,0xf1,
+  0x57,0xcb,0xb4,0x7e,0xef,0x7e,0x96,0xef,0x67,0x73,0xd3,0x94,0x40,0x44,0x59,0x06,
+  0xd1,0x73,0x7d,0x8c,0xa2,0x84,0x66,0x39,0xfc,0x75,0xd3,0x4f,0x72,0xb0,0x4b,0xdf,
+  0x6f,0x04,0x49,0x53,0x65,0x28,0x97,0x48,0x28,0x94,0x30,0x55,0x3d,0xb8,0xc7,0x3c,
+  0x04,0xa5,0xb9,0x8c,0xc2,0x65,0x52,0x88,0xde,0x14,0xd0,0x2c,0x87,0xbf,0x7e,0xcf,
+  0x0b,0xf4,0x3c,0x7d,0x02,0x64,0x89,0x32,0xe2,0xa2,0xea,0x2e,0xf6,0xcf,0xd6,0xe4,
+  0xdc,0x8d,0xf9,0xd0,0x44,0xf1,0xf2,0xb3,0x21,0xe7,0x7d,0xb6,0xeb,0x7f,0xad,0xf1,
+  0xec,0x51,0xf3,0xa3,0xc3,0x5f,0xb4,0x0d,0x96,0x7b,0xf2,0x51,0x29,0x84,0xf8,0x7e,
+  0xee,0x6f,0x99,0x85,0x8a,0x88,0x6e,0xfc,0x35,0x33,0xa6,0x6e,0x71,0xe5,0x76,0x39,
+  0x93,0x71,0x7a,0xda,0x33,0xea,0x2d,0xa5,0x42,0xcc,0x22,0x6d,0x59,0x4c,0x4f,0xdc,
+  0xb6,0xba,0xc4,0x84,0xe5,0x74,0x33,0x3a,0x30,0xb9,0xfa,0xcb,0x77,0xc1,0x8b,0x56,
+  0xed,0x5e,0x81,0xbf,0x4e,0x81,0x10,0x99,0xc7,0x75,0xc3,0xce,0xff,0x9a,0x46,0x89,
+  0x60,0x6a,0xfa,0x3e,0x21,0x4d,0x4f,0xa5,0xc1,0x2e,0x8b,0xfc,0x2f,0xbc,0x34,0xc1,
+  0x48,0x91,0x43,0x1b,0x76,0xe9,0x1f,0xf2,0x6e,0x27,0xfe,0x30,0x49,0x85,0x62,0xdd,
+  0xa7,0x46,0xba,0xcd,0x88,0x51,0xfd,0xe5,0xb5,0xf9,0xd0,0x0e,0xa9,0xb4,0x26,0xf7,
+  0xaf,0x1c,0xff,0xf5,0x19,0x5c,0x7b,0xbf,0xc1,0x71,0x35,0x3e,0x05,0xdf,0x33,0xef,
+  0x1d,0x70,0xa2,0xe0,0xf2,0x91,0x72,0x33,0xd7,0x15,0xc5,0xe0,0xfb,0x4c,0xb4,0xbc,
+  0x59,0x95,0xe4,0xf7,0x8a,0xc3,0x34,0xd8,0x20,0xa3,0xe9,0x0a,0xf8,0xaf,0xc5,0x71,
+  0x8d,0x60,0xd7,0x29,0xde,0x3d,0x22,0xf1,0x57,0xc7,0x62,0xa9,0x7f,0x78,0x10,0x11,
+  0x59,0xc9,0xc3,0xc9,0xd9,0x52,0xf6,0x50,0xe6,0x88,0x09,0xfc,0x75,0x01,0x5e,0xce,
+  0xec,0x27,0x23,0xc7,0x7f,0xed,0x71,0xb8,0xad,0x11,0xca,0x29,0x96,0x79,0x2e,0x1f,
+  0xc6,0xed,0x03,0xdb,0xef,0x50,0xd8,0xc6,0x01,0x2d,0xa7,0xe4,0x3c,0xec,0x6c,0x40,
+  0x59,0x98,0x58,0x87,0x9e,0x43,0x3a,0x8f,0xbf,0x2e,0xc3,0xc5,0xd4,0x82,0x34,0x49,
+  0x1a,0x9a,0x1f,0x39,0xfa,0x1b,0x76,0xfe,0x97,0xac,0xff,0x85,0x46,0xa3,0xf7,0x44,
+  0x22,0x96,0xdd,0x62,0xe7,0xb0,0x0c,0xd9,0x60,0x8d,0xa0,0x99,0x2b,0xff,0x0b,0x9e,
+  0xe7,0x15,0xad,0x62,0x4f,0xd9,0xa2,0x57,0x64,0x73,0x81,0xf4,0x01,0xa7,0xfe,0x17,
+  0x6e,0x5b,0x67,0xad,0x67,0xd2,0xd5,0x94,0xff,0x75,0x06,0xa1,0x2b,0x1a,0xa4,0xa4,
+  0xf1,0x5b,0xda,0xbf,0x5a,0x5d,0xfc,0x97,0x71,0xd0,0xa8,0x30,0xb5,0x07,0x70,0x08,
+  0xf6,0xe4,0x74,0x14,0x6d,0xb4,0x35,0xf3,0xa0,0x8c,0xc3,0x6f,0x6c,0x7d,0xc6,0x10,
+  0xa9,0x61,0xaf,0x4b,0x89,0x60,0x09,0xd6,0xe8,0x88,0xb2,0xe8,0x15,0x07,0x7f,0xfd,
+  0xc2,0x40,0xe4,0x6b,0x8a,0xa1,0x4c,0x98,0x90,0x8f,0x9f,0xcf,0xd7,0x4f,0x59,0xc8,
+  0x5e,0x35,0x76,0x83,0x9f,0x5a,0x2c,0xe8,0x36,0xec,0xfd,0xeb,0x49,0x3a,0x48,0xe4,
+  0xf9,0xfc,0xaf,0x9f,0xc0,0x44,0x3b,0x45,0x12,0x96,0x8f,0x78,0x3f,0x6c,0xde,0x2d,
+  0x1d,0xb3,0x6b,0x79,0x78,0xdb,0x45,0x44,0x46,0xd8,0xfb,0x21,0x13,0xfe,0xe1,0xb0,
+  0xcc,0x30,0x12,0x1c,0x99,0x21,0x52,0x0f,0x3e,0x70,0xf0,0x17,0xfa,0x09,0x96,0x40,
+  0x52,0xe8,0x67,0xaa,0x2e,0xfd,0x43,0x27,0x61,0xbc,0x37,0xb0,0xff,0xc9,0x1c,0xfe,
+  0x1a,0x9e,0x02,0xae,0x69,0xa2,0x89,0xef,0x93,0xd2,0x27,0x3d,0xd7,0xd2,0x0b,0x20,
+  0x40,0x22,0x12,0x6f,0xc3,0x7e,0xcb,0x5f,0xa0,0x7f,0xf8,0x56,0xbe,0x34,0x98,0xdd,
+  0x62,0x1b,0x83,0x9c,0xa2,0xe0,0x70,0x3d,0x34,0x9c,0xfd,0xeb,0xef,0xa0,0x9b,0x07,
+  0xe3,0x5a,0x26,0xb8,0x96,0x12,0x99,0xc5,0xcf,0xf1,0x14,0x20,0xa9,0xd2,0x48,0x70,
+  0xb3,0xde,0x29,0x43,0xcb,0xde,0x77,0x34,0x16,0xce,0xc1,0x73,0x54,0xdb,0x2b,0x77,
+  0x7e,0xc8,0xa7,0xd5,0x12,0x0b,0x33,0x20,0x3e,0xb5,0xd5,0x0c,0x5a,0xea,0x14,0x20,
+  0x56,0x23,0x13,0x82,0x7e,0x28,0x2b,0x82,0x0d,0x40,0xee,0x39,0x49,0xf2,0x33,0x77,
+  0x24,0x8c,0xfc,0xf9,0xe1,0x11,0x15,0x77,0xa2,0x48,0xe2,0x24,0x47,0x1f,0x72,0xc0,
+  0xe6,0xa9,0xe5,0xa0,0xb4,0x2f,0x30,0x71,0xc2,0xee,0x6f,0xde,0xe7,0x7d,0xd2,0x10,
+  0xd0,0x6c,0x00,0x92,0x66,0x58,0x0e,0x9c,0xd0,0xe2,0xd6,0xa3,0x2c,0x5f,0x7f,0xf9,
+  0x70,0x04,0x57,0xb6,0x2e,0x65,0xa4,0xea,0x0c,0x7c,0x53,0xfa,0x63,0x2f,0xe9,0xb1,
+  0x5f,0xad,0xca,0x4c,0x1f,0xe1,0x6f,0x99,0xc2,0x33,0x0f,0xb3,0xb7,0xd4,0x86,0xdf,
+  0x60,0xf7,0x0e,0x51,0xbd,0x80,0xe3,0x62,0x5e,0x9c,0x06,0x31,0x5e,0x39,0xfd,0x79,
+  0x51,0x16,0xd6,0x14,0x64,0xe2,0x27,0xd0,0xf4,0x5a,0x81,0x8c,0x03,0x45,0x24,0x5a,
+  0xa5,0x0f,0xe0,0x10,0x7c,0x02,0xdf,0x1d,0x10,0x28,0xe9,0x9a,0x2c,0xd6,0x3c,0x2a,
+  0xef,0x19,0x2c,0xd0,0x9f,0x27,0x49,0xf9,0x71,0xbc,0x84,0x90,0xea,0x98,0x8f,0xe6,
+  0xce,0xa4,0xc4,0x56,0x31,0x84,0x78,0x4d,0xd9,0x62,0x7b,0xc6,0x19,0x92,0x5f,0xe6,
+  0xb1,0x2c,0x29,0x88,0xc3,0xef,0xda,0x62,0x1e,0xbf,0x55,0xe9,0xe6,0xbf,0x48,0x64,
+  0xa3,0x2b,0x4a,0xdc,0xd6,0x6d,0xa3,0x22,0x11,0xac,0x9e,0x2a,0x32,0x5f,0x61,0x3f,
+  0x83,0x97,0x52,0x35,0x02,0x88,0x11,0x47,0x66,0x84,0x9c,0x1c,0x31,0x95,0x52,0xc3,
+  0x48,0xc0,0x50,0xd5,0x95,0xd1,0x29,0xfc,0x57,0x94,0x59,0x2c,0x01,0xc6,0xa0,0x94,
+  0x81,0x15,0x8b,0x5e,0xb3,0x3f,0xcf,0xb0,0x74,0xd3,0xa7,0x9c,0xa5,0x12,0x77,0x46,
+  0x2f,0x1d,0x62,0x70,0x97,0xfe,0xfc,0x4d,0x39,0xb5,0x8d,0x0f,0xa0,0x43,0x0f,0x3a,
+  0xfc,0x0e,0xcb,0x0b,0x71,0x14,0x0b,0x49,0x4c,0x56,0x3a,0xc3,0x7e,0x25,0x84,0x40,
+  0x7a,0xd0,0x78,0xae,0x28,0xdc,0xde,0xb2,0xbd,0x79,0x34,0x9f,0xff,0x25,0xb1,0x4c,
+  0xe5,0x87,0xde,0x63,0xe8,0x36,0x97,0x12,0xff,0x75,0x59,0xc4,0xee,0x52,0x52,0x95,
+  0x60,0xa0,0xfe,0x4e,0xdc,0x13,0xc9,0xe5,0x64,0xf9,0x79,0xb2,0x06,0x3e,0xf4,0xc4,
+  0xd6,0xf9,0xf7,0x2a,0x1e,0x17,0xff,0xc5,0x6c,0xf5,0x86,0xf1,0x8e,0x7f,0xb3,0x44,
+  0x20,0xe2,0x15,0xf8,0x2f,0x96,0xcc,0x1e,0x2a,0xca,0x1f,0x59,0x54,0xe4,0xcf,0x2e,
+  0x4c,0x6d,0x00,0x01,0x6f,0xcd,0xbd,0xb5,0x6f,0x94,0x17,0xd4,0x5f,0x16,0x53,0xef,
+  0x7d,0xf6,0xb2,0x99,0x71,0xce,0x49,0xea,0xf2,0xf1,0x6c,0x7f,0x4e,0x33,0xf7,0x08,
+  0xd8,0x73,0x19,0x6f,0x7e,0x07,0xdd,0xd4,0x3d,0x54,0x6c,0x6e,0xd0,0xbf,0x4f,0x4b,
+  0x5d,0xc7,0x7f,0x7d,0x62,0x1e,0x33,0x2b,0x5d,0xe5,0x18,0xa4,0x22,0x7d,0x3e,0x64,
+  0x17,0xf2,0x33,0x25,0xcd,0x2a,0x40,0x33,0x82,0xbf,0x08,0xe9,0xca,0xba,0x42,0xfe,
+  0xab,0x98,0x4a,0x63,0xa4,0x4c,0x7b,0x6f,0xca,0xe4,0x13,0x5a,0x73,0x3c,0x48,0x15,
+  0xd8,0x46,0xcd,0xa0,0x06,0x0c,0x3c,0x4a,0xda,0x20,0x97,0xc6,0x15,0x7f,0x78,0x30,
+  0x2d,0x7c,0xfe,0xdf,0x08,0x6e,0x4b,0x2c,0xd4,0x19,0x5e,0x31,0xac,0xad,0x77,0x17,
+  0x08,0xfe,0x3e,0xaf,0x0e,0x09,0xa4,0xb0,0x88,0x16,0xea,0x06,0x74,0x57,0x36,0xa4,
+  0x2a,0xaa,0xd4,0xfb,0xd9,0xc3,0x85,0xfc,0x57,0x49,0xa4,0xbc,0x37,0xfe,0x9a,0x69,
+  0xd7,0xff,0x3a,0x8f,0xdb,0x96,0xd4,0xdf,0xa0,0xd2,0xcc,0xf5,0xca,0x49,0xf3,0xa2,
+  0xde,0x18,0x9a,0x2e,0x5b,0xc2,0xa4,0xdf,0x9b,0xf0,0xbe,0x9c,0xca,0xac,0x0f,0xdf,
+  0xac,0x6c,0x73,0xf1,0x5f,0xf2,0x10,0x23,0x4b,0xcb,0xe9,0x6f,0xa6,0x8b,0x20,0x43,
+  0x8a,0x2d,0x3c,0x9f,0xc4,0x05,0xb6,0xac,0xa9,0xff,0xd6,0x51,0x71,0xc0,0x15,0x03,
+  0x7b,0xbc,0x84,0x46,0x47,0x96,0x46,0x79,0x59,0xed,0xe8,0xf5,0xfc,0x97,0x08,0xaa,
+  0x69,0xb0,0x49,0x2e,0x4e,0x0b,0x1a,0x3e,0x67,0xc2,0xd9,0x10,0xc5,0x73,0x9c,0xf7,
+  0x27,0x4c,0xf5,0xd6,0x27,0x28,0x5e,0x34,0xbd,0xe2,0x7a,0xfe,0x4b,0x57,0x2f,0x52,
+  0xf1,0x3b,0x8a,0x96,0x7f,0x5e,0x1c,0xf7,0xd1,0x06,0xb4,0xc6,0xde,0xe8,0xbf,0xef,
+  0xaa,0xbf,0x4c,0xb4,0x97,0xee,0x7d,0x09,0x2a,0xdb,0xfc,0xf1,0xa9,0xfc,0x17,0x76,
+  0x66,0xb9,0xf7,0x05,0x41,0x72,0x95,0xbd,0xed,0xe9,0xce,0xe1,0xaf,0x74,0x75,0xf6,
+  0x0b,0x52,0x76,0xbe,0xda,0xc8,0x09,0x71,0xa8,0xf5,0xcd,0x65,0x94,0x8b,0x37,0x5a,
+  0x5c,0xcf,0xa6,0xf0,0x5f,0x88,0xb6,0x14,0x78,0xce,0x10,0xf8,0x8b,0xde,0x04,0xd5,
+  0x99,0x9e,0xf9,0x94,0x8a,0xd6,0x1c,0x11,0xa6,0xde,0x5e,0xe6,0x81,0x23,0xde,0xaa,
+  0x51,0xb5,0xfe,0x7a,0xfe,0x4b,0xbb,0xcb,0x7c,0x31,0x47,0x72,0x59,0x51,0x74,0x96,
+  0x44,0xfd,0xe5,0x18,0x2f,0x96,0xfc,0xd7,0xe2,0x54,0x4e,0x88,0xc3,0x9f,0x55,0xea,
+  0xcd,0xcb,0xf8,0x0a,0x94,0x64,0xb5,0x42,0xfe,0xcb,0xe3,0x4e,0xfb,0x8a,0xab,0xe8,
+  0xe9,0x49,0xb6,0xeb,0x0c,0x94,0x4a,0xd8,0x85,0xb8,0xc0,0xeb,0x92,0x9d,0x4f,0x8a,
+  0x9b,0xcb,0x02,0x9e,0xa9,0xf9,0x5f,0x88,0xb6,0xe6,0xc2,0x31,0x7d,0x6a,0xd9,0x2f,
+  0x37,0x05,0xb0,0xd4,0x49,0x0d,0x5b,0x87,0xc6,0xdc,0x65,0xe3,0x66,0x34,0x1e,0xbe,
+  0x41,0xfd,0xe5,0xb2,0x2a,0xb6,0x71,0x20,0x2a,0x9d,0xe4,0xf7,0x25,0x5c,0x72,0xf0,
+  0x97,0x92,0xd3,0xb8,0x13,0x2d,0x71,0x35,0xe5,0x9b,0x43,0x1c,0xc7,0xba,0x96,0xd4,
+  0xd4,0xfc,0xaf,0x4e,0x74,0xda,0xcd,0xa7,0xe0,0x6b,0xee,0x8f,0x97,0x0d,0x79,0x0a,
+  0x28,0x12,0x99,0x1a,0xe6,0x09,0xa3,0x51,0x36,0xc7,0x7b,0x08,0x8c,0x16,0x75,0x07,
+  0x2b,0x92,0xfb,0x8e,0xc3,0x7f,0xdd,0x72,0x93,0xcf,0x6b,0xb6,0xe9,0x69,0xe9,0xf3,
+  0xef,0xb4,0xeb,0x02,0x3b,0x70,0x80,0x94,0xd2,0x6b,0x1c,0x5e,0x66,0x6d,0x5c,0xa5,
+  0xf8,0xc3,0x6e,0x48,0x0f,0xa8,0x37,0xfb,0xa6,0xf0,0x5f,0x9a,0x57,0xa9,0xd8,0x79,
+  0x66,0x4d,0x9d,0xcd,0x7f,0x85,0x6a,0x10,0x5b,0xb5,0x09,0xfc,0x95,0x87,0xb7,0x22,
+  0x47,0x6c,0x3d,0xe9,0x82,0x8a,0x88,0xb2,0xff,0x1a,0x9d,0xe1,0x7f,0x74,0x69,0x0d,
+  0x93,0xf8,0x2b,0x57,0x7f,0x59,0xb9,0xc4,0x7f,0x6e,0x90,0xe6,0x83,0x87,0x72,0xb2,
+  0x66,0xdb,0xdd,0xeb,0x99,0x4d,0xac,0xe2,0x1e,0xf4,0xf0,0x9b,0x2c,0xa7,0xc3,0x97,
+  0x07,0x7e,0x55,0x79,0xc9,0x1c,0x87,0x26,0x17,0xff,0xe5,0xd4,0x5f,0x2e,0x25,0x48,
+  0xf5,0xef,0x1e,0xbb,0x9f,0x85,0xe6,0xf9,0x75,0x99,0x4a,0x12,0x4a,0x7b,0x05,0x58,
+  0x5b,0x08,0xaf,0x7a,0x49,0x7f,0x43,0xbb,0x1e,0x7f,0x59,0x42,0xd2,0x30,0x07,0xbb,
+  0xa6,0x32,0x62,0x35,0x4e,0xfc,0x61,0x58,0x30,0x62,0x8c,0x43,0xd0,0x83,0xeb,0xd8,
+  0x0d,0xf8,0x2f,0x75,0xbf,0x37,0xed,0x80,0x2c,0x47,0xe7,0x04,0x47,0xe7,0x16,0xd9,
+  0x52,0x63,0xce,0xcf,0xe3,0x2f,0x5f,0x91,0xc0,0x5f,0x21,0xfd,0x46,0xfc,0x97,0xf1,
+  0xaf,0x7a,0x30,0xcf,0x7f,0x91,0xe1,0x2d,0x18,0x77,0xb7,0x34,0xc7,0x5c,0xa1,0xda,
+  0xd1,0xb2,0xfd,0xc6,0xfc,0x17,0x8f,0xda,0x05,0xbc,0x5a,0x1a,0x44,0x44,0x62,0xb1,
+  0x2d,0xbb,0x21,0x5f,0xe3,0x9c,0x22,0x07,0x22,0xa9,0x39,0x14,0x9a,0xb8,0xc6,0x9f,
+  0xd2,0x6e,0x50,0x7f,0x59,0x7f,0x43,0xb5,0xe3,0x72,0xcf,0xa7,0xaf,0x97,0xa3,0x11,
+  0xd3,0xc1,0x51,0x44,0x54,0xfa,0x55,0xc9,0x60,0x2e,0xbd,0x9e,0xff,0xaa,0xe0,0x16,
+  0x42,0x57,0x89,0xbf,0xcc,0x9c,0xfe,0x61,0x57,0xae,0x72,0x84,0x9e,0x2b,0x21,0x41,
+  0x62,0x89,0xa4,0x88,0x48,0xf5,0xbb,0xdd,0xfc,0x97,0x2c,0xa9,0x7c,0x97,0xf7,0x09,
+  0x84,0x54,0x94,0xff,0x35,0xf3,0xb0,0x04,0x59,0xc3,0x5e,0x5b,0x91,0x9e,0xf8,0xaf,
+  0xb0,0xd3,0x52,0x4b,0x1a,0x89,0xa4,0x3f,0x4f,0xfa,0x87,0xc9,0xe5,0xf9,0xfc,0x2f,
+  0x5b,0x2c,0xc8,0x0f,0xdc,0xac,0xba,0x81,0x1f,0x9e,0x53,0x26,0x77,0x8c,0x3e,0x11,
+  0x74,0x4d,0xfe,0xa1,0x3a,0x93,0x4d,0xe5,0xbf,0xbe,0xc3,0x6e,0xc2,0xe7,0x48,0xd9,
+  0x79,0x4f,0xb7,0x13,0x1f,0xde,0xfd,0x58,0x8e,0xff,0xfa,0x86,0x6d,0xb0,0x6f,0xa4,
+  0x11,0x3b,0xf8,0x0d,0x3a,0x1f,0xeb,0x30,0x83,0xee,0xfa,0xcb,0x84,0xad,0xc6,0x95,
+  0xd9,0xd0,0xcf,0xef,0x70,0xf8,0xaf,0xe7,0x1d,0x46,0x8c,0x84,0xe8,0x3d,0x52,0x7f,
+  0xa3,0x54,0xb6,0x54,0x67,0xfd,0xf5,0xca,0xcd,0x08,0xc4,0x22,0xe9,0xf0,0x3d,0xca,
+  0x75,0xf5,0x97,0x65,0x1f,0x3a,0xee,0x01,0xc5,0xb3,0xa1,0x03,0x43,0x3a,0xc9,0xd7,
+  0xa5,0x1a,0x71,0x61,0xd8,0xf9,0x44,0xae,0xfc,0x2f,0xc1,0x7f,0x8d,0x2b,0x57,0xcd,
+  0x57,0xf9,0x22,0x97,0xfe,0xc6,0x05,0x91,0xed,0xb5,0x60,0x48,0xc1,0x4b,0xde,0x6b,
+  0x89,0xc5,0x43,0xa5,0xa2,0x34,0x33,0x5e,0x7a,0xe2,0x10,0x5e,0x3a,0xbd,0xed,0xd6,
+  0x21,0xff,0x98,0xc7,0xad,0x7f,0xc8,0xab,0x29,0xc8,0xf0,0x2a,0xfc,0x18,0x8c,0xac,
+  0x7d,0x6c,0x28,0xea,0x7f,0xcd,0x86,0x45,0xba,0x5d,0xff,0xeb,0x60,0x3a,0x4c,0xf5,
+  0xbf,0x70,0x03,0xd2,0x6b,0xf7,0xaa,0xf5,0xca,0x29,0x9e,0xa0,0x1f,0xa8,0x26,0x0a,
+  0xf2,0xbf,0xc4,0x66,0xf7,0xba,0xd1,0xee,0x84,0x7f,0x88,0x9e,0x8f,0x88,0xa8,0xce,
+  0x9d,0xd6,0x0a,0x29,0xdf,0x51,0x3b,0x20,0x64,0x37,0x08,0x7f,0xe1,0xc0,0x7d,0x2e,
+  0x41,0x75,0x30,0x8b,0x1f,0x28,0xd4,0x9f,0x17,0x55,0xde,0xfa,0x61,0x6f,0xca,0x09,
+  0x3b,0xb4,0x72,0xc2,0xe6,0x46,0x4e,0xe7,0xed,0x82,0x3d,0xee,0x88,0xe8,0x89,0x61,
+  0xa1,0x88,0x05,0xf5,0xe6,0x02,0xfe,0xcb,0x23,0x9c,0x76,0x3a,0x3b,0x3d,0x2c,0xd2,
+  0x52,0x3c,0x36,0xc8,0xda,0xe7,0xc9,0x1d,0xd4,0x63,0xf7,0x8e,0x3a,0x48,0x8a,0x97,
+  0x1e,0x60,0xd5,0x14,0x0c,0xbc,0xa4,0x64,0xbb,0x52,0x58,0x7f,0xd9,0x52,0x70,0xbc,
+  0x42,0x13,0x2d,0x65,0xb6,0x5f,0xa7,0x0b,0x46,0x6c,0xad,0xd7,0x3d,0x4c,0xfd,0xf9,
+  0xf1,0xda,0xaf,0xec,0x83,0x31,0x4f,0x4c,0xaf,0xcd,0xe1,0x2f,0xa7,0xfe,0xf2,0xaa,
+  0x51,0x74,0xd1,0x8f,0xc3,0xed,0x32,0xff,0xeb,0x9a,0xba,0x80,0xfc,0xcc,0x87,0xa5,
+  0x4b,0xe3,0xb8,0x97,0x7e,0x69,0xd4,0x82,0x7f,0x9d,0x06,0x94,0xff,0xe5,0xc5,0xf9,
+  0xee,0xaa,0xff,0x65,0xfb,0x87,0x06,0xdf,0x94,0xce,0xe1,0xa6,0x3a,0x09,0x97,0x1c,
+  0x00,0xa5,0x53,0x48,0xe1,0x72,0x5b,0xba,0x6d,0xbb,0x2f,0xc3,0xaa,0xa0,0x63,0x30,
+  0xa8,0xe3,0x8e,0x56,0x51,0xc8,0x7f,0xe1,0x25,0x15,0x36,0xa1,0xdb,0x53,0x9c,0x2f,
+  0xfb,0x55,0xa8,0x48,0x3f,0x5f,0x52,0x24,0x47,0xa8,0x7c,0x58,0x86,0xdd,0x8f,0xa0,
+  0x6f,0x7e,0x9f,0xe0,0xbf,0x6c,0xfc,0xe5,0x77,0x70,0x81,0xca,0x93,0x10,0x97,0x45,
+  0x6d,0x68,0x9e,0x92,0x2e,0x04,0x97,0xa5,0x99,0xa9,0xc5,0xa8,0x39,0x49,0xe3,0x65,
+  0x60,0x4b,0xdb,0xf2,0x48,0xa2,0x04,0x78,0xd0,0xe0,0x7b,0x67,0x26,0x0a,0xf4,0xe7,
+  0x11,0xd5,0x8e,0x26,0x0c,0x3e,0x00,0x5d,0xfd,0xd2,0xfb,0xd2,0xa3,0xfd,0x92,0xbf,
+  0x30,0x1d,0x9d,0xff,0x50,0xec,0xb8,0x5f,0xcc,0x14,0x33,0xe6,0xf7,0xbf,0xa0,0xfc,
+  0xbd,0x71,0xbc,0xbe,0x67,0xd6,0xe6,0xd4,0x52,0x57,0xfd,0xaf,0x89,0xbf,0x17,0x9c,
+  0x66,0xd6,0x9c,0xcc,0xd5,0x87,0x35,0xa8,0xfe,0x97,0xb2,0xcf,0x94,0xd2,0x88,0xcd,
+  0x82,0x11,0x1b,0x10,0x3e,0xff,0x77,0x21,0xd6,0x1e,0xb8,0x90,0xdc,0x47,0xa2,0x55,
+  0xfe,0x40,0x2a,0xe9,0xc6,0x5f,0x89,0xa6,0xec,0x96,0x71,0xdc,0xbf,0x3e,0x81,0xbb,
+  0x72,0x81,0xbe,0xf2,0x9c,0xff,0xf7,0x94,0xb8,0x97,0xc5,0xdd,0xea,0xb4,0x14,0xba,
+  0x89,0xc0,0xe9,0xc4,0x22,0xe7,0x9e,0xbb,0x38,0x22,0xb2,0xbc,0xfe,0xbc,0x2a,0xe2,
+  0x0f,0xbb,0xd8,0x10,0xa7,0xd8,0x42,0xcd,0x41,0x5b,0xd0,0xc1,0xde,0xa1,0x1d,0xcd,
+  0x50,0x79,0x62,0x2e,0x3c,0x47,0xf7,0xd0,0x36,0xf1,0x5c,0xee,0x1e,0x7a,0x9f,0x73,
+  0xfc,0x97,0x2b,0xfe,0xf0,0xa4,0xb1,0x33,0x1f,0x8e,0x5b,0x03,0x3e,0x60,0x14,0xc7,
+  0x18,0x02,0xb5,0xac,0xcc,0x4f,0x32,0xe6,0x78,0xa9,0x4c,0x85,0x64,0x91,0x2b,0x79,
+  0x56,0x75,0xeb,0xcf,0xe7,0xc4,0x63,0xf9,0x46,0x1c,0xf7,0x15,0xe2,0x6d,0x61,0xf6,
+  0xee,0x29,0x45,0x83,0x9b,0xc3,0x32,0x23,0x8c,0xc2,0x75,0x76,0xc3,0xfc,0x5e,0x07,
+  0x68,0x70,0xd5,0xad,0x3f,0xef,0xb7,0x59,0xfb,0x77,0xe0,0x43,0x2b,0x27,0x47,0xd3,
+  0x28,0xcf,0x25,0xa8,0x5a,0x93,0xfa,0xd3,0xe9,0x35,0x44,0x3d,0x0f,0x05,0x32,0x5a,
+  0x88,0xbb,0x34,0x09,0x1b,0x48,0xa5,0xd0,0x72,0xc7,0x1f,0xd6,0xd2,0xcb,0x7f,0x09,
+  0xfe,0xe8,0x9a,0x05,0xe6,0xaa,0xac,0x1d,0x91,0x58,0xdb,0x72,0xdb,0xbf,0x7b,0xae,
+  0xa5,0xe9,0xd2,0xf4,0xb3,0xfa,0x35,0xd5,0x49,0xa2,0xc4,0x99,0x5b,0xa8,0xbf,0x91,
+  0x9b,0x8c,0xc7,0x4d,0x79,0xf0,0x02,0xdf,0x81,0x06,0x3e,0xcd,0x49,0x78,0x09,0x6c,
+  0xd7,0xc2,0x06,0xae,0x09,0x83,0x61,0xaa,0xe4,0x75,0x42,0x8f,0x3a,0x35,0x01,0x1b,
+  0x29,0x02,0x79,0x30,0x8f,0xbf,0xee,0x82,0x52,0x19,0x85,0xbb,0xc9,0xb0,0xd1,0x16,
+  0xe9,0x3a,0xaa,0x69,0xf1,0x1a,0x07,0xad,0x27,0x38,0xab,0x35,0x8e,0x38,0x69,0x95,
+  0x9d,0x66,0x5d,0x6f,0x3e,0xd0,0x17,0xfb,0xa7,0x00,0x7f,0xd1,0x62,0xd5,0x4f,0x52,
+  0xd5,0xce,0x58,0x50,0xb4,0x46,0xf4,0xa4,0x6a,0xcb,0x54,0x9e,0x96,0x84,0x48,0xa6,
+  0xd9,0x84,0xa4,0x95,0x3b,0x6b,0x0a,0xf7,0xa3,0x71,0xd9,0xad,0x3f,0x2f,0x70,0xc1,
+  0x6f,0xf8,0xf7,0x1c,0xfc,0xf5,0x0c,0xaf,0x35,0x80,0xd4,0xe6,0x8f,0xf2,0x79,0x86,
+  0x9d,0x1a,0x56,0x3b,0x0c,0xf7,0x40,0x33,0x62,0xb4,0xcf,0x0f,0x38,0x22,0x12,0x06,
+  0x1a,0x93,0x85,0xf8,0x4b,0x6b,0x50,0xde,0x83,0x37,0xcc,0x88,0x84,0x5d,0xdd,0x7a,
+  0x3d,0x94,0xc0,0xd2,0x3e,0x6b,0x14,0xbd,0xc1,0xc0,0x76,0x76,0xd2,0xfc,0x56,0x66,
+  0x21,0x85,0x02,0xb6,0xb0,0x97,0xf5,0xe8,0x88,0xa3,0x7f,0xc8,0xfd,0x91,0xa9,0xfa,
+  0xf3,0x22,0xfe,0xf0,0xa3,0xdc,0x78,0x51,0xe1,0x80,0x41,0x65,0xd4,0x1c,0xf3,0x2c,
+  0x82,0xd2,0x4b,0xe5,0x54,0x2f,0x60,0x71,0x7f,0x60,0xb0,0xbc,0x07,0x2e,0x7a,0x05,
+  0x07,0x8d,0xd0,0x4c,0x17,0x93,0x71,0x2a,0xfe,0xea,0x51,0x0c,0x3a,0x87,0x74,0xed,
+  0x7a,0xf5,0x76,0xf0,0xf6,0x13,0x42,0x2f,0xc5,0x23,0x2e,0x85,0x0a,0x36,0x44,0x28,
+  0xa8,0xbf,0x2c,0x77,0x99,0x51,0xb6,0x10,0xda,0x5d,0x81,0x2e,0x4b,0x72,0xfa,0xf3,
+  0xea,0xba,0x22,0x69,0x74,0xae,0xf3,0x3d,0xed,0x0e,0x86,0xa9,0xe5,0xe8,0x0c,0x5c,
+  0xb8,0x0e,0x7f,0x7d,0x56,0xdd,0xd3,0x91,0x97,0x3d,0x4c,0x6b,0x03,0x89,0x6d,0xc6,
+  0x01,0x5e,0x5b,0xe1,0x3b,0xc3,0xbe,0x12,0x11,0xf7,0xd4,0xb3,0x9b,0x55,0xb7,0x34,
+  0x22,0xf5,0x73,0xf6,0xba,0xf8,0x43,0xf4,0x5b,0xe2,0xb9,0x39,0x58,0x3d,0x8a,0x37,
+  0xff,0x89,0x1d,0x81,0x13,0x2c,0xa5,0xdc,0x8a,0x88,0x76,0x3b,0xdb,0x02,0xdd,0xde,
+  0x9c,0x36,0x8b,0x10,0xeb,0x70,0xe5,0x7f,0xd9,0xd5,0xbe,0xea,0xe1,0x63,0x2b,0x2f,
+  0x7b,0x98,0x58,0x95,0x56,0x9e,0x83,0xcb,0xa3,0xb1,0x03,0xa5,0x69,0xa5,0x05,0x2e,
+  0xa7,0x9b,0xf6,0x04,0xf6,0x2a,0x0d,0x6d,0xae,0xd4,0xb0,0xef,0x66,0x36,0xa7,0xf3,
+  0xf9,0x5f,0x37,0x56,0x51,0x5b,0xac,0x06,0x2c,0x65,0x90,0x5f,0x32,0x17,0x7b,0x03,
+  0xa6,0x26,0xd4,0xe6,0x09,0x7f,0x59,0x86,0x5b,0x04,0xc0,0x5b,0x7b,0x9d,0xfe,0x06,
+  0x39,0x93,0x46,0xaf,0xbb,0xec,0xf2,0x2c,0x91,0x2f,0x23,0xd4,0x36,0xa6,0x57,0x99,
+  0x94,0xd2,0x45,0x15,0xc1,0x3c,0x79,0xcd,0x3d,0x4f,0xdd,0x7d,0xfe,0xeb,0xf4,0xe7,
+  0x65,0x90,0x21,0x77,0x95,0x5d,0x96,0x8a,0x76,0x69,0x5b,0x51,0xfc,0x0d,0xa7,0xb4,
+  0xd3,0x1b,0x66,0x43,0xce,0xc7,0x8e,0x97,0xa4,0xd8,0x14,0xfd,0xf9,0x15,0xa9,0xb2,
+  0x7e,0xd8,0x68,0xb8,0x9e,0x53,0x3c,0xca,0x2e,0xc1,0xe3,0x7a,0xa5,0xe9,0x1b,0x14,
+  0x82,0xe4,0xf7,0x5b,0x22,0x11,0x4c,0x06,0x34,0x16,0xd1,0x3d,0x73,0xfb,0x49,0x87,
+  0x7c,0x4a,0xfc,0xe1,0x4d,0xac,0xff,0x9d,0xb6,0x90,0x61,0xc3,0x01,0x56,0xbd,0xbc,
+  0xe2,0xee,0xc4,0xeb,0xbb,0x1e,0x0d,0xed,0x5c,0x3e,0xff,0xaf,0x36,0xf9,0xd3,0x5b,
+  0x3d,0x6b,0x89,0xed,0xf2,0xf2,0xb6,0x1c,0x64,0x00,0x63,0x79,0x71,0xa1,0xfe,0x3c,
+  0x75,0x5d,0xbb,0x72,0x8e,0x0f,0x18,0x5d,0xb9,0x0e,0x57,0x8b,0x13,0x44,0x52,0xac,
+  0x8b,0xaa,0xbe,0x57,0x98,0xd1,0x3e,0x00,0xb3,0x89,0xed,0x8a,0xb3,0x4d,0xad,0xf9,
+  0x5c,0x3c,0xd5,0xcf,0x97,0xe6,0xf8,0xaf,0x9c,0x8b,0x7e,0x89,0x5f,0x99,0xef,0x72,
+  0xe3,0x73,0x28,0xa0,0xa4,0x4c,0x21,0x39,0x47,0x84,0x4b,0xaf,0x25,0x2f,0xb5,0x3a,
+  0x90,0xca,0x3b,0x3e,0xaf,0xe9,0xb8,0x9b,0xff,0x72,0x39,0xff,0x57,0x0a,0xcb,0x64,
+  0x2b,0x7b,0xbc,0x1f,0x41,0x84,0x8c,0x07,0x85,0x52,0xba,0xb8,0xf4,0xaa,0xa8,0x14,
+  0x5c,0x39,0x24,0x0a,0x31,0x93,0xca,0xe5,0x0d,0xe3,0x0f,0x0b,0x61,0x97,0xe1,0x20,
+  0x32,0x19,0x7f,0xa8,0xc8,0x1d,0x64,0x97,0xb8,0x47,0xdf,0x2b,0x11,0xd9,0xa9,0xeb,
+  0xf1,0x97,0x08,0x63,0xcb,0x93,0x5c,0x24,0x4a,0xb9,0x93,0x5a,0x52,0xcc,0xeb,0x75,
+  0xd1,0x5e,0x02,0x02,0x4b,0xb1,0xc4,0x8e,0xeb,0xf4,0xe7,0xa9,0xa6,0x36,0x27,0xde,
+  0xd3,0x19,0xf7,0xff,0x4b,0xfb,0x1e,0x9b,0xc3,0x93,0x66,0xb0,0x55,0xa3,0x2c,0xbf,
+  0x43,0xfa,0xfd,0x2d,0x74,0x89,0x77,0x3a,0xb5,0xe1,0xec,0x64,0x31,0x97,0xfe,0x86,
+  0x1d,0xe7,0xf9,0x9e,0x3e,0x6e,0xd9,0xf5,0x97,0x45,0xcb,0x4c,0xa5,0x1d,0xde,0x87,
+  0xae,0xb8,0xb6,0x43,0xa9,0x5a,0x32,0xee,0xa9,0xb9,0x9b,0xee,0x61,0x6d,0xa2,0x7f,
+  0xe8,0x55,0xf7,0xc4,0xd6,0x85,0xa7,0xea,0x6f,0xd8,0xdd,0x5b,0x00,0xbb,0x76,0x10,
+  0x0b,0x9c,0x46,0x90,0xb5,0x4d,0xf9,0x89,0x13,0x76,0xf8,0x4a,0x01,0x22,0x23,0x72,
+  0xf3,0x7a,0xfc,0x75,0x0e,0x06,0x4c,0x97,0xec,0x7c,0x69,0x3b,0x15,0xf2,0x56,0xa3,
+  0x02,0xb6,0xb7,0x0e,0x40,0xcc,0x2d,0xcd,0xb1,0x34,0xeb,0x54,0x0d,0xbb,0x51,0xfc,
+  0xe1,0x9b,0x6c,0x57,0x81,0xec,0x61,0x08,0x5e,0xec,0x0f,0xb6,0xb5,0x18,0x6c,0x1c,
+  0x9e,0x85,0x06,0x49,0x8d,0xbd,0x98,0x76,0x05,0x2b,0x62,0x8b,0x6f,0x2a,0xfe,0x72,
+  0x28,0x2d,0x17,0xda,0x42,0x97,0xcf,0x32,0xa8,0x8e,0xc6,0x31,0x9e,0x04,0x57,0x8e,
+  0x98,0x16,0x91,0xa5,0x99,0xb3,0xa1,0xc8,0x75,0xf8,0xeb,0x5b,0x65,0x6f,0xf3,0xad,
+  0x50,0x51,0x80,0x0b,0x66,0xc1,0x7e,0xb5,0x32,0xeb,0x7b,0x80,0xbd,0x09,0xcf,0xc0,
+  0x7f,0xcf,0xaa,0x0f,0x88,0xf8,0xf0,0xfc,0x1a,0x3e,0xa8,0x3e,0xe4,0x0b,0x5d,0x17,
+  0x7f,0x78,0xca,0xb2,0xb9,0x2d,0x07,0x6d,0x31,0xba,0x24,0x48,0xae,0x37,0xf5,0x5f,
+  0xb6,0xfd,0x49,0xb6,0xea,0xe1,0x82,0xd2,0xcc,0xbc,0x29,0x1e,0x9e,0xbc,0x01,0xfe,
+  0xfa,0xc8,0x1a,0xb7,0xf7,0x94,0xbc,0x1b,0x4f,0x2d,0x25,0xdd,0xbf,0x1e,0x70,0xee,
+  0x59,0xeb,0xda,0x77,0xf4,0xd8,0x92,0x7c,0xfe,0x97,0xd0,0x9f,0x27,0xfc,0x35,0x49,
+  0x90,0x2a,0x25,0xf4,0xd9,0x5e,0xc4,0x16,0x61,0xc4,0xe0,0x54,0xea,0x2e,0x4a,0x5d,
+  0x79,0xd3,0xc4,0x4b,0x43,0xe2,0xd2,0xb5,0x6d,0xb7,0xe6,0x7c,0x48,0xd2,0xa8,0x1f,
+  0x74,0xeb,0xcf,0x57,0xcb,0xfd,0xe2,0xd1,0x48,0x78,0x44,0x96,0x4b,0xe6,0x82,0xed,
+  0xf2,0xc3,0xe6,0x3d,0xd8,0x63,0x0f,0xf9,0x66,0x5a,0xbf,0x86,0x70,0x56,0xec,0x68,
+  0x07,0xd2,0xe1,0xdc,0xfe,0x45,0x89,0xcc,0x1f,0xb8,0xf4,0xe7,0x73,0x1a,0xbf,0xa6,
+  0x00,0xb3,0xd8,0x12,0xac,0x26,0xd6,0x63,0x96,0xb9,0xc1,0x98,0xd7,0xa7,0x3d,0xc0,
+  0x76,0x78,0x37,0xa8,0xdf,0x38,0x29,0x2f,0xb9,0xfa,0xb9,0x19,0x9f,0xd3,0xef,0x8a,
+  0x3f,0x14,0x5b,0x52,0x59,0xc0,0x6a,0x6b,0xcf,0xfb,0x90,0xa3,0x5a,0x3d,0x3a,0xed,
+  0x49,0xd3,0x18,0xd5,0x5e,0x0c,0x02,0xd5,0x36,0x3d,0xa9,0xdd,0xc9,0x4a,0x68,0x0a,
+  0xdb,0xfb,0x97,0xa7,0x26,0x8e,0x6f,0xc2,0x99,0xbc,0xfe,0xbc,0xcc,0xfa,0xd1,0x1a,
+  0xd9,0x09,0x43,0xc2,0x2e,0x3a,0xfd,0x7e,0x2f,0x70,0xf4,0x96,0x1a,0x76,0x62,0xa0,
+  0xa1,0x3f,0x70,0x55,0xd9,0x0b,0x27,0xda,0x63,0xa3,0xda,0x18,0x73,0x39,0x6f,0xe8,
+  0xd7,0x3d,0x88,0x08,0xe8,0xe3,0x29,0xfa,0xf3,0xce,0xe8,0xe4,0xfd,0x04,0x84,0x03,
+  0xd6,0x84,0x60,0xc4,0x2a,0xf3,0xb4,0x57,0xfb,0xe5,0x9c,0x58,0x87,0x57,0xb0,0x9c,
+  0x53,0xe2,0x0f,0x57,0x8d,0xa2,0x4b,0xf3,0xcb,0x7c,0x22,0xd8,0x62,0x42,0x5b,0x6b,
+  0xe1,0x6a,0xc2,0xae,0x54,0x45,0xd2,0xf4,0xa5,0x11,0xa1,0xbf,0xb1,0xc0,0x9a,0x6e,
+  0xc7,0x28,0x0e,0xaf,0x1c,0x55,0xb2,0x39,0xfc,0xa5,0x4a,0xff,0x39,0x38,0xa2,0x93,
+  0xff,0x5c,0x90,0xc8,0x03,0x3d,0xfd,0xc2,0xb5,0xd6,0x12,0xbb,0x99,0x70,0xad,0xc3,
+  0x9e,0xc3,0x96,0x0c,0x2d,0xf3,0x12,0xb6,0x12,0x15,0x99,0xaf,0x8f,0x3f,0xec,0x84,
+  0x29,0xcf,0x51,0x0f,0xeb,0xe2,0xd2,0xd7,0x6d,0x44,0xd6,0x1c,0xd6,0xbb,0xf9,0x7d,
+  0xb2,0x22,0xb3,0x88,0x75,0x74,0xe5,0x7f,0xf9,0x89,0x82,0x14,0x43,0xc0,0xd0,0xcf,
+  0x3c,0x63,0xa3,0xad,0xf0,0x31,0x31,0x2b,0xbb,0x6c,0x68,0xc6,0x8e,0x40,0x1a,0xdf,
+  0x84,0x90,0x1f,0xba,0x0c,0xc8,0x1d,0xa1,0x98,0xf3,0x72,0xf9,0x5f,0x22,0xfe,0x70,
+  0x3d,0xf6,0xe1,0x37,0x95,0x2b,0xb8,0x89,0x47,0xa5,0x0a,0xcd,0x84,0x11,0xeb,0x0b,
+  0x8b,0x28,0xdc,0x60,0xcc,0xda,0xb2,0xee,0xbf,0xac,0x21,0x21,0xbb,0xb7,0x03,0xa4,
+  0x97,0x72,0x38,0xe4,0x20,0x68,0x52,0x91,0xc5,0x7e,0x76,0xe9,0x6f,0x48,0x4a,0x6b,
+  0x92,0xf4,0xe7,0x05,0xfe,0xf2,0x08,0x59,0x00,0x34,0x42,0x97,0x67,0x34,0x59,0x5b,
+  0x2e,0xa1,0xd3,0xfe,0x49,0xa8,0x69,0x40,0x48,0x50,0x5e,0x86,0xa6,0xbe,0x9c,0x28,
+  0x4a,0x61,0xfe,0x97,0x10,0x39,0xb4,0x94,0x08,0x0e,0xdd,0x02,0x72,0x2f,0x63,0x70,
+  0xad,0xbd,0xe9,0xe5,0x92,0x31,0xdc,0xfe,0x4e,0x52,0x46,0x21,0x55,0x4b,0x39,0x4d,
+  0x97,0x5c,0xd4,0xf3,0x25,0xe2,0x97,0x71,0x28,0x6f,0x73,0xf1,0x5f,0x24,0xa9,0xa1,
+  0x72,0x5c,0x49,0x0e,0xb1,0x60,0x6f,0xe7,0x0e,0x26,0xf4,0xe7,0x47,0x11,0x64,0x0d,
+  0xb1,0x0e,0x1e,0xcc,0x86,0x52,0xc1,0xb9,0xc4,0x2a,0xe6,0xa0,0x19,0x19,0x96,0x2a,
+  0x5a,0x32,0x65,0x2e,0xfd,0x0d,0x12,0xcd,0x2b,0x36,0x70,0x1d,0xc1,0xad,0x9f,0xb2,
+  0xb4,0xfc,0xf9,0x15,0x32,0x21,0x96,0xc1,0x3f,0xf3,0xe3,0xa7,0x0c,0x70,0x2f,0x95,
+  0x24,0x56,0x3f,0x4c,0x43,0xe9,0xd2,0x3f,0xec,0xa1,0x70,0x82,0xbd,0xec,0x36,0x72,
+  0x69,0x46,0x3b,0x3b,0xf2,0xfa,0xf3,0xef,0x51,0x90,0x0f,0x49,0x85,0xd4,0xcc,0xa7,
+  0x57,0x62,0x85,0x8b,0x09,0x3d,0x07,0x49,0xf6,0x75,0x32,0x22,0xf9,0xfc,0xaf,0x31,
+  0x12,0x39,0x3c,0xac,0xdc,0x86,0x46,0x57,0x7a,0x55,0x8f,0x26,0xb3,0xbd,0x10,0x38,
+  0xff,0xde,0x38,0x46,0x6c,0x57,0x87,0xf6,0x79,0xef,0x89,0x54,0x57,0x8e,0x6f,0x22,
+  0x68,0xf6,0x9e,0x79,0xc2,0x8b,0x60,0xed,0x33,0x79,0xfd,0xf9,0xa3,0x70,0x5e,0xc8,
+  0x81,0x2e,0x18,0x83,0x2b,0x69,0x19,0x7f,0xa8,0xda,0x63,0x31,0x84,0xb3,0xe0,0xe7,
+  0x56,0x09,0x28,0x67,0xd9,0xa7,0x6a,0x13,0xe4,0x0e,0x28,0x10,0x88,0x11,0x5f,0xb9,
+  0x88,0x28,0x6c,0x77,0xfd,0x65,0xf3,0x82,0x55,0x92,0x4e,0x7e,0xa8,0x9e,0x6f,0x8d,
+  0x6e,0xf5,0x47,0x02,0xe1,0x5c,0x84,0x9b,0x10,0xe2,0x40,0xa7,0xb4,0x9a,0x64,0xf4,
+  0x52,0x61,0x81,0xdf,0xe5,0xa5,0x21,0x38,0x61,0x44,0x7b,0x11,0x9a,0xb9,0xf2,0xbf,
+  0xb0,0x5b,0x2e,0xa9,0x07,0xd8,0xfb,0x26,0x0e,0xdc,0x76,0x35,0xa3,0xd1,0x71,0x44,
+  0xad,0x2c,0x62,0x9e,0xe4,0x8b,0x2c,0xdf,0xb3,0xec,0x36,0xf3,0x88,0x15,0xe4,0x6e,
+  0xca,0xf8,0x65,0xab,0xd3,0x5c,0x60,0x69,0xcf,0xbb,0xf5,0x37,0x32,0xd8,0xbd,0xc5,
+  0xed,0x38,0x04,0x5d,0x03,0x86,0x21,0xb4,0x28,0xed,0xf1,0x1a,0x06,0x4e,0x11,0x89,
+  0x3a,0x5b,0xa6,0x13,0xff,0xe5,0xde,0xbf,0x68,0xbc,0xe8,0x8c,0xd1,0xe7,0xca,0xff,
+  0x7a,0xbe,0xa3,0xe2,0x1d,0xb5,0x05,0xf1,0xd7,0x0b,0xa9,0x73,0x41,0xb5,0xc1,0xa9,
+  0x0b,0xbc,0x9e,0xfd,0xda,0x6c,0xa7,0x40,0xc4,0x16,0xf6,0x5f,0x61,0x51,0x8f,0x91,
+  0x6d,0x59,0x0f,0x39,0x8d,0xc4,0xdf,0xc0,0x86,0x54,0xc5,0x30,0x22,0x85,0x99,0x2e,
+  0xfd,0x43,0x13,0x57,0x00,0x35,0xd9,0x67,0x4d,0x40,0xc4,0x1f,0x06,0xdf,0x4a,0xa1,
+  0x2d,0x8f,0x40,0xec,0x14,0xef,0x53,0xeb,0x2d,0xbf,0xae,0x2c,0x8b,0x5f,0x4c,0x2f,
+  0xbc,0xd3,0x4f,0xdf,0x07,0x2f,0x11,0x46,0xeb,0xf7,0xbe,0x9c,0x3e,0x90,0x0d,0xc4,
+  0xdc,0xf9,0x5f,0x57,0x68,0x08,0x2c,0x85,0x72,0x5a,0x9a,0x96,0x05,0xde,0x91,0x83,
+  0x42,0x93,0xe8,0x92,0x79,0x1e,0xee,0xc0,0x4b,0x5a,0xc6,0xbc,0x36,0x43,0x4e,0x3d,
+  0x73,0x42,0xb7,0x87,0xf2,0xda,0x8c,0xbb,0xac,0xc2,0xfa,0x5f,0xe2,0xf8,0x11,0x9d,
+  0x1c,0x5d,0x64,0x37,0xa4,0xb4,0xdc,0x78,0x0d,0x53,0x90,0x8f,0x55,0xca,0xd1,0xab,
+  0x9c,0x80,0xa8,0x99,0xe3,0x4f,0xa5,0xc6,0x0b,0x71,0x64,0xe9,0x02,0xfd,0x43,0x26,
+  0x4a,0x49,0xea,0x8e,0xc8,0x61,0x2e,0xe3,0x60,0x10,0x1e,0x83,0x3b,0x86,0xd5,0xd6,
+  0x20,0x85,0x5b,0x54,0x98,0x05,0x25,0x29,0xd9,0x06,0xa8,0x18,0xd4,0xb2,0xcc,0xa5,
+  0x7f,0x48,0xb4,0x97,0xe6,0x67,0x9f,0x85,0xe7,0xf9,0x4e,0x43,0x9b,0x29,0xfb,0x59,
+  0xf2,0x8c,0x1b,0xda,0xab,0x46,0xb0,0x9f,0x7f,0x43,0xd9,0x28,0xd9,0x9c,0x46,0x62,
+  0xb1,0x24,0x25,0xbf,0x3a,0xbc,0x62,0xaa,0xfe,0x21,0x89,0xb4,0x54,0x50,0xa0,0xc2,
+  0x42,0xad,0x29,0x3f,0x4f,0xfb,0x59,0xd2,0xaa,0x22,0x56,0xba,0x0f,0x9f,0x93,0x1e,
+  0x73,0x8d,0xbb,0x28,0x5e,0x2f,0xce,0x96,0x5d,0xfc,0xd7,0xd5,0x34,0x42,0xaa,0xac,
+  0x72,0x27,0x5c,0x6d,0x59,0x90,0x0e,0x0c,0xdb,0x65,0xbf,0xb4,0x34,0xbe,0xf3,0xa7,
+  0xb2,0x75,0xbc,0x74,0xa8,0xf2,0x32,0x5c,0xe6,0x0b,0x3a,0xfc,0x4e,0x22,0x58,0x09,
+  0xc2,0x2e,0x7e,0xdc,0x5b,0x47,0x9f,0x72,0xf3,0x5f,0x24,0x72,0x98,0xd0,0xb2,0x7c,
+  0x54,0x8d,0xb1,0x5c,0x39,0x2a,0xe9,0xe0,0xa9,0x42,0x76,0x3e,0xdb,0x32,0x46,0x6a,
+  0xbd,0x7c,0x7a,0x36,0xef,0x04,0x8e,0x99,0xa2,0x16,0x9b,0x0b,0x7f,0x9d,0x4f,0xdb,
+  0x6e,0x3c,0x85,0x60,0xad,0x94,0xf5,0xa4,0xec,0x3a,0x47,0xbd,0xb0,0xd0,0xf4,0xff,
+  0x40,0x99,0x66,0xfc,0x0a,0x5f,0x11,0xbf,0x80,0x03,0x8e,0x64,0xfa,0x31,0x3e,0xcb,
+  0xf4,0x17,0xf2,0x5f,0x1c,0x9d,0xe4,0x54,0xe2,0x5d,0xb6,0xd1,0xdc,0xd5,0x1a,0x4a,
+  0xf9,0xaa,0x6c,0xfc,0x15,0x7c,0x57,0xdd,0x78,0x26,0x68,0x86,0xb6,0x93,0x6c,0xf8,
+  0xb2,0x60,0x5e,0x37,0x83,0x9c,0x6d,0x26,0xce,0x57,0xb7,0x6e,0x2a,0xe0,0xbf,0xe6,
+  0x36,0xd3,0x25,0xda,0xbf,0x5a,0x5b,0x9c,0x3a,0x50,0xc5,0x29,0xd6,0x6f,0x6c,0x84,
+  0xb9,0x2d,0xa1,0x19,0x6c,0x0e,0x6c,0x54,0xe7,0xe7,0x9f,0xe3,0x43,0xf7,0x9b,0x6d,
+  0x8c,0x8b,0x02,0x5e,0x05,0xf9,0x5f,0x55,0xcb,0x08,0x7f,0x99,0x6d,0xba,0xb1,0x4c,
+  0xd5,0x7d,0xf9,0x2c,0x24,0x13,0x51,0xc0,0x72,0x15,0x61,0x57,0xba,0x2d,0x14,0x22,
+  0x16,0xa6,0x1f,0x6e,0x97,0x00,0xe1,0x24,0x29,0x72,0xe0,0xa5,0x02,0xfe,0x2b,0xf4,
+  0x82,0x1e,0x78,0x2c,0x79,0x2e,0x73,0x7c,0x4d,0xf4,0x66,0x7f,0xa2,0x53,0xa8,0x25,
+  0xf8,0xd0,0x6d,0xee,0xdd,0x35,0x10,0x7a,0x41,0xf5,0x27,0x34,0xa3,0xfd,0x8c,0x71,
+  0xd8,0xe7,0x96,0xb6,0xeb,0xb5,0xac,0xbf,0x8c,0xa9,0x05,0xf9,0x5f,0x38,0xbf,0x1a,
+  0x5a,0xb6,0xbc,0x86,0xf8,0x0b,0x37,0xb2,0x16,0xa1,0x09,0xef,0x04,0x07,0xf2,0x3f,
+  0x10,0xda,0x7a,0x6d,0xf7,0x25,0xb8,0x12,0x5a,0x54,0x00,0xa9,0xec,0x00,0xc2,0x7c,
+  0xfe,0x97,0x67,0x08,0xec,0x1a,0x61,0x8d,0xb2,0xa4,0x72,0xca,0x29,0xd6,0x4c,0x37,
+  0xdb,0x45,0x96,0x17,0xe2,0x3d,0x75,0xf9,0xe7,0xac,0x4a,0x09,0x64,0x47,0x75,0x15,
+  0x61,0xee,0x14,0xfd,0xc3,0x34,0x33,0x58,0x47,0xd1,0x7c,0x08,0xa5,0x73,0xd1,0x86,
+  0xc1,0x61,0x76,0x06,0x48,0x64,0xde,0x67,0x38,0x19,0x61,0x2e,0xb2,0xac,0xc7,0x2b,
+  0x8c,0x42,0xfe,0xcb,0x72,0xb2,0xbd,0x2c,0x51,0xed,0xcb,0x46,0x5b,0x43,0xcc,0x16,
+  0x99,0xff,0x33,0x1a,0x0b,0x6c,0x29,0xba,0x5e,0x23,0x91,0xb9,0xf8,0x2f,0x92,0x11,
+  0xde,0x41,0x83,0x0b,0xf3,0x9b,0x3b,0x44,0xfd,0x65,0xaf,0x44,0xf4,0x8c,0xaa,0x2d,
+  0x87,0x66,0x92,0xda,0x86,0x11,0x6c,0xb9,0x81,0x22,0x7d,0xa6,0x80,0xff,0xca,0xe2,
+  0x2f,0xdd,0xae,0xcd,0x81,0x63,0x66,0xb4,0x75,0x25,0x89,0x1c,0x1e,0x92,0xd1,0x86,
+  0xef,0xb2,0x5e,0x23,0x6a,0xaa,0x4f,0x27,0xfe,0x4e,0x94,0x51,0xa0,0xfe,0xf1,0x8c,
+  0x53,0x7e,0x9c,0xa3,0x1b,0xbf,0x6a,0x5b,0xf9,0x54,0xfe,0x4b,0x57,0xfa,0x29,0x8b,
+  0xb6,0x60,0x50,0xf0,0xe6,0x94,0x04,0xbc,0xfc,0x7c,0x0e,0x41,0x17,0x4a,0xd3,0x6b,
+  0x6e,0xfd,0x0d,0x82,0xe4,0x88,0xb6,0xe2,0x63,0x3c,0xaa,0x7f,0x11,0x34,0xc3,0x4e,
+  0x04,0x53,0xce,0xe9,0x67,0xcc,0xa8,0x17,0x5f,0xa4,0xb4,0x4b,0x91,0x23,0x27,0x44,
+  0x3f,0x55,0xff,0xd0,0x43,0x94,0x96,0x76,0x8e,0xdd,0x09,0x2f,0xaa,0x8b,0x52,0xa5,
+  0xb2,0x10,0xb3,0xc0,0x56,0x6f,0xc2,0x13,0x33,0x8d,0xb4,0xfa,0xd1,0xae,0x31,0x78,
+  0x91,0xd9,0x1a,0xf5,0x36,0x34,0x1b,0x83,0x27,0xf8,0x14,0xfd,0x43,0x2f,0xfa,0xe1,
+  0xbd,0xb7,0x14,0x33,0x56,0x8c,0x8e,0xc7,0x4c,0x9f,0x53,0xbe,0x50,0xa5,0x3a,0xf2,
+  0x09,0xca,0x6e,0x68,0x64,0x03,0xb8,0xc4,0xc5,0x0b,0xf0,0xd7,0x2b,0x89,0xe4,0xa0,
+  0x48,0x04,0x9b,0x82,0xbf,0x6e,0x31,0xd9,0x0c,0x4f,0x06,0xe6,0x98,0x3e,0x8a,0x4f,
+  0x38,0x08,0x6b,0x05,0x11,0x66,0x3c,0x46,0x55,0x57,0x5a,0x71,0x59,0xee,0x32,0x9d,
+  0xd0,0x3b,0x8f,0x58,0x9f,0x7f,0x0b,0x8f,0x51,0x22,0xd8,0xea,0x42,0xfd,0xc3,0xea,
+  0x6c,0xe0,0x8c,0x52,0x06,0x7f,0xe0,0xb7,0x1b,0x5f,0xac,0xd7,0x24,0x22,0xf3,0xaf,
+  0x57,0x2e,0xc3,0xaf,0xf9,0xf3,0x54,0xed,0xeb,0x47,0xd8,0x92,0x71,0xa8,0x31,0x81,
+  0xbf,0x7e,0xc3,0x4e,0x13,0x34,0x1b,0xd3,0x5c,0xf8,0x8b,0xdc,0x78,0x05,0x37,0x17,
+  0x58,0xcf,0xec,0x40,0x44,0x67,0x73,0x11,0xc2,0x0e,0xff,0xc6,0xa7,0xf0,0x5f,0xc2,
+  0x4f,0x60,0x13,0x05,0xfa,0x1b,0x12,0x7f,0x2d,0x38,0x17,0x18,0x50,0x2e,0xc0,0x49,
+  0x1e,0xab,0x12,0xb4,0xd7,0x84,0x40,0x5b,0x9e,0x3f,0xc2,0x6f,0x12,0x77,0xc6,0x4b,
+  0x7b,0x2a,0x1f,0x82,0x5f,0xf2,0xe8,0x90,0xd4,0xd0,0x4e,0x89,0x1c,0xb1,0x3f,0xc2,
+  0x8a,0xed,0x0b,0xb2,0xb8,0xeb,0x0d,0xba,0xf3,0xbf,0x2a,0xac,0x4e,0x2f,0xba,0x58,
+  0x8f,0x42,0x75,0x48,0xee,0x5f,0x5c,0x24,0x82,0x8d,0xc0,0x63,0x59,0xdc,0xb6,0xd6,
+  0x2b,0xb3,0x20,0x61,0x18,0x59,0xa9,0xbf,0xc1,0x05,0x10,0x1b,0x5c,0xb6,0x69,0x67,
+  0x68,0x58,0xd3,0x0a,0xf0,0x17,0xd5,0x5f,0x36,0x71,0xd7,0xfb,0x1e,0x55,0x2d,0x14,
+  0xcf,0x31,0x9c,0x7d,0x30,0x34,0xcf,0xf4,0x3d,0xc8,0x66,0x19,0xdf,0x87,0xaf,0x5a,
+  0xc5,0x92,0x08,0x13,0xf1,0x87,0x16,0x22,0x9c,0x39,0x54,0x82,0xcd,0xc6,0x5f,0x6b,
+  0x66,0xd8,0x51,0x55,0x5e,0xd6,0x0b,0x5b,0x13,0x35,0x71,0x47,0x65,0xc5,0xf6,0x33,
+  0x2d,0x83,0x8a,0x93,0x96,0xc2,0x93,0x50,0xd5,0xe7,0x8e,0xe8,0x78,0xc5,0x14,0xf5,
+  0xbf,0xea,0x1d,0xfc,0xd5,0x73,0xd3,0x3e,0x99,0x8d,0x82,0x7b,0x53,0xd1,0x9b,0x9b,
+  0x62,0x7b,0x03,0x0d,0x4a,0x78,0xd6,0x84,0x57,0x44,0x1b,0x8e,0xb0,0xe3,0x56,0xbd,
+  0xf9,0x44,0x5a,0xa9,0x85,0x37,0xe0,0x85,0xc1,0x12,0x99,0xb1,0x22,0xfb,0x19,0x9d,
+  0xff,0x3a,0x2b,0x70,0xd8,0xc1,0x5f,0x82,0xff,0x62,0x42,0xfc,0xfc,0xfd,0x35,0x1f,
+  0xc4,0x63,0x3c,0x27,0xb0,0x86,0xc6,0x7f,0xa8,0xef,0x34,0xc7,0xcc,0x2d,0xed,0xb7,
+  0xec,0x63,0x1f,0x40,0xa4,0x3f,0x90,0x99,0xee,0xf2,0xeb,0x48,0xb8,0xb2,0x73,0x0f,
+  0x6e,0x64,0x39,0xfc,0x75,0x51,0xc0,0xae,0xe4,0x59,0x78,0x05,0x16,0x24,0xd0,0xa9,
+  0x78,0xd8,0xd1,0xd9,0xfe,0x1b,0x38,0xb5,0x79,0x91,0xf9,0x78,0xb1,0x56,0x65,0xfc,
+  0x3f,0xa4,0xd8,0x86,0x7e,0x8b,0xd7,0x76,0x41,0xdf,0x46,0x0f,0x7f,0x51,0x6f,0xe0,
+  0xd8,0x52,0x17,0xff,0x85,0xfb,0x57,0xe6,0xd6,0xa3,0xe8,0xab,0x6f,0x3a,0x57,0xd7,
+  0xd3,0x81,0xfe,0xa1,0x67,0x42,0x38,0x81,0xcd,0xef,0x18,0xcf,0x0e,0x06,0xe3,0x25,
+  0x9b,0x8b,0x6a,0x8d,0x23,0xdb,0x82,0x0e,0x6f,0x45,0xb9,0x39,0x78,0xf3,0x73,0x29,
+  0x44,0x52,0x9b,0x99,0x91,0xd3,0x3f,0xf4,0x1e,0x61,0xe8,0xe1,0xef,0x65,0x1f,0x78,
+  0x36,0x25,0x48,0xc3,0xed,0x66,0x87,0xf6,0x0a,0x0e,0x2d,0xd9,0xe4,0x99,0xbb,0xac,
+  0x38,0x9d,0xa8,0x21,0x41,0x60,0x6b,0xa6,0x78,0x8e,0x52,0x63,0x6d,0x42,0xf8,0xc6,
+  0xc9,0x45,0xd7,0xf4,0xb2,0x02,0xfe,0xcb,0x30,0x6f,0xf6,0x30,0x7c,0xa7,0x61,0x35,
+  0xd5,0x12,0x5d,0x49,0x31,0x6f,0x03,0xb7,0x44,0x8a,0x2c,0x7d,0x97,0x8a,0x20,0x2b,
+  0x48,0x32,0x95,0xfa,0xb0,0x0c,0x99,0xeb,0x36,0x04,0x77,0x63,0xb1,0xb4,0x61,0xf4,
+  0x6b,0x1e,0xc6,0x6e,0xca,0xe3,0xaf,0x10,0x3e,0x39,0xad,0xbc,0x0f,0xc7,0xa1,0xab,
+  0x63,0xa5,0xf0,0x7b,0x05,0xbc,0x55,0xce,0xb5,0x0e,0x18,0x2f,0x98,0x7f,0xc1,0x8b,
+  0x70,0x07,0x31,0x1b,0xce,0x08,0x7f,0xec,0x3b,0x86,0x1d,0xa0,0x3b,0x00,0x5d,0xd6,
+  0xaa,0xc7,0x3a,0x1d,0xfe,0xeb,0x73,0x02,0x49,0x51,0xb2,0xf3,0x68,0x7a,0x12,0x9a,
+  0x74,0x47,0xe7,0x9f,0xbc,0xc1,0x51,0x7e,0x99,0x35,0x99,0xd3,0xfb,0x15,0x8a,0x70,
+  0xb3,0x53,0x57,0x26,0x66,0x34,0xbc,0x32,0x9d,0xc8,0x97,0xc9,0xfa,0x58,0x7f,0xa0,
+  0xaf,0x20,0xfe,0x10,0x04,0xa4,0xb2,0x6b,0xe2,0xe0,0x03,0xc5,0x8e,0x56,0x7a,0x46,
+  0xb9,0x08,0xff,0x5d,0x14,0xf9,0x5a,0x3a,0xca,0x11,0x88,0xf9,0xfc,0x7d,0xc9,0x51,
+  0x18,0xf0,0x2e,0xf0,0xd1,0x3d,0xfc,0x64,0x45,0x13,0x6c,0xb1,0x6e,0xa0,0xbf,0xe1,
+  0x18,0xf0,0x31,0x1c,0x16,0x41,0x86,0x41,0x44,0xbe,0xfc,0xf3,0x43,0xea,0x24,0x3b,
+  0x67,0x76,0xe8,0x35,0xba,0xda,0x8e,0x73,0xb0,0xc3,0x0c,0xea,0x5a,0x3b,0xb5,0xb4,
+  0xd6,0x6c,0xd7,0x1e,0x2f,0xd0,0xdf,0xd0,0xed,0xd0,0x4d,0x51,0xbd,0x17,0xd0,0xd8,
+  0x2f,0x40,0x56,0xf3,0x49,0x79,0x0c,0xb5,0x10,0x5b,0xd0,0x2b,0xf0,0xf8,0x74,0xf6,
+  0x0b,0x8a,0x79,0x03,0x9c,0x44,0x32,0xa9,0x7c,0x85,0xe1,0xaa,0xff,0x75,0x5d,0x94,
+  0xe9,0x5a,0x5a,0x84,0x2d,0x75,0x3f,0x23,0xa1,0x80,0x22,0xa2,0x63,0x06,0xe8,0xb8,
+  0x98,0x64,0xd5,0xb3,0xf0,0x03,0x79,0xc2,0x39,0x44,0xc5,0x5f,0xbc,0xb8,0x50,0x3b,
+  0xfa,0x87,0x37,0xe5,0x5e,0x75,0xd7,0x5e,0x40,0x2b,0xdb,0xec,0x1e,0xe5,0x63,0xfd,
+  0x04,0x7b,0x84,0xd8,0xa5,0x8f,0x94,0x01,0x2b,0x36,0x58,0xb3,0x19,0xc7,0xf4,0xad,
+  0x96,0xae,0x75,0x81,0x4d,0xca,0x70,0x62,0x80,0xf2,0x22,0xb7,0x6b,0x33,0x0a,0xeb,
+  0x2f,0x17,0xe6,0x45,0x5e,0x45,0xe3,0xd6,0x51,0xe5,0x6a,0xf3,0xef,0x60,0xb1,0xf5,
+  0x6f,0xa3,0xca,0x88,0x31,0xf6,0x54,0xec,0xb5,0x92,0x8d,0xca,0xe5,0xc4,0x27,0x10,
+  0x5b,0x1d,0x38,0xa6,0x5c,0x8e,0xa0,0x57,0xc9,0x03,0xed,0x85,0xfc,0x57,0xb4,0xe0,
+  0xfb,0xc4,0xe5,0x71,0x96,0x70,0xda,0x3d,0x31,0x52,0xdb,0x38,0xc7,0x8e,0x9b,0x5d,
+  0xa9,0xf0,0x1e,0xcd,0xaf,0x8e,0xeb,0xb1,0x1d,0x08,0xdb,0x87,0xf5,0x89,0x96,0xae,
+  0xbb,0xc3,0x0b,0xf1,0xfb,0xe4,0xf0,0x97,0x0c,0x32,0x54,0x72,0x1d,0x15,0xa6,0x68,
+  0x0d,0xab,0x44,0x9e,0x54,0x04,0x88,0x6a,0xf9,0x10,0x36,0xb5,0x04,0x33,0xea,0x3e,
+  0x76,0x9b,0x7a,0x64,0xb0,0xa6,0x47,0x3d,0x90,0xf8,0x10,0x0e,0x37,0x07,0x75,0xdc,
+  0xd1,0xa2,0x6e,0xfe,0x4b,0x1c,0x1b,0x9a,0xce,0x78,0x99,0xc2,0x97,0x28,0xc6,0xf1,
+  0x2a,0x4a,0x7a,0x56,0x92,0xb2,0xeb,0xcb,0xde,0x84,0x19,0x8c,0xb4,0x84,0x12,0xac,
+  0xaa,0xc7,0x13,0x4e,0xb7,0x44,0x12,0xe7,0xcc,0x2e,0xd3,0x98,0xa1,0x1a,0x6c,0xbd,
+  0x2b,0xfe,0x50,0xd2,0x5e,0x3f,0x92,0x70,0x60,0x0c,0x71,0xc1,0x0b,0x08,0xbb,0xe6,
+  0x09,0x5c,0xf0,0x58,0x35,0x25,0x1f,0xbd,0x66,0xe0,0x6e,0x15,0x1c,0xf8,0xfb,0xc4,
+  0x67,0xbd,0xcf,0x4b,0xb1,0xfa,0xd7,0xc4,0xa7,0xd0,0x58,0xeb,0xe2,0xbf,0xd2,0x11,
+  0x6b,0x55,0x44,0xa1,0xf7,0xa7,0x31,0x84,0x7e,0xb8,0x89,0x1e,0x75,0x63,0xf6,0xa7,
+  0x11,0xe5,0x23,0x78,0x39,0xd3,0x68,0x6d,0x69,0x50,0x7e,0x61,0xbe,0x6c,0x46,0x46,
+  0xbd,0x9f,0x29,0xf7,0x57,0x8d,0xee,0x6f,0x3c,0xb3,0xd2,0xa0,0x18,0xc5,0x96,0xc8,
+  0xa0,0xbf,0x4a,0xb9,0xdb,0x15,0x7f,0xa8,0x37,0x49,0xae,0xff,0xbb,0xf4,0x02,0x50,
+  0x98,0xe8,0x55,0xbe,0xb8,0xbf,0xf6,0xbc,0x32,0x62,0xe6,0xeb,0x7f,0x51,0x84,0xc0,
+  0xaf,0x9c,0xf8,0xc3,0x73,0xb8,0xa0,0x8d,0x83,0xf8,0x54,0xca,0xcd,0x7f,0xc9,0xf1,
+  0x62,0xb2,0xde,0x8d,0x46,0xe3,0x45,0x81,0xa3,0x0b,0x48,0x31,0x09,0x27,0xe3,0xcf,
+  0x2b,0xc3,0x52,0xe1,0x21,0xa3,0x18,0x84,0x2f,0xa4,0x0f,0x89,0x86,0x67,0x0a,0xff,
+  0x15,0xb7,0x8f,0x55,0x7f,0xeb,0x1c,0x00,0xbe,0x20,0xe4,0x76,0xcb,0xce,0x7a,0x71,
+  0xeb,0x3f,0xae,0x3d,0xd0,0x37,0x0b,0x7e,0xee,0xad,0x30,0xb5,0xd1,0xe0,0x0c,0xdc,
+  0xfa,0x9b,0x4c,0x75,0xb0,0x79,0x86,0x23,0x56,0xef,0xe2,0xbf,0x6c,0x25,0xf9,0x3e,
+  0x68,0xa7,0x20,0x43,0x95,0x95,0x21,0x4a,0x9a,0xf3,0x8e,0xef,0x61,0x47,0xf9,0xbf,
+  0x1e,0xa1,0xd9,0xc1,0x76,0xba,0x27,0x31,0x9b,0x94,0x4f,0xb0,0x7b,0x9b,0xbf,0x02,
+  0x07,0x3b,0x44,0x76,0x5e,0x01,0xff,0x55,0x65,0xad,0x90,0x39,0x11,0x36,0x11,0xd6,
+  0xe5,0xa9,0xca,0xaa,0xf5,0x65,0xa7,0x5b,0xed,0xfa,0x29,0x35,0xd0,0xad,0x56,0x9d,
+  0xd5,0x1a,0x71,0x23,0xeb,0x7e,0x30,0x3c,0xa6,0xd6,0xb1,0x95,0xf1,0x6e,0x5a,0x13,
+  0xea,0xdc,0xfc,0xd7,0x65,0xa8,0x93,0x94,0x56,0x02,0xc2,0x94,0xf6,0x15,0x82,0x0b,
+  0x30,0x97,0x97,0xa6,0xa7,0x8f,0x79,0x2e,0x7b,0x1f,0xa1,0x4b,0x77,0xf1,0xab,0x7d,
+  0x07,0x33,0x81,0x21,0xad,0x81,0x3f,0x62,0xfd,0x43,0x57,0x78,0xe4,0xb6,0xef,0xd0,
+  0xdc,0xe1,0xfe,0xa1,0x42,0xfe,0x4b,0x84,0x1d,0x8e,0xc2,0x59,0xb9,0x8e,0x51,0xd9,
+  0xe5,0x06,0x7d,0x36,0x25,0x8f,0x8c,0x11,0xef,0xc9,0xa9,0xda,0x57,0x59,0x03,0x62,
+  0x07,0xf4,0xf4,0x10,0x76,0xe9,0x81,0x47,0x95,0x9d,0xa4,0xbf,0xa1,0x17,0xf2,0x5f,
+  0xe7,0x21,0x2a,0xb3,0x87,0xa8,0x04,0x6d,0x09,0xa9,0xe7,0x91,0x16,0x4a,0x0d,0x29,
+  0xc8,0x8d,0x7b,0x4b,0xa9,0xe5,0x5d,0x38,0x66,0x45,0xe3,0x9b,0x77,0x28,0x73,0xe1,
+  0x8d,0x74,0x34,0xee,0x9f,0x49,0xc1,0x8a,0x46,0xf4,0xde,0x02,0xfe,0xcb,0x6b,0x47,
+  0x8b,0xf5,0x0b,0x69,0x7a,0xf2,0xc3,0xc9,0x91,0x6e,0xcd,0xa1,0xa4,0x16,0x82,0x54,
+  0x1b,0xad,0x20,0xe9,0xcf,0xcf,0x41,0xd7,0x5a,0xe8,0xc6,0xcf,0x69,0xdf,0x18,0x0f,
+  0xae,0x43,0x23,0x9b,0xd3,0x3f,0xcc,0x45,0x9d,0xc1,0x3f,0xc3,0xe7,0xcd,0xe2,0x41,
+  0xf6,0x20,0x1a,0x86,0xb9,0xdc,0x15,0x76,0xf8,0x63,0x59,0x3d,0xea,0x26,0xe6,0x4f,
+  0xb5,0x31,0xe3,0xcf,0xd4,0xad,0xcd,0x5e,0x84,0x54,0xc1,0x65,0xa1,0x29,0xfc,0x57,
+  0x9c,0x3c,0xfc,0x4b,0xe9,0x7f,0x0e,0x55,0x2e,0x57,0x5f,0x4b,0x2c,0x4c,0x3f,0x1e,
+  0x32,0x8e,0xab,0x88,0x02,0x5a,0x1c,0x20,0x96,0xf6,0xcc,0x4f,0x23,0xda,0x3a,0xee,
+  0x47,0x20,0x66,0xa0,0xf1,0x98,0x77,0x57,0x5b,0x28,0x7d,0x5c,0xcd,0xe7,0x7f,0x09,
+  0xfc,0x65,0xa7,0xe4,0x9c,0x31,0xea,0xd4,0x92,0x84,0x12,0xe7,0x67,0x8d,0xa8,0x5a,
+  0x6a,0x17,0xb3,0xf6,0x95,0x24,0x76,0xa7,0x13,0xc7,0x8d,0x68,0x47,0x78,0x97,0x62,
+  0x24,0xde,0x34,0xba,0xd4,0xf0,0x2e,0xcd,0xe0,0x03,0x46,0x04,0xa1,0x99,0xe2,0xe6,
+  0xbf,0x98,0x0c,0x7e,0xf3,0xe4,0x93,0x86,0xe0,0xa5,0xe5,0x54,0x6d,0xd9,0x49,0x59,
+  0x9a,0x4c,0x0b,0x8d,0xc4,0xd7,0x92,0x97,0xc8,0x38,0x1e,0xb8,0x40,0xc6,0x7c,0xaa,
+  0x1a,0x56,0x18,0x7f,0x68,0xe3,0xe5,0xf3,0x10,0x31,0x37,0x93,0x71,0x4e,0xd4,0x5f,
+  0x26,0xc5,0x3f,0x2f,0x95,0x66,0x6e,0xbe,0x04,0x1f,0x61,0xcb,0x96,0x41,0x45,0x26,
+  0x8b,0x95,0x0e,0x2e,0x95,0xf1,0x87,0x82,0xa9,0x71,0xf8,0x2f,0x5d,0xd2,0x5e,0xe8,
+  0xfc,0xf7,0x78,0xee,0x13,0x61,0x12,0xd3,0x3a,0xec,0x68,0x43,0x34,0xe6,0x52,0x14,
+  0x65,0x56,0x94,0x5d,0x5e,0xe1,0x0a,0x44,0x74,0xa8,0x31,0x28,0xe0,0xbf,0x0c,0x8a,
+  0x17,0x25,0x23,0x4d,0x60,0x76,0x88,0x32,0x9a,0x4d,0x9f,0x60,0xbb,0x58,0x5e,0x76,
+  0x23,0x0f,0xbb,0x54,0x1b,0xac,0xc5,0xb5,0x3c,0xff,0x25,0xe2,0x0f,0x83,0x92,0x35,
+  0x3b,0xe4,0x2a,0x04,0x46,0x6a,0xcf,0xfd,0x08,0xd2,0x8b,0x64,0xcb,0x53,0x66,0x4d,
+  0xab,0xb6,0xdd,0xa1,0x56,0x75,0x02,0x6b,0xf1,0xe0,0x54,0xfd,0x79,0xe8,0x72,0xba,
+  0x97,0x9e,0xa3,0x10,0x47,0x16,0x33,0x67,0xa7,0x3c,0xef,0xb6,0x6d,0x44,0x43,0xcd,
+  0xa1,0xa4,0xad,0xca,0x7b,0x9c,0x08,0x2c,0xdc,0x90,0x49,0x9a,0x43,0x7c,0xca,0xc5,
+  0x7f,0x9d,0x07,0x47,0x52,0xc3,0x9b,0x2f,0xbb,0xbc,0x7a,0x4b,0x6a,0xfa,0x90,0x18,
+  0xaf,0x5a,0x9c,0x17,0xc6,0xfb,0xdb,0x71,0xdb,0xda,0x41,0xa5,0xb4,0x77,0xc4,0xbe,
+  0x16,0x78,0x2a,0xf9,0x8a,0x89,0x0f,0x5c,0xb6,0x65,0xdb,0x54,0xfe,0x4b,0x93,0xc1,
+  0xc0,0x75,0x32,0x48,0xb5,0x43,0xa2,0xad,0x73,0xe8,0xe4,0x88,0x79,0x0a,0x80,0xab,
+  0xbf,0x1a,0x48,0x10,0xc7,0x8a,0xf3,0x92,0xea,0xf4,0x59,0x76,0x9d,0xf4,0xe3,0x2e,
+  0xfe,0x8b,0xd9,0x94,0xd6,0x26,0x19,0x7f,0x38,0x80,0x46,0x45,0xca,0x27,0x5b,0x4a,
+  0xe9,0x52,0x3d,0xbc,0x38,0x50,0xbb,0x53,0x1b,0x61,0xe3,0xf0,0x84,0x5a,0x99,0xd1,
+  0x86,0x12,0x88,0xc8,0x8c,0xda,0x6d,0x6e,0xfd,0xc3,0x5c,0xfc,0x21,0xe9,0x47,0x55,
+  0x89,0xf0,0x69,0x96,0x04,0xa3,0x65,0x5e,0xc1,0xca,0xd6,0x3d,0x20,0xbc,0xee,0x53,
+  0x90,0xb4,0x8c,0xf3,0xa2,0xd2,0xd0,0x91,0x74,0x78,0x14,0x2f,0x1d,0x2f,0xc4,0x5f,
+  0xc5,0xeb,0xca,0xae,0x7a,0xb7,0x48,0x35,0x75,0xd2,0xf7,0x33,0x08,0x20,0x9c,0x55,
+  0x85,0x1c,0xc4,0x7a,0xc4,0x05,0x07,0xa0,0x5a,0xd7,0xbe,0x84,0x1b,0x59,0x3b,0xaf,
+  0x60,0x22,0x41,0xe9,0x80,0x8c,0x18,0x1f,0x9e,0x12,0x7f,0x88,0xd8,0x4a,0xfd,0x2d,
+  0xbf,0x23,0x5b,0xb2,0x5e,0x39,0x45,0x49,0x5e,0x06,0x1a,0xd7,0x2c,0xaa,0x08,0xb6,
+  0xaa,0xbe,0x7c,0x36,0x42,0xb3,0xc5,0xd9,0x2d,0xeb,0x95,0xab,0xac,0x8f,0x60,0x57,
+  0x0b,0x76,0x2f,0x65,0x8d,0xb9,0xf3,0xbf,0x1c,0xaa,0x05,0xbf,0xaa,0x0b,0x64,0xbd,
+  0x08,0x45,0xa2,0x0a,0x95,0x08,0xe9,0xb9,0x6d,0x88,0xc6,0xc2,0xc4,0x05,0x76,0x48,
+  0xcd,0xdd,0x73,0x59,0x46,0xc2,0xbb,0xe3,0x0f,0xb9,0x1d,0x7f,0x78,0x2d,0xa7,0xbf,
+  0xc1,0x17,0x1b,0xf7,0x8f,0x29,0x6f,0x9b,0xa7,0xdb,0x9a,0x86,0xd8,0x98,0x52,0xb7,
+  0x6c,0x32,0x81,0x68,0x6b,0x18,0x31,0x9a,0xb8,0x87,0x8c,0xab,0xbc,0x29,0x1e,0x70,
+  0xe9,0x1f,0x3e,0x0d,0xdd,0x19,0xd1,0x09,0x14,0x5b,0x28,0xb0,0xd5,0x59,0x12,0x52,
+  0x00,0xec,0xa8,0xb7,0x4d,0xec,0x9f,0x7e,0x35,0xca,0xb6,0xc3,0x50,0xda,0x98,0xd4,
+  0xe2,0xec,0x7f,0xc2,0xa7,0x61,0xdc,0x89,0x5a,0x25,0x51,0x48,0xfd,0xe3,0xae,0xff,
+  0x45,0x9d,0xf9,0x80,0x1d,0x5b,0xe8,0x70,0x5b,0x0c,0x01,0xef,0xa4,0x41,0x95,0xd7,
+  0x96,0xe3,0xce,0x18,0xd9,0x6f,0x54,0x80,0xf8,0xf8,0xf3,0x50,0xdd,0x81,0xc6,0x19,
+  0xea,0x67,0xd0,0x5c,0xfa,0x87,0xb9,0x22,0x95,0xaf,0xea,0xdd,0x5f,0x0a,0xbf,0x8e,
+  0x63,0x7a,0xda,0xec,0x36,0xf1,0xfb,0xdc,0xce,0x4e,0x19,0x4f,0x82,0x1f,0xe1,0x76,
+  0x70,0x33,0xa4,0xc1,0xe0,0x38,0x2b,0x2d,0x23,0x4d,0x4a,0x62,0x06,0x4d,0xd8,0x96,
+  0xf0,0xdd,0x5a,0xd4,0xad,0x7f,0xe8,0xe4,0x6e,0x4b,0x55,0xc9,0xc3,0xd4,0xbd,0xe9,
+  0xc6,0x73,0xa5,0x3d,0x38,0x3a,0x6f,0xc1,0x6c,0xf2,0xde,0xe7,0x8a,0x6c,0x02,0xb1,
+  0xc7,0x1d,0xa2,0xf8,0x0d,0x5e,0x29,0xe6,0x0e,0x55,0x83,0xfd,0xa0,0x30,0xfe,0x10,
+  0x9f,0x73,0xd2,0xb8,0xa8,0x36,0xf6,0x05,0x22,0xc9,0x11,0x7e,0x51,0xe0,0x82,0xf2,
+  0x11,0xf8,0x90,0x89,0xc2,0x01,0xe7,0xe0,0x43,0xb3,0x91,0xaf,0xaa,0xc2,0x96,0x89,
+  0x16,0x6c,0x59,0xa8,0x0c,0xc0,0x79,0xb3,0x31,0x93,0xe7,0xbf,0x3c,0x39,0xfd,0x8d,
+  0xca,0x49,0x95,0x48,0x2e,0x04,0x59,0xb3,0x88,0x3d,0x19,0x2c,0x19,0x2d,0xa7,0xb4,
+  0x2f,0x01,0x0c,0x1b,0xc4,0xe8,0xf8,0x07,0x95,0x19,0xe6,0x2f,0xf9,0x82,0xf8,0xaa,
+  0x33,0x4a,0x23,0x3f,0x45,0x47,0x55,0x79,0xfd,0x43,0xb7,0xfe,0x86,0x53,0x7f,0x59,
+  0xed,0x84,0xe0,0xa0,0xa8,0xfa,0x24,0xb3,0xb4,0x96,0xfe,0x7d,0xfc,0xc8,0x99,0x9a,
+  0x21,0x75,0x7b,0x62,0xbe,0xb7,0x23,0x15,0xf4,0x6b,0x3f,0x45,0xf8,0xdc,0xd9,0x1a,
+  0xfc,0xac,0xe0,0xad,0x6e,0xcc,0x7f,0xd9,0x75,0x9c,0x83,0x9c,0x0a,0x31,0x7b,0x3a,
+  0xe1,0x7e,0x8a,0x3a,0x33,0x64,0x54,0xd5,0x4e,0xdc,0xfa,0x37,0xa9,0xb8,0x7c,0xa5,
+  0xb1,0xa5,0x53,0x15,0x27,0xff,0x71,0x17,0xfe,0x8a,0x08,0x92,0x0b,0xa7,0xa7,0x37,
+  0xdd,0x17,0x8a,0x50,0x91,0x2f,0xaa,0x42,0x95,0xf1,0x85,0x8d,0xa4,0xbe,0x9a,0xa4,
+  0x39,0x5a,0x68,0x4c,0x57,0x92,0x9a,0x0d,0xce,0x82,0xb4,0x4a,0x87,0x60,0x5e,0x4a,
+  0xd8,0x5c,0xe3,0xd2,0x3f,0x44,0xfc,0xb5,0x46,0xbe,0xea,0xa9,0x13,0x10,0x3d,0x2b,
+  0x8a,0x46,0x9d,0x68,0x0d,0xa6,0x4a,0x32,0xe5,0x8d,0xcc,0x8e,0x5e,0x0b,0xc1,0xe5,
+  0xaa,0xd8,0x0f,0xc2,0x74,0x54,0x35,0xd0,0x1a,0xc5,0x65,0x47,0x0b,0x89,0x52,0xf5,
+  0xfe,0xcc,0x52,0x97,0xfe,0x3c,0xf9,0xf3,0x5b,0xf6,0x97,0x93,0x37,0x28,0x82,0x0c,
+  0x05,0x23,0xb6,0x49,0x04,0x41,0xbd,0x44,0xd4,0xd8,0x05,0x74,0x45,0x44,0x75,0x36,
+  0x51,0xff,0x6b,0x0e,0x1d,0xf7,0x09,0x09,0x14,0xc1,0xb0,0x4c,0xd1,0x3f,0xdc,0x6c,
+  0x29,0x31,0xbc,0x84,0xcb,0x20,0xcd,0xaf,0xb7,0xa8,0x10,0x58,0x76,0x41,0x8a,0xa8,
+  0x31,0x12,0xb6,0x6a,0x34,0x4e,0x43,0xf4,0xb8,0xff,0x02,0x0e,0x93,0x18,0xd3,0x56,
+  0x2d,0xc6,0x3e,0xe4,0x77,0x40,0x5e,0x7f,0x83,0xf0,0x57,0x0f,0xaf,0xe1,0xea,0x0e,
+  0x56,0xe3,0x3f,0x34,0x2d,0x08,0x25,0x24,0x72,0xf8,0x1c,0x2f,0xcd,0x6a,0x1d,0xc1,
+  0x30,0x5e,0x22,0x92,0x8b,0xa5,0x09,0x76,0x51,0xd6,0x0f,0xa7,0x6d,0xcb,0xab,0xee,
+  0x61,0x7e,0x6f,0x67,0xd1,0x7c,0x43,0xdb,0x51,0x56,0x18,0x7f,0x48,0x99,0x5c,0xa2,
+  0xda,0x17,0xcf,0x17,0x46,0xa4,0x4f,0xe1,0xd6,0xd6,0x8f,0xfd,0x0c,0x14,0x62,0x8d,
+  0x63,0xc2,0xc0,0xe4,0xba,0x01,0xc5,0x6d,0xa4,0x07,0xab,0x08,0x46,0xec,0x82,0x2b,
+  0xff,0x8b,0xd5,0x6c,0x55,0x49,0x64,0xfe,0x30,0x37,0x32,0x42,0xff,0x50,0x46,0x1b,
+  0x06,0xab,0x1c,0xdd,0x4b,0xfc,0x1a,0xcb,0x76,0xe5,0xb7,0xd1,0x62,0xce,0xfc,0xac,
+  0x93,0x0e,0x36,0x77,0xf0,0xd1,0x3c,0xfe,0xba,0x6c,0xc5,0x46,0xc3,0xcf,0xe2,0x30,
+  0x5d,0x6e,0x8b,0xe2,0x73,0x14,0x5b,0xe8,0xe6,0x59,0xdc,0xa9,0x2f,0x1b,0x51,0x1e,
+  0xd8,0xf3,0x5f,0x0c,0x1c,0x9d,0xe8,0xa8,0xff,0x28,0x0e,0xdc,0x71,0x3d,0xda,0x5e,
+  0x52,0xa6,0x90,0x22,0x7d,0xdd,0x70,0xe0,0xa8,0xc7,0x15,0x7f,0x78,0xb5,0xaa,0x69,
+  0x68,0xd5,0xb7,0x85,0x4c,0x4a,0x13,0x17,0x63,0x41,0x55,0xf0,0x02,0xcb,0xca,0x2f,
+  0x9b,0xa3,0xf0,0x92,0x29,0xca,0x04,0x5c,0x80,0xc5,0xde,0xda,0x2f,0x68,0xaf,0x27,
+  0xfe,0xd0,0xf1,0xf3,0xfb,0x6a,0x64,0x68,0xe2,0x2d,0x43,0x38,0x82,0x85,0xf8,0xab,
+  0x37,0xc0,0xa7,0x8f,0xe8,0x97,0xe3,0xd1,0x6d,0xf6,0xba,0xfa,0x08,0x55,0x8b,0x33,
+  0xbc,0x27,0xf0,0x25,0x29,0xd5,0x95,0x30,0xff,0x00,0xa2,0xb3,0x56,0xb6,0x69,0x55,
+  0xe2,0x0c,0xdf,0x2f,0x0a,0xc9,0x19,0x38,0xb8,0x7b,0x94,0xbf,0x74,0xe7,0x7f,0x05,
+  0x07,0x35,0x3a,0x04,0xfb,0xa0,0x3f,0xc8,0x65,0xfd,0x65,0x7c,0x8e,0x96,0x4a,0xcc,
+  0x31,0xdf,0x94,0x3b,0x75,0x18,0x36,0x65,0xff,0x11,0x4a,0x3a,0xd8,0x5c,0x6b,0xa3,
+  0xba,0xcb,0x54,0xdb,0x95,0xb5,0xac,0x33,0x1d,0x5c,0x88,0x3d,0xf6,0xc7,0x3c,0xfe,
+  0xda,0x4f,0xe1,0x55,0x24,0x72,0xd8,0xa3,0x1b,0xdf,0xc4,0x21,0xf8,0x78,0x99,0xac,
+  0x56,0x99,0x00,0x51,0x4a,0x00,0x1d,0x8f,0x55,0x7a,0xa2,0x03,0xdd,0x2f,0xc6,0x1e,
+  0x63,0x6d,0x56,0x7a,0x5d,0x48,0x4d,0x94,0x9a,0x9d,0x2f,0x1b,0x91,0x8e,0x32,0x37,
+  0xfe,0x7a,0x7e,0xf0,0xde,0x51,0xed,0xaf,0x11,0x7f,0xfd,0x38,0x51,0xb1,0x5a,0xa6,
+  0x23,0xf1,0x79,0xc3,0xda,0x3c,0x16,0xe3,0x8f,0xa6,0x8c,0xb4,0xef,0xeb,0x3e,0xd2,
+  0xe5,0x31,0x88,0x8e,0xb9,0x19,0x1e,0xcb,0x54,0xa4,0xd5,0xb1,0xc4,0xff,0xaf,0x6f,
+  0xc3,0x9e,0x8a,0xa0,0x7a,0x4f,0x41,0xfc,0xe1,0x8e,0x88,0x15,0x20,0x9d,0x9c,0x51,
+  0x33,0xf3,0x75,0xcd,0x4e,0xf2,0x1a,0x0e,0xe8,0xf8,0xda,0xb4,0xa5,0x23,0xa9,0xd2,
+  0x67,0x93,0x66,0xbc,0x57,0x87,0x51,0x7f,0x44,0x51,0xe1,0x38,0x8f,0x6e,0xf2,0xeb,
+  0x4a,0x69,0xff,0x89,0x4c,0x66,0x18,0x0d,0x17,0xfe,0xfa,0x94,0x90,0x14,0xa9,0xcd,
+  0x7f,0x04,0xb7,0x4e,0xcb,0xe9,0x6f,0x6c,0x19,0xd5,0x26,0x53,0xd7,0xa6,0x35,0xf1,
+  0x92,0xac,0x32,0xca,0xff,0x47,0xd5,0x77,0x85,0xec,0xa1,0x80,0x03,0x81,0x37,0x28,
+  0xf5,0x52,0xff,0x6e,0x7f,0xed,0xaf,0xdc,0xfc,0xd7,0x45,0x1e,0xb5,0x36,0xef,0xa5,
+  0x5a,0x12,0x3c,0x8a,0x90,0x6a,0xe9,0xc7,0xb6,0x50,0x12,0x02,0xb1,0xe3,0x52,0x60,
+  0xd6,0xd0,0xdd,0x65,0x46,0xc9,0x08,0x8b,0xa5,0x00,0x0d,0x77,0xfe,0x97,0x47,0x6c,
+  0xeb,0xb3,0xe0,0x28,0x54,0xe2,0xb6,0xd5,0x7c,0x56,0x7f,0x06,0xb7,0x9b,0xa5,0x71,
+  0xfa,0x5d,0xc4,0x88,0x59,0x78,0xe9,0x19,0xd8,0x6d,0x55,0x8f,0xfa,0xa8,0x40,0xc3,
+  0x3c,0xcb,0xbf,0xce,0xd7,0x48,0x62,0x53,0x96,0x6a,0xba,0xf3,0xbf,0x5e,0x22,0xc4,
+  0xda,0x78,0x37,0x61,0xab,0x8a,0x38,0xe5,0x7f,0x79,0x37,0xb4,0xe3,0x66,0x37,0xb3,
+  0xac,0xcc,0xb3,0x81,0xcf,0x0b,0x2a,0x2d,0x89,0x2f,0xc2,0xf7,0x7b,0x2b,0xb2,0x26,
+  0x45,0xbc,0x6c,0x40,0xb0,0xd6,0x71,0x8f,0x30,0x42,0x59,0x55,0x2d,0xc8,0xff,0x52,
+  0x71,0x39,0xad,0xa7,0x43,0x27,0x6b,0x97,0x21,0xe6,0xa9,0x2d,0x24,0xe5,0xf5,0x24,
+  0x53,0xa4,0xa3,0xe8,0xfb,0xbf,0xd5,0x97,0x10,0x21,0x6e,0x24,0xf9,0xa9,0x67,0xcc,
+  0xea,0xc1,0x8e,0x56,0x11,0xe8,0x8b,0x40,0xcc,0xbb,0xc9,0xcd,0x7f,0x99,0x0b,0x7a,
+  0xc2,0x44,0x7b,0x5d,0x85,0x05,0x7b,0xfd,0x52,0x08,0xb1,0x46,0x30,0x62,0xe8,0xef,
+  0x34,0xf0,0x5b,0xd3,0xca,0xd7,0xf9,0x9b,0x3c,0xca,0x67,0xa5,0x03,0x24,0x3b,0x5f,
+  0xc7,0x49,0xac,0x1e,0x1d,0x9f,0xbb,0x32,0xe1,0xa1,0x02,0xfe,0xcb,0xfb,0xa2,0x5d,
+  0xff,0x6b,0x66,0xcc,0xc8,0x57,0x5b,0x06,0x85,0x1b,0x63,0xb0,0x18,0x6e,0x35,0x95,
+  0xad,0xb8,0xcb,0x35,0x41,0xa9,0xa9,0x0c,0xc2,0x25,0x0a,0xbf,0x35,0x11,0x14,0x23,
+  0xfe,0x9a,0x31,0xa5,0xfe,0x17,0xcf,0x69,0xcb,0xbb,0x0a,0x81,0x09,0xcf,0xf3,0x57,
+  0x54,0x6d,0x79,0xab,0x32,0xc7,0x38,0xa6,0x77,0xb5,0xcc,0xda,0xa6,0xcc,0x8d,0x1f,
+  0xdb,0x1b,0xfd,0x9a,0x7f,0x6b,0x39,0x4d,0xb4,0x46,0xd3,0xaf,0x97,0x17,0xe6,0x7f,
+  0xad,0x93,0x68,0x6b,0x59,0x0d,0xc1,0xae,0x77,0x6d,0x92,0x22,0x51,0x25,0x44,0x36,
+  0x70,0xa9,0x9c,0x4b,0x46,0xab,0xc0,0x5f,0xc2,0xd8,0x4e,0x81,0x88,0x71,0xbc,0xf9,
+  0x69,0x77,0xfe,0xd7,0x91,0xb8,0x93,0x23,0xa6,0xd6,0xb4,0xa8,0xa9,0xe6,0x77,0xa5,
+  0xfe,0xc6,0x36,0xb6,0xc7,0xdc,0x08,0x73,0x49,0x90,0x6a,0xa1,0xf1,0x73,0xf5,0xc7,
+  0xad,0xea,0x68,0x62,0x21,0x3c,0xce,0xce,0xb5,0xae,0xa1,0xe7,0x3c,0xc5,0x6a,0x5a,
+  0x5a,0xb6,0x25,0x0a,0xf5,0x0f,0x57,0x0b,0x6e,0x6b,0xbf,0x1e,0xee,0x97,0xf5,0xbf,
+  0x24,0x0a,0xf0,0x36,0x6f,0x85,0x8a,0xe5,0xa1,0xbb,0x37,0xcd,0xd8,0xf5,0x7c,0xe8,
+  0xc7,0x64,0xcc,0xda,0xb5,0x21,0x74,0xef,0x72,0xf5,0xee,0x4d,0x7e,0xd8,0x0a,0x54,
+  0x7f,0x79,0x53,0x61,0xfe,0x97,0xee,0x4f,0x50,0xea,0xdc,0x9a,0xd8,0xcd,0x61,0xae,
+  0xf4,0x52,0x60,0x2d,0x04,0x12,0xc9,0x9d,0xe9,0x81,0x50,0x1d,0x81,0x2c,0x83,0x8f,
+  0x22,0x34,0x0b,0x91,0x41,0xb0,0x6b,0x73,0x73,0xb9,0x81,0x1e,0x50,0x8c,0x87,0x5d,
+  0xf5,0x97,0x87,0x54,0x84,0x42,0x92,0xf6,0xba,0x62,0xd4,0x4a,0xd9,0xf9,0x71,0x29,
+  0x4e,0x78,0x89,0x53,0x71,0x2e,0x21,0x84,0x78,0x6c,0x7e,0xc3,0xf1,0xe9,0x64,0x4c,
+  0x84,0x66,0x0b,0x20,0xb6,0x6b,0x3c,0xd4,0xd4,0xbf,0x25,0x8f,0xbf,0xbc,0x54,0xff,
+  0x4b,0x20,0xa9,0x2a,0x81,0xad,0xfc,0x42,0x5b,0x03,0x62,0x92,0x11,0x13,0xd0,0x6c,
+  0x50,0x59,0xc8,0x04,0xda,0x1a,0x64,0x68,0x78,0x16,0x98,0x6b,0x5b,0x95,0x19,0xf0,
+  0x2a,0xdd,0x3c,0x45,0x7f,0xc3,0x15,0x64,0x48,0xb0,0x8b,0x75,0x48,0x46,0x2c,0xed,
+  0xdd,0x24,0x2f,0x71,0x6c,0x89,0x91,0x10,0x3d,0x6e,0x54,0x30,0x1f,0x42,0xe8,0x91,
+  0x21,0x34,0xbb,0xdf,0x53,0x92,0xd3,0xdf,0x50,0xbd,0xfd,0x54,0x3c,0xe8,0x5e,0x59,
+  0xdb,0x8b,0x87,0xcd,0xf9,0x39,0xfd,0xf9,0x88,0x2f,0xaf,0x7f,0xa8,0x4b,0xc3,0xe7,
+  0x65,0x5b,0xbd,0x55,0x88,0x9b,0x8a,0xbc,0x2c,0xc9,0xc2,0xbd,0x2d,0x53,0xf4,0x0f,
+  0x83,0x71,0x8a,0x4d,0xf5,0x1e,0x81,0xb9,0x54,0x4a,0xbb,0x5f,0x04,0x97,0xde,0xb2,
+  0xa3,0xb9,0xba,0x95,0xde,0x16,0x6d,0xbb,0x6f,0x8e,0x2c,0xbb,0x4c,0x04,0xe8,0x53,
+  0x04,0xed,0xb7,0x33,0xaf,0xe0,0x4f,0x8b,0x0b,0xf4,0x0f,0xcf,0xcf,0xc4,0x4e,0xd8,
+  0xda,0x59,0x45,0x2f,0xb6,0x4c,0xf2,0x12,0xfd,0xf3,0x34,0xfe,0xf6,0xf7,0xad,0xae,
+  0xf8,0xad,0x29,0xcf,0x5c,0x38,0x96,0x09,0xae,0xd3,0x76,0x54,0xce,0x65,0x6f,0xf0,
+  0x68,0xdc,0x4f,0x8e,0x07,0x3e,0x67,0x5d,0x78,0xbb,0xe2,0xe6,0xbf,0x92,0x2f,0x4a,
+  0x91,0x8d,0xf1,0x9c,0x5e,0x8a,0x64,0xc4,0xde,0x83,0xf7,0x0d,0x6c,0xf9,0x81,0x32,
+  0x14,0x17,0x69,0x7a,0xdb,0xba,0x87,0x52,0xe7,0x2a,0x28,0x22,0x51,0xdb,0x23,0x33,
+  0xcb,0x0a,0xf5,0x37,0x5a,0x62,0xe0,0xf7,0x92,0xa4,0xbc,0x27,0x56,0x16,0xb6,0xb3,
+  0x32,0x05,0x23,0xd6,0x67,0xa1,0x51,0x4c,0xb2,0x1b,0x56,0x3c,0xaa,0xfb,0xb1,0x7b,
+  0x71,0x61,0x8c,0xcd,0xf4,0xb7,0x29,0x86,0x81,0xd0,0x4c,0x47,0xc3,0x15,0x7f,0xf8,
+  0x62,0x73,0x2d,0x71,0x5b,0x68,0xb4,0xd4,0x12,0xfe,0x1a,0x17,0x6a,0x1b,0x5a,0x96,
+  0xd5,0xcf,0x20,0x43,0xcd,0xb2,0xbb,0xe0,0x89,0x65,0x95,0x09,0xff,0xc7,0x94,0xf6,
+  0x75,0x6f,0xed,0x8e,0xc7,0x47,0xca,0xee,0x84,0x27,0xe8,0x53,0x43,0x53,0xe2,0x0f,
+  0x55,0x95,0xf2,0xbf,0x32,0x56,0x0d,0xb9,0x97,0xa7,0x0d,0x51,0x75,0xb7,0x8e,0x05,
+  0x75,0x72,0x3c,0x8a,0x0f,0x24,0xee,0x37,0x93,0x56,0x7c,0x50,0xad,0x2f,0xaa,0xb1,
+  0x92,0x3f,0xae,0x19,0x6d,0x39,0xcc,0xfe,0x02,0x92,0xa4,0xa7,0x57,0xd5,0x57,0xc8,
+  0x7f,0xc5,0xef,0x59,0x17,0x9c,0x85,0xae,0x7e,0x98,0x16,0xea,0x7f,0x77,0x54,0xf8,
+  0x3e,0xab,0x6f,0x80,0x70,0x56,0x9d,0x51,0x34,0x0b,0x1e,0xf3,0xc5,0xe3,0xc5,0xad,
+  0x6c,0x26,0x7c,0x8f,0x9e,0x9c,0xc5,0x97,0x98,0xee,0x09,0x19,0xcc,0x15,0x7f,0xb8,
+  0x88,0x37,0x19,0xe1,0x7a,0x05,0x41,0x56,0x42,0xd2,0x5e,0x4c,0xa8,0x6d,0xd4,0x2b,
+  0xa0,0x6f,0x40,0xa3,0xe4,0x1e,0xed,0xbf,0xb2,0x24,0xc2,0x2e,0x74,0xd5,0x3e,0xcb,
+  0x10,0x91,0xc5,0xfd,0xeb,0xb5,0xbf,0x81,0x5f,0xb6,0x35,0x66,0xfd,0x6b,0xb4,0xc2,
+  0xf8,0x43,0x49,0x7b,0x51,0xf5,0x79,0xb7,0xc8,0xc6,0x10,0x7c,0x47,0x1a,0xab,0xc5,
+  0x71,0x5f,0x29,0x55,0x8f,0x7a,0x5f,0x02,0xb1,0xb4,0xbc,0x27,0x5d,0x50,0xff,0x2b,
+  0xd1,0x64,0x04,0x0e,0x29,0x35,0xea,0x24,0x8f,0xa6,0xc3,0xc4,0x6d,0x7d,0x22,0x83,
+  0xa0,0xde,0x31,0x4f,0x4b,0xfd,0x8d,0x87,0xe0,0x8d,0x54,0x8c,0x6f,0xa6,0x88,0xc4,
+  0xd3,0x78,0x0f,0x7e,0xb1,0x9a,0x66,0x52,0x75,0xf3,0x0f,0x17,0xe8,0x1f,0x66,0xab,
+  0xcd,0x15,0xeb,0x7d,0xb3,0xf9,0xf3,0xba,0x90,0xe5,0x7f,0x5d,0xf6,0xcf,0x37,0x83,
+  0x7f,0x4c,0x27,0x29,0x62,0xf3,0x3c,0x9b,0x69,0xb4,0xa7,0x17,0x87,0xd5,0xd6,0xe6,
+  0x99,0x91,0x8d,0xb0,0x33,0xad,0xae,0x66,0x41,0x73,0xc3,0xce,0xf0,0x60,0xcb,0xea,
+  0x02,0xfd,0xc3,0x75,0xd5,0xe4,0xe9,0x7d,0xd9,0x7a,0x1e,0xe6,0x6c,0x54,0x89,0xf6,
+  0x7a,0xc6,0x8e,0x03,0xb1,0xc4,0x73,0x5a,0xd1,0xe3,0x78,0x14,0xc2,0x9b,0x71,0x28,
+  0x67,0xc0,0x33,0x24,0x5a,0xf8,0xcd,0x04,0xee,0x8c,0x86,0x18,0x94,0x3f,0x73,0xe3,
+  0xaf,0x9a,0x25,0xa4,0x12,0xe6,0xdd,0x6f,0x56,0xe9,0x2a,0x1d,0xf8,0x0b,0x3f,0xf3,
+  0xf6,0x60,0x3f,0x4b,0xb6,0x1a,0xa3,0xda,0x2c,0xc6,0x38,0xef,0x9d,0xff,0x60,0xa8,
+  0x86,0x4d,0x87,0xb4,0x85,0x3e,0xa4,0x97,0x19,0xaa,0x86,0xf7,0x74,0x2c,0x64,0xf7,
+  0x14,0xe0,0xaf,0x5d,0x01,0xa9,0x21,0xf9,0xc2,0x97,0xa4,0xbe,0x16,0x1d,0x83,0x1f,
+  0x50,0x3e,0x84,0x4e,0xab,0xeb,0xbd,0xc0,0xd3,0x49,0xf4,0xbe,0x66,0x96,0x5a,0xfe,
+  0x9f,0x69,0xb5,0xec,0x59,0x88,0x66,0xd1,0xb1,0x0f,0xb3,0xe7,0x60,0x96,0xe5,0xdf,
+  0x77,0xcb,0xd7,0x5d,0xf8,0xcb,0x8a,0xbd,0x16,0xc8,0x24,0xf7,0xe9,0x97,0x5b,0x1a,
+  0xcc,0x55,0x19,0x11,0x15,0x13,0xa3,0xba,0xae,0x1f,0x71,0x5b,0x64,0xe3,0xa7,0xf0,
+  0xc1,0xb2,0x58,0x73,0xa0,0x5d,0x79,0x9f,0xef,0x80,0xd8,0x20,0x1a,0x62,0x4c,0x53,
+  0xb5,0x7b,0x71,0x6f,0x72,0xe3,0x2f,0x8f,0x9f,0x34,0xb8,0x2e,0xc3,0xe2,0x21,0xff,
+  0xe8,0x74,0x1b,0x91,0xb5,0x7a,0xea,0xe1,0xb4,0xba,0xd8,0xf2,0x0f,0x26,0xdf,0xa3,
+  0xe8,0xb5,0x81,0x95,0x6b,0x70,0x19,0x3c,0xb5,0x79,0xc1,0x7d,0xfe,0xb3,0xc9,0x7a,
+  0xf3,0x77,0xb0,0x20,0xbb,0xd2,0x48,0xe4,0xf9,0x2f,0xcf,0x11,0xab,0x26,0x2e,0xe0,
+  0xd2,0xe1,0xfe,0x1a,0x23,0x90,0x29,0x7b,0xd7,0x10,0xfc,0xd7,0xbe,0xe0,0x4f,0x11,
+  0x40,0xc5,0xac,0x59,0x3b,0x12,0xc3,0xf1,0x8d,0x33,0x83,0x5d,0xa1,0xa7,0x95,0xbf,
+  0x87,0x37,0xf5,0x60,0x44,0xdd,0xc7,0x42,0xac,0x93,0xe3,0x46,0xb6,0xd3,0xa5,0x7f,
+  0xe8,0x3d,0x92,0xa8,0x21,0xf7,0x9b,0x6a,0xeb,0xdc,0x0f,0xc5,0x99,0xe6,0x61,0x53,
+  0x20,0xb2,0xa3,0xb8,0x85,0xff,0x10,0x6a,0x7a,0xd5,0x8e,0xb2,0x01,0xca,0x5a,0xe5,
+  0xc5,0x3b,0x13,0xe1,0x74,0x42,0x35,0x1e,0x2b,0xd6,0xd9,0x5a,0xf8,0x21,0x0f,0x0e,
+  0xa8,0xbc,0x28,0x5d,0x98,0xff,0xb5,0x46,0xcc,0x53,0x71,0xbc,0x2f,0xb4,0x35,0xd6,
+  0x0e,0xae,0x88,0xb0,0x01,0x96,0x34,0x43,0x96,0xea,0xfd,0xaf,0xfd,0x8c,0x1b,0x69,
+  0x56,0x0c,0xcc,0xc4,0x6d,0x2b,0xdd,0x32,0x4f,0x9f,0xdf,0xb2,0xa9,0xad,0xc3,0x48,
+  0x75,0x40,0x69,0x22,0x8f,0xbf,0x0e,0x47,0x62,0x26,0xba,0xf1,0xfb,0xf8,0x65,0x68,
+  0x6c,0x0f,0x93,0xe8,0xc7,0x11,0x33,0x46,0x15,0xdc,0xb2,0x89,0xb7,0xcc,0x1a,0x2b,
+  0xd4,0xbe,0x34,0x4b,0xd4,0x18,0xe2,0x7e,0x05,0x1d,0xe5,0xd6,0x2e,0x28,0x01,0xe5,
+  0x1b,0x37,0xbd,0x15,0xef,0x1a,0x44,0xe7,0x2d,0x9d,0xc7,0x5f,0x57,0xee,0x6b,0xa2,
+  0x92,0x94,0x57,0x44,0xa1,0xd8,0x52,0xa1,0xad,0x11,0x12,0xf9,0x5f,0xfb,0x55,0x0a,
+  0x4d,0x2c,0xed,0x23,0x4a,0x4b,0xff,0x2e,0x2b,0xb5,0x14,0xaa,0x28,0x85,0xf7,0x58,
+  0xca,0xa1,0xf4,0xe4,0x7c,0xbc,0x27,0xab,0xac,0xb1,0xf1,0x97,0xc7,0xd6,0x9f,0x3f,
+  0xa4,0xdc,0xaf,0xbe,0xc4,0x63,0xa3,0x74,0xbe,0xe1,0xfd,0x14,0x44,0xfe,0x57,0x18,
+  0x70,0x50,0xda,0x71,0x93,0x72,0x14,0x11,0xa7,0xbb,0x6a,0x34,0xdb,0x73,0xd0,0x85,
+  0xbf,0xb0,0x57,0x29,0xff,0xab,0x86,0xf8,0xaf,0x01,0x41,0x84,0xe1,0x46,0x66,0xa8,
+  0x1d,0x2c,0x08,0x3d,0x89,0xa0,0xaa,0xf6,0x50,0xfd,0x65,0x1e,0xec,0x5b,0xd1,0xd3,
+  0x9c,0x27,0xcb,0xbc,0xb6,0x71,0x5d,0xfe,0x57,0x91,0x2b,0x30,0x3b,0x13,0x12,0xf9,
+  0x5f,0x9c,0x42,0x13,0xc9,0x9f,0x3f,0x89,0x5b,0x52,0xe8,0x98,0xe4,0x19,0xbd,0x6b,
+  0xf3,0x31,0xdb,0xda,0xf5,0xf9,0x5f,0x91,0x5c,0xb6,0x60,0x33,0x15,0xf9,0xaa,0xf1,
+  0xa8,0xa2,0x8c,0xa6,0x11,0x04,0xd2,0x4b,0xe1,0x47,0xd8,0x7c,0x3b,0xfe,0xd0,0x53,
+  0x53,0x10,0x88,0x98,0xcf,0xff,0x9a,0x1a,0x23,0xbd,0x34,0x97,0xff,0xb5,0x4f,0x7d,
+  0x0b,0xf1,0x97,0x3f,0x03,0x23,0xde,0x8b,0xa3,0x3f,0xa0,0xb3,0x26,0x51,0x97,0xc1,
+  0x12,0x04,0xb1,0x5d,0xb2,0xc1,0xba,0xa1,0xfe,0xbc,0x2d,0x72,0x78,0x25,0xd5,0xd4,
+  0x1a,0x58,0xa7,0x3d,0x8c,0xde,0xe0,0xcf,0xd1,0x6d,0xa6,0xee,0x05,0x3b,0xed,0xeb,
+  0xa5,0x29,0x64,0xd9,0x8d,0xf2,0xbf,0x84,0xd6,0x87,0x58,0x60,0x29,0xed,0xcb,0x4e,
+  0xb2,0xb0,0xc3,0xd8,0xcc,0x86,0xde,0x92,0xcc,0xd2,0x7d,0xde,0x09,0x2f,0x89,0x87,
+  0x78,0x72,0x9f,0xfa,0x9f,0x85,0xfa,0x1b,0x9d,0x4e,0x59,0x07,0x59,0xe4,0x0b,0xd7,
+  0x3b,0xcd,0xae,0x86,0x66,0x39,0xa5,0xd3,0x7a,0xdd,0xf1,0x87,0x39,0xc3,0x55,0x7f,
+  0xf9,0x49,0x1e,0xa6,0x20,0x79,0xa7,0x7e,0x0a,0x14,0xe4,0x2f,0x23,0x94,0xa6,0xa8,
+  0x33,0xa7,0xb4,0x8a,0xc7,0xa5,0xcc,0x50,0x45,0x9f,0x1a,0x73,0xf3,0x5f,0xb6,0xd4,
+  0x1e,0xf1,0x5f,0x42,0x7f,0xfe,0x28,0xaf,0x48,0x6b,0x2d,0xec,0x35,0xfe,0x52,0xe2,
+  0x36,0x23,0x84,0x2d,0x9e,0x83,0x89,0xea,0x73,0x60,0xc7,0xc5,0x0d,0xdf,0xe2,0x2a,
+  0xd6,0xec,0xe0,0xaf,0x16,0xbf,0xf7,0x62,0x87,0xd4,0x9f,0x1f,0xbc,0x08,0xb1,0x6c,
+  0x09,0xe1,0xaf,0x0b,0xb0,0x50,0x45,0x3f,0xbc,0x2f,0x35,0x8a,0x4e,0xf2,0xd3,0xa4,
+  0x48,0xff,0xad,0x4c,0x43,0x76,0x5a,0x64,0xc1,0xc9,0xe2,0x6f,0x41,0xe3,0x70,0x20,
+  0xf2,0xf9,0xcd,0x7f,0x7d,0x11,0x1a,0xfb,0xff,0x25,0xf2,0x79,0x57,0xfe,0xd7,0x84,
+  0x4d,0x72,0xb5,0x5e,0x83,0x06,0xa9,0x3f,0x2f,0x92,0x8f,0x88,0x20,0xfe,0x54,0xbf,
+  0x43,0x0f,0x64,0xca,0x29,0x82,0x34,0x66,0xfd,0x0b,0xde,0x33,0xed,0x1a,0xfb,0x2e,
+  0x75,0xef,0xe4,0x4d,0xf8,0xa9,0xde,0x5b,0x33,0x37,0xc8,0xff,0x0a,0x0b,0x98,0x2c,
+  0xd2,0x06,0x2f,0x3a,0x72,0xb2,0xf8,0x92,0x6c,0x2d,0x95,0x99,0x77,0x8f,0xe0,0x30,
+  0x11,0x23,0xc6,0x1e,0xb1,0xdc,0x01,0x06,0xd7,0xe7,0x7f,0xd1,0x46,0xff,0x0f,0x56,
+  0x07,0x9d,0xfb,0xbd,0x0b,0x39,0x46,0x6c,0x8e,0x55,0x10,0x76,0x68,0x1b,0x9f,0x75,
+  0x8c,0xe6,0xeb,0xf3,0xbf,0x6c,0xc1,0x7f,0xea,0xc3,0x17,0x29,0xbd,0xae,0x85,0x3d,
+  0x00,0x7b,0x78,0x75,0xdc,0xb7,0x3e,0x81,0xbd,0xda,0x56,0x9d,0x3d,0xb1,0x3e,0x88,
+  0x46,0x42,0x88,0xd5,0xbf,0xed,0x24,0x82,0x5d,0x97,0xff,0x15,0xf4,0xe7,0x06,0x17,
+  0x9e,0x61,0x15,0x83,0xda,0xfa,0xa2,0xb3,0xb0,0x81,0xcd,0xb1,0x66,0xd6,0xb3,0x57,
+  0xd0,0xa5,0x71,0x86,0xdb,0xeb,0x88,0x3c,0x4b,0x6a,0xac,0x80,0xff,0x12,0x29,0x5d,
+  0x21,0x77,0xd9,0xaf,0x06,0x1e,0xd8,0x9b,0xf8,0xef,0xc6,0xb3,0x10,0x3b,0x4a,0x15,
+  0xc1,0x42,0x57,0x79,0x3e,0x35,0xcc,0x31,0x6a,0x88,0x2c,0xcb,0xf3,0x5f,0xde,0xeb,
+  0xb5,0x0d,0x47,0xe0,0x3b,0x8c,0xc6,0xcb,0xb8,0x04,0x8b,0xec,0x4b,0xba,0x4b,0x7f,
+  0xfe,0x3f,0xab,0xbf,0xac,0xbb,0x42,0xa7,0xe4,0x39,0xbf,0x1a,0x46,0xc7,0x3e,0xd9,
+  0x2f,0x44,0xf3,0x24,0x22,0x53,0xf3,0xc2,0x05,0x05,0x46,0x9e,0xff,0xd2,0x9d,0x90,
+  0x30,0xaf,0x4b,0x64,0xa3,0xc1,0x26,0x32,0xbc,0x85,0x61,0x87,0xd2,0xe8,0x74,0xb5,
+  0x64,0x6f,0xa0,0x3f,0x4f,0x62,0xe3,0x76,0xfd,0xe5,0x5a,0x53,0x1d,0x64,0x14,0x44,
+  0x57,0x61,0xfa,0x52,0x5e,0xf9,0x27,0x96,0xbb,0x14,0x11,0x73,0xcf,0xb9,0x41,0xfe,
+  0x17,0x1a,0x7e,0x51,0x7f,0x19,0x9e,0x6f,0xf8,0x7b,0x44,0x5b,0x89,0xd7,0x77,0xfd,
+  0x38,0xb4,0xf3,0x8b,0xbe,0xb2,0x84,0xbc,0x74,0xc3,0xda,0xc1,0x39,0xfe,0xcb,0xee,
+  0xb1,0x76,0xd2,0x60,0xf7,0xc6,0x74,0x59,0x88,0x39,0x1e,0x23,0xd8,0x95,0xe5,0x63,
+  0xc6,0xed,0x33,0x6b,0x12,0x1e,0x99,0xad,0x53,0x34,0x35,0x7f,0x87,0xfa,0x39,0xcf,
+  0x7f,0x79,0xd1,0x8d,0xa7,0xfc,0x2f,0x97,0xc8,0xfc,0xb8,0xd1,0x60,0x4e,0x4f,0x29,
+  0xfd,0xea,0x1b,0xd8,0x52,0x22,0xe8,0xaa,0x69,0x6e,0x57,0xdf,0x1d,0xf3,0x96,0xe7,
+  0xbf,0xae,0x4c,0xb9,0x64,0xe7,0x91,0xe9,0x68,0xfc,0xca,0x41,0xd0,0xef,0xcb,0xb0,
+  0xba,0x1b,0x3c,0xc7,0x85,0xbf,0x9c,0xfa,0x5f,0x3d,0x9e,0xb0,0x87,0x0c,0x2f,0xee,
+  0x17,0xbc,0x84,0xb3,0x61,0xef,0x80,0x40,0x64,0xcd,0x59,0x47,0xff,0xf0,0x7a,0xb1,
+  0xfa,0x29,0xf9,0x5f,0x2b,0xa8,0xa4,0x32,0xa9,0x6d,0x2c,0x75,0xd4,0x36,0x7c,0xfa,
+  0x67,0xfb,0xbd,0x6e,0xd9,0x79,0xb3,0xf8,0x46,0xfd,0xfc,0xda,0xf5,0xfa,0x1b,0x2e,
+  0x43,0x00,0xf0,0xc4,0x10,0x3f,0x64,0x12,0xa2,0x87,0x21,0xf3,0x50,0x45,0xee,0x9e,
+  0x52,0xf7,0xcd,0x77,0x3b,0xfc,0xd7,0x8c,0x1b,0xe9,0xc6,0x1f,0x4a,0xc5,0x5a,0x7d,
+  0x3b,0x94,0x77,0x61,0xbc,0x8d,0x92,0xbc,0xca,0x87,0x3c,0xef,0xc7,0xef,0xbf,0xae,
+  0x7f,0x6a,0xdc,0xfc,0x17,0xdc,0x50,0x7f,0x1e,0xec,0x11,0x3c,0x46,0xf8,0x2b,0x55,
+  0xfe,0x9e,0x4b,0xff,0x70,0x8a,0x71,0x5d,0xfe,0xd7,0x74,0x47,0x7f,0x5e,0xbc,0x24,
+  0x51,0x1d,0x81,0xd8,0xbd,0xe8,0x0a,0xd5,0xe9,0x42,0xff,0x90,0xaa,0x42,0xf8,0x6f,
+  0x34,0x4f,0x1d,0xfe,0xcb,0x1b,0x22,0x09,0x4a,0x3b,0xa5,0x8b,0xd5,0xf0,0x95,0x32,
+  0xc8,0x70,0x21,0xef,0x20,0x44,0x46,0x8c,0x98,0x6a,0x47,0x24,0x8a,0xfc,0x2f,0x6f,
+  0x81,0x58,0xfd,0x8d,0xf8,0x2f,0x26,0xb3,0x95,0x73,0xf5,0xbf,0x8a,0x65,0x65,0x8d,
+  0x1a,0x32,0x36,0xe7,0x96,0x38,0x6f,0x2e,0x8f,0xd5,0xfe,0xd4,0x71,0x67,0xff,0x72,
+  0xf2,0xbf,0x64,0xfd,0x65,0xbb,0xfe,0x17,0xaf,0xb0,0xd4,0x31,0xf6,0x15,0xd8,0xc2,
+  0xe7,0x59,0x2d,0xf5,0xec,0xac,0xe7,0x20,0x7c,0xe3,0x5d,0xcf,0x0d,0x16,0x6a,0x87,
+  0xff,0x0a,0x39,0xfc,0xd7,0xb7,0x99,0x8c,0x2d,0x14,0xf5,0xbf,0xae,0x65,0x0d,0x32,
+  0xbe,0x08,0xbf,0xe4,0x4d,0xc3,0x68,0xfc,0x08,0xfe,0x5f,0x34,0xa6,0xad,0x2f,0xcc,
+  0xff,0x5a,0x9c,0xbd,0x11,0xff,0xa5,0x88,0xc0,0xb6,0x9c,0x68,0x43,0xaf,0x48,0x50,
+  0x9a,0x90,0x82,0x5d,0xc2,0xa5,0x19,0x70,0x74,0x21,0xdc,0x81,0x88,0xd3,0x5d,0xf1,
+  0x87,0xd7,0x52,0x8b,0x88,0xff,0x8a,0xf9,0xaf,0xf1,0xc0,0x25,0x5b,0x7f,0xbe,0xfb,
+  0xdd,0xc0,0x98,0xf6,0xb6,0xf9,0x1c,0x6f,0xba,0x50,0x42,0xb2,0x1b,0xa7,0xf9,0x77,
+  0x2f,0xf9,0xc7,0x2a,0x6d,0x67,0xd2,0x95,0xa8,0xe2,0x8a,0x3f,0x7c,0x29,0x4d,0xbb,
+  0x55,0x33,0x76,0x94,0x5e,0x92,0xb5,0xf3,0xbf,0xe6,0x89,0x6c,0x2f,0xeb,0x19,0x5e,
+  0x6d,0x95,0xac,0x67,0x5f,0x36,0x37,0x78,0xbe,0x31,0x54,0xb2,0x2e,0x48,0xa5,0xd3,
+  0xee,0x2c,0xd8,0xc8,0xdc,0xfc,0x97,0x4e,0xaa,0x26,0x86,0x4b,0xf0,0xbf,0x1b,0x2a,
+  0xde,0xc0,0xb1,0x68,0x54,0x45,0x41,0xe7,0x75,0xdb,0x26,0xf5,0x67,0x70,0x43,0xec,
+  0x14,0x1f,0xf7,0x56,0xdb,0x81,0x88,0xf2,0x66,0x77,0xfe,0x97,0x8c,0xdb,0xf1,0xeb,
+  0x79,0x9f,0x64,0x07,0xb6,0x34,0xb0,0x12,0xd8,0xcd,0xc3,0x97,0x10,0x91,0x7d,0x11,
+  0x92,0x7a,0xee,0x95,0x08,0xb9,0xc6,0x3d,0x93,0xd7,0x3f,0xa4,0xd2,0x69,0x75,0x94,
+  0xff,0x15,0x46,0x5f,0xab,0xc9,0xc9,0xed,0x8a,0x5a,0xab,0x1a,0x5f,0xae,0x1d,0x78,
+  0xee,0x9e,0x26,0x4b,0xed,0x59,0xfa,0x71,0xf0,0x65,0xab,0xc9,0x2a,0x96,0x11,0x2f,
+  0x35,0x4e,0x3f,0x93,0xc1,0x5c,0xf1,0x87,0x85,0x69,0x5f,0xb6,0x91,0x95,0x3a,0x6f,
+  0xac,0x71,0xa0,0x56,0x8e,0xd7,0x23,0x52,0xeb,0xde,0x1e,0x4a,0x57,0x74,0xd6,0x14,
+  0xfd,0x0d,0x77,0x9c,0xd5,0xef,0xc1,0x29,0xfb,0x85,0x2d,0x61,0x81,0xc8,0xd4,0x05,
+  0xb6,0x92,0xb3,0x14,0x25,0xa0,0x9b,0x6f,0xb5,0x66,0x8f,0x2a,0x53,0xf4,0x37,0x56,
+  0x4c,0xf1,0xfd,0x82,0x79,0xfd,0x0d,0xd5,0xc9,0xf6,0x52,0xa4,0x10,0x47,0xcc,0xed,
+  0x1f,0x2a,0xf7,0x3a,0xf8,0x6b,0xad,0x90,0xda,0xbb,0x5e,0x7f,0x5e,0xcb,0x14,0xad,
+  0x75,0xa4,0x39,0xe4,0x73,0x92,0xf9,0x7b,0xca,0x64,0x20,0x62,0x67,0x26,0xa7,0xbf,
+  0x01,0x7e,0x92,0xe4,0x25,0x17,0xe2,0x55,0xb7,0xba,0x57,0xba,0x0f,0x1f,0xe8,0x37,
+  0xbb,0x2b,0x29,0x40,0x2e,0x41,0xd9,0x79,0xdc,0xf2,0xd8,0xf1,0x87,0x52,0xaf,0x72,
+  0x81,0x1c,0xaf,0x66,0x1b,0x7f,0xa9,0xb6,0xc8,0xc6,0xff,0x23,0x44,0xc2,0xed,0x00,
+  0xa7,0x0f,0xd5,0xe8,0x40,0x20,0xb3,0x60,0xad,0x70,0xf9,0x4a,0xbb,0xf0,0xaf,0x4f,
+  0xfc,0xe5,0xed,0xb6,0x34,0xbd,0xe7,0xfe,0x5e,0x51,0x14,0xe0,0x3b,0x32,0xb1,0xc8,
+  0xad,0xbf,0x51,0xdf,0x24,0x8b,0x2c,0x5f,0x73,0xf4,0x37,0x9c,0xfa,0x5f,0x6d,0xd7,
+  0xcc,0xc5,0x14,0x90,0x76,0x16,0x72,0xd2,0xf4,0xd7,0xcc,0xa6,0x01,0xb7,0x3f,0xef,
+  0xe2,0xbf,0xae,0x7a,0x17,0x98,0xe2,0x18,0xea,0xac,0x37,0x0a,0xa7,0xc7,0x96,0x52,
+  0x46,0x58,0x37,0xf8,0x2d,0x44,0x7f,0x38,0x89,0xa0,0x84,0xca,0x3a,0x1c,0x21,0xd8,
+  0x35,0xb8,0x94,0x18,0xcc,0x68,0xf6,0x56,0x2a,0x04,0x36,0x01,0x77,0x99,0x7e,0x2b,
+  0xaf,0x3f,0xff,0xb1,0x88,0xbb,0x50,0x7b,0xd8,0xfd,0xd0,0x41,0x21,0xd6,0x88,0xad,
+  0xf4,0x7a,0x08,0x76,0x20,0xbc,0x9d,0x4b,0xbd,0x6a,0xa8,0x8e,0xec,0xa1,0xb6,0x43,
+  0x30,0x98,0xbb,0x64,0xb0,0xe2,0x21,0x1e,0x3c,0x87,0x18,0x2d,0xa7,0x3f,0x4f,0xc9,
+  0x74,0x86,0x19,0xa2,0xb0,0xc3,0x6d,0xe2,0x9d,0x6f,0x16,0xf5,0xa4,0x9a,0x71,0xdb,
+  0x52,0xa9,0xe7,0x41,0x4c,0x87,0x27,0x65,0x8c,0xbd,0x1f,0x12,0x76,0xce,0xec,0x8c,
+  0xfd,0xac,0x8a,0xf2,0x97,0x5d,0xf8,0x2b,0xc3,0xd1,0xc9,0xe1,0xa4,0x2f,0xc1,0xe7,
+  0x67,0x85,0x5a,0x4b,0x8f,0x3e,0xbf,0x5d,0x6d,0x67,0x06,0x09,0x69,0x82,0xcf,0x81,
+  0x5d,0x5a,0xcf,0xb3,0xfe,0x99,0xf9,0xdc,0x40,0xfd,0x27,0x99,0x50,0x07,0x73,0xe9,
+  0x1f,0x5e,0xa6,0x63,0x9f,0x84,0xf2,0x1f,0xf0,0x96,0xd5,0x10,0x95,0x07,0x4a,0xd0,
+  0x60,0xf8,0x7f,0x5a,0x4e,0x1e,0x75,0x63,0x56,0x04,0xfe,0x09,0x05,0xf8,0x9e,0x72,
+  0xa2,0x2d,0xa2,0x32,0x7f,0xe7,0x32,0xaf,0x8b,0xfb,0x3b,0x92,0xbf,0xca,0xe1,0x2f,
+  0x15,0x21,0x70,0x15,0x4e,0xa2,0xbb,0x5b,0x2f,0xc2,0x22,0xc9,0x7f,0x5d,0xe5,0x0b,
+  0xb3,0xb5,0x6b,0x10,0x7d,0x5d,0x53,0x9b,0x86,0x4a,0x72,0xa3,0x13,0x51,0x26,0x0d,
+  0x1c,0x2f,0x4b,0x68,0x24,0x7e,0xca,0x6f,0x47,0x9f,0x1f,0xec,0xfa,0x5f,0xad,0xfa,
+  0x3e,0xf5,0xb2,0x1a,0x6d,0x29,0x49,0x2b,0x15,0x14,0x64,0x98,0x90,0x09,0x9b,0x66,
+  0x70,0x89,0x7f,0xfb,0x93,0xa1,0x76,0x4d,0x26,0x63,0x8a,0xb5,0xb7,0x7f,0xcb,0x01,
+  0x65,0x1f,0x3b,0x6e,0x90,0x46,0xc7,0x5f,0x8d,0xe8,0x97,0xa1,0xab,0xd5,0xbf,0x5d,
+  0x79,0x3d,0x8f,0xbf,0x7a,0xe2,0xc1,0xf5,0xb8,0x37,0x19,0x9e,0x4e,0x4f,0x30,0xa5,
+  0x39,0x40,0xac,0x24,0xc1,0x2a,0x49,0x96,0x44,0x1e,0x9d,0x09,0x4c,0xfd,0x63,0xd6,
+  0x64,0xe4,0xfb,0xc7,0x08,0xbe,0xa0,0x7e,0x2f,0xe1,0xc2,0x5f,0x54,0xb2,0x61,0x1e,
+  0x30,0x74,0x50,0x70,0x6d,0x13,0x40,0xec,0x48,0xca,0x00,0xb5,0xd1,0xe7,0x59,0x82,
+  0xc3,0x04,0x8e,0x6c,0xd4,0xf0,0x2d,0x3a,0x0b,0xc0,0x46,0x27,0xc7,0x39,0xd5,0x61,
+  0xac,0x53,0xbd,0x0e,0xfe,0xea,0x21,0xfe,0x4b,0xd0,0x31,0xac,0xb4,0xa3,0x9d,0xdf,
+  0x1b,0x92,0xb2,0x87,0xa9,0x39,0x46,0x71,0x88,0x7d,0x56,0xfd,0x7e,0x5b,0xf5,0xea,
+  0x62,0x47,0xa0,0x4f,0xbb,0x87,0xfd,0xc8,0x7a,0xd4,0xd1,0xe8,0xd8,0x9f,0xda,0x59,
+  0xa5,0xb6,0xe0,0x17,0x93,0xf8,0x4b,0xf5,0xc3,0x79,0x33,0xd2,0x52,0x72,0xb3,0x4f,
+  0xe1,0xdc,0x8c,0xac,0x91,0xfa,0x1b,0xa6,0x41,0x69,0x5f,0x3e,0xf3,0xd7,0xd0,0xd8,
+  0x5e,0x1a,0x51,0x36,0xc3,0xc5,0x74,0x63,0x36,0x70,0x93,0xb6,0x99,0x1f,0x37,0x22,
+  0xd9,0xe9,0x54,0x9a,0xf9,0xb5,0x74,0x66,0x99,0x5f,0x2f,0x77,0xe1,0xaf,0xa3,0xf0,
+  0x92,0x59,0xfb,0xab,0x72,0xa2,0x8c,0x63,0x5e,0x67,0xee,0xe0,0x58,0xb0,0x51,0xf8,
+  0x84,0x64,0x37,0x32,0x0a,0x62,0xea,0x9b,0x70,0xea,0x59,0xca,0xc3,0x69,0x67,0xad,
+  0xf3,0x1e,0xf1,0x2c,0xf6,0xd6,0x0e,0x16,0xe6,0x7f,0x51,0xe5,0xeb,0xf2,0x1a,0x2a,
+  0x7b,0x6a,0x88,0x7a,0x01,0xc3,0xf0,0x13,0xf0,0x67,0x64,0x22,0x18,0xcf,0xa5,0x7d,
+  0xa1,0x97,0x32,0x42,0x19,0xf1,0xf6,0x02,0x4b,0x07,0xd1,0xdc,0xc1,0x5f,0x03,0xb8,
+  0x7f,0x1d,0x80,0x34,0x84,0x22,0x6c,0x16,0xba,0xd2,0xb5,0x20,0xf6,0xf7,0x3a,0xa8,
+  0x34,0x7d,0x71,0x96,0x0b,0x32,0xb4,0x77,0x99,0xd6,0xe0,0x59,0xfe,0xa8,0x03,0xcd,
+  0xba,0x61,0x1e,0xa8,0x71,0x27,0xfe,0x90,0x23,0xfe,0xca,0xd8,0xfd,0xec,0x69,0x47,
+  0xb4,0x45,0x49,0x5e,0xfa,0x1d,0xd8,0x99,0x2d,0x33,0x83,0x37,0x53,0xd4,0xfd,0xae,
+  0x16,0x12,0xfc,0x17,0x68,0xeb,0x1e,0xec,0xde,0x9f,0x38,0xfd,0x7c,0x10,0x8c,0xb8,
+  0x7a,0x8f,0x1b,0x7f,0x65,0x4c,0x1c,0xc1,0x3b,0x8b,0x02,0x4b,0x38,0x0f,0xcf,0x14,
+  0xfc,0xd7,0x11,0xee,0xb3,0x36,0x15,0x33,0x85,0x86,0x7b,0x70,0x7e,0x6e,0xb7,0x2a,
+  0x41,0x4f,0x26,0x97,0xdb,0x7e,0x04,0xe7,0xf6,0xcc,0x98,0x1b,0x7f,0x5d,0xd5,0x17,
+  0x64,0xc2,0x59,0xa5,0x9e,0x9d,0xb2,0x9a,0x52,0x52,0xff,0x30,0xbb,0x20,0xe5,0x1d,
+  0x56,0xee,0x34,0x2e,0x43,0x53,0x26,0x2c,0x85,0xe8,0x45,0x8e,0xd8,0x30,0x7c,0xec,
+  0x04,0x72,0x5c,0x35,0x16,0xf0,0xf0,0x48,0x61,0xfc,0x61,0x63,0x91,0x0c,0x32,0x8c,
+  0x48,0x9f,0x4d,0xa5,0x74,0x7e,0x32,0x42,0x63,0x42,0x85,0xcf,0xf1,0xe2,0x12,0xa2,
+  0xd2,0x90,0xe3,0xd7,0xb5,0xc4,0x8c,0x40,0xdb,0x94,0xf8,0xc3,0x75,0x61,0x5d,0xa6,
+  0x11,0xad,0x93,0xb2,0xf3,0xa9,0x68,0x73,0x09,0x45,0x1b,0x8e,0xf3,0xc3,0x77,0xe7,
+  0x65,0xe2,0x74,0xa5,0x68,0xd9,0xb1,0x9c,0xd4,0x1e,0x8f,0xae,0xc3,0x16,0x37,0xff,
+  0x65,0x52,0x24,0xa1,0x0f,0x1d,0x69,0x4f,0xcd,0x3a,0xc2,0x4d,0x2a,0x09,0x29,0xf8,
+  0x66,0xb3,0xb9,0x70,0x8e,0x3f,0x9b,0xc3,0x5f,0x6b,0xb5,0xa7,0xa8,0x5c,0x72,0xab,
+  0xa3,0xb1,0x30,0x18,0x5c,0x83,0x2b,0xa4,0x3b,0xff,0x2b,0x2e,0x38,0x32,0x01,0xc4,
+  0x6c,0x41,0x7b,0x35,0x68,0x16,0x6f,0x83,0xaa,0xd4,0x21,0xe3,0x59,0x6b,0x53,0x4e,
+  0x91,0x5e,0x24,0x94,0xa9,0xf3,0xe5,0x73,0x8e,0x50,0xf4,0xda,0xb6,0x82,0xfc,0x2f,
+  0x91,0xf6,0xc5,0x04,0x10,0xa3,0xb2,0xcb,0x54,0x7f,0x39,0x8d,0x2d,0xc1,0x22,0xd8,
+  0xa9,0xef,0xb5,0xf2,0x71,0x71,0x65,0x8f,0x79,0x79,0x5b,0x44,0x6a,0x47,0xe8,0x47,
+  0x42,0xc6,0x72,0xe5,0xe6,0x84,0x9b,0xff,0x12,0x69,0x5f,0x49,0x23,0x3d,0x16,0x8a,
+  0xdd,0x2c,0x02,0xc9,0x46,0xb1,0xa5,0x84,0x5a,0x2e,0x9b,0x0d,0xbe,0x52,0x57,0x3f,
+  0xe3,0x42,0x6c,0x3a,0xb5,0x00,0x8c,0xa8,0x1a,0x48,0x68,0xee,0xfc,0xaf,0x8a,0x97,
+  0x88,0xff,0x12,0x31,0x81,0x2d,0x1e,0x21,0xa0,0x21,0x12,0xc1,0xe6,0x5d,0x82,0xf7,
+  0x8d,0x97,0x72,0x4a,0x11,0xcb,0x03,0x83,0x95,0x43,0xd9,0x2b,0xb7,0xdb,0x02,0xe9,
+  0x57,0x3c,0x22,0xdb,0xab,0x00,0x7f,0xdd,0x4e,0xb5,0x83,0xab,0x1c,0x49,0x8d,0x21,
+  0x91,0xed,0x55,0x2a,0x9f,0xbc,0xc0,0x89,0x94,0x6b,0x72,0x88,0xb0,0x9c,0x58,0x87,
+  0x48,0x0d,0x73,0xd7,0xff,0xf2,0xee,0x82,0x90,0x8c,0x85,0xa8,0x81,0x6a,0x2a,0xbb,
+  0x2c,0x64,0xe7,0x25,0xc8,0xda,0x25,0xcb,0x49,0x93,0x62,0xef,0x0f,0xe9,0x9e,0x44,
+  0x81,0x34,0xbd,0x5b,0x7f,0x5e,0x56,0xf2,0xc2,0x7e,0xa6,0x3a,0xd7,0x0e,0xda,0xaa,
+  0xa2,0x63,0xc3,0x57,0xc4,0x16,0x99,0x87,0x5d,0xf5,0x22,0xec,0x30,0x07,0xc4,0xa6,
+  0xd6,0xff,0xc2,0x75,0x75,0xb9,0x18,0xf7,0x8d,0xaa,0x8d,0xdf,0xf7,0x9b,0x73,0x4d,
+  0xdf,0x0e,0x86,0xb0,0x0b,0x82,0x08,0xc4,0x98,0x8d,0xd1,0xb6,0xf9,0xbc,0xb0,0xd1,
+  0x90,0x92,0x98,0x70,0xa8,0x22,0xe1,0xae,0xff,0x75,0x13,0x49,0xc1,0x77,0xb5,0x86,
+  0x7f,0x44,0xb1,0x10,0x3c,0xd6,0x6c,0x47,0x1b,0xbe,0x70,0x5f,0xe9,0xd3,0xc9,0x77,
+  0x05,0x3f,0x58,0x22,0x15,0x23,0xb1,0x7b,0x9f,0x2e,0xaf,0xf2,0xe0,0x3d,0x4e,0x8f,
+  0x45,0x5b,0xf2,0xfc,0xd7,0x1a,0x3b,0xff,0xab,0xf6,0x07,0x54,0x7f,0xd9,0x68,0x5c,
+  0x67,0x63,0xab,0xfa,0x96,0x12,0xc2,0xb0,0x85,0x68,0x4b,0xa7,0xba,0x78,0xdc,0x69,
+  0x69,0x6f,0x6c,0x9e,0xa2,0x3f,0xaf,0x46,0x20,0x4c,0xfc,0xd7,0xb0,0x89,0xb0,0xdd,
+  0xd6,0x3f,0xd4,0xfd,0x8f,0x49,0x91,0xc3,0x22,0x67,0x9e,0xaa,0xa5,0x7c,0xfa,0x3b,
+  0x42,0xa3,0x83,0xde,0x31,0xef,0x98,0xda,0x05,0x2b,0xb9,0x5b,0xff,0xf0,0xc5,0x78,
+  0x25,0x82,0xac,0xf2,0x35,0x6c,0x13,0xd4,0xee,0x2a,0x15,0x22,0x1b,0xd9,0x20,0x0f,
+  0x65,0x59,0x83,0xfe,0x04,0x9f,0xb7,0xd5,0x4e,0xfb,0xaa,0xcd,0xa8,0x54,0x76,0xfd,
+  0x09,0x5b,0x11,0xd1,0xfb,0xc2,0xc0,0xa2,0x6d,0xea,0x50,0xc2,0xcd,0x7f,0x59,0xe9,
+  0x5e,0x95,0xd4,0x95,0x77,0x43,0x38,0x12,0x92,0xce,0x9b,0x61,0xa9,0x2a,0xf3,0x44,
+  0x36,0xa6,0x42,0xf1,0x8d,0xf6,0x3a,0x96,0xd5,0xe8,0xfb,0x25,0xa9,0xec,0xb2,0x68,
+  0x31,0x43,0xe7,0x5b,0x1a,0x13,0x79,0xfe,0xcb,0xd3,0x0d,0xbb,0xa9,0xfc,0xca,0x97,
+  0xe1,0x19,0xf2,0x52,0xd6,0x89,0xe0,0xb7,0x8a,0x01,0x75,0x16,0x2b,0x33,0x1e,0x85,
+  0x50,0x2e,0x2d,0x97,0x2a,0x82,0xf5,0xfb,0x36,0x74,0xdc,0x6b,0x7d,0x4e,0xb6,0xec,
+  0xa3,0xcc,0x32,0x17,0xff,0x75,0x90,0xdf,0x9e,0xf6,0xaf,0x57,0x4a,0xe1,0xf7,0x7c,
+  0xb1,0xe1,0x5f,0x5f,0x89,0xf8,0x8b,0x47,0x86,0xfd,0x2d,0x1a,0xd3,0x4f,0xf1,0x3b,
+  0x0d,0x81,0xc8,0xfe,0x5f,0x42,0x37,0xeb,0xd9,0x9b,0xf0,0x0b,0x47,0xa3,0xe3,0x22,
+  0xbf,0x33,0x1b,0x5e,0xef,0xd6,0xdf,0xb8,0xec,0xf0,0x5f,0x6f,0xb1,0x18,0x94,0x66,
+  0x0c,0xe1,0xe1,0xf7,0x07,0xec,0xb4,0x2f,0x70,0x32,0x8c,0xcc,0x2d,0x22,0x8d,0x28,
+  0xef,0xf3,0xbf,0xe0,0xca,0xff,0x92,0xf1,0x87,0x54,0xed,0x4b,0xa8,0x1d,0x36,0x55,
+  0x09,0xb4,0x75,0x2d,0x75,0xd7,0x50,0xe9,0xb0,0xd6,0x80,0x6f,0xd4,0x82,0x0a,0xa9,
+  0x48,0xdf,0xd6,0xb4,0x7a,0xe3,0xfb,0xf8,0x35,0x4e,0x6c,0x5d,0x90,0x9d,0x46,0xfe,
+  0xe1,0x35,0x5e,0x79,0x6e,0xe5,0x18,0xae,0x00,0x79,0xfe,0x8b,0x57,0xf4,0x57,0xdb,
+  0x69,0xcb,0x86,0xc0,0x5f,0x8b,0x28,0x12,0xc3,0x64,0x9f,0x33,0x1f,0xe7,0x15,0x2a,
+  0xfe,0x0a,0x44,0x64,0x50,0xbb,0x26,0x20,0xa8,0x31,0xbc,0xb9,0xf8,0x9b,0xec,0x6d,
+  0xf3,0xf9,0xbd,0x15,0x03,0x2d,0xdf,0x2c,0xd0,0x3f,0xc4,0xe5,0x13,0x9d,0x8a,0x59,
+  0x06,0x3e,0xa7,0xe5,0x16,0x7a,0x4e,0x04,0x42,0x03,0x3e,0xaa,0xcc,0xf4,0x4f,0x9e,
+  0x0a,0x8f,0x9d,0x79,0x57,0xbd,0x4c,0x74,0xf8,0x6e,0x7b,0x1f,0x6c,0x79,0x41,0xdf,
+  0xb9,0x6d,0xe3,0x3a,0xb7,0xfe,0x61,0x86,0x44,0x90,0x16,0xfa,0x4a,0xa0,0xbb,0xb9,
+  0x46,0x17,0x65,0x53,0x52,0xdb,0x8c,0xac,0x0a,0x09,0x95,0x8a,0xe3,0xe8,0xb6,0x10,
+  0x22,0x31,0xd7,0x38,0x3d,0x77,0x99,0x86,0x04,0x62,0x19,0xcb,0x48,0x17,0x37,0x32,
+  0xd5,0x85,0xbf,0xb2,0xd1,0x77,0x7c,0x99,0x64,0x35,0x39,0xf6,0xa3,0x76,0x0c,0xe7,
+  0x91,0xdf,0x94,0xb6,0x2b,0x73,0x28,0x70,0x7d,0x86,0x7d,0xbe,0x1a,0xb3,0xc2,0x07,
+  0xca,0x47,0x7c,0x1f,0x40,0xd4,0xc6,0x4d,0x66,0xd7,0xe8,0x37,0x32,0x5a,0xa1,0xfe,
+  0xa1,0x9d,0xa6,0xa7,0xc6,0x36,0xdb,0x7e,0x66,0xa3,0x85,0x73,0xa7,0x8f,0xbf,0x0f,
+  0x8d,0x79,0x79,0x81,0xc0,0x51,0xc4,0x0e,0x37,0x23,0x10,0x73,0x94,0x93,0xad,0xd2,
+  0x03,0x6e,0xfc,0xf5,0x29,0x74,0xb7,0xfb,0x47,0x93,0xe8,0x43,0xc2,0x74,0x91,0xe4,
+  0x05,0xbf,0x81,0xcf,0x93,0x8c,0xde,0x33,0xb8,0x7b,0x36,0x81,0x3f,0xe7,0x67,0x0e,
+  0xbe,0x7c,0x95,0xff,0xa2,0x65,0x81,0x25,0x72,0x97,0x26,0xd4,0x60,0x3c,0x10,0x49,
+  0xda,0xf5,0xbf,0x38,0xe2,0xaf,0xc3,0xf1,0xbc,0x5c,0x7c,0x46,0xca,0x6e,0x98,0xf3,
+  0xad,0x92,0xc7,0x9b,0xe7,0x52,0xa9,0x29,0xdd,0x91,0x2b,0x5c,0x87,0xbb,0xd5,0x90,
+  0xda,0x61,0x4a,0xff,0xd0,0xdb,0x3d,0x1a,0x8c,0x97,0x1e,0x2d,0xac,0xff,0x95,0xcb,
+  0x11,0x9b,0x8b,0xcf,0x21,0x6d,0x0d,0x13,0xe1,0xdb,0x01,0xbc,0x67,0x23,0xaf,0xd9,
+  0xa4,0xda,0x82,0xe4,0xbb,0xb4,0x9e,0xc4,0xab,0xd0,0xb1,0x24,0x48,0xb0,0x8b,0x5a,
+  0x9e,0x7d,0x5d,0x3b,0xea,0xd6,0x3f,0xec,0xaa,0x40,0x5c,0x60,0x1f,0xe6,0xef,0x90,
+  0xc9,0x98,0xca,0xde,0xbe,0x62,0x8a,0x6b,0xda,0x49,0xe7,0xfc,0xa4,0x4e,0xb9,0xa0,
+  0x2c,0xdc,0x27,0x34,0x3a,0x38,0x80,0x38,0xef,0x4d,0xed,0xd7,0x43,0xd6,0xdf,0x50,
+  0x5e,0xad,0x7c,0x7d,0x4a,0xd6,0xc2,0xc5,0x50,0x84,0xd7,0x3c,0x5f,0xf9,0x91,0x79,
+  0x04,0xea,0xee,0x11,0xfe,0xd8,0x58,0x30,0x36,0xe0,0x4f,0x6b,0x15,0x2d,0x94,0x21,
+  0x12,0xee,0x4a,0x8a,0x5e,0x95,0xd2,0x1c,0xc5,0x46,0x94,0xa8,0xb1,0x9f,0xf2,0xcb,
+  0x6b,0x1a,0x60,0x55,0x46,0x83,0x3c,0xfe,0x1a,0x87,0x1c,0xfe,0xaa,0xf1,0x0b,0xff,
+  0x70,0x8c,0xb2,0x51,0x28,0x39,0xeb,0xdf,0xf5,0xc5,0x14,0xc4,0x4b,0x11,0x89,0xb8,
+  0x7f,0x8d,0xc2,0x25,0x75,0x52,0x6f,0x3a,0x8e,0x1e,0xfe,0x95,0xcc,0x84,0xb1,0xc8,
+  0x2a,0xcd,0x5e,0x57,0x7f,0x99,0xa6,0xd5,0xa4,0x51,0xa7,0xae,0xea,0xc3,0x8f,0x8f,
+  0x19,0xb1,0x92,0x00,0x1a,0xed,0x93,0x15,0x4d,0xc5,0xab,0x12,0xc4,0xa3,0x55,0xc5,
+  0x54,0xdc,0xbf,0xde,0xa6,0x18,0x21,0xd3,0xef,0x3a,0xdf,0xc8,0xf1,0x5f,0x23,0x92,
+  0xd2,0xea,0x4a,0x8c,0x78,0x26,0xfa,0x6b,0x46,0xb1,0xeb,0xfe,0x01,0x8e,0x58,0x0d,
+  0xfd,0x68,0x7c,0xdc,0x72,0x24,0x55,0x33,0xa4,0x1d,0xaa,0xfc,0x04,0x5b,0xd0,0xd8,
+  0x47,0xa5,0x99,0x41,0xd4,0xff,0xca,0x11,0x61,0xd9,0xeb,0xf5,0x0f,0x3b,0x32,0x7a,
+  0xd8,0xab,0x79,0x98,0x65,0xa2,0x01,0x64,0xe4,0x32,0xc2,0x9c,0x96,0x53,0x54,0x8e,
+  0xdc,0x74,0x27,0xc6,0xbe,0x73,0x83,0xfc,0xaf,0xbd,0x72,0xaf,0xbc,0x17,0x7a,0xd4,
+  0xf9,0xa0,0xb5,0xb1,0x73,0x74,0x68,0xe9,0xd5,0x78,0x5f,0xba,0x8a,0xb2,0xa7,0x3b,
+  0x11,0xa3,0xe9,0x87,0xf9,0xdc,0xb8,0xfd,0xb2,0xdd,0x7f,0x63,0xfe,0x6b,0x04,0x0e,
+  0xa5,0x63,0x77,0x07,0xb6,0xe3,0xb6,0x85,0x8b,0xd5,0xdd,0x81,0xa7,0x5f,0x7e,0x17,
+  0x0e,0x5b,0x35,0x6b,0x02,0x9b,0xd9,0x87,0x14,0xa3,0xb8,0x26,0xf0,0x23,0x5c,0xc7,
+  0x2e,0xa7,0xeb,0xd6,0xe5,0x3c,0xea,0x55,0x99,0xca,0x1b,0xf1,0x5f,0x97,0xb7,0x37,
+  0xed,0x09,0xbc,0xaf,0xac,0x31,0xaf,0xe9,0x4d,0xed,0xe8,0x55,0xbe,0x8f,0x0e,0x1e,
+  0x3a,0xf6,0x87,0x94,0xa1,0x96,0x2b,0xdb,0x63,0x7b,0x03,0x1f,0x28,0x54,0x5c,0xa0,
+  0x1e,0x6a,0xff,0xff,0xf0,0x5f,0x97,0xcd,0x68,0xca,0xbf,0x47,0x99,0x47,0xb2,0x1b,
+  0xd2,0x38,0x46,0xf5,0x6a,0x0f,0x90,0x7a,0xb0,0x97,0x1c,0xfb,0xa5,0x43,0x70,0xdc,
+  0x6c,0x68,0xcd,0x7b,0xf8,0x2e,0xfd,0xc3,0x6a,0x33,0xd7,0x3f,0x87,0xc5,0x69,0x21,
+  0x6e,0x01,0x9d,0x8e,0xb1,0x91,0x76,0xab,0x8c,0xd4,0x67,0xa3,0x28,0xdc,0x21,0x0a,
+  0xc7,0x05,0xf5,0x3f,0xe1,0xbf,0x9c,0xe3,0x88,0x2e,0x48,0xf3,0x90,0xe1,0x53,0xd9,
+  0x6e,0xc7,0x68,0x83,0x2c,0xa7,0xc0,0x1b,0x72,0x45,0xb0,0x05,0xa1,0xf4,0x46,0x5e,
+  0x28,0x24,0x35,0x56,0x58,0x7f,0x59,0xb8,0xfa,0xcf,0x73,0x63,0x0d,0xba,0x22,0x9f,
+  0xc5,0xa7,0xa0,0xcf,0x3f,0x13,0x3e,0x4b,0x49,0xca,0xab,0xb5,0x2f,0xb0,0x9b,0xf5,
+  0x7f,0xe2,0xd5,0xab,0x45,0xb4,0x21,0x3f,0x30,0x27,0x2f,0x10,0x81,0x9f,0x3a,0x33,
+  0xa5,0xfe,0x32,0xc2,0x2e,0xf3,0xbc,0x11,0x89,0x23,0xec,0xf2,0xe2,0x97,0x88,0xac,
+  0x51,0xc9,0xe8,0xb3,0x22,0x66,0xc0,0xa7,0xa8,0xbc,0x2f,0xde,0xb8,0xda,0x0f,0xca,
+  0x80,0xf9,0x32,0xde,0xbc,0x32,0x32,0xfd,0xa4,0x49,0xfc,0x57,0xa0,0x50,0xff,0xd0,
+  0x56,0xb3,0x51,0xff,0x87,0x74,0xde,0x2e,0x99,0x67,0x75,0xa1,0x7d,0x7d,0x09,0x21,
+  0x43,0xd3,0x12,0x9c,0x20,0x63,0xf0,0xb1,0x07,0x8d,0xde,0xe9,0x63,0xd6,0x55,0x99,
+  0xe2,0x9a,0xab,0x35,0x9f,0xc3,0x5f,0x1f,0xe7,0xcb,0x32,0x12,0x89,0x5c,0xed,0x9c,
+  0x6b,0xf9,0x73,0x46,0x8f,0x52,0x03,0x27,0xda,0xa2,0x59,0xff,0xb3,0x4a,0x95,0x8e,
+  0x43,0x69,0x6e,0x71,0x8d,0x57,0x8e,0xff,0x3a,0x9a,0xaf,0x29,0x99,0xc1,0x3d,0x44,
+  0xa5,0x04,0xe4,0x03,0x04,0xc4,0xd0,0xf0,0x1e,0xa0,0x40,0x7a,0x60,0x22,0xe0,0x13,
+  0x31,0x44,0x62,0x06,0x6c,0x41,0xa7,0xd4,0x7d,0xbe,0xfa,0x5a,0x8e,0xff,0xd2,0xbe,
+  0x9f,0x97,0x34,0xfc,0xf1,0x3b,0x76,0x1f,0xce,0xb3,0x3b,0xd3,0xaa,0xce,0x86,0xd6,
+  0xfb,0x66,0x07,0x37,0x58,0x3f,0xce,0xae,0x59,0xef,0x5b,0x80,0xfb,0xe0,0xce,0x9c,
+  0xfe,0x21,0x19,0xa3,0x79,0xfc,0xf5,0xa4,0x3c,0x59,0x3a,0x89,0x7f,0x62,0x8e,0xa5,
+  0x3e,0xcc,0xfe,0x9d,0xee,0xb9,0xa0,0x7e,0x93,0xfd,0x3b,0x3f,0xe8,0xa9,0xfe,0xa3,
+  0xfa,0x5d,0x8a,0x87,0x8c,0xe3,0x30,0x3d,0x84,0x5f,0x2c,0xd9,0x6c,0xbc,0xe6,0x3e,
+  0x37,0x76,0xe1,0xaf,0x37,0x73,0x94,0x56,0xb6,0x2e,0x53,0xb2,0x53,0xf9,0xe0,0x57,
+  0x87,0xf5,0x86,0x84,0x7f,0x1f,0xfb,0x80,0xe3,0xb4,0xe2,0xfe,0x7d,0xca,0x6d,0xb0,
+  0xc9,0xaa,0x4b,0x63,0xff,0x20,0x46,0xcb,0x2e,0xb0,0xa5,0xe9,0xe5,0xa7,0x72,0xf8,
+  0xeb,0x9c,0x8c,0x82,0x23,0xe7,0x6d,0xd2,0xb8,0x8b,0xad,0xea,0x55,0x06,0x3d,0x93,
+  0x33,0x9a,0x20,0x20,0xc2,0x00,0x54,0x99,0xd9,0x6a,0x9c,0x85,0xbb,0x8a,0xa8,0x40,
+  0x30,0x8c,0xdd,0xd7,0xf0,0x9f,0xf0,0x5f,0xa6,0xed,0x4c,0x56,0xe5,0x34,0x04,0x8a,
+  0xde,0x98,0x8e,0x5e,0x4a,0x5e,0x7f,0xbe,0xdc,0x65,0xe4,0xf1,0x57,0x21,0xff,0x05,
+  0x5f,0xe3,0x92,0x89,0x58,0xea,0x12,0x42,0x3c,0xe6,0x66,0x34,0xfe,0x9b,0x43,0x8d,
+  0xad,0xa0,0xd0,0xb2,0x5f,0x41,0xb0,0x80,0xec,0xc8,0xf3,0x5f,0x8e,0xc8,0x3c,0xe2,
+  0x2f,0xe5,0x1f,0x4c,0x6d,0xb0,0xec,0x92,0xfe,0x38,0x88,0xb2,0xcb,0x97,0xbc,0x3f,
+  0xf7,0xd4,0x9a,0x2b,0x84,0xc1,0xc4,0xa5,0x21,0xfd,0x29,0x2a,0xa4,0x72,0x43,0xfe,
+  0xcb,0x63,0xf3,0x5f,0xcb,0xcc,0xe7,0x2b,0xbe,0xd1,0xa2,0xdd,0xcd,0x5e,0xe7,0x8f,
+  0x1a,0xd5,0x2b,0xb5,0xbb,0xa3,0xaf,0xf3,0xe7,0x8d,0x6a,0xd9,0xf2,0xbc,0x21,0x2e,
+  0x0d,0xc1,0x53,0x86,0xb1,0xfc,0x86,0xfc,0x97,0xad,0x3f,0xdf,0xae,0x54,0xb8,0xb4,
+  0x11,0xec,0xca,0x6b,0xf9,0xd4,0x1e,0x71,0x89,0xfa,0xf9,0x4d,0x68,0x50,0xff,0xc5,
+  0xd5,0xcf,0x79,0xfe,0x2b,0xed,0xb0,0x27,0x7c,0x62,0x46,0x6c,0x19,0xc9,0x7c,0x99,
+  0xe3,0x7a,0x6c,0xe5,0xaa,0xad,0xca,0xd0,0xb2,0x71,0xbd,0x66,0x99,0x34,0xca,0xd0,
+  0x63,0xdc,0xaa,0xbc,0x0e,0x57,0xea,0x9b,0x6e,0xc4,0x7f,0x51,0xfd,0xaf,0x5c,0xb5,
+  0x2f,0xbb,0x64,0x95,0x1d,0x74,0x2d,0x0c,0x4f,0xcc,0x64,0x92,0xff,0x0a,0x92,0xf4,
+  0x7a,0x15,0xfc,0x42,0x96,0x71,0xb9,0x21,0xff,0xc5,0x6c,0x48,0xd5,0xe1,0x94,0x5d,
+  0xde,0x2b,0xf1,0x97,0xa1,0x3b,0x89,0x60,0x9f,0xe9,0x71,0x0a,0x31,0x3b,0xfa,0x87,
+  0xff,0x09,0xff,0xa5,0x48,0x6d,0xc3,0xb4,0x0c,0x32,0x24,0x43,0xd5,0x7d,0xed,0xac,
+  0xcd,0x1b,0x96,0xf2,0x26,0x3b,0x3d,0x94,0x8b,0xe7,0xab,0x72,0xca,0x7e,0xb9,0xfa,
+  0xd9,0xc1,0x5f,0xce,0xb8,0xf7,0xc3,0x46,0x3d,0xd8,0x4a,0x65,0x97,0x3d,0x1b,0xcd,
+  0xe0,0x3d,0xea,0xf7,0x28,0x5a,0x95,0xf8,0xaf,0x6d,0x89,0x77,0x5b,0x0e,0x79,0x83,
+  0x22,0xa2,0xb5,0xa2,0xb3,0xf0,0xfd,0x09,0xba,0xf3,0xbf,0xf0,0x35,0x5e,0x81,0xd0,
+  0x8c,0x82,0xe4,0x11,0xa4,0x2b,0x9f,0x87,0x63,0xfd,0xc1,0xf8,0xac,0xed,0xca,0x4f,
+  0xe0,0x58,0x5b,0x4d,0xdc,0xbf,0x9d,0xfa,0xe7,0x0b,0xc1,0xd6,0xc0,0x8e,0xf2,0x2a,
+  0x76,0x2c,0x81,0x6e,0x98,0xab,0x7f,0x6e,0xa8,0x7f,0xd8,0x1e,0x6b,0x09,0x6c,0x27,
+  0xfa,0xcc,0x6c,0x34,0x6b,0x77,0x48,0xfd,0x8d,0xd5,0x25,0xa9,0x4a,0x84,0x5d,0xd6,
+  0x8b,0xab,0x03,0xf4,0x40,0x34,0x0a,0x88,0xcb,0xe3,0x53,0xf9,0x2f,0xc4,0x5f,0x83,
+  0xa6,0xd0,0x96,0x07,0x51,0x7f,0xd9,0xef,0x2d,0x07,0x9d,0xb2,0xbd,0xfc,0xed,0x95,
+  0x06,0x58,0xcb,0xea,0x28,0x46,0xb1,0xc2,0x2e,0xcf,0x77,0x3d,0xff,0x35,0xad,0x1e,
+  0x0e,0x2b,0xb6,0xda,0xe1,0x26,0x29,0xbb,0x11,0xca,0x6f,0x64,0x76,0x46,0x98,0x43,
+  0x84,0x31,0x55,0x7f,0xb1,0x23,0xf8,0xbf,0xe2,0xbf,0x7c,0xb2,0xc8,0x57,0xd8,0xa2,
+  0xbc,0x12,0x3a,0x57,0x47,0xa3,0x54,0x24,0x98,0x58,0xf3,0x65,0xa6,0xc9,0x5e,0xfb,
+  0x92,0x3f,0xd4,0xdb,0x79,0x3d,0xff,0x85,0xf8,0xcb,0x10,0x2b,0xed,0x43,0x6c,0x16,
+  0xdf,0x40,0xb2,0x1b,0x24,0x7b,0xd8,0x4d,0x85,0x42,0x22,0x45,0xb3,0x70,0x15,0x35,
+  0x2c,0x1f,0x85,0x1c,0x24,0xe1,0xef,0xe5,0xa5,0xc5,0x05,0x1a,0x89,0xae,0xfc,0xaf,
+  0xcf,0x4a,0xb5,0xc3,0xcb,0x4b,0x9b,0xac,0xdf,0x0a,0xd9,0x8d,0x72,0x81,0xc8,0xb2,
+  0x02,0x91,0xbd,0x4c,0xfa,0xf3,0xf5,0x68,0xfc,0x92,0xcf,0xa4,0x16,0x92,0xe6,0xb8,
+  0xf3,0xc6,0xfc,0x97,0x8c,0x24,0xdc,0xb2,0x5f,0x44,0xaf,0xd5,0xb8,0xb9,0x12,0x96,
+  0x8f,0x9c,0x51,0x73,0x02,0xe9,0xe3,0x90,0xd3,0x76,0xbe,0x4e,0x7f,0x83,0x7f,0x77,
+  0x88,0xea,0x7f,0xe9,0xa7,0x9d,0xd8,0x27,0xf4,0xfd,0xde,0x09,0x48,0x90,0x25,0xe2,
+  0x0f,0xaf,0x7a,0x26,0x52,0xb1,0x73,0x76,0xd9,0xaf,0xe8,0x7f,0xc6,0x7f,0x1d,0xcc,
+  0x7c,0xc3,0xd2,0xbe,0xcd,0xae,0xd2,0x46,0x96,0x95,0x65,0x53,0xa0,0xba,0x4f,0xa3,
+  0xfa,0x5f,0x0b,0x8c,0x0a,0x12,0xc7,0x38,0x6b,0xfe,0x7e,0xeb,0xe2,0x6c,0x31,0x5d,
+  0x7a,0x4e,0xdf,0x39,0xec,0xee,0x1f,0x9b,0xff,0x9a,0x69,0xe7,0x7f,0x91,0xc8,0x3c,
+  0xdf,0x20,0x0c,0x49,0x38,0xf6,0xd3,0xcd,0xed,0x4f,0x7a,0x76,0x5a,0x4b,0x6d,0xd9,
+  0x0d,0xba,0x34,0x89,0x7f,0xab,0x62,0xc0,0xfd,0x9c,0x1c,0xff,0x35,0x90,0xf3,0x33,
+  0xf5,0x64,0x2a,0x3c,0xd2,0x79,0x67,0xd9,0x29,0xb3,0x3b,0x15,0x1e,0x5c,0x71,0x27,
+  0x43,0xc3,0x32,0x86,0xb4,0xc5,0xec,0xb4,0xb9,0x9b,0x87,0x46,0x8b,0xef,0xa4,0xd0,
+  0x7a,0xd5,0xd1,0xdc,0x93,0x9f,0x72,0xf4,0x37,0x72,0xfa,0x87,0xe8,0xaa,0x9d,0x00,
+  0x11,0xc6,0x46,0x7d,0xd8,0x94,0x5d,0x41,0xea,0x67,0x6f,0x0d,0x60,0xf7,0x1e,0x60,
+  0x1f,0xc1,0x91,0x81,0x9a,0x0b,0x81,0x4c,0x70,0x04,0x7a,0x21,0x58,0xd0,0xcf,0x1f,
+  0x5f,0x97,0xff,0x25,0xf0,0x97,0x45,0xe5,0x69,0x8c,0x09,0x4a,0x04,0x13,0x86,0x51,
+  0xd7,0x47,0x25,0xab,0xf8,0x87,0x46,0x6c,0xa0,0x84,0x2a,0xd7,0x4c,0x25,0xcb,0x72,
+  0xfa,0x87,0x97,0xf2,0xb5,0xbd,0x7e,0x0b,0xb7,0x5b,0xfe,0x75,0xca,0x2c,0xf8,0x25,
+  0x25,0x0d,0xad,0x5b,0x4a,0x46,0xae,0x45,0x18,0x42,0xb3,0xa8,0x20,0xce,0x2a,0xa7,
+  0x7f,0x18,0xcf,0xd7,0x56,0x76,0xe7,0x6d,0xb9,0x8d,0x32,0x32,0xe6,0x53,0x8b,0x1f,
+  0x36,0x5a,0x4e,0x25,0x65,0xaf,0x14,0xb2,0x73,0xf4,0x37,0x9c,0x64,0x31,0xec,0xba,
+  0x1f,0xde,0xf0,0x39,0xc5,0x84,0xb6,0x72,0x97,0x3a,0xda,0x83,0x05,0x64,0x99,0x4b,
+  0xff,0x30,0x39,0x57,0xe6,0x7f,0xe1,0x24,0x4a,0x9f,0x94,0xd3,0xd3,0x4c,0x8b,0x59,
+  0x19,0xa4,0x24,0xaf,0x79,0x11,0xdf,0x66,0x96,0xf4,0x1b,0xc7,0x20,0x52,0x8a,0xcf,
+  0xd1,0xf7,0x0e,0xb8,0xc7,0x2b,0xaf,0x7f,0xc8,0x4e,0x84,0x28,0xaa,0x33,0x49,0xd5,
+  0xd0,0x84,0x36,0x78,0x18,0x4e,0x98,0xd1,0x41,0x69,0x40,0x17,0xa1,0xda,0x7d,0x9e,
+  0xb7,0xa0,0x6b,0x30,0x9c,0x29,0x0f,0xb3,0x63,0x9e,0xe8,0x89,0x82,0x7e,0x76,0xf0,
+  0xd7,0x18,0x91,0x26,0x96,0x5d,0xed,0xab,0xe9,0xa4,0x93,0xff,0x75,0xfc,0xcf,0xa5,
+  0xe0,0x3f,0x05,0x10,0x26,0x89,0x70,0xac,0x7d,0x53,0xd4,0x62,0xbb,0x62,0x14,0xc6,
+  0xb3,0x4d,0xa9,0xff,0x55,0x62,0xeb,0x6f,0x64,0x03,0x24,0xa9,0x71,0x9a,0x37,0x59,
+  0x7e,0x4b,0xd9,0x86,0x8b,0xde,0x02,0xf8,0x22,0xd1,0xca,0xd7,0xda,0x44,0xfe,0xf2,
+  0x42,0xdc,0x6a,0x17,0x11,0xff,0x95,0xa5,0xf3,0x43,0x97,0xfe,0xbc,0x95,0xd3,0xdf,
+  0x68,0x26,0x7f,0x1e,0x8d,0xf4,0x9f,0xa1,0x3f,0xcf,0x6b,0xfb,0x7d,0x9c,0xcd,0x57,
+  0x0f,0xf1,0x60,0x5a,0xed,0x99,0x4e,0xf7,0xcc,0x8d,0x97,0xa6,0x98,0x17,0x12,0x50,
+  0x47,0xb0,0xeb,0x1d,0xdc,0x2f,0x0c,0x08,0x21,0xfe,0x2a,0xca,0xf1,0x5f,0x76,0x8f,
+  0x59,0x1e,0x51,0x46,0x0a,0xf0,0x01,0x49,0xb9,0x42,0x3e,0x46,0xd4,0x58,0x4e,0x46,
+  0xcf,0x94,0xda,0xd7,0x32,0xd4,0x6d,0x80,0x9c,0x52,0x4a,0x16,0x7b,0xc7,0x13,0x9f,
+  0x82,0xbf,0x3e,0x80,0xc3,0xbc,0xd4,0x5a,0xb1,0x97,0x3d,0x1b,0xc1,0x37,0xa1,0xd7,
+  0xb7,0x97,0xd5,0xd0,0xc1,0x66,0xbb,0x8d,0xbb,0x4b,0xef,0xf3,0xed,0x28,0x43,0x10,
+  0xa6,0xce,0xa5,0x4c,0xc0,0x61,0x38,0xc4,0x0d,0xa1,0x3f,0x2f,0xf7,0x41,0xf3,0x33,
+  0x42,0x24,0x81,0x06,0xe5,0x43,0x98,0x48,0xcf,0xb6,0x02,0x2f,0xb2,0x67,0x85,0x47,
+  0x5d,0xba,0x4f,0xa3,0x25,0x2e,0x1a,0x09,0xdb,0x0b,0x5a,0x26,0xd0,0xa1,0xcc,0xe5,
+  0x03,0x26,0x95,0x48,0x50,0xce,0xc1,0x78,0x7a,0x17,0x9f,0xaa,0x3f,0xdf,0x54,0xe0,
+  0xa2,0xdf,0x23,0x8d,0x34,0xf6,0xe1,0xb8,0xf7,0xe7,0x82,0x11,0xd3,0xaf,0xc1,0x22,
+  0x5e,0x64,0x29,0xaf,0x1b,0x93,0xd2,0x9f,0x1f,0x86,0x3f,0xc8,0x7c,0xbd,0xb1,0x1c,
+  0xff,0xe5,0xc9,0xd5,0xff,0x12,0xb5,0x7a,0x77,0x57,0xbe,0x8f,0x0b,0x6c,0xe3,0xc9,
+  0xc0,0x41,0x6d,0x2e,0xf4,0xb5,0x45,0x5b,0x4b,0x6d,0xfe,0x4b,0xc7,0x99,0x1b,0x42,
+  0xc4,0x41,0xeb,0xea,0x9f,0xbf,0x8b,0x3d,0xd4,0xf0,0x7a,0xa1,0xfe,0xbc,0x53,0xff,
+  0x2b,0xde,0xd9,0x5a,0x63,0x95,0xee,0x41,0x1f,0xe5,0x08,0xfc,0x43,0x16,0x97,0x8b,
+  0x90,0x5d,0x31,0x4d,0x3c,0x87,0xb2,0xe1,0xd8,0x6d,0x89,0x4d,0x0e,0xff,0x85,0xd0,
+  0xec,0x75,0x5f,0x0e,0x7f,0x0d,0xe7,0xe3,0x37,0xfa,0x20,0x45,0x46,0x47,0x51,0xbf,
+  0xde,0xed,0x0d,0x8f,0x6a,0x1d,0x02,0x0e,0xa4,0xcd,0x5c,0xfd,0x14,0xed,0x79,0xd1,
+  0x22,0x78,0x7c,0x72,0x4e,0x42,0x34,0x5e,0xa3,0xd2,0xcf,0x4c,0xe7,0xf0,0x57,0xd1,
+  0x6f,0x60,0x3b,0x17,0x6a,0x87,0xbf,0x11,0x65,0x97,0x7d,0x2d,0xcd,0x0d,0x9e,0x47,
+  0xd3,0x46,0xdc,0xf7,0x10,0xa1,0x80,0xf6,0xea,0x61,0xed,0x9e,0x60,0x99,0xb9,0x61,
+  0xb4,0x42,0xea,0xf2,0x6d,0xe1,0x15,0x06,0x6e,0x6d,0x67,0xbc,0xba,0x83,0xbf,0xba,
+  0x33,0x02,0x7f,0xf5,0xe2,0xf7,0x69,0xcc,0x06,0x40,0xe9,0x87,0x6f,0x65,0xc2,0x59,
+  0xed,0xb3,0x0a,0x98,0x7d,0xe9,0x48,0x2b,0xee,0x5f,0x24,0x7b,0x38,0x6b,0x0d,0xf6,
+  0x21,0x78,0x7b,0xf7,0x53,0xd9,0x65,0x76,0x9a,0x1f,0xe3,0xf5,0x29,0xa1,0x3f,0xaf,
+  0x3b,0xf8,0xcb,0xd6,0x4b,0xa1,0x30,0x36,0xec,0xe7,0x5e,0xfc,0xaa,0xd7,0x3c,0x4d,
+  0x7d,0xe4,0x55,0xea,0x93,0x7a,0x93,0x39,0x6d,0x54,0x39,0x4a,0x01,0x84,0xcb,0x48,
+  0x91,0x9e,0x64,0xe7,0xc5,0xe0,0x2e,0xa3,0xe4,0xbe,0x55,0x88,0xbf,0xbc,0x36,0xfe,
+  0x72,0xad,0x90,0x62,0xcd,0xa4,0x12,0x1b,0x13,0x4a,0xec,0xcd,0x6f,0x70,0x59,0x76,
+  0x99,0xe7,0xc3,0x3f,0xd2,0x4a,0x50,0x27,0x45,0xc4,0x12,0x2a,0x76,0x70,0x82,0x53,
+  0x68,0xab,0xd2,0x97,0xe7,0xbf,0x72,0x6a,0x87,0x07,0x40,0x08,0x21,0xce,0xf0,0x92,
+  0x36,0xaf,0x4a,0x8a,0x88,0xcf,0x43,0x35,0x17,0xc7,0x7d,0xbf,0xa7,0x4b,0x96,0x4f,
+  0xa7,0x8c,0x30,0x4b,0x14,0xb2,0xdc,0x00,0xb7,0x43,0x09,0xe2,0xaf,0x22,0x7b,0x9d,
+  0xcf,0xc5,0x1f,0xbe,0x06,0x07,0x48,0x7f,0x7e,0x66,0x90,0x6a,0x7b,0x55,0xbf,0xaf,
+  0xaa,0x08,0x78,0x5f,0xe8,0x5b,0x9b,0xf5,0xd9,0x68,0x2b,0x8e,0xf7,0xfc,0x19,0x7a,
+  0x0e,0xf3,0xe8,0xe6,0x57,0x20,0xc9,0xbf,0x9a,0x56,0xd7,0x37,0x0f,0x5c,0xa7,0x3f,
+  0x9f,0x35,0x7b,0xd0,0xe8,0xdc,0x58,0x14,0x34,0x85,0x6e,0x98,0xbf,0xcf,0x63,0x64,
+  0xe2,0xe1,0xb3,0x4e,0x46,0x58,0x7c,0xc5,0xf6,0x32,0x93,0x39,0x75,0x4b,0x8d,0xa4,
+  0x2e,0x8a,0x27,0xbe,0x09,0x53,0xe3,0x0f,0x27,0xe0,0x6a,0x0a,0x8d,0x21,0xe5,0x4e,
+  0xd1,0xe2,0xff,0x58,0xfb,0x1c,0xa5,0x09,0x67,0x4a,0x25,0xda,0xa2,0x93,0x8a,0xe9,
+  0xeb,0xe1,0x14,0xce,0x66,0x29,0x8d,0xc8,0x3f,0x9f,0xf2,0x1b,0x88,0xbf,0x24,0x3e,
+  0xbd,0x4e,0x7f,0xbe,0x9d,0x88,0x30,0x34,0x9e,0x68,0x5f,0x9a,0x9d,0x36,0x66,0x52,
+  0x5e,0x7f,0x65,0x96,0x30,0xda,0xb4,0x40,0x7b,0x72,0x37,0x8c,0x71,0x79,0xb3,0x39,
+  0x06,0x2f,0x4a,0xfc,0x15,0xb7,0xf1,0x57,0xce,0x33,0x4f,0x93,0xbf,0xfa,0xc5,0xd4,
+  0x06,0x52,0x9b,0x6f,0x5c,0x56,0xb2,0x43,0x11,0x0c,0x82,0x93,0x11,0x56,0xb3,0x24,
+  0xb0,0x43,0x59,0x6d,0x9e,0x17,0x15,0x7e,0x45,0x4b,0x98,0xa4,0x11,0x99,0x9c,0x5f,
+  0xae,0xfa,0x5f,0xbf,0x67,0x1b,0x07,0x77,0x99,0xda,0xd3,0x42,0x25,0xbe,0x26,0xae,
+  0x6e,0x23,0xe3,0x17,0x0d,0xae,0xf8,0xc3,0x1f,0xb0,0xcf,0x1b,0x87,0x5c,0xfe,0x73,
+  0x73,0x68,0x07,0x4b,0x5f,0x17,0x7f,0xf8,0x2e,0xd5,0xc1,0x34,0xb5,0x6d,0x89,0x2a,
+  0x83,0x72,0x7c,0x3e,0x77,0x13,0xa5,0x8f,0xc5,0xa5,0xec,0xa1,0x47,0xf0,0x5f,0x5b,
+  0x99,0x4b,0xac,0xc3,0x0e,0x7a,0x2c,0x9d,0x12,0x7f,0xa8,0x4b,0xfd,0x43,0x04,0x62,
+  0x3e,0x6f,0x73,0x1b,0x84,0x97,0xa9,0x37,0xb1,0x2a,0x66,0x17,0x9f,0x72,0x50,0x40,
+  0x91,0x37,0xdd,0x6d,0xa4,0x45,0xa5,0x2a,0xbe,0x3f,0x14,0x5e,0xae,0xea,0x6c,0xd3,
+  0xb4,0x02,0xfc,0x45,0xd2,0x91,0xe9,0x81,0x35,0x51,0x28,0x7d,0x2c,0x51,0x91,0x46,
+  0xfc,0xf5,0x83,0x92,0xc7,0x3a,0x0d,0x18,0x08,0x35,0xe4,0x64,0x0f,0x7d,0x81,0x44,
+  0x32,0xce,0xc7,0x5a,0x1d,0x8d,0x71,0xa3,0x51,0x5d,0xc9,0xdd,0xfa,0x87,0x39,0xb5,
+  0xc3,0x2b,0x46,0xcc,0x5c,0x45,0x42,0x88,0xe3,0x0c,0x1d,0x7b,0x34,0xd4,0x2b,0x70,
+  0x97,0x83,0xb6,0x9a,0x4c,0xed,0xb5,0xce,0x4b,0xe9,0x2b,0x32,0x28,0xf4,0x52,0x8b,
+  0x50,0xe4,0xc0,0xd1,0xf1,0xba,0xf4,0x37,0x72,0x6a,0x87,0x51,0xf3,0x56,0xda,0xa4,
+  0xc6,0x1d,0x45,0xc4,0x02,0x45,0xfa,0xd2,0x41,0xe5,0x41,0x8a,0xdf,0x30,0x6d,0xb0,
+  0x26,0xf8,0xaf,0x1b,0xe8,0xcf,0x33,0xc2,0x5f,0xb7,0x72,0xb6,0x57,0x26,0x82,0x91,
+  0x1b,0xdf,0xe3,0xa9,0xcb,0xa3,0xad,0x2d,0x5c,0xcb,0x82,0x9d,0x11,0x36,0x2c,0xc0,
+  0x5a,0x08,0xf1,0x57,0x51,0x9e,0xff,0x22,0x0d,0x7f,0x01,0xb2,0xb0,0x57,0x57,0xd8,
+  0x84,0xe3,0x12,0x9f,0xcc,0x08,0x4b,0x2f,0xa1,0x4b,0x33,0x28,0x22,0xf1,0xe6,0x94,
+  0x6f,0xd9,0x8c,0x36,0xaf,0x2c,0xc1,0xe6,0x48,0x23,0xbe,0x26,0xe7,0x57,0x61,0xfd,
+  0x2f,0xd8,0xb5,0xc4,0xb7,0xbd,0x48,0xb6,0x74,0x44,0x9b,0x09,0x92,0x07,0x5b,0xf3,
+  0x68,0xeb,0x7b,0x37,0xff,0x1e,0x92,0x86,0x28,0xbb,0x3c,0x64,0xe2,0x4b,0x12,0x17,
+  0x75,0x07,0x8c,0x1c,0xfe,0x72,0x70,0xd3,0xfb,0x46,0x17,0x71,0x88,0x73,0x66,0x11,
+  0x22,0x2b,0xdd,0x4e,0x27,0x0c,0xf8,0x46,0x39,0xfd,0x83,0xfb,0xb2,0xf6,0x35,0x76,
+  0xcc,0x14,0x42,0x88,0xbf,0x87,0x63,0x66,0xd7,0xdd,0xfe,0x1c,0xfe,0x5a,0x93,0xc7,
+  0x5f,0xfd,0x22,0xaa,0x93,0x48,0x2e,0x43,0xd6,0x0b,0x58,0x31,0xc4,0xcf,0xa7,0xdc,
+  0x6a,0xf3,0x3b,0x88,0x23,0x83,0xc3,0x05,0x78,0xf9,0xb5,0x1c,0xfe,0xf2,0x38,0xf3,
+  0x94,0x8f,0xb5,0xd0,0xbb,0x51,0x79,0x8e,0x91,0xec,0x86,0xbf,0x9d,0xf4,0x5b,0x8c,
+  0xc2,0x53,0x11,0x83,0x0d,0xc4,0x85,0xd8,0x4b,0x2f,0x89,0x17,0xdd,0x84,0xaf,0x56,
+  0x9f,0x4b,0x7f,0xc3,0x33,0x97,0x90,0xd4,0xb8,0xf7,0x45,0x04,0x59,0xa5,0x43,0x6c,
+  0x0c,0x07,0xa5,0x96,0xfb,0xb2,0xcd,0xc3,0xf0,0xa2,0x64,0xbb,0xd6,0xc0,0x0f,0x3c,
+  0x61,0x5e,0x1a,0x67,0x0d,0xfc,0x09,0xcb,0xc6,0x5f,0x4f,0x40,0xed,0x5e,0xf5,0x46,
+  0xf1,0x87,0x16,0x44,0x5a,0x71,0x8d,0x62,0xac,0x97,0x80,0x18,0x11,0xfa,0xfd,0x90,
+  0xe1,0x2e,0x45,0x7a,0xad,0x1e,0x67,0x53,0x92,0xdb,0x71,0x68,0xe4,0x55,0xae,0xd1,
+  0xa7,0xea,0x6f,0x08,0x49,0x8d,0xe7,0x65,0xc9,0xe0,0x3e,0x92,0x83,0x00,0x9f,0x50,
+  0x81,0x20,0xc9,0xbe,0x75,0x45,0x5f,0xa6,0xfa,0x8c,0x96,0xef,0x41,0xa6,0x42,0x52,
+  0xb5,0xf1,0xd7,0x06,0x1d,0x97,0xee,0x56,0x96,0xf5,0xda,0xf8,0x2b,0xa7,0xbf,0xf1,
+  0x1a,0x4c,0x0a,0x6d,0x8d,0xf2,0xd7,0xe0,0xb7,0x54,0x7d,0x75,0x7d,0x39,0x15,0xc4,
+  0xdc,0x2f,0xd1,0xd6,0xff,0xfb,0x28,0xde,0x73,0x46,0xfb,0x2c,0x02,0x31,0x81,0xbf,
+  0x4e,0xc1,0x2f,0xd3,0x8d,0x69,0xff,0x3d,0xca,0x3b,0xee,0xf8,0x43,0x11,0x64,0x38,
+  0xe4,0xa5,0x7d,0x47,0xb0,0xd2,0x1f,0xca,0x5e,0x25,0x82,0xa6,0xce,0x3a,0x4d,0xf1,
+  0x6c,0x14,0xb7,0xb3,0x25,0x4d,0x65,0x97,0xc5,0x71,0xb1,0x62,0x17,0x96,0xa2,0x73,
+  0x24,0x31,0x5e,0x2e,0xfd,0x8d,0x0b,0xf8,0x7d,0x9a,0x86,0x02,0x03,0xca,0x1f,0xc9,
+  0x3f,0xa4,0x6a,0xb0,0x2f,0xc0,0x23,0x88,0xbf,0xfc,0xe3,0x92,0xff,0xca,0xae,0x38,
+  0x53,0x1e,0x03,0x51,0x23,0x8c,0xc4,0x3a,0x7e,0xc7,0x17,0xc5,0xfd,0x67,0x10,0x7f,
+  0x19,0x36,0xfe,0x9a,0xd9,0xad,0x23,0x4a,0x5a,0xdf,0xfc,0x2b,0x38,0x60,0x84,0x87,
+  0x71,0xff,0xba,0x14,0xc7,0xdd,0x01,0x4a,0xff,0x92,0xcd,0x4e,0xff,0x9e,0x84,0xa4,
+  0x44,0xfd,0xaf,0x4c,0x78,0x64,0xc5,0xdd,0x6c,0x26,0x6c,0xd1,0x6f,0xcf,0x6a,0xeb,
+  0xf0,0x97,0x26,0x37,0xdf,0x9e,0xfa,0x8b,0xbf,0x64,0x1f,0x14,0x89,0xe7,0xb8,0xf4,
+  0x37,0x5e,0x37,0x0e,0xa8,0xf8,0x40,0x3a,0x87,0x44,0x20,0x66,0xaa,0x0f,0xb2,0xa7,
+  0xf9,0x7e,0x9d,0x04,0xa9,0x8a,0xa4,0xec,0xe1,0x0f,0x89,0x6b,0x7b,0x54,0xe0,0xaf,
+  0xb2,0x93,0x1d,0xdf,0x37,0x2a,0x00,0xfb,0xb9,0x6f,0xaa,0xfe,0x06,0xae,0xab,0x19,
+  0x8e,0xfb,0x97,0x56,0x46,0xf9,0x44,0x61,0x72,0x37,0x4b,0x60,0xb7,0x69,0xb8,0x4e,
+  0x89,0xc1,0x57,0x6c,0x24,0xb2,0x69,0xba,0xf9,0x09,0xf3,0xc9,0xac,0x91,0x99,0xa7,
+  0xe3,0xc6,0x2a,0x7f,0x57,0x5e,0x7f,0xe3,0x03,0xb8,0x3c,0x88,0x9d,0xb9,0x07,0x0d,
+  0x91,0xbb,0x9d,0x86,0xcd,0x30,0x96,0x8a,0x0e,0x87,0x65,0xaf,0x96,0xd2,0xb1,0xcf,
+  0x3c,0x11,0x8f,0x24,0xfc,0xa8,0xdf,0x59,0x75,0x67,0x70,0x7e,0x5d,0x8f,0xbf,0xde,
+  0xe7,0x0d,0x34,0x28,0x07,0x94,0x8f,0x0c,0x59,0x2c,0x0c,0x61,0xd7,0x98,0xd5,0xe8,
+  0x42,0xd0,0x3b,0xc8,0x97,0x30,0x1b,0x9c,0x14,0x86,0xc6,0x1d,0xb5,0xa9,0xeb,0xf5,
+  0x37,0x70,0x8b,0xfc,0x9d,0x14,0xe2,0x18,0xa3,0x28,0x38,0x1e,0x38,0xa6,0xc4,0xa0,
+  0x9f,0x47,0x2d,0x6f,0x4e,0x91,0x5e,0x57,0xe6,0x52,0x05,0x01,0x0a,0x44,0x3c,0x2b,
+  0x50,0x1b,0x1a,0xc3,0x4e,0xfc,0xc6,0x5a,0xa7,0x48,0xee,0x7f,0x40,0x67,0x87,0x08,
+  0x5a,0xfb,0x90,0xb8,0x89,0xc8,0x8a,0xf6,0x9b,0x6b,0xa0,0xe3,0x0c,0xf9,0x87,0xd3,
+  0xa5,0x8f,0xed,0xa3,0x0c,0xa3,0x0e,0xab,0xc1,0x01,0x6b,0xe2,0xc4,0x7e,0x38,0xa7,
+  0x7f,0x98,0xf7,0xc3,0x7f,0x40,0xc1,0x6f,0xfb,0x8a,0x3e,0x30,0x10,0xa3,0x8d,0xe2,
+  0x64,0x0c,0x53,0xa5,0xaa,0x5c,0xd9,0x2f,0x6b,0xe6,0x0e,0xa6,0xa6,0x3b,0xf2,0xa0,
+  0xaf,0xc6,0xf4,0x6d,0x2b,0xd0,0x9f,0x97,0x22,0xf3,0x03,0x42,0x05,0x5d,0x33,0xe4,
+  0xe8,0xa4,0xa8,0x2e,0x30,0xe7,0x54,0xa7,0xef,0x76,0xe2,0x2b,0x0d,0x44,0x0a,0x3a,
+  0x03,0xc6,0x6f,0x0a,0x0b,0x71,0xb0,0x44,0xd2,0x58,0xcb,0x71,0x5d,0xed,0x93,0xfb,
+  0x97,0xd0,0xdf,0x68,0xb5,0xd5,0xa7,0xcf,0x40,0xec,0xe4,0xaa,0x74,0x79,0x56,0x9f,
+  0xb8,0xbb,0x66,0x30,0x00,0xd3,0xc3,0xbb,0x06,0x5a,0xa3,0x56,0x8d,0xed,0xcf,0x9f,
+  0xdd,0x4c,0x02,0x08,0x03,0x66,0x43,0x1f,0xf5,0xb3,0x75,0xa2,0xbe,0xd1,0x2c,0xcd,
+  0x94,0xbb,0xf5,0xe7,0xb1,0xc7,0x4a,0xf6,0x0b,0xdc,0x44,0x41,0x50,0x1e,0x51,0x64,
+  0x99,0x4e,0x1d,0x47,0x60,0x92,0xe1,0xa5,0x0b,0xe8,0x1f,0x4e,0x98,0xb1,0x93,0x01,
+  0xab,0x9c,0xee,0x69,0x10,0xfe,0xa1,0x75,0xb1,0x4a,0x88,0x3f,0x0c,0x43,0x1e,0x7f,
+  0x25,0x24,0x93,0xd5,0x3e,0x69,0x34,0xa9,0xab,0xfa,0xfe,0x6a,0x94,0x3f,0x0c,0x4d,
+  0x82,0x08,0x6b,0x3f,0x5b,0xd5,0xa4,0xca,0x03,0x64,0xa3,0xc9,0x44,0x8c,0xb6,0x10,
+  0x5e,0x7d,0x6c,0x11,0x38,0xfc,0x57,0xdc,0xbf,0xbe,0x00,0x7f,0x51,0xfd,0xe5,0x1e,
+  0xe5,0xe3,0x56,0x62,0xbb,0x4a,0x0f,0xb1,0x8f,0xcd,0x23,0x56,0xcd,0xbb,0x9a,0x30,
+  0x52,0x35,0xbf,0xd0,0x5e,0x50,0x6a,0xbd,0x68,0xec,0x11,0xc4,0x4a,0x1b,0x1d,0x2d,
+  0xba,0x0a,0x31,0xbb,0xe2,0x0f,0x73,0xeb,0x61,0x4e,0xff,0x30,0xa3,0x87,0x3d,0xd2,
+  0xa0,0x16,0xef,0x36,0xde,0x2a,0x8c,0x08,0xae,0x35,0x9d,0x8e,0xb0,0x39,0x1d,0x5e,
+  0x61,0x3f,0x77,0x5d,0xc7,0x7f,0x89,0x4d,0x53,0xdd,0xd4,0xde,0x9c,0xed,0xe8,0xb9,
+  0x89,0x76,0xd8,0xe6,0x2c,0xef,0xf1,0xd4,0x78,0x35,0x48,0x18,0xd0,0x13,0x16,0xd4,
+  0x33,0xdc,0xd7,0xa9,0xe3,0x3b,0x94,0xab,0x4d,0x90,0xca,0xc5,0x1f,0xce,0xd8,0xe7,
+  0x84,0xda,0x7e,0x20,0x6a,0x4f,0x07,0x8e,0x8a,0xd8,0xcb,0xd8,0x57,0xd1,0x78,0x8f,
+  0xbf,0x41,0x75,0x4f,0x9e,0x5a,0xfa,0x93,0xc1,0x71,0x2b,0x46,0xfa,0xa2,0x73,0x58,
+  0xaf,0xa7,0x2e,0x6a,0xcf,0xb8,0xd8,0x3a,0x7f,0x8f,0xa7,0x3f,0x87,0xbf,0x74,0x7b,
+  0x5e,0xfc,0x58,0x9f,0x5c,0xd2,0x64,0x7c,0xb1,0xbf,0xfc,0x82,0x77,0xd2,0xd3,0xd4,
+  0xb6,0xaa,0xbf,0x7c,0xcc,0x7b,0xf5,0x4f,0x9b,0x76,0xad,0xca,0x96,0x0f,0xcf,0xb8,
+  0x4a,0x3d,0x7f,0xbe,0x73,0x94,0x5d,0xe1,0x4d,0x55,0x4e,0x5c,0xee,0x6a,0xa1,0xf0,
+  0xe0,0xe0,0x2f,0x47,0xaa,0x68,0x88,0xe2,0x37,0xf4,0x40,0xfb,0xd2,0x73,0x64,0x6c,
+  0xc5,0x05,0x56,0x26,0xce,0x30,0x4a,0xa5,0xf9,0xc0,0x6c,0x30,0xd1,0x71,0x1d,0x22,
+  0x6a,0xcc,0x44,0x20,0x2f,0x12,0xd3,0x5a,0x6b,0x52,0x49,0xfd,0x3a,0xfc,0x35,0x24,
+  0xe2,0x6d,0xe4,0xc1,0xaf,0xa7,0xa1,0x4d,0xe5,0xe2,0x90,0x30,0x98,0x28,0xb5,0xcf,
+  0x0f,0x4d,0x75,0x4f,0x22,0xfb,0xca,0x1b,0xcc,0x68,0x71,0xf8,0x2f,0xd2,0x07,0xa8,
+  0x2b,0xac,0xbf,0x2c,0x4a,0x00,0xa4,0x61,0xad,0x18,0xaf,0x99,0x69,0x08,0x73,0x1f,
+  0x14,0x0d,0x40,0x97,0x37,0x94,0xf2,0x19,0x8c,0x0e,0x8b,0xd7,0x00,0xce,0x8b,0x01,
+  0x68,0xf3,0x86,0xca,0xec,0x95,0x6d,0x2e,0xf8,0x6e,0x62,0xf5,0xf9,0xf8,0x43,0xbb,
+  0xfe,0xd7,0x9b,0xe8,0xf3,0x57,0xbf,0x8b,0xd8,0xea,0x94,0xb9,0x81,0xf8,0xaf,0xf5,
+  0xcd,0xbf,0x69,0xdd,0xfa,0x68,0xc5,0x57,0xd5,0x7b,0xd8,0x3f,0xe9,0x6d,0x69,0x23,
+  0xeb,0xfb,0x6b,0xf6,0x9a,0xf9,0x3d,0xae,0xee,0x71,0xf8,0xaf,0x75,0x78,0xe9,0xa8,
+  0x5b,0xff,0xb0,0xd1,0x2a,0xad,0x67,0x27,0xac,0xff,0x80,0xc6,0x11,0x11,0x7f,0xb8,
+  0x1b,0x1a,0x5b,0x4a,0x17,0x2a,0xaf,0xa0,0xb7,0xdc,0x60,0xfa,0x52,0x5a,0x3b,0x9c,
+  0xcb,0xd4,0xa7,0x4b,0x6f,0xc2,0x4b,0xbd,0x50,0x1f,0x5e,0x29,0xeb,0x7f,0xc5,0x5a,
+  0x4b,0x75,0xb7,0xfe,0xbc,0xe0,0xbf,0xce,0xd3,0xf2,0xa5,0xcb,0x80,0x6a,0xef,0x35,
+  0x1d,0xdd,0xc2,0xd1,0xf2,0x4b,0x33,0xc6,0x11,0x7f,0x95,0xfe,0xaa,0xfc,0x41,0xf3,
+  0xca,0xb4,0xa6,0xcd,0x25,0xbf,0x2a,0x3f,0x8b,0xc3,0xfd,0x29,0x77,0xea,0xb5,0x2d,
+  0xab,0x1d,0x54,0x5a,0xa7,0xd6,0x5f,0x16,0xfc,0x57,0x5d,0xb6,0xa4,0xa7,0xf2,0x7e,
+  0x76,0x82,0x8b,0x9d,0xf1,0x63,0xf8,0xa1,0x12,0xcb,0x96,0x64,0xca,0xc3,0x34,0xa6,
+  0x3d,0xe1,0xd4,0xf4,0x10,0x1c,0x73,0x72,0xfa,0xb0,0xc5,0xf0,0xa7,0xa6,0x7f,0xc0,
+  0xae,0xc7,0x5f,0x82,0xff,0x02,0x9d,0xe3,0xaa,0x5d,0x01,0xc5,0xb8,0x01,0xa9,0xed,
+  0xb0,0x12,0x54,0x13,0x97,0x86,0x03,0xe4,0x51,0xb7,0x16,0x3d,0xcd,0x1e,0xcd,0x47,
+  0x24,0xd6,0x9a,0xb8,0xef,0x5c,0x00,0x17,0xfe,0x12,0x90,0xea,0x6d,0xcf,0xc1,0x4d,
+  0x5f,0x7d,0x47,0x5b,0xff,0xd8,0x57,0x8c,0x0d,0x89,0xaf,0x52,0xdd,0xae,0x53,0xea,
+  0xf7,0xa5,0xda,0xfc,0x6c,0xca,0xf6,0x7a,0x47,0x1d,0x60,0x77,0xd3,0x58,0xe4,0x78,
+  0x46,0x8a,0x3f,0x4c,0x17,0xe2,0xaf,0x13,0x11,0xf6,0xb6,0xf7,0x60,0x7b,0xc5,0x28,
+  0xac,0x9f,0xfb,0x15,0xd8,0x60,0x55,0x0c,0x16,0x7f,0x93,0x12,0xcf,0xbd,0x73,0xce,
+  0xa9,0x93,0xcd,0xff,0xb7,0x7e,0xb0,0x1f,0x91,0x9d,0xb7,0xf9,0x94,0x99,0x64,0x6b,
+  0x2f,0x74,0x38,0x27,0x27,0xe4,0x67,0x5e,0x97,0xff,0xf5,0x41,0xfc,0xb2,0x59,0xc7,
+  0x03,0x3b,0x95,0x35,0xe6,0x71,0xb5,0xee,0x40,0x60,0x9f,0x32,0xcc,0xdf,0xd4,0x63,
+  0xed,0x25,0x7b,0x95,0x79,0xd6,0x65,0x8e,0x88,0xec,0x5e,0xed,0x6f,0xe0,0x78,0xba,
+  0xa9,0x27,0x6c,0x23,0x32,0x12,0xe2,0xb8,0xbe,0xfe,0x57,0x8e,0xed,0xca,0xd8,0x82,
+  0xae,0xc9,0x51,0xef,0xe4,0x67,0x9b,0x66,0x04,0x7a,0x15,0x34,0xf4,0x26,0xba,0x67,
+  0xa7,0xbb,0xfe,0x57,0x6c,0x06,0x82,0xb5,0x1b,0xd4,0xff,0x02,0x84,0x03,0xcd,0x5b,
+  0x84,0x51,0x1c,0x13,0x85,0x6b,0x0d,0x6c,0x59,0x77,0x6b,0x6a,0x77,0x95,0x3a,0xae,
+  0x22,0x64,0xa0,0x88,0xc4,0x63,0x50,0x5f,0xa0,0xd1,0x91,0xb8,0x41,0xfd,0xaf,0xa7,
+  0x6c,0x43,0x64,0x84,0x05,0x6c,0xda,0xeb,0x5b,0xb3,0x53,0xac,0x4a,0x27,0x1c,0x87,
+  0x5b,0xdb,0xe7,0xd9,0x1b,0x38,0xd1,0x4a,0x6c,0x8f,0xfa,0x3e,0x74,0xc8,0x8d,0x1b,
+  0xe4,0x7f,0xbd,0x44,0xe5,0x21,0x06,0xd9,0xa4,0x63,0x5c,0x82,0x9f,0x2b,0xb5,0x66,
+  0xe7,0x20,0x5b,0x08,0x3f,0x27,0x46,0x0c,0xf1,0x57,0xba,0xcd,0x55,0xd0,0xf9,0x5e,
+  0x6c,0x79,0xec,0x3a,0xfc,0xe5,0xb0,0x5d,0xcd,0x5f,0x12,0x86,0x7a,0x77,0xd1,0xeb,
+  0xfc,0x0e,0x34,0x7c,0x7f,0xc5,0x66,0xf0,0x1f,0x13,0xff,0x95,0x61,0x5e,0xbe,0x15,
+  0xaa,0x5a,0xf2,0x91,0x72,0x29,0x36,0xa5,0xfe,0xb2,0xe8,0xba,0x1e,0xb7,0xe1,0xd0,
+  0x5e,0x33,0x34,0xaf,0x46,0x12,0x16,0xd8,0xcf,0x8f,0x6a,0x15,0xe6,0x40,0x6b,0xe3,
+  0x8c,0x70,0xae,0x9f,0xd3,0xca,0xcf,0x3c,0x53,0xf1,0xd7,0xd0,0xb2,0xcf,0xdd,0x64,
+  0xf3,0x5f,0x13,0x7a,0x6c,0x99,0xb2,0xb5,0x7c,0x68,0xd9,0xf8,0x8c,0xd8,0xb2,0x55,
+  0xdd,0x78,0xe9,0x3b,0x54,0x4d,0xaf,0x55,0x79,0xdd,0xbc,0xc2,0xee,0x5a,0x56,0xea,
+  0x8a,0x24,0x74,0xe1,0xaf,0xf7,0x8b,0x24,0x5e,0x9e,0x81,0xe8,0xf8,0xeb,0xfe,0x1d,
+  0xc9,0xb9,0xc6,0x78,0x47,0xf4,0xef,0xff,0xe2,0x07,0xca,0x5c,0xfe,0x06,0x5f,0x70,
+  0x1f,0xb6,0x7c,0x2d,0x74,0x6c,0x6f,0xf4,0xbe,0x55,0x83,0xca,0x97,0xd8,0xab,0x4e,
+  0x8c,0x22,0x3d,0xa7,0xe4,0x06,0xf8,0xab,0x48,0x48,0xf2,0xea,0x25,0xed,0xac,0x02,
+  0x7a,0xcc,0x20,0xa9,0xf5,0x1a,0x7a,0x87,0x77,0x7e,0x4a,0x6d,0x6f,0x36,0xa0,0x63,
+  0x59,0xd0,0xe1,0xbf,0xd0,0xcd,0x10,0x88,0xcc,0xeb,0xae,0xff,0xd5,0xe2,0xaa,0xff,
+  0xc5,0xb6,0xa2,0xd1,0x23,0xf1,0x97,0x41,0x38,0x77,0x1a,0xdb,0x6a,0x0a,0x90,0xb5,
+  0x4c,0xd2,0x5e,0x33,0x85,0x51,0x98,0x11,0x76,0x7d,0xfe,0xd7,0xbb,0x1d,0x14,0x5b,
+  0x68,0x47,0x1b,0x06,0xff,0x7a,0xf9,0x56,0x01,0xe4,0xe7,0xb7,0xa8,0xa9,0xa0,0x90,
+  0x6d,0x31,0x4f,0xe8,0x2c,0x0c,0x1b,0x13,0xce,0xb8,0x7b,0x6a,0x9a,0xd5,0xad,0x6e,
+  0xfd,0x43,0x99,0x93,0xc5,0x7e,0x0f,0xb8,0x5b,0xad,0x57,0x53,0xca,0xe7,0x61,0xdc,
+  0x8a,0xae,0x2b,0xf9,0xc1,0x5f,0x7d,0x9e,0xbf,0x11,0x8f,0xc6,0xfd,0x4f,0x2b,0x7f,
+  0x67,0x1e,0xc3,0x96,0xc0,0x76,0xe5,0x6b,0x09,0xec,0xc3,0xd6,0xb0,0xfd,0x3e,0x3f,
+  0x58,0x7d,0x23,0xfc,0x25,0x41,0xd6,0xaa,0xed,0xb7,0x7c,0x15,0xc6,0x97,0xbc,0x68,
+  0x7e,0x63,0xc7,0x2d,0x43,0xed,0xe3,0xfa,0x0b,0xf1,0x7f,0xd8,0xae,0xbd,0xc7,0xc6,
+  0xff,0xf4,0xc5,0xd6,0x92,0x54,0xf9,0x10,0xff,0xb6,0x4b,0xa3,0xfe,0xbe,0x1b,0xd6,
+  0xff,0xb2,0x60,0xd8,0x13,0x81,0x22,0x28,0x4f,0xcf,0xc8,0x42,0x3d,0x94,0x82,0xc2,
+  0x61,0xb0,0xa8,0xfe,0xa6,0x2f,0x52,0xa2,0x77,0x16,0x1a,0x28,0x85,0xb3,0x0d,0x06,
+  0x78,0x2c,0xe2,0xbc,0x3f,0x10,0x4e,0x14,0xe8,0x1f,0x8a,0xfa,0xcb,0x45,0x52,0xff,
+  0x90,0x88,0x30,0xcf,0x9b,0x0e,0xff,0x75,0x18,0x2a,0x33,0x25,0x69,0x44,0xd0,0x82,
+  0xff,0xca,0xfa,0xea,0xe1,0x6d,0xb5,0x36,0xed,0x44,0x24,0x92,0x34,0xc7,0x75,0xf8,
+  0x2b,0xb8,0x19,0xb7,0x89,0x21,0x5c,0xd0,0xa2,0x9b,0xfd,0xdd,0x2c,0x84,0x3b,0x5a,
+  0x11,0x85,0x9f,0x85,0x3e,0xed,0xa4,0x38,0xb4,0xdd,0xde,0x35,0xb4,0xc7,0x6d,0x26,
+  0x89,0x86,0xac,0xbd,0x7f,0xd5,0xe8,0xea,0xc2,0x1c,0xfe,0x02,0x57,0x3a,0xd2,0x06,
+  0x2e,0x74,0x14,0x11,0xac,0x81,0x70,0xe3,0x05,0x11,0x66,0xa9,0x0b,0xd0,0xc0,0x96,
+  0xac,0xba,0x1a,0x77,0x3d,0x04,0x62,0x7d,0x4e,0x44,0x22,0x05,0x93,0xbb,0xf4,0x0f,
+  0x89,0xc9,0xd2,0xd6,0x2b,0x4f,0xc0,0x7f,0xb4,0xdf,0x71,0xae,0x74,0xbd,0xf2,0x23,
+  0xfd,0x20,0x82,0xac,0xb7,0xd7,0x57,0xfe,0x48,0xff,0x94,0xdf,0x99,0xee,0x7c,0x28,
+  0xf9,0xc4,0xb4,0xdf,0x27,0xef,0xcc,0x3e,0xf1,0xc1,0xd2,0x1f,0x79,0x49,0x76,0x63,
+  0x96,0x5d,0xff,0x0b,0x31,0x5a,0x8e,0xff,0x9a,0xe5,0x8a,0x93,0x21,0x6d,0xf0,0x52,
+  0xd2,0x7f,0x26,0xd9,0xc3,0x5b,0x72,0x6e,0xfc,0x81,0xdc,0xa9,0xfe,0xd2,0x21,0x57,
+  0x85,0x5f,0x36,0x55,0xff,0x50,0xd4,0xff,0x92,0x2e,0x5f,0xdd,0xd0,0x86,0xb1,0x8a,
+  0xab,0x7c,0x22,0x5d,0x3a,0x82,0xc6,0x23,0xd2,0x09,0xec,0x12,0xa1,0x89,0xb1,0x93,
+  0x25,0x63,0xc9,0x59,0xfc,0x14,0xbf,0xcb,0x08,0xdb,0xfe,0xa1,0x51,0xf2,0x6d,0xb7,
+  0xfe,0xc6,0x45,0x5e,0x4d,0xe7,0xa2,0x9b,0xe1,0xa0,0x6e,0xd8,0xdc,0x96,0x5d,0xff,
+  0xcb,0x3c,0xb8,0xad,0xc4,0xab,0x8e,0xb3,0x59,0x66,0xb7,0x1e,0x7e,0x5f,0x8b,0xb3,
+  0x1d,0xf0,0x18,0x0f,0xe7,0xf6,0xaf,0xcf,0xa1,0x71,0x7d,0xfd,0x65,0xba,0x34,0xa7,
+  0x5f,0xfb,0x26,0x3b,0xbb,0x5d,0xf4,0xfc,0xed,0x14,0x76,0xe8,0x45,0x30,0xfb,0x80,
+  0x0c,0x71,0x3c,0xa9,0xf5,0xa2,0xf1,0x98,0xec,0xde,0xb3,0xd8,0xe1,0xf3,0xe0,0x0b,
+  0xeb,0xca,0xda,0xf3,0xf8,0x6b,0xb7,0xf4,0x5b,0x4e,0x99,0xdd,0x83,0x55,0xa4,0xfa,
+  0x7b,0x8a,0x77,0x93,0xe8,0xfd,0x9d,0xac,0xd4,0xec,0x4e,0x84,0xd3,0x2d,0x77,0x92,
+  0x6c,0x6f,0x0a,0xa1,0x62,0x84,0xb5,0x43,0x22,0x1f,0xb7,0x53,0xb3,0xae,0x25,0xc2,
+  0x76,0xe4,0xe3,0x0f,0x65,0xea,0x93,0x08,0x29,0xac,0x7b,0x27,0x70,0xf4,0xe5,0x4f,
+  0x8c,0x89,0x63,0xb1,0x0b,0xd8,0xbd,0xd8,0xe1,0x27,0x63,0x17,0xbc,0x97,0x58,0xad,
+  0x81,0x7e,0xf8,0x85,0x92,0x75,0x4a,0x2d,0x3b,0xa6,0x36,0x58,0xb6,0x7f,0xd8,0x70,
+  0x77,0x49,0x46,0x7b,0xf6,0x3a,0xfc,0xb5,0xcf,0x98,0xa8,0x68,0x10,0x6c,0x97,0x67,
+  0xa2,0x22,0x36,0x40,0x46,0x64,0xc2,0x88,0x0d,0xd4,0x12,0xff,0x35,0x51,0x85,0xbe,
+  0x28,0xee,0x95,0xa9,0x71,0x53,0xa4,0x86,0x89,0xfa,0x5f,0xf7,0xd4,0x1e,0x50,0xbe,
+  0x7a,0x1d,0xfe,0x3a,0x0b,0x2f,0x0b,0x92,0xab,0x72,0x96,0xff,0x97,0xca,0xed,0xd6,
+  0xe6,0x75,0xe5,0x44,0x7b,0x7d,0x33,0x33,0x6b,0x9d,0xf2,0x65,0xc9,0x7f,0x65,0x95,
+  0x7a,0x78,0x95,0x0c,0x87,0x97,0xf1,0x0f,0x7a,0xb2,0x2e,0xfc,0xc5,0x0a,0xf8,0xaf,
+  0xe9,0x6b,0xd1,0x99,0x0c,0xf6,0xaa,0x99,0x66,0xe2,0xad,0xfe,0x91,0x70,0x13,0x1a,
+  0x5e,0x6a,0xa9,0x5c,0x01,0x6f,0x8c,0xd6,0x59,0x21,0xdb,0x3f,0x1c,0x55,0xbb,0x6e,
+  0xa4,0x7f,0xe8,0xe9,0x84,0xfb,0xac,0x2f,0x64,0xee,0x0e,0xcf,0x20,0xb6,0x6b,0x87,
+  0xf8,0xf8,0xb4,0xe0,0x12,0xa2,0xbd,0x8a,0xed,0x3a,0x50,0x35,0xf0,0x24,0x9b,0x9f,
+  0x8b,0xb3,0x8a,0x87,0xba,0x0a,0xf0,0x97,0x29,0xf9,0xca,0x15,0x49,0x6f,0xd6,0xda,
+  0x48,0x89,0x7b,0x49,0xc3,0xe8,0xdb,0x21,0xe8,0x69,0x95,0xc8,0x97,0x4d,0xfe,0xe2,
+  0xa4,0x9e,0x1d,0x28,0x36,0x7c,0x6b,0xe0,0xc9,0x0a,0x51,0x5e,0x56,0xfa,0x1b,0xa1,
+  0x42,0xfd,0xc3,0x78,0x4d,0xaf,0xf6,0xbc,0xf2,0x11,0xf9,0xc6,0x67,0xaa,0x33,0xbe,
+  0x30,0x7b,0x0b,0xba,0x06,0x70,0x50,0xc2,0xe6,0x09,0x23,0x0d,0xa1,0x51,0x26,0xd3,
+  0x88,0xaa,0xb9,0x12,0xc2,0x4b,0x3d,0x90,0x8b,0x1f,0xf3,0xa7,0x96,0xba,0xf1,0x57,
+  0x3c,0x4f,0x69,0xbd,0x59,0x4a,0x82,0x93,0x32,0x62,0xaa,0x72,0x32,0x25,0x15,0xf6,
+  0xa6,0x1f,0x25,0x21,0xc4,0x57,0x4a,0xd7,0xa1,0x0f,0x39,0xa1,0x2f,0x70,0xe5,0x7f,
+  0x65,0x6f,0xc0,0x7f,0x51,0xda,0x97,0xd0,0x17,0x1d,0x25,0x6d,0x0d,0x58,0x65,0x2d,
+  0x25,0x45,0xc4,0x05,0x20,0xe3,0x7b,0xf9,0x22,0xca,0x08,0x6b,0x14,0x37,0x6f,0x11,
+  0x2d,0x89,0x05,0xd6,0x8d,0xf8,0x2f,0xec,0xba,0x1f,0x40,0x78,0x40,0x70,0x5b,0x9d,
+  0xd4,0xc2,0x99,0xdf,0x3b,0xce,0x83,0xb9,0xfc,0xaf,0x78,0x68,0xaf,0x72,0x7f,0x5e,
+  0xac,0xbe,0x1b,0x7b,0xbe,0x85,0x50,0x52,0x01,0xfe,0x92,0xa1,0xb6,0x0e,0x10,0xdb,
+  0x4d,0x55,0xec,0xa9,0x10,0x18,0xf1,0x5f,0x0e,0x9f,0x82,0xa8,0xb6,0x59,0x80,0x62,
+  0xa7,0x52,0xf9,0x5e,0x4b,0xbd,0x2e,0xfe,0x50,0xc8,0xfa,0xfd,0x40,0x26,0x00,0x0e,
+  0x19,0x9d,0x70,0x7f,0x5a,0xe3,0x89,0x1a,0x0a,0xda,0x2f,0x72,0x46,0x99,0x4e,0x38,
+  0xd7,0x7a,0xee,0xb2,0x5f,0x12,0xef,0x11,0xf8,0x3a,0x7d,0x1f,0x57,0xfe,0x97,0xe4,
+  0xbf,0x96,0xa2,0xd1,0x21,0xcb,0x04,0xd0,0x39,0x52,0x45,0xa0,0x47,0x99,0xaf,0x5e,
+  0x84,0xae,0x51,0x27,0xbe,0x37,0xee,0x27,0xbc,0x4c,0x7a,0x17,0xf6,0x49,0x45,0x03,
+  0x39,0xd2,0xb6,0xfe,0xea,0x68,0x8e,0xff,0xaa,0x94,0xb2,0xf3,0x38,0x16,0x96,0x49,
+  0xea,0x0d,0x81,0x87,0x3b,0x27,0x71,0x69,0x68,0xcc,0x3a,0x95,0xf2,0x5a,0x03,0x26,
+  0x71,0x64,0xde,0xef,0x5a,0x36,0x23,0x76,0x07,0xd5,0x9c,0x1a,0xb3,0xbf,0x4f,0x9e,
+  0xff,0x1a,0x31,0x4e,0x98,0xc2,0x57,0x1f,0xa6,0xf3,0x16,0xee,0x3f,0xa0,0x54,0xc1,
+  0x71,0x4a,0x64,0xb6,0xf9,0x2f,0x1e,0x48,0x91,0xf0,0x4e,0x2e,0xe4,0x20,0x18,0xc5,
+  0x89,0xef,0xd4,0xff,0x3a,0xe3,0xe2,0xbf,0x60,0x93,0x5e,0x63,0x95,0xe4,0xce,0x2e,
+  0x0e,0x34,0xd7,0xf0,0x0e,0x23,0x1f,0x6d,0x38,0xa3,0x33,0xcd,0x1a,0xf3,0x64,0xf4,
+  0x11,0xf3,0x39,0x2a,0x50,0x1e,0x2d,0xc4,0x5f,0x38,0x04,0xa7,0x4d,0x0e,0xf6,0x1a,
+  0x85,0x9b,0x14,0xb4,0x78,0xd9,0x13,0x06,0x77,0xf1,0x95,0xe9,0xc2,0x52,0x6e,0x47,
+  0x70,0x93,0xc2,0x4b,0x11,0x39,0x2d,0x32,0x79,0xfc,0xf5,0x36,0xe9,0xa2,0x13,0x0a,
+  0x20,0x20,0xf6,0x8d,0xb8,0xda,0xc2,0x7e,0xd4,0xfa,0xe8,0xeb,0x15,0x86,0x6a,0xe7,
+  0x7f,0xc5,0x6f,0x59,0x43,0xda,0x11,0xed,0xe2,0xe6,0xaf,0xf0,0x83,0x29,0x11,0x88,
+  0xa8,0xca,0xe7,0x08,0xfe,0x4b,0xc6,0x1f,0x7e,0xcc,0x2d,0x68,0x1c,0xf6,0x47,0x97,
+  0xf6,0xb3,0xa5,0xd0,0x08,0xd8,0x2d,0x5b,0x12,0x7d,0x7a,0xc6,0xf2,0x4a,0x45,0xc4,
+  0xc6,0x5d,0x01,0x3d,0xe9,0x67,0x17,0x09,0xa3,0xdd,0xae,0x9c,0x82,0x8b,0x7b,0xeb,
+  0xa8,0x33,0xcb,0x8a,0xf2,0xf8,0x0b,0x6e,0x15,0x43,0xd0,0x3c,0x29,0xcb,0x3a,0x5c,
+  0x12,0xf5,0xb2,0x45,0x1e,0xeb,0x98,0xde,0xd4,0xef,0xcc,0x26,0x08,0xdc,0x4b,0xb1,
+  0x07,0x37,0x39,0xe4,0xa6,0x7e,0x97,0x8c,0x3f,0x34,0x6c,0xfc,0xe5,0xa5,0xda,0xca,
+  0x22,0xa4,0xf0,0x18,0xef,0xb2,0xc3,0x0e,0xbd,0xc2,0x03,0x09,0xc3,0x87,0x2c,0x9a,
+  0x5d,0xe9,0xcc,0x6e,0x74,0x7b,0x04,0x10,0xa3,0xb0,0x55,0x4a,0x05,0x8d,0x52,0x6a,
+  0xe1,0xf5,0xfc,0xd7,0x59,0x78,0x5c,0xea,0x1b,0x9f,0x81,0x83,0x6c,0x0e,0xc9,0x1e,
+  0x36,0xc2,0xaf,0x68,0x7f,0x97,0x5b,0x12,0xba,0x73,0xc0,0x6e,0x75,0xe7,0x77,0x57,
+  0x0c,0xe0,0xa5,0xd7,0xdc,0xf8,0x4b,0xf6,0xb3,0xda,0x2e,0xa5,0xfb,0x65,0x6d,0x65,
+  0x52,0xe4,0x30,0x7e,0xe2,0x6a,0x49,0xab,0xf7,0xd8,0x1a,0x1d,0xb6,0xce,0x49,0xc5,
+  0x08,0x0e,0xca,0xf5,0xfc,0xd7,0x08,0x70,0xcb,0xb0,0x3a,0xc4,0x46,0x06,0x61,0x5d,
+  0x5b,0xe8,0x2b,0xed,0xe0,0xcd,0xc6,0xa0,0x33,0xee,0xd0,0x31,0x2f,0xe8,0x1e,0x77,
+  0xfa,0xaa,0x19,0xf6,0xe6,0x75,0xf8,0x6b,0x18,0x4e,0x9d,0x89,0x72,0x3f,0x71,0x5b,
+  0x87,0x69,0xf9,0x22,0x22,0xec,0x67,0x19,0xda,0x09,0x6d,0xfe,0xcb,0x3f,0xa4,0x15,
+  0x68,0x74,0x44,0x45,0x21,0x30,0xcf,0x54,0xfc,0x75,0x4e,0x24,0xef,0x0b,0x07,0x6f,
+  0x0c,0xea,0x58,0xa0,0x2d,0x99,0x55,0x47,0xa5,0x78,0x75,0x3e,0xff,0xcb,0x45,0x96,
+  0x79,0x45,0xec,0xdc,0x6b,0x72,0x5e,0xb8,0xf1,0x17,0x97,0xb5,0x95,0x97,0xda,0x7a,
+  0x71,0x33,0x95,0x2a,0x21,0x44,0x6f,0x7b,0x95,0x8d,0x2d,0x22,0xb4,0xf5,0x98,0x92,
+  0x73,0x4a,0x1f,0x88,0x6b,0x85,0xf5,0xbf,0x6c,0xdc,0xc4,0x37,0xe6,0x0a,0x31,0x93,
+  0xf1,0x74,0x70,0x2e,0x3b,0x06,0xbb,0x72,0x2c,0xd5,0xfa,0x50,0x8a,0xf2,0xb6,0xf2,
+  0xa1,0x89,0xc1,0x75,0x68,0x18,0xf2,0x7d,0x76,0xd5,0x5f,0xc6,0x8f,0xeb,0xf9,0xe7,
+  0x58,0xda,0xd6,0x44,0x91,0xf1,0xd4,0x8c,0xa0,0x53,0x6d,0xb9,0xc6,0xec,0xd8,0x21,
+  0x29,0xb6,0xdc,0x73,0xee,0x59,0x91,0x2a,0xac,0xff,0x25,0x71,0x41,0x73,0x52,0x0f,
+  0x2f,0x93,0x9c,0x8b,0x77,0xad,0x20,0xc2,0xcc,0xad,0xdc,0x15,0x05,0x07,0x33,0x7d,
+  0xde,0xb4,0x28,0xe7,0x41,0x2d,0xdd,0x90,0x5e,0xae,0xe9,0xbe,0xeb,0xf1,0x57,0x2f,
+  0x0c,0xac,0x89,0xe9,0x04,0xbb,0x88,0xff,0xf2,0x05,0x1e,0x4b,0x56,0x4c,0x3b,0x33,
+  0x2f,0xaa,0x39,0xfd,0xec,0xa3,0x1c,0x31,0x3e,0xe0,0xf4,0xf3,0x68,0xab,0x31,0x2b,
+  0xc0,0xb5,0x9a,0xe9,0xd7,0xe1,0x2f,0xe2,0xbf,0x5a,0x3a,0x65,0x6d,0x2f,0xaa,0xb6,
+  0x2c,0xf4,0x0f,0x9d,0x68,0x43,0x99,0xed,0x25,0xb0,0xb0,0x5b,0xf3,0x21,0xf9,0xb1,
+  0x5b,0x7f,0xde,0xc5,0x7f,0x39,0xf7,0x2c,0x99,0x45,0x44,0xd8,0xab,0xde,0x1c,0x3b,
+  0x29,0xd4,0x0e,0x1d,0x30,0x42,0xa9,0x61,0x52,0x7f,0xfe,0xd4,0x75,0xfc,0x97,0x85,
+  0x4e,0xbb,0x91,0x67,0xbb,0x4a,0x08,0x6d,0x9d,0x81,0xfb,0x9c,0x44,0xb0,0x1a,0x78,
+  0x3c,0x1d,0xcc,0xe6,0xcf,0xac,0xec,0x88,0xc4,0x57,0xe0,0x3a,0xfc,0x55,0x10,0x5b,
+  0x78,0xaf,0x14,0x99,0xe7,0x46,0x9c,0x84,0xe8,0xbd,0xfb,0x3d,0x6b,0xe3,0x04,0xbb,
+  0x18,0x49,0xd3,0xdf,0xa2,0x7f,0x56,0xe6,0x7f,0xdd,0x72,0x23,0xfe,0x8b,0xd4,0xe6,
+  0x83,0xf4,0x02,0xbc,0x2b,0x22,0x5a,0x43,0xc4,0x9f,0xfe,0xd0,0x10,0x24,0x97,0x1c,
+  0xf7,0x8d,0xdb,0x9c,0x57,0x2b,0x05,0x43,0xb0,0xdf,0x33,0x77,0x89,0xd0,0x9f,0x17,
+  0xcf,0x29,0xe0,0xbf,0x8e,0x99,0x51,0x19,0x72,0x49,0x2d,0xea,0x36,0xed,0xf3,0xfc,
+  0x98,0xb9,0xcb,0xe9,0x9f,0xd8,0x83,0x7e,0xc4,0x4d,0xec,0x5f,0x25,0x58,0xcb,0xa9,
+  0xfa,0x0f,0xdb,0xf5,0x92,0x0a,0xf1,0xd7,0x8b,0xce,0x01,0x45,0x23,0x05,0x19,0xbe,
+  0x6b,0xd8,0x55,0xd5,0xc4,0xbc,0xa0,0xf0,0xc5,0x7e,0xef,0x75,0xfa,0x1b,0x36,0x6e,
+  0xca,0xe3,0xaf,0x2c,0x1f,0x68,0xe9,0x12,0x22,0x1b,0xde,0x33,0xe4,0xf3,0x7b,0xff,
+  0xca,0xd0,0x2d,0x3d,0x02,0xb3,0xf2,0x14,0xb6,0x46,0x7a,0xb0,0x4e,0x8c,0xab,0x1e,
+  0x9b,0x92,0xff,0x65,0x47,0x12,0x5e,0x16,0xb9,0x5d,0x84,0xad,0xf4,0x4d,0x45,0x52,
+  0xff,0xd0,0xfb,0x04,0xec,0xe2,0xf5,0xe9,0x32,0x99,0xff,0xa5,0x0d,0x23,0x22,0x7b,
+  0xd3,0x11,0xeb,0x78,0xa2,0x57,0xa8,0x26,0x4a,0x98,0xe2,0xe6,0xbf,0x4e,0x43,0x47,
+  0xab,0xcd,0x7a,0x88,0xc8,0x6a,0x48,0x84,0x19,0xe7,0x62,0x65,0xa3,0x75,0x6c,0x6d,
+  0x58,0xf3,0xf7,0xf9,0x1d,0x45,0x7a,0xdc,0xe3,0x06,0xc2,0x59,0xf4,0x52,0x58,0x21,
+  0xff,0x45,0x9a,0x0f,0xb8,0xeb,0x55,0x0c,0xab,0xeb,0x9a,0xdf,0x96,0x11,0xe3,0xcb,
+  0x8a,0x66,0x48,0x20,0x66,0xa3,0x2d,0x53,0xbb,0x27,0xe1,0x17,0x44,0x18,0x85,0xde,
+  0xd1,0x3d,0xa3,0xc5,0x0f,0xe1,0xfe,0x25,0xe6,0xa9,0xab,0xfe,0xf2,0xdb,0xac,0xbf,
+  0xed,0xf6,0xff,0xf0,0x13,0xb7,0x25,0xf4,0x0f,0x67,0x6a,0x0d,0x22,0xdb,0x4b,0xc5,
+  0x4b,0xde,0x4f,0xdb,0x16,0x1b,0x81,0xd0,0xd2,0xd9,0xf0,0xe7,0x8e,0xfe,0xc6,0x2b,
+  0xe8,0x98,0x55,0x4f,0x2a,0x3e,0xb9,0x7f,0xb9,0xf4,0x37,0xb2,0xa4,0x33,0xf9,0xba,
+  0x90,0x31,0x17,0x27,0xc9,0x14,0x06,0xe0,0x8e,0x5e,0x83,0x92,0xd4,0xd2,0xbc,0xf8,
+  0xb9,0x58,0x60,0x4b,0xaf,0xd7,0x9f,0x1f,0x2b,0xbf,0xa0,0x9f,0x4c,0x75,0x89,0x22,
+  0x5f,0xde,0xd3,0x74,0x62,0x3f,0x80,0xb0,0x6b,0x84,0x44,0x0e,0x7b,0x84,0x7f,0x18,
+  0x33,0xfc,0xd8,0xc2,0x3e,0x49,0xd8,0xc9,0x2c,0x76,0xfd,0xe5,0x33,0x39,0xfe,0x0b,
+  0xfb,0x50,0xfc,0xe4,0x91,0x65,0x8f,0x46,0x82,0x43,0x3e,0xc4,0x4d,0xfc,0x97,0x14,
+  0x7f,0x68,0x32,0x83,0x6f,0x48,0x55,0x5b,0xd3,0x1e,0x12,0xd9,0xca,0xe1,0xbd,0xea,
+  0xbd,0x24,0x57,0x98,0x6e,0xa4,0x9b,0x4f,0xa1,0x13,0x58,0x6b,0x52,0xfd,0x65,0xb0,
+  0x57,0x44,0xd7,0x39,0x64,0xfb,0x17,0x2a,0x48,0x87,0xea,0xa4,0x94,0xf7,0x07,0x36,
+  0xcb,0xfb,0x0c,0x79,0x20,0x32,0xb2,0x31,0xec,0x47,0x9c,0x4b,0xb2,0x87,0x79,0x9d,
+  0x93,0x7e,0xf5,0x06,0xfa,0xf3,0xcc,0x52,0x69,0x94,0xd1,0xab,0x7c,0x95,0x06,0x77,
+  0x50,0x54,0xb4,0x4c,0x9a,0x42,0x7f,0x9e,0xee,0xf1,0x83,0x6a,0x30,0x3f,0xdb,0xed,
+  0xe8,0x6f,0xf4,0x40,0xb8,0x0d,0xf7,0x2f,0x3b,0x8e,0xc8,0xc5,0x7f,0x8d,0xb0,0x13,
+  0x7c,0x81,0xb5,0x39,0xb3,0x94,0x1c,0xfb,0x9a,0x41,0xdc,0xa4,0xe6,0xc0,0xfb,0x3a,
+  0x29,0x9b,0x89,0x7e,0x9e,0x9d,0xd9,0xbc,0x59,0x23,0x59,0xec,0x1a,0x27,0xe0,0x13,
+  0x7d,0xb6,0x51,0xe5,0x03,0x67,0x5f,0xce,0x9f,0xd3,0x7a,0x2f,0xdb,0x5c,0x24,0x17,
+  0x1a,0x6e,0x7b,0xb4,0xf7,0xf8,0xb8,0x95,0x1b,0xaf,0xc6,0x35,0x01,0xa8,0x74,0xd2,
+  0x5b,0xec,0xe7,0xa0,0x61,0xf3,0x56,0x2e,0xfc,0x25,0x6a,0xfe,0x4a,0x20,0x76,0x9a,
+  0xea,0x96,0xae,0x53,0xea,0xcd,0x5f,0xf0,0x7c,0xb4,0xa1,0xd7,0xff,0xb4,0xe2,0xb7,
+  0x83,0x15,0x19,0x25,0xb9,0x2f,0x58,0xed,0x1f,0x2d,0x87,0x2f,0xe5,0xf0,0xd7,0x0f,
+  0x1d,0xfe,0xe2,0xb0,0x65,0x6b,0x62,0x08,0x27,0x70,0xaf,0x2f,0x04,0x1b,0x07,0xf3,
+  0x51,0x82,0xba,0xfa,0x34,0x22,0xa9,0xb7,0x1c,0xff,0xb0,0x27,0x15,0x8c,0xa2,0xff,
+  0x6c,0x5c,0xc7,0x7f,0x65,0x29,0xf9,0x28,0xc7,0x6d,0x91,0xfe,0xa1,0xd0,0x01,0xce,
+  0x3d,0x67,0x50,0x6d,0xc7,0xe7,0x3c,0x97,0xd7,0xe8,0x30,0xc8,0x05,0x35,0xe4,0xfc,
+  0x42,0xfc,0xe5,0x92,0x49,0xf1,0x86,0x4f,0x76,0xda,0x7e,0x26,0x11,0x61,0xc0,0xda,
+  0x8c,0xb4,0x0c,0x4d,0xec,0x5e,0xb6,0xf6,0x4c,0x08,0xfd,0xcc,0xd2,0x27,0x55,0x79,
+  0x33,0x4f,0x49,0x17,0xd4,0x9e,0xef,0x02,0x7f,0x99,0x72,0x5e,0x98,0x63,0xd0,0x74,
+  0x5c,0x74,0xf8,0x09,0xd2,0x0f,0x47,0xef,0x4b,0x44,0x1f,0x69,0x5d,0x02,0x4a,0xc7,
+  0x6e,0xf6,0x73,0x8d,0x64,0xc3,0x69,0xee,0x50,0x4b,0x6b,0x97,0x89,0xfe,0x33,0x14,
+  0xc9,0x78,0x2d,0xc4,0x5f,0xbf,0x0b,0x89,0xee,0x1d,0xe5,0xe8,0x1f,0xba,0xb0,0x95,
+  0xa5,0x8c,0x19,0xe3,0xa6,0x5d,0x9f,0xe8,0x9a,0x2c,0x85,0x33,0xe9,0x04,0x53,0x7d,
+  0x64,0x5c,0xaf,0x3f,0x9f,0xc3,0x5f,0xd7,0x0c,0x1c,0xa6,0x0b,0x4a,0xa3,0x71,0x4d,
+  0x6d,0x3a,0x7e,0xfa,0xc2,0xae,0x46,0xcf,0x44,0xae,0x82,0x76,0xa8,0xe9,0xb8,0x4c,
+  0xd3,0x03,0x8a,0xf8,0x65,0x57,0xe1,0x8a,0xe7,0x26,0x63,0xd5,0x20,0xb8,0xea,0x7f,
+  0x4d,0x08,0x48,0xa5,0xfc,0x0c,0x5e,0xc2,0xcf,0x04,0x26,0xd9,0x4b,0x68,0xd4,0x8e,
+  0x6a,0x93,0xec,0xe7,0xf0,0x49,0xbc,0x72,0xf4,0x96,0x49,0x76,0xcd,0xf3,0x92,0xd5,
+  0x34,0xaa,0x5d,0x61,0xd7,0x48,0x08,0xd1,0xd6,0xdf,0x48,0xa0,0xb1,0xa3,0xa0,0xfe,
+  0x97,0xe8,0xe7,0xbb,0x4f,0x7a,0xbb,0x75,0x3f,0x1d,0x6b,0xf8,0x9d,0x0c,0xa3,0xc7,
+  0x11,0x02,0xa7,0x07,0xb5,0x85,0x64,0x40,0x4e,0x0b,0xc5,0x8e,0x10,0xd8,0x4f,0x13,
+  0x44,0xbf,0xbe,0xfe,0x57,0x33,0x19,0x73,0x7b,0x97,0x4b,0x03,0x91,0x6f,0xc6,0xdc,
+  0xe7,0x08,0xb9,0x88,0x71,0xef,0x95,0xd2,0xeb,0x4e,0x8d,0xef,0x9e,0x8e,0xf9,0xf8,
+  0x7d,0x82,0x91,0xc2,0xfc,0xaf,0x12,0xfb,0x68,0xc8,0xea,0xcc,0x54,0xa2,0x93,0xcc,
+  0xc8,0xa3,0x46,0xe3,0x08,0x8b,0x5a,0x4a,0xa6,0x72,0x9f,0x4a,0x67,0x20,0x5b,0x32,
+  0x7f,0xeb,0x0a,0xa8,0x9e,0xe0,0x0d,0xd9,0x55,0x3b,0xca,0x5d,0xf5,0x97,0x3f,0x91,
+  0x43,0x60,0x03,0xb1,0x75,0xce,0x78,0x65,0xda,0xa4,0x10,0xbd,0xac,0x42,0xee,0xbd,
+  0x45,0x76,0xf8,0x41,0x68,0xea,0x15,0xc6,0x05,0x52,0x44,0x34,0x92,0x37,0xd4,0x3f,
+  0x64,0x39,0x3d,0x46,0x01,0xb2,0xd6,0x8a,0x3a,0x11,0x5b,0x32,0x41,0x92,0xd1,0xab,
+  0xc1,0xa5,0xa0,0x92,0x14,0x1e,0x9c,0xef,0x13,0x6f,0xc8,0x9e,0xe4,0x8a,0xab,0xfe,
+  0xd7,0x87,0xf6,0xab,0xae,0xfe,0x0b,0x1d,0xa7,0x8f,0xca,0x73,0xf5,0x5e,0x5c,0xac,
+  0x1a,0x61,0x0b,0x19,0x76,0xcb,0x70,0xc9,0x28,0x3b,0x8a,0xfd,0x53,0x97,0x4b,0x16,
+  0xb3,0xd4,0x9f,0xb8,0xf0,0x97,0x5e,0xe9,0x96,0x34,0xd4,0x72,0xfb,0x17,0x1a,0xde,
+  0xe7,0x3c,0xc4,0x02,0x3b,0xfa,0x87,0x54,0xa2,0x77,0xbf,0x9e,0x1b,0x2f,0x63,0x23,
+  0x7a,0x20,0x0d,0xf9,0xfc,0xaf,0x67,0x9c,0xbc,0xa4,0xef,0xf3,0xea,0x11,0x61,0x2c,
+  0xe2,0xd5,0xe7,0x3a,0xbf,0xdd,0xf7,0x23,0xc1,0xc2,0x24,0x1d,0xd9,0xc3,0xe2,0x3b,
+  0x45,0x8e,0xd8,0x1c,0x89,0x0b,0x0e,0x74,0xec,0xce,0xaa,0x7f,0x8d,0xdf,0x59,0x7c,
+  0x1f,0xc2,0x5f,0xff,0x61,0xe7,0x7f,0xc9,0xda,0xca,0xb7,0x2b,0x27,0x4d,0x44,0x5b,
+  0x64,0x8c,0xb4,0xec,0xc6,0x55,0x7d,0xc3,0x9d,0xb8,0x62,0x5f,0xd4,0x1b,0x87,0x1f,
+  0x8f,0xe0,0xfa,0x73,0x71,0xdb,0xba,0x01,0x71,0xf3,0x79,0xa8,0xb7,0x56,0xe6,0xf9,
+  0xaf,0xcf,0x51,0x6c,0x61,0x93,0xb5,0x94,0xba,0xee,0x77,0x4b,0x28,0xb6,0x70,0xe9,
+  0x15,0xa9,0x3f,0x7f,0x5e,0xf9,0x86,0x71,0xad,0x15,0x07,0xee,0x0f,0xca,0x15,0x5a,
+  0x0f,0x5f,0xa7,0x31,0xf5,0x7c,0xea,0xb5,0x83,0xc0,0xc7,0xa8,0x2a,0x44,0x2a,0x97,
+  0xff,0xe5,0x71,0xf3,0x5f,0xe6,0x23,0x03,0xfe,0x2e,0x12,0xde,0x31,0x62,0x03,0x81,
+  0x28,0x95,0xc9,0x36,0x1f,0x18,0x08,0x1c,0x50,0x7e,0x4a,0x2d,0x83,0x81,0xc3,0x4a,
+  0x38,0xbf,0x33,0xa2,0xff,0x93,0x5d,0x99,0xf2,0xcc,0x9f,0xa2,0x7f,0x68,0x07,0xb7,
+  0xbf,0xe6,0x7b,0x30,0x71,0xd6,0x73,0xb0,0x65,0xf1,0x6b,0xda,0x83,0xc9,0x2f,0xf3,
+  0x83,0xf7,0xdd,0x71,0x3c,0x20,0x4a,0xa2,0xcc,0xab,0x1e,0x08,0x3c,0xb0,0x9b,0xb4,
+  0x79,0xed,0x9b,0x0f,0xc0,0x4e,0x4b,0x35,0x3f,0xeb,0xd2,0x9f,0xcf,0xc9,0x1e,0x1e,
+  0x4c,0x85,0xdf,0xef,0x78,0x88,0xbd,0x6d,0x22,0xaa,0x1d,0xd6,0x1e,0x0a,0x8a,0x12,
+  0x6c,0x43,0x9d,0xdf,0xa6,0x96,0x54,0xf5,0x90,0x76,0x27,0x9b,0x6d,0xe5,0x92,0xf2,
+  0xf6,0xf3,0x9d,0x59,0x55,0x2d,0x35,0xae,0xc3,0x5f,0xb9,0x1a,0xe8,0x8e,0x48,0x54,
+  0x91,0x1f,0x16,0xe0,0x5f,0xf2,0x45,0xe0,0xa4,0xba,0x00,0xfc,0x96,0xd0,0xf8,0xcd,
+  0x6b,0x99,0x42,0xfc,0x92,0x5a,0x54,0x53,0x76,0x03,0xfc,0x25,0xc2,0x0e,0xf3,0xda,
+  0x86,0x3e,0x42,0x5b,0x0c,0xbd,0x26,0xcf,0x30,0x3c,0x84,0x6e,0x99,0xd0,0x48,0xbc,
+  0xe0,0xdc,0x7c,0x15,0x16,0xa4,0xfc,0x43,0x4a,0x34,0xc7,0x7f,0xe5,0xe2,0x9a,0xd4,
+  0x31,0x7c,0x1b,0x02,0x20,0xf0,0x17,0xf9,0x75,0x85,0x2a,0x6a,0x8f,0xd0,0xb9,0xba,
+  0xe5,0x6a,0x59,0x12,0xf3,0x14,0xd6,0xff,0x1a,0xcf,0x6b,0xe5,0x3d,0xe2,0xa4,0x11,
+  0x35,0x52,0x6c,0xe1,0x32,0xc4,0xb9,0x79,0x0f,0x7f,0xb5,0x9f,0xb4,0xb8,0x8f,0x79,
+  0xec,0xfc,0xaf,0xf3,0x6a,0xc3,0x03,0x81,0x9b,0xdc,0xf8,0x6b,0x3c,0x0f,0x85,0xee,
+  0x17,0x75,0xc4,0x04,0xc8,0x5a,0xf3,0x23,0xe5,0x27,0x20,0x64,0xc3,0x73,0xe5,0x92,
+  0x29,0x7f,0xf9,0x5f,0x73,0x71,0x83,0x54,0xcd,0x61,0xfb,0x0d,0xf9,0xaf,0x43,0x1e,
+  0xe2,0x38,0x9a,0x25,0xc8,0x22,0x65,0x06,0xf3,0xa9,0x82,0x68,0xc3,0xad,0xe4,0x87,
+  0x73,0xe7,0xe6,0xd6,0xf9,0xcd,0x5a,0xca,0xad,0x3f,0xbf,0x33,0x27,0xb5,0x67,0x84,
+  0x5b,0x8a,0xcb,0xd8,0xb2,0xb6,0x36,0x83,0xb4,0xe5,0xcb,0xda,0xad,0xad,0x91,0x50,
+  0xcb,0x2d,0x65,0x14,0x6d,0x58,0x11,0x6e,0xf1,0x91,0xb1,0xd3,0xa8,0x72,0x6e,0x46,
+  0x10,0x51,0xe6,0xf3,0xe5,0xf1,0x17,0x61,0x10,0xbb,0x33,0x6b,0x9c,0xa2,0x09,0x42,
+  0xad,0x6e,0x1e,0x0c,0x9a,0xd1,0x1c,0xab,0x28,0xf5,0xeb,0x06,0xf2,0x3d,0x2f,0x42,
+  0xcb,0xae,0x8b,0x3f,0xf4,0x08,0xc1,0xc9,0x3f,0x0d,0xc8,0xb4,0xaf,0xd8,0xb2,0x2d,
+  0x5b,0xa7,0xef,0x19,0x7c,0x3f,0x12,0x5b,0x86,0x2d,0xab,0xcd,0xf1,0x32,0x61,0x0c,
+  0x99,0x57,0x6e,0xb2,0xfb,0xf9,0x8a,0xbe,0x98,0xea,0x2f,0xff,0xde,0xc9,0xff,0x2a,
+  0x90,0xda,0x6b,0x70,0x62,0x0b,0x63,0x66,0x69,0x2b,0xe2,0xaf,0xbf,0xce,0x8f,0xd7,
+  0xad,0x84,0xbf,0xaa,0xec,0x88,0xc4,0xa5,0xa4,0x5a,0xff,0x5f,0xe8,0x2c,0xe5,0x6b,
+  0xd7,0xc7,0x1f,0x42,0x8f,0x27,0x08,0xab,0x48,0xff,0xf0,0x8c,0xc8,0xff,0x52,0x4c,
+  0x2f,0xa9,0xcd,0xbb,0x10,0x99,0x5d,0x88,0x59,0x93,0xdc,0x5f,0xf0,0xfa,0xfa,0xcb,
+  0x0e,0xec,0x0a,0x49,0x63,0x2b,0x1a,0x22,0xfe,0x70,0xab,0x8d,0xc8,0x44,0x2e,0x1e,
+  0x7a,0x05,0x82,0x1a,0xb3,0x6f,0xe6,0xab,0xe3,0x2b,0x66,0xb2,0xbb,0x6f,0xa8,0x7f,
+  0x68,0x8f,0xf2,0xe7,0x3c,0x41,0x13,0x7d,0x92,0xd5,0xf8,0x02,0xf8,0xf2,0xaf,0x56,
+  0xb1,0xc8,0x0d,0xd4,0x09,0xa3,0x51,0x8b,0xf7,0x3d,0xba,0xe4,0xae,0xbf,0xec,0xee,
+  0x9f,0x2d,0xa9,0xca,0x21,0x78,0x83,0x35,0x98,0x4f,0xe8,0x95,0x55,0x2a,0x9d,0x27,
+  0x6c,0xb1,0xa9,0x5e,0x73,0x73,0xaa,0xb2,0xca,0x9b,0x2f,0x16,0x66,0xd6,0x99,0xa7,
+  0xb7,0x2b,0x6b,0x6e,0x94,0xff,0x25,0x45,0xcb,0xfb,0x9d,0x8a,0x60,0x32,0xc5,0xec,
+  0xd6,0x02,0xd9,0xc3,0xf3,0xdc,0x29,0x16,0xa6,0x36,0x7c,0x6d,0x8a,0xfe,0x46,0x0e,
+  0x92,0x3b,0xc6,0x30,0xe0,0x96,0xd3,0x96,0x8c,0x1b,0x16,0xee,0x2b,0x9d,0xb6,0x90,
+  0xaf,0xf3,0xfe,0xd0,0x6b,0x23,0x14,0x35,0x5f,0x80,0xcd,0x3c,0x99,0x98,0xca,0x7f,
+  0xd9,0x29,0x5d,0xa5,0xb9,0xdc,0xae,0x21,0x76,0x27,0x22,0xe8,0xf9,0x7c,0x45,0x3a,
+  0x48,0x2d,0x46,0x5a,0x8d,0xb3,0xe1,0xa2,0x4d,0x4e,0xfe,0xd7,0x8b,0x56,0x65,0x4a,
+  0x1d,0x46,0x7f,0xcc,0x9c,0x82,0xbf,0x5c,0xeb,0x98,0xa8,0xa3,0xa1,0x16,0xfd,0x1d,
+  0xe4,0xbc,0x6e,0xaa,0xfd,0x4a,0xd0,0xcc,0x93,0xcc,0xb5,0xe8,0x46,0x36,0xd4,0xc8,
+  0x36,0x5d,0x17,0x7f,0x28,0x53,0x8d,0x7c,0xb6,0xd1,0xab,0x99,0x45,0x9f,0x41,0x14,
+  0x30,0xcf,0xbe,0xc4,0xe7,0x34,0xab,0xad,0x08,0x2b,0x36,0xe4,0xf5,0x91,0x2a,0x46,
+  0xd5,0x48,0xa2,0x40,0x7f,0xc3,0x25,0x69,0x58,0x4a,0xc6,0xef,0xf9,0xe2,0x73,0xab,
+  0x5a,0x96,0xfe,0x0d,0xfb,0x64,0xe0,0x4e,0x47,0x6d,0xe3,0x0e,0x8a,0x3e,0x7a,0xdb,
+  0xfb,0x8b,0xf6,0x5c,0xfe,0x97,0xc8,0x11,0x7b,0xf6,0x46,0xfa,0x87,0x52,0xba,0x4d,
+  0xe2,0x2f,0x8d,0x97,0x0f,0xc3,0x5b,0x66,0x4e,0x3d,0xaf,0x7e,0x89,0x70,0x41,0xcf,
+  0xe7,0x6f,0xae,0xb7,0xb6,0xa4,0x2b,0xf3,0xf9,0x5f,0xe6,0x94,0xfa,0x5f,0xe5,0x57,
+  0xbd,0xd7,0xda,0x9a,0xce,0x05,0x86,0x95,0x3f,0xb6,0x7f,0xc2,0x03,0x43,0x7e,0xaa,
+  0xc8,0x7c,0x3a,0xd5,0xb4,0xac,0x68,0x3d,0x1a,0x57,0x52,0x0b,0x1c,0xb2,0xac,0x32,
+  0xbb,0x6a,0xcc,0xd3,0xea,0xaa,0xff,0xb5,0xb3,0xda,0x52,0x64,0xfd,0xaf,0x99,0x43,
+  0xf4,0xdb,0xa9,0x4e,0x4d,0xbf,0xb6,0x44,0xf9,0x2d,0xd5,0xff,0xa2,0x9e,0x47,0xb8,
+  0xc4,0xeb,0x57,0x63,0xd7,0xe1,0x66,0x17,0xa9,0xc8,0x3a,0xe7,0x87,0xf7,0x68,0x0f,
+  0x38,0xfc,0x97,0x0e,0x4f,0x7b,0x0f,0x1a,0xdf,0xb8,0xbe,0xfe,0x17,0x05,0xe4,0xb7,
+  0x13,0xec,0xea,0x15,0xc2,0x95,0xdf,0xa7,0x3a,0x50,0xad,0xf8,0xc0,0xe7,0x3d,0x4e,
+  0x9e,0x9d,0xb9,0xb3,0xaf,0xf3,0xc1,0xa2,0x65,0x6e,0xfd,0xc3,0xdc,0xb8,0x93,0x4f,
+  0xd2,0xec,0xe0,0x6e,0xd6,0x5f,0x4c,0x86,0x42,0xcf,0xb1,0x5f,0x89,0xcd,0xb2,0x58,
+  0xb3,0xbc,0x39,0x4e,0x4a,0x2c,0x33,0xaf,0xab,0xff,0x55,0xa0,0x5b,0x38,0x9b,0x74,
+  0x33,0xf6,0x88,0xaa,0xa0,0x25,0x22,0xce,0xd3,0x83,0x53,0x06,0x84,0x06,0x72,0x97,
+  0xe3,0x0c,0x44,0x87,0x56,0xf5,0x68,0xb6,0xfe,0xfc,0xf6,0x82,0xfc,0x2f,0xb0,0x0f,
+  0x6c,0x2f,0x92,0x83,0xd7,0x8e,0xcf,0xf9,0x50,0x8c,0xe0,0xf4,0x7d,0xf0,0xa1,0x57,
+  0x2c,0x71,0xee,0xfc,0x2f,0x33,0x96,0x0a,0x1c,0x55,0xde,0xcd,0xd7,0x5f,0x76,0xf0,
+  0x97,0xfa,0xa9,0x10,0xd3,0x16,0xfa,0xf3,0x68,0x0c,0x28,0xeb,0xe1,0x1a,0xfb,0xa6,
+  0xc8,0xff,0xf2,0xfe,0x92,0xe1,0xfb,0x63,0x29,0x8d,0xde,0xf3,0xbc,0x52,0xfa,0x2d,
+  0x17,0x8d,0x05,0xa4,0x1a,0xed,0xe8,0x1f,0x82,0x53,0xff,0x4b,0xd9,0xa7,0x1f,0xb1,
+  0x73,0xd6,0xd0,0xb9,0x0d,0x5a,0x25,0x9b,0xd9,0xb3,0xb0,0x02,0xfe,0x91,0x4e,0xec,
+  0xf7,0x21,0xec,0x9a,0x1f,0x2f,0xf9,0x51,0xe5,0x5a,0x38,0x94,0x72,0x3c,0x6a,0x1e,
+  0x4c,0xe1,0x7a,0x18,0xbf,0x41,0xfd,0x2f,0xf4,0xc3,0xa5,0x0e,0x39,0x19,0x2b,0x12,
+  0xbe,0xfb,0xa0,0x9b,0x05,0xad,0x9b,0x6d,0x8a,0xad,0x65,0x63,0x87,0x50,0x56,0xb4,
+  0xf3,0xc8,0x0e,0x9b,0xbb,0x2c,0xed,0x80,0xab,0xfe,0x97,0x47,0xd6,0x05,0x2e,0xda,
+  0xec,0x41,0x37,0x63,0x50,0x25,0x7a,0x7a,0x37,0xc4,0xfb,0x6f,0x06,0x1f,0x37,0x76,
+  0xd3,0xe8,0x2c,0xc4,0xe9,0xf9,0xa4,0x4f,0x25,0x69,0xa9,0x95,0x24,0x8f,0x23,0x84,
+  0x38,0xbc,0x14,0x2c,0x84,0x46,0x73,0x2e,0xff,0x4b,0x7e,0x1f,0x04,0x59,0xed,0x47,
+  0xbc,0x75,0x6f,0xc8,0x2f,0xd6,0x8a,0xce,0x2d,0x57,0xd6,0xf0,0x97,0x60,0x97,0x9c,
+  0x29,0x27,0x8c,0xba,0xe6,0x12,0xae,0x84,0xbd,0xe3,0xe6,0x61,0xcb,0xd6,0x54,0x21,
+  0x47,0x5a,0x73,0xeb,0x1f,0xa2,0x37,0x38,0xfd,0x80,0xa8,0xff,0x55,0x27,0xf3,0xbf,
+  0xbe,0x6b,0x34,0x0d,0x94,0x98,0xe8,0x9c,0x9c,0x56,0xed,0xf8,0xc3,0xef,0x88,0x4a,
+  0x28,0x95,0x54,0x88,0xb9,0xae,0x20,0xff,0x6b,0x6f,0x1e,0x7f,0x5d,0x91,0x92,0x1a,
+  0xa3,0x74,0x88,0x01,0xc2,0xb8,0x02,0x95,0xe8,0x37,0x95,0x47,0xd0,0xcb,0x6d,0x52,
+  0x15,0x4e,0x72,0x7c,0x10,0x3d,0x5e,0x92,0xab,0xff,0x75,0x77,0x32,0x46,0xa9,0x61,
+  0x56,0x5e,0xff,0x50,0xd4,0xff,0x82,0xba,0xb4,0x4a,0xf8,0xeb,0x08,0xd1,0x28,0x3d,
+  0x62,0x3d,0xdc,0x65,0xa8,0x9c,0xfd,0x84,0xbc,0x02,0xab,0x9a,0x18,0xb1,0x1e,0x6b,
+  0x7e,0xc5,0x0a,0x2e,0xf3,0x80,0xbc,0x2d,0x7b,0x58,0x0d,0xfa,0x63,0x41,0x2b,0xd4,
+  0xa1,0xb8,0xf4,0x37,0xba,0x28,0x5b,0x39,0x52,0x66,0x11,0xe0,0x5d,0x22,0xea,0x32,
+  0xe0,0xcb,0xcf,0x07,0x28,0x2c,0x61,0xab,0x37,0xdc,0x7f,0xdb,0xed,0x65,0x96,0x37,
+  0xb3,0x4c,0x94,0x5d,0xe6,0x26,0xbf,0x89,0x62,0x41,0xa8,0x08,0x91,0x8c,0x9f,0x77,
+  0xf1,0x5f,0x87,0xcc,0xb9,0x1d,0x21,0x2a,0xc9,0x7d,0x44,0x86,0xa4,0x7e,0x10,0x3a,
+  0xcc,0x77,0xa5,0xd5,0xc7,0x48,0x77,0x45,0x86,0xb6,0xc6,0x49,0xd1,0x45,0x14,0x76,
+  0xc1,0x67,0xa8,0xa4,0x60,0x10,0x86,0x1e,0x95,0xbe,0x0f,0xcb,0xe4,0xf9,0xaf,0xb1,
+  0x54,0xd7,0x6b,0x7e,0x91,0xff,0x45,0x21,0x10,0x14,0x88,0x38,0x9e,0x8e,0x76,0x61,
+  0x4b,0x92,0xbf,0x85,0xae,0xfe,0x96,0x8c,0xe7,0x63,0x3e,0xa1,0x47,0xd3,0x81,0x1e,
+  0x5c,0xe0,0x4f,0xf0,0xa8,0x15,0xde,0x86,0xc0,0x79,0x8c,0x72,0xfa,0x36,0x33,0x57,
+  0xfe,0xd7,0x15,0xde,0x94,0xa6,0x9e,0x27,0x92,0xab,0x25,0x30,0x5a,0x39,0x1c,0xba,
+  0x0a,0x8b,0xf9,0x96,0xf5,0xda,0x25,0x7e,0xa5,0xac,0x09,0x34,0x4b,0xb9,0x08,0x97,
+  0xa0,0xa9,0x35,0xd0,0xaf,0x3d,0xec,0xb9,0xb4,0xa3,0x49,0x0d,0x50,0xfd,0xaf,0xc9,
+  0xf4,0x4b,0x7d,0xb8,0x49,0xb9,0xf0,0xd7,0x18,0x44,0xf0,0x4d,0x98,0xfe,0x3e,0x3b,
+  0xa1,0x47,0x4d,0xf1,0xc5,0x7a,0x4d,0x51,0xcb,0x2f,0xcb,0x4f,0x40,0xd4,0x28,0xe1,
+  0xe5,0xe7,0xd4,0x0e,0xa8,0x8b,0xfb,0xa7,0xe3,0x6b,0x33,0xa0,0x47,0x29,0x6c,0x63,
+  0x1f,0x5c,0x34,0xeb,0x07,0xc3,0xdb,0x35,0x57,0xfc,0xe1,0xa1,0xbb,0x85,0xc8,0xc6,
+  0x88,0xde,0x69,0x05,0xff,0x2b,0x85,0xec,0xc2,0xa6,0xc1,0x3a,0xae,0xfd,0x3c,0x91,
+  0x55,0x37,0xca,0xc4,0xf3,0x38,0x76,0xcb,0x3f,0x9a,0x25,0x9b,0x9b,0x47,0xac,0x0e,
+  0x2b,0x68,0xa8,0x9b,0x95,0xb5,0x02,0xba,0x56,0xff,0x73,0xc2,0xc5,0x7f,0x1d,0x91,
+  0x4b,0x93,0x05,0xc9,0x6c,0xc8,0x98,0x29,0x73,0xbb,0xf6,0x99,0x2b,0xd4,0xe6,0x93,
+  0x9e,0x36,0x7c,0xf9,0x8b,0x29,0x70,0x94,0x93,0x4c,0x8a,0x4a,0xba,0x34,0x66,0xa8,
+  0x4c,0x85,0x3f,0xf3,0x93,0x40,0x68,0xaa,0x45,0x85,0xfa,0xbc,0xfe,0xfc,0xfe,0x6d,
+  0x42,0xea,0xe1,0x37,0x94,0xad,0x9c,0x9e,0xb9,0x3e,0xf8,0x1a,0x3c,0xfe,0x83,0x1f,
+  0x93,0x2e,0xfa,0x29,0x78,0x9c,0x1b,0xc4,0xcb,0xac,0xa4,0x4b,0xbc,0x98,0x72,0x97,
+  0x36,0x20,0x52,0x50,0xc7,0x8a,0xbe,0xc2,0x0f,0x66,0x8c,0x1f,0x17,0xb7,0x38,0xe7,
+  0x87,0x22,0xfe,0x90,0xfa,0x27,0xc2,0x7a,0xe1,0x04,0xd4,0xaf,0x09,0x47,0x94,0xfe,
+  0xe6,0x5e,0x68,0x5c,0x16,0x88,0xb2,0x01,0xa3,0x2d,0x13,0xb1,0x4a,0xea,0x11,0x91,
+  0xbd,0x0c,0x55,0x7b,0xfc,0x0b,0xd1,0x0f,0x4f,0x5a,0x3d,0xaf,0xf9,0xf5,0xe4,0x13,
+  0x70,0x31,0x55,0xdf,0x1a,0x9e,0xe1,0x8e,0x3f,0xbc,0x22,0x67,0xca,0x28,0x4d,0x99,
+  0x76,0xc1,0x7f,0xd9,0xb9,0x78,0xa3,0xf0,0x3f,0xa6,0xc9,0x25,0x8e,0x0b,0x45,0xc4,
+  0xf3,0x95,0x94,0xff,0x85,0x78,0xf9,0x8d,0xf2,0x49,0x47,0xb5,0xc3,0xa5,0x7f,0x88,
+  0x2e,0x0d,0x4d,0x6a,0x91,0x10,0xcd,0x79,0xa6,0x62,0x88,0x40,0xb1,0x39,0x9d,0x2b,
+  0x55,0xec,0x04,0x22,0x1c,0x3f,0x95,0x5d,0xb6,0xfd,0xd5,0x7c,0xfd,0x2f,0xd2,0x64,
+  0xe6,0xe1,0x82,0xfa,0x5f,0xb4,0x05,0xb4,0xd0,0xb9,0x9f,0xad,0x76,0xd8,0x8a,0x7b,
+  0xc1,0x4e,0x13,0xf7,0x1d,0xef,0xff,0xd7,0xde,0xdf,0x87,0xc7,0x51,0x5c,0x69,0xc3,
+  0x78,0xf5,0x87,0xe4,0xd6,0xf4,0x48,0xd3,0xfa,0x80,0x15,0xe0,0x98,0xd6,0x48,0x36,
+  0x83,0x33,0x92,0xc6,0x23,0x63,0x8c,0x2c,0x8f,0xda,0x92,0x70,0x06,0xec,0xc4,0x0a,
+  0x61,0x13,0xef,0x2e,0x4f,0x9e,0xb1,0xe3,0xdd,0xf5,0xe6,0x75,0x76,0x05,0xcb,0xb5,
+  0xeb,0x90,0xbc,0xa4,0x34,0x12,0x58,0xb6,0x0c,0x1e,0x1b,0x67,0x63,0x12,0x27,0xcf,
+  0xd8,0x38,0xc1,0x04,0x36,0x19,0xc9,0x06,0xcb,0x1f,0xd8,0x2d,0x23,0x88,0xfc,0x81,
+  0x2d,0x58,0x6f,0x62,0x12,0x2f,0x8c,0x89,0x20,0x02,0x0c,0xc8,0xe0,0x10,0xc9,0x9f,
+  0xef,0x39,0x55,0xdd,0x3d,0x3d,0x92,0x08,0xfb,0x64,0xf7,0x79,0x7f,0xef,0xf5,0xbb,
+  0x18,0xfe,0xe0,0x5c,0x55,0xa5,0xf6,0x4c,0x55,0x77,0xd7,0xb9,0xeb,0x9c,0x73,0xdf,
+  0xb0,0x9b,0x57,0x93,0x7c,0x02,0xdb,0xd6,0xf7,0x78,0x97,0x57,0xa9,0x06,0xd8,0xe5,
+  0x09,0x79,0x26,0x93,0x9d,0xb2,0x4e,0x3d,0x86,0x58,0x94,0xc1,0x5f,0x4f,0xd3,0xb2,
+  0xf4,0x1a,0x2e,0x5d,0x1d,0x4c,0xdb,0x1a,0xd6,0xba,0x34,0x5b,0xfc,0xbe,0xf6,0x5d,
+  0x5a,0xa9,0x93,0x68,0xee,0x14,0xab,0xcb,0x3f,0x45,0x9e,0x84,0xb2,0x5f,0x8b,0xc5,
+  0x29,0xf2,0x0e,0xfa,0xe3,0xb4,0x52,0x0a,0xa0,0xca,0xc1,0x5f,0xbb,0x8b,0xf4,0x34,
+  0xec,0x4d,0x07,0xe9,0x0e,0x4c,0x39,0x08,0x89,0xf3,0xc8,0xde,0x04,0x09,0xe5,0x3d,
+  0x2b,0xc6,0x49,0x2b,0xad,0x9c,0x9d,0xf7,0x05,0x91,0x61,0xc6,0x01,0xa5,0xc5,0xf3,
+  0x19,0xe5,0x71,0xf0,0x37,0x3c,0xcd,0xf0,0x9c,0xee,0xd5,0x2a,0x06,0xa7,0xcf,0x8c,
+  0xbb,0xf5,0xbf,0x68,0x4d,0xb2,0x20,0x29,0x8d,0xea,0x7b,0x48,0x7d,0x9c,0xc5,0xbf,
+  0xa0,0x65,0xbb,0xef,0x8c,0xba,0x87,0xfe,0x9a,0x46,0x7a,0xbc,0x3f,0xb5,0xa8,0xe9,
+  0xa1,0x6b,0x7a,0xc5,0x61,0xb2,0x07,0x0d,0x14,0x0b,0xdb,0x45,0x95,0x6c,0xfd,0xaf,
+  0x58,0x9d,0x9c,0xc3,0xa8,0xd2,0x78,0xb4,0x2b,0x16,0x60,0xb5,0x5d,0xed,0xe0,0x3f,
+  0x0f,0x69,0xf5,0x64,0x11,0xca,0x7e,0x9d,0x20,0x73,0xb9,0xc4,0xfc,0x39,0xf2,0x19,
+  0xcd,0x67,0xa0,0xa7,0xa7,0xcc,0x1e,0xcb,0x3f,0x4f,0x6c,0x92,0x79,0x70,0x80,0xb9,
+  0x61,0xde,0xd3,0xe0,0x4b,0xb4,0x4d,0x23,0x6f,0x91,0x3a,0x63,0xb2,0xc5,0xf0,0xd0,
+  0xb0,0x70,0x53,0xb9,0x9c,0x3c,0xa4,0x87,0x97,0x79,0x37,0x96,0x63,0x29,0x0d,0xfc,
+  0x55,0x36,0xff,0x21,0xdd,0x6a,0x04,0x2c,0x70,0xd4,0x6c,0x19,0x5b,0x0d,0xf5,0x5f,
+  0x3c,0x15,0x89,0xd5,0x62,0x15,0xf2,0x42,0xb0,0x03,0xc0,0x98,0xf2,0x43,0x71,0x2a,
+  0x79,0xc5,0xf0,0x63,0x5a,0x2f,0x2b,0xe0,0x5a,0x1a,0xc8,0xd2,0xff,0x42,0x44,0xa6,
+  0x30,0x6a,0x3b,0x83,0x49,0x3b,0x31,0xfa,0x3b,0xc6,0xc8,0x61,0x30,0x20,0x86,0xf9,
+  0x87,0x3f,0x24,0xe5,0x4d,0x79,0xcd,0xf1,0x9b,0xc8,0x43,0x46,0x79,0x03,0xd3,0x11,
+  0x63,0x14,0x79,0xeb,0xdd,0xf8,0x0b,0x3c,0x46,0x2b,0xd5,0x4d,0x0b,0xf6,0xdd,0xa8,
+  0x89,0x47,0x8d,0x1d,0xac,0x10,0x8c,0xb1,0xf0,0x55,0x7e,0xc1,0x83,0xfa,0x5f,0xdf,
+  0x0d,0x6c,0xb9,0xfd,0xc6,0x3b,0x0e,0x96,0x74,0xa3,0x11,0xb8,0x63,0x0d,0xfc,0x95,
+  0x9e,0xbe,0x5d,0x29,0x8a,0x5b,0xe7,0x87,0x16,0xff,0xa1,0x67,0x2d,0x86,0xbd,0x46,
+  0x8c,0xc8,0xb5,0xf9,0x58,0x08,0x36,0xb2,0xdc,0xef,0x59,0xf4,0x60,0x9b,0xbe,0x15,
+  0xd5,0x9a,0xa2,0x28,0xfb,0x75,0x52,0x0f,0x2b,0x9f,0x17,0x99,0xec,0x72,0x58,0x51,
+  0x0e,0xe2,0x1d,0xde,0x1c,0x56,0xbc,0xc8,0x7f,0xa8,0xd9,0xf8,0xeb,0x92,0x5e,0x8f,
+  0xa2,0xbd,0xe7,0x0a,0x77,0xeb,0xf5,0xd1,0x82,0x84,0x80,0x85,0x60,0x3c,0xfe,0x05,
+  0x8f,0x5e,0xd5,0x6d,0x8b,0xd0,0x7b,0xc7,0x70,0x95,0xb8,0xa1,0xf5,0x4c,0x72,0x34,
+  0x10,0xb9,0xdd,0xf7,0x72,0x2b,0xe2,0x2f,0xae,0xbf,0x3c,0xc9,0x89,0x7f,0x5d,0xb2,
+  0x4b,0xf0,0xfe,0x6f,0xa1,0x1e,0x55,0x0b,0x2f,0x92,0x17,0x61,0xf7,0x5e,0x37,0x20,
+  0xed,0x84,0x15,0xac,0xe6,0x5d,0xbc,0xda,0xab,0x11,0x63,0x64,0x35,0x46,0xb0,0x99,
+  0x01,0xb1,0x9a,0x79,0xc1,0x6c,0xfe,0xc3,0x0c,0xdb,0x21,0xe6,0x16,0xfa,0x59,0x6d,
+  0x17,0x65,0xfa,0x5f,0x3d,0x76,0xb6,0xe1,0x76,0x00,0x62,0x96,0x34,0x18,0x32,0x22,
+  0x02,0x10,0xdb,0x93,0xc5,0x7f,0xc8,0xf0,0x17,0x4d,0x22,0xda,0xea,0xd3,0x38,0xdb,
+  0xbc,0x9f,0xd5,0xba,0x22,0x23,0xc7,0x83,0x08,0xcd,0xb0,0x3c,0xa1,0x49,0xb1,0xaa,
+  0xbd,0x00,0x9a,0x09,0xac,0xf2,0x0e,0x81,0x58,0xd2,0x54,0x4a,0x45,0xd1,0x85,0xbf,
+  0x60,0xdd,0x3d,0x5c,0x36,0x2e,0xd7,0xd6,0x5f,0x66,0xfa,0x20,0x15,0xe4,0x16,0x52,
+  0x15,0x85,0x55,0x7e,0x83,0x3c,0x61,0x4c,0xff,0x22,0x76,0xd1,0x47,0x0d,0xff,0x9d,
+  0xca,0x46,0x0f,0xac,0xbb,0xee,0x4f,0x2b,0x9b,0xb2,0xf1,0x97,0x13,0x04,0xe4,0xb9,
+  0x85,0xda,0x21,0x52,0xdb,0xe2,0xdb,0x2c,0x3d,0x8e,0xc8,0xb7,0xe5,0x61,0x9b,0xba,
+  0xe4,0xa9,0x1f,0x49,0x6f,0x88,0x80,0xc8,0x62,0xc1,0x47,0x55,0xbc,0x9f,0xbb,0x17,
+  0x7b,0x91,0xff,0x50,0x77,0xe3,0x2f,0xa4,0x46,0xd4,0x46,0x09,0xd7,0x5f,0x16,0xcf,
+  0x7a,0x23,0xcd,0x8c,0x41,0x05,0xc3,0x5e,0xea,0x7a,0xe9,0x05,0x63,0x34,0x19,0x59,
+  0x8e,0x78,0x99,0xbc,0x95,0x8c,0x2c,0xe1,0x62,0x61,0x00,0xc4,0xd6,0x69,0xd2,0x61,
+  0xfe,0xde,0x60,0xf8,0x4b,0x0f,0x59,0x64,0xa4,0x42,0xa4,0x04,0x6e,0xa4,0xd3,0x3a,
+  0xe3,0x9f,0x97,0x55,0x3f,0x93,0x2d,0x08,0x72,0x68,0x06,0xaf,0xc1,0xb8,0x5a,0xa6,
+  0xf7,0x2b,0x61,0x31,0x48,0xdb,0x90,0x91,0xbe,0x5b,0xf1,0xb5,0xba,0xf3,0x0f,0xf7,
+  0x1b,0x3f,0xa5,0x84,0x41,0xaa,0x8e,0xea,0x76,0x25,0xe9,0x1f,0xd1,0xf6,0x0b,0x98,
+  0x6d,0x28,0xce,0xc6,0xb0,0xd7,0x46,0x2b,0xdb,0x50,0x7f,0x0c,0xd0,0xd6,0x1c,0xf9,
+  0x61,0xa5,0xbc,0x43,0x79,0x1b,0xc5,0xc2,0x92,0xe5,0xeb,0x3b,0x31,0xff,0x90,0xd8,
+  0xf8,0x6b,0xbb,0xa1,0x9b,0x02,0xea,0x2f,0xa7,0x3a,0x56,0x68,0xe0,0xbd,0x9f,0x26,
+  0x29,0x03,0xd6,0x42,0x89,0x13,0x74,0xbf,0x9b,0xed,0x93,0x25,0xc3,0x33,0x13,0xdc,
+  0x95,0x4e,0xc3,0x3f,0xac,0xec,0xc4,0xf7,0x18,0x1e,0xd8,0x86,0xdd,0xf5,0x5f,0x3b,
+  0xc9,0x8d,0xf0,0xee,0xf5,0xe3,0x91,0x57,0xa5,0x91,0x07,0x2f,0x6a,0xe5,0x26,0xcc,
+  0x36,0xbc,0x53,0x2c,0x64,0x61,0xaf,0xdb,0x39,0xda,0x42,0x22,0x8e,0xb8,0xa6,0xb7,
+  0x8a,0x84,0x2a,0x5c,0x4c,0x84,0x01,0x84,0xfe,0x0c,0xfe,0x4a,0xd3,0x10,0xa7,0x9d,
+  0x3f,0x47,0xeb,0x90,0xed,0xf0,0x65,0xd2,0x82,0xd8,0x4a,0x51,0x8b,0x00,0x64,0xd5,
+  0xc5,0x0a,0x38,0xda,0x7a,0x34,0x5d,0x35,0xa4,0x46,0xc4,0x5f,0xd0,0xae,0x98,0x77,
+  0xb1,0x3a,0x05,0x10,0x19,0x23,0x42,0x3c,0x9c,0xc1,0x5f,0xa3,0x80,0x35,0x99,0x7b,
+  0x09,0xb3,0x3a,0xef,0x0b,0x2c,0x10,0x06,0x2d,0x0c,0xf0,0xc2,0x4e,0x34,0xcf,0x61,
+  0xcf,0xcb,0x4f,0x16,0xb3,0x88,0x18,0x61,0x8e,0xfd,0xf9,0x2c,0xfe,0x0d,0x8c,0x7f,
+  0x8d,0xd0,0x9a,0xf4,0xda,0x11,0xe9,0x3d,0xe5,0x28,0x8d,0x54,0x78,0x47,0xa5,0x8f,
+  0xc4,0xa3,0xf1,0xf2,0xd3,0x8b,0xfa,0x1b,0xfd,0x0c,0x9a,0x79,0x46,0xd5,0x08,0x39,
+  0x42,0x23,0x83,0xeb,0x4e,0x72,0xfd,0xaf,0xb4,0x3c,0xa4,0x56,0x19,0x17,0x00,0x88,
+  0x81,0x33,0xe9,0xca,0x3f,0xdc,0x99,0xde,0x82,0x99,0x18,0xaf,0xc6,0x1f,0x20,0x95,
+  0x7a,0xa0,0x45,0x3c,0x4b,0x1e,0x20,0x4f,0xf4,0xab,0xa6,0x58,0x04,0x2f,0x22,0xe4,
+  0x8d,0x8f,0x4f,0x26,0xab,0x92,0x95,0x43,0x0b,0x9a,0xe3,0x09,0xda,0xaa,0xdc,0xb8,
+  0x15,0x80,0x73,0x01,0xbc,0xe5,0xcb,0x11,0xcc,0xba,0xf2,0x0f,0x53,0x7a,0x39,0x93,
+  0x5f,0xa1,0xed,0x4c,0xbe,0x99,0x0c,0xc4,0x28,0x6c,0x76,0xb0,0x0f,0x4e,0xa6,0x5c,
+  0x02,0xdb,0x3f,0x59,0x7f,0x5c,0xaf,0x04,0x64,0xe7,0x81,0x17,0x32,0xd1,0xa3,0x0a,
+  0x76,0x3d,0x0d,0xab,0x73,0x63,0x16,0xff,0x61,0x8f,0x5e,0x81,0x49,0x1a,0x2f,0xc2,
+  0x63,0x1e,0x14,0xf3,0xb0,0x80,0x9d,0x15,0xa7,0x13,0x91,0xe8,0x3b,0x68,0xc5,0x70,
+  0x5e,0x9d,0xe8,0xe5,0x48,0x5c,0x8e,0x77,0xfa,0xa9,0x19,0x18,0x56,0x82,0xcc,0xcf,
+  0x0c,0xa4,0xc1,0xd5,0x77,0xe1,0xaf,0x91,0x68,0x18,0xb3,0xd7,0x30,0xec,0x15,0xd9,
+  0xc0,0xfc,0xb1,0xc3,0x4a,0xf7,0x80,0x2f,0x89,0xfc,0xc6,0x4a,0x24,0x0c,0xf3,0x5c,
+  0x4d,0xde,0x39,0x19,0x59,0x0c,0x28,0xa9,0x52,0x3f,0x3c,0x0f,0xdc,0xc2,0x67,0x3c,
+  0xb8,0xbf,0xef,0x49,0xe7,0xed,0x94,0x5c,0xfc,0x87,0x23,0xc6,0x6c,0x56,0x95,0x80,
+  0x65,0x5f,0x09,0x44,0x01,0xf4,0x83,0x28,0x5b,0x8b,0xd7,0xd1,0x8d,0x2f,0x2d,0x00,
+  0xc8,0x20,0xfe,0x15,0xb9,0x1f,0x0f,0x6c,0xd9,0x01,0x57,0x62,0x11,0x46,0x6a,0x46,
+  0xc8,0xd5,0x7d,0x05,0x3d,0xd9,0xf5,0x5f,0x35,0x07,0x83,0x98,0x8a,0x73,0x99,0x73,
+  0x6b,0x9c,0x24,0xc7,0xa0,0xc5,0x17,0x03,0xfc,0x75,0x1c,0xb6,0x3f,0x6f,0x48,0x0a,
+  0xea,0x57,0xe4,0x6a,0x73,0xd1,0x76,0xa9,0x4e,0x39,0xa6,0xd4,0x2c,0xf5,0xbe,0x24,
+  0xd5,0x11,0x58,0x2f,0x70,0x45,0xda,0xdc,0xfa,0xcb,0xe6,0x56,0xce,0x7f,0xb8,0xa7,
+  0xdf,0x3f,0xa4,0x62,0x21,0x58,0x87,0x09,0x38,0xe5,0x29,0x51,0xa4,0x9d,0xa4,0xca,
+  0x6f,0xf3,0x16,0x62,0x26,0x46,0x99,0xb2,0x26,0xe1,0x0f,0x05,0xe4,0x02,0x26,0xb6,
+  0x3b,0xac,0xec,0x13,0xd3,0x56,0xfc,0x4b,0x66,0xe2,0xbf,0xd6,0x75,0xa8,0x3f,0xf9,
+  0x03,0x74,0xc8,0xc1,0xe1,0x34,0x3b,0x7b,0xfc,0xcb,0xe8,0x0f,0x48,0x55,0x5a,0xb1,
+  0x09,0xed,0x55,0xad,0xc8,0x47,0xb6,0x2a,0xfa,0x0b,0x79,0xc9,0x78,0x90,0xa4,0x14,
+  0x78,0x8f,0xf5,0xc4,0xd3,0x82,0x8d,0xbf,0x60,0xdd,0x79,0x78,0x9a,0x76,0x89,0xba,
+  0xf7,0x3a,0x1e,0xff,0xaa,0xc0,0xbf,0xd2,0xf5,0x47,0x34,0x40,0x0a,0x33,0x1a,0x18,
+  0x5f,0x65,0x3f,0x38,0x9c,0x72,0x51,0x6b,0x61,0x52,0x84,0xbd,0x12,0xfe,0x4a,0xd9,
+  0x8a,0x75,0x49,0x07,0xf9,0xdd,0x43,0xf2,0x56,0xc0,0xa2,0x20,0xed,0x86,0x88,0xb7,
+  0x7a,0x37,0x65,0x85,0x60,0x87,0x11,0x5b,0x25,0xa5,0x15,0x14,0xcb,0x21,0x31,0x11,
+  0x11,0xcf,0xc3,0x8f,0x41,0x8b,0x4e,0x86,0xe0,0x45,0x04,0x9e,0x55,0xd0,0x18,0xd5,
+  0x99,0xb3,0x6d,0x4a,0x4e,0xfc,0x0b,0xbc,0x77,0x9c,0x5e,0xa6,0xff,0xe5,0x55,0x87,
+  0xb1,0xba,0x01,0x43,0x4f,0xe8,0x5d,0xbc,0x8f,0x1b,0xd9,0x07,0x9c,0x76,0xde,0x9c,
+  0x64,0xf2,0x02,0x2e,0x52,0x60,0x0a,0x17,0x0d,0x56,0x1c,0x91,0xc9,0x3f,0x94,0x39,
+  0xff,0xe1,0xa2,0x9e,0xe2,0xf7,0xe4,0x2b,0xa4,0xa0,0xdf,0x22,0x54,0xe4,0xc9,0x54,
+  0xed,0x57,0xca,0x6a,0xfa,0x8f,0x62,0xcb,0x85,0xf2,0x5a,0x3b,0xc4,0x16,0xe6,0xfc,
+  0x87,0x97,0xc1,0xed,0xca,0xd4,0x7f,0xd1,0x4c,0xfe,0xe1,0x7b,0xe4,0xc0,0x40,0xf5,
+  0x39,0x75,0x54,0xbc,0x82,0xfc,0xdd,0xc3,0x9d,0xe7,0xc4,0xcb,0xc6,0x81,0x8d,0x9f,
+  0x1d,0x7c,0x88,0xb5,0x24,0xaa,0x07,0x31,0xfe,0x65,0x20,0x3d,0x32,0xcb,0x48,0xdc,
+  0xc3,0x52,0x13,0x1b,0x6c,0xfd,0x2f,0xd9,0x7d,0x2e,0xc1,0xa5,0x82,0x5e,0xc4,0xcc,
+  0x4f,0x0c,0x7b,0x1d,0xcd,0xdb,0x41,0x62,0x6c,0x09,0x0c,0x3e,0xa6,0x08,0x35,0x3b,
+  0x02,0x3c,0xc3,0xad,0x8b,0x31,0xbf,0x8d,0xd3,0xff,0x1a,0xab,0x5d,0xd5,0x6b,0x01,
+  0xf0,0xe9,0x88,0xbf,0xdc,0x5d,0xc6,0xf4,0x98,0x7d,0x93,0xe8,0x4a,0x2a,0x3e,0x26,
+  0xff,0x70,0x9c,0x2e,0x03,0x0b,0x3c,0xc9,0x17,0x04,0x5c,0x4a,0x56,0x5d,0x65,0x95,
+  0x43,0x9e,0xd7,0xf6,0x58,0xfc,0x87,0x66,0x38,0xe0,0xdd,0x26,0x0d,0xb8,0xf8,0x37,
+  0x64,0x4b,0xf6,0x0b,0xa7,0x97,0x9d,0x6f,0xb8,0x14,0xc1,0xe6,0x66,0xa1,0x63,0xa4,
+  0xa6,0xbf,0xc9,0x60,0xfc,0x87,0x97,0xd1,0x63,0xfc,0x58,0xfd,0xaf,0x5e,0x1f,0xa7,
+  0x6d,0xb1,0x14,0xca,0x3e,0x74,0x55,0x0f,0xf1,0x23,0x8b,0x0f,0x48,0x77,0x29,0x1b,
+  0x03,0x77,0x9d,0x0e,0x2f,0xd8,0x8d,0x0e,0xfe,0xd2,0x9c,0xdf,0x7e,0x80,0xc7,0xbf,
+  0xf6,0x91,0x9f,0x93,0xea,0xde,0xbc,0x73,0x62,0x9d,0x72,0x40,0xae,0x1e,0x51,0x86,
+  0xed,0x4a,0x13,0x34,0x60,0x5a,0x5a,0x98,0xf4,0x43,0x77,0xd4,0x2f,0xa8,0xbb,0x27,
+  0xc8,0x3f,0x74,0x16,0xce,0x2b,0xb7,0x61,0xd8,0x6b,0x66,0x9c,0x75,0xf5,0x2b,0x59,
+  0xa1,0xb1,0x2e,0x9d,0xa6,0x19,0x71,0x4a,0x8a,0x02,0x82,0x0e,0x88,0x7b,0xb2,0xf5,
+  0xbf,0x78,0xaa,0x5b,0xa2,0xf2,0x2d,0x00,0x62,0x3f,0x62,0x11,0xb1,0x3c,0xae,0x54,
+  0x15,0x34,0x19,0x53,0x3a,0xcb,0x18,0x67,0x1c,0x89,0x9b,0xb6,0x0c,0xc1,0x17,0x9b,
+  0x42,0xf6,0x91,0xb2,0x90,0x3a,0x02,0x5f,0x8c,0x7d,0x1f,0x8b,0xff,0xb0,0xcf,0x37,
+  0x1b,0x53,0x0a,0x51,0xdb,0x6b,0x86,0xe4,0x25,0xcf,0x11,0x84,0xc9,0xd2,0x17,0xfa,
+  0x90,0xe4,0xd0,0x1b,0xc6,0xd0,0x58,0x12,0x65,0xbf,0x00,0x88,0x8d,0x16,0xb5,0xbc,
+  0xed,0xeb,0x82,0x31,0x23,0x5a,0x88,0xf8,0xb4,0xb6,0x0d,0xe3,0xf5,0xbf,0x8c,0x2b,
+  0x18,0xb0,0x1e,0xfe,0x1a,0x46,0xbb,0x22,0x03,0xf9,0xe7,0xe0,0x89,0xbb,0x22,0xd5,
+  0x9f,0x84,0xd7,0xe0,0x25,0xe3,0x4a,0x73,0x64,0xc0,0xf7,0x7b,0x58,0xa6,0x4b,0xda,
+  0x15,0x94,0x4a,0xbc,0x48,0x46,0xca,0x10,0x91,0x8d,0xd3,0xff,0x62,0x8b,0x92,0xa8,
+  0x3d,0xec,0xdb,0x55,0x7c,0xa6,0xe9,0xc2,0xf4,0x70,0x9f,0x6f,0xb7,0x1a,0xc4,0x82,
+  0x97,0xbe,0x02,0x56,0xf9,0xb2,0x01,0x5a,0xba,0x98,0x26,0x85,0xa5,0xe0,0x86,0x88,
+  0x2c,0x3f,0xe0,0xc6,0x5f,0xbf,0xcb,0xc4,0xbf,0xca,0x06,0xd4,0x7b,0xe2,0xa7,0x3a,
+  0x0e,0x18,0x79,0xfd,0xea,0x07,0xb8,0xef,0x84,0x2a,0x59,0xde,0x05,0xdd,0xa1,0x73,
+  0xba,0x27,0x73,0x07,0x29,0x37,0x58,0xc6,0xcb,0x4e,0xa1,0x12,0x8d,0x31,0xf1,0x2f,
+  0x4e,0xef,0xef,0x14,0x82,0x31,0x92,0x79,0x80,0x5d,0xdf,0x63,0xa1,0x31,0x03,0xc7,
+  0x30,0x7a,0x93,0x57,0x8d,0xef,0xd9,0xf5,0x5f,0x3b,0x3b,0x82,0xb1,0xbc,0xc5,0x6e,
+  0xfd,0xe5,0xc7,0xb2,0xcf,0x0f,0xf9,0xd9,0x20,0x8f,0x7f,0x59,0x29,0xc4,0x70,0x03,
+  0x88,0xb6,0x12,0x9c,0xa6,0xf3,0xba,0x09,0x54,0x04,0x53,0x66,0x36,0x8c,0x8b,0x7f,
+  0x89,0x96,0xec,0x97,0x9d,0x5b,0x88,0xd1,0x2e,0xe5,0xd7,0xa4,0x2e,0xab,0x65,0x48,
+  0xb8,0x4c,0xeb,0x93,0x2c,0x23,0xf1,0xb2,0x56,0x4f,0xf3,0x4f,0xab,0x73,0x6c,0xfc,
+  0x95,0x74,0x07,0xb9,0xea,0x6c,0x83,0x71,0x6b,0x30,0x44,0xa6,0x15,0xd0,0x49,0xd8,
+  0xb2,0x92,0xb5,0x08,0x23,0xca,0x94,0x12,0x3b,0x52,0x33,0xe3,0xe3,0xea,0xbf,0x6c,
+  0xf5,0xa8,0x2e,0x58,0x14,0x94,0x97,0x15,0x90,0xa6,0x20,0x3f,0x51,0xc3,0xa1,0xd9,
+  0x42,0x3e,0xa6,0x02,0xc6,0x60,0xbe,0x16,0xad,0x8b,0xe6,0x6f,0xce,0xe8,0x7f,0x65,
+  0xe9,0x76,0x55,0xd9,0xb5,0x5d,0x7e,0x24,0xe2,0xc0,0x20,0x45,0xed,0x9d,0xcc,0xa3,
+  0x7e,0xcb,0xdd,0xc5,0x33,0xca,0xbe,0x58,0xd5,0xac,0xfc,0xe8,0x63,0xf4,0xbf,0x9c,
+  0xda,0xae,0x69,0xc6,0x75,0x36,0xfd,0x78,0x5e,0x56,0x57,0x17,0xf9,0xa9,0xc9,0x8c,
+  0xbd,0x4a,0x15,0xa2,0xbf,0xb1,0xfa,0x5f,0xae,0xf8,0x57,0x1f,0xed,0x0a,0x55,0x44,
+  0xd5,0x1a,0x3f,0x18,0xfa,0x72,0xde,0xb2,0x45,0x5f,0xc1,0x8c,0x44,0x97,0x1e,0xb8,
+  0xdd,0xae,0x4b,0xea,0x57,0xb2,0xf8,0x0f,0x7b,0x32,0xf3,0x8c,0x87,0x06,0x28,0x04,
+  0x66,0xcc,0x22,0x0b,0xda,0xa5,0x24,0x76,0xd1,0x7c,0xea,0x8e,0x7f,0x8d,0x34,0xd7,
+  0x76,0x38,0xf5,0x3b,0x0b,0xb3,0xf5,0xbf,0x9c,0x79,0xd6,0x22,0x4d,0x2a,0x06,0xb9,
+  0x46,0x43,0xb5,0x4d,0xbe,0x47,0xc0,0xd8,0xad,0xd5,0x35,0x15,0x60,0xcb,0x5b,0xd0,
+  0xd5,0xb9,0x1e,0x89,0x61,0x8b,0x6a,0x6e,0xb7,0x78,0xe3,0xeb,0x9b,0x0a,0xb2,0xf8,
+  0xe7,0xc7,0x4a,0x56,0x59,0x0b,0xc7,0xb2,0x16,0xc9,0xdc,0x0c,0xbf,0x3a,0xeb,0x42,
+  0xfc,0xc5,0xd6,0xeb,0xf7,0xa4,0x1e,0x76,0x15,0xe9,0x85,0x0c,0xfe,0x1a,0xca,0xc4,
+  0xbf,0xaa,0xc8,0x02,0x30,0x4a,0x86,0x48,0x01,0x43,0x5b,0x88,0xbf,0x84,0x7c,0x4a,
+  0xf0,0xb7,0xd7,0xf2,0x31,0x27,0x19,0xfe,0xb2,0x22,0x62,0xca,0x38,0xfe,0x43,0x17,
+  0xa5,0xe1,0x1d,0x7d,0x72,0x97,0xec,0x65,0x40,0x4c,0xee,0x22,0x2b,0xb2,0x65,0xbf,
+  0xe4,0x56,0xb2,0xdc,0xa9,0xff,0x8a,0x45,0x27,0xa8,0xff,0xca,0x75,0xe9,0x7f,0x21,
+  0xcb,0x8a,0x8d,0xe8,0x71,0xdd,0x31,0xc7,0x75,0xfa,0x3c,0x26,0x1b,0xb7,0x9e,0x0b,
+  0x79,0x43,0x97,0x09,0x77,0xc2,0x46,0x77,0xfd,0x97,0xfd,0xdb,0xb5,0x51,0x77,0xb8,
+  0xca,0x29,0x5a,0xcc,0x4f,0x4c,0x73,0xe7,0x28,0x92,0x3d,0x2d,0xbc,0xfe,0xcb,0xa8,
+  0x6b,0x59,0xbb,0xc9,0xcd,0x7f,0x38,0x5e,0xdb,0xeb,0x2d,0x57,0x91,0x17,0x52,0x50,
+  0x2e,0xb3,0x43,0x90,0x7d,0x24,0xa3,0xe9,0x46,0x18,0x46,0x9b,0x28,0xfe,0x65,0xcb,
+  0x56,0x0a,0x2c,0x36,0xda,0x6a,0xdd,0x24,0xd6,0xfd,0x83,0x81,0x54,0xcc,0x3f,0xa4,
+  0xdd,0x8e,0x46,0x98,0xe8,0xed,0xc8,0xaa,0xff,0x22,0x4e,0xfc,0xcb,0x4f,0x17,0x80,
+  0x91,0xc3,0x5a,0xd2,0xac,0xa5,0x32,0xe1,0xe3,0x5d,0xd3,0x61,0x4c,0x51,0x40,0x7c,
+  0xb8,0xb5,0x86,0xe5,0x28,0x92,0xfd,0x5f,0x2c,0x4f,0x4e,0x54,0xff,0xc5,0xfc,0x8d,
+  0x0a,0x3b,0x5b,0x83,0xf9,0xe1,0x6c,0x47,0x2b,0xb5,0xe4,0x9f,0x96,0xa1,0x5a,0x25,
+  0xe6,0x1f,0x4e,0x7b,0xdd,0xda,0xd1,0xf4,0x74,0x40,0x98,0x80,0x7f,0x83,0xcb,0x7e,
+  0xa9,0x2d,0x45,0x9c,0x85,0x0f,0x70,0x01,0x0b,0xd0,0x88,0x3c,0xda,0x45,0x2b,0x91,
+  0xc7,0x03,0x80,0x86,0x52,0x36,0xc0,0xde,0xcf,0x07,0x3a,0xf4,0x83,0x00,0x10,0xc6,
+  0xd4,0x7f,0xd9,0x41,0x2e,0x6e,0xec,0x32,0x6f,0x49,0xfb,0xa2,0x3c,0x22,0x06,0x88,
+  0x8c,0x49,0x83,0xb1,0x2e,0x64,0x44,0xbc,0x19,0x69,0xe7,0x79,0xfc,0x2b,0x18,0x9d,
+  0x48,0xff,0x4b,0xc1,0x04,0x78,0x5f,0xea,0x6b,0xd6,0x4e,0x84,0xfc,0x1b,0xdf,0x72,
+  0xa8,0xce,0xc1,0x6f,0x99,0xc4,0x53,0xe2,0xef,0xb7,0x36,0x29,0x61,0x3f,0x5d,0x44,
+  0xb3,0xf2,0x0f,0x9d,0xfa,0xaf,0x44,0x3d,0xe6,0x1f,0x02,0x9e,0xa6,0x73,0xd2,0x05,
+  0xfd,0xd2,0x7e,0xf2,0x0e,0x9d,0x9b,0xcc,0xff,0x40,0xba,0x1f,0x19,0x39,0x70,0x4c,
+  0x84,0xf4,0x24,0x6a,0x62,0x0e,0x3f,0xb6,0xf7,0x90,0x5d,0x7f,0xc1,0xf8,0x0f,0x93,
+  0xf9,0x6c,0x7e,0xb4,0x5d,0xe1,0xca,0x33,0x6b,0x5a,0xc4,0xcd,0xc6,0xe7,0x60,0x97,
+  0xf1,0x00,0x38,0x32,0x56,0xd1,0x4a,0xe2,0x59,0x89,0xf1,0x2f,0x52,0x99,0xf6,0xdd,
+  0x23,0xdd,0x45,0x76,0xa2,0x74,0x1a,0xe7,0xf0,0xaf,0xec,0x87,0xf9,0x71,0xeb,0x7f,
+  0x39,0xf3,0x2c,0x54,0xf6,0xe1,0x2e,0xd3,0x8c,0x41,0xc9,0x6b,0x0d,0x58,0x94,0x5d,
+  0x62,0x25,0xc9,0xc3,0x0d,0x08,0x03,0x6a,0xb7,0x21,0xf3,0xe4,0x4e,0x7f,0x19,0xdf,
+  0x07,0x77,0x69,0x95,0x03,0x4a,0x53,0x7c,0x7c,0xfe,0xa1,0x6d,0xb0,0xf8,0x17,0x78,
+  0xf8,0x44,0x64,0x94,0xce,0x84,0x51,0x62,0x5a,0x7b,0xdc,0x42,0x3c,0xde,0x4f,0x70,
+  0x3f,0xb3,0x3d,0xd8,0xae,0x28,0x62,0xbf,0x85,0xbf,0x4a,0xc6,0xc4,0xbf,0x30,0xda,
+  0x25,0x1e,0x67,0x05,0x77,0x12,0xb8,0x85,0x42,0x1d,0x79,0x08,0xbd,0x26,0xcb,0x43,
+  0x63,0xf9,0x48,0xcd,0xbc,0xfe,0x2b,0x1a,0x49,0x07,0x03,0xd2,0xdb,0xd9,0xf5,0x5f,
+  0xd7,0xdb,0xd7,0x79,0x18,0xab,0x48,0x58,0xfe,0x61,0x88,0x1b,0x82,0xc5,0xab,0x66,
+  0x49,0x88,0x8e,0xd8,0x2b,0x78,0x5e,0x8f,0x98,0xd5,0xc9,0x0c,0xfe,0xda,0x67,0xe9,
+  0x7f,0xb1,0xb0,0x17,0xfa,0x2d,0xc5,0x96,0x57,0x99,0x80,0x59,0xfd,0x15,0x29,0xaf,
+  0x60,0xfc,0x87,0x00,0xc4,0xcc,0xb5,0xcc,0xe1,0x8c,0x87,0x1b,0x2c,0xcf,0x33,0x84,
+  0xfc,0x1b,0xc4,0x85,0xbf,0x1c,0xdf,0xd8,0x2a,0x04,0x13,0x30,0xcb,0xcb,0xb7,0x96,
+  0x30,0xda,0xc3,0xd9,0xf9,0x58,0x11,0xf6,0x1b,0x4b,0xc0,0x8b,0xa4,0xd2,0xe1,0x18,
+  0x1b,0xdc,0x4d,0xfc,0x9a,0xb2,0x39,0xae,0x4f,0x18,0xff,0xb2,0xb5,0xbd,0x58,0xfe,
+  0x21,0x0b,0xb1,0x4d,0x27,0xd3,0xed,0x8c,0x44,0x4e,0x71,0xaf,0x4d,0x8f,0xd9,0x71,
+  0xb4,0x17,0x3c,0xdb,0x5d,0xf1,0x2f,0xc6,0xad,0xe1,0x5a,0xaf,0x5c,0xfe,0x9c,0xe2,
+  0x32,0x19,0x6d,0x4a,0x80,0xa8,0xa8,0xff,0xf5,0x88,0xe6,0x3d,0xca,0x0e,0x4c,0x7a,
+  0xf4,0x80,0xc1,0x06,0x87,0xa8,0x6e,0x06,0x92,0x8e,0xfe,0x17,0xe6,0x1f,0xae,0x84,
+  0x5f,0xf1,0x34,0x97,0x5b,0x3a,0xc5,0x0b,0x24,0x15,0x16,0xe9,0xfb,0x06,0xc0,0xae,
+  0x5a,0x52,0xd0,0x0d,0xb8,0xf2,0x88,0x11,0x39,0xcc,0xdc,0xb0,0x61,0xbd,0xd6,0x7e,
+  0x52,0xc2,0x38,0xf3,0x86,0x2b,0xfe,0xc5,0x7c,0x75,0x01,0x83,0x53,0xa8,0xff,0x25,
+  0x5c,0xc4,0xe2,0x91,0x3e,0x16,0x34,0xc1,0xb4,0x43,0xb8,0x13,0x90,0xff,0x30,0xc2,
+  0x70,0x93,0x7c,0x51,0xab,0x11,0xdd,0xf5,0x5f,0xae,0xf8,0xd7,0x08,0xa9,0x11,0xf2,
+  0x91,0xd2,0xf0,0x14,0x62,0xbd,0x01,0x29,0x05,0xf7,0x02,0x66,0x2d,0xaa,0x15,0xf0,
+  0x58,0xcd,0x21,0x0b,0xcd,0xf2,0x16,0x72,0xa4,0x3d,0x02,0xf0,0x8d,0x9d,0x6f,0x44,
+  0xd2,0x93,0xf0,0xf9,0xc2,0xf8,0x17,0x5d,0x29,0xb9,0xf2,0x0f,0x77,0x8b,0x7e,0x5e,
+  0xff,0xf5,0x04,0x1e,0x09,0x6e,0x42,0x32,0x49,0xfe,0x86,0x94,0x31,0xbc,0xa8,0xa3,
+  0xd4,0x14,0xe6,0x28,0x26,0x03,0x94,0xe9,0x7f,0x55,0xa5,0x17,0x70,0x8d,0x66,0xff,
+  0x69,0x25,0x2b,0xff,0x10,0x23,0x86,0xf0,0x58,0xf5,0x6b,0x78,0x48,0x18,0xd5,0x8a,
+  0x3a,0xe4,0x38,0xea,0x61,0x03,0xaa,0x25,0x6d,0x22,0xcb,0xd4,0x55,0x3c,0x6d,0x24,
+  0x28,0xcc,0xd6,0x44,0x3b,0x1f,0xdb,0x7f,0x94,0xc7,0xbf,0x92,0xee,0xfc,0xc3,0x2e,
+  0x4c,0x71,0x44,0xde,0x95,0x27,0x62,0x22,0x85,0x7f,0xa2,0x4a,0x5f,0x43,0xab,0xda,
+  0xaf,0xdb,0x4e,0x2a,0xe4,0x4e,0xd1,0x4f,0x3d,0x81,0x5c,0xd2,0xbc,0x17,0x15,0x99,
+  0x93,0x62,0x50,0xb3,0xeb,0x9b,0xe4,0x9e,0x52,0x7f,0x19,0xdc,0x09,0x21,0x57,0xfc,
+  0xcb,0x0c,0x7f,0x80,0x94,0x74,0xb4,0xdf,0xe8,0x0e,0x04,0xb7,0x4b,0x8f,0x91,0x77,
+  0xfa,0x23,0x2d,0xbe,0x7d,0x35,0xd3,0x94,0x23,0xa4,0xb6,0xa9,0x60,0x8d,0x34,0x2d,
+  0xc1,0x18,0x6f,0x9e,0x52,0x83,0x19,0xb2,0x71,0xf8,0xab,0x61,0xef,0xb6,0x72,0x39,
+  0x83,0xbf,0x46,0x6c,0x6c,0xf5,0x7b,0x32,0x57,0xae,0x6e,0x51,0x2f,0xe6,0x5e,0xc6,
+  0x24,0xc3,0x16,0xe9,0xf7,0xe2,0x95,0xfc,0xfd,0x7a,0x7e,0xfa,0x07,0x3f,0x61,0x0a,
+  0x53,0xf9,0xa7,0xda,0x2e,0x02,0x54,0xe5,0xf5,0x5f,0x4c,0x9a,0xd9,0x77,0x2e,0x2b,
+  0xfe,0x65,0x76,0x0f,0x30,0xd8,0x7e,0x48,0x0b,0x1b,0x8b,0x92,0xea,0x13,0xe4,0xc2,
+  0xbc,0x7b,0x4a,0xaa,0x76,0xe2,0xbf,0x2e,0x46,0xb0,0x9e,0x28,0x70,0xf0,0x08,0xee,
+  0x8c,0x37,0x61,0x45,0x21,0xfb,0x3e,0x88,0x10,0x1b,0xc2,0xda,0xba,0x6d,0x5f,0x73,
+  0xc7,0xbf,0xee,0xc4,0x90,0xf1,0xd5,0xef,0x1a,0xab,0xe3,0xfe,0x7d,0x9d,0xa9,0xf2,
+  0xff,0x4b,0xd9,0xb3,0x61,0x56,0xbb,0xb2,0x1d,0xeb,0x22,0xfb,0x83,0x54,0xd9,0x27,
+  0x95,0xe1,0x32,0xcd,0x54,0x53,0x0b,0xfe,0xc1,0xe8,0x6c,0x40,0x31,0x3e,0x06,0x5d,
+  0xfd,0xba,0x1a,0x76,0xf3,0x6f,0xa4,0x78,0xf8,0x3e,0x4d,0xe2,0xc9,0x40,0xf2,0x3a,
+  0xcd,0xb3,0x95,0xa6,0xcc,0x0a,0xa2,0xe6,0xc1,0x6d,0xdc,0x69,0x06,0x09,0xc9,0x13,
+  0x45,0x7c,0x8f,0x19,0xaa,0x17,0xae,0xdc,0xe6,0x3c,0x44,0xba,0xbe,0x0c,0x3c,0x10,
+  0x57,0xfc,0xeb,0xe9,0x44,0x19,0xe6,0xc5,0xfd,0xb2,0xac,0x95,0xde,0x18,0xeb,0x2c,
+  0xf5,0xdc,0xa1,0xef,0xfc,0xae,0x5e,0x91,0x17,0x15,0x7f,0x44,0xe1,0xfd,0x1c,0x52,
+  0xa2,0xe2,0xb5,0xf3,0x00,0x91,0x6d,0x57,0x6f,0x13,0xbf,0x8a,0x19,0x89,0x1c,0x88,
+  0xed,0x48,0x95,0x2d,0x51,0xef,0x2a,0x72,0xe5,0x1f,0x0e,0xa7,0x75,0xd3,0x37,0x43,
+  0x7c,0x9d,0x1e,0x24,0x3d,0x43,0x8b,0xc2,0x8d,0x94,0x8e,0x28,0xdb,0x4e,0xac,0x6b,
+  0x97,0x1e,0xd6,0x9f,0xd3,0x82,0x46,0x30,0xa1,0x7a,0x8d,0xdf,0xd2,0xba,0xbf,0xf1,
+  0x25,0x05,0x06,0xcd,0x10,0xa3,0x01,0x22,0x4b,0x84,0x34,0xdf,0xcc,0x72,0x37,0xff,
+  0x86,0x7c,0x3d,0x16,0x79,0x0d,0x1b,0x17,0xc9,0xcd,0x60,0xa8,0xe7,0xf0,0xa0,0xa3,
+  0x6f,0xa1,0xc9,0x1e,0xab,0x6a,0xf4,0x1c,0x2e,0xce,0x7f,0x0d,0x7d,0x89,0x34,0xe7,
+  0x20,0xb5,0x2a,0xc2,0x4a,0xea,0xc9,0xa2,0xe1,0x6c,0xfd,0xaf,0x30,0x96,0x7d,0xa1,
+  0xa8,0x7a,0x98,0x82,0x2f,0xb1,0xb4,0xe4,0x50,0x7b,0xb7,0xf1,0x05,0x0a,0xce,0xc9,
+  0x05,0x31,0x12,0xf3,0x52,0x5f,0x05,0x39,0x22,0x30,0xfd,0xaf,0xa0,0xcc,0x73,0x4a,
+  0xd9,0x0b,0x16,0x81,0x98,0xe8,0xd2,0x5f,0x7e,0x9a,0x94,0xf5,0x06,0x5a,0x18,0xdd,
+  0x53,0x00,0x7c,0xb6,0xa2,0x10,0x16,0x82,0x19,0x4a,0xb3,0x78,0x42,0xd9,0x25,0x04,
+  0x89,0x82,0xe5,0x99,0xb0,0x7f,0x51,0x98,0xd5,0xcd,0xf2,0xae,0x4c,0xfe,0x61,0x99,
+  0x11,0x6d,0x11,0x5d,0xfa,0xcb,0x3b,0x69,0xf2,0x34,0x0b,0x7b,0x3d,0x82,0x20,0x6b,
+  0x79,0xd1,0x1d,0xf2,0xc6,0x76,0xc0,0x5f,0x51,0xf1,0x35,0x06,0xcd,0x60,0x9e,0xa7,
+  0x28,0xdf,0x8b,0x33,0xfe,0x43,0x44,0xbe,0xdf,0xb0,0xc0,0x9a,0xb9,0x4c,0xdf,0x34,
+  0x46,0x7f,0x39,0x79,0x14,0xb6,0xa4,0x5e,0xfa,0x48,0xf3,0x74,0x33,0x6f,0x6e,0x7c,
+  0x9e,0x9c,0x38,0x1c,0x3b,0x98,0x27,0xc7,0xd9,0x1b,0x72,0x67,0x80,0x34,0x78,0x43,
+  0x60,0xcc,0xb6,0x85,0x54,0xac,0x75,0x37,0x63,0xa4,0x74,0x4e,0x96,0xfe,0x17,0xa9,
+  0x49,0x79,0x93,0xd2,0x28,0x79,0x95,0xd6,0xd0,0xfc,0x33,0xea,0x37,0x73,0x5f,0x4d,
+  0xd7,0x24,0xaa,0xdf,0x44,0x46,0x29,0x52,0xdd,0xee,0x7d,0x63,0xd2,0x6c,0xf2,0x6b,
+  0xa1,0x3e,0xe9,0x1b,0x74,0x6b,0x34,0x5f,0x36,0x77,0x51,0x6f,0x5a,0x3a,0xcf,0x79,
+  0xc3,0x58,0xfc,0x8b,0x46,0x04,0xe6,0xd7,0xa5,0xa3,0xf0,0xb2,0x22,0x6a,0x52,0x1f,
+  0x12,0x2c,0x21,0xe6,0x11,0x46,0x90,0x3e,0x89,0x0a,0x43,0xa4,0x4e,0xf6,0xb5,0xaf,
+  0x72,0x67,0x24,0xea,0x11,0xfd,0x1f,0xb2,0xe3,0x5f,0xf4,0x03,0x63,0x5d,0x62,0xd2,
+  0x9b,0xc2,0x21,0x58,0x82,0x85,0x09,0x1f,0x0a,0x81,0xd5,0x19,0xf9,0x93,0xb1,0xda,
+  0x2b,0x51,0x1b,0xf3,0xad,0x97,0xa6,0x29,0x87,0xc0,0xab,0xf4,0x96,0x20,0xff,0x86,
+  0x6e,0xf3,0xcf,0x1b,0x21,0xf4,0x69,0x0f,0xba,0xe2,0x5f,0x64,0xab,0xb1,0x00,0xfc,
+  0x67,0x56,0xbf,0x13,0x40,0xef,0x74,0x37,0x8a,0x41,0x30,0x45,0x27,0x5a,0xfb,0x4f,
+  0x6a,0x22,0xbe,0x8d,0xac,0x16,0xaa,0x62,0x81,0x8d,0x5b,0xa7,0x8a,0x8c,0xdb,0xd0,
+  0x02,0x62,0xf3,0xc0,0x7f,0x76,0xe1,0xaf,0x2e,0x9d,0x75,0xf5,0xcd,0x5b,0x4d,0xa6,
+  0x81,0x8f,0xed,0xa9,0xc8,0xd9,0x6d,0x4c,0x6f,0x66,0x59,0x67,0xf0,0xe7,0x28,0xf5,
+  0x5b,0xd1,0x06,0x06,0x56,0xad,0xe6,0x18,0xad,0x86,0x95,0xd9,0xd8,0x85,0x80,0x6e,
+  0xfd,0x41,0x37,0xfe,0xd2,0x78,0xaa,0x1b,0xf2,0x1f,0x36,0x29,0x5a,0x41,0xae,0xd1,
+  0xa5,0x05,0x9a,0x02,0x85,0x9e,0xdc,0xc6,0x36,0x26,0xfb,0x25,0xb6,0x37,0xb6,0x62,
+  0x01,0x45,0x51,0x5c,0x26,0xad,0xd6,0x60,0x78,0x4e,0x93,0x0b,0xb2,0xf1,0xd7,0xf0,
+  0x72,0xbf,0xc7,0x47,0x8b,0x7a,0x93,0x6b,0x96,0xcf,0xba,0x76,0x61,0x7c,0x4d,0xd9,
+  0xb6,0x91,0xe5,0xb5,0xd7,0xe6,0x3f,0xd8,0x56,0x96,0xec,0xbf,0xe3,0x7e,0x8f,0xef,
+  0x01,0xa9,0x2c,0x19,0x25,0x11,0xcf,0xc2,0xb8,0xaa,0x6b,0xfd,0x8e,0xfe,0x17,0xc6,
+  0xbf,0x68,0x79,0x06,0x7f,0x91,0x2b,0x15,0xf5,0x86,0x84,0xfc,0x87,0x57,0x98,0xec,
+  0x17,0xa6,0x01,0xe8,0x73,0xa2,0x05,0x8c,0x08,0x91,0x5c,0x67,0xf8,0x5e,0x2a,0x3f,
+  0x47,0x77,0xb3,0x8a,0xb0,0x47,0x06,0x93,0xa3,0xba,0xe5,0xf3,0x5f,0x29,0xb9,0xde,
+  0xa8,0xce,0xe0,0x2f,0x61,0xd0,0x26,0x39,0x3c,0x67,0x61,0x2b,0xe9,0x5c,0xee,0x8b,
+  0x72,0x8d,0x51,0x30,0xc0,0x5a,0xb0,0x7c,0x4c,0x98,0x49,0xf2,0xb0,0xfe,0x6b,0x18,
+  0x2b,0xc2,0x88,0x68,0xe5,0x31,0xc2,0x60,0x5f,0x73,0x36,0xff,0x86,0x3f,0xc3,0x3f,
+  0xaf,0x20,0xff,0xe1,0xaf,0x09,0x53,0x04,0xc3,0x96,0x02,0x87,0x76,0x03,0x5b,0x92,
+  0x22,0xb5,0xf9,0xe7,0x53,0x30,0xf8,0xc8,0x18,0xfc,0xb5,0x2d,0x53,0xff,0xb5,0x38,
+  0x81,0x46,0x8e,0xce,0x22,0x62,0x8c,0x6d,0x03,0xba,0x64,0x0d,0x8d,0xa8,0x56,0x25,
+  0xbb,0x6b,0xc4,0xf4,0xb4,0x5a,0xda,0xe0,0xc2,0x5f,0x5d,0x94,0xdf,0x12,0x21,0xb8,
+  0x7f,0x1a,0x90,0x7f,0x83,0xae,0x26,0x7a,0x94,0x6c,0xcc,0x54,0x14,0x56,0x50,0xc6,
+  0xa8,0x59,0x08,0x48,0xbc,0x35,0x93,0x89,0x0a,0xc6,0xa6,0x2c,0xfc,0x65,0x32,0x4a,
+  0xc3,0x37,0x1b,0x0e,0x19,0xdd,0x2d,0xc1,0x4d,0xea,0x20,0x59,0x6d,0x84,0x17,0xe7,
+  0xe2,0x24,0xac,0x46,0x72,0x8c,0x1f,0x76,0x56,0xc4,0xe1,0x7e,0x8e,0x29,0xdf,0xb7,
+  0xa8,0xfb,0xf9,0xfd,0x6c,0x76,0x37,0x4f,0xc8,0x3f,0xff,0x82,0xc8,0xb0,0xd5,0x06,
+  0xb5,0x8f,0x9c,0xdd,0xc4,0x23,0x62,0xfe,0x51,0x94,0x69,0xd3,0xa4,0x37,0x75,0x7c,
+  0x52,0x16,0x6d,0x6a,0x73,0x83,0xe2,0x1b,0x23,0xcb,0x16,0x8d,0xe1,0xdf,0x60,0x49,
+  0xaa,0xa7,0xe9,0x10,0xbc,0x3d,0xe0,0x7d,0x58,0x46,0x47,0x8c,0x6e,0xcd,0x0b,0x68,
+  0x4b,0x3c,0x09,0xfe,0x8f,0x17,0x65,0xe3,0xfa,0x49,0x44,0xc9,0x6f,0x57,0xf5,0x78,
+  0x3f,0xb1,0x33,0x5a,0x0d,0x8c,0x88,0x49,0x6e,0xfd,0xaf,0x56,0x16,0x9d,0x3c,0xaf,
+  0x3f,0x1c,0xbd,0x39,0x11,0xd5,0xc5,0xd9,0xfa,0x7e,0xbd,0x3c,0x01,0xfb,0xd7,0x6c,
+  0xf2,0xb0,0x0c,0x20,0x6b,0x68,0xc3,0x1c,0xf2,0x53,0x52,0x4d,0x37,0xbd,0x27,0xce,
+  0x21,0x0f,0xb7,0xdb,0xf9,0x87,0xd4,0x4f,0x3b,0xd2,0x1e,0xb7,0xfe,0x17,0x78,0x68,
+  0xd7,0xb1,0x38,0x88,0xa1,0x87,0x14,0x24,0xf5,0x4a,0x99,0xfa,0x88,0x07,0x35,0xb9,
+  0x28,0xa9,0xd0,0xa3,0xb3,0x3d,0xcc,0xcd,0x28,0x53,0x66,0x82,0x1b,0xd2,0x96,0xb4,
+  0x75,0x0c,0x4d,0xbd,0x57,0x99,0x2c,0x66,0xf4,0xbf,0xc8,0x0e,0x65,0x8b,0x79,0x1d,
+  0xbe,0x9f,0x5b,0xc9,0xd4,0xe6,0xbc,0x16,0x8f,0x06,0xf7,0xc6,0x92,0x01,0xcf,0xca,
+  0xb8,0x40,0xda,0xe9,0x8f,0xb7,0x2a,0xba,0xa8,0xe9,0x8f,0x93,0x60,0x33,0xfc,0x13,
+  0x8b,0xf5,0x55,0xca,0x12,0x0b,0x44,0x28,0xc9,0x74,0xe0,0x94,0x5b,0xff,0xeb,0x0f,
+  0x3c,0x92,0x75,0x99,0xf4,0xd1,0x90,0x1e,0x9c,0x2d,0x15,0x91,0x73,0xb4,0x26,0x59,
+  0x35,0x22,0x4d,0x21,0xa7,0xe8,0x4c,0xdd,0xbb,0x18,0xdc,0xb0,0xcf,0x01,0x10,0xab,
+  0x5c,0xac,0xde,0x4f,0x5e,0xb0,0xf5,0xbf,0x58,0xfe,0xe1,0x62,0xb7,0xfe,0x97,0x55,
+  0x8a,0x8e,0xf1,0x40,0xf4,0xde,0x05,0xb6,0x28,0x94,0x89,0xbb,0xe1,0x12,0xfc,0x1c,
+  0x9d,0xf6,0x6f,0xa1,0x54,0x7d,0x42,0xda,0x6e,0x87,0xbd,0xce,0x28,0xcc,0x48,0x94,
+  0x8f,0xd7,0xff,0xba,0x4c,0x2e,0xd2,0x1a,0x1d,0x1c,0xc5,0x59,0x48,0x84,0x88,0xdc,
+  0x86,0x1f,0x18,0xa3,0x89,0x7a,0x3d,0xd8,0x5f,0x7e,0x99,0x1c,0x6f,0xad,0x4f,0xae,
+  0xc3,0xae,0x51,0x9e,0x7f,0xf8,0x9e,0x71,0x19,0x8d,0x93,0x59,0xfc,0xf3,0x06,0x83,
+  0x54,0xaf,0x18,0x4f,0x37,0xdd,0xb8,0x54,0xb9,0x5b,0x4c,0x60,0xa0,0xb0,0x1d,0x5a,
+  0x06,0xcc,0x07,0x00,0x96,0xc2,0xbe,0xf3,0x1f,0xe4,0x71,0xa1,0x72,0x44,0x1d,0x16,
+  0x35,0xb2,0x2f,0x01,0x18,0xf6,0x6e,0xd8,0x77,0x9e,0xa1,0x65,0x7d,0xea,0x3c,0x37,
+  0xfe,0x7a,0xda,0x28,0x3b,0xe8,0xb1,0x78,0x26,0x15,0x25,0xe4,0xb9,0x53,0x87,0xeb,
+  0x60,0x56,0xe7,0x09,0x6d,0x9b,0x5e,0xa9,0xa1,0x81,0xf8,0xeb,0x2f,0xf3,0x9a,0xc5,
+  0x12,0xe3,0x69,0x2b,0xcf,0x93,0x76,0xc1,0x5a,0xa8,0xcd,0xf1,0xbe,0x0c,0xfe,0xea,
+  0xc2,0x48,0x4d,0xa8,0xe8,0x39,0xba,0x3b,0x31,0x9d,0x28,0x61,0xf1,0x79,0x92,0x32,
+  0x82,0x49,0xa5,0x54,0xec,0x13,0x28,0x46,0xd6,0x64,0xf1,0x4d,0xc6,0xdf,0x0b,0x7e,
+  0x0b,0xbc,0xf8,0xec,0x33,0xc6,0x1e,0x92,0xec,0xbd,0x4e,0x71,0xeb,0x2f,0x9f,0x27,
+  0xdd,0xa7,0x0b,0x30,0x6e,0x75,0x9e,0x51,0x16,0xab,0x5f,0x27,0x17,0x34,0xc0,0x56,
+  0x07,0x60,0x93,0x7a,0x5b,0x88,0x34,0x3f,0x05,0x5e,0x2e,0x05,0x37,0x2c,0xa4,0x6e,
+  0xe9,0xb4,0xf3,0x0f,0xcb,0x79,0x56,0x8c,0xaf,0x24,0x0b,0x7f,0x35,0xb3,0xb4,0xc3,
+  0x37,0xc8,0xf9,0x86,0x48,0x47,0x41,0xa8,0xfc,0x09,0x85,0x2b,0xb8,0x95,0x9f,0x26,
+  0xef,0x88,0xe0,0xce,0xb5,0x4a,0x69,0x01,0xdc,0x03,0xd8,0x90,0xe0,0xca,0x0e,0xe8,
+  0x63,0x0f,0xda,0xbf,0xd8,0xf9,0x87,0x18,0xff,0x3a,0x4f,0xc2,0x07,0xd7,0x21,0xfe,
+  0x7a,0x5b,0xf1,0xd3,0x85,0xc3,0x52,0xa9,0x7e,0x5c,0xb8,0x3f,0x95,0x8f,0x11,0xb1,
+  0x63,0xb0,0x0f,0x7a,0xfb,0x56,0x9d,0x21,0xc7,0xc5,0xb9,0xc4,0xdb,0x2f,0xcd,0x2d,
+  0x3d,0x9a,0xb4,0xf2,0x0f,0xaf,0x68,0x33,0xfa,0xbc,0x2f,0x65,0xe9,0x2f,0x9f,0x60,
+  0x2a,0xc9,0x83,0x64,0x8d,0xe9,0x4f,0x82,0x4b,0x3c,0x9d,0x76,0x9a,0xf7,0xeb,0xde,
+  0xf5,0xe2,0xef,0x62,0xdb,0x3b,0xaa,0x8a,0x94,0xf6,0x49,0xa7,0x3d,0x9d,0x28,0xec,
+  0xbb,0xf9,0xda,0x72,0xa5,0x83,0x72,0xfe,0x43,0x65,0x0f,0xee,0x3b,0x1b,0xdc,0xfa,
+  0x5f,0xdd,0xbc,0xd8,0xa7,0x1f,0x75,0x78,0x87,0x3b,0x52,0x9e,0xe9,0xf2,0x9a,0x83,
+  0x41,0xcc,0xa3,0xee,0x57,0xc0,0x21,0xa7,0xd1,0x76,0x78,0x2a,0xe1,0x3a,0x72,0xc7,
+  0x96,0x78,0x0e,0x23,0xb4,0x57,0x31,0xb2,0xd6,0x83,0x79,0x71,0x19,0xfd,0x65,0xc0,
+  0x5f,0x35,0x32,0x5b,0x82,0x43,0x18,0xa6,0x34,0x4a,0x43,0x05,0x2c,0x89,0x8e,0x28,
+  0x21,0xbf,0x29,0x3c,0xa6,0xac,0x40,0xe0,0xdc,0x81,0xcf,0x69,0xa2,0x14,0xd3,0xe1,
+  0xe2,0x7a,0xe0,0x25,0x96,0x7f,0x98,0x08,0x25,0xcd,0xd9,0xba,0x5b,0xff,0x6b,0x44,
+  0xc3,0x25,0x10,0x4f,0x8b,0x6b,0xc8,0x9e,0xf6,0x60,0xaa,0x38,0x20,0x1e,0x86,0xd7,
+  0x29,0x80,0xe2,0xb7,0x94,0xc3,0x3a,0x92,0xfc,0xf8,0xd3,0xe4,0x48,0x73,0xa4,0x14,
+  0x7c,0x12,0x5d,0x3c,0x24,0xd7,0xa2,0xb3,0xfd,0x14,0x19,0x8d,0x76,0x9b,0xde,0xac,
+  0xfc,0x43,0x44,0x52,0x12,0xd6,0x7f,0xd5,0x91,0x59,0x32,0x4b,0x8b,0xc2,0xda,0x2e,
+  0xd8,0x77,0x86,0x93,0x17,0xc9,0xf5,0xc4,0xd7,0x5a,0x8c,0x8c,0x88,0x91,0x52,0x16,
+  0x11,0xbb,0xa8,0xcd,0x61,0x40,0x0c,0x8b,0xce,0x4c,0xd8,0xbf,0x26,0xd0,0xff,0x22,
+  0x17,0xf5,0x88,0xc2,0x54,0x72,0x18,0x7b,0xf0,0x41,0x56,0x59,0x36,0x07,0x33,0x79,
+  0xe0,0x82,0x65,0x11,0x65,0xdd,0x00,0xbc,0x01,0x8e,0xdb,0x83,0xf1,0x7c,0x23,0x38,
+  0x94,0x1d,0xff,0x2a,0xe0,0xf1,0xaf,0xbd,0xb4,0xea,0xb4,0xda,0x43,0xde,0xc3,0x82,
+  0x3b,0xbb,0xc5,0x93,0x46,0x21,0x30,0x99,0xc5,0xc8,0xb6,0x8b,0x3f,0x23,0x4f,0x52,
+  0xa7,0xab,0xaa,0x55,0xe9,0x29,0xb2,0xf8,0xe7,0x59,0xfd,0x97,0xec,0xb5,0x4a,0x45,
+  0x0c,0xd4,0xff,0x02,0x9f,0x31,0x35,0x0f,0x69,0x0f,0x8b,0x4c,0x23,0x55,0x98,0x24,
+  0x92,0x8c,0x44,0x88,0xac,0x0b,0x3c,0x90,0x36,0x31,0x03,0x8a,0xa9,0x27,0x2b,0xff,
+  0xd0,0xe1,0x6f,0xe9,0x89,0xe1,0xc1,0xa6,0x3f,0xa6,0xf5,0xe8,0x55,0x02,0xf2,0x1f,
+  0x92,0x1e,0xaf,0xdf,0xa3,0xd2,0x78,0x5a,0xef,0x09,0x54,0x49,0xb0,0x8d,0x26,0x5d,
+  0x75,0x7f,0x72,0x15,0xf5,0xf4,0xc4,0x87,0xf9,0x7e,0x91,0xa5,0xff,0x35,0x82,0x47,
+  0x79,0xfb,0x1a,0xdf,0x05,0x5f,0xab,0x6a,0xc0,0xb7,0x53,0xc2,0x22,0x8b,0xf0,0x80,
+  0xef,0xbb,0xe5,0xef,0x1a,0xa3,0x66,0xe4,0x84,0xef,0x47,0x92,0xd7,0x25,0xf6,0x84,
+  0x7c,0x7a,0xdb,0x27,0xd0,0xff,0xfa,0x36,0x02,0xe7,0xed,0xbe,0x43,0xd2,0xeb,0x0f,
+  0x5c,0x46,0x61,0xdf,0x56,0xe9,0x6d,0xfa,0x11,0x89,0xe8,0x8b,0xb6,0x17,0xbf,0xae,
+  0x9d,0xa7,0x11,0xdd,0xb7,0xd5,0x1d,0x08,0x03,0xe3,0xb9,0xfc,0xb1,0xf1,0x2f,0x3b,
+  0x79,0x9b,0xf9,0xf3,0xa7,0x85,0xdb,0x79,0xd2,0x5a,0x00,0x3c,0xfc,0x88,0x36,0x79,
+  0x1b,0xe0,0xa6,0xc3,0x80,0xb6,0xc0,0xe7,0xaf,0xf0,0x1e,0x71,0xf8,0x40,0x68,0x78,
+  0x38,0xb8,0x73,0x02,0xfe,0x79,0xf8,0xc9,0x39,0x5b,0xe9,0x72,0x4c,0xaa,0x39,0x4f,
+  0x3e,0x02,0xef,0xe2,0xda,0x00,0xdc,0x99,0x55,0xa4,0x32,0xe9,0x8b,0x81,0x01,0x1e,
+  0x48,0x68,0x8d,0x2e,0xff,0x86,0xd4,0xda,0xf3,0xe3,0x1f,0x26,0x3d,0x0d,0x1f,0x8c,
+  0x8f,0x7f,0x69,0x35,0x24,0x46,0x15,0xd2,0x60,0x6a,0x22,0xe0,0x29,0x42,0x72,0x15,
+  0x12,0x97,0x59,0xf9,0x2a,0xc1,0x04,0x1b,0x81,0x04,0x1a,0x6c,0xbc,0xdc,0x00,0xeb,
+  0x15,0xf3,0x0f,0x28,0xb3,0x6d,0xfe,0xf9,0x2c,0xfd,0xaf,0x9d,0xdf,0x8b,0xc5,0x14,
+  0xac,0x42,0x6a,0x4d,0x94,0x9d,0x51,0xbe,0x79,0xf5,0xd5,0xc6,0x03,0x89,0xca,0xc1,
+  0xe8,0x62,0x71,0x0a,0x18,0x65,0x43,0xca,0x5f,0x14,0x45,0xc8,0xf7,0x92,0x37,0xda,
+  0xba,0x54,0x65,0xe9,0xe8,0xb7,0x8b,0x5c,0xfc,0xf3,0x1f,0xa6,0xea,0xf8,0x2d,0x31,
+  0x4c,0x42,0xcb,0xbc,0x33,0xa4,0x17,0xe1,0x3a,0x7a,0x1a,0x0c,0x99,0xf4,0x26,0xea,
+  0xfa,0xe0,0x05,0xeb,0x35,0x7a,0xb5,0xd0,0x19,0xaf,0x00,0x2d,0xcf,0xa5,0xec,0x62,
+  0x31,0x2d,0x7c,0xd2,0x1b,0x6a,0x73,0xf1,0xcf,0x7f,0xc7,0x5e,0x82,0x6f,0x93,0xfa,
+  0x26,0x0c,0x84,0x35,0x61,0x46,0xe2,0xa4,0xb3,0x98,0x1f,0x25,0x00,0xda,0xfa,0x37,
+  0x78,0x9a,0x2e,0x15,0x56,0xf7,0x21,0xb1,0x9e,0xe1,0x88,0x0b,0xfc,0x81,0xa7,0x26,
+  0x8e,0xe7,0x9f,0xc7,0x25,0x80,0x07,0xbf,0x47,0xad,0x12,0x8f,0xd0,0xee,0x74,0xd0,
+  0x32,0x4c,0xc7,0xf0,0xfd,0x44,0x0d,0x2a,0xac,0x14,0xd4,0xba,0x7f,0x8c,0x0c,0xff,
+  0x7c,0x56,0xfd,0xd7,0x30,0xb9,0x89,0x74,0x1a,0x92,0x41,0xda,0xc9,0x4c,0x4b,0xf6,
+  0x4b,0xd6,0x6d,0xfd,0x2f,0xc0,0xcc,0x85,0x78,0xbe,0x4a,0xe6,0xb2,0x62,0x70,0xb2,
+  0x4b,0xc4,0xd4,0x8e,0x22,0x8b,0x7f,0x3e,0x2b,0xfe,0xb5,0xab,0x7d,0xc9,0xe9,0xeb,
+  0x66,0xcf,0x9f,0x42,0xda,0xe8,0x12,0x0c,0x72,0x4d,0x29,0x5c,0x45,0xcb,0x86,0x4b,
+  0x11,0x76,0x81,0xf1,0x7a,0xe7,0x4a,0x40,0xd9,0x58,0x79,0xd7,0x69,0xeb,0x7f,0x05,
+  0x26,0xe2,0xdf,0x38,0x4a,0x30,0xb7,0x50,0x5d,0x19,0xff,0x4c,0xc7,0xaa,0x8e,0xb2,
+  0x11,0xe5,0x7e,0xf8,0xd7,0x27,0x19,0x65,0xc3,0x70,0xc1,0xeb,0xe9,0xaa,0x58,0x99,
+  0x29,0xad,0x8c,0x13,0x92,0xa9,0x9b,0x20,0x55,0x67,0x60,0xdd,0xc7,0xf3,0xcf,0x0f,
+  0x91,0x3d,0x69,0xff,0x3e,0xdf,0xcf,0xc4,0xcf,0x92,0xdb,0xd3,0xfe,0x1e,0xef,0x56,
+  0xe9,0xb3,0x1d,0x6b,0x0c,0xb8,0xc3,0x7f,0x26,0x7d,0x96,0x02,0x74,0x4d,0xa9,0x49,
+  0xa9,0x14,0x5f,0x95,0x76,0x44,0xac,0x3e,0x19,0x7c,0xbb,0x71,0x22,0xfe,0xf9,0x8b,
+  0x32,0x57,0xfb,0x32,0xf0,0x7d,0xb8,0x8e,0xbd,0xfd,0x42,0x73,0x15,0x24,0x42,0x24,
+  0xc8,0x7f,0xb8,0x68,0x1e,0x43,0x64,0x53,0x9c,0xfa,0x2f,0x80,0x66,0xe2,0x78,0xfe,
+  0x79,0x30,0x14,0x34,0xca,0xed,0x48,0x4d,0x23,0x27,0xdc,0xb6,0xd9,0xe1,0x1a,0x7c,
+  0xdf,0xbf,0xae,0x82,0x53,0x73,0x38,0x31,0x97,0xcd,0x36,0x3f,0x76,0x16,0xff,0x61,
+  0xc6,0x10,0x5d,0x2d,0xd1,0x84,0x9f,0x1b,0x9d,0xc8,0x9b,0xf1,0x84,0x33,0x26,0xa7,
+  0x6a,0xb1,0xb2,0xf9,0x63,0xe2,0x5f,0x2c,0x18,0x7d,0x2e,0x13,0x95,0x46,0xda,0x43,
+  0x85,0x11,0x21,0x72,0x45,0x30,0x37,0xff,0x06,0xad,0x8a,0x06,0x12,0x0d,0xc7,0x26,
+  0x88,0x7f,0xb9,0xd4,0xbe,0xa6,0x72,0xe3,0xbb,0x8c,0x08,0xd1,0xa1,0x46,0x64,0xfc,
+  0xb4,0xd6,0x60,0xc6,0x57,0x09,0xf3,0x3e,0x8e,0x7f,0x9e,0x4f,0xf8,0x3a,0x5a,0x8c,
+  0x62,0xd6,0xf7,0x8f,0x29,0xfb,0xb2,0xf4,0xbf,0x74,0xb1,0x5f,0xcc,0x74,0x95,0x64,
+  0xc5,0xbf,0xb4,0xac,0xf8,0x97,0x6f,0xfd,0x9f,0x0d,0xa2,0xfe,0x57,0x1f,0x2f,0x04,
+  0x2b,0x8c,0x34,0x2d,0x62,0x44,0x88,0x60,0x5c,0xbf,0x5e,0x3a,0xe5,0x5a,0x14,0xa1,
+  0x1e,0xf0,0x57,0xb1,0xc5,0x7f,0x68,0xd5,0x7f,0xcd,0xb3,0x96,0xc0,0x92,0xfd,0xc2,
+  0x28,0x0c,0x33,0xde,0xe2,0x11,0xcc,0x0a,0x9e,0x83,0x37,0x20,0x54,0x64,0xae,0x73,
+  0x89,0x33,0x72,0x64,0xf0,0x97,0x96,0xa9,0xff,0x22,0xff,0x44,0x3e,0x43,0xc5,0x80,
+  0x30,0x62,0xe9,0x7f,0x15,0x9e,0xc4,0xbb,0x8e,0x36,0xd8,0xd9,0x86,0xe0,0x15,0x6c,
+  0x72,0x07,0xcb,0x14,0x87,0x7f,0xde,0x8e,0x7f,0x35,0x72,0x92,0x8d,0xa4,0x71,0xbb,
+  0x76,0x6d,0xbb,0x3c,0x03,0x8c,0xe9,0x9a,0xa7,0x5d,0x41,0xfd,0x2f,0x34,0x60,0xcc,
+  0x76,0x63,0xbb,0x36,0xbf,0x5d,0xce,0x0a,0x96,0x05,0x32,0xfc,0x1b,0x85,0xb6,0xfe,
+  0x57,0x03,0xa7,0x52,0xf1,0x00,0xfe,0x32,0x10,0xc8,0xa3,0x21,0xc0,0x2a,0x37,0x29,
+  0x89,0x07,0x31,0x46,0x36,0xbd,0x51,0x49,0xac,0xc9,0x2a,0x16,0xab,0x5a,0xaa,0xfc,
+  0xcb,0x84,0xfc,0xf3,0xa3,0xc3,0xf0,0xe7,0x3f,0x92,0x60,0xf0,0xc9,0xf0,0xbd,0x05,
+  0x3f,0x6c,0xfb,0x71,0x6c,0x75,0x7f,0xc4,0xf0,0x6c,0x94,0xb6,0xc5,0x76,0x0f,0xd4,
+  0xc6,0xbc,0x9b,0xa4,0xec,0x22,0xaf,0x66,0xef,0x84,0xfa,0x5f,0x25,0x67,0x49,0xdd,
+  0x92,0xca,0x0d,0x8d,0xcb,0xb4,0x51,0x79,0xe6,0xbc,0x7c,0xad,0xb1,0x49,0x7c,0x65,
+  0x63,0xdd,0x3c,0xdf,0xb5,0x8d,0x7f,0xa3,0x9d,0x6d,0x9f,0xf9,0xc5,0xfc,0x8d,0x0b,
+  0xfe,0x9a,0xbc,0xe2,0x7e,0x2e,0x16,0x25,0xda,0x5e,0x1e,0x1f,0xff,0x12,0xb0,0x7e,
+  0x30,0x9f,0x48,0x3a,0xbc,0x95,0x9c,0x3b,0x2a,0x8c,0x09,0xc3,0xa7,0x99,0xa2,0x9c,
+  0xb7,0x1d,0xbc,0xc1,0x11,0xd9,0xe6,0xdf,0xd0,0x59,0xcb,0xc1,0xec,0xf8,0x57,0x1e,
+  0x42,0xaa,0xaf,0x83,0x61,0x24,0x03,0x01,0xe2,0x21,0x05,0x34,0x37,0x49,0x86,0xc0,
+  0x09,0x14,0xa9,0x04,0x06,0xb4,0xe4,0x82,0x93,0x46,0x5d,0xc1,0xb2,0x87,0xe5,0xea,
+  0xed,0xcb,0xb3,0xe2,0x5f,0x8f,0xc9,0xce,0x71,0x3a,0xea,0x7f,0xe5,0x7a,0xc5,0xb6,
+  0x4c,0x64,0x84,0xb1,0x8e,0x1f,0x65,0x2d,0x01,0xcd,0xe3,0x0a,0x96,0xb5,0x91,0xaa,
+  0x97,0xf3,0x42,0xd9,0xf1,0xaf,0x6f,0xc0,0xfb,0xd9,0x7f,0x0a,0x0f,0xc1,0x30,0x4b,
+  0xa7,0x80,0x19,0x1e,0x1e,0xf6,0x2a,0xe3,0x6c,0x12,0xab,0x50,0x2a,0x51,0xe3,0x02,
+  0xc1,0xd8,0x72,0x99,0xac,0xf2,0x56,0x1a,0x79,0xf7,0xda,0x3c,0x6f,0x88,0xbf,0x7e,
+  0x67,0xc7,0xbf,0x76,0xd1,0x3a,0x2e,0xf2,0xf5,0x8b,0x4c,0x45,0x98,0x85,0xb6,0x7e,
+  0x81,0x5d,0x8b,0xa5,0xaf,0xda,0xc1,0xb2,0xcb,0xd0,0x52,0xbf,0x24,0x7f,0x65,0x36,
+  0xff,0xbc,0x5d,0xb7,0x6e,0xd7,0x7f,0xfd,0xc6,0x66,0x78,0xb8,0x90,0x31,0x66,0xe1,
+  0xb9,0xdf,0x53,0x2e,0xfe,0x43,0xd4,0x26,0x48,0x14,0x67,0xe9,0x7f,0x81,0xcb,0xb7,
+  0x5b,0x7a,0x4f,0xb9,0x92,0x88,0x0c,0x32,0xdf,0xef,0x40,0x82,0x55,0x84,0xa1,0xfe,
+  0x57,0x3d,0x63,0x9b,0x47,0x6a,0xe8,0x41,0xdf,0x62,0x56,0x08,0xc6,0x34,0xc2,0x2e,
+  0x62,0xd7,0x0a,0xef,0x88,0x8b,0x7f,0x5e,0xdb,0xb5,0x05,0x7e,0x32,0x6c,0x25,0x98,
+  0x25,0xf8,0x36,0x6e,0x64,0xba,0x35,0x09,0xaf,0xc6,0x76,0x04,0xf8,0xd6,0xa6,0xb3,
+  0xbd,0xe9,0x8b,0xf1,0xc9,0xe4,0x43,0x52,0xc9,0xea,0xbf,0x8c,0x5d,0x5f,0xac,0x46,
+  0x25,0x65,0x8b,0x7f,0xbe,0xd4,0xe6,0x3f,0x64,0xf5,0x5f,0xf2,0x37,0xfa,0x38,0x86,
+  0x95,0xf1,0xcf,0xe7,0x9f,0x6a,0xde,0x25,0x54,0x5a,0xfa,0x5f,0x58,0x1a,0xd6,0x2c,
+  0xd6,0xc1,0x84,0x7f,0xa3,0x97,0x5f,0x87,0x54,0x46,0x4b,0x5b,0x44,0x47,0xff,0xcb,
+  0x1d,0xff,0x0a,0x05,0x07,0xc0,0x38,0x46,0xa1,0xe5,0xa8,0x5a,0x23,0x1e,0xa5,0x3b,
+  0x92,0xde,0xa3,0x9d,0x35,0xd8,0x12,0x0a,0x9e,0x90,0xae,0x15,0xbd,0xd4,0x95,0xec,
+  0x11,0x6c,0x5a,0x3c,0xd3,0xe6,0x9f,0xef,0xc9,0xaa,0xff,0x32,0x22,0xc3,0x93,0xf6,
+  0x90,0xf7,0x51,0xa8,0x08,0xb3,0x9f,0xdf,0x97,0x2f,0x98,0x11,0x74,0x14,0xdf,0xc7,
+  0xae,0x01,0xdf,0x64,0xb5,0x12,0xf0,0x45,0xc6,0x3f,0x6c,0xf1,0x96,0x8c,0x8d,0x7f,
+  0xb1,0xae,0x0f,0x31,0x68,0x12,0x6a,0x3b,0x4a,0x2e,0x28,0xe8,0x9c,0x94,0x1f,0xd5,
+  0x3e,0xe4,0x81,0x30,0x56,0xd2,0xde,0xbf,0x28,0x91,0x95,0x8b,0x65,0x44,0x16,0xc3,
+  0xab,0x72,0x5c,0xfd,0x57,0x39,0x1a,0xc8,0x6d,0xd8,0x58,0xc7,0xf5,0xbf,0x86,0xa5,
+  0x3a,0x80,0x5d,0x35,0xe6,0xf5,0xcc,0xc0,0x96,0x57,0xc0,0x17,0x3d,0xee,0xf2,0x33,
+  0x89,0x77,0xa0,0x2d,0xe0,0xc2,0x5f,0x99,0xb8,0xd5,0x56,0x73,0x7a,0xca,0xf3,0x14,
+  0xa0,0xad,0x9f,0x32,0x43,0x04,0xa3,0x57,0x45,0xe6,0xc0,0x4e,0xe8,0x0a,0xf4,0x48,
+  0x0b,0x33,0xfc,0x1b,0xbb,0x1f,0x08,0x86,0x94,0xcd,0x34,0x30,0x8e,0x7f,0x83,0x1d,
+  0xdd,0x67,0xeb,0x7f,0xc9,0x3f,0xe0,0xd0,0xcc,0x6a,0x49,0x88,0x2b,0x5c,0x3c,0x6f,
+  0x14,0xde,0x63,0x9b,0xdc,0xf8,0x8b,0xc5,0xbf,0xc2,0xb8,0x3a,0x44,0x3f,0xa9,0xf0,
+  0x60,0x34,0xd2,0x7c,0x35,0x78,0xf5,0x47,0x78,0xfd,0x17,0xb4,0xe8,0x31,0xcc,0xd6,
+  0x58,0x41,0x1e,0x31,0x82,0x87,0x6d,0x7f,0xc3,0x50,0x34,0x8f,0xc8,0xf7,0x2f,0x9a,
+  0xbf,0x42,0x71,0xc5,0x2b,0x6d,0xd9,0x2f,0x70,0xe3,0x37,0x83,0x41,0x7f,0xc3,0x54,
+  0xa4,0xb1,0x45,0x0f,0x9f,0xf0,0x26,0x8a,0x57,0x88,0x47,0x0c,0x58,0x0b,0x6b,0xbd,
+  0xc8,0xc2,0x84,0xe4,0xc6,0x5f,0xa5,0xf5,0xe6,0x3a,0x96,0x0d,0x25,0x66,0xf4,0xbf,
+  0x60,0x7a,0x27,0x5d,0x94,0xdf,0x0f,0xd8,0xb3,0x6a,0x54,0xf7,0x2d,0x1a,0x90,0x4e,
+  0x69,0x99,0xc4,0x36,0xd8,0x77,0xc0,0x27,0xb1,0xde,0xab,0xa6,0x80,0xda,0x0d,0xf6,
+  0xd3,0xdd,0x5a,0x93,0xfe,0x21,0xc7,0x56,0x73,0x38,0xc8,0xe2,0xd0,0xac,0x91,0x73,
+  0xd4,0xb3,0x33,0x90,0x77,0x58,0x8b,0xf0,0x1e,0x60,0xbd,0x9b,0xd3,0xc1,0x01,0x3b,
+  0xfe,0xc5,0xf8,0x0f,0x5b,0x6d,0x48,0x15,0x9f,0x75,0x7a,0xb3,0x4b,0x5b,0xf9,0x3d,
+  0x6d,0xaf,0x0b,0x6d,0xe1,0xcc,0xbf,0x47,0xe6,0xd8,0x2d,0xc8,0xe7,0xe0,0x41,0xbe,
+  0x8b,0x10,0xc7,0x05,0x9c,0xf6,0xd0,0x83,0x21,0x2d,0x5e,0x58,0x54,0x74,0x54,0x70,
+  0x9e,0x14,0xac,0x8b,0xc4,0x0c,0x01,0x79,0x07,0xbc,0x54,0x3d,0xf0,0xce,0xcc,0x90,
+  0x3f,0x74,0x71,0xae,0x57,0x37,0xff,0x06,0xad,0xfa,0x85,0xda,0xe5,0xe7,0xe5,0x7e,
+  0x6b,0x9e,0x46,0x15,0x3c,0x52,0xd5,0xaf,0xa6,0xfc,0x67,0x84,0xbd,0xd7,0xb2,0x48,
+  0x28,0x4a,0x60,0x57,0x2d,0xe9,0x18,0x93,0xa3,0xe8,0x37,0xa7,0x6f,0xcf,0x8a,0x7f,
+  0x91,0xc8,0xe9,0x82,0x7d,0xd2,0x19,0xfd,0xc3,0x64,0x78,0x58,0xed,0x61,0xf7,0xfc,
+  0xb5,0x1f,0xf8,0x9e,0x96,0xde,0x35,0xe0,0xb5,0x03,0xcf,0x17,0xcc,0xc6,0x05,0xa3,
+  0x76,0x78,0x0a,0x2e,0xd3,0x3b,0x58,0x7a,0xc9,0xc1,0xda,0x33,0xe6,0xc2,0x4d,0xe5,
+  0x19,0xfe,0x0d,0xc5,0x5a,0x82,0xcb,0x09,0x16,0xc7,0x1f,0x6e,0xbc,0x6c,0x5c,0x31,
+  0x38,0x98,0x55,0xae,0xb4,0xd7,0xbf,0x71,0xfd,0x59,0xe1,0x7e,0xab,0x7a,0xa8,0xcd,
+  0x85,0xbf,0x3e,0x4a,0x82,0x41,0x5c,0xfc,0xf3,0x1a,0x6c,0x52,0x03,0x05,0x3b,0xcb,
+  0x57,0x90,0x77,0x8c,0xf0,0xc0,0xda,0x9d,0xd2,0xbb,0x60,0x30,0x3a,0xd9,0x4a,0xf2,
+  0x4e,0x53,0x18,0x9f,0xf7,0x77,0x15,0x7c,0xde,0x6d,0x1a,0x7c,0xfe,0xa6,0x1d,0xf5,
+  0xd6,0xf6,0xc1,0xcd,0x56,0xe2,0xc6,0x5f,0xce,0xe3,0x30,0xcb,0x52,0x61,0xc8,0xa9,
+  0xe2,0x87,0x0f,0x4e,0x15,0xe4,0x5e,0x01,0xd6,0x6b,0x5f,0x91,0x7b,0x7e,0xcc,0xad,
+  0xe7,0xf2,0x1f,0xcf,0xca,0x3f,0xa4,0xba,0xb9,0x06,0x63,0xf4,0x58,0x05,0x59,0xea,
+  0xd4,0x2f,0xc3,0x46,0x06,0xab,0x83,0xf1,0xca,0x30,0x7b,0x0a,0x4c,0xf0,0xba,0x5d,
+  0x2f,0xbd,0x94,0x36,0xdd,0x54,0x4a,0x3c,0x16,0xff,0xc6,0x76,0xc4,0x5f,0x66,0x79,
+  0x5a,0x19,0x15,0xc1,0xa7,0x8b,0xdf,0x70,0xd4,0x56,0xa1,0x4a,0xab,0x23,0x45,0x3f,
+  0x32,0x0e,0x60,0xa6,0xdc,0x7d,0x57,0x23,0x64,0xf8,0x46,0xda,0x26,0x42,0xc4,0x94,
+  0xb9,0x57,0x69,0x2a,0x55,0x96,0xce,0x8b,0x66,0xe5,0x1f,0x46,0x43,0x66,0x41,0x08,
+  0xde,0x09,0xbf,0x25,0xa1,0x73,0x5e,0x7c,0x6b,0xfd,0x16,0x75,0xe4,0x67,0x48,0x5e,
+  0xe3,0x6b,0x89,0x96,0x01,0xdf,0x6c,0xe9,0xa8,0x0c,0x2f,0xb4,0x73,0x32,0xbe,0xe2,
+  0x76,0x24,0x19,0xfe,0x3a,0x46,0x86,0xcd,0x5a,0x54,0xc4,0x70,0xc5,0xbf,0xfe,0xe0,
+  0xc4,0x97,0xb5,0xb9,0xec,0xec,0x42,0x61,0xfa,0x5f,0x2d,0x6d,0x67,0xe0,0x65,0xce,
+  0xa3,0x93,0x65,0x17,0x4a,0x23,0xbd,0x36,0xed,0x7c,0x9f,0xef,0xac,0x70,0x11,0x3c,
+  0xfc,0xef,0x60,0x0e,0xf0,0x98,0xfc,0xc3,0x45,0x3d,0x8d,0x3c,0x36,0xba,0x88,0x65,
+  0x1b,0x26,0xc2,0xe6,0xa2,0x54,0xf1,0x7b,0xf2,0x91,0xc2,0xc8,0xe0,0x17,0x76,0x17,
+  0x07,0xc9,0x87,0x14,0x5a,0x7a,0x58,0x7e,0x42,0xe6,0xe5,0x80,0x8c,0x88,0x6f,0x8f,
+  0xe1,0x3f,0xbc,0x07,0xf5,0x3d,0x63,0x95,0xfd,0x9d,0xb0,0xd1,0xc3,0x46,0x76,0x23,
+  0x93,0xad,0x6c,0x5f,0xa5,0x57,0xf6,0x5b,0xbc,0xbb,0x37,0x21,0x9d,0x91,0x2b,0x19,
+  0xe6,0x00,0x4a,0xab,0x18,0x76,0xfc,0xcb,0xe2,0x3f,0xc4,0xf4,0xe0,0x08,0x62,0xab,
+  0x33,0xea,0x7d,0xb0,0x21,0x1e,0x60,0xf9,0x87,0xe2,0x95,0x5b,0x57,0x6d,0xa9,0x1e,
+  0xf5,0x9c,0x17,0xa7,0xd0,0x03,0x49,0xd6,0xf2,0x55,0x17,0x58,0xa3,0x5b,0xd2,0x81,
+  0xc5,0x59,0xf1,0x2f,0xac,0x87,0x9d,0x3d,0xbd,0xa0,0x81,0xb9,0x2b,0x33,0xe3,0x47,
+  0xf5,0x1d,0xc9,0x00,0x66,0xd7,0x1c,0x57,0xda,0xcc,0xe0,0x80,0x32,0xab,0xc8,0x67,
+  0xec,0x48,0x54,0xbc,0xe4,0x09,0xa1,0xdf,0x22,0xd8,0xfb,0x57,0x33,0xdc,0x75,0xb9,
+  0x59,0xf1,0x2f,0xad,0x3e,0x85,0x6c,0x87,0xc6,0xb1,0xe6,0xfa,0xc4,0xba,0x65,0xd2,
+  0x28,0xb9,0x2c,0xd7,0xac,0xf5,0xbd,0x2f,0x8d,0x82,0xc3,0x52,0xbf,0xb1,0x20,0x2d,
+  0xcd,0x21,0x97,0x9b,0x6b,0x12,0x80,0xbf,0x96,0x33,0xb0,0xa6,0xf2,0xf8,0x17,0x40,
+  0xb3,0xc1,0x2c,0xfe,0xf9,0x79,0x11,0x2b,0x8b,0x49,0x8b,0xe4,0xa2,0x61,0x80,0x01,
+  0xce,0x5b,0x63,0x9a,0xa2,0xb1,0xa8,0x55,0x65,0x1c,0x1d,0x8a,0x0f,0x5d,0x33,0x74,
+  0x02,0xaf,0xb7,0xe2,0x5f,0xda,0xd8,0xfa,0x2f,0x2c,0x1f,0x6b,0x03,0x97,0x4f,0x08,
+  0x73,0xa1,0xd8,0x93,0x56,0x5a,0x94,0x3c,0xa2,0x70,0x6f,0x50,0x3f,0x09,0x48,0x6a,
+  0xb2,0xed,0x5e,0x1e,0x67,0x84,0x03,0x09,0x70,0xfe,0x4b,0x55,0x77,0xfd,0xd7,0x6d,
+  0x55,0xe4,0xaf,0x90,0x4f,0x2f,0xc9,0x03,0x2b,0x14,0xbc,0xca,0x20,0x89,0xba,0x44,
+  0x7b,0x4d,0x8c,0xa7,0xb4,0x28,0x1b,0xb3,0x30,0x9a,0xe1,0x37,0x96,0x8f,0xa9,0xff,
+  0xaa,0x22,0x0b,0x92,0x45,0x18,0x85,0x79,0x1d,0xfe,0xaa,0x48,0x47,0xc1,0x59,0x92,
+  0x87,0xcc,0xdb,0xec,0x3a,0x49,0x31,0x2d,0x7f,0x5f,0x08,0xb6,0x04,0x12,0xf1,0x31,
+  0xd7,0x09,0x74,0x4d,0xc0,0x7f,0x88,0x69,0x6c,0xba,0xd1,0x09,0x6e,0xbc,0xc8,0xc8,
+  0xea,0x19,0x52,0xb0,0xbb,0x50,0x11,0x2c,0x50,0xc8,0xe0,0xc0,0x0a,0x3b,0x59,0x31,
+  0x69,0x60,0xfd,0x97,0xa0,0xbb,0xf0,0x97,0xa7,0x33,0xfe,0x58,0x3a,0xd9,0x1f,0x08,
+  0x7b,0x7c,0xf1,0xe7,0x74,0x30,0x22,0x9e,0xfc,0x78,0x5b,0x3a,0x39,0x12,0x60,0xb2,
+  0x5f,0xe9,0x6d,0x27,0xa7,0x33,0x6f,0xd9,0x1d,0x67,0x6c,0x0e,0x51,0xc0,0xd4,0x2e,
+  0xfe,0x0d,0x44,0x40,0xbe,0xe6,0xc6,0x53,0x25,0x48,0x2b,0x3a,0x09,0xc3,0x55,0x6f,
+  0x70,0x6e,0xf9,0x13,0xd0,0x35,0x17,0x83,0x53,0x17,0xc9,0x25,0xb1,0x3e,0x5a,0xb0,
+  0xc1,0x9d,0xf3,0x76,0x49,0xab,0x62,0xf5,0x5f,0x99,0xfc,0xc3,0x4b,0x24,0xb2,0xdc,
+  0xf7,0xfd,0xe2,0x17,0x12,0xbd,0xc9,0x30,0x18,0x8d,0x6f,0xd2,0x51,0x8a,0x2d,0xd2,
+  0x9b,0xf4,0xd0,0x36,0x30,0x36,0x81,0x31,0xba,0x65,0x8e,0xb9,0x70,0x20,0xc3,0x1d,
+  0xc1,0xe3,0x5f,0xde,0x31,0xf5,0x5f,0x2c,0xed,0xf0,0x34,0xe9,0x30,0x66,0x69,0x6a,
+  0x3b,0x18,0x7b,0x9a,0xf0,0xbc,0x8e,0x55,0x7b,0xc1,0x3c,0x6f,0x63,0x99,0x96,0x7e,
+  0x1e,0x11,0x73,0xc0,0x5a,0x0a,0x96,0x57,0x71,0xf8,0x37,0x2c,0xfe,0xc3,0x66,0xb5,
+  0x44,0x7c,0x43,0x5c,0x6d,0xe8,0x2d,0x60,0x3c,0x4f,0xba,0x0c,0xde,0x42,0x5a,0xb9,
+  0xf1,0x3c,0xd9,0x5d,0x18,0x70,0xd2,0x0e,0x79,0x68,0xac,0x8b,0x2c,0x03,0x9c,0xbb,
+  0xb4,0xc8,0x95,0x7f,0x68,0x56,0x45,0xd5,0x0d,0x2c,0xda,0x85,0xda,0x5e,0xf1,0x41,
+  0x1d,0xb5,0xe1,0xae,0xdb,0x28,0xbe,0x41,0x57,0xcb,0x55,0x0d,0x2a,0xc3,0xef,0x8a,
+  0x6e,0x94,0xe2,0x72,0xdf,0x62,0xaf,0x7b,0x97,0x51,0x81,0x39,0x8a,0xee,0xfa,0x2f,
+  0x23,0xf2,0x25,0x5f,0xa2,0xed,0x79,0xad,0xd7,0x08,0x2f,0xf3,0x3d,0x8a,0xfc,0x87,
+  0x46,0xa4,0x99,0x09,0x28,0x1f,0x4a,0x45,0xee,0xf5,0xfd,0x50,0xfa,0xdd,0xbc,0xb3,
+  0x89,0xe9,0xf7,0xac,0xcd,0x70,0x6b,0xb0,0x8c,0xcd,0x59,0x86,0xf2,0x5d,0xd5,0xaa,
+  0xff,0x5a,0x2e,0x6c,0x13,0x38,0xce,0x6d,0xc4,0xd0,0x18,0x27,0xfc,0xe7,0xd5,0x5e,
+  0x9b,0x5d,0x99,0x8d,0x85,0x6f,0xb9,0xd2,0x0e,0x1d,0xd2,0x8f,0x86,0x6a,0xe4,0xdf,
+  0xd0,0x1d,0xfc,0x65,0x46,0x2c,0x90,0xe5,0x62,0x6b,0xd1,0xb8,0xfe,0x97,0x01,0x06,
+  0x95,0x4e,0x8b,0xfd,0x86,0x1b,0xc8,0xdb,0xd0,0xcc,0xdb,0xe6,0xce,0x3f,0x7c,0x6f,
+  0xad,0x05,0xa9,0x7e,0x4a,0xb6,0x5a,0x89,0x88,0x39,0x55,0xd4,0x93,0x14,0xfb,0x19,
+  0xda,0xf2,0x20,0xff,0xc6,0x1a,0x52,0x9d,0x50,0xde,0x8d,0x43,0x97,0xcd,0x7f,0xb8,
+  0x9f,0x7e,0x96,0x2a,0x83,0xee,0xfa,0x2f,0x17,0xa4,0xd2,0x4d,0x47,0x5b,0x59,0xc9,
+  0x18,0x0d,0x8c,0x69,0xed,0xf5,0x3c,0xe2,0xde,0xbf,0x76,0xd0,0x6d,0x66,0x60,0xb6,
+  0x1b,0x7f,0x3d,0xce,0x75,0x81,0x2f,0x92,0x9f,0x67,0xb4,0x95,0xab,0xd3,0x8e,0xe1,
+  0x69,0xf1,0x33,0xe9,0xe1,0x97,0xf2,0x0c,0x9b,0x32,0x82,0xc7,0xbf,0xb0,0x42,0xd6,
+  0x5d,0xff,0xe5,0xe4,0x1f,0xfe,0xc2,0x89,0x6d,0xb5,0xa2,0x10,0x33,0x1a,0x71,0xcb,
+  0x00,0xb4,0x95,0xac,0x5c,0x9c,0x91,0x5d,0x7e,0x95,0x7c,0x44,0x6f,0xc2,0x2e,0xbb,
+  0xfe,0xeb,0x1a,0x2b,0x7b,0x2d,0xbb,0x6e,0x42,0xac,0xb3,0x88,0x38,0xc0,0x60,0x6c,
+  0x87,0x4c,0x61,0x8a,0xba,0xc7,0xbc,0x02,0xfb,0x4e,0xb5,0xbb,0xfe,0x2b,0xfa,0x1d,
+  0x2e,0xb2,0x1c,0x31,0xae,0xd0,0x1a,0xcc,0x3f,0x9c,0x62,0x1c,0x07,0xd8,0x75,0xfd,
+  0xa8,0xb4,0xdf,0xb8,0xe2,0x9c,0xc6,0x27,0xea,0x97,0xb1,0x8c,0x44,0xce,0xd1,0x01,
+  0x2d,0x97,0xc6,0xd5,0x7f,0xed,0xc2,0x48,0x56,0x0b,0x60,0xc6,0x5d,0x44,0x1f,0xf2,
+  0xb4,0x48,0x9b,0xc9,0xaf,0xc8,0xdc,0xa3,0x30,0x09,0x53,0x18,0x5c,0x02,0xbf,0x0e,
+  0x66,0x63,0x4b,0xd5,0xdf,0x28,0xa6,0x38,0x19,0xe1,0x12,0x9f,0xba,0xbd,0xb4,0xbc,
+  0x29,0x8b,0x7f,0x5e,0xae,0x8f,0x6e,0xc1,0xd3,0xa7,0xc9,0xc9,0x03,0xe4,0x86,0xfe,
+  0xbc,0x61,0xf1,0xdb,0xc2,0x2a,0x0d,0x26,0x73,0x38,0xbc,0xb9,0x83,0xcf,0x6a,0x9c,
+  0xe3,0x2f,0x8f,0x81,0x05,0xc8,0x9a,0xc5,0xd1,0xb1,0x53,0x29,0x33,0x03,0xcb,0xdc,
+  0xf5,0x5f,0xe0,0xc6,0x0f,0xab,0xb7,0x88,0x9f,0xd7,0x77,0xf4,0x57,0x0c,0x48,0xb3,
+  0xc5,0x87,0x0b,0xc1,0xbd,0x1c,0x56,0x67,0x13,0xa4,0x50,0x66,0xab,0x7c,0x0c,0x8c,
+  0xaa,0x01,0x25,0x8b,0xb7,0x79,0x37,0xf5,0x13,0x45,0xf7,0xb8,0xea,0xbf,0x3e,0xa4,
+  0xa1,0x41,0x1f,0x8a,0x62,0x7f,0x48,0x67,0xbd,0xfe,0x50,0x8f,0xf4,0xf7,0xc2,0x73,
+  0x1d,0x91,0x93,0xbe,0x1e,0xe9,0x67,0x3a,0xf8,0x87,0xaf,0x43,0xd7,0xbb,0x1d,0x17,
+  0x68,0xd5,0x17,0xab,0x92,0xd2,0x53,0xd9,0x87,0xb1,0xde,0xac,0xfa,0x2f,0x96,0xbd,
+  0x86,0xda,0xca,0x17,0xb4,0x3d,0xe6,0xc3,0x5d,0x6d,0x67,0x62,0x17,0x94,0x5a,0xd3,
+  0xd7,0x85,0xfa,0xcb,0xa5,0x11,0x4b,0x88,0x39,0x14,0x59,0xec,0x12,0x0e,0xb0,0xeb,
+  0xf5,0x76,0x8e,0xa9,0xff,0xea,0xcd,0x1f,0x96,0xbe,0x2d,0xbf,0x86,0x65,0x5f,0xdc,
+  0x39,0xa9,0x39,0xf8,0x30,0x1a,0xef,0x03,0xec,0x9a,0x04,0xf8,0x0b,0x7d,0xd1,0x40,
+  0x3e,0xef,0xaa,0x36,0xd7,0x71,0x5c,0x50,0xd3,0xee,0xed,0x91,0xac,0xfa,0x2f,0xc6,
+  0x3f,0x9f,0x76,0xfc,0x43,0xdb,0x1b,0x24,0xd3,0x01,0x76,0xe5,0x9e,0x51,0x76,0x30,
+  0xdc,0xe4,0x41,0x1f,0xb2,0x96,0x28,0xfb,0x5c,0xfe,0xb3,0xdc,0x43,0xfc,0x89,0xfc,
+  0x67,0xb3,0xf8,0xe7,0x29,0x13,0x59,0x5e,0x41,0x7e,0x20,0x22,0xc9,0x7c,0x11,0x72,
+  0x8c,0xe3,0x9f,0x83,0x67,0xfe,0x24,0x18,0x3f,0xb0,0xea,0xbf,0xb4,0xbc,0xa7,0x9c,
+  0xeb,0xe4,0x02,0x8e,0x53,0xfc,0xcd,0xca,0xce,0x86,0xb4,0xc3,0x7f,0x48,0xf6,0xea,
+  0xfc,0xfb,0xd0,0x4e,0x31,0xf0,0x32,0xcb,0x0a,0xde,0xcb,0x0e,0x75,0x8b,0x16,0x92,
+  0xbd,0x5a,0xcc,0xec,0x4c,0x71,0x9a,0x65,0x51,0x61,0xcf,0xa9,0xb6,0x82,0xeb,0x2f,
+  0x77,0xeb,0x49,0xf3,0xef,0x42,0x4e,0xfd,0x57,0xfe,0x0a,0xc6,0xa4,0xc1,0x49,0x51,
+  0xc0,0x91,0x5e,0x84,0xb1,0x48,0x9e,0x5b,0x28,0x22,0xe1,0x64,0xb7,0xe9,0x7b,0xba,
+  0x38,0x28,0x5f,0xd0,0xef,0x4f,0x3c,0x94,0xc4,0xd4,0x44,0x4e,0x96,0xf8,0xae,0x81,
+  0x42,0x96,0xf0,0x46,0x32,0x45,0xa7,0xfe,0xeb,0x6c,0x03,0xd2,0xe8,0x7d,0xe9,0x8c,
+  0xf1,0xcf,0x00,0x8a,0x39,0x9f,0x9e,0xc0,0x88,0xf5,0xde,0xe5,0xde,0xfb,0x07,0xc5,
+  0xc8,0xd1,0x51,0x1b,0x67,0xfc,0x87,0x57,0x04,0x40,0x0a,0x8c,0x9f,0x2d,0x54,0x6f,
+  0x56,0x8f,0xe3,0x3f,0xc4,0x23,0x0b,0xfa,0x3e,0xf2,0x28,0x7e,0x80,0x24,0xf3,0x7a,
+  0x8d,0x19,0x04,0xcf,0x93,0xbc,0x86,0xa4,0x28,0xc3,0xad,0x17,0x03,0x57,0x94,0x62,
+  0x58,0xca,0x36,0x18,0x4c,0x2c,0x68,0x76,0x91,0xd4,0x24,0xbd,0xc3,0xaa,0x1b,0x7f,
+  0x71,0x48,0x75,0x05,0xe0,0x1d,0xbc,0x76,0x46,0xfc,0x11,0xb2,0xcb,0x28,0x1f,0x50,
+  0x30,0x97,0xee,0xe7,0xa4,0xdc,0x54,0x47,0xa4,0x2b,0xe4,0x80,0xf9,0xd9,0x61,0xf5,
+  0xa2,0xf4,0x1e,0x18,0x16,0xff,0x61,0x97,0x08,0xf7,0x73,0x87,0xc7,0x85,0xbf,0xac,
+  0x5b,0x7d,0x6d,0xe9,0x63,0x58,0xf6,0x35,0xc3,0xe3,0x35,0x76,0x18,0xfa,0xf3,0x1d,
+  0x33,0xb5,0x17,0x95,0x1d,0x9a,0xde,0x37,0xa6,0xe4,0xa4,0xc9,0x3a,0x57,0x4f,0x22,
+  0xff,0xbc,0x7e,0xfb,0x38,0xfe,0x43,0xb8,0x25,0x2c,0x4c,0x1d,0x2c,0xdd,0xc1,0x11,
+  0xc7,0x19,0xe1,0x49,0xf1,0xa7,0x48,0x4d,0xff,0x94,0xb0,0xd7,0x0e,0x77,0xe2,0x2d,
+  0xd1,0xc9,0xf0,0x3b,0x9d,0xfe,0x1c,0x78,0x44,0x16,0xfe,0x92,0xdd,0xf1,0xaf,0x77,
+  0x6c,0xda,0x43,0x0c,0x22,0x03,0xba,0x39,0xaa,0x5c,0x10,0x91,0x14,0xa5,0x08,0x53,
+  0xac,0xfd,0xd0,0x25,0xf2,0x84,0x6a,0x8e,0xbf,0xe8,0x9e,0xe1,0x85,0x49,0xb5,0x70,
+  0x5c,0xfc,0xeb,0x14,0xcf,0xcb,0x75,0xf8,0x0f,0xf9,0x53,0x70,0x33,0x2f,0x0d,0x63,
+  0x3e,0x7f,0x4a,0xba,0x28,0xfc,0x21,0x93,0xac,0x78,0xf3,0x90,0xaf,0x4c,0x9d,0xb0,
+  0xfe,0x4b,0x88,0x58,0x5a,0x12,0x0a,0xbb,0xa3,0x78,0xf6,0x5a,0x3e,0x3b,0xd7,0x12,
+  0x19,0x8d,0x79,0xd0,0xfa,0x3e,0xc5,0x67,0xb4,0x93,0xa4,0x76,0xc0,0xbb,0xdf,0xc6,
+  0x5f,0x2e,0xfe,0x79,0x5e,0xe4,0xc5,0xaa,0xbd,0xea,0xcd,0x72,0x33,0x7f,0x58,0x7c,
+  0x96,0x42,0xcb,0xeb,0x76,0xfd,0xd7,0x90,0x3a,0xdc,0x10,0xd4,0x0e,0xc8,0x16,0xbf,
+  0xcd,0x6e,0xf2,0xd3,0x81,0x8e,0x9d,0x62,0xf7,0xc7,0xd7,0x7f,0x81,0x31,0xe0,0xef,
+  0xcd,0x0b,0x15,0x15,0xd0,0xbd,0x84,0x91,0xf4,0xb2,0xae,0x93,0xac,0x34,0x6c,0x87,
+  0x1d,0x07,0x49,0xc4,0xfc,0xb1,0x7e,0xcd,0x7f,0x0b,0x7f,0xbe,0x86,0x5d,0xf1,0x2f,
+  0x93,0x91,0x1c,0x62,0xf1,0x11,0xf8,0xfc,0x6f,0xdc,0xb8,0x52,0x44,0x01,0x14,0x56,
+  0x08,0x66,0xc3,0x2e,0x78,0x63,0xef,0xa0,0x16,0x40,0xd8,0x99,0x78,0xf2,0x0e,0x40,
+  0x64,0x4f,0x39,0xf8,0x0b,0xd9,0x0e,0x0f,0xb1,0xfa,0xaf,0x1d,0xc8,0x7f,0xc8,0x4f,
+  0x8d,0xc2,0x66,0x4e,0x48,0x2a,0x18,0xf8,0x50,0x8b,0x98,0x0f,0x85,0x8a,0x31,0xdb,
+  0x90,0xd5,0x7f,0x21,0x59,0xc7,0x6c,0xae,0x11,0x36,0x60,0xd4,0xf6,0x2d,0x2c,0x52,
+  0x33,0xf8,0x8b,0x1f,0x59,0x58,0x24,0xa2,0x03,0x05,0xec,0xa0,0xc3,0xa8,0x1f,0x98,
+  0x74,0x6f,0xdb,0x25,0x80,0xdb,0xac,0x85,0xd5,0x57,0x9e,0xf0,0x9d,0x53,0x1d,0x7e,
+  0x51,0x1c,0xbc,0xff,0x68,0x36,0xff,0x86,0xad,0x74,0x4f,0x50,0xbc,0xde,0xd7,0x2d,
+  0xbd,0x47,0xdf,0xd1,0x6b,0x87,0xbc,0xb5,0x52,0xa5,0xb1,0xd7,0x5f,0xd5,0xef,0xdd,
+  0x81,0xef,0x1f,0xbd,0x6a,0xc8,0xbb,0xc3,0x5a,0x38,0x0b,0xbf,0x23,0x46,0x53,0xa7,
+  0x8f,0xe3,0x9f,0x7f,0xb1,0x7f,0x52,0xb4,0x72,0x40,0xbd,0x17,0x1d,0x06,0xfd,0xb3,
+  0xa6,0x07,0xb3,0xe5,0xff,0x40,0xaa,0xb1,0xce,0xee,0x87,0xe6,0x2e,0x74,0x18,0x5a,
+  0x1a,0x60,0x03,0x6a,0x99,0xca,0xf7,0xf7,0xa7,0x01,0x91,0xa9,0x21,0xe9,0x9e,0x2c,
+  0xfc,0xc5,0xf9,0xe7,0x6f,0x60,0xb4,0x87,0x30,0xcf,0x8f,0x27,0x6e,0x1c,0x54,0x18,
+  0x99,0xff,0x86,0xca,0xc1,0x8e,0xfb,0xe6,0x4f,0x51,0xd0,0x88,0xde,0xe7,0x7f,0x35,
+  0x83,0xbf,0x52,0xf4,0x09,0x34,0xc6,0xf0,0x1f,0x1e,0xe1,0x7e,0x8b,0xb5,0xee,0x9d,
+  0x0c,0x6e,0xe7,0x22,0x12,0x5f,0x61,0xce,0x46,0x49,0x1d,0x97,0x27,0x63,0x17,0x82,
+  0x91,0xa7,0x46,0x00,0xb5,0xdd,0xe1,0xe0,0x2f,0xe5,0x3c,0x99,0xc2,0x43,0x5a,0x6f,
+  0xdb,0x81,0xb0,0xb7,0x49,0x2d,0x92,0x6c,0x44,0x95,0x3d,0x8c,0x76,0xa3,0xdc,0xe6,
+  0xdf,0x28,0x1f,0x72,0xe5,0x1f,0x1a,0x73,0x7a,0x7c,0x67,0xb2,0xf8,0x37,0xc6,0xd7,
+  0x7f,0x19,0x76,0x8b,0xe8,0x96,0x66,0xce,0x36,0x94,0x9f,0x10,0x9f,0xd0,0x96,0xc1,
+  0x5f,0xc2,0xa8,0xc0,0xd5,0xbe,0xc8,0x59,0x16,0x4f,0x11,0x59,0x2e,0x96,0xc1,0x44,
+  0x69,0x57,0x93,0x3a,0x83,0xd3,0xce,0x8f,0xab,0x85,0x81,0x31,0xb7,0x2e,0x4a,0x34,
+  0x8e,0xe3,0x9f,0xf7,0xf3,0x94,0x30,0x5e,0x85,0x64,0x2e,0x65,0x8a,0x4e,0xfa,0x13,
+  0xa4,0xaa,0x39,0x3f,0x51,0x8e,0x44,0x76,0x55,0x2d,0x63,0x62,0x64,0xe6,0xd6,0xe6,
+  0xce,0x8d,0x0d,0xe3,0xf5,0x97,0x31,0x7c,0xc6,0x89,0x38,0xe4,0xdd,0x76,0xb2,0x22,
+  0x5c,0xa7,0x21,0x2f,0x51,0x54,0x21,0xaf,0x16,0xaa,0xe6,0x67,0x5f,0xa7,0x0b,0xc7,
+  0x6c,0x8a,0x4f,0xc0,0x3f,0x4f,0xbb,0xf4,0x98,0x5d,0xed,0xa5,0x2f,0x54,0x99,0x11,
+  0x0a,0x2e,0x44,0x46,0x44,0x8a,0x8c,0x88,0xd8,0xe2,0x2e,0x16,0x4b,0x9a,0x6a,0x91,
+  0x27,0x9e,0x5d,0xff,0xa5,0xf2,0xaa,0x3a,0xab,0x36,0x07,0xf6,0x5c,0x8d,0x13,0xd9,
+  0x81,0xff,0x9c,0xc3,0x64,0x73,0x9d,0xe9,0x0d,0x38,0xf8,0x2b,0x7c,0xd5,0x3a,0xaa,
+  0x8e,0xd7,0x5f,0x66,0x61,0xaf,0xa6,0x49,0xac,0xfe,0x6b,0x76,0x64,0x21,0xc6,0xbf,
+  0xe6,0x8d,0x86,0xb8,0x61,0xd8,0xa5,0x61,0x2e,0xfc,0x55,0x72,0x00,0xf9,0x0f,0xdf,
+  0x9c,0x90,0xff,0xd0,0x89,0x6d,0xcd,0xe1,0xf9,0x87,0xb7,0x01,0xc8,0xf2,0xd8,0xfc,
+  0xf3,0xbe,0x44,0xf9,0x36,0xf7,0x98,0x1a,0xc0,0x7a,0xea,0x18,0xfc,0x25,0x65,0x61,
+  0x2b,0x3c,0x6c,0xc8,0xb7,0x69,0x37,0x3c,0xbc,0x2b,0xc2,0x13,0x11,0x33,0xc1,0x32,
+  0xf9,0x19,0xda,0x49,0x1b,0xdc,0xf8,0x4b,0xf4,0xba,0xeb,0xbf,0x44,0x14,0x62,0x0e,
+  0xd8,0xf9,0x87,0x7a,0x06,0x76,0x41,0x57,0xbb,0xbb,0x58,0x2c,0x69,0x2c,0xd0,0x72,
+  0x37,0x64,0xd5,0x7f,0xcd,0x73,0xaf,0xe9,0x32,0x46,0xd7,0x8c,0x45,0x5e,0x85,0x37,
+  0x92,0xe9,0x18,0x08,0x73,0xba,0xf8,0x4d,0x22,0x61,0xcb,0x0e,0xe3,0x6f,0xa2,0xea,
+  0xc6,0xdc,0x07,0x1d,0xfc,0xa5,0xb8,0xf5,0xec,0x0c,0x1f,0xaf,0x3a,0x44,0x19,0xc4,
+  0xf2,0x41,0x72,0x48,0xb6,0xa8,0x66,0x76,0x13,0x8b,0xae,0xd0,0x35,0x99,0xe1,0x66,
+  0x5f,0x42,0xdd,0x3e,0xb1,0xfe,0x17,0x2f,0xf2,0x3a,0xeb,0x88,0x02,0xc8,0x63,0x29,
+  0x28,0x33,0x83,0x99,0x34,0xf3,0x82,0xbf,0x74,0xc5,0xbf,0xe4,0x29,0xe3,0x9e,0x41,
+  0x76,0x23,0x19,0xc4,0x84,0xa7,0xd0,0x67,0xd1,0x66,0x2a,0x5e,0x22,0xda,0x85,0x60,
+  0x6c,0x4c,0x18,0x7c,0xb0,0xb6,0xf1,0xfc,0xf3,0x8c,0xf6,0xb0,0x95,0x9d,0xc9,0xec,
+  0xa7,0xe5,0x9b,0x94,0xa4,0x38,0x1b,0x10,0xd9,0xcd,0x09,0xec,0x12,0xd7,0x90,0x1b,
+  0x7a,0x38,0x11,0x87,0x6c,0xe7,0x1f,0x0a,0x4f,0xa6,0x94,0xb4,0xe2,0xce,0x3f,0x1c,
+  0xb7,0x7f,0x3d,0x66,0x4c,0x3b,0x08,0xcb,0x84,0x65,0xe6,0x01,0xbf,0x05,0xcd,0x82,
+  0xac,0xcc,0x5c,0x73,0xd5,0xba,0x56,0x9c,0x54,0x34,0x72,0xfb,0xf8,0xfa,0x2f,0x81,
+  0x1b,0x45,0x9b,0xc9,0xd3,0xca,0x54,0x33,0x70,0xd7,0xfc,0x84,0xb2,0xa3,0x82,0xd5,
+  0x7f,0x21,0xdb,0x7c,0x45,0x8c,0x95,0x23,0xd5,0x50,0x07,0xa3,0x55,0xa6,0x95,0x66,
+  0x71,0xb9,0x1b,0x7f,0x55,0x66,0xf8,0x0f,0x7d,0xf8,0xee,0x1d,0x44,0x6c,0xb5,0x58,
+  0xfa,0x25,0xf9,0xc3,0xe9,0x5b,0x62,0xab,0x90,0x91,0x1e,0xf3,0x0f,0x99,0x22,0xb3,
+  0x13,0x11,0xbb,0xc4,0x0b,0xc1,0xbe,0x3e,0x2e,0xff,0x30,0x2b,0x81,0xe7,0x5a,0xd3,
+  0xa7,0x15,0x37,0x01,0x34,0x9b,0x65,0x38,0xa7,0xfa,0x3e,0x56,0xa9,0xe4,0x9c,0xd3,
+  0x92,0x3d,0xc8,0xdd,0x17,0x77,0xc5,0xbf,0x32,0xfa,0x5f,0x2c,0xfe,0x15,0x81,0x96,
+  0xee,0xc1,0x82,0x11,0xf1,0x5f,0xe0,0x4f,0xeb,0x75,0x5f,0x4f,0x39,0x9e,0xe1,0xcf,
+  0xae,0x58,0x38,0x52,0x8c,0x40,0xcc,0xe6,0x3f,0x4c,0xed,0x38,0xbd,0xf0,0x15,0x89,
+  0x64,0xf3,0x1f,0xb2,0xa9,0x83,0x4d,0x0a,0x65,0xbf,0x26,0x93,0xfd,0xc9,0xb2,0x21,
+  0xe5,0xee,0x22,0x42,0x7f,0x95,0xac,0x24,0x3e,0xce,0x3f,0x1f,0x48,0xe6,0x63,0x0c,
+  0x71,0x17,0x9d,0x69,0xcd,0x4f,0xe8,0xe6,0x5e,0xe5,0x2b,0xd2,0xd7,0x1d,0xfe,0x43,
+  0xb7,0xfe,0x17,0xbb,0xe0,0x64,0xb2,0x53,0x2f,0xeb,0xf3,0xb4,0x88,0x1b,0xc9,0x2a,
+  0xb9,0xd2,0xc0,0x03,0x49,0x70,0xbf,0xcb,0x88,0x62,0xd1,0x4b,0x5a,0x79,0xf8,0x2d,
+  0x65,0x7d,0x4a,0x4b,0x2e,0x99,0x90,0xff,0x90,0xd7,0xad,0x33,0xaf,0x92,0xb1,0x92,
+  0x3e,0x42,0xbc,0x86,0xcd,0xbb,0x42,0xf2,0xb2,0xf6,0xaf,0xdd,0xb4,0x22,0xad,0x5c,
+  0x23,0x46,0xf9,0xf3,0xce,0xe2,0x5f,0x62,0xd6,0x3c,0x5f,0x17,0x84,0xc9,0x0c,0xf7,
+  0x16,0xe0,0xd3,0x74,0x5c,0x9c,0x42,0x55,0xab,0xce,0x8e,0x78,0x53,0xc2,0x99,0x0c,
+  0x1f,0xf5,0x79,0x3d,0xdc,0xfb,0xd4,0x46,0xd5,0xc2,0x5f,0xed,0x63,0xe2,0x5f,0x76,
+  0x6e,0x21,0xc0,0x64,0xad,0xf1,0x0d,0xec,0xd2,0xb0,0x05,0xb5,0x87,0x0c,0xd7,0xbf,
+  0x35,0x09,0xae,0x63,0x00,0x6a,0xd3,0xda,0xd2,0xe3,0xf9,0x0f,0x11,0x76,0x71,0xe3,
+  0x22,0xe9,0x1e,0xca,0x4f,0x34,0x7e,0x99,0x62,0xb4,0x8b,0xa1,0x2d,0x40,0x0a,0x84,
+  0xd5,0x7f,0x1d,0x70,0xe2,0x32,0x85,0x3b,0x4c,0x78,0x15,0x10,0x17,0xfe,0x12,0x9d,
+  0x90,0xc4,0x2c,0x0e,0x97,0x7a,0xf8,0xfb,0xe7,0x06,0xd2,0x29,0x56,0xb5,0x2c,0xe0,
+  0x5d,0x41,0xdd,0x93,0x15,0xbf,0xd8,0x63,0x6c,0x8f,0x29,0x9b,0xc5,0xe4,0x84,0xf5,
+  0x5f,0x96,0x0f,0x09,0x7e,0x38,0xc9,0xdb,0x20,0xfe,0x35,0x46,0xbb,0x52,0x36,0xb2,
+  0xd3,0x95,0xec,0xeb,0x90,0xad,0xe9,0x68,0x76,0xfc,0x4b,0x08,0xf2,0x3c,0x61,0x58,
+  0x8b,0x7e,0x76,0x4e,0xd2,0xcd,0x39,0x1f,0x64,0xb1,0x8d,0x54,0x50,0xb6,0x3a,0x35,
+  0x46,0x50,0xb9,0x9d,0xad,0x97,0xdf,0x5a,0xdc,0x6e,0xf2,0xd3,0x34,0x20,0xb2,0x78,
+  0x86,0xff,0xf0,0xc2,0x12,0xf0,0x8d,0x9f,0x66,0xb5,0xf6,0xe1,0x53,0xc8,0xc3,0x20,
+  0x8f,0xe8,0x61,0x05,0x09,0x8a,0x8d,0x23,0x65,0xe0,0x5d,0x58,0xfc,0xf3,0x0a,0x27,
+  0x52,0x08,0x44,0x06,0xd8,0x84,0x7f,0x80,0xe7,0xe1,0x54,0x22,0x56,0xfc,0xeb,0x1a,
+  0x98,0xc3,0xd9,0x08,0xb2,0x38,0x09,0xdb,0x8b,0x56,0x0e,0x67,0xbd,0xe6,0x83,0x7d,
+  0x87,0x5e,0xd0,0xea,0xe9,0xa4,0xb3,0x3c,0x22,0x96,0xeb,0xe3,0xbc,0xf1,0xf5,0x87,
+  0x31,0x28,0x29,0x5f,0x26,0x07,0xe8,0x22,0x53,0x1a,0x12,0x1d,0xfc,0x75,0x89,0x30,
+  0x25,0x2f,0x06,0xc4,0x8c,0x02,0x3b,0xb7,0xd0,0x87,0xb1,0x2d,0x70,0xc9,0xd3,0x3e,
+  0xb3,0x78,0x84,0x1c,0xa7,0xd5,0xd6,0x63,0x45,0x8a,0xad,0xc1,0x3c,0xa6,0xe9,0xc2,
+  0x5f,0xbb,0x29,0x32,0x96,0x60,0xb4,0xeb,0x81,0xaa,0x5e,0x8f,0x13,0xff,0x4a,0x14,
+  0xe9,0xa5,0x7b,0xc0,0xc8,0xdb,0x04,0x6f,0xfe,0x4e,0x27,0x46,0x86,0x13,0xce,0xea,
+  0xbf,0xe8,0xf4,0xb4,0x12,0xca,0xc6,0x5f,0x31,0x1a,0xb5,0xf2,0x01,0x8c,0xe9,0xae,
+  0x02,0x49,0x45,0x5e,0x2f,0xc2,0x12,0x10,0xd8,0xdd,0xdb,0x08,0x97,0xb7,0x66,0xd4,
+  0x88,0x76,0x3d,0xac,0x19,0x18,0x13,0xff,0xf2,0xaf,0xb1,0xd6,0x34,0x98,0xb6,0x6e,
+  0x92,0x02,0x53,0x4d,0xc4,0xa7,0xe3,0xee,0x19,0xbb,0x8e,0x1a,0x83,0x99,0x70,0x67,
+  0x17,0x9d,0x7e,0x82,0x0f,0xa6,0xd3,0xcd,0x8e,0xae,0xb8,0x8b,0x7f,0x7e,0xb4,0x3f,
+  0xac,0x7b,0x2d,0xbc,0xd3,0x5d,0xc5,0xf1,0x32,0xdc,0xfc,0x0f,0xa9,0x55,0xf8,0x38,
+  0x7c,0x00,0xe8,0x66,0xc8,0xc8,0xa4,0x1d,0x52,0xd4,0x3b,0xe6,0x86,0xe9,0xdd,0x27,
+  0xb9,0xea,0xbf,0x86,0x61,0xe6,0xab,0xad,0x58,0x89,0x8b,0x6d,0xe3,0xa4,0x74,0x31,
+  0x07,0x95,0x1a,0xf2,0x5f,0x92,0x5e,0x17,0xb1,0xe5,0x7a,0xf6,0x38,0xe4,0xd4,0x25,
+  0xad,0xfa,0x2f,0x78,0x06,0x47,0x5c,0xf8,0x4b,0x38,0x4f,0x42,0x0e,0xc9,0x06,0xad,
+  0xb4,0x1f,0x46,0xef,0x46,0x69,0x3b,0xec,0x83,0xe1,0x01,0x35,0xd9,0x76,0x48,0x77,
+  0x18,0x39,0x60,0x8f,0x5b,0xef,0xb5,0xe2,0xd4,0x87,0xbc,0x3b,0x55,0x8b,0x7f,0xc3,
+  0x84,0xe7,0x62,0x8f,0x07,0xb5,0xf3,0x78,0x7d,0xe5,0x70,0x3e,0xaf,0xed,0x42,0xed,
+  0xe9,0xa2,0x1b,0x9b,0x7a,0xfc,0x7e,0x53,0x6a,0x8f,0x9f,0x26,0x9d,0x82,0x9d,0xc3,
+  0xa9,0x30,0xa6,0x1a,0x1c,0x53,0x7d,0x52,0x99,0x6d,0xc7,0xbf,0x86,0x60,0xff,0xea,
+  0xe2,0x4a,0x5e,0x47,0x39,0xf9,0x8c,0x65,0xa4,0x95,0x9d,0x71,0x4a,0x92,0x31,0x9d,
+  0x4a,0xc1,0xdc,0xde,0x4c,0x46,0x47,0x57,0x2c,0xb8,0x2c,0x73,0xb4,0x58,0xea,0x19,
+  0xc9,0xe0,0xaf,0xa7,0xf1,0xcd,0xb6,0x32,0xf7,0x55,0x6d,0x57,0x6b,0xe5,0xeb,0xb7,
+  0xf1,0x98,0xcb,0x37,0xd2,0x4a,0xa9,0x58,0x64,0x3e,0x93,0x00,0xb4,0xb5,0xf8,0xea,
+  0x5f,0xb2,0x74,0x38,0xc6,0x61,0xfb,0x34,0xca,0x01,0x5b,0x31,0x32,0xc4,0x0e,0xdf,
+  0xce,0xc4,0xbf,0xba,0xc8,0x4c,0x33,0x68,0xf3,0xcf,0x57,0x5a,0xc6,0x41,0x6f,0x48,
+  0x8a,0xd3,0xb3,0x24,0xd4,0xe7,0xd3,0x8b,0x7b,0xc5,0xe7,0xa8,0x05,0xcd,0xce,0x1a,
+  0x75,0x69,0x7b,0x70,0x9f,0x57,0xef,0x7c,0xd9,0xcd,0x7f,0x38,0xa7,0xcf,0x87,0x49,
+  0xbd,0xb0,0x28,0x47,0x17,0xd9,0x34,0x29,0xd5,0x2f,0x09,0xc3,0xcd,0x23,0x32,0x23,
+  0xba,0x39,0xc7,0xe2,0x95,0x12,0x3e,0x68,0xa3,0x24,0xa3,0x08,0xd6,0x57,0x7d,0x5a,
+  0x4a,0xb8,0xea,0xbf,0xf0,0x4e,0xe0,0xa7,0x8e,0x6e,0x76,0x14,0x4c,0x8b,0x3a,0xc2,
+  0xb2,0xc1,0xd5,0x15,0xae,0xb2,0x41,0x7c,0xcc,0xf9,0x98,0x3a,0x78,0x1f,0xba,0xf1,
+  0xd7,0x4e,0x97,0x88,0x8c,0x19,0x70,0x36,0xa0,0x01,0x51,0x13,0xe3,0xb8,0xcb,0x20,
+  0xdd,0xee,0xaf,0x9c,0xb2,0x2f,0x39,0x33,0xb8,0x3f,0xc3,0xbf,0x81,0xf8,0x2b,0x95,
+  0x11,0xf9,0x0a,0xbe,0x1e,0x70,0xe2,0x8c,0x8b,0xc5,0x5c,0xfd,0x01,0xe8,0xba,0x26,
+  0x20,0x16,0xe8,0x30,0xcf,0xa7,0x2d,0xd8,0x95,0x51,0x04,0xc3,0x79,0x76,0xe1,0xaf,
+  0x14,0x61,0xf9,0xf3,0x8c,0x27,0xe7,0xa4,0xb3,0xa6,0x6a,0xb1,0x58,0xae,0x53,0x5d,
+  0x1f,0x56,0x05,0xb1,0x5a,0x7b,0xc4,0x96,0xe7,0x4b,0x19,0xc9,0x41,0x67,0x4c,0x47,
+  0x86,0xff,0xb0,0x90,0xd5,0x7f,0x6d,0x0f,0x22,0xc9,0x3c,0x3c,0x05,0xa9,0xa0,0x4d,
+  0x44,0xef,0x3b,0xa3,0xce,0xd6,0x8e,0x99,0x35,0xa9,0xfc,0x33,0xd2,0x1c,0x4c,0xac,
+  0x75,0x68,0xe7,0x29,0xe7,0xdf,0x40,0x44,0x36,0xa8,0xba,0xf1,0x17,0xdd,0x27,0x72,
+  0xb6,0x0d,0x40,0x5b,0xff,0x60,0xd1,0x6e,0x20,0x11,0x7d,0x9a,0x0c,0x6b,0x11,0xd9,
+  0x27,0xb7,0x9d,0x9e,0x08,0xa3,0xc1,0xe0,0x6a,0x92,0x5d,0xff,0x15,0x31,0xaa,0x2c,
+  0x31,0xa3,0x0c,0x4d,0x01,0xac,0xd7,0x8f,0xc9,0xa1,0x44,0xf8,0x76,0xdf,0x26,0x69,
+  0x9a,0x7e,0xc8,0xa1,0x7a,0x50,0x6a,0xed,0x31,0x75,0xc6,0xc2,0x4d,0xe5,0x6e,0xfc,
+  0x95,0xe0,0xdc,0x1a,0xb2,0x4d,0x8e,0xc1,0xf4,0x97,0x99,0xda,0xf2,0xea,0x34,0x23,
+  0xe2,0x98,0xea,0x4a,0x17,0x34,0x6d,0xfe,0x0d,0x52,0x75,0xa7,0x92,0x1d,0xff,0x42,
+  0x8e,0x7a,0xab,0xab,0xc1,0x51,0x7d,0x82,0xeb,0x3c,0xc5,0x09,0xf1,0xfe,0x45,0x9c,
+  0x9a,0x91,0x18,0xeb,0x0a,0x4c,0xe7,0xd7,0x41,0x9d,0xf4,0xc0,0x77,0xc7,0xc6,0xbf,
+  0x6c,0xf2,0x87,0x68,0xc0,0x41,0x01,0x85,0xa2,0x4c,0x79,0x15,0x92,0x47,0x6e,0x70,
+  0xd2,0x0e,0xb1,0x58,0x2c,0x60,0x93,0x75,0x04,0x8a,0xb2,0xf4,0xbf,0x02,0x11,0x4f,
+  0x81,0xcd,0x5f,0x17,0xa4,0x8d,0x96,0x23,0xfd,0x93,0xb6,0x27,0x8c,0xfe,0x00,0x78,
+  0xcb,0x71,0x2c,0x04,0x73,0xe6,0x79,0x79,0xad,0xc7,0x09,0x64,0x78,0x73,0x8a,0xdd,
+  0xf1,0x2f,0xc1,0x16,0xf9,0x92,0xea,0x9b,0x32,0x4e,0xfb,0xcb,0xd2,0x39,0xe3,0x12,
+  0x39,0x60,0xb0,0x8d,0x0c,0xb1,0x30,0x0b,0x2f,0x5e,0xd1,0xad,0xc1,0x57,0x50,0xac,
+  0x39,0x0b,0x7f,0x5d,0x22,0x05,0xf6,0x12,0xd4,0x1b,0x6b,0x1d,0xb4,0x85,0xfa,0x5f,
+  0x97,0xc8,0x0c,0x6e,0x1c,0x22,0x53,0x32,0xb0,0x6b,0xa1,0x3d,0xc6,0x3b,0x20,0x4d,
+  0xcb,0xc2,0x5f,0x54,0x61,0xd9,0xe9,0x62,0x15,0x29,0x75,0x01,0x31,0x5d,0xe6,0xa5,
+  0x61,0x57,0x63,0x24,0xd4,0xc9,0x51,0xb4,0xf9,0x37,0x44,0x54,0x90,0xf4,0x64,0xc7,
+  0xbf,0x32,0x20,0x2b,0xe0,0x42,0x5b,0xb2,0xdc,0x25,0xe8,0x48,0x32,0x2f,0xbb,0xd3,
+  0x3b,0x33,0x88,0x0c,0xf7,0x2f,0x77,0xfc,0x8b,0x3a,0x74,0x2b,0x41,0xc3,0xb5,0xee,
+  0x71,0xb8,0x25,0xda,0xfd,0x51,0x06,0xbb,0x1e,0x75,0x32,0x5a,0xa9,0x7f,0x31,0x1f,
+  0xa3,0x31,0x8d,0x30,0x77,0xfc,0x2b,0xc9,0xb4,0x29,0x39,0x10,0x0b,0x64,0xee,0x67,
+  0xb5,0xc2,0x1c,0xed,0xef,0x6e,0xf6,0x21,0x6b,0x22,0x9e,0x27,0x70,0x02,0x79,0x33,
+  0x6c,0x65,0xd8,0x9a,0x11,0x83,0xf1,0x1f,0xba,0xf1,0x57,0xb4,0xda,0x42,0x5b,0x0d,
+  0x6e,0x90,0xf5,0x66,0x19,0x23,0xa2,0xd7,0xda,0xfa,0x32,0x42,0x60,0x67,0x65,0x26,
+  0x04,0xc6,0x9f,0x0b,0xdf,0x98,0xfa,0xaf,0x3a,0xcd,0xae,0xca,0x14,0x72,0x32,0x40,
+  0x0c,0x1e,0xcf,0x93,0x19,0x1a,0x58,0xfb,0xfe,0xa1,0x61,0x27,0x10,0xa6,0x7b,0xbd,
+  0x59,0xfa,0x5f,0x42,0x15,0x97,0xfd,0xda,0x43,0xaa,0x13,0x95,0x16,0x10,0xdb,0xaa,
+  0x0e,0x16,0x8d,0x56,0x3c,0xfc,0x4a,0x15,0x35,0x5e,0x67,0x40,0xcc,0x0e,0x7b,0x59,
+  0x1a,0x61,0x96,0xfe,0xb2,0x67,0x0c,0xfe,0xf2,0x58,0xfe,0xc6,0x70,0x5e,0xe8,0x0e,
+  0x04,0x59,0x41,0xd4,0x2d,0x7d,0x8e,0x50,0x33,0x68,0x10,0x39,0x57,0xc8,0x94,0x39,
+  0x60,0x99,0x9e,0xa3,0xeb,0x0a,0x0b,0xe7,0xaa,0xff,0xda,0xa5,0x20,0xf7,0x6c,0xee,
+  0x29,0x65,0x97,0x58,0x39,0x70,0x23,0x7f,0xf7,0x7e,0x03,0xf9,0x37,0x7e,0x49,0x1e,
+  0x24,0xd5,0x4b,0x15,0x72,0x75,0x21,0x8b,0x91,0xb1,0xf7,0x73,0x17,0xb1,0xf8,0x37,
+  0x90,0x1a,0x11,0x8c,0x2c,0xfe,0xf9,0x3a,0x4e,0x3b,0xff,0x87,0xd6,0xfa,0x74,0xa5,
+  0x03,0xc4,0x16,0x4b,0x1f,0x88,0x27,0xda,0xe7,0xa6,0x17,0x46,0xd5,0x70,0x26,0x23,
+  0xf1,0xf7,0x34,0x64,0xf3,0x6f,0xcc,0x8d,0x79,0x4b,0xdd,0xf5,0x5f,0xa3,0xac,0x4e,
+  0xa1,0x78,0x2c,0x6f,0x58,0x42,0xe2,0xfa,0x5f,0xd5,0xf8,0xe4,0xba,0xba,0xf6,0xdb,
+  0x46,0x9d,0x91,0x89,0x7f,0x19,0x56,0xfd,0x97,0x97,0x49,0x7a,0xb5,0xd7,0xeb,0x55,
+  0x8e,0x7f,0xd8,0x2f,0x85,0xc9,0x45,0x4c,0x94,0x5a,0x5d,0x3c,0x8b,0x1c,0x6f,0xab,
+  0x67,0xb4,0x00,0xc6,0x25,0x18,0x9c,0x6f,0x8d,0x89,0xad,0xed,0x2f,0x76,0xc7,0xbf,
+  0xc8,0x96,0x3e,0x5b,0xa4,0x92,0x3a,0x1b,0x99,0x6a,0x16,0x1b,0xc6,0xcc,0x54,0xd9,
+  0x41,0xf5,0x3e,0x51,0xd3,0xc0,0x4f,0xe8,0xcb,0x63,0xc7,0x86,0x71,0xdd,0x01,0x59,
+  0x9a,0x62,0xd8,0xf1,0x2f,0x85,0xf1,0x6f,0x94,0x33,0xe9,0x6a,0x05,0xa7,0xce,0xe3,
+  0x5c,0xa7,0x59,0x6c,0x26,0x3b,0x8d,0x1b,0x4d,0xd8,0x77,0x34,0xae,0xbc,0x06,0x5d,
+  0x25,0x4f,0x1b,0x36,0xce,0xd5,0x60,0x9e,0xb5,0xb8,0x9c,0xc1,0x5f,0xf6,0x52,0xca,
+  0x3b,0xa4,0xaa,0x3e,0x0b,0x5c,0xc3,0x2a,0x7f,0x5f,0x9c,0x07,0x7b,0x81,0x6e,0x4a,
+  0x44,0x14,0x8c,0x36,0x4e,0x24,0xc5,0x70,0x37,0x38,0xc4,0xb8,0xee,0xb1,0x20,0x09,
+  0x94,0xda,0xfc,0x87,0x0c,0x7f,0x19,0xe1,0x74,0xc0,0x9a,0xde,0xe6,0x2a,0x67,0x9e,
+  0xd7,0x4a,0x7f,0x67,0x7c,0xd3,0xa8,0x35,0xd5,0x7d,0xb7,0x7f,0x96,0xed,0xef,0x9d,
+  0x08,0xa0,0x46,0x49,0x68,0xc8,0x59,0x8b,0xe0,0xa6,0xac,0xf8,0x97,0x5c,0xe7,0x2c,
+  0x53,0xfc,0x1f,0x9c,0xeb,0xb4,0x7e,0xe9,0xdd,0x12,0x3c,0x37,0xf6,0x4d,0x97,0x5e,
+  0x8c,0x3b,0x39,0xa5,0xa3,0x0e,0x10,0xa3,0xcc,0x18,0xcc,0xe0,0xaf,0x0b,0xdb,0xeb,
+  0xd1,0x33,0x67,0xae,0x48,0x73,0x90,0x1b,0xd7,0x63,0x02,0xcf,0x64,0xd8,0x46,0x6b,
+  0x5e,0x2f,0xe8,0x85,0x87,0xfa,0xe7,0x82,0x05,0xc4,0xce,0x9a,0x35,0xaf,0x5b,0x83,
+  0x67,0xe1,0xfb,0x50,0xcf,0xe8,0x2f,0xef,0xa6,0x16,0x27,0x06,0x4a,0x2a,0xdb,0xda,
+  0xca,0x48,0xda,0x50,0x45,0x3b,0x07,0xfc,0xe9,0x87,0xdb,0x1b,0xa6,0x8b,0x8e,0xff,
+  0xbc,0x27,0x66,0xf1,0xd7,0x81,0xb3,0x7d,0x27,0x3c,0x17,0x65,0xd9,0xf8,0xcb,0xbe,
+  0x4e,0xc2,0x36,0x0c,0xb5,0x03,0xd6,0x74,0x7b,0x93,0xbf,0x4f,0xdd,0x28,0x56,0xe9,
+  0x4e,0xf9,0xcf,0x6e,0xe2,0xef,0xb7,0xc6,0x4c,0x33,0xc6,0xe4,0x1f,0xf2,0x37,0xe4,
+  0x98,0xf0,0xb4,0x5a,0xea,0xcf,0x83,0xe9,0xd3,0xcd,0x23,0x21,0x8f,0x97,0x3c,0x26,
+  0xae,0xe0,0x01,0x9a,0x2e,0x25,0x60,0x2e,0xb7,0xc6,0x20,0x19,0x85,0xe8,0xe0,0x2f,
+  0x76,0xd4,0xb0,0xd9,0xba,0xd5,0xfb,0xbc,0xa9,0x2f,0x9d,0xd1,0xf6,0xf2,0x3a,0x3b,
+  0x5d,0x5c,0x1e,0x00,0x7f,0x2c,0x0e,0xef,0x9f,0x77,0x4a,0x32,0x32,0x40,0xb6,0xcf,
+  0x36,0x0b,0x77,0x99,0xac,0xfa,0xaf,0xb1,0xa4,0x79,0xdc,0x28,0x1e,0xa6,0x58,0xe4,
+  0x35,0xa5,0x77,0xfe,0x30,0x79,0x8d,0xd4,0xf7,0x33,0x7f,0x7e,0x34,0xa7,0xde,0x8a,
+  0x45,0x8a,0x6c,0x6f,0xca,0x8e,0x7f,0x19,0xa5,0x1c,0x52,0xd5,0xf3,0x34,0x51,0x34,
+  0x0a,0xd0,0xb8,0x40,0x32,0x7a,0x6d,0xfd,0x8b,0x3e,0x28,0xae,0xa3,0x56,0xb1,0xd8,
+  0x30,0x39,0x4a,0x9f,0x4e,0x2f,0x1c,0x2a,0xcf,0x8e,0x7f,0xc5,0x18,0xa4,0x7a,0x7f,
+  0xa0,0xfa,0x9c,0xe7,0x92,0x78,0xc0,0x38,0xd0,0x5c,0xfd,0xef,0xca,0x25,0xff,0x01,
+  0xe3,0x7d,0xf3,0xe6,0x73,0xea,0x25,0xe9,0x0a,0x59,0x67,0xde,0x30,0x88,0xb9,0x4f,
+  0x86,0x15,0x2c,0x7b,0x53,0xfb,0x29,0x6a,0x6a,0x6f,0x17,0x33,0xf8,0x4b,0x81,0x19,
+  0x8b,0x71,0x37,0x1e,0x00,0x6f,0x34,0x54,0xe4,0x95,0x77,0x08,0x01,0xf3,0xf6,0x90,
+  0x06,0x4b,0xa0,0x21,0x43,0x11,0x40,0xe0,0xc7,0x8c,0xa0,0xd9,0x89,0x13,0x6e,0x09,
+  0x34,0x20,0x83,0x0a,0x43,0x01,0xdd,0x59,0xf1,0x2f,0xfb,0x96,0x98,0x86,0xf9,0x75,
+  0x3c,0x22,0xd6,0xc1,0x0c,0x21,0x97,0x87,0xbd,0x7e,0x20,0x4c,0xe3,0x09,0xa8,0x16,
+  0xee,0x7e,0x8f,0x3c,0x89,0x28,0x72,0x9f,0xcd,0x3f,0x0f,0xf8,0x0b,0xd7,0x2b,0xe6,
+  0xe4,0x51,0x7b,0x39,0x89,0x4d,0x2d,0x5c,0x50,0x65,0x07,0x1d,0xb0,0x4c,0x0d,0x67,
+  0xac,0x58,0xbf,0x80,0x5d,0x55,0x18,0xe2,0xff,0x2d,0x39,0x42,0x9f,0xf9,0xc0,0xdb,
+  0xa3,0xd2,0x0c,0xfe,0x3a,0x20,0xc3,0x4e,0xc4,0xa3,0xc0,0x73,0xdd,0xfa,0x5f,0x6d,
+  0x17,0x2d,0x69,0xb0,0x2f,0xa1,0xf1,0x9d,0xac,0x35,0x45,0xcd,0x5f,0x94,0x53,0x93,
+  0xbe,0x99,0x15,0xff,0x3a,0x58,0x90,0x91,0xfd,0xb2,0x72,0xd5,0x58,0x44,0x15,0xab,
+  0x87,0x10,0xd1,0x03,0xfe,0xaa,0x35,0xd7,0x85,0xb2,0x72,0x0f,0x74,0xb8,0x91,0x9e,
+  0x96,0xb2,0xf5,0x97,0x07,0x14,0xce,0x7f,0x78,0x83,0xad,0xff,0x55,0x9e,0x56,0xbe,
+  0x2d,0xd6,0x81,0x1b,0x5f,0xdf,0xdb,0x39,0x9c,0xfb,0x1f,0xda,0xcf,0x15,0x1f,0x74,
+  0xc1,0xf7,0xe1,0x22,0xef,0xb8,0x28,0xe2,0xac,0x2f,0x2b,0x37,0x09,0xff,0x94,0xc1,
+  0x5f,0xa8,0xba,0xeb,0x71,0x1e,0x07,0x6e,0xf8,0x4d,0x46,0x7f,0xd7,0xc6,0x54,0xf0,
+  0x1a,0x5e,0x94,0xdb,0xa8,0xe2,0x1c,0x1b,0xa2,0xd1,0x47,0xba,0x0d,0x98,0x67,0xdd,
+  0xe6,0xdf,0x60,0xf1,0xaf,0xf6,0x4a,0xbf,0xe2,0xc0,0x01,0x1e,0xed,0xd2,0x87,0x94,
+  0x95,0xf1,0x08,0xf9,0x1e,0xfd,0xbb,0x34,0x46,0x6a,0x6c,0x8d,0xb0,0x1f,0x09,0xbb,
+  0x38,0x77,0xdf,0x2f,0xc9,0x33,0xe4,0x06,0x54,0x7c,0xba,0x3f,0x2b,0xfe,0x65,0x14,
+  0xd8,0xf8,0x8b,0xfd,0xa3,0x17,0x68,0xe8,0xbd,0xfc,0x10,0xcc,0xcf,0x73,0x34,0x68,
+  0xfa,0x66,0xdf,0x71,0xb4,0xe4,0x39,0x79,0xf6,0x99,0x45,0xd8,0xf5,0x21,0x80,0x47,
+  0x00,0x62,0x7d,0xe4,0x42,0x28,0x84,0xe7,0x3f,0xae,0xfc,0xc3,0x0b,0x5a,0x3d,0x51,
+  0xf1,0xcc,0xea,0x3b,0xc6,0xac,0x13,0x3e,0x1e,0xff,0x3a,0xd0,0x07,0xc6,0xbb,0x78,
+  0x7c,0x74,0x70,0xc1,0x39,0xe9,0x14,0xcf,0xeb,0xfe,0xbd,0x74,0x71,0x19,0xcf,0x3f,
+  0x84,0xf5,0xba,0x80,0x64,0xf5,0xeb,0xc7,0xc4,0xbf,0x08,0xbf,0x7f,0xb0,0xbc,0xa5,
+  0x4b,0xfa,0x99,0x71,0x44,0x8b,0xbc,0x00,0xc6,0x0a,0xe3,0x42,0x0b,0x52,0xf1,0x20,
+  0xe5,0x2c,0xef,0x7a,0xcf,0x06,0x62,0x8c,0xa3,0x1e,0x6f,0xb6,0xec,0xfc,0x43,0x7e,
+  0xa6,0xb7,0x4b,0xaf,0xec,0xbf,0xee,0x1e,0xf1,0x28,0xfd,0x15,0x18,0xea,0x3d,0xd2,
+  0x5d,0x74,0x57,0xa0,0xf2,0x28,0x3b,0xf7,0xfb,0x1d,0x6b,0x11,0x4f,0x99,0xb8,0x01,
+  0xf9,0xb0,0x48,0x19,0xf3,0x0f,0xb7,0xb7,0x64,0xe7,0x1f,0x06,0xf5,0xdb,0x00,0xe7,
+  0x66,0xe6,0x79,0x15,0xb5,0xa2,0x8a,0x18,0x79,0x5c,0xb0,0x72,0xda,0x29,0xc3,0xea,
+  0x3a,0x46,0x57,0xd9,0xfc,0x1b,0x98,0xa3,0x18,0x18,0xc3,0xbf,0x11,0xd4,0x95,0xac,
+  0x75,0x7f,0xc4,0x66,0x8b,0x72,0x18,0x8a,0x30,0x10,0x66,0x1f,0x20,0xf3,0x8c,0x8e,
+  0xbd,0x86,0x9f,0x96,0x86,0xe2,0xae,0xfc,0x43,0xac,0xe4,0xca,0x77,0x60,0x57,0x92,
+  0xf1,0xc1,0xde,0xcf,0xd5,0xbe,0x5c,0xd4,0x88,0xbc,0xec,0x4b,0xb4,0x80,0xd8,0x79,
+  0xba,0xdf,0xac,0x89,0x07,0x07,0xdb,0xce,0x67,0xc5,0xbf,0xbc,0x59,0xe7,0xea,0x93,
+  0x33,0xf8,0xcb,0x0e,0x84,0x0d,0x65,0xa8,0x11,0x23,0x64,0x0a,0x18,0x1a,0xcb,0x51,
+  0x1c,0xc3,0x7f,0x58,0x17,0x75,0xc3,0x2e,0xcb,0xd8,0x24,0xc9,0xc2,0xa1,0x64,0x88,
+  0xbb,0xfa,0x2f,0xb1,0xd0,0x58,0x23,0x2f,0x0d,0x5b,0x84,0xb1,0x80,0x57,0xf2,0x6a,
+  0x8d,0x82,0xf5,0xe5,0x59,0xfc,0x1b,0x08,0x97,0xfc,0xae,0x98,0xd4,0x28,0xb9,0xbf,
+  0x19,0x60,0xd7,0x36,0xe5,0x89,0xe4,0x2c,0x80,0x66,0xc5,0xed,0xf2,0x6a,0xea,0xb7,
+  0xf9,0x0f,0x6d,0x6d,0xe5,0x7e,0x7f,0x33,0xf8,0xcf,0x63,0xea,0xbf,0x1c,0xf7,0xfb,
+  0x3a,0xae,0xf1,0x54,0x75,0x67,0xe7,0x77,0xc5,0x0a,0xe1,0x51,0xdc,0xa4,0x12,0xe2,
+  0x36,0xf9,0x51,0xdd,0xcf,0xf3,0xd0,0xac,0xeb,0x9c,0x21,0xab,0x5b,0xab,0x9a,0x3d,
+  0xd9,0xfc,0x87,0x82,0x0d,0xbb,0xac,0x20,0x17,0xdd,0x12,0x0a,0x2c,0xbc,0xae,0x48,
+  0x6c,0xa7,0x5d,0x7a,0x05,0x46,0xc4,0x1e,0xa4,0xad,0x7a,0x32,0xfa,0x17,0x8c,0x1a,
+  0xd1,0x0e,0x96,0xb5,0x92,0x0a,0x04,0x11,0x2e,0xfe,0x0d,0x9c,0x3a,0x84,0x1e,0x0a,
+  0x9f,0x67,0xc4,0x20,0x46,0x95,0xc6,0x12,0x35,0x37,0x31,0xd9,0xa6,0xcf,0x25,0x4b,
+  0x4e,0x92,0x7b,0xb2,0xf3,0xc7,0xc4,0xfe,0xe6,0xba,0x92,0x02,0x77,0xfd,0x17,0x22,
+  0xa0,0x26,0x57,0xfd,0x17,0xe3,0x3f,0x8c,0x2c,0xf4,0x15,0x4a,0x83,0x77,0xbe,0xc5,
+  0x5a,0x1a,0xb7,0x61,0xfc,0xeb,0xd6,0x75,0xac,0x8b,0x87,0x5a,0xce,0x35,0xbd,0x4b,
+  0xe6,0xe0,0x5b,0x34,0x2b,0xfe,0x05,0x48,0x2a,0x51,0xec,0x04,0x71,0xac,0x96,0xe6,
+  0x46,0xae,0xf6,0x05,0xeb,0x85,0x42,0xcc,0x63,0x63,0x64,0xef,0x92,0x1d,0xc6,0xc2,
+  0x81,0x72,0x37,0xff,0x86,0x5c,0x45,0x64,0x1e,0xce,0xab,0xb2,0x7e,0x17,0xa9,0x25,
+  0xd3,0xb1,0x3a,0xb8,0x07,0xfc,0x77,0x0f,0x1a,0xdb,0xc9,0xfd,0x36,0xfe,0xb2,0x88,
+  0x10,0x3b,0x04,0x96,0x91,0x78,0xcc,0xa5,0xbf,0x2c,0x20,0xb7,0x46,0x11,0xd6,0x7f,
+  0xb9,0x02,0x61,0x79,0x0c,0x7f,0x01,0xda,0x2a,0xd5,0x72,0x5d,0xf8,0x0b,0x07,0x5b,
+  0x31,0x32,0x1d,0x2b,0x83,0x5e,0xce,0xc9,0xe0,0x2f,0xa1,0xaa,0xe5,0x36,0x4e,0x72,
+  0x58,0x65,0xdc,0x8e,0x8b,0xfb,0xa8,0xe0,0x37,0xf2,0x12,0x9e,0x6d,0x36,0x24,0xdf,
+  0x46,0x9e,0xcc,0x08,0xc9,0x71,0x43,0x5f,0x6d,0xe8,0x46,0xc7,0x06,0x87,0x7f,0xa3,
+  0x90,0xfd,0xe4,0x98,0x5d,0xb4,0x08,0x63,0x2c,0x23,0x5f,0x93,0x2a,0xac,0x08,0x2f,
+  0xa3,0xdd,0xa8,0xca,0x9a,0x9f,0x37,0xc9,0x5b,0x03,0xe1,0x95,0xde,0x8d,0xc2,0x90,
+  0x1b,0x7f,0xd5,0x19,0x55,0x89,0xc6,0xec,0x40,0x58,0xc3,0xc3,0xe3,0x9f,0x14,0x6e,
+  0x30,0xd2,0x8f,0x3e,0xcc,0x05,0x6d,0x86,0x67,0x67,0x0c,0xff,0xe1,0xa2,0xcc,0xbd,
+  0x51,0xee,0x94,0x0d,0xc6,0xf8,0xa9,0x08,0x61,0xfc,0x1b,0xb3,0x9c,0x40,0x18,0x17,
+  0x55,0xef,0x37,0x6b,0x43,0xde,0xf6,0x2c,0xfe,0xc3,0x9c,0xea,0x24,0x0b,0x7b,0xed,
+  0x21,0xd3,0x5a,0x11,0x64,0x29,0x7b,0x48,0x7d,0x22,0xff,0x74,0x43,0x80,0xec,0x3f,
+  0x0d,0x3e,0x62,0x72,0xd2,0x4a,0xf2,0x6a,0x88,0x87,0xbd,0xe4,0x35,0x2c,0x6f,0x59,
+  0x1c,0x12,0x1f,0x26,0xe5,0xb4,0xe3,0xad,0x31,0xfc,0x87,0x69,0x5e,0x92,0x9c,0xe1,
+  0x55,0xab,0x42,0xfa,0x85,0x85,0x78,0x5a,0x88,0x09,0x4e,0x51,0xa3,0xd5,0x60,0x1c,
+  0x1d,0x59,0xb1,0xfe,0x80,0xa9,0xcc,0x1c,0xc3,0x7f,0x78,0x50,0x6d,0x11,0xdd,0x04,
+  0x7d,0xa1,0x00,0x51,0x9a,0xc4,0xc9,0xf2,0xd3,0x3c,0x52,0xd3,0x4f,0xbe,0xcb,0xc3,
+  0x5e,0xaf,0x0a,0x16,0x40,0x38,0x8a,0x42,0x60,0x86,0xd2,0x1c,0x1f,0xc7,0x7f,0xc8,
+  0xf6,0x41,0xa7,0xec,0xab,0x32,0xa6,0x44,0xa5,0xaf,0x02,0xda,0x62,0x5d,0x5f,0x25,
+  0xbd,0x9c,0xff,0xf0,0x58,0x06,0x88,0x1d,0x6f,0x9d,0x93,0x04,0x20,0xf6,0x36,0xb1,
+  0xf1,0x97,0xfc,0x2d,0x21,0x42,0xff,0xa7,0xe5,0x3a,0xc2,0x9e,0xc2,0x09,0xdf,0x8c,
+  0xcf,0x62,0xb6,0x21,0x20,0x68,0x84,0x66,0xcb,0x1d,0x19,0x29,0xd1,0xca,0xdb,0x59,
+  0x61,0x47,0xc4,0x0e,0x5a,0xf5,0x17,0x32,0xf3,0x0f,0x97,0x79,0x47,0x8a,0x2f,0x1b,
+  0xdf,0x49,0xcc,0xe1,0xf1,0xaf,0xe3,0x74,0x8e,0xee,0x8b,0x5e,0x77,0x59,0x79,0x9f,
+  0x7b,0x83,0x2f,0x93,0x17,0x13,0x73,0x38,0xff,0xe1,0x15,0xc0,0x8c,0xeb,0xd0,0x99,
+  0x7c,0x8f,0x32,0xfd,0x65,0x1b,0x7f,0x69,0x9b,0xc9,0x0e,0x9a,0xdf,0xc7,0xf7,0x77,
+  0xa2,0x0f,0xb1,0x89,0x6a,0xd3,0xf4,0xc2,0x02,0x03,0xf9,0xb5,0xd8,0xfc,0x48,0x03,
+  0xf4,0xdf,0x13,0x33,0x87,0x16,0xb4,0x48,0x58,0x1f,0x77,0xcb,0x10,0x9b,0xc3,0x55,
+  0x5a,0x35,0x0d,0xb4,0xb8,0xf4,0xbf,0xd8,0xf4,0x22,0xff,0xfc,0xda,0x1d,0x42,0x3e,
+  0xe6,0x8b,0xde,0x05,0x8b,0x72,0x23,0xea,0xb0,0xac,0xa5,0xd6,0xcc,0x9f,0x20,0x0f,
+  0x90,0xb2,0xfe,0xbc,0x16,0x9e,0x87,0xcf,0xf3,0x0f,0x01,0xf9,0x12,0x00,0x6b,0xb9,
+  0x96,0x9e,0x38,0xdf,0xbf,0x3a,0xb2,0x73,0x33,0xda,0xe0,0xf1,0xf4,0x10,0x71,0xad,
+  0xbd,0x91,0x99,0x64,0x3d,0xef,0x5a,0x48,0xac,0xbc,0x1d,0xa6,0xd1,0xfc,0xa6,0xa7,
+  0x62,0xac,0xfe,0x97,0xab,0xd6,0x63,0x3e,0xe3,0x3f,0xa4,0x70,0xd3,0x3e,0x65,0x4f,
+  0x6f,0x3f,0xe9,0xe5,0xd3,0xeb,0xd4,0x17,0xbc,0x8b,0xc9,0x30,0xc3,0x05,0x4e,0xfe,
+  0x61,0x82,0xb0,0xd8,0x96,0xed,0xce,0x31,0x22,0x7a,0x76,0xe5,0x04,0x5e,0x47,0x7b,
+  0x8b,0x77,0x6d,0x27,0xa3,0x0d,0x4e,0xee,0xd3,0x7d,0xcc,0xd0,0xc1,0x03,0x31,0x04,
+  0x37,0xfe,0x92,0xaf,0xe0,0x59,0x0a,0xfa,0x6c,0x7f,0x60,0x21,0x12,0x00,0xe0,0x7f,
+  0x20,0x37,0x1b,0xb0,0x3a,0xdf,0x26,0xbf,0xe7,0xf9,0x87,0x23,0xe4,0x45,0x2c,0x0d,
+  0x4b,0x65,0xfc,0xcc,0x33,0x98,0x0d,0x4e,0xbd,0xc3,0xad,0x19,0xfc,0x25,0x80,0x7f,
+  0xa8,0x5f,0x67,0x05,0xa7,0xd0,0xbd,0x44,0xb5,0x2f,0x7f,0xda,0x97,0x07,0xde,0xf2,
+  0x6e,0x3a,0xab,0xb7,0x00,0xc9,0xc1,0x5e,0x31,0xb1,0x0b,0xc6,0xfc,0xc0,0x01,0x50,
+  0x66,0x15,0xe9,0xa8,0x74,0xf1,0x6f,0x68,0x7b,0xa5,0xaa,0x25,0x4e,0xfc,0xcb,0x62,
+  0x1d,0x9f,0x96,0x54,0xdb,0xc5,0x15,0x64,0x6f,0x07,0x8b,0x88,0x3d,0x49,0x3a,0xa8,
+  0xdf,0x5c,0x9d,0x5d,0x07,0xd4,0x81,0x1c,0x1d,0xf1,0xa4,0x0b,0x7f,0x85,0x9c,0xfa,
+  0xaf,0xc0,0x2b,0x79,0x48,0xea,0xd5,0x66,0xe8,0x09,0x58,0x2f,0x2f,0xed,0x36,0x2a,
+  0x4c,0xcf,0x4c,0x78,0x59,0x24,0x02,0x81,0xa3,0x0c,0x3b,0x3c,0x62,0x04,0x79,0xfe,
+  0x61,0x0d,0x82,0xfd,0x54,0x83,0x2b,0xfe,0xc5,0xd0,0x1f,0x4c,0x1d,0xdd,0x4b,0xc2,
+  0x27,0xf3,0x39,0xf9,0xf9,0x2c,0x4d,0xa5,0xd2,0x0a,0xba,0xdb,0x08,0xf3,0x79,0x3e,
+  0x4c,0x8a,0x7e,0x9d,0x6f,0x85,0x2d,0x2c,0x20,0x26,0x30,0xf1,0xa9,0xa4,0x8b,0xff,
+  0x30,0x56,0x4f,0x30,0x17,0xd4,0x80,0x09,0xe7,0xb9,0x85,0xdf,0x21,0xf5,0x1d,0x3e,
+  0x13,0x16,0x17,0x89,0x02,0x0a,0x3e,0x80,0x79,0x1e,0x76,0x42,0x2d,0xa2,0x35,0x86,
+  0xa9,0x1a,0xc5,0xa4,0xe5,0x6e,0xfc,0xc5,0xf4,0xbf,0xce,0xc1,0x32,0xed,0xe6,0xdc,
+  0xf2,0xef,0x23,0xbf,0x68,0x8b,0x9a,0xe2,0x07,0x1d,0x14,0xd9,0xe6,0x49,0x37,0xea,
+  0xb5,0x5d,0xc6,0x35,0xe5,0x81,0x30,0x3c,0x5a,0x5c,0x3b,0xe0,0xe6,0x3f,0x44,0x31,
+  0x35,0xc0,0x5f,0x6f,0x2b,0x7b,0xe3,0x7e,0x1e,0x2b,0xe9,0x44,0x90,0x95,0x12,0xa7,
+  0x73,0x46,0x8e,0x04,0x67,0x9b,0x37,0x02,0xdb,0x59,0x68,0xcc,0xca,0x3f,0x84,0x96,
+  0x25,0xb0,0x5b,0xe9,0x2e,0xfe,0x0d,0x92,0xe4,0x38,0xb7,0x8b,0x04,0x08,0x53,0x9f,
+  0x47,0x19,0x44,0x8f,0x2e,0x12,0xfe,0x86,0xd4,0xc5,0xa3,0xb6,0xda,0x17,0x7b,0x76,
+  0xf8,0x01,0xfb,0x1e,0xce,0x1d,0xea,0x77,0xe3,0x2f,0xfd,0x20,0x7c,0x8d,0xf7,0x49,
+  0x0f,0xdd,0x6a,0x7d,0x1f,0xb6,0xb8,0x64,0x3a,0x5b,0x65,0xa9,0x47,0x3c,0x23,0xf4,
+  0xc0,0x6e,0xa5,0xb4,0xb2,0xb0,0xd7,0x34,0x6b,0xdd,0x2b,0x60,0x70,0x47,0x7c,0xb6,
+  0x9b,0x7f,0x23,0xdc,0x02,0x33,0xff,0x3b,0x70,0xe3,0xf7,0xbc,0xc5,0xb0,0xf0,0x3b,
+  0xc8,0x2f,0x9a,0x90,0x9e,0xe4,0x4f,0xd3,0x4f,0xfd,0x67,0xc8,0xf9,0x86,0xf0,0xb0,
+  0xd2,0x81,0x61,0x65,0xe5,0x27,0x56,0x10,0x39,0x16,0x0e,0x7b,0xf7,0x49,0x24,0x2b,
+  0xff,0xb0,0xaf,0x1a,0x6f,0xf5,0x8f,0x94,0x67,0xcd,0x6a,0x87,0x17,0xf4,0x2c,0x2c,
+  0x93,0x45,0x4a,0x09,0x8f,0x8c,0x56,0x3f,0x04,0xee,0x25,0xa6,0xe3,0xce,0xb1,0x16,
+  0x4e,0x9e,0x4b,0x00,0xac,0x65,0xe5,0x1f,0x86,0x4f,0xb2,0x2c,0xee,0x43,0x06,0xc7,
+  0xe6,0x94,0x7d,0x0d,0x22,0xdd,0xc8,0x4b,0x6e,0xb7,0x72,0xf5,0xa8,0xfe,0x82,0x7f,
+  0x51,0x83,0xe4,0x03,0xc3,0xd6,0x5f,0x46,0x16,0xbe,0xa7,0x24,0x17,0xff,0x21,0x3c,
+  0x56,0x1c,0x7f,0x75,0x20,0x05,0xe5,0xb3,0xbc,0x3e,0x0e,0x26,0x21,0x1e,0xe0,0x46,
+  0x8f,0x27,0xc8,0x55,0x84,0xe2,0xf0,0xc4,0xed,0x11,0x1d,0xc5,0x6a,0x7f,0xab,0xb2,
+  0xcd,0x5d,0xff,0xb5,0x37,0x0a,0x4f,0x01,0x42,0xaa,0xd6,0x84,0x7e,0xab,0x32,0x9b,
+  0xc5,0x97,0x61,0x99,0x6a,0xc5,0x76,0x66,0xe4,0xc9,0x28,0xbb,0x1c,0xd3,0x5b,0x3c,
+  0x58,0x20,0xe9,0xe8,0x18,0x76,0x13,0x7d,0x9e,0xa2,0xc5,0x43,0x6e,0xfe,0x8d,0x40,
+  0x3a,0x8a,0x90,0xaa,0x9d,0x96,0xb5,0x04,0x56,0xc6,0xed,0xfa,0x2f,0x63,0x03,0x37,
+  0xfe,0x12,0x00,0x42,0xf7,0xda,0xb2,0x98,0xb2,0x1c,0x8c,0x67,0x79,0x81,0x12,0x92,
+  0xa8,0x97,0xb5,0x28,0x8b,0xe1,0x7d,0x98,0xe1,0xdf,0x20,0x21,0x0a,0xf8,0xab,0x4f,
+  0xec,0x25,0xa1,0x26,0xaf,0x05,0xc4,0x4c,0x9f,0x2e,0xb4,0x23,0x34,0x33,0xf3,0x57,
+  0xb7,0x79,0xc1,0xf1,0x48,0xc4,0x0a,0x34,0xcc,0x3f,0x4c,0x86,0x78,0x65,0xeb,0x07,
+  0x38,0xb8,0x08,0xf0,0x97,0xc3,0xbf,0x61,0x51,0x1a,0x9e,0x23,0x17,0xb5,0x03,0x2e,
+  0x50,0x7c,0x56,0x6a,0x61,0x61,0xaf,0x45,0xa6,0x64,0xa9,0x03,0x98,0x3c,0xf4,0xdc,
+  0x67,0x15,0xbd,0xd6,0xcf,0xab,0x36,0xb3,0xf9,0x37,0xba,0x69,0x30,0xc5,0x93,0x73,
+  0xe6,0xb9,0x13,0x42,0x2a,0x34,0x87,0x10,0x78,0x14,0x65,0x77,0x6c,0x68,0xcf,0xf2,
+  0x0a,0x60,0xbd,0x04,0x70,0x60,0x3c,0x6e,0xfe,0x8d,0x72,0xb3,0x92,0x53,0x1a,0x6e,
+  0x31,0x16,0x38,0xe7,0x7e,0x2d,0x9e,0x12,0x5b,0x80,0x12,0x5b,0x6e,0x32,0x00,0xd5,
+  0xba,0xea,0xbf,0x76,0x88,0x65,0x44,0x6d,0x16,0x8b,0xdc,0xfc,0x1b,0x65,0xc9,0x00,
+  0x97,0x54,0x76,0x38,0x4c,0x6e,0x4c,0x7b,0x96,0x8b,0x45,0xbc,0xfc,0x39,0x5a,0xf4,
+  0xaa,0xd2,0x15,0x2f,0x4b,0xe7,0x2d,0x16,0x5d,0xa4,0x28,0xa8,0x11,0xa6,0x2a,0x76,
+  0xfe,0xbc,0xc5,0x7f,0x08,0x28,0xbb,0xe1,0x98,0x99,0x92,0xf5,0xb4,0x3b,0x91,0x43,
+  0x02,0xc3,0x6b,0xaa,0x0f,0x62,0x8b,0x81,0x94,0x10,0x1e,0x27,0xa3,0x1e,0x5b,0x92,
+  0x04,0xae,0x73,0xad,0x9b,0x7f,0x83,0x85,0xb4,0x46,0x61,0x32,0xf7,0xa6,0x2c,0x6e,
+  0x8d,0x5a,0xe4,0xf2,0xb9,0x85,0xe3,0xaf,0xc1,0xb6,0x21,0x61,0x3f,0xa9,0xd9,0x9e,
+  0x9f,0x46,0xd9,0xaf,0xb4,0xc5,0x51,0x7f,0x39,0x51,0xde,0xaa,0x0e,0xa9,0xb5,0x59,
+  0xfc,0x1b,0x1a,0x77,0xe7,0xf2,0x00,0x88,0x39,0xc5,0x47,0x60,0xd0,0x11,0xc1,0x96,
+  0x7c,0x55,0x2c,0x46,0xc4,0x61,0xc5,0xe2,0x85,0x18,0xd6,0x22,0x21,0xdf,0x43,0x52,
+  0x16,0xff,0x86,0x15,0x02,0x38,0x4b,0x9f,0x41,0x1f,0xf2,0x0d,0xf2,0x4d,0x2c,0x8a,
+  0xd9,0x24,0x39,0xec,0x0d,0xcb,0x08,0xaa,0x81,0x00,0x52,0xe0,0xc4,0x0e,0x76,0xbe,
+  0x56,0xcc,0xf7,0xa8,0x24,0xba,0xf8,0x37,0x0c,0x7f,0x4b,0xc0,0x2e,0xc5,0x52,0xbf,
+  0x1b,0xff,0x1d,0x07,0x47,0x9b,0xc5,0x0a,0x57,0xda,0x98,0xe1,0xbf,0x53,0xb5,0xe4,
+  0xba,0x32,0x49,0x86,0xd9,0xfa,0xcb,0x5d,0x24,0xc9,0xc9,0xea,0xf7,0x36,0x4f,0x8b,
+  0x76,0x26,0xc4,0x37,0x38,0x33,0x43,0x21,0xee,0x83,0xd6,0x75,0x30,0x23,0x71,0x00,
+  0x9e,0x5c,0xf7,0x75,0xc8,0xd6,0x26,0xb5,0x44,0x2c,0xc8,0xe2,0x3f,0x6c,0xe2,0xa1,
+  0x16,0x5d,0x8f,0xa9,0x85,0x4e,0xfc,0xcb,0x23,0x73,0xb4,0x15,0xe6,0x2a,0x54,0x4d,
+  0x18,0x08,0x73,0xe9,0x02,0xeb,0x7a,0x14,0xf5,0x97,0x33,0xfc,0x1b,0xf0,0x4a,0xb9,
+  0x16,0xb1,0x55,0x72,0x84,0xcc,0xf2,0x60,0x21,0x8f,0xc1,0xe6,0x79,0x5a,0x1b,0x97,
+  0xb1,0xf3,0x3d,0xa0,0x82,0x11,0x08,0x69,0xbe,0x38,0xb6,0x04,0xba,0x9d,0xfa,0x1d,
+  0xba,0xe8,0x81,0x46,0x77,0xfe,0xa1,0xff,0x00,0xd6,0x0a,0x9d,0x53,0x2e,0xe1,0xf3,
+  0x65,0x17,0x79,0x2d,0xc2,0xf8,0x17,0x9b,0xe7,0x97,0x24,0x16,0x23,0x8b,0xfa,0xb0,
+  0x6e,0xeb,0x92,0x9d,0xea,0x76,0x49,0xab,0x67,0xf1,0xaf,0x0c,0xff,0xc6,0x25,0x4e,
+  0x7b,0x68,0xa7,0x14,0xc2,0x03,0xcb,0xb2,0x43,0x87,0xed,0xf5,0x1a,0x90,0x2a,0x94,
+  0x67,0xa1,0xeb,0x7f,0x0d,0x64,0x56,0x10,0xff,0xad,0x9a,0x79,0xbe,0xec,0xf8,0x97,
+  0xc8,0xb8,0x35,0x86,0xb4,0x1e,0xf2,0x53,0x92,0x29,0xfb,0x4a,0x8a,0x01,0xd2,0x23,
+  0xfc,0x3d,0x1a,0x98,0x76,0x98,0x24,0xd7,0x25,0x9d,0xfc,0x43,0x46,0xb9,0xef,0x27,
+  0x0b,0x88,0x58,0xe0,0xe6,0xdf,0x00,0x04,0x64,0xc7,0xb6,0x38,0x11,0xa2,0xc8,0xe3,
+  0x5f,0x4e,0x20,0xcc,0xee,0x72,0x8b,0x02,0x50,0x68,0x29,0xf5,0x14,0x59,0xfc,0x1b,
+  0x2c,0xff,0x30,0xc9,0x70,0x37,0xdd,0x4d,0xa7,0xa3,0xec,0xd7,0xa0,0x1d,0x2d,0x75,
+  0xdf,0x3f,0xd4,0x1f,0x85,0x6d,0xd4,0x69,0xc1,0xbf,0xf2,0xc7,0xe0,0x41,0xcb,0x75,
+  0xf3,0x6f,0x84,0x2d,0xfc,0x75,0x3a,0x1c,0x63,0xf8,0x8b,0xcd,0xcf,0x46,0x75,0x2a,
+  0x67,0xec,0xdf,0x88,0x6a,0x5f,0x34,0xbc,0x54,0xdd,0xec,0xa9,0xb0,0xd2,0x05,0xf9,
+  0xfd,0xbc,0xdc,0xe7,0xc4,0xbf,0x2c,0xfe,0x0d,0x2e,0x01,0x70,0x36,0xbb,0xc8,0xab,
+  0xd3,0x32,0xae,0xc1,0x2e,0x25,0x12,0xf3,0x69,0x6d,0x3c,0x88,0xcc,0xc7,0x1c,0xdc,
+  0x0f,0x46,0x36,0xff,0xc6,0x56,0xf0,0x89,0xb0,0xda,0x2b,0xca,0xaa,0xbd,0x5e,0xe7,
+  0xf7,0x8f,0xac,0x96,0x59,0x69,0xab,0x6d,0x08,0xed,0xc3,0x9a,0xb7,0xbd,0x31,0x83,
+  0xdf,0x51,0x11,0xac,0xc8,0x4b,0x55,0xd1,0xc5,0x7f,0x48,0xcb,0x13,0x9c,0x52,0xbe,
+  0xa9,0x9a,0x2a,0x67,0xc4,0xf3,0xc4,0xe2,0x9f,0x0f,0x60,0x81,0x24,0x55,0xcf,0x00,
+  0xa8,0xd9,0x6f,0x7c,0x76,0x3b,0x74,0x21,0x34,0x73,0x92,0x15,0x1f,0x4b,0x44,0x87,
+  0x44,0x57,0xfc,0x6b,0xaf,0x1d,0xd2,0xea,0x32,0x82,0x69,0x25,0x02,0x98,0x9a,0xbd,
+  0xc7,0xea,0x6c,0x76,0x65,0x99,0xbd,0xb5,0xc0,0x4f,0xc8,0xae,0xff,0x22,0xfa,0xef,
+  0x95,0x3a,0x77,0xfc,0xeb,0x19,0x65,0xcb,0x41,0x85,0xd1,0xce,0x8b,0xc1,0x61,0xa5,
+  0x25,0xce,0x85,0x1a,0xd5,0x7b,0xe1,0x19,0x5c,0x65,0xbf,0x9f,0x77,0x90,0x1b,0xd3,
+  0x4a,0x2c,0xee,0xae,0xff,0xc2,0x7f,0xbd,0x25,0xae,0xcb,0x36,0xfe,0x92,0x2f,0xb7,
+  0xd6,0xa4,0x17,0xb2,0xd8,0x56,0xfb,0x5c,0x8c,0x6d,0xfd,0x92,0x23,0xb2,0xd9,0xaa,
+  0x45,0xc4,0xc1,0xcb,0xbe,0x66,0xe8,0xc1,0xc5,0x8d,0xae,0xfa,0x2f,0xd4,0xff,0x82,
+  0xc1,0xfe,0x4c,0xfc,0xeb,0x3c,0xcc,0xd0,0x24,0x2b,0x56,0xd2,0xcb,0xc2,0x5e,0xce,
+  0x76,0x93,0x31,0x00,0xa3,0xf9,0xb2,0xea,0xbf,0x2c,0xc3,0xc6,0x5f,0xae,0xf8,0x17,
+  0x79,0x91,0xd6,0x9c,0xf6,0x9d,0x94,0xc2,0x76,0xc5,0x4a,0xc4,0x0e,0x84,0x61,0x8e,
+  0x62,0x5d,0x6c,0x6d,0xbf,0x14,0x91,0xaf,0xc0,0x73,0x63,0x25,0x2b,0x5a,0xf5,0x5f,
+  0x6c,0xbd,0x30,0xfe,0xb5,0xdf,0xb0,0x28,0xe5,0x57,0x69,0x65,0x48,0x16,0x54,0xc8,
+  0x27,0xe1,0xac,0x67,0x72,0x6c,0x07,0x16,0x70,0xcd,0xc3,0xd9,0x40,0xa4,0x39,0x0f,
+  0xf6,0xaf,0x1d,0xda,0x16,0xab,0x74,0xae,0xa8,0x8c,0x06,0xee,0x16,0xa7,0x73,0xfe,
+  0x0d,0xc4,0x5f,0xcf,0xd8,0xd2,0x2a,0xed,0x46,0x59,0x1f,0x6c,0x6d,0xd6,0xf6,0x17,
+  0xb3,0x77,0x3d,0xbe,0x0f,0xc2,0x2d,0x21,0xe3,0x75,0x5c,0x3a,0xd7,0x27,0x94,0x98,
+  0xfd,0x5c,0x60,0xfc,0xab,0x1b,0xd5,0x69,0x43,0xe2,0x71,0x14,0xe3,0xbb,0x03,0x9e,
+  0x1d,0xcb,0xbd,0x9c,0x1c,0xcf,0xe7,0x46,0x2e,0xae,0xb2,0x0e,0xde,0x3b,0x78,0xf8,
+  0xae,0xbc,0x53,0xd4,0x86,0x0b,0x89,0xa5,0x19,0xfe,0x0d,0x78,0x52,0x3e,0x90,0x11,
+  0x52,0x1d,0x22,0xa9,0x01,0x5f,0x4a,0x0d,0xb0,0x39,0x54,0xf7,0x49,0xd5,0xec,0xd4,
+  0xda,0xb7,0x8d,0x9d,0x7e,0x47,0xb4,0x8a,0x76,0x54,0x04,0x63,0x5a,0xc6,0x58,0xa8,
+  0x82,0x75,0xd0,0xa9,0xeb,0x5c,0xf1,0xaf,0x51,0xb2,0xff,0x20,0xaa,0x1a,0xf5,0xc3,
+  0x9f,0x9f,0x58,0x94,0x92,0xde,0xe2,0x6b,0xd1,0xa5,0x02,0xc8,0x22,0xb6,0x22,0xb3,
+  0x01,0xcf,0x57,0x9d,0x3b,0x47,0xf1,0x43,0x2d,0xd2,0xec,0xdb,0xd9,0x66,0xe1,0xaf,
+  0x84,0x86,0xd9,0x86,0x30,0xf3,0xe8,0x67,0x9e,0x35,0x61,0x1f,0xc6,0x14,0xb5,0x2b,
+  0x22,0x82,0x2c,0x75,0x32,0x67,0xdb,0x68,0xc1,0x08,0x8b,0x50,0x33,0xdd,0x0a,0xb5,
+  0x38,0x11,0x96,0x90,0xe9,0x0d,0x48,0x2e,0xfe,0x8d,0x9e,0x81,0xad,0x14,0xc3,0x5e,
+  0xca,0xee,0xb8,0xff,0xef,0x94,0xcd,0x62,0x39,0x77,0x0b,0x57,0x17,0x05,0x79,0xd8,
+  0x6b,0x1f,0x86,0x2d,0x4c,0x3d,0x04,0xae,0x63,0x30,0x93,0x5b,0x08,0xc6,0xb7,0x95,
+  0x9d,0xa2,0x8b,0x7f,0x63,0x07,0xf1,0x2f,0xee,0x60,0xd7,0x11,0xb6,0x9e,0x56,0x30,
+  0x5f,0x80,0x5d,0x27,0x84,0x95,0x65,0x98,0xe2,0xf8,0x14,0x6e,0x64,0x1d,0x7e,0x0d,
+  0xde,0xbd,0xec,0x3a,0xbd,0x19,0xb2,0x8e,0x0d,0xd9,0xf1,0x2f,0xdd,0x91,0x9a,0x32,
+  0x94,0x90,0x47,0x71,0x12,0x47,0x35,0xf6,0x9c,0x32,0x37,0x43,0xf2,0xdf,0xc1,0xeb,
+  0xf5,0x0c,0xbd,0xdf,0x7e,0x4e,0x0d,0x00,0x11,0x19,0xfe,0x0d,0xe4,0xab,0xe4,0x21,
+  0xad,0x11,0x21,0x2c,0x78,0x93,0x36,0x28,0xa6,0xc8,0x1f,0x8e,0x68,0x6b,0x8b,0x14,
+  0x54,0xce,0x57,0x84,0x4b,0xbd,0xd8,0x72,0x21,0xe3,0x3f,0x63,0xcd,0x91,0x9b,0xff,
+  0xf0,0x32,0x32,0x93,0xc3,0xd4,0x79,0x2f,0xc9,0x2c,0xa4,0x35,0xe2,0x0a,0x84,0x21,
+  0xff,0xc6,0xc1,0x46,0xe6,0x16,0x2a,0xdc,0x3f,0x24,0x07,0xfa,0xdc,0x81,0x15,0x9b,
+  0x7f,0x23,0xe7,0xb2,0x32,0x4c,0x66,0xdc,0x06,0x8f,0x67,0x15,0x2c,0x1c,0x23,0xad,
+  0x1a,0xa6,0xfb,0x96,0x20,0x81,0x58,0x6e,0x1a,0xf3,0x0f,0x15,0x24,0x23,0xa4,0x98,
+  0x8f,0x0d,0xff,0xc4,0xab,0x00,0xcd,0x66,0xb1,0x62,0x31,0xe5,0x45,0x71,0x86,0xee,
+  0x1d,0xc8,0xf0,0x1f,0x9e,0x11,0xf6,0x9a,0x5b,0x53,0x18,0x4c,0x44,0xda,0xc3,0x61,
+  0xf5,0x59,0x00,0x3e,0x7b,0xb5,0xaa,0x93,0xea,0x3e,0x3f,0x18,0x03,0x55,0x28,0xca,
+  0x56,0x1d,0xed,0x34,0xab,0xce,0xa9,0x4f,0x60,0x98,0x89,0x30,0xfc,0x95,0x26,0x9d,
+  0x02,0x13,0x02,0xb3,0xf5,0xbf,0x90,0x7f,0x63,0x9e,0xde,0x0c,0x5e,0x81,0x17,0x49,
+  0x0e,0x35,0x95,0x80,0x1b,0x9d,0xd2,0x57,0x5c,0xab,0xca,0x0d,0xbd,0x42,0x8a,0x04,
+  0xb5,0xe9,0x72,0x11,0x11,0xa9,0x11,0x24,0xd0,0x75,0x86,0x4b,0xb0,0xe1,0x3c,0xe3,
+  0x39,0xad,0x42,0x1a,0xb2,0xf4,0xbf,0xfc,0x54,0xbd,0x0a,0x25,0x95,0xad,0xa4,0x91,
+  0x24,0x37,0xe2,0xec,0x84,0x53,0x51,0xe8,0x41,0xce,0x27,0x0c,0x5d,0xbc,0x12,0x90,
+  0x91,0x64,0xae,0x96,0xa7,0xc5,0x02,0x5b,0x0f,0x0e,0x67,0xf2,0x0f,0xf7,0xe1,0xb6,
+  0x8e,0xfc,0x09,0x23,0x14,0x5e,0x56,0x1b,0x61,0x4f,0x39,0xff,0xfd,0x48,0xb7,0x6f,
+  0x9b,0xf8,0x46,0xe8,0x42,0x2a,0xf2,0x81,0x37,0x51,0x5e,0x65,0x1c,0xe9,0xaf,0x1a,
+  0x54,0xe3,0x52,0x1f,0x66,0x56,0x63,0x20,0xec,0x8c,0x79,0x44,0x9f,0xa5,0x7b,0x37,
+  0x36,0xba,0xf9,0x0f,0xe5,0xef,0x50,0x46,0x0d,0x74,0x41,0x83,0xfd,0x6b,0x1b,0xea,
+  0x38,0x4b,0xf0,0xec,0x3c,0x0a,0x0f,0xda,0xc5,0xd6,0xb9,0x65,0xbe,0xaf,0xc3,0x64,
+  0xb2,0xd3,0xf8,0x9d,0x2c,0xec,0xc5,0x48,0x6c,0x30,0x23,0x71,0x8e,0xe1,0xdb,0x24,
+  0x5e,0x74,0xf0,0x17,0xaa,0x55,0x36,0x78,0x7f,0xc2,0x9e,0xe5,0xb0,0x01,0xf7,0xcf,
+  0x8d,0x8c,0x34,0x18,0x3c,0x90,0x80,0xc6,0xf6,0xaf,0x6d,0x78,0x7e,0x08,0x00,0x89,
+  0xf1,0x67,0x1e,0xa1,0xd6,0x73,0xda,0xab,0xd7,0xc6,0xbc,0x9b,0x33,0xf8,0xab,0x52,
+  0xde,0xa1,0xcd,0xa2,0xca,0xce,0x38,0xde,0xf3,0x5b,0x8d,0xaf,0x27,0x3d,0x01,0x71,
+  0xb5,0xf8,0x36,0xec,0xf8,0x9e,0x40,0xee,0x76,0x54,0xc0,0xf9,0x57,0xe9,0x6b,0x4d,
+  0x1d,0xc2,0x56,0x12,0x48,0x7a,0x74,0x3b,0x51,0xf3,0x8d,0xd8,0x6a,0xc5,0x1f,0x0b,
+  0x50,0x87,0x7f,0x5e,0xf8,0xbc,0x91,0x1a,0xd0,0x5b,0xa2,0xb3,0xf1,0x9e,0x17,0x00,
+  0x52,0xe9,0xa2,0xa2,0xb4,0xb2,0xdc,0x8c,0x22,0x45,0x4b,0x10,0x58,0xa6,0xb2,0x22,
+  0x62,0x70,0xa6,0x50,0xa6,0x3b,0xc0,0xe3,0x20,0x22,0x35,0xfd,0x34,0x10,0x6a,0xb0,
+  0xe2,0x5f,0x88,0xbf,0x0e,0xd0,0xc7,0xb7,0x02,0x7c,0x9b,0x42,0x76,0xb6,0x97,0x6d,
+  0x03,0x48,0x75,0xb5,0xf1,0x20,0xad,0x4c,0x76,0x2c,0x01,0xe3,0x7b,0x89,0xca,0x41,
+  0x75,0xb1,0xf8,0x55,0x79,0x15,0x56,0x2a,0xdd,0xe6,0x8f,0x18,0x56,0xc8,0xe6,0x97,
+  0x72,0x1b,0x8f,0xcb,0xb8,0xf9,0xe7,0x69,0x28,0xea,0xad,0x95,0x0a,0xcc,0x61,0x2d,
+  0xb4,0xdd,0x5b,0x28,0xc9,0xe4,0x60,0x51,0x05,0xf5,0x96,0x49,0xb9,0xc6,0xbf,0xb1,
+  0x84,0x6a,0xc9,0x6b,0x3c,0x97,0x9c,0x3d,0x08,0x5d,0x60,0xd8,0x35,0x62,0x26,0xe9,
+  0x69,0x0a,0xfa,0x5d,0xf1,0x2f,0xe3,0x02,0x99,0x93,0xac,0xfe,0x80,0xa5,0x4f,0x47,
+  0xda,0x99,0x5f,0x77,0x5e,0x0c,0xd3,0xea,0x34,0x18,0x18,0xaf,0xcc,0xd7,0xa4,0x53,
+  0x25,0x57,0xb4,0x69,0x26,0x78,0x83,0x17,0x0d,0x4b,0x76,0x19,0x07,0xd7,0xf7,0xfa,
+  0x86,0x27,0x65,0xf1,0xcf,0x47,0x38,0xb6,0xfa,0x0d,0xfc,0x5b,0x6b,0x53,0xd2,0x7b,
+  0xe2,0x02,0x12,0x49,0x57,0x39,0x44,0x88,0xd8,0xf5,0x21,0x0d,0xa7,0x83,0x3f,0x03,
+  0x47,0x68,0x01,0xb5,0x9e,0x77,0x24,0xab,0xf7,0x25,0x26,0x4d,0xd7,0x6c,0xfc,0xa5,
+  0xc1,0xe6,0x82,0x69,0x1b,0x98,0x88,0x58,0x49,0x14,0x43,0x34,0x49,0xbb,0x5c,0x69,
+  0xd3,0x1e,0xc2,0xab,0xc9,0x68,0xd0,0xb4,0x9d,0x68,0x14,0xc2,0x96,0xb4,0x8a,0xef,
+  0x3b,0x27,0xd9,0xf9,0x2a,0x38,0x78,0x2e,0xfd,0xaf,0x9d,0x34,0x18,0x53,0xbe,0x2d,
+  0xfe,0x88,0xa7,0x77,0x62,0x20,0xec,0x71,0xcc,0xfc,0xfc,0xb6,0x38,0x45,0x58,0xd5,
+  0x5b,0x36,0x4c,0x66,0x7b,0x00,0x76,0xc5,0x59,0xda,0x61,0x0d,0x12,0x21,0x32,0xfc,
+  0xa5,0x7f,0x97,0x96,0xc5,0xd4,0xc5,0x63,0xea,0xbf,0xa8,0x32,0x33,0xbe,0x16,0x8b,
+  0xf2,0x70,0x63,0x7d,0x55,0x5f,0x95,0xa8,0x44,0x99,0xb6,0xc9,0xfa,0xe3,0x66,0xd9,
+  0xb0,0x32,0xd2,0x00,0x1b,0xa2,0x56,0x76,0x10,0xae,0x2c,0xb1,0xda,0x76,0x58,0xf7,
+  0xf7,0xc5,0xf5,0x8d,0x5b,0x97,0x00,0x2e,0x70,0xe9,0x7f,0x7d,0x80,0x99,0x84,0x67,
+  0x54,0x00,0x62,0x79,0x91,0xe4,0xd1,0xad,0xd2,0x3b,0x58,0x08,0xd6,0x51,0x00,0x37,
+  0x76,0xc7,0x61,0x33,0xdc,0xe5,0xfd,0xf1,0x86,0xcf,0xc6,0xce,0xbf,0x14,0x4e,0x29,
+  0x3f,0x95,0xae,0x13,0x0f,0xa3,0x66,0x62,0x52,0xba,0x40,0x5e,0x05,0x44,0xe6,0x73,
+  0xe5,0x1f,0x9e,0x26,0x17,0x8d,0x7a,0x86,0xb6,0x70,0x09,0x64,0x64,0x3b,0x64,0xfc,
+  0x87,0x8c,0xfd,0xf5,0x94,0x8e,0xaf,0xc1,0x46,0xc6,0x10,0x2b,0xaf,0x3b,0x08,0x88,
+  0xec,0xa4,0xed,0xd7,0x0d,0x95,0x62,0x8c,0xcc,0x55,0xff,0xa5,0x8d,0x96,0x84,0x97,
+  0x2d,0x7a,0x94,0xfb,0xea,0x0d,0x93,0x2c,0x22,0xc4,0x06,0x1f,0xb2,0x5b,0x8c,0xf2,
+  0x34,0xb6,0x76,0xe4,0xeb,0x9e,0xe7,0xc3,0x98,0xcb,0x21,0x81,0xc7,0x0b,0x74,0xeb,
+  0x19,0x74,0xf2,0x0f,0xff,0xda,0xd8,0x9d,0xf4,0x1b,0x0b,0x36,0x58,0xbe,0x71,0x9e,
+  0x1d,0xc8,0xb0,0x18,0xed,0xaa,0x10,0x64,0x4d,0x63,0x04,0xf2,0x3c,0xec,0xc5,0xfd,
+  0xe7,0x37,0xc4,0xd5,0xa6,0x3f,0xa6,0x24,0xa4,0x98,0x3b,0xfe,0x55,0x6e,0x2c,0xd0,
+  0xe0,0x3a,0x7b,0x6d,0xfe,0x43,0x8b,0xed,0xd0,0x31,0xf6,0x91,0x87,0xb0,0x6b,0x20,
+  0xec,0x5c,0x67,0x70,0x4b,0x6b,0x00,0xaf,0x93,0xc9,0x3f,0xf4,0x92,0x67,0x03,0x65,
+  0xb7,0xab,0xc8,0x2d,0xff,0x74,0x45,0x65,0x34,0xef,0x0e,0xf1,0x4e,0xfa,0x74,0xa8,
+  0x72,0x61,0xde,0x1d,0x4b,0x4f,0xd0,0xa7,0xfd,0x95,0xb7,0x35,0x7e,0x20,0x4e,0x4e,
+  0x3c,0xa0,0x57,0x46,0x3b,0xef,0x40,0x22,0x8e,0x84,0x1d,0xff,0xd2,0x61,0xb3,0x2b,
+  0xb2,0xf5,0x53,0x58,0xfc,0x4b,0xaf,0x51,0x7c,0x93,0x54,0xdd,0x95,0xcc,0x69,0x44,
+  0x34,0x57,0xe4,0x51,0x48,0xb2,0xb0,0xc5,0x22,0x53,0x4a,0x8b,0xa6,0x81,0xb1,0x24,
+  0xa9,0xd7,0x30,0x9b,0xc3,0x25,0xe0,0x75,0x67,0xf0,0x57,0x72,0xb7,0xb0,0xdf,0x58,
+  0x84,0xd8,0xca,0x0a,0xfe,0x62,0xfc,0x6b,0xca,0x42,0x5f,0x57,0xf9,0x20,0xea,0xe2,
+  0xb1,0x88,0x58,0xb3,0xc5,0x88,0x78,0x82,0x58,0xfc,0xf3,0xe7,0x9a,0x19,0x58,0x3b,
+  0x9b,0x89,0x7f,0x9d,0x23,0x97,0xb6,0xd7,0x2c,0xf7,0x36,0xb3,0xf5,0xaa,0x99,0xc7,
+  0xa3,0x39,0xc2,0x7d,0x1c,0x91,0xb1,0x45,0x69,0xc6,0xf8,0x97,0x88,0x71,0x46,0x78,
+  0x15,0xbc,0xc8,0x0b,0x94,0x38,0x35,0x7d,0x70,0x58,0xcd,0xca,0x3f,0xf4,0x6b,0x51,
+  0x8c,0xe2,0x21,0xa4,0xca,0xa7,0xe0,0xc6,0x77,0xe4,0x2c,0x25,0x2c,0x23,0x11,0x19,
+  0xe9,0x09,0xc2,0xae,0x35,0xb2,0xc5,0x7f,0x98,0xe4,0x1b,0xc7,0x10,0xe9,0xc8,0xad,
+  0x72,0xf1,0x6f,0x30,0xfc,0x25,0xfa,0x07,0x14,0x4e,0x72,0x98,0x44,0xea,0x2d,0x59,
+  0x6c,0x25,0xdb,0x78,0x22,0xe2,0x16,0x64,0xa4,0xd7,0x3c,0x4d,0x52,0x2b,0xef,0x72,
+  0xf1,0x4c,0xb6,0x61,0xb6,0xa1,0xd6,0xe0,0xce,0x3f,0x44,0xd9,0x82,0x9d,0x78,0xff,
+  0x68,0x2c,0xb8,0x89,0x27,0x19,0xd3,0x0c,0x65,0x3d,0x06,0xb9,0x88,0xbf,0x21,0x9a,
+  0xf0,0x2f,0x23,0xab,0x75,0x96,0xb6,0x3a,0x35,0xc3,0x9f,0xb9,0xba,0x1d,0x79,0x2f,
+  0x9d,0xfc,0xc3,0x42,0x87,0x16,0x72,0x1b,0xe6,0x16,0xb6,0x44,0x37,0x4b,0x37,0x90,
+  0x43,0x7a,0xd5,0x3f,0xad,0xdd,0x2c,0xbd,0x99,0xf3,0x77,0x46,0xf8,0x5e,0xef,0x46,
+  0x61,0x59,0xec,0x90,0x19,0x6e,0x5e,0x98,0x80,0x7b,0x63,0x35,0x9f,0x9f,0xdf,0x89,
+  0xab,0x5b,0x99,0x58,0xb3,0x0b,0x7f,0x9d,0x25,0x0c,0x49,0xc1,0x75,0xe4,0xba,0x96,
+  0xea,0xcd,0xa8,0xb6,0xbc,0x8d,0x0d,0xfe,0x45,0xee,0x59,0x6d,0x5f,0xac,0xfa,0xfb,
+  0xd2,0x83,0xa8,0x82,0xb7,0xac,0xfa,0x1a,0x57,0x8d,0x18,0x45,0x83,0xf1,0x6f,0xd8,
+  0xf8,0x8b,0xf6,0x6b,0xdd,0x02,0x8b,0x96,0x0e,0x1b,0x00,0xb2,0x64,0x66,0x84,0x84,
+  0x85,0xed,0x28,0xd2,0xdd,0x54,0x84,0x2d,0xa7,0x43,0x66,0x4e,0x98,0x4c,0x6a,0x87,
+  0xa7,0xa0,0x5f,0x67,0xfa,0x05,0xa7,0xe3,0xfd,0x34,0x12,0xf2,0xb9,0xe2,0x5f,0xb3,
+  0xc9,0xc3,0xa4,0x2c,0xa1,0x2e,0x97,0x96,0x33,0xfd,0x2f,0x2f,0xc2,0xe4,0x3d,0x3c,
+  0xc9,0x10,0x8d,0xad,0x74,0x76,0x5a,0xbd,0x4f,0x5f,0xc3,0x14,0xb4,0x73,0x87,0xc8,
+  0xab,0x26,0x0b,0x84,0x8d,0xc2,0x5f,0xcd,0x45,0xc3,0x89,0x7f,0x7d,0x9e,0xb4,0x75,
+  0xe8,0x07,0xd5,0x52,0xa6,0x5a,0xb8,0xcd,0xfc,0x2c,0x4f,0xaa,0x41,0x1f,0xdb,0xe3,
+  0x15,0x1e,0x11,0x74,0x4c,0xe4,0x78,0x51,0x7c,0x44,0x4e,0x5b,0x21,0x12,0x1a,0xb0,
+  0xfd,0x0d,0xb6,0x70,0x4e,0xfc,0xeb,0x6a,0xc2,0x92,0xc0,0xd3,0x1b,0xee,0x82,0x3f,
+  0x9f,0x8a,0x7f,0xc5,0x9c,0xff,0x7e,0x65,0xb6,0x85,0x02,0xf2,0x62,0xe2,0x5d,0xe4,
+  0x11,0x30,0xae,0x43,0x8e,0x8e,0xef,0x75,0xb0,0xf7,0xf3,0x09,0x1d,0xa0,0x99,0x01,
+  0x20,0xc2,0x89,0x7f,0xcd,0x12,0x57,0x61,0x49,0xd7,0x72,0x09,0x03,0x61,0x33,0x11,
+  0x5b,0xa1,0x51,0xce,0x89,0x10,0xff,0x40,0x43,0xe9,0xbc,0x16,0xe9,0x18,0xf9,0x15,
+  0x2b,0xfb,0x12,0xbf,0xaa,0xfd,0x82,0xde,0xc2,0x64,0x97,0x49,0x1f,0x00,0xb1,0xff,
+  0xb5,0x38,0xa3,0xff,0xb5,0x4d,0x19,0xcd,0x40,0xaa,0x5a,0x8b,0x76,0xc3,0x0d,0xb2,
+  0x0a,0xf8,0x49,0x72,0xc4,0x09,0x7b,0x99,0x4c,0xd4,0x66,0x04,0x0f,0x00,0x13,0x99,
+  0xfc,0xc3,0xf3,0xe4,0x38,0x56,0x9f,0x0d,0x31,0xb4,0x75,0x73,0x5a,0x65,0x89,0x88,
+  0x1d,0xe5,0x6f,0xaa,0x23,0xe2,0x65,0xe3,0x42,0xa2,0x7e,0xd0,0xf7,0x4d,0xe8,0xb2,
+  0x18,0x11,0x91,0xb1,0xcd,0x3a,0x9f,0x07,0xb0,0x16,0xbb,0xfe,0x2f,0x54,0x27,0xff,
+  0x70,0x23,0xf9,0xd5,0xa6,0x32,0xe2,0x5d,0x22,0xb2,0x44,0xcd,0xf7,0x50,0xbf,0x92,
+  0x1c,0xd8,0x04,0x9b,0x0b,0x18,0xcb,0x77,0xfd,0xb4,0xf2,0x98,0xfa,0x75,0xe9,0x7f,
+  0x34,0xed,0xba,0xa5,0xf2,0x4d,0x46,0xdb,0xfb,0x2c,0x0f,0x14,0x0e,0xfb,0x1f,0x50,
+  0xb6,0x34,0xc1,0xfc,0x38,0xf1,0xaf,0x8d,0xc8,0x21,0xd9,0xa7,0xc4,0x3c,0x99,0xd8,
+  0x96,0xb2,0x4b,0x67,0x83,0xef,0x82,0xed,0x66,0x2a,0xb2,0xfe,0x4e,0x46,0x21,0x30,
+  0x73,0x41,0x4b,0xc3,0x29,0xe3,0x19,0xde,0xc5,0x22,0x62,0x03,0x6a,0xf3,0x56,0x27,
+  0xfe,0xd5,0x47,0x1e,0x31,0xf4,0x84,0x52,0x21,0xb2,0xb3,0xc1,0x01,0x75,0x76,0xee,
+  0xd1,0x7e,0xa6,0x44,0x50,0x8b,0x11,0x16,0x3d,0x88,0x15,0x46,0x9f,0x37,0xa0,0xab,
+  0x1f,0x19,0x11,0x2d,0x91,0x1d,0xd8,0x73,0x5b,0x1b,0xf4,0xb4,0x3a,0xd9,0x1d,0xff,
+  0x3a,0x44,0x9f,0xb9,0xe8,0xdd,0x88,0xfe,0x18,0x8d,0x0c,0xfb,0x7a,0x30,0x3d,0x86,
+  0xd6,0x0c,0xf9,0xf6,0x49,0xe0,0xf7,0x9a,0xd3,0x86,0x61,0x32,0x2b,0x31,0x00,0x31,
+  0xec,0xdb,0x29,0xf2,0x54,0x25,0x56,0x11,0x76,0xa8,0x39,0xbc,0xd4,0xf7,0xac,0x54,
+  0x65,0xc7,0xbf,0xde,0x25,0x67,0xa3,0x75,0x1c,0xac,0x7d,0xe8,0xa9,0xeb,0x5f,0x17,
+  0x7a,0xec,0x28,0xf9,0x50,0xa9,0x3b,0xe8,0x0b,0x15,0x1f,0x55,0x3e,0xc4,0x12,0xb3,
+  0x19,0x6d,0x43,0xf4,0x43,0xc6,0x88,0x98,0x59,0xca,0xa3,0xf4,0x3c,0x7f,0xd0,0x9c,
+  0xfa,0xaf,0x8f,0x60,0xdd,0x6b,0x0c,0x6f,0xba,0xad,0xce,0x2e,0x11,0xaa,0x13,0x8e,
+  0x3b,0xfc,0x87,0x60,0x5c,0x8f,0xf9,0xd8,0xc7,0xc9,0xcd,0x3c,0xc3,0xcd,0xe6,0x3f,
+  0xa4,0xbd,0x1a,0x00,0xb1,0x11,0x29,0x6d,0xe3,0xaf,0x7f,0xa0,0xbb,0xd3,0xfe,0x25,
+  0xd1,0x99,0x0c,0x13,0x75,0x9b,0x81,0x94,0x27,0x38,0xe9,0x37,0xc2,0x56,0x66,0x30,
+  0xda,0xc3,0xcf,0xec,0xf3,0x14,0x10,0xc6,0x7f,0x98,0x82,0x47,0xc6,0xe2,0x3f,0x7c,
+  0x9f,0x76,0x2c,0xf5,0xb7,0xa8,0xeb,0xfd,0x0e,0xff,0x46,0xc0,0x60,0x75,0x49,0x3c,
+  0xc7,0x6c,0x9a,0x19,0x4d,0x15,0x05,0x95,0x27,0x19,0x0f,0x43,0x6e,0x50,0x03,0xe7,
+  0xdf,0x54,0x37,0x8b,0xc1,0x8d,0x4f,0x0a,0x16,0x23,0x62,0xa7,0x6c,0xc5,0xbf,0x3a,
+  0x89,0x3f,0x04,0x46,0x3a,0xb3,0x7f,0x75,0xe9,0x49,0xa2,0xa4,0xa6,0xe3,0xe3,0x19,
+  0xeb,0xb7,0xf9,0x0f,0xe1,0x39,0x85,0x27,0xb7,0xad,0x0c,0x8c,0x70,0x91,0x97,0x3c,
+  0x66,0xc4,0x50,0x53,0x3b,0x48,0xd6,0xdb,0x3a,0x47,0x71,0x58,0x70,0xd5,0xc9,0xdf,
+  0xa0,0xf9,0x06,0x19,0x6d,0x0e,0x1b,0x81,0x9b,0x60,0x51,0x2e,0x90,0x59,0xc7,0x58,
+  0x3e,0xdb,0x93,0x7a,0xb8,0xdf,0x9b,0x12,0x82,0xc6,0x91,0x00,0xac,0x4e,0x02,0x5a,
+  0xde,0x31,0x8a,0x4e,0x16,0xa4,0x0a,0x83,0x98,0x6f,0x73,0x82,0x3d,0x32,0x87,0xc0,
+  0xf1,0x58,0x94,0x6a,0x4c,0xdb,0xf5,0x5f,0x23,0x64,0x14,0xfd,0x0d,0xf0,0x0f,0x93,
+  0x57,0x48,0xe4,0x10,0x2f,0xf2,0xc2,0xdd,0x6a,0xb8,0xf1,0xa2,0x00,0x80,0xb7,0xd7,
+  0xb7,0xb3,0x1c,0x09,0x34,0xee,0x3b,0xc9,0xa8,0xdb,0x2e,0x5a,0xfe,0xa1,0xc8,0x7c,
+  0x92,0xb1,0xf9,0x87,0xb6,0x64,0x5e,0x0d,0x9d,0x74,0x12,0x73,0x0b,0x49,0x7d,0x3a,
+  0x7f,0xc4,0x7f,0x86,0x1c,0x8f,0x57,0x13,0x96,0x6d,0x78,0x11,0xcf,0xd0,0x50,0xff,
+  0x0b,0x0c,0x7e,0xf4,0xf1,0x7b,0xb2,0x03,0x0b,0xc1,0x5c,0xfc,0xf3,0x7b,0x90,0x2b,
+  0x8f,0xd7,0x76,0xf9,0xf5,0xce,0x04,0x97,0x4d,0x41,0x90,0x75,0x14,0x03,0x61,0x3a,
+  0x18,0x4b,0xc9,0x6e,0xb8,0xc3,0x3b,0x3a,0x00,0xa3,0xf5,0xb4,0xa2,0x38,0x97,0x07,
+  0xc0,0x5a,0x3b,0xab,0x1a,0x73,0xe3,0xaf,0x4c,0x7a,0xa7,0x4e,0x61,0xea,0xfa,0x49,
+  0x5c,0x08,0x9a,0xd7,0x84,0x58,0xd9,0xd7,0x0a,0xac,0xb3,0x33,0x05,0x16,0xff,0x42,
+  0x9c,0xdb,0x0d,0xf8,0x0b,0x9e,0x14,0xaf,0xd2,0xcd,0x6b,0x27,0x5d,0xf8,0x6b,0x4f,
+  0x87,0x95,0x77,0xba,0xc3,0x58,0x1a,0xba,0x6e,0x93,0xf8,0x36,0xf9,0x3e,0x75,0x16,
+  0xf7,0x0b,0x5b,0xc1,0x58,0x42,0xad,0x8a,0x42,0xc4,0x68,0x3f,0xe1,0x8c,0x2e,0x7b,
+  0x44,0x7f,0x0a,0xfe,0xca,0xad,0xbf,0x6c,0x44,0x8a,0xac,0x12,0xaa,0x70,0x72,0xdd,
+  0xe6,0xe7,0xde,0x23,0x47,0xfa,0x58,0x16,0xee,0xdb,0x70,0x1f,0x4e,0x49,0xb2,0x6c,
+  0xb1,0xf3,0x26,0xec,0x71,0x18,0x30,0x1a,0x35,0x66,0xf1,0x40,0xf3,0x48,0x7f,0x38,
+  0x04,0x7f,0x35,0x90,0x15,0xff,0x6a,0xae,0x46,0x99,0x80,0x2b,0xda,0x01,0xc2,0x88,
+  0x38,0xde,0xb6,0x18,0x11,0x0d,0x58,0x2f,0x0a,0x0b,0xf7,0x11,0xae,0x69,0x93,0xef,
+  0x36,0x16,0x3b,0xb6,0xe2,0x5f,0x17,0xb5,0x3a,0xc2,0xaa,0xc6,0x6c,0xfc,0x45,0x2e,
+  0x98,0x8c,0x99,0xfc,0x3d,0xfd,0x08,0x09,0x6f,0xf0,0xf5,0x94,0x0f,0x91,0x0b,0xd1,
+  0x6e,0xf6,0x30,0xe2,0xeb,0x34,0x61,0x57,0x0b,0x1a,0xec,0xd6,0x3a,0x6f,0x74,0xf3,
+  0xef,0x73,0xd6,0xf0,0x17,0xb2,0xef,0x63,0xe1,0x2f,0x78,0x1c,0x7a,0xab,0x0c,0x1e,
+  0x16,0xd4,0xfd,0xa1,0x05,0xbb,0xc5,0xb7,0xe4,0xbd,0x8a,0xdf,0x61,0x2c,0xa1,0x6a,
+  0x2a,0x74,0x86,0xf4,0xe8,0xd3,0xd3,0x6c,0x7e,0xf6,0xd8,0x4c,0xa1,0xe0,0x15,0x4c,
+  0x86,0xbf,0xfa,0x28,0x13,0xff,0xea,0x8a,0x55,0x11,0xa6,0x23,0xdf,0x26,0x54,0x24,
+  0x61,0xbd,0x7a,0x75,0x40,0xd0,0xa6,0x14,0x02,0xe7,0x8d,0xc9,0x7e,0x85,0xc0,0x1b,
+  0xdb,0x91,0x06,0x6f,0x90,0x30,0xf9,0x78,0x1d,0xaf,0x83,0x81,0x30,0xc0,0xcb,0x21,
+  0x71,0x24,0x4b,0x7f,0xb9,0x25,0x0a,0xae,0xbe,0xb8,0x8e,0x4e,0x4d,0xaa,0x28,0x50,
+  0xb5,0xd3,0x72,0xfe,0x93,0x80,0xb6,0x74,0x16,0x85,0xb9,0x89,0xde,0xf8,0xb6,0x12,
+  0x00,0x8c,0x96,0xe2,0x5d,0x53,0xc8,0xb3,0x89,0xa9,0xba,0xb2,0xb2,0xe1,0x4c,0x06,
+  0x7f,0x61,0x31,0x02,0x2b,0xe9,0x3a,0x48,0x66,0xc6,0x7d,0x7a,0x63,0x2f,0xee,0xef,
+  0xf8,0xd6,0x3a,0x8c,0x44,0x88,0x06,0x18,0xfd,0x18,0xed,0x5a,0xee,0x25,0x18,0xff,
+  0x32,0x42,0x67,0x60,0x7e,0xbc,0xc6,0x59,0x32,0xd3,0xf0,0x86,0x24,0x57,0xfd,0x17,
+  0x40,0x2a,0x3c,0x45,0x3f,0xa5,0x7c,0x44,0xe6,0x50,0x5b,0xdf,0xc1,0xb4,0x03,0xcd,
+  0x04,0xa3,0x5d,0xe8,0xe1,0x37,0xad,0xc3,0xfa,0xaf,0x4b,0xec,0xf9,0x52,0x31,0xbe,
+  0xbc,0x97,0x8c,0xe1,0xdf,0xa0,0x61,0x56,0xe3,0x0c,0x1d,0x08,0xa9,0xc4,0x37,0xc5,
+  0x57,0x28,0x5b,0x94,0xb4,0x78,0x84,0x67,0x71,0xa7,0x31,0xed,0x90,0xaf,0x17,0xe6,
+  0x1b,0xc3,0x3b,0x3c,0x08,0x6f,0x51,0xf6,0x57,0x2e,0xfd,0xaf,0x03,0x80,0xa4,0x16,
+  0xa0,0xbe,0xcc,0x2e,0x52,0x46,0x71,0x6f,0x02,0xfc,0x55,0x66,0x27,0xb1,0xc0,0x26,
+  0xde,0x72,0xc7,0x09,0xf2,0xef,0x72,0xb5,0xa1,0xc4,0xec,0x73,0x3f,0x24,0x42,0xec,
+  0x22,0x65,0x44,0xcd,0xd2,0xff,0xda,0x85,0x48,0x0a,0x27,0xf3,0xbb,0xad,0x5b,0x92,
+  0x9d,0xcb,0xc5,0x5f,0x56,0x50,0x6b,0x9e,0x89,0x35,0xcf,0x87,0xe5,0x07,0xe9,0x37,
+  0x62,0x9b,0x66,0xb3,0xf8,0x97,0x35,0xcf,0x4f,0x77,0x6c,0xc1,0x2e,0x77,0xfe,0x61,
+  0xae,0xbf,0x59,0x0d,0x15,0x1d,0x37,0x30,0xa6,0xf9,0x57,0x3d,0xb0,0x37,0x51,0x4d,
+  0x77,0xb2,0x0d,0x65,0x30,0x8e,0xeb,0x00,0xc0,0x63,0xa5,0x73,0x70,0x8f,0xeb,0xc0,
+  0x2e,0x78,0x51,0x77,0x99,0x7a,0x08,0xba,0xb2,0xf4,0xbf,0x76,0x3c,0xb5,0x2e,0x29,
+  0x8d,0x18,0x00,0xa9,0xa8,0xef,0x6d,0x69,0x84,0x1c,0xe3,0x6a,0xcb,0xa3,0x0d,0x6b,
+  0x48,0x7d,0x92,0x65,0x1b,0x1e,0x23,0x91,0xed,0xc1,0xb4,0x1a,0x20,0x97,0x93,0xdd,
+  0x3c,0x35,0xf1,0xb2,0x51,0xb3,0x0d,0xbb,0x5c,0xf9,0x87,0xad,0x4e,0xcd,0xc8,0x7e,
+  0x74,0xd5,0x4e,0xeb,0x23,0x51,0xd6,0xd2,0x8b,0xb8,0x40,0xf4,0x21,0xdf,0xe0,0xb0,
+  0x9d,0x91,0x98,0x39,0x57,0x57,0x22,0x25,0xe3,0xf8,0x0f,0xed,0x7a,0x22,0x78,0x88,
+  0xd6,0x83,0xcf,0x6b,0x39,0xff,0x6f,0xc2,0x4b,0xd8,0xaa,0x08,0x3b,0x64,0x76,0xf3,
+  0xc4,0xad,0xb3,0x99,0xf8,0xd7,0x38,0xfd,0xaf,0x78,0x15,0x22,0xa0,0x37,0x49,0x97,
+  0xa1,0xdf,0x13,0xdc,0x28,0xde,0x60,0x07,0x29,0x7e,0xc7,0xca,0xb5,0x58,0x48,0xeb,
+  0x15,0x86,0xb6,0xb2,0xe2,0x5f,0xc4,0xdf,0x1c,0x48,0x64,0xe5,0x1f,0x62,0x5e,0x77,
+  0x22,0xf7,0x4d,0xa4,0xe6,0x88,0x2a,0x1b,0xc5,0x6d,0xba,0x9d,0xac,0x48,0x57,0x8b,
+  0xd6,0x75,0x3a,0x0d,0x7d,0x82,0xeb,0x28,0xd9,0xf9,0x87,0x1b,0x83,0xcb,0x18,0x0a,
+  0xd8,0x4d,0xf4,0x28,0x80,0xf4,0x76,0x74,0x33,0x98,0xf3,0xdf,0xd0,0x4a,0x56,0xf0,
+  0xd4,0xc4,0xf5,0x44,0x5f,0xa6,0x8c,0x89,0x7f,0x25,0xa3,0x63,0xf4,0x97,0x8d,0x48,
+  0x21,0xcb,0x2d,0x1c,0x6e,0x0e,0x0b,0xde,0x76,0x75,0x8b,0x31,0xd2,0xcc,0x18,0x39,
+  0x4e,0x6f,0xed,0xb7,0xf8,0xe7,0xb7,0xf5,0x4f,0x0f,0x6b,0x41,0x27,0xfe,0xf5,0x80,
+  0xcd,0x5f,0x97,0x95,0x7f,0x78,0x09,0x65,0xbf,0x10,0x0a,0x31,0x49,0xe5,0x97,0xa5,
+  0x7b,0x8d,0x4b,0x1a,0x07,0x59,0x94,0xa7,0x26,0x16,0x9f,0x73,0xe2,0x5f,0xca,0x25,
+  0xe2,0x8e,0x7f,0x25,0xdc,0xfc,0x87,0x57,0x58,0xfe,0x21,0x5c,0xe7,0x1f,0xec,0xf8,
+  0x97,0x35,0xf8,0x9c,0x80,0x81,0x1e,0x05,0xff,0x0a,0x1c,0x8f,0x79,0x8b,0x18,0x77,
+  0x1f,0xef,0xaa,0xb0,0xb2,0x16,0xdd,0xfa,0xcb,0xb0,0x7f,0x71,0x6e,0xc3,0x35,0x5c,
+  0xdb,0x8b,0xd5,0x13,0xb1,0x83,0x3b,0x01,0x77,0x2c,0x85,0x13,0x71,0x6c,0xb5,0xf3,
+  0x0f,0x59,0xfc,0x2b,0x36,0xb1,0xfe,0x72,0x0c,0x66,0xec,0x0c,0xa0,0xad,0x58,0x2c,
+  0x8b,0x88,0x43,0x6c,0xb5,0x4b,0xc3,0x5a,0xe9,0xf2,0x2c,0x8e,0x0e,0xd9,0xfe,0xab,
+  0x31,0xfa,0xcb,0xb8,0xb8,0x46,0x2b,0x79,0xdd,0x58,0xb0,0x9e,0x38,0xc9,0xa5,0xbf,
+  0x53,0xe0,0xfe,0x61,0x6a,0xcb,0xf4,0x09,0xf2,0x75,0x53,0xdd,0x68,0x95,0x7d,0x31,
+  0x8e,0x8e,0xdd,0xcd,0xec,0xaf,0xdc,0xfa,0x5f,0x34,0xd2,0x04,0xbf,0xf4,0x0d,0xfd,
+  0xad,0x44,0xf7,0x17,0xd7,0x6d,0x90,0x7e,0x67,0xd8,0x89,0x88,0xe2,0x6a,0x5b,0x4f,
+  0xe1,0x90,0x51,0x3b,0x8f,0xa7,0x26,0xea,0xf6,0xfc,0xd0,0x2a,0xc4,0x5f,0x6e,0xfe,
+  0x79,0xfb,0x29,0x80,0x0b,0xce,0xf3,0x31,0x91,0xaf,0xed,0x4e,0xb0,0xac,0x0e,0x97,
+  0xf2,0x05,0x4c,0x3b,0x64,0xa1,0x31,0x25,0x13,0xff,0xa2,0x75,0x46,0x75,0x76,0xfd,
+  0x57,0x0c,0x95,0xe0,0xa4,0xd3,0xf4,0xe4,0xed,0x61,0x0c,0x84,0x95,0x3b,0x6c,0x2d,
+  0xba,0x53,0xf6,0x35,0xa0,0x87,0xc5,0x0c,0x23,0x3d,0x82,0x35,0x24,0x7b,0x01,0xc3,
+  0x95,0x7f,0xb8,0x9f,0x94,0x23,0xda,0x3a,0xa9,0x3c,0x6c,0x94,0x6f,0x54,0x06,0x51,
+  0xf6,0xcb,0x60,0x41,0xae,0xf3,0x3c,0xfe,0xc5,0xd8,0xe6,0xa9,0x94,0x70,0x34,0x9a,
+  0xd5,0xa4,0x07,0xa1,0x59,0x79,0x16,0xfe,0x5a,0x08,0xee,0x81,0x9f,0x9f,0xab,0x3f,
+  0x62,0x6c,0x1b,0x04,0xb8,0x14,0x27,0xd4,0x60,0xce,0xdb,0xbb,0x86,0x93,0x6d,0x98,
+  0x38,0x21,0x6b,0x56,0x6a,0xa2,0xb5,0x7f,0x81,0x81,0x95,0x26,0x99,0xfc,0x43,0xe5,
+  0x69,0xca,0x38,0x1f,0x2e,0x96,0x3e,0xa0,0xe0,0x71,0x56,0xee,0x23,0xa4,0xdd,0x0e,
+  0x72,0xd9,0xe5,0x48,0x5a,0x82,0x4c,0x15,0x58,0x7d,0x13,0xd3,0x68,0xbe,0x1b,0x91,
+  0x02,0x65,0x2f,0x73,0x57,0xfe,0xe1,0x25,0x7c,0x2e,0x57,0x4a,0xaf,0x2a,0xbf,0x42,
+  0xe0,0x33,0xa2,0x76,0x33,0x6c,0x65,0x91,0xcc,0xcf,0xe5,0x69,0x87,0xbf,0xa4,0x4f,
+  0x9f,0x76,0xc2,0x5e,0x3e,0x94,0x06,0xfb,0x90,0x13,0x71,0xb8,0xf4,0x97,0x61,0x95,
+  0x05,0xe6,0x15,0x7c,0x08,0x98,0x7a,0x1d,0x1e,0xe9,0x8c,0x08,0x5c,0x0c,0x54,0xbc,
+  0x60,0xb3,0x34,0x0f,0xd9,0x74,0x61,0x59,0xa4,0x5e,0xbe,0x54,0x96,0xfe,0x72,0x7b,
+  0x8d,0xce,0xfc,0xc3,0xe3,0xad,0x73,0xd2,0x12,0xc6,0xbf,0x2e,0x25,0x6a,0x06,0x7d,
+  0x80,0xbf,0xc8,0x11,0x1b,0x76,0xbd,0x48,0xeb,0x2b,0xbc,0x9c,0x9a,0x63,0x87,0x1d,
+  0x1a,0xc3,0x31,0x6e,0xfd,0xe5,0x67,0xb5,0x72,0x96,0x3f,0x6f,0xac,0xd2,0xe0,0xb7,
+  0x37,0x88,0x25,0x64,0x1f,0x99,0x81,0xd3,0x72,0x91,0xae,0x4a,0x31,0x6a,0xfa,0x53,
+  0x06,0xcc,0xd8,0xf4,0x40,0x0b,0x9f,0x16,0xbe,0x7f,0xed,0x52,0xca,0xda,0x61,0x8c,
+  0x4b,0xff,0x6b,0x27,0x61,0xf3,0x7c,0x42,0x5c,0x47,0xca,0x0e,0xaa,0x03,0x4b,0x35,
+  0x63,0x27,0xf9,0x6b,0x44,0xb5,0xa7,0xc8,0xf7,0x2c,0x6a,0x7a,0xb2,0x4a,0x63,0xd2,
+  0xcc,0x88,0xd1,0xd8,0x16,0xc9,0x36,0xc4,0x01,0x30,0x5c,0xfa,0xcb,0xbb,0xd7,0xa0,
+  0xdc,0x5b,0xee,0x0b,0xb0,0x5b,0x25,0x75,0xb5,0x24,0x57,0x10,0x7a,0x14,0xb6,0x7f,
+  0x1d,0xa7,0x8f,0x90,0xe0,0xcb,0x2c,0xdb,0x90,0x02,0xac,0xc8,0x9b,0x81,0xcb,0xad,
+  0xd9,0xeb,0x4e,0xd9,0x98,0xfe,0x0c,0xfe,0x1a,0xe9,0x0f,0x5d,0x0d,0x7b,0xf7,0xfb,
+  0xc6,0x11,0x12,0x1a,0xf6,0x3d,0xad,0xa2,0xb3,0xf4,0x0c,0xce,0xe1,0xfb,0xf4,0x37,
+  0x24,0x32,0x80,0x68,0x4b,0xea,0x37,0x23,0xfa,0x43,0xfb,0xec,0xf8,0xd7,0x30,0xc6,
+  0x5c,0x68,0x18,0x89,0x1d,0x5c,0xfc,0xf3,0x23,0x78,0x94,0x07,0x1e,0xbe,0x31,0x6a,
+  0x44,0xcc,0x45,0xfb,0xa4,0x21,0x9d,0x2f,0x4a,0xf9,0xa0,0x0d,0x93,0x8f,0xea,0x23,
+  0x6b,0xaa,0xb4,0x2f,0x30,0x8e,0xc4,0x0c,0x59,0xc7,0x7e,0xca,0x5c,0x08,0xf6,0x7d,
+  0x04,0x1e,0xff,0xa2,0xac,0xa4,0x0b,0xb0,0xd5,0xc1,0xfc,0x61,0xe9,0x24,0x79,0x98,
+  0x07,0xb9,0x2e,0x33,0xfe,0x8d,0x82,0xe1,0x49,0x67,0x70,0xbd,0xce,0x7a,0x5b,0x58,
+  0x85,0x11,0x73,0x69,0x10,0xac,0xcd,0x18,0x82,0xbf,0x32,0x33,0xfa,0xcb,0xe0,0xa2,
+  0xff,0x16,0x3c,0xbd,0x83,0xa4,0x33,0x56,0x15,0x8b,0x6e,0x8e,0xbf,0xa3,0x74,0x98,
+  0xcc,0x09,0x3c,0x68,0x9d,0xc6,0x4b,0x67,0x38,0x7f,0x2f,0xb8,0x85,0xca,0x5e,0xae,
+  0x4f,0xf4,0x94,0xcd,0xaa,0xed,0xe2,0x3f,0xec,0xa1,0x7e,0xac,0x03,0xfa,0x99,0x0e,
+  0x4f,0x65,0x2c,0xaf,0x47,0x7c,0x9f,0x3c,0x09,0xd7,0x41,0x42,0x06,0x47,0x75,0x97,
+  0xac,0x01,0x1f,0xb2,0xc3,0x55,0x07,0xc4,0x83,0x02,0x4a,0x16,0xfe,0x4a,0x51,0x3f,
+  0x7a,0x8c,0x83,0x00,0xa9,0xaa,0x0c,0xe4,0xd9,0x16,0x1f,0xe3,0xa0,0xf8,0x4d,0xd2,
+  0xa6,0xaf,0xc0,0xd4,0xc4,0xb5,0x22,0x25,0x2b,0x8a,0x4a,0x43,0x19,0xbe,0x4a,0x4c,
+  0x25,0xd5,0x69,0x20,0x64,0xef,0x5f,0x4c,0xff,0x0b,0x90,0xd4,0xda,0x94,0xb4,0x8d,
+  0x39,0x5d,0x95,0x38,0x75,0x6f,0x03,0x8a,0x2c,0x40,0x37,0xfe,0x88,0x0e,0xb3,0xda,
+  0x0d,0xdf,0xe7,0x08,0xa9,0xdb,0x14,0x4c,0xe1,0x7a,0x95,0xdd,0x7f,0xc2,0x4a,0x1c,
+  0x0d,0xcf,0x83,0x55,0x36,0x33,0xf1,0x2f,0xf0,0xfd,0xd0,0x2d,0x3c,0x81,0xa4,0x79,
+  0xc4,0xd7,0x8c,0xc7,0xbc,0x96,0x7f,0x98,0xba,0x62,0xd4,0x9b,0xd7,0x77,0xf1,0xa3,
+  0x7b,0xc5,0xa2,0xe6,0xe0,0xfa,0x5f,0x4e,0xfc,0xcb,0xc6,0x5f,0xc3,0xe0,0x1d,0xcf,
+  0x25,0xbe,0x3e,0x69,0x06,0x40,0xf0,0x59,0xcd,0xbe,0x93,0xd2,0x07,0x02,0x78,0xf8,
+  0x26,0x2c,0xdc,0x25,0xfd,0x38,0x99,0x73,0xcc,0xbb,0x03,0xd0,0xf1,0x71,0x12,0x4e,
+  0xae,0x73,0x4a,0x2f,0x47,0x04,0xc4,0x68,0x35,0x74,0x51,0xba,0xd1,0x85,0xbf,0xac,
+  0x6c,0xc3,0x20,0xbc,0xfd,0xfc,0x66,0x01,0x07,0x62,0x55,0xc4,0x33,0x02,0xcf,0xd7,
+  0x6b,0xc6,0x67,0xe1,0x82,0xf0,0xc0,0xbe,0x46,0xa7,0x27,0x8b,0xad,0x2e,0x84,0x66,
+  0x6f,0x93,0x27,0xe2,0xfe,0xa4,0xba,0x5d,0x4c,0xdb,0xf8,0x0b,0xbc,0x38,0x0c,0x9a,
+  0x88,0xa2,0xde,0xbe,0x85,0x54,0xb0,0x18,0xa2,0x0c,0xef,0x23,0x02,0x4f,0xc1,0x51,
+  0xda,0x36,0x2f,0x60,0x6e,0x9f,0x29,0x1e,0x35,0xda,0xb4,0x18,0xe5,0x54,0xb1,0x8a,
+  0x95,0xa9,0xbb,0x15,0xff,0x4a,0x77,0xeb,0x7f,0x01,0x94,0x66,0x22,0x05,0xb0,0x5e,
+  0x4e,0x6c,0xb4,0x4a,0xc3,0x75,0x17,0x1f,0x21,0xd3,0x59,0x26,0xaa,0xf2,0x03,0x32,
+  0xfd,0x75,0x97,0x36,0x37,0xee,0xb0,0xda,0xcf,0x88,0x9a,0x0c,0xdb,0xf1,0xaf,0x42,
+  0x27,0x05,0x9d,0x90,0xb7,0x78,0x6c,0xeb,0x7d,0x7d,0x2f,0xb9,0x3f,0xc5,0x68,0x06,
+  0xb1,0xcc,0xca,0x8b,0xd9,0x62,0x47,0x50,0x9f,0xc8,0xf5,0x1e,0x4b,0xd3,0xb7,0xda,
+  0x01,0x38,0xef,0x94,0x32,0xf1,0x2f,0xd9,0x25,0x01,0x30,0xc5,0x2c,0x38,0x27,0x5d,
+  0x9e,0x07,0x2d,0x83,0xac,0xe5,0x80,0xc0,0xbb,0xe4,0x0b,0x7c,0x4d,0x9d,0x65,0x3a,
+  0x49,0x2f,0xd1,0xf2,0xa4,0xaf,0x3b,0x93,0x7f,0x98,0x14,0x46,0xf4,0xb0,0x8e,0x6c,
+  0xd8,0x8c,0x2a,0xd6,0xcb,0x0e,0xaf,0x84,0x48,0x2b,0xdc,0x3f,0x5e,0x01,0x49,0x1b,
+  0xe0,0x8b,0x79,0xc9,0x0f,0x48,0x78,0xfd,0x9f,0xa5,0xbe,0x74,0xa6,0xe4,0x5b,0x02,
+  0x13,0x0b,0x7b,0x43,0x3b,0xe8,0x8f,0x34,0xaf,0xdb,0x96,0x89,0x7f,0x79,0x19,0x2f,
+  0xa8,0x82,0x69,0xbd,0x6b,0xee,0xf4,0xf7,0xe6,0x5b,0xf9,0xe1,0x3b,0x4b,0x87,0xc5,
+  0x7d,0x85,0x07,0xc8,0x77,0x4c,0x05,0xbf,0xc6,0xaf,0x5e,0x9a,0x8e,0x9a,0xec,0x0e,
+  0x99,0xe4,0x20,0x39,0x19,0x2b,0xf0,0xab,0x4f,0x64,0xf2,0x0f,0x8d,0xb2,0x54,0xb3,
+  0x4e,0xf2,0xe8,0xd5,0xa6,0xbc,0x7e,0x9e,0x6e,0x44,0x43,0x57,0xc3,0x7a,0x09,0x55,
+  0x7d,0x9e,0x50,0x11,0x7f,0x0a,0xf2,0x42,0xfe,0x85,0xf2,0x8e,0x79,0x15,0x82,0x3b,
+  0x45,0xad,0x8f,0x6c,0x30,0x82,0xdd,0x6a,0xa9,0x98,0x89,0x7f,0xe9,0xbb,0xb6,0x94,
+  0x63,0xcc,0x65,0x3f,0x6c,0x9a,0x65,0xe9,0x6b,0x00,0x0e,0x68,0xbb,0xe8,0x8d,0xdb,
+  0x95,0xd9,0x61,0x56,0xed,0x35,0xa8,0xdc,0x92,0xfb,0x2a,0xdd,0xd5,0xf1,0x8d,0xe4,
+  0x9a,0x95,0x56,0xec,0x06,0x0b,0x94,0xc8,0x77,0x69,0xe5,0x36,0x75,0x65,0xbc,0xd4,
+  0xc6,0x5f,0x04,0x9e,0xd3,0x10,0xc9,0x27,0x70,0x4b,0xbc,0x44,0x42,0x43,0x5e,0xf8,
+  0x47,0xe9,0x87,0xc9,0xaa,0xd3,0xb7,0x87,0xbe,0x86,0x2f,0xcf,0x2a,0x33,0xbf,0x56,
+  0x5a,0x08,0x6f,0xad,0x99,0x41,0x35,0x24,0xc0,0xde,0xc4,0xf9,0xe7,0xfb,0xc9,0xcb,
+  0x7a,0xdd,0x9d,0x3e,0x41,0x1d,0xc7,0x3f,0x0f,0x30,0xf9,0x23,0x7a,0x80,0x73,0xcb,
+  0xf3,0x20,0x57,0xf1,0xc5,0xd8,0x95,0xc6,0x7a,0x53,0xfd,0xfd,0xa2,0xcd,0x89,0xd7,
+  0x8c,0x39,0xd4,0xa6,0xbe,0xc1,0xc1,0x23,0xf8,0x54,0xe6,0xb8,0xf9,0xe7,0xed,0xfb,
+  0x47,0x5d,0x0a,0xeb,0x35,0x0b,0xd5,0xb1,0x71,0x8f,0x9b,0x45,0xf3,0x0f,0x48,0xc1,
+  0xed,0x47,0xb4,0xf0,0xb9,0x60,0xf7,0xa4,0xe0,0x9b,0x47,0x96,0x22,0xda,0x2a,0xe6,
+  0xb4,0x2d,0x0c,0xd1,0x1f,0xa1,0xdd,0xb1,0x0c,0xff,0x3c,0xe2,0xaf,0x55,0x36,0xdd,
+  0xd3,0x83,0xa4,0xcc,0xe6,0xd6,0xa8,0xe9,0x55,0xee,0x6e,0xbc,0xab,0x5d,0x22,0x37,
+  0xf5,0xe5,0x7f,0xd0,0x30,0x99,0xac,0x5a,0xc6,0x76,0x73,0x4e,0x3b,0xcf,0x8c,0x1f,
+  0x13,0xbd,0x15,0x06,0xbf,0x6c,0xe3,0xaf,0x0d,0xa4,0x1d,0x41,0x56,0x54,0x2c,0x22,
+  0x0f,0xd0,0xa9,0xaf,0xe7,0xd9,0x1a,0x6a,0x79,0xb5,0x00,0xb2,0x26,0x61,0xc1,0xdd,
+  0xb7,0xc4,0x82,0x4d,0x8f,0x61,0xb6,0xa1,0xdd,0xc5,0xe6,0x39,0x4e,0x59,0xe6,0xe7,
+  0x70,0x06,0x7f,0xb5,0xd9,0xb4,0x51,0x71,0x52,0x91,0xce,0x9b,0x0d,0x40,0x6c,0x2f,
+  0x21,0x23,0x0a,0xb2,0xcd,0x63,0x54,0x3a,0x8f,0x9f,0x50,0x25,0xa9,0x45,0xc9,0xc2,
+  0x5e,0x95,0x2f,0xd2,0xa4,0xa2,0x2b,0x4a,0xb5,0x1b,0x7f,0x1d,0x24,0x75,0x1c,0x52,
+  0x1d,0x26,0xb3,0xe8,0xe7,0xb7,0x4f,0x1a,0x21,0xe7,0xc9,0x97,0x52,0x95,0xd0,0x22,
+  0xae,0x41,0x85,0xbb,0x64,0x71,0x80,0xfc,0x14,0xa1,0x19,0x4f,0x4d,0xe4,0xd0,0x8c,
+  0x1c,0x6b,0xa8,0xe9,0x71,0xf3,0xcf,0x9f,0xe5,0x27,0x4b,0x66,0x31,0xde,0xc8,0xb5,
+  0x64,0x4a,0x2b,0x13,0x18,0xaa,0x93,0xdd,0x44,0x88,0xa7,0x39,0xfe,0x72,0xd5,0x25,
+  0x99,0x3c,0x6b,0x31,0xab,0xfe,0x0b,0x96,0x09,0x63,0x25,0xcb,0xc8,0x68,0x32,0x6c,
+  0x5c,0x9f,0x28,0x46,0xd9,0xaf,0xb0,0x51,0x90,0x90,0xfa,0xe4,0x5e,0x44,0x5b,0x9a,
+  0x94,0xdb,0xc1,0x65,0x6a,0x05,0x57,0xc1,0xcb,0xa1,0xc2,0x88,0xb1,0x6e,0x7d,0x06,
+  0x7f,0x35,0xc9,0xab,0x89,0x7f,0x49,0x07,0x62,0xa2,0xae,0x0e,0xff,0x3c,0x17,0xb6,
+  0xf2,0x0f,0x92,0xb7,0xb8,0x4a,0xf2,0x36,0xf2,0x04,0xfd,0xe9,0x18,0x8d,0xb0,0xd5,
+  0x1d,0x55,0xcd,0x9d,0x3f,0x72,0xe1,0x2f,0xfd,0x87,0xf4,0x86,0xe8,0x6d,0xcd,0xe2,
+  0xbd,0xe4,0x59,0xd8,0x92,0xac,0xc1,0x4b,0x79,0x41,0x10,0x57,0x6d,0x5e,0x5a,0xa1,
+  0xaf,0xd6,0x6d,0xd8,0x95,0x53,0x35,0xaf,0x33,0x71,0xc7,0x60,0xc9,0x6a,0xb9,0xaa,
+  0x05,0x1e,0x58,0x07,0x7f,0xcd,0x4c,0x3e,0x14,0x28,0xbf,0x3d,0xfa,0xa5,0x35,0x25,
+  0xe9,0x67,0x6f,0xd1,0xbf,0x60,0x91,0x6c,0xc4,0x96,0x77,0x14,0xc5,0xfb,0x86,0xba,
+  0x6a,0x03,0x5f,0xe8,0x2c,0x8e,0xb7,0x27,0xb7,0x04,0x02,0x36,0xff,0x46,0xd0,0x90,
+  0xc0,0x48,0x58,0x8c,0x88,0x19,0xfc,0x45,0x4f,0xea,0xb3,0x94,0xfc,0x07,0x1b,0xe7,
+  0xd1,0x73,0xb1,0x50,0xa9,0xca,0x80,0x98,0x11,0x2e,0xa9,0x8a,0x4b,0xbd,0xad,0xfd,
+  0xb1,0x70,0xa9,0xef,0x41,0x49,0x6f,0xed,0xd7,0x1d,0xd9,0xdc,0x08,0x99,0xc4,0xea,
+  0xbf,0xf8,0x84,0x3b,0xf8,0xab,0x4f,0x63,0x7c,0xe6,0x1b,0xa4,0x41,0x3a,0xca,0xf4,
+  0x97,0xb1,0x48,0x59,0x87,0x07,0x0d,0x26,0x93,0xbe,0xa5,0xa3,0xc2,0xaf,0x88,0x5c,
+  0x94,0xf5,0x26,0x77,0xe3,0x75,0x56,0xa0,0x74,0xb1,0xc9,0xce,0x3f,0xcc,0xc4,0xbf,
+  0x9e,0x27,0xc5,0x80,0xa4,0xca,0x2b,0x84,0x17,0x79,0xcd,0x11,0x12,0xfd,0xdd,0xcc,
+  0x74,0x81,0x01,0x88,0xb1,0xa2,0xe9,0x73,0xca,0x1b,0x19,0x98,0x6c,0xad,0xd7,0x8b,
+  0x9c,0x7f,0xde,0x15,0xff,0xea,0xb0,0xb5,0xbd,0xb6,0xdb,0x42,0xcc,0x58,0x11,0x66,
+  0xd1,0x1e,0xea,0x0c,0x7f,0x89,0xdb,0xad,0xd4,0x44,0x25,0x65,0x13,0x71,0xc0,0x5f,
+  0xd1,0x8e,0xac,0xf8,0x57,0xab,0xa0,0x1b,0xcb,0xb5,0x6b,0x65,0x59,0x10,0x2a,0x60,
+  0x32,0xfd,0xed,0xac,0xc8,0x6b,0x9e,0x56,0x84,0xa1,0xb1,0x0a,0x8e,0xbf,0xb6,0x08,
+  0xc8,0x76,0x58,0xd4,0x97,0xd1,0xff,0x6a,0xa5,0xba,0xa1,0x94,0x7a,0x44,0x07,0x7f,
+  0xe1,0xfd,0x03,0x48,0xaa,0x41,0x26,0x4f,0x20,0xa6,0x5e,0x3f,0x6d,0xd0,0x70,0x55,
+  0x02,0x62,0x97,0x7f,0x30,0xf7,0x89,0x4c,0xfd,0x97,0x7d,0xff,0xc8,0xfe,0x58,0x36,
+  0xff,0xfc,0x21,0xbb,0xc8,0x6b,0x35,0x9f,0x9f,0xc7,0x19,0x5d,0x3c,0xce,0x8f,0xf2,
+  0x4d,0x68,0x09,0x62,0xf5,0xe2,0x69,0x18,0xa3,0x26,0x26,0x39,0x35,0x62,0x18,0x87,
+  0xed,0x8e,0x79,0x5d,0xf9,0x87,0xed,0xe2,0x59,0x65,0xdf,0x3c,0xb8,0xf9,0xd9,0x98,
+  0x65,0xd7,0x27,0x26,0xbd,0x89,0x65,0x44,0x4d,0x59,0xb3,0xaa,0x73,0xc9,0x3c,0xd6,
+  0xc2,0xd6,0xeb,0x79,0x72,0xd6,0x88,0x60,0xa6,0xee,0x61,0x07,0x7f,0x69,0x27,0xb5,
+  0x59,0x64,0x1d,0x40,0x2a,0xad,0x9f,0x41,0x72,0x96,0x64,0x58,0xc7,0xeb,0x07,0xfb,
+  0xb5,0x59,0xbc,0xf2,0xae,0x9f,0x14,0x69,0x6e,0xfc,0x05,0x2d,0xb4,0x0e,0xf5,0x97,
+  0x1d,0xfc,0x55,0x4b,0x1e,0x6e,0x62,0x21,0xad,0x00,0xb8,0x97,0x2e,0x6e,0x8d,0x7c,
+  0x68,0x11,0xb0,0xc5,0xc3,0xa2,0x5d,0xfd,0x7e,0x5a,0x60,0xe1,0xaf,0x56,0x0b,0x91,
+  0x55,0xf7,0x28,0x67,0xdc,0xf8,0x6b,0x3d,0x65,0x25,0x0c,0x5e,0xb1,0x93,0x85,0xbd,
+  0xf8,0x26,0xa5,0x30,0xb6,0xde,0x27,0x85,0x69,0xe6,0x6a,0x3c,0xf8,0x7d,0xc4,0x48,
+  0x3b,0x69,0x87,0xcc,0x10,0x29,0x0d,0x2a,0x01,0x25,0x83,0xbf,0xea,0xf4,0x87,0xd0,
+  0xc3,0xff,0x47,0xd4,0x07,0x31,0xca,0x86,0x6c,0x7e,0x09,0x92,0xc7,0xe4,0x14,0xc9,
+  0x92,0x7e,0x4f,0x0b,0x39,0x49,0xbe,0x27,0xda,0x74,0x10,0xc9,0x32,0x53,0x62,0x49,
+  0x74,0x4a,0x90,0x28,0x46,0xa6,0xfe,0xeb,0x5a,0xf2,0xef,0x58,0xdb,0x35,0xd2,0xe6,
+  0xd3,0xdb,0x90,0xef,0x1d,0x40,0x96,0xf7,0x0f,0xf1,0xef,0xc4,0x7c,0xb3,0xa5,0x48,
+  0xc7,0xcf,0x5b,0x6f,0x3a,0x93,0xff,0x9d,0xc2,0x97,0xc5,0x5f,0x39,0xd4,0xf4,0xdd,
+  0x33,0x38,0x22,0xeb,0x43,0x46,0xc4,0x68,0x06,0x7f,0xad,0x25,0x0c,0x64,0xa1,0x3c,
+  0xcd,0x79,0x57,0xd8,0x0b,0x3c,0x7c,0xf5,0xdd,0xe4,0x05,0x79,0xca,0x89,0xfc,0xd4,
+  0xd7,0x4c,0xed,0x1d,0x3b,0x10,0x76,0xa1,0x65,0xbf,0x69,0x13,0x76,0x19,0x30,0xe1,
+  0x2e,0xfe,0x8d,0xd1,0xc4,0x67,0x62,0xde,0x5b,0xa4,0x9f,0x91,0xe3,0x34,0xfc,0x26,
+  0x80,0xac,0x57,0xc9,0xf1,0xfe,0x9b,0xf5,0xea,0x11,0xe9,0xbd,0x65,0xc7,0xe3,0x37,
+  0x63,0x92,0x61,0xed,0xe4,0x23,0xf1,0x70,0x7a,0x2d,0xf7,0x0f,0xc3,0xbc,0xfe,0xeb,
+  0x18,0xad,0xd1,0x7d,0x43,0x19,0xfe,0xf9,0x8d,0xb1,0xa7,0xdf,0xc6,0xec,0x88,0xa2,
+  0x08,0x59,0x47,0x6e,0x4c,0x33,0xde,0x8c,0x55,0x82,0x50,0xe4,0x41,0x5a,0xc8,0xc7,
+  0x78,0x6a,0x62,0x29,0x7d,0x90,0x96,0x9d,0x61,0x5d,0x7b,0xb5,0x32,0x5e,0xff,0xf5,
+  0x13,0xad,0x4c,0xcc,0xc4,0xbf,0x4a,0xc9,0x26,0xf2,0x74,0xa8,0x12,0xe9,0x9a,0x37,
+  0xd3,0x07,0xc8,0xd4,0x83,0x00,0x66,0x2f,0xc6,0x1e,0xd7,0x2a,0x9a,0xd8,0xe0,0x36,
+  0x8d,0x5d,0xc7,0x90,0x57,0x91,0x27,0xfb,0xad,0x25,0x98,0xca,0x62,0x64,0x0d,0xad,
+  0x18,0x2d,0x25,0x19,0xfe,0x0d,0xa6,0x0a,0x71,0x42,0xa9,0x69,0xf0,0x19,0x74,0xc0,
+  0xaa,0x4d,0xee,0x24,0x15,0x86,0xc7,0x2a,0x04,0xc3,0x3b,0xc1,0xc4,0xe8,0x49,0x9f,
+  0x27,0xab,0x46,0x0c,0xf6,0xaf,0x24,0xe6,0xcf,0xdb,0xfc,0x1b,0x3f,0x23,0xe7,0x69,
+  0xc4,0x0c,0x9e,0x13,0x9f,0x25,0x47,0x8c,0x9b,0xd3,0xf9,0x3d,0xd2,0xfb,0x80,0x30,
+  0x66,0xa5,0x90,0xc5,0x9a,0x2c,0x20,0x48,0x24,0x2e,0x2d,0xd7,0x8e,0x90,0xd9,0x03,
+  0xec,0x0c,0xff,0x0a,0xf3,0x21,0xa5,0xf7,0xc4,0x43,0xb4,0xbb,0xc5,0xb7,0x49,0x75,
+  0xf2,0x0f,0x8f,0xea,0x1f,0x46,0xeb,0x0e,0xfa,0x58,0x39,0x89,0x5e,0x6b,0x16,0x74,
+  0xb1,0xf5,0x5a,0x59,0xca,0xab,0xf3,0x8c,0x3d,0xbd,0x98,0xd9,0xe8,0x01,0x4f,0xaf,
+  0x7f,0x11,0x5b,0x2f,0xb9,0x16,0x5a,0x1a,0x8f,0x1a,0xf8,0xaf,0xc3,0x86,0xe8,0xe2,
+  0xdf,0x38,0x06,0xff,0xe8,0x94,0x61,0xe9,0x2e,0xf2,0x0b,0x3c,0xcb,0x1d,0x2e,0xde,
+  0xa7,0x1f,0x17,0x76,0x80,0x61,0x9c,0x51,0x3e,0xd2,0x0b,0xd1,0x63,0x9c,0x8d,0xe8,
+  0x98,0x73,0x74,0x7c,0x87,0x41,0x33,0x80,0xe4,0x47,0x8d,0xb9,0xc4,0x7b,0xc8,0xa5,
+  0xbf,0xac,0x77,0xf6,0xfa,0x07,0x59,0x2c,0x69,0x0d,0x2f,0xe7,0xc7,0x20,0x97,0x1f,
+  0xd1,0xd6,0x0a,0xf2,0x6b,0x00,0x50,0x05,0x29,0xcf,0x74,0x6d,0x07,0xf8,0x90,0xf9,
+  0x59,0xdc,0x86,0x27,0x0f,0x56,0x9d,0x83,0xe7,0x42,0xcf,0xe4,0x1f,0x76,0x32,0x3f,
+  0x13,0xfe,0xea,0x49,0x47,0xed,0x4b,0x04,0x9f,0x9f,0xb3,0x6d,0x7c,0xdd,0xec,0x08,
+  0xf9,0xa7,0xdb,0xdc,0xf2,0x58,0xba,0xb2,0xd4,0xec,0x4c,0x15,0x9d,0x81,0xad,0xad,
+  0x4a,0x53,0x5c,0xfa,0xcb,0xb2,0xd8,0x16,0x4b,0x9a,0x81,0x6e,0xd1,0x1b,0x07,0xa7,
+  0xe2,0x24,0x73,0xec,0xdb,0x0c,0x05,0xd5,0xcc,0x17,0xd2,0x56,0x23,0x60,0x7a,0x42,
+  0x77,0x78,0x48,0xb7,0xbe,0xf5,0x24,0xf7,0x37,0xe6,0xf1,0xfc,0x43,0x71,0x03,0xf2,
+  0x6f,0xcc,0x76,0xf1,0x6f,0x28,0x47,0x8c,0x30,0xdc,0x3f,0x37,0x7c,0x1b,0xfc,0xf9,
+  0x1a,0x40,0xc7,0xc5,0x41,0x71,0x95,0xc1,0xb0,0xf0,0x45,0xd2,0xd3,0x70,0x8b,0xd9,
+  0x34,0x5c,0x1e,0x54,0x46,0xc5,0xf0,0x80,0xc2,0xd6,0xcb,0x08,0x1f,0xb6,0xe2,0x5f,
+  0x11,0x14,0xdb,0x75,0xf2,0x0f,0xcf,0x21,0xf7,0xb5,0xe9,0x3b,0x57,0x76,0x09,0x5d,
+  0xbe,0x97,0x2c,0x32,0xff,0x9b,0x0d,0x98,0xcc,0x4b,0x04,0x70,0x3f,0xe0,0xdc,0xb6,
+  0x8b,0xf2,0x47,0xc6,0xdc,0x01,0x9f,0xcd,0xf3,0xbf,0x08,0x6b,0x8e,0x18,0x6a,0x33,
+  0x8b,0x5d,0xf1,0xaf,0xdf,0xf3,0xfa,0xaf,0xcb,0xa8,0xad,0x8c,0xa1,0xb1,0x61,0x2e,
+  0xb2,0x8c,0x59,0x8b,0xfd,0xa4,0x3e,0xe6,0x1b,0x91,0xee,0x67,0xb0,0xcb,0x6b,0x4a,
+  0xb3,0x78,0xd7,0x90,0x74,0xd1,0xce,0x01,0x1e,0x76,0xf1,0x6f,0x10,0x3f,0xf2,0x6f,
+  0x9c,0x21,0x9d,0xed,0x58,0x3d,0x64,0xd7,0x7f,0x6d,0x17,0xdf,0x2b,0x59,0xd3,0x1e,
+  0xe4,0xec,0x16,0x7b,0x69,0xd0,0x0c,0x6c,0xf2,0x04,0x79,0x17,0x2d,0x7a,0xd3,0x62,
+  0xad,0x97,0x2c,0xfd,0x65,0xc6,0x7f,0x48,0xf5,0x98,0xe2,0xaa,0x75,0xe5,0x6c,0x87,
+  0x80,0xad,0xfa,0xe0,0x71,0xc0,0x78,0x8a,0xe5,0xc6,0x2b,0xba,0x47,0xe6,0x95,0x92,
+  0xae,0xc4,0xec,0xd7,0xb3,0xf8,0x0f,0x75,0xbb,0xec,0x0b,0xfe,0x89,0xf8,0xdb,0x1c,
+  0xb6,0x6f,0x17,0xdf,0xd4,0xd7,0xd0,0x2a,0x03,0x95,0x08,0x90,0xad,0xc5,0x64,0xf5,
+  0x4d,0xac,0x7e,0x70,0xad,0xff,0x75,0x1b,0x68,0xa4,0x9c,0xfa,0x2f,0xf9,0x02,0xdd,
+  0x9a,0xf6,0xa6,0x18,0x28,0x8e,0xc0,0x23,0x23,0xbd,0x4e,0x8e,0x60,0x38,0x78,0xb3,
+  0xf4,0x3e,0xe9,0x5f,0x1d,0x59,0xe2,0xc0,0x2e,0xef,0x5a,0xd8,0xe3,0x98,0xc4,0x61,
+  0x52,0x7a,0x8f,0xd7,0x64,0xa5,0xc4,0xac,0xf8,0xd7,0x5c,0x07,0x5b,0x21,0x26,0x3a,
+  0xc5,0xf5,0x02,0x92,0xe0,0xfc,0x9f,0x27,0xf5,0xcb,0x32,0xb0,0xab,0x59,0xfa,0x28,
+  0xfe,0x3e,0xaf,0x08,0x4b,0xdb,0x40,0x2c,0xa3,0xff,0x85,0x48,0xbc,0x8f,0x3d,0x95,
+  0xf0,0x7d,0x5e,0x82,0x17,0x6c,0x80,0x9f,0x93,0xec,0x54,0xfd,0xe4,0xb0,0x11,0x5e,
+  0x88,0xd4,0x1c,0x32,0x3e,0xa7,0x6b,0xb7,0xc2,0x86,0xc8,0xba,0xb6,0x4a,0x4f,0x89,
+  0x16,0xb1,0x83,0x3b,0xfe,0xa5,0xb3,0xa7,0xe0,0x7d,0x9c,0x96,0xa3,0x60,0x04,0xec,
+  0xdf,0x8e,0x02,0x43,0xb0,0x94,0xcf,0x5a,0xb0,0x34,0xf0,0x20,0xa7,0x53,0x33,0x61,
+  0xff,0x2a,0x33,0xac,0x23,0x8b,0x0f,0x32,0xfc,0x1b,0x7b,0xb0,0x72,0x21,0x24,0x9e,
+  0xa1,0x6d,0xdc,0x97,0x10,0xf8,0x5a,0x10,0x46,0xf3,0xa5,0x0f,0xd8,0xd4,0x1c,0x03,
+  0x9e,0xd9,0xe2,0x1b,0xbc,0xab,0x42,0xa4,0xf6,0xd1,0xa2,0xa5,0xbf,0x8c,0xfc,0x1b,
+  0x07,0x06,0xca,0x42,0x2c,0xd5,0x6d,0x15,0xad,0x8c,0x01,0x40,0xb8,0x9a,0x17,0x1f,
+  0xa1,0xd1,0x9e,0x2c,0x4b,0xa3,0x22,0x33,0x63,0xe1,0xf3,0x2c,0x66,0xda,0xc1,0xd0,
+  0xb5,0x5c,0x2c,0xb2,0x13,0x11,0xfb,0x89,0xbb,0xfe,0xcb,0x60,0x31,0xfa,0xe7,0x48,
+  0x5d,0xb3,0x4f,0x53,0x05,0x5e,0xff,0x25,0xa3,0xfe,0x72,0x32,0x65,0x14,0xd4,0xb6,
+  0xb1,0x8a,0xb0,0xa1,0x02,0x1d,0x1c,0x8f,0x0f,0xc9,0x64,0xcc,0xf8,0xa5,0x98,0x88,
+  0x88,0x40,0xec,0xe5,0xac,0xfa,0x2f,0x62,0x2f,0x0a,0x3f,0x57,0x67,0x6b,0x81,0xb4,
+  0x87,0xe8,0x04,0xae,0xb3,0xd9,0x0e,0xf3,0x4d,0x27,0x5f,0x54,0x1a,0x6e,0xb6,0x8c,
+  0xec,0xf8,0x97,0x11,0x74,0xb6,0xbf,0x04,0x0f,0x7b,0x39,0x3c,0x54,0x86,0xc5,0xe8,
+  0x12,0x81,0x7b,0x4c,0xad,0xe0,0xf8,0x3d,0xc9,0x23,0x62,0xec,0x1c,0x32,0xc3,0xbf,
+  0x71,0x80,0x58,0x9c,0xba,0x56,0xed,0xc0,0xb0,0x5d,0x56,0x30,0x40,0x76,0x92,0x6a,
+  0x23,0xd0,0xc2,0x53,0x32,0x4c,0xa5,0xd9,0xce,0x84,0x8f,0xc1,0xed,0x87,0x63,0x0a,
+  0x00,0x7f,0xe5,0x5a,0xef,0x79,0x84,0xae,0xc9,0x98,0x9b,0xe7,0xe4,0x65,0xce,0xbf,
+  0x11,0x65,0x01,0x47,0x64,0x95,0x2c,0x42,0xc0,0x5b,0x99,0x56,0x02,0xf6,0x12,0x2c,
+  0x17,0x0f,0x12,0x67,0x9e,0x1d,0xfc,0xb5,0xe3,0xa4,0x95,0x8f,0xcd,0x0a,0xd8,0xe7,
+  0x6e,0xe8,0xa5,0x6d,0xa8,0x64,0x4a,0xe2,0x4c,0x1e,0x3d,0xa6,0xd8,0xc7,0x50,0x0a,
+  0x11,0x73,0xad,0xca,0xcd,0x78,0x2f,0x7b,0x96,0xe1,0x96,0x70,0xe9,0x2f,0x5f,0xa6,
+  0x35,0x09,0xaf,0x25,0xa9,0xfc,0x14,0xdc,0xf3,0xa3,0x9c,0xed,0x70,0x10,0xee,0xf9,
+  0xcb,0x24,0xd2,0x11,0x48,0x4a,0x5c,0xa3,0xd9,0x9b,0x96,0xa6,0x53,0x56,0x11,0xf6,
+  0xf7,0xd2,0x88,0x43,0xc4,0xe1,0xaa,0xff,0x92,0x23,0xa5,0x0c,0x64,0xf1,0x42,0x30,
+  0x6e,0xa0,0xa7,0xf7,0x3a,0xb1,0x75,0xbb,0xc8,0x48,0x56,0xfc,0x8b,0x95,0x86,0x71,
+  0x5c,0x90,0x55,0xff,0x55,0x17,0xb3,0x29,0x0d,0xd1,0xe8,0x33,0x58,0xbd,0x8c,0x26,
+  0x4d,0x12,0x0f,0xa1,0xa8,0xfa,0x7a,0x9e,0x9a,0x18,0x93,0x36,0xab,0x4e,0x3d,0x51,
+  0x93,0xcd,0x48,0x9f,0xad,0xbf,0xfc,0x37,0xe8,0x2d,0x63,0xb8,0x0a,0x83,0x53,0x6f,
+  0xd8,0xc9,0x81,0xd3,0x18,0xed,0xbc,0x82,0xe5,0x36,0xc8,0xd1,0xa1,0x6e,0xf6,0x5b,
+  0xa1,0xb1,0x0d,0x19,0x46,0xc4,0xf1,0xfc,0x1b,0x6f,0xa2,0x11,0x55,0x5c,0xc9,0x8a,
+  0xe8,0x51,0x07,0x9b,0x3d,0x1a,0x4f,0x71,0x6c,0x52,0x77,0xc2,0x95,0xad,0xeb,0xfc,
+  0xb5,0x3d,0xc6,0xa5,0xbf,0xbc,0x43,0xe3,0x74,0x7c,0x06,0xf8,0xfc,0xac,0x10,0x8c,
+  0xb2,0x1c,0xaa,0x22,0x78,0x8b,0x02,0xc8,0xc2,0x16,0x16,0x85,0x69,0x82,0x47,0xd8,
+  0x6b,0x30,0x5c,0x90,0x60,0xd4,0x88,0x3c,0xcf,0xca,0xa5,0xbf,0x6c,0x44,0x90,0xd2,
+  0x90,0x4d,0xef,0xf7,0x83,0xf1,0xb6,0xb7,0x1a,0x2c,0x6c,0xa5,0x23,0xed,0xa1,0x56,
+  0x30,0x95,0x45,0x2b,0xea,0xb0,0xfe,0xab,0xcc,0xaa,0x08,0x93,0x62,0xe3,0xf0,0x57,
+  0x86,0xd2,0x10,0xa3,0x5d,0x88,0xbf,0x9c,0xb2,0x2f,0xf6,0x7c,0x39,0x15,0x46,0x51,
+  0x4e,0x84,0xc8,0x2b,0xb9,0xac,0x31,0x89,0xec,0xfa,0x2f,0x86,0xd1,0xce,0xd9,0x21,
+  0xad,0x73,0xf6,0xa2,0x60,0x21,0x18,0x23,0x39,0x74,0xd8,0x0e,0x4b,0xec,0x8a,0xb0,
+  0x73,0xf6,0x7a,0xbd,0x90,0xcd,0x3f,0xef,0xc4,0xb6,0x14,0x17,0xff,0xe1,0x90,0x7c,
+  0x12,0x36,0xf1,0x40,0xa6,0xcb,0x63,0xd7,0x7f,0x35,0x58,0x35,0x62,0x8e,0xfe,0xb2,
+  0xc5,0x7f,0x98,0x09,0x7b,0xb9,0xd9,0xe6,0x79,0xd2,0x9a,0x02,0xb0,0x4b,0xe8,0xe2,
+  0xaa,0xd6,0x32,0xe7,0xdf,0x40,0xdf,0xcf,0x9a,0x67,0x5b,0x7f,0xf9,0xaa,0x6d,0xbc,
+  0x4e,0xdc,0xc2,0x56,0x4d,0x19,0xfe,0xc3,0x44,0xfc,0x4d,0xf2,0xa8,0xc2,0xee,0x28,
+  0xde,0xb2,0x7d,0xbd,0xbf,0xc2,0x2e,0x2d,0x74,0xee,0x0d,0xb7,0xfe,0x32,0x32,0x60,
+  0xd8,0x93,0x19,0xdc,0xd8,0xf6,0xa6,0x69,0xf1,0xc9,0xbc,0x49,0x0e,0x51,0x27,0xd4,
+  0xcb,0xd4,0xc3,0xa7,0xf1,0xf9,0x61,0xd2,0x60,0x7c,0x7e,0xdc,0xfc,0x1b,0xba,0x8b,
+  0xf6,0xb0,0x7a,0x3d,0x06,0xc2,0x70,0xcc,0x06,0x78,0x8b,0x5a,0xa1,0x31,0x87,0xa9,
+  0x06,0xd7,0xf4,0x7e,0x96,0x7f,0x68,0xaf,0x85,0xbb,0xfe,0xcb,0xa5,0xed,0x35,0x19,
+  0xe3,0xd4,0xd4,0x21,0xd9,0x40,0x92,0xc3,0x02,0x1e,0xed,0x82,0x31,0xe4,0x91,0x34,
+  0xbf,0xb5,0xda,0x33,0xf8,0xdd,0xa5,0xbf,0xbc,0x5f,0xa9,0xde,0x0a,0xb0,0xeb,0x02,
+  0xc2,0xae,0x24,0xec,0x4d,0x17,0x28,0x86,0xbd,0x3a,0x2d,0x20,0xb6,0xbd,0x63,0x90,
+  0x25,0x22,0x56,0x27,0x95,0x21,0x71,0x04,0xde,0x37,0x55,0x54,0x1d,0x14,0x47,0xec,
+  0xd0,0x98,0x3b,0xfe,0x45,0x79,0xbe,0x8d,0xbe,0x03,0xfd,0x04,0xf4,0xba,0xdb,0xec,
+  0x43,0x42,0x6c,0xf1,0xd4,0xc5,0xf1,0x3d,0xf6,0xf7,0x69,0x45,0x16,0x5f,0x10,0xd9,
+  0x2b,0x6e,0x56,0xc6,0x39,0xc9,0xe2,0xdf,0x08,0xa6,0xe1,0xfd,0xfc,0xef,0x8c,0xd2,
+  0x10,0xde,0xcf,0x2f,0xdb,0x61,0xaf,0x13,0x32,0x7b,0x2d,0xaf,0x60,0xb2,0xcb,0xdf,
+  0x38,0xa8,0xdc,0x29,0xfe,0x52,0xfc,0x5e,0x86,0x7f,0x83,0x19,0x69,0xa7,0xfe,0x8b,
+  0x95,0x74,0x05,0x33,0xfc,0xf3,0xd2,0x07,0xa2,0x15,0xf6,0xe2,0x85,0x60,0x9e,0x11,
+  0x15,0xc7,0xd4,0x27,0xbd,0xcb,0xa5,0x5f,0x7b,0xac,0xae,0x5f,0xdb,0xa1,0xb1,0x31,
+  0xfa,0xcb,0x2c,0x32,0x72,0xc1,0xce,0xb2,0xb0,0x5a,0x06,0x35,0xab,0x85,0x8d,0xa1,
+  0xb0,0x3a,0xf6,0xb9,0x71,0xe3,0xc4,0xf5,0x5f,0xf5,0x69,0x9b,0x1f,0x1b,0x8d,0x0f,
+  0x2c,0xdf,0x6f,0xd2,0x47,0xbc,0xc8,0xeb,0xa4,0x1a,0x61,0xfa,0x5f,0xde,0x7e,0xe9,
+  0x23,0xee,0x1f,0x66,0x0e,0xea,0x25,0x33,0x53,0xff,0x05,0x93,0x80,0xfc,0x87,0x27,
+  0x90,0x8a,0xf0,0xcf,0x03,0x2d,0xf1,0x13,0xf6,0x46,0xf6,0xcb,0xa6,0x5d,0x5a,0x39,
+  0xba,0xdf,0x18,0xf6,0x82,0x1b,0xdb,0x10,0xcf,0x59,0xd3,0xe2,0x77,0x36,0xbb,0xb7,
+  0x33,0xf5,0x5f,0xf0,0xe7,0x03,0xfc,0x3a,0x9c,0x3a,0xd2,0xaa,0xb3,0x6b,0x89,0xff,
+  0xbb,0x81,0xd1,0x2e,0xbe,0xfd,0x85,0x2a,0x09,0x18,0x27,0xf9,0x75,0x96,0x89,0xaf,
+  0xd8,0xd7,0x31,0x5d,0xfc,0x1b,0x34,0x88,0xf1,0x94,0x3e,0xe4,0x79,0x6b,0x51,0xea,
+  0xc4,0x5e,0xab,0xee,0x2f,0x6e,0xb1,0x92,0x5a,0xfb,0x17,0x21,0x25,0xac,0xce,0x05,
+  0xc5,0x2e,0x33,0x7e,0xa6,0xb5,0x0f,0x32,0xfe,0x0d,0x33,0xa3,0xb5,0xba,0xc1,0xdb,
+  0xc3,0x88,0xcd,0x61,0x0e,0xf7,0x61,0x66,0x75,0x7f,0x77,0xda,0xde,0xdf,0xcd,0xe0,
+  0x5a,0x78,0x64,0xd8,0xb6,0xbe,0xc7,0x1e,0xe3,0xc4,0xbf,0x12,0xc8,0x7f,0xd8,0x6c,
+  0x51,0x73,0x5c,0x20,0x5c,0xf3,0x37,0x66,0xaf,0x17,0x96,0x8f,0xf5,0xf1,0x3a,0x32,
+  0x12,0x49,0x2c,0xf2,0xc2,0x75,0x1c,0x51,0x1b,0x67,0x95,0x6d,0xfc,0xa5,0x5d,0x51,
+  0xea,0x4c,0x6f,0x86,0x67,0xbb,0xcd,0xa9,0x4b,0x7a,0x0d,0xfe,0xf5,0x7a,0x13,0x96,
+  0x89,0xf9,0x2d,0xcb,0x7d,0xe9,0xb6,0xd9,0x3c,0xff,0x70,0x40,0x2a,0xb5,0x13,0x11,
+  0xfb,0x33,0xfc,0xf3,0x7b,0xcc,0xaa,0x73,0xc8,0x9f,0xa0,0xb3,0x58,0x49,0x4a,0x7c,
+  0x27,0x43,0x52,0xd7,0x89,0xaf,0xaf,0x6d,0x71,0xe6,0x1f,0xce,0x56,0x1f,0x16,0xab,
+  0x14,0xe6,0x16,0x96,0x32,0xb1,0x30,0x36,0x66,0xc8,0xa5,0xbf,0x4c,0x19,0xed,0xa1,
+  0x15,0x73,0x71,0x5d,0x87,0xd1,0x8f,0xa7,0x95,0x2e,0x3b,0xfc,0xb1,0x05,0xf6,0x2f,
+  0xf6,0xe7,0x3d,0x62,0x05,0xed,0xb4,0x03,0x22,0xd6,0xfe,0x85,0x19,0x53,0x41,0x9b,
+  0xea,0x3c,0x5b,0x38,0xa0,0x0f,0x80,0x58,0x95,0xc5,0x4a,0x2a,0x04,0x3b,0x98,0xe7,
+  0xc9,0xd6,0x2b,0x25,0x3a,0x5a,0xea,0x07,0x33,0xf5,0x5f,0x78,0xcf,0x07,0x39,0xc5,
+  0x59,0xf6,0x73,0x71,0x86,0x1e,0xc1,0x57,0xd3,0x03,0xbc,0x5e,0xef,0x4e,0xf0,0x2e,
+  0x74,0x72,0x44,0x66,0xfe,0x98,0x6e,0xfb,0x63,0xd9,0xf1,0x2f,0xd3,0xa2,0xc8,0x63,
+  0x89,0x52,0xc3,0xf6,0x3c,0xbf,0x21,0xa3,0x10,0x33,0xe3,0x73,0xb8,0x60,0x44,0x64,
+  0x9f,0xcb,0x3f,0x9c,0xa0,0xfe,0x8b,0x65,0xc2,0x7b,0x4f,0x4e,0xda,0x87,0x49,0x1a,
+  0xd4,0x6b,0x48,0x21,0xf9,0xa2,0x6c,0x25,0xf1,0x1e,0x6f,0xaf,0xb1,0xa3,0xc9,0x3b,
+  0xe0,0xd1,0x6b,0xbc,0x2c,0x3b,0x2d,0xc7,0x79,0xa2,0xaf,0x13,0xff,0x7a,0x93,0x74,
+  0xc0,0xb3,0xd3,0xb1,0x49,0xac,0x22,0xeb,0xcc,0xe9,0x49,0x98,0xf0,0x0a,0xa4,0xed,
+  0x4d,0x33,0x20,0xa6,0x92,0xe9,0xf8,0x66,0xfb,0x99,0x17,0x30,0x1a,0xa7,0x82,0xef,
+  0xc4,0x16,0xc4,0xc2,0x76,0x21,0x98,0x1d,0xff,0x3a,0xc3,0x76,0x22,0x8f,0x45,0x6f,
+  0x62,0xe4,0x11,0xbf,0x82,0x5c,0x0d,0xe6,0x75,0x21,0xff,0x51,0xb9,0x93,0xc4,0x60,
+  0x32,0x8b,0xbc,0xc2,0x0e,0x41,0x37,0x0d,0x46,0x43,0x24,0x04,0xa0,0xcb,0xe3,0x95,
+  0xdb,0x58,0x97,0xf8,0x3a,0x7f,0x2e,0xcc,0xc2,0x9f,0x90,0x8e,0x83,0x55,0xb1,0xe9,
+  0x9b,0xf1,0x96,0x10,0xa6,0xc7,0x18,0x4f,0xf0,0x1e,0xd3,0x12,0xf9,0x62,0x8a,0x72,
+  0x5d,0x62,0xe5,0x6d,0x08,0xdb,0xf9,0xf7,0xd1,0xa7,0xf7,0x41,0x8b,0x17,0xbe,0xcf,
+  0x52,0x58,0xb8,0x86,0x61,0x3e,0x3f,0xe4,0xaa,0x63,0xe4,0x90,0x19,0x59,0x5a,0x50,
+  0x5a,0x84,0x10,0x26,0x1c,0x9f,0xfa,0x94,0xf4,0x59,0x72,0x9e,0x76,0xbf,0xec,0xdb,
+  0x59,0xfc,0xae,0x08,0x50,0xba,0xdf,0xd7,0xd3,0x59,0x4d,0x2e,0x0c,0x84,0xcf,0x79,
+  0x77,0xb7,0xbd,0x47,0x8f,0x74,0xd4,0x1e,0xf4,0xa5,0x1e,0xa9,0xf2,0x1f,0xe9,0xe8,
+  0x36,0x8e,0xa7,0xca,0xcd,0x26,0x07,0x7f,0x5d,0x24,0x75,0x46,0xfe,0x80,0x74,0x94,
+  0x2d,0xc1,0xba,0x98,0x3a,0xa4,0x9f,0x57,0x98,0xe0,0xda,0xc5,0x0e,0x58,0xaf,0x61,
+  0x0c,0x10,0x73,0x68,0x06,0xc0,0x99,0xc2,0xeb,0x8b,0x85,0x5a,0x0c,0x78,0xb3,0x35,
+  0x67,0xf0,0x97,0xa1,0x3d,0x45,0x0f,0xc9,0x91,0x06,0x7c,0xde,0xe5,0xe7,0x48,0x68,
+  0x60,0x61,0xb2,0xf3,0x46,0xf1,0x30,0x2b,0x12,0x6c,0x44,0x44,0xf6,0x01,0x13,0x62,
+  0x56,0x2e,0xdc,0x16,0x1e,0xb8,0x3e,0xe5,0xab,0x24,0x47,0x94,0x6e,0xd3,0xd7,0x8d,
+  0xa5,0x85,0x5a,0xb7,0xe1,0xc6,0x5f,0xd3,0x49,0x87,0x5e,0xd5,0xac,0x1c,0x10,0x2f,
+  0x92,0xe3,0xb2,0xdf,0x54,0x7e,0x22,0x7d,0x83,0xac,0x31,0x66,0xe1,0xfc,0xbc,0x3f,
+  0xaf,0xb3,0x94,0x55,0x89,0x62,0x58,0x59,0x87,0x0b,0xae,0x5a,0x41,0xfe,0x4d,0x0f,
+  0x9b,0xea,0x33,0x30,0x99,0xbf,0x19,0x08,0x1b,0x19,0xfc,0x95,0xce,0xf9,0xbc,0xd1,
+  0x4a,0x56,0xc4,0x84,0x3a,0x7e,0x6a,0x44,0x3d,0x5e,0xb1,0x55,0x5e,0x6d,0xe0,0x61,
+  0x51,0xd1,0x99,0xd2,0x27,0xf1,0xd4,0xa8,0x7b,0xfe,0xc2,0xc2,0xbd,0x66,0xb2,0xff,
+  0xaf,0x30,0x97,0xb8,0x8d,0x92,0x5e,0x58,0xee,0x02,0xa1,0xd3,0x64,0x07,0x4a,0x23,
+  0x99,0xfa,0x2f,0x79,0xa0,0x32,0x96,0xb7,0xbc,0xe1,0x55,0xa1,0x8d,0xea,0xc9,0x6b,
+  0x17,0x7b,0xbe,0x8c,0x01,0x1a,0x26,0xb2,0xbc,0x7c,0x55,0x62,0x6a,0xda,0xf3,0xcd,
+  0x69,0x5f,0xcd,0xdb,0xf5,0x54,0xd9,0x90,0x07,0x4f,0x14,0xbf,0x47,0x97,0x0c,0x5d,
+  0xc7,0x0d,0x16,0xa0,0x39,0x99,0xc9,0x3f,0x34,0x69,0xb0,0x21,0x7f,0xb6,0x78,0x4c,
+  0x7c,0x2e,0x27,0x94,0xfe,0x82,0xa0,0xb6,0xc2,0x1d,0x35,0xb3,0xcf,0x77,0x93,0xf4,
+  0x3e,0x7d,0xd2,0x40,0xfe,0x4c,0xcf,0x42,0xf3,0x82,0x19,0x1a,0x66,0xb7,0xdf,0x11,
+  0x3d,0x94,0xc6,0xf8,0xb2,0xff,0x48,0x05,0x8c,0x71,0xe5,0x1f,0x6e,0xf6,0x5c,0xd4,
+  0xea,0xfb,0xe4,0x5e,0xe9,0xa2,0xfc,0xbe,0x76,0xc0,0x44,0x81,0x47,0xfe,0xc4,0x9d,
+  0x95,0x2e,0x6a,0xdf,0x62,0xd4,0xf4,0xd2,0xbe,0x66,0x47,0x6b,0xfe,0x02,0xb9,0x9e,
+  0xf1,0x8b,0x8a,0xe3,0xf1,0xd7,0x37,0x49,0xb7,0xe1,0x9d,0x0d,0x4b,0xa0,0x86,0xc2,
+  0xad,0xe8,0x78,0x78,0x47,0xec,0x03,0xc9,0x23,0x98,0xa8,0xd0,0x83,0x61,0x6e,0x0d,
+  0xd5,0xbe,0xca,0xe1,0xe5,0x20,0xf3,0xfc,0x43,0xfb,0x79,0x3f,0x6c,0xe1,0x1d,0x81,
+  0xe5,0x5d,0x18,0x4a,0x4c,0xfa,0x0f,0xed,0x31,0x2d,0x40,0x3d,0xcd,0x0c,0x76,0x55,
+  0xf6,0xab,0xf7,0x62,0xfe,0x06,0x66,0xb9,0x9f,0x13,0x27,0xd3,0x5d,0x7a,0x59,0xbf,
+  0x7a,0x0f,0xb1,0x0d,0x71,0x72,0x7c,0x95,0xce,0x84,0xc0,0x5e,0xb6,0x74,0x07,0x00,
+  0x7f,0xed,0xa0,0x15,0xfa,0x8d,0x2b,0xb1,0x2a,0x9c,0x96,0xbd,0xae,0x44,0xe3,0x2f,
+  0x23,0x99,0x3f,0x13,0x62,0x36,0x57,0x6d,0x2c,0x1b,0x5c,0x70,0x9f,0x7f,0x8a,0xb9,
+  0x6b,0x4b,0xd9,0xbb,0xea,0x37,0xe3,0x53,0x86,0x76,0x6d,0x28,0x7b,0x1d,0x0d,0x73,
+  0x55,0xa2,0x72,0x18,0xe6,0xd9,0xb4,0xf1,0xd7,0x11,0xd2,0x9d,0xd4,0x4f,0x5e,0x13,
+  0xf0,0x30,0x7a,0x9c,0xb4,0xe7,0x61,0xf1,0xb7,0x34,0xd5,0x1e,0xec,0x53,0x67,0x88,
+  0xc7,0xc5,0xb6,0x0e,0xbd,0x4f,0x8d,0xf8,0x7d,0x78,0x0c,0x35,0xa0,0xd6,0x79,0x0a,
+  0x30,0xff,0x70,0x18,0x0c,0xdf,0xbc,0x36,0xb3,0x22,0xcd,0xf2,0x0f,0x75,0x8e,0xbf,
+  0xf6,0x18,0x97,0xe9,0xcd,0x89,0xfc,0xb7,0x55,0x8c,0x7f,0x01,0x10,0x3b,0x23,0x5d,
+  0x20,0x97,0x7b,0xeb,0x37,0xae,0x7b,0x43,0x1a,0xd1,0x8f,0xb5,0x97,0x23,0xff,0xc6,
+  0x1c,0x72,0x39,0xd6,0xb5,0x09,0xd5,0xbe,0xc8,0x65,0xa5,0x2b,0x01,0xd0,0xec,0x1a,
+  0x72,0xcc,0x8c,0x60,0x6a,0xe2,0x88,0x53,0xff,0x65,0x8c,0x34,0xd7,0x82,0x6f,0xc5,
+  0xfd,0x3a,0x96,0xbc,0x64,0x8c,0x4c,0xe1,0xb0,0x8b,0x8e,0x68,0xb5,0x0a,0x7a,0x71,
+  0x31,0x00,0x62,0xe2,0x22,0xda,0x96,0xa4,0xe0,0x04,0x32,0x91,0xe5,0xd0,0x48,0x29,
+  0x0b,0xd0,0xb8,0xe2,0x5f,0x67,0x69,0x08,0x99,0xe4,0xfb,0x48,0xaf,0x1c,0x36,0xf2,
+  0x1f,0x95,0x96,0xa1,0x2f,0xca,0x74,0x9c,0x49,0x3f,0x92,0xa2,0xac,0x46,0x66,0xfb,
+  0x44,0x58,0x87,0xa5,0xf4,0x1b,0x60,0x70,0x67,0xb2,0x9f,0x86,0x39,0xfe,0xca,0xe4,
+  0x1f,0x1a,0x7e,0xee,0x24,0xbf,0x42,0x66,0xf2,0x22,0x9d,0xd5,0xac,0x18,0x4a,0x3c,
+  0x2d,0x76,0x18,0x7e,0xa2,0xae,0x45,0x79,0x23,0xea,0x97,0x95,0x76,0xd1,0x4f,0x7a,
+  0x4c,0x3f,0xc9,0x47,0xcd,0xdf,0x0e,0xd3,0xef,0xc6,0x5f,0x42,0x05,0xdd,0x5d,0xba,
+  0xb4,0x69,0xf1,0xfa,0xf8,0x20,0x79,0x94,0xf8,0x8d,0xbc,0x94,0x38,0xd5,0x58,0xdd,
+  0x5c,0x45,0xae,0xa3,0xa2,0x99,0xa4,0x78,0x1d,0x2c,0x68,0x4d,0x11,0xbf,0xa8,0x90,
+  0x0d,0xba,0x9c,0xca,0xc3,0x20,0xce,0x86,0xd3,0x84,0xc6,0xfc,0xdc,0x0f,0x77,0xf0,
+  0xd7,0x0c,0x5d,0x8f,0x96,0x02,0x1c,0x78,0xb0,0x55,0x98,0x16,0x55,0x8a,0x8a,0xe4,
+  0x44,0xab,0xbe,0x22,0xea,0x29,0x12,0xfb,0x3a,0x5a,0x19,0xc9,0x06,0x53,0x04,0xf3,
+  0x47,0x03,0x45,0x00,0xbb,0xba,0xb8,0x31,0x18,0xc7,0xfa,0x2f,0xc0,0x05,0xcf,0x59,
+  0xf1,0xaf,0x9c,0xe5,0x2c,0x24,0x11,0x44,0x7a,0xff,0x4d,0x81,0x6e,0x92,0xff,0x63,
+  0xb5,0xac,0xa1,0x9f,0xe5,0x1f,0x16,0x9f,0x6e,0x30,0x9b,0x31,0xdb,0xb0,0x3c,0x4d,
+  0xba,0xc1,0x58,0x98,0xa3,0x96,0x19,0xc3,0x60,0x28,0x39,0x52,0xaf,0xd1,0xdf,0xdc,
+  0xcd,0xf1,0x17,0xfb,0x5d,0x9b,0xae,0x39,0x47,0xe6,0x16,0xfd,0xbc,0x6f,0xdd,0x80,
+  0x7f,0xb0,0x69,0x54,0x64,0x21,0xad,0x73,0x98,0x7f,0xd8,0xc4,0xd9,0x0e,0x8b,0x6c,
+  0x46,0xc4,0x12,0xdb,0xb0,0x34,0xc2,0xa2,0xa3,0x1a,0x43,0x6d,0xbf,0x9b,0x14,0xe3,
+  0xf8,0xeb,0x9c,0x9b,0x76,0x23,0xcc,0x8d,0x17,0x49,0x38,0xf6,0xbf,0xbe,0x2f,0x7d,
+  0x44,0x2f,0xd1,0xf0,0x72,0xdf,0xaf,0xa5,0x69,0xf4,0x52,0xb2,0x7e,0x79,0xfe,0xaf,
+  0xa5,0x59,0xed,0x97,0xb6,0xde,0xff,0x75,0xdf,0xc9,0xb6,0x59,0xfa,0x8b,0xdb,0xc3,
+  0x3c,0x9b,0xce,0x5d,0xff,0x65,0x87,0xb4,0xa6,0x53,0x8b,0x7f,0x63,0xeb,0x46,0xf5,
+  0x01,0xf1,0x74,0xf3,0xec,0xa6,0xad,0x25,0xea,0x8f,0xa5,0x32,0xad,0x07,0x56,0xf0,
+  0xf6,0xa4,0xf8,0x84,0xd1,0xd3,0xfc,0xf7,0x09,0x55,0x17,0x03,0x62,0xd2,0x60,0x19,
+  0x89,0x99,0xfc,0x43,0xb9,0x4b,0xb6,0x69,0x37,0x04,0xdb,0xb0,0x92,0x39,0xb5,0x19,
+  0x06,0x1a,0xfe,0x26,0xa3,0xab,0x68,0x45,0x73,0xde,0x46,0x17,0x23,0x87,0xd8,0x4a,
+  0x58,0xe4,0xd1,0x9d,0x7f,0xd8,0x01,0x3b,0xe3,0x26,0x11,0xb3,0x04,0xa7,0x5b,0xe9,
+  0xa6,0xc4,0xdf,0xa4,0xae,0x17,0x07,0x63,0x28,0x4e,0xaa,0x16,0x8a,0x53,0xe9,0xee,
+  0xc2,0xbf,0x9f,0xaf,0x6c,0x40,0xda,0x0d,0xa5,0x0a,0x57,0x50,0xa6,0x5b,0x78,0x68,
+  0x35,0x93,0x7f,0xa8,0x8f,0x9a,0x78,0xd2,0x5e,0x3c,0x28,0xc2,0xfc,0x2c,0xf3,0xfd,
+  0x0b,0xca,0x52,0x27,0xc3,0xcd,0x0b,0x36,0x14,0xbf,0xa1,0x8d,0x0e,0x84,0x9b,0x7d,
+  0x1b,0xd5,0xbf,0x26,0xa3,0xb7,0x47,0x9a,0xf3,0x37,0x4a,0x53,0xc9,0xa8,0x59,0xd5,
+  0xb2,0x68,0x93,0x7a,0x03,0x4c,0x66,0xad,0x0b,0x7f,0xf1,0xfa,0x2f,0x44,0x52,0x6d,
+  0x7d,0x99,0x18,0xe2,0x68,0x85,0x93,0x64,0x18,0x59,0xc6,0x53,0x13,0x05,0xc0,0x68,
+  0x80,0xec,0x8c,0x51,0x33,0x12,0x43,0x43,0x19,0xd5,0x59,0xd0,0xcd,0xc9,0x3f,0x7c,
+  0x4c,0xb0,0xd8,0x0e,0xd3,0xb2,0x49,0xba,0x35,0x1f,0xed,0x2c,0xa3,0x23,0x2d,0x08,
+  0xb2,0xbe,0x74,0x5a,0xeb,0xc7,0x8a,0x30,0xfa,0x35,0x9d,0xf4,0x47,0xc3,0x72,0x3e,
+  0x12,0x41,0xf7,0xcf,0x0f,0x83,0xab,0x51,0xac,0xcb,0x23,0x62,0x38,0x2b,0xff,0xb0,
+  0x96,0xee,0xd7,0xab,0x3b,0x4a,0xd3,0xf3,0x87,0xc8,0x4f,0xe5,0xa5,0xd4,0x37,0x24,
+  0xad,0xac,0xb8,0x4c,0xd9,0x99,0xcc,0x08,0x79,0x95,0xce,0xa2,0x9f,0x79,0x5d,0x5a,
+  0x2e,0xbf,0x2a,0xde,0x94,0x50,0x96,0x01,0x10,0x7b,0x95,0xf8,0x69,0xe7,0xbb,0xf1,
+  0x5a,0x65,0x3f,0x4b,0x44,0xcc,0xe0,0x2f,0x83,0xa4,0xd2,0xc1,0xd3,0x8a,0xdc,0x00,
+  0xfb,0x97,0xac,0x9b,0xaa,0xde,0x50,0x4e,0x7a,0x0c,0x9b,0xe4,0x90,0xea,0xa6,0x32,
+  0xbb,0xc1,0x0b,0xae,0x48,0x85,0x91,0x87,0x35,0xce,0x6d,0xed,0x31,0xa4,0xe6,0x28,
+  0x90,0x77,0xc0,0xcb,0x94,0xe1,0x2f,0x8d,0xe3,0x2f,0x8d,0xcc,0x44,0xfc,0xd5,0x2c,
+  0x1e,0x15,0x1e,0x07,0x14,0xe0,0x59,0xfe,0xa0,0x46,0xb6,0x89,0x37,0x9a,0x6b,0x5a,
+  0x8a,0xba,0xc9,0xff,0x52,0x6e,0x48,0xe7,0xa5,0xc5,0xfb,0xc9,0xff,0xa2,0x53,0x0d,
+  0xe5,0x5e,0xb1,0x9e,0xfc,0x8b,0xc9,0xf3,0xe2,0x74,0x2b,0x41,0x6e,0x88,0x5f,0x67,
+  0xbb,0x52,0x84,0x87,0x60,0x5c,0xf2,0x03,0x4b,0x9b,0xd5,0x11,0xf1,0x6a,0xf9,0x69,
+  0x76,0xf6,0xe5,0xe7,0x8a,0xcc,0x0a,0x16,0x82,0xfd,0x82,0xde,0x14,0xcb,0x1f,0x52,
+  0xaf,0x86,0xb9,0xe9,0x4a,0x2f,0x5a,0xae,0x5e,0x2b,0x9f,0x03,0x83,0xe5,0x1f,0x6a,
+  0x1c,0x7f,0x31,0x9e,0x49,0xe3,0x06,0x57,0x4a,0x21,0x7b,0x31,0x62,0x3e,0x9b,0x49,
+  0x3e,0x40,0xfd,0xe5,0x10,0xc1,0x5a,0x8f,0x3a,0xf4,0x0a,0xfa,0x78,0xb1,0x18,0x1e,
+  0x82,0xd9,0xf8,0xcb,0x8a,0x7f,0x09,0x1f,0x18,0x23,0x48,0x29,0x7f,0xb2,0xfc,0xab,
+  0x18,0xff,0x4a,0x17,0x20,0xed,0x7c,0x7f,0xa2,0xee,0x0d,0xf4,0x06,0x09,0xb2,0xcd,
+  0xfb,0x7a,0x1a,0x23,0xe4,0x32,0x4d,0x2d,0xf7,0x9e,0x04,0xb7,0x10,0x65,0x97,0xe1,
+  0x6b,0xcc,0x82,0x6f,0xc8,0xfc,0xc3,0x01,0x2b,0xfe,0x25,0xac,0xd7,0xbb,0x28,0x80,
+  0xa3,0x12,0x70,0x89,0x57,0x91,0xc0,0x50,0xe7,0x52,0xf8,0xa2,0xed,0x5b,0x2b,0x11,
+  0xb1,0x9a,0xf4,0xc0,0x56,0xd8,0xad,0xbe,0x2e,0x4d,0x26,0xdd,0xba,0x1e,0x53,0xd2,
+  0x28,0xe9,0x95,0x84,0x1d,0xc4,0x10,0xf7,0x91,0xc7,0xb5,0x1b,0xcd,0x4c,0xfe,0xa1,
+  0x46,0x36,0x96,0xec,0x34,0xca,0x0e,0x2a,0xc3,0xf1,0xc9,0x58,0xda,0xdc,0xbf,0xe0,
+  0xce,0x5c,0xb8,0x0e,0xca,0x5f,0xb6,0x88,0xa7,0xe4,0xa7,0xf5,0xb2,0x5e,0xf5,0x8e,
+  0xf8,0x5d,0xfa,0xae,0x3c,0xa1,0x09,0x70,0x1c,0x52,0x73,0x4c,0xc5,0x3c,0x46,0x8d,
+  0xac,0x55,0xd8,0x3c,0xbf,0x60,0xc7,0xbf,0x5e,0x60,0x54,0x60,0xca,0x2c,0x96,0xa4,
+  0x11,0x18,0x50,0xf5,0x5c,0x42,0xa9,0x11,0x1c,0x50,0x66,0x02,0x10,0xeb,0x36,0x60,
+  0xdb,0xda,0x28,0xe6,0xc3,0x9d,0xa0,0x2f,0x0d,0x4c,0xf7,0xc0,0x4b,0x78,0xb8,0xe2,
+  0x23,0xf5,0x21,0xf1,0xa7,0xfa,0x93,0xfd,0xac,0x00,0xf0,0xa4,0x9d,0x7f,0xf8,0xc4,
+  0xbc,0xf3,0x04,0x40,0x16,0xd6,0x7f,0x81,0x7f,0x38,0x50,0xf0,0x94,0x74,0x23,0x9e,
+  0x1f,0x9a,0xc1,0x3a,0xf0,0x37,0xce,0x4f,0xe9,0x7e,0x01,0x9e,0xaf,0xbf,0x37,0x46,
+  0x13,0xa1,0x93,0xde,0x9e,0xb6,0x0a,0xfd,0x82,0xf9,0x4c,0xda,0xb7,0x59,0xaa,0x14,
+  0x8f,0xf0,0x44,0x97,0xf7,0xf8,0xf3,0x95,0x30,0xde,0xc5,0xd5,0xe9,0x28,0xd8,0x88,
+  0xa0,0x58,0xde,0x6f,0xfa,0xb6,0xab,0x43,0xe2,0x79,0x05,0x0b,0x63,0xdb,0xde,0xd5,
+  0x47,0x39,0x5f,0xca,0x53,0x28,0xe1,0x37,0xc0,0x9e,0xb8,0xf3,0xbc,0x4c,0xef,0x8c,
+  0x31,0x62,0xe3,0x2f,0x8e,0xe3,0xb4,0x11,0x3c,0x7f,0x46,0xfc,0x75,0x8a,0x3c,0x27,
+  0xd7,0x1c,0xbc,0x1e,0xc1,0xf5,0x1f,0xb8,0x10,0x73,0x98,0x5c,0x36,0x6b,0x4c,0xdf,
+  0xe9,0x36,0xc6,0xbf,0x61,0x3c,0x34,0x24,0x9d,0x93,0x31,0x58,0xb6,0xce,0x84,0x96,
+  0xa3,0xbc,0x46,0x2c,0xcd,0x9f,0xaf,0x56,0xf9,0xff,0x22,0x17,0x0e,0x6e,0x0d,0x29,
+  0x9b,0x18,0x37,0xc2,0x2c,0xf3,0xfa,0x4d,0xe2,0x3b,0xfa,0x9e,0x7e,0xe6,0x3f,0xeb,
+  0x2d,0x23,0x4d,0x7e,0x53,0xdd,0x86,0x65,0x3b,0x09,0x7f,0xec,0xa1,0x4d,0xe2,0x9b,
+  0x46,0x07,0xc6,0xb6,0x56,0x8b,0x95,0xa4,0xe3,0x2f,0x75,0x96,0x7f,0x68,0xe3,0xaf,
+  0xe9,0xe8,0x75,0xc7,0x4a,0x37,0xf1,0x92,0x2e,0x53,0xdd,0x5e,0xf4,0x9e,0xb6,0x97,
+  0x2e,0xe5,0x81,0xb0,0x94,0xe1,0xc7,0xf4,0x69,0x2c,0xff,0xf1,0xb7,0xe4,0xad,0x47,
+  0xda,0x5e,0x56,0x02,0x53,0x34,0x95,0x0d,0xce,0xce,0x3f,0x2c,0x37,0x98,0xda,0xd7,
+  0x8b,0xe4,0x31,0xa9,0x02,0xe9,0xf8,0xfa,0xe1,0x6e,0x49,0xf6,0xb3,0xa4,0xd0,0x2d,
+  0x24,0xc9,0xf9,0x37,0x52,0x44,0x57,0x6e,0x24,0xe2,0x51,0x8d,0x7a,0xd3,0x18,0x02,
+  0xf0,0x8a,0x14,0xaf,0xe3,0xe4,0x1f,0xd2,0x9c,0x15,0xa4,0x36,0x16,0x36,0x82,0xa8,
+  0xff,0x05,0xeb,0xf5,0x8a,0xc5,0x07,0x8b,0x41,0x2e,0xb5,0xac,0xa9,0xa7,0x02,0x16,
+  0x45,0x2c,0x0f,0x92,0x0f,0x9b,0xbb,0xef,0xca,0xa7,0xd2,0xa0,0x78,0xd0,0x8f,0xa1,
+  0x31,0xb5,0x02,0xb6,0xfe,0x6e,0x73,0x61,0xaa,0xd8,0xa9,0xff,0x02,0x48,0x15,0xab,
+  0x27,0x52,0xb3,0x74,0xb1,0x1d,0x5c,0xbe,0x5f,0xb3,0x32,0xf3,0x8b,0x06,0x3f,0x84,
+  0x07,0x7f,0x03,0x3c,0xfc,0xbe,0xf2,0x8b,0x1a,0x78,0x8c,0xb7,0xae,0x43,0xfc,0x35,
+  0x42,0xaa,0x0f,0x4f,0x32,0x25,0x07,0xb5,0x65,0xd5,0x7f,0x55,0x67,0x1d,0x59,0x5c,
+  0xe6,0xb2,0x5f,0x23,0xb0,0x82,0xc7,0x01,0x05,0xd8,0x47,0x1f,0x94,0x55,0x7b,0xe1,
+  0xf9,0x86,0x77,0x80,0xe1,0xaf,0xfa,0x2c,0xfc,0xe5,0xe8,0x2f,0xe3,0xf4,0x66,0x0c,
+  0x93,0x91,0x1c,0x76,0x62,0xd8,0xcb,0x52,0x04,0x4b,0x2a,0x3d,0x0d,0xaf,0x8b,0x9d,
+  0xf1,0x2a,0x13,0x26,0xd3,0x0a,0x84,0x65,0xd5,0x7f,0x8d,0xd7,0x43,0xec,0xb6,0x8d,
+  0x36,0x7c,0xc5,0xb1,0x8c,0x44,0x11,0xb0,0xb0,0x6e,0x85,0xc6,0xb0,0x54,0xd6,0x3e,
+  0x8f,0xca,0xe2,0xdf,0x70,0x74,0xdf,0x6c,0x23,0x53,0xff,0x55,0x95,0xe4,0xd4,0xf4,
+  0x42,0x55,0x87,0xb2,0x4f,0x4c,0xeb,0xc8,0x0b,0xa1,0xd4,0x31,0x82,0x08,0x36,0xc6,
+  0x5d,0xff,0xe5,0x4e,0x8d,0x66,0x2c,0x34,0x23,0x07,0xf9,0xb9,0x04,0x05,0x27,0x39,
+  0xe6,0xe5,0xa5,0x3d,0x11,0x12,0xec,0xc1,0x8c,0x44,0x91,0x1d,0x74,0x38,0xfe,0x73,
+  0x9f,0x13,0xff,0x52,0xb2,0x20,0xf0,0x22,0x56,0xaf,0x27,0x59,0x45,0x79,0x57,0xc8,
+  0x5c,0x40,0xd0,0x7f,0x86,0x5d,0x75,0x18,0x23,0xeb,0xe3,0x30,0x79,0x20,0x83,0x97,
+  0x27,0xd4,0x5f,0xb6,0x8d,0xf3,0x24,0x7c,0x90,0x65,0x7a,0x1f,0xc1,0xad,0xcd,0x0e,
+  0xb5,0x60,0xf6,0x3e,0xfb,0x1a,0xde,0x6d,0x99,0xef,0xe3,0x8e,0x7f,0x8d,0x9b,0x9f,
+  0x3d,0x04,0x59,0xd4,0xf8,0xfc,0x10,0xc5,0x51,0x04,0x83,0xa7,0x00,0x8f,0x23,0xfa,
+  0x03,0xdb,0xc5,0x6a,0x7b,0x7e,0x5c,0xf5,0x5f,0xe3,0xd7,0x0b,0x9e,0x82,0x01,0x3b,
+  0x70,0x69,0x64,0xd4,0x52,0xd8,0x49,0x05,0xce,0xf3,0xd5,0xa2,0x37,0x66,0xad,0x57,
+  0x76,0xfd,0x97,0x4d,0xb5,0x67,0x19,0x3b,0x19,0xfe,0x12,0xcf,0x63,0xf0,0x25,0x16,
+  0xb5,0xba,0x30,0x76,0xf3,0x2b,0x6c,0x19,0x54,0x90,0xa0,0xcf,0x8a,0xcb,0xb8,0xea,
+  0xbf,0x3e,0xe4,0x91,0xac,0xa3,0x19,0x63,0x98,0xa4,0xb8,0xf1,0x9c,0x5c,0x47,0x38,
+  0x23,0x62,0xaa,0x8e,0xac,0x0d,0x49,0xfd,0x22,0x86,0xbd,0xbc,0x5a,0x9b,0x97,0x38,
+  0xf1,0x2f,0x0b,0x7f,0xed,0xe3,0xd1,0xc9,0x2c,0x7d,0x87,0x4b,0x0e,0x29,0x25,0x0b,
+  0x8d,0x4d,0xe2,0xc6,0x3f,0xf0,0xa3,0x8f,0xb9,0xb8,0x5e,0xa7,0x0c,0x0b,0x91,0x8d,
+  0xd7,0x5f,0x76,0xeb,0x60,0xf2,0x77,0x2f,0x3f,0x99,0x74,0xd6,0xcb,0x6b,0xc5,0x34,
+  0x4d,0x70,0x4e,0xaa,0xec,0xf5,0x7a,0xdb,0xcd,0x7f,0xe8,0xd6,0x9d,0xe4,0x44,0x88,
+  0x16,0xc9,0x86,0x75,0x12,0xc8,0xa4,0x55,0x4c,0xa5,0xa5,0xa8,0x8f,0x9d,0xfb,0xc1,
+  0x06,0x34,0xd9,0x3e,0x5f,0xcd,0xaa,0xff,0xaa,0x4c,0x5f,0x97,0x35,0xcf,0x29,0xba,
+  0xc5,0x99,0x79,0xdd,0x0e,0x8d,0xc5,0x02,0x2b,0x8b,0x7e,0xcd,0xa6,0x57,0x89,0x66,
+  0xe6,0x39,0x9b,0x7f,0x3e,0x7b,0xdd,0xb5,0x94,0xc1,0x93,0x73,0x04,0x68,0x29,0x0d,
+  0xe0,0xfe,0xbe,0x83,0xac,0x38,0xa5,0xcc,0xdc,0xc0,0x8f,0x94,0x03,0x24,0xf3,0x9c,
+  0x66,0xf1,0xcf,0x47,0xec,0xdc,0x42,0x47,0xe4,0x2b,0xcc,0xfd,0xa8,0xf3,0xa4,0x3e,
+  0xe1,0xe5,0xfc,0xf3,0xf5,0x29,0xef,0xa0,0x34,0x62,0x1e,0xe6,0x81,0xb0,0x40,0x26,
+  0xfe,0x65,0xe1,0xaf,0x89,0xb5,0x95,0x33,0x49,0x86,0x60,0x14,0x8f,0x91,0xfd,0xf2,
+  0x75,0x64,0x06,0x8f,0xa9,0xff,0x1a,0x4b,0xa6,0x0d,0xce,0xa4,0x45,0x1c,0xb7,0x2c,
+  0x13,0x2f,0xe0,0xc4,0xdd,0x96,0x31,0x6a,0xc7,0xbf,0x32,0xf8,0xcb,0x15,0xbf,0x70,
+  0x8c,0x16,0x9b,0x6d,0xa3,0xd9,0x89,0x5f,0x60,0xe0,0x49,0x67,0x2d,0x1b,0x01,0xa3,
+  0xed,0x9e,0x30,0xfe,0x95,0x7d,0x1d,0x78,0x2a,0xef,0xb4,0xae,0x13,0x74,0x14,0xc1,
+  0xb0,0x8e,0x75,0x1a,0x6f,0x29,0x8a,0xdf,0xa0,0xed,0xb6,0xe3,0x20,0x0e,0xfe,0x72,
+  0x49,0xfd,0x3a,0xda,0xca,0x99,0xba,0x24,0x8b,0x1a,0x51,0x64,0x52,0x53,0x8c,0x20,
+  0xbd,0x09,0x81,0x98,0x3d,0x78,0x0c,0xff,0xfc,0x38,0x31,0x6b,0xac,0xa1,0x4b,0x27,
+  0xfb,0x49,0xdd,0xb5,0x41,0xab,0xc5,0x13,0xa4,0xaa,0xbe,0x15,0x5a,0x34,0x6f,0x8e,
+  0x24,0x18,0x23,0xe3,0xe2,0x5f,0x13,0xe8,0x26,0x5b,0xf5,0x5f,0x84,0x45,0xc4,0x6c,
+  0x26,0x79,0x84,0x54,0x1a,0x0b,0x84,0xbd,0x74,0x5d,0x86,0x20,0x3d,0x53,0xff,0x35,
+  0xd1,0x7a,0xb1,0x40,0x18,0x26,0x8d,0xd4,0xf7,0x3e,0xc5,0x5b,0xa6,0x18,0x05,0xa9,
+  0x4c,0x44,0x6c,0xa6,0x7c,0x48,0xfc,0xa3,0xf1,0x2f,0x66,0x9c,0x27,0x56,0x45,0x58,
+  0x87,0x3b,0x22,0xa6,0x64,0x5a,0x1a,0x88,0x13,0xff,0xca,0xaa,0xff,0x1a,0x3b,0xcf,
+  0xf8,0x54,0x6a,0x0d,0x08,0xc4,0x58,0x91,0x17,0xef,0xf2,0x94,0xc2,0xea,0xb4,0xda,
+  0x81,0x30,0x3b,0xfe,0x95,0x5d,0xff,0x95,0xb5,0xee,0xf2,0x13,0x56,0xfe,0x21,0x00,
+  0x31,0x97,0x22,0x98,0x82,0x8c,0x2e,0xab,0x89,0xd7,0x50,0x36,0xe5,0x7a,0x9d,0xf8,
+  0x97,0xab,0xfe,0x6b,0xdc,0xfc,0xec,0xb6,0xc2,0x5e,0x7e,0x8c,0xe7,0xda,0xf7,0x73,
+  0x43,0xc1,0x26,0xe9,0x8d,0x06,0xbc,0x9f,0x83,0x1b,0xad,0x1b,0x9b,0xe1,0x2f,0xdd,
+  0xc6,0x5f,0x13,0xcc,0xb3,0xe9,0x8a,0x88,0x2d,0xb2,0x42,0xc6,0x06,0xa7,0xb2,0xc4,
+  0xe9,0xd5,0x16,0x0c,0x6a,0xd6,0xe0,0x5f,0xf3,0xf7,0x86,0xcd,0x3f,0x3f,0xe6,0xfe,
+  0x11,0x22,0x64,0xad,0xf5,0x9c,0x56,0x38,0x5d,0xeb,0x9c,0x27,0x37,0x9e,0x51,0x04,
+  0x73,0xf3,0xcf,0x67,0x28,0x0d,0x1d,0xa3,0x9a,0x76,0x58,0x46,0xd2,0xdd,0x85,0xd4,
+  0x88,0xd5,0x1d,0xea,0x50,0xbc,0x36,0x13,0xff,0x22,0xfc,0x3a,0x13,0xed,0x5f,0x8c,
+  0x7f,0x7e,0xa2,0x93,0x76,0xd3,0x32,0x3c,0xf3,0x27,0x8c,0x7f,0x8d,0x7d,0x3f,0x67,
+  0x14,0x43,0xb2,0xbb,0xfc,0xff,0x61,0x6b,0x07,0xdf,0xa9,0x5b,0xef,0xe7,0xfe,0xec,
+  0xf8,0x97,0x4b,0x7f,0x99,0x19,0xf5,0x31,0x1e,0x11,0x6b,0x9d,0x9b,0x5e,0xe7,0xea,
+  0xfa,0xa5,0x6d,0x7c,0x59,0xfc,0x05,0xef,0x3a,0x3c,0x2e,0xfe,0x95,0xd9,0x77,0x64,
+  0x5b,0x6d,0x79,0x6c,0x57,0xa3,0xa3,0xbf,0xbc,0x7d,0x4c,0xfc,0x8b,0xe4,0xb8,0xdc,
+  0xc2,0x8c,0x91,0xa8,0xd7,0x7d,0x56,0xc6,0x54,0xa6,0xab,0x60,0x44,0xfa,0x40,0x3b,
+  0xce,0x63,0x64,0xb3,0xec,0xae,0x81,0x4c,0xfd,0xd7,0x84,0xf3,0x83,0x81,0xc2,0x53,
+  0x4b,0x61,0x12,0xfa,0x54,0xa4,0x8e,0xdc,0x81,0xdb,0xd6,0xdd,0xe2,0x09,0x56,0xd1,
+  0xac,0xdc,0xeb,0x29,0x31,0xac,0xf9,0x71,0xd5,0x7f,0x4d,0x70,0x1d,0x91,0x5d,0x87,
+  0x05,0x13,0x07,0x9c,0x2e,0x8f,0x1d,0x5e,0x54,0x96,0x30,0x42,0x2a,0x77,0xfc,0x4b,
+  0x9f,0x68,0xff,0x22,0x3b,0x36,0x05,0xe7,0xb9,0xd4,0x52,0x1a,0x58,0xd7,0xa0,0x62,
+  0x85,0x3b,0x0d,0x45,0xf7,0x2b,0xf6,0xba,0x3b,0xf8,0x6b,0x22,0x7f,0xec,0x02,0x9e,
+  0x03,0x00,0xb6,0x52,0x16,0xd8,0xbc,0x85,0x16,0xe1,0xc9,0xa0,0x72,0x04,0x83,0x2f,
+  0x3b,0xa5,0x0a,0xe4,0xe0,0x72,0xc5,0xbf,0x28,0x99,0xc8,0x4f,0x60,0xd1,0x49,0xf4,
+  0xeb,0x2e,0x10,0x4b,0x05,0x98,0x69,0x84,0xf5,0xf0,0xf8,0x17,0x2a,0x05,0x3b,0xb1,
+  0x1b,0x57,0xfd,0xd7,0xd8,0x50,0x0b,0x33,0x58,0xe6,0x95,0x78,0x9c,0xcc,0x6d,0x77,
+  0x42,0x63,0x60,0xfc,0x92,0x1c,0x27,0x3e,0xd3,0x77,0x8f,0x3a,0xd3,0x8e,0x7f,0xb9,
+  0xea,0xbf,0xb2,0xfc,0xc3,0x4e,0xcb,0x48,0xda,0xfe,0xe1,0x06,0x47,0x2e,0x19,0x8c,
+  0xdf,0xa1,0x50,0xec,0xcb,0xea,0xce,0x8c,0x7f,0x98,0x9e,0x50,0x7f,0x39,0x63,0x24,
+  0x5d,0x7e,0xa6,0x73,0x1d,0xff,0x1b,0xe8,0x67,0x62,0x97,0x6c,0x38,0xd7,0x69,0xb6,
+  0xf1,0xd7,0x44,0xcf,0x69,0x30,0xc9,0x96,0xa9,0x4d,0x0e,0x12,0x97,0x34,0x58,0x03,
+  0xf3,0x33,0x61,0xfb,0x11,0x89,0x28,0x59,0xf1,0x2f,0x7e,0xf7,0x90,0xfc,0x15,0xe3,
+  0x6f,0x7e,0xe2,0x3c,0x17,0xcc,0xfb,0x62,0x5d,0xcd,0xcc,0x18,0xc4,0x42,0x30,0xd3,
+  0xa7,0x4b,0xb2,0x13,0xff,0xe2,0xe7,0x1b,0x5c,0xff,0x6b,0xcc,0x3c,0x6b,0xee,0x8c,
+  0xa9,0x4c,0x57,0x35,0x8b,0x91,0x89,0xcc,0x9f,0x77,0x02,0x61,0x0e,0xfe,0xfa,0x88,
+  0x5c,0x84,0xa7,0xdb,0xf7,0x81,0x94,0x22,0xff,0x33,0x50,0x63,0xe6,0xe1,0x5f,0xfd,
+  0x43,0x59,0x4d,0xbf,0xf7,0x03,0x69,0x2e,0xec,0x32,0x35,0xad,0x05,0xc3,0xf0,0xbc,
+  0xd7,0x53,0x49,0xf7,0x9d,0x14,0x87,0xc9,0x3b,0xa4,0x26,0x7d,0x3d,0x92,0xe1,0xbc,
+  0x80,0xa1,0xe7,0xa1,0x46,0x57,0xfe,0x61,0x6d,0x7b,0x41,0x5a,0x3a,0x27,0x06,0x48,
+  0xb5,0x51,0x3e,0xe0,0x39,0x27,0x5e,0x12,0x1f,0x0f,0xdf,0xd4,0xe7,0xf9,0x3d,0xf9,
+  0x21,0x3d,0x49,0xa7,0xa7,0x3d,0x17,0x19,0x22,0x9b,0x5e,0xa6,0x6e,0x12,0xdf,0x16,
+  0xd7,0x99,0xfe,0xf4,0x75,0xdb,0xc5,0x2a,0xad,0xb3,0xdd,0x7f,0x3a,0xc3,0xbf,0xd1,
+  0x9f,0xd3,0x8f,0xa9,0xb6,0xb4,0x73,0x66,0x43,0x07,0x69,0x13,0xb6,0xf6,0x45,0x67,
+  0x92,0xcf,0x6b,0xe5,0x4a,0x00,0x31,0x6c,0x3e,0x49,0xc0,0xdb,0xd7,0x33,0x03,0x26,
+  0xfc,0xfb,0x82,0x4e,0xae,0xd3,0x58,0x62,0xb6,0x8e,0x79,0x71,0x41,0x18,0x3c,0xbd,
+  0x37,0x1a,0xca,0xf0,0x1f,0xfe,0x4c,0x01,0xb4,0x35,0xb0,0x00,0xd9,0xef,0x11,0x4a,
+  0x8b,0x98,0x80,0x8a,0x6b,0xca,0x84,0xc0,0x1e,0xed,0x98,0xee,0xe7,0x8a,0xcc,0xca,
+  0xed,0xe4,0xba,0x0d,0xe2,0xdb,0xe4,0x07,0xc4,0x3f,0xac,0xfe,0x98,0x4c,0x35,0x3a,
+  0xe9,0xf4,0x98,0xb2,0x29,0xee,0xf0,0x1f,0xbe,0x4f,0xce,0xa7,0x67,0xbd,0x04,0x33,
+  0xff,0x18,0x3c,0x3b,0x61,0x53,0xc6,0xf2,0xd5,0x77,0x48,0x6d,0x2f,0x86,0x95,0x85,
+  0xfe,0xbe,0x70,0x8a,0xa5,0x4f,0xff,0xc6,0x0c,0x6b,0x2c,0x35,0xf1,0x43,0xd2,0x9d,
+  0x56,0xb7,0x4b,0xd5,0xf2,0x91,0xc3,0x2b,0x3f,0x00,0x44,0xe6,0xe2,0x3f,0xbc,0x6c,
+  0xcf,0x3c,0x5f,0x82,0xb6,0x33,0xe4,0x8a,0x7c,0x33,0xab,0x30,0xca,0x19,0x26,0x75,
+  0xf1,0xeb,0x53,0xe5,0x8c,0xc6,0xa1,0xe8,0xfa,0x93,0xd2,0x49,0x64,0xd8,0x3b,0xe8,
+  0x4b,0xff,0xe6,0xa2,0x76,0x89,0xfc,0x73,0x03,0x23,0xb7,0x64,0xdf,0xa7,0x59,0x7b,
+  0x42,0xbb,0xd0,0x34,0x2b,0xe5,0x0b,0x35,0xfe,0x1d,0x7d,0x4e,0x88,0xf4,0x7d,0x3e,
+  0x35,0xe9,0x8c,0xfe,0x9c,0x10,0xe6,0xc2,0x64,0xaf,0x18,0xb3,0x34,0x2c,0x1b,0x2c,
+  0x3b,0xec,0x01,0x8f,0x28,0xc1,0x8e,0xb3,0xc2,0xe6,0xc2,0xd6,0xe2,0x1b,0xf5,0x51,
+  0x05,0x7c,0xda,0x9d,0xd2,0xbf,0x3b,0xf1,0x2f,0xba,0x27,0xe9,0x4f,0xab,0xbf,0x17,
+  0x3f,0x2b,0xff,0xfc,0x6c,0x75,0x3a,0x3a,0xb2,0xe1,0x0a,0xfd,0xb9,0x58,0xfe,0x7a,
+  0xfe,0xb0,0xb8,0x0f,0x2b,0x05,0x66,0x7b,0x87,0xc5,0x2a,0xd2,0xd9,0x5f,0xa5,0x2f,
+  0x48,0xc0,0x46,0x76,0x80,0xfa,0xa3,0xf9,0xb2,0xb4,0x48,0xee,0x9a,0x87,0x64,0xda,
+  0x99,0xf8,0xd7,0x7c,0x40,0x5b,0x15,0x98,0x42,0xb3,0x8c,0x3c,0x86,0xf1,0xe5,0xd9,
+  0x45,0xef,0xc1,0xcd,0x2f,0xa6,0x3d,0xa9,0xdc,0xa3,0x1a,0x95,0xb7,0xc5,0x94,0xd0,
+  0xfc,0x82,0x79,0x6b,0xcc,0x60,0x19,0x78,0x17,0x34,0x67,0x47,0x68,0x1b,0xca,0x7e,
+  0xad,0x8b,0xee,0x98,0x47,0xfa,0x16,0xd4,0x15,0x59,0xf8,0x6b,0x44,0xf8,0x33,0xb2,
+  0x8f,0x1f,0xf7,0x15,0x19,0x28,0xf2,0xe5,0x41,0x14,0xf0,0x78,0x72,0x49,0xfa,0xba,
+  0xd9,0xe2,0xab,0x46,0x3b,0xcd,0xd1,0xf5,0xbb,0x8b,0xa6,0xe4,0x3d,0x48,0x2b,0x03,
+  0xea,0x62,0xf1,0x65,0xb2,0x6b,0xe3,0x0d,0xa7,0x85,0xe5,0x30,0xe6,0xd9,0xce,0x32,
+  0x54,0x64,0xbe,0xe8,0xd4,0x7f,0x19,0x23,0xa9,0x99,0x7d,0xbe,0x54,0x71,0x93,0xbf,
+  0x4d,0x8f,0x0c,0xf9,0xc2,0xf8,0x78,0xd2,0xd0,0x50,0x41,0x48,0x5a,0x48,0x5e,0x4a,
+  0x96,0x44,0x83,0x73,0x24,0xef,0xc2,0xb8,0x3f,0x18,0xf2,0x15,0x49,0xbd,0xfa,0x87,
+  0xc9,0x59,0x66,0x93,0x5f,0x5a,0x4b,0xce,0x62,0xd6,0xa2,0xd6,0xe6,0xe0,0xaf,0x14,
+  0x19,0x91,0xaf,0xe7,0x6f,0xb6,0xff,0x69,0x4c,0x39,0x5c,0x89,0x65,0x5f,0xdf,0xd1,
+  0xea,0xfb,0xf2,0x87,0x85,0xa7,0xc4,0x4b,0x45,0xf5,0xe4,0xe1,0xb3,0xd2,0x45,0x83,
+  0x3d,0xb9,0xf8,0x7c,0xfd,0x61,0x71,0x6d,0x9f,0x2f,0x56,0xfc,0x6d,0xc3,0xaa,0x4f,
+  0x71,0xf0,0xd7,0xa0,0x75,0xea,0xd8,0x36,0x28,0x1e,0xd1,0xc3,0x27,0xf3,0x77,0x34,
+  0x56,0x8a,0xef,0x7c,0x31,0x3c,0x22,0x3f,0xd3,0x76,0x46,0x1f,0x90,0x67,0xe9,0x0b,
+  0xf7,0x35,0xb2,0x77,0x38,0x99,0xcc,0x28,0x82,0xf5,0x22,0x73,0x51,0x92,0xbf,0x0a,
+  0xc0,0x6f,0x69,0x74,0xf4,0xbf,0x36,0x62,0xb4,0x0b,0x53,0x5f,0x4a,0xc8,0x2f,0x62,
+  0x37,0xbf,0x18,0x98,0x21,0x7d,0xdb,0x68,0x53,0x6e,0x3a,0xaa,0xfc,0x13,0xbc,0x76,
+  0x4e,0x90,0x32,0x12,0xb8,0x27,0x0e,0x3e,0x80,0x5c,0x49,0xbc,0xcd,0x0d,0x88,0xc8,
+  0x6e,0x32,0xd5,0x58,0xc3,0x29,0xf2,0x00,0xe7,0xd7,0x72,0xf4,0xbf,0x36,0x90,0xa7,
+  0x39,0xaa,0x8d,0x93,0x47,0x92,0x53,0xd3,0x81,0xfb,0xc4,0x29,0xda,0xe3,0x74,0xea,
+  0xa0,0xc2,0xe2,0x5f,0x1d,0xba,0x1e,0x9d,0x93,0x3b,0x85,0x3c,0x43,0xab,0xf5,0x6b,
+  0x16,0x03,0xfe,0xda,0x91,0x2c,0x4b,0xaa,0x38,0xcf,0xdf,0x8d,0x57,0x22,0xff,0xa1,
+  0x83,0xbf,0x7a,0x01,0xd3,0x62,0x88,0xdf,0x53,0xc6,0xa4,0xf7,0x3a,0x42,0xe2,0x42,
+  0x94,0xa1,0xe7,0x05,0x14,0x8f,0xb4,0xea,0x9a,0x12,0xca,0x5d,0x8b,0x39,0x1e,0x7d,
+  0xb3,0x0b,0xe1,0x97,0xef,0x90,0x2b,0x36,0x2d,0x88,0x40,0xd7,0x7a,0x1a,0xbc,0x43,
+  0x2d,0xcd,0xe0,0xaf,0x1e,0xe3,0x72,0xec,0xe6,0xa4,0x2f,0xe9,0xdf,0x4d,0x7e,0x2d,
+  0xcf,0xa2,0x81,0xa4,0x18,0x80,0xc7,0x71,0x1a,0x55,0x10,0x88,0x1d,0xa3,0x35,0xd4,
+  0x8b,0xa5,0x61,0xfb,0x7b,0xe7,0x26,0xf3,0xb7,0x4b,0x23,0xf4,0x3c,0xf9,0xda,0x76,
+  0xdf,0x90,0xf4,0x0a,0xfd,0x51,0xba,0x3e,0xe1,0x3b,0x33,0xc9,0x8d,0xbf,0x94,0xc8,
+  0x55,0x3e,0xda,0xb8,0x05,0x63,0x5b,0x48,0x32,0x6f,0x0a,0x56,0x22,0x62,0x5a,0x38,
+  0xd9,0x5a,0x5b,0xea,0xa3,0x93,0x00,0x3b,0x4c,0xb6,0x98,0xfa,0x86,0x8d,0xfb,0x34,
+  0xdf,0x03,0xd2,0x69,0xff,0x50,0x05,0xb4,0x3c,0xb0,0x2a,0x0b,0x7f,0x85,0x9b,0x79,
+  0xbd,0x4c,0x4e,0x78,0x99,0x9a,0xb8,0x0e,0x7d,0xd1,0x70,0xb4,0x60,0xa3,0xd4,0x47,
+  0x7a,0x85,0x6e,0x04,0x62,0xbf,0x9b,0x3c,0xda,0x76,0xff,0xd2,0xa3,0x89,0xf2,0x0a,
+  0x7a,0x88,0xcc,0x9a,0x77,0x3c,0x51,0x33,0xcd,0x0b,0xfe,0x7c,0x6c,0xdd,0xa6,0xeb,
+  0x1c,0xfe,0xc3,0xbf,0xd5,0xbb,0x6e,0xd7,0x0d,0xe5,0xd1,0x9f,0x4e,0x25,0xaf,0x34,
+  0x6f,0xc5,0x02,0x25,0x24,0xa9,0xf3,0xb7,0xa8,0x9b,0x8a,0xd0,0x91,0xf6,0xdf,0x83,
+  0x44,0x0a,0x4c,0x9a,0xf9,0x76,0x4c,0xfc,0x1b,0x25,0xfe,0xbb,0x16,0x68,0xc5,0xcb,
+  0xcc,0xd5,0xcd,0x55,0xff,0xa4,0x5e,0xe3,0xf0,0xcf,0x0b,0x55,0xac,0xda,0x0b,0x9c,
+  0xed,0x15,0x79,0x4f,0x10,0xdd,0xb8,0xa6,0x44,0xac,0xd0,0x5b,0xc9,0x34,0xe6,0x90,
+  0x0b,0xab,0xc9,0xd2,0x26,0x35,0x51,0xb4,0xad,0x62,0xb7,0x56,0xb5,0xf8,0x76,0x9b,
+  0x22,0x4f,0x5d,0x2f,0x56,0x08,0xab,0x8d,0x2a,0x03,0x9e,0xdc,0xf9,0x19,0xfc,0xb5,
+  0x9b,0x6c,0x9d,0x77,0xa3,0x56,0xe0,0x6d,0xed,0x0a,0xe8,0xb7,0x3f,0x5a,0x44,0x9b,
+  0x92,0x5b,0x66,0xa7,0xbf,0xa0,0x16,0xc5,0xfb,0xd2,0x5b,0xf4,0x58,0x14,0xab,0xbd,
+  0xb4,0x2e,0x2e,0x2c,0x85,0xf9,0xa2,0x04,0xc3,0xdc,0x4d,0x42,0x2b,0x4f,0x44,0x74,
+  0xf1,0x1f,0xf6,0x10,0x3f,0x5d,0xbb,0xaa,0x6d,0x49,0xf4,0xed,0x96,0xf0,0xe4,0xfc,
+  0x55,0x93,0xca,0xfa,0xfa,0x97,0xcc,0x7c,0xd4,0xb7,0xaa,0xfc,0x74,0x7b,0x3f,0xe9,
+  0x26,0x52,0xbc,0x2d,0x2d,0x8c,0xc0,0xbb,0xe3,0x18,0xcb,0x48,0x0c,0xcc,0x22,0x8b,
+  0x68,0xb1,0x2e,0x30,0xff,0x39,0x29,0xfd,0xbd,0x8d,0xbf,0xce,0x71,0x91,0x94,0x84,
+  0xb4,0xd3,0x78,0x05,0x6e,0xf5,0xb5,0x09,0x69,0x9b,0x32,0xaa,0x4f,0x03,0xd8,0xd5,
+  0x38,0x48,0x39,0xc9,0x46,0x39,0xe6,0x16,0xce,0x05,0xfc,0xa5,0x02,0x22,0x13,0xbf,
+  0x83,0x40,0xec,0x84,0x78,0x29,0x07,0x11,0x59,0xe3,0x4f,0xec,0xfa,0x2f,0xa6,0xa8,
+  0x02,0x2d,0x22,0x86,0xbd,0xe6,0x00,0xb6,0x52,0x51,0x6d,0x79,0x87,0xc1,0x58,0xeb,
+  0x5f,0x24,0x7b,0xf1,0x18,0xea,0x5e,0x78,0x8b,0xce,0x61,0xa9,0x89,0xf2,0x25,0x79,
+  0x8e,0xb1,0x88,0x0d,0x96,0xea,0x4d,0x00,0x62,0x6f,0x4e,0x80,0xbf,0x3a,0xc8,0x2c,
+  0xe4,0x3f,0x24,0x64,0xc0,0x8e,0x88,0x9d,0x04,0xc3,0x8b,0xc6,0x10,0x11,0xa9,0x95,
+  0x88,0xe8,0xc7,0x10,0xe4,0x72,0x1b,0x9a,0x1d,0xb3,0xf5,0x97,0x5f,0x60,0xcc,0x42,
+  0x9d,0x30,0x99,0x72,0x2b,0x17,0x49,0x91,0xad,0xf8,0x57,0x43,0x9f,0xbc,0x45,0x0c,
+  0x40,0x4b,0x43,0x13,0xac,0x45,0x60,0x9e,0x05,0xc4,0x90,0x88,0xa3,0x68,0x50,0xb0,
+  0xa8,0x39,0x32,0xf8,0xcb,0x70,0x58,0x56,0x3a,0x85,0x69,0xe6,0x35,0x98,0x65,0xfa,
+  0x28,0xdc,0x09,0x6a,0xc2,0x8f,0x8a,0xde,0xfe,0xa5,0x79,0x88,0xbf,0x9e,0x98,0xe7,
+  0x6f,0xda,0x04,0x37,0x92,0xb0,0x9b,0x4c,0x6f,0x46,0xfe,0x0d,0x31,0x4f,0xaf,0x32,
+  0x02,0x9b,0x1d,0xfc,0x55,0x02,0xb8,0xe9,0xe8,0xac,0x7b,0x11,0x25,0xc5,0x31,0x3e,
+  0xb8,0x90,0x1f,0x1a,0x58,0xd5,0x70,0x6f,0xa5,0xef,0x6b,0xf1,0x62,0xa9,0xe3,0xd9,
+  0x78,0x6d,0x8b,0xfc,0x28,0xe3,0x27,0xa9,0xbd,0x53,0xdd,0xd4,0xf6,0x0b,0xe3,0x90,
+  0x5e,0x17,0xf5,0x6e,0xba,0xc1,0xc9,0x3f,0xfc,0x09,0x19,0x2d,0x45,0xce,0xcf,0x49,
+  0x56,0xda,0x61,0x42,0xb5,0x81,0x58,0xe3,0xa0,0xf0,0x92,0xbe,0xcf,0x28,0x60,0x17,
+  0xd4,0x23,0x4b,0x31,0xff,0x50,0x3f,0x4b,0x66,0xc5,0xd6,0x6d,0x90,0x96,0x95,0x60,
+  0xb1,0x98,0x3b,0xfe,0x95,0xd4,0x47,0xb4,0x48,0x91,0x8f,0xb6,0x95,0x51,0x78,0x57,
+  0xc8,0xd5,0x71,0xc9,0x28,0xeb,0x27,0x1f,0x61,0xc0,0xda,0x14,0xfb,0x8d,0x6e,0x8d,
+  0xeb,0x2f,0xeb,0xb0,0x9f,0xf2,0x88,0xf3,0x2c,0x2d,0xa3,0x25,0xe1,0xaa,0xff,0xba,
+  0xa5,0x74,0x3f,0xad,0x4e,0xa8,0x67,0xc4,0x5a,0xf9,0x61,0xe3,0xb3,0x54,0x79,0x5d,
+  0xbc,0x05,0xb0,0x55,0x79,0x62,0x41,0xb2,0x01,0xd5,0xbe,0xca,0x9f,0x9a,0x9b,0x24,
+  0xb3,0x63,0x0f,0x2b,0x37,0xa6,0xd4,0xa4,0xd0,0x43,0x5e,0x8d,0x96,0x3f,0xd1,0x99,
+  0x2e,0x1a,0x25,0xfb,0xcd,0xea,0x4d,0x6a,0x3a,0xee,0xc4,0xbf,0x6e,0x43,0x9f,0xad,
+  0x45,0xcd,0x17,0xfd,0x24,0x69,0xe8,0x07,0xd5,0x3a,0x71,0x11,0x79,0x92,0x9d,0x1f,
+  0x5e,0x7d,0x94,0x48,0x24,0x19,0x03,0xbf,0xae,0x80,0x6c,0xe5,0xac,0x41,0xfd,0xa4,
+  0x4b,0xaf,0x48,0xaa,0x33,0xe3,0xbd,0xad,0x5d,0x27,0x83,0x43,0x6a,0x20,0x83,0xbf,
+  0x34,0x6d,0x97,0x00,0xce,0x7f,0xa9,0x28,0x90,0x2d,0xe4,0x46,0x33,0xaf,0x45,0xbc,
+  0x8a,0x3c,0x4e,0xfe,0x1a,0x7c,0x7e,0xed,0x14,0x13,0x96,0xca,0x5b,0x29,0x4e,0x86,
+  0x96,0x1b,0x25,0xb5,0x85,0xec,0x10,0x9f,0x21,0x53,0xcd,0xce,0x98,0x78,0x6a,0xea,
+  0xd3,0xa4,0xb2,0x17,0x5a,0x9c,0xfa,0xaf,0x22,0xa6,0xa4,0xec,0x8b,0x4a,0x45,0xb0,
+  0xf2,0x35,0xe9,0xea,0x95,0xc2,0x57,0xc5,0xc7,0x07,0xb0,0xc8,0x4b,0x40,0xfe,0x8d,
+  0xb2,0x98,0x32,0x5b,0x9a,0x4c,0xde,0xa4,0x33,0xf4,0x75,0x2b,0x8b,0x5f,0x16,0x87,
+  0xb1,0x58,0x6c,0xb9,0xf0,0xaa,0x25,0x0d,0x26,0x38,0xf5,0x5f,0x49,0x3c,0x2e,0x36,
+  0xd8,0xbb,0xee,0x24,0x3a,0xff,0x21,0x30,0x7e,0xa3,0xd7,0x62,0xb4,0xeb,0xdd,0x8e,
+  0x0b,0xb9,0x11,0xb3,0x3a,0xa5,0x1e,0x25,0xff,0xc6,0x39,0x3a,0x4c,0xf1,0xd7,0x64,
+  0x8f,0xad,0x84,0xc2,0x72,0xe3,0x9d,0xfa,0xaf,0x57,0x8d,0xdf,0x25,0x6a,0x96,0xf9,
+  0x0e,0x49,0xcf,0x80,0xa3,0xc8,0xb4,0x95,0x79,0xee,0x93,0x77,0xe4,0x4b,0xf5,0xfa,
+  0xf1,0xc4,0x1c,0xbd,0x60,0xa4,0x31,0x22,0xff,0x61,0x6b,0x4d,0x45,0xce,0xa8,0x30,
+  0x40,0x8e,0xc5,0xe7,0x24,0xd7,0x0e,0x91,0xcb,0x4d,0x97,0x5a,0x11,0x7f,0x15,0x0f,
+  0x64,0xea,0xbf,0x5a,0x69,0xd9,0x7c,0xac,0x3b,0xa6,0xcf,0x12,0xfd,0x8c,0x72,0xa7,
+  0x74,0x97,0x88,0x65,0x56,0xf9,0x2d,0xd2,0xfd,0x64,0x55,0xb8,0x4c,0x09,0x30,0xba,
+  0x8c,0x9e,0x40,0x1d,0xa0,0xa4,0x81,0xe8,0x2f,0x49,0xd9,0x88,0x27,0xc6,0x91,0x54,
+  0x9f,0x1b,0x7f,0x6d,0x6c,0xda,0x15,0x5b,0x42,0xae,0x33,0xc4,0x04,0x7d,0x9a,0x4c,
+  0xed,0x57,0xee,0x66,0x67,0x8c,0x3a,0x66,0xa6,0xdd,0x45,0xbf,0x47,0xfe,0xce,0x98,
+  0x8e,0xd7,0x39,0x10,0xfe,0x6b,0x4f,0x5e,0x4b,0xee,0x80,0xf1,0x20,0xf9,0x6c,0x7f,
+  0x29,0x5e,0xe7,0xbb,0x0a,0xcb,0x51,0x3c,0x68,0xc7,0xbf,0x7a,0xc9,0xfa,0xab,0x74,
+  0x7c,0xba,0x45,0xd2,0x25,0x54,0xa0,0x60,0xc4,0x72,0x0c,0x80,0x12,0xa6,0x5b,0xfa,
+  0x48,0x54,0xc7,0xc2,0x22,0xaf,0xb0,0xc3,0x58,0x21,0x74,0xce,0xf0,0x3f,0x17,0xdb,
+  0x00,0x5f,0xf5,0x5a,0x82,0xd4,0x88,0x34,0x98,0x86,0x9b,0xc4,0xc1,0x5f,0x49,0xf9,
+  0x42,0x5f,0x28,0xb6,0x2e,0x29,0x3d,0x19,0x3a,0x4f,0x9e,0x31,0xd7,0xa2,0x1b,0x76,
+  0x5c,0x62,0x0c,0xe7,0xdf,0x26,0xbf,0x11,0x6a,0x07,0x0a,0x58,0xfe,0xe1,0xc0,0x2c,
+  0x2d,0xbf,0x47,0x7a,0x83,0x1c,0x26,0xb3,0xa3,0xde,0x6d,0xd2,0x7b,0xfa,0xe8,0x40,
+  0xdd,0x2f,0x7d,0xbb,0x27,0xbd,0xc7,0x7f,0xd7,0x46,0xb2,0x85,0xbe,0x23,0x32,0x90,
+  0x35,0xa4,0x9c,0x27,0xb5,0x03,0x55,0x3b,0xa5,0x77,0x45,0x2b,0x70,0xc9,0x68,0x2a,
+  0xa3,0xd5,0xa9,0xeb,0xde,0x25,0x17,0x8c,0xda,0x06,0x96,0x91,0xf8,0x01,0x22,0xb2,
+  0x6d,0x6d,0xef,0xf2,0x67,0x70,0x67,0x26,0xff,0x70,0x98,0x5c,0xc9,0xad,0x3f,0xe8,
+  0x4d,0x09,0x75,0xfa,0x65,0x32,0x17,0x1e,0x31,0xa9,0x4e,0xfe,0x05,0xaa,0x7d,0x35,
+  0x4b,0x75,0xe4,0x39,0x32,0x6b,0x3b,0xc0,0xae,0x91,0xd6,0xef,0x90,0xeb,0x43,0x60,
+  0x0c,0x90,0xc3,0xfa,0xcd,0xa6,0x37,0x0d,0x08,0xfa,0x3b,0xa4,0xbe,0xcf,0x3b,0x2c,
+  0x38,0xfa,0x5f,0xe5,0xe0,0x1b,0x57,0xa5,0x4b,0xf7,0x8b,0x9f,0x25,0x3d,0x7d,0x55,
+  0x03,0x9e,0x7f,0x15,0x9f,0x38,0x78,0x44,0xae,0xc5,0xdd,0xe1,0x29,0xa5,0x93,0x04,
+  0x06,0xf2,0xb1,0x74,0xe5,0x07,0x1d,0x41,0x1d,0x1c,0xe9,0xdf,0xc2,0x75,0xfc,0xe9,
+  0xfc,0xa7,0xe2,0xef,0xc6,0xf6,0x9a,0x55,0x27,0x95,0x90,0xdf,0xd1,0xff,0x9a,0x56,
+  0x06,0xd8,0x6a,0x69,0x74,0xbb,0xff,0xe7,0x64,0x4f,0xbc,0x8a,0x7a,0xb0,0xce,0xe5,
+  0x07,0x18,0x93,0xea,0x62,0x15,0x97,0xd3,0xe2,0xd1,0x54,0xc3,0x60,0x19,0xf8,0xea,
+  0x14,0x80,0xd8,0xeb,0xfa,0xf7,0x31,0x23,0x71,0x3b,0x96,0x86,0x75,0x54,0x99,0xd1,
+  0xae,0x0d,0x8e,0xfe,0x97,0xac,0x74,0x2d,0x81,0x37,0xa4,0x3f,0x4e,0x69,0xb7,0xb8,
+  0x62,0x8d,0x27,0x24,0x76,0xc0,0xfd,0x83,0x65,0x5f,0xb9,0x6b,0x93,0x60,0x90,0xbc,
+  0x99,0xe0,0x5d,0x74,0xe9,0x2b,0xbc,0xd0,0x65,0x8a,0x71,0x2d,0xd8,0x9f,0xa7,0x63,
+  0xa4,0x86,0xac,0x40,0x9f,0xc4,0xd1,0xff,0x5a,0x46,0xce,0x2f,0x89,0x18,0x01,0xea,
+  0x79,0xaa,0xe3,0x3c,0xa9,0xeb,0x78,0x38,0x29,0x29,0xe4,0x7b,0x46,0x38,0x01,0x1b,
+  0x74,0x1d,0x3d,0xd2,0x8c,0x94,0xe0,0x8d,0x67,0xe4,0xbd,0x01,0x16,0xc8,0x48,0x93,
+  0x5f,0x1b,0x91,0xc3,0x4a,0xd2,0x02,0x6b,0xc1,0x54,0x5e,0x52,0x22,0x1c,0x7f,0x9d,
+  0x23,0x23,0x06,0xec,0x3b,0xb4,0x38,0x66,0x5c,0x24,0x11,0x0f,0x86,0x48,0xb4,0x2b,
+  0xde,0x7a,0x0f,0xec,0x3b,0xe0,0xd8,0xeb,0xbb,0x0c,0x26,0x9b,0xfb,0x1b,0x21,0x52,
+  0xca,0x52,0x13,0x2f,0x93,0x10,0xcf,0x48,0xbc,0xcc,0xb0,0x70,0xe3,0xf2,0x49,0xae,
+  0xf8,0xd7,0xb8,0xf3,0x0d,0x5a,0xcf,0x45,0xcc,0x8f,0x92,0x9b,0xd3,0xb0,0x4c,0x11,
+  0xf2,0xae,0x58,0x6d,0x7a,0x4d,0xa4,0xbe,0xc1,0xc2,0xbd,0x11,0x69,0x26,0xec,0x7a,
+  0x37,0x8f,0xad,0xff,0xb2,0xc2,0x5e,0xcc,0x90,0x7a,0xac,0x6a,0x2f,0xa5,0xc7,0x7f,
+  0x86,0x6c,0xa7,0xfe,0xde,0xa8,0xc5,0xfc,0x9f,0x86,0x5d,0xc6,0x0f,0x1b,0x3d,0x13,
+  0x0b,0xd3,0xb1,0x94,0x98,0xe5,0x1f,0xba,0xea,0xbf,0x26,0xc2,0xb9,0x58,0x00,0x68,
+  0xe2,0x46,0x86,0xe5,0x24,0x5e,0x99,0xd7,0x7f,0xc1,0x8b,0x71,0x07,0xd1,0x93,0x79,
+  0x09,0x76,0x4e,0xbb,0x6d,0x6c,0xfd,0xd7,0x04,0xb8,0x3b,0xc8,0xaa,0xfc,0x8c,0x27,
+  0x3a,0xe0,0x3a,0x5c,0x6e,0xa0,0xaa,0x5f,0xf9,0x71,0x51,0x90,0xe0,0xf7,0xc9,0xeb,
+  0x12,0xfd,0x72,0x0f,0x61,0x42,0x60,0x36,0xde,0xc9,0x8a,0x7f,0xd9,0xac,0x2f,0x96,
+  0x0a,0x39,0xec,0x0e,0x26,0x3c,0x68,0x3b,0x3b,0x83,0x64,0xc8,0x8c,0xd0,0x60,0xbb,
+  0xaa,0xcb,0x17,0x68,0x77,0xba,0x72,0xa6,0x54,0x5d,0x31,0xca,0x39,0x70,0xb2,0xf9,
+  0x0f,0xc7,0x9f,0x4b,0x70,0x63,0x18,0x8d,0x3a,0xe9,0xa2,0x70,0x09,0x09,0x85,0x9a,
+  0xdb,0xce,0x92,0x4b,0x46,0xfd,0x20,0x20,0xdf,0x21,0x72,0xc5,0x98,0xf3,0xc7,0xe2,
+  0x5f,0xd7,0x73,0xe3,0x7e,0x8e,0x14,0xfa,0x9b,0x01,0x6d,0xb5,0xab,0x4f,0x91,0x51,
+  0x23,0x85,0x8e,0x6b,0x50,0x3e,0x42,0xba,0xe3,0x70,0x23,0x55,0x92,0x5e,0xd2,0xed,
+  0x8a,0x7f,0x9d,0xfc,0xb8,0x73,0x89,0x53,0x81,0x94,0xf8,0xae,0x01,0x1e,0xe3,0x29,
+  0x25,0x51,0xbc,0x02,0x57,0xc7,0x54,0x90,0x78,0x79,0x75,0x8b,0x1f,0xc5,0xc2,0x02,
+  0x64,0x35,0xf5,0xbb,0xea,0xbf,0x26,0x8e,0x7f,0x59,0xc6,0x19,0x81,0xb2,0x3a,0x56,
+  0xcf,0x5a,0x54,0x11,0x42,0xef,0x82,0xc0,0x0a,0x6e,0xc5,0x20,0xb2,0x8c,0xbc,0xd6,
+  0x66,0xa6,0xfe,0x2b,0x39,0x61,0xfc,0x0b,0xab,0xbd,0x30,0x1c,0x23,0x6c,0x4c,0x30,
+  0x3a,0xf4,0xaf,0x02,0x76,0x48,0xc6,0x94,0xc5,0xf1,0x30,0x79,0x00,0x77,0xa2,0x21,
+  0xf1,0x6a,0x9e,0xa4,0xb1,0x52,0xec,0x77,0xeb,0x7f,0xb9,0xe2,0x5f,0x2a,0x33,0x84,
+  0xa0,0x59,0x8d,0x15,0x61,0xbd,0x5a,0xc8,0xf4,0x86,0xca,0xd7,0xc2,0xfc,0x84,0xcc,
+  0x20,0x0a,0x7d,0xe2,0xb4,0x78,0x35,0x49,0x96,0x7b,0x95,0xd4,0xf8,0xfa,0xaf,0x8f,
+  0x5b,0xaf,0x2b,0x9a,0x25,0x7d,0x7e,0x09,0x65,0xbf,0x4c,0xe9,0x14,0x37,0x5a,0x98,
+  0x8a,0x35,0xcf,0x3f,0x74,0xeb,0x7f,0x8d,0x65,0xfd,0x75,0x0c,0x0c,0x84,0x79,0x91,
+  0x66,0x67,0x14,0x89,0x26,0x12,0xe0,0x78,0x30,0x23,0xc5,0x42,0x2d,0x61,0x9e,0x7f,
+  0xe8,0xd4,0x7f,0x4d,0x74,0x7e,0x58,0xcd,0x88,0x38,0x72,0x76,0x72,0x46,0x8e,0xcd,
+  0xe4,0x59,0x9e,0x00,0xaf,0x91,0xa7,0x71,0xe6,0x31,0x37,0xde,0x22,0xa2,0xcf,0xd4,
+  0x7f,0x69,0x13,0xce,0x33,0x07,0xbc,0x5d,0x00,0xcd,0x18,0xbd,0xe4,0xd3,0xb4,0x3c,
+  0xa9,0x2c,0x17,0xef,0x00,0x83,0xcd,0xfc,0x0b,0x38,0xe1,0x69,0x77,0xfe,0xe1,0x04,
+  0xcf,0x29,0xf2,0xae,0xa0,0x72,0xdf,0x31,0x56,0xad,0x1c,0xc0,0x14,0xe2,0xdd,0x0d,
+  0xfa,0x29,0xa5,0x4c,0x6c,0x40,0xa1,0xa2,0x3e,0x25,0x54,0xf4,0x9c,0xdc,0x1a,0x4b,
+  0xe2,0x60,0x57,0xfd,0xd7,0xf8,0xf8,0x17,0x1a,0x05,0xc9,0xe2,0x51,0xfd,0x72,0xf3,
+  0x33,0xd4,0x3b,0x88,0x6c,0x87,0xc9,0xc7,0x52,0x81,0x21,0xe9,0x3e,0x7a,0x3e,0xb9,
+  0x23,0x19,0x4c,0x4b,0xe7,0xc9,0x31,0x33,0x4c,0xd7,0x65,0xd7,0x7f,0x4d,0x14,0x97,
+  0x21,0xd5,0x14,0x89,0x10,0x8d,0x5a,0xa6,0x2b,0x04,0xef,0xcc,0x3a,0x54,0x1a,0xda,
+  0xea,0x8c,0x69,0x60,0x8a,0x0f,0x63,0xea,0xbf,0x26,0x88,0x7f,0x21,0x5f,0xc1,0x9b,
+  0xe4,0x90,0x51,0x60,0x04,0x35,0xa4,0xf2,0x56,0xc2,0x86,0x77,0x33,0x17,0x4e,0x02,
+  0xc7,0xbe,0x8d,0xf3,0xcf,0x8f,0xab,0xff,0x1a,0x1f,0xff,0x32,0x02,0x09,0xff,0xf3,
+  0x74,0x75,0x03,0x8b,0x7f,0x31,0xfd,0x26,0x43,0xf9,0x3e,0x1a,0x89,0xad,0xd8,0xf2,
+  0x3b,0xd2,0x6a,0xf8,0x3f,0x31,0xfe,0x85,0xc6,0x8d,0x09,0xff,0x19,0x63,0x35,0x09,
+  0x2e,0x55,0x38,0x8f,0x87,0xdf,0xe8,0xb0,0x04,0xc5,0x0c,0x25,0xe5,0x7f,0xbe,0x61,
+  0x35,0x80,0xbe,0x05,0x89,0x86,0x63,0x7f,0x34,0xfe,0xc5,0xe2,0x32,0xc8,0x36,0xaf,
+  0xaf,0x68,0x52,0xb0,0x10,0xac,0x4b,0x83,0xe7,0xb4,0x70,0x3e,0x33,0x96,0x21,0x40,
+  0x68,0x5f,0xcd,0xf3,0x0f,0xdd,0xf5,0x5f,0x13,0xc6,0xbf,0xf2,0x69,0xf9,0x69,0xe3,
+  0x30,0xa9,0xd3,0x16,0x52,0x35,0x49,0xde,0x5e,0x1e,0xf6,0x04,0x73,0xdb,0x90,0x5a,
+  0xbc,0x1b,0xc5,0xc2,0x4e,0x23,0xff,0xfc,0x27,0xc6,0xbf,0x58,0x61,0x11,0xa0,0x24,
+  0xf1,0x59,0x54,0xe8,0x60,0xfa,0x5f,0x65,0xcf,0xce,0xf3,0xbd,0x8c,0xb8,0x49,0xaf,
+  0x8f,0x56,0x0f,0xb0,0x1c,0xc5,0xfd,0xae,0xfa,0xaf,0x8f,0x8f,0x7f,0x15,0x58,0xcc,
+  0x8a,0x08,0xbb,0xb6,0x09,0x97,0x00,0x26,0xab,0x03,0x6a,0x05,0x17,0x0b,0x4b,0xf1,
+  0x1c,0xc5,0x4f,0x8c,0x7f,0xf5,0xf0,0xf8,0xd7,0x10,0x18,0x41,0x4e,0xcd,0x61,0xe5,
+  0x28,0x72,0x03,0x5a,0x4c,0x91,0x72,0x46,0xc4,0xec,0xfa,0xaf,0xf1,0xf3,0x6c,0x78,
+  0x18,0xff,0x06,0x96,0x9c,0x30,0x6a,0x7a,0x5a,0x61,0xa8,0xac,0xfe,0x8b,0x63,0xb4,
+  0x17,0xec,0x1c,0x45,0x57,0xfd,0xd7,0xc7,0xdd,0x3f,0x58,0x09,0xa8,0x7b,0x0d,0x85,
+  0x49,0x1b,0x88,0x7e,0x43,0xb2,0x78,0x2f,0x6f,0x57,0x12,0x0f,0xf6,0x89,0xab,0x89,
+  0x7f,0x6c,0xfd,0x57,0x66,0x5a,0x5c,0x22,0xcb,0x55,0x28,0x6c,0x37,0x6a,0x4c,0x31,
+  0x82,0x1b,0xdb,0xe0,0xdf,0x12,0x67,0xc5,0x7c,0xdf,0x95,0x2a,0x62,0xa3,0xa4,0xdb,
+  0x08,0x3e,0x2a,0xbd,0x21,0x1f,0x4a,0x86,0xc7,0xd6,0x7f,0x4d,0xb8,0x5e,0xee,0x85,
+  0x1b,0x44,0xf9,0xb0,0x26,0xce,0xd1,0xc1,0xf3,0x0f,0xc1,0xd8,0xb4,0x7f,0x6c,0xfd,
+  0xd7,0x44,0xf7,0x8f,0xa2,0xd2,0xe2,0xd7,0xc5,0x7e,0x8a,0x65,0x5f,0xc8,0x48,0xdf,
+  0x5e,0x4b,0x82,0x14,0xf9,0x33,0xf5,0x90,0xe2,0x05,0xfc,0xa5,0x19,0xc6,0xd6,0x31,
+  0xf5,0x5f,0x13,0xc6,0xbf,0x30,0xec,0x75,0x9e,0x3e,0xac,0x54,0x73,0x22,0x7a,0xcc,
+  0x36,0x54,0x06,0xe3,0x58,0x2c,0xc6,0xc4,0xc2,0x46,0x1a,0x1e,0x36,0xfc,0x63,0xeb,
+  0xbf,0x26,0x8a,0x7f,0xa5,0x9c,0x38,0x48,0x20,0xc4,0x68,0x7b,0xc1,0xd3,0x93,0xc1,
+  0xf1,0xd8,0x1b,0xd7,0x65,0x3c,0x62,0x32,0xda,0x38,0xd7,0xeb,0x27,0xc5,0xbf,0x1a,
+  0x50,0x6d,0x19,0x83,0x2f,0x08,0x10,0x26,0x63,0xc6,0x42,0xda,0x63,0xb0,0x42,0x5d,
+  0x2c,0xe6,0xf5,0x9f,0x14,0xad,0xf7,0x73,0xfa,0x8f,0xc7,0xbf,0x5c,0xfc,0x87,0x0b,
+  0x57,0xaa,0x53,0x48,0x0b,0x9d,0x9d,0x2e,0x08,0x48,0x53,0xb0,0x02,0x8b,0x85,0xc6,
+  0xe4,0x5f,0xf0,0xfc,0xc3,0xf1,0xf5,0x5f,0xd9,0x1b,0xd0,0xbc,0xec,0x16,0x3c,0x1b,
+  0xcc,0x67,0xfa,0x5f,0xe2,0x7e,0x83,0x53,0x3d,0xfc,0x67,0xe2,0x5f,0xb4,0x3e,0x96,
+  0x6f,0x8b,0x7c,0x61,0x35,0x8a,0x8c,0xd0,0xcc,0x77,0x52,0xba,0xac,0x41,0x8b,0x1e,
+  0x1c,0x21,0x97,0xfb,0x3f,0x97,0xa8,0x19,0x5f,0xff,0x35,0x7e,0x7e,0x9a,0x60,0x93,
+  0xc2,0x68,0x20,0x23,0x39,0x9c,0x4c,0xf6,0xe1,0x6c,0x34,0x43,0xd7,0xd3,0xde,0x32,
+  0x05,0xb7,0xb6,0x86,0x07,0x67,0x97,0xb9,0xea,0xbf,0x3e,0x26,0xfe,0x45,0x2a,0x8d,
+  0x1b,0xe1,0x3a,0x3a,0xcb,0x36,0xc4,0x3a,0xe8,0x9d,0xd6,0x75,0xa0,0x45,0xc7,0xcc,
+  0x90,0x13,0xed,0x0f,0xf0,0x79,0xfe,0xe3,0xf1,0x2f,0xf2,0x05,0x43,0x09,0x11,0xd8,
+  0xbf,0x1a,0x58,0x71,0x84,0x97,0x74,0x29,0x80,0xc4,0x91,0x5e,0xa0,0x8b,0xfa,0x9b,
+  0x03,0x33,0x30,0x81,0xc7,0xe4,0xfc,0x87,0xae,0xfa,0x2f,0x5e,0xe9,0x7f,0x26,0x63,
+  0x80,0x1f,0x45,0x2b,0x53,0xd2,0x31,0x72,0x41,0x63,0x4e,0x60,0x10,0xa9,0x9c,0xfa,
+  0x7c,0x0f,0x60,0x6d,0x17,0xed,0x26,0xac,0x46,0xec,0x08,0x27,0xa6,0xfe,0xe3,0xf1,
+  0x2f,0xc1,0xae,0x08,0xa3,0xb0,0x7f,0xa5,0xda,0xce,0x08,0x67,0xd1,0xb7,0xb1,0xf4,
+  0xda,0x34,0x04,0x6b,0x36,0xb9,0xca,0x1f,0x8f,0x7f,0x09,0xf5,0x43,0x8c,0x20,0xe2,
+  0x39,0x52,0x33,0x0c,0x4e,0x4e,0x1d,0xb9,0x22,0xce,0x41,0xd8,0x55,0xa7,0x1f,0xd7,
+  0x6b,0x1a,0xbc,0xc3,0x6d,0xc7,0xf5,0xe3,0x1d,0x35,0x63,0xea,0xbf,0x26,0xf4,0x0f,
+  0x91,0x49,0xfe,0x1d,0xd2,0x69,0xa2,0x4a,0x97,0xb4,0x82,0x73,0xb8,0xad,0x46,0x0e,
+  0xae,0xf4,0xd6,0x16,0x4b,0xf3,0x97,0x09,0x78,0xb9,0xeb,0xbf,0x26,0xba,0x0e,0x26,
+  0xd2,0xbf,0x29,0x74,0x9a,0x36,0xab,0x36,0x9d,0x6e,0x32,0xae,0x8f,0x4e,0xc2,0xe8,
+  0xc7,0xcf,0x88,0x6d,0x31,0xff,0x98,0xfa,0xaf,0x89,0xfd,0x4c,0x64,0x44,0x14,0x5a,
+  0xe1,0xed,0xa2,0x22,0x70,0xee,0xa2,0xba,0x19,0xc0,0xb4,0xba,0xd5,0xe0,0xff,0x60,
+  0x44,0x4c,0x6e,0x23,0xcc,0xdf,0xb0,0xea,0xbf,0x26,0x88,0x7f,0x31,0x23,0x68,0xe4,
+  0xf3,0xf8,0x57,0xd8,0xf4,0xd9,0x32,0xac,0x18,0xc8,0x10,0x7b,0x39,0xc7,0x1d,0x26,
+  0x26,0xb1,0x2e,0x57,0xfd,0xd7,0xb8,0x79,0x96,0x9d,0x8c,0xa9,0xcb,0x59,0x5d,0x26,
+  0x5f,0x82,0x09,0xeb,0xbf,0x84,0xcb,0xe4,0x48,0xfb,0x9c,0xb4,0xaf,0xa7,0xf8,0x7d,
+  0xe2,0x6b,0x0d,0xa5,0x15,0x7c,0x9a,0x5e,0x83,0x07,0xed,0x33,0x23,0xd2,0x7b,0xf0,
+  0x7c,0xcd,0xe0,0x6c,0x36,0x4f,0xd2,0x70,0xaa,0xa2,0x5f,0x88,0x28,0xf5,0x74,0x16,
+  0x78,0x48,0xc5,0x97,0xc9,0xc3,0x98,0xa3,0xd8,0x9f,0xd1,0x5f,0x7e,0x1b,0x67,0xfe,
+  0xb4,0xc5,0x36,0x3f,0x3d,0xed,0x49,0xdd,0x51,0x45,0x9e,0x24,0x0e,0x22,0xdb,0x0a,
+  0x46,0xe3,0xcf,0x48,0x67,0x7c,0x26,0x55,0x3a,0xa4,0xbf,0x21,0x7b,0x5b,0xab,0x90,
+  0xf6,0xd0,0x62,0x4d,0xec,0x01,0xbc,0x6c,0xe5,0x1f,0xb6,0x8b,0x9d,0x4c,0x6a,0xbc,
+  0xe8,0x8c,0xd2,0x89,0x82,0xce,0xa1,0xa2,0xa7,0x84,0x36,0x86,0xbf,0x96,0xda,0xec,
+  0x43,0x45,0x47,0xf1,0x84,0xaa,0x83,0xf1,0x99,0xaf,0x67,0x71,0xc6,0xf0,0x99,0xd2,
+  0x56,0xbe,0x28,0xb6,0xfe,0x72,0x49,0x52,0xef,0xac,0xb4,0xab,0xbd,0x0a,0xa7,0xf7,
+  0x7a,0xba,0xc5,0xa7,0xf4,0x27,0x95,0xaa,0xfe,0xeb,0xba,0x00,0x7f,0xed,0x15,0xc4,
+  0x3e,0xb5,0xcb,0x8f,0x77,0xcb,0xb4,0x2d,0x0a,0xf5,0xff,0x0d,0x6e,0x6d,0x49,0x75,
+  0x0b,0xac,0x7b,0x9e,0x59,0x15,0x5b,0x90,0x12,0x43,0x76,0xfe,0xe1,0x7b,0xe4,0x08,
+  0xad,0x3d,0xe7,0xdb,0xf9,0xc8,0xbb,0xd2,0x11,0x33,0xfc,0xd2,0xda,0x9e,0xb6,0x9f,
+  0x41,0x4b,0x64,0x38,0xaf,0xe7,0x91,0xf7,0xf4,0x0b,0x7a,0x78,0x08,0x15,0x1f,0x94,
+  0xdf,0xd2,0x70,0x77,0x70,0x9d,0x70,0x03,0xf9,0x4d,0x7a,0x56,0xd2,0xf7,0x53,0xe1,
+  0xb8,0x01,0x63,0xd2,0xbe,0xb9,0x19,0xfd,0xe5,0x67,0x51,0x1a,0xde,0x5c,0x34,0x2a,
+  0x5d,0x36,0x60,0x7a,0x87,0xd5,0xe1,0x9a,0x6f,0xb7,0xbf,0xaf,0xb3,0x33,0xa2,0xcb,
+  0xf2,0x95,0xcf,0xb0,0x37,0xdb,0x7e,0x03,0x96,0x89,0xfa,0xfa,0xdb,0xce,0xe9,0x57,
+  0xe6,0xd5,0xd3,0xeb,0xd3,0xc5,0x17,0xc9,0xff,0x24,0xf5,0x0d,0xbe,0x61,0x75,0x44,
+  0xb3,0xf1,0x17,0xc6,0x5c,0x06,0xae,0x4f,0xb1,0xea,0xb3,0xc8,0x40,0x70,0x27,0x0a,
+  0x19,0x18,0xb3,0x06,0x0a,0x18,0x7b,0x9e,0x18,0x31,0x3f,0x8f,0x94,0x47,0xbf,0x31,
+  0x18,0x5b,0xcb,0x1b,0xcd,0xa3,0x72,0x18,0x25,0xd4,0x2b,0x31,0x9f,0xc4,0xf4,0xed,
+  0x2c,0x77,0xf3,0x1f,0x8a,0x55,0xe6,0x75,0xa9,0x22,0xdc,0x65,0x6a,0x01,0x7d,0xc0,
+  0x64,0xbe,0x43,0xfc,0xbd,0x12,0xcc,0x98,0x00,0x1b,0x90,0x19,0x4d,0x35,0xbc,0x68,
+  0xac,0x06,0x8f,0xda,0xab,0x88,0x6f,0xa0,0xa3,0xb8,0x51,0x5d,0x23,0x56,0x1a,0xab,
+  0x07,0xaa,0x96,0x2c,0xd8,0xe9,0x71,0xeb,0x2f,0xdb,0x8f,0xc3,0x63,0x22,0x06,0x91,
+  0x09,0xa0,0x63,0xa1,0xc2,0x14,0xad,0x07,0xe4,0x60,0x5e,0xc8,0x7f,0x5c,0x6b,0x13,
+  0xfe,0x9e,0xe4,0x11,0x74,0x45,0x4a,0x75,0xea,0xd1,0xe3,0xeb,0xc8,0x96,0xe6,0x15,
+  0x03,0x0b,0xea,0xb6,0xce,0xb6,0xf3,0x0f,0xaf,0x27,0xbb,0x36,0x56,0xa6,0xff,0xea,
+  0x3e,0xf1,0xd5,0x3b,0x1f,0x4f,0x7e,0x76,0x48,0x59,0x49,0xa6,0x90,0x9f,0xb7,0x72,
+  0x5e,0xf4,0x9c,0x5d,0x5b,0xfe,0x01,0x50,0xc0,0x1d,0xaf,0x5e,0x3d,0x89,0x56,0x06,
+  0xa2,0xd1,0xf8,0x2f,0x11,0x17,0x6c,0xed,0x1c,0x12,0xa7,0xe8,0x3f,0x8e,0x7f,0x03,
+  0xa3,0x66,0xa5,0xae,0xfc,0xc3,0xf5,0x75,0xa7,0xd4,0xd9,0xc5,0xc7,0xe2,0xbf,0x25,
+  0x75,0x69,0x6f,0x97,0xe4,0x35,0x2e,0xe8,0x33,0xfb,0x0b,0x66,0x34,0x1e,0x6b,0xdd,
+  0x71,0x6d,0x5d,0x7f,0xfe,0x4d,0xd2,0x51,0xfd,0x4b,0xb4,0x4e,0x7f,0x48,0x40,0x7a,
+  0x2e,0x2d,0x94,0xf4,0x95,0xab,0x6b,0x8d,0xd3,0xa4,0xae,0xc1,0x77,0x53,0x5b,0x11,
+  0x7f,0x4c,0x11,0x7f,0x5d,0x50,0x7c,0x7d,0x93,0x86,0x85,0x8b,0xcd,0xaf,0x55,0x55,
+  0xf1,0xe7,0xeb,0x82,0x02,0x73,0x78,0xf6,0xb9,0x8b,0xc6,0x95,0x59,0xf5,0x98,0xf0,
+  0x89,0xd9,0x86,0x56,0x7d,0xe5,0xef,0xe5,0xeb,0xa9,0x6f,0x89,0x74,0x4a,0xfd,0x0f,
+  0xac,0x4f,0x69,0x91,0x06,0xae,0x66,0xeb,0x85,0xf8,0xeb,0x43,0x00,0x59,0xeb,0x90,
+  0xce,0xe8,0x48,0x6b,0x68,0x70,0x2d,0xe3,0x35,0x12,0xaa,0xd2,0x39,0x29,0xe9,0x3d,
+  0xe3,0x82,0x56,0x6b,0xae,0x4b,0x09,0x47,0xe5,0x27,0x27,0x45,0x5a,0x0b,0x28,0x78,
+  0xf8,0x79,0xe0,0xf2,0x4d,0x4a,0x72,0x97,0x86,0x8c,0xc9,0x3f,0xac,0x28,0x3b,0xa9,
+  0xb6,0x68,0x97,0x12,0x8f,0xeb,0x37,0xf6,0x06,0xee,0x81,0x6d,0xeb,0x80,0x5c,0x7e,
+  0x92,0xdc,0xd3,0x70,0x4a,0xf8,0x05,0x29,0xeb,0x55,0xef,0x15,0x4f,0xd1,0x1b,0x50,
+  0x77,0xd2,0x60,0x72,0x27,0x95,0x34,0x0f,0xcf,0xfd,0x9e,0x66,0x39,0x1e,0xc4,0xe1,
+  0x3f,0xfc,0x91,0x7e,0x60,0xcb,0x96,0xf4,0x82,0xfb,0xb4,0x57,0xdb,0xd7,0xd1,0xb2,
+  0xa1,0x8e,0x6f,0x8b,0xaf,0xd1,0x5d,0xdb,0xca,0xd3,0xcb,0xef,0x13,0x2f,0x03,0xa0,
+  0xa9,0x1c,0x56,0xbf,0x2d,0x5e,0x31,0x1e,0x6c,0xab,0x4c,0x2d,0x88,0x16,0x7d,0xc0,
+  0xc8,0x12,0x6f,0x5b,0x2e,0xbe,0xc6,0xe3,0x5f,0x2b,0x0d,0x87,0xff,0xf0,0xb8,0x82,
+  0x0f,0x63,0x27,0x52,0x1a,0x3e,0xb6,0x64,0xf9,0x28,0xd3,0x49,0xdf,0x91,0xd0,0x07,
+  0x4a,0x67,0xfa,0x8f,0x2a,0x8f,0x60,0x71,0xdf,0x6c,0xf1,0x45,0xb2,0x55,0x09,0x26,
+  0xf3,0x66,0x8b,0xa6,0xde,0xba,0x2c,0xf8,0x52,0xde,0x5c,0x78,0x8b,0x75,0xdd,0x1e,
+  0xbc,0x43,0xad,0xcd,0xc4,0xbf,0x76,0x93,0xcb,0x7a,0x4d,0x87,0xef,0xf5,0xe2,0x91,
+  0x8e,0x63,0x7a,0x0d,0x5d,0x3b,0x04,0xd8,0xea,0x72,0xeb,0x8e,0x4d,0xde,0xd7,0xa5,
+  0x0b,0xe4,0x85,0x54,0xfd,0x4e,0x1f,0xa0,0x2d,0xe3,0x3d,0x7d,0x6e,0xab,0x2f,0x26,
+  0x8d,0x74,0xbc,0x60,0xd4,0x77,0x5f,0x3f,0x28,0x9d,0x24,0x97,0xe7,0xd5,0x27,0x7c,
+  0x6f,0x67,0xe5,0x1f,0xea,0x11,0xc5,0x17,0xe7,0xee,0x9c,0x8c,0x68,0x4b,0x1f,0xf1,
+  0x86,0x89,0x48,0x1f,0x4b,0xc7,0x86,0xc4,0x5a,0xc1,0x47,0x1f,0xe7,0x9e,0xde,0xc3,
+  0x6d,0xd2,0x69,0x71,0x84,0xdc,0x4f,0x3e,0x83,0x45,0x28,0x16,0x11,0x47,0x26,0xfe,
+  0xb5,0x05,0xb3,0xa1,0xd6,0xb1,0x92,0x2e,0x31,0x42,0xae,0x67,0x06,0x99,0x25,0xad,
+  0xa3,0x8d,0xe9,0xbc,0x95,0xf1,0x22,0x7d,0x1d,0x15,0x63,0xb2,0x85,0xc8,0x6e,0x60,
+  0xc2,0xb5,0xbe,0x44,0xdb,0xa0,0x7e,0x68,0x63,0x81,0xe1,0xdd,0x44,0x9c,0xfc,0xc3,
+  0xbf,0xa5,0x3d,0x64,0x1a,0x7a,0xe6,0x26,0xe9,0x90,0x59,0xd9,0x97,0x49,0xa8,0x88,
+  0x41,0x93,0xa2,0x74,0xce,0x48,0xf3,0xac,0x0a,0x15,0x3c,0x78,0xf1,0x10,0xec,0x44,
+  0xdf,0x48,0x88,0x53,0xf5,0xdd,0xba,0xbf,0x59,0xdd,0x80,0x29,0x85,0x34,0xb8,0x44,
+  0x59,0x7f,0xd0,0x85,0xbf,0x6c,0x16,0x08,0x9e,0x3a,0x05,0x7f,0x4e,0x3a,0xc8,0xdf,
+  0xd0,0x4e,0x06,0x10,0x8c,0xe9,0x9a,0x4a,0xa7,0x0d,0x91,0x1f,0x88,0x28,0x31,0xe6,
+  0x01,0x47,0x5a,0xff,0x7a,0xbf,0xba,0xbe,0xe1,0xfd,0xd2,0x47,0x85,0xaa,0xc3,0x63,
+  0xf8,0xe7,0x31,0x4e,0xad,0x5d,0x3d,0xd8,0xc0,0x0a,0x6c,0x01,0x76,0x15,0xad,0x2e,
+  0x41,0x9f,0x3f,0xdc,0xa7,0x3d,0xc1,0x82,0x5c,0xa4,0x5d,0x6c,0x15,0xab,0x9a,0xf2,
+  0x36,0x91,0x76,0x78,0x1f,0x6e,0x37,0x1b,0xb5,0xa2,0x41,0xa5,0x30,0xc9,0x32,0x24,
+  0xdd,0xfc,0xf3,0x81,0x88,0xc7,0x17,0x6f,0x3b,0x9d,0xec,0x07,0x43,0x5d,0x15,0x4f,
+  0x27,0xfb,0x97,0xcf,0x52,0xd5,0x78,0x5b,0x7a,0x7b,0x4f,0xa0,0x16,0xbb,0xd2,0x3f,
+  0x59,0x2c,0x44,0xb4,0x87,0x00,0xc3,0xa3,0x9c,0x10,0xe3,0x3f,0x24,0x27,0xe5,0x08,
+  0xbc,0xaa,0xcb,0xdf,0xcb,0xc4,0xbf,0xae,0x90,0x3f,0x33,0x26,0x01,0xa4,0x6a,0xff,
+  0x3d,0xa0,0x24,0xd4,0x35,0x93,0x2f,0x4d,0xc3,0x48,0x56,0xf1,0x09,0xf9,0x0f,0x48,
+  0x24,0x35,0x20,0xdd,0x8b,0xb5,0xc9,0x00,0xbb,0xc4,0x3b,0xb5,0x4b,0xd0,0xb2,0x0e,
+  0x06,0x7b,0xde,0x47,0xa2,0xd1,0x81,0x1a,0x27,0xff,0xf0,0x1c,0x39,0x44,0x6b,0x63,
+  0x05,0xdf,0x97,0xa6,0x25,0x0f,0x25,0xeb,0xd1,0xe7,0xff,0x09,0x99,0x9b,0x8c,0x7c,
+  0x7d,0xd1,0xb5,0xd2,0x47,0x15,0x2f,0x82,0xa3,0xf8,0x85,0xef,0x17,0x7d,0x94,0xfc,
+  0x3b,0x32,0xd9,0x20,0xcd,0x22,0x22,0xb2,0x4a,0xfc,0x27,0x66,0x92,0x67,0x79,0x82,
+  0x77,0x86,0xff,0x50,0xec,0x20,0x7e,0xd9,0x48,0x02,0xa0,0x0a,0x94,0x54,0x69,0x0b,
+  0xe8,0x97,0x92,0xc6,0x26,0x98,0x79,0x6f,0x2b,0x92,0xe2,0x8a,0x55,0xb2,0x82,0xd1,
+  0xae,0xc3,0x9c,0x88,0x7e,0xc8,0x5e,0x94,0xa4,0x6d,0x38,0xfc,0x87,0xb0,0x82,0x85,
+  0xd3,0x8d,0xdb,0xd7,0x6b,0x32,0x69,0x15,0x82,0x4d,0x0b,0xd6,0xe7,0xca,0xf2,0xfa,
+  0x42,0x2f,0x62,0xab,0x41,0xd2,0xa6,0x05,0x63,0x9e,0xc2,0x86,0x41,0x79,0x8b,0x60,
+  0x53,0x73,0xe4,0xe0,0xcc,0x63,0x45,0x33,0x07,0x6b,0x36,0xff,0x61,0xe1,0x36,0x79,
+  0xb5,0xe6,0xbf,0x33,0xba,0xbe,0x68,0x9b,0xf0,0x84,0xf7,0xef,0x1b,0x99,0x6c,0xdc,
+  0xa3,0xda,0xb4,0x5b,0xaf,0xd9,0x48,0x06,0xe5,0x27,0x84,0xaa,0x5b,0x3d,0x89,0xad,
+  0xcb,0xc8,0xa3,0x24,0xd8,0x50,0xca,0xa0,0x99,0x0e,0x2f,0xf3,0x7f,0x69,0xf8,0x31,
+  0xaa,0x15,0x44,0x17,0x7c,0x37,0xc3,0x7f,0xf8,0x82,0xd1,0x6b,0xcc,0x36,0x0a,0x26,
+  0x4b,0x53,0x63,0x87,0xb4,0xc8,0x32,0xdf,0xa3,0xd2,0x8f,0x3b,0x5e,0x49,0x46,0xee,
+  0xf9,0xdc,0x66,0x09,0x6e,0xda,0x86,0x88,0x51,0xb0,0x5e,0xfa,0x45,0xde,0x5b,0x26,
+  0x00,0xb1,0xef,0x4b,0x6f,0x08,0xa3,0xd1,0xc8,0x1d,0xbe,0x12,0x24,0xe2,0x30,0x23,
+  0xcd,0x8b,0x36,0xa9,0x0e,0xff,0xe1,0x4f,0x2c,0x6e,0x8d,0x46,0x07,0x76,0x6d,0x5b,
+  0xfb,0xca,0x03,0x11,0x98,0xf9,0x72,0x64,0xb0,0x8c,0x2c,0x85,0xc7,0xe1,0x6f,0xe6,
+  0xbd,0x85,0xf2,0xcd,0x8f,0x4a,0x83,0x32,0x1f,0x5c,0xfe,0x3b,0xcb,0x70,0xf1,0x1f,
+  0x92,0x91,0x79,0xf7,0x6b,0x98,0xa4,0x9a,0xd3,0xdf,0x10,0xd1,0xd6,0xb5,0x4b,0xa7,
+  0x95,0x11,0x21,0x4c,0x00,0x64,0x95,0xe5,0x8d,0xe4,0x45,0xc8,0x43,0x48,0xc4,0xd1,
+  0x6f,0x44,0xb4,0xb5,0xf4,0x4b,0x65,0x21,0x94,0x96,0xf3,0xb6,0x36,0xea,0xa8,0x25,
+  0xa1,0xf9,0x1e,0xfc,0x5a,0x46,0xff,0xcb,0xd8,0xc3,0xa2,0xe4,0x45,0xe8,0x82,0x56,
+  0xd1,0x02,0xfd,0xcf,0xb6,0x7b,0xf7,0x08,0x7e,0x9a,0x93,0x14,0x15,0x6d,0xff,0xad,
+  0xb7,0x74,0x40,0xd7,0x88,0xbc,0x46,0xa8,0xa2,0xf9,0x6f,0x8b,0x3d,0x00,0xc4,0xaa,
+  0xdb,0xf3,0xcf,0x88,0xb7,0x90,0xfd,0x46,0xf5,0x83,0xea,0x8a,0x06,0x97,0xfe,0xd7,
+  0x0e,0x79,0x85,0x19,0x0d,0x89,0x67,0xf2,0x76,0x88,0x8c,0x1a,0xe8,0x28,0x92,0x8d,
+  0xf7,0x8a,0x78,0x7c,0xb4,0xc3,0x08,0x36,0x0b,0xe0,0x6c,0x53,0xe6,0x81,0xe8,0xd3,
+  0xe2,0x5a,0x2a,0x19,0x7c,0x3e,0x2f,0x22,0xe6,0x20,0x4c,0x35,0xc0,0x33,0x77,0xf0,
+  0xd7,0x67,0x00,0x05,0xfc,0x2d,0x3b,0x0d,0x7b,0x80,0x25,0xbf,0xdd,0x2d,0xc2,0x1b,
+  0x9b,0x96,0xe3,0xde,0x84,0x90,0xe1,0xef,0x0c,0xc2,0x4f,0xc3,0xaa,0xfb,0xf2,0x56,
+  0x8a,0xeb,0xc9,0x2e,0xa3,0xb2,0x4c,0x88,0x89,0x25,0xf2,0x33,0x5c,0xa3,0xd9,0xc5,
+  0x3f,0x8f,0xd4,0x52,0x48,0x7b,0x48,0xbf,0x07,0x68,0xab,0x00,0x36,0x44,0xf2,0x1d,
+  0x70,0xc3,0x0a,0x56,0x36,0x62,0xea,0xf8,0xdc,0xd8,0xad,0x2b,0x8b,0x7f,0x2d,0xac,
+  0xa2,0x73,0x87,0xf2,0x97,0x4b,0x1b,0x34,0x80,0x66,0xfa,0xe7,0x57,0xaa,0x57,0x7b,
+  0x3f,0x6a,0x9f,0x9b,0xcd,0x3f,0x2f,0x7f,0x8b,0x54,0x30,0xf7,0xd2,0xf8,0x81,0x38,
+  0xc5,0x14,0x53,0x02,0xba,0x07,0x41,0x33,0x3f,0xa5,0xae,0x20,0x73,0x64,0x2c,0xfb,
+  0x2a,0x36,0x99,0xc3,0xc0,0xe8,0x9e,0xbe,0x85,0xaf,0xc1,0x90,0x34,0xa8,0x70,0x9f,
+  0xbf,0xdc,0xe1,0x9f,0x7f,0x95,0xbc,0x16,0x67,0xce,0xc9,0x15,0x4c,0x29,0x1c,0xf4,
+  0xe1,0xdb,0xf1,0xca,0xfa,0x7a,0x74,0x0b,0x5f,0x95,0x7f,0x13,0x9f,0x1b,0x5b,0x3b,
+  0xda,0x78,0x12,0xf5,0xbf,0x4e,0x88,0x43,0xe2,0xb5,0xcd,0x47,0x68,0x75,0xd0,0x3b,
+  0x22,0x7c,0x44,0x2e,0xa3,0x34,0xd8,0x88,0x7d,0xfe,0x0c,0xf8,0xcb,0x58,0xb5,0x31,
+  0x9f,0xc1,0x25,0xed,0x71,0x52,0xf9,0x2e,0xa2,0x2d,0x65,0x17,0xad,0x1c,0xca,0xbb,
+  0x5b,0x3c,0x55,0xb4,0x2a,0x59,0x69,0xe4,0xdf,0xb7,0x61,0x20,0x0d,0x5d,0x83,0xca,
+  0x1d,0x62,0xc2,0x58,0xb5,0xb5,0x52,0x66,0x44,0x88,0xcf,0x68,0x2c,0xa5,0xd0,0x89,
+  0x7f,0xed,0x23,0xab,0x4a,0x2b,0x5f,0x50,0x5b,0xe2,0xa7,0x74,0x18,0xdc,0xd7,0x79,
+  0x16,0xa7,0x57,0xf9,0xc6,0x61,0x46,0x26,0xf9,0x80,0x5e,0x69,0x28,0x77,0x8b,0x27,
+  0x8d,0x55,0x62,0xe5,0x8b,0x6a,0xac,0xa1,0x44,0x5e,0x15,0xab,0x56,0xf2,0x90,0xac,
+  0xe3,0x5f,0xe6,0x31,0xb0,0xd6,0x67,0xe3,0x2f,0x93,0xb4,0x61,0x24,0x6b,0x76,0xee,
+  0x31,0xf2,0x58,0x3a,0x38,0xac,0xd6,0x89,0x3e,0x8c,0x6d,0x0d,0xff,0xc5,0x6c,0xf1,
+  0x38,0x0a,0xa6,0x37,0xe7,0x85,0xc4,0xe7,0xc8,0x63,0xb8,0xee,0xb2,0x3f,0x0e,0x6e,
+  0x7c,0x30,0xa0,0x86,0xc5,0xe3,0x31,0x64,0x12,0x53,0x43,0x0d,0x4e,0xfc,0xeb,0x5f,
+  0x8d,0x23,0x66,0x64,0xd8,0x57,0x07,0xf3,0xf3,0x4e,0xb2,0xce,0x5c,0x74,0x5e,0x7d,
+  0x4a,0xf9,0x30,0x1e,0x49,0x2f,0x8a,0x80,0x3f,0x76,0x44,0xaf,0x5b,0xec,0x9d,0x2d,
+  0x1d,0x01,0xa3,0x7e,0xc0,0xf7,0x54,0x9b,0xdf,0xdf,0x6f,0xd4,0x05,0xf2,0x91,0x8f,
+  0xfa,0xbc,0x50,0x97,0xf6,0xed,0x81,0xfd,0xdd,0xc6,0x5f,0xf2,0x3b,0xde,0x88,0x39,
+  0x29,0x55,0xce,0x8a,0x59,0x8e,0xfa,0xba,0xc9,0x19,0xf0,0x5b,0x22,0xfd,0x52,0x77,
+  0xf9,0x99,0xde,0x77,0x54,0x78,0x88,0xba,0xa5,0xa1,0x3c,0xc6,0x57,0xf9,0x13,0x29,
+  0xad,0x20,0xfe,0x2a,0xd8,0x29,0xbd,0x81,0xf8,0x6b,0x64,0xd1,0xce,0xb6,0x37,0x1c,
+  0xfc,0x55,0x8a,0xb4,0xf3,0xeb,0x86,0xbf,0x57,0x57,0x71,0x3c,0xb7,0xde,0x9c,0x0c,
+  0x7e,0x4b,0xde,0x15,0xf2,0x8f,0xbd,0xf9,0xc3,0x8d,0x75,0x88,0x97,0x0f,0x7a,0x87,
+  0xa5,0xd9,0x15,0xc7,0x59,0x7a,0x95,0x16,0x42,0xce,0x07,0xc5,0x3b,0xdc,0x78,0x91,
+  0x7c,0x84,0xaa,0xcd,0x17,0x0d,0xcb,0x0f,0x6f,0x25,0x0b,0x01,0x0a,0x4d,0x03,0xff,
+  0xb9,0x71,0x85,0x82,0xda,0x5e,0x48,0x72,0x28,0xef,0x15,0x66,0x9a,0x1d,0x29,0x7f,
+  0x50,0xfe,0xf0,0xd1,0xa5,0xc9,0xfc,0x54,0xf9,0xd7,0x39,0x81,0x7c,0xf0,0x91,0x79,
+  0xb1,0x36,0x61,0x56,0x48,0xd9,0x27,0xbe,0x1f,0xda,0x9b,0x9e,0x75,0x42,0x99,0x19,
+  0xd7,0x9b,0x39,0xfe,0x12,0xb8,0xc8,0xf2,0x82,0x54,0xae,0x97,0x71,0xdc,0xe5,0x31,
+  0xda,0x43,0xdd,0x8f,0x46,0x50,0xde,0x4b,0xfc,0x77,0x2b,0xa9,0x86,0x2a,0xf2,0x03,
+  0x99,0x31,0xe3,0x25,0x91,0xab,0x81,0xc0,0x75,0xde,0x94,0xf7,0xb6,0xf9,0x69,0x47,
+  0x4a,0x74,0xe2,0x5f,0x5e,0xa1,0x6d,0xe6,0x32,0xcc,0xb7,0x59,0xd8,0xf0,0x08,0xa9,
+  0x3a,0x7a,0x5b,0xa8,0xe1,0xa8,0xbc,0x5b,0xf9,0x9b,0x7e,0x74,0x5c,0x8d,0x6e,0x32,
+  0xdd,0xc8,0xeb,0x16,0x6f,0x27,0x8f,0x14,0x06,0x8f,0xaa,0x49,0x78,0x06,0x3a,0xf5,
+  0xa0,0x16,0xd0,0xc2,0x47,0x95,0x1a,0xcc,0xc9,0x49,0xd9,0xf1,0x2f,0xc4,0x5f,0x9d,
+  0x51,0xbc,0xc3,0x1b,0x26,0x93,0xdf,0xc8,0x91,0x97,0x6f,0xc3,0x09,0xdf,0xed,0xf7,
+  0x1f,0x7e,0x28,0xa5,0x56,0xc2,0xcb,0xca,0x6f,0xac,0x85,0x2f,0x26,0xfe,0xc6,0x98,
+  0x7b,0xd8,0x97,0xf4,0x24,0x01,0x91,0xd5,0x6a,0x6b,0x11,0x9a,0x7d,0x4b,0x0c,0x9b,
+  0x0b,0x53,0x6a,0xd2,0xc6,0x5f,0xc3,0x80,0xd1,0x6e,0x00,0xb7,0xf0,0x91,0x7d,0xf4,
+  0x00,0xba,0xd6,0x28,0xea,0x37,0x8a,0x4f,0x13,0xaa,0x7d,0xbd,0x5f,0xf2,0x67,0x18,
+  0x94,0x1c,0xd1,0xde,0x47,0x2a,0x95,0x58,0x63,0x0b,0xb9,0x62,0xdc,0x44,0xd6,0x61,
+  0x18,0x05,0xb3,0x3e,0x8e,0x0f,0x97,0x2f,0xcf,0xd2,0xff,0x9a,0x20,0xfe,0x05,0x3e,
+  0x3f,0x26,0x85,0x5a,0x44,0x1c,0x7f,0xb0,0x65,0xf5,0xc6,0x0e,0xfe,0xb8,0xf8,0x57,
+  0xc6,0xd8,0x84,0xac,0x26,0xd4,0x6f,0xb5,0x08,0xfe,0x89,0xc6,0x64,0xf2,0x0f,0x6f,
+  0xfd,0xb8,0xf8,0x17,0xdc,0xf3,0x32,0xa1,0x8e,0x0a,0x79,0xc6,0xc8,0x8c,0xe9,0x5d,
+  0x10,0xca,0xfd,0xe3,0xf5,0x5f,0x68,0x74,0x88,0x7e,0x11,0xb6,0x36,0xde,0xb2,0xa3,
+  0x1d,0x0d,0xbf,0x3d,0xc6,0x31,0x26,0xae,0xff,0xca,0x32,0x7a,0xa4,0x2a,0xb9,0x3f,
+  0xd9,0xcd,0x5b,0x46,0x49,0x78,0xa2,0x31,0x29,0xa9,0xf7,0x13,0xe3,0x5f,0x86,0xda,
+  0x4f,0x7e,0x4f,0x0e,0x7c,0x6c,0xa8,0xe5,0x3f,0x51,0xff,0x65,0x1b,0xda,0x61,0xfb,
+  0x6b,0xd8,0xdf,0x47,0x71,0xba,0x2c,0xe3,0xc4,0x27,0xc4,0xbf,0x4c,0xf0,0xeb,0x00,
+  0x4a,0x0f,0xd8,0x8c,0xfd,0xba,0x7f,0xa2,0x39,0x4c,0x49,0xdd,0x19,0xfe,0xc3,0x8f,
+  0x59,0xaf,0x6b,0xe2,0x2f,0xd0,0xb8,0xf9,0x71,0xeb,0x25,0xec,0xc8,0xaa,0xff,0x4a,
+  0x7d,0x5c,0xfc,0x8b,0xf3,0xf2,0xd9,0x2a,0xc0,0xe4,0x80,0x6d,0x8c,0x1d,0xbc,0xef,
+  0x8f,0xd5,0x7f,0x31,0xa3,0x44,0x7a,0x5e,0x7f,0x4e,0x09,0xf5,0x5a,0x2d,0x21,0xd3,
+  0x37,0x83,0x19,0x41,0xdb,0xc0,0xc1,0x35,0x4e,0xfe,0xe1,0xc7,0xce,0x33,0x3a,0x93,
+  0x1f,0x7e,0xec,0x12,0xd8,0xc6,0x1f,0xad,0xff,0xba,0xc0,0x73,0x3c,0x2a,0x58,0x76,
+  0xa8,0xd5,0xf2,0x31,0xf7,0xcf,0xdb,0x7f,0x3c,0xfe,0xc5,0xf8,0x0f,0x35,0x79,0x07,
+  0xd9,0x62,0x62,0xfe,0xbc,0x7c,0x80,0x19,0xe3,0x2b,0x0e,0x32,0xf9,0x87,0x3f,0xfa,
+  0xb8,0x79,0x2e,0x65,0x6c,0x87,0xce,0xf4,0x6e,0x99,0x78,0x9e,0xff,0x58,0xfd,0x17,
+  0x37,0x64,0x98,0xc1,0x1d,0x1b,0xec,0xe5,0xa6,0x13,0x3c,0xa7,0xe6,0x75,0x9f,0x50,
+  0xff,0xc5,0x8c,0xb4,0x74,0x8b,0x7c,0xd9,0x0c,0xf3,0x96,0x3d,0xc9,0xf0,0x44,0x63,
+  0x3e,0xa9,0xfe,0x8b,0x33,0xff,0x9f,0xa6,0xc3,0xd1,0x8c,0x52,0xf0,0x04,0x63,0x16,
+  0x7d,0x72,0xfd,0x17,0xe6,0xa6,0xca,0x99,0xc4,0xad,0xd1,0xc4,0x58,0x3e,0xf3,0xff,
+  0x64,0xfd,0x17,0x1a,0x53,0xdb,0x31,0x48,0xb1,0x20,0x51,0x34,0xe8,0x96,0xeb,0xca,
+  0x1e,0xf3,0x89,0xf1,0x2f,0x75,0xa3,0xa7,0x82,0xae,0x6e,0xb7,0x18,0xe9,0xbb,0x3e,
+  0xee,0x3a,0x7f,0xbc,0xfe,0x8b,0xf1,0x1f,0xf2,0x60,0xb4,0xd5,0xa2,0xe9,0xa8,0xf5,
+  0x6c,0x8f,0xb1,0x08,0xd2,0x17,0x7c,0x72,0xfd,0x17,0x17,0x69,0x3a,0xcc,0x44,0x9a,
+  0x8a,0xd3,0x85,0xe7,0x8d,0xee,0x89,0xc7,0x7c,0x62,0xfc,0x0b,0x89,0x38,0x1a,0xac,
+  0x42,0x30,0xd4,0x08,0xc3,0x9c,0xb7,0x09,0xe6,0xf9,0x13,0xea,0xbf,0x90,0xe4,0x50,
+  0xad,0x83,0xcd,0x8e,0x2d,0xd3,0x36,0x30,0xba,0x27,0x5e,0xaf,0x89,0xf2,0x0f,0xdd,
+  0x86,0xa0,0xba,0xc2,0x5e,0x69,0xb7,0x91,0x3d,0xd8,0xc9,0x3f,0xfc,0xb8,0xf8,0x17,
+  0x3c,0x5f,0xb9,0xb6,0xaa,0x5a,0xbb,0x4b,0x5e,0x6d,0xcc,0xe0,0x3f,0x56,0xff,0x65,
+  0x1b,0x15,0xb2,0x73,0xdb,0xec,0x18,0xbf,0xee,0xe2,0x27,0xd7,0x7f,0x71,0x92,0xc3,
+  0xe2,0xa9,0x64,0x34,0xda,0xcd,0xe7,0x67,0xf7,0x38,0x7e,0xfe,0xd1,0xf1,0xfc,0x87,
+  0x1f,0xf3,0x5c,0xa0,0x91,0xb4,0x5b,0x94,0x82,0x89,0xaf,0xf3,0xeb,0x4f,0x88,0x7f,
+  0xf1,0xfb,0xc7,0x8c,0xf1,0xdb,0x46,0x5e,0x29,0x86,0xc7,0x8f,0x11,0x3e,0xb9,0xfe,
+  0x0b,0x8c,0xd3,0x1b,0x66,0x93,0x87,0xa9,0x9f,0xb7,0xec,0xef,0xf7,0x4f,0x34,0xe6,
+  0x13,0xe3,0x5f,0x8c,0x6f,0xb9,0x80,0x3c,0xe2,0xbc,0xbe,0x0c,0x3c,0x45,0xf7,0x8f,
+  0x7f,0xe9,0x7d,0x52,0xfc,0xab,0x17,0xae,0xe3,0x23,0x8f,0x18,0x36,0xed,0xbc,0x2d,
+  0x0b,0xb2,0x4b,0xc8,0x1e,0xec,0xc2,0x5f,0x1f,0x13,0xff,0x5a,0x2e,0x4d,0x11,0x7f,
+  0xc5,0x83,0x5c,0xaf,0xb2,0x83,0x71,0xa7,0x6b,0xd1,0xca,0x72,0x67,0xf0,0xdb,0x9f,
+  0x10,0xff,0x02,0xb4,0xa5,0x0e,0xa1,0xc0,0xfd,0xc7,0xee,0x5f,0xb2,0x9b,0x7f,0xe3,
+  0x63,0xe3,0x5f,0x48,0x82,0xed,0xb0,0xb1,0x39,0x81,0xb0,0xf1,0x83,0x3f,0xa9,0xfe,
+  0xab,0x4f,0xc5,0x43,0xc2,0x55,0xce,0xb4,0x94,0x96,0xf5,0x66,0x8d,0x69,0xda,0xa5,
+  0xfd,0x27,0xea,0xbf,0x38,0xd9,0xaf,0xfb,0x3a,0x19,0x23,0x7b,0xf0,0xc1,0x3f,0x1e,
+  0xff,0x62,0xeb,0xde,0x4f,0xe2,0x56,0x21,0x33,0x4a,0x25,0x4e,0x9c,0xdb,0xf3,0xc7,
+  0xeb,0xbf,0xd0,0x78,0x4a,0xc4,0x13,0x72,0xcb,0x3f,0xbc,0x40,0x6d,0xc3,0x56,0x5e,
+  0xb3,0x09,0x0c,0x3f,0xa1,0xfe,0xcb,0x64,0x82,0xce,0x1f,0xea,0x56,0x0b,0x4a,0x83,
+  0x8d,0x1f,0xb3,0xe8,0x93,0xeb,0xbf,0x4c,0xdf,0xf2,0xb6,0x88,0x7e,0x89,0x0b,0x81,
+  0x5d,0x24,0x97,0xb5,0x1a,0xf7,0x98,0x46,0x67,0x70,0xda,0xde,0xbf,0x3e,0x26,0xfe,
+  0x65,0x76,0xf6,0x88,0x53,0x69,0xcf,0x62,0x16,0xe4,0x3a,0x43,0x7a,0x8c,0x89,0xfc,
+  0xc3,0x05,0x9f,0x5c,0xff,0x65,0xaa,0xf1,0x78,0xb0,0xdd,0x61,0xad,0xdf,0x43,0x26,
+  0xf6,0x33,0x3f,0x39,0xfe,0xa5,0xda,0x82,0xe9,0x16,0xf3,0x40,0x72,0xe2,0xf5,0x72,
+  0xe9,0x7f,0x7d,0x9c,0x5f,0x37,0x09,0xd3,0x90,0xac,0x65,0xfa,0xf0,0x63,0xfc,0x31,
+  0x87,0x7f,0x63,0xa2,0xf8,0x17,0x37,0xd2,0xd2,0x29,0x5b,0xba,0x68,0x4c,0xd7,0x3a,
+  0x57,0x8b,0x5b,0xff,0x4b,0xae,0x27,0xde,0x11,0x69,0x3f,0xe3,0xb7,0x61,0x06,0xc6,
+  0x6e,0x30,0xd1,0xb7,0xe4,0x7d,0x78,0xac,0x16,0xf5,0x40,0x0b,0xca,0x3a,0xf8,0xfa,
+  0x25,0x64,0xbc,0xa9,0xd7,0x7d,0x27,0x8b,0x31,0xd0,0x5c,0x8f,0xcf,0xbb,0xc3,0xbf,
+  0x71,0x46,0xc1,0xe3,0x59,0xa5,0x87,0x51,0x6a,0xd8,0xc1,0x44,0x5a,0x65,0x7a,0x01,
+  0x2f,0x93,0x36,0xb2,0x15,0x9d,0x76,0xcc,0x3f,0x04,0xfc,0xd5,0x81,0x19,0x14,0xb4,
+  0x56,0x07,0x68,0xf6,0x9e,0x62,0xe1,0x2f,0x87,0xff,0xb0,0x1f,0x49,0xe6,0x51,0x8b,
+  0x6d,0xad,0xd2,0x29,0xea,0x66,0x29,0x23,0x42,0x64,0xb4,0x1b,0x7e,0x2f,0xb1,0x04,
+  0xd7,0xd6,0x6a,0x3b,0x04,0x24,0x3c,0xe1,0xdb,0x16,0x41,0x6a,0x5f,0x65,0x0c,0xff,
+  0x7c,0xe1,0xcf,0xc8,0x9a,0xd6,0xaa,0x94,0x92,0x0a,0x7b,0x95,0xce,0x3b,0xe0,0xfb,
+  0xa4,0xe2,0x4f,0xe9,0x9d,0x5f,0x0c,0x9a,0x04,0x75,0xa9,0x1e,0xab,0xc4,0xe5,0xbe,
+  0x76,0x85,0xb1,0x17,0x80,0x98,0x44,0x1b,0x90,0x06,0x7f,0x7a,0x48,0x45,0x92,0x16,
+  0x8c,0x0a,0x81,0xe1,0xd4,0x7f,0xfd,0x36,0x7e,0xe8,0x74,0x24,0x1d,0xec,0x29,0xfe,
+  0x59,0xc3,0x11,0x98,0x84,0x60,0x57,0xe3,0xbf,0x8a,0x47,0xe6,0x45,0xd2,0x15,0xdd,
+  0x6a,0x90,0xbe,0x43,0x98,0x70,0xc0,0xbf,0x56,0x5c,0x88,0x76,0xff,0xd2,0xf7,0xa0,
+  0xf4,0xbe,0x3e,0x9a,0x8e,0xe8,0xbe,0xef,0xdb,0xef,0xb1,0x9e,0x4c,0xfe,0x61,0x8f,
+  0xf7,0x0a,0x99,0x1b,0xf7,0x5d,0xe4,0xd4,0xfd,0x1f,0xae,0x1b,0xa9,0xb9,0xdf,0x00,
+  0xe3,0xac,0xef,0xbc,0x74,0x99,0xbe,0x16,0xaf,0x1f,0xf4,0x8d,0xb2,0x79,0x86,0xd5,
+  0xe9,0xe5,0x99,0x33,0x64,0x42,0xfe,0x8d,0xed,0xad,0x17,0x1a,0x22,0x03,0xeb,0x76,
+  0x4a,0xef,0xd2,0x23,0x46,0xb8,0x0f,0x73,0x0b,0x07,0x8e,0x90,0x48,0x1f,0x03,0xe9,
+  0x47,0xf4,0xee,0x13,0xde,0x9d,0x0b,0x2a,0x39,0xc3,0x79,0xbb,0xb4,0x2c,0x81,0x61,
+  0x14,0x24,0x4b,0x34,0x91,0xd4,0x74,0xd1,0x83,0xaa,0x13,0xff,0x62,0xfb,0x57,0x82,
+  0xf1,0xc6,0x3f,0x97,0xe3,0x37,0x9f,0x4a,0x35,0x7e,0x03,0xeb,0xe3,0xce,0x21,0xed,
+  0x7c,0xb3,0xaa,0xf8,0x7b,0x95,0x99,0x28,0x47,0x8e,0x4f,0xc1,0x9a,0xa2,0xa9,0x64,
+  0xb7,0x1f,0xe5,0x18,0x8a,0xde,0x25,0x7b,0x4f,0x56,0xbd,0xb4,0x60,0x53,0xdc,0x89,
+  0x7f,0xc5,0x48,0x2a,0xb6,0x42,0x83,0xeb,0x1c,0x17,0xda,0x88,0x7f,0x78,0x41,0x8a,
+  0x54,0xb3,0xf5,0xf2,0xdc,0x22,0x1e,0x6d,0x68,0x8b,0xeb,0x43,0x4a,0xdd,0x86,0xb5,
+  0x70,0x9d,0x60,0xaf,0x2a,0xc7,0x6f,0xc5,0x0c,0x9c,0xd2,0x52,0x4d,0x3c,0xce,0x49,
+  0xcb,0xeb,0x44,0x27,0xfe,0x75,0x35,0xd9,0xd9,0xc5,0x45,0x96,0x0d,0x40,0x5b,0x43,
+  0x9e,0x95,0xfe,0xaf,0x2a,0xab,0xb6,0x55,0x9e,0x59,0xf3,0x4d,0xf1,0x55,0x79,0x55,
+  0xa2,0x2c,0x1d,0xf8,0xd6,0xd6,0x1f,0x91,0x55,0x89,0xca,0xb7,0x1a,0x91,0x91,0xfe,
+  0x69,0xb3,0x52,0x57,0x16,0xc3,0xe0,0x5d,0x89,0xca,0xd7,0xd5,0x93,0xa2,0xe2,0xd2,
+  0xff,0x4a,0x05,0x65,0x80,0x54,0xef,0x36,0x3c,0x57,0x14,0x3e,0x07,0x68,0x2b,0xd8,
+  0xf0,0x1c,0xfd,0x6a,0xba,0x0a,0xf3,0x0f,0x9f,0x4b,0x16,0x0d,0x2c,0x9c,0x2d,0xad,
+  0xd5,0x9e,0x23,0x75,0x83,0x3e,0x51,0x6a,0xa2,0x67,0x13,0x75,0x98,0xf1,0x62,0xe1,
+  0xaf,0x99,0xe5,0x8e,0xfe,0x57,0x8a,0x5c,0xd4,0xea,0x89,0x8a,0x65,0x5f,0xbf,0xd3,
+  0xea,0xcd,0xfc,0xb3,0xc8,0x45,0x29,0xd4,0x3f,0x87,0x71,0xfc,0xe8,0x95,0x12,0x58,
+  0x94,0x96,0xc6,0xbb,0x2c,0x04,0x8d,0x42,0xb1,0x64,0x6e,0xbb,0xcf,0x2c,0xbf,0x68,
+  0x17,0x5a,0xba,0xf4,0xbf,0x46,0xc4,0x59,0x86,0x2f,0x55,0x7e,0xcc,0x56,0x51,0x0c,
+  0xca,0x78,0x6f,0x60,0xbd,0x9e,0xf1,0x5b,0x02,0x2b,0xb8,0x5b,0x2a,0x80,0xae,0x5a,
+  0x78,0x03,0x14,0xb3,0x72,0xf5,0x32,0x6f,0x42,0x3a,0x86,0xfa,0x5f,0x88,0xd1,0x9c,
+  0xf8,0xd7,0x46,0xf2,0xb4,0x28,0x18,0x18,0xe4,0x4a,0xac,0xaa,0xa8,0x1c,0x58,0x70,
+  0x8f,0xf8,0x43,0x3c,0x44,0xed,0x8f,0xde,0x2b,0xd6,0x11,0xe4,0x3f,0x54,0x5a,0xa4,
+  0xbb,0xc8,0x3a,0x72,0xd3,0x49,0x15,0xe3,0x5f,0x3b,0x09,0x23,0xe0,0x3d,0x45,0x7e,
+  0xc5,0x33,0x31,0x32,0xfa,0x5f,0x72,0x8a,0x2e,0xd1,0xd5,0xfb,0xc5,0xcb,0xf2,0xe3,
+  0xa9,0xca,0x21,0xf5,0x5b,0x5b,0xaf,0xef,0xd8,0x95,0xae,0x4c,0x47,0xef,0x2b,0x9a,
+  0x42,0x7f,0x9e,0x28,0x1b,0xca,0xbb,0x4f,0xbc,0xdf,0x7c,0x7c,0xf8,0xc6,0x61,0x75,
+  0x21,0xfc,0xd5,0xd3,0xed,0xd5,0x7e,0x65,0x71,0xfc,0x55,0x06,0x81,0x17,0x2c,0xce,
+  0xe8,0x7f,0x99,0xa4,0x47,0x5f,0x3a,0x53,0x9d,0x19,0x3f,0x46,0xdb,0x92,0xc1,0x74,
+  0xe7,0x4e,0x71,0x5d,0xc5,0x0e,0x5a,0x35,0x14,0xe8,0xf6,0x78,0xcd,0xce,0x64,0x6c,
+  0xf8,0xc6,0x90,0xf8,0x79,0xd2,0xd9,0x57,0x31,0xbc,0x60,0xa6,0xd8,0xab,0x75,0x29,
+  0xc1,0x16,0xa5,0x04,0xde,0x87,0x8f,0xe0,0x23,0x5c,0x92,0x15,0xff,0x02,0x94,0xe6,
+  0x1b,0x94,0xce,0xd3,0xf7,0xb6,0xd5,0x6f,0xf2,0x0d,0x95,0xcf,0x21,0x1f,0x91,0xfa,
+  0xed,0xde,0xa1,0xb6,0x6b,0xc5,0xf7,0x3a,0x6a,0xb6,0xe6,0xbf,0xd5,0xfa,0xad,0xd8,
+  0x7b,0x03,0x73,0x76,0xfa,0xfe,0x1a,0x19,0xe9,0x3b,0xea,0xd7,0x07,0xd3,0xc5,0x43,
+  0xe0,0xea,0x87,0xa8,0x6f,0xa8,0x2d,0x83,0xbf,0xf4,0x11,0x52,0x2b,0x1e,0xa7,0x4c,
+  0xf6,0x2b,0xa2,0xf8,0x68,0xdb,0x69,0x4b,0x91,0xb9,0x91,0x7b,0x71,0x05,0xcc,0x8b,
+  0x93,0xdd,0xb4,0xf3,0x71,0x29,0xad,0x70,0x07,0xaf,0xcd,0xc1,0x5f,0x7d,0xf4,0x90,
+  0x1e,0x6e,0x62,0xfc,0x6c,0x98,0x9a,0xe8,0xa5,0x5f,0xd2,0x8d,0x7e,0x12,0x96,0xbd,
+  0x1d,0xe0,0x1f,0x9e,0xa4,0x61,0xd1,0xdb,0x6a,0xcb,0x12,0x6d,0x2a,0xac,0x90,0x57,
+  0x9b,0x91,0x7b,0x38,0x89,0x3a,0x8d,0x44,0xbd,0xdf,0xcf,0xe0,0xaf,0xbf,0x26,0x4f,
+  0xe8,0x7e,0x03,0xb9,0x1a,0xa2,0xfd,0xb4,0x4a,0xef,0x78,0x40,0x2c,0x43,0xad,0x28,
+  0x2d,0xb0,0x56,0x2c,0x8f,0x75,0x74,0xf8,0x35,0x8b,0xcf,0x61,0x16,0x51,0x1f,0xf5,
+  0x4c,0xb2,0x69,0x13,0xde,0x20,0xbb,0xcd,0xaa,0x68,0x60,0x43,0x86,0xff,0x70,0xaa,
+  0x02,0x60,0xad,0x41,0x49,0x8a,0x69,0xbd,0x87,0x04,0x15,0xa5,0xfd,0x5a,0x2a,0xc3,
+  0x75,0xc4,0x8e,0xd6,0x35,0xba,0xbc,0x49,0x4b,0xe6,0x06,0x92,0x61,0x0b,0x17,0x24,
+  0x0e,0x6e,0x4b,0x3c,0x61,0xe0,0x75,0x8a,0x06,0x75,0x5b,0x87,0xd7,0xda,0xbf,0x9a,
+  0x64,0xba,0x45,0x4f,0x22,0xa5,0x61,0x1f,0xa0,0xad,0x60,0xbf,0x52,0x24,0xb6,0xd3,
+  0xd5,0xa8,0xad,0x5c,0x54,0x54,0x81,0xf8,0x2b,0x5a,0x5a,0x9c,0xdb,0x47,0xbb,0x66,
+  0x54,0x44,0xa5,0x84,0x7f,0x1b,0xd9,0x22,0x06,0x8d,0x4e,0x8d,0x38,0x24,0xea,0x0e,
+  0xfe,0x5a,0x62,0xf4,0x37,0x87,0x4b,0x30,0xa5,0x30,0x8a,0x69,0x87,0xc1,0x1c,0xf5,
+  0x89,0x86,0x7e,0x12,0x2a,0x69,0xcf,0x11,0xcb,0x8c,0x93,0xcd,0xa1,0x12,0xaf,0x8c,
+  0x53,0xc7,0xf1,0xd7,0x76,0x32,0xc4,0xa6,0xb7,0x30,0xad,0x71,0xd6,0x3b,0x57,0xfc,
+  0x8b,0x57,0x4a,0xae,0x2f,0x3e,0xd3,0xf4,0x8a,0xc6,0x48,0x0e,0x97,0x31,0x92,0x43,
+  0x87,0xed,0xd0,0xf7,0x08,0x1a,0xa1,0x48,0xd3,0xba,0x01,0xe9,0x5e,0xf1,0x3f,0xc4,
+  0xb9,0xbc,0xa4,0xeb,0x2c,0x27,0x90,0x77,0xc5,0xbf,0x98,0x92,0xd7,0xf7,0xdb,0x3e,
+  0x22,0x2f,0x6e,0xaf,0x5f,0x2e,0x9f,0x6c,0x9b,0x45,0x0e,0x75,0xd4,0xff,0x5f,0xde,
+  0x5f,0x4b,0x1f,0x91,0x4b,0xc9,0x9a,0xd8,0xc2,0x5f,0xff,0xf6,0xa3,0xf6,0xd1,0xf6,
+  0xf0,0xd7,0xbc,0x03,0xd2,0x4e,0x72,0x29,0x67,0x2e,0x8a,0x58,0x9d,0xb3,0xaa,0xc6,
+  0x32,0xf9,0x87,0x43,0x22,0xca,0x2e,0x07,0x90,0x82,0x72,0x4d,0x53,0xb0,0xe4,0xe1,
+  0x76,0x58,0xaf,0xed,0xa8,0x41,0x43,0xc5,0x5e,0x74,0x33,0x34,0xa5,0xbd,0x01,0xbc,
+  0x77,0x63,0x16,0x61,0x89,0x6d,0x4c,0x9a,0x39,0x39,0x0e,0x7f,0x31,0xfd,0x2f,0x9e,
+  0x52,0xf8,0xbc,0xd6,0x2a,0x54,0x19,0x1d,0x9a,0x7f,0x2a,0x69,0x95,0x83,0x46,0xb4,
+  0xa4,0xe8,0x79,0xa5,0xcb,0xd0,0x9b,0x15,0xed,0x0e,0xd4,0x1e,0xf2,0x63,0x26,0x61,
+  0xfb,0x38,0xfc,0x75,0x30,0x83,0xbf,0x50,0xd3,0x4d,0xd9,0x28,0x0e,0xa2,0xda,0x32,
+  0x96,0x5d,0x54,0xe8,0x4f,0x78,0xab,0x30,0xda,0xf5,0x06,0xdd,0x1b,0xf3,0x47,0x95,
+  0x8d,0x4b,0x07,0xe9,0x6e,0x6d,0x5a,0x73,0x34,0x51,0x04,0x88,0x4c,0xf8,0x7b,0x43,
+  0xda,0xd0,0xc0,0x99,0x58,0x54,0x57,0xfd,0xd7,0x1b,0xc6,0x21,0x33,0x1c,0x85,0x57,
+  0xca,0x9b,0x0d,0x87,0x9a,0x23,0xd1,0xb5,0x89,0xce,0x1b,0xc8,0x21,0x23,0x72,0x6f,
+  0x70,0xd3,0x23,0xa8,0xa4,0x1c,0x5e,0x19,0x4c,0x48,0x6f,0x28,0xa3,0x66,0x38,0xe6,
+  0xbd,0x4a,0xfa,0x09,0x81,0x99,0xbf,0x67,0x91,0x8b,0x49,0xde,0xe6,0x3f,0x24,0x3f,
+  0x21,0x67,0x3b,0xa0,0x65,0x3d,0x76,0xb5,0x33,0x15,0x86,0x37,0xb7,0x8f,0xfa,0xa1,
+  0x05,0xe3,0x68,0xa3,0x64,0x3f,0x76,0x31,0x45,0xb0,0xe5,0x48,0x7b,0x18,0x1d,0xed,
+  0x88,0x7c,0x9d,0xe7,0x1f,0x72,0xfc,0xe5,0xc4,0xbf,0xb6,0x88,0xfd,0xc6,0x07,0x45,
+  0x9c,0x32,0xb4,0x29,0x22,0x7a,0xd7,0x16,0x97,0xc9,0x18,0xed,0xf2,0xb5,0xb7,0x61,
+  0xd9,0x57,0x44,0x09,0xb6,0x4b,0xa7,0xe1,0xfe,0x09,0x0b,0x48,0x4d,0x4f,0xfa,0xc9,
+  0x14,0x5e,0x11,0x86,0xcc,0xa5,0xbe,0x07,0xda,0x6c,0xfc,0x25,0xd7,0xd2,0x87,0x3b,
+  0xca,0x93,0x18,0xe4,0x02,0xc7,0xa3,0x32,0xa9,0xbc,0x2d,0xfd,0x15,0xac,0xe0,0x9c,
+  0x94,0x3a,0xe4,0xb9,0x85,0x3c,0xfc,0x7c,0x75,0x52,0x49,0x33,0xb4,0xa5,0xd3,0x82,
+  0x37,0xc4,0xf3,0xda,0xc3,0x1d,0xd5,0x29,0x58,0xb8,0x39,0xca,0x7e,0xa3,0x7a,0xbb,
+  0xea,0xd2,0xff,0x5a,0x42,0xa9,0x09,0x8b,0x1b,0x12,0xdf,0x0b,0xb4,0x6e,0x08,0x22,
+  0xe1,0x76,0x81,0xd1,0x46,0xaa,0x7e,0xa9,0xce,0x05,0xdc,0xd4,0x99,0xa8,0x1a,0x50,
+  0xb4,0xdc,0xa3,0xe0,0xb7,0xe8,0xbd,0x0b,0x72,0x44,0x33,0xd4,0x6a,0x06,0x63,0x9e,
+  0x90,0x98,0x6f,0xee,0x30,0x61,0xbd,0x66,0xdb,0xf8,0x4b,0x17,0x88,0x42,0x89,0xae,
+  0x61,0x36,0x9d,0x86,0x25,0xb7,0xca,0x70,0xd1,0x5d,0x00,0x07,0x6e,0x34,0x3b,0x57,
+  0xfa,0xff,0x0c,0xb3,0x11,0x0e,0x2a,0xb1,0x22,0x8e,0x0b,0x3c,0x31,0xf1,0x97,0xfe,
+  0x07,0x48,0xf5,0x52,0xcf,0x08,0xd3,0x17,0x76,0xe3,0xaf,0x80,0x72,0x35,0xe9,0xa3,
+  0x65,0x7a,0x70,0xa5,0x78,0x99,0x51,0x6a,0x04,0x57,0x96,0x23,0x97,0xe0,0x5c,0x1d,
+  0xbc,0xaf,0x29,0xe4,0x41,0xa4,0x9d,0x5f,0xcc,0xf0,0x57,0xd7,0x69,0x5f,0xb4,0xf1,
+  0x97,0xe4,0x79,0x3a,0x37,0xf6,0x85,0x95,0xea,0x94,0x71,0xf8,0xcb,0xc2,0xb9,0xa9,
+  0xb2,0x33,0x5e,0xf0,0xf9,0x29,0xec,0x83,0x58,0x0c,0x8e,0x69,0x6c,0xd2,0x90,0xc8,
+  0xd8,0x1b,0x58,0x1a,0x1b,0x8d,0x98,0xeb,0x68,0x79,0x1f,0xe3,0x4b,0xc9,0x47,0x82,
+  0x08,0x4b,0x00,0xc5,0xa9,0xff,0xfa,0x80,0x1c,0x6a,0xbf,0x39,0x16,0xdc,0x2d,0xbd,
+  0x39,0x70,0x65,0x63,0x64,0x5b,0xb0,0x1f,0xd9,0xb0,0x13,0x73,0x07,0xbd,0x23,0xea,
+  0x74,0xe3,0xb5,0xd6,0x19,0x31,0xf8,0x3e,0xfb,0x95,0x0b,0x9b,0x6a,0xd3,0xbe,0x43,
+  0xf0,0xc4,0xfd,0x1e,0x5e,0x9e,0x3c,0x93,0x87,0xc7,0xbf,0x1c,0xfd,0xe5,0x9d,0xf4,
+  0xa1,0xd6,0x72,0x51,0x59,0x29,0xfe,0x92,0x02,0x14,0x5a,0xa9,0x18,0xd2,0x5d,0x68,
+  0x50,0xcf,0x80,0x58,0xd4,0xbe,0x9a,0x6c,0xa1,0x4a,0x4c,0x9c,0x2c,0x1f,0x48,0x96,
+  0x0d,0xaa,0xf3,0xfc,0x27,0x68,0x17,0x29,0xab,0x50,0xef,0x11,0x2d,0xa2,0x92,0x7b,
+  0x1d,0xfc,0x65,0x6c,0x54,0xda,0xbd,0x65,0x24,0xef,0x1e,0xf1,0xa4,0x06,0x53,0x87,
+  0xf4,0x26,0x77,0x96,0xec,0x12,0xaa,0xcd,0x3c,0x64,0x3b,0x5c,0xa5,0xdd,0x70,0x30,
+  0x6f,0x80,0x05,0x1c,0x61,0xe6,0x71,0x1f,0x7c,0x9a,0x94,0x2d,0xc4,0x93,0x49,0xcd,
+  0x02,0xbc,0xa6,0x5d,0xff,0xd5,0x47,0x3a,0x74,0xdd,0x9f,0x77,0x0b,0x86,0xb4,0xcc,
+  0x2a,0xed,0xb6,0xdd,0x22,0x43,0xe2,0x29,0xb5,0xa4,0x48,0x30,0xda,0x66,0x54,0x6c,
+  0xcf,0xcb,0x11,0xf3,0xa3,0x3b,0xee,0xd6,0xcd,0x05,0x3e,0xf1,0x85,0x66,0x78,0x72,
+  0x49,0xc6,0x9f,0x9f,0x99,0xd1,0x5f,0xde,0xbe,0xe2,0xb0,0x11,0x4e,0x7c,0xbe,0xa7,
+  0xfc,0x6d,0x24,0x1b,0x7f,0xd9,0xdb,0x23,0x7d,0x9d,0x5e,0x48,0x46,0x06,0xf2,0xeb,
+  0xa4,0x6a,0xf1,0x88,0xfc,0x4f,0xe9,0x6f,0x94,0x48,0xff,0x2a,0xff,0x61,0x5e,0xad,
+  0xb9,0x08,0xee,0x79,0x78,0x0d,0x86,0x87,0x7d,0xa9,0xc6,0xa7,0xf8,0x11,0x6e,0x4f,
+  0x26,0xff,0xf0,0x2d,0x72,0x41,0xda,0x63,0x16,0xa4,0xda,0x06,0x79,0x79,0xc2,0xce,
+  0x47,0xce,0xe8,0x17,0xbc,0x91,0xa6,0x29,0xc8,0xd4,0xf7,0x76,0x43,0xad,0x59,0x90,
+  0x28,0x66,0x95,0x26,0xcf,0xc3,0x8e,0x36,0x88,0xcf,0xe9,0x09,0x9f,0x45,0x56,0x4f,
+  0xd7,0xed,0x6b,0x73,0xf0,0x17,0x8a,0xb6,0xd4,0x50,0xdf,0x70,0xf9,0x08,0x39,0xee,
+  0xa9,0x7f,0xce,0x6b,0x96,0xdf,0x87,0xb2,0xcb,0x07,0x17,0x8e,0xb4,0xdd,0x1f,0xbb,
+  0xbc,0xa5,0x26,0xe6,0x7d,0xb9,0xad,0x4e,0xbf,0x42,0x6e,0x3e,0xa8,0x1e,0x92,0x66,
+  0x92,0x2b,0x4a,0x4d,0xc3,0xc2,0xe1,0xc6,0xf3,0xf4,0x38,0xad,0x19,0x5c,0x38,0x9a,
+  0xe1,0xdf,0xf8,0x7a,0x60,0x8f,0xe9,0xef,0x56,0x53,0xb9,0xef,0xea,0x9d,0xad,0x55,
+  0xc3,0xc1,0xb8,0xf4,0x77,0x7a,0x27,0xb9,0xff,0x4e,0xef,0x1e,0xb1,0x5a,0xdb,0x63,
+  0xf8,0xd3,0xca,0x86,0x46,0xc4,0x68,0xfe,0xde,0x05,0x25,0xf1,0x69,0xe0,0xd7,0xcd,
+  0x5c,0xfe,0x50,0x0a,0x93,0xdf,0x0c,0x7d,0x00,0x50,0x80,0xcd,0x7f,0x28,0x4f,0x57,
+  0xf6,0x3c,0xef,0x4f,0x2f,0x48,0xdd,0x71,0xf4,0x8b,0x9d,0xda,0xf4,0xbe,0xd2,0x9e,
+  0xbf,0x6c,0x2a,0xe9,0x94,0x83,0xcf,0x29,0x5b,0xc5,0x15,0x65,0x5d,0x44,0xbf,0x5d,
+  0x49,0x34,0x20,0x46,0x9b,0x66,0xc2,0x5b,0x74,0x1a,0xe0,0x82,0x69,0x4b,0xf2,0x50,
+  0x19,0x6a,0x4d,0xc0,0x8f,0x8c,0x52,0x36,0xfe,0x6a,0x52,0xc8,0x8e,0x00,0x78,0x0e,
+  0xe1,0x78,0x5f,0x2b,0xb8,0x97,0x03,0x58,0x6f,0x2e,0xb4,0x19,0x01,0x73,0x13,0x26,
+  0x6e,0x75,0x01,0x52,0x50,0x0a,0x1b,0x30,0x17,0x0b,0xf3,0x45,0xfd,0x32,0xd9,0xbd,
+  0x61,0xda,0xbc,0x3c,0xa4,0x4c,0xb7,0xa4,0xdc,0x6c,0xfc,0x95,0x17,0x23,0x3d,0xb1,
+  0xad,0xc4,0xd7,0x2d,0x0e,0xf9,0x3b,0xc1,0xe5,0x9b,0x1c,0x2a,0x5e,0x06,0xfe,0x7c,
+  0xd5,0x40,0x30,0x29,0x2d,0x94,0x2f,0x60,0x58,0x1b,0xf9,0x18,0xf7,0x2a,0xb3,0xd0,
+  0x1f,0x0b,0x2a,0x28,0x28,0x5f,0x99,0xca,0xe1,0xa9,0x89,0x6b,0x5d,0xf9,0x87,0xc3,
+  0xe4,0x62,0xa0,0x9e,0x70,0x48,0x25,0xd6,0x0f,0x14,0x0c,0x0b,0x2c,0xc9,0x10,0x79,
+  0x26,0x2f,0x91,0x2b,0x41,0x40,0x5b,0x2f,0x97,0x33,0xef,0x7d,0x80,0xe5,0x1f,0x5e,
+  0xaa,0xa8,0xbf,0x95,0x57,0xac,0x88,0x6e,0xfc,0x45,0x9e,0x9f,0x27,0xb5,0x18,0xa7,
+  0xb4,0x7f,0x96,0xf3,0x7b,0x99,0x71,0xb3,0x9c,0xdf,0x07,0x5b,0xc0,0xa9,0xe6,0x9b,
+  0xb1,0xe5,0x6e,0xde,0xe2,0x18,0x26,0x8e,0x31,0x6e,0xf6,0xe6,0x3f,0x2f,0x59,0x63,
+  0xcc,0x19,0xfc,0x77,0x3d,0xdf,0x94,0x73,0xb7,0x70,0x97,0xf1,0x15,0xed,0xaa,0x3e,
+  0xc7,0x10,0xee,0x16,0x16,0xba,0x5b,0xb4,0x4c,0x97,0x3c,0x43,0xf0,0xa2,0xf1,0x82,
+  0xdd,0x62,0xce,0x60,0xbf,0x8b,0x50,0x51,0xd0,0x69,0x54,0x2f,0x52,0xe4,0xb8,0x6d,
+  0x3c,0x08,0xc6,0x62,0xde,0x52,0xc6,0x5a,0x72,0x0e,0x62,0x57,0x0c,0x5b,0xe0,0xf5,
+  0x7a,0x57,0xac,0xa8,0x94,0x8d,0x61,0x2d,0x54,0xe7,0xdf,0x87,0x12,0x21,0x46,0x16,
+  0x93,0x2f,0x93,0x1c,0xca,0x8c,0xab,0x49,0x4e,0xbc,0x10,0x8c,0xd8,0xd5,0x99,0x96,
+  0x07,0xda,0x85,0x25,0xbc,0x8b,0x96,0xb5,0x28,0xdc,0xb0,0x07,0xdb,0xd7,0x79,0x3e,
+  0x9a,0x73,0x8f,0x70,0x17,0xfd,0x33,0xfd,0xaa,0x7e,0x66,0x7c,0x05,0x8c,0x5b,0xef,
+  0x29,0x5c,0x68,0x7e,0x45,0x2f,0xb1,0x5b,0xd0,0x68,0x05,0xa3,0x02,0xba,0xc2,0xc2,
+  0x5d,0xdb,0xbe,0xc2,0x06,0x17,0xde,0x95,0xf8,0x8a,0x5e,0x68,0x16,0xf2,0xdf,0xf5,
+  0xbc,0x01,0x1b,0x50,0x29,0xc9,0x25,0x02,0x75,0x19,0x9a,0x42,0x72,0x05,0xd2,0xce,
+  0x5b,0x0a,0x85,0x38,0x1a,0x06,0x76,0xc1,0xd3,0x0e,0x2d,0x9a,0xc0,0xba,0x74,0x6c,
+  0xb1,0xe7,0x39,0x2a,0xfb,0x05,0x2c,0x45,0xd0,0x3a,0x98,0xd1,0xc0,0x8d,0x52,0x30,
+  0x0a,0xc1,0x68,0x75,0x5a,0x94,0x74,0x43,0x08,0x8c,0xa5,0x38,0x26,0xa4,0xad,0xe5,
+  0x83,0x2b,0x34,0xe7,0x3a,0xb7,0xe7,0x34,0xb4,0x36,0x27,0x4b,0x02,0x57,0x79,0x98,
+  0x71,0x27,0x37,0xee,0x4c,0x83,0xf1,0x05,0xde,0x32,0xfb,0xaa,0xdb,0x73,0x1a,0xed,
+  0xae,0x3b,0x32,0x63,0x9a,0xd3,0xd0,0x45,0xec,0xf5,0xf2,0x0a,0x5f,0x22,0x77,0x9a,
+  0x57,0x85,0x72,0x16,0x66,0x8c,0xaf,0x18,0x60,0xb4,0xe4,0xdc,0x05,0x2d,0x7f,0x8e,
+  0x06,0xb4,0x50,0xd6,0xf2,0x3f,0x84,0xaf,0x10,0x77,0x57,0x28,0xc7,0x70,0xd6,0x0b,
+  0x1e,0x34,0x8d,0xc8,0x44,0xc8,0x18,0xb2,0x65,0xc8,0xbc,0x45,0xe3,0x5d,0x46,0x66,
+  0x8c,0xd3,0xa2,0x09,0x82,0xbd,0x5e,0x31,0x80,0x62,0x78,0x5b,0x28,0xba,0x6d,0x94,
+  0x91,0xb1,0x2d,0xd9,0x86,0xc6,0x0d,0x83,0xb5,0x08,0x33,0xec,0xf5,0xca,0x89,0x09,
+  0x78,0xff,0x5c,0x45,0x33,0xc6,0x32,0x34,0x8c,0xab,0x12,0xd0,0xf2,0x17,0x68,0xb8,
+  0x5a,0xb2,0xbb,0x60,0xb0,0x35,0xcf,0x7d,0x86,0x14,0x23,0x27,0x59,0x41,0xff,0xc7,
+  0x1b,0xa6,0x84,0x77,0x1d,0x6b,0xd1,0xc9,0xa9,0xec,0x31,0xf6,0x7a,0x35,0xc8,0xa1,
+  0x56,0xaf,0xde,0xa8,0x68,0x07,0x27,0x30,0x74,0x66,0x14,0xc6,0xe5,0x10,0xe5,0x2d,
+  0x25,0x7a,0x6b,0x69,0xd6,0x18,0xfb,0xf9,0x6a,0x25,0xf0,0xa2,0xf6,0x62,0xe5,0x9b,
+  0xf9,0xf1,0x06,0xcd,0xb4,0xe8,0x30,0x79,0x59,0x63,0xec,0xf5,0x12,0x85,0x10,0x5d,
+  0xa8,0x17,0x2b,0xf2,0xc1,0x09,0x0c,0xfd,0xe3,0xbb,0x2c,0xc3,0xbe,0xce,0xf3,0x0d,
+  0x39,0xb1,0xd6,0xc5,0xfa,0x97,0x95,0xab,0xe2,0xff,0x09,0xa3,0x6d,0x5c,0x0b,0xb5,
+  0xd7,0xab,0xe1,0x8f,0xac,0x30,0x37,0x48,0xa6,0x85,0xe2,0xef,0xca,0x1a,0xe3,0x9a,
+  0xe7,0x18,0x4c,0xdd,0x7c,0x9c,0x4c,0xcb,0xd8,0x20,0x2f,0x6b,0xbd,0x86,0x1b,0xac,
+  0x25,0x0a,0x5d,0xac,0x25,0x5a,0xf8,0x08,0xb4,0x30,0x63,0x83,0xdd,0xe2,0x5c,0x27,
+  0x96,0xb3,0x58,0xf8,0x32,0xf9,0x73,0x7a,0xd5,0x9f,0x60,0xdc,0x4a,0xaf,0x32,0xac,
+  0xf7,0x06,0xcd,0x15,0xe6,0xd1,0xe6,0x58,0x49,0x69,0x4e,0x96,0x71,0x27,0x1a,0xf3,
+  0xed,0x96,0xf9,0xc4,0xe9,0xfa,0xe2,0x98,0xc1,0x24,0xb3,0x5e,0x04,0xde,0x2a,0x9a,
+  0x22,0x3b,0x46,0x91,0x20,0x53,0x01,0x0c,0x52,0xc4,0x5b,0xa2,0x44,0x84,0x96,0x79,
+  0x60,0xc8,0x45,0xb0,0xd0,0xdc,0xb0,0x5b,0xec,0xeb,0x3c,0x3f,0x5f,0xfa,0x22,0x3d,
+  0x11,0xbb,0xa9,0x34,0x3f,0xcb,0x68,0x07,0x43,0x99,0x2f,0x15,0xb2,0x16,0x05,0x5b,
+  0xee,0x64,0x5d,0x22,0x6f,0xf1,0x3a,0x83,0x0d,0x7b,0xbd,0xe6,0xe7,0xdc,0xdd,0x7a,
+  0x57,0xec,0x73,0xa5,0xb8,0x05,0x80,0xf1,0x95,0xd2,0xab,0x0e,0xe6,0xb4,0x70,0xe3,
+  0x85,0x9c,0x25,0xb6,0x71,0x77,0xeb,0x66,0xde,0x05,0x63,0xf4,0xaf,0x94,0x96,0xbc,
+  0x60,0x8f,0xb1,0xf7,0x9d,0x5b,0xe7,0x4b,0x77,0xd3,0x53,0xb1,0x9b,0x4b,0xf3,0x5f,
+  0xc8,0x18,0x2d,0x68,0x28,0x76,0x8b,0xf2,0x19,0xa7,0xeb,0xa0,0x65,0xe4,0x39,0x2d,
+  0x66,0xa1,0x7d,0x1d,0xfb,0x6b,0xbc,0xf0,0x27,0x19,0xf6,0x7b,0x9e,0x8c,0xdf,0xbf,
+  0xfe,0xb7,0x0c,0x4a,0xac,0x4f,0xae,0xb0,0x84,0xc2,0x6e,0x55,0x9a,0xf3,0xe0,0xff,
+  0x86,0x21,0x38,0x2d,0xf6,0x75,0x6e,0x35,0x72,0x5a,0x84,0xbb,0xc8,0x57,0xc8,0x55,
+  0xe6,0x78,0x43,0xe6,0x46,0xce,0x04,0x5d,0x8e,0x61,0xfd,0xae,0x5b,0x1b,0x48,0x8c,
+  0xc2,0x4e,0xa4,0xe0,0x26,0xf5,0x31,0x46,0xa1,0xd3,0xd2,0x36,0x6e,0x0c,0xb5,0xe7,
+  0xb9,0x01,0x5e,0x56,0x8a,0xde,0xa0,0x68,0xf1,0x3f,0xc9,0xc8,0x5c,0x27,0xc7,0x68,
+  0x6d,0xd6,0xef,0x54,0xae,0x12,0x1d,0x43,0x1e,0xd7,0x62,0x1b,0xd2,0xb8,0x16,0x62,
+  0xaf,0x97,0x24,0x34,0x9b,0x77,0x86,0xae,0xf2,0xe6,0x34,0x66,0x0c,0xcd,0x34,0xc6,
+  0xb4,0x38,0x06,0x01,0xa3,0x90,0xb7,0x34,0x61,0x8b,0x61,0xaf,0x97,0x42,0x1a,0x88,
+  0x46,0x65,0x5d,0x70,0x19,0x45,0xe8,0x80,0x66,0xb5,0x38,0x86,0x08,0x86,0xc0,0x5b,
+  0x64,0x6c,0xb1,0x2f,0x73,0x6b,0x83,0x48,0x28,0xd5,0x75,0x45,0x11,0x33,0x86,0x36,
+  0xae,0x25,0xcb,0x28,0xe3,0x46,0x3b,0xb6,0xd8,0xbf,0xeb,0xd6,0x89,0xf6,0xaf,0x18,
+  0x89,0x8e,0x6d,0xb1,0x0d,0x7d,0x6c,0x8b,0x35,0xcf,0xcf,0xff,0x67,0xf6,0xaf,0x3f,
+  0x66,0xd8,0x3f,0x8c,0xc8,0x21,0xc1,0x4b,0x1a,0x89,0x66,0xfe,0x69,0x86,0x73,0x9d,
+  0x71,0xbb,0xd5,0x00,0x18,0xf9,0x68,0xbc,0x40,0x66,0x12,0xaf,0x21,0x19,0xd0,0x72,
+  0x13,0xb6,0x68,0xb6,0xd1,0x4c,0x4e,0xe0,0x98,0x18,0xfb,0x2b,0xeb,0x93,0x23,0xcc,
+  0x30,0x16,0x36,0x17,0x97,0xc8,0xcf,0x4f,0x6c,0xb4,0x4c,0xd0,0x35,0x39,0xd3,0xe2,
+  0x5c,0xa7,0x3c,0x67,0x79,0xef,0x5f,0x86,0xbe,0xbc,0xf6,0xaa,0xc7,0xc6,0x19,0xa7,
+  0xb9,0xd1,0x61,0xb7,0x6c,0x06,0xe3,0xc6,0xd6,0xec,0x31,0x99,0xf9,0x61,0x5b,0xad,
+  0x48,0xf8,0xde,0x84,0x46,0x02,0x8c,0x3c,0xde,0x52,0x41,0x14,0x43,0xc4,0xdf,0x35,
+  0xd5,0xc8,0xe3,0x5d,0x15,0xf0,0xbb,0xc4,0x66,0xb2,0x11,0xc7,0x18,0x6c,0x8c,0x7d,
+  0x1f,0x36,0x2d,0x2d,0x2c,0x6d,0x9f,0x5f,0x56,0xd8,0x31,0xde,0x90,0xc1,0xa0,0xf3,
+  0xcb,0xb4,0xfe,0xa6,0xa5,0x02,0xb4,0xe8,0x85,0xab,0x9b,0xfc,0x82,0x17,0x0d,0xbb,
+  0xab,0x30,0xf3,0x7d,0x6e,0x6d,0x2e,0xbc,0x53,0xfe,0x73,0xe1,0x2a,0x23,0xcb,0x20,
+  0x7f,0x2e,0x94,0x18,0x39,0xac,0x85,0x94,0x40,0x8b,0x00,0x2d,0x1a,0x74,0x15,0x16,
+  0x36,0x41,0xcb,0x55,0xf3,0x72,0xd8,0x18,0x72,0x55,0xe6,0xb9,0x28,0x6b,0x50,0x9a,
+  0xe3,0x25,0xfa,0x03,0x19,0x43,0xc0,0xe7,0x98,0xb7,0x10,0xbb,0x85,0x34,0x53,0x7b,
+  0x0c,0x18,0x39,0x38,0x86,0xb5,0x38,0x5f,0xc7,0x23,0x88,0xd4,0x48,0x6a,0x01,0xd9,
+  0x6d,0x98,0xe3,0x5a,0x3e,0xce,0x70,0xae,0xe3,0x95,0xbe,0x44,0x4e,0x98,0x37,0x85,
+  0xf2,0x17,0xfe,0x49,0x46,0xe6,0x77,0x39,0x70,0x60,0x8c,0x51,0x31,0xce,0xd0,0xaf,
+  0x3a,0x34,0x6e,0x70,0xe6,0xfe,0x29,0x8d,0xbe,0x50,0x34,0xa3,0x7d,0xed,0x92,0x8c,
+  0x41,0x8c,0x83,0x45,0x21,0xd9,0xbb,0x44,0x52,0xa2,0x7d,0xda,0x8c,0x76,0xaf,0x50,
+  0xae,0x19,0x26,0xb6,0x94,0x49,0xc4,0xe8,0x43,0x43,0x90,0x48,0xf4,0xa0,0x16,0x92,
+  0xd7,0x96,0x39,0xbf,0xab,0xfe,0xca,0xa2,0x2b,0xff,0x76,0xe5,0xdc,0x95,0x4b,0x7f,
+  0x9a,0x41,0xfe,0xbb,0x3f,0xc1,0xdf,0xa8,0xb3,0x0e,0xbe,0x98,0xda,0xb1,0x22,0x63,
+  0xbc,0xb6,0x60,0xd6,0xc1,0xd7,0xce,0xed,0x58,0x51,0x7f,0x41,0xbd,0xf9,0xdf,0xde,
+  0x4d,0xed,0x3a,0x13,0x7c,0x6d,0xd1,0x95,0x97,0x5f,0x3b,0x77,0xe5,0x4c,0xf0,0x37,
+  0xbe,0x67,0x0e,0xbe,0xc8,0xbe,0xcf,0x82,0x59,0xcf,0x5d,0x39,0xb7,0xeb,0x8c,0x73,
+  0x9d,0x9a,0xba,0x85,0xc7,0x8b,0x6b,0xfa,0x8e,0x9e,0xcd,0x18,0xf5,0x60,0xd4,0x9f,
+  0x3b,0x7a,0xb6,0xfe,0xe2,0xc2,0xe3,0xff,0xf6,0x61,0xdf,0x71,0x68,0x81,0x5f,0x51,
+  0x7f,0xee,0x0a,0x8c,0x59,0x04,0x63,0xd8,0x75,0x60,0xcc,0x95,0x73,0xc7,0xcf,0x3a,
+  0xd7,0x99,0x73,0xff,0x17,0x5e,0x7b,0x64,0xd7,0xe0,0xbb,0xa3,0x19,0x63,0x4a,0xf4,
+  0x17,0x60,0x3c,0x64,0xb7,0x3c,0x74,0xda,0xe9,0x2a,0x2f,0xfd,0xc2,0xab,0xc5,0x5d,
+  0x7c,0xf0,0x2f,0x58,0x4b,0xe6,0x87,0x49,0x77,0x93,0xc9,0xe4,0x86,0x92,0xbc,0xe7,
+  0x49,0x8b,0xb9,0xb9,0x79,0x92,0x17,0x8d,0x79,0x9b,0xb5,0xcf,0xc9,0xf9,0xcf,0x8b,
+  0x2d,0xc6,0xe6,0xc2,0x1b,0xe4,0x42,0x68,0x01,0xbc,0x7c,0xb5,0x9c,0xd7,0x0b,0xc6,
+  0x64,0xe8,0xca,0xeb,0x95,0xa1,0x8b,0xfc,0xad,0x7c,0x8d,0xb3,0xee,0x72,0xce,0x8c,
+  0x56,0x44,0xbe,0x39,0x36,0x28,0xfe,0xf3,0xbe,0xdc,0xbb,0x85,0x53,0xc6,0x3f,0x6b,
+  0x77,0xb6,0x0b,0x77,0xe7,0x9c,0x32,0xfe,0x4c,0xcb,0xc7,0xae,0xa8,0xf1,0x35,0xe8,
+  0x62,0x63,0xfe,0xd9,0x86,0xd2,0x8d,0x5a,0xe6,0x7d,0x28,0x0a,0x31,0x1a,0x4d,0xa2,
+  0xe7,0x00,0x5e,0x5c,0x94,0x00,0x16,0xce,0x02,0xce,0x68,0x94,0xb0,0x96,0x64,0xc6,
+  0xcd,0xb0,0xc7,0x88,0x4a,0x8e,0x99,0xf9,0x61,0x4b,0x00,0x45,0xe6,0x96,0x0a,0xf1,
+  0x92,0x25,0x00,0x39,0xe7,0x13,0xa1,0x5d,0x68,0x19,0x83,0x58,0xdb,0x65,0x34,0xae,
+  0x82,0x16,0x39,0x26,0x64,0xba,0xc4,0x49,0xa4,0x95,0xda,0x57,0x51,0x9a,0xee,0x29,
+  0x9c,0xdc,0xfe,0xb9,0x90,0xdc,0x2f,0xdf,0x23,0x4c,0xa6,0xb7,0xea,0x85,0xdc,0xf8,
+  0x9c,0x5e,0x78,0x98,0xdc,0x61,0x19,0xd0,0x52,0x62,0x7e,0xce,0xe9,0x0a,0x70,0xa3,
+  0x7d,0x92,0x2e,0xb8,0xbe,0xcf,0x52,0xf6,0x8f,0x16,0xd2,0xf1,0xc0,0x59,0x76,0x5a,
+  0x0c,0x6e,0x10,0x12,0x93,0x4b,0xe1,0xc5,0x68,0x8d,0x99,0x4f,0x32,0xef,0x31,0x45,
+  0xae,0x40,0xe4,0x6b,0x68,0x09,0xf9,0x06,0x21,0x8f,0x34,0xb4,0x68,0x1b,0x00,0x0b,
+  0x83,0xa1,0x43,0x4b,0x05,0x47,0xd0,0x09,0x70,0x8a,0x59,0x8b,0x26,0xcb,0x60,0xcc,
+  0x8f,0x41,0x0b,0x8c,0xa1,0x0d,0x31,0xcd,0xb9,0xce,0x74,0x39,0x4a,0x8b,0xf4,0xa6,
+  0x4d,0x85,0x31,0x72,0x7b,0x6f,0x91,0x2e,0x3f,0x55,0x58,0x4e,0x16,0x40,0x8b,0xbc,
+  0xbd,0xd0,0x2f,0x47,0xcd,0xa2,0x2d,0x4d,0xdb,0x05,0xbf,0x76,0x7b,0x6b,0x51,0x4a,
+  0x7e,0xea,0x8b,0x7e,0x82,0x83,0x4b,0xb6,0x17,0x96,0xcb,0x0b,0x5a,0x8b,0x92,0x4d,
+  0xdb,0x0b,0xed,0x6f,0x43,0xf3,0xc9,0x97,0x48,0x89,0x99,0x13,0x22,0x05,0xe4,0x4b,
+  0x54,0x46,0x63,0x21,0x29,0xa6,0xc4,0x2c,0x0c,0x09,0x0b,0x61,0x13,0x83,0x96,0x99,
+  0x60,0xc0,0x18,0x22,0x68,0x64,0xa1,0x3d,0xd8,0x0b,0x63,0xd0,0x10,0xf8,0xb1,0x16,
+  0x51,0x60,0x9e,0x9a,0xe0,0x97,0xca,0x2d,0x64,0x13,0xf9,0x6b,0x92,0xd3,0x2a,0x2f,
+  0x36,0x9a,0xc9,0x0c,0x98,0x09,0x83,0xcc,0x83,0x9f,0x41,0xf0,0x3f,0x58,0xa2,0x79,
+  0x72,0xe1,0xbc,0x79,0x04,0xc0,0x25,0x4e,0x09,0xe2,0x69,0x59,0x23,0x85,0x00,0xac,
+  0x05,0x7e,0x5c,0x07,0xd7,0x31,0xd0,0x75,0x20,0xba,0x8e,0xd3,0x47,0xda,0x91,0xd5,
+  0x00,0x13,0x2a,0xa9,0x80,0xa8,0x39,0x17,0x5b,0x10,0x86,0xe3,0x06,0x43,0xcb,0x74,
+  0x85,0xed,0x34,0x82,0x1f,0xf7,0xa7,0x90,0xb5,0x51,0x39,0xd7,0x81,0x5b,0x62,0x13,
+  0xfc,0x33,0x3a,0x15,0xf1,0xde,0xf8,0x1b,0xf8,0xf7,0x72,0x63,0xcc,0x2b,0x2a,0x44,
+  0xff,0x86,0x2f,0x8a,0xc8,0x6f,0x9b,0x42,0xea,0x89,0x89,0x9b,0xd8,0x18,0x76,0x23,
+  0x61,0x17,0xbf,0x8e,0x26,0x18,0x22,0xae,0xfb,0x34,0x92,0xd7,0x01,0x4b,0xb9,0x89,
+  0xce,0x27,0x79,0x70,0x1d,0xb8,0x72,0x2e,0x18,0x62,0x8c,0x75,0x5d,0xc3,0xba,0xb0,
+  0x05,0xcf,0x37,0xe0,0xa6,0x25,0xd7,0x50,0x05,0x5b,0xfc,0x24,0xcf,0xe2,0xb9,0x35,
+  0x6e,0xb5,0xf1,0xb2,0x01,0x10,0xf8,0x01,0x17,0x5e,0x9e,0x07,0x06,0x09,0xd1,0xb5,
+  0x56,0xcb,0x03,0xde,0x2d,0x5f,0xe3,0x5d,0xd8,0x52,0x7a,0x30,0x17,0xc7,0x34,0x28,
+  0x85,0x94,0xfb,0x51,0x06,0xb1,0xfc,0x0d,0x3d,0xe3,0x6f,0xf4,0xa3,0x41,0x99,0x11,
+  0x16,0xc6,0x20,0x68,0x98,0x7a,0x7c,0x39,0xf3,0x31,0x24,0xb3,0x2f,0xe3,0x14,0x86,
+  0x7a,0xe1,0x05,0xee,0x25,0xcf,0x21,0x48,0x0f,0x49,0x0a,0x39,0x82,0xdf,0x27,0x85,
+  0x06,0xd6,0x18,0xeb,0x92,0x62,0x34,0xca,0x1a,0xef,0x7a,0x0e,0x25,0x64,0x42,0x8d,
+  0xd8,0x85,0x88,0x1e,0xf0,0xa9,0x69,0xff,0x2e,0x98,0xe7,0x5e,0x78,0x3c,0xbd,0x39,
+  0x6d,0x88,0x46,0x53,0x57,0x03,0x28,0x96,0x5b,0x5a,0x17,0x83,0x51,0xd8,0x46,0x74,
+  0xec,0x02,0xf7,0x1b,0xd0,0x71,0x69,0xe8,0x73,0xd0,0x02,0x83,0x17,0x87,0x00,0xba,
+  0xb6,0x01,0x6e,0x62,0x60,0xd6,0xfe,0x5d,0x02,0xe2,0x65,0xbc,0x72,0x61,0x5c,0x0b,
+  0x01,0x04,0x96,0x10,0x0b,0xa3,0xaf,0x3e,0x1f,0x0c,0xd9,0x4f,0x27,0x73,0x74,0x8c,
+  0x5d,0xb9,0x68,0x84,0xa9,0x97,0x8f,0x01,0xbc,0xec,0xfa,0x5d,0xcd,0x42,0x83,0xbc,
+  0x14,0x66,0x6c,0x3e,0xba,0xe8,0xa1,0xd6,0xd2,0x64,0x2e,0x4e,0xa6,0xbf,0x55,0x49,
+  0x36,0x20,0x82,0x06,0x43,0x9f,0x1f,0x10,0x18,0x94,0xe6,0x2d,0x61,0x76,0x2e,0x91,
+  0x01,0xd7,0x34,0xf3,0xbb,0x9a,0x65,0x99,0xdc,0x8a,0x61,0x47,0x4d,0x80,0x9b,0x9f,
+  0x14,0xe2,0x11,0x4f,0x09,0xcc,0x5c,0xa1,0x21,0xe3,0xcd,0x7e,0x2b,0x11,0x0c,0xa7,
+  0xab,0x84,0x9f,0x10,0x59,0x2d,0xb7,0x92,0xc2,0x06,0xfe,0xbb,0xa2,0x70,0x57,0xcc,
+  0xa3,0x1a,0xbc,0x0d,0x04,0x6e,0x34,0xa1,0xd1,0x68,0xb5,0x00,0x3a,0x46,0xa3,0x90,
+  0x19,0x69,0x67,0x8c,0xdb,0x20,0x96,0x8e,0xfc,0x3c,0x84,0xc9,0x51,0x84,0xc9,0x71,
+  0x81,0xb4,0x67,0x01,0xe7,0x26,0x84,0x78,0x86,0xd5,0x45,0x8d,0xb2,0x66,0xde,0xc5,
+  0x06,0x8b,0x39,0x16,0xb8,0x26,0xf6,0xef,0xb2,0x91,0xef,0x67,0xb2,0xf0,0x32,0xc3,
+  0x9e,0xf3,0x73,0xef,0x66,0x30,0xd9,0x9b,0x2b,0x62,0xd7,0x0c,0x77,0x97,0x83,0x97,
+  0x2d,0x7f,0x5e,0x98,0x4f,0xee,0x69,0xdd,0xac,0x4f,0x9a,0x2d,0x1c,0xcb,0xbd,0xbb,
+  0x75,0x72,0xec,0x6f,0x4b,0x0b,0x5f,0x90,0xef,0xa6,0xcc,0x38,0x26,0x63,0xcb,0xa4,
+  0xd2,0xa9,0x2f,0xe4,0xde,0x1d,0x9f,0x9c,0xfe,0x32,0x74,0xc1,0x98,0xcd,0x69,0x3e,
+  0xa6,0x75,0xb2,0xfe,0xb9,0xd2,0x42,0xeb,0xfe,0x89,0x0a,0xf3,0xc5,0x7f,0x84,0xbf,
+  0xba,0x01,0x20,0x30,0xb9,0x9b,0x6e,0x8e,0xfd,0x59,0xa9,0x80,0xc6,0x5d,0x70,0x9d,
+  0xbc,0x63,0xe4,0x6e,0xab,0x4b,0xc4,0xae,0x49,0x00,0xa5,0x05,0xf8,0xf3,0xf4,0x24,
+  0x68,0xc9,0xc1,0x16,0x18,0x63,0x5d,0xa7,0x99,0xe1,0x65,0x2f,0x20,0x5f,0xf2,0x02,
+  0x6e,0x64,0x30,0xf8,0xaa,0x17,0x72,0xcb,0xe8,0xc2,0xd8,0xd7,0xc0,0x20,0x33,0x5a,
+  0xd7,0x42,0xd7,0x9f,0xa3,0x71,0xd7,0x92,0xaf,0x95,0xde,0x89,0x5f,0xc3,0x1b,0xfb,
+  0x12,0xb4,0xc8,0x38,0xf8,0x9f,0x01,0xd1,0xdb,0xcf,0x57,0x91,0x30,0x8d,0xfe,0x0f,
+  0xbd,0x28,0x4a,0x36,0x08,0xcb,0x60,0x0e,0xbf,0x14,0x95,0x37,0x08,0x15,0x0f,0xfc,
+  0x45,0x52,0x54,0xe4,0x0d,0xa4,0x02,0x6e,0x3f,0xb6,0x6d,0xdd,0x4b,0x6f,0x4b,0x0a,
+  0xd1,0x9c,0xb8,0x10,0x6e,0xbf,0x4b,0xbf,0x1a,0xc7,0x40,0x8b,0x0b,0x2f,0x1b,0xb0,
+  0xee,0x5f,0xeb,0x2d,0x8d,0xe5,0x96,0x92,0x07,0x73,0x96,0xd0,0xd2,0xf4,0x7c,0xc0,
+  0xc2,0xe4,0x6b,0x66,0x69,0x5a,0x44,0xa3,0xdc,0x54,0x62,0xb9,0xb3,0x85,0x5c,0x19,
+  0xbb,0x10,0x26,0xcb,0x5f,0xa3,0xa5,0xb1,0x2f,0x83,0x81,0x83,0xe1,0xaf,0x04,0xfb,
+  0x3d,0xdf,0x14,0x93,0xef,0x9b,0x57,0x40,0x1a,0x93,0x64,0xb9,0xbc,0x52,0x98,0x42,
+  0x3e,0x47,0x0b,0xd3,0x25,0x2b,0x85,0x02,0xf2,0x15,0x5a,0xf8,0x16,0x99,0x2d,0x5c,
+  0x0d,0x2d,0x70,0xeb,0x40,0x17,0xc5,0x2e,0x30,0xbe,0x4a,0xe1,0xf6,0xc2,0x31,0x53,
+  0x48,0x03,0xb5,0xcf,0x7b,0xa3,0xc2,0x1d,0x64,0x19,0xcd,0xd3,0xc5,0xe5,0xda,0xf7,
+  0xc1,0x00,0x08,0x1c,0x15,0x36,0x90,0x65,0xc8,0x62,0xa6,0x08,0x1b,0xe4,0x0a,0x06,
+  0x8a,0xe1,0x69,0x5a,0x46,0xaf,0x49,0xca,0x51,0x84,0xc9,0xa6,0x92,0xcc,0x85,0x49,
+  0xc0,0x16,0x78,0xf4,0xec,0xef,0x03,0xcf,0xa9,0xac,0xdb,0xe7,0x51,0x2e,0x2c,0x5c,
+  0xca,0x9f,0xb8,0x18,0x6b,0x81,0x2e,0x0c,0xfa,0x42,0x97,0x58,0xa2,0xb7,0x6a,0x7a,
+  0x43,0x20,0x33,0xd8,0x79,0xbe,0x1a,0x64,0x03,0xfc,0xe9,0x5b,0xbd,0x85,0x0d,0xc4,
+  0x80,0x31,0xb2,0x52,0x28,0x82,0x51,0x82,0x86,0x24,0x37,0x53,0x4d,0x6f,0xb2,0xba,
+  0xca,0xac,0x2e,0x0d,0xe0,0xad,0x35,0x98,0x28,0x85,0xc4,0x5e,0x2f,0x09,0xb0,0x98,
+  0x37,0x24,0x28,0x42,0x23,0xba,0xec,0xa1,0x1c,0x34,0xee,0x40,0x97,0xdd,0xcb,0x9d,
+  0xf8,0x10,0x18,0xd0,0x65,0x32,0x27,0x1e,0xba,0x4c,0x68,0x09,0x60,0x17,0x18,0x82,
+  0x57,0x30,0xac,0xef,0x33,0x4f,0xb1,0xce,0x76,0x71,0xe3,0x25,0xa5,0xb0,0x45,0xcc,
+  0x53,0xe4,0x06,0x6c,0x03,0x2c,0x2c,0x37,0x08,0x00,0x93,0x09,0xc7,0xcb,0xeb,0x9b,
+  0xa0,0x0b,0x8f,0x79,0x61,0x57,0x9b,0xd7,0xc1,0xc6,0x08,0x0e,0x5e,0x86,0xdf,0x25,
+  0x16,0xd1,0xf6,0x64,0x99,0x52,0xca,0xb1,0x30,0x51,0x14,0x49,0xd4,0x71,0x43,0x03,
+  0x50,0x4c,0x18,0x4c,0x0e,0xd8,0x86,0x85,0x97,0x93,0xcc,0xd0,0xc1,0x28,0x73,0xf0,
+  0xb2,0x21,0xd8,0xfb,0x17,0xee,0x4d,0x42,0xa9,0x36,0x1f,0xf6,0x14,0x99,0x1b,0xf6,
+  0x26,0x25,0x73,0xb7,0xa7,0x30,0x97,0x6d,0x64,0xf3,0xc6,0xec,0x5f,0xf6,0x7a,0x19,
+  0xe2,0x32,0xf2,0x19,0x92,0x6b,0x28,0x09,0x72,0x2f,0x79,0x94,0x4c,0x02,0x9f,0x44,
+  0xac,0x20,0xd7,0xe0,0x6e,0x95,0x60,0x1b,0x66,0xae,0x71,0x1b,0xd5,0x70,0xdb,0x16,
+  0x0d,0x68,0xb9,0x57,0xf8,0x0c,0x99,0x64,0x5c,0x83,0x5d,0x8f,0xc2,0x05,0xf3,0x9c,
+  0xf5,0x8a,0xc9,0xb5,0xc2,0xb5,0xf8,0xe6,0x4a,0xca,0xcb,0x85,0x02,0x61,0x3e,0x25,
+  0x69,0x71,0x3a,0xdc,0x87,0x0d,0xb4,0x39,0x2d,0x07,0x84,0x35,0x44,0x4a,0xc2,0x7d,
+  0xb8,0x3c,0xa7,0xa0,0x75,0x29,0xde,0x7e,0xcb,0x61,0xf0,0x7c,0xe8,0xca,0x0d,0xc0,
+  0x18,0xf8,0x2b,0xeb,0x3e,0x6c,0x86,0x97,0xe4,0x0c,0x4d,0xd1,0x00,0x0b,0xaf,0x25,
+  0x65,0x86,0x57,0x13,0x65,0xad,0x97,0xe8,0xcc,0x20,0x7d,0x06,0x26,0x0a,0x34,0x4e,
+  0x26,0xac,0x85,0x42,0x0b,0x1a,0x0a,0xb1,0x0c,0xa4,0x45,0x73,0xf6,0x1d,0x92,0x43,
+  0x6e,0x9a,0x97,0xdf,0x2c,0xb5,0x90,0xef,0xca,0x33,0x69,0x7e,0x4b,0xa3,0x66,0x34,
+  0x21,0xb8,0xc6,0xa8,0xe7,0x2f,0xe1,0x1f,0x51,0x9a,0xa5,0x3b,0xc9,0xf3,0xf2,0x0c,
+  0xc3,0x6b,0xc0,0x3f,0xfa,0xe7,0xf2,0x4d,0x80,0x04,0x1b,0x9b,0xb5,0x2f,0xc3,0x3f,
+  0x9a,0xdf,0xdc,0x58,0x42,0x9c,0x7d,0xb9,0x51,0x5e,0xd2,0x5b,0x1a,0x9a,0x3f,0x59,
+  0x58,0x85,0x1b,0x59,0xcb,0x7c,0x2f,0xdb,0xa4,0x4a,0x43,0xb9,0x60,0x10,0x34,0x9c,
+  0x16,0xb8,0x21,0x25,0x39,0x66,0xb2,0x96,0x49,0x6c,0xd7,0x9b,0xe4,0xda,0xbf,0x0c,
+  0x4e,0xc0,0x44,0xb4,0xd6,0x6c,0xe0,0xdc,0x00,0x3e,0x8b,0xac,0xbb,0x3d,0x14,0x14,
+  0xba,0xb3,0x06,0xf3,0x16,0x70,0x2a,0x9c,0xdf,0x25,0x44,0x9b,0x96,0x14,0x96,0xca,
+  0xf3,0x85,0xf5,0xdc,0x97,0x60,0x78,0x39,0x56,0x58,0xfa,0x00,0x62,0x61,0x0e,0x9c,
+  0x05,0x68,0x69,0x28,0x64,0x78,0x79,0xad,0x1c,0xd3,0xf0,0xdc,0x95,0xe3,0x65,0xb9,
+  0xa1,0xcc,0xf6,0xc3,0x61,0xff,0x6a,0x6a,0xd6,0x4a,0xe4,0x5b,0x73,0x60,0xdb,0x6a,
+  0x2e,0x2c,0x91,0x73,0x84,0x42,0xc3,0x40,0xe3,0x56,0x30,0x78,0x97,0xf0,0x12,0xb4,
+  0x08,0x25,0x39,0x39,0x85,0xd8,0xa5,0xe1,0x18,0x81,0xb5,0xc8,0x82,0xa0,0x19,0xf6,
+  0xf3,0xa5,0xc0,0x0a,0x94,0xc4,0x73,0xc8,0x03,0xf0,0x40,0x13,0xed,0x41,0x3c,0x2c,
+  0x0a,0x35,0x60,0x8b,0xde,0x4a,0x62,0x77,0xf0,0xa7,0x3f,0x1a,0x6b,0x60,0xa2,0x39,
+  0xec,0x11,0x2f,0x11,0x73,0x74,0x21,0xca,0x5e,0x0c,0x38,0xc6,0xfa,0x08,0x80,0x7c,
+  0x3b,0x48,0x12,0x89,0x26,0xcb,0x6c,0x2c,0x5c,0x26,0xb6,0x62,0x0b,0x82,0xe2,0x56,
+  0x6c,0x21,0x1e,0x22,0x52,0x92,0x6c,0x06,0xa3,0xd0,0x1e,0x93,0x83,0x06,0x09,0x64,
+  0xf6,0xaf,0xcf,0x03,0xf2,0x6d,0x1f,0x28,0x9b,0xb9,0x16,0x8c,0x28,0x40,0xe0,0x99,
+  0x0f,0x7c,0x5e,0xf8,0x92,0xd2,0x6e,0x96,0xcd,0xcc,0xff,0xbc,0x28,0x18,0xe6,0xc0,
+  0x55,0x21,0xe5,0xf3,0x52,0xb1,0xd1,0x07,0x5d,0xde,0xcf,0x4b,0x5f,0x6c,0x6a,0x7f,
+  0x69,0xea,0x4c,0x25,0xbf,0xf8,0x4b,0xc6,0x09,0xf8,0x2b,0x7b,0xff,0x82,0x79,0x06,
+  0x0f,0x7f,0x33,0x3a,0xff,0xfd,0xb9,0xe8,0xf3,0xff,0xad,0x0b,0x17,0xf4,0x4f,0x6a,
+  0x01,0x50,0xfc,0x39,0x5d,0xe8,0x9f,0x74,0x0f,0xb9,0x2b,0xfe,0x39,0x80,0xc9,0x62,
+  0x8b,0xb0,0x89,0xfe,0xb3,0x6b,0x8c,0x69,0xff,0xb0,0x72,0xc5,0x30,0xb5,0x50,0x3b,
+  0x7a,0x59,0x60,0xcc,0x90,0xd7,0x0a,0x88,0x97,0x11,0x0b,0x2f,0x01,0x50,0x6c,0x02,
+  0x82,0xf6,0x2e,0x29,0xd7,0xa2,0x07,0x39,0x5e,0xd6,0x0c,0x40,0xd0,0x2e,0xbc,0x3c,
+  0xcf,0xbe,0x0c,0xe0,0xe5,0xcf,0x5d,0x02,0xe4,0xfb,0x9d,0x1f,0xd6,0xff,0x61,0xd1,
+  0x85,0x7f,0xbb,0x72,0xef,0x95,0x67,0xb9,0x01,0xe0,0xf1,0xfa,0x3f,0x30,0x50,0xfc,
+  0x9d,0x4b,0xf5,0x68,0x5c,0xfe,0x7f,0x0b,0x2f,0x4f,0x7a,0xfa,0xe5,0x17,0x53,0xd6,
+  0xf7,0x79,0xf7,0xde,0x5d,0xcf,0x06,0x7f,0xb5,0xe0,0x3e,0x06,0x9c,0xa7,0xfc,0x6a,
+  0x01,0x22,0xe8,0x6f,0xad,0x80,0x96,0xfb,0x0f,0xbe,0x9a,0xba,0xb0,0x22,0x62,0x61,
+  0xea,0xff,0x1b,0x8c,0xfb,0xd9,0x18,0xe7,0x3a,0x35,0x75,0x9f,0x7b,0xf1,0xdf,0x6a,
+  0xfa,0xac,0xeb,0x7c,0x78,0xef,0xf1,0x67,0x6b,0x6e,0x5e,0x78,0x81,0x01,0xe7,0xeb,
+  0x6f,0x66,0x08,0xfa,0xdb,0x67,0xa1,0xe5,0x4a,0x71,0xa4,0xef,0xe2,0xd9,0x7a,0x0b,
+  0x53,0x5f,0x02,0xe3,0x0a,0x1b,0xe3,0x5c,0x67,0xce,0x14,0xa3,0xaf,0x68,0xc6,0xa0,
+  0x57,0x98,0xd3,0xf2,0x85,0xe7,0x1e,0xd9,0x25,0x9f,0xb9,0x65,0x8e,0x16,0x7d,0x6e,
+  0xc3,0x8c,0xf6,0x77,0x47,0x25,0xed,0x0b,0x2f,0x14,0xef,0x1a,0xcc,0x1f,0x85,0xae,
+  0xd7,0x1e,0x49,0xb5,0x9f,0xf9,0xe6,0x9c,0x95,0xd1,0x57,0x8b,0x6e,0x6e,0x5f,0xfb,
+  0xcd,0x39,0xa5,0x5f,0x78,0x0d,0xc7,0x9c,0x76,0xae,0x23,0xb6,0x93,0x2d,0x24,0xf0,
+  0x8f,0x1e,0x8d,0x1b,0x86,0xdb,0x58,0x15,0xca,0xb4,0x1c,0x75,0x77,0x79,0x0f,0xda,
+  0x63,0x9c,0xcb,0xb8,0x42,0x83,0xcc,0x11,0x23,0xee,0x50,0x86,0x65,0x64,0x87,0x0f,
+  0x49,0x56,0x97,0x73,0x42,0xd6,0x8e,0xcc,0x5b,0x06,0x7b,0x29,0x4c,0x64,0x74,0xb0,
+  0x54,0x2b,0x71,0x8c,0xe1,0x74,0x11,0x6b,0xe7,0xb1,0xbe,0xc6,0x3f,0xea,0x13,0x7c,
+  0x0d,0x65,0x52,0x38,0xd3,0x72,0xd4,0xd5,0xe5,0x0e,0x70,0x3a,0xbf,0x8b,0x8e,0x3b,
+  0xf8,0x03,0xe3,0xe8,0xb8,0x96,0x8f,0x33,0xf8,0xef,0xfa,0x4f,0x0f,0xff,0x63,0x57,
+  0x62,0xd7,0x61,0x34,0x77,0x1d,0xfc,0x7d,0xc9,0x0d,0x36,0xa2,0x03,0x46,0x58,0x2d,
+  0xe2,0x98,0x2e,0x85,0x0d,0x26,0x56,0x8b,0xfd,0x99,0xf8,0x1f,0x39,0xfa,0x9f,0xfd,
+  0x46,0xf6,0xf7,0x91,0x3d,0xed,0xe2,0x16,0xb2,0xdd,0x98,0xae,0xfd,0x69,0x86,0x28,
+  0xd8,0xbf,0x6b,0xfc,0x32,0xfd,0xef,0x18,0xce,0xfc,0x7c,0xd2,0xfd,0xf3,0x49,0x06,
+  0xb1,0xef,0x9f,0x49,0x21,0xe1,0x28,0xf9,0x47,0x32,0xd9,0xfc,0x93,0x8c,0x83,0xf2,
+  0x7f,0xe5,0xfb,0x4c,0x36,0xed,0x16,0x31,0x73,0x23,0xfe,0x09,0xb7,0x8d,0xe6,0xb4,
+  0x64,0x3e,0x7f,0xca,0xcd,0xa7,0x65,0xdf,0x85,0x38,0x3f,0xe6,0x1f,0x7b,0x59,0x7e,
+  0xdc,0xc7,0x9b,0xf9,0x2b,0x9e,0x1f,0x15,0xfa,0x53,0xae,0x92,0x75,0x45,0x83,0xfd,
+  0x2f,0xa4,0xff,0x57,0xaf,0x63,0x4d,0xd1,0x24,0xf3,0xbf,0x78,0x21,0x61,0xf8,0xbf,
+  0x78,0x81,0xff,0x43,0x9f,0xfa,0x2b,0x57,0xae,0x98,0x7f,0xba,0xf1,0xe9,0x75,0xfe,
+  0x5f,0xbe,0xce,0x04,0xdb,0xf1,0xff,0x8e,0xe1,0x5c,0xe7,0xbf,0xf8,0x5e,0xcd,0x5c,
+  0x67,0xdc,0x9e,0xfb,0x31,0x86,0x6b,0xa7,0x9e,0xe0,0xbd,0x4a,0xc8,0x7f,0xfe,0x5f,
+  0xb7,0x5c,0x08,0x32,0xd1,0xbe,0xfc,0xdf,0xb2,0x9b,0xfe,0xf7,0xee,0xcb,0xce,0x56,
+  0x3b,0x76,0x83,0xfe,0x24,0x23,0xeb,0xfb,0xfc,0x89,0x6f,0xfa,0xb1,0xfb,0x32,0xc1,
+  0x1d,0xf6,0xe8,0xf6,0x7f,0x9c,0x70,0xf3,0x5d,0x15,0x86,0x2e,0x97,0x31,0xf9,0x30,
+  0xeb,0x72,0x0f,0xce,0xfc,0xae,0xff,0xbe,0x7d,0x59,0xff,0xb8,0x5d,0x8f,0x4e,0xdc,
+  0x45,0xc6,0xdf,0x3f,0x0a,0xdb,0x97,0xc9,0xb8,0x3d,0x97,0xb7,0xb0,0x9b,0x64,0x7c,
+  0x97,0xc1,0xbb,0xfe,0x1b,0xf6,0xe5,0x8c,0xf1,0x5f,0xdb,0x97,0x33,0xc6,0x7f,0xf3,
+  0xfd,0x4c,0x32,0x01,0x91,0x3f,0xf1,0xc3,0xf3,0xe7,0xff,0xbb,0x3e,0x75,0x75,0xff,
+  0xc5,0x0b,0xf8,0x7c,0xff,0x2d,0xdf,0xe3,0xff,0xbb,0x9f,0xff,0xaf,0xed,0x3b,0x9f,
+  0x5e,0xe7,0x8f,0x5f,0xe7,0xbf,0xe7,0x13,0x22,0xba,0x20,0xb2,0xff,0x37,0x6d,0xf8,
+  0x3f,0x70,0xf9,0x4f,0x3f,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,0xe7,
+  0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,
+  0xe7,0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0xff,0x7f,0xf8,0x61,0x67,0x4a,0x22,0x3b,0x53,
+  0xa2,0xff,0xbf,0xfe,0x2e,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,0xe7,
+  0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,
+  0xe7,0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0x9f,0x7e,0xfe,0xcf,0x7e,0x42,0x04,0x53,0x21,
+  0x3d,0x7f,0x15,0x22,0x14,0x0b,0x2c,0xa4,0x10,0x31,0x8a,0xfe,0xfb,0xae,0xcd,0xae,
+  0x99,0x13,0x22,0x49,0x21,0xf3,0x6f,0xcd,0xbe,0x3c,0x76,0xdc,0xff,0x03,0xe6,0xeb,
+  0xaf,0xb2,0x8c,0x8c,0x02,0x00,
diff --git a/u-boot/board/esd/tasreg/tasreg.c b/u-boot/board/esd/tasreg/tasreg.c
new file mode 100644
index 0000000..d2488b8
--- /dev/null
+++ b/u-boot/board/esd/tasreg/tasreg.c
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/m5249.h>
+#include <asm/io.h>
+
+
+/* Prototypes */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here for FPGA programming (before including fpga.c) */
+#define SET_FPGA(data)  mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_PROG_ACTIVE_HIGH          /* on this platform is PROG active high!   */
+#define out32(a,b)                     /* nothing to do (gpio already configured) */
+
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int checkboard (void) {
+	ulong val;
+	uchar val8;
+
+	puts ("Board: ");
+	puts("esd TASREG");
+	val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+	printf(" (Switch=%1X)\n", val8);
+
+	/*
+	 * Set LED on
+	 */
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
+
+	return 0;
+};
+
+
+phys_size_t initdram (int board_type) {
+	unsigned long	junk = 0xa5a59696;
+
+	/*
+	 *  Note:
+	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+	 */
+
+#ifdef CONFIG_SYS_FAST_CLK
+	/*
+	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CONFIG_SYS_PLL_BYPASS
+	/*
+	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+	/*
+	 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+	/*
+	 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+	 * PM=1 (continuous page mode)
+	 */
+
+	/* RE=0 (keep auto-refresh disabled while setting up registers) */
+	mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+	/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+	mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+	/** Precharge sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+	out_be32((void *)0, junk); /* write to a memory location to init. precharge */
+	udelay(0x10); /* Allow several Precharge cycles */
+
+	/** Refresh Sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+	udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+	/** Mode Register initialization **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+	out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	uchar buf[8];
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 *
+	 */
+	buf[0] = 0x00;
+	buf[1] = 0x32;
+	buf[2] = 0x3f;
+	i2c_write(0x38, 0, 0, buf, 3);
+
+	return (0);
+}
+
+
+#if 1 /* test-only: board specific test commands */
+int i2c_probe(uchar addr);
+
+/*
+ */
+int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+
+	printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+	for (;;) {
+		i2c_probe(addr);
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	iploop,	2,	1,	do_iploop,
+	"i2c probe loop <addr>",
+	""
+);
+
+/*
+ */
+int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar buf[8];
+
+	out_be16((void *)0xe0000000, 0x4000);
+
+	udelay(5000); /* wait for 5ms */
+
+	buf[0] = 0x10;
+	buf[1] = 0x07;
+	buf[2] = 0x03;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x01;
+	buf[2] = 0x80;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x02;
+	buf[2] = 0x03;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x03;
+	buf[2] = 0x29;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x04;
+	buf[2] = 0x00;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x05;
+	buf[2] = 0x00;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x07;
+	buf[2] = 0x02;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	return 0;
+}
+U_BOOT_CMD(
+	codec,	1,	1,	do_codec,
+	"Enable codec",
+	""
+);
+
+/*
+ */
+int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	ulong instr;
+	ulong cntrl;
+	ulong data;
+	uchar buf[8];
+
+	if (argc < 5) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	instr = simple_strtol (argv[2], NULL, 16);
+	cntrl = simple_strtol (argv[3], NULL, 16);
+	data = simple_strtol (argv[4], NULL, 16);
+
+	buf[0] = (uchar)instr;
+	buf[1] = (uchar)cntrl;
+	buf[2] = (uchar)data;
+	i2c_write(addr, 0, 0, buf, 3);
+
+	return 0;
+}
+U_BOOT_CMD(
+	saa,	5,	1,	do_saa,
+	"Write to SAA1064 <addr> <instr> <cntrl> <data>",
+	""
+);
+
+/*
+ */
+int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	ulong data0;
+	ulong data1;
+	ulong data2;
+	ulong data3;
+	uchar buf[8];
+	int cnt;
+
+	if (argc < 3) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = simple_strtol (argv[2], NULL, 16);
+	data0 = simple_strtol (argv[3], NULL, 16);
+	data1 = simple_strtol (argv[4], NULL, 16);
+	data2 = simple_strtol (argv[5], NULL, 16);
+	data3 = simple_strtol (argv[6], NULL, 16);
+
+	printf("Writing %d bytes to device %lx!\n", cnt, addr);
+	buf[0] = (uchar)data0;
+	buf[1] = (uchar)data1;
+	buf[2] = (uchar)data2;
+	buf[3] = (uchar)data3;
+	i2c_write(addr, 0, 0, buf, cnt);
+
+	return 0;
+}
+U_BOOT_CMD(
+	iwrite,	6,	1,	do_iwrite,
+	"Write n bytes to I2C-device",
+	"addr cnt data0 ... datan"
+);
+
+/*
+ */
+int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	ulong cnt;
+	uchar buf[32];
+	int i;
+
+	if (argc < 3) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = simple_strtol (argv[2], NULL, 16);
+
+	i2c_read(addr, 0, 0, buf, cnt);
+	printf("I2C Data:");
+	for (i=0; i<cnt; i++) {
+		printf(" %02X", buf[i]);
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	iread,	3,	1,	do_iread,
+	"Read from I2C <addr> <cnt>",
+	""
+);
+
+/*
+ */
+int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	uchar buf[32];
+	int cnt;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = 1;
+
+	printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+	for (;;) {
+		i2c_read(addr, 0, 0, buf, cnt);
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(3000);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	ireadl,	2,	1,	do_ireadl,
+	"Read-loop from I2C <addr>",
+	""
+);
+#endif
diff --git a/u-boot/board/esd/tasreg/u-boot.lds b/u-boot/board/esd/tasreg/u-boot.lds
new file mode 100644
index 0000000..d4fd705
--- /dev/null
+++ b/u-boot/board/esd/tasreg/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/esd/vme8349/Makefile b/u-boot/board/esd/vme8349/Makefile
new file mode 100644
index 0000000..5b926b2
--- /dev/null
+++ b/u-boot/board/esd/vme8349/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2009 esd gmbh hannover germany.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o caddy.o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/vme8349/caddy.c b/u-boot/board/esd/vme8349/caddy.c
new file mode 100644
index 0000000..ca8357d
--- /dev/null
+++ b/u-boot/board/esd/vme8349/caddy.c
@@ -0,0 +1,194 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+	struct caddy_answer *answer;
+	uint32_t ptr;
+
+	answer = &caddy_interface->answer[caddy_interface->answer_in];
+	memset((void *)answer, 0, sizeof(struct caddy_answer));
+	answer->answer = cmd->cmd;
+	answer->issue = cmd->issue;
+	answer->status = status;
+	memcpy(answer->par, result, 5 * sizeof(result[0]));
+	ptr = caddy_interface->answer_in + 1;
+	ptr = ptr & (ANSWER_SIZE - 1);
+	if (ptr != caddy_interface->answer_out)
+		caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long base_addr;
+	uint32_t ptr;
+	struct caddy_cmd *caddy_cmd;
+	uint32_t result[5];
+	uint16_t data16;
+	uint8_t data8;
+	uint32_t status;
+	pci_dev_t dev;
+	void *pci_ptr;
+
+	if (argc < 2) {
+		puts("Missing parameter\n");
+		return 1;
+	}
+
+	base_addr = simple_strtoul(argv[1], NULL, 16);
+	caddy_interface = (struct caddy_interface *) base_addr;
+
+	memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+	memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+	while (ctrlc() == 0) {
+		if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+			memset(result, 0, 5 * sizeof(result[0]));
+			status = 0;
+			caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+			pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+				(caddy_cmd->addr & 0x001fffff);
+
+			switch (caddy_cmd->cmd) {
+			case CADDY_CMD_IO_READ_8:
+				result[0] = in_8(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_16:
+				result[0] = in_be16(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_32:
+				result[0] = in_be32(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_WRITE_8:
+				data8 = caddy_cmd->par[0] & 0x000000ff;
+				out_8(pci_ptr, data8);
+				break;
+
+			case CADDY_CMD_IO_WRITE_16:
+				data16 = caddy_cmd->par[0] & 0x0000ffff;
+				out_be16(pci_ptr, data16);
+				break;
+
+			case CADDY_CMD_IO_WRITE_32:
+				out_be32(pci_ptr, caddy_cmd->par[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_READ_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_byte(dev,
+							      caddy_cmd->addr,
+							      &data8);
+				result[0] = data8;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_word(dev,
+							      caddy_cmd->addr,
+							      &data16);
+				result[0] = data16;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_dword(dev,
+							       caddy_cmd->addr,
+							       &result[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data8 = caddy_cmd->par[3] & 0x000000ff;
+				status = pci_write_config_byte(dev,
+							       caddy_cmd->addr,
+							       data8);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data16 = caddy_cmd->par[3] & 0x0000ffff;
+				status = pci_write_config_word(dev,
+							       caddy_cmd->addr,
+							       data16);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_write_config_dword(dev,
+								caddy_cmd->addr,
+								caddy_cmd->par[3]);
+				break;
+
+			default:
+				status = 0xffffffff;
+				break;
+			}
+
+			generate_answer(caddy_cmd, status, &result[0]);
+
+			ptr = caddy_interface->cmd_out + 1;
+			ptr = ptr & (CMD_SIZE - 1);
+			caddy_interface->cmd_out = ptr;
+		}
+
+		caddy_interface->heartbeat++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	caddy,	2,	0,	do_caddy,
+	"Start Caddy server.",
+	"Start Caddy server with Data structure a given addr\n"
+	);
diff --git a/u-boot/board/esd/vme8349/caddy.h b/u-boot/board/esd/vme8349/caddy.h
new file mode 100644
index 0000000..65257ba
--- /dev/null
+++ b/u-boot/board/esd/vme8349/caddy.h
@@ -0,0 +1,77 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE	1024
+#define ANSWER_SIZE	1024
+#define CADDY_MAGIC	"esd vme8349 V1.0"
+
+enum caddy_cmds {
+	CADDY_CMD_IO_READ_8,
+	CADDY_CMD_IO_READ_16,
+	CADDY_CMD_IO_READ_32,
+	CADDY_CMD_IO_WRITE_8,
+	CADDY_CMD_IO_WRITE_16,
+	CADDY_CMD_IO_WRITE_32,
+	CADDY_CMD_CONFIG_READ_8,
+	CADDY_CMD_CONFIG_READ_16,
+	CADDY_CMD_CONFIG_READ_32,
+	CADDY_CMD_CONFIG_WRITE_8,
+	CADDY_CMD_CONFIG_WRITE_16,
+	CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+	uint32_t cmd;
+	uint32_t issue;
+	uint32_t addr;
+	uint32_t par[5];
+};
+
+struct caddy_answer {
+	uint32_t answer;
+	uint32_t issue;
+	uint32_t status;
+	uint32_t par[5];
+};
+
+struct caddy_interface {
+	uint8_t  magic[16];
+	uint32_t cmd_in;
+	uint32_t cmd_out;
+	uint32_t heartbeat;
+	uint32_t reserved1;
+	struct caddy_cmd cmd[CMD_SIZE];
+	uint32_t answer_in;
+	uint32_t answer_out;
+	uint32_t reserved2;
+	uint32_t reserved3;
+	struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */
diff --git a/u-boot/board/esd/vme8349/pci.c b/u-boot/board/esd/vme8349/pci.c
new file mode 100644
index 0000000..2802be1
--- /dev/null
+++ b/u-boot/board/esd/vme8349/pci.c
@@ -0,0 +1,136 @@
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "vme8349pin.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u8 reg8;
+	int monarch = 0;
+
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
+	    (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
+		if (reg8 & 0x40) {
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+			printf("PCI:   66MHz\n");
+		} else {
+			clk->occr = 0xffff0003;	/* 33 MHz PCI */
+			printf("PCI:   33MHz\n");
+		}
+		if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+			monarch = 1;
+	} else {
+		clk->occr = 0xffff0003;	/* 33 MHz PCI */
+		printf("PCI:   33MHz (I2C read failed)\n");
+	}
+	udelay(2000);
+
+	/*
+	 * Assert/deassert VME reset
+	 */
+	clrsetbits_be32(&immr->gpio[1].dat,
+			GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
+			GPIO2_VME_RESET_N  | GPIO2_L_RESET_EN_N);
+	setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+		     GPIO2_TSI_POWERUP_RESET_N |
+		     GPIO2_VME_RESET_N |
+		     GPIO2_L_RESET_EN_N);
+	clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
+	udelay(600000);
+	clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	if (monarch == 0) {
+		mpc83xx_pci_init(1, reg);
+	} else {
+		/*
+		 * Release PCI RST Output signal
+		 */
+		out_be32(&immr->pci_ctrl[0].gcr, 0);
+		udelay(2000);
+		out_be32(&immr->pci_ctrl[0].gcr, 1);
+	}
+}
diff --git a/u-boot/board/esd/vme8349/vme8349.c b/u-boot/board/esd/vme8349/vme8349.c
new file mode 100644
index 0000000..96698e7
--- /dev/null
+++ b/u-boot/board/esd/vme8349/vme8349.c
@@ -0,0 +1,221 @@
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <spd.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <netdev.h>
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main memory */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+	msize = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* Now check memory size (after ECC is initialized) */
+	msize = get_ram_size(0, msize);
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+#ifdef VME_CADDY2
+	puts("Board: esd VME-CADDY/2\n");
+#else
+	puts("Board: esd VME-CPU/8349\n");
+#endif
+
+	return 0;
+}
+
+#ifdef VME_CADDY2
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+
+int misc_init_r()
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
+
+	return 0;
+}
+
+/*
+ * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
+ * and VME-CADDY/2) have different SDRAM configurations.
+ */
+#ifdef VME_CADDY2
+#define SMALL_RAM	0xff
+#define LARGE_RAM	0x00
+#else
+#define SMALL_RAM	0x00
+#define LARGE_RAM	0xff
+#endif
+
+#define SPD_VAL(a, b)	(((a) & SMALL_RAM) | ((b) & LARGE_RAM))
+
+static spd_eeprom_t default_spd_eeprom = {
+	SPD_VAL(0x80, 0x80),	/* 00 use 128 Bytes */
+	SPD_VAL(0x07, 0x07),	/* 01 use 128 Bytes */
+	SPD_MEMTYPE_DDR2,	/* 02 type is DDR2 */
+	SPD_VAL(0x0d, 0x0d),	/* 03 rows: 13 */
+	SPD_VAL(0x09, 0x0a),	/* 04 cols:  9 / 10 */
+	SPD_VAL(0x00, 0x00),	/* 05 */
+	SPD_VAL(0x40, 0x40),	/* 06 */
+	SPD_VAL(0x00, 0x00),	/* 07 */
+	SPD_VAL(0x05, 0x05),	/* 08 */
+	SPD_VAL(0x30, 0x30),	/* 09 */
+	SPD_VAL(0x45, 0x45),	/* 10 */
+	SPD_VAL(0x02, 0x02),	/* 11 ecc used */
+	SPD_VAL(0x82, 0x82),	/* 12 */
+	SPD_VAL(0x10, 0x10),	/* 13 */
+	SPD_VAL(0x08, 0x08),	/* 14 */
+	SPD_VAL(0x00, 0x00),	/* 15 */
+	SPD_VAL(0x0c, 0x0c),	/* 16 */
+	SPD_VAL(0x04, 0x08),	/* 17 banks: 4 / 8 */
+	SPD_VAL(0x38, 0x38),	/* 18 */
+	SPD_VAL(0x00, 0x00),	/* 19 */
+	SPD_VAL(0x02, 0x02),	/* 20 */
+	SPD_VAL(0x00, 0x00),	/* 21 */
+	SPD_VAL(0x03, 0x03),	/* 22 */
+	SPD_VAL(0x3d, 0x3d),	/* 23 */
+	SPD_VAL(0x45, 0x45),	/* 24 */
+	SPD_VAL(0x50, 0x50),	/* 25 */
+	SPD_VAL(0x45, 0x45),	/* 26 */
+	SPD_VAL(0x3c, 0x3c),	/* 27 */
+	SPD_VAL(0x28, 0x28),	/* 28 */
+	SPD_VAL(0x3c, 0x3c),	/* 29 */
+	SPD_VAL(0x2d, 0x2d),	/* 30 */
+	SPD_VAL(0x20, 0x80),	/* 31 */
+	SPD_VAL(0x20, 0x20),	/* 32 */
+	SPD_VAL(0x27, 0x27),	/* 33 */
+	SPD_VAL(0x10, 0x10),	/* 34 */
+	SPD_VAL(0x17, 0x17),	/* 35 */
+	SPD_VAL(0x3c, 0x3c),	/* 36 */
+	SPD_VAL(0x1e, 0x1e),	/* 37 */
+	SPD_VAL(0x1e, 0x1e),	/* 38 */
+	SPD_VAL(0x00, 0x00),	/* 39 */
+	SPD_VAL(0x00, 0x06),	/* 40 */
+	SPD_VAL(0x37, 0x37),	/* 41 */
+	SPD_VAL(0x4b, 0x7f),	/* 42 */
+	SPD_VAL(0x80, 0x80),	/* 43 */
+	SPD_VAL(0x18, 0x18),	/* 44 */
+	SPD_VAL(0x22, 0x22),	/* 45 */
+	SPD_VAL(0x00, 0x00),	/* 46 */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	SPD_VAL(0x10, 0x10),	/* 62 */
+	SPD_VAL(0x7e, 0x1d),	/* 63 */
+	{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
+	SPD_VAL(0x00, 0x00),	/* 72 */
+#ifdef VME_CADDY2
+	{ "vme-caddy/2 ram   " }
+#else
+	{ "vme-cpu/2 ram     " }
+#endif
+};
+
+int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int old_bus = I2C_GET_BUS();
+	unsigned int l, sum;
+	int valid = 0;
+
+	I2C_SET_BUS(0);
+
+	if (i2c_read(chip, addr, alen, buffer, len) == 0)
+		if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
+			sum = 0;
+			for (l = 0; l < 63; l++)
+				sum = (sum + buffer[l]) & 0xff;
+			if (sum == buffer[63])
+				valid = 1;
+			else
+				printf("Invalid checksum in EEPROM %02x %02x\n",
+				       sum, buffer[63]);
+		}
+
+	if (valid == 0) {
+		memcpy(buffer, (void *)&default_spd_eeprom, len);
+		sum = 0;
+		for (l = 0; l < 63; l++)
+			sum = (sum + buffer[l]) & 0xff;
+		if (sum != buffer[63])
+			printf("Invalid checksum in FLASH %02x %02x\n",
+			       sum, buffer[63]);
+		buffer[63] = sum;
+	}
+
+	I2C_SET_BUS(old_bus);
+
+	return 0;
+}
diff --git a/u-boot/board/esd/vme8349/vme8349pin.h b/u-boot/board/esd/vme8349/vme8349pin.h
new file mode 100644
index 0000000..d1fd1b2
--- /dev/null
+++ b/u-boot/board/esd/vme8349/vme8349pin.h
@@ -0,0 +1,36 @@
+/*
+ * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __VME8349PIN_H__
+#define __VME8349PIN_H__
+
+#define GPIO2_V_SCON		0x80000000 /* In:  from tsi148 1: is syscon */
+#define GPIO2_VME_RESET_N	0x20000000 /* Out: to tsi148                */
+#define GPIO2_TSI_PLL_RESET_N	0x08000000 /* Out: to tsi148                */
+#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148              */
+#define GPIO2_L_RESET_EN_N	0x00100000 /* Out: 0:vme can assert cpu lrst*/
+
+#endif /* of ifndef __VME8349PIN_H__ */
diff --git a/u-boot/board/esd/voh405/Makefile b/u-boot/board/esd/voh405/Makefile
new file mode 100644
index 0000000..401622f
--- /dev/null
+++ b/u-boot/board/esd/voh405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/voh405/flash.c b/u-boot/board/esd/voh405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/voh405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/voh405/fpgadata.c b/u-boot/board/esd/voh405/fpgadata.c
new file mode 100644
index 0000000..02c94a2
--- /dev/null
+++ b/u-boot/board/esd/voh405/fpgadata.c
@@ -0,0 +1,2011 @@
+  0x1f,0x8b,0x08,0x08,0x38,0x6c,0x35,0x42,0x00,0x03,0x76,0x6f,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x33,0x2e,0x62,0x69,0x74,0x00,0xed,0xfd,0x7d,0x7c,0x1c,0xd5,
+  0x91,0x2f,0x8c,0x57,0x9f,0x6e,0xc9,0xad,0xe9,0x91,0xa6,0xf5,0x62,0x22,0x40,0x98,
+  0xd6,0x48,0x98,0x41,0x19,0x49,0x63,0xc9,0x18,0x63,0xcc,0xa8,0x2d,0x09,0x22,0x6c,
+  0x07,0x4f,0x80,0xcd,0xfa,0x66,0xb9,0xd9,0x31,0xf1,0x66,0xbd,0xfb,0x73,0xb8,0x82,
+  0xe4,0xd9,0x75,0x72,0xb3,0xe4,0x68,0x24,0xdb,0x23,0xcb,0xc1,0x83,0x71,0x88,0x20,
+  0xde,0xec,0xd8,0x78,0x89,0x21,0x4e,0xee,0x58,0x36,0x20,0x63,0x16,0x5a,0x46,0x80,
+  0x6c,0x8c,0x51,0x58,0x27,0xeb,0x10,0x42,0xc6,0x44,0x21,0x82,0x18,0x22,0x8c,0x49,
+  0xe4,0xf7,0xe7,0xd4,0xe9,0x97,0xe9,0x99,0x91,0xd9,0xcd,0xbd,0xf7,0x79,0xee,0x7e,
+  0x7e,0x8f,0x27,0x7f,0xa4,0xe8,0x39,0x6e,0xf5,0xa9,0x39,0x5d,0xf5,0x3d,0x55,0xdf,
+  0xaa,0x03,0x45,0xbe,0x09,0xf3,0x7f,0x00,0xc2,0x32,0x50,0xff,0xee,0xbf,0xad,0x98,
+  0x1d,0xba,0xf6,0x2f,0x67,0xfd,0x65,0xa8,0xb9,0xe1,0xee,0x2f,0x2d,0x87,0xbb,0x40,
+  0x69,0xfa,0xea,0xb5,0xa1,0xbf,0xfa,0xda,0x3d,0xb3,0x66,0xcf,0x86,0x2f,0xb1,0xff,
+  0x0a,0x85,0xae,0x6d,0x0c,0x35,0x37,0xce,0x9a,0x0d,0xcb,0xa1,0x68,0xd6,0xac,0x79,
+  0xb3,0xaf,0x9f,0xd7,0x34,0x17,0xfe,0x0a,0x84,0xe6,0x6d,0xe7,0xd9,0xe7,0x89,0x87,
+  0xff,0xec,0xcb,0x21,0xa0,0x02,0x00,0x4c,0x0b,0x09,0x51,0xfc,0x7f,0x25,0x24,0x68,
+  0x02,0xd0,0x96,0xfa,0x10,0x18,0xf8,0xdf,0x60,0x7d,0x5f,0x14,0x02,0xcd,0xfd,0xdf,
+  0x42,0x08,0x74,0x88,0x80,0xbe,0x5e,0x2d,0x83,0x7f,0xff,0x23,0xe8,0x12,0xb5,0xe5,
+  0x3f,0x71,0xfc,0xf9,0x03,0xf4,0x82,0xc3,0x32,0x9f,0x96,0xe3,0x49,0x4b,0x52,0x49,
+  0xe8,0x3f,0x72,0x7f,0xb0,0xef,0xfa,0xfb,0x37,0xfe,0x43,0xf7,0xff,0x83,0x7d,0xff,
+  0x3f,0x75,0x3c,0xa8,0xff,0x81,0xe1,0x00,0x92,0xf3,0x3c,0xaa,0xa0,0x41,0x07,0x14,
+  0x82,0x40,0x21,0x0a,0x95,0x17,0x10,0x5a,0x86,0xed,0xf1,0x86,0x70,0x0e,0xce,0xd3,
+  0x96,0x03,0xbe,0x81,0xee,0x7b,0xe1,0x1c,0x84,0xf5,0xe2,0x09,0xf1,0x3e,0xf5,0x4d,
+  0xb5,0x45,0xf3,0xbd,0x24,0x1e,0x87,0x33,0xb4,0xb9,0xd2,0xbb,0x4f,0x0c,0x41,0xa7,
+  0x3d,0x3e,0xfe,0x63,0xd8,0x4b,0x1b,0x26,0x94,0x13,0x7d,0x7e,0x58,0x67,0x34,0xec,
+  0xf3,0x9c,0x28,0xab,0xad,0xe8,0x8d,0x34,0x68,0x4a,0x8c,0xbc,0x03,0x83,0xd4,0x2f,
+  0xcb,0xb1,0x7d,0xa1,0x5a,0x5b,0x8b,0x23,0xd2,0x7a,0xd8,0x05,0x41,0x43,0x69,0x22,
+  0x00,0x03,0x0b,0x82,0x23,0x97,0xce,0x22,0x2b,0x20,0xa1,0xad,0xd4,0x94,0x42,0x62,
+  0xc0,0x20,0x68,0x95,0x72,0x39,0x69,0x02,0xcd,0xbe,0xbf,0xb4,0x03,0xf6,0x42,0x83,
+  0xa1,0xa4,0x88,0x46,0xd7,0x91,0x86,0xb4,0x27,0x45,0x02,0x6a,0x3c,0x7e,0xab,0xae,
+  0xc4,0x49,0x5a,0xdf,0x43,0xfd,0x9a,0xdc,0x4f,0x42,0x92,0xfd,0x3c,0x37,0x4d,0x3f,
+  0x06,0xa7,0xd9,0x78,0x5f,0xaa,0xcd,0x0f,0xa7,0x92,0xe1,0x0f,0x8b,0x53,0x0b,0x16,
+  0xc3,0x11,0x63,0x86,0xe0,0x7b,0x44,0x4c,0xc3,0x84,0x36,0xb0,0xc2,0xbb,0x5e,0x54,
+  0xdb,0xed,0xf1,0x49,0xe1,0x59,0x78,0x1e,0xae,0x64,0xe3,0xd9,0x77,0x1f,0x24,0xc2,
+  0x86,0x38,0xe1,0x3f,0xc1,0xee,0xd0,0xa2,0xfa,0xa8,0x78,0x02,0x35,0x00,0xbe,0x44,
+  0xdb,0x38,0xd3,0x94,0xf9,0x19,0x55,0x77,0xb0,0x6f,0xc3,0x86,0x2f,0x24,0x26,0xd5,
+  0x53,0xd0,0x34,0x5a,0x9c,0x12,0x8f,0xc1,0x49,0x68,0xea,0xf2,0x25,0x6f,0x0f,0x56,
+  0x8f,0xab,0xe1,0x98,0x77,0x4b,0x77,0x48,0xb2,0x9f,0x7f,0xa4,0x20,0xa8,0xee,0x85,
+  0x46,0x43,0x99,0x28,0x9b,0x16,0x5f,0x07,0x73,0x0c,0x79,0x82,0x1c,0x83,0x3d,0x11,
+  0xbf,0xa1,0xac,0xf6,0x37,0xb0,0xaf,0x1a,0x64,0x39,0x41,0xe6,0xb0,0xd5,0x6f,0xcf,
+  0x77,0x31,0x3c,0x08,0xb5,0x86,0x12,0x22,0x14,0x06,0x88,0xdf,0x90,0x53,0x64,0x31,
+  0x0c,0xa8,0x01,0x43,0x09,0x10,0x05,0x1e,0x1d,0x69,0x48,0xca,0xdb,0x0b,0x57,0xb1,
+  0x77,0xc5,0xfc,0x4c,0xc0,0x17,0xe1,0x69,0x5a,0x9f,0x56,0x56,0x91,0x32,0xf8,0x76,
+  0xe2,0xaa,0xb4,0xbc,0xaa,0xf0,0x67,0xb0,0x1b,0xaf,0x2c,0x25,0x33,0x54,0xf6,0x55,
+  0x54,0x5e,0x4a,0xee,0x73,0xee,0xdf,0x01,0x8b,0xd5,0x8f,0x60,0xbe,0xe1,0x9b,0x2b,
+  0x52,0xf8,0x50,0x0d,0x4d,0x7a,0x43,0xe2,0x08,0x9d,0x60,0x8a,0xf7,0x95,0xf6,0x41,
+  0xf2,0x2e,0x98,0xaf,0x7b,0x0b,0xc5,0xdb,0x88,0xbd,0x90,0xf4,0x2b,0x9e,0x85,0xf3,
+  0xd0,0xc2,0xf4,0xd3,0x35,0xaa,0x7f,0x58,0x1a,0x8e,0x97,0xec,0x14,0x27,0xe1,0x8c,
+  0xda,0x7c,0x87,0xef,0x27,0xe2,0x04,0x7e,0xd5,0xbe,0x61,0x54,0x4c,0x14,0xda,0xfa,
+  0x91,0x81,0xeb,0x67,0xcc,0x3b,0xd0,0x0d,0xf0,0x06,0x0d,0xa5,0xbd,0xbb,0xbb,0x83,
+  0x6c,0x58,0xd3,0x88,0x6f,0x42,0x7c,0x0f,0xf6,0xb7,0x37,0x1a,0xde,0xb4,0xe8,0x71,
+  0x7e,0xdf,0x91,0xca,0xcd,0xf0,0x34,0xd4,0x8f,0x14,0xdf,0x2b,0x26,0xe0,0xa7,0x50,
+  0x6d,0x14,0xfc,0x9d,0x78,0x07,0xfb,0x45,0xaa,0x47,0x94,0x08,0x79,0xd3,0xf8,0xc1,
+  0x8a,0x46,0x5d,0x1e,0x25,0x4d,0x8e,0x3e,0x35,0xf8,0x3e,0x9b,0x6f,0x30,0x5d,0xf4,
+  0x0d,0xcf,0x57,0xe1,0x01,0x5a,0x93,0xee,0x58,0x55,0xf8,0x45,0x78,0x92,0x56,0x6f,
+  0x63,0x1a,0x38,0xb7,0xa0,0x27,0x5e,0x9f,0x8e,0xaf,0x20,0xaa,0x73,0xff,0x15,0xd6,
+  0x7a,0x2b,0x4a,0x91,0x0d,0xf0,0x80,0xa0,0x19,0x0f,0xa7,0xc8,0x57,0xe8,0x9e,0x94,
+  0x96,0x56,0xfe,0x91,0x1c,0xa4,0x8f,0x42,0xf0,0x2e,0xf9,0x32,0x4f,0x99,0x73,0xff,
+  0xf1,0xe9,0xe3,0xc2,0x29,0x08,0xd3,0xe2,0xa4,0xb8,0x0a,0xde,0x92,0x76,0xd1,0x91,
+  0xa4,0xf8,0x75,0x38,0xa7,0x0f,0xc4,0x7c,0x63,0xe2,0x7b,0xda,0x01,0x68,0x19,0x0c,
+  0xbe,0x27,0xce,0x93,0xec,0xf9,0x76,0x08,0x49,0x98,0x84,0xb0,0xe0,0xa3,0x35,0x28,
+  0xdc,0xe7,0xf5,0xd1,0xdb,0xd3,0x15,0x93,0x7a,0x58,0xf5,0xad,0xa9,0x39,0x5a,0x39,
+  0xd9,0x1a,0x86,0x0d,0x3d,0xe2,0xeb,0x60,0xaf,0x7f,0x59,0xdd,0xc6,0x56,0x4b,0x58,
+  0xf7,0x25,0xca,0x67,0x26,0x2d,0xa1,0x16,0xf6,0x43,0x53,0x74,0x43,0x7f,0x73,0xad,
+  0x7a,0x12,0xe6,0x47,0xbd,0xa5,0x22,0x91,0xec,0xf1,0x54,0x5a,0xce,0xc6,0x37,0xe8,
+  0x8b,0x12,0xa4,0xa7,0xac,0x97,0x09,0x25,0x09,0xb2,0x0d,0x7a,0x75,0xff,0x4b,0x4a,
+  0xbf,0x27,0x48,0xf7,0xea,0x0d,0x2b,0xd8,0xfa,0xd7,0x1c,0xb3,0x30,0xb7,0xa0,0x16,
+  0x1e,0x66,0xc3,0x2e,0x4f,0x90,0xab,0xc8,0xe3,0x4c,0x50,0x12,0x85,0xb5,0xd0,0x1b,
+  0xdd,0xaa,0x2b,0x0f,0x90,0xda,0xf8,0x1e,0xda,0x70,0x13,0x5b,0x6f,0x85,0xce,0x7a,
+  0xd0,0x2a,0x24,0xd8,0x02,0x41,0x5d,0xa9,0xf0,0x6c,0x83,0x2e,0x08,0x46,0x94,0x8a,
+  0xc2,0xd5,0xd0,0xb5,0x40,0xd3,0x95,0xd9,0x4d,0x12,0xec,0x64,0x57,0xe4,0xd9,0x04,
+  0x04,0x7b,0x3d,0xac,0xf2,0x46,0xa1,0x1f,0x5f,0x0a,0x50,0x34,0x18,0x27,0x61,0x58,
+  0x02,0x6d,0x1a,0x19,0x81,0x26,0xf0,0xd1,0x36,0x0d,0x98,0xea,0x20,0x48,0x95,0x19,
+  0xa2,0xbd,0x3e,0xfb,0xa7,0xf3,0xf9,0x46,0x7c,0x9b,0xca,0x4f,0xc0,0xd9,0xd6,0x96,
+  0xc8,0xfd,0x9b,0x6a,0x4e,0xc0,0x79,0x7d,0x86,0xe1,0x3b,0x2c,0x0e,0xb3,0xaf,0x5a,
+  0x22,0x1b,0x0e,0x8b,0xef,0x14,0xda,0xef,0x63,0x65,0xc1,0x98,0xa9,0x9f,0x07,0xc5,
+  0x0a,0x54,0x8b,0xee,0xdd,0x54,0xbe,0xed,0xb6,0x57,0xe5,0x26,0x9d,0x8e,0x8a,0x4c,
+  0x51,0x85,0x2d,0x1d,0xde,0xd7,0xc5,0x42,0xc7,0xfe,0xcc,0xad,0x4c,0xb3,0xb5,0xdb,
+  0x50,0xa1,0xac,0x65,0x4a,0x88,0x13,0xbf,0xbc,0x8e,0x92,0x00,0xc4,0x61,0x2b,0x78,
+  0x62,0x4d,0x9a,0x7c,0x04,0x1a,0x2a,0xe3,0x6b,0x36,0x96,0x38,0xfa,0xec,0x80,0x1e,
+  0x9c,0x94,0xae,0xa8,0x33,0x25,0xd2,0xa5,0x6b,0xb7,0x29,0x15,0xa4,0x87,0x76,0xc9,
+  0x7e,0x5d,0xae,0xd8,0x58,0x8b,0xaa,0xb8,0x59,0x2e,0xf5,0x94,0x09,0xf6,0xfd,0xfb,
+  0xa5,0x6d,0xb0,0x47,0x60,0x6a,0x54,0x49,0xad,0xdc,0xab,0x69,0x4b,0xbf,0xa7,0x12,
+  0x89,0xf6,0x82,0x5f,0x0f,0xa4,0xb6,0x5e,0x45,0xf7,0x30,0x0d,0xcb,0x0f,0x91,0x99,
+  0xce,0x7a,0x48,0x4e,0xb7,0x9e,0x3f,0xf1,0xa5,0xab,0xa3,0xfb,0xa3,0x03,0x9f,0xf3,
+  0x25,0xc4,0x6d,0xf2,0x7e,0x23,0xa4,0x57,0x3c,0xac,0x48,0xea,0xbb,0x5a,0x78,0x65,
+  0x30,0xd1,0x16,0x70,0xec,0xd5,0x88,0x60,0xaf,0x07,0x65,0x2c,0xf4,0x21,0x0d,0x47,
+  0x4b,0x12,0xe2,0x98,0xf4,0xe1,0x48,0x78,0xb9,0x4f,0x15,0xc7,0xd4,0x9f,0x4b,0xf3,
+  0xa3,0xbe,0xca,0x07,0x4f,0x39,0xf6,0x47,0x56,0xf9,0x7a,0x63,0x4a,0x16,0x35,0x38,
+  0xb2,0xa0,0x49,0x0d,0xd2,0x1a,0x0d,0x98,0xfe,0x43,0xbe,0x78,0x8d,0x16,0x60,0x0b,
+  0x4f,0xf6,0xd2,0xb6,0x03,0xce,0x7a,0x0e,0x14,0x04,0xe0,0x19,0x68,0xa0,0x72,0x92,
+  0x3c,0xa2,0x3d,0x41,0xb6,0x52,0x92,0x64,0xfa,0xf9,0xb1,0xee,0xa7,0xca,0x38,0xb9,
+  0x46,0x7a,0x06,0x1a,0x37,0x06,0xc6,0xc9,0x01,0x67,0x3d,0x04,0x98,0xfd,0xc1,0xf7,
+  0x45,0x0e,0x91,0xcf,0x30,0x43,0x14,0x30,0x6e,0x09,0x11,0x2f,0x74,0x19,0x9a,0xa1,
+  0x54,0x92,0x62,0x68,0x86,0x60,0x54,0xae,0x62,0xe3,0x9d,0xf5,0x09,0x77,0xb2,0xf7,
+  0x37,0x98,0x96,0x9b,0xc8,0x11,0xe8,0x86,0x1a,0x34,0x5c,0x55,0xb0,0x45,0xae,0x1e,
+  0x55,0xf4,0x8d,0x95,0xf8,0x6a,0x53,0xb9,0x33,0x36,0xee,0xac,0xcf,0x78,0xfc,0x8b,
+  0xf0,0x47,0x7a,0x63,0xda,0xbb,0x4a,0xbc,0x0d,0xfe,0xad,0x67,0xd6,0xb1,0xe2,0x6f,
+  0xae,0x0d,0x1b,0x2f,0xd3,0x59,0x6f,0xfb,0x26,0xc5,0x19,0xda,0x89,0x75,0x2d,0x51,
+  0xef,0xd2,0x9a,0xf7,0xfc,0xf6,0x78,0xcf,0x15,0xa6,0xbd,0xdd,0xf0,0x64,0x75,0x92,
+  0x09,0xf3,0x8f,0x94,0x0c,0x90,0xaf,0xc0,0x59,0x78,0xee,0x48,0x71,0xfa,0xf2,0x31,
+  0x7a,0x9a,0xb4,0x80,0x6f,0x54,0xdc,0xe7,0xd8,0x1f,0xd2,0xf3,0x1c,0xfa,0xaf,0xb4,
+  0xf7,0xac,0xcf,0xaf,0x33,0xe1,0x9d,0xe2,0x93,0xe2,0x17,0xb5,0x63,0xb4,0x39,0xed,
+  0x3b,0x22,0x86,0xdb,0x5f,0xa3,0x2d,0x51,0x26,0x18,0xce,0xfa,0xd9,0x5e,0x59,0x85,
+  0x0f,0x69,0x14,0xaf,0x22,0xe5,0xd2,0xda,0x6d,0xf5,0xe3,0x05,0xab,0x0a,0xab,0xa4,
+  0xf5,0x52,0xb5,0xd1,0x67,0x90,0xca,0x8e,0x1f,0x40,0x7d,0x5c,0xe9,0xf4,0xbf,0xd7,
+  0x6e,0xdf,0x1f,0x80,0xdb,0x2b,0x43,0x6e,0x2a,0x8b,0xd0,0x1f,0xa8,0xf5,0xfb,0x98,
+  0xa2,0xe6,0xc3,0x63,0x50,0xad,0x2a,0x9f,0x23,0x73,0xa1,0x47,0xae,0xd7,0x99,0x60,
+  0xa8,0xb6,0xfe,0x35,0xc9,0x6b,0xda,0x9f,0x10,0x81,0x40,0xf7,0x68,0xf0,0x27,0xbd,
+  0x21,0x66,0xcf,0xbb,0x75,0x0d,0x94,0xf9,0x44,0x50,0x1f,0x35,0x82,0xcf,0xf6,0x6d,
+  0x27,0x23,0xce,0xfa,0xdc,0x3e,0xdd,0x9c,0xaf,0x77,0xa2,0x46,0x84,0xdf,0xb1,0x3f,
+  0xe4,0x9d,0x50,0xee,0x83,0x77,0x7b,0x8e,0x83,0xef,0x11,0xe5,0x2a,0x78,0xa5,0x2b,
+  0xdc,0xc9,0x1c,0xd3,0x7b,0xce,0xfa,0xa1,0x02,0xf3,0x77,0x02,0xfa,0xa3,0x69,0xbf,
+  0x86,0xdf,0x69,0xe1,0x7d,0xbe,0x94,0xb8,0xa3,0xe3,0xe4,0x65,0xec,0x0d,0xa5,0xe2,
+  0xb8,0xc4,0xd6,0x43,0xc2,0xb7,0xe5,0xc1,0xb4,0xb3,0x7e,0xaa,0x55,0xb4,0xe7,0xf3,
+  0x0c,0x66,0x8d,0x3b,0x8b,0x5e,0x86,0x66,0x76,0x7f,0xf1,0x0c,0xbc,0x06,0x2d,0x69,
+  0xdf,0x44,0xf7,0x89,0xd0,0x9b,0x72,0x8b,0xee,0x33,0x44,0x68,0xb7,0x9f,0x7f,0x8b,
+  0xb4,0xd2,0xf6,0xbf,0x5b,0xe1,0x17,0xc0,0xfd,0xd1,0x31,0xd8,0x4e,0x67,0x4e,0x2e,
+  0x59,0x4f,0xc6,0x60,0x90,0xd9,0x1f,0x65,0x73,0x4c,0xd3,0x55,0xe7,0x79,0x82,0xf6,
+  0x78,0xbf,0xd0,0x27,0xf0,0xf1,0x07,0xd9,0xaf,0xde,0x20,0x2b,0xfd,0x64,0x8c,0xee,
+  0x1d,0x6e,0x88,0x2a,0x71,0xbf,0xe6,0xac,0x37,0xb9,0xc2,0xd4,0x0f,0x5b,0x36,0xc9,
+  0x40,0xb9,0xe6,0x3f,0x72,0x59,0x53,0xd9,0x41,0x39,0x09,0xb5,0x40,0xa0,0x6c,0xa4,
+  0x22,0x05,0x41,0x50,0x80,0x38,0xee,0x08,0x48,0xf1,0x4a,0xa6,0x1f,0xf6,0xfc,0x27,
+  0xd8,0xfa,0x57,0xe4,0x59,0x6f,0x78,0x8f,0x77,0x9f,0x61,0xeb,0x3f,0x0c,0x0a,0x65,
+  0xfe,0xfd,0x88,0x10,0x16,0xa6,0x51,0x05,0x6a,0xec,0xe7,0xd9,0x52,0x70,0x86,0xfb,
+  0xaf,0x25,0x4f,0x75,0x8f,0xca,0xa7,0xc9,0x7d,0x06,0xf3,0xd7,0x67,0xe0,0x0c,0x7c,
+  0x0a,0x7c,0x46,0xcd,0x28,0x13,0x5a,0x60,0x89,0x51,0x3e,0x3e,0xcd,0xc1,0x33,0x05,
+  0xe7,0xe0,0x74,0x77,0x4b,0x7a,0xc9,0x53,0x62,0x18,0x17,0x12,0x04,0x07,0xdb,0x8e,
+  0xeb,0xaf,0xd1,0xeb,0x64,0xef,0xbe,0xf2,0x89,0xf8,0x41,0xb5,0x59,0xf3,0x8d,0x30,
+  0xc7,0xe7,0xe8,0x5f,0xfd,0x40,0x66,0xf8,0x27,0xad,0x34,0xfb,0x1b,0x18,0x10,0x0a,
+  0x26,0x3a,0x42,0x65,0xc7,0x68,0x1f,0xf5,0x17,0x06,0x1e,0x26,0xef,0xe8,0xf1,0x4e,
+  0xbf,0xd6,0x17,0xf7,0xa7,0x33,0xf6,0xbf,0xe0,0xa0,0x35,0xdf,0x32,0x9c,0x78,0x83,
+  0x24,0x87,0xee,0x32,0xa0,0x17,0x6a,0x65,0x19,0x0a,0x0d,0x60,0x70,0x06,0x16,0xa9,
+  0x85,0xfb,0x1c,0xfb,0x63,0x4c,0xb7,0xf1,0x8f,0x87,0x2b,0x96,0x32,0x7d,0xbe,0x03,
+  0xbd,0xaa,0xbf,0x9a,0x99,0xfd,0xb7,0x21,0x4e,0x19,0x90,0x48,0xcc,0x9c,0x70,0xec,
+  0x0f,0x54,0xb0,0xf5,0x23,0x85,0x11,0xff,0x04,0x71,0x21,0x6d,0x94,0x53,0xe2,0x3b,
+  0xf0,0x02,0x9d,0xd3,0xe9,0x5d,0x27,0xee,0xa3,0xfb,0xe3,0x03,0xba,0xef,0x47,0x0f,
+  0x8e,0x3a,0xf6,0xe1,0x28,0xe0,0x7a,0xb8,0x12,0xd7,0x03,0x57,0x54,0x17,0x0a,0xe4,
+  0xbc,0x14,0xa6,0x3e,0x3a,0xed,0x84,0x3c,0x21,0xb5,0xd4,0xfa,0xc6,0xc5,0x49,0xdd,
+  0x1e,0x6f,0xa8,0x3b,0xe4,0xd3,0x70,0x1f,0xbb,0xbf,0x88,0xf7,0x9f,0x97,0xf0,0xa6,
+  0xc4,0xe5,0xda,0x49,0xb8,0xef,0x92,0x20,0xbb,0x42,0x0f,0x2c,0x6d,0x5a,0xe6,0xdb,
+  0x2d,0x4e,0x64,0xf0,0x8f,0xc4,0x1f,0xfb,0xed,0x45,0x13,0x04,0x85,0x20,0x7b,0x7e,
+  0xf1,0x2b,0xb0,0x07,0xee,0x0e,0x31,0x37,0x74,0x35,0x33,0xd4,0xec,0xf9,0x77,0xbe,
+  0x30,0xe0,0xfc,0xbe,0xe9,0x02,0xd3,0xfe,0xb0,0xf5,0x83,0xfa,0x09,0x80,0x1c,0xf2,
+  0x47,0x6f,0x1a,0xc0,0x89,0x6b,0xc4,0xa3,0xc4,0x20,0x49,0x15,0x6f,0xeb,0xa4,0x83,
+  0x7f,0x96,0x09,0x33,0x38,0xfe,0x59,0xb4,0x8a,0xcc,0xe8,0x42,0x21,0xb0,0x8a,0x7c,
+  0x1e,0x9e,0x62,0xc2,0xa5,0x1d,0xe4,0x36,0x58,0x9d,0xaa,0x4e,0x5e,0xbe,0x8a,0xf4,
+  0xeb,0xf6,0x7a,0xeb,0x90,0xbd,0xf0,0xd1,0xea,0xa0,0xe1,0x9b,0xa7,0x94,0xd0,0x8f,
+  0x52,0x73,0xc1,0x7b,0x83,0xd8,0x01,0xc7,0x21,0xb8,0xd4,0xab,0x2a,0xa0,0x0d,0x85,
+  0x42,0xe0,0x13,0x98,0xbf,0xb6,0x3f,0x0e,0xfe,0xf9,0xa8,0xed,0x8c,0xcc,0x85,0x09,
+  0xf1,0x59,0xfd,0x1c,0xb4,0xe8,0x25,0x3f,0x61,0x88,0xe5,0x6c,0xa8,0xc5,0x78,0x6d,
+  0xa2,0x6d,0xd4,0xb1,0x3f,0xdb,0x0b,0x8e,0x99,0xf8,0x10,0xf5,0xf3,0x3b,0x06,0x24,
+  0x98,0x30,0x86,0x78,0x32,0xca,0x60,0xcf,0x9b,0xf0,0x2b,0x3a,0x30,0xe2,0xeb,0x61,
+  0x40,0xc8,0xb1,0xff,0xa5,0xa6,0x3d,0x51,0xbe,0x26,0xde,0x29,0x5d,0xc7,0xac,0x25,
+  0xb3,0x36,0x6f,0xc2,0xd3,0xc2,0xd5,0x46,0x9d,0xee,0x3f,0x4c,0xbe,0x0d,0xd5,0x31,
+  0xa5,0x33,0x76,0xdc,0xf9,0x7d,0x0d,0x8e,0x7f,0x18,0xba,0xfb,0x06,0xf9,0x22,0xfc,
+  0x80,0xd6,0x27,0x19,0xec,0x79,0x0b,0x38,0xcc,0x63,0x02,0xf9,0x2e,0xad,0xfe,0xca,
+  0xa2,0x5b,0x6e,0x9e,0x70,0xf0,0x4f,0x47,0x85,0xb9,0xde,0x16,0xa5,0x5a,0xb9,0x62,
+  0x77,0x31,0xc5,0x1e,0x12,0x76,0x45,0x6b,0xef,0x92,0x2f,0x25,0x2f,0xc2,0x03,0xaa,
+  0x86,0xaf,0xde,0xeb,0x8e,0xfd,0x61,0xf8,0x07,0x9d,0x38,0xf5,0x25,0x95,0x15,0xf0,
+  0x1e,0xb4,0xd0,0x2b,0x93,0xe2,0x49,0xfd,0x9c,0xde,0xb2,0x95,0x3d,0xff,0x69,0xfa,
+  0x56,0xa2,0x89,0x7d,0x25,0x9e,0xca,0xe0,0x1f,0x30,0xfd,0x11,0x5b,0x2d,0x5c,0x90,
+  0xae,0xa4,0xe2,0x51,0x7d,0x12,0x4a,0x60,0x49,0x5c,0x4c,0x6b,0xe3,0xed,0xe1,0xd0,
+  0x34,0x9a,0x85,0x7f,0x98,0x7f,0x24,0xe1,0x15,0xbe,0x84,0xaf,0xd6,0x72,0x7c,0xe8,
+  0xd6,0x21,0xbc,0x60,0x49,0xa2,0x6d,0x0c,0xf6,0x27,0xf8,0x95,0x7d,0x59,0xf8,0x87,
+  0x39,0xd9,0x65,0x4a,0x82,0xd4,0x32,0x21,0xcc,0xf0,0x8c,0xf8,0x92,0xdc,0x2b,0x84,
+  0xbf,0xc6,0xae,0x0c,0xcb,0xbd,0xcb,0x1a,0x8e,0x28,0xbb,0xd9,0x8b,0x6f,0xbf,0xef,
+  0x95,0x52,0x2d,0x3c,0x6e,0xe2,0x9f,0x5a,0x61,0x0f,0xc7,0x3f,0x64,0x26,0xf4,0x11,
+  0x2e,0x8c,0x41,0x2f,0x0a,0x9b,0xc8,0x4b,0x8e,0x7e,0x64,0x49,0x32,0xf1,0x40,0x05,
+  0x91,0x84,0x9d,0x1c,0xff,0x30,0xb5,0x74,0x41,0x20,0xb2,0x48,0xf5,0x0f,0x4b,0x5d,
+  0xed,0x08,0x15,0xca,0xf6,0x39,0xeb,0x61,0x50,0x66,0xb0,0x07,0x1a,0x18,0xec,0xf1,
+  0x68,0xd6,0xc4,0xc5,0x00,0xb3,0x3f,0x0d,0x74,0x03,0xda,0x9f,0x11,0xf3,0xca,0x07,
+  0xc4,0x7e,0x9e,0xfe,0x4b,0x2d,0x3c,0xb0,0x49,0x44,0xe1,0x86,0xc8,0xb4,0x44,0xf9,
+  0x6e,0x72,0x96,0xc1,0x1e,0x86,0x7f,0xce,0x16,0x9e,0xd5,0xf9,0x7c,0x1f,0x73,0xf0,
+  0x4f,0x3f,0xc7,0x0f,0x2d,0x7a,0x30,0xf1,0x43,0xae,0x9f,0x0e,0x86,0x07,0x4e,0xe8,
+  0xfb,0xd9,0x15,0x6f,0x42,0x3c,0x1c,0x7b,0xf5,0x7a,0xf6,0xfe,0xe2,0x1b,0x9d,0xc1,
+  0x3f,0x51,0xc4,0x3f,0x20,0xc7,0x18,0xfe,0x61,0x82,0x87,0x09,0x69,0xf6,0x60,0x6c,
+  0x5b,0xb1,0xa5,0x26,0x49,0xe2,0xb5,0x7e,0x34,0x8c,0xf7,0x3b,0xfa,0x04,0x18,0xc6,
+  0xf9,0x2e,0x90,0xd5,0x8d,0x92,0xba,0x13,0x56,0x2c,0xf6,0x94,0xc5,0x7a,0x10,0xf8,
+  0xdd,0x5a,0xa9,0x92,0xe1,0xd6,0x2e,0xd0,0xa2,0x4a,0xa8,0xd0,0x10,0x32,0x78,0x6c,
+  0x1b,0x70,0x90,0xa3,0x72,0xfd,0x33,0x21,0x81,0xfb,0x17,0xb8,0x5b,0xaf,0x64,0x40,
+  0x94,0xf6,0x06,0xfc,0x1d,0x4c,0xb1,0x6b,0x32,0xf8,0x07,0xf1,0x12,0x9b,0xaf,0x17,
+  0x7f,0x56,0x66,0x16,0x18,0x5e,0x15,0xdf,0x11,0xf6,0xd3,0x92,0xbf,0xf7,0xfe,0x23,
+  0xd3,0x00,0x22,0x3a,0xdf,0x43,0xcc,0x31,0xd9,0xf7,0x7f,0xc2,0xc4,0xc3,0x0b,0x98,
+  0x12,0xd8,0xc4,0x25,0xae,0x8d,0x31,0x7a,0x72,0xc1,0xfc,0x68,0x63,0x42,0x5c,0xa3,
+  0x9e,0xa4,0xe1,0x56,0x76,0xe5,0x3d,0x6a,0xdf,0x3f,0x60,0xe1,0x9f,0x12,0xc4,0x3f,
+  0x28,0x78,0x99,0xa0,0x1d,0x81,0xfb,0x64,0x6f,0x8f,0x52,0x1d,0x1d,0xd1,0x99,0xfe,
+  0x7b,0xc4,0x75,0x19,0xfc,0x23,0x05,0xe0,0x3d,0x21,0x18,0x2f,0x4a,0x16,0x6e,0x97,
+  0x10,0x08,0x15,0x27,0xc9,0xf5,0xb0,0x0e,0x6e,0x88,0x31,0x44,0x74,0xbd,0x7c,0x28,
+  0xd1,0x90,0x5a,0xb4,0x4d,0x5c,0x97,0xc1,0x3f,0xab,0xf9,0x6b,0x12,0xb5,0xed,0x33,
+  0x3a,0xee,0x46,0x06,0x84,0x82,0x9d,0x45,0xa1,0x42,0x2f,0x79,0x98,0x06,0x27,0xd8,
+  0xd6,0x75,0x9d,0x66,0xdb,0x9f,0x6a,0xc1,0xc4,0x0f,0x4a,0x67,0xe1,0x66,0x99,0x01,
+  0xa1,0xa1,0xa2,0x6f,0x90,0x4b,0x61,0x2d,0x5c,0xa3,0x17,0xcd,0xf5,0x57,0x09,0x6b,
+  0xe5,0xfa,0x7d,0x4a,0x27,0x89,0x3b,0xf6,0x27,0x20,0xa3,0xbd,0xba,0x31,0x5d,0x72,
+  0x8e,0xcc,0x80,0xbf,0xa7,0x37,0x9e,0x2a,0x3a,0x33,0x6d,0x1e,0xf9,0x37,0xda,0x18,
+  0xad,0x5f,0x25,0xce,0x80,0x9f,0xd2,0x1b,0xdf,0xf6,0xad,0xea,0x5e,0xe7,0x38,0x3c,
+  0xf9,0xd2,0x1d,0x68,0x46,0x8c,0xe2,0xdd,0x5f,0xb2,0x0c,0xcb,0xee,0x0d,0x69,0xb4,
+  0x27,0x7a,0x49,0xaa,0xed,0x18,0x39,0x4b,0xd8,0x95,0xc7,0x5c,0xf8,0x47,0x2f,0xe0,
+  0xfb,0xf7,0xf4,0x95,0x67,0xc4,0xfb,0x98,0x10,0x1e,0xf3,0x9d,0xac,0x99,0x57,0xf6,
+  0x72,0xe2,0x86,0xed,0xde,0x49,0x31,0x4c,0x5e,0xed,0x6a,0xfe,0x4d,0x70,0x9c,0xa1,
+  0x73,0x07,0xff,0x30,0xfb,0xf3,0x5b,0x7c,0xfe,0x7b,0xc5,0x5b,0xe9,0x2e,0xa8,0x1f,
+  0x57,0xbe,0x51,0x7e,0x5b,0x74,0x2d,0x5c,0xeb,0x91,0x3b,0xbb,0x97,0xfa,0xd7,0x4a,
+  0xd5,0x37,0xcb,0x11,0xf2,0x84,0xf3,0xfb,0x3e,0x0c,0xf6,0x7c,0x9b,0xaa,0x28,0x13,
+  0xde,0x64,0xb3,0x5b,0x2a,0x6d,0x10,0xae,0x59,0x0f,0xf7,0x90,0x3b,0xf5,0xd5,0xf2,
+  0xd5,0x3d,0x95,0x47,0x49,0xad,0xe3,0x2f,0xa2,0xcc,0xfe,0x3c,0x6a,0xfa,0x77,0xae,
+  0xd8,0x74,0x5f,0x88,0x2c,0xa3,0x22,0x68,0x09,0x79,0x2e,0xe9,0x85,0x75,0x46,0xad,
+  0x2a,0xcb,0x33,0x1f,0x71,0xd6,0xe7,0xdc,0xe9,0x3b,0xa4,0xd3,0x6c,0x52,0x0a,0xf3,
+  0x17,0x5e,0x36,0x4d,0xe6,0x38,0xc4,0xbf,0x85,0x57,0xa0,0xae,0xd3,0xfb,0xac,0xe7,
+  0x6e,0x7d,0xa4,0x67,0x8e,0x26,0x6f,0xea,0xf6,0xf4,0xd8,0xfa,0xa4,0xb0,0xd2,0xb6,
+  0xb7,0xc7,0x98,0x7f,0xb9,0xcf,0x98,0x96,0x12,0xdf,0x55,0x4f,0xe3,0x1b,0x37,0x00,
+  0x5f,0x91,0x4f,0xc9,0xf3,0x54,0xdf,0x00,0x5b,0x5a,0xf6,0xfd,0xbb,0x54,0xee,0xe6,
+  0x46,0xc4,0x90,0x38,0x9f,0x09,0x37,0x1a,0x8b,0x27,0xc4,0x49,0xf5,0x57,0xc0,0x96,
+  0x59,0x4a,0x3c,0xb7,0x69,0x44,0x6a,0x26,0xe2,0x68,0x79,0xba,0xdd,0x1e,0x3f,0x04,
+  0x2b,0x05,0xe6,0xbf,0x86,0x94,0x94,0x68,0x02,0xa1,0x92,0x14,0x79,0x5b,0xfa,0x21,
+  0x34,0x5c,0x7f,0x65,0x8a,0xbc,0x2a,0xf5,0x1a,0x7e,0x59,0x49,0x92,0x89,0x0c,0xfe,
+  0x91,0x70,0xbf,0xcf,0xf1,0x8f,0x09,0x84,0x3a,0x52,0x33,0xff,0x16,0xbe,0x27,0x34,
+  0x24,0xd9,0x95,0xdf,0x90,0xed,0x86,0x3f,0xad,0xc4,0x49,0x32,0x83,0x7f,0x10,0x1f,
+  0xaa,0x4c,0x3f,0xb3,0xc9,0x62,0x8d,0xa1,0xeb,0x11,0x4f,0x88,0x8c,0xd0,0x47,0x85,
+  0xa0,0xbe,0x30,0x34,0xf3,0x20,0x7b,0x9d,0xd8,0x46,0x4c,0x85,0x7d,0xce,0xfe,0x8b,
+  0x16,0xad,0x94,0xf7,0xea,0x6c,0xbe,0x27,0xae,0x0e,0x1a,0x7b,0xf5,0x2b,0xf7,0x57,
+  0xfd,0x5d,0xcd,0x38,0xfd,0x05,0xe2,0x1f,0x74,0x34,0xe3,0x42,0x53,0x17,0xb3,0xc0,
+  0x49,0xd1,0x1e,0x9f,0x2c,0xb6,0xf0,0xcf,0x84,0x78,0x4c,0x3a,0x1f,0x68,0x19,0x2e,
+  0xd9,0xd5,0x6d,0xe8,0xec,0x0a,0x6c,0x98,0x60,0xfe,0xe8,0x4e,0xe1,0x46,0x58,0xa2,
+  0x8b,0xd9,0xf8,0x07,0xd7,0x8f,0xef,0x8c,0x12,0x80,0x5f,0xd2,0xeb,0xf6,0xfb,0x4e,
+  0x3c,0x78,0xa3,0x74,0x50,0xbb,0x41,0x5d,0x6c,0x88,0x21,0x83,0x6d,0xfc,0xc1,0x3b,
+  0x4c,0x5c,0xf1,0x1f,0xf5,0x03,0x8c,0xff,0xa4,0xc5,0x14,0xc3,0x3f,0x7d,0xb4,0x66,
+  0x58,0xd9,0x4d,0xaa,0xe4,0xde,0x8a,0xad,0xaa,0xbc,0x5e,0xac,0x36,0x06,0x3b,0xfd,
+  0x77,0xca,0xab,0x5b,0x5d,0xf1,0x1f,0x1b,0xff,0x0c,0xb0,0x6d,0xc8,0xc3,0x18,0xe8,
+  0xf0,0x13,0xef,0xc6,0x18,0x04,0x2a,0x65,0x89,0x80,0x9a,0xaa,0xd6,0x48,0x07,0x71,
+  0xc7,0x7f,0x2c,0xfc,0xf3,0x17,0xa8,0xcf,0xde,0x6e,0x44,0x3b,0xc4,0x5b,0xf8,0xc3,
+  0x98,0x5f,0x93,0x77,0x2c,0xac,0x83,0xb9,0xd4,0x9f,0x94,0x07,0x0b,0x33,0xf1,0x1f,
+  0xbd,0x74,0xa5,0x1d,0x9f,0xa9,0x95,0x7e,0xd2,0x33,0xc7,0xf0,0x25,0x7e,0x10,0x84,
+  0xf8,0xc1,0x79,0x2b,0xbc,0x5e,0xf1,0x6a,0x38,0x99,0x1c,0xf0,0x33,0x20,0x94,0x1d,
+  0xff,0x31,0xdd,0x7a,0xf7,0x31,0xee,0xdf,0x37,0xdc,0xa1,0x9c,0x21,0x3f,0x61,0x1b,
+  0xdb,0x0d,0x09,0x31,0x2d,0x1f,0x87,0xf9,0xfa,0xff,0xd0,0x17,0x65,0xc5,0x7f,0x64,
+  0x8e,0x3f,0x77,0x8a,0xb5,0x0c,0x4d,0x85,0x0f,0xb2,0xd5,0x15,0x84,0x37,0xe0,0xa9,
+  0x5e,0xef,0xa6,0x9a,0xea,0x7d,0x6c,0x23,0xd6,0xea,0x7d,0xd0,0x8d,0x7f,0x0a,0xcc,
+  0x65,0x50,0xf4,0x6c,0xdb,0x62,0xd2,0x67,0x34,0xa6,0x7d,0x94,0xcc,0xd7,0xfb,0xc0,
+  0x1f,0xf0,0x3e,0xe2,0xa9,0x91,0x47,0x96,0xfa,0x3b,0x3c,0x9b,0xc9,0x1f,0x9c,0xf5,
+  0x60,0xe2,0x9f,0x00,0x7b,0x5f,0xfc,0x1d,0xd0,0xdd,0xce,0xac,0xcd,0xec,0x4b,0x8a,
+  0xe1,0x81,0x75,0x33,0x13,0xb7,0x84,0xd6,0xdc,0x22,0x0c,0x50,0x2d,0x59,0x39,0xdb,
+  0x9f,0xc1,0x3f,0x93,0xc2,0x0c,0x81,0xe3,0x81,0x53,0x85,0x5f,0x34,0xa6,0xd1,0xfa,
+  0x31,0xcf,0x42,0x32,0x43,0x5a,0x9b,0xaa,0x8e,0xca,0xb7,0x14,0xce,0xf8,0xdc,0x3f,
+  0xd3,0x6a,0xcd,0x73,0x4b,0xd9,0xb9,0x4c,0xfc,0x47,0x46,0xb3,0x36,0xd7,0xf0,0x3d,
+  0xd3,0xb6,0x30,0x29,0xa4,0xe6,0x8f,0x2b,0xdb,0x15,0x2f,0xfc,0x6b,0x60,0xb7,0xfe,
+  0x59,0xed,0xba,0x02,0xe9,0x43,0x08,0xc5,0x83,0x21,0xf1,0xf5,0x4c,0xfc,0xa7,0xd8,
+  0xd4,0x4f,0xf1,0xce,0x1a,0x06,0x9b,0x85,0x46,0xe3,0xca,0xb4,0x78,0xc6,0x7f,0x5e,
+  0x63,0xdb,0x84,0xf4,0xa7,0xce,0xc0,0x2f,0x19,0x42,0x28,0x9e,0x10,0xa7,0xc4,0x3f,
+  0x12,0x7b,0x6d,0xc3,0xc7,0x8b,0x93,0x4a,0xbd,0xff,0x77,0xb8,0xd1,0x88,0x88,0x7f,
+  0x80,0xd7,0x48,0x4b,0x54,0x36,0xdc,0xf1,0x1f,0x66,0x7f,0xae,0xe3,0xf6,0xc4,0x53,
+  0x55,0xb4,0x96,0x2d,0x8c,0x75,0x11,0xe2,0x4d,0x30,0xb3,0xa3,0xcb,0x11,0x71,0x36,
+  0x59,0x0b,0x8d,0xba,0x6c,0x78,0x32,0xf1,0x1f,0x6a,0xe3,0x1f,0x84,0x79,0x6b,0xe9,
+  0x57,0xc6,0x2a,0x3b,0x5a,0x67,0xc0,0xa3,0x54,0x4b,0xcb,0x4b,0xc9,0x43,0xb5,0xab,
+  0x69,0xfd,0x5d,0x45,0x4b,0x5d,0xf1,0x1f,0x0b,0xff,0x0c,0x2d,0x0a,0x91,0x25,0xd0,
+  0x9d,0x0c,0x1a,0x9e,0x62,0x06,0x2c,0xbb,0x13,0xfe,0xc8,0xf6,0xaa,0x56,0xb6,0x91,
+  0x8f,0x30,0xc3,0xbe,0x71,0xa6,0x3b,0xfe,0xb3,0xdd,0xc4,0x3f,0x9a,0xb8,0x2a,0xfa,
+  0xd2,0xd6,0x30,0x8d,0xa7,0xc5,0x80,0xf4,0x63,0xe9,0xab,0x49,0xef,0xb1,0xee,0x67,
+  0xe0,0x10,0x6d,0x61,0x7f,0xbc,0xdb,0x15,0xff,0x61,0x2b,0x83,0xc3,0x80,0x1e,0x31,
+  0x59,0xc6,0x1d,0x13,0xd4,0x1c,0x65,0x57,0x9e,0xbb,0xc4,0xb7,0x46,0x64,0xae,0x4a,
+  0x0e,0x97,0x95,0xf4,0xe4,0xe2,0x1f,0xb4,0x4e,0xfd,0x62,0x3b,0xf3,0x86,0xcc,0x9b,
+  0x27,0xba,0xb7,0xc1,0x4f,0x36,0x35,0x45,0x83,0x09,0xf1,0x2a,0x38,0x49,0x9b,0xa2,
+  0x05,0x9b,0x72,0xe2,0x3f,0xe8,0x76,0xfb,0x1e,0x21,0x57,0x91,0xde,0x68,0x9d,0x7e,
+  0x3f,0xc3,0x33,0x72,0xaf,0xe4,0xef,0x94,0x2f,0x41,0x8f,0x9c,0xdc,0x1a,0x5d,0xf4,
+  0x90,0x2b,0xfe,0x53,0x59,0x60,0xba,0x69,0x65,0x63,0x61,0x2d,0xe9,0xa3,0x75,0x51,
+  0x06,0x84,0x7a,0xe8,0xc3,0xc4,0xdf,0x11,0x4f,0x94,0x8c,0x69,0x7b,0x54,0x7f,0xfb,
+  0xa5,0xee,0xf8,0x8f,0x1b,0xff,0x48,0x02,0x68,0xf7,0xc8,0x15,0xa4,0x58,0xea,0xd2,
+  0xb5,0x51,0x59,0x2d,0x5c,0x0d,0x3b,0x17,0x68,0x91,0xef,0x55,0x78,0x32,0xf1,0x9f,
+  0xb9,0xc5,0x88,0x37,0x10,0xe4,0x30,0xfb,0xd0,0x81,0x61,0x1f,0x60,0xd3,0x7c,0x03,
+  0x06,0x60,0x31,0xc5,0xf9,0x42,0x13,0x2d,0xa6,0xa2,0x2b,0xfe,0x73,0x85,0x35,0xdf,
+  0x88,0xf0,0x31,0xdb,0xb6,0x87,0x3f,0x57,0x72,0x58,0xfc,0x8d,0xe7,0xac,0xfe,0x3c,
+  0xc3,0x3f,0x6d,0xff,0x00,0xe7,0x75,0x0e,0x84,0xdc,0xf1,0x1f,0x2b,0x1e,0x32,0x2a,
+  0x9e,0xd0,0x3e,0x86,0x96,0x85,0x55,0xa3,0x62,0xed,0x2d,0xef,0x83,0x12,0x91,0x5e,
+  0x8f,0xcd,0x4e,0x17,0x43,0xf3,0xc2,0xe2,0xd1,0x6e,0x57,0xfc,0x47,0xe5,0xf1,0x1f,
+  0x06,0x72,0x08,0x17,0x2a,0x7d,0xa4,0x55,0x28,0x8d,0x47,0xfd,0x95,0x72,0x0f,0xa9,
+  0x86,0xf8,0x3d,0x4d,0x0f,0x30,0x44,0xe4,0x8a,0xff,0x48,0xed,0xe6,0x7c,0x43,0x31,
+  0x0e,0x84,0x5a,0x3d,0xb3,0xd7,0xad,0xa6,0x5b,0x3a,0x92,0x11,0x86,0x70,0xa4,0x9e,
+  0x2e,0xb9,0xb6,0x55,0x56,0x63,0x99,0xf8,0x4f,0xe5,0x74,0x13,0xff,0x70,0xf4,0xb8,
+  0xb7,0xb5,0x61,0x81,0xa2,0x92,0x1e,0xdc,0x7f,0x7d,0x4e,0xde,0xb8,0xae,0x96,0x16,
+  0x81,0x7f,0x81,0xbc,0x69,0xca,0xf8,0x8f,0x38,0x26,0x9f,0x8c,0xdc,0xa7,0xcb,0xdf,
+  0x13,0xb7,0xc1,0xe3,0xb1,0xa6,0x48,0xb0,0x02,0xae,0x82,0xfd,0xfa,0x53,0x51,0x6f,
+  0xbf,0x98,0x89,0xff,0x8c,0x3b,0xf1,0x9f,0x72,0xf6,0x0f,0x85,0xf9,0xad,0xc5,0x09,
+  0x71,0xa5,0x7c,0x52,0x9e,0xbf,0xdc,0xd7,0xff,0xe9,0x97,0xc8,0x87,0xea,0xfc,0x85,
+  0x8d,0x65,0x7d,0x99,0xf8,0x8f,0x8d,0x7f,0x7c,0x71,0x86,0x7f,0x46,0xf4,0x26,0x58,
+  0xdc,0xd3,0xac,0xa9,0x23,0x64,0x8e,0xe8,0xa3,0x35,0xcb,0x8c,0xf8,0xe2,0x26,0xd5,
+  0xdb,0x23,0x7a,0xf2,0xe2,0x3f,0x4a,0xda,0x33,0x57,0xba,0x5f,0xaf,0x49,0x79,0xd2,
+  0xa4,0x8e,0x30,0x21,0xa6,0xa4,0xc9,0x3c,0xf8,0x71,0xec,0xd1,0xe4,0x8a,0x71,0xe2,
+  0xc9,0xe0,0x1f,0x7b,0xff,0x15,0x22,0x52,0x6d,0xf7,0x88,0x36,0x01,0x21,0x7d,0x31,
+  0x5d,0x47,0x6b,0x23,0xec,0xca,0x8b,0xc2,0x16,0xaa,0xb5,0xcb,0x15,0x97,0x2d,0x74,
+  0xd6,0x5b,0xd2,0xc6,0x3f,0xab,0xc8,0x25,0xb0,0xd6,0xa8,0xde,0xb7,0xb0,0x93,0xfc,
+  0x57,0xe8,0xd6,0xab,0x75,0xb6,0x6d,0xd9,0x04,0x6b,0xe4,0x6a,0xda,0x7f,0x07,0x59,
+  0xe1,0x8c,0xdf,0xce,0xf0,0x0f,0xc6,0x7f,0x7c,0x93,0x62,0x19,0xbc,0x4c,0x1f,0x4c,
+  0x7b,0x57,0x29,0x5f,0x24,0x2f,0x75,0x5d,0x9b,0xdc,0xb0,0x4a,0xfc,0x03,0x79,0x9f,
+  0x36,0x47,0xbd,0x47,0xca,0xff,0xd6,0x89,0xff,0xc8,0x56,0xfc,0x87,0x81,0x6a,0xa3,
+  0xcc,0x32,0x2c,0x3f,0x4a,0x9e,0x24,0xcf,0x03,0xb3,0xf0,0x5f,0x23,0xb8,0x7f,0x67,
+  0x4b,0x25,0xe6,0xd8,0x1f,0xe0,0xfe,0xeb,0x86,0xb4,0x6f,0xbf,0x38,0x07,0xce,0xd1,
+  0x96,0x31,0xf6,0x87,0xc2,0xf2,0xb9,0xc4,0xd3,0xcb,0x97,0x4c,0x92,0x53,0xf4,0x97,
+  0x9b,0xd8,0x46,0x6c,0x9c,0x79,0x47,0x37,0xfe,0xe1,0xcf,0xff,0x48,0xab,0x8a,0xeb,
+  0x61,0x9c,0xb9,0xe9,0x2a,0x78,0x2a,0x54,0x7d,0xf3,0xa2,0xce,0x32,0x55,0x7b,0x6a,
+  0x96,0x8f,0x16,0xeb,0x4d,0x75,0xba,0x73,0x7f,0x1e,0xff,0xb9,0xc6,0x50,0xa2,0x24,
+  0x02,0x4f,0xab,0xf5,0x07,0x19,0xfe,0xa9,0x82,0xdd,0xa4,0x7a,0x75,0xd1,0xff,0x45,
+  0x2a,0x7b,0x9e,0x84,0xfa,0xf6,0xa2,0x65,0x04,0x1c,0xfb,0xa3,0x59,0xfb,0x2f,0x05,
+  0x88,0xae,0xee,0xf4,0x72,0x47,0xef,0x85,0xeb,0x65,0x7f,0x92,0xe9,0xb3,0x08,0x9e,
+  0xd1,0x83,0x0f,0x5d,0x73,0x95,0x2a,0xe7,0xc4,0x7f,0x98,0x7f,0x09,0xd5,0x2c,0xd3,
+  0x4f,0x1a,0x61,0xe3,0xf2,0x14,0xdb,0x5f,0x7c,0x83,0x36,0x45,0x8a,0x37,0x79,0x66,
+  0x96,0xb2,0x2b,0x91,0xe2,0xcd,0x45,0x75,0x99,0xf8,0x0f,0x58,0xf6,0x36,0x71,0xf9,
+  0x76,0x1c,0x3f,0x7a,0xe5,0x13,0x35,0xc7,0xe4,0x49,0x3a,0xaf,0xc3,0xb7,0x45,0xf9,
+  0x67,0xed,0x54,0x24,0x9c,0x28,0xd9,0x24,0x66,0xe2,0x3f,0x82,0x89,0x7f,0x0c,0xdf,
+  0xbb,0x62,0x08,0x5e,0x8b,0x7d,0x6b,0xc2,0x3b,0x51,0xae,0xaa,0x6f,0x18,0xcd,0x34,
+  0xd8,0x2f,0xce,0x96,0xce,0xca,0x0a,0x5b,0xea,0x5d,0x86,0x13,0xff,0xa1,0x56,0xfc,
+  0xa7,0xef,0x31,0x52,0xa4,0x9f,0x36,0x1a,0x26,0xb6,0xff,0x28,0x76,0x75,0xf4,0x87,
+  0x50,0x17,0x90,0xe7,0x76,0x7f,0x09,0x06,0x87,0xfd,0x51,0x65,0x1d,0x89,0x66,0xc5,
+  0x7f,0x7e,0x08,0x77,0xf3,0x7c,0x8d,0xd6,0xab,0x05,0x47,0x8b,0x54,0xa2,0x15,0xf5,
+  0xcb,0x77,0x45,0xe5,0x01,0xff,0xdf,0x6a,0x7b,0xe2,0xfe,0xce,0xcb,0xb7,0xb7,0xa6,
+  0xb3,0xf1,0x0f,0xea,0x47,0x25,0x72,0xfb,0x4e,0x3d,0x38,0x24,0x03,0xdb,0x88,0x25,
+  0xd9,0x8a,0x61,0xfb,0x7d,0x7c,0x55,0x35,0xe8,0x03,0xf6,0x4a,0x3b,0xea,0x2f,0x5e,
+  0xc9,0xf1,0xb0,0xaf,0xa7,0x4d,0x53,0x5f,0xd1,0x1b,0x86,0x8b,0x1f,0x28,0xd7,0x98,
+  0xfd,0x69,0xd2,0xbd,0xa9,0x1a,0x4d,0x9d,0x44,0x8b,0x94,0x10,0x8d,0xab,0x6d,0xfb,
+  0x93,0xbc,0xc2,0x9a,0x6f,0xf7,0xa3,0x93,0xf1,0xf3,0x24,0xec,0xfd,0xa7,0x7d,0x66,
+  0xda,0x02,0x7c,0x13,0x8d,0x29,0x38,0xc3,0x9c,0x8f,0xcf,0xb8,0x7d,0xdc,0xb1,0x3f,
+  0x56,0xfe,0x4b,0x5b,0xd9,0xd1,0x76,0x37,0x9c,0xaf,0x6e,0x4e,0x6f,0x18,0x14,0x3f,
+  0x60,0xe3,0x9b,0x47,0x8b,0x57,0x89,0x9d,0xa3,0x07,0x2b,0x9a,0xbd,0xde,0x17,0xc4,
+  0xce,0x4c,0xfc,0x07,0x18,0xfe,0xe9,0x99,0x97,0x96,0x07,0x49,0x03,0x3c,0x9f,0x60,
+  0xe8,0x6e,0x90,0x7c,0x00,0xcf,0xaf,0xaa,0x39,0x5c,0xbc,0xbd,0x55,0xdb,0xc7,0x0c,
+  0x51,0x95,0xbc,0xa9,0x55,0x73,0x7e,0x5f,0x2b,0xfe,0x93,0x96,0x43,0x7e,0x9c,0x38,
+  0xdf,0x7d,0x1f,0x2c,0xda,0x0b,0xda,0x48,0x51,0xaa,0xb0,0x9d,0x52,0x55,0xd3,0xe3,
+  0x85,0xad,0x24,0x13,0xff,0x29,0x45,0xfc,0x53,0x07,0xf2,0xa0,0x1f,0x7f,0x08,0x3f,
+  0x2a,0x96,0x01,0x5d,0xe2,0x37,0x8a,0xb6,0x96,0xf9,0xb5,0x38,0xf5,0x17,0xca,0xf1,
+  0x58,0xc8,0xb1,0x3f,0x3a,0xcf,0x7f,0xcd,0x1f,0xf6,0xce,0x56,0x56,0x4a,0xa7,0x61,
+  0xc0,0x04,0xc6,0x1f,0xd2,0x01,0xbd,0x3e,0x21,0x7e,0x09,0x46,0x92,0x03,0xd4,0xbb,
+  0x9e,0x19,0x53,0xfb,0xfe,0x69,0xc4,0x3f,0x84,0xe9,0xc7,0x10,0x9f,0xc5,0x6d,0x85,
+  0x15,0x08,0xc2,0x6d,0xe9,0x48,0xb7,0x21,0x7f,0x28,0xcd,0x5f,0xf6,0xdf,0x54,0x71,
+  0xd2,0x59,0x3f,0x86,0x99,0xff,0x3a,0xe8,0xdd,0x59,0x13,0x84,0x8f,0xa0,0xc9,0xbc,
+  0xff,0x49,0x75,0xb6,0xf1,0xd9,0x84,0xf8,0x37,0xf2,0x2b,0xd0,0xf4,0xa6,0x77,0x77,
+  0x76,0xfe,0x0b,0xd7,0xcf,0x84,0xfc,0x2f,0x0c,0xbf,0xfd,0x9e,0x8d,0xc7,0xe7,0x97,
+  0xf6,0x76,0x6d,0x1d,0x8a,0x4b,0xc4,0xcf,0xfc,0xef,0xd6,0xcf,0xc9,0xfd,0x64,0x20,
+  0x07,0xff,0x30,0xfd,0xcc,0xaf,0x43,0xfd,0xf0,0x44,0xd8,0x41,0xd8,0x49,0x6b,0xd9,
+  0x46,0xac,0xb5,0x48,0xeb,0x56,0xa3,0x9a,0x7c,0x0d,0x99,0xeb,0xe0,0x9f,0x28,0x8f,
+  0xff,0x7c,0x25,0x2d,0xaf,0x62,0xfb,0xa9,0x1f,0xd0,0x6a,0xb6,0x7f,0x21,0x6f,0xc1,
+  0xae,0x44,0xf5,0x58,0x7c,0x55,0xeb,0x25,0x42,0x4f,0xa2,0xba,0x56,0x5e,0x48,0xfa,
+  0x5d,0xf9,0x2f,0x2f,0x7c,0x24,0xcc,0x37,0x82,0x82,0x58,0x22,0x7d,0x44,0x77,0x8f,
+  0xfb,0xe6,0x89,0x87,0xf4,0x0f,0x85,0xdd,0xc6,0x67,0x43,0xa2,0xb4,0xde,0x50,0x43,
+  0x34,0x08,0x4a,0x59,0x4e,0xfe,0xeb,0x46,0xa3,0xf1,0x43,0x36,0xcd,0xf3,0xf2,0xf3,
+  0x86,0xef,0x43,0xae,0x9f,0x96,0x21,0xa6,0xa8,0xdd,0x70,0x46,0x65,0x0b,0x69,0xdf,
+  0x67,0x22,0x19,0xfc,0xc3,0xf5,0xcf,0xb6,0xa5,0x6c,0x77,0x06,0xa7,0x3b,0xc2,0xc6,
+  0x22,0x2e,0xe8,0xcf,0xb5,0x7a,0x43,0xe2,0xb3,0xf2,0x6b,0xc0,0xec,0xdb,0xa4,0x58,
+  0x97,0x17,0xff,0x09,0x74,0x4e,0x33,0x85,0x92,0x4e,0xf2,0x26,0x3c,0xcd,0x60,0xbf,
+  0xdc,0x49,0x2a,0xa4,0x17,0xa1,0x46,0x97,0x47,0xc5,0x7b,0x73,0xe2,0x3f,0x75,0x38,
+  0xdf,0xb7,0xe0,0xe9,0x64,0x7d,0xfa,0xe1,0x55,0xfe,0xb7,0x8a,0x10,0x11,0xc9,0xab,
+  0x6e,0xbe,0x1f,0xbe,0x6b,0x54,0xa7,0x3d,0xab,0x18,0x3e,0xb7,0xf5,0xdf,0x21,0x1d,
+  0x94,0x98,0x3e,0x25,0x86,0xae,0xcd,0x44,0x98,0x07,0xf5,0xb9,0x2b,0xa1,0x0d,0x07,
+  0xe6,0x62,0x62,0x88,0x6a,0x5f,0xab,0x9b,0xee,0xb9,0x2d,0x13,0xff,0x29,0x40,0xfc,
+  0x33,0x37,0xe9,0xdd,0xc2,0x36,0xe9,0x66,0x22,0x6c,0x1a,0x8f,0x08,0x6d,0x61,0x66,
+  0x73,0x6f,0xdd,0x5b,0xfb,0x76,0x25,0x4b,0xc6,0xdd,0xf9,0x2f,0xc0,0x68,0x43,0xb8,
+  0xcc,0x87,0xde,0x7f,0x82,0x39,0xe2,0x12,0x74,0xc4,0x93,0x6c,0x1b,0xde,0xb8,0x5a,
+  0x4c,0x6b,0x88,0x7f,0x8a,0xe8,0xda,0x8d,0x19,0xfc,0x03,0xe8,0x1f,0xe7,0xe9,0x0c,
+  0x2d,0xa3,0xd0,0x64,0x6e,0xfc,0x3f,0x34,0xc2,0x7a,0xf0,0x01,0xf1,0x6a,0xd2,0x4b,
+  0x9b,0xda,0xa7,0x6d,0x9e,0x96,0x13,0xff,0x11,0x1a,0x3a,0x64,0xf4,0xbf,0x7b,0xa0,
+  0xce,0x74,0xc4,0x7b,0x20,0xa9,0x33,0xfc,0x33,0x93,0x3d,0xff,0xd6,0xce,0xa2,0x4d,
+  0xad,0xae,0xf8,0xcf,0x74,0xc4,0x3f,0x0c,0x34,0x9e,0xe0,0xc3,0xfc,0xd6,0x78,0xf9,
+  0xc7,0x0b,0xe4,0x94,0xa7,0x56,0x7b,0xfc,0x32,0xbc,0x12,0x5b,0x93,0x83,0x7f,0xea,
+  0x19,0xda,0x6c,0x65,0x78,0x40,0x08,0x60,0xa2,0x87,0x09,0x7a,0x5d,0x64,0xbb,0x4a,
+  0x0a,0x8a,0xb6,0xe8,0x5a,0xa4,0xa8,0x42,0xdd,0x97,0x85,0x7f,0x78,0xfe,0xc5,0x10,
+  0x71,0xe2,0x98,0xf6,0xe2,0x82,0x19,0x88,0x90,0x57,0x30,0xfc,0xb3,0x81,0x8a,0x87,
+  0xf2,0xf1,0x4f,0xaa,0x86,0xe1,0x01,0x33,0xda,0x33,0x06,0x1f,0xeb,0xd7,0x45,0x98,
+  0xdb,0xfa,0x18,0x7e,0xda,0xde,0xf2,0x39,0xdf,0xe1,0x9a,0xdc,0xfc,0x57,0x8b,0xee,
+  0xed,0xc4,0xf8,0x89,0xdc,0xa4,0x6f,0xc0,0xf1,0x67,0xf5,0xe7,0x16,0x96,0x8c,0x8a,
+  0x4f,0xca,0x37,0x86,0x5a,0x22,0x2b,0x0f,0x8b,0x37,0xe7,0xe2,0x1f,0x41,0xa6,0x18,
+  0xff,0x69,0xf7,0x0b,0x08,0x84,0xe4,0x41,0x9d,0xe1,0x1f,0x8c,0x25,0x0f,0x76,0x36,
+  0x24,0x3a,0x7a,0x3c,0x25,0x2e,0xfb,0x83,0xd3,0x0c,0xea,0xb2,0xea,0x67,0x13,0x97,
+  0xb4,0x05,0xe6,0x7c,0xa3,0xc1,0xd6,0x85,0x2a,0x61,0x78,0x0f,0x1a,0x22,0x4c,0xb1,
+  0x24,0x17,0xff,0x2c,0x90,0xcd,0xf8,0x9b,0xa9,0xcf,0xa2,0x3d,0xb0,0x55,0x97,0x13,
+  0x85,0x41,0xba,0x47,0x2b,0x31,0x2a,0x19,0x9e,0xcc,0xc1,0x3f,0xf3,0x6f,0xf6,0x3e,
+  0xa0,0xd4,0x4a,0x27,0x19,0xbe,0x5d,0xc2,0x03,0x3b,0x10,0x8e,0x96,0xa8,0xe2,0x63,
+  0x9b,0xbe,0x9e,0x0c,0x47,0xa5,0x47,0xda,0x56,0x38,0xf6,0x67,0xbb,0x89,0x7f,0xa2,
+  0x8d,0xfd,0xa2,0x0d,0x9c,0x08,0x0a,0xcf,0x2e,0xf7,0x25,0xbe,0xf4,0x8e,0x7c,0xb2,
+  0x27,0xdc,0xe1,0x2b,0x13,0xdf,0xcb,0xc3,0x3f,0x0c,0xe4,0x68,0x30,0x21,0x34,0x09,
+  0xa6,0xfe,0x6b,0xe7,0x61,0x46,0xac,0x06,0x46,0x8a,0x9a,0xca,0xbc,0xb4,0x3b,0x0b,
+  0xff,0x60,0x92,0x8b,0xca,0x5f,0x89,0xa1,0xe0,0xa7,0x6c,0xb7,0x3e,0x0e,0xcf,0xe9,
+  0x75,0xd4,0x93,0xf6,0x0c,0xd2,0xfb,0x63,0x5b,0x52,0x1d,0x63,0xf9,0xf8,0xe7,0x48,
+  0x40,0xf5,0x38,0xf6,0x79,0x31,0x3c,0x43,0x03,0x43,0xf2,0x5c,0x22,0x95,0x6d,0x91,
+  0x02,0xfa,0xf5,0x95,0x7e,0x8f,0x63,0x7f,0x6c,0xfc,0x23,0x23,0x0c,0x78,0x1a,0xaa,
+  0x8d,0x22,0x7c,0x7f,0x9f,0xd2,0x1f,0x1f,0xf6,0x7c,0xcd,0xf3,0x33,0x6f,0x4f,0xfc,
+  0x9a,0xd6,0xcb,0xef,0x80,0x80,0x73,0x7f,0x1b,0xff,0x78,0x57,0x89,0x33,0x98,0xfd,
+  0xd9,0x99,0x5e,0xb2,0x6a,0xda,0x5b,0xf2,0x47,0x74,0x30,0x1d,0x5c,0x25,0xce,0x91,
+  0xde,0x5f,0x73,0x43,0xb4,0x78,0x5c,0xa9,0xcb,0xc4,0x7f,0xae,0xc0,0xfd,0xe6,0x7c,
+  0x8c,0xe7,0x73,0xc3,0x32,0x64,0x09,0xcf,0x19,0x8d,0x21,0x65,0xb7,0xc4,0xfc,0x97,
+  0xee,0x4d,0xbb,0xe2,0x3f,0x88,0x7f,0x4e,0xe3,0xfd,0x27,0xc5,0x73,0xf0,0x1a,0xa6,
+  0xbd,0x50,0x38,0x4f,0xc5,0xa3,0x25,0x93,0xe2,0x73,0xea,0xf9,0xc4,0xae,0xf4,0xe2,
+  0x23,0x60,0x64,0xe3,0x1f,0xca,0x9f,0xff,0x1c,0x65,0xdb,0x28,0xc3,0xd7,0x59,0xc6,
+  0xec,0x8f,0x5a,0x3d,0x22,0xdf,0xcb,0x36,0xf2,0x4f,0x75,0x56,0x0f,0xc7,0x23,0xf0,
+  0x5e,0x26,0xbf,0x60,0xe6,0xbf,0x5e,0x92,0x3b,0x63,0x67,0xf4,0xb5,0xa4,0x9a,0x6d,
+  0xdc,0xd8,0x7c,0x77,0xb1,0x89,0xaf,0x9b,0xb8,0xf9,0x3b,0xf0,0x24,0x54,0xeb,0x45,
+  0x0b,0x88,0x91,0x8b,0x7f,0xde,0x66,0xda,0x3b,0x08,0x8f,0x12,0xcd,0xb4,0x3f,0x7b,
+  0xd4,0xad,0x46,0x47,0x68,0x4d,0x1d,0xa4,0x92,0xfe,0x4d,0x45,0x4f,0xe6,0xe5,0xbf,
+  0xe6,0xa7,0xbd,0xcf,0x32,0x7b,0xfb,0x0a,0xf3,0x5f,0x4a,0x0a,0x33,0x5c,0xb4,0x79,
+  0xa8,0x64,0xdb,0xed,0x5b,0x13,0x27,0xd3,0x4d,0xa1,0xe2,0xcd,0x62,0xe6,0x79,0x2c,
+  0xfc,0xa3,0x37,0xa2,0x1b,0x72,0x02,0x41,0xa7,0x31,0x42,0x82,0x61,0x61,0x34,0x44,
+  0x25,0x9b,0xa6,0x65,0xf2,0x2f,0x36,0xfe,0xf1,0x9e,0x79,0xf4,0x8c,0xf4,0x11,0xdb,
+  0x96,0x72,0x7f,0x77,0x56,0x9d,0x63,0x78,0x8f,0x30,0xb7,0xbe,0x9f,0x16,0x12,0x39,
+  0xdd,0x0d,0x4e,0xfc,0xa7,0x4b,0x5a,0x29,0x31,0xff,0xd5,0x29,0x3f,0x85,0x6e,0xd7,
+  0xf6,0xbf,0x7b,0xa2,0x75,0x46,0x5d,0x25,0xd9,0x0a,0x71,0x3a,0x33,0x2a,0xaf,0x23,
+  0xae,0xfc,0x97,0xe9,0xef,0xde,0x96,0xb9,0x9b,0xb3,0xc7,0x7f,0x0f,0x1e,0x1b,0xda,
+  0xfe,0xd8,0x6d,0x75,0x6a,0x9f,0x7f,0x66,0xf2,0x32,0xcc,0xd7,0xdb,0xeb,0x81,0xe3,
+  0x1f,0x8d,0xbd,0x8f,0xdc,0x2c,0x43,0x72,0x74,0x51,0xa8,0x15,0x85,0xed,0xa8,0x28,
+  0x0c,0xcc,0xd6,0xc2,0x23,0xc0,0xde,0x47,0x47,0xfd,0x98,0xff,0xba,0x26,0x6c,0x04,
+  0xd9,0x32,0x18,0x39,0xad,0x35,0x8d,0xfa,0x9e,0x6c,0x7b,0x9f,0xbd,0x2f,0xec,0xf9,
+  0x53,0xec,0x8d,0x38,0x00,0x73,0x30,0x34,0x0a,0x62,0x36,0xfe,0xb9,0x52,0x58,0x92,
+  0x16,0x8f,0x19,0xa7,0x3b,0x98,0x7f,0x3f,0x2e,0x9e,0x49,0x9e,0x87,0xe7,0x8d,0xc6,
+  0x4e,0x71,0x82,0xe3,0xe7,0x62,0xa3,0xc6,0x85,0x7f,0x0a,0xce,0xc0,0xcb,0xc0,0x96,
+  0xcd,0xbe,0x9a,0x39,0xd2,0x9b,0xed,0x2d,0xe9,0x0d,0x23,0x62,0x48,0x3b,0x08,0xd7,
+  0x6d,0x2b,0x66,0xc0,0x69,0xe4,0x4c,0x57,0x8b,0xd7,0x37,0xec,0xe2,0xff,0x50,0xf5,
+  0x18,0x6c,0xa0,0x0c,0xf6,0x74,0xc7,0xea,0xe4,0x27,0xb4,0xa6,0xb4,0x92,0x8c,0x69,
+  0xea,0x11,0xa8,0xa3,0xf2,0x3f,0x7a,0xaa,0x87,0x07,0x69,0x83,0xa4,0xac,0xf6,0xb8,
+  0xf1,0xcf,0x08,0x4f,0x2b,0x2b,0x65,0x7a,0x2d,0x24,0xb4,0x20,0xd2,0x5a,0x7a,0x52,
+  0x71,0x98,0x39,0x52,0x04,0xc4,0x50,0x99,0x69,0x92,0x17,0x11,0x97,0xfd,0x31,0xd8,
+  0x7e,0xfc,0x7b,0x50,0x37,0xa4,0x3c,0x40,0x6a,0xe4,0x1f,0x4a,0x0d,0x43,0x8b,0xb6,
+  0x92,0xc7,0xa0,0x5f,0x63,0xf7,0x8f,0x5f,0x36,0x13,0xf3,0x8f,0x51,0x11,0xf9,0x3f,
+  0xce,0xfa,0xac,0xf8,0x31,0xfc,0x9c,0x3e,0x63,0xf8,0x92,0x62,0xa1,0x34,0x7a,0x14,
+  0xdf,0x97,0xf2,0x27,0xc8,0x48,0xf7,0xec,0x78,0x71,0x5c,0xfc,0x35,0x9a,0x8e,0xbb,
+  0x7c,0x71,0xa2,0xba,0xf2,0x5f,0x3f,0x6e,0x7d,0xbf,0xff,0x3a,0xc3,0x17,0x65,0xcb,
+  0xe0,0x9c,0xda,0x8c,0x81,0xb2,0x28,0x9c,0xa2,0x2d,0x71,0xf6,0xa2,0x9d,0x09,0x9e,
+  0xd1,0x99,0xc6,0x22,0x9f,0x76,0xe7,0xbf,0xd6,0xc3,0x10,0xe2,0x73,0x0c,0x2a,0x1e,
+  0xd4,0x9b,0x0e,0xfa,0xfa,0xcb,0x6b,0xe5,0xfd,0xf0,0x07,0xc3,0x9b,0x10,0xab,0x71,
+  0xe1,0xa9,0xec,0x4f,0x67,0xe7,0xbf,0x7a,0x0d,0x3f,0xc6,0xbb,0x7e,0x03,0x7d,0xcc,
+  0x36,0x97,0x68,0xfe,0x00,0x74,0xff,0xf4,0x5e,0x83,0xed,0x37,0xaf,0x0a,0x3c,0xa3,
+  0x35,0xe8,0x45,0xdf,0x69,0xcb,0xca,0x7f,0x49,0x3c,0xdb,0x3e,0xbb,0x70,0x98,0xd2,
+  0x1e,0x6d,0x62,0x91,0x06,0x5a,0x68,0x2b,0x68,0xfb,0x18,0x1e,0x2e,0x91,0x06,0x68,
+  0x70,0x8d,0x32,0xcb,0x95,0xff,0x8a,0x2e,0x98,0x01,0xab,0x69,0x75,0x5a,0x59,0x55,
+  0xf6,0x87,0xd6,0x6e,0xa1,0x7a,0xdc,0x73,0x90,0x5c,0x06,0x8f,0xad,0xaf,0xd9,0x2a,
+  0xaf,0xa8,0x9c,0x21,0x21,0x30,0x28,0x5a,0x4a,0x8e,0x50,0x7b,0xbd,0x75,0x30,0x7c,
+  0xdd,0x25,0xa7,0x0c,0xdf,0x7c,0x66,0xf6,0x0d,0x39,0x35,0xe6,0xd3,0x44,0x6f,0xec,
+  0x6d,0x48,0x8e,0x04,0xa1,0x48,0xa0,0x1f,0x6a,0xf3,0x65,0x9f,0xdf,0x1d,0xff,0xb9,
+  0x22,0xa5,0x9f,0x1d,0x6d,0x41,0xd8,0x73,0x58,0x3d,0x1f,0x6a,0x31,0x96,0x74,0x8a,
+  0x27,0xe0,0x2d,0xb8,0x91,0x32,0xc4,0x78,0x82,0xed,0xe8,0x5b,0x70,0xab,0x9e,0xc8,
+  0x8a,0xff,0xfc,0x42,0x6f,0xc2,0xf8,0x9b,0x04,0x23,0x1a,0x17,0x02,0x70,0x88,0xe1,
+  0xf3,0xfa,0x51,0x31,0x55,0x75,0xa0,0xbb,0x19,0x0e,0x8e,0xb4,0xb9,0xf1,0x4f,0x15,
+  0xac,0x05,0x6e,0x46,0x2a,0x88,0x58,0xb1,0xc5,0x58,0xd4,0xe9,0xaf,0xaa,0x58,0xc3,
+  0x96,0xa5,0xa7,0x93,0xcc,0x87,0xb5,0x9d,0x8f,0x1a,0x9c,0xff,0x63,0xdf,0xdf,0x80,
+  0x35,0xd0,0xcd,0xe7,0xab,0xce,0x51,0xd7,0xc4,0x99,0x30,0x59,0x76,0x5f,0xed,0x77,
+  0xbb,0xaa,0xd3,0xc2,0x52,0xb2,0x11,0xfe,0x89,0x56,0x33,0x27,0xec,0xc6,0x3f,0x15,
+  0x2f,0x4a,0xdd,0x54,0x1b,0x62,0x66,0xbc,0x40,0xea,0x46,0x7b,0xae,0x7a,0x3e,0x0b,
+  0xdf,0xfb,0x49,0x30,0xed,0xa9,0x22,0x57,0x97,0x3d,0x08,0xfe,0xa8,0x5c,0xe5,0x29,
+  0x73,0xe5,0xbf,0x06,0xc9,0x81,0xad,0x03,0xd4,0x97,0x56,0xe6,0x4a,0xeb,0x68,0x13,
+  0xf5,0xad,0x14,0xbf,0x40,0xbe,0x0f,0xcd,0xa9,0x1f,0xa5,0xd7,0xee,0xd5,0xdf,0x60,
+  0x42,0x70,0x9c,0xb8,0xf1,0x8f,0xc1,0xf6,0xc8,0xc8,0x87,0x11,0x8f,0x26,0x26,0x85,
+  0x30,0x6c,0xe8,0x16,0x93,0xea,0x78,0x34,0x5c,0xe8,0xeb,0x59,0x9b,0xd6,0xc7,0x49,
+  0xb8,0x8a,0x5d,0xc9,0x8e,0xff,0xf0,0x24,0x48,0xbf,0xf8,0x65,0x78,0x85,0xcc,0xe9,
+  0xf4,0x3d,0x22,0xce,0xd4,0xf6,0xd3,0xe7,0xa2,0xde,0xcd,0xe2,0x36,0x69,0x7f,0x4f,
+  0x58,0x87,0x7e,0x31,0xe6,0xc2,0x3f,0x63,0xc8,0xf6,0xd1,0x95,0x4d,0x65,0xd3,0x42,
+  0x5d,0x06,0x13,0xfa,0xcb,0x6a,0xf5,0xde,0x4b,0x93,0x77,0xe0,0xfa,0x81,0xbe,0x48,
+  0xc3,0x52,0x79,0x73,0x61,0x76,0xfe,0xab,0x57,0x66,0x30,0x69,0xe3,0xba,0x5a,0xfd,
+  0x61,0x6d,0x66,0xe4,0x72,0xe6,0xa6,0xa1,0x17,0x4a,0x74,0x66,0x91,0xb6,0xdd,0xd5,
+  0xab,0x37,0xb4,0xcb,0x3b,0x63,0x2f,0x65,0xf8,0x24,0x20,0xdd,0xd6,0x05,0x01,0x8c,
+  0xff,0xd4,0x42,0x97,0x2e,0xe9,0xca,0xe6,0xd6,0xab,0x98,0x90,0x1c,0x8d,0x33,0x8d,
+  0x09,0x5d,0x42,0x30,0x72,0xa0,0x82,0x64,0xf2,0x5f,0x73,0xe5,0x65,0xc9,0x91,0xc0,
+  0x33,0x08,0x7b,0x34,0xf2,0x05,0xb6,0xe7,0xf7,0x51,0x45,0x63,0xf6,0x9e,0x33,0x52,
+  0x92,0x3c,0xff,0xc5,0x84,0x1f,0x67,0xf2,0x5f,0x57,0x9c,0xa0,0x67,0x61,0x8e,0xbe,
+  0xe1,0x30,0x5b,0x2d,0x27,0xf5,0x79,0x6c,0xb5,0x94,0xff,0x14,0xce,0x2e,0x60,0xcb,
+  0xe6,0x6b,0xe5,0x1f,0xab,0x1f,0x42,0x4b,0xe4,0xdb,0x87,0x3f,0xe3,0xc2,0x3f,0xd2,
+  0x18,0x3d,0x19,0x08,0xeb,0xd3,0x26,0xfc,0xb3,0xe1,0x63,0xf5,0x3a,0xfd,0x9f,0x46,
+  0xc5,0x0a,0xed,0x55,0xf9,0xab,0x7a,0x7d,0x44,0x9c,0xdd,0xfb,0x0b,0x68,0xe9,0xf0,
+  0x8e,0xae,0x9d,0xe9,0xc6,0x3f,0xc9,0x41,0x98,0x07,0x8a,0x14,0xd3,0x60,0x44,0xf5,
+  0x83,0x12,0x23,0x49,0xe4,0xff,0x10,0xb9,0x8b,0x54,0x27,0xe3,0x98,0x61,0x5f,0x23,
+  0x96,0x38,0xfa,0x07,0x69,0xd8,0xe0,0xf1,0x9f,0x1b,0x48,0xad,0xb0,0x05,0x6a,0xf5,
+  0x75,0x65,0x31,0x29,0xd0,0x25,0xd7,0xea,0x45,0x6a,0x61,0xa1,0xd1,0x05,0xc1,0x85,
+  0xb2,0x1a,0x83,0x0c,0xfe,0x29,0xfd,0x67,0x84,0x9d,0x0b,0x18,0xec,0x09,0x12,0xa4,
+  0xfd,0x2c,0x4a,0x94,0x6d,0x2b,0xed,0x5a,0xe0,0xd7,0xe5,0x81,0xb2,0x5a,0xa9,0x57,
+  0x68,0x18,0xed,0xd8,0x54,0xe6,0xc2,0x3f,0xea,0x63,0x56,0xbe,0x4f,0x91,0xf4,0x77,
+  0xb5,0x39,0x7a,0x49,0x55,0xf7,0xd5,0xb1,0xfd,0x0b,0x42,0x1d,0xcc,0x6d,0xd5,0xea,
+  0xfb,0x53,0x61,0x1e,0xff,0xe9,0x71,0xf2,0x5f,0xb0,0x8d,0x9e,0x96,0xe7,0x59,0xf1,
+  0x1f,0xf5,0x3e,0x7d,0xc3,0x66,0x71,0xb8,0xe7,0xa4,0xc4,0x60,0x4f,0xe5,0xa2,0x61,
+  0xcf,0x49,0x3a,0xff,0xaf,0x1a,0xcb,0x94,0x0c,0xfe,0xa9,0x53,0x51,0xc9,0x03,0x6c,
+  0xbd,0xbd,0xac,0x2d,0x18,0x6f,0x9d,0x03,0xde,0x58,0xf9,0x51,0x6d,0xa4,0xe3,0xde,
+  0x32,0xef,0x6a,0x31,0xda,0xc3,0xf4,0x4f,0x16,0xf7,0x94,0x2f,0xcc,0xca,0x7f,0xad,
+  0x33,0x18,0xec,0x19,0xab,0xf9,0x86,0xf4,0x96,0x5c,0x43,0xe5,0x0f,0xca,0xbe,0x0e,
+  0xf7,0xb7,0xff,0x3d,0xad,0x3f,0x46,0xe6,0x69,0x4f,0xa8,0x8d,0x5d,0xf2,0xb8,0xe2,
+  0xc9,0xca,0x7f,0xb1,0xf7,0xc5,0x60,0x3f,0xaa,0x42,0xf7,0xd0,0x5a,0x5a,0x19,0x98,
+  0xf9,0x0a,0x6c,0x14,0x34,0xb6,0x63,0x8d,0x15,0xa8,0xdd,0x87,0x83,0x77,0x54,0x96,
+  0x91,0x0c,0xfe,0xa9,0x16,0x66,0xd0,0xb5,0xf1,0x6a,0xa3,0x4f,0x27,0x95,0xd2,0x5a,
+  0xa1,0x3a,0x2a,0x47,0xc8,0x7f,0x15,0xbe,0x03,0xd5,0xa3,0x45,0x9d,0x75,0xed,0xd2,
+  0x3f,0x33,0x68,0xbd,0xf4,0x0e,0xd2,0xd1,0xee,0xdc,0x5f,0x6e,0x81,0x17,0xe8,0xac,
+  0xb4,0x0f,0xf9,0x8a,0xbb,0x63,0xd7,0x46,0x19,0x10,0x7a,0x03,0xde,0xa2,0x8f,0xa6,
+  0xbd,0x2b,0xc4,0xdb,0xe0,0xa5,0x9e,0x16,0x2d,0x38,0x22,0x7a,0x0a,0xed,0x9f,0x8b,
+  0xe1,0x1f,0x72,0x6a,0x05,0xc6,0x37,0x3e,0x6d,0xc0,0x33,0x30,0x57,0x6f,0x4c,0x88,
+  0xc7,0x0a,0x7f,0xb7,0x82,0x69,0x38,0x29,0xa6,0x2e,0x79,0x63,0x05,0xdb,0x7f,0x19,
+  0xec,0x7d,0xb1,0xf5,0x83,0xf9,0xaf,0x83,0x08,0x7b,0xb6,0xb7,0x1d,0x97,0xf7,0x27,
+  0xc2,0xdb,0xc8,0x60,0xcd,0x3c,0x86,0xb8,0x9a,0x19,0x22,0x2a,0x0f,0x47,0x5e,0xdb,
+  0xd8,0x32,0xee,0x9b,0x9c,0x96,0xc8,0xc2,0x3f,0x6b,0xd0,0xfe,0x54,0xfa,0x7f,0x96,
+  0xf8,0xb7,0xed,0xc1,0x15,0xf2,0x7b,0xa4,0xb2,0xe3,0x49,0xed,0xc6,0x8e,0xc0,0x3d,
+  0xeb,0x66,0x1f,0x78,0x51,0xad,0x6f,0x55,0x3a,0xa7,0x3d,0xe1,0xc2,0x1b,0xeb,0x61,
+  0x35,0x5c,0x65,0x28,0x7a,0xe1,0xe1,0x44,0x8f,0x56,0xaf,0x7b,0x6e,0x8b,0x8d,0xc2,
+  0xf7,0x85,0x6b,0x10,0x41,0x55,0xaa,0xdf,0x29,0xaf,0x8f,0xf7,0x2d,0x60,0x08,0xd6,
+  0xd6,0x7f,0xb4,0xe2,0xa0,0x10,0xc3,0x6d,0x6c,0x82,0xbc,0x0c,0x1b,0x0d,0xe6,0xe8,
+  0x2b,0x2e,0x3b,0xaa,0xed,0xea,0x6a,0x50,0xe5,0xd9,0x85,0x1e,0xbd,0x4b,0x0a,0x26,
+  0x94,0xed,0xfe,0x7e,0xe7,0x7d,0x0f,0x4c,0x7f,0x96,0xbc,0x02,0x4f,0xa1,0xff,0x7a,
+  0xbb,0x77,0x64,0x38,0xac,0x7b,0x52,0xe2,0xef,0xb4,0x37,0xb4,0x3a,0x23,0xb8,0x47,
+  0xbc,0x4a,0xfe,0x45,0x6b,0x38,0xaa,0x6c,0x16,0xef,0xcf,0xc2,0x3f,0x6c,0x3f,0x65,
+  0x6c,0xd8,0x54,0x93,0x16,0x4e,0x69,0xe1,0x88,0x2f,0x45,0x02,0x0c,0x78,0xcf,0x18,
+  0x41,0xe2,0x01,0x3d,0x29,0x84,0x5b,0x97,0x7c,0xf7,0x53,0xc9,0x2c,0xfc,0x73,0x9a,
+  0x9a,0xf1,0x1f,0xed,0x8c,0xd0,0xb2,0xc0,0x67,0x74,0xcf,0x65,0xf6,0xf9,0x3a,0xc3,
+  0x7b,0x82,0xfd,0xa8,0x87,0xe4,0x1b,0xc1,0x6b,0x88,0xb5,0xcb,0x9d,0xfc,0x97,0xb4,
+  0x12,0x98,0x13,0xc7,0xe7,0x17,0x49,0x9c,0x36,0x74,0x2e,0xba,0x44,0xfc,0x9b,0xd9,
+  0xdd,0x68,0x36,0x43,0xe5,0x5b,0x61,0x1d,0x34,0x84,0x56,0x3c,0x42,0x42,0x59,0xf8,
+  0x67,0x50,0x63,0xe3,0x93,0xb1,0x99,0x9e,0x67,0x5e,0x68,0xb8,0xa3,0x77,0x67,0x59,
+  0x00,0xfa,0x84,0x86,0x34,0xdb,0x7f,0xfd,0x18,0xc7,0x63,0xa8,0x24,0x1b,0xff,0xa4,
+  0x30,0xfe,0x53,0xe3,0xa9,0xad,0x8e,0xc9,0xc1,0x0e,0x65,0x63,0xac,0xa3,0xac,0x4b,
+  0x0a,0x18,0x81,0x10,0x89,0x11,0xca,0x76,0xe3,0x83,0x59,0xf8,0xc7,0x1b,0x44,0x3e,
+  0x24,0xf3,0xbf,0xdd,0xb5,0x74,0x12,0x1a,0x3a,0x8a,0x07,0xca,0x35,0xf6,0xfc,0xf7,
+  0xa1,0xff,0xad,0x95,0x47,0x30,0xf5,0x4c,0x6b,0xb4,0x2c,0xfc,0x73,0x06,0xc3,0x1a,
+  0xaf,0xb7,0x0d,0x93,0x73,0x70,0xe3,0xcd,0x7d,0x46,0xf9,0x04,0x9c,0x17,0xae,0x05,
+  0x5f,0x84,0xe1,0x3d,0xa6,0x01,0xce,0xff,0x71,0xe1,0x9f,0xe3,0x70,0x30,0x31,0xab,
+  0xd6,0x7b,0xa7,0xf8,0xe9,0x8a,0xf3,0xc1,0x1b,0x0c,0x0b,0x3f,0x5f,0x9f,0x2e,0x7e,
+  0x01,0xf9,0xcf,0xa1,0x66,0xc9,0xf7,0x42,0x4d,0xc8,0xc9,0x1f,0x19,0xaa,0x81,0x24,
+  0x16,0x41,0xde,0x48,0x64,0x78,0x5e,0xaf,0x49,0x97,0x0c,0x92,0x0f,0xd4,0xbd,0x0c,
+  0x11,0xc9,0x6b,0xc8,0xdb,0x80,0xf9,0x2f,0xa5,0xa7,0x35,0xe3,0x8f,0x46,0x0a,0x0c,
+  0x6d,0x6b,0xf5,0x8a,0xb8,0x5c,0x46,0x46,0x1e,0x30,0x13,0x3d,0x1c,0xf8,0xd5,0x41,
+  0x51,0x69,0xd9,0x4b,0x6a,0x8a,0xe1,0xbd,0x45,0x97,0xb4,0x36,0x09,0xf6,0x78,0x63,
+  0x7a,0x92,0xd9,0x88,0xba,0x2e,0xb9,0x92,0x6d,0x5b,0x76,0x31,0x3c,0xe9,0x49,0x99,
+  0x40,0x14,0xe4,0xed,0x24,0x4d,0xf7,0x1a,0x33,0xef,0x52,0xe2,0xfe,0x4c,0xfe,0xcb,
+  0x98,0xfe,0x0e,0x1b,0x38,0x0f,0x69,0x81,0xe3,0x66,0x20,0x11,0xf1,0xf0,0x47,0x64,
+  0xee,0x89,0xe2,0x75,0xe2,0x38,0x9c,0xa4,0x73,0x42,0xbe,0xf5,0x8a,0xaa,0x67,0xf2,
+  0x5f,0x4f,0xe9,0x6f,0xca,0x4f,0xe3,0x4b,0x34,0x97,0x01,0xc5,0xb0,0x31,0xcd,0x22,
+  0x02,0x61,0xc4,0xf5,0xb8,0xfa,0xb1,0xb4,0xb7,0xcb,0x47,0xa7,0x8d,0x3b,0xeb,0xed,
+  0x30,0xb3,0x6f,0x07,0x84,0x26,0x1a,0x44,0xda,0xc3,0x2b,0xec,0xfe,0x4b,0x52,0x35,
+  0x88,0xd8,0xe7,0xa8,0xc5,0x54,0x0c,0xc2,0x64,0x47,0xd3,0xed,0xde,0xc7,0x14,0x77,
+  0xfc,0x67,0x26,0xac,0x8b,0x37,0xc5,0xe5,0xb5,0xad,0x01,0x66,0xb4,0x6a,0x38,0x7f,
+  0x4c,0xdd,0x2b,0xf8,0xe5,0xed,0xdf,0x66,0xcb,0x60,0x0f,0xdd,0x7a,0xbb,0xbc,0xde,
+  0xc5,0x7f,0x4e,0x0b,0x7f,0xa3,0xa1,0xbf,0x0b,0x84,0x3c,0xb2,0xf4,0xa0,0x80,0xfc,
+  0x43,0xf6,0xc6,0xed,0x8a,0xd7,0xbe,0x5e,0x54,0x4d,0xc4,0xe8,0x40,0x42,0x4b,0xc8,
+  0x3f,0x22,0xf3,0x32,0xfc,0xe7,0xa1,0xcb,0xe0,0xdb,0x94,0x99,0x9d,0xd3,0x0c,0xf6,
+  0x3c,0xc8,0x80,0xc1,0x2d,0x26,0x1f,0x66,0xd9,0x58,0xe5,0x2a,0xb6,0xd5,0x7a,0x32,
+  0xc1,0xf0,0xc0,0x7f,0x69,0x9d,0xef,0xca,0x7f,0xc9,0xf0,0xc2,0x50,0xc8,0x08,0xce,
+  0x15,0x3d,0xf4,0x5f,0x31,0x11,0x76,0x83,0xb8,0x1e,0x3e,0x92,0xbf,0x66,0x14,0xab,
+  0xa2,0x24,0x9c,0x52,0x9b,0x74,0xef,0xf4,0x69,0x99,0xa2,0x82,0xd6,0xe2,0xc1,0xd6,
+  0x3f,0xc2,0x79,0x5c,0x06,0x93,0xad,0xbf,0x67,0xfa,0x29,0x41,0xfd,0xfc,0xd1,0x0a,
+  0x94,0x15,0x9c,0x57,0x5b,0xda,0x37,0xfc,0xc4,0x95,0xff,0x7a,0x82,0xe1,0x9f,0xfd,
+  0xb8,0x08,0x93,0x62,0x9d,0xf0,0xca,0xe7,0xe6,0xbc,0x7d,0xbf,0xb9,0x31,0x99,0x6f,
+  0x94,0x8c,0x2a,0x75,0xc0,0x7e,0x6a,0xba,0x78,0xa2,0xdc,0x95,0xff,0x7a,0x60,0x33,
+  0xb3,0x27,0xf5,0x7a,0x47,0xda,0x33,0x17,0x5e,0x0e,0x68,0x23,0x5e,0x1e,0xff,0xc1,
+  0x1d,0x65,0x84,0x5c,0x31,0xf2,0x53,0xa8,0xa6,0x4c,0xc8,0xce,0x7f,0xfd,0x80,0x36,
+  0xa6,0x19,0xc8,0xb9,0x0c,0xba,0x63,0x57,0x8d,0x79,0x2c,0xfe,0x0f,0xe2,0x99,0x30,
+  0xd0,0x58,0x6d,0x94,0x6d,0xb5,0xdc,0xf9,0xaf,0x63,0xf0,0x28,0x7b,0x5f,0x18,0x7a,
+  0x94,0x99,0xa0,0x21,0xb1,0xf3,0xa0,0xcc,0x19,0x9e,0xfd,0x7e,0xaf,0xf4,0xf0,0xc4,
+  0xcc,0xc8,0xf6,0x8d,0xad,0xee,0xfc,0xd7,0xe3,0xe4,0x3d,0x08,0x53,0xf6,0xfc,0x73,
+  0x71,0x37,0x41,0x4b,0x92,0x22,0xc6,0x7f,0x6e,0xa4,0x25,0xbf,0x41,0x20,0xa7,0x5f,
+  0x97,0xf4,0xbe,0xa7,0x64,0xe5,0xbf,0x34,0xe4,0x03,0x37,0x1e,0x2c,0x4f,0x83,0x61,
+  0x12,0x33,0xcc,0x6d,0x97,0xaf,0x87,0x07,0x46,0xe6,0x5d,0xe1,0xcb,0xce,0x7f,0xbd,
+  0x63,0xd1,0x7a,0x39,0x3f,0x04,0x1d,0x9f,0xc0,0x19,0xce,0xd1,0xe2,0x7e,0xbc,0xa2,
+  0x97,0xad,0x60,0xfe,0xd1,0x9d,0xff,0xfa,0x6b,0xe8,0xa2,0xfe,0x88,0xfc,0x90,0xa7,
+  0xd6,0x15,0xcf,0xd1,0x1a,0xa2,0xf2,0xf7,0x5b,0x83,0xf2,0x1e,0xdd,0xdf,0x29,0x6f,
+  0xf6,0x64,0xe5,0xbf,0xf4,0x6f,0xd3,0x4f,0xbf,0xcc,0x94,0x56,0x2b,0x5b,0xf1,0x22,
+  0x9e,0x41,0x1b,0x2e,0x7a,0x00,0x23,0x18,0x7a,0x9d,0x2e,0x7f,0xc7,0x95,0xff,0x02,
+  0xe9,0x53,0xb0,0x5a,0xaf,0x8e,0xc8,0x77,0x90,0x02,0x98,0xb5,0x40,0xd3,0x17,0xf1,
+  0x78,0x08,0xa0,0xa1,0x26,0x12,0xec,0xd4,0xd3,0x91,0x78,0x45,0x99,0x3b,0xff,0xa5,
+  0x33,0xb5,0xcc,0xc3,0xf8,0x0f,0xf2,0x4f,0xe6,0x21,0x10,0x32,0x23,0x42,0xc5,0x0c,
+  0x08,0xe1,0x15,0x7c,0x35,0x32,0xf9,0xaf,0x23,0x57,0x8c,0x91,0x93,0xf0,0x2c,0x86,
+  0x7d,0x10,0xff,0x30,0xfb,0x9c,0x10,0xc7,0xd4,0x93,0xb8,0x7e,0x0e,0x2b,0xc3,0xf2,
+  0xf9,0xd6,0x96,0xc8,0x92,0xac,0xfc,0x57,0xf1,0x09,0x78,0x15,0x9a,0x75,0xef,0xe1,
+  0xb6,0x5a,0x75,0xbf,0xb7,0xa9,0x95,0xc7,0x8b,0x10,0x66,0x17,0xff,0xa4,0x3b,0x08,
+  0x67,0x3b,0x9a,0x97,0x66,0xf1,0x9f,0x57,0x41,0x1a,0xed,0x0f,0x74,0xc4,0x88,0x26,
+  0xc7,0x75,0xbf,0x6a,0x26,0xc2,0x48,0x03,0xc8,0xdb,0x30,0x22,0x14,0xf5,0x43,0x60,
+  0xcd,0xba,0xac,0xf8,0xcf,0xd6,0xae,0x80,0xb6,0x30,0xae,0x92,0x5a,0xad,0x2b,0x10,
+  0xd0,0xfb,0x54,0x3f,0xce,0xb7,0xc1,0x28,0x2a,0xc3,0xf9,0x82,0xb6,0x54,0x2e,0x25,
+  0xee,0xfc,0xd7,0x7a,0x86,0x1e,0x31,0xda,0xc3,0xb4,0xd7,0x2b,0x38,0xf1,0xb7,0x06,
+  0xc4,0x93,0x57,0xe1,0x2f,0x12,0xc9,0xe3,0x3f,0xef,0xa7,0x4d,0x3a,0x73,0x6b,0x12,
+  0xd9,0x0f,0xcf,0x20,0x5f,0xcb,0x0c,0xec,0x14,0xf7,0x2b,0xec,0xf7,0xa5,0x5b,0xa3,
+  0xcc,0x50,0x67,0xe5,0xbf,0xb4,0x93,0xc1,0xf0,0xf2,0x0d,0x88,0x7f,0x3e,0x64,0x40,
+  0xd1,0x67,0x8d,0xef,0xf4,0x95,0x62,0x60,0x30,0x30,0x7f,0xa1,0xaf,0x52,0xcc,0xca,
+  0x7f,0x49,0x23,0x02,0x46,0xdb,0xba,0x99,0xb6,0x9d,0xf8,0x0f,0x84,0x43,0x5e,0x5a,
+  0xae,0xcd,0x46,0xe2,0xbd,0x97,0xba,0xf3,0x5f,0x37,0x5d,0xef,0xbf,0x9f,0x36,0x0e,
+  0xca,0xe3,0x24,0x00,0xcf,0x08,0x76,0xfc,0x07,0xea,0xa9,0x67,0xec,0x89,0x6b,0xe0,
+  0x39,0xb9,0x31,0x16,0x18,0x3b,0xe0,0x8e,0xff,0x7c,0x16,0xfa,0x8c,0x86,0x71,0xf9,
+  0x49,0x1e,0x9f,0x07,0xdb,0x3e,0xb3,0xf7,0x65,0x06,0x29,0xd6,0x77,0xea,0xc1,0xa8,
+  0x7c,0x19,0xc3,0x3f,0x99,0xfc,0x57,0x05,0xac,0x91,0x1b,0x8d,0x80,0x1d,0xff,0xe1,
+  0xf1,0x90,0x27,0x8b,0xea,0x0d,0xb6,0x7f,0xa9,0xb0,0x5f,0xe4,0x40,0x26,0xff,0x45,
+  0xe7,0xc1,0x30,0xbd,0x31,0xea,0x1d,0x57,0x66,0x24,0x3f,0xda,0x8e,0x40,0x48,0x7c,
+  0x0b,0xfe,0x80,0x11,0x9b,0x11,0x71,0x06,0x7c,0x4c,0x5b,0x34,0x26,0xd4,0x65,0xf8,
+  0xcf,0xd3,0xb7,0xb1,0xb7,0x6f,0xbe,0xce,0xa6,0xc9,0xcc,0x08,0x79,0xce,0x8a,0xb7,
+  0xb3,0x2b,0x8d,0x46,0xcd,0x98,0x76,0x16,0xf9,0xcf,0x46,0xb9,0x8b,0xff,0xcc,0xf0,
+  0xcf,0x21,0x44,0x3b,0x47,0xc4,0x19,0xda,0x6b,0xf1,0xeb,0xd2,0x1b,0x4e,0x72,0xff,
+  0xd5,0x92,0xf4,0x1e,0x69,0x3b,0xa7,0x9f,0xa1,0x2d,0x18,0x7f,0x36,0x1c,0xfd,0x3f,
+  0x5e,0xda,0xcf,0xd6,0x4f,0x4d,0xbb,0x4c,0x63,0x6c,0x23,0x96,0xaa,0x1e,0xf7,0x85,
+  0x2c,0xfb,0x53,0xdc,0x49,0x8e,0xc0,0x53,0x50,0x3f,0xc2,0x80,0xcd,0x7b,0x3d,0xf6,
+  0xfd,0xb1,0x00,0xa9,0x07,0x8d,0x12,0xdf,0x9d,0xc1,0x55,0x23,0x97,0x77,0xce,0x7c,
+  0x13,0x87,0x51,0xb9,0x9d,0xfd,0xc3,0xdd,0x50,0x2f,0xc8,0x7a,0x56,0xfc,0x07,0xd7,
+  0xa7,0xc6,0xf6,0x19,0xc4,0x0b,0x7d,0x60,0xc5,0x7f,0x38,0x23,0x5a,0x63,0x40,0xe7,
+  0x99,0x24,0x53,0xec,0xf5,0x31,0x77,0xfc,0x27,0x48,0x0e,0x90,0x01,0xc3,0xbb,0xbb,
+  0x6d,0x3e,0x79,0x0d,0xe6,0x18,0x8a,0x1d,0xd8,0xf1,0x3e,0x52,0xf3,0x2e,0x9c,0x34,
+  0xc2,0x77,0x05,0xfb,0x5d,0xfc,0x49,0x0a,0xef,0x63,0x74,0x5a,0x67,0x46,0xc6,0x22,
+  0x42,0x9b,0xfa,0x09,0x8f,0xfa,0x52,0x9f,0x19,0xbb,0x63,0x6f,0x24,0xfc,0x3a,0x5b,
+  0x5a,0xee,0xfc,0xd7,0x09,0x38,0x64,0x34,0x1b,0x81,0x0f,0xbb,0xe7,0xb3,0xdb,0x5e,
+  0x67,0xc6,0x7f,0xce,0x21,0xc3,0xc1,0x10,0x27,0xab,0xdf,0x27,0x4d,0xe8,0x0a,0x75,
+  0x67,0xbf,0xdf,0x25,0x7d,0x99,0x81,0x16,0x2d,0x2a,0xc7,0x38,0x9f,0xc7,0x8c,0xe7,
+  0x48,0x7b,0xb0,0x2c,0x62,0x33,0xf9,0x4d,0xd7,0x60,0x8f,0x3f,0xa4,0xc4,0xcb,0xd2,
+  0x2e,0xfc,0x13,0x68,0x8d,0xcb,0x75,0xe9,0xba,0x10,0x09,0xaa,0x7b,0x0b,0x67,0x1a,
+  0x7d,0xa6,0xbf,0x6e,0xd8,0x77,0x0d,0xf2,0x75,0x07,0x7b,0xfd,0x77,0x29,0x83,0x6b,
+  0xdc,0xf9,0x2f,0x99,0xcd,0x61,0xbb,0xee,0x61,0xfa,0xd1,0x9b,0x41,0x1b,0x51,0x66,
+  0xdb,0xeb,0x0d,0x98,0x1a,0x77,0xb2,0x07,0x5f,0x04,0x64,0x9f,0x2b,0xfe,0xa3,0x4b,
+  0x23,0x64,0x1e,0x2d,0xd9,0xa9,0xcc,0x87,0x6f,0x69,0x97,0x60,0x98,0xeb,0x18,0x9c,
+  0x22,0x61,0xa3,0x18,0x5f,0x84,0x71,0xdc,0x1a,0x50,0x51,0x77,0xec,0xcf,0xd6,0xe2,
+  0x09,0x38,0x23,0x5f,0x07,0xf5,0xfb,0xc4,0x33,0xf4,0xb4,0x1e,0x1e,0xf6,0x4d,0xb4,
+  0x9d,0xe1,0x19,0x0d,0x9f,0x51,0x33,0x61,0xf1,0x9f,0xdb,0xc6,0xd7,0x64,0xf3,0x7f,
+  0x6e,0x48,0xb3,0x9b,0x84,0xe8,0x7e,0x18,0x10,0x16,0xf7,0xd6,0x84,0x8c,0xd7,0x70,
+  0x59,0x4e,0x8a,0xe7,0xe1,0x60,0xa0,0xa5,0x72,0xf1,0x48,0x5b,0x16,0xff,0x99,0xf3,
+  0x7f,0x94,0x1d,0x44,0x5a,0xf1,0x6d,0xd8,0xaa,0x79,0xb6,0x12,0x8d,0xf6,0xd1,0x86,
+  0x68,0xfd,0x60,0xeb,0x31,0x35,0xae,0x35,0x14,0xc9,0x71,0x92,0xce,0xcd,0x7f,0x19,
+  0xca,0x96,0x99,0xdb,0xa1,0x4b,0xd0,0x8c,0x75,0x1a,0x59,0x0d,0xdd,0x98,0xe1,0x0a,
+  0x31,0x45,0x3d,0x18,0x68,0xa8,0x64,0x1b,0xdb,0x58,0x2e,0xff,0x79,0x48,0xd9,0x4e,
+  0x76,0xd4,0xb2,0xfd,0xd7,0x81,0x85,0x5b,0x62,0xdb,0x68,0x9f,0xd4,0xd0,0x59,0xc4,
+  0x14,0x4b,0xe3,0x66,0x68,0x7a,0x22,0x27,0xff,0xc5,0x96,0xc1,0xf6,0x2f,0x75,0x91,
+  0xfd,0xc6,0x00,0x78,0xb6,0x89,0xbd,0x6c,0xa1,0xcd,0x4b,0x7b,0x53,0xe2,0x07,0xe2,
+  0x88,0x16,0x4e,0x04,0xb7,0x8a,0x89,0xec,0xfc,0x17,0xb4,0xec,0xf3,0x19,0x8f,0x7e,
+  0x4b,0x3e,0xa9,0xdf,0xa8,0xb1,0x8d,0xff,0x37,0x34,0x76,0x85,0xb2,0x85,0x31,0x29,
+  0x7d,0xb3,0xb5,0x25,0xe1,0x7b,0xbb,0x3c,0x2f,0xff,0x85,0xfc,0x9f,0x24,0x79,0x25,
+  0x3a,0x60,0xf8,0xe2,0xcd,0xf5,0x48,0x74,0x89,0xb0,0xfb,0x1f,0xd3,0xdf,0x50,0x9b,
+  0xee,0x64,0x42,0x36,0xff,0xe7,0x7b,0xd0,0xf0,0xae,0x32,0x97,0xac,0x94,0xfb,0xa2,
+  0xfe,0xe1,0xe2,0x41,0xb6,0x90,0xfa,0x20,0x08,0xcc,0x7e,0xbe,0x06,0xf1,0x51,0xad,
+  0x53,0x1e,0x20,0xc7,0x73,0xf3,0x5f,0x86,0x22,0x17,0x52,0x29,0xde,0xa5,0xa5,0x3e,
+  0xfd,0x14,0x29,0x66,0xfa,0x09,0x02,0x8f,0x10,0x52,0x4c,0x0c,0x11,0x32,0x99,0x93,
+  0xff,0xaa,0x4f,0xf7,0xdd,0x72,0xd7,0x17,0xa1,0x67,0x6b,0xcd,0x8e,0x4b,0x97,0x7a,
+  0x66,0x68,0x6b,0xe9,0x7f,0x8b,0xca,0xab,0x5a,0xcf,0xab,0xab,0x69,0x75,0x52,0xee,
+  0x28,0x3c,0x92,0xc3,0xff,0x99,0x6f,0x6c,0x08,0x88,0x94,0x6d,0xc4,0x42,0x4f,0x5c,
+  0x39,0x57,0xac,0x27,0x2f,0xc0,0x7c,0x08,0x86,0xc4,0x83,0xf0,0x73,0x74,0xcd,0x5a,
+  0x56,0xfc,0xe7,0x59,0xf8,0x15,0x7a,0xab,0xa3,0xe2,0x2a,0xfd,0x34,0xb9,0xb1,0x67,
+  0xc9,0x3d,0xfc,0x7d,0xbc,0x11,0x98,0x7e,0xde,0xd4,0xcf,0xaa,0x2d,0x7a,0x63,0x5a,
+  0x1c,0x25,0xb6,0x7e,0x1c,0xfe,0x0f,0x5b,0x84,0xc2,0x90,0x1c,0xea,0x2a,0x4e,0x55,
+  0xaf,0xe4,0xf8,0x07,0xf5,0x03,0xbf,0xc7,0x0a,0x92,0x4d,0xae,0x78,0xbe,0xc3,0x7f,
+  0xd6,0xfd,0x15,0x0c,0x08,0x55,0xd3,0xc0,0x04,0xa9,0x92,0x9e,0x96,0xea,0x01,0xed,
+  0x8f,0xbc,0x9a,0xe3,0x9f,0x29,0xf8,0xcf,0xdf,0x9b,0x9c,0x19,0x9e,0xbd,0x81,0x3e,
+  0x9a,0x94,0x57,0x14,0x62,0x05,0x5c,0x63,0x48,0x5e,0x45,0xfe,0x80,0x44,0xa0,0xa8,
+  0xfc,0x75,0x92,0xcb,0x7f,0xf6,0x0e,0x31,0xfd,0x37,0x40,0xf7,0x5d,0xc9,0x2e,0xb9,
+  0x3f,0x16,0x84,0x5d,0x24,0x58,0x59,0x14,0x22,0x2f,0x31,0xd7,0x96,0xbc,0x93,0x29,
+  0xf6,0xf5,0x02,0x7b,0xbc,0xc9,0xff,0x99,0x41,0xd9,0xfe,0xe8,0x86,0xc2,0xfb,0x17,
+  0xcc,0xa2,0x1d,0xe3,0x2f,0xac,0x92,0x11,0xff,0x30,0x44,0xf4,0xf3,0xea,0x1f,0x1b,
+  0xcd,0x29,0xef,0xb6,0x2c,0xfe,0x33,0xf7,0x3e,0xaa,0xaf,0xeb,0x86,0x2d,0xd2,0xa4,
+  0xca,0xf0,0x4f,0x0f,0xe7,0x3f,0x23,0x43,0xa6,0x2d,0xdd,0x3d,0x59,0x19,0x56,0x1b,
+  0x69,0x77,0x1e,0xff,0x07,0xab,0x7b,0x96,0x6b,0xfb,0xd5,0x81,0x8e,0xe2,0xcd,0x35,
+  0xb5,0xfa,0x7e,0x93,0x31,0xfb,0x8e,0xb4,0x3f,0x19,0x5a,0xee,0x7d,0x04,0xf2,0xf8,
+  0xcf,0xb7,0x29,0x9b,0x63,0x57,0xf7,0xf4,0x8e,0xd4,0xe9,0xc5,0x0f,0x61,0xda,0x8b,
+  0xf9,0x5f,0x4f,0x02,0x0b,0x01,0x64,0xe6,0x9a,0x07,0x49,0x3a,0x9f,0xff,0xd3,0x4f,
+  0xbe,0xcc,0x96,0x8d,0x5f,0xff,0x2f,0x89,0xb2,0x5a,0xed,0x61,0x93,0xb8,0x3b,0xa6,
+  0xf7,0x62,0x05,0x47,0x82,0x4d,0xdc,0x5e,0x0f,0x0e,0xff,0x47,0x2d,0x2c,0x20,0x5d,
+  0x0c,0x1d,0x15,0x55,0x90,0x02,0xf2,0x00,0xde,0x5f,0x25,0xbf,0xa9,0xe8,0x6a,0xd7,
+  0x22,0x01,0x95,0x64,0xe7,0xbf,0x4c,0xfe,0x8f,0x18,0xc5,0xb2,0x23,0x13,0xf6,0x60,
+  0xd9,0x05,0x73,0xbb,0xe3,0x30,0xc2,0xb6,0x06,0x72,0x72,0xaa,0xfc,0xd7,0xd7,0xca,
+  0xcf,0xc2,0x59,0xbd,0x25,0x72,0x2b,0xa6,0xbd,0xde,0xc5,0xb0,0x61,0xa2,0xfc,0x70,
+  0x21,0x5e,0x61,0x1e,0xdf,0x8d,0x7f,0xac,0xf1,0x1b,0x93,0xbb,0xb7,0xbd,0x1a,0x6d,
+  0xee,0xe8,0x89,0x90,0xd9,0x81,0x5e,0x76,0x45,0x46,0x04,0xf5,0xfe,0x5d,0xcd,0xed,
+  0xc1,0x94,0xbb,0xfe,0x0b,0x30,0xff,0x55,0x02,0xca,0x30,0x39,0x0a,0xf1,0xe8,0xd6,
+  0x44,0x09,0x25,0x49,0x1a,0x17,0x1a,0xd8,0x83,0x89,0xc9,0x64,0x5c,0xf3,0x57,0xac,
+  0xa7,0xe4,0xfe,0xec,0xfc,0x17,0xc3,0xdb,0x4a,0x84,0x6c,0x6b,0x7a,0x40,0xd7,0x22,
+  0x95,0x6a,0x6c,0x8d,0xd6,0x05,0x77,0xeb,0xb2,0x5a,0x36,0x26,0x6c,0x59,0x5e,0xdb,
+  0x21,0xf7,0xe7,0xe6,0xbf,0x84,0x46,0x5d,0x19,0x9d,0x39,0x46,0x1f,0xfe,0xbc,0x5f,
+  0xf7,0x6c,0x2a,0xdb,0xc6,0xf5,0x5f,0x94,0x20,0x3f,0x8a,0xf5,0x46,0x67,0x46,0x8a,
+  0x12,0xb0,0x26,0x9f,0xff,0xf3,0xc0,0xed,0xdb,0xe0,0xe7,0x6d,0xa1,0x68,0xb0,0x4a,
+  0xfc,0x67,0x06,0x84,0xe6,0xb7,0xb2,0xdf,0x77,0x58,0x78,0x57,0x7f,0x6a,0xb9,0xb7,
+  0x52,0x08,0xe4,0xe6,0xbf,0x5a,0x7d,0xfd,0xdd,0x63,0xea,0x51,0x6f,0xb8,0x63,0xc3,
+  0x46,0x2c,0x8b,0x2b,0x64,0xf8,0x27,0x21,0x6e,0x53,0x3f,0x8c,0x3f,0x13,0x2d,0xd9,
+  0x98,0x97,0xff,0xba,0x4f,0x42,0xd8,0x43,0x99,0xfe,0xa5,0xfb,0x7b,0x1e,0xd5,0xe2,
+  0x6c,0xdb,0x2b,0x4c,0xa3,0xe2,0x51,0x3a,0x0e,0x4d,0x32,0xfb,0x21,0xf2,0xea,0xbf,
+  0x12,0x7d,0x3b,0xd4,0x23,0xe4,0x7e,0xe1,0xd3,0x34,0x7e,0x4c,0x5c,0x25,0xaf,0x13,
+  0x1a,0x10,0x08,0x9d,0xf2,0xdf,0x0f,0x35,0x49,0x6f,0xb2,0xf5,0x40,0x6e,0xfe,0x2b,
+  0xaa,0x5c,0x41,0x0e,0x62,0xbc,0xf4,0x5d,0x25,0x08,0x4b,0xe4,0x6e,0x58,0xc9,0x80,
+  0x50,0xeb,0x8b,0xe4,0x01,0x83,0xe1,0xed,0x10,0x39,0x90,0x97,0xff,0x62,0xb0,0xe7,
+  0x97,0xd2,0x5a,0xe9,0xd3,0x0b,0xe4,0x13,0x65,0xff,0x15,0xd6,0x0a,0x9c,0x11,0x7d,
+  0x18,0x36,0xe9,0xd5,0xad,0x0c,0x2a,0x8c,0x67,0xf2,0x5f,0x80,0xf9,0xaf,0xfa,0xb4,
+  0x6f,0x85,0x78,0xce,0x3b,0x44,0x77,0x46,0xff,0x72,0x55,0xcd,0xad,0x64,0x2d,0x32,
+  0x82,0x90,0xff,0xf3,0x2b,0xba,0x2b,0x1a,0x5c,0xd1,0xfd,0x5e,0x26,0xff,0x65,0xd6,
+  0x43,0xe9,0x3e,0x74,0xbb,0xa7,0xc5,0xf9,0x0b,0x4a,0x12,0xe2,0xb8,0x9d,0xe8,0x39,
+  0x01,0x1f,0x20,0x11,0xfa,0xa1,0x9c,0xfc,0x17,0x43,0x3b,0xeb,0xab,0x06,0xcb,0xcf,
+  0x49,0xe7,0x1e,0x98,0xb5,0x52,0x9b,0xac,0x39,0x0e,0xaf,0xd1,0x2b,0x31,0x23,0xf6,
+  0x06,0xbc,0x48,0x9b,0x93,0x6c,0x2b,0x97,0x93,0xff,0x92,0x18,0x48,0xfb,0xcb,0xdb,
+  0xde,0xa4,0x4f,0x37,0x57,0xdf,0xe4,0xbd,0x99,0xfc,0x72,0xfd,0x5a,0xd5,0xc4,0x3f,
+  0xa4,0x47,0xaf,0xa6,0x6c,0x6a,0xb9,0xf9,0xaf,0x46,0xa3,0xbf,0xb3,0x2c,0x21,0x3d,
+  0x09,0xd5,0x1d,0x72,0xe7,0xeb,0x47,0x18,0x10,0x6a,0xdc,0xc7,0xa6,0x39,0xa1,0x7f,
+  0x5b,0xbd,0x0a,0x94,0x68,0x7e,0xfe,0x8b,0xca,0x01,0x62,0xac,0xd8,0x25,0x24,0x31,
+  0xd1,0x93,0x46,0x7b,0x9e,0x2e,0x42,0x7b,0x1e,0x33,0x6a,0x13,0x8a,0x3a,0x55,0xfd,
+  0xd7,0x40,0xdb,0x0e,0xb6,0x4d,0x68,0x1a,0xaa,0x54,0xc5,0x63,0xcc,0x7f,0x85,0xd3,
+  0x72,0x4a,0xfc,0x0d,0xec,0xbf,0xe3,0xa9,0x15,0xc8,0x87,0xcf,0xcd,0x7f,0x61,0x51,
+  0xc6,0x31,0x86,0x9f,0xc3,0x5d,0x55,0x0f,0xf1,0x7a,0x13,0x5e,0x08,0x36,0x16,0x9b,
+  0x54,0xe7,0x75,0xf8,0x92,0xe5,0x79,0xf9,0x2f,0xea,0x5d,0xd0,0x56,0xc5,0x36,0x62,
+  0xbb,0x0c,0xef,0xb8,0xa8,0x09,0xaf,0x61,0x46,0x6c,0x82,0xe9,0xf3,0x35,0xe0,0xf5,
+  0x5f,0x86,0x3b,0xff,0xc5,0xf9,0x3f,0x9e,0x24,0x09,0xca,0xbd,0x1f,0x06,0x52,0xc1,
+  0xcd,0x62,0x9d,0xda,0x87,0x44,0x82,0x14,0x73,0x1b,0x71,0xa3,0x41,0xbb,0xb5,0x97,
+  0xa4,0x73,0xf2,0x5f,0xc1,0x8a,0x22,0x36,0xfe,0x52,0xb6,0x31,0x79,0xbb,0x63,0xa7,
+  0x67,0x26,0xf3,0x77,0x0d,0x58,0x81,0xfb,0x1e,0xe9,0xed,0xba,0x7b,0x2b,0xdb,0x41,
+  0xe4,0xf2,0x7f,0xd8,0x6a,0x9c,0xbd,0xce,0x0b,0x5d,0x0b,0x02,0xc3,0xb7,0x6c,0x62,
+  0xdb,0x90,0x6e,0xfc,0x8b,0xa8,0xa8,0x2e,0xb2,0x12,0x3c,0x81,0x2c,0xfc,0xb3,0x92,
+  0x97,0x11,0x15,0x3f,0x26,0xf2,0xb2,0xd3,0xa1,0xaa,0x4d,0x4c,0xe8,0x43,0x86,0x7c,
+  0x0a,0xeb,0x2f,0x84,0xf0,0x02,0xa4,0x8a,0xe5,0xe4,0xbf,0x5a,0xe0,0x7e,0xfc,0xc9,
+  0xcf,0x6a,0x2d,0x23,0xf7,0x1b,0x62,0xca,0xc4,0x3f,0x13,0xe5,0x13,0x04,0xe3,0x3f,
+  0x6c,0xbe,0xe3,0x24,0x1b,0xff,0x5c,0x37,0x56,0xfc,0x73,0x31,0x0c,0xa7,0x69,0x38,
+  0xfd,0xda,0x64,0xf9,0x39,0xfd,0x35,0xb6,0x3e,0x8b,0x27,0xc5,0x09,0xfd,0x60,0x69,
+  0x8b,0xb6,0x61,0xb8,0x2d,0x95,0x83,0x7f,0xfc,0x98,0xcd,0x69,0x30,0x81,0xd0,0x20,
+  0xc1,0xfa,0x2f,0x1e,0xe6,0x3a,0x1a,0x89,0x47,0x1a,0xaa,0x95,0xef,0xfe,0x79,0x26,
+  0xfe,0x86,0xf8,0x67,0x6f,0x61,0xed,0xc8,0x2d,0x65,0x3c,0xbf,0xcc,0x89,0xa9,0xeb,
+  0x63,0xdd,0x66,0x85,0xa0,0xb1,0x9e,0x6a,0x41,0xaa,0x40,0x6b,0xac,0x34,0x1b,0xff,
+  0xb0,0xfb,0x3f,0x60,0xf1,0xc9,0x2f,0x47,0x3c,0x89,0xfa,0x94,0x53,0xfe,0xb7,0xe5,
+  0xbe,0x38,0x53,0x5d,0x9c,0xa4,0xb2,0xf0,0xcf,0x5e,0x06,0x9b,0xd9,0x6e,0x3a,0x68,
+  0xbd,0x26,0xe5,0xeb,0xd5,0x57,0x4c,0xfd,0xbc,0x13,0x1b,0x31,0x98,0xab,0x5a,0x97,
+  0x8f,0x7f,0x8c,0x0d,0x47,0xac,0xb0,0xcf,0x95,0x4e,0xfc,0x67,0x42,0x1c,0x55,0xd9,
+  0xc6,0x53,0xda,0x90,0xcc,0xe1,0xff,0xfc,0x0e,0x18,0x8c,0xdc,0xa8,0xd8,0xf7,0x17,
+  0x3f,0xc0,0x2b,0x23,0xec,0xfe,0xe3,0x95,0x93,0xed,0x4d,0x23,0x08,0x1d,0xb3,0xf9,
+  0x3f,0x42,0xc3,0x09,0xac,0x56,0xb6,0x0b,0x03,0xf1,0xf9,0x83,0x13,0xc5,0x29,0xf2,
+  0x6b,0x7d,0xcf,0x28,0x43,0xd4,0x1b,0x66,0x36,0x65,0xe1,0x9f,0xbd,0x30,0xd3,0x50,
+  0xfe,0x91,0x38,0x85,0x81,0xbc,0x82,0x60,0x82,0xe9,0x67,0x04,0x89,0x2b,0x11,0x45,
+  0x23,0xab,0xf2,0xf0,0x8f,0xf2,0x5f,0x0a,0x67,0x70,0x3e,0x8c,0xb2,0xaa,0xf0,0x57,
+  0xb0,0x16,0xd3,0x5e,0xab,0xc8,0xcf,0xb4,0xa7,0x69,0x75,0x74,0xd1,0x2a,0x52,0xa9,
+  0xda,0xf7,0xe7,0xf5,0x5f,0xea,0x7c,0x83,0xf9,0xdf,0x12,0x61,0x57,0x72,0x7e,0xda,
+  0x37,0xb7,0xe6,0x03,0xf8,0x35,0xcc,0xdf,0x57,0x3c,0xeb,0xea,0x61,0xe6,0xb8,0x43,
+  0xe0,0x53,0x95,0xdb,0x9c,0xe5,0x86,0xf8,0x87,0xd3,0xa2,0x12,0xe2,0x19,0xfd,0x3c,
+  0x4e,0x7c,0x27,0x17,0xbe,0x85,0x81,0xa0,0x13,0x70,0x5e,0x7d,0x1e,0x7c,0xa3,0xd3,
+  0xf2,0xf9,0xcf,0x6c,0xdb,0xeb,0xd2,0xcf,0x2b,0xec,0x17,0xf1,0x99,0x85,0x87,0x03,
+  0x47,0x7c,0xa3,0x8b,0xf2,0xf9,0x3f,0x8b,0x22,0x6c,0xff,0xf8,0x5b,0xd3,0x90,0x9e,
+  0x81,0x7f,0x63,0xc2,0xe5,0x9d,0xe4,0x30,0xe6,0xd3,0x5f,0x51,0x3a,0xdb,0x9a,0xf2,
+  0xf0,0x4f,0xd1,0xd2,0xb2,0x19,0xb2,0x45,0x84,0x7e,0x0b,0xd6,0xf6,0x98,0x82,0x90,
+  0xa2,0xd5,0xc7,0x94,0xca,0xac,0xfc,0x97,0x85,0xb7,0x07,0xd9,0x7a,0x7b,0xd4,0xd6,
+  0xe7,0x83,0xa6,0xf0,0x9b,0x65,0x7b,0x22,0xda,0xeb,0xca,0x77,0x88,0x3b,0xff,0x65,
+  0xf2,0x9f,0x8b,0x9f,0x10,0x03,0x4c,0x68,0x40,0xc3,0x32,0xce,0x03,0x41,0x1b,0xb0,
+  0xec,0xeb,0x5c,0xac,0x29,0xe1,0x9b,0x82,0xff,0xc3,0x2c,0x2c,0xdf,0x7d,0x98,0xb0,
+  0x07,0x30,0x11,0xe6,0xa3,0x35,0x4c,0xe8,0x08,0xc3,0x92,0x35,0xe2,0xc6,0x5c,0xfc,
+  0x13,0xf5,0xf1,0x68,0x0f,0x73,0xa3,0xf6,0x7e,0x1f,0x85,0x77,0x60,0x7f,0xb2,0x69,
+  0xb9,0xaf,0x3f,0x9f,0xff,0xdc,0xa9,0xf4,0x17,0xd6,0x32,0xd8,0xd0,0x60,0xc7,0x1f,
+  0x66,0xa0,0xf0,0x4e,0xac,0x97,0xbd,0x7a,0xe2,0x66,0x25,0x9a,0xc1,0x3f,0x02,0xc7,
+  0x3f,0x77,0x28,0x0f,0x58,0xf5,0x4a,0x97,0x9b,0xe3,0x4b,0xd8,0x78,0x18,0xbb,0x05,
+  0xf1,0x8f,0xb2,0x31,0x96,0xcb,0x7f,0x5e,0x19,0x61,0xdb,0x2e,0x09,0xb6,0x08,0x41,
+  0xfd,0x72,0x95,0xbc,0x08,0x3b,0x09,0x27,0x02,0xbd,0x28,0x6c,0xd1,0x35,0x4c,0x8d,
+  0xb5,0x66,0xe1,0x1f,0x8e,0xee,0x78,0xfd,0x17,0xb9,0xcf,0xe6,0xff,0x34,0x98,0xc2,
+  0x01,0xbe,0xff,0xaa,0x29,0xc9,0xc7,0x3f,0xa3,0x6c,0x9a,0xef,0x9a,0xd3,0x3c,0xa1,
+  0x5a,0xf3,0xfd,0x58,0xfa,0x25,0x32,0x82,0x0e,0xbb,0xea,0xbf,0x2c,0xfe,0x4f,0xbb,
+  0x0f,0xab,0xdd,0xcf,0x62,0xa2,0x70,0x94,0xfd,0xfd,0xfd,0x1c,0x2f,0x89,0x27,0x8c,
+  0x57,0x03,0x4d,0x86,0xef,0xf5,0x69,0x53,0xf0,0x9f,0x63,0x31,0xac,0xff,0xda,0x8a,
+  0x44,0x68,0x8d,0xed,0xb8,0x39,0x23,0x7a,0x1c,0x18,0xfe,0xc1,0xaf,0x72,0xf8,0x3f,
+  0x80,0x61,0x76,0x8c,0xf6,0x08,0x18,0xef,0x62,0x8a,0xed,0x82,0x95,0x9c,0xf8,0x64,
+  0x74,0x05,0xf8,0x7c,0xf3,0xf8,0x3f,0x88,0x27,0x99,0x3e,0x25,0x1e,0x7f,0xab,0xe5,
+  0xf8,0x47,0x49,0xf8,0x99,0xa1,0xd3,0xfc,0x7a,0x5f,0xa2,0x2c,0x97,0xff,0xc3,0x26,
+  0xa5,0x62,0xb4,0x07,0x9f,0x3f,0xc1,0x0b,0xf9,0xf9,0x7c,0x7f,0x43,0xf6,0x6b,0x4d,
+  0x77,0xfa,0xfe,0x71,0x5d,0x1e,0xfe,0x71,0x2f,0x83,0x45,0xce,0x7a,0x78,0x49,0xfd,
+  0x90,0x3e,0xa7,0xfb,0x2a,0xbb,0xb3,0xf1,0x0f,0x5b,0x66,0x08,0x72,0x9c,0xfa,0x3b,
+  0x2c,0xbb,0xe3,0x3f,0xc4,0x51,0x44,0xa4,0x2a,0x5b,0x81,0xb9,0xfc,0xe7,0xc6,0x54,
+  0xe0,0x03,0x4f,0x00,0xb0,0x8c,0x94,0x59,0x8f,0x49,0x69,0x1d,0x34,0x26,0x11,0xff,
+  0xb4,0xde,0x4f,0xfd,0x09,0x65,0xac,0x3b,0x9b,0xff,0xc3,0x5e,0x93,0x61,0xb9,0x2a,
+  0xe6,0xb5,0x5f,0x93,0x7d,0xb4,0x9b,0x04,0xc7,0x98,0xf0,0xb2,0xd0,0x15,0x4f,0xbe,
+  0xa9,0x54,0x91,0x3c,0xfe,0x4f,0xd2,0xe2,0xff,0xf0,0xf7,0x77,0x74,0xeb,0x5a,0x53,
+  0x38,0xa2,0xad,0x95,0xab,0xd9,0xd6,0x86,0xac,0xc8,0xe2,0xff,0xfc,0x16,0xeb,0xd3,
+  0x27,0xc5,0x19,0xf2,0x1f,0x4d,0xd8,0xf3,0x3a,0x7d,0xb9,0xab,0x3e,0x7d,0x25,0xc3,
+  0x3f,0xea,0xab,0x58,0x08,0x7f,0x24,0x9b,0xff,0x83,0xf6,0x87,0x9a,0xf1,0x1f,0xd3,
+  0x9e,0xbc,0x6d,0x0b,0x13,0x70,0x96,0x84,0x47,0x7d,0xc6,0x5f,0xe7,0xf2,0x9f,0x5b,
+  0xa2,0xbe,0x11,0xb1,0x41,0xff,0x45,0xa2,0x85,0xf3,0x7f,0x34,0x5e,0xf6,0x3e,0x29,
+  0xfe,0x1d,0xbc,0x4a,0x5b,0xc6,0xbc,0x93,0xd3,0xb2,0xf0,0x0f,0x96,0x9d,0xca,0xca,
+  0x37,0x49,0x09,0x65,0xf6,0xd3,0x28,0x99,0x47,0xda,0x19,0x9e,0xb9,0x91,0x3f,0x3f,
+  0xac,0xad,0xac,0xa7,0xc5,0x7a,0x61,0x1e,0xff,0x47,0xff,0x8b,0x28,0xe1,0xf5,0x5f,
+  0x86,0x72,0x0f,0x79,0x13,0xbe,0x8b,0x88,0x9a,0xd9,0x2b,0xfd,0x3b,0xd0,0xa8,0x17,
+  0x75,0x12,0x9a,0x8b,0x7f,0x74,0x85,0x16,0x7a,0x6d,0xfe,0x61,0x7b,0x21,0x67,0x80,
+  0x84,0x6e,0x1e,0x87,0x8d,0x5a,0x10,0x8a,0x76,0xe7,0xe3,0x1f,0xea,0x7b,0x44,0x0c,
+  0xca,0xbf,0x20,0x7c,0x9a,0x69,0xf8,0x05,0x1a,0xa2,0xd4,0xb4,0x2f,0xd7,0x1e,0xd9,
+  0x17,0x86,0xe2,0x47,0xf2,0xf1,0x0f,0xf0,0x30,0x08,0xf2,0xa3,0xbc,0x29,0x38,0x6a,
+  0x32,0x84,0x53,0xd3,0xde,0x85,0xf7,0x78,0x6b,0x8e,0x07,0xf3,0xf0,0x0f,0xf8,0xd2,
+  0xe2,0x7c,0xb6,0x1b,0xbd,0x61,0xc8,0x37,0x21,0x4c,0x20,0xec,0xa1,0x25,0x13,0xd3,
+  0xc6,0x6a,0x87,0xa1,0x39,0xa4,0x8c,0x2a,0x90,0x8b,0x7f,0xe6,0xf6,0xf5,0x12,0xdb,
+  0x7f,0x95,0x19,0xfe,0x3e,0xb8,0xfb,0x75,0xe6,0xc8,0x7e,0x2b,0xc7,0x29,0x7b,0xbf,
+  0xe2,0x62,0x1e,0xff,0x47,0xe3,0xf5,0x5f,0x37,0x98,0xe3,0x8f,0x49,0x7d,0xf8,0x3e,
+  0xa6,0xe0,0x31,0x88,0xd3,0xbb,0x8c,0xcb,0x07,0x63,0x39,0xfc,0x1f,0x2c,0x72,0x6f,
+  0x22,0x5e,0xc4,0xbe,0xc3,0x7d,0x4d,0x0c,0x3d,0x76,0x9b,0x0b,0xcf,0x90,0xba,0x20,
+  0x9a,0xbc,0x3c,0x8f,0xff,0x83,0x6f,0x07,0x74,0xd7,0xd3,0xdf,0x45,0xe7,0x8d,0xfa,
+  0x06,0xc4,0xf7,0xf5,0x57,0xd8,0xfd,0xef,0x4f,0xd5,0xe0,0x8b,0x30,0x80,0xa1,0xc2,
+  0x5c,0xfe,0x4f,0x0b,0x5e,0x3c,0x93,0x7e,0x5e,0x65,0x8e,0x6c,0xd7,0x83,0xa3,0xd4,
+  0xf2,0xef,0x18,0xff,0xb9,0x11,0x36,0x18,0x6d,0xdb,0x73,0xf8,0xcf,0x37,0x2e,0xf7,
+  0x55,0x8a,0x9d,0x65,0xaf,0xd2,0xa6,0x64,0x09,0x55,0xb0,0x10,0x7e,0x97,0x49,0x24,
+  0xfb,0x3d,0x5b,0xba,0x4a,0x36,0xff,0x87,0xc7,0x7f,0x18,0x5e,0xf5,0xa8,0x52,0x2f,
+  0xdd,0x9a,0xbc,0x7c,0x47,0x59,0x10,0x13,0x55,0xe9,0x45,0x48,0x84,0xde,0x83,0x88,
+  0xa8,0x87,0xe4,0xf1,0x9f,0xd9,0x32,0x88,0x01,0xe9,0x05,0x8d,0x2a,0x5d,0x66,0xa1,
+  0xb7,0xe9,0x98,0xb6,0xe2,0xc4,0x0b,0x99,0xbd,0x75,0xe1,0x1f,0x99,0xd7,0x4f,0xed,
+  0x26,0x5a,0x92,0x59,0x7b,0x6a,0x15,0xd6,0xd5,0x31,0xc5,0x16,0x1e,0x43,0xd3,0x67,
+  0x2c,0x8a,0xbb,0xf8,0x3f,0x7a,0x29,0xef,0xff,0x33,0x52,0xf8,0xac,0xf8,0x37,0xf2,
+  0x10,0x34,0x3d,0xc4,0xfc,0x17,0x2f,0x54,0xe7,0x81,0x44,0x95,0x2f,0x8c,0x47,0xa6,
+  0xa9,0xb9,0xf8,0x67,0xf8,0xd6,0x33,0xe5,0xa7,0xe0,0xac,0xd0,0x82,0xfe,0x0e,0x35,
+  0x76,0x9d,0x53,0x11,0x6f,0xf8,0x68,0x56,0xfc,0x27,0x88,0x61,0xc6,0x74,0x70,0xb7,
+  0x58,0xa4,0xed,0x87,0xa6,0x1e,0x5f,0xb2,0x3b,0xa8,0x9f,0x36,0xfd,0x3b,0x2e,0x5d,
+  0x66,0x9f,0x93,0x42,0x1e,0xff,0x39,0x1d,0xd8,0xdd,0xf6,0x37,0xb4,0xf7,0xb6,0x3f,
+  0x6c,0x51,0x02,0x31,0x3b,0x90,0x28,0x9a,0xd0,0x6e,0xd1,0xb7,0x63,0x59,0xf8,0x47,
+  0xc0,0xb2,0xd3,0xcb,0x52,0x65,0x22,0x96,0x21,0x33,0x34,0x48,0x4a,0xd8,0x30,0x4e,
+  0x84,0x5e,0x0f,0x6c,0x07,0x61,0xfc,0xc5,0xb6,0x3c,0xfe,0x73,0xfd,0xd8,0x17,0xbe,
+  0x19,0xbb,0x0d,0x56,0x3f,0x52,0x14,0x58,0xf4,0xb7,0x64,0x06,0x7b,0x91,0x91,0x21,
+  0x43,0xbe,0x0f,0xff,0x42,0xab,0xd3,0xdf,0x5b,0x0a,0x95,0xee,0xf8,0x8f,0x8e,0xfd,
+  0x7f,0x4a,0xe6,0x2a,0x10,0x7b,0xa1,0x47,0x7e,0xd7,0xe7,0xc1,0x42,0xf8,0xe4,0x6c,
+  0x24,0xea,0xac,0x97,0x8e,0x4b,0x21,0x63,0x89,0x2a,0xe6,0xf2,0x9f,0x5b,0x8c,0xe2,
+  0xe3,0xcc,0xba,0x7e,0xa4,0xcd,0x91,0xcc,0xfc,0xa0,0x6a,0x11,0xc5,0x4f,0xa0,0x7e,
+  0x46,0xdd,0xf5,0x5f,0x26,0xff,0xdc,0xf0,0xa6,0x7c,0xd5,0x64,0x88,0x5c,0x92,0x94,
+  0x35,0xae,0x7f,0x8b,0x28,0xce,0x0d,0xd7,0x44,0x3e,0xff,0x79,0x48,0xee,0x2c,0x54,
+  0x55,0x8c,0xf6,0x74,0x44,0xc5,0x3b,0x9d,0x40,0xba,0xca,0x2d,0x4c,0x84,0xe4,0xe2,
+  0x9f,0xc6,0xb4,0xfc,0x4d,0x32,0x43,0xfa,0x6e,0xd7,0xd5,0xbf,0x96,0x57,0x10,0xd4,
+  0x40,0xb5,0x09,0x84,0x9e,0x8e,0x33,0x20,0x34,0x37,0x1f,0xff,0x6c,0x8d,0x07,0x49,
+  0xc9,0xbe,0x07,0xd9,0x7a,0x5b,0xa1,0xc5,0x10,0x61,0x26,0x99,0x3e,0x0b,0xd9,0x57,
+  0x0b,0xd8,0x7a,0xdb,0xb4,0xce,0x85,0x7f,0x38,0xff,0x99,0xed,0x8f,0xde,0x25,0xd7,
+  0x93,0xd7,0xe1,0x53,0x49,0xf9,0x2e,0x0e,0x84,0x9a,0x4c,0x20,0xf4,0x9c,0x1e,0xa6,
+  0xd3,0x8e,0x91,0x1c,0xfc,0x23,0x84,0xa5,0xc6,0x1e,0x71,0x88,0x8c,0xdb,0xfe,0x68,
+  0x32,0x4b,0x58,0xed,0xce,0x7f,0x81,0xe9,0xdd,0xbc,0x09,0x71,0x26,0xec,0xdf,0xd6,
+  0xb4,0x82,0xa1,0x9d,0x99,0xd2,0xc9,0xb2,0x26,0xcb,0x03,0xca,0xec,0xd5,0xde,0xec,
+  0xc6,0x3f,0xb0,0x5c,0xc6,0x68,0x73,0x60,0x86,0xb2,0x5c,0xef,0x1d,0xf2,0x47,0x95,
+  0x07,0xc4,0xe5,0xfa,0x1e,0x24,0x02,0x25,0x44,0xbb,0x34,0xc9,0x93,0x57,0xff,0x85,
+  0x41,0x8c,0x5a,0xa1,0x57,0x46,0xef,0x8c,0x85,0xf0,0x3a,0x17,0xc6,0xec,0x52,0xa6,
+  0x2c,0xfc,0x83,0x65,0xef,0x9d,0x72,0x05,0xf9,0x2c,0x5b,0x6f,0x58,0x6d,0x4a,0x6e,
+  0x82,0x9d,0x3a,0x17,0x7a,0xec,0xd2,0x30,0x92,0x8d,0x7f,0x84,0x06,0x24,0xf9,0x60,
+  0xf3,0x1a,0x3f,0x27,0x02,0xc1,0x84,0x45,0x84,0x2e,0xe5,0xf3,0x4d,0x5e,0xed,0xc2,
+  0x3f,0xc5,0x26,0x9f,0x79,0x43,0x44,0xfc,0x98,0x9c,0x85,0x7f,0xd1,0x37,0x1c,0x2e,
+  0x1f,0x93,0x4e,0x4a,0xcf,0xe1,0x7c,0xb7,0x61,0x45,0x98,0x9e,0x5d,0xff,0x25,0xe0,
+  0xf8,0x1b,0x75,0xef,0x68,0xdb,0x6c,0xed,0x55,0xe9,0xc6,0x05,0xd2,0x68,0xdf,0xff,
+  0x65,0x02,0x21,0xd4,0xcf,0xd7,0x39,0x94,0xea,0xce,0xe1,0x3f,0x4b,0x0d,0x72,0x20,
+  0x46,0xaa,0x09,0xc2,0x9e,0xe2,0x24,0xd1,0xe8,0x20,0x3c,0xe1,0x54,0x84,0x81,0xb2,
+  0x86,0xe4,0xe1,0x9f,0x56,0x39,0x11,0x6b,0x4f,0x76,0x41,0x30,0x5a,0xa4,0x62,0x99,
+  0x09,0xc2,0x1e,0xb5,0x70,0xd8,0x0a,0x85,0xc5,0xf2,0xf0,0x4f,0xbb,0x9c,0x68,0xfa,
+  0x0a,0xb2,0x7d,0x30,0xec,0x53,0x8b,0xf9,0x7a,0x6c,0xac,0x94,0xd1,0x67,0x2e,0xff,
+  0xf9,0x5e,0xaf,0xda,0xf7,0x65,0xd8,0x4f,0xc3,0x7a,0xf1,0x26,0x71,0x79,0xc5,0x49,
+  0x62,0x3e,0xbf,0x74,0xb2,0x96,0x3d,0xff,0x23,0x4a,0x1e,0xff,0x59,0xf7,0x6d,0xbc,
+  0xfd,0x07,0x70,0xb2,0x2e,0xac,0xb3,0xb7,0x2f,0x53,0x41,0x56,0xc1,0x85,0x4b,0xf3,
+  0xf9,0xcf,0xaa,0x97,0x2a,0xd5,0x12,0xc6,0xdf,0xea,0x7a,0xc4,0xa4,0x3c,0x49,0x6c,
+  0x22,0x7a,0x21,0x26,0x5e,0x6b,0x72,0xe3,0x3f,0x8d,0xdb,0xe5,0x71,0x32,0x97,0xdc,
+  0x4f,0x67,0x6f,0x1d,0x39,0x56,0x58,0x47,0x9f,0x03,0x3f,0x5d,0x84,0x89,0xb0,0x67,
+  0x60,0x1e,0x55,0xd2,0xf9,0xf1,0x9f,0xb4,0xac,0x7a,0x1a,0x68,0xd7,0x90,0xa6,0xdf,
+  0x02,0xb1,0xf5,0xf2,0x00,0xd5,0x32,0x89,0x30,0xa5,0x34,0x96,0x1b,0xff,0x69,0x34,
+  0xe4,0x48,0xac,0x14,0xee,0x8f,0x5f,0xad,0x17,0xb5,0x93,0x2a,0xe9,0x29,0xdd,0x4a,
+  0x84,0xf1,0x52,0xa9,0x88,0x3b,0xfe,0x63,0xf3,0x9f,0x8f,0x5c,0x1d,0x86,0x43,0x3d,
+  0xb3,0xa2,0xc5,0x1d,0xcc,0x4c,0x9d,0xa5,0x3b,0xcd,0x44,0x18,0xfb,0xea,0x28,0x13,
+  0xde,0xcb,0xc1,0x3f,0x61,0xa3,0x31,0x29,0x8e,0x91,0x53,0x52,0x58,0x2f,0x01,0x66,
+  0x76,0x98,0xa2,0x98,0x3d,0xa9,0x31,0xed,0xc9,0x86,0xd1,0xfc,0xf8,0x4f,0x14,0xd9,
+  0x3e,0x70,0xe8,0xc1,0xe6,0xe5,0xbe,0xb9,0x62,0x03,0x0c,0xd2,0x46,0x2c,0x04,0xbb,
+  0x4f,0x3f,0x4f,0x9b,0xc7,0x7c,0x3f,0x27,0x2e,0xfc,0x23,0x98,0x78,0x46,0xee,0xdc,
+  0x78,0x49,0x3c,0x96,0xac,0xfe,0xdb,0x45,0x0b,0x3d,0x25,0x34,0x95,0xa8,0xb7,0x9e,
+  0xbf,0xb2,0x7a,0x98,0x3d,0xbf,0x0b,0xff,0xa8,0x9b,0xe1,0x07,0x38,0xfe,0x1e,0x86,
+  0x7f,0xee,0x97,0xae,0x6a,0x57,0x6e,0x23,0x55,0xfa,0x93,0x26,0xde,0x7b,0x93,0xed,
+  0x06,0xab,0x71,0xe3,0x96,0x1b,0xff,0x69,0x38,0x1a,0x80,0x2f,0x48,0x24,0x06,0xb5,
+  0x4b,0x15,0x2f,0xb3,0xff,0x3b,0xed,0x8d,0xd8,0x2e,0x49,0x33,0xfa,0x76,0xe4,0xe0,
+  0x1f,0xe6,0xa4,0x5a,0xbd,0x73,0x45,0x99,0x1c,0x80,0xdd,0xe9,0xbe,0x75,0x6c,0x23,
+  0x90,0x21,0x36,0xd3,0x32,0xc3,0xb7,0x3e,0x1f,0xff,0xb4,0xfa,0x52,0xdd,0x47,0xc9,
+  0x29,0x61,0x1e,0x03,0x5a,0xcc,0xcd,0x71,0xfe,0xb3,0x69,0x6f,0x9f,0x33,0x7c,0xdd,
+  0x62,0x3e,0xfe,0xf1,0x4e,0x88,0x5a,0xec,0x10,0xdb,0x68,0x78,0x0d,0xf1,0x9c,0xfe,
+  0x6a,0x6b,0x73,0xc6,0xdf,0x29,0x69,0x31,0x07,0xff,0x90,0x86,0xb9,0xf2,0x76,0xb6,
+  0xad,0x58,0xb7,0xa6,0x61,0x99,0x27,0xce,0xdc,0xfa,0x4f,0x74,0xbb,0x10,0x09,0x11,
+  0x4e,0x3c,0x9f,0xff,0x1c,0x65,0xf6,0x27,0x00,0xeb,0x28,0x7b,0x5f,0xfa,0xd9,0xb0,
+  0x1f,0x32,0x37,0xd7,0x97,0x19,0x9f,0x8f,0x7f,0x74,0x99,0x19,0x31,0x1a,0xdb,0xd6,
+  0xd0,0xe1,0x01,0x72,0x70,0xfd,0x83,0xb2,0x7b,0xbd,0x81,0xc7,0x85,0x7f,0x0a,0x38,
+  0xfe,0x81,0x8e,0xef,0x30,0xb3,0x7c,0xa0,0x22,0x7c,0xe7,0x67,0x1f,0x64,0xf8,0xe7,
+  0xd5,0x68,0x93,0xb1,0xc1,0xf6,0x2f,0x4b,0x12,0x35,0x2e,0xfc,0x33,0x9d,0x67,0xbb,
+  0xc0,0xd7,0x2a,0xa6,0x23,0xc7,0x9b,0xc2,0xed,0xbe,0x17,0xc4,0x33,0x77,0x9c,0x0d,
+  0x3c,0x6f,0xce,0x97,0x13,0x39,0x0c,0xd1,0xc5,0xff,0x99,0x8e,0xfc,0xf9,0x16,0x8b,
+  0x36,0x9f,0xb8,0x6e,0xb8,0x78,0x52,0x1c,0xc5,0xfc,0x97,0x4d,0xa4,0x6f,0xa9,0xf4,
+  0x1a,0x6d,0x79,0xf8,0xc7,0x2c,0xfb,0xda,0xab,0xd5,0xbc,0x29,0x0f,0x92,0x77,0x8d,
+  0x5f,0x38,0x57,0x68,0x83,0x24,0x7f,0x7b,0x0a,0xfc,0x63,0x7a,0x1f,0xa8,0x1d,0xc2,
+  0x30,0x60,0x05,0xdb,0x5f,0x38,0xf3,0x95,0x65,0x70,0xd7,0x7f,0x15,0xec,0xc8,0x84,
+  0x4d,0x90,0xff,0xd3,0x81,0x69,0xaf,0xef,0xd9,0x57,0x10,0x6a,0xca,0x83,0xee,0xfa,
+  0x2f,0xc1,0x4d,0x83,0xc7,0x40,0x10,0xb6,0x05,0x78,0x05,0xee,0x73,0x12,0xa9,0x9d,
+  0xc1,0xcd,0x62,0x1e,0xfe,0xb1,0x7f,0x7d,0xee,0x9d,0xcf,0x91,0xcc,0x15,0x69,0x3e,
+  0xf8,0x22,0x8a,0x0b,0xff,0xc0,0x0e,0xfb,0xfe,0x28,0xcc,0x65,0x8e,0xbe,0x9c,0xc7,
+  0x27,0xed,0x2b,0xe1,0x44,0x90,0x4e,0x4b,0x65,0xe3,0x1f,0xa9,0x01,0xcb,0xa0,0x70,
+  0x22,0x26,0xff,0x87,0xc7,0xaf,0xec,0xe7,0xaf,0x92,0x13,0xee,0xfc,0xd7,0x74,0xc4,
+  0x3f,0x41,0x0b,0xed,0x30,0x58,0x28,0x87,0xee,0x1d,0xb7,0xf1,0xb0,0x19,0x4a,0xad,
+  0xd4,0xc8,0xa0,0x1b,0xff,0x48,0x56,0x18,0xe4,0xfb,0x1c,0x06,0x04,0x56,0x91,0x5f,
+  0xf0,0xf8,0x8f,0xd3,0x18,0xa7,0x7f,0x29,0xc9,0xce,0x7f,0x7d,0x44,0xe7,0x73,0xb4,
+  0x03,0xa7,0x93,0x73,0x87,0xbc,0xa1,0xb6,0x43,0xda,0x0b,0xaa,0x75,0x85,0x41,0xa3,
+  0x88,0xb7,0x5a,0xdc,0x98,0xdf,0xff,0x70,0x02,0xeb,0xbf,0x18,0xec,0xc1,0x42,0x03,
+  0xdd,0xa5,0x31,0x06,0xad,0x73,0xeb,0xdf,0x3f,0xa2,0x0e,0xda,0x69,0x3a,0x88,0xfa,
+  0x81,0x57,0x84,0x39,0x6c,0x7d,0x4e,0x3b,0x66,0x86,0x92,0x8c,0xbc,0xfe,0x3f,0x96,
+  0xb5,0x7c,0x5e,0xa8,0xd9,0x57,0xdc,0xc9,0xa6,0xf9,0x6f,0x60,0xdb,0x1f,0x91,0xa7,
+  0x2a,0x72,0xf3,0x5f,0x36,0xda,0xa1,0xd5,0xe3,0xbc,0x10,0x6c,0x2d,0xbd,0x8a,0x5f,
+  0xf1,0x3e,0x1d,0x63,0x13,0xef,0xc8,0xcb,0x7f,0xd9,0x6f,0x13,0xd1,0x8c,0x5e,0x57,
+  0xfc,0x87,0x9b,0xa6,0x3b,0x94,0x8a,0xd8,0xeb,0x39,0xf1,0x9f,0x01,0x13,0xed,0x20,
+  0xec,0x59,0x9c,0xfc,0xcc,0x24,0x8f,0xff,0x58,0x57,0x5a,0xb6,0xf9,0xc6,0xba,0xf3,
+  0xf2,0x5f,0x19,0xb4,0xb3,0x84,0xb2,0xfd,0xa9,0xfb,0x0a,0x36,0xd2,0x9c,0xa2,0xfe,
+  0xdd,0xdc,0xef,0x87,0x10,0x08,0x0d,0xdb,0xf1,0x01,0x33,0x34,0xe4,0x55,0xa7,0xa8,
+  0x7f,0xb7,0xc2,0x3e,0x1e,0x7d,0x21,0x6f,0xe3,0x93,0xb9,0xd2,0xd0,0xba,0x3d,0x91,
+  0x57,0xff,0x6e,0xd1,0x54,0x76,0x82,0x9f,0x19,0x96,0xa6,0xb1,0x48,0x6f,0xa6,0x70,
+  0x8c,0x97,0x92,0x4d,0x51,0xff,0xae,0x92,0xe1,0x82,0x9d,0x0b,0x02,0x11,0x8f,0x4a,
+  0x5e,0xc6,0x7e,0x38,0xfc,0x0a,0xef,0x08,0x24,0xab,0x90,0x83,0x7f,0x4c,0xda,0x8f,
+  0x59,0xff,0xe5,0xa5,0xe5,0x69,0x32,0x92,0xb9,0x82,0xd4,0x14,0x25,0x17,0xff,0x64,
+  0x66,0x17,0x69,0x4c,0x88,0x1f,0xbb,0xaf,0xe4,0xd5,0xbf,0x8f,0x99,0xa0,0xc8,0x1a,
+  0xdf,0xce,0xf4,0x73,0x62,0x74,0xbf,0x7b,0xbc,0x77,0x63,0x77,0xa1,0x90,0x85,0x7f,
+  0xec,0xfa,0xf7,0x54,0x6d,0xb0,0xa2,0x98,0x92,0x65,0xea,0x11,0x7e,0x45,0x4c,0xe2,
+  0x57,0xaa,0xbc,0x8d,0xe1,0x1f,0xfb,0xf9,0x2d,0xfc,0xc3,0x67,0x27,0xcf,0x92,0x83,
+  0x1d,0xb2,0x4a,0x5e,0xa4,0x38,0x5f,0xd1,0x22,0x3e,0x2d,0x65,0x1a,0x20,0x82,0xad,
+  0x7f,0x77,0xfd,0xbb,0xba,0x87,0x34,0x2c,0x60,0xf8,0xe7,0x2b,0xd2,0xc3,0x66,0xfe,
+  0x8b,0x7f,0xd5,0xea,0xc9,0xc7,0x3f,0xae,0x78,0x8e,0x97,0x87,0xf5,0x48,0xd8,0x21,
+  0x02,0x75,0x36,0xb8,0xeb,0xdf,0xdd,0xf1,0x1f,0xd5,0xee,0xff,0x93,0x74,0xdf,0xa1,
+  0xb3,0xd8,0xcd,0x7f,0x76,0xea,0xdf,0x4d,0x6d,0xcf,0x45,0x20,0xca,0xb6,0xbd,0x84,
+  0x5f,0xe1,0x5f,0x91,0xa9,0xf2,0x5f,0x9c,0xf6,0x23,0x63,0xfd,0x97,0x9c,0x64,0x37,
+  0x5d,0x47,0x30,0xb0,0xc9,0xf1,0x4f,0x63,0x2a,0x90,0x24,0x39,0xf8,0x47,0x72,0xde,
+  0x0e,0xb4,0x3f,0xea,0xbb,0x65,0x2e,0xfb,0xd3,0xa0,0xab,0x17,0xc8,0x7f,0xbd,0x89,
+  0xef,0xa3,0xc1,0x36,0x32,0x6f,0x02,0xc6,0x7f,0x3c,0x26,0xfe,0x09,0xaa,0xd9,0xf9,
+  0x2f,0xbb,0xfe,0x1d,0xd1,0xce,0xd3,0xf4,0xfa,0xb7,0xbd,0xab,0x98,0x5b,0x79,0x99,
+  0x5d,0x51,0x56,0x89,0xdf,0xb7,0x4b,0xc3,0xf2,0xf1,0x8f,0xd9,0xdf,0x46,0x0a,0x0f,
+  0x5b,0xfd,0xc4,0xac,0x2b,0xbf,0xc0,0x50,0x46,0x4a,0xdc,0xe7,0xe4,0xdf,0xc1,0xee,
+  0xdf,0xc2,0xbc,0x95,0x7e,0xfa,0x88,0x25,0x98,0xfe,0x6b,0xda,0x39,0xfd,0xbc,0x19,
+  0x08,0xca,0xc2,0x3f,0xb2,0xf5,0xfc,0x6f,0xc1,0xae,0x64,0xfd,0x70,0xf1,0x37,0xc8,
+  0x21,0x30,0xe3,0x57,0x22,0x87,0x46,0xa0,0xdc,0x53,0x96,0x8d,0x7f,0x38,0xa8,0x63,
+  0xb3,0x5b,0xff,0xb4,0xdf,0x8c,0xff,0xd0,0x1f,0x58,0x1a,0x90,0xbf,0x6b,0x0a,0x79,
+  0xf9,0x2f,0xae,0x3d,0xd5,0xea,0xa7,0xf4,0x92,0x1d,0x88,0x46,0x0b,0xdf,0x90,0x52,
+  0xae,0xcf,0x8d,0xff,0x98,0x61,0x9f,0x63,0xaa,0xd9,0x78,0x96,0x4d,0xf3,0x77,0x19,
+  0x8f,0x16,0xbe,0xcb,0xb7,0x3b,0x1f,0xff,0x38,0xdf,0x0e,0x31,0xe1,0x60,0xe4,0x17,
+  0x96,0x3f,0x92,0x4f,0x93,0x06,0xb2,0x61,0x20,0x3f,0xff,0x65,0x5b,0xef,0x79,0x46,
+  0x31,0x1a,0xf6,0xd7,0xdc,0xfb,0xfd,0xf5,0x13,0x90,0x9f,0xff,0x42,0x6f,0x25,0xf3,
+  0x44,0x4c,0xaa,0x6c,0x8c,0xe1,0x99,0x99,0x96,0xff,0x12,0x18,0xd4,0x49,0xb9,0xeb,
+  0xdf,0x0b,0x82,0x6e,0x7f,0x5d,0x67,0x14,0xa5,0xca,0xd0,0xdf,0x7d,0xd9,0x1a,0x2f,
+  0x35,0xdc,0xc3,0xc6,0x4f,0x51,0xff,0xce,0xf4,0xa3,0xed,0xd2,0x34,0x43,0x6e,0x22,
+  0xaf,0x92,0x47,0xed,0xc2,0xe7,0x66,0x81,0x13,0x3f,0x5a,0xb3,0xf1,0x8f,0x85,0xee,
+  0xe8,0xf9,0xd2,0x1b,0x8c,0xfa,0x01,0xf1,0x7d,0x6a,0xe5,0x17,0x8e,0xc1,0x7f,0xe7,
+  0xa5,0xc7,0xee,0xfc,0x17,0xe2,0x9f,0x80,0xe9,0xbf,0xd4,0xf3,0x51,0x26,0xec,0xac,
+  0x19,0x33,0xdc,0xfe,0x0b,0x7c,0x13,0x6d,0x6e,0xfe,0xf3,0x73,0x66,0xfc,0xf0,0xf5,
+  0xee,0x73,0xf0,0xda,0x9a,0xe6,0xe8,0x67,0x97,0xb6,0x61,0xfc,0xe7,0x3a,0x5c,0x48,
+  0xd8,0x28,0xb2,0x39,0x3d,0x6d,0x52,0x9c,0xa0,0x19,0xfe,0x15,0x82,0x9c,0x92,0xa8,
+  0xb2,0xb9,0xec,0x20,0xf2,0x0d,0x34,0x39,0x4e,0x7e,0x8c,0x61,0x0d,0xc4,0x3f,0x6f,
+  0xc2,0x06,0x5a,0x87,0xc2,0x44,0x86,0xdf,0x2e,0xd9,0xfd,0x25,0x5a,0x5f,0x62,0xe3,
+  0x35,0x3d,0xae,0xb6,0xba,0x0a,0xbd,0xbb,0x4d,0x57,0x75,0x3c,0xbb,0xff,0x0f,0x69,
+  0x88,0x8a,0x83,0xe4,0x1d,0xd2,0xdd,0x73,0x97,0x26,0xaf,0x27,0x3b,0x32,0x85,0x78,
+  0x7d,0x3c,0x10,0xc4,0xee,0x6f,0x3f,0x0f,0x48,0xf8,0xbe,0xcc,0xe8,0xf4,0x6d,0xc2,
+  0xb4,0xcb,0x48,0xea,0x1e,0xaf,0x99,0x08,0x33,0xf5,0xc3,0x80,0x0a,0x77,0xcd,0x86,
+  0xc3,0xdf,0xde,0xa2,0xce,0x37,0x9d,0x78,0x02,0xb5,0x41,0xbe,0x05,0x3e,0x43,0xe1,
+  0x6a,0x19,0xe2,0xfa,0x31,0x2b,0xe2,0x9b,0xc7,0x73,0xf8,0x3f,0x73,0x46,0x7d,0xbb,
+  0x7d,0xb5,0xc8,0x7f,0xee,0xf0,0x6d,0xea,0x66,0xf7,0xc7,0x42,0xa7,0x54,0xf7,0x41,
+  0x78,0x45,0x46,0xa1,0x2d,0xa7,0xff,0x21,0x69,0x78,0xbb,0x6f,0xb0,0x15,0x0b,0x73,
+  0xfc,0x6a,0x9f,0x4c,0x82,0xf0,0x6b,0x7d,0x8e,0xa1,0x3c,0x1b,0x3b,0xc3,0x1c,0x37,
+  0x32,0xdc,0xca,0x32,0xfd,0x7f,0x0c,0x73,0x3d,0x8c,0x2b,0x65,0x24,0x48,0xba,0xe9,
+  0xb6,0x3b,0x14,0x19,0x5f,0x93,0x51,0xac,0x08,0x43,0xfd,0x98,0x1b,0xb1,0x53,0x19,
+  0xfc,0x03,0x1c,0xff,0x44,0x17,0x7d,0x81,0xcc,0x80,0xb5,0xbb,0xff,0x6a,0xa5,0x32,
+  0xce,0x0b,0xe1,0xaf,0x4a,0x5f,0x8e,0xfd,0x00,0xd7,0xc6,0x39,0x30,0x38,0x93,0xc1,
+  0x3f,0x95,0x5e,0xfd,0x23,0x75,0xfe,0x61,0x65,0x76,0xac,0x04,0x5e,0x48,0xce,0xff,
+  0xa6,0x0f,0xd6,0xad,0x97,0x3e,0x92,0x42,0x43,0x3e,0xe4,0xff,0xbc,0x00,0x21,0x04,
+  0x42,0x2e,0xfe,0x8f,0xf7,0x59,0xf5,0x3c,0x69,0x59,0xe0,0x3b,0x5e,0x8e,0x68,0x70,
+  0xde,0xb0,0xaf,0xcb,0x84,0xcd,0xc3,0x4c,0x3f,0x67,0xed,0x40,0x50,0xa6,0xfe,0x5d,
+  0xb6,0xf9,0x3f,0xaa,0x18,0x44,0x6d,0x47,0xbd,0xb2,0x68,0x75,0xec,0x1c,0x14,0x83,
+  0xf4,0x95,0xa5,0x5c,0xff,0x07,0x9c,0xdf,0x77,0xdc,0xe6,0xff,0x74,0x96,0x61,0x21,
+  0xd8,0xb5,0xc6,0x76,0x3d,0x43,0xa4,0xbc,0x82,0xad,0x07,0x2e,0x1c,0x77,0xf4,0x09,
+  0x76,0xff,0x9f,0x23,0x64,0x86,0x70,0x3f,0x12,0xbf,0x3b,0x08,0xf2,0x7f,0xae,0xc1,
+  0x69,0x96,0xd0,0xef,0x9a,0xd0,0x68,0x34,0x37,0xfe,0x13,0x57,0xea,0xc8,0x35,0x6c,
+  0x3f,0x52,0x9b,0x8e,0xcb,0x4e,0xbc,0xd1,0x13,0x64,0x40,0xc8,0xea,0x7f,0xe8,0x3c,
+  0x8f,0x64,0xc6,0x7f,0x7c,0x1f,0x78,0xe6,0xea,0x87,0x8e,0x7e,0x35,0xe9,0x7d,0xaf,
+  0x74,0x05,0xbb,0x32,0x0f,0xf1,0x4f,0x00,0x1b,0xdd,0xe4,0xf4,0x3f,0xcc,0xf2,0x47,
+  0x1d,0xf7,0x55,0x98,0xb4,0x67,0xbd,0x90,0xf3,0x9f,0xd9,0x8b,0xce,0xbf,0x9a,0xa2,
+  0xff,0xf3,0x65,0xe2,0xcc,0xf8,0x7e,0xa3,0x69,0x99,0xe9,0xe6,0xe8,0x1c,0xac,0x08,
+  0x1b,0x83,0xfd,0xc9,0x81,0xdc,0xfe,0x87,0xdc,0xc9,0xfe,0xf5,0xa2,0x04,0xae,0x1f,
+  0x63,0xeb,0xbd,0x7d,0x8f,0x30,0xfb,0xb3,0x53,0xad,0xc3,0x7e,0xce,0x63,0x58,0x5a,
+  0xa8,0xf3,0x7c,0xba,0x83,0x7f,0xa4,0x5a,0xdb,0x5f,0x5f,0x05,0xbd,0x92,0xff,0x16,
+  0x65,0xa3,0xab,0x10,0x9e,0x3c,0xae,0x73,0xc1,0xc5,0xff,0xa9,0x90,0x24,0xb3,0x1f,
+  0x8e,0xa7,0x40,0xed,0xd6,0x35,0xbd,0xcf,0xac,0x7f,0x0f,0xe8,0xbc,0xdf,0x8b,0x15,
+  0x11,0x32,0x32,0xf8,0xa7,0x28,0x6a,0xcf,0x97,0x2d,0x6e,0xd8,0xc8,0x27,0x2e,0x9d,
+  0xb2,0xe3,0x0f,0xe3,0x66,0x20,0xe8,0x9c,0x63,0x7f,0x06,0xcd,0x7e,0x86,0x0b,0x18,
+  0xc8,0x39,0x43,0x3e,0x86,0x1b,0xf5,0x0d,0x98,0x08,0xfb,0x90,0x67,0x88,0xc4,0xdf,
+  0x80,0x55,0x11,0x9f,0xc1,0x3f,0x73,0x79,0xfe,0x8b,0xa1,0xf1,0x44,0xf7,0x6c,0xf8,
+  0x25,0x3c,0xad,0x7b,0x23,0x64,0x39,0x9c,0xd5,0x07,0x30,0x83,0x56,0x1b,0x7f,0x31,
+  0xd0,0x64,0x26,0x0a,0x1d,0xbc,0x04,0x49,0x8c,0xff,0xc0,0xa2,0x61,0xa2,0xa9,0x71,
+  0x4e,0xc3,0x16,0xa3,0x30,0x88,0x69,0x2f,0xea,0xd1,0xb6,0xc6,0xcd,0x8c,0xd8,0x21,
+  0x47,0xff,0xba,0xd4,0x63,0xf2,0x7f,0x56,0x11,0x69,0x4b,0x57,0x70,0x26,0xd2,0xa2,
+  0xda,0x79,0x22,0x8c,0x4d,0x5c,0x32,0xac,0xf9,0xbe,0x9e,0x89,0xff,0x54,0x6c,0x53,
+  0xf7,0x40,0x63,0x64,0xd1,0xeb,0x4d,0x12,0xe9,0x2d,0xe2,0xb0,0x67,0xb9,0x64,0xe9,
+  0x13,0x13,0x61,0x28,0x14,0xbe,0xe3,0xac,0x87,0xad,0xd2,0x36,0x93,0xbd,0x9c,0x50,
+  0x66,0xc2,0xd0,0xd0,0x6c,0x7d,0xbd,0x2a,0x22,0x82,0x65,0x8f,0x8d,0x1d,0x14,0x79,
+  0xe9,0x5f,0xe2,0xb6,0x4c,0xff,0xc3,0xf7,0x54,0xab,0x3f,0xb6,0x8a,0xd5,0x3a,0x46,
+  0xb8,0xd3,0x6c,0x14,0x29,0xf3,0x8e,0x88,0xc3,0xa6,0xa2,0x12,0x2e,0xfe,0x73,0x9d,
+  0x6a,0x81,0x9c,0x58,0xf9,0x51,0xe9,0x88,0xde,0x24,0x6f,0x30,0x13,0x61,0xc7,0x33,
+  0x8c,0x2c,0x9f,0x1b,0xff,0xc8,0x92,0xc9,0xff,0x91,0x93,0x65,0x93,0xfa,0xfd,0x50,
+  0xf3,0xf8,0xa2,0x71,0x71,0x85,0xf4,0x54,0xd4,0x4f,0x95,0x34,0xdb,0xa1,0xdf,0xcf,
+  0x2b,0xe2,0x5d,0xfd,0x0f,0x65,0x33,0xfe,0x53,0x3b,0x17,0xc8,0x6b,0x68,0x6d,0x52,
+  0x8a,0xe0,0xf7,0xc2,0x00,0x56,0xa4,0x96,0x91,0xc5,0xd0,0x65,0xda,0x9f,0x03,0xce,
+  0x7a,0x33,0xfb,0x1f,0x36,0xa6,0x2b,0x3b,0xc9,0x2f,0x91,0x48,0xaf,0x2b,0x06,0xb9,
+  0x13,0x9e,0x32,0x5f,0xdb,0x2a,0x58,0x63,0x06,0x82,0xb6,0x3b,0xe3,0x03,0x95,0x26,
+  0xff,0x87,0xc3,0x9e,0x43,0x74,0xa7,0xe6,0xeb,0x50,0x66,0x48,0xe7,0xe8,0x96,0xb4,
+  0x6f,0xa9,0x78,0x9f,0xf6,0x92,0x19,0x08,0x7a,0x6f,0xa6,0x3d,0x5e,0x2e,0x36,0xf1,
+  0x8f,0x92,0x6c,0x3b,0x56,0x38,0x1e,0xbd,0x0f,0xbb,0xbb,0x38,0x16,0xe6,0x58,0xeb,
+  0x29,0xd3,0xd1,0x67,0xe2,0x3f,0x51,0xc9,0xec,0xff,0x5c,0x32,0x29,0x86,0xe1,0x45,
+  0xa3,0x39,0xea,0x1b,0x67,0x7f,0xe8,0x1c,0xef,0xff,0xac,0x3c,0xc7,0x80,0x16,0x4f,
+  0x64,0x8c,0x66,0xf0,0x0f,0xe2,0x19,0x52,0xdf,0xae,0x2c,0x2d,0xf3,0xea,0x3f,0xd1,
+  0x66,0x77,0xf6,0xe9,0x58,0xbf,0x1f,0xb9,0xd6,0x50,0xbe,0x46,0xaa,0xe8,0x1a,0x73,
+  0x22,0x6e,0xbc,0xc1,0xed,0x55,0xc2,0xd3,0x59,0x38,0x17,0xbe,0x5f,0x58,0x2d,0x28,
+  0x3a,0xa7,0x3d,0xf3,0x34,0x5f,0x95,0xfa,0x90,0x39,0x7e,0x58,0xb3,0xf5,0xaf,0x57,
+  0xf0,0xb6,0x1b,0xbf,0x51,0x66,0x97,0xc9,0xb4,0x9f,0xd4,0x36,0x2d,0xaa,0x2a,0x3b,
+  0x28,0x0d,0x88,0xb5,0xd8,0x11,0xc8,0x4b,0x36,0x72,0xfb,0x73,0xc9,0x91,0x8c,0x7f,
+  0xe4,0xfb,0xfd,0xb0,0x51,0xb2,0xdb,0x5f,0xcc,0xac,0x4d,0xe8,0x5e,0x5f,0x21,0x73,
+  0x73,0xc7,0x99,0xbf,0xf3,0x25,0xc8,0x7c,0x78,0xdd,0xec,0xe8,0x32,0xe2,0xac,0x9f,
+  0xa4,0x6a,0xf2,0x7f,0x96,0x3c,0x27,0xbe,0x2f,0x4d,0x0e,0x85,0xf5,0x0d,0x4e,0xfc,
+  0xa7,0x87,0xd9,0xf3,0xf7,0x4c,0xa8,0x70,0x34,0xb7,0xff,0x8f,0xce,0xdc,0xe2,0x39,
+  0xfd,0x10,0x34,0x83,0xd7,0xe8,0x7e,0x16,0xce,0x19,0xff,0x1d,0xc3,0xf8,0xf3,0xa5,
+  0xb7,0xd4,0x66,0xac,0x00,0x4a,0x3b,0xeb,0x67,0xc8,0xc2,0x3f,0x72,0x6a,0xdf,0xef,
+  0x61,0x7b,0xfb,0x56,0xcd,0xd3,0x2f,0x62,0x45,0xfc,0xbd,0x86,0xe2,0x65,0xf6,0x73,
+  0x9d,0xbe,0x15,0x03,0x0b,0x49,0x77,0xff,0x43,0xe4,0xe7,0x8c,0xc8,0x5b,0xc8,0x31,
+  0x2d,0x5e,0xe4,0x5f,0xc6,0xf0,0xc0,0x0e,0x18,0x14,0x98,0x9b,0xee,0x27,0x38,0x9e,
+  0x3b,0xee,0x3c,0xfe,0x4f,0x3a,0xd0,0x44,0x8e,0x2d,0x48,0xea,0xda,0x42,0x0f,0x78,
+  0x16,0x4b,0x03,0xbc,0x50,0x97,0x19,0xea,0x98,0x69,0x9f,0x63,0x5d,0x60,0x7f,0xe4,
+  0x20,0x3f,0xdf,0xc1,0x3b,0x10,0x1b,0xc3,0xb2,0xe2,0x22,0x2f,0xfd,0xcc,0x0e,0xb6,
+  0xfe,0xff,0x16,0x19,0xa7,0x55,0x6c,0xa3,0xca,0xfd,0x4b,0x3a,0x8f,0xff,0xc3,0xbe,
+  0x3d,0x0c,0x67,0xb4,0xb0,0xc8,0xa6,0x79,0x46,0xfa,0x03,0xdc,0x60,0xf8,0x74,0x66,
+  0x91,0xce,0x99,0x40,0x68,0xfb,0xcc,0x0c,0xfe,0x39,0x0f,0x07,0xd5,0xeb,0x52,0xde,
+  0x49,0xf1,0x6e,0x38,0xbf,0xa6,0x45,0x0d,0x0e,0x96,0x7f,0xa0,0xff,0xca,0x15,0xff,
+  0x41,0xc1,0x85,0x7f,0x2a,0x0f,0x42,0x97,0x36,0x87,0xca,0x83,0x6c,0xbe,0x7b,0x69,
+  0xc3,0x03,0x95,0x83,0x65,0x26,0xff,0xc7,0x8e,0xff,0x64,0xe3,0x1f,0xb9,0x00,0x0f,
+  0x1d,0xd8,0x16,0xb7,0xea,0xfd,0x83,0x95,0x28,0x50,0xd7,0x7e,0x3c,0x98,0x83,0x7f,
+  0x0a,0xd6,0x93,0xbe,0xd5,0x33,0xa9,0x6c,0x45,0x4b,0xb6,0x2a,0xd8,0x4f,0xdb,0x1d,
+  0x3f,0x61,0x42,0x6b,0x06,0xff,0x20,0xff,0x67,0xff,0xc8,0x1c,0x1a,0x4c,0x71,0xb7,
+  0x1b,0x0e,0x79,0xcd,0x6d,0x42,0x06,0x21,0xa3,0xf0,0x13,0xa7,0xbf,0x13,0xf6,0x3f,
+  0xfc,0x18,0xae,0x8c,0x39,0xe8,0xd7,0x8b,0x49,0x41,0x37,0x3e,0xe4,0xf8,0xc7,0xdd,
+  0xff,0x19,0x7e,0xa7,0xce,0x5b,0xed,0xb5,0x60,0x39,0xa7,0x3d,0x67,0x21,0x70,0x9e,
+  0x98,0x76,0xc5,0x7f,0x1a,0xb0,0x1b,0x76,0x97,0x1d,0xf6,0x39,0x5c,0x90,0x22,0x1f,
+  0x68,0x7b,0xb3,0x9f,0x9f,0xfc,0xc1,0xf9,0x79,0x0d,0x69,0x49,0xbc,0x3b,0xe9,0xdf,
+  0x22,0x9b,0xb4,0x9f,0x06,0xea,0x47,0xfd,0xec,0xca,0xd1,0x8f,0x8b,0xff,0xac,0x7e,
+  0x91,0x81,0xa8,0xea,0xa4,0x19,0x06,0xd9,0x56,0x9f,0xc4,0xfe,0x3f,0xf4,0x69,0x5a,
+  0xec,0xc4,0x7f,0x38,0xfe,0x49,0xd8,0xeb,0xad,0x43,0xc6,0xfc,0xfe,0x33,0x34,0x18,
+  0x12,0x3f,0xa0,0xbf,0x4e,0x86,0xe9,0xe7,0xe7,0x95,0x1f,0x4a,0xf0,0x13,0x31,0x10,
+  0xff,0x7c,0xd5,0x14,0x5c,0xf8,0xa7,0xe0,0x59,0xc2,0x40,0x4e,0x0f,0x6a,0x43,0x3f,
+  0xcd,0x04,0xaf,0x8b,0x1f,0x95,0x21,0x4a,0x65,0xe1,0x9f,0x17,0xa0,0x89,0x22,0xdb,
+  0x1c,0x77,0x67,0xc3,0x8b,0xb3,0xf5,0x63,0x6e,0x6d,0x32,0xf8,0x67,0xe4,0xd2,0xcd,
+  0x0c,0xf6,0xd4,0x60,0x3d,0xc5,0x19,0xa4,0x4d,0xa6,0xab,0xec,0xfa,0x2f,0x25,0x23,
+  0xf8,0x33,0xf8,0x07,0xcf,0xbf,0xd8,0x60,0xcf,0xf7,0x07,0xb4,0x7e,0x5c,0x5e,0x75,
+  0xd7,0x5b,0x19,0x22,0x90,0x25,0x64,0xf0,0xcf,0x0a,0x89,0x81,0x46,0x9d,0x6d,0x7b,
+  0x4d,0x74,0xdd,0x30,0x2a,0xbb,0xd4,0xe8,0x08,0xd9,0xfd,0x9f,0x99,0x59,0xe8,0x0a,
+  0xe2,0xee,0xf8,0x0d,0xa9,0xa5,0x67,0x87,0x19,0xf6,0x09,0xdb,0xf1,0x9f,0x70,0x0e,
+  0xfe,0x11,0xb6,0x90,0xc9,0x8e,0xe7,0x54,0x13,0xff,0x48,0x76,0xfd,0x57,0x4e,0x22,
+  0xcc,0x8d,0x7f,0x66,0xd2,0x21,0x61,0x00,0xc3,0x02,0x76,0x7c,0xa0,0xf5,0x9d,0x5c,
+  0x06,0x48,0x16,0xfe,0xf9,0x6b,0xe8,0x8d,0xfa,0x97,0xf2,0xfe,0x3f,0xd7,0x33,0x47,
+  0x1c,0x47,0x1a,0xb3,0x2b,0x22,0xd4,0x90,0x8d,0x7f,0xe6,0x16,0x48,0xd0,0x5b,0xba,
+  0x15,0xd9,0xd1,0x38,0xbe,0x21,0x22,0x27,0xca,0xc6,0xd4,0xdc,0xf1,0x2f,0x39,0xeb,
+  0x2d,0x50,0x51,0x00,0x5d,0xba,0x16,0xa9,0xe3,0xb4,0x1f,0xf0,0x62,0x1b,0xc0,0x17,
+  0x9d,0x08,0x89,0x25,0xb4,0x1a,0xce,0xf8,0xb9,0xc5,0x1d,0xfc,0xb4,0x0b,0x6b,0x9a,
+  0x33,0xc0,0xcb,0x69,0x4e,0x39,0xf3,0x3d,0x97,0xa9,0x7f,0x67,0xf8,0xe7,0x6c,0x7b,
+  0x8b,0x5e,0x6c,0xce,0xee,0xc6,0xd1,0xff,0xe6,0x9a,0x66,0x86,0xf8,0xe4,0x8a,0xff,
+  0x7c,0x0c,0xfb,0xa3,0x4d,0x11,0x4b,0x3f,0x2d,0xba,0x94,0x10,0x3f,0x26,0xfb,0x73,
+  0xc7,0xbb,0xfa,0x3f,0x1b,0x94,0x46,0x6b,0x64,0x19,0xe3,0x3f,0x73,0xa1,0x01,0x02,
+  0xb4,0x2c,0x4d,0xe3,0xae,0x8e,0x88,0x1c,0xff,0x64,0x9d,0x7f,0xb1,0x7a,0x41,0x35,
+  0xf6,0x73,0x1e,0x9e,0xbd,0x93,0x57,0xbb,0xb3,0x69,0x76,0x65,0xcf,0x97,0x8c,0x66,
+  0xf0,0x8f,0xb4,0x8d,0xac,0xd6,0x6b,0x38,0x7b,0x9c,0xab,0xb1,0xd2,0x8e,0xbf,0x15,
+  0xb9,0xf4,0xf9,0x4e,0x56,0xfc,0x07,0xdb,0x5a,0x06,0x33,0xbf,0x6f,0xf9,0x18,0xe4,
+  0x3e,0x7f,0x06,0xff,0xf0,0xf3,0x2f,0x12,0xce,0xb7,0xf3,0xb9,0x10,0xca,0xd5,0x4f,
+  0xf6,0xf9,0x17,0x23,0xd1,0x66,0xec,0xb6,0xc4,0xb5,0x5d,0xee,0xa5,0x9f,0x32,0x89,
+  0x67,0xee,0x85,0xe7,0x8e,0xff,0x78,0xc8,0x3a,0x5c,0xff,0xb8,0x9e,0x1f,0x81,0x46,
+  0x06,0x84,0xc8,0x69,0x75,0x9d,0x15,0x11,0x32,0xf3,0x5f,0x49,0x72,0x40,0xd3,0x9d,
+  0xf1,0x4b,0x8c,0x6e,0xe4,0x73,0xb2,0xb7,0x03,0x1b,0x67,0x25,0x8b,0x42,0xe4,0x7d,
+  0x1e,0xaf,0xf0,0xb8,0xde,0x97,0x57,0x9c,0xf7,0x8b,0x96,0x56,0x30,0x90,0x53,0x83,
+  0xd5,0xdf,0x6f,0xd2,0xa7,0x21,0x38,0x8a,0xfd,0x7f,0x6a,0xd7,0x66,0xde,0x5f,0x0c,
+  0x95,0xb4,0x8e,0xd8,0xb7,0x87,0xb8,0x7c,0x19,0x03,0x21,0x3b,0x93,0x0c,0xff,0xfc,
+  0x8a,0x47,0x7b,0xea,0x57,0x31,0x27,0xf4,0x5b,0xec,0x08,0x6d,0xe5,0xbf,0x10,0xff,
+  0xbc,0xe2,0xb7,0xc7,0xcb,0x05,0x49,0xac,0xff,0xa2,0x8d,0xb6,0x19,0x2f,0x99,0xc2,
+  0xde,0x96,0xef,0x23,0xf6,0xf3,0x40,0xc5,0x73,0x70,0x3a,0x61,0xb7,0xfd,0x49,0xb4,
+  0xa4,0xbd,0x27,0x79,0x23,0xa0,0x6c,0xff,0xe5,0xc6,0x3f,0xdf,0x81,0xe7,0x28,0x82,
+  0x96,0x9b,0xdf,0x84,0x5d,0xf4,0x06,0x43,0xbe,0x87,0x9c,0x86,0xb5,0xd9,0xf6,0xa7,
+  0xcc,0x5d,0xff,0xd5,0x0f,0x4f,0x6b,0xd5,0x49,0xf3,0x5b,0xad,0xde,0x08,0xdc,0x73,
+  0xdb,0xe6,0x9c,0xf1,0xf7,0xb8,0xea,0xdf,0xb5,0x0a,0xca,0x94,0x9c,0xa4,0x76,0x99,
+  0xf3,0x11,0xa6,0x58,0x23,0x2b,0x9e,0x8f,0xad,0x39,0x8e,0x64,0xc5,0x7f,0xb0,0x6d,
+  0x14,0x67,0x4b,0xe2,0xec,0xe4,0x14,0x6f,0x04,0x94,0xed,0x5f,0x46,0x5c,0xf5,0xb0,
+  0xbf,0x51,0x27,0xb1,0x7f,0xb8,0xf5,0x6d,0x7a,0x09,0x06,0x8e,0x9c,0x42,0x30,0x1c,
+  0x7f,0x25,0x32,0x88,0xec,0xf1,0xd5,0xea,0x69,0x38,0x2b,0x37,0x6b,0xdc,0x8c,0xff,
+  0x9e,0x59,0xef,0xa0,0x75,0xfe,0x85,0xdb,0x9e,0xd7,0xa4,0x97,0xdb,0xe3,0xb7,0x48,
+  0xcb,0x60,0x70,0x42,0x83,0x80,0xd9,0x76,0x0f,0x81,0x50,0xeb,0xb1,0x5c,0xff,0x4b,
+  0x3e,0x74,0x7e,0x5f,0x8c,0xff,0xb0,0xdd,0xc1,0x2d,0xb6,0xbf,0xbe,0x8b,0x9f,0x7f,
+  0xf1,0xbd,0x9c,0xf1,0x69,0xf7,0xfe,0x0b,0x52,0x9a,0x5f,0xe7,0x6c,0xf0,0x5d,0xa1,
+  0xa0,0x1e,0xc0,0x40,0x50,0x77,0xb6,0x7d,0x6e,0x75,0xf3,0x9f,0x57,0xc0,0xc9,0xc0,
+  0x00,0xac,0xc7,0x34,0x04,0xf3,0xbf,0x7a,0xd5,0x4e,0xce,0xff,0xc9,0xd6,0x4f,0x3a,
+  0x27,0xff,0xd5,0x02,0x25,0x13,0x35,0x58,0xff,0x85,0xd9,0x8a,0x9a,0xb1,0x5c,0xff,
+  0x55,0x3e,0x7e,0xb3,0x13,0x3f,0x01,0xd2,0x03,0x5b,0x20,0x80,0xe5,0x1f,0x17,0x16,
+  0xc0,0xfd,0x91,0xb0,0x3a,0x56,0x67,0x16,0xf8,0x13,0x04,0xf7,0xa7,0x07,0xaa,0x41,
+  0xd6,0x89,0xfa,0x49,0xc2,0xff,0xca,0xfd,0xa9,0x59,0x6e,0xf8,0x89,0x82,0xeb,0xf3,
+  0xc9,0x03,0x4d,0xe1,0x7f,0xe5,0xfe,0x7f,0xea,0xe7,0x3f,0x99,0xfe,0x55,0x3c,0xcb,
+  0x0f,0x81,0x51,0x95,0xf1,0x09,0x82,0xf4,0x3f,0x7d,0xff,0xff,0x87,0xf5,0x2f,0xa9,
+  0xf4,0x3f,0xa0,0x73,0xc1,0x15,0x5f,0xfa,0xd3,0x3e,0xf3,0xe7,0xff,0x47,0x46,0xf9,
+  0x7c,0xff,0x93,0xb7,0xff,0x7f,0xe1,0xd3,0x72,0xfe,0xfc,0x79,0xe3,0xdf,0x11,0xfe,
+  0xbf,0x3c,0xfe,0x3f,0xd9,0xfb,0x78,0xd1,0x1e,0x5e,0xb4,0x87,0xff,0x0b,0xfa,0xbf,
+  0x68,0x0f,0xff,0xbd,0xcf,0x7f,0x36,0xfb,0xf3,0x9f,0x6b,0xbc,0x51,0x70,0x5c,0x5f,
+  0x4c,0x9b,0x6b,0xbd,0x77,0xce,0x0c,0xc3,0x47,0x74,0x2f,0xb6,0xad,0x08,0x3b,0x19,
+  0x67,0x27,0x3e,0xe6,0xe2,0x47,0xa5,0x69,0x07,0x4d,0x0a,0x6c,0xff,0xd8,0xc0,0xdb,
+  0x22,0x2d,0xe4,0xf9,0x41,0x1e,0x16,0xf3,0x4f,0x15,0x1f,0x03,0x03,0x9b,0x5e,0xc6,
+  0xe3,0x04,0xd3,0x34,0x24,0x60,0xec,0x07,0x77,0x21,0x98,0x1d,0x1f,0x73,0xf1,0xc3,
+  0x93,0xea,0xc3,0x98,0xd6,0x97,0xfd,0x41,0xd8,0xab,0xf9,0x0f,0x5f,0x8e,0xf1,0xc6,
+  0x1b,0x72,0xf0,0x76,0xa6,0x3f,0x80,0x50,0xf1,0x18,0x19,0xa1,0x73,0x54,0x6f,0x82,
+  0x04,0xd9,0xf3,0xcf,0x9b,0x28,0xbe,0xbf,0x2d,0x98,0x17,0xbf,0xca,0xf4,0xc7,0xd8,
+  0x02,0x4f,0xe9,0xc7,0x92,0x2d,0xf0,0x3f,0x46,0xc5,0x33,0xc2,0x79,0xfa,0xbc,0x31,
+  0xc3,0x70,0xc7,0x7f,0x9e,0x37,0x05,0x77,0x7e,0x70,0x5b,0x74,0x3f,0x69,0xa2,0xde,
+  0x2e,0x93,0x0d,0x3e,0x51,0xb2,0x5a,0xdc,0xf1,0x49,0xf1,0x31,0xe9,0x2a,0xe8,0x92,
+  0xb7,0x6e,0x96,0xbf,0x4d,0x70,0xe3,0x10,0x48,0xb3,0xd7,0xd5,0x95,0x41,0xde,0x9b,
+  0x46,0x21,0x36,0xe1,0xe2,0x87,0xaf,0x80,0x01,0xa8,0xc3,0x32,0x52,0x54,0x4b,0xd2,
+  0x50,0x3c,0x56,0x63,0x67,0x53,0x3f,0xe9,0x60,0x4e,0x7e,0x50,0xb8,0x0c,0xd6,0xd0,
+  0x6b,0x56,0x74,0x4c,0x62,0x7d,0x5c,0xe2,0x9a,0x68,0x91,0xc9,0x97,0xce,0x8e,0x17,
+  0xb9,0xf2,0x83,0x72,0x80,0xfe,0x5a,0x9d,0x6b,0x78,0x03,0xa2,0x17,0x3e,0x4a,0x86,
+  0xc6,0x7d,0xb2,0x49,0x8b,0x32,0xe3,0x63,0x1f,0xe5,0xc5,0xc7,0xae,0x18,0x24,0x7f,
+  0x84,0xeb,0x46,0x96,0xfc,0xce,0x6a,0x2b,0x71,0xab,0x26,0x1e,0x73,0x35,0x12,0xcf,
+  0x8d,0x8f,0x05,0xa4,0x1d,0x70,0x40,0x9a,0xa3,0x7b,0xf9,0xf9,0x71,0x14,0xd2,0x6c,
+  0x23,0x9f,0xaf,0x1f,0x17,0x3f,0x4a,0xc5,0xfe,0x6c,0x8d,0x7a,0xdc,0xac,0xaf,0xb9,
+  0x96,0x6d,0xb4,0x39,0x3f,0x3c,0x6b,0x7f,0xea,0xe2,0x47,0x61,0x7e,0x90,0xb3,0xbf,
+  0x56,0x90,0xef,0xc3,0xf3,0xb4,0xc6,0x08,0x8c,0xb0,0xf9,0x7e,0x37,0x67,0xbe,0x99,
+  0xfd,0x60,0x47,0xc5,0x7a,0xbe,0x1b,0x2d,0xd2,0xb0,0xdf,0x4b,0x59,0xed,0x6e,0xd9,
+  0x4f,0x16,0x7f,0x62,0x7c,0xec,0x71,0xc2,0x9e,0x9f,0x3e,0x9e,0x94,0x03,0xf0,0x0c,
+  0x6d,0x4e,0xca,0x69,0xb2,0x3d,0x13,0x1f,0x3b,0x6e,0x1e,0x1d,0xe2,0xe6,0x47,0x1d,
+  0xd5,0x90,0x04,0x55,0x32,0xcc,0xa3,0x13,0xf7,0x95,0x35,0xf6,0x64,0xc5,0xc7,0xf4,
+  0xbc,0xf8,0xd8,0x3b,0x66,0x37,0x80,0x8d,0x58,0x1f,0x67,0x34,0xac,0xe8,0x78,0x44,
+  0xb4,0x0f,0x4a,0x43,0x6a,0x74,0x92,0x77,0xc8,0x71,0xf3,0xa3,0xfe,0x0a,0x7a,0x69,
+  0x43,0x34,0xb0,0xc9,0x83,0xf5,0x71,0xc1,0xa5,0xf2,0x65,0xa2,0x9b,0x31,0xa5,0xf1,
+  0x44,0x55,0x32,0x93,0x1f,0x04,0x89,0x7c,0xbb,0xf6,0x2b,0xc3,0xf2,0x1d,0xd6,0xf9,
+  0x68,0x0b,0x13,0x7e,0x6c,0x94,0xe4,0xc4,0xc7,0x66,0x22,0x51,0xdc,0xdd,0x1f,0xe9,
+  0x0a,0xb2,0x1a,0xea,0x23,0x81,0x3b,0x78,0x77,0x20,0x1c,0x0f,0xed,0x30,0x2b,0x13,
+  0x2f,0x02,0x24,0x0e,0xc5,0x9c,0xfd,0xe9,0xaa,0x22,0x9d,0x9f,0x86,0xe6,0xd5,0x45,
+  0x7e,0x1a,0xac,0x30,0x23,0xab,0x50,0x6b,0x12,0xe6,0xa0,0xd0,0xe0,0xae,0x8f,0x23,
+  0xa7,0xed,0x68,0xcf,0x6f,0xb0,0xcd,0x51,0xe4,0xdf,0x89,0x8f,0x9d,0xd0,0x5f,0x85,
+  0x5d,0x7a,0x70,0x54,0x6c,0x87,0xb3,0x50,0xbd,0xa0,0x3e,0x22,0x2e,0xcf,0x8c,0xff,
+  0xd8,0x2c,0xb5,0x7b,0x27,0x8b,0x1f,0x1e,0x07,0x3c,0x84,0x1a,0xf0,0xe0,0x36,0x3f,
+  0xc8,0x49,0x6c,0x8b,0x24,0xcc,0x04,0x85,0xde,0x36,0x45,0x7c,0x4c,0xbf,0x69,0x6c,
+  0x63,0xaf,0xa4,0xe1,0x21,0x20,0x3d,0xea,0x4e,0x61,0xab,0x7e,0x29,0xe7,0x87,0x63,
+  0x87,0xcc,0x0c,0x3f,0xdc,0x95,0x1f,0xc4,0xf3,0x6d,0x7b,0x05,0xde,0x54,0x61,0xb9,
+  0xf7,0x71,0xf0,0xdf,0x01,0x66,0xa3,0xec,0x99,0xd9,0xf1,0x46,0x57,0x7c,0x6c,0x18,
+  0x86,0xf4,0xa6,0x68,0xf0,0x21,0xd1,0xac,0x8f,0xbb,0x69,0x93,0xeb,0xf9,0xe5,0x3d,
+  0xb9,0xf1,0xb1,0xf7,0xb0,0x3f,0x12,0x84,0x6f,0xf3,0x25,0x94,0x6d,0xea,0x49,0x2d,
+  0x1c,0xed,0x9e,0x2a,0x7e,0x98,0x9d,0x1f,0x1c,0xe1,0x24,0xb4,0x05,0x49,0x12,0x67,
+  0xda,0x6e,0xef,0x69,0x4b,0xe6,0xe8,0xbf,0xab,0xdb,0x15,0x1f,0x5b,0x3d,0x57,0x5e,
+  0x47,0x1b,0x13,0xf2,0x78,0xd9,0x5c,0x69,0x8d,0x50,0x9d,0xfc,0xec,0x5d,0x24,0xa0,
+  0x22,0x63,0xaa,0xcf,0x6c,0x94,0x84,0xad,0x23,0xb3,0xce,0x87,0xf5,0x41,0x37,0x6d,
+  0x18,0x96,0x07,0x63,0x1d,0x68,0xa8,0x7b,0x2e,0xf3,0xbb,0xed,0x4f,0x12,0x89,0x1c,
+  0x81,0xc2,0x0c,0x3f,0xaa,0x1a,0xae,0x80,0xb5,0x3a,0xf6,0x47,0x8a,0x5d,0xc6,0xfb,
+  0x7b,0xdc,0x90,0x26,0x55,0xc2,0xd3,0x50,0x6c,0xbe,0xbf,0x4f,0x61,0xe8,0x29,0x5a,
+  0x98,0xe1,0x47,0x05,0xe2,0x61,0xde,0x0d,0xc0,0x3b,0xa9,0x3c,0xa2,0xbe,0x44,0xaf,
+  0x4d,0x96,0x2c,0x6d,0xfb,0xbe,0xf0,0xc7,0x1e,0x8b,0x31,0x75,0x82,0x5e,0x8b,0xad,
+  0x03,0x32,0xfc,0x28,0x4f,0x15,0xf2,0x85,0xe6,0x83,0x0f,0xdb,0xd4,0xe3,0xdb,0xb7,
+  0x38,0x99,0x09,0xfb,0xf0,0x46,0x40,0xd8,0x4a,0x31,0x93,0x1f,0x6c,0x5d,0x8d,0x6c,
+  0xab,0xe6,0x80,0x6f,0x5c,0xac,0x83,0x0f,0x13,0xb0,0xc3,0xfb,0x2e,0x3f,0x28,0xad,
+  0x25,0xad,0x60,0xa0,0xec,0x0c,0xfa,0xaf,0x23,0xee,0xf8,0x58,0x69,0x0a,0x69,0x09,
+  0xa0,0x74,0x15,0x7e,0xc1,0x78,0x92,0xce,0xde,0x1e,0xa8,0x41,0x43,0xa4,0x9a,0xc4,
+  0x27,0xfd,0x29,0x95,0xd7,0xa7,0xb8,0xf3,0x83,0x09,0xec,0x67,0x3b,0xa2,0x44,0x3c,
+  0x95,0xf0,0x94,0x56,0xb3,0x5e,0x4e,0xfb,0x6d,0x7b,0xe5,0xe7,0xfd,0x91,0x70,0xfc,
+  0xb0,0x63,0x7f,0xa2,0x15,0x18,0x0d,0xab,0x05,0xa5,0x84,0x99,0x8a,0x01,0x5a,0x0b,
+  0x95,0xdc,0x10,0xd9,0x0c,0xb4,0x9d,0xe6,0xd1,0x18,0x6f,0x64,0xf2,0x83,0x15,0x14,
+  0xf3,0x0b,0x43,0x8b,0x1e,0x2a,0x0a,0xc0,0x71,0xb9,0x69,0xa7,0xbc,0x43,0x59,0x89,
+  0xb4,0x1f,0x6e,0x3f,0xa5,0x49,0xe4,0x3f,0x53,0x71,0xc4,0xf5,0x3c,0x3f,0xc2,0xf7,
+  0x4b,0xf5,0x6d,0x2b,0x67,0x66,0x4a,0x7f,0x6e,0xd0,0xf7,0x63,0x77,0xfc,0x70,0xd2,
+  0xd4,0x8f,0x9b,0x1f,0xf5,0x2c,0x7b,0xbf,0x9a,0xd3,0xde,0x09,0x71,0x12,0xce,0xd1,
+  0xeb,0xf0,0xb4,0xee,0xf9,0x19,0x7f,0x77,0x26,0xc9,0x84,0x03,0x62,0x86,0xcf,0x3c,
+  0x24,0xd5,0x63,0x13,0x95,0xd9,0xf2,0xb6,0xd8,0x38,0x3c,0x13,0x49,0xa6,0x8b,0x35,
+  0xd1,0x66,0x4c,0x95,0x1d,0x83,0xc1,0x5b,0x98,0x50,0x1b,0xcb,0xd8,0x1f,0x5a,0xa0,
+  0x69,0x7d,0x18,0x5f,0xdd,0xe8,0x67,0xe3,0xf5,0x99,0x29,0xf9,0x31,0xb7,0xbf,0xc3,
+  0x7a,0x2e,0x5e,0xc1,0x6a,0xaf,0x07,0x59,0xc2,0xea,0x7e,0x3f,0xa2,0xd8,0x91,0xae,
+  0x81,0x4a,0xff,0xc6,0xa2,0x24,0xb1,0x19,0xc2,0xad,0x07,0x21,0x25,0xf1,0xa3,0x55,
+  0x32,0xf6,0x07,0x8a,0xa3,0x48,0x7b,0xc0,0xb6,0x00,0x98,0xad,0x98,0x73,0x64,0xf1,
+  0x3f,0x67,0x0a,0xb1,0x1d,0xfd,0xb8,0xfb,0x43,0x9a,0xa7,0x81,0x34,0xee,0xeb,0x9e,
+  0xd4,0xcf,0x69,0x2d,0x23,0x7f,0x79,0x97,0xdb,0xbf,0x9f,0xc9,0xe5,0x87,0xef,0x13,
+  0xce,0x49,0xe7,0x63,0x6c,0x91,0xac,0xaa,0x09,0xc3,0xe9,0x8d,0xcd,0xe9,0x69,0x7f,
+  0xa8,0xf9,0x40,0xcd,0x89,0xaf,0xb6,0x65,0xf2,0x83,0x86,0x6c,0x83,0x9c,0xc2,0x06,
+  0x86,0x4f,0xea,0xd2,0x25,0xf7,0xb0,0xd7,0xaa,0x0f,0x2e,0x94,0x1f,0x1c,0x81,0xf5,
+  0xd2,0x2e,0xde,0x6d,0x03,0xfd,0xbb,0xa6,0x19,0x4a,0x13,0xf3,0x56,0x8f,0xe6,0xe2,
+  0x9f,0x4c,0x7e,0x50,0x72,0xf8,0xe1,0x41,0xce,0x37,0xf3,0xa4,0xc8,0xfb,0xf0,0xc3,
+  0x6c,0xfc,0x73,0x5b,0x26,0x3f,0x58,0xed,0x9c,0xcf,0x45,0x9c,0xb2,0xac,0x77,0xb3,
+  0xf8,0x75,0x28,0x8c,0x66,0xf2,0x83,0xa5,0xcf,0xc2,0x79,0xc9,0x62,0x43,0xa1,0x5a,
+  0x6e,0x9d,0xa8,0x39,0x6d,0x76,0x04,0xb2,0xae,0xb0,0xaf,0x6a,0xb2,0xf3,0x83,0x66,
+  0x7f,0x24,0xa4,0x45,0x15,0xf2,0xfb,0x6b,0x2e,0xff,0x2e,0x9b,0x8d,0x3b,0x1c,0xfb,
+  0x73,0x84,0xf3,0xe5,0x4a,0x0c,0x65,0x2e,0x5f,0x06,0x73,0x86,0x94,0x09,0x22,0xc3,
+  0xde,0x64,0x36,0x7e,0x3b,0xee,0xfc,0xbc,0x23,0x19,0xbe,0xdc,0x62,0x9b,0xd8,0xdc,
+  0xa1,0x36,0x3b,0xfa,0x51,0x73,0xf2,0x83,0x13,0x2a,0x43,0x3b,0x5d,0xf5,0xc8,0x86,
+  0x42,0xd8,0xc3,0xd9,0x50,0x5f,0xa0,0xb9,0xf8,0xe7,0x9c,0x93,0x1f,0x5c,0x51,0x69,
+  0xf2,0xc3,0x97,0x34,0x29,0x8b,0x19,0x3e,0x09,0xa1,0xb0,0x90,0x7e,0x02,0xfe,0xa9,
+  0x30,0xf9,0xe1,0xd3,0x26,0xac,0x78,0xb5,0x6f,0x42,0x19,0x74,0xf1,0xc3,0xd5,0xbc,
+  0xfc,0xa0,0x83,0x76,0x56,0x0a,0xfc,0x7c,0x96,0x5d,0x4a,0x50,0xce,0xc5,0x3f,0xae,
+  0xfc,0x60,0xd1,0x66,0x37,0xda,0xa9,0x36,0xfa,0xbe,0x4a,0x2a,0xff,0x9d,0xfc,0x60,
+  0x66,0x76,0x5d,0xd5,0x58,0x0d,0x77,0x59,0x1e,0xde,0x73,0xf1,0xa3,0x24,0x2c,0x2a,
+  0xe4,0x41,0x78,0xa6,0x3d,0x01,0xf5,0x59,0x56,0x3f,0x05,0xfe,0xb1,0xc7,0x9b,0xfc,
+  0xa8,0x30,0x92,0x46,0xc6,0xed,0xb2,0xb8,0xb9,0x59,0xf9,0xc1,0xae,0x2b,0x73,0xf8,
+  0x51,0x82,0xed,0x7d,0x24,0x8b,0x1f,0x9e,0xd6,0x1c,0x7f,0x34,0x78,0x41,0x7e,0x94,
+  0xe9,0xdd,0x9a,0x98,0xf7,0x2c,0xdf,0x26,0xff,0xdc,0x70,0xae,0xe4,0xf1,0xa3,0x2c,
+  0xbe,0xd3,0x03,0xb1,0x31,0x69,0x8f,0x60,0xd2,0x72,0xd4,0x5e,0x3d,0x9c,0x61,0x80,
+  0xe7,0xe4,0x07,0x6b,0x33,0xe8,0x68,0x27,0xba,0x69,0x95,0x6c,0x83,0x87,0x1d,0xfc,
+  0x63,0xf3,0xa3,0xec,0x8f,0x56,0x61,0xf2,0xc3,0x8b,0x4c,0x5a,0x94,0xa6,0x5f,0x5e,
+  0x81,0x6d,0xb1,0x17,0x78,0x6d,0xfc,0x93,0xc3,0x8f,0x5a,0x75,0x05,0xe7,0x47,0x09,
+  0xbf,0xa2,0xad,0x69,0x98,0x60,0x50,0x7d,0x09,0x53,0x15,0xbc,0x91,0xf1,0xbf,0x26,
+  0x3f,0xca,0x59,0x3f,0x9c,0x1f,0x25,0x85,0xf9,0x31,0x1f,0x12,0x4e,0x7c,0xc9,0x26,
+  0x6c,0x14,0xc9,0x1b,0x63,0x4e,0x85,0x7f,0x4c,0x7e,0x14,0x07,0x39,0x56,0x7d,0xfd,
+  0xc6,0xee,0xe5,0x70,0xd6,0x22,0x4e,0xc3,0x59,0xb3,0x83,0xa2,0x8b,0x1f,0x25,0xa7,
+  0xf9,0x79,0xb5,0xdc,0xa8,0x0e,0x4a,0x26,0x2d,0x8a,0xab,0xdd,0xca,0x0f,0xe2,0x15,
+  0x7f,0x76,0x7e,0xd0,0x02,0x39,0x92,0x3c,0x4b,0xd6,0x74,0x8f,0xba,0xb5,0x5d,0xdb,
+  0x29,0x3b,0x78,0xaf,0x96,0x09,0x33,0x33,0xf9,0xc1,0x7e,0x69,0x1b,0x3f,0x6f,0x57,
+  0x71,0x9d,0x0f,0x62,0x6a,0xd8,0xca,0x0f,0xe6,0xf0,0xa3,0x92,0x60,0xff,0xbe,0x7f,
+  0x6d,0x9e,0x0f,0x72,0x6b,0x42,0xc1,0xf3,0xa3,0x9d,0xdf,0x77,0x0e,0x12,0xc5,0x5d,
+  0xf9,0x41,0xb6,0x1e,0xcc,0xb6,0x09,0x8a,0xa3,0x8d,0xdf,0xe6,0xe9,0xe7,0x94,0x73,
+  0x3e,0xac,0xac,0x26,0xa5,0x55,0x12,0x6a,0x7b,0x6d,0x5a,0x5a,0x25,0x34,0x99,0xf5,
+  0x89,0x93,0x52,0x76,0x7e,0x36,0x73,0x3e,0xac,0xc5,0x8f,0xa2,0x4a,0x74,0x1a,0x66,
+  0x03,0x79,0x7f,0xc8,0x00,0x9c,0x33,0xee,0x33,0xf3,0x83,0x4f,0xd1,0x06,0xec,0x80,
+  0xea,0xe2,0x47,0x49,0xa6,0xf7,0x79,0xa5,0x9e,0xbd,0x1d,0x7b,0x99,0xfd,0x59,0x94,
+  0x2a,0xf3,0x7a,0x77,0x15,0xdb,0xef,0x0b,0xe5,0xc2,0x3a,0x87,0xff,0x03,0xea,0x9d,
+  0x05,0x58,0xdf,0xca,0xde,0xd6,0xcd,0x98,0x38,0x33,0xfe,0xe2,0x5e,0x52,0x45,0x7f,
+  0xa0,0x5f,0x63,0xbd,0xbf,0x3a,0x7f,0x91,0xe3,0xf6,0xed,0x41,0xee,0xff,0x22,0x4f,
+  0x02,0xf2,0xb7,0xf5,0x7c,0x62,0x56,0xda,0x77,0xfd,0xd5,0x33,0x92,0x78,0x9e,0xb5,
+  0xd3,0x28,0x92,0x09,0xeb,0x9c,0xfc,0xa0,0xc7,0xea,0x17,0xb4,0x21,0x55,0x73,0xac,
+  0xe2,0xb4,0xf6,0x1c,0xb3,0x27,0x7f,0xf9,0xbe,0x7e,0xca,0x6d,0x4f,0x4a,0x90,0x1f,
+  0x6e,0x3f,0x4f,0xb4,0xe2,0x39,0xe0,0x6c,0x96,0x93,0x35,0x3f,0x86,0x5f,0xc5,0x9b,
+  0xd3,0x4b,0x06,0x6b,0x1a,0xe4,0x73,0x3d,0xcd,0x63,0xdc,0x7f,0x9d,0xb5,0xf2,0x83,
+  0x8e,0xff,0x7a,0x02,0x36,0x33,0x23,0x50,0x3f,0x5c,0x72,0x8f,0x88,0xfb,0xa9,0x6a,
+  0xa3,0xe4,0x14,0x99,0x61,0xac,0x67,0x1b,0x31,0x9b,0x1f,0x8e,0x27,0x86,0xe4,0xf5,
+  0x07,0x60,0xe8,0xa8,0xd5,0xb4,0x57,0x0a,0x9b,0x6f,0x7c,0x1b,0x54,0x0f,0xf1,0xf9,
+  0xee,0x36,0x0d,0xd7,0x58,0xd4,0x7e,0x1e,0x8b,0x1f,0x65,0x5b,0x1b,0x6d,0xc8,0x83,
+  0x07,0x63,0xc5,0x9d,0x7a,0x67,0x9e,0x1f,0x9c,0xe9,0xc2,0x3f,0xd3,0x8f,0x55,0xec,
+  0xb5,0x67,0x77,0x1e,0xed,0xe7,0x84,0x72,0x63,0xcf,0xef,0xdc,0xf5,0xc5,0x57,0xa6,
+  0xa6,0x1d,0xe8,0xb1,0xef,0x9f,0x14,0x76,0x58,0x4a,0x68,0xcb,0x6c,0x33,0x7b,0x7e,
+  0x97,0xa3,0x9f,0x4c,0xbe,0xb2,0x5a,0xb5,0xea,0x7d,0x26,0x85,0x33,0xd2,0x79,0xf8,
+  0xaa,0xb1,0x04,0xf9,0x30,0x6f,0xd9,0x07,0x85,0x58,0x7c,0xa1,0xb4,0xe3,0x1f,0xb7,
+  0x48,0x2b,0x79,0x7d,0xba,0xf2,0x5c,0xab,0xd9,0x78,0xa7,0x2f,0x05,0x07,0xd5,0x27,
+  0xa8,0xd5,0xb8,0xd2,0x8e,0x3f,0x38,0xbf,0x2f,0x2d,0x58,0x69,0x9e,0x0f,0xbb,0x93,
+  0x1c,0x93,0x76,0x71,0x1a,0x33,0x1c,0x83,0x7e,0x6a,0xf1,0xc9,0xf7,0xe0,0x51,0x6b,
+  0x29,0x92,0x14,0x6c,0xff,0x25,0xab,0xa6,0xbf,0xbb,0x9c,0xeb,0x47,0x4b,0x22,0x1e,
+  0x38,0x16,0x4f,0xba,0xf4,0x63,0x88,0x21,0xb2,0x2f,0xc3,0x8f,0xaa,0x5c,0x09,0xa7,
+  0xdb,0xb9,0x7f,0xc7,0x7a,0x25,0x3f,0x7b,0xda,0xb6,0x37,0x4f,0x1c,0x21,0x4d,0xe6,
+  0x95,0x49,0x73,0xe2,0x49,0xe2,0xe0,0x9f,0x07,0xce,0x08,0x9c,0x1f,0x3e,0x8a,0xfc,
+  0x96,0x52,0x26,0x9c,0x68,0x3b,0x43,0xcf,0x5c,0x30,0x3f,0xc8,0xfb,0x23,0xc9,0xcd,
+  0xc3,0x0c,0x9f,0x37,0x70,0xb4,0x53,0x6c,0xc2,0x9e,0xeb,0xd8,0x8a,0x6a,0x9b,0x22,
+  0xfe,0x63,0xf4,0x7f,0x20,0x3f,0x17,0x9d,0x33,0xcc,0xcf,0x47,0xdb,0x6b,0xb6,0x45,
+  0x42,0xd8,0x33,0x33,0xad,0x0c,0x4c,0x89,0x7f,0x0a,0xd8,0xa4,0x64,0xbf,0x2e,0xa7,
+  0x42,0x5e,0xde,0xa6,0xb8,0xc8,0x71,0x43,0x4d,0x53,0xc6,0x7f,0x18,0xfe,0x79,0x86,
+  0x99,0xf1,0x4a,0xeb,0xbc,0xdd,0x21,0xd9,0x05,0x1b,0xa6,0x88,0xff,0x2c,0x98,0x7e,
+  0x4c,0x9d,0xe8,0x6a,0xf2,0x07,0x43,0x08,0x0b,0x0b,0xef,0xc3,0xfa,0x38,0x07,0x11,
+  0x1d,0xb3,0x81,0xf4,0xa8,0x63,0x7f,0x52,0xc2,0xb3,0x30,0x99,0x08,0x2f,0xf7,0x4d,
+  0x74,0x9b,0xda,0x68,0x9c,0xc8,0xeb,0x0f,0xe0,0x8e,0xff,0x8c,0xaa,0xc8,0x46,0x1b,
+  0x18,0x95,0xa7,0xa2,0x45,0x31,0x41,0xcd,0xe3,0x47,0x05,0x61,0x30,0x91,0x34,0xe2,
+  0xe6,0xf9,0x32,0xc1,0xac,0xc7,0xce,0x3c,0xbf,0x8b,0x1f,0xbe,0x98,0x19,0xe1,0xa4,
+  0x5e,0x34,0x3b,0xa3,0x0d,0xb7,0x20,0x73,0x60,0x7c,0xca,0x85,0x7f,0xbe,0x08,0x4f,
+  0xf6,0x57,0xaf,0xfc,0x1b,0x66,0x4f,0xf4,0x0c,0x0c,0x48,0x66,0xe1,0x01,0x2d,0x13,
+  0xff,0x59,0x21,0x2f,0x86,0x0f,0xd5,0xd4,0xe2,0xfa,0x59,0xe2,0x21,0xde,0x28,0xc0,
+  0x77,0x83,0x78,0x08,0x3e,0x4a,0x66,0xe1,0x1f,0xc1,0x85,0x7f,0xa6,0x3f,0x0b,0x67,
+  0x13,0x2d,0x8b,0x6f,0xb5,0xd9,0xf2,0xca,0x04,0x9f,0xe6,0x05,0xf9,0x51,0xc8,0xcf,
+  0xf7,0x36,0x61,0x37,0xc8,0x43,0x79,0xb4,0xb4,0x29,0xe2,0x3f,0xe3,0x95,0x9b,0xf9,
+  0xe9,0x42,0x72,0x27,0xb9,0x33,0x97,0x96,0x60,0x09,0x7d,0xee,0xf8,0x0f,0xc7,0x3f,
+  0x46,0x75,0x5a,0x5e,0x55,0xf8,0x96,0x15,0xf6,0x99,0xf9,0x56,0x1e,0xfe,0x49,0x67,
+  0xe3,0x1f,0x43,0x9b,0x90,0x11,0x4f,0x76,0xe7,0xeb,0x73,0x2a,0x7e,0xd4,0xb9,0x9e,
+  0x5d,0xdb,0x83,0x88,0x76,0xde,0xc8,0xa6,0x45,0x91,0x29,0xf9,0x51,0x49,0x98,0x90,
+  0xc3,0x64,0x09,0x15,0xf2,0x69,0x42,0x53,0xf2,0xa3,0xd0,0x3f,0xa6,0xf0,0x90,0x08,
+  0xdb,0xbb,0x95,0xbb,0xf7,0xfb,0x74,0x4e,0x2e,0xfe,0x59,0x0e,0x7b,0x0c,0x3f,0xd6,
+  0xdb,0x8e,0x41,0x2e,0xcd,0x89,0x21,0x1c,0x3a,0x05,0xfe,0xd9,0xab,0xf9,0xdb,0xe5,
+  0x8d,0x53,0x8e,0xdf,0xa3,0xce,0xcc,0xe6,0x87,0x6b,0x77,0x60,0x13,0xec,0xe4,0xe7,
+  0x64,0x17,0x3b,0x68,0xd8,0x6e,0x0b,0xe0,0xe0,0x9f,0x0c,0x3f,0x61,0x15,0xdb,0x7f,
+  0x9d,0x62,0xb3,0x09,0x4e,0x35,0x4d,0x27,0xfe,0xe3,0xea,0x0f,0xc9,0xf0,0xcf,0xbf,
+  0xe8,0x2d,0xa3,0x8d,0xa3,0xd6,0x34,0x97,0x4c,0x15,0xdf,0xc8,0xa9,0x8f,0x4b,0x36,
+  0xaf,0xf2,0x46,0xc4,0xd9,0x80,0x6d,0x91,0xae,0x74,0x0d,0xdb,0x66,0x37,0x0a,0x78,
+  0xc9,0xc5,0x8f,0x62,0x20,0x67,0xfb,0xd6,0xeb,0x65,0x4a,0x92,0x24,0x43,0x8b,0x12,
+  0x78,0xc7,0x24,0x1b,0xff,0xe4,0xf0,0xa3,0xd8,0x7c,0xb1,0xe9,0xa5,0x94,0x47,0x8b,
+  0xea,0xe1,0xf3,0xed,0xcb,0x8a,0xff,0x70,0x7e,0xbe,0xd6,0x2e,0x63,0x35,0x5c,0x2f,
+  0x34,0x2c,0x58,0x94,0xad,0x4f,0xb2,0x35,0x37,0xfe,0xc3,0x61,0xed,0x3d,0x8b,0x13,
+  0x6d,0xb5,0x9c,0x16,0xa5,0x64,0x3d,0xff,0x49,0x86,0x97,0xf2,0xf9,0x51,0xcc,0x82,
+  0x5a,0xc7,0xa2,0x85,0x5d,0x6d,0x10,0x9c,0x7e,0x11,0xb9,0xfc,0x28,0x06,0x32,0xd5,
+  0x60,0x2c,0x3b,0xec,0x66,0x0b,0x02,0xf6,0xc3,0xc9,0xa9,0x8f,0x7b,0x8e,0xfa,0x69,
+  0x20,0xca,0xb6,0x5d,0x76,0xa1,0x9c,0x64,0x0b,0xf0,0x94,0xce,0x05,0x77,0xfc,0x67,
+  0x31,0xec,0xd5,0x35,0x23,0x30,0x77,0x8a,0x30,0xe9,0x41,0x86,0x77,0x83,0x26,0x3f,
+  0xdc,0xfe,0x7d,0xa9,0x7a,0x27,0x3c,0xaf,0x57,0x63,0xfc,0x27,0x13,0xb6,0x35,0xdb,
+  0x7a,0x74,0x32,0x84,0x60,0x15,0xce,0x67,0xe2,0x3f,0xf1,0xf8,0x17,0xe1,0x63,0x3c,
+  0x04,0x76,0x95,0xf2,0xc5,0x4c,0xa1,0x1c,0x0a,0x1b,0xcc,0xf8,0x0f,0xbf,0x92,0xd5,
+  0x1f,0x52,0xbd,0x07,0x9e,0x8b,0x34,0xa6,0xf2,0xc2,0xc8,0x3b,0xed,0xf8,0x8f,0x9b,
+  0x1f,0x4e,0x7a,0x90,0x1f,0xde,0x3c,0xe1,0x1d,0xe7,0x6e,0x2b,0xcc,0x61,0x8f,0xce,
+  0x77,0xf4,0x93,0x62,0x58,0x3a,0x67,0xfa,0x2f,0x57,0x7d,0x1c,0xb3,0x3f,0x4f,0xa2,
+  0xfd,0x89,0x9a,0xd6,0x26,0xcd,0x66,0x77,0x88,0xee,0x4a,0xb2,0xc7,0xfe,0x90,0x54,
+  0xa9,0x16,0x9e,0xc9,0xc6,0x3f,0x3b,0xd5,0xea,0xa8,0x3d,0x7e,0x04,0xe7,0xab,0x3f,
+  0x1d,0xaa,0x37,0xf9,0xf0,0xbb,0xf3,0xea,0xe3,0x98,0xfd,0x19,0x00,0xb6,0xde,0xb4,
+  0x2c,0xb3,0x23,0x7a,0x87,0x98,0xd9,0xb7,0x8e,0xc6,0x08,0x65,0xd5,0xc7,0x1d,0x53,
+  0x3f,0xd2,0x9b,0x22,0xcc,0x7f,0x99,0x8d,0x56,0xac,0xf9,0xce,0x40,0x33,0x1b,0xe4,
+  0xfe,0x9d,0x01,0x0f,0x57,0x3c,0x0a,0xf1,0x4f,0x34,0xdc,0xe1,0xf4,0x47,0xb2,0xc6,
+  0xdf,0x67,0xc5,0x7f,0x74,0xab,0xc3,0x92,0x7d,0x7f,0xc4,0x3f,0x67,0x81,0xa1,0xc1,
+  0x09,0x2b,0xec,0xc3,0xcf,0x3b,0x38,0x2f,0x70,0x33,0x3e,0x1f,0x2c,0x60,0x90,0xa9,
+  0x8f,0x63,0xf8,0x87,0x6d,0x9a,0xb6,0xa6,0x95,0xdd,0x84,0x37,0xfa,0x33,0x5c,0xfe,
+  0xd7,0x13,0xc4,0xf3,0xb9,0x4c,0xbe,0x53,0x56,0x7d,0x1c,0xf3,0xef,0xca,0x1a,0x62,
+  0x35,0x96,0x4c,0xb5,0x1e,0xcb,0x44,0x30,0x06,0xa3,0xb9,0xfc,0x28,0xb6,0xdf,0xdf,
+  0xc3,0x8d,0x8c,0xc7,0xdb,0xfe,0x20,0x12,0xcb,0x99,0x7e,0xd6,0xef,0xd2,0x82,0x66,
+  0x84,0xc4,0xd2,0x4f,0x76,0x7f,0xc8,0x93,0x30,0x0b,0xd9,0xe0,0x3c,0xec,0x73,0xe0,
+  0xd6,0x27,0xc5,0xf7,0x75,0xab,0x62,0x2e,0x68,0xe3,0x9f,0x4c,0x7d,0xdc,0x96,0x2b,
+  0x32,0xd1,0x1e,0xb3,0x2d,0xd2,0x71,0xf1,0x98,0x7e,0x7a,0x85,0x3b,0xfe,0x33,0xe1,
+  0xee,0x0f,0xc0,0xf0,0xcf,0x19,0xd8,0x15,0x65,0x78,0xe9,0x3e,0x38,0x1d,0x6b,0x4e,
+  0x17,0x0f,0x8b,0x61,0x3c,0x16,0xdc,0x1d,0xff,0x99,0xe6,0xce,0x7f,0xfd,0x58,0x45,
+  0xfb,0xac,0x7c,0x9b,0xe3,0x1f,0x7f,0x5a,0xde,0xc6,0x84,0x75,0x39,0xf1,0x1f,0x57,
+  0x7f,0x6c,0xe9,0x20,0x53,0x1a,0x33,0x32,0x66,0xda,0x6b,0x85,0x51,0x34,0x87,0xed,
+  0x47,0xa8,0x83,0x00,0xcd,0xf9,0xba,0xfa,0x63,0x97,0xee,0x80,0x3d,0x68,0xe4,0xe3,
+  0xbc,0xad,0x50,0x1d,0xc3,0x57,0x03,0x41,0xe8,0xd5,0x2f,0x84,0x7f,0x34,0xec,0x8f,
+  0x44,0x07,0xa2,0xbe,0x4a,0xab,0x2c,0xab,0x78,0xbb,0xd8,0x18,0x3b,0xa0,0x67,0xfb,
+  0xdf,0x51,0xc7,0x3e,0x60,0x7f,0x00,0xe6,0xd6,0x6f,0xf2,0x19,0xe2,0x19,0xf5,0xbc,
+  0x74,0x9d,0xb1,0x21,0x29,0x9e,0x87,0xf3,0x46,0xb6,0x7f,0x9f,0xcc,0x89,0xff,0x34,
+  0xad,0xf0,0xf5,0x30,0x6d,0xbf,0xa2,0x86,0x47,0x7c,0x4f,0x62,0xa3,0x86,0xc8,0x85,
+  0xf9,0xe1,0x41,0xb6,0x69,0xf2,0x47,0xfa,0x92,0xe2,0xdd,0xb5,0xff,0x3a,0xea,0x35,
+  0x94,0xc1,0xa6,0x12,0xad,0x6f,0xdf,0x85,0xe2,0x3f,0x46,0xc1,0x62,0x48,0xc5,0x70,
+  0x1b,0x1e,0xf3,0x32,0x7f,0xed,0x3d,0xc1,0xb4,0xe7,0xe5,0xfa,0xb9,0x00,0x3f,0x5c,
+  0x98,0x21,0x3c,0x69,0x2c,0x5b,0xde,0xb7,0x82,0x7c,0x91,0x7e,0x17,0x61,0xcf,0x3f,
+  0x90,0x30,0x5d,0x63,0xd8,0x78,0x20,0xc6,0x85,0x23,0xba,0xbd,0xde,0x56,0xc8,0x5e,
+  0xe6,0xaf,0x43,0xfa,0x12,0x98,0x56,0x42,0x5f,0x48,0x72,0xfc,0x53,0x12,0x1b,0x62,
+  0x2f,0xda,0x95,0x19,0xfc,0xf3,0x99,0xec,0xfe,0xd8,0x0c,0xed,0xe8,0xbe,0x6a,0xf1,
+  0x4d,0x86,0xb7,0x71,0x76,0x97,0x1f,0xc1,0xf3,0x1a,0xb2,0x1b,0x69,0xe6,0xf4,0x87,
+  0x6c,0x8a,0x32,0xff,0xc5,0xd7,0x27,0xb6,0x25,0x2f,0x0e,0xed,0x17,0xe6,0x0d,0x39,
+  0x85,0xae,0x4b,0x52,0x6d,0x4f,0x64,0x9d,0x8f,0x86,0x87,0x2a,0xca,0x9d,0x9e,0xaa,
+  0x8a,0xeb,0x78,0xa3,0x24,0x4f,0x45,0x1e,0x10,0xca,0xee,0x0f,0xb0,0x8b,0xd6,0x44,
+  0xe5,0xa5,0xb1,0x19,0xbc,0x51,0x52,0xd1,0x5c,0x12,0x86,0xd5,0x31,0x6b,0xbe,0x3f,
+  0x30,0xf1,0x4f,0x4e,0x7f,0x80,0x7d,0x49,0x43,0x9e,0x43,0x38,0xde,0xd6,0xaf,0x49,
+  0x95,0x11,0xc0,0x7e,0x14,0x45,0x17,0xc0,0x3f,0xdb,0xe1,0x5c,0xaa,0x89,0x7a,0x8f,
+  0x29,0x01,0xf8,0x06,0x36,0x8a,0x4c,0x97,0x7b,0xc8,0x21,0xb3,0x3e,0x6e,0x1c,0xfb,
+  0xad,0xa1,0xf0,0x4c,0x5e,0x7f,0xec,0x46,0x1e,0xff,0xd1,0x39,0x4d,0xf7,0x68,0xfb,
+  0x24,0xbd,0x30,0xfe,0x19,0x83,0x0f,0xb7,0x62,0xb5,0x94,0xf8,0x65,0x7a,0x52,0x0d,
+  0x47,0x7d,0x8f,0xd4,0x04,0x69,0x2e,0x7f,0x38,0x07,0xff,0xe8,0xfe,0x7b,0xcd,0xb0,
+  0x43,0xbc,0x81,0x9f,0x8f,0x46,0x7b,0x69,0x16,0xb0,0x11,0xb3,0xfa,0x63,0x4b,0x7b,
+  0xe4,0xba,0x0e,0xfb,0x58,0x90,0x76,0xfc,0x87,0x72,0xce,0x78,0x86,0x7f,0x6c,0xfd,
+  0xc8,0xed,0x92,0x6a,0x66,0x7f,0x3c,0x12,0xa6,0xbd,0x96,0x29,0x55,0x08,0x0c,0xf4,
+  0x6c,0x60,0xb0,0xcf,0x59,0x9f,0x66,0x7f,0x80,0x67,0x80,0x29,0xc1,0x2e,0x94,0x53,
+  0x34,0x32,0x42,0x1a,0xb2,0xe6,0xfb,0x81,0xeb,0x7c,0xb4,0x31,0xf9,0xac,0x7e,0xad,
+  0xbe,0xe4,0xb0,0xc9,0x0f,0xd7,0x37,0x1c,0xbe,0x3c,0xbb,0x03,0x00,0x0a,0x39,0xfd,
+  0x21,0x79,0x13,0xc8,0xee,0xaf,0xc1,0xc7,0xb8,0x2d,0x3d,0xde,0x3d,0x1b,0x5e,0xd3,
+  0x11,0x38,0x65,0x10,0x42,0x76,0xfe,0x6b,0xb0,0xbd,0x06,0x94,0x9e,0x32,0xcd,0x44,
+  0x3b,0x6b,0x48,0xb2,0xf2,0xc2,0xfc,0x70,0xec,0x0f,0xf0,0x2f,0x50,0xa0,0x2f,0x9a,
+  0xeb,0xb7,0x27,0xbe,0xb1,0x10,0xba,0xcc,0xc6,0x98,0xce,0x7c,0x8d,0xac,0xfe,0x48,
+  0x4f,0xc2,0x0f,0x0c,0x65,0x23,0xb1,0x1a,0x2f,0xa4,0x18,0x10,0xea,0xd3,0x1b,0x2e,
+  0x94,0xff,0x42,0x7c,0x4b,0xe7,0x44,0x97,0x24,0x14,0xeb,0xfc,0x97,0x07,0xc5,0x5a,
+  0xb2,0x7f,0xf4,0x42,0xfc,0xf0,0xed,0x18,0x2f,0x0a,0xcc,0xeb,0x30,0xd1,0x91,0xf4,
+  0xd4,0x72,0x5f,0x62,0xd1,0x72,0x26,0x34,0x98,0x07,0xe3,0x5a,0xe3,0x73,0xfb,0x03,
+  0x60,0xd8,0xa7,0x9b,0xe1,0x1f,0x8d,0x09,0x3d,0xdd,0x5b,0x61,0x44,0x6f,0xca,0xd2,
+  0xbf,0x0b,0xff,0x48,0x01,0xf9,0x99,0xb8,0x9f,0x2a,0xcb,0xc5,0x15,0xf2,0x53,0x20,
+  0x26,0xfb,0xd2,0xa4,0x12,0xee,0x17,0xfd,0x36,0x3f,0x1c,0xf1,0x8f,0xdf,0xcd,0x0f,
+  0x67,0xf6,0xc7,0x48,0x8a,0xec,0xa5,0x90,0x74,0xb6,0x11,0x1b,0x56,0x9e,0xf5,0x78,
+  0xed,0xb2,0x5c,0xe7,0x7d,0xc9,0xe0,0x1f,0x4d,0xa8,0x9a,0xfe,0x3c,0x6c,0xd9,0xa7,
+  0xe0,0xfe,0xe5,0x69,0xb9,0x1a,0x8a,0xbe,0xe6,0xa9,0x90,0xd7,0xec,0xab,0x76,0xbf,
+  0xbf,0xad,0x23,0x8e,0xfd,0x09,0xf0,0xfe,0x00,0xfc,0x58,0x10,0x2e,0x68,0xcc,0xad,
+  0x3c,0x42,0x5e,0x73,0xf5,0x47,0x42,0xe1,0x80,0xbb,0x3f,0x80,0xfc,0x21,0x1a,0xd5,
+  0x50,0x0d,0x5a,0x4b,0x36,0x3b,0xe6,0xdd,0xd4,0x53,0xd2,0x7d,0x59,0xf6,0x36,0x83,
+  0x7f,0xf0,0x7c,0x34,0x3c,0x0d,0x8d,0xdd,0x24,0xac,0x9f,0xa6,0xcd,0xcb,0x79,0x22,
+  0xec,0xb5,0x9e,0x96,0xf4,0x92,0x49,0x61,0x2a,0x7e,0x78,0xe9,0x66,0xfd,0xa9,0xe4,
+  0x16,0x43,0xb9,0x87,0xd9,0xdb,0xa7,0x13,0x5b,0x0a,0x4b,0xaa,0x63,0x84,0xf6,0xa8,
+  0x59,0x7c,0xef,0x9c,0xf8,0xcf,0xf3,0x81,0x65,0x12,0x56,0xcf,0xc1,0xd3,0xc2,0x35,
+  0x05,0x97,0x47,0x49,0x65,0x72,0x75,0x8e,0xbd,0x1a,0x73,0xfc,0x45,0x14,0xed,0x8f,
+  0xac,0x61,0x98,0x9a,0x97,0xe5,0xc2,0x17,0xe4,0x32,0x91,0xc4,0x8d,0x6c,0x7b,0xee,
+  0xaa,0x8f,0x9b,0xbe,0x03,0x3e,0xa2,0xfe,0xa3,0x4b,0x76,0x63,0xff,0x61,0x61,0x5e,
+  0x74,0xc9,0xe0,0x0d,0x75,0x30,0x62,0xe4,0xc4,0xcf,0x73,0xfb,0x03,0x54,0x58,0xc7,
+  0xc2,0xce,0xc1,0x46,0x91,0x47,0x61,0x32,0x32,0x23,0x6b,0xfc,0x58,0x56,0x7f,0x80,
+  0x73,0x94,0x1f,0x03,0x7a,0xde,0x2c,0x1c,0xbb,0x57,0x9c,0xad,0x1d,0x93,0x79,0xfc,
+  0xc7,0x69,0x05,0x33,0xe6,0xee,0x0f,0xa0,0xee,0x1d,0xf1,0x4f,0x28,0xcf,0xc6,0x8e,
+  0xa1,0x37,0xd7,0x94,0x67,0xc9,0x1a,0x7f,0xdc,0x98,0x93,0xed,0x7f,0x5d,0xfd,0x01,
+  0x18,0x5e,0xd2,0xb6,0x8e,0x28,0xd8,0x16,0x69,0x6f,0x65,0x43,0x94,0xbd,0x7d,0x75,
+  0x10,0xa7,0x7e,0xe3,0x02,0xfc,0x70,0xf0,0xc2,0xde,0x6a,0x5e,0x0d,0xf7,0x2a,0x1e,
+  0x14,0x0b,0x0a,0x10,0x1a,0xa2,0x76,0xbd,0xbc,0x19,0x1a,0x72,0xf3,0xc3,0x65,0xe6,
+  0xd6,0x85,0x7b,0x0d,0x66,0x0d,0xde,0xc7,0x46,0x01,0xcc,0x10,0x29,0x9a,0x31,0x6e,
+  0xc6,0xc7,0x1c,0x84,0x9c,0x5d,0x1f,0x37,0xa9,0xf2,0x26,0xd8,0x67,0xe0,0x0f,0x2b,
+  0x5a,0x60,0x43,0xa4,0x7b,0x34,0x37,0xfe,0x93,0x83,0x7f,0xce,0x63,0x13,0xd1,0x93,
+  0xe2,0xf3,0xf0,0x7b,0xa3,0x69,0x79,0xc9,0x49,0x86,0x7f,0x5e,0xa5,0xb3,0x10,0x48,
+  0xcf,0xd0,0x5f,0x4b,0xb4,0x8c,0x2d,0x7e,0x97,0xe4,0xf5,0x47,0x1a,0x91,0x07,0xf8,
+  0xb1,0x17,0x18,0xd8,0x29,0x0b,0xd2,0xee,0x6a,0xff,0x88,0x32,0xd0,0x1a,0xa4,0x7d,
+  0x1a,0xfb,0x2a,0x49,0x92,0x79,0xfd,0x91,0x18,0xcc,0xdb,0x41,0x77,0x69,0x75,0x1d,
+  0x0b,0x9b,0xfc,0xde,0xda,0x98,0x17,0x4f,0xf0,0xdc,0xe8,0x95,0xbb,0x11,0x01,0x6a,
+  0x59,0xfd,0x21,0xcd,0xec,0x61,0x20,0x44,0x82,0xfa,0xf7,0xa0,0xae,0x9d,0xe1,0x4f,
+  0xaf,0x8e,0x19,0x46,0xcc,0x28,0xe9,0xd8,0xa8,0x9c,0xdd,0x3f,0x83,0x7f,0xc0,0x3a,
+  0x1f,0x84,0xb9,0xdd,0xf5,0x4c,0xd8,0xae,0x17,0xa6,0xd8,0x42,0xea,0x33,0x36,0xa2,
+  0x5a,0x02,0xfe,0x57,0xba,0xc2,0x06,0xdb,0xda,0xeb,0xf9,0xe7,0x83,0x4c,0x28,0x58,
+  0x2f,0x70,0x1d,0x76,0xfb,0x39,0x83,0xfd,0x91,0x46,0xd9,0x95,0x49,0x38,0xdf,0xcf,
+  0xbe,0x4a,0x8b,0x83,0xf9,0xe7,0x83,0xa4,0xba,0xd9,0x1f,0xd2,0xb0,0x71,0x3d,0xf6,
+  0xeb,0x90,0xc3,0xc3,0xec,0x2f,0xbe,0x0f,0xaf,0x40,0xd3,0x70,0xf6,0xf9,0xb0,0x3c,
+  0xff,0x15,0x4c,0xb3,0xf5,0xc3,0x14,0xa5,0xb3,0xf5,0xf0,0x1c,0xf9,0x3d,0xe5,0x8d,
+  0x26,0x06,0x63,0x07,0xa3,0xbf,0x30,0xe6,0x4c,0x28,0x3f,0xce,0x3f,0x1f,0x64,0x98,
+  0xcd,0xee,0xe0,0xf0,0x5e,0x23,0xb8,0x82,0x8d,0x7f,0x8d,0xee,0x55,0x97,0xbf,0x5b,
+  0x89,0xf1,0xb1,0xee,0x17,0xb4,0x51,0xe5,0xb1,0x29,0xce,0x07,0x71,0xba,0x21,0x59,
+  0x42,0x4d,0x1a,0x56,0x91,0x73,0x0b,0xbe,0x8b,0x19,0xb1,0x15,0x65,0x59,0xfd,0x91,
+  0xd4,0x4c,0xb6,0x4b,0xae,0xba,0x4b,0x99,0x45,0x10,0xf6,0xcc,0x36,0xf0,0x7c,0x10,
+  0x7d,0xbf,0x1c,0x32,0x7c,0xb9,0xe7,0x83,0x58,0x41,0xc2,0x63,0xbc,0x91,0xa6,0x95,
+  0xf6,0xba,0x0e,0x4f,0x8c,0x3d,0xa3,0xff,0x0b,0x06,0x82,0xd2,0x79,0xf8,0x67,0x7e,
+  0x9a,0x97,0xb1,0xfc,0x82,0xce,0xd3,0x17,0xe3,0x79,0xd6,0xaf,0x98,0x07,0xd5,0x8d,
+  0x43,0x1f,0xb6,0x4e,0x4a,0xe6,0xf5,0x47,0xc2,0xf3,0xa9,0x35,0x6c,0x8b,0x5d,0xa3,
+  0x63,0xa1,0x0d,0x6c,0x80,0x6b,0x75,0xbe,0x91,0xe4,0x47,0xc7,0x46,0x0b,0x33,0xf8,
+  0x67,0xc8,0xca,0x7f,0x1d,0x58,0xa5,0x9d,0x83,0xb5,0xf4,0x9a,0xa8,0x8c,0xf5,0x35,
+  0x1b,0x68,0xf5,0x84,0xb2,0x94,0xbc,0xa5,0xae,0x8e,0x55,0x23,0x35,0x28,0xb7,0x3f,
+  0x52,0x10,0xb7,0x2d,0x2f,0x61,0x37,0x80,0x68,0x47,0x88,0xc1,0xf2,0xee,0xce,0x99,
+  0x08,0xcb,0xb1,0x11,0x10,0x3f,0x0a,0xd3,0x85,0x7f,0xbe,0x63,0xe6,0xbf,0x4a,0xd8,
+  0x43,0xd2,0x03,0xc2,0xbc,0xc7,0xbd,0x28,0x1c,0x5a,0xe0,0xa7,0xbe,0x27,0xc4,0x23,
+  0xfe,0x03,0x64,0x80,0xfa,0xa2,0xf9,0xe7,0x83,0x64,0xbc,0x0f,0x02,0x21,0xf6,0xfb,
+  0xcc,0xc1,0x8a,0xb9,0xa3,0x74,0x92,0x84,0xd5,0x9c,0xf3,0xd1,0xac,0xd3,0xaf,0x12,
+  0x62,0x2d,0xec,0xa7,0x25,0x18,0x08,0xfa,0x32,0xdc,0x42,0xe7,0xb5,0x7b,0x13,0xe5,
+  0x33,0xe9,0xc3,0xc9,0x70,0x2e,0xff,0xc7,0xea,0x8f,0xbd,0x99,0xcc,0xa4,0xbd,0x46,
+  0x43,0xa7,0xdc,0x4f,0xae,0x86,0xae,0x61,0xff,0x5d,0x72,0x7f,0x8c,0x01,0x21,0xbd,
+  0x61,0x05,0x73,0xcd,0x79,0xfd,0x21,0x75,0xe5,0x21,0x22,0xd1,0xde,0x48,0xb0,0x5d,
+  0x2e,0x8d,0xfd,0xd5,0xc2,0x1f,0x46,0xea,0x74,0x79,0x63,0x19,0xfb,0x4a,0x6e,0xe8,
+  0x78,0x25,0x51,0x98,0xd7,0x1f,0x29,0xa2,0x54,0x10,0x2c,0x94,0x0b,0x46,0x64,0x14,
+  0xae,0xc1,0x83,0x33,0x2a,0xc8,0x55,0xb0,0x85,0x5d,0x51,0x36,0xb9,0xfa,0x43,0x0e,
+  0x9a,0xfd,0xb1,0x29,0x3f,0x1f,0xd6,0x60,0x42,0x90,0x96,0x47,0x61,0x05,0xcc,0xc3,
+  0xb6,0x48,0x00,0x13,0x3c,0x03,0xd8,0x96,0xc5,0xff,0xb1,0xf2,0x59,0xca,0x09,0x5e,
+  0xef,0xc6,0x66,0x77,0x58,0xfe,0x25,0x13,0x1a,0x47,0xc5,0x13,0xf0,0x4b,0xf3,0xab,
+  0x4c,0xfc,0xa7,0x9f,0xe7,0xbf,0xbe,0xd5,0x5e,0xc2,0xbd,0xbf,0xde,0xa4,0x7b,0x13,
+  0x6d,0x57,0x61,0x59,0x7d,0xbb,0xb7,0xb4,0x86,0x09,0x6c,0x6b,0xec,0xdd,0x94,0x8b,
+  0x7f,0xf0,0xf4,0x9c,0x98,0x3f,0x4d,0x07,0x61,0xab,0x2c,0xc7,0x62,0x5a,0x6c,0x9d,
+  0x96,0x64,0x02,0xdb,0x58,0xe1,0xd1,0x69,0xb2,0xe1,0xc2,0x3f,0x60,0xf5,0xc7,0xf6,
+  0x44,0x62,0x87,0xb5,0x27,0xb5,0xea,0xd6,0xa2,0x48,0x61,0x05,0xac,0x96,0x19,0x02,
+  0x8f,0x90,0x0a,0xba,0x5a,0xe3,0xc2,0xbe,0xbc,0xfe,0xd8,0xf2,0x28,0x39,0x41,0x9f,
+  0x04,0xa1,0xbd,0x08,0x8f,0xfd,0x5a,0x0d,0x7c,0x58,0x15,0xc5,0xf5,0xc9,0xbe,0xca,
+  0x8d,0xff,0x34,0xe8,0xfc,0xf9,0xb1,0x2d,0x40,0x3d,0x6f,0x04,0x9a,0x68,0x8a,0x06,
+  0xf1,0x7c,0x34,0x7e,0x34,0x5e,0x82,0x8c,0x5f,0xa0,0x3f,0x36,0x09,0xb3,0x7f,0xa8,
+  0x8c,0x51,0xde,0x31,0x60,0xa3,0x38,0x46,0x4e,0x26,0x9e,0xd3,0x1b,0x13,0xdd,0x79,
+  0xfd,0x91,0xb4,0xc5,0x31,0x51,0xc3,0xf3,0x41,0xcc,0x83,0xd2,0x4c,0x41,0xac,0xa6,
+  0xbc,0x63,0x95,0xe1,0x3e,0x1f,0x6d,0x35,0xe6,0xbf,0x82,0x58,0x16,0x87,0xfd,0x31,
+  0xb6,0xc6,0x57,0xec,0xe8,0xfb,0xf4,0x5d,0xeb,0xd4,0xad,0x29,0x79,0x07,0xf9,0x34,
+  0x3c,0xa3,0xfb,0xd9,0x57,0xe2,0xc2,0xdc,0xfe,0x90,0xcb,0xe5,0xb9,0xa4,0x04,0xba,
+  0xe3,0xc1,0x91,0xa2,0xf9,0x64,0x09,0x74,0x1b,0xda,0xdb,0xf2,0x3c,0xe2,0x83,0x5d,
+  0x49,0x6d,0x3c,0x50,0x9b,0xdf,0x1f,0x5b,0x97,0xbf,0x49,0xae,0x14,0xd6,0xea,0xf5,
+  0x46,0x11,0x86,0x41,0xd6,0xca,0xd5,0xfb,0xe4,0x89,0xd8,0x15,0xc2,0x77,0x75,0x26,
+  0xac,0x88,0x65,0xf7,0xc7,0xfe,0x23,0x33,0x53,0xde,0x49,0x25,0x4c,0x5e,0x33,0xf3,
+  0x0b,0xf7,0xc1,0x6b,0xb4,0x3a,0xbd,0x78,0x95,0x32,0x03,0xb0,0x11,0xb1,0x97,0x21,
+  0x96,0xdc,0xfe,0x48,0x66,0x7d,0x1c,0xce,0xae,0x04,0xd1,0x3e,0xbf,0x62,0x13,0x81,
+  0x96,0xb8,0xf9,0x3f,0xcc,0x7f,0xa9,0xe7,0xf1,0xfc,0xb5,0xc9,0xf2,0xfb,0xb2,0xcb,
+  0xe2,0xbc,0x93,0x36,0x91,0x35,0x9b,0xff,0xb3,0x19,0xd9,0x3e,0x09,0x59,0x27,0x97,
+  0x18,0x6c,0xdb,0x45,0x79,0xbf,0xeb,0xa7,0x93,0x8d,0x11,0xf6,0xb3,0x56,0xe9,0x4f,
+  0xaa,0xf5,0xc3,0xca,0x6d,0x79,0xe7,0x83,0xb0,0xf9,0x4e,0x90,0xa5,0xfc,0x60,0x47,
+  0x25,0x42,0x46,0x61,0xb7,0x5a,0xaf,0x17,0x39,0x1d,0xc2,0x3b,0xca,0x32,0xfc,0x1f,
+  0xab,0x3f,0x12,0x36,0xf9,0x09,0xb6,0x76,0x41,0xb0,0x96,0xef,0x26,0x70,0x23,0x56,
+  0x34,0x8b,0x14,0x63,0x69,0xbc,0xa1,0x40,0x59,0x06,0xff,0xac,0xe0,0xf9,0xbe,0xf9,
+  0xba,0x37,0x55,0x7e,0x37,0xf4,0x59,0xf1,0x2e,0xed,0x34,0x6d,0x48,0xd7,0x0f,0x2a,
+  0x41,0x30,0x53,0x63,0x85,0x79,0xf8,0x27,0xd2,0x68,0xe2,0x9f,0xf0,0xa8,0x6f,0x9b,
+  0xf8,0xbe,0x7c,0x3a,0x12,0xee,0x29,0xd9,0x26,0x1e,0x35,0x4e,0xe1,0x79,0xe5,0x78,
+  0xb0,0x88,0x7d,0x7f,0xc3,0xec,0x0f,0x30,0xce,0xb4,0x71,0x8e,0x1e,0x62,0x02,0xb3,
+  0xde,0xe7,0xf4,0x33,0x72,0xcb,0x88,0x99,0xff,0x52,0x9b,0x13,0xde,0xb4,0x92,0xe1,
+  0xff,0x58,0xfd,0x91,0xd2,0xf2,0x93,0x0c,0xff,0xac,0x5b,0xda,0x30,0xa2,0xfc,0x88,
+  0xfc,0x1e,0xf6,0x76,0x34,0x3c,0xb0,0xe8,0xf1,0x8d,0xbf,0xd7,0x07,0x8c,0x39,0x09,
+  0xb9,0x36,0xbf,0x3f,0xa4,0x81,0x65,0xaa,0x5a,0x9f,0x60,0x6e,0xf3,0xb5,0xbd,0x6a,
+  0x9d,0x71,0x39,0x86,0xa9,0x31,0x5f,0x2c,0x27,0xf2,0xfb,0x43,0xe2,0x69,0x68,0xc3,
+  0xb4,0x5b,0x34,0x61,0xa1,0xcc,0xd3,0x1c,0xaa,0xdf,0x60,0xe3,0x6b,0xb1,0x34,0x35,
+  0x63,0x7f,0xa8,0xd5,0x1f,0x9b,0x79,0xdb,0x11,0xab,0x6c,0xb0,0xec,0x98,0x3c,0xa9,
+  0xcd,0xb3,0xf1,0x5e,0x93,0x11,0xcc,0xe6,0xff,0x98,0xfd,0x10,0x1a,0x3b,0xc5,0x63,
+  0x6d,0xa6,0xa3,0x77,0xda,0xfe,0xd8,0xf8,0xc7,0xcd,0xff,0x19,0x9a,0x3e,0xa1,0x1d,
+  0x84,0xeb,0xc0,0xbb,0x4f,0x0c,0x73,0xbe,0x2d,0x13,0x66,0x33,0xbc,0xd4,0x9c,0xce,
+  0xe2,0x3f,0x67,0xf0,0x89,0xfa,0x36,0xc4,0x47,0xb7,0xce,0x8e,0xc7,0xd9,0x16,0x30,
+  0x3e,0xe4,0xdf,0x27,0x3f,0x10,0xbb,0x1a,0x06,0xa9,0xdf,0x1d,0xff,0xf1,0x4f,0xd4,
+  0xda,0xfa,0x3c,0xc0,0x7e,0xb1,0xa4,0xb0,0x82,0xcd,0x9b,0xe1,0xe1,0x2d,0xba,0x36,
+  0xe2,0xf1,0xd7,0x15,0x43,0xca,0x3c,0x38,0xcf,0x49,0x95,0x1e,0x17,0x9c,0xf5,0xcc,
+  0xde,0xf7,0xed,0x7a,0x1d,0xc8,0xc9,0x58,0x10,0x1e,0x67,0xdb,0x90,0xc0,0x76,0x12,
+  0xa4,0x7b,0xe2,0x59,0x78,0xd2,0x9f,0xe1,0xff,0x2c,0x28,0xf8,0x80,0xa4,0xe9,0xbc,
+  0xf1,0xe0,0x77,0xd8,0x6a,0xf9,0x1d,0x6d,0x1a,0x3a,0x18,0x7f,0xa1,0x96,0x4e,0xc6,
+  0xca,0xb2,0xf0,0xe1,0xa8,0xd3,0x1f,0x29,0x59,0xfa,0x3f,0xe0,0x48,0x62,0xce,0x88,
+  0x6f,0x90,0x69,0xe3,0x57,0x70,0xa5,0xd1,0x47,0xc5,0x3f,0xb0,0x8d,0xe7,0xf3,0x17,
+  0xc8,0x7f,0x19,0xea,0xb7,0xd9,0x6e,0x2b,0x34,0xea,0xad,0xc0,0xf8,0x0f,0xef,0x86,
+  0xc4,0x84,0x23,0x34,0x1b,0x9f,0x67,0xf8,0x3f,0x06,0x5b,0x0f,0x6f,0x68,0x4d,0x86,
+  0xbc,0x87,0xd9,0x93,0xdb,0x75,0xff,0x9b,0x25,0x18,0x06,0xec,0xb5,0x0f,0x3a,0x71,
+  0xe2,0x3f,0xf6,0x7a,0x30,0x98,0x84,0x54,0x4e,0xf9,0x2a,0x8f,0x57,0x05,0x3d,0x99,
+  0x56,0x76,0xb0,0x8d,0xc9,0x46,0xe1,0x42,0xf1,0x9f,0x49,0xf5,0x36,0xb2,0x86,0xf2,
+  0x43,0xe1,0xc3,0xf0,0x7d,0x66,0x46,0x3c,0x5f,0x27,0x61,0xe3,0xa1,0x44,0x0e,0xff,
+  0xc7,0x85,0x7f,0xf0,0xfe,0x29,0x08,0x6a,0x62,0xb0,0xf6,0x05,0xb6,0xd5,0xf3,0x69,
+  0x7d,0x25,0xf4,0x5f,0x61,0xfe,0x8b,0x8a,0x13,0xff,0x99,0xe5,0xc6,0x3f,0xa5,0xcf,
+  0xb2,0x97,0x82,0x29,0xe1,0x27,0x6c,0x76,0x7f,0x34,0xfb,0x95,0x1d,0x84,0xdf,0x4b,
+  0x9f,0x90,0xff,0x22,0x6f,0xd0,0xa6,0x74,0x70,0xb0,0xa6,0x04,0xd1,0xa0,0x11,0x4c,
+  0x89,0x1d,0xf0,0xb2,0xd9,0xd6,0x63,0x2a,0xfe,0x4f,0x65,0x3f,0xf0,0xf3,0x16,0xb1,
+  0xbb,0xc8,0x6a,0x61,0x99,0x21,0x4f,0xf8,0x2b,0x3d,0xab,0xa1,0x3a,0x27,0xfe,0xe3,
+  0xd8,0x13,0x58,0x43,0x62,0x78,0x08,0xda,0x5c,0x32,0x03,0xba,0xe8,0x3f,0xa7,0xe5,
+  0x49,0xf2,0x05,0xec,0x90,0x70,0xc1,0xfe,0x00,0xeb,0xa1,0x5b,0xd7,0xc6,0x02,0xea,
+  0x65,0x5e,0xa9,0x2b,0x3a,0xd3,0x90,0x77,0x33,0x47,0xd0,0x6d,0x64,0xef,0x67,0x5d,
+  0xfc,0x9f,0xe9,0x27,0xe1,0x10,0xdd,0x95,0xf0,0x7e,0x20,0x06,0xe0,0x25,0x7d,0x0e,
+  0xf5,0xa6,0xc5,0xaf,0x63,0x23,0x8e,0x0b,0xf6,0x07,0xa0,0xd1,0xf1,0xca,0x30,0xf1,
+  0xd1,0x17,0xd2,0x65,0x93,0x9f,0x9b,0x87,0xfb,0xf1,0x34,0x9d,0x0c,0x5d,0x38,0xfe,
+  0xf3,0x98,0x1d,0xed,0x79,0x87,0xb3,0x7d,0xbc,0x9b,0x99,0x5b,0x1c,0xb2,0xfb,0x3f,
+  0xe7,0xc7,0x7f,0xe0,0xcb,0xb8,0x5a,0x18,0x08,0xc1,0x6e,0xd8,0x1a,0x59,0x1a,0xd8,
+  0x4c,0x6a,0xe1,0xe7,0xd4,0x9f,0x15,0x7f,0x70,0xe7,0xbf,0xf8,0xea,0x6a,0x55,0x12,
+  0xb1,0xb1,0x1e,0xd3,0xda,0x40,0x2d,0xf4,0xaa,0xfe,0x9c,0xf8,0x8f,0xbd,0x1e,0x90,
+  0xff,0xd3,0x95,0xc9,0xfe,0x24,0x19,0xfe,0xf1,0xd7,0xc2,0x03,0x90,0xcc,0x8a,0xff,
+  0x18,0xee,0xfc,0x17,0x19,0xe1,0xec,0x1a,0x3e,0xbb,0x10,0x30,0x7c,0xa8,0xd9,0x6d,
+  0x79,0x9c,0xf9,0xbe,0xe5,0xca,0x7f,0x7d,0x4c,0xf0,0x10,0xb4,0x0d,0x87,0x31,0x7b,
+  0xa5,0x87,0xb1,0x51,0xd2,0xc7,0x28,0x5c,0x38,0xff,0xa5,0xed,0x97,0x9b,0x5a,0x4b,
+  0x36,0x8a,0xb3,0xe1,0xac,0xbc,0xab,0xdd,0xfb,0x33,0x66,0x7f,0x5e,0xd5,0xb2,0xc7,
+  0xbb,0xf3,0x5f,0x47,0x49,0x5c,0xf7,0x43,0xdf,0x30,0xa7,0x3d,0x6b,0xf0,0xed,0x35,
+  0xa4,0x1a,0xd6,0x2d,0x70,0xe2,0x3f,0xf3,0x98,0x50,0xe6,0xce,0x7f,0x3d,0x84,0xe8,
+  0x25,0xaa,0xdc,0x89,0xb4,0x67,0xaa,0x75,0x14,0x55,0x91,0x02,0x79,0x4b,0x4e,0xbc,
+  0x2b,0x3b,0xff,0xf5,0x6d,0xa3,0x46,0x57,0x8e,0xf0,0x78,0x9a,0xa6,0x17,0x25,0x3c,
+  0xb5,0xf0,0xb8,0xe6,0xc4,0x7f,0xea,0x72,0xfb,0x03,0xfc,0x96,0xc1,0xda,0x81,0x88,
+  0x6f,0x93,0xb2,0x1c,0x4e,0xd2,0x26,0xbd,0x38,0x51,0x5e,0x4b,0xde,0xfd,0x84,0xfe,
+  0x00,0x3f,0x80,0x0f,0x49,0xb8,0xc3,0xa7,0x32,0xfd,0x7c,0xc8,0xd0,0xef,0x86,0x32,
+  0x71,0x58,0xff,0xf9,0x27,0xf4,0x07,0xa0,0x3d,0x9c,0xff,0x6c,0x88,0x9a,0xce,0xd1,
+  0x4e,0x1c,0xf5,0x7f,0xe1,0xf8,0xcf,0x4d,0x01,0x8c,0xc6,0xd3,0x78,0x92,0x6d,0xc3,
+  0x9f,0x83,0x9a,0x84,0x27,0xbd,0x8e,0x5d,0x89,0x67,0xc5,0x7f,0xb2,0xf2,0x5f,0x9f,
+  0xc5,0x4d,0x68,0x5a,0x0e,0x90,0x42,0xd8,0xd5,0x9f,0x3c,0x12,0x9f,0x5b,0xe6,0x05,
+  0x11,0xb4,0xa1,0xec,0xf8,0x8f,0xe3,0xef,0xd4,0xc5,0x08,0x03,0x26,0xe4,0xe5,0xcc,
+  0xfb,0x63,0x22,0x7b,0x21,0xa6,0x2d,0xba,0xe8,0x96,0xac,0xf8,0xcf,0xb8,0x33,0x3e,
+  0x1e,0xff,0x3c,0x79,0x99,0xce,0x4f,0x06,0xe7,0x2a,0x66,0x20,0xc8,0xbb,0xaa,0x7c,
+  0x06,0xbb,0x32,0x2b,0x2b,0xfe,0xf3,0x9e,0x73,0x3e,0xac,0x3c,0x9d,0xe3,0x43,0xea,
+  0xee,0x2e,0x92,0x9f,0x4f,0x77,0xf5,0x87,0xac,0x78,0x06,0xce,0xc7,0x9a,0xa3,0xbc,
+  0x6c,0xe7,0x8f,0xf4,0xab,0x2e,0xd8,0xe3,0xf2,0x5f,0x86,0x66,0xeb,0xff,0x71,0xb5,
+  0x1f,0x9e,0x24,0xd5,0xfa,0x08,0x6f,0xcb,0xa6,0x6e,0x89,0x17,0x7f,0x8d,0x3d,0xff,
+  0x93,0x95,0xd9,0xf5,0xfe,0x6e,0xfc,0x93,0x80,0xa7,0x75,0x66,0x9f,0xab,0x62,0x55,
+  0xf0,0x3c,0x6c,0xa1,0xee,0x83,0x51,0x1c,0x7b,0xe5,0xee,0x0f,0x49,0x71,0x99,0xa9,
+  0x72,0x25,0x8f,0xff,0xf8,0x29,0xf3,0xfe,0x5e,0x4e,0xa3,0x72,0xc7,0x9f,0xdd,0xf9,
+  0xaf,0xbb,0xe1,0xb8,0xd6,0x94,0xf6,0x6e,0x57,0x82,0xbc,0xd1,0xae,0x8c,0xfe,0xe5,
+  0x64,0x8e,0x7f,0x79,0x4f,0x72,0xf2,0x8f,0xc2,0x8f,0xb5,0x49,0xb6,0xdf,0xdc,0x90,
+  0x6c,0xc3,0xc4,0x07,0x7b,0xbf,0xb6,0x61,0x5a,0xb0,0x38,0xa7,0x5e,0xde,0x59,0x3f,
+  0xd5,0xea,0x6e,0x66,0xc4,0x9a,0x63,0xde,0x4e,0x9e,0xff,0xda,0x85,0xf1,0xf9,0x3b,
+  0xb1,0x91,0x54,0x96,0x3d,0x37,0x5c,0xfc,0x9f,0xe5,0xea,0x20,0x3e,0x36,0x73,0x5b,
+  0xfa,0x5e,0x66,0x76,0xe2,0xdb,0x3d,0x68,0x61,0xb2,0xfc,0x6f,0xf6,0xf9,0xb0,0xea,
+  0x33,0xec,0xa5,0x88,0x53,0xac,0xf7,0x89,0xfb,0x87,0xe5,0xfe,0xb2,0x20,0xf4,0x09,
+  0xd9,0xf1,0x9f,0xa8,0xab,0x3f,0x80,0xcc,0xd0,0x42,0x40,0x97,0xc1,0xe3,0x95,0x66,
+  0x99,0xe5,0x7c,0x5e,0xbd,0x0b,0xb2,0xed,0xb3,0x3b,0xff,0x85,0xf9,0x77,0xb6,0xdb,
+  0xc2,0xf3,0xa7,0xbe,0x0e,0x21,0xea,0xa5,0xe5,0x41,0xbb,0xed,0x61,0xa6,0xbe,0x29,
+  0x83,0x7f,0xbe,0x83,0xfc,0xa6,0xa7,0x61,0xc3,0xa8,0x99,0xed,0x02,0xdf,0xa8,0x90,
+  0xdf,0xdf,0x26,0xf7,0x7c,0x58,0x0e,0xcb,0xbf,0x60,0x37,0xda,0x32,0xaf,0x5c,0x79,
+  0x81,0xfa,0x2f,0x27,0xc9,0xf5,0x9e,0xab,0x51,0x36,0x13,0x8a,0x5c,0xf9,0xaf,0xe8,
+  0x14,0xfd,0xb1,0x49,0x07,0x6f,0x0b,0x89,0x6d,0x37,0x2a,0x76,0xb1,0xf7,0x39,0x7b,
+  0xbe,0x99,0xf8,0x8f,0xc3,0x7f,0x1e,0x37,0x89,0xc4,0xa8,0xc6,0xdc,0xfa,0xaf,0xce,
+  0xfc,0xf3,0x61,0x53,0xe2,0x0a,0xde,0x16,0xd2,0xe9,0xa7,0xa1,0xb8,0xf4,0x33,0x3a,
+  0x55,0x7f,0xec,0xc9,0x6c,0xb5,0x14,0xbb,0xf3,0x5f,0x53,0xc4,0x7f,0x98,0x37,0xcc,
+  0x69,0xcb,0xd0,0x76,0x81,0xfc,0x97,0xfd,0xfc,0x24,0xb7,0xad,0xc4,0x14,0xf8,0xc7,
+  0x39,0x1f,0x96,0x19,0x19,0x3d,0x9f,0xaf,0xf2,0x20,0x03,0x42,0x8b,0x42,0x30,0x65,
+  0xfc,0xe7,0x94,0xee,0xb4,0xc5,0xbe,0xae,0x27,0x0b,0xff,0xf8,0x73,0xfa,0x63,0x9b,
+  0xf1,0x9f,0x11,0x78,0x81,0x0b,0x6d,0x0c,0xf6,0xd0,0x2a,0x2e,0xe8,0xff,0x9a,0x5f,
+  0xff,0x95,0xa5,0x1f,0xe4,0x3f,0x0b,0x67,0x32,0xfc,0xe7,0x6f,0x4d,0x9d,0xff,0xb2,
+  0x40,0x4e,0x6e,0xdb,0x0a,0x4b,0x98,0xab,0xd4,0x55,0xe4,0xc6,0x7f,0xf8,0x69,0x44,
+  0xff,0x96,0xcb,0xff,0x51,0xf1,0xe8,0x46,0x26,0xe4,0x9f,0x8f,0xc6,0x66,0xf7,0x06,
+  0xac,0x5d,0x8d,0xc4,0xef,0xc2,0x7c,0xfe,0xcf,0x14,0xe7,0xa3,0xe1,0xe9,0x72,0x0f,
+  0xba,0xd3,0xac,0x6d,0x2e,0xc5,0xe6,0x9f,0x8f,0xe6,0xc3,0x43,0xf1,0x0e,0xb8,0xf9,
+  0x3f,0xa2,0x0b,0xff,0xcc,0x73,0xd6,0x43,0x5e,0xfc,0xc7,0x47,0xa7,0xb9,0x4e,0x4c,
+  0x9b,0x32,0xff,0x65,0x3b,0x7d,0x6a,0x6f,0xfc,0x39,0x31,0xb8,0xc4,0x8d,0x7f,0x9c,
+  0xf1,0x39,0xfd,0xb1,0x6d,0x41,0xb8,0x50,0x7f,0xa4,0xac,0xfe,0xd8,0x39,0xff,0xb0,
+  0x15,0x85,0xbb,0x73,0xfa,0x43,0xba,0xfa,0x63,0x0b,0x39,0x6d,0x91,0x5c,0xf9,0x2f,
+  0xc7,0xfe,0xe4,0xf4,0xc7,0x76,0x4d,0xfc,0x4a,0xd7,0x95,0x29,0xce,0x87,0x4d,0x70,
+  0xda,0x73,0xb6,0x5b,0x9f,0x0a,0xff,0x14,0x5f,0x60,0xfc,0x82,0x0d,0x89,0x69,0xe6,
+  0x57,0xff,0x34,0xea,0xc6,0x3f,0xe0,0xea,0x8f,0x9d,0x25,0x5c,0x4e,0x2f,0x49,0x43,
+  0x3f,0x13,0xfe,0x22,0x37,0xff,0x75,0xc1,0x69,0xba,0xe6,0x9b,0x1b,0xff,0xb1,0x4f,
+  0x03,0x59,0xe0,0xd2,0x67,0xd9,0x18,0x3c,0xcc,0x7e,0x88,0x45,0xf9,0xfc,0x1f,0x7c,
+  0xec,0xdb,0xc7,0xf8,0x31,0x70,0x26,0xff,0xa7,0xd0,0xe2,0xab,0x5b,0x57,0x2e,0x14,
+  0xff,0xc9,0x17,0xa4,0x29,0xf3,0x5f,0x61,0xbb,0x1b,0x67,0x0e,0xff,0x47,0x35,0x19,
+  0xf8,0x6d,0x53,0xf7,0xc7,0xce,0x15,0xc4,0xed,0xa6,0x90,0xce,0xed,0x8f,0x6d,0xbe,
+  0x14,0xc3,0xba,0xab,0x2c,0xa5,0xd6,0xd5,0x1f,0x49,0x9b,0xba,0x3f,0xf6,0x61,0xe7,
+  0xb5,0x15,0xb2,0xf1,0x40,0x34,0xef,0x7c,0x58,0x04,0x39,0xb7,0xbf,0xa5,0xfe,0xd6,
+  0xa6,0x3d,0xff,0x11,0xcb,0xbe,0x1c,0xfc,0xb3,0x42,0xcc,0x3b,0x1f,0xd6,0x4c,0xe2,
+  0xe4,0xc2,0x1e,0xeb,0xab,0x64,0xfe,0xf9,0x20,0xe9,0x2b,0x4f,0x8a,0x3f,0x6b,0x7d,
+  0x8d,0x9f,0x86,0x96,0x87,0x7f,0xc6,0x15,0xc8,0x8a,0xff,0x5c,0x67,0x82,0x9c,0xc3,
+  0xfa,0x5a,0xb5,0x31,0xed,0x99,0x20,0x55,0xfa,0x2e,0xab,0xfe,0x0b,0x9f,0x7f,0x98,
+  0x3d,0x7f,0x5d,0x1e,0xff,0xd9,0xd3,0x59,0x76,0x02,0x8f,0x85,0x1d,0x91,0x27,0xf2,
+  0xf0,0x4f,0x94,0x40,0x6e,0xfc,0x07,0x8d,0xf6,0x30,0xe7,0x1f,0x7a,0x42,0x56,0xbd,
+  0xb3,0xe8,0xd2,0xa7,0x9c,0x77,0x3e,0xec,0xb4,0x54,0xcd,0x18,0xb7,0x9f,0x1c,0xff,
+  0x64,0xfb,0xaf,0xa4,0x58,0x97,0x1b,0xff,0x71,0xeb,0x47,0x39,0x66,0x31,0xc6,0x33,
+  0xe3,0x2f,0xd8,0x1f,0x7b,0x4a,0x21,0x3d,0xc5,0xf9,0xb0,0xcc,0x49,0x8d,0x39,0x6e,
+  0x4b,0xda,0x2b,0xb8,0xfd,0x57,0x32,0xef,0x7c,0x58,0x67,0x7c,0x5d,0x56,0x1b,0xc3,
+  0xcc,0xf8,0xdc,0xf8,0x0f,0xa2,0xeb,0x61,0x17,0x3f,0x4a,0x77,0x3b,0x3e,0x2d,0x87,
+  0xff,0xe3,0x9a,0xaf,0x19,0xf6,0x91,0xb1,0x1f,0xd4,0x95,0xae,0xf9,0xe6,0x9d,0x0f,
+  0x8b,0xb3,0x3b,0x01,0xfc,0x7c,0x4f,0x3e,0x4d,0xcd,0x3d,0xdf,0xa8,0x3b,0xff,0x25,
+  0x58,0x6c,0xe7,0x49,0xf1,0x38,0x9c,0x31,0x9a,0xd3,0xf5,0xb8,0x6c,0x0e,0xd2,0x66,
+  0x1d,0x23,0x66,0x88,0xa0,0xf2,0xf1,0xcf,0xef,0x18,0xc8,0x11,0x07,0x5b,0x19,0xda,
+  0x11,0xfc,0x26,0xff,0xf9,0x09,0xe2,0xa7,0x81,0x41,0xac,0x77,0xcb,0xe3,0xff,0x64,
+  0xf0,0xcf,0xad,0xbc,0xfe,0x4b,0x0e,0x91,0x63,0x6a,0x0c,0xb4,0x65,0xbc,0x71,0x5f,
+  0x6a,0x2a,0xfc,0xf3,0x43,0x47,0x9f,0x3d,0x0c,0x4f,0xa2,0x3e,0x7f,0xe8,0xf1,0x27,
+  0xb9,0xc0,0xee,0x9f,0xcd,0xff,0x31,0xf1,0x0f,0xef,0x86,0x7d,0x37,0x9c,0xd6,0x06,
+  0xd2,0xbc,0x7f,0xe3,0x7e,0xd5,0x12,0x26,0x39,0x90,0x26,0x53,0xe2,0x9f,0xf3,0xd2,
+  0x19,0xc1,0xe2,0x83,0x9d,0xa5,0x37,0x9a,0x44,0xe8,0x93,0x9f,0x80,0x7f,0x02,0xba,
+  0x73,0xec,0xd7,0xa4,0x19,0xe8,0x30,0x85,0x0b,0xe0,0x1f,0x4f,0x03,0xec,0x1d,0x9d,
+  0x6d,0xf6,0x4b,0xdf,0x43,0xac,0xe7,0xdf,0xa3,0xfa,0x2f,0x88,0x7f,0x6e,0x65,0xe8,
+  0x91,0xc3,0x60,0x36,0xcd,0x68,0x52,0x63,0xfa,0x39,0xa4,0xa7,0x46,0xb5,0x3c,0xfe,
+  0x0f,0x77,0xfa,0x97,0xaf,0x2a,0xfb,0x0b,0xe9,0xf9,0xae,0xab,0xd2,0x45,0xab,0xe0,
+  0x2d,0x78,0x2a,0x5e,0x9d,0xc2,0x0e,0x8a,0xea,0x6e,0x33,0x30,0x32,0x05,0xfe,0x99,
+  0x25,0x2e,0x86,0xc9,0x00,0x76,0xc3,0x9e,0x76,0x10,0x4e,0xab,0x4d,0x1e,0x2f,0x02,
+  0xa1,0x09,0x8c,0x08,0x4d,0x89,0x7f,0x3a,0xc5,0x67,0xe1,0xb4,0xc0,0xf3,0x5f,0xc7,
+  0xac,0xb6,0xea,0x99,0x7a,0x81,0x29,0xf1,0x0f,0xbe,0xbf,0x4d,0xa6,0xda,0x4f,0x9a,
+  0x19,0xc9,0x63,0x70,0x2a,0x97,0xff,0xec,0xc2,0x3f,0x98,0xed,0xda,0xc9,0x1b,0xcd,
+  0x59,0x19,0xb1,0x0b,0xf1,0x7f,0x2c,0x90,0xf3,0x01,0xac,0xa5,0x57,0xa7,0x65,0x13,
+  0xf6,0x04,0x35,0x2e,0x3c,0x35,0x25,0xff,0xc7,0xac,0xa6,0x34,0x6e,0xa3,0x51,0x4d,
+  0x8f,0xe3,0x32,0xe3,0xc7,0xd6,0xf0,0xf7,0x2b,0x31,0x05,0xff,0xc7,0x02,0x39,0x07,
+  0xf0,0x58,0x90,0xf8,0x4a,0x84,0x3d,0xe7,0x3a,0x5a,0x92,0x9c,0x11,0x7d,0x2e,0x2f,
+  0xfe,0x93,0xc1,0x3f,0x6f,0xf3,0x6a,0x77,0x93,0x08,0x2d,0x87,0x35,0x7e,0x5e,0xe7,
+  0xa4,0x71,0x61,0xfc,0x33,0xa6,0xef,0x17,0x9c,0xb0,0x4f,0xd3,0x72,0xef,0xd4,0xf1,
+  0x9f,0x0c,0xfe,0x79,0x07,0x7a,0xe9,0x56,0x0b,0xcf,0x50,0x0c,0xec,0x90,0xdf,0x6a,
+  0x17,0xc0,0x3f,0x0d,0xd8,0x1f,0xf2,0x04,0x59,0xad,0xd9,0x61,0x1f,0xf6,0x0f,0x65,
+  0xde,0x58,0x52,0x6d,0xb8,0x20,0xfe,0xf9,0x19,0xac,0x36,0x8f,0x45,0xe3,0x85,0x60,
+  0x9d,0x01,0x57,0xa3,0xc8,0x5c,0xfc,0x63,0x75,0x23,0x7c,0x29,0x13,0xf6,0x69,0x32,
+  0x3b,0x16,0x9e,0xfa,0x04,0xfc,0x83,0xf6,0xea,0x46,0xab,0x8c,0xab,0xb0,0x25,0x62,
+  0x0a,0xb9,0xfd,0xb1,0x2b,0x33,0xf5,0x5f,0x27,0xe0,0x57,0x6a,0xb3,0x5d,0xf6,0xd5,
+  0xbc,0x00,0x0f,0x0a,0x81,0xb3,0x01,0x1c,0x3f,0x6d,0x4d,0xfe,0xf9,0xb0,0x1c,0xf6,
+  0x68,0x7e,0xc1,0x14,0xe4,0xad,0x04,0x3b,0x46,0x26,0xcd,0xaf,0xa6,0xdd,0x3f,0x35,
+  0xfe,0x61,0xf6,0x07,0xcf,0x87,0x1d,0x86,0x3d,0x9a,0xd6,0x8e,0x0c,0x70,0x6a,0x7d,
+  0x15,0x9b,0x02,0xff,0x94,0x8d,0xb5,0xef,0x94,0xfc,0xe6,0x79,0xbb,0x7b,0x79,0x60,
+  0x8d,0x2b,0x16,0xf1,0x4f,0xd9,0x9a,0xa9,0xce,0x07,0xf9,0x2d,0xfd,0x39,0xc5,0x6a,
+  0x3e,0x6c,0x6b,0x20,0x37,0x7d,0xd3,0xec,0x18,0x49,0xf9,0x57,0xdb,0xa7,0xc4,0x3f,
+  0xda,0x49,0x7f,0xb8,0xc3,0x5c,0x0f,0xfb,0xe6,0xdf,0x65,0x5e,0x91,0x3f,0x01,0xff,
+  0x48,0x93,0xb1,0x39,0xd9,0xfa,0xd7,0x27,0x55,0xfc,0xaa,0x7c,0x0a,0xfc,0x93,0xbe,
+  0x64,0x92,0x1f,0x8b,0x56,0xc2,0x69,0xcf,0x91,0xbf,0xdf,0x2a,0x27,0xc9,0x29,0x78,
+  0xce,0x04,0x42,0xeb,0xf2,0xf1,0x8f,0xe6,0x3f,0xc0,0x61,0x8f,0xb9,0x5f,0x68,0xd5,
+  0x54,0xd9,0x55,0xff,0x35,0x05,0xfe,0x89,0xe2,0x69,0xce,0x42,0xb5,0xb1,0xd0,0xc4,
+  0x3f,0x5b,0x00,0xdf,0xdf,0xd2,0xa7,0x73,0xf9,0xcf,0x98,0xff,0x7a,0x9a,0x83,0x1c,
+  0xf2,0x96,0x74,0xce,0x86,0x3d,0x67,0x69,0x4d,0x32,0xb8,0x4a,0x7c,0x03,0x3e,0xe6,
+  0xd0,0x68,0x9a,0x0b,0xff,0x14,0x3b,0x20,0xc7,0xa9,0xee,0x61,0x16,0x46,0xe2,0x11,
+  0xa1,0x71,0x8b,0xff,0x5c,0x93,0x77,0x3e,0x2c,0x82,0x9c,0x30,0xbb,0x2d,0x96,0xed,
+  0x98,0xf5,0x3b,0xcb,0x98,0xff,0x3a,0x85,0xd4,0x68,0xe4,0xaf,0x1a,0xd9,0xf9,0x2f,
+  0x2c,0xb2,0x88,0x92,0x0a,0xd8,0x2d,0xf0,0xb0,0xf3,0x5b,0xf0,0x3c,0xcc,0xc2,0xe7,
+  0x1f,0xd5,0x9f,0xaa,0xc4,0x42,0xb6,0xfc,0xf3,0x61,0x71,0xbe,0x55,0xda,0x93,0x3c,
+  0x4c,0xad,0xbe,0x09,0x4f,0x56,0x56,0xef,0xc3,0xf1,0xf0,0xb4,0x7e,0x55,0x6e,0xfc,
+  0xc7,0x76,0xe2,0x97,0x94,0x48,0x29,0x24,0x02,0x99,0x6e,0xdd,0x8f,0xfa,0x4c,0x73,
+  0x3e,0xf9,0xa2,0x50,0xfe,0xf9,0xb0,0x38,0xdf,0x46,0xfd,0x74,0xb2,0xe9,0x6d,0x9c,
+  0xaf,0x70,0x92,0x36,0x51,0xee,0x5f,0x4e,0x1a,0x73,0xcc,0xf8,0x8f,0xfd,0x3c,0x0e,
+  0xfe,0x49,0xb2,0x65,0x33,0x09,0xcf,0x58,0xfe,0xe8,0xae,0x70,0xc2,0x62,0x04,0xcd,
+  0xcb,0xe6,0x3f,0xdb,0xf8,0xa7,0x24,0xcd,0xcf,0x83,0xb0,0x60,0xc0,0x59,0x08,0xef,
+  0xe3,0x15,0xf1,0x23,0x34,0x87,0xff,0xec,0xe0,0x9f,0x64,0xd9,0xef,0x03,0xcf,0x24,
+  0xec,0x32,0xf6,0x7d,0x0d,0x13,0xcc,0x7f,0xbd,0x07,0x47,0x78,0x21,0x73,0xeb,0x14,
+  0xf8,0x27,0xc9,0xec,0xd5,0x1e,0x7b,0x9b,0xcf,0x5e,0x93,0xb7,0x8b,0x52,0xe4,0x6d,
+  0xe8,0xd5,0xee,0x9e,0xaa,0x3f,0x36,0x07,0x39,0xc3,0x90,0xa2,0x99,0xb6,0x00,0x10,
+  0x08,0x11,0x43,0xdd,0x38,0x15,0xff,0x99,0x17,0xb5,0xe1,0x7c,0x3f,0xb4,0x60,0x21,
+  0x6e,0x24,0xd1,0xff,0xe2,0xf9,0xb0,0xb9,0xf1,0x9f,0x2b,0x1c,0x90,0x73,0x42,0x32,
+  0x69,0x3f,0x6d,0xef,0x23,0x7f,0x55,0xe7,0xe7,0xc3,0x9e,0xbb,0x00,0xff,0xc7,0xf0,
+  0x8e,0x8a,0xdf,0xe4,0x0b,0x29,0xc8,0x8f,0x85,0x95,0xd9,0xb2,0x39,0x2e,0xce,0xa7,
+  0xe7,0xa1,0x79,0x9f,0xef,0x88,0xeb,0x7c,0x58,0x03,0xcc,0x20,0x8f,0xdc,0xef,0xae,
+  0xff,0x8a,0x1b,0x98,0xff,0xf2,0xd7,0xc1,0x33,0x66,0x22,0x2c,0x95,0xa9,0xff,0x9a,
+  0xce,0xd7,0x83,0x2e,0x87,0xca,0xcc,0x17,0x8d,0x87,0x01,0x1f,0xc5,0x78,0x97,0x44,
+  0xbc,0x0c,0x78,0x73,0xff,0xde,0x94,0x17,0xff,0x09,0x3c,0x6b,0xf1,0xc9,0x8b,0xcc,
+  0x46,0xd3,0xfe,0x61,0x25,0x09,0xd7,0x98,0x07,0x85,0x0c,0xb0,0xfb,0x47,0x9d,0xf1,
+  0x66,0xbf,0x74,0xb9,0x5f,0xfc,0x8a,0x86,0x8a,0x2a,0xc6,0x7c,0xcd,0xaf,0x11,0x96,
+  0x0c,0x28,0x57,0x61,0x45,0x2a,0x32,0xe8,0x32,0xe7,0xa3,0x25,0x4d,0xfc,0x43,0x7d,
+  0xaa,0xf8,0xa3,0x0c,0x1f,0x7e,0x12,0xf3,0x5f,0xa9,0xb6,0xe3,0xfa,0x1f,0xd0,0xdf,
+  0x4d,0xb2,0x85,0xe4,0xdc,0x5f,0xb5,0xf3,0xb3,0x98,0xff,0xca,0xec,0x47,0xd8,0xfd,
+  0x41,0xbc,0xca,0xec,0x88,0xbb,0xd3,0x95,0xff,0x32,0xf1,0xcf,0x3c,0x83,0x59,0xe3,
+  0xbb,0x39,0x5b,0x09,0xd7,0x83,0x8a,0xf6,0x93,0xad,0x10,0x8d,0x97,0x0a,0xca,0xd7,
+  0x8b,0x03,0x19,0xfc,0x23,0x98,0x6a,0x61,0xd6,0xf8,0x16,0x77,0xfc,0x87,0xab,0xc5,
+  0xcc,0x0f,0xca,0xb3,0x5d,0xf8,0x27,0xdd,0x85,0xf6,0xe4,0x9a,0xb4,0x1c,0xe1,0x69,
+  0x20,0x2b,0x0c,0x62,0xc1,0x9e,0xef,0x0b,0x88,0x07,0x02,0xab,0xc8,0xb3,0x19,0xfc,
+  0x03,0x1c,0xff,0xe8,0xde,0x59,0xa2,0x97,0xbc,0x90,0x29,0x7b,0xd7,0x0c,0x9f,0xaa,
+  0x98,0x8d,0x80,0xbc,0x59,0xf8,0x67,0xfa,0xb3,0xbc,0xed,0x4f,0xe3,0xf1,0x0c,0x3b,
+  0x0e,0x57,0x14,0xcf,0x0f,0x7e,0x93,0xc7,0x7f,0x36,0x4c,0x88,0x09,0xc7,0xfe,0x3c,
+  0x61,0xe2,0x1f,0xca,0xbc,0x55,0xd4,0xd4,0xcf,0xa0,0xd9,0x28,0x29,0xed,0x1d,0x14,
+  0x4b,0x60,0x3f,0x6d,0xd2,0xbc,0x59,0xf8,0xe7,0x01,0x6e,0x4f,0x28,0x7b,0x7e,0xd5,
+  0xa4,0x3d,0x4f,0xf0,0x32,0x0a,0x5e,0x11,0x56,0x05,0x6b,0x30,0x35,0xe6,0xc6,0x3f,
+  0x94,0xe3,0x9f,0x20,0xe6,0xbf,0x6e,0x36,0xeb,0xbf,0x26,0x09,0x67,0x44,0xa7,0xe5,
+  0x4a,0x9e,0x11,0xd3,0x3a,0xe5,0xec,0xfe,0x3f,0x7c,0xbd,0x1d,0x09,0xcc,0x27,0x85,
+  0xad,0x56,0x1b,0x76,0xde,0x58,0x29,0x1d,0x08,0x79,0x4a,0x48,0x37,0x4d,0x4e,0x04,
+  0xf2,0xf1,0x4f,0x4b,0xc2,0x3b,0x5e,0xbe,0xca,0xaa,0xff,0x22,0xdb,0xd9,0x6b,0xd2,
+  0x94,0xf4,0xa6,0xc5,0x79,0xf4,0x50,0xb2,0x99,0x7a,0xb7,0xe6,0xe1,0x9f,0xf9,0xe0,
+  0xeb,0x72,0xef,0xc7,0x27,0x20,0x2c,0xd9,0x1b,0x73,0xd9,0x47,0xdb,0xf2,0xf1,0x8f,
+  0x57,0xed,0xce,0x3a,0x16,0x2d,0x3b,0xff,0x15,0xcb,0xc5,0x3f,0x11,0x99,0x9f,0xf7,
+  0x61,0xb2,0x9d,0xb7,0x99,0x65,0xec,0x9b,0xfc,0x58,0xcf,0xde,0x10,0x99,0x0a,0xff,
+  0xb4,0x06,0x12,0x64,0x5b,0x75,0xe6,0x18,0x35,0xac,0xc8,0x48,0xc4,0x50,0xc0,0xd4,
+  0x18,0x59,0xe3,0xea,0xff,0x63,0xe2,0x9f,0xdc,0x7a,0x28,0x1b,0x08,0x81,0x77,0x2a,
+  0xfc,0x83,0xe7,0xc3,0xd6,0x24,0x79,0x22,0xcc,0x5d,0xf6,0x6e,0x76,0x00,0x60,0xc2,
+  0xfd,0x8e,0xfd,0x39,0x62,0x9e,0x0f,0x1b,0x69,0x3c,0x2c,0x3e,0xe9,0x2a,0xe3,0xd2,
+  0xff,0x45,0xb7,0x12,0x61,0x0c,0x08,0x8d,0xe6,0xe3,0x9f,0x56,0x2f,0xf7,0xfe,0xee,
+  0xfa,0xaf,0x25,0x89,0x9a,0x5a,0xba,0x3f,0x10,0xee,0x60,0x5f,0x65,0xf0,0xcf,0x2a,
+  0x0b,0xff,0xb0,0xf7,0x6b,0x96,0x0b,0x08,0xe9,0x4c,0xe8,0x22,0x1a,0x6c,0x07,0x06,
+  0x74,0x8d,0xbc,0xf8,0x4f,0x7d,0x54,0xfe,0x26,0xf9,0x99,0xea,0x00,0xa1,0x27,0x0d,
+  0xb6,0xf0,0x96,0x92,0x0a,0xfd,0x3b,0x94,0x7d,0x15,0x71,0x9f,0x0f,0x62,0xe2,0x9f,
+  0x8e,0xc0,0xeb,0xfe,0xdd,0x99,0xf8,0xcf,0xbf,0x40,0x63,0x87,0x72,0x84,0xcc,0x46,
+  0x41,0x0f,0xbc,0x9e,0x17,0xff,0x99,0x8f,0x24,0xa5,0xdf,0x40,0x26,0xfe,0xc3,0xfb,
+  0x1b,0x28,0xb5,0xf0,0x73,0x3d,0x1c,0xf1,0xf6,0xbb,0xe2,0x3f,0xe3,0x36,0xfe,0x51,
+  0xdd,0x6d,0x8e,0x4e,0x9a,0xf9,0xbe,0x61,0xb3,0x34,0xbe,0xbf,0xfb,0x54,0x1e,0xfe,
+  0x61,0x68,0x67,0x02,0x4c,0xfd,0x63,0x7f,0x72,0x72,0x2f,0xaa,0xdd,0x0f,0x47,0x30,
+  0x23,0x39,0x34,0xc5,0xf9,0x68,0xbc,0x3f,0xb6,0xab,0x2d,0xb6,0x1f,0x69,0xeb,0x98,
+  0x1a,0xf3,0x53,0x79,0x5b,0x3e,0xfe,0x49,0xcb,0x21,0x86,0xfe,0x33,0xf6,0x07,0x37,
+  0x62,0x73,0xfd,0x5e,0x78,0x90,0x6a,0x69,0x39,0x58,0x98,0x87,0x7f,0x46,0xd9,0x4b,
+  0xfa,0x0b,0x57,0xd9,0x82,0x51,0x6d,0xf4,0x21,0x43,0x78,0xad,0x51,0x3d,0x2a,0x47,
+  0x0b,0xb7,0xe7,0xf0,0x7f,0xe6,0x23,0xda,0x39,0x44,0x5e,0xb6,0xeb,0xbf,0x8e,0xd3,
+  0xae,0xb4,0x2f,0xa0,0x94,0xc0,0xeb,0x34,0x95,0x0c,0x66,0xf5,0xff,0xb1,0xf8,0x3f,
+  0xd9,0x61,0xe4,0x53,0xcc,0x6c,0x72,0x44,0x64,0x6d,0x55,0x5c,0xf5,0x5f,0xab,0xad,
+  0xf3,0x61,0x8f,0x88,0x7e,0xdd,0x09,0xfb,0xbc,0x4f,0x6f,0x88,0x1e,0x3c,0xc2,0xf0,
+  0xcf,0xab,0xec,0x2b,0xe6,0xbf,0xb2,0xf0,0x8f,0xc4,0xf9,0x3c,0x11,0x52,0x06,0xd6,
+  0xe9,0x66,0x67,0xe0,0xdb,0x50,0xdd,0x1e,0xff,0x9c,0xff,0x88,0xfc,0x1d,0x93,0xe1,
+  0x93,0x8b,0x7f,0x82,0x20,0xdf,0x11,0xbb,0x84,0x3e,0x6d,0x8f,0xdf,0x01,0xd7,0xb4,
+  0xca,0x3a,0xdb,0x66,0x6e,0x82,0x7a,0x49,0x59,0x1a,0xcb,0xc3,0x3f,0x10,0xa8,0x64,
+  0xef,0xd7,0x83,0x76,0xd8,0x87,0xca,0x9a,0x2e,0x03,0xd9,0x0f,0x09,0x3d,0x08,0x4a,
+  0x65,0x3e,0xfe,0x49,0x7b,0x83,0xa2,0x9c,0x49,0x34,0xfc,0x2e,0x3a,0x97,0x32,0xfb,
+  0xc9,0x76,0x94,0x34,0x9c,0xf6,0x6d,0xcf,0xc3,0x3f,0xf3,0xd3,0x3c,0x4c,0x6d,0xd5,
+  0xdb,0xbe,0x6b,0x6a,0x0c,0xc7,0xff,0x1a,0xc7,0x4f,0x11,0xff,0xa1,0xbc,0xed,0xcf,
+  0x6b,0xf6,0xee,0xfe,0x9c,0x79,0x65,0x4c,0x3b,0x24,0x37,0x53,0x9f,0xfb,0x7c,0x58,
+  0x6a,0xe2,0x1f,0x1a,0x48,0x72,0x7e,0x2f,0xc7,0x33,0xef,0x52,0x73,0x45,0xf9,0x87,
+  0xf9,0xfa,0x51,0x34,0x31,0x0a,0x39,0xf8,0x47,0x97,0xb1,0x1f,0x45,0x9f,0x9d,0xb8,
+  0xd9,0x83,0x6f,0x68,0x82,0xe1,0x9f,0xc7,0xcd,0x0e,0x12,0x53,0x9c,0x0f,0x2b,0x13,
+  0x88,0x75,0xdb,0x81,0x7a,0xf6,0x62,0x6a,0x32,0xa6,0xdd,0xb7,0x30,0x43,0x24,0x26,
+  0xa0,0x35,0x17,0xff,0xe0,0xfa,0xaf,0xb5,0xfd,0xef,0x38,0xb7,0x48,0x88,0xff,0xa5,
+  0x71,0xf4,0xef,0x09,0x11,0xb2,0xf1,0x8f,0xe4,0x03,0x9f,0xce,0xac,0x8d,0x93,0xc8,
+  0x38,0x83,0x27,0xc6,0x1a,0xec,0x0d,0x7a,0x93,0x6d,0xe4,0x37,0x8c,0xe6,0xe3,0x9f,
+  0xb4,0x6f,0xbf,0xd8,0x04,0x67,0x8c,0x59,0x51,0x2b,0x6c,0x78,0xa5,0xc1,0xf0,0x21,
+  0xd6,0x0f,0xd6,0x18,0xde,0x29,0xf3,0x5f,0x6c,0xbe,0x81,0x94,0x56,0x17,0xb5,0xf2,
+  0x5f,0x41,0xa3,0x38,0xe4,0x69,0xa8,0xd8,0xdb,0xa3,0x19,0xf2,0x94,0xf1,0x1f,0x52,
+  0x08,0x94,0x6d,0xbb,0x74,0x27,0xcc,0x85,0x15,0xca,0xd2,0x20,0xf0,0x88,0x50,0x5e,
+  0xfe,0x6b,0x48,0xa1,0x85,0x1a,0x06,0xf6,0x3b,0xac,0x78,0x1a,0x07,0x4e,0x2b,0xd5,
+  0x3d,0x18,0x41,0xca,0xaa,0xff,0xb2,0xf3,0x5f,0xfd,0xca,0xcc,0xca,0x49,0xda,0x04,
+  0xce,0x8b,0xe3,0xe5,0x27,0x86,0x2c,0xe3,0x81,0x9a,0xec,0xfa,0x2f,0xae,0x96,0x9f,
+  0x8b,0x7f,0xd0,0xcf,0x24,0x1a,0x35,0x77,0x3c,0xf0,0x59,0xe1,0x02,0xf5,0x5f,0x78,
+  0x7f,0xf1,0x31,0xf4,0xe6,0xe0,0x9c,0x0f,0xe2,0xe5,0x1d,0x81,0x8c,0xf0,0xbe,0x60,
+  0x2a,0xf7,0x7c,0x58,0x7c,0xfe,0x7f,0x24,0xbf,0xd5,0xd9,0xfe,0x1d,0xac,0xfa,0xc1,
+  0xc6,0x09,0x79,0xb2,0x0c,0x3b,0x1a,0x35,0xe2,0xf3,0x1f,0xa7,0xf6,0xcf,0x6b,0xd8,
+  0xfb,0xaf,0x24,0x89,0xcb,0xeb,0xcc,0xf8,0x18,0xd7,0xcf,0x3e,0xd9,0xae,0x07,0x64,
+  0x42,0xd6,0xf9,0xb0,0x70,0x1d,0xc2,0x80,0x15,0xe4,0x0d,0x58,0x93,0xa8,0x49,0x17,
+  0x59,0x69,0xa0,0xb7,0x65,0xec,0x08,0x84,0xf8,0x47,0xce,0xad,0xff,0xe2,0xf1,0x1f,
+  0x4d,0xdc,0x4e,0x5e,0x50,0x43,0x9c,0xf6,0xcc,0xaf,0x04,0x43,0x8a,0x97,0x39,0xee,
+  0xf9,0x43,0xde,0xd0,0xed,0x53,0x9c,0x0f,0x7b,0x94,0x29,0xe1,0xb4,0x1a,0x4e,0x23,
+  0x3e,0x94,0xf8,0x95,0x0f,0x71,0xe3,0x20,0xb4,0xbc,0xb4,0x24,0x2b,0xfe,0x93,0xc9,
+  0x3f,0x06,0xf1,0xb4,0x1a,0xcb,0x70,0x09,0x33,0x0c,0xaf,0x5d,0x9f,0xe8,0xbd,0x40,
+  0xfc,0x87,0xa1,0x1d,0x52,0x4d,0xed,0x30,0xf2,0x88,0xfc,0x77,0x9e,0x2a,0x78,0xca,
+  0x0c,0x04,0x4d,0x19,0xff,0x99,0xc1,0x0f,0x46,0xb1,0xd2,0x5e,0x2b,0xc7,0xe4,0x79,
+  0x64,0x46,0xe9,0x93,0x34,0x38,0x2e,0xaf,0x2a,0x74,0xc5,0x7f,0x24,0x27,0xde,0x58,
+  0x0c,0x7d,0x44,0xeb,0x37,0xd7,0x1b,0x09,0x1a,0xdb,0x99,0x3e,0xf9,0x89,0x8d,0x81,
+  0x50,0xa1,0x0b,0xff,0x14,0x58,0xf1,0x9f,0x6d,0x4a,0xc0,0x73,0x00,0x06,0x12,0x4e,
+  0xfe,0xcb,0x9b,0x54,0x02,0x3c,0xfe,0x13,0x9c,0x3a,0xfe,0xd3,0x8d,0x6d,0x7f,0x5a,
+  0x2c,0x3c,0x80,0xe7,0x75,0xf6,0x88,0xe9,0xca,0xc9,0x35,0xb9,0xe7,0xc3,0x82,0x05,
+  0x72,0x1e,0x16,0x99,0x37,0x4f,0xba,0x60,0x0f,0x73,0x8b,0xb5,0x18,0x1f,0xc0,0x13,
+  0x51,0xa7,0x88,0xff,0x6c,0xf6,0x5c,0x4d,0x7a,0xf7,0x65,0x68,0x3c,0x91,0x78,0xc2,
+  0x5f,0x2b,0xed,0x79,0xa0,0x21,0x2a,0x67,0xe1,0x9f,0xe9,0x16,0xff,0x59,0xf5,0x54,
+  0x30,0x33,0x5e,0x83,0xdd,0x0e,0x71,0x7c,0xb0,0x55,0xbe,0x04,0x2b,0x98,0x84,0x06,
+  0x0c,0x5c,0x64,0xfa,0xff,0x38,0xf1,0x9f,0x3b,0xc9,0xa7,0x60,0xb5,0x51,0xcd,0xfe,
+  0x61,0x19,0x8f,0x90,0x44,0x02,0x15,0xc4,0xa4,0x46,0x07,0xf2,0xeb,0xbf,0xd8,0xec,
+  0x40,0xc4,0x1f,0x63,0x57,0xd6,0xb1,0xb0,0x9a,0x3c,0x29,0x20,0x23,0x3a,0xbb,0xfe,
+  0xcb,0x9d,0xd6,0x79,0xce,0x99,0x6f,0x84,0x1f,0x04,0x76,0x56,0x0a,0x47,0x2e,0x14,
+  0xff,0x99,0xcd,0xab,0xdd,0x11,0x08,0xa9,0x0c,0x08,0x2d,0xf5,0x8e,0x76,0xd7,0xb2,
+  0xa5,0xd8,0x8c,0xd0,0xe8,0x1d,0x07,0x3f,0xb8,0xe2,0x3f,0x1a,0xba,0x75,0xf0,0x70,
+  0xfc,0x43,0x1a,0xe4,0xe2,0x18,0xd1,0x98,0x3d,0xd9,0x5a,0xc9,0x4c,0xf1,0xa1,0xc2,
+  0xbc,0xf8,0x4f,0xd9,0x3a,0x29,0xb9,0x13,0x1b,0x71,0x58,0x69,0xaf,0x88,0xac,0xc6,
+  0x24,0xe4,0x5b,0xb6,0xca,0xb9,0xf5,0x5f,0xa6,0x3e,0x99,0xf6,0xd8,0xb6,0x5d,0xf7,
+  0x60,0xda,0x6b,0x0f,0x69,0xd0,0x7b,0x55,0x5e,0x11,0x86,0xfc,0xcc,0xd6,0x97,0x1c,
+  0x7c,0x92,0xac,0x70,0xe2,0x39,0xec,0xd7,0xd4,0x5d,0x07,0xc1,0x2c,0x46,0xfc,0xf3,
+  0x61,0x7c,0x0e,0x1e,0x1d,0x32,0xee,0xf4,0x9f,0xd9,0x0e,0xdb,0xe0,0x93,0xf2,0x5f,
+  0x1a,0x6f,0x04,0x94,0x39,0x9f,0xc2,0xc4,0x3f,0x98,0x7f,0xac,0xd1,0xe4,0x11,0x7d,
+  0x80,0xeb,0x5f,0x46,0xfd,0x2f,0x66,0xfa,0xc7,0x1f,0x42,0xda,0x40,0xc5,0x4c,0x7f,
+  0x98,0x80,0xdd,0xff,0x67,0x8c,0x5c,0x0f,0xf7,0xeb,0x35,0xd8,0xad,0x69,0x5c,0x7d,
+  0x06,0x1a,0x29,0x36,0xf6,0x54,0x9f,0xf1,0x36,0x26,0x95,0xbc,0xf3,0x61,0xf1,0x7d,
+  0x99,0x47,0x4a,0xba,0xba,0xdf,0xf0,0xd3,0x3e,0xd3,0xfe,0xb0,0x8d,0xad,0xf9,0xbe,
+  0xe4,0xd7,0x7f,0x99,0xef,0xef,0x1d,0xe4,0x53,0x12,0xf6,0x3f,0xb4,0xde,0xdf,0x60,
+  0x82,0x21,0x0a,0xe7,0xd5,0xce,0xad,0xff,0xba,0x1e,0xe3,0x33,0xf3,0xc8,0x21,0x3a,
+  0x2b,0xe9,0xa4,0xbd,0x82,0xe3,0x9c,0x11,0x74,0xa3,0x96,0x5b,0xff,0x65,0xc5,0x37,
+  0x84,0x71,0x93,0x78,0x9f,0x9b,0x4f,0xd7,0xf3,0xea,0xbf,0x2c,0xd8,0x83,0x29,0xe8,
+  0xe6,0xe4,0x95,0x66,0xfc,0x87,0x21,0x22,0x17,0x11,0x7a,0x34,0x2f,0xfe,0xa3,0x18,
+  0x6c,0xc9,0xae,0xc9,0x3c,0x7f,0x23,0xee,0xc8,0xde,0x94,0x9e,0x14,0xd0,0xfe,0x4c,
+  0xd5,0xff,0x27,0x62,0xd2,0xe0,0x29,0x6f,0x7b,0xc8,0x11,0x54,0x14,0x0b,0xe1,0x71,
+  0x2b,0x97,0x57,0xff,0x85,0x4a,0xa3,0x0b,0xf1,0xfc,0x3e,0x2d,0xe5,0xf8,0x3b,0x66,
+  0x7f,0x0e,0x22,0x02,0x47,0x7b,0xee,0xee,0xff,0xb3,0x23,0x63,0x3f,0x5f,0x11,0x9a,
+  0x36,0xe3,0x34,0xd5,0xd3,0x66,0x7c,0xe3,0x98,0xf0,0x91,0xcc,0x85,0x43,0x53,0xc5,
+  0x7f,0xde,0x35,0x0d,0x17,0xaa,0xe5,0xbf,0x43,0xb8,0xcb,0x3c,0x48,0xce,0x9f,0x53,
+  0xff,0xee,0xca,0x7f,0xcd,0x87,0x57,0x55,0xb6,0x9b,0x73,0x0e,0xc6,0x42,0x44,0x74,
+  0x76,0xa8,0x19,0xbc,0xd8,0xff,0x27,0x2f,0xfe,0xb3,0xc3,0x53,0x07,0x71,0x43,0xb3,
+  0x0e,0xea,0xe2,0x07,0x85,0x90,0x1d,0x98,0xc8,0xd0,0xe5,0x54,0x6b,0x76,0xfd,0x17,
+  0x1f,0xff,0x40,0xac,0x36,0xda,0x07,0x84,0x16,0x59,0xfe,0x1a,0x3b,0xfa,0x06,0x79,
+  0x47,0xa9,0x8e,0x54,0x59,0x76,0xfd,0x17,0xd7,0x0f,0x10,0xc0,0x1e,0xa6,0xd4,0xf6,
+  0x77,0x94,0xbd,0x86,0xeb,0xf9,0xc6,0x5f,0xce,0xab,0xff,0xc2,0xf9,0x26,0x44,0x09,
+  0x69,0x93,0x66,0x58,0x0c,0x97,0x01,0x33,0xcb,0x41,0xf6,0xe2,0x84,0xf0,0x4a,0xde,
+  0xf9,0x68,0x06,0x47,0x3b,0x67,0x30,0xd0,0x31,0xe1,0x0a,0x7c,0x79,0xcf,0x5e,0x20,
+  0xfe,0x93,0x66,0x17,0xb3,0xfa,0xff,0xb4,0x8c,0xb0,0x65,0x73,0x9d,0xcd,0xa8,0x77,
+  0xf5,0xff,0xa1,0xbc,0xdb,0xf3,0x51,0x65,0xbb,0x19,0xff,0x39,0x6a,0xf3,0x7f,0x26,
+  0xe4,0x81,0x58,0x0f,0xf4,0xe5,0xf5,0xff,0xc9,0xf0,0x31,0xdc,0x6d,0x9f,0x49,0xb0,
+  0x9d,0x4d,0x5c,0xea,0xe9,0xb6,0xf9,0xcf,0x59,0xf8,0x47,0x62,0xfa,0xdc,0x9e,0xd5,
+  0x36,0x19,0xf8,0xb1,0xbc,0x8f,0x31,0x8f,0x96,0xdb,0xff,0x59,0xda,0x21,0x59,0xfa,
+  0x09,0x5e,0x6a,0x2e,0xa4,0x1a,0xb3,0x7f,0x82,0x37,0xa4,0x38,0x88,0x71,0xc8,0xb1,
+  0x9f,0x5d,0x80,0xfe,0xbd,0x11,0xc7,0x67,0xa5,0x41,0xc3,0xe8,0xdf,0x4f,0x58,0x57,
+  0xbe,0x94,0xe1,0x3f,0x8f,0x81,0xb5,0x3e,0x55,0xd7,0xb1,0xb3,0x76,0x44,0x68,0xa5,
+  0xfa,0x8a,0xd9,0x81,0x21,0x93,0xff,0x4a,0x4b,0xd6,0x63,0x27,0x5c,0xcf,0x2f,0x71,
+  0x84,0x9c,0x22,0x41,0xb9,0xcf,0x3e,0x1f,0xcd,0x5e,0x0f,0x86,0xe4,0x9d,0x4a,0x3f,
+  0xb8,0x1e,0xca,0xc8,0x72,0xb5,0x3b,0x97,0xff,0x3c,0x0a,0x16,0xff,0x27,0xbb,0xed,
+  0x73,0xa2,0x1e,0x4f,0x10,0xbb,0x84,0x47,0x84,0x2e,0xcf,0xea,0xff,0x0c,0x0e,0xff,
+  0xa7,0x84,0x0b,0x1b,0x2c,0xfc,0xf3,0x00,0x7b,0xfe,0x76,0x78,0x41,0xcd,0xeb,0x7f,
+  0xe8,0x8a,0x3f,0xbb,0xcd,0x0e,0x75,0x67,0xe4,0x73,0xfa,0xff,0xe4,0xd3,0x7e,0xe8,
+  0x3c,0x4c,0x84,0x6d,0x73,0xf8,0x7b,0x19,0xfc,0x03,0x9b,0x73,0xb2,0xe7,0x28,0x3c,
+  0x8f,0xcb,0x7e,0x82,0x59,0x98,0x29,0xfb,0x3f,0xe7,0xb2,0x7d,0xde,0x82,0xe7,0xd7,
+  0x5c,0x83,0x30,0xef,0xa1,0x29,0xfa,0xff,0xd8,0xfd,0xc7,0x66,0x59,0xb0,0xc7,0x5a,
+  0x6f,0xec,0xfe,0x73,0xc9,0xcc,0xfc,0xfa,0xf7,0x11,0xab,0xff,0xa1,0x6f,0x9c,0xc3,
+  0x9e,0x06,0x9b,0xff,0x73,0x03,0xf5,0x3e,0x21,0x3e,0x41,0xf3,0xf9,0xcf,0x60,0xe5,
+  0x23,0xe2,0x59,0x7c,0x18,0x29,0xac,0x35,0x4e,0xcd,0xff,0xf9,0x24,0x7f,0x87,0xe7,
+  0x8d,0x86,0xf5,0x69,0x53,0xf6,0x3f,0x44,0x18,0xf3,0x6e,0x16,0x9f,0xa7,0x82,0x9f,
+  0x4f,0x9a,0x9b,0xff,0x82,0xda,0x5c,0xda,0x8f,0x45,0xd3,0x5d,0x94,0x60,0xf3,0x35,
+  0x5b,0xf9,0x41,0x26,0xff,0x05,0x6a,0x86,0xff,0x03,0x5b,0xb2,0x68,0x30,0x55,0x97,
+  0x15,0x08,0x5b,0x72,0xf3,0x5f,0x4b,0x2b,0xed,0xb2,0xf7,0x9a,0x2c,0xfe,0x0f,0x67,
+  0x04,0x69,0xc4,0x8a,0x80,0x7d,0x90,0xd5,0xff,0x87,0xcf,0xee,0xf0,0xed,0xf8,0xfc,
+  0xf7,0xd9,0xf3,0xe5,0x61,0x9f,0x13,0xf0,0xf3,0xa9,0xfa,0xff,0xb8,0xea,0xa1,0xee,
+  0x73,0xe2,0x3f,0x1d,0xde,0x9f,0x28,0xbb,0xf5,0xde,0xdc,0xfa,0xf7,0xca,0xac,0xfc,
+  0x17,0xdc,0xed,0xf0,0x7f,0x4a,0xe5,0x18,0x01,0xfb,0xa0,0xb4,0x4c,0xfc,0x27,0x6a,
+  0xf7,0x3f,0xac,0xc8,0xa1,0xfd,0x60,0xfe,0x6b,0x9b,0x1d,0x01,0xcb,0xc4,0x7f,0x06,
+  0x2b,0xb6,0x65,0xe9,0x33,0xc3,0xff,0x09,0xf0,0xc6,0x02,0xb9,0xf5,0xef,0xd6,0xf9,
+  0xb0,0xf6,0x34,0x1b,0x32,0xb4,0x1f,0x6f,0xa5,0xd8,0xc3,0x0f,0x7a,0x9b,0xe6,0xe6,
+  0xff,0x1c,0xc8,0x59,0x0f,0x0b,0x2c,0x61,0xfe,0x72,0xdf,0xc6,0x45,0xef,0x24,0xf3,
+  0xf8,0xcf,0x1e,0x48,0xba,0xd5,0x8e,0xdd,0x7e,0xca,0x4d,0xfc,0xc3,0x1b,0x21,0x8e,
+  0x48,0x39,0xfc,0x67,0xa7,0xff,0x61,0xb2,0x35,0x97,0xff,0x73,0x94,0xcc,0xb5,0x23,
+  0x42,0x07,0xf2,0xf3,0x11,0xf9,0x6d,0xb2,0x90,0xc1,0xdb,0x9d,0x8b,0x7f,0x04,0xc8,
+  0x67,0xff,0xbe,0x69,0x23,0xa2,0x2a,0x3b,0x22,0x94,0xc9,0x7f,0xc9,0xf1,0x19,0xae,
+  0xb6,0x3f,0x5d,0x56,0xdb,0x1f,0x7e,0xe5,0x88,0x72,0x89,0x1d,0x11,0xca,0xc4,0x7f,
+  0xea,0xaa,0x76,0xc8,0x6e,0x76,0xe5,0x50,0xc6,0xb0,0x24,0x32,0xf6,0xc7,0xd5,0xff,
+  0x19,0xcf,0x87,0x4d,0x38,0x6c,0x1f,0xb3,0xff,0x8f,0x8d,0x88,0xe6,0x41,0x5e,0xfd,
+  0xfb,0x13,0x2a,0x8f,0xff,0x58,0x8f,0x2d,0xd4,0x8f,0xbb,0x68,0xcf,0x1e,0xa7,0x11,
+  0x6b,0x06,0xff,0x24,0x81,0x9f,0x27,0xeb,0x4c,0x73,0xc4,0x35,0xf1,0x58,0xc4,0x1e,
+  0x9f,0xe9,0x2f,0xe1,0xf4,0x3f,0xcc,0xf4,0x73,0x6b,0x3d,0x66,0x0a,0x01,0xa2,0xe7,
+  0xd7,0xbf,0x3b,0xf6,0xf3,0x49,0xd1,0xa4,0xb9,0x5a,0xf3,0x6d,0xc0,0x40,0xba,0x43,
+  0x7d,0x71,0xd7,0x7f,0x4d,0x69,0x6f,0x01,0xf9,0x30,0xca,0x0e,0x4b,0x70,0xd7,0xbf,
+  0xc3,0xb3,0x92,0x93,0xf6,0xfa,0xbd,0xed,0xef,0xcc,0x7e,0xbf,0x35,0xf3,0x6d,0x62,
+  0x67,0x26,0x5e,0x31,0x64,0xf9,0xaf,0x45,0x59,0xb4,0x55,0xee,0xb6,0xc2,0xa4,0xde,
+  0x3e,0xe8,0xd3,0xd5,0xff,0x47,0xca,0x76,0xd3,0xa6,0xc0,0xcf,0x47,0x1b,0x74,0x3c,
+  0x20,0xb8,0xf0,0x8f,0x9a,0xbd,0xde,0xf6,0x71,0xbe,0x47,0x77,0x8e,0x07,0x74,0xe1,
+  0x9f,0xf8,0x4a,0xd7,0x34,0xed,0x36,0x08,0x66,0xe0,0x4b,0x09,0xaa,0x79,0xf5,0xef,
+  0x14,0xcf,0x47,0xb3,0xaa,0x75,0xb4,0x6c,0x9a,0x53,0xa7,0x79,0x10,0x3c,0xe6,0x2f,
+  0x5c,0xf8,0x67,0xfa,0x39,0xf8,0x95,0xc9,0xff,0x39,0x27,0xff,0x9e,0xad,0x96,0xaa,
+  0x2c,0xda,0x33,0xb6,0xce,0x66,0x77,0x08,0xb9,0xce,0x87,0x75,0x48,0xce,0x1f,0x08,
+  0x28,0x78,0xdc,0x6d,0x7f,0x48,0x9c,0xf8,0xd3,0x7d,0xa9,0xb2,0x54,0xa6,0xdf,0x08,
+  0x8f,0xff,0xac,0xe4,0xd5,0x04,0x15,0xb8,0xfb,0x46,0xbc,0x57,0x69,0x4d,0x13,0x5b,
+  0x85,0x27,0x8d,0x3e,0x8d,0x34,0x09,0xf6,0x78,0x43,0xb0,0xf9,0xcf,0x65,0xc7,0xa4,
+  0x1b,0x78,0x3f,0x25,0x47,0xb1,0x85,0xbf,0x05,0x2c,0x84,0x7f,0x65,0x0b,0x49,0x39,
+  0xf6,0x04,0x2a,0x76,0x48,0xbf,0x90,0x10,0x96,0x08,0xc7,0xe0,0xff,0x07,0xd6,0xf9,
+  0x7a,0x96,0x5a,0x7e,0xad,0x1e,0x48,0x36,0x19,0x4b,0x9e,0x55,0x4a,0x1d,0x7e,0xfb,
+  0x51,0x86,0x7f,0x5a,0xb8,0x5a,0x6e,0x3f,0x53,0x90,0xcb,0x07,0x4b,0x4b,0x3c,0x3f,
+  0xd8,0xd9,0x3c,0x45,0xff,0xe7,0x94,0x75,0x0c,0xdf,0x12,0xfb,0xfe,0x25,0x58,0x66,
+  0xc8,0x89,0xe8,0x49,0x71,0xb6,0x63,0x7f,0x0e,0x48,0x41,0xe9,0x74,0x81,0xb5,0x0c,
+  0x70,0x19,0x97,0xb8,0xf8,0x60,0xbf,0x31,0xfa,0xee,0xd9,0x6a,0x30,0xd3,0xd4,0xe4,
+  0xfc,0xbc,0x2e,0xfe,0xcf,0x41,0xb3,0x3a,0xd2,0xb6,0x3f,0x9e,0x50,0xd9,0x7b,0x6a,
+  0x2f,0xe5,0xad,0x12,0xe6,0x3a,0xf6,0x67,0x99,0x30,0x43,0xfd,0x01,0xfd,0x0a,0x73,
+  0xfa,0x53,0xd0,0x80,0xdf,0x82,0x9e,0x44,0x75,0x9a,0x19,0xae,0xf9,0xd4,0x5e,0x6f,
+  0xc8,0xff,0xd9,0x95,0xd3,0xed,0xf9,0x20,0x6f,0x84,0x58,0x12,0x12,0x47,0xc8,0x2b,
+  0x6a,0x68,0x78,0x49,0x85,0x52,0xe6,0x3c,0x8f,0x7e,0xe9,0xb3,0x66,0x77,0xac,0x94,
+  0x80,0xef,0x0b,0x9f,0xa6,0xd3,0xf6,0xf9,0x04,0xcc,0x57,0x5b,0x86,0x7d,0x3f,0x11,
+  0x47,0x2f,0xb1,0xdf,0x47,0xce,0xff,0x91,0x78,0xda,0x2b,0x98,0xf7,0x62,0x9e,0x51,
+  0xad,0xf3,0x8b,0x3d,0x99,0xfa,0x2f,0x7b,0xff,0x35,0x21,0xe6,0x1c,0x7b,0xd1,0x87,
+  0x42,0x0f,0x66,0xd8,0x43,0xa4,0x29,0x53,0x4f,0x67,0xe2,0x9f,0xa3,0xca,0xe4,0x14,
+  0xc7,0x7c,0x1c,0x82,0x58,0x9c,0x27,0xfe,0xd4,0xa9,0xf8,0xcf,0x19,0xc5,0xca,0x96,
+  0x70,0xa8,0x35,0xfe,0xb6,0x86,0x2f,0x66,0x99,0xab,0xfe,0xcb,0xe1,0xff,0x04,0x9c,
+  0xb6,0xcf,0xaa,0x25,0x9c,0xd4,0x0f,0xe9,0x03,0xd4,0xf7,0x9e,0x72,0xc3,0x85,0xeb,
+  0xdf,0xff,0xdd,0xfe,0x87,0x9f,0x40,0x73,0x1d,0xe6,0xf5,0xd1,0x4b,0x12,0xa2,0x38,
+  0x15,0xff,0xc7,0xc6,0x33,0xcd,0x8e,0x47,0xfe,0x8d,0x75,0x3e,0xbb,0xbb,0xfe,0xdd,
+  0x85,0x97,0x84,0x3c,0x20,0x14,0xb5,0xc6,0xdf,0xec,0xfc,0xbe,0x6e,0xfe,0xb3,0x25,
+  0xf8,0x9d,0x0e,0xc9,0x2f,0xe2,0xd1,0xb1,0x0c,0x2a,0x78,0x74,0x67,0xfc,0xa0,0xac,
+  0xf1,0x68,0xf3,0x05,0xe6,0x3b,0x82,0xf1,0x67,0xaa,0xdc,0x77,0xa1,0xf8,0x8f,0x99,
+  0xff,0x92,0x2d,0xe1,0x2c,0x39,0xdf,0xca,0x2b,0xc2,0x32,0xfd,0x7f,0xfa,0xa7,0x4f,
+  0x05,0x0b,0x6d,0x46,0x74,0xf2,0x55,0x19,0x3b,0x42,0xaf,0x75,0xc5,0x7f,0x2a,0x6d,
+  0xfc,0xd3,0xea,0x00,0xa1,0xa4,0x2d,0x1c,0x8d,0x61,0x69,0x98,0xb2,0xc6,0x15,0xff,
+  0x01,0x87,0xff,0xe3,0xb7,0x84,0x04,0x86,0xb9,0x24,0x53,0x03,0x5a,0x77,0x00,0x13,
+  0x7f,0x31,0xd7,0xf9,0xb0,0x05,0xa6,0xb6,0x2f,0x77,0xa9,0x31,0x83,0x88,0x2a,0x7a,
+  0x91,0x61,0xb5,0x89,0xbc,0x93,0x89,0xff,0x48,0xf9,0x6d,0x2d,0x9d,0xe7,0xff,0x2d,
+  0xec,0xd7,0x91,0x11,0x44,0x32,0xf1,0x9f,0x27,0xd4,0x4f,0xc0,0xc3,0x2f,0x23,0xc3,
+  0x81,0xe3,0x1f,0x67,0xbd,0x65,0xf1,0x9f,0xf3,0x04,0x63,0xa4,0xa3,0x09,0x3b,0x72,
+  0xbb,0xea,0xdf,0x7b,0x4c,0xfc,0xb3,0xc8,0xcd,0x7f,0x96,0x2d,0x61,0x12,0xee,0xd7,
+  0xb7,0xa2,0xe0,0x99,0x8a,0xff,0x6c,0xbd,0x38,0x29,0x14,0xa4,0xa0,0xd1,0x17,0x22,
+  0x43,0x58,0x4a,0x89,0x5f,0x79,0x9c,0xf5,0x50,0x9d,0xe1,0x3f,0xbf,0x29,0xe5,0x02,
+  0xa1,0x51,0xe0,0xfd,0x2b,0xe6,0x11,0xd9,0x36,0x57,0x56,0xfc,0xe7,0xc6,0xac,0x6a,
+  0x2f,0x47,0x38,0xce,0x1b,0x01,0x2d,0x59,0xa5,0x78,0x9c,0xfe,0xcf,0x4e,0xfc,0xc7,
+  0x0a,0x6b,0x64,0xd9,0x93,0x34,0x31,0x85,0xf2,0x29,0xe3,0x3f,0x8e,0xf0,0x81,0x73,
+  0x85,0xbc,0x1a,0x43,0xfe,0x4f,0xb7,0x9a,0x89,0xbf,0x95,0xe6,0xec,0xbf,0x4a,0x3a,
+  0xc9,0x5b,0x71,0xab,0xec,0xe2,0x88,0xf9,0xfc,0x9d,0x65,0x4f,0x38,0xf1,0xb7,0xfe,
+  0xa9,0xf6,0x6b,0xd4,0xb9,0xf2,0x1d,0xd3,0x5e,0x6d,0xcb,0x8f,0xff,0x84,0x5a,0x0f,
+  0xaa,0xa6,0x19,0x77,0x95,0xf9,0x68,0x0f,0xc6,0x79,0x61,0x5d,0xbf,0xf3,0xbe,0xcf,
+  0x9d,0x7e,0x21,0x3c,0xc3,0x84,0xdf,0xa9,0x3f,0x4f,0x37,0xa1,0xe1,0xbd,0xdf,0x75,
+  0x3e,0x6c,0xfe,0x30,0x47,0x78,0x57,0x7f,0x57,0x67,0x42,0xc8,0xb5,0x1f,0xec,0x4a,
+  0x9c,0x91,0x6d,0x37,0x57,0xe1,0xf8,0x3b,0x0b,0x08,0x1d,0x63,0xeb,0x8d,0x17,0x82,
+  0x69,0x8e,0x7f,0x1c,0x92,0x56,0x7a,0x91,0xed,0xdc,0x97,0x53,0xb6,0x33,0x0f,0x85,
+  0x77,0xb0,0x35,0x2b,0x13,0xda,0xbe,0xe6,0x18,0x88,0xa9,0xf1,0x8f,0x25,0x7c,0x50,
+  0x3d,0xc8,0xc6,0x33,0x28,0xa5,0xe5,0xc7,0x7f,0xdc,0x78,0x9b,0xee,0x82,0x00,0x13,
+  0x66,0x8e,0x08,0x3b,0x39,0xf1,0x63,0x61,0x26,0xff,0x45,0xe5,0x95,0x32,0x96,0x01,
+  0x6e,0x40,0x36,0xb5,0x3d,0x5f,0xed,0x77,0x36,0x50,0x44,0xfe,0xed,0x92,0x94,0x92,
+  0x53,0xff,0x2e,0xf2,0xfe,0x2d,0x56,0xda,0xc2,0xe5,0xdf,0x4f,0xc0,0x3f,0x98,0xc0,
+  0x2f,0xeb,0x7c,0xd8,0xee,0xd0,0x96,0x83,0xf6,0xe9,0x7b,0x07,0x03,0xcd,0x9e,0xaa,
+  0x7d,0xff,0xc7,0xcf,0x43,0x3c,0x68,0xdf,0x0d,0x05,0x3c,0x7d,0xef,0x13,0xee,0x2f,
+  0x77,0x37,0x69,0x66,0xdf,0x0f,0x0c,0x89,0x4f,0x2d,0xb8,0x3f,0xff,0xcf,0x9e,0xc7,
+  0xc7,0x3e,0x62,0x08,0xfe,0x94,0xcf,0x7f,0xc6,0xf3,0x10,0xe1,0x7f,0xe2,0x3c,0xc4,
+  0x2a,0x63,0x6d,0xc8,0xba,0x1b,0x13,0x0e,0xca,0x5f,0xfd,0x77,0xce,0x43,0x44,0x02,
+  0x8a,0xa5,0x3f,0x64,0xa2,0xf0,0x04,0xf9,0x27,0xe9,0x1f,0xef,0x66,0x69,0xdb,0xba,
+  0xed,0x54,0xfa,0xcf,0x9c,0x87,0xe8,0x35,0x9c,0x1f,0x82,0x09,0x07,0xa1,0xd9,0x35,
+  0xea,0xe2,0x79,0x88,0x9f,0x2c,0xfc,0x7f,0x79,0xfc,0x7f,0xb2,0xf7,0xf1,0x4f,0xbe,
+  0x7f,0xc6,0xfa,0x71,0xc3,0xd8,0xfc,0x7f,0xdc,0x1e,0x66,0x7f,0x9a,0x3f,0xe9,0x4b,
+  0xfe,0x3c,0x6b,0x43,0x5c,0xc9,0x53,0xb8,0xa1,0xff,0xad,0xfa,0xff,0xc4,0x1f,0x22,
+  0xf3,0x71,0xec,0xa1,0xe5,0x8f,0xfe,0x77,0x9c,0x0f,0x5b,0x65,0xfc,0x69,0xfa,0xcf,
+  0x7e,0xfe,0x7f,0x5f,0xff,0xae,0xf1,0xff,0xa1,0xf3,0x61,0xbd,0x43,0x17,0xed,0xe1,
+  0x7f,0x1a,0xfb,0xf3,0x9f,0x6c,0xfc,0x8b,0x0b,0xa0,0x53,0x7f,0x53,0xbd,0x0e,0x8a,
+  0x87,0x44,0x2e,0x54,0x14,0xbf,0x28,0xde,0x63,0xdc,0xa9,0x7e,0xca,0x12,0x22,0x9f,
+  0x92,0x0a,0x8c,0x59,0xce,0xf8,0x9b,0xda,0x85,0x7b,0x84,0x3b,0xf5,0x3f,0x57,0xd5,
+  0x9e,0x02,0x53,0x98,0x3e,0xec,0x08,0xd6,0x57,0x57,0x18,0xb3,0x9c,0x0d,0x12,0x25,
+  0x82,0x46,0x3b,0xb4,0x32,0x59,0xda,0x67,0x0a,0x95,0x78,0x6c,0xa1,0x79,0x85,0x0b,
+  0x51,0x26,0x50,0xcd,0xb9,0x3f,0x05,0x21,0x0a,0x95,0x70,0x09,0x7c,0x87,0x32,0x61,
+  0x29,0x5c,0x22,0x17,0x30,0x41,0x58,0x0a,0x9f,0xaf,0xb4,0x05,0x28,0xa0,0x9a,0xf3,
+  0x0a,0xdc,0xb4,0xb4,0x60,0x8e,0xf0,0x59,0x7a,0xfb,0x02,0x29,0x5e,0x70,0xaf,0x70,
+  0x27,0xfd,0x73,0x6d,0xfa,0x88,0x2d,0x1c,0x14,0x6e,0x13,0xee,0x4c,0x32,0xc1,0xf5,
+  0x3c,0x2f,0xea,0xba,0xa6,0xca,0x12,0x11,0xd8,0x5f,0xc2,0x3f,0x54,0x08,0x42,0xcc,
+  0x14,0x54,0x21,0x26,0x59,0x57,0x68,0x06,0xe2,0xbd,0xd8,0x21,0xdd,0x25,0x54,0xd2,
+  0x9b,0x99,0x61,0x95,0x34,0x41,0x4e,0xb4,0x6a,0x6a,0x5c,0xaa,0x16,0x64,0x68,0x0d,
+  0xa9,0x3d,0x78,0x05,0x05,0x9a,0xd1,0xcf,0x8b,0x0b,0x57,0xdf,0xd6,0x75,0x47,0xf2,
+  0xcf,0x02,0x92,0x5c,0xd0,0xda,0x15,0x99,0xb8,0x23,0x30,0xdd,0x53,0xa0,0xd3,0x88,
+  0x56,0x11,0x98,0x4e,0x4c,0xc1,0x5b,0x00,0x2e,0xfd,0x5c,0xd1,0xf5,0xe7,0xf0,0x67,
+  0xc6,0xf4,0x88,0x74,0xbf,0xf0,0x67,0x4c,0x28,0xed,0x2c,0xb8,0x53,0xb8,0x9d,0xde,
+  0x61,0x4c,0x0f,0x31,0xa1,0x1c,0x98,0x30,0x57,0x72,0xb6,0x5f,0x6c,0xbc,0xa6,0x77,
+  0x40,0x19,0x48,0x94,0x99,0xab,0x56,0x50,0x75,0x01,0x4d,0x60,0x1b,0xa8,0x54,0x52,
+  0x05,0x89,0xd9,0x08,0x14,0xd4,0xa1,0xcc,0xf8,0x17,0x97,0x31,0x8b,0xc1,0x13,0xd1,
+  0x1a,0xdb,0xe6,0xc6,0x90,0x7f,0xad,0x11,0xfb,0x4a,0x21,0x17,0x92,0xf2,0x02,0x97,
+  0x7e,0x22,0xd3,0x96,0x0b,0xff,0x05,0x3e,0xaf,0x57,0xd0,0x02,0x53,0x98,0x9e,0x28,
+  0x88,0x0a,0x47,0xe0,0xef,0x80,0x09,0x9a,0x29,0xb8,0xe7,0xab,0x8b,0x51,0x38,0x02,
+  0x73,0x90,0xaf,0x87,0xbf,0xd7,0x1c,0x28,0xa6,0xe2,0x5d,0xc2,0x52,0x7a,0x09,0x17,
+  0x00,0x05,0xf7,0xf8,0x9b,0x5a,0xa5,0x50,0x97,0x57,0x6b,0x93,0xe5,0x98,0x14,0xa2,
+  0x28,0xa8,0xfb,0xac,0x2b,0xea,0x3e,0x35,0x34,0xc4,0x05,0xd7,0xef,0xc5,0x3e,0x21,
+  0xc0,0x8e,0x2d,0xec,0xf7,0xb2,0x04,0xc3,0x16,0x46,0x4c,0x41,0x03,0xc3,0xa5,0x1f,
+  0x22,0x84,0xe8,0x62,0xad,0x5c,0x96,0x62,0xb6,0xb0,0x4f,0x08,0x19,0x8b,0x43,0xb7,
+  0xcb,0xd2,0x2b,0x42,0xa8,0x8b,0x09,0x5e,0xc9,0x35,0xfe,0xc5,0xd6,0x82,0x68,0xd7,
+  0x52,0xed,0xf3,0x6c,0xbc,0x64,0x0a,0xd3,0x63,0x05,0xd1,0xa1,0xa5,0x21,0x26,0x74,
+  0x0b,0x9a,0x29,0x50,0x97,0x7e,0x5a,0x4d,0x5d,0x3a,0x4a,0x35,0x05,0xaf,0x26,0x32,
+  0x41,0x32,0x05,0x21,0x7b,0xbe,0xd1,0xae,0x4a,0xed,0xe6,0x0e,0xd8,0xc8,0x84,0x4b,
+  0xb5,0x9b,0xe5,0xd2,0x98,0xb4,0x1c,0xe7,0xdb,0x51,0xba,0x51,0xd2,0x50,0x58,0xec,
+  0x5e,0x3f,0x37,0x45,0x0b,0x96,0x0a,0x9f,0x87,0x3f,0xa3,0x92,0x26,0x99,0xc2,0x74,
+  0xbc,0x52,0x08,0xa5,0x28,0xc8,0x70,0x33,0x0a,0xba,0x6b,0xfd,0xdc,0x2c,0x7c,0x8e,
+  0xde,0x11,0x9d,0xde,0xcf,0xde,0xa6,0x05,0x34,0x12,0xad,0xa8,0x2c,0x28,0xcc,0x13,
+  0x9c,0xed,0x32,0xf3,0x5e,0x6c,0xef,0xc9,0xde,0x3e,0xa2,0x43,0x19,0x13,0x16,0xf0,
+  0x77,0xa1,0x54,0xa2,0xec,0xa5,0xe8,0x90,0xf0,0x0a,0x0a,0x15,0xae,0xf1,0x2f,0xde,
+  0x4c,0x3e,0x47,0x37,0x45,0xab,0x55,0xb8,0x59,0xc4,0x3f,0x34,0xab,0xb2,0x18,0x85,
+  0xc3,0xd1,0x6b,0x99,0x30,0xcd,0x12,0x5c,0xcf,0xf3,0xe2,0xcd,0x05,0xf7,0x74,0xdd,
+  0x19,0xfd,0xf3,0xca,0xab,0x5e,0x2a,0xb8,0x67,0xf5,0xe6,0xe8,0xe7,0x2b,0x4b,0x99,
+  0x10,0x7b,0x33,0xfa,0xf7,0x95,0xd3,0x99,0xd0,0xc5,0x05,0x97,0x3d,0x69,0xbf,0x59,
+  0xc4,0x8b,0xd7,0x55,0x16,0xbc,0x44,0xee,0xa1,0x28,0x14,0xbf,0x24,0xe2,0x1d,0x3e,
+  0xc5,0x84,0x69,0xf7,0x50,0xbc,0xd5,0x74,0xa3,0x34,0xa3,0x1f,0xeb,0xfe,0x4b,0xe5,
+  0x35,0x28,0x2c,0xfb,0x73,0xbc,0x6d,0x75,0x97,0x1c,0xfd,0x0c,0x13,0x60,0x56,0x97,
+  0x37,0xda,0x56,0x59,0x41,0x4b,0x9d,0xe7,0x61,0xef,0x87,0x06,0xfc,0x8d,0x71,0x0c,
+  0x51,0x8c,0x4d,0xd3,0x5c,0x21,0xec,0x87,0xbb,0x53,0xfb,0x14,0xb3,0x3f,0xae,0xd5,
+  0x56,0x28,0x2c,0xeb,0x5a,0x1a,0xbd,0x04,0xcd,0xd4,0x32,0x8a,0x42,0x81,0x29,0x7c,
+  0x1e,0x85,0x6a,0xfe,0xd5,0x74,0x9a,0xc9,0x5f,0xdc,0xa4,0x17,0x84,0xb4,0xc5,0xf2,
+  0xed,0x20,0xd1,0x82,0x4e,0xe1,0x4e,0xf8,0x73,0x98,0x6e,0x14,0x74,0x82,0x25,0x84,
+  0xac,0x2b,0x99,0xe7,0xb9,0xa9,0x95,0xb2,0x17,0x2e,0xc0,0x97,0x4d,0x94,0x56,0x6a,
+  0x92,0x2c,0x98,0x42,0x21,0x0a,0x9a,0x29,0x50,0xd7,0x7c,0x5b,0x7b,0xa2,0x49,0xb6,
+  0x7e,0xf8,0xea,0xea,0x92,0xf9,0x49,0xb7,0x12,0x2e,0x3c,0x2e,0x44,0xcd,0x2b,0xee,
+  0xf1,0x6d,0x57,0x45,0x8c,0x3b,0x42,0x7f,0x26,0xbf,0xc8,0xac,0x4d,0x57,0x44,0xbb,
+  0x43,0xb6,0xcd,0x8e,0x3c,0x5d,0x2c,0x88,0x50,0xbc,0x52,0x00,0x99,0xe7,0x01,0x51,
+  0xc0,0xf1,0xd3,0x65,0xa9,0xcd,0x14,0xbc,0x05,0x4c,0x18,0xe2,0x42,0xab,0xf5,0x55,
+  0x81,0xee,0xd2,0x0f,0xe8,0xba,0xaa,0x4a,0x92,0xa0,0xc6,0xd1,0xfe,0x50,0xd3,0x04,
+  0x9a,0x02,0xc0,0x5d,0x5c,0x28,0x75,0x8d,0xbe,0x69,0x21,0x21,0x94,0x26,0xb5,0x0e,
+  0x4a,0x08,0x50,0x1a,0xd2,0x64,0x99,0x0b,0x1a,0x0a,0x85,0x96,0xe0,0x7a,0x1e,0xa6,
+  0x4f,0xd3,0xc8,0xd7,0x52,0x2e,0x3c,0xc4,0xac,0x87,0x80,0x16,0x06,0xcd,0x8e,0x6d,
+  0x88,0x5c,0xf3,0x5d,0xad,0x8b,0xf8,0xed,0x25,0x30,0x4c,0x45,0xd3,0x10,0x15,0xa3,
+  0x70,0x27,0x7c,0x8a,0x0d,0x9b,0xa6,0x71,0x21,0xeb,0xf7,0x05,0x29,0x24,0xa0,0xf5,
+  0xa0,0x94,0x0b,0xcc,0x74,0x1a,0x4c,0xa8,0x64,0x2f,0x16,0x18,0x44,0xe3,0x42,0xa5,
+  0x7b,0xbc,0x64,0x1a,0x19,0x9d,0xd9,0x9f,0x59,0xe0,0xd5,0xc5,0x08,0x1c,0x86,0xd9,
+  0x50,0x04,0x44,0x57,0x0f,0x43,0x2d,0x17,0xc0,0x3d,0xbe,0x40,0x98,0xa5,0x2f,0x8e,
+  0x94,0x27,0x7a,0x5e,0x44,0x21,0x5a,0x5e,0x21,0x31,0x61,0xc1,0xe2,0xc8,0xed,0x15,
+  0xd2,0x70,0x57,0x35,0x0a,0x6a,0xd6,0xf3,0xd4,0x14,0xac,0x18,0xfa,0x42,0xe8,0xf3,
+  0xf1,0x82,0x47,0x4d,0x61,0xfd,0x74,0x5b,0x28,0xf8,0xc1,0x6a,0xeb,0x8a,0x7b,0xbc,
+  0x97,0x03,0xfd,0x42,0xfc,0xa3,0x1c,0x6c,0xde,0x01,0xdf,0xb1,0x1f,0x23,0x31,0xd5,
+  0xf3,0xc0,0xf2,0x68,0x69,0xa5,0xc4,0xde,0xfa,0x78,0xbb,0xe9,0xc8,0x4a,0xe3,0xd2,
+  0x5d,0xa5,0x95,0x3d,0x37,0x57,0x0b,0x3d,0xcb,0x4d,0xa1,0xd4,0x3d,0x5e,0xb8,0x29,
+  0x52,0x7a,0x87,0xf4,0x67,0x42,0x05,0x14,0x44,0x3e,0x87,0xc2,0x74,0xfd,0xa6,0x08,
+  0xdc,0x21,0x4d,0x87,0x02,0x7d,0x41,0x24,0x74,0x87,0x77,0xba,0x90,0xb5,0x1e,0xe4,
+  0x6a,0x22,0xeb,0x31,0x55,0xeb,0x91,0xab,0x5b,0xe5,0x48,0xac,0x42,0x2b,0x90,0x85,
+  0xd6,0x00,0x0a,0xd3,0xe5,0xea,0xdb,0xf8,0x95,0xd5,0xee,0xc7,0xf1,0x00,0xa1,0x90,
+  0xd4,0x03,0x15,0x1e,0x81,0x50,0x7d,0xbb,0x1a,0x90,0x98,0x90,0xd0,0x93,0x28,0xa4,
+  0x99,0xb0,0x4d,0xad,0xab,0x70,0x8f,0xf7,0x92,0x72,0xe8,0x31,0x96,0x85,0x84,0xc5,
+  0xe2,0xed,0x70,0xf8,0xc0,0xac,0x50,0x31,0x13,0xd4,0xc3,0xc6,0xb5,0xa1,0x82,0xc5,
+  0xef,0x94,0xc3,0xe1,0xe1,0x6b,0x9b,0x8a,0xdd,0xcf,0x53,0x54,0x70,0xef,0x82,0xaa,
+  0x84,0x09,0x03,0xa0,0x8a,0x5e,0x62,0xe2,0x81,0x37,0xe9,0xdf,0x3b,0x82,0x7f,0xba,
+  0xe1,0x1a,0xaf,0x7c,0xa1,0xf5,0x67,0x89,0x27,0xb7,0xd5,0x17,0x7d,0x7a,0x21,0x13,
+  0x76,0x6f,0xab,0xbf,0x45,0xb9,0x6d,0xe1,0xe8,0xc6,0x27,0x6b,0x7f,0x54,0xa4,0xb4,
+  0x2e,0x3c,0xcc,0x05,0xf7,0xf3,0xdc,0x70,0xfe,0xd6,0xf3,0xff,0xfa,0xfc,0x89,0xf7,
+  0x4f,0xb6,0x7c,0x8b,0x09,0x4f,0x9f,0xf8,0xfd,0xc9,0x1b,0xce,0x2d,0xf9,0xd5,0x83,
+  0xe7,0xc7,0xce,0x9e,0xbc,0xe1,0xbe,0x25,0xe7,0xb9,0x00,0xff,0x0b,0x9f,0xf0,0xc3,
+  0x45,0x33,0x5b,0x6f,0x49,0x6c,0x5c,0x7e,0xd5,0x49,0xdf,0x63,0x6d,0xe7,0x13,0xa7,
+  0xfe,0x21,0xfc,0x4f,0xb7,0x7c,0xeb,0xf5,0x5b,0x12,0xdf,0x3d,0xdb,0x72,0xfe,0x96,
+  0xab,0x5f,0xbf,0xe5,0xc4,0x77,0xc7,0xdc,0xe3,0x5b,0xee,0xbb,0xf5,0x57,0x0f,0x3e,
+  0x3d,0xf6,0xbe,0xf3,0x18,0x67,0xcd,0x07,0x1b,0xfb,0x3d,0x1b,0x7f,0xeb,0xaf,0xf8,
+  0x13,0xba,0xc7,0xd7,0xdc,0xd7,0xf1,0xab,0x8d,0xd7,0x8d,0xad,0x5f,0x76,0x03,0xfe,
+  0xc3,0x9d,0xf8,0x0f,0xef,0xbb,0xf5,0xad,0xf2,0xa7,0x7b,0xde,0x3f,0x59,0x53,0xc9,
+  0x85,0x63,0xcb,0xb2,0x1e,0x28,0xd6,0xa9,0x6f,0x56,0xaf,0xbe,0x74,0xba,0x41,0x98,
+  0x00,0x57,0x57,0x14,0xbd,0x48,0xee,0x31,0xd8,0x95,0x8a,0xa2,0x21,0x06,0x1d,0xab,
+  0xd4,0x69,0x65,0x97,0xba,0xf5,0x29,0x59,0x68,0x50,0x18,0xbe,0x8a,0x0b,0x95,0x2e,
+  0x7c,0x28,0xcd,0x12,0xbc,0x7a,0x9b,0x5a,0xe9,0x1e,0x6f,0x9b,0xe5,0x9e,0x58,0xc6,
+  0x3e,0x5b,0x40,0x31,0x56,0xdd,0x89,0xf6,0xb9,0x92,0xd2,0xac,0x07,0x32,0xd1,0x5a,
+  0x17,0xb5,0x61,0x5b,0x0f,0x2c,0x63,0xbb,0x37,0x84,0x6d,0xb5,0xd1,0x4b,0x2b,0xc9,
+  0xcd,0x90,0x35,0x5e,0x6e,0xbf,0xb7,0xc8,0x4b,0xdb,0x0a,0xe8,0xfe,0xe5,0x4d,0x42,
+  0x55,0xcf,0x67,0xb4,0xd2,0x11,0xe9,0x5e,0xa1,0x8a,0x7e,0x26,0x60,0x0a,0xf1,0xcf,
+  0x5c,0x23,0x18,0xd9,0xf7,0x8f,0xc8,0x85,0xa4,0x00,0x5d,0x21,0x54,0xaa,0x78,0x5b,
+  0x1b,0x28,0xda,0x42,0xd6,0xfb,0xe5,0x95,0xfc,0xf8,0x5a,0x45,0x18,0x3e,0xbc,0x4b,
+  0x90,0x69,0x6b,0x54,0x7d,0x44,0xba,0x7a,0x01,0x17,0x12,0x15,0xb5,0x42,0x11,0xb4,
+  0x66,0xbf,0x8f,0x9f,0x96,0x16,0x0e,0x5d,0x92,0xbc,0x29,0x0e,0x0d,0xd2,0x17,0xba,
+  0xca,0x92,0xed,0xdb,0x4b,0xeb,0xa4,0x85,0x28,0xec,0x28,0x9d,0x09,0x1d,0xf4,0x32,
+  0x4d,0xda,0xe1,0xda,0x6d,0xca,0x46,0x31,0x94,0x43,0x85,0x51,0xb0,0x49,0x2d,0x66,
+  0x46,0xab,0x62,0x14,0xd8,0x8b,0x00,0xb7,0xe3,0x95,0x10,0xdc,0x0d,0x7f,0x01,0x97,
+  0x18,0x05,0xbb,0x33,0xec,0x1f,0x66,0xc3,0x0a,0x99,0x2e,0xd8,0x5e,0xb6,0x53,0xed,
+  0x01,0xdc,0xdd,0x82,0x2e,0xa8,0x70,0x13,0x5e,0xd1,0x99,0x2d,0x44,0xf4,0xc0,0x40,
+  0xae,0x1e,0xca,0xdc,0x1f,0xf7,0xad,0x6c,0x5f,0xc9,0x36,0xbf,0xb8,0xc1,0x54,0xdd,
+  0x3b,0x4d,0x2b,0x04,0xa7,0xc9,0x59,0xe3,0xa5,0x28,0x37,0x92,0xdc,0xe2,0x57,0xc2,
+  0x6d,0xe6,0x1d,0x2b,0xf9,0xad,0x0b,0xa3,0x42,0x3f,0x7c,0x99,0x09,0xce,0x78,0x55,
+  0x00,0x12,0x85,0x7e,0x98,0xa9,0xc9,0xd4,0x14,0xa0,0xc8,0x11,0xe2,0x12,0xbe,0xa1,
+  0xd3,0x90,0x28,0x69,0x7f,0x74,0x1b,0x1f,0x76,0x40,0xb7,0x03,0x0b,0x6d,0xe1,0x75,
+  0x06,0x9c,0x18,0x82,0xea,0x50,0x33,0xfe,0x5d,0x97,0x5c,0xf8,0x50,0xcd,0xc1,0x87,
+  0x46,0x66,0xdf,0xec,0xdc,0x9f,0xfd,0x67,0xc8,0x44,0x6b,0xdd,0xb6,0xb0,0xcf,0x16,
+  0x5e,0x00,0x86,0x3f,0x43,0x6d,0xb2,0x7b,0xbc,0x8d,0xdf,0xd0,0xff,0x9a,0x42,0xa9,
+  0x23,0x74,0x03,0x13,0x42,0x4c,0x70,0x3d,0x8f,0x30,0x35,0x3e,0x34,0x05,0xc9,0xfa,
+  0x43,0x99,0xfb,0x47,0x84,0xa9,0xef,0xaf,0x9a,0x82,0x89,0x87,0x4b,0xdd,0xcf,0xa3,
+  0x4b,0x11,0x66,0x9b,0xd9,0x2f,0x6a,0x0b,0xa5,0x2e,0xc1,0x0c,0x89,0x94,0xb6,0x3a,
+  0xcf,0xd3,0xc1,0x96,0xeb,0x02,0x5a,0x11,0x2d,0xa8,0x64,0x10,0xf2,0x73,0x54,0x8d,
+  0x4a,0x28,0x2c,0xc8,0x16,0x16,0x64,0x96,0x4f,0x07,0x22,0x26,0xf6,0x9b,0x33,0xbc,
+  0xc4,0xfe,0x8b,0xea,0x60,0xed,0x95,0x9c,0x4d,0x13,0x13,0xc0,0xb5,0x3e,0xf5,0x9b,
+  0x3e,0xcf,0xd0,0x60,0x4f,0xf4,0xaa,0x08,0x5c,0x42,0x4a,0xe9,0x4f,0x39,0x2c,0xb4,
+  0xf1,0x61,0xbb,0xf8,0x39,0x38,0xbc,0xe0,0xda,0x48,0xb1,0xee,0xc2,0x63,0x37,0x4b,
+  0xf7,0x74,0x55,0x31,0x50,0x57,0xfa,0x12,0x17,0xa6,0xd9,0xc2,0x67,0x98,0x50,0x78,
+  0x4f,0xd7,0xe6,0xe8,0x5f,0x57,0x96,0x1a,0x99,0xfb,0x0b,0x37,0x33,0x58,0xb8,0x39,
+  0x7a,0x35,0xfb,0x96,0x0b,0x9f,0xa9,0x2c,0x7a,0xc9,0xba,0x52,0xf4,0x12,0xdc,0x43,
+  0xab,0x18,0x50,0x74,0x8d,0x8f,0xd8,0xf8,0xb0,0x12,0x5e,0x2a,0x30,0x61,0xe4,0xf4,
+  0x97,0xac,0x2b,0xd3,0x5f,0xaa,0x98,0x45,0xbd,0xec,0x0e,0xc5,0xfb,0x32,0xbf,0x17,
+  0x83,0xc1,0x1c,0x1f,0x32,0xef,0xc9,0xcc,0xce,0x2d,0xa6,0xfd,0xa9,0x45,0xfb,0xd3,
+  0x21,0x6d,0x14,0xd0,0xfe,0x94,0x2f,0x96,0xa8,0x13,0x62,0xd2,0xd9,0xba,0x5d,0x46,
+  0x2b,0xa3,0x85,0xfd,0xea,0x63,0x4c,0xb8,0x2c,0x5a,0x58,0x29,0xac,0x81,0x65,0x3d,
+  0x95,0x5c,0x90,0x96,0x75,0x55,0x46,0x6f,0xee,0x17,0x32,0xbf,0x17,0xc3,0xf3,0xd2,
+  0xaa,0xea,0x12,0xb9,0x2d,0x06,0xc9,0x9e,0xb9,0xc2,0x0c,0x10,0x69,0x29,0x1e,0x74,
+  0x3b,0x03,0x3e,0x93,0x11,0x04,0xc3,0xb5,0x7e,0x6e,0x83,0x28,0xe2,0xc3,0xc5,0xd8,
+  0xdd,0x9e,0x5e,0xca,0x96,0x0d,0x83,0x85,0xcb,0x11,0x16,0x76,0x08,0x1b,0x4d,0xa0,
+  0xd8,0xe1,0xba,0xbf,0x5e,0x40,0x24,0x6d,0x0b,0x5f,0x3f,0xeb,0x10,0x0d,0x26,0x0b,
+  0x39,0x3e,0x74,0x80,0x22,0x17,0xd8,0x6b,0x9d,0xf9,0xbd,0x88,0xa4,0x0f,0x55,0x84,
+  0x6e,0x62,0x2f,0x88,0x14,0x61,0xcb,0xec,0x33,0x72,0x29,0xbb,0xb2,0x5a,0xd5,0xda,
+  0x99,0x00,0x3a,0x33,0x00,0x0c,0x91,0x42,0x69,0x66,0xbe,0xec,0x7d,0x31,0x2a,0x42,
+  0x6c,0xe7,0xe1,0x61,0x2f,0x54,0x45,0x52,0xf0,0x0a,0x6d,0x10,0xc1,0x2b,0x8e,0x20,
+  0xb3,0x51,0xba,0x33,0x5e,0x06,0xd5,0xc4,0x87,0xa0,0xfb,0x99,0xda,0x04,0x17,0x3e,
+  0xb4,0x05,0x17,0x3e,0x64,0xef,0x97,0xbf,0x0c,0xf1,0xa1,0xa7,0x9f,0xf8,0x99,0xe1,
+  0xf6,0x0b,0x0e,0x3e,0xf4,0xa2,0x90,0x84,0x80,0x56,0x44,0x75,0x97,0x7e,0x74,0x6a,
+  0xda,0x9f,0x52,0xb6,0xea,0x84,0x4a,0xf9,0xcb,0x6e,0xfb,0x73,0x73,0xb4,0xb4,0x5f,
+  0xfa,0xb2,0x78,0xad,0x4b,0x3f,0x82,0xbe,0x75,0x39,0x5c,0x0a,0x33,0xf5,0xa2,0x44,
+  0x2c,0x0a,0x0f,0xcb,0xcc,0xec,0x24,0x6c,0xfb,0x93,0xd0,0x3b,0xd5,0x2a,0x98,0x26,
+  0x16,0xb9,0xdf,0xaf,0x65,0xd2,0x5c,0x28,0x81,0xb6,0x18,0xc5,0xdf,0xab,0x44,0x6a,
+  0xa3,0x6a,0x5a,0x62,0x02,0xa0,0x50,0xbb,0xa2,0xe8,0x32,0x72,0x73,0x57,0x22,0xf3,
+  0x7b,0x45,0xd8,0xeb,0x72,0x7d,0xb4,0xe4,0x0e,0xf1,0x21,0xf8,0x67,0x1a,0xd2,0xbd,
+  0xaa,0x28,0xc1,0xcb,0x60,0x09,0x43,0x98,0xf5,0x60,0xea,0x05,0xd7,0x7a,0x86,0x02,
+  0xb8,0xd6,0x28,0x8e,0x30,0x18,0xb9,0x09,0x66,0xe9,0xc5,0xba,0x58,0x01,0x3f,0x65,
+  0x82,0x37,0x22,0xaa,0xf0,0xd3,0xda,0x59,0x0b,0xbc,0x91,0x36,0x15,0xf6,0xb9,0x9e,
+  0xa7,0x4d,0x8a,0x0e,0x55,0x76,0xb2,0xdf,0x77,0x2d,0x0a,0xa1,0x9b,0xbd,0xa5,0xdd,
+  0xb6,0xe0,0x58,0x0c,0xf7,0xfa,0xd1,0xa1,0x06,0x03,0xc1,0xaa,0x15,0x2c,0x14,0x21,
+  0x93,0x57,0x59,0x6d,0x19,0x46,0xf7,0xfa,0x11,0x3a,0xda,0x11,0x1f,0xde,0x2c,0x40,
+  0x4f,0xfb,0x5d,0x28,0x54,0x3b,0xf8,0x90,0x09,0x4d,0xa5,0xde,0x9e,0xb6,0x6a,0xd5,
+  0xbd,0x7e,0xf4,0xf6,0x3b,0x4a,0xa7,0x57,0xdc,0xf4,0x19,0x55,0x6d,0x8f,0x94,0x56,
+  0x48,0x9f,0x13,0x4a,0xf5,0x76,0x66,0x7f,0xa4,0x9b,0x98,0x00,0xfc,0x97,0x17,0x54,
+  0xd7,0xef,0x05,0xb8,0x00,0xef,0xb0,0x4d,0xa0,0x1a,0x2b,0xb0,0x96,0x41,0x0c,0xd7,
+  0x83,0xbd,0x48,0xc1,0xe5,0xc1,0x18,0x3e,0xec,0xc2,0x9f,0x9d,0x03,0x45,0x9d,0x09,
+  0x12,0x07,0x8a,0x88,0x0f,0x15,0x4b,0xe8,0x71,0xaf,0x9f,0xcf,0xd6,0x94,0x2f,0xe8,
+  0x19,0xad,0x9e,0x0d,0x9f,0x25,0xe5,0xfa,0x61,0x26,0x14,0x7f,0x56,0xbc,0x9d,0x09,
+  0xd7,0xba,0x04,0xf7,0xfa,0xe9,0xe0,0xf8,0xf0,0x33,0xfe,0xd2,0xfd,0xed,0x1c,0x06,
+  0x38,0x78,0x40,0x2b,0xdd,0x5f,0x78,0xaf,0xb0,0x99,0xfe,0xb5,0xe6,0xb2,0x27,0xcc,
+  0x5f,0x2f,0xb4,0xf0,0xa1,0xb2,0x70,0x21,0xe2,0xc3,0x1f,0x59,0xf8,0x70,0x5b,0x06,
+  0x1f,0x5e,0xe3,0x1a,0x0e,0x1c,0x7d,0x21,0x3e,0xbc,0xe1,0x5b,0x4b,0x10,0x1f,0x9e,
+  0xb7,0x80,0xd9,0x89,0xff,0x4d,0xf8,0x90,0xc3,0xc2,0x77,0x13,0xe7,0xcf,0xb6,0x9c,
+  0x34,0x81,0xa2,0x8d,0x0f,0x37,0xfe,0x83,0x73,0xc5,0x3d,0x9e,0xff,0xf5,0x3f,0x8e,
+  0xb1,0xf1,0xe7,0x4c,0xa0,0x68,0xe3,0xc3,0xf7,0x33,0x57,0xb2,0xc6,0xcf,0xb0,0xf0,
+  0x61,0xcd,0x8c,0x5b,0x7f,0xb5,0x71,0x96,0x89,0x0f,0x71,0xd8,0xb1,0xaf,0xdf,0xb0,
+  0x6a,0x2a,0x7c,0xf8,0x27,0x7d,0x42,0xa0,0x09,0xec,0xb5,0x66,0xff,0xdf,0xe6,0xfd,
+  0x9f,0xbf,0xcb,0xc5,0xcf,0xc5,0xcf,0xc5,0xcf,0xc5,0xcf,0xc5,0xcf,0xc5,0xcf,0xc5,
+  0xcf,0xc5,0xcf,0xc5,0xcf,0xc5,0xcf,0xc5,0xcf,0xff,0xbf,0x7f,0xf8,0xde,0x41,0xba,
+  0xb8,0x77,0xb8,0xf8,0xb9,0xf8,0xb9,0xf8,0xb9,0xf8,0xb9,0xf8,0xb9,0xf8,0xb9,0xf8,
+  0xb9,0xf8,0xb9,0xf8,0xb9,0xf8,0xb9,0xf8,0xf9,0xe4,0x0f,0xdf,0x3b,0x14,0x5e,0xdc,
+  0x3b,0x5c,0xfc,0x5c,0xfc,0x5c,0xfc,0x5c,0xfc,0x5c,0xfc,0x5c,0xfc,0x5c,0xfc,0x5c,
+  0xfc,0x5c,0xfc,0x5c,0xfc,0x5c,0xfc,0x7c,0xf2,0x87,0xef,0x1d,0x64,0xbe,0x77,0xf8,
+  0x3f,0xfd,0x28,0x17,0x3f,0x17,0x3f,0x17,0x3f,0x17,0x3f,0x17,0x3f,0x17,0x3f,0x17,
+  0x3f,0x17,0x3f,0x17,0x3f,0x17,0x3f,0x17,0x3f,0xff,0x2f,0x7e,0x42,0x58,0x1f,0x07,
+  0x3f,0x5b,0x19,0x02,0xde,0x03,0x40,0x0c,0x81,0xfe,0x27,0xe7,0x13,0xac,0x7f,0x5b,
+  0x10,0x82,0xa4,0x90,0xb9,0xe7,0xd1,0x2f,0xe4,0x8e,0xfb,0xbf,0x01,0x1e,0x39,0x58,
+  0x36,0xf1,0x33,0x01,0x00,
diff --git a/u-boot/board/esd/voh405/logo_320_240_4bpp.c b/u-boot/board/esd/voh405/logo_320_240_4bpp.c
new file mode 100644
index 0000000..e9f8cb4
--- /dev/null
+++ b/u-boot/board/esd/voh405/logo_320_240_4bpp.c
@@ -0,0 +1,77 @@
+  0x1f,0x8b,0x08,0x08,0x7f,0x95,0xab,0x3f,0x00,0x03,0x50,0x50,0x43,0x5f,0x53,0x74,
+  0x61,0x72,0x74,0x6c,0x6f,0x67,0x6f,0x5f,0x31,0x36,0x67,0x2e,0x62,0x6d,0x70,0x00,
+  0xed,0x9b,0xcb,0x71,0xe3,0x38,0x10,0x86,0x7b,0xaa,0xe6,0xb6,0x87,0x2e,0x4f,0x08,
+  0x3e,0xed,0xdd,0x09,0x6c,0x6d,0xf9,0x3a,0x47,0xa7,0xe0,0x10,0xc6,0x29,0x38,0x82,
+  0xad,0x72,0x0a,0x4e,0xc1,0x29,0x38,0x05,0xa7,0xe0,0xea,0x0c,0x30,0x12,0x89,0x06,
+  0x1a,0x4f,0x3d,0x2c,0x01,0x9c,0xad,0xff,0xf3,0x48,0xa2,0x44,0x82,0xf8,0xd8,0x20,
+  0x5e,0x24,0xe7,0xdf,0x9f,0xbf,0xfe,0xa3,0x85,0x5f,0xbb,0xd7,0xdf,0xbb,0xd7,0x3f,
+  0xdf,0x88,0x64,0xf7,0xf9,0x8d,0xbe,0x93,0xf2,0xe3,0xaf,0xf5,0x65,0xb9,0xb9,0xb9,
+  0xa1,0xdb,0xdb,0x5b,0xba,0xbb,0xbb,0xa3,0xfb,0xfb,0x7b,0x7a,0x78,0x78,0xa0,0xc7,
+  0xc7,0x47,0x7a,0x7a,0x7a,0xa2,0xe7,0xe7,0x67,0x7a,0x79,0x79,0xa1,0xd7,0xd7,0x57,
+  0x7a,0x7b,0x7b,0xa3,0xf7,0xf7,0x77,0xfa,0xf8,0xf8,0xa0,0xcf,0xcf,0x4f,0x72,0xce,
+  0xed,0x5f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0xff,
+  0x02,0xa1,0x8b,0x03,0x3f,0xf8,0xc1,0x0f,0x7e,0xf0,0xfb,0xb3,0xfd,0xf6,0x59,0xf3,
+  0x66,0xfd,0xc2,0xe6,0x7d,0xc5,0x49,0x7e,0xfb,0xcd,0x84,0x59,0xd8,0x1d,0x48,0x30,
+  0xc7,0x6f,0xd9,0x88,0x77,0x7f,0x3b,0x41,0xd7,0x0d,0xe1,0x14,0xbf,0x45,0x88,0x97,
+  0x7f,0xb2,0x38,0xb4,0x05,0x67,0xf8,0x2d,0x3a,0xb2,0x2a,0x2e,0xff,0xcb,0xb0,0x23,
+  0x38,0xc1,0x6f,0xd5,0xf3,0x21,0x5c,0xdf,0xa4,0x99,0x68,0xbc,0x9f,0x04,0xab,0xf5,
+  0x4d,0x5c,0x4f,0x70,0xb8,0xdf,0x6a,0xb2,0x48,0xad,0x7e,0xde,0xb2,0x51,0xc2,0xc3,
+  0xfd,0x28,0x37,0xf3,0xae,0x8d,0x64,0xa3,0xfd,0x24,0x96,0xa9,0xfa,0xf9,0x00,0xd6,
+  0xd3,0x8d,0xf6,0xb3,0xe1,0xd3,0x0f,0x31,0xe6,0x93,0xfd,0xba,0xd9,0x6d,0xc0,0x8f,
+  0x4c,0xc0,0x42,0xfc,0x7a,0x01,0x1c,0xeb,0x27,0xb6,0x5e,0xc4,0x4f,0x97,0xfe,0x3c,
+  0xcf,0x2f,0x0d,0x5f,0xee,0x57,0x4b,0x39,0xd4,0x2f,0x0b,0x5f,0x5c,0x68,0x17,0xf0,
+  0x58,0xbf,0x6a,0xd8,0xba,0x01,0x1c,0xea,0x97,0x15,0x6f,0xe1,0x27,0xae,0x60,0xa4,
+  0x5f,0x5e,0xbc,0x66,0xa9,0x59,0xc0,0x43,0xfd,0xea,0x51,0x33,0xab,0xca,0xb4,0x23,
+  0xfd,0x7a,0x35,0xbb,0x55,0xc0,0x98,0x5f,0xfe,0x39,0x7e,0xbb,0x21,0x8a,0x0e,0x9d,
+  0xd7,0x8d,0x74,0x58,0xef,0xc7,0xf7,0x93,0xdb,0xbf,0x5d,0x56,0x9c,0xf8,0x91,0xce,
+  0xdc,0x7c,0xa2,0xc9,0x7e,0xe4,0x0d,0xd4,0x4f,0x38,0x8e,0x9d,0xc3,0x8a,0x89,0x7e,
+  0x6c,0xfc,0x74,0xe6,0x46,0xce,0x2c,0xcc,0xf5,0x0b,0x33,0x36,0xeb,0x27,0x9b,0xf2,
+  0x5b,0xcf,0x37,0xbd,0x2e,0x54,0xfa,0x51,0x79,0x29,0xa1,0xea,0xb7,0xac,0x89,0x5f,
+  0xf9,0xb4,0x23,0xe9,0xc5,0xcf,0x2f,0x48,0x33,0x7e,0x79,0xea,0x4a,0xae,0x9c,0xad,
+  0x0a,0x87,0xb4,0x5b,0x32,0x0d,0xbc,0x6d,0xeb,0xcd,0x51,0x1f,0xe5,0x17,0x95,0x8e,
+  0xf5,0xe3,0xb0,0xc8,0xd9,0x3a,0xf3,0xfd,0x4b,0x7e,0x49,0xfd,0x50,0xb7,0xa2,0x7e,
+  0xb4,0xfc,0xd6,0x5d,0x67,0xc5,0x23,0x45,0x71,0x7d,0xc5,0x8f,0xf4,0x5a,0x41,0x6c,
+  0x5f,0xd6,0x98,0x9e,0xe4,0x97,0x9c,0xa0,0x14,0x5b,0xd0,0xa2,0x03,0x3f,0xd9,0x4f,
+  0x7c,0x36,0xa1,0x1a,0x84,0x33,0xdd,0x1d,0xac,0x1f,0x1c,0x96,0xfd,0xaf,0xc1,0x4f,
+  0x3f,0xc9,0x4e,0xac,0xcf,0xf2,0x2b,0xa7,0xe0,0x47,0x74,0xd5,0xb9,0x9f,0x1e,0x58,
+  0x38,0xd4,0xf0,0xdd,0x5c,0x37,0xa9,0xfa,0x1d,0xaa,0xbf,0xe7,0x21,0x66,0x9f,0xb6,
+  0x00,0xd4,0x94,0x5d,0x72,0x0c,0x62,0x44,0xe2,0x1a,0x3a,0xe4,0x57,0x36,0x12,0x7d,
+  0xf2,0x3a,0x9a,0x16,0xa7,0x3d,0x25,0x4d,0xce,0x13,0xfd,0x58,0x77,0xc3,0x59,0xa6,
+  0x72,0x19,0xbf,0xf3,0x09,0x7e,0xf1,0x42,0xb0,0xcd,0x48,0x74,0x13,0x73,0x29,0x67,
+  0x82,0x9f,0x5b,0x4b,0xf2,0x9a,0x7e,0xc2,0xbe,0x02,0x53,0xda,0xd8,0x2d,0x27,0x3d,
+  0xfb,0x2a,0xb9,0x16,0x97,0x6d,0x63,0x32,0x3f,0x93,0xa7,0x89,0xea,0x25,0xfc,0xa8,
+  0xe1,0xb7,0xef,0x34,0xc9,0xfa,0x49,0xdb,0xcf,0x5d,0xd3,0x8f,0xaa,0x7e,0xe2,0xf3,
+  0x26,0x13,0xe4,0xc2,0x8f,0xb5,0xa5,0xab,0xfa,0x91,0xc5,0x24,0xcc,0xfc,0xc2,0xfe,
+  0x3a,0x7e,0x12,0xfd,0xfc,0x4b,0x7b,0xe4,0xe8,0x47,0xd2,0xf6,0x0b,0xe1,0xba,0xbc,
+  0x1f,0x8b,0xcf,0x3a,0xf5,0xd3,0x89,0x47,0xf0,0x93,0x8a,0x9f,0xd3,0x9e,0xb6,0xea,
+  0x27,0x97,0xf0,0x93,0xa3,0xfd,0x78,0x96,0x1f,0x3b,0x56,0x3f,0x3d,0x65,0xfd,0x29,
+  0x68,0xeb,0x07,0xb9,0x8e,0x9f,0xe3,0x6b,0xfa,0xed,0x0d,0xcf,0xf1,0xe3,0xa8,0xd9,
+  0x6c,0xff,0xcc,0x6f,0x76,0xb5,0xf1,0x2b,0x0f,0x21,0xf5,0x5b,0xa2,0x47,0xd5,0xf2,
+  0x75,0x2e,0x94,0x6f,0x18,0x14,0xd6,0xfd,0x5c,0xee,0x97,0xe4,0xfc,0x05,0x3f,0x72,
+  0x99,0x9f,0x39,0x15,0xad,0x9f,0x56,0x69,0xeb,0xa7,0x3b,0xcf,0xca,0x33,0xef,0x7f,
+  0x35,0x9e,0xe7,0xfa,0x91,0xb8,0xd2,0x2f,0x6f,0x5f,0x8e,0xf0,0x2b,0xc6,0x2f,0x72,
+  0x21,0x3f,0x52,0x13,0xed,0x0f,0x54,0x26,0xb6,0xcf,0xc4,0x55,0xbf,0x38,0xca,0x8a,
+  0x3e,0x7e,0x29,0x0a,0x6b,0x07,0x73,0x8e,0x9f,0xf8,0xae,0xc2,0xfb,0xed,0xf1,0xb9,
+  0x2c,0xfd,0x9b,0x0e,0x89,0x25,0x9c,0x53,0xc6,0x8f,0x73,0xbf,0x38,0x90,0x16,0x33,
+  0x60,0x8d,0x53,0x99,0xba,0x9f,0x06,0xaa,0xee,0xc7,0xb9,0x1f,0x7b,0x3f,0x9f,0xd7,
+  0xb1,0x7e,0xe9,0x15,0x4c,0xe3,0xc9,0x1a,0x86,0x90,0xf2,0x14,0xbf,0x0e,0xbd,0xbb,
+  0xfb,0xa1,0xdf,0x0d,0xd9,0x54,0x1b,0xc7,0x6a,0xe6,0x97,0xf2,0xeb,0x53,0xf8,0xd9,
+  0xdd,0xe7,0x79,0xcb,0x0c,0xbf,0x6c,0x04,0x6f,0xf2,0x2a,0x32,0xa7,0xaf,0xf9,0xf9,
+  0x35,0xa6,0xb3,0x89,0xeb,0xd8,0x6e,0x91,0xfb,0x85,0x1e,0x62,0xd9,0xbf,0xa6,0x0f,
+  0x15,0xb2,0xf8,0xa1,0x4f,0x3b,0x16,0xdc,0xf4,0x2b,0x6e,0x3d,0x44,0xbf,0x46,0x0e,
+  0x76,0x05,0x9f,0xa2,0xd7,0x29,0x5f,0xae,0x5b,0x85,0xa5,0xc9,0xf7,0x67,0x8a,0xfb,
+  0x5b,0xf9,0x9d,0xae,0x4a,0xd2,0x9a,0x1f,0x2f,0xdb,0x5f,0xc1,0x2f,0x2f,0xe0,0xdc,
+  0xaf,0xd2,0xd0,0x0c,0xf5,0xcb,0x35,0x24,0x5d,0x38,0xf6,0xfa,0xee,0xf5,0xfc,0xb2,
+  0x02,0xce,0x6e,0x54,0xd7,0x52,0x8e,0xf5,0xcb,0x0a,0x58,0x92,0xcf,0x0d,0x3c,0x7f,
+  0xd0,0x3f,0xe8,0xea,0x11,0x8d,0xf5,0x4b,0x03,0x98,0x3c,0xc7,0xb1,0x89,0xe7,0x5f,
+  0xd2,0xe7,0x73,0xc4,0x7e,0x34,0xe6,0x05,0x83,0xfd,0xec,0xe3,0x61,0x49,0xaf,0xd1,
+  0x78,0x40,0x6c,0xb4,0x9f,0xef,0xdf,0x6d,0x4f,0xb2,0xa9,0xe7,0xc3,0xe2,0x8c,0x3c,
+  0x98,0x71,0xd4,0xde,0x82,0x9f,0x29,0xe1,0xf8,0xd6,0x1c,0xa3,0x8e,0xf7,0xf3,0x82,
+  0xec,0xd5,0xd6,0x09,0x5c,0x33,0xd1,0x04,0x3f,0x17,0x67,0xfe,0xea,0xd9,0x19,0x93,
+  0x4d,0xf0,0x73,0x7a,0x2d,0x4f,0x74,0xc2,0xd5,0xde,0x74,0x8a,0xdf,0x3a,0x2a,0xde,
+  0x4d,0xd7,0xf6,0x86,0xcd,0x2b,0x72,0x13,0xfd,0xd6,0x99,0x21,0x89,0x30,0x1d,0x78,
+  0x00,0x7f,0x96,0x5f,0x6d,0xea,0xb2,0x29,0xbf,0x23,0x81,0x1f,0xfc,0xe0,0x07,0x3f,
+  0xf8,0x6d,0xd3,0x0f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x5c,0x8e,0xdf,
+  0xe3,0xb7,0xe4,0x39,0x76,0x96,0x00,0x00,
diff --git a/u-boot/board/esd/voh405/logo_640_480_24bpp.c b/u-boot/board/esd/voh405/logo_640_480_24bpp.c
new file mode 100644
index 0000000..7d3c7a3
--- /dev/null
+++ b/u-boot/board/esd/voh405/logo_640_480_24bpp.c
@@ -0,0 +1,1722 @@
+  0x1f,0x8b,0x08,0x08,0x70,0xff,0xbe,0x40,0x00,0x03,0x65,0x73,0x64,0x5f,0x77,0x65,
+  0x6c,0x6c,0x65,0x5f,0x36,0x34,0x30,0x78,0x34,0x38,0x30,0x5f,0x32,0x34,0x2d,0x62,
+  0x69,0x74,0x2e,0x62,0x6d,0x70,0x00,0xec,0x9d,0x77,0x7c,0x54,0xd7,0x95,0xc7,0xc9,
+  0xfe,0xbb,0x9b,0xac,0x77,0xd7,0xd9,0xc4,0x59,0x27,0xbb,0x9b,0xac,0x5b,0x12,0x3b,
+  0xce,0x92,0xf5,0xc6,0x66,0x1d,0x17,0xec,0x34,0x57,0x6c,0xe3,0xde,0x6d,0xec,0x38,
+  0x2e,0xb8,0x42,0x5c,0xc0,0x54,0xd3,0x8b,0x11,0x45,0x14,0x61,0x04,0x98,0x66,0x84,
+  0x31,0x18,0x30,0x1d,0x51,0x0c,0x02,0x09,0x19,0x84,0x85,0x10,0x48,0x02,0x09,0x90,
+  0x84,0xba,0x46,0x1a,0x95,0xd1,0x9c,0xbb,0xf7,0xbc,0x69,0xef,0xcd,0xbc,0x72,0xef,
+  0x9b,0xf7,0x66,0x46,0xd2,0xf9,0x7d,0x7e,0xf0,0x11,0x42,0x7a,0xa3,0x11,0xe8,0x7d,
+  0xe7,0x94,0x7b,0xce,0xad,0x77,0x5d,0x77,0xd1,0xf7,0xfa,0xa0,0xae,0xe3,0xbf,0xae,
+  0xe4,0xbf,0x46,0xfc,0x5d,0x9f,0x3e,0xa7,0xbf,0xd3,0xa7,0xcf,0x77,0xfa,0xfc,0x50,
+  0x79,0x7f,0x1f,0xfe,0xf7,0x3f,0xbb,0xa6,0x8f,0xf2,0x2b,0x24,0x46,0x22,0x91,0x92,
+  0x28,0x00,0xb4,0xdf,0xcf,0xfc,0x5d,0xac,0xb3,0x3d,0xe8,0x76,0x0f,0xf3,0x36,0xb1,
+  0x96,0x3a,0xe6,0xa9,0x61,0x4d,0x95,0xac,0xe1,0x2c,0xab,0x2b,0x0f,0xba,0xb6,0x8c,
+  0x5d,0x38,0x05,0xd5,0xc5,0x50,0x76,0x10,0xca,0x72,0xa0,0x68,0x27,0x1c,0xdb,0x04,
+  0x05,0x1b,0x61,0xef,0x42,0xd8,0x9b,0x01,0x5b,0xa7,0xc2,0x97,0xa3,0x60,0xfd,0x08,
+  0x58,0xf6,0x57,0x58,0xfa,0x17,0x58,0xfa,0x42,0xd0,0xe9,0xf7,0xc3,0x8c,0x3b,0xd0,
+  0xe3,0x6f,0x80,0xd1,0xbf,0x82,0x51,0xd7,0xc0,0x48,0xee,0x5f,0x06,0x3d,0xfc,0x2a,
+  0x78,0xfd,0xa2,0xa0,0x07,0x5f,0x04,0xaf,0x7d,0x4f,0xf1,0x77,0xd1,0xaf,0xfe,0x43,
+  0xc4,0xaf,0xfc,0x3d,0xfe,0xfe,0xc6,0xc5,0x30,0xf4,0xc7,0xf0,0xde,0x4f,0x61,0xd8,
+  0x95,0x78,0x91,0xc9,0xb7,0x40,0xfa,0x7d,0x30,0x77,0x20,0xac,0x78,0x0d,0xd6,0x7d,
+  0x08,0x9b,0x27,0xa2,0xb7,0x7f,0x0c,0x47,0xd6,0xc1,0xc9,0xbd,0x21,0xef,0x81,0xca,
+  0xc2,0xe0,0x33,0x65,0x51,0x26,0x91,0x48,0x24,0x12,0xc9,0x1d,0xf9,0x14,0x9e,0x72,
+  0x98,0x72,0x8c,0xd6,0x94,0xb2,0xaa,0x22,0x56,0x9e,0x8f,0x3e,0x93,0xc7,0x4e,0xed,
+  0x83,0xe3,0xdb,0xe1,0xd8,0x57,0x90,0xb7,0x1a,0x72,0x57,0xc1,0xae,0x39,0x41,0x6f,
+  0x1c,0x0b,0x5f,0x0c,0x47,0xa2,0x2d,0x79,0x01,0x16,0x3c,0x0a,0x33,0xef,0x86,0x69,
+  0xb7,0x2b,0xbe,0x0d,0xc6,0x5d,0x0f,0xa3,0xae,0x45,0xf0,0x0d,0xbf,0x02,0x86,0x5d,
+  0x8e,0x1c,0x1c,0x72,0x69,0xc8,0xff,0x06,0x43,0x7e,0x14,0xf4,0x3b,0x8a,0xdf,0xfe,
+  0xa1,0xe2,0x1f,0xa0,0xdf,0xfa,0xd7,0xa0,0xdf,0xfc,0x3e,0xbc,0x79,0x31,0xbc,0xf1,
+  0x2f,0xf0,0xfa,0x3f,0x87,0x7c,0x91,0x96,0xbf,0xff,0xa8,0xe2,0xef,0x77,0xe1,0xed,
+  0x4b,0x60,0xe4,0xd5,0x30,0xe5,0x56,0x98,0x73,0x1f,0x2c,0x1e,0x04,0x1b,0x3f,0x82,
+  0x43,0x2b,0xe0,0x44,0x36,0x9c,0x3b,0x06,0x9e,0x1a,0xe8,0x68,0x55,0xc0,0xea,0x8f,
+  0x35,0xf8,0xbb,0x2c,0xcd,0xd4,0xc6,0xcf,0x0a,0x30,0x9a,0x44,0x22,0x91,0x48,0x24,
+  0x33,0x41,0x57,0x27,0x74,0x78,0xa1,0xad,0x19,0x5a,0xeb,0xa1,0xbe,0x1c,0xce,0x17,
+  0x42,0xc9,0x7e,0x28,0xdc,0x06,0x87,0xd7,0xc0,0xfe,0x25,0x90,0x9d,0x0e,0xd9,0x73,
+  0x60,0xcb,0x64,0x8c,0x49,0xd7,0xbc,0x0b,0xcb,0x5f,0x85,0xcc,0xe7,0x20,0xe3,0x71,
+  0x98,0x75,0x0f,0x3a,0xed,0x0e,0x98,0x7c,0x33,0x4c,0xb8,0x01,0xc6,0xf6,0xc5,0x08,
+  0xf4,0x83,0xcb,0x55,0xfe,0xaf,0x88,0xdf,0x57,0xcc,0x39,0x8b,0xfe,0x4f,0x78,0xf7,
+  0x3f,0x22,0xfe,0xdb,0x4f,0xd0,0x11,0xfe,0x5e,0x1a,0xe1,0xef,0x10,0x63,0xfe,0x22,
+  0x82,0x2f,0x46,0x1b,0xf1,0x97,0xa3,0x99,0x7f,0x3d,0x1f,0xff,0x11,0x83,0xe8,0x75,
+  0x23,0x60,0xf7,0x5c,0x76,0x6c,0x13,0x3b,0x77,0x8c,0x35,0x57,0xb3,0xae,0x4e,0xdb,
+  0xa8,0x8d,0x30,0x97,0x5f,0x24,0xe2,0x0e,0xad,0x95,0x77,0xfa,0x7d,0x8a,0xbb,0x80,
+  0x88,0x4c,0x22,0x91,0x48,0xbd,0x55,0x10,0x10,0x67,0x41,0xc3,0x39,0xa8,0x2c,0x84,
+  0x8a,0xa3,0x70,0x62,0x17,0xe4,0x7f,0x0e,0xfb,0x16,0xc2,0xe6,0xc9,0x88,0xa7,0xd5,
+  0x6f,0xc3,0xa7,0x4a,0xb2,0x77,0xd1,0x33,0x30,0xff,0x61,0x98,0x7d,0x2f,0x4c,0xff,
+  0x23,0x82,0x95,0x07,0xaa,0x63,0xfa,0xc2,0x98,0x5f,0xc3,0xe8,0x6b,0x61,0x54,0x28,
+  0xe5,0x3b,0xe2,0x97,0x8a,0x7f,0x81,0xfe,0xf0,0xe7,0x21,0x5f,0x05,0xc3,0xaf,0x84,
+  0x61,0x57,0x08,0xf1,0x57,0x8d,0x60,0x4b,0xfe,0xbe,0x73,0x89,0x41,0x08,0x1c,0xc5,
+  0xdf,0x7f,0x42,0xf2,0xf2,0x4b,0xa5,0x3f,0x80,0xe1,0x6d,0xce,0x52,0x1e,0x98,0xb3,
+  0xca,0xe3,0x98,0xfd,0xee,0x6c,0x0b,0x45,0xa6,0xee,0x31,0x37,0xda,0xe0,0x6b,0x0f,
+  0x99,0xbf,0xdd,0xc9,0xcd,0x71,0x4c,0x2c,0x26,0x91,0x48,0xa4,0x9e,0xa2,0x50,0xd6,
+  0x34,0x48,0x87,0x0e,0xc6,0x6f,0xf8,0xed,0x1e,0xa8,0x3f,0x8b,0xd5,0xd5,0xf2,0xc3,
+  0x70,0x74,0x03,0xec,0x5d,0x00,0xeb,0x47,0x21,0x5e,0xd3,0x07,0xc2,0xcc,0xbb,0x20,
+  0xed,0xcf,0x30,0xe3,0x4f,0x30,0xed,0xf7,0x30,0xb5,0x3f,0x4c,0xfa,0x1d,0x4c,0xe8,
+  0x07,0xe3,0x7f,0x0b,0xe3,0xae,0x83,0xb1,0xbf,0x09,0x7a,0xcc,0x7f,0xa3,0x47,0x5d,
+  0xab,0xf2,0x35,0x11,0x8f,0xd4,0x22,0x38,0xc2,0xdf,0x9f,0x23,0x7f,0xb9,0x75,0x43,
+  0x60,0x13,0xfe,0xea,0x20,0xf8,0x47,0x42,0x29,0x68,0xf4,0xf7,0xe1,0xad,0x1f,0xc0,
+  0xd0,0x4b,0x61,0xf2,0x4d,0x18,0x98,0xe7,0xad,0x86,0x9a,0x52,0xe6,0xa9,0x65,0x1d,
+  0xad,0x4a,0x90,0xab,0x9f,0x52,0x96,0xc7,0xae,0x05,0x6a,0x35,0xd8,0xed,0x6c,0xd7,
+  0xb3,0x37,0xe4,0x36,0xf0,0x71,0x63,0x8c,0x8c,0x57,0x26,0x10,0x93,0x48,0x24,0x52,
+  0xb7,0x10,0x67,0x07,0x0f,0xe5,0xbc,0x8d,0xac,0xa9,0x8a,0xd5,0x95,0x43,0x65,0x11,
+  0x9c,0xce,0x85,0x63,0x9b,0x21,0xff,0x0b,0xd8,0x33,0x1f,0x83,0xbe,0x55,0x6f,0xc2,
+  0xc2,0x27,0xb0,0x43,0x69,0x8a,0xc2,0xd6,0x89,0xff,0x87,0x9e,0xa0,0x78,0xfc,0x0d,
+  0x8a,0x7f,0x1b,0xf4,0x38,0xc5,0x1f,0x5d,0xa7,0xf8,0x7f,0xd0,0x61,0xfe,0xea,0x20,
+  0xd8,0x98,0xbf,0x6a,0x04,0x9b,0xf0,0xf7,0x03,0x29,0xfe,0x5e,0x6a,0xc1,0x5f,0xfe,
+  0x36,0x0f,0xb7,0xf9,0x13,0xe4,0xa1,0x7a,0x76,0x3a,0x54,0x1e,0x87,0x2e,0x5f,0x30,
+  0xae,0x8c,0x97,0xb9,0xbe,0x80,0x1d,0x65,0xae,0x99,0xf1,0xf5,0x52,0x97,0x8f,0x11,
+  0x8b,0x49,0x24,0x12,0x29,0x75,0xe4,0xeb,0x64,0xed,0xcd,0xac,0xb1,0x92,0x55,0x9f,
+  0xc4,0x36,0xa7,0x13,0xd9,0xd8,0x8e,0xfb,0x75,0x26,0x96,0x62,0xb3,0x86,0x60,0x11,
+  0x36,0xfd,0x7e,0xec,0x65,0x9a,0x72,0x2b,0x7a,0xf2,0xcd,0x8a,0x6f,0x42,0x73,0x30,
+  0x05,0x6c,0xc2,0x5f,0x0d,0x82,0x2d,0xf9,0x7b,0xad,0x10,0x7f,0x75,0x10,0xec,0x54,
+  0x0a,0x3a,0x80,0xe0,0x4b,0xf0,0x0a,0xd3,0x7f,0x8f,0xa1,0x6e,0xce,0x32,0xb8,0x50,
+  0x02,0x1c,0x7f,0x0e,0x60,0xd7,0x27,0x81,0x5d,0x5f,0xc4,0x2a,0xd4,0xb6,0xa9,0x2c,
+  0x84,0xdd,0xa0,0x3b,0x42,0xe6,0x20,0xe6,0xaf,0xac,0xf8,0xf5,0xf9,0xd7,0xc0,0xbf,
+  0x6c,0x12,0x89,0x44,0x22,0x25,0x44,0xc1,0xe2,0x6c,0x4b,0x2d,0x54,0x15,0x41,0xf1,
+  0x6e,0x3c,0x89,0x73,0x68,0x25,0x64,0xcf,0x83,0xaf,0x26,0xc0,0x17,0xc3,0x60,0xe5,
+  0xeb,0xf0,0xc9,0x53,0x30,0x67,0x00,0xd6,0x64,0x31,0x6f,0x7c,0x1b,0xa6,0x8e,0xa7,
+  0xde,0x1a,0xb1,0x11,0x7f,0x27,0xdd,0xa8,0x42,0x70,0x3f,0x85,0xbf,0xd7,0x8b,0x85,
+  0xc0,0x7d,0x91,0xbf,0xa3,0x7f,0x6d,0x1c,0x02,0x5f,0x2d,0x96,0x82,0xbe,0x4c,0x2c,
+  0x04,0xfe,0x77,0xe4,0xef,0xd0,0x1f,0x1b,0x76,0x41,0xf3,0xdf,0xf9,0xb3,0x5b,0xf3,
+  0x37,0x38,0xb0,0x14,0x5f,0x8a,0xb4,0x7b,0x9c,0x2b,0xe3,0x5a,0x54,0x72,0x55,0x65,
+  0x5c,0xc5,0xf6,0x98,0xdb,0x61,0xe0,0xf6,0x56,0x95,0x5b,0xd0,0x1d,0xad,0x4a,0x8e,
+  0xba,0x83,0x22,0x62,0x12,0x89,0x44,0x72,0x49,0x78,0x5b,0xae,0xaf,0x80,0x33,0xb9,
+  0x70,0x64,0x3d,0xec,0x9a,0x8d,0xc7,0x4e,0x57,0xbd,0x09,0x4b,0x5f,0x82,0x8c,0x27,
+  0x60,0xde,0x43,0x48,0xdb,0x99,0x77,0x62,0xfb,0x6e,0xc0,0x3c,0xe8,0xe3,0x9e,0xf6,
+  0xfb,0x10,0x7f,0x6f,0x33,0xe0,0xef,0xcd,0x5a,0xfe,0xa6,0x5e,0x0a,0xfa,0xfd,0x9f,
+  0xc9,0xa5,0xa0,0x87,0x5d,0x81,0x2d,0x61,0x87,0x56,0x61,0xeb,0x72,0x4b,0x5d,0x30,
+  0x3c,0x8c,0x17,0xbb,0x02,0x29,0x65,0x1d,0xe0,0x46,0x61,0x57,0x26,0xbc,0x35,0xc4,
+  0x6e,0x8b,0xca,0x1e,0x95,0x03,0x20,0xf6,0x62,0xd7,0x16,0x51,0x98,0x44,0x22,0x91,
+  0x6c,0x88,0xdf,0xf6,0x7d,0xed,0xac,0xa3,0x05,0x8f,0xf6,0x34,0x56,0x42,0xc5,0x11,
+  0xa4,0xed,0xee,0xb9,0x18,0xca,0x2d,0x7e,0x01,0x32,0x1e,0x43,0xd4,0xa6,0xdf,0x07,
+  0xb3,0xef,0x51,0x3a,0xa3,0xee,0x44,0xcf,0xf8,0xb3,0xe2,0x3f,0xa1,0xc3,0xfc,0xd5,
+  0x41,0xb0,0x96,0xbf,0x3d,0x29,0x05,0x3d,0xf4,0x27,0xf8,0x89,0x93,0x6e,0xc2,0x41,
+  0x1c,0x35,0x25,0xac,0xad,0x59,0x7d,0x62,0x28,0xe1,0xad,0x53,0xa2,0x95,0x5c,0x33,
+  0xe6,0x6a,0x38,0x6b,0xc4,0xdc,0x90,0xbd,0xcd,0x2a,0x7b,0xa0,0xcd,0x83,0xd9,0xe9,
+  0x40,0xff,0x36,0x89,0x44,0x22,0x91,0x74,0xc5,0x43,0x15,0x4e,0x8a,0xf6,0x16,0x3c,
+  0xf3,0x52,0x77,0x1a,0x67,0x3b,0x7c,0xbb,0x05,0xb2,0xe7,0xc2,0xda,0xf7,0x20,0xf3,
+  0x79,0x6c,0x16,0x9a,0xc3,0x51,0x3b,0x00,0x4f,0xf7,0x70,0xe0,0x22,0x73,0xef,0x56,
+  0x7c,0x67,0xc4,0xc8,0xdf,0x3b,0xc4,0xf8,0x7b,0x9b,0x10,0x7f,0x03,0x08,0x0e,0xf2,
+  0xb7,0x9f,0x31,0x7f,0x63,0x10,0x3c,0xa6,0xaf,0x58,0x17,0xb4,0x25,0x7f,0x65,0xba,
+  0xa0,0x79,0x74,0xcc,0xb1,0xbb,0xe8,0x59,0xc8,0xcb,0x02,0x6f,0x63,0x52,0xcb,0xb8,
+  0x76,0x2b,0xb9,0x3c,0x6e,0x0d,0xdb,0x12,0xbb,0x6d,0x2a,0x47,0x98,0xdb,0xa4,0x75,
+  0x63,0xd0,0x1d,0x2d,0xca,0xb1,0x62,0x3f,0x45,0xc4,0x24,0x12,0x89,0x84,0xe2,0x74,
+  0xe0,0x01,0x5a,0x7d,0x05,0xab,0xc8,0x87,0x13,0x3b,0xe1,0x70,0x16,0x4e,0x50,0xdc,
+  0x3c,0x09,0x4f,0xd4,0x66,0x3c,0x8e,0x67,0x51,0xd3,0xef,0x47,0x73,0xf2,0x86,0x1d,
+  0xe6,0xef,0x2c,0x3d,0xfe,0x1a,0x85,0xc0,0xd3,0xff,0x60,0x95,0x82,0xbe,0xc5,0x90,
+  0xbf,0x9a,0x10,0x58,0xb0,0x04,0xfc,0x9b,0x98,0x12,0xf0,0xaf,0xc4,0x4e,0x21,0x5d,
+  0x65,0xc5,0x5f,0xbd,0x14,0x34,0x27,0x2f,0x7f,0xfa,0x1b,0x46,0x43,0xe9,0x01,0xce,
+  0xbe,0xee,0xd4,0x3a,0x25,0xc4,0x5c,0x8f,0x0c,0x73,0x1b,0x75,0xcd,0x5a,0xd1,0x4a,
+  0x38,0xdc,0x86,0x79,0x78,0x12,0x89,0x44,0xea,0x7d,0xc2,0x7b,0x75,0xdd,0x19,0x1c,
+  0x12,0x75,0x64,0x3d,0x8e,0xb0,0xd8,0x3a,0x0d,0x47,0x58,0xac,0x18,0x1c,0x1c,0x5e,
+  0x31,0xef,0x41,0xf4,0xdc,0x07,0x71,0x9e,0x30,0xf2,0xf7,0x01,0x3d,0xfe,0xaa,0x43,
+  0xe0,0xbb,0x84,0xf8,0xab,0x09,0x81,0x6f,0x77,0x34,0x05,0xfd,0xbf,0xce,0xa7,0xa0,
+  0xc5,0x07,0x71,0xf0,0x3f,0xf2,0xef,0x4f,0x76,0x3a,0x94,0xe7,0x23,0xbf,0x12,0x54,
+  0xc9,0x4d,0x4c,0x19,0x57,0x8d,0xdd,0xe6,0xa0,0x35,0xe9,0x65,0x7d,0xe6,0x06,0x50,
+  0x6b,0x66,0xfe,0x92,0x8f,0x7f,0xaf,0x02,0xa7,0xae,0x48,0x24,0x12,0xa9,0x47,0x0b,
+  0x6f,0xe0,0x9c,0xb9,0x3c,0xc2,0xe5,0xe1,0xed,0x97,0xa3,0xe0,0xb3,0xb7,0x70,0xa2,
+  0x45,0x60,0x12,0xe3,0xfc,0x47,0x61,0xde,0xc3,0x8a,0x1f,0x8c,0x78,0xae,0xe2,0x30,
+  0x7f,0xd5,0x08,0x8e,0xe6,0xaf,0x69,0x08,0xec,0x54,0x0a,0x5a,0x83,0x60,0xb1,0x14,
+  0x74,0x00,0xc1,0x2e,0x0e,0xe2,0xf8,0x29,0x8e,0xaf,0xcc,0xcb,0x82,0x9a,0x12,0xc4,
+  0x99,0x83,0xb3,0xa7,0x5c,0x2a,0xe3,0x1a,0x56,0x72,0x0d,0x98,0xeb,0x6d,0xd6,0xb3,
+  0x59,0x78,0x2b,0x68,0x68,0xa9,0x47,0x23,0x88,0x3d,0xcc,0x4f,0x3d,0x5a,0x24,0x12,
+  0xa9,0x67,0x08,0x94,0x25,0x3e,0x6d,0x18,0x62,0xb4,0xd4,0xc2,0xd9,0xa3,0xf0,0xcd,
+  0x17,0x78,0xe4,0x76,0xc5,0x6b,0x90,0xf9,0x2c,0x2c,0x7a,0x1a,0x32,0x9e,0x84,0x05,
+  0x8f,0xe3,0x42,0x81,0xb0,0xe7,0x3f,0x1a,0x42,0xb0,0x18,0x7f,0xd5,0x29,0x68,0x4b,
+  0xfe,0x6a,0x52,0xd0,0x82,0x5d,0xd0,0x8e,0xf2,0x57,0xb0,0x0b,0x5a,0x90,0xbf,0xe8,
+  0xcb,0x31,0xad,0x3d,0xe7,0x7e,0xcc,0x1e,0x70,0xf4,0x28,0x93,0xa0,0xe2,0x6f,0xa0,
+  0x72,0xb1,0x7b,0xca,0x35,0xec,0x4a,0x31,0x37,0x82,0x5d,0xad,0x99,0xa7,0x0e,0xaf,
+  0xdf,0x45,0x14,0x26,0x91,0x48,0xdd,0x53,0xfe,0x40,0x19,0xb7,0x1c,0x81,0x5b,0xb4,
+  0x03,0x0e,0x2e,0x87,0xaf,0x26,0xc2,0xb2,0x97,0x11,0xb8,0x9f,0x28,0x5e,0xf8,0xa4,
+  0xe2,0x27,0xd0,0xc8,0xdf,0xc7,0xf4,0xf8,0x1b,0x83,0xe0,0xf4,0x81,0xc6,0xfc,0x35,
+  0x40,0xb0,0x65,0x0a,0x3a,0xc8,0x5f,0xab,0x14,0xb4,0xe0,0x29,0x24,0xf7,0xba,0xa0,
+  0x75,0x52,0xd0,0x97,0x61,0xf5,0x79,0xf1,0x20,0x7c,0x49,0xd3,0xae,0x4e,0x35,0xc7,
+  0x5f,0xc6,0x75,0xa4,0x92,0xdb,0x2a,0x51,0xc9,0x6d,0xb3,0x59,0xc9,0x15,0xe0,0x6c,
+  0x83,0xda,0x2a,0xd4,0xd6,0x85,0x8d,0x33,0x36,0xb5,0xc6,0xf7,0xb7,0x7b,0x18,0x9d,
+  0x57,0x22,0x91,0x48,0xdd,0x45,0xfc,0x96,0xd5,0x70,0x8e,0x95,0x1f,0xc6,0x91,0x17,
+  0xfb,0x16,0xc2,0x86,0x31,0x4a,0x9c,0xfb,0x1c,0x56,0x72,0x39,0x79,0x03,0xd6,0xe7,
+  0xef,0xe3,0x31,0xfc,0x7d,0xc4,0x22,0x04,0xd6,0xf0,0xd7,0xb8,0x0b,0x3a,0x4d,0xaa,
+  0x0b,0xba,0xbf,0x58,0x09,0xf8,0x46,0x89,0x2e,0x68,0x0d,0x7f,0xad,0xba,0xa0,0x47,
+  0x5c,0x2d,0xd6,0x05,0x7d,0x19,0x5e,0x79,0xf9,0x6b,0xb8,0xf4,0xa1,0xa5,0xd6,0xce,
+  0xb0,0x47,0x7d,0xe6,0x4a,0x56,0x72,0xcd,0xbb,0xa7,0x44,0x4e,0x09,0xe9,0x00,0xd7,
+  0xac,0x92,0x2b,0x13,0xe7,0xc6,0x02,0xd7,0x82,0xb9,0x3a,0xe6,0x9f,0xd2,0xde,0xc2,
+  0xba,0xa8,0x3b,0x8b,0x44,0x22,0xa5,0xa2,0x00,0xfc,0x78,0x43,0xe3,0xcc,0x3d,0x9c,
+  0x05,0x3b,0xd2,0x60,0xd3,0x78,0x3c,0x8d,0xbb,0xf4,0x45,0x58,0xfc,0x3c,0x2c,0x7e,
+  0x0e,0xbd,0xe8,0x59,0xc5,0x4f,0x6b,0x11,0xfc,0x94,0x21,0x7f,0x35,0x21,0xf0,0x43,
+  0x32,0x29,0xe8,0x7b,0x9d,0x4f,0x41,0x4f,0x71,0xbb,0x0b,0x5a,0x7e,0x10,0xc7,0x87,
+  0xbf,0xc0,0x89,0x91,0xdf,0x6e,0x81,0xc6,0xf3,0x76,0x57,0x08,0x19,0xc5,0xb9,0x56,
+  0xd8,0x15,0x1f,0x3c,0x25,0xd2,0x3a,0xd5,0xa6,0x0b,0x5c,0x0d,0x76,0x25,0xf3,0xc9,
+  0x0d,0x2a,0x47,0xf2,0xc9,0x2a,0x5b,0x32,0xb7,0x46,0xc7,0x9c,0xe3,0xfc,0x79,0xd1,
+  0x79,0x61,0x12,0x89,0x94,0x1a,0x42,0xec,0x36,0x55,0x42,0x71,0x36,0xec,0x4a,0xc7,
+  0xa1,0x8e,0xab,0xdf,0x86,0xe5,0xaf,0xe0,0x6a,0xf8,0xb0,0x91,0xbf,0xcf,0x1b,0xf3,
+  0x37,0x36,0x04,0xd6,0xe5,0xaf,0x78,0x08,0x1c,0x7f,0x0a,0x5a,0x97,0xbf,0xa9,0x94,
+  0x82,0xc6,0x31,0x1a,0x37,0xc3,0x37,0x6b,0x59,0x53,0x25,0xce,0x21,0x11,0xec,0x58,
+  0xee,0x6e,0x65,0x5c,0x9b,0xdd,0x53,0xd1,0x65,0x5c,0x81,0xf0,0xd6,0x1c,0xbb,0xdc,
+  0xcd,0x17,0x82,0xe6,0x6f,0xf3,0xcb,0xfa,0xda,0x92,0xfd,0x63,0x47,0x22,0x91,0x7a,
+  0x9f,0x00,0xf0,0x86,0xcf,0xef,0x8d,0xf5,0x67,0xe1,0xd4,0xd7,0xd8,0xb4,0x9c,0xf5,
+  0x0e,0xae,0x62,0x0f,0x6c,0xb9,0x45,0xbf,0x88,0xd6,0xe5,0x6f,0x2c,0x82,0x45,0x53,
+  0xd0,0x6e,0x74,0x41,0x3b,0x3a,0x88,0x63,0xa2,0x25,0x7f,0x63,0x07,0x71,0x58,0xad,
+  0x23,0xd4,0xe5,0xef,0xc8,0xab,0xf1,0x90,0xd4,0x8e,0x99,0x80,0xd3,0xab,0x88,0xb9,
+  0x09,0x61,0xae,0xca,0xd0,0x5c,0x1d,0x30,0x6b,0x69,0x60,0xd4,0x9a,0x45,0x22,0x91,
+  0x12,0x20,0xf0,0xb3,0xd6,0x7a,0xb8,0x70,0x0a,0x4a,0x0f,0x62,0x7b,0xed,0x8e,0x34,
+  0x58,0x3d,0x04,0xdb,0xa8,0x38,0x79,0x03,0x46,0xfe,0xbe,0x64,0xc0,0xdf,0x41,0x56,
+  0xfc,0x55,0xa5,0xa0,0x33,0xe2,0x4e,0x41,0xab,0x4b,0xc0,0xc1,0x41,0x1c,0xba,0x07,
+  0x81,0x63,0xf9,0x6b,0x3c,0x88,0x63,0x4a,0x9c,0x83,0x38,0xf4,0x0e,0x02,0x8f,0x89,
+  0xdd,0xc5,0xa0,0x3b,0x88,0x43,0xc5,0x5f,0xfe,0x58,0x59,0x43,0x71,0xd8,0x26,0xc6,
+  0xbc,0x82,0x95,0xdc,0x54,0x18,0x82,0x61,0x51,0xc6,0x75,0xa4,0x92,0xeb,0x00,0x73,
+  0xf5,0x80,0xab,0x66,0x2e,0xba,0x29,0xe4,0xc6,0x2a,0xd6,0x5c,0x83,0x7d,0x0e,0xfe,
+  0xae,0x64,0xff,0x70,0x92,0x48,0xa4,0x1e,0x28,0x6c,0xe6,0xf1,0xd4,0xe2,0x0d,0xbf,
+  0x60,0x13,0xec,0x55,0xda,0xa8,0x56,0xbe,0x01,0x2b,0x5e,0x45,0x2f,0x7b,0x25,0x02,
+  0xdf,0x00,0x7f,0x45,0x42,0x60,0x67,0x53,0xd0,0x96,0x25,0x60,0x1b,0x29,0xe8,0xe9,
+  0x62,0x29,0xe8,0x04,0xcf,0x82,0xe6,0x68,0xe6,0xdf,0xc0,0xfc,0xb5,0x08,0x20,0xdd,
+  0x32,0xae,0x8b,0x2b,0x84,0xac,0xc2,0x5b,0xfd,0x32,0xae,0x7e,0xc7,0xb2,0xfc,0xc9,
+  0xa0,0xe8,0x4a,0xae,0xb6,0x8c,0x6b,0xb7,0x92,0x2b,0x82,0xda,0x08,0x73,0xab,0x22,
+  0x6e,0x54,0xbb,0x12,0xcd,0xbf,0x24,0x1c,0x2c,0x46,0x81,0x30,0x89,0x44,0x72,0x40,
+  0xb8,0xb6,0xcf,0x53,0x03,0xa5,0x39,0xb8,0x0d,0x76,0xdb,0x74,0x58,0x3f,0x12,0xc7,
+  0x62,0xac,0x7c,0x1d,0x7b,0x98,0xd1,0x61,0xfe,0xbe,0x2c,0xcd,0xdf,0xcc,0x00,0x82,
+  0x2d,0xbb,0xa0,0x1f,0x8b,0x41,0xb0,0x6e,0x17,0xf4,0x40,0xbb,0x29,0x68,0xcb,0x2e,
+  0xe8,0xdb,0x25,0xba,0xa0,0x75,0xd6,0x11,0x3a,0x9a,0x82,0xe6,0x0f,0xb1,0x7b,0x3e,
+  0xbb,0x70,0x8a,0x19,0x02,0xd7,0x09,0xe6,0x6a,0x5a,0xa7,0xac,0xba,0xa7,0x5c,0x63,
+  0xae,0x16,0xb8,0xba,0xcc,0x75,0x33,0xbc,0x15,0x64,0x6e,0xd0,0xe7,0x03,0x66,0xcd,
+  0x55,0x8c,0x3f,0x5f,0xea,0xcb,0x22,0x91,0x48,0x76,0x84,0xc3,0x31,0xc0,0xd7,0x81,
+  0x77,0x95,0xa2,0x1d,0xb0,0x3b,0x1d,0xd6,0x8f,0x80,0xcf,0xdf,0x43,0xec,0xae,0x7a,
+  0x03,0xc9,0x1b,0x70,0x34,0x7f,0x4d,0x43,0x60,0xc1,0x12,0xf0,0x22,0xab,0x12,0x70,
+  0xb7,0x1c,0xc4,0xe1,0xd0,0x3a,0xc2,0x31,0x7d,0xb1,0x99,0xad,0xaa,0x08,0xd1,0x96,
+  0xba,0x65,0x5c,0x07,0x86,0x60,0x24,0xb8,0x8c,0x6b,0x88,0xdd,0xc6,0x2a,0x3d,0x9f,
+  0xd7,0x35,0x6b,0x3c,0xa7,0xf2,0x79,0xe0,0x97,0xed,0xea,0x48,0xf6,0x0f,0x32,0x89,
+  0x44,0xea,0x3e,0xe2,0x61,0x54,0x73,0x0d,0x9c,0x2f,0x84,0xbc,0x35,0xb8,0xdd,0x60,
+  0xcd,0x50,0xf8,0xec,0x6d,0xf4,0xaa,0x37,0x15,0xbf,0xa1,0xe1,0x6f,0x10,0xc1,0x62,
+  0xfc,0x55,0x23,0x38,0xc8,0xdf,0x64,0xa4,0xa0,0xa5,0xf8,0xeb,0x46,0x17,0xb4,0x3d,
+  0xfe,0x8e,0xed,0x8b,0xcf,0xeb,0x70,0x16,0x22,0x32,0x15,0x99,0xdb,0x8d,0x5b,0xa7,
+  0x9c,0x63,0xae,0x8e,0xb1,0x2f,0x8e,0x2a,0xc2,0x24,0x12,0xc9,0x44,0x7e,0x1f,0xce,
+  0xf6,0x39,0x57,0x80,0x85,0xdd,0x1d,0x33,0x61,0xcd,0x7b,0x78,0x6e,0x28,0xec,0x08,
+  0x82,0x75,0xf9,0x6b,0x80,0x60,0xc1,0x14,0xf4,0x62,0xc1,0x14,0xb4,0x7c,0x17,0xb4,
+  0x60,0x09,0x58,0x6e,0x1d,0xa1,0x60,0x0a,0xfa,0x77,0x62,0x25,0x60,0xb1,0x14,0xf4,
+  0xb4,0xfe,0xb0,0x71,0x2c,0x86,0xbd,0x29,0xd1,0x3d,0x25,0xba,0x42,0x48,0xa4,0x75,
+  0x4a,0x7c,0xf0,0x94,0x2b,0xd8,0x6d,0xd2,0x34,0x50,0x99,0xa4,0x94,0x65,0xb1,0x8b,
+  0xd3,0x66,0x42,0x06,0xfe,0x15,0x76,0xb6,0x27,0xfb,0x27,0x9c,0x44,0x22,0xa5,0x96,
+  0xb0,0xb0,0xdb,0x5a,0x8f,0x0b,0x71,0x8e,0x7e,0x89,0x47,0x87,0x36,0x8c,0xc6,0x80,
+  0x37,0x6b,0x28,0x36,0x33,0xaf,0x7e,0x47,0x8f,0xbf,0xb1,0x08,0x1e,0x6c,0x15,0x02,
+  0xbf,0x64,0x1a,0x02,0x5b,0x0e,0xe2,0x78,0xd2,0x38,0x05,0xfd,0x88,0xcc,0x20,0x8e,
+  0x01,0x2e,0x0f,0xe2,0x30,0x09,0x81,0xfb,0xc9,0x0c,0xe2,0xd0,0x76,0x41,0xf3,0x37,
+  0x32,0x9f,0xc1,0x7f,0x1d,0x6f,0x83,0x13,0xad,0x53,0x8e,0x0c,0xc1,0xb0,0x1d,0xde,
+  0xba,0x33,0x04,0xc3,0x76,0x19,0xb7,0xc9,0xa2,0x8c,0x2b,0xc4,0xd9,0x70,0x9c,0xdb,
+  0x70,0x56,0xe3,0xfa,0xb0,0x2b,0xd0,0x4d,0x55,0xd8,0x1a,0x4d,0x4d,0x59,0x24,0x12,
+  0x09,0x57,0xfb,0x79,0x31,0xc9,0x7c,0x78,0x0d,0xec,0x9c,0x09,0x1b,0x3f,0x82,0xb5,
+  0x1f,0xe0,0x70,0x2a,0xf4,0x50,0x34,0xf2,0x77,0x88,0x18,0x7f,0x55,0x21,0xb0,0x54,
+  0x0a,0x7a,0xc9,0x20,0x89,0x14,0x74,0x86,0xa3,0x29,0xe8,0x59,0xf7,0xc8,0xa4,0xa0,
+  0xad,0xd6,0x01,0xdb,0x1e,0xc4,0x61,0x99,0x82,0x1e,0x77,0x3d,0x6c,0x9d,0x0a,0xd5,
+  0xc5,0xd0,0xd1,0xe2,0x6e,0xc7,0xb2,0xcc,0xda,0xbe,0xf8,0x99,0xab,0xc5,0x6e,0x62,
+  0xbb,0xa7,0xa2,0xb3,0xca,0x71,0x31,0x57,0x83,0xdd,0xfa,0x28,0x57,0x84,0x5c,0x1e,
+  0x34,0xff,0x18,0xfe,0xdc,0xa9,0x29,0x8b,0x44,0xea,0x9d,0xf2,0xfb,0xf0,0x4e,0x5b,
+  0x75,0x02,0x72,0x57,0xc2,0xe6,0xc9,0xf0,0xe5,0x48,0x9c,0x4f,0xf5,0xf9,0x7b,0x41,
+  0x9b,0xf0,0x37,0x16,0xc1,0xae,0xa4,0xa0,0x5d,0x18,0xc4,0x21,0x95,0x82,0x76,0x76,
+  0x10,0x87,0xd4,0x29,0xa4,0xa8,0x14,0x34,0x7f,0x7f,0xc6,0xa3,0x38,0xcf,0x84,0x23,
+  0x4f,0xa2,0x63,0x59,0x60,0xae,0x72,0x92,0x5a,0xa7,0x9c,0xa9,0xe4,0x3a,0xd0,0x3a,
+  0xa5,0x5f,0xc9,0x95,0x63,0x6e,0x34,0x6a,0xc3,0x2e,0xb7,0x76,0x53,0x25,0x6e,0x50,
+  0x22,0x91,0x48,0xbd,0x44,0xfc,0x25,0x37,0xbf,0x8b,0xd6,0x9e,0xc6,0x4e,0xe6,0xed,
+  0x69,0xf0,0xc5,0x70,0x8c,0x76,0xd1,0xef,0xa3,0xc3,0xfc,0x55,0x23,0x38,0x6b,0x88,
+  0x44,0x0a,0x7a,0x85,0x65,0x0a,0xfa,0xaf,0x76,0xf9,0x6b,0x35,0x0b,0x7a,0x9e,0x4c,
+  0x0a,0xda,0x64,0x17,0x43,0x82,0xd6,0x01,0x8b,0xa5,0xa0,0xa7,0xf6,0xc7,0x8c,0x44,
+  0x53,0xb5,0x29,0x76,0x2d,0xcb,0xb8,0x06,0x2b,0x84,0xac,0xe6,0x2a,0x77,0x97,0x32,
+  0xae,0x06,0xbb,0xfa,0x65,0x5c,0xeb,0x4a,0xae,0x5c,0x19,0x57,0x27,0xb6,0xd5,0x46,
+  0xb8,0x02,0x66,0x75,0x67,0x80,0x5f,0xaa,0xd3,0x4b,0xb9,0x68,0x12,0xa9,0x87,0x8b,
+  0xbf,0xd2,0xe6,0x3f,0xf5,0xa5,0x39,0xb8,0xe6,0x6f,0xf3,0x04,0x58,0x37,0x1c,0xe1,
+  0x8b,0xfc,0x1d,0x66,0xc1,0x5f,0x3b,0x29,0x68,0x85,0xbf,0xcb,0x5f,0x31,0x3e,0x08,
+  0xfc,0x62,0x4c,0x09,0xd8,0x78,0x10,0x96,0x26,0x04,0xb6,0x1c,0x84,0x25,0xbf,0x8e,
+  0xd0,0x6c,0x10,0x56,0x6c,0x09,0xd8,0x2a,0x05,0x2d,0x3a,0x08,0x2b,0xb6,0x0b,0x3a,
+  0x66,0x10,0x16,0x7f,0x2d,0x71,0x70,0x05,0xe6,0x81,0xa9,0x75,0xca,0x0e,0x73,0x2b,
+  0x13,0xc2,0x5c,0x09,0xe0,0x06,0x98,0x1b,0x6d,0x7e,0x91,0xb6,0x66,0x42,0x30,0x89,
+  0xd4,0x33,0xc5,0xef,0xc0,0x67,0x8f,0xc2,0xe1,0xcf,0x21,0x3b,0x1d,0x36,0x8c,0x45,
+  0xf2,0x86,0x1d,0x44,0xb0,0x5e,0x08,0x6c,0x9d,0x82,0x7e,0xcb,0xad,0x14,0xb4,0x8d,
+  0x41,0x1c,0xae,0xcc,0x82,0x76,0x74,0x10,0x87,0x68,0x0a,0x5a,0x41,0xf0,0xb8,0xeb,
+  0xf0,0x9b,0xcc,0x5f,0x2c,0x71,0x92,0xba,0x5f,0xc6,0x8d,0xa3,0x92,0xeb,0x68,0x19,
+  0x57,0xf6,0x70,0x90,0xc5,0x10,0x8c,0x38,0xb2,0xca,0xfa,0x95,0x5c,0x39,0xe6,0xea,
+  0xa0,0x96,0xbb,0xf6,0xb4,0x8e,0xf9,0x07,0xb7,0x52,0x39,0x98,0x44,0xea,0x41,0x02,
+  0x80,0xe6,0x2a,0xcc,0x33,0xef,0x59,0x00,0x5b,0xa7,0xc0,0xba,0x91,0xb0,0x6e,0x44,
+  0xc8,0x02,0xfc,0x75,0x24,0x04,0xb6,0x4c,0x41,0x4b,0x75,0x41,0x8b,0x0e,0xe2,0x78,
+  0x58,0xac,0x0b,0xda,0xb5,0x75,0x84,0x71,0x0e,0xe2,0x18,0xdf,0x0f,0x76,0xcd,0xc1,
+  0xfb,0x3c,0x1d,0xc8,0x75,0xf9,0x40,0xae,0x40,0x25,0x37,0xbe,0xd8,0xd6,0x98,0xb9,
+  0x50,0x5b,0xa6,0x71,0xdd,0x69,0xe6,0xb9,0x00,0x7e,0x42,0x30,0x89,0xd4,0x9d,0xe5,
+  0xf7,0x61,0xc0,0x5b,0x59,0xc8,0x0e,0x7c,0x0a,0x1b,0xc7,0xe1,0x58,0xe6,0x2f,0x47,
+  0xa1,0x23,0xf0,0x1d,0x11,0x1d,0x02,0x27,0x87,0xbf,0x36,0x4e,0x21,0x3d,0x2d,0xcd,
+  0x5f,0x37,0x06,0x71,0x58,0x9f,0x42,0xba,0xd5,0x26,0x7f,0xb9,0x67,0xdc,0x01,0x05,
+  0x1b,0x30,0x51,0x4c,0xd8,0xed,0x0d,0xd8,0x0d,0xbb,0xa6,0x14,0xcd,0x1f,0xda,0x47,
+  0x63,0xb2,0x48,0xa4,0x6e,0x27,0x60,0xed,0x2d,0x58,0x4b,0x2a,0xf9,0x9a,0xf1,0x80,
+  0x77,0x23,0xc7,0x6e,0xc0,0xa3,0x22,0x36,0xe2,0xaf,0x61,0x0a,0xfa,0x5d,0x8b,0x14,
+  0xf4,0xaa,0xb7,0xc4,0x06,0x71,0xd8,0x98,0x05,0xfd,0x6c,0x92,0x07,0x71,0xa4,0x89,
+  0x0d,0xe2,0x98,0x2a,0x95,0x82,0xbe,0xd1,0x2c,0x05,0x3d,0xa1,0x1f,0x7e,0x7f,0xce,
+  0x16,0x08,0xb5,0x4e,0x39,0x5c,0xc9,0x6d,0x48,0x44,0x25,0x37,0xe5,0x5a,0xa7,0xec,
+  0x57,0x72,0x25,0x72,0xcb,0x46,0xcc,0x0d,0x00,0x37,0xc6,0xfc,0x47,0x98,0x75,0x7a,
+  0x93,0x7d,0x33,0x21,0x91,0x48,0xc2,0xf2,0x36,0xb0,0x8a,0x23,0x70,0x64,0x3d,0xdb,
+  0x35,0x07,0x36,0x8d,0xc3,0xf9,0x48,0x16,0xfc,0xfd,0x50,0x26,0x05,0x3d,0x54,0xa8,
+  0x0b,0x5a,0xc3,0x5f,0xab,0x2e,0x68,0xc3,0x75,0x84,0x71,0x74,0x41,0xcf,0x77,0xaf,
+  0x0b,0xda,0x8d,0x75,0xc0,0xda,0x41,0x1c,0x13,0x6e,0xc0,0x57,0x3b,0xd5,0x27,0xcd,
+  0xba,0xa7,0xa2,0xc3,0xdb,0x38,0xdb,0x95,0x1b,0x0d,0x76,0xf6,0x25,0x73,0x6d,0x9f,
+  0x48,0x25,0x57,0x22,0xc8,0xd5,0x67,0xae,0x74,0x25,0xd7,0x6d,0xe6,0x6a,0x5d,0x02,
+  0x75,0xe5,0xf8,0x5a,0x9a,0x44,0x22,0xa5,0xb2,0x00,0xf0,0x3e,0x59,0xb2,0x1f,0x5b,
+  0x9a,0xb7,0x7f,0x0c,0x9b,0xc6,0xa3,0x37,0x7e,0xa4,0x78,0x8c,0x92,0x79,0xe6,0x1e,
+  0xad,0xc7,0xdf,0xd8,0x10,0x78,0x58,0x04,0xc1,0x8e,0xa5,0xa0,0x15,0x04,0x2f,0x97,
+  0x5a,0x47,0x28,0xd8,0x05,0x6d,0x32,0x08,0x2b,0xce,0x41,0x1c,0x62,0x5d,0xd0,0xd6,
+  0x83,0x38,0x6e,0x91,0xe8,0xc2,0xe2,0xef,0xe1,0xff,0x70,0xfc,0xde,0x2b,0x31,0x78,
+  0xca,0x91,0x15,0x42,0xba,0x83,0xa7,0x2c,0xb1,0xeb,0xc4,0x2e,0x03,0xa9,0x15,0x42,
+  0xf6,0x5a,0xa7,0x0c,0xbb,0xa7,0xac,0xb1,0x9b,0x28,0xd4,0x86,0x7c,0xa1,0x44,0xe5,
+  0x53,0x68,0xfe,0x70,0x6d,0xcd,0xc9,0xbe,0xbf,0x90,0x48,0x24,0x5d,0x01,0xf0,0x3b,
+  0x5b,0xe1,0x16,0xd8,0x33,0x0f,0xc7,0x22,0x7d,0x35,0x1e,0x1d,0xc5,0x5f,0x67,0x52,
+  0xd0,0x56,0x5d,0xd0,0x96,0xfc,0x75,0x7d,0x1d,0xb0,0xdb,0x29,0x68,0xab,0x75,0xc0,
+  0x41,0x04,0xdb,0x5d,0x07,0xcc,0xff,0xb8,0x2f,0x03,0x31,0xd4,0x83,0xca,0xb8,0x29,
+  0x33,0x07,0x23,0xee,0xc3,0x41,0xee,0x62,0xf7,0x94,0x81,0x4f,0xa2,0x6b,0x4b,0xa1,
+  0x8d,0xa2,0x60,0x12,0x29,0x65,0x04,0x7e,0x4c,0x4c,0xd5,0x94,0xb1,0xc3,0xab,0x61,
+  0xcb,0x64,0xf8,0x6a,0xa2,0xe2,0xf1,0x11,0x47,0x10,0x6c,0xc9,0x5f,0xf9,0x2e,0x68,
+  0xcb,0x41,0x58,0x76,0xd6,0x11,0xca,0xa4,0xa0,0xdd,0x58,0x47,0x28,0x3a,0x08,0xcb,
+  0x9d,0x2e,0xe8,0xf4,0xfb,0xe0,0xf8,0x8e,0x9e,0xc1,0xdc,0xee,0xd8,0x3a,0x95,0x72,
+  0xcc,0x8d,0xb5,0x97,0x8e,0x06,0x93,0x48,0xc9,0x16,0x27,0xaf,0xa7,0x06,0x9b,0x73,
+  0xf2,0x3f,0xc7,0xad,0xf7,0x5b,0x26,0xa1,0x37,0x07,0xf8,0x3b,0x41,0x8f,0xbf,0x06,
+  0x29,0xe8,0xf5,0x26,0xa7,0x90,0x04,0x07,0x71,0x08,0xee,0x62,0x88,0x1d,0xc4,0x21,
+  0xd8,0x05,0x6d,0x95,0x82,0x56,0x97,0x80,0x83,0x83,0x38,0x74,0x0f,0x02,0xc7,0x96,
+  0x80,0x4d,0x06,0x71,0xdc,0x93,0x84,0x41,0x1c,0xfc,0x59,0x9c,0xdc,0xe3,0xc4,0x10,
+  0x0c,0xa3,0x4a,0x6e,0x62,0xf7,0x07,0x19,0x56,0x72,0xe3,0xde,0x1f,0x64,0x58,0xc9,
+  0x75,0xae,0x8c,0x6b,0xaf,0x5d,0xd9,0xb2,0x92,0x1b,0xb0,0x08,0x70,0xab,0x8b,0x03,
+  0x66,0x55,0x27,0xd4,0xe6,0x1f,0xc9,0xf8,0xff,0x01,0x46,0x08,0x26,0x91,0x92,0x20,
+  0x3c,0x95,0xcf,0x6f,0x74,0x65,0x07,0xe1,0xd0,0x4a,0xd8,0xf6,0x31,0x66,0x9b,0x79,
+  0xe4,0x8b,0x56,0x10,0x1c,0x15,0x02,0x27,0x25,0x05,0xfd,0x99,0x7b,0x5d,0xd0,0xcf,
+  0x25,0x39,0x05,0x3d,0x53,0x30,0x05,0x7d,0xbb,0x44,0x0a,0x7a,0xd2,0x8d,0xe8,0x15,
+  0x83,0xa1,0xf4,0x80,0x43,0x43,0x30,0x1c,0x5d,0x21,0x24,0x15,0xde,0xca,0xac,0x10,
+  0xb2,0x5f,0xc6,0x8d,0x5d,0x21,0xd4,0x0d,0xca,0xb8,0x25,0xe6,0xb1,0x2d,0xe3,0xa8,
+  0x55,0x5b,0x8b,0x5d,0x8d,0x39,0x82,0xdb,0x1a,0x29,0x0a,0x26,0x91,0x12,0x2c,0x8c,
+  0x5f,0x4e,0xee,0x85,0x9c,0xa5,0xb8,0x99,0x88,0x93,0x37,0x60,0x13,0xfe,0x06,0x11,
+  0x3c,0x4e,0xe1,0xaf,0x53,0x5d,0xd0,0xef,0xba,0x96,0x82,0x7e,0x49,0x6c,0x10,0xc7,
+  0x33,0xf2,0x29,0xe8,0x47,0x5c,0x18,0x84,0x65,0x99,0x82,0xee,0x2f,0x9a,0x82,0x5e,
+  0x3f,0x02,0x2a,0x0b,0x6d,0x30,0x97,0xb9,0x37,0x7b,0xaa,0xdb,0xad,0x10,0x4a,0x45,
+  0xec,0x5a,0xa7,0x94,0x85,0x80,0x1b,0x71,0x51,0xd0,0x18,0x05,0x37,0x25,0xfb,0x6e,
+  0x44,0x22,0xf5,0x0e,0x81,0x1f,0x6f,0xce,0xc5,0xbb,0x70,0x74,0xd5,0x8e,0x34,0xd8,
+  0x36,0x0d,0x1d,0xe6,0x6f,0x10,0xc1,0x26,0xfc,0x8d,0x0d,0x81,0xad,0x4a,0xc0,0x1a,
+  0x04,0x3b,0x3b,0x88,0x43,0x7e,0x1d,0xa1,0x1b,0x83,0x38,0x04,0x07,0x61,0xcd,0x96,
+  0x59,0x47,0x28,0x3a,0x88,0x43,0xb5,0x8e,0x90,0x33,0x7a,0xd7,0x2c,0xa4,0x52,0x7c,
+  0x65,0x5c,0x5a,0x21,0x94,0x6c,0xe6,0x4a,0x94,0x71,0xc5,0x50,0x1b,0xc3,0xdc,0x28,
+  0x57,0x17,0x03,0x21,0x98,0x44,0x72,0x55,0x5d,0x9d,0x58,0xe7,0x3d,0xb5,0x0f,0x76,
+  0xcf,0x83,0xed,0x33,0xb0,0xd4,0x8b,0xd6,0xe5,0xaf,0xdd,0x14,0xb4,0xb3,0xfc,0x4d,
+  0x95,0x2e,0x68,0x87,0x4e,0x21,0xd9,0xe8,0x82,0x16,0xe7,0x2f,0xbf,0xda,0x81,0x25,
+  0xe0,0x6d,0x48,0xb5,0xd6,0x29,0x62,0x6e,0x8a,0x32,0xb7,0xf2,0xb8,0xc6,0x55,0x45,
+  0x40,0xb5,0x60,0x12,0xc9,0x0d,0x61,0x9d,0xb7,0x9a,0x95,0xe5,0xc0,0x81,0xc5,0xb0,
+  0x63,0x06,0x7a,0xfb,0x0c,0x43,0x04,0x5b,0xa6,0xa0,0x45,0x4b,0xc0,0xdd,0xb0,0x0b,
+  0xda,0xb2,0x04,0xac,0x59,0x47,0xe8,0x42,0x17,0xb4,0xbd,0x41,0x1c,0xfc,0xe1,0x72,
+  0x57,0x22,0x46,0x8d,0x67,0x4f,0xf5,0xd6,0x15,0x42,0x6e,0xcd,0xc1,0x88,0xa3,0x7b,
+  0xaa,0xc4,0xaa,0x7b,0xea,0x54,0x54,0xdf,0x94,0x6e,0xf7,0x94,0x1d,0xec,0x46,0x31,
+  0x37,0xec,0xf3,0x85,0xdc,0x50,0x55,0x0c,0x74,0x2e,0x98,0x44,0x72,0x50,0x00,0xac,
+  0xb5,0x1e,0xc9,0x9b,0xbb,0x0a,0x76,0xce,0x0a,0xc2,0xd7,0x9c,0xbf,0x5b,0xa7,0x44,
+  0x10,0xbc,0x79,0x92,0x45,0x09,0xd8,0xce,0x20,0x0e,0x93,0x75,0xc0,0x31,0x5d,0xd0,
+  0x66,0x21,0xf0,0xe0,0xf8,0x06,0x71,0x98,0x84,0xc0,0x4f,0x45,0x10,0x9c,0x61,0x12,
+  0x02,0x3f,0x24,0x16,0x02,0x0f,0x70,0x77,0x10,0xc7,0xdc,0x07,0x20,0x7f,0x2d,0xe3,
+  0x30,0x4d,0x9d,0xd6,0x29,0xc3,0x21,0x18,0xfa,0xc0,0x75,0x62,0x08,0x46,0x62,0x5b,
+  0xa7,0xe2,0x1f,0x82,0x61,0x7c,0x2c,0x48,0xa6,0x8c,0x2b,0x16,0xdb,0x6a,0x39,0x1b,
+  0x65,0x38,0xff,0x6d,0xc4,0xd5,0x27,0xf1,0x10,0x22,0xb5,0x63,0x91,0x48,0x71,0x0b,
+  0xf7,0xba,0x9e,0x3e,0x84,0x03,0xac,0xb2,0xe7,0xc2,0x8e,0x99,0x8a,0x67,0x68,0x10,
+  0x2c,0x9a,0x82,0x36,0x3e,0x85,0x64,0x27,0x05,0xed,0xde,0x20,0x0e,0xf9,0x2e,0x68,
+  0x67,0x53,0xd0,0x73,0x07,0xba,0x35,0x88,0xc3,0x28,0x05,0xcd,0x2f,0x5b,0xb8,0x8d,
+  0x35,0xd7,0xa4,0x56,0xeb,0x54,0x4a,0xae,0xed,0x4b,0x2a,0x76,0x85,0x5b,0xa7,0x92,
+  0x82,0x5d,0x95,0x59,0xf5,0x29,0xe8,0x6c,0x4f,0xf6,0xad,0x8b,0x44,0xea,0xb6,0x02,
+  0x80,0x8e,0x56,0x76,0xee,0x18,0xe4,0x2c,0x83,0xdd,0x73,0x61,0xd7,0xec,0x10,0x7c,
+  0x63,0xf8,0xdb,0x1d,0x53,0xd0,0xce,0xae,0x03,0xb6,0x9d,0x82,0x76,0x65,0x10,0x87,
+  0xd4,0x2c,0xe8,0xfe,0xf8,0xa0,0xa5,0x39,0xe0,0xa9,0x4d,0xe6,0x10,0x0c,0x99,0x32,
+  0xae,0x14,0x73,0xa9,0x8c,0x6b,0x9f,0xb9,0x7a,0xc0,0x35,0x64,0x2e,0xbf,0x51,0x68,
+  0xcd,0xaa,0x4f,0x42,0x57,0x67,0xb2,0xef,0x62,0x24,0x52,0x77,0x13,0x00,0x6b,0xf7,
+  0xb0,0xaa,0x62,0x96,0xb7,0x1a,0xb2,0xd3,0xd1,0x1c,0xbe,0x1a,0xfe,0xa6,0x89,0xf1,
+  0x77,0x8a,0x44,0x17,0xb4,0x54,0x0a,0xda,0xbd,0x41,0x1c,0xce,0x76,0x41,0xeb,0x0c,
+  0xe2,0x48,0xa9,0x75,0xc0,0xfd,0x21,0xf3,0x79,0x38,0x7d,0x30,0x05,0xca,0xb8,0xbd,
+  0x6b,0x85,0x90,0x9d,0x32,0xae,0xb6,0x92,0x9b,0xb2,0xd8,0xd5,0x20,0xb8,0xa6,0x84,
+  0xd1,0xb2,0x42,0x12,0x49,0x5c,0xbe,0x0e,0xa8,0x3e,0x05,0xdf,0x6e,0xc1,0x83,0x45,
+  0x01,0xf8,0xea,0xf0,0x77,0x66,0x0c,0x7f,0x3f,0x36,0x4e,0x41,0x8b,0x0d,0xc2,0x8a,
+  0x0d,0x81,0x75,0x07,0x61,0x59,0x74,0x41,0x1b,0xaf,0x23,0xfc,0xcc,0x72,0x1d,0xa1,
+  0x7a,0x10,0x96,0x58,0x0a,0x5a,0x3d,0x08,0x4b,0x74,0x1d,0xa1,0xee,0x20,0xac,0xd8,
+  0x2e,0x68,0x93,0x41,0x58,0xf7,0x9a,0x0e,0xc2,0xd2,0x5b,0x47,0xa8,0x19,0x84,0xa5,
+  0x5a,0x47,0xb8,0xe4,0x2f,0x50,0xca,0xe1,0x4b,0xcc,0x25,0xe6,0x3a,0xc6,0x5c,0xc5,
+  0x05,0x61,0xe3,0x77,0xaf,0xcb,0x97,0xec,0x9b,0x1a,0x89,0x94,0xf2,0xe2,0x61,0x2f,
+  0xbf,0x0d,0x16,0xed,0x84,0x03,0x4b,0x31,0xe1,0xcc,0x1d,0xe6,0x6f,0xf6,0x1c,0xe4,
+  0x2f,0x76,0x5e,0x25,0x2b,0x05,0x2d,0xb5,0x8e,0xd0,0xd1,0x14,0xf4,0x32,0xb7,0x53,
+  0xd0,0x6e,0x74,0x41,0x0b,0xa4,0xa0,0x3f,0x7d,0x99,0xc3,0xd7,0xdd,0xc3,0x41,0x34,
+  0x04,0xc3,0x56,0x19,0xd7,0xfe,0x10,0x0c,0xa7,0xcb,0xb8,0x02,0xa8,0x55,0xf9,0x6c,
+  0x41,0xc8,0x47,0x55,0x2e,0x60,0xf5,0x67,0xa9,0x17,0x8b,0x44,0x32,0x11,0xf0,0xb0,
+  0xf7,0x4c,0x1e,0x0e,0x90,0xdc,0x9b,0x81,0x07,0x7b,0xa3,0xf9,0x2b,0x12,0x02,0x9b,
+  0x74,0x61,0x75,0x97,0x41,0x1c,0x2e,0xa4,0xa0,0xdd,0x5b,0x47,0x18,0x4f,0x0a,0x7a,
+  0xc9,0x20,0x7e,0x6f,0x74,0xa5,0x63,0x39,0x85,0x77,0x19,0x24,0x70,0xae,0xb2,0x79,
+  0x25,0xd7,0x80,0xb9,0x2e,0x9f,0x0c,0x72,0x87,0xb9,0x47,0x75,0x5c,0xa1,0x35,0x27,
+  0x32,0xff,0x5f,0x44,0x08,0x26,0x91,0x62,0xe5,0x6b,0xc7,0xd7,0xe4,0xb9,0x9f,0xe1,
+  0x8e,0xb9,0x3d,0x0b,0xd0,0xc8,0xdf,0x79,0x8e,0xf2,0x77,0xb2,0x0c,0x7f,0xe5,0xbb,
+  0xa0,0x9d,0x1d,0x84,0x65,0x67,0x10,0x87,0x18,0x7f,0x53,0x61,0x10,0xc7,0xf4,0x3f,
+  0xc0,0x92,0xe7,0x81,0xdf,0x93,0x09,0xbb,0x29,0x80,0xdd,0x54,0x49,0x29,0x4b,0x61,
+  0x57,0x97,0xb9,0xb1,0xd8,0x0d,0xb8,0xfc,0x1b,0x34,0xff,0x5b,0x3a,0x14,0x4c,0x22,
+  0xa9,0xe5,0xf7,0xe1,0xfd,0xb0,0x68,0x27,0xec,0xfb,0x04,0xf6,0x2e,0x40,0x47,0xf1,
+  0x57,0x8d,0xe0,0x5d,0x32,0x29,0x68,0xc1,0x41,0x58,0xc1,0x14,0xf4,0x38,0x27,0x53,
+  0xd0,0x26,0x25,0xe0,0x78,0xbb,0xa0,0x5f,0x72,0x3e,0x05,0x3d,0x5f,0x6c,0x10,0x87,
+  0x86,0xbf,0x03,0xe2,0x4a,0x41,0xf3,0x2f,0xb8,0xfc,0x70,0x82,0xcb,0xb8,0xd6,0xcc,
+  0xa5,0x32,0x6e,0x2a,0x32,0x37,0x52,0xc6,0x15,0x60,0xee,0x91,0x88,0x03,0xcc,0x0d,
+  0x3a,0x3f,0x60,0xc6,0x1f,0xae,0x9d,0x96,0x05,0x93,0x48,0x8a,0xbc,0x8d,0x98,0x70,
+  0xce,0x5d,0x05,0x7b,0x17,0x06,0xe1,0x1b,0xe1,0xef,0x7c,0xb1,0x14,0xb4,0xb3,0x5d,
+  0xd0,0x32,0x83,0x38,0x04,0xd7,0x11,0x66,0x0d,0x91,0xe8,0x82,0x5e,0x31,0x58,0x22,
+  0x05,0x2d,0xc7,0x5f,0xc1,0x2e,0xe8,0xd8,0x75,0x84,0x26,0x21,0xb0,0xad,0x41,0x58,
+  0x8b,0x9e,0x81,0x93,0xfb,0xa4,0xeb,0xb9,0xfa,0xcc,0x75,0x62,0x6d,0x9f,0x3e,0x73,
+  0x1d,0x5d,0xdb,0xe7,0x7c,0x3d,0x57,0x98,0xb9,0xc6,0x3b,0xfb,0x52,0xb8,0x75,0xea,
+  0x98,0x0c,0x73,0x8f,0x1a,0x30,0x37,0x82,0x5d,0xfe,0x62,0x2f,0x62,0xfe,0xd4,0xa8,
+  0x1d,0x9a,0xd4,0xbb,0x05,0xe0,0xc7,0x84,0xf3,0xb1,0x4d,0xf0,0xf5,0x62,0x05,0xbe,
+  0x2a,0xfe,0x5a,0x84,0xc0,0xc6,0x29,0xe8,0x20,0x82,0x4d,0xba,0xa0,0xd5,0x83,0xb0,
+  0x9c,0xed,0x82,0x76,0x61,0x10,0xc7,0x72,0xa9,0x41,0x1c,0x83,0xe4,0xd7,0x11,0x8a,
+  0x75,0x41,0x5b,0x0e,0xe2,0x90,0x1a,0x84,0xc5,0x1f,0xab,0x68,0xa7,0x73,0x43,0x30,
+  0x9c,0x58,0xdb,0x67,0x37,0xd4,0x4d,0xea,0xda,0xbe,0xe4,0x0d,0xc1,0x70,0x1e,0xb5,
+  0xb1,0xad,0x53,0x05,0x02,0x29,0xe5,0x23,0x2a,0xeb,0x32,0x57,0x8b,0x5d,0x95,0xf1,
+  0x9f,0x03,0xfc,0xc9,0xbe,0x05,0x92,0x48,0xc9,0x11,0xb4,0x35,0x43,0x71,0x36,0x0e,
+  0xb3,0xfa,0x7a,0x11,0xec,0x53,0xec,0x24,0x7f,0x6d,0xa7,0xa0,0x13,0xbc,0x0e,0x38,
+  0x95,0x06,0x71,0xb8,0xb1,0x0e,0x38,0x36,0x05,0xcd,0x3f,0xa6,0x70,0x2b,0x6b,0xaa,
+  0x4a,0xb1,0x75,0x06,0x12,0xe1,0x6d,0x32,0xb0,0xdb,0x13,0xe6,0x60,0x38,0x5c,0xc9,
+  0xd5,0xb1,0x3e,0x6a,0x0d,0x9c,0xcf,0x9a,0xab,0x92,0x7d,0x17,0x24,0x91,0x12,0xae,
+  0x0e,0x2f,0xfe,0xcc,0x1e,0x5c,0x09,0xfb,0x17,0x23,0x7c,0x35,0xfc,0x8d,0x4d,0x41,
+  0xeb,0xf1,0x57,0x07,0xc1,0x62,0xa7,0x90,0xa4,0xba,0xa0,0x9d,0x1d,0x84,0xe5,0x4a,
+  0x17,0xb4,0xe5,0x3a,0xe0,0xd8,0x41,0x1c,0x8e,0x0e,0xc2,0x92,0xed,0x82,0xe6,0x57,
+  0x28,0xd8,0x24,0xd9,0x3a,0x45,0x2b,0x84,0x12,0xc2,0xdc,0xd4,0xec,0x58,0xb6,0x60,
+  0xae,0x0c,0x70,0xcf,0xe8,0x19,0x77,0x24,0x91,0x48,0xbd,0x43,0xfe,0x2e,0xc6,0x6f,
+  0x9e,0x27,0xb2,0x71,0xb5,0x1c,0x87,0x2f,0xf2,0x37,0x53,0xc5,0xdf,0x4f,0x74,0x42,
+  0x60,0xd1,0x12,0xb0,0x7b,0x83,0x38,0x46,0xc7,0x37,0x88,0xc3,0x92,0xbf,0x26,0x83,
+  0x38,0x5e,0x73,0x6d,0x10,0x87,0xba,0x04,0xec,0xd0,0x20,0x8e,0xd9,0x46,0x29,0xe8,
+  0xd0,0x20,0x8e,0xb9,0x03,0xe1,0xe0,0x0a,0x4c,0x23,0x1b,0x56,0x72,0xe3,0x2e,0xe3,
+  0x1a,0x56,0x72,0x9d,0x2b,0xe3,0xba,0xd2,0xae,0x6c,0x5e,0xc9,0x3d,0xe9,0x56,0x25,
+  0x37,0x41,0xcc,0xb5,0xea,0x9e,0xb2,0x5d,0xc6,0x95,0x63,0x6e,0x5e,0xd0,0xa7,0x73,
+  0xc3,0x66,0x67,0x0b,0x58,0xa7,0x37,0xd9,0xb7,0x45,0x12,0xc9,0x7d,0x75,0xb4,0xe2,
+  0x8f,0x55,0xfe,0xda,0x08,0x7c,0x83,0x08,0x5e,0x64,0x27,0x05,0x1d,0x18,0xc4,0x91,
+  0xcc,0x14,0xb4,0xe0,0x20,0x0e,0x99,0x2e,0x68,0xb9,0x75,0x84,0x2e,0x74,0x41,0x2f,
+  0x10,0x4b,0x41,0xdb,0x18,0xc4,0x31,0xeb,0x6e,0xd8,0x9f,0x09,0x1c,0x8b,0x02,0x2b,
+  0x84,0xec,0x97,0x71,0x93,0xb8,0x42,0xc8,0x7e,0x19,0xd7,0x62,0x85,0x90,0xa6,0x8c,
+  0x6b,0x8d,0xdd,0xd4,0x38,0x19,0x64,0x34,0x04,0xc3,0xe9,0x32,0xae,0x45,0x78,0x7b,
+  0x3a,0x4f,0xe5,0x5c,0x95,0x0f,0x45,0x5c,0x7d,0x12,0xe3,0x02,0x12,0xa9,0xa7,0x0a,
+  0x00,0xcb,0x7c,0xc7,0xb7,0x63,0xf8,0x73,0x60,0x29,0xf2,0x57,0x8d,0xe0,0x68,0xfe,
+  0x66,0x48,0xa4,0xa0,0x6d,0x0c,0xc2,0xda,0x6a,0xd9,0x05,0xad,0x5a,0x47,0xe8,0x6c,
+  0x0a,0x3a,0x76,0x1d,0xa1,0x59,0x0a,0x5a,0xb0,0x0b,0xda,0x8d,0x14,0xf4,0x23,0x32,
+  0x5d,0xd0,0x03,0xac,0x53,0xd0,0x69,0x77,0xc0,0xce,0x99,0x50,0x5b,0x4e,0x83,0xa7,
+  0xf4,0x5a,0xa7,0xac,0xb0,0x9b,0xea,0x87,0x83,0xe2,0xef,0x9e,0x8a,0x23,0xd4,0xb5,
+  0xc0,0x6e,0xae,0x21,0x76,0xc3,0x3e,0x93,0xcb,0xff,0x17,0xd1,0x50,0x0e,0x52,0x8f,
+  0x14,0xce,0xb3,0x3a,0xff,0x2d,0xcb,0xcb,0x62,0x39,0xcb,0x14,0xf8,0x5a,0xf2,0xd7,
+  0x34,0x04,0x16,0x4c,0x41,0xcb,0xad,0x23,0x74,0x61,0x10,0x87,0x2b,0xeb,0x08,0xa5,
+  0x06,0x71,0xb8,0xb1,0x8e,0xf0,0x41,0x3b,0x83,0x38,0x66,0xde,0x85,0x79,0x7b,0xce,
+  0x2f,0x2a,0xe3,0x52,0xeb,0x94,0x23,0xad,0x53,0xfa,0xcc,0xcd,0x35,0xb0,0x1e,0x73,
+  0xb9,0x4b,0x0f,0x46,0x5c,0x96,0x8b,0x4b,0x2d,0x49,0xa4,0x9e,0x24,0xf0,0xe3,0x3a,
+  0x9b,0xe3,0xdb,0x39,0x79,0x03,0xd6,0xe7,0x6f,0x00,0xc1,0x82,0xfc,0xb5,0xd3,0x05,
+  0x6d,0xc9,0xdf,0x89,0x12,0xfc,0x75,0xa3,0x0b,0x5a,0x94,0xbf,0xf2,0x5d,0xd0,0xa2,
+  0xfc,0x75,0xaf,0x0b,0xfa,0x2e,0x3c,0xfb,0xcc,0x31,0x94,0x50,0xe6,0xaa,0x32,0xcf,
+  0x4a,0x8c,0xcc,0xea,0x2b,0x74,0x6c,0x00,0x5f,0x62,0x6e,0xcf,0x64,0xae,0x1a,0xb8,
+  0x1a,0x1f,0x40,0xf3,0xab,0x75,0xd0,0x50,0x0e,0x52,0x4f,0x91,0xaf,0x13,0x6f,0x38,
+  0x47,0xd6,0xb1,0x9c,0xe5,0x61,0xfe,0x86,0x10,0xac,0xc7,0xdf,0x44,0x76,0x41,0x5b,
+  0x96,0x80,0x5d,0xef,0x82,0x16,0x2b,0x01,0x27,0xbf,0x0b,0x5a,0x6a,0x10,0x87,0x5e,
+  0x0a,0x7a,0xf9,0xab,0x50,0xf1,0x8d,0xa3,0x2b,0x84,0x38,0x52,0x2b,0x80,0x73,0x99,
+  0x5f,0x13,0x5b,0xb9,0x2e,0xa0,0x3d,0x35,0xd0,0x52,0x13,0xd8,0x5d,0x88,0x2b,0x83,
+  0xbd,0x0d,0xe0,0x6d,0x0a,0x98,0xb5,0x35,0xe3,0x0a,0xcb,0x58,0xb7,0x79,0xb0,0xf7,
+  0xd5,0xdb,0x80,0x1f,0x1c,0xfc,0xc4,0x3a,0xd6,0x52,0x8b,0x97,0x0a,0x1c,0x3a,0x6e,
+  0xac,0xc4,0x6a,0x35,0x7f,0xb8,0xba,0x33,0xe8,0x1a,0x23,0x04,0x77,0xf3,0xd9,0x53,
+  0xf1,0x77,0x4f,0x59,0xcf,0x9e,0xca,0x97,0xab,0xe4,0xea,0x63,0x37,0x4f,0xb7,0x81,
+  0x4a,0x1f,0xbb,0x65,0x2a,0x47,0x38,0x9b,0xa3,0xf5,0x81,0x68,0xf3,0xef,0x27,0x15,
+  0x82,0x49,0x3d,0x40,0xed,0x2d,0x50,0x96,0x0b,0x87,0xd7,0xc0,0xc1,0x15,0x7a,0xfc,
+  0x8d,0x45,0x70,0xa6,0x55,0x08,0x3c,0x5f,0x2c,0x05,0x9d,0x16,0x83,0x60,0xdd,0x2e,
+  0xe8,0x29,0x12,0x83,0x38,0x62,0x07,0x61,0x99,0x75,0x41,0x0f,0x13,0x0b,0x81,0xdf,
+  0x91,0x0e,0x81,0x97,0x4b,0xa5,0xa0,0x07,0x59,0x85,0xc0,0x4f,0x45,0x10,0x9c,0xe1,
+  0xda,0x20,0x8e,0xcc,0x67,0xa0,0x78,0xb7,0xdd,0x4a,0x6e,0x00,0xb5,0xfc,0x03,0x2a,
+  0x59,0x90,0xb0,0x0a,0x58,0x03,0x3c,0xed,0xf4,0xb2,0xce,0x36,0x1c,0x61,0xd4,0xe5,
+  0x43,0xf3,0xdb,0x26,0xf0,0x3b,0x27,0x84,0x6c,0x5b,0xca,0xa7,0xf3,0x4b,0xf1,0x6b,
+  0xfa,0x3a,0x59,0x67,0x3b,0x3e,0x10,0x0f,0x8b,0xb8,0x39,0xca,0x5b,0xeb,0xc1,0xc3,
+  0x01,0x7d,0x01,0x7b,0xf8,0xf9,0xd7,0xc6,0x83,0xe2,0x84,0x55,0x72,0x53,0x64,0x85,
+  0x90,0xe1,0xe1,0x20,0xf3,0xee,0x29,0xbb,0xe1,0xad,0x61,0x25,0xd7,0x20,0xa5,0x5c,
+  0x76,0x30,0x68,0x4d,0x78,0xab,0x0f,0x5c,0x56,0xba,0x3f,0xc6,0x07,0xa0,0xa9,0x92,
+  0x0a,0xc1,0xa4,0xee,0x2d,0x1e,0x89,0x14,0x6e,0xfb,0xff,0xf6,0xce,0x04,0x4c,0x8e,
+  0xa3,0x3c,0xff,0x7f,0x03,0xe6,0x0c,0x21,0x21,0x1c,0x01,0x42,0x38,0x02,0x81,0x10,
+  0x02,0x01,0x92,0x40,0x12,0x13,0x12,0xc2,0x7d,0x05,0x08,0xe0,0x98,0xcb,0x60,0xc0,
+  0x96,0x7c,0xe3,0xfb,0x90,0x7c,0xc9,0xa7,0x90,0xb0,0x65,0xd9,0x96,0x6d,0xc9,0xc8,
+  0xb2,0x2c,0x4b,0xb2,0x6c,0x24,0x59,0x96,0x25,0x59,0xf7,0x61,0xdd,0xf7,0xb9,0xab,
+  0xd5,0x6a,0xb5,0xd2,0x4a,0x7b,0xdf,0xd7,0x9c,0x5f,0xff,0xab,0x66,0x67,0x67,0x7a,
+  0x66,0xaa,0xbb,0xaa,0x7a,0xba,0xa7,0x7a,0x66,0xde,0xdf,0xf3,0x3e,0x7e,0x6c,0x4b,
+  0x33,0xea,0xea,0x1d,0xf5,0x3b,0xdf,0x57,0x5f,0x7d,0x1f,0x1f,0xa3,0xb0,0x7d,0x9e,
+  0xb2,0xff,0xda,0x42,0xe0,0xea,0x4c,0x41,0x07,0x3e,0x8e,0x30,0x80,0x14,0xb4,0x7b,
+  0x15,0x34,0xfb,0x3d,0x07,0x97,0x5b,0xdd,0x4d,0xea,0x59,0x65,0xfe,0xff,0x59,0xd4,
+  0xc9,0x3c,0x8e,0x45,0xa6,0xd1,0x7e,0x8a,0x0e,0xa5,0x1c,0x36,0x66,0x25,0x47,0x1c,
+  0x36,0x99,0x7a,0x36,0x9a,0x7b,0x3c,0xb2,0x3f,0x9d,0x5d,0x03,0xbb,0x12,0x76,0x49,
+  0xec,0xc2,0xd8,0x17,0x80,0xe8,0x10,0xbf,0xd4,0xbe,0x76,0xab,0xfb,0x94,0xc5,0xed,
+  0xb8,0x9c,0x0f,0xe4,0x96,0x63,0x4a,0xd9,0x31,0xab,0x5c,0x10,0xdb,0x3a,0x7a,0x6e,
+  0xae,0x1a,0x77,0x5a,0xc3,0xfd,0xc6,0x3e,0x60,0x00,0x14,0x43,0x22,0xc6,0x73,0x6b,
+  0x7b,0x16,0xd1,0x8e,0x67,0xb9,0xb2,0xfe,0x8b,0x14,0xb4,0xce,0x38,0x60,0xbd,0x53,
+  0x48,0x17,0x6b,0x9f,0x42,0x0a,0xa2,0x11,0x47,0x9e,0xff,0x3e,0xf2,0x7d,0xfe,0x53,
+  0xee,0x6a,0x72,0x36,0x5c,0x16,0xf6,0x9e,0x61,0xe2,0x8d,0xb0,0x06,0x98,0xe1,0xf6,
+  0x11,0xb3,0xb3,0xb4,0xcf,0x52,0x59,0xc5,0x20,0x94,0xf1,0x65,0x8a,0x47,0xac,0xc1,
+  0x1e,0xea,0x6d,0xb5,0x78,0x74,0x7c,0xdc,0x6a,0xad,0x73,0x8e,0x79,0xc3,0x51,0xae,
+  0xac,0xd5,0x04,0xa3,0x52,0x3d,0xd7,0x26,0x3a,0xb6,0x99,0x8f,0x09,0x66,0x9f,0x43,
+  0x00,0xca,0x09,0xe2,0x09,0x3a,0xf6,0x57,0x83,0x85,0xbd,0x3b,0x9f,0xe5,0xe2,0xfe,
+  0x3b,0xdf,0xd9,0x7f,0x0b,0xab,0xa0,0xa5,0x29,0xe8,0x19,0x01,0x8c,0x03,0x9e,0xa4,
+  0xd3,0x88,0xa3,0x72,0xc7,0x11,0xba,0xcd,0x62,0xd0,0x1f,0x47,0x38,0xed,0x7b,0xfc,
+  0xf6,0x76,0x9e,0xca,0xd9,0xc6,0xe5,0x19,0xe6,0x33,0xfc,0xe4,0x51,0x5f,0x1b,0x33,
+  0x5c,0xf6,0x69,0x49,0x1b,0x6e,0xa5,0xc2,0x96,0x16,0x19,0xe0,0x5f,0x2d,0xba,0x4f,
+  0xf3,0x12,0xaf,0xf6,0x94,0x1d,0x57,0xca,0x08,0x21,0xa3,0xdb,0xb8,0xdb,0x25,0xdb,
+  0xb8,0x8a,0x9e,0x5b,0x9f,0x15,0xb7,0x5d,0xae,0x57,0xd2,0x62,0x3f,0xaf,0x72,0xfa,
+  0x06,0x08,0xaa,0x1c,0xe2,0x01,0x4e,0xcd,0xba,0xac,0xf9,0x8e,0xf8,0x6f,0x4e,0x08,
+  0xac,0x96,0x82,0xce,0x69,0x84,0xe5,0x7c,0x10,0x38,0xc7,0x7f,0x65,0xe3,0x08,0xdd,
+  0x1a,0x61,0xb9,0xa7,0xa0,0x9d,0xc7,0x11,0xe6,0x6c,0x01,0x3b,0x37,0xe2,0xc8,0xf1,
+  0x5f,0x59,0x23,0x0e,0x69,0x23,0xac,0x79,0x4e,0xb3,0x18,0x64,0x8d,0x38,0xdc,0x1a,
+  0x61,0xb9,0xcf,0x62,0x10,0x8d,0x23,0x94,0x36,0xc2,0x62,0x8b,0x6d,0xae,0xc9,0xda,
+  0x6e,0x6f,0x0b,0xf5,0x77,0xf0,0x4a,0xa7,0x48,0x3f,0xc5,0x22,0x34,0x12,0xe1,0x56,
+  0x0f,0x44,0x94,0x88,0xa5,0xbc,0xb8,0xd3,0xea,0x6d,0xe6,0x75,0xd7,0x6d,0xc7,0xca,
+  0xa7,0x74,0xaa,0x82,0x3c,0xb7,0x5e,0xe8,0xb9,0x36,0xdb,0x3d,0xb6,0x29,0x2d,0xf6,
+  0xab,0x83,0x5d,0xa6,0x3f,0x37,0x00,0x28,0xc0,0xbe,0xe7,0xb7,0xd5,0xf1,0x19,0x46,
+  0x3b,0x9f,0x73,0xf5,0x5f,0xbb,0x05,0xcf,0x29,0xab,0x14,0x74,0x00,0x8d,0x38,0xb4,
+  0x52,0xd0,0xaa,0x8d,0x38,0x0a,0x7b,0x51,0x96,0xb8,0x17,0x74,0xaa,0x11,0xc7,0x9c,
+  0x31,0xbc,0x00,0x86,0x05,0x7d,0x7d,0xed,0x34,0xd8,0x6d,0x45,0x07,0xf9,0x56,0x69,
+  0xb5,0x79,0xae,0x13,0x94,0xe4,0x77,0x83,0x7d,0x0f,0x61,0x5f,0x48,0xd8,0x97,0x13,
+  0x16,0x11,0x97,0xac,0x74,0x2a,0xb8,0x26,0x18,0x7a,0xa5,0x53,0x0e,0x59,0x65,0x71,
+  0xe9,0x94,0xb8,0x7a,0x4a,0x2f,0xa5,0x5c,0xbf,0x39,0xad,0x63,0x9b,0x45,0x9e,0x6b,
+  0xb3,0x5d,0xbb,0xd8,0xc2,0x31,0xa0,0x10,0x84,0x9c,0x64,0x8c,0xff,0x85,0xda,0xf7,
+  0x02,0xed,0x7e,0x3e,0xe5,0xbf,0xcf,0x65,0xfd,0xd7,0x66,0xc1,0xaa,0x29,0x68,0xad,
+  0x83,0xc0,0xfe,0xa6,0xa0,0x3d,0x54,0x61,0xc9,0x53,0xd0,0x3a,0xbd,0xa0,0xcb,0xab,
+  0x11,0x87,0x53,0x0a,0x7a,0xfa,0xff,0xb1,0x07,0x1a,0xaf,0x16,0x4e,0x7b,0x2e,0xe6,
+  0xbb,0x39,0xc0,0xbe,0x8d,0xb0,0x2f,0xae,0xb1,0x61,0x1a,0xea,0xe6,0x59,0x82,0x96,
+  0x3a,0x81,0xf9,0x96,0xfa,0x40,0x6e,0xd1,0xdb,0xb8,0x8e,0x3b,0xb9,0x26,0xb6,0x71,
+  0x05,0x12,0xf9,0xac,0x93,0xea,0x36,0x59,0xed,0x0d,0xa6,0x3f,0x25,0x00,0x38,0x42,
+  0xd1,0x41,0x3a,0xba,0x91,0x76,0x2f,0xe4,0xe6,0xeb,0xea,0xbf,0x9e,0x52,0xd0,0xbe,
+  0x56,0x41,0x07,0xe1,0xbf,0x01,0x56,0x41,0x97,0x67,0x23,0x8e,0xc7,0xcf,0xe5,0x05,
+  0xcf,0x88,0x73,0xb5,0xe1,0xe5,0x5b,0x14,0x19,0xe4,0x47,0xa4,0x5b,0xeb,0xa8,0xf9,
+  0x88,0x86,0xf9,0x86,0x61,0x84,0x50,0x65,0xd9,0x6e,0x8e,0x06,0x31,0x1d,0x09,0x84,
+  0x10,0xa2,0x81,0x0e,0xaa,0xdd,0xc0,0x4b,0x9d,0x77,0xff,0x31,0x25,0x91,0x05,0x3b,
+  0xa7,0xa0,0x69,0xab,0x62,0x0a,0x5a,0xad,0x17,0xf4,0xc8,0x16,0xb0,0xd3,0x41,0x60,
+  0xb7,0x14,0xb4,0xac,0x17,0xf4,0x4b,0xb6,0x5e,0xd0,0x4b,0xb5,0x52,0xd0,0xe3,0x65,
+  0xbd,0xa0,0xaf,0x93,0xf4,0x82,0xce,0xf1,0x5f,0xe7,0x14,0xb4,0xe2,0x16,0xb0,0xe3,
+  0x2c,0x86,0xf3,0x25,0xfe,0xab,0xd8,0x88,0x83,0xfd,0x73,0xfd,0x34,0x0c,0x34,0x2f,
+  0x0a,0x22,0xbe,0x39,0x3e,0xdc,0xc7,0x5b,0x8b,0xb4,0x1f,0xe7,0x7b,0xe8,0xea,0x3b,
+  0xb9,0xc2,0x6d,0x5c,0xc7,0x26,0x18,0xc1,0x6f,0xe3,0x2a,0x35,0xc1,0xf0,0xea,0xb9,
+  0x92,0x6d,0x5c,0x87,0x94,0xb2,0xdc,0x73,0x37,0xe6,0xe8,0xe8,0x06,0xb6,0x6a,0x0b,
+  0x59,0x68,0x10,0x2a,0x58,0x80,0xd3,0xdd,0x44,0x35,0x6b,0xb8,0xf9,0x2a,0xf9,0xaf,
+  0xac,0x0a,0x3a,0xc7,0x7f,0x65,0x55,0xd0,0xde,0xc7,0x11,0xca,0xc6,0x01,0x7b,0x18,
+  0x47,0xe8,0x6f,0x0a,0x5a,0xb1,0x0a,0x7a,0xae,0xd6,0x16,0xf0,0x6f,0xd4,0xaa,0xa0,
+  0x7f,0xa6,0x51,0x05,0x2d,0xf4,0xdf,0x17,0xc6,0xf3,0xfe,0x51,0xc0,0x17,0x98,0x11,
+  0xc7,0xa3,0x34,0xd8,0xcd,0x8d,0xb8,0xed,0x98,0x5a,0x9c,0x5b,0xd2,0xb1,0x7d,0x6e,
+  0x71,0xae,0xa4,0x7a,0xca,0x5f,0xcf,0x15,0x55,0x4f,0x69,0xc7,0xb9,0x36,0xc3,0x2d,
+  0x54,0xfb,0x71,0x93,0x47,0xce,0x01,0xb0,0xc1,0xbe,0xa0,0xf3,0x07,0xc2,0xa1,0x15,
+  0xb4,0x77,0x11,0x17,0xb7,0xe0,0x85,0x59,0x0b,0x96,0xa7,0xa0,0xe7,0x2a,0xa5,0xa0,
+  0xd3,0x16,0x2c,0x1a,0x07,0xec,0xbd,0x11,0xc7,0x14,0xff,0xc7,0x11,0xca,0xc7,0x01,
+  0x7b,0x18,0x47,0x78,0xb5,0x5a,0x23,0x0e,0xb5,0x71,0xc0,0x39,0x55,0xd0,0xbf,0xf2,
+  0x5a,0x05,0x2d,0x6b,0x84,0xc5,0xfe,0x94,0xb6,0x7a,0xd3,0x9f,0xcd,0x4a,0x84,0x92,
+  0xbc,0x01,0x17,0xfb,0x62,0xd3,0xd1,0xc0,0x5d,0x38,0x54,0x63,0xfb,0x0a,0x4b,0xa7,
+  0xf2,0x0b,0xa8,0x04,0xa1,0xae,0x56,0x3e,0xd9,0x7b,0xf5,0x94,0x4b,0x4a,0x79,0x44,
+  0x47,0x37,0xda,0x94,0x71,0xdb,0xf5,0x02,0xd5,0xbf,0xc2,0x5b,0xac,0x00,0x60,0x1a,
+  0x4a,0x26,0x78,0x51,0xe5,0x81,0x17,0xd3,0xe6,0x9b,0xf6,0x5f,0xcf,0x29,0x68,0xa9,
+  0xff,0x6a,0x8d,0x03,0x0e,0xac,0x0a,0x5a,0x75,0x0b,0xb8,0x0c,0x1b,0x71,0x28,0x8e,
+  0x03,0x76,0xaf,0x82,0x7e,0xec,0x5c,0xf6,0x78,0xc4,0xb6,0x6f,0x90,0xf0,0x62,0x2d,
+  0x8a,0x0e,0xf1,0x70,0x98,0xb9,0xb0,0xa0,0x56,0x39,0x7c,0xe3,0x0c,0x42,0xb5,0x8d,
+  0x9b,0xb5,0x5d,0x51,0x84,0x2b,0xb4,0x5d,0xa6,0xda,0x75,0x23,0xb2,0x1a,0x77,0x12,
+  0xfa,0x42,0x03,0xa3,0x50,0x64,0x80,0x1f,0x8b,0xdb,0xfb,0x42,0x4a,0xca,0xfe,0xbb,
+  0x53,0xda,0x08,0xcb,0xf3,0x38,0xc2,0x00,0x52,0xd0,0xd2,0x46,0x58,0x41,0x57,0x41,
+  0xfb,0x30,0x8b,0x41,0xff,0x14,0x92,0xdd,0x82,0xdd,0xfc,0x57,0x54,0x05,0xfd,0xf8,
+  0xb9,0xec,0xe7,0x6b,0xfa,0xb3,0x59,0x45,0x50,0x32,0xc9,0xfb,0x73,0xf2,0xa4,0xf4,
+  0x21,0xbd,0xac,0x72,0xb5,0x95,0x4e,0x15,0xe7,0xb9,0xf9,0x6a,0x3f,0x86,0x6f,0x98,
+  0xc0,0x18,0x83,0xdd,0xfc,0x2f,0xd4,0xfe,0x25,0x0e,0xfe,0xbb,0x30,0xeb,0xbf,0xbb,
+  0x9e,0x13,0x1c,0x04,0xf6,0xde,0x08,0x4b,0x96,0x82,0xd6,0xf3,0x5f,0xc5,0x46,0x1c,
+  0x3a,0x8d,0xb0,0x4c,0x36,0xe2,0xd0,0xaa,0x82,0xfe,0x55,0x71,0x8d,0x38,0x1c,0xaa,
+  0xa0,0x5f,0x9c,0xc0,0xbe,0x98,0x99,0xfe,0x74,0x56,0x1d,0x7c,0x1b,0x68,0xb0,0x87,
+  0x4f,0x65,0x6a,0x3e,0x42,0xa7,0x9c,0x5d,0x38,0xdf,0x6d,0xdd,0x77,0x72,0x4b,0xb2,
+  0x8d,0x7b,0x3c,0xb8,0x6d,0x5c,0xd9,0x4e,0xae,0xae,0xe7,0xda,0x55,0xb7,0xc1,0x42,
+  0x16,0x1a,0x94,0x1e,0x22,0x5e,0x57,0x53,0xb7,0x91,0x99,0xaf,0xc0,0x7f,0x8b,0x4b,
+  0x41,0x2b,0x37,0xe2,0x50,0xab,0x82,0x5e,0x2f,0x6b,0x84,0xe5,0xbd,0x11,0xc7,0x3d,
+  0xda,0x8d,0x38,0x5e,0x50,0x4b,0x41,0x3f,0xaf,0x35,0x8e,0x50,0xda,0x88,0x63,0x6c,
+  0x60,0x8d,0x38,0xce,0x13,0x54,0x41,0xb3,0x3f,0xb1,0x1d,0xdb,0xbe,0xe6,0x60,0x11,
+  0x19,0xfb,0xf2,0xd3,0xdb,0x6c,0x35,0xd7,0x68,0xee,0xe4,0xca,0xe6,0x07,0xc9,0xb6,
+  0x71,0xbd,0x37,0xc1,0xa8,0xf7,0x75,0x1b,0x57,0x6b,0x27,0x57,0xd1,0x6a,0x33,0xaa,
+  0x59,0x6b,0xd3,0x1a,0x5e,0xdb,0x86,0x2c,0x34,0x28,0x31,0xbd,0xad,0x7c,0x84,0x5c,
+  0xca,0x7c,0xb9,0xf6,0x8d,0x58,0xf0,0x62,0xd3,0x29,0x68,0xfd,0x71,0x84,0x6e,0x29,
+  0x68,0xd9,0x29,0x24,0xf7,0x71,0x84,0x6e,0x29,0x68,0xd9,0x29,0xa4,0xc2,0x71,0x84,
+  0x66,0x52,0xd0,0xe7,0x6b,0xa7,0xa0,0x99,0x23,0xd7,0xae,0x43,0x52,0xce,0x3c,0x94,
+  0xb4,0xa2,0x83,0xd4,0xd7,0x62,0x9d,0x3e,0xe8,0xa5,0x7a,0xca,0x87,0xb1,0x7d,0x9e,
+  0xab,0xa7,0x8a,0xc9,0x2a,0x17,0x7a,0xae,0xef,0xb6,0xbb,0x26,0xab,0x23,0xec,0x9f,
+  0xeb,0xf8,0xac,0x10,0x00,0x4a,0x03,0xa5,0xba,0x3a,0x1f,0x5e,0x49,0x07,0x5e,0xca,
+  0xfa,0xaf,0x24,0x04,0xf6,0xb5,0x11,0x47,0x35,0x8f,0x23,0x54,0x6d,0x84,0xa5,0xdf,
+  0x88,0xc3,0x97,0x71,0x84,0xd3,0xcf,0xe5,0xd5,0xe9,0x89,0x98,0xe9,0xcf,0x28,0x18,
+  0x85,0xfd,0x6d,0x8d,0x47,0xf9,0xa0,0xe4,0xa6,0x83,0xb9,0x19,0xe6,0x4a,0xd9,0xc9,
+  0x15,0xa7,0x94,0x1d,0x3c,0x57,0xcf,0x70,0xd7,0x88,0x75,0xa4,0x40,0xc7,0x5e,0xb1,
+  0xe2,0x11,0xd3,0x3f,0x69,0x50,0x05,0x24,0x13,0xd4,0x79,0xd2,0x3a,0xb4,0x9c,0x99,
+  0xef,0x88,0x8c,0xf9,0xaf,0x56,0x15,0xb4,0xaa,0xff,0xfa,0x7a,0x0a,0xa9,0x2c,0xc7,
+  0x01,0xeb,0x54,0x41,0x17,0xfa,0x2f,0x5b,0x57,0x6c,0xc8,0xf4,0x67,0x14,0x08,0xa0,
+  0x64,0x9c,0xfa,0x5a,0x69,0x24,0x23,0x6d,0xb2,0x5c,0xb9,0x0c,0x3d,0xb7,0xd0,0x70,
+  0x47,0x74,0x78,0x55,0x56,0x2d,0x35,0xc8,0xf9,0x80,0x60,0x61,0xe6,0xdb,0x71,0x82,
+  0x0e,0xbd,0x9c,0x31,0x5f,0x49,0x08,0x5c,0xd4,0x16,0x70,0xf9,0x56,0x41,0x1b,0x6c,
+  0xc4,0x71,0x99,0x7e,0x23,0x0e,0xff,0xaa,0xa0,0xd9,0x3b,0x9c,0x39,0x6c,0xfa,0x33,
+  0x0a,0xdc,0xa0,0x44,0xdc,0xea,0x6d,0x61,0x66,0xc1,0x43,0x60,0xc1,0x36,0xae,0x0f,
+  0x23,0x84,0x1c,0xb6,0x71,0x75,0x0a,0xa8,0x84,0xa5,0x53,0xfe,0x57,0x4f,0xad,0xcd,
+  0x4a,0x6e,0xbb,0xab,0xb3,0xca,0xda,0xee,0xca,0xac,0x6a,0xd6,0x5a,0x18,0x8d,0x04,
+  0x82,0x83,0x7d,0xbb,0x6b,0x3b,0x66,0x1d,0x59,0xc5,0x47,0x1a,0x31,0x65,0x2d,0x78,
+  0xa9,0x2c,0x04,0x5e,0x28,0x0b,0x81,0xe7,0xeb,0x84,0xc0,0xb3,0x02,0x6e,0xc4,0xe1,
+  0x32,0x0e,0xb8,0xa0,0x0a,0x3a,0x88,0x46,0x1c,0xf2,0x10,0xd8,0xdf,0x46,0x1c,0xbf,
+  0xd1,0x68,0xc4,0xf1,0x84,0x73,0x15,0xf4,0xf4,0xf3,0xd8,0x4f,0x13,0x83,0x15,0xca,
+  0x83,0xd8,0xb0,0xd5,0xdb,0xcc,0xbe,0x2c,0x15,0xc6,0xb9,0xd5,0xbb,0x8d,0x2b,0x8e,
+  0x70,0x57,0x8f,0x6a,0x95,0xc8,0x76,0x5f,0xce,0x51,0xe3,0x2e,0x14,0x62,0x81,0x40,
+  0xa0,0x24,0xef,0xb7,0x76,0x78,0x95,0x75,0x70,0x79,0x81,0xff,0x2a,0xa6,0xa0,0xed,
+  0x16,0xec,0x57,0x23,0xac,0x50,0x8d,0x23,0xac,0xee,0x46,0x1c,0x0b,0x6f,0xa6,0xe1,
+  0x3e,0xd3,0x1f,0x53,0xa0,0x0c,0xfb,0x3a,0xcd,0x1b,0x77,0x34,0xd3,0xc9,0xbd,0xa1,
+  0xd8,0xc6,0xf5,0xeb,0x40,0xae,0xbf,0x59,0xe5,0xac,0x5e,0x96,0xeb,0xc8,0x4a,0x3e,
+  0x5e,0x13,0x00,0x7f,0x61,0x41,0x0d,0x37,0xdf,0x95,0xcc,0x7c,0xdd,0xfd,0x77,0xd4,
+  0x82,0xfd,0x3a,0x85,0xa4,0x9f,0x82,0x0e,0xc2,0x7f,0xb5,0x52,0xd0,0xfe,0xfa,0x6f,
+  0x48,0x1a,0x71,0x48,0xfd,0x77,0xe6,0x2f,0xa9,0xed,0x98,0xe9,0x8f,0x29,0xd0,0x67,
+  0xa4,0xa1,0x74,0x67,0xa3,0x75,0x62,0x87,0xe5,0x1c,0xfc,0xc2,0x73,0xa5,0xb2,0x0e,
+  0xad,0x60,0xe2,0x17,0x89,0x42,0x2c,0xe0,0x23,0xc9,0x04,0xef,0x31,0x3b,0xfa,0x01,
+  0xcb,0x5a,0xb0,0xe2,0x16,0xf0,0xde,0x82,0x46,0x1c,0x25,0x1e,0x07,0xac,0x37,0x8e,
+  0x50,0xb1,0x11,0x87,0xf1,0x2a,0xe8,0x20,0x1a,0x71,0x78,0x1d,0x47,0xf8,0xc4,0xcf,
+  0xf8,0x8f,0x18,0xc5,0x27,0xe5,0x0c,0x45,0x86,0xa8,0xf5,0x98,0xd5,0xb8,0xcb,0xa1,
+  0x0f,0x46,0xf1,0x23,0x84,0x82,0xdb,0xc9,0x5d,0xab,0xb3,0x93,0xbb,0x5a,0xbe,0x93,
+  0xab,0x6f,0xbb,0x39,0x6a,0x46,0x21,0x16,0xf0,0x09,0xf6,0x54,0xed,0x38,0x41,0x35,
+  0xab,0x05,0xfe,0x6b,0xb3,0x60,0x6b,0xff,0x8b,0x59,0xff,0xdd,0x27,0xab,0x82,0x16,
+  0x36,0xc2,0x72,0xac,0x82,0x76,0x6e,0xc4,0x91,0xd3,0x08,0x4b,0x67,0x1c,0xa1,0xbc,
+  0x11,0x47,0xa1,0xff,0x3a,0x1f,0x04,0x5e,0x56,0x30,0x8e,0xd0,0xcd,0x7f,0x9d,0x1b,
+  0x61,0xe5,0xf8,0xaf,0xad,0x11,0x96,0xdb,0x38,0xc2,0x42,0xff,0x2d,0x7a,0x1c,0xa1,
+  0x6a,0x23,0xac,0x51,0xff,0x65,0xef,0xb6,0xf6,0x11,0x8a,0xf4,0x9b,0xfe,0xa4,0x82,
+  0x62,0xe1,0x5d,0xdc,0xfb,0xda,0xad,0xe6,0x23,0x54,0xbf,0x35,0xa8,0xb1,0x7d,0xbe,
+  0x55,0x2c,0xcb,0x0c,0xd7,0xc9,0x73,0xc5,0xdb,0xb8,0x45,0x7b,0xee,0xe8,0x83,0x91,
+  0x3f,0x1b,0x8f,0xac,0xc2,0x5c,0x06,0xe0,0x03,0xcc,0x7c,0xbb,0x4e,0xf1,0x4f,0xb8,
+  0xfd,0x83,0x17,0xfe,0x14,0xf4,0x26,0xad,0x14,0xb4,0x62,0x23,0x0e,0x9d,0x14,0xb4,
+  0xe2,0x38,0x60,0xc5,0x46,0x58,0x9e,0xc7,0x11,0x06,0xd2,0x88,0xc3,0xe6,0xbf,0xec,
+  0xe5,0xec,0xfb,0x4c,0xc3,0x0e,0x94,0x7d,0x56,0x14,0xf1,0x08,0xdf,0x14,0x6e,0xdc,
+  0x5d,0xc4,0xe1,0x20,0x61,0xe9,0x94,0x2f,0x87,0x83,0x7c,0x2c,0x9d,0x92,0x7b,0xae,
+  0xd8,0x67,0x6d,0x56,0x6b,0x57,0xfa,0x91,0x38,0xa2,0x93,0x7b,0x10,0x02,0x83,0xa2,
+  0xe0,0x4d,0x36,0x9a,0xa9,0x76,0xbd,0xe0,0x03,0x29,0x0e,0x81,0x4d,0x34,0xe2,0x50,
+  0x4c,0x41,0x2b,0x9e,0x42,0xaa,0xcc,0x46,0x1c,0x6a,0xfe,0xab,0x95,0x82,0x66,0x31,
+  0x32,0xbb,0xb1,0x2d,0x35,0x16,0x2f,0xb8,0xc2,0x73,0xa6,0xe2,0x60,0x5f,0xbc,0x23,
+  0x03,0xd4,0x7a,0xb4,0x6a,0xb7,0x71,0xbd,0x78,0xae,0x5d,0xec,0xf7,0xf7,0xb7,0x99,
+  0xfe,0x29,0x82,0xb2,0x65,0xc4,0x7c,0xd9,0xf7,0xcc,0xdc,0x4f,0xaf,0x1f,0xfe,0x1b,
+  0xc4,0x38,0x60,0xfd,0x71,0x84,0x26,0x1b,0x71,0x68,0x55,0x61,0xa9,0x35,0xe2,0x28,
+  0x4d,0x15,0xf4,0xac,0x5f,0xf3,0xf7,0x67,0x3f,0x8b,0x9e,0x33,0x38,0x67,0x54,0xf9,
+  0xf0,0x51,0x0e,0xdd,0x7c,0x94,0x52,0xfd,0x66,0xd8,0xae,0x92,0xed,0xda,0xf2,0x81,
+  0x2c,0xfc,0xb7,0xd0,0x05,0x0e,0x78,0x81,0xa8,0xaf,0x8d,0xff,0x3d,0xca,0x7e,0xb0,
+  0xe5,0xfe,0x2b,0xb2,0x60,0x9d,0x5e,0xd0,0xf2,0x14,0xb4,0x87,0x53,0x48,0xd3,0xfd,
+  0x4c,0x41,0xdb,0xb7,0x80,0x57,0xf8,0xd4,0x0b,0x3a,0xed,0xbf,0xb2,0x5e,0xd0,0x6e,
+  0x5b,0xc0,0x85,0xfe,0x7b,0x85,0x5a,0x23,0x8e,0x42,0xff,0xfd,0x8d,0xa3,0xff,0xb2,
+  0x5f,0x5d,0x72,0x3b,0xdf,0xb2,0xef,0x3e,0x8d,0x3a,0xab,0xaa,0x82,0x12,0x51,0x6a,
+  0x3f,0xce,0xa7,0x1d,0x65,0xf6,0x73,0xc3,0xdc,0x04,0xc3,0xac,0xe7,0xe6,0xa9,0xfd,
+  0xb8,0xe9,0x9f,0x1e,0x28,0x43,0x86,0xba,0xf9,0x3c,0xdf,0x9c,0x2f,0x96,0x82,0x10,
+  0x58,0xc1,0x7f,0x5d,0xc7,0x11,0x8a,0x67,0x31,0x78,0x1e,0x47,0xe8,0x53,0x0a,0xba,
+  0x44,0xe3,0x08,0x9d,0x53,0xd0,0x8a,0x5b,0xc0,0x7a,0x29,0x68,0xc5,0x46,0x1c,0x17,
+  0x0a,0xfc,0xf7,0xe9,0x0b,0xf9,0x32,0xf7,0x2f,0xa5,0xce,0x93,0x84,0x98,0xb7,0x2a,
+  0xe1,0x3f,0xf7,0xfe,0x0e,0x3e,0x56,0xd8,0xcf,0x6e,0x18,0xea,0x9e,0xbb,0x46,0x56,
+  0x3d,0x15,0x26,0xcf,0xb5,0x75,0x25,0x62,0x17,0x6c,0x61,0x04,0x27,0xd0,0x22,0x32,
+  0xc8,0x5b,0xc2,0x66,0xff,0x16,0xac,0x1e,0xfd,0xa8,0xab,0x84,0xc0,0xd2,0x46,0x58,
+  0xb6,0x10,0x78,0x97,0x46,0x23,0x0e,0x85,0x71,0x84,0x3a,0x55,0xd0,0x81,0x8f,0x23,
+  0x94,0xa6,0xa0,0xd5,0xaa,0xa0,0x17,0xde,0x28,0x6b,0xc4,0x71,0xb5,0xd7,0x14,0xb4,
+  0xb4,0x0a,0xfa,0x57,0x3c,0x1c,0x5e,0x39,0x99,0x37,0x96,0xef,0x46,0xb6,0x19,0xf0,
+  0x96,0x59,0xd4,0x79,0xca,0xaa,0x7f,0xc5,0x63,0x3e,0xb9,0xb6,0x60,0x6c,0x9f,0x4b,
+  0x4a,0x39,0x5b,0x3a,0x95,0x57,0x40,0x55,0x74,0xf5,0x94,0xc8,0x67,0x1d,0xad,0x56,
+  0xc9,0x67,0xed,0x67,0x40,0xec,0x4a,0x3d,0x06,0x4f,0x1f,0x42,0x21,0x16,0x50,0x84,
+  0x8f,0xad,0x69,0xdc,0x95,0xdd,0x7c,0x11,0x85,0xc0,0x9a,0x29,0x68,0x7f,0xab,0xa0,
+  0xcb,0xa5,0x11,0x56,0x70,0x8d,0x38,0x14,0xc7,0x01,0xeb,0x34,0xe2,0x28,0xf4,0xdf,
+  0xd9,0xbf,0xe1,0x0b,0x39,0xb1,0xd3,0x1a,0xea,0x85,0xf3,0x82,0x2c,0x94,0xa4,0xa1,
+  0x1e,0xde,0x65,0xb1,0x56,0xd9,0x7c,0xd5,0x47,0x08,0x39,0x6e,0xe3,0xfa,0xb1,0x93,
+  0x1b,0xa0,0xed,0x2e,0x71,0xd3,0x81,0x65,0x14,0x45,0x08,0x0c,0x14,0x88,0x47,0xe9,
+  0xd4,0xde,0x9c,0xbf,0x38,0xb2,0x14,0xb4,0x5e,0x23,0x0e,0xc5,0x71,0xc0,0xc1,0x35,
+  0xe2,0xf0,0x6d,0x16,0x83,0xd7,0x2a,0x68,0x7f,0x67,0x31,0xf8,0x5f,0x05,0x7d,0x11,
+  0x7f,0x43,0xb6,0xc6,0xa6,0x03,0x94,0x84,0xed,0x02,0x31,0xfc,0xb3,0xd1,0xde,0xc0,
+  0x8b,0xb2,0x02,0xf4,0xdc,0x10,0xa6,0x94,0x97,0x66,0x24,0xf1,0xdc,0x5c,0xb1,0xaf,
+  0x2b,0x08,0x81,0x81,0x84,0x44,0x9c,0x5a,0x8e,0x0a,0xfe,0x12,0xa5,0x73,0x41,0xaa,
+  0x29,0x68,0x33,0x8d,0x38,0x36,0x97,0xb2,0x11,0x87,0xd4,0x7f,0x03,0x6b,0xc4,0xe1,
+  0xf3,0x38,0x42,0x7b,0x0a,0xfa,0x22,0x5e,0xe2,0xc5,0xee,0x09,0x0b,0x6d,0xe2,0xc3,
+  0xa6,0x3f,0x8b,0x20,0xf4,0x30,0x43,0xe9,0x6f,0xa7,0xc6,0x3d,0xa9,0x40,0xb8,0xd2,
+  0xb7,0x71,0xd5,0x3d,0x77,0x5f,0x5a,0xa3,0xa1,0x47,0x4a,0xec,0x91,0x38,0xd8,0x69,
+  0xfa,0x07,0x06,0xc2,0x0b,0x51,0x92,0x3a,0x1a,0x78,0x41,0x85,0xd0,0x7f,0x9d,0x42,
+  0x60,0x33,0x55,0xd0,0x1e,0xc6,0x11,0xfa,0x5a,0x05,0xbd,0x72,0x72,0xd6,0x82,0x55,
+  0x1b,0x71,0x28,0x8e,0x23,0x94,0x56,0x41,0x5f,0xaf,0x51,0x05,0x3d,0xff,0x8a,0xac,
+  0x05,0xcf,0x75,0x0d,0x81,0xd9,0x6b,0xb7,0xcc,0xa2,0x13,0x3b,0x50,0x2b,0x02,0xf4,
+  0x60,0x1f,0x98,0xd6,0x3a,0xbe,0x11,0xac,0xd4,0x04,0xc3,0xd7,0x6d,0xdc,0x40,0xac,
+  0x56,0xb8,0x93,0x2b,0x0b,0x6f,0x59,0x94,0x91,0x51,0xd6,0x76,0x17,0xdb,0xb4,0xc8,
+  0x3a,0xbe,0x15,0x73,0x91,0x80,0x13,0xd4,0xdd,0xc4,0x5b,0xcc,0xe5,0xd7,0x54,0xac,
+  0xb5,0x85,0xc0,0x25,0x4e,0x41,0xeb,0x54,0x41,0x6f,0x09,0xa0,0x0a,0x7a,0x8d,0x5a,
+  0x0a,0xba,0x70,0x1c,0x61,0x79,0xa5,0xa0,0xd9,0xaf,0xb2,0x1b,0x78,0xfa,0x10,0x6f,
+  0xa3,0x81,0x14,0x19,0xf0,0x40,0x22,0x4e,0x3d,0x67,0xf8,0xd3,0x43,0xaf,0xf7,0x54,
+  0xa8,0x22,0x5c,0xbf,0x3c,0xd7,0x6e,0xbb,0x8b,0x72,0xc4,0x82,0xe2,0xde,0x66,0xd3,
+  0x3f,0x2a,0x10,0x46,0x68,0xa0,0x8b,0x9f,0x36,0xca,0x9c,0x26,0x70,0x0b,0x81,0x9d,
+  0xfd,0xd7,0xf3,0x38,0x42,0x83,0x8d,0x38,0x54,0x1b,0x61,0xe9,0x57,0x61,0xf9,0xdb,
+  0x08,0x4b,0xab,0x11,0x87,0x4a,0x0a,0x7a,0xee,0x25,0xf4,0xec,0x95,0xfc,0x56,0x74,
+  0x34,0x50,0x74,0x08,0xce,0x0b,0x8a,0x82,0x88,0x86,0xfb,0xf9,0xce,0x85,0x78,0x33,
+  0xb7,0xb4,0xa5,0x53,0x7a,0x9e,0xab,0xb3,0x8d,0xbb,0xf7,0x05,0x07,0x2d,0x52,0xd2,
+  0xd1,0x75,0x16,0x42,0x60,0x90,0x0b,0x45,0x07,0xa8,0x61,0xdb,0x68,0x1f,0x1b,0xa9,
+  0xff,0x6a,0x57,0x41,0x2b,0x8f,0x03,0x56,0x4a,0x41,0x07,0x32,0x0e,0x38,0x08,0xff,
+  0x0d,0xef,0x38,0xe0,0x4b,0xf8,0x99,0xa6,0xf5,0xd3,0x78,0x6b,0x41,0x14,0x36,0x03,
+  0xff,0xa0,0x64,0x9c,0x5a,0x8f,0xf1,0xc7,0x48,0x48,0xcb,0x95,0x3d,0x95,0x4e,0x15,
+  0xe9,0xb9,0xf6,0x27,0x1e,0x53,0x7b,0xbd,0xe9,0x9f,0x12,0x08,0x13,0xb1,0x61,0x6a,
+  0xda,0x9f,0xdb,0x47,0x2e,0xd7,0x82,0xa5,0x5b,0xc0,0xc1,0xa5,0xa0,0xb5,0x1a,0x71,
+  0x94,0x57,0x15,0xb4,0xbc,0x11,0x87,0x87,0x14,0xb4,0xc2,0x38,0xc2,0xe7,0x6f,0xe0,
+  0x77,0x83,0x57,0x58,0xa1,0x2d,0x1e,0x08,0x80,0x91,0xa6,0xb5,0xc7,0xb7,0x86,0xe6,
+  0x70,0xae,0x4e,0xc5,0xf2,0x3e,0x87,0xea,0xa9,0xdc,0x9d,0x5c,0x2f,0xb6,0xbb,0x67,
+  0x61,0x5a,0x87,0x5e,0xb6,0xa2,0x28,0x6e,0x04,0x29,0x88,0xa8,0xb5,0xce,0xd6,0x53,
+  0x7d,0xa3,0x28,0x04,0xb6,0x6d,0x01,0xfb,0xdc,0x88,0x63,0x61,0x41,0x23,0x0e,0x97,
+  0x2a,0x68,0xad,0x10,0x78,0xa6,0xaf,0x29,0xe8,0x29,0xe1,0x48,0x41,0x4b,0x1b,0x71,
+  0xb8,0xa6,0xa0,0xd9,0xbf,0x6c,0x7c,0x9c,0x0f,0x2a,0x1a,0xee,0x35,0xfd,0xb1,0x03,
+  0x95,0xce,0x50,0x0f,0xff,0x56,0x3f,0xfa,0xa0,0x30,0x5a,0x3d,0xa5,0x10,0xe1,0x8a,
+  0xb7,0x71,0x9d,0x77,0x72,0x25,0x56,0x6b,0x13,0xef,0xf5,0xb7,0x70,0xb4,0xe3,0xdf,
+  0xa8,0x5a,0x8f,0x99,0xfe,0xf1,0x80,0x10,0xc0,0xbe,0xa9,0xf6,0xb6,0xf0,0x13,0x7c,
+  0xf6,0x99,0x26,0xc1,0xa4,0xa0,0xad,0xe0,0xc6,0x11,0x2a,0xa6,0xa0,0xf5,0xc6,0x11,
+  0xaa,0xa5,0xa0,0xb5,0xc6,0x11,0xbe,0x64,0x74,0x1c,0x21,0xbb,0xec,0xc6,0xdd,0x34,
+  0xd0,0x85,0x7d,0x5e,0x50,0x22,0x62,0xc3,0x56,0xc7,0x09,0xde,0x7d,0x31,0x9c,0x15,
+  0xcb,0x3e,0xa6,0x94,0xf3,0x3d,0xf7,0x8f,0x22,0x3d,0x9f,0xd5,0xc1,0x15,0xc8,0x3e,
+  0x01,0x1a,0xee,0xb7,0x1a,0xb6,0xe5,0xcf,0x14,0x2b,0x22,0x05,0xed,0xa9,0x17,0xb4,
+  0x34,0x05,0xed,0xef,0x29,0xa4,0x19,0x6a,0xfe,0xab,0x95,0x82,0xd6,0xf2,0xdf,0xc0,
+  0xaa,0xa0,0x85,0xfe,0xfb,0xfc,0xf5,0xb4,0x62,0x12,0xcf,0x36,0xa3,0xc2,0x0a,0x94,
+  0x1e,0xf6,0x91,0xeb,0x6b,0xa3,0xda,0xb5,0x41,0x7a,0x6e,0xf1,0x3b,0xb9,0x25,0xf1,
+  0x5c,0xbb,0xd8,0x53,0xae,0x0d,0x21,0x70,0x75,0x13,0x1b,0xa6,0x93,0x7b,0xe9,0xd8,
+  0x66,0x25,0xff,0xf5,0xa5,0x11,0x87,0x0f,0xe3,0x80,0xc3,0x51,0x05,0x1d,0xc8,0x38,
+  0x42,0xbf,0xab,0xa0,0x17,0xde,0xc8,0xd3,0xe6,0xec,0xe7,0x1b,0x8f,0x9a,0xfe,0xa8,
+  0x81,0xea,0x66,0xa8,0x97,0x8e,0x6f,0xb5,0x0e,0xae,0x28,0xce,0x76,0x97,0x6a,0xec,
+  0xe4,0xee,0x73,0xda,0xc9,0xf5,0x6f,0x1b,0x77,0xcf,0x42,0x07,0xcf,0xb5,0xd9,0xee,
+  0x2e,0x9b,0xd2,0x0f,0xb7,0x74,0xaf,0x21,0x6b,0xff,0x52,0x9e,0x1f,0x00,0xd5,0x09,
+  0x25,0xa8,0xa5,0x36,0x65,0xbe,0x85,0xfe,0x2b,0xdc,0x02,0xf6,0xa3,0x0a,0x7a,0x5f,
+  0xe6,0xaf,0x80,0xe7,0x46,0x58,0x76,0xff,0x95,0xce,0x62,0x78,0xd2,0xa1,0x11,0x96,
+  0xa8,0x11,0x87,0xa0,0x11,0x96,0x73,0x23,0x8e,0x1c,0xff,0x9d,0x2c,0xf3,0x5f,0x5b,
+  0x23,0xac,0xa5,0x5a,0x8d,0xb0,0x5c,0x1a,0x71,0x5c,0xef,0x36,0x8e,0x90,0xfd,0x9f,
+  0x35,0x0f,0xf3,0x5d,0xfb,0xc1,0x2e,0x4c,0x09,0x04,0xa1,0x20,0x32,0xc0,0xbf,0xed,
+  0xe7,0x99,0xaf,0xef,0x15,0xcb,0xe2,0xd2,0x29,0xcd,0x6d,0x5c,0x71,0xa8,0xab,0xec,
+  0xb9,0xbb,0x9d,0x3c,0x77,0xe4,0xc9,0xb6,0x60,0xf4,0xf9,0xb6,0x80,0x9a,0x6b,0x4d,
+  0xff,0x54,0x80,0x09,0xd8,0x43,0xb9,0xb7,0x85,0x37,0x63,0xc9,0xf3,0xdf,0xea,0x4a,
+  0x41,0x07,0x50,0x05,0x9d,0x6e,0xc4,0x21,0x4d,0x41,0x2b,0x36,0xc2,0xf2,0x34,0x8e,
+  0x90,0x7d,0x1f,0xa8,0x5d,0x67,0xf5,0x34,0x63,0x62,0x02,0x08,0x17,0x2c,0xdc,0x6b,
+  0xa9,0xb1,0x0e,0x2d,0xf7,0x79,0x1b,0x57,0xde,0x04,0x43,0xc1,0x76,0x25,0xa5,0x53,
+  0x0b,0xe5,0x59,0x65,0x16,0x3b,0x64,0x24,0xf6,0xdc,0x05,0x39,0x8f,0x35,0x26,0xb6,
+  0xd8,0x58,0xc4,0xf4,0x4f,0x05,0x94,0x1a,0x8a,0x0e,0x52,0xe3,0x4e,0xeb,0xf8,0x16,
+  0x26,0x87,0x10,0x58,0x9a,0x82,0x96,0x9d,0x42,0xd2,0xab,0x82,0xd6,0x4a,0x41,0xab,
+  0x9d,0x42,0x0a,0x30,0x05,0xad,0x73,0x0a,0x29,0x88,0x14,0xb4,0x93,0xff,0xb2,0x08,
+  0xfa,0xf0,0x4a,0xea,0x6b,0xb3,0x92,0x71,0xd3,0x1f,0x31,0x00,0x44,0xb0,0x4f,0x66,
+  0x47,0x23,0x7f,0x44,0x04,0x52,0x3a,0xe5,0xc7,0x4e,0xae,0x4a,0x78,0x6b,0xdf,0xc6,
+  0x15,0xeb,0x59,0x35,0x2d,0xa0,0xd6,0xa3,0xa6,0x7f,0x24,0xa0,0xb4,0x24,0xe2,0x74,
+  0xfa,0xe0,0x88,0xf9,0x0a,0xfc,0xf7,0x98,0x9a,0xff,0x06,0xde,0x88,0x43,0x71,0x1c,
+  0x30,0xc6,0x11,0x5e,0xcf,0x47,0x33,0x2c,0xbd,0x8b,0xdf,0x67,0x3e,0x25,0x10,0xd9,
+  0x66,0x10,0x7a,0xfa,0x3b,0x2c,0xf6,0x30,0xf1,0xad,0x7a,0xaa,0xec,0x6c,0xd7,0xf6,
+  0x58,0xdb,0xfb,0x82,0x15,0x1b,0x34,0xfd,0xf3,0x00,0xa5,0x82,0x88,0x3a,0x4f,0xf0,
+  0x5a,0x88,0x8c,0xff,0xd6,0x6b,0xa5,0xa0,0xd7,0x9a,0x9b,0xc5,0xa0,0xd3,0x88,0x63,
+  0xb3,0x73,0x2f,0x68,0x97,0x2d,0x60,0xa5,0x59,0x0c,0x53,0x24,0x55,0xd0,0x2b,0x26,
+  0x4a,0x7a,0x41,0x17,0xce,0x62,0x10,0x36,0xe2,0x90,0x6f,0x01,0xa7,0xfc,0x97,0xfd,
+  0x71,0x7b,0x16,0x52,0x6f,0x33,0xf6,0x79,0x41,0x39,0xc1,0xbe,0x2b,0xb2,0xa7,0x90,
+  0x53,0xa8,0x2b,0x2f,0x9d,0x0a,0xae,0x7a,0x4a,0xb4,0x8d,0x9b,0xb3,0x93,0xeb,0x9c,
+  0x4f,0x56,0x31,0xdc,0x1d,0xa3,0x9d,0xed,0x47,0x65,0xb1,0x68,0x08,0x54,0x07,0x34,
+  0xdc,0x4b,0x27,0x76,0xd8,0xfd,0x77,0x34,0x04,0x7e,0x45,0x23,0x05,0xad,0xd8,0x08,
+  0x4b,0xab,0x0a,0x3a,0xbd,0xc3,0x12,0x40,0x0a,0x7a,0x93,0xbf,0x8d,0x38,0x3c,0x8f,
+  0x23,0xf4,0x3b,0x05,0xcd,0x5c,0x7b,0xc7,0x3c,0x6a,0x3e,0x42,0x09,0x1c,0x24,0x04,
+  0x65,0x48,0xaa,0x22,0x2b,0xc7,0x82,0x25,0x8d,0xa7,0x8a,0x09,0x72,0x8b,0xf4,0xdc,
+  0xe7,0xfc,0xf5,0xdc,0x91,0x47,0x59,0x5a,0x7b,0x17,0x5b,0x38,0xa1,0x50,0x05,0xb0,
+  0x07,0x35,0x9d,0x39,0x4c,0xc7,0xb7,0x89,0xfc,0xb7,0x30,0x04,0xde,0x98,0xb5,0x60,
+  0x71,0x0a,0x3a,0xff,0x14,0x92,0x6a,0x08,0xbc,0x4f,0xd6,0x88,0x43,0xa7,0x11,0x96,
+  0xb5,0x6d,0x8e,0x5a,0x15,0x96,0xda,0x38,0xe0,0xf5,0x8a,0xe3,0x80,0x9d,0xc6,0x11,
+  0xba,0xa4,0xa0,0x7d,0x1d,0x07,0xcc,0xae,0xbc,0xe9,0x00,0x1f,0x57,0x04,0x40,0xf9,
+  0x12,0x8f,0x50,0x4b,0x4d,0xb6,0x86,0x2a,0xa8,0xd2,0xa9,0x85,0x92,0x7c,0xb2,0x87,
+  0xd2,0x29,0x89,0xd5,0xda,0xb3,0x76,0x19,0x65,0x3d,0x77,0xf4,0x21,0x96,0x16,0xb5,
+  0xa1,0x23,0x74,0xe5,0x43,0x9d,0x27,0xe9,0x38,0x0b,0x7e,0xb7,0xf3,0xd6,0xac,0xf6,
+  0x14,0xb4,0xbf,0x55,0xd0,0xaa,0x29,0x68,0x9d,0x2a,0xe8,0x40,0xc6,0x01,0x07,0xd1,
+  0x88,0x43,0x6d,0x1c,0xb0,0xe7,0x46,0x1c,0x4c,0xec,0x7d,0xea,0x37,0xd3,0x50,0x0f,
+  0xb6,0x7a,0x41,0x25,0x90,0x4c,0x58,0xad,0x75,0x2c,0x0a,0x2e,0xef,0x6d,0xdc,0x7c,
+  0xdb,0x9d,0x27,0x54,0x9e,0xed,0x66,0x1e,0x65,0xfc,0x80,0x15,0xb2,0x58,0x15,0x0d,
+  0x0d,0x76,0xa7,0x32,0xcf,0xdb,0x0b,0xfd,0xb7,0x34,0x55,0xd0,0x0a,0x29,0x68,0xe9,
+  0x38,0x60,0xfd,0x14,0x74,0x10,0xe3,0x80,0x8d,0xa4,0xa0,0xd9,0x3f,0xd9,0x9b,0xb3,
+  0xbf,0xa7,0x51,0x54,0x6b,0x80,0xca,0x82,0x7d,0x93,0xec,0x68,0xa0,0x83,0x2f,0x55,
+  0x95,0xe7,0xe6,0x89,0xda,0xea,0x4c,0xff,0x18,0x40,0x60,0xb0,0x2f,0x57,0xa7,0x0f,
+  0x72,0xff,0x6d,0x18,0xf1,0x5f,0x59,0x0a,0x5a,0xaf,0x11,0x87,0xe2,0x2c,0x86,0xc2,
+  0x46,0x1c,0x2e,0x29,0xe8,0x20,0x1a,0x71,0xe8,0x54,0x41,0x7b,0x48,0x41,0x4b,0x1b,
+  0x71,0xa4,0x2d,0x58,0x9a,0x82,0x2e,0xa8,0xc2,0x5a,0xf1,0x3b,0x7e,0x37,0x3a,0x4e,
+  0xa0,0xc8,0x0a,0x54,0x26,0xec,0x93,0xdd,0xd1,0xc8,0x9f,0x24,0x12,0xcf,0x2d,0xbe,
+  0x09,0x86,0xaf,0xd5,0x53,0xc5,0x79,0x6e,0x8e,0xff,0xee,0x5f,0x6a,0x25,0xb0,0x0b,
+  0x5c,0x89,0xb0,0xcf,0x76,0xcf,0x19,0x3a,0xb1,0x93,0xfb,0xaf,0x43,0x08,0x1c,0x44,
+  0x23,0x0e,0x85,0x71,0x84,0x3a,0x55,0xd0,0x3b,0x47,0x3f,0xf9,0x1a,0xe3,0x08,0x9d,
+  0xab,0xa0,0xd3,0x16,0x3c,0x5d,0x2d,0x04,0x9e,0x9a,0x6f,0xc1,0xaa,0x8d,0x38,0x74,
+  0xaa,0xa0,0x85,0xfe,0xbb,0xe4,0x36,0xfe,0xed,0xe2,0xf4,0x41,0x2b,0x8e,0x73,0xfa,
+  0xa0,0xb2,0x61,0x8f,0xa9,0x66,0x3a,0xb2,0x2a,0x80,0x26,0x18,0x45,0x6f,0xe3,0x3a,
+  0xec,0xe4,0x3a,0xf8,0xac,0xc4,0x6a,0xf3,0x9d,0x97,0x87,0x0f,0x29,0x61,0x2e,0x70,
+  0x45,0x12,0x19,0xe0,0x83,0xc0,0x5c,0xfd,0xd7,0xaa,0xd7,0xaa,0x82,0x5e,0xeb,0x35,
+  0x05,0xed,0xbc,0x05,0x5c,0x66,0x29,0x68,0x97,0x53,0x48,0xfe,0x8d,0x03,0x66,0x6f,
+  0xde,0xb0,0xdd,0x1a,0xec,0xc6,0x56,0x2f,0xa8,0x0a,0x58,0xa4,0xd0,0xdf,0xce,0x1f,
+  0x2c,0x4e,0x63,0xfb,0x9c,0xc6,0x19,0x48,0xaa,0xa7,0xbc,0xa6,0x94,0x73,0x6c,0x57,
+  0x1a,0xde,0x7a,0xb5,0xdd,0xf4,0xb3,0xeb,0x69,0xda,0xff,0x12,0x3a,0xe7,0x54,0x1a,
+  0x94,0xb4,0x5a,0x8f,0xf2,0xc1,0x73,0xdc,0x7f,0xf3,0x2d,0x58,0xa1,0x0a,0xba,0xbc,
+  0xc6,0x11,0x96,0x4b,0x23,0x0e,0xd7,0x2d,0x60,0x66,0xc4,0xcb,0xee,0xa1,0x7d,0x4b,
+  0x78,0x91,0x55,0x32,0x61,0xfa,0x03,0x04,0x40,0x29,0x21,0x2b,0x3a,0x40,0x35,0xeb,
+  0x6c,0xce,0xeb,0x3c,0x42,0x28,0x7c,0xdb,0xb8,0xae,0x86,0xfb,0xb4,0x83,0x66,0x8f,
+  0xea,0x69,0x6a,0x6f,0x30,0x7d,0xff,0x81,0xaf,0xf4,0xb5,0xd1,0xc9,0xdd,0x55,0xe3,
+  0xbf,0xe5,0x3f,0x0e,0x78,0xf9,0x7d,0x6c,0x15,0x56,0x57,0x23,0x62,0x5e,0x50,0xb5,
+  0x50,0x6c,0x98,0x3f,0x79,0xf2,0xcc,0x37,0xac,0xa5,0x53,0xc5,0x79,0xae,0x4d,0xec,
+  0x79,0x75,0x60,0xa9,0x85,0x42,0xe8,0x8a,0x21,0x16,0xb1,0xce,0x1c,0x4c,0xfb,0x6f,
+  0xda,0x82,0x9d,0x53,0xd0,0x25,0xaa,0x82,0x96,0xa6,0xa0,0x03,0x68,0xc4,0xf1,0x8a,
+  0x5a,0x23,0x0e,0xb3,0x55,0xd0,0xec,0x3f,0x5f,0x99,0x69,0x35,0xec,0xa0,0xd8,0x90,
+  0xe9,0xcf,0x0d,0x00,0xa6,0x89,0x0e,0xf1,0x67,0x51,0xbe,0xed,0x16,0x5f,0x3d,0xe5,
+  0xd0,0x04,0xc3,0x07,0xdb,0x9d,0x93,0x91,0xb6,0xed,0x66,0xc4,0xfe,0xb3,0xa3,0xd1,
+  0xf4,0xad,0x07,0x3e,0xd1,0x79,0x92,0x9b,0x6f,0x8e,0xff,0xa6,0x2c,0xb8,0x61,0x87,
+  0x52,0x15,0x74,0x4e,0x23,0x0e,0x97,0x10,0x58,0x63,0x1c,0x70,0xce,0x1c,0xb1,0x40,
+  0x1a,0x71,0x78,0x18,0x47,0xe8,0x6b,0x23,0x0e,0x79,0x0a,0x5a,0xd4,0x88,0x83,0xbd,
+  0x4f,0xed,0x5a,0xab,0xb7,0x85,0xe7,0xdf,0x00,0x00,0x16,0x2f,0x5c,0xb1,0xea,0x37,
+  0xfb,0xb3,0x93,0x2b,0xda,0xc6,0xf5,0x29,0xc2,0x2d,0xd8,0xc6,0x55,0xb4,0x5a,0x27,
+  0x1d,0x5e,0x65,0xfa,0xbe,0x03,0x3f,0x18,0x1e,0xa0,0x53,0xfb,0xd2,0xfe,0xeb,0x9c,
+  0x82,0x0e,0xba,0x0a,0xba,0x7c,0xc6,0x11,0x06,0xd0,0x88,0xe3,0x65,0xa5,0x71,0x84,
+  0xd6,0x8e,0xb9,0x56,0xd7,0x49,0xf4,0xa0,0x03,0x20,0x9f,0xe8,0x20,0x3f,0x05,0xe9,
+  0x5f,0x56,0xd9,0xa7,0xd2,0x29,0xe5,0xd8,0x56,0xd1,0x73,0xed,0x0f,0x2b,0xf6,0x56,
+  0x83,0x5d,0xa6,0xef,0x3b,0x28,0x8e,0x64,0xd2,0x6a,0x39,0x9a,0x35,0x5f,0xbd,0x14,
+  0xb4,0x9a,0xff,0x6a,0xf5,0x82,0x36,0xe8,0xbf,0xc1,0x55,0x41,0xab,0xfa,0xaf,0x43,
+  0x0a,0x9a,0x05,0xc2,0xeb,0x1e,0xa6,0x53,0xfb,0xe1,0xbc,0x00,0x38,0x41,0xb1,0x08,
+  0x4f,0xc1,0xed,0x2a,0x08,0x7e,0x2b,0xc9,0x73,0xf3,0x54,0xb7,0x11,0x79,0xb0,0xb2,
+  0x86,0x06,0x3a,0x53,0xc1,0xef,0x5e,0x91,0xff,0xda,0x2d,0x58,0xb6,0x05,0x7c,0x4c,
+  0xab,0x11,0x47,0x70,0xe3,0x08,0xfd,0x6d,0xc4,0xa1,0x98,0x82,0x0e,0xb2,0x0a,0x9a,
+  0xbd,0x1b,0xbb,0x0f,0x43,0xbd,0xa6,0x3f,0x29,0x00,0x84,0x1d,0x8a,0x47,0xa9,0x7e,
+  0x0b,0x3f,0x5e,0xa4,0x32,0xce,0xa0,0x58,0xdb,0x9d,0xa3,0xb0,0x93,0xeb,0xd9,0x73,
+  0x67,0x65,0x55,0x68,0xbb,0xa3,0xcf,0x28,0x6b,0xeb,0xd3,0xd6,0x30,0x9e,0x0c,0x65,
+  0x0b,0xfb,0xb8,0x36,0x1f,0xa1,0x93,0xb9,0xfe,0x2b,0x4e,0x41,0x17,0x6c,0x01,0xbb,
+  0x8d,0x23,0x2c,0xf4,0x5f,0xc7,0x71,0x84,0x9a,0x8d,0xb0,0x3c,0x8c,0x23,0xd4,0x3a,
+  0x85,0x14,0xdc,0x38,0x42,0x59,0x23,0xac,0xc2,0x71,0x84,0xbc,0x99,0xd5,0xb3,0xa9,
+  0xb9,0x45,0x38,0xeb,0x07,0x80,0x12,0x3c,0x0a,0x6e,0xd8,0x41,0x3b,0x16,0x04,0xe3,
+  0xb9,0xcf,0xf8,0x50,0x3a,0xa5,0x62,0xbb,0xce,0x9e,0x6b,0xd3,0x4c,0xae,0x13,0x3b,
+  0x4c,0xdf,0x72,0xe0,0x89,0x91,0x6e,0x57,0xa7,0xf6,0x73,0x15,0xfa,0x6f,0xe3,0x2e,
+  0x63,0x29,0x68,0x9f,0x1b,0x71,0xcc,0xf7,0x3a,0x8e,0x50,0x96,0x82,0xd6,0x1b,0x47,
+  0xa8,0xd9,0x88,0x63,0xdd,0x34,0xeb,0xf8,0x36,0x0b,0xfb,0x3b,0x00,0xe8,0x12,0x1b,
+  0xb6,0xd8,0x13,0x2c,0x90,0xd2,0xa9,0x39,0xfe,0x59,0xad,0xfd,0x3b,0x7f,0x46,0x4e,
+  0x56,0x6b,0x3f,0x9a,0x91,0x51,0xea,0x01,0xc5,0x9e,0x6f,0x51,0x9c,0x83,0x28,0x3f,
+  0xf8,0x17,0xc5,0xd3,0x07,0x6d,0xfe,0xeb,0x9c,0x82,0x56,0x3c,0x85,0x14,0xc8,0x41,
+  0xe0,0xa5,0x1a,0x29,0x68,0xf9,0x29,0xa4,0xb9,0x1a,0xfe,0x9b,0xb6,0x60,0x7f,0xc7,
+  0x01,0x2b,0xa4,0xa0,0x5f,0x9e,0x68,0xed,0x59,0xc8,0x2b,0x9c,0xd1,0xe2,0x06,0x00,
+  0x6f,0xc4,0x23,0x54,0xbf,0xa5,0xa4,0x07,0x72,0x8b,0xd9,0xc6,0x75,0xf1,0xdc,0x74,
+  0x14,0x50,0xa8,0xcc,0x73,0xe9,0x09,0x3a,0x73,0xd8,0xf4,0xed,0x06,0xba,0x10,0x1f,
+  0x32,0xd8,0xb4,0x9f,0xab,0xd0,0x7f,0x7d,0x68,0xc4,0xe1,0x32,0x0e,0xb8,0xc8,0x71,
+  0x84,0x01,0x34,0xe2,0xd0,0xaa,0x82,0x56,0xdd,0x02,0xf6,0x50,0x05,0x3d,0x99,0x1f,
+  0xec,0x6d,0xad,0x43,0x4b,0x0d,0x00,0x8a,0x84,0x92,0x09,0xf6,0x74,0xb2,0xb6,0xcf,
+  0xaf,0x50,0xdb,0xb5,0x69,0xd7,0x02,0xf4,0xe2,0x28,0x33,0x22,0xfd,0x74,0xe6,0x10,
+  0x35,0x1d,0x48,0xfb,0x6f,0xda,0x82,0xf7,0xe4,0xfa,0xaf,0x62,0x0a,0x5a,0xad,0x17,
+  0x74,0xce,0x16,0xf0,0x6a,0x1d,0xff,0x75,0x1e,0x47,0xb8,0x47,0xad,0x11,0xc7,0x76,
+  0x9d,0x59,0x0c,0x39,0x5b,0xc0,0x2e,0x8d,0x38,0x3c,0xf8,0xaf,0x6b,0x0a,0x9a,0xbd,
+  0xf6,0xd0,0xcb,0xbc,0x93,0x24,0x00,0xc0,0x0f,0x78,0x39,0x56,0xdd,0x26,0xe7,0xc8,
+  0x57,0xbf,0x74,0x4a,0xb7,0x7a,0x4a,0x7d,0x1b,0xf7,0x95,0x99,0xb9,0x3e,0xfb,0xc4,
+  0xa8,0x44,0x86,0x5b,0xa8,0xd6,0x63,0xa6,0x6f,0x36,0x50,0x85,0x28,0x69,0xb5,0x37,
+  0xf0,0xe4,0x33,0x53,0x8e,0xff,0x16,0x9d,0x82,0x56,0x6c,0x84,0x95,0x0e,0x81,0x95,
+  0xb6,0x80,0xf5,0xaa,0xa0,0x03,0x49,0x41,0xeb,0x34,0xe2,0xf0,0x90,0x82,0x5e,0x39,
+  0x99,0xb6,0xcf,0xb5,0x4e,0x1f,0xb2,0x50,0x67,0x05,0x80,0xbf,0x44,0x07,0xd8,0xb3,
+  0x48,0xb6,0x93,0xeb,0xcb,0xe1,0xa0,0xe2,0xb6,0x71,0x73,0x3c,0x57,0xc1,0x76,0x37,
+  0xe6,0x6a,0xdf,0x12,0x74,0x80,0x2f,0x17,0x68,0x38,0x15,0xfc,0x66,0xfc,0x57,0x25,
+  0x05,0x6d,0x6b,0x84,0xa5,0xd0,0x88,0x63,0xa3,0x5a,0x23,0x8e,0x95,0xda,0x29,0xe8,
+  0x7d,0xb2,0x71,0x84,0x85,0x8d,0xb0,0xdc,0x0e,0x02,0xcf,0xf1,0x3f,0x05,0x9d,0xd3,
+  0x08,0x4b,0xa1,0x0a,0x7a,0xf5,0x83,0x56,0xed,0x5a,0xab,0xaf,0xdd,0xf4,0x87,0x02,
+  0x80,0x0a,0x25,0xd2,0x6f,0x1d,0x59,0x55,0x81,0x9e,0xbb,0xd1,0x76,0x28,0x83,0xbd,
+  0xbc,0xbf,0xd5,0xf4,0x8d,0x06,0x0a,0x10,0x51,0xfb,0xf1,0xb4,0xf9,0xda,0xfd,0x57,
+  0x5c,0x05,0xed,0x6b,0x23,0x0e,0xdf,0xc6,0x01,0xeb,0x37,0xe2,0x48,0x59,0x70,0xb8,
+  0x1a,0x71,0x30,0x6d,0xfa,0x83,0xd5,0x7e,0x1c,0x5d,0x35,0x00,0x08,0x14,0x8a,0xf4,
+  0xd3,0xfe,0xa5,0xfe,0x55,0x2c,0x2b,0x6f,0xe3,0x3a,0xee,0xe4,0xaa,0x65,0x95,0x25,
+  0xb6,0xfb,0x78,0x8e,0x58,0x98,0x0f,0x42,0x0f,0x45,0x6c,0xc1,0xaf,0xaa,0xff,0x06,
+  0x90,0x82,0xd6,0x39,0x85,0xa4,0x9c,0x82,0xf6,0x75,0x16,0x43,0x20,0xa7,0x90,0x46,
+  0x2d,0x78,0xe3,0xe3,0x7c,0x38,0x72,0x2c,0x62,0xfa,0xe3,0x00,0x40,0x55,0x40,0x91,
+  0x41,0x3a,0xb0,0xb4,0xd2,0x3c,0xd7,0xfe,0x14,0xda,0x34,0x9d,0xd0,0xa5,0x27,0xe4,
+  0xb0,0xe0,0xb7,0xe3,0x44,0x8e,0xff,0xe6,0x6c,0x01,0xab,0x34,0xc2,0x2a,0xb2,0x11,
+  0x47,0xd1,0x8d,0xb0,0x02,0x69,0xc4,0xa1,0x33,0x8e,0x50,0xaf,0x11,0x56,0x41,0x0a,
+  0x9a,0x69,0xe7,0x02,0xab,0xed,0x18,0x8a,0x9c,0x01,0x28,0x25,0xbc,0xd7,0xdf,0xbe,
+  0x17,0x8b,0x2a,0x9d,0xca,0xf7,0x5c,0x61,0xe9,0x94,0x7e,0xf5,0x94,0xc0,0x73,0xa7,
+  0xa7,0x25,0x36,0xdc,0xd1,0x27,0x4f,0xae,0xac,0xfa,0xad,0xa6,0xef,0x31,0x70,0x25,
+  0xd2,0x6f,0x9d,0x39,0xcc,0xfd,0x57,0x23,0x04,0xf6,0xb5,0x0a,0xba,0x76,0x6d,0x50,
+  0xe3,0x08,0xf7,0x48,0xc7,0x11,0x6a,0x35,0xe2,0x98,0x25,0x0b,0x81,0xa7,0x7b,0x09,
+  0x81,0xd9,0xef,0xaf,0xdb,0x88,0xae,0x1a,0x00,0x98,0xa1,0xb7,0xc5,0x62,0x4f,0x89,
+  0x60,0xb7,0x71,0x65,0xb6,0xeb,0xb2,0x8d,0x9b,0x95,0x9b,0xcf,0xe6,0x7f,0xe7,0xcf,
+  0x88,0x3d,0xc7,0xa2,0x83,0xa6,0x6f,0x31,0x70,0x80,0xf8,0x99,0x5f,0xe6,0xbf,0x69,
+  0x0b,0xce,0x86,0xc0,0xae,0xa7,0x90,0xc2,0x92,0x82,0x56,0x6c,0xc4,0xa1,0x98,0x82,
+  0xd6,0xaa,0x82,0x96,0x8d,0x03,0x56,0xf4,0xdf,0xed,0x73,0x88,0x85,0xbd,0xd8,0xed,
+  0x05,0xc0,0x18,0x44,0x5d,0xa7,0xf8,0x57,0xf1,0x1c,0xdb,0x55,0x49,0x29,0x17,0x7a,
+  0xae,0x66,0x9c,0x2b,0xb7,0x5d,0x49,0x78,0xeb,0x68,0xbb,0x59,0x3d,0x46,0x4d,0x07,
+  0x4c,0xdf,0x61,0x20,0x86,0xef,0x36,0x36,0xd7,0x88,0xfc,0x57,0xf9,0x14,0x92,0x97,
+  0x46,0x1c,0xeb,0xb5,0xab,0xb0,0xc2,0xdf,0x88,0x43,0x77,0x16,0xc3,0xfa,0x47,0xd8,
+  0x92,0xad,0xe1,0x3e,0xe4,0x9c,0x01,0x30,0x0c,0xfb,0x3b,0xd8,0xd9,0x48,0xdb,0xe6,
+  0x84,0x74,0x1b,0x57,0xdb,0x73,0x73,0xb5,0x7d,0x2e,0xa1,0x17,0x47,0x38,0xe9,0x69,
+  0xb6,0x9a,0x8f,0x38,0xfa,0xaf,0x66,0x23,0x2c,0x13,0xe3,0x80,0xa5,0x8d,0x38,0xc2,
+  0x37,0x0e,0x78,0xed,0x23,0xb4,0x63,0x1e,0xb5,0x1e,0x85,0xf3,0x02,0x10,0x16,0x88,
+  0xa8,0xa5,0x96,0x1f,0x47,0xaa,0x0c,0xcf,0x1d,0x79,0xe0,0x8c,0x8a,0x3f,0xe4,0x41,
+  0xd8,0x88,0x47,0xb9,0x0b,0xd8,0xfd,0x37,0x67,0x0b,0xd8,0x54,0x0a,0x7a,0x75,0xde,
+  0x41,0x60,0xdf,0xaa,0xa0,0x77,0x69,0x55,0x41,0xcb,0xc6,0x11,0xa6,0xf3,0x4e,0x6a,
+  0x8d,0x38,0xd6,0x4d,0x4b,0x1f,0x04,0x66,0xbf,0xa1,0x66,0xad,0x35,0xd8,0x69,0xfa,
+  0x67,0x0f,0x00,0xc8,0x81,0x92,0x09,0xeb,0xc4,0x2e,0xda,0xfc,0x54,0x41,0x01,0x95,
+  0xce,0x81,0x5c,0x69,0xf5,0x94,0x63,0x01,0x95,0x67,0xcf,0x9d,0x96,0x55,0xc6,0x73,
+  0xd9,0xa3,0x26,0x23,0xf6,0x9d,0x7f,0xf7,0xf3,0xe8,0xe4,0x13,0x3a,0xfa,0xdb,0xad,
+  0x96,0x1a,0xee,0xbf,0x45,0x86,0xc0,0x0d,0x0e,0x55,0xd0,0x6e,0x8d,0x38,0x02,0x48,
+  0x41,0xef,0x53,0x4c,0x41,0x2b,0x8d,0x03,0x0e,0x24,0x05,0xbd,0x6d,0x0e,0xbf,0xe1,
+  0xb1,0x61,0xd3,0x3f,0x78,0x00,0x80,0x88,0x78,0xd4,0x62,0x4f,0x27,0x1f,0x9b,0x60,
+  0xa8,0xef,0xe4,0xea,0x85,0xb7,0xd3,0x6c,0x72,0xf0,0x5c,0xbb,0xd8,0xaf,0x76,0x9d,
+  0x34,0x7d,0x73,0x41,0x16,0x4a,0x26,0xf9,0x81,0x17,0x66,0x07,0x23,0x16,0x2c,0x0e,
+  0x81,0x5d,0xab,0xa0,0x65,0x29,0x68,0xf3,0xe3,0x08,0x75,0x1a,0x71,0xe8,0x1d,0x04,
+  0xf6,0xd0,0x88,0x63,0xff,0x52,0xea,0x6b,0x43,0xce,0x19,0x80,0x50,0x13,0x1d,0xa4,
+  0x03,0xcb,0xfc,0x4e,0x29,0xfb,0xe2,0xb9,0x8f,0x08,0x94,0xe7,0xb3,0xce,0xb2,0x0e,
+  0xaf,0x34,0x7d,0x67,0x41,0x16,0x7e,0x2e,0xbb,0xa5,0x36,0xeb,0xbf,0x29,0x0b,0xd6,
+  0x3c,0x85,0xa4,0xd8,0x08,0x2b,0xd8,0x2a,0x68,0x3f,0xc6,0x01,0x07,0xdc,0x88,0x83,
+  0x4f,0xc4,0xde,0x65,0x25,0x50,0xe4,0x0c,0x40,0x19,0x40,0x91,0x01,0xfe,0xc4,0x08,
+  0xdf,0x36,0xae,0xae,0xe7,0xe6,0x1c,0xb5,0x60,0x31,0xf8,0x70,0xbf,0xe9,0x5b,0x0b,
+  0x52,0x24,0x93,0xd4,0xd9,0x28,0xf7,0xdf,0x12,0x54,0x41,0x97,0xc1,0x38,0xc2,0x82,
+  0xf6,0x38,0xea,0x29,0xe8,0x8d,0xd3,0xd9,0x9f,0x6e,0x75,0x22,0xf3,0x03,0x40,0x39,
+  0x41,0xfd,0x1d,0xb4,0x73,0x9e,0x6f,0xdb,0xb8,0x4a,0xb6,0xab,0xb0,0x8d,0x2b,0xd1,
+  0x54,0x9b,0x1e,0x2c,0x94,0xd5,0xb8,0xdb,0xf4,0x7d,0x05,0x1c,0x8a,0x0e,0xf2,0xca,
+  0xab,0x02,0xff,0x75,0xdd,0x02,0xde,0x27,0x4a,0x41,0x0b,0x1a,0x71,0x88,0x1a,0x61,
+  0x39,0x37,0xe2,0xc8,0xf1,0xdf,0xb5,0x3e,0xf9,0xaf,0x87,0x46,0x58,0x9e,0xc7,0x11,
+  0x0a,0x67,0x31,0xa4,0xfe,0x6e,0xb2,0xb0,0xf7,0xe8,0x06,0x6b,0xb0,0xdb,0xf4,0x4f,
+  0x1b,0x00,0xa0,0x09,0x91,0xd5,0x71,0x82,0x9f,0x48,0x52,0xea,0x3d,0x55,0x4c,0xa8,
+  0x5b,0xe0,0xb9,0x76,0xdb,0x55,0x8a,0x70,0xdd,0x3c,0x37,0x47,0x5b,0x9f,0x46,0x15,
+  0x56,0x18,0xa0,0xde,0xe6,0x94,0xf9,0xd6,0x2a,0x84,0xc0,0x2a,0x55,0xd0,0x01,0xa4,
+  0xa0,0x8f,0x88,0xc6,0x01,0x17,0xdb,0x08,0x2b,0x88,0x71,0x84,0x0e,0x8d,0x38,0xb6,
+  0xcf,0x25,0x76,0x3f,0x51,0x6a,0x05,0x40,0x99,0xc2,0x2c,0xb8,0xb9,0x96,0xff,0x05,
+  0x97,0xf6,0x9e,0xd2,0x4a,0x29,0x7b,0xa8,0x9e,0xd2,0x0f,0x75,0x05,0x4d,0xe6,0xb9,
+  0xa6,0x52,0x47,0x83,0xe9,0xdb,0x5a,0xf5,0x24,0x63,0xd4,0x56,0xef,0xe4,0xbf,0x1a,
+  0x55,0xd0,0xa5,0x4d,0x41,0x2b,0x36,0xc2,0x0a,0x30,0x05,0xed,0xd6,0x0b,0x3a,0x77,
+  0x9f,0x88,0x05,0xe0,0xbc,0xd4,0x2a,0x69,0xfa,0x27,0x0d,0x00,0x28,0x82,0x64,0x82,
+  0x1f,0xeb,0x10,0xda,0xae,0xb6,0xe7,0x16,0xb9,0x8d,0xfb,0x90,0xdc,0x67,0xc5,0x9e,
+  0x6b,0xd3,0xaa,0x07,0x68,0xff,0x8b,0x28,0x01,0x35,0xcc,0x40,0x17,0xb5,0xd5,0xd9,
+  0xfc,0xb7,0x56,0xb5,0x0a,0x3a,0x34,0x8d,0x38,0xc2,0x3b,0x8e,0x90,0xfd,0x1e,0xb6,
+  0xe4,0x24,0x92,0x3c,0x00,0x54,0x04,0x94,0xe4,0xbd,0x08,0x84,0x27,0x0a,0x4b,0x51,
+  0x3d,0xe5,0x93,0xed,0x66,0xb4,0xfa,0x41,0x0c,0x16,0x37,0x49,0x32,0x69,0x75,0x9d,
+  0x64,0xfe,0x9b,0x6b,0xc1,0xee,0xfe,0xab,0x9c,0x82,0x6e,0xd0,0x9a,0xc5,0xb0,0x51,
+  0xe4,0xbf,0xf6,0x2d,0x60,0x59,0x23,0x0e,0xbd,0x46,0x58,0x0b,0x0b,0x1a,0x71,0x08,
+  0x0e,0x02,0x8b,0xfc,0xd7,0xb9,0x11,0xc7,0x2b,0xb9,0x8d,0x38,0xd8,0xfb,0xa3,0xab,
+  0x15,0x00,0x95,0x05,0x2f,0x87,0xde,0xb3,0xb8,0x84,0xdb,0xb8,0x0a,0x29,0x65,0x47,
+  0xcf,0x9d,0x92,0x96,0xdd,0x73,0xb3,0x4a,0x4d,0x18,0xaf,0x5d,0x6f,0xfa,0x8e,0x56,
+  0x31,0x91,0x41,0x6a,0x3b,0xe6,0xe8,0xbf,0x2e,0x29,0x68,0x61,0x15,0xb4,0x38,0x04,
+  0x96,0x6d,0x01,0x07,0x3d,0x8e,0xd0,0xad,0x11,0x56,0x30,0xe3,0x08,0x5f,0x99,0x69,
+  0x1d,0x59,0xcd,0x07,0xa9,0x00,0x00,0x2a,0x8f,0xde,0x16,0x5e,0x8b,0x15,0x96,0x6d,
+  0xdc,0xbc,0xf0,0x76,0x8a,0x4d,0xb9,0x56,0x5b,0xa8,0x95,0xbf,0xa7,0x0d,0xd3,0xad,
+  0xc8,0x80,0xe9,0x1b,0x5a,0x95,0x10,0x51,0x4f,0x8b,0xc8,0x7f,0x95,0x53,0xd0,0xa7,
+  0x84,0x55,0xd0,0x82,0x71,0xc0,0x39,0x16,0x5c,0xaf,0xd3,0x88,0xa3,0xf8,0x14,0xf4,
+  0x3e,0xfd,0x2a,0xe8,0x62,0x7a,0x41,0x6f,0x9e,0x65,0x9d,0xd8,0xc9,0xc7,0x38,0x02,
+  0x00,0x2a,0x13,0xa2,0xd6,0x3a,0x5e,0xff,0x5c,0xa6,0x9e,0x9b,0xa3,0xfb,0xad,0xa6,
+  0xfd,0xa6,0xef,0x67,0x35,0x42,0xc9,0x04,0xb5,0x37,0xa4,0xfc,0x57,0x12,0x02,0x7b,
+  0x3a,0x08,0x1c,0xfa,0x46,0x1c,0x01,0x8c,0x23,0xb4,0xd8,0x6f,0xee,0x68,0x44,0x55,
+  0x3f,0x00,0x15,0x4e,0x32,0xc9,0x1b,0xed,0xda,0x33,0xcc,0x25,0xde,0xc6,0xcd,0xdb,
+  0xc9,0xd5,0xb6,0x5d,0x9b,0xb6,0xcf,0x45,0x75,0x68,0xe9,0xa1,0xe1,0x5e,0x6a,0x3f,
+  0xae,0xe2,0xbf,0xde,0xc7,0x11,0x2a,0xfa,0xef,0x31,0xc5,0x53,0x48,0x81,0xa5,0xa0,
+  0x8b,0xf7,0xdf,0x6d,0x73,0xf8,0x85,0x0d,0xf5,0x9a,0xfe,0xa9,0x02,0x00,0x4a,0x01,
+  0xef,0xd9,0x7b,0x74,0x1d,0x9f,0x5f,0x66,0xa4,0x74,0x4a,0xea,0xb9,0x2e,0x86,0x5b,
+  0xa8,0x01,0x8c,0x80,0x29,0x39,0x3d,0xcd,0xdc,0x7f,0xd3,0x16,0x2c,0x4a,0x41,0xfb,
+  0xda,0x88,0x23,0xa7,0x0a,0xba,0xbe,0x34,0xe3,0x08,0x8b,0xae,0x82,0x56,0x4c,0x41,
+  0xef,0x7c,0xd6,0x3a,0xb9,0x8b,0xa2,0x38,0xde,0x0b,0x40,0x15,0x41,0xf1,0x08,0x7f,
+  0xaa,0x14,0xd3,0x04,0xc3,0x63,0xe9,0x94,0xa7,0x38,0x37,0xad,0xc9,0x69,0xbd,0x3c,
+  0x29,0xab,0xa3,0x1b,0x4d,0xdf,0xcb,0xea,0x82,0x12,0x31,0x9e,0x7c,0xce,0xfa,0x6f,
+  0xca,0x82,0xd3,0x5d,0xb0,0xb4,0xb6,0x80,0x8b,0x19,0x47,0xf8,0x8a,0x5a,0x08,0xbc,
+  0xb6,0xa0,0x11,0x87,0xe2,0x38,0xc2,0xa5,0x45,0x37,0xe2,0x98,0x2f,0x0f,0x81,0x79,
+  0x9d,0x73,0x2d,0xbb,0xa1,0xa6,0x7f,0xa4,0x00,0x80,0x52,0x43,0xfd,0xed,0xb4,0x65,
+  0xb6,0x3f,0x3b,0xb9,0xe2,0x6d,0x5c,0x3f,0xc2,0xdb,0x97,0x27,0xdb,0x64,0xb3,0xdd,
+  0x97,0x7f,0x97,0xd6,0xc6,0x19,0x14,0x8b,0x98,0xbe,0x97,0xd5,0xc4,0x60,0x77,0xda,
+  0x7c,0x3d,0xa6,0xa0,0x0f,0x04,0x92,0x82,0xae,0x13,0x9d,0x42,0x2a,0x4d,0x0a,0x7a,
+  0xd7,0xf3,0xea,0x29,0x68,0x6b,0xdb,0xe8,0x29,0xa4,0x7d,0x2f,0x50,0xcf,0x19,0xec,
+  0x9e,0x00,0x50,0xa5,0x10,0x51,0x5b,0x3d,0xaf,0xbf,0xf2,0xa1,0x7a,0xca,0x97,0xf0,
+  0x56,0x68,0xbb,0x93,0xc4,0xb6,0x9b,0xd1,0xca,0x49,0xd4,0x5c,0x6b,0xfa,0x56,0x56,
+  0x0d,0xbc,0xf2,0xf9,0x4c,0xd6,0x7f,0xd5,0x53,0xd0,0x2a,0xe3,0x90,0x9c,0x1b,0x61,
+  0x79,0x1f,0x47,0x68,0x64,0x16,0x83,0x7b,0x0a,0x9a,0xa9,0x66,0x1d,0x0d,0xf7,0xe1,
+  0x84,0x2f,0x00,0x55,0x4d,0x32,0xc1,0x13,0x80,0x6b,0x45,0x3b,0xbc,0x41,0x97,0x4e,
+  0x09,0x3c,0x77,0x92,0x83,0x0a,0x3c,0x97,0x69,0xf9,0xc4,0xac,0x76,0x3c,0x8b,0x47,
+  0x59,0x69,0xa0,0x44,0x8c,0xb7,0x13,0xef,0x68,0x50,0x0d,0x81,0xcb,0x6b,0x1c,0xb0,
+  0x62,0x23,0x8e,0x62,0xc6,0x11,0xb2,0x60,0xf9,0xd4,0x5e,0x34,0xb6,0x02,0x00,0x70,
+  0x28,0xc9,0xb7,0xc6,0xd6,0x4e,0x0d,0x93,0xe7,0x8a,0x0c,0x37,0xcf,0x73,0xb3,0xba,
+  0x97,0xff,0x52,0x3f,0x7a,0x61,0x95,0x02,0x1a,0xea,0xe1,0xe6,0x9b,0xe3,0xbf,0xf5,
+  0xda,0xa7,0x90,0xf2,0x1b,0x61,0x39,0x87,0xc0,0xe9,0x46,0x58,0xdb,0xd4,0xaa,0xa0,
+  0x03,0x4b,0x41,0xef,0x93,0xa6,0xa0,0x1d,0x1b,0x61,0xe5,0x84,0xc0,0xfb,0x96,0x50,
+  0xeb,0x51,0x42,0xce,0x19,0x00,0x30,0x0a,0x9f,0x22,0xc7,0x1e,0x1d,0xf6,0xd2,0x29,
+  0x69,0xef,0x29,0x6d,0xdb,0x9d,0x9c,0x23,0x77,0xdb,0x5d,0x91,0xab,0xac,0xd5,0xde,
+  0x67,0xd3,0xbd,0x39,0xaa,0x59,0x63,0xfa,0x2e,0x56,0x01,0xa9,0xe4,0x73,0x7e,0xfc,
+  0x5b,0x6c,0x0a,0x5a,0xa5,0x11,0x47,0x41,0x08,0xec,0x6f,0x23,0x8e,0x92,0xa4,0xa0,
+  0x89,0xfd,0x11,0xdd,0xa7,0x91,0xa8,0x01,0x00,0xe4,0xc1,0x37,0xf5,0x36,0xce,0xf0,
+  0xff,0x70,0x90,0xfa,0x36,0x2e,0xb7,0xdd,0x89,0x69,0xe5,0x47,0xb8,0x0e,0x9e,0x6b,
+  0xd7,0xba,0x69,0x38,0xc4,0x11,0x34,0x14,0x8f,0xf2,0x1e,0x11,0x23,0xfe,0x2b,0x4a,
+  0x41,0x7b,0x6a,0x84,0x25,0x4a,0x41,0x57,0x5c,0x23,0x0e,0x9e,0x62,0xe2,0x03,0x7c,
+  0x61,0xbe,0x00,0x80,0x42,0x88,0x17,0xa6,0xf2,0x54,0xb3,0xb9,0x6d,0xdc,0xbc,0xac,
+  0xb2,0xba,0x96,0xdd,0xcb,0xdd,0xb9,0xf9,0xb0,0xe9,0x7b,0x58,0xe1,0xf0,0x1e,0x11,
+  0x1d,0x27,0x5c,0xfc,0xd7,0x64,0x23,0x0e,0xd5,0x71,0xc0,0x6b,0xd4,0xfd,0xd7,0x9f,
+  0x46,0x1c,0x3b,0x17,0x50,0xc3,0x36,0xfe,0xd5,0x05,0x00,0x00,0x9c,0xa0,0x24,0x7f,
+  0x76,0xf1,0xb4,0x73,0x99,0x78,0x6e,0xae,0xac,0xad,0xcf,0xe0,0x34,0x47,0x80,0x10,
+  0x59,0x7d,0x2d,0x56,0xa7,0x28,0xfe,0x2d,0x32,0x05,0xad,0x3c,0x0e,0x38,0xc0,0x71,
+  0x84,0xaa,0x29,0x68,0xcd,0x5e,0xd0,0xec,0x25,0x6c,0xa5,0xf8,0x58,0x02,0x00,0x64,
+  0xb0,0x6f,0xe9,0xfc,0x31,0xa2,0xbe,0x93,0x2b,0xb5,0x5d,0xf1,0x36,0xae,0xeb,0x4e,
+  0xae,0xaa,0xed,0xde,0x93,0xd5,0x4b,0x77,0x73,0x2d,0xbb,0x8f,0x7a,0x9a,0x4d,0xdf,
+  0xc2,0xca,0x25,0x99,0xa0,0xae,0x93,0x23,0xfe,0xeb,0x96,0x82,0xf6,0xd0,0x88,0xa3,
+  0xa8,0x46,0x58,0x85,0xe3,0x08,0x85,0xfe,0xbb,0x36,0xb0,0x46,0x58,0x0b,0x1d,0xfd,
+  0x97,0xbd,0x03,0xbb,0x33,0x30,0x5f,0x00,0x80,0x22,0x7d,0xad,0x7c,0x3a,0x83,0x8b,
+  0xed,0xaa,0x84,0xba,0x62,0xcf,0x55,0xdb,0xc9,0x95,0x84,0xba,0xb9,0x9e,0x9b,0xd6,
+  0x5d,0x69,0x1d,0x5d,0x67,0xfa,0xf6,0x55,0x2e,0x91,0xfe,0xb4,0xff,0x0a,0x43,0x60,
+  0x2f,0xb3,0x18,0x54,0xc6,0x01,0x8f,0x54,0x41,0x6b,0x8d,0x23,0x94,0x56,0x41,0xfb,
+  0xdb,0x08,0xab,0xb0,0x11,0x47,0xaa,0x0a,0x9a,0xfd,0x11,0xbd,0x2d,0xa8,0xb6,0x02,
+  0x00,0xe8,0x40,0x56,0xd3,0x81,0x74,0xfe,0x59,0xdc,0x7b,0xca,0xe1,0x70,0x50,0xa6,
+  0x7a,0x6a,0x85,0x53,0x9c,0x2b,0xb3,0xdd,0x82,0x94,0x72,0x5a,0x2f,0xdd,0x63,0x53,
+  0x81,0xe7,0x72,0xdd,0x99,0xd6,0x86,0xc7,0x2c,0x9c,0xac,0x0c,0x88,0xfe,0x76,0x37,
+  0xff,0x2d,0xb6,0x17,0xb4,0xca,0x38,0xe0,0xed,0x01,0x8d,0x03,0xf6,0xbd,0x0a,0xda,
+  0xaa,0xdb,0xc0,0xdb,0x6b,0xa0,0xda,0x0a,0x00,0xa0,0x4b,0x32,0x4e,0x07,0x57,0x98,
+  0xda,0xc6,0x4d,0x19,0xee,0xdd,0x0e,0xba,0x53,0xa0,0x17,0x6d,0x5a,0x7a,0x97,0xd5,
+  0x5e,0x6f,0xfa,0xf6,0x55,0x22,0x94,0xb4,0x7a,0x4e,0xdb,0xfd,0xb7,0x14,0x55,0xd0,
+  0xaa,0x8d,0x38,0xc2,0x54,0x05,0xbd,0x7b,0x21,0xbf,0xe6,0x24,0x5a,0x3a,0x03,0x00,
+  0xbc,0x92,0x88,0xf2,0x2e,0xb5,0xe5,0x62,0xbb,0x76,0xed,0x5c,0x80,0xa4,0x9f,0xef,
+  0xf0,0x69,0x1d,0x5d,0x27,0x47,0xe4,0xec,0xbf,0xfa,0x8d,0x38,0xf2,0xab,0xa0,0x85,
+  0x29,0xe8,0x1d,0x1a,0x8d,0x38,0xea,0xd4,0x1a,0x71,0x1c,0xd6,0x48,0x41,0xe7,0x34,
+  0xc2,0x72,0x6b,0xc4,0xf1,0x3c,0xaf,0xce,0x6a,0x3a,0x80,0x0c,0x0c,0x00,0xa0,0x58,
+  0xba,0x9b,0x78,0x5f,0xca,0x92,0x6e,0xe3,0xde,0x2d,0x48,0x29,0x33,0x2d,0x1d,0x55,
+  0xbe,0xdb,0x4e,0x18,0xd5,0x1d,0x59,0xad,0x98,0x48,0x03,0x1d,0xa6,0xef,0x5d,0xc5,
+  0x31,0xd8,0x93,0xe3,0xbf,0x76,0x0b,0xce,0x4f,0x41,0x8b,0x42,0x60,0x5f,0x53,0xd0,
+  0xe1,0xac,0x82,0x66,0x36,0x4d,0xcd,0x35,0x16,0x22,0x5f,0x00,0x80,0x0f,0x10,0xd5,
+  0x6f,0xb1,0x99,0xaf,0x4e,0xc5,0xb2,0xc6,0x36,0xae,0xc3,0x4e,0xee,0x52,0xa1,0xed,
+  0x4e,0xc8,0xd5,0x1d,0x62,0xd5,0x61,0x22,0xa1,0xaf,0x10,0x51,0x6f,0x4b,0xc6,0x7f,
+  0x95,0xaa,0xa0,0xbd,0xa4,0xa0,0x45,0x55,0xd0,0x8d,0x92,0x2a,0xe8,0xd1,0x46,0x58,
+  0x6a,0x55,0xd0,0xf6,0x71,0x84,0x7e,0xa5,0xa0,0x47,0xfc,0x77,0xdf,0x12,0xab,0xbd,
+  0x01,0xe6,0x0b,0x00,0xf0,0x8d,0xd8,0x90,0xb5,0xf3,0xd9,0x30,0x79,0xae,0x83,0xe1,
+  0xda,0xb5,0xe4,0x76,0x16,0xb6,0x23,0x07,0xe8,0x23,0x7c,0xe0,0x6f,0x57,0x93,0x96,
+  0xff,0x16,0x91,0x82,0xf6,0x69,0x1c,0xa1,0x6a,0x23,0x0e,0x1f,0xc6,0x11,0x5a,0xfb,
+  0x97,0x5a,0xbc,0xd4,0x19,0xe7,0x8c,0x00,0x00,0x7e,0x42,0xfd,0x1d,0xbc,0x29,0x96,
+  0x3f,0x3b,0xb9,0xa2,0x6d,0x5c,0xc7,0x9d,0x5c,0x05,0xab,0xcd,0xe8,0x85,0xdb,0x72,
+  0xb4,0xe4,0x76,0x7e,0x0a,0x15,0xf8,0x04,0xc5,0x86,0x55,0xfd,0x57,0x5c,0x05,0xad,
+  0xd0,0x08,0x4b,0xb3,0x11,0x47,0x10,0x55,0xd0,0xde,0xfc,0xd7,0xaa,0x59,0x4d,0xfd,
+  0x9d,0xa6,0x7f,0x44,0x00,0x80,0xca,0x84,0x3f,0x2d,0x5f,0x9e,0xa4,0x70,0x4a,0xc8,
+  0xa8,0xe7,0xe6,0x69,0xdb,0x1c,0x54,0x61,0xf9,0x05,0x9f,0x79,0xc4,0xfd,0xb7,0x49,
+  0x6f,0x0b,0xb8,0x54,0x8d,0x38,0x4a,0x35,0x8e,0xb0,0x30,0x05,0xbd,0x98,0xea,0x36,
+  0x58,0xbc,0xab,0x33,0x00,0x00,0x04,0x43,0x32,0xce,0x1f,0x35,0xc2,0xc6,0x53,0xcb,
+  0x64,0x07,0x72,0x97,0xfa,0x91,0x55,0x5e,0x72,0x7b,0x56,0xee,0xb6,0xcb,0x75,0x2b,
+  0x17,0xfb,0xa3,0xfb,0x30,0x91,0xd0,0x0f,0xf8,0xe6,0x6f,0x9b,0xd5,0x7d,0x5a,0x39,
+  0x04,0xf6,0x50,0x05,0xad,0xdb,0x88,0x43,0x58,0x05,0xfd,0x4a,0x81,0x05,0x07,0xdb,
+  0x88,0xc3,0xaa,0xdf,0x62,0x0d,0xf7,0x9a,0xfe,0xf1,0x00,0x00,0x2a,0x9d,0x81,0x2e,
+  0xde,0x14,0xab,0xa8,0x6d,0xdc,0xe0,0x3d,0x37,0xad,0x5b,0xd2,0xaa,0x59,0x6b,0xfa,
+  0xae,0x55,0x02,0x94,0x4c,0x5a,0x3d,0x67,0x52,0x87,0x7f,0x99,0xff,0x9e,0x52,0x0e,
+  0x81,0x7d,0x4a,0x41,0xfb,0xd0,0x88,0x63,0x83,0xef,0x29,0x68,0x3e,0xc6,0xb7,0x7e,
+  0xab,0x15,0x19,0x30,0xfd,0xc3,0x01,0x00,0x54,0x07,0x2d,0xb5,0xbc,0x0a,0xda,0xaf,
+  0x53,0x42,0x52,0xdb,0x95,0x7b,0xee,0x6d,0x02,0xcf,0xb5,0x6b,0xf5,0x83,0x14,0x8f,
+  0x99,0xbe,0x6b,0x65,0x0f,0xc5,0x86,0x98,0xf9,0x8e,0xfa,0xaf,0x7a,0x0a,0x5a,0xd4,
+  0x08,0x2b,0xf0,0x71,0x84,0x3e,0x9d,0x42,0x72,0x4f,0x41,0x1f,0x78,0x91,0x85,0xe1,
+  0x16,0xe6,0x19,0x01,0x00,0x4a,0x06,0x25,0x79,0x13,0xfb,0x65,0x77,0xf9,0xbc,0x8d,
+  0x2b,0xdd,0xc9,0xcd,0x91,0xc8,0x67,0x9d,0xb4,0xe4,0x56,0x6a,0x6f,0x30,0x7d,0xd7,
+  0xca,0x1e,0xde,0x47,0x71,0xc4,0x7f,0xbb,0x5d,0xfd,0xd7,0xe7,0x46,0x1c,0xc2,0x2a,
+  0xac,0x00,0x1a,0x71,0xa4,0x2d,0x58,0xb9,0x11,0x07,0xfb,0xcf,0xa6,0x7d,0xa8,0xae,
+  0x07,0x00,0x94,0x18,0x16,0x4e,0xd2,0x96,0xd9,0xde,0x63,0x5b,0xbd,0xf0,0xd6,0x35,
+  0xb6,0x75,0xd2,0x62,0xbb,0xc6,0xd3,0xae,0x05,0xe8,0xc1,0x5b,0x24,0x34,0xd8,0x39,
+  0xe2,0xbf,0xe2,0x14,0xb4,0xbf,0x55,0xd0,0x2a,0xa7,0x90,0x0c,0x56,0x41,0x1f,0x5c,
+  0x41,0xcd,0x87,0x29,0x81,0xa4,0x0a,0x00,0xc0,0x00,0xd4,0x79,0x92,0xcf,0x62,0xf0,
+  0xb6,0x8d,0x2b,0xb7,0x5d,0xd1,0x36,0xae,0x9e,0xed,0x8e,0xcf,0x6a,0xd1,0x38,0x9e,
+  0x21,0x8f,0xf4,0x9b,0xbe,0x67,0x65,0x0c,0x25,0x93,0x7c,0x88,0x4f,0x8e,0xff,0x2a,
+  0x86,0xc0,0xa3,0x07,0x81,0x3d,0x54,0x41,0x17,0xd5,0x88,0x23,0xa8,0x14,0x34,0xff,
+  0xf7,0x96,0xa3,0x16,0xcc,0x17,0x00,0x60,0x0a,0x22,0xfe,0x34,0x93,0x3a,0xaf,0x8f,
+  0xdb,0xb8,0x6e,0x11,0xee,0xa8,0x16,0x8d,0x1f,0xd5,0xb8,0x5c,0xdd,0x4c,0x27,0x76,
+  0x99,0xbe,0x65,0x65,0x0c,0x9f,0x07,0x9d,0x2a,0xbe,0x12,0xfa,0xaf,0xf7,0x46,0x1c,
+  0x4a,0x5b,0xc0,0x61,0x6a,0xc4,0x71,0x70,0x59,0xaa,0xbd,0x15,0xd2,0xce,0x00,0x00,
+  0xa3,0x44,0x87,0x68,0xcb,0xac,0xe2,0xb6,0x71,0x35,0x77,0x72,0xc5,0x9e,0x3b,0xce,
+  0x41,0x37,0xe7,0x68,0xe3,0x0c,0x5e,0xc1,0x0b,0x3c,0x41,0x91,0x7e,0xbb,0xff,0xba,
+  0x84,0xc0,0x1e,0x1a,0x61,0x69,0xa4,0xa0,0xc5,0x55,0xd0,0x8a,0xe3,0x80,0x8b,0x4e,
+  0x41,0x1f,0x5e,0x69,0xb1,0x95,0xe2,0x53,0x04,0x00,0x08,0x03,0x7d,0xed,0xbc,0x16,
+  0x3a,0xb4,0x9e,0x3b,0xa2,0x85,0x37,0x71,0x2d,0x1e,0x4f,0x5d,0xa7,0x4c,0xdf,0xaf,
+  0xb2,0x65,0xa0,0x9b,0xf9,0xaf,0x4b,0x08,0xac,0x54,0x05,0xed,0x25,0x05,0x5d,0xcc,
+  0x38,0x42,0xb5,0x5e,0xd0,0x35,0x6b,0x95,0x52,0xd0,0x35,0x6b,0xb9,0xf9,0x02,0x00,
+  0x40,0x78,0x38,0xbe,0x8d,0x67,0xa1,0xe5,0xdb,0xb8,0x3e,0xed,0xe4,0xea,0xda,0xae,
+  0x5d,0xfb,0x96,0x98,0xbe,0x59,0xe5,0x09,0x91,0xd5,0xdf,0xae,0xe7,0xbf,0x3e,0xa7,
+  0xa0,0x73,0x1b,0x71,0xa8,0x36,0xc2,0xf2,0x30,0x0e,0xd8,0xa1,0x11,0x07,0xfb,0xd5,
+  0xae,0x26,0x34,0x52,0x03,0x00,0x84,0x8b,0xd8,0x30,0x6d,0x7f,0xc6,0xef,0x8a,0xe5,
+  0x5b,0x64,0x9e,0x2b,0x32,0x5c,0xa1,0xe7,0xda,0xb5,0xec,0x5e,0x2b,0x3a,0x64,0xfa,
+  0x7e,0x95,0x1f,0x23,0xc5,0x57,0xd4,0xd3,0x9c,0x93,0x82,0xee,0x76,0x6c,0xc4,0xa1,
+  0xd6,0x08,0xcb,0x7d,0x1c,0xe1,0x01,0xd5,0x2d,0x60,0x5b,0x23,0x2c,0x85,0x71,0x84,
+  0x1b,0x3d,0x54,0x61,0xf1,0x5f,0xea,0x86,0xf9,0x02,0x00,0x42,0x09,0x8b,0x8c,0x5e,
+  0x9e,0xac,0x61,0xbb,0xc2,0x94,0x72,0x4e,0xf5,0xd4,0x78,0xed,0xd8,0xd6,0x45,0x7f,
+  0xbc,0x31,0xad,0x85,0x37,0xb2,0x27,0xb9,0xe9,0x9b,0x55,0x86,0x24,0x62,0xd4,0xd3,
+  0x92,0x52,0xb1,0x21,0xb0,0xc4,0x7f,0xfd,0x4b,0x41,0xfb,0x36,0x0e,0xb8,0x66,0x95,
+  0xd5,0xd3,0x8c,0x91,0x46,0x00,0x80,0x90,0x42,0xc4,0x9f,0x7e,0x1e,0x3d,0xb7,0x88,
+  0x7c,0xb2,0x9b,0xe7,0xde,0x20,0xd6,0xe6,0x59,0x84,0x40,0x46,0x13,0x8a,0x0e,0x52,
+  0x5f,0xab,0xd4,0x7f,0xc3,0x5e,0x05,0xad,0x98,0x82,0x4e,0x5b,0x70,0xca,0x7c,0x6b,
+  0xd7,0x59,0x7d,0xad,0xa6,0x6f,0x3f,0x00,0x00,0x48,0xa0,0x9d,0x0b,0xc2,0x6b,0xbb,
+  0x7f,0xbc,0x3e,0x2d,0xf6,0x7b,0xf0,0x44,0xd5,0x84,0x86,0x7a,0x47,0xfd,0xb7,0x59,
+  0x54,0x05,0xad,0xd0,0x88,0x43,0xa1,0x11,0x96,0xf7,0x46,0x1c,0x8a,0x8d,0xb0,0x8e,
+  0x69,0x36,0xc2,0xaa,0xdb,0x48,0xbd,0xad,0x48,0x3b,0x03,0x00,0xc2,0x0f,0x1f,0x10,
+  0xbc,0x62,0x92,0xa0,0xf7,0x94,0x2f,0xa5,0x53,0x02,0xdd,0x98,0x96,0xd4,0x73,0x99,
+  0x9e,0x1f,0xd5,0x73,0xd7,0xd1,0xa1,0x15,0xa6,0x6f,0x55,0x59,0xc1,0x0c,0x68,0xa0,
+  0x6b,0xd4,0x7f,0x03,0x48,0x41,0x2b,0x8d,0x23,0x54,0x9d,0xc5,0xe0,0xbd,0x11,0x47,
+  0x6d,0x6e,0x15,0xf4,0xd1,0x8d,0xa9,0xc8,0x17,0xe6,0x0b,0x00,0x28,0x0f,0xf8,0x23,
+  0xce,0x71,0x1b,0xd7,0xd7,0x9d,0xdc,0x3f,0xde,0xe8,0x68,0xb5,0x59,0xcf,0xbd,0x2e,
+  0xab,0xe7,0x6c,0x5a,0x33,0x95,0x12,0xe8,0x9f,0xa0,0x0c,0x25,0xf9,0x29,0x33,0xe6,
+  0xbf,0xbd,0x3e,0xa5,0xa0,0x85,0xa7,0x90,0x84,0xbd,0xa0,0x95,0x1a,0x61,0x49,0x53,
+  0xd0,0x6a,0xa7,0x90,0xec,0x21,0x30,0xfb,0xf7,0xde,0x16,0x98,0x2f,0x00,0xa0,0x8c,
+  0xe0,0x1b,0x85,0x9b,0x66,0x14,0x5b,0xa5,0xac,0xe4,0xb9,0x22,0xc3,0x75,0xf4,0xdc,
+  0x6b,0x73,0xc4,0x5e,0xde,0x7d,0xda,0xf4,0xad,0x2a,0x1f,0x12,0x51,0xab,0xaf,0x8d,
+  0xfb,0xaf,0x2d,0x04,0xf6,0xd2,0x88,0x23,0x74,0xbd,0xa0,0x1d,0xc6,0x11,0xd6,0xae,
+  0x4d,0x15,0x5c,0xc1,0x7c,0x01,0x00,0x65,0x06,0xef,0x0b,0xbd,0xe4,0xb6,0xc0,0x76,
+  0x72,0x1d,0x6c,0xf7,0xb9,0xeb,0x44,0xba,0xc6,0x51,0xfb,0x97,0x9a,0xbe,0x4f,0x65,
+  0x03,0x1f,0x3b,0x58,0xe0,0xbf,0xc5,0x36,0xe2,0x08,0xed,0x38,0xe0,0xba,0x0d,0x7c,
+  0xc6,0x31,0xcc,0x17,0x00,0x50,0x9e,0x50,0xcd,0xea,0x74,0xf0,0xeb,0x6f,0xe9,0x94,
+  0xdc,0x70,0x5d,0x3d,0xd7,0xae,0xa5,0x77,0x12,0xc6,0xb6,0xaa,0xc1,0xc7,0x0e,0xf6,
+  0xb5,0xa5,0x2d,0xb8,0xd7,0xa7,0x2d,0x60,0x8d,0x46,0x58,0x07,0xdc,0x1a,0x71,0xa8,
+  0x8e,0x03,0x56,0xab,0x82,0x66,0xff,0x9f,0x5d,0x39,0xcc,0x17,0x00,0x50,0xb6,0xf0,
+  0x2c,0xf4,0x9a,0x87,0x94,0x4a,0xa7,0x54,0xaa,0xa7,0x9e,0xcf,0xad,0x9e,0x12,0x67,
+  0x95,0xd5,0x6c,0x37,0xa3,0x05,0xd7,0xd0,0xe9,0x43,0xa6,0xef,0x53,0x99,0x30,0xd8,
+  0x93,0xf5,0x5f,0xd1,0x29,0xa4,0xd1,0x46,0x1c,0x27,0xbd,0x36,0xe2,0xf0,0xab,0x0a,
+  0x7a,0x87,0x46,0x15,0x74,0x5d,0x41,0x15,0x34,0xfb,0x4f,0x6e,0xbe,0x09,0xd3,0xb7,
+  0x1b,0x00,0x00,0x8a,0x82,0x5a,0x6a,0x79,0x21,0xb4,0xef,0xa5,0x53,0x5a,0x9e,0xbb,
+  0xc0,0x59,0xcf,0x5e,0xcd,0xe7,0x17,0x23,0xd2,0x51,0x80,0x06,0xba,0xad,0xfe,0xf6,
+  0x5c,0xff,0x6d,0x16,0x85,0xc0,0x82,0x46,0x58,0xde,0xab,0xa0,0x8b,0x4b,0x41,0x7b,
+  0x69,0xc4,0xd1,0xd1,0x60,0x25,0x61,0xbe,0x00,0x80,0xf2,0x27,0x99,0xa4,0xdd,0x7f,
+  0xcc,0xb5,0x5d,0x85,0xac,0xb2,0xd8,0x73,0xaf,0xd3,0x8b,0x73,0xdd,0x6d,0x37,0xad,
+  0xab,0x78,0x7a,0x7c,0xa8,0xd7,0xf4,0x6d,0x0a,0x3d,0xbc,0xf3,0x73,0xc7,0x88,0xff,
+  0xa6,0x2d,0x58,0x61,0x0b,0x38,0xe0,0x46,0x1c,0xbb,0x3d,0xa5,0xa0,0x9d,0xfd,0xb7,
+  0x6e,0x03,0xbb,0x24,0x98,0x2f,0x00,0xa0,0x62,0xa0,0xa1,0x3e,0x7a,0x79,0x52,0xe0,
+  0x3b,0xb9,0x72,0xcf,0xbd,0xca,0x41,0xbf,0xe5,0x67,0x3c,0x81,0x2b,0x94,0x8c,0xe7,
+  0xfb,0xaf,0x7a,0x23,0x0e,0xf1,0x38,0x42,0x79,0x0a,0x3a,0xdf,0x7f,0xb5,0xab,0xa0,
+  0x15,0x53,0xd0,0x29,0x0b,0xae,0xdb,0x48,0x2d,0x47,0xb1,0xe7,0x0b,0x00,0xa8,0x30,
+  0xf8,0x63,0x73,0xd1,0x38,0xd9,0x4e,0x6e,0x71,0xdb,0xb8,0x39,0xba,0x3a,0x2b,0x27,
+  0xcf,0xb5,0x6b,0xd5,0x03,0x88,0x7a,0x24,0xc4,0x23,0x0e,0xfe,0x5b,0xf2,0x53,0x48,
+  0xe9,0x14,0xb4,0xe8,0x20,0xb0,0xb4,0x0a,0xba,0xde,0xc9,0x7f,0x37,0xb2,0x3f,0x91,
+  0x12,0x31,0xd3,0x77,0x19,0x00,0x00,0x7c,0x86,0x92,0x09,0xde,0x6f,0x39,0x40,0xcf,
+  0xbd,0x5a,0xdb,0x73,0x33,0x9a,0x7f,0x25,0x2d,0xb8,0x0a,0x13,0x81,0xdd,0xa1,0xe8,
+  0x50,0xda,0x7f,0x83,0x48,0x41,0x7b,0x69,0xc4,0x21,0x4c,0x41,0x2b,0x8e,0x23,0x2c,
+  0x68,0xc4,0x71,0xfa,0xa0,0x15,0x1b,0x36,0x7d,0x8f,0x01,0x00,0x20,0x10,0x78,0x4e,
+  0x72,0xc9,0xed,0x5e,0xb6,0x71,0x5d,0xb2,0xca,0xf6,0x6d,0x5c,0x45,0xab,0x75,0x12,
+  0x26,0x02,0xbb,0x42,0x91,0x01,0x81,0xff,0x0a,0xab,0xa0,0x7b,0x44,0x55,0xd0,0x42,
+  0xff,0x55,0x08,0x81,0x8b,0x4e,0x41,0xcb,0x4e,0x21,0x31,0x35,0xee,0x81,0xf9,0x02,
+  0x00,0x2a,0x19,0x4a,0xd2,0xc1,0x65,0x3e,0xec,0xe4,0xba,0x6c,0xe3,0xea,0x7a,0xae,
+  0x5d,0xfc,0x20,0x30,0xd2,0x8f,0x8e,0xd0,0x50,0x5f,0xca,0x7f,0x8b,0x4a,0x41,0x3b,
+  0x34,0xe2,0x50,0x18,0x47,0x18,0x5c,0x15,0x74,0xe3,0x4e,0x8a,0x0d,0x9a,0xbe,0xbb,
+  0x00,0x00,0x10,0x2c,0x14,0x8b,0xf0,0x96,0xcb,0xfe,0x96,0x4e,0x15,0xe3,0xb9,0x19,
+  0xcd,0xbb,0x9c,0xe6,0x5d,0xc1,0x6b,0x5f,0x81,0x10,0x22,0x7e,0xf8,0x37,0xe3,0xbf,
+  0x76,0x0b,0x16,0x36,0xe2,0xe8,0xd6,0x4e,0x41,0x97,0xbc,0x11,0x47,0x2a,0x05,0xdd,
+  0xb8,0xdb,0x42,0xe9,0x3b,0x00,0xa0,0x3a,0xe0,0x0f,0xdb,0x45,0x37,0x17,0x57,0x3a,
+  0xe5,0x60,0xbb,0x4a,0x56,0x7b,0x45,0x8e,0xb8,0xed,0xda,0xb4,0x6b,0x81,0xe9,0xdb,
+  0x13,0x56,0x52,0x93,0x8f,0xc4,0xfe,0xeb,0x56,0x05,0xad,0xe2,0xbf,0x41,0x56,0x41,
+  0xbb,0x8f,0x23,0x3c,0xb1,0xd3,0x1a,0xec,0x42,0xc1,0x33,0x00,0xa0,0x4a,0x20,0x4a,
+  0xd2,0x8e,0x67,0x45,0x41,0x6e,0x70,0x9e,0x7b,0xa5,0xa3,0xe1,0xe6,0xe8,0x32,0xbe,
+  0x3d,0x1d,0x1d,0x32,0x7d,0x87,0xc2,0x08,0x25,0x93,0x34,0xd0,0x39,0xea,0xbf,0x59,
+  0x0b,0x96,0xa5,0xa0,0x9d,0x1b,0x71,0x48,0xb6,0x80,0x45,0x29,0x68,0x7f,0xc7,0x11,
+  0xd6,0x6f,0xa3,0xfe,0x36,0x0c,0x36,0x02,0x00,0x54,0x15,0xc4,0x9e,0xdb,0x4b,0xef,
+  0xcc,0xad,0x9e,0xba,0x3a,0x80,0x94,0xf2,0x15,0x36,0x15,0x58,0x6d,0xa1,0xe6,0x5e,
+  0x4a,0x73,0x2f,0xa7,0xa6,0x03,0xa6,0x6f,0x4f,0x18,0xe1,0xe5,0xeb,0xd9,0xf8,0xd7,
+  0x4b,0x15,0xb4,0x4a,0x23,0xac,0x52,0x36,0xe2,0xb0,0xba,0x4e,0xf3,0x71,0x8a,0x00,
+  0x00,0x50,0x55,0x10,0xf1,0x76,0x07,0x41,0x6d,0xe3,0x3a,0xc4,0xb6,0x42,0x3d,0x73,
+  0x69,0xbe,0xb6,0xcc,0x42,0x2f,0x4a,0x01,0x89,0xa8,0x9b,0xff,0x96,0x57,0x15,0x74,
+  0xc3,0x56,0xab,0xfd,0x38,0xd2,0xce,0x00,0x80,0xea,0x84,0xc7,0x53,0x6b,0x1f,0x0e,
+  0x91,0xed,0xa6,0x75,0x31,0xff,0x32,0x10,0x19,0x30,0x7d,0x7b,0xc2,0x47,0x3c,0x92,
+  0xf2,0xdf,0xdc,0x14,0xb4,0xcf,0x55,0xd0,0x9e,0x67,0x31,0x08,0x1b,0x71,0x08,0x0e,
+  0x02,0xa7,0x37,0x7f,0x5b,0x8e,0x5a,0xc9,0xb8,0xe9,0x1b,0x0a,0x00,0x00,0xc6,0xe0,
+  0x4f,0xdd,0x85,0x37,0x06,0xb0,0x93,0x9b,0x97,0x55,0x1e,0x55,0xbe,0xd5,0x5e,0x32,
+  0xaa,0x8b,0xf3,0x75,0x6c,0x93,0xe9,0x7b,0x13,0x3a,0x28,0x3a,0xc4,0xfc,0xd7,0x2d,
+  0x04,0xee,0x15,0x84,0xc0,0x5e,0xc6,0x11,0xba,0xcf,0x62,0x70,0x4b,0x41,0xab,0x55,
+  0x41,0x9f,0x41,0x9f,0x0d,0x00,0x40,0xd5,0x43,0x44,0x3b,0xe7,0x17,0xb7,0x93,0xeb,
+  0x10,0xde,0xf2,0x9d,0xdc,0x51,0x89,0x3d,0x57,0x64,0xbb,0x19,0xad,0x99,0x42,0xe8,
+  0x45,0x99,0x0b,0x45,0x06,0x0b,0xfc,0x57,0x18,0x02,0x07,0xd8,0x08,0xab,0x20,0x04,
+  0x3e,0xa0,0x9a,0x82,0xce,0xf8,0x2f,0xf3,0x68,0x24,0x37,0x00,0x00,0x80,0x3d,0xd5,
+  0x7b,0x5b,0x68,0xf1,0x38,0x99,0xe1,0x96,0xc4,0x73,0x33,0x9a,0x73,0x31,0x3d,0x7b,
+  0x25,0xf5,0xb5,0x9b,0xbe,0x37,0xe1,0x82,0x22,0xfd,0xd6,0x60,0x8f,0x82,0xff,0xfa,
+  0x9b,0x82,0x56,0x68,0xc4,0x21,0xf4,0x5f,0x61,0x15,0xf4,0x89,0x5d,0xbc,0x85,0x08,
+  0x00,0x00,0x00,0x2b,0x15,0x02,0x1f,0x59,0xad,0xb0,0x8d,0xeb,0x60,0xbb,0x8e,0xdb,
+  0xb8,0x97,0x2a,0x59,0x6d,0x9e,0xed,0xda,0x75,0x68,0x85,0xe9,0x5b,0x13,0x2e,0x32,
+  0xfe,0x2b,0x4c,0x41,0xe7,0xf9,0xaf,0xcf,0x29,0x68,0x95,0x46,0x58,0xc2,0x2a,0x68,
+  0xbb,0xff,0x32,0xf3,0xed,0xc7,0x77,0x2a,0x00,0x00,0xc8,0x42,0xc9,0x38,0x2d,0xbf,
+  0xcf,0x80,0xe7,0xce,0x71,0xd6,0xd3,0x63,0x68,0xc9,0x1d,0x18,0x87,0x64,0x87,0xcf,
+  0x47,0x76,0xf6,0x5f,0xb7,0x14,0x74,0xba,0x11,0xd6,0x29,0x8d,0x14,0xb4,0xc6,0x29,
+  0x24,0xc5,0x14,0xf4,0x4e,0xab,0xf3,0x24,0x0a,0x9e,0x01,0x00,0x20,0x0f,0xbe,0x2b,
+  0xb7,0xe0,0x6a,0x81,0xed,0xce,0x75,0xaa,0x9e,0xba,0x44,0x3b,0xab,0x2c,0xb6,0xdd,
+  0xb1,0x59,0x31,0xcf,0xb5,0x8b,0xfd,0x6a,0xc7,0x71,0xd3,0x37,0x26,0x34,0x50,0x92,
+  0x37,0x9f,0xe4,0xea,0x16,0xa4,0xa0,0xf3,0x43,0xe0,0x66,0xc5,0x10,0xb8,0xe0,0x14,
+  0x92,0xb0,0x11,0x96,0x7a,0x08,0xec,0x38,0x8e,0xd0,0x6a,0xad,0xb3,0x12,0x28,0x78,
+  0x06,0x00,0x80,0x02,0x12,0x31,0xda,0x38,0xc3,0xff,0x6d,0x5c,0x71,0x6c,0x3b,0xd6,
+  0x26,0xbb,0xe7,0x5e,0x94,0xaf,0x9d,0xcf,0x9a,0xbe,0x2f,0x61,0x81,0x57,0xa3,0xa5,
+  0xfd,0x77,0x24,0x04,0x16,0x34,0xc2,0xf2,0xb7,0x11,0x47,0x11,0x55,0xd0,0xf9,0xfe,
+  0x6b,0x35,0x1d,0x40,0xc1,0x33,0x00,0x00,0x38,0xc1,0x9f,0xba,0xf3,0xaf,0x28,0xf0,
+  0x5c,0xd7,0x53,0x42,0x1e,0x6d,0x77,0x8c,0xc4,0x76,0x47,0x34,0xfb,0x42,0xde,0x8b,
+  0x12,0xa7,0x44,0x53,0x14,0xf8,0xaf,0x66,0x0a,0xda,0x43,0x15,0xb4,0x7a,0x23,0x0e,
+  0x77,0xff,0x65,0xff,0x07,0x05,0xcf,0x00,0x00,0xe0,0x0c,0x6f,0xc7,0xb1,0x6d,0x8e,
+  0x3f,0xa5,0x53,0xf6,0x6d,0x5c,0xb1,0x9c,0x3d,0xd7,0x2e,0xf6,0x3b,0x3b,0x4f,0x98,
+  0xbe,0x31,0xe1,0x20,0x11,0xb5,0xf9,0xaf,0x28,0x05,0xad,0x34,0x8b,0x41,0x25,0x05,
+  0xed,0x6b,0x23,0xac,0x53,0x7b,0x89,0x5d,0x18,0x00,0x00,0x00,0x57,0x78,0x60,0xb5,
+  0x68,0x9c,0xff,0x3b,0xb9,0xba,0xb6,0x6b,0xd7,0x8e,0x79,0xa6,0xef,0x4a,0x38,0xb0,
+  0xf9,0xef,0xe8,0x29,0x24,0x79,0x23,0x2c,0xff,0x52,0xd0,0x0a,0x8d,0xb0,0x9a,0x0a,
+  0x1b,0x61,0xed,0xb1,0xd8,0x9f,0x88,0x0e,0xcf,0x00,0x00,0xa0,0x00,0xd5,0xae,0x4f,
+  0xa5,0xa0,0x8d,0x7a,0x6e,0x56,0xbf,0xa1,0x85,0x37,0x62,0xeb,0x90,0x93,0x88,0xd2,
+  0x50,0x8f,0x73,0x0a,0xba,0x43,0xda,0x08,0xcb,0xea,0x56,0x1f,0x47,0x28,0x6f,0xc4,
+  0x51,0x10,0x02,0x0b,0xc6,0x01,0x5b,0x6d,0xf5,0x56,0x22,0x66,0xfa,0xc6,0x01,0x00,
+  0x40,0x99,0x10,0x1d,0xa2,0x95,0xbf,0xf7,0x54,0x3d,0xe5,0x60,0xb5,0x4a,0x3e,0x6b,
+  0xd3,0x53,0xbf,0xb1,0xe9,0xd7,0xfc,0xff,0x60,0x1c,0x92,0x95,0xef,0xbf,0x45,0x34,
+  0xe2,0x38,0xe9,0x4b,0x0a,0xda,0x35,0x04,0xe6,0x29,0x68,0x8b,0xfd,0x1f,0x7c,0x71,
+  0x02,0x00,0x00,0x1d,0xe8,0xcc,0x11,0x9f,0xb7,0x71,0x95,0x6c,0xf7,0xd7,0x0e,0xfa,
+  0x15,0x6d,0x7a,0x02,0xe3,0x90,0x46,0xfc,0xd7,0x35,0x04,0x2e,0x49,0x23,0x0e,0x95,
+  0x2a,0x68,0xe6,0xbf,0xa7,0xf6,0x5b,0x83,0xbd,0xa6,0x6f,0x19,0x00,0x00,0x94,0x1b,
+  0xcc,0xed,0xd6,0x4c,0x0d,0xdc,0x73,0x1d,0x0d,0x37,0xe5,0xb9,0x76,0xcd,0x19,0x4b,
+  0xc3,0xfd,0xa6,0x6f,0x8a,0x61,0x58,0x2c,0xa9,0xe8,0xbf,0xa3,0x29,0x68,0x91,0xff,
+  0x76,0xab,0x57,0x41,0x0b,0x0f,0x02,0x2b,0x37,0xe2,0xe8,0x69,0x46,0xab,0x0d,0x00,
+  0x00,0xf0,0x00,0x7f,0xfc,0xce,0xbf,0xd2,0xcf,0x6d,0xdc,0x8c,0x54,0x3c,0x77,0x96,
+  0x4d,0x4f,0x5e,0xc0,0x55,0xb7,0xd1,0xf4,0x2d,0x31,0x0c,0xc5,0x86,0x0a,0xfc,0xb7,
+  0x5b,0xe1,0x14,0x92,0xb0,0x0a,0xfa,0x54,0xb0,0x55,0xd0,0xed,0xf5,0x84,0x56,0x1b,
+  0x00,0x00,0xe0,0x09,0x7e,0x16,0x69,0xcb,0xec,0xa2,0x43,0x5d,0x1d,0xcf,0x7d,0xaa,
+  0xc0,0x73,0xb3,0xfa,0x25,0xad,0x9c,0x6c,0x55,0x77,0x19,0x2d,0x1f,0x3e,0x38,0xd4,
+  0x5b,0xb8,0x05,0xec,0x73,0x23,0x8e,0x7c,0xff,0xd5,0x4f,0x41,0xb3,0x5f,0x8d,0x0d,
+  0x99,0xbe,0x5b,0x00,0x00,0x50,0xc6,0xf0,0xd0,0x69,0xc1,0xd5,0xc5,0x56,0x4f,0x39,
+  0x59,0x6d,0xd6,0x73,0x2f,0xc8,0x2a,0xcf,0x73,0xb3,0xfa,0x05,0xcd,0x19,0x43,0x7d,
+  0x2d,0xa6,0x6f,0x89,0x49,0x52,0xfe,0xdb,0xa7,0x97,0x82,0x2e,0x7d,0x23,0x0e,0xa6,
+  0xa1,0x6e,0xd3,0xb7,0x0a,0x00,0x00,0xca,0x1c,0x22,0xda,0xfd,0x5c,0xb1,0xa5,0x53,
+  0x42,0xe5,0x87,0xb7,0x19,0xfd,0xc2,0x4d,0x87,0x96,0x9b,0xbe,0x23,0x26,0x11,0xfa,
+  0xaf,0x5a,0x15,0xf4,0x99,0x52,0x55,0x41,0x1f,0x62,0x7f,0x1c,0xb6,0x7d,0x01,0x00,
+  0xa0,0x78,0x28,0xd2,0x4f,0xcf,0x5f,0x57,0x6c,0xf5,0x54,0x91,0xb6,0x9b,0xd1,0xc2,
+  0x9b,0xab,0x79,0x1c,0x12,0x45,0x07,0x53,0xfe,0xdb,0x27,0xf2,0x5f,0x79,0x23,0x8e,
+  0x12,0x8c,0x03,0xb6,0xd8,0x6b,0xab,0xf8,0x07,0x04,0x00,0x00,0xfe,0x42,0xfb,0x97,
+  0xd2,0xec,0x8b,0x8a,0xad,0x9e,0x12,0x64,0x95,0xd5,0x3c,0x37,0xa3,0x99,0xbf,0xe0,
+  0x09,0xea,0xb6,0x63,0xa6,0xef,0x87,0x31,0x28,0x32,0x90,0xf1,0x5f,0x9d,0x2a,0xe8,
+  0x20,0x1b,0x71,0xd8,0xb7,0x80,0xd9,0xff,0x89,0x62,0xdb,0x17,0x00,0x00,0x7c,0x83,
+  0x3f,0xed,0x17,0x8d,0xf3,0x69,0x1b,0x57,0xcd,0x76,0x67,0x8a,0xf4,0x87,0xf3,0xb9,
+  0xf6,0x2c,0x32,0x7d,0x3f,0x8c,0xc1,0xfd,0x77,0xb8,0x5f,0x94,0x82,0xf6,0xdc,0x0b,
+  0x5a,0xa5,0x0a,0xda,0xf5,0x14,0x92,0xdd,0x82,0x07,0x3a,0xd9,0x35,0x9a,0xbe,0x49,
+  0x00,0x00,0x50,0x49,0x10,0x1d,0x5e,0x55,0x54,0xe9,0x94,0x37,0xc3,0xcd,0x78,0x6e,
+  0x5a,0x3f,0xe7,0x5a,0x72,0x7b,0xd5,0x36,0x13,0xe6,0xfe,0x1b,0xe9,0x77,0x4a,0x41,
+  0xbb,0x85,0xc0,0x3e,0x54,0x41,0x8b,0x52,0xd0,0xb6,0x10,0xd8,0xea,0x6e,0xc2,0xb6,
+  0x2f,0x00,0x00,0xf8,0x4f,0x3c,0x9a,0x0a,0x81,0x7d,0xda,0xc6,0x95,0xdb,0xee,0xcf,
+  0x1d,0xf4,0x33,0xfe,0xaa,0xee,0xd3,0xa6,0x6f,0x87,0x19,0xf2,0xfc,0x57,0x23,0x05,
+  0xed,0x53,0x23,0x2c,0xc7,0x46,0x1c,0x6d,0xf5,0x56,0x12,0x4d,0x9e,0x01,0x00,0x20,
+  0x10,0xe8,0xc4,0x4e,0x7e,0x9e,0xc8,0x88,0xe7,0xe6,0x69,0xd7,0x73,0xa6,0x6f,0x86,
+  0x19,0xd2,0xfe,0x1b,0x11,0xa4,0xa0,0xd5,0x4e,0x21,0x29,0xa4,0xa0,0x3d,0x34,0xc2,
+  0x6a,0x3d,0x6a,0x55,0x7d,0x6b,0x32,0x00,0x00,0x08,0x0e,0x8a,0xc7,0x68,0xf9,0xc4,
+  0xa2,0xaa,0xa7,0xb2,0x3a,0x3f,0x2b,0x15,0xdb,0x7d,0xc2,0xa6,0x19,0x3f,0xa5,0x85,
+  0x37,0xb1,0x78,0xdc,0xf4,0xfd,0x30,0x40,0xae,0xff,0xf6,0x16,0x6e,0x01,0x0b,0x1b,
+  0x71,0xf8,0xd7,0x0b,0x5a,0x9c,0x82,0x4e,0xcd,0xf6,0x45,0xe6,0x19,0x00,0x00,0x02,
+  0x84,0x9a,0xf6,0xa5,0x92,0xcf,0x3e,0xed,0xe4,0x3a,0x85,0xb7,0x69,0xcf,0xfd,0x69,
+  0x56,0x33,0xec,0xfa,0x09,0xcd,0xfc,0x39,0xb1,0x87,0x7f,0xf5,0x91,0xeb,0xbf,0xe1,
+  0xa8,0x82,0x66,0x2f,0xc1,0x81,0x23,0x00,0x00,0x08,0x9a,0x44,0x8c,0x56,0xde,0xef,
+  0xd5,0x76,0x65,0x59,0xe5,0x3c,0xdb,0x9d,0x51,0x60,0xbb,0x69,0xfd,0x98,0x6b,0xfb,
+  0x5c,0xd3,0xf7,0xc2,0x00,0x29,0xff,0x55,0x4f,0x41,0x7b,0x1d,0x47,0xa8,0xbc,0x05,
+  0x4c,0xed,0xc7,0xac,0x78,0xc4,0xf4,0x5d,0x01,0x00,0x80,0xaa,0x80,0x6f,0x05,0xf2,
+  0x5d,0x60,0x97,0x53,0x42,0x4e,0xf9,0x64,0x07,0xcf,0xcd,0xf7,0x59,0xbb,0x7e,0xec,
+  0xa8,0x79,0x97,0x51,0xb2,0xea,0xda,0xfb,0x53,0x64,0xb0,0x30,0x04,0x56,0xa9,0x82,
+  0x0e,0xa4,0x11,0x07,0x0b,0x84,0x07,0xd1,0x67,0x12,0x00,0x00,0x4a,0x07,0x1f,0xc5,
+  0xab,0xb1,0x8d,0xfb,0x73,0xc7,0x6d,0x5c,0x71,0x78,0xfb,0x13,0x37,0xdb,0xb5,0xeb,
+  0xf4,0x41,0xd3,0x77,0xa2,0xd4,0xf0,0xfe,0x93,0x9e,0x52,0xd0,0x69,0xff,0x15,0x8e,
+  0x23,0xf4,0x30,0x0e,0x38,0x95,0x82,0xe6,0x85,0x5b,0xd5,0x7a,0x10,0x0c,0x00,0x00,
+  0x8c,0x40,0x9d,0x27,0xf9,0x34,0x5e,0x6f,0xa5,0x53,0x62,0xc3,0x55,0xf6,0xdc,0x8c,
+  0xa6,0xff,0x98,0x36,0x3c,0x6e,0xfa,0x4e,0x94,0x9a,0x51,0xff,0x4d,0x59,0xb0,0xa8,
+  0x11,0x87,0x5a,0x0a,0xba,0x59,0xb4,0x05,0x2c,0x68,0xc4,0x91,0x1f,0x02,0xdb,0x52,
+  0xd0,0xd4,0x56,0x8f,0x09,0x47,0x00,0x00,0x50,0x6a,0x92,0x49,0xda,0xf0,0x98,0x3f,
+  0xdb,0xb8,0x2a,0x3e,0x2b,0xd4,0xe3,0xe7,0xd1,0x33,0x17,0x33,0x27,0x32,0x7d,0x2f,
+  0x4a,0x4a,0x8e,0xff,0x8a,0xb6,0x80,0xc5,0xb3,0x18,0x8a,0xac,0x82,0x16,0xa6,0xa0,
+  0xd9,0x3b,0x03,0x00,0x00,0x28,0x39,0x3c,0x86,0x9a,0x75,0x81,0xf2,0x4e,0xae,0x7e,
+  0x6c,0x2b,0xf6,0xdc,0xff,0xcb,0xd1,0xf4,0xf3,0xa8,0x71,0x97,0xe9,0x3b,0x51,0x52,
+  0xb8,0xff,0x7a,0x4d,0x41,0xab,0x8f,0x23,0x94,0xa6,0xa0,0xad,0xae,0x53,0x68,0x75,
+  0x05,0x00,0x00,0x46,0x20,0xc6,0xb6,0xb9,0x66,0x6c,0x37,0xab,0x1f,0xd1,0xaa,0x07,
+  0x4c,0xdf,0x89,0x92,0x62,0xf3,0xdf,0x91,0x14,0xb4,0xd0,0x7f,0x55,0x7a,0x41,0xe7,
+  0xfa,0x6f,0x77,0x93,0x46,0x23,0x0e,0xf6,0x9f,0xb1,0x61,0xd3,0x77,0x02,0x00,0x00,
+  0xaa,0x17,0xea,0xef,0xa0,0x79,0x97,0x7b,0x2c,0x9d,0x12,0x78,0xee,0x79,0x39,0xca,
+  0xf1,0xd9,0x73,0x6d,0xfa,0x51,0x8e,0x9e,0xbc,0x80,0xaa,0xa9,0xf3,0x12,0xc5,0x46,
+  0xfc,0x77,0xd0,0xb5,0x11,0x87,0xca,0x38,0x60,0x61,0x23,0x2c,0x41,0x08,0x5c,0x38,
+  0x0e,0xd8,0x1a,0xec,0x44,0xf0,0x0b,0x00,0x00,0x66,0xa1,0x3d,0x0b,0x8b,0xf3,0xdc,
+  0x1f,0x3b,0x18,0x6e,0x9e,0xed,0xfe,0xc8,0x59,0xe7,0xd2,0x89,0x2a,0x4a,0x41,0xa7,
+  0xfd,0x57,0x29,0x05,0x2d,0x68,0x84,0xa5,0xde,0x0b,0xda,0x31,0x04,0xee,0x3a,0x65,
+  0x55,0xdf,0xb1,0x2f,0x00,0x00,0x08,0x1b,0xec,0x21,0x4f,0xcf,0x5c,0xa2,0x9d,0x52,
+  0x7e,0xfc,0x3c,0x9b,0x9c,0x3c,0xd7,0xdd,0x76,0x47,0xf5,0xd8,0x8f,0x68,0xfd,0x63,
+  0x54,0x35,0xe1,0x58,0xae,0xff,0xaa,0xcf,0x62,0x90,0xa7,0xa0,0xc5,0x8d,0x38,0x0a,
+  0x43,0xe0,0x6a,0xca,0x36,0x00,0x00,0x40,0x78,0x61,0xce,0xb7,0x73,0xbe,0x9a,0xe7,
+  0x3a,0xef,0xe1,0x6a,0xe9,0xb1,0x02,0xcd,0xbe,0x88,0xe2,0xd5,0x12,0x91,0x71,0xff,
+  0x8d,0x0d,0x95,0xb8,0x0a,0x3a,0xe3,0xbf,0x56,0x5f,0x8b,0xe9,0x1b,0x00,0x00,0x00,
+  0x20,0x0d,0x7f,0xfe,0xcf,0xbb,0xcc,0x4b,0xe9,0x54,0x91,0xb6,0x3b,0xa2,0x47,0x7f,
+  0xc0,0x55,0xbf,0xd9,0xf4,0x6d,0x28,0x11,0x14,0x1b,0xd6,0x49,0x41,0xfb,0x3a,0x8e,
+  0xb0,0xb3,0x91,0xaa,0x72,0xe6,0x05,0x00,0x00,0x84,0x16,0xda,0xbf,0x94,0xa6,0xff,
+  0xc4,0x79,0x27,0x57,0x27,0x9f,0xec,0xe6,0xb9,0x3f,0x4c,0x6b,0xc4,0x73,0xed,0x5a,
+  0xf9,0xfb,0x2a,0x99,0xbf,0x43,0xb1,0x88,0x20,0x05,0xad,0xd4,0x88,0xa3,0xa8,0x59,
+  0x0c,0xdc,0x82,0x07,0xbb,0x4c,0xaf,0x1e,0x00,0x00,0x40,0x0e,0xbc,0xfe,0x76,0xc1,
+  0xd5,0xc5,0x6e,0xe3,0x8a,0xc3,0xdb,0x1f,0xda,0x64,0xf7,0xdc,0xff,0xcd,0xd1,0xac,
+  0x5f,0xb2,0x6b,0x30,0x7d,0x1b,0x4a,0x41,0xda,0x7f,0x95,0x52,0xd0,0x2a,0xa7,0x90,
+  0x9a,0x45,0x21,0xb0,0xa0,0x11,0x16,0x75,0x9f,0xc1,0x90,0x23,0x00,0x00,0x08,0x21,
+  0x74,0x68,0x45,0xa9,0x3d,0x37,0xa3,0x69,0xdf,0xe7,0xff,0x3c,0xf6,0x8a,0xe9,0x7b,
+  0x50,0x0a,0x72,0xfc,0x37,0xf8,0x14,0x74,0x26,0x04,0xa6,0xe8,0xa0,0xe9,0xa5,0x03,
+  0x00,0x00,0x10,0xc0,0xf7,0x25,0x9f,0xb9,0xc4,0x87,0x9d,0x5c,0x81,0x9c,0x6d,0xd7,
+  0xae,0x65,0xf7,0x98,0xbe,0x07,0x25,0x21,0x11,0x2d,0xf0,0x5f,0xf5,0x2a,0x68,0x79,
+  0x23,0x2c,0x61,0x15,0x34,0xf5,0xb5,0xe3,0xc0,0x2f,0x00,0x00,0x84,0x16,0x3a,0xb8,
+  0xdc,0x31,0xf2,0xd5,0x33,0x5c,0x65,0xcf,0xb5,0xeb,0xb1,0x73,0xf9,0x89,0xd7,0x8a,
+  0x27,0xdf,0x7f,0x55,0x1a,0x71,0x74,0xba,0xa6,0xa0,0x85,0xe3,0x08,0x6d,0x29,0x68,
+  0xf6,0xef,0x09,0x94,0x5d,0x01,0x00,0x40,0x78,0xe1,0xbd,0x10,0xe7,0xff,0xd6,0xc1,
+  0x76,0x7f,0xe8,0x56,0x3d,0xe5,0x6e,0xbb,0x2e,0x9e,0x9b,0xd5,0xf7,0xb8,0x0e,0x2e,
+  0x37,0x7d,0x0f,0x82,0x27,0xe3,0xbf,0x25,0x4b,0x41,0x0f,0x56,0xc1,0xb7,0x1a,0x00,
+  0x00,0x28,0x73,0xf8,0x2e,0x70,0x31,0xdb,0xb8,0x5a,0x7a,0xe4,0x7b,0x36,0x7d,0x97,
+  0xeb,0x85,0x5b,0xa9,0xe2,0x6b,0x84,0xc4,0xfe,0xeb,0x35,0x05,0x2d,0xab,0x82,0xb6,
+  0xba,0x9b,0xac,0x44,0xb5,0x9c,0xad,0x06,0x00,0x80,0xf2,0x85,0x1f,0x84,0x61,0x21,
+  0xb0,0xc0,0x73,0x83,0xb0,0xdd,0xef,0xe6,0xea,0x7f,0x78,0xf6,0xbb,0xe2,0x1b,0x44,
+  0xb8,0xf8,0xaf,0xa8,0x0a,0x5a,0xad,0x11,0x96,0x30,0x05,0x9d,0xb2,0xe0,0xa1,0x3e,
+  0xd3,0x0b,0x06,0x00,0x00,0xa0,0x04,0xd5,0xac,0xb1,0x25,0x99,0xfd,0xf2,0xdc,0xef,
+  0x3a,0xe8,0x7f,0xf2,0xb5,0x77,0x91,0xe9,0x1b,0x10,0x2c,0x2c,0xc0,0x4f,0xb7,0xe0,
+  0x70,0x4d,0x41,0xe7,0x6d,0x01,0xbb,0x86,0xc0,0x8e,0x29,0x68,0xde,0xed,0x0a,0x65,
+  0x57,0x00,0x00,0x50,0x26,0x50,0x3c,0x46,0xf3,0xae,0x28,0x76,0x27,0x77,0x44,0x2a,
+  0xb6,0xfb,0xb0,0x4d,0x0f,0x7d,0x87,0x9e,0xbb,0xb6,0xb2,0x8f,0xa9,0xa6,0xfc,0x37,
+  0xe2,0xe8,0xbf,0xe2,0x71,0x84,0xfa,0xe3,0x80,0xbb,0x9b,0xb8,0xa2,0x43,0xa6,0x97,
+  0x0b,0x00,0x00,0x40,0x03,0xda,0xbb,0xb0,0xa4,0x9e,0x9b,0xd5,0xb7,0xf9,0x9f,0xd8,
+  0xdb,0x6c,0xfa,0x06,0x04,0x09,0x25,0x73,0xfc,0x57,0xdc,0x88,0xa3,0xd7,0x5b,0x23,
+  0x0e,0x7b,0x0a,0x9a,0xff,0x36,0x04,0xbf,0x00,0x00,0x50,0x56,0xf0,0xa1,0x48,0xb3,
+  0x2f,0x2a,0x6a,0x27,0x57,0xa8,0x87,0xbf,0x93,0xd6,0x43,0xdf,0xc9,0xb7,0xdd,0xb4,
+  0xbe,0x45,0x0f,0x7f,0x9b,0x0e,0xad,0x30,0x7d,0x03,0x82,0x24,0xed,0xbf,0xce,0x21,
+  0xb0,0x4e,0x0a,0xda,0x69,0x16,0x03,0x75,0x9f,0x41,0xab,0x67,0x00,0x00,0x28,0x43,
+  0x88,0xb6,0x3f,0xa3,0xb3,0x8d,0xeb,0xec,0xb9,0xf9,0x56,0x9b,0xd1,0xb7,0x1c,0xb5,
+  0xf8,0x56,0xa2,0xa4,0xe9,0x3b,0x10,0x18,0xca,0xfe,0x5b,0x54,0x0a,0xba,0x3a,0x9a,
+  0x79,0x02,0x00,0x40,0xe5,0xc1,0x53,0xa0,0x33,0x7f,0xae,0x5d,0x3d,0x25,0xf1,0x5c,
+  0x57,0xdb,0xcd,0x88,0xbd,0x73,0x6f,0xe5,0x56,0x41,0x33,0xff,0x8d,0x3b,0xf9,0xaf,
+  0x63,0x0a,0x9a,0x06,0xba,0x35,0x1a,0x71,0xf4,0x36,0x5b,0x49,0x9c,0x39,0x02,0x00,
+  0x80,0xb2,0x84,0x28,0x15,0x02,0x7b,0xde,0xc6,0xcd,0x91,0x82,0xe7,0xda,0x35,0xf5,
+  0x5b,0xb4,0xfb,0x8f,0xa6,0x6f,0x40,0x60,0x10,0xa5,0x8e,0x20,0x45,0xf2,0xab,0xa0,
+  0xf3,0x1b,0x61,0x15,0x91,0x82,0x66,0xc1,0x2f,0x76,0x7e,0x01,0x00,0xa0,0x6c,0xa1,
+  0xde,0x66,0x7a,0xe2,0x67,0x82,0x38,0x57,0xec,0xb9,0xdf,0xf1,0x6e,0xb8,0x23,0x9e,
+  0x9b,0xd5,0x37,0x69,0x41,0xe5,0x56,0x41,0x67,0xfd,0xd7,0x39,0x04,0x2e,0x62,0x1c,
+  0xa1,0xd5,0xdb,0x8a,0xe0,0x17,0x00,0x00,0xca,0x1b,0x16,0x02,0xaf,0x79,0x28,0xbf,
+  0x74,0x2a,0xbf,0x7a,0x4a,0x33,0xce,0x9d,0xea,0xa0,0x07,0xbf,0x69,0xd3,0x37,0x78,
+  0x4d,0x57,0xe7,0x49,0xd3,0xeb,0x0f,0x8c,0x42,0xff,0x55,0x18,0x47,0xa8,0xda,0x88,
+  0x63,0x18,0x0d,0x37,0x00,0x00,0xa0,0xec,0xa1,0x8e,0x06,0xbe,0xff,0xeb,0x6d,0x1b,
+  0x57,0xc9,0x76,0xbf,0xe1,0xa0,0xaf,0x57,0x70,0x0a,0x9a,0xe2,0xb1,0x51,0x0b,0xd6,
+  0xf0,0xdf,0xd1,0x59,0x0c,0x1d,0x6e,0x29,0xe8,0xfe,0x36,0xab,0x82,0x4b,0xd7,0x00,
+  0x00,0xa0,0x6a,0xe0,0xbb,0xc0,0xeb,0x1f,0x2d,0x9d,0xe7,0xda,0xf5,0xf4,0x98,0x8a,
+  0x4d,0x41,0x27,0xa2,0xe2,0x2d,0xe0,0xa2,0x1b,0x71,0x58,0xc3,0x03,0xa6,0xd7,0x06,
+  0x00,0x00,0xc0,0x1f,0xa8,0xe3,0x04,0x3d,0xfe,0x7f,0x5e,0x3d,0xf7,0x9b,0x69,0x29,
+  0x7a,0x6e,0x46,0x53,0xbe,0xc6,0x13,0xd1,0xed,0xf5,0xa6,0x57,0x1f,0x08,0x94,0x88,
+  0xc9,0xb7,0x80,0xc5,0x21,0xb0,0xa8,0x11,0xc7,0x68,0x08,0x6c,0x0d,0x74,0x56,0xec,
+  0x37,0x16,0x00,0x00,0xa8,0x42,0x58,0x08,0xbc,0xea,0x01,0xd5,0xd8,0xb6,0x70,0x27,
+  0x57,0xc5,0x6a,0x9d,0xb4,0xf9,0x49,0xd3,0x8b,0x0f,0x04,0x4a,0xc6,0x79,0x08,0x1c,
+  0x17,0xa5,0xa0,0xa3,0x82,0x71,0xc0,0x05,0x21,0x70,0xa7,0x38,0x04,0x46,0xb7,0x49,
+  0x00,0x00,0xa8,0x2c,0x58,0x1c,0xca,0xdb,0x42,0x3a,0xd9,0x6e,0x8e,0xe1,0x2a,0x78,
+  0xae,0x8b,0xe1,0xe6,0xe9,0xe9,0x31,0x15,0xd9,0xc4,0x89,0xcf,0x58,0xcc,0xa6,0xa0,
+  0x9d,0x43,0x60,0xad,0x46,0x1c,0xe8,0x36,0x09,0x00,0x00,0x95,0x07,0x25,0x69,0xf1,
+  0x2d,0x1e,0xb7,0x71,0x3d,0xd8,0xee,0x88,0x1e,0xf8,0x0a,0xff,0x67,0xf3,0x11,0xd3,
+  0x8b,0xf7,0x1f,0x5f,0xfd,0x37,0x5d,0x05,0xcd,0x02,0x67,0xd3,0xcb,0x02,0x00,0x00,
+  0xe0,0x3f,0x74,0x72,0x2f,0x3f,0xf0,0x5b,0x02,0xcf,0xcd,0xd3,0xba,0x47,0x4c,0x2f,
+  0x3d,0x00,0x28,0x99,0xf6,0xdf,0xb8,0xf0,0x14,0x92,0x20,0x05,0x5d,0x50,0x05,0x9d,
+  0x9b,0x82,0x1e,0xe8,0xa4,0x24,0xca,0x9e,0x01,0x00,0xa0,0x02,0xa1,0x44,0x82,0x9e,
+  0xbd,0xca,0x57,0xdb,0xfd,0x6a,0x56,0x85,0xb6,0x3b,0xa2,0xfb,0xbf,0x42,0x7f,0x38,
+  0xdf,0x8a,0x47,0x4c,0xaf,0xde,0x6f,0x52,0x2d,0x38,0x64,0x55,0xd0,0x1a,0x21,0x30,
+  0xfb,0x9d,0xa6,0x97,0x04,0x00,0x00,0x20,0x28,0xe8,0xc8,0x9a,0x54,0x25,0x73,0x31,
+  0xe1,0xed,0x57,0x6d,0xca,0xf5,0x59,0xa1,0x7e,0xff,0x65,0x9a,0xf2,0x75,0x6a,0x3b,
+  0x66,0x7a,0xe9,0x7e,0x93,0xef,0xbf,0x7a,0x8d,0xb0,0x04,0x55,0xd0,0x28,0x7b,0x06,
+  0x00,0x80,0x0a,0x86,0xf9,0xc2,0xac,0x5f,0x17,0x67,0xbb,0x05,0xe1,0xad,0x93,0xed,
+  0xa6,0xf5,0x25,0xfe,0xcf,0x6d,0x4f,0x9b,0x5e,0xb9,0xdf,0xd8,0xfc,0x57,0xdc,0x88,
+  0x43,0x61,0x1c,0xa1,0x2d,0xf8,0xc5,0x99,0x5f,0x00,0x00,0xa8,0x70,0x68,0xef,0x0b,
+  0x4a,0xfe,0xeb,0x94,0x4f,0x76,0xf3,0xdc,0x2f,0x39,0xe8,0x8b,0x7c,0x12,0x71,0x85,
+  0x35,0x34,0x26,0xca,0x94,0x60,0xb9,0x86,0xc0,0x0a,0xb3,0x18,0xf8,0xce,0x6f,0x65,
+  0xdd,0x1c,0x00,0x00,0x00,0x05,0xf0,0xa6,0x4c,0x33,0x7f,0xae,0xbd,0x8d,0x9b,0x63,
+  0xbb,0x5f,0xce,0x2a,0xdf,0x6a,0xff,0xdb,0xa6,0x2f,0x66,0xc5,0x7e,0x67,0x85,0xa5,
+  0xa0,0xb5,0xfc,0x57,0xdc,0x08,0x6b,0x34,0x05,0x3d,0x3c,0x80,0x63,0x47,0x00,0x00,
+  0x50,0xf1,0xf0,0x76,0x94,0xdb,0x9e,0xce,0xb1,0xdd,0xa2,0x3c,0xf7,0xbf,0x1d,0x3d,
+  0x37,0x4f,0x9b,0x67,0x9a,0x5e,0xba,0xcf,0xd8,0xfd,0x57,0xbd,0x11,0x47,0x41,0x08,
+  0xdc,0x69,0x25,0x10,0xfc,0x02,0x00,0x40,0x55,0x40,0x7d,0x6d,0xf4,0xe8,0x0f,0xf4,
+  0xb7,0x71,0x85,0xb6,0xeb,0x6c,0xb8,0x76,0x4d,0xfe,0x22,0xcd,0xbe,0x90,0x12,0x95,
+  0xd5,0x88,0x63,0xf4,0x08,0x92,0x56,0x0a,0x3a,0xbf,0x0a,0x1a,0x73,0x7e,0x01,0x00,
+  0xa0,0x8a,0x48,0xb5,0xa3,0xf4,0xb0,0x8d,0xab,0xa5,0xc9,0xb9,0x62,0xef,0x5c,0x69,
+  0x29,0xe8,0xa4,0x5a,0x0a,0xda,0x6d,0x1c,0x92,0x55,0x61,0xdf,0x49,0x00,0x00,0x00,
+  0xb8,0x42,0x5d,0xa7,0xe8,0xe1,0xef,0x96,0xc2,0x76,0x33,0x9a,0xf4,0x9f,0xb4,0x71,
+  0x86,0xe9,0x75,0xfb,0x4a,0x9e,0xff,0x8a,0x1b,0x71,0x0c,0xb8,0xa5,0xa0,0x11,0xfc,
+  0x02,0x00,0x40,0x95,0xc1,0x77,0x81,0x97,0xdf,0xa7,0x54,0x3a,0xa5,0xed,0xb9,0xff,
+  0x95,0x15,0xf3,0x5c,0xbb,0x9e,0xf8,0x59,0x45,0xed,0x75,0xe6,0x96,0x60,0x89,0x1b,
+  0x71,0xe4,0x37,0xc2,0xca,0xa9,0x82,0x66,0xbf,0xd9,0xf4,0x1a,0x00,0x00,0x00,0x94,
+  0x1a,0x3a,0x73,0x28,0x15,0xf6,0x7a,0xf2,0x5c,0x41,0x84,0xeb,0xe0,0xb9,0x59,0x7d,
+  0x81,0xff,0xb6,0xe6,0x5a,0xd3,0xeb,0xf6,0x8f,0x94,0xff,0xa6,0x07,0x21,0xe9,0x37,
+  0xe2,0xe0,0x3b,0xbf,0x68,0x38,0x09,0x00,0x00,0xd5,0x07,0x25,0x62,0xf4,0xcc,0xc5,
+  0xde,0xf3,0xc9,0x3c,0xa5,0xfc,0x5f,0x36,0xd9,0x7c,0xd6,0x49,0xbf,0xfb,0x8f,0x8a,
+  0x4a,0x41,0xa7,0xfd,0xd7,0x79,0x0b,0x58,0x9c,0x82,0x4e,0x87,0xc0,0x98,0xb6,0x00,
+  0x00,0x00,0x55,0x0b,0x1d,0x78,0xc9,0x93,0xed,0x3a,0x84,0xb7,0x4e,0x9e,0x6b,0xd7,
+  0x93,0x17,0x50,0x05,0xa5,0xa0,0x47,0xfd,0x37,0xa6,0xdb,0x08,0x2b,0x55,0xf6,0x8c,
+  0xe0,0x17,0x00,0x00,0xaa,0x14,0x5e,0x32,0xf4,0xe4,0x2f,0x95,0x4a,0xa7,0x8a,0xf1,
+  0xdc,0x3c,0x35,0x1d,0x30,0xbd,0x6e,0xdf,0x18,0xf1,0x5f,0x8d,0x2a,0xe8,0x4c,0x23,
+  0x8e,0xe8,0x10,0x2a,0xaf,0x00,0x00,0xa0,0x9a,0xa1,0xdd,0xcf,0x69,0x6f,0xe3,0x7a,
+  0xf0,0xdc,0xac,0x3e,0x4f,0xeb,0xa6,0x99,0x5e,0xb4,0x7f,0xa4,0x4a,0xa0,0xf5,0x53,
+  0xd0,0xbd,0x68,0x38,0x09,0x00,0x00,0x55,0x0e,0x0d,0x74,0xd2,0xe3,0xe7,0x8a,0xb6,
+  0x71,0x8b,0xb7,0xda,0x51,0x4d,0xfc,0xbc,0x4d,0xe7,0xd0,0x13,0x3f,0xa5,0x78,0xa5,
+  0x1c,0x7a,0x2d,0xf0,0xdf,0xd1,0x46,0x58,0x79,0xe3,0x08,0x73,0xab,0xa0,0x87,0xfb,
+  0x91,0x7c,0x06,0x00,0x80,0x6a,0x87,0x88,0xd6,0x3f,0x16,0xb8,0xe7,0x66,0x74,0xdf,
+  0x39,0x3c,0xb8,0xee,0x3a,0x69,0x7a,0xd9,0x3e,0x31,0xea,0xbf,0x7a,0x8d,0x38,0x62,
+  0x15,0x37,0x0d,0x19,0x00,0x00,0x80,0x3e,0xd4,0xd5,0xc4,0xcf,0xff,0xfa,0x63,0xbb,
+  0xe7,0x88,0x75,0x5f,0xae,0x76,0xcc,0x37,0xbd,0x68,0x9f,0x18,0x2d,0x81,0xd6,0x49,
+  0x41,0x0f,0x10,0x46,0xfd,0x02,0x00,0x00,0x48,0x41,0x8b,0xc6,0x79,0x34,0x5c,0x75,
+  0xcf,0xcd,0xe8,0xde,0x7f,0xa3,0xa7,0x7e,0x55,0x21,0x1e,0x94,0xe3,0xbf,0x31,0xb7,
+  0x46,0x1c,0x99,0x2a,0xe8,0xd8,0x30,0x2a,0xaf,0x00,0x00,0x00,0x8c,0x40,0x0d,0xdb,
+  0x78,0xfd,0xb3,0xb4,0x74,0x2a,0x23,0x55,0xcf,0xfd,0xf7,0xac,0x98,0xed,0xa6,0xf5,
+  0xaf,0x34,0xe9,0x3f,0xa8,0xb3,0xd1,0xf4,0xa2,0xfd,0x80,0x39,0xa9,0x66,0x0a,0xda,
+  0x42,0xe5,0x15,0x00,0x00,0x80,0x0c,0xcc,0x2c,0x66,0x5f,0xa8,0xb7,0x8d,0x2b,0x8e,
+  0x6d,0xff,0x3d,0x57,0x36,0xcf,0xcd,0xea,0x73,0x5c,0x5b,0x9f,0x36,0xbd,0x66,0x9f,
+  0x50,0xf1,0xdf,0x4c,0x0a,0x3a,0x3a,0x64,0xfa,0x72,0x01,0x00,0x00,0x84,0x0b,0xda,
+  0xf7,0x42,0x51,0x29,0x65,0xb1,0x3e,0xe7,0xa8,0xa7,0x2e,0xa4,0xca,0xe8,0xbe,0x28,
+  0xf2,0x5f,0xa7,0x46,0x1c,0x98,0x76,0x04,0x00,0x00,0x20,0x0f,0x6e,0x10,0x8f,0xfd,
+  0x30,0x58,0xcf,0xb5,0x6b,0xe2,0x7f,0x50,0xfb,0x71,0xd3,0x8b,0xf6,0x03,0x9b,0xff,
+  0x4a,0x53,0xd0,0x38,0x76,0x04,0x00,0x00,0xa0,0x10,0xda,0x32,0xdb,0xc1,0x76,0x85,
+  0xdb,0xb8,0xa2,0xac,0xb2,0xba,0xee,0xf9,0x1c,0x6d,0x9c,0x6e,0x7a,0xc5,0x7e,0x60,
+  0x2b,0xc1,0x72,0x1b,0x47,0xc8,0xfd,0x17,0x95,0x57,0x00,0x00,0x00,0x04,0x50,0xe7,
+  0x29,0xba,0xff,0xcb,0xc1,0x7a,0x6e,0x56,0x9f,0xa5,0x99,0xe7,0x57,0x42,0x31,0x92,
+  0x43,0x09,0x96,0x20,0x05,0x9d,0x88,0x99,0xbe,0x56,0x00,0x00,0x00,0xa1,0x24,0x99,
+  0xa4,0xe7,0xae,0x29,0x28,0x9d,0xca,0xb3,0x5d,0x0f,0x56,0x6b,0xd3,0xdd,0x9f,0x1d,
+  0xd5,0xbf,0x70,0x67,0x6f,0xad,0x33,0xbd,0xe6,0xa2,0x91,0xf8,0x6f,0xd6,0x82,0x11,
+  0xfc,0x02,0x00,0x00,0x70,0x82,0x8e,0xae,0xd3,0xdb,0xc6,0x55,0xf2,0xdc,0x7f,0x11,
+  0xe9,0x9f,0xb9,0x5e,0x99,0x69,0x7a,0xc5,0x45,0x93,0xeb,0xbf,0xce,0x5b,0xc0,0x11,
+  0xf8,0x2f,0x00,0x00,0x00,0x27,0x28,0x1e,0xa5,0x3f,0xfc,0xdc,0x07,0xcf,0x75,0xb7,
+  0xdd,0x8c,0x66,0x9c,0x57,0x09,0xbd,0xa0,0x29,0xe9,0x1a,0x02,0xa7,0x1a,0x71,0x54,
+  0x40,0xa6,0x1d,0x00,0x00,0x40,0x90,0xd0,0x8e,0xf9,0x7a,0xdb,0xb8,0x19,0x89,0x0d,
+  0xb7,0xc0,0x73,0x33,0xba,0xeb,0x9f,0x78,0x22,0xfa,0xcc,0x61,0xd3,0x2b,0x2e,0x9a,
+  0xfc,0x14,0x74,0xac,0x20,0x04,0x1e,0x46,0xe5,0x33,0x00,0x00,0x00,0x77,0xa8,0xbf,
+  0x83,0xa6,0x7c,0x4d,0x16,0xe7,0x16,0xe1,0xb9,0x79,0x5a,0xf7,0x88,0xe9,0x15,0x17,
+  0x4d,0xca,0x7f,0x5d,0x1a,0x71,0x58,0x15,0x10,0xe3,0x03,0x00,0x00,0x08,0x1e,0x5a,
+  0x7a,0xa7,0x6b,0xe9,0xd4,0x67,0x3d,0x5a,0xad,0x50,0xd3,0xcf,0xa3,0x72,0xef,0x4a,
+  0xe1,0xec,0xbf,0x23,0x16,0x6c,0x51,0x45,0x34,0xbb,0x06,0x00,0x00,0x10,0x30,0xd4,
+  0xb0,0x5d,0xb6,0x8d,0x5b,0xb4,0xed,0x66,0xc4,0x82,0xe8,0x8e,0x13,0xa6,0x57,0x5c,
+  0x1c,0x02,0xff,0x8d,0xe5,0xfa,0x2f,0x2a,0xaf,0x00,0x00,0x00,0xc8,0xa1,0x64,0x9c,
+  0xf7,0x87,0x0c,0xce,0x73,0xef,0xfc,0x74,0x8e,0xb6,0xce,0x36,0xbd,0xe2,0xa2,0x71,
+  0xa9,0x82,0x8e,0xc7,0xe0,0xbf,0x00,0x00,0x00,0x14,0xa1,0xfd,0x4b,0x53,0x79,0x66,
+  0x07,0xc3,0xd5,0xf0,0xdc,0xcf,0xa4,0x95,0xe7,0xb9,0x13,0x3e,0x95,0xd6,0x1d,0xff,
+  0x48,0x4f,0x5e,0x50,0xf6,0xe3,0x08,0x5d,0x52,0xd0,0xe5,0xbe,0x34,0x00,0x00,0x00,
+  0x25,0x84,0x86,0x7a,0xe9,0xe1,0xff,0xf1,0x1a,0xde,0x7e,0xc6,0xa6,0x02,0xc3,0xcd,
+  0xd8,0x6e,0x46,0x2c,0xb2,0x2e,0xf7,0x71,0x84,0x05,0xfe,0xcb,0x0f,0x1c,0x8d,0xf8,
+  0x2f,0x82,0x5f,0x00,0x00,0x00,0xea,0x10,0xd1,0xba,0x69,0x5e,0x6d,0xd7,0x21,0xce,
+  0x75,0xd1,0x96,0x32,0x4f,0x41,0x73,0xff,0x15,0xa4,0xa0,0xd1,0x73,0x12,0x00,0x00,
+  0x80,0x2e,0xd4,0x73,0x86,0xcf,0x22,0x54,0xdf,0xc6,0xcd,0xc8,0xdd,0x6a,0x05,0xfa,
+  0x04,0x3d,0xf1,0x33,0x4a,0x94,0x73,0x87,0x8a,0x51,0xff,0xcd,0x4b,0x41,0x97,0x7d,
+  0x5e,0x1d,0x00,0x00,0x80,0x09,0xe8,0x85,0x5b,0x03,0xf4,0x5c,0xbb,0x58,0xd4,0xdc,
+  0x5c,0xce,0x8d,0x38,0x44,0xfe,0xcb,0xbf,0x51,0x20,0xf9,0x0c,0x00,0x00,0x40,0x1f,
+  0xaa,0x7f,0x85,0x6f,0xce,0xde,0xe5,0x90,0x52,0x96,0x66,0x95,0xd3,0xfa,0xa4,0x4d,
+  0x9f,0x70,0xd4,0xda,0x32,0x6f,0xc4,0x21,0x0c,0x81,0x01,0x00,0x00,0x00,0x7d,0x28,
+  0x3a,0x48,0x8f,0xfe,0x30,0x40,0xcf,0xcd,0xe8,0xf6,0x4f,0xd0,0xa3,0x3f,0x28,0x6f,
+  0xc3,0x2a,0xf0,0x5f,0xf4,0x9c,0x04,0x00,0x00,0xe0,0x19,0xda,0x30,0xdd,0x7b,0x56,
+  0x59,0xea,0xb9,0x76,0x4d,0xf8,0x34,0xb5,0xd4,0x9a,0x5e,0x6e,0x71,0xe4,0xfb,0x2f,
+  0x92,0xcf,0x00,0x00,0x00,0x3c,0x42,0x03,0x9d,0x34,0xf1,0xf3,0xfe,0x18,0xae,0xd0,
+  0x76,0x33,0xba,0xed,0xe3,0xb4,0xfa,0x01,0xd3,0xcb,0x2d,0x0e,0xf8,0x2f,0x00,0x00,
+  0x00,0xff,0xa0,0xa5,0x13,0xbc,0xa4,0x94,0x1d,0x3d,0xf7,0x1f,0x72,0xc4,0x6c,0x37,
+  0xa3,0xa9,0xdf,0xe2,0xa3,0x82,0xca,0x17,0xdb,0x29,0x24,0x24,0x9f,0x01,0x00,0x00,
+  0x14,0x09,0x9d,0xdc,0x43,0x77,0xfd,0x73,0xd1,0x71,0xae,0xc8,0x70,0x73,0xf4,0xf7,
+  0xfc,0x57,0x4f,0xed,0x31,0xbd,0xdc,0xe2,0x18,0x0d,0x81,0x11,0xfc,0x02,0x00,0x00,
+  0x28,0x96,0x78,0x94,0x4f,0x29,0xf2,0x92,0x52,0xfe,0x07,0x9b,0x72,0xad,0x56,0xa8,
+  0x5b,0x3f,0x46,0x2b,0x26,0x9a,0x5e,0x6d,0x71,0x64,0xab,0xb0,0xe0,0xbf,0x00,0x00,
+  0x00,0x8a,0x85,0x36,0x3d,0xa1,0xb1,0x8d,0xeb,0x14,0xde,0x3a,0x79,0xae,0x5d,0x53,
+  0xbe,0x4a,0xf1,0x88,0xe9,0xe5,0x16,0x41,0xda,0x7f,0x61,0xbe,0x00,0x00,0x00,0x7c,
+  0x80,0x06,0x3a,0x68,0xe2,0x39,0x01,0xda,0xae,0x5d,0xf5,0x9b,0x4d,0x2f,0xb7,0x08,
+  0xe0,0xbf,0x00,0x00,0x00,0xfc,0x83,0x18,0x2f,0x4e,0xc8,0xaf,0x9e,0xf2,0xd1,0x73,
+  0xb3,0xfa,0x3b,0x7a,0xe9,0x6e,0xd3,0xcb,0x2d,0x0e,0xf8,0x2f,0x00,0x00,0x00,0xff,
+  0xa0,0xa6,0x7d,0xbc,0x4b,0xa4,0x96,0xe1,0xaa,0x7a,0x6e,0xca,0x76,0x47,0x74,0xcb,
+  0x47,0xe9,0x91,0xef,0x96,0x77,0x23,0x0e,0x00,0x00,0x00,0xc0,0x47,0x12,0x31,0x3e,
+  0xa8,0xd7,0x07,0xab,0x1d,0xd5,0x2d,0x7f,0x67,0xd3,0x47,0xb3,0x62,0xbf,0xd4,0x56,
+  0x6f,0x7a,0xb5,0x00,0x00,0x00,0x40,0x58,0xa0,0x7d,0x2f,0x16,0xeb,0xb9,0xdc,0x76,
+  0x3f,0x2a,0xd0,0xb8,0xbf,0xcd,0xd1,0xba,0x69,0xa6,0xd7,0x0a,0x00,0x00,0x00,0x84,
+  0x05,0x8a,0x0c,0xd0,0xfd,0x5f,0xf2,0xc7,0x70,0x0b,0x3d,0xd7,0xae,0x87,0xbe,0x8d,
+  0xc9,0xb9,0x00,0x00,0x00,0x40,0x06,0x5a,0x7c,0x8b,0xea,0x36,0xae,0x5d,0xe3,0x3f,
+  0x92,0x96,0x8b,0xe7,0xda,0xc5,0xde,0xea,0xf4,0x41,0xd3,0x6b,0x05,0x00,0x00,0x00,
+  0xc2,0x02,0x35,0xee,0xc9,0x4f,0x3b,0x3b,0x6d,0xe3,0x66,0x3c,0x57,0xd5,0x76,0x3f,
+  0x6c,0xd3,0x87,0x68,0xf5,0x83,0xa6,0xd7,0x0a,0x00,0x00,0x00,0x84,0x86,0x44,0x8c,
+  0xa6,0xfd,0x6f,0xae,0xed,0x16,0x17,0xea,0xda,0x3d,0xd7,0xae,0xa9,0xdf,0xa6,0x64,
+  0xdc,0xf4,0x6a,0x01,0x00,0x00,0x80,0xb0,0x40,0x9b,0x9f,0xcc,0xb7,0x5d,0x55,0xab,
+  0xcd,0xe8,0x43,0x72,0x8d,0xff,0x28,0x9d,0x3e,0x64,0x7a,0xad,0x00,0x00,0x00,0x40,
+  0x58,0xa0,0x9e,0x66,0xba,0xe7,0x73,0x81,0x78,0xae,0x5d,0x37,0x7f,0x88,0x5e,0x9e,
+  0x64,0x7a,0xad,0x00,0x00,0x00,0x40,0x88,0xa0,0xe7,0xae,0x53,0xdd,0xc6,0xf5,0x60,
+  0xbb,0x19,0x4d,0xf9,0x5a,0x79,0xf7,0x82,0x06,0x00,0x00,0x00,0x7c,0x85,0x8e,0x6d,
+  0x51,0xdd,0xc6,0x55,0xf1,0xd9,0x3c,0xdd,0xf4,0x37,0x69,0x8d,0xff,0x08,0x9d,0xda,
+  0x6f,0x7a,0xad,0x00,0x00,0x00,0x40,0x58,0xa0,0xe8,0x10,0x3d,0xf0,0x95,0xa2,0x62,
+  0xdb,0x7c,0xcf,0xfd,0xa0,0x48,0x1f,0xa0,0x95,0xbf,0x37,0xbd,0x56,0x00,0x00,0x00,
+  0x20,0x44,0xd0,0xba,0x69,0x45,0x79,0xae,0xd8,0x70,0x53,0x9e,0x6b,0xd7,0xfd,0x5f,
+  0x46,0x23,0x0e,0x00,0x00,0x00,0x20,0x03,0x75,0x9d,0xa2,0x3b,0x3f,0xad,0x66,0xbb,
+  0x7f,0x93,0x95,0xa2,0xed,0x66,0xc4,0x5e,0xd2,0xb8,0xd3,0xf4,0x5a,0x01,0x00,0x00,
+  0x80,0xb0,0xc0,0x27,0x12,0x3e,0x3d,0x26,0x10,0xcf,0xbd,0xf1,0xfd,0x39,0x5a,0x76,
+  0xaf,0xe9,0xb5,0x02,0x00,0x00,0x00,0x21,0x82,0x0e,0x2c,0x73,0x2c,0x9d,0xf2,0x66,
+  0xb5,0x42,0x4d,0xfe,0x4f,0xa2,0xa4,0xe9,0xb5,0x02,0x00,0x00,0x00,0x61,0x81,0x86,
+  0xfa,0xe8,0x77,0x5f,0x28,0x36,0xbc,0x95,0x8a,0xbd,0xa4,0xe7,0xb4,0xe9,0xb5,0x02,
+  0x00,0x00,0x00,0x21,0x82,0x56,0xde,0xaf,0xe4,0xb9,0x1e,0x6c,0xf7,0x86,0xbf,0xce,
+  0x6a,0xed,0x23,0xa6,0x17,0x0a,0x00,0x00,0x00,0x84,0x08,0x6a,0xda,0xcf,0x77,0x7e,
+  0x8b,0xf2,0xdc,0xf7,0x65,0x95,0x31,0xdc,0xeb,0xdf,0x9b,0xd5,0x75,0x7f,0x45,0x0f,
+  0x7d,0xc7,0x42,0x15,0x34,0x00,0x00,0x00,0x30,0x0a,0xc5,0xa3,0xfc,0x88,0x90,0x97,
+  0x20,0xb7,0xc0,0x73,0xed,0xb6,0xcb,0x3c,0xd7,0xae,0x9b,0x3f,0x44,0xcd,0x47,0x4c,
+  0xaf,0x15,0x00,0x00,0x00,0x08,0x11,0xb4,0xea,0x01,0xb5,0x7c,0xf2,0xfb,0x72,0xe5,
+  0x10,0xea,0x3a,0x09,0xe3,0x08,0x01,0x00,0x00,0x00,0x1b,0xd4,0x52,0xcb,0xfb,0x4f,
+  0xaa,0x6c,0xe3,0xda,0xe5,0x62,0xb5,0x42,0x3d,0xf0,0x55,0xf6,0x47,0x99,0x5e,0x2b,
+  0x00,0x00,0x00,0x10,0x16,0xf8,0x41,0xe0,0x3f,0xfc,0x34,0x10,0xcf,0xbd,0xee,0xdd,
+  0x59,0xdd,0xf0,0x5e,0x6a,0xdc,0x65,0x7a,0xad,0x00,0x00,0x00,0x40,0x88,0xa0,0x5d,
+  0xcf,0x2b,0x6d,0xe3,0xba,0xe9,0x3d,0xa3,0x7a,0xb7,0xa3,0x96,0xde,0x6d,0x7a,0xa1,
+  0x00,0x00,0x00,0x40,0x88,0xa0,0xbe,0x36,0xde,0x8b,0x52,0xcf,0x76,0xdf,0x93,0x2b,
+  0x67,0xdb,0x1d,0xd1,0xb5,0xef,0xe6,0xe3,0x08,0x93,0x09,0xd3,0x6b,0x05,0x00,0x00,
+  0x00,0x42,0x03,0x11,0xcd,0xbe,0xd0,0xb7,0x38,0x37,0xcf,0x76,0x33,0xba,0xe9,0x83,
+  0xd4,0xd9,0x68,0x7a,0xa9,0x00,0x00,0x00,0x40,0x88,0xa0,0xbd,0x8b,0x9d,0x23,0x5f,
+  0x35,0xab,0x15,0x7a,0x6e,0x9e,0x36,0x3c,0x66,0x7a,0xa1,0x00,0x00,0x00,0x40,0x88,
+  0xa0,0xc8,0x20,0xdd,0xf3,0x59,0xff,0x3d,0xf7,0x9a,0xbf,0xcc,0xd1,0xd4,0x6f,0x59,
+  0x89,0xb8,0xe9,0xb5,0x02,0x00,0x00,0x00,0x21,0x82,0x5e,0xb8,0xb5,0x38,0xdb,0x7d,
+  0x57,0x56,0x79,0xb6,0x9b,0xd1,0x8d,0xef,0xa7,0x96,0x1a,0xd3,0x0b,0x05,0x00,0x00,
+  0x00,0x42,0x04,0x9d,0xdc,0xc3,0x5b,0x60,0x69,0x47,0xb8,0xef,0x1a,0x55,0x9e,0xdb,
+  0xbe,0x53,0xac,0x75,0xd3,0x4c,0x2f,0x14,0x00,0x00,0x00,0x08,0x11,0xbc,0x17,0xe5,
+  0x94,0xaf,0x7b,0xc9,0x2a,0x4b,0x3d,0xf7,0xea,0x77,0x64,0xf5,0xe0,0x37,0x4c,0x2f,
+  0x14,0x00,0x00,0x00,0x08,0x17,0xb4,0x75,0x76,0x20,0x9e,0x6b,0x17,0x7b,0x49,0xeb,
+  0x51,0xd3,0x0b,0x05,0x00,0x00,0x00,0x42,0x04,0x0d,0x74,0xf1,0x5e,0x94,0x2a,0x3b,
+  0xb9,0xba,0xb6,0x9b,0xd5,0xdb,0x69,0xd5,0xfd,0xa6,0x17,0x0a,0x00,0x00,0x00,0x84,
+  0x08,0xde,0x8b,0x72,0xc6,0x4f,0xf4,0x0c,0x57,0xd1,0x73,0x33,0xba,0xea,0x6d,0xf4,
+  0xd8,0x8f,0xac,0x64,0xd2,0xf4,0x5a,0x01,0x00,0x00,0x80,0x10,0xc1,0x7b,0x51,0x3a,
+  0xb9,0xad,0xdc,0x67,0x73,0x75,0xd5,0xdb,0x47,0xf5,0xb6,0x1c,0xdd,0xf4,0x41,0xea,
+  0x6a,0x32,0xbd,0x50,0x00,0x00,0x00,0x20,0x44,0xd0,0x40,0x27,0xdd,0xfa,0xb1,0x22,
+  0x3c,0xf7,0x6d,0x62,0x5d,0xf9,0xd6,0xac,0x7e,0xfb,0x17,0xb4,0x75,0xb6,0xe9,0x85,
+  0x02,0x00,0x00,0x00,0xe1,0x82,0x16,0xdd,0x1c,0x88,0xed,0xda,0xf5,0xc8,0xf7,0x2d,
+  0x42,0x0a,0x1a,0x00,0x00,0x00,0xc8,0x42,0x0d,0xdb,0x78,0x87,0x67,0xf7,0x6d,0xdc,
+  0xab,0x73,0xb3,0xca,0x2c,0xa4,0xcd,0xc8,0xc9,0x73,0xed,0xba,0xf6,0xdd,0xd4,0x79,
+  0xd2,0xf4,0x42,0x01,0x00,0x00,0x80,0x30,0x11,0x8f,0xd0,0xe4,0x2f,0xca,0xb7,0x71,
+  0xed,0xb6,0xab,0xe2,0xb9,0x5c,0x7f,0x9e,0xd5,0x86,0xc7,0x4d,0xaf,0x13,0x00,0x00,
+  0x00,0x08,0x17,0xb4,0x7a,0x8a,0xa3,0xed,0xea,0x86,0xba,0x76,0xcf,0xbd,0xf2,0xcf,
+  0xb2,0x7a,0xe8,0xdb,0x84,0x14,0x34,0x00,0x00,0x00,0x60,0x83,0x5a,0x8f,0xf2,0x2a,
+  0x68,0x95,0x9d,0x5c,0x47,0xfd,0x99,0x44,0xec,0xfd,0xbb,0x4e,0x99,0x5e,0x28,0x00,
+  0x00,0x00,0x10,0x22,0xf8,0x41,0xe0,0xfb,0xbf,0xec,0xb3,0xe1,0x16,0x0a,0x8d,0x38,
+  0x00,0x00,0x00,0x80,0x5c,0x68,0xed,0xc3,0x0a,0x29,0x65,0x4d,0xc3,0xbd,0x22,0x57,
+  0xf7,0x7f,0xc9,0x4a,0x44,0x4d,0x2f,0x14,0x00,0x00,0x00,0x08,0x11,0xd4,0x5a,0x47,
+  0xd7,0xbf,0x57,0xbe,0x8d,0xab,0x68,0xb5,0x19,0x5d,0xfe,0x96,0xac,0xae,0x7e,0x07,
+  0xc6,0x11,0x02,0x00,0x00,0x00,0x39,0x24,0xe2,0x34,0xf5,0xdb,0xda,0xa1,0xae,0xdc,
+  0x76,0xff,0x34,0x47,0x6b,0xa6,0x98,0x5e,0x27,0x00,0x00,0x00,0x10,0x2e,0x68,0xcb,
+  0xec,0xe2,0x3c,0xf7,0x4f,0x1d,0xf4,0xe6,0xac,0x7e,0xf7,0x1f,0x68,0xc4,0x01,0x00,
+  0x00,0x00,0xd8,0xa1,0xfe,0x0e,0xba,0xe1,0xbd,0xfe,0x7b,0x6e,0x46,0x97,0xfd,0x09,
+  0xff,0xe7,0xe9,0xc3,0xa6,0x17,0x0a,0x00,0x00,0x00,0x84,0x08,0x5e,0x05,0xfd,0x87,
+  0xf3,0x1d,0x6c,0xf7,0x2d,0x39,0xd2,0xb5,0x5d,0xbb,0x96,0xdd,0x6b,0x7a,0xa1,0x00,
+  0x00,0x00,0x40,0xb8,0xa0,0x2d,0x4f,0x29,0x6d,0xe3,0x0a,0x7d,0xb6,0xd0,0x6a,0x85,
+  0xfa,0xdd,0x39,0x14,0x8f,0x98,0x5e,0x28,0x00,0x00,0x00,0x10,0x22,0xa8,0xb3,0x91,
+  0xae,0x79,0x97,0x46,0x6c,0xab,0xe8,0xb9,0x76,0xfd,0xf6,0xad,0xd4,0xb4,0xdf,0xf4,
+  0x42,0x01,0x00,0x00,0x80,0x30,0x41,0x44,0x8f,0xfd,0xd0,0x7f,0xcf,0xbd,0xf4,0x8d,
+  0x39,0x5a,0xf3,0xa0,0xe9,0x75,0x02,0x00,0x00,0x00,0xe1,0x82,0xb6,0xcf,0x53,0xdd,
+  0xc9,0x15,0xeb,0x4d,0x59,0xe5,0xd9,0x6e,0x46,0x0f,0x7c,0xcd,0x4a,0x26,0x4c,0x2f,
+  0x14,0x00,0x00,0x00,0x08,0x11,0xd4,0xdb,0x4a,0x37,0x7d,0x50,0x3f,0xd4,0x95,0x79,
+  0xee,0x25,0x36,0xfd,0xf6,0x6d,0xd4,0x56,0x6f,0x7a,0xa1,0x00,0x00,0x00,0x40,0x98,
+  0xa0,0x24,0x3d,0xf9,0x0b,0x85,0x94,0xf2,0x9b,0x72,0xe5,0x60,0xb5,0x76,0x5d,0xfc,
+  0x86,0xac,0xd6,0x3e,0x64,0x7a,0x9d,0x00,0x00,0x00,0x40,0xb8,0xa0,0xdd,0xcf,0x2b,
+  0x6d,0xe3,0x4a,0x3d,0xf7,0xe2,0xd7,0x3b,0xea,0x81,0xaf,0x50,0x12,0x8d,0x38,0x00,
+  0x00,0x00,0x80,0x2c,0x14,0x1d,0xa4,0x1b,0xdf,0x1f,0x88,0xed,0x5e,0xfc,0xda,0xb4,
+  0xd8,0x6f,0x6b,0xab,0x33,0xbd,0x50,0x00,0x00,0x00,0x20,0x5c,0xd0,0x8c,0xf3,0x14,
+  0x0c,0xf7,0x0d,0x59,0xe5,0x98,0xec,0xeb,0x72,0xf5,0x5a,0xb1,0x56,0x4c,0x34,0xbd,
+  0x4a,0x00,0x00,0x00,0x20,0x5c,0xa4,0x52,0xd0,0x6f,0x92,0x6d,0xe3,0xbe,0xde,0xc1,
+  0x76,0x1d,0x0c,0x37,0x4f,0x13,0xcf,0xa1,0x38,0xc6,0x11,0x02,0x00,0x00,0x00,0x59,
+  0x78,0x2f,0xe8,0x9b,0x3e,0x28,0x2e,0x9d,0x72,0x0c,0x75,0x15,0x3c,0x77,0xac,0x4d,
+  0x97,0xbd,0x99,0xce,0xa0,0x17,0x34,0x00,0x00,0x00,0x60,0x83,0x88,0xe6,0x5e,0x2a,
+  0xdf,0xc6,0x55,0xd4,0x58,0x07,0xad,0x98,0x64,0x7a,0x9d,0x00,0x00,0x00,0x40,0xb8,
+  0xa0,0x86,0x6d,0xfc,0x60,0x91,0xef,0x9e,0x3b,0xe6,0x35,0x59,0xdd,0xf1,0x09,0x2b,
+  0x19,0x37,0xbd,0x50,0x00,0x00,0x00,0x20,0x44,0x50,0x22,0x4a,0x77,0x7e,0xba,0x38,
+  0xcf,0x3d,0x3b,0x2d,0xbb,0xe7,0xda,0xc5,0x7e,0xcf,0xa9,0xbd,0xa6,0x17,0x0a,0x00,
+  0x00,0x00,0x84,0x0b,0x5a,0x76,0x8f,0x5e,0x78,0x3b,0xe6,0xec,0x5c,0xd9,0xdd,0xf6,
+  0xd5,0x02,0x5d,0xf4,0x2a,0x5a,0x7c,0xab,0xe9,0x55,0x02,0x00,0x00,0x00,0xe1,0x82,
+  0x4e,0xed,0xe7,0xe7,0x7f,0x35,0x6c,0xf7,0x35,0x72,0xcf,0x1d,0xb1,0xdd,0x8c,0x26,
+  0x7c,0x1a,0xe3,0x08,0x01,0x00,0x00,0x00,0x3b,0x94,0x88,0xd3,0xed,0xff,0x20,0xdf,
+  0xc6,0x55,0xb1,0x5d,0xbb,0xe7,0xda,0x35,0xf6,0x6c,0x3a,0xb1,0xcb,0xf4,0x42,0x01,
+  0x00,0x00,0x80,0x70,0x41,0x4b,0x6e,0x53,0xf0,0x5c,0x85,0x38,0xd7,0x45,0x0b,0xae,
+  0x32,0xbd,0x4a,0x00,0x00,0x00,0x20,0x5c,0x50,0xe3,0x1e,0x7e,0xfe,0xd7,0x7f,0xdb,
+  0x3d,0x2b,0xab,0xf1,0x1f,0xb1,0xa2,0x83,0xa6,0x17,0x0a,0x00,0x00,0x00,0x84,0x89,
+  0x78,0x84,0x26,0x7c,0x4a,0xcf,0x6a,0xd9,0xff,0xbf,0xea,0x6d,0x12,0xfd,0xf6,0x2f,
+  0xb2,0xba,0xe6,0x9d,0xcc,0xe5,0x4d,0xaf,0x13,0x00,0x00,0x00,0x08,0x17,0x74,0x6a,
+  0x1f,0xd5,0xae,0x17,0xab,0x66,0xad,0x40,0xec,0xff,0x37,0x6c,0xa3,0x86,0xed,0x0e,
+  0xda,0x26,0xd0,0x60,0x97,0xe9,0x55,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x11,0x8a,0x0f,0x53,0x5f,0x1b,0xef,
+  0x4d,0xd1,0xb8,0x9b,0x6a,0xd7,0xd1,0xc1,0xe5,0xa1,0x53,0xdd,0x06,0x7e,0x6d,0xa7,
+  0x0f,0x52,0x7f,0x3b,0xbb,0x5a,0x7f,0x56,0xdd,0x52,0xeb,0xf1,0x62,0x8e,0xac,0xe2,
+  0x17,0xc3,0xd4,0x73,0x9a,0x22,0xfd,0xbe,0x5c,0x0c,0x00,0x00,0x80,0x2a,0x81,0x77,
+  0xa2,0x68,0x39,0x4a,0x9b,0xfe,0x40,0x33,0x7f,0x41,0x93,0xbe,0x40,0xb7,0x7f,0x82,
+  0x8f,0xe7,0xbb,0xe9,0x03,0x74,0xfd,0x7b,0xe9,0xba,0xf7,0x84,0x4e,0x37,0xfc,0x35,
+  0xbf,0xb6,0x9b,0xff,0x86,0x5f,0x27,0xbb,0xda,0x59,0xbf,0xa6,0x57,0xfe,0xc0,0xaf,
+  0xbf,0x88,0x61,0x07,0xb4,0x73,0xbe,0xc7,0x8b,0xb9,0xfe,0xaf,0xf8,0xc5,0x30,0xdd,
+  0xfa,0x31,0xba,0xef,0x5f,0xe9,0xb1,0x1f,0xd2,0xca,0xdf,0x53,0xfd,0x16,0x8a,0xa1,
+  0xed,0x15,0x00,0x00,0x80,0x42,0xc8,0x8a,0x0e,0x52,0x47,0x03,0xed,0x5d,0x4c,0x4f,
+  0x8f,0xa1,0x1b,0xde,0x47,0x17,0xa5,0x8e,0xdb,0x5c,0x78,0x16,0x5d,0xf8,0xff,0xca,
+  0x4d,0x67,0xa5,0x4e,0x06,0xbd,0x9a,0x9b,0xe0,0xbc,0xcb,0xd9,0x8a,0xac,0xce,0x46,
+  0xdd,0x23,0xb7,0xd4,0xdb,0x4a,0x97,0xbe,0xd1,0xa7,0x8b,0x49,0x5d,0xcf,0x95,0x6f,
+  0xa5,0xe9,0xe7,0xd1,0xf6,0xf9,0xd4,0x76,0xcc,0x1a,0xee,0xe3,0x37,0x1c,0x00,0x00,
+  0x40,0x95,0x33,0xdc,0x4b,0x87,0x57,0xf2,0xd6,0x4f,0x77,0x7c,0x82,0xdb,0x96,0x79,
+  0x03,0xf5,0x55,0x6c,0x45,0x2c,0x2e,0x7e,0x71,0x02,0xd5,0xae,0xb7,0x22,0x03,0x8a,
+  0xb7,0x84,0x28,0x49,0xf7,0x7f,0x39,0x80,0x8b,0x39,0x8b,0xc7,0xe9,0xcf,0x5d,0x4b,
+  0x07,0x97,0x5b,0xfd,0xed,0x81,0xfe,0x54,0x01,0x00,0x00,0x84,0x16,0x9e,0x67,0x3e,
+  0xb6,0x89,0x8f,0x9e,0xbf,0xf1,0x7d,0xe5,0x19,0xea,0xaa,0xeb,0x2c,0x1a,0xf7,0x61,
+  0x7a,0xf6,0x2a,0xbe,0xde,0x84,0x52,0x5e,0x9a,0xd6,0x4c,0x0d,0xf0,0x7a,0xae,0x7b,
+  0x37,0xcf,0xed,0xef,0x59,0x48,0xca,0x5f,0x09,0x00,0x00,0x00,0x54,0x06,0xd4,0x7d,
+  0x86,0x16,0xde,0x44,0xb7,0x7f,0x3c,0x95,0x67,0x36,0xee,0x8f,0x25,0xd1,0x98,0x57,
+  0xf3,0xf5,0x2e,0x1a,0x4f,0xbd,0xcd,0xf2,0xfb,0xd3,0x56,0xcf,0x7b,0x51,0x06,0x7a,
+  0x3d,0x37,0xbc,0x8f,0xef,0x56,0x37,0xd7,0x10,0x21,0x1d,0x0d,0x00,0x00,0x55,0x40,
+  0x32,0x41,0x35,0x6b,0x78,0x56,0xf6,0x92,0x37,0x98,0xf7,0xc4,0xd2,0xeb,0xd2,0x37,
+  0xd2,0x84,0x7f,0xa4,0x9a,0xd5,0xec,0x3e,0xb8,0xde,0xa5,0x24,0xdd,0xf7,0xef,0x81,
+  0x5f,0xcc,0xd8,0xb3,0x69,0xdc,0x87,0x68,0xcb,0x53,0x98,0x4b,0x08,0x00,0x00,0x15,
+  0x4e,0x7f,0x3b,0x2d,0x1e,0x4f,0x17,0xbf,0xde,0xbc,0x0f,0x9a,0xd5,0x25,0xaf,0xa7,
+  0x17,0xef,0xa0,0x3e,0xb7,0x4d,0x58,0x5a,0xfd,0x60,0x89,0x2e,0xe6,0xa2,0x57,0xd1,
+  0xcc,0xf3,0xa9,0xe5,0xa8,0x85,0x40,0x18,0x00,0x00,0x2a,0x11,0xea,0x38,0x41,0xb3,
+  0x2e,0xe0,0xd3,0x7c,0x8c,0xdb,0x5f,0x18,0xc4,0xee,0xc3,0x53,0xbf,0x66,0xf7,0xc4,
+  0xf1,0x76,0xb5,0xd4,0x96,0x34,0x45,0x70,0xdf,0xbf,0x51,0xdd,0x46,0x58,0x30,0x00,
+  0x00,0x54,0x18,0xd4,0x5a,0xc7,0x8f,0xa3,0x5e,0xe4,0xa9,0xce,0x6a,0xec,0x6b,0xf9,
+  0x1c,0x9f,0xeb,0xdf,0xcb,0x33,0xb7,0x13,0x3e,0x15,0x22,0xdd,0xfe,0x0f,0xfc,0xc8,
+  0xed,0x65,0x6f,0xa2,0x8b,0x5f,0xe7,0x65,0x5d,0xec,0x6e,0xb0,0x7b,0xd2,0x76,0x4c,
+  0x7c,0xcb,0x12,0x31,0xba,0xe7,0x73,0xf2,0x77,0xb8,0xfd,0xe3,0xd9,0xeb,0xb9,0xf9,
+  0x83,0x74,0xed,0xbb,0xf9,0xc5,0x78,0xbb,0xcf,0x13,0x3e,0x49,0x07,0x5e,0xc2,0x76,
+  0x30,0x00,0x00,0x54,0x0c,0x34,0xd0,0x49,0x53,0xbe,0xc2,0x0b,0x90,0xb4,0xec,0xe0,
+  0x9a,0x77,0xd2,0xc3,0xdf,0xa6,0xa5,0x13,0x68,0xcf,0x42,0xab,0x6e,0x93,0x75,0x7c,
+  0xab,0xd5,0xb4,0xcf,0x6a,0xda,0x1f,0x22,0x9d,0xda,0x6b,0x1d,0xdf,0x62,0xd5,0xae,
+  0xa5,0x7d,0x8b,0x69,0xf9,0x7d,0xf4,0xf8,0xb9,0x34,0xfe,0x6f,0x35,0xa3,0xe0,0x57,
+  0xd3,0x83,0xdf,0x60,0xf7,0x47,0x7c,0xdf,0x96,0xdc,0x21,0x7b,0x87,0xb3,0x68,0xdb,
+  0xd3,0xd9,0xeb,0x39,0xb1,0xc3,0xaa,0xdf,0x4c,0xfb,0x5e,0xa0,0x35,0x0f,0xd2,0x13,
+  0x3f,0xe5,0x75,0xce,0xba,0x16,0x3c,0xee,0x43,0xc4,0xee,0x33,0x00,0x00,0x80,0xf2,
+  0x87,0x86,0x07,0x68,0xda,0xf7,0x55,0xcd,0x77,0xec,0xd9,0x74,0xc5,0x9f,0xd1,0xd4,
+  0x6f,0xf0,0x5e,0x1c,0x3d,0xa7,0xad,0xa1,0x5e,0x2b,0x1e,0xb1,0x28,0x69,0x7a,0x11,
+  0x32,0xd8,0x15,0xb2,0xeb,0x1c,0xee,0xe3,0xad,0x33,0x0e,0xae,0xa0,0x3f,0xfc,0x82,
+  0xae,0xf9,0x4b,0x1a,0xab,0x96,0x69,0x67,0x77,0x86,0xdd,0x9f,0xe8,0x90,0xe0,0x5d,
+  0x4f,0x1f,0x94,0xa7,0xeb,0x5f,0xb8,0xb5,0xe0,0x65,0xc4,0x62,0x67,0x7e,0x31,0x3d,
+  0x67,0xf8,0x8c,0xc2,0xe9,0xe7,0xd1,0x55,0x6f,0xe7,0x37,0x56,0xd5,0x82,0x3f,0x4c,
+  0x2d,0xb5,0x25,0xb8,0x67,0x00,0x00,0x00,0x02,0x24,0x11,0xa3,0x25,0xb7,0xab,0x3e,
+  0xf9,0xaf,0x7b,0x0f,0x3d,0x73,0x09,0x9d,0xd8,0x45,0xe1,0x37,0x5c,0x19,0xd4,0x7a,
+  0x94,0xe6,0x8c,0xe5,0xfd,0x2e,0x14,0x0f,0x58,0xbd,0x38,0x81,0x9b,0x66,0xe1,0xfb,
+  0xdc,0xf5,0x4f,0x92,0x17,0xde,0xf6,0xf7,0x56,0x3c,0x2a,0xb9,0x98,0x96,0x1a,0x7a,
+  0xf6,0xb7,0xbc,0x25,0x97,0x62,0x5e,0xfa,0xfe,0x2f,0x39,0x85,0xe4,0x00,0x00,0x00,
+  0xca,0x02,0x3a,0xb2,0x9a,0xae,0x78,0x8b,0x52,0x0c,0x38,0xf1,0x1c,0xda,0x3e,0x57,
+  0xb1,0x3d,0x45,0x59,0xc0,0xdb,0x58,0x1d,0x59,0x45,0x53,0xbf,0xa5,0xb4,0x3b,0xcc,
+  0xee,0x52,0xcd,0x1a,0xc1,0x9b,0x48,0x53,0xd0,0xec,0xd6,0x35,0xee,0x56,0xb8,0x18,
+  0xe2,0x7b,0xbb,0x93,0xff,0x4b,0xa9,0xfe,0x8d,0xd9,0xf4,0x8b,0x77,0x94,0x41,0xda,
+  0x01,0x00,0x00,0x80,0x08,0x8a,0xf4,0xd3,0xc4,0xcf,0x2b,0x05,0x5c,0x4f,0xfe,0x92,
+  0x6f,0x5f,0x56,0xe4,0x03,0xbf,0xad,0x9e,0x77,0xbe,0x52,0x71,0xbd,0x49,0x5f,0x28,
+  0x1c,0x5a,0x44,0x27,0x76,0xd2,0x18,0x59,0xea,0xf8,0x85,0xdb,0xd4,0x2e,0x85,0xac,
+  0x33,0x87,0x78,0xd1,0xb5,0x4a,0x14,0x7c,0xf5,0x3b,0xe8,0xe4,0x1e,0xdf,0x6f,0x06,
+  0x00,0x00,0x80,0x12,0x40,0xeb,0xa7,0x29,0xf9,0xce,0x63,0x3f,0xa4,0xde,0x16,0xd3,
+  0x17,0x1b,0x20,0xbc,0xfc,0x8c,0xb9,0x9e,0xf4,0x3e,0x8c,0x3d,0x9b,0xd6,0x3f,0x9a,
+  0xff,0xda,0x58,0x84,0x6e,0xfb,0xb8,0xe4,0x85,0x77,0x7e,0x5a,0x3d,0x6f,0xc0,0x77,
+  0xa8,0xa7,0x9f,0xa7,0xf4,0xa5,0x68,0xda,0xf7,0x29,0x59,0x89,0xdf,0x88,0x00,0x00,
+  0xa0,0xa2,0xa1,0xa1,0x1e,0x1a,0x27,0x2d,0x06,0x3e,0x8b,0x1e,0xf9,0x1e,0x0d,0x76,
+  0x99,0xbe,0xd8,0xc0,0xa1,0xc8,0x00,0x3d,0xfc,0x5d,0x79,0xe0,0x39,0xee,0x43,0x82,
+  0x10,0x78,0xe1,0x8d,0xb2,0x74,0xf1,0xab,0xa8,0xe9,0x80,0xc6,0xc5,0xb0,0x1f,0xcd,
+  0xb4,0xff,0x95,0xf7,0xdc,0xbe,0xf8,0xf5,0x54,0xbf,0xd9,0xd7,0xdb,0x00,0x00,0x00,
+  0x20,0x70,0x68,0xcb,0x6c,0x79,0x84,0x75,0xe3,0x07,0x78,0x91,0x73,0x75,0xc0,0x07,
+  0x2c,0xde,0xfe,0x09,0xf9,0x3d,0xd9,0xf6,0x4c,0xfe,0x0b,0x4f,0xec,0x90,0x57,0x8f,
+  0x2f,0x1a,0xaf,0x77,0x31,0xbd,0xcd,0x34,0xfe,0x23,0xf2,0x8b,0x99,0x71,0x1e,0x3a,
+  0x72,0x00,0x00,0x40,0x79,0xc1,0x4b,0x7d,0xdc,0x9f,0xed,0xcc,0x53,0x36,0x3c,0x5e,
+  0x55,0xdd,0x1e,0x68,0xef,0x0b,0xbc,0xf3,0xa4,0xfb,0x6d,0x79,0xe0,0x2b,0x79,0xad,
+  0xa1,0x29,0x1e,0x95,0x67,0x12,0xee,0xfc,0x8c,0x95,0x90,0x54,0x41,0xe7,0xbc,0x27,
+  0x63,0xd7,0xf3,0xbc,0x73,0x88,0xfb,0xdb,0x5e,0xfe,0xa7,0xd4,0x73,0xc6,0xef,0xdb,
+  0x00,0x00,0x00,0x20,0x28,0x78,0xab,0xc9,0x4b,0x65,0xbd,0x13,0xef,0xfb,0x77,0x6b,
+  0xb8,0xd7,0xf4,0x95,0x96,0x14,0xbe,0x99,0x3b,0xe5,0xab,0x72,0xcb,0x6b,0xaf,0xcf,
+  0x7f,0xe1,0xfc,0x2b,0x65,0xb9,0xe2,0xd7,0xd1,0xa9,0x7d,0x7a,0x57,0x13,0x8f,0xf0,
+  0x86,0x21,0xd2,0x10,0x78,0xf3,0x93,0xbe,0xad,0x1f,0x00,0x00,0x40,0xc0,0xd0,0xa6,
+  0x27,0xe4,0x0f,0xf6,0x8d,0x4f,0xa8,0xbe,0x5b,0x6f,0x2b,0x3f,0xc7,0xe4,0x2e,0x97,
+  0x46,0xca,0x03,0x9d,0xf2,0x97,0x97,0x4c,0x0b,0x6f,0x92,0xdf,0x99,0x57,0xf2,0xef,
+  0x0c,0xd5,0xae,0x97,0x9f,0x23,0x5e,0x7a,0x97,0xf6,0x8f,0x69,0xdf,0x12,0xf9,0xc5,
+  0x4c,0xfb,0xbe,0xee,0xdb,0x02,0x00,0x00,0x30,0x05,0x9f,0xb3,0xe0,0xfe,0x54,0xbf,
+  0xe6,0x1d,0xea,0x1d,0x1e,0x58,0x3c,0x48,0x97,0xbe,0x89,0x17,0x2f,0xb9,0xe8,0xa1,
+  0xef,0x38,0xbe,0x7c,0xf5,0x14,0xc9,0x6b,0x4b,0x2c,0xa9,0xe5,0x3d,0xf5,0xeb,0xfc,
+  0x25,0xc4,0xa3,0x74,0xd3,0x07,0x25,0xaf,0xba,0xe5,0xef,0x24,0x33,0x0d,0x0b,0xef,
+  0x4c,0x74,0x90,0x77,0xd5,0x76,0x7f,0xdb,0x1b,0xfe,0x9a,0x62,0xc3,0x5a,0x6f,0x0b,
+  0x00,0x00,0xc0,0x14,0x7c,0x98,0x8e,0xfb,0x53,0xfd,0xf1,0x73,0xd5,0x77,0x7e,0x79,
+  0x23,0x0b,0xe9,0x1b,0x5e,0xf1,0x67,0x8e,0x5d,0x94,0x9f,0xbe,0x48,0x6e,0x79,0xa1,
+  0xd2,0xc4,0x73,0x04,0xab,0x98,0x77,0x85,0xfc,0x85,0x4d,0x07,0xb5,0x7f,0x52,0x8f,
+  0xff,0x9f,0xe4,0x3d,0x2f,0x79,0x03,0xb6,0x80,0x01,0x00,0xa0,0x2c,0xa0,0x64,0x42,
+  0x5e,0x2f,0xb4,0xfc,0x5e,0xbd,0xf7,0x5c,0x31,0x51,0xee,0x3e,0xbb,0xff,0x28,0x7e,
+  0xed,0xfd,0x5f,0x36,0x6f,0xa9,0x5a,0x1a,0xf7,0x61,0xc1,0x2a,0x8e,0xac,0x92,0xa7,
+  0xa0,0x5f,0x9c,0xa0,0xfd,0xc3,0x52,0xe9,0x0e,0xda,0x5c,0xa3,0xfb,0xb6,0x00,0x00,
+  0x00,0x4a,0x0f,0x6f,0x7b,0x75,0xed,0xbb,0x24,0x8f,0xf4,0xed,0x73,0xf5,0xde,0xf3,
+  0xf4,0x61,0x79,0x17,0xc7,0x27,0x7e,0x2a,0x7e,0xed,0x9d,0x9f,0x32,0x6f,0xa9,0x5a,
+  0xba,0xe2,0x2d,0x82,0x55,0x0c,0xf7,0xf2,0xfe,0xd8,0xee,0x2f,0xbc,0xfb,0x9f,0x49,
+  0xd4,0x44,0xda,0xed,0xc6,0xbe,0xf2,0xa4,0xfc,0x7a,0x8e,0xae,0xd7,0x7a,0x4f,0x00,
+  0x00,0x00,0x46,0xe0,0xed,0x1d,0xae,0x7a,0x9b,0xe4,0x91,0x7e,0x70,0x85,0xde,0x7b,
+  0xaa,0x0c,0xc3,0xbd,0xee,0xdd,0xec,0x8f,0x16,0xbc,0xf6,0x0e,0x85,0x53,0xb7,0xa1,
+  0xd2,0xc5,0xaf,0x17,0xde,0x03,0x7a,0xea,0x57,0xb2,0x17,0xbe,0x96,0xce,0x1c,0xd2,
+  0xbb,0xb1,0x87,0x57,0xc9,0xaf,0xe7,0xd0,0xcb,0x5a,0xef,0x09,0x00,0x00,0xc0,0x08,
+  0xa9,0xf8,0x57,0x36,0x79,0x76,0xd3,0x0c,0xed,0xb7,0x5d,0xf5,0x80,0xdc,0x29,0xf6,
+  0x2c,0x16,0xbc,0xf0,0xde,0x7f,0x35,0x6f,0xa9,0x5a,0xba,0xfa,0xed,0xe2,0x3b,0x70,
+  0x78,0xa5,0xfc,0xb5,0x85,0xe3,0x08,0xdd,0xef,0xea,0xe6,0x27,0xe5,0xef,0x79,0xec,
+  0x15,0xdd,0x1f,0x16,0x00,0x00,0x00,0x23,0xd0,0x6d,0x1f,0xf3,0xd7,0x26,0xf8,0x7b,
+  0xb6,0x1c,0x95,0xa7,0xa0,0x9f,0xbc,0x40,0xf0,0xc2,0x47,0x7f,0x60,0xde,0x52,0xb5,
+  0x34,0xe1,0x53,0xe2,0x3b,0x10,0x1d,0xa4,0x6b,0xde,0x29,0x7f,0xad,0x4e,0x0a,0x9a,
+  0x5e,0x9c,0x20,0xbb,0x9e,0xb3,0xa8,0xbd,0x41,0xf7,0x87,0x05,0x00,0x00,0xc0,0x08,
+  0xf4,0xfb,0xff,0x96,0x3c,0xd5,0xa7,0x7c,0x95,0x34,0x0f,0xcb,0x58,0x94,0xa4,0xbb,
+  0xff,0x45,0xf2,0xb6,0xd7,0xbf,0x97,0x22,0x03,0xf9,0xaf,0x7b,0xe6,0x52,0xf3,0x96,
+  0xaa,0xa5,0x87,0xbf,0xeb,0x78,0x0f,0x66,0x9e,0x2f,0x79,0xed,0xd8,0xd7,0xa8,0x37,
+  0xe2,0xe0,0x85,0xe5,0x53,0xbf,0x29,0x79,0xc3,0xcb,0xdf,0x4c,0x7d,0xad,0x7a,0x3f,
+  0x29,0x00,0x00,0x00,0x86,0xa0,0x79,0x97,0x4b,0x9e,0xea,0x57,0xfe,0x39,0x75,0x37,
+  0x69,0xbf,0xed,0xb2,0x7b,0x24,0x6f,0x7b,0xd1,0xab,0xe9,0xf0,0xca,0xfc,0x57,0xad,
+  0x7b,0x44,0x6e,0x79,0x97,0xbe,0x91,0xae,0x7a,0x7b,0x58,0xf4,0xd2,0xdd,0x8e,0x77,
+  0x60,0xcf,0x42,0xf9,0xcb,0xd7,0x3e,0xac,0x7a,0x3f,0x7b,0x9b,0xe9,0xca,0xb7,0x4a,
+  0xee,0xcc,0xf8,0x8f,0x5a,0xc9,0xca,0x19,0xca,0x0c,0x00,0x00,0x95,0x0d,0xed,0x98,
+  0x2f,0xb3,0xbc,0xb3,0x68,0xe5,0x64,0xed,0xb7,0x3d,0x73,0x88,0x1f,0x47,0x75,0x7f,
+  0xe7,0x67,0x2e,0xc9,0x7f,0x55,0xe3,0x1e,0xf9,0xc9,0x9d,0x07,0xbf,0x49,0x9d,0x27,
+  0xa9,0xab,0x29,0x14,0x1a,0xce,0x1f,0x81,0x94,0x5d,0x4b,0x3c,0x22,0x7f,0xb9,0xa8,
+  0x08,0x4d,0xfc,0x6e,0x6b,0xa6,0xca,0xa7,0x20,0xcd,0x3c,0x5f,0xf7,0xc7,0x04,0x00,
+  0x00,0xc0,0x14,0xbc,0x04,0xfa,0x8a,0xb7,0x48,0x1e,0xec,0x77,0x7c,0x52,0xbd,0x05,
+  0x56,0xfa,0x6d,0x29,0x49,0x13,0xcf,0x91,0xbc,0xed,0x8d,0xef,0xcb,0x4b,0x41,0x73,
+  0xcf,0x92,0x0e,0x1e,0x62,0xf1,0x6f,0xe3,0x6e,0x5f,0xef,0x41,0xd8,0xa1,0x81,0x2e,
+  0x9a,0xf0,0x69,0xf9,0xd7,0xa4,0x7d,0x4b,0x4c,0x5f,0x29,0x00,0x00,0x00,0x55,0xf8,
+  0x78,0x9d,0xe9,0x3f,0x96,0xe5,0x8a,0xcf,0xa2,0x65,0xf7,0xe8,0x8e,0xb7,0xa3,0x15,
+  0x93,0xe4,0xc9,0xe4,0xba,0x8d,0xf9,0xaf,0x5a,0x2a,0xad,0x32,0xfa,0x7f,0x34,0xfd,
+  0x3c,0xad,0xca,0xa5,0x32,0x87,0x68,0xf9,0x44,0x79,0x33,0xcc,0xeb,0xde,0x53,0x38,
+  0x8f,0x18,0x00,0x00,0x40,0x98,0xa1,0xfd,0x4b,0x69,0xcc,0x6b,0x24,0x8f,0xf7,0x6b,
+  0xdf,0x4d,0xa7,0xf5,0x5a,0x26,0x52,0x73,0x0d,0x3f,0xe5,0xea,0xfe,0xb6,0x0b,0xae,
+  0xc9,0x7f,0x55,0x4b,0x2d,0x8f,0x70,0xa5,0x21,0xf0,0x8e,0x79,0x55,0x32,0x0f,0x91,
+  0x9a,0x8f,0xc8,0xbb,0x79,0x30,0xcd,0xbb,0x92,0xfd,0x5e,0xd3,0x17,0x0b,0x00,0x00,
+  0x40,0x03,0x7e,0x58,0x66,0xc2,0x3f,0xca,0x9f,0xf0,0x93,0xff,0x8b,0x7a,0x5b,0x34,
+  0xde,0x36,0x11,0xa3,0xbb,0x3e,0x23,0x79,0xcf,0x5b,0x3e,0x46,0xb1,0x48,0xce,0xab,
+  0x92,0x09,0x9a,0xf6,0x3d,0xf9,0xc5,0xdc,0xf0,0x3e,0x6a,0xda,0xef,0xf7,0x9d,0x08,
+  0x1d,0xd4,0xd7,0x22,0x2f,0x50,0x67,0xba,0xe4,0xf5,0xd4,0x74,0xc0,0xf4,0xc5,0x02,
+  0x00,0x00,0xd0,0x86,0xb6,0x3d,0x43,0x63,0xcf,0x96,0x67,0xa1,0x27,0x7d,0x81,0xba,
+  0xcf,0xa8,0x27,0xa2,0xe9,0x65,0x59,0x0a,0x7a,0xcc,0xab,0xa9,0x7e,0x6b,0xfe,0xab,
+  0xea,0xb7,0xd0,0x65,0x7f,0x22,0x37,0x9d,0x3b,0xfe,0x91,0x9a,0x0f,0x33,0xc3,0xf6,
+  0xfb,0x66,0x84,0x03,0x16,0xde,0xf7,0xb4,0xd0,0xe4,0x2f,0xca,0x0b,0xd2,0x2e,0x3c,
+  0x8b,0x66,0xfe,0x42,0x77,0x77,0x00,0x00,0x00,0x40,0x18,0xa0,0x78,0x8c,0xa6,0x7c,
+  0x5d,0x6e,0x79,0x4c,0x0f,0x7c,0x85,0x37,0x19,0x8e,0x47,0xe4,0x6f,0xca,0xab,0xa0,
+  0x0f,0xf3,0xd0,0xcc,0xfd,0x0d,0xff,0x78,0x83,0xe0,0x85,0xfc,0x54,0x94,0xc2,0xf8,
+  0xbf,0xdb,0xfe,0x9e,0x8e,0xac,0x52,0xbc,0x98,0x72,0x22,0x1e,0xa5,0xba,0x4d,0x34,
+  0xe5,0x6b,0x4a,0x3f,0x91,0xeb,0xdf,0x8b,0xb6,0x1b,0x00,0x00,0x50,0xbe,0xd0,0xf1,
+  0x6d,0xbc,0x2d,0xb3,0xca,0x03,0x7f,0xdc,0x87,0x59,0x60,0x6b,0x75,0x9f,0x96,0xbf,
+  0x67,0x22,0x2e,0x6f,0xc4,0x71,0xdb,0xc7,0xad,0x44,0xfe,0xa9,0x55,0x6a,0x3f,0x2e,
+  0x2f,0x84,0xce,0x5c,0xcc,0xf2,0xfb,0x54,0x2e,0xa6,0x6c,0xe8,0x3c,0xc9,0xf3,0x06,
+  0xe3,0x65,0x73,0xa9,0x46,0x74,0xf1,0x6b,0x69,0xfd,0x63,0x55,0xb2,0x15,0x0e,0x00,
+  0x00,0x95,0x09,0x7b,0x88,0x6f,0x9c,0x21,0x0f,0x57,0x47,0x74,0xd9,0x9b,0xe9,0xc1,
+  0x6f,0xd0,0x9a,0x07,0xa9,0xa3,0xd1,0xfd,0xe1,0x4f,0xcb,0xee,0x93,0xbc,0xd5,0x98,
+  0xd7,0x08,0x77,0x72,0xe9,0xd0,0xcb,0xf2,0x8e,0x13,0xe9,0x8b,0xf9,0x13,0x9a,0xfa,
+  0x0d,0xda,0x32,0x8b,0xfa,0x3b,0x02,0xbb,0x3b,0x81,0xc3,0x0b,0xd1,0x99,0xf3,0xb2,
+  0x5b,0xfa,0xc0,0x57,0x78,0x27,0x2b,0x95,0x85,0x33,0x3d,0xf5,0x2b,0x2b,0x3a,0x68,
+  0xfa,0xda,0x01,0x00,0x00,0x14,0x47,0x6c,0x98,0x16,0x5c,0xa5,0xfa,0xe4,0xbf,0xe8,
+  0x2c,0x7e,0x70,0xf8,0xd6,0x8f,0xd1,0x73,0xd7,0x50,0xcd,0x3a,0x5e,0xc4,0x25,0x32,
+  0x62,0x3a,0x7d,0x40,0xbe,0xb3,0x2c,0xec,0x22,0x95,0x8c,0xd3,0x9a,0x87,0x68,0x8c,
+  0x74,0xf7,0x73,0xf4,0x62,0xae,0xfa,0x0b,0xba,0xeb,0x9f,0x68,0xc9,0xad,0xd4,0xb8,
+  0x8b,0xd8,0x6b,0xcb,0x24,0x24,0xe4,0xb6,0xcb,0x6e,0xdd,0x91,0x55,0xf4,0xec,0x55,
+  0xbc,0x17,0xb7,0xf4,0x2c,0xb6,0x5d,0x93,0xbf,0x48,0xbd,0xcd,0xa6,0x57,0x00,0x00,
+  0x00,0xc0,0x07,0xb8,0x1d,0xcc,0xfc,0x85,0x7c,0x7a,0x42,0xbe,0xce,0xa2,0xcb,0xff,
+  0x94,0x26,0xff,0x27,0x2d,0xbc,0x89,0x36,0x4c,0xa7,0x5d,0x0b,0xa8,0x76,0x7d,0x5a,
+  0x47,0x56,0xd3,0x0d,0xef,0x97,0xbc,0x7c,0xc2,0xa7,0x28,0x11,0x15,0x5f,0xcf,0xd2,
+  0x09,0x74,0xe9,0x9b,0xf4,0x2e,0x86,0x79,0xf1,0xd5,0xef,0xa4,0x07,0xbf,0xc6,0xbf,
+  0x18,0xac,0x9e,0x4a,0x3b,0x6d,0x17,0x13,0x1e,0xed,0x98,0x4f,0xeb,0x1f,0xa5,0xe7,
+  0xae,0xe5,0x1e,0xca,0x6e,0x9d,0xca,0x66,0x77,0xce,0x1a,0x5f,0x45,0x13,0x3f,0x4f,
+  0x83,0xaa,0xed,0xb3,0x00,0x00,0x00,0x84,0x1f,0xea,0xef,0xa0,0x59,0xbf,0xa2,0x8b,
+  0xd5,0x12,0xd1,0x4e,0x1a,0xfb,0xba,0xac,0xa4,0xbd,0x23,0x98,0xdd,0x37,0x89,0x0f,
+  0x17,0x53,0x2c,0xc2,0x3d,0xfd,0x8a,0x3f,0xf5,0xed,0x62,0x42,0xa2,0x62,0x96,0xc3,
+  0xcc,0xf7,0x81,0xaf,0x50,0xfb,0xf1,0x12,0x7f,0x30,0x00,0x00,0x00,0x04,0x4e,0x5f,
+  0x1b,0x0f,0xcd,0x2e,0xd3,0x0c,0x3c,0x8b,0xd1,0xf2,0x89,0x8e,0x17,0x13,0x1d,0xe0,
+  0x0d,0xa0,0xae,0x79,0x57,0xe9,0x2e,0x26,0xcc,0x1a,0xf3,0x6a,0x9a,0xf6,0x7d,0x6a,
+  0xa9,0x29,0xe1,0xa7,0x01,0x00,0x00,0x40,0x09,0x19,0xea,0xa1,0x75,0x8f,0xd2,0xf5,
+  0x7f,0x55,0x22,0x5b,0xb9,0xf7,0x5f,0xdd,0x76,0x6c,0x63,0xc3,0xbc,0x49,0x97,0x62,
+  0x45,0x74,0x05,0xeb,0x92,0xd7,0xd3,0xa2,0x71,0x56,0x47,0x43,0xe9,0x3e,0x06,0x00,
+  0x00,0x00,0x4a,0x4f,0x3c,0x4a,0x27,0xb6,0xf3,0x7d,0x46,0x69,0x01,0x95,0x0f,0xce,
+  0xf2,0x46,0x49,0x42,0x95,0x92,0xd4,0x71,0x82,0x66,0xff,0x86,0x2e,0x7d,0x83,0xf6,
+  0x6e,0x69,0x05,0x68,0xcc,0x6b,0xf8,0x61,0xe7,0x03,0x2f,0x59,0xd1,0xfc,0xa1,0xc9,
+  0x00,0x00,0x00,0x2a,0x12,0x3e,0x93,0x68,0xc3,0xe3,0x34,0xe1,0x93,0xf2,0x79,0x82,
+  0x45,0xea,0xe5,0x49,0xf2,0x8b,0x61,0x2e,0x7c,0x70,0x19,0xdd,0x77,0x0e,0x9f,0x4a,
+  0x6c,0xdc,0x13,0x4b,0xa3,0x8b,0x5f,0x4b,0xb7,0x7c,0x94,0x5e,0xba,0x9b,0x22,0x7d,
+  0x25,0xf8,0x71,0x03,0x00,0x00,0x08,0x15,0xd4,0x5e,0x4f,0x0b,0x6f,0xa4,0x3b,0x3f,
+  0x23,0x1f,0x8e,0xe0,0x59,0x93,0xfe,0xd3,0x4a,0x26,0x94,0x2e,0xa6,0xaf,0x8d,0x56,
+  0x3f,0x48,0xbf,0xff,0x12,0x1f,0x61,0x6f,0xdc,0x1f,0x83,0xd3,0xd8,0xd7,0xf2,0xc9,
+  0x8f,0xf3,0xaf,0xa0,0x93,0x7b,0xcb,0xe5,0x38,0x15,0x00,0x00,0x00,0xff,0x49,0xc6,
+  0xad,0xe3,0xdb,0x68,0xd5,0x03,0xf4,0xd0,0xb7,0xe8,0xb7,0x6f,0x95,0x57,0x35,0xeb,
+  0xea,0xd2,0x37,0x51,0xe7,0x29,0x8d,0xeb,0x69,0x3b,0x46,0x5b,0x9f,0xa6,0x27,0x2f,
+  0xe0,0x73,0x84,0xe5,0x4d,0x92,0xcb,0x4a,0x97,0xfd,0x09,0x9f,0x76,0xb1,0xec,0x5e,
+  0xeb,0xd8,0xa6,0x0a,0xec,0xae,0x09,0x00,0x00,0xc0,0x03,0x89,0x98,0xd5,0x71,0x82,
+  0x6a,0xd7,0xf1,0xf1,0xbe,0x53,0xbe,0xea,0x73,0x04,0xba,0x71,0x86,0xde,0xc5,0xb0,
+  0xa8,0xb0,0xaf,0xcd,0x6a,0xd8,0x4e,0x9b,0x9e,0xe0,0x55,0xc1,0xd7,0x95,0xaa,0x5a,
+  0x2c,0x20,0x5d,0xf1,0x16,0x7e,0x1c,0x78,0xc9,0x1d,0x74,0x78,0xa5,0xd5,0x7a,0x14,
+  0xce,0x0b,0x00,0x00,0x40,0x40,0x3c,0x6a,0x0d,0xf5,0x52,0xf7,0x69,0xaa,0x59,0x43,
+  0x2f,0xdc,0x42,0xd3,0xcf,0xa5,0x7b,0x3e,0x47,0x37,0x7e,0x80,0x4f,0x06,0xbc,0xfa,
+  0x1d,0x3c,0x40,0xf6,0xa0,0x27,0x7e,0xea,0xf1,0x62,0x58,0x6c,0x3e,0xdc,0x47,0xbd,
+  0xcd,0x54,0xbf,0x99,0x96,0xdf,0x4b,0x33,0x7e,0xc2,0xcb,0xc6,0x6e,0xfa,0x1b,0x7e,
+  0x31,0xd7,0xfe,0xa5,0xc7,0x8b,0x09,0x54,0xec,0x16,0xb1,0x6b,0xbb,0xe9,0x03,0x7c,
+  0x44,0x23,0xfb,0xe6,0xb0,0xf0,0x26,0xda,0xff,0x22,0xef,0x3f,0x39,0xd8,0x9d,0xb2,
+  0x5d,0x64,0x9b,0x01,0x00,0x00,0xa8,0xc2,0x7b,0x67,0x31,0x47,0x1e,0xec,0xa6,0xee,
+  0x26,0xea,0x68,0xf0,0xa2,0xae,0x26,0x3f,0xaf,0x27,0xd2,0xcf,0x2f,0xa6,0xa7,0xd9,
+  0xe3,0xc5,0x04,0x2a,0x76,0x8b,0xd8,0xb5,0x0d,0xa3,0xa4,0x0a,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xca,0x15,0x3a,
+  0xbc,0x92,0xa6,0x7c,0x3d,0x40,0x1d,0x78,0xc9,0xf4,0x12,0x01,0x00,0x00,0x80,0xd0,
+  0x41,0x6d,0xf5,0xda,0x13,0x15,0xb5,0xf4,0xe8,0x0f,0x2c,0x4a,0x9a,0x5e,0x25,0x00,
+  0x00,0x00,0x10,0x2e,0x28,0x11,0xa3,0xfb,0xfe,0x2d,0x40,0xff,0xbd,0xfa,0x1d,0x34,
+  0xd0,0x65,0x7a,0x95,0x00,0x00,0x00,0x40,0xe8,0xa0,0x65,0xf7,0x04,0xd9,0xc7,0xe3,
+  0x2c,0xda,0xbb,0xd8,0xf4,0x12,0x01,0x00,0x00,0x80,0xd0,0x41,0x2d,0x47,0x83,0xed,
+  0xa3,0x35,0xf3,0x17,0xa6,0x97,0x08,0x00,0x00,0x00,0x84,0x11,0xba,0xe7,0xb3,0x01,
+  0xfa,0xef,0x55,0x6f,0xa3,0xc1,0x4e,0xd3,0x4b,0x04,0x00,0x00,0x00,0x42,0x07,0x2d,
+  0x9f,0x18,0x6c,0x08,0xbc,0x67,0xa1,0xe9,0x25,0x02,0x00,0x00,0x00,0xa1,0x83,0x8f,
+  0x14,0xbc,0xe4,0xf5,0x01,0xfa,0xef,0xac,0x0b,0x30,0xb2,0x10,0x00,0x00,0x00,0xc8,
+  0x27,0x1e,0xa5,0x09,0x9f,0x0a,0xd0,0x7f,0xaf,0x7d,0x37,0x45,0x06,0x4c,0x2f,0x12,
+  0x00,0x00,0x00,0x08,0x1d,0xb4,0xf8,0x96,0x00,0xfd,0xf7,0xa2,0xb3,0xf8,0x10,0x43,
+  0x00,0x00,0x00,0x00,0xe4,0x42,0x4d,0xfb,0x69,0xec,0xd9,0x41,0xa6,0xa0,0x7f,0x8d,
+  0x39,0x86,0x00,0x00,0x00,0x40,0x1e,0x14,0x8f,0xd2,0x1d,0x9f,0x0c,0xd0,0x7f,0x6f,
+  0x78,0x3f,0x0d,0xf5,0x98,0x5e,0x25,0x00,0x00,0x00,0x10,0x3a,0x68,0xd1,0xb8,0x20,
+  0x53,0xd0,0xaf,0x46,0x0a,0x1a,0x00,0x00,0x00,0x28,0x84,0x8e,0x6f,0xe3,0x2e,0x19,
+  0x9c,0x05,0xcf,0xbd,0xd4,0xf4,0x12,0x01,0x00,0x00,0x80,0xd0,0x41,0x89,0x38,0x8d,
+  0xff,0x48,0x90,0x29,0xe8,0xf7,0x51,0x3c,0x6a,0x7a,0x95,0x00,0x00,0x00,0x40,0xe8,
+  0xa0,0x45,0x37,0x05,0x99,0x82,0x3e,0x8b,0x6a,0xd6,0x9a,0x5e,0x22,0x00,0x00,0x00,
+  0x10,0x3a,0xe8,0xf8,0x56,0x1a,0xfb,0x9a,0x20,0x53,0xd0,0x97,0x99,0x5e,0x22,0x00,
+  0x00,0x00,0x10,0x3e,0xa2,0x83,0xc1,0xa6,0xa0,0xc7,0x7d,0x88,0xa2,0xc3,0xa6,0x17,
+  0x09,0x00,0x00,0x00,0x84,0x0e,0x9a,0x77,0x45,0x80,0xfe,0x3b,0xe6,0xd5,0x54,0xbf,
+  0xd5,0xf4,0x12,0x01,0x00,0x00,0x80,0xd0,0x41,0xf5,0x9b,0xe9,0xa2,0x57,0x05,0x68,
+  0xc1,0xcf,0xfe,0xd6,0xf4,0x12,0x01,0x00,0x00,0x80,0xd0,0x41,0xf1,0x18,0xdd,0xf4,
+  0xc1,0x20,0x53,0xd0,0x7f,0x6b,0xc5,0x86,0x4c,0xaf,0x12,0x00,0x00,0x00,0x08,0x17,
+  0xc4,0x98,0x77,0x79,0x80,0xfe,0x3b,0xf6,0x6c,0xaa,0xdf,0x62,0x7a,0x95,0x00,0x00,
+  0x00,0x40,0xe8,0xa0,0xc3,0xab,0x82,0x4d,0x41,0x2f,0x1a,0x67,0x7a,0x89,0x00,0x00,
+  0x00,0x40,0xe8,0xa0,0x48,0x3f,0x5d,0xff,0xde,0x00,0xfd,0x77,0xfc,0x47,0x31,0x0e,
+  0x18,0x00,0x00,0x00,0x28,0x84,0xe6,0x07,0x59,0x05,0xcd,0x74,0x62,0x87,0xe9,0x25,
+  0x02,0x00,0x00,0x00,0xa1,0x83,0x8e,0x04,0x9d,0x82,0xbe,0xc9,0xf4,0x12,0x01,0x00,
+  0x00,0x80,0xd0,0x41,0x43,0xbd,0xc1,0xa6,0xa0,0xef,0xfc,0x34,0xc5,0x22,0xa6,0x57,
+  0x09,0x00,0x00,0x00,0x84,0x0c,0x22,0x9a,0xf5,0xab,0x00,0xfd,0xf7,0xe2,0xd7,0xd1,
+  0xc9,0xbd,0xa6,0x17,0x09,0x00,0x00,0x00,0x84,0x0e,0x3a,0xf0,0x22,0x5d,0x78,0x56,
+  0x80,0x16,0xfc,0xe2,0x04,0xd3,0x4b,0x04,0x00,0x00,0x00,0x42,0x07,0xc5,0x86,0xe8,
+  0xda,0x77,0x05,0xe8,0xbf,0xb7,0x7f,0xd2,0x4a,0xc4,0x4d,0xaf,0x12,0x00,0x00,0x00,
+  0x08,0x1d,0x34,0xeb,0x97,0x01,0xfa,0xef,0x98,0xb3,0xe9,0xf4,0x41,0xd3,0x4b,0x04,
+  0x00,0x00,0x00,0x42,0x07,0xed,0x5b,0x1c,0xa0,0xff,0x32,0x2d,0xbb,0xd7,0xf4,0x12,
+  0x01,0x00,0x00,0x80,0xd0,0x41,0x03,0x1d,0x74,0xd5,0xdb,0x03,0xf4,0xdf,0xfb,0xfe,
+  0x8d,0x92,0x48,0x41,0x03,0x00,0x00,0x00,0x79,0x10,0xcd,0xf8,0x59,0x80,0xfe,0x3b,
+  0xf6,0x6c,0x6a,0xa9,0x35,0xbd,0x46,0x00,0x00,0x00,0x20,0x74,0xd0,0x9e,0x45,0xc1,
+  0xa6,0xa0,0x97,0x4f,0x34,0xbd,0x44,0x00,0x00,0x00,0x20,0x74,0xd0,0x50,0x0f,0x5d,
+  0xf5,0xb6,0x40,0x53,0xd0,0x56,0x22,0x66,0x7a,0x95,0x00,0x00,0x00,0x40,0xd8,0x20,
+  0x7a,0xec,0x87,0x01,0xfa,0xef,0xa5,0x6f,0x44,0x0a,0x1a,0x00,0x00,0x00,0x28,0x84,
+  0xb6,0xcd,0x09,0x36,0x05,0xbd,0xe6,0x21,0xd3,0x4b,0x04,0x00,0x00,0x00,0x42,0x07,
+  0xf5,0xb6,0xd0,0xe5,0x6f,0x0e,0xd0,0x7f,0x1f,0xf8,0xf2,0xff,0x07,0x66,0x87,0xe4,
+  0x0f,0x36,0x10,0x0e,0x00,
diff --git a/u-boot/board/esd/voh405/voh405.c b/u-boot/board/esd/voh405/voh405.c
new file mode 100644
index 0000000..5f28a48
--- /dev/null
+++ b/u-boot/board/esd/voh405/voh405.c
@@ -0,0 +1,393 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13806_320_240_4bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFFB5);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	unsigned short *lcd_contrast =
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
+	unsigned short *lcd_backlight =
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	char *str;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_INIT pin
+	 */
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
+	udelay(1000); /* wait 1ms */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT);   /* reset high */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Setup EEPROM write protection
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8(duart0_mcr, 0x08);
+	out_8(duart1_mcr, 0x08);
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	str = getenv("bd_type");
+	if (strcmp(str, "voh405_bw") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+	} else if (strcmp(str, "voh405_bwbw") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+		lcd_setup(1, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_320_240_4bpp,
+			 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+	} else if (strcmp(str, "voh405_bwc") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_640_480_16bpp,
+			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+			 logo_bmp_640, sizeof(logo_bmp_640));
+	} else {
+		printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+		return 0;
+	}
+
+	/*
+	 * Set invert bit in small lcd controller
+	 */
+	out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
+	      in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
+
+	/*
+	 * Set default contrast voltage on epson vga controller
+	 */
+	out_be16(lcd_contrast, 0x4646);
+
+	/*
+	 * Enable backlight
+	 */
+	out_be16(lcd_backlight, 0xffff);
+
+	/*
+	 * Enable external I2C bus
+	 */
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOH405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s)", str);
+	} else {
+		puts(" (Missing bd_type!)");
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		out_be16((void *)FPGA_MODE,
+			 in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		out_be16((void *)FPGA_MODE,
+			 in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/u-boot/board/esd/vom405/Makefile b/u-boot/board/esd/vom405/Makefile
new file mode 100644
index 0000000..d4012b0
--- /dev/null
+++ b/u-boot/board/esd/vom405/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/vom405/flash.c b/u-boot/board/esd/vom405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/vom405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/vom405/vom405.c b/u-boot/board/esd/vom405/vom405.c
new file mode 100644
index 0000000..f665a3e
--- /dev/null
+++ b/u-boot/board/esd/vom405/vom405.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO12 (CS3) pin
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12));
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | (0x80000000 >> 12));
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Init magnetic coupler
+	 */
+	if (!getenv("noinitcoupler"))
+		init_coupler(CAN_BA);
+
+	return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+	int flashcnt;
+	int delay;
+	u8 *led_reg = (u8 *)(CAN_BA + 0x1000);
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOM405");
+	} else {
+		puts(str);
+	}
+
+	printf(" (PLD-Version=%02d)\n", in_8(led_reg));
+
+	/*
+	 * Flash LEDs
+	 */
+	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+		out_8(led_reg, 0x40);        /* LED_B..D off */
+		for (delay = 0; delay < 100; delay++)
+			udelay(1000);
+		out_8(led_reg, 0x47);        /* LED_B..D on */
+		for (delay = 0; delay < 50; delay++)
+			udelay(1000);
+	}
+	out_8(led_reg, 0x40);
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/u-boot/board/esd/wuh405/Makefile b/u-boot/board/esd/wuh405/Makefile
new file mode 100644
index 0000000..401622f
--- /dev/null
+++ b/u-boot/board/esd/wuh405/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esd/wuh405/flash.c b/u-boot/board/esd/wuh405/flash.c
new file mode 100644
index 0000000..895a836
--- /dev/null
+++ b/u-boot/board/esd/wuh405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/esd/wuh405/fpgadata.c b/u-boot/board/esd/wuh405/fpgadata.c
new file mode 100644
index 0000000..fdc02e3
--- /dev/null
+++ b/u-boot/board/esd/wuh405/fpgadata.c
@@ -0,0 +1,1818 @@
+  0x1f,0x8b,0x08,0x08,0xe2,0x44,0xc5,0x42,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x0d,0x74,0x14,0xd7,0x95,0x2e,0xba,
+  0xeb,0x54,0x49,0x94,0xba,0x5b,0xea,0x42,0x48,0x1e,0xd9,0x60,0x5c,0x6a,0x09,0xd2,
+  0x28,0x8d,0x68,0x24,0x47,0x60,0x21,0x4b,0x45,0x8b,0x78,0x14,0x20,0x41,0xe3,0x78,
+  0x12,0xee,0x7d,0x5e,0x99,0xb6,0x43,0x66,0x78,0x33,0xc4,0x97,0xc4,0xb9,0x77,0x88,
+  0x27,0xd7,0x3e,0x6a,0x09,0x23,0x2c,0x6c,0xda,0x36,0x89,0x71,0xe2,0xc9,0x34,0x98,
+  0x24,0xd8,0x61,0x32,0x0d,0xc2,0x46,0x80,0x63,0x97,0xb0,0xe2,0x34,0x58,0xc6,0x8a,
+  0xe3,0xc9,0x60,0xcc,0xe0,0x26,0x51,0x6c,0xd9,0x96,0xb1,0x8c,0x19,0x5b,0x20,0x40,
+  0xef,0xec,0x53,0x5d,0xd5,0x55,0xfd,0x23,0x27,0x77,0xd6,0xbc,0x35,0x6f,0xbd,0x61,
+  0xd6,0xba,0x77,0xa7,0xba,0x52,0xa9,0x73,0x74,0x6a,0xef,0xef,0x7c,0xfb,0xdb,0xfb,
+  0x40,0x91,0x77,0xcc,0xf8,0x3f,0x00,0xe1,0x36,0x28,0xfe,0xdb,0xff,0xb9,0xf6,0xfa,
+  0xe0,0x67,0xfe,0x62,0x61,0xed,0x1d,0x5f,0x5d,0x03,0xb7,0x83,0xbb,0xee,0xce,0xcf,
+  0x04,0xbf,0xf6,0xad,0x6f,0x2c,0xbc,0xfe,0x7a,0xf8,0x2a,0xfb,0x4f,0xc1,0xe0,0x67,
+  0x16,0x04,0x17,0x2d,0x08,0x2e,0x84,0x35,0x50,0xb4,0xf0,0x33,0x8d,0x75,0x8b,0x1b,
+  0x83,0xf5,0xf0,0x35,0x10,0xea,0x77,0x4d,0xb2,0x7f,0x4f,0x3e,0xfa,0xe7,0x7f,0x19,
+  0x04,0x2a,0x00,0xc0,0xb4,0xa0,0x10,0xc6,0xff,0xdf,0x1d,0x14,0x54,0x01,0x68,0xcb,
+  0xfc,0x20,0xe8,0xf8,0x9f,0x21,0xf5,0x7b,0x51,0x10,0x54,0xfb,0x7f,0x16,0x82,0xa0,
+  0x41,0x3b,0x68,0x5b,0x84,0x52,0xf8,0x43,0xfe,0x75,0xd1,0x94,0x21,0xfd,0x61,0xf7,
+  0x4b,0xe6,0xfd,0x93,0xc7,0x68,0xde,0x9b,0xd2,0xff,0x5a,0xce,0xc5,0x52,0x56,0x01,
+  0x09,0x7e,0xf2,0xed,0x82,0x46,0xcd,0xa7,0x5e,0x3c,0xf9,0x07,0x3d,0xff,0x7f,0x99,
+  0xcf,0xbf,0xf2,0x47,0xde,0x0f,0xca,0x1f,0x70,0x3b,0x1b,0xaf,0x69,0x5c,0x54,0x40,
+  0x06,0x02,0x40,0xc1,0x0f,0x2e,0x20,0x14,0x62,0xb9,0x8c,0x96,0x65,0xe6,0xfd,0xfa,
+  0xc6,0x2b,0x30,0xd1,0xd9,0x92,0x74,0x8f,0x88,0xdf,0xaa,0x98,0xa4,0x0d,0x27,0x8a,
+  0xc7,0xc4,0x3a,0x66,0xb4,0x0c,0x7b,0xc7,0xc5,0x31,0x78,0x83,0xd6,0x27,0xd1,0x10,
+  0xc2,0xe6,0xfd,0x15,0x3f,0x86,0xc3,0xb4,0x36,0xe9,0xde,0x4d,0xe6,0x42,0x4f,0x75,
+  0x65,0x7f,0xcf,0x37,0x9e,0xf7,0xe1,0x95,0x84,0xb7,0x8f,0xbc,0x09,0x3d,0xd4,0x97,
+  0x74,0xf7,0x91,0xa4,0x64,0xce,0x62,0x42,0xea,0x92,0x7b,0x21,0xa0,0xbb,0x63,0x85,
+  0xc3,0xd0,0x2b,0x07,0x06,0xdd,0x41,0x02,0x78,0x25,0xc1,0x8c,0x63,0xd2,0xc3,0x92,
+  0xaa,0x33,0xe3,0x88,0xa0,0x9a,0xcf,0x2f,0x18,0x86,0xc3,0x50,0xdb,0xcf,0x9e,0x1f,
+  0x9b,0xde,0x09,0x35,0xfd,0x2b,0xe2,0x35,0x7e,0x38,0x4c,0x6a,0x75,0x77,0x1c,0x9f,
+  0x0f,0x3e,0x34,0xc6,0xa4,0xf5,0xa9,0xfb,0x97,0x96,0x8f,0xc2,0x04,0x34,0xeb,0xde,
+  0x1a,0xf1,0x26,0x8a,0x46,0x71,0x7c,0x86,0x9f,0x5d,0x99,0xad,0x5f,0x17,0x17,0xcf,
+  0xc2,0xeb,0x50,0xa7,0x7b,0xe3,0xe2,0xd0,0x32,0xf3,0xfe,0xb8,0xb0,0x1f,0x26,0xa1,
+  0x45,0xf7,0x26,0x3b,0xbe,0xc6,0x8c,0x45,0xfa,0xaa,0x31,0x71,0xbf,0x3a,0x49,0x5a,
+  0xf4,0x92,0xb1,0x69,0x83,0xec,0xca,0x73,0xba,0x77,0x4c,0x1c,0x01,0x73,0xbc,0x43,
+  0xca,0x2e,0xe3,0xf9,0x31,0x71,0x97,0x3e,0x01,0x8d,0x7a,0x71,0x50,0x9c,0x27,0x4d,
+  0x48,0xcd,0xfd,0x5e,0x7c,0xfe,0xbb,0xa4,0x19,0x9f,0x3f,0x26,0x99,0xef,0x9f,0x28,
+  0xa8,0xc6,0xf7,0xd7,0xdd,0xbb,0xe9,0xa7,0xd8,0xdb,0x56,0xe9,0xf2,0x18,0x99,0x4f,
+  0x71,0x44,0x33,0xe3,0x64,0x14,0x3a,0x81,0x0f,0xe4,0x1c,0x5b,0xfd,0xa9,0xf1,0x4a,
+  0x2b,0x81,0xcf,0x8f,0x9f,0xfc,0x52,0x7a,0x5c,0xf0,0xb3,0xd9,0x28,0xfc,0x53,0xe3,
+  0x4a,0x90,0xe8,0xf0,0xb8,0x61,0x8c,0xb3,0x6f,0xc5,0xf8,0x37,0xa6,0x7c,0x49,0x3b,
+  0x10,0x9b,0x9f,0x74,0x7f,0xdb,0x75,0x15,0x6c,0xa2,0x95,0x23,0xae,0x6f,0xcf,0x7e,
+  0x05,0x0e,0xc4,0xbe,0x3e,0xe2,0xde,0x40,0xde,0x60,0x57,0xd8,0x4f,0x1b,0xc8,0x09,
+  0xeb,0xf9,0x6d,0xf2,0x32,0xf8,0x30,0xde,0xa4,0x7b,0x55,0xb1,0x8b,0x0d,0x64,0x71,
+  0xd2,0x1b,0x14,0xff,0xf4,0xc4,0x87,0xd1,0xa6,0x11,0x77,0x50,0x1c,0x84,0xdf,0x01,
+  0xfb,0x29,0x28,0xbe,0x42,0xcc,0xf5,0xa0,0x15,0xec,0x57,0x26,0xcb,0xd8,0xfc,0x28,
+  0xe2,0x7e,0x78,0x1f,0x1a,0x87,0x8a,0xe3,0xa2,0xdf,0x98,0xb1,0xb1,0xaa,0xd4,0x54,
+  0x8f,0x89,0x43,0xc4,0x9c,0x1f,0x59,0xda,0x03,0x2f,0xe2,0x45,0x75,0xda,0xb7,0x60,
+  0x82,0x36,0xbe,0xea,0x79,0xfa,0xc5,0xf9,0x2a,0xbb,0x2d,0xe9,0x89,0xb3,0x69,0xe4,
+  0xf7,0xc7,0xc5,0x63,0x60,0xcd,0x4f,0xc5,0x36,0xf8,0x17,0x98,0xaf,0xbb,0xc3,0x64,
+  0x16,0x3c,0x07,0x6a,0xa2,0xf8,0x9b,0xe2,0x2d,0xf4,0x80,0x34,0x5f,0x97,0xd7,0x93,
+  0x53,0x70,0x00,0x7f,0x5a,0x4f,0xce,0x59,0xf3,0xa9,0xc2,0xd3,0x7c,0x50,0x3d,0x23,
+  0x91,0xef,0x49,0x07,0x22,0xf3,0x46,0xe4,0x1b,0xc8,0x57,0xb4,0x03,0xec,0x4a,0xd1,
+  0x06,0x72,0x1a,0x0e,0x18,0xe3,0xd5,0xad,0xe7,0x8f,0x48,0x5d,0xf0,0x30,0x9f,0xcf,
+  0x23,0xf7,0xb2,0x69,0x54,0xf5,0xa2,0x60,0xe8,0x0b,0x6a,0xaf,0x18,0xd0,0xe5,0x20,
+  0x39,0x4e,0x53,0x13,0xfb,0x8a,0xf5,0xfc,0x64,0xf9,0x08,0x1c,0x83,0x66,0xea,0x1d,
+  0x15,0x0f,0xeb,0x17,0xa1,0x91,0x7a,0x62,0x55,0x7f,0x43,0x2f,0xb2,0x2b,0x81,0x98,
+  0x38,0xce,0x0d,0xf6,0xa7,0x1f,0x97,0xcc,0xf1,0xb6,0x09,0x31,0x18,0x87,0x66,0xf0,
+  0x52,0xb7,0xca,0x8d,0x05,0xb4,0x2a,0x09,0xe3,0x04,0xaf,0x88,0x67,0x52,0x3f,0x89,
+  0xaf,0x80,0xb9,0xfe,0x65,0xb6,0x7e,0x8e,0x42,0xb3,0xe6,0xfd,0xbe,0xb8,0x0b,0x5e,
+  0x83,0x26,0xcd,0x13,0x15,0xab,0xe1,0xa0,0xc0,0xae,0x44,0xc5,0xbf,0xa4,0x17,0x80,
+  0x1b,0x47,0xac,0xef,0x85,0x4a,0xcb,0xc8,0x66,0xa8,0xd5,0xdc,0x65,0x44,0x62,0xf7,
+  0xd7,0x6a,0xc5,0x51,0x12,0xf0,0x1c,0xc4,0x2b,0xd1,0xd2,0xdf,0x53,0xc3,0x20,0x49,
+  0xcb,0x2d,0x2c,0x16,0xaa,0xa5,0xcd,0x42,0xad,0xb6,0x22,0x5a,0xba,0x4b,0x79,0x94,
+  0xfd,0xea,0x57,0x08,0x7b,0xbe,0x71,0xdb,0xb0,0x69,0xbc,0x60,0xad,0x07,0x7f,0x59,
+  0x35,0x74,0xc0,0x3a,0x76,0xf1,0xa6,0xea,0xd8,0x83,0x10,0x58,0x5e,0x54,0x7a,0x4c,
+  0x82,0xbd,0x10,0xd0,0xdc,0x0a,0x19,0x88,0xa5,0x8c,0x23,0x82,0xb9,0x1e,0x36,0x14,
+  0x87,0xa1,0x1b,0x07,0x15,0x13,0x63,0xf4,0x04,0x34,0xcb,0x9e,0xc8,0x0c,0x1c,0x78,
+  0x13,0x0e,0x33,0x4c,0x53,0xe3,0x3d,0x2d,0x9a,0xeb,0x73,0x7b,0xc1,0xab,0xc0,0x07,
+  0x35,0x24,0x9e,0x87,0x0b,0xfe,0xe6,0xe5,0x25,0x0f,0x75,0x0e,0xe3,0x95,0xe5,0x6c,
+  0x98,0xe7,0x21,0x35,0xde,0x37,0x89,0xf9,0x3d,0x56,0x94,0x0f,0x1b,0x17,0xdb,0xc5,
+  0x6a,0x7a,0x14,0xee,0x0a,0x05,0xb6,0x89,0xec,0x8a,0xd4,0x8c,0x13,0x75,0x5e,0xbd,
+  0x6c,0xdc,0xff,0x02,0x98,0xf7,0x2f,0x56,0x92,0xd0,0x07,0xb5,0xcc,0xd1,0xb8,0x6f,
+  0x63,0x2f,0xe6,0x03,0x79,0x13,0xe1,0x57,0x64,0x17,0x35,0x0c,0x70,0x53,0x72,0xdc,
+  0x9a,0xff,0x36,0xe8,0x82,0xbd,0x42,0x40,0x9b,0xa9,0x7c,0x69,0x0e,0xec,0x90,0xfd,
+  0x21,0xb9,0x94,0x0c,0xe0,0x78,0x43,0xb2,0x82,0x86,0x10,0x58,0xca,0xc6,0xfb,0x8a,
+  0x60,0x3e,0x7f,0x7b,0xd9,0x2e,0x36,0x69,0x25,0x6c,0x7e,0x0a,0xbf,0x46,0x3a,0x40,
+  0xd5,0xe4,0x68,0x68,0x98,0x4d,0x7b,0x40,0x73,0x45,0x99,0xff,0x31,0xe6,0x33,0xf4,
+  0xa6,0xb5,0x1e,0x62,0x05,0x7f,0x69,0xbc,0xbf,0x22,0x4e,0xd3,0xde,0x96,0x6a,0xf0,
+  0xb5,0xd9,0xfb,0x0b,0xcd,0x4b,0x67,0xb1,0x61,0xaa,0x38,0x10,0xf6,0xfe,0x23,0x96,
+  0xbf,0x4a,0x4c,0xdf,0x65,0xfc,0xd1,0x1f,0xab,0x3a,0x2b,0xa7,0x66,0x63,0x18,0x32,
+  0x8d,0x8b,0x96,0xff,0x91,0x15,0x73,0xbd,0x89,0x61,0x7d,0x04,0x6a,0x05,0x0f,0x15,
+  0x55,0x3e,0xed,0x1e,0x63,0xbd,0x35,0xe2,0x4f,0xc7,0xac,0xf5,0xec,0x2f,0xf0,0xc3,
+  0x21,0x61,0x2e,0x75,0x0f,0xbb,0xe6,0x49,0x87,0xa0,0x96,0xca,0xb1,0xba,0x79,0xd4,
+  0x30,0x98,0x1b,0x39,0x04,0x3e,0xea,0x8e,0x91,0x63,0xe9,0xf5,0x60,0xfa,0x9f,0xea,
+  0xc8,0x4a,0x19,0xbd,0x4d,0x5b,0x90,0x94,0xf0,0x2b,0xf8,0xbd,0x30,0x03,0x3d,0x12,
+  0xbb,0xdf,0x5c,0x6f,0x54,0xb9,0x95,0x7d,0xa4,0x73,0xd8,0xf7,0xeb,0xba,0x05,0x0e,
+  0xa8,0x81,0x81,0x8a,0x6f,0xbb,0xca,0xf0,0xb3,0x4d,0xb0,0xef,0xf7,0x5f,0xe1,0x39,
+  0x5a,0x89,0xdf,0xef,0x88,0x75,0x7f,0x77,0xf7,0x57,0x94,0x8f,0xe9,0x8d,0x49,0xef,
+  0x06,0xf1,0x2b,0xf0,0x57,0x4f,0xdc,0xf8,0xbb,0x59,0x17,0xc5,0xd9,0xf0,0x71,0x47,
+  0xcb,0xc5,0xc0,0x06,0xf1,0x34,0x4c,0xd2,0x1b,0xf0,0xa7,0x77,0xe6,0x9a,0xf7,0xcb,
+  0x05,0x7b,0xb8,0xf7,0x66,0x83,0xda,0x15,0x9b,0x50,0x9b,0x13,0xde,0xfd,0xc2,0x30,
+  0xba,0x91,0xa3,0xcc,0x8d,0x24,0x4d,0x7f,0x72,0xe4,0x5e,0x73,0x7e,0x40,0x7a,0x96,
+  0xb9,0x1d,0x16,0xbf,0xd6,0x8a,0x77,0x2c,0x7b,0xa3,0x7b,0xd1,0xb0,0xe7,0xb2,0xd8,
+  0x22,0xbc,0x1b,0xad,0x39,0xe3,0x19,0x17,0x9f,0xd6,0x58,0x20,0xc3,0xf8,0xa5,0xc7,
+  0xcc,0xf9,0xdf,0x5d,0xf1,0x18,0x7a,0x0f,0xdd,0xbd,0x8e,0x94,0xc2,0x5b,0xb0,0xe0,
+  0x8c,0xff,0x2e,0x42,0x76,0xfd,0x3a,0x56,0x9b,0x2c,0x5e,0x4f,0x4e,0x2b,0xdc,0x9f,
+  0xac,0x27,0xef,0x58,0x7f,0x5f,0xa0,0x8f,0xb1,0xd1,0x7d,0x5d,0x77,0xaf,0x89,0xdc,
+  0x1a,0xdb,0x04,0xf3,0x07,0x8a,0xea,0x6e,0x6e,0xea,0x3e,0xe0,0xe3,0xfe,0xea,0x9f,
+  0x29,0xfe,0x34,0x73,0xbd,0xcd,0xff,0xa8,0xd2,0x03,0xc6,0x7c,0x02,0x21,0xf2,0xe3,
+  0x85,0x01,0xbd,0x28,0x7e,0x4d,0x2b,0xf7,0x48,0x45,0x41,0x9f,0x6e,0x3a,0xf6,0x84,
+  0xf5,0xbd,0xef,0x2e,0x3f,0xab,0xf2,0x41,0x05,0xc4,0xe5,0xf0,0x32,0x8b,0x47,0x47,
+  0xc7,0x5a,0xfd,0x45,0x13,0xe4,0xef,0x74,0xe6,0x3f,0x7f,0x4a,0x53,0xe3,0x7d,0xc7,
+  0x5a,0x3f,0x54,0xd8,0x93,0x8a,0x47,0xad,0x23,0xd5,0x68,0xd4,0xc6,0xc5,0xdd,0x1d,
+  0xef,0xe2,0x8c,0xc5,0xc5,0x51,0x01,0xaf,0xfc,0x29,0x4e,0x94,0xf9,0xfe,0x95,0xca,
+  0x33,0xa9,0x78,0x27,0x6e,0x90,0x5e,0x26,0x4b,0x58,0x98,0x9b,0xd1,0xd8,0x75,0x0f,
+  0x59,0xa4,0x17,0x8f,0xb1,0xf5,0x80,0x81,0x8f,0xf9,0x73,0x7d,0x99,0xf9,0xfe,0x3b,
+  0xa4,0x75,0xa9,0xf8,0x45,0xe6,0xd1,0x1e,0x1e,0x76,0x5b,0xd7,0x4a,0x87,0x85,0x5a,
+  0x7d,0x45,0x9c,0xbc,0x4b,0x0f,0x1b,0xf1,0x2b,0xa9,0x59,0xeb,0xa1,0x20,0x20,0xe3,
+  0x45,0xd7,0x6e,0xb2,0x66,0xd9,0x0f,0xa0,0x04,0x7f,0x9d,0x23,0xa4,0x6e,0x7b,0x07,
+  0xcc,0xfb,0xad,0xf5,0x26,0x97,0x79,0xa0,0x57,0x65,0x93,0xa0,0x46,0x54,0xb5,0x53,
+  0x08,0x0c,0xad,0x08,0x7e,0x69,0xa9,0x6a,0xe0,0x01,0x18,0x84,0x5e,0x29,0x60,0xe0,
+  0x01,0x73,0xfa,0xa1,0x78,0x1d,0x4c,0x28,0xb5,0x7a,0x49,0x4c,0x5c,0x03,0xec,0xfd,
+  0x4f,0xcc,0x3e,0x37,0xa3,0x5a,0x99,0xf0,0x2d,0x1a,0xbc,0x3f,0x3e,0x6d,0x64,0x0b,
+  0xae,0x90,0xad,0x71,0x51,0xb7,0xfc,0x4f,0xec,0x17,0x97,0x60,0x52,0xbb,0x0e,0xe3,
+  0xf5,0x10,0x1b,0x78,0xf3,0x09,0xef,0xfe,0x56,0x1d,0x26,0xd7,0xb6,0x0c,0x62,0x58,
+  0xd7,0x26,0x94,0xe6,0x01,0x34,0x0a,0xcd,0xf9,0xd4,0xcb,0xaf,0x00,0x5f,0x24,0x71,
+  0xb1,0x59,0x7a,0xb9,0xa3,0x59,0xf4,0xee,0x23,0x01,0x78,0xff,0x86,0x4f,0x9d,0x2c,
+  0x4e,0x88,0xef,0xb4,0xbd,0xae,0xd5,0x25,0x03,0x08,0x84,0xac,0xf9,0x57,0xce,0xca,
+  0x1c,0xff,0x44,0x4b,0xd7,0x31,0x27,0x54,0x1b,0x77,0x7f,0x44,0xaa,0x63,0x5b,0x97,
+  0x7d,0x7a,0x48,0xde,0xcd,0x96,0xfd,0x56,0xcd,0x17,0x92,0x71,0xbc,0x96,0xff,0x2f,
+  0x18,0x94,0x53,0x1f,0xd1,0x4a,0x5c,0x06,0xe0,0x5e,0xb8,0x73,0xa5,0xf4,0x38,0x51,
+  0x13,0x45,0x40,0xf4,0xee,0x47,0xc3,0xbe,0x84,0x8c,0xe3,0xb5,0xde,0xa7,0x60,0x8f,
+  0x31,0x7b,0x51,0xb2,0x0e,0x7e,0x00,0xb5,0xc9,0xd6,0xb8,0xab,0x9a,0xc1,0x86,0x1a,
+  0x5d,0xde,0x49,0x75,0xc4,0x3f,0x9a,0x8c,0xf8,0xc7,0x5a,0x9f,0x5d,0xe6,0x7a,0x70,
+  0x07,0xc8,0xeb,0xd0,0xbc,0x77,0x55,0xbc,0x2a,0xcc,0x60,0x49,0x9d,0xfe,0xf9,0xa8,
+  0xf8,0x36,0xfc,0x1a,0xe2,0xb8,0x90,0x74,0xcb,0x3f,0x9c,0x81,0xd4,0x7a,0x88,0x89,
+  0x4d,0x2c,0xbe,0xb7,0xd0,0x7f,0x08,0x8a,0xe3,0xf0,0x77,0xd0,0xd8,0xef,0x4d,0x3e,
+  0x3f,0x8e,0x3f,0xb5,0x7b,0xc7,0x3a,0xc7,0xcd,0x3f,0x17,0xe8,0xb0,0x07,0xde,0x35,
+  0xf0,0xcf,0x3a,0x0c,0xf4,0x23,0x0c,0x06,0xc4,0xe0,0xfd,0x82,0x6b,0xf4,0xe2,0x6d,
+  0x33,0xde,0x91,0x8e,0x76,0x1f,0xc2,0xe7,0xdb,0xf0,0x8f,0x14,0x30,0xfe,0xe8,0x31,
+  0x36,0xd6,0x1e,0xa8,0x1d,0x73,0x8f,0x11,0x3f,0x6c,0x85,0x4f,0xf7,0xbb,0x62,0x64,
+  0x84,0xa4,0xde,0xff,0x9c,0xf5,0xe7,0x4d,0x96,0xaf,0x34,0x40,0x4e,0xbc,0x70,0x1d,
+  0x1b,0x66,0x20,0xca,0x26,0x6a,0x37,0x41,0xe0,0x57,0x24,0x91,0x04,0xbb,0xb2,0x1b,
+  0x1d,0x51,0x1a,0xff,0x84,0x85,0xd9,0x46,0xd0,0x5f,0x5d,0xf7,0x15,0x0e,0x0c,0x66,
+  0xfe,0x1d,0x21,0xdd,0x9b,0xa2,0x0c,0x08,0xad,0x8e,0x5c,0x3c,0xb2,0x29,0x56,0x19,
+  0x96,0x9d,0xf8,0xc7,0xa3,0xfd,0x0e,0xf1,0x4f,0x93,0x78,0x07,0x79,0x1e,0x9a,0x76,
+  0x6f,0xbd,0x41,0xec,0xa1,0xbf,0x8b,0x2d,0x3e,0x53,0x0c,0xe2,0x11,0x7a,0x34,0xd6,
+  0x98,0x0c,0x30,0xfc,0x63,0xbd,0x8f,0x76,0x6d,0x6a,0x7e,0x7e,0x25,0x72,0x63,0x60,
+  0xda,0x98,0x98,0xd4,0x26,0xb4,0xe6,0x23,0x2c,0xa2,0x0d,0x69,0x93,0xed,0xd7,0x69,
+  0xde,0x0f,0xc4,0xa1,0x42,0x73,0xfe,0x77,0x17,0x8c,0x9a,0x4e,0x69,0x1d,0x37,0x3c,
+  0x1f,0xe2,0x42,0x55,0x0b,0x13,0x9e,0x5e,0xc4,0x9f,0x5a,0x1d,0xce,0xcf,0x3b,0x90,
+  0xf6,0xff,0x8f,0xa5,0x40,0x4e,0xe9,0x29,0xe6,0x7f,0x98,0x1b,0xb9,0x13,0x66,0x41,
+  0x67,0xb8,0x72,0x70,0xf9,0x9d,0x0c,0xff,0xfc,0x13,0x7c,0x1a,0x1d,0xcb,0x39,0xeb,
+  0xef,0xab,0xc3,0x0f,0x4d,0x90,0x83,0x68,0x27,0x30,0xc6,0x60,0xcf,0x4d,0xbe,0x4d,
+  0x3b,0x7f,0x3f,0xd2,0xb6,0x21,0x34,0x09,0xdf,0xa5,0x95,0x49,0x36,0xde,0x31,0xcb,
+  0xff,0xb4,0x95,0x0d,0x1a,0x4e,0xa6,0x8f,0x0c,0xc2,0xe3,0x02,0xbb,0x3f,0x4e,0x8a,
+  0x69,0x8f,0xb4,0x46,0x77,0x2d,0x26,0x2f,0xb1,0xa9,0xae,0x4d,0xfa,0x11,0xff,0x98,
+  0xeb,0x73,0xa4,0x7c,0x37,0x70,0x90,0x73,0x56,0x5c,0x2b,0x5d,0x14,0xee,0xe9,0xba,
+  0x36,0x26,0x7e,0x9b,0x21,0xa2,0x06,0xea,0xd9,0x25,0x5e,0x5c,0x7a,0x12,0xf6,0xed,
+  0xf6,0xc4,0xc4,0x8b,0x69,0xfc,0x03,0xc9,0x54,0x3c,0xea,0x4c,0xc2,0x08,0xdc,0x0d,
+  0x25,0x74,0x06,0x5e,0x59,0x0c,0xde,0x0e,0x76,0x65,0x4c,0x6b,0x84,0xeb,0xec,0xf8,
+  0xa7,0x5b,0x31,0x83,0xda,0xb4,0x6a,0x66,0x34,0xad,0x9d,0x16,0x6d,0x45,0x20,0xd4,
+  0xa8,0x79,0xbe,0xcf,0x80,0xd0,0xdb,0xcc,0x58,0xb9,0xcd,0x81,0x7f,0xd6,0x98,0xa0,
+  0xa5,0x5a,0x61,0x46,0xfb,0x7d,0x68,0x6c,0x86,0x06,0x4d,0x5e,0x7c,0x4d,0xb5,0x70,
+  0x10,0xd7,0xcf,0x76,0x1b,0xfe,0xa9,0x90,0xaa,0xe1,0x09,0x7e,0xbf,0xc4,0x61,0xcf,
+  0x90,0x1c,0x25,0x5d,0xd2,0xa3,0xc2,0xed,0x2c,0x70,0x97,0x06,0xd8,0x95,0x1a,0x66,
+  0x30,0xfc,0x63,0xfe,0x93,0x21,0x85,0x76,0x4a,0x23,0xdc,0x58,0xee,0x2a,0x8d,0x74,
+  0xc5,0x3a,0xe6,0x55,0x2f,0xf7,0x47,0x49,0x21,0xec,0x0d,0xb0,0x88,0x6f,0xc7,0x3f,
+  0x7d,0x72,0x98,0x0d,0x93,0x8d,0x37,0xe2,0xe2,0x78,0x4f,0x2e,0x26,0x33,0x18,0x10,
+  0x9a,0x1b,0x94,0x65,0x3a,0x43,0x95,0xde,0x51,0x0f,0x41,0x80,0x8a,0xc7,0x89,0x85,
+  0x7f,0xae,0x4d,0x8d,0xf7,0x95,0x5f,0x0f,0xc7,0x2e,0x90,0x16,0x6d,0xeb,0x43,0x1d,
+  0xdf,0x8a,0x5d,0xf0,0xd7,0x2e,0x9f,0x16,0x15,0x5f,0x8d,0x5d,0xf6,0xb7,0x2c,0xf7,
+  0x3e,0xd4,0xf9,0xe6,0x34,0x0b,0x6f,0x70,0xfc,0xd3,0xa2,0x79,0x1f,0x16,0x7f,0xcf,
+  0xa6,0xa5,0xa5,0xad,0xf8,0x41,0x71,0x58,0x3b,0xaa,0x34,0x2f,0x2f,0x66,0xf8,0x87,
+  0xdc,0x0f,0x75,0xcb,0x3c,0x43,0xe2,0x4d,0x69,0xfc,0x53,0x91,0x94,0x0d,0x90,0x13,
+  0x4a,0x52,0x66,0x6c,0x2b,0xde,0xc8,0xbc,0x71,0xf7,0x2d,0x75,0x50,0xc4,0xf0,0x8f,
+  0x9a,0x90,0x19,0x22,0x8a,0x1c,0x29,0x91,0xd2,0xfe,0x87,0x81,0x1c,0xc2,0xc6,0x3b,
+  0x83,0x0c,0xd0,0xbd,0x6c,0x36,0x8a,0x4a,0x43,0x03,0xd0,0x51,0xe5,0x0f,0x7d,0x4e,
+  0x29,0x1d,0xee,0xe8,0x50,0xd8,0x78,0x4b,0x49,0xc8,0xf2,0x3f,0x15,0x05,0xbb,0x84,
+  0x34,0x7a,0x94,0x6a,0xb5,0xa2,0x28,0xb0,0xfb,0x19,0x10,0x62,0x0b,0x69,0x18,0x36,
+  0x57,0xef,0xc4,0xf9,0x29,0x4c,0xe3,0x1f,0x69,0x97,0x85,0x5e,0x14,0x86,0x76,0x96,
+  0xfe,0x7d,0x74,0xfa,0x30,0x39,0x0a,0x8d,0x4b,0xd9,0xfb,0x0f,0x08,0x1d,0xb0,0x4f,
+  0x0b,0x44,0xc5,0xb5,0x5d,0xe6,0xf3,0x9f,0x54,0x76,0x39,0xd1,0xce,0xec,0x68,0x2b,
+  0x1a,0x8d,0x5a,0x49,0xb4,0xf3,0xcd,0x65,0x17,0x28,0x5f,0x2a,0xef,0x44,0xcd,0xe7,
+  0xfb,0x19,0xfe,0x19,0x49,0xe1,0x1f,0x92,0x98,0xd6,0xac,0x14,0x30,0xfc,0x23,0x27,
+  0xa0,0x41,0x08,0x51,0x31,0x29,0x21,0xa2,0x61,0x40,0xe8,0x58,0x97,0xb9,0xfe,0x55,
+  0xc9,0x0f,0xef,0x48,0xb5,0x08,0x72,0xfc,0xca,0x7d,0x30,0x3f,0xca,0xdc,0x8e,0x1f,
+  0xee,0x63,0xb0,0x07,0xf1,0x8f,0xf0,0x80,0xd6,0x40,0xe5,0x51,0xe6,0x58,0x4c,0xff,
+  0xe0,0xdf,0x98,0xf2,0x3f,0xc1,0xc2,0x95,0xe8,0x7f,0x7e,0x23,0x07,0x4b,0x3d,0xcc,
+  0xa8,0xd6,0x5d,0xc1,0x52,0xf6,0x05,0xc9,0xcc,0xf1,0x2e,0x61,0xf8,0xc7,0xfc,0xfb,
+  0x56,0x0a,0xb3,0xe0,0x27,0xf8,0xfd,0xde,0x45,0x66,0x03,0xc3,0x03,0x7a,0xc5,0x37,
+  0xd8,0x46,0x66,0x93,0x7a,0x5b,0x42,0x6e,0x67,0xdf,0xef,0x4f,0x60,0x4e,0x42,0x66,
+  0x2f,0xaa,0x59,0xcf,0x97,0x67,0xc3,0x5b,0x88,0x7f,0x16,0x8b,0xf7,0xc0,0x2f,0x99,
+  0x51,0x5c,0xf7,0x50,0x73,0xe8,0x65,0xfd,0xfa,0xe1,0xc2,0x0d,0x9d,0x2c,0xf4,0x74,
+  0x2c,0x19,0x0b,0xac,0x16,0x8e,0x59,0xfb,0x2f,0xf9,0xea,0x3d,0xa6,0x3f,0x41,0xc7,
+  0x72,0xbd,0xbe,0x60,0xbf,0x38,0x4a,0x27,0xd6,0xde,0xc3,0x02,0x19,0xbb,0xc2,0x3c,
+  0x70,0x92,0x4d,0xc5,0x11,0x6b,0xff,0xa5,0x15,0xb0,0xfd,0x7b,0xf4,0xc6,0xa4,0x67,
+  0xbc,0x33,0x15,0xc8,0xc6,0xc5,0x66,0x75,0x32,0xde,0xf2,0x5b,0xcf,0x78,0xeb,0x15,
+  0xf8,0x0b,0xba,0x28,0xe9,0x49,0xb0,0x50,0x68,0xe1,0x1f,0xe6,0x7f,0x7a,0x63,0x1c,
+  0xbd,0x0c,0x0a,0x6f,0xc1,0x8d,0xc7,0x7a,0xc6,0x84,0x1f,0xb2,0x2b,0x8d,0xa3,0xc5,
+  0x4b,0x23,0xa7,0x60,0x93,0xc0,0xfc,0x4f,0x3b,0x0b,0xdc,0xe6,0xf3,0xb7,0x33,0xef,
+  0x84,0xfe,0xaa,0x68,0x7d,0x84,0xef,0xce,0xfa,0x19,0x3a,0x9a,0x55,0x79,0x40,0x98,
+  0xaf,0x0b,0x6c,0xbf,0xa6,0x3d,0x52,0xf1,0xa3,0x23,0x6c,0xbc,0x49,0xcb,0xff,0x87,
+  0x15,0xc3,0xff,0x14,0x61,0x34,0xaf,0x82,0x80,0xca,0xfc,0xf9,0xf1,0xb2,0xde,0x02,
+  0xbf,0x5e,0x14,0x60,0xfb,0xdf,0x1e,0xa8,0x49,0x32,0xff,0x7f,0xc2,0x5a,0x9f,0x35,
+  0xe5,0xc6,0x78,0xe7,0x8f,0xcd,0xb8,0xc4,0x8c,0xbb,0xc3,0x2c,0x3a,0x37,0x31,0x58,
+  0xb2,0x40,0xff,0xfc,0x13,0x33,0x46,0xe1,0x24,0x39,0x90,0xdc,0xc3,0xf6,0x8f,0xd6,
+  0x7a,0x8b,0xc2,0x28,0x8b,0x56,0xcd,0x7a,0x49,0x5c,0x18,0x85,0x77,0x85,0xbb,0xfe,
+  0x1b,0xdb,0xbd,0xee,0xa9,0x98,0x40,0x8f,0x8d,0x1b,0x87,0x11,0x23,0x54,0xa5,0xfd,
+  0x43,0x47,0xf4,0x52,0x6a,0xf7,0x2a,0x72,0x63,0xe9,0xd6,0xb1,0x69,0x4d,0xd2,0x24,
+  0xdc,0xa3,0x7b,0x8f,0x88,0xe3,0x91,0x63,0x50,0xaf,0xb3,0xef,0x8b,0x2e,0x33,0xdf,
+  0xa7,0x1f,0x10,0xff,0x34,0xeb,0x3d,0x71,0x71,0x0f,0x06,0xb2,0xf5,0x0c,0xbd,0x18,
+  0x11,0xad,0x68,0x5b,0xe9,0xef,0xe8,0x89,0x64,0x83,0x2e,0x53,0x12,0x4c,0xe3,0x1f,
+  0x33,0xde,0xc5,0x09,0xbf,0xff,0xf6,0x1f,0xc4,0x43,0x01,0x58,0xc2,0xe2,0x35,0x8b,
+  0x80,0xa3,0x70,0x1f,0xf5,0xe1,0xfd,0xb1,0x34,0xfe,0x91,0x18,0xfe,0x09,0x73,0x90,
+  0xb3,0x85,0x4d,0x94,0x47,0x73,0x2f,0xf4,0x6d,0x51,0x7b,0x83,0xeb,0xf4,0xab,0x81,
+  0xfc,0x82,0x0d,0xaf,0x5a,0x67,0xdf,0x17,0xb1,0xfc,0x0f,0x2d,0x62,0x61,0x25,0xcc,
+  0x06,0xf5,0x94,0xf8,0x8f,0x08,0x8c,0x35,0xf7,0xd8,0x35,0x4d,0x43,0x93,0x72,0xcb,
+  0x2b,0x6c,0x19,0x1c,0x25,0xc7,0x96,0xd6,0x0d,0xb1,0x8d,0x2a,0x15,0x2c,0xfc,0x53,
+  0x8c,0xf8,0x67,0x89,0xee,0x3d,0x27,0x3e,0x13,0xbb,0x07,0x98,0xb7,0x39,0x57,0xb5,
+  0x8e,0x4e,0xcc,0x6d,0x3e,0x56,0xac,0x8b,0x63,0x94,0xf9,0x9f,0x63,0x88,0x7f,0xca,
+  0xd2,0x78,0x83,0xad,0x1f,0xb2,0x24,0x59,0xbc,0x9a,0xe1,0xcf,0xf7,0xcb,0x16,0x0d,
+  0x14,0x9f,0xeb,0x3c,0x07,0x13,0xa5,0xb5,0x7a,0xf1,0xb8,0x78,0x05,0xde,0x37,0x56,
+  0x54,0x1a,0xff,0xe8,0xca,0x59,0xf8,0x9b,0x21,0x5f,0xd2,0xbd,0x9d,0x3c,0x09,0x5b,
+  0x6f,0xaf,0x1a,0x72,0x5d,0x0a,0xbd,0x09,0xcf,0x85,0x17,0xbc,0x22,0xf7,0x91,0xb3,
+  0x06,0x35,0xe4,0xe0,0x7f,0x0a,0x06,0x8d,0x4d,0x84,0xc2,0x96,0xec,0xe3,0x5a,0xf5,
+  0x6b,0xee,0x60,0x29,0x83,0xc1,0x4b,0x03,0xaf,0x15,0x05,0x59,0x84,0x7a,0x58,0x08,
+  0xf4,0xb3,0x2b,0x47,0xac,0xf8,0xa5,0x97,0xef,0x51,0x0e,0x23,0xc9,0xb3,0x9d,0xec,
+  0x80,0x4f,0x33,0x63,0x79,0x9c,0x9c,0x81,0xc3,0x42,0x89,0xde,0x86,0xfc,0xc9,0x61,
+  0xa9,0xd6,0xc9,0xff,0x68,0xe5,0xeb,0xa4,0x09,0xe9,0x9a,0xfe,0xe2,0x6e,0x71,0x05,
+  0x03,0x2a,0x0d,0x7a,0xb1,0x41,0x3b,0xcc,0x46,0x63,0xb4,0x82,0x43,0x97,0xb8,0x90,
+  0xe6,0x7f,0x62,0xc2,0x33,0xca,0x5b,0x6c,0x3d,0xb8,0x87,0xc4,0x09,0x78,0x9d,0x19,
+  0x05,0x63,0xe2,0x65,0xb6,0x1e,0x38,0xad,0x71,0x49,0x30,0x96,0xca,0x34,0x3b,0xff,
+  0x13,0x30,0xbe,0xc7,0x4e,0x71,0x2d,0xbc,0x25,0xdd,0x80,0xd1,0xfc,0x0c,0x9b,0xb1,
+  0x1b,0xd9,0x0a,0x6c,0xb5,0x42,0xbf,0x9d,0xff,0x09,0xc8,0xcf,0xe1,0x7a,0x08,0x72,
+  0xd8,0x53,0xa5,0xef,0x1e,0x63,0xb3,0xf1,0x1c,0x2c,0xd0,0x65,0xfe,0xfe,0xc0,0x81,
+  0x74,0x9a,0xff,0x19,0x29,0x30,0xf6,0x5f,0x45,0x65,0xa4,0x4d,0x41,0xfe,0xa7,0x88,
+  0xcd,0x06,0xed,0x95,0xfc,0xfd,0x2e,0x9c,0x9f,0xde,0x2c,0xfe,0xc7,0xc4,0x3f,0x27,
+  0x49,0x63,0xe4,0x53,0xb4,0x68,0xd8,0xbf,0x81,0xfc,0x26,0xb8,0x28,0x3e,0x3f,0x09,
+  0x0c,0x21,0x74,0xb0,0x9f,0x46,0x32,0xf8,0x1f,0x8f,0xc1,0xff,0x54,0x88,0x5f,0xa0,
+  0xbf,0x83,0xc6,0x11,0xcf,0x0d,0xe2,0x71,0xe5,0xce,0x78,0x53,0xb2,0x24,0x28,0x1e,
+  0x87,0x3b,0x69,0x53,0xd2,0xc9,0xff,0x30,0xfc,0xf3,0x77,0x70,0x9d,0xbe,0x75,0x68,
+  0xfa,0x25,0xed,0x0d,0x68,0x78,0xd5,0xfb,0x41,0xeb,0xa5,0x30,0x67,0x84,0x3e,0x10,
+  0xad,0x4f,0xc9,0x89,0x7f,0xf8,0xec,0x81,0x28,0xc3,0xa4,0x6f,0xc9,0xab,0xb3,0xf6,
+  0x77,0xbe,0x1b,0x7b,0x37,0xd8,0x32,0x1a,0xe0,0x1e,0x8c,0x64,0xf2,0x3f,0xcc,0xff,
+  0xbc,0x85,0xfb,0xaf,0xf5,0xe2,0x6a,0xd8,0xa4,0x54,0x26,0xe4,0x6f,0x92,0x53,0xb4,
+  0x53,0xa9,0x1a,0xcc,0xcd,0xff,0x50,0x86,0x7f,0x7e,0x82,0xe3,0x6d,0x0b,0x5d,0xa3,
+  0xf6,0x46,0xfd,0x23,0xf2,0xb7,0x4b,0xaf,0x74,0x1d,0xd8,0x31,0x6f,0x24,0x37,0xff,
+  0x83,0xf8,0x87,0xfb,0xf3,0xfa,0xd0,0x72,0xe6,0x6d,0x54,0xdc,0xcf,0x0e,0x6a,0x0f,
+  0x33,0x43,0xe6,0xf3,0x29,0x65,0xf0,0x3f,0x23,0xe5,0x2c,0x5e,0x20,0xfe,0x49,0x8a,
+  0xd7,0x30,0x20,0xd4,0xd8,0xe1,0x89,0xb5,0xbe,0xc3,0x8c,0x43,0x94,0xc1,0x9e,0x11,
+  0x16,0x5d,0x32,0xf9,0x1f,0x48,0x9a,0xf1,0xe8,0xb7,0xe6,0xc6,0x1c,0xaf,0x70,0xd8,
+  0x93,0xcc,0xc5,0xff,0x60,0x74,0xab,0xd5,0xbc,0x8f,0x32,0xb4,0xf3,0x1a,0x83,0x31,
+  0x2c,0x2c,0xae,0x81,0x6f,0x40,0x1d,0x0b,0x73,0xc2,0xb0,0x94,0x83,0xff,0x59,0x23,
+  0xf1,0xf8,0x5b,0xca,0x60,0xff,0x66,0x44,0x3b,0x51,0xb6,0x6c,0x10,0xf6,0xd8,0xf9,
+  0x1c,0x1b,0xfe,0x29,0xb0,0xd8,0x9e,0xb9,0xd2,0xa3,0x20,0xb1,0x78,0x4d,0xd6,0xb0,
+  0x08,0x7e,0x3b,0x32,0x42,0xc3,0xc6,0xa3,0xa2,0xbe,0x17,0x6c,0xfe,0x87,0xc1,0x1e,
+  0x3f,0x27,0x79,0xaa,0xa1,0xc3,0x1f,0x5b,0x2e,0x97,0xbe,0x30,0x20,0xef,0xf5,0xab,
+  0xcb,0x91,0xff,0x91,0x0c,0xfe,0x07,0xd2,0xf8,0x67,0x71,0x71,0x18,0xc6,0x55,0x3e,
+  0x28,0x15,0x4e,0xf8,0x1a,0xe4,0xe2,0x88,0x88,0x57,0xf6,0xc9,0x38,0xf0,0xe9,0xd9,
+  0xfc,0x8f,0x81,0x7f,0x96,0x1a,0xfc,0x4f,0x80,0xd3,0x3e,0x03,0x70,0x61,0xde,0xb3,
+  0xcb,0xb7,0x46,0xab,0x2c,0x7e,0xe3,0x4d,0x6b,0xff,0xc5,0xf9,0x1f,0x0c,0xfa,0xed,
+  0xee,0xeb,0xe1,0xb5,0x70,0x73,0x5b,0xc9,0x43,0xe2,0x70,0xc5,0x05,0x7f,0xe3,0x72,
+  0x8f,0x8d,0x0f,0xc9,0xe6,0x7f,0xdc,0xb4,0x54,0x85,0x6e,0xa8,0x9d,0x25,0x33,0xfc,
+  0x03,0xf1,0x70,0x43,0x85,0x83,0xff,0xb1,0xe6,0xb3,0x0d,0xf1,0x8f,0xe6,0x67,0x83,
+  0xba,0xa9,0x1a,0x1e,0xd4,0x90,0xf6,0x29,0x65,0x57,0x64,0x7f,0xa8,0x5b,0x31,0x88,
+  0x20,0xcd,0xc1,0xff,0x54,0x08,0xbb,0x8c,0xf9,0x7c,0xb0,0x10,0xe7,0x3f,0xa0,0x31,
+  0x58,0x38,0x2c,0x1f,0x04,0x69,0xa9,0x0b,0xe7,0xff,0x86,0x6c,0xfe,0xc7,0x40,0x2f,
+  0xc8,0xff,0x04,0x5f,0x03,0x4e,0x5b,0xbd,0xd5,0x7d,0x01,0x4c,0x22,0xc8,0x80,0xbe,
+  0x69,0xfe,0x67,0x84,0x3d,0xff,0x42,0x01,0xbb,0xb8,0x7d,0xc6,0x9b,0x9a,0x39,0x1b,
+  0x94,0x3f,0x21,0x27,0xff,0xe3,0x87,0x58,0x8a,0xe4,0xe9,0xbc,0x8d,0x2f,0xbc,0x12,
+  0x2a,0x56,0xc1,0x38,0x69,0x40,0xd8,0x63,0xad,0xb7,0x0c,0xfe,0x07,0x18,0xfe,0x19,
+  0x26,0x7e,0xf5,0x24,0x33,0x3c,0x0c,0xff,0xd0,0x43,0x50,0x43,0x8b,0xd9,0xfe,0x4b,
+  0xe6,0x3f,0x39,0xf8,0x9f,0xf2,0x95,0xdc,0x3f,0xaf,0x08,0x16,0x7e,0x81,0x18,0x40,
+  0x68,0x6e,0x09,0x73,0x53,0x81,0xd4,0xf7,0x62,0xf8,0x9f,0x34,0xff,0x13,0x13,0x0c,
+  0x3c,0xe0,0x1e,0xbb,0xe9,0x3b,0xc2,0x23,0xc1,0xc0,0x20,0xdb,0x7d,0x94,0xc1,0x01,
+  0x75,0x5e,0xa2,0xc8,0xf6,0xfd,0xa6,0xf9,0x9f,0xdd,0x32,0xfa,0xab,0x1b,0xce,0x78,
+  0xd7,0x8a,0x5f,0x81,0x9f,0xc4,0x6e,0xfc,0x2d,0x03,0x42,0xb3,0xe1,0xe3,0xa1,0xa6,
+  0x8b,0x1e,0xe4,0x7f,0x52,0xd4,0xd0,0x3b,0x3e,0x8b,0xff,0x29,0x36,0xf1,0xcf,0x17,
+  0xb7,0xc0,0xc4,0x9a,0xe6,0x84,0x37,0xde,0xf6,0x7b,0x98,0x50,0x1b,0x12,0x29,0x44,
+  0x64,0xf0,0x3f,0x16,0xfe,0x01,0x16,0xbf,0x26,0xa3,0x3c,0x48,0x9d,0x86,0xf7,0x07,
+  0x96,0xa0,0xf1,0xae,0x3c,0x11,0xad,0x43,0xfe,0xc7,0x42,0x44,0x36,0xfe,0x07,0xf7,
+  0x5f,0xbb,0xe6,0x0f,0xb8,0x17,0x92,0x59,0x74,0x13,0xf8,0x47,0x7e,0x10,0x24,0x2f,
+  0xd0,0x03,0xb1,0xca,0xa4,0x6b,0x7d,0x6a,0xbc,0x6c,0x20,0x69,0xfc,0x03,0x90,0xda,
+  0xaf,0x8d,0x91,0x6d,0x0c,0xdd,0xcd,0x4b,0xb0,0xd1,0x9d,0xa0,0x07,0xa0,0xb2,0xdf,
+  0xee,0xaf,0x6c,0xfc,0x0f,0xdf,0x7f,0xad,0xd3,0xdd,0x0b,0xa9,0xc4,0x60,0xa4,0x5f,
+  0x17,0x83,0x2c,0xac,0xff,0x00,0x76,0xea,0x96,0x3f,0x2f,0x72,0xf2,0x3f,0x7b,0x4c,
+  0x27,0xb9,0x85,0xed,0xc7,0x59,0xe0,0x8e,0xb7,0xbe,0xc7,0x3c,0x6a,0x3d,0x06,0x1a,
+  0x6b,0xbc,0x36,0xfe,0x07,0xac,0x8b,0x38,0x51,0x4d,0x68,0x8c,0xd8,0x11,0x23,0x66,
+  0x40,0x6c,0xfc,0x8f,0xa0,0x18,0x4e,0x7b,0xeb,0x98,0xd8,0x0c,0x2f,0x33,0xc3,0xb3,
+  0x5e,0x68,0x52,0xef,0x01,0xb6,0x2d,0x1d,0x4b,0xfb,0xf3,0x34,0xff,0x43,0xa5,0x75,
+  0x9c,0xcf,0x71,0x57,0x90,0x9f,0xe1,0xfe,0x9d,0x3d,0x8d,0xec,0x06,0x8c,0xc8,0xc5,
+  0x3c,0x7e,0x91,0x6c,0xfe,0x87,0xa1,0x1d,0x76,0xf1,0x69,0xb6,0x0f,0xea,0x91,0xe6,
+  0xea,0xae,0x38,0x89,0x69,0x78,0xbf,0x15,0xef,0x9c,0xfc,0x0f,0xe2,0x1f,0xbe,0xa8,
+  0x7c,0x5b,0x34,0xb6,0xde,0x5e,0x5a,0xb1,0xb0,0x30,0xc2,0xf0,0x80,0x7a,0xe2,0x73,
+  0xe8,0xa8,0x7b,0xb5,0x1c,0xfc,0xcf,0x61,0x95,0x8d,0x6e,0xaf,0x18,0x60,0x78,0x7b,
+  0xd1,0x2b,0x25,0xfb,0xeb,0x77,0x68,0x1f,0x6b,0xf5,0x43,0xc6,0xfc,0x68,0xcd,0xaf,
+  0xb2,0x81,0xeb,0xd3,0x2c,0xfc,0x73,0x2d,0x83,0x91,0x15,0x2d,0xec,0x82,0x78,0x29,
+  0xf2,0x06,0xc2,0x80,0xb1,0x2f,0x8e,0x0d,0x4c,0x36,0xb4,0xbc,0x86,0xf1,0x9d,0xb2,
+  0xf1,0x26,0x9c,0xfc,0x0f,0xae,0x9f,0x8d,0x2d,0xc9,0xcf,0x8f,0x7f,0xf5,0x32,0xbc,
+  0xa1,0x2e,0x19,0x2e,0x3e,0x27,0x7e,0x9d,0x8e,0xab,0x0d,0xfa,0xfd,0x63,0xe2,0x37,
+  0xb5,0x97,0x68,0x7d,0xac,0xf8,0x03,0x31,0x68,0xe7,0x7f,0x4c,0x90,0x33,0x4a,0xb7,
+  0x46,0x7d,0x09,0xf7,0x9d,0x91,0xa6,0xd5,0xae,0x0d,0x55,0x27,0xe5,0x8f,0x23,0xa0,
+  0xec,0x90,0xfc,0xd4,0xf5,0x10,0x89,0xd9,0xf6,0x5f,0xd6,0x1f,0x7d,0x0b,0x3c,0xcc,
+  0x3f,0xb4,0xd2,0x95,0x74,0xbb,0x20,0x0d,0xf4,0x04,0xc9,0x4a,0x29,0x32,0x4f,0xbd,
+  0x4f,0x56,0x19,0xde,0x4b,0xf3,0x51,0x7b,0xcc,0x49,0x1b,0x84,0x9f,0x42,0x4d,0xff,
+  0xe7,0xe2,0xc4,0x03,0xf7,0x69,0x2a,0x4e,0x6c,0x40,0x78,0x92,0x7d,0xc8,0xcc,0xd1,
+  0xc5,0x2d,0xff,0xa3,0x95,0x5b,0x7f,0xf4,0x3d,0xf0,0xba,0xd0,0xa8,0x7f,0x3e,0xfe,
+  0xd5,0x75,0xf2,0x85,0x68,0x03,0x5b,0x0f,0x55,0x61,0x38,0x2a,0xd4,0x51,0xcf,0x6e,
+  0x51,0xb1,0xd6,0x4f,0x52,0x78,0x26,0x8d,0x87,0x5f,0x87,0x45,0xfd,0xee,0xb1,0xaa,
+  0x4b,0x70,0x59,0x6a,0xc1,0x27,0x8c,0xc1,0x65,0x68,0xa1,0xde,0x01,0x71,0xdc,0x5a,
+  0x3f,0xba,0xb2,0x47,0x30,0x57,0x97,0xf2,0x31,0xc3,0x57,0xd7,0x05,0xc5,0x40,0x51,
+  0x42,0xab,0x4b,0x14,0xaf,0xef,0x1c,0xad,0x38,0x06,0xec,0xf9,0x7d,0x4e,0xfc,0x63,
+  0xbe,0xff,0x25,0x68,0x61,0xcb,0x60,0xeb,0x98,0xab,0x99,0x76,0xc1,0xa7,0xf5,0xe5,
+  0x63,0x64,0xc1,0xf6,0x93,0xc9,0x86,0x6d,0xc5,0xdb,0x6c,0xf8,0x27,0x99,0xc2,0x3f,
+  0x9c,0x1f,0xe3,0x13,0xb5,0x98,0x4d,0x14,0x05,0xff,0xd0,0xf6,0x20,0x79,0x9c,0x3e,
+  0x9a,0xac,0xa1,0x72,0x34,0x92,0xc1,0xff,0x60,0xfe,0x6b,0x83,0x8f,0x47,0xff,0x61,
+  0x17,0xdb,0x88,0xd1,0xc2,0xd8,0xa7,0x87,0xc9,0x06,0xf2,0x90,0x5c,0x4e,0xe7,0xc4,
+  0x84,0x4c,0xfc,0xd3,0x4b,0xbf,0x83,0x49,0xae,0x95,0xf0,0x21,0xc1,0xb4,0x57,0xe4,
+  0x67,0x0f,0x15,0xc5,0x18,0x10,0x0a,0x8a,0x83,0xf4,0x66,0x25,0x48,0x3d,0x90,0x81,
+  0x7f,0xf8,0x6e,0x62,0x8c,0xed,0x2f,0x26,0x49,0xbd,0xbe,0xf5,0x5c,0xe7,0xff,0x66,
+  0x13,0xd5,0x3c,0x54,0xf2,0x6f,0x9d,0xdf,0x81,0x2b,0x5d,0x2d,0x08,0x15,0x6c,0xf8,
+  0xa7,0x7c,0x34,0xfd,0xf5,0x4d,0x6a,0xec,0x0f,0x51,0xc7,0x80,0xfa,0xf3,0x75,0x3e,
+  0x3d,0x70,0x9e,0x45,0xcc,0x83,0x84,0xe1,0x07,0x9a,0xc5,0xff,0xdc,0xc0,0x9c,0x06,
+  0x9c,0xa2,0x07,0xd6,0x22,0xff,0x13,0xf2,0x44,0x7f,0x22,0xcf,0x3b,0xc1,0x80,0x90,
+  0x02,0x4f,0xc1,0x7c,0xea,0x0e,0xe7,0xe1,0x7f,0x78,0xda,0x6b,0x33,0x1b,0xb8,0xf6,
+  0x0f,0xb1,0xea,0x64,0xdb,0x5d,0xbe,0xd9,0xf0,0x74,0x64,0x7e,0xcc,0xbd,0x9a,0x8c,
+  0x59,0x9f,0x4b,0x9b,0x34,0x28,0xa5,0xf8,0xc6,0x51,0x21,0x45,0xe3,0x6f,0x81,0x9f,
+  0xd2,0x80,0xde,0x1d,0x24,0x1e,0x65,0x1f,0xfb,0x4a,0xd9,0x0c,0xd8,0xf8,0x9f,0x82,
+  0x14,0xff,0x83,0x68,0x07,0x8d,0x6b,0xd1,0x38,0x89,0xfc,0x4f,0xcc,0xed,0x67,0x57,
+  0x16,0x50,0xef,0x70,0x16,0xff,0xd3,0x68,0xc0,0x1e,0x8c,0x3e,0xd7,0xd1,0x6b,0x6e,
+  0x83,0xf1,0xab,0xd9,0x15,0x69,0x46,0x12,0x2e,0x65,0xe1,0x1f,0xb0,0x65,0x37,0xfa,
+  0x11,0xf6,0x54,0xb4,0x76,0xc1,0x8b,0xb1,0x46,0x0d,0x1e,0x14,0xd7,0xc8,0x3c,0x62,
+  0x6e,0xcf,0xc9,0xff,0xf8,0x86,0x09,0xc7,0x3f,0x0f,0x92,0x39,0x91,0xcd,0xba,0x4f,
+  0x6b,0xfb,0x1e,0x99,0x03,0x07,0xb5,0x5a,0xcd,0xef,0xe0,0x7f,0xca,0x39,0xff,0xb3,
+  0x94,0xa3,0xa3,0xcd,0xa0,0x6a,0xae,0xa8,0x6f,0x17,0xd9,0xcc,0x22,0x3e,0x03,0x4e,
+  0x5f,0x83,0x9f,0x87,0xd6,0x69,0xab,0x1f,0x24,0x19,0xf8,0xc7,0x08,0xfa,0xc3,0xb1,
+  0x0e,0xbf,0xaa,0xc9,0x75,0x11,0x89,0x19,0xc9,0xe5,0x35,0xa5,0x91,0x32,0x36,0xff,
+  0x1e,0x4d,0x2e,0x8d,0x38,0xf1,0x4f,0x0a,0xef,0x25,0xbb,0x12,0x6a,0x1c,0xbc,0x11,
+  0x31,0xc6,0x8c,0x46,0x59,0x26,0x62,0x18,0x4e,0xc1,0x6c,0xf0,0x44,0xc4,0xe3,0xa2,
+  0xf9,0x3e,0xdb,0x8b,0xd3,0xe3,0x8d,0x5d,0x80,0xd9,0xcb,0xbd,0x0f,0x3d,0xcc,0x0c,
+  0x7f,0xf3,0xf2,0x62,0xc3,0xb8,0x67,0xb9,0xfb,0x95,0xe7,0xdf,0x9c,0x66,0xce,0x67,
+  0x45,0x41,0xfa,0xfe,0xe8,0x05,0xb5,0x59,0x2b,0xfe,0x15,0x59,0xa3,0xbe,0x56,0xd6,
+  0x10,0x2a,0x79,0x58,0xac,0xd6,0x8e,0x2a,0x75,0x0c,0x48,0x74,0xde,0x94,0x03,0xff,
+  0x90,0x24,0xed,0x6b,0xaf,0x2d,0x72,0x6f,0x22,0x82,0x42,0xdb,0x77,0x56,0xb4,0x6d,
+  0x2a,0x8d,0x95,0xde,0xa7,0xee,0x94,0xe5,0x01,0x92,0xc1,0xff,0x60,0xbe,0x4f,0x21,
+  0xbf,0x50,0xd9,0xc0,0x5b,0x8b,0x14,0x72,0x4b,0xec,0xbb,0xea,0x9c,0x90,0xab,0x9d,
+  0x94,0xd1,0x8d,0x50,0x15,0x92,0xdb,0xa9,0x8d,0xff,0x29,0xdf,0x65,0xcf,0x1e,0xce,
+  0x5d,0xea,0x56,0x4a,0xaf,0x87,0x8d,0xe4,0xab,0x9a,0xdc,0x4e,0x1e,0x81,0x8d,0x4a,
+  0xd5,0xd2,0xb6,0xa1,0x88,0x8d,0xff,0x29,0xcf,0xc8,0x5e,0x71,0x7c,0xfb,0x9a,0xda,
+  0xa0,0x7d,0x21,0x5a,0x35,0xa7,0xe2,0xe8,0xb2,0xa0,0x16,0xd8,0x26,0xae,0xb5,0xfc,
+  0xcf,0x6e,0x21,0x83,0xff,0xd9,0xca,0xf1,0x21,0x34,0x85,0xcc,0x2b,0xa1,0x05,0xd1,
+  0xce,0x74,0xfc,0xf5,0xa7,0xf3,0x5f,0x49,0x48,0x30,0x63,0x56,0xb7,0xa8,0x76,0x8c,
+  0x40,0x03,0x02,0xa1,0x1d,0x90,0x08,0x35,0x83,0x67,0x99,0xe8,0xca,0xc6,0x3f,0x0c,
+  0xed,0xc0,0x7d,0xa4,0x96,0xba,0x76,0x21,0xff,0x23,0x71,0xfe,0xc7,0x0f,0x27,0x85,
+  0x5a,0x06,0x84,0x5c,0xae,0x34,0xfe,0x31,0xf7,0x5f,0x18,0x9d,0x3b,0xf1,0x7b,0x59,
+  0x5c,0x58,0x0c,0x8f,0x53,0xff,0x18,0xfb,0x82,0x1e,0xc0,0x2b,0x63,0xfe,0x26,0xe2,
+  0xb2,0xfc,0x8f,0x85,0x7f,0xd6,0x93,0xe3,0xf4,0x11,0x98,0x3f,0xea,0x0a,0xb2,0x65,
+  0xb3,0x49,0x9e,0x37,0x24,0x87,0xc9,0xb5,0xf0,0x88,0xf4,0xf5,0x48,0xd1,0xfa,0x88,
+  0xdf,0x7a,0x3e,0xe2,0x1f,0x04,0x39,0xc5,0x0c,0xed,0x44,0x7e,0xc9,0xd0,0x88,0xbc,
+  0x56,0x9c,0x4d,0x7e,0x4c,0x97,0x24,0x6b,0xc7,0xc5,0x43,0x0c,0x7a,0xb4,0x24,0x3d,
+  0x27,0xc4,0x9a,0x34,0xff,0x73,0xad,0x81,0x7f,0xdc,0x71,0xf1,0xbd,0x18,0xdb,0xbd,
+  0x9e,0xf4,0xc6,0xdc,0xc3,0x70,0x17,0xec,0xb3,0xe2,0x3b,0xc5,0xfd,0x42,0xa9,0x39,
+  0x3f,0x88,0x7f,0x9e,0x43,0x90,0xd3,0x27,0x5e,0x51,0x5f,0x46,0xe3,0xa0,0xf8,0xd7,
+  0xd2,0x4b,0x91,0x7a,0x75,0xeb,0xf8,0xb4,0x17,0xe0,0x45,0x1a,0x4c,0xae,0x1c,0x11,
+  0x75,0x27,0xff,0xc3,0xf6,0x5f,0x25,0x77,0x95,0x5e,0xa1,0xff,0x82,0x8e,0x77,0x43,
+  0x61,0xe9,0xab,0x1b,0x63,0x95,0xeb,0xae,0xb9,0x8d,0xed,0xa7,0x36,0xed,0xae,0x1c,
+  0x95,0x6f,0x0f,0xd9,0xf2,0x5f,0x26,0xfe,0xc1,0x6d,0x1a,0xf2,0x5d,0xee,0x3a,0xe6,
+  0xa8,0x23,0x7e,0x55,0x66,0x78,0x69,0x0c,0x1e,0x08,0x56,0xe9,0xf2,0x5a,0x9a,0x89,
+  0x7f,0x02,0xc6,0xee,0xf5,0x61,0xa1,0x56,0xe7,0x1b,0x8d,0x08,0xdd,0xb9,0x94,0xc5,
+  0xaf,0x41,0x09,0xf5,0x1b,0xb2,0x3f,0x13,0xff,0x00,0x57,0x53,0x5c,0x82,0x17,0xd1,
+  0xf1,0x06,0xc5,0x75,0xd2,0x8b,0x50,0xd7,0xef,0x8d,0xce,0x18,0x85,0xa3,0x5a,0x9d,
+  0x16,0xe8,0x13,0xd3,0xef,0x63,0xc3,0x3f,0xa3,0xf0,0xa1,0xd0,0xdc,0xbf,0x8a,0x19,
+  0x84,0xc1,0x00,0xcc,0x18,0x8e,0x4a,0x13,0xb8,0x54,0x10,0xff,0x98,0xcf,0x37,0xf1,
+  0x4f,0x8a,0xff,0xa9,0xd7,0x4b,0xce,0x88,0xcf,0x46,0xde,0x82,0xfa,0x64,0xc9,0x07,
+  0xe2,0x62,0x18,0xac,0xa8,0x6f,0xf7,0xb4,0xdb,0xf8,0x9f,0x0e,0x33,0xff,0x65,0xa0,
+  0x97,0xab,0xf4,0xb6,0xdd,0x24,0x00,0x3d,0xaa,0x6f,0x58,0xc6,0x40,0xcc,0xde,0x1f,
+  0xd8,0x46,0x40,0x75,0xe0,0x1f,0xdb,0xfd,0x84,0x85,0x69,0xd7,0x6e,0xe6,0x91,0x7c,
+  0x14,0x89,0x6b,0x66,0xd4,0xe8,0xae,0x58,0x26,0xff,0x73,0x3d,0xc6,0xbb,0xc8,0x20,
+  0xdb,0xe6,0x57,0x33,0xb7,0x7c,0x9f,0x0c,0x1d,0x3e,0xf5,0x57,0x32,0xb8,0x02,0x6a,
+  0x27,0xec,0x4e,0xb8,0x54,0x1b,0xff,0xc3,0xf3,0x5f,0xc6,0x78,0x2f,0xc5,0x26,0xa0,
+  0x7e,0xa0,0x64,0x9f,0xfb,0x1f,0xf5,0x77,0xcb,0xea,0xb6,0x97,0xc4,0x45,0x95,0x32,
+  0x47,0xa4,0xb3,0x8d,0x2a,0x4d,0xe7,0xbf,0xae,0x66,0xf8,0x27,0xcc,0xc7,0x8b,0x1b,
+  0x73,0x44,0x3b,0xc2,0x65,0x98,0x08,0x3e,0x7b,0x82,0xcf,0xc0,0xc7,0xda,0xa2,0x21,
+  0x16,0xbf,0x9c,0xf9,0xaf,0xb7,0x0c,0x91,0xcf,0xb3,0x30,0x19,0xac,0x4f,0x78,0x12,
+  0xe2,0x28,0x4d,0xd0,0xd9,0xbf,0xf7,0xda,0xf0,0xb3,0x2d,0xff,0x55,0xc1,0xf0,0x8f,
+  0x8a,0x22,0x9f,0xdb,0x6b,0xe1,0xb9,0x3b,0x3f,0x7d,0x4a,0xee,0x0e,0xfd,0xab,0xde,
+  0x43,0x6b,0x13,0xee,0x9c,0xfc,0x0f,0xe2,0x9f,0xc7,0xe5,0xea,0x14,0xdf,0xa5,0xaa,
+  0x47,0x64,0x28,0x1d,0xac,0x8e,0x11,0x1e,0xf1,0xad,0xfd,0x85,0x23,0xff,0xc5,0x40,
+  0xe6,0x5c,0x9d,0xd3,0x6e,0xbd,0x92,0x5f,0xf7,0x77,0x91,0xd1,0xb2,0x9f,0xa6,0x67,
+  0x38,0xc5,0xff,0x58,0xeb,0x53,0xda,0x03,0xbf,0x63,0xb0,0xc4,0x1b,0x24,0xb8,0x90,
+  0x7c,0x3a,0xdb,0x76,0x8d,0x62,0x62,0x42,0xb7,0xef,0x17,0x6c,0xf9,0x2f,0x9e,0x0f,
+  0x3d,0xcc,0xd7,0x83,0xcc,0x03,0xfd,0x30,0x9b,0x96,0x37,0x8e,0x19,0x2b,0x44,0x4a,
+  0x2d,0x95,0x71,0xcd,0xbc,0x9f,0xe1,0x1f,0x40,0xd9,0xcf,0xd6,0x7d,0xfc,0x69,0x75,
+  0xfa,0xca,0x6d,0x30,0xea,0x49,0x68,0xb3,0xfb,0xed,0xcf,0xcf,0xc8,0x7f,0xc9,0x35,
+  0xba,0x7b,0x3f,0x7b,0xff,0xe7,0xa4,0x2a,0xdd,0x1f,0x0b,0x5d,0xe2,0x40,0xda,0xfe,
+  0xfe,0xb6,0xfc,0x97,0x89,0x7f,0xae,0x27,0x83,0x4a,0x3d,0xa8,0xfa,0x72,0x95,0xdd,
+  0x46,0xc1,0x39,0x3f,0x19,0xf8,0x27,0xca,0xf1,0x00,0x6e,0xac,0x76,0x8c,0xba,0x37,
+  0x84,0x4e,0x6b,0x5d,0xdd,0x5c,0xff,0x63,0xf1,0x21,0x19,0xfc,0x4f,0x8c,0xe3,0x9f,
+  0xc1,0xe8,0x87,0x50,0x97,0x2c,0xa9,0xfc,0xea,0x71,0xfd,0xf9,0x78,0xd3,0x08,0x5e,
+  0x81,0x0f,0xb3,0xf4,0x3f,0x88,0x7f,0x84,0x25,0xba,0xfb,0x1b,0xb8,0x7e,0xe4,0x96,
+  0x13,0x2b,0x3f,0x10,0x2f,0x1b,0xdf,0xd7,0x58,0x3e,0xfe,0x67,0x82,0xd6,0xf1,0xcf,
+  0x96,0x2d,0xbc,0xba,0xa1,0x4d,0xdb,0xd4,0xf7,0x18,0xca,0x61,0x33,0x66,0xdf,0xbf,
+  0x38,0xf0,0xcf,0x73,0x80,0x22,0x81,0xd2,0x59,0xd0,0xeb,0xaf,0x4c,0xc8,0xff,0xd3,
+  0x37,0x48,0xbb,0x54,0xee,0x51,0x6d,0xfc,0x8f,0xf9,0x7c,0x9d,0x05,0xd8,0x9f,0xd0,
+  0xca,0xe4,0x8a,0x0d,0xa5,0x3f,0x14,0x0e,0xd0,0xca,0x61,0xd7,0xea,0x9d,0xa7,0xdb,
+  0x37,0x75,0x59,0x19,0x31,0x34,0x42,0x8e,0xfc,0x17,0xc3,0x3f,0x31,0xe4,0xf3,0x91,
+  0x5f,0x55,0xfb,0xdb,0x1a,0xd0,0xb1,0x0b,0x1e,0xc7,0x7c,0xda,0xf3,0x5f,0x23,0xf0,
+  0x0e,0x03,0xb1,0x5e,0xd5,0x8b,0x40,0xa8,0xae,0x63,0xf6,0x2e,0x11,0x15,0x41,0xd7,
+  0x98,0x88,0xe8,0x6e,0x34,0xec,0xf8,0x87,0xc5,0x23,0x0d,0xe3,0x51,0x01,0xe6,0x83,
+  0x2e,0x41,0x49,0x97,0xa8,0xbb,0xc6,0x6f,0x6a,0x4e,0x23,0xa2,0x2c,0xfe,0xe7,0x6d,
+  0x16,0xe6,0xa6,0x7d,0x9f,0x85,0xc5,0x0f,0x18,0xfe,0x59,0xf9,0xd8,0x8c,0x35,0xd2,
+  0x51,0x32,0xdb,0xce,0x0f,0x38,0xf1,0x8f,0xcc,0xe3,0xef,0xf6,0xdb,0xab,0x39,0xed,
+  0xe3,0xaa,0x63,0x6e,0xe4,0xa7,0x61,0x2e,0x04,0xca,0xc5,0xff,0x48,0x16,0xff,0xb3,
+  0x86,0xdf,0xef,0x8f,0xfa,0xd6,0x40,0x0f,0x0d,0x20,0xfe,0xb1,0xe9,0x7f,0xcc,0x7f,
+  0x36,0xfc,0x23,0x61,0xb6,0x6b,0xb9,0x1c,0x2d,0x94,0x62,0x3b,0xd8,0x95,0x22,0x1b,
+  0x1f,0x72,0xc4,0xba,0x7f,0xb1,0x1c,0x86,0x8b,0x5c,0xdd,0x54,0x15,0x96,0xfa,0xd4,
+  0xb8,0xbc,0x92,0x8a,0x61,0x9a,0x30,0xf4,0x27,0x6c,0xbc,0x85,0x7c,0xbc,0xc7,0x89,
+  0x85,0x7f,0xae,0xdd,0x85,0xb2,0x1f,0x6d,0x55,0x74,0xc6,0x30,0xd7,0xff,0x18,0x40,
+  0x48,0x32,0x8c,0x1c,0xfc,0xcf,0xf4,0x61,0xe1,0xb2,0xa1,0x17,0xaa,0x86,0x0b,0x0b,
+  0x67,0x33,0xfc,0x26,0xfc,0x5e,0xba,0x20,0x34,0x6a,0x79,0xf8,0x9f,0x0a,0xc4,0x3f,
+  0x8d,0x0c,0xff,0xb8,0xc3,0xb0,0x38,0x58,0x5b,0x2a,0x53,0x72,0x46,0xef,0x43,0xb7,
+  0x9c,0x93,0xff,0xe1,0xf8,0x07,0xf9,0xae,0x20,0x59,0x06,0x7b,0xd5,0x75,0x2b,0x67,
+  0x2a,0xa5,0x03,0xd1,0x83,0x10,0x58,0x2e,0xdb,0xc7,0x6b,0xcf,0x7f,0xb1,0x8f,0xb4,
+  0x86,0xcf,0x27,0xe6,0x1f,0xb5,0x22,0x06,0x44,0xe1,0xa0,0xef,0x0b,0x9a,0x2b,0x3d,
+  0x9f,0xa5,0x2f,0x38,0xf2,0x5f,0x07,0x0d,0xfd,0x0f,0x7b,0x7f,0xd2,0xbc,0xf4,0x1f,
+  0xf0,0xb5,0x3f,0xf8,0x5a,0xf3,0x52,0xfe,0xfe,0x37,0x40,0x86,0xfe,0xe7,0x49,0x65,
+  0x97,0x4d,0xf6,0x43,0xac,0xfc,0x57,0x9d,0x83,0xff,0x79,0x87,0x9a,0xcf,0x37,0xf0,
+  0x4f,0x9d,0xc1,0xbf,0xa1,0xd1,0xd6,0xd1,0x99,0x54,0x4e,0x68,0xcd,0x4e,0xfe,0xc7,
+  0x91,0xff,0x3a,0x8b,0x22,0x9f,0xdf,0x87,0xfc,0xd2,0x21,0xa1,0x81,0xca,0x7b,0xc8,
+  0x88,0x7c,0x1f,0xd4,0x76,0x20,0xff,0xe3,0x49,0x41,0xa3,0x84,0x62,0xfa,0x07,0xcc,
+  0x7f,0xed,0x88,0xa9,0xfa,0x4c,0x70,0xe1,0xc6,0x7c,0x2e,0x03,0x42,0x85,0x2c,0x70,
+  0x33,0x37,0xe5,0xe0,0x7f,0x54,0x7b,0xfe,0xeb,0x29,0x9d,0x7d,0xbf,0xed,0x84,0x01,
+  0x21,0x5a,0x8d,0xb4,0xcf,0x69,0x0e,0x0c,0x8a,0xd6,0x17,0x5a,0xdf,0xaf,0x33,0xff,
+  0x75,0x89,0xee,0x4d,0x7a,0xdb,0xc4,0xd9,0x0c,0x78,0x7c,0xe6,0xdc,0xe7,0x37,0x54,
+  0x4d,0x4a,0xff,0x8c,0xb0,0xc7,0xc6,0xff,0x38,0xf3,0x5f,0x3c,0x89,0xa3,0xa0,0xf7,
+  0x58,0xd3,0x3c,0xe4,0xda,0xdf,0x39,0xaa,0x5e,0x5c,0xdb,0xfc,0xcf,0x0e,0xfe,0xc7,
+  0xf2,0x3f,0x5a,0xc1,0x15,0xed,0x23,0x8c,0x5f,0x4f,0x88,0x77,0x6b,0x93,0x83,0x75,
+  0xc3,0x9e,0x27,0xd8,0xf8,0x5f,0xa6,0xf5,0x63,0xd3,0xc6,0xc5,0xb3,0x30,0x11,0x6d,
+  0x4e,0x7a,0x2f,0x64,0xe4,0xbf,0xf6,0xa1,0x48,0xe9,0xff,0x16,0x4f,0xd3,0xe7,0x40,
+  0x4d,0xba,0xfe,0x9a,0x9c,0xd6,0xb7,0xd2,0x79,0x23,0xec,0xb5,0x4f,0x1b,0x5b,0x4b,
+  0x3b,0xff,0x43,0xe1,0x31,0xa9,0x01,0xfd,0x55,0x88,0xa0,0xf0,0x49,0xd5,0xe5,0x10,
+  0x39,0xa5,0xfc,0xa3,0xa7,0x12,0x89,0xa0,0x53,0x0a,0x8e,0x77,0xc5,0xfa,0x50,0xd2,
+  0xf2,0x3f,0x61,0x86,0x7f,0xf6,0xb1,0xdb,0xdc,0xc0,0x60,0xd2,0x61,0x08,0xeb,0xae,
+  0x22,0x36,0x9f,0x3b,0xfb,0xd7,0x72,0xff,0xa3,0xa4,0xe6,0x33,0x9d,0xff,0xf2,0x33,
+  0xfc,0x13,0x67,0x61,0xcb,0x0b,0xcc,0x7f,0x72,0xda,0x67,0x1b,0x73,0xb3,0x4f,0x3e,
+  0x5c,0xe5,0x88,0x5f,0xc7,0x1c,0xf8,0xe7,0x22,0x5e,0xec,0x9a,0x81,0xbf,0x5e,0xd1,
+  0x57,0x6d,0x7b,0x78,0x94,0xbc,0x66,0xe7,0x7f,0xae,0xcb,0xc4,0x3f,0x97,0xb4,0x7a,
+  0xdd,0x3b,0x88,0x7a,0x06,0xb2,0xb0,0xdf,0x93,0x14,0x07,0xe5,0x53,0xb0,0x28,0xed,
+  0xcf,0x57,0x21,0xff,0x63,0xe5,0xbf,0x18,0xfe,0x39,0x84,0xf9,0x97,0x2d,0xbe,0x00,
+  0xa7,0x7d,0xe4,0x1f,0x95,0x8e,0x42,0x77,0xdb,0x1d,0xce,0xf8,0xeb,0xc8,0x7f,0x7d,
+  0x1f,0xef,0xa7,0x91,0x3d,0xc6,0xfd,0xdb,0xd8,0x6d,0xdf,0x2f,0xab,0x71,0xdc,0x6f,
+  0xe3,0x7f,0xc0,0x03,0xfb,0xc2,0x6c,0x7e,0x08,0xf1,0x50,0xe6,0x9f,0x07,0xe5,0x52,
+  0x32,0xa8,0x76,0xc8,0x5c,0x0f,0xcc,0x10,0x91,0x6a,0xe0,0x81,0x02,0x73,0x3d,0x80,
+  0xbc,0xae,0xe8,0xe4,0xda,0x3a,0x44,0x77,0x7b,0xba,0x26,0xa1,0xf7,0xd8,0x96,0x48,
+  0xe7,0xa5,0xb6,0x13,0xed,0xf5,0x27,0x71,0xbc,0x74,0xc2,0x6f,0xc4,0x77,0x07,0xff,
+  0x73,0x51,0x65,0x41,0x6a,0xa9,0x38,0xaa,0x4d,0x92,0x96,0xc4,0x02,0x9d,0x0d,0x73,
+  0x5c,0x68,0xc6,0xb4,0xd7,0x25,0x0d,0x15,0x1d,0xc8,0xff,0x48,0x69,0xbc,0x71,0x05,
+  0x26,0xba,0x38,0xc8,0x39,0x2b,0xbd,0x51,0x59,0x3f,0xc8,0x56,0xcb,0x1b,0x65,0xbf,
+  0xeb,0xa8,0xfb,0x45,0xe0,0x23,0xb1,0x09,0x5e,0x4e,0xe1,0x9f,0x34,0x3e,0xb1,0xf1,
+  0x3f,0xf0,0x3f,0xa2,0x9f,0x7e,0xc9,0xbd,0x8f,0x8c,0xd2,0x9e,0x6a,0x5f,0x87,0xeb,
+  0x63,0xd2,0x14,0xe3,0x40,0x25,0x3b,0xff,0x95,0x8a,0xe6,0x0f,0x83,0x3f,0xd1,0x1a,
+  0xf4,0xb1,0xfd,0xb8,0xac,0x76,0xcb,0x75,0xc4,0xd3,0xf5,0xb8,0x89,0x7f,0xcc,0xbf,
+  0xaf,0x8d,0xff,0x19,0x55,0x7e,0x8a,0x69,0xc4,0x78,0x68,0x54,0xe9,0x81,0x18,0xca,
+  0x84,0x02,0xf0,0x53,0xc8,0xc8,0x7f,0xe9,0xe5,0xa3,0x8a,0x85,0x87,0x5f,0x97,0x1a,
+  0x91,0xf6,0x19,0x85,0x33,0xd1,0x73,0x9a,0x27,0x2e,0x06,0x0c,0xe9,0x0e,0xea,0x9f,
+  0xd3,0xfb,0x97,0x67,0xe4,0xe7,0xd2,0x78,0x78,0x01,0xfe,0xf5,0x2f,0xc1,0x65,0xda,
+  0xa2,0xda,0xe3,0xbb,0x3d,0xff,0xb5,0x47,0xb6,0xf8,0xc6,0x5f,0x33,0x58,0xb5,0x05,
+  0x8d,0xa3,0x72,0x03,0x61,0xcf,0xf7,0x68,0x2f,0x42,0xf3,0x60,0x49,0x3c,0x07,0xff,
+  0x53,0x14,0x67,0x0b,0x75,0x2b,0x4f,0x7b,0xb1,0xff,0x67,0xb3,0xea,0x6b,0xab,0x18,
+  0xeb,0xfc,0xdf,0xf2,0x8b,0xe8,0x58,0xe2,0xb9,0xf9,0x9f,0x2d,0x5c,0x26,0x27,0x23,
+  0x90,0xeb,0x80,0xea,0x76,0xb9,0x29,0xf2,0x80,0x8f,0x5d,0x19,0x72,0xd9,0xf1,0xcf,
+  0x78,0x2a,0xff,0x85,0xd9,0x1f,0xfa,0x08,0x9d,0x3f,0x22,0x6f,0x28,0x7c,0x96,0x6e,
+  0x8d,0xdc,0xe6,0x97,0x11,0x0f,0x6c,0x8a,0xcd,0x1f,0x81,0x0c,0xfc,0x23,0x7d,0x48,
+  0xbf,0xd3,0xef,0x5d,0x22,0xfe,0x8c,0xbd,0xff,0x1d,0x49,0xf9,0xb0,0xf8,0x00,0x7d,
+  0x9e,0x36,0x04,0xda,0xe3,0x78,0x85,0xf9,0x87,0x12,0x07,0xfe,0xf9,0x7b,0x83,0xff,
+  0xb9,0x1f,0x67,0xe3,0x7d,0xf9,0xee,0x17,0xd8,0x6c,0x7c,0x27,0x34,0xa9,0xb4,0x2c,
+  0x65,0xc6,0xdd,0x39,0xf0,0x8f,0x60,0xdb,0x8f,0x30,0x98,0xc4,0x69,0x6a,0xf1,0x45,
+  0xa9,0x4e,0x5f,0xb5,0xbf,0x73,0xbe,0xce,0xa5,0xd1,0x7d,0x6e,0x57,0x3a,0xff,0xf5,
+  0xa0,0xa9,0xff,0x41,0xb4,0xe3,0x9f,0x3f,0xc0,0x69,0xf3,0x8d,0xd0,0x41,0x19,0x02,
+  0x9c,0xed,0xdb,0x64,0xfc,0xb4,0xcf,0x91,0xff,0x32,0x40,0x0e,0xe7,0xbb,0x02,0x23,
+  0xae,0x0d,0xe4,0x0a,0x7c,0x37,0x52,0x19,0x9b,0x79,0x17,0xf9,0x21,0x45,0x05,0xd4,
+  0x8a,0x0d,0x21,0xc8,0xd6,0xff,0xb0,0xf5,0x26,0xf7,0x9a,0x34,0xfe,0xa3,0x82,0x3a,
+  0xe0,0x0e,0xba,0xb6,0x30,0x20,0xca,0x7f,0x7a,0xc8,0xaa,0x17,0x48,0x96,0x67,0xf0,
+  0x3f,0x5e,0x83,0xff,0xe9,0xdd,0xc1,0x8c,0xdd,0x86,0x34,0x3a,0x26,0x2e,0x96,0xac,
+  0xf9,0x84,0xa4,0x60,0xea,0x51,0x53,0xd1,0x67,0xc6,0x19,0x69,0xc4,0x7e,0x65,0x6b,
+  0x76,0xfe,0x8b,0x27,0x41,0x0c,0x83,0x85,0x45,0x54,0x44,0xf7,0x69,0x7b,0x50,0x08,
+  0x7d,0x54,0xd9,0xa7,0x95,0x64,0xe0,0x1f,0x9e,0x2f,0x4b,0xf1,0x0f,0x77,0x20,0xec,
+  0xa9,0x76,0x15,0xa1,0xfe,0x27,0x3a,0x63,0x0d,0x6c,0xa6,0x3c,0x23,0xe6,0xcc,0x7f,
+  0x3d,0x9a,0xc6,0x3f,0x01,0x54,0xa7,0x74,0xa9,0x9b,0x29,0x97,0xa9,0x48,0xb0,0x59,
+  0x08,0x63,0xe0,0x76,0xf2,0x3f,0x3b,0x52,0x6a,0x67,0x04,0x06,0xcb,0x8b,0xf0,0xb6,
+  0x0e,0x5a,0xbd,0x42,0x2e,0x3d,0xb2,0x2c,0xd6,0x09,0x19,0xfa,0x1f,0xe4,0x7f,0xb6,
+  0xf3,0xd1,0xb1,0xff,0xd1,0x71,0xb5,0x56,0x66,0x61,0x37,0x06,0xba,0xd8,0x28,0xcb,
+  0x11,0x11,0x22,0x6d,0x2c,0x22,0x97,0x60,0xfe,0xcb,0x7c,0x9f,0x13,0xd7,0xda,0xf9,
+  0x1f,0x84,0x3d,0x0f,0x75,0xbe,0x1a,0xbb,0x5c,0xb3,0x88,0x19,0x8f,0x23,0xff,0x33,
+  0x7b,0xf9,0x34,0xa5,0x35,0x37,0xff,0x03,0x47,0x3d,0x35,0xa1,0x92,0x07,0x99,0xf1,
+  0x22,0xdb,0xf6,0x7a,0xbe,0x27,0xee,0xa2,0x2f,0x91,0x16,0x84,0x46,0x2f,0x94,0x9a,
+  0xdf,0xfb,0x06,0x8b,0xff,0x61,0xaf,0xd1,0x0d,0xbe,0x0a,0x86,0x7f,0xf4,0x0e,0x0a,
+  0x3e,0xb9,0x7b,0x93,0x6b,0x21,0xed,0x66,0x6f,0xe8,0xd0,0x3f,0x1b,0xfc,0x8f,0x31,
+  0xde,0x9d,0x1d,0xe0,0x0f,0xb9,0x4a,0xc9,0xab,0xfe,0x8d,0x52,0xe5,0xcd,0x72,0x3b,
+  0x29,0x47,0xc7,0x1b,0x72,0xe6,0xbf,0xd2,0xfc,0x4f,0x17,0xe7,0xd3,0xe4,0x68,0x68,
+  0x80,0xdc,0xaf,0x54,0x69,0xf2,0x10,0xb9,0x9e,0x5d,0xe1,0x54,0xdb,0x9b,0xb9,0xf9,
+  0x9f,0xa3,0x04,0x65,0x3c,0x22,0x12,0x71,0xfb,0xda,0x02,0xd1,0x19,0xbb,0x08,0x4a,
+  0xdf,0xa7,0xd9,0xf1,0xcf,0x88,0x50,0x9d,0xbe,0xff,0x1b,0x02,0x02,0x45,0x71,0x98,
+  0xf0,0x8c,0xa1,0x22,0x0e,0x4c,0x37,0x7e,0xaa,0xba,0x98,0x83,0xff,0xf9,0x22,0xa2,
+  0x9d,0x06,0xb8,0x9f,0xb6,0x8e,0xc1,0x29,0xa8,0x57,0x3c,0xba,0x38,0x56,0xc1,0x80,
+  0x68,0x61,0xee,0xfc,0x17,0xf2,0x3f,0x87,0xb8,0xec,0xa7,0x74,0x84,0xeb,0x7f,0x3e,
+  0xbf,0x33,0x34,0xa2,0x3d,0x00,0x0b,0xe2,0xee,0xa4,0x3d,0xff,0x95,0xf6,0x3f,0xf8,
+  0xe1,0x54,0xf7,0x73,0x22,0xe8,0xb0,0x54,0xf3,0x4a,0x22,0xe8,0xdb,0xcc,0x19,0xa1,
+  0x99,0x6a,0xae,0xfc,0x17,0xfb,0x6c,0xe9,0x22,0x98,0x93,0x68,0xfb,0x46,0xe9,0x10,
+  0xec,0x12,0xe6,0x41,0x91,0x56,0xf8,0x2a,0x2a,0x82,0xc0,0x1d,0xb6,0xe7,0xbf,0xba,
+  0x67,0x9b,0x20,0xe7,0x0d,0xb5,0x97,0x2e,0x4a,0x16,0x7f,0xbb,0xea,0x24,0x9c,0xa7,
+  0x4b,0x10,0xff,0x5c,0x24,0xcb,0xf0,0xa7,0xb5,0xe2,0x3b,0xaa,0x95,0xff,0xba,0xd6,
+  0xd2,0xff,0xbc,0x47,0xd9,0xc6,0xf3,0xc4,0xaa,0x7d,0xe2,0xb0,0xfc,0x3a,0x3c,0x8d,
+  0xdf,0xd7,0xef,0x83,0xe3,0x86,0x14,0xff,0x48,0x97,0x39,0x3f,0xb0,0xf1,0x8a,0x92,
+  0xda,0xa4,0xb3,0xdd,0x7a,0x67,0xfd,0x47,0x2c,0x7e,0x9d,0x85,0x17,0x69,0xdd,0x8f,
+  0x3c,0x27,0x30,0xe3,0x83,0x8e,0x7d,0xad,0x08,0xd4,0x91,0xff,0x8a,0xb1,0xf7,0x0f,
+  0xc2,0x29,0xed,0x2d,0x68,0x1a,0x91,0x83,0xa5,0xbf,0x7d,0xa5,0x6b,0xd7,0xbc,0xb5,
+  0x25,0x49,0x17,0xf0,0xf1,0xb2,0xf7,0xaf,0x59,0x66,0x3d,0x1f,0xf9,0x9f,0xf4,0xee,
+  0x4c,0xd5,0x5d,0xeb,0xaf,0x3a,0xf1,0x50,0x97,0xfa,0x75,0xca,0x11,0x60,0x97,0x31,
+  0x5e,0xc8,0xe4,0x7f,0x52,0xf3,0x29,0x05,0xfa,0x2b,0x82,0xec,0x43,0xee,0x24,0x81,
+  0x76,0x97,0x5a,0xaa,0x1a,0x1b,0x5b,0x95,0xc8,0x36,0xfe,0x27,0x60,0xf1,0x1b,0xcc,
+  0xb8,0x53,0x3f,0x3e,0x26,0x0e,0x17,0xbe,0x48,0x9b,0xb5,0xad,0x31,0x51,0x25,0x09,
+  0x43,0xcf,0x53,0x93,0x2b,0xff,0x35,0xca,0xa2,0xdb,0x5d,0x7a,0x09,0xe6,0xbf,0x46,
+  0x94,0xd5,0x11,0xef,0x36,0x71,0x54,0xe1,0x5b,0xb3,0x58,0x8e,0xfc,0x57,0x6a,0xbf,
+  0x7f,0x03,0x73,0xec,0x33,0x30,0xd1,0x57,0xa5,0xed,0x49,0xce,0x58,0x0f,0xef,0xd3,
+  0x5e,0x94,0x46,0x3b,0xf2,0x5f,0xa9,0xf8,0x65,0xa0,0x97,0x7e,0x16,0xad,0x9a,0x94,
+  0x4d,0xf0,0x78,0x57,0xc5,0x90,0xab,0x29,0xd4,0xa3,0xf9,0x80,0x2d,0xad,0x64,0x2e,
+  0xfe,0xc7,0x08,0xdc,0x6c,0xfd,0xac,0xd1,0x7a,0xa4,0xe5,0xcc,0xd3,0x90,0x6a,0x39,
+  0x16,0xf6,0xc1,0xcc,0x58,0x66,0xfe,0x2b,0x68,0xf0,0x8d,0x5a,0x3d,0x04,0x8e,0xb0,
+  0xf9,0x91,0x0b,0xba,0x55,0x75,0x80,0x39,0x6a,0x59,0xa3,0x08,0x1d,0x55,0xdb,0xfe,
+  0x0b,0x3c,0x29,0xfd,0xcf,0x5e,0xf1,0xe7,0x6c,0xe0,0x4b,0x4e,0x15,0x9f,0x17,0x6f,
+  0xeb,0xd6,0x2b,0x16,0x5f,0x23,0x53,0x71,0x19,0xbc,0xab,0xd4,0x95,0xb1,0x89,0xd2,
+  0x2d,0xff,0x13,0x2b,0x66,0xf1,0x4b,0x69,0xd1,0x8b,0xcf,0xf1,0x68,0xce,0xfe,0x8b,
+  0xe7,0x22,0x97,0x7e,0x6b,0xcc,0xc0,0x8c,0x71,0x83,0x11,0x4a,0x8a,0x23,0xd3,0xec,
+  0xf8,0xe7,0x32,0x5b,0x96,0xde,0x0a,0xf1,0x9b,0xca,0x79,0xda,0xb0,0xcb,0x73,0x4e,
+  0x5c,0x47,0x51,0xf6,0x53,0xc2,0xf1,0x33,0x6d,0xce,0xe0,0x7f,0x18,0xfe,0x79,0x9b,
+  0x72,0xfd,0x8f,0x0f,0x46,0x3a,0x7c,0xdd,0xf2,0x07,0xad,0x77,0xa3,0x10,0x5a,0xcf,
+  0xcf,0xff,0x1c,0x24,0x9c,0xff,0xd1,0x98,0xe3,0x0a,0x74,0xbb,0x82,0x37,0x7b,0xda,
+  0x19,0xec,0x79,0x7e,0x66,0x6e,0xfe,0x87,0xe1,0x9f,0x83,0x0a,0xd7,0xff,0xdc,0x06,
+  0x7d,0xb4,0x66,0xa7,0x2b,0x4e,0xd6,0x65,0xf1,0x27,0x63,0x8e,0xfc,0xd7,0x87,0xc8,
+  0xff,0x6c,0x17,0xc3,0x10,0x8f,0x35,0xc7,0x6b,0x4d,0xd8,0x53,0x62,0xc3,0xcf,0x43,
+  0x8e,0xfc,0x17,0x1b,0x9d,0xce,0x9c,0xea,0x5e,0xb6,0x94,0x50,0x06,0x2f,0x9e,0x72,
+  0x28,0xc4,0x38,0xff,0x63,0xcf,0x7f,0xc1,0x44,0x8c,0x3f,0xe4,0x71,0x38,0x01,0x88,
+  0xaf,0x66,0x04,0x94,0x17,0xed,0x78,0x3b,0x53,0xff,0x23,0xf1,0x97,0x54,0x68,0x2d,
+  0xf3,0xcf,0x44,0xef,0x1c,0x23,0x4d,0x24,0x9b,0xff,0x31,0xd7,0x03,0xe2,0x9f,0x07,
+  0x31,0xe9,0x39,0x2b,0x42,0x69,0x14,0x5c,0xe0,0x46,0x9a,0x91,0xbb,0x9d,0xbc,0xfc,
+  0xcf,0x53,0x5c,0xff,0x1c,0x2a,0x85,0x2d,0xb4,0x32,0xd9,0xb3,0xb8,0xb0,0x64,0xe9,
+  0x26,0x43,0xf6,0x73,0x9a,0xe6,0xd4,0xff,0xfc,0xca,0xd0,0xff,0x44,0x60,0x08,0x16,
+  0xaf,0xf5,0x06,0x5b,0x4b,0xb4,0xe7,0x29,0xe7,0x7f,0x8e,0xd3,0x0f,0x0d,0xc3,0xc9,
+  0xff,0x5c,0x36,0xf4,0xcf,0x43,0xda,0x28,0x2c,0x19,0x58,0x35,0xe6,0xfe,0x39,0x4c,
+  0x2a,0xcd,0x53,0xe8,0x7f,0x78,0xfe,0x51,0x11,0x7d,0x32,0x43,0x0b,0xaa,0xa7,0xb7,
+  0xf5,0xbd,0xf6,0xd7,0xd9,0x95,0xad,0x71,0xf1,0x38,0x3c,0x4f,0x83,0xc9,0xdc,0xfa,
+  0xe7,0xf6,0x4f,0x2b,0xca,0xbd,0xb0,0x40,0x93,0xef,0x64,0xc3,0x44,0xd8,0x23,0xae,
+  0x87,0x53,0x64,0x13,0xdb,0x6a,0xf9,0x33,0xf5,0xcf,0x4f,0xd1,0xaf,0x27,0x8b,0x4e,
+  0x90,0x5e,0xd4,0x7b,0x87,0x8b,0x18,0x10,0x42,0xe0,0xc7,0xf9,0x9f,0xe9,0x9b,0x72,
+  0xeb,0x9f,0xd7,0xe1,0xfe,0x2b,0xa2,0x46,0x92,0x81,0xf0,0xe7,0x38,0xb1,0x6f,0xf2,
+  0x8d,0x9d,0x86,0x10,0xe8,0x15,0xc9,0xfc,0x5e,0x4c,0xfd,0x73,0xf1,0xef,0xc5,0x83,
+  0xf2,0xf1,0x58,0xcb,0x43,0xc5,0x0c,0xff,0x28,0x27,0x4d,0x20,0x74,0x8c,0x6d,0x16,
+  0xb9,0xfe,0xd9,0x9a,0x4f,0xcc,0x7f,0x2d,0x6d,0x66,0xf1,0x57,0x50,0xd9,0x9f,0xa5,
+  0x99,0x94,0x18,0xdb,0xf0,0xbb,0x53,0x08,0x21,0xa7,0xfe,0x47,0xc5,0xfa,0xaf,0x19,
+  0xc3,0x6c,0xe3,0x3f,0x1b,0x89,0x02,0x09,0xde,0x16,0x1a,0x58,0x98,0x9b,0x91,0x9b,
+  0xff,0x81,0x83,0x2a,0x8b,0xbf,0x4a,0x64,0x8e,0xc9,0x36,0xec,0x82,0xcd,0x19,0xf5,
+  0x5c,0x39,0xf4,0x3f,0x71,0x62,0x05,0x6e,0x53,0x11,0x9d,0xab,0xfe,0xcb,0xe2,0x7f,
+  0xa2,0x6c,0x99,0xa5,0x84,0xd0,0x5d,0xb1,0x0e,0x0b,0x11,0x65,0xd6,0x7f,0x71,0xfd,
+  0x8f,0x31,0xa8,0x54,0x20,0x8e,0x88,0x2a,0xc5,0xfc,0x8b,0x9d,0xef,0x3a,0xee,0xd0,
+  0xff,0x70,0x3e,0x67,0x4c,0x7c,0x15,0x17,0x12,0xcf,0x7f,0x49,0x17,0x84,0xe6,0xe5,
+  0xab,0x0c,0x7e,0x63,0x36,0xe2,0x01,0x1b,0xff,0x23,0x0c,0xb3,0x6d,0x69,0x09,0x03,
+  0x39,0xd3,0xf6,0xc3,0x99,0x02,0xa4,0x4d,0x3a,0x39,0x42,0x68,0xe7,0xf5,0x62,0x97,
+  0x51,0x1a,0x1d,0xb5,0xe1,0x1f,0xcc,0x7f,0x2d,0x36,0xf0,0x8f,0xca,0x81,0x90,0xe7,
+  0xde,0x08,0x37,0x10,0xf6,0xe4,0xa8,0xff,0x62,0xf8,0x47,0x5a,0x68,0x54,0x6f,0x75,
+  0xc1,0x0e,0x21,0xb0,0x7c,0xa6,0x42,0x0a,0x14,0x36,0xcc,0x36,0x77,0x6e,0xfe,0x07,
+  0xf1,0x4f,0x29,0xd7,0xff,0xec,0xd2,0x0e,0x6a,0x48,0xa3,0xb9,0x72,0xd4,0xd3,0x65,
+  0xe1,0x9f,0x92,0x32,0xf2,0xe3,0xae,0xb7,0xa1,0x19,0xd3,0x58,0xd5,0xce,0x0c,0x97,
+  0x83,0xff,0xb1,0xf2,0x5f,0xdb,0xc5,0xb9,0xdc,0xf8,0x27,0x25,0x35,0x2d,0xb6,0xfb,
+  0xab,0x1c,0xf9,0x2f,0x13,0x6f,0x9f,0x81,0x11,0xad,0x8e,0x45,0xf4,0xf4,0xb4,0xe7,
+  0xd1,0xff,0x3c,0x8b,0xf8,0xe7,0x1d,0xf6,0xac,0xfb,0xe0,0x2a,0x5a,0xc2,0x81,0x90,
+  0x64,0x21,0xa2,0x4c,0xfd,0x0f,0xe2,0x1f,0x63,0xd3,0x3d,0x48,0x1f,0x07,0xb5,0xbf,
+  0x35,0x18,0xb2,0x47,0x70,0x53,0xff,0x63,0xcf,0x7f,0x3d,0xc5,0xf1,0x4f,0xe1,0x2b,
+  0x0c,0xe9,0xcf,0x19,0x70,0x7d,0x93,0x03,0x83,0xe2,0x01,0xb7,0x43,0xff,0x63,0x3e,
+  0xdf,0xd0,0xff,0xdc,0x98,0x5c,0xb5,0xa1,0xf5,0xa4,0xf2,0x16,0x5d,0x38,0xe2,0xbd,
+  0x1b,0x69,0x9f,0x8e,0x6b,0x47,0xbc,0x76,0xfd,0x8f,0xb9,0xdc,0x38,0xfe,0xb9,0x90,
+  0x22,0xed,0xd1,0xb1,0x0c,0x79,0x9f,0xee,0x64,0x1e,0x46,0x6a,0x3e,0xe9,0xe0,0x7f,
+  0xd2,0xfc,0x3f,0xd7,0x3f,0x73,0xd9,0x4f,0x23,0x4c,0xd2,0xba,0xf3,0x25,0xe3,0xad,
+  0xcd,0x58,0xf6,0xe5,0xd4,0xff,0x38,0xf8,0x9f,0x33,0x49,0xf6,0x92,0xff,0xb3,0x90,
+  0xaa,0x07,0xe0,0x33,0x23,0xf2,0x7a,0xf1,0x2b,0xd0,0x1b,0x5f,0x87,0xfa,0x1f,0xeb,
+  0xfd,0x9d,0xf9,0xaf,0xa7,0xe5,0x79,0xba,0x6b,0x8c,0xac,0xd6,0x9e,0x83,0xaa,0x01,
+  0x76,0xdb,0xad,0x14,0x6f,0xab,0x30,0xee,0x67,0x3f,0x65,0xea,0x7f,0xf6,0xa2,0xb7,
+  0x69,0xf2,0xf5,0x43,0xaf,0x16,0x48,0xb6,0x05,0xc9,0x4a,0xa1,0x17,0x2b,0xa4,0x6c,
+  0xf3,0xe9,0xcc,0x7f,0x7d,0xc8,0xc2,0x4a,0x49,0xac,0xf3,0x76,0x38,0xac,0x54,0x8d,
+  0x95,0x8c,0x89,0xeb,0x14,0xdc,0x81,0xca,0x6c,0xbc,0x05,0x13,0x42,0x23,0x06,0x32,
+  0x67,0xfe,0xeb,0x6d,0x64,0xe3,0xf7,0xcd,0x88,0x31,0x7c,0xd8,0x30,0xc8,0xbc,0xb7,
+  0x7d,0x07,0x6a,0x14,0x82,0x39,0xf9,0x9f,0xcb,0x50,0xdf,0xcf,0xbe,0xc7,0x20,0xf3,
+  0xde,0x4b,0xf4,0x82,0xb1,0xaa,0x26,0xb8,0x87,0x05,0x3e,0x4b,0xff,0x53,0x6c,0xe7,
+  0x7f,0x30,0xff,0xf5,0x28,0x65,0xf1,0xb7,0x89,0x3c,0xae,0xbe,0xcb,0xf5,0x3f,0x21,
+  0xac,0xf0,0x9a,0x9b,0xd2,0xff,0x64,0xd5,0x7f,0x09,0x0c,0xff,0x74,0xf9,0xb0,0x5e,
+  0xcc,0xc7,0x65,0x63,0xae,0xb8,0x0b,0x11,0xd1,0x1d,0x53,0xe8,0x7f,0x1e,0x54,0x63,
+  0x7a,0x4f,0x3c,0x44,0x71,0x36,0x8e,0xb0,0xd9,0x28,0xde,0xd8,0x5b,0x57,0xfd,0x4a,
+  0x91,0x03,0x0f,0x58,0xd3,0x5f,0xbc,0x8e,0xe1,0x01,0x5e,0xc4,0xad,0xb6,0x1d,0x86,
+  0x96,0x81,0x92,0xf5,0x62,0x20,0x36,0xe1,0xf9,0xcc,0xd1,0x59,0x0c,0x21,0xe3,0x8e,
+  0x1b,0x2b,0x94,0x6d,0xf5,0x5f,0xd7,0x5e,0x82,0x7f,0xc5,0xfc,0x57,0x7b,0xe7,0x58,
+  0xf7,0x5b,0xe4,0x7f,0x27,0x8a,0x51,0xc8,0xc1,0x0b,0x09,0xd9,0x78,0xf7,0x4c,0xa6,
+  0xf4,0xcf,0x0e,0xfd,0xcf,0x84,0xb1,0x48,0xd8,0xee,0x9e,0x36,0x25,0xff,0x71,0x4c,
+  0x6c,0x8a,0x4d,0xd2,0xeb,0x38,0xa2,0xd6,0x26,0x81,0x21,0xf6,0x4c,0xfc,0x73,0x38,
+  0x52,0x9b,0xec,0xe9,0x13,0x7f,0xc6,0x06,0xde,0x98,0x94,0x2f,0x91,0x16,0xdc,0x96,
+  0x26,0x57,0xf4,0x91,0x61,0x7a,0x50,0xf6,0x1d,0x71,0x65,0xe2,0x1f,0x1c,0x94,0xc8,
+  0x47,0x27,0x32,0x3c,0xb9,0x10,0xf5,0x18,0xc0,0x11,0xd1,0xe0,0x74,0xf6,0xe9,0x25,
+  0x8a,0x32,0xf1,0x8f,0x0d,0x4f,0xd6,0xe8,0x10,0x0f,0xed,0x61,0xfe,0xbf,0xa6,0xbb,
+  0x07,0xfd,0xcf,0x42,0x94,0x76,0x64,0xe2,0x9f,0x54,0xfe,0x74,0x1d,0xd7,0x83,0x79,
+  0x90,0x9f,0xf9,0x9d,0x81,0x58,0x86,0xe5,0xf1,0x30,0x4a,0x83,0xa6,0x0d,0xe5,0xd0,
+  0xff,0x90,0x4b,0xbc,0xfa,0xef,0x67,0x63,0xe2,0x77,0xe0,0x3d,0xbd,0x3e,0xc9,0xa6,
+  0xe5,0x3c,0x5c,0x61,0x0b,0xa3,0x04,0x81,0xa2,0xf9,0x7c,0x23,0xff,0x95,0x46,0x3b,
+  0x03,0xec,0xf9,0x83,0xbc,0xac,0x7e,0x15,0x7b,0x3e,0xfa,0x1f,0x3d,0x9b,0xff,0x11,
+  0x6c,0x68,0x87,0x45,0xe7,0x4b,0x70,0x90,0xd6,0x50,0xf7,0x77,0xd9,0xfb,0x1f,0xca,
+  0xcd,0xff,0x54,0x5b,0xde,0x26,0xe9,0xba,0x01,0x8d,0xb6,0x6a,0x84,0xc1,0x48,0xa5,
+  0x06,0x74,0x57,0x56,0xfe,0x2b,0x66,0x65,0x7f,0x16,0x20,0x1f,0x72,0x1a,0x0e,0x3d,
+  0x34,0x6f,0x64,0xc5,0x06,0xf2,0x2a,0xec,0xef,0xe0,0x42,0xe8,0xcc,0xfc,0x17,0x4f,
+  0x72,0x0d,0xc2,0x87,0xca,0x77,0x46,0x4a,0xea,0xaa,0x18,0xec,0xd9,0x1d,0x1c,0xf5,
+  0x56,0x8b,0x83,0xda,0x39,0xf6,0xfe,0x85,0x99,0xf8,0x67,0x92,0xe1,0x67,0x6f,0x7c,
+  0x1a,0xc7,0xcf,0x03,0x5f,0x67,0x13,0x1b,0x66,0xd3,0xd2,0xc5,0x10,0x23,0x1b,0xaf,
+  0xd2,0x9c,0x1b,0xff,0xa4,0xe6,0xa7,0x49,0x2f,0xd9,0xff,0xfc,0x71,0xfa,0x3c,0xb0,
+  0xf8,0x1e,0x53,0xdf,0xc4,0xd4,0x0f,0x4e,0x54,0xae,0xfa,0xaf,0x94,0xb7,0x41,0x19,
+  0xa1,0x7a,0x2f,0xf9,0x9a,0xb6,0x62,0x3d,0xe1,0xfb,0xc7,0xcc,0xfc,0x17,0xf2,0x3f,
+  0x73,0x70,0xbc,0x5f,0xe1,0x44,0x90,0xeb,0xdb,0x85,0xa7,0xe9,0x26,0x3a,0x2f,0xec,
+  0x5e,0x4b,0x3e,0x82,0x8d,0x0c,0x1a,0xb9,0x73,0xd6,0x7f,0xb1,0xf9,0x94,0xd0,0xe8,
+  0xc6,0x89,0x8d,0x14,0x04,0x54,0x8c,0x77,0x45,0x9d,0x6a,0x6d,0x66,0xfe,0x6b,0x37,
+  0xfb,0xa3,0x34,0x20,0xda,0x59,0xcb,0x81,0x50,0x09,0xc2,0x9e,0x23,0xd0,0x18,0x43,
+  0xfc,0x43,0xcf,0xd2,0xe6,0xcc,0xfc,0x97,0x3d,0xfa,0x48,0xcd,0x42,0x4a,0xf6,0xbc,
+  0x53,0xc2,0x2b,0x02,0x9b,0x9f,0xdc,0xf9,0x2f,0x33,0xba,0x85,0x8b,0x1e,0xab,0x1f,
+  0x56,0x2e,0x40,0x5d,0xd8,0x8a,0x77,0x25,0x51,0x92,0xb3,0xfe,0x0b,0xa3,0x6d,0x20,
+  0x2c,0x6f,0xf7,0x0d,0xcb,0x07,0xb5,0x9a,0xb0,0x15,0x7f,0xb3,0xf8,0x1f,0x7b,0x74,
+  0x6e,0xe3,0x78,0xe9,0xa0,0xfc,0x37,0xcb,0x7e,0x30,0x94,0xba,0x3f,0x8b,0xff,0x31,
+  0x82,0x7e,0x21,0x8f,0xfe,0x4b,0xfd,0xa5,0x74,0x20,0xf6,0x14,0xcc,0xd3,0xd8,0x7e,
+  0x76,0x00,0x16,0xfa,0x03,0xd9,0xfc,0xcf,0x88,0x3d,0xda,0xfe,0x8f,0xc8,0xd2,0x18,
+  0xc5,0xb2,0xa3,0xad,0x3a,0x5e,0x51,0xb9,0x22,0xf7,0x78,0xa6,0xfe,0xd9,0x1c,0x6f,
+  0x0b,0xea,0x5b,0x18,0x22,0x12,0x3e,0xc2,0x2b,0xaf,0xee,0xba,0x6c,0x64,0xc4,0x6c,
+  0xf8,0xc7,0xc6,0xff,0x78,0xf0,0x7e,0xd7,0x2b,0x9d,0xe7,0x95,0x7f,0x83,0x7d,0xec,
+  0x4a,0xeb,0x30,0x1c,0xf5,0xd7,0x2d,0x2b,0xce,0xd4,0x3f,0x8f,0xa4,0xf4,0x3f,0x1c,
+  0xed,0xc8,0x5d,0x21,0xac,0x08,0x63,0xdb,0x52,0x9d,0xe8,0xb1,0x11,0xd5,0x27,0xcb,
+  0x59,0xf9,0x2f,0x03,0xe4,0x2c,0x93,0x50,0x08,0x74,0x8d,0x42,0x7e,0x01,0x3f,0x87,
+  0x39,0x61,0xb6,0xcc,0x86,0x37,0xef,0xf5,0x07,0xda,0x8a,0x94,0xc2,0x23,0x56,0xfd,
+  0x08,0xe2,0x1f,0x07,0x7a,0xac,0x88,0x86,0xd0,0xf8,0x53,0xcd,0x7d,0x82,0x5d,0xd9,
+  0xc1,0x66,0x4c,0xce,0x85,0x7f,0xbc,0x28,0xfb,0x41,0xa3,0xd0,0x18,0x78,0xc3,0x52,
+  0x43,0xf8,0x0d,0xcf,0x6a,0x7f,0x9f,0x13,0xff,0x98,0xf9,0xaf,0xad,0xc6,0xfd,0x8d,
+  0xa9,0x0a,0x32,0x23,0x11,0x96,0x47,0xff,0x83,0x78,0x9b,0x27,0xc2,0x86,0xa0,0x51,
+  0x4d,0x29,0x82,0xea,0xf2,0xe8,0x9f,0x91,0xf6,0x39,0x04,0xf3,0xa3,0xf2,0x4e,0xf0,
+  0xcb,0xf7,0x19,0x65,0xef,0x23,0x50,0xc3,0x8c,0x15,0x59,0xf8,0xc7,0x8e,0x76,0x8a,
+  0x82,0x3e,0x0f,0x44,0x61,0x2d,0xb8,0xa1,0x70,0x50,0xc0,0xc2,0x81,0x2c,0xfc,0x63,
+  0xff,0x7e,0xb5,0x4f,0x6f,0x20,0x25,0xf2,0x56,0x98,0x0f,0x2b,0xda,0x7d,0xa7,0xa0,
+  0xb7,0xb2,0x32,0x1b,0xff,0xa4,0x40,0x8e,0x81,0x76,0x8a,0x51,0xff,0xfc,0xcf,0xf4,
+  0x86,0x98,0xb7,0x4d,0x3c,0x4d,0xff,0x25,0xb6,0xf7,0x1d,0xc4,0x3f,0x76,0xfd,0xcf,
+  0x74,0xbb,0x3f,0x59,0x8a,0x32,0x57,0x69,0x02,0x33,0xd4,0x51,0x71,0x54,0x7b,0xb7,
+  0xbd,0xf9,0x84,0xdb,0x9e,0xff,0x02,0x29,0x15,0xbf,0x2e,0x88,0x67,0x19,0xec,0xb9,
+  0x31,0xe6,0xb9,0x20,0xce,0xd6,0xf4,0xe8,0x5d,0x61,0xef,0x88,0x38,0x29,0x4f,0xea,
+  0xf5,0x6f,0x3a,0xf1,0x8f,0xf2,0x18,0x7b,0x8d,0x6f,0x63,0xfd,0xda,0x69,0x84,0x31,
+  0xaa,0xbc,0xa1,0xb4,0xa4,0xfb,0xd7,0x3b,0x82,0x61,0xf7,0xb7,0xf0,0x4a,0x5f,0xe5,
+  0x48,0x16,0xfe,0xf9,0x09,0x31,0xf4,0x3f,0x38,0x5e,0xda,0xb6,0xde,0x37,0x8b,0x6e,
+  0xf4,0x7f,0x7d,0xc8,0x1d,0x26,0xa7,0xf6,0xf6,0xf2,0x54,0x7e,0x96,0xfe,0xd9,0x6f,
+  0xcd,0xa7,0xe0,0x0f,0xb2,0x8d,0xc6,0xc3,0xba,0x8a,0x0a,0x87,0xb3,0x3c,0x43,0x94,
+  0x85,0x7f,0xde,0x95,0xd2,0xf1,0x85,0x56,0xb0,0xfd,0xbb,0x44,0x3b,0x1a,0xf5,0x55,
+  0xfb,0xbf,0x78,0xa5,0x6c,0x52,0xea,0xc5,0x8d,0xa4,0x13,0xff,0xbc,0xcb,0xb7,0xe1,
+  0x22,0x87,0x85,0x8a,0x37,0xee,0x1e,0x65,0x1b,0x2b,0x76,0xff,0x33,0x9d,0xa6,0x2b,
+  0x16,0x9c,0xf8,0xe7,0x7d,0x6b,0x77,0x2f,0xb5,0xc8,0xf3,0x0f,0x7e,0xf1,0x92,0x7c,
+  0xb9,0x3b,0x95,0xff,0xda,0xca,0x10,0x91,0x27,0x03,0xff,0xc8,0x69,0x3d,0x0f,0x09,
+  0xa8,0x72,0x1f,0x19,0x15,0x0e,0x22,0xe3,0x81,0x57,0x7e,0x6a,0x08,0xa1,0x73,0xf2,
+  0x3f,0x3c,0xde,0x45,0x3f,0x17,0x2f,0x1d,0x85,0x3e,0xf5,0xa6,0x81,0x9e,0x3e,0x7e,
+  0x7f,0x8d,0x2e,0xe7,0xd4,0x3f,0xd7,0x91,0x41,0x2c,0x7b,0x07,0xac,0x4f,0xe9,0xda,
+  0x1b,0x8c,0x8d,0xe0,0x8c,0x75,0x3c,0xae,0xaa,0x47,0x36,0x67,0xd5,0xbf,0x23,0xff,
+  0x63,0xe8,0x4f,0x9a,0x67,0x15,0xef,0x6b,0x7d,0xaf,0xeb,0x60,0x51,0xc3,0x51,0xce,
+  0x98,0xbd,0x0f,0x87,0x13,0x9e,0x4c,0xfc,0x33,0xb9,0x98,0x8d,0x77,0x6f,0x2b,0x8f,
+  0x5f,0x15,0x25,0x0f,0x8a,0xa3,0xc9,0xcb,0xea,0x73,0x98,0xc8,0x18,0xc5,0xfa,0x77,
+  0x94,0x82,0x3b,0xf1,0xcf,0x08,0x03,0x39,0x25,0xe3,0x5f,0xbd,0x02,0x2f,0xd1,0x7a,
+  0x8d,0xcd,0xc6,0x6f,0xd8,0x26,0x63,0x61,0x98,0xe1,0xe7,0xd9,0xcc,0xb8,0x31,0xe9,
+  0x19,0x71,0xe8,0x9f,0x47,0xe1,0x01,0xae,0xee,0x2e,0x1d,0xe5,0xdd,0x78,0x18,0x30,
+  0x1e,0x35,0xcb,0xd2,0x79,0xc5,0x37,0x0a,0xed,0x54,0x9b,0xff,0x19,0x05,0x3f,0x43,
+  0x8f,0x2e,0x73,0xf7,0xcd,0xd6,0xc3,0x00,0x1a,0x1a,0x5f,0x18,0x9d,0x10,0xa0,0x19,
+  0xfa,0x67,0x0f,0x96,0xbd,0xa0,0xda,0x79,0x50,0xeb,0xec,0x37,0x0c,0xda,0xc3,0x02,
+  0xbf,0xfd,0xf9,0x41,0x1b,0xfe,0x39,0xab,0x8d,0x68,0xd7,0x23,0x08,0x39,0x4b,0x5e,
+  0xa4,0x0f,0x45,0xf1,0x7b,0x21,0x2f,0xc2,0xbe,0x64,0x20,0xee,0xae,0x65,0x46,0x73,
+  0xcc,0x13,0x73,0x3b,0xf5,0xcf,0x17,0x85,0x96,0x21,0x06,0x7a,0xaf,0xe0,0xfc,0x3c,
+  0xb4,0xca,0x30,0xf8,0x0a,0x41,0xbc,0xd7,0xb2,0x6b,0x41,0x32,0x83,0xff,0x49,0x18,
+  0x4d,0x84,0xf0,0xb1,0x4d,0xd1,0xaf,0xec,0x13,0x03,0xf8,0xd8,0x04,0xd7,0x9f,0xbf,
+  0xa8,0x34,0x23,0x3f,0x10,0xb4,0xe1,0x9f,0xf9,0x5a,0x27,0x3c,0x89,0xeb,0xe1,0xbd,
+  0x76,0xfe,0xb6,0x97,0x48,0x40,0xe8,0xe9,0xae,0x1d,0x2a,0xde,0x4f,0xde,0x54,0x5f,
+  0x6f,0xaf,0xdd,0x56,0xbc,0x27,0x52,0xe7,0xc0,0x3f,0x51,0xc3,0xc9,0x18,0xfa,0x43,
+  0x57,0x53,0xc8,0x43,0x7b,0xa4,0x80,0x2e,0x3f,0x4d,0x46,0x69,0x27,0xd4,0x26,0xe5,
+  0x9d,0x64,0xb1,0x03,0xff,0x7c,0x2f,0x3e,0xcf,0xc0,0x3f,0x9b,0xba,0x8a,0x93,0xf2,
+  0x86,0xc2,0x66,0x75,0x13,0xfd,0x1f,0xc3,0x45,0x98,0x18,0xfa,0x13,0xba,0x20,0x59,
+  0xb4,0x96,0x54,0xd8,0xf0,0x4f,0x80,0xfc,0x4a,0x8f,0x23,0xfe,0xc1,0xa7,0xcd,0xd2,
+  0x43,0xf1,0x9e,0x62,0xd2,0x09,0x4d,0x97,0x50,0xff,0x0c,0xcf,0x43,0xd3,0x49,0x36,
+  0x3f,0xa5,0x0e,0xfc,0xf3,0x1e,0xce,0x46,0xdc,0xd8,0x1d,0x60,0xb6,0x74,0x54,0xe2,
+  0x88,0x28,0x95,0x3f,0xd5,0x9d,0xfa,0xe7,0x82,0x51,0x92,0x50,0xf7,0xe9,0x01,0xa4,
+  0xdd,0x50,0x28,0xe5,0xe9,0x15,0x3d,0xe4,0x75,0x08,0xb2,0xbf,0x48,0x15,0xd6,0xab,
+  0xd6,0xa1,0x3e,0xcd,0x89,0x7f,0x22,0x32,0xb6,0x45,0xba,0x6a,0x96,0x74,0x00,0x2a,
+  0x8f,0xc8,0x77,0xb6,0xde,0x0a,0x48,0xfb,0xc8,0x58,0x11,0xcf,0x8d,0x4c,0xfd,0xf3,
+  0x46,0xba,0x03,0x49,0x9e,0xaf,0xc0,0x73,0xfa,0xbc,0xa4,0xbc,0x38,0xd4,0x0c,0x9b,
+  0x22,0x55,0x49,0x17,0x5e,0xd9,0x44,0x2b,0xc3,0xf2,0x5a,0x07,0xfe,0xb9,0x49,0xeb,
+  0xdc,0xa6,0x86,0xe5,0xe0,0xf2,0x65,0xda,0x3e,0xa8,0x19,0x60,0xcb,0x66,0x6d,0x5b,
+  0x0f,0xec,0x8c,0xb1,0x15,0x38,0xaa,0x75,0x12,0x75,0x8c,0xad,0x37,0x27,0xfe,0x39,
+  0x0e,0x3e,0x2c,0x72,0xff,0x6b,0xb8,0xa2,0x35,0x46,0xbf,0x13,0x13,0x6f,0x80,0x63,
+  0x50,0xdf,0x57,0xcb,0x5e,0x9b,0x39,0xfe,0xfa,0xdd,0x81,0x64,0x6e,0xfc,0xc3,0x02,
+  0x93,0xdc,0xc0,0xc3,0x90,0x8f,0x21,0x04,0x32,0xdf,0xe8,0xc7,0xf2,0x2c,0xc9,0xc2,
+  0x3f,0xaf,0xb1,0xa0,0x26,0x3f,0x28,0x56,0xcb,0x47,0x19,0x2c,0xe4,0x65,0xef,0x45,
+  0xd3,0x51,0xd6,0x2b,0xbe,0x49,0x8f,0xb2,0x0f,0x07,0xa2,0x22,0xb1,0xe3,0x1f,0xb2,
+  0x59,0xf3,0xb5,0xcb,0xb3,0x48,0x35,0xe9,0x00,0xdf,0x7a,0xf9,0x31,0xf2,0x29,0xd8,
+  0xac,0xed,0xd4,0xe4,0x6d,0xe4,0xcd,0xc8,0x66,0xd8,0xa9,0xf9,0x15,0x97,0x6a,0xc3,
+  0x3f,0x12,0x74,0x68,0xbb,0x56,0x2f,0xdf,0x46,0x0a,0x84,0xcd,0xda,0x8f,0xc7,0xd8,
+  0x6d,0x73,0x85,0x27,0x64,0x1f,0xde,0x3f,0xec,0xe9,0x08,0xfb,0x57,0xbb,0xb0,0xb0,
+  0xdd,0x5c,0x0f,0x88,0x7f,0x50,0xf6,0xec,0x8a,0xba,0x24,0x61,0x33,0xa8,0xcb,0xe5,
+  0xd2,0x48,0x21,0xd9,0x81,0xdf,0x23,0xf2,0x21,0x1d,0xe0,0x47,0xbc,0x44,0x6c,0xf8,
+  0x47,0x83,0x84,0xda,0xc0,0x16,0x72,0x95,0xca,0x3e,0x84,0xcf,0xc8,0x81,0x88,0x5b,
+  0x65,0x5f,0x51,0x1d,0x78,0xe8,0x74,0x9d,0xfd,0x79,0x16,0x23,0xfe,0x29,0x49,0xe3,
+  0x9f,0xe2,0xf3,0xb1,0xc9,0x40,0xcb,0xf2,0xe2,0x57,0x1e,0x3f,0x1f,0xfb,0xd8,0xff,
+  0xdc,0x72,0xef,0x43,0xcf,0x7f,0x2b,0xf6,0xaf,0x58,0xf6,0xce,0x80,0x4d,0xec,0x82,
+  0x7f,0x11,0xfb,0xa9,0xd3,0x59,0xff,0xf5,0xb6,0xff,0x9b,0x9a,0x67,0xdb,0xb4,0x6a,
+  0x38,0x0a,0x75,0x21,0xde,0x1f,0xe9,0xa8,0xe4,0xd3,0x4a,0xb6,0xa1,0xfe,0xd9,0xc8,
+  0x18,0x3a,0xf0,0x0f,0xed,0x0e,0xef,0x93,0xfd,0xe0,0x52,0x69,0x37,0xf8,0x14,0xff,
+  0x46,0x36,0x1b,0xdd,0xaa,0x0f,0x5c,0xc4,0xa5,0x2a,0x98,0xff,0x92,0x75,0x07,0xfe,
+  0x39,0xaf,0xfe,0x48,0xae,0x0c,0xc9,0xed,0xe4,0x7a,0x75,0xa3,0xbf,0x72,0xb9,0x7c,
+  0xf3,0x6f,0xcb,0x62,0x1b,0xe5,0xaf,0x2e,0x77,0xdd,0x5c,0x5a,0x46,0x37,0xca,0x0b,
+  0xd8,0x4f,0x11,0xbb,0xfe,0x67,0xbf,0xb0,0x11,0x04,0x4d,0x6e,0x2f,0xfd,0x16,0xd9,
+  0xa4,0x54,0x2e,0x2b,0x5a,0xef,0x2b,0x87,0x8d,0xe4,0xf1,0xf6,0x9a,0x76,0x52,0x06,
+  0xf7,0x4b,0xde,0x56,0xff,0x90,0x1d,0xff,0x14,0x2c,0x83,0xb7,0x69,0x29,0xbe,0xa4,
+  0xc4,0xd5,0xaa,0xf8,0xfe,0xe4,0xa8,0x50,0xa7,0xd5,0x72,0x43,0x9a,0xbd,0xde,0xe3,
+  0xc4,0x3f,0x3f,0xd6,0x2e,0xc4,0x9a,0xd7,0xb0,0x68,0xce,0x0c,0x78,0x36,0x84,0xf9,
+  0x32,0xd5,0x94,0x45,0x69,0x17,0x5c,0xcd,0x6d,0x4e,0xfc,0x03,0x31,0x48,0x68,0x75,
+  0xf2,0xca,0x8e,0x56,0xb5,0x22,0xc1,0xa6,0x7d,0x10,0xf1,0x4f,0x4a,0x7f,0x85,0x8d,
+  0x80,0x18,0xfe,0xd1,0x33,0xf0,0x0f,0x43,0x3b,0x51,0xae,0x76,0xbe,0x8f,0xfa,0x68,
+  0xf7,0x8f,0x22,0xfe,0xae,0xfb,0xd4,0x80,0xa1,0x7f,0x3e,0x04,0x6a,0x2c,0xa3,0xfe,
+  0xeb,0x0b,0xf0,0x30,0xdd,0x9d,0x94,0x83,0x91,0x07,0xa0,0x33,0x1a,0xfb,0x40,0xc6,
+  0xfe,0x3f,0x9d,0x34,0x80,0x57,0xbc,0xd0,0xab,0xef,0x1e,0xc9,0xc0,0x3f,0x57,0xc3,
+  0x23,0xda,0xbc,0x21,0xb6,0x6d,0x79,0x14,0xbf,0xd6,0x21,0x58,0x4f,0x14,0xd8,0x88,
+  0x40,0x8b,0x19,0xea,0xd3,0xdd,0xf3,0x22,0x19,0xf8,0xa7,0x99,0xc1,0x8a,0x25,0xb1,
+  0x40,0x9b,0xf8,0x2c,0x79,0x99,0xd6,0xc7,0x02,0xb2,0xd8,0x0c,0x28,0x7b,0x0e,0xac,
+  0x65,0xf1,0xc5,0xec,0xff,0x63,0xc3,0x3f,0xbb,0xe1,0x1d,0x89,0xed,0x47,0xa8,0x7b,
+  0x9d,0xa1,0x76,0xa6,0x90,0x24,0xe3,0x12,0xca,0xf0,0xdc,0x49,0xb6,0x43,0x61,0x3f,
+  0x39,0xf0,0x4f,0xc1,0x47,0x30,0x11,0xfd,0xdb,0xb0,0x77,0xdc,0x3d,0x17,0x69,0x9f,
+  0x70,0xc9,0xc1,0xd6,0x66,0xed,0x5d,0x1a,0x5f,0x53,0x62,0xec,0xe8,0x5b,0x30,0x90,
+  0xd9,0xf9,0x9f,0x28,0xdb,0x3f,0x2e,0x6c,0x73,0xdf,0x25,0x96,0x22,0x9e,0x59,0xcd,
+  0x1c,0x4b,0x29,0xdd,0x18,0x53,0xfd,0xf8,0xfe,0xf0,0x34,0x2c,0x00,0x79,0xbd,0x43,
+  0xff,0xbc,0x0d,0x9e,0x56,0x2a,0xf5,0x9e,0x73,0xe4,0x55,0x7a,0xa0,0x62,0x41,0xc7,
+  0xf7,0x35,0xd2,0x04,0x3f,0x53,0x3f,0xa5,0xb9,0x93,0xe4,0x56,0x78,0x04,0xe6,0x87,
+  0xe4,0x0d,0x0e,0xfc,0xa3,0xcb,0x87,0xba,0x54,0xf4,0xff,0x5d,0xda,0x61,0x1a,0xe8,
+  0x90,0x81,0x2c,0x65,0xa8,0xa5,0x5a,0x91,0x63,0x3e,0x4d,0x3b,0x04,0x01,0x45,0x76,
+  0xe2,0x9f,0x9f,0xd1,0x0b,0xe1,0xba,0x11,0x77,0xdc,0x7d,0x16,0xfa,0x68,0xf3,0x91,
+  0xda,0xb8,0xb8,0xe0,0xc8,0xbb,0xb0,0x7f,0xa8,0x24,0xea,0xbe,0x03,0xa1,0xf2,0x40,
+  0x13,0x38,0xf0,0xcf,0x3a,0xb8,0xa0,0xa2,0xba,0x72,0x86,0x1f,0x36,0x68,0xcd,0x43,
+  0xde,0xfd,0xee,0x18,0xe2,0x67,0xea,0xdd,0x26,0xee,0x40,0x69,0x62,0xd4,0xdb,0xe5,
+  0xe0,0x7f,0xae,0x2c,0xbd,0xa0,0x55,0xd1,0x55,0x3a,0x9b,0xf6,0xcb,0x9f,0xab,0xa7,
+  0xc5,0x89,0x19,0x57,0xe0,0x74,0xac,0xe5,0x88,0xa7,0x9f,0x34,0xd3,0xcb,0x9a,0xa8,
+  0x7b,0x13,0x2e,0xb0,0xe3,0x1f,0xe1,0xa0,0xc4,0xd0,0x32,0x2d,0xad,0x85,0xb7,0x35,
+  0x35,0x5a,0x4c,0xc9,0xf3,0x7a,0x37,0x06,0xb2,0x08,0x51,0xa1,0x4f,0xf0,0x3d,0xcd,
+  0xb6,0x1e,0xaa,0x9d,0xff,0xa9,0x3e,0x2c,0xd7,0x68,0xee,0xb8,0x2f,0xa0,0x3d,0x29,
+  0xd4,0x68,0xf2,0x5e,0x32,0x4a,0x7e,0x80,0x8d,0xc8,0xa2,0xe4,0x1f,0xd9,0x46,0xac,
+  0x46,0xeb,0x89,0x44,0x32,0xf4,0xcf,0x7e,0xbf,0xb6,0x22,0x58,0x28,0xab,0x3b,0x99,
+  0xf7,0x9b,0x57,0x47,0x92,0xb4,0x03,0x6a,0xaf,0x91,0x95,0x5a,0x0a,0x71,0xb6,0xe0,
+  0x45,0x4a,0x22,0x19,0xf5,0x5f,0x87,0x18,0xfe,0xe9,0x09,0x74,0xbf,0x0b,0xfb,0x68,
+  0x80,0xb0,0x40,0x76,0xd2,0xcf,0xdc,0x02,0x15,0x91,0x2a,0x3c,0xa4,0x4d,0xa3,0x76,
+  0xfd,0x33,0xe2,0x1f,0xff,0x22,0x2c,0x53,0xba,0x34,0xfd,0x7d,0xb8,0xb1,0xdf,0xfb,
+  0x81,0xf8,0x12,0x7c,0x04,0x2d,0xb2,0xb7,0x5d,0xfc,0x0e,0xef,0xf8,0xc7,0xbe,0x97,
+  0xb5,0xce,0xfa,0xaf,0x94,0x7e,0x1e,0x26,0xd5,0xe6,0xb1,0xf9,0xfb,0x66,0x3c,0x13,
+  0x3a,0xae,0xb4,0x0c,0x16,0x8f,0x8b,0x01,0x14,0x8a,0x24,0x3d,0x59,0xfc,0x8f,0x91,
+  0xe4,0x3a,0x0b,0xcf,0x0d,0xd5,0x26,0xe4,0x31,0x22,0xd1,0xfb,0xd4,0x05,0xa7,0x96,
+  0xf7,0x91,0x05,0x5a,0x8f,0xec,0x7b,0xd1,0xd5,0x07,0xd9,0xfc,0x4f,0xaa,0xde,0xdf,
+  0x9f,0x90,0x17,0x92,0x6e,0x5a,0x05,0x81,0x04,0x03,0x36,0x0f,0xc8,0x9d,0x2a,0x57,
+  0x68,0xd8,0xf9,0x1f,0x13,0x4f,0x96,0x8e,0xf2,0x46,0x40,0xae,0x78,0x21,0x85,0x9f,
+  0xd2,0x5a,0xfd,0x9a,0xb8,0x6b,0x0f,0xed,0x94,0xfc,0x88,0x88,0xb2,0xf8,0x1f,0x0b,
+  0x0f,0x63,0x19,0xd7,0x93,0xf0,0x1e,0x9d,0x8d,0x8d,0x0a,0x77,0xf3,0xd6,0x7c,0x9e,
+  0x78,0x55,0x2e,0xfe,0x87,0xe7,0x5b,0x39,0xfb,0xf7,0x4d,0xed,0x5f,0x09,0xa7,0x35,
+  0x6e,0x67,0x3f,0x1d,0xc8,0x91,0xff,0x4a,0x3d,0x5f,0xe6,0x40,0xbd,0x8e,0xfd,0x0f,
+  0xbd,0x0d,0x4d,0xfd,0xec,0x7f,0x28,0xc1,0xe3,0x7b,0x4e,0xfd,0x0f,0xc7,0xc3,0xcf,
+  0x81,0xaf,0x5f,0x1c,0x2b,0x1d,0x66,0xb0,0x6d,0x81,0x2e,0xef,0x63,0x30,0xb8,0xc7,
+  0x28,0x0c,0xcc,0xd6,0xff,0xa4,0xd8,0xbf,0xb9,0x6c,0x9b,0xa0,0x0e,0x48,0xfb,0xc0,
+  0xc3,0xfb,0x6f,0x28,0x9d,0x20,0xe7,0xd0,0x3f,0x5b,0xfd,0x70,0x3a,0xd8,0x6e,0x65,
+  0x43,0xe4,0x74,0xd1,0xf7,0xd8,0x95,0x1a,0xac,0x90,0xda,0x1a,0xe3,0x85,0xe1,0x19,
+  0xfc,0x0f,0x8a,0x9c,0x97,0xf0,0x6e,0x87,0xb3,0x46,0xbd,0x4b,0x66,0xe8,0x51,0x76,
+  0xa5,0xbf,0x16,0xf3,0x5f,0xcf,0xd3,0x6b,0xb2,0xeb,0xdf,0xed,0xd9,0xc0,0x5f,0x78,
+  0xc7,0x3a,0x46,0x30,0x9f,0xf8,0xaa,0x87,0xe7,0xbf,0x14,0xe4,0xc7,0xf2,0xf0,0x3f,
+  0xc2,0x84,0xca,0xd0,0xf5,0xfe,0xce,0x30,0x66,0x40,0x12,0x4d,0x71,0x16,0x4f,0xb1,
+  0x90,0x21,0x4f,0xff,0x1f,0xdc,0x4f,0xb5,0xe3,0xc6,0xaa,0xf4,0x04,0x3c,0x55,0xc8,
+  0xfb,0xa7,0x9d,0x52,0xde,0x80,0x2a,0xe4,0x93,0xf3,0xf5,0xff,0x89,0xa0,0x31,0xf7,
+  0x37,0xc2,0x81,0xae,0xf9,0xc3,0xae,0x0d,0xbe,0xdf,0xc0,0x4f,0x0c,0x68,0x64,0xc7,
+  0x3f,0x19,0xfb,0x59,0x9e,0x46,0x3c,0xac,0x19,0xfc,0xb3,0x76,0x18,0x33,0xf8,0x39,
+  0xfb,0xff,0xa4,0xf5,0x3f,0x55,0xdf,0x86,0x2b,0x4a,0x73,0x47,0x49,0x8c,0x2d,0x03,
+  0x94,0x46,0x7b,0xd4,0xbc,0xfc,0x0f,0x33,0xdc,0x5d,0x24,0xa9,0x8e,0x5f,0x35,0x1b,
+  0x3a,0x18,0xfe,0x51,0x4f,0xe4,0xae,0x7f,0xb7,0x67,0x43,0xb6,0xa3,0x50,0x04,0xea,
+  0x96,0xba,0x98,0xc1,0xf0,0x0f,0xd7,0xff,0x90,0x7c,0xfc,0x0f,0x33,0xb6,0xf9,0x50,
+  0x4f,0x52,0x83,0x6d,0x7f,0x06,0xe8,0x13,0x46,0x45,0xbc,0x9a,0x97,0xff,0x59,0xea,
+  0x7e,0x30,0x32,0x00,0x4f,0x30,0xfc,0xe0,0x7a,0x28,0xb4,0x26,0x55,0x11,0x96,0x81,
+  0x7f,0xf6,0xda,0xf4,0x3f,0x5a,0x4f,0x69,0x64,0x20,0xde,0x11,0xf0,0x2f,0x5f,0x8e,
+  0xfd,0x0f,0x77,0x70,0xfd,0x8f,0x8b,0xe4,0xca,0x7f,0x21,0xdb,0x33,0x1b,0xf3,0x5f,
+  0x49,0x3a,0xa2,0x06,0x65,0x06,0x7b,0x50,0x08,0x5d,0x97,0x81,0x7f,0x9c,0xfc,0x4f,
+  0xf3,0xf2,0x55,0x0f,0x75,0x9e,0xdf,0x39,0xe9,0x6f,0x5e,0xfe,0xf9,0x21,0xf1,0xbc,
+  0x92,0xcd,0xff,0xd8,0xf5,0x33,0xaf,0xf9,0x1b,0xb5,0x92,0xa1,0xce,0x39,0xea,0x6b,
+  0xe1,0xba,0xe5,0xde,0x21,0xf1,0x7a,0x9c,0x28,0xcd,0x33,0x24,0xbe,0x20,0xd9,0xf0,
+  0x8f,0x55,0xff,0xa5,0xf4,0x69,0x3e,0x90,0xef,0x25,0x95,0x0c,0xff,0x5c,0x5f,0xc1,
+  0xae,0xec,0xd0,0xba,0x61,0x67,0x5e,0xfe,0x07,0x0d,0xff,0xf2,0xfb,0x82,0xd8,0xf8,
+  0xe8,0x76,0x35,0x54,0xa4,0xa0,0xc2,0xc7,0xaf,0x86,0x64,0xe4,0x7f,0xec,0xfa,0x67,
+  0xb3,0xfe,0x0e,0x0e,0x16,0xa0,0xfe,0xa7,0xac,0xda,0xb7,0x43,0xfd,0x4b,0x9c,0xe1,
+  0x5d,0xd2,0x66,0xf6,0x85,0xf0,0x7e,0x4a,0xe6,0x7a,0x88,0xd9,0xf5,0x4b,0xaf,0x09,
+  0x8d,0xda,0x17,0xa2,0xe2,0x1c,0xe5,0xdb,0x7a,0x29,0x0a,0x7b,0x76,0xf1,0x8a,0x3f,
+  0xc4,0x3f,0xe9,0xf8,0x6b,0xe7,0x7f,0xfe,0x1b,0x17,0x4e,0xcf,0x44,0x84,0xcc,0xaf,
+  0x0c,0x90,0x0b,0x42,0xb3,0xb6,0x20,0x13,0xff,0x98,0xf3,0x2f,0x8d,0xc1,0x3e,0xb6,
+  0x47,0xed,0x54,0xe1,0x84,0x31,0xed,0x49,0x6a,0xf6,0x3f,0xb4,0xd6,0x7f,0xb6,0xfe,
+  0x67,0x98,0xec,0x36,0xfa,0xff,0xf8,0x7d,0x13,0xdd,0x87,0x48,0x43,0x06,0xff,0x53,
+  0xee,0xf8,0x5e,0x54,0xd4,0xff,0xac,0xe3,0x1d,0x24,0x5c,0x8b,0xe1,0xb8,0x62,0xf6,
+  0x3f,0x94,0x72,0xf1,0x3f,0xec,0xd7,0xca,0x81,0xb6,0xf5,0x3c,0x71,0xf6,0xf5,0xdf,
+  0xcb,0xbc,0x43,0x8e,0x92,0x23,0xff,0x65,0xf2,0x3f,0xca,0xc7,0xb4,0x7e,0xb4,0x78,
+  0x9c,0x7c,0x25,0xf2,0x56,0xfc,0xc6,0xd1,0x42,0xde,0xff,0x30,0x7e,0x43,0x16,0xff,
+  0xc3,0xfc,0x49,0xad,0x43,0x5d,0xb0,0x27,0xb9,0x02,0xf6,0x0d,0xa5,0x14,0x86,0x0d,
+  0x27,0x32,0xf0,0x8f,0x95,0xbf,0xc0,0x6e,0x42,0x75,0xbf,0xf7,0x4c,0x88,0xcf,0x2a,
+  0x2f,0x77,0xf7,0xbe,0xed,0x19,0xaf,0xba,0x82,0xfd,0x7b,0x7f,0xeb,0xd9,0x20,0x82,
+  0x23,0xff,0xc5,0xf5,0x3f,0xd8,0xbd,0xe7,0x80,0x34,0x2f,0xe9,0xba,0x93,0xfc,0x90,
+  0x6d,0xa3,0x3e,0x3d,0x2a,0xaf,0xaf,0x3b,0xa5,0x1e,0x80,0x4f,0x0f,0x30,0x47,0xf4,
+  0xa4,0xb3,0xfe,0xcb,0xd4,0xff,0xb0,0xf1,0x26,0x5c,0x77,0x5e,0x35,0x08,0x3f,0x01,
+  0x21,0xf1,0xfd,0xf5,0x64,0x48,0x7b,0x04,0xe6,0xe8,0x35,0xeb,0x09,0xcd,0xa1,0xff,
+  0xf1,0x19,0x44,0x10,0xf3,0x36,0xb5,0x6c,0x3e,0xfd,0x7a,0x0d,0xf6,0xb3,0xed,0x35,
+  0xf8,0xfc,0xee,0xcc,0xfa,0x2f,0x73,0xbc,0xf5,0xfa,0x17,0xe2,0xad,0x97,0xd4,0xf7,
+  0xb1,0x50,0x2b,0x2e,0xbe,0x09,0x6f,0x90,0x45,0x68,0x3c,0xe9,0xe0,0x7f,0xd2,0xf7,
+  0x0b,0xcd,0xfd,0xee,0xeb,0x61,0x94,0xbc,0x1e,0x69,0xd2,0xe7,0x61,0x3e,0xe2,0x30,
+  0x69,0x64,0x11,0x50,0xc8,0x5b,0xff,0xc5,0x37,0xb6,0x4d,0x65,0x2f,0x4a,0x3c,0xf0,
+  0x9d,0x87,0x49,0xb1,0xb7,0x7f,0xeb,0x98,0x60,0xe3,0x7f,0x80,0xb7,0xdd,0xc3,0xfa,
+  0x3b,0xc3,0x28,0xea,0x8b,0x70,0xda,0x01,0xc3,0xd6,0xb0,0xc1,0x5f,0x65,0xf0,0x3f,
+  0x82,0x8d,0xff,0x61,0xf1,0xab,0x2f,0x14,0x50,0x7a,0x48,0x6d,0xbf,0x6b,0x5f,0xe9,
+  0x68,0x7b,0x6f,0xea,0xfe,0x6c,0xfe,0x67,0x21,0xea,0x81,0xa5,0xc0,0x51,0xb6,0xde,
+  0x3c,0x72,0xa7,0xcc,0xf0,0x40,0x90,0xbc,0xa4,0xf4,0x6a,0xe1,0xa1,0x9e,0x2c,0xfe,
+  0xc7,0x67,0xcd,0xcf,0x8d,0xaf,0xae,0x7a,0xaa,0xb5,0x09,0x5e,0x56,0x5b,0x12,0x25,
+  0xf1,0x19,0x67,0xa4,0x8f,0x97,0xcd,0xf8,0xd5,0xd6,0x4c,0xfe,0xe7,0x0d,0xb6,0x5b,
+  0x9f,0x76,0x4e,0x6c,0x82,0x37,0xa0,0xe5,0xc4,0xfd,0x47,0x66,0x8e,0x86,0x30,0x71,
+  0x33,0x7f,0x88,0xc1,0x18,0x53,0xdf,0xeb,0xc0,0x3f,0x17,0x61,0x51,0x8c,0x2d,0x92,
+  0xb3,0x0c,0x08,0x2d,0x31,0xda,0xfe,0xa4,0x64,0x3f,0xb9,0xea,0xbf,0xe0,0xac,0xcc,
+  0x3f,0xab,0xbe,0xba,0x5a,0x06,0x84,0xaa,0xc6,0xec,0x6d,0x7f,0xd2,0xfa,0x1f,0xdb,
+  0xf7,0x38,0x28,0xf7,0x41,0x35,0x95,0x83,0xb7,0x73,0xfc,0x33,0x64,0x4f,0xf3,0xd9,
+  0xf2,0x7d,0xe6,0xfd,0xfa,0x9f,0xef,0x61,0xfe,0xcd,0xd7,0x01,0x46,0xdb,0x25,0x67,
+  0x1b,0x01,0x9b,0xfe,0xc7,0x7c,0x1f,0xac,0xff,0xba,0x28,0x35,0x74,0x55,0x07,0x45,
+  0xa3,0x50,0xab,0xc0,0xf6,0xe1,0xa4,0xeb,0xbf,0xd2,0xfd,0x2d,0x95,0x26,0xb8,0xa8,
+  0xb7,0x24,0xb7,0x8e,0xf1,0xfe,0x7e,0xce,0xb2,0xa6,0xb4,0xfe,0xd9,0x56,0xff,0x15,
+  0x60,0xa0,0xba,0xa1,0xdb,0xb3,0xb7,0x73,0x1d,0xbc,0xab,0x36,0x19,0x6d,0x19,0x5e,
+  0x37,0x2a,0x34,0xf3,0xd4,0x7f,0xc5,0xa9,0x6f,0xc8,0xff,0x0c,0x7b,0xff,0x4e,0x6d,
+  0x81,0xee,0xcf,0xf5,0xfe,0xe9,0xfa,0x2f,0x5d,0xf2,0x48,0xfb,0xe8,0x93,0xf1,0x9a,
+  0xeb,0xc9,0xca,0xf0,0xe3,0x5a,0x40,0xbf,0xc6,0x10,0x8a,0xe7,0xad,0xff,0xd2,0x66,
+  0xc3,0xd3,0xe3,0xf3,0x6a,0x5c,0xdf,0x26,0xb3,0xbb,0xa7,0xd1,0xe2,0x24,0xcf,0x7f,
+  0xd9,0x32,0x62,0x99,0xf5,0x5f,0x15,0x1e,0xed,0x5c,0xb2,0x91,0x3e,0x50,0x27,0x7e,
+  0x81,0x7e,0x15,0x9a,0x06,0x78,0xdb,0x9f,0x5f,0xc7,0x9a,0x86,0xbd,0xc1,0xaa,0x74,
+  0xfd,0x57,0xa1,0xf9,0x3e,0x9a,0xe7,0x19,0xb8,0x52,0x56,0x2f,0x9b,0xb2,0xa8,0x23,
+  0xc5,0xa9,0x69,0xe9,0xcf,0x5d,0xff,0x25,0x17,0x8c,0x4a,0x17,0x21,0x48,0xd9,0xb4,
+  0xdc,0x81,0x68,0xd3,0xd1,0xa6,0x23,0x5d,0xbf,0x90,0xee,0xcf,0xbc,0x94,0xf9,0x13,
+  0xa1,0x52,0x63,0x4e,0x66,0x16,0x6c,0x22,0xf3,0x8f,0xd8,0x65,0x03,0xe9,0xfa,0x2f,
+  0xeb,0x7e,0x60,0xf8,0xa7,0x97,0x56,0xc5,0x8a,0xb0,0xde,0xcd,0x94,0x39,0xd9,0x3b,
+  0x22,0xe6,0xe8,0xff,0xd3,0xfb,0xb9,0x9d,0x5a,0x51,0x30,0x64,0xc8,0xa8,0xdc,0xb9,
+  0xd6,0x9b,0xad,0xff,0x8f,0xb4,0x1b,0xae,0x68,0xf5,0xd1,0xf9,0xaa,0xe8,0x27,0xf7,
+  0xd9,0x81,0xd0,0x56,0x9b,0x22,0xda,0xd6,0xff,0xc7,0xc8,0x47,0x94,0x96,0x50,0xf7,
+  0x99,0x54,0x21,0x58,0x0e,0x3d,0x86,0xb3,0xff,0xf3,0x07,0x4a,0x5d,0x98,0x05,0xc1,
+  0x1f,0x67,0xc9,0x42,0x72,0xea,0x7f,0xaa,0xe5,0x83,0x47,0x7c,0xcb,0xe4,0x68,0xe4,
+  0x53,0xea,0xc1,0x36,0xa7,0xec,0x24,0x5f,0xfd,0x97,0xb6,0x53,0xab,0x60,0xd1,0x99,
+  0x66,0xde,0x96,0xaf,0xfe,0xcb,0xaf,0x6a,0x15,0x0a,0x91,0x64,0xec,0x7f,0x68,0x00,
+  0x03,0x29,0x43,0xff,0x63,0xe9,0xc3,0x17,0x5f,0x8d,0xdd,0x7e,0xea,0x68,0x80,0xfd,
+  0x0d,0x64,0xec,0x7f,0x98,0x73,0xbc,0xa7,0x0b,0xcd,0xf7,0xe9,0x43,0xfd,0xcf,0xbc,
+  0x96,0xe5,0x6c,0xb7,0x35,0x90,0x1a,0xdd,0x0c,0xde,0x0f,0xd9,0x31,0xde,0x37,0xd3,
+  0x78,0x86,0xe1,0x8d,0xcb,0x70,0xe3,0x32,0x4f,0x3b,0x43,0x3b,0x97,0x8d,0xb4,0x11,
+  0xde,0x76,0xb7,0xe3,0xfe,0x34,0xff,0x53,0x01,0x49,0xb9,0x4f,0xae,0x85,0x62,0xea,
+  0x42,0xd9,0x4f,0x8d,0xe2,0x36,0x64,0x57,0xb6,0x8c,0x98,0xb3,0xff,0xcf,0xb2,0x2e,
+  0x79,0x6f,0xe8,0x0e,0x06,0x5a,0xae,0x5a,0x86,0xa3,0x5b,0x66,0x1f,0x66,0xae,0xfe,
+  0x3f,0x65,0xbb,0x52,0x65,0x5f,0x5c,0x4f,0x5e,0x93,0x9a,0x46,0xc1,0x39,0x9f,0x69,
+  0xfd,0xf3,0x4e,0xec,0x7f,0xf8,0xf7,0xcd,0x4b,0x3d,0x4a,0x2a,0xff,0xd5,0x63,0xbc,
+  0x76,0xad,0xf1,0xfe,0x07,0x53,0xfa,0x1f,0xab,0xff,0xe1,0x08,0xf6,0x3f,0xe4,0x4d,
+  0x0e,0x3b,0x6d,0x40,0xe8,0xed,0x8c,0xf5,0x70,0xd1,0x51,0xff,0x35,0xa2,0xd6,0xb1,
+  0xf1,0x8a,0x61,0x3e,0xcc,0x9c,0xf3,0x9f,0xae,0xff,0x02,0xc9,0x0f,0xcf,0xca,0x95,
+  0x54,0x3e,0x4b,0x96,0xd0,0xa7,0xb5,0x12,0x87,0xec,0xc7,0x32,0xd2,0xfd,0x0f,0x65,
+  0xb6,0xff,0x7a,0x5c,0xaf,0x86,0xa2,0x26,0xd2,0xa6,0xee,0x8b,0x3b,0x65,0x87,0x36,
+  0xfd,0x8f,0xf9,0x0f,0xeb,0xbf,0x9e,0xa6,0x9f,0x3a,0x22,0xaf,0x2f,0x5c,0x0d,0x4f,
+  0x63,0x23,0xe8,0x5c,0xdf,0x6f,0xc2,0x7c,0x3c,0xf8,0x2b,0x66,0xc3,0x59,0xfa,0x54,
+  0xac,0x78,0x83,0xf8,0xdf,0xe1,0x23,0x7b,0x22,0xcc,0x6e,0x1c,0xf3,0x59,0xeb,0xb3,
+  0x78,0x0f,0x5c,0x82,0x43,0x94,0x79,0xd7,0xdd,0x46,0xa1,0x93,0xad,0x8d,0x58,0x5a,
+  0xff,0x73,0xaf,0x39,0xde,0x70,0xd9,0xb3,0xda,0x95,0x68,0xbd,0xea,0x19,0x71,0x5f,
+  0x05,0x03,0x74,0x89,0x19,0xb6,0x9a,0x87,0xed,0xf1,0x6b,0x28,0xad,0x7f,0xae,0x78,
+  0x0c,0x9e,0x8e,0x55,0x6a,0xc5,0x9f,0x21,0xab,0xa1,0x4b,0x5b,0x88,0xb2,0xa5,0x41,
+  0x7c,0xed,0xa4,0xfb,0x1b,0x36,0xfd,0x8f,0xa5,0xaf,0xa6,0xf0,0x98,0xb0,0x5f,0x79,
+  0x7c,0x1b,0xf3,0x57,0xab,0x51,0xed,0xac,0x9b,0xb7,0x25,0x7a,0x6c,0xe3,0x4d,0xc7,
+  0x3b,0x8d,0xc5,0xf7,0xb8,0xa6,0x52,0x16,0xe6,0xda,0x08,0x35,0x89,0xfd,0x54,0xdb,
+  0x31,0x6b,0x3e,0x6d,0xf5,0x5f,0x05,0x7b,0xe0,0x43,0x8d,0xfb,0x4f,0x3f,0xca,0xfc,
+  0xf4,0xeb,0x30,0x4c,0x4c,0x48,0x77,0x38,0xe2,0x4b,0x9a,0xdf,0x8b,0x29,0xa3,0x70,
+  0x51,0x65,0xd1,0x19,0xe7,0x67,0xdc,0xda,0x78,0x66,0xf8,0xdb,0xf4,0xfb,0x20,0xfe,
+  0xb9,0x08,0xf5,0xb4,0x03,0x37,0xf5,0x97,0x48,0xaa,0xcc,0xf9,0x0d,0xc3,0x8d,0x7f,
+  0x27,0xbb,0xff,0x4f,0xbf,0xb4,0x4e,0xee,0xeb,0xa8,0x89,0xb9,0x9e,0x21,0xef,0x40,
+  0x9f,0xee,0x0c,0x5b,0xb6,0xfa,0x2f,0xf3,0xef,0x85,0xf5,0x5f,0xbb,0xa9,0x2f,0xe6,
+  0xde,0x4e,0xf6,0x68,0x7d,0x34,0x75,0xdb,0x0f,0x32,0xee,0x77,0xf6,0x7f,0xee,0x53,
+  0x6b,0x74,0xd7,0xf5,0xe4,0x28,0xc4,0x53,0xcb,0xac,0xad,0x57,0x31,0xea,0xbf,0x72,
+  0xe8,0x7f,0xe4,0x75,0x30,0xb2,0xbe,0x8e,0x2e,0xd8,0x26,0x3e,0x61,0x8d,0x17,0xe3,
+  0xef,0x0b,0x56,0xc7,0x5d,0xaf,0x03,0xff,0x94,0x5d,0x82,0xf1,0xe0,0x8d,0x74,0xd5,
+  0x7a,0xe6,0xb4,0x2f,0x19,0xb2,0xe7,0x4b,0x74,0x92,0xe1,0xa5,0xeb,0xec,0xf1,0x3d,
+  0x9b,0xff,0xc1,0xd5,0xf2,0x06,0x2c,0x49,0x94,0x9c,0xeb,0x0c,0xb0,0xf9,0xaf,0x3d,
+  0xe6,0x5d,0x2d,0x36,0x51,0xf6,0x53,0x3f,0xf2,0x3f,0x36,0xfd,0x39,0x03,0x39,0x1d,
+  0xb5,0x49,0x91,0xa3,0x1d,0xdd,0x37,0x26,0x6f,0x21,0x0b,0x94,0x43,0x7a,0x6d,0x9c,
+  0xcd,0xc0,0x02,0xed,0x70,0x64,0xc1,0x70,0x4e,0xfd,0x0f,0x1f,0xdd,0x0e,0xcd,0x2f,
+  0x31,0x98,0x27,0xc0,0x5e,0x8d,0x77,0x08,0x07,0xe8,0x2d,0xe0,0x78,0xd8,0xd1,0xff,
+  0xd0,0x36,0xdb,0x84,0x01,0xad,0x68,0xe1,0x6e,0x85,0xcf,0x67,0x37,0xf3,0x78,0x06,
+  0x23,0x14,0x4a,0xe3,0x31,0xb0,0xeb,0x4f,0x5e,0x97,0x1a,0x13,0x25,0x41,0xf7,0x7c,
+  0x89,0x5f,0x99,0x2d,0xd6,0x6a,0x13,0x70,0x77,0x3f,0xc3,0xcf,0xba,0x85,0x67,0x62,
+  0xd3,0x1d,0xfc,0x0f,0xdb,0x68,0x24,0xb1,0xad,0x0d,0xb4,0xec,0x66,0xfb,0x4d,0x06,
+  0x1d,0xc9,0xdd,0x99,0xf8,0x67,0x8f,0x59,0x54,0x38,0x0a,0x1f,0xb4,0x2d,0x2e,0x62,
+  0x4f,0xdb,0x11,0x3a,0x0a,0xcd,0x47,0xbc,0xdb,0x3a,0x55,0x3d,0xa5,0x38,0x4a,0xf3,
+  0x0f,0x06,0xff,0x63,0x56,0x0b,0x52,0x5f,0x54,0x7e,0xa6,0x75,0x77,0xd9,0xeb,0x43,
+  0x0c,0x16,0x6e,0xef,0xbc,0x0d,0x0e,0x4b,0x0b,0x18,0x42,0x73,0xe2,0x9f,0xf4,0xd7,
+  0xb1,0xef,0x66,0x7f,0xd2,0xd5,0x04,0x0f,0xd0,0xce,0x23,0x81,0xb0,0xdb,0xd6,0x88,
+  0x7e,0xdc,0xda,0x7f,0x85,0x21,0xad,0xff,0x11,0x9e,0x8e,0x56,0x0e,0xcb,0x9f,0x23,
+  0x3f,0xa4,0xf7,0xd2,0xf9,0xb1,0x9e,0x71,0x54,0xc8,0x74,0xcc,0x1f,0x2e,0xca,0xc0,
+  0x3f,0xf0,0x61,0x0c,0x9f,0x2f,0x0e,0xc2,0x07,0xe0,0xff,0xeb,0x92,0x60,0xe7,0xa6,
+  0x68,0x47,0x77,0xd3,0xed,0xd3,0x82,0xa2,0x87,0x7e,0x08,0xb3,0x74,0x8f,0x83,0xff,
+  0x99,0x95,0xd2,0xff,0x18,0xab,0xe5,0x1e,0xdd,0x3b,0xd4,0x7a,0xaa,0xed,0x0d,0x58,
+  0x30,0x60,0xea,0x9f,0xfb,0x9d,0xf8,0x27,0xcd,0xbf,0xad,0x83,0x8b,0xb4,0x2e,0xe9,
+  0xe9,0x13,0x6b,0xb1,0xfe,0x02,0x23,0x3e,0x43,0x44,0x05,0xcd,0xaf,0x78,0x1c,0xfd,
+  0x0f,0x05,0x1b,0xff,0xf3,0x34,0xcf,0x76,0xf9,0x66,0x49,0xf7,0x02,0xf3,0xd8,0xed,
+  0x64,0x0b,0x6c,0x82,0xc0,0x09,0xbf,0xf3,0xfc,0x0b,0x1b,0xff,0xb3,0x97,0x56,0x87,
+  0xe5,0xc5,0xe4,0x5e,0xe8,0xe8,0xf0,0x87,0xe1,0x44,0x88,0x77,0xc0,0x46,0x05,0x54,
+  0x1a,0xff,0xac,0x75,0xd4,0x5f,0x40,0x4c,0xf7,0x2f,0xac,0xd9,0x42,0xb0,0x8d,0xb6,
+  0x7f,0x56,0x64,0x0b,0x74,0x4a,0x01,0x83,0xff,0x31,0xef,0x1f,0x29,0xb3,0xf8,0x9f,
+  0xb5,0xa8,0xfe,0xa2,0x9e,0x11,0xb1,0x0f,0x8e,0xc3,0x12,0xea,0xf9,0x4b,0x71,0x03,
+  0x39,0x66,0x28,0x82,0xec,0xfd,0x0f,0x6d,0xfb,0x71,0xc3,0x10,0xc2,0xbc,0x30,0x07,
+  0xeb,0xbf,0x24,0x3c,0x18,0xa2,0x20,0x13,0xff,0xe4,0x85,0x3d,0x86,0x50,0x36,0x90,
+  0x81,0x7f,0x6c,0xe8,0x45,0xab,0x6d,0x77,0x6f,0x23,0xbf,0x37,0x8c,0x68,0xea,0x60,
+  0x8b,0xfc,0xfa,0x9f,0xc3,0x72,0x6d,0xc8,0x1d,0x8d,0x0c,0xab,0x07,0x99,0xb1,0x22,
+  0x7a,0x4d,0xc0,0xbc,0xff,0x05,0x6b,0x7e,0x32,0xf9,0x9f,0xe5,0xee,0xd2,0xc8,0xc0,
+  0xee,0xbd,0x35,0x81,0xe5,0x2b,0x18,0x22,0xc2,0xf3,0x2f,0x96,0x3b,0xf5,0x3f,0xd7,
+  0x3a,0xf8,0x1f,0x86,0x7f,0x90,0xff,0x19,0x57,0x67,0x23,0x10,0xe2,0x07,0x31,0x60,
+  0x45,0xd8,0x69,0x6b,0xfd,0xf4,0xd9,0xfa,0xff,0x18,0xea,0xe5,0x21,0xf1,0xbc,0xf4,
+  0x73,0xd2,0xa2,0xad,0x6a,0xb7,0x9d,0x7f,0x51,0x98,0xc6,0x3f,0xf6,0x69,0x91,0xeb,
+  0x34,0xcf,0x43,0x9d,0xc3,0xd5,0x17,0xe4,0xe6,0x10,0x17,0xc6,0xb0,0x0f,0x2d,0x14,
+  0x70,0xe2,0x9f,0x98,0xc5,0xff,0xb0,0x8d,0x55,0x43,0x99,0xdc,0xe5,0x3b,0x03,0x7d,
+  0x5a,0xad,0xc2,0xc2,0xfa,0x85,0xf6,0x6e,0xa8,0x55,0xda,0x1c,0xf8,0x47,0xea,0x4a,
+  0x8f,0xf7,0xe7,0xb4,0x52,0xdb,0xbc,0x9a,0xbc,0x0a,0x4f,0x75,0xcc,0x0f,0x8b,0xed,
+  0xe4,0x94,0xd2,0x61,0x54,0xcc,0x39,0xf0,0x4f,0x7a,0x3e,0x9f,0x82,0x4f,0x85,0x8a,
+  0x86,0x6e,0xfe,0xb7,0xe8,0xcf,0xd5,0x05,0x5a,0xcf,0x10,0x39,0x7f,0xcb,0x66,0x63,
+  0x3e,0x6d,0xf5,0x5f,0x92,0xfd,0xef,0x1b,0xaa,0xd3,0xe6,0x6f,0x13,0xdf,0x82,0x0b,
+  0x7a,0x73,0x3b,0xf6,0xe3,0x25,0x47,0x8d,0x83,0x3c,0x6c,0xf5,0x5f,0x8e,0xf5,0xa0,
+  0x34,0x2f,0x2b,0x89,0x56,0xbd,0x99,0x42,0x44,0x88,0x18,0x85,0xeb,0xb3,0xf1,0x8f,
+  0x35,0xff,0x97,0xa0,0x1e,0x3c,0xba,0xb8,0x10,0x2e,0x15,0xd4,0x43,0xc9,0x00,0x73,
+  0x3b,0xe3,0x42,0x06,0xfe,0x91,0x25,0x07,0xff,0xe3,0xe7,0x69,0x2f,0x63,0xc7,0xba,
+  0xb3,0x34,0x8d,0x7f,0x54,0xd3,0x3f,0xc8,0x0e,0xfd,0x0f,0x55,0xcf,0xb0,0xef,0x0b,
+  0x3b,0x86,0xa9,0x49,0x66,0x0c,0x4a,0x58,0xc1,0xc4,0xf1,0x8f,0xf5,0x3d,0xda,0xf5,
+  0x3f,0xfb,0xb5,0x79,0x4a,0xdb,0x4a,0xa2,0xc0,0x7e,0xbd,0x32,0x28,0x6b,0x64,0x08,
+  0xb0,0x31,0x72,0x16,0xfe,0xb1,0xd0,0xce,0x39,0x1a,0x8f,0x05,0xfc,0xee,0x6b,0x0c,
+  0x23,0x8d,0x7f,0xaa,0x6c,0xf8,0xe7,0x5a,0x1b,0x1f,0x72,0x01,0x65,0x84,0xd6,0xf7,
+  0x42,0xed,0xe7,0x5f,0x98,0xef,0xc3,0xf0,0x8f,0x11,0xbf,0x0e,0x8a,0x58,0xc8,0x53,
+  0xb7,0x66,0xeb,0x76,0x6e,0xb4,0x84,0x59,0xfc,0x2a,0x64,0x8e,0xa8,0x19,0xf3,0x17,
+  0x43,0xe9,0xfe,0x87,0xf2,0x63,0x6c,0xbc,0xec,0x25,0x37,0x70,0xff,0xa3,0xc6,0x4a,
+  0xd6,0x5e,0x35,0xc4,0x0c,0x6c,0x3b,0xe6,0xfb,0x3e,0xdd,0xb4,0x6b,0xfe,0xa8,0xec,
+  0xd4,0xff,0xcc,0xb2,0xfa,0xff,0xc0,0x33,0x30,0x47,0x6e,0xd5,0x98,0x77,0xdd,0x8f,
+  0x65,0x5f,0x43,0xe4,0x2a,0xfa,0x13,0x95,0x13,0xd7,0x76,0xfc,0xb3,0xc5,0xee,0x7f,
+  0x76,0xe9,0xae,0x1b,0x23,0x03,0xa8,0x30,0x3f,0xe2,0x56,0x49,0x37,0xee,0xc8,0xfa,
+  0xe5,0xcc,0xfa,0xf7,0x34,0x7a,0xa1,0x0d,0x98,0x88,0x79,0x13,0x26,0x74,0x86,0x70,
+  0xd8,0x8e,0x8c,0x17,0xf2,0xec,0x71,0xe0,0x1f,0x18,0x95,0xac,0xfb,0xc7,0x69,0xa3,
+  0x5a,0x82,0xec,0xdf,0x38,0xbd,0x5b,0xf5,0x46,0xdd,0xc3,0x52,0x4e,0xfc,0x93,0x8a,
+  0x77,0xcf,0x60,0x98,0xc3,0xee,0x6d,0x63,0xda,0x71,0xc3,0x58,0xcc,0x22,0x7e,0xb3,
+  0x13,0xff,0x38,0xfa,0xff,0x5c,0x20,0xfc,0x43,0x18,0x65,0x9f,0x61,0x89,0xd6,0xfa,
+  0xbd,0xd2,0xea,0x1c,0xf8,0x47,0xb0,0xdd,0x6f,0x7d,0x38,0x9b,0x61,0xae,0x86,0x69,
+  0x32,0x25,0x67,0xfd,0xbb,0x35,0x3f,0xfb,0xc0,0xb3,0x9d,0x4d,0x4b,0x82,0x44,0x20,
+  0x40,0x57,0xc4,0x49,0x09,0x4d,0x29,0xa2,0x6d,0xf8,0xa7,0xc2,0x00,0x39,0xee,0x7d,
+  0x9d,0x7b,0x60,0x0c,0x9a,0x67,0x7a,0x23,0x9d,0xbc,0x11,0x96,0x84,0x27,0x10,0xc5,
+  0x5e,0x57,0xf9,0x8e,0xdb,0x86,0x7f,0xb0,0xff,0xb3,0x3f,0x15,0xbf,0x4c,0xe1,0x93,
+  0xfa,0x4f,0x2e,0x34,0xdc,0xec,0xa7,0x50,0x06,0xfe,0x01,0xc0,0xba,0x08,0xcc,0xfa,
+  0x2b,0x53,0x18,0x60,0xff,0x27,0x01,0x7b,0x3b,0x8d,0x79,0xe0,0x29,0x0c,0xfb,0xbf,
+  0x2e,0xa8,0x04,0xf6,0x71,0x28,0x53,0x19,0xff,0x9e,0xe7,0x23,0xf9,0x98,0x3a,0xf3,
+  0x2c,0xaf,0x61,0xfb,0x37,0xf5,0x8d,0x86,0xf1,0xef,0x79,0xfe,0x1f,0xfb,0xef,0x3f,
+  0xd9,0xfc,0x2b,0x78,0x96,0xdf,0x20,0xdc,0xc9,0x80,0xd1,0x14,0x86,0xf4,0x7f,0xfc,
+  0xfc,0xff,0xe0,0xf9,0x97,0x14,0xfa,0x07,0xcc,0xb9,0x60,0xf9,0x93,0x3f,0xf6,0x5f,
+  0x53,0xd3,0x1f,0x72,0x97,0xd7,0xfb,0x7f,0xf8,0xf8,0xff,0x17,0xfe,0xb5,0x4c,0x4e,
+  0x4e,0xea,0x9f,0x60,0xfc,0xff,0xf9,0xfe,0xff,0x64,0xdf,0xe3,0x7f,0xf9,0xc3,0xff,
+  0xf2,0x87,0xff,0x8e,0xf9,0xff,0x2f,0x7f,0xf8,0x49,0xff,0xfe,0xb3,0xf9,0x9f,0xff,
+  0x5c,0xf7,0xeb,0x05,0xe7,0xe1,0x38,0x6d,0xd1,0x3c,0x23,0xe2,0xb3,0xf0,0x2f,0x94,
+  0x57,0xc3,0x71,0x7e,0x35,0x5f,0x7e,0x50,0xf9,0x4b,0xb8,0x8f,0x2e,0x08,0xcb,0xbb,
+  0x4b,0x6b,0xf9,0x69,0xb0,0xb9,0xf3,0x83,0x69,0x7e,0x8c,0xad,0xd9,0x08,0xb6,0xd9,
+  0x8f,0x95,0x6e,0x51,0xbe,0x0f,0xd5,0x7a,0xee,0xfc,0xa0,0x8d,0x1f,0x7b,0x4b,0xb9,
+  0xaf,0xbb,0x96,0x3d,0x1f,0xd5,0xe0,0x42,0x9e,0xfc,0xe0,0xb8,0xb5,0xdf,0x14,0xca,
+  0xfe,0x49,0x3a,0xd6,0xdf,0xec,0x0f,0xa8,0x33,0xf6,0x48,0xbf,0x56,0x1b,0x8c,0x32,
+  0xc6,0x89,0x8c,0xfc,0x9d,0x2d,0x3f,0x08,0x5b,0xc8,0x15,0xb8,0x91,0xed,0x0e,0xd8,
+  0x6e,0x73,0x52,0x6d,0x31,0xfa,0x23,0x4d,0x95,0x1f,0x7c,0x02,0x9b,0xe4,0x2c,0x0b,
+  0x44,0xc4,0x3d,0x74,0x42,0x6e,0xd4,0x03,0xb9,0xf2,0x5f,0xce,0xfc,0xe0,0x7d,0xb4,
+  0x56,0xef,0xde,0x4f,0x8a,0xd9,0xee,0x40,0x1d,0xc9,0xf9,0xfe,0x76,0x7d,0xd4,0x32,
+  0x78,0x78,0x7d,0x20,0x24,0x57,0x87,0xb6,0x42,0xaf,0xe2,0x77,0xb4,0x65,0xcb,0xd9,
+  0x1f,0xe0,0x2a,0xed,0x11,0x54,0x6f,0xae,0x0d,0xcd,0x56,0x5b,0x68,0x65,0x72,0x79,
+  0xae,0x7c,0x99,0x5d,0x1f,0x25,0xc1,0x2b,0x5d,0x4d,0x5a,0x40,0x15,0xb7,0xc0,0x87,
+  0xea,0x62,0xdd,0x93,0x6a,0x0b,0x99,0xcc,0xd7,0x1f,0x72,0x3f,0x79,0x07,0x5a,0x86,
+  0xbc,0x61,0xde,0x5f,0xf4,0x46,0xfd,0xf3,0x46,0x23,0x71,0x7e,0xac,0x5e,0x8e,0xfc,
+  0xa0,0x5f,0xfa,0x31,0xbc,0xc8,0xb6,0xb1,0x25,0x31,0x71,0x9d,0x34,0x41,0x50,0x48,
+  0x4f,0xb2,0xe7,0x27,0xfd,0xf7,0x4d,0x28,0x8f,0xc1,0x26,0xa1,0xb2,0x5f,0xc6,0xf3,
+  0x61,0x0f,0xc0,0x8e,0xdc,0xf9,0x85,0x73,0x36,0x7f,0xf5,0x00,0x3c,0x70,0xdf,0x9c,
+  0xb0,0x6b,0x64,0xee,0x57,0x90,0xdf,0xe0,0x8d,0x92,0x64,0x6b,0xbc,0x3f,0x31,0x8c,
+  0x84,0x3d,0x3f,0xb8,0xbc,0x9b,0xa8,0xbf,0x95,0xeb,0x78,0xbf,0x71,0xd5,0x31,0x8d,
+  0x39,0xf2,0x83,0xc9,0xf2,0x43,0xf0,0x00,0x5d,0xb4,0xbd,0xe4,0x8e,0x3b,0xd7,0x96,
+  0x5d,0x39,0x55,0x67,0x10,0x0b,0x99,0x1d,0x93,0xc6,0x33,0xf4,0x51,0x4d,0xe0,0xed,
+  0x42,0x35,0x26,0x34,0x2b,0x9f,0x98,0x1f,0x1c,0x16,0x2e,0x44,0xeb,0xda,0x78,0xdb,
+  0x9c,0x0b,0x94,0x57,0x3f,0x59,0x0c,0xc9,0x9a,0x3c,0xfd,0x01,0xc8,0xce,0x0d,0xf2,
+  0xb6,0xc8,0x1c,0xd8,0x9b,0xf0,0xad,0x2d,0x49,0xa7,0xa5,0x42,0x79,0xfb,0x43,0xfa,
+  0x34,0x88,0x62,0x7f,0x00,0xb5,0xa6,0xcd,0x4a,0x63,0xcd,0xcc,0x9d,0x1f,0x04,0x29,
+  0x76,0x10,0x65,0xe1,0x46,0x7f,0x00,0xbf,0x36,0x33,0x57,0xbe,0x2c,0xdd,0x9f,0x64,
+  0x83,0x1c,0xa6,0x87,0xa0,0x4e,0xae,0x35,0xfa,0x03,0x1c,0x72,0x0c,0xd3,0xa2,0xce,
+  0x4e,0xdb,0xfa,0x43,0x9e,0x2f,0xfa,0x37,0xb8,0x11,0xcf,0x7b,0x1d,0x96,0xff,0x0d,
+  0x17,0x46,0x2e,0x62,0xd0,0x5e,0x1f,0x77,0x1e,0x5e,0x82,0xfa,0x90,0x67,0x68,0xda,
+  0x79,0xf9,0x32,0x2c,0xd1,0x66,0x19,0xc7,0xc8,0xb6,0x20,0x6d,0x98,0xf3,0x7c,0x90,
+  0x33,0x6d,0xdd,0x05,0x3e,0x45,0x66,0xae,0x07,0x85,0x04,0x30,0xdb,0x2a,0x94,0xcb,
+  0x77,0x3e,0xc8,0x35,0x9b,0xa9,0x1a,0xf6,0x07,0x0b,0x07,0xd8,0x6c,0xf8,0x35,0xab,
+  0x2d,0xa4,0xbd,0x3f,0xa4,0xed,0x7c,0xd8,0xf2,0x5d,0x32,0x6f,0x4b,0xfe,0x5d,0xd4,
+  0x47,0x15,0xf9,0xd2,0x6d,0x21,0xe5,0x9c,0xf9,0xc1,0xd8,0xf4,0x37,0x83,0xfd,0x74,
+  0x5f,0xbb,0xe7,0xb1,0xc2,0xe1,0x32,0x2c,0x73,0x4b,0xb5,0xb5,0x6c,0x72,0xf4,0xb7,
+  0xb4,0xf7,0x47,0xfa,0xf1,0xb2,0x1b,0x14,0x73,0x36,0xa2,0xf9,0xce,0x87,0xb5,0xf3,
+  0x63,0x42,0xa2,0x28,0x88,0x6a,0xf0,0x58,0x45,0xe2,0xb6,0x46,0x58,0x35,0x75,0x7e,
+  0x50,0x2d,0x90,0x85,0x07,0xe4,0xaa,0x7b,0xbb,0x87,0xc5,0x3e,0xf6,0x69,0x56,0xc6,
+  0x3c,0x6c,0x3d,0x2b,0x87,0x60,0x81,0x33,0x3f,0x68,0xf1,0x63,0xfe,0x2e,0x8f,0x10,
+  0xd1,0xd4,0xb8,0x3c,0x77,0x6e,0x1b,0xa5,0xba,0xbf,0xd4,0xcc,0x0f,0xd2,0xd4,0xf7,
+  0xe2,0xcf,0xc8,0x0f,0x82,0x07,0x36,0x81,0x4a,0x65,0xec,0x0f,0xb0,0x47,0xab,0x54,
+  0x52,0x65,0xf2,0x5f,0xa7,0x79,0xf2,0x83,0xdd,0xb3,0x95,0x4d,0x91,0x85,0x6a,0x60,
+  0xad,0xf8,0xdf,0xa5,0x01,0x7a,0x43,0xf8,0xba,0x14,0x2d,0x16,0x4b,0xe5,0x07,0x6f,
+  0xc8,0xc8,0x0f,0x7a,0xf6,0x90,0x0f,0x8d,0x8f,0x8e,0xc2,0x98,0xd0,0xa4,0xa5,0xdb,
+  0x62,0x1b,0x46,0x83,0x93,0x1f,0xd3,0xca,0x4f,0x6b,0xff,0xa0,0x2c,0x8c,0x79,0xba,
+  0xc9,0x69,0xed,0xf7,0x74,0xa1,0xca,0xe2,0xd7,0x03,0xe4,0xe5,0xe8,0x8d,0xb1,0x5a,
+  0x7b,0x7e,0x30,0xcd,0x8f,0x5d,0xfd,0x98,0xde,0x19,0xaf,0xa4,0xf2,0x0a,0xf1,0x15,
+  0x3a,0x00,0x3b,0xba,0xe5,0x31,0x32,0x9b,0x6e,0x8a,0xcd,0xdf,0x9d,0x3a,0xef,0xe3,
+  0x06,0xdd,0xd9,0x1f,0x92,0x3e,0x53,0xb4,0xb5,0x6e,0x0e,0x95,0xb5,0x9b,0x4e,0xc8,
+  0xfb,0xe5,0x4a,0xa1,0x68,0x8c,0x3c,0x86,0xfd,0x30,0xbb,0xe5,0x9c,0xf9,0xc1,0xb0,
+  0xf4,0x92,0xd0,0x39,0xbd,0x3a,0xe6,0x87,0x7b,0x75,0xa0,0x47,0x18,0x5c,0xb3,0xca,
+  0xa0,0x72,0xe7,0x07,0xa5,0x3d,0xea,0xd1,0x8e,0xeb,0x9f,0x67,0x7f,0x5f,0x5d,0x8a,
+  0xd3,0x3a,0xb8,0x1f,0xeb,0xbb,0x7b,0x0a,0x9a,0x69,0x4d,0xce,0xfc,0x20,0xd6,0x67,
+  0xbd,0x0b,0x8d,0x51,0xef,0x46,0xf4,0x3f,0x2a,0xef,0x86,0xed,0x98,0x9f,0xc6,0x4c,
+  0x7e,0xec,0x19,0x75,0x12,0x16,0xc1,0x16,0x5d,0x8c,0xc3,0xa0,0xb6,0x44,0x33,0xdd,
+  0x38,0x4d,0x19,0x8b,0xb2,0xf2,0x83,0xd0,0x3b,0xe0,0xa3,0xb2,0x4c,0xaa,0xe8,0xb8,
+  0xee,0x0b,0xbb,0xb1,0x3f,0xcf,0x61,0xec,0x2f,0x91,0x3b,0x3f,0x88,0xfd,0x01,0xf4,
+  0xb9,0x11,0x79,0x0b,0xd9,0x09,0xf7,0x69,0x35,0xaa,0x79,0x1b,0x4d,0x2b,0xa6,0xb2,
+  0xf4,0x51,0xf2,0x5c,0x2a,0xd3,0x10,0xd0,0x3e,0xf6,0x9a,0x78,0x30,0x04,0xed,0x95,
+  0x03,0x91,0xd6,0xbc,0xfd,0x01,0x26,0xd4,0x06,0xea,0x89,0x74,0xc6,0x68,0x02,0x1a,
+  0xc1,0x68,0x3b,0xac,0x36,0x3f,0x66,0x5f,0x0f,0xce,0xfe,0x90,0x1f,0xce,0x5b,0x42,
+  0xbd,0xba,0x98,0xfc,0x1c,0x9e,0x50,0xc1,0xcb,0x9a,0xf8,0xfc,0xe4,0xce,0x0f,0x6e,
+  0x34,0x17,0x49,0x55,0xca,0x18,0x9b,0xf6,0x91,0xf6,0x46,0x74,0x91,0xd1,0x31,0xe0,
+  0x8d,0xa6,0x7a,0x95,0x19,0x71,0xeb,0x3c,0x6b,0xbd,0xc2,0xc8,0x0f,0xa6,0xd1,0xce,
+  0x33,0xa1,0xd1,0xd2,0x1e,0x3c,0xdf,0xb6,0x8e,0x78,0xe8,0x26,0xd5,0xb7,0x83,0xfd,
+  0x34,0x66,0xf9,0xff,0x04,0x6c,0x51,0x9c,0xd1,0xe7,0x7a,0x36,0x2d,0x8f,0x73,0x1a,
+  0x30,0xb2,0x52,0x7d,0x18,0x54,0x8d,0xfd,0x74,0x2e,0xad,0x0f,0x97,0xf6,0x64,0xa1,
+  0x85,0x51,0x9a,0x6a,0x0b,0x19,0x80,0x99,0xc2,0xed,0xda,0x4c,0xbb,0x3e,0xfc,0xb3,
+  0xe5,0xa3,0xfc,0x3c,0x3b,0x5b,0xb4,0x25,0xc7,0x95,0x17,0x85,0x06,0x7d,0x55,0x7c,
+  0xfa,0x3a,0xe9,0x75,0xa9,0x6e,0x0e,0xfb,0x29,0x66,0xf9,0x9f,0x58,0x4a,0x1f,0xbe,
+  0xd5,0x36,0x1b,0x57,0xe0,0x1f,0x52,0xf8,0x47,0x79,0x1f,0xbc,0xfd,0x8e,0xfe,0x90,
+  0x98,0x1f,0x7c,0xd7,0xf9,0xfc,0x3f,0x31,0x96,0x19,0xf6,0x9f,0x54,0x5f,0x64,0xa1,
+  0x81,0xfd,0xf4,0x81,0xb5,0x3e,0x4f,0x64,0xd4,0x4b,0xe2,0xc1,0x3a,0xcc,0xe8,0xae,
+  0xfd,0x6d,0x71,0x5f,0xe7,0x1d,0xea,0x1b,0xa4,0xae,0x9d,0xcd,0xe6,0x47,0xd6,0x7a,
+  0xd0,0xa5,0x95,0x59,0xd1,0x79,0x25,0xcc,0x68,0x0b,0x24,0xe4,0x7d,0x64,0x0f,0xfc,
+  0x00,0xaa,0x95,0x1e,0xc7,0xf9,0x68,0x8a,0x51,0x26,0xef,0xbe,0xab,0x90,0xa3,0x9d,
+  0xb7,0x2d,0xd8,0x83,0x1d,0x23,0xa3,0x07,0xa2,0x95,0x31,0x76,0x65,0xdc,0x86,0x7f,
+  0x56,0x1a,0x20,0xa7,0x91,0xa1,0x9d,0x5e,0x25,0x90,0x74,0x2f,0xb9,0x69,0x50,0xf9,
+  0x10,0x38,0x10,0x7a,0x80,0x3e,0x1f,0xbf,0x7e,0xd4,0xeb,0x38,0x1f,0xb6,0x1c,0xfb,
+  0x43,0xde,0x63,0x76,0x43,0x42,0xf6,0x98,0x37,0x0a,0x58,0x34,0xc0,0xf3,0xe9,0x6f,
+  0x40,0xcb,0x11,0xc4,0x3f,0xd6,0xfc,0xcb,0xd2,0x9e,0x74,0x7e,0x10,0x0b,0x57,0x4b,
+  0xe2,0x55,0x28,0x94,0xe2,0x07,0xd5,0x8d,0x0a,0x2f,0xf6,0xd7,0xc9,0x5b,0x1d,0xfa,
+  0xf0,0x0a,0x67,0x7f,0x80,0x7e,0xf7,0x37,0x7d,0x58,0x16,0x57,0xc5,0x1b,0x05,0xe0,
+  0x89,0x69,0x83,0x45,0x0c,0xff,0xa8,0xe6,0xf3,0x1d,0xf9,0x41,0x6e,0x7c,0x9b,0xe0,
+  0x89,0x69,0x73,0xf8,0x78,0xe1,0xe1,0xef,0xfd,0x08,0xc7,0x9b,0xb4,0xf0,0xea,0x88,
+  0x9d,0x9f,0xaf,0x37,0x8c,0xe3,0xa1,0x1e,0x53,0x68,0x27,0x1a,0x08,0x3c,0xad,0x0f,
+  0x4f,0x96,0x8f,0x28,0x06,0xc8,0x31,0x60,0x4f,0xc7,0x3f,0xc4,0x44,0x3c,0x31,0xad,
+  0x81,0x9f,0x27,0x25,0x1e,0x33,0x5a,0x07,0xd8,0xf0,0x8f,0xe0,0xac,0xd7,0x36,0x8f,
+  0x45,0xbb,0xcb,0xcc,0x18,0x36,0xc2,0xb4,0x3c,0xf9,0xc1,0x94,0xa1,0x54,0x55,0xf3,
+  0x7e,0xc8,0xdd,0xbc,0x10,0x4c,0xe0,0x89,0xb0,0xbc,0xfd,0x01,0xb8,0x50,0x19,0x1b,
+  0x25,0xed,0xd4,0xfc,0x51,0x57,0xb5,0x6b,0x33,0x94,0x24,0x1d,0xf8,0x67,0x71,0x41,
+  0x46,0x37,0x24,0x16,0xaf,0xab,0x55,0x3c,0x1f,0xad,0x07,0x11,0xd1,0x66,0xde,0x31,
+  0xc0,0xd6,0x1f,0xc0,0x5f,0x86,0xf9,0xc1,0x6a,0x5e,0x2f,0x0f,0x0f,0xf2,0xfe,0x48,
+  0xf7,0xe1,0x95,0x30,0xd2,0x0f,0x58,0x3a,0x97,0xd1,0x1f,0x69,0x43,0x66,0x7f,0x00,
+  0x6f,0x44,0x64,0xab,0x10,0x4a,0xa1,0x84,0x56,0x51,0x48,0x18,0x47,0xa7,0x9d,0xb5,
+  0xea,0xeb,0xb7,0x67,0x9e,0x97,0xc1,0x46,0x77,0x3e,0x75,0x3e,0x48,0x64,0xf8,0x47,
+  0xd8,0x3a,0xdb,0x1b,0x9d,0xf1,0x51,0xce,0xfe,0x00,0x86,0xf1,0x50,0xe7,0xef,0xe1,
+  0x35,0xa5,0x41,0xf3,0x60,0x7d,0xdc,0x6b,0x59,0x7a,0xaa,0x8a,0xb4,0x3e,0x9c,0x1b,
+  0x62,0x17,0x33,0xba,0x19,0x10,0xc2,0x63,0x2b,0x61,0x44,0xe5,0x3f,0x9d,0x4e,0xe3,
+  0x1f,0xb0,0xe5,0x07,0x1f,0x34,0x8d,0xef,0xaa,0xf3,0x97,0xcb,0xed,0xe4,0x16,0xfa,
+  0xe0,0xe7,0x02,0xe1,0x99,0xf6,0xfe,0x48,0xdb,0xa5,0x5d,0x59,0xea,0xb2,0x01,0x7a,
+  0x3f,0x99,0xaf,0xe1,0xfd,0xe6,0x54,0xdb,0xf4,0xe1,0x99,0xe3,0xc5,0xb7,0xe5,0x7a,
+  0x6f,0x7f,0xd4,0xbd,0x46,0x7a,0x4d,0x68,0x0e,0x7b,0xa3,0x64,0xc4,0xd2,0xe7,0x24,
+  0x1c,0xfd,0x01,0xd2,0x46,0x0a,0x18,0x17,0xc1,0xec,0x35,0x0e,0xfc,0x23,0x67,0xf4,
+  0x07,0x60,0xc6,0x34,0x23,0x51,0xc8,0x3c,0xfc,0x18,0x76,0xcc,0xc6,0x7a,0xcc,0x63,
+  0xd4,0x5c,0xff,0x19,0xfa,0x70,0x34,0x0a,0x47,0x78,0x07,0x0c,0xbc,0x22,0x19,0x86,
+  0xd8,0x9d,0x5e,0x0f,0x52,0xd6,0xee,0xe0,0xe6,0x41,0xdc,0xb8,0xa1,0x50,0x3c,0x81,
+  0x19,0xf6,0x01,0x87,0x3e,0x9c,0x2a,0xb7,0x9a,0xdf,0xef,0xad,0xb6,0x44,0x21,0xcc,
+  0x01,0x51,0x23,0xaf,0xc2,0x81,0x6d,0x73,0x10,0x08,0x8d,0x68,0xe6,0xf3,0xbb,0xbb,
+  0xbf,0x92,0x4a,0x02,0x12,0x33,0x1b,0x48,0x4e,0xb2,0x40,0x53,0x99,0xdc,0xba,0x41,
+  0x3c,0x09,0x1f,0xc6,0x17,0x1a,0xe7,0xa3,0x99,0xeb,0x4d,0x76,0xea,0xa5,0xb1,0xde,
+  0x67,0xc6,0x08,0x8c,0x4b,0x77,0xa0,0x42,0x6c,0x18,0x26,0xb4,0xc6,0xed,0xec,0xa7,
+  0xc8,0xbd,0xe6,0xfc,0x40,0xd9,0xb3,0x2c,0x5a,0x2d,0x31,0xce,0x77,0x78,0xc3,0x6c,
+  0x14,0x90,0xd2,0xf7,0xde,0xc5,0xfe,0x87,0xee,0x39,0xcf,0xae,0x8c,0x59,0xf3,0xff,
+  0xa4,0x62,0xf6,0x87,0xe4,0xfe,0x27,0xf0,0x36,0x1b,0xe6,0x69,0x6d,0xff,0xce,0x1b,
+  0x02,0x6e,0x8d,0x48,0x5a,0xaf,0x52,0xcd,0xf1,0x8f,0x35,0xff,0x00,0x8f,0x09,0x76,
+  0x7f,0x95,0x70,0xaf,0x57,0x4e,0x44,0x53,0x8a,0xf1,0xff,0x8e,0x57,0xda,0x57,0xac,
+  0xb7,0xed,0xdf,0x55,0x65,0x4b,0x96,0x3f,0x4f,0xc8,0x71,0xc9,0x0f,0x6e,0x60,0xdf,
+  0x57,0x2f,0x54,0x87,0x33,0xfa,0x03,0x18,0xd1,0xc4,0xda,0xad,0x5f,0x17,0x27,0x67,
+  0xbb,0x27,0x8c,0xfe,0x72,0x6b,0xd1,0x03,0xb7,0xb1,0xf1,0x9e,0x4e,0xeb,0xc3,0x85,
+  0x3d,0x52,0xc6,0xfc,0x60,0xa2,0x50,0xe0,0x65,0x02,0xc3,0xf2,0x04,0xcc,0x56,0x1c,
+  0xfd,0x91,0x2a,0x95,0xac,0x78,0xd7,0x3a,0x6e,0x1c,0x14,0x82,0x8a,0x29,0x76,0x25,
+  0xec,0x19,0x63,0xfb,0x77,0xf3,0xfe,0x1d,0x92,0x71,0x3e,0xac,0x01,0x7b,0x52,0x6c,
+  0x03,0x3c,0xc3,0x22,0xb6,0x5b,0x27,0xe7,0xd9,0xff,0x62,0x00,0xe4,0xb8,0x2f,0xed,
+  0x7f,0xb0,0x3f,0x40,0xe6,0xe9,0x15,0xa3,0x90,0x92,0x85,0x8f,0x60,0xab,0x9c,0x6d,
+  0x8e,0xfe,0x00,0xae,0x32,0x4f,0x3a,0xcc,0x3d,0x0c,0x81,0xa3,0xd8,0x38,0x48,0x8d,
+  0x57,0x86,0x89,0x08,0x75,0x03,0x4a,0xaf,0x52,0xdb,0xe5,0x77,0xe0,0x9f,0xfb,0x59,
+  0x58,0x41,0x7d,0xf8,0x53,0x33,0x46,0xb1,0x51,0xf3,0xa9,0x9e,0xfd,0x5f,0x1d,0xa1,
+  0x13,0x6a,0x5d,0xa2,0x24,0x28,0xbe,0x8d,0xf3,0x03,0x2c,0x10,0x27,0xd3,0xe7,0xc3,
+  0x96,0x5f,0x82,0x09,0x85,0x9f,0x0f,0x8b,0xea,0xaf,0xe6,0x97,0x5e,0x3e,0xd7,0x39,
+  0x0e,0x97,0x94,0x16,0xfc,0x5e,0xce,0xc7,0xde,0x57,0x5b,0x8a,0x1c,0xf8,0xa7,0xbf,
+  0x20,0x0e,0xef,0x09,0xd3,0xcf,0x04,0xc6,0xc5,0x66,0x98,0xec,0xba,0x51,0xf5,0x8c,
+  0x73,0xa1,0x78,0x4b,0x1e,0xfe,0x47,0x97,0x93,0x42,0x31,0xf5,0xe9,0xfe,0x3e,0x82,
+  0xfa,0xf0,0x5a,0xd5,0x35,0x35,0xff,0x73,0x4c,0x8a,0xc1,0x0e,0xca,0x9b,0xf2,0xe1,
+  0xc0,0x6b,0x21,0x27,0xbf,0x61,0xe3,0x7f,0xa4,0xc7,0xe5,0xcd,0x2a,0x46,0x2b,0x29,
+  0xe0,0x61,0xf3,0xa9,0xba,0xa6,0xd6,0x87,0x2f,0x2d,0x7f,0x1b,0x76,0x40,0x10,0xa3,
+  0x79,0x40,0x9a,0x90,0x9a,0x82,0xf6,0x63,0xf5,0xd2,0xfd,0x21,0xad,0xf3,0x61,0xe3,
+  0xc2,0x6e,0xf9,0x02,0xe5,0x41,0x9c,0xaf,0x07,0xc8,0xad,0x0f,0xb7,0xf5,0xc7,0x7e,
+  0x12,0x8e,0xc2,0x3e,0xab,0xdb,0x24,0x94,0xe4,0x7a,0xbe,0xbd,0x3e,0x4e,0x86,0x13,
+  0xe0,0x3b,0xc3,0xd0,0x0b,0x7f,0xdb,0xd2,0x4f,0xe2,0x7f,0xa4,0x65,0xd0,0x19,0x56,
+  0x93,0xae,0x3a,0xec,0x8e,0x0e,0x01,0xd9,0x95,0x6b,0x7e,0xc6,0xd2,0xf8,0x07,0xbe,
+  0x1c,0xfa,0x2e,0xad,0x1c,0x96,0x53,0xfd,0x91,0x62,0x90,0x02,0x06,0x79,0xce,0x07,
+  0x59,0x5b,0xa1,0xc1,0xf3,0x34,0x7e,0x04,0x65,0xe1,0x03,0x1f,0x4a,0x4d,0xed,0x25,
+  0x4b,0xc4,0xe3,0x90,0x6a,0x0b,0x69,0xf1,0x3f,0x27,0xd3,0xfc,0xcf,0xd5,0x71,0xe1,
+  0x3d,0xb0,0xce,0x97,0x69,0xd6,0xec,0x8d,0x02,0x72,0xea,0xc3,0xf7,0x28,0x2f,0xb6,
+  0xd5,0x25,0x4b,0x16,0xf3,0xfe,0x00,0x4d,0x6a,0xf1,0xd4,0xfa,0xf0,0xc4,0xd5,0x8f,
+  0xc1,0x2f,0x79,0x37,0x00,0xce,0xff,0xcc,0x07,0x39,0x17,0xff,0x73,0xd1,0xa6,0x8f,
+  0x8a,0xa8,0x0f,0x73,0xda,0xa7,0x90,0x17,0x06,0xae,0xe7,0xb0,0xe7,0x11,0x3a,0x3f,
+  0x8f,0x3e,0x3c,0x21,0xdd,0x27,0x77,0x42,0x8c,0x81,0x9c,0xab,0xf8,0x87,0xa6,0x15,
+  0x05,0xe7,0x4e,0xcd,0xff,0x8c,0xc3,0x0f,0x63,0x75,0x88,0x7f,0xf0,0x34,0xb4,0x96,
+  0x58,0xb1,0xa3,0x51,0x76,0x36,0xff,0x23,0xc4,0xa6,0x8d,0x85,0xd9,0x32,0xe8,0x42,
+  0x7d,0xb8,0x71,0x5e,0xe7,0x27,0xe9,0xc3,0xf1,0x90,0x2f,0xef,0x43,0xfc,0x18,0xd0,
+  0x86,0xb5,0xb6,0xc0,0x27,0xe4,0xd2,0x87,0xc3,0x1a,0xd8,0x9c,0xf4,0xb5,0xbb,0x51,
+  0x4f,0x9e,0x57,0xef,0x6d,0xc7,0x3f,0x52,0xe1,0x66,0x69,0x67,0x78,0x66,0x94,0xfc,
+  0x08,0xcf,0xf3,0xca,0xa7,0x0f,0x37,0xd7,0x83,0x5f,0x92,0xf8,0xb1,0x68,0x16,0xdb,
+  0x93,0x9b,0xff,0x49,0xe3,0x1f,0x4f,0x98,0x26,0x54,0x9c,0x1f,0xce,0xff,0x38,0xdb,
+  0x42,0xa6,0xf5,0xe1,0xb6,0xfa,0xb8,0xfd,0xb1,0xcb,0xd0,0xb4,0xdc,0x1b,0x9d,0xb6,
+  0x8b,0xd3,0x38,0xa8,0x0f,0x97,0xa6,0xe2,0x7f,0xfe,0x8d,0xfe,0xab,0xa7,0x5e,0xf3,
+  0x0c,0x89,0xdf,0x62,0xbf,0xde,0xe8,0xa0,0x4d,0x72,0x9f,0x0f,0xd2,0xd5,0xad,0xed,
+  0x04,0x3f,0x0d,0x31,0xfc,0x43,0x4c,0xda,0x47,0xc8,0xab,0x0f,0xd7,0x36,0x76,0x3d,
+  0x88,0x7c,0x97,0x39,0x3a,0xd7,0xd4,0xfa,0x70,0x86,0x7f,0x2a,0x1e,0x65,0xe8,0x91,
+  0x57,0x03,0xb1,0xd9,0xbb,0x05,0x8c,0x69,0x2c,0xc9,0xa3,0x0f,0x8f,0x95,0xbf,0x15,
+  0x7e,0xcd,0x13,0xd4,0x56,0x46,0x5b,0x39,0x9b,0xb7,0x3e,0xe0,0xd0,0x87,0x67,0xf1,
+  0x3f,0x09,0xe1,0xc7,0xd2,0x19,0x78,0xd6,0xf1,0xd7,0xcf,0xc1,0xff,0x58,0xfe,0x47,
+  0x56,0x76,0x40,0xe2,0xb6,0x3a,0xc9,0x13,0x31,0x66,0x5b,0x31,0x8e,0x05,0x21,0x25,
+  0x79,0xfb,0x43,0x2e,0x0e,0x3f,0xa0,0x55,0xc5,0xe5,0x24,0xb9,0x60,0xf4,0x47,0xca,
+  0xa5,0x0f,0xb7,0xd5,0xc7,0x49,0xff,0x03,0x22,0x5a,0xac,0x93,0xcd,0x4f,0x02,0xfb,
+  0xd5,0x6c,0xe0,0x65,0xb9,0xd9,0xfa,0x70,0x2b,0xde,0x31,0xfc,0xd3,0xc9,0xd0,0x8e,
+  0xbc,0x8c,0x9c,0x62,0xc0,0x60,0x41,0xf4,0xaf,0x73,0x7d,0xbf,0xe9,0xfe,0xd8,0xdd,
+  0xdd,0x77,0xc3,0x2f,0x69,0x7d,0x38,0xd0,0x26,0xbe,0xa2,0x30,0xfc,0x73,0x5b,0xc9,
+  0x06,0x16,0xcd,0x3f,0xee,0x72,0xea,0xc3,0x6d,0xe7,0xc3,0x16,0xec,0x99,0x31,0x81,
+  0x45,0x7f,0x31,0x43,0x0d,0x05,0x39,0xfd,0x89,0xad,0x3e,0xae,0xeb,0x59,0xe5,0x97,
+  0xf7,0xd6,0xc7,0x3c,0x89,0xd6,0x93,0x0c,0xff,0xdc,0xa8,0xda,0xc3,0x56,0xae,0xf3,
+  0x61,0x2b,0x1e,0xd3,0xc4,0xe9,0x8b,0x40,0x5e,0x4a,0x12,0xda,0x26,0x98,0x5f,0xe8,
+  0x42,0x20,0xc4,0x36,0x86,0x8e,0xf7,0x77,0xf6,0x47,0xda,0x8a,0x7a,0x7b,0x54,0x7f,
+  0x3d,0x82,0xb2,0xa8,0x5c,0xe3,0xb5,0xf5,0x07,0x60,0xfb,0xaf,0x4e,0x7d,0x2e,0x66,
+  0xe9,0x74,0xb6,0xdb,0x0a,0x40,0x4e,0xfe,0xd9,0x81,0x7f,0x68,0xbf,0x5e,0x47,0x3d,
+  0x54,0xd0,0x91,0x66,0x0f,0x7b,0xe3,0x42,0xf6,0x78,0x6d,0xe7,0xc3,0x0a,0xbb,0xc9,
+  0x05,0xb6,0xe9,0x58,0xd5,0x85,0xc7,0x94,0xb3,0xf9,0xa9,0xcd,0x35,0x3f,0xe9,0xfe,
+  0xd8,0x95,0xca,0x63,0xdd,0x2f,0x03,0xfb,0xbe,0x06,0x59,0x10,0x7f,0x9f,0x7d,0x8f,
+  0xa9,0x7a,0x1f,0xaf,0x23,0xde,0xd9,0xf2,0x23,0xd2,0xdf,0xd0,0x9e,0x63,0x35,0x20,
+  0x77,0x93,0xdf,0xe1,0x69,0x02,0x6a,0x71,0xae,0xf8,0xe5,0xec,0x8f,0xf4,0x44,0x87,
+  0x8f,0xb2,0xcf,0xd0,0xa7,0x32,0x20,0xa4,0x5e,0x9d,0xf3,0x7e,0x9b,0x3e,0x5c,0xc2,
+  0x26,0x24,0xec,0xff,0x48,0x3f,0x5b,0x48,0xb5,0x70,0xf5,0x42,0x63,0x5a,0x86,0xf2,
+  0xe8,0xc3,0xef,0x5f,0x09,0x3f,0x55,0xb0,0x3e,0x45,0x54,0x91,0x88,0x60,0xeb,0x61,
+  0xc6,0x7b,0x5a,0x56,0xfd,0x57,0x5a,0x1f,0x55,0x7e,0x1e,0x26,0xab,0x39,0xda,0x19,
+  0xa3,0x3c,0xbe,0x9f,0xc3,0x63,0x61,0xfd,0xfc,0x58,0xd8,0x3c,0xfa,0x70,0xac,0xaf,
+  0x34,0xd3,0x5e,0x7a,0x71,0xa2,0xaa,0x8e,0x19,0x9c,0xff,0x39,0x07,0x83,0xb4,0x65,
+  0x30,0xab,0x3f,0xb6,0xc1,0xff,0xa0,0x50,0x9c,0x2e,0x48,0xc2,0x76,0x32,0xb7,0xe2,
+  0x30,0xd4,0x20,0xec,0xf9,0x2d,0x3c,0x19,0x59,0x30,0x98,0xd5,0x1f,0xbb,0x97,0xa4,
+  0xce,0x87,0xc5,0xb2,0xd3,0x22,0x5a,0x0a,0xf0,0xb0,0x51,0xa6,0xbd,0x1b,0xcb,0x11,
+  0x13,0x59,0xfd,0xb1,0x1d,0xb3,0x27,0x47,0x7d,0x81,0x78,0x2f,0x3f,0x28,0x84,0x6d,
+  0x44,0xad,0xf3,0x41,0xcc,0xbf,0xaf,0x5a,0x6e,0x83,0xc1,0x48,0xd4,0xdc,0x5f,0x20,
+  0x56,0xc2,0x84,0xd1,0xd1,0x68,0x80,0x26,0x84,0xd4,0xf9,0x68,0xe6,0xf3,0x1d,0xfd,
+  0x01,0x26,0x59,0xf4,0x77,0x8f,0xfc,0xe8,0xa3,0xd4,0x15,0xe1,0x63,0xf5,0xb2,0xd1,
+  0x28,0x20,0x7f,0x7f,0x48,0xdd,0x43,0xf9,0xc2,0xe3,0x34,0xe3,0xdb,0xbc,0x82,0xc3,
+  0x93,0xb3,0x3f,0xb6,0xf1,0xfe,0x0b,0xf4,0xb6,0x5d,0x22,0xb6,0x05,0x6b,0x48,0xe1,
+  0x61,0x76,0x05,0xec,0xf8,0x47,0xcf,0x3c,0x1f,0x56,0xae,0x26,0xcb,0xb5,0x19,0x46,
+  0xe2,0x46,0xd3,0xe2,0x61,0x43,0x1f,0x9e,0xa7,0x3f,0x00,0x83,0x3d,0xfe,0xd5,0xe4,
+  0xa4,0x76,0x20,0x86,0x1d,0x14,0x43,0xaf,0xc0,0xd3,0x5d,0xf3,0xb1,0x5e,0xde,0x86,
+  0x7f,0xb0,0x3f,0x40,0x34,0x80,0xe7,0xc7,0x71,0xb4,0x33,0xe2,0xa9,0x14,0x5f,0x18,
+  0x98,0xa0,0x1b,0x30,0xff,0x35,0x00,0x1f,0x48,0x4d,0x89,0x40,0xce,0xfe,0x00,0x06,
+  0xec,0x69,0xfe,0x4d,0xed,0x83,0x33,0x9e,0x99,0x9e,0x9a,0xb1,0x61,0x6d,0x62,0x75,
+  0x66,0x7f,0xc8,0xf2,0x51,0x93,0x1f,0xe3,0x13,0x75,0xc2,0xbb,0xbf,0xf3,0x9d,0xfe,
+  0x89,0x54,0x7f,0xf2,0xee,0x13,0x7a,0xdd,0xb9,0x29,0xfa,0x03,0xe0,0x7e,0xea,0x9b,
+  0xa1,0x13,0x9a,0x71,0xbe,0x12,0xf9,0xd7,0xd8,0x53,0xea,0xf5,0x27,0xe4,0xcc,0xfe,
+  0x00,0x3f,0x71,0xa0,0x9d,0xbf,0x23,0x1f,0x75,0xe1,0x15,0xd7,0x06,0xf2,0x06,0x3c,
+  0x4b,0x2b,0x51,0x1f,0x3e,0x66,0xf1,0x3f,0x6d,0x52,0xca,0x7b,0xc7,0xcd,0xaf,0xa9,
+  0x29,0x82,0x07,0x0d,0xf3,0xc6,0x77,0x83,0x65,0xbd,0x72,0x75,0x46,0x7f,0x80,0x82,
+  0xdd,0xf0,0x8e,0x03,0xed,0xfc,0x18,0x0d,0x81,0xcb,0xc2,0xdf,0xd6,0x4e,0xf6,0xd7,
+  0xd1,0xda,0xfc,0xfd,0x21,0x31,0x11,0x86,0xc6,0x76,0xa1,0x19,0xa6,0xb1,0xf8,0xcb,
+  0xfb,0x43,0x16,0xe4,0x39,0x1f,0xd6,0x50,0x83,0x17,0x6f,0x47,0x22,0xc8,0xaa,0x17,
+  0xe3,0xa9,0x10,0xe2,0xc4,0x3f,0x46,0x90,0x15,0x0d,0xa3,0xbb,0x8f,0xbc,0x4f,0x31,
+  0xc3,0xc5,0xc2,0x2e,0xdb,0x91,0xe9,0x99,0xf9,0xaf,0x72,0x4b,0x1f,0x6e,0x18,0xf3,
+  0xf6,0x62,0x9b,0x56,0x06,0x84,0xb0,0x9f,0x2a,0x0a,0xc5,0xf3,0xf6,0xc7,0xe6,0xf5,
+  0x62,0x0c,0x18,0x84,0x10,0x06,0xa8,0x08,0x84,0x96,0x09,0xa9,0x8a,0xb9,0x9c,0xfd,
+  0xb1,0xf1,0x7c,0xae,0x66,0xb9,0x98,0xb6,0xc6,0xa4,0x71,0x78,0xd6,0x8a,0xbf,0x28,
+  0x14,0x3f,0x6b,0xef,0x0f,0xe0,0x44,0x3b,0x2f,0x47,0x2b,0x07,0xc0,0xa0,0x7d,0xd8,
+  0x95,0x0f,0x60,0x8a,0xfe,0x90,0xfc,0x74,0x54,0x34,0xe4,0x0b,0xc8,0xff,0xa4,0xae,
+  0xb4,0x79,0x1c,0xfc,0x8f,0xe2,0xe4,0x7f,0x14,0x99,0x03,0x21,0xf0,0xc1,0xe7,0x28,
+  0x19,0x91,0xb1,0x51,0x76,0x76,0x7f,0x00,0x5e,0xfd,0x17,0x4a,0xe3,0x1f,0x61,0xaf,
+  0x9a,0x46,0x80,0x37,0xcb,0x59,0xfd,0xb1,0xed,0xe8,0x91,0xa7,0xbd,0xf6,0xb2,0xf9,
+  0x2f,0xe2,0x57,0xa8,0xd1,0x1f,0x32,0xcd,0xff,0x94,0x65,0xf0,0x39,0x0f,0x30,0xa3,
+  0xeb,0x02,0x3c,0x8d,0xef,0xff,0xe6,0xe7,0x2e,0x84,0x67,0x63,0x22,0x2f,0xcd,0xff,
+  0xec,0x06,0xc7,0xfd,0x4d,0x5a,0x49,0xb4,0x6a,0x98,0x66,0xe2,0xe1,0xcc,0xf3,0xd1,
+  0x6c,0x68,0x73,0x6b,0x87,0x78,0x86,0x5a,0x1d,0xb3,0xc7,0x8d,0x83,0xd2,0x6c,0xfd,
+  0x01,0xa4,0x0c,0xfe,0x47,0xde,0x43,0xde,0xa5,0x68,0x30,0x84,0xff,0x0e,0x1c,0x52,
+  0x79,0x7f,0xb9,0x74,0x7d,0x9c,0xdf,0xd9,0x9f,0x84,0x7d,0x2f,0x8d,0xd2,0xcb,0xf0,
+  0xb0,0x10,0xd0,0x85,0x20,0xf9,0x82,0xd2,0x4b,0x3d,0xe8,0x7f,0xd2,0xfc,0x8f,0x43,
+  0x1f,0x6e,0xf6,0x77,0x85,0x03,0x41,0x7e,0xe5,0x9f,0x19,0x3e,0xe6,0x57,0xd2,0xfc,
+  0x8f,0xdf,0xde,0x1f,0xf2,0x00,0x6d,0x4a,0x7a,0x57,0x8b,0xa7,0x85,0x8f,0x77,0xf3,
+  0x2b,0x27,0xe1,0x6f,0x69,0xcb,0x48,0x20,0xbb,0x3f,0x80,0xcd,0xdf,0x2e,0xf8,0x1e,
+  0x5b,0xc6,0xd8,0x78,0x84,0xf9,0x93,0x61,0x3a,0xa1,0x35,0x1f,0xf1,0x66,0x9c,0x8f,
+  0x66,0x80,0x9c,0x0b,0x29,0xb4,0xe3,0x19,0x65,0x61,0x2b,0x05,0x7b,0x26,0x61,0x52,
+  0x6f,0x79,0xd3,0x11,0xbf,0x76,0x9b,0xfe,0xe7,0x2e,0xe3,0xfd,0x93,0xdd,0x77,0x1b,
+  0x65,0xfb,0x03,0xee,0x6f,0x90,0xdf,0xd0,0xa7,0xd1,0xc3,0x64,0xe2,0x1f,0xc7,0x78,
+  0xdb,0x42,0x85,0x27,0xd4,0xd4,0x95,0x13,0xf4,0x29,0x82,0x8c,0x90,0x0d,0xff,0x84,
+  0xcb,0x32,0xd0,0x8e,0x5c,0xc1,0x76,0xf7,0xa9,0x0a,0x20,0xb6,0xde,0x64,0x03,0x4f,
+  0xe6,0xd1,0x87,0x63,0x34,0xe9,0xeb,0x3c,0x2b,0x4d,0x9a,0xf5,0x80,0x17,0x84,0x16,
+  0xec,0xaf,0x7b,0xda,0xde,0x1f,0xc0,0xc9,0xff,0x2c,0xd8,0x35,0xe3,0x3d,0xf3,0x09,
+  0x6f,0xc3,0x38,0x4d,0xe1,0x1f,0xf3,0xf9,0x19,0xfd,0x01,0x9a,0x74,0xcf,0x07,0x9d,
+  0xe3,0xaa,0x75,0x0c,0xc4,0x95,0x23,0x2d,0x48,0x04,0xa5,0xf9,0x9f,0x8c,0xf3,0x61,
+  0x59,0xfc,0x8d,0x91,0x33,0xb0,0xc4,0xb8,0xf2,0x36,0x1c,0x0a,0xd7,0xea,0x33,0x9d,
+  0xf8,0x27,0xf3,0x7e,0xca,0xfe,0x5e,0xa9,0xfa,0xb8,0xe1,0x18,0xfb,0x82,0xf4,0xd6,
+  0x78,0x69,0x86,0x3e,0x5c,0x33,0xfa,0x43,0xe2,0xfc,0x9c,0x90,0x09,0x9b,0x16,0x63,
+  0xc6,0x4a,0x75,0x1a,0x37,0x0e,0x4a,0x73,0xd6,0xc7,0xf1,0xd3,0x39,0x53,0xe3,0x3d,
+  0xc9,0x56,0xfb,0xdb,0x78,0x10,0xf9,0xab,0x7c,0x98,0xe3,0xbc,0x51,0x80,0x98,0x74,
+  0xf6,0x47,0xc2,0xd1,0xed,0xaf,0xe2,0xf1,0x2b,0xb1,0xa0,0x43,0x1c,0x8b,0xa5,0x14,
+  0xe3,0x49,0x6d,0xdc,0x10,0x72,0xd8,0xf1,0xcf,0x2b,0xf0,0x91,0xba,0x88,0x06,0x6c,
+  0x68,0x79,0x2a,0xfe,0x87,0x2a,0x6f,0xc2,0x73,0x7a,0xd5,0x58,0x1b,0x67,0x7b,0xc0,
+  0x79,0x2c,0x48,0xce,0xf3,0x41,0x58,0xbc,0x57,0xe6,0x76,0xe5,0xa4,0x7d,0x72,0x9e,
+  0x0f,0x32,0x57,0x62,0xde,0x3b,0xb7,0xec,0x27,0xd7,0xf9,0xb0,0xe5,0xbf,0xa5,0x13,
+  0xbb,0x1a,0xda,0x73,0xd2,0x3e,0x39,0xce,0x87,0x4d,0x0a,0xfb,0x61,0x32,0xda,0xd8,
+  0x96,0x93,0xf6,0x49,0x9f,0x0f,0x62,0xd3,0xff,0xc4,0xc2,0x47,0xa1,0xb4,0x3d,0xa7,
+  0xec,0x27,0x27,0xff,0xf3,0x29,0xe8,0xe8,0xbe,0x3e,0x3c,0xf5,0xfb,0xdb,0xce,0x87,
+  0x15,0xbe,0x40,0xe8,0x6d,0x6a,0x41,0x4e,0xda,0x27,0xf7,0xf9,0x20,0xca,0x46,0x3a,
+  0x27,0xe8,0x4a,0x9d,0x06,0x92,0xc4,0x46,0xaf,0x53,0xea,0x7f,0x64,0x38,0x02,0x41,
+  0x85,0xb7,0x05,0xf8,0x10,0x66,0x8d,0x78,0x1b,0xd1,0x10,0x9a,0xfa,0xf3,0xe8,0x7f,
+  0x8a,0xfb,0xd8,0xfc,0xb4,0xa8,0xd7,0x8e,0x99,0xb4,0xcf,0x07,0x9c,0x08,0x72,0xce,
+  0x8f,0xbd,0x3f,0x12,0x5b,0x84,0xae,0xba,0x23,0xa9,0xf9,0x6f,0x4c,0xae,0x8c,0xb7,
+  0x9e,0x85,0xcc,0xf3,0x53,0x9c,0xf8,0xe7,0x29,0xa8,0xd4,0x8b,0xd1,0x9f,0x3c,0x67,
+  0xa4,0xbd,0x2e,0xc1,0xbf,0x64,0xe9,0x7f,0xcc,0xe7,0xf7,0xc3,0x43,0xb0,0x8f,0xde,
+  0x96,0xe4,0x7c,0xd7,0x73,0x74,0x1e,0x1a,0x57,0xb0,0x2c,0xce,0x31,0x5e,0x5b,0x7f,
+  0xa4,0x6d,0xc7,0xa1,0x37,0x1c,0x1e,0x9b,0x97,0xea,0xf7,0xa2,0x43,0xae,0x7e,0x0b,
+  0xf6,0xfe,0x48,0x7d,0x70,0x45,0xeb,0xc5,0xfe,0x90,0x88,0x7f,0x1a,0x29,0x37,0x96,
+  0x67,0xf0,0x3f,0x69,0xfc,0xb3,0x1c,0x92,0xfa,0x18,0x34,0x95,0x5a,0xf1,0x28,0xa7,
+  0x1e,0xc3,0xce,0xff,0xbc,0xa9,0x1d,0x55,0xf7,0x99,0x6a,0x96,0xba,0xdc,0xfb,0x7d,
+  0x7b,0xfe,0xeb,0x26,0xd8,0xac,0xee,0xbc,0xd9,0x50,0x9b,0x10,0x9f,0x11,0x88,0x1f,
+  0x9d,0xf2,0x7c,0x90,0xcd,0x82,0x2f,0x1d,0xa6,0x3f,0xb1,0x3f,0x40,0x21,0xf6,0x87,
+  0x34,0xf9,0x90,0x58,0x46,0x62,0x28,0x4b,0xff,0xd3,0xc7,0xf0,0x4f,0x42,0xdd,0x27,
+  0x07,0x8c,0xd1,0xd5,0xe1,0xe9,0x6f,0xd9,0xe3,0xb5,0x9f,0x0f,0x7b,0x9e,0x5c,0x46,
+  0xfd,0x0f,0x1f,0x1d,0xef,0x86,0x34,0x23,0x7b,0xbc,0x69,0xfc,0xb3,0x5d,0x38,0x0f,
+  0xef,0x75,0xd7,0xaf,0x4d,0xa1,0x9d,0xda,0xf6,0x9c,0xf3,0xe3,0xec,0x8f,0x8d,0x6d,
+  0x91,0xba,0x39,0xfe,0x51,0x03,0x82,0x9d,0xf6,0xc9,0x79,0x3e,0xc8,0x0b,0xb0,0x03,
+  0xaa,0x97,0xad,0x56,0x4a,0x79,0xf4,0xe1,0xc3,0x14,0xb2,0xf9,0x2e,0x1b,0xfe,0x91,
+  0x0e,0xaa,0x73,0x1d,0x6a,0x9f,0x1c,0xf3,0x99,0xe6,0x7f,0xbe,0xfb,0x7b,0x78,0x1b,
+  0x7e,0xcc,0xfe,0xbe,0xa1,0x29,0xf8,0x1c,0x5b,0x7f,0xc8,0xa5,0xd5,0xea,0x07,0x74,
+  0x71,0x28,0xe7,0x6d,0x39,0xf0,0x4f,0x4d,0xea,0x7c,0x58,0x8f,0x39,0xff,0x9e,0x5c,
+  0xf3,0x6f,0xd7,0xff,0x2c,0x66,0xd8,0xb4,0x8a,0xa6,0x68,0x9f,0x3a,0xea,0x8a,0xd5,
+  0x4d,0xd5,0x1f,0xc0,0x5f,0xb0,0x4c,0xeb,0xa5,0xfe,0x32,0x0b,0xff,0xe4,0x74,0xd4,
+  0xe9,0xf3,0x61,0x63,0x42,0x05,0x8b,0x5f,0xf3,0x84,0x22,0xfc,0x5a,0x17,0xd1,0x4a,
+  0xc7,0xb1,0x1a,0x69,0xfd,0xcf,0x32,0xf3,0xf9,0xbb,0xe5,0x6b,0x18,0xfe,0xe9,0x53,
+  0xe7,0x6f,0xa8,0x3a,0x0d,0x93,0x7b,0x3e,0x73,0xde,0x93,0xb3,0x3f,0x80,0xd5,0x9f,
+  0x44,0x2e,0xde,0x8d,0xa2,0x0e,0x8b,0x66,0x3f,0x61,0xf0,0x3f,0x66,0x07,0xe9,0xd7,
+  0x21,0xe3,0x7c,0x10,0xbd,0xe0,0x9c,0x36,0x11,0xfd,0x46,0x75,0xc9,0x78,0xd5,0x59,
+  0x6d,0x72,0x7b,0xcb,0x70,0x49,0x5f,0x8e,0xfe,0x36,0xf6,0xf3,0x61,0xa3,0xeb,0x37,
+  0x45,0x2b,0x1f,0x63,0xfe,0xe7,0x38,0x1c,0x88,0xd6,0x26,0xe5,0x46,0x74,0xa4,0x71,
+  0x0e,0x7b,0x72,0xf1,0x3f,0xda,0x5e,0x6d,0x87,0x5a,0xc9,0x69,0x6a,0x7a,0x80,0xed,
+  0x5e,0xf1,0x3c,0x14,0x7a,0xa0,0xc0,0x39,0xde,0xb4,0xde,0x46,0x2d,0xd3,0xb0,0xfb,
+  0x71,0xf4,0xea,0xa0,0x71,0x3e,0x23,0x56,0xc3,0xb1,0x1d,0x59,0xde,0xfe,0x00,0x6b,
+  0xcb,0xff,0x09,0x7e,0x87,0x85,0x62,0x18,0x1d,0xd0,0xbb,0x96,0xf0,0x7a,0x7f,0xc9,
+  0xe9,0x3f,0xed,0xe7,0xc3,0x8e,0x20,0xcd,0x1e,0xc2,0x5f,0xa5,0x09,0x21,0x4f,0x3c,
+  0x4a,0xe3,0x1f,0x5d,0x61,0x20,0x47,0xee,0xcd,0x4d,0xfb,0xd8,0xf8,0x9f,0x34,0xfe,
+  0xf9,0x6b,0x38,0x1c,0xf6,0xa5,0xe2,0x97,0x90,0x2f,0xfe,0xda,0xf0,0x0f,0x1e,0x0b,
+  0xe2,0x0b,0xa7,0xd2,0x34,0x7f,0x9d,0xfb,0x7e,0xbb,0xfe,0x07,0x94,0xc3,0xb2,0xaa,
+  0xd5,0x04,0xc9,0x4b,0xb4,0x57,0xf5,0x0c,0xe0,0xc1,0xe8,0xb2,0x79,0x42,0x4d,0x36,
+  0xff,0x43,0x8b,0x79,0x7f,0x12,0xad,0x04,0xcf,0xcb,0x9b,0x54,0x97,0xf0,0xfe,0x33,
+  0x5d,0x13,0x55,0xce,0x46,0x34,0xf6,0xfe,0x48,0x43,0x38,0x28,0x3e,0x5e,0xec,0x86,
+  0x3d,0xe0,0x3d,0x2f,0x8e,0x26,0x27,0xcb,0x9c,0xf9,0x8b,0x5c,0xfa,0x9f,0x94,0xec,
+  0xf9,0xe5,0xed,0x55,0xcd,0xcc,0xa8,0x4f,0x7a,0x93,0x6c,0x1a,0x4f,0xa8,0x75,0xb2,
+  0xf7,0x15,0x5b,0x7f,0x6c,0xae,0xff,0xa1,0x77,0xd8,0xd0,0xce,0x76,0xf8,0x19,0x33,
+  0x6a,0x92,0xee,0x3d,0xe4,0x7d,0xed,0xa7,0xd1,0x9a,0x31,0x66,0xc4,0xd3,0xe7,0xc3,
+  0x66,0xe9,0x7f,0xf0,0xfc,0x2f,0x6c,0xd3,0xe7,0xae,0x24,0xba,0x42,0x41,0x95,0xdc,
+  0xd3,0x49,0x5d,0x0e,0xfd,0x4f,0x68,0x1d,0x36,0x9e,0xea,0x5f,0xb1,0x37,0x75,0x50,
+  0x88,0x3b,0xf6,0x90,0xd1,0x6f,0x9c,0x7d,0xbf,0x71,0x6b,0x3d,0x2c,0xe5,0xfc,0x8f,
+  0xd9,0x4f,0x0c,0x97,0x4d,0x05,0x4f,0xc4,0xd4,0xe1,0xc1,0xf7,0x63,0x80,0x1a,0x10,
+  0xef,0x90,0xb8,0xd0,0xf2,0x3f,0x71,0x27,0xff,0xc3,0x8c,0x13,0xa6,0x91,0x14,0x53,
+  0x47,0xcd,0xc6,0x9c,0xe7,0xc3,0x9a,0x22,0xab,0x14,0xd1,0x14,0x4d,0xc9,0xae,0x3c,
+  0xbb,0x44,0x5d,0xd1,0xd1,0x23,0x29,0x8e,0xfe,0xd8,0x99,0xfa,0x9f,0x68,0xca,0x28,
+  0x8e,0x11,0xfc,0x7e,0x1b,0xfa,0x8b,0x63,0xe2,0xff,0x9a,0x42,0xff,0xa3,0x30,0xe3,
+  0xb0,0xe1,0x88,0x74,0xa3,0xe0,0x41,0xb1,0xf5,0xc7,0xb6,0xf4,0x3f,0x56,0xda,0x6b,
+  0xb5,0x91,0x08,0xe3,0x7a,0x18,0xe5,0x91,0xd8,0x1c,0xec,0x8f,0xbd,0x21,0x5b,0xff,
+  0x83,0x68,0xa7,0x17,0x9a,0x46,0xdc,0x4b,0x0a,0x07,0x35,0x3c,0xaf,0xc7,0x13,0x14,
+  0x8f,0x80,0x1e,0x0b,0xaa,0xec,0xfd,0x6d,0xfd,0xb1,0xcb,0x9f,0x01,0xdb,0xf9,0xb9,
+  0x46,0x7f,0x6c,0x63,0x06,0x3e,0x30,0xcf,0x17,0x1e,0xb1,0xe7,0xbf,0x9c,0xfa,0x1f,
+  0xbe,0x4d,0xdb,0x63,0x74,0xb0,0xef,0x13,0x55,0x38,0x41,0x1b,0xc0,0x1b,0x75,0xd7,
+  0xe4,0xd5,0xff,0xd8,0x0c,0x43,0x28,0x58,0x89,0xe7,0x33,0xd6,0x55,0x9b,0xcf,0x57,
+  0xb5,0x1f,0xca,0x99,0xe8,0xce,0x32,0x4a,0x61,0x1b,0x9d,0xa3,0xba,0x2b,0x88,0x9a,
+  0xee,0xbf,0xe4,0xac,0xcf,0x0d,0xe8,0x3d,0x41,0x9e,0x8f,0x0e,0x98,0xcf,0xe7,0xe7,
+  0x0f,0x96,0x5a,0xe7,0xa3,0x25,0xcb,0x47,0xf0,0xfc,0xf7,0xf4,0xf9,0x20,0xde,0xdd,
+  0x16,0xec,0x71,0xfb,0xe1,0xa4,0xa1,0xff,0x59,0x9c,0x43,0xff,0x33,0x23,0x15,0x7d,
+  0x3a,0xd2,0x61,0x68,0x0c,0x2e,0x49,0x2d,0xe0,0xd5,0xa6,0xea,0x0f,0x50,0x90,0x2a,
+  0x7b,0x37,0xea,0xc1,0xdf,0x36,0x84,0xb2,0x91,0x2c,0xfd,0xcf,0xcc,0x28,0xd8,0xc2,
+  0xee,0x6b,0x66,0xfe,0x25,0x55,0x9f,0xae,0xda,0xf5,0x3f,0xd2,0x0d,0xf6,0xee,0x3d,
+  0x45,0x56,0x7d,0x6e,0x94,0x9c,0x87,0x7f,0xc4,0x13,0xe8,0x86,0xc8,0xbd,0x19,0xfa,
+  0x1f,0x67,0xf4,0x1f,0x4e,0x09,0x81,0x22,0xaf,0xc6,0x36,0xd6,0xce,0x5f,0xee,0xbf,
+  0xf9,0x08,0x71,0xe8,0x7f,0x78,0x1b,0x4c,0x33,0xda,0x16,0xa3,0x91,0x30,0x84,0x40,
+  0xd8,0x28,0xb2,0x59,0xf6,0x1c,0x11,0x1f,0x48,0xf3,0x3f,0x59,0x7a,0x98,0xa1,0xcc,
+  0xf8,0x3e,0x2d,0x2a,0x4e,0xa5,0xff,0x49,0x0b,0x81,0xc4,0x35,0xf4,0xa8,0x5a,0x17,
+  0x2a,0x8e,0x76,0xde,0x64,0xe9,0x0f,0xb3,0xf4,0x3f,0x56,0x7f,0xa4,0x99,0x5d,0xbe,
+  0x4a,0x14,0x02,0x29,0x72,0x17,0x99,0x6d,0xcd,0xbf,0x43,0xff,0x63,0x1a,0x12,0x67,
+  0x84,0xa6,0x93,0x65,0x5a,0x87,0x56,0xad,0x15,0x29,0x24,0x34,0x85,0xfe,0x67,0x3b,
+  0x33,0x9e,0x30,0x19,0x36,0x9c,0x58,0x36,0xc3,0x85,0xb9,0xcf,0x87,0xb5,0x0c,0x6c,
+  0x8b,0x84,0x0c,0x9e,0x82,0x1d,0xd1,0x99,0xc7,0x58,0x6b,0xcb,0x7f,0x4d,0xd1,0x2f,
+  0x62,0x80,0x7c,0x00,0x87,0xb4,0x12,0xc5,0x91,0xff,0xca,0xd2,0xff,0x98,0x06,0xf0,
+  0x3f,0xc4,0x62,0x58,0x49,0x67,0xb8,0x6c,0xf9,0xaf,0xdd,0x59,0x68,0xc7,0x66,0xf0,
+  0x46,0x91,0x31,0xe2,0x52,0xac,0xf5,0x90,0x43,0x7f,0x98,0x36,0x48,0x27,0xf8,0x75,
+  0x7f,0xd0,0xe5,0xb2,0xfc,0x8f,0x4d,0xff,0x93,0x0d,0x7b,0x4e,0xf1,0xef,0x97,0x41,
+  0x05,0xbf,0xb5,0xde,0xba,0xbb,0xbf,0xa2,0xd8,0xd0,0xce,0xb5,0x0e,0xd8,0x73,0x1c,
+  0x7e,0x49,0x17,0x27,0x3d,0x8b,0xc5,0x1a,0xf3,0xf5,0xb3,0xf5,0x3f,0x39,0x0d,0xdb,
+  0xf9,0xb0,0x66,0x7f,0x00,0xb3,0x2d,0xd2,0xaa,0xf1,0x19,0x57,0xe4,0x54,0xfe,0x22,
+  0x9d,0xff,0x4a,0xf3,0x6f,0xca,0x63,0x9a,0xfd,0xb5,0xf1,0x34,0x10,0xc4,0x3f,0x46,
+  0xa3,0xa7,0xf0,0x81,0x0a,0x03,0xff,0xa4,0xcf,0x87,0xa5,0x39,0xfc,0x15,0x03,0x42,
+  0xce,0xc6,0x50,0xf6,0xfe,0xd8,0xd9,0xfa,0x1f,0x34,0xf8,0x09,0x50,0x2f,0x21,0xf5,
+  0x71,0x9e,0x45,0xfc,0x4c,0xfd,0x8f,0x35,0x3a,0x0c,0x64,0xa5,0xc8,0xf0,0xf0,0x88,
+  0xf3,0x3e,0x4c,0x74,0xdd,0x3d,0xe4,0x7d,0xd6,0xde,0x1f,0x3b,0x53,0xff,0xb3,0x35,
+  0x3e,0x03,0x8d,0xd9,0xfc,0x0a,0xfd,0x50,0x66,0xc0,0x60,0x5f,0x0e,0xfd,0x8f,0x3d,
+  0xfa,0xdb,0xae,0xb4,0xc0,0x42,0xdd,0x63,0xc7,0x3f,0x3b,0x32,0xf9,0x1f,0x77,0xbc,
+  0x70,0xd4,0x3a,0x31,0x44,0x4a,0x75,0x2c,0x74,0xea,0x7f,0x32,0xee,0xf7,0x39,0xf0,
+  0x8f,0x2f,0xe3,0x7c,0x90,0xb4,0xfe,0x87,0xcf,0x0f,0x6f,0x8b,0x44,0xcd,0x46,0xbe,
+  0x32,0xef,0xe8,0x92,0xa1,0x7f,0x96,0xd3,0xe3,0x15,0xee,0x1e,0x5c,0xb5,0xbf,0x75,
+  0x0f,0xea,0x9f,0xf9,0x15,0x6d,0xa2,0xbd,0xee,0xd5,0x2d,0x76,0xfc,0xb3,0xb3,0xdc,
+  0x89,0xee,0x5e,0xea,0x39,0xd7,0xf9,0x1e,0x3f,0x31,0x16,0xaf,0xf0,0x46,0x49,0xf9,
+  0xce,0x47,0xbb,0x43,0xb0,0x16,0xd2,0xdf,0x4d,0x51,0xff,0x75,0xb6,0x28,0x83,0xed,
+  0xb9,0x6a,0x6a,0xfe,0x27,0xbd,0x0c,0x2a,0xd2,0x03,0x27,0xeb,0xf2,0xf2,0x3f,0xe9,
+  0xfc,0x97,0xf4,0x07,0xf0,0x3f,0xd8,0x1f,0xfb,0xb0,0x89,0x96,0x0d,0x21,0x74,0x8e,
+  0xfa,0xa3,0x3c,0xfd,0xb1,0xf3,0xf3,0x3f,0xf9,0xf3,0x5f,0xc6,0x36,0x24,0xa3,0x5f,
+  0x59,0x8e,0xfe,0xd8,0xfb,0xec,0xaf,0x3d,0xf5,0xf9,0xb0,0xd9,0xdf,0x8b,0xc1,0x57,
+  0x14,0xe6,0xe6,0x7f,0x6c,0xdd,0x20,0x0d,0x03,0xf9,0x90,0xe2,0xbc,0xfc,0x0f,0x3f,
+  0x1f,0x0d,0xd9,0x9e,0xe3,0xfa,0x87,0x94,0x97,0x7d,0x9d,0xd5,0x7f,0x1d,0xcf,0x5f,
+  0xff,0xf5,0x87,0xcc,0x4f,0x8e,0xfe,0xd8,0x8b,0xc5,0x29,0x1c,0x57,0xce,0xfc,0xd7,
+  0xac,0xfc,0x8e,0xd4,0x9e,0xff,0xb2,0xf2,0x7d,0x99,0x42,0xe8,0xdc,0xfc,0x4f,0x99,
+  0xd5,0x16,0xdb,0x93,0xdf,0xb1,0xe7,0xea,0x8f,0x4d,0xb2,0x1a,0x65,0xe7,0xe2,0x7f,
+  0x1c,0xf9,0xaf,0xc5,0xe9,0x78,0x54,0x9b,0x97,0xff,0x49,0x45,0x37,0x3c,0xf6,0x1d,
+  0xd3,0x5e,0xee,0x4f,0xe2,0x7f,0xb2,0xf4,0xcf,0x53,0xf7,0x87,0xb4,0xf7,0x47,0x9a,
+  0xa2,0x3f,0xa4,0xb9,0x1e,0x9c,0xfd,0x91,0xf2,0x19,0x39,0xf3,0x5f,0x38,0xba,0xd9,
+  0xb9,0xf5,0x3f,0x79,0xcf,0x47,0xcb,0x63,0x38,0xf3,0x5f,0xaf,0x19,0x30,0xe9,0x3c,
+  0x87,0x85,0xc5,0x46,0x5b,0xec,0x0c,0xfe,0x27,0x8d,0x7f,0x8c,0xfc,0x17,0xa7,0x7d,
+  0x48,0x37,0xc7,0x3f,0x2e,0x35,0x65,0xe4,0x39,0x1f,0x36,0xcd,0x6e,0x61,0x37,0xa4,
+  0x22,0x2e,0xf3,0x9e,0x8a,0xff,0xb1,0xb7,0x79,0xb1,0x60,0xcf,0x54,0xe7,0xc3,0x1a,
+  0x22,0x6d,0x62,0xc0,0xda,0x22,0x2e,0x6b,0xcf,0xcf,0xff,0xd8,0xf1,0xcf,0x6b,0x79,
+  0xf9,0x9f,0xbc,0xe7,0xa3,0x99,0x46,0x43,0x5e,0xfd,0x4f,0x2a,0xff,0xb5,0x9b,0x24,
+  0x0c,0x23,0x6c,0x1a,0xf9,0xcf,0x87,0xc5,0x8f,0xa2,0xc2,0xfc,0x3a,0xd4,0x74,0xbc,
+  0xb6,0xe9,0x7f,0xd2,0xfc,0x4f,0xea,0xb3,0xbd,0x25,0xf5,0xb5,0x8a,0xe1,0x9c,0xfa,
+  0x1f,0xf3,0xf9,0xbc,0x3f,0x76,0xc7,0x8d,0x67,0x30,0xed,0x05,0x1f,0x47,0x18,0xec,
+  0x59,0xcb,0xf1,0xcf,0x67,0x50,0xff,0x9c,0xe7,0x7c,0x58,0x0e,0x03,0xa2,0xa6,0xf7,
+  0x88,0xf1,0xc0,0x97,0x81,0x7f,0x1c,0xe7,0xc3,0xa6,0xf2,0x5f,0x67,0xe5,0x7b,0xd0,
+  0x18,0x11,0xf1,0x7c,0xd8,0x25,0x8e,0xfe,0x90,0x7a,0x66,0xfe,0x6b,0xc0,0xdd,0xce,
+  0xbc,0x07,0x1f,0x5d,0x98,0x94,0xd0,0xcc,0xf7,0xcf,0x91,0xff,0x6a,0xbf,0x2a,0x65,
+  0x18,0x85,0xab,0xf3,0xf4,0x9e,0x3c,0xf8,0x87,0xd3,0x3e,0x7c,0x1b,0x2b,0x18,0xf3,
+  0xe9,0xca,0x76,0x44,0xce,0xf3,0xd1,0x78,0xd8,0x8a,0x8a,0xc6,0xc0,0xff,0x22,0x16,
+  0x0a,0x28,0x13,0xd2,0x35,0x6c,0x98,0x7f,0x6a,0xd3,0xff,0x98,0xef,0x63,0xf5,0xc7,
+  0x76,0xcc,0x4f,0x46,0x05,0x50,0xae,0xfc,0xd7,0x10,0xf7,0xde,0x4b,0x70,0x9b,0x3f,
+  0x35,0xff,0x93,0xc2,0x3f,0xd1,0xd2,0x54,0xb4,0x8a,0xd9,0x03,0xd9,0xbb,0xb9,0xf4,
+  0x3f,0x4e,0xfd,0x73,0xec,0x13,0xf8,0x1f,0x8f,0xa1,0xb6,0x52,0x42,0x83,0x46,0x22,
+  0x8c,0xad,0xb7,0xca,0xd4,0x46,0x75,0x90,0x2b,0x64,0xb2,0xea,0xbf,0xde,0xd5,0xf8,
+  0x78,0xdf,0xc3,0xec,0xe7,0x90,0x3b,0xf6,0xa7,0xef,0x9d,0x60,0xc6,0x40,0x3e,0xfe,
+  0x27,0x3d,0xde,0x24,0x43,0x3b,0xc7,0x8c,0x42,0x66,0x53,0xff,0xf3,0x7e,0x2e,0xfd,
+  0xcf,0xfb,0x19,0x68,0xf9,0x2c,0xbc,0x1e,0x31,0x80,0x90,0xfc,0x5c,0x0e,0xfc,0x93,
+  0x85,0x76,0x4c,0xa3,0x34,0x0f,0xfe,0x79,0x3c,0x4f,0x7c,0x9f,0x1a,0xff,0x84,0x46,
+  0x61,0x89,0x94,0x32,0x8c,0x2b,0x90,0x07,0xff,0xbc,0x6b,0xe7,0x67,0xec,0x34,0x69,
+  0x5e,0xfc,0x73,0x9d,0x33,0xac,0x2b,0x7f,0x2c,0xfe,0x99,0x2a,0xff,0x95,0x85,0x87,
+  0xc9,0xa8,0x62,0xbf,0xd2,0xff,0xc9,0xf8,0x47,0xa9,0x9f,0x2a,0xff,0x95,0x0d,0x03,
+  0xa8,0x01,0x84,0x42,0x78,0x62,0xc8,0xfc,0x33,0x22,0xc3,0x3f,0xd6,0xfe,0xce,0x3a,
+  0x1f,0xc4,0x2c,0x7b,0x7f,0x99,0x27,0xc2,0x52,0x27,0xc6,0x2a,0x78,0x50,0xc8,0xb4,
+  0xa9,0xf0,0x4f,0x8a,0x36,0x54,0x3e,0x11,0xff,0xe4,0x9e,0x9f,0xbf,0xcb,0x85,0x7f,
+  0xde,0x72,0x7a,0x9b,0x50,0x96,0xff,0xf4,0x4d,0xa5,0xff,0xe1,0xc3,0x9c,0x12,0xff,
+  0x64,0xaf,0xb7,0xde,0x0c,0x3c,0xe9,0xc4,0x3f,0x0e,0xfd,0x8f,0x3b,0x97,0xe1,0xc4,
+  0x3f,0x23,0xb9,0xf7,0xe3,0x53,0xe3,0x9f,0x29,0xf1,0xc0,0x27,0xe2,0x1f,0xe1,0x8f,
+  0xc4,0x3f,0xd2,0x7f,0x10,0xfe,0x31,0x8d,0x42,0xab,0xf0,0xed,0x93,0xf0,0xcf,0x75,
+  0x59,0xe3,0xbd,0x6e,0x2a,0xfd,0x8f,0x69,0x60,0x63,0xc0,0xd6,0xdc,0xf9,0x2f,0x21,
+  0x83,0xff,0xe1,0xfa,0x9f,0x3b,0xf2,0xe8,0x9f,0x33,0xce,0x07,0xc9,0x3b,0xde,0x7c,
+  0xfa,0x9f,0xa5,0x9f,0x94,0xff,0x2a,0xb7,0x9a,0x60,0xa7,0xdf,0x5f,0xba,0x00,0x73,
+  0xff,0x10,0xfc,0x63,0x33,0x4a,0xfe,0x48,0xfc,0xd3,0xfc,0x49,0xf8,0x27,0x8b,0xff,
+  0x11,0xa7,0xc6,0x3f,0x53,0xe6,0xdf,0xf3,0x9f,0x0f,0x9b,0xc3,0xe8,0x59,0xef,0x9b,
+  0xe2,0x7c,0xd8,0x5c,0x86,0x30,0x85,0xfe,0x27,0x37,0xff,0xe3,0x38,0x1f,0xc4,0x91,
+  0xbf,0x30,0x0e,0xba,0x32,0x03,0xd9,0x44,0x14,0x1b,0x65,0xcf,0xc8,0xc2,0x3f,0xe6,
+  0xdb,0x06,0x92,0xb3,0xef,0x22,0xa7,0x84,0xb7,0x8c,0x63,0x4d,0x4e,0xeb,0x07,0x3e,
+  0x51,0xff,0xb3,0xe2,0x9b,0x85,0xf6,0xf1,0xaa,0x19,0xfa,0x1f,0x35,0x53,0xff,0xe3,
+  0xb2,0x85,0xf5,0x3c,0xf8,0x27,0x63,0x74,0x55,0x19,0x8c,0x90,0x3b,0x27,0xfe,0x31,
+  0xef,0x2f,0x31,0x85,0xaf,0x46,0x46,0x2c,0x2f,0xfe,0xc9,0xd8,0xc6,0x2e,0xf9,0x24,
+  0xfc,0x33,0xa5,0x7e,0x23,0xff,0xf9,0xb0,0x4e,0x43,0xc8,0x8d,0x7f,0x9c,0xfc,0x4f,
+  0x64,0xd0,0x40,0x44,0xc1,0x3a,0x06,0x84,0xaa,0x32,0xfb,0x43,0x16,0xaf,0x73,0x8c,
+  0xf7,0x05,0xef,0x3e,0xf1,0xbd,0xb6,0x94,0xfe,0x76,0x94,0x4e,0xc8,0x99,0xfd,0x21,
+  0xaf,0xcd,0x31,0x5e,0xa4,0x7d,0xcc,0x2b,0xf7,0xe8,0xd7,0x39,0xf1,0xcf,0x45,0x6d,
+  0x30,0xba,0xa8,0xda,0x73,0x54,0xac,0x63,0x46,0xbd,0xea,0x39,0x21,0x5e,0x92,0x26,
+  0xa1,0x1e,0xdb,0x8a,0xe6,0xe4,0x7f,0x46,0x90,0x64,0x96,0xf1,0xb4,0x38,0xda,0x8d,
+  0xa7,0x51,0x6f,0x27,0xef,0xc8,0x87,0x33,0x1a,0x01,0xd9,0xfb,0xff,0x74,0x77,0x53,
+  0x9f,0x0a,0x32,0x31,0xda,0x57,0x91,0x22,0x48,0x09,0x33,0x64,0xc7,0xf7,0x65,0xae,
+  0x1f,0xbd,0x7c,0xc4,0xac,0x66,0x0d,0x73,0xa3,0x88,0x92,0x51,0xf9,0x70,0x85,0xb3,
+  0x11,0xd0,0xb8,0xad,0xfe,0x6b,0x94,0x1c,0xa5,0xfb,0xc2,0x81,0xed,0xee,0xb9,0xdc,
+  0x98,0xcf,0x27,0x8a,0xee,0x73,0x34,0xea,0x49,0xd7,0x7f,0xc5,0x84,0x67,0xa4,0xcb,
+  0xd1,0x25,0x6b,0xb6,0xbe,0x26,0x3e,0xad,0x5d,0x8e,0xb6,0xac,0x29,0x19,0xab,0xba,
+  0xa8,0x7d,0x48,0xf3,0xd5,0x7f,0xe9,0xca,0xcf,0xe0,0x42,0xac,0x39,0xec,0xdd,0x2e,
+  0xf2,0x36,0xb6,0x61,0x63,0x3f,0xd2,0x5e,0x97,0x17,0xff,0xd4,0xc2,0x41,0xbd,0x36,
+  0xec,0xde,0x4e,0xde,0x84,0x83,0x94,0x19,0x31,0xc4,0x3f,0xba,0x9a,0x87,0xff,0xd1,
+  0x0b,0xd6,0x66,0xf8,0x2b,0x74,0xcb,0xfb,0x92,0xce,0xc6,0x35,0x76,0xfc,0x73,0x0d,
+  0x3c,0x1d,0x9d,0x1f,0x73,0xaf,0x25,0x27,0xe1,0x69,0xca,0x0c,0xd4,0x3f,0x3f,0xcd,
+  0x2b,0xa4,0x72,0xd6,0x7f,0xc9,0xb2,0x76,0x4e,0x69,0xa2,0x5e,0x55,0x4c,0xc0,0x39,
+  0x60,0x06,0x88,0x03,0x0c,0x08,0xc5,0xf5,0x7c,0xfc,0x4f,0x1f,0x5c,0x51,0x5a,0xba,
+  0xbc,0x67,0xc4,0x71,0x8d,0x1b,0x47,0xf9,0x7a,0xc8,0x87,0x7f,0xfc,0x98,0xff,0x32,
+  0xda,0x62,0xdf,0x81,0x6d,0xb1,0x93,0x9e,0xb8,0x7b,0x2e,0x24,0xa8,0x73,0x7e,0xd2,
+  0xf5,0x7d,0x23,0xdc,0x9f,0xa4,0xea,0xbf,0x8c,0x63,0x61,0x49,0x05,0x74,0x19,0xc7,
+  0x4c,0xe7,0xea,0xff,0xa3,0xfc,0x70,0xfa,0x81,0x48,0x25,0xca,0x7e,0xf0,0x7c,0x10,
+  0x66,0x8c,0x90,0x42,0xe8,0xa0,0xb7,0xe5,0x3d,0x1f,0x64,0x8b,0xb9,0xba,0x8c,0x6c,
+  0x97,0x1c,0x23,0x1e,0xd2,0xb1,0x2d,0x96,0x9a,0x4f,0x29,0x85,0x7f,0xcc,0xfb,0x93,
+  0xe5,0x4f,0xc0,0x45,0x6d,0x5f,0x34,0xb0,0xcb,0x3d,0x8f,0x1c,0x43,0xe3,0x49,0xb2,
+  0x18,0x8e,0x43,0x9d,0x89,0x88,0xee,0xce,0xea,0xff,0xa3,0x8e,0xcb,0x78,0x4c,0x79,
+  0x67,0xca,0xd0,0xad,0x30,0xd4,0x9a,0x1f,0xff,0x2c,0x33,0xf8,0x1f,0x1e,0xdd,0xaa,
+  0x8c,0xb6,0x3f,0x9e,0xfc,0xf8,0x47,0xab,0x5d,0xef,0x7e,0x2c,0xdd,0x16,0x7b,0x0e,
+  0x33,0x02,0x0e,0x45,0x8a,0x13,0xff,0xfc,0x1c,0x16,0x68,0xee,0x21,0x72,0xde,0x34,
+  0xd6,0x70,0xd9,0x33,0xde,0x2f,0xe7,0xc4,0x3f,0x4f,0xd1,0xf9,0x61,0xb6,0x6c,0x7e,
+  0x63,0x18,0x43,0xd8,0x16,0xdb,0x1f,0x30,0xce,0x87,0xcd,0xae,0xff,0x2a,0x08,0xc3,
+  0x18,0xca,0xbc,0x81,0x6d,0xa2,0xb9,0xa1,0x8b,0x61,0x8a,0x8d,0x47,0xec,0x42,0x94,
+  0xd3,0xf6,0xfc,0x17,0xaf,0x76,0xf7,0x3e,0xd4,0x69,0x18,0xab,0x14,0xf1,0x3c,0x9e,
+  0x97,0x97,0x97,0xff,0xc1,0x5f,0xeb,0x97,0x71,0xfe,0xe7,0xb2,0xd2,0x82,0xd3,0x52,
+  0x0d,0x17,0xfc,0x8b,0xf2,0xeb,0x7f,0xd4,0x3e,0xd9,0x07,0xee,0x48,0x24,0x49,0xfb,
+  0xd4,0x5a,0xe2,0xa7,0x44,0x6d,0x7b,0x46,0xf3,0xe5,0xab,0xff,0x2a,0x18,0xa0,0x7b,
+  0xd9,0xb2,0xee,0x29,0x25,0x03,0xb1,0xbd,0x6a,0xa0,0xcd,0xb5,0x9a,0x5c,0x25,0x3f,
+  0x45,0x55,0x07,0xfe,0x71,0xf4,0xff,0x61,0x17,0x77,0x9a,0x68,0x27,0xa0,0xb9,0xa2,
+  0xae,0xfd,0x6c,0x62,0x9d,0xc2,0xaa,0x37,0x33,0xf2,0x5f,0xbe,0xf4,0xdb,0x96,0x28,
+  0xe2,0x1c,0xb8,0xa0,0xed,0xcb,0x83,0x7f,0x46,0x32,0xf1,0x4f,0xb1,0xad,0x0d,0x54,
+  0x8e,0xfa,0x2f,0x7e,0x3e,0x08,0x36,0xd9,0x88,0xa4,0x67,0x5b,0x85,0x41,0x3c,0x16,
+  0x36,0x1f,0xfe,0x91,0xcf,0x42,0x55,0xd4,0x3d,0x4c,0x50,0xa4,0xbe,0x20,0xe6,0xde,
+  0x45,0xfc,0x10,0x81,0xaa,0xbc,0xf5,0x5f,0x2b,0xa1,0xca,0xd6,0x26,0x2b,0xe9,0x6a,
+  0x20,0x25,0x10,0xa1,0x2a,0xcd,0x5d,0xff,0x15,0x83,0x5b,0xe0,0x47,0x50,0xa9,0xb9,
+  0xdb,0xc9,0xab,0xf2,0x53,0x30,0x3f,0xc4,0xbe,0xd6,0xeb,0xe0,0x5e,0xad,0x92,0xe6,
+  0xae,0xff,0xda,0xdd,0xfd,0x15,0x38,0x4b,0x17,0xc6,0xbc,0x6b,0xc5,0x93,0x78,0x3e,
+  0x08,0xb6,0xfd,0x71,0x91,0xe7,0xe9,0xde,0x58,0x9e,0xfa,0xaf,0x22,0x9c,0x9f,0x67,
+  0x29,0xaf,0xff,0xe2,0xa3,0x0b,0xba,0x51,0xf1,0x62,0xf5,0xb7,0xc9,0x81,0x7f,0xde,
+  0x8f,0xb6,0x24,0x1f,0xc0,0xfa,0xe5,0x97,0x51,0xb6,0x31,0x22,0xfe,0x58,0x1e,0x8c,
+  0xde,0x18,0x0b,0xe4,0xcc,0x7f,0x3d,0x31,0x7d,0x3f,0x6c,0xa4,0x0b,0x34,0xb9,0x9d,
+  0x5c,0xa5,0x6f,0xd4,0x2a,0x87,0xdc,0xe1,0x9d,0x57,0xe9,0x5d,0xe9,0xfe,0x3f,0x19,
+  0xe7,0x83,0x20,0xfe,0xf9,0xb1,0x3a,0x07,0x0f,0x6d,0xac,0x80,0xef,0xc1,0x1c,0xea,
+  0xbe,0x0d,0xcf,0xc3,0xa5,0xce,0xfe,0x3f,0x76,0xfc,0xc3,0x69,0x46,0x8c,0x56,0x2a,
+  0x6c,0x87,0xb9,0xd4,0x5d,0x1d,0x11,0xf0,0x8a,0xa3,0xff,0x8f,0x33,0xff,0xf5,0xae,
+  0x34,0x97,0xc1,0x18,0x12,0x40,0x75,0x84,0xee,0x9d,0x25,0x3e,0x80,0x1d,0xe7,0xa8,
+  0x3d,0x7e,0xd9,0xeb,0xbf,0x38,0x5e,0xd2,0x38,0xff,0xf3,0xae,0xd6,0xd8,0xbe,0x35,
+  0x3a,0xed,0xac,0x41,0x53,0x3b,0xf8,0x1f,0xf3,0xfd,0x05,0xe5,0x59,0xb8,0x12,0x6d,
+  0xa1,0xc5,0x49,0xd2,0xc4,0xe6,0xa7,0x4a,0xf7,0x0c,0x89,0x8b,0xfd,0x2f,0x43,0x0b,
+  0x75,0xe7,0xac,0xff,0x62,0xf8,0x47,0x63,0x41,0x1c,0x93,0xa4,0x01,0xe8,0xe9,0xe2,
+  0xc2,0x42,0x3f,0xe6,0x2f,0x3a,0xa6,0xc2,0x3f,0x7e,0xbd,0x28,0x4e,0x7e,0x06,0x3f,
+  0x55,0x6b,0x74,0xb9,0xbb,0xb4,0x1a,0xf0,0x3c,0xd9,0x29,0xf8,0x1f,0x99,0x77,0xdf,
+  0x7a,0x80,0xc1,0xc2,0xb5,0xba,0x0c,0x44,0xda,0x42,0xe5,0x40,0x77,0x9e,0xfa,0x2f,
+  0x86,0x7f,0x2e,0xaa,0x8d,0x78,0xda,0xe9,0x96,0xe8,0xef,0xb0,0xed,0x0c,0x15,0x54,
+  0x38,0xaa,0x3a,0xc7,0xeb,0xc0,0x3f,0xca,0x84,0x31,0xa8,0x75,0x1a,0x9e,0x2e,0xe7,
+  0xd5,0xc4,0x21,0x8d,0x7d,0x56,0x5d,0xf9,0xeb,0xbf,0x26,0x23,0x46,0xfd,0x97,0x92,
+  0x99,0x36,0xcd,0x9d,0xff,0x72,0xf4,0xff,0x39,0x93,0x32,0xe6,0xe2,0x95,0x3b,0xa6,
+  0xcc,0x7f,0x39,0x13,0xa3,0xfd,0xd6,0x41,0x3c,0x3d,0xb9,0xf9,0x9f,0x9b,0x4c,0xf4,
+  0x18,0x32,0xdb,0x28,0xdd,0xb4,0x2e,0x9b,0xff,0x51,0xa7,0xa7,0xeb,0xbf,0x94,0x09,
+  0xa9,0xc1,0x89,0x9f,0xa5,0x94,0x90,0xcc,0x51,0xff,0x95,0xc5,0xf6,0xfc,0xf1,0xf9,
+  0x2f,0x0b,0x78,0x4f,0xc1,0xff,0x08,0xc6,0x40,0x4a,0x9c,0xc0,0x58,0xc8,0xc2,0x3f,
+  0x59,0xfb,0x2f,0x18,0x94,0xea,0xa5,0xd4,0xc6,0x21,0x17,0xff,0x23,0x18,0x41,0xdf,
+  0xe8,0xff,0x33,0xe2,0x72,0x12,0x41,0x1d,0x5f,0xcf,0xc4,0x3f,0x6c,0xbd,0x09,0x4d,
+  0xfd,0xab,0x82,0x7f,0x6a,0xd4,0x7f,0x79,0x17,0x8b,0xd8,0xd2,0xb5,0x49,0x2f,0x09,
+  0x0a,0xc7,0xa3,0x1f,0xd2,0xa6,0xd1,0xac,0xfc,0xd7,0x44,0x3a,0x4d,0xdc,0xac,0x4f,
+  0xfb,0x60,0xc6,0x25,0xb8,0x47,0x30,0xe6,0x47,0x4b,0x11,0x41,0x9f,0xc8,0xff,0x10,
+  0x73,0xfe,0x85,0x66,0x7d,0x55,0xbc,0x35,0x7f,0xfd,0x57,0xff,0x27,0xe6,0xbf,0xcc,
+  0xb4,0xd7,0x4d,0xe9,0x61,0xf2,0x19,0x98,0x69,0xe7,0x7f,0xd2,0xf5,0x5f,0x65,0x83,
+  0x12,0x4e,0xda,0x8a,0x1c,0xdb,0x58,0xdf,0x94,0xf9,0xaf,0x1c,0x69,0xaf,0x4f,0xca,
+  0x7f,0xd9,0x84,0x40,0xb3,0xff,0x63,0xf9,0x9f,0xff,0xd8,0xfc,0x97,0xf2,0x47,0xf3,
+  0x3f,0x19,0xc6,0xd9,0x7f,0x57,0xfe,0xcb,0xb8,0xd8,0x6a,0xbf,0x4d,0xca,0xec,0xa8,
+  0x93,0x91,0xff,0x4a,0xa3,0x9d,0x22,0x6e,0x14,0x18,0x57,0xa4,0x3f,0x94,0xff,0x11,
+  0x9c,0x85,0xff,0x53,0xd4,0x7f,0x19,0x65,0x5f,0x70,0x47,0x3e,0xfe,0x27,0xb3,0xfe,
+  0xeb,0x93,0xf4,0xcf,0xf0,0x87,0xdc,0x3f,0x45,0xfd,0xd7,0x27,0xf1,0x3f,0xa9,0xfa,
+  0x2f,0x3b,0xdb,0x33,0x22,0x35,0x0a,0x19,0xfa,0xe7,0x74,0xff,0xc3,0xbc,0xfc,0x8f,
+  0x18,0xd4,0x72,0xf0,0x3f,0x59,0xf5,0x5f,0x39,0x8d,0x3c,0xf5,0x5f,0x79,0x8d,0x5c,
+  0xfc,0x4f,0x8e,0x32,0xf0,0x1c,0xf8,0x47,0x2b,0xc8,0x8e,0x56,0x48,0xfb,0xe4,0x8b,
+  0x5f,0x99,0xfc,0xcf,0x08,0x1b,0x1d,0x73,0x9b,0xfb,0xf9,0x15,0x14,0x46,0x06,0x74,
+  0x47,0xff,0xc3,0x4c,0xfe,0x27,0x61,0xe8,0x7f,0x54,0xa7,0xfe,0x27,0xbd,0xbf,0xcb,
+  0xa8,0xff,0xaa,0xcd,0xcd,0xa7,0xa5,0xf1,0x4f,0x56,0xfd,0x57,0x4a,0xe8,0xd2,0xd0,
+  0x6f,0xbf,0x72,0x3a,0x3f,0xff,0x63,0x13,0x7e,0x4c,0x9b,0x2a,0xff,0x65,0xd2,0x3e,
+  0x1e,0x6e,0x48,0xbc,0xec,0xeb,0x92,0x72,0x8f,0xf1,0x53,0xbe,0xfa,0x2f,0x52,0xa2,
+  0x17,0xe7,0x12,0xf6,0xe4,0xaa,0xff,0x2a,0x4c,0xd5,0x7f,0x7d,0x82,0xfe,0xd9,0x76,
+  0x3e,0x88,0x84,0xf3,0x53,0xc4,0x69,0x1f,0xd9,0x9c,0x1f,0x81,0x17,0xc2,0x3b,0xeb,
+  0xbf,0x6c,0xd9,0xbd,0xc6,0x53,0x9e,0xa7,0x90,0xf6,0x51,0x79,0xfc,0x7d,0x4f,0x9b,
+  0x68,0x6f,0xc6,0x83,0x83,0x6d,0xfd,0x7f,0x9c,0xfc,0x4f,0xf3,0x60,0x06,0x11,0x04,
+  0x86,0xfe,0xe7,0x2a,0x73,0x3d,0x1c,0x29,0x40,0xd8,0xd3,0x9b,0xf4,0x26,0xd8,0xfe,
+  0x8b,0xe1,0xe7,0x30,0xfb,0xb5,0x76,0x0a,0xfc,0xa3,0xf3,0xfc,0x97,0xef,0x8c,0xbb,
+  0x3b,0xf4,0x26,0xef,0xff,0xec,0x5e,0x88,0x07,0xb9,0xe6,0xd5,0xff,0x24,0x0a,0x8c,
+  0xfd,0xb8,0x1b,0xd8,0xd7,0xf7,0x30,0x57,0x9f,0xfa,0xb2,0xf3,0xa1,0x69,0xfe,0x27,
+  0xa9,0xec,0xe1,0xa2,0x29,0xe6,0xc4,0xce,0xc2,0x0f,0x54,0xdf,0x80,0x3b,0x16,0x09,
+  0x28,0x99,0xf3,0x69,0xeb,0xff,0xcc,0xf5,0xb7,0x75,0x3a,0x0b,0x43,0x6f,0x92,0xd7,
+  0x60,0x9f,0xee,0xdd,0xef,0x0e,0x64,0xd7,0x7f,0x59,0xf8,0x76,0x2f,0x3c,0x23,0xa5,
+  0xf2,0x83,0xe7,0x81,0x37,0xba,0x59,0x9f,0xab,0xff,0x8f,0x15,0x4f,0xc7,0xc0,0x58,
+  0x9f,0xd7,0x75,0xb3,0xcf,0xea,0x28,0x65,0x4f,0xeb,0x16,0x03,0x59,0xf5,0x4d,0xce,
+  0xfe,0xcf,0xbd,0x46,0x1a,0x74,0x10,0x7e,0xc5,0x8c,0x9e,0x0e,0x12,0x50,0x5f,0xcf,
+  0x5b,0xff,0xa5,0x9b,0x7c,0x20,0xd2,0x62,0x1d,0x12,0x76,0x5b,0x75,0x95,0x64,0x1d,
+  0x6c,0x9a,0xee,0xff,0x33,0xa4,0x60,0xfe,0x8b,0x81,0x9c,0x36,0x72,0x85,0x7c,0xd7,
+  0x88,0xfe,0xd7,0x75,0x3c,0x12,0xcb,0xd7,0xff,0xc7,0xcc,0x7f,0xb9,0xa1,0xf5,0x25,
+  0xe8,0xe7,0x8d,0x10,0xab,0x6a,0xe1,0x79,0x7b,0xff,0x9f,0xad,0x8e,0xfe,0x3f,0x65,
+  0x7b,0x38,0x68,0xd9,0x4a,0xd9,0xaf,0x17,0x14,0x36,0xba,0x7d,0xee,0x1c,0x7a,0x2a,
+  0x27,0xff,0x83,0x6c,0x64,0xb7,0xb8,0x05,0x65,0x0f,0xf8,0x6b,0xad,0xd2,0x03,0x4d,
+  0x49,0x7b,0x45,0x9e,0xad,0xff,0xb3,0x95,0x4f,0x27,0xb3,0xd8,0x46,0x92,0xcb,0x9e,
+  0x9b,0xe0,0x27,0xcc,0xf0,0xe7,0xe6,0x7f,0x10,0xff,0x74,0xcc,0x4b,0x76,0x26,0xc8,
+  0xb3,0xb8,0xed,0x4a,0xba,0x6f,0x45,0x22,0x28,0x32,0x3f,0x29,0xe7,0xee,0xff,0x93,
+  0xd2,0x1f,0xce,0xac,0x26,0xc5,0xf2,0x8e,0x28,0x43,0xd7,0x0a,0xf1,0xc0,0xe3,0x92,
+  0x59,0xd8,0x22,0xf0,0xf9,0x3c,0x69,0x3d,0x5f,0x97,0x76,0xf3,0xb2,0x2f,0xef,0x6f,
+  0xc5,0x83,0x7c,0xdb,0xe5,0x1d,0x71,0xfb,0xe1,0x08,0x33,0x3c,0x79,0xfa,0x3f,0x9b,
+  0xf1,0x08,0xf9,0x9f,0x3f,0x20,0xff,0x95,0x8e,0x77,0x03,0x70,0x94,0x34,0xb3,0x68,
+  0xeb,0xae,0xce,0x2a,0x04,0xcb,0x3e,0x1f,0x6d,0x26,0x9e,0xcf,0xfe,0x9a,0xa9,0x3f,
+  0x79,0x3b,0x83,0x7f,0xb0,0xe1,0x1f,0xa8,0x96,0x78,0x76,0x0c,0xf9,0xc6,0xcd,0xd4,
+  0xb8,0x5f,0x3b,0x98,0x71,0xbf,0xad,0xfe,0x4b,0x49,0xe3,0x9f,0x18,0x17,0xc6,0x5c,
+  0x13,0x29,0x84,0x1d,0xa9,0x42,0x30,0x29,0xab,0xfe,0x6b,0x75,0x45,0x5a,0xff,0x4c,
+  0x51,0xf6,0xfc,0x72,0x84,0x17,0xc2,0x3b,0xf9,0x07,0x5b,0xff,0x67,0xce,0x87,0xd4,
+  0x2e,0xf5,0xb6,0x8b,0xe7,0xa5,0xcb,0xe0,0xd5,0xbc,0xaf,0x74,0x0e,0xc7,0xde,0xe6,
+  0x1d,0x6f,0xc4,0x61,0x25,0x27,0xfe,0xb9,0x6c,0xe8,0x7f,0xae,0x87,0x97,0xe0,0x7a,
+  0x7d,0xc5,0xab,0x0f,0x5f,0x2f,0xf3,0x83,0xd5,0xf0,0xfe,0x83,0x99,0xfc,0x4f,0x85,
+  0xa9,0xff,0x89,0x85,0x54,0xce,0x0f,0xbb,0x77,0x11,0xd5,0x7e,0x62,0x5a,0x06,0xfe,
+  0x59,0x9b,0xd6,0x3f,0xff,0x15,0x3c,0x9a,0x6a,0xfc,0xa8,0xe6,0xef,0xff,0xd3,0xa7,
+  0x18,0xf8,0xa7,0x27,0xea,0x5a,0x23,0x3d,0xca,0xa6,0xb1,0xe7,0xa1,0xd0,0xba,0xac,
+  0x7c,0x62,0xf6,0xf9,0x68,0xee,0xc7,0x66,0xfc,0x15,0xf9,0x15,0x34,0x20,0x51,0xbc,
+  0x26,0x2b,0x23,0x96,0x3e,0x1f,0x36,0x01,0xbb,0xa4,0x94,0xba,0xfb,0x47,0x78,0x2c,
+  0x6c,0xbb,0x77,0xbb,0xdb,0x81,0x88,0x78,0xe3,0x20,0x5b,0xff,0x43,0x73,0xbd,0x75,
+  0x89,0x49,0xf9,0x84,0xd0,0x0c,0x01,0x49,0x54,0xf9,0x1f,0x22,0xcf,0xf9,0xb0,0x5d,
+  0xa9,0xfc,0x97,0xca,0x9c,0xea,0x49,0x99,0x6d,0xe4,0x47,0x48,0xa3,0x7a,0x5f,0x46,
+  0x46,0x2c,0x91,0x9d,0x8f,0x58,0xc8,0x16,0xc9,0xc3,0x94,0x7d,0x26,0x8b,0x4b,0x3c,
+  0xd0,0x49,0x32,0xfd,0xb3,0xf9,0x4f,0xe0,0xe7,0x85,0x7d,0x1d,0xbf,0xdf,0xf3,0xea,
+  0x23,0xb0,0x20,0xd9,0xdd,0x7e,0x2f,0xfb,0x1e,0xf3,0x9e,0x0f,0x2b,0x77,0x9b,0xf8,
+  0x67,0xc6,0x6f,0xe4,0x7f,0x61,0x86,0x67,0x44,0x6c,0x20,0xbf,0xcc,0x7b,0x3e,0xac,
+  0x7f,0x96,0xe1,0x6f,0x57,0xc5,0xd9,0xf7,0x92,0x12,0xba,0x0c,0x5b,0xfe,0xc7,0x94,
+  0xc2,0xda,0xfa,0x3f,0x7b,0x9e,0x6d,0xe3,0x41,0xea,0xdb,0x9c,0xff,0x69,0x19,0xf6,
+  0x8e,0x57,0x35,0xda,0xe2,0x97,0x01,0x84,0xd2,0xe7,0xc3,0x3e,0x29,0x5b,0x78,0xe6,
+  0x7a,0x7c,0xed,0xdf,0xba,0x97,0xb8,0x66,0x99,0xb0,0x27,0x07,0xff,0x13,0x83,0xc7,
+  0x14,0x7e,0x71,0xcc,0xb8,0x7f,0xd0,0x7d,0x3b,0xd9,0x66,0x43,0x44,0x24,0xeb,0x7c,
+  0x58,0xac,0xf7,0xf1,0xe8,0x33,0x9b,0x48,0x01,0xf6,0xb7,0x41,0x6f,0x5f,0x9d,0x15,
+  0xef,0xd2,0xf5,0x5f,0xb2,0xc4,0xfc,0x2d,0xdb,0x2d,0xba,0x9f,0x13,0x0b,0xe0,0xc5,
+  0x82,0xda,0x33,0xde,0xf8,0xa7,0xab,0xa5,0xcc,0x8d,0xa4,0xad,0xff,0x33,0x98,0x78,
+  0xc9,0x3d,0x4c,0xf8,0x44,0x45,0x45,0xab,0xfe,0x1d,0x0f,0x8a,0xbd,0xdb,0xc0,0x3f,
+  0xe6,0xfd,0x02,0x18,0x7a,0x86,0x92,0x8b,0xe2,0x79,0xdf,0xcb,0xcc,0x28,0x4e,0x8a,
+  0xdf,0x02,0x34,0xdc,0x63,0x58,0x21,0x4e,0xf0,0x04,0x84,0x2a,0x7b,0xff,0x67,0x16,
+  0xcd,0x89,0x51,0xbd,0x0e,0x3d,0x65,0xb5,0x7a,0x5b,0x94,0x7c,0x8a,0xeb,0x57,0x57,
+  0xe4,0x3d,0x1f,0xd6,0x8c,0xce,0x04,0x6f,0x2b,0x8a,0xc3,0x1d,0x59,0x7a,0x57,0x07,
+  0xfe,0xe1,0x65,0x71,0x6c,0x12,0x86,0x71,0x7e,0x12,0xdd,0x7b,0x49,0xfa,0x20,0x6f,
+  0x39,0x9b,0xff,0x81,0x75,0xe6,0x7a,0x18,0x96,0x8f,0x0a,0xcd,0x89,0xfb,0xe7,0x3e,
+  0xfc,0x35,0xf2,0x22,0xd7,0xff,0xa4,0x89,0x8e,0x34,0xff,0xd3,0x51,0x60,0x06,0xf1,
+  0x19,0xe7,0x11,0xff,0x0c,0x79,0xf7,0x89,0xe7,0xb1,0xfe,0x3d,0xb1,0x2a,0x2f,0xff,
+  0xf3,0xf2,0xa6,0xfa,0x33,0xeb,0xc6,0x5b,0x11,0xed,0xd4,0x25,0xef,0xb7,0xf3,0x3f,
+  0xe4,0x0d,0x64,0x14,0x33,0xf9,0x1f,0x84,0x3d,0x6d,0x7d,0x75,0x1c,0x08,0x25,0xed,
+  0xfc,0xcf,0x59,0xa9,0xc7,0xb8,0x32,0xe6,0xe0,0x7f,0xb0,0x88,0x40,0x0e,0x02,0xfe,
+  0xf5,0x79,0x37,0xf5,0xb4,0x10,0x5a,0x78,0xd8,0xa0,0x5e,0xcf,0x39,0xf8,0x9f,0x1e,
+  0xa1,0x26,0x05,0x23,0x25,0x9f,0xde,0x93,0xe6,0x7f,0x4a,0x47,0xa1,0x47,0xf2,0x65,
+  0xd4,0xbf,0x97,0xed,0x61,0x68,0x84,0x77,0x63,0xc6,0xea,0xad,0x3a,0xdd,0xd9,0x2f,
+  0xeb,0x75,0xa3,0x11,0x50,0xd2,0xc2,0x4b,0x67,0xe0,0x99,0xd2,0x49,0x38,0x80,0xf3,
+  0x83,0x30,0xf8,0x39,0xe3,0xfc,0x8b,0x7b,0xd2,0xf8,0xe7,0xb9,0xcc,0xfc,0xd7,0x1e,
+  0xd9,0x90,0xd9,0x5b,0x8f,0x6d,0x75,0xe8,0x5b,0xf8,0xf3,0x3f,0xb0,0xf1,0x3f,0x1e,
+  0x5e,0xef,0xb6,0x02,0x5f,0xbb,0xd7,0x5a,0x06,0x5c,0xc8,0x54,0x8a,0x33,0xc0,0xdf,
+  0xff,0x23,0xa7,0xfe,0x47,0xf2,0xf4,0xdb,0xb6,0x5d,0x1c,0x18,0x7b,0xcc,0xef,0x25,
+  0xe6,0xe4,0x7f,0x6e,0xcb,0xec,0xff,0xe3,0xd4,0x03,0x2f,0xea,0xe0,0x89,0xb0,0xf1,
+  0x2c,0xfc,0x63,0xaa,0x7d,0x46,0xbd,0xf5,0xa8,0xff,0xe9,0xc2,0x2b,0x4b,0x11,0xff,
+  0x04,0xfb,0xbd,0x0b,0xf3,0xeb,0x7f,0xd8,0x32,0xdb,0xdb,0x7a,0x49,0x9f,0xac,0xe6,
+  0x2b,0x6a,0x94,0xdd,0xcf,0x96,0xe2,0x58,0xab,0xbd,0xff,0xcf,0xa0,0x89,0x06,0x2d,
+  0xe3,0x0b,0x0c,0x5f,0x19,0xf9,0x2f,0xe5,0x43,0xc3,0xb0,0xf1,0x3f,0x57,0x3f,0x06,
+  0x9b,0xa4,0x94,0xf7,0x40,0x63,0xc5,0xfa,0xba,0x53,0x65,0x9b,0xd2,0xf9,0x2f,0x6e,
+  0x9c,0xb3,0xea,0xbf,0x74,0xf8,0x21,0x31,0xbb,0x1d,0x92,0x4d,0x74,0x1e,0x27,0x82,
+  0xc8,0x26,0x23,0xdf,0xf7,0x43,0xe1,0x00,0xdd,0x81,0x8a,0xa0,0x74,0xff,0xe7,0x36,
+  0xc9,0x54,0x97,0xf9,0x06,0xf9,0x67,0xf5,0x7f,0xc5,0xd9,0x32,0xc3,0x15,0xb8,0xc2,
+  0xf8,0xbe,0xc2,0x19,0xfc,0x4f,0x41,0x37,0x9c,0x34,0x40,0x4e,0xc2,0xc0,0x3f,0x08,
+  0x7b,0x8e,0xc1,0x3e,0x66,0x7c,0x11,0x5b,0x43,0xd7,0x65,0xe0,0x1f,0x16,0x7f,0x47,
+  0x24,0x5b,0xb6,0xcb,0xcd,0xf9,0x1f,0xc1,0xd0,0xa3,0x2a,0x1b,0x8c,0x13,0x63,0xd3,
+  0xf8,0xa7,0x5b,0x19,0x16,0x4d,0x35,0x2c,0x31,0x8c,0x19,0xd5,0xe9,0x78,0x77,0x43,
+  0x16,0xfe,0xc1,0xfe,0x87,0x1c,0xff,0x88,0x86,0xfe,0xb6,0xc4,0xc0,0x3f,0x8d,0x3c,
+  0xfe,0x4a,0x07,0x0d,0xc3,0x71,0xfe,0x85,0x60,0xaa,0x73,0xa5,0xcd,0xc2,0x1d,0xda,
+  0x0a,0xb3,0x11,0xd0,0x4c,0x9b,0x70,0xc8,0xc6,0xff,0x80,0xa5,0xfe,0xed,0xe2,0x86,
+  0x2b,0xea,0x92,0xf8,0xa9,0x53,0x29,0x3c,0xe0,0x5f,0xea,0xe0,0x7f,0xfa,0x64,0x4c,
+  0x43,0x37,0x1b,0x7c,0x8b,0x11,0x76,0x89,0x6a,0xc3,0x7b,0xe2,0x6c,0xac,0x88,0x77,
+  0xf0,0x3f,0x8a,0x83,0xcd,0x78,0x20,0x5a,0x35,0x0c,0x6f,0x4b,0x8d,0xe6,0x15,0x34,
+  0x6c,0xfd,0x9f,0xb7,0x17,0x9c,0xe7,0x65,0x31,0xec,0x57,0x34,0xf6,0xa5,0x0c,0xc2,
+  0x9f,0x80,0x47,0x63,0x34,0x6b,0xab,0x32,0xf9,0x1f,0x0e,0x7b,0x28,0xb1,0x1b,0xa9,
+  0xfe,0x87,0x0c,0xcc,0x66,0xf4,0x7f,0x46,0xfe,0xa7,0x03,0x9b,0xcc,0x63,0xff,0x1f,
+  0x41,0x50,0x35,0xd1,0x14,0x42,0xbb,0x95,0xc2,0x61,0x6e,0xcc,0xcc,0xe4,0x7f,0x36,
+  0x9b,0xe8,0xd1,0x30,0x42,0xc3,0x69,0xfd,0xf3,0x13,0x52,0x0e,0xfe,0xe7,0xa8,0x89,
+  0x66,0x6d,0x46,0xb3,0xc3,0xc8,0xe6,0x7f,0x1c,0xb2,0x28,0x05,0x85,0xf1,0xc5,0xa9,
+  0x2b,0x4b,0xbd,0x79,0xcf,0x87,0xcd,0x34,0x8c,0x9f,0x3c,0x8e,0xfa,0x77,0xf6,0x17,
+  0xde,0xc7,0x40,0x4e,0x49,0xac,0x34,0x21,0xed,0x4b,0xa1,0x1d,0x01,0x61,0xcf,0x8a,
+  0x58,0xeb,0x6e,0x38,0x24,0x94,0x20,0xb0,0xef,0x4e,0xf3,0x3f,0x1b,0xb3,0xf8,0x9f,
+  0x9b,0xad,0x30,0xbd,0x87,0x3b,0xa2,0xa2,0x60,0x28,0xcd,0xff,0x54,0xa6,0xf8,0x9f,
+  0x8c,0xb2,0x77,0xe3,0x58,0xd8,0xc7,0x0a,0x0e,0x30,0x44,0x54,0xb1,0x9e,0xec,0xb6,
+  0xf3,0x3f,0x4a,0xba,0xdb,0x61,0xd7,0x7c,0x66,0xb4,0x1a,0xfe,0x8a,0x5d,0xf9,0x21,
+  0xc3,0x3f,0x2d,0xc9,0x62,0x47,0xff,0xe7,0x14,0xff,0x53,0xe2,0x70,0xb3,0x48,0xe3,
+  0x6f,0x75,0xe0,0x1f,0x73,0x7e,0xb4,0xf2,0x2b,0xda,0x64,0x9a,0xed,0x59,0x62,0x18,
+  0x5c,0xd1,0x7a,0x81,0xfd,0x2f,0xbe,0x8c,0xc2,0x06,0x16,0xbf,0xec,0xe7,0x5f,0x68,
+  0x07,0x14,0xf3,0xb5,0x95,0xf9,0xd8,0x4f,0x0c,0xf5,0x27,0x5c,0x88,0x78,0x3a,0xb4,
+  0x89,0xce,0x1f,0xed,0xb1,0xeb,0x7f,0xa2,0xf0,0x98,0x74,0x40,0xb2,0xa1,0xbb,0x15,
+  0xeb,0x2d,0xfd,0x4f,0xe9,0x29,0x03,0x11,0x39,0xfa,0xff,0x48,0x56,0x10,0x47,0xa3,
+  0xd6,0x22,0xa2,0x0d,0x0f,0x9f,0x0a,0xf4,0xb9,0xfa,0xff,0x60,0x34,0x2f,0xb4,0x02,
+  0x4d,0x83,0x71,0x22,0xf9,0x8b,0x46,0xfe,0xe2,0xa4,0xf5,0x3e,0xdb,0x72,0xf2,0x3f,
+  0x68,0xfc,0x85,0x69,0xb0,0x27,0x0c,0x5b,0xfe,0xa7,0x43,0xb9,0x24,0x18,0xfe,0xfc,
+  0xab,0x86,0xfa,0xd7,0x93,0x86,0x01,0x55,0x16,0x1e,0x48,0xc7,0xeb,0xfe,0xae,0x34,
+  0xff,0xc3,0xcb,0xbe,0x8a,0x6d,0xb2,0x55,0x1b,0x9e,0xb1,0xf8,0x1f,0x29,0x20,0x3b,
+  0xd8,0x09,0x8b,0xff,0xe1,0x15,0xf1,0x46,0xe3,0x20,0x5f,0x16,0xff,0xd3,0x6f,0xf2,
+  0x3f,0x2f,0x14,0xd5,0x61,0x3d,0xb2,0x62,0xcc,0x18,0xed,0x55,0xb1,0x1f,0x20,0xd8,
+  0xea,0xdf,0xed,0xfc,0xcf,0xbb,0x52,0x73,0xc2,0xb3,0xaf,0x33,0x3d,0x70,0x75,0xc2,
+  0xdf,0x7c,0xcc,0x9b,0xb3,0xff,0x4f,0x2a,0x7e,0xa1,0x3a,0xc8,0xd2,0xff,0xa4,0xfe,
+  0x8b,0x63,0x33,0xb2,0xcf,0x87,0xbd,0xd3,0x95,0xeb,0x3c,0xbe,0xce,0xe0,0xbf,0xff,
+  0x3c,0x3e,0xb9,0x8b,0x54,0x42,0xb7,0xc6,0xeb,0x52,0x6d,0xc6,0x27,0x9c,0x87,0x78,
+  0xe7,0xbf,0xf3,0x3c,0xc4,0xc1,0xff,0x64,0xe7,0x21,0x0e,0xe6,0xfd,0xe5,0xff,0x2b,
+  0xe7,0x21,0x6a,0x86,0x01,0x9f,0x70,0x1e,0xe2,0x9d,0x7f,0xe4,0x79,0x88,0xda,0x1f,
+  0x39,0xff,0xda,0x7f,0x9d,0x87,0xf8,0xef,0xfb,0xf7,0x9f,0xeb,0xfc,0xc1,0xff,0x7c,
+  0xf7,0x93,0xae,0xb2,0x0e,0xd1,0xdf,0x4e,0xca,0x60,0xa0,0x7a,0x47,0x27,0x03,0x88,
+  0x65,0x91,0x2e,0xa9,0x72,0x85,0x3f,0x44,0x94,0xc8,0xa6,0xb2,0xbd,0x62,0xd6,0xf7,
+  0x58,0xe0,0x17,0x28,0x84,0x65,0x05,0x0a,0x64,0x21,0x01,0x21,0xa8,0xd0,0xa6,0xc9,
+  0xd3,0x11,0x61,0x54,0xe8,0xd3,0xfc,0x02,0x48,0x99,0xdf,0xe3,0xbd,0x50,0x19,0x92,
+  0xf1,0xf9,0xf7,0xaa,0xea,0x11,0xe6,0x0f,0xb7,0x75,0x6f,0x2a,0x3c,0xf3,0x85,0xee,
+  0x90,0xaf,0xa2,0xfb,0x97,0x85,0x95,0x04,0x3d,0xa4,0xe3,0x7e,0xa9,0x02,0x3f,0x6a,
+  0xa1,0x0c,0x24,0x79,0xba,0x0c,0x4b,0x81,0x19,0x52,0x87,0xc6,0x1e,0x3b,0x8b,0x16,
+  0x96,0xe5,0xf8,0xde,0x3b,0x41,0x6d,0x93,0xc1,0x25,0x91,0xe7,0x41,0xa5,0x1e,0xfc,
+  0x3a,0x96,0xaa,0x6a,0x9b,0xca,0x0c,0x4a,0xd5,0x60,0x37,0x57,0x62,0xda,0xc7,0x2b,
+  0x2a,0x51,0x03,0x3e,0x89,0x40,0x07,0xf0,0x7b,0x8a,0x84,0x20,0xba,0x52,0x62,0xff,
+  0x5b,0xcc,0x9b,0xd0,0x65,0xd5,0x42,0xc6,0xf7,0xd8,0x59,0x8d,0xcf,0xbf,0x4f,0x22,
+  0x9d,0x92,0x9a,0xc0,0xa7,0x85,0x3b,0xaa,0xe9,0xa0,0x4c,0x5c,0x40,0x87,0xaa,0x55,
+  0xf6,0xfc,0x88,0xe3,0x76,0x45,0xa8,0x86,0x22,0x80,0x22,0xe6,0x9b,0x24,0xa5,0x08,
+  0x5f,0x47,0x63,0x17,0xfb,0xab,0x7d,0x1a,0x66,0x67,0xf0,0xa7,0x8c,0xf9,0xdf,0xe4,
+  0xaf,0x1c,0xf4,0x7f,0xd3,0x35,0x2b,0xb4,0x49,0xde,0xe1,0x09,0xb4,0x2e,0x9f,0x15,
+  0xd9,0x54,0xb1,0x50,0x63,0x7f,0x88,0x8a,0xa1,0x17,0xd4,0x4a,0x8a,0x48,0xdd,0xf1,
+  0x5f,0x98,0x26,0x4d,0xa7,0x10,0x92,0x2b,0xd4,0x69,0x52,0x47,0x9b,0xda,0xaa,0x29,
+  0x74,0x9a,0xbf,0x03,0x27,0xaa,0x42,0x2f,0x58,0xcc,0xfe,0x22,0xad,0x19,0xf3,0xf3,
+  0x4b,0x55,0x0d,0xb1,0x69,0x91,0xe8,0x26,0x58,0xf8,0x00,0xb4,0x8a,0x8a,0xc6,0x8c,
+  0x9b,0x20,0x44,0xca,0x8e,0xdc,0xbb,0xb8,0xf2,0x05,0x4f,0x6b,0x96,0x3f,0xec,0x20,
+  0x7c,0x92,0x99,0xf7,0x0b,0x49,0xdf,0x84,0x59,0x63,0xd3,0xd4,0xe9,0x2f,0x4a,0x77,
+  0xea,0xb3,0xa2,0x05,0xc1,0x8e,0xad,0xf0,0x4d,0xee,0x78,0xd3,0xff,0xba,0xca,0x2a,
+  0x25,0x99,0x2d,0x1b,0xe8,0x62,0xef,0xe3,0x69,0xd7,0x14,0x3d,0x12,0x5c,0xe8,0xf2,
+  0x68,0x11,0x45,0xf9,0xa5,0x52,0x19,0xf1,0x2f,0x15,0x33,0xfc,0xa1,0xaa,0xb8,0x54,
+  0xd0,0x64,0x36,0x33,0x4a,0xa1,0xa0,0x16,0x41,0x52,0x08,0x40,0x1b,0xfe,0x21,0x42,
+  0x42,0x35,0xd5,0x40,0x6c,0x73,0xbc,0x7e,0x50,0x57,0x62,0x05,0x1e,0x08,0x49,0x41,
+  0x0a,0xc1,0xcf,0x79,0x94,0x56,0x69,0x28,0x12,0x0c,0xde,0x8f,0x6e,0xf0,0x21,0x86,
+  0xf4,0x3b,0x40,0x0c,0xd9,0xee,0x96,0x18,0x7e,0x96,0x29,0xe0,0xa4,0xab,0x20,0x51,
+  0xad,0x1a,0x34,0x29,0x54,0x08,0x51,0xfe,0xc2,0xaa,0x28,0xe3,0xff,0x43,0x1d,0xfe,
+  0xd0,0x78,0x39,0xf6,0x9f,0xa3,0x2a,0xd2,0x1d,0xcc,0x8e,0x72,0x9f,0xaa,0xda,0x0c,
+  0x6a,0xdd,0xdd,0xd4,0x14,0x8c,0x53,0xaa,0xa9,0x0a,0x28,0x63,0x94,0xb2,0xeb,0x8a,
+  0x86,0x46,0x0c,0x18,0x62,0xe6,0x57,0xf8,0x4f,0x2f,0xdb,0xfc,0x61,0x53,0x47,0xe4,
+  0x47,0xf4,0xc6,0xef,0xdf,0xfd,0x67,0x91,0xce,0x8e,0x99,0xb4,0xa9,0xe2,0x33,0x0f,
+  0x76,0x74,0x2e,0xfd,0x2b,0x76,0xe5,0x3b,0xd7,0x2c,0x5d,0x2d,0xb4,0xea,0x4d,0x57,
+  0xef,0xa9,0x70,0x2e,0x08,0xbe,0x66,0x94,0x72,0x42,0x09,0xa5,0xec,0x7b,0x6a,0xd7,
+  0x22,0x94,0x2d,0x31,0x6d,0x29,0xe0,0x40,0x69,0x59,0x59,0x99,0x85,0xae,0xcc,0x7f,
+  0xf5,0x84,0x74,0xf3,0x55,0x58,0x2f,0x09,0x1d,0x7c,0xa8,0xf5,0x82,0x20,0xf3,0x75,
+  0x5f,0x2f,0x77,0x2f,0x5b,0x66,0xbf,0x37,0xed,0x0d,0xee,0xc9,0xf2,0x0f,0x57,0xee,
+  0x99,0xa4,0x90,0xf1,0x2f,0xfd,0xeb,0xc7,0xef,0x67,0xdc,0xbf,0xe4,0x4a,0xcb,0x64,
+  0xe6,0xab,0xd8,0xee,0x7f,0xe3,0x0d,0xf3,0xfe,0xe7,0xde,0x37,0x8c,0xf7,0x5b,0xa6,
+  0xf2,0x57,0xf7,0xb4,0x98,0xf7,0xdf,0xf3,0x07,0xf9,0xb7,0x67,0x5b,0x3e,0x4e,0xdd,
+  0x66,0xfd,0x17,0x27,0x3f,0x9e,0xe2,0xfe,0x2b,0x0b,0x8c,0xd1,0xb5,0x5c,0x99,0x34,
+  0x8c,0xeb,0x26,0xaf,0x64,0x3d,0xff,0x17,0x4b,0xc5,0xf5,0xda,0x29,0x65,0x11,0x14,
+  0xf4,0x1b,0x46,0x59,0xf1,0x2f,0xc4,0x6f,0x68,0xb7,0x5a,0x46,0xfb,0x9f,0x48,0xc5,
+  0xfa,0x42,0xeb,0xfe,0xcf,0x2e,0x93,0xbe,0x21,0xdc,0xaa,0x7d,0x99,0x05,0xff,0x02,
+  0x66,0x2c,0xfd,0x72,0x45,0xf9,0x00,0x33,0xda,0xb4,0x56,0xa5,0x7c,0x40,0x60,0x57,
+  0xc2,0x5f,0x56,0xca,0xf5,0xe9,0x26,0x5e,0x05,0x4a,0x04,0xb5,0xab,0x4d,0x2d,0x95,
+  0xa5,0x88,0xa0,0xd2,0x94,0x51,0xc9,0x8c,0x3f,0x91,0xa5,0x7b,0xcd,0x2b,0xd6,0xf1,
+  0x3e,0xb8,0xf4,0xd8,0x5e,0x75,0x35,0x5c,0x05,0xdb,0xa8,0x10,0x46,0x43,0x29,0xb8,
+  0x57,0x08,0x0b,0xab,0xc9,0x55,0x15,0x05,0x54,0xb8,0xad,0x63,0xb5,0xf6,0x25,0x28,
+  0xb0,0xdd,0xff,0xd9,0xd5,0x05,0x0d,0xc2,0xe7,0xe9,0x97,0x97,0x4a,0xdd,0x05,0xdf,
+  0x14,0x6e,0xa5,0x5f,0x56,0xcb,0x13,0x05,0x77,0xa6,0x0c,0x21,0x75,0xc5,0xf6,0x3e,
+  0xbf,0xd0,0xc2,0xaa,0x22,0x4b,0x84,0xb9,0x3e,0x08,0x43,0x05,0x14,0x82,0x60,0x19,
+  0x5d,0x92,0x79,0x25,0x3d,0xde,0x5f,0x68,0xd2,0xed,0x42,0x05,0xbd,0x49,0x85,0x2d,
+  0x92,0x4f,0x90,0xf5,0x90,0xaa,0x74,0x4b,0x6a,0x87,0x4c,0x43,0x41,0xe5,0x5e,0x49,
+  0x65,0xce,0x93,0x5d,0xb1,0xdf,0xbf,0xbc,0xe0,0xe6,0x8e,0x5b,0x62,0xb7,0xf8,0x0b,
+  0x5c,0x05,0xa1,0x8e,0xf6,0xf8,0x2d,0xfe,0x72,0x57,0xc1,0x52,0xda,0xce,0xae,0x94,
+  0x93,0x02,0x8d,0xb6,0xab,0x65,0x4d,0xe5,0xb0,0x30,0x3d,0x3f,0xb3,0x84,0x69,0xda,
+  0x9f,0xeb,0xe5,0xb7,0x48,0xb3,0x84,0x2f,0xc3,0x9f,0xeb,0xd3,0xd7,0x17,0xdc,0x2a,
+  0x7c,0x11,0x6e,0xd1,0xcb,0x83,0xcc,0x10,0xd1,0x58,0x2c,0x59,0xf4,0x0f,0xbb,0xdf,
+  0xcf,0x1c,0x47,0x29,0x48,0x54,0xc1,0xa6,0x37,0x4a,0x58,0x40,0x48,0x88,0x2e,0x90,
+  0x85,0x11,0x89,0x7d,0x49,0x0a,0x95,0x14,0x16,0x10,0xd2,0xef,0xb3,0x96,0xc8,0x5a,
+  0x04,0xd4,0xae,0x0a,0x95,0x30,0xd7,0x0f,0x95,0x54,0x36,0x0c,0x95,0x19,0x85,0x29,
+  0x63,0x69,0xfa,0x7d,0x7e,0xd1,0x5e,0x50,0x2d,0xfc,0x37,0xf8,0x92,0x56,0x1e,0x2d,
+  0x58,0x63,0x1a,0x61,0xe1,0x04,0x7c,0x09,0x52,0xc6,0xff,0x82,0x72,0xc7,0xfc,0x88,
+  0x61,0x38,0xc1,0xfe,0x5e,0x05,0x94,0x1b,0x0d,0xd8,0x41,0xe7,0x76,0xf6,0x87,0xfb,
+  0x5b,0x66,0x4c,0x63,0x06,0xbd,0x8a,0x19,0xb6,0xf5,0xc3,0x1c,0x5b,0x87,0x07,0x3d,
+  0x53,0x44,0x52,0x3a,0x3c,0x95,0xad,0xb2,0x72,0x84,0x5d,0x91,0xd4,0x9b,0x98,0x01,
+  0xc1,0x7e,0x4f,0x90,0x5d,0xd1,0xd3,0xef,0xc3,0xfe,0x05,0xd9,0x9e,0x4a,0xc4,0x95,
+  0x91,0x32,0x74,0x6e,0x10,0x4c,0xb6,0x98,0x57,0x6c,0xf3,0x43,0x84,0x20,0x5d,0xa9,
+  0xce,0x90,0xcb,0x22,0x29,0x43,0x3a,0x22,0x04,0xfb,0xb9,0xf1,0x22,0xf3,0xe7,0x2b,
+  0xd5,0x2f,0xca,0x92,0xed,0xfe,0x5f,0x84,0x0a,0xc2,0x1d,0xab,0x55,0xb6,0xa8,0x22,
+  0x86,0x21,0x97,0x33,0xa3,0x7f,0xb5,0x7a,0x95,0x5c,0xde,0x59,0xa0,0xf6,0xaf,0x0e,
+  0xb2,0x2b,0xd4,0x36,0x3f,0x21,0x3e,0x73,0xd6,0x14,0xa6,0x0c,0x8f,0x1a,0x32,0x0d,
+  0x36,0x34,0xfb,0x78,0x6f,0x96,0xc2,0x1d,0x15,0x95,0x37,0xb5,0xc1,0x43,0xcc,0xb8,
+  0x9a,0x0d,0x73,0x7a,0x44,0x5a,0xc3,0x66,0xe0,0xa6,0xb6,0xe9,0x0f,0xb1,0x85,0xe4,
+  0x51,0x5b,0xdb,0xa6,0xd3,0xe9,0x56,0xc8,0xf8,0x6c,0xb8,0x60,0xb5,0xf0,0x25,0xf8,
+  0x2c,0x95,0x54,0x6e,0xfc,0x39,0x2d,0x0f,0x4b,0xab,0xe1,0x26,0x6e,0x08,0x15,0xcc,
+  0x98,0x4e,0xcb,0x35,0xdb,0xf7,0x55,0x08,0x7f,0x46,0x6f,0x09,0x97,0x6f,0x97,0x0a,
+  0x05,0xb6,0xcc,0xc2,0x65,0x15,0x05,0x68,0xdc,0x62,0x1a,0xfc,0x0a,0x0b,0x41,0xe6,
+  0xfd,0xfd,0xa5,0x1c,0x56,0xdf,0xdc,0x06,0xa5,0xec,0x13,0x58,0x6a,0x7c,0x0b,0x12,
+  0xba,0xf1,0x36,0x09,0xaf,0x70,0xc3,0xda,0xee,0x03,0x0c,0xdc,0x44,0xa6,0xd3,0xae,
+  0xf0,0xd7,0x2a,0x2a,0x6e,0x12,0xff,0x8c,0xbe,0x1a,0xfe,0x4c,0x45,0x31,0x1a,0xdb,
+  0xb8,0x31,0x6d,0xba,0x71,0x45,0x4b,0xcf,0x4f,0xd7,0x4d,0x05,0xdf,0xe8,0x40,0x27,
+  0x70,0xed,0x0b,0x45,0x68,0xfc,0x49,0x45,0xf9,0x0b,0xec,0xca,0x29,0xed,0xcb,0x68,
+  0xdc,0xd6,0x71,0x2a,0xfc,0xb7,0x15,0xe5,0x76,0x7f,0x72,0x93,0xf0,0x0d,0x7a,0x2a,
+  0xbc,0xa8,0xa2,0xf8,0x05,0x11,0x8d,0x69,0x86,0x71,0xab,0x71,0xe5,0x36,0x8a,0x4f,
+  0xb8,0x56,0x9f,0x6e,0xbb,0x5f,0xe2,0xcf,0x5f,0xdd,0xf6,0x42,0x41,0xfa,0xf9,0x1b,
+  0x3d,0x61,0x7c,0x3e,0x2c,0xec,0xf0,0x84,0x5b,0x2b,0xec,0xdf,0x3b,0xe0,0x7a,0x40,
+  0x27,0x03,0x86,0xff,0x69,0x37,0x1c,0xd1,0xad,0xa6,0x47,0xba,0x15,0x1d,0x11,0xb5,
+  0xad,0xb6,0x42,0xe1,0x36,0xba,0x3a,0x7c,0x55,0x05,0xf3,0x4e,0x86,0xc1,0xfc,0x0f,
+  0x73,0x3b,0x86,0x51,0xc9,0x8c,0x2f,0x55,0x94,0xdb,0xee,0xff,0xac,0x56,0x1e,0x14,
+  0x56,0xc2,0x17,0x41,0xd2,0x0b,0xd6,0x0b,0xb7,0xc2,0x97,0xa1,0x3c,0x6d,0x08,0xc1,
+  0x94,0x91,0x7e,0x9f,0xcf,0xb6,0x82,0x1a,0x93,0xfd,0x0c,0x4d,0x45,0x20,0x4c,0x2b,
+  0xd8,0x27,0x28,0xa4,0x0d,0x49,0x35,0x0c,0x6a,0x1b,0xef,0x72,0x29,0xbc,0xa3,0x42,
+  0xbd,0x89,0xdd,0x8f,0x6e,0x87,0x2d,0x33,0xc5,0x66,0x84,0x0d,0xc3,0x7e,0xbf,0x36,
+  0xa7,0x7d,0xe9,0x2d,0xa5,0x7f,0x0e,0x5d,0xcc,0xdb,0x74,0xb4,0x57,0xde,0x22,0x73,
+  0xb7,0xf3,0x67,0x2a,0x33,0xc4,0x82,0x76,0xf4,0x3f,0x72,0x01,0xd8,0xe6,0xc7,0x2d,
+  0xb4,0x27,0x6e,0x09,0x96,0xcb,0x52,0xab,0xd0,0xae,0xdf,0xa2,0x96,0x7b,0x0a,0xb8,
+  0x11,0x64,0x46,0xc8,0x30,0xe4,0x02,0xcd,0x36,0x3f,0xa0,0x85,0x15,0x45,0x92,0x04,
+  0xc4,0x2f,0xa0,0x74,0x14,0x72,0x17,0xc8,0xb6,0x65,0xcc,0x17,0x02,0x5e,0xe1,0x46,
+  0x1a,0x01,0x7d,0xb6,0xf5,0xff,0x69,0xef,0xfc,0x42,0xe3,0x38,0xee,0x38,0xfe,0x9b,
+  0xbb,0xd9,0xf3,0x9e,0x7d,0x72,0x77,0xa5,0xbd,0x66,0xd5,0x08,0xb3,0xfa,0x53,0x4b,
+  0xa6,0xa4,0xac,0x82,0x95,0xba,0x08,0xa2,0x39,0xdd,0x9d,0x7c,0x12,0x8e,0x7c,0x96,
+  0x1c,0xc5,0x18,0x53,0xd6,0x46,0x34,0x26,0x50,0x90,0x0d,0xa5,0xee,0x43,0x9d,0x39,
+  0xf5,0x9c,0xaa,0xc5,0x85,0x8b,0xac,0x62,0x19,0x04,0x3d,0x13,0xd5,0xf4,0x25,0xd0,
+  0x42,0x8d,0xf3,0xd6,0x93,0x62,0xab,0x2e,0xf4,0xc1,0xa4,0xaa,0xc9,0x43,0xa9,0x6c,
+  0xd0,0x4b,0xa1,0x26,0x2f,0x86,0xa2,0x16,0x45,0xfd,0xcd,0xec,0xdd,0xed,0xc8,0x0d,
+  0x86,0xa4,0xd0,0x42,0x99,0xef,0xd3,0x97,0xd9,0xb9,0xd5,0x6f,0x67,0x67,0x7e,0xf3,
+  0xf9,0xed,0xea,0xa4,0x58,0x17,0xe7,0x37,0xbd,0xc2,0xe2,0xac,0x04,0x54,0x30,0x05,
+  0x52,0xf2,0x52,0x9f,0x87,0x26,0x21,0x5a,0xd0,0x28,0xf1,0xe4,0xd9,0x1e,0xcc,0xf6,
+  0x30,0x15,0x4f,0x73,0x43,0x98,0x87,0x20,0x0c,0x7c,0x4c,0x31,0xff,0xe0,0x8e,0x50,
+  0xcf,0x3f,0xd1,0xf5,0x5e,0x61,0x69,0xb1,0x4d,0xbc,0x12,0xff,0x29,0x8f,0x37,0xf3,
+  0x4f,0x00,0x67,0xa8,0x30,0x7b,0x3c,0x1c,0xff,0x17,0xd0,0xa8,0xf1,0xcb,0xa4,0x91,
+  0xa5,0x9c,0x3b,0x3e,0x49,0x89,0xd4,0x59,0xa3,0x3e,0x71,0x63,0xc2,0xe0,0xbc,0x17,
+  0x2b,0x0c,0x4d,0x24,0x1a,0x26,0x19,0x86,0xc5,0x6e,0x3f,0xa4,0x82,0x78,0x11,0xd6,
+  0xe1,0x30,0x62,0x2d,0xb6,0xac,0x83,0x40,0xdf,0x98,0xc8,0x48,0x4a,0x7f,0xa3,0x9f,
+  0x1d,0x2b,0xb6,0x2d,0x94,0x7f,0x47,0xfa,0x6b,0xc7,0x58,0x9b,0x93,0xbb,0x47,0xfa,
+  0x33,0xe3,0xc5,0x36,0x87,0xde,0x25,0x9d,0xb9,0x63,0xc5,0x49,0x8b,0xaa,0xfd,0xbb,
+  0x8d,0xf3,0x2b,0xdf,0xf2,0xa7,0xe6,0xe8,0x7b,0x68,0x4e,0xfb,0x53,0x57,0xd3,0xd2,
+  0x78,0xa1,0xa9,0xc9,0x16,0x35,0x7e,0x23,0xfc,0xf6,0x14,0x6b,0x14,0xdf,0x45,0x58,
+  0xc0,0x18,0x65,0x3c,0x0b,0x8d,0x78,0x76,0x5d,0x6f,0x2e,0xb0,0x5d,0x3a,0x42,0x60,
+  0x2e,0xdc,0xc8,0x7c,0x1b,0x8d,0xed,0x96,0xb3,0x9d,0x36,0x9f,0x3e,0x67,0xb9,0xe5,
+  0x11,0x34,0x6a,0xff,0xb3,0x45,0x3b,0x47,0xf3,0xc4,0x61,0x46,0xd1,0x3e,0x49,0x5f,
+  0x27,0xe9,0x5c,0xbe,0xe8,0x9d,0xa4,0x27,0x20,0x9d,0xbb,0x27,0x5a,0xd2,0x24,0xad,
+  0xce,0x07,0xb3,0x53,0xa4,0x40,0xcb,0x2b,0x9b,0xa2,0xec,0x99,0x75,0xc4,0x7f,0x28,
+  0x6e,0x98,0xce,0x09,0x57,0x98,0x2b,0xea,0xe9,0xf7,0x1a,0xb1,0x12,0x54,0xa1,0x0f,
+  0xf6,0x92,0x18,0x67,0x55,0xab,0x8f,0xa2,0xa9,0x44,0xe6,0x16,0x1a,0xb5,0x7f,0x2a,
+  0x31,0x49,0xca,0xb5,0x4e,0x1f,0x8e,0xc5,0x27,0x61,0xbd,0x36,0xe0,0xb7,0x44,0xe6,
+  0xe0,0xa4,0x75,0xf2,0xee,0xc0,0xcb,0x2d,0x6a,0x3c,0x49,0xe3,0x62,0xe6,0x4c,0xe5,
+  0x0d,0xcf,0xbe,0x4f,0x71,0xf7,0x9f,0x7d,0xc1,0x33,0xee,0x23,0x18,0xfc,0x39,0x04,
+  0x83,0x8b,0xf1,0x25,0xfe,0x3d,0xef,0x67,0xea,0xf8,0xbf,0x38,0x36,0xfc,0xb0,0x72,
+  0x7b,0xf9,0xa5,0xe4,0x3e,0x61,0x7e,0xb3,0xfc,0xd2,0xe8,0xbe,0x89,0xb1,0x07,0xf3,
+  0xb7,0x7b,0xde,0x4f,0xee,0x1b,0x1e,0x5b,0x17,0xe6,0x90,0x1a,0xcf,0xe0,0xdb,0xe3,
+  0x3b,0x7f,0xfc,0xed,0xd3,0x27,0x5b,0xd2,0xdc,0x79,0xfa,0xc9,0xd6,0xe0,0xa7,0xc7,
+  0x37,0xae,0xed,0x6c,0x6e,0x6f,0x0d,0x5e,0x3e,0xbe,0x23,0xcc,0x36,0xfc,0x07,0x7a,
+  0xf5,0x46,0xf2,0xe0,0xf0,0x68,0x65,0x7e,0x7a,0x68,0xeb,0x4b,0xb7,0xb2,0x3b,0x95,
+  0x7f,0xfc,0xe0,0xd5,0x9f,0x8f,0xbe,0xfd,0xd1,0x68,0xe5,0xfa,0xf6,0xd0,0xce,0x68,
+  0xef,0x47,0xa3,0x4f,0xaf,0x6f,0xaa,0xfd,0x87,0x2e,0x8f,0x6f,0x5c,0xbb,0xb3,0xf9,
+  0x64,0x6b,0xa8,0x1e,0xc6,0xf6,0x90,0x0c,0x6c,0xf3,0x13,0xec,0x3f,0xbe,0x21,0x23,
+  0x54,0xfb,0x77,0x1f,0x28,0x6c,0xcc,0x7f,0x63,0xf3,0xea,0xd9,0x41,0xf1,0xc1,0x5f,
+  0xe3,0x07,0xd1,0xfc,0xa5,0xed,0x4e,0xf9,0xc9,0x56,0xb7,0x2b,0xcd,0xdf,0xbe,0xbf,
+  0x2b,0xa0,0xec,0x0c,0x5b,0xb2,0x7a,0x5b,0x93,0xb5,0xae,0x99,0xcc,0x12,0xbc,0x49,
+  0x5b,0x56,0x40,0xb6,0xd0,0xe4,0x4a,0x0c,0x8d,0xdf,0x4b,0x89,0x3a,0x9e,0x38,0xff,
+  0x05,0x1f,0xba,0x20,0xb0,0x50,0x80,0xa2,0x7d,0x57,0x24,0x6a,0x34,0x98,0xa8,0x4f,
+  0xc8,0x16,0x43,0xed,0x1f,0x23,0x81,0xc8,0xcf,0x2e,0x34,0xf9,0x70,0x95,0x78,0x20,
+  0x8d,0xe4,0xc3,0xa0,0x75,0x77,0x7e,0x46,0xe6,0x11,0x90,0x16,0x2b,0x21,0xb6,0xc9,
+  0xfd,0xb0,0xc4,0x43,0x6c,0x73,0x11,0xe4,0xce,0x72,0xc1,0x6f,0x27,0xd4,0xfe,0x66,
+  0xee,0x62,0x32,0xc5,0xb3,0x06,0xcc,0x4d,0xbf,0x0c,0x1d,0xe5,0x3d,0xe1,0xc4,0xe8,
+  0xe0,0x47,0x9b,0xa6,0xc7,0x56,0xe3,0x01,0x08,0xea,0x7c,0x88,0xd4,0xe5,0x5a,0x2a,
+  0x1f,0x2a,0x26,0x52,0x12,0xb1,0x10,0x97,0x55,0x20,0xd6,0x97,0xfc,0x5a,0xa3,0x55,
+  0xa1,0xbd,0x04,0xf9,0x30,0xb0,0x16,0xe9,0x41,0x92,0xe4,0xc3,0xc5,0x5d,0xcf,0xac,
+  0x0e,0xd1,0xb1,0xd2,0x97,0xab,0xf9,0x0f,0xec,0x3e,0x7a,0xba,0xdc,0x7a,0x93,0xfe,
+  0xd2,0xee,0x82,0xb1,0x52,0x6b,0x35,0xf7,0x81,0xfd,0x75,0x2a,0xcd,0x9c,0xf2,0x76,
+  0xdc,0xac,0xb5,0x40,0x1b,0x38,0x0f,0x8c,0x8a,0x24,0x1d,0xa7,0x06,0xbf,0x92,0xbb,
+  0x8d,0x53,0x33,0xfc,0xc8,0xb0,0xe8,0x03,0x35,0x8a,0xc9,0x17,0x2f,0x60,0x02,0xde,
+  0x01,0x59,0xec,0x31,0x1c,0xa4,0x00,0xeb,0x3c,0x6a,0x92,0xb0,0xcc,0xa5,0xc8,0x8c,
+  0x7e,0x74,0x7e,0xf1,0xf8,0x8e,0x5b,0x1e,0x16,0xeb,0x22,0x71,0x58,0xf2,0x81,0x1b,
+  0x35,0xc5,0x93,0xbb,0x39,0xab,0x8b,0x9a,0xa5,0x18,0x1e,0xda,0xd5,0xbf,0x3e,0xec,
+  0x32,0xd1,0xbb,0x98,0xf1,0x6d,0x9e,0x68,0x80,0x09,0x0d,0x4d,0x3b,0x6f,0xf6,0xb7,
+  0x08,0x8b,0x05,0xe2,0x8b,0x32,0x82,0xcc,0x84,0xc1,0xd1,0xbb,0x0f,0xd3,0xa2,0x45,
+  0xfc,0xea,0xf1,0x34,0xdc,0x80,0x83,0x1e,0x89,0x9e,0x28,0xb0,0x3a,0x1f,0x66,0x0b,
+  0xb8,0xdf,0x49,0x50,0x2c,0xe0,0xb6,0xe8,0xff,0x58,0x80,0x62,0x65,0xb5,0x47,0x1e,
+  0x32,0x2b,0xb5,0xe6,0xef,0x43,0x32,0xf8,0x77,0x3e,0xe4,0xac,0x81,0x85,0x4d,0xd3,
+  0xfc,0x7b,0x11,0x0c,0xd3,0xa3,0x2f,0x21,0xcd,0x9a,0xad,0x1b,0xf8,0x90,0xd6,0xcd,
+  0x6a,0xd8,0x92,0xb2,0x6a,0x56,0x14,0x0f,0x13,0xfc,0xe6,0x8d,0xe0,0x4d,0x17,0x06,
+  0x90,0xdf,0x7e,0x28,0x2e,0xd3,0x93,0xd7,0xcb,0xf0,0xd0,0x04,0xb5,0x79,0x14,0x0f,
+  0xf9,0x2c,0x3e,0xf4,0x9f,0x69,0xa9,0x35,0x2b,0xda,0x22,0x19,0x0e,0xcf,0x2f,0x78,
+  0x38,0x34,0xb6,0xb8,0xf0,0xba,0x11,0x2d,0xb8,0xbf,0x47,0xf3,0x53,0xc4,0x53,0x24,
+  0x0e,0xe4,0xd1,0xd7,0x8d,0x8d,0x37,0xb5,0x6e,0x1a,0x87,0x86,0x9b,0xfb,0x69,0x01,
+  0x07,0x3c,0xc3,0x9d,0xc0,0x70,0x89,0x58,0x17,0x56,0x40,0x85,0xc9,0x3c,0x63,0xa2,
+  0xe9,0x53,0x00,0x31,0xf3,0x4d,0x9c,0x05,0x8e,0x88,0x96,0xd5,0x6b,0xa5,0x72,0xc3,
+  0x84,0x2d,0xa0,0xc4,0x33,0x85,0x34,0x58,0x0e,0x3a,0x4f,0xb9,0x53,0x08,0x8a,0x7f,
+  0x0a,0xd2,0xae,0xd1,0x00,0xc5,0x54,0x93,0x18,0x15,0x5e,0x25,0x82,0xdf,0x3a,0x82,
+  0xa3,0x96,0xb3,0x26,0xcd,0x9b,0x56,0xfb,0x5a,0xe2,0xbb,0x04,0x5b,0x8a,0xce,0x3a,
+  0x96,0x96,0x1d,0xec,0xe8,0xa9,0x43,0xca,0xf5,0x92,0x84,0x73,0x81,0x77,0x04,0xbd,
+  0x2e,0x59,0x8b,0x5d,0xe0,0x4b,0x68,0x92,0x6b,0x20,0x4c,0x1b,0x9a,0xd8,0x85,0x92,
+  0x68,0x51,0xf2,0x49,0x31,0x3f,0x22,0xe9,0xf1,0x0d,0xd7,0x8c,0xf8,0x90,0x0e,0x94,
+  0xcf,0x04,0x6d,0xa7,0xd2,0x0f,0xc9,0x85,0x2b,0x02,0x1d,0xed,0xd5,0x66,0x3c,0x0c,
+  0xa1,0x57,0xa6,0x1d,0xe4,0x73,0x34,0xa3,0x21,0x16,0xce,0xf0,0xdd,0x15,0xab,0x12,
+  0x0f,0xce,0x64,0x4c,0x32,0x41,0x62,0x11,0x6e,0xa1,0xf9,0x4a,0x80,0x69,0xe7,0x1d,
+  0x2a,0x5b,0xd0,0x84,0x87,0x5c,0x75,0x3f,0xcd,0x07,0x70,0x89,0xec,0x87,0xec,0x2c,
+  0x3c,0x2a,0x1f,0x21,0x07,0x20,0xcb,0xed,0x47,0xf4,0x12,0x9a,0xa3,0x68,0x7a,0x2e,
+  0x81,0x34,0x11,0x1f,0x32,0x32,0x01,0xde,0x32,0xf2,0x21,0xc6,0xc3,0x3d,0xde,0xee,
+  0xc7,0x10,0x0b,0xf9,0xb4,0xc0,0xc2,0x02,0x99,0xe7,0x41,0x68,0xb8,0x12,0x0f,0xce,
+  0xb7,0x9b,0x72,0xfe,0xfc,0xa4,0x8c,0x34,0x58,0xc5,0x32,0x6a,0xb6,0xdc,0xe0,0xc3,
+  0xb2,0x98,0x6f,0x82,0x0f,0xd5,0xf5,0x45,0x20,0xe3,0xb4,0x86,0xf3,0xa7,0x64,0x79,
+  0x79,0x13,0x59,0x8a,0xa1,0xc9,0xa1,0xa1,0xa1,0xc9,0x44,0x3c,0xc6,0x18,0x96,0x94,
+  0xf7,0x1d,0xdf,0x30,0x61,0x2f,0xae,0x23,0xa7,0x4a,0x52,0x24,0xeb,0x15,0x6b,0xd8,
+  0x82,0x06,0xea,0x86,0x91,0x28,0x1e,0x93,0xfa,0xb6,0xe4,0x43,0xce,0xba,0x30,0xdb,
+  0xc4,0x91,0x0f,0x59,0x1d,0x0b,0x9b,0x06,0x94,0xf5,0x35,0xec,0xb5,0x96,0x78,0xd5,
+  0x33,0x17,0x63,0x5d,0x48,0x83,0x58,0x62,0x0b,0x3e,0x9c,0x43,0x12,0xdb,0x3b,0x87,
+  0x09,0xa3,0x22,0xf8,0x70,0x0e,0x94,0xf5,0xc5,0xae,0xca,0x24,0x83,0x39,0xb7,0xec,
+  0x49,0x53,0xc2,0xfc,0x63,0xbb,0xf0,0x6d,0x62,0xf3,0x3f,0x04,0x16,0xa2,0x4e,0xac,
+  0x9d,0x37,0xd7,0x17,0xf6,0xe7,0xd3,0xd0,0x0e,0x89,0x8c,0x59,0xe1,0x01,0xdc,0x88,
+  0x63,0x46,0xae,0xc0,0x4c,0x1f,0xe6,0x9f,0x18,0xa9,0xac,0x61,0x8e,0x46,0x53,0x52,
+  0xd7,0x57,0xc0,0x8e,0xc0,0x7e,0x88,0xcf,0xd6,0xaa,0xfc,0x08,0xd9,0x4f,0xb2,0xbc,
+  0xf2,0x88,0x9e,0x6f,0x11,0x77,0x90,0x3f,0x9a,0x3e,0x92,0xdc,0x1f,0xc7,0x3b,0xc8,
+  0x9b,0xe3,0x53,0xc4,0xf2,0xfb,0x9b,0xc1,0xfe,0x53,0xf1,0x05,0xf8,0x05,0xf8,0x2c,
+  0x65,0xc5,0x29,0x7c,0x88,0xb9,0x53,0x9a,0x95,0x46,0x8b,0x7a,0xbf,0x28,0x0c,0xb0,
+  0x96,0x62,0x7c,0xa2,0xb2,0xc0,0xfb,0x59,0x4b,0x26,0xee,0xc0,0x3d,0xda,0x5f,0x48,
+  0x15,0x43,0xc3,0x52,0x13,0x71,0xc7,0x5a,0x25,0x56,0x33,0x9e,0x2c,0x0d,0x56,0x5c,
+  0x7f,0xc4,0x85,0x1f,0x95,0x99,0x30,0xa6,0x7d,0x2d,0x6c,0x49,0xd9,0xd7,0x21,0x58,
+  0x29,0x08,0xc3,0x2d,0x65,0x7c,0xa0,0x1b,0xb3,0xb4,0xfa,0xf2,0xe4,0xee,0x67,0xbc,
+  0xd7,0x8a,0xd6,0x57,0xa1,0xc1,0x87,0x3c,0x77,0x4e,0x98,0x4e,0xeb,0x63,0xe4,0x43,
+  0x4b,0x60,0xe1,0x22,0x9c,0xb3,0xcd,0x90,0x0f,0x9b,0xe3,0x99,0x67,0xb9,0xd7,0xed,
+  0xb4,0x93,0xcf,0xf3,0x13,0xd3,0x45,0xdb,0x31,0xf2,0xc4,0x62,0x0c,0xd3,0x8e,0x81,
+  0xf9,0x27,0x07,0xd8,0x42,0xf3,0x40,0xa2,0xf5,0x8e,0xf3,0x21,0xac,0x8c,0xbb,0x64,
+  0xe6,0xb3,0x66,0x0d,0x39,0x37,0x41,0x14,0x31,0xc4,0xac,0xd7,0x0b,0x25,0x88,0x78,
+  0x5e,0xf0,0x21,0x87,0x2a,0x43,0x1a,0xa4,0xb1,0x32,0x43,0x50,0xa4,0x2a,0x28,0x86,
+  0x26,0xea,0xcd,0xf2,0xaf,0x91,0x49,0x46,0x1f,0x9c,0x7d,0xc5,0x6d,0x49,0xb4,0xb1,
+  0xf5,0x07,0x9d,0x87,0x53,0x2d,0xf1,0x49,0x34,0x03,0x87,0x8d,0xd7,0xea,0x46,0xc9,
+  0x3f,0x78,0xbd,0x3d,0x17,0x33,0x4b,0xc8,0x87,0xef,0xfe,0xbe,0x47,0xec,0xfe,0x7b,
+  0xbc,0x74,0x2d,0x31,0x23,0x79,0xa0,0xbd,0x01,0x06,0x4a,0xfe,0x01,0xf8,0xda,0x5b,
+  0x23,0x0f,0xdf,0xbd,0xbd,0xfc,0x9d,0x1b,0x2f,0xbe,0x35,0x26,0xf8,0xf0,0xfd,0x3a,
+  0x1f,0x2e,0x47,0x7c,0xb8,0xeb,0x19,0xf7,0x50,0xc4,0x87,0xc7,0x05,0x1f,0xee,0xd4,
+  0xf9,0xf0,0x69,0xc4,0x87,0xbb,0x78,0xec,0xf3,0xea,0xab,0x02,0x0b,0xff,0x5a,0xd9,
+  0xd9,0x1e,0xda,0xaa,0x83,0x22,0x12,0xe3,0x73,0xf8,0x50,0xfe,0xf4,0xbf,0x6f,0x62,
+  0xff,0x4f,0x1b,0xa0,0x78,0xf9,0x79,0x7c,0x38,0xd8,0xe0,0xc3,0xee,0x03,0xe3,0x1b,
+  0xf3,0xfd,0x9b,0x4f,0x1e,0x0f,0x5d,0x7a,0xa6,0xff,0xe3,0x2f,0x1e,0xbd,0x0f,0x1e,
+  0x11,0x2f,0x28,0x7c,0xc8,0xa6,0xbe,0xf8,0x59,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,
+  0xb4,0xb4,0xb4,0xb4,0xfe,0xdf,0x25,0x6b,0x07,0xaa,0x6b,0x07,0x2d,0x2d,0x2d,0x2d,
+  0x2d,0x2d,0x2d,0x2d,0x2d,0x2d,0xad,0xe7,0x4b,0xd6,0x0e,0x09,0x5d,0x3b,0x68,0x69,
+  0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x3d,0x5f,0xb2,0x76,0x30,0x65,0xed,
+  0xf0,0xbf,0x0e,0x45,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0xeb,0xbf,
+  0x28,0x5f,0xfc,0xd1,0x24,0xf8,0xe7,0x79,0x1f,0xb8,0xf8,0xce,0x53,0xdc,0x07,0xf6,
+  0xb9,0xdf,0x27,0xd4,0x3f,0x6b,0xf8,0x50,0x25,0xd1,0x39,0x1f,0x9f,0x7e,0xb6,0xdf,
+  0xbf,0x00,0x34,0x34,0xbf,0x69,0xee,0x33,0x01,0x00,
diff --git a/u-boot/board/esd/wuh405/wuh405.c b/u-boot/board/esd/wuh405/wuh405.c
new file mode 100644
index 0000000..d8d4bb5
--- /dev/null
+++ b/u-boot/board/esd/wuh405/wuh405.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10); /* wait 10us */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)(DUART0_BA + 4), 0x08);
+	out_8((void *)(DUART1_BA + 4), 0x08);
+	out_8((void *)(DUART2_BA + 4), 0x08);
+	out_8((void *)(DUART3_BA + 4), 0x08);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming WUH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
diff --git a/u-boot/board/espt/Makefile b/u-boot/board/espt/Makefile
new file mode 100644
index 0000000..4ecef4a
--- /dev/null
+++ b/u-boot/board/espt/Makefile
@@ -0,0 +1,50 @@
+#
+# Copyright (C) 2009 Renesas Solutions Corp.
+# Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/espt/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= espt.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/espt/espt.c b/u-boot/board/espt/espt.c
new file mode 100644
index 0000000..44ab635
--- /dev/null
+++ b/u-boot/board/espt/espt.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/espt.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: ESPT-GIGA\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
diff --git a/u-boot/board/espt/lowlevel_init.S b/u-boot/board/espt/lowlevel_init.S
new file mode 100644
index 0000000..1a11eee
--- /dev/null
+++ b/u-boot/board/espt/lowlevel_init.S
@@ -0,0 +1,332 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write32 WDTCSR_A, WDTCSR_D
+
+	write32 WDTST_A, WDTST_D
+
+	write32 WDTBST_A, WDTBST_D
+
+	write32 CCR_A, CCR_CACHE_ICI_D
+
+	write32 MMUCR_A, MMU_CONTROL_TI_D
+
+	write32 MSTPCR0_A, MSTPCR0_D
+
+	write32 MSTPCR1_A, MSTPCR1_D
+
+	write32 RAMCR_A, RAMCR_D
+
+	/*
+	 * Setting infomation from
+	 * original ESPT-GIGA bootloader register
+	 */
+	write32 MMSEL_A, MMSEL_D
+
+	/* dummy */
+	mov.l   @r1, r2
+	mov.l   @r1, r2
+	synco
+
+    write32 BCR_A, BCR_D
+
+    write32 CS0BCR_A, CS0BCR_D
+
+    write32 CS0WCR_A, CS0WCR_D
+
+	/*
+	 * DDR-SDRAM setting
+	 */
+
+	/* set DDR-SDRAM dummy read */
+	write32 MMSEL_A, MMSEL_D
+
+	write32 MMSEL_A, CS0_A
+
+	/* set DDR-SDRAM bus/endian etc */
+	write32 MIM_U_A, MIM_U_D
+
+	write32 MIM_L_A, MIM_L_D0
+
+	write32 SDR_L_A, SDR_L_A_D0
+
+	write32 STR_L_A, STR_L_A_D0
+
+	/* DDR-SDRAM access control */
+	write32 MIM_L_A, MIM_L_D1
+
+	write32 SCR_L_A, SCR_L_A_D0
+
+	write32 SCR_L_A, SCR_L_A_D1
+
+	write32 EMRS_A, EMRS_D
+
+	write32 MRS1_A, MRS1_D
+
+	write32 MIM_U_A, MIM_U_D
+
+	write32 MIM_L_A, MIM_L_A_D2
+
+	write32 SCR_L_A, SCR_L_A_D2
+
+	write32 SCR_L_A, SCR_L_A_D2
+
+	write32 MRS2_A, MRS2_D
+
+	/* wait 200us */
+	wait_timer REPEAT_R3
+
+	/* GPIO setting */
+	write16 PSEL0_A, PSEL0_D
+
+	write16 PSEL1_A, PSEL1_D
+
+	write16 PSEL2_A, PSEL2_D
+
+	write16 PSEL3_A, PSEL3_D
+
+	write16 PSEL4_A, PSEL4_D
+
+	write8 PADR_A, PADR_D
+
+	write16 PACR_A, PACR_D
+
+	write8 PBDR_A, PBDR_D
+
+	write16 PBCR_A, PBCR_D
+
+	write8 PCDR_A, PCDR_D
+
+	write16 PCCR_A, PCCR_D
+
+	write8	PDDR_A, PDDR_D
+
+	write16 PDCR_A, PDCR_D
+
+	write16 PECR_A, PECR_D
+
+	write16 PFCR_A, PFCR_D
+
+	write16 PGCR_A, PGCR_D
+
+	write16 PHCR_A, PHCR_D
+
+	write16 PICR_A, PICR_D
+
+	write8 PJDR_A, PJDR_D
+
+	write16 PJCR_A, PJCR_D
+
+	/* wait 50us */
+	wait_timer REPEAT_R3
+
+	write8 PKDR_A, PKDR_D
+
+	write16 PKCR_A, PKCR_D
+
+	write16 PLCR_A, PLCR_D
+
+	write16 PMCR_A, PMCR_D
+
+	write16 PNCR_A, PNCR_D
+
+	write16 POCR_A, POCR_D
+
+
+	/* ICR0 ,ICR1 */
+	write32 ICR0_A, ICR0_D
+
+	write32 ICR1_A, ICR1_D
+
+	/* USB Host */
+	write32 USB_USBHSC_A, USB_USBHSC_D
+
+	write32 CCR_A, CCR_CACHE_D_2
+
+	rts
+	nop
+
+	.align	2
+
+/* GPIO Crontrol Register */
+PACR_A:	.long	0xFFEF0000
+PBCR_A:	.long	0xFFEF0002
+PCCR_A:	.long	0xFFEF0004
+PDCR_A:	.long	0xFFEF0006
+PECR_A:	.long	0xFFEF0008
+PFCR_A:	.long	0xFFEF000A
+PGCR_A:	.long	0xFFEF000C
+PHCR_A:	.long	0xFFEF000E
+PICR_A:	.long	0xFFEF0010
+PJCR_A:	.long	0xFFEF0012
+PKCR_A:	.long	0xFFEF0014
+PLCR_A:	.long	0xFFEF0016
+PMCR_A:	.long	0xFFEF0018
+PNCR_A:	.long	0xFFEF001A
+POCR_A:	.long	0xFFEF001C
+
+/* GPIO Data Register */
+PADR_A:	.long	0xFFEF0020
+PBDR_A:	.long	0xFFEF0022
+PCDR_A:	.long	0xFFEF0024
+PDDR_A:	.long	0xFFEF0026
+PJDR_A:	.long	0xFFEF0032
+PKDR_A:	.long	0xFFEF0034
+
+/* GPIO Set data */
+PADR_D:	.long	0x00000000
+PACR_D:	.word 	0x1400
+.align 2
+PBDR_D:	.long	0x00000000
+PBCR_D:	.word	0x555A
+.align 2
+PCDR_D:	.long	0x00000000
+PCCR_D:	.word	0x5555
+.align 2
+PDDR_D:	.long	0x00000000
+PDCR_D:	.word	0x0155
+PECR_D:	.word	0x0000
+PFCR_D:	.word	0x0000
+PGCR_D:	.word	0x0000
+PHCR_D:	.word	0x0000
+PICR_D:	.word	0x0800
+PJDR_D:	.long	0x00000006
+PJCR_D:	.word	0x5A57
+.align 2
+PKDR_D:	.long	0x00000000
+PKCR_D:	.word	0xFFF9
+.align 2
+PLCR_D:	.word 	0xC330
+PMCR_D:	.word	0xFFFF
+PNCR_D:	.word	0x0242
+POCR_D:	.word	0x0000
+
+/* Pin Select */
+PSEL0_A:	.long	0xFFEF0070
+PSEL1_A:	.long	0xFFEF0072
+PSEL2_A:	.long	0xFFEF0074
+PSEL3_A:	.long	0xFFEF0076
+PSEL4_A:	.long	0xFFEF0078
+PSEL0_D:	.word	0x0001
+PSEL1_D:	.word	0x2400
+PSEL2_D:	.word	0x0000
+PSEL3_D:	.word	0x2421
+PSEL4_D:	.word	0x0000
+.align 2
+
+MMSEL_A:	.long	0xFE600020
+BCR_A:		.long	0xFF801000
+CS0BCR_A:	.long	0xFF802000
+CS0WCR_A:	.long	0xFF802008
+ICR0_A:		.long	0xFFD00000
+ICR1_A:		.long	0xFFD0001C
+
+MMSEL_D:	.long	0xA5A50000
+BCR_D:		.long	0x05000000
+CS0BCR_D:	.long	0x232306F0
+CS0WCR_D:	.long	0x00011104
+ICR0_D:		.long	0x80C00000
+ICR1_D:		.long	0x00020000
+
+/* RWBT Address */
+WDTST_A:	.long	0xFFCC0000
+WDTCSR_A:	.long	0xFFCC0004
+WDTBST_A:	.long	0xFFCC0008
+/* RWBT Data */
+WDTST_D:	.long	0x5A000FFF
+WDTCSR_D:	.long	0xA5000000
+WDTBST_D:	.long	0x55000000
+
+/* Cache Address */
+CCR_A:		.long	0xFF00001C
+MMUCR_A:	.long	0xFF000010
+RAMCR_A:	.long	0xFF000074
+
+/* Cache Data */
+CCR_CACHE_ICI_D:.long	0x00000800
+CCR_CACHE_D_2:	.long	0x00000103
+MMU_CONTROL_TI_D:.long	0x00000004
+RAMCR_D:	.long	0x00000200
+
+/* Low power mode control Address */
+MSTPCR0_A:	.long	0xFFC80030
+MSTPCR1_A:	.long	0xFFC80038
+/* Low power mode control Data */
+MSTPCR0_D:	.long	0x00000000
+MSTPCR1_D:	.long	0x00000000
+
+REPEAT0_R3:	.long	0x00002000
+REPEAT_R3:	.long	0x00000200
+CS0_A:		.long	0xA8000000
+
+MIM_U_A:	.long	0xFE800008
+MIM_L_A:	.long	0xFE80000C
+SCR_U_A:	.long	0xFE800010
+SCR_L_A:	.long	0xFE800014
+STR_U_A:	.long	0xFE800018
+STR_L_A:	.long	0xFE80001C
+SDR_U_A:	.long	0xFE800030
+SDR_L_A:	.long	0xFE800034
+EMRS_A:		.long	0xFE902000
+MRS1_A:		.long	0xFE900B08
+MRS2_A:		.long	0xFE900308
+
+MIM_U_D:	.long	0x00000000
+MIM_L_D0:	.long	0x04100008
+MIM_L_D1:	.long	0x02EE0009
+MIM_L_D2:	.long	0x02EE0209
+
+SDR_L_A_D0:	.long	0x00000300
+STR_L_A_D0:	.long	0x00010040
+MIM_L_A_D1:	.long	0x04100009
+SCR_L_A_D0:	.long 	0x00000003
+SCR_L_A_D1:	.long 	0x00000002
+MIM_L_A_D2:	.long	0x04100209
+SCR_L_A_D2:	.long	0x00000004
+
+SCR_L_NORMAL:	.long	0x00000000
+SCR_L_NOP:		.long	0x00000001
+SCR_L_PALL:		.long	0x00000002
+SCR_L_CKE_EN:	.long	0x00000003
+SCR_L_CBR:		.long	0x00000004
+
+STR_L_D:	.long	0x000F3980
+SDR_L_D:	.long	0x00000400
+EMRS_D:		.long	0x00000000
+MRS1_D:		.long	0x00000000
+MRS2_D:		.long	0x00000000
+
+/* USB */
+USB_USBHSC_A:	.long	0xFFEC80F0
+USB_USBHSC_D:	.long	0x00000000
diff --git a/u-boot/board/esteem192e/Makefile b/u-boot/board/esteem192e/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/esteem192e/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/esteem192e/esteem192e.c b/u-boot/board/esteem192e/esteem192e.c
new file mode 100644
index 0000000..b784cbb
--- /dev/null
+++ b/u-boot/board/esteem192e/esteem192e.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Modified By Conn Clark to work with Esteem 192E 7/31/00
+ *
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 *
+	 * active, NOP, read, precharge, NOP */
+	0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
+	0x11FFCC05,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 * NOP, Program
+	 */
+	0x0F0A8C34, 0x1F354C37,	/* last */
+
+	_NOT_USED_,		/* Not used */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
+	0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
+	0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 * active, NOP, write, NOP, precharge, NOP */
+	0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
+	0x0FF74C04, 0x1FFFCC05,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
+	0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
+	0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 * precharge, NOP, auto_ref, NOP, NOP, NOP */
+	0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
+	0x0FFFCCB4, 0x1FFFCC35,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x0FFB8C00, 0x1FF74C03,	/* last */
+	_NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Esteem 192E\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1;
+
+	/*
+	 * Explain frequency of refresh here
+	 */
+
+	memctl->memc_mptpr = 0x0200;	/* divide by 32 */
+
+	memctl->memc_mamr = 0x18003112;	/*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	/* not defined yet */
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+
+	/* perform SDRAM initializsation sequence */
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 0 execute 8 refresh */
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+
+	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 1 execute 8 refresh */
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* 0x18803112  start refresh timer TODO: explain here */
+
+/* printf ("banks 0 and 1 are programed\n"); */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 */
+	size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
+
+/* printf ("bank 1 size %u\n",size_b1); */
+
+	if (size_b1 == 0) {
+		/*
+		 * Adjust refresh rate if bank 0 isn't stuffed
+		 */
+		memctl->memc_mptpr = 0x0400;	/* divide by 64 */
+		memctl->memc_br3 &= 0x0FFFFFFFE;
+
+		/*
+		 * Adjust OR2 for size of bank 0
+		 */
+		memctl->memc_or2 |= 7 * size_b0;
+	} else {
+		if (size_b0 < size_b1) {
+			memctl->memc_br2 &= 0x00007FFE;
+			memctl->memc_br3 &= 0x00007FFF;
+
+			/*
+			 * Adjust OR3 for size of bank 1
+			 */
+			memctl->memc_or3 |= 15 * size_b1;
+
+			/*
+			 * Adjust OR2 for size of bank 0
+			 */
+			memctl->memc_or2 |= 15 * size_b0;
+			memctl->memc_br2 += (size_b1 + 1);
+		} else {
+			memctl->memc_br3 &= 0x00007FFE;
+
+			/*
+			 * Adjust OR2 for size of bank 0
+			 */
+			memctl->memc_or2 |= 15 * size_b0;
+
+			/*
+			 * Adjust OR3 for size of bank 1
+			 */
+			memctl->memc_or3 |= 15 * size_b1;
+			memctl->memc_br3 += (size_b0 + 1);
+		}
+	}
+
+	/* before leaving set all unused i/o pins to outputs */
+
+	/*
+	 *      --*Unused Pin List*--
+	 *
+	 * group/port           bit number
+	 * IP_B                 0,1,3,4,5  Taken care of in pcmcia-cs-x.x.xx
+	 * PA                   5,7,8,9,14,15
+	 * PB                   22,23,31
+	 * PC                   4,5,6,7,10,11,12,13,14,15
+	 * PD                   5,6,7
+	 *
+	 */
+
+	/*
+	 *   --*Pin Used for I/O List*--
+	 *
+	 * port     input bit number    output bit number    either
+	 * PB                           18,26,27
+	 * PD       3,4                                      8,9,10,11,12,13,14,15
+	 *
+	 */
+
+	immap->im_ioport.iop_papar &= ~0x05C3;	/* set pins as io */
+	immap->im_ioport.iop_padir |= 0x05C3;	/* set pins as output */
+	immap->im_ioport.iop_paodr &= 0x0008;	/* config pins 9 & 14 as normal outputs */
+	immap->im_ioport.iop_padat |= 0x05C3;	/* set unused pins as high */
+
+	immap->im_cpm.cp_pbpar &= ~0x00001331;	/* set unused port b pins as io */
+	immap->im_cpm.cp_pbdir |= 0x00001331;	/* set unused port b pins as output */
+	immap->im_cpm.cp_pbodr &= ~0x00001331;	/* config bits 18,22,23,26,27 & 31 as normal outputs */
+	immap->im_cpm.cp_pbdat |= 0x00001331;	/* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
+
+	immap->im_ioport.iop_pcpar &= ~0x0F3F;	/* set unused port c pins as io */
+	immap->im_ioport.iop_pcdir |= 0x0F3F;	/* set unused port c pins as output */
+	immap->im_ioport.iop_pcso &= ~0x0F3F;	/* clear special purpose bit for unused port c pins for clarity */
+	immap->im_ioport.iop_pcdat |= 0x0F3F;	/* set unused port c pins high */
+
+	immap->im_ioport.iop_pdpar &= 0xE000;	/* set pins as io */
+	immap->im_ioport.iop_pddir &= 0xE000;	/* set bit 3 & 4 as inputs */
+	immap->im_ioport.iop_pddir |= 0x07FF;	/* set bits 5 - 15 as outputs */
+	immap->im_ioport.iop_pddat = 0x0055;	/* set alternating pattern on test port */
+
+	return (size_b0 + size_b1);
+}
diff --git a/u-boot/board/esteem192e/flash.c b/u-boot/board/esteem192e/flash.c
new file mode 100644
index 0000000..cce73fa
--- /dev/null
+++ b/u-boot/board/esteem192e/flash.c
@@ -0,0 +1,1135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+#ifdef CONFIG_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define	FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
+
+#ifndef CONFIG_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t * info, ulong dest, ushort data);
+#endif
+/*int flash_write (uchar *, ulong, ulong); */
+/*flash_info_t *addr2info (ulong);   */
+
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *)
+				FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
+	}
+
+	size_b1 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *)
+				FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1 << 20, size_b0, size_b0 << 20);
+		flash_info[0].flash_id = FLASH_UNKNOWN;
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[0].sector_count = -1;
+		flash_info[1].sector_count = -1;
+		flash_info[0].size = 0;
+		flash_info[1].size = 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = CONFIG_SYS_FLASH_BASE | 0x00000801;	/*  (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
+
+	/* Re-do sizing to get full correct info */
+
+	size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE,
+				  &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 =
+			CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 =
+			(CONFIG_SYS_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
+		/*((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		   BR_MS_GPCM | BR_V; */
+
+		/* Re-do sizing to get full correct info */
+		size_b1 =
+			flash_get_size ((volatile FLASH_WORD_SIZE
+					 *) (CONFIG_SYS_FLASH_BASE + size_b0),
+					&flash_info[1]);
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CONFIG_SYS_MONITOR_BASE,
+				      CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;	/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[] = ", bottom boot sect)\n";
+	uchar topboot[] = ", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	if (info->flash_id & 0x0001) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800B:
+		printf ("INTEL28F800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800T:
+		printf ("INTEL28F800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160B:
+		printf ("INTEL28F160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160T:
+		printf ("INTEL28F160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320B:
+		printf ("INTEL28F320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320T:
+		printf ("INTEL28F320T (32 Mbit%s", boottype);
+		break;
+
+#if 0				/* enable when devices are available */
+
+	case FLASH_INTEL640B:
+		printf ("INTEL28F640B (64 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL640T:
+		printf ("INTEL28F640T (64 Mbit%s", boottype);
+		break;
+#endif
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
+{
+	short i;
+	ulong base = (ulong) addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CONFIG_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if (addr[0x0000] != 0x00890089) {
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if (addr[0x0000] != 0x0089) {
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+
+	}
+
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0				/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+#if 0				/* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
+#ifndef CONFIG_FLASH_16BIT
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+#else
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+#endif
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
+
+
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
+#ifndef CONFIG_FLASH_16BIT
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
+				}
+#else
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
+#endif
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
+		}
+
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+#ifndef CONFIG_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CONFIG_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i = 0; i < 2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_short (info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CONFIG_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id > FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+	*((vu_long *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id > FLASH_AMD_COMP) {
+
+		while ((*((vu_long *) dest) & 0x00800080) !=
+		       (data & 0x00800080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+
+		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+
+			if (addr[0] & 0x003A003A) {	/* check for error */
+				barf = addr[0] & 0x003A0000;
+				if (barf) {
+					barf >>= 16;
+				} else {
+					barf = addr[0] & 0x0000003A;
+				}
+				printf ("\nFlash write error at address %lx\n", (unsigned long) dest);
+				if (barf & 0x0002)
+					printf ("Block locked, not erased.\n");
+				if (barf & 0x0010)
+					printf ("Programming error.\n");
+				if (barf & 0x0008)
+					printf ("Vpp Low error.\n");
+				return (2);
+			}
+
+
+		}
+
+		return (0);
+
+	}
+
+#else
+
+static int write_short (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+		/* intel stuff */
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		if (addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+		*addr = 0x00FF;
+	}
+	return (0);
+}
+
+#endif
+/*-----------------------------------------------------------------------*/
diff --git a/u-boot/board/esteem192e/u-boot.lds b/u-boot/board/esteem192e/u-boot.lds
new file mode 100644
index 0000000..93b756b
--- /dev/null
+++ b/u-boot/board/esteem192e/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    net/libnet.o			(.text*)
+    board/esteem192e/libesteem192e.o	(.text*)
+    *(.text.*printf)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/etin/debris/Makefile b/u-boot/board/etin/debris/Makefile
new file mode 100644
index 0000000..99a9c9d
--- /dev/null
+++ b/u-boot/board/etin/debris/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS =  $(BOARD).o flash.o phantom.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/etin/debris/debris.c b/u-boot/board/etin/debris/debris.c
new file mode 100644
index 0000000..33efe16
--- /dev/null
+++ b/u-boot/board/etin/debris/debris.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2000
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <net.h>
+#include <pci.h>
+#include <i2c.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Debris "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	return 0;
+}
+
+#if 0	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+phys_size_t initdram (int board_type)
+{
+	int m, row, col, bank, i;
+	unsigned long start, end;
+	uint32_t mccr1;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (i2c_reg_read (0x50, 2) != 0x04) return 0;	/* Memory type */
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	start = CONFIG_SYS_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_debris_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_debris_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*) dest;
+	volatile uchar *s = (volatile uchar*) src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+	return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*)dest;
+	volatile uchar *s = (volatile uchar*)src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+}
+
+int misc_init_r(void)
+{
+	uchar ethaddr[6];
+
+	if (eth_getenv_enetaddr("ethaddr", ethaddr))
+		/* Write ethernet addr in NVRAM for VxWorks */
+		nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
+				ethaddr, 6);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/etin/debris/flash.c b/u-boot/board/etin/debris/flash.c
new file mode 100644
index 0000000..f9e8619
--- /dev/null
+++ b/u-boot/board/etin/debris/flash.c
@@ -0,0 +1,721 @@
+/*
+ * board/eva/flash.c
+ *
+ * (C) Copyright 2002
+ * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <mpc824x.h>
+#include <asm/mmu.h>
+
+int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
+int (*write_dword)(flash_info_t*, ulong, uint64_t);
+
+typedef uint64_t cfi_word;
+
+#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
+
+#define cfi_write(flash, val, addr) \
+	move64((cfi_word*)&val, \
+			(cfi_word*)(flash->start[0] + addr))
+
+#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
+
+static void write32(unsigned long addr, uint32_t value)
+{
+	*(volatile uint32_t*)(addr) = value;
+	asm volatile("sync");
+}
+
+static uint32_t read32(unsigned long addr)
+{
+	uint32_t value;
+	value = *(volatile uint32_t*)addr;
+	asm volatile("sync");
+	return value;
+}
+
+static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
+{
+	uint32_t base = flash->start[0];
+	uint32_t val=(cmd << 16) | cmd;
+	addr <<= 3;
+	write32(base + addr, val);
+	return addr;
+}
+
+static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
+{
+	uint32_t base = flash->start[0];
+	addr <<= 3;
+	return (uint16_t)read32(base + addr);
+}
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static void move64(uint64_t *src, uint64_t *dest)
+{
+	asm volatile("lfd  0, 0(3)\n\t" /* fpr0   =  *scr       */
+	 "stfd 0, 0(4)"         /* *dest  =  fpr0       */
+	 : : : "fr0" );         /* Clobbers fr0         */
+	return;
+}
+
+static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
+{
+	unsigned long start;
+	cfi_word status = 0;
+
+	status = cfi_read(flash, dest);
+	data &= status;
+
+	cfi_cmd(flash, 0x40, 0);
+	cfi_write(flash, data, dest);
+
+	udelay(10);
+	start = get_timer (0);
+	for(;;) {
+		status = cfi_read(flash, dest);
+		status &= CMD(0x80);
+		if(status == CMD(0x80))
+			break;
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			cfi_cmd(flash, 0xff, 0);
+			return 1;
+		}
+		udelay(1);
+	}
+	cfi_cmd(flash, 0xff, 0);
+
+	return 0;
+}
+
+static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
+{
+	ulong start;
+	cfi_word status = 0;
+
+	status = cfi_read(flash, dest);
+	if(status != CMD(0xffff)) return 2;
+
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	cfi_cmd(flash, 0xa0, 0x555);
+
+	cfi_write(flash, data, dest);
+
+	udelay(10);
+	start = get_timer (0);
+	status = ~data;
+	while(status != data) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+			return 1;
+		status = cfi_read(flash, dest);
+		udelay(1);
+	}
+	return 0;
+}
+
+static __inline__ unsigned long get_msr(void)
+{
+	unsigned long msr;
+	__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+	return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
+
+int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	int i, s, l, rc;
+	cfi_word data;
+	uint8_t *t = (uint8_t*)&data;
+	unsigned long base = flash->start[0];
+	uint32_t msr;
+
+	if (flash->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	if (cnt == 0)
+		return 0;
+
+	addr -= base;
+
+	msr = get_msr();
+	set_msr(msr|MSR_FP);
+
+	wp = (addr & ~7);   /* get lower word aligned address */
+
+	if((addr-wp) != 0) {
+		data = cfi_read(flash, wp);
+		s = addr & 7;
+		l = ( cnt < (8-s) ) ? cnt : (8-s);
+		for(i = 0; i < l; i++)
+			t[s+i] = *src++;
+		if ((rc = write_dword(flash, wp, data)) != 0)
+			goto DONE;
+		wp += 8;
+		cnt -= l;
+	}
+
+	while (cnt >= 8) {
+		for (i = 0; i < 8; i++)
+			t[i] = *src++;
+		if ((rc = write_dword(flash, wp, data)) != 0)
+			goto DONE;
+		wp  += 8;
+		cnt -= 8;
+	}
+
+	if (cnt == 0) {
+		rc = 0;
+		goto DONE;
+	}
+
+	data = cfi_read(flash, wp);
+	for(i = 0; i < cnt; i++)
+		t[i] = *src++;
+	rc = write_dword(flash, wp, data);
+DONE:
+	set_msr(msr);
+	return rc;
+}
+
+static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
+{
+	int sa;
+	int flag;
+	ulong start, last, now;
+	cfi_word status;
+
+	flag = disable_interrupts();
+
+	sa = (flash->start[sect] - flash->start[0]);
+	write32(flash->start[sect], 0x00200020);
+	write32(flash->start[sect], 0x00d000d0);
+
+	if (flag)
+		enable_interrupts();
+
+	udelay(1000);
+	start = get_timer (0);
+	last  = start;
+
+	for (;;) {
+		status = cfi_read(flash, sa);
+		status &= CMD(0x80);
+		if (status == CMD(0x80))
+			break;
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			cfi_cmd(flash, 0xff, 0);
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+
+		if ((now - last) > 1000) {
+			serial_putc ('.');
+			last = now;
+		}
+		udelay(10);
+	}
+	cfi_cmd(flash, 0xff, 0);
+	return ERR_OK;
+}
+
+static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
+{
+	int sect;
+	int rc = ERR_OK;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (flash->protect[sect] == 0) {
+			rc = cfi_erase_oneblock(flash, sect);
+			if (rc != ERR_OK) break;
+		}
+	}
+	printf (" done\n");
+	return rc;
+}
+
+static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
+{
+	int sect;
+	cfi_word status;
+	int sa = -1;
+	int flag;
+	ulong start, last, now;
+
+	flag = disable_interrupts();
+
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	cfi_cmd(flash, 0x80, 0x555);
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	for ( sect = s_first; sect <= s_last; sect++) {
+		if (flash->protect[sect] == 0) {
+			sa = flash->start[sect] - flash->start[0];
+			write32(flash->start[sect], 0x00300030);
+		}
+	}
+	if (flag)
+		enable_interrupts();
+
+	if (sa < 0)
+		goto DONE;
+
+	udelay (1000);
+	start = get_timer (0);
+	last  = start;
+	for(;;) {
+		status = cfi_read(flash, sa);
+		if (status == CMD(0xffff))
+			break;
+
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+
+		if ((now - last) > 1000) {
+			serial_putc ('.');
+			last = now;
+		}
+		udelay(10);
+	}
+DONE:
+	cfi_cmd(flash, 0xf0, 0);
+
+	printf (" done\n");
+
+	return ERR_OK;
+}
+
+int flash_erase (flash_info_t *flash, int s_first, int s_last)
+{
+	int sect;
+	int prot;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (flash->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return ERR_NOT_ERASED;
+	}
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return ERR_NOT_ERASED;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++)
+		if (flash->protect[sect]) prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+					                        prot);
+	else
+		printf ("\n");
+
+	return do_flash_erase(flash, s_first, s_last);
+}
+
+struct jedec_flash_info {
+	const uint16_t mfr_id;
+	const uint16_t dev_id;
+	const char *name;
+	const int DevSize;
+	const int InterfaceDesc;
+	const int NumEraseRegions;
+	const ulong regions[4];
+};
+
+#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
+
+#define SIZE_1MiB 20
+#define SIZE_2MiB 21
+#define SIZE_4MiB 22
+
+static const struct jedec_flash_info jedec_table[] = {
+	{
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV800T,
+		name: "AMD AM29LV800T",
+		DevSize: SIZE_1MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV800B,
+		name: "AMD AM29LV800B",
+		DevSize: SIZE_1MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+		          ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV160T,
+		name: "AMD AM29LV160T",
+		DevSize: SIZE_2MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,31),
+		          ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV160B,
+		name: "AMD AM29LV160B",
+		DevSize: SIZE_2MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x04000,1),
+		          ERASEINFO(0x02000,2),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x10000,31)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV320T,
+		name: "AMD AM29LV320T",
+		DevSize: SIZE_4MiB,
+		NumEraseRegions: 2,
+		regions: {ERASEINFO(0x10000,63),
+		          ERASEINFO(0x02000,8)
+		}
+
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV320B,
+		name: "AMD AM29LV320B",
+		DevSize: SIZE_4MiB,
+		NumEraseRegions: 2,
+		regions: {ERASEINFO(0x02000,8),
+		          ERASEINFO(0x10000,63)
+		}
+	}
+};
+
+static ulong cfi_init(uint32_t base,  flash_info_t *flash)
+{
+	int sector;
+	int block;
+	int block_count;
+	int offset = 0;
+	int reverse = 0;
+	int primary;
+	int mfr_id;
+	int dev_id;
+
+	flash->start[0] = base;
+	cfi_cmd(flash, 0xF0, 0);
+	cfi_cmd(flash, 0x98, 0);
+	if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
+		cfi_read_query(flash, 0x11) == 'R' &&
+		cfi_read_query(flash, 0x12) == 'Y' )) {
+		cfi_cmd(flash, 0xff, 0);
+		return 0;
+	}
+
+	flash->size = 1 << cfi_read_query(flash, 0x27);
+	flash->size *= 4;
+	block_count = cfi_read_query(flash, 0x2c);
+	primary = cfi_read_query(flash, 0x15);
+	if ( cfi_read_query(flash, primary + 4) == 0x30)
+		reverse = (cfi_read_query(flash, 0x1) & 0x01);
+	else
+		reverse = (cfi_read_query(flash, primary+15) == 3);
+
+	flash->sector_count = 0;
+
+	for ( block = reverse ? block_count - 1	: 0;
+		      reverse ? block >= 0	: block < block_count;
+		      reverse ? block--		: block ++) {
+		int sector_size =
+			(cfi_read_query(flash, 0x2d + block*4+2) |
+			(cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
+		int sector_count =
+			(cfi_read_query(flash, 0x2d + block*4+0) |
+			(cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
+		for(sector = 0; sector < sector_count; sector++) {
+			flash->start[flash->sector_count++] = base + offset;
+			offset += sector_size * 4;
+		}
+	}
+	mfr_id = cfi_read_query(flash, 0x00);
+	dev_id = cfi_read_query(flash, 0x01);
+
+	cfi_cmd(flash, 0xff, 0);
+
+	flash->flash_id = (mfr_id << 16) | dev_id;
+
+	for (sector = 0; sector < flash->sector_count; sector++) {
+		write32(flash->start[sector], 0x00600060);
+		write32(flash->start[sector], 0x00d000d0);
+	}
+	cfi_cmd(flash, 0xff, 0);
+
+	for (sector = 0; sector < flash->sector_count; sector++)
+		flash->protect[sector] = 0;
+
+	do_flash_erase = cfi_erase;
+	write_dword = cfi_write_dword;
+
+	return flash->size;
+}
+
+static ulong jedec_init(unsigned long base, flash_info_t *flash)
+{
+	int i;
+	int block, block_count;
+	int sector, offset;
+	int mfr_id, dev_id;
+	flash->start[0] = base;
+	cfi_cmd(flash, 0xF0, 0x000);
+	cfi_cmd(flash, 0xAA, 0x555);
+	cfi_cmd(flash, 0x55, 0x2AA);
+	cfi_cmd(flash, 0x90, 0x555);
+	mfr_id = cfi_read_query(flash, 0x000);
+	dev_id = cfi_read_query(flash, 0x0001);
+	cfi_cmd(flash, 0xf0, 0x000);
+
+	for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
+		if((jedec_table[i].mfr_id == mfr_id) &&
+			(jedec_table[i].dev_id == dev_id)) {
+
+			flash->flash_id = (mfr_id << 16) | dev_id;
+			flash->size = 1 << jedec_table[0].DevSize;
+			flash->size *= 4;
+			block_count = jedec_table[i].NumEraseRegions;
+			offset = 0;
+			flash->sector_count = 0;
+			for (block = 0; block < block_count; block++) {
+				int sector_size = jedec_table[i].regions[block];
+				int sector_count = (sector_size & 0xff) + 1;
+				sector_size >>= 8;
+				for (sector=0; sector<sector_count; sector++) {
+					flash->start[flash->sector_count++] =
+						base + offset;
+					offset += sector_size * 4;
+				}
+			}
+			break;
+		}
+	}
+
+	for (sector = 0; sector < flash->sector_count; sector++)
+		flash->protect[sector] = 0;
+
+	do_flash_erase = jedec_erase;
+	write_dword = jedec_write_dword;
+
+	return flash->size;
+}
+
+inline void mtibat1u(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   530, %0" :: "r" (x));
+}
+
+inline void mtibat1l(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   531, %0" :: "r" (x));
+}
+
+inline void mtdbat1u(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   538, %0" :: "r" (x));
+}
+
+inline void mtdbat1l(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   539, %0" :: "r" (x));
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	unsigned int msr;
+
+	/* BAT1 */
+	CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
+	CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
+	msr = get_msr();
+	set_msr(msr & ~(MSR_IR | MSR_DR));
+	mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	set_msr(msr);
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (!size)
+		size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN)
+		printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+
+	return size;
+}
+
+void flash_print_info  (flash_info_t *flash)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *p;
+
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		flash_init();
+	}
+
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (((flash->flash_id) >> 16) & 0xff) {
+	case 0x01:
+		printf ("AMD ");
+		break;
+	case 0x04:
+		printf("FUJITSU ");
+		break;
+	case 0x20:
+		printf("STM ");
+		break;
+	case 0xBF:
+		printf("SST ");
+		break;
+	case 0x89:
+	case 0xB0:
+		printf("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch ((flash->flash_id) & 0xffff) {
+	case (uint16_t)AMD_ID_LV800T:
+		printf ("AM29LV800T\n");
+		break;
+	case (uint16_t)AMD_ID_LV800B:
+		printf ("AM29LV800B\n");
+		break;
+	case (uint16_t)AMD_ID_LV160T:
+		printf ("AM29LV160T\n");
+		break;
+	case (uint16_t)AMD_ID_LV160B:
+		printf ("AM29LV160B\n");
+		break;
+	case (uint16_t)AMD_ID_LV320T:
+		printf ("AM29LV320T\n");
+		break;
+	case (uint16_t)AMD_ID_LV320B:
+		printf ("AM29LV320B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F800C3T:
+		printf ("28F800C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F800C3B:
+		printf ("28F800C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F160C3T:
+		printf ("28F160C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F160C3B:
+		printf ("28F160C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F320C3T:
+		printf ("28F320C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F320C3B:
+		printf ("28F320C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F640C3T:
+		printf ("28F640C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F640C3B:
+		printf ("28F640C3B\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (flash->size >= (1 << 20)) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+				flash->size >> 20, flash->sector_count);
+	} else {
+		printf ("  Size: %ld kB in %d Sectors\n",
+				flash->size >> 10, flash->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < flash->sector_count; ++i) {
+		/* Check if whole sector is erased*/
+		if (i != (flash->sector_count-1))
+			size = flash->start[i+1] - flash->start[i];
+		else
+			size = flash->start[0] + flash->size - flash->start[i];
+
+		erased = 1;
+		p = (volatile unsigned long *)flash->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*p++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s%s",
+			flash->start[i],
+			erased ? " E" : "  ",
+			flash->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
diff --git a/u-boot/board/etin/debris/phantom.c b/u-boot/board/etin/debris/phantom.c
new file mode 100644
index 0000000..63feb7c
--- /dev/null
+++ b/u-boot/board/etin/debris/phantom.c
@@ -0,0 +1,304 @@
+/*
+ * board/eva/phantom.c
+ *
+ * Phantom RTC device driver for EVA
+ *
+ * Author: Sangmoon Kim
+ *         dogoil@etinsys.com
+ *
+ * Copyright 2002 Etinsys Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if defined(CONFIG_CMD_DATE)
+
+#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
+
+#define RTC_YEAR                ( RTC_BASE + 7 )
+#define RTC_MONTH               ( RTC_BASE + 6 )
+#define RTC_DAY_OF_MONTH        ( RTC_BASE + 5 )
+#define RTC_DAY_OF_WEEK         ( RTC_BASE + 4 )
+#define RTC_HOURS               ( RTC_BASE + 3 )
+#define RTC_MINUTES             ( RTC_BASE + 2 )
+#define RTC_SECONDS             ( RTC_BASE + 1 )
+#define RTC_CENTURY             ( RTC_BASE + 0 )
+
+#define RTC_CONTROLA            RTC_CENTURY
+#define RTC_CONTROLB            RTC_SECONDS
+#define RTC_CONTROLC            RTC_DAY_OF_WEEK
+
+#define RTC_CA_WRITE            0x80
+#define RTC_CA_READ             0x40
+
+#define RTC_CB_OSC_DISABLE      0x80
+
+#define RTC_CC_BATTERY_FLAG     0x80
+#define RTC_CC_FREQ_TEST        0x40
+
+
+static int phantom_flag = -1;
+static int century_flag = -1;
+
+static uchar rtc_read(unsigned int addr)
+{
+	return *(volatile unsigned char *)(addr);
+}
+
+static void rtc_write(unsigned int addr, uchar val)
+{
+	*(volatile unsigned char *)(addr) = val;
+}
+
+static unsigned char phantom_rtc_sequence[] = {
+	0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
+};
+
+static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
+{
+	int i, j;
+	unsigned char v;
+	unsigned char save = rtc_read(addr);
+
+	for (j = 0; j < 8; j++) {
+		v = phantom_rtc_sequence[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	for (j = 0; j < 8; j++) {
+		v = 0;
+		for (i = 0; i < 8; i++) {
+			if(rtc_read(addr) & 1)
+				v |= 1 << i;
+		}
+		rtc[j] = v;
+	}
+	rtc_write(addr, save);
+	return rtc;
+}
+
+static void phantom_rtc_write(int addr, unsigned char rtc[8])
+{
+	int i, j;
+	unsigned char v;
+	unsigned char save = rtc_read(addr);
+	for (j = 0; j < 8; j++) {
+		v = phantom_rtc_sequence[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	for (j = 0; j < 8; j++) {
+		v = rtc[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	rtc_write(addr, save);
+}
+
+static int get_phantom_flag(void)
+{
+	int i;
+	unsigned char rtc[8];
+
+	phantom_rtc_read(RTC_BASE, rtc);
+
+	for(i = 1; i < 8; i++) {
+		if (rtc[i] != rtc[0])
+			return 1;
+	}
+	return 0;
+}
+
+void rtc_reset(void)
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag) {
+		unsigned char rtc[8];
+		phantom_rtc_read(RTC_BASE, rtc);
+		if(rtc[4] & 0x30) {
+			printf( "real-time-clock was stopped. Now starting...\n" );
+			rtc[4] &= 0x07;
+			phantom_rtc_write(RTC_BASE, rtc);
+		}
+	} else {
+		uchar reg_a, reg_b, reg_c;
+		reg_a = rtc_read( RTC_CONTROLA );
+		reg_b = rtc_read( RTC_CONTROLB );
+
+		if ( reg_b & RTC_CB_OSC_DISABLE )
+		{
+			printf( "real-time-clock was stopped. Now starting...\n" );
+			reg_a |= RTC_CA_WRITE;
+			reg_b &= ~RTC_CB_OSC_DISABLE;
+			rtc_write( RTC_CONTROLA, reg_a );
+			rtc_write( RTC_CONTROLB, reg_b );
+		}
+
+		/* make sure read/write clock register bits are cleared */
+		reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
+		rtc_write( RTC_CONTROLA, reg_a );
+
+		reg_c = rtc_read( RTC_CONTROLC );
+		if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
+			printf( "RTC battery low. Clock setting may not be reliable.\n");
+	}
+}
+
+static int get_century_flag(void)
+{
+	int flag = 0;
+	int bcd, century;
+	bcd = rtc_read( RTC_CENTURY );
+	century = bcd2bin( bcd & 0x3F );
+	rtc_write( RTC_CENTURY, bin2bcd(century+1));
+	if (bcd == rtc_read( RTC_CENTURY ))
+		flag = 1;
+	rtc_write( RTC_CENTURY, bcd);
+	return flag;
+}
+
+int rtc_get( struct rtc_time *tmp)
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag)
+	{
+		unsigned char rtc[8];
+
+		phantom_rtc_read(RTC_BASE, rtc);
+
+		tmp->tm_sec	= bcd2bin(rtc[1] & 0x7f);
+		tmp->tm_min	= bcd2bin(rtc[2] & 0x7f);
+		tmp->tm_hour	= bcd2bin(rtc[3] & 0x1f);
+		tmp->tm_wday	= bcd2bin(rtc[4] & 0x7);
+		tmp->tm_mday	= bcd2bin(rtc[5] & 0x3f);
+		tmp->tm_mon	= bcd2bin(rtc[6] & 0x1f);
+		tmp->tm_year	= bcd2bin(rtc[7]) + 1900;
+		tmp->tm_yday = 0;
+		tmp->tm_isdst = 0;
+
+		if( (rtc[3] & 0x80)  && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
+		if (tmp->tm_year < 1970) tmp->tm_year += 100;
+	} else {
+		uchar sec, min, hour;
+		uchar mday, wday, mon, year;
+
+		int century;
+
+		uchar reg_a;
+
+		if (century_flag < 0)
+			century_flag = get_century_flag();
+
+		reg_a = rtc_read( RTC_CONTROLA );
+		/* lock clock registers for read */
+		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
+
+		sec     = rtc_read( RTC_SECONDS );
+		min     = rtc_read( RTC_MINUTES );
+		hour    = rtc_read( RTC_HOURS );
+		mday    = rtc_read( RTC_DAY_OF_MONTH );
+		wday    = rtc_read( RTC_DAY_OF_WEEK );
+		mon     = rtc_read( RTC_MONTH );
+		year    = rtc_read( RTC_YEAR );
+		century = rtc_read( RTC_CENTURY );
+
+		/* unlock clock registers after read */
+		rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
+
+		tmp->tm_sec  = bcd2bin( sec  & 0x7F );
+		tmp->tm_min  = bcd2bin( min  & 0x7F );
+		tmp->tm_hour = bcd2bin( hour & 0x3F );
+		tmp->tm_mday = bcd2bin( mday & 0x3F );
+		tmp->tm_mon  = bcd2bin( mon & 0x1F );
+		tmp->tm_wday = bcd2bin( wday & 0x07 );
+
+		if (century_flag) {
+			tmp->tm_year = bcd2bin( year ) +
+				( bcd2bin( century & 0x3F ) * 100 );
+		} else {
+			tmp->tm_year = bcd2bin( year ) + 1900;
+			if (tmp->tm_year < 1970) tmp->tm_year += 100;
+		}
+
+		tmp->tm_yday = 0;
+		tmp->tm_isdst= 0;
+	}
+
+	return 0;
+}
+
+int rtc_set( struct rtc_time *tmp )
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag) {
+		uint year;
+		unsigned char rtc[8];
+
+		year = tmp->tm_year;
+		year -= (year < 2000) ? 1900 : 2000;
+
+		rtc[0] = bin2bcd(0);
+		rtc[1] = bin2bcd(tmp->tm_sec);
+		rtc[2] = bin2bcd(tmp->tm_min);
+		rtc[3] = bin2bcd(tmp->tm_hour);
+		rtc[4] = bin2bcd(tmp->tm_wday);
+		rtc[5] = bin2bcd(tmp->tm_mday);
+		rtc[6] = bin2bcd(tmp->tm_mon);
+		rtc[7] = bin2bcd(year);
+
+		phantom_rtc_write(RTC_BASE, rtc);
+	} else {
+		uchar reg_a;
+		if (century_flag < 0)
+			century_flag = get_century_flag();
+
+		/* lock clock registers for write */
+		reg_a = rtc_read( RTC_CONTROLA );
+		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
+
+		rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
+
+		rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
+		rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
+		rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
+		rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
+		rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
+
+		/* break year up into century and year in century */
+		if (century_flag) {
+			rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
+			rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
+			reg_a &= 0xc0;
+			reg_a |= bin2bcd( tmp->tm_year / 100 );
+		} else {
+			rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
+				((tmp->tm_year < 2000) ? 1900 : 2000)));
+		}
+
+		/* unlock clock registers after read */
+		rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
+	}
+
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/etin/debris/speed.h b/u-boot/board/etin/debris/speed.h
new file mode 100644
index 0000000..3f32a14
--- /dev/null
+++ b/u-boot/board/etin/debris/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK			CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/u-boot/board/etin/kvme080/Makefile b/u-boot/board/etin/kvme080/Makefile
new file mode 100644
index 0000000..644b4e3
--- /dev/null
+++ b/u-boot/board/etin/kvme080/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o multiverse.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/etin/kvme080/kvme080.c b/u-boot/board/etin/kvme080/kvme080.c
new file mode 100644
index 0000000..21616f5
--- /dev/null
+++ b/u-boot/board/etin/kvme080/kvme080.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+int checkboard(void)
+{
+	puts ("Board: KVME080\n");
+	return 0;
+}
+
+unsigned long setdram(int m, int row, int col, int bank)
+{
+	int i;
+	unsigned long start, end;
+	uint32_t mccr1;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	start = CONFIG_SYS_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned int msr;
+	long int size = 0;
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
+	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
+	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
+	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
+	mtmsr(msr);
+
+	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
+		size = 0x20000000;	/* 512MB */
+	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
+		size = 0x10000000;	/* 256MB */
+	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
+		size = 0x10000000;	/* 256MB */
+	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
+		size = 0x08000000;	/* 128MB */
+	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
+		size = 0x08000000;	/* 128MB */
+	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
+		size = 0x04000000;	/* 64MB */
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
+	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
+	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
+	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
+	mtmsr(msr);
+
+	return size;
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_early_init_f(void)
+{
+	*(volatile unsigned char *)(0xff080120) = 0xfb;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	unsigned int msr;
+
+	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
+	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
+	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtmsr(msr);
+
+	return 0;
+}
+
+extern int multiverse_init(void);
+
+int misc_init_r(void)
+{
+	multiverse_init();
+	return 0;
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*) dest;
+	volatile uchar *s = (volatile uchar*) src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+	return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*)dest;
+	volatile uchar *s = (volatile uchar*)src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/etin/kvme080/multiverse.c b/u-boot/board/etin/kvme080/multiverse.c
new file mode 100644
index 0000000..eb89581
--- /dev/null
+++ b/u-boot/board/etin/kvme080/multiverse.c
@@ -0,0 +1,186 @@
+/*
+ * multiverse.c
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ *	    dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "multiverse.h"
+
+static unsigned long vme_asi_addr;
+static unsigned long vme_iack_addr;
+static unsigned long pci_reg_addr;
+static unsigned long vme_reg_addr;
+
+int multiv_reset(unsigned long base)
+{
+	writeb(0x09, base + VME_SLAVE32_AM);
+	writeb(0x39, base + VME_SLAVE24_AM);
+	writeb(0x29, base + VME_SLAVE16_AM);
+	writeb(0x2f, base + VME_SLAVE_REG_AM);
+	writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
+	writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
+	writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
+#ifdef A32_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
+				base + VME_SLAVE32_MASK);
+		writeb(0x01, base + VME_SLAVE32_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE32_MASK);
+		writeb(0x00, base + VME_SLAVE32_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE32_MASK);
+	writeb(0x00, base + VME_SLAVE32_EN);
+#endif
+#ifdef A24_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
+				base + VME_SLAVE24_MASK);
+		writeb(0x01, base + VME_SLAVE24_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE24_MASK);
+		writeb(0x00, base + VME_SLAVE24_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE24_MASK);
+	writeb(0x00, base + VME_SLAVE24_EN);
+#endif
+#ifdef A16_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
+				base + VME_SLAVE16_MASK);
+		writeb(0x01, base + VME_SLAVE16_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE16_MASK);
+		writeb(0x00, base + VME_SLAVE16_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE16_MASK);
+	writeb(0x00, base + VME_SLAVE16_EN);
+#endif
+#ifdef REG_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
+				base + VME_SLAVE_REG_MASK);
+		writeb(0x01, base + VME_SLAVE_REG_EN);
+	} else {
+		writeb(0xf8, base + VME_SLAVE_REG_MASK);
+	}
+#else
+	writeb(0xf8, base + VME_SLAVE_REG_MASK);
+#endif
+	writeb(0x09, base + VME_MASTER32_AM);
+	writeb(0x39, base + VME_MASTER24_AM);
+	writeb(0x29, base + VME_MASTER16_AM);
+	writeb(0x2f, base + VME_MASTER_REG_AM);
+	writel(0x00000000, base + VME_RMW_ADRS);
+	writeb(0x00, base + VME_IRQ);
+	writeb(0x00, base + VME_INT_EN);
+	writel(0x00000000, base + VME_IRQ1_REG);
+	writel(0x00000000, base + VME_IRQ2_REG);
+	writel(0x00000000, base + VME_IRQ3_REG);
+	writel(0x00000000, base + VME_IRQ4_REG);
+	writel(0x00000000, base + VME_IRQ5_REG);
+	writel(0x00000000, base + VME_IRQ6_REG);
+	writel(0x00000000, base + VME_IRQ7_REG);
+	return 0;
+}
+
+void multiv_auto_slot_id(unsigned long base)
+{
+	unsigned int vector;
+	int slot_id = 1;
+	if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
+		*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
+		writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
+		writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
+				base + VME_CTRL);
+		while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
+		if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+			while (readb(base + VME_INT) & 0x04) {
+				vector = *(volatile unsigned int*)
+					(vme_iack_addr + VME_IACK2);
+				*(unsigned char*)(vme_asi_addr + 0x7ffff)
+					= (slot_id << 3) & 0xff;
+				slot_id ++;
+				if (slot_id > 31)
+					break;
+			}
+		}
+	}
+}
+
+int multiverse_init(void)
+{
+	int i;
+	pci_dev_t pdev;
+	unsigned int bar[6];
+
+	pdev = pci_find_device(0x1895, 0x0001, 0);
+
+	if (pdev == 0)
+		return -1;
+
+	for (i = 0; i < 6; i++)
+		pci_read_config_dword (pdev,
+				PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
+
+	pci_reg_addr = bar[0];
+	vme_reg_addr = bar[1] + 0x00F00000;
+	vme_iack_addr = bar[1] + 0x00200000;
+	vme_asi_addr = bar[3];
+
+	pci_write_config_dword (pdev, PCI_COMMAND,
+		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	writel(0xFF000000, pci_reg_addr + P_TA1);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL1);
+	writel(0xf0000000, pci_reg_addr + P_TA2);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL2);
+	writel(0xF1000000, pci_reg_addr + P_TA3);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL3);
+	writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
+	writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL5);
+
+	writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
+	writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
+	writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL1);
+
+	writel(0xF0000000, pci_reg_addr + W_BA2);
+	writel(0xFF000000, pci_reg_addr + W_AM2);
+	writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL2);
+
+	writel(0xFF000000, pci_reg_addr + W_BA3);
+	writel(0xFF000000, pci_reg_addr + W_AM3);
+	writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL3);
+
+	writel(0x00000001, pci_reg_addr + W_ERR_CS);
+	writel(0x00000001, pci_reg_addr + P_ERR_CS);
+
+	multiv_reset(vme_reg_addr);
+	writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
+		vme_reg_addr + VME_CTRL);
+
+	multiv_auto_slot_id(vme_reg_addr);
+
+	return 0;
+}
diff --git a/u-boot/board/etin/kvme080/multiverse.h b/u-boot/board/etin/kvme080/multiverse.h
new file mode 100644
index 0000000..776162d
--- /dev/null
+++ b/u-boot/board/etin/kvme080/multiverse.h
@@ -0,0 +1,176 @@
+/*
+ * multiverse.h
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ *	    dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MULTIVERSE_H__
+#define __MULTIVERSE_H__
+
+#define VME_A32_MSTR_BUS	0x90000000
+#define VME_A32_MSTR_SIZE	0x01000000
+
+#define VME_A32_SLV_SIZE	0x01000000
+
+#define VME_A32_SLV_BUS		0x90000000
+#define VME_A24_SLV_BUS		0x00000000
+#define VME_A16_SLV_BUS		0x00000000
+
+#define VME_A32_SLV_LOCAL	0x00000000
+#define VME_A24_SLV_LOCAL	0x00000000
+#define VME_A16_SLV_LOCAL	0x00000000
+
+#define A32_SLV_WINDOW
+#undef	A24_SLV_WINDOW
+#undef	A16_SLV_WINDOW
+#undef	REG_SLV_WINDOW
+
+/* PCI Registers */
+
+#define P_IMG_CTRL0		0x100
+#define P_BA0			0x104
+#define P_AM0			0x108
+#define P_TA0			0x10C
+#define P_IMG_CTRL1		0x110
+#define P_BA1			0x114
+#define P_AM1			0x118
+#define P_TA1			0x11C
+#define P_IMG_CTRL2		0x120
+#define P_BA2			0x124
+#define P_AM2			0x128
+#define P_TA2			0x12C
+#define P_IMG_CTRL3		0x130
+#define P_BA3			0x134
+#define P_AM3			0x138
+#define P_TA3			0x13C
+#define P_IMG_CTRL4		0x140
+#define P_BA4			0x144
+#define P_AM4			0x148
+#define P_TA4			0x14C
+#define P_IMG_CTRL5		0x150
+#define P_BA5			0x154
+#define P_AM5			0x158
+#define P_TA5			0x15C
+#define P_ERR_CS		0x160
+#define P_ERR_ADDR		0x164
+#define P_ERR_DATA		0x168
+
+#define WB_CONF_SPC_BAR		0x180
+#define W_IMG_CTRL1		0x184
+#define W_BA1			0x188
+#define W_AM1			0x18C
+#define W_TA1			0x190
+#define W_IMG_CTRL2		0x194
+#define W_BA2			0x198
+#define W_AM2			0x19C
+#define W_TA2			0x1A0
+#define W_IMG_CTRL3		0x1A4
+#define W_BA3			0x1A8
+#define W_AM3			0x1AC
+#define W_TA3			0x1B0
+#define W_IMG_CTRL4		0x1B4
+#define W_BA4			0x1B8
+#define W_AM4			0x1BC
+#define W_TA4			0x1C0
+#define W_IMG_CTRL5		0x1C4
+#define W_BA5			0x1C8
+#define W_AM5			0x1CC
+#define W_TA5			0x1D0
+#define W_ERR_CS		0x1D4
+#define W_ERR_ADDR		0x1D8
+#define W_ERR_DATA		0x1DC
+#define CNF_ADDR		0x1E0
+#define CNF_DATA		0x1E4
+#define INT_ACK			0x1E8
+#define ICR			0x1EC
+#define ISR			0x1F0
+
+/* VME registers */
+
+#define VME_SLAVE32_AM		0x03
+#define VME_SLAVE24_AM		0x02
+#define VME_SLAVE16_AM		0x01
+#define VME_SLAVE_REG_AM	0x00
+#define VME_SLAVE32_A		0x07
+#define VME_SLAVE24_A		0x06
+#define VME_SLAVE16_A		0x05
+#define VME_SLAVE_REG_A		0x04
+#define VME_SLAVE32_MASK	0x0B
+#define VME_SLAVE24_MASK	0x0A
+#define VME_SLAVE16_MASK	0x09
+#define VME_SLAVE_REG_MASK	0x08
+#define VME_SLAVE32_EN		0x0F
+#define VME_SLAVE24_EN		0x0E
+#define VME_SLAVE16_EN		0x0D
+#define VME_SLAVE_REG_EN	0x0C
+#define VME_MASTER32_AM		0x13
+#define VME_MASTER24_AM		0x12
+#define VME_MASTER16_AM		0x11
+#define VME_MASTER_REG_AM	0x10
+#define VME_RMW_ADRS		0x14
+#define VME_MBOX		0x18
+#define VME_STATUS		0x1E
+#define VME_CTRL		0x1C
+#define VME_IRQ			0x20
+#define VME_INT_EN		0x21
+#define VME_INT			0x22
+#define VME_IRQ1_REG		0x24
+#define VME_IRQ2_REG		0x28
+#define VME_IRQ3_REG		0x2C
+#define VME_IRQ4_REG		0x30
+#define VME_IRQ5_REG		0x34
+#define VME_IRQ6_REG		0x38
+#define VME_IRQ7_REG		0x3C
+
+/* VME control register */
+
+#define VME_CTRL_BRDRST		0x01
+#define VME_CTRL_SYSRST		0x02
+#define VME_CTRL_RMW		0x04
+#define VME_CTRL_SHORT_D	0x08
+#define VME_CTRL_SYSFAIL	0x10
+#define VME_CTRL_VOWN		0x20
+#define VME_CTRL_A16_REG_MODE	0x40
+
+/* VME status register */
+
+#define VME_STATUS_SYSCON	0x01
+#define VME_STATUS_SYSFAIL	0x02
+#define VME_STATUS_ACFAIL	0x04
+#define VME_STATUS_SYSRST	0x08
+#define VME_STATUS_VOWN		0x10
+
+/* Interrupt types */
+
+#define LVL1			0x0002
+#define LVL2			0x0004
+#define LVL3			0x0008
+#define LVL4			0x0010
+#define LVL5			0x0020
+#define LVL6			0x0040
+#define LVL7			0x0080
+#define MULTIVERSE_INTI_INT	0x0100
+#define MULTIVERSE_WB_INT	0x0200
+#define MULTIVERSE_PCI_INT	0x0400
+
+/* interrupt acknowledge */
+
+#define VME_IACK1		0x04
+#define VME_IACK2		0x08
+#define VME_IACK3		0x0c
+#define VME_IACK4		0x10
+#define VME_IACK5		0x14
+#define VME_IACK6		0x18
+#define VME_IACK7		0x1c
+
+#endif /* __MULTIVERSE_H__ */
diff --git a/u-boot/board/etx094/Makefile b/u-boot/board/etx094/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/etx094/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/etx094/etx094.c b/u-boot/board/etx094/etx094.c
new file mode 100644
index 0000000..d6f638a
--- /dev/null
+++ b/u-boot/board/etx094/etx094.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static void read_hw_vers (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+
+	/* single read   (offset 0x00 in upm ram) */
+
+	0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04,
+	0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_,
+
+	/* burst read    (offset 0x08 in upm ram) */
+
+	0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04,
+	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00,
+	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write  (offset 0x18 in upm ram) */
+
+	0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00,
+	0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+
+	0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00,
+	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05,
+
+	/* init part1      (offset 0x28 in upm ram) */
+
+	0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34,
+	0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* refresh   (offset 0x30 in upm ram) */
+
+	0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05,
+
+	/* init part2     (offset 0x34 in upm ram) */
+
+	0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34,
+	0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_,
+
+	/* exception     (offset 0x3C in upm ram) */
+
+	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ETX ID string (ETX_xxx...)
+ *
+ * Return 1 always.
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+	char *e;
+
+	puts ("Board: ");
+
+#ifdef SB_ETX094
+	gd->board_type = 0; /* 0 = 2SDRAM-Device */
+#else
+	gd->board_type = 1; /* 1 = 1SDRAM-Device */
+#endif
+
+	if (!s || strncmp (s, "ETX_", 4)) {
+		puts ("### No HW ID - assuming ETX_094\n");
+		read_hw_vers ();
+		return (0);
+	}
+
+	for (e = s; *e; ++e) {
+		if (*e == ' ')
+			break;
+	}
+
+	for (; s < e; ++s) {
+		putc (*s);
+	}
+	putc ('\n');
+
+	read_hw_vers ();
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;	/* MPTPR_PTP_DIV32 0x0200 */
+
+	/* A3(SDRAM)=0      => Bursttype = Sequential
+	 * A2-A0(SDRAM)=010 => Burst length = 4
+	 * A4-A6(SDRAM)=010 => CasLat=2
+	 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+	if (board_type == 0) {	/* "L" type boards have only one bank SDRAM */
+		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+	}
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004128;	/* SDRAM bank 0 (CS2) - Init Part 1 */
+	memctl->memc_mcr = 0x80004734;	/* SDRAM bank 0 (CS2) - Init Part 2 */
+	udelay (1);
+
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		memctl->memc_mcr = 0x80006128;	/* SDRAM bank 1 (CS3) - Init Part 1 */
+		memctl->memc_mcr = 0x80006734;	/* SDRAM bank 1 (CS3) - Init Part 2 */
+		udelay (1);
+	}
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {					/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		/*
+		 * Check Bank 1 Memory Size
+		 * use current column settings
+		 * [9 column SDRAM may also be used in 8 column mode,
+		 *  but then only half the real size will be used.]
+		 */
+		size_b1 =
+				dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
+						   SDRAM_MAX_SIZE);
+/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
+	} else {
+		size_b1 = 0;
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/*DIV16 */
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br3 =
+			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or2 =
+				((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br2 =
+				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+				+ size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {			/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or3 =
+					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br3 =
+					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					+ size_b0;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br3 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* HW-ID Table (Bits: 2^9;2^7;2^5) */
+#define HW_ID_0 0x0000
+#define HW_ID_1 0x0020
+#define HW_ID_2 0x0080
+#define HW_ID_3 0x00a0
+#define HW_ID_4 0x0200
+#define HW_ID_5 0x0220
+#define HW_ID_6 0x0280
+#define HW_ID_7 0x02a0
+
+void read_hw_vers ()
+{
+	unsigned short rd_msk = 0x02A0;
+
+	/* HW-ID pin-definition */
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	immr->im_ioport.iop_pddir &= ~(rd_msk);
+	immr->im_ioport.iop_pdpar &= ~(rd_msk);
+
+	/* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */
+
+	/* Check the HW-ID */
+	printf ("HW-Version: ");
+	switch (immr->im_ioport.iop_pddat & rd_msk) {
+	case HW_ID_0:
+		printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n");
+		break;
+	case HW_ID_1:
+		printf ("V0.9 / W50037-Q1-D6-1\n");
+		break;
+	case HW_ID_2:
+		printf ("NOT USED - assuming ID#2\n");
+		break;
+	case HW_ID_3:
+		printf ("NOT USED - assuming ID#3\n");
+		break;
+	case HW_ID_4:
+		printf ("NOT USED - assuming ID#4\n");
+		break;
+	case HW_ID_5:
+		printf ("NOT USED - assuming ID#5\n");
+		break;
+	case HW_ID_6:
+		printf ("NOT USED - assuming ID#6\n");
+		break;
+	case HW_ID_7:
+		printf ("NOT USED - assuming ID#7\n");
+		break;
+	default:
+		printf ("###Error###\n");
+		break;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/etx094/flash.c b/u-boot/board/etx094/flash.c
new file mode 100644
index 0000000..fa51c90
--- /dev/null
+++ b/u-boot/board/etx094/flash.c
@@ -0,0 +1,744 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+#ifdef CONFIG_FLASH_16BIT
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
+#else
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+#endif
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+#ifdef CONFIG_FLASH_16BIT
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V | BR_PS_16;
+#else
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+#endif
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00002000);
+		}
+		return;
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+#ifdef CONFIG_FLASH_16BIT
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+#else
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+#endif
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_SST200A:	printf ("39xF200A (2M = 128K x 16)\n");
+				break;
+	case FLASH_SST400A:	printf ("39xF400A (4M = 256K x 16)\n");
+				break;
+	case FLASH_SST800A:	printf ("39xF800A (8M = 512K x 16)\n");
+				break;
+	case FLASH_STM800AB:	printf ("M29W800AB (8M = 512K x 16)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+#ifdef CONFIG_FLASH_16BIT
+	vu_short *s_addr = (vu_short*)addr;
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x0090;
+	value = s_addr[0];
+	value = value|(value<<16);
+#else
+	addr[0x5555] = 0x00AA00AA;
+	addr[0x2AAA] = 0x00550055;
+	addr[0x5555] = 0x00900090;
+	value = addr[0];
+#endif
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+#ifdef CONFIG_FLASH_16BIT
+	value = s_addr[1];
+	value = value|(value<<16);
+#else
+	value = addr[1];			/* device ID		*/
+#endif
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+#ifdef CONFIG_FLASH_16BIT
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB */
+#else
+		info->sector_count = 19;
+		info->size = 0x00200000;	/* => 2 MB	*/
+#endif
+		break;
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+#ifdef CONFIG_FLASH_16BIT
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB	*/
+#else
+		info->sector_count = 35;
+		info->size = 0x00400000;	/* => 4 MB	*/
+#endif
+
+		break;
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	case SST_ID_xF200A:
+		info->flash_id += FLASH_SST200A;
+		info->sector_count = 64;	/* 39xF200A ID ( 2M = 128K x 16	) */
+		info->size = 0x00080000;
+		break;
+	case SST_ID_xF400A:
+		info->flash_id += FLASH_SST400A;
+		info->sector_count = 128;	/* 39xF400A ID ( 4M = 256K x 16	) */
+		info->size = 0x00100000;
+		break;
+	case SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 256;	/* 39xF800A ID ( 8M = 512K x 16	) */
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case STM_ID_x800AB:
+		info->flash_id += FLASH_STM800AB;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00002000);
+		}
+	} else {	/* AMD and Fujitsu types */
+		/* set up sector start address table */
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+#ifdef CONFIG_FLASH_16BIT
+
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+#else
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00020000) - 0x00060000;
+#endif
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+
+		/* check for protected sectors */
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address:
+			 * (A7 .. A0) = 0x02
+			 * D0 = 1 if protected
+			 */
+#ifdef CONFIG_FLASH_16BIT
+			s_addr = (volatile unsigned short *)(info->start[i]);
+			info->protect[i] = s_addr[2] & 1;
+#else
+			addr = (volatile unsigned long *)(info->start[i]);
+			info->protect[i] = addr[2] & 1;
+#endif
+		}
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#ifdef CONFIG_FLASH_16BIT
+		s_addr = (volatile unsigned short *)(info->start[0]);
+		*s_addr = 0x00F0;	/* reset bank */
+#else
+		addr = (volatile unsigned long *)info->start[0];
+		*addr = 0x00F000F0;	/* reset bank */
+#endif
+
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect;
+	ulong start, now, last;
+#ifdef CONFIG_FLASH_16BIT
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+/*#ifndef CONFIG_FLASH_16BIT
+	ulong type;
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return;
+	}
+#endif*/
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+#ifdef CONFIG_FLASH_16BIT
+			vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
+#else
+			vu_long	*sect_addr = (vu_long*)(info->start[sect]);
+#endif
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+#ifdef CONFIG_FLASH_16BIT
+
+			/*printf("\ns_sect_addr=%x",s_sect_addr);*/
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_addr[0x5555] = 0x0080;
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_sect_addr[0] = 0x0030;
+#else
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			addr[0x5555] = 0x00800080;
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			sect_addr[0] = 0x00300030;
+#endif
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+#ifdef CONFIG_FLASH_16BIT
+			while ((s_sect_addr[0] & 0x0080) != 0x0080) {
+#else
+			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
+#endif
+				if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+		}
+	}
+
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#ifdef CONFIG_FLASH_16BIT
+	s_addr[0] = 0x00F0;	/* reset bank */
+#else
+	addr[0] = 0x00F000F0;	/* reset bank */
+#endif
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+
+#ifdef CONFIG_FLASH_16BIT
+	vu_short high_data;
+	vu_short low_data;
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+#ifdef CONFIG_FLASH_16BIT
+	/* Write the 16 higher-bits */
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	high_data = ((data>>16) & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+
+	*((vu_short *)dest) = high_data;
+
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+
+	/* Write the 16 lower-bits */
+#endif
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#ifdef CONFIG_FLASH_16BIT
+	dest += 0x2;
+	low_data = (data & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+	*((vu_short *)dest) = low_data;
+
+#else
+	addr[0x5555] = 0x00AA00AA;
+	addr[0x2AAA] = 0x00550055;
+	addr[0x5555] = 0x00A000A0;
+	*((vu_long *)dest) = data;
+#endif
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+#ifdef CONFIG_FLASH_16BIT
+	while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
+#else
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+#endif
+
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/etx094/u-boot.lds b/u-boot/board/etx094/u-boot.lds
new file mode 100644
index 0000000..614880b
--- /dev/null
+++ b/u-boot/board/etx094/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    net/libnet.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    *(.text.*printf*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/etx094/u-boot.lds.debug b/u-boot/board/etx094/u-boot.lds.debug
new file mode 100644
index 0000000..be05d8f
--- /dev/null
+++ b/u-boot/board/etx094/u-boot.lds.debug
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text)
+    arch/powerpc/cpu/mpc8xx/interrupts.o	(.text)
+    arch/powerpc/cpu/mpc8xx/cpu.o	(.text)
+    arch/powerpc/cpu/mpc8xx/cpu_init.o	(.text)
+    arch/powerpc/cpu/mpc8xx/speed.o	(.text)
+    arch/powerpc/cpu/mpc8xx/serial.o	(.text)
+    arch/powerpc/lib/extable.o	(.text)
+    arch/powerpc/lib/ppcstring.o	(.text)
+    lib/string.o	(.text)
+    lib/crc32.o		(.text)
+    common/dlmalloc.o	(.text)
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/eukrea/cpu9260/Makefile b/u-boot/board/eukrea/cpu9260/Makefile
new file mode 100644
index 0000000..4d02aae
--- /dev/null
+++ b/u-boot/board/eukrea/cpu9260/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# (C) Copyright 2009
+# Eric Benard <eric@eukrea.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += led.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eukrea/cpu9260/config.mk b/u-boot/board/eukrea/cpu9260/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/u-boot/board/eukrea/cpu9260/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/u-boot/board/eukrea/cpu9260/cpu9260.c b/u-boot/board/eukrea/cpu9260/cpu9260.c
new file mode 100644
index 0000000..61b6c33
--- /dev/null
+++ b/u-boot/board/eukrea/cpu9260/cpu9260.c
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void cpu9260_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+#if defined(CONFIG_CPU9G20)
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 |
+		       AT91_SMC_TDF_(3));
+#elif defined(CONFIG_CPU9260)
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 |
+		       AT91_SMC_TDF_(2));
+#endif
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void cpu9260_macb_hw_init(void)
+{
+	unsigned long rstc;
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+		       (AT91_RSTC_ERSTL & (0x0D << 8)) |
+		       AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
+		;
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+		       (rstc) |
+		       AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of the board */
+#if defined(CONFIG_CPU9G20)
+	gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
+#elif defined(CONFIG_CPU9260)
+	gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	cpu9260_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	cpu9260_macb_hw_init();
+#endif
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) !=
+	    PHYS_SDRAM_SIZE)
+		return -1;
+
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/eukrea/cpu9260/led.c b/u-boot/board/eukrea/cpu9260/led.c
new file mode 100644
index 0000000..e73543b
--- /dev/null
+++ b/u-boot/board/eukrea/cpu9260/led.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
+		STATUS_LED_OFF, STATUS_LED_OFF};
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+	at91_set_gpio_output(CONFIG_BLUE_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 1);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+}
+
+void red_LED_off(void)
+{
+	at91_set_gpio_value(CONFIG_RED_LED, 1);
+	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void green_LED_off(void)
+{
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
+}
+
+void yellow_LED_off(void)
+{
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
+}
+
+void blue_LED_off(void)
+{
+	at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
+}
+
+void red_LED_on(void)
+{
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void green_LED_on(void)
+{
+	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+	saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
+}
+
+void yellow_LED_on(void)
+{
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+	saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
+}
+
+void blue_LED_on(void)
+{
+	at91_set_gpio_value(CONFIG_BLUE_LED, 0);
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
+			blue_LED_off();
+		else
+			blue_LED_on();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_LED_off();
+		else
+			red_LED_on();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+			green_LED_off();
+		else
+			green_LED_on();
+	} else if (STATUS_LED_YELLOW == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
+			yellow_LED_off();
+		else
+			yellow_LED_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == state)
+			blue_LED_on();
+		else
+			blue_LED_off();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_LED_on();
+		else
+			red_LED_off();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == state)
+			green_LED_on();
+		else
+			green_LED_off();
+	} else if (STATUS_LED_YELLOW == mask) {
+		if (STATUS_LED_ON == state)
+			yellow_LED_on();
+		else
+			yellow_LED_off();
+	}
+}
diff --git a/u-boot/board/eukrea/cpuat91/Makefile b/u-boot/board/eukrea/cpuat91/Makefile
new file mode 100644
index 0000000..15da3d8
--- /dev/null
+++ b/u-boot/board/eukrea/cpuat91/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de. <http://lists.denx.de/mailman/listinfo/u-boot>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cpuat91.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/eukrea/cpuat91/config.mk b/u-boot/board/eukrea/cpuat91/config.mk
new file mode 100644
index 0000000..463f46b
--- /dev/null
+++ b/u-boot/board/eukrea/cpuat91/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21F00000
diff --git a/u-boot/board/eukrea/cpuat91/cpuat91.c b/u-boot/board/eukrea/cpuat91/cpuat91.c
new file mode 100644
index 0000000..cd4d42c
--- /dev/null
+++ b/u-boot/board/eukrea/cpuat91/cpuat91.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com>
+ * Eric Benard <eric@eukrea.com>
+ * based on at91rm9200dk.c which is :
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+	/* arch number of CPUAT91-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+void i2c_init_board(void)
+{
+	u32 pin;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	writel(1 << AT91_ID_PIOA, &pmc->pcer);
+	pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+	writel(pin, &pio->pioa.idr);
+	writel(pin, &pio->pioa.pudr);
+	writel(pin, &pio->pioa.per);
+	writel(pin, &pio->pioa.oer);
+	writel(pin, &pio->pioa.sodr);
+}
+#endif
diff --git a/u-boot/board/evb4510/Makefile b/u-boot/board/evb4510/Makefile
new file mode 100644
index 0000000..102eade
--- /dev/null
+++ b/u-boot/board/evb4510/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= evb4510.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/evb4510/config.mk b/u-boot/board/evb4510/config.mk
new file mode 100644
index 0000000..140c989
--- /dev/null
+++ b/u-boot/board/evb4510/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+# Curt Brune <curt@cucy.com>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x007d0000
diff --git a/u-boot/board/evb4510/evb4510.c b/u-boot/board/evb4510/evb4510.c
new file mode 100644
index 0000000..13abbb7
--- /dev/null
+++ b/u-boot/board/evb4510/evb4510.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EVB4510
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	icache_enable();
+
+	/* address for the kernel command line */
+	gd->bd->bi_boot_params = 0x800;
+
+	/* enable board LEDs for output */
+	PUT_REG( REG_IOPDATA, 0x0);
+	PUT_REG( REG_IOPMODE, 0xFFFF);
+	PUT_REG( REG_IOPDATA, 0xFF);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+#if CONFIG_NR_DRAM_BANKS == 2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/evb4510/flash.c b/u-boot/board/evb4510/flash.c
new file mode 100644
index 0000000..c9c6e02
--- /dev/null
+++ b/u-boot/board/evb4510/flash.c
@@ -0,0 +1,539 @@
+/*
+ *
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <flash.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+typedef enum {
+	FLASH_DEV_U9_512KB = 0,
+	FLASH_DEV_U7_2MB = 1
+} FLASH_DEV;
+
+#define FLASH_DQ7		(0x80)
+#define FLASH_DQ5		(0x20)
+
+#define PROG_ADDR		(0xAAA)
+#define SETUP_ADDR		(0xAAA)
+#define ID_ADDR			(0xAAA)
+#define UNLOCK_ADDR1		(0xAAA)
+#define UNLOCK_ADDR2		(0x555)
+
+#define UNLOCK_CMD1		(0xAA)
+#define UNLOCK_CMD2		(0x55)
+#define ERASE_SUSPEND_CMD	(0xB0)
+#define ERASE_RESUME_CMD	(0x30)
+#define RESET_CMD		(0xF0)
+#define ID_CMD			(0x90)
+#define SELECT_CMD		(0x90)
+#define CHIPERASE_CMD		(0x10)
+#define BYPASS_CMD		(0x20)
+#define SECERASE_CMD		(0x30)
+#define PROG_CMD		(0xa0)
+#define SETUP_CMD		(0x80)
+
+#if 0
+#define WRITE_UNLOCK(addr) { \
+	PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \
+	PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \
+}
+
+/* auto select command */
+#define CMD_ID(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, ID_CMD); \
+}
+
+#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, RESET_CMD); \
+}
+
+#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( addr, SECERASE_CMD);
+
+#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD);
+
+/* prepare for bypass programming */
+#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, 0x20); \
+}
+
+/* terminate bypass programming */
+#define CMD_BYPASS_RESET(addr) { \
+	PUT__U8(addr, 0x90); \
+	PUT__U8(addr, 0x00); \
+}
+#endif
+
+inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		PUT__U8 (base + 0xAAA, 0xAA);
+		PUT__U8 (base + 0x555, 0x55);
+		break;
+	case FLASH_DEV_U9_512KB:
+		PUT__U8 (base + 0x555, 0xAA);
+		PUT__U8 (base + 0x2AA, 0x55);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SELECT_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SELECT_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, RESET_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, RESET_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, BYPASS_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, BYPASS_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base)
+{
+	PUT__U8 (base, SELECT_CMD);
+	PUT__U8 (base, 0x0);
+}
+
+/* poll for flash command completion */
+static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut)
+{
+	u32 done = 0;
+	ulong t0;
+
+	u16 error = 0;
+	volatile u16 flashData;
+
+	data = data & 0xFF;
+	t0 = get_timer (0);
+	while (get_timer (t0) < timeOut) {
+		/*	for( i = 0; i < POLL_LOOPS; i++) { */
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+
+		/*  FLASH_DQ7 = Data? */
+		if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) {
+			done = 1;
+			break;
+		}
+
+		/*  Check Timeout (FLASH_DQ5==1) */
+		if (flashData & FLASH_DQ5) {
+			/*  Read the Data */
+			flashData = GET__U8 (addr);
+
+			/*  FLASH_DQ7 = Data? */
+			if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) {
+				printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n");
+				error = ERR_PROG_ERROR;
+			}
+			FLASH_CMD_RESET (dev, addr);
+			done = 1;
+			break;
+		}
+		/*  spin delay */
+		udelay (10);
+	}
+
+
+	/*  error update */
+	if (!done) {
+		printf ("_flash_poll(): Timeout\n");
+		error = ERR_TIMOUT;
+	}
+
+	/*  Check the data */
+	if (!error) {
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+		if (flashData != data) {
+			error = ERR_PROG_ERROR;
+			printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n",
+				flashData, data);
+		}
+	}
+
+	return error;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int _flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+	int sect, prot = 0;
+
+	for (sect = s_first; sect <= s_last; sect++)
+		if (info->protect[sect]) {
+			printf ("  Flash sector %d protected.\n", sect);
+			prot++;
+		}
+	return prot;
+}
+
+static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId)
+{
+
+	u32 baseAddr = base | CACHE_DISABLE_MASK;
+	u8 vendorId, deviceId;
+
+	/*	printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */
+
+	/* Send auto select command and read manufacturer info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+	vendorId = GET__U8 (baseAddr);
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* Send auto select command and read device info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+
+	if (dev == FLASH_DEV_U7_2MB) {
+		deviceId = GET__U8 (baseAddr + 2);
+	} else if (dev == FLASH_DEV_U9_512KB) {
+		deviceId = GET__U8 (baseAddr + 1);
+	} else {
+		return 0;
+	}
+
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n",
+		vendorId, deviceId);
+	 */
+
+	return (vendorId == venId) && (deviceId == devId);
+
+}
+
+/******************************************************************************
+ *
+ * Public u-boot interface functions below
+ *
+ *****************************************************************************/
+
+/***************************************************************************
+ *
+ * Flash initialization
+ *
+ * This board has two banks of flash, but the base addresses depend on
+ * how the board is jumpered.
+ *
+ * The two flash types are:
+ *
+ *   AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB
+ *
+ *   AMD Am29LV040B  (512KB)  sectors: 8x64KB
+ *****************************************************************************/
+
+unsigned long flash_init (void)
+{
+	flash_info_t *info;
+	u16 i;
+	u32 flashtest;
+	s16 amd160 = -1;
+	u32 amd160base = 0;
+
+#if CONFIG_SYS_MAX_FLASH_BANKS == 2
+	s16 amd040 = -1;
+	u32 amd040base = 0;
+#endif
+
+	/* configure PHYS_FLASH_1 */
+	if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) {
+		amd160 = 0;
+		amd160base = PHYS_FLASH_1;
+#if CONFIG_SYS_MAX_FLASH_BANKS == 1
+	}
+#else
+		if (_detectFlash
+		    (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) {
+			amd040 = 1;
+			amd040base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	} else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) {
+		amd040 = 0;
+		amd040base = PHYS_FLASH_1;
+		if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) {
+			amd160 = 1;
+			amd160base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	}
+#endif
+	else {
+		printf ("flash_init(): Unable to detect PHYS_FLASH_1: 0x%08x\n",
+			PHYS_FLASH_1);
+	}
+
+	/* Configure AMD Am29LV160DB (2MB) */
+	info = &flash_info[amd160];
+	info->flash_id = FLASH_DEV_U7_2MB;
+	info->sector_count = 35;
+	info->size = 2 * 1024 * 1024;	/* 2MB */
+	/* 1*16K Boot Block
+	   2*8K Parameter Block
+	   1*32K Small Main Block */
+	info->start[0] = amd160base;
+	info->start[1] = amd160base + 0x4000;
+	info->start[2] = amd160base + 0x6000;
+	info->start[3] = amd160base + 0x8000;
+	for (i = 1; i < info->sector_count; i++)
+		info->start[3 + i] = amd160base + i * (64 * 1024);
+
+	for (i = 0; i < info->sector_count; i++) {
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd160base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+
+	/*
+	 * protect monitor and environment sectors in 2MB flash
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       amd160base, amd160base + monitor_flash_len - 1, info);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, info);
+
+#if CONFIG_SYS_MAX_FLASH_BANKS == 2
+	/* Configure AMD Am29LV040B (512KB) */
+	info = &flash_info[amd040];
+	info->flash_id = FLASH_DEV_U9_512KB;
+	info->sector_count = 8;
+	info->size = 512 * 1024;	/* 512KB, 8 x 64KB */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = amd040base + i * (64 * 1024);
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd040base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+#endif
+
+	return flash_info[0].size
+#if CONFIG_SYS_MAX_FLASH_BANKS == 2
+		+ flash_info[1].size
+#endif
+		;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_DEV_U7_2MB) {
+		printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n");
+	} else if (info->flash_id == FLASH_DEV_U9_512KB) {
+		printf ("AMD Am29LV040B	 (512KB) 8x64KB\n");
+	} else {
+		printf ("Unknown flash_id ...\n");
+		return;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" S%02d @ 0x%08lX%s", i,
+			info->start[i], info->protect[i] ? " !" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	u16 i, error = 0;
+
+	printf ("\n");
+
+	/* check flash protection bits */
+	if (_flash_check_protection (info, s_first, s_last)) {
+		printf ("  Flash erase aborted due to protected sectors\n");
+		return ERR_PROTECTED;
+	}
+
+	if ((s_first < info->sector_count) && (s_first <= s_last)) {
+		for (i = s_first; i <= s_last && !error; i++) {
+			printf ("  Erasing Sector %d @ 0x%08lx ... ", i,
+				info->start[i]);
+			/* bypass the cache to access the flash memory */
+			FLASH_CMD_ERASE_SEC (info->flash_id,
+					     (info->
+					      start[0] | CACHE_DISABLE_MASK),
+					     (info->
+					      start[i] | CACHE_DISABLE_MASK));
+			/* look for sector to become 0xFF after erase */
+			error = _flash_poll (info->flash_id,
+					     info->
+					     start[i] | CACHE_DISABLE_MASK,
+					     0xFF, CONFIG_SYS_FLASH_ERASE_TOUT);
+			FLASH_CMD_RESET (info->flash_id,
+					 (info->
+					  start[0] | CACHE_DISABLE_MASK));
+			printf ("done\n");
+			if (error) {
+				break;
+			}
+		}
+	} else
+		error = ERR_INVAL;
+
+	return error;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	u16 error = 0, i;
+	u32 n;
+	u8 *bp, *bps;
+
+	/*  Write Setup */
+	/* bypass the cache to access the flash memory */
+	FLASH_CMD_UNLOCK_BYPASS (info->flash_id,
+				 (info->start[0] | CACHE_DISABLE_MASK));
+
+	/*  Write the Data to Flash */
+
+	bp = (u8 *) (addr | CACHE_DISABLE_MASK);
+	bps = (u8 *) src;
+
+	for (n = 0; n < cnt && !error; n++, bp++, bps++) {
+
+		if (!(n % (cnt / 15))) {
+			printf (".");
+		}
+
+		/*  write the flash command for flash memory */
+		*bp = 0xA0;
+
+		/*  Write the data */
+		*bp = *bps;
+
+		/*  Check if the write is done */
+		for (i = 0; i < 0xff; i++);
+		error = _flash_poll (info->flash_id, (u32) bp, *bps,
+				     CONFIG_SYS_FLASH_WRITE_TOUT);
+		if (error) {
+			return error;
+		}
+	}
+
+	/*  Reset the Flash Mode to read */
+	FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]);
+
+	printf (" ");
+
+	return error;
+}
diff --git a/u-boot/board/evb4510/lowlevel_init.S b/u-boot/board/evb4510/lowlevel_init.S
new file mode 100644
index 0000000..7184d72
--- /dev/null
+++ b/u-boot/board/evb4510/lowlevel_init.S
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM.  After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000.	After lowlevel_init completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ *     to	8MB SRAM (U5) -- 8MB Map
+ * 0x00800000
+ *
+ * 0x01000000
+ *     to	2MB Flash @ 0x00000000 (U7) -- 2MB Map
+ * 0x01200000
+ *
+ * 0x02000000
+ *     to	512KB Flash @ 0x02000000 (U9) -- 2MB Map
+ * 0x02080000
+ *
+ * Load all 12 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written.	The
+ * last register written re-enables memory access.  For more info see
+ * the user's manual for the S3C4510B, available from Samsung's web
+ * site.  Search for part number "S3C4510B".
+ *
+ ***********************************************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* preserve the temp register (r12 AKA ip) and remap it. */
+	ldr r1, =SRAM_BASE+0xC
+	add r0, r12, #0x01000000
+	str r0, [r1]
+
+	/* remap the link register for when we return */
+	add lr, lr, #0x01000000
+
+	/* store a short program in the on chip SRAM, which is
+	 * unaffected when remapping memory.  Note the cache must be
+	 * disabled for the on chip SRAM to be available.
+	 */
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe8801ffe  /* stmia r0, {r1-r12} */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe59fc000  /* ldr r12, [pc, #0]  */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe1a0f00e  /* mov pc, lr	   */
+	str r0, [r1]
+
+	adr   r0, memory_map_data
+	ldmia r0, {r1-r12}
+	ldr   r0, =REG_EXTDBWTH
+
+	ldr pc, =SRAM_BASE
+
+.globl reset_cpu
+reset_cpu:
+	/*
+	 * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
+	 * address 0x0.	 We accomplish this by storing a few
+	 * instructions into the on chip SRAM (8KB) and run from
+	 * there.  Note the cache must be disabled for the on chip
+	 * SRAM to be available.
+	 *
+	 * load r2 with REG_ROMCON0
+	 * load r3 with 0x12040060	   configure FLASH bank 0 @ 0x00000000
+	 * load r4 with REG_DRAMCON0
+	 * load r5 with 0x08000380	   configure   RAM bank 0 @ 0x01000000
+	 * load r6 with REG_REFEXTCON
+	 * load r7 with 0x9c218360
+	 * load r8 with 0x0
+	 * store str r3,[r2] @ SRAM_BASE
+	 * store str r5,[r4] @ SRAM_BASE + 0x4
+	 * store str r7,[r6] @ SRAM_BASE + 0x8
+	 * store mov pc,r8   @ SRAM_BASE + 0xC
+	 * mov pc, SRAM_BASE
+	 *
+	 */
+
+	/* disable cache */
+	ldr r0, =REG_SYSCFG
+	ldr r1, =0x83ffffa0	/* cache-disabled  */
+	str r1, [r0]
+
+	ldr r2, =REG_ROMCON0
+	ldr r3, =0x02000060	/* Bank0 2MB FLASH   @ 0x00000000 */
+	ldr r4, =REG_DRAMCON0
+	ldr r5, =0x18040380	/* DRAM0 8MB SRAM    @ 0x01000000 */
+	ldr r6, =REG_REFEXTCON
+	ldr r7, =0xce278360
+	ldr r8, =0x00000000
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe5823000	/* str	r3, [r2] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+4
+	ldr r0, =0xe5845000	/* str	r5, [r4] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+8
+	ldr r0, =0xe5867000	/* str	r7, [r6] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+0xC
+	ldr r0, =0xe1a0f008	/* mov	pc, r8	 */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE
+	mov pc, r1
+
+	/* never return */
+
+/************************************************************************
+ * Below are twelve 32-bit values for the twelve memory registers of
+ * the system manager, starting with register REG_EXTDBWTH.
+ ***********************************************************************/
+memory_map_data:
+	.long 0x00f03005     /* memory widths */
+	.long 0x12040060     /* Bank0 2MB FLASH	  @ 0x01000000 */
+	.long 0x22080060     /* Bank1 512KB FLASH @ 0x02000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x08000380     /* DRAM0 8MB SRAM	  @ 0x00000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x9c218360     /* enable memory */
diff --git a/u-boot/board/evb64260/64260.h b/u-boot/board/evb64260/64260.h
new file mode 100644
index 0000000..d106ced
--- /dev/null
+++ b/u-boot/board/evb64260/64260.h
@@ -0,0 +1,31 @@
+#ifndef __64260_H__
+#define __64260_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_AACK_DELAY	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_TA_DELAY	(1 << 15)
+#define CPU_CONF_RD_OOO		(1 << 16)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_FAST_CLK	(1 << 23)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+#define CPU_CONF_CONF_SB_DIS	(1 << 28)
+#define CPU_CONF_IO_SB_DIS	(1 << 29)
+#define CPU_CONF_CLK_SYNC	(1 << 30)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64260_H__ */
diff --git a/u-boot/board/evb64260/Makefile b/u-boot/board/evb64260/Makefile
new file mode 100644
index 0000000..d72465e
--- /dev/null
+++ b/u-boot/board/evb64260/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	= misc.o
+COBJS	= $(BOARD).o flash.o serial.o memory.o pci.o \
+	  eth.o eth_addrtbl.o mpsc.o i2c.o \
+	  sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/evb64260/bootseq.txt b/u-boot/board/evb64260/bootseq.txt
new file mode 100644
index 0000000..e4fefb3
--- /dev/null
+++ b/u-boot/board/evb64260/bootseq.txt
@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+    b boot_cold
+
+start_warm:
+    b boot_warm
+
+
+boot_cold:
+boot_warm:
+    clear bats
+    init l2 (if enabled)
+    init altivec (if enabled)
+    invalidate l2 (if enabled)
+    setup bats (from defines in config_EVB)
+    enable_addr_trans: (if MMU enabled)
+	enable MSR_IR and MSR_DR
+    jump to in_flash
+
+in_flash:
+    enable l1 dcache
+    gal_low_init: (board/evb64260/sdram_init.S)
+	config SDRAM (CFG, TIMING, DECODE)
+	init scratch regs (810 + 814)
+
+	detect DIMM0 (bank 0 only)
+	config SDRAM_PARA0 to 256/512Mbit
+	bl sdram_op_mode
+	detect bank0 width
+	    write scratch reg 810
+	config SDRAM_PARA0 with results
+	config SDRAM_PARA1 with results
+
+	detect DIMM1 (bank 2 only)
+	config SDRAM_PARA2 to 256/512Mbit
+	detect bank2 width
+	    write scratch reg 814
+	config SDRAM_PARA2 with results
+	config SDRAM_PARA3 with results
+
+	setup device bus timings/width
+	setup boot device timings/width
+
+	setup CPU_CONF (0x0)
+	setup cpu master control register 0x160
+	setup PCI0 TIMEOUT
+	setup PCI1 TIMEOUT
+	setup PCI0 BAR
+	setup PCI1 BAR
+
+	setup MPP control 0-3
+	setup GPP level control
+	setup Serial ports multiplex
+
+    setup stack pointer (r1)
+    setup GOT
+    call cpu_init_f
+	debug leds
+    board_init_f: (common/board.c)
+	board_early_init_f:
+	    remap gt regs?
+	    map PCI mem/io
+	    map device space
+	    clear out interupts
+	init_timebase
+	env_init
+	serial_init
+	console_init_f
+	display_options
+	initdram: (board/evb64260/evb64260.c)
+	    detect memory
+	    for each bank:
+		dram_size()
+		setup PCI slave memory mappings
+		setup SCS
+	setup monitor
+	alloc board info struct
+	init bd struct
+	relocate_code: (cpu/mpc7xxx/start.S)
+	    copy,got,clearbss
+	    board_init_r(bd, dest_addr) (common/board.c)
+		setup bd function pointers
+		trap_init
+		flash_init: (board/evb64260/flash.c)
+		setup bd flash info
+		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+		    nothing
+		mem_malloc_init
+		malloc_bin_reloc
+		spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
+		env_relocated
+		misc_init_r(bd): (board/evb64260/evb64260.c)
+		    mpsc_init2
diff --git a/u-boot/board/evb64260/ecctest.c b/u-boot/board/evb64260/ecctest.c
new file mode 100644
index 0000000..5d3679a
--- /dev/null
+++ b/u-boot/board/evb64260/ecctest.c
@@ -0,0 +1,111 @@
+indent: Standard input:27: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+#ifdef ECC_TEST
+static inline void ecc_off (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
+}
+
+static inline void ecc_on (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
+}
+
+static int putshex (const char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
+	}
+	return 0;
+}
+
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/evb64260/eth.c b/u-boot/board/evb64260/eth.c
new file mode 100644
index 0000000..352505a
--- /dev/null
+++ b/u-boot/board/evb64260/eth.c
@@ -0,0 +1,808 @@
+/**************************************************************************
+Etherboot -  BOOTP/TFTP Bootstrap Program
+Skeleton NIC driver for Etherboot
+***************************************************************************/
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+/*
+ * This file is a modified version from the Galileo polled mode
+ * network driver for the ethernet contained within the GT64260
+ * chip. It has been modified to fit into the U-Boot framework, from
+ * the original (etherboot) setup.  Also, additional cleanup and features
+ * were added.
+ *
+ * - Josh Huber <huber@mclx.com>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+#include <asm/cache.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+
+#include "eth.h"
+#include "eth_addrtbl.h"
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+
+#define GT6426x_ETH_BUF_SIZE	1536
+
+/* if you like verbose output, turn this on! */
+#undef DEBUG
+
+/* Restart autoneg if we detect link is up on phy init. */
+
+/*
+ * The GT doc's say that after Rst is deasserted, and the PHY
+ * reports autoneg complete, it runs through its autoneg
+ * procedures. This doesn't seem to be the case for MII
+ * PHY's. To work around this check for link up && autoneg
+ * complete when initilizing the port. If they are both set,
+ * then restart PHY autoneg. Of course, it may be something
+ * completly different.
+ */
+#ifdef CONFIG_ETHER_PORT_MII
+# define RESTART_AUTONEG
+#endif
+
+/* do this if you dont want to use snooping */
+#define USE_SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+/* bummer - w/o flush, nothing works, even with snooping - FIXME */
+/* #define FLUSH_DCACHE(a,b) */
+#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+struct eth_dev_s {
+	eth0_tx_desc_single *eth_tx_desc;
+	eth0_rx_desc_single *eth_rx_desc;
+	char *eth_tx_buffer;
+	char *eth_rx_buffer[NR];
+	int tdn, rdn;
+	int dev;
+	unsigned int reg_base;
+};
+
+
+#ifdef CONFIG_INTEL_LXT97X
+/* for intel LXT972 */
+static const char ether_port_phy_addr[3]={0,1,2};
+#else
+static const char ether_port_phy_addr[3]={4,5,6};
+#endif
+
+/* MII PHY access routines are common for all i/f, use gal_ent0 */
+#define GT6426x_MII_DEVNAME	"gal_enet0"
+
+int gt6426x_miiphy_read(const char *devname, unsigned char phy,
+		unsigned char reg, unsigned short *val);
+
+static inline unsigned short
+miiphy_read_ret(unsigned short phy, unsigned short reg)
+{
+    unsigned short val;
+    gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
+    return val;
+}
+
+
+/**************************************************************************
+RESET - Reset adapter
+***************************************************************************/
+void
+gt6426x_eth_reset(void *v)
+{
+	/*  we should do something here...
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = wp->priv;
+	*/
+
+	printf ("RESET\n");
+	/* put the card in its initial state */
+}
+
+static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
+{
+#ifdef DEBUG
+    printf("SMI interrupt: ");
+
+    if(icr&0x20000000) {
+	printf("SMI done\n");
+    }
+#endif
+
+    if(icr&0x10000000) {
+	unsigned int psr;
+	psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
+#ifdef DEBUG
+	printf("PHY state change:\n"
+	       "  GT:%s:%s:%s:%s\n",
+		psr&1?"100":" 10",
+		psr&8?" Link":"nLink",
+		psr&2?"FD":"HD",
+		psr&4?" FC":"nFC");
+
+#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
+	{
+	unsigned short mii_11;
+	mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
+
+	printf(" mii:%s:%s:%s:%s %s:%s %s\n",
+		mii_11&(1<<14)?"100":" 10",
+		mii_11&(1<<10)?" Link":"nLink",
+		mii_11&(1<<9)?"FD":"HD",
+		mii_11&(1<<4)?" FC":"nFC",
+
+		mii_11&(1<<7)?"ANc":"ANnc",
+		mii_11&(1<<8)?"AN":"Manual",
+		""
+		);
+	}
+#endif /* CONFIG_INTEL_LXT97X */
+#endif /* DEBUG */
+    }
+}
+
+static int
+gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
+{
+	int eth_len=0;
+	char *eth_data;
+
+	eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
+
+	INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
+
+	if (rx->command_status & 0x80000000) {
+		return 0; /* No packet received */
+	}
+
+	eth_len = (unsigned int)
+		(rx->buff_size_byte_count) & 0x0000ffff;
+	eth_data = (char *) p->eth_rx_buffer[p->rdn];
+
+#ifdef DEBUG
+	if (eth_len) {
+		printf ("%s: Recived %d byte Packet @ 0x%p\n",
+			__FUNCTION__, eth_len, eth_data);
+	}
+#endif
+	/*
+	 * packet is now in:
+	 * eth0_rx_buffer[RDN_ETH0];
+	 */
+
+	/* let the upper layer handle the packet */
+	NetReceive ((uchar *)eth_data, eth_len);
+
+	rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
+
+
+	/* GT96100 Owner */
+	rx->command_status = 0x80000000;
+
+	FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
+
+	p->rdn ++;
+	if (p->rdn == NR) {p->rdn = 0;}
+
+	sync();
+
+	/* Start Rx*/
+	GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
+
+#ifdef DEBUG
+	{
+	    int i;
+	    for (i=0;i<12;i++) {
+		printf(" %02x", eth_data[i]);
+	    }
+	}
+	printf(": %d bytes\n", eth_len);
+#endif
+	INVALIDATE_DCACHE((unsigned int)eth_data,
+		(unsigned int)eth_data+eth_len);
+	return eth_len;
+}
+
+/**************************************************************************
+POLL - look for an rx frame, handle other conditions
+***************************************************************************/
+int
+gt6426x_eth_poll(void *v)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = wp->priv;
+	unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
+
+	if(icr) {
+	    GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
+#ifdef DEBUG
+	    printf("poll got ICR %08x\n", icr);
+#endif
+	    /* SMI done or PHY state change*/
+	    if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
+	}
+	/* always process. We aren't using RX interrupts */
+	return gt6426x_eth_receive(p, icr);
+}
+
+/**************************************************************************
+TRANSMIT - Transmit a frame
+***************************************************************************/
+int
+gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
+#ifdef DEBUG
+	unsigned int old_command_stat,old_psr;
+#endif
+	eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
+
+	/* wait for tx to be ready */
+	INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+	while (tx->command_status & 0x80000000) {
+	    int i;
+	    for(i=0;i<1000;i++);
+			INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+	}
+
+	GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
+		      (unsigned int)tx);
+
+#ifdef DEBUG
+	printf("copying to tx_buffer [%p], length %x, desc = %p\n",
+	       dev->eth_tx_buffer, s, dev->eth_tx_desc);
+#endif
+	memcpy(dev->eth_tx_buffer, (char *) p, s);
+
+	tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
+	tx->bytecount_reserved = ((__u16)s) << 16;
+
+	/*    31 - own
+	 *    22 - gencrc
+	 * 18:16 - pad, last, first */
+	tx->command_status = (1<<31) | (1<<22) | (7<<16);
+#if 0
+	/* FEr #18 */
+	tx->next_desc = NULL;
+#else
+	tx->next_desc =
+		(struct eth0_tx_desc_struct *)
+		&dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
+
+	/* cpu owned */
+	dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16);	/* pad, last, first */
+#endif
+
+#ifdef DEBUG
+	old_command_stat=tx->command_status,
+	old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+#endif
+
+	FLUSH_DCACHE((unsigned int)tx,
+		(unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
+
+	FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
+
+	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
+
+#ifdef DEBUG
+	{
+	    unsigned int command_stat=0;
+	    printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
+	    /* wait for tx to be ready */
+	    do {
+		unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+		command_stat=tx->command_status;
+		if(command_stat!=old_command_stat || psr !=old_psr) {
+		    printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
+		    old_command_stat = command_stat;
+		    old_psr = psr;
+		}
+		/* gt6426x_eth0_poll(); */
+	    } while (command_stat & 0x80000000);
+
+	    printf("sent %d byte frame\n", s);
+
+	    if((command_stat & (3<<15)) == 3) {
+		printf("frame had error (stat=%08x)\n", command_stat);
+	    }
+	}
+#endif
+	return 0;
+}
+
+/**************************************************************************
+DISABLE - Turn off ethernet interface
+***************************************************************************/
+void
+gt6426x_eth_disable(void *v)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+
+	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
+}
+
+/**************************************************************************
+MII utilities - write: write to an MII register via SMI
+***************************************************************************/
+int
+gt6426x_miiphy_write(const char *devname, unsigned char phy,
+		unsigned char reg, unsigned short data)
+{
+    unsigned int temp= (reg<<21) | (phy<<16) | data;
+
+    while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));	/* wait for !Busy */
+
+    GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
+    return 0;
+}
+
+/**************************************************************************
+MII utilities - read: read from an MII register via SMI
+***************************************************************************/
+int
+gt6426x_miiphy_read(const char *devname, unsigned char phy,
+		unsigned char reg, unsigned short *val)
+{
+    unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
+
+    while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));	/* wait for !Busy */
+
+    GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
+
+    while(1) {
+	temp=GTREGREAD(ETHERNET_SMI_REGISTER);
+	if(temp & (1<<27)) break;		/* wait for ReadValid */
+    }
+    *val = temp & 0xffff;
+
+    return 0;
+}
+
+#ifdef DEBUG
+/**************************************************************************
+MII utilities - dump mii registers
+***************************************************************************/
+static void
+gt6426x_dump_mii(bd_t *bis, unsigned short phy)
+{
+	printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
+		miiphy_read_ret(phy, 0x0),
+		miiphy_read_ret(phy, 0x1),
+		miiphy_read_ret(phy, 0x2),
+		miiphy_read_ret(phy, 0x3)
+		);
+	printf("        4 - 7:   %04x %04x %04x %04x\n",
+		miiphy_read_ret(phy, 0x4),
+		miiphy_read_ret(phy, 0x5),
+		miiphy_read_ret(phy, 0x6),
+		miiphy_read_ret(phy, 0x7)
+		);
+	printf("        8:       %04x\n",
+		miiphy_read_ret(phy, 0x8)
+		);
+	printf("        16-19:   %04x %04x %04x %04x\n",
+		miiphy_read_ret(phy, 0x10),
+		miiphy_read_ret(phy, 0x11),
+		miiphy_read_ret(phy, 0x12),
+		miiphy_read_ret(phy, 0x13)
+		);
+	printf("        20,30:   %04x %04x\n",
+		miiphy_read_ret(phy, 20),
+		miiphy_read_ret(phy, 30)
+		);
+}
+#endif
+
+#ifdef RESTART_AUTONEG
+
+/* If link is up && autoneg compleate, and if
+ * GT and PHY disagree about link capabilitys,
+ * restart autoneg - something screwy with FD/HD
+ * unless we do this. */
+static void
+check_phy_state(struct eth_dev_s *p)
+{
+	int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
+	int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
+
+	if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
+		int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
+				miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
+		int want;
+
+		if (nego & LPA_100FULL) {
+			want = 0x3;
+			printf("MII: 100Base-TX, Full Duplex\n");
+		} else if (nego & LPA_100HALF) {
+			want = 0x1;
+			printf("MII: 100Base-TX, Half Duplex\n");
+		} else if (nego & LPA_10FULL) {
+			want = 0x2;
+			printf("MII: 10Base-T, Full Duplex\n");
+		} else if (nego & LPA_10HALF) {
+			want = 0x0;
+			printf("MII: 10Base-T, Half Duplex\n");
+		} else {
+			printf("MII: Unknown link-foo! %x\n", nego);
+			return;
+		}
+
+		if ((psr & 0x3) != want) {
+			printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
+					psr & 0x3, want);
+			miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
+					miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
+			udelay(10000);	/* the EVB's GT takes a while to notice phy
+					   went down and up */
+		}
+	}
+}
+#endif
+
+/**************************************************************************
+PROBE - Look for an adapter, this routine's visible to the outside
+***************************************************************************/
+int
+gt6426x_eth_probe(void *v, bd_t *bis)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+	int dev = p->dev;
+	unsigned int reg_base = p->reg_base;
+	unsigned long temp;
+	int i;
+
+	if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
+	{	/* This should never happen */
+		printf("%s: Invalid device %d\n", __FUNCTION__, dev );
+		return 0;
+	}
+
+#ifdef DEBUG
+	printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
+	printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
+		GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
+		GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
+#endif
+
+	/* clear MIB counters */
+	for(i=0;i<255; i++)
+	    temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
+
+#ifdef CONFIG_INTEL_LXT97X
+	/* for intel LXT972 */
+
+	/* led 1: 0x1=txact
+	   led 2: 0xc=link/rxact
+	   led 3: 0x2=rxact (N/C)
+	   strch: 0,2=30 ms, enable */
+	miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
+
+	/* 2.7ns port rise time */
+	/*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
+#else
+	/* already set up in mpsc.c */
+	/*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);	/  b400 */
+
+	/* already set up in sdram_init.S... */
+	/* MPSC0, MPSC1, RMII */
+	/*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);		/  f010 */
+#endif
+	GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
+	     ether_port_phy_addr[0]     |
+	    (ether_port_phy_addr[1]<<5) |
+	    (ether_port_phy_addr[2]<<10));			/* 2000 */
+
+	/* 13:12 -   10: 4x64bit burst	(cache line size = 32 bytes)
+	 *    9  -    1: RIFB - interrupt on frame boundaries only
+	 *  6:7  -   00: big endian rx and tx
+	 *  5:2  - 1111: 15 retries */
+	GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
+		(2<<12) | (1<<9) | (0xf<<2) );			/* 2440 */
+
+#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
+	/* enable rx/tx desc/buffer cache snoop */
+	GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
+		&temp);						/* f200 */
+	temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
+	GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
+		temp);
+#endif
+
+	/* 31  28 27  24 23  20 19  16
+	 *  0000   0000   0000   0000	[0004]
+	 * 15  12 11  8   7  4   3  0
+	 *  1000   1101   0000   0000	[4d00]
+	 *    20 - 0=MII 1=RMII
+	 *    19 - 0=speed autoneg
+	 * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
+	 *    11 - no force link pass
+	 *    10 - 1=disable fctl autoneg
+	 *     8 - override prio ?? */
+	temp = 0x00004d00;
+#ifndef CONFIG_ETHER_PORT_MII
+	temp |= (1<<20);	/* RMII */
+#endif
+	/* set En */
+	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
+		     temp);				/* 2408 */
+
+	/* hardcode E1 also? */
+	/* -- according to dox, this is safer due to extra pulldowns? */
+	if (dev<2) {
+	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
+		     temp);				/* 2408 */
+	}
+
+	/* wake up MAC */				 /* 2400 */
+	GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
+	temp |= (1<<7);		/* enable port */
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+	temp |= (1<<12);	/* hash size 1/2k */
+#else
+	temp |= 1;		/* promisc */
+#endif
+	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
+							/* 2400 */
+
+#ifdef RESTART_AUTONEG
+	check_phy_state(p);
+#endif
+
+	printf("%s: Waiting for link up..\n", wp->name);
+	temp = 10 * 1000;
+	/* wait for link back up */
+	while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
+			&& (--temp > 0)){
+	    udelay(1000);	/* wait 1 ms */
+	}
+	if ( temp == 0) {
+		printf("%s: Failed!\n", wp->name);
+		return (0);
+	}
+
+	printf("%s: OK!\n", wp->name);
+
+	p->tdn = 0;
+	p->rdn = 0;
+	p->eth_tx_desc[p->tdn].command_status = 0;
+
+	/* Initialize Rx Side */
+	for (temp = 0; temp < NR; temp++) {
+		p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
+		p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
+
+		/* GT96100 Owner */
+		p->eth_rx_desc[temp].command_status = 0x80000000;
+		p->eth_rx_desc[temp].next_desc =
+			(struct eth0_rx_desc_struct *)
+			&p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
+	}
+
+	FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
+		     (unsigned int)&p->eth_tx_desc[NR]);
+	FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
+		     (unsigned int)&p->eth_rx_desc[NR]);
+
+	GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
+		      (unsigned int) p->eth_tx_desc);
+	GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
+		      (unsigned int) p->eth_rx_desc);
+	GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
+		      (unsigned int) p->eth_rx_desc);
+
+#ifdef DEBUG
+	printf ("\nRx descriptor pointer is %08x %08x\n",
+		GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
+		GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
+	printf ("\n\n%08x %08x\n",
+		(unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
+
+	printf ("Descriptor dump:\n");
+	printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
+	printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
+	printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
+	printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
+	printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
+	printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
+	printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
+	printf ("%08x\n\n",
+		*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
+#endif
+
+#ifdef DEBUG
+	gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
+#endif
+
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+	{
+		unsigned int hashtable_base;
+	    u8 *b = (u8 *)(wp->enetaddr);
+		u32 macH, macL;
+
+		/* twist the MAC up into the way the discovery wants it */
+		macH= (b[0]<<8) | b[1];
+	    macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
+
+	    /* mode 0, size 0x800 */
+	    hashtable_base =initAddressTable(dev,0,1);
+
+	    if(!hashtable_base) {
+			printf("initAddressTable failed\n");
+			return 0;
+	    }
+
+	    addAddressTableEntry(dev, macH, macL, 1, 0);
+	    GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
+		    hashtable_base);
+	}
+#endif
+
+	/* Start Rx*/
+	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
+	printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
+	return 1;
+}
+
+/* enter all the galileo ethernet devs into MULTI-BOOT */
+void
+gt6426x_eth_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	struct eth_dev_s *p;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+#ifdef DEBUG
+	printf( "\n%s\n", __FUNCTION );
+#endif
+
+	for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
+		dev = calloc(sizeof(*dev), 1);
+		if (!dev) {
+			printf( "%s: gal_enet%d allocation failure, %s\n",
+					__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf(dev->name, "gal_enet%d", devnum);
+
+#ifdef DEBUG
+		printf( "Initializing %s\n", dev->name );
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum)
+		{
+			case 0: s = "ethaddr"; break;
+#if (GAL_ETH_DEVS > 1)
+			case 1: s = "eth1addr"; break;
+#endif
+#if (GAL_ETH_DEVS > 2)
+			case 2: s = "eth2addr";	break;
+#endif
+			default: /* this should never happen */
+				printf( "%s: Invalid device number %d\n",
+						__FUNCTION__, devnum );
+				return;
+		}
+
+		temp = getenv_f(s, buf, sizeof(buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s );
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e+1 : e;
+		}
+
+		dev->init = (void*)gt6426x_eth_probe;
+		dev->halt = (void*)gt6426x_eth_reset;
+		dev->send = (void*)gt6426x_eth_transmit;
+		dev->recv = (void*)gt6426x_eth_poll;
+
+		p = calloc( sizeof(*p), 1 );
+		dev->priv = (void*)p;
+		if (!p)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Private Device Structure");
+			free(dev);
+			return;
+		}
+
+		p->dev = devnum;
+		p->tdn=0;
+		p->rdn=0;
+		p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
+
+		p->eth_tx_desc =
+			(eth0_tx_desc_single *)
+			(((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
+						(NT+1)) & 0xfffffff0) + 0x10);
+		if (!p)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Tx Descriptor");
+			free(dev);
+			return;
+		}
+
+		p->eth_rx_desc =
+			(eth0_rx_desc_single *)
+			(((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
+						(NR+1)) & 0xfffffff0) + 0x10);
+		if (!p->eth_rx_desc)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Rx Descriptor");
+			free(dev);
+			free(p);
+			return;
+		}
+
+		p->eth_tx_buffer =
+			(char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+		if (!p->eth_tx_buffer)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Tx Bufffer");
+			free(dev);
+			free(p);
+			free(p->eth_rx_desc);
+			return;
+		}
+
+		for (temp = 0 ; temp < NR ; temp ++) {
+			p->eth_rx_buffer[temp] =
+				(char *)
+				(((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+			if (!p->eth_rx_buffer[temp])
+			{
+				printf( "%s: %s allocation failure, %s\n",
+						__FUNCTION__, dev->name, "Rx Buffers");
+				free(dev);
+				free(p);
+				free(p->eth_tx_buffer);
+				free(p->eth_rx_desc);
+				free(p->eth_tx_desc);
+				while (temp >= 0)
+					free(p->eth_rx_buffer[--temp]);
+				return;
+			}
+		}
+
+
+		eth_register(dev);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+		miiphy_register(dev->name,
+				gt6426x_miiphy_read, gt6426x_miiphy_write);
+#endif
+	}
+
+}
+#endif
diff --git a/u-boot/board/evb64260/eth.h b/u-boot/board/evb64260/eth.h
new file mode 100644
index 0000000..beb6db1
--- /dev/null
+++ b/u-boot/board/evb64260/eth.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __GT6426x_ETH_H__
+#define __GT6426x_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+typedef struct eth0_tx_desc_struct {
+	volatile __u32 bytecount_reserved;
+	volatile __u32 command_status;
+	volatile struct eth0_tx_desc_struct * next_desc;
+	/* Note - the following will not work for 64 bit addressing */
+	volatile unsigned char * buff_pointer;
+} __attribute__ ((packed)) eth0_tx_desc_single;
+
+typedef struct eth0_rx_desc_struct {
+  volatile __u32 buff_size_byte_count;
+  volatile __u32 command_status;
+  volatile struct eth0_rx_desc_struct * next_desc;
+  volatile unsigned char * buff_pointer;
+} __attribute__ ((packed)) eth0_rx_desc_single;
+
+#define NT 20 /* Number of Transmit buffers */
+#define NR 20 /* Number of Receive buffers */
+#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */
+#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
+
+unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/
+unsigned int EVB64260_ETH0_irq;
+
+#define CLOSED 0
+#define OPENED 1
+
+#define PORT_ETH0 0
+
+extern eth0_tx_desc_single *eth0_tx_desc;
+extern eth0_rx_desc_single *eth0_rx_desc;
+extern char *eth0_tx_buffer;
+extern char *eth0_rx_buffer[NR];
+extern char *eth_data;
+
+extern int gt6426x_eth_poll(void *v);
+extern int gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s);
+extern void gt6426x_eth_disable(void *v);
+extern int gt6426x_eth_probe(void *v, bd_t *bis);
+
+#endif  /* __GT64260x_ETH_H__ */
diff --git a/u-boot/board/evb64260/eth_addrtbl.c b/u-boot/board/evb64260/eth_addrtbl.c
new file mode 100644
index 0000000..e8ef0e3
--- /dev/null
+++ b/u-boot/board/evb64260/eth_addrtbl.c
@@ -0,0 +1,221 @@
+#include <common.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+#include <asm/cache.h>
+#include "eth.h"
+#include "eth_addrtbl.h"
+
+#define TRUE 1
+#define FALSE 0
+
+#define PRINTF printf
+
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+
+static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
+static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
+static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
+static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
+
+static const u32 hashLength[2] = {
+	(0x8000),		/* 8K * 4 entries */
+	(0x8000 / 16),		/* 512 * 4 entries */
+};
+
+/* Initialize the address table for a port, if needed */
+unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
+{
+	unsigned int tableBase;
+
+	if (port < 0 || port >= GAL_ETH_DEVS) {
+		printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
+		return 0;
+	}
+
+	if (hashMode > 1) {
+		printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
+		return 0;
+	}
+
+	if (realAddrTableBase[port] &&
+	    (addressTableHashSize[port] != hashSizeSelector)) {
+		/* we have been here before,
+		 * but now we want a different sized table
+		 */
+		free (realAddrTableBase[port]);
+		realAddrTableBase[port] = 0;
+		addressTableBase[port] = 0;
+
+	}
+
+	tableBase = (unsigned int) addressTableBase[port];
+	/* we get called for every probe, so only do this once */
+	if (!tableBase) {
+		int bytes =
+			hashLength[hashSizeSelector] * sizeof (addrTblEntry);
+
+		realAddrTableBase[port] =
+			malloc (bytes + 64);
+		tableBase = (unsigned int)realAddrTableBase;
+
+		if (!tableBase) {
+			printf ("%s: alloc memory failed \n", __FUNCTION__);
+			return 0;
+		}
+
+		/* align to octal byte */
+		if (tableBase & 63)
+			tableBase = (tableBase + 63) & ~63;
+
+		addressTableHashMode[port] = hashMode;
+		addressTableHashSize[port] = hashSizeSelector;
+		addressTableBase[port] = (addrTblEntry *) tableBase;
+
+		memset ((void *) tableBase, 0, bytes);
+	}
+
+	return tableBase;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * This function will calculate the hash function of the address.
+ * depends on the hash mode and hash size.
+ * Inputs
+ * macH             - the 2 most significant bytes of the MAC address.
+ * macL             - the 4 least significant bytes of the MAC address.
+ * hashMode         - hash mode 0 or hash mode 1.
+ * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800)
+ * Outputs
+ * return the calculated entry.
+ */
+u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
+{
+	u32 hashResult;
+	u32 addrH;
+	u32 addrL;
+	u32 addr0;
+	u32 addr1;
+	u32 addr2;
+	u32 addr3;
+	u32 addrHSwapped;
+	u32 addrLSwapped;
+
+
+	addrH = NIBBLE_SWAPPING_16_BIT (macH);
+	addrL = NIBBLE_SWAPPING_32_BIT (macL);
+
+	addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+		+ ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
+
+	addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+		+ ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+		+ ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+		+ ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+		+ ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+		+ ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
+
+	addrH = addrHSwapped;
+	addrL = addrLSwapped;
+
+	if (hash_mode == 0) {
+		addr0 = (addrL >> 2) & 0x03f;
+		addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
+		addr2 = (addrL >> 15) & 0x1ff;
+		addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
+	} else {
+		addr0 = FLIP_6_BITS (addrL & 0x03f);
+		addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
+		addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
+		addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
+				      ((addrH & 0x1) << 8)));
+	}
+
+	hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+
+	if (HashSize == _8K_TABLE) {
+		hashResult = hashResult & 0xffff;
+	} else {
+		hashResult = hashResult & 0x07ff;
+	}
+
+	return (hashResult);
+}
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * This function will add an entry to the address table.
+ * depends on the hash mode and hash size that was initialized.
+ * Inputs
+ * port - ETHERNET port number.
+ * macH - the 2 most significant bytes of the MAC address.
+ * macL - the 4 least significant bytes of the MAC address.
+ * skip - if 1, skip this address.
+ * rd   - the RD field in the address table.
+ * Outputs
+ * address table entry is added.
+ * TRUE if success.
+ * FALSE if table full
+ */
+int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
+{
+	addrTblEntry *entry;
+	u32 newHi;
+	u32 newLo;
+	u32 i;
+
+	newLo = (((macH >> 4) & 0xf) << 15)
+		| (((macH >> 0) & 0xf) << 11)
+		| (((macH >> 12) & 0xf) << 7)
+		| (((macH >> 8) & 0xf) << 3)
+		| (((macL >> 20) & 0x1) << 31)
+		| (((macL >> 16) & 0xf) << 27)
+		| (((macL >> 28) & 0xf) << 23)
+		| (((macL >> 24) & 0xf) << 19)
+		| (skip << SKIP_BIT) | (rd << 2) | VALID;
+
+	newHi = (((macL >> 4) & 0xf) << 15)
+		| (((macL >> 0) & 0xf) << 11)
+		| (((macL >> 12) & 0xf) << 7)
+		| (((macL >> 8) & 0xf) << 3)
+		| (((macL >> 21) & 0x7) << 0);
+
+	/*
+	 * Pick the appropriate table, start scanning for free/reusable
+	 * entries at the index obtained by hashing the specified MAC address
+	 */
+	entry = addressTableBase[port];
+	entry += hashTableFunction (macH, macL, addressTableHashSize[port],
+				    addressTableHashMode[port]);
+	for (i = 0; i < HOP_NUMBER; i++, entry++) {
+		if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
+			break;
+		} else {	/* if same address put in same position */
+			if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
+			    && (entry->hi == newHi)) {
+				break;
+			}
+		}
+	}
+
+	if (i == HOP_NUMBER) {
+		PRINTF ("addGT64260addressTableEntry: table section is full\n");
+		return (FALSE);
+	}
+
+	/*
+	 * Update the selected entry
+	 */
+	entry->hi = newHi;
+	entry->lo = newLo;
+	DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
+	return (TRUE);
+}
+
+#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
diff --git a/u-boot/board/evb64260/eth_addrtbl.h b/u-boot/board/evb64260/eth_addrtbl.h
new file mode 100644
index 0000000..5a62c67
--- /dev/null
+++ b/u-boot/board/evb64260/eth_addrtbl.h
@@ -0,0 +1,83 @@
+#ifndef _ADDRESS_TABLE_H
+#define _ADDRESS_TABLE_H 1
+
+/*
+ * ----------------------------------------------------------------------------
+ * addressTable.h - this file has all the declarations of the address table
+ */
+
+#define _8K_TABLE                           0
+#define ADDRESS_TABLE_ALIGNMENT             8
+#define HASH_DEFAULT_MODE                   14
+#define HASH_MODE                           13
+#define HASH_SIZE                           12
+#define HOP_NUMBER                          12
+#define MAC_ADDRESS_STRING_SIZE             12
+#define MAC_ENTRY_SIZE                      sizeof(addrTblEntry)
+#define MAX_NUMBER_OF_ADDRESSES_TO_STORE    1000
+#define PROMISCUOUS_MODE                    0
+#define SKIP                                1<<1
+#define SKIP_BIT                            1
+#define VALID                               1
+
+/*
+ * ----------------------------------------------------------------------------
+ * XXX_MIKE - potential sign-extension bugs lurk here...
+ */
+#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \
+				  | (((X) & 0x0f0f0f0f) << 4) )
+
+#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \
+				  | (((X) & 0x00000f0f) << 4) )
+
+#define FLIP_4_BITS(X)  ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \
+			| (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) )
+
+#define FLIP_6_BITS(X)  ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \
+			| (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \
+			| (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) )
+
+#define FLIP_9_BITS(X)  ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \
+			| (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \
+			| (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \
+	 | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) )
+
+/*
+ * V: value we're operating on
+ * O: offset of rightmost bit in field
+ * W: width of field to shift
+ * S: distance to shift left
+ */
+#define MASK( fieldWidth )                            ((1 << (fieldWidth)) - 1)
+#define leftShiftedBitfield( V,O,W,S)        (((V) & (MASK(W) << (O)))  << (S))
+#define rightShiftedBitfield(V,O,W,S)  (((u32)((V) & (MASK(W) << (O)))) >> (S))
+
+
+/*
+ * Push to main memory all cache lines associated with
+ * the specified range of virtual memory addresses
+ *
+ * A: Address of first byte in range to flush
+ * N: Number of bytes to flush
+ * Note - flush_dcache_range() does a "sync", does NOT invalidate
+ */
+#define DCACHE_FLUSH_N_SYNC( A, N )        flush_dcache_range( (A), ((A)+(N)) )
+
+
+typedef struct addressTableEntryStruct  {
+    u32 hi;
+    u32 lo;
+} addrTblEntry;
+
+u32
+uncachedPages( u32 pages  );
+u32
+hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode );
+
+unsigned int
+initAddressTable( u32 port, u32 hashMode, u32 hashSize );
+
+int
+addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip          );
+
+#endif                                           /* #ifndef _ADDRESS_TABLE_H */
diff --git a/u-boot/board/evb64260/evb64260.c b/u-boot/board/evb64260/evb64260.c
new file mode 100644
index 0000000..80756a5
--- /dev/null
+++ b/u-boot/board/evb64260/evb64260.c
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * evb64260.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <galileo/memory.h>
+#include <galileo/pci.h>
+#include <galileo/gt64260R.h>
+#include <net.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64260.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ZUMA_V2
+extern void zuma_mbox_init(void);
+#endif
+
+#undef	DEBUG
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void
+my_remap_gt_regs(u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+}
+
+static void
+gt_pci_config(void)
+{
+	/* move PCI stuff out of the way - NTL */
+	/* map PCI Host 0 */
+	pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE,
+		CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE);
+
+	pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
+	pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
+	pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
+
+	pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI,
+		CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE);
+
+	/* map PCI Host 1 */
+	pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE,
+		CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE);
+
+	pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
+	pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
+	pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
+
+	pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI,
+		CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE);
+
+	/* PCI interface settings */
+	GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
+	GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
+	GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
+	GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
+
+
+}
+
+/* Setup CPU interface paramaters */
+static void
+gt_cpu_config(void)
+{
+	cpu_t cpu = get_cpu_type();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD(CPU_CONFIGURATION);
+
+	/* set the AACK delay bit
+	 * see Res#14 */
+	tmp |= CPU_CONF_AACK_DELAY;
+	tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
+
+	/* Galileo claims this is necessary for all busses >= 100 MHz */
+	tmp |= CPU_CONF_FAST_CLK;
+
+	if (cpu == CPU_750CX) {
+		tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
+		tmp &= ~CPU_CONF_AP_VALID;
+	} else {
+		tmp |= CPU_CONF_DP_VALID;
+		tmp |= CPU_CONF_AP_VALID;
+	}
+
+	/* this only works with the MPX bus */
+	tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
+	tmp |= CPU_CONF_PIPELINE;
+	tmp |= CPU_CONF_TA_DELAY;
+
+	GT_REG_WRITE(CPU_CONFIGURATION, tmp);
+
+	/* CPU master control register */
+	tmp = GTREGREAD(CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) ||
+	    (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+	my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+	gt_pci_config();
+
+	/* mask all external interrupt sources */
+	GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	GT_REG_WRITE(CPU_INT_3_MASK, 0);
+
+	/* now, onto the configuration */
+	GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG);
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM
+	 * 1 - RTC
+	 * 2 - UART
+	 * 3 - Flash
+	 * boot - BootCS
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+	/* Zuma has no SRAM */
+	sram_boot = 0;
+#else
+	if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE)
+		sram_boot = 1;
+#endif
+
+		memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+
+	memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
+
+	/* configure device timing */
+#ifdef CONFIG_SYS_DEV0_PAR
+	if (!sram_boot)
+		GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+#endif
+
+#ifdef CONFIG_SYS_DEV1_PAR
+	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+#endif
+#ifdef CONFIG_SYS_DEV2_PAR
+	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+#endif
+
+#ifdef CONFIG_EVB64260
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+#endif
+#else /* CONFIG_EVB64260 not defined */
+		/* We are booting from 16-bit flash.
+		 */
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR);
+#endif
+
+	gt_cpu_config();
+
+	/* MPP setup */
+	GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+	GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX);
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r (void)
+{
+	icache_enable();
+#ifdef CONFIG_SYS_L2
+	l2cache_enable();
+#endif
+
+#ifdef CONFIG_MPSC
+	mpsc_init2();
+#endif
+
+#ifdef CONFIG_ZUMA_V2
+	zuma_mbox_init();
+#endif
+	return (0);
+}
+
+void
+after_reloc(ulong dest_addr)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+
+	if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) {
+		memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M);
+	}
+
+	/* now, jump to the main U-Boot board init code */
+	board_init_r ((gd_t *)gd, dest_addr);
+
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int
+checkboard (void)
+{
+	puts ("Board: " CONFIG_SYS_BOARD_NAME "\n");
+	return (0);
+}
+
+/* utility functions */
+void
+debug_led(int led, int mode)
+{
+#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
+	volatile int *addr = NULL;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000);
+			break;
+
+		case 1:
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000);
+			break;
+
+		case 2:
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000);
+			break;
+
+		case 1:
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000);
+			break;
+
+		case 2:
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000);
+			break;
+		}
+	}
+	WRITE_CHAR(addr, 0);
+	dummy = *addr;
+#endif /* CONFIG_ZUMA_V2 */
+}
+
+void
+display_mem_map(void)
+{
+    int i,j;
+    unsigned int base,size,width;
+    /* SDRAM */
+    printf("SDRAM\n");
+    for(i=0;i<=BANK3;i++) {
+	base = memoryGetBankBaseAddress(i);
+	size = memoryGetBankSize(i);
+	if(size !=0)
+	{
+	    printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
+	}
+    }
+
+    /* CPU's PCI windows */
+    for(i=0;i<=PCI_HOST1;i++) {
+	printf("\nCPU's PCI %d windows\n", i);
+	base=pciGetSpaceBase(i,PCI_IO);
+	size=pciGetSpaceSize(i,PCI_IO);
+	printf("      IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
+	for(j=0;j<=PCI_REGION3;j++) {
+	    base = pciGetSpaceBase(i,j);
+	    size = pciGetSpaceSize(i,j);
+	    printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
+		    size>>20);
+	}
+    }
+
+    /* Devices */
+    printf("\nDEVICES\n");
+	for(i=0;i<=DEVICE3;i++) {
+	base = memoryGetDeviceBaseAddress(i);
+	size = memoryGetDeviceSize(i);
+	width= memoryGetDeviceWidth(i) * 8;
+	printf("DEV %d:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
+	       i, base, size>>20, width);
+    }
+
+    /* Bootrom */
+    base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
+    size = memoryGetDeviceSize(BOOT_DEVICE);
+    width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
+    printf(" BOOT:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
+	   base, size>>20, width);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	gt6426x_eth_initialize(bis);
+	return 0;
+}
diff --git a/u-boot/board/evb64260/flash.c b/u-boot/board/evb64260/flash.c
new file mode 100644
index 0000000..825bbaf
--- /dev/null
+++ b/u-boot/board/evb64260/flash.c
@@ -0,0 +1,853 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * flash.c - flash support for the 512k, 8bit boot flash on the GEVB
+ *           most of this file was based on the existing U-Boot
+ *           flash drivers.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <galileo/gt64260R.h>
+#include <galileo/memory.h>
+#include "intel_flash.h"
+
+#define FLASH_ROM       0xFFFD       /* unknown flash type                   */
+#define FLASH_RAM       0xFFFE       /* unknown flash type                   */
+#define FLASH_MAN_UNKNOWN 0xFFFF0000
+
+/* #define DEBUG */
+/* #define FLASH_ID_OVERRIDE */	/* Hack to set type to 040B if ROM emulator is installed.
+				 * Can be used to program a ROM in circuit if a programmer
+				 * is not available by swapping the rom out. */
+
+/* Intel flash commands */
+int flash_erase_intel(flash_info_t *info, int s_first, int s_last);
+int write_word_intel(bank_addr_t addr, bank_word_t value);
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+	unsigned int i;
+	unsigned long size_b0 = 0, size_b1 = 0;
+	unsigned long base, flash_size;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* the boot flash */
+	base = CONFIG_SYS_FLASH_BASE;
+#ifndef CONFIG_SYS_BOOT_FLASH_WIDTH
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	1
+#endif
+	size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base,
+	                         &flash_info[0]);
+
+#ifndef CONFIG_P3G4
+	printf("[");
+	print_size (size_b0, "");
+	printf("@%08lX] ", base);
+#endif
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
+			base, size_b0, size_b0<<20);
+	}
+
+	base = memoryGetDeviceBaseAddress(CONFIG_SYS_EXTRA_FLASH_DEVICE);
+	for(i=1;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
+	    unsigned long size = flash_get_size(CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);
+
+#ifndef CONFIG_P3G4
+	    printf("[");
+	    print_size (size, "");
+	    printf("@%08lX] ", base);
+#endif
+
+	    if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+		if(i==1) {
+		    printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
+			    base, size_b1, size_b1<<20);
+		}
+		break;
+	    }
+	    size_b1+=size;
+	    base+=size;
+	}
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+	              CONFIG_SYS_MONITOR_BASE,
+	              CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+	              flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef  CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+	              CONFIG_ENV_ADDR,
+	              CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+	              flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	flash_size = size_b0 + size_b1;
+	return flash_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	int sector_size;
+
+	if(!info->sector_count) return;
+
+	/* set up sector start address table */
+	switch(info->flash_id & FLASH_TYPEMASK) {
+	    case FLASH_AM040:
+	    case FLASH_28F128J3A:
+	    case FLASH_28F640J3A:
+	    case FLASH_RAM:
+		/* this chip has uniformly spaced sectors */
+		sector_size=info->size/info->sector_count;
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sector_size);
+		break;
+	    default:
+		if (info->flash_id & FLASH_BTYPE) {
+		    /* set sector offsets for bottom boot block type	*/
+		    info->start[0] = base + 0x00000000;
+		    info->start[1] = base + 0x00008000;
+		    info->start[2] = base + 0x0000C000;
+		    info->start[3] = base + 0x00010000;
+		    for (i = 4; i < info->sector_count; i++) {
+			    info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		    }
+		} else {
+		    /* set sector offsets for top boot block type		*/
+		    i = info->sector_count - 1;
+		    info->start[i--] = base + info->size - 0x00008000;
+		    info->start[i--] = base + info->size - 0x0000C000;
+		    info->start[i--] = base + info->size - 0x00010000;
+		    for (; i >= 0; i--) {
+			    info->start[i] = base + i * 0x00020000;
+		    }
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A (64 Mbit)\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A (128 Mbit)\n");
+		break;
+	case FLASH_ROM:
+		printf ("ROM\n");
+		break;
+	case FLASH_RAM:
+		printf ("RAM\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	puts ("  Size: ");
+	print_size (info->size, "");
+	printf (" in %d Sectors\n", info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd)
+{
+	/* supports 1x8, 1x16, and 2x16 */
+	/* 2x8 and 4x8 are not supported */
+	if(width==4) {
+	    /* assuming chips are in 16 bit mode */
+	    /* 2x16 */
+	    unsigned long cmd32=(cmd<<16)|cmd;
+	    *(volatile unsigned long *)(addr+offset*2)=cmd32;
+	} else if (width == 2) {
+	    /* 1x16 */
+	    *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd;
+	} else {
+	    /* 1x8 */
+	    *(volatile unsigned char *)(addr+offset)=cmd;
+	}
+}
+
+static ulong
+flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr = (unsigned char *)addr;
+	volatile unsigned short *saddr = (unsigned short *)addr;
+	volatile unsigned long *laddr = (unsigned long *)addr;
+	char old[2], save;
+	ulong id, manu, base = (ulong)addr;
+
+	info->portwidth=portwidth;
+
+	save = *caddr;
+
+	flash_cmd(portwidth,caddr,0,0xf0);
+	flash_cmd(portwidth,caddr,0,0xf0);
+
+	udelay(10);
+
+	old[0] = caddr[0];
+	old[1] = caddr[1];
+
+
+	if(old[0]!=0xf0) {
+	    flash_cmd(portwidth,caddr,0,0xf0);
+	    flash_cmd(portwidth,caddr,0,0xf0);
+
+	    udelay(10);
+
+	    if(*caddr==0xf0) {
+		/* this area is ROM */
+		*caddr=save;
+#ifndef FLASH_ID_OVERRIDE
+		info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+		info->sector_count = 8;
+		info->size = 0x80000;
+#else
+		info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		info->chipwidth=1;
+#endif
+		flash_get_offsets(base, info);
+		return info->size;
+	    }
+	} else {
+	    *caddr=0;
+
+	    udelay(10);
+
+	    if(*caddr==0) {
+		/* this area is RAM */
+		*caddr=save;
+		info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		flash_get_offsets(base, info);
+		return info->size;
+	    }
+	    flash_cmd(portwidth,caddr,0,0xf0);
+
+	    udelay(10);
+	}
+
+	/* Write auto select command: read Manufacturer ID */
+	flash_cmd(portwidth,caddr,0x555,0xAA);
+	flash_cmd(portwidth,caddr,0x2AA,0x55);
+	flash_cmd(portwidth,caddr,0x555,0x90);
+
+	udelay(10);
+
+	if ((caddr[0] == old[0]) &&
+	    (caddr[1] == old[1])) {
+
+	    /* this area is ROM */
+#ifndef FLASH_ID_OVERRIDE
+	    info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+	    info->sector_count = 8;
+	    info->size = 0x80000;
+#else
+		info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		info->chipwidth=1;
+#endif
+	    flash_get_offsets(base, info);
+	    return info->size;
+#ifdef DEBUG
+	} else {
+	    printf("%px%d: %02x:%02x -> %02x:%02x\n",
+		    caddr, portwidth, old[0], old[1],
+		    caddr[0], caddr[1]);
+#endif
+	}
+
+	switch(portwidth) {
+	    case 1:
+		manu = caddr[0];
+		manu |= manu<<16;
+		id = caddr[1];
+		break;
+	    case 2:
+		manu = saddr[0];
+		manu |= manu<<16;
+		id = saddr[1];
+		id |= id<<16;
+		break;
+	    case 4:
+		manu = laddr[0];
+		id = laddr[1];
+		break;
+	default:
+		id = manu = -1;
+		break;
+	}
+
+#ifdef DEBUG
+	printf("\n%08lx:%08lx:%08lx\n", base, manu, id);
+	printf("%08lx %08lx %08lx %08lx\n",
+		laddr[0],laddr[1],laddr[2],laddr[3]);
+#endif
+
+	switch (manu) {
+	    case AMD_MANUFACT:
+		    info->flash_id = FLASH_MAN_AMD;
+		    break;
+	    case FUJ_MANUFACT:
+		    info->flash_id = FLASH_MAN_FUJ;
+		    break;
+	    case INTEL_MANUFACT:
+		    info->flash_id = FLASH_MAN_INTEL;
+		    break;
+	    default:
+		    printf("Unknown Mfr [%08lx]:%08lx\n", manu, id);
+		    info->flash_id = FLASH_UNKNOWN;
+		    info->sector_count = 0;
+		    info->size = 0;
+		    return (0);			/* no or unknown flash	*/
+	}
+
+	switch (id) {
+	    case AMD_ID_LV400T:
+		    info->flash_id += FLASH_AM400T;
+		    info->sector_count = 11;
+		    info->size = 0x00100000;
+		    info->chipwidth=1;
+		    break;				/* => 1 MB	*/
+
+	    case AMD_ID_LV400B:
+		    info->flash_id += FLASH_AM400B;
+		    info->sector_count = 11;
+		    info->size = 0x00100000;
+		    info->chipwidth=1;
+		    break;				/* => 1 MB	*/
+
+	    case AMD_ID_LV800T:
+		    info->flash_id += FLASH_AM800T;
+		    info->sector_count = 19;
+		    info->size = 0x00200000;
+		    info->chipwidth=1;
+		    break;				/* => 2 MB	*/
+
+	    case AMD_ID_LV800B:
+		    info->flash_id += FLASH_AM800B;
+		    info->sector_count = 19;
+		    info->size = 0x00200000;
+		    info->chipwidth=1;
+		    break;				/* => 2 MB	*/
+
+	    case AMD_ID_LV160T:
+		    info->flash_id += FLASH_AM160T;
+		    info->sector_count = 35;
+		    info->size = 0x00400000;
+		    info->chipwidth=1;
+		    break;				/* => 4 MB	*/
+
+	    case AMD_ID_LV160B:
+		    info->flash_id += FLASH_AM160B;
+		    info->sector_count = 35;
+		    info->size = 0x00400000;
+		    info->chipwidth=1;
+		    break;				/* => 4 MB	*/
+#if 0	/* enable when device IDs are available */
+	    case AMD_ID_LV320T:
+		    info->flash_id += FLASH_AM320T;
+		    info->sector_count = 67;
+		    info->size = 0x00800000;
+		    break;				/* => 8 MB	*/
+
+	    case AMD_ID_LV320B:
+		    info->flash_id += FLASH_AM320B;
+		    info->sector_count = 67;
+		    info->size = 0x00800000;
+		    break;				/* => 8 MB	*/
+#endif
+	    case AMD_ID_LV040B:
+		    info->flash_id += FLASH_AM040;
+		    info->sector_count = 8;
+		    info->size = 0x80000;
+		    info->chipwidth=1;
+		    break;
+
+	    case INTEL_ID_28F640J3A:
+		    info->flash_id += FLASH_28F640J3A;
+		    info->sector_count = 64;
+		    info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */
+		    info->chipwidth=2;
+		    if(portwidth==4) info->size*=2;	/* 2x16 */
+		    break;
+
+	    case INTEL_ID_28F128J3A:
+		    info->flash_id += FLASH_28F128J3A;
+		    info->sector_count = 128;
+		    info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */
+		    info->chipwidth=2;
+		    if(portwidth==4) info->size*=2;	/* 2x16 */
+		    break;
+
+	    default:
+		    printf("Unknown id %lx:[%lx]\n", manu, id);
+		    info->flash_id = FLASH_UNKNOWN;
+		    info->chipwidth=1;
+		    return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets(base, info);
+
+#if 0
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_AM040) {
+		/* this chip has uniformly spaced sectors */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0)=0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		saddr = (volatile unsigned short *)(info->start[i]);
+		laddr = (volatile unsigned long *)(info->start[i]);
+		if(portwidth==1)
+		    info->protect[i] = caddr[2] & 1;
+		else if(portwidth==2)
+		    info->protect[i] = saddr[2] & 1;
+		else
+		    info->protect[i] = laddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (volatile unsigned char *)info->start[0];
+
+		flash_cmd(portwidth,caddr,0,0xF0);	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+/* TODO: 2x16 unsupported */
+int
+flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (uchar *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	/* TODO: 2x16 unsupported */
+	if(info->portwidth==4) return 1;
+
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+	    for (sect = s_first; sect<=s_last; sect++) {
+		int sector_size=info->size/info->sector_count;
+		addr = (uchar *)(info->start[sect]);
+		memset((void *)addr, 0, sector_size);
+	    }
+	    return 0;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL)  {
+		return flash_erase_intel(info,
+				(unsigned short)s_first,
+				(unsigned short)s_last);
+	}
+
+#if 0
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+#endif
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_cmd(info->portwidth,addr,0x555,0xAA);
+	flash_cmd(info->portwidth,addr,0x2AA,0x55);
+	flash_cmd(info->portwidth,addr,0x555,0x80);
+	flash_cmd(info->portwidth,addr,0x555,0xAA);
+	flash_cmd(info->portwidth,addr,0x2AA,0x55);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (uchar *)(info->start[sect]);
+			flash_cmd(info->portwidth,addr,0,0x30);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+	/* broken for 2x16: TODO */
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+	flash_cmd(info->portwidth,addr,0,0xf0);
+	flash_cmd(info->portwidth,addr,0,0xf0);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+/* broken for 2x16: TODO */
+int
+write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if(info->portwidth==4) return 1;
+
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0;
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+	    memcpy((void *)addr, src, cnt);
+	    return 0;
+	}
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+/* broken for 2x16: TODO */
+static int
+write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (uchar *)(info->start[0]);
+	ulong start;
+	int flag, i;
+
+	if(info->portwidth==4) return 1;
+
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+	    *(unsigned long *)dest=data;
+	    return 0;
+	}
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)  {
+		unsigned short low = data & 0xffff;
+		unsigned short hi  = (data >> 16) & 0xffff;
+		int ret = write_word_intel((bank_addr_t)dest, hi);
+
+		if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low);
+
+		return ret;
+	}
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	addr[0x555] = 0xAA;
+	addr[0x2AA] = 0x55;
+	addr[0x555] = 0x20;
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		addr[0] = 0xA0;
+		*(((char *)dest)+i) = data_ch[i];
+		udelay(10); /* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	addr[0] = 0x90;
+	addr[0] = 0x00;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/evb64260/i2c.c b/u-boot/board/evb64260/i2c.c
new file mode 100644
index 0000000..c62b647
--- /dev/null
+++ b/u-boot/board/evb64260/i2c.c
@@ -0,0 +1,315 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000  /* Should be at least the # of MHz of Tclk */
+#undef	DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void
+i2c_init(int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualFreq, actualN=0, actualM=0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = 125000000;
+
+	DP(puts("i2c_init\n"));
+
+	for(n = 0 ; n < 8 ; n++)
+	{
+		for(m = 0 ; m < 16 ; m++)
+		{
+			power = 2<<n; /* power = 2^(n+1) */
+			freq = tclk/(10*(m+1)*power);
+			if (speed > freq)
+				margin = speed - freq;
+			else
+				margin = freq - speed;
+			if(margin < minMargin)
+			{
+				minMargin   = margin;
+				actualFreq  = freq;
+				actualN	    = n;
+				actualM	    = m;
+			}
+		}
+	}
+
+	DP(puts("setup i2c bus\n"));
+
+	/* Setup bus */
+
+	GT_REG_WRITE(I2C_SOFT_RESET, 0);
+
+	DP(puts("udelay...\n"));
+
+	udelay(I2C_DELAY);
+
+	DP(puts("set baudrate\n"));
+
+	GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+
+	udelay(I2C_DELAY * 10);
+
+	DP(puts("read control, baudrate\n"));
+
+	GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+	GT_REG_READ(I2C_CONTROL, &control);
+}
+
+static uchar
+i2c_start(void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP(puts("i2c_start\n"));
+
+	/* Set the start bit */
+
+	GT_REG_READ(I2C_CONTROL, &control);
+	control |= (0x1 << 5);
+	GT_REG_WRITE(I2C_CONTROL, control);
+
+	GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+
+	count = 0;
+	while ((status & 0xff) != 0x08) {
+		udelay(I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+			return (status);
+		}
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar
+i2c_select_device(uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP(puts("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS(I2C_CONTROL, BIT3);
+
+	udelay(I2C_DELAY);
+
+	GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		udelay(I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+			return(status);
+		}
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar
+i2c_get_data(uchar* return_data, int len) {
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP(puts("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
+
+		udelay(I2C_DELAY * 5);
+
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			udelay(I2C_DELAY);
+			if(count > 2) {
+				GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+				return 0;
+			}
+			GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ(I2C_DATA, &data);
+		len--;
+		*return_data = (uchar)data;
+		return_data++;
+	}
+	RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3);
+	while ((status & 0xff) != 0x58) {
+		udelay(I2C_DELAY);
+		if(count > 200) {
+			GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+			return (status);
+		}
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */
+
+	return (0);
+}
+
+static uchar
+i2c_write_data(unsigned int data, int len)
+{
+	unsigned int status;
+	int count = 0;
+
+	DP(puts("i2c_write_data\n"));
+
+	if (len > 4)
+		return -1;
+
+	while (len) {
+		/* Set and assert the data */
+
+		GT_REG_WRITE(I2C_DATA, (unsigned int)data);
+		RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
+
+		udelay(I2C_DELAY);
+
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay(I2C_DELAY);
+			if(count > 20) {
+				GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+				return (status);
+			}
+			GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+	}
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4));
+
+	udelay(I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit)
+{
+	uchar status;
+
+	DP(puts("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device(dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Failed to select device setting offset: 0x%02x\n",
+		       status);
+#endif
+		return status;
+	}
+
+	status = i2c_write_data(offset, 1);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Failed to write data: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return (0);
+}
+
+uchar
+i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data,
+	 int ten_bit)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = 400000;
+
+	DP(puts("i2c_read\n"));
+
+	i2c_init(i2cFreq,0);
+
+	status = i2c_start();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset(dev_addr, 0, 0);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Failed to set offset: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	i2c_init(i2cFreq,0);
+
+	status = i2c_start();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device(dev_addr, 1, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data(data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/evb64260/i2c.h b/u-boot/board/evb64260/i2c.h
new file mode 100644
index 0000000..9c21992
--- /dev/null
+++ b/u-boot/board/evb64260/i2c.h
@@ -0,0 +1,7 @@
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/u-boot/board/evb64260/intel_flash.c b/u-boot/board/evb64260/intel_flash.c
new file mode 100644
index 0000000..994264a
--- /dev/null
+++ b/u-boot/board/evb64260/intel_flash.c
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <galileo/gt64260R.h>
+#include <galileo/memory.h>
+#include "intel_flash.h"
+
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+static void
+bank_reset(flash_info_t *info, int sect)
+{
+	bank_addr_t addrw, eaddrw;
+
+	addrw = (bank_addr_t)info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD(addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = BANK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void
+bank_erase_init(flash_info_t *info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
+	printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
+	printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
+	printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
+	printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
+	printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
+	printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
+#endif
+
+	saddrw = (bank_addr_t)info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
+
+#ifdef FLASH_DEBUG
+	printf("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long)saddrw, (unsigned long)eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = BANK_CMD_ERASE1;
+		*addrw = BANK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+}
+
+static int
+bank_erase_poll(flash_info_t *info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (bank_addr_t)info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		bank_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf("  checking status at addr "
+			"0x%08x [0x%08x]\n",
+			(unsigned long)addrw, stat);
+#endif
+		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & BANK_STAT_ERR) != 0) {
+			printf(" failed on sector %d "
+				"(stat = 0x%08x) at "
+				"address 0x%p\n",
+				sect, stat, addrw);
+			*addrw = BANK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+int
+write_word_intel(bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong)stat, (ulong)addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase_intel(flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+
+#ifdef FLASH_DEBUG
+	printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info(info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sector%s will not be erased!\n",
+			prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init(info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer(start);
+
+			do {
+				now = get_timer(start);
+
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) { /* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll(info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset(info, sect);
+		}
+	}
+	return haderr;
+}
diff --git a/u-boot/board/evb64260/intel_flash.h b/u-boot/board/evb64260/intel_flash.h
new file mode 100644
index 0000000..cc3a339
--- /dev/null
+++ b/u-boot/board/evb64260/intel_flash.h
@@ -0,0 +1,160 @@
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
+#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
+#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
+#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST		0xFF		/* reset flash */
+#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
+#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define CHIP_CMD_PROG		0x40		/* program word command */
+#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
+#define CHIP_STAT_VPPS		0x08		/* VPP Status */
+#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
+#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
+#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS		128
+#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
+#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS		CHIP_NBLOCKS
+#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS		1		/* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o)	((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/u-boot/board/evb64260/local.h b/u-boot/board/evb64260/local.h
new file mode 100644
index 0000000..8a3f4b2
--- /dev/null
+++ b/u-boot/board/evb64260/local.h
@@ -0,0 +1,62 @@
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells U-Boot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! U-Boot figures this out  based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+			/* Note: If you defined CONFIG_EVB64260_750CX this */
+			/* gets defined automatically. */
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CONFIG_SYS_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY  */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+#define CONFIG_ETHADDR          00:11:22:33:44:55
+
+/* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:11:22:33:44:66
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		00:11:22:33:44:77
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
diff --git a/u-boot/board/evb64260/memory.c b/u-boot/board/evb64260/memory.c
new file mode 100644
index 0000000..e339854
--- /dev/null
+++ b/u-boot/board/evb64260/memory.c
@@ -0,0 +1,457 @@
+/* Memory.c - Memory mappings and remapping functions */
+
+/* Copyright - Galileo technology. */
+
+/* modified by Josh Huber to clean some things up, and
+ * fit it into the U-Boot framework */
+
+#include <galileo/core.h>
+#include <galileo/memory.h>
+
+/********************************************************************
+* memoryGetBankBaseAddress - Gets the base address of a memory bank
+*      - If the memory bank size is 0 then this base address has no meaning!!!
+*
+*
+* INPUTS:   MEMORY_BANK bank - The bank we ask for its base Address.
+* OUTPUT:   N/A
+* RETURNS: Memory bank base address.
+*********************************************************************/
+static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank)
+{
+    switch (bank)
+    {
+	case BANK0:
+	    return SCS_0_LOW_DECODE_ADDRESS;
+	case BANK1:
+	    return SCS_1_LOW_DECODE_ADDRESS;
+	case BANK2:
+	    return SCS_2_LOW_DECODE_ADDRESS;
+	case BANK3:
+	    return SCS_3_LOW_DECODE_ADDRESS;
+    }
+    return SCS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank)
+{
+    unsigned int base;
+    unsigned int regOffset=memoryGetBankRegOffset(bank);
+
+    GT_REG_READ(regOffset,&base);
+    base = base << 20;
+    return base;
+}
+
+/********************************************************************
+* memoryGetDeviceBaseAddress - Gets the base address of a device.
+*           - If the device size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   DEVICE device - The device we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: Device base address.
+*********************************************************************/
+static unsigned int memoryGetDeviceRegOffset(DEVICE device)
+{
+    switch (device)
+    {
+	case DEVICE0:
+	    return CS_0_LOW_DECODE_ADDRESS;
+	case DEVICE1:
+	    return CS_1_LOW_DECODE_ADDRESS;
+	case DEVICE2:
+	    return CS_2_LOW_DECODE_ADDRESS;
+	case DEVICE3:
+	    return CS_3_LOW_DECODE_ADDRESS;
+	case BOOT_DEVICE:
+	    return BOOTCS_LOW_DECODE_ADDRESS;
+    }
+    return CS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetDeviceBaseAddress(DEVICE device)
+{
+    unsigned int regBase;
+    unsigned int regEnd;
+    unsigned int regOffset=memoryGetDeviceRegOffset(device);
+
+    GT_REG_READ(regOffset, &regBase);
+    GT_REG_READ(regOffset+8, &regEnd);
+
+    if(regEnd<=regBase) return 0xffffffff;	/* ERROR !!! */
+
+    regBase = regBase << 20;
+    return regBase;
+}
+
+/********************************************************************
+* memoryGetBankSize - Returns the size of a memory bank.
+*
+*
+* INPUT:    MEMORY_BANK bank - The bank we ask for its size.
+* OUTPUT:   N/A
+* RETURNS: Memory bank size.
+*********************************************************************/
+unsigned int memoryGetBankSize(MEMORY_BANK bank)
+{
+    unsigned int size,base;
+    unsigned int highValue;
+    unsigned int highAddress=memoryGetBankRegOffset(bank)+8;
+
+    base = memoryGetBankBaseAddress(bank);
+    GT_REG_READ(highAddress,&highValue);
+    highValue = (highValue + 1) << 20;
+    if(base > highValue)
+	size=0;
+    else
+	size = highValue - base;
+    return size;
+}
+
+/********************************************************************
+* memoryGetDeviceSize - Returns the size of a device memory space
+*
+*
+* INPUT:    DEVICE device - The device we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS:  Size of a device memory space.
+*********************************************************************/
+unsigned int memoryGetDeviceSize(DEVICE device)
+{
+    unsigned int size,base;
+    unsigned int highValue;
+    unsigned int highAddress=memoryGetDeviceRegOffset(device)+8;
+
+    base = memoryGetDeviceBaseAddress(device);
+    GT_REG_READ(highAddress,&highValue);
+    if (highValue == 0xfff)
+    {
+	size = (~base) + 1;	/* what the heck is this? */
+	return size;
+    }
+    else
+	highValue = (highValue + 1) << 20;
+
+    if(base > highValue)
+	size=0;
+    else
+	size = highValue - base;
+    return size;
+}
+
+/********************************************************************
+* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width.
+*                  The width is determine in registers: 'Device Parameters'
+*                  registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device.
+*                  at bits: [21:20].
+*
+* INPUT:    DEVICE device - Device number
+* OUTPUT:   N/A
+* RETURNS:  Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
+*********************************************************************/
+unsigned int memoryGetDeviceWidth(DEVICE device)
+{
+    unsigned int width;
+    unsigned int regValue;
+
+    GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,&regValue);
+    width =  (regValue & 0x00300000) >> 20;
+    switch (width)
+    {
+	case 0:
+	    return 1;
+	case 1:
+	    return 2;
+	case 2:
+	    return 4;
+	case 3:
+	    return 8;
+	default:
+	    return 0;
+    }
+}
+
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength)
+{
+    unsigned int low=0xfff;
+    unsigned int high=0x0;
+    unsigned int regOffset=memoryGetBankRegOffset(bank);
+
+    if(bankLength!=0) {
+	low = (bankBase >> 20) & 0xffff;
+	high=((bankBase+bankLength)>>20)-1;
+    }
+
+#ifdef DEBUG
+    {
+	unsigned int oldLow, oldHigh;
+	GT_REG_READ(regOffset,&oldLow);
+	GT_REG_READ(regOffset+8,&oldHigh);
+
+	printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high);
+    }
+#endif
+
+    GT_REG_WRITE(regOffset,low);
+    GT_REG_WRITE(regOffset+8,high);
+
+    return true;
+}
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength)
+{
+    /* TODO: what are appropriate "unmapped" values? */
+    unsigned int low=0xfff;
+    unsigned int high=0x0;
+    unsigned int regOffset=memoryGetDeviceRegOffset(device);
+
+    if(deviceLength != 0) {
+	low=deviceBase>>20;
+	high=((deviceBase+deviceLength)>>20)-1;
+    } else {
+	/* big problems in here... */
+	/* this will HANG */
+    }
+
+    GT_REG_WRITE(regOffset,low);
+    GT_REG_WRITE(regOffset+8,high);
+
+    return true;
+}
+
+
+/********************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internals
+*                                   registers.
+*
+* INPUTS:  unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase)
+{
+    unsigned int currentValue;
+    unsigned int internalValue = internalRegBase;
+
+    internalRegBase = (internalRegBase >> 20);
+    GT_REG_READ(INTERNAL_SPACE_DECODE,&currentValue);
+    internalRegBase = (currentValue & 0xffff0000) | internalRegBase;
+    GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase);
+    INTERNAL_REG_BASE_ADDR = internalValue;
+    return true;
+}
+
+/********************************************************************
+* memoryGetInternalRegistersSpace - Gets internal registers Base Address.
+*
+* INPUTS:  unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+unsigned int memoryGetInternalRegistersSpace(void)
+{
+    return INTERNAL_REG_BASE_ADDR;
+}
+
+/********************************************************************
+* memorySetProtectRegion - This function modifys one of the 8 regions with
+*                          one of the three protection mode.
+*                        - Be advised to check the spec before modifying them.
+*
+*
+* Inputs: CPU_PROTECT_REGION - one of the eight regions.
+*         CPU_ACCESS - general access.
+*         CPU_WRITE - read only access.
+*         CPU_CACHE_PROTECT - chache access.
+*      we defining CPU because there is another protect from the pci SIDE.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memAccess,
+			    MEMORY_ACCESS_WRITE memWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+    unsigned int protectHigh = baseAddress + regionLength;
+
+    if(regionLength == 0) /* closing the region */
+    {
+	GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff);
+	GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0);
+	return true;
+    }
+    baseAddress =  (baseAddress & 0xfff00000) >> 20;
+    baseAddress = baseAddress | memAccess << 16 |  memWrite << 17
+		     | cacheProtection << 18;
+    GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress);
+    protectHigh = (protectHigh & 0xfff00000) >> 20;
+    GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1);
+    return true;
+}
+
+/********************************************************************
+* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
+*                            supports Cache Coherency.
+*
+*
+* Inputs: SNOOP_REGION region - One of the four regions.
+*         SNOOP_TYPE snoopType - There is four optional Types:
+*                               1. No Snoop.
+*                               2. Snoop to WT region.
+*                               3. Snoop to WB region.
+*                               4. Snoop & Invalidate to WB region.
+*         unsigned int baseAddress - Base Address of this region.
+*         unsigned int topAddress - Top Address of this region.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength)
+{
+    unsigned int snoopXbaseAddress;
+    unsigned int snoopXtopAddress;
+    unsigned int data;
+    unsigned int snoopHigh = baseAddress + regionLength;
+
+    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
+	return false;
+    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
+    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
+    if(regionLength == 0) /* closing the region */
+    {
+	GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
+	GT_REG_WRITE(snoopXtopAddress,0);
+	return true;
+    }
+    baseAddress = baseAddress & 0xffff0000;
+    data = (baseAddress >> 16) | snoopType << 16;
+    GT_REG_WRITE(snoopXbaseAddress,data);
+    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
+    return true;
+}
+
+/********************************************************************
+* memoryRemapAddress - This fubction used for address remapping.
+*
+*
+* Inputs: regOffset: remap register
+*         remapValue :
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue)
+{
+    unsigned int valueForReg;
+    valueForReg = (remapValue & 0xfff00000) >> 20;
+    GT_REG_WRITE(remapReg, valueForReg);
+    return true;
+}
+
+/********************************************************************
+* memoryGetDeviceParam - This function used for getting device parameters from
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
+{
+    unsigned int valueOfReg;
+    unsigned int calcData;
+
+    GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
+    calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19);
+    deviceParam -> turnOff = calcData;          /* Turn Off */
+
+    calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19);
+    deviceParam -> acc2First = calcData;        /* Access To First */
+
+    calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20);
+    deviceParam -> acc2Next = calcData;         /* Access To Next */
+
+    calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22);
+    deviceParam -> ale2Wr = calcData;           /* Ale To Write */
+
+    calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23);
+    deviceParam -> wrLow = calcData;            /* Write Active */
+
+    calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24);
+    deviceParam -> wrHigh = calcData;           /* Write High */
+
+    calcData = ((0x300000 & valueOfReg) >> 20);
+    switch (calcData)
+    {
+    case 0:
+	deviceParam -> deviceWidth = 1;         /* one Byte - 8-bit */
+	break;
+    case 1:
+	deviceParam -> deviceWidth = 2;         /* two Bytes - 16-bit */
+	break;
+    case 2:
+	deviceParam -> deviceWidth = 4;         /* four Bytes - 32-bit */
+	break;
+    case 3:
+	deviceParam -> deviceWidth = 8;         /* eight Bytes - 64-bit */
+	break;
+    default:
+	deviceParam -> deviceWidth = 1;
+	break;
+    }
+    return true;
+}
+
+/********************************************************************
+* memorySetDeviceParam - This function used for setting device parameters to
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
+{
+    unsigned int valueForReg;
+
+    if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) ||
+       (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) ||
+	(deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf))
+	return false;
+    valueForReg = (((deviceParam -> turnOff) & 0x7) |
+		   (((deviceParam -> turnOff) & 0x8) << 19) |
+		   (((deviceParam -> acc2First) & 0xf) << 3) |
+		   (((deviceParam -> acc2First) & 0x10) << 19) |
+		   (((deviceParam -> acc2Next) & 0xf) << 7) |
+		   (((deviceParam -> acc2Next) & 0x10) << 20) |
+		   (((deviceParam -> ale2Wr) & 0x7) << 11) |
+		   (((deviceParam -> ale2Wr) & 0xf) << 22) |
+		   (((deviceParam -> wrLow) & 0x7) << 14) |
+		   (((deviceParam -> wrLow) & 0xf) << 23) |
+		   (((deviceParam -> wrHigh) & 0x7) << 17) |
+		   (((deviceParam -> wrHigh) & 0xf) << 24));
+    /* insert the device width: */
+    switch(deviceParam->deviceWidth)
+    {
+    case 1:
+	valueForReg = valueForReg | _8BIT;
+	break;
+    case 2:
+	valueForReg = valueForReg | _16BIT;
+	break;
+    case 4:
+	valueForReg = valueForReg | _32BIT;
+	break;
+    case 8:
+	valueForReg = valueForReg | _64BIT;
+	break;
+    default:
+	valueForReg = valueForReg | _8BIT;
+	break;
+    }
+    GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
+    return true;
+}
diff --git a/u-boot/board/evb64260/misc.S b/u-boot/board/evb64260/misc.S
new file mode 100644
index 0000000..f09528d
--- /dev/null
+++ b/u-boot/board/evb64260/misc.S
@@ -0,0 +1,182 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include <galileo/gt64260R.h>
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CONFIG_SYS_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11:	gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	rlwinm	r7, r4, 12, 16, 31
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0
+led_on0:
+	xor     r18, r18, r18
+	lis     r18, 0x1c80
+	ori     r18, r18, 0x8000
+	stw     r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor     r18, r18, r18
+	lis     r18, 0x1c80
+	ori     r18, r18, 0xc000
+	stw     r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor     r18, r18, r18
+	lis     r18, 0x1c81
+	ori     r18, r18, 0x0000
+	stw     r18, 0x0(r18)
+	sync
+	blr
diff --git a/u-boot/board/evb64260/mpsc.c b/u-boot/board/evb64260/mpsc.c
new file mode 100644
index 0000000..f3dc20b
--- /dev/null
+++ b/u-boot/board/evb64260/mpsc.c
@@ -0,0 +1,854 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int (*mpsc_putchar)(char ch) = mpsc_putchar_early;
+
+static volatile unsigned int *rx_desc_base=NULL;
+static unsigned int rx_desc_index=0;
+static volatile unsigned int *tx_desc_base=NULL;
+static unsigned int tx_desc_index=0;
+
+/* local function declarations */
+static int galmpsc_connect(int channel, int connect);
+static int galmpsc_route_serial(int channel, int connect);
+static int galmpsc_route_rx_clock(int channel, int brg);
+static int galmpsc_route_tx_clock(int channel, int brg);
+static int galmpsc_write_config_regs(int mpsc, int mode);
+static int galmpsc_config_channel_regs(int mpsc);
+static int galmpsc_set_char_length(int mpsc, int value);
+static int galmpsc_set_stop_bit_length(int mpsc, int value);
+static int galmpsc_set_parity(int mpsc, int value);
+static int galmpsc_enter_hunt(int mpsc);
+static int galmpsc_set_brkcnt(int mpsc, int value);
+static int galmpsc_set_tcschar(int mpsc, int value);
+static int galmpsc_set_snoop(int mpsc, int value);
+static int galmpsc_shutdown(int mpsc);
+
+static int galsdma_set_RFT(int channel);
+static int galsdma_set_SFM(int channel);
+static int galsdma_set_rxle(int channel);
+static int galsdma_set_txle(int channel);
+static int galsdma_set_burstsize(int channel, unsigned int value);
+static int galsdma_set_RC(int channel, unsigned int value);
+
+static int galbrg_set_CDV(int channel, int value);
+static int galbrg_enable(int channel);
+static int galbrg_disable(int channel);
+static int galbrg_set_clksrc(int channel, int value);
+static int galbrg_set_CUV(int channel, int value);
+
+static void galsdma_enable_rx(void);
+
+/* static int galbrg_reset(int channel); */
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+
+/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack[0]))
+
+#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
+#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
+
+#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
+#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
+
+/* make sure this isn't bigger than 16 long words (u-boot.h) */
+struct _tag_mirror_hack {
+    unsigned GALMPSC_PROTOCONF_REG_M[2];	/* 8008 */
+    unsigned GALMPSC_CHANNELREG_1_M[2];		/* 800c */
+    unsigned GALMPSC_CHANNELREG_2_M[2];		/* 8010 */
+    unsigned GALBRG_0_CONFREG_M[2];		/* b200 */
+
+    unsigned GALMPSC_ROUTING_REGISTER_M;	/* b400 */
+    unsigned GALMPSC_RxC_ROUTE_M;		/* b404 */
+    unsigned GALMPSC_TxC_ROUTE_M;		/* b408 */
+
+    unsigned int baudrate;			/* current baudrate, for tsc delay calc */
+};
+
+/* static struct _tag_mirror_hack *mh = NULL;   */
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int
+mpsc_putchar_early(char ch)
+{
+	int mpsc=CHANNEL;
+	int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	galmpsc_set_tcschar(mpsc,ch);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int
+mpsc_putchar_sdma(char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset((void *)p, 0, 8 * sizeof(unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;						/* x */
+	p[5] = (unsigned int)ch;				/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;					/* 0 */
+	p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;		/* 4 */
+	p[2] = 0;						/* 8 */
+	p[3] = (unsigned int)&p[4];				/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int)&p[0];
+	p[11] = (unsigned int)&p[12];
+#endif
+
+	FLUSH_DCACHE(&p[0], &p[8]);
+
+	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+		     (unsigned int)&p[0]);
+	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+		     (unsigned int)&p[0]);
+
+	temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE(&p[1], &p[2]);
+
+	while(p[1] & DESC_OWNER) {
+	    udelay(100);
+	    INVALIDATE_DCACHE(&p[1], &p[2]);
+	}
+
+	return 0;
+}
+
+char mpsc_getchar (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2,
+						 CHANNEL, GALMPSC_REG_GAP);
+			temp |= (1 << 23);
+			GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL,
+					     GALMPSC_REG_GAP, temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+int
+mpsc_test_char(void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index*8];
+
+	INVALIDATE_DCACHE(&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER) return 0;
+	else return 1;
+}
+
+int
+mpsc_init(int baud)
+{
+	memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
+	MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
+
+	/* BRG CONFIG */
+	galbrg_set_baudrate(CHANNEL, baud);
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+	galbrg_set_clksrc(CHANNEL,0x8);	/* connect TCLK -> BRG */
+#else
+	galbrg_set_clksrc(CHANNEL,0);
+#endif
+	galbrg_set_CUV(CHANNEL, 0);
+	galbrg_enable(CHANNEL);
+
+	/* Set up clock routing */
+	galmpsc_connect(CHANNEL, GALMPSC_CONNECT);
+	galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT);
+	galmpsc_route_rx_clock(CHANNEL, CHANNEL);
+	galmpsc_route_tx_clock(CHANNEL, CHANNEL);
+
+	/* reset MPSC state */
+	galmpsc_shutdown(CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle(CHANNEL);
+	galsdma_set_rxle(CHANNEL);
+	galsdma_set_RC(CHANNEL, 0xf);
+	galsdma_set_SFM(CHANNEL);
+	galsdma_set_RFT(CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs(CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs(CHANNEL);
+	galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8);       /* 8 */
+	galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE);              /* N */
+	galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1);     /* 1 */
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop(CHANNEL, 0);				/* disable snoop */
+#else
+	galmpsc_set_snoop(CHANNEL, 1);				/* enable snoop */
+#endif
+
+	return 0;
+}
+
+void
+mpsc_init2(void)
+{
+	int i;
+
+	mpsc_putchar = mpsc_putchar_sdma;
+
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) *
+		sizeof(unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int)rx_desc_base+32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */
+		rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */
+		rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST;  /* Command & control */
+		rx_desc_base[i*8] = 0x00100000;
+	}
+	rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0];
+
+	FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]);
+	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+		     (unsigned int)&rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) *
+		sizeof(unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int)tx_desc_base+32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i*8 + 5] = (unsigned int)0x23232323;
+		tx_desc_base[i*8 + 4] = (unsigned int)0x23232323;
+		tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4];
+		tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8];
+		tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i*8] = 0x00010001;
+	}
+	tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0];
+
+	FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]);
+
+	udelay(100);
+
+	galsdma_enable_rx();
+
+	return;
+}
+
+int
+galbrg_set_baudrate(int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable(channel);
+
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+	/* from tclk */
+	clock = (CONFIG_SYS_BUS_CLK/(16*rate)) - 1;
+#else
+	clock = (3686400/(16*rate)) - 1;
+#endif
+
+	galbrg_set_CDV(channel, clock);
+
+	galbrg_enable(channel);
+
+	MIRROR_HACK->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int
+galbrg_set_CDV(int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galbrg_enable(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+	temp |= 0x00010000;
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galbrg_disable(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galbrg_set_clksrc(int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
+	temp &= 0xFF83FFFF;
+	temp |= (value << 18);
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galbrg_set_CUV(int channel, int value)
+{
+	GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int
+galbrg_reset(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int
+galsdma_set_RFT(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_SFM(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_rxle(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_txle(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_RC(int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_burstsize(int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	 case 8:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x3 << 12)));
+		break;
+
+	 case 4:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x2 << 12)));
+		break;
+
+	 case 2:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x1 << 12)));
+		break;
+
+	 case 1:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x0 << 12)));
+		break;
+
+	 default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int
+galmpsc_connect(int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_route_serial(int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX);
+
+	if ((channel == 0) && connect)
+		temp |= 0x00000100;
+	else if ((channel == 1) && connect)
+		temp |= 0x00001000;
+	else if ((channel == 0) && !connect)
+		temp &= ~0x00000100;
+	else
+		temp &= ~0x00001000;
+
+	GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_route_rx_clock(int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
+
+	if (channel == 0)
+		temp |= brg;
+	else
+		temp |= (brg << 8);
+
+	GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_route_tx_clock(int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
+
+	if (channel == 0)
+		temp |= brg;
+	else
+		temp |= (brg << 8);
+
+	GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_write_config_regs(int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP),
+			     0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP),
+			     0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int
+galmpsc_config_channel_regs(int mpsc)
+{
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt(mpsc, 0x3);
+	galmpsc_set_tcschar(mpsc, 0xab);
+
+	return 0;
+}
+
+static int
+galmpsc_set_brkcnt(int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_tcschar(int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_char_length(int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_stop_bit_length(int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
+	temp |= (value << 14);
+	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_parity(int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_enter_hunt(int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	temp |= 0x80000000;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
+
+	/* Should Poll on Enter Hunt bit, but the register is write-only */
+	/* errata suggests pausing 100 system cycles */
+	udelay(100);
+
+	return 0;
+}
+
+
+static int
+galmpsc_shutdown(int mpsc)
+{
+#if 0
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp);
+#endif
+
+	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
+	             SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0);
+
+	udelay(100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
+	             0x000000fc);
+
+	udelay(100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+
+	udelay(100);
+
+	return 0;
+}
+
+static void
+galsdma_enable_rx(void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt(CHANNEL);
+}
+
+static int
+galmpsc_set_snoop(int mpsc, int value)
+{
+	int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp=GTREGREAD(reg);
+	if(value)
+	    temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
+	else
+	    temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
+	GT_REG_WRITE(reg, temp);
+	return 0;
+}
diff --git a/u-boot/board/evb64260/mpsc.h b/u-boot/board/evb64260/mpsc.h
new file mode 100644
index 0000000..c71258c
--- /dev/null
+++ b/u-boot/board/evb64260/mpsc.h
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include <galileo/gt64260R.h>
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_init2(void);
+char mpsc_getchar(void);
+int mpsc_test_char(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+extern int (*mpsc_putchar)(char ch);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/u-boot/board/evb64260/pci.c b/u-boot/board/evb64260/pci.c
new file mode 100644
index 0000000..582f24c
--- /dev/null
+++ b/u-boot/board/evb64260/pci.c
@@ -0,0 +1,760 @@
+/* PCI.c - PCI functions */
+
+/* Copyright - Galileo technology. */
+
+#include <common.h>
+#include <pci.h>
+
+#include <galileo/pci.h>
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+#ifdef CONFIG_ZUMA_V2
+	{0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0},
+	{0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0}
+#else				/* EVB??? This is a guess */
+	{0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0},
+	{0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0}
+#endif
+};
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static unsigned int local_buses[] = { 0, 0 };
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = PCI_BUS (pciDevNum);
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = PCI_BUS (pciDevNum);
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_WRITE (pci_configuration_data[host], data);
+	} else {		/* configuration Transaction over the pci. */
+
+		/* The PCI is working in LE Mode So it swap the Data. */
+		GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));
+	}
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_READ (pci_configuration_data[host], &data);
+		return data;
+	} else {		/* The PCI is working in LE Mode So it swap the Data. */
+
+		GT_REG_READ (pci_configuration_data[host], &data);
+		return WORD_SWAP (data);
+	}
+}
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 20) & 0xfff;
+		high = ((bankBase + bankLength) >> 20) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 20);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xfff) << 20;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	high &= 0xfff;
+	low &= 0xfff;
+	if (high <= low)
+		return 0;
+	return (high + 1 - low) << 20;
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + 4 * bank,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+}
+
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+/*
+ *
+ */
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), value,
+					     bus);
+	}
+	return 0;
+}
+
+/*
+ *
+ */
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+#ifndef CONFIG_P3G4
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
+	fixup_irq:gt_fixup_irq,
+#endif
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
+	fixup_irq:gt_fixup_irq,
+#endif
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+
+#ifndef CONFIG_P3G4
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif
+
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci0_hose.current_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+#ifndef CONFIG_P3G4
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+}
diff --git a/u-boot/board/evb64260/sdram_init.c b/u-boot/board/evb64260/sdram_init.c
new file mode 100644
index 0000000..e2f0769
--- /dev/null
+++ b/u-boot/board/evb64260/sdram_init.c
@@ -0,0 +1,663 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <galileo/memory.h>
+#include <galileo/pci.h>
+#include <galileo/gt64260R.h>
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64260.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* #define	DEBUG */
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#define GB         (1 << 30)
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+	int size;		/* detected size, not from I2C but from dram_size() */
+} sdram_info_t;
+
+#ifdef DEBUG
+void dump_dimm_info (struct sdram_info *d)
+{
+	static const char *ecc_legend[] = { "", " Parity", " ECC" };
+
+	printf ("dimm%s %sDRAM: %dMibytes:\n",
+		ecc_legend[d->ecc],
+		d->registered ? "R" : "", (d->size >> 20));
+	printf ("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+		d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+		d->banks, d->slot);
+}
+#endif
+
+static int
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+	return 0;
+}
+
+#ifdef MAP_PCI
+static int
+memory_map_bank_pci (unsigned int bankNo,
+		     unsigned int bankBase, unsigned int bankLength)
+{
+	PCI_HOST host;
+
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+	return 0;
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+#ifdef CONFIG_ZUMA_V2
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+	/* assume 2 dimms, 2 banks each 256M - we dont have an
+	 * dimm i2c so rely on the detection routines later */
+
+	memset (info, 0, sizeof (*info));
+
+	info->slot = slot;
+	info->banks = 2;	/* Detect later */
+	info->registered = 0;
+	info->drb_size = 32;	/* 16 - 256MBit, 32 - 512MBit
+				   but doesn't matter, both do same
+				   thing in setup_sdram() */
+	info->tpar = 3;
+	info->tras_clocks = 5;
+	info->burst_len = 4;
+#ifdef CONFIG_ECC
+	info->ecc = 0;		/* Detect later */
+#endif /* CONFIG_ECC */
+	return 0;
+}
+
+#elif defined(CONFIG_P3G4)
+
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+	memset (info, 0, sizeof (*info));
+
+	if (slot)
+		return 0;
+
+	info->slot = slot;
+	info->banks = 1;
+	info->registered = 0;
+	info->drb_size = 4;
+	info->tpar = 3;
+	info->tras_clocks = 6;
+	info->burst_len = 4;
+#ifdef CONFIG_ECC
+	info->ecc = 2;
+#endif
+	return 0;
+}
+
+#else  /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
+	ulong tmemclk;
+	uchar trp_clocks, trcd_clocks;
+	uchar data[128];
+
+	get_clocks ();
+
+	tmemclk = 1000000000 / (gd->bus_clk / 100);	/* in 10 ps units */
+
+#ifdef CONFIG_EVB64260_750CX
+	if (0 != slot) {
+		printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
+		printf ("            called with slot=%d insetad!\n", slot);
+		return 0;
+	}
+#endif
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 128, data, 0);
+
+	DP (puts ("after i2c read\n"));
+
+	/* zero all the values */
+	memset (info, 0, sizeof (*info));
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	}
+
+	/* first, do some sanity checks */
+	if (data[2] != 0x4) {
+		printf ("Not SDRAM in slot %d\n", slot);
+		return 0;
+	}
+
+	/* get various information */
+	rows = data[3];
+	cols = data[4];
+	info->banks = data[5];
+	sdram_banks = data[17];
+	width = data[13] & 0x7f;
+
+	DP (printf
+	    ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
+
+	/* check if the memory is registered */
+	if (data[21] & (BIT1 | BIT4))
+		info->registered = 1;
+
+#ifdef CONFIG_ECC
+	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+	info->ecc = (data[11] & 2) >> 1;
+#endif
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (data[18] & 0x6) >> 1;
+
+	/* compute the relevant clock values */
+	trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
+	info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
+
+	DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
+		    trp_clocks, trcd_clocks, info->tras_clocks));
+
+	/* try a CAS latency of 3 first... */
+	cal_val = 0;
+	if (supp_cal & 3) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 3;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 2;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		return 0;
+	}
+
+	/* get the largest delay -- these values need to all be the same
+	 * see Res#6 */
+	info->tpar = cal_val;
+	if (trp_clocks > info->tpar)
+		info->tpar = trp_clocks;
+	if (trcd_clocks > info->tpar)
+		info->tpar = trcd_clocks;
+
+	DP (printf ("tpar set to: %d\n", info->tpar));
+
+#ifdef CONFIG_SYS_BROKEN_CL2
+	if (info->tpar == 2) {
+		info->tpar = 3;
+		DP (printf ("tpar fixed-up to: %d\n", info->tpar));
+	}
+#endif
+	/* compute the module DRB size */
+	info->drb_size =
+		(((1 << (rows + cols)) * sdram_banks) * width) / _16M;
+
+	DP (printf ("drb_size set to: %d\n", info->drb_size));
+
+	/* find the burst len */
+	info->burst_len = data[16] & 0xf;
+	if ((info->burst_len & 8) == 8) {
+		info->burst_len = 1;
+	} else if ((info->burst_len & 4) == 4) {
+		info->burst_len = 0;
+	} else {
+		return 0;
+	}
+
+	info->slot = slot;
+	return 0;
+}
+#endif /* ! CONFIG_ZUMA_V2 */
+
+static int setup_sdram_common (sdram_info_t info[2])
+{
+	ulong tmp;
+	int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
+
+	if (!info[0].banks && !info[1].banks)
+		return 0;
+
+	if (info[0].banks) {
+		if (info[0].tpar > tpar)
+			tpar = info[0].tpar;
+		if (info[0].tras_clocks > tras_clocks)
+			tras_clocks = info[0].tras_clocks;
+		if (!info[0].registered)
+			registered = 0;
+		if (info[0].ecc != 2)
+			ecc = 0;
+	}
+
+	if (info[1].banks) {
+		if (info[1].tpar > tpar)
+			tpar = info[1].tpar;
+		if (info[1].tras_clocks > tras_clocks)
+			tras_clocks = info[1].tras_clocks;
+		if (!info[1].registered)
+			registered = 0;
+		if (info[1].ecc != 2)
+			ecc = 0;
+	}
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIGURATION);
+
+	/* Turn on physical interleave if both DIMMs
+	 * have even numbers of banks. */
+	if ((info[0].banks == 0 || info[0].banks == 2) &&
+	    (info[1].banks == 0 || info[1].banks == 2)) {
+		/* physical interleave on */
+		tmp &= ~(1 << 15);
+	} else {
+		/* physical interleave off */
+		tmp |= (1 << 15);
+	}
+
+	tmp |= (registered << 17);
+
+	/* Use buffer 1 to return read data to the CPU
+	 * See Res #12 */
+	tmp |= (1 << 26);
+
+	GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
+	DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
+
+	/* SDRAM timing */
+	tmp = (((tpar == 3) ? 2 : 1) |
+	       (((tpar == 3) ? 2 : 1) << 2) |
+	       (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
+
+#ifdef CONFIG_ECC
+	/* Setup ECC */
+	if (ecc == 2)
+		tmp |= 1 << 13;
+#endif /* CONFIG_ECC */
+
+	GT_REG_WRITE (SDRAM_TIMING, tmp);
+	DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+		    GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
+
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
+	DP (printf ("SDRAM decode: %08x\n",
+		    GTREGREAD (SDRAM_ADDRESS_DECODE)));
+
+	return 0;
+}
+
+/* sets up the GT properly with information passed in */
+static int setup_sdram (sdram_info_t * info)
+{
+	ulong tmp, check;
+	ulong *addr = 0;
+	int i;
+
+	/* sanity checking */
+	if (!info->banks)
+		return 0;
+
+	/* ---------------------------- */
+	/* Program the GT with the discovered data */
+
+	/* bank parameters */
+	tmp = (0xf << 16);	/* leave all virt bank pages open */
+
+	DP (printf ("drb_size: %d\n", info->drb_size));
+	switch (info->drb_size) {
+	case 1:
+		tmp |= (1 << 14);
+		break;
+	case 4:
+	case 8:
+		tmp |= (2 << 14);
+		break;
+	case 16:
+	case 32:
+		tmp |= (3 << 14);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		return 1;
+	}
+
+	/* SDRAM bank parameters */
+	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
+	GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
+	GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
+	DP (printf
+	    ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
+	     info->slot * 2, (info->slot * 2) + 1, tmp));
+
+	/* set the SDRAM configuration for each bank */
+	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
+		DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+
+		/* set SDRAM mode */
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);
+
+		/* dummy write */
+		*addr = 0;
+
+		/* wait for the command to complete */
+		while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);
+
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+		DP (printf ("*** MRS cycle for bank %d done ***\n", i));
+	}
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* U-Boot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+phys_size_t initdram (int board_type)
+{
+	ulong checkbank[4] = {[0 ... 3] = 0 };
+	int bank_no;
+	ulong total;
+	int nhr;
+	sdram_info_t dimm_info[2];
+
+
+	/* first, use the SPD to get info about the SDRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0 () & (1 << 16);
+
+	if (nhr) {
+		printf ("Skipping SDRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		check_dimm (0, &dimm_info[0]);
+
+		/* DIMM1 */
+#ifndef CONFIG_EVB64260_750CX	/* EVB64260_750CX has only 1 DIMM */
+		check_dimm (1, &dimm_info[1]);
+#else  /* CONFIG_EVB64260_750CX */
+		memset (&dimm_info[1], 0, sizeof (sdram_info_t));
+#endif
+
+		/* unmap all banks */
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
+
+		/* Now, program the GT with the correct values */
+		if (setup_sdram_common (dimm_info)) {
+			printf ("Setup common failed.\n");
+		}
+
+		if (setup_sdram (&dimm_info[0])) {
+			printf ("Setup for DIMM1 failed.\n");
+		}
+
+		if (setup_sdram (&dimm_info[1])) {
+			printf ("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0 (get_hid0 () | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	total = 0;
+	if (dimm_info[0].banks > 0)
+		checkbank[0] = 1;
+	if (dimm_info[0].banks > 1)
+		checkbank[1] = 1;
+	if (dimm_info[0].banks > 2)
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+	if (dimm_info[1].banks > 0)
+		checkbank[2] = 1;
+	if (dimm_info[1].banks > 1)
+		checkbank[3] = 1;
+	if (dimm_info[1].banks > 2)
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+	/* Generic dram sizer: works even if we don't have i2c DIMMs,
+	 * as long as the timing settings are more or less correct */
+
+	/*
+	 * pass 1: size all the banks, using first bat (0-256M)
+	 *         limitation: we only support 256M per bank due to
+	 *         us only having 1 BAT for all DRAM
+	 */
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (!checkbank[bank_no])
+			continue;
+
+		DP (printf ("checking bank %d\n", bank_no));
+
+		memory_map_bank (bank_no, 0, GB / 4);
+		checkbank[bank_no] = dram_size (NULL, GB / 4);
+		memory_map_bank (bank_no, 0, 0);
+
+		DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
+	}
+
+	/*
+	 * pass 2: contiguously map each bank into physical address
+	 *         space.
+	 */
+	dimm_info[0].banks = dimm_info[1].banks = 0;
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+		if (!checkbank[bank_no])
+			continue;
+
+		dimm_info[bank_no / 2].banks++;
+		dimm_info[bank_no / 2].size += checkbank[bank_no];
+
+		memory_map_bank (bank_no, total, checkbank[bank_no]);
+#ifdef MAP_PCI
+		memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
+#endif
+		total += checkbank[bank_no];
+	}
+
+#ifdef CONFIG_ECC
+#ifdef CONFIG_ZUMA_V2
+	/*
+	 * We always enable ECC when bank 2 and 3 are unpopulated
+	 * If we 2 or 3 are populated, we CAN'T support ECC.
+	 * (Zuma boards only support ECC in banks 0 and 1; assume that
+	 * in that configuration, ECC chips are mounted, even for stacked
+	 * chips)
+	 */
+	if (checkbank[2] == 0 && checkbank[3] == 0) {
+		dimm_info[0].ecc = 2;
+		GT_REG_WRITE (SDRAM_TIMING,
+			      GTREGREAD (SDRAM_TIMING) | (1 << 13));
+		/* TODO: do we have to run MRS cycles again? */
+	}
+#endif /* CONFIG_ZUMA_V2 */
+
+	if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
+		puts ("[ECC] ");
+	}
+#endif /* CONFIG_ECC */
+
+#ifdef DEBUG
+	dump_dimm_info (&dimm_info[0]);
+	dump_dimm_info (&dimm_info[1]);
+#endif
+	/* TODO: return at MOST 256M? */
+	/* return total > GB/4 ? GB/4 : total; */
+	return total;
+}
diff --git a/u-boot/board/evb64260/serial.c b/u-boot/board/evb64260/serial.c
new file mode 100644
index 0000000..9d71115
--- /dev/null
+++ b/u-boot/board/evb64260/serial.c
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include <galileo/memory.h>
+
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+#include <ns16550.h>
+#endif
+
+#include "serial.h"
+
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
+				(NS16550_t) CONFIG_SYS_NS16550_COM2 };
+#endif
+
+#ifdef CONFIG_MPSC
+
+int serial_init (void)
+{
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+#endif
+
+	mpsc_init(gd->baudrate);
+
+	/* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CONFIG_SYS_INIT_CHAN1
+	NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+	return (0);
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		mpsc_putchar('\r');
+
+	mpsc_putchar(c);
+}
+
+int
+serial_getc(void)
+{
+	return mpsc_getchar();
+}
+
+int
+serial_tstc(void)
+{
+	return mpsc_test_char();
+}
+
+void
+serial_setbrg (void)
+{
+	galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else /* ! CONFIG_MPSC */
+
+int serial_init (void)
+{
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	(void)NS16550_init(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	(void)NS16550_init(COM_PORTS[1], clock_divisor);
+#endif
+
+	return (0);
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
+
+	NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
+}
+
+int
+serial_getc(void)
+{
+	return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+int
+serial_tstc(void)
+{
+	return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+void
+serial_setbrg (void)
+{
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void
+kgdb_serial_init(void)
+{
+}
+
+void
+putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void
+putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int
+getDebugChar (void)
+{
+	return serial_getc();
+}
+
+void
+kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/u-boot/board/evb64260/serial.h b/u-boot/board/evb64260/serial.h
new file mode 100644
index 0000000..bac9253
--- /dev/null
+++ b/u-boot/board/evb64260/serial.h
@@ -0,0 +1,63 @@
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/u-boot/board/evb64260/u-boot.lds b/u-boot/board/evb64260/u-boot.lds
new file mode 100644
index 0000000..bc0bb06
--- /dev/null
+++ b/u-boot/board/evb64260/u-boot.lds
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/powerpc/cpu/74xx_7xx/start.o	(.text*)
+    *(.text*)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/evb64260/zuma_pbb.c b/u-boot/board/evb64260/zuma_pbb.c
new file mode 100644
index 0000000..aa15fa0
--- /dev/null
+++ b/u-boot/board/evb64260/zuma_pbb.c
@@ -0,0 +1,220 @@
+#include <common.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CMD_BSP)
+#include <command.h>
+#endif
+
+#include <pci.h>
+#include <galileo/pci.h>
+#include "zuma_pbb.h"
+
+#undef DEBUG
+
+#define PAT_LO 0x00010203
+#define PAT_HI 0x04050607
+
+static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL;
+static char test_buf1[2048];
+static char test_buf2[2048];
+void zuma_init_pbb(void);
+int zuma_mbox_init(void);
+int zuma_test_dma(int cmd, int size);
+
+int zuma_test_dma (int cmd, int size)
+{
+	static const char *const test_legend[] = {
+		"write", "verify",
+		"copy", "compare",
+		"write inc", "verify inc"
+	};
+	register int i, j;
+	unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
+	unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
+	volatile unsigned int *ps = (unsigned int *) p1;
+	volatile unsigned int *pd = (unsigned int *) p2;
+	unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI;
+	DMA_INT_STATUS stat;
+	int ret = 0;
+
+	if (!zuma_pbb_reg) {
+		printf ("not initted\n");
+		return -1;
+	}
+
+	if (cmd < 0 || cmd > 5) {
+		printf ("inv cmd %d\n", cmd);
+		return -1;
+	}
+
+	if (cmd == 2 || cmd == 3) {
+		/* not implemented */
+		return 0;
+	}
+
+	if (size <= 0 || size > 1024)
+		size = 1024;
+
+	size &= (~7);				/* throw away bottom 3 bits */
+
+	p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
+	p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
+
+	memset ((void *) p1, 0, size);
+	memset ((void *) p2, 0, size);
+
+	for (i = 0; i < size / 4; i += 2) {
+		ps[i] = pat_lo;
+		ps[i + 1] = pat_hi;
+		if (cmd == 4 || cmd == 5) {
+			unsigned char *pl = (unsigned char *) &pat_lo;
+			unsigned char *ph = (unsigned char *) &pat_hi;
+
+			for (j = 0; j < 4; j++) {
+				pl[j] += 8;
+				ph[j] += 8;
+			}
+		}
+	}
+
+	funct = (1 << 31) | (cmd << 24) | (size);
+
+	zuma_pbb_reg->int_mask.pci_bits.chan0 =
+			EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG;
+
+	zuma_pbb_reg->debug_57 = PAT_LO;	/* patl */
+	zuma_pbb_reg->debug_58 = PAT_HI;	/* path */
+
+	zuma_pbb_reg->debug_54 = cpu_to_le32 (p1);	/* src 0x01b0 */
+	zuma_pbb_reg->debug_55 = cpu_to_le32 (p2);	/* dst 0x01b8 */
+	zuma_pbb_reg->debug_56 = cpu_to_le32 (funct);	/* func, 0x01c0 */
+
+	/* give DMA time to chew on things.. dont use DRAM or PCI */
+	/* if you can avoid it. */
+	do {
+		for (i = 0; i < 1000 * 10; i++);
+	} while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31));
+
+	stat.word = zuma_pbb_reg->status.word;
+	zuma_pbb_reg->int_mask.word = 0;
+
+	printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0);
+
+	printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
+	printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2],
+			ps[3]);
+	printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2],
+			pd[3]);
+	printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
+
+
+	if (cmd == 0 || cmd == 4) {
+		/* this is a write */
+		if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) ||	/* not done */
+			(memcmp ((void *) ps, (void *) pd, size) != 0)) {	/* cmp error */
+			for (i = 0; i < size / 4; i += 2) {
+				if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) {
+					printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]);
+					printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]);
+				}
+			}
+			ret = -1;
+		}
+	} else {
+		/* this is a verify */
+		if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) ||	/* not done */
+			(stat.pci_bits.chan0 & EOB_TX_FLAG)) {	/* cmp error */
+			printf ("%08x: %08x %08x\n",
+					le32_to_cpu (zuma_pbb_reg->debug_63),
+					zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62);
+			ret = -1;
+		}
+	}
+
+	printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size,
+			(ret == 0) ? "PASSED" : "FAILED");
+	return 0;
+}
+
+void zuma_init_pbb (void)
+{
+	unsigned int iobase;
+	pci_dev_t dev =
+			pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+
+	if (dev == -1) {
+		printf ("no zuma pbb\n");
+		return;
+	}
+
+	pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase);
+
+	iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+	zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase;
+
+
+	if (!zuma_pbb_reg) {
+		printf ("zuma pbb bar none! (hah hah, get it?)\n");
+		return;
+	}
+
+	zuma_pbb_reg->int_mask.word = 0;
+
+	printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg,
+			zuma_pbb_reg->version.pci_bits.rev_major,
+			zuma_pbb_reg->version.pci_bits.rev_minor,
+			zuma_pbb_reg->timestamp);
+
+}
+
+#if defined(CONFIG_CMD_BSP)
+
+static int last_cmd = 4;		/* write increment */
+static int last_size = 64;
+
+int
+do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	zuma_init_pbb ();
+	return 0;
+}
+
+int
+do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc > 1) {
+		last_cmd = simple_strtoul (argv[1], NULL, 10);
+	}
+	if (argc > 2) {
+		last_size = simple_strtoul (argv[2], NULL, 10);
+	}
+	zuma_test_dma (last_cmd, last_size);
+	return 0;
+}
+
+int
+do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	zuma_mbox_init ();
+	return 0;
+}
+
+U_BOOT_CMD(
+	zinit,	 1,	 0,	 do_zuma_init_pbb,
+	"init zuma pbb",
+	"\n"
+);
+U_BOOT_CMD(
+	zdtest,	  3,	  1,	  do_zuma_test_dma,
+	"run dma test",
+	"[cmd [count]]\n"
+	"    - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes"
+);
+U_BOOT_CMD(
+	zminit,	  1,	  0,	  do_zuma_init_mbox,
+	"init zuma mbox",
+	"\n"
+);
+
+#endif
diff --git a/u-boot/board/evb64260/zuma_pbb.h b/u-boot/board/evb64260/zuma_pbb.h
new file mode 100644
index 0000000..300b2fe
--- /dev/null
+++ b/u-boot/board/evb64260/zuma_pbb.h
@@ -0,0 +1,346 @@
+#ifndef ZUMA_PBB_H
+#define ZUMA_PBB_H
+
+#define MAX_NUM_BUFFER_PER_RING	32
+
+#ifdef __BIG_ENDIAN
+#define cpu_bits _be_s_bits	/* use with le32_to_cpu only */
+#define pci_bits _be_bits	/* may contain swapped bytes,
+				   but dont need le32_to_cpu */
+#endif
+
+#ifdef __LITTLE_ENDIAN
+#define cpu_bits _le_bits
+#define pci_bits _le_bits
+#endif
+
+#define VENDOR_ID_ZUMA		0x1172
+#define DEVICE_ID_ZUMA_PBB	0x0004
+
+#define RXDBP(chan)		(&sip->rx_desc[chan].base)	/* ch*8      */
+#define RXDP(chan)		(&sip->rx_desc[chan].current)	/* ch*8 +  4 */
+#define TXDBP(chan)		(&sip->tx_desc[chan].base)	/* ch*8 + 64 */
+#define TXDP(chan)		(&sip->tx_desc[chan].current)	/* ch*8 + 68 */
+
+#define PBB_DMA_OWN_BIT		0x80000000
+#define PBB_DMA_LAST_BIT	0x40000000
+
+#define EOF_RX_FLAG		1	/* bit 0 */
+#define EOB_RX_FLAG		2	/* bit 1 */
+#define EOF_TX_FLAG		4	/* bit 2 */
+#define EOB_TX_FLAG		8	/* bit 3 */
+
+#define TX_MODE(m)		(((m)&7) << 16)
+
+#define RX_DESC(i)		(cs->rx_desc[i])
+#define TX_DESC(i)		(cs->tx_desc[i])
+
+#define RX_CONTROL(i)		(RX_DESC(i).control.word)
+#define RX_CONTROL_SIZE(i)	(RX_DESC(i).control.rx.size)
+#define TX_CONTROL(i)		(TX_DESC(i).control.word)
+
+#define RX_DATA_P(i)		(&RX_DESC(i).ptr)
+#define TX_DATA_P(i)		(&TX_DESC(i).ptr)
+
+typedef volatile unsigned char V8;
+typedef volatile unsigned short V16;
+typedef volatile unsigned int V32;
+
+/* RAM descriptor layout */
+typedef struct _tag_dma_descriptor {
+    V32 ptr;
+    union {
+	struct {
+	    V32 owner:1;
+	    V32 last:1;
+	    V32 reserved0: 10;
+	    V32 tx_mode: 4;
+
+	    V32 reserved1: 5;
+	    V32 size: 11;
+	} tx;
+	struct {
+	    V32 owner:1;
+	    V32 last:1;
+	    V32 reserved0: 14;
+
+	    V32 reserved1: 5;
+	    V32 size: 11;
+	} rx;
+	V32 word;
+    } control;
+} DMA_DESCRIPTOR;
+
+/*
+ * NOTE: DO NOT USE structure to write non-word values... all registers
+ * MUST be written 4 bytes at a time in SI version 0.
+ * Non-word writes will result in "unaccessed" bytes written as zero.
+ *
+ * Byte reads are allowed.
+ *
+ * V32 pads are because the registers are spaced every 8 bytes (64 bits)
+ *
+ */
+
+/* NOTE!!! 4 dwords */
+typedef struct _tag_dma_descriptor_ring {
+    DMA_DESCRIPTOR *base;
+    V32 pad1;	/* skip high dword */
+    volatile DMA_DESCRIPTOR *current;
+    V32 pad3;	/* skip high dword */
+} DMA_DESCRIPTOR_RING;
+
+/* 1 dword */
+typedef union _tag_dma_generic {
+    struct {	/* byte 3 2 1 0 */
+	V32 chan7:4;	/* bits 31-28 */
+	V32 chan6:4;	/* bits 27-24 */
+	V32 chan5:4;	/* bits 23-20 */
+	V32 chan4:4;	/* bits 19-16 */
+	V32 chan3:4;	/* bits 15-12 */
+	V32 chan2:4;	/* bits 11-8 */
+	V32 chan1:4;	/* bits 7-4 */
+	V32 chan0:4;	/* bits 3-0 */
+    } _be_s_bits;
+    struct {	/* byte 0 1 2 3 */
+	V32 chan1:4;	/* bits 7-4 */
+	V32 chan0:4;	/* bits 3-0 */
+	V32 chan3:4;	/* bits 15-12 */
+	V32 chan2:4;	/* bits 11-8 */
+	V32 chan5:4;	/* bits 23-20 */
+	V32 chan4:4;	/* bits 19-16 */
+	V32 chan7:4;	/* bits 31-28 */
+	V32 chan6:4;	/* bits 27-24 */
+    } _be_bits;
+    struct {	/* byte 0 1 2 3 */
+	V32 chan0:4;	/* bits 0-3 */
+	V32 chan1:4;	/* bits 4-7 */
+	V32 chan2:4;	/* bits 8-11 */
+	V32 chan3:4;	/* bits 12-15 */
+	V32 chan4:4;	/* bits 16-19 */
+	V32 chan5:4;	/* bits 20-23 */
+	V32 chan6:4;	/* bits 24-27 */
+	V32 chan7:4;	/* bits 28-31 */
+    } _le_bits;
+    V8 byte[4];
+    V32 word;
+} DMA_RXTX_ENABLE, DMA_RX_DELETE,
+  DMA_INT_STATUS, DMA_INT_MASK,
+  DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK;
+
+/* 1 dword */
+typedef union _tag_dma_rx_timer{
+    struct {
+	V32 res0:8;	/* bits 32-24 */
+	V32 res1:7;	/* bits 23-17 */
+	V32 enable:1;	/* bit 16 */
+	V32 value:16;	/* bits 15-0 */
+    } _be_s_bits;
+    struct {
+	/* crosses byte boundary. must use swap. */
+	V32 s_value:16;	/* bits 7-0,15-8 */
+	V32 enable:1;	/* bit 16 */
+	V32 res1:7;	/* bits 23-17 */
+	V32 res0:8;	/* bits 32-24 */
+    } _be_bits;
+    struct {
+	V32 value:16;	/* bits 0-15 */
+	V32 enable:1;	/* bit 16 */
+	V32 res1:7;	/* bits 17-23 */
+	V32 res0:8;	/* bits 24-32 */
+    } _le_bits;
+    V8 byte[4];
+    V32 word;
+} DMA_RX_TIMER;
+
+/* NOTE!!!: 2 dwords */
+typedef struct _tag_dma_desc_level{
+    union {
+	struct {
+	    V32 res1:8;	/* bits 31-24 */
+	    V32 res0:7;	/* bits 23-17 */
+	    V32 write:1;	/* bit 16 */
+	    V32 thresh:8;	/* bits 15-8 */
+	    V32 level:8;	/* bits 7-0 */
+	} _be_s_bits;
+	struct {
+	    V32 level:8;	/* bits 7-0 */
+	    V32 thresh:8;	/* bits 15-8 */
+	    V32 res0:7;	/* bits 30-17 */
+	    V32 write:1;	/* bit 16 */
+	    V32 res1:8;	/* bits 31-24 */
+	} _be_bits;
+	struct {
+	    V32 level:8;	/* bits 0-7 */
+	    V32 thresh:8;	/* bits 8-15 */
+	    V32 write:1;	/* bit 16 */
+	    V32 res0:7;	/* bit 17-30 */
+	    V32 res1:8;	/* bits 24-31 */
+	} _le_bits;
+	V8 byte[4];
+	V32 word;
+    } desc;
+    V32 pad1;
+} DMA_DESC_LEVEL;
+
+typedef struct _tag_pbb_dma_reg_map {
+    /* 0-15 (0x000-0x078) */
+    DMA_DESCRIPTOR_RING rx_desc[8];	/* 4 dwords each, 128 bytes tot. */
+
+    /* 16-31 (0x080-0x0f8) */
+    DMA_DESCRIPTOR_RING tx_desc[8];	/* 4 dwords each, 128 bytes tot. */
+
+    /* 32/33 (0x100/0x108) */
+    V32 reserved_32;
+    V32 pad_32;
+    V32 reserved_33;
+    V32 pad_33;
+
+    /* 34 (0x110) */
+    DMA_RXTX_ENABLE rxtx_enable;
+    V32 pad_34;
+
+    /* 35 (0x118) */
+    DMA_RX_DELETE rx_delete;
+    V32 pad_35;
+
+    /* 36-38 (0x120-0x130) */
+    DMA_INT_STATUS status;
+    V32 pad_36;
+    DMA_INT_STATUS last_status;
+    V32 pad_37;
+    DMA_INT_MASK int_mask;
+    V32 pad_38;
+
+    /* 39/40 (0x138/0x140) */
+    union {
+	/* NOTE!! 4 dwords */
+	struct {
+	    V32 channel_3:8;
+	    V32 channel_2:8;
+	    V32 channel_1:8;
+	    V32 channel_0:8;
+	    V32 pad1;
+	    V32 channel_7:8;
+	    V32 channel_6:8;
+	    V32 channel_5:8;
+	    V32 channel_4:8;
+	    V32 pad3;
+	} _be_s_bits;
+	struct {
+	    V32 channel_0:8;
+	    V32 channel_1:8;
+	    V32 channel_2:8;
+	    V32 channel_3:8;
+	    V32 pad1;
+	    V32 channel_4:8;
+	    V32 channel_5:8;
+	    V32 channel_6:8;
+	    V32 channel_7:8;
+	    V32 pad3;
+	} _be_bits, _le_bits;
+	V8 byte[16];
+	V32 word[4];
+    } rx_size;
+
+    /* 41/42 (0x148/0x150) */
+    V32 reserved_41;
+    V32 pad_41;
+    V32 reserved_42;
+    V32 pad_42;
+
+    /* 43/44 (0x158/0x160) */
+    DMA_RX_LEVEL_STATUS rx_level_status;
+    V32 pad_43;
+    DMA_RX_LEVEL_INT_MASK rx_level_int_mask;
+    V32 pad_44;
+
+    /* 45 (0x168) */
+    DMA_RX_TIMER rx_timer;
+    V32 pad_45;
+
+    /* 46 (0x170) */
+    V32 reserved_46;
+    V32 pad_46;
+
+    /* 47 (0x178) */
+    V32 mbox_status;
+    V32 pad_47;
+
+    /* 48/49 (0x180/0x188) */
+    V32 mbox_out;
+    V32 pad_48;
+    V32 mbox_in;
+    V32 pad_49;
+
+    /* 50 (0x190) */
+    V32 config;
+    V32 pad_50;
+
+    /* 51/52 (0x198/0x1a0) */
+    V32 c2a_ctr;
+    V32 pad_51;
+    V32 a2c_ctr;
+    V32 pad_52;
+
+    /* 53 (0x1a8) */
+    union {
+	struct {
+	    V32 rev_major:8;	/* bits 31-24 */
+	    V32 rev_minor:8;	/* bits 23-16 */
+	    V32 reserved:16;	/* bits 15-0 */
+	} _be_s_bits;
+	struct {
+	    V32 s_reserved:16;	/* bits 7-0, 15-8 */
+	    V32 rev_minor:8;	/* bits 23-16 */
+	    V32 rev_major:8;	/* bits 31-24 */
+	} _be_bits;
+	struct {
+	    V32 reserved:16;	/* bits 0-15 */
+	    V32 rev_minor:8;	/* bits 16-23 */
+	    V32 rev_major:8;	/* bits 24-31 */
+	} _le_bits;
+	V8 byte[4];
+	V32 word;
+    } version;
+    V32 pad_53;
+
+    /* 54-59 (0x1b0-0x1d8) */
+    V32 debug_54;
+    V32 pad_54;
+    V32 debug_55;
+    V32 pad_55;
+    V32 debug_56;
+    V32 pad_56;
+    V32 debug_57;
+    V32 pad_57;
+    V32 debug_58;
+    V32 pad_58;
+    V32 debug_59;
+    V32 pad_59;
+
+    /* 60 (0x1e0) */
+    V32 timestamp;
+    V32 pad_60;
+
+    /* 61-63 (0x1e8-0x1f8) */
+    V32 debug_61;
+    V32 pad_61;
+    V32 debug_62;
+    V32 pad_62;
+    V32 debug_63;
+    V32 pad_63;
+
+    /* 64-71 (0x200 - 0x238) */
+    DMA_DESC_LEVEL rx_desc_level[8];	/* 2 dwords each, 32 bytes tot. */
+
+    /* 72-98 (0x240 - 0x2f8) */
+    /* reserved */
+
+    /* 96-127 (0x300 - 0x3f8) */
+    /* mirrors (0x100 - 0x1f8) */
+
+} PBB_DMA_REG_MAP;
+
+
+#endif /* ZUMA_PBB_H */
diff --git a/u-boot/board/evb64260/zuma_pbb_mbox.c b/u-boot/board/evb64260/zuma_pbb_mbox.c
new file mode 100644
index 0000000..8e38102
--- /dev/null
+++ b/u-boot/board/evb64260/zuma_pbb_mbox.c
@@ -0,0 +1,189 @@
+#include <common.h>
+#include <galileo/pci.h>
+#include <net.h>
+#include <pci.h>
+
+#include "zuma_pbb.h"
+#include "zuma_pbb_mbox.h"
+
+
+struct _zuma_mbox_dev zuma_mbox_dev;
+
+
+static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data)
+{
+  unsigned int status, count = 0, i;
+
+  status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+
+  while((status & OUT_PENDING) && count < 1000) {
+    count++;
+    for(i=0;i<1000;i++);
+    status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+  }
+  if(count < 1000) {
+    /* if SET it means msg pending */
+    /* printf("mbox real write %08x\n",data); */
+    dev->sip->mbox_out = cpu_to_le32(data);
+    return 4;
+  }
+
+  printf("mbox tx timeout\n");
+  return 0;
+}
+
+static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data)
+{
+  unsigned int status, count = 0, i;
+
+  status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+
+  while(!(status & IN_VALID) && count < 1000) {
+    count++;
+    for(i=0;i<1000;i++);
+    status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+  }
+  if(count < 1000) {
+    /* if SET it means msg pending */
+    *data=le32_to_cpu(dev->sip->mbox_in);
+    /*printf("mbox real read %08x\n", *data); */
+    return 4;
+  }
+  printf("mbox rx timeout\n");
+  return 0;
+}
+
+static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in)
+{
+  int ret;
+  ret=zuma_mbox_write(&zuma_mbox_dev,out);
+  /*printf("write 0x%08x (%d bytes)\n", out, ret); */
+  if(ret!=4) return -1;
+  ret=zuma_mbox_read(&zuma_mbox_dev,in);
+  /*printf("read 0x%08x (%d bytes)\n", *in, ret); */
+  if(ret!=4) return -1;
+  return 0;
+}
+
+
+#define RET_IF_FAILED(x)	if ((x) == -1) return -1
+
+static int zuma_mbox_do_all_mailbox(void)
+{
+  unsigned int data_in;
+  unsigned short sdata_in;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in));
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in));
+  memcpy(zuma_acc_mac+2,&data_in,4);
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in));
+  sdata_in=data_in&0xffff;
+  memcpy(zuma_acc_mac,&sdata_in,2);
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in));
+  zuma_ip=data_in;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in));
+  zuma_slot_bac=data_in>>3;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in));
+  zuma_console_baud = data_in & 0xffff;
+  zuma_debug_baud   = data_in >> 16;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in));
+  memcpy(zuma_prv_mac+2,&data_in,4);
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in));
+  sdata_in=data_in&0xffff;
+  memcpy(zuma_prv_mac,&sdata_in,2);
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in));
+
+  return 0;
+}
+
+
+static void
+zuma_mbox_dump(void)
+{
+  printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2));
+  printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2));
+  printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3);
+  printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud);
+}
+
+
+static void
+zuma_mbox_setenv(void)
+{
+  char *data, buf[32];
+  unsigned char save = 0;
+
+  data = getenv("baudrate");
+
+  if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) {
+    sprintf(buf, "%6d", zuma_console_baud);
+    setenv("baudrate", buf);
+    save=1;
+    printf("baudrate doesn't match from mbox\n");
+  }
+
+  ip_to_string(zuma_ip, buf);
+  setenv("ipaddr", buf);
+
+  sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
+	  zuma_prv_mac[0],
+	  zuma_prv_mac[1],
+	  zuma_prv_mac[2],
+	  zuma_prv_mac[3],
+	  zuma_prv_mac[4],
+	  zuma_prv_mac[5]);
+  setenv("ethaddr", buf);
+
+  sprintf(buf,"%02x",zuma_slot_bac);
+  setenv("bacslot", buf);
+
+  if(save)
+    saveenv();
+}
+
+/**
+ *	zuma_mbox_init:
+ */
+
+int zuma_mbox_init(void)
+{
+  unsigned int iobase;
+  memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev));
+
+  zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+
+  if(zuma_mbox_dev.dev == -1) {
+    printf("no zuma pbb\n");
+    return -1;
+  }
+
+  pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
+
+  iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+  zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)iobase;
+
+  zuma_mbox_dev.sip->int_mask.word=0;
+
+  printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip,
+	 zuma_mbox_dev.sip->version.pci_bits.rev_major,
+	 zuma_mbox_dev.sip->version.pci_bits.rev_minor,
+	 zuma_mbox_dev.sip->timestamp);
+
+  if (zuma_mbox_do_all_mailbox() == -1) {
+	  printf("mailbox failed.. no ACC?\n");
+	  return -1;
+  }
+
+  zuma_mbox_dump();
+
+  zuma_mbox_setenv();
+
+  return 0;
+}
diff --git a/u-boot/board/evb64260/zuma_pbb_mbox.h b/u-boot/board/evb64260/zuma_pbb_mbox.h
new file mode 100644
index 0000000..b4a4c0c
--- /dev/null
+++ b/u-boot/board/evb64260/zuma_pbb_mbox.h
@@ -0,0 +1,43 @@
+#define IN_VALID 1
+#define OUT_PENDING 2
+
+enum {
+	ZUMA_MBOXMSG_DONE,
+	ZUMA_MBOXMSG_MACL,
+	ZUMA_MBOXMSG_MACH,
+	ZUMA_MBOXMSG_IP,
+	ZUMA_MBOXMSG_SLOT,
+	ZUMA_MBOXMSG_RESET,
+	ZUMA_MBOXMSG_BAUD,
+	ZUMA_MBOXMSG_START,
+	ZUMA_MBOXMSG_ENG_PRV_MACL,
+	ZUMA_MBOXMSG_ENG_PRV_MACH,
+
+	MBOXMSG_LAST
+};
+
+struct zuma_mailbox_info {
+	unsigned char acc_mac[6];
+	unsigned char prv_mac[6];
+	unsigned int ip;
+	unsigned int slot_bac;
+	unsigned int console_baud;
+	unsigned int debug_baud;
+};
+
+struct _zuma_mbox_dev {
+	pci_dev_t dev;
+	PBB_DMA_REG_MAP *sip;
+	struct zuma_mailbox_info mailbox;
+};
+
+#define zuma_prv_mac		zuma_mbox_dev.mailbox.prv_mac
+#define zuma_acc_mac		zuma_mbox_dev.mailbox.acc_mac
+#define zuma_ip                 zuma_mbox_dev.mailbox.ip
+#define zuma_slot_bac		zuma_mbox_dev.mailbox.slot_bac
+#define zuma_console_baud	zuma_mbox_dev.mailbox.console_baud
+#define zuma_debug_baud		zuma_mbox_dev.mailbox.debug_baud
+
+
+extern struct _zuma_mbox_dev zuma_mbox_dev;
+extern int zuma_mbox_init (void);
diff --git a/u-boot/board/fads/Makefile b/u-boot/board/fads/Makefile
new file mode 100644
index 0000000..cf79029
--- /dev/null
+++ b/u-boot/board/fads/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o lamp.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/fads/fads.c b/u-boot/board/fads/fads.c
new file mode 100644
index 0000000..9f7faaf
--- /dev/null
+++ b/u-boot/board/fads/fads.c
@@ -0,0 +1,949 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* ========================================================================= */
+
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
+
+#if defined(CONFIG_DRAM_50MHZ)
+/* 50MHz tables */
+static const uint dram_60ns[] =
+{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
+  0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
+  0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
+  0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
+  0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
+  0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint dram_70ns[] =
+{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+  0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+  0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
+  0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
+  0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+  0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_60ns[] =
+{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
+  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
+  0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
+  0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
+  0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_70ns[] =
+{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
+  0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
+  0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
+  0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
+  0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+  0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+#elif defined(CONFIG_DRAM_25MHZ)
+
+/* 25MHz tables */
+
+static const uint dram_60ns[] =
+{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint dram_70ns[] =
+{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_60ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
+  0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
+  0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_70ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
+  0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
+  0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+  0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+  0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+#else
+#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
+#endif
+
+/* ------------------------------------------------------------------------- */
+static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* init upm */
+
+	switch (delay) {
+	case 70:
+		if (edo) {
+			upmconfig (UPMA, (uint *) edo_70ns,
+				   sizeof (edo_70ns) / sizeof (uint));
+		} else {
+			upmconfig (UPMA, (uint *) dram_70ns,
+				   sizeof (dram_70ns) / sizeof (uint));
+		}
+
+		break;
+
+	case 60:
+		if (edo) {
+			upmconfig (UPMA, (uint *) edo_60ns,
+				   sizeof (edo_60ns) / sizeof (uint));
+		} else {
+			upmconfig (UPMA, (uint *) dram_60ns,
+				   sizeof (dram_60ns) / sizeof (uint));
+		}
+
+		break;
+
+	default:
+		return -1;
+	}
+
+	memctl->memc_mptpr = 0x0400;	/* divide by 16 */
+
+	switch (noMbytes) {
+	case 4:				/* 4 Mbyte uses only CS2 */
+#ifdef CONFIG_ADS
+		memctl->memc_mamr = 0xc0a21114;
+#else
+		memctl->memc_mamr = 0x13a01114;	/* PTA 0x13 AMA 010 */
+#endif
+		memctl->memc_or2 = 0xffc00800;	/* 4M */
+		break;
+
+	case 8:				/* 8 Mbyte uses both CS3 and CS2 */
+		memctl->memc_mamr = 0x13a01114;	/* PTA 0x13 AMA 010 */
+		memctl->memc_or3 = 0xffc00800;	/* 4M */
+		memctl->memc_br3 = 0x00400081 + base;
+		memctl->memc_or2 = 0xffc00800;	/* 4M */
+		break;
+
+	case 16:			/* 16 Mbyte uses only CS2 */
+#ifdef CONFIG_ADS	/* XXX: why PTA=0x60 only in 16M case? - NTL */
+		memctl->memc_mamr = 0x60b21114;	/* PTA 0x60 AMA 011 */
+#else
+		memctl->memc_mamr = 0x13b01114;	/* PTA 0x13 AMA 011 */
+#endif
+		memctl->memc_or2 = 0xff000800;	/* 16M */
+		break;
+
+	case 32:			/* 32 Mbyte uses both CS3 and CS2 */
+		memctl->memc_mamr = 0x13b01114;	/* PTA 0x13 AMA 011 */
+		memctl->memc_or3 = 0xff000800;	/* 16M */
+		memctl->memc_br3 = 0x01000081 + base;
+		memctl->memc_or2 = 0xff000800;	/* 16M */
+		break;
+
+	default:
+		return -1;
+	}
+
+	memctl->memc_br2 = 0x81 + base;	/* use upma */
+
+	*((uint *) BCSR1) &= ~BCSR1_DRAM_EN;	/* enable dram */
+
+	/* if no dimm is inserted, noMbytes is still detected as 8m, so
+	 * sanity check top and bottom of memory */
+
+	/* check bytes / 2 because get_ram_size tests at base+bytes, which
+	 * is not mapped */
+	if (noMbytes == 8)
+		if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
+			*((uint *) BCSR1) |= BCSR1_DRAM_EN;	/* disable dram */
+			return -1;
+		}
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void _dramdisable(void)
+{
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br2 = 0x00000000;
+	memctl->memc_br3 = 0x00000000;
+
+	/* maybe we should turn off upma here or something */
+}
+#endif /* !CONFIG_MPC885ADS */
+
+/* ========================================================================= */
+
+#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */
+
+#if defined(CONFIG_SDRAM_100MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table by Dan Malek                                                  */
+
+/* This has the stretched early timing so the 50 MHz
+ * processor can make the 100 MHz timing.  This will
+ * work at all processor speeds.
+ */
+
+#ifdef SDRAM_ALT_INIT_SEQENCE
+# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
+#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
+# define SDRAM_MCRVALUE0  0x80808111   /* run upmb cs4 loop 1 addr 0x11 MRS */
+# define SDRAM_MCRVALUE1  SDRAM_MCRVALUE0  /* ??? why not 0x80808130? */
+#else
+# define SDRAM_MxMR_PTx         195
+# define UPM_MRS_ADDR           0x11
+# define UPM_REFRESH_ADDR       0x30    /* or 0x11 if we want to be like above? */
+#endif /* !SDRAM_ALT_INIT_SEQUENCE */
+
+static const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
+	0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
+	0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
+	0x1ff77c45,
+
+	/* precharge + MRS. (offset 11 in upm RAM) */
+	0xeffbbc04, 0x1ff77c34, 0xefeabc34,
+	0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
+	0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
+	0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
+
+#elif defined(CONFIG_SDRAM_50MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table stolen from the fads manual                                   */
+/* for chip MB811171622A-100                                                 */
+
+/* this table is for 32-50MHz operation */
+#ifdef SDRAM_ALT_INIT_SEQENCE
+# define SDRAM_MBMRVALUE0 0x80802114   /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
+# define SDRAM_MBMRVALUE1 0x80802118   /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
+# define SDRAM_MCRVALUE0  0x80808105   /* run upmb cs4 loop 1 addr 0x5 MRS */
+# define SDRAM_MCRVALUE1  0x80808130   /* run upmb cs4 loop 1 addr 0x30 REFRESH */
+# define SDRAM_MPTRVALUE  0x400
+#define SDRAM_MARVALUE   0x88
+#else
+# define SDRAM_MxMR_PTx         128
+# define UPM_MRS_ADDR           0x5
+# define UPM_REFRESH_ADDR       0x30
+#endif  /* !SDRAM_ALT_INIT_SEQUENCE */
+
+static const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* precharge + MRS. (offset 5 in upm RAM) */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+/* ------------------------------------------------------------------------- */
+#else
+#error SDRAM not correctly configured
+#endif
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+#define SDRAM_OR4VALUE   0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
+#define SDRAM_BR4VALUE   0x000000c1 /* UPMB,base addr or'ed on later */
+
+/* ------------------------------------------------------------------------- */
+#ifdef SDRAM_ALT_INIT_SEQENCE
+/* ------------------------------------------------------------------------- */
+
+static int _initsdram(uint base, uint noMbytes)
+{
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
+
+	/* Configure the refresh (mostly).  This needs to be
+	* based upon processor clock speed and optimized to provide
+	* the highest level of performance.  For multiple banks,
+	* this time has to be divided by the number of banks.
+	* Although it is not clear anywhere, it appears the
+	* refresh steps through the chip selects for this UPM
+	* on each refresh cycle.
+	* We have to be careful changing
+	* UPM registers after we ask it to run these commands.
+	*/
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */
+	memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */
+
+	udelay(200);
+
+	/* Now run the precharge/nop/mrs commands.
+	*/
+
+	memctl->memc_mcr = 0x80808111;   /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
+	                                 /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+
+	memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/
+					    /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
+
+	udelay(200);
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */
+	memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */
+					    /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
+
+	udelay(200);
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */
+
+	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
+	memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#else  /* !SDRAM_ALT_INIT_SEQUENCE */
+/* ------------------------------------------------------------------------- */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
+# define MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
+# define MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
+# define MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
+# define MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
+
+/*
+ * MxMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTBE  |   \
+			MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
+			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
+/* 9 column SDRAM */
+# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTAE  |   \
+			MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
+			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
+
+static int _initsdram(uint base, uint noMbytes)
+{
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = MPTPR_2BK_4K;
+	memctl->memc_mbmr  = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
+
+	/* map CS 4 */
+	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
+	memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+	/* Perform SDRAM initilization */
+# ifdef UPM_NOP_ADDR    /* not currently in UPM table */
+	/* step 1: nop */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(0) | UPM_NOP_ADDR;
+# endif
+
+	/* step 2: delay */
+	udelay(200);
+
+# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
+	/* step 3: precharge */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
+# endif
+
+	/* step 4: refresh */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(2) | UPM_REFRESH_ADDR;
+
+	/*
+	 * note: for some reason, the UPM values we are using include
+	 * precharge with MRS
+	 */
+
+	/* step 5: mrs */
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(1) | UPM_MRS_ADDR;
+
+# ifdef UPM_NOP_ADDR
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(0) | UPM_NOP_ADDR;
+# endif
+	/*
+	 * Enable refresh
+	 */
+
+	memctl->memc_mbmr |= MBMR_PTBE;
+	return 0;
+}
+#endif  /* !SDRAM_ALT_INIT_SEQUENCE */
+
+/* ------------------------------------------------------------------------- */
+
+static void _sdramdisable(void)
+{
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = 0x00000000;
+
+	/* maybe we should turn off upmb here or something */
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int initsdram(uint base, uint *noMbytes)
+{
+	uint m = CONFIG_SYS_SDRAM_SIZE>>20;
+
+	/* _initsdram needs access to sdram */
+	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
+
+	if(!_initsdram(base, m))
+	{
+	        *noMbytes += m;
+		return 0;
+	}
+	else
+	{
+		*((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
+
+		_sdramdisable();
+
+		return -1;
+	}
+}
+
+#endif /* CONFIG_FADS */
+
+/* ========================================================================= */
+
+phys_size_t initdram (int board_type)
+{
+	uint sdramsz = 0;	/* size of sdram in Mbytes */
+	uint base = 0;		/* base of dram in bytes */
+	uint m = 0;		/* size of dram in Mbytes */
+#ifndef CONFIG_MPC885ADS
+	uint k, s;
+#endif
+
+#ifdef CONFIG_FADS
+	if (!initsdram (0x00000000, &sdramsz)) {
+		base = sdramsz << 20;
+		printf ("(%u MB SDRAM) ", sdramsz);
+	}
+#endif
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
+	k = (*((uint *) BCSR2) >> 23) & 0x0f;
+
+	switch (k & 0x3) {
+		/* "MCM36100 / MT8D132X" */
+	case 0x00:
+		m = 4;
+		break;
+
+		/* "MCM36800 / MT16D832X" */
+	case 0x01:
+		m = 32;
+		break;
+		/* "MCM36400 / MT8D432X" */
+	case 0x02:
+		m = 16;
+		break;
+		/* "MCM36200 / MT16D832X ?" */
+	case 0x03:
+		m = 8;
+		break;
+
+	}
+
+	switch (k >> 2) {
+	case 0x02:
+		k = 70;
+		break;
+
+	case 0x03:
+		k = 60;
+		break;
+
+	default:
+		printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
+		k = 70;
+	}
+
+#ifdef CONFIG_FADS
+	/* the FADS is missing this bit, all rams treated as non-edo */
+	s = 0;
+#else
+	s = (*((uint *) BCSR2) >> 27) & 0x01;
+#endif
+
+	if (!_draminit (base, m, s, k)) {
+		printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
+	} else {
+		_dramdisable ();
+		m = 0;
+	}
+#endif /* !CONFIG_MPC885ADS */
+	m += sdramsz;				/* add sdram size to total */
+
+	return (m << 20);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+    /* TODO: XXX XXX XXX */
+    printf ("test: 16 MB - ok\n");
+
+    return (0);
+}
+
+/* ========================================================================= */
+
+/*
+ * Check Board Identity:
+ */
+
+#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD)
+static void checkdboard(void)
+{
+	/* get db type from BCSR 3 */
+	uint k = (*((uint *)BCSR3) >> 24) & 0x3f;
+
+	puts (" with db ");
+
+	switch(k) {
+	case 0x03 :
+		puts ("MPC823");
+		break;
+	case 0x20 :
+		puts ("MPC801");
+		break;
+	case 0x21 :
+		puts ("MPC850");
+		break;
+	case 0x22 :
+		puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
+		break;
+	case 0x23 :
+		puts ("MPC860SAR");
+		break;
+	case 0x24 :
+	case 0x2A :
+		puts ("MPC860T");
+		break;
+	case 0x3F :
+		puts ("MPC850SAR");
+		break;
+	default : printf("0x%x", k);
+	}
+}
+#endif	/* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */
+
+int checkboard (void)
+{
+#if   defined(CONFIG_MPC86xADS)
+	puts ("Board: MPC86xADS\n");
+#elif defined(CONFIG_MPC885ADS)
+	puts ("Board: MPC885ADS\n");
+#else /* Only old ADS/FADS have got revision ID in BCSR3 */
+	uint r =  (((*((uint *) BCSR3) >> 23) & 1) << 3)
+		| (((*((uint *) BCSR3) >> 19) & 1) << 2)
+		| (((*((uint *) BCSR3) >> 16) & 3));
+
+	puts ("Board: ");
+#if defined(CONFIG_FADS)
+	puts ("FADS");
+	checkdboard ();
+#else
+	puts ("ADS");
+#endif
+
+	puts (" rev ");
+
+	switch (r) {
+#if defined(CONFIG_ADS)
+	case 0x00:
+		puts ("ENG - this board sucks, check the errata, not supported\n");
+		return -1;
+	case 0x01:
+		puts ("PILOT - warning, read errata \n");
+		break;
+	case 0x02:
+		puts ("A - warning, read errata \n");
+		break;
+	case 0x03:
+		puts ("B\n");
+		break;
+#else  /* FADS */
+	case 0x00:
+		puts ("ENG\n");
+		break;
+	case 0x01:
+		puts ("PILOT\n");
+		break;
+#endif /* CONFIG_ADS */
+	default:
+		printf ("unknown (0x%x)\n", r);
+		return -1;
+	}
+#endif /* CONFIG_MPC86xADS */
+
+	return 0;
+}
+
+/* ========================================================================= */
+
+#if defined(CONFIG_CMD_PCMCIA)
+
+#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init(void)
+{
+	volatile pcmconf8xx_t	*pcmp;
+	uint v, slota = 0, slotb = 0;
+
+	/*
+	** Enable the PCMCIA for a Flash card.
+	*/
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+#if 0
+	pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
+	pcmp->pcmc_por0 = 0xc00ff05d;
+#endif
+
+	/* Set all slots to zero by default. */
+	pcmp->pcmc_pgcra = 0;
+	pcmp->pcmc_pgcrb = 0;
+#ifdef CONFIG_PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0x40;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0x40;
+#endif
+
+	/* enable PCMCIA buffers */
+	*((uint *)BCSR1) &= ~BCSR1_PCCEN;
+
+	/* Check if any PCMCIA card is plugged in. */
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
+	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+#endif
+
+	if (!(slota || slotb)) {
+		printf("No card present\n");
+		pcmp->pcmc_pgcra = 0;
+		pcmp->pcmc_pgcrb = 0;
+		return -1;
+	}
+	else
+		printf("Card present (");
+
+	v = 0;
+
+	/* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
+	**
+	** Paolo - Yes, but i have to insert some 3.3V card in that slot on
+	**	   my FADS... :-)
+	*/
+
+#if defined(CONFIG_MPC86x)
+	switch ((pcmp->pcmc_pipr >> 30) & 3)
+#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
+	switch ((pcmp->pcmc_pipr >> 14) & 3)
+#endif
+	{
+	case 0x03 :
+		printf("5V");
+		v = 5;
+		break;
+	case 0x01 :
+		printf("5V and 3V");
+#ifdef CONFIG_FADS
+		v = 3; /* User lower voltage if supported! */
+#else
+		v = 5;
+#endif
+		break;
+	case 0x00 :
+		printf("5V, 3V and x.xV");
+#ifdef CONFIG_FADS
+		v = 3; /* User lower voltage if supported! */
+#else
+		v = 5;
+#endif
+		break;
+	}
+
+	switch (v) {
+#ifdef CONFIG_FADS
+	case 3:
+		printf("; using 3V");
+		/*
+		** Enable 3 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
+		*((uint *)BCSR1) |= BCSR1_PCCVCC0;
+		break;
+#endif
+	case 5:
+		printf("; using 5V");
+#ifdef CONFIG_ADS
+		/*
+		** Enable 5 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
+#endif
+#ifdef CONFIG_FADS
+		/*
+		** Enable 5 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
+		*((uint *)BCSR1) |= BCSR1_PCCVCC1;
+#endif
+		break;
+
+	default:
+		*((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */
+
+		printf("; unknown voltage");
+		return -1;
+	}
+	printf(")\n");
+	/* disable pcmcia reset after a while */
+
+	udelay(20);
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0;
+#endif
+
+	/* If you using a real hd you should give a short
+	* spin-up time. */
+#ifdef CONFIG_DISK_SPINUP_TIME
+	udelay(CONFIG_DISK_SPINUP_TIME);
+#endif
+
+	return 0;
+}
+
+#endif
+
+/* ========================================================================= */
+
+#ifdef CONFIG_SYS_PC_IDE_RESET
+
+void ide_set_reset(int on)
+{
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Configure PC for IDE Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+	} else {		/* release RESET */
+		immr->im_ioport.iop_pcdat |=   CONFIG_SYS_PC_IDE_RESET;
+	}
+
+	/* program port pin as GPIO output */
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso  &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |=   CONFIG_SYS_PC_IDE_RESET;
+}
+
+#endif	/* CONFIG_SYS_PC_IDE_RESET */
diff --git a/u-boot/board/fads/fads.h b/u-boot/board/fads/fads.h
new file mode 100644
index 0000000..3dc5358
--- /dev/null
+++ b/u-boot/board/fads/fads.h
@@ -0,0 +1,495 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
+ * and Dan Malek
+ *
+ * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+ *
+ * This header file contains values common to all FADS family boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * Flash Memory Map as used by U-Boot:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
+ * |                       | 0xFE00_0100     Reset Vector
+ * +                       + 0xFE0?_????
+ * | U-Boot code           |
+ * |                       |
+ * +-----------------------+ 0xFE04_0000 (sector border)
+ * |                       |
+ * |                       |
+ * | U-Boot environment    |
+ * |                       |                                 ^
+ * |                       |                                 | U-Boot
+ * +=======================+ 0xFE08_0000 (sector border)    -----------------
+ * | Available             |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND							\
+    "dhcp;"									\
+    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "			\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm"
+
+#define CONFIG_BOOTCOMMAND							\
+    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if !defined(CONFIG_MPC885ADS)
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+#endif
+
+/*
+ * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
+ * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
+ * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
+ * got FEC so FEC is the default.
+ */
+#ifndef CONFIG_ADS
+#undef	CONFIG_SCC1_ENET		/* Disable SCC1 ethernet */
+#define	CONFIG_FEC_ENET			/* Use FEC ethernet  */
+#else					/* Old ADS has not got FEC option */
+#define	CONFIG_SCC1_ENET		/* Use SCC1 ethernet */
+#undef	CONFIG_FEC_ENET			/* No FEC ethernet  */
+#endif /* !CONFIG_ADS */
+
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#ifdef CONFIG_FEC_ENET
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII_INIT		1
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_PROMPT		"=>"		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size	*/
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define	CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
+#define	CONFIG_SYS_SDRAM_SIZE		0x00800000	/* 8 Mbyte */
+/*
+ * 2048	SDRAM rows
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CONFIG_SYS_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
+#elif defined(CONFIG_FADS)				/* Old/new FADS */
+#define	CONFIG_SYS_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
+#else							/* Old ADS */
+#define	CONFIG_SYS_SDRAM_SIZE		0x00000000		/* No SDRAM */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#if (CONFIG_SYS_SDRAM_SIZE)
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
+#else
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#endif /* CONFIG_SYS_SDRAM_SIZE */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CONFIG_SYS_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
+#define CONFIG_ENV_OFFSET		CONFIG_ENV_SECT_SIZE
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment		*/
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+#if defined(CONFIG_CMD_JFFS2)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
+#define MTDPARTS_DEFAULT	"mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
+*/
+
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+
+/*-----------------------------------------------------------------------
+ * I2C configuration
+ */
+#if defined(CONFIG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address defaults */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	SCCR_TBS
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register
+ *-----------------------------------------------------------------------
+ * Set to zero to prevent the processor from entering debug mode
+ */
+#define CONFIG_SYS_DER		 0
+
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register.  For CS0, you must write
+ * the base register first, followed by the option register.
+ */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/OR0 (Flash)
+ * BR1/OR1 (BCSR)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define BCSR_ADDR		((uint) 0xFF080000)
+
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CONFIG_SYS_OR1_PRELIM	0xFFFF8110		/* 64Kbyte address space */
+#define CONFIG_SYS_BR1_PRELIM	((BCSR_ADDR) | BR_V)
+
+/* values according to the manual */
+
+#define	BCSR0			((uint) (BCSR_ADDR + 0x00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/*
+ * (F)ADS bitvalues by Helmut Buchsbaum
+ *
+ * See User's Manual for a proper
+ * description of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR1_PCCVCCON		 BCSR1_PCCVCC0
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT     28
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      23
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#if defined(CONFIG_MPC823)
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#define BCSR4_VCCO               ((uint)0x02000000)
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#elif defined(CONFIG_MPC850)
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#elif defined(CONFIG_MPC860SAR)
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#else /* MPC860T and other chips with FEC */
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif
+
+/* BSCR5 exists on MPC86xADS and MPC885ADS only */
+
+#define CONFIG_SYS_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+
+#define BCSR5			(CONFIG_SYS_PHYDEV_ADDR + 0x300)
+
+#define BCSR5_MII2_EN		0x40
+#define BCSR5_MII2_RST		0x20
+#define BCSR5_T1_RST		0x10
+#define BCSR5_ATM155_RST	0x08
+#define BCSR5_ATM25_RST		0x04
+#define BCSR5_MII1_EN		0x02
+#define BCSR5_MII1_RST		0x01
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_MAC_PARTITION    1
+#define CONFIG_DOS_PARTITION    1
+#define CONFIG_ISO_PARTITION	1
+
+#undef	CONFIG_ATAPI
+#if 0	/* does not make sense when CONFIG_CMD_IDE is not enabled, too */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+#endif
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+/* #undef CONFIG_DISK_SPINUP_TIME */	/* usin  Compact Flash */
diff --git a/u-boot/board/fads/flash.c b/u-boot/board/fads/flash.c
new file mode 100644
index 0000000..b9afb75
--- /dev/null
+++ b/u-boot/board/fads/flash.c
@@ -0,0 +1,560 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+#define QUAD_ID(id)	((((ulong)(id) & 0xFF) << 24) | \
+			 (((ulong)(id) & 0xFF) << 16) | \
+			 (((ulong)(id) & 0xFF) << 8)  | \
+			 (((ulong)(id) & 0xFF) << 0)    \
+			)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	vu_long *bcsr = (vu_long *)BCSR_ADDR;
+	unsigned long pd_size, total_size, bsize, or_am;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].size = 0;
+		flash_info[i].sector_count = 0;
+		flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */
+	}
+
+	switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) {
+	case 2:
+	case 4:
+	case 6:
+		pd_size = 0x800000;
+		or_am = 0xFF800000;
+		break;
+
+	case 5:
+	case 7:
+		pd_size = 0x400000;
+		or_am = 0xFFC00000;
+		break;
+
+	case 8:
+		pd_size = 0x200000;
+		or_am = 0xFFE00000;
+		break;
+
+	default:
+		pd_size = 0;
+		or_am = 0xFFE00000;
+		printf("## Unsupported flash detected by BCSR: 0x%08lX\n", bcsr[2]);
+	}
+
+	total_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
+		bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size),
+				       &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, bsize, bsize >> 20);
+		}
+
+		total_size += bsize;
+	}
+
+	if (total_size != pd_size) {
+		printf("## Detected flash size %lu conflicts with PD data %lu\n",
+		       total_size, pd_size);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CONFIG_SYS_MONITOR_BASE,
+				       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+				       &flash_info[i]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		if (CONFIG_ENV_ADDR >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CONFIG_ENV_ADDR,
+				       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+				       &flash_info[i]);
+#endif
+	}
+
+	return total_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM080:
+		printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ * The following code can not run from flash!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x90909090;
+
+	switch (addr[0]) {
+	case QUAD_ID(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case QUAD_ID(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	switch (addr[1]) {	/* device ID            */
+	case QUAD_ID(AMD_ID_F040B):
+	case QUAD_ID(AMD_ID_LV040B):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case QUAD_ID(AMD_ID_F080B):
+		info->flash_id += FLASH_AM080;
+		info->sector_count = 16;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif /* 0 */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+#if 0
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#else
+	/* set sector offsets for uniform sector type */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = (ulong)addr + (i * 0x00040000);
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *) (info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *) info->start[0];
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x80808080;
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *) (info->start[sect]);
+			addr[0] = 0x30303030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (vu_long *) (info->start[l_sect]);
+	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+	{
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *) info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0xA0A0A0A0;
+
+	*((vu_long *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
+	{
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return ERR_TIMOUT;
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/fads/lamp.c b/u-boot/board/fads/lamp.c
new file mode 100644
index 0000000..4e58291
--- /dev/null
+++ b/u-boot/board/fads/lamp.c
@@ -0,0 +1,47 @@
+#include <config.h>
+
+#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */
+
+#include <common.h>
+
+void
+signal_delay(unsigned int n)
+{
+  while (n--);
+}
+
+void
+signal_on(void)
+{
+  *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */
+}
+
+void
+signal_off(void)
+{
+  *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */
+}
+
+void
+slow_blink(unsigned int n)
+{
+  while (n--) {
+    signal_on();
+    signal_delay(0x00400000);
+    signal_off();
+    signal_delay(0x00400000);
+  }
+}
+
+void
+fast_blink(unsigned int n)
+{
+  while (n--) {
+    signal_on();
+    signal_delay(0x00100000);
+    signal_off();
+    signal_delay(0x00100000);
+  }
+}
+
+#endif /* !CONFIG_ADS */
diff --git a/u-boot/board/fads/pcmcia.c b/u-boot/board/fads/pcmcia.c
new file mode 100644
index 0000000..99fe0b4
--- /dev/null
+++ b/u-boot/board/fads/pcmcia.c
@@ -0,0 +1,84 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#ifdef	CONFIG_ADS
+#define	PCMCIA_BOARD_MSG "ADS"
+#else
+#define	PCMCIA_BOARD_MSG "FADS"
+#endif
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	u_long reg = 0;
+
+	switch(vpp) {
+		case 0: reg = 0; break;
+		case 50: reg = 1; break;
+		case 120: reg = 2; break;
+		default: return 1;
+	}
+
+	switch(vcc) {
+		case 0: reg = 0; break;
+#ifdef CONFIG_ADS
+	case 50: reg = BCSR1_PCCVCCON; break;
+#endif
+#ifdef CONFIG_FADS
+	case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
+	case 50: reg = BCSR1_PCCVCC1; break;
+#endif
+	default: return 1;
+	}
+
+	/* first, turn off all power */
+
+#ifdef CONFIG_ADS
+	*((uint *)BCSR1) |= BCSR1_PCCVCCON;
+#endif
+#ifdef CONFIG_FADS
+	*((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
+#endif
+	*((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
+
+	/* enable new powersettings */
+
+#ifdef CONFIG_ADS
+	*((uint *)BCSR1) &= ~reg;
+#endif
+#ifdef CONFIG_FADS
+	*((uint *)BCSR1) |= reg;
+#endif
+
+	*((uint *)BCSR1) |= reg << 20;
+
+	return 0;
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+	*((uint *)BCSR1) &= ~BCSR1_PCCEN;
+	return 0;
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	*((uint *)BCSR1) &= ~BCSR1_PCCEN;
+	return 0;
+}
+#endif
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/fads/u-boot.lds b/u-boot/board/fads/u-boot.lds
new file mode 100644
index 0000000..c1ad141
--- /dev/null
+++ b/u-boot/board/fads/u-boot.lds
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    /*. = DEFINED(env_offset) ? env_offset : .;*/
+    common/env_embedded.o	(.ppcenv*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/u-boot/board/faraday/a320evb/Makefile b/u-boot/board/faraday/a320evb/Makefile
new file mode 100644
index 0000000..fb540b4
--- /dev/null
+++ b/u-boot/board/faraday/a320evb/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= a320evb.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/faraday/a320evb/a320evb.c b/u-boot/board/faraday/a320evb/a320evb.c
new file mode 100644
index 0000000..b9343e4
--- /dev/null
+++ b/u-boot/board/faraday/a320evb/a320evb.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <asm/arch/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_1;
+	unsigned long expected_size = PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/u-boot/board/faraday/a320evb/lowlevel_init.S b/u-boot/board/faraday/a320evb/lowlevel_init.S
new file mode 100644
index 0000000..97718c0
--- /dev/null
+++ b/u-boot/board/faraday/a320evb/lowlevel_init.S
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/macro.h>
+#include <asm/arch/ftsdmc020.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define TP0_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
+#define TP1_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
+#define CR_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
+#define B0_BSR_A	(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
+#define ACR_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
+
+#define TP0_D		CONFIG_SYS_FTSDMC020_TP0
+#define TP1_D		CONFIG_SYS_FTSDMC020_TP1
+#define CR_D1		FTSDMC020_CR_IPREC
+#define CR_D2		FTSDMC020_CR_ISMR
+#define CR_D3		FTSDMC020_CR_IREF
+
+#define B0_BSR_D	(CONFIG_SYS_FTSDMC020_BANK0_BSR | \
+			FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
+#define ACR_D		FTSDMC020_ACR_TOC(0x18)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	ldr	r0, =CONFIG_FTSDMC020_BASE
+1:
+	ldr	r1, [r0, #FTSDMC020_OFFSET_CR]
+	cmp	r1, #0
+	bne	1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r11, lr
+
+	led	0x0
+
+	bl	init_sdmc
+
+	led	0x1
+
+	/* everything is fine now */
+	mov	lr, r11
+	mov	pc, lr
+
+/*
+ * memory initialization
+ */
+init_sdmc:
+	led	0x10
+
+	/* set SDRAM register */
+
+	write32	TP0_A, TP0_D
+	led	0x11
+
+	write32	TP1_A, TP1_D
+	led	0x12
+
+	/* set to precharge */
+	write32	CR_A, CR_D1
+	led	0x13
+
+	wait_sdram
+	led	0x14
+
+	/* set mode register */
+	write32	CR_A, CR_D2
+	led	0x15
+
+	wait_sdram
+	led	0x16
+
+	/* set to refresh */
+	write32	CR_A, CR_D3
+	led	0x17
+
+	wait_sdram
+	led	0x18
+
+	write32	B0_BSR_A, B0_BSR_D
+	led	0x19
+
+	write32	ACR_A, ACR_D
+	led	0x1a
+
+	mov	pc, lr
diff --git a/u-boot/board/flagadm/Makefile b/u-boot/board/flagadm/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/flagadm/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/flagadm/flagadm.c b/u-boot/board/flagadm/flagadm.c
new file mode 100644
index 0000000..dc9e2dc
--- /dev/null
+++ b/u-boot/board/flagadm/flagadm.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*Orginal table, GPL4 disabled*/
+const uint sdram_table[] =
+{
+	/* single read   (offset 0x00 in upm ram) */
+	0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
+	0x1ff74c47,
+	/* Precharge */
+	0x1FF74C05,
+	_NOT_USED_,
+	_NOT_USED_,
+	/* burst read    (offset 0x08 in upm ram) */
+	0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
+	0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* single write  (offset 0x18 in upm ram) */
+	0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
+	/* Load moderegister */
+	0x1FF74C34, /*Precharge*/
+	0xEFEA8C34, /*NOP*/
+	0x1FB54C35, /*Load moderegister*/
+	_NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+	0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
+	0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
+	0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* GPL5 driven every cycle */
+/* the display and the DSP */
+const uint dsp_disp_table[] =
+{
+	/* single read   (offset 0x00 in upm ram) */
+	0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
+	0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
+	/* burst read    (offset 0x08 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* single write  (offset 0x18 in upm ram) */
+	0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
+	0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
+	/* burst write   (offset 0x20 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+int checkboard (void)
+{
+	puts ("Board: FlagaDM V3.0\n");
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0;
+
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
+
+	udelay(100);
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = MPTPR_PTP_DIV16;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
+
+	/*Do the initialization of the SDRAM*/
+	/*Start with the precharge cycle*/
+	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
+				MCR_MLCF(1) | MCR_MAD(0x5));
+
+	/*Then we need two refresh cycles*/
+	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
+	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
+				MCR_MLCF(2) | MCR_MAD(0x30));
+
+	/*Mode register programming*/
+	memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
+	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
+				MCR_MLCF(1) | MCR_MAD(0x1C));
+
+	/* That should do it, just enable the periodic refresh in burst of 4*/
+	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
+	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
+
+	size_b0 = 16*1024*1024;
+
+	/*
+	 * No bank 1 or 3
+	 * invalidate bank
+	 */
+	memctl->memc_br1 = 0;
+	memctl->memc_br3 = 0;
+
+	upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
+
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;
+
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
+
+	return (size_b0);
+}
diff --git a/u-boot/board/flagadm/flash.c b/u-boot/board/flagadm/flash.c
new file mode 100644
index 0000000..a69b1a4
--- /dev/null
+++ b/u-boot/board/flagadm/flash.c
@@ -0,0 +1,703 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <flash.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+ulong flash_recognize (vu_long *base);
+int write_word (flash_info_t *info, ulong dest, ulong data);
+void flash_get_geometry (vu_long *base, flash_info_t *info);
+void flash_unprotect(flash_info_t *info);
+int _flash_real_protect(flash_info_t *info, long idx, int on);
+
+
+unsigned long flash_init (void)
+{
+	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	int i;
+	int rec;
+
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	*((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
+
+	flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+		(memctl->memc_br0 & ~(BR_BA_MSK));
+
+	rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE);
+
+	if (rec == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				flash_info[0].size, flash_info[0].size<<20);
+	}
+
+#if CONFIG_SYS_FLASH_PROTECTION
+	/*Unprotect all the flash memory*/
+	flash_unprotect(&flash_info[0]);
+#endif
+
+	*((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
+
+	return (flash_info[0].size);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_OFFSET,
+		      CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (flash_info[0].size);
+}
+
+
+int flash_get_protect_status(flash_info_t * info, long idx)
+{
+	vu_short * base;
+	ushort res;
+
+#ifdef DEBUG
+	printf("\n Attempting to set protection info with %d sectors\n", info->sector_count);
+#endif
+
+
+	base = (vu_short*)info->start[idx];
+
+	*(base) = 0xffff;
+
+	*(base + 0x55) = 0x0098;
+	res = base[0x2];
+
+	*(base) = 0xffff;
+
+	if(res != 0)
+		res = 1;
+	else
+		res = 0;
+
+	return res;
+}
+
+void flash_get_geometry (vu_long *base, flash_info_t *info)
+{
+	int i,j;
+	ulong ner = 0;
+	vu_short * sb  = (vu_short*)base;
+	ulong offset = (ulong)base;
+
+	/* Read Device geometry */
+
+	*sb = 0xffff;
+
+	*sb = 0x0090;
+
+	info->flash_id = ((ulong)base[0x0]);
+#ifdef DEBUG
+	printf("Id is %x\n", (uint)(ulong)info->flash_id);
+#endif
+
+	*sb = 0xffff;
+
+	*(sb+0x55) = 0x0098;
+
+	info->size = 1 << (sb[0x27]); /* Read flash size */
+
+#ifdef DEBUG
+	printf("Size is %x\n", (uint)(ulong)info->size);
+#endif
+
+	*sb = 0xffff;
+
+	*(sb + 0x55) = 0x0098;
+	ner = sb[0x2c] ; /*Number of erase regions*/
+
+#ifdef DEBUG
+	printf("Number of erase regions %x\n", (uint)ner);
+#endif
+
+	info->sector_count = 0;
+
+	for(i = 0; i < ner; i++)
+	{
+		uint s;
+		uint count;
+		uint t1,t2,t3,t4;
+
+		*sb = 0xffff;
+
+		*(sb + 0x55) = 0x0098;
+
+		t1 = sb[0x2d + i*4];
+		t2 = sb[0x2e + i*4];
+		t3 = sb[0x2f + i*4];
+		t4 = sb[0x30 + i*4];
+
+		count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/
+		s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/
+
+#ifdef DEBUG
+		printf("count and size %x, %x\n", count, s);
+		printf("sector count for erase region %d is %d\n", i, count);
+#endif
+		for(j = 0; j < count; j++)
+		{
+#ifdef DEBUG
+			printf("%x, ", (uint)offset);
+#endif
+			info->start[ info->sector_count + j] = offset;
+			offset += s;
+		}
+		info->sector_count += count;
+	}
+
+	if ((offset - (ulong)base) != info->size)
+		printf("WARNING reported size %x does not match to calculted size %x.\n"
+				, (uint)info->size, (uint)(offset - (ulong)base) );
+
+	/* Next check if there are any sectors protected.*/
+
+	for(i = 0; i < info->sector_count; i++)
+		info->protect[i] = flash_get_protect_status(info, i);
+
+	*sb = 0xffff;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case INTEL_MANUFACT & FLASH_VENDMASK:
+		printf ("Intel ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case INTEL_ID_28F320C3B & FLASH_TYPEMASK:
+		printf ("28F320RC3(4 MB)\n");
+		break;
+	case INTEL_ID_28F320J3A:
+		printf("28F320J3A (4 MB)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+			break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf ("  %02d %08lX%s",
+			i, info->start[i],
+			info->protect[i]!=0 ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return ;
+}
+
+ulong flash_recognize (vu_long *base)
+{
+	ulong id;
+	ulong res = FLASH_UNKNOWN;
+	vu_short * sb = (vu_short*)base;
+
+	*sb = 0xffff;
+
+	*sb = 0x0090;
+	id = base[0];
+
+	switch (id & 0x00FF0000)
+	{
+		case (MT_MANUFACT & 0x00FF0000):	/* MT or => Intel */
+		case (INTEL_ALT_MANU & 0x00FF0000):
+		res = FLASH_MAN_INTEL;
+		break;
+	default:
+		res = FLASH_UNKNOWN;
+	}
+
+	*sb = 0xffff;
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+#define INTEL_FLASH_STATUS_BLS	0x02
+#define INTEL_FLASH_STATUS_PSS	0x04
+#define INTEL_FLASH_STATUS_VPPS	0x08
+#define INTEL_FLASH_STATUS_PS	0x10
+#define INTEL_FLASH_STATUS_ES	0x20
+#define INTEL_FLASH_STATUS_ESS	0x40
+#define INTEL_FLASH_STATUS_WSMS	0x80
+
+int	flash_decode_status_bits(char status)
+{
+	int err = 0;
+
+	if(!(status & INTEL_FLASH_STATUS_WSMS)) {
+		printf("Busy\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_ESS) {
+		printf("Erase suspended\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_ES) {
+		printf("Error in block erase\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_PS) {
+		printf("Error in programming\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_VPPS) {
+		printf("Vpp low, operation aborted\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_PSS) {
+		printf("Program is suspended\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_BLS) {
+		printf("Attempting to program/erase a locked sector\n");
+		err = -1;
+	}
+
+	if((status & INTEL_FLASH_STATUS_PS) &&
+	   (status & INTEL_FLASH_STATUS_ES) &&
+	   (status & INTEL_FLASH_STATUS_ESS)) {
+		printf("A command sequence error\n");
+		return -1;
+	}
+
+	return err;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr;
+	int flag, prot, sect;
+	ulong start, now;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		char tmp;
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short *)(info->start[sect]);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Single Block Erase Command */
+			*addr = 0x0020;
+			/* Confirm */
+			*addr = 0x00D0;
+			/* Resume Command, as per errata update */
+			*addr = 0x00D0;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			*addr = 0x70; /*Read status register command*/
+			tmp = (short)*addr & 0x00FF; /* Read the status */
+			while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = 0x0050; /* Reset the status register */
+					*addr = 0xffff;
+					printf ("Timeout\n");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - start) > 1000) {	/* every second */
+					putc ('.');
+				}
+				udelay(100000); /* 100 ms */
+				*addr = 0x0070; /*Read status register command*/
+				tmp = (short)*addr & 0x00FF; /* Read status */
+				start = get_timer(0);
+			}
+			if( tmp & INTEL_FLASH_STATUS_ES )
+				flash_decode_status_bits(tmp);
+
+			*addr = 0x0050; /* Reset the status register */
+			*addr = 0xffff; /* Reset to read mode */
+		}
+	}
+
+
+	printf (" done\n");
+	return rcode;
+}
+
+void flash_unprotect (flash_info_t *info)
+{
+	/*We can only unprotect the whole flash at once*/
+	/*Therefore we must prevent the _flash_real_protect()*/
+	/*from re-protecting sectors, that ware protected before */
+	/*we called flash_real_protect();*/
+
+	int i;
+
+	for(i = 0; i < info->sector_count; i++)
+		info->protect[i] = 0;
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+		_flash_real_protect(info, 0, 0);
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word (flash_info_t *info, ulong dest, ulong da)
+{
+	vu_short *addr = (vu_short *)dest;
+	ulong start;
+	char csr;
+	int flag;
+	int i;
+	union {
+		u32 data32;
+		u16 data16[2];
+	} data;
+
+	data.data32 = da;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((*addr & data.data16[0]) != data.data16[0]) ||
+	    ((*(addr+1) & data.data16[1]) != data.data16[1])) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for(i = 0; i < 2; i++)
+	{
+		/* Write Command */
+		*addr = 0x0010;
+
+		/* Write Data */
+		*addr = data.data16[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		flag  = 0;
+		*addr = 0x0070; /*Read statusregister command */
+		while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+			*addr = 0x0070; /*Read statusregister command */
+		}
+		if (csr & INTEL_FLASH_STATUS_PSS) {
+			printf ("CSR indicates write error (%0x) at %08lx\n",
+					csr, (ulong)addr);
+			flag = 1;
+		}
+
+		/* Clear Status Registers Command */
+		*addr = 0x0050;
+		/* Reset to read array mode */
+		*addr = 0xffff;
+		addr++;
+	}
+
+	return (flag);
+}
+
+int flash_real_protect(flash_info_t *info, long offset, int prot)
+{
+	int i, idx;
+
+	for(idx = 0; idx < info->sector_count; idx++)
+		if(info->start[idx] == offset)
+			break;
+
+	if(idx==info->sector_count)
+		return -1;
+
+	if(prot == 0) {
+		/* Unprotect one sector, which means unprotect all flash
+		 * and reprotect the other protected sectors.
+		 */
+		_flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/
+		info->protect[idx] = 0;
+
+		for(i = 0; i < info->sector_count; i++)
+			if(info->protect[i])
+				_flash_real_protect(info, i, 1);
+		}
+	else {
+		/* We can protect individual sectors */
+		_flash_real_protect(info, idx, 1);
+	}
+
+	for( i = 0; i < info->sector_count; i++)
+		info->protect[i] = flash_get_protect_status(info, i);
+
+	return 0;
+}
+
+int _flash_real_protect(flash_info_t *info, long idx, int prot)
+{
+	vu_short *addr;
+	int flag;
+	ushort cmd;
+	ushort tmp;
+	ulong now, start;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		printf ("Can't change protection for unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return -1;
+	}
+
+	if(prot == 0) {
+		/*Unlock the sector*/
+		cmd = 0x00D0;
+	}
+	else {
+		/*Lock the sector*/
+		cmd = 0x0001;
+	}
+
+	addr = (vu_short *)(info->start[idx]);
+
+	/* If chip is busy, wait for it */
+	start = get_timer(0);
+	*addr = 0x0070; /*Read status register command*/
+	tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
+	while(!(tmp & INTEL_FLASH_STATUS_WSMS)) {
+		/*Write State Machine Busy*/
+		/*Wait untill done or timeout.*/
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = 0x0050; /* Reset the status register */
+			*addr = 0xffff; /* Reset the chip */
+			printf ("TTimeout\n");
+			return 1;
+		}
+		*addr = 0x0070;
+		tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
+		start = get_timer(0);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Unlock block*/
+	*addr = 0x0060;
+
+	*addr = cmd;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+	*addr = 0x0070; /*Read status register command*/
+	tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */
+	while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
+		/* Write State Machine Busy */
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = 0x0050; /* Reset the status register */
+			*addr = 0xffff;
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - start) > 1000) {	/* every second */
+			putc ('.');
+		}
+		udelay(100000); /* 100 ms */
+		*addr = 0x70; /*Read status register command*/
+		tmp = (short)*addr & 0x00FF; /* Read status */
+		start = get_timer(0);
+	}
+	if( tmp & INTEL_FLASH_STATUS_PS )
+		flash_decode_status_bits(tmp);
+
+	*addr =0x0050; /*Clear status register*/
+
+	/* reset to read mode */
+	*addr = 0xffff;
+
+	return 0;
+}
diff --git a/u-boot/board/flagadm/u-boot.lds b/u-boot/board/flagadm/u-boot.lds
new file mode 100644
index 0000000..4a96388
--- /dev/null
+++ b/u-boot/board/flagadm/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/flagadm/u-boot.lds.debug b/u-boot/board/flagadm/u-boot.lds.debug
new file mode 100644
index 0000000..99098bf
--- /dev/null
+++ b/u-boot/board/flagadm/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/common/Makefile b/u-boot/board/freescale/common/Makefile
new file mode 100644
index 0000000..1abd3e5
--- /dev/null
+++ b/u-boot/board/freescale/common/Makefile
@@ -0,0 +1,70 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/freescale/common)
+endif
+
+LIB	= $(obj)libfreescale.o
+
+COBJS-$(CONFIG_FSL_CADMUS)	+= cadmus.o
+COBJS-$(CONFIG_FSL_VIA)		+= cds_via.o
+COBJS-$(CONFIG_FSL_PIXIS)	+= pixis.o
+COBJS-$(CONFIG_FSL_NGPIXIS)	+= ngpixis.o
+COBJS-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
+COBJS-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
+COBJS-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
+
+COBJS-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
+COBJS-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
+COBJS-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
+
+COBJS-$(CONFIG_MPC8536DS)	+= ics307_clk.o
+COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
+COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
+COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
+COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/common/cadmus.c b/u-boot/board/freescale/common/cadmus.c
new file mode 100644
index 0000000..db54bc4
--- /dev/null
+++ b/u-boot/board/freescale/common/cadmus.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CONFIG_SYS_CADMUS_BASE_REG
+#define CONFIG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+    u_char cm_ver;		/* Board version */
+    u_char cm_csr;		/* General control/status */
+    u_char cm_rst;		/* Reset control */
+    u_char cm_hsclk;		/* High speed clock */
+    u_char cm_hsxclk;		/* High speed clock extended */
+    u_char cm_led;		/* LED data */
+    u_char cm_pci;		/* PCI control/status */
+    u_char cm_dma;		/* DMA control */
+    u_char cm_reserved[248];	/* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+	if (pci1_speed == 0) {
+		return 33000000;
+	} else if (pci1_speed == 1) {
+		return 66000000;
+	} else {
+		/* Really, unknown. Be safe? */
+		return 33000000;
+	}
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	/*
+	 * PCI slot in USER bits CSR[6:7] by convention.
+	 */
+	return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	/*
+	 * PCI DUAL in CM_PCI[3]
+	 */
+	return cadmus->cm_pci & 0x10;
+}
diff --git a/u-boot/board/freescale/common/cadmus.h b/u-boot/board/freescale/common/cadmus.h
new file mode 100644
index 0000000..217ea64
--- /dev/null
+++ b/u-boot/board/freescale/common/cadmus.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif	/* __CADMUS_H_ */
diff --git a/u-boot/board/freescale/common/cds_pci_ft.c b/u-boot/board/freescale/common/cds_pci_ft.c
new file mode 100644
index 0000000..6f221af
--- /dev/null
+++ b/u-boot/board/freescale/common/cds_pci_ft.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "cadmus.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void cds_pci_fixup(void *blob)
+{
+	int node, tmp[2];
+	const char *path;
+	int len, slot, i;
+	u32 *map = NULL;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			node = fdt_path_offset(blob, path);
+			if (node >= 0) {
+				map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+			}
+		}
+	}
+
+	if (map) {
+		len /= sizeof(u32);
+
+		slot = get_pci_slot();
+
+		for (i=0;i<len;i+=7) {
+			/* We rotate the interrupt pins so that the mapping
+			 * changes depending on the slot the carrier card is in.
+			 */
+			map[3] = ((map[3] + slot - 2) % 4) + 1;
+			map+=7;
+		}
+	}
+}
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+	cds_pci_fixup(blob);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/common/cds_via.c b/u-boot/board/freescale/common/cds_via.c
new file mode 100644
index 0000000..4a63d77
--- /dev/null
+++ b/u-boot/board/freescale/common/cds_via.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+			pci_dev_t dev, struct pci_config_table *tab)
+{
+	pci_dev_t bridge;
+	unsigned int cmdstat;
+
+	/* Enable USB and IDE functions */
+	pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+	cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+
+	/*
+	 * Force the backplane P2P bridge to have a window
+	 * open from 0x00000000-0x00001fff in PCI I/O space.
+	 * This allows legacy I/O (i8259, etc) on the VIA
+	 * southbridge to be accessed.
+	 */
+	bridge = PCI_BDF(0,BRIDGE_ID,0);
+	pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+	pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+	pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+	pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+			       pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+	/*
+	 * Since the P2P window was forced to cover the fixed
+	 * legacy I/O addresses, it is necessary to manually
+	 * place the base addresses for the IDE and USB functions
+	 * within this window.
+	 */
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+			    pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+			     pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+			      pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+			     pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
diff --git a/u-boot/board/freescale/common/eeprom.h b/u-boot/board/freescale/common/eeprom.h
new file mode 100644
index 0000000..12a0789
--- /dev/null
+++ b/u-boot/board/freescale/common/eeprom.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min)	((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev)	(((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev)	((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN	MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0	MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1	MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif	/* __CADMUS_H_ */
diff --git a/u-boot/board/freescale/common/ics307_clk.c b/u-boot/board/freescale/common/ics307_clk.c
new file mode 100644
index 0000000..89d8810
--- /dev/null
+++ b/u-boot/board/freescale/common/ics307_clk.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "ics307_clk.h"
+
+#ifdef CONFIG_FSL_NGPIXIS
+#include "ngpixis.h"
+#else
+#include "pixis.h"
+#endif
+
+/* decode S[0-2] to Output Divider (OD) */
+static u8 ics307_s_to_od[] = {
+	10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/*
+ * Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it.
+ */
+static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
+{
+	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+	unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+	unsigned long rdw = cw2 & 0x7F;
+	unsigned long od = ics307_s_to_od[cw0 & 0x7];
+	unsigned long freq;
+
+	/*
+	 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
+	 *
+	 * cw0:  C1 C0 TTL F1 F0 S2 S1 S0
+	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
+	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
+	 *
+	 * R6:R0 = Reference Divider Word (RDW)
+	 * V8:V0 = VCO Divider Word (VDW)
+	 * S2:S0 = Output Divider Select (OD)
+	 * F1:F0 = Function of CLK2 Output
+	 * TTL = duty cycle
+	 * C1:C0 = internal load capacitance for cyrstal
+	 *
+	 */
+
+	freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
+
+	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+			freq);
+	return freq;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return ics307_clk_freq(
+			in_8(&pixis->sclk[0]),
+			in_8(&pixis->sclk[1]),
+			in_8(&pixis->sclk[2]));
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return ics307_clk_freq(
+			in_8(&pixis->dclk[0]),
+			in_8(&pixis->dclk[1]),
+			in_8(&pixis->dclk[2]));
+}
diff --git a/u-boot/board/freescale/common/ics307_clk.h b/u-boot/board/freescale/common/ics307_clk.h
new file mode 100644
index 0000000..db3dbc4
--- /dev/null
+++ b/u-boot/board/freescale/common/ics307_clk.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ICS_CLK_H_
+#define __ICS_CLK_H_	1
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(void);
+extern unsigned long get_board_ddr_clk(void);
+#endif
+
+#endif	/* __ICS_CLK_H_ */
diff --git a/u-boot/board/freescale/common/ngpixis.c b/u-boot/board/freescale/common/ngpixis.c
new file mode 100644
index 0000000..a135fbe
--- /dev/null
+++ b/u-boot/board/freescale/common/ngpixis.c
@@ -0,0 +1,136 @@
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard.  It contains
+ * eight "bits".  The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches.  There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ *    is used in the PIXIS_SW() macro to determine which offset in
+ *    the PIXIS register map corresponds to the physical switch that controls
+ *    the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ *    boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+
+#include "ngpixis.h"
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void pixis_reset(void)
+{
+	out_8(&pixis->rst, 0);
+
+	while (1);
+}
+
+/*
+ * Reset the board.  Like pixis_reset(), but it honors the ENx registers.
+ */
+void pixis_bank_reset(void)
+{
+	out_8(&pixis->vctl, 0);
+	out_8(&pixis->vctl, 1);
+
+	while (1);
+}
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void clear_altbank(void)
+{
+	/* Tell the ngPIXIS to use this the bits in the physical switch for the
+	 * boot bank value, instead of the SWx register.  We need to be careful
+	 * only to set the bits in SWx that correspond to the boot bank.
+	 */
+	clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void set_altbank(void)
+{
+	/* Program the alternate bank number into the SWx register.
+	 */
+	clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
+		     PIXIS_LBMAP_ALTBANK);
+
+	/* Tell the ngPIXIS to use this the bits in the SWx register for the
+	 * boot bank value, instead of the physical switch.  We need to be
+	 * careful only to set the bits in SWx that correspond to the boot bank.
+	 */
+	setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+
+int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int i;
+	char *p_altbank = NULL;
+	char *unknown_param = NULL;
+
+	/* No args is a simple reset request.
+	 */
+	if (argc <= 1)
+		pixis_reset();
+
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "altbank") == 0) {
+			p_altbank = argv[i];
+			continue;
+		}
+
+		unknown_param = argv[i];
+	}
+
+	if (unknown_param) {
+		printf("Invalid option: %s\n", unknown_param);
+		return 1;
+	}
+
+	if (p_altbank)
+		set_altbank();
+	else
+		clear_altbank();
+
+	pixis_bank_reset();
+
+	/* Shouldn't be reached. */
+	return 0;
+}
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer",
+	"- hard reset to default bank\n"
+	"pixis_reset altbank - reset to alternate bank\n"
+	);
diff --git a/u-boot/board/freescale/common/ngpixis.h b/u-boot/board/freescale/common/ngpixis.h
new file mode 100644
index 0000000..089408b
--- /dev/null
+++ b/u-boot/board/freescale/common/ngpixis.h
@@ -0,0 +1,57 @@
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/* ngPIXIS register set. Hopefully, this won't change too much over time.
+ * Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct ngpixis {
+	u8 id;
+	u8 arch;
+	u8 scver;
+	u8 csr;
+	u8 rst;
+	u8 res1;
+	u8 aux;
+	u8 spd;
+	u8 brdcfg0;
+	u8 brdcfg1;	/* On some boards, this register is called 'dma' */
+	u8 addr;
+	u8 res2[2];
+	u8 data;
+	u8 led;
+	u8 res3;
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 res4;
+	u8 ocmcsr;
+	u8 ocmmsg;
+	u8 gmdbg;
+	u8 res5[2];
+	u8 sclk[3];
+	u8 dclk[3];
+	u8 watch;
+	struct {
+		u8 sw;
+		u8 en;
+	} s[8];
+} __attribute__ ((packed)) ngpixis_t;
+
+/* Pointer to the PIXIS register set */
+#define pixis ((ngpixis_t *)PIXIS_BASE)
+
+/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_SW(x)		(pixis->s[(x) - 1].sw)
+
+/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_EN(x)		(pixis->s[(x) - 1].en)
diff --git a/u-boot/board/freescale/common/pixis.c b/u-boot/board/freescale/common/pixis.c
new file mode 100644
index 0000000..a35b5cf
--- /dev/null
+++ b/u-boot/board/freescale/common/pixis.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright 2006,2010 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#define pixis_base (u8 *)PIXIS_BASE
+
+/*
+ * Simple board reset.
+ */
+void pixis_reset(void)
+{
+	out_8(pixis_base + PIXIS_RST, 0);
+
+	while (1);
+}
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+static int set_px_sysclk(unsigned long sysclk)
+{
+	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+	switch (sysclk) {
+	case 33:
+		sysclk_s = 0x04;
+		sysclk_r = 0x04;
+		sysclk_v = 0x07;
+		sysclk_aux = 0x00;
+		break;
+	case 40:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x20;
+		sysclk_aux = 0x01;
+		break;
+	case 50:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x2A;
+		sysclk_aux = 0x02;
+		break;
+	case 66:
+		sysclk_s = 0x01;
+		sysclk_r = 0x04;
+		sysclk_v = 0x04;
+		sysclk_aux = 0x03;
+		break;
+	case 83:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x04;
+		break;
+	case 100:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x5C;
+		sysclk_aux = 0x05;
+		break;
+	case 134:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x3B;
+		sysclk_aux = 0x06;
+		break;
+	case 166:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x07;
+		break;
+	default:
+		printf("Unsupported SYSCLK frequency.\n");
+		return 0;
+	}
+
+	vclkh = (sysclk_s << 5) | sysclk_r;
+	vclkl = sysclk_v;
+
+	out_8(pixis_base + PIXIS_VCLKH, vclkh);
+	out_8(pixis_base + PIXIS_VCLKL, vclkl);
+
+	out_8(pixis_base + PIXIS_AUX, sysclk_aux);
+
+	return 1;
+}
+
+/* Set the CFG_SYSPLL bits
+ *
+ * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
+ * read_from_px_regs() is called.
+ */
+static int set_px_mpxpll(unsigned long mpxpll)
+{
+	switch (mpxpll) {
+	case 2:
+	case 4:
+	case 6:
+	case 8:
+	case 10:
+	case 12:
+	case 14:
+	case 16:
+		clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
+		return 1;
+	}
+
+	printf("Unsupported MPXPLL ratio.\n");
+	return 0;
+}
+
+static int set_px_corepll(unsigned long corepll)
+{
+	u8 val;
+
+	switch (corepll) {
+	case 20:
+		val = 0x08;
+		break;
+	case 25:
+		val = 0x0C;
+		break;
+	case 30:
+		val = 0x10;
+		break;
+	case 35:
+		val = 0x1C;
+		break;
+	case 40:
+		val = 0x14;
+		break;
+	case 45:
+		val = 0x0E;
+		break;
+	default:
+		printf("Unsupported COREPLL ratio.\n");
+		return 0;
+	}
+
+	clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
+	return 1;
+}
+
+#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
+#endif
+
+/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or various other PIXIS registers to determine the values for COREPLL,
+ * MPXPLL, and SYSCLK.
+ *
+ * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * register that tells the pixis to use the various PIXIS register.
+ */
+static void read_from_px_regs(int set)
+{
+	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
+
+	if (set)
+		tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+	else
+		tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+
+	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
+}
+
+/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+ * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
+#define CONFIG_SYS_PIXIS_VBOOT_ENABLE	0x04
+#endif
+
+/* Configure the source of the boot location
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or the PX_VBOOT[LBMAP] register to determine where we should boot.
+ *
+ * If we want to boot from the alternate boot bank, we need to tell the PIXIS
+ * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
+ */
+static void read_from_px_regs_altbank(int set)
+{
+	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
+
+	if (set)
+		tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+	else
+		tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+
+	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
+}
+
+/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+ * tells the PIXIS what the alternate flash bank is.
+ *
+ * Note that it's not really a mask.  It contains the actual LBMAP bits that
+ * must be set to select the alternate bank.  This code assumes that the
+ * primary bank has these bits set to 0, and the alternate bank has these
+ * bits set to 1.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
+#endif
+
+/* Tell the PIXIS to boot from the default flash bank
+ *
+ * Program the default flash bank into the VBOOT register.  This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void clear_altbank(void)
+{
+	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+}
+
+/* Tell the PIXIS to boot from the alternate flash bank
+ *
+ * Program the alternate flash bank into the VBOOT register.  This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void set_altbank(void)
+{
+	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+}
+
+/* Reset the board with watchdog disabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go(void)
+{
+	/* Disable the VELA sequencer and watchdog */
+	clrbits_8(pixis_base + PIXIS_VCTL, 9);
+
+	/* Reboot by starting the VELA sequencer */
+	setbits_8(pixis_base + PIXIS_VCTL, 0x1);
+
+	while (1);
+}
+
+/* Reset the board with watchdog enabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go_with_watchdog(void)
+{
+	/* Disable the VELA sequencer */
+	clrbits_8(pixis_base + PIXIS_VCTL, 1);
+
+	/* Enable the watchdog and reboot by starting the VELA sequencer */
+	setbits_8(pixis_base + PIXIS_VCTL, 0x9);
+
+	while (1);
+}
+
+/* Disable the watchdog
+ *
+ */
+static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+				      char * const argv[])
+{
+	/* Disable the VELA sequencer and the watchdog */
+	clrbits_8(pixis_base + PIXIS_VCTL, 9);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	diswd, 1, 0, pixis_disable_watchdog_cmd,
+	"Disable watchdog timer",
+	""
+);
+
+#ifdef CONFIG_PIXIS_SGMII_CMD
+
+/* Enable or disable SGMII mode for a TSEC
+ */
+static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int which_tsec = -1;
+	unsigned char mask;
+	unsigned char switch_mask;
+
+	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
+		which_tsec = simple_strtoul(argv[1], NULL, 0);
+
+	switch (which_tsec) {
+#ifdef CONFIG_TSEC1
+	case 1:
+		mask = PIXIS_VSPEED2_TSEC1SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC1SER;
+		break;
+#endif
+#ifdef CONFIG_TSEC2
+	case 2:
+		mask = PIXIS_VSPEED2_TSEC2SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC2SER;
+		break;
+#endif
+#ifdef CONFIG_TSEC3
+	case 3:
+		mask = PIXIS_VSPEED2_TSEC3SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC3SER;
+		break;
+#endif
+#ifdef CONFIG_TSEC4
+	case 4:
+		mask = PIXIS_VSPEED2_TSEC4SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC4SER;
+		break;
+#endif
+	default:
+		mask = PIXIS_VSPEED2_MASK;
+		switch_mask = PIXIS_VCFGEN1_MASK;
+		break;
+	}
+
+	/* Toggle whether the switches or FPGA control the settings */
+	if (!strcmp(argv[argc - 1], "switch"))
+		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
+	else
+		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
+
+	/* If it's not the switches, enable or disable SGMII, as specified */
+	if (!strcmp(argv[argc - 1], "on"))
+		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
+	else if (!strcmp(argv[argc - 1], "off"))
+		setbits_8(pixis_base + PIXIS_VSPEED2, mask);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
+	"pixis_set_sgmii"
+	" - Enable or disable SGMII mode for a given TSEC \n",
+	"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
+	"    TSEC num: 1,2,3,4 or 'all'.  'all' is default.\n"
+	"    on - enables SGMII\n"
+	"    off - disables SGMII\n"
+	"    switch - use switch settings"
+);
+
+#endif
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+static unsigned long strfractoint(char *strptr)
+{
+	int i, j;
+	int mulconst;
+	int intarr_len, no_dec = 0;
+	unsigned long intval = 0, decval = 0;
+	char intarr[3], decarr[3];
+
+	/* Assign the integer part to intarr[]
+	 * If there is no decimal point i.e.
+	 * if the ratio is an integral value
+	 * simply create the intarr.
+	 */
+	i = 0;
+	while (strptr[i] != '.') {
+		if (strptr[i] == 0) {
+			no_dec = 1;
+			break;
+		}
+		intarr[i] = strptr[i];
+		i++;
+	}
+
+	/* Assign length of integer part to intarr_len. */
+	intarr_len = i;
+	intarr[i] = '\0';
+
+	if (no_dec) {
+		/* Currently needed only for single digit corepll ratios */
+		mulconst = 10;
+		decval = 0;
+	} else {
+		j = 0;
+		i++;		/* Skipping the decimal point */
+		while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
+			decarr[j] = strptr[i];
+			i++;
+			j++;
+		}
+
+		decarr[j] = '\0';
+
+		mulconst = 1;
+		for (i = 0; i < j; i++)
+			mulconst *= 10;
+		decval = simple_strtoul(decarr, NULL, 10);
+	}
+
+	intval = simple_strtoul(intarr, NULL, 10);
+	intval = intval * mulconst;
+
+	return intval + decval;
+}
+
+static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int i;
+	char *p_cf = NULL;
+	char *p_cf_sysclk = NULL;
+	char *p_cf_corepll = NULL;
+	char *p_cf_mpxpll = NULL;
+	char *p_altbank = NULL;
+	char *p_wd = NULL;
+	int unknown_param = 0;
+
+	/*
+	 * No args is a simple reset request.
+	 */
+	if (argc <= 1) {
+		pixis_reset();
+		/* not reached */
+	}
+
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "cf") == 0) {
+			p_cf = argv[i];
+			if (i + 3 >= argc) {
+				break;
+			}
+			p_cf_sysclk = argv[i+1];
+			p_cf_corepll = argv[i+2];
+			p_cf_mpxpll = argv[i+3];
+			i += 3;
+			continue;
+		}
+
+		if (strcmp(argv[i], "altbank") == 0) {
+			p_altbank = argv[i];
+			continue;
+		}
+
+		if (strcmp(argv[i], "wd") == 0) {
+			p_wd = argv[i];
+			continue;
+		}
+
+		unknown_param = 1;
+	}
+
+	/*
+	 * Check that cf has all required parms
+	 */
+	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
+	    ||	unknown_param) {
+#ifdef CONFIG_SYS_LONGHELP
+		puts(cmdtp->help);
+#endif
+		return 1;
+	}
+
+	/*
+	 * PIXIS seems to be sensitive to the ordering of
+	 * the registers that are touched.
+	 */
+	read_from_px_regs(0);
+
+	if (p_altbank)
+		read_from_px_regs_altbank(0);
+
+	clear_altbank();
+
+	/*
+	 * Clock configuration specified.
+	 */
+	if (p_cf) {
+		unsigned long sysclk;
+		unsigned long corepll;
+		unsigned long mpxpll;
+
+		sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
+		corepll = strfractoint(p_cf_corepll);
+		mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
+
+		if (!(set_px_sysclk(sysclk)
+		      && set_px_corepll(corepll)
+		      && set_px_mpxpll(mpxpll))) {
+#ifdef CONFIG_SYS_LONGHELP
+			puts(cmdtp->help);
+#endif
+			return 1;
+		}
+		read_from_px_regs(1);
+	}
+
+	/*
+	 * Altbank specified
+	 *
+	 * NOTE CHANGE IN BEHAVIOR: previous code would default
+	 * to enabling watchdog if altbank is specified.
+	 * Now the watchdog must be enabled explicitly using 'wd'.
+	 */
+	if (p_altbank) {
+		set_altbank();
+		read_from_px_regs_altbank(1);
+	}
+
+	/*
+	 * Reset with watchdog specified.
+	 */
+	if (p_wd)
+		set_px_go_with_watchdog();
+	else
+		set_px_go();
+
+	/*
+	 * Shouldn't be reached.
+	 */
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer",
+	"    pixis_reset\n"
+	"    pixis_reset [altbank]\n"
+	"    pixis_reset altbank wd\n"
+	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
+);
diff --git a/u-boot/board/freescale/common/pixis.h b/u-boot/board/freescale/common/pixis.h
new file mode 100644
index 0000000..7f86de7
--- /dev/null
+++ b/u-boot/board/freescale/common/pixis.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __PIXIS_H_
+#define __PIXIS_H_	1
+
+/* PIXIS register set. */
+#if defined(CONFIG_MPC8536DS)
+typedef struct pixis {
+	u8 id;
+	u8 ver;
+	u8 pver;
+	u8 csr;
+	u8 rst;
+	u8 rst2;
+	u8 aux1;
+	u8 spd;
+	u8 aux2;
+	u8 csr2;
+	u8 watch;
+	u8 led;
+	u8 pwr;
+	u8 res[3];
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 vcfgen1;
+	u8 vcore0;
+	u8 res1;
+	u8 vboot;
+	u8 vspeed[3];
+	u8 sclk[3];
+	u8 dclk[3];
+	u8 i2cdacr;
+	u8 vcoreacc[4];
+	u8 vcorecnt[3];
+	u8 vcoremax[2];
+	u8 vplatacc[4];
+	u8 vplatcnt[3];
+	u8 vplatmax[2];
+	u8 vtempacc[4];
+	u8 vtempcnt[3];
+	u8 vtempmax[2];
+	u8 res2[4];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8544DS)
+typedef struct pixis {
+	u8 id;
+	u8 ver;
+	u8 pver;
+	u8 csr;
+	u8 rst;
+	u8 pwr;
+	u8 aux1;
+	u8 spd;
+	u8 res[8];
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 vcfgen1;
+	u8 vcore0;
+	u8 res1;
+	u8 vboot;
+	u8 vspeed[2];
+	u8 vclkh;
+	u8 vclkl;
+	u8 watch;
+	u8 led;
+	u8 vspeed2;
+	u8 res2[34];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8572DS)
+typedef struct pixis {
+	u8 id;
+	u8 ver;
+	u8 pver;
+	u8 csr;
+	u8 rst;
+	u8 pwr1;
+	u8 aux1;
+	u8 spd;
+	u8 aux2;
+	u8 res[7];
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 vcfgen1;
+	u8 vcore0;
+	u8 res1;
+	u8 vboot;
+	u8 vspeed[3];
+	u8 res2[2];
+	u8 sclk[3];
+	u8 dclk[3];
+	u8 res3[2];
+	u8 watch;
+	u8 led;
+	u8 res4[25];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8610HPCD)
+typedef struct pixis {
+	u8 id;
+	u8 ver;	/* also called arch */
+	u8 pver;
+	u8 csr;
+	u8 rst;
+	u8 pwr;
+	u8 aux;
+	u8 spd;
+	u8 brdcfg0;
+	u8 brdcfg1;
+	u8 res[4];
+	u8 led;
+	u8 serno;
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 vcfgen1;
+	u8 vcore0;
+	u8 res1;
+	u8 vboot;
+	u8 vspeed[2];
+	u8 res2;
+	u8 sclk[3];
+	u8 res3;
+	u8 watch;
+	u8 res4[33];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8641HPCN)
+typedef struct pixis {
+	u8 id;
+	u8 ver;
+	u8 pver;
+	u8 csr;
+	u8 rst;
+	u8 pwr;
+	u8 aux;
+	u8 spd;
+	u8 res[8];
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 vcfgen1;
+	u8 vcore0;
+	u8 res1;
+	u8 vboot;
+	u8 vspeed[2];
+	u8 vclkh;
+	u8 vclkl;
+	u8 watch;
+	u8 res3[36];
+} __attribute__ ((packed)) pixis_t;
+#else
+#error Need to define pixis_t for this board
+#endif
+
+/* Pointer to the PIXIS register set */
+#define pixis ((pixis_t *)PIXIS_BASE)
+
+#endif	/* __PIXIS_H_ */
diff --git a/u-boot/board/freescale/common/pq-mds-pib.c b/u-boot/board/freescale/common/pq-mds-pib.c
new file mode 100644
index 0000000..5f7a67d
--- /dev/null
+++ b/u-boot/board/freescale/common/pq-mds-pib.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Tony Li <tony.li@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "pq-mds-pib.h"
+
+int pib_init(void)
+{
+	u8 val8;
+	u8 orig_i2c_bus;
+
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0;
+#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
+	/* Assign PIB PMC slot to desired PCI bus */
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(CONFIG_MPC832XEMDS)
+	val8 = 0xf9;            /* PMC2, PMC3 slot to PCI bus */
+#else
+	val8 = 0xf3;		/* PMC1, PMC2, PMC3 slot to PCI bus */
+#endif
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+
+	eieio();
+
+#if defined(CONFIG_MPC832XEMDS)
+	printf("PCI 32bit bus on PMC2 &PMC3\n");
+#else
+	printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
+#endif
+#endif
+
+#if defined(CONFIG_PQ_MDS_PIB_ATM)
+#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
+	val8 = 0;
+	i2c_write(0x20, 0x6, 1, &val8, 1);
+	i2c_write(0x20, 0x7, 1, &val8, 1);
+
+	val8 = 0xdf;
+	i2c_write(0x20, 0x2, 1, &val8, 1);
+	val8 = 0xf7;
+	i2c_write(0x20, 0x3, 1, &val8, 1);
+
+	eieio();
+
+	printf("QOC3 ATM card on PMC0\n");
+#elif defined(CONFIG_MPC832XEMDS)
+	val8 = 0;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+	val8 = 0xf7;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x21, 0x6, 1, &val8, 1);
+	i2c_write(0x21, 0x7, 1, &val8, 1);
+
+	val8 = 0xdf;
+	i2c_write(0x21, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x21, 0x3, 1, &val8, 1);
+
+	eieio();
+
+	printf("QOC3 ATM card on PMC1\n");
+#endif
+#endif
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+	return 0;
+}
diff --git a/u-boot/board/freescale/common/pq-mds-pib.h b/u-boot/board/freescale/common/pq-mds-pib.h
new file mode 100644
index 0000000..67066fd
--- /dev/null
+++ b/u-boot/board/freescale/common/pq-mds-pib.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+extern int pib_init(void);
diff --git a/u-boot/board/freescale/common/sgmii_riser.c b/u-boot/board/freescale/common/sgmii_riser.c
new file mode 100644
index 0000000..4f40a1d
--- /dev/null
+++ b/u-boot/board/freescale/common/sgmii_riser.c
@@ -0,0 +1,88 @@
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <libfdt.h>
+#include <tsec.h>
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		if (tsec_info[i].flags & TSEC_SGMII)
+			tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
+}
+
+void fsl_sgmii_riser_fdt_fixup(void *fdt)
+{
+	struct eth_device *dev;
+	int node;
+	int i = -1;
+	int etsec_num = 0;
+
+	node = fdt_path_offset(fdt, "/aliases");
+	if (node < 0)
+		return;
+
+	while ((dev = eth_get_dev_by_index(++i)) != NULL) {
+		struct tsec_private *priv;
+		int enet_node;
+		char enet[16];
+		const u32 *phyh;
+		int phynode;
+		const char *model;
+		const char *path;
+
+		if (!strstr(dev->name, "eTSEC"))
+			continue;
+
+		sprintf(enet, "ethernet%d", etsec_num++);
+		path = fdt_getprop(fdt, node, enet, NULL);
+		if (!path) {
+			debug("No alias for %s\n", enet);
+			continue;
+		}
+
+		enet_node = fdt_path_offset(fdt, path);
+		if (enet_node < 0)
+			continue;
+
+		model = fdt_getprop(fdt, enet_node, "model", NULL);
+
+		/*
+		 * We only want to do this to eTSECs.  On some platforms
+		 * there are more than one type of gianfar-style ethernet
+		 * controller, and as we are creating an implicit connection
+		 * between ethernet nodes and eTSEC devices, it is best to
+		 * make the connection use as much explicit information
+		 * as exists.
+		 */
+		if (!strstr(model, "TSEC"))
+			continue;
+
+		phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
+		if (!phyh)
+			continue;
+
+		phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh));
+
+		priv = dev->priv;
+
+		if (priv->flags & TSEC_SGMII)
+			fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
+	}
+}
diff --git a/u-boot/board/freescale/common/sgmii_riser.h b/u-boot/board/freescale/common/sgmii_riser.h
new file mode 100644
index 0000000..e1fcc85
--- /dev/null
+++ b/u-boot/board/freescale/common/sgmii_riser.h
@@ -0,0 +1,16 @@
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
+void fsl_sgmii_riser_fdt_fixup(void *fdt);
diff --git a/u-boot/board/freescale/common/sys_eeprom.c b/u-boot/board/freescale/common/sys_eeprom.c
new file mode 100644
index 0000000..3ecfb06
--- /dev/null
+++ b/u-boot/board/freescale/common/sys_eeprom.c
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+#include "../common/eeprom.h"
+#define MAX_NUM_PORTS	8
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS	8
+#define NXID_VERSION	0
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS	23
+#define NXID_VERSION	1
+#endif
+
+/**
+ * static eeprom: EEPROM layout for CCID or NXID formats
+ *
+ * See application note AN3638 for details.
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+	u8 major;         /* 0x04        Board revision, major */
+	u8 minor;         /* 0x05        Board revision, minor */
+	u8 sn[10];        /* 0x06 - 0x0F Serial Number*/
+	u8 errata[2];     /* 0x10 - 0x11 Errata Level */
+	u8 date[6];       /* 0x12 - 0x17 Build Date */
+	u8 res_0[40];     /* 0x18 - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - 0x71 MAC addresses */
+	u32 crc;          /* 0x72        CRC32 checksum */
+#endif
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
+	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
+	u8 date[6];       /* 0x15 - 0x1a Build Date */
+	u8 res_0;         /* 0x1b        Reserved */
+	u32 version;      /* 0x1c - 0x1f NXID Version */
+	u8 tempcal[8];    /* 0x20 - 0x27 Temperature Calibration Factors */
+	u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+	u8 tempcalflags;  /* 0x2a        Temperature Calibration Flags */
+	u8 res_1[21];     /* 0x2b - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - x MAC addresses */
+	u32 crc;          /* x+1         CRC32 checksum */
+#endif
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read = 0;
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* Is this a valid NXID EEPROM? */
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+		  (e.id[2] == 'I') || (e.id[3] == 'D'))
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+/* Is this a valid CCID EEPROM? */
+#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \
+		  (e.id[2] == 'I') || (e.id[3] == 'D'))
+#endif
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+	int i;
+	unsigned int crc;
+
+	/* EEPROM tag ID, either CCID or NXID */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+		be32_to_cpu(e.version));
+#else
+	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
+
+	/* Serial number */
+	printf("SN: %s\n", e.sn);
+
+	/* Errata level. */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	printf("Errata: %s\n", e.errata);
+#else
+	printf("Errata: %c%c\n",
+		e.errata[0] ? e.errata[0] : '.',
+		e.errata[1] ? e.errata[1] : '.');
+#endif
+
+	/* Build date, BCD date values, as YYMMDDhhmmss */
+	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+		e.date[0], e.date[1], e.date[2],
+		e.date[3] & 0x7F, e.date[4], e.date[5],
+		e.date[3] & 0x80 ? "PM" : "");
+
+	/* Show MAC addresses  */
+	for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+
+		u8 *p = e.mac[i];
+
+		printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
+			p[0], p[1], p[2], p[3],	p[4], p[5]);
+	}
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+	if (crc == be32_to_cpu(e.crc))
+		printf("CRC: %08x\n", be32_to_cpu(e.crc));
+	else
+		printf("CRC: %08x (should be %08x)\n",
+			be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+	for (i = 0; i < sizeof(e); i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)&e)[i]);
+		if (((i % 16) == 15) || (i == sizeof(e) - 1))
+			printf("\n");
+	}
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+	int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	if (has_been_read)
+		return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+		(void *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+	show_eeprom();
+#endif
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
+}
+
+/**
+ *  update_crc - update the CRC
+ *
+ *  This function should be called after each update to the EEPROM structure,
+ *  to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+	u32 crc;
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+	e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+	int ret = 0;
+	int i;
+	void *p;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	/* Set the reserved values to 0xFF   */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	e.res_0 = 0xFF;
+	memset(e.res_1, 0xFF, sizeof(e.res_1));
+#else
+	memset(e.res_0, 0xFF, sizeof(e.res_0));
+#endif
+	update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	/*
+	 * The AT24C02 datasheet says that data can only be written in page
+	 * mode, which means 8 bytes at a time, and it takes up to 5ms to
+	 * complete a given write.
+	 */
+	for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
+		ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+			p, min((sizeof(e) - i), 8));
+		if (ret)
+			break;
+		udelay(5000);	/* 5ms write cycle timing */
+	}
+
+	if (!ret) {
+		/* Verify the write by reading back the EEPROM and comparing */
+		struct eeprom e2;
+
+		ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+		if (!ret && memcmp(&e, &e2, sizeof(e)))
+			ret = -1;
+	}
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+	if (ret) {
+		printf("Programming failed.\n");
+		has_been_read = 0;
+		return -1;
+	}
+
+	printf("Programming passed.\n");
+	return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+	if ((p >= '0') && (p <= '9'))
+		return p - '0';
+
+	if ((p >= 'A') && (p <= 'F'))
+		return (p - 'A') + 10;
+
+	if ((p >= 'a') && (p <= 'f'))
+		return (p - 'a') + 10;
+
+	return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+	unsigned int i;
+
+	if (strlen(string) != 12) {
+		printf("Usage: mac date YYMMDDhhmmss\n");
+		return;
+	}
+
+	for (i = 0; i < 6; i++)
+		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+	update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in one of the MAC address fields of the EEPROM local copy.
+ */
+static void set_mac_address(unsigned int index, const char *string)
+{
+	char *p = (char *) string;
+	unsigned int i;
+
+	if ((index >= MAX_NUM_PORTS) || !string) {
+		printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
+		return;
+	}
+
+	for (i = 0; *p && (i < 6); i++) {
+		e.mac[index][i] = simple_strtoul(p, &p, 16);
+		if (*p == ':')
+			p++;
+	}
+
+	update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd;
+
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
+
+	cmd = argv[1][0];
+
+	if (cmd == 'r') {
+		read_eeprom();
+		return 0;
+	}
+
+	if (cmd == 'i') {
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+		memcpy(e.id, "NXID", sizeof(e.id));
+		e.version = NXID_VERSION;
+#else
+		memcpy(e.id, "CCID", sizeof(e.id));
+#endif
+		update_crc();
+		return 0;
+	}
+
+	if (!is_valid) {
+		printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
+		return 0;
+	}
+
+	if (argc == 2) {
+		switch (cmd) {
+		case 's':	/* save */
+			prog_eeprom();
+			break;
+		default:
+			return cmd_usage(cmdtp);
+		}
+
+		return 0;
+	}
+
+	/* We know we have at least one parameter  */
+
+	switch (cmd) {
+	case 'n':	/* serial number */
+		memset(e.sn, 0, sizeof(e.sn));
+		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+		update_crc();
+		break;
+	case 'e':	/* errata */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+		memset(e.errata, 0, 5);
+		strncpy((char *)e.errata, argv[2], 4);
+#else
+		e.errata[0] = argv[2][0];
+		e.errata[1] = argv[2][1];
+#endif
+		update_crc();
+		break;
+	case 'd':	/* date BCD format YYMMDDhhmmss */
+		set_date(argv[2]);
+		break;
+	case 'p':	/* MAC table size */
+		e.mac_count = simple_strtoul(argv[2], NULL, 16);
+		update_crc();
+		break;
+	case '0' ... '9':	/* "mac 0" through "mac 22" */
+		set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
+		break;
+	case 'h':	/* help */
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+/**
+ * mac_read_from_eeprom - read the MAC addresses from EEPROM
+ *
+ * This function reads the MAC addresses from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ */
+int mac_read_from_eeprom(void)
+{
+	unsigned int i;
+	u32 crc;
+
+	puts("EEPROM: ");
+
+	if (read_eeprom()) {
+		printf("Read failed.\n");
+		return -1;
+	}
+
+	if (!is_valid) {
+		printf("Invalid ID (%02x %02x %02x %02x)\n",
+		       e.id[0], e.id[1], e.id[2], e.id[3]);
+		return -1;
+	}
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+	if (crc != be32_to_cpu(e.crc)) {
+		printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
+		return -1;
+	}
+
+	for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+		if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
+		    memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+			char ethaddr[18];
+			char enetvar[9];
+
+			sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+				e.mac[i][0],
+				e.mac[i][1],
+				e.mac[i][2],
+				e.mac[i][3],
+				e.mac[i][4],
+				e.mac[i][5]);
+			sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
+			/* Only initialize environment variables that are blank
+			 * (i.e. have not yet been set)
+			 */
+			if (!getenv(enetvar))
+				setenv(enetvar, ethaddr);
+		}
+	}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+		be32_to_cpu(e.version));
+#else
+	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+
+/**
+ * get_cpu_board_revision - get the CPU board revision on 85xx boards
+ *
+ * Read the EEPROM to determine the board revision.
+ *
+ * This function is called before relocation, so we need to read a private
+ * copy of the EEPROM into a local variable on the stack.
+ *
+ * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM.  The global
+ * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM,
+ * so that the SPD code will work.  This means that all pre-relocation I2C
+ * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus.  So if
+ * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when
+ * this function is called.  Oh well.
+ */
+unsigned int get_cpu_board_revision(void)
+{
+	struct board_eeprom {
+		u32 id;           /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+		u8 major;         /* 0x04        Board revision, major */
+		u8 minor;         /* 0x05        Board revision, minor */
+	} be;
+
+	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+		(void *)&be, sizeof(be));
+
+	if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
+		return MPC85XX_CPU_BOARD_REV(0, 0);
+
+	if ((be.major == 0xff) && (be.minor == 0xff))
+		return MPC85XX_CPU_BOARD_REV(0, 0);
+
+	return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
+}
+#endif
diff --git a/u-boot/board/freescale/common/via.h b/u-boot/board/freescale/common/via.h
new file mode 100644
index 0000000..77cfacc
--- /dev/null
+++ b/u-boot/board/freescale/common/via.h
@@ -0,0 +1,18 @@
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
diff --git a/u-boot/board/freescale/corenet_ds/Makefile b/u-boot/board/freescale/corenet_ds/Makefile
new file mode 100644
index 0000000..1047d78
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/Makefile
@@ -0,0 +1,56 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
+COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/corenet_ds/corenet_ds.c b/u-boot/board/freescale/corenet_ds/corenet_ds.c
new file mode 100644
index 0000000..232dc72
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/corenet_ds.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+extern void pci_of_setup(void *blob, bd_t *bd);
+
+#include "../common/ngpixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+int checkboard (void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->cpu;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	unsigned int i;
+
+	printf("Board: %sDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+	sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+#ifdef CONFIG_PHYS_64BIT
+	puts("36-bit Addressing\n");
+#endif
+
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
+	/* Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = in_8(&PIXIS_SW(3));
+	printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
+	printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
+	printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/*
+	 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
+	 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
+	 * the noise introduced by these unterminated and unused clock pairs.
+	 */
+	setbits_be32(&gur->ddrclkdr, 0x001B001B);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
+
+	set_liodns();
+	setup_portals();
+
+	return 0;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch(clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	default:
+		return "???";
+	}
+}
+
+#define NUM_SRDS_BANKS	3
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	u8 sw3;
+
+	/* Warn if the expected SERDES reference clocks don't match the
+	 * actual reference clocks.  This needs to be done after calling
+	 * p4080_erratum_serdes8(), since that function may modify the clocks.
+	 */
+	sw3 = in_8(&PIXIS_SW(3));
+	actual[0] = (sw3 & 0x40) ?
+		SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
+	actual[1] = (sw3 & 0x20) ?
+		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+	actual[2] = (sw3 & 0x10) ?
+		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/freescale/corenet_ds/ddr.c b/u-boot/board/freescale/corenet_ds/ddr.c
new file mode 100644
index 0000000..6660b01
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/ddr.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num);
+
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+extern fixed_ddr_parm_t fixed_ddr_parm_1[];
+#endif
+
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	sys_info_t sysinfo;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	unsigned int lawbar1_target_id;
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, sysinfo.freqDDRBus));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
+		   (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs,
+				fixed_ddr_parm_0[i].ddr_settings,
+				sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+			strmhz(buf, sysinfo.freqDDRBus));
+
+	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+	memcpy(&ddr_cfg_regs,
+		fixed_ddr_parm_1[i].ddr_settings,
+		sizeof(ddr_cfg_regs));
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
+#endif
+
+	/*
+	 * setup laws for DDR. If not interleaving, presuming half memory on
+	 * DDR1 and the other half on DDR2
+	 */
+	if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size,
+				 LAW_TRGT_IF_DDR_INTRLV) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+	} else {
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+		/* We require both controllers have identical DIMMs */
+		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size / 2,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+		lawbar1_target_id = LAW_TRGT_IF_DDR_2;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
+				 ddr_size / 2,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+#else
+		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+#endif
+	}
+	return ddr_size;
+}
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	int ret;
+
+	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+	if (ret) {
+		debug("DDR: failed to read SPD from address %u\n", i2c_address);
+		memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		else if (ctrl_num == 1 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS2;
+
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][30] = {
+	{
+	/*
+	 * memory controller 0
+	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
+	 * mhz| mhz|ranks|adjst| start | delay|
+	 */
+		{  0, 333,    4,    5,     7,   0xff,    2,  0},
+		{334, 400,    4,    5,     7,   0xff,    2,  0},
+		{401, 549,    4,    5,     7,   0xff,    2,  0},
+		{550, 680,    4,    5,     7,   0xff,    2,  0},
+		{681, 850,    4,    5,     7,   0xff,    2,  0},
+		{851, 1050,   4,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
+		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
+		{  0, 333,    2,    5,     7,   0xff,    2,  0},
+		{334, 400,    2,    5,     7,   0xff,    2,  0},
+		{401, 549,    2,    5,     7,   0xff,    2,  0},
+		{550, 680,    2,    5,     7,   0xff,    2,  0},
+		{681, 850,    2,    5,     7,   0xff,    2,  0},
+		{851, 1050,   2,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
+		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
+		{  0, 333,    1,    5,     7,   0xff,    2,  0},
+		{334, 400,    1,    5,     7,   0xff,    2,  0},
+		{401, 549,    1,    5,     7,   0xff,    2,  0},
+		{550, 680,    1,    5,     7,   0xff,    2,  0},
+		{681, 850,    1,    5,     7,   0xff,    2,  0}
+	},
+
+	{
+	/*
+	 * memory controller 1
+	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
+	 * mhz| mhz|ranks|adjst| start | delay|
+	 */
+		{  0, 333,    4,    5,     7,   0xff,    2,  0},
+		{334, 400,    4,    5,     7,   0xff,    2,  0},
+		{401, 549,    4,    5,     7,   0xff,    2,  0},
+		{550, 680,    4,    5,     7,   0xff,    2,  0},
+		{681, 850,    4,    5,     7,   0xff,    2,  0},
+		{851, 1050,   4,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
+		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
+		{  0, 333,    2,    5,     7,   0xff,    2,  0},
+		{334, 400,    2,    5,     7,   0xff,    2,  0},
+		{401, 549,    2,    5,     7,   0xff,    2,  0},
+		{550, 680,    2,    5,     7,   0xff,    2,  0},
+		{681, 850,    2,    5,     7,   0xff,    2,  0},
+		{851, 1050,   2,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
+		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
+		{  0, 333,    1,    5,     7,   0xff,    2,  0},
+		{334, 400,    1,    5,     7,   0xff,    2,  0},
+		{401, 549,    1,    5,     7,   0xff,    2,  0},
+		{550, 680,    1,    5,     7,   0xff,    2,  0},
+		{681, 850,    1,    5,     7,   0xff,    2,  0}
+	}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+			ddr_freq <= pbsp->datarate_mhz_high &&
+			pdimm[0].n_ranks == pbsp->n_ranks) {
+			popts->cpo_override = pbsp->cpo;
+			popts->write_data_delay = pbsp->write_data_delay;
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->wrlvl_start = pbsp->wrlvl_start;
+			popts->twoT_en = pbsp->force_2T;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 60 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+
+	/* override SPD values. rcw_2 should vary at differnt speed */
+	if (pdimm[0].n_ranks == 4) {
+		popts->rcw_override = 1;
+		popts->rcw_1 = 0x000a5a00;
+		if (ddr_freq <= 800)
+			popts->rcw_2 = 0x00000000;
+		else if (ddr_freq <= 1066)
+			popts->rcw_2 = 0x00100000;
+		else if (ddr_freq <= 1333)
+			popts->rcw_2 = 0x00200000;
+		else
+			popts->rcw_2 = 0x00300000;
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....");
+
+	if (fsl_use_spd()) {
+		puts("using SPD\n");
+		dram_size = fsl_ddr_sdram();
+	} else {
+		puts("using fixed parameters\n");
+		dram_size = fixed_sdram();
+	}
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/u-boot/board/freescale/corenet_ds/law.c b/u-boot/board/freescale/corenet_ds/law.c
new file mode 100644
index 0000000..43b4b97
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/law.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/corenet_ds/p4080ds_ddr.c b/u-boot/board/freescale/corenet_ds/p4080ds_ddr.c
new file mode 100644
index 0000000..4ad89ff
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#define DATARATE_800MHZ			800000000
+#define DATARATE_900MHZ			900000000
+#define DATARATE_1000MHZ		1000000000
+#define DATARATE_1200MHZ		1200000000
+#define DATARATE_1300MHZ		1300000000
+
+#define CONFIG_SYS_DDR_TIMING_3_1200	0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200	0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200	0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200	0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200	0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200	0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200	0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000	0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000	0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000	0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000	0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000	0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000	0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900	0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900	0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900	0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900	0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900	0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900	0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800	0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS		0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS		0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS	0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS	0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS	0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG	0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG	0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG	0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x24401031
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
+	{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
+	{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
+	{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
+	{0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+	{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
+	{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
+	{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
+	{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
+	{0, 0, NULL}
+};
diff --git a/u-boot/board/freescale/corenet_ds/pci.c b/u-boot/board/freescale/corenet_ds/pci.c
new file mode 100644
index 0000000..18a75de
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/pci.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/u-boot/board/freescale/corenet_ds/tlb.c b/u-boot/board/freescale/corenet_ds/tlb.c
new file mode 100644
index 0000000..1ae0416
--- /dev/null
+++ b/u-boot/board/freescale/corenet_ds/tlb.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_1M, 1),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/m5208evbe/Makefile b/u-boot/board/freescale/m5208evbe/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m5208evbe/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5208evbe/config.mk b/u-boot/board/freescale/m5208evbe/config.mk
new file mode 100644
index 0000000..21dece4
--- /dev/null
+++ b/u-boot/board/freescale/m5208evbe/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/u-boot/board/freescale/m5208evbe/m5208evbe.c b/u-boot/board/freescale/m5208evbe/m5208evbe.c
new file mode 100644
index 0000000..5f99e2f
--- /dev/null
+++ b/u-boot/board/freescale/m5208evbe/m5208evbe.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M5208EVBe\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+#endif
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	asm("nop");
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	asm("nop");
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	asm("nop");
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	asm("nop");
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5208evbe/u-boot.lds b/u-boot/board/freescale/m5208evbe/u-boot.lds
new file mode 100644
index 0000000..8602869
--- /dev/null
+++ b/u-boot/board/freescale/m5208evbe/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/cpu/mcf52x2/libmcf52x2.o	(.text)
+    arch/m68k/lib/libm68k.o		(.text)
+    common/dlmalloc.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m52277evb/Makefile b/u-boot/board/freescale/m52277evb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m52277evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m52277evb/config.mk b/u-boot/board/freescale/m52277evb/config.mk
new file mode 100644
index 0000000..4ed60f2
--- /dev/null
+++ b/u-boot/board/freescale/m52277evb/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/u-boot/board/freescale/m52277evb/m52277evb.c b/u-boot/board/freescale/m52277evb/m52277evb.c
new file mode 100644
index 0000000..9109edb
--- /dev/null
+++ b/u-boot/board/freescale/m52277evb/m52277evb.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M52277 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize;
+
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
+	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	__asm__("nop");
+
+	/* Issue LEMR */
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	__asm__("nop");
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	__asm__("nop");
+
+	udelay(1000);
+
+	/* Issue PALL */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	__asm__("nop");
+
+	/* Perform two refresh cycles */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	__asm__("nop");
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	__asm__("nop");
+
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
+
+	udelay(100);
+#endif
+	return (dramsize);
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m52277evb/u-boot.spa b/u-boot/board/freescale/m52277evb/u-boot.spa
new file mode 100644
index 0000000..9458aef
--- /dev/null
+++ b/u-boot/board/freescale/m52277evb/u-boot.spa
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5227x/start.o	(.text)
+    arch/m68k/cpu/mcf5227x/libmcf5227x.o	(.text)
+    arch/m68k/lib/libm68k.o		(.text)
+    lib/libgeneric.o	(.text)
+    common/cmd_mem.o		(.text)
+    common/main.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m52277evb/u-boot.stm b/u-boot/board/freescale/m52277evb/u-boot.stm
new file mode 100644
index 0000000..1ec83e9
--- /dev/null
+++ b/u-boot/board/freescale/m52277evb/u-boot.stm
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5227x/start.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5235evb/Makefile b/u-boot/board/freescale/m5235evb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m5235evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5235evb/config.mk b/u-boot/board/freescale/m5235evb/config.mk
new file mode 100644
index 0000000..2a4381a
--- /dev/null
+++ b/u-boot/board/freescale/m5235evb/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/u-boot/board/freescale/m5235evb/m5235evb.c b/u-boot/board/freescale/m5235evb/m5235evb.c
new file mode 100644
index 0000000..b9e6126
--- /dev/null
+++ b/u-boot/board/freescale/m5235evb/m5235evb.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M5235 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	u32 dramsize, i, dramclk;
+
+	/*
+	 * When booting from external Flash, the port-size is less than
+	 * the port-size of SDRAM.  In this case it is necessary to enable
+	 * Data[15:0] on Port Address/Data.
+	 */
+	gpio->par_ad =
+	    GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+	    GPIO_PAR_AD_DATAL;
+
+	/* Initialize PAR to enable SDRAM signals */
+	gpio->par_sdram =
+	    GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
+	    GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+		/* Initialize DRAM Control Register: DCR */
+		sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
+		    SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
+
+		/* Initialize DACR0 */
+		sdram->dacr0 =
+		    SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
+		    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+		asm("nop");
+
+		/* Initialize DMR0 */
+		sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+		asm("nop");
+
+		/* Set IP (bit 3) in DACR */
+		sdram->dacr0 |= SDRAMC_DARCn_IP;
+
+		/* Wait 30ns to allow banks to precharge */
+		for (i = 0; i < 5; i++) {
+			asm("nop");
+		}
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+
+		/*  Set RE (bit 15) in DACR */
+		sdram->dacr0 |= SDRAMC_DARCn_RE;
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		for (i = 0; i < 0x2000; i++) {
+			asm("nop");
+		}
+
+		/* Finish the configuration by issuing the MRS. */
+		sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+		asm("nop");
+
+		/* Write to the SDRAM Mode Register */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+	}
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5235evb/u-boot.16 b/u-boot/board/freescale/m5235evb/u-boot.16
new file mode 100644
index 0000000..d7bd10f
--- /dev/null
+++ b/u-boot/board/freescale/m5235evb/u-boot.16
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf523x/start.o		(.text)
+    arch/m68k/cpu/mcf523x/cpu_init.o	(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5235evb/u-boot.32 b/u-boot/board/freescale/m5235evb/u-boot.32
new file mode 100644
index 0000000..47ec6dc
--- /dev/null
+++ b/u-boot/board/freescale/m5235evb/u-boot.32
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf523x/start.o		(.text)
+    arch/m68k/cpu/mcf523x/cpu.o		(.text)
+    arch/m68k/cpu/mcf523x/cpu_init.o	(.text)
+    arch/m68k/cpu/mcf523x/interrupts.o	(.text)
+    arch/m68k/cpu/mcf523x/speed.o		(.text)
+    arch/m68k/lib/libm68k.o		(.text)
+    common/dlmalloc.o		(.text)
+    common/cmd_bootm.o		(.text)
+    common/cmd_flash.o		(.text)
+    common/cmd_elf.o		(.text)
+    common/cmd_mem.o		(.text)
+    common/console.o		(.text)
+    common/main.o		(.text)
+    lib/libgeneric.o	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5249evb/Makefile b/u-boot/board/freescale/m5249evb/Makefile
new file mode 100644
index 0000000..ac860c1
--- /dev/null
+++ b/u-boot/board/freescale/m5249evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5249evb/config.mk b/u-boot/board/freescale/m5249evb/config.mk
new file mode 100644
index 0000000..5b8c608
--- /dev/null
+++ b/u-boot/board/freescale/m5249evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/u-boot/board/freescale/m5249evb/m5249evb.c b/u-boot/board/freescale/m5249evb/m5249evb.c
new file mode 100644
index 0000000..894873b
--- /dev/null
+++ b/u-boot/board/freescale/m5249evb/m5249evb.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/immap.h>
+
+int checkboard (void) {
+	ulong val;
+	uchar val8;
+
+	puts ("Board: ");
+	puts("Freescale M5249EVB");
+	val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+	printf(" (Switch=%1X)\n", val8);
+
+	/*
+	 * Set LED on
+	 */
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
+
+	return 0;
+};
+
+
+phys_size_t initdram (int board_type) {
+	unsigned long	junk = 0xa5a59696;
+
+	/*
+	 *  Note:
+	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+	 */
+
+#ifdef CONFIG_SYS_FAST_CLK
+	/*
+	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CONFIG_SYS_PLL_BYPASS
+	/*
+	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+	/*
+	 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+	/*
+	 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+	 * PM=1 (continuous page mode)
+	 */
+
+	/* RE=0 (keep auto-refresh disabled while setting up registers) */
+	mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+	/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+	mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+	/** Precharge sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+	*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+	udelay(0x10); /* Allow several Precharge cycles */
+
+	/** Refresh Sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+	udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+	/** Mode Register initialization **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5249evb/u-boot.lds b/u-boot/board/freescale/m5249evb/u-boot.lds
new file mode 100644
index 0000000..d4fd705
--- /dev/null
+++ b/u-boot/board/freescale/m5249evb/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5253demo/Makefile b/u-boot/board/freescale/m5253demo/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/freescale/m5253demo/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5253demo/config.mk b/u-boot/board/freescale/m5253demo/config.mk
new file mode 100644
index 0000000..93fce15
--- /dev/null
+++ b/u-boot/board/freescale/m5253demo/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFF800000
diff --git a/u-boot/board/freescale/m5253demo/flash.c b/u-boot/board/freescale/m5253demo/flash.c
new file mode 100644
index 0000000..08f767d
--- /dev/null
+++ b/u-boot/board/freescale/m5253demo/flash.c
@@ -0,0 +1,467 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/immap.h>
+
+#ifndef CONFIG_SYS_FLASH_CFI
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x5555
+#define FLASH_CYCLE2    0x2aaa
+
+#define SYNC			__asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int write_word(flash_info_t * info, FPWV * dest, u16 data);
+void inline spin_wheel(void);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+	ulong size = 0;
+	ulong fbase = 0;
+
+	fbase = (ulong) CONFIG_SYS_FLASH_BASE;
+	flash_get_size((FPWV *) fbase, &flash_info[0]);
+	flash_get_offsets((ulong) fbase, &flash_info[0]);
+	fbase += flash_info[0].size;
+	size += flash_info[0].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+int flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int j, k;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+
+		info->start[0] = base;
+		for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
+			info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
+			info->protect[k] = 0;
+		}
+	}
+
+	return ERR_OK;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_SST6401B:
+		printf("SST39VF6401B\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	if (info->size > 0x100000) {
+		int remainder;
+
+		printf("  Size: %ld", info->size >> 20);
+
+		remainder = (info->size % 0x100000);
+		if (remainder) {
+			remainder >>= 10;
+			remainder = (int)((float)
+					  (((float)remainder / (float)1024) *
+					   10000));
+			printf(".%d ", remainder);
+		}
+
+		printf("MB in %d Sectors\n", info->sector_count);
+	} else
+		printf("  Size: %ld KB in %d Sectors\n",
+		       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	u16 value;
+
+	addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPWV) 0x00550055;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPWV) 0x00900090;	/* selects Intel or Atmel */
+
+	switch (addr[0] & 0xffff) {
+	case (u8) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		value = addr[1];
+		break;
+	default:
+		printf("Unknown Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+
+		*addr = (FPW) 0x00F000F0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+	case (u16) SST_ID_xF6401B:
+		info->flash_id += FLASH_SST6401B;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	info->sector_count = 0;
+	info->size = 0;
+	info->sector_count = CONFIG_SYS_SST_SECT;
+	info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
+
+	/* reset ID mode */
+	*addr = (FPWV) 0x00F000F0;
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	return (info->size);
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect, count;
+	ulong type, start, last;
+	int rcode = 0, flashtype = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+
+	switch (type) {
+	case FLASH_MAN_SST:
+		flashtype = 1;
+		break;
+	default:
+		type = (info->flash_id & FLASH_VENDMASK);
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	flag = disable_interrupts();
+
+	start = get_timer(0);
+	last = start;
+
+	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
+		if (prot == 0) {
+			addr = (FPWV *) info->start[0];
+
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			addr[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			*addr = 0x0030;	/* erase chip */
+
+			count = 0;
+			start = get_timer(0);
+
+			while ((*addr & 0x0080) != 0x0080) {
+				if (count++ > 0x10000) {
+					spin_wheel();
+					count = 0;
+				}
+
+				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = 0x00F0;	/* reset to read mode */
+
+					return 1;
+				}
+			}
+
+			*addr = 0x00F0;	/* reset to read mode */
+
+			printf("\b. done\n");
+
+			if (flag)
+				enable_interrupts();
+
+			return 0;
+		} else if (prot == CONFIG_SYS_SST_SECT) {
+			return 1;
+		}
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			addr = (FPWV *) (info->start[sect]);
+
+			printf(".");
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			switch (flashtype) {
+			case 1:
+				{
+					FPWV *base;	/* first address in bank */
+
+					flag = disable_interrupts();
+
+					base = (FPWV *) (CONFIG_SYS_FLASH_BASE);	/* First sector */
+
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					base[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					*addr = 0x0050;	/* erase sector */
+
+					if (flag)
+						enable_interrupts();
+
+					while ((*addr & 0x0080) != 0x0080) {
+						if (get_timer(start) >
+						    CONFIG_SYS_FLASH_ERASE_TOUT) {
+							printf("Timeout\n");
+							*addr = 0x00F0;	/* reset to read mode */
+
+							rcode = 1;
+							break;
+						}
+					}
+
+					*addr = 0x00F0;	/* reset to read mode */
+					break;
+				}
+			}	/* switch (flashtype) */
+		}
+	}
+	printf(" done\n");
+
+	if (flag)
+		enable_interrupts();
+
+	return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, count;
+	u16 data;
+	int rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	/* get lower word aligned address */
+	wp = addr;
+	port_width = sizeof(FPW);
+
+	/* handle unaligned start bytes */
+	if (wp & 1) {
+		data = *((FPWV *) wp);
+		data = (data << 8) | *src;
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		cnt -= 1;
+		src++;
+	}
+
+	while (cnt >= 2) {
+		/*
+		 * handle word aligned part
+		 */
+		count = 0;
+		data = *((FPWV *) src);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp += 2;
+		src += 2;
+		cnt -= 2;
+
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+	/* handle word aligned part */
+	if (cnt) {
+		/* handle word aligned part */
+		count = 0;
+		data = *((FPWV *) wp);
+
+		data = (data & 0x00FF) | (*src << 8);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		src++;
+		cnt -= 1;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash
+ * A word is 16 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word(flash_info_t * info, FPWV * dest, u16 data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & (u8) data) != (u8) data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (u8) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (u8) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (u8) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (u8) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	*dest++ = (u8) 0x00F000F0;	/* reset bank */
+
+	return (res);
+}
+
+void inline spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+#endif
diff --git a/u-boot/board/freescale/m5253demo/m5253demo.c b/u-boot/board/freescale/m5253demo/m5253demo.c
new file mode 100644
index 0000000..4772074
--- /dev/null
+++ b/u-boot/board/freescale/m5253demo/m5253demo.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5253 DEMO\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize = 0;
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+		u32 RC, temp;
+
+		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+		RC = (RC * 15) >> 4;
+
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+		__asm__("nop");
+
+		/* Initialize DMR0 */
+		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+		temp = (dramsize - 1) & 0xFFFC0000;
+		mbar_writeLong(MCFSIM_DMR0, temp | 1);
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+		__asm__("nop");
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+		__asm__("nop");
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
+		__asm__("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		udelay(500);
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
+		__asm__("nop");
+
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+	}
+
+	return dramsize;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
+	};
+
+	if (idereset) {
+		ata->cr = 0;	/* control reset */
+		udelay(100);
+	} else {
+		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		ata->t1 = CALC_TIMING(piotms[2][0]);
+		ata->t2w = CALC_TIMING(piotms[2][1]);
+		ata->t2r = CALC_TIMING(piotms[2][1]);
+		ata->ta = CALC_TIMING(piotms[2][8]);
+		ata->trd = CALC_TIMING(piotms[2][7]);
+		ata->t4 = CALC_TIMING(piotms[2][3]);
+		ata->t9 = CALC_TIMING(piotms[2][6]);
+
+		ata->cr = 0x40;	/* IORDY enable */
+		udelay(2000);
+		ata->cr |= 0x01;	/* IORDY enable */
+	}
+}
+#endif				/* CONFIG_CMD_IDE */
+
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/freescale/m5253demo/u-boot.lds b/u-boot/board/freescale/m5253demo/u-boot.lds
new file mode 100644
index 0000000..4f8bb20
--- /dev/null
+++ b/u-boot/board/freescale/m5253demo/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5253evbe/Makefile b/u-boot/board/freescale/m5253evbe/Makefile
new file mode 100644
index 0000000..ac860c1
--- /dev/null
+++ b/u-boot/board/freescale/m5253evbe/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5253evbe/config.mk b/u-boot/board/freescale/m5253evbe/config.mk
new file mode 100644
index 0000000..5b8c608
--- /dev/null
+++ b/u-boot/board/freescale/m5253evbe/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/u-boot/board/freescale/m5253evbe/m5253evbe.c b/u-boot/board/freescale/m5253evbe/m5253evbe.c
new file mode 100644
index 0000000..ae69f67
--- /dev/null
+++ b/u-boot/board/freescale/m5253evbe/m5253evbe.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5253 EVBE\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+		u32 RC, dramsize;
+
+		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+		RC = (RC * 15) >> 4;
+
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+		asm("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00002320);
+		asm("nop");
+
+		/* Initialize DMR0 */
+		dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
+		mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
+		asm("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00002328);
+		asm("nop");
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+		asm("nop");
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
+		asm("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		udelay(500);
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
+		asm("nop");
+
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+	}
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
+	};
+
+	if (idereset) {
+		ata->cr = 0;	/* control reset */
+		udelay(100);
+	} else {
+		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		ata->t1 = CALC_TIMING(piotms[2][0]);
+		ata->t2w = CALC_TIMING(piotms[2][1]);
+		ata->t2r = CALC_TIMING(piotms[2][1]);
+		ata->ta = CALC_TIMING(piotms[2][8]);
+		ata->trd = CALC_TIMING(piotms[2][7]);
+		ata->t4 = CALC_TIMING(piotms[2][3]);
+		ata->t9 = CALC_TIMING(piotms[2][6]);
+
+		ata->cr = 0x40;	/* IORDY enable */
+		udelay(2000);
+		ata->cr |= 0x01;	/* IORDY enable */
+	}
+}
+#endif				/* CONFIG_CMD_IDE */
diff --git a/u-boot/board/freescale/m5253evbe/u-boot.lds b/u-boot/board/freescale/m5253evbe/u-boot.lds
new file mode 100644
index 0000000..797c837
--- /dev/null
+++ b/u-boot/board/freescale/m5253evbe/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5271evb/Makefile b/u-boot/board/freescale/m5271evb/Makefile
new file mode 100644
index 0000000..ac860c1
--- /dev/null
+++ b/u-boot/board/freescale/m5271evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5271evb/config.mk b/u-boot/board/freescale/m5271evb/config.mk
new file mode 100644
index 0000000..cf6d375
--- /dev/null
+++ b/u-boot/board/freescale/m5271evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/u-boot/board/freescale/m5271evb/m5271evb.c b/u-boot/board/freescale/m5271evb/m5271evb.c
new file mode 100644
index 0000000..446f102
--- /dev/null
+++ b/u-boot/board/freescale/m5271evb/m5271evb.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard (void) {
+	puts ("Board: Freescale M5271EVB\n");
+	return 0;
+};
+
+phys_size_t initdram (int board_type) {
+
+	int i;
+
+	/* Enable Address lines 23-21 and lower 16bits of data path */
+	mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
+			MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
+			MCF_GPIO_AD_DATAL);
+
+	/* Set CS2 pin to be SD_CS0 */
+	mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
+			| MCF_GPIO_PAR_CS_PAR_CS2);
+
+	/* Configure SDRAM Control Pin Assignemnt Register */
+	mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
+			MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
+			MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
+			MCF_GPIO_SDRAM_SDCS_11);
+	asm(" nop");
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCF_SDRAMC_DCR,
+				MCF_SDRAMC_DCR_RTIM(2)
+				| MCF_SDRAMC_DCR_RC(0x2E));
+		asm(" nop");
+
+		/*
+		 * Initialize DACR0
+		 *
+		 * CASL: 01
+		 * CBM: cmd at A20, bank select bits 21 and up
+		 * PS: 32bit port size
+		 */
+		mbar_writeLong(MCF_SDRAMC_DACR0,
+				MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
+				| MCF_SDRAMC_DACRn_CASL(1)
+				| MCF_SDRAMC_DACRn_CBM(3)
+				| MCF_SDRAMC_DACRn_PS(0));
+		asm(" nop");
+
+		/* Initialize DMR0 */
+		mbar_writeLong(MCF_SDRAMC_DMR0,
+				MCF_SDRAMC_DMRn_BAM_16M
+				| MCF_SDRAMC_DMRn_V);
+		asm(" nop");
+
+		/* Set IP bit in DACR */
+		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+				| MCF_SDRAMC_DACRn_IP);
+		asm(" nop");
+
+		/* Wait at least 20ns to allow banks to precharge */
+		for (i = 0; i < 5; i++)
+			asm(" nop");
+
+		/* Write to this block to initiate precharge */
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+		asm(" nop");
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+				| MCF_SDRAMC_DACRn_RE);
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		for (i = 0; i < 2000; i++)
+			asm(" nop");
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+				| MCF_SDRAMC_DACRn_MRS);
+		asm(" nop");
+
+		/*
+		 * Write to the SDRAM Mode Register A0-A11 = 0x400
+		 *
+		 * Write Burst Mode = Programmed Burst Length
+		 * Op Mode = Standard Op
+		 * CAS Latency = 2
+		 * Burst Type = Sequential
+		 * Burst Length = 1
+		 */
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+		asm(" nop");
+	}
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void) {
+
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5271evb/u-boot.lds b/u-boot/board/freescale/m5271evb/u-boot.lds
new file mode 100644
index 0000000..9878ec1
--- /dev/null
+++ b/u-boot/board/freescale/m5271evb/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+GROUP(libgcc.o)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5272c3/Makefile b/u-boot/board/freescale/m5272c3/Makefile
new file mode 100644
index 0000000..ac860c1
--- /dev/null
+++ b/u-boot/board/freescale/m5272c3/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5272c3/config.mk b/u-boot/board/freescale/m5272c3/config.mk
new file mode 100644
index 0000000..5b8c608
--- /dev/null
+++ b/u-boot/board/freescale/m5272c3/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/u-boot/board/freescale/m5272c3/m5272c3.c b/u-boot/board/freescale/m5272c3/m5272c3.c
new file mode 100644
index 0000000..902ca3a
--- /dev/null
+++ b/u-boot/board/freescale/m5272c3/m5272c3.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+
+int checkboard (void) {
+	puts ("Board: ");
+	puts ("Freescale MCF5272C3 EVB\n");
+	return 0;
+	};
+
+phys_size_t initdram (int board_type) {
+	volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *)0) = 0;
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	};
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5272c3/u-boot.lds b/u-boot/board/freescale/m5272c3/u-boot.lds
new file mode 100644
index 0000000..8b011df
--- /dev/null
+++ b/u-boot/board/freescale/m5272c3/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5275evb/Makefile b/u-boot/board/freescale/m5275evb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m5275evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5275evb/config.mk b/u-boot/board/freescale/m5275evb/config.mk
new file mode 100644
index 0000000..5b8c608
--- /dev/null
+++ b/u-boot/board/freescale/m5275evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/u-boot/board/freescale/m5275evb/m5275evb.c b/u-boot/board/freescale/m5275evb/m5275evb.c
new file mode 100644
index 0000000..35c9b20
--- /dev/null
+++ b/u-boot/board/freescale/m5275evb/m5275evb.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+#define PERIOD		13	/* system bus period in ns */
+#define SDRAM_TREFI	7800	/* in ns */
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5275 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+	gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+
+	/* Set up chip select */
+	sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
+	sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+
+	/* Set up timing */
+	sdp->sdcfg1 = 0x83711630;
+	sdp->sdcfg2 = 0x46770000;
+
+	/* Enable clock */
+	sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+
+	/* Set precharge */
+	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Send LEMR */
+	sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
+			| MCF_SDRAMC_SDMR_AD(0x0)
+			| MCF_SDRAMC_SDMR_CMD;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Send LMR */
+	sdp->sdmr = 0x058d0000;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Stop sending commands */
+	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+
+	/* Set precharge */
+	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Stop manual precharge, send 2 IREF */
+	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
+	sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Write mode register, clear reset DLL */
+	sdp->sdmr = 0x018d0000;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Stop sending commands */
+	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+
+	/* Turn on auto refresh, lock SDMR */
+	sdp->sdcr =
+		MCF_SDRAMC_SDCR_CKE
+		| MCF_SDRAMC_SDCR_REF
+		| MCF_SDRAMC_SDCR_MUX(1)
+		/* 1 added to round up */
+		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+		| MCF_SDRAMC_SDCR_DQS_OE(0x3);
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5275evb/u-boot.lds b/u-boot/board/freescale/m5275evb/u-boot.lds
new file mode 100644
index 0000000..cd17b0a
--- /dev/null
+++ b/u-boot/board/freescale/m5275evb/u-boot.lds
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/string.o	(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+    .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5282evb/Makefile b/u-boot/board/freescale/m5282evb/Makefile
new file mode 100644
index 0000000..ac860c1
--- /dev/null
+++ b/u-boot/board/freescale/m5282evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5282evb/config.mk b/u-boot/board/freescale/m5282evb/config.mk
new file mode 100644
index 0000000..882f93a
--- /dev/null
+++ b/u-boot/board/freescale/m5282evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFFE00000
diff --git a/u-boot/board/freescale/m5282evb/m5282evb.c b/u-boot/board/freescale/m5282evb/m5282evb.c
new file mode 100644
index 0000000..b0c9fc8
--- /dev/null
+++ b/u-boot/board/freescale/m5282evb/m5282evb.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+	puts ("Board: Freescale M5282EVB Evaluation Board\n");
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	u32 dramsize, i, dramclk;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
+	{
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+		/* Initialize DRAM Control Register: DCR */
+		MCFSDRAMC_DCR = (0
+			| MCFSDRAMC_DCR_RTIM_6
+			| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
+		asm("nop");
+
+		/* Initialize DACR0 */
+		MCFSDRAMC_DACR0 = (0
+			| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+			| MCFSDRAMC_DACR_CASL(1)
+			| MCFSDRAMC_DACR_CBM(3)
+			| MCFSDRAMC_DACR_PS_32);
+		asm("nop");
+
+		/* Initialize DMR0 */
+		MCFSDRAMC_DMR0 = (0
+			| ((dramsize - 1) & 0xFFFC0000)
+			| MCFSDRAMC_DMR_V);
+		asm("nop");
+
+		/* Set IP (bit 3) in DACR */
+		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+		asm("nop");
+
+		/* Wait 30ns to allow banks to precharge */
+		for (i = 0; i < 5; i++) {
+			asm ("nop");
+		}
+
+		/* Write to this block to initiate precharge */
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+		asm("nop");
+
+		/* Set RE (bit 15) in DACR */
+		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+		asm("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		for (i = 0; i < 2000; i++) {
+			asm(" nop");
+		}
+
+		/* Finish the configuration by issuing the IMRS. */
+		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+		asm("nop");
+
+		/* Write to the SDRAM Mode Register */
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+	}
+	return dramsize;
+}
diff --git a/u-boot/board/freescale/m5282evb/u-boot.lds b/u-boot/board/freescale/m5282evb/u-boot.lds
new file mode 100644
index 0000000..5ad0fad
--- /dev/null
+++ b/u-boot/board/freescale/m5282evb/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/string.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+    .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m53017evb/Makefile b/u-boot/board/freescale/m53017evb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m53017evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m53017evb/config.mk b/u-boot/board/freescale/m53017evb/config.mk
new file mode 100644
index 0000000..21dece4
--- /dev/null
+++ b/u-boot/board/freescale/m53017evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/u-boot/board/freescale/m53017evb/m53017evb.c b/u-boot/board/freescale/m53017evb/m53017evb.c
new file mode 100644
index 0000000..f331786
--- /dev/null
+++ b/u-boot/board/freescale/m53017evb/m53017evb.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M53017EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+#endif
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	asm("nop");
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	asm("nop");
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	asm("nop");
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	asm("nop");
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m53017evb/u-boot.lds b/u-boot/board/freescale/m53017evb/u-boot.lds
new file mode 100644
index 0000000..2e002ad
--- /dev/null
+++ b/u-boot/board/freescale/m53017evb/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf532x/start.o		(.text)
+    arch/m68k/cpu/mcf532x/libmcf532x.o	(.text)
+    arch/m68k/lib/libm68k.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5329evb/Makefile b/u-boot/board/freescale/m5329evb/Makefile
new file mode 100644
index 0000000..f8699fc
--- /dev/null
+++ b/u-boot/board/freescale/m5329evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5329evb/config.mk b/u-boot/board/freescale/m5329evb/config.mk
new file mode 100644
index 0000000..21dece4
--- /dev/null
+++ b/u-boot/board/freescale/m5329evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/u-boot/board/freescale/m5329evb/m5329evb.c b/u-boot/board/freescale/m5329evb/m5329evb.c
new file mode 100644
index 0000000..b4df22f
--- /dev/null
+++ b/u-boot/board/freescale/m5329evb/m5329evb.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5329 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5329evb/nand.c b/u-boot/board/freescale/m5329evb/nand.c
new file mode 100644
index 0000000..16025f9
--- /dev/null
+++ b/u-boot/board/freescale/m5329evb/nand.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE		0x10
+#define SET_ALE		0x08
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
+			*nCE |= 0x0004;
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= SET_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= SET_ALE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/*
+	 * set up pin configuration - enabled 2nd output buffer's signals
+	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+	 * to use nCE signal
+	 */
+	gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
+	gpio->pddr_timer |= 0x08;
+	gpio->ppd_timer |= 0x08;
+	gpio->pclrr_timer = 0;
+	gpio->podr_timer = 0;
+
+	nand->chip_delay = 60;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_hwcontrol;
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/freescale/m5329evb/u-boot.lds b/u-boot/board/freescale/m5329evb/u-boot.lds
new file mode 100644
index 0000000..ba7ca27
--- /dev/null
+++ b/u-boot/board/freescale/m5329evb/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf532x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m5373evb/Makefile b/u-boot/board/freescale/m5373evb/Makefile
new file mode 100644
index 0000000..f8699fc
--- /dev/null
+++ b/u-boot/board/freescale/m5373evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m5373evb/config.mk b/u-boot/board/freescale/m5373evb/config.mk
new file mode 100644
index 0000000..21dece4
--- /dev/null
+++ b/u-boot/board/freescale/m5373evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/u-boot/board/freescale/m5373evb/m5373evb.c b/u-boot/board/freescale/m5373evb/m5373evb.c
new file mode 100644
index 0000000..376de4b
--- /dev/null
+++ b/u-boot/board/freescale/m5373evb/m5373evb.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5373 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m5373evb/nand.c b/u-boot/board/freescale/m5373evb/nand.c
new file mode 100644
index 0000000..df8c03b
--- /dev/null
+++ b/u-boot/board/freescale/m5373evb/nand.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE		0x10
+#define SET_ALE		0x08
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
+			*nCE |= 0x0004;
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= SET_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= SET_ALE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	fbcs->csmr2 &= ~FBCS_CSMR_WP;
+
+	/*
+	 * set up pin configuration - enabled 2nd output buffer's signals
+	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+	 * to use nCE signal
+	 */
+	gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
+	gpio->pddr_timer |= 0x08;
+	gpio->ppd_timer |= 0x08;
+	gpio->pclrr_timer = 0;
+	gpio->podr_timer = 0;
+
+	nand->chip_delay = 60;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_hwcontrol;
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/freescale/m5373evb/u-boot.lds b/u-boot/board/freescale/m5373evb/u-boot.lds
new file mode 100644
index 0000000..a2540bb
--- /dev/null
+++ b/u-boot/board/freescale/m5373evb/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf532x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m54451evb/Makefile b/u-boot/board/freescale/m54451evb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m54451evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m54451evb/config.mk b/u-boot/board/freescale/m54451evb/config.mk
new file mode 100644
index 0000000..4ed60f2
--- /dev/null
+++ b/u-boot/board/freescale/m54451evb/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/u-boot/board/freescale/m54451evb/m54451evb.c b/u-boot/board/freescale/m54451evb/m54451evb.c
new file mode 100644
index 0000000..088c8c4
--- /dev/null
+++ b/u-boot/board/freescale/m54451evb/m54451evb.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Freescale M54451 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize;
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
+	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
+	    (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+		return dramsize;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	udelay(200);
+
+	/* Issue PALL */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	__asm__("nop");
+
+	/* Perform two refresh cycles */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	__asm__("nop");
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	__asm__("nop");
+
+	/* Issue LEMR */
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	__asm__("nop");
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	__asm__("nop");
+
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+
+	udelay(100);
+#endif
+	return (dramsize);
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/freescale/m54451evb/u-boot.spa b/u-boot/board/freescale/m54451evb/u-boot.spa
new file mode 100644
index 0000000..bd86a45
--- /dev/null
+++ b/u-boot/board/freescale/m54451evb/u-boot.spa
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5445x/start.o		(.text)
+    arch/m68k/cpu/mcf5445x/libmcf5445x.o	(.text)
+    arch/m68k/lib/libm68k.o		(.text)
+    common/cmd_flash.o		(.text)
+    common/dlmalloc.o		(.text)
+    common/main.o		(.text)
+    common/image.o		(.text)
+    lib/libgeneric.o	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m54451evb/u-boot.stm b/u-boot/board/freescale/m54451evb/u-boot.stm
new file mode 100644
index 0000000..e64a56c
--- /dev/null
+++ b/u-boot/board/freescale/m54451evb/u-boot.stm
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5445x/start.o		(.text)
+/*    arch/m68k/cpu/mcf5445x/cpu_init.o		(.text)
+    arch/m68k/cpu/mcf5445x/cpu.o			(.text)
+    arch/m68k/cpu/mcf5445x/dspi.o			(.text)
+    arch/m68k/cpu/mcf5445x/interrupt.o		(.text)
+    arch/m68k/cpu/mcf5445x/speed.o		(.text)
+    arch/m68k/lib/board.o			(.text)
+    common/serial.o			(.text)
+    common/console.o			(.text)
+    lib/display_options.o	(.text)
+    board/freescale/m54455evb/m54455evb.o	(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+*/
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m54455evb/Makefile b/u-boot/board/freescale/m54455evb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m54455evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m54455evb/config.mk b/u-boot/board/freescale/m54455evb/config.mk
new file mode 100644
index 0000000..4ed60f2
--- /dev/null
+++ b/u-boot/board/freescale/m54455evb/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/u-boot/board/freescale/m54455evb/m54455evb.c b/u-boot/board/freescale/m54455evb/m54455evb.c
new file mode 100644
index 0000000..2a84514
--- /dev/null
+++ b/u-boot/board/freescale/m54455evb/m54455evb.c
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M54455 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize;
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
+#else
+	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
+	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+
+	/* Perform two refresh cycles */
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+	udelay(100);
+#endif
+	return (dramsize << 1);
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_CMD_IDE)
+#include <ata.h>
+
+int ide_preinit(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+	gpio->par_feci2c |=
+	    (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
+					   GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
+	gpio->par_ata |=
+	    (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+	     GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
+	     | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+	     GPIO_PAR_ATA_IORDY_IORDY);
+	gpio->par_pci |=
+	    (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile atac_t *ata = (atac_t *) MMAP_ATA;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = {
+		{70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+		{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+		{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+		{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+		{25, 70, 20, 10, 20, 5, 10, 0, 35}
+	};			/* PIO 4 */
+
+	if (idereset) {
+		ata->cr = 0;	/* control reset */
+		udelay(10000);
+	} else {
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / gd->bus_clk;	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		ata->t1 = CALC_TIMING(piotms[2][0]);
+		ata->t2w = CALC_TIMING(piotms[2][1]);
+		ata->t2r = CALC_TIMING(piotms[2][1]);
+		ata->ta = CALC_TIMING(piotms[2][8]);
+		ata->trd = CALC_TIMING(piotms[2][7]);
+		ata->t4 = CALC_TIMING(piotms[2][3]);
+		ata->t9 = CALC_TIMING(piotms[2][6]);
+
+		ata->cr = 0x40;	/* IORDY enable */
+		udelay(200000);
+		ata->cr |= 0x01;	/* IORDY enable */
+	}
+}
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf5445x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf5445x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
+
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	int sect[] = CONFIG_SYS_ATMEL_SECT;
+	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
+	int i, j, k;
+
+	if (base != CONFIG_SYS_ATMEL_BASE)
+		return 0;
+
+	info->flash_id          = 0x01000000;
+	info->portwidth         = 1;
+	info->chipwidth         = 1;
+	info->buffer_size       = 1;
+	info->erase_blk_tout    = 16384;
+	info->write_tout        = 2;
+	info->buffer_write_tout = 5;
+	info->vendor            = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
+	info->cmd_reset         = 0x00F0;
+	info->interface         = FLASH_CFI_X8;
+	info->legacy_unlock     = 0;
+	info->manufacturer_id   = (u16) ATM_MANUFACT;
+	info->device_id         = ATM_ID_LV040;
+	info->device_id2        = 0;
+
+	info->ext_addr          = 0;
+	info->cfi_version       = 0x3133;
+	info->cfi_offset        = 0x0000;
+	info->addr_unlock1      = 0x00000555;
+	info->addr_unlock2      = 0x000002AA;
+	info->name              = "CFI conformant";
+
+	info->size              = 0;
+	info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
+	info->start[0] = base;
+	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
+		info->size += sect[i] * sectsz[i];
+
+		for (j = 0; j < sect[i]; j++, k++) {
+			info->start[k + 1] = info->start[k] + sectsz[i];
+			info->protect[k] = 0;
+		}
+	}
+
+	return 1;
+}
+#endif				/* CONFIG_SYS_FLASH_CFI */
diff --git a/u-boot/board/freescale/m54455evb/u-boot.atm b/u-boot/board/freescale/m54455evb/u-boot.atm
new file mode 100644
index 0000000..ebf801a
--- /dev/null
+++ b/u-boot/board/freescale/m54455evb/u-boot.atm
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5445x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m54455evb/u-boot.int b/u-boot/board/freescale/m54455evb/u-boot.int
new file mode 100644
index 0000000..153556f
--- /dev/null
+++ b/u-boot/board/freescale/m54455evb/u-boot.int
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5445x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m54455evb/u-boot.stm b/u-boot/board/freescale/m54455evb/u-boot.stm
new file mode 100644
index 0000000..9cda102
--- /dev/null
+++ b/u-boot/board/freescale/m54455evb/u-boot.stm
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf5445x/start.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m547xevb/Makefile b/u-boot/board/freescale/m547xevb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m547xevb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m547xevb/config.mk b/u-boot/board/freescale/m547xevb/config.mk
new file mode 100644
index 0000000..93fce15
--- /dev/null
+++ b/u-boot/board/freescale/m547xevb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFF800000
diff --git a/u-boot/board/freescale/m547xevb/m547xevb.c b/u-boot/board/freescale/m547xevb/m547xevb.c
new file mode 100644
index 0000000..9f1ec38
--- /dev/null
+++ b/u-boot/board/freescale/m547xevb/m547xevb.c
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5475 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+#ifdef CONFIG_SYS_DRAMSZ1
+	u32 temp;
+#endif
+
+	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/u-boot/board/freescale/m547xevb/u-boot.lds b/u-boot/board/freescale/m547xevb/u-boot.lds
new file mode 100644
index 0000000..54bf278
--- /dev/null
+++ b/u-boot/board/freescale/m547xevb/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf547x_8x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/m548xevb/Makefile b/u-boot/board/freescale/m548xevb/Makefile
new file mode 100644
index 0000000..c454d76
--- /dev/null
+++ b/u-boot/board/freescale/m548xevb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/m548xevb/config.mk b/u-boot/board/freescale/m548xevb/config.mk
new file mode 100644
index 0000000..93fce15
--- /dev/null
+++ b/u-boot/board/freescale/m548xevb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFF800000
diff --git a/u-boot/board/freescale/m548xevb/m548xevb.c b/u-boot/board/freescale/m548xevb/m548xevb.c
new file mode 100644
index 0000000..4a2a5c7
--- /dev/null
+++ b/u-boot/board/freescale/m548xevb/m548xevb.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5485 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/u-boot/board/freescale/m548xevb/u-boot.lds b/u-boot/board/freescale/m548xevb/u-boot.lds
new file mode 100644
index 0000000..54bf278
--- /dev/null
+++ b/u-boot/board/freescale/m548xevb/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf547x_8x/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/lib/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/freescale/mpc5121ads/Makefile b/u-boot/board/freescale/mpc5121ads/Makefile
new file mode 100644
index 0000000..cded9eb
--- /dev/null
+++ b/u-boot/board/freescale/mpc5121ads/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc5121ads/README b/u-boot/board/freescale/mpc5121ads/README
new file mode 100644
index 0000000..defcd6b
--- /dev/null
+++ b/u-boot/board/freescale/mpc5121ads/README
@@ -0,0 +1,7 @@
+To configure for the current (Rev 3.x) ADS5121
+	make ads5121_config
+This will automatically include PCI, the Real Time CLock, add backup flash
+ability and set the correct frequency and memory configuration.
+
+To configure for the older Rev 2 ADS5121 type (this will not have PCI)
+	make ads5121_rev2_config
diff --git a/u-boot/board/freescale/mpc5121ads/mpc5121ads.c b/u-boot/board/freescale/mpc5121ads/mpc5121ads.c
new file mode 100644
index 0000000..b356a47
--- /dev/null
+++ b/u-boot/board/freescale/mpc5121ads/mpc5121ads.c
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <net.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN |		\
+			 CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |  	\
+			 CLOCK_SCCR2_USB1_EN | 		\
+			 CLOCK_SCCR2_USB2_EN)
+
+void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
+
+/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
+extern int mpc5121_nfc_chip;
+
+/* Control chips select signal on MPC5121ADS board */
+void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+	unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
+	u8 v;
+
+	v = in_8(csreg);
+	v |= 0x0F;
+
+	if (chip >= 0) {
+		__mpc5121_nfc_select_chip(mtd, 0);
+		v &= ~(1 << mpc5121_nfc_chip);
+	} else {
+		__mpc5121_nfc_select_chip(mtd, -1);
+	}
+
+	out_8(csreg, v);
+}
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	/*
+	 * Initialize Local Window for the CPLD registers access (CS2 selects
+	 * the CPLD chip)
+	 */
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_CPLD_BASE) |
+		CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+	sync_law(&im->sysconf.lpcs2aw);
+
+	/*
+	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
+	 *
+	 * Without this the flash identification routine fails, as it needs to issue
+	 * write commands in order to establish the device ID.
+	 */
+
+#ifdef CONFIG_MPC5121ADS_REV2
+	out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+#else
+	if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+	} else {
+		/* running from Backup flash */
+		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
+	}
+#endif
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+
+	if (SVR_MJREV (spridr) >= 2)
+		out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	return 0;
+}
+
+int is_micron(void){
+
+	ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar macaddr[6];
+	u32 brddate, macchk, ismicron;
+
+	/*
+	 * MAC address has serial number with date of manufacture
+	 * Boards made before Nov-08 #1180 use Micron memory;
+	 * 001e59 is the STx vendor #
+	 * Default is Elpida since it works for both but is slightly slower
+	 */
+	ismicron = 0;
+	if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
+		brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
+		macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
+		debug("brddate = %d\n\t", brddate);
+
+		if (macchk == 0x001e59 && brddate <= 8111180)
+			ismicron = 1;
+	} else if (brd_rev < 0x400) {
+		ismicron = 1;
+	}
+	debug("Using %s Memory settings\n\t",
+		ismicron ? "Micron" : "Elpida");
+	return(ismicron);
+}
+
+phys_size_t initdram(int board_type)
+{
+	u32 msize = 0;
+	/*
+	 * Elpida MDDRC and initialization settings are an alternative
+	 * to the Default Micron ones for all but the earliest Rev 4 boards
+	 */
+	ddr512x_config_t elpida_mddrc_config = {
+		.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+		.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+		.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+		.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
+	};
+
+	u32 elpida_init_sequence[] = {
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_EM3,
+		CONFIG_SYS_DDRCMD_EN_DLL,
+		CONFIG_SYS_ELPIDA_RES_DLL,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+		CONFIG_SYS_ELPIDA_OCD_EXIT,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP
+	};
+
+	if (is_micron()) {
+		msize = fixed_sdram(NULL, NULL, 0);
+	} else {
+		msize = fixed_sdram(&elpida_mddrc_config,
+				elpida_init_sequence,
+				sizeof(elpida_init_sequence)/sizeof(u32));
+	}
+
+	return msize;
+}
+
+int misc_init_r(void)
+{
+	u8 tmp_val;
+
+	/* Using this for DIU init before the driver in linux takes over
+	 *  Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+
+	i2c_set_bus_num(2);
+	tmp_val = 0xBF;
+	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+	tmp_val = 0x10;
+	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* Set highest Slew on 9 PATA pins */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SPDIF_TXCLK */
+	{
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+	{
+		offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static  iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard (void)
+{
+	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 spridr = in_be32(&im->sysconf.spridr);
+
+	printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
+		brd_rev, cpld_rev);
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	if (SVR_MJREV (spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/freescale/mpc7448hpc2/Makefile b/u-boot/board/freescale/mpc7448hpc2/Makefile
new file mode 100644
index 0000000..5df9d5d
--- /dev/null
+++ b/u-boot/board/freescale/mpc7448hpc2/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o tsi108_init.o
+SOBJS	:= asm_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+.PHONY: distclean
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc7448hpc2/asm_init.S b/u-boot/board/freescale/mpc7448hpc2/asm_init.S
new file mode 100644
index 0000000..b9495fd
--- /dev/null
+++ b/u-boot/board/freescale/mpc7448hpc2/asm_init.S
@@ -0,0 +1,918 @@
+/*
+ * (C) Copyright 2004-05;  Tundra Semiconductor Corp.
+ *
+ * Added automatic detect of SDC settings
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ * Maintainer tie-fei.zang@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * FILENAME: asm_init.s
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Initialization code for the Tundra Tsi108 bridge chip
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/processor.h>
+
+#include <tsi108.h>
+
+/*
+ * Build Configuration Options
+ */
+
+/* #define DISABLE_PBM		disables usage of PB Master */
+/* #define SDC_HARDCODED_INIT	config SDRAM controller with hardcoded values */
+/* #define SDC_AUTOPRECH_EN	enable SDRAM auto precharge */
+
+/*
+ * Hardcoded SDC settings
+ */
+
+#ifdef SDC_HARDCODED_INIT
+
+/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
+
+#define VAL_SD_REFRESH	(0x61A)
+#define VAL_SD_TIMING	(0x0308336b)
+#define VAL_SD_D0_CTRL	(0x07100021)	/* auto-precharge disabled */
+#define VAL_SD_D0_BAR	(0x0FE00000)	/* 512MB @ 0x00000000 */
+#define VAL_SD_D1_CTRL	(0x07100021)	/* auto-precharge disabled */
+#define VAL_SD_D1_BAR	(0x0FE00200)	/* 512MB @ 0x20000000 */
+
+#endif /* SDC_HARDCODED_INIT */
+
+/*
+ CPU Configuration:
+
+ CPU Address and Data Parity enables.
+
+#define CPU_AP
+#define CPU_DP
+*/
+
+/*
+ * Macros
+ * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
+ * expected to work correctly for the CSR space within 32KB range.
+ *
+ * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
+ * These macros are absolutely identical except their names. This difference
+ * is provided intentionally for better readable code.
+ */
+
+#define LOAD_PTR(reg,const32) \
+	addis reg,r0,const32@h; ori reg,reg,const32@l
+
+#define LOAD_U32(reg,const32) \
+	addis reg,r0,const32@h; ori reg,reg,const32@l
+
+/* LOADMEM initializes a register with the contents of a specified 32-bit
+ * memory location, usually a CSR value.
+ */
+
+#define LOAD_MEM(reg,addr32) \
+	addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
+
+#ifndef SDC_HARDCODED_INIT
+sdc_clk_sync:
+	/* MHz: 0,0,183,100,133,167,200,233 */
+	.long	0, 0, 6, 10, 8, 6, 5, 4		/* nSec */
+#endif
+
+/*
+ * board_asm_init() - early initialization function. Coded to be portable to
+ * dual-CPU configuration.
+ * Checks CPU number and performs board HW initialization if called for CPU0.
+ * Registers used: r3,r4,r5,r6,r19,r29
+ *
+ * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
+ * and the rest of the board. Current implementation demonstrates two
+ * possible ways to identify CPU number:
+ * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
+ * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
+ */
+
+	.globl board_asm_init
+board_asm_init:
+	mflr	r19	/* Save LR to be able return later. */
+	bl	icache_enable	/* Enable icache to reduce reads from flash. */
+
+/* Initialize pointer to Tsi108 register space */
+
+	LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
+	ori r4,r29,TSI108_PB_REG_OFFSET
+
+/* Check Processor Version Number */
+
+	mfspr	r3, PVR
+	rlwinm	r3,r3,16,16,23	/* get ((Processor Version Number) & 0xFF00) */
+
+	cmpli	0,0,r3,0x8000	/* MPC74xx */
+	bne	cont_brd_init
+
+	/*
+	 * For MPC744x/5x enable extended BATs[4-7]
+	 * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
+	 * to disable prefetch
+	 */
+
+	mfspr	r5, HID0
+	oris	r5, r5, 0x0080	/* Set HID0[HIGH_BAT_EN] bit #8 */
+	ori	r5, r5, 0x0380	/* Set SPD,XBSEN,SGE bits #22,23,24 */
+	mtspr	HID0, r5
+	isync
+	sync
+
+	/* Adding code to disable external interventions in MPX bus mode */
+	mfspr	r3, 1014
+	oris	r3, r3, 0x0100	/* Set the EIDIS bit in MSSCR0:  bit 7 */
+	mtspr	1014, r3
+	isync
+	sync
+
+	/* Sri: code to enable FP unit */
+	mfmsr	r3
+	ori	r3, r3, 0x2000
+	mtmsr	r3
+	isync
+	sync
+
+	/* def CONFIG_DUAL_CPU
+	 * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
+	 */
+#if(1)
+	mfspr	r3,1014		/* read MSSCR0 */
+	rlwinm.	r3,r3,27,31,31	/* get processor ID number */
+	mtspr	SPRN_PIR,r3	/* Save CPU ID */
+	sync
+	bne	init_done
+	b	do_tsi108_init
+
+cont_brd_init:
+
+	/* An alternative method of checking the processor number (in addition
+	 * to configuration using MSSCR0[ID] bit on MPC74xx).
+	 * Good for IBM PPC750FX/GX.
+	 */
+
+	lwz	r3,PB_BUS_MS_SELECT(r4)	/* read PB_ID register */
+	rlwinm.	r3,r3,24,31,31		/* get processor ID number */
+	bne init_done
+#else
+
+cont_brd_init:
+
+#endif /* CONFIG_DUAL_CPU */
+
+	/* Initialize Tsi108 chip */
+
+do_tsi108_init:
+
+	/*
+	 * Adjust HLP/Flash parameters. By default after reset the HLP port is
+	 * set to support slow devices. Better performance can be achived when
+	 * an optimal parameters are used for specific EPROM device.
+	 * NOTE: This should be performed ASAP for the emulation platform
+	 * because it has 5MHz HLP clocking.
+	 */
+
+#ifdef CONFIG_TSI108EMU
+	ori	r4,r29,TSI108_HLP_REG_OFFSET
+	LOAD_U32(r5,0x434422c0)
+	stw	r5,0x08(r4)	/* set HLP B0_CTRL0 */
+	sync
+	LOAD_U32(r5,0xd0012000)
+	stw	r5,0x0c(r4)		/* set HLP B0_CTRL1 */
+	sync
+#endif
+
+	/* Initialize PB interface. */
+
+	ori r4,r29,TSI108_PB_REG_OFFSET
+
+#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE)
+	/* Relocate (if required) Tsi108 registers. Set new value for
+	 * PB_REG_BAR:
+	 * Note we are in the 32-bit address mode.
+	 */
+	LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
+	stw	r5,PB_REG_BAR(r4)
+	andis.	r29,r5,0xFFFF
+	sync
+	ori	r4,r29,TSI108_PB_REG_OFFSET
+#endif
+
+	/* Set PB Slave configuration register */
+
+	LOAD_U32(r5,0x00002481)	/* PB_SCR: TEA enabled,AACK delay = 1 */
+	lwz	r3, PB_RSR(r4)	/* get PB bus mode */
+	xori	r3,r3,0x0001	/* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
+	rlwimi  r5,r3,14,17,17	/* for MPX: set DTI_MODE bit */
+	stw	r5,PB_SCR(r4)
+	sync
+
+	/* Configure PB Arbiter */
+
+	lwz	r5,PB_ARB_CTRL(r4)	/* Read PB Arbiter Control Register */
+	li	r3, 0x00F0		/* ARB_PIPELINE_DEP mask */
+#ifdef DISABLE_PBM
+	ori	r3,r3,0x1000	/* add PBM_EN to clear (enabled by default) */
+#endif
+	andc	r5,r5,r3	/* Clear the masked bit fields */
+	ori	r5,r5,0x0001	/* Set pipeline depth */
+	stw	r5,PB_ARB_CTRL(r4)
+
+#if (0)	/* currently using the default settings for PBM after reset */
+	LOAD_U32(r5,0x)		/* value for PB_MCR */
+	stw	r5,PB_MCR(r4)
+	sync
+
+	LOAD_U32(r5,0x)		/* value for PB_MCMD */
+	stw	r5,PB_MCMD(r4)
+	sync
+#endif
+
+	/* Disable or enable PVT based on processor bus frequency
+	 * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
+	 * 2. See if the value is < or > 133mhz (18:16 = 100)
+	 * 3. If > enable PVT
+	 */
+
+	LOAD_U32(r3,0xC0002234)
+	lwz	r3,0(r3)
+	rlwinm	r3,r3,16,29,31
+
+	cmpi	0,0,r3,0x0004
+	bgt	sdc_init
+
+#ifndef CONFIG_TSI108EMU
+	/* FIXME: Disable PB calibration control for any real Tsi108 board */
+	li	r5,0x0101	/* disable calibration control */
+	stw	r5,PB_PVT_CTRL2(r4)
+	sync
+#endif
+
+	/* Initialize SDRAM controller. */
+
+sdc_init:
+
+#ifndef SDC_HARDCODED_INIT
+	/* get SDC clock prior doing sdram controller autoconfig */
+	ori	r4,r29,TSI108_CLK_REG_OFFSET	/* r4 - ptr to CG registers */
+	lwz	r3, CG_PWRUP_STATUS(r4)		/* get CG configuration */
+	rlwinm	r3,r3,12,29,31			/* r3 - SD clk */
+	lis	r5,sdc_clk_sync@h
+	ori	r5,r5,sdc_clk_sync@l
+	/* Sri:  At this point check if r3 = 001. If yes,
+	 * the memory frequency should be same as the
+	 * MPX bus frequency
+	 */
+	cmpi	0,0,r3,0x0001
+	bne	get_nsec
+	lwz	r6, CG_PWRUP_STATUS(r4)
+	rlwinm	r6,r6,16,29,31
+	mr	r3,r6
+
+get_nsec:
+	rlwinm	r3,r3,2,0,31
+	lwzx	r9,r5,r3	/* get SD clk rate in nSec */
+	/* ATTN: r9 will be used by SPD routine */
+#endif /* !SDC_HARDCODED_INIT */
+
+	ori	r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
+
+	/* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
+
+	LOAD_U32(r5,0x00)
+	stw	r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
+#ifdef ENABLE_SDRAM_ECC
+	li	r5, 0x01
+#endif /* ENABLE_SDRAM_ECC */
+	stw	r5,SD_ECC_CTRL(r4)	/* Enable/Disable ECC */
+	sync
+
+#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
+
+	/* First read the CG_PWRUP_STATUS register to get the
+	 * memory speed from bits 22,21,20
+	 */
+
+	LOAD_U32(r3,0xC0002234)
+	lwz	r3,0(r3)
+	rlwinm	r3,r3,12,29,31
+
+	/* Now first check for 166, then 200, or default */
+
+	cmpi	0,0,r3,0x0005
+	bne	check_for_200mhz
+
+	/* set values for 166 Mhz memory speed
+	 * Set refresh rate and timing parameters
+	 */
+	LOAD_U32(r5,0x00000515)
+	stw	r5,SD_REFRESH(r4)
+	LOAD_U32(r5,0x03073368)
+	stw	r5,SD_TIMING(r4)
+	sync
+
+	/* Initialize DIMM0 control and BAR registers */
+	LOAD_U32(r5,VAL_SD_D0_CTRL)	/* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+	oris	r5,r5,0x0001		/* set auto precharge EN bit */
+#endif
+	stw	r5,SD_D0_CTRL(r4)
+	LOAD_U32(r5,VAL_SD_D0_BAR)
+	stw	r5,SD_D0_BAR(r4)
+	sync
+
+	/* Initialize DIMM1 control and BAR registers
+	 * (same as dimm 0, next 512MB, disabled)
+	 */
+	LOAD_U32(r5,VAL_SD_D1_CTRL)	/* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+	oris	r5,r5,0x0001	/* set auto precharge EN bit */
+#endif
+	stw	r5,SD_D1_CTRL(r4)
+	LOAD_U32(r5,VAL_SD_D1_BAR)
+	stw	r5,SD_D1_BAR(r4)
+	sync
+
+	b	sdc_init_done
+
+check_for_200mhz:
+
+	cmpi	0,0,r3,0x0006
+	bne	set_default_values
+
+	/* set values for 200Mhz memory speed
+	 * Set refresh rate and timing parameters
+	 */
+	LOAD_U32(r5,0x0000061a)
+	stw	r5,SD_REFRESH(r4)
+	LOAD_U32(r5,0x03083348)
+	stw	r5,SD_TIMING(r4)
+	sync
+
+	/* Initialize DIMM0 control and BAR registers */
+	LOAD_U32(r5,VAL_SD_D0_CTRL)	/* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+	oris	r5,r5,0x0001		/* set auto precharge EN bit */
+#endif
+	stw	r5,SD_D0_CTRL(r4)
+	LOAD_U32(r5,VAL_SD_D0_BAR)
+	stw	r5,SD_D0_BAR(r4)
+	sync
+
+	/* Initialize DIMM1 control and BAR registers
+	 * (same as dimm 0, next 512MB, disabled)
+	 */
+	LOAD_U32(r5,VAL_SD_D1_CTRL)	/* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+	oris	r5,r5,0x0001		/* set auto precharge EN bit */
+#endif
+	stw	r5,SD_D1_CTRL(r4)
+	LOAD_U32(r5,VAL_SD_D1_BAR)
+	stw	r5,SD_D1_BAR(r4)
+	sync
+
+	b	sdc_init_done
+
+set_default_values:
+
+	/* Set refresh rate and timing parameters */
+	LOAD_U32(r5,VAL_SD_REFRESH)
+	stw	r5,SD_REFRESH(r4)
+	LOAD_U32(r5,VAL_SD_TIMING)
+	stw	r5,SD_TIMING(r4)
+	sync
+
+	/* Initialize DIMM0 control and BAR registers */
+	LOAD_U32(r5,VAL_SD_D0_CTRL)	/* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+	oris	r5,r5,0x0001		/* set auto precharge EN bit */
+#endif
+	stw	r5,SD_D0_CTRL(r4)
+	LOAD_U32(r5,VAL_SD_D0_BAR)
+	stw	r5,SD_D0_BAR(r4)
+	sync
+
+	/* Initialize DIMM1 control and BAR registers
+	 * (same as dimm 0, next 512MB, disabled)
+	 */
+	LOAD_U32(r5,VAL_SD_D1_CTRL)	/* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+	oris	r5,r5,0x0001		/* set auto precharge EN bit */
+#endif
+	stw	r5,SD_D1_CTRL(r4)
+	LOAD_U32(r5,VAL_SD_D1_BAR)
+	stw	r5,SD_D1_BAR(r4)
+	sync
+#else /* !SDC_HARDCODED_INIT */
+	bl	tsi108_sdram_spd	/* automatically detect SDC settings */
+#endif /* SDC_HARDCODED_INIT */
+
+sdc_init_done:
+
+#ifdef DISABLE_PBM
+	LOAD_U32(r5,0x00000030)		/* PB_EN + OCN_EN */
+#else
+	LOAD_U32(r5,0x00000230)		/* PB_EN + OCN_EN + PB/OCN=80/20 */
+#endif /* DISABLE_PBM */
+
+#ifdef CONFIG_TSI108EMU
+	oris	r5,r5,0x0010		/* set EMULATION_MODE bit */
+#endif
+
+	stw	r5,SD_CTRL(r4)
+	eieio
+	sync
+
+	/* Enable SDRAM access */
+
+	oris	r5,r5,0x8000		/* start SDC: set SD_CTRL[ENABLE] bit */
+	stw	r5,SD_CTRL(r4)
+	sync
+
+wait_init_complete:
+	lwz	r5,SD_STATUS(r4)
+	andi.	r5,r5,0x0001
+	/* wait until SDRAM initialization is complete */
+	beq	wait_init_complete
+
+	/* Map SDRAM into the processor bus address space */
+
+	ori	r4,r29,TSI108_PB_REG_OFFSET
+
+	/* Setup BARs associated with direct path PB<->SDRAM */
+
+	/* PB_SDRAM_BAR1:
+	 * provides a direct path to the main system memory (cacheable SDRAM)
+	 */
+
+	/* BA=0,Size=512MB, ENable, No Addr.Translation */
+	LOAD_U32(r5, 0x00000011)
+	stw	r5,PB_SDRAM_BAR1(r4)
+	sync
+
+	/* Make sure that PB_SDRAM_BAR1 decoder is set
+	 * (to allow following immediate read from SDRAM)
+	 */
+	lwz	r5,PB_SDRAM_BAR1(r4)
+	sync
+
+	/* PB_SDRAM_BAR2:
+	 * provides non-cacheable alias (via the direct path) to main
+	 * system memory.
+	 * Size = 512MB, ENable, Addr.Translation - ON,
+	 * BA = 0x0_40000000, TA = 0x0_00000000
+	 */
+
+	LOAD_U32(r5, 0x40010011)
+	stw	r5,PB_SDRAM_BAR2(r4)
+	sync
+
+	/* Make sure that PB_SDRAM_BAR2 decoder is set
+	 * (to allow following immediate read from SDRAM)
+	 */
+	lwz	r5,PB_SDRAM_BAR2(r4)
+	sync
+
+init_done:
+
+	/* All done. Restore LR and return. */
+	mtlr	r19
+	blr
+
+#if (0)
+	/*
+	 * init_cpu1
+	 * This routine enables CPU1 on the dual-processor system.
+	 * Now there is only one processor in the system
+	 */
+
+	.global enable_cpu1
+enable_cpu1:
+
+	lis	r3,Tsi108_Base@ha	/* Get Grendel CSR Base Addr */
+	addi	r3,r3,Tsi108_Base@l
+	lwz	r3,0(r3)		/* R3 = CSR Base Addr */
+	ori	r4,r3,TSI108_PB_REG_OFFSET
+	lwz	r3,PB_ARB_CTRL(r4)	/* Read PB Arbiter Control Register */
+	ori	r3,r3,0x0200		/* Set M1_EN bit */
+	stw	r3,PB_ARB_CTRL(r4)
+
+	blr
+#endif
+
+	/*
+	 * enable_EI
+	 * Enable CPU core external interrupt
+	 */
+
+	.global	enable_EI
+enable_EI:
+	mfmsr	r3
+	ori	r3,r3,0x8000	/* set EE bit */
+	mtmsr	r3
+	blr
+
+	/*
+	 * disable_EI
+	 * Disable CPU core external interrupt
+	 */
+
+	.global disable_EI
+disable_EI:
+	mfmsr	r3
+	li	r4,-32768	/* aka "li  r4,0x8000" */
+	andc	r3,r3,r4	/* clear EE bit */
+	mtmsr	r3
+	blr
+
+#ifdef ENABLE_SDRAM_ECC
+	/* enables SDRAM ECC  */
+
+	.global	enable_ECC
+enable_ECC:
+	ori	r4,r29,TSI108_SD_REG_OFFSET
+	lwz	r3,SD_ECC_CTRL(r4)	/* Read SDRAM ECC Control Register */
+	ori	r3,r3,0x0001		/* Set ECC_EN bit */
+	stw	r3,SD_ECC_CTRL(r4)
+	blr
+
+	/*
+	 * clear_ECC_err
+	 * Clears all pending SDRAM ECC errors
+	 * (normally after SDRAM scrubbing/initialization)
+	 */
+
+	.global	clear_ECC_err
+clear_ECC_err:
+	ori r4,r29,TSI108_SD_REG_OFFSET
+	ori r3,r0,0x0030	/* ECC_UE_INT + ECC_CE_INT bits */
+	stw r3,SD_INT_STATUS(r4)
+	blr
+
+#endif /* ENABLE_SDRAM_ECC */
+
+#ifndef SDC_HARDCODED_INIT
+
+	/* SDRAM SPD Support */
+#define	SD_I2C_CTRL1	(0x400)
+#define	SD_I2C_CTRL2	(0x404)
+#define SD_I2C_RD_DATA	(0x408)
+#define SD_I2C_WR_DATA	(0x40C)
+
+	/*
+	 * SDRAM SPD Support Macros
+	 */
+
+#define SPD_DIMM0	(0x00000100)
+#define SPD_DIMM1	(0x00000200)	/* SPD_DIMM1 was 0x00000000 */
+
+#define SPD_RDIMM			(0x01)
+#define SPD_UDIMM			(0x02)
+
+#define SPD_CAS_3			0x8
+#define SPD_CAS_4			0x10
+#define SPD_CAS_5			0x20
+
+#define ERR_NO_DIMM_FOUND		(0xdb0)
+#define ERR_TRAS_FAIL			(0xdb1)
+#define ERR_TRCD_FAIL			(0xdb2)
+#define ERR_TRP_FAIL			(0xdb3)
+#define ERR_TWR_FAIL			(0xdb4)
+#define ERR_UNKNOWN_PART		(0xdb5)
+#define ERR_NRANK_INVALID		(0xdb6)
+#define ERR_DIMM_SIZE			(0xdb7)
+#define ERR_ADDR_MODE			(0xdb8)
+#define ERR_RFRSH_RATE			(0xdb9)
+#define ERR_DIMM_TYPE			(0xdba)
+#define ERR_CL_VALUE			(0xdbb)
+#define ERR_TRFC_FAIL			(0xdbc)
+
+/* READ_SPD requirements:
+ * byte - byte address in SPD device (0 - 255)
+ * r3 = will return data read from I2C Byte location
+ * r4 - unchanged (SDC base addr)
+ * r5 - clobbered in routine (I2C status)
+ * r10 - number of DDR slot where first SPD device is detected
+ */
+
+#define READ_SPD(byte_num)		\
+	addis	r3, 0, byte_num@l;	\
+	or	r3, r3, r10;		\
+	ori	r3, r3, 0x0A;		\
+	stw	r3, SD_I2C_CTRL1(r4);	\
+	li	r3, I2C_CNTRL2_START;	\
+	stw	r3, SD_I2C_CTRL2(r4);	\
+	eieio;				\
+	sync;				\
+	li	r3, 0x100;		\
+1:;					\
+	addic.	r3, r3, -1;		\
+	bne	1b;			\
+2:;					\
+	lwz	r5, SD_I2C_CTRL2(r4);	\
+	rlwinm.	r3,r5,0,23,23;		\
+	bne	2b;			\
+	rlwinm.	r3,r5,0,3,3;		\
+	lwz	r3,SD_I2C_RD_DATA(r4)
+
+#define SPD_MIN_RFRSH	(0x80)
+#define SPD_MAX_RFRSH	(0x85)
+
+refresh_rates:	/* in nSec */
+	.long	15625	/* Normal (0x80) */
+	.long	3900	/* Reduced 0.25x (0x81) */
+	.long	7800	/* Reduced 0.5x (0x82) */
+	.long	31300	/* Extended 2x (0x83) */
+	.long	62500	/* Extended 4x (0x84) */
+	.long	125000	/* Extended 8x (0x85) */
+
+/*
+ * tsi108_sdram_spd
+ *
+ * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
+ * Uses registers: r4 - SDC base address (not changed)
+ *				   r9 - SDC clocking period in nSec
+ * Changes registers: r3,r5,r6,r7,r8,r10,r11
+ */
+
+tsi108_sdram_spd:
+
+	li	r10,SPD_DIMM0
+	xor	r11,r11,r11		/* DIMM Base Address: starts from 0 */
+
+do_first_dimm:
+
+	/* Program Refresh Rate	Register */
+
+	READ_SPD(12)			/* get Refresh Rate */
+	beq	check_next_slot
+	li	r5, ERR_RFRSH_RATE
+	cmpi	0,0,r3,SPD_MIN_RFRSH
+	ble	spd_fail
+	cmpi	0,0,r3,SPD_MAX_RFRSH
+	bgt	spd_fail
+	addi	r3,r3,-SPD_MIN_RFRSH
+	rlwinm	r3,r3,2,0,31
+	lis	r5,refresh_rates@h
+	ori	r5,r5,refresh_rates@l
+	lwzx	r5,r5,r3		/* get refresh rate in nSec */
+	divwu	r5,r5,r9		/* calculate # of SDC clocks */
+	stw	r5,SD_REFRESH(r4)	/* Set refresh rate */
+	sync
+
+	/* Program SD Timing Register */
+
+	li	r7, 0		/* clear r7 prior parameter collection */
+
+	READ_SPD(20)		/* get DIMM type: Registered or Unbuffered */
+	beq	spd_read_fail
+	li	r5, ERR_DIMM_TYPE
+	cmpi	0,0,r3,SPD_UDIMM
+	beq	do_cl
+	cmpi	0,0,r3,SPD_RDIMM
+	bne	spd_fail
+	oris	r7,r7,0x1000	/* set SD_TIMING[DIMM_TYPE] bit */
+
+do_cl:
+	READ_SPD(18)		/* Get CAS Latency */
+	beq	spd_read_fail
+	li	r5,ERR_CL_VALUE
+	andi.	r6,r3,SPD_CAS_3
+	beq	cl_4
+	li	r6,3
+	b	set_cl
+cl_4:
+	andi.	r6,r3,SPD_CAS_4
+	beq	cl_5
+	li	r6,4
+	b	set_cl
+cl_5:
+	andi.	r6,r3,SPD_CAS_5
+	beq	spd_fail
+	li	r6,5
+set_cl:
+	rlwimi	r7,r6,24,5,7
+
+	READ_SPD(30)		/* Get tRAS */
+	beq	spd_read_fail
+	divwu	r6,r3,r9
+	mullw	r8,r6,r9
+	subf.	r8,r8,r3
+	beq	set_tras
+	addi	r6,r6,1
+set_tras:
+	li r5,ERR_TRAS_FAIL
+	cmpi	0,0,r6,0x0F	/* max supported value */
+	bgt	spd_fail
+	rlwimi	r7,r6,16,12,15
+
+	READ_SPD(29)	/* Get tRCD */
+	beq	spd_read_fail
+	/* right shift tRCD by 2 bits as per DDR2 spec */
+	rlwinm	r3,r3,30,2,31
+	divwu	r6,r3,r9
+	mullw	r8,r6,r9
+	subf.	r8,r8,r3
+	beq	set_trcd
+	addi	r6,r6,1
+set_trcd:
+	li	r5,ERR_TRCD_FAIL
+	cmpi	0,0,r6,0x07	/* max supported value */
+	bgt	spd_fail
+	rlwimi	r7,r6,12,17,19
+
+	READ_SPD(27)	/* Get tRP value */
+	beq	spd_read_fail
+	rlwinm	r3,r3,30,2,31	/* right shift tRP by 2 bits as per DDR2 spec */
+	divwu	r6,r3,r9
+	mullw	r8,r6,r9
+	subf.	r8,r8,r3
+	beq	set_trp
+	addi	r6,r6,1
+set_trp:
+	li	r5,ERR_TRP_FAIL
+	cmpi	0,0,r6,0x07	/* max supported value */
+	bgt	spd_fail
+	rlwimi	r7,r6,8,21,23
+
+	READ_SPD(36)	/* Get tWR value */
+	beq	spd_read_fail
+	rlwinm	r3,r3,30,2,31	/* right shift tWR by 2 bits as per DDR2 spec */
+	divwu	r6,r3,r9
+	mullw	r8,r6,r9
+	subf.	r8,r8,r3
+	beq	set_twr
+	addi	r6,r6,1
+set_twr:
+	addi	r6,r6,-1	/* Tsi108 SDC always gives one extra clock */
+	li	r5,ERR_TWR_FAIL
+	cmpi	0,0,r6,0x07	/* max supported value */
+	bgt	spd_fail
+	rlwimi	r7,r6,5,24,26
+
+	READ_SPD(42)	/* Get tRFC */
+	beq	spd_read_fail
+	li	r5, ERR_TRFC_FAIL
+	/* Tsi108 spec: tRFC=(tRFC + 1)/2 */
+	addi	r3,r3,1
+	rlwinm.	r3,r3,31,1,31	/* divide by 2 */
+	beq	spd_fail
+	divwu	r6,r3,r9
+	mullw	r8,r6,r9
+	subf.	r8,r8,r3
+	beq	set_trfc
+	addi	r6,r6,1
+set_trfc:
+	cmpi	0,0,r6,0x1F	/* max supported value */
+	bgt	spd_fail
+	rlwimi	r7,r6,0,27,31
+
+	stw	r7,SD_TIMING(r4)
+	sync
+
+	/*
+	 * The following two registers are set on per-DIMM basis.
+	 * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
+	 */
+
+do_each_dimm:
+
+	/* Program SDRAM DIMM Control Register */
+
+	li	r7, 0		/* clear r7 prior parameter collection */
+
+	READ_SPD(13)		/* Get Primary SDRAM Width */
+	beq	spd_read_fail
+	cmpi	0,0,r3,4	/* Check for 4-bit SDRAM */
+	beq	do_nbank
+	oris	r7,r7,0x0010	/* Set MEM_WIDTH bit */
+
+do_nbank:
+	READ_SPD(17)		/* Get Number of banks on SDRAM device */
+	beq	spd_read_fail
+	/* Grendel only distinguish betw. 4 or 8-bank memory parts */
+	li	r5,ERR_UNKNOWN_PART	/* non-supported memory part */
+	cmpi	0,0,r3,4
+	beq	do_nrank
+	cmpi	0,0,r3,8
+	bne	spd_fail
+	ori	r7,r7,0x1000
+
+do_nrank:
+	READ_SPD(5)		/* Get # of Ranks */
+	beq	spd_read_fail
+	li	r5,ERR_NRANK_INVALID
+	andi.	r6,r3,0x7	/* Use bits [2..0] only */
+	beq	do_addr_mode
+	cmpi	0,0,r6,1
+	bgt	spd_fail
+	rlwimi	r7,r6,8,23,23
+
+do_addr_mode:
+	READ_SPD(4)		/* Get # of Column Addresses */
+	beq	spd_read_fail
+	li	r5, ERR_ADDR_MODE
+	andi.	r3,r3,0x0f	/* cut off reserved bits */
+	cmpi	0,0,r3,8
+	ble	spd_fail
+	cmpi	0,0,r3,15
+	bgt	spd_fail
+	addi	r6,r3,-8	/* calculate ADDR_MODE parameter */
+	rlwimi	r7,r6,4,24,27	/* set ADDR_MODE field */
+
+set_dimm_ctrl:
+#ifdef SDC_AUTOPRECH_EN
+	oris	r7,r7,0x0001	/* set auto precharge EN bit */
+#endif
+	ori	r7,r7,1		/* set ENABLE bit */
+	cmpi	0,0,r10,SPD_DIMM0
+	bne	1f
+	stw	r7,SD_D0_CTRL(r4)
+	sync
+	b	set_dimm_bar
+1:
+	stw	r7,SD_D1_CTRL(r4)
+	sync
+
+
+	/* Program SDRAM DIMMx Base Address Register */
+
+set_dimm_bar:
+	READ_SPD(5)		/* get # of Ranks */
+	beq	spd_read_fail
+	andi.	r7,r3,0x7
+	addi	r7,r7,1
+	READ_SPD(31)		/* Read DIMM rank density */
+	beq	spd_read_fail
+	rlwinm	r5,r3,27,29,31
+	rlwinm	r6,r3,3,24,28
+	or	r5,r6,r5	/* r5 = Normalized Rank Density byte */
+	lis	r8, 0x0080	/* 128MB >> 4 */
+	mullw	r8,r8,r5	/* r8 = (rank_size >> 4) */
+	mullw	r8,r8,r7	/* r8 = (DIMM_size >> 4) */
+	neg	r7,r8
+	rlwinm	r7,r7,28,4,31
+	or	r7,r7,r11	/* set ADDR field */
+	rlwinm	r8,r8,12,20,31
+	add	r11,r11,r8	/* set Base Addr for next DIMM */
+
+	cmpi	0,0,r10,SPD_DIMM0
+	bne	set_dimm1_size
+	stw	r7,SD_D0_BAR(r4)
+	sync
+	li	r10,SPD_DIMM1
+	READ_SPD(0)
+	bne do_each_dimm
+	b spd_done
+
+set_dimm1_size:
+	stw	r7,SD_D1_BAR(r4)
+	sync
+spd_done:
+	blr
+
+check_next_slot:
+	cmpi	0,0,r10,SPD_DIMM1
+	beq	spd_read_fail
+	li	r10,SPD_DIMM1
+	b	do_first_dimm
+spd_read_fail:
+	ori	r3,r0,0xdead
+	b	err_hung
+spd_fail:
+	li	r3,0x0bad
+	sync
+err_hung:	/* hang here for debugging */
+	nop
+	nop
+	b	err_hung
+
+#endif /* !SDC_HARDCODED_INIT */
diff --git a/u-boot/board/freescale/mpc7448hpc2/config.mk b/u-boot/board/freescale/mpc7448hpc2/config.mk
new file mode 100644
index 0000000..84a46e3
--- /dev/null
+++ b/u-boot/board/freescale/mpc7448hpc2/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2005 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
diff --git a/u-boot/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/u-boot/board/freescale/mpc7448hpc2/mpc7448hpc2.c
new file mode 100644
index 0000000..117b951
--- /dev/null
+++ b/u-boot/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2005 Freescale Semiconductor, Inc.
+ *
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the Tsi108 Emul Board by avb@Tundra
+ */
+
+/*
+ * board support/init functions for the
+ * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <fdt_support.h>
+#include <netdev.h>
+
+#undef	DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void tsi108_init_f (void);
+
+int display_mem_map (void);
+
+void after_reloc (ulong dest_addr)
+{
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *) gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/*
+ * Check Board Identity:
+ * report board type
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
+	return (l_type);
+}
+
+/*
+ * Read Processor ID:
+ *
+ * report calling processor number
+ */
+
+int read_pid (void)
+{
+	return 0;		/* we are on single CPU platform for a while */
+}
+
+long int dram_size (int board_type)
+{
+	return 0x20000000;	/* 256M bytes */
+}
+
+phys_size_t initdram (int board_type)
+{
+	return dram_size (board_type);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#if defined(CONFIG_TSI108_ETH)
+	rc = tsi108_eth_initialize(bis);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/freescale/mpc7448hpc2/tsi108_init.c b/u-boot/board/freescale/mpc7448hpc2/tsi108_init.c
new file mode 100644
index 0000000..e1c63f8
--- /dev/null
+++ b/u-boot/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -0,0 +1,665 @@
+/*****************************************************************************
+ * (C) Copyright 2003;  Tundra Semiconductor Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ * FILENAME: tsi108_init.c
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Initialization code for the Tundra Tsi108 bridge chip
+ *---------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <tsi108.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void mpicInit (int verbose);
+
+/*
+ * Configuration Options
+ */
+
+typedef struct {
+	ulong upper;
+	ulong lower;
+} PB2OCN_LUT_ENTRY;
+
+PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
+	/* 0 - 7 */
+	{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
+
+	/* 8 - 15 */
+	{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
+
+	/* 16 - 23 */
+	{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
+	/* 24 - 31 */
+	{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
+	{0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X  PCI I/O (Byte-Swap + Translate) */
+	{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X  PCI Config (Byte-Swap) */
+
+	{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
+	{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
+	{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
+	{0x00000000, 0x00000240}  /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
+};
+
+#ifdef CONFIG_SYS_CLK_SPREAD
+typedef struct {
+	ulong ctrl0;
+	ulong ctrl1;
+} PLL_CTRL_SET;
+
+/*
+ * Clock Generator SPLL0 initialization values
+ * PLL0 configuration table for various PB_CLKO freq.
+ * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
+ * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
+ */
+
+static PLL_CTRL_SET pll0_config[8] = {
+	{0x00000000, 0x00000000},	/* 0: bypass */
+	{0x00000000, 0x00000000},	/* 1: reserved */
+	{0x00430044, 0x00000043},	/* 2: CG_PB_CLKO = 183 MHz */
+	{0x005c0044, 0x00000039},	/* 3: CG_PB_CLKO = 100 MHz */
+	{0x005c0044, 0x00000039},	/* 4: CG_PB_CLKO = 133 MHz */
+	{0x004a0044, 0x00000040},	/* 5: CG_PB_CLKO = 167 MHz */
+	{0x005c0044, 0x00000039},	/* 6: CG_PB_CLKO = 200 MHz */
+	{0x004f0044, 0x0000003e}	/* 7: CG_PB_CLKO = 233 MHz */
+};
+#endif	/* CONFIG_SYS_CLK_SPREAD */
+
+/*
+ * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
+ * (based on recommended Tsi108 reference clock 33MHz)
+ */
+static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
+
+/*
+ * get_board_bus_clk ()
+ *
+ * returns the bus clock in Hz.
+ */
+unsigned long get_board_bus_clk (void)
+{
+	ulong i;
+
+	/* Detect PB clock freq. */
+	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */
+
+	return pb_clk_sel[i] * 1000000;
+}
+
+/*
+ * board_early_init_f ()
+ *
+ * board-specific initialization executed from flash
+ */
+
+int board_early_init_f (void)
+{
+	ulong i;
+
+	gd->mem_clk = 0;
+	i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
+			CG_PWRUP_STATUS);
+	i = (i >> 20) & 0x07;	/* Get GD PLL multiplier */
+	switch (i) {
+	case 0:	/* external clock */
+		printf ("Using external clock\n");
+		break;
+	case 1:	/* system clock */
+		gd->mem_clk = gd->bus_clk;
+		break;
+	case 4:	/* 133 MHz */
+	case 5:	/* 166 MHz */
+	case 6:	/* 200 MHz */
+		gd->mem_clk = pb_clk_sel[i] * 1000000;
+		break;
+	default:
+		printf ("Invalid DDR2 clock setting\n");
+		return -1;
+	}
+	printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
+	printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
+	return 0;
+}
+
+/*
+ * board_early_init_r() - Tsi108 initialization function executed right after
+ * relocation. Contains code that cannot be executed from flash.
+ */
+
+int board_early_init_r (void)
+{
+	ulong temp, i;
+	ulong reg_val;
+	volatile ulong *reg_ptr;
+
+	reg_ptr =
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
+
+	for (i = 0; i < 32; i++) {
+		*reg_ptr++ = 0x00000201;	/* SWAP ENABLED */
+		*reg_ptr++ = 0x00;
+	}
+
+	__asm__ __volatile__ ("eieio");
+	__asm__ __volatile__ ("sync");
+
+	/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
+		0x80000001);
+	__asm__ __volatile__ ("sync");
+
+	/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
+	 * read from SDRAM)
+	 */
+
+	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
+	 * processor bus address space. Immediately after reset LUT and address
+	 * translation are disabled for this BAR. Now we have to initialize LUT
+	 * and switch from the BOOT mode to the normal operation mode.
+	 *
+	 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
+	 * and covers 512MB of address space. To allow larger aperture we also
+	 * have to relocate register window of Tsi108
+	 *
+	 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
+	 * mode.
+	 *
+	 * initialize pointer to LUT associated with PB_OCN_BAR1
+	 */
+	reg_ptr =
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
+
+	for (i = 0; i < 32; i++) {
+		*reg_ptr++ = pb2ocn_lut1[i].lower;
+		*reg_ptr++ = pb2ocn_lut1[i].upper;
+	}
+
+	__asm__ __volatile__ ("sync");
+
+	/* Base addresses for CS0, CS1, CS2, CS3 */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
+		0x00000000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
+		0x00100000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
+		0x00200000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
+		0x00300000);
+	__asm__ __volatile__ ("sync");
+
+	/* Masks for HLP banks */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
+		0xFFF00000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
+		0xFFF00000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
+		0xFFF00000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
+		0xFFF00000);
+	__asm__ __volatile__ ("sync");
+
+	/* Set CTRL0 values for banks */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
+		0x7FFC44C2);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
+		0x7FFC44C0);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
+		0x7FFC44C0);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
+		0x7FFC44C2);
+	__asm__ __volatile__ ("sync");
+
+	/* Set banks to latched mode, enabled, and other default settings */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
+		0x7C0F2000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
+		0x7C0F2000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
+		0x7C0F2000);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
+		0x7C0F2000);
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
+	 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
+	 */
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
+		0xE0000011);
+	__asm__ __volatile__ ("sync");
+
+	/* Make sure that OCN_BAR2 decoder is set (to allow following
+	 * immediate read from SDRAM)
+	 */
+
+	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * SRI: At this point we have enabled the HLP banks. That means we can
+	 * now read from the NVRAM and initialize the environment variables.
+	 * We will over-ride the env_init called in board_init_f
+	 * This is really a work-around because, the HLP bank 1
+	 * where NVRAM resides is not visible during board_init_f
+	 * (arch/powerpc/lib/board.c)
+	 * Alternatively, we could use the I2C EEPROM at start-up to configure
+	 * and enable all HLP banks and not just HLP 0 as is being done for
+	 * Taiga Rev. 2.
+	 */
+
+	env_init ();
+
+#ifndef DISABLE_PBM
+
+	/*
+	 * For IBM processors we have to set Address-Only commands generated
+	 * by PBM that are different from ones set after reset.
+	 */
+
+	temp = get_cpu_type ();
+
+	if ((CPU_750FX == temp) || (CPU_750GX == temp))
+		out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
+			0x00009955);
+#endif	/* DISABLE_PBM */
+
+#ifdef CONFIG_PCI
+	/*
+	 * Initialize PCI/X block
+	 */
+
+	/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+		PCI_PFAB_BAR0_UPPER, 0);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
+		0xFB000001);
+	__asm__ __volatile__ ("sync");
+
+	/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
+
+	temp =	in32(CONFIG_SYS_TSI108_CSR_BASE +
+		TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
+
+	temp &= ~0xFF00;	/* Clear the BUS_NUM field */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
+		temp);
+
+	/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
+		0);
+	__asm__ __volatile__ ("sync");
+
+	/* This register is on the PCI side to interpret the address it receives
+	 * and maps it as a IO address.
+	 */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
+		0x00000001);
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * Map PCI/X Memory Space
+	 *
+	 * Transactions directed from OCM to PCI Memory Space are directed
+	 * from PB to PCI
+	 * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
+	 * If address remapping is required the corresponding PCI_PFAB_MEM32
+	 * and PCI_PFAB_PFMx register groups have to be configured.
+	 *
+	 * Map the path from the PCI/X bus into the system memory
+	 *
+	 * The memory mapped window assotiated with PCI P2O_BAR2 provides
+	 * access to the system memory without address remapping.
+	 * All system memory is opened for accesses initiated by PCI/X bus
+	 * masters.
+	 *
+	 * Initialize LUT associated with PCI P2O_BAR2
+	 *
+	 * set pointer to LUT associated with PCI P2O_BAR2
+	 */
+
+	reg_ptr =
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
+
+#ifdef DISABLE_PBM
+
+	/* In case when PBM is disabled (no HW supported cache snoopng on PB)
+	 * P2O_BAR2 is directly mapped into the system memory without address
+	 * translation.
+	 */
+
+	reg_val = 0x00000004;	/* SDRAM port + NO Addr_Translation */
+
+	for (i = 0; i < 32; i++) {
+		*reg_ptr++ = reg_val;	/* P2O_BAR2_LUTx */
+		*reg_ptr++ = 0;		/* P2O_BAR2_LUT_UPPERx */
+	}
+
+	/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
+	reg_val = 0x00007500;
+#else
+
+	reg_val = 0x00000002;	/* Destination port = PBM */
+
+	for (i = 0; i < 32; i++) {
+		*reg_ptr++ = reg_val;	/* P2O_BAR2_LUTx */
+/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
+		*reg_ptr++ = 0x40000000;
+/* offset = 16MB, address translation is enabled to allow byte swapping */
+		reg_val += 0x01000000;
+	}
+
+/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
+	reg_val = 0x00007100;
+#endif
+
+	__asm__ __volatile__ ("eieio");
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+		reg_val);
+	__asm__ __volatile__ ("sync");
+
+	/* Set 64-bit PCI bus address for system memory
+	 * ( 0 is the best choice for easy mapping)
+	 */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
+		0x00000000);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
+		0x00000000);
+	__asm__ __volatile__ ("sync");
+
+#ifndef DISABLE_PBM
+	/*
+	 *  The memory mapped window assotiated with PCI P2O_BAR3 provides
+	 *  access to the system memory using SDRAM OCN port and address
+	 *  translation. This is alternative way to access SDRAM from PCI
+	 *  required for Tsi108 emulation testing.
+	 *  All system memory is opened for accesses initiated by
+	 *  PCI/X bus masters.
+	 *
+	 *  Initialize LUT associated with PCI P2O_BAR3
+	 *
+	 *  set pointer to LUT associated with PCI P2O_BAR3
+	 */
+	reg_ptr =
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
+
+	reg_val = 0x00000004;	/* Destination port = SDC */
+
+	for (i = 0; i < 32; i++) {
+		*reg_ptr++ = reg_val;	/* P2O_BAR3_LUTx */
+
+/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
+		*reg_ptr++ = 0;
+
+/* offset = 16MB, address translation is enabled to allow byte swapping */
+		reg_val += 0x01000000;
+	}
+
+	__asm__ __volatile__ ("eieio");
+	__asm__ __volatile__ ("sync");
+
+	/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
+
+	reg_val =
+		in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+		 PCI_P2O_PAGE_SIZES);
+	reg_val &= ~0x00FF;
+	reg_val |= 0x0071;
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+		reg_val);
+	__asm__ __volatile__ ("sync");
+
+	/* Set 64-bit base PCI bus address for window (0x20000000) */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
+		0x00000000);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
+		0x20000000);
+	__asm__ __volatile__ ("sync");
+
+#endif	/* !DISABLE_PBM */
+
+#ifdef ENABLE_PCI_CSR_BAR
+	/* open if required access to Tsi108 CSRs from the PCI/X bus */
+	/* enable BAR0 on the PCI/X bus */
+	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
+		TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
+	reg_val |= 0x02;
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
+		reg_val);
+	__asm__ __volatile__ ("sync");
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
+		0x00000000);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
+		CONFIG_SYS_TSI108_CSR_BASE);
+	__asm__ __volatile__ ("sync");
+
+#endif
+
+	/*
+	 * Finally enable PCI/X Bus Master and Memory Space access
+	 */
+
+	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
+	reg_val |= 0x06;
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
+	__asm__ __volatile__ ("sync");
+
+#endif	/* CONFIG_PCI */
+
+	/*
+	 * Initialize MPIC outputs (interrupt pins):
+	 * Interrupt routing on the Grendel Emul. Board:
+	 * PB_INT[0] -> INT (CPU0)
+	 * PB_INT[1] -> INT (CPU1)
+	 * PB_INT[2] -> MCP (CPU0)
+	 * PB_INT[3] -> MCP (CPU1)
+	 * Set interrupt controller outputs as Level_Sensitive/Active_Low
+	 */
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * Ensure that Machine Check exception is enabled
+	 * We need it to support PCI Bus probing (configuration reads)
+	 */
+
+	reg_val = mfmsr ();
+	mtmsr(reg_val | MSR_ME);
+
+	return 0;
+}
+
+/*
+ * Needed to print out L2 cache info
+ * used in the misc_init_r function
+ */
+
+unsigned long get_l2cr (void)
+{
+	unsigned long l2controlreg;
+	asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
+	return l2controlreg;
+}
+
+/*
+ * misc_init_r()
+ *
+ * various things to do after relocation
+ *
+ */
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_SYS_CLK_SPREAD	/* Initialize Spread-Spectrum Clock generation */
+	ulong i;
+
+	/* Ensure that Spread-Spectrum is disabled */
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
+
+	/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
+	 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
+	 */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+		0x002e0044);	/* D = 0.25% */
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
+		0x00000039);	/* BWADJ */
+
+	/* Initialize PLL0: CG_PB_CLKO  */
+	/* Detect PB clock freq. */
+	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */
+
+	out32 (CONFIG_SYS_TSI108_CSR_BASE +
+		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE +
+		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
+
+	/* Wait and set SSEN for both PLL0 and 1 */
+	udelay (1000);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+		0x802e0044);	/* D=0.25% */
+	out32 (CONFIG_SYS_TSI108_CSR_BASE +
+		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
+		0x80000000 | pll0_config[i].ctrl0);
+#endif	/* CONFIG_SYS_CLK_SPREAD */
+
+#ifdef CONFIG_SYS_L2
+	l2cache_enable ();
+#endif
+	printf ("BUS:   %lu MHz\n", gd->bus_clk / 1000000);
+	printf ("MEM:   %lu MHz\n", gd->mem_clk / 1000000);
+
+	/*
+	 * All the information needed to print the cache details is avaiblable
+	 * at this point i.e. above call to l2cache_enable is the very last
+	 * thing done with regards to enabling diabling the cache.
+	 * So this seems like a good place to print all this information
+	 */
+
+	printf ("CACHE: ");
+	switch (get_cpu_type()) {
+	case CPU_7447A:
+		printf ("L1 Instruction cache - 32KB 8-way");
+		(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
+			printf (" DISABLED\n");
+		printf ("L1 Data cache - 32KB 8-way");
+		(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
+			printf (" DISABLED\n");
+		printf ("Unified L2 cache - 512KB 8-way");
+		(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
+			printf (" DISABLED\n");
+		printf ("\n");
+		break;
+
+	case CPU_7448:
+		printf ("L1 Instruction cache - 32KB 8-way");
+		(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
+			printf (" DISABLED\n");
+		printf ("L1 Data cache - 32KB 8-way");
+		(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
+			printf (" DISABLED\n");
+		printf ("Unified L2 cache - 1MB 8-way");
+		(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
+			printf (" DISABLED\n");
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
diff --git a/u-boot/board/freescale/mpc8260ads/Makefile b/u-boot/board/freescale/mpc8260ads/Makefile
new file mode 100644
index 0000000..74f5b85
--- /dev/null
+++ b/u-boot/board/freescale/mpc8260ads/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8260ads/flash.c b/u-boot/board/freescale/mpc8260ads/flash.c
new file mode 100644
index 0000000..e03852f
--- /dev/null
+++ b/u-boot/board/freescale/mpc8260ads/flash.c
@@ -0,0 +1,492 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Re-written to support multi-bank flash SIMMs.
+ * Added support for real protection and JFFS2.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x89898989
+#define INTEL_ALT     0xB0B0B0B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x10101010
+#define INTEL_ERASE   0x20202020
+#define INTEL_CLEAR   0x50505050
+#define INTEL_LOCKBIT 0x60606060
+#define INTEL_PROTECT 0x01010101
+#define INTEL_STATUS  0x70707070
+#define INTEL_READID  0x90909090
+#define INTEL_CONFIRM 0xD0D0D0D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x80808080
+#define INTEL_OK       0x80808080
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
+ * Up to 32MB of flash supported (up to 4 banks.)
+ * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
+ *
+ * The following code can not run from flash!
+ */
+unsigned long flash_init (void)
+{
+	ulong size = 0, sect_start, sect_size = 0, bank_size;
+	ushort sect_count = 0;
+	int i, j, nbanks;
+	vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
+	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
+
+	switch (bcsr[2] & 0xF) {
+	case 0:
+		nbanks = 4;
+		break;
+	case 1:
+		nbanks = 2;
+		break;
+	case 2:
+		nbanks = 1;
+		break;
+	default:		/* Unsupported configurations */
+		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
+	}
+
+	if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
+		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
+
+	for (i = 0; i < nbanks; i++) {
+		*addr = INTEL_READID;	/* Read Intelligent Identifier */
+		if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
+			switch (addr[1]) {
+			case SHARP_ID_28F016SCL:
+			case SHARP_ID_28F016SCZ:
+				flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+				sect_count = 32;
+				sect_size = 0x40000;
+				break;
+			default:
+				flash_info[i].flash_id = FLASH_UNKNOWN;
+				sect_count = CONFIG_SYS_MAX_FLASH_SECT;
+				sect_size =
+				   CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
+			}
+		}
+		else
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
+			       addr[0], addr[1], (ulong)addr);
+			size = 0;
+			*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+			break;
+		}
+		flash_info[i].sector_count = sect_count;
+		flash_info[i].size = bank_size = sect_size * sect_count;
+		size += bank_size;
+		sect_start = (ulong)addr;
+		for (j = 0; j < sect_count; j++) {
+			addr = (vu_long *)sect_start;
+			flash_info[i].start[j]   = sect_start;
+			flash_info[i].protect[j] = (addr[2] == 0x01010101);
+			sect_start += sect_size;
+		}
+		*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+		addr = (vu_long *)sect_start;
+	}
+
+	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
+		sect_start = CONFIG_SYS_FLASH_BASE;
+		for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
+			flash_info[i].sector_count = sect_count;
+			for (j = 0; j < sect_count; j++) {
+				flash_info[i].start[j]   = sect_start;
+				flash_info[i].protect[j] = 0;
+				sect_start += sect_size;
+			}
+		}
+		size = CONFIG_SYS_FLASH_SIZE;
+	}
+	else
+		for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+		}
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Clear Status Register */
+			*addr = INTEL_CLEAR;
+			/* Single Block Erase Command */
+			*addr = INTEL_ERASE;
+			/* Confirm */
+			*addr = INTEL_CONFIRM;
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = INTEL_CONFIRM;
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = INTEL_RESET;	/* reset bank */
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			if (*addr != INTEL_OK) {
+				printf("Block erase failed at %08X, CSR=%08X\n",
+				       (uint)addr, (uint)*addr);
+				*addr = INTEL_RESET;	/* reset bank */
+				return 1;
+			}
+
+			/* reset to read mode */
+			*addr = INTEL_RESET;
+		}
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong start;
+	int rc = 0;
+	int flag;
+	vu_long *addr = (vu_long *)dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+
+	*addr = INTEL_CLEAR; /* Clear status register */
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = INTEL_PROGRAM;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			printf("Write timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+	if (*addr != INTEL_OK) {
+		printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	*addr = INTEL_RESET; /* Reset to read array mode */
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	rc = write_word(info, wp, data);
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	start = get_timer(0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+		for (i = 0; i < info->sector_count; i++)
+			if (info->protect[i]) {
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
+			}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/u-boot/board/freescale/mpc8260ads/mpc8260ads.c b/u-boot/board/freescale/mpc8260ads/mpc8260ads.c
new file mode 100644
index 0000000..8f617ca
--- /dev/null
+++ b/u-boot/board/freescale/mpc8260ads/mpc8260ads.c
@@ -0,0 +1,560 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * (C) Copyright 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
+	/* PA9  */ { 0,          0,   0,   0,   0,   0 }, /* PA9 */
+	/* PA8  */ { 0,          0,   0,   0,   0,   0 }, /* PA8 */
+	/* PA7  */ { 0,          0,   0,   1,   0,   0 }, /* PA7 */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
+	/* PA5  */ { 0,          0,   0,   1,   0,   0 }, /* PA5 */
+	/* PA4  */ { 0,          0,   0,   1,   0,   0 }, /* PA4 */
+	/* PA3  */ { 0,          0,   0,   1,   0,   0 }, /* PA3 */
+	/* PA2  */ { 0,          0,   0,   1,   0,   0 }, /* PA2 */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
+	/* PA0  */ { 0,          0,   0,   1,   0,   0 }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
+	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
+	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
+	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
+	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
+	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
+	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
+	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
+	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
+	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
+	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
+	/* PC16 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
+#else
+	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
+#else
+	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
+	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5 */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4 */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3 */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2 */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1 */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+void reset_phy (void)
+{
+	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
+
+	/* Reset the PHY */
+#if CONFIG_SYS_PHY_ADDR == 0
+	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
+	udelay(2);
+	bcsr[1] |=  FETH1_RST;
+#else
+	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
+	udelay(2);
+	bcsr[3] |=  FETH2_RST;
+#endif /* CONFIG_SYS_PHY_ADDR == 0 */
+	udelay(1000);
+#ifdef CONFIG_MII
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+	/*
+	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
+	 * Enable autonegotiation.
+	 */
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+#else
+	/*
+	 * Ethernet PHY is configured (by means of configuration pins)
+	 * to work at 10Mb/s only. We reconfigure it using MII
+	 * to advertise all capabilities, including 100Mb/s, and
+	 * restart autonegotiation.
+	 */
+
+	/* Advertise all capabilities */
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
+
+	/* Do not bypass Rx/Tx (de)scrambler */
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER,  0x0000);
+
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+#endif /* CONFIG_MII */
+}
+
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
+int board_early_init_f (void)
+{
+	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
+
+#ifdef CONFIG_PCI
+	volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
+
+	/* mask alll the PCI interrupts */
+	pci_ic->pci_int_mask |= 0xfff00000;
+#endif
+#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
+	bcsr[1] &= ~RS232EN_1;
+#endif
+#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
+	bcsr[1] &= ~RS232EN_2;
+#endif
+
+#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+	if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+	{
+		volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+		immap->im_siu_conf.sc_siumcr =
+			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+			| SIUMCR_LBPC01;
+	}
+#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
+
+	return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+phys_size_t initdram (int board_type)
+{
+#if   CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+	long int msize = 32;
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+	long int msize = 64;
+#else
+	long int msize = 16;
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *ramaddr, c = 0xff;
+	uint or;
+	uint psdmr;
+	uint psrt;
+
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x00000002;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+#ifdef CONFIG_SYS_LSDRAM_BASE
+	/*
+	  Initialise local bus SDRAM only if the pins
+	  are configured as local bus pins and not as PCI.
+	  The configuration is determined by the HRCW.
+	*/
+	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
+		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
+		memctl->memc_or3   = 0xFF803280;
+		memctl->memc_br3   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
+#else				  /* CS4 */
+		memctl->memc_or4   = 0xFFC01480;
+		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
+		ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
+	}
+#endif /* CONFIG_SYS_LSDRAM_BASE */
+
+	/* Init 60x bus SDRAM */
+#ifdef CONFIG_SPD_EEPROM
+	{
+		spd_eeprom_t spd;
+		uint pbi, bsel, rowst, lsb, tmp;
+
+		i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
+
+		/* Bank-based interleaving is not supported for physical bank
+		   sizes greater than 128MB which is encoded as 0x20 in SPD
+		 */
+		pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
+		msize = spd.nrows * (4 * spd.row_dens);	/* Mixed size not supported */
+		or = ~(msize - 1) << 20;	/* SDAM */
+		switch (spd.nbanks) {	/* BPD */
+		case 2:
+			bsel = 1;
+			break;
+		case 4:
+			bsel = 2;
+			or |= 0x00002000;
+			break;
+		case 8:
+			bsel = 3;
+			or |= 0x00004000;
+			break;
+		}
+		lsb = 3;	/* For 64-bit port, lsb is 3 bits */
+
+		if (pbi) {	/* Bus partition depends on interleaving */
+			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
+			or |= (rowst << 9);	/* ROWST */
+		} else {
+			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
+			or |= ((rowst * 2 - 12) << 9);	/* ROWST */
+		}
+		or |= ((spd.nrow_addr - 9) << 6);	/* NUMR */
+
+		psdmr = (pbi << 31);	/* PBI */
+		/* Bus multiplexing parameters */
+		tmp = 32 - (lsb + spd.nrow_addr);	/* Tables 10-19 and 10-20 */
+		psdmr |= ((tmp - (rowst - 5) - 13) << 24);	/* SDAM */
+		psdmr |= ((tmp - 3 - 12) << 21);	/* BSMA */
+
+		tmp = (31 - lsb - 10) - tmp;
+		/* Pin connected to SDA10 is (31 - lsb - 10).
+		   rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
+		   so (rowst + tmp) alternates with AP.
+		 */
+		if (pbi)				/* Table 10-7 */
+			psdmr |= ((10 - (rowst + tmp)) << 18);	/* SDA10 */
+		else
+			psdmr |= ((12 - (rowst + tmp)) << 18);	/* SDA10 */
+
+		/* SDRAM device-specific parameters */
+		tmp = ns2clk (70);	/* Refresh recovery is not in SPD, so assume 70ns */
+		switch (tmp) {		/* RFRC */
+		case 1:
+		case 2:
+			psdmr |= (1 << 15);
+			break;
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 8:
+			psdmr |= ((tmp - 2) << 15);
+			break;
+		default:
+			psdmr |= (7 << 15);
+		}
+		psdmr |= (ns2clk (spd.trp) % 8 << 12);	/* PRETOACT */
+		psdmr |= (ns2clk (spd.trcd) % 8 << 9);	/* ACTTORW */
+		/* BL=0 because for 64-bit SDRAM burst length must be 4 */
+		/* LDOTOPRE ??? */
+		for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
+			tmp >>= 1;
+		switch (i) {			/* WRC */
+		case 0:
+		case 1:
+			psdmr |= (1 << 4);
+			break;
+		case 2:
+		case 3:
+			psdmr |= (i << 4);
+			break;
+		}
+		/* EAMUX=0 - no external address multiplexing */
+		/* BUFCMD=0 - no external buffers */
+		for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
+			tmp >>= 1;
+		psdmr |= i;				/* CL */
+
+		switch (spd.refresh & 0x7F) {
+		case 1:
+			tmp = 3900;
+			break;
+		case 2:
+			tmp = 7800;
+			break;
+		case 3:
+			tmp = 31300;
+			break;
+		case 4:
+			tmp = 62500;
+			break;
+		case 5:
+			tmp = 125000;
+			break;
+		default:
+			tmp = 15625;
+		}
+		psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
+				  ((memctl->memc_mptpr >> 8) + 1)) - 1;
+#ifdef SPD_DEBUG
+		printf ("\nDIMM type:       %-18.18s\n", spd.mpart);
+		printf ("SPD size:        %d\n", spd.info_size);
+		printf ("EEPROM size:     %d\n", 1 << spd.chip_size);
+		printf ("Memory type:     %d\n", spd.mem_type);
+		printf ("Row addr:        %d\n", spd.nrow_addr);
+		printf ("Column addr:     %d\n", spd.ncol_addr);
+		printf ("# of rows:       %d\n", spd.nrows);
+		printf ("Row density:     %d\n", spd.row_dens);
+		printf ("# of banks:      %d\n", spd.nbanks);
+		printf ("Data width:      %d\n",
+				256 * spd.dataw_msb + spd.dataw_lsb);
+		printf ("Chip width:      %d\n", spd.primw);
+		printf ("Refresh rate:    %02X\n", spd.refresh);
+		printf ("CAS latencies:   %02X\n", spd.cas_lat);
+		printf ("Write latencies: %02X\n", spd.write_lat);
+		printf ("tRP:             %d\n", spd.trp);
+		printf ("tRCD:            %d\n", spd.trcd);
+
+		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
+#endif /* SPD_DEBUG */
+	}
+#else  /* !CONFIG_SPD_EEPROM */
+	or    = CONFIG_SYS_OR2;
+	psdmr = CONFIG_SYS_PSDMR;
+	psrt  = CONFIG_SYS_PSRT;
+#endif /* CONFIG_SPD_EEPROM */
+	memctl->memc_psrt = psrt;
+	memctl->memc_or2 = or;
+	memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
+	ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
+	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
+	*ramaddr = c;
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/* return total 60x bus SDRAM size */
+	return (msize * 1024 * 1024);
+}
+
+int checkboard (void)
+{
+#if   CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
+	puts ("Board: Motorola MPC8260ADS\n");
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
+	puts ("Board: Motorola MPC8266ADS\n");
+#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+	puts ("Board: Motorola PQ2FADS-ZU\n");
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+	puts ("Board: Motorola MPC8272ADS\n");
+#else
+	puts ("Board: unknown\n");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8266ads/Makefile b/u-boot/board/freescale/mpc8266ads/Makefile
new file mode 100644
index 0000000..f4938c4
--- /dev/null
+++ b/u-boot/board/freescale/mpc8266ads/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8266ads/flash.c b/u-boot/board/freescale/mpc8266ads/flash.c
new file mode 100644
index 0000000..06dde36
--- /dev/null
+++ b/u-boot/board/freescale/mpc8266ads/flash.c
@@ -0,0 +1,509 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifndef CONFIG_MPC8266ADS
+	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+#endif
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+#ifndef CONFIG_MPC8266ADS
+	bcsr->bd_ctrl |= BD_CTRL_FLWE;
+#endif
+
+
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+#ifndef CONFIG_MPC8266ADS
+	/* Remap FLASH according to real size */
+	memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br1 & ~(BR_BA_MSK));
+#endif
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+
+	value = addr[0] & 0x00FF00FF;
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x80808080) != 0x80808080) {
+				if(*addr & 0x20202020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return 1;
+				}
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+		}
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+	while (((csr = *addr) & 0x80808080) != 0x80808080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	/* Clear Status Register */
+	*addr = 0x50505050;
+
+	*addr = 0x60606060;
+	*addr = 0xd0d0d0d0;
+
+	start = get_timer (0);
+	while(*addr != 0x80808080){
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			return 1;
+		}
+	}
+	return 0;
+}
diff --git a/u-boot/board/freescale/mpc8266ads/mpc8266ads.c b/u-boot/board/freescale/mpc8266ads/mpc8266ads.c
new file mode 100644
index 0000000..66acc41
--- /dev/null
+++ b/u-boot/board/freescale/mpc8266ads/mpc8266ads.c
@@ -0,0 +1,586 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <i2c.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * PBI Page Based Interleaving
+ *   PSDMR_PBI page based interleaving
+ *   0         bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ *   (this can help with marginal board layouts)
+ *   PSDMR_EAMUX  adds a clock
+ *   0            no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ *   PSDMR_BUFCMD adds a clock
+ *   0            no extra clock
+ */
+#define CONFIG_PBI		0
+#define PESSIMISTIC_SDRAM	0
+#define EAMUX			0	/* EST requires EAMUX */
+#define BUFCMD			0
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT970 FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+typedef struct bscr_ {
+	unsigned long bcsr0;
+	unsigned long bcsr1;
+	unsigned long bcsr2;
+	unsigned long bcsr3;
+	unsigned long bcsr4;
+	unsigned long bcsr5;
+	unsigned long bcsr6;
+	unsigned long bcsr7;
+} bcsr_t;
+
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+} pci_ic_t;
+
+void reset_phy(void)
+{
+    volatile bcsr_t  *bcsr           = (bcsr_t *)CONFIG_SYS_BCSR;
+
+    /* reset the FEC port */
+    bcsr->bcsr1                    &= ~FETH_RST;
+    bcsr->bcsr1                    |= FETH_RST;
+}
+
+
+int board_early_init_f (void)
+{
+    volatile bcsr_t  *bcsr         = (bcsr_t *)CONFIG_SYS_BCSR;
+    volatile pci_ic_t *pci_ic      = (pci_ic_t *) CONFIG_SYS_PCI_INT;
+
+    bcsr->bcsr1                    = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
+
+    /* mask all PCI interrupts */
+    pci_ic->pci_int_mask |= 0xfff00000;
+
+    return 0;
+}
+
+int checkboard(void)
+{
+    puts ("Board: Motorola MPC8266ADS\n");
+    return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	/* Autoinit part stolen from board/sacsng/sacsng.c */
+    volatile immap_t *immap         = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8260_t *memctl   = &immap->im_memctl;
+    volatile uchar c = 0xff;
+    volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+    uint  psdmr = CONFIG_SYS_PSDMR;
+    int i;
+
+    uint   psrt = 0x21;					/* for no SPD */
+    uint   chipselects = 1;				/* for no SPD */
+    uint   sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;	/* for no SPD */
+    uint   or = CONFIG_SYS_OR2_PRELIM;				/* for no SPD */
+    uint   data_width;
+    uint   rows;
+    uint   banks;
+    uint   cols;
+    uint   caslatency;
+    uint   width;
+    uint   rowst;
+    uint   sdam;
+    uint   bsma;
+    uint   sda10;
+    u_char spd_size;
+    u_char data;
+    u_char cksum;
+    int    j;
+
+    /* Keep the compiler from complaining about potentially uninitialized vars */
+    data_width = rows = banks = cols = caslatency = 0;
+
+    /*
+     * Read the SDRAM SPD EEPROM via I2C.
+     */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+    i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+    spd_size = data;
+    cksum    = data;
+    for(j = 1; j < 64; j++)
+	{	/* read only the checksummed bytes */
+	/* note: the I2C address autoincrements when alen == 0 */
+		i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+		/*printf("addr %d = 0x%02x\n", j, data);*/
+		if(j ==  5) chipselects = data & 0x0F;
+		else if(j ==  6) data_width  = data;
+		else if(j ==  7) data_width |= data << 8;
+		else if(j ==  3) rows        = data & 0x0F;
+		else if(j ==  4) cols        = data & 0x0F;
+		else if(j == 12)
+		{
+			/*
+				 * Refresh rate: this assumes the prescaler is set to
+			 * approximately 0.39uSec per tick and the target refresh period
+			 * is about 85% of maximum.
+			 */
+			switch(data & 0x7F)
+			{
+					default:
+					case 0:  psrt = 0x21; /*  15.625uS */  break;
+					case 1:  psrt = 0x07; /*   3.9uS   */  break;
+					case 2:  psrt = 0x0F; /*   7.8uS   */  break;
+					case 3:  psrt = 0x43; /*  31.3uS   */  break;
+					case 4:  psrt = 0x87; /*  62.5uS   */  break;
+					case 5:  psrt = 0xFF; /* 125uS     */  break;
+			}
+		}
+		else if(j == 17) banks       = data;
+		else if(j == 18)
+		{
+			caslatency = 3; /* default CL */
+#		    if(PESSIMISTIC_SDRAM)
+				if((data & 0x04) != 0) caslatency = 3;
+				else if((data & 0x02) != 0) caslatency = 2;
+				else if((data & 0x01) != 0) caslatency = 1;
+#			else
+				if((data & 0x01) != 0) caslatency = 1;
+				else if((data & 0x02) != 0) caslatency = 2;
+				else if((data & 0x04) != 0) caslatency = 3;
+#			endif
+			else
+			{
+			printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+					data);
+			}
+		}
+		else if(j == 63)
+		{
+			if(data != cksum)
+			{
+				printf ("WARNING: Configuration data checksum failure:"
+					" is 0x%02x, calculated 0x%02x\n",
+				data, cksum);
+			}
+		}
+		cksum += data;
+    }
+
+    /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+    if(caslatency < 2) {
+		printf("CL was %d, forcing to 2\n", caslatency);
+		caslatency = 2;
+    }
+    if(rows > 14) {
+		printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+		rows = 14;
+    }
+    if(cols > 11) {
+		printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+		cols = 11;
+    }
+
+    if((data_width != 64) && (data_width != 72))
+    {
+		printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+			data_width);
+    }
+    width = 3;		/* 2^3 = 8 bytes = 64 bits wide */
+    /*
+     * Convert banks into log2(banks)
+     */
+    if     (banks == 2)	banks = 1;
+    else if(banks == 4)	banks = 2;
+    else if(banks == 8)	banks = 3;
+
+
+    sdram_size = 1 << (rows + cols + banks + width);
+    /* hack for high density memory (512MB per CS) */
+    /* !!!!! Will ONLY work with Page Based Interleave !!!!!
+	     ( PSDMR[PBI] = 1 )
+    */
+    /* mamory actually has 11 column addresses, but the memory controller
+       doesn't really care.
+       the calculations that follow will however move the rows so that
+       they are muxed one bit off if you use 11 bit columns.
+       The solution is to tell the memory controller the correct size of the memory
+       but change the number of columns to 10 afterwards.
+       The 11th column addre will still be mucxed correctly onto the bus.
+
+       Also be aware that the MPC8266ADS board Rev B has not connected
+       Row addres 13 to anything.
+
+       The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
+    */
+    if (cols > 10)
+	    cols = 10;
+
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+    rowst = 32 - (rows + banks + cols + width);
+#endif
+
+   or = ~(sdram_size - 1)    |	/* SDAM address mask	*/
+	  ((banks-1) << 13)   |	/* banks per device	*/
+	  (rowst << 9)        |	/* rowst		*/
+	  ((rows - 9) << 6);	/* numr			*/
+
+
+    /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
+
+    /*
+     * SDAM specifies the number of columns that are multiplexed
+     * (reference AN2165/D), defined to be (columns - 6) for page
+     * interleave, (columns - 8) for bank interleave.
+     *
+     * BSMA is 14 - max(rows, cols).  The bank select lines come
+     * into play above the highest "address" line going into the
+     * the SDRAM.
+     */
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    sdam = cols - 8;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam + 2;
+#else
+    sdam = cols + banks - 8;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_16_CLK       |\
+	     PSDMR_PRETOACT_8W       |\
+	     PSDMR_ACTTORW_8W        |\
+	     PSDMR_WRC_4C            |\
+	     PSDMR_EAMUX             |\
+	     PSDMR_BUFCMD)           |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#else
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_7_CLK        |\
+	     PSDMR_PRETOACT_3W       |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_ACTTORW_2W        |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_WRC_1C            |	/* 1 clock + 7nSec */
+	     EAMUX                   |\
+	     BUFCMD)                 |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#endif
+	/*printf("psdmr = 0x%08x\n", psdmr);*/
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     * Quote from Micron MT48LC8M16A2 data sheet:
+     *
+     *  "...the SDRAM requires a 100uS delay prior to issuing any
+     *  command other than a COMMAND INHIBIT or NOP.  Starting at some
+     *  point during this 100uS period and continuing at least through
+     *  the end of this period, COMMAND INHIBIT or NOP commands should
+     *  be applied."
+     *
+     *  "Once the 100uS delay has been satisfied with at least one COMMAND
+     *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
+     *  should be applied.  All banks must then be precharged, thereby
+     *  placing the device in the all banks idle state."
+     *
+     *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
+     *  performed.  After the AUTO REFRESH cycles are complete, the
+     *  SDRAM is ready for mode register programming."
+     *
+     *  (/emphasis/ mine, gvb)
+     *
+     *  The way I interpret this, Micron start up sequence is:
+     *  1. Issue a PRECHARGE-BANK command (initial precharge)
+     *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+     *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+     *  4. Issue a MODE-SET command to initialize the mode register
+     *
+     *  --------
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+     */
+
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+    memctl->memc_psrt  = psrt;
+
+    memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+    memctl->memc_or2 = or;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+
+    /*
+     * Do it a second time for the second set of chips if the DIMM has
+     * two chip selects (double sided).
+     */
+    if(chipselects > 1)
+	{
+	ramaddr += sdram_size;
+
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
+		memctl->memc_or3 = or;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+		*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+		*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+		*ramaddr = c;
+    }
+
+	/* print info */
+	printf("SDRAM configuration read from SPD\n");
+	printf("\tSize per side = %dMB\n", sdram_size >> 20);
+	printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
+	printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    printf(", Using Bank Based Interleave\n");
+#else
+    printf(", Using Page Based Interleave\n");
+#endif
+	printf("\tTotal size: ");
+
+    /* this delay only needed for original 16MB DIMM...
+     * Not needed for any other memory configuration */
+    if ((sdram_size * chipselects) == (16 *1024 *1024))
+	udelay (250000);
+    return (sdram_size * chipselects);
+	/*return (16 * 1024 * 1024);*/
+}
+
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8308rdb/Makefile b/u-boot/board/freescale/mpc8308rdb/Makefile
new file mode 100644
index 0000000..241a557
--- /dev/null
+++ b/u-boot/board/freescale/mpc8308rdb/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8308rdb/mpc8308rdb.c b/u-boot/board/freescale/mpc8308rdb/mpc8308rdb.c
new file mode 100644
index 0000000..5c54357
--- /dev/null
+++ b/u-boot/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"1.0",
+		"<reserved>",
+		"<reserved>",
+		"<reserved>",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4 : info & 0x03;
+
+	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		return 1;
+	}
+#endif
+
+	return 0;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/u-boot/board/freescale/mpc8308rdb/sdram.c b/u-boot/board/freescale/mpc8308rdb/sdram.c
new file mode 100644
index 0000000..1a6b9c7
--- /dev/null
+++ b/u-boot/board/freescale/mpc8308rdb/sdram.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/u-boot/board/freescale/mpc8313erdb/Makefile b/u-boot/board/freescale/mpc8313erdb/Makefile
new file mode 100644
index 0000000..f18aded
--- /dev/null
+++ b/u-boot/board/freescale/mpc8313erdb/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8313erdb/mpc8313erdb.c b/u-boot/board/freescale/mpc8313erdb/mpc8313erdb.c
new file mode 100644
index 0000000..08f873d
--- /dev/null
+++ b/u-boot/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <ns16550.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8313ERDB\n");
+	return 0;
+}
+
+#ifndef CONFIG_NAND_SPL
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+#else /* CONFIG_NAND_SPL */
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+	             CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
+	              CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8313erdb/sdram.c b/u-boot/board/freescale/mpc8313erdb/sdram.c
new file mode 100644
index 0000000..7aede13
--- /dev/null
+++ b/u-boot/board/freescale/mpc8313erdb/sdram.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+#endif
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+
+	/* Currently we use only one CS, so disable the other bank. */
+	im->ddr.cs_config[1] = 0;
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
+	else
+#endif
+		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
+
+	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+#endif
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	sync();
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/u-boot/board/freescale/mpc8315erdb/Makefile b/u-boot/board/freescale/mpc8315erdb/Makefile
new file mode 100644
index 0000000..f18aded
--- /dev/null
+++ b/u-boot/board/freescale/mpc8315erdb/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8315erdb/mpc8315erdb.c b/u-boot/board/freescale/mpc8315erdb/mpc8315erdb.c
new file mode 100644
index 0000000..5dc558a
--- /dev/null
+++ b/u-boot/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *         Dave Liu <daveliu@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+#ifndef CONFIG_NAND_SPL
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"0.0",
+		"0.1",
+		"1.0",
+		"1.1",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4: info & 0x03;
+
+	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_tsec1_fixup(void *fdt, bd_t *bd)
+{
+	const char disabled[] = "disabled";
+	const char *path;
+	int ret;
+
+	if (hwconfig_arg_cmp("board_type", "tsec1")) {
+		return;
+	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
+		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
+		       "        Assuming board with TSEC1.\n");
+		return;
+	}
+
+	ret = fdt_path_offset(fdt, "/aliases");
+	if (ret < 0) {
+		printf("WARNING: can't find /aliases node\n");
+		return;
+	}
+
+	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
+	if (!path) {
+		printf("WARNING: can't find ethernet0 alias\n");
+		return;
+	}
+
+	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	fdt_fixup_dr_usb(blob, bd);
+	fdt_tsec1_fixup(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */
+	return pci_eth_init(bis);
+}
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8315ERDB\n");
+	return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+		      CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */
diff --git a/u-boot/board/freescale/mpc8315erdb/sdram.c b/u-boot/board/freescale/mpc8315erdb/sdram.c
new file mode 100644
index 0000000..fe8ec1e
--- /dev/null
+++ b/u-boot/board/freescale/mpc8315erdb/sdram.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+static long fixed_sdram(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	/* Currently we use only one CS, so disable the other bank. */
+	im->ddr.cs_config[1] = 0;
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+	else
+		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	sync();
+
+	return msize;
+}
+#else
+static long fixed_sdram(void)
+{
+	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/u-boot/board/freescale/mpc8323erdb/Makefile b/u-boot/board/freescale/mpc8323erdb/Makefile
new file mode 100644
index 0000000..4a1b249
--- /dev/null
+++ b/u-boot/board/freescale/mpc8323erdb/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8323erdb/mpc8323erdb.c b/u-boot/board/freescale/mpc8323erdb/mpc8323erdb.c
new file mode 100644
index 0000000..7a0ff18
--- /dev/null
+++ b/u-boot/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Michael Barkowski <michael.barkowski@freescale.com>
+ * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <command.h>
+#include <libfdt.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <asm/mmu.h>
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* UCC3 */
+	{1,  0, 1, 0, 1}, /* TxD0 */
+	{1,  1, 1, 0, 1}, /* TxD1 */
+	{1,  2, 1, 0, 1}, /* TxD2 */
+	{1,  3, 1, 0, 1}, /* TxD3 */
+	{1,  9, 1, 0, 1}, /* TxER */
+	{1, 12, 1, 0, 1}, /* TxEN */
+	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+	{1,  4, 2, 0, 1}, /* RxD0 */
+	{1,  5, 2, 0, 1}, /* RxD1 */
+	{1,  6, 2, 0, 1}, /* RxD2 */
+	{1,  7, 2, 0, 1}, /* RxD3 */
+	{1,  8, 2, 0, 1}, /* RxER */
+	{1, 10, 2, 0, 1}, /* RxDV */
+	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+	{1, 11, 2, 0, 1}, /* COL */
+	{1, 13, 2, 0, 1}, /* CRS */
+
+	/* UCC2 */
+	{0, 18, 1, 0, 1}, /* TxD0 */
+	{0, 19, 1, 0, 1}, /* TxD1 */
+	{0, 20, 1, 0, 1}, /* TxD2 */
+	{0, 21, 1, 0, 1}, /* TxD3 */
+	{0, 27, 1, 0, 1}, /* TxER */
+	{0, 30, 1, 0, 1}, /* TxEN */
+	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
+
+	{0, 22, 2, 0, 1}, /* RxD0 */
+	{0, 23, 2, 0, 1}, /* RxD1 */
+	{0, 24, 2, 0, 1}, /* RxD2 */
+	{0, 25, 2, 0, 1}, /* RxD3 */
+	{0, 26, 1, 0, 1}, /* RxER */
+	{0, 28, 2, 0, 1}, /* Rx_DV */
+	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
+	{0, 29, 2, 0, 1}, /* COL */
+	{0, 31, 2, 0, 1}, /* CRS */
+
+	{3,  4, 3, 0, 2}, /* MDIO */
+	{3,  5, 1, 0, 2}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	__asm__ __volatile__ ("sync");
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	__asm__ __volatile__ ("sync");
+	return msize;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8323ERDB\n");
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+
+#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
+int mac_read_from_eeprom(void)
+{
+	uchar buf[28];
+	char str[18];
+	int i = 0;
+	unsigned int crc = 0;
+	unsigned char enetvar[32];
+
+	/* Read MAC addresses from EEPROM */
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
+		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+	} else {
+		if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
+			printf("Reading MAC from EEPROM\n");
+			for (i = 0; i < 4; i++) {
+				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
+					sprintf(str,
+						"%02X:%02X:%02X:%02X:%02X:%02X",
+						buf[i * 6], buf[i * 6 + 1],
+						buf[i * 6 + 2], buf[i * 6 + 3],
+						buf[i * 6 + 4], buf[i * 6 + 5]);
+					sprintf((char *)enetvar,
+						i ? "eth%daddr" : "ethaddr", i);
+					setenv((char *)enetvar, str);
+				}
+			}
+		}
+	}
+	return 0;
+}
+#endif				/* CONFIG_I2C_MAC_OFFSET */
diff --git a/u-boot/board/freescale/mpc832xemds/Makefile b/u-boot/board/freescale/mpc832xemds/Makefile
new file mode 100644
index 0000000..4f76eab
--- /dev/null
+++ b/u-boot/board/freescale/mpc832xemds/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc832xemds/mpc832xemds.c b/u-boot/board/freescale/mpc832xemds/mpc832xemds.c
new file mode 100644
index 0000000..d4d4479
--- /dev/null
+++ b/u-boot/board/freescale/mpc832xemds/mpc832xemds.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* ETH3 */
+	{1,  0, 1, 0, 1}, /* TxD0 */
+	{1,  1, 1, 0, 1}, /* TxD1 */
+	{1,  2, 1, 0, 1}, /* TxD2 */
+	{1,  3, 1, 0, 1}, /* TxD3 */
+	{1,  9, 1, 0, 1}, /* TxER */
+	{1, 12, 1, 0, 1}, /* TxEN */
+	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+	{1,  4, 2, 0, 1}, /* RxD0 */
+	{1,  5, 2, 0, 1}, /* RxD1 */
+	{1,  6, 2, 0, 1}, /* RxD2 */
+	{1,  7, 2, 0, 1}, /* RxD3 */
+	{1,  8, 2, 0, 1}, /* RxER */
+	{1, 10, 2, 0, 1}, /* RxDV */
+	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+	{1, 11, 2, 0, 1}, /* COL */
+	{1, 13, 2, 0, 1}, /* CRS */
+
+	/* ETH4 */
+	{1, 18, 1, 0, 1}, /* TxD0 */
+	{1, 19, 1, 0, 1}, /* TxD1 */
+	{1, 20, 1, 0, 1}, /* TxD2 */
+	{1, 21, 1, 0, 1}, /* TxD3 */
+	{1, 27, 1, 0, 1}, /* TxER */
+	{1, 30, 1, 0, 1}, /* TxEN */
+	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
+
+	{1, 22, 2, 0, 1}, /* RxD0 */
+	{1, 23, 2, 0, 1}, /* RxD1 */
+	{1, 24, 2, 0, 1}, /* RxD2 */
+	{1, 25, 2, 0, 1}, /* RxD3 */
+	{1, 26, 1, 0, 1}, /* RxER */
+	{1, 28, 2, 0, 1}, /* Rx_DV */
+	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
+	{1, 29, 2, 0, 1}, /* COL */
+	{1, 31, 2, 0, 1}, /* CRS */
+
+	{3,  4, 3, 0, 2}, /* MDIO */
+	{3,  5, 1, 0, 2}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+	volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
+
+	/* Enable flash write */
+	bcsr[9] &= ~0x08;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CONFIG_SYS_DDR_SIZE != 128)
+#warning Currenly any ddr size other than 128 is not supported
+#endif
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	__asm__ __volatile__ ("sync");
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	__asm__ __volatile__ ("sync");
+	return msize;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC832XEMDS\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/mpc832xemds/pci.c b/u-boot/board/freescale/mpc832xemds/pci.c
new file mode 100644
index 0000000..8cab771
--- /dev/null
+++ b/u-boot/board/freescale/mpc832xemds/pci.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+#endif
+
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	mpc83xx_pci_init(1, reg);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar0 = 0x0;
+	pci_ctrl[0].pibar0 = 0x0;
+	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+	pci_ctrl[0].pitar2 = 0x0;
+	pci_ctrl[0].pibar2 = 0x0;
+	pci_ctrl[0].piebar2 = 0x0;
+	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+	/* Unlock the configuration bit */
+	mpc83xx_pcislave_unlock(0);
+	printf("PCI:   Agent mode enabled\n");
+}
+#else
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+	struct pci_region *reg[] = { pci1_regions };
+#else
+	struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+	/* initialize the PCA9555PW IO expander on the PIB board */
+	pib_init();
+
+#if defined(CONFIG_PCI_66M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#elif defined(CONFIG_PCI_33M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+	printf("PCI clock is 33MHz\n");
+#else
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#endif
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+	udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+	mpc83xx_pci_init(1, reg);
+#else
+	mpc83xx_pci_init(2, reg);
+#endif
+}
+#endif				/* CONFIG_PCISLAVE */
diff --git a/u-boot/board/freescale/mpc8349emds/Makefile b/u-boot/board/freescale/mpc8349emds/Makefile
new file mode 100644
index 0000000..4f76eab
--- /dev/null
+++ b/u-boot/board/freescale/mpc8349emds/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8349emds/mpc8349emds.c b/u-boot/board/freescale/mpc8349emds/mpc8349emds.c
new file mode 100644
index 0000000..365ac37
--- /dev/null
+++ b/u-boot/board/freescale/mpc8349emds/mpc8349emds.c
@@ -0,0 +1,297 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spi.h>
+#include <miiphy.h>
+#include <spd_sdram.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+int board_early_init_f (void)
+{
+	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
+
+	/* Enable flash write */
+	bcsr[1] &= ~0x01;
+
+#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
+	/* Use USB PHY on SYS board */
+	bcsr[5] |= 0x02;
+#endif
+
+	return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+#ifdef CONFIG_DDR_II
+	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+#else
+	im->ddr.csbnds[2].csbnds = 0x0000000f;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.cs_config[0] = 0;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+	/* for 32-bit mode burst length is 8 */
+	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+#endif
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	return msize;
+}
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	/*
+	 * Warning: do not read the BCSR registers here
+	 *
+	 * There is a timing bug in the 8349E and 8349EA BCSR code
+	 * version 1.2 (read from BCSR 11) that will cause the CFI
+	 * flash initialization code to overwrite BCSR 0, disabling
+	 * the serial ports and gigabit ethernet
+	 */
+
+	puts("Board: Freescale MPC8349EMDS\n");
+	return 0;
+}
+
+/*
+ * if MPC8349EMDS is soldered with SDRAM
+ */
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/* setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733; mode register write operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+}
+#endif
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK	0x80000000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat &= ~SPI_CS_MASK;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat |=  SPI_CS_MASK;
+}
+#endif /* CONFIG_HARD_SPI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8349emds/pci.c b/u-boot/board/freescale/mpc8349emds/pci.c
new file mode 100644
index 0000000..832477f
--- /dev/null
+++ b/u-boot/board/freescale/mpc8349emds/pci.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+#endif
+
+#ifndef CONFIG_PCISLAVE
+void pib_init(void)
+{
+	u8 val8, orig_i2c_bus;
+	/*
+	 * Assign PIB PMC slot to desired PCI bus
+	 */
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(PCI_64BIT)
+	val8 = 0xf4;	/* PMC2:PCI1/64-bit */
+#elif defined(PCI_ALL_PCI1)
+	val8 = 0xf3;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
+#elif defined(PCI_ONE_PCI1)
+	val8 = 0xf9;	/* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
+#else
+	val8 = 0xf5;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
+#endif
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+	asm("eieio");
+
+#if defined(PCI_64BIT)
+	printf("PCI1: 64-bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+	printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+	printf("PCI1: 32-bit on PMC1\n");
+	printf("PCI2: 32-bit on PMC2, PMC3\n");
+#else
+	printf("PCI1: 32-bit on PMC1, PMC2\n");
+	printf("PCI2: 32-bit on PMC3\n");
+#endif
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+}
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+	struct pci_region *reg[] = { pci1_regions };
+#else
+	struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+	/* initialize the PCA9555PW IO expander on the PIB board */
+	pib_init();
+
+	/* Enable all 8 PCI_CLK_OUTPUTS */
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+	mpc83xx_pci_init(1, reg);
+#else
+	mpc83xx_pci_init(2, reg);
+#endif
+}
+
+#else
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	mpc83xx_pci_init(1, reg);
+
+	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
+	pci_ctrl->pitar0 = 0x0;
+	pci_ctrl->pibar0 = 0x0;
+	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+	pci_ctrl->pitar1  = 0x0;
+	pci_ctrl->pibar1  = 0x0;
+	pci_ctrl->piebar1 = 0x0;
+	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+	pci_ctrl->pitar2  = 0x0;
+	pci_ctrl->pibar2  = 0x0;
+	pci_ctrl->piebar2 = 0x0;
+	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+	/* Unlock the configuration bit */
+	mpc83xx_pcislave_unlock(0);
+	printf("PCI:   Agent mode enabled\n");
+}
+#endif /* CONFIG_PCISLAVE */
diff --git a/u-boot/board/freescale/mpc8349itx/Makefile b/u-boot/board/freescale/mpc8349itx/Makefile
new file mode 100644
index 0000000..f431316
--- /dev/null
+++ b/u-boot/board/freescale/mpc8349itx/Makefile
@@ -0,0 +1,50 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8349itx/mpc8349itx.c b/u-boot/board/freescale/mpc8349itx/mpc8349itx.c
new file mode 100644
index 0000000..5647579
--- /dev/null
+++ b/u-boot/board/freescale/mpc8349itx/mpc8349itx.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <vsc7385.h>
+#ifdef CONFIG_PCI
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#endif
+#include <spd_sdram.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#ifndef CONFIG_SPD_EEPROM
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 ddr_size;		/* The size of RAM, in bytes */
+	u32 ddr_size_log2 = 0;
+
+	for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+		ddr_size_log2++;
+	}
+
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+
+	/* Only one CS0 for DDR */
+	im->ddr.csbnds[0].csbnds = 0x0000000f;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+
+	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
+	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
+
+	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
+	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
+
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
+	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
+	im->ddr.sdram_mode =
+	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
+	im->ddr.sdram_interval =
+	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
+						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
+	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
+	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
+	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
+	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
+
+	return CONFIG_SYS_DDR_SIZE;
+}
+#endif
+
+#ifdef CONFIG_PCI
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
+	{
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 0x0f,
+	 PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {
+	  PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc83xxmitx_config_table,
+#endif
+	 },
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc83xxmitx_config_table,
+#endif
+	 }
+};
+#endif				/* CONFIG_PCI */
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+#ifdef CONFIG_DDR_ECC
+	volatile ddr83xx_t *ddr = &im->ddr;
+#endif
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#ifdef CONFIG_SPD_EEPROM
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#ifdef CONFIG_DDR_ECC
+	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+		/* Unlike every other board, on the 83xx spd_sdram() returns
+		   megabytes instead of just bytes.  That's why we need to
+		   multiple by 1MB when calling ddr_enable_ecc(). */
+		ddr_enable_ecc(msize * 1048576);
+#endif
+
+	/* return total bus RAM size(bytes) */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_MPC8349ITX
+	puts("Board: Freescale MPC8349E-mITX\n");
+#else
+	puts("Board: Freescale MPC8349E-mITX-GP\n");
+#endif
+
+	return 0;
+}
+
+/*
+ * Implement a work-around for a hardware problem with compact
+ * flash.
+ *
+ * Program the UPM if compact flash is enabled.
+ */
+int misc_init_f(void)
+{
+#ifdef CONFIG_VSC7385_ENET
+	volatile u32 *vsc7385_cpuctrl;
+
+	/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
+	   default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
+	   means it is 0 when the IRQ is not active.  This makes the wire-AND
+	   logic always assert IRQ7 to CPU even if there is no request from the
+	   switch.  Since the compact flash and the switch share the same IRQ,
+	   the Linux kernel will think that the compact flash is requesting irq
+	   and get stuck when it tries to clear the IRQ.  Thus we need to set
+	   the L2_IRQ0 and L2_IRQ1 to active low.
+
+	   The following code sets the L1_IRQ and L2_IRQ polarity to active low.
+	   Without this code, compact flash will not work in Linux because
+	   unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
+	   don't enable compact flash for U-Boot.
+	 */
+
+	vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
+	*vsc7385_cpuctrl |= 0x0c;
+#endif
+
+#ifdef CONFIG_COMPACT_FLASH
+	/* UPM Table Configuration Code */
+	static uint UPMATable[] = {
+		0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
+		0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
+		0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
+	};
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+
+	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
+	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
+	 */
+	immap->im_lbc.mamr = 0x08404440;
+
+	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
+
+	puts("UPMA:  Configured for compact flash\n");
+#endif
+
+	return 0;
+}
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Make sure the EEPROM has the HRCW correctly programmed.
+ * Make sure the RTC is correctly programmed.
+ *
+ * The MPC8349E-mITX can be configured to load the HRCW from
+ * EEPROM instead of flash.  This is controlled via jumpers
+ * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
+ * jumpered), but if they're set to 001 or 010, then the HRCW is
+ * read from the "I2C EEPROM".
+ *
+ * This function makes sure that the I2C EEPROM is programmed
+ * correctly.
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+ */
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_HARD_I2C
+
+	unsigned int orig_bus = i2c_get_bus_num();
+	u8 i2c_data;
+
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
+	u8 ds1339_data[17];
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+	static u8 eeprom_data[] =	/* HRCW data */
+	{
+		0xAA, 0x55, 0xAA,       /* Preamble */
+		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
+		0x02, 0x40,	        /* RCWL ADDR=0x0_0900 */
+		(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
+		(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
+		(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
+		CONFIG_SYS_HRCW_LOW & 0xFF,
+		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
+		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
+		(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
+		(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
+		(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
+		CONFIG_SYS_HRCW_HIGH & 0xFF
+	};
+
+	u8 data[sizeof(eeprom_data)];
+#endif
+
+	printf("Board revision: ");
+	i2c_set_bus_num(1);
+	if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+		printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+	else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+		printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+	else {
+		printf("Unknown\n");
+		rc = 1;
+	}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
+		if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
+			if (i2c_write
+			    (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
+			     sizeof(eeprom_data)) != 0) {
+				puts("Failure writing the HRCW to EEPROM via I2C.\n");
+				rc = 1;
+			}
+		}
+	} else {
+		puts("Failure reading the HRCW from EEPROM via I2C.\n");
+		rc = 1;
+	}
+#endif
+
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
+	i2c_set_bus_num(1);
+
+	if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
+	    == 0) {
+
+		/* Work-around for MPC8349E-mITX bug #13601.
+		   If the RTC does not contain valid register values, the DS1339
+		   Linux driver will not work.
+		 */
+
+		/* Make sure status register bits 6-2 are zero */
+		ds1339_data[0x0f] &= ~0x7c;
+
+		/* Check for a valid day register value */
+		ds1339_data[0x03] &= ~0xf8;
+		if (ds1339_data[0x03] == 0) {
+			ds1339_data[0x03] = 1;
+		}
+
+		/* Check for a valid date register value */
+		ds1339_data[0x04] &= ~0xc0;
+		if ((ds1339_data[0x04] == 0) ||
+		    ((ds1339_data[0x04] & 0x0f) > 9) ||
+		    (ds1339_data[0x04] >= 0x32)) {
+			ds1339_data[0x04] = 1;
+		}
+
+		/* Check for a valid month register value */
+		ds1339_data[0x05] &= ~0x60;
+
+		if ((ds1339_data[0x05] == 0) ||
+		    ((ds1339_data[0x05] & 0x0f) > 9) ||
+		    ((ds1339_data[0x05] >= 0x13)
+		     && (ds1339_data[0x05] <= 0x19))) {
+			ds1339_data[0x05] = 1;
+		}
+
+		/* Enable Oscillator and rate select */
+		ds1339_data[0x0e] = 0x1c;
+
+		/* Work-around for MPC8349E-mITX bug #13330.
+		   Ensure that the RTC control register contains the value 0x1c.
+		   This affects SATA performance.
+		 */
+
+		if (i2c_write
+		    (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
+		     sizeof(ds1339_data))) {
+			puts("Failure writing to the RTC via I2C.\n");
+			rc = 1;
+		}
+	} else {
+		puts("Failure reading from the RTC via I2C.\n");
+		rc = 1;
+	}
+#endif
+
+	i2c_set_bus_num(orig_bus);
+#endif
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8349itx/pci.c b/u-boot/board/freescale/mpc8349itx/pci.c
new file mode 100644
index 0000000..7d30d9b
--- /dev/null
+++ b/u-boot/board/freescale/mpc8349itx/pci.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+#endif
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+	struct pci_region *reg[] = { pci1_regions };
+#else
+	struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+	u8 reg8;
+
+#ifdef CONFIG_HARD_I2C
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
+	    (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
+		if (reg8 & I2C_8574_PCI66)
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+		else
+			clk->occr = 0xff600001;	/* 33 MHz PCI */
+	} else {
+		clk->occr = 0xff600001;	/* 33 MHz PCI */
+	}
+#else
+	clk->occr = 0xff000000;	/* 66 MHz PCI */
+#endif
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+	udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+	mpc83xx_pci_init(1, reg);
+#else
+	mpc83xx_pci_init(2, reg);
+#endif
+}
diff --git a/u-boot/board/freescale/mpc8360emds/Makefile b/u-boot/board/freescale/mpc8360emds/Makefile
new file mode 100644
index 0000000..4f76eab
--- /dev/null
+++ b/u-boot/board/freescale/mpc8360emds/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8360emds/mpc8360emds.c b/u-boot/board/freescale/mpc8360emds/mpc8360emds.c
new file mode 100644
index 0000000..0babd26
--- /dev/null
+++ b/u-boot/board/freescale/mpc8360emds/mpc8360emds.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <spd_sdram.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/fsl_enet.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <hwconfig.h>
+#include <fdt_support.h>
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+#include "../../../drivers/qe/uec.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GETH1 */
+	{0,  3, 1, 0, 1}, /* TxD0 */
+	{0,  4, 1, 0, 1}, /* TxD1 */
+	{0,  5, 1, 0, 1}, /* TxD2 */
+	{0,  6, 1, 0, 1}, /* TxD3 */
+	{1,  6, 1, 0, 3}, /* TxD4 */
+	{1,  7, 1, 0, 1}, /* TxD5 */
+	{1,  9, 1, 0, 2}, /* TxD6 */
+	{1, 10, 1, 0, 2}, /* TxD7 */
+	{0,  9, 2, 0, 1}, /* RxD0 */
+	{0, 10, 2, 0, 1}, /* RxD1 */
+	{0, 11, 2, 0, 1}, /* RxD2 */
+	{0, 12, 2, 0, 1}, /* RxD3 */
+	{0, 13, 2, 0, 1}, /* RxD4 */
+	{1,  1, 2, 0, 2}, /* RxD5 */
+	{1,  0, 2, 0, 2}, /* RxD6 */
+	{1,  4, 2, 0, 2}, /* RxD7 */
+	{0,  7, 1, 0, 1}, /* TX_EN */
+	{0,  8, 1, 0, 1}, /* TX_ER */
+	{0, 15, 2, 0, 1}, /* RX_DV */
+	{0, 16, 2, 0, 1}, /* RX_ER */
+	{0,  0, 2, 0, 1}, /* RX_CLK */
+	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
+	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
+	/* GETH2 */
+	{0, 17, 1, 0, 1}, /* TxD0 */
+	{0, 18, 1, 0, 1}, /* TxD1 */
+	{0, 19, 1, 0, 1}, /* TxD2 */
+	{0, 20, 1, 0, 1}, /* TxD3 */
+	{1,  2, 1, 0, 1}, /* TxD4 */
+	{1,  3, 1, 0, 2}, /* TxD5 */
+	{1,  5, 1, 0, 3}, /* TxD6 */
+	{1,  8, 1, 0, 3}, /* TxD7 */
+	{0, 23, 2, 0, 1}, /* RxD0 */
+	{0, 24, 2, 0, 1}, /* RxD1 */
+	{0, 25, 2, 0, 1}, /* RxD2 */
+	{0, 26, 2, 0, 1}, /* RxD3 */
+	{0, 27, 2, 0, 1}, /* RxD4 */
+	{1, 12, 2, 0, 2}, /* RxD5 */
+	{1, 13, 2, 0, 3}, /* RxD6 */
+	{1, 11, 2, 0, 2}, /* RxD7 */
+	{0, 21, 1, 0, 1}, /* TX_EN */
+	{0, 22, 1, 0, 1}, /* TX_ER */
+	{0, 29, 2, 0, 1}, /* RX_DV */
+	{0, 30, 2, 0, 1}, /* RX_ER */
+	{0, 31, 2, 0, 1}, /* RX_CLK */
+	{2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
+	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
+
+	{0,  1, 3, 0, 2}, /* MDIO */
+	{0,  2, 1, 0, 1}, /* MDC */
+
+	{5,  0, 1, 0, 2}, /* UART2_SOUT */
+	{5,  1, 2, 0, 3}, /* UART2_CTS */
+	{5,  2, 1, 0, 1}, /* UART2_RTS */
+	{5,  3, 2, 0, 2}, /* UART2_SIN */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
+static int board_handle_erratum2(void)
+{
+	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
+	       REVID_MINOR(immr->sysconf.spridr) == 1;
+}
+
+int board_early_init_f(void)
+{
+	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+	/* Enable flash write */
+	bcsr[0xa] &= ~0x04;
+
+	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
+	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
+		bcsr[0xe] = 0x30;
+
+	/* Enable second UART */
+	bcsr[0x9] &= ~0x01;
+
+	if (board_handle_erratum2()) {
+		void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
+
+		/*
+		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+		 */
+		setbits_be32(immap, 0x0c003000);
+
+		/*
+		 * IMMR + 0x14AC[20:27] = 10101010
+		 * (data delay for both UCC's)
+		 */
+		clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
+	}
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_UEC_ETH
+static uec_info_t uec_info[] = {
+#ifdef CONFIG_UEC_ETH1
+	STD_UEC_INFO(1),
+#endif
+#ifdef CONFIG_UEC_ETH2
+	STD_UEC_INFO(2),
+#endif
+};
+
+int board_eth_init(bd_t *bd)
+{
+	if (board_handle_erratum2()) {
+		int i;
+
+		for (i = 0; i < ARRAY_SIZE(uec_info); i++)
+			uec_info[i].enet_interface_type = RGMII_RXID;
+			uec_info[i].speed = 1000;
+	}
+	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
+}
+#endif /* CONFIG_UEC_ETH */
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+static int sdram_init(unsigned int base);
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 lbc_sdram_size;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize DDR ECC byte
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
+	if (!msize)
+		msize = lbc_sdram_size;
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+#ifdef CONFIG_DDR_II
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+#else
+	im->ddr.csbnds[0].csbnds = 0x00000007;
+	im->ddr.csbnds[1].csbnds = 0x0008000f;
+
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+#endif
+	udelay(200);
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+#endif				/*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8360EMDS\n");
+	return 0;
+}
+
+/*
+ * if MPC8360EMDS is soldered with SDRAM
+ */
+#ifdef CONFIG_SYS_LB_SDRAM
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+static int sdram_init(unsigned int base)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
+	int rem = base % sdram_size;
+	uint *sdram_addr;
+
+	/* window base address should be aligned to the window size */
+	if (rem)
+		base = base - rem + sdram_size;
+
+	sdram_addr = (uint *)base;
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_br(2, base | CONFIG_SYS_BR2);
+	set_lbc_or(2, CONFIG_SYS_OR2);
+	immap->sysconf.lblaw[2].bar = base;
+	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
+
+	/*setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;	/* Normal Operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;	/* Precharge All Banks */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/*
+	 * We need do 8 times auto refresh operation.
+	 */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;	/* 1 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 2 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 3 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 4 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 5 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 6 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 7 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 8 times */
+	udelay(100);
+
+	/* Mode register write operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	asm("sync");
+	*(sdram_addr + 0xcc) = 0xff;
+	udelay(100);
+
+	/* Normal operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/*
+	 * In non-aligned case we don't [normally] use that memory because
+	 * there is a hole.
+	 */
+	if (rem)
+		return 0;
+	return CONFIG_SYS_LBC_SDRAM_SIZE;
+}
+#else
+static int sdram_init(unsigned int base) { return 0; }
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
+		return;
+
+	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
+			   "peripheral", sizeof("peripheral"), 1);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_board_fixup_qe_usb(blob, bd);
+	/*
+	 * mpc8360ea pb mds errata 2: RGMII timing
+	 * if on mpc8360ea rev. 2.1,
+	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
+	 */
+	if (board_handle_erratum2()) {
+		int nodeoffset;
+		const char *prop;
+		int path;
+
+		nodeoffset = fdt_path_offset(blob, "/aliases");
+		if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+			/* fixup UCC 1 if using rgmii-id mode */
+			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+			if (prop) {
+				path = fdt_path_offset(blob, prop);
+				prop = fdt_getprop(blob, path,
+				                   "phy-connection-type", 0);
+				if (prop && (strcmp(prop, "rgmii-id") == 0))
+					fdt_fixup_phy_connection(blob, path,
+								RGMII_RXID);
+			}
+#endif
+#if defined(CONFIG_HAS_ETH1)
+			/* fixup UCC 2 if using rgmii-id mode */
+			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+			if (prop) {
+				path = fdt_path_offset(blob, prop);
+				prop = fdt_getprop(blob, path,
+				                   "phy-connection-type", 0);
+				if (prop && (strcmp(prop, "rgmii-id") == 0))
+					fdt_fixup_phy_connection(blob, path,
+								RGMII_RXID);
+			}
+#endif
+		}
+	}
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8360emds/pci.c b/u-boot/board/freescale/mpc8360emds/pci.c
new file mode 100644
index 0000000..5466a08
--- /dev/null
+++ b/u-boot/board/freescale/mpc8360emds/pci.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+#endif
+
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+	mpc83xx_pci_init(1, reg);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar0 = 0x0;
+	pci_ctrl[0].pibar0 = 0x0;
+	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+	pci_ctrl[0].pitar2 = 0x0;
+	pci_ctrl[0].pibar2 = 0x0;
+	pci_ctrl[0].piebar2 = 0x0;
+	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+	/* Unlock the configuration bit */
+	mpc83xx_pcislave_unlock(0);
+	printf("PCI:   Agent mode enabled\n");
+}
+#else
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+	struct pci_region *reg[] = { pci1_regions };
+#else
+	struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+	/* initialize the PCA9555PW IO expander on the PIB board */
+	pib_init();
+
+#if defined(CONFIG_PCI_66M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#elif defined(CONFIG_PCI_33M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+	printf("PCI clock is 33MHz\n");
+#else
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#endif
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+	udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+	mpc83xx_pci_init(1, reg);
+#else
+	mpc83xx_pci_init(2, reg);
+#endif
+}
+#endif				/* CONFIG_PCISLAVE */
diff --git a/u-boot/board/freescale/mpc8360erdk/Makefile b/u-boot/board/freescale/mpc8360erdk/Makefile
new file mode 100644
index 0000000..107bdc3
--- /dev/null
+++ b/u-boot/board/freescale/mpc8360erdk/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8360erdk/mpc8360erdk.c b/u-boot/board/freescale/mpc8360erdk/mpc8360erdk.c
new file mode 100644
index 0000000..2baa11a
--- /dev/null
+++ b/u-boot/board/freescale/mpc8360erdk/mpc8360erdk.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <libfdt.h>
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* MDIO */
+	{0,  1, 3, 0, 2}, /* MDIO */
+	{0,  2, 1, 0, 1}, /* MDC */
+
+	/* UCC1 - UEC (Gigabit) */
+	{0,  3, 1, 0, 1}, /* TxD0 */
+	{0,  4, 1, 0, 1}, /* TxD1 */
+	{0,  5, 1, 0, 1}, /* TxD2 */
+	{0,  6, 1, 0, 1}, /* TxD3 */
+	{0,  9, 2, 0, 1}, /* RxD0 */
+	{0, 10, 2, 0, 1}, /* RxD1 */
+	{0, 11, 2, 0, 1}, /* RxD2 */
+	{0, 12, 2, 0, 1}, /* RxD3 */
+	{0,  7, 1, 0, 1}, /* TX_EN */
+	{0,  8, 1, 0, 1}, /* TX_ER */
+	{0, 15, 2, 0, 1}, /* RX_DV */
+	{0,  0, 2, 0, 1}, /* RX_CLK */
+	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
+	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
+
+	/* UCC2 - UEC (Gigabit) */
+	{0, 17, 1, 0, 1}, /* TxD0 */
+	{0, 18, 1, 0, 1}, /* TxD1 */
+	{0, 19, 1, 0, 1}, /* TxD2 */
+	{0, 20, 1, 0, 1}, /* TxD3 */
+	{0, 23, 2, 0, 1}, /* RxD0 */
+	{0, 24, 2, 0, 1}, /* RxD1 */
+	{0, 25, 2, 0, 1}, /* RxD2 */
+	{0, 26, 2, 0, 1}, /* RxD3 */
+	{0, 21, 1, 0, 1}, /* TX_EN */
+	{0, 22, 1, 0, 1}, /* TX_ER */
+	{0, 29, 2, 0, 1}, /* RX_DV */
+	{0, 31, 2, 0, 1}, /* RX_CLK */
+	{2,  2, 1, 0, 2}, /* GTX_CLK - CLK10 */
+	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
+
+	/* UCC7 - UEC */
+	{4,  0, 1, 0, 1}, /* TxD0 */
+	{4,  1, 1, 0, 1}, /* TxD1 */
+	{4,  2, 1, 0, 1}, /* TxD2 */
+	{4,  3, 1, 0, 1}, /* TxD3 */
+	{4,  6, 2, 0, 1}, /* RxD0 */
+	{4,  7, 2, 0, 1}, /* RxD1 */
+	{4,  8, 2, 0, 1}, /* RxD2 */
+	{4,  9, 2, 0, 1}, /* RxD3 */
+	{4,  4, 1, 0, 1}, /* TX_EN */
+	{4,  5, 1, 0, 1}, /* TX_ER */
+	{4, 12, 2, 0, 1}, /* RX_DV */
+	{4, 13, 2, 0, 1}, /* RX_ER */
+	{4, 10, 2, 0, 1}, /* COL */
+	{4, 11, 2, 0, 1}, /* CRS */
+	{2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
+	{2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
+
+	/* UCC4 - UEC */
+	{1, 14, 1, 0, 1}, /* TxD0 */
+	{1, 15, 1, 0, 1}, /* TxD1 */
+	{1, 16, 1, 0, 1}, /* TxD2 */
+	{1, 17, 1, 0, 1}, /* TxD3 */
+	{1, 20, 2, 0, 1}, /* RxD0 */
+	{1, 21, 2, 0, 1}, /* RxD1 */
+	{1, 22, 2, 0, 1}, /* RxD2 */
+	{1, 23, 2, 0, 1}, /* RxD3 */
+	{1, 18, 1, 0, 1}, /* TX_EN */
+	{1, 19, 1, 0, 2}, /* TX_ER */
+	{1, 26, 2, 0, 1}, /* RX_DV */
+	{1, 27, 2, 0, 1}, /* RX_ER */
+	{1, 24, 2, 0, 1}, /* COL */
+	{1, 25, 2, 0, 1}, /* CRS */
+	{2,  6, 2, 0, 1}, /* TX_CLK - CLK7 */
+	{2,  7, 2, 0, 1}, /* RX_CLK - CLK8 */
+
+	/* PCI1 */
+	{5,  4, 2, 0, 3}, /* PCI_M66EN */
+	{5,  5, 1, 0, 3}, /* PCI_INTA */
+	{5,  6, 1, 0, 3}, /* PCI_RSTO */
+	{5,  7, 3, 0, 3}, /* PCI_C_BE0 */
+	{5,  8, 3, 0, 3}, /* PCI_C_BE1 */
+	{5,  9, 3, 0, 3}, /* PCI_C_BE2 */
+	{5, 10, 3, 0, 3}, /* PCI_C_BE3 */
+	{5, 11, 3, 0, 3}, /* PCI_PAR */
+	{5, 12, 3, 0, 3}, /* PCI_FRAME */
+	{5, 13, 3, 0, 3}, /* PCI_TRDY */
+	{5, 14, 3, 0, 3}, /* PCI_IRDY */
+	{5, 15, 3, 0, 3}, /* PCI_STOP */
+	{5, 16, 3, 0, 3}, /* PCI_DEVSEL */
+	{5, 17, 0, 0, 0}, /* PCI_IDSEL */
+	{5, 18, 3, 0, 3}, /* PCI_SERR */
+	{5, 19, 3, 0, 3}, /* PCI_PERR */
+	{5, 20, 3, 0, 3}, /* PCI_REQ0 */
+	{5, 21, 2, 0, 3}, /* PCI_REQ1 */
+	{5, 22, 2, 0, 3}, /* PCI_GNT2 */
+	{5, 23, 3, 0, 3}, /* PCI_GNT0 */
+	{5, 24, 1, 0, 3}, /* PCI_GNT1 */
+	{5, 25, 1, 0, 3}, /* PCI_GNT2 */
+	{5, 26, 0, 0, 0}, /* PCI_CLK0 */
+	{5, 27, 0, 0, 0}, /* PCI_CLK1 */
+	{5, 28, 0, 0, 0}, /* PCI_CLK2 */
+	{5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
+	{6,  0, 3, 0, 3}, /* PCI_AD0 */
+	{6,  1, 3, 0, 3}, /* PCI_AD1 */
+	{6,  2, 3, 0, 3}, /* PCI_AD2 */
+	{6,  3, 3, 0, 3}, /* PCI_AD3 */
+	{6,  4, 3, 0, 3}, /* PCI_AD4 */
+	{6,  5, 3, 0, 3}, /* PCI_AD5 */
+	{6,  6, 3, 0, 3}, /* PCI_AD6 */
+	{6,  7, 3, 0, 3}, /* PCI_AD7 */
+	{6,  8, 3, 0, 3}, /* PCI_AD8 */
+	{6,  9, 3, 0, 3}, /* PCI_AD9 */
+	{6, 10, 3, 0, 3}, /* PCI_AD10 */
+	{6, 11, 3, 0, 3}, /* PCI_AD11 */
+	{6, 12, 3, 0, 3}, /* PCI_AD12 */
+	{6, 13, 3, 0, 3}, /* PCI_AD13 */
+	{6, 14, 3, 0, 3}, /* PCI_AD14 */
+	{6, 15, 3, 0, 3}, /* PCI_AD15 */
+	{6, 16, 3, 0, 3}, /* PCI_AD16 */
+	{6, 17, 3, 0, 3}, /* PCI_AD17 */
+	{6, 18, 3, 0, 3}, /* PCI_AD18 */
+	{6, 19, 3, 0, 3}, /* PCI_AD19 */
+	{6, 20, 3, 0, 3}, /* PCI_AD20 */
+	{6, 21, 3, 0, 3}, /* PCI_AD21 */
+	{6, 22, 3, 0, 3}, /* PCI_AD22 */
+	{6, 23, 3, 0, 3}, /* PCI_AD23 */
+	{6, 24, 3, 0, 3}, /* PCI_AD24 */
+	{6, 25, 3, 0, 3}, /* PCI_AD25 */
+	{6, 26, 3, 0, 3}, /* PCI_AD26 */
+	{6, 27, 3, 0, 3}, /* PCI_AD27 */
+	{6, 28, 3, 0, 3}, /* PCI_AD28 */
+	{6, 29, 3, 0, 3}, /* PCI_AD29 */
+	{6, 30, 3, 0, 3}, /* PCI_AD30 */
+	{6, 31, 3, 0, 3}, /* PCI_AD31 */
+
+	/* NAND */
+	{4, 18, 2, 0, 0}, /* NAND_RYnBY */
+
+	/* DUART - UART2 */
+	{5,  0, 1, 0, 2}, /* UART2_SOUT */
+	{5,  2, 1, 0, 1}, /* UART2_RTS */
+	{5,  3, 2, 0, 2}, /* UART2_SIN */
+	{5,  1, 2, 0, 3}, /* UART2_CTS */
+
+	/* UCC5 - UART3 */
+	{3,  0, 1, 0, 1}, /* UART3_TX */
+	{3,  4, 1, 0, 1}, /* UART3_RTS */
+	{3,  6, 2, 0, 1}, /* UART3_RX */
+	{3, 12, 2, 0, 0}, /* UART3_CTS */
+	{3, 13, 2, 0, 0}, /* UCC5_CD */
+
+	/* UCC6 - UART4 */
+	{3, 14, 1, 0, 1}, /* UART4_TX */
+	{3, 18, 1, 0, 1}, /* UART4_RTS */
+	{3, 20, 2, 0, 1}, /* UART4_RX */
+	{3, 26, 2, 0, 0}, /* UART4_CTS */
+	{3, 27, 2, 0, 0}, /* UCC6_CD */
+
+	/* Fujitsu MB86277 (MINT) graphics controller */
+	{0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
+	{1,  5, 1, 0, 0}, /* nXRST_GRAPHICS */
+	{1,  7, 1, 0, 0}, /* LVDS_BKLT_CTR */
+	{2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
+
+	/* AD7843 ADC/Touchscreen controller */
+	{4, 14, 1, 0, 0}, /* SPI_nCS0 */
+	{4, 28, 3, 0, 3}, /* SPI_MOSI */
+	{4, 29, 3, 0, 3}, /* SPI_MISO */
+	{4, 30, 3, 0, 3}, /* SPI_CLK */
+
+	/* Freescale QUICC Engine USB Host Controller (FHCI) */
+	{1,  2, 1, 0, 3}, /* USBOE */
+	{1,  3, 1, 0, 3}, /* USBTP */
+	{1,  8, 1, 0, 1}, /* USBTN */
+	{1,  9, 2, 1, 3}, /* USBRP */
+	{1, 10, 2, 0, 3}, /* USBRXD */
+	{1, 11, 2, 1, 3}, /* USBRN */
+	{2, 20, 2, 0, 1}, /* CLK21 */
+	{4, 20, 1, 0, 0}, /* SPEED */
+	{4, 21, 1, 0, 0}, /* SUSPND */
+
+	/* END of table */
+	{0,  0, 0, 0, QE_IOP_TAB_END},
+};
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
+	u32 val;
+
+	/*
+	 * Because of errata in the UCCs, we have to write to the reserved
+	 * registers to slow the clocks down.
+	 */
+	val = in_be32(reg);
+	/* UCC1 */
+	val |= 0x00003000;
+	/* UCC2 */
+	val |= 0x0c000000;
+	out_be32(reg, val);
+
+	return 0;
+}
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1)
+			return -1;
+	}
+
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	udelay(200);
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+	msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize DDR ECC byte
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale/Logic MPC8360ERDK\n");
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+		.size = CONFIG_SYS_PCI1_MEM_SIZE,
+		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+		.size = CONFIG_SYS_PCI1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions, };
+
+#if defined(CONFIG_PCI_33M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+		    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+	printf("PCI clock is 33MHz\n");
+#else
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#endif
+
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	ft_pci_setup(blob, bd);
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8360erdk/nand.c b/u-boot/board/freescale/mpc8360erdk/nand.c
new file mode 100644
index 0000000..92d56a3
--- /dev/null
+++ b/u-boot/board/freescale/mpc8360erdk/nand.c
@@ -0,0 +1,92 @@
+/*
+ * MPC8360E-RDK support for the NAND on FSL UPM
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_83xx.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/fsl_upm.h>
+#include <nand.h>
+
+static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
+
+static const u32 upm_array[] = {
+	0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words  0 to  3 */
+	0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words  4 to  7 */
+	0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words  8 to 11 */
+	0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
+	0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
+	0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
+	0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
+	0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
+	0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
+	0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
+	0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
+	0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
+	0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
+	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
+	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
+	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
+};
+
+static void upm_setup(struct fsl_upm *upm)
+{
+	int i;
+
+	/* write upm array */
+	out_be32(upm->mxmr, MxMR_OP_WARR);
+
+	for (i = 0; i < 64; i++) {
+		out_be32(upm->mdr, upm_array[i]);
+		out_8(upm->io_addr, 0x0);
+	}
+
+	/* normal operation */
+	out_be32(upm->mxmr, MxMR_OP_NORM);
+	while (in_be32(upm->mxmr) != MxMR_OP_NORM)
+		eieio();
+}
+
+static int dev_ready(int chip_nr)
+{
+	if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
+		debug("nand ready\n");
+		return 1;
+	}
+
+	debug("nand busy\n");
+	return 0;
+}
+
+static struct fsl_upm_nand fun = {
+	.upm = {
+		.io_addr = (void *)CONFIG_SYS_NAND_BASE,
+	},
+	.width = 8,
+	.upm_cmd_offset = 8,
+	.upm_addr_offset = 16,
+	.dev_ready = dev_ready,
+	.wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
+	.chip_delay = 50,
+};
+
+int board_nand_init(struct nand_chip *nand)
+{
+	fun.upm.mxmr = &im->im_lbc.mamr;
+	fun.upm.mdr = &im->im_lbc.mdr;
+	fun.upm.mar = &im->im_lbc.mar;
+
+	upm_setup(&fun.upm);
+
+	return fsl_upm_nand_init(nand, &fun);
+}
diff --git a/u-boot/board/freescale/mpc837xemds/Makefile b/u-boot/board/freescale/mpc837xemds/Makefile
new file mode 100644
index 0000000..4f76eab
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xemds/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc837xemds/mpc837xemds.c b/u-boot/board/freescale/mpc837xemds/mpc837xemds.c
new file mode 100644
index 0000000..51dd692
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xemds/mpc837xemds.c
@@ -0,0 +1,342 @@
+/*
+ * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * CREDITS: Kim Phillips contribute to LIBFDT code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <asm/fsl_enet.h>
+#include <spd_sdram.h>
+#include <tsec.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include "pci.h"
+#include "../common/pq-mds-pib.h"
+
+int board_early_init_f(void)
+{
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+	/* Enable flash write */
+	bcsr[0x9] &= ~0x04;
+	/* Clear all of the interrupt of BCSR */
+	bcsr[0xe] = 0xff;
+
+#ifdef CONFIG_FSL_SERDES
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+
+	/* we check only part num, and don't look for CPU revisions */
+	switch (PARTID_NO_E(spridr)) {
+	case SPR_8377:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	case SPR_8378:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
+				FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
+		break;
+	case SPR_8379:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	default:
+		printf("serdes not configured: unknown CPU part number: "
+				"%04x\n", spridr >> 16);
+		break;
+	}
+#endif /* CONFIG_FSL_SERDES */
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+	if (!hwconfig("esdhc"))
+		return 0;
+
+	/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
+	bcsr[0xc] |= 0x4c;
+
+	/* Set proper bits in SICR to allow SD signals through */
+	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+	clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
+			SICRH_GPIO2_E_SD | SICRH_SPI_SD);
+
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
+int board_eth_init(bd_t *bd)
+{
+	struct tsec_info_struct tsec_info[2];
+	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+	u32 rcwh = in_be32(&im->reset.rcwh);
+	u32 tsec_mode;
+	int num = 0;
+
+	/* New line after Net: */
+	printf("\n");
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+
+	printf(CONFIG_TSEC1_NAME ": ");
+
+	tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
+	if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
+		printf("RGMII\n");
+		/* this is default, no need to fixup */
+	} else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
+		printf("SGMII\n");
+		tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
+		tsec_info[num].flags = TSEC_GIGABIT;
+	} else {
+		printf("unsupported PHY type\n");
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+
+	printf(CONFIG_TSEC2_NAME ": ");
+
+	tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
+	if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
+		printf("RGMII\n");
+		/* this is default, no need to fixup */
+	} else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
+		printf("SGMII\n");
+		tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+		tsec_info[num].flags = TSEC_GIGABIT;
+	} else {
+		printf("unsupported PHY type\n");
+	}
+	num++;
+#endif
+	return tsec_eth_init(bd, tsec_info, num);
+}
+
+static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
+			    int phy_addr)
+{
+	const u32 *ph;
+	int off;
+	int err;
+
+	off = fdt_path_offset(blob, alias);
+	if (off < 0) {
+		printf("WARNING: could not find %s alias: %s.\n", alias,
+			fdt_strerror(off));
+		return;
+	}
+
+	err = fdt_fixup_phy_connection(blob, off, SGMII);
+
+	if (err) {
+		printf("WARNING: could not set phy-connection-type for %s: "
+			"%s.\n", alias, fdt_strerror(err));
+		return;
+	}
+
+	ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
+	if (!ph) {
+		printf("WARNING: could not get phy-handle for %s.\n",
+			alias);
+		return;
+	}
+
+	off = fdt_node_offset_by_phandle(blob, *ph);
+	if (off < 0) {
+		printf("WARNING: could not get phy node for %s: %s\n", alias,
+			fdt_strerror(off));
+		return;
+	}
+
+	phy_addr = cpu_to_fdt32(phy_addr);
+	err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
+	if (err < 0) {
+		printf("WARNING: could not set phy node's reg for %s: "
+			"%s.\n", alias, fdt_strerror(err));
+		return;
+	}
+}
+
+static void ft_tsec_fixup(void *blob, bd_t *bd)
+{
+	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+	u32 rcwh = in_be32(&im->reset.rcwh);
+	u32 tsec_mode;
+
+#ifdef CONFIG_TSEC1
+	tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
+	if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
+		__ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
+#endif
+
+#ifdef CONFIG_TSEC2
+	tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
+	if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
+		__ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
+#endif
+}
+#else
+static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
+#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize DDR ECC byte */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* return total bus DDR size(bytes) */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+#if (CONFIG_SYS_DDR_SIZE != 512)
+#warning Currenly any ddr size other than 512 is not supported
+#endif
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+	udelay(50000);
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	udelay(1000);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	udelay(1000);
+
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	__asm__ __volatile__("sync");
+	udelay(1000);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	udelay(2000);
+	return CONFIG_SYS_DDR_SIZE;
+}
+#endif /*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC837xEMDS\n");
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+int board_pci_host_broken(void)
+{
+	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+	const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
+
+	/* It's always OK in case of external arbiter. */
+	if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
+		return 0;
+
+	if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
+		return 1;
+
+	return 0;
+}
+
+static void ft_pci_fixup(void *blob, bd_t *bd)
+{
+	const char *status = "broken (no arbiter)";
+	int off;
+	int err;
+
+	off = fdt_path_offset(blob, "pci0");
+	if (off < 0) {
+		printf("WARNING: could not find pci0 alias: %s.\n",
+			fdt_strerror(off));
+		return;
+	}
+
+	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+	if (err) {
+		printf("WARNING: could not set status for pci0: %s.\n",
+			fdt_strerror(err));
+		return;
+	}
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	ft_tsec_fixup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+	if (board_pci_host_broken())
+		ft_pci_fixup(blob, bd);
+	ft_pcie_fixup(blob, bd);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/u-boot/board/freescale/mpc837xemds/pci.c b/u-boot/board/freescale/mpc837xemds/pci.c
new file mode 100644
index 0000000..edb3ff0
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xemds/pci.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/fsl_i2c.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static int is_pex_x2(void)
+{
+	const char *pex_x2 = getenv("pex_x2");
+
+	if (pex_x2 && !strcmp(pex_x2, "yes"))
+		return 1;
+	return 0;
+}
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+	int pex2 = is_pex_x2();
+
+	if (board_pci_host_broken())
+		goto skip_pci;
+
+	/* Enable all 5 PCI_CLK_OUTPUTS */
+	clk->occr |= 0xf8000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	udelay(2000);
+
+	mpc83xx_pci_init(1, reg);
+skip_pci:
+	/* There is no PEX in MPC8379 parts. */
+	if (PARTID_NO_E(spridr) == SPR_8379)
+		return;
+
+	if (pex2)
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+	else
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	if (!pex2)
+		out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
+}
+
+void ft_pcie_fixup(void *blob, bd_t *bd)
+{
+	const char *status = "disabled (PCIE1 is x2)";
+
+	if (!is_pex_x2())
+		return;
+
+	do_fixup_by_path(blob, "pci2", "status", status,
+			 strlen(status) + 1, 1);
+}
diff --git a/u-boot/board/freescale/mpc837xemds/pci.h b/u-boot/board/freescale/mpc837xemds/pci.h
new file mode 100644
index 0000000..fd7a916
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xemds/pci.h
@@ -0,0 +1,6 @@
+#ifndef __BOARD_MPC837XEMDS_PCI_H
+#define __BOARD_MPC837XEMDS_PCI_H
+
+extern void ft_pcie_fixup(void *blob, bd_t *bd);
+
+#endif /* __BOARD_MPC837XEMDS_PCI_H */
diff --git a/u-boot/board/freescale/mpc837xerdb/Makefile b/u-boot/board/freescale/mpc837xerdb/Makefile
new file mode 100644
index 0000000..4f76eab
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xerdb/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c b/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c
new file mode 100644
index 0000000..d636796
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Kevin Lam <kevin.lam@freescale.com>
+ * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <vsc7385.h>
+#include <fsl_esdhc.h>
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize DDR ECC byte */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	/* return total bus DDR size(bytes) */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+	udelay(50000);
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	udelay(1000);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	udelay(1000);
+
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+	udelay(1000);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	udelay(2000);
+	return CONFIG_SYS_DDR_SIZE;
+}
+#endif	/*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC837xERDB\n");
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_FSL_SERDES
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+
+	/* we check only part num, and don't look for CPU revisions */
+	switch (PARTID_NO_E(spridr)) {
+	case SPR_8377:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	case SPR_8378:
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	case SPR_8379:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	default:
+		printf("serdes not configured: unknown CPU part number: "
+		       "%04x\n", spridr >> 16);
+		break;
+	}
+#endif /* CONFIG_FSL_SERDES */
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+
+	if (!hwconfig("esdhc"))
+		return 0;
+
+	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+	clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
+
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/u-boot/board/freescale/mpc837xerdb/pci.c b/u-boot/board/freescale/mpc837xerdb/pci.c
new file mode 100644
index 0000000..3512bd4
--- /dev/null
+++ b/u-boot/board/freescale/mpc837xerdb/pci.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+
+	/* Enable all 5 PCI_CLK_OUTPUTS */
+	clk->occr |= 0xf8000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+
+	/* There is no PEX in MPC8379 parts. */
+	if (PARTID_NO_E(spridr) == SPR_8379)
+		return;
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg);
+}
diff --git a/u-boot/board/freescale/mpc8536ds/Makefile b/u-boot/board/freescale/mpc8536ds/Makefile
new file mode 100644
index 0000000..2ee7b43
--- /dev/null
+++ b/u-boot/board/freescale/mpc8536ds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2008 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8536ds/config.mk b/u-boot/board/freescale/mpc8536ds/config.mk
new file mode 100644
index 0000000..228d8c0
--- /dev/null
+++ b/u-boot/board/freescale/mpc8536ds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2008, 2011 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8536ds board
+#
+ifndef NAND_SPL
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
diff --git a/u-boot/board/freescale/mpc8536ds/ddr.c b/u-boot/board/freescale/mpc8536ds/ddr.c
new file mode 100644
index 0000000..2bad787
--- /dev/null
+++ b/u-boot/board/freescale/mpc8536ds/ddr.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * For wake up arp feature, we need enable auto self refresh
+	 */
+	popts->auto_self_refresh_en = 1;
+	popts->sr_it = 0x6;
+}
diff --git a/u-boot/board/freescale/mpc8536ds/law.c b/u-boot/board/freescale/mpc8536ds/law.c
new file mode 100644
index 0000000..61b7454
--- /dev/null
+++ b/u-boot/board/freescale/mpc8536ds/law.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8536ds/mpc8536ds.c b/u-boot/board/freescale/mpc8536ds/mpc8536ds.c
new file mode 100644
index 0000000..f83f629
--- /dev/null
+++ b/u-boot/board/freescale/mpc8536ds/mpc8536ds.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <spd_sdram.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <netdev.h>
+#include <sata.h>
+
+#include "../common/sgmii_riser.h"
+
+int board_early_init_f (void)
+{
+#ifdef CONFIG_MMC
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SD_DATA |
+			 MPC85xx_PMUXCR_SDHC_CD |
+			 MPC85xx_PMUXCR_SDHC_WP));
+
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	puts("Board: MPC8536DS ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+
+	printf ("Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
+		case PIXIS_VBOOT_LBMAP_NOR0:
+			puts ("vBank: 0\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR1:
+			puts ("vBank: 1\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR2:
+			puts ("vBank: 2\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR3:
+			puts ("vBank: 3\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_PJET:
+			puts ("Promjet\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NAND:
+			puts ("NAND\n");
+			break;
+	}
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	uint d_init;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+
+#if defined (CONFIG_DDR_ECC)
+	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+#endif
+	asm("sync;isync");
+
+	udelay(500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+		udelay(1000);
+	}
+	debug("DDR: memory initialized\n\n");
+	asm("sync; isync");
+	udelay(500);
+#endif
+
+	return 512 * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+	int first_free_busno;
+
+	first_free_busno = fsl_pcie_init_board(0);
+
+#ifdef CONFIG_PCI1
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+
+	pci_speed = 66666000;
+	pci_32 = 1;
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter",
+			pci_info.regs);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+	struct tsec_info_struct tsec_info[2];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode.\n");
+		tsec_info[num].phyaddr = 0;
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.\n");
+		tsec_info[num].phyaddr = 1;
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	if (is_serdes_configured(SGMII_TSEC1) ||
+	    is_serdes_configured(SGMII_TSEC3)) {
+		fsl_sgmii_riser_init(tsec_info, num);
+	}
+#endif
+
+	tsec_eth_init(bis, tsec_info, num);
+#endif
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8536ds/tlb.c b/u-boot/board/freescale/mpc8536ds/tlb.c
new file mode 100644
index 0000000..dc52d7f
--- /dev/null
+++ b/u-boot/board/freescale/mpc8536ds/tlb.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8540ads/Makefile b/u-boot/board/freescale/mpc8540ads/Makefile
new file mode 100644
index 0000000..b94237e
--- /dev/null
+++ b/u-boot/board/freescale/mpc8540ads/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8540ads/ddr.c b/u-boot/board/freescale/mpc8540ads/ddr.c
new file mode 100644
index 0000000..93d1100
--- /dev/null
+++ b/u-boot/board/freescale/mpc8540ads/ddr.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8540ads/law.c b/u-boot/board/freescale/mpc8540ads/law.c
new file mode 100644
index 0000000..4640c1d
--- /dev/null
+++ b/u-boot/board/freescale/mpc8540ads/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	/* This is not so much the SDRAM map as it is the whole localbus map. */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8540ads/mpc8540ads.c b/u-boot/board/freescale/mpc8540ads/mpc8540ads.c
new file mode 100644
index 0000000..c75585e
--- /dev/null
+++ b/u-boot/board/freescale/mpc8540ads/mpc8540ads.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+int checkboard (void)
+{
+	puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+	printf("PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("PCI1: disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller.
+	 */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+phys_size_t fixed_sdram(void)
+{
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+
+static struct pci_controller hose;
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	ft_cpu_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8540ads/tlb.c b/u-boot/board/freescale/mpc8540ads/tlb.c
new file mode 100644
index 0000000..adcc0ad
--- /dev/null
+++ b/u-boot/board/freescale/mpc8540ads/tlb.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8541cds/Makefile b/u-boot/board/freescale/mpc8541cds/Makefile
new file mode 100644
index 0000000..b50d7fd
--- /dev/null
+++ b/u-boot/board/freescale/mpc8541cds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8541cds/ddr.c b/u-boot/board/freescale/mpc8541cds/ddr.c
new file mode 100644
index 0000000..c84a6cb
--- /dev/null
+++ b/u-boot/board/freescale/mpc8541cds/ddr.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8541cds/law.c b/u-boot/board/freescale/mpc8541cds/law.c
new file mode 100644
index 0000000..8e3de22
--- /dev/null
+++ b/u-boot/board/freescale/mpc8541cds/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8541cds/mpc8541cds.c b/u-boot/board/freescale/mpc8541cds/mpc8541cds.c
new file mode 100644
index 0000000..0d3752d
--- /dev/null
+++ b/u-boot/board/freescale/mpc8541cds/mpc8541cds.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf("PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf("PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf("PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+		mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
+	{},
+};
+
+static struct pci_controller hose[] = {
+	{ config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8541cds/tlb.c b/u-boot/board/freescale/mpc8541cds/tlb.c
new file mode 100644
index 0000000..ae6812f
--- /dev/null
+++ b/u-boot/board/freescale/mpc8541cds/tlb.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8544ds/Makefile b/u-boot/board/freescale/mpc8544ds/Makefile
new file mode 100644
index 0000000..8684f5c
--- /dev/null
+++ b/u-boot/board/freescale/mpc8544ds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8544ds/ddr.c b/u-boot/board/freescale/mpc8544ds/ddr.c
new file mode 100644
index 0000000..b8330eb
--- /dev/null
+++ b/u-boot/board/freescale/mpc8544ds/ddr.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8544ds/law.c b/u-boot/board/freescale/mpc8544ds/law.c
new file mode 100644
index 0000000..59e03fc
--- /dev/null
+++ b/u-boot/board/freescale/mpc8544ds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8544ds/mpc8544ds.c b/u-boot/board/freescale/mpc8544ds/mpc8544ds.c
new file mode 100644
index 0000000..a48c815
--- /dev/null
+++ b/u-boot/board/freescale/mpc8544ds/mpc8544ds.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <netdev.h>
+
+#include "../common/sgmii_riser.h"
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	if ((uint)&gur->porpllsr != 0xe00e0000) {
+		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
+	}
+	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	if (vboot & PIXIS_VBOOT_FMAP)
+		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+	else
+		puts ("Promjet\n");
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr, io_sel;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+	int first_free_busno = 0;
+
+	int pcie_ep, pcie_configured;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+	puts("\n");
+
+#ifdef CONFIG_PCIE3
+	pcie_configured = is_serdes_configured(PCIE3);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+		/* contains both PCIE3 MEM & IO space */
+		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
+				LAW_TRGT_IF_PCIE_3);
+		SET_STD_PCIE_INFO(pci_info, 3);
+		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
+
+		/* outbound memory */
+		pci_set_region(&pcie3_hose.regions[0],
+			       CONFIG_SYS_PCIE3_MEM_BUS2,
+			       CONFIG_SYS_PCIE3_MEM_PHYS2,
+			       CONFIG_SYS_PCIE3_MEM_SIZE2,
+			       PCI_REGION_MEM);
+
+		pcie3_hose.region_count = 1;
+
+		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+			pcie_ep ? "Endpoint" : "Root Complex",
+			pci_info.regs);
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pcie3_hose, first_free_busno);
+
+		/*
+		 * Activate ULI1575 legacy chip by performing a fake
+		 * memory access.  Needed to make ULI RTC work.
+		 */
+		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
+	} else {
+		printf("PCIE3: disabled\n");
+	}
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+	SET_STD_PCIE_INFO(pci_info, 1);
+	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
+#else
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+	SET_STD_PCIE_INFO(pci_info, 2);
+	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
+#else
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCI1
+	pci_speed = 66666000;
+	pci_32 = 1;
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter",
+			pci_info.regs);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+}
+
+int last_stage_init(void)
+{
+	return 0;
+}
+
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+	u8 i, go_bit, rd_clks;
+	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	go_bit = in_8(pixis_base + PIXIS_VCTL);
+	go_bit &= 0x01;
+
+	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
+	rd_clks &= 0x1C;
+
+	/*
+	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
+	 * should we be using the AUX register. Remember, we also set the
+	 * GO bit to boot from the alternate bank on the on-board flash
+	 */
+
+	if (go_bit) {
+		if (rd_clks == 0x1c)
+			i = in_8(pixis_base + PIXIS_AUX);
+		else
+			i = in_8(pixis_base + PIXIS_SPD);
+	} else {
+		i = in_8(pixis_base + PIXIS_SPD);
+	}
+
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33333333;
+		break;
+	case 1:
+		val = 40000000;
+		break;
+	case 2:
+		val = 50000000;
+		break;
+	case 3:
+		val = 66666666;
+		break;
+	case 4:
+		val = 83000000;
+		break;
+	case 5:
+		val = 100000000;
+		break;
+	case 6:
+		val = 133333333;
+		break;
+	case 7:
+		val = 166666666;
+		break;
+	}
+
+	return val;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+	struct tsec_info_struct tsec_info[2];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+	if (is_serdes_configured(SGMII_TSEC1) ||
+	    is_serdes_configured(SGMII_TSEC3)) {
+		fsl_sgmii_riser_init(tsec_info, num);
+	}
+
+
+	tsec_eth_init(bis, tsec_info, num);
+#endif
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8544ds/tlb.c b/u-boot/board/freescale/mpc8544ds/tlb.c
new file mode 100644
index 0000000..d99441b
--- /dev/null
+++ b/u-boot/board/freescale/mpc8544ds/tlb.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	1G	PCIE  8,9,a,b
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe100_0000	255M	PCI IO range
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8548cds/Makefile b/u-boot/board/freescale/mpc8548cds/Makefile
new file mode 100644
index 0000000..b50d7fd
--- /dev/null
+++ b/u-boot/board/freescale/mpc8548cds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8548cds/ddr.c b/u-boot/board/freescale/mpc8548cds/ddr.c
new file mode 100644
index 0000000..ab64fa8
--- /dev/null
+++ b/u-boot/board/freescale/mpc8548cds/ddr.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8548cds/law.c b/u-boot/board/freescale/mpc8548cds/law.c
new file mode 100644
index 0000000..5b6943d
--- /dev/null
+++ b/u-boot/board/freescale/mpc8548cds/law.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
+ * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
+ * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
+ * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+#endif
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8548cds/mpc8548cds.c b/u-boot/board/freescale/mpc8548cds/mpc8548cds.c
new file mode 100644
index 0000000..f5c799b
--- /dev/null
+++ b/u-boot/board/freescale/mpc8548cds/mpc8548cds.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void local_bus_init(void);
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
+
+	ecm->eedr = 0xffffffff;		/* clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* enable ecm errors */
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8548 uses "new" 15-16 style addressing.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+		mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
+	{},
+};
+
+static struct pci_controller pci1_hose = {
+	config_table: pci_mpc85xxcds_config_table};
+#endif	/* CONFIG_PCI */
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif	/* CONFIG_PCI2 */
+
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr, io_sel;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+	int first_free_busno = 0;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+#ifdef CONFIG_PCI1
+	pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter",
+			pci_info.regs);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+
+#ifdef CONFIG_PCIX_CHECK
+		if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+			/* PCI-X init */
+			if (CONFIG_SYS_CLK_FREQ < 66000000)
+				printf("PCI-X will only work at 66 MHz\n");
+
+			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+		}
+#endif
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+	uint pci2_clk_sel = porpllsr & 0x4000;	/* PORPLLSR[17] */
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	if (pci_dual) {
+		printf("PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf("PCI2: disabled\n");
+	}
+}
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
+#endif /* CONFIG_PCI2 */
+
+	fsl_pcie_init_board(first_free_busno);
+}
+
+int last_stage_init(void)
+{
+	unsigned short temp;
+
+	/* Change the resistors for the PHY */
+	/* This is needed to get the RGMII working for the 1.3+
+	 * CDS cards */
+	if (get_board_version() ==  0x13) {
+		miiphy_write(CONFIG_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 29, 18);
+
+		miiphy_read(CONFIG_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 30, &temp);
+
+		temp = (temp & 0xf03f);
+		temp |= 2 << 9;		/* 36 ohm */
+		temp |= 2 << 6;		/* 39 ohm */
+
+		miiphy_write(CONFIG_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 30, temp);
+
+		miiphy_write(CONFIG_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 29, 3);
+
+		miiphy_write(CONFIG_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 30, 0x8000);
+	}
+
+	return 0;
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8548cds/tlb.c b/u-boot/board/freescale/mpc8548cds/tlb.c
new file mode 100644
index 0000000..b2c1b31
--- /dev/null
+++ b/u-boot/board/freescale/mpc8548cds/tlb.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	1M	PCI1 IO
+	 * 0xe210_0000	1M	PCI2 IO
+	 * 0xe300_0000	1M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	64M	Non-cacheable, guarded
+	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_64M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8555cds/Makefile b/u-boot/board/freescale/mpc8555cds/Makefile
new file mode 100644
index 0000000..b50d7fd
--- /dev/null
+++ b/u-boot/board/freescale/mpc8555cds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8555cds/ddr.c b/u-boot/board/freescale/mpc8555cds/ddr.c
new file mode 100644
index 0000000..c84a6cb
--- /dev/null
+++ b/u-boot/board/freescale/mpc8555cds/ddr.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8555cds/law.c b/u-boot/board/freescale/mpc8555cds/law.c
new file mode 100644
index 0000000..8e3de22
--- /dev/null
+++ b/u-boot/board/freescale/mpc8555cds/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8555cds/mpc8555cds.c b/u-boot/board/freescale/mpc8555cds/mpc8555cds.c
new file mode 100644
index 0000000..60d1758
--- /dev/null
+++ b/u-boot/board/freescale/mpc8555cds/mpc8555cds.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf("PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf("PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf("PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+		mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
+	{},
+};
+
+
+static struct pci_controller hose[] = {
+	{
+	config_table: pci_mpc85xxcds_config_table,
+	},
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
+#endif
+};
+
+#endif
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8555cds/tlb.c b/u-boot/board/freescale/mpc8555cds/tlb.c
new file mode 100644
index 0000000..ae6812f
--- /dev/null
+++ b/u-boot/board/freescale/mpc8555cds/tlb.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8560ads/Makefile b/u-boot/board/freescale/mpc8560ads/Makefile
new file mode 100644
index 0000000..9fce3be
--- /dev/null
+++ b/u-boot/board/freescale/mpc8560ads/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8560ads/ddr.c b/u-boot/board/freescale/mpc8560ads/ddr.c
new file mode 100644
index 0000000..93d1100
--- /dev/null
+++ b/u-boot/board/freescale/mpc8560ads/ddr.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8560ads/law.c b/u-boot/board/freescale/mpc8560ads/law.c
new file mode 100644
index 0000000..4640c1d
--- /dev/null
+++ b/u-boot/board/freescale/mpc8560ads/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	/* This is not so much the SDRAM map as it is the whole localbus map. */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8560ads/mpc8560ads.c b/u-boot/board/freescale/mpc8560ads/mpc8560ads.c
new file mode 100644
index 0000000..1a165bf
--- /dev/null
+++ b/u-boot/board/freescale/mpc8560ads/mpc8560ads.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_lbc.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+
+void local_bus_init(void);
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+
+/*
+ * MPC8560ADS Board Status & Control Registers
+ */
+typedef struct bcsr_ {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+} bcsr_t;
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+}
+
+
+int checkboard (void)
+{
+	puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+	printf("PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("PCI1: disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller.
+	 */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+phys_size_t fixed_sdram(void)
+{
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	ft_cpu_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8560ads/tlb.c b/u-boot/board/freescale/mpc8560ads/tlb.c
new file mode 100644
index 0000000..adcc0ad
--- /dev/null
+++ b/u-boot/board/freescale/mpc8560ads/tlb.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8568mds/Makefile b/u-boot/board/freescale/mpc8568mds/Makefile
new file mode 100644
index 0000000..eda359f
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2004-2007 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= bcsr.o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8568mds/bcsr.c b/u-boot/board/freescale/mpc8568mds/bcsr.c
new file mode 100644
index 0000000..30676e1
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/bcsr.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8568mds_duart()
+{
+	volatile uint* duart_mux	= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
+	volatile uint* devices		= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
+	volatile u8 *bcsr		= (u8 *)(CONFIG_SYS_BCSR);
+
+	*duart_mux = 0x80000000;	/* Set the mux to Duart on PMUXCR */
+	*devices  = 0;			/* Enable all peripheral devices */
+	bcsr[5] |= 0x01;		/* Enable Duart in BCSR*/
+}
+
+void enable_8568mds_flash_write()
+{
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	bcsr[9] |= 0x01;
+}
+
+void disable_8568mds_flash_write()
+{
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	bcsr[9] &= ~(0x01);
+}
+
+void enable_8568mds_qe_mdio()
+{
+	u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	bcsr[7] |= 0x01;
+}
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void)
+{
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	/* Turn off UCC1 & UCC2 */
+	out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
+	out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
+
+	/* Mode is RGMII, all bits clear */
+	out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
+					     BCSR_UCC2_MODE_MSK));
+
+	/* Turn UCC1 & UCC2 on */
+	out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
+	out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8568mds/bcsr.h b/u-boot/board/freescale/mpc8568mds/bcsr.h
new file mode 100644
index 0000000..046025b
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/bcsr.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions
+	* BCSR 0 *
+	0:3	ccb sys pll
+	4:6	cfg core pll
+	7	cfg boot seq
+
+	* BCSR 1 *
+	0:2	cfg rom lock
+	3:5	cfg host agent
+	6	PCI IO
+	7	cfg RIO size
+
+	* BCSR 2 *
+	0:4	QE PLL
+	5	QE clock
+	6	cfg PCI arbiter
+
+	* BCSR 3 *
+	0	TSEC1 reduce
+	1	TSEC2 reduce
+	2:3	TSEC1 protocol
+	4:5	TSEC2 protocol
+	6	PHY1 slave
+	7	PHY2 slave
+
+	* BCSR 4 *
+	4	clock enable
+	5	boot EPROM
+	6	GETH transactive reset
+	7	BRD write potect
+
+	* BCSR 5 *
+	1:3	Leds 1-3
+	4	UPC1 enable
+	5	UPC2 enable
+	6	UPC2 pos
+	7	RS232 enable
+
+	* BCSR 6 *
+	0	CFG ver 0
+	1	CFG ver 1
+	6	Register config led
+	7	Power on reset
+
+	* BCSR 7 *
+	2	board host mode indication
+	5	enable TSEC1 PHY
+	6	enable TSEC2 PHY
+
+	* BCSR 8 *
+	0	UCC GETH1 enable
+	1	UCC GMII enable
+	3	UCC TBI enable
+	5	UCC MII enable
+	7	Real time clock reset
+
+	* BCSR 9 *
+	0	UCC2 GETH enable
+	1	UCC2 GMII enable
+	3	UCC2 TBI enable
+	5	UCC2 MII enable
+	6	Ready only - indicate flash ready after burning
+	7	Flash write protect
+*/
+
+#define BCSR_UCC1_GETH_EN	(0x1 << 7)
+#define BCSR_UCC2_GETH_EN	(0x1 << 7)
+#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
+#define BCSR_UCC2_MODE_MSK	(0x3 << 0)
+
+/*BCSR Utils functions*/
+
+void enable_8568mds_duart(void);
+void enable_8568mds_flash_write(void);
+void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void);
+#endif
+
+#endif	/* __BCSR_H_ */
diff --git a/u-boot/board/freescale/mpc8568mds/ddr.c b/u-boot/board/freescale/mpc8568mds/ddr.c
new file mode 100644
index 0000000..482fd91
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/ddr.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8568mds/law.c b/u-boot/board/freescale/mpc8568mds/law.c
new file mode 100644
index 0000000..c5cf7ba
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/law.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
+ *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
+ *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
+ *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8568mds/mpc8568mds.c b/u-boot/board/freescale/mpc8568mds/mpc8568mds.c
new file mode 100644
index 0000000..5cda81c
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/mpc8568mds.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GETH1 */
+	{4, 10, 1, 0, 2}, /* TxD0 */
+	{4,  9, 1, 0, 2}, /* TxD1 */
+	{4,  8, 1, 0, 2}, /* TxD2 */
+	{4,  7, 1, 0, 2}, /* TxD3 */
+	{4, 23, 1, 0, 2}, /* TxD4 */
+	{4, 22, 1, 0, 2}, /* TxD5 */
+	{4, 21, 1, 0, 2}, /* TxD6 */
+	{4, 20, 1, 0, 2}, /* TxD7 */
+	{4, 15, 2, 0, 2}, /* RxD0 */
+	{4, 14, 2, 0, 2}, /* RxD1 */
+	{4, 13, 2, 0, 2}, /* RxD2 */
+	{4, 12, 2, 0, 2}, /* RxD3 */
+	{4, 29, 2, 0, 2}, /* RxD4 */
+	{4, 28, 2, 0, 2}, /* RxD5 */
+	{4, 27, 2, 0, 2}, /* RxD6 */
+	{4, 26, 2, 0, 2}, /* RxD7 */
+	{4, 11, 1, 0, 2}, /* TX_EN */
+	{4, 24, 1, 0, 2}, /* TX_ER */
+	{4, 16, 2, 0, 2}, /* RX_DV */
+	{4, 30, 2, 0, 2}, /* RX_ER */
+	{4, 17, 2, 0, 2}, /* RX_CLK */
+	{4, 19, 1, 0, 2}, /* GTX_CLK */
+	{1, 31, 2, 0, 3}, /* GTX125 */
+
+	/* GETH2 */
+	{5, 10, 1, 0, 2}, /* TxD0 */
+	{5,  9, 1, 0, 2}, /* TxD1 */
+	{5,  8, 1, 0, 2}, /* TxD2 */
+	{5,  7, 1, 0, 2}, /* TxD3 */
+	{5, 23, 1, 0, 2}, /* TxD4 */
+	{5, 22, 1, 0, 2}, /* TxD5 */
+	{5, 21, 1, 0, 2}, /* TxD6 */
+	{5, 20, 1, 0, 2}, /* TxD7 */
+	{5, 15, 2, 0, 2}, /* RxD0 */
+	{5, 14, 2, 0, 2}, /* RxD1 */
+	{5, 13, 2, 0, 2}, /* RxD2 */
+	{5, 12, 2, 0, 2}, /* RxD3 */
+	{5, 29, 2, 0, 2}, /* RxD4 */
+	{5, 28, 2, 0, 2}, /* RxD5 */
+	{5, 27, 2, 0, 3}, /* RxD6 */
+	{5, 26, 2, 0, 2}, /* RxD7 */
+	{5, 11, 1, 0, 2}, /* TX_EN */
+	{5, 24, 1, 0, 2}, /* TX_ER */
+	{5, 16, 2, 0, 2}, /* RX_DV */
+	{5, 30, 2, 0, 2}, /* RX_ER */
+	{5, 17, 2, 0, 2}, /* RX_CLK */
+	{5, 19, 1, 0, 2}, /* GTX_CLK */
+	{1, 31, 2, 0, 3}, /* GTX125 */
+	{4,  6, 3, 0, 2}, /* MDIO */
+	{4,  5, 1, 0, 2}, /* MDC */
+
+	/* UART1 */
+	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
+	{2, 1, 1, 0, 2}, /* UART_RTS1 */
+	{2, 2, 2, 0, 2}, /* UART_CTS1 */
+	{2, 3, 2, 0, 2}, /* UART_SIN1 */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	enable_8568mds_duart();
+	enable_8568mds_flash_write();
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+	reset_8568mds_uccs();
+#endif
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+	enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CONFIG_SYS_I2C2_OFFSET
+	/* Enable I2C2_SCL and I2C2_SDA */
+	volatile struct par_io *port_c;
+	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
+	port_c->cpdir2 |= 0x0f000000;
+	port_c->cppar2 &= ~0x0f000000;
+	port_c->cppar2 |= 0x0a000000;
+#endif
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: 8568 MDS\n");
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	asm("msync");
+
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8568 uses "new" 15-16 style addressing.
+	 */
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI)
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8568mds_config_table[] = {
+	{
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+};
+#endif
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc8568mds_config_table,
+#endif
+};
+#endif	/* CONFIG_PCI */
+
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+	u8 val8, orig_i2c_bus;
+	/*
+	 * Assign PIB PMC2/3 to PCI bus
+	 */
+
+	/*switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0x00;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0x00;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+	val8 = 0xf9;
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0x00;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+
+	asm("eieio");
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr, io_sel;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+	pci_speed = 66666000;
+	pci_32 = 1;
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter",
+			pci_info.regs);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8568mds/tlb.c b/u-boot/board/freescale/mpc8568mds/tlb.c
new file mode 100644
index 0000000..8470c87
--- /dev/null
+++ b/u-boot/board/freescale/mpc8568mds/tlb.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 Initializations */
+	/*
+	 * TLBe 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH (upper half)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 1:	16M	Non-cacheable, guarded
+	 * 0xfe000000	16M	FLASH (lower half)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 2:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000	512M	PCIe MEM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLBe 3:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	8M	PCI1 IO
+	 * 0xe280_0000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 4:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 5:	256K	Non-cacheable, guarded
+	 * 0xf8000000	32K BCSR
+	 * 0xf8008000	32K PIB (CS4)
+	 * 0xf8010000	32K PIB (CS5)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8569mds/Makefile b/u-boot/board/freescale/mpc8569mds/Makefile
new file mode 100644
index 0000000..1d49757
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2004-2009 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= bcsr.o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8569mds/bcsr.c b/u-boot/board/freescale/mpc8569mds/bcsr.c
new file mode 100644
index 0000000..b688e5c
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/bcsr.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8569mds_flash_write()
+{
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void disable_8569mds_flash_write()
+{
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void enable_8569mds_qe_uec()
+{
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+	/* Set UCC1-4 working at RMII mode */
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
+}
+
+void disable_8569mds_brd_eeprom_write_protect()
+{
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
+}
diff --git a/u-boot/board/freescale/mpc8569mds/bcsr.h b/u-boot/board/freescale/mpc8569mds/bcsr.h
new file mode 100644
index 0000000..091b69c
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/bcsr.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions*/
+/****************************************/
+/* BCSR defines                         */
+/****************************************/
+#define BCSR6_UPC1_EN		0x80
+#define BCSR6_UPC1_POS_EN	0x40
+#define BCSR6_UPC1_ADDR_EN	0x20
+#define BCSR6_UPC1_DEV2		0x10
+#define BCSR6_SD_CARD_1BIT	0x08
+#define BCSR6_SD_CARD_4BITS	0x04
+#define BCSR6_TDM2G_EN		0x02
+#define BCSR6_UCC7_RMII_EN	0x01
+
+#define BCSR7_UCC1_GETH_EN	0x80
+#define BCSR7_UCC1_RGMII_EN	0x40
+#define BCSR7_UCC1_RTBI_EN	0x20
+#define BCSR7_GETHRST_MRVL	0x04
+#define BCSR7_BRD_WRT_PROTECT	0x02
+
+#define BCSR8_UCC2_GETH_EN	0x80
+#define BCSR8_UCC2_RGMII_EN	0x40
+#define BCSR8_UCC2_RTBI_EN	0x20
+#define BCSR8_UEM_MARVEL_RESET	0x02
+
+#define BCSR9_UCC3_GETH_EN	0x80
+#define BCSR9_UCC3_RGMII_EN	0x40
+#define BCSR9_UCC3_RTBI_EN	0x20
+#define BCSR9_UCC3_RMII_EN	0x10
+#define BCSR9_UCC3_UEM_MICREL	0x01
+
+#define BCSR10_UCC4_GETH_EN	0x80
+#define BCSR10_UCC4_RGMII_EN	0x40
+#define BCSR10_UCC4_RTBI_EN	0x20
+
+#define BCSR11_LED0		0x40
+#define BCSR11_LED1		0x20
+#define BCSR11_LED2		0x10
+
+#define BCSR12_UCC6_RMII_EN	0x20
+#define BCSR12_UCC8_RMII_EN	0x20
+
+#define BCSR15_SMII6_DIS	0x08
+#define BCSR15_SMII8_DIS	0x04
+#define BCSR15_QEUART_EN	0x01
+
+#define BCSR16_UPC1_DEV2	0x02
+
+#define BCSR17_nUSBEN		0x80
+#define BCSR17_nUSBLOWSPD	0x40
+#define BCSR17_USBVCC		0x20
+#define BCSR17_USBMODE		0x10
+#define BCSR17_FLASH_nWP	0x01
+
+/*BCSR Utils functions*/
+
+void enable_8569mds_flash_write(void);
+void disable_8569mds_flash_write(void);
+void enable_8569mds_qe_uec(void);
+void disable_8569mds_brd_eeprom_write_protect(void);
+
+#endif	/* __BCSR_H_ */
diff --git a/u-boot/board/freescale/mpc8569mds/config.mk b/u-boot/board/freescale/mpc8569mds/config.mk
new file mode 100644
index 0000000..54b2eb1
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8569mds board
+#
+ifndef NAND_SPL
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
diff --git a/u-boot/board/freescale/mpc8569mds/ddr.c b/u-boot/board/freescale/mpc8569mds/ddr.c
new file mode 100644
index 0000000..e3f5b4a
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/ddr.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		if (ctrl_num == 0 && i == 1)
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 4;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0xff;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 2;
+
+	/*
+	 * Enable half drive strength
+	 */
+	popts->half_strength_driver_enable = 1;
+
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xa;
+	popts->wrlvl_start = 0x4;
+
+	/* Rtt and Rtt_W override */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = DDR3_RTT_60_OHM;
+	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+}
diff --git a/u-boot/board/freescale/mpc8569mds/law.c b/u-boot/board/freescale/mpc8569mds/law.c
new file mode 100644
index 0000000..4f4a93b
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/law.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *2)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *3)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
+ *4.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *4.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *4.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *4.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *4.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8569mds/mpc8569mds.c b/u-boot/board/freescale/mpc8569mds/mpc8569mds.c
new file mode 100644
index 0000000..ecda222
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/mpc8569mds.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+
+#include "bcsr.h"
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* QE_MUX_MDC */
+	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
+
+	/* QE_MUX_MDIO */
+	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
+
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+	/* UCC_1_RGMII */
+	{2, 11, 2, 0, 1}, /* CLK12 */
+	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
+	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
+	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
+	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
+	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
+	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
+	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
+	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
+	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
+	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
+	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
+	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
+
+	/* UCC_2_RGMII */
+	{2, 16, 2, 0, 3}, /* CLK17 */
+	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
+	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
+	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
+	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
+	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
+	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
+	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
+	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
+	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
+	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
+	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
+	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
+
+	/* UCC_3_RGMII */
+	{2, 11, 2, 0, 1}, /* CLK12 */
+	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
+	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
+	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
+	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
+	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
+	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
+	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
+	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
+	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
+	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
+	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
+	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
+
+	/* UCC_4_RGMII */
+	{2, 16, 2, 0, 3}, /* CLK17 */
+	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
+	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
+	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
+	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
+	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
+	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
+	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
+	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
+	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
+	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
+	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
+	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
+
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+	/* UCC_1_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
+	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
+	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
+	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
+	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
+	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
+
+	/* UCC_2_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
+	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
+	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
+	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
+	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
+	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
+
+	/* UCC_3_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
+	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
+	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
+	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
+	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
+	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
+
+	/* UCC_4_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
+	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
+	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
+	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
+	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
+	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
+#endif
+
+	/* UART1 is muxed with QE PortF bit [9-12].*/
+	{5, 12, 2, 0, 3}, /* UART1_SIN */
+	{5, 9,  1, 0, 3}, /* UART1_SOUT */
+	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
+	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
+
+	/* QE UART                                     */
+	{0, 19, 1, 0, 2}, /* QEUART_TX                 */
+	{1, 17, 2, 0, 3}, /* QEUART_RX                 */
+	{0, 25, 1, 0, 1}, /* QEUART_RTS                */
+	{1, 23, 2, 0, 1}, /* QEUART_CTS                */
+
+	/* QE USB                                      */
+	{5,  3, 1, 0, 1}, /* USB_OE                    */
+	{5,  4, 1, 0, 2}, /* USB_TP                    */
+	{5,  5, 1, 0, 2}, /* USB_TN                    */
+	{5,  6, 2, 0, 2}, /* USB_RP                    */
+	{5,  7, 2, 0, 1}, /* USB_RX                    */
+	{5,  8, 2, 0, 1}, /* USB_RN                    */
+	{2,  4, 2, 0, 2}, /* CLK5                      */
+
+	/* SPI Flash, M25P40                           */
+	{4, 27, 3, 0, 1}, /* SPI_MOSI                  */
+	{4, 28, 3, 0, 1}, /* SPI_MISO                  */
+	{4, 29, 3, 0, 1}, /* SPI_CLK                   */
+	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	enable_8569mds_flash_write();
+
+#ifdef CONFIG_QE
+	enable_8569mds_qe_uec();
+#endif
+
+#if CONFIG_SYS_I2C2_OFFSET
+	/* Enable I2C2 signals instead of SD signals */
+	volatile struct ccsr_gur *gur;
+	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
+	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
+	gur->plppar1 |= PLPPAR1_I2C2_VAL;
+	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
+	gur->plpdir1 |= PLPDIR1_I2C2_VAL;
+
+	disable_8569mds_brd_eeprom_write_protect();
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+	const u8 flash_esel = 0;
+
+	/*
+	 * Remap Boot flash to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,	/* tlb, epn, rpn */
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
+		0, flash_esel,				/* ts, esel */
+		BOOKE_PAGESZ_64M, 1);			/* tsize, iprot */
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: 8569 MDS\n");
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	uint d_init;
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
+	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
+	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+#if defined (CONFIG_DDR_ECC)
+	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
+	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
+	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
+#endif
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+		udelay(1000);
+	}
+	debug("DDR: memory initialized\n\n");
+	udelay(500);
+#endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
+	if (clkdiv == 16)
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+	else if (clkdiv == 8)
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+	else if (clkdiv == 4)
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+
+	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
+}
+
+static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
+{
+	const char *status = "disabled";
+	int off;
+	int err;
+
+	off = fdt_path_offset(blob, alias);
+	if (off < 0) {
+		printf("WARNING: could not find %s alias: %s.\n", alias,
+			fdt_strerror(off));
+		return;
+	}
+
+	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+	if (err) {
+		printf("WARNING: could not set status for serial0: %s.\n",
+			fdt_strerror(err));
+		return;
+	}
+}
+
+/*
+ * Because of an erratum in prototype boards it is impossible to use eSDHC
+ * without disabling UART0 (which makes it quite easy to 'brick' the board
+ * by simply issung 'setenv hwconfig esdhc', and not able to interact with
+ * U-Boot anylonger).
+ *
+ * So, but default we assume that the board is a prototype, which is a most
+ * safe assumption. There is no way to determine board revision from a
+ * register, so we use hwconfig.
+ */
+
+static int prototype_board(void)
+{
+	if (hwconfig_subarg("board", "rev", NULL))
+		return hwconfig_subarg_cmp("board", "rev", "prototype");
+	return 1;
+}
+
+static int esdhc_disables_uart0(void)
+{
+	return prototype_board() ||
+	       hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
+}
+
+static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
+{
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+	const char *devtype = "serial";
+	const char *compat = "ucc_uart";
+	const char *clk = "brg9";
+	u32 portnum = 0;
+	int off = -1;
+
+	if (!hwconfig("qe_uart"))
+		return;
+
+	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
+		printf("QE UART: won't enable with esdhc.\n");
+		return;
+	}
+
+	fdt_board_disable_serial(blob, bd, "serial1");
+
+	while (1) {
+		const u32 *idx;
+		int len;
+
+		off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
+		if (off < 0) {
+			printf("WARNING: unable to fixup device tree for "
+				"QE UART\n");
+			return;
+		}
+
+		idx = fdt_getprop(blob, off, "cell-index", &len);
+		if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
+			continue;
+		break;
+	}
+
+	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
+	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
+	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
+	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
+	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
+
+	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+int board_mmc_init(bd_t *bd)
+{
+	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+	u8 bcsr6 = BCSR6_SD_CARD_1BIT;
+
+	if (!hwconfig("esdhc"))
+		return 0;
+
+	printf("Enabling eSDHC...\n"
+	       "  For eSDHC to function, I2C2 ");
+	if (esdhc_disables_uart0()) {
+		printf("and UART0 should be disabled.\n");
+		printf("  Redirecting stderr, stdout and stdin to UART1...\n");
+		console_assign(stderr, "eserial1");
+		console_assign(stdout, "eserial1");
+		console_assign(stdin, "eserial1");
+		printf("Switched to UART1 (initial log has been printed to "
+		       "UART0).\n");
+
+		clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
+					       PLPPAR1_ESDHC_4BITS_VAL);
+		clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
+					       PLPDIR1_ESDHC_4BITS_VAL);
+		bcsr6 |= BCSR6_SD_CARD_4BITS;
+	} else {
+		printf("should be disabled.\n");
+	}
+
+	/* Assign I2C2 signals to eSDHC. */
+	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
+				       PLPPAR1_ESDHC_VAL);
+	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
+				       PLPDIR1_ESDHC_VAL);
+
+	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
+	setbits_8(&bcsr[6], bcsr6);
+
+	return fsl_esdhc_mmc_init(bd);
+}
+
+static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
+{
+	const char *status = "disabled";
+	int off = -1;
+
+	if (!hwconfig("esdhc"))
+		return;
+
+	if (esdhc_disables_uart0())
+		fdt_board_disable_serial(blob, bd, "serial0");
+
+	while (1) {
+		const u32 *idx;
+		int len;
+
+		off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
+		if (off < 0)
+			break;
+
+		idx = fdt_getprop(blob, off, "cell-index", &len);
+		if (!idx || len != sizeof(*idx))
+			continue;
+
+		if (*idx == 1) {
+			fdt_setprop(blob, off, "status", status,
+				    strlen(status) + 1);
+			break;
+		}
+	}
+
+	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
+		off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
+		if (off < 0) {
+			printf("WARNING: could not find esdhc node\n");
+			return;
+		}
+		fdt_delprop(blob, off, "sdhci,1-bit-only");
+	}
+}
+#else
+static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif
+
+static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+
+	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
+		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+	else
+		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+
+	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
+		clrbits_8(&bcsr[17], BCSR17_USBVCC);
+		clrbits_8(&bcsr[17], BCSR17_USBMODE);
+		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
+				   "peripheral", sizeof("peripheral"), 1);
+	} else {
+		setbits_8(&bcsr[17], BCSR17_USBVCC);
+		setbits_8(&bcsr[17], BCSR17_USBMODE);
+	}
+
+	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+#if defined(CONFIG_PQ_MDS_PIB)
+	pib_init();
+#endif
+
+	fsl_pcie_init_board(0);
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_SYS_UCC_RMII_MODE)
+	int nodeoff, off, err;
+	unsigned int val;
+	const u32 *ph;
+	const u32 *index;
+
+	/* fixup device tree for supporting rmii mode */
+	nodeoff = -1;
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
+				"ucc_geth")) >= 0) {
+		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
+						"clk16");
+		if (err < 0) {
+			printf("WARNING: could not set tx-clock-name %s.\n",
+				fdt_strerror(err));
+			break;
+		}
+
+		err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
+
+		if (err < 0) {
+			printf("WARNING: could not set phy-connection-type "
+				"%s.\n", fdt_strerror(err));
+			break;
+		}
+
+		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
+		if (index == NULL) {
+			printf("WARNING: could not get cell-index of ucc\n");
+			break;
+		}
+
+		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
+		if (ph == NULL) {
+			printf("WARNING: could not get phy-handle of ucc\n");
+			break;
+		}
+
+		off = fdt_node_offset_by_phandle(blob, *ph);
+		if (off < 0) {
+			printf("WARNING: could not get phy node	%s.\n",
+				fdt_strerror(err));
+			break;
+		}
+
+		val = 0x7 + *index; /* RMII phy address starts from 0x8 */
+
+		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
+		if (err < 0) {
+			printf("WARNING: could not set reg for phy-handle "
+				"%s.\n", fdt_strerror(err));
+			break;
+		}
+	}
+#endif
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+
+	fdt_board_fixup_esdhc(blob, bd);
+	fdt_board_fixup_qe_uart(blob, bd);
+	fdt_board_fixup_qe_usb(blob, bd);
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8569mds/tlb.c b/u-boot/board/freescale/mpc8569mds/tlb.c
new file mode 100644
index 0000000..f852fc3
--- /dev/null
+++ b/u-boot/board/freescale/mpc8569mds/tlb.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 Initializations */
+	/*
+	 * TLBe 0:	64M	write-through, guarded
+	 * Out of reset this entry is only 4K.
+	 * 0xfc000000	32MB	NAND FLASH (CS3)
+	 * 0xfe000000	32MB	NOR FLASH (CS0)
+	 */
+#ifdef CONFIG_NAND_SPL
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+#endif
+	/*
+	 * TLBe 1:	256KB	Non-cacheable, guarded
+	 * 0xf8000000	32K	BCSR
+	 * 0xf8008000	32K	PIB (CS4)
+	 * 0xf8010000	32K	PIB (CS5)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256K, 1),
+
+	/*
+	 * TLBe 2:	256M	Non-cacheable, guarded
+	 * 0xa00000000	256M	PCIe MEM (lower half)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLBe 3:	256M	Non-cacheable, guarded
+	 * 0xb00000000	256M	PCIe MEM (higher half)
+	 */
+	SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
+		      (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLBe 4:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe280_0000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8572ds/Makefile b/u-boot/board/freescale/mpc8572ds/Makefile
new file mode 100644
index 0000000..5b9fa10
--- /dev/null
+++ b/u-boot/board/freescale/mpc8572ds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8572ds/config.mk b/u-boot/board/freescale/mpc8572ds/config.mk
new file mode 100644
index 0000000..9fd30f9
--- /dev/null
+++ b/u-boot/board/freescale/mpc8572ds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8572ds board
+#
+ifndef NAND_SPL
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
diff --git a/u-boot/board/freescale/mpc8572ds/ddr.c b/u-boot/board/freescale/mpc8572ds/ddr.c
new file mode 100644
index 0000000..d66ede2
--- /dev/null
+++ b/u-boot/board/freescale/mpc8572ds/ddr.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+		if (ctrl_num == 1 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+	/* 	memory controller 0 			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,    6,   7,    3,  0},
+		{334, 400,    2,    6,   9,    3,  0},
+		{401, 549,    2,    6,  11,    3,  0},
+		{550, 680,    2,    1,  10,    5,  0},
+		{681, 850,    2,    1,  12,    5,  1},
+		{  0, 333,    1,    6,   7,    3,  0},
+		{334, 400,    1,    6,   9,    3,  0},
+		{401, 549,    1,    6,  11,    3,  0},
+		{550, 680,    1,    1,  10,    5,  0},
+		{681, 850,    1,    1,  12,    5,  0}
+	},
+
+	{
+	/*	memory controller 1			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,     6,  7,    3,  0},
+		{334, 400,    2,     6,  9,    3,  0},
+		{401, 549,    2,     6, 11,    3,  0},
+		{550, 680,    2,     1, 11,    6,  0},
+		{681, 850,    2,     1, 13,    6,  1},
+		{  0, 333,    1,     6,  7,    3,  0},
+		{334, 400,    1,     6,  9,    3,  0},
+		{401, 549,    1,     6, 11,    3,  0},
+		{550, 680,    1,     1, 11,    6,  0},
+		{681, 850,    1,     1, 13,    6,  0}
+	}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+			popts->cs_local_opts[i].odt_rd_cfg = 3;
+			popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high &&
+		    pdimm->n_ranks == pbsp->n_ranks) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->write_data_delay = pbsp->write_data_delay;
+			popts->twoT_en = pbsp->force_2T;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8572ds/law.c b/u-boot/board/freescale/mpc8572ds/law.c
new file mode 100644
index 0000000..7c63f84
--- /dev/null
+++ b/u-boot/board/freescale/mpc8572ds/law.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8572ds/mpc8572ds.c b/u-boot/board/freescale/mpc8572ds/mpc8572ds.c
new file mode 100644
index 0000000..4b2ef4e
--- /dev/null
+++ b/u-boot/board/freescale/mpc8572ds/mpc8572ds.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <netdev.h>
+
+#include "../common/sgmii_riser.h"
+
+int checkboard (void)
+{
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	puts ("Board: MPC8572DS ");
+#ifdef CONFIG_PHYS_64BIT
+	puts ("(36-bit addrmap) ");
+#endif
+	printf ("Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
+		case PIXIS_VBOOT_LBMAP_NOR0:
+			puts ("vBank: 0\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_PJET:
+			puts ("Promjet\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NAND:
+			puts ("NAND\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR1:
+			puts ("vBank: 1\n");
+			break;
+	}
+
+	return 0;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	uint d_init;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+
+#if defined (CONFIG_DDR_ECC)
+	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+#endif
+	asm("sync;isync");
+
+	udelay(500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+		udelay(1000);
+	}
+	debug("DDR: memory initialized\n\n");
+	asm("sync; isync");
+	udelay(500);
+#endif
+
+	return 512 * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	struct pci_controller *hose;
+
+	fsl_pcie_init_board(0);
+
+	hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
+
+	if (hose) {
+		u32 temp32;
+		u8 uli_busno = hose->first_busno + 2;
+
+		/*
+		 * Activate ULI1575 legacy chip by performing a fake
+		 * memory access.  Needed to make ULI RTC work.
+		 * Device 1d has the first on-board memory BAR.
+		 */
+		pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
+				PCI_BASE_ADDRESS_1, &temp32);
+
+		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+			void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
+					temp32, 4, 0);
+			debug(" uli1572 read to %p\n", p);
+			in_be32(p);
+		}
+	}
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
+
+	return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		puts("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC4
+	SET_STD_TSEC_INFO(tsec_info[num], 4);
+	if (is_serdes_configured(SGMII_TSEC4)) {
+		puts("eTSEC4 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/freescale/mpc8572ds/tlb.c b/u-boot/board/freescale/mpc8572ds/tlb.c
new file mode 100644
index 0000000..575bdb5
--- /dev/null
+++ b/u-boot/board/freescale/mpc8572ds/tlb.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_4K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
+			CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 9, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 10, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/mpc8610hpcd/Makefile b/u-boot/board/freescale/mpc8610hpcd/Makefile
new file mode 100644
index 0000000..e91c2c5
--- /dev/null
+++ b/u-boot/board/freescale/mpc8610hpcd/Makefile
@@ -0,0 +1,53 @@
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
+COBJS-y	+= law.o
+
+COBJS-$(CONFIG_FSL_DIU_FB)	+= mpc8610hpcd_diu.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8610hpcd/ddr.c b/u-boot/board/freescale/mpc8610hpcd/ddr.c
new file mode 100644
index 0000000..0117d13
--- /dev/null
+++ b/u-boot/board/freescale/mpc8610hpcd/ddr.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/freescale/mpc8610hpcd/law.c b/u-boot/board/freescale/mpc8610hpcd/law.c
new file mode 100644
index 0000000..26e41b6
--- /dev/null
+++ b/u-boot/board/freescale/mpc8610hpcd/law.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
+#endif
+	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd.c
new file mode 100644
index 0000000..d7dd470
--- /dev/null
+++ b/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <netdev.h>
+
+void sdram_init(void);
+phys_size_t fixed_sdram(void);
+int mpc8610hpcd_diu_init(void);
+
+
+/* called before any console output */
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u8 tmp_val, version;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	/*Do not use 8259PIC*/
+	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
+
+	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
+	version = in_8(pixis_base + PIXIS_PVER);
+	if(version >= 0x07) {
+		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
+	}
+
+	/* Using this for DIU init before the driver in linux takes over
+	 *  Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+
+	tmp_val = 0xBF;
+	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+
+	tmp_val = 0x10;
+	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
+		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	mcm->abcr |= 0x00010000; /* 0 */
+	mcm->hpmr3 = 0x80000008; /* 4c */
+	mcm->hpmr0 = 0;
+	mcm->hpmr1 = 0;
+	mcm->hpmr2 = 0;
+	mcm->hpmr4 = 0;
+	mcm->hpmr5 = 0;
+
+	return 0;
+}
+
+
+phys_size_t
+initdram(int board_type)
+{
+	phys_size_t dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram();
+#endif
+
+	setup_ddr_bat(dram_size);
+
+	puts(" DDR: ");
+	return dram_size;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+	uint d_init;
+
+	ddr->cs0_bnds = 0x0000001f;
+	ddr->cs0_config = 0x80010202;
+
+	ddr->timing_cfg_3 = 0x00000000;
+	ddr->timing_cfg_0 = 0x00260802;
+	ddr->timing_cfg_1 = 0x3935d322;
+	ddr->timing_cfg_2 = 0x14904cc8;
+	ddr->sdram_mode = 0x00480432;
+	ddr->sdram_mode_2 = 0x00000000;
+	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
+	ddr->sdram_data_init = 0xDEADBEEF;
+	ddr->sdram_clk_cntl = 0x03800000;
+	ddr->sdram_cfg_2 = 0x04400010;
+
+#if defined(CONFIG_DDR_ECC)
+	ddr->err_int_en = 0x0000000d;
+	ddr->err_disable = 0x00000000;
+	ddr->err_sbe = 0x00010000;
+#endif
+	asm("sync;isync");
+
+	udelay(500);
+
+	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+		udelay(1000);
+
+	debug("DDR: memory initialized\n\n");
+	asm("sync; isync");
+	udelay(500);
+#endif
+
+	return 512 * 1024 * 1024;
+#endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				 PCI_ENET0_MEMADDR,
+				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
+	{}
+};
+#endif
+
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+config_table:pci_mpc86xxcts_config_table
+#endif
+};
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr;
+	int first_free_busno;
+	int pci_agent;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+
+	first_free_busno = fsl_pcie_init_board(0);
+
+#ifdef CONFIG_PCI1
+	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI: connected to PCI slots as %s" \
+			" (base address %lx)\n",
+			pci_agent ? "Agent" : "Host",
+			pci_info.regs);
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+}
+#endif
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+	u8 i;
+	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	i = in_8(pixis_base + PIXIS_SPD);
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33333000;
+		break;
+	case 1:
+		val = 39999600;
+		break;
+	case 2:
+		val = 49999500;
+		break;
+	case 3:
+		val = 66666000;
+		break;
+	case 4:
+		val = 83332500;
+		break;
+	case 5:
+		val = 99999000;
+		break;
+	case 6:
+		val = 133332000;
+		break;
+	case 7:
+		val = 166665000;
+		break;
+	}
+
+	return val;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void board_reset(void)
+{
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	out_8(pixis_base + PIXIS_RST, 0);
+
+	while (1)
+		;
+}
diff --git a/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
new file mode 100644
index 0000000..81e53e7
--- /dev/null
+++ b/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <fsl_diu_fb.h>
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
+	unsigned long speed_ccb, temp, pixval;
+
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000/pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+	temp = *guts_clkdvdr & 0x2000FFFF;
+	*guts_clkdvdr = temp;				/* turn off clock */
+	*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
+	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+}
+
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
+{
+	char *monitor_port;
+	int gamma_fix;
+	unsigned int pixel_format;
+	unsigned char tmp_val;
+	unsigned char pixis_arch;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+	pixis_arch = in_8(pixis_base + PIXIS_VER);
+
+	monitor_port = getenv("monitor");
+	if (!strncmp(monitor_port, "0", 1)) {	/* 0 - DVI */
+		*xres = 1280;
+		*yres = 1024;
+		if (pixis_arch == 0x01)
+			pixel_format = 0x88882317;
+		else
+			pixel_format = 0x88883316;
+		gamma_fix = 0;
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
+
+	} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+		*xres = 1024;
+		*yres = 768;
+		pixel_format = 0x88883316;
+		gamma_fix = 0;
+		out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
+
+	} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
+		*xres = 1280;
+		*yres = 1024;
+		pixel_format = 0x88883316;
+		gamma_fix = 1;
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
+
+	} else {	/* DVI */
+		*xres = 1280;
+		*yres = 1024;
+		pixel_format = 0x88882317;
+		gamma_fix = 0;
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
+	}
+
+	return fsl_diu_init(*xres, pixel_format, gamma_fix);
+}
diff --git a/u-boot/board/freescale/mpc8641hpcn/Makefile b/u-boot/board/freescale/mpc8641hpcn/Makefile
new file mode 100644
index 0000000..433c132
--- /dev/null
+++ b/u-boot/board/freescale/mpc8641hpcn/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mpc8641hpcn/ddr.c b/u-boot/board/freescale/mpc8641hpcn/ddr.c
new file mode 100644
index 0000000..8dc249b
--- /dev/null
+++ b/u-boot/board/freescale/mpc8641hpcn/ddr.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+		if (ctrl_num == 0 && i == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		}
+		if (ctrl_num == 1 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS3;
+		}
+		if (ctrl_num == 1 && i == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS4;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+} board_specific_parameters_t;
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+const board_specific_parameters_t board_specific_parameters[2][16] = {
+	{
+	/* 	memory controller 0		 	*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay	*/
+		{  0, 333,    4,    7,   7,     3},
+		{334, 400,    4,    7,   9,     3},
+		{401, 549,    4,    7,   9,     3},
+		{550, 650,    4,    7,  10,     4},
+
+		{  0, 333,    3,    7,   7,     3},
+		{334, 400,    3,    7,   9,     3},
+		{401, 549,    3,    7,   9,     3},
+		{550, 650,    3,    7,  10,     4},
+
+		{  0, 333,    2,    7,   7,     3},
+		{334, 400,    2,    7,   9,     3},
+		{401, 549,    2,    7,   9,     3},
+		{550, 650,    2,    7,  10,     4},
+
+		{  0, 333,    1,    7,   7,     3},
+		{334, 400,    1,    7,   9,     3},
+		{401, 549,    1,    7,   9,     3},
+		{550, 650,    1,    7,  10,     4}
+	},
+
+	{
+	/* 	memory controller 1			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata	*/
+	/*       mhz| mhz|ranks|adjst|    | delay	*/
+		{  0, 333,    4,    7,   7,    3},
+		{334, 400,    4,    7,   9,    3},
+		{401, 549,    4,    7,   9,    3},
+		{550, 650,    4,    7,  10,    4},
+
+		{  0, 333,    3,    7,   7,    3},
+		{334, 400,    3,    7,   9,    3},
+		{401, 549,    3,    7,   9,    3},
+		{550, 650,    3,    7,  10,    4},
+
+		{  0, 333,    2,    7,   7,    3},
+		{334, 400,    2,    7,   9,    3},
+		{401, 549,    2,    7,   9,    3},
+		{550, 650,    2,    7,  10,    4},
+
+		{  0, 333,    1,    7,   7,    3},
+		{334, 400,    1,    7,   9,    3},
+		{401, 549,    1,    7,   9,    3},
+		{550, 650,    1,    7,  10,    4}
+	}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			dimm_params_t *pdimm,
+			unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+			&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+			sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	u32 j;
+	ulong ddr_freq;
+
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {      /* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
+				(pdimm[i/2].n_ranks != 0)) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			} else {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			}
+		}
+	}
+
+	/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000;
+	for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+		if (pdimm[j].n_ranks > 0) {
+			for (i = 0; i < num_params; i++) {
+				if (ddr_freq >= pbsp->datarate_mhz_low &&
+				ddr_freq <= pbsp->datarate_mhz_high &&
+				pdimm[j].n_ranks == pbsp->n_ranks) {
+					popts->clk_adjust = pbsp->clk_adjust;
+					popts->cpo_override = pbsp->cpo;
+					popts->write_data_delay =
+						pbsp->write_data_delay;
+					break;
+				}
+				pbsp++;
+			}
+		}
+	}
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+}
diff --git a/u-boot/board/freescale/mpc8641hpcn/law.c b/u-boot/board/freescale/mpc8641hpcn/law.c
new file mode 100644
index 0000000..08f1eb2
--- /dev/null
+++ b/u-boot/board/freescale/mpc8641hpcn/law.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0x8000_0000     0x9fff_ffff     PCIE1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCIE2 MEM                512M
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
+ * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0xffc0_0000     0xffc0_ffff     PCIE1 IO                 64K
+ * 0xffc1_0000     0xffc1_ffff     PCIE2 IO                 64K
+ * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
+ * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
+ * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR doesn't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+#endif
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/u-boot/board/freescale/mpc8641hpcn/mpc8641hpcn.c
new file mode 100644
index 0000000..166ff0c
--- /dev/null
+++ b/u-boot/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright 2006, 2007, 2010 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+
+phys_size_t fixed_sdram(void);
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	if (vboot & PIXIS_VBOOT_FMAP)
+		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+	else
+		puts ("Promjet\n");
+
+#ifdef CONFIG_PHYS_64BIT
+	printf ("       36-bit physical address map\n");
+#endif
+	return 0;
+}
+
+phys_size_t
+initdram(int board_type)
+{
+	phys_size_t dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram();
+#endif
+
+	setup_ddr_bat(dram_size);
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t
+fixed_sdram(void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
+	ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
+
+#if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000008D;
+	ddr->err_sbe = 0x00ff0000;
+#endif
+	asm("sync;isync");
+
+	udelay(500);
+
+#if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+#else
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+#endif
+	asm("sync; isync");
+
+	udelay(500);
+#endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+
+#ifdef CONFIG_PCIE1
+		/*
+		 * Activate ULI1575 legacy chip by performing a fake
+		 * memory access.  Needed to make ULI RTC work.
+		 */
+		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
+				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
+#endif /* CONFIG_PCIE1 */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int off;
+	u64 *tmp;
+	u32 *addrcells;
+
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+
+	/*
+	 * Warn if it looks like the device tree doesn't match u-boot.
+	 * This is just an estimation, based on the location of CCSR,
+	 * which is defined by the "reg" property in the soc node.
+	 */
+	off = fdt_path_offset(blob, "/soc8641");
+	addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+	tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+	if (tmp) {
+		u64 addr;
+		if (addrcells && (*addrcells == 1))
+			addr = *(u32 *)tmp;
+		else
+			addr = *tmp;
+
+		if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+			printf("WARNING: The CCSRBAR address in your .dts "
+			       "does not match the address of the CCSR "
+			       "in u-boot.  This means your .dts might "
+			       "be old.\n");
+	}
+}
+#endif
+
+
+/*
+ * get_board_sys_clk
+ *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+	u8 i, go_bit, rd_clks;
+	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	go_bit = in_8(pixis_base + PIXIS_VCTL);
+	go_bit &= 0x01;
+
+	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
+	rd_clks &= 0x1C;
+
+	/*
+	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
+	 * should we be using the AUX register. Remember, we also set the
+	 * GO bit to boot from the alternate bank on the on-board flash
+	 */
+
+	if (go_bit) {
+		if (rd_clks == 0x1c)
+			i = in_8(pixis_base + PIXIS_AUX);
+		else
+			i = in_8(pixis_base + PIXIS_SPD);
+	} else {
+		i = in_8(pixis_base + PIXIS_SPD);
+	}
+
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33000000;
+		break;
+	case 1:
+		val = 40000000;
+		break;
+	case 2:
+		val = 50000000;
+		break;
+	case 3:
+		val = 66000000;
+		break;
+	case 4:
+		val = 83000000;
+		break;
+	case 5:
+		val = 100000000;
+		break;
+	case 6:
+		val = 134000000;
+		break;
+	case 7:
+		val = 166000000;
+		break;
+	}
+
+	return val;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	/* Initialize TSECs */
+	cpu_eth_init(bis);
+	return pci_eth_init(bis);
+}
+
+void board_reset(void)
+{
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	out_8(pixis_base + PIXIS_RST, 0);
+
+	while (1)
+		;
+}
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/freescale/mx31ads/Makefile b/u-boot/board/freescale/mx31ads/Makefile
new file mode 100644
index 0000000..be4d61a
--- /dev/null
+++ b/u-boot/board/freescale/mx31ads/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx31ads.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mx31ads/config.mk b/u-boot/board/freescale/mx31ads/config.mk
new file mode 100644
index 0000000..2303f30
--- /dev/null
+++ b/u-boot/board/freescale/mx31ads/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE = 0x87f00000
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/u-boot/board/freescale/mx31ads/lowlevel_init.S b/u-boot/board/freescale/mx31ads/lowlevel_init.S
new file mode 100644
index 0000000..e166058
--- /dev/null
+++ b/u-boot/board/freescale/mx31ads/lowlevel_init.S
@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x77777777
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =0x53F00000
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+
+	ldr r0, =0x53F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =0x43F04000
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =0x00302154
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =0xB8003000
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro  init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =0x43FAC200
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+	ldr r0, =WEIM_BASE
+	ldr r1, =0x0000D843
+	str r1, [r0, #0x40]
+	ldr r1, =0x22252521
+	str r1, [r0, #0x44]
+	ldr r1, =0x22220A00
+	str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Redboot initializes very early AIPS, what for?
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF */
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	init_cs4
+
+	/* Image Processing Unit: */
+	/* Too early to switch display on? */
+	REG	IPU_CONF, IPU_CONF_DI_EN	/* Switch on Display Interface */
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5		/* Use CKIH, MCU PLL off */
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE			/* MCU PLL on */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS	/* Switch to MCU PLL */
+
+	/* PBC CPLD on CS4 */
+	mov	r1, #CS4_BASE
+	ldrh	r1, [r1, #0x2]
+	/* Is 27MHz switch set? */
+	ands	r1, r1, #0x10
+
+	/* 532-133-66.5 */
+	ldr	r0, =CCM_BASE
+	ldr	r1, =0xFF871D58
+	/* PDR0 */
+	str	r1, [r0, #0x4]
+	ldreq	r1, MPCTL_PARAM_532
+	ldrne	r1, MPCTL_PARAM_532_27
+	/* MPCTL */
+	str	r1, [r0, #0x10]
+
+	/* Set UPLL=240MHz, USB=60MHz */
+	ldr	r1, =0x49FCFE7F
+	/* PDR1 */
+	str	r1, [r0, #0x8]
+	ldreq	r1, UPCTL_PARAM_240
+	ldrne	r1, UPCTL_PARAM_240_27
+	/* UPCTL */
+	str	r1, [r0, #0x14]
+	/* default CLKO to 1/8 of the ARM core */
+	mov	r1, #0x000002C0
+	add	r1, r1, #0x00000006
+	/* COSR */
+	str	r1, [r0, #0x1c]
+
+	/* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
+/*	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+
+	/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+/*	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
+	/* Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x006ac73a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+	mov	pc, lr
+
+MPCTL_PARAM_532:
+	.word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+	.word (((1-1) << 26) + ((15-1) << 16) + (9  << 10) + (13 << 0))
+UPCTL_PARAM_240:
+	.word (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
+UPCTL_PARAM_240_27:
+	.word (((2-1) << 26) + ((9 -1) << 16) + (8  << 10) + (8  << 0))
diff --git a/u-boot/board/freescale/mx31ads/mx31ads.c b/u-boot/board/freescale/mx31ads/mx31ads.c
new file mode 100644
index 0000000..bc25c6d
--- /dev/null
+++ b/u-boot/board/freescale/mx31ads/mx31ads.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init (void)
+{
+	int i;
+
+	/* CS0: Nor Flash */
+	/*
+	 * CS0L and CS0A values are from the RedBoot sources by Freescale
+	 * and are also equal to those used by Sascha Hauer for the Phytec
+	 * i.MX31 board. CS0U is just a slightly optimized hardware default:
+	 * the only non-zero field "Wait State Control" is set to half the
+	 * default value.
+	 */
+	__REG(CSCR_U(0)) = 0x00000f00;
+	__REG(CSCR_L(0)) = 0x10000D03;
+	__REG(CSCR_A(0)) = 0x00720900;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* SPI2 */
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+	/* PBC setup */
+	/* Enable UART transceivers also reset the Ethernet/external UART */
+	readw(CS4_BASE + 4);
+
+	writew(0x8023, CS4_BASE + 4);
+
+	/* RedBoot also has an empty loop with 100000 iterations here -
+	 * clock doesn't run yet */
+	for (i = 0; i < 100000; i++)
+		;
+
+	/* Clear the reset, toggle the LEDs */
+	writew(0xDF, CS4_BASE + 6);
+
+	/* clock still doesn't run */
+	for (i = 0; i < 100000; i++)
+		;
+
+	/* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
+	readb(CS4_BASE + 8);
+	readb(CS4_BASE + 7);
+	readb(CS4_BASE + 8);
+	readb(CS4_BASE + 7);
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX31ADS;	/* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf("Board: MX31ADS\n");
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/freescale/mx31ads/u-boot.lds b/u-boot/board/freescale/mx31ads/u-boot.lds
new file mode 100644
index 0000000..ecd9707
--- /dev/null
+++ b/u-boot/board/freescale/mx31ads/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+	  arch/arm/cpu/arm1136/start.o			(.text)
+	  board/freescale/mx31ads/libmx31ads.o	(.text)
+	  arch/arm/lib/libarm.o			(.text)
+	  net/libnet.o				(.text)
+	  drivers/mtd/libmtd.o			(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/u-boot/board/freescale/mx31pdk/Makefile b/u-boot/board/freescale/mx31pdk/Makefile
new file mode 100644
index 0000000..0287885
--- /dev/null
+++ b/u-boot/board/freescale/mx31pdk/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx31pdk.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mx31pdk/config.mk b/u-boot/board/freescale/mx31pdk/config.mk
new file mode 100644
index 0000000..de2c642
--- /dev/null
+++ b/u-boot/board/freescale/mx31pdk/config.mk
@@ -0,0 +1,5 @@
+ifdef CONFIG_NAND_SPL
+CONFIG_SYS_TEXT_BASE = 0x87ec0000
+else
+CONFIG_SYS_TEXT_BASE = 0x87f00000
+endif
diff --git a/u-boot/board/freescale/mx31pdk/lowlevel_init.S b/u-boot/board/freescale/mx31pdk/lowlevel_init.S
new file mode 100644
index 0000000..cd0503e
--- /dev/null
+++ b/u-boot/board/freescale/mx31pdk/lowlevel_init.S
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr	r0, =ARM_PPMRR      /* start from AIPS 2GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+
+	write32	IPU_CONF, IPU_CONF_DI_EN
+	write32	CCM_CCMR, CCM_CCMR_SETUP
+
+	wait_timer	0x40000
+
+	write32	CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
+	write32	CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
+
+	/* Set up clock to 532MHz */
+	write32	CCM_PDR0, CCM_PDR0_SETUP_532MHZ
+	write32	CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
+
+	write32	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+	/* Set up MX31 DDR pins */
+	write32	IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
+	write32	IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
+	write32	IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
+	write32	IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
+	write32	IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
+	write32	IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
+	write32	IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
+	write32	IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
+	write32	IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
+	write32	IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
+	write32	IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
+	write32	IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
+	write32	IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
+	write32	IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
+	write32	IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
+	write32	IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
+	write32	IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
+	write32	IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
+	write32	IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
+	write32	IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
+	write32	IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
+	write32	IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
+	write32	IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
+	write32	IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
+	write32	IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
+	write32	IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
+	write32	IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
+
+	/* Set up MX31 DDR Memory Controller */
+	write32	WEIM_ESDMISC, ESDMISC_MDDR_SETUP
+	write32	WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
+
+	/* Perform DDR init sequence */
+	write32	WEIM_ESDCTL0, ESDCTL_PRECHARGE
+	write32	CSD0_BASE | 0x0f00, 0x12344321
+	write32	WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
+	write32	CSD0_BASE, 0x12344321
+	write32	CSD0_BASE, 0x12344321
+	write32	WEIM_ESDCTL0, ESDCTL_LOADMODEREG
+	write8	CSD0_BASE | 0x00000033, 0xda
+	write8	CSD0_BASE | 0x01000000, 0xff
+	write32	WEIM_ESDCTL0, ESDCTL_RW
+	write32	CSD0_BASE, 0xDEADBEEF
+	write32	WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
+
+	mov	pc, lr
diff --git a/u-boot/board/freescale/mx31pdk/mx31pdk.c b/u-boot/board/freescale/mx31pdk/mx31pdk.c
new file mode 100644
index 0000000..a9f0fb4
--- /dev/null
+++ b/u-boot/board/freescale/mx31pdk/mx31pdk.c
@@ -0,0 +1,84 @@
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+int board_early_init_f(void)
+{
+	/* CS5: CPLD incl. network controller */
+	__REG(CSCR_U(5)) = 0x0000d843;
+	__REG(CSCR_L(5)) = 0x22252521;
+	__REG(CSCR_A(5)) = 0x22220a00;
+
+	/* Setup UART1 and SPI2 pins */
+	mx31_uart1_hw_init();
+	mx31_spi2_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: i.MX31 MAX PDK (3DS)\n");
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/freescale/mx35pdk/Makefile b/u-boot/board/freescale/mx35pdk/Makefile
new file mode 100644
index 0000000..b4a60d6
--- /dev/null
+++ b/u-boot/board/freescale/mx35pdk/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx35pdk.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mx35pdk/lowlevel_init.S b/u-boot/board/freescale/mx35pdk/lowlevel_init.S
new file mode 100644
index 0000000..9b0f1b5
--- /dev/null
+++ b/u-boot/board/freescale/mx35pdk/lowlevel_init.S
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+#include "mx35pdk.h"
+
+/*
+ * return soc version
+ * 	0x10:  TO1
+ *	0x20:  TO2
+ *	0x30:  TO3
+ */
+.macro check_soc_version ret, tmp
+	ldr \tmp, =IIM_BASE_ADDR
+	ldr \ret, [\tmp, #IIM_SREV]
+	cmp \ret, #0x00
+	moveq \tmp, #ROMPATCH_REV
+	ldreq \ret, [\tmp]
+	moveq \ret, \ret, lsl #4
+	addne \ret, \ret, #0x10
+.endm
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_MPR_CONFIG
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_OPACR_CONFIG
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+.endm
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =MAX_BASE_ADDR
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =MAX_MPR_CONFIG
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =MAX_SGPCR_CONFIG
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =MAX_MGPCR_CONFIG
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm
+
+/* M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =M3IF_BASE_ADDR
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =M3IF_CONFIG
+	str r0, [r1]  /* M3IF control reg */
+.endm
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+	ldr r0, =DBG_BASE_ADDR
+	ldr r1, =DBG_CSCR_U_CONFIG
+	str r1, [r0, #0x00]
+	ldr r1, =DBG_CSCR_L_CONFIG
+	str r1, [r0, #0x04]
+	ldr r1, =DBG_CSCR_A_CONFIG
+	str r1, [r0, #0x08]
+.endm
+
+/* clock setup */
+.macro init_clock
+	ldr r0, =CCM_BASE_ADDR
+
+	/* default CLKO to 1/32 of the ARM core*/
+	ldr r1, [r0, #CLKCTL_COSR]
+	bic r1, r1, #0x00000FF00
+	bic r1, r1, #0x0000000FF
+	mov r2, #0x00006C00
+	add r2, r2, #0x67
+	orr r1, r1, r2
+	str r1, [r0, #CLKCTL_COSR]
+
+	ldr r2, =CCM_CCMR_CONFIG
+	str r2, [r0, #CLKCTL_CCMR]
+
+	check_soc_version r1, r2
+	cmp r1, #CHIP_REV_2_0
+	ldrhs r3, =CCM_MPLL_532_HZ
+	bhs 1f
+	ldr r2, [r0, #CLKCTL_PDR0]
+	tst r2, #CLKMODE_CONSUMER
+	ldrne r3, =CCM_MPLL_532_HZ  /* consumer path*/
+	ldreq r3, =CCM_MPLL_399_HZ  /* auto path*/
+1:
+	str r3, [r0, #CLKCTL_MPCTL]
+
+	ldr r1, =CCM_PPLL_300_HZ
+	str r1, [r0, #CLKCTL_PPCTL]
+
+	ldr r1, =CCM_PDR0_CONFIG
+	bic r1, r1, #0x800000
+	str r1, [r0, #CLKCTL_PDR0]
+
+	ldr r1, [r0, #CLKCTL_CGR0]
+	orr r1, r1, #0x0C300000
+	str r1, [r0, #CLKCTL_CGR0]
+
+	ldr r1, [r0, #CLKCTL_CGR1]
+	orr r1, r1, #0x00000C00
+	orr r1, r1, #0x00000003
+	str r1, [r0, #CLKCTL_CGR1]
+.endm
+
+.macro setup_sdram
+	ldr r0, =ESDCTL_BASE_ADDR
+	mov r3, #0x2000
+	str r3, [r0, #0x0]
+	str r3, [r0, #0x8]
+
+	/*ip(r12) has used to save lr register in upper calling*/
+	mov fp, lr
+
+	mov r5, #0x00
+	mov r2, #0x00
+	mov r1, #CSD0_BASE_ADDR
+	bl setup_sdram_bank
+	cmp r3, #0x0
+	orreq r5, r5, #1
+	eorne r2, r2, #0x1
+	blne setup_sdram_bank
+
+	mov lr, fp
+
+1:
+	ldr r3, =ESDCTL_DELAY_LINE5
+	str r3, [r0, #0x30]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+	mov r10, lr
+
+	mrc 15, 0, r1, c1, c0, 0
+
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #7
+	mcr 15, 0, r0, c1, c0, 1
+	orr r1, r1, #(1<<11)
+
+	/* Set unaligned access enable */
+	orr r1, r1, #(1<<22)
+
+	/* Set low int latency enable */
+	orr r1, r1, #(1<<21)
+
+	mcr 15, 0, r1, c1, c0, 0
+
+	mov r0, #0
+
+	/* Set branch prediction enable */
+	mcr 15, 0, r0, c15, c2, 4
+
+	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
+	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+
+	/*
+	 * initializes very early AIPS
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF
+	 * Also setup the Peripheral Port Remap register inside the core
+	 */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_clock
+	init_debug_board
+
+	cmp pc, #PHYS_SDRAM_1
+	blo init_sdram_start
+	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+	blo skip_sdram_setup
+
+init_sdram_start:
+	/*init_sdram*/
+	setup_sdram
+
+skip_sdram_setup:
+	mov lr, r10
+	mov pc, lr
+
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ */
+setup_sdram_bank:
+	mov r3, #0xE
+	tst r2, #0x1
+	orreq r3, r3, #0x300 /*DDR2*/
+	str r3, [r0, #0x10]
+	bic r3, r3, #0x00A
+	str r3, [r0, #0x10]
+	beq 2f
+
+	mov r3, #0x20000
+1:      subs r3, r3, #1
+	bne 1b
+
+2:      tst r2, #0x1
+	ldreq r3, =ESDCTL_DDR2_CONFIG
+	ldrne r3, =ESDCTL_MDDR_CONFIG
+	cmp r1, #CSD1_BASE_ADDR
+	strlo r3, [r0, #0x4]
+	strhs r3, [r0, #0xC]
+
+	ldr r3, =ESDCTL_0x92220000
+	strlo r3, [r0, #0x0]
+	strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+	ldr r4, =ESDCTL_PRECHARGE
+	strb r3, [r1, r4]
+
+	tst r2, #0x1
+	bne skip_set_mode
+
+	cmp r1, #CSD1_BASE_ADDR
+	ldr r3, =ESDCTL_0xB2220000
+	strlo r3, [r0, #0x0]
+	strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+	ldr r4, =ESDCTL_DDR2_EMR2
+	strb r3, [r1, r4]
+	ldr r4, =ESDCTL_DDR2_EMR3
+	strb r3, [r1, r4]
+	ldr r4, =ESDCTL_DDR2_EN_DLL
+	strb r3, [r1, r4]
+	ldr r4, =ESDCTL_DDR2_RESET_DLL
+	strb r3, [r1, r4]
+
+	ldr r3, =ESDCTL_0x92220000
+	strlo r3, [r0, #0x0]
+	strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+	ldr r4, =ESDCTL_PRECHARGE
+	strb r3, [r1, r4]
+
+skip_set_mode:
+	cmp r1, #CSD1_BASE_ADDR
+	ldr r3, =ESDCTL_0xA2220000
+	strlo r3, [r0, #0x0]
+	strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+	strb r3, [r1]
+	strb r3, [r1]
+
+	ldr r3, =ESDCTL_0xB2220000
+	strlo r3, [r0, #0x0]
+	strhs r3, [r0, #0x8]
+	tst r2, #0x1
+	ldreq r4, =ESDCTL_DDR2_MR
+	ldrne r4, =ESDCTL_MDDR_MR
+	mov r3, #0xDA
+	strb r3, [r1, r4]
+	ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
+	streqb r3, [r1, r4]
+	ldreq r4, =ESDCTL_DDR2_EN_DLL
+	ldrne r4, =ESDCTL_MDDR_EMR
+	strb r3, [r1, r4]
+
+	cmp r1, #CSD1_BASE_ADDR
+	ldr r3, =ESDCTL_0x82228080
+	strlo r3, [r0, #0x0]
+	strhs r3, [r0, #0x8]
+
+	tst r2, #0x1
+	moveq r4, #0x20000
+	movne r4, #0x200
+1:      subs r4, r4, #1
+	bne 1b
+
+	str r3, [r1, #0x100]
+	ldr r4, [r1, #0x100]
+	cmp r3, r4
+	movne r3, #1
+	moveq r3, #0
+
+	mov pc, lr
diff --git a/u-boot/board/freescale/mx35pdk/mx35pdk.c b/u-boot/board/freescale/mx35pdk/mx35pdk.c
new file mode 100644
index 0000000..da926e5
--- /dev/null
+++ b/u-boot/board/freescale/mx35pdk/mx35pdk.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <fsl_pmic.h>
+#include <mc9sdz60.h>
+#include <mc13892.h>
+#include <linux/types.h>
+#include <mxc_gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef BOARD_LATE_INIT
+#error "BOARD_LATE_INIT must be set for this board"
+#endif
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_i2c(void)
+{
+	int pad;
+
+	/* setup pins for I2C1 */
+	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+	mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+	int pad;
+
+	/* setup pins for FEC */
+	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+	pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
+			PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
+
+	mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
+			 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+}
+
+int board_early_init_f(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	/* enable clocks */
+	writel(readl(&ccm->cgr0) |
+		MXC_CCM_CGR0_EMI_MASK |
+		MXC_CCM_CGR0_EDI0_MASK |
+		MXC_CCM_CGR0_EPIT1_MASK,
+		&ccm->cgr0);
+
+	writel(readl(&ccm->cgr1) |
+		MXC_CCM_CGR1_FEC_MASK |
+		MXC_CCM_CGR1_GPIO1_MASK |
+		MXC_CCM_CGR1_GPIO2_MASK |
+		MXC_CCM_CGR1_GPIO3_MASK |
+		MXC_CCM_CGR1_I2C1_MASK |
+		MXC_CCM_CGR1_I2C2_MASK |
+		MXC_CCM_CGR1_IPU_MASK,
+		&ccm->cgr1);
+
+	/* Setup NAND */
+	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+	setup_iomux_i2c();
+	setup_iomux_fec();
+	setup_iomux_spi();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;	/* board id for linux */
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+static inline int pmic_detect(void)
+{
+	int id;
+
+	id = pmic_reg_read(REG_IDENTIFICATION);
+
+	id = (id >> 6) & 0x7;
+	if (id == 0x7)
+		return 1;
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	int rev;
+
+	rev = pmic_detect();
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+int board_late_init(void)
+{
+	u8 val;
+	u32 pmic_val;
+
+	if (pmic_detect()) {
+		mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
+					MUX_CONFIG_ALT1);
+
+		pmic_val = pmic_reg_read(REG_SETTING_0);
+		pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
+		pmic_val = pmic_reg_read(REG_MODE_0);
+		pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
+
+		mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
+		mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+
+		mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_set(37, 1);
+	}
+
+	val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
+	mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
+	mdelay(200);
+
+	val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
+	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+	mdelay(200);
+
+	val |= 0x80;
+	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 cpu_rev = get_cpu_rev();
+
+	/*
+	 * Be sure that I2C is initialized to check
+	 * the board revision
+	 */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/* Print board revision */
+	printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
+
+	/* Print CPU revision */
+	printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
+
+	switch (readl(&ccm->rcsr) & 0x0F) {
+	case 0x0000:
+		puts("POR");
+		break;
+	case 0x0002:
+		puts("JTAG");
+		break;
+	case 0x0004:
+		puts("RST");
+		break;
+	case 0x0008:
+		puts("WDT");
+		break;
+	default:
+		puts("unknown");
+	}
+	puts("]\n");
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+	cpu_eth_init(bis);
+
+	return rc;
+}
diff --git a/u-boot/board/freescale/mx35pdk/mx35pdk.h b/u-boot/board/freescale/mx35pdk/mx35pdk.h
new file mode 100644
index 0000000..409aeb2
--- /dev/null
+++ b/u-boot/board/freescale/mx35pdk/mx35pdk.h
@@ -0,0 +1,101 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define AIPS_MPR_CONFIG		0x77777777
+#define AIPS_OPACR_CONFIG	0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG		0x00302154
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG	0x00000010
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG	0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG	0x00000040
+
+#define DBG_BASE_ADDR		WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG	0x0000D843
+#define DBG_CSCR_L_CONFIG	0x22252521
+#define DBG_CSCR_A_CONFIG	0x22220A00
+
+#define CCM_CCMR_CONFIG		0x003F4208
+#define CCM_PDR0_CONFIG		0x00801000
+
+#define PLL_BRM_OFFSET	31
+#define PLL_PD_OFFSET	26
+#define PLL_MFD_OFFSET	16
+#define PLL_MFI_OFFSET	10
+
+#define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
+#define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
+#define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
+#define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+/* MEMORY SETTING */
+#define ESDCTL_0x92220000	0x92220000
+#define ESDCTL_0xA2220000	0xA2220000
+#define ESDCTL_0xB2220000	0xB2220000
+#define ESDCTL_0x82228080	0x82228080
+
+#define ESDCTL_PRECHARGE	0x00000400
+
+#define ESDCTL_MDDR_CONFIG	0x007FFC3F
+#define ESDCTL_MDDR_MR		0x00000033
+#define ESDCTL_MDDR_EMR		0x02000000
+
+#define ESDCTL_DDR2_CONFIG	0x007FFC3F
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5	0x00F49F00
+#endif				/* __BOARD_MX35_3STACK_H */
diff --git a/u-boot/board/freescale/mx51evk/Makefile b/u-boot/board/freescale/mx51evk/Makefile
new file mode 100644
index 0000000..3344c28
--- /dev/null
+++ b/u-boot/board/freescale/mx51evk/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx51evk.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mx51evk/config.mk b/u-boot/board/freescale/mx51evk/config.mk
new file mode 100644
index 0000000..6e90671
--- /dev/null
+++ b/u-boot/board/freescale/mx51evk/config.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
diff --git a/u-boot/board/freescale/mx51evk/imximage.cfg b/u-boot/board/freescale/mx51evk/imximage.cfg
new file mode 100644
index 0000000..a875e8f
--- /dev/null
+++ b/u-boot/board/freescale/mx51evk/imximage.cfg
@@ -0,0 +1,119 @@
+#
+# (C Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM	spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x73FA88a0 0x200
+DATA 4 0x73FA850c 0x20c5
+DATA 4 0x73FA8510 0x20c5
+DATA 4 0x73FA883c 0x2
+DATA 4 0x73FA8848 0x2
+DATA 4 0x73FA84b8 0xe7
+DATA 4 0x73FA84bc 0x45
+DATA 4 0x73FA84c0 0x45
+DATA 4 0x73FA84c4 0x45
+DATA 4 0x73FA84c8 0x45
+DATA 4 0x73FA8820 0x0
+DATA 4 0x73FA84a4 0x3
+DATA 4 0x73FA84a8 0x3
+DATA 4 0x73FA84ac 0xe3
+DATA 4 0x73FA84b0 0xe3
+DATA 4 0x73FA84b4 0xe3
+DATA 4 0x73FA84cc 0xe3
+DATA 4 0x73FA84d0 0xe2
+
+DATA 4 0x73FA882c 0x6
+DATA 4 0x73FA88a4 0x6
+DATA 4 0x73FA88ac 0x6
+DATA 4 0x73FA88b8 0x6
+
+# Setting DDR for micron
+# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+# CAS=3 BL=4
+# ESDCTL_ESDCTL0
+DATA 4 0x83FD9000 0x82a20000
+# ESDCTL_ESDCTL1
+DATA 4 0x83FD9008 0x82a20000
+# ESDCTL_ESDMISC
+DATA 4 0x83FD9010 0x000ad0d0
+# ESDCTL_ESDCFG0
+DATA 4 0x83FD9004 0x333574aa
+# ESDCTL_ESDCFG1
+DATA 4 0x83FD900C 0x333574aa
+
+# Init DRAM on CS0
+# ESDCTL_ESDSCR
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x0000801a
+DATA 4 0x83FD9014 0x0000801b
+DATA 4 0x83FD9014 0x00448019
+DATA 4 0x83FD9014 0x07328018
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x06328018
+DATA 4 0x83FD9014 0x03808019
+DATA 4 0x83FD9014 0x00408019
+DATA 4 0x83FD9014 0x00008000
+
+# Init DRAM on CS1
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x0000801e
+DATA 4 0x83FD9014 0x0000801f
+DATA 4 0x83FD9014 0x0000801d
+DATA 4 0x83FD9014 0x0732801c
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x0632801c
+DATA 4 0x83FD9014 0x0380801d
+DATA 4 0x83FD9014 0x0040801d
+DATA 4 0x83FD9014 0x00008004
+
+# Write to CTL0
+DATA 4 0x83FD9000 0xb2a20000
+# Write to CTL1
+DATA 4 0x83FD9008 0xb2a20000
+# ESDMISC
+DATA 4 0x83FD9010 0x000ad6d0
+#ESDCTL_ESDCDLYGD
+DATA 4 0x83FD9034 0x90000000
+DATA 4 0x83FD9014 0x00000000
diff --git a/u-boot/board/freescale/mx51evk/mx51evk.c b/u-boot/board/freescale/mx51evk/mx51evk.c
new file mode 100644
index 0000000..02a765d
--- /dev/null
+++ b/u-boot/board/freescale/mx51evk/mx51evk.c
@@ -0,0 +1,471 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+	{MMC_SDHC2_BASE_ADDR, 1},
+};
+#endif
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+
+	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
+
+	/* FEC RDATA[3] */
+	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+	/* FEC RDATA[2] */
+	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+	/* FEC RDATA[1] */
+	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+	/* FEC RDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+	/* FEC TDATA[3] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
+
+	/* FEC TDATA[2] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
+
+	/* FEC TDATA[1] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
+
+	/* FEC TDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
+
+	/* FEC TX_ER */
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
+
+	/* FEC TX_COL */
+	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+
+	/* FEC RX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+	/* FEC RX_CRS */
+	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+	/* FEC RX_DV */
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+}
+
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
+
+	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
+
+	/* de-select SS1 of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
+
+	/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
+
+	/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
+
+	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
+}
+#endif
+
+static void power_init(void)
+{
+	unsigned int val;
+	unsigned int reg;
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+	/* Write needed to Power Gate 2 register */
+	val = pmic_reg_read(REG_POWER_MISC);
+	val &= ~PWGT2SPIEN;
+	pmic_reg_write(REG_POWER_MISC, val);
+
+	/* Externally powered */
+	val = pmic_reg_read(REG_CHARGE);
+	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+	pmic_reg_write(REG_CHARGE, val);
+
+	/* power up the system first */
+	pmic_reg_write(REG_POWER_MISC, PWUP);
+
+	/* Set core voltage to 1.1V */
+	val = pmic_reg_read(REG_SW_0);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+	pmic_reg_write(REG_SW_0, val);
+
+	/* Setup VCC (SW2) to 1.25 */
+	val = pmic_reg_read(REG_SW_1);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+	pmic_reg_write(REG_SW_1, val);
+
+	/* Setup 1V2_DIG1 (SW3) to 1.25 */
+	val = pmic_reg_read(REG_SW_2);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+	pmic_reg_write(REG_SW_2, val);
+	udelay(50);
+
+	/* Raise the core frequency to 800MHz */
+	writel(0x0, &mxc_ccm->cacrr);
+
+	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
+	/* Setup the switcher mode for SW1 & SW2*/
+	val = pmic_reg_read(REG_SW_4);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	pmic_reg_write(REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	val = pmic_reg_read(REG_SW_5);
+	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+		(SWMODE_MASK << SWMODE4_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+	pmic_reg_write(REG_SW_5, val);
+
+	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+	val = pmic_reg_read(REG_SETTING_0);
+	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+	val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+	pmic_reg_write(REG_SETTING_0, val);
+
+	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+	val = pmic_reg_read(REG_SETTING_1);
+	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+	pmic_reg_write(REG_SETTING_1, val);
+
+	/* Configure VGEN3 and VCAM regulators to use external PNP */
+	val = VGEN3CONFIG | VCAMCONFIG;
+	pmic_reg_write(REG_MODE_1, val);
+	udelay(200);
+
+	reg = readl(GPIO2_BASE_ADDR + 0x0);
+	reg &= ~0x4000;  /* Lower reset line */
+	writel(reg, GPIO2_BASE_ADDR + 0x0);
+
+	reg = readl(GPIO2_BASE_ADDR + 0x4);
+	reg |= 0x4000;	/* configure GPIO lines as output */
+	writel(reg, GPIO2_BASE_ADDR + 0x4);
+
+	/* Reset the ethernet controller over GPIO */
+	writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
+
+	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+		VVIDEOEN | VAUDIOEN  | VSDEN;
+	pmic_reg_write(REG_MODE_1, val);
+
+	udelay(500);
+
+	reg = readl(GPIO2_BASE_ADDR + 0x0);
+	reg |= 0x4000;
+	writel(reg, GPIO2_BASE_ADDR + 0x0);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = readl(GPIO1_BASE_ADDR) & 0x01;
+	else
+		*cd = readl(GPIO1_BASE_ADDR) & 0x40;
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+			index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX51_PIN_SD1_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_CLK,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA0,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA1,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA2,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA3,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_request_iomux(MX51_PIN_GPIO1_0,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+				PAD_CTL_HYS_ENABLE);
+			mxc_request_iomux(MX51_PIN_GPIO1_1,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+				PAD_CTL_HYS_ENABLE);
+			break;
+		case 1:
+			mxc_request_iomux(MX51_PIN_SD2_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD2_CLK,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD2_DATA0,
+				IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX51_PIN_SD2_DATA1,
+				IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX51_PIN_SD2_DATA2,
+				IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX51_PIN_SD2_DATA3,
+				IOMUX_CONFIG_ALT0);
+			mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_request_iomux(MX51_PIN_SD2_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_GPIO1_6,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
+				PAD_CTL_HYS_ENABLE);
+			mxc_request_iomux(MX51_PIN_GPIO1_5,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
+				PAD_CTL_HYS_ENABLE);
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	system_rev = get_cpu_rev();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_MXC_SPI
+	setup_iomux_spi();
+	power_init();
+#endif
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: MX51EVK ");
+
+	switch (system_rev & 0xff) {
+	case CHIP_REV_3_0:
+		puts("3.0 [");
+		break;
+	case CHIP_REV_2_5:
+		puts("2.5 [");
+		break;
+	case CHIP_REV_2_0:
+		puts("2.0 [");
+		break;
+	case CHIP_REV_1_1:
+		puts("1.1 [");
+		break;
+	case CHIP_REV_1_0:
+	default:
+		puts("1.0 [");
+		break;
+	}
+
+	switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		puts("POR");
+		break;
+	case 0x0009:
+		puts("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		puts("WDOG");
+		break;
+	default:
+		puts("unknown");
+	}
+	puts("]\n");
+	return 0;
+}
diff --git a/u-boot/board/freescale/mx53evk/Makefile b/u-boot/board/freescale/mx53evk/Makefile
new file mode 100644
index 0000000..6b820f4
--- /dev/null
+++ b/u-boot/board/freescale/mx53evk/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx53evk.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/mx53evk/config.mk b/u-boot/board/freescale/mx53evk/config.mk
new file mode 100644
index 0000000..0e60454
--- /dev/null
+++ b/u-boot/board/freescale/mx53evk/config.mk
@@ -0,0 +1,24 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
diff --git a/u-boot/board/freescale/mx53evk/imximage.cfg b/u-boot/board/freescale/mx53evk/imximage.cfg
new file mode 100644
index 0000000..dd7528c
--- /dev/null
+++ b/u-boot/board/freescale/mx53evk/imximage.cfg
@@ -0,0 +1,112 @@
+#
+# (C Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM	sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x53fa8554 0x00200000
+DATA 4 0x53fa8560 0x00200000
+DATA 4 0x53fa8594 0x00200000
+DATA 4 0x53fa8584 0x00200000
+DATA 4 0x53fa8558 0x00200040
+DATA 4 0x53fa8568 0x00200040
+DATA 4 0x53fa8590 0x00200040
+DATA 4 0x53fa857c 0x00200040
+DATA 4 0x53fa8564 0x00200040
+DATA 4 0x53fa8580 0x00200040
+DATA 4 0x53fa8570 0x00200000
+DATA 4 0x53fa8578 0x00200000
+DATA 4 0x53fa872c 0x00200000
+DATA 4 0x53fa8728 0x00200000
+DATA 4 0x53fa871c 0x00200000
+DATA 4 0x53fa8718 0x00200000
+DATA 4 0x53fa8574 0x00280000
+DATA 4 0x53fa8588 0x00280000
+DATA 4 0x53fa86f0 0x00280000
+DATA 4 0x53fa8720 0x00280000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa86f4 0x00000200
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8724 0x06000000
+DATA 4 0x63fd9088 0x34333936
+DATA 4 0x63fd9090 0x49434942
+DATA 4 0x63fd90F8 0x00000800
+DATA 4 0x63fd907c 0x01350138
+DATA 4 0x63fd9080 0x01380139
+DATA 4 0x63fd9018 0x00001710
+DATA 4 0x63fd9000 0xc4110000
+DATA 4 0x63fd900C 0x4d5122d2
+DATA 4 0x63fd9010 0x92d18a22
+DATA 4 0x63fd9014 0x00c70092
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f000e
+DATA 4 0x63fd9008 0x12272000
+DATA 4 0x63fd9004 0x00030012
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00008031
+DATA 4 0x63fd901c 0x0b5280b0
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x0a528030
+DATA 4 0x63fd901c 0x03c68031
+DATA 4 0x63fd901c 0x00448031
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00008039
+DATA 4 0x63fd901c 0x0b528138
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x0a528038
+DATA 4 0x63fd901c 0x03c68039
+DATA 4 0x63fd901c 0x00448039
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9058 0x00033335
+DATA 4 0x63fd901c 0x00000000
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x53fa8004 0x00194005
diff --git a/u-boot/board/freescale/mx53evk/mx53evk.c b/u-boot/board/freescale/mx53evk/mx53evk.c
new file mode 100644
index 0000000..e71701b
--- /dev/null
+++ b/u-boot/board/freescale/mx53evk/mx53evk.c
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mxc_gpio.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_i2c(unsigned int port_number)
+{
+	switch (port_number) {
+	case 0:
+		/* i2c1 SDA */
+		mxc_request_iomux(MX53_PIN_CSI0_D8,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		/* i2c1 SCL */
+		mxc_request_iomux(MX53_PIN_CSI0_D9,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		break;
+	case 1:
+		/* i2c2 SDA */
+		mxc_request_iomux(MX53_PIN_KEY_ROW3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+		/* i2c2 SCL */
+		mxc_request_iomux(MX53_PIN_KEY_COL3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		break;
+	default:
+		printf("Warning: Wrong I2C port number\n");
+		break;
+	}
+}
+
+void power_init(void)
+{
+	unsigned int val;
+
+	/* Set VDDA to 1.25V */
+	val = pmic_reg_read(REG_SW_2);
+	val &= ~SWX_OUT_MASK;
+	val |= SWX_OUT_1_25;
+	pmic_reg_write(REG_SW_2, val);
+
+	/*
+	 * Need increase VCC and VDDA to 1.3V
+	 * according to MX53 IC TO2 datasheet.
+	 */
+	if (is_soc_rev(CHIP_REV_2_0) == 0) {
+		/* Set VCC to 1.3V for TO2 */
+		val = pmic_reg_read(REG_SW_1);
+		val &= ~SWX_OUT_MASK;
+		val |= SWX_OUT_1_30;
+		pmic_reg_write(REG_SW_1, val);
+
+		/* Set VDDA to 1.3V for TO2 */
+		val = pmic_reg_read(REG_SW_2);
+		val &= ~SWX_OUT_MASK;
+		val |= SWX_OUT_1_30;
+		pmic_reg_write(REG_SW_2, val);
+	}
+}
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	 /* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+	{MMC_SDHC3_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = mxc_gpio_get(77); /*GPIO3_13*/
+	else
+		*cd = mxc_gpio_get(75); /*GPIO3_11*/
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA3,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_EIM_DA13,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			break;
+		case 1:
+			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_IORDY,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA8,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA9,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA10,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA11,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA0,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA1,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA2,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA3,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_EIM_DA11,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setup_i2c(1);
+	power_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	puts("Board: MX53EVK [");
+
+	cause = src_regs->srsr;
+	switch (cause) {
+	case 0x0001:
+		printf("POR");
+		break;
+	case 0x0009:
+		printf("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		printf("WDOG");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf("]\n");
+	return 0;
+}
diff --git a/u-boot/board/freescale/p1022ds/Makefile b/u-boot/board/freescale/p1022ds/Makefile
new file mode 100644
index 0000000..30d1740
--- /dev/null
+++ b/u-boot/board/freescale/p1022ds/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/p1022ds/ddr.c b/u-boot/board/freescale/p1022ds/ddr.c
new file mode 100644
index 0000000..7ecfb3e
--- /dev/null
+++ b/u-boot/board/freescale/p1022ds/ddr.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
+{
+	int ret;
+
+	/*
+	 * The P1022 has only one DDR controller, and the board has only one
+	 * DIMM slot.
+	 */
+	ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
+		       sizeof(ddr3_spd_eeprom_t));
+	if (ret) {
+		debug("DDR: failed to read SPD from address %u\n",
+		      SPD_EEPROM_ADDRESS1);
+		memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;		/* Range: 0-8 */
+	u32 cpo;		/* Range: 2-31 */
+	u32 write_data_delay;	/* Range: 0-6 */
+	u32 force_2T;
+} board_specific_parameters_t;
+
+static const board_specific_parameters_t bsp[] = {
+/*
+ *        lo|  hi|  num|  clk| cpo|wrdata|2T
+ *       mhz| mhz|ranks|adjst|    | delay|
+ */
+	{  0, 333,    1,    5,  31,     3, 0},
+	{334, 400,    1,    5,  31,     3, 0},
+	{401, 549,    1,    5,  31,     3, 0},
+	{550, 680,    1,    5,  31,     5, 0},
+	{681, 850,    1,    5,  31,     5, 0},
+	{  0, 333,    2,    5,  31,     3, 0},
+	{334, 400,    2,    5,  31,     3, 0},
+	{401, 549,    2,    5,  31,     3, 0},
+	{550, 680,    2,    5,  31,     5, 0},
+	{681, 850,    2,    5,  31,     5, 0},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	unsigned long ddr_freq;
+	unsigned int i;
+
+	/* set odt_rd_cfg and odt_wr_cfg. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = 0;
+		popts->cs_local_opts[i].odt_wr_cfg = 1;
+	}
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < ARRAY_SIZE(bsp); i++) {
+		if (ddr_freq >= bsp[i].datarate_mhz_low &&
+		    ddr_freq <= bsp[i].datarate_mhz_high &&
+		    pdimm->n_ranks == bsp[i].n_ranks) {
+			popts->clk_adjust = bsp[i].clk_adjust;
+			popts->cpo_override = bsp[i].cpo;
+			popts->write_data_delay = bsp[i].write_data_delay;
+			popts->twoT_en = bsp[i].force_2T;
+			break;
+		}
+	}
+
+	popts->half_strength_driver_enable = 1;
+
+	/* Per AN4039, enable ZQ calibration. */
+	popts->zq_en = 1;
+
+	/*
+	 * For wake-up on ARP, we need auto self refresh enabled
+	 */
+	popts->auto_self_refresh_en = 1;
+	popts->sr_it = 0xb;
+}
diff --git a/u-boot/board/freescale/p1022ds/diu.c b/u-boot/board/freescale/p1022ds/diu.c
new file mode 100644
index 0000000..8f5305c
--- /dev/null
+++ b/u-boot/board/freescale/p1022ds/diu.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include "../common/ngpixis.h"
+#include <fsl_diu_fb.h>
+
+/* The CTL register is called 'csr' in the ngpixis_t structure */
+#define PX_CTL_ALTACC		0x80
+
+#define PX_BRDCFG0_ELBC_SPI_MASK	0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC	0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL	0xc0
+#define PX_BRDCFG0_ELBC_DIU		0x02
+
+#define PX_BRDCFG1_DVIEN	0x80
+#define PX_BRDCFG1_DFPEN	0x40
+#define PX_BRDCFG1_BACKLIGHT	0x20
+
+#define PMUXCR_ELBCDIU_MASK	0xc0000000
+#define PMUXCR_ELBCDIU_NOR16	0x80000000
+#define PMUXCR_ELBCDIU_DIU	0x40000000
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register.  So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F		0x10000000
+#define AD_ALPHA_C_SHIFT	25
+#define AD_BLUE_C_SHIFT		23
+#define AD_GREEN_C_SHIFT	21
+#define AD_RED_C_SHIFT		19
+#define AD_PIXEL_S_SHIFT	16
+#define AD_COMP_3_SHIFT		12
+#define AD_COMP_2_SHIFT		8
+#define AD_COMP_1_SHIFT		4
+#define AD_COMP_0_SHIFT		0
+
+/*
+ * Variables used by the DIU/LBC switching code.  It's safe to makes these
+ * global, because the DIU requires DDR, so we'll only run this code after
+ * relocation.
+ */
+static u8 px_brdcfg0;
+static u32 pmuxcr;
+static void *lbc_lcs0_ba;
+static void *lbc_lcs1_ba;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	unsigned long speed_ccb, temp;
+	u32 pixval;
+
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000 / pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+	out_be32(&gur->clkdvdr, temp);			/* turn off clock */
+	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	char *monitor_port;
+	u32 pixel_format;
+	u8 temp;
+
+	/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
+	lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
+	lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
+
+	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+	temp = in_8(&pixis->brdcfg1);
+
+	monitor_port = getenv("monitor");
+	if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+		*xres = 1024;
+		*yres = 768;
+		/* Enable the DFP port, disable the DVI and the backlight */
+		temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
+		temp |= PX_BRDCFG1_DFPEN;
+	} else {	/* DVI */
+		*xres = 1280;
+		*yres = 1024;
+		/* Enable the DVI port, disable the DFP and the backlight */
+		temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+		temp |= PX_BRDCFG1_DVIEN;
+	}
+
+	out_8(&pixis->brdcfg1, temp);
+
+	/*
+	 * Enable PIXIS indirect access mode.  This is a hack that allows us to
+	 * access PIXIS registers even when the LBC pins have been muxed to the
+	 * DIU.
+	 */
+	setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+	/*
+	 * Route the LAD pins to the DIU.  This will disable access to the eLBC,
+	 * which means we won't be able to read/write any NOR flash addresses!
+	 */
+	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+	px_brdcfg0 = in_8(lbc_lcs1_ba);
+	out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
+
+	/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
+	clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
+	pmuxcr = in_be32(&gur->pmuxcr);
+
+	return fsl_diu_init(*xres, pixel_format, 0);
+}
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
+ *
+ * On the Freescale P1022, the DIU video signal and the LBC address/data lines
+ * share the same pins, which means that when the DIU is active (e.g. the
+ * console is on the DVI display), NOR flash cannot be accessed.  So we use the
+ * weak accessor feature of the CFI flash code to temporarily switch the pin
+ * mux from DIU to LBC whenever we want to read or write flash.  This has a
+ * significant performance penalty, but it's the only way to make it work.
+ *
+ * There are two muxes: one on the chip, and one on the board. The chip mux
+ * controls whether the pins are used for the DIU or the LBC, and it is
+ * set via PMUXCR.  The board mux controls whether those signals go to
+ * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
+ */
+static int set_mux_to_lbc(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Switch the muxes only if they're currently set to DIU mode */
+	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+	    PMUXCR_ELBCDIU_NOR16) {
+		/*
+		 * In DIU mode, the PIXIS can only be accessed indirectly
+		 * since we can't read/write the LBC directly.
+		 */
+
+		/* Set the board mux to LBC.  This will disable the display. */
+		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+		px_brdcfg0 = in_8(lbc_lcs1_ba);
+		out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
+			| PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
+
+		/* Disable indirect PIXIS mode */
+		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
+		clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
+
+		/* Set the chip mux to LBC mode, so that writes go to flash. */
+		out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
+			 PMUXCR_ELBCDIU_NOR16);
+		in_be32(&gur->pmuxcr);
+
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * set_mux_to_diu - re-enable the DIU muxing
+ *
+ * This function restores the chip and board muxing to point to the DIU.
+ */
+static void set_mux_to_diu(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Enable indirect PIXIS mode */
+	setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+	/* Set the board mux to DIU.  This will enable the display. */
+	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+	out_8(lbc_lcs1_ba, px_brdcfg0);
+	in_8(lbc_lcs1_ba);
+
+	/* Set the chip mux to DIU mode. */
+	out_be32(&gur->pmuxcr, pmuxcr);
+	in_be32(&gur->pmuxcr);
+}
+
+void flash_write8(u8 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	__raw_writeb(value, addr);
+	if (sw) {
+		/*
+		 * To ensure the post-write is completed to eLBC, software must
+		 * perform a dummy read from one valid address from eLBC space
+		 * before changing the eLBC_DIU from NOR mode to DIU mode.
+		 * set_mux_to_diu() includes a sync that will ensure the
+		 * __raw_readb() completes before it switches the mux.
+		 */
+		__raw_readb(addr);
+		set_mux_to_diu();
+	}
+}
+
+void flash_write16(u16 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	__raw_writew(value, addr);
+	if (sw) {
+		/*
+		 * To ensure the post-write is completed to eLBC, software must
+		 * perform a dummy read from one valid address from eLBC space
+		 * before changing the eLBC_DIU from NOR mode to DIU mode.
+		 * set_mux_to_diu() includes a sync that will ensure the
+		 * __raw_readb() completes before it switches the mux.
+		 */
+		__raw_readb(addr);
+		set_mux_to_diu();
+	}
+}
+
+void flash_write32(u32 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	__raw_writel(value, addr);
+	if (sw) {
+		/*
+		 * To ensure the post-write is completed to eLBC, software must
+		 * perform a dummy read from one valid address from eLBC space
+		 * before changing the eLBC_DIU from NOR mode to DIU mode.
+		 * set_mux_to_diu() includes a sync that will ensure the
+		 * __raw_readb() completes before it switches the mux.
+		 */
+		__raw_readb(addr);
+		set_mux_to_diu();
+	}
+}
+
+void flash_write64(u64 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+	uint32_t *p = addr;
+
+	/*
+	 * There is no __raw_writeq(), so do the write manually.  We don't trust
+	 * the compiler, so we use inline assembly.
+	 */
+	__asm__ __volatile__(
+		"stw%U0%X0 %2,%0;\n"
+		"stw%U1%X1 %3,%1;\n"
+		: "=m" (*p), "=m" (*(p + 1))
+		: "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
+
+	if (sw) {
+		/*
+		 * To ensure the post-write is completed to eLBC, software must
+		 * perform a dummy read from one valid address from eLBC space
+		 * before changing the eLBC_DIU from NOR mode to DIU mode.  We
+		 * read addr+4 because we just wrote to addr+4, so that's how we
+		 * maintain execution order.  set_mux_to_diu() includes a sync
+		 * that will ensure the __raw_readb() completes before it
+		 * switches the mux.
+		 */
+		__raw_readb(addr + 4);
+		set_mux_to_diu();
+	}
+}
+
+u8 flash_read8(void *addr)
+{
+	u8 ret;
+
+	int sw = set_mux_to_lbc();
+
+	ret = __raw_readb(addr);
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 ret;
+
+	int sw = set_mux_to_lbc();
+
+	ret = __raw_readw(addr);
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+u32 flash_read32(void *addr)
+{
+	u32 ret;
+
+	int sw = set_mux_to_lbc();
+
+	ret = __raw_readl(addr);
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+u64 flash_read64(void *addr)
+{
+	u64 ret;
+
+	int sw = set_mux_to_lbc();
+
+	/* There is no __raw_readq(), so do the read manually */
+	ret = *(volatile u64 *)addr;
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+#endif
diff --git a/u-boot/board/freescale/p1022ds/law.c b/u-boot/board/freescale/p1022ds/law.c
new file mode 100644
index 0000000..b23b8f9
--- /dev/null
+++ b/u-boot/board/freescale/p1022ds/law.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/p1022ds/p1022ds.c b/u-boot/board/freescale/p1022ds/p1022ds.c
new file mode 100644
index 0000000..0ea0bdf
--- /dev/null
+++ b/u-boot/board/freescale/p1022ds/p1022ds.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <asm/mp.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <hwconfig.h>
+
+#include "../common/ngpixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, 0x1000);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+	/* Set the pin muxing to enable ETSEC2. */
+	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	u8 sw;
+
+	puts("Board: P1022DS ");
+
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+
+	switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
+	case 0:
+		printf ("vBank: %u\n", ((sw & 0x30) >> 4));
+		break;
+	case 1:
+		printf ("NAND\n");
+		break;
+	case 2:
+	case 3:
+		puts ("Promjet\n");
+		break;
+	}
+
+	return 0;
+}
+
+#define CONFIG_TFP410_I2C_ADDR	0x38
+
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK	0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK	0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI	0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12		0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11		0x01
+
+int misc_init_r(void)
+{
+	u8 temp;
+	const char *audclk;
+	size_t arglen;
+
+	/* For DVI, enable the TFP410 Encoder. */
+
+	temp = 0xBF;
+	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
+		return -1;
+	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
+		return -1;
+	debug("DVI Encoder Read: 0x%02x\n", temp);
+
+	temp = 0x10;
+	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
+		return -1;
+	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
+		return -1;
+	debug("DVI Encoder Read: 0x%02x\n",temp);
+
+	/*
+	 * Enable the reference clock for the WM8776 codec, and route the MUX
+	 * pins for SSI. The default is the 12.288 MHz clock
+	 */
+
+	temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+		CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+	temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+	audclk = hwconfig_arg("audclk", &arglen);
+	/* Check the first two chars only */
+	if (audclk && (strncmp(audclk, "11", 2) == 0))
+		temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+	else
+		temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+	out_8(&pixis->brdcfg1, temp);
+
+	return 0;
+}
+
+/*
+ * A list of PCI and SATA slots
+ */
+enum slot_id {
+	SLOT_PCIE1 = 1,
+	SLOT_PCIE2,
+	SLOT_PCIE3,
+	SLOT_PCIE4,
+	SLOT_PCIE5,
+	SLOT_SATA1,
+	SLOT_SATA2
+};
+
+/*
+ * This array maps the slot identifiers to their names on the P1022DS board.
+ */
+static const char *slot_names[] = {
+	[SLOT_PCIE1] = "Slot 1",
+	[SLOT_PCIE2] = "Slot 2",
+	[SLOT_PCIE3] = "Slot 3",
+	[SLOT_PCIE4] = "Slot 4",
+	[SLOT_PCIE5] = "Mini-PCIe",
+	[SLOT_SATA1] = "SATA 1",
+	[SLOT_SATA2] = "SATA 2",
+};
+
+/*
+ * This array maps a given SERDES configuration and SERDES device to the PCI or
+ * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
+ */
+static u8 serdes_dev_slot[][SATA2 + 1] = {
+	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
+	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
+		   [PCIE2] = SLOT_PCIE5 },
+	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+		   [PCIE2] = SLOT_PCIE3,
+		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+		   [PCIE2] = SLOT_PCIE3 },
+	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
+		   [PCIE2] = SLOT_PCIE3,
+		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x1c] = { [PCIE1] = SLOT_PCIE1,
+		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
+	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
+};
+
+
+/*
+ * Returns the name of the slot to which the PCIe or SATA controller is
+ * connected
+ */
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
+	const char *name = slot_names[slot];
+
+	if (name)
+		return name;
+	else
+		return "Nothing";
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	return 0;
+}
+
+/*
+ * Initialize on-board and/or PCI Ethernet devices
+ *
+ * Returns:
+ *      <0, error
+ *       0, no ethernet devices found
+ *      >0, number of ethernet devices initialized
+ */
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[2];
+	unsigned int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+
+	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+	const char *audclk;
+	size_t arglen;
+	u32 freq;
+
+	audclk = hwconfig_arg("audclk", &arglen);
+	if (audclk && (strncmp(audclk, "11", 2) == 0))
+		freq = 11289600;
+	else
+		freq = 12288000;
+
+	do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+
+	/* Update the WM8776 node's clock frequency property */
+	ft_codec_setup(blob, "wlf,wm8776");
+}
+#endif
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/freescale/p1022ds/tlb.c b/u-boot/board/freescale/p1022ds/tlb.c
new file mode 100644
index 0000000..e620112
--- /dev/null
+++ b/u-boot/board/freescale/p1022ds/tlb.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_4K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/p1_p2_rdb/Makefile b/u-boot/board/freescale/p1_p2_rdb/Makefile
new file mode 100644
index 0000000..ba7e5df
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-$(CONFIG_PCI)  += pci.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/p1_p2_rdb/config.mk b/u-boot/board/freescale/p1_p2_rdb/config.mk
new file mode 100644
index 0000000..0769804
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/config.mk
@@ -0,0 +1,31 @@
+#
+# Copyright 2009, 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# p1_p2rdb board
+#
+
+ifndef NAND_SPL
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
diff --git a/u-boot/board/freescale/p1_p2_rdb/ddr.c b/u-boot/board/freescale/p1_p2_rdb/ddr.c
new file mode 100644
index 0000000..e54fde2
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/ddr.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num);
+
+#define DATARATE_400MHZ 400000000
+#define DATARATE_533MHZ 533333333
+#define DATARATE_667MHZ 666666666
+#define DATARATE_800MHZ 800000000
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0x43000000	/* Type = DDR2*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000000
+#define CONFIG_SYS_DDR_TIMING_5		0x00000000
+
+#define CONFIG_SYS_DDR_TIMING_3_400	0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_400	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_400	0x39355322
+#define CONFIG_SYS_DDR_TIMING_2_400	0x1f9048ca
+#define CONFIG_SYS_DDR_CLK_CTRL_400	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_400	0x00480432
+#define CONFIG_SYS_DDR_MODE_2_400	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_400	0x06180100
+
+#define CONFIG_SYS_DDR_TIMING_3_533	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_533	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_533	0x4c47c432
+#define CONFIG_SYS_DDR_TIMING_2_533	0x0f9848ce
+#define CONFIG_SYS_DDR_CLK_CTRL_533	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_533	0x00040642
+#define CONFIG_SYS_DDR_MODE_2_533	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_533	0x08200100
+
+#define CONFIG_SYS_DDR_TIMING_3_667	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_667	0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_667	0x5f599543
+#define CONFIG_SYS_DDR_TIMING_2_667	0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_667	0x03000000
+#define CONFIG_SYS_DDR_MODE_1_667	0x00040852
+#define CONFIG_SYS_DDR_MODE_2_667	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667	0x0a280100
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00040000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b6543
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00040852
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0a280100
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	size_t ddr_size;
+	struct cpu_type *cpu;
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, sysinfo.freqDDRBus));
+
+	if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
+	else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
+	else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
+	else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
+	else
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+					strmhz(buf, sysinfo.freqDDRBus));
+
+	cpu = gd->cpu;
+	/* P1020 and it's derivatives support max 32bit DDR width */
+	if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
+		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
+		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+	}
+	else
+		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+	set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
+	return ddr_size;
+}
diff --git a/u-boot/board/freescale/p1_p2_rdb/law.c b/u-boot/board/freescale/p1_p2_rdb/law.c
new file mode 100644
index 0000000..4c80fa6
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/law.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/u-boot/board/freescale/p1_p2_rdb/p1_p2_rdb.c
new file mode 100644
index 0000000..0780942
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VSC7385_RST_SET		0x00080000
+#define SLIC_RST_SET		0x00040000
+#define SGMII_PHY_RST_SET	0x00020000
+#define PCIE_RST_SET		0x00010000
+#define RGMII_PHY_RST_SET	0x02000000
+
+#define USB_RST_CLR		0x04000000
+
+#define GPIO_DIR		0x060f0000
+
+#define BOARD_PERI_RST_SET	VSC7385_RST_SET | SLIC_RST_SET | \
+				SGMII_PHY_RST_SET | PCIE_RST_SET | \
+				RGMII_PHY_RST_SET
+
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+#define BOARDREV_B	0x10100000
+#define BOARDREV_C	0x00100000
+#define BOARDREV_D	0x00000000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_50	50000000
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val_gpdat, sysclk_gpio, board_rev_gpio;
+
+	val_gpdat = in_be32(&pgpio->gpdat);
+	sysclk_gpio = val_gpdat & SYSCLK_MASK;
+	board_rev_gpio = val_gpdat & BOARDREV_MASK;
+	if (board_rev_gpio == BOARDREV_C) {
+		if(sysclk_gpio == 0)
+			return SYSCLK_66;
+		else
+			return SYSCLK_100;
+	} else if (board_rev_gpio == BOARDREV_B) {
+		if(sysclk_gpio == 0)
+			return SYSCLK_66;
+		else
+			return SYSCLK_50;
+	} else if (board_rev_gpio == BOARDREV_D) {
+		if(sysclk_gpio == 0)
+			return SYSCLK_66;
+		else
+			return SYSCLK_100;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD |
+			 MPC85xx_PMUXCR_SDHC_WP));
+	return 0;
+}
+#endif
+
+int checkboard (void)
+{
+	u32 val_gpdat, board_rev_gpio;
+	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	char board_rev = 0;
+	struct cpu_type *cpu;
+
+	val_gpdat = in_be32(&pgpio->gpdat);
+	board_rev_gpio = val_gpdat & BOARDREV_MASK;
+	if (board_rev_gpio == BOARDREV_C)
+		board_rev = 'C';
+	else if (board_rev_gpio == BOARDREV_B)
+		board_rev = 'B';
+	else if (board_rev_gpio == BOARDREV_D)
+		board_rev = 'D';
+	else
+		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
+
+	cpu = gd->cpu;
+	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
+	setbits_be32(&pgpio->gpdir, GPIO_DIR);
+
+/*
+ * Bringing the following peripherals out of reset via GPIOs
+ * 0 = reset and 1 = out of reset
+ * GPIO12 - Reset to Ethernet Switch
+ * GPIO13 - Reset to SLIC/SLAC devices
+ * GPIO14 - Reset to SGMII_PHY_N
+ * GPIO15 - Reset to PCIe slots
+ * GPIO6  - Reset to RGMII PHY
+ * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
+ */
+	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_16M, 1);
+	rtc_reset();
+	return 0;
+}
+
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+	char *tmp;
+	unsigned int vscfw_addr;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+#ifdef CONFIG_VSC7385_ENET
+/* If a VSC7385 microcode image is present, then upload it. */
+	if ((tmp = getenv ("vscfw_addr")) != NULL) {
+		vscfw_addr = simple_strtoul (tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *) vscfw_addr,
+					CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else
+		puts("No address specified for VSC7385 microcode.\n");
+#endif
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_pci_board_setup(void *blob);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+	ft_pci_board_setup(blob);
+#endif /* #if defined(CONFIG_PCI) */
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/freescale/p1_p2_rdb/pci.c b/u-boot/board/freescale/p1_p2_rdb/pci.c
new file mode 100644
index 0000000..bd1a91e
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/pci.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void ft_pci_board_setup(void *blob)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/u-boot/board/freescale/p1_p2_rdb/tlb.c b/u-boot/board/freescale/p1_p2_rdb/tlb.c
new file mode 100644
index 0000000..b85c268
--- /dev/null
+++ b/u-boot/board/freescale/p1_p2_rdb/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_16M, 1),
+
+#if defined(CONFIG_PCI)
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256K, 1),
+
+#endif /* #if defined(CONFIG_PCI) */
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 8, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/freescale/p2020ds/Makefile b/u-boot/board/freescale/p2020ds/Makefile
new file mode 100644
index 0000000..3306e44
--- /dev/null
+++ b/u-boot/board/freescale/p2020ds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/freescale/p2020ds/ddr.c b/u-boot/board/freescale/p2020ds/ddr.c
new file mode 100644
index 0000000..9a1b075
--- /dev/null
+++ b/u-boot/board/freescale/p2020ds/ddr.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+	/* 	memory controller 0 			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+#ifdef CONFIG_FSL_DDR2
+		{  0, 333,    2,    4,   0x1f,    2,  0},
+		{334, 400,    2,    4,   0x1f,    2,  0},
+		{401, 549,    2,    4,   0x1f,    2,  0},
+		{550, 680,    2,    4,   0x1f,    3,  0},
+		{681, 850,    2,    4,   0x1f,    4,  0},
+		{  0, 333,    1,    4,   0x1f,    2,  0},
+		{334, 400,    1,    4,   0x1f,    2,  0},
+		{401, 549,    1,    4,   0x1f,    2,  0},
+		{550, 680,    1,    4,   0x1f,    3,  0},
+		{681, 850,    1,    4,   0x1f,    4,  0}
+#else
+		{  0, 850,    2,    6,   0x1f,    4,  0},
+		{  0, 850,    1,    4,   0x1f,    4,  0}
+#endif
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 1;
+	}
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high &&
+		    pdimm->n_ranks == pbsp->n_ranks) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->write_data_delay = pbsp->write_data_delay;
+			popts->twoT_en = pbsp->force_2T;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	popts->wrlvl_en = 1;
+	/* Write leveling override */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xa;
+	popts->wrlvl_start = 0x8;
+	/* Rtt and Rtt_WR override */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = DDR3_RTT_120_OHM;
+	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+}
diff --git a/u-boot/board/freescale/p2020ds/law.c b/u-boot/board/freescale/p2020ds/law.c
new file mode 100644
index 0000000..91642a9
--- /dev/null
+++ b/u-boot/board/freescale/p2020ds/law.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/freescale/p2020ds/p2020ds.c b/u-boot/board/freescale/p2020ds/p2020ds.c
new file mode 100644
index 0000000..8546aa9
--- /dev/null
+++ b/u-boot/board/freescale/p2020ds/p2020ds.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <asm/mp.h>
+#include <netdev.h>
+
+#include "../common/ngpixis.h"
+#include "../common/sgmii_riser.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	u8 sw;
+
+	puts("Board: P2020DS ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+	sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		/* The lower two bits are the actual vbank number */
+		printf("vBank: %d\n", sw & 3);
+	else
+		puts("Promjet\n");
+
+	return 0;
+}
+
+#if !defined(CONFIG_DDR_SPD)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	uint d_init;
+
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+	ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
+	ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
+	ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
+	ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
+	ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
+
+	if (!strcmp("performance", getenv("perf_mode"))) {
+		/* Performance Mode Values */
+
+		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
+		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
+		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
+
+		asm("sync;isync");
+
+		udelay(500);
+
+		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
+	} else {
+		/* Stable Mode Values */
+
+		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+		/* ECC will be assumed in stable mode */
+		ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+		ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+		ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+
+		asm("sync;isync");
+
+		udelay(500);
+
+		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	}
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+		udelay(1000);
+	debug("DDR: memory initialized\n\n");
+	asm("sync; isync");
+	udelay(500);
+#endif
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+			 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
+			 LAW_TRGT_IF_DDR) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		puts("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+}
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/freescale/p2020ds/tlb.c b/u-boot/board/freescale/p2020ds/tlb.c
new file mode 100644
index 0000000..824b3b2
--- /dev/null
+++ b/u-boot/board/freescale/p2020ds/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_4K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/funkwerk/vovpn-gw/Makefile b/u-boot/board/funkwerk/vovpn-gw/Makefile
new file mode 100644
index 0000000..91d4d35
--- /dev/null
+++ b/u-boot/board/funkwerk/vovpn-gw/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o m88e6060.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/funkwerk/vovpn-gw/flash.c b/u-boot/board/funkwerk/vovpn-gw/flash.c
new file mode 100644
index 0000000..fd3b16e
--- /dev/null
+++ b/u-boot/board/funkwerk/vovpn-gw/flash.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
+ * and 28F128J3A flashs working in 8 Bit mode.
+ *
+ * Most of this code is taken from existing u-boot source code.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t				flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xd0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_SUSPEND_ERASE		0xb0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_WRITE_BUFF		0xe8
+#define FLASH_CMD_PROG_RESUME		0xd0
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xd0
+#define FLASH_STATUS_DONE		0x80
+
+#define FLASH_WRITE_BUFFER_SIZE		32
+
+#ifdef CONFIG_SYS_FLASH_16BIT
+#define FLASH_WORD_SIZE			unsigned short
+#define FLASH_ID_MASK			0xffff
+#define FLASH_CMD_ADDR_SHIFT		0
+#else
+#define FLASH_WORD_SIZE			unsigned char
+#define FLASH_ID_MASK			0xff
+/* A0 is not used in either 8x or 16x for READ ID */
+#define FLASH_CMD_ADDR_SHIFT		1
+#endif
+
+
+static unsigned long
+flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	volatile FLASH_WORD_SIZE *p;
+	FLASH_WORD_SIZE value;
+	int i;
+
+	addr[0] = FLASH_CMD_READ_ID;
+
+	/* manufactor */
+	value = addr[0 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+
+	}
+
+	/* device */
+	value = addr[1 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+	}
+
+	/* setup sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
+	}
+
+	/* check protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
+	}
+
+	/* reset bank */
+	*addr = FLASH_CMD_RESET;
+	return (info->size);
+}
+
+unsigned long
+flash_init(void)
+{
+	unsigned long	size;
+	int		i;
+
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+	size = flash_get((volatile FLASH_WORD_SIZE *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH Size=0x%08lx\n", size);
+		return (0);
+	}
+
+	/* always protect 1 sector containing the HRCW */
+	flash_protect(FLAG_PROTECT_SET,
+		      flash_info[0].start[0],
+		      flash_info[0].start[1] - 1,
+		      &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_FLASH,
+		      CONFIG_SYS_MONITOR_FLASH+CONFIG_SYS_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320JA3 (32 Mbit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640JA3 (64 Mbit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128JA3 (128 Mbit)\n");
+				break;
+	default:		printf ("Unknown Chip Type");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long start, now, last;
+	int flag, prot, sect;
+	volatile FLASH_WORD_SIZE *addr;
+	FLASH_WORD_SIZE status;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return (1);
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Cannot erase unknown flash - aborted\n");
+		return (1);
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect]) {
+			continue;
+		}
+
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+#ifdef DEBUG
+		printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+		*addr = FLASH_CMD_CLEAR_STATUS;
+		*addr = FLASH_CMD_BLOCK_ERASE;
+		*addr = FLASH_CMD_ERASE_CONFIRM;
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+			if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf("Flash erase timeout at address %lx\n", info->start[sect]);
+				*addr = FLASH_CMD_SUSPEND_ERASE;
+				*addr = FLASH_CMD_RESET;
+				return (1);
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		*addr = FLASH_CMD_RESET;
+	}
+	printf (" done\n");
+	return (0);
+}
+
+static int
+write_buff2( volatile FLASH_WORD_SIZE *dst,
+	     volatile FLASH_WORD_SIZE *src,
+	     unsigned long cnt )
+{
+	unsigned long start;
+	FLASH_WORD_SIZE status;
+	int flag, i;
+
+	start = get_timer (0);
+	while (1) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		dst[0] = FLASH_CMD_WRITE_BUFF;
+		if ((status = *dst) & FLASH_STATUS_DONE) {
+			break;
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (-1);
+		}
+	}
+	dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
+	for (i=0; i<cnt; i++) {
+		dst[i] = src[i];
+	}
+	dst[0] = FLASH_CMD_PROG_RESUME;
+
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return( 0 );
+}
+
+static int
+poll_status( volatile FLASH_WORD_SIZE *addr )
+{
+	unsigned long start;
+
+	start = get_timer (0);
+	/* wait for error or finish */
+	while (1) {
+		if (*addr == FLASH_STATUS_DONE) {
+			if (*addr == FLASH_STATUS_DONE) {
+				break;
+			}
+		}
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = FLASH_CMD_RESET;
+			return (-1);
+		}
+	}
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * write_buff return values:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
+{
+	volatile FLASH_WORD_SIZE *addr, *dst;
+	unsigned long bcnt;
+	int flag, i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return (4);
+	}
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+	dst = (volatile FLASH_WORD_SIZE *) udst;
+
+#ifdef CONFIG_SYS_FLASH_16BIT
+#error NYI
+#else
+	while (cnt > 0) {
+		/* Check if buffer write is possible */
+		if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
+			bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
+			/* Check if Flash is (sufficiently) erased */
+			for (i=0; i<bcnt; i++) {
+				if ((dst[i] & src[i]) != src[i]) {
+					return (2);
+				}
+			}
+			if (write_buff2( dst,src,bcnt ) != 0) {
+				addr[0] = FLASH_CMD_READ_STATUS;
+			}
+			if (poll_status( dst ) != 0) {
+				return (1);
+			}
+			cnt -= bcnt;
+			dst += bcnt;
+			src += bcnt;
+			continue;
+		}
+
+		/* Check if Flash is (sufficiently) erased */
+		if ((*dst & *src) != *src) {
+			return (2);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		addr[0] = FLASH_CMD_ERASE_CONFIRM;
+		addr[0] = FLASH_CMD_WRITE;
+		*dst++ = *src++;
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (poll_status( dst ) != 0) {
+			return (1);
+		}
+		cnt --;
+	}
+#endif
+	return (0);
+}
+
+int
+flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	volatile FLASH_WORD_SIZE *addr;
+	unsigned long start;
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
diff --git a/u-boot/board/funkwerk/vovpn-gw/m88e6060.c b/u-boot/board/funkwerk/vovpn-gw/m88e6060.c
new file mode 100644
index 0000000..58b5b6e
--- /dev/null
+++ b/u-boot/board/funkwerk/vovpn-gw/m88e6060.c
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+#if defined(CONFIG_CMD_NET)
+static int		prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
+static int		phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
+
+static m88x_regCfg_t	prtCfg0[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001e },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg1[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001d },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg2[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001b },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg3[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x0017 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg4[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x000f },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*prtCfg[M88X_PRT_CNT] = {
+	prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
+};
+
+static m88x_regCfg_t	phyCfgX[] = {
+	{  4, 0xfa1f, 0x01e0 },
+	{  0, 0x213f, 0x1200 },
+	{ 24, 0x81ff, 0x1200 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*phyCfg[M88X_PHY_CNT] = {
+	phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
+};
+
+#if 0
+static void
+m88e6060_dump( int devAddr )
+{
+	int		i, j;
+	unsigned short	val[6];
+
+	printf( "M88E6060 Register Dump\n" );
+	printf( "====================================\n" );
+	printf( "PortNo    0    1    2    3    4    5\n" );
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
+	printf( "STAT   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
+	printf( "ID     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
+	printf( "CNTL   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
+	printf( "VLAN   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
+	printf( "PAV    %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
+	printf( "RX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
+	printf( "TX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	printf( "------------------------------------\n" );
+	printf( "PhyNo     0    1    2    3    4\n" );
+	for (i=0; i<9; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+	for (i=0x10; i<0x1d; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+}
+#endif
+
+int
+m88e6060_initialize( int devAddr )
+{
+	static char	*_f = "m88e6060_initialize:";
+	m88x_regCfg_t	*p;
+	int		err;
+	int		i;
+	unsigned short	val;
+
+	/*** reset all phys into powerdown ************************************/
+	for (i=0, err=0; i<M88X_PHY_CNT; i++) {
+		err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+		/* keep SpeedLSB, Duplex */
+		val &= 0x2100;
+		/* set SWReset, AnegEn, PwrDwn, RestartAneg */
+		val |= 0x9a00;
+		err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] reset phys\n",_f );
+		return( -1 );
+	}
+
+	/*** disable all ports ************************************************/
+	for (i=0, err=0; i<M88X_PRT_CNT; i++) {
+		err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+		val &= 0xfffc;
+		err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] disable ports\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize switch ************************************************/
+	/* set switch mac addr */
+#define ea eth_get_dev()->enetaddr
+	val = (ea[4] <<  8) | ea[5];
+	err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
+	val = (ea[2] <<  8) | ea[3];
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
+	val = (ea[0] <<  8) | ea[1];
+#undef ea
+	val &= 0xfeff;		/* clear DiffAddr */
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
+	if (err) {
+		printf( "%s [ERR] switch mac address register\n",_f );
+		return( -1 );
+	}
+
+	/* !DiscardExcessive, MaxFrameSize, CtrMode */
+	err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
+	val &= 0xd870;
+	val |= 0x0500;
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] switch global control register\n",_f );
+		return( -1 );
+	}
+
+	/* LernDis off, ATUSize 1024, AgeTime 5min */
+	err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
+	val &= 0x000f;
+	val |= 0x2130;
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] atu control register\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize ports *************************************************/
+	for (i=0; i<M88X_PRT_CNT; i++) {
+		if ((p = prtCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+
+	/*** initialize phys **************************************************/
+	for (i=0; i<M88X_PHY_CNT; i++) {
+		if ((p = phyCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+	udelay(100000);
+	return( 0 );
+}
+#endif
diff --git a/u-boot/board/funkwerk/vovpn-gw/m88e6060.h b/u-boot/board/funkwerk/vovpn-gw/m88e6060.h
new file mode 100644
index 0000000..15d4583
--- /dev/null
+++ b/u-boot/board/funkwerk/vovpn-gw/m88e6060.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INC_m88e6060_h_
+#define _INC_m88e6060_h_
+
+/* ************************************************************************** */
+/* *** DEFINES ************************************************************** */
+
+/* switch hw */
+#define M88X_PRT_CNT			6
+#define M88X_PHY_CNT			5
+
+/* phy register offsets */
+#define M88X_PHY_CNTL			0x00
+#define M88X_PHY_STAT			0x00
+#define M88X_PHY_ID0			0x02
+#define M88X_PHY_ID1			0x03
+#define M88X_PHY_ANEG_ADV		0x04
+#define M88X_PHY_LPA			0x05
+#define M88X_PHY_ANEG_EXP		0x06
+#define M88X_PHY_NPT			0x07
+#define M88X_PHY_LPNP			0x08
+
+/* port register offsets */
+#define M88X_PRT_STAT			0x00
+#define M88X_PRT_ID			0x03
+#define M88X_PRT_CNTL			0x04
+#define M88X_PRT_VLAN			0x06
+#define M88X_PRT_PAV			0x0b
+#define M88X_PRT_RX			0x10
+#define M88X_PRT_TX			0x11
+
+/* global/atu register offsets */
+#define M88X_GLB_STAT			0x00
+#define M88X_GLB_MAC01			0x01
+#define M88X_GLB_MAC23			0x02
+#define M88X_GLB_MAC45			0x03
+#define M88X_GLB_CNTL			0x04
+#define M88X_ATU_CNTL			0x0a
+#define M88X_ATU_OP			0x0b
+
+/* id0 register - 0x02 */
+#define M88X_PHY_ID0_VALUE		0x0141
+
+/* id1 register - 0x03 */
+#define M88X_PHY_ID1_VALUE		0x0c80		/* without revision ! */
+
+
+/* misc */
+#define M88E6060_ID		((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
+
+/* ************************************************************************** */
+/* *** TYPEDEFS ************************************************************* */
+
+typedef struct {
+	int		reg;
+	unsigned short	msk;
+	unsigned short	val;
+} m88x_regCfg_t;
+
+/* ************************************************************************** */
+/* *** PROTOTYPES *********************************************************** */
+
+extern int		m88e6060_initialize( int );
+
+#endif	/* _INC_m88e6060_h_ */
diff --git a/u-boot/board/funkwerk/vovpn-gw/vovpn-gw.c b/u-boot/board/funkwerk/vovpn-gw/vovpn-gw.c
new file mode 100644
index 0000000..a4bfbc9
--- /dev/null
+++ b/u-boot/board/funkwerk/vovpn-gw/vovpn-gw.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A configuration */
+    {	/*	     conf ppar psor pdir podr pdat */
+	/* PA31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1252           */
+	/* PA30 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    BP_RES           */
+	/* PA29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1253           */
+	/* PA28 */ { 1,   1,   1,   1,   0,   0 }, /* FCC1   RMII TX_EN       */
+	/* PA27 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII CRS_DV      */
+	/* PA26 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII RX_ERR      */
+	/* PA25 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA24 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA23 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA22 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA21 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA20 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    LED STATUS       */
+	/* PA19 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[1]      */
+	/* PA18 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[0]      */
+	/* PA17 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[0]      */
+	/* PA16 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[1]      */
+	/* PA15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1255           */
+	/* PA14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP????           */
+	/* PA13 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    EN_BCTL1 XXX jse */
+	/* PA12 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    SWITCH RESET     */
+	/* PA11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL1 RESET    */
+	/* PA10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL2 RESET    */
+	/* PA9  */ { 1,   1,   0,   1,   0,   0 }, /* SMC2   TXD              */
+	/* PA8  */ { 1,   1,   0,   0,   0,   0 }, /* SMC2   RXD              */
+	/* PA7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exit       */
+    },
+
+    /* Port B configuration */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PB31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1257           */
+	/* PB30 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII CRS_DV      */
+	/* PB29 */ { 1,   1,   1,   1,   0,   0 }, /* FCC2   RMII TX_EN       */
+	/* PB28 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RX_ERR      */
+	/* PB27 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1TXD XXX val=0  */
+	/* PB26 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1RXD XXX val,dr */
+	/* PB25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1259           */
+	/* PB24 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_B2 L1RSYNC          */
+	/* PB23 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[1]      */
+	/* PB22 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[0]      */
+	/* PB21 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[0]      */
+	/* PB20 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[1]      */
+	/* PB19 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    PHY MDC          */
+	/* PB18 */ { 1,   0,   0,   0,   0,   0 }, /* GPIO   PHY MDIO         */
+	/* PB17 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB16 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB15 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB14 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    },
+
+    /* Port C */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PC31 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC30 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1183           */
+	/* PC28 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1184           */
+	/* PC27 */ { 1,   1,   0,   0,   0,   0 }, /* CLK5   TDM_A1 RX        */
+	/* PC26 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1185           */
+	/* PC25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1178           */
+	/* PC24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1186           */
+	/* PC23 */ { 1,   1,   0,   0,   0,   0 }, /* CLK9   TDM_B2 RX        */
+	/* PC22 */ { 1,   1,   0,   0,   0,   0 }, /* CLK10  FCC1 RMII REFCLK */
+	/* PC21 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1187           */
+	/* PC20 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1182           */
+	/* PC19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1188           */
+	/* PC18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    HW RESET         */
+	/* PC17 */ { 1,   1,   0,   1,   0,   0 }, /* BRG8   SWITCH CLKIN     */
+	/* PC16 */ { 1,   1,   0,   0,   0,   0 }, /* CLK16  FCC2 RMII REFCLK */
+	/* PC15 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_3      */
+	/* PC14 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_2      */
+	/* PC13 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_1      */
+	/* PC12 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_0      */
+	/* PC11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1176           */
+	/* PC10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1177           */
+	/* PC9  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_3      */
+	/* PC8  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_2      */
+	/* PC7  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_1      */
+	/* PC6  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_0      */
+	/* PC5  */ { 1,   1,   0,   1,   0,   0 }, /* SMC1   TXD              */
+	/* PC4  */ { 1,   1,   0,   0,   0,   0 }, /* SMC1   RXD              */
+	/* PC3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC1  */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1192           */
+	/* PC0  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    RACK             */
+    },
+
+    /* Port D */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PD31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1193           */
+	/* PD30 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1194           */
+	/* PD29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1195           */
+	/* PD28 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD27 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD26 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1179           */
+	/* PD24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1180           */
+	/* PD23 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1181           */
+	/* PD22 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1TXD            */
+	/* PD21 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1RXD            */
+	/* PD20 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_A2 L1RSYNC          */
+	/* PD19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1196           */
+	/* PD18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1197           */
+	/* PD17 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1198           */
+	/* PD16 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1199           */
+	/* PD15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1250           */
+	/* PD14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1251           */
+	/* PD13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD7  */ { 0,   0,   0,   1,   0,   0 }, /* GPO    FL_BYTE          */
+	/* PD6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    }
+};
+
+void reset_phy (void)
+{
+	volatile ioport_t *iop;
+#if defined(CONFIG_CMD_NET)
+	int i;
+	unsigned short val;
+#endif
+
+	iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
+
+	/* Reset the PHY */
+	iop->pdat &= 0xfff7ffff;	/* PA12 = |SWITCH_RESET */
+#if defined(CONFIG_CMD_NET)
+	udelay(20000);
+	iop->pdat |= 0x00080000;
+	for (i=0; i<100; i++) {
+		udelay(20000);
+		if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
+			break;
+		}
+	}
+	/* initialize switch */
+	m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
+#endif
+}
+
+static unsigned long UPMATable[] = {
+	0x8fffec00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 0 to 3	*/
+	0x0ffcfc04,  0x3ffdfc00,  0xfffffc01,  0xfffffc01, /* Words 4 to 7	*/
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, /* Words 8 to 11	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 12 to 15	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 16 to 19	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 20 to 23	*/
+	0x8fffec00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 24 to 27	*/
+	0x0ffffc04,  0xfffffc01,  0xfffffc01,  0xfffffc01, /* Words 28 to 31	*/
+	0xfffffc00,  0xfffffc01,  0xfffffc01,  0xfffffc00, /* Words 32 to 35	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 36 to 39	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 40 to 43	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 44 to 47	*/
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, /* Words 48 to 51	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59	*/
+	0xffffec00,  0xffffec04,  0xffffec00,  0xfffffc01  /* Words 60 to 63	*/
+};
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	int i;
+
+	immap = (immap_t *) CONFIG_SYS_IMMR;
+	memctl = &immap->im_memctl;
+
+#if 0
+	/* CS2-5 - DSP via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#else
+	/* CS7 - DPRAM via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	volatile ioport_t *iop;
+	unsigned char temp;
+#if 0
+	/* DUMP UPMA RAM */
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	unsigned char c;
+	int i;
+
+	immap = (immap_t *) CONFIG_SYS_IMMR;
+	memctl = &immap->im_memctl;
+
+
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_RARR;
+	for (i = 0; i < 64; i++) {
+		c = *dummy;
+		printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
+		        memctl->memc_mamr,
+		        memctl->memc_mar,
+		        memctl->memc_mdr );
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	/* enable buffers (DSP, DPRAM) */
+	iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
+	iop->pdat &= 0xfffbffff;	/* PA13 = |EN_M_BCTL1 */
+
+	/* destroy DPRAM magic */
+	*(volatile unsigned char *)0xf0500000 = 0x00;
+
+	/* clear any pending DPRAM irq */
+	temp = *(volatile unsigned char *)0xf05003ff;
+
+	/* write module-id into DPRAM */
+	*(volatile unsigned char *)0xf0500201 = 0x50;
+
+	return 0;
+}
+
+#if defined(CONFIG_HAVE_OWN_RESET)
+int
+do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	volatile ioport_t *iop;
+
+	iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
+	iop->pdat |= 0x00002000;	/* PC18 = HW_RESET */
+	return 1;
+}
+#endif	/* CONFIG_HAVE_OWN_RESET */
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+phys_size_t initdram (int board_type)
+{
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile uchar *ramaddr;
+	int i;
+	uchar c;
+
+	immap = (immap_t *) CONFIG_SYS_IMMR;
+	memctl = &immap->im_memctl;
+	ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
+	c = 0xff;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
+	immap->im_siu_conf.sc_tescr1   = 0x00000000;
+	immap->im_siu_conf.sc_tescr2   = 0x00000000;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
+
+	/* Precharge all banks */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
+	*ramaddr = c;
+
+	/* CBR refresh */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	/* Mode Register write */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
+	*ramaddr = c;
+
+	/* Refresh enable */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
+	*ramaddr = c;
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return (CONFIG_SYS_SDRAM_SIZE);
+}
+
+int checkboard (void)
+{
+#ifdef CONFIG_CLKIN_66MHz
+	puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
+#else
+	puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
+#endif
+	return 0;
+}
diff --git a/u-boot/board/g2000/Makefile b/u-boot/board/g2000/Makefile
new file mode 100644
index 0000000..0f53340
--- /dev/null
+++ b/u-boot/board/g2000/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o strataflash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/g2000/g2000.c b/u-boot/board/g2000/g2000.c
new file mode 100644
index 0000000..713b699
--- /dev/null
+++ b/u-boot/board/g2000/g2000.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#define MEM_MCOPT1_INIT_VAL     0x00800000
+#define MEM_RTR_INIT_VAL        0x04070000
+#define MEM_PMIT_INIT_VAL       0x07c00000
+#define MEM_MB0CF_INIT_VAL      0x00082001
+#define MEM_MB1CF_INIT_VAL      0x04082000
+#define MEM_SDTR1_INIT_VAL      0x00854005
+#define SDRAM0_CFG_ENABLE       0x80000000
+
+#define CONFIG_SYS_SDRAM_SIZE          0x04000000      /* 64 MB */
+
+int board_early_init_f (void)
+{
+#if 0 /* test-only */
+	mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);      /* disable all ints */
+	mtdcr (UIC0CR, 0x00000010);
+	mtdcr (UIC0PR, 0xFFFF7FF0);      /* set int polarities */
+	mtdcr (UIC0TR, 0x00000010);      /* set int trigger levels */
+	mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+#else
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFFF0);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+#endif
+
+#if 1 /* test-only */
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+#endif
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+#if defined(CONFIG_CMD_NAND)
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
+#endif
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming G2000");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+
+/* -------------------------------------------------------------------------
+  G2000 rev B is an embeded design. we don't read for spd of this version.
+  Doing static SDRAM controller configuration in the following section.
+   ------------------------------------------------------------------------- */
+
+long int init_sdram_static_settings(void)
+{
+	/* disable memcontroller so updates work */
+	mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
+	mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
+	mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
+	mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
+	mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
+	mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
+
+	/* SDRAM have a power on delay,  500 micro should do */
+	udelay(500);
+	mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
+
+	return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
+ }
+
+
+phys_size_t initdram (int board_type)
+{
+	long int ret;
+
+/* flzt, we can still turn this on in the future */
+/* #ifdef CONFIG_SPD_EEPROM
+	ret = spd_sdram ();
+#else
+	ret = init_sdram_static_settings();
+#endif
+*/
+
+	ret = init_sdram_static_settings();
+
+	return ret;
+}
+
+#if 0 /* test-only !!! */
+int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong ap, cr;
+
+	printf("\nEBC registers for PPC405GP:\n");
+	mfebc(PB0AP, ap); mfebc(PB0CR, cr);
+	printf("0: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(PB1AP, ap); mfebc(PB1CR, cr);
+	printf("1: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(PB2AP, ap); mfebc(PB2CR, cr);
+	printf("2: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(PB3AP, ap); mfebc(PB3CR, cr);
+	printf("3: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(PB4AP, ap); mfebc(PB4CR, cr);
+	printf("4: AP=%08lx CP=%08lx\n", ap, cr);
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpebc,	1,	1,	do_dumpebc,
+	"Dump all EBC registers",
+	""
+);
+
+
+int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+
+	printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
+	for (i=0; i<=0x1e0; i++) {
+		if (!(i % 0x8)) {
+			printf("\n%04x ", i);
+		}
+		printf("%08lx ", get_dcr(i));
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpdcr,	1,	1,	do_dumpdcr,
+	"Dump all DCR registers",
+	""
+);
+
+
+int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
+	printf("\n%04x %08x ", 947, mfspr(947));
+	printf("\n%04x %08x ", 9, mfspr(9));
+	printf("\n%04x %08x ", 1014, mfspr(1014));
+	printf("\n%04x %08x ", 1015, mfspr(1015));
+	printf("\n%04x %08x ", 1010, mfspr(1010));
+	printf("\n%04x %08x ", 957, mfspr(957));
+	printf("\n%04x %08x ", 1008, mfspr(1008));
+	printf("\n%04x %08x ", 1018, mfspr(1018));
+	printf("\n%04x %08x ", 954, mfspr(954));
+	printf("\n%04x %08x ", 950, mfspr(950));
+	printf("\n%04x %08x ", 951, mfspr(951));
+	printf("\n%04x %08x ", 981, mfspr(981));
+	printf("\n%04x %08x ", 980, mfspr(980));
+	printf("\n%04x %08x ", 982, mfspr(982));
+	printf("\n%04x %08x ", 1012, mfspr(1012));
+	printf("\n%04x %08x ", 1013, mfspr(1013));
+	printf("\n%04x %08x ", 948, mfspr(948));
+	printf("\n%04x %08x ", 949, mfspr(949));
+	printf("\n%04x %08x ", 1019, mfspr(1019));
+	printf("\n%04x %08x ", 979, mfspr(979));
+	printf("\n%04x %08x ", 8, mfspr(8));
+	printf("\n%04x %08x ", 945, mfspr(945));
+	printf("\n%04x %08x ", 987, mfspr(987));
+	printf("\n%04x %08x ", 287, mfspr(287));
+	printf("\n%04x %08x ", 953, mfspr(953));
+	printf("\n%04x %08x ", 955, mfspr(955));
+	printf("\n%04x %08x ", 272, mfspr(272));
+	printf("\n%04x %08x ", 273, mfspr(273));
+	printf("\n%04x %08x ", 274, mfspr(274));
+	printf("\n%04x %08x ", 275, mfspr(275));
+	printf("\n%04x %08x ", 260, mfspr(260));
+	printf("\n%04x %08x ", 276, mfspr(276));
+	printf("\n%04x %08x ", 261, mfspr(261));
+	printf("\n%04x %08x ", 277, mfspr(277));
+	printf("\n%04x %08x ", 262, mfspr(262));
+	printf("\n%04x %08x ", 278, mfspr(278));
+	printf("\n%04x %08x ", 263, mfspr(263));
+	printf("\n%04x %08x ", 279, mfspr(279));
+	printf("\n%04x %08x ", 26, mfspr(26));
+	printf("\n%04x %08x ", 27, mfspr(27));
+	printf("\n%04x %08x ", 990, mfspr(990));
+	printf("\n%04x %08x ", 991, mfspr(991));
+	printf("\n%04x %08x ", 956, mfspr(956));
+	printf("\n%04x %08x ", 284, mfspr(284));
+	printf("\n%04x %08x ", 285, mfspr(285));
+	printf("\n%04x %08x ", 986, mfspr(986));
+	printf("\n%04x %08x ", 984, mfspr(984));
+	printf("\n%04x %08x ", 256, mfspr(256));
+	printf("\n%04x %08x ", 1, mfspr(1));
+	printf("\n%04x %08x ", 944, mfspr(944));
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpspr,	1,	1,	do_dumpspr,
+	"Dump all SPR registers",
+	""
+);
+#endif
diff --git a/u-boot/board/g2000/strataflash.c b/u-boot/board/g2000/strataflash.c
new file mode 100644
index 0000000..effe65a
--- /dev/null
+++ b/u-boot/board/g2000/strataflash.c
@@ -0,0 +1,793 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CONFIG_SYS_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CONFIG_SYS_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       - CONFIG_SYS_MONITOR_LEN,
+		       - 1, &flash_info[1]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			if (len & 0x1) { /* test-only: unaligned size */
+				puts("\nUnalgined size!!!\n"); /* test-only */
+				cnt++;
+			}
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/u-boot/board/gaisler/gr_cpci_ax2000/Makefile b/u-boot/board/gaisler/gr_cpci_ax2000/Makefile
new file mode 100644
index 0000000..66d5a38
--- /dev/null
+++ b/u-boot/board/gaisler/gr_cpci_ax2000/Makefile
@@ -0,0 +1,52 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+#flash.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gaisler/gr_cpci_ax2000/config.mk b/u-boot/board/gaisler/gr_cpci_ax2000/config.mk
new file mode 100644
index 0000000..e8df9a3
--- /dev/null
+++ b/u-boot/board/gaisler/gr_cpci_ax2000/config.mk
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2008
+# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# GR-CPCI-AX2000 board
+#
+
+# U-BOOT IN FLASH
+CONFIG_SYS_TEXT_BASE = 0x00000000
+
+# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON
+#CONFIG_SYS_TEXT_BASE = 0x40000000
+
+# U-BOOT IN SDRAM
+#CONFIG_SYS_TEXT_BASE = 0x60000000
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+	-I$(TOPDIR)/board
diff --git a/u-boot/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/u-boot/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
new file mode 100644
index 0000000..7fe85b8
--- /dev/null
+++ b/u-boot/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2008
+ * Daniel Hellstrom, daniel@gaisler.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <config.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+	return 1;
+}
+
+int checkboard(void)
+{
+	puts("Board: GR-CPCI-AX2000\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/gaisler/gr_cpci_ax2000/u-boot.lds b/u-boot/board/gaisler/gr_cpci_ax2000/u-boot.lds
new file mode 100644
index 0000000..2282682
--- /dev/null
+++ b/u-boot/board/gaisler/gr_cpci_ax2000/u-boot.lds
@@ -0,0 +1,158 @@
+/* Linker script for Gaisler Research AB's GR-CPCI-AX2000 board
+ * with template design.
+ *
+ * (C) Copyright 2008
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
+OUTPUT_ARCH(sparc)
+ENTRY(_start)
+SECTIONS
+{
+
+/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.interp : { *(.interp) }
+	.hash          : { *(.hash)		}
+	.dynsym        : { *(.dynsym)		}
+	.dynstr        : { *(.dynstr)		}
+	.rel.text      : { *(.rel.text)		}
+	.rela.text     : { *(.rela.text)	}
+	.rel.data      : { *(.rel.data)		}
+	.rela.data     : { *(.rela.data)	}
+	.rel.rodata    : { *(.rel.rodata)	}
+	.rela.rodata   : { *(.rela.rodata)	}
+	.rel.got       : { *(.rel.got)		}
+	.rela.got      : { *(.rela.got)		}
+	.rel.ctors     : { *(.rel.ctors)	}
+	.rela.ctors    : { *(.rela.ctors)	}
+	.rel.dtors     : { *(.rel.dtors)	}
+	.rela.dtors    : { *(.rela.dtors)	}
+	.rel.bss       : { *(.rel.bss)		}
+	.rela.bss      : { *(.rela.bss)		}
+	.rel.plt       : { *(.rel.plt)		}
+	.rela.plt      : { *(.rela.plt)		}
+	.init          : { *(.init)		}
+	.plt : { *(.plt) }
+
+	.text : {
+		_load_addr = .;
+		_text = .;
+
+		*(.start)
+		arch/sparc/cpu/leon3/start.o (.text)
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
+		. = ALIGN(8192);
+/* PROM CODE, Will be relocated to the end of memory,
+ * no global data accesses please.
+ */
+		__prom_start = .;
+		*(.prom.pgt)
+		*(.prom.data)
+		*(.prom.text)
+		. = ALIGN(16);
+		__prom_end = .;
+		*(.text)
+		*(.fixup)
+		*(.gnu.warning)
+/*		*(.got1)*/
+		. = ALIGN(16);
+		*(.eh_frame)
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN(4);
+	_etext = .;
+
+	/* CMD Table */
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	.data	:
+	{
+		*(.data)
+		*(.data1)
+		*(.data.rel)
+		*(.data.rel.*)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	}
+	_edata	=	.;
+	PROVIDE (edata = .);
+
+	. = ALIGN(4);
+	__got_start = .;
+	.got : {
+		*(.got)
+/*		*(.data.rel)
+		*(.data.rel.local)*/
+		. = ALIGN(16);
+	}
+	__got_end = .;
+
+/*	.data.rel : { } */
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss		:
+	{
+	 *(.sbss) *(.scommon)
+	 *(.dynbss)
+	 *(.bss)
+	 *(COMMON)
+	. = ALIGN(16); /* to speed clearing of bss up */
+	}
+	__bss_end = . ;
+	_end = . ;
+	PROVIDE (end = .);
+
+/* Relocated into main memory */
+
+	/* Start of main memory */
+	/*. = 0x40000000;*/
+
+	.stack (NOLOAD)	: { *(.stack) }
+
+	/* PROM CODE */
+
+	/* global data in RAM passed to kernel after booting */
+
+  .stab 0		: { *(.stab) }
+  .stabstr 0		: { *(.stabstr) }
+  .stab.excl 0		: { *(.stab.excl) }
+  .stab.exclstr 0	: { *(.stab.exclstr) }
+  .stab.index 0		: { *(.stab.index) }
+  .stab.indexstr 0	: { *(.stab.indexstr) }
+  .comment 0		: { *(.comment) }
+
+}
diff --git a/u-boot/board/gaisler/gr_ep2s60/Makefile b/u-boot/board/gaisler/gr_ep2s60/Makefile
new file mode 100644
index 0000000..66d5a38
--- /dev/null
+++ b/u-boot/board/gaisler/gr_ep2s60/Makefile
@@ -0,0 +1,52 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+#flash.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gaisler/gr_ep2s60/config.mk b/u-boot/board/gaisler/gr_ep2s60/config.mk
new file mode 100644
index 0000000..ce82469
--- /dev/null
+++ b/u-boot/board/gaisler/gr_ep2s60/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2008
+# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Altera NIOS delopment board Stratix II edition, FPGA device EP2S60,
+# with GRLIB Template design (GPL Open Source SPARC/LEON3)
+#
+
+# U-BOOT IN FLASH
+CONFIG_SYS_TEXT_BASE = 0x00000000
+
+# U-BOOT IN SDRAM
+#CONFIG_SYS_TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+	-I$(TOPDIR)/board
diff --git a/u-boot/board/gaisler/gr_ep2s60/gr_ep2s60.c b/u-boot/board/gaisler/gr_ep2s60/gr_ep2s60.c
new file mode 100644
index 0000000..7241c6d
--- /dev/null
+++ b/u-boot/board/gaisler/gr_ep2s60/gr_ep2s60.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2008
+ * Daniel Hellstrom, daniel@gaisler.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <config.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+	return 1;
+}
+
+int checkboard(void)
+{
+	puts("Board: EP2S60 GRLIB\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/gaisler/gr_ep2s60/u-boot.lds b/u-boot/board/gaisler/gr_ep2s60/u-boot.lds
new file mode 100644
index 0000000..0ca2651
--- /dev/null
+++ b/u-boot/board/gaisler/gr_ep2s60/u-boot.lds
@@ -0,0 +1,158 @@
+/* Linker script for Gaisler Research AB's Template design
+ * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
+ *
+ * (C) Copyright 2008
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
+OUTPUT_ARCH(sparc)
+ENTRY(_start)
+SECTIONS
+{
+
+/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.interp : { *(.interp) }
+	.hash          : { *(.hash)		}
+	.dynsym        : { *(.dynsym)		}
+	.dynstr        : { *(.dynstr)		}
+	.rel.text      : { *(.rel.text)		}
+	.rela.text     : { *(.rela.text)	}
+	.rel.data      : { *(.rel.data)		}
+	.rela.data     : { *(.rela.data)	}
+	.rel.rodata    : { *(.rel.rodata)	}
+	.rela.rodata   : { *(.rela.rodata)	}
+	.rel.got       : { *(.rel.got)		}
+	.rela.got      : { *(.rela.got)		}
+	.rel.ctors     : { *(.rel.ctors)	}
+	.rela.ctors    : { *(.rela.ctors)	}
+	.rel.dtors     : { *(.rel.dtors)	}
+	.rela.dtors    : { *(.rela.dtors)	}
+	.rel.bss       : { *(.rel.bss)		}
+	.rela.bss      : { *(.rela.bss)		}
+	.rel.plt       : { *(.rel.plt)		}
+	.rela.plt      : { *(.rela.plt)		}
+	.init          : { *(.init)		}
+	.plt : { *(.plt) }
+
+	.text : {
+		_load_addr = .;
+		_text = .;
+
+		*(.start)
+		arch/sparc/cpu/leon3/start.o (.text)
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
+		. = ALIGN(8192);
+/* PROM CODE, Will be relocated to the end of memory,
+ * no global data accesses please.
+ */
+		__prom_start = .;
+		*(.prom.pgt)
+		*(.prom.data)
+		*(.prom.text)
+		. = ALIGN(16);
+		__prom_end = .;
+		*(.text)
+		*(.fixup)
+		*(.gnu.warning)
+/*		*(.got1)*/
+		. = ALIGN(16);
+		*(.eh_frame)
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN(4);
+	_etext = .;
+
+	/* CMD Table */
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	.data	:
+	{
+		*(.data)
+		*(.data1)
+		*(.data.rel)
+		*(.data.rel.*)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	}
+	_edata	=	.;
+	PROVIDE (edata = .);
+
+	. = ALIGN(4);
+	__got_start = .;
+	.got : {
+		*(.got)
+/*		*(.data.rel)
+		*(.data.rel.local)*/
+		. = ALIGN(16);
+	}
+	__got_end = .;
+
+/*	.data.rel : { } */
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss		:
+	{
+	 *(.sbss) *(.scommon)
+	 *(.dynbss)
+	 *(.bss)
+	 *(COMMON)
+	. = ALIGN(16); /* to speed clearing of bss up */
+	}
+	__bss_end = . ;
+	_end = . ;
+	PROVIDE (end = .);
+
+/* Relocated into main memory */
+
+	/* Start of main memory */
+	/*. = 0x40000000;*/
+
+	.stack (NOLOAD)	: { *(.stack) }
+
+	/* PROM CODE */
+
+	/* global data in RAM passed to kernel after booting */
+
+  .stab 0		: { *(.stab) }
+  .stabstr 0		: { *(.stabstr) }
+  .stab.excl 0		: { *(.stab.excl) }
+  .stab.exclstr 0	: { *(.stab.exclstr) }
+  .stab.index 0		: { *(.stab.index) }
+  .stab.indexstr 0	: { *(.stab.indexstr) }
+  .comment 0		: { *(.comment) }
+
+}
diff --git a/u-boot/board/gaisler/gr_xc3s_1500/Makefile b/u-boot/board/gaisler/gr_xc3s_1500/Makefile
new file mode 100644
index 0000000..66d5a38
--- /dev/null
+++ b/u-boot/board/gaisler/gr_xc3s_1500/Makefile
@@ -0,0 +1,52 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+#flash.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gaisler/gr_xc3s_1500/config.mk b/u-boot/board/gaisler/gr_xc3s_1500/config.mk
new file mode 100644
index 0000000..c60ef7b
--- /dev/null
+++ b/u-boot/board/gaisler/gr_xc3s_1500/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2007
+# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# GR-XC3S-1500 board
+#
+
+# U-BOOT IN FLASH
+CONFIG_SYS_TEXT_BASE = 0x00000000
+
+# U-BOOT IN RAM
+#CONFIG_SYS_TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+	-I$(TOPDIR)/board
diff --git a/u-boot/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/u-boot/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
new file mode 100644
index 0000000..fc8cf84
--- /dev/null
+++ b/u-boot/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2007
+ * Daniel Hellstrom, daniel@gaisler.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+	return 1;
+}
+
+int checkboard(void)
+{
+	puts("Board: GR-XC3S-1500\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
diff --git a/u-boot/board/gaisler/gr_xc3s_1500/u-boot.lds b/u-boot/board/gaisler/gr_xc3s_1500/u-boot.lds
new file mode 100644
index 0000000..67222ac
--- /dev/null
+++ b/u-boot/board/gaisler/gr_xc3s_1500/u-boot.lds
@@ -0,0 +1,160 @@
+/* Linker script for Gaisler Research AB's GR-XC3S-1500 board
+ * with template design.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
+OUTPUT_ARCH(sparc)
+ENTRY(_start)
+SECTIONS
+{
+
+/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.interp : { *(.interp) }
+	.hash          : { *(.hash)		}
+	.dynsym        : { *(.dynsym)		}
+	.dynstr        : { *(.dynstr)		}
+	.rel.text      : { *(.rel.text)		}
+	.rela.text     : { *(.rela.text)	}
+	.rel.data      : { *(.rel.data)		}
+	.rela.data     : { *(.rela.data)	}
+	.rel.rodata    : { *(.rel.rodata)	}
+	.rela.rodata   : { *(.rela.rodata)	}
+	.rel.got       : { *(.rel.got)		}
+	.rela.got      : { *(.rela.got)		}
+	.rel.ctors     : { *(.rel.ctors)	}
+	.rela.ctors    : { *(.rela.ctors)	}
+	.rel.dtors     : { *(.rel.dtors)	}
+	.rela.dtors    : { *(.rela.dtors)	}
+	.rel.bss       : { *(.rel.bss)		}
+	.rela.bss      : { *(.rela.bss)		}
+	.rel.plt       : { *(.rel.plt)		}
+	.rela.plt      : { *(.rela.plt)		}
+	.init          : { *(.init)		}
+	.plt : { *(.plt) }
+
+	.text : {
+		_load_addr = .;
+		_text = .;
+
+		*(.start)
+		arch/sparc/cpu/leon3/start.o (.text)
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
+		. = ALIGN(8192);
+/* PROM CODE, Will be relocated to the end of memory,
+ * no global data accesses please.
+ */
+		__prom_start = .;
+		*(.prom.pgt)
+		*(.prom.data)
+		*(.prom.text)
+		. = ALIGN(16);
+		__prom_end = .;
+		*(.text)
+		*(.fixup)
+		*(.gnu.warning)
+/*		*(.got1)*/
+		. = ALIGN(16);
+		*(.eh_frame)
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN(4);
+	_etext = .;
+
+	/* CMD Table */
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	.data	:
+	{
+		*(.data)
+		*(.data1)
+		*(.data.rel)
+		*(.data.rel.*)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	}
+	_edata	=	.;
+	PROVIDE (edata = .);
+
+	. = ALIGN(4);
+	__got_start = .;
+	.got : {
+		*(.got)
+/*		*(.data.rel)
+		*(.data.rel.local)*/
+		. = ALIGN(16);
+	}
+	__got_end = .;
+
+/*	.data.rel : { } */
+
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss		:
+	{
+	 *(.sbss) *(.scommon)
+	 *(.dynbss)
+	 *(.bss)
+	 *(COMMON)
+	. = ALIGN(16); /* to speed clearing of bss up */
+	}
+	__bss_end = . ;
+	_end = . ;
+	PROVIDE (end = .);
+
+/* Relocated into main memory */
+
+	/* Start of main memory */
+	/*. = 0x40000000;*/
+
+	.stack (NOLOAD)	: { *(.stack) }
+
+	/* PROM CODE */
+
+	/* global data in RAM passed to kernel after booting */
+
+
+  .stab 0		: { *(.stab) }
+  .stabstr 0		: { *(.stabstr) }
+  .stab.excl 0		: { *(.stab.excl) }
+  .stab.exclstr 0	: { *(.stab.exclstr) }
+  .stab.index 0		: { *(.stab.index) }
+  .stab.indexstr 0	: { *(.stab.indexstr) }
+  .comment 0		: { *(.comment) }
+
+}
diff --git a/u-boot/board/gaisler/grsim/Makefile b/u-boot/board/gaisler/grsim/Makefile
new file mode 100644
index 0000000..a567c76
--- /dev/null
+++ b/u-boot/board/gaisler/grsim/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gaisler/grsim/config.mk b/u-boot/board/gaisler/grsim/config.mk
new file mode 100644
index 0000000..c2e8268
--- /dev/null
+++ b/u-boot/board/gaisler/grsim/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2007
+# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# GRSIM simulating a LEON3 GR-XC3S-1500 board
+#
+
+# U-BOOT IN FLASH
+CONFIG_SYS_TEXT_BASE = 0x00000000
+
+# U-BOOT IN RAM
+#CONFIG_SYS_TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+	-I$(TOPDIR)/board
diff --git a/u-boot/board/gaisler/grsim/grsim.c b/u-boot/board/gaisler/grsim/grsim.c
new file mode 100644
index 0000000..deccd3d
--- /dev/null
+++ b/u-boot/board/gaisler/grsim/grsim.c
@@ -0,0 +1,43 @@
+/* GRSIM/TSIM board
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+	return 1;
+}
+
+int checkboard(void)
+{
+	puts("Board: GRSIM/TSIM\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
diff --git a/u-boot/board/gaisler/grsim/u-boot.lds b/u-boot/board/gaisler/grsim/u-boot.lds
new file mode 100644
index 0000000..681fd8d
--- /dev/null
+++ b/u-boot/board/gaisler/grsim/u-boot.lds
@@ -0,0 +1,159 @@
+/* Linker script for Gaisler Research AB's GRSIM LEON3 simulator.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
+OUTPUT_ARCH(sparc)
+ENTRY(_start)
+SECTIONS
+{
+
+/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.interp : { *(.interp) }
+	.hash          : { *(.hash) }
+	.dynsym        : { *(.dynsym) }
+	.dynstr        : { *(.dynstr) }
+	.rel.text      : { *(.rel.text) }
+	.rela.text     : { *(.rela.text) }
+	.rel.data      : { *(.rel.data) }
+	.rela.data     : { *(.rela.data) }
+	.rel.rodata    : { *(.rel.rodata) }
+	.rela.rodata   : { *(.rela.rodata) }
+	.rel.got       : { *(.rel.got) }
+	.rela.got      : { *(.rela.got) }
+	.rel.ctors     : { *(.rel.ctors) }
+	.rela.ctors    : { *(.rela.ctors) }
+	.rel.dtors     : { *(.rel.dtors) }
+	.rela.dtors    : { *(.rela.dtors) }
+	.rel.bss       : { *(.rel.bss) }
+	.rela.bss      : { *(.rela.bss) }
+	.rel.plt       : { *(.rel.plt) }
+	.rela.plt      : { *(.rela.plt) }
+	.init          : { *(.init) }
+	.plt : { *(.plt) }
+
+	.text : {
+		_load_addr = .;
+		_text = .;
+
+		*(.start)
+		arch/sparc/cpu/leon3/start.o (.text)
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
+		. = ALIGN(8192);
+/* PROM CODE, Will be relocated to the end of memory,
+ * no global data accesses please.
+ */
+		__prom_start = .;
+		*(.prom.pgt)
+		*(.prom.data)
+		*(.prom.text)
+		. = ALIGN(16);
+		__prom_end = .;
+		*(.text)
+		*(.fixup)
+		*(.gnu.warning)
+/*		*(.got1)*/
+		. = ALIGN(16);
+		*(.eh_frame)
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN(4);
+	_etext = .;
+
+	/* CMD Table */
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	.data	:
+	{
+		*(.data)
+		*(.data1)
+		*(.data.rel)
+		*(.data.rel.*)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	}
+	_edata	=	.;
+	PROVIDE (edata = .);
+
+	. = ALIGN(4);
+	__got_start = .;
+	.got : {
+		*(.got)
+/*		*(.data.rel)
+		*(.data.rel.local)*/
+		. = ALIGN(16);
+	}
+	__got_end = .;
+
+/*	.data.rel : { } */
+
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss	:
+	{
+	 *(.sbss) *(.scommon)
+	 *(.dynbss)
+	 *(.bss)
+	 *(COMMON)
+	. = ALIGN(16); /* to speed clearing of bss up */
+	}
+	__bss_end = . ;
+	_end = . ;
+	PROVIDE (end = .);
+
+/* Relocated into main memory */
+
+	/* Start of main memory */
+	/*. = 0x40000000;*/
+
+	.stack (NOLOAD)	: { *(.stack) }
+
+	/* PROM CODE */
+
+	/* global data in RAM passed to kernel after booting */
+
+
+	.stab 0		: { *(.stab) }
+	.stabstr 0		: { *(.stabstr) }
+	.stab.excl 0		: { *(.stab.excl) }
+	.stab.exclstr 0	: { *(.stab.exclstr) }
+	.stab.index 0		: { *(.stab.index) }
+	.stab.indexstr 0	: { *(.stab.indexstr) }
+	.comment 0		: { *(.comment) }
+
+}
diff --git a/u-boot/board/gaisler/grsim_leon2/Makefile b/u-boot/board/gaisler/grsim_leon2/Makefile
new file mode 100644
index 0000000..a567c76
--- /dev/null
+++ b/u-boot/board/gaisler/grsim_leon2/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gaisler/grsim_leon2/config.mk b/u-boot/board/gaisler/grsim_leon2/config.mk
new file mode 100644
index 0000000..4d88691
--- /dev/null
+++ b/u-boot/board/gaisler/grsim_leon2/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2007
+# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# GRSIM simulating a LEON2 board
+#
+
+# RUN U-BOOT FROM PROM
+CONFIG_SYS_TEXT_BASE = 0x00000000
+
+# RUN U-BOOT FROM RAM
+#CONFIG_SYS_TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+	-I$(TOPDIR)/board
diff --git a/u-boot/board/gaisler/grsim_leon2/grsim_leon2.c b/u-boot/board/gaisler/grsim_leon2/grsim_leon2.c
new file mode 100644
index 0000000..61445fe
--- /dev/null
+++ b/u-boot/board/gaisler/grsim_leon2/grsim_leon2.c
@@ -0,0 +1,43 @@
+/* GRSIM/TSIM board
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+	return 1;
+}
+
+int checkboard(void)
+{
+	puts("Board: GRSIM/TSIM LEON2\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
diff --git a/u-boot/board/gaisler/grsim_leon2/u-boot.lds b/u-boot/board/gaisler/grsim_leon2/u-boot.lds
new file mode 100644
index 0000000..a12e7fb
--- /dev/null
+++ b/u-boot/board/gaisler/grsim_leon2/u-boot.lds
@@ -0,0 +1,157 @@
+/* Linker script for Gaisler Research AB's GRSIM LEON2 simulator.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
+OUTPUT_ARCH(sparc)
+ENTRY(_start)
+SECTIONS
+{
+
+/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.interp : { *(.interp) }
+	.hash          : { *(.hash) }
+	.dynsym        : { *(.dynsym) }
+	.dynstr        : { *(.dynstr) }
+	.rel.text      : { *(.rel.text) }
+	.rela.text     : { *(.rela.text) }
+	.rel.data      : { *(.rel.data) }
+	.rela.data     : { *(.rela.data) }
+	.rel.rodata    : { *(.rel.rodata) }
+	.rela.rodata   : { *(.rela.rodata) }
+	.rel.got       : { *(.rel.got) }
+	.rela.got      : { *(.rela.got) }
+	.rel.ctors     : { *(.rel.ctors) }
+	.rela.ctors    : { *(.rela.ctors) }
+	.rel.dtors     : { *(.rel.dtors) }
+	.rela.dtors    : { *(.rela.dtors) }
+	.rel.bss       : { *(.rel.bss) }
+	.rela.bss      : { *(.rela.bss) }
+	.rel.plt       : { *(.rel.plt) }
+	.rela.plt      : { *(.rela.plt) }
+	.init          : { *(.init) }
+	.plt : { *(.plt) }
+
+	.text : {
+		_load_addr = .;
+		_text = .;
+
+		*(.start)
+		arch/sparc/cpu/leon2/start.o (.text)
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
+		. = ALIGN(8192);
+/* PROM CODE, Will be relocated to the end of memory,
+ * no global data accesses please.
+ */
+		__prom_start = .;
+		*(.prom.pgt)
+		*(.prom.data)
+		*(.prom.text)
+		. = ALIGN(16);
+		__prom_end = .;
+		*(.text)
+		*(.fixup)
+		*(.gnu.warning)
+/*		*(.got1)*/
+		. = ALIGN(16);
+		*(.eh_frame)
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN(4);
+	_etext = .;
+
+	/* CMD Table */
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	.data	:
+	{
+		*(.data)
+		*(.data1)
+		*(.data.rel)
+		*(.data.rel.*)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	}
+	_edata	=	.;
+	PROVIDE (edata = .);
+
+	. = ALIGN(4);
+	__got_start = .;
+	.got : {
+		*(.got)
+/*		*(.data.rel)
+		*(.data.rel.local)*/
+		. = ALIGN(16);
+	}
+	__got_end = .;
+
+/*	.data.rel : { } */
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss	:
+	{
+	 *(.sbss) *(.scommon)
+	 *(.dynbss)
+	 *(.bss)
+	 *(COMMON)
+	. = ALIGN(16); /* to speed clearing of bss up */
+	}
+	__bss_end = . ;
+	_end = . ;
+	PROVIDE (end = .);
+
+/* Relocated into main memory */
+
+	/* Start of main memory */
+	/*. = 0x40000000;*/
+
+	.stack (NOLOAD)	: { *(.stack) }
+
+	/* PROM CODE */
+
+	/* global data in RAM passed to kernel after booting */
+
+	.stab 0		: { *(.stab) }
+	.stabstr 0		: { *(.stabstr) }
+	.stab.excl 0		: { *(.stab.excl) }
+	.stab.exclstr 0	: { *(.stab.exclstr) }
+	.stab.index 0		: { *(.stab.index) }
+	.stab.indexstr 0	: { *(.stab.indexstr) }
+	.comment 0		: { *(.comment) }
+
+}
diff --git a/u-boot/board/galaxy5200/Makefile b/u-boot/board/galaxy5200/Makefile
new file mode 100644
index 0000000..f5d88bb
--- /dev/null
+++ b/u-boot/board/galaxy5200/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/galaxy5200/galaxy5200.c b/u-boot/board/galaxy5200/galaxy5200.c
new file mode 100644
index 0000000..d4a2245
--- /dev/null
+++ b/u-boot/board/galaxy5200/galaxy5200.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * (C) Copyright 2009
+ * Eric Millbrandt, DEKA Research and Development Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	volatile struct mpc5xxx_cdm *cdm =
+		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+#ifdef SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32 (&sdram->mode, (SDRAM_EMODE));
+
+	/* set mode register: reset DLL */
+	out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
+#endif
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+	/* auto refresh */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
+
+	/* set mode register */
+	out_be32 (&sdram->mode, (SDRAM_MODE));
+
+	/* normal operation */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | hi_addr_bit));
+
+	/* set CDM clock enable register, set MPC5200B SDRAM bus */
+	/* to reduced driver strength */
+	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make
+ *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
+ *	work if CONFIG_SYS_SDRAM_BASE
+ *	is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+							 /* 256MB at 0x0 */
+	out_be32 (&mm->sdram0, 0x0000001b);
+							 /* disabled */
+	out_be32 (&mm->sdram1, 0x10000000);
+
+	/* setup config registers */
+	out_be32 (&sdram->config1, SDRAM_CONFIG1);
+	out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32 (&mm->sdram0,
+			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+							/* disabled */
+		out_be32 (&mm->sdram0, 0);
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mm->sdram0) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+	puts("Board: galaxy5200\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t * bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+	debug ("init_ide_reset\n");
+
+	/* Configure TIMER_5 as GPIO output for ATA reset */
+	/* Deassert reset */
+	gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
+}
+
+void ide_set_reset (int idereset)
+{
+	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+	debug ("ide_reset(%d)\n", idereset);
+
+	/* Configure TIMER_5 as GPIO output for ATA reset */
+	if (idereset) {
+		gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
+
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(50);
+	} else {
+		gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
+		udelay(50);
+	}
+}
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/u-boot/board/gcplus/Makefile b/u-boot/board/gcplus/Makefile
new file mode 100644
index 0000000..e62aa1b
--- /dev/null
+++ b/u-boot/board/gcplus/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2003 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= gcplus.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gcplus/config.mk b/u-boot/board/gcplus/config.mk
new file mode 100644
index 0000000..a9bd3ff
--- /dev/null
+++ b/u-boot/board/gcplus/config.mk
@@ -0,0 +1,13 @@
+#
+# ADS GCPlus board with SA1110 cpu
+#
+# The ADS GCPlus has 2 banks of 16 MiB SDRAM
+#
+# We use the ADS GCPlus Linux boot ROM to load U-Boot into SDRAM
+# at c020'0000 and then move ourself to c8f0'0000. Basically, just
+# install the U-Boot binary as you would the Linux zImage and then
+# reap the benfits of more convenient Linux development cycles, i.e.
+# bootp;tftp;bootm, repeat, etc.,.
+#
+
+CONFIG_SYS_TEXT_BASE = 0xc8f00000
diff --git a/u-boot/board/gcplus/flash.c b/u-boot/board/gcplus/flash.c
new file mode 100644
index 0000000..8511582
--- /dev/null
+++ b/u-boot/board/gcplus/flash.c
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)				__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)				__swab32(x)
+#endif
+
+#define FPW				FLASH_PORT_WIDTH
+#define FPWV				FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPW * addr, flash_info_t * info);
+static int write_data(flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+void inline spin_wheel(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init(void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_FLASH_BASE,
+		      CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf("28F128J3A\n");
+		break;
+	case FLASH_28F640J5:
+		printf("28F640J5\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong
+flash_get_size(FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb();
+	value = addr[1];	/* device ID            */
+	switch (value) {
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+	case (FPW) INTEL_ID_28F640J5:
+		info->flash_id += FLASH_28F640J5;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf(" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_data(flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/gcplus/gcplus.c b/u-boot/board/gcplus/gcplus.c
new file mode 100644
index 0000000..71607f2
--- /dev/null
+++ b/u-boot/board/gcplus/gcplus.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <SA-1100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT;
+
+	gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */
+
+	/* Most of the ADS GCPlus I/O is connected to Static nCS2.
+	 * So I'm brute forcing nCS2 timiming here for worst case.
+	 */
+	MSC1 &= ~0xFFFF;
+	MSC1 |= 0x8649;
+
+	/* Nothing is connected to Static nCS4 or nCS5. But I'm using
+	 * nCS4 as a paranoia safe guard to force nCS2, nOE; nWE high
+	 * after accessing I/O via (non-VLIO) nCS2. What can I say, I'm
+	 * paranoid and lack decent tools to alleviate my fear. I sure
+	 * do wish I had a logic analyzer. : (
+	 */
+
+	MSC2 =  0xfff9fff9;
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/gcplus/lowlevel_init.S b/u-boot/board/gcplus/lowlevel_init.S
new file mode 100644
index 0000000..f292c4d
--- /dev/null
+++ b/u-boot/board/gcplus/lowlevel_init.S
@@ -0,0 +1,77 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
+	 * However the darn thing leaves the MMU enabled before handing control
+	 * over to us. So we need to disable the MMU and we use lowlevel_init
+	 * to do it.
+	 */
+
+@ The following code segment was borrowed with gratitude from:
+@	linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
+
+	@ Data cache might be active.
+	@ Be sure to flush kernel binary out of the cache,
+	@ whatever state it is, before it is turned off.
+	@ This is done by fetching through currently executed
+	@ memory to be sure we hit the same cache.
+	bic	r2, pc, #0x1f
+	add	r3, r2, #0x4000		@ 16 kb is quite enough...
+1:	ldr	r0, [r2], #32
+	teq	r2, r3
+	bne	1b
+	mcr	p15, 0, r0, c7, c10, 4	@ drain WB
+	mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
+
+	@ disabling MMU and caches
+	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+	bic	r0, r0, #0x0d		@ clear WB, DC, MMU
+	bic	r0, r0, #0x1000		@ clear Icache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	b	2f
+2:
+	nop
+	nop
+	nop
+	nop
+	nop
+
+
+	mov	pc, lr
diff --git a/u-boot/board/gdsys/405ep/405ep.c b/u-boot/board/gdsys/405ep/405ep.c
new file mode 100644
index 0000000..86a3ec8
--- /dev/null
+++ b/u-boot/board/gdsys/405ep/405ep.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
+
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->fpga_state[k] = 0;
+
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	/*
+	 * setup io-latches for reset
+	 */
+	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+
+	/*
+	 * wait for fpga-done
+	 */
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!(in_le16((void *)LATCH2_BASE)
+			& CONFIG_SYS_FPGA_DONE(k))) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
+
+	/*
+	 * setup io-latches for boot (stop reset)
+	 */
+	udelay(10);
+	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			out_le16(&fpga->reflection_low,
+				REFLECTION_TESTPATTERN);
+			if (in_le16(&fpga->reflection_high) ==
+				REFLECTION_TESTPATTERN_INV)
+				break;
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/gdsys/405ep/Makefile b/u-boot/board/gdsys/405ep/Makefile
new file mode 100644
index 0000000..169418c
--- /dev/null
+++ b/u-boot/board/gdsys/405ep/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-$(CONFIG_IO) += io.o
+COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
+
+COBJS   := $(BOARD).o $(COBJS-y)
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gdsys/405ep/dlvision-10g.c b/u-boot/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 0000000..df7fb14
--- /dev/null
+++ b/u-boot/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+enum {
+	UNITTYPE_VIDEO_USER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+	HWVER_101 = 0,
+	HWVER_110 = 1,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_156250 = 2,
+};
+
+enum {
+	RAM_NONE = 0,
+	RAM_DDR2_32 = 1,
+	RAM_DDR2_64 = 2,
+};
+
+static void print_fpga_info(unsigned dev)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_rs232;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+	int fpga_state = get_fpga_state(dev);
+
+	printf("FPGA%d: ", dev);
+
+	hardware_version = versions & 0x000f;
+
+	if (fpga_state
+	    && !((hardware_version == HWVER_101)
+		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+		puts("not available\n");
+		print_fpga_state(dev);
+		return;
+	}
+
+	unit_type = (versions >> 4) & 0x000f;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features >> 13) & 0x0003;
+	feature_rs232 = fpga_features & (1<<11);
+	feature_audio = (fpga_features >> 9) & 0x0003;
+	feature_sysclock = (fpga_features >> 7) & 0x0003;
+	feature_ramconfig = (fpga_features >> 5) & 0x0003;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features >> 2) & 0x0003;
+	feature_video_channels = fpga_features & 0x0003;
+
+	switch (unit_type) {
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel Userside");
+		break;
+
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel Userside");
+		break;
+
+	case UNITTYPE_VIDEO_SERVER:
+		printf("Videochannel Serverside");
+		break;
+
+	case UNITTYPE_MAIN_SERVER:
+		printf("Mainchannel Serverside");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_101:
+		printf(" HW-Ver 1.01\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	switch (feature_sysclock) {
+	case SYSCLK_156250:
+		printf(", clock 156.25 MHz");
+		break;
+
+	default:
+		printf(", clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_ramconfig) {
+	case RAM_NONE:
+		printf("no RAM");
+		break;
+
+	case RAM_DDR2_32:
+		printf("RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR2_64:
+		printf("RAM 64 bit DDR2");
+		break;
+
+	default:
+		printf("RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+		feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	unsigned k;
+	char *s = getenv("serial#");
+
+	printf("Board: ");
+
+	printf("DLVision 10G");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		print_fpga_info(k);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
+		if (!get_fpga_state(k)
+		    || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
+			osd_probe(k);
+
+	return 0;
+}
diff --git a/u-boot/board/gdsys/405ep/io.c b/u-boot/board/gdsys/405ep/io.c
new file mode 100644
index 0000000..0974019
--- /dev/null
+++ b/u-boot/board/gdsys/405ep/io.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <miiphy.h>
+
+#include <gdsys_fpga.h>
+
+#define PHYREG_CONTROL				0
+#define PHYREG_PAGE_ADDRESS			22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
+
+enum {
+	UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_121 = 2,
+	HWVER_122 = 3,
+};
+
+int configure_gbit_phy(unsigned char addr)
+{
+	unsigned short value;
+
+	/* select page 2 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0002))
+		goto err_out;
+	/* disable SGMII autonegotiation */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+		goto err_out;
+	/* select page 0 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0000))
+		goto err_out;
+	/* switch from powerdown to normal operation */
+	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+		goto err_out;
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+		goto err_out;
+	/* reset phy so settings take effect */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_CONTROL, 0x9140))
+		goto err_out;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	char *s = getenv("serial#");
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+	unsigned feature_expansion;
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+	feature_expansion = fpga_features & (1<<15);
+
+	printf("Board: ");
+
+	printf("CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_CCD_SWITCH:
+		printf("CCD-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	case HWVER_121:
+		printf(" HW-Ver 1.21\n");
+		break;
+
+	case HWVER_122:
+		printf(" HW-Ver 1.22\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)", feature_channels);
+
+	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+
+	return 0;
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	unsigned int k;
+
+	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+		bb_miiphy_read, bb_miiphy_write);
+
+	for (k = 0; k < 32; ++k)
+		configure_gbit_phy(k);
+
+	/* take fpga serdes blocks out of reset */
+	out_le16(&fpga->quad_serdes_reset, 0);
+
+	return 0;
+}
diff --git a/u-boot/board/gdsys/405ep/iocon.c b/u-boot/board/gdsys/405ep/iocon.c
new file mode 100644
index 0000000..20770e4
--- /dev/null
+++ b/u-boot/board/gdsys/405ep/iocon.c
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+enum {
+	UNITTYPE_MAIN_SERVER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_104 = 1,
+	HWVER_110 = 2,
+};
+
+enum {
+	COMPRESSION_NONE = 0,
+	COMPRESSION_TYPE1_DELTA,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_147456 = 0,
+};
+
+enum {
+	RAM_DDR2_32 = 0,
+};
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	char *s = getenv("serial#");
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_osd;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features & 0xe000) >> 13;
+	feature_osd = fpga_features & (1<<11);
+	feature_audio = (fpga_features & 0x0600) >> 9;
+	feature_sysclock = (fpga_features & 0x0180) >> 7;
+	feature_ramconfig = (fpga_features & 0x0060) >> 5;
+	feature_carriers = (fpga_features & 0x000c) >> 2;
+	feature_video_channels = fpga_features & 0x0003;
+
+	printf("Board: ");
+
+	printf("IoCon");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel");
+		break;
+
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_104:
+		printf(" HW-Ver 1.04\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+
+	switch (feature_compression) {
+	case COMPRESSION_NONE:
+		printf(" no compression");
+		break;
+
+	case COMPRESSION_TYPE1_DELTA:
+		printf(" type1-deltacompression");
+		break;
+
+	default:
+		printf(" compression %d(not supported)", feature_compression);
+		break;
+	}
+
+	printf(", %sosd", feature_osd ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+
+	default:
+		printf("clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	switch (feature_ramconfig) {
+	case RAM_DDR2_32:
+		printf(", RAM 32 bit DDR2");
+		break;
+
+	default:
+		printf(", RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s)", feature_carriers);
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	return osd_probe(0);
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ */
+void fpga_gpio_set(int pin)
+{
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
+}
+
+void fpga_gpio_clear(int pin)
+{
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
+}
+
+int fpga_gpio_get(int pin)
+{
+	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
+}
diff --git a/u-boot/board/gdsys/common/Makefile b/u-boot/board/gdsys/common/Makefile
new file mode 100644
index 0000000..4c7fc99
--- /dev/null
+++ b/u-boot/board/gdsys/common/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS-$(CONFIG_IO) += miiphybb.o
+COBJS-$(CONFIG_IOCON) += osd.o
+COBJS-$(CONFIG_DLVISION_10G) += osd.o
+
+COBJS   := $(COBJS-y)
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gdsys/common/miiphybb.c b/u-boot/board/gdsys/common/miiphybb.c
new file mode 100644
index 0000000..e56e966
--- /dev/null
+++ b/u-boot/board/gdsys/common/miiphybb.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
+
+	return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
+
+	return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
+
+	return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	*v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
+
+	return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
+
+	return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = CONFIG_SYS_GBIT_MII_BUSNAME,
+		.init = io_bb_mii_init,
+		.mdio_active = io_bb_mdio_active,
+		.mdio_tristate = io_bb_mdio_tristate,
+		.set_mdio = io_bb_set_mdio,
+		.get_mdio = io_bb_get_mdio,
+		.set_mdc = io_bb_set_mdc,
+		.delay = io_bb_delay,
+	}
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);
diff --git a/u-boot/board/gdsys/common/osd.c b/u-boot/board/gdsys/common/osd.c
new file mode 100644
index 0000000..4d8c046
--- /dev/null
+++ b/u-boot/board/gdsys/common/osd.c
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include <gdsys_fpga.h>
+
+#define CH7301_I2C_ADDR 0x75
+
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
+#define PIXCLK_640_480_60 25180000
+
+#define BASE_WIDTH 32
+#define BASE_HEIGHT 16
+#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
+
+enum {
+	CH7301_CM = 0x1c,		/* Clock Mode Register */
+	CH7301_IC = 0x1d,		/* Input Clock Register */
+	CH7301_GPIO = 0x1e,		/* GPIO Control Register */
+	CH7301_IDF = 0x1f,		/* Input Data Format Register */
+	CH7301_CD = 0x20,		/* Connection Detect Register */
+	CH7301_DC = 0x21,		/* DAC Control Register */
+	CH7301_HPD = 0x23,		/* Hot Plug Detection Register */
+	CH7301_TCTL = 0x31,		/* DVI Control Input Register */
+	CH7301_TPCP = 0x33,		/* DVI PLL Charge Pump Ctrl Register */
+	CH7301_TPD = 0x34,		/* DVI PLL Divide Register */
+	CH7301_TPVT = 0x35,		/* DVI PLL Supply Control Register */
+	CH7301_TPF = 0x36,		/* DVI PLL Filter Register */
+	CH7301_TCT = 0x37,		/* DVI Clock Test Register */
+	CH7301_TSTP = 0x48,		/* Test Pattern Register */
+	CH7301_PM = 0x49,		/* Power Management register */
+	CH7301_VID = 0x4a,		/* Version ID Register */
+	CH7301_DID = 0x4b,		/* Device ID Register */
+	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
+};
+
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	ihs_i2c_t *i2c = &fpga->i2c;
+
+	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+		;
+	out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
+	out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	ihs_i2c_t *i2c = &fpga->i2c;
+	unsigned int ctr = 0;
+
+	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+		;
+	out_le16(&fpga->extended_interrupt, 1 << 14);
+	out_le16(&i2c->write_mailbox_ext, reg);
+	out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
+	while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
+		udelay(100000);
+		if (ctr++ > 5) {
+			printf("iic receive timeout\n");
+			break;
+		}
+	}
+	return in_le16(&i2c->read_mailbox_ext) >> 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+static void mpc92469ac_calc_parameters(unsigned int fout,
+	unsigned int *post_div, unsigned int *feedback_div)
+{
+	unsigned int n = *post_div;
+	unsigned int m = *feedback_div;
+	unsigned int a;
+	unsigned int b = 14745600 / 16;
+
+	if (fout < 50169600)
+		n = 8;
+	else if (fout < 100339199)
+		n = 4;
+	else if (fout < 200678399)
+		n = 2;
+	else
+		n = 1;
+
+	a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+	m = a / b;
+
+	*post_div = n;
+	*feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	unsigned int n;
+	unsigned int m;
+	unsigned int bitval = 0;
+	mpc92469ac_calc_parameters(fout, &n, &m);
+
+	switch (n) {
+	case 1:
+		bitval = 0x00;
+		break;
+	case 2:
+		bitval = 0x01;
+		break;
+	case 4:
+		bitval = 0x02;
+		break;
+	case 8:
+		bitval = 0x03;
+		break;
+	}
+
+	out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
+}
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+	unsigned int *_mint, unsigned int *_mfrac,
+	unsigned int *_n)
+{
+	unsigned int n;
+	unsigned int foutiic;
+	unsigned int fvcoiic;
+	unsigned int mint;
+	unsigned long long mfrac;
+
+	n = 2550000000U / fout;
+	if ((n & 1) && (n > 5))
+		n -= 1;
+
+	foutiic = fout - (fout / 10000);
+	fvcoiic = foutiic * n;
+
+	mint = fvcoiic / 114285000;
+	if ((mint < 17) || (mint > 63))
+		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+		/ 114285000LL;
+
+	*_mint = mint;
+	*_mfrac = mfrac;
+	*_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int mint;
+	unsigned int mfrac;
+	u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+	ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
+
+	reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+	reg0 |= (mint & 0x1f) << 1;
+	reg0 |= (mfrac >> 17) & 0x01;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+	reg4 = mfrac >> 9;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+	reg8 = mfrac >> 1;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+	reg12 = mfrac << 7;
+	reg12 |= n & 0x7f;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+	reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+	reg18 |= 0x20;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+	reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+	reg20 |= mint & (1 << 5);
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+	u16 *data, size_t charcount)
+{
+	ihs_fpga_t *fpga =
+		(ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	unsigned int k;
+
+	for (k = 0; k < charcount; ++k) {
+		if (offset + k >= BUFSIZE)
+			return -1;
+		out_le16(&fpga->videomem + offset + k, data[k]);
+	}
+
+	return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+
+	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned charcount;
+		unsigned len;
+		u8 color;
+		unsigned int k;
+		u16 buf[BUFSIZE];
+		char *text;
+		int res;
+
+		if (argc < 5) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		color = simple_strtoul(argv[3], NULL, 16);
+		text = argv[4];
+		charcount = strlen(text);
+		len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+		for (k = 0; k < len; ++k)
+			buf[k] = (text[k] << 8) | color;
+
+		res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
+		if (res < 0)
+			return res;
+	}
+
+	return 0;
+}
+
+int osd_probe(unsigned screen)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	ihs_osd_t *osd = &fpga->osd;
+	u16 version = in_le16(&osd->version);
+	u16 features = in_le16(&osd->features);
+	unsigned width;
+	unsigned height;
+	u8 value;
+
+	width = ((features & 0x3f00) >> 8) + 1;
+	height = (features & 0x001f) + 1;
+
+	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+		screen, version/100, version%100, width, height);
+
+#ifdef CONFIG_SYS_CH7301
+	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+	if (value != 0x17) {
+		printf("       Probing CH7301 failed, DID %02x\n", value);
+		return -1;
+	}
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+	mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01
+	ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_SIL1178
+	value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+	if (value != 0x06) {
+		printf("       Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+		return -1;
+	}
+	/* magic initialization sequence adapted from datasheet */
+	fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+#endif
+
+	out_le16(&fpga->videocontrol, 0x0002);
+	out_le16(&osd->control, 0x0049);
+
+	out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
+
+	return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+
+	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned k;
+		u16 buffer[BASE_WIDTH];
+		char *rp;
+		u16 *wp = buffer;
+		unsigned count = (argc > 4) ?
+			simple_strtoul(argv[4], NULL, 16) : 1;
+
+		if ((argc < 4) || (strlen(argv[3]) % 4)) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		rp = argv[3];
+
+
+		while (*rp) {
+			char substr[5];
+
+			memcpy(substr, rp, 4);
+			substr[4] = 0;
+			*wp = simple_strtoul(substr, NULL, 16);
+
+			rp += 4;
+			wp++;
+			if (wp - buffer > BASE_WIDTH)
+				break;
+		}
+
+		for (k = 0; k < count; ++k) {
+			unsigned offset =
+				y * BASE_WIDTH + x + k * (wp - buffer);
+			osd_write_videomem(screen, offset, buffer,
+				wp - buffer);
+		}
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	osdw, 5, 0, osd_write,
+	"write 16-bit hex encoded buffer to osd memory",
+	"pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+	osdp, 5, 0, osd_print,
+	"write ASCII buffer to osd memory",
+	"pos_x pos_y color text\n"
+);
diff --git a/u-boot/board/gdsys/common/osd.h b/u-boot/board/gdsys/common/osd.h
new file mode 100644
index 0000000..c59d9c3
--- /dev/null
+++ b/u-boot/board/gdsys/common/osd.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OSD_H_
+#define _OSD_H_
+
+int osd_probe(unsigned screen);
+
+#endif
diff --git a/u-boot/board/gdsys/dlvision/Makefile b/u-boot/board/gdsys/dlvision/Makefile
new file mode 100644
index 0000000..1c3dadb
--- /dev/null
+++ b/u-boot/board/gdsys/dlvision/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gdsys/dlvision/dlvision.c b/u-boot/board/gdsys/dlvision/dlvision.c
new file mode 100644
index 0000000..3499bdc
--- /dev/null
+++ b/u-boot/board/gdsys/dlvision/dlvision.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+enum {
+	HWTYPE_DLVISION_CPU = 0,
+	HWTYPE_DLVISION_CON = 1,
+};
+
+#define HWREV_100	6
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	/*
+	 * setup io-latches
+	 */
+	out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0);
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002);
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000);
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26);
+	u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36);
+	u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76);
+	u8 unit_type;
+	u8 local_con;
+	u8 audio;
+	u8 hardware_version;
+
+	printf("Board: ");
+
+	unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00;
+	local_con = (channel2_msr & 0x20) ? 0x01 : 0x00;
+	audio = (channel3_msr & 0x20) ? 0x01 : 0x00;
+	hardware_version =
+		  ((channel7_msr & 0x20) ? 0x01 : 0x00)
+		| ((channel7_msr & 0x80) ? 0x02 : 0x00)
+		| ((channel7_msr & 0x40) ? 0x04 : 0x00);
+
+	switch (unit_type) {
+	case HWTYPE_DLVISION_CON:
+		printf("DL-Vision-CON");
+		break;
+
+	case HWTYPE_DLVISION_CPU:
+		printf("DL-Vision-CPU");
+		break;
+
+	default:
+		printf("UnitType %d, unsupported", unit_type);
+		break;
+	}
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (hardware_version) {
+	case HWREV_100:
+		printf("HW-Ver 1.00");
+		break;
+
+	default:
+		printf("HW-Ver %d, unsupported",
+		       hardware_version);
+		break;
+	}
+
+	if (local_con)
+		printf(", local console");
+
+	if (audio)
+		printf(", audio support");
+
+	puts("\n");
+
+	return 0;
+}
diff --git a/u-boot/board/gdsys/gdppc440etx/Makefile b/u-boot/board/gdsys/gdppc440etx/Makefile
new file mode 100644
index 0000000..5b0ffc2
--- /dev/null
+++ b/u-boot/board/gdsys/gdppc440etx/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gdsys/gdppc440etx/config.mk b/u-boot/board/gdsys/gdppc440etx/config.mk
new file mode 100644
index 0000000..5b9543c
--- /dev/null
+++ b/u-boot/board/gdsys/gdppc440etx/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# G&D 440EP/GR ETX-Module
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/gdsys/gdppc440etx/gdppc440etx.c b/u-boot/board/gdsys/gdppc440etx/gdppc440etx.c
new file mode 100644
index 0000000..328eb95
--- /dev/null
+++ b/u-boot/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/yosemite/yosemite.c
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	/*
+	 * Setup the external bus controller/chip selects
+	 */
+	mfebc(EBC0_CFG, reg);
+	mtebc(EBC0_CFG, reg | 0x04000000);		/* Set ATC */
+
+	/*
+	 * Setup the GPIO pins
+	 */
+
+	/* setup Address lines for flash size 64Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
+
+	/* setup emac */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+	/* UART0 and UART1*/
+	out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
+	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
+
+	/* disable boot-eeprom WP */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
+
+	/* external interrupts IRQ0...3 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Setup other serial configuration
+	 */
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
+	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val;
+	uint sz;
+
+	/* Re-do sizing to get full correct info */
+	mfebc(PB0CR, pbcr);
+
+	if (gd->bd->bi_flashsize > 0x08000000)
+		panic("Max. flash banksize is 128 MB!\n");
+
+	for (sz = gd->bd->bi_flashsize, size_val = 7;
+	    ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
+		sz <<= 1;
+
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtebc(PB0CR, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ * Override weak pci_pre_init()
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+	/* First call common code */
+	__pci_pre_init(hose);
+
+	/* enable 66 MHz ext. Clock */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
+	out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
+
+	return 1;
+}
+#endif	/* defined(CONFIG_PCI) */
diff --git a/u-boot/board/gdsys/gdppc440etx/init.S b/u-boot/board/gdsys/gdppc440etx/init.S
new file mode 100644
index 0000000..4a40e4b
--- /dev/null
+++ b/u-boot/board/gdsys/gdppc440etx/init.S
@@ -0,0 +1,76 @@
+/*
+* (C) Copyright 2008
+* Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+*
+* based on board/amcc/yosemite/init.S
+* original Copyright not specified there
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
+     * the speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
+	0, AC_RWX | SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
+	0, AC_RWX | SA_G )
+
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
+	0, AC_RWX | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
+	0, AC_RW | SA_IG )
+
+    /* PCI */
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
+	0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
+	0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
+	0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
+	0, AC_RW | SA_IG )
+
+    tlbtab_end
diff --git a/u-boot/board/gdsys/intip/Makefile b/u-boot/board/gdsys/intip/Makefile
new file mode 100644
index 0000000..4d87ea9
--- /dev/null
+++ b/u-boot/board/gdsys/intip/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	:= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gdsys/intip/chip_config.c b/u-boot/board/gdsys/intip/chip_config.c
new file mode 100644
index 0000000..e46f4d8
--- /dev/null
+++ b/u-boot/board/gdsys/intip/chip_config.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/gdsys/intip/config.mk b/u-boot/board/gdsys/intip/config.mk
new file mode 100644
index 0000000..3923e01
--- /dev/null
+++ b/u-boot/board/gdsys/intip/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2008-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# G&D CompactCenter
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/gdsys/intip/init.S b/u-boot/board/gdsys/intip/init.S
new file mode 100644
index 0000000..7513f1d
--- /dev/null
+++ b/u-boot/board/gdsys/intip/init.S
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/init.S
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+		4, AC_RWX | SA_G) /* TLB 0 */
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+		0, AC_RWX | SA_G)
+#endif
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+		AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for NVRAM */
+	tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for UART */
+	tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for IO */
+	tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+		AC_RWX | SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
+		4, AC_RWX | SA_IG)
+
+	/* AHB: Internal USB Peripherals (USB, SATA) */
+	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
+		AC_RWX | SA_IG)
+
+	tlbtab_end
diff --git a/u-boot/board/gdsys/intip/intip.c b/u-boot/board/gdsys/intip/intip.c
new file mode 100644
index 0000000..aa85ea4
--- /dev/null
+++ b/u-boot/board/gdsys/intip/intip.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/canyonlands.c
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_BCSR3_PCIE		0x10
+
+int board_early_init_f(void)
+{
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * enable GPIO 49-63
+	 * UART0: 4 pins
+	 */
+	mtsdr(SDR0_PFC0, 0x00007fff);
+	mtsdr(SDR0_PFC1, 0x00040000);
+
+	/* Enable PCI host functionality in SDR0_PCI0 */
+	mtsdr(SDR0_PCI0, 0xe0000000);
+
+	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	/*
+	* Configure USB-STP pins as alternate and not GPIO
+	* It seems to be neccessary to configure the STP pins as GPIO
+	* input at powerup (perhaps while USB reset is asserted). So
+	* we configure those pins to their "real" function now.
+	*/
+	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+	/* Trigger board component reset */
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+	udelay(50);
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
+	udelay(50);
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+
+	return 0;
+}
+
+int get_cpu_num(void)
+{
+	int cpu = NA_OR_UNKNOWN_CPU;
+
+	return cpu;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+#ifdef CONFIG_DEVCONCENTER
+	printf("Board: DevCon-Center");
+#else
+	printf("Board: Intip");
+#endif
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
+	 * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
+	 * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfn00.0000 -> 4.cn00.0000
+	 */
+
+	u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
+		EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
+
+	/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
+	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
+		| bxcr_bw
+		| EBC_BXCR_BU_RW
+		| EBC_BXCR_BW_16BIT);
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+	u32 eth_cfg;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	/* disable SGMII mode */
+	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+		     SDR0_ETH_CFG_SGMII1_ENABLE |
+		     SDR0_ETH_CFG_SGMII0_ENABLE);
+	/* Set the for 2 RGMII mode */
+	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	__ft_board_setup(blob, bd);
+
+	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+			     "disabled", sizeof("disabled"), 1);
+
+	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+			     "disabled", sizeof("disabled"), 1);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/gdsys/neo/Makefile b/u-boot/board/gdsys/neo/Makefile
new file mode 100644
index 0000000..1c3dadb
--- /dev/null
+++ b/u-boot/board/gdsys/neo/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gdsys/neo/neo.c b/u-boot/board/gdsys/neo/neo.c
new file mode 100644
index 0000000..a56c2cc
--- /dev/null
+++ b/u-boot/board/gdsys/neo/neo.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2007-2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#define HWTYPE_CCX16	1
+#define HWREV_300	3
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
+	u8 unit_type;
+	u8 hardware_cpu_ports;
+	u8 hardware_con_ports;
+	u8 hardware_version;
+
+	printf("Board: CATCenter Neo");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	unit_type = (val & 0xf000) >> 12;
+	hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
+	hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
+	hardware_version = val & 0x000f;
+
+	switch (unit_type) {
+	case HWTYPE_CCX16:
+		printf("CCX16-FPGA (80 UARTs)");
+		break;
+
+	default:
+		printf("UnitType %d, unsupported", unit_type);
+		break;
+	}
+
+	printf(", %d cpu ports, %d console ports,",
+	       hardware_cpu_ports, hardware_con_ports);
+
+	switch (hardware_version) {
+	case HWREV_300:
+		printf(" HW-Ver 3.00\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d, unsupported\n",
+		       hardware_version);
+		break;
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/gen860t/Makefile b/u-boot/board/gen860t/Makefile
new file mode 100644
index 0000000..5853626
--- /dev/null
+++ b/u-boot/board/gen860t/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o beeper.o fpga.o ioport.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gen860t/README b/u-boot/board/gen860t/README
new file mode 100644
index 0000000..e20680d
--- /dev/null
+++ b/u-boot/board/gen860t/README
@@ -0,0 +1,144 @@
+This directory contains board specific code for a generic MPC860T based
+embedded computer, called 'GEN860T'.  The design is generic in the sense that
+common, readily available components are used and that the architecture of the
+system is relatively straightforward:
+
+	One eight bit wide boot (FLASH) memory
+	32 bit main memory using SDRAM
+	DOC 2000+
+	Ethernet PHY
+	Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC.
+	Some other miscellaneous peripherals
+
+NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this
+port.  I guess the computer is not as generic as I first said 8)  However,
+these extras can be safely ignored.
+
+Given the GEN860T files, it should be pretty easy to reverse engineer the
+hardware configuration, if that's useful to you.  Hopefully, this code will
+be useful to someone as a basis for a port to a new system or as a head start
+on a custom design.  If you end up using any of this, I would appreciate
+hearing from you, especially if you discover bugs or find ways to improve the
+quality of this U-Boot port.
+
+Here are the salient features of the system:
+Clock						:	33.3 Mhz oscillator
+Processor core frequency	:	66.6 Mhz  if in 1:2:1 mode; can also run 1:1
+Bus frequency				:	33.3 Mhz
+
+Main memory:
+	Type	: SDRAM
+	Width	: 32 bits
+	Size	: 64 mibibytes
+	Chip	: Two Micron MT48LC16M16A2TG-7E
+	CS		: MPC860T CS1*/UPMA
+	UPMA CONNECTIONS:
+		SDRAM A10	: GPLA0*
+		SDRAM CAS*	: GPLA2*
+		SDRAM WE*	: GPLA3*
+		SDRAM RAS*	: GPLA4*
+
+Boot memory:
+	Type	: FLASH
+	Width	: 8 bits
+	Size	: 16 mibibytes
+	Chip	: One Intel 28F128J3A (StrataFlash)
+	CS		: MPC860T CS0*/GPCM (this is the "boot" chip select)
+
+EEPROM memory:
+	Type	: Serial I2C EEPROM
+	Width	: 8 bits
+	Size	: 32 kibibytes
+	Chip	: One Atmel AT25C256
+	CS		: 0x50 (external I2C address pins on device are tied to GND)
+
+Filesystem memory:
+	Type	: NAND FLASH (Toshiba)
+	Width	: 8 bits (i.e. interface to DOC is 8 bits)
+	Size	: 32 mibibytes
+	Chip	: One DiskOnCHip Millenium Plus (DOC 2000+)
+	CS		: MPC860T CS2*/GPCM
+
+Network support:
+	MAC		: MPC86OT FEC (Fast Ethernet Controller)
+	PHY		: Intel LXT971A
+	MII Addr: 0x0 (hardwired on the board)
+	MII IRQ	:
+
+Console:
+	RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter)
+
+Real Time Clock:
+	Type	: Low power, I2C interface
+	Chip	: Maxim DS1337
+	CS		: Address 0x68 on I2C bus
+
+	The MPC860T's internal RTC has a defect in Mask rev D that increases
+	the current drain on the KAPWR line to 10 mA.  Since this is an
+	unreasonable amount of current draw for a RTC, and Motorola does not
+	plan to fix this in future mask revisions, a serial (I2C) RTC that
+	works has been included instead.  NOTE that the DS1337 can be
+	configured to output a 32768 Hz clock while the main power is on.
+	This clock output has been routed to the MPC860T's EXTAL pin to allow
+	the internal RTC to be used.  NOTE also that due to yet another
+	defect in the rev D mask, the RTC does not operate reliably when the
+	internal RTC divisor is set to use a 32768 Hz reference.  So just use
+	the I2C RTC.
+
+Miscellaneous:
+	Xilinx Virtex FPGA on CS3*/GPCM.
+	Virtex FPGA slave SelectMap interface on cs4*/UPMB.
+	Mil-Std 1553 databus interface on CS5*/GPCM.
+	Audio sounder (beeper) with digital volume control connected to SPKROUT.
+
+SC variant:
+	A reduced-feature version of the GEN860T port is also supported: GEN860T_SC.
+	The 'SC' variant only provides support for the Virtex FPGA, SDRAM main
+	memory, EEPROM and flash memory.  The system clock frequency is reduced
+	to 24 MHz.
+
+Issues:
+	The DOC 2000+ returns 0x40 as its device ID when probed using the method
+	desxribed in the DOC datasheet.  Unfortunately, the U-Boot DOC driver
+	does not recognize this device.  As of this writing, it seems that MTD
+	does not support the DOC 2000+ either.
+
+Status:
+	Everything appears to work except DOC support. As of this writing,
+	David Woodhouse has stated on the MTD mailing list that he has no
+	knowledge of the DOC Millineum Plus and therfore there is no support
+	in MTD for this device.  I wish I had known this sooner :(
+
+The GEN860T board specific files and configuration is based on the work
+of others who have contributed to U-Boot. The copyright and license notices
+of these authors have been retained wherever their code has been reused.
+All new code to support the GEN860T board is:
+
+	(C) Copyright 2001-2003
+	Keith Outwater (keith_outwater@mvis.com)
+
+and the following license applies:
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License as
+published by the Free Software Foundation; either version 2 of
+the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+MA 02111-1307 USA
+
+Thanks to Wolfgang Denk for a great software package and to everyone
+who contributed to its development.
+
+Keith Outwater
+Sr. Staff Engineer
+Microvision, Inc.
+<keith_outwater@mvis.com>
+<outwater@eskimo.com>
diff --git a/u-boot/board/gen860t/beeper.c b/u-boot/board/gen860t/beeper.c
new file mode 100644
index 0000000..c6be83f
--- /dev/null
+++ b/u-boot/board/gen860t/beeper.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2002
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <linux/ctype.h>
+
+/*
+ * Basic beeper support for the GEN860T board.  The GEN860T includes
+ * an audio sounder driven by a Phillips TDA8551 amplifier.  The
+ * TDA8551 features a digital volume control which uses a "trinary"
+ * input (high/high-Z/low) to set volume.  The 860's SPKROUT pin
+ * drives the amplifier input.
+ */
+
+/*
+ * Initialize beeper-related hardware. Initialize timer 1 for use with
+ * the beeper. Use 66 MHz internal clock with prescale of 33 to get
+ * 1 uS period per count.
+ * FIXME: we should really compute the prescale based on the reported
+ * core clock frequency.
+ */
+void init_beeper (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
+	immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
+		| TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN;
+	immap->im_cpmtimer.cpmt_tcn1 = 0;
+	immap->im_cpmtimer.cpmt_ter1 = 0xffff;
+	immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
+}
+
+/*
+ * Set beeper frequency.  Max allowed frequency is 2.5 KHz.  This limit
+ * is mostly arbitrary, but the beeper isn't really much good beyond this
+ * frequency.
+ */
+void set_beeper_frequency (uint frequency)
+{
+#define FREQ_LIMIT	2500
+
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	/*
+	 * Compute timer ticks given desired frequency.  The timer is set up
+	 * to count 0.5 uS per tick and it takes two ticks per cycle (Hz).
+	 */
+	if (frequency > FREQ_LIMIT)
+		frequency = FREQ_LIMIT;
+	frequency = 1000000 / frequency;
+	immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency;
+}
+
+/*
+ * Turn the beeper on
+ */
+void beeper_on (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
+}
+
+/*
+ * Turn the beeper off
+ */
+void beeper_off (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
+}
+
+/*
+ * Increase or decrease the beeper volume.  Volume can be set
+ * from off to full in 64 steps.  To increase volume, the output
+ * pin is actively driven high, then returned to tristate.
+ * To decrease volume, output a low on the port pin (no need to
+ * change pin mode to tristate) then output a high to go back to
+ * tristate.
+ */
+void set_beeper_volume (int steps)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	int i;
+
+	if (steps >= 0) {
+		for (i = 0; i < (steps >= 64 ? 64 : steps); i++) {
+			immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19);
+			udelay (1);
+			immap->im_cpm.cp_pbodr |= (0x80000000 >> 19);
+			udelay (1);
+		}
+	} else {
+		for (i = 0; i > (steps <= -64 ? -64 : steps); i--) {
+			immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19);
+			udelay (1);
+			immap->im_cpm.cp_pbdat |= (0x80000000 >> 19);
+			udelay (1);
+		}
+	}
+}
+
+/*
+ * Check the environment to see if the beeper needs beeping.
+ * Controlled by a sequence of the form:
+ * freq/delta volume/on time/off time;... where:
+ * freq			= frequency in Hz (0 - 2500)
+ * delta volume = volume steps up or down (-64 <= vol <= 64)
+ * on time		= time in mS
+ * off time		= time in mS
+ *
+ * Return 1 on success, 0 on failure
+ */
+int do_beeper (char *sequence)
+{
+#define DELIMITER	';'
+
+	int args[4];
+	int i;
+	int val;
+	char *p = sequence;
+	char *tp;
+
+	/*
+	 * Parse the control sequence.  This is a really simple parser
+	 * without any real error checking.  You can probably blow it
+	 * up really easily.
+	 */
+	if (*p == '\0' || !isdigit (*p)) {
+		printf ("%s:%d: null or invalid string (%s)\n",
+			__FILE__, __LINE__, p);
+		return 0;
+	}
+
+	i = 0;
+	while (*p != '\0') {
+		while (*p != DELIMITER) {
+			if (i > 3)
+				i = 0;
+			val = (int) simple_strtol (p, &tp, 0);
+			if (tp == p) {
+				printf ("%s:%d: no digits or bad format\n",
+					__FILE__, __LINE__);
+				return 0;
+			} else {
+				args[i] = val;
+			}
+
+			i++;
+			if (*tp == DELIMITER)
+				p = tp;
+			else
+				p = ++tp;
+		}
+		p++;
+
+		/*
+		 * Well, we got something that has a chance of being correct
+		 */
+#if 0
+		for (i = 0; i < 4; i++) {
+			printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i,
+				args[i]);
+		}
+		printf ("\n");
+#endif
+		set_beeper_frequency (args[0]);
+		set_beeper_volume (args[1]);
+		beeper_on ();
+		udelay (1000 * args[2]);
+		beeper_off ();
+		udelay (1000 * args[3]);
+	}
+	return 1;
+}
diff --git a/u-boot/board/gen860t/beeper.h b/u-boot/board/gen860t/beeper.h
new file mode 100644
index 0000000..125b90f
--- /dev/null
+++ b/u-boot/board/gen860t/beeper.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2002
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void init_beeper(void);
+void set_beeper_frequency(uint frequency);
+void beeper_on(void);
+void beeper_off(void);
+void set_beeper_volume(int steps);
+int do_beeper(char *sequence);
diff --git a/u-boot/board/gen860t/flash.c b/u-boot/board/gen860t/flash.c
new file mode 100644
index 0000000..827d9e0
--- /dev/null
+++ b/u-boot/board/gen860t/flash.c
@@ -0,0 +1,644 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvsi.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*
+ * Use buffered writes to flash by default - they are about 32x faster than
+ * single byte writes.
+ */
+#ifndef  CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
+#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
+#endif
+
+/*
+ * Max time to wait (in mS) for flash device to allocate a write buffer.
+ */
+#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT
+#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT		100
+#endif
+
+/*
+ * These functions support a single Intel StrataFlash device (28F128J3A)
+ * in byte mode only!.  The flash routines are very basic and simple
+ * since there isn't really any remapping necessary.
+ */
+
+/*
+ * Intel SCS (Scalable Command Set) command definitions
+ * (taken from 28F128J3A datasheet)
+ */
+#define SCS_READ_CMD				0xff
+#define SCS_READ_ID_CMD				0x90
+#define SCS_QUERY_CMD				0x98
+#define SCS_READ_STATUS_CMD			0x70
+#define SCS_CLEAR_STATUS_CMD		0x50
+#define SCS_WRITE_BUF_CMD			0xe8
+#define SCS_PROGRAM_CMD				0x40
+#define SCS_BLOCK_ERASE_CMD			0x20
+#define SCS_BLOCK_ERASE_RESUME_CMD	0xd0
+#define SCS_PROGRAM_RESUME_CMD		0xd0
+#define SCS_BLOCK_ERASE_SUSPEND_CMD	0xb0
+#define SCS_SET_BLOCK_LOCK_CMD		0x60
+#define SCS_CLR_BLOCK_LOCK_CMD		0x60
+
+/*
+ * SCS status/extended status register bit definitions
+ */
+#define  SCS_SR7					0x80
+#define  SCS_XSR7					0x80
+
+/*---------------------------------------------------------------------*/
+#if 0
+#define DEBUG_FLASH
+#endif
+
+#ifdef DEBUG_FLASH
+#define PRINTF(fmt,args...) printf(fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data8 (flash_info_t *info, ulong dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ * Initialize the flash memory.
+ */
+unsigned long
+flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/*
+	 * The gen860t board only has one FLASH memory device, so the
+	 * FLASH Bank configuration is done statically.
+	 */
+	PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM);
+	size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+				"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+				flash_info[0].flash_id,size_b0, size_b0 << 20);
+	}
+
+	PRINTF("## Before remap:\n"
+		   "  BR0: 0x%08x    OR0: 0x%08x\n  BR1: 0x%08x    OR1: 0x%08x\n",
+		   memctl->memc_br0, memctl->memc_or0,
+		   memctl->memc_br1, memctl->memc_or1);
+
+	/*
+	 * Remap FLASH according to real size
+	 */
+	memctl->memc_or0 |= (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK);
+
+	PRINTF("## After remap:\n"
+		   "  BR0: 0x%08x    OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0);
+
+	/*
+	 * Re-do sizing to get full correct info
+	 */
+	size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/*
+	 * Monitor protection is ON by default
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+			  CONFIG_SYS_MONITOR_BASE,
+			  CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			  &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/*
+	 * Environment protection ON by default
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+			  CONFIG_ENV_ADDR,
+			  CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			  &flash_info[0]);
+#endif
+
+	PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0);
+	return (size_b0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Fill in the FLASH offset table
+ */
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:
+		for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 1024 * 128;
+		}
+		return;
+
+		default:
+			printf ("Don't know sector offsets for FLASH"
+			        " type 0x%lx\n", info->flash_id);
+	    return;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * Display FLASH device info
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+			printf ("Intel ");
+			break;
+	default:
+			printf ("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+			printf ("28F128J3A (128Mbit = 128K x 128)\n");
+			break;
+	default:
+			printf ("Unknown Chip Type\n");
+			break;
+	}
+
+	if (info->size >= (1024 * 1024)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+			info->size >> i,
+			(i == 20) ? 'M' : 'k',
+			info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Get size and other information for a FLASH device.
+ * NOTE: The following code cannot be run from FLASH!
+ */
+static
+ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+#define NO_FLASH	0
+
+	vu_char value[2];
+
+	/*
+	 * Try to read the manufacturer ID
+	 */
+	addr[0] = SCS_READ_CMD;
+	addr[0] = SCS_READ_ID_CMD;
+	value[0] = addr[0];
+	value[1] = addr[2];
+	addr[0] = SCS_READ_CMD;
+
+	PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]);
+	switch (value[0]) {
+		case (INTEL_MANUFACT & 0xff):
+			info->flash_id = FLASH_MAN_INTEL;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (NO_FLASH);
+	}
+
+	/*
+	 * Read the device ID
+	 */
+	PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]);
+	switch (value[1]) {
+		case (INTEL_ID_28F128J3A & 0xff):
+			info->flash_id += FLASH_28F128J3A;
+			info->sector_count = 128;
+			info->size = 16 * 1024 * 1024;
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (NO_FLASH);
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+				info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Erase the specified sectors in the specified FLASH device
+ */
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	/*
+	 * Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_char *addr = (uchar *)(info->start[sect]);
+			vu_char status;
+
+			/*
+			 * Disable interrupts which might cause a timeout
+			 */
+			flag = disable_interrupts();
+
+			*addr = SCS_CLEAR_STATUS_CMD;
+			*addr = SCS_BLOCK_ERASE_CMD;
+			*addr = SCS_BLOCK_ERASE_RESUME_CMD;
+
+			/*
+			 * Re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts();
+
+			/*
+			 * Wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			while (((status = *addr) & SCS_SR7) != SCS_SR7) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = SCS_BLOCK_ERASE_SUSPEND_CMD;
+					*addr = SCS_READ_CMD;
+					return 1;
+				}
+
+				/*
+				 * Show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* 1 second */
+					putc ('.');
+					last = now;
+				}
+			}
+			*addr = SCS_READ_CMD;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+
+#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
+/*
+ * Allocate a flash buffer, fill it with data and write it to the flash.
+ * 0 - OK
+ * 1 - Timeout on buffer request
+ *
+ * NOTE: After the last call to this function, WSM status needs to be checked!
+ */
+static int
+write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p,
+				    uint count)
+{
+	vu_char *block_addr_p = NULL;
+	vu_char *start_addr_p = NULL;
+	ulong blocksize = info_p->size / (ulong)info_p->sector_count;
+
+	int i;
+	uint time = get_timer(0);
+
+	PRINTF("%s:%d: src: 0x%p dest: 0x%p  count: %d\n",
+		   __FUNCTION__, __LINE__, src_p, dest_p, count);
+
+	/*
+	 * What block are we in? We already know that the source address is
+	 * in the flash address range, but we also can't cross a block boundary.
+	 * We assume that the block does not cross a boundary (we'll check before
+	 * calling this function).
+	 */
+	for (i = 0; i < info_p->sector_count; ++i) {
+		if ( ((ulong)dest_p >= info_p->start[i]) &&
+		    ((ulong)dest_p < (info_p->start[i] + blocksize)) ) {
+			PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n",
+				   __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]);
+			block_addr_p = (vu_char *)info_p->start[i];
+			break;
+		}
+	}
+
+	/*
+	 * Request a buffer
+	 */
+	*block_addr_p = SCS_WRITE_BUF_CMD;
+	while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) {
+		if (get_timer(time) >  CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) {
+			PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n",
+				   __FUNCTION__, __LINE__, block_addr_p,
+				   CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT);
+			return 1;
+		}
+		*block_addr_p = SCS_WRITE_BUF_CMD;
+	}
+
+	/*
+	 * Fill the buffer with data
+	 */
+	start_addr_p = dest_p;
+	*block_addr_p = count - 1; /* flash device wants count - 1 */
+	PRINTF("%s:%d: Fill buffer at block addr 0x%p\n",
+		   __FUNCTION__, __LINE__, block_addr_p);
+	for (i = 0; i < count; i++) {
+		*start_addr_p++ = *src_p++;
+	}
+
+	/*
+	 * Flush buffer to flash
+	 */
+	*block_addr_p = SCS_PROGRAM_RESUME_CMD;
+#if 1
+	time = get_timer(0);
+	while ((*block_addr_p & SCS_SR7) != SCS_SR7) {
+		if (get_timer(time) >  CONFIG_SYS_FLASH_WRITE_TOUT) {
+			PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n",
+				   __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT);
+			return 1;
+		}
+	}
+
+#endif
+	return 0;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count)
+{
+	int rc = 0;
+#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
+#define FLASH_WRITE_BUF_SIZE	0x00000020	/* 32 bytes */
+	int i;
+	uint bufs;
+	ulong buf_count;
+	vu_char *sp;
+	vu_char *dp;
+#else
+	ulong wp;
+#endif
+
+	PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n",
+		   __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count);
+
+	if (info_p->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
+	sp = src_p;
+	dp = (uchar *)addr;
+
+	/*
+	 * For maximum performance, we want to align the start address to
+	 * the beginning of a write buffer boundary (i.e. A4-A0 of the
+	 * start address = 0). See how many bytes are required to get to a
+	 * write-buffer-aligned address.  If that number is non-zero, do
+	 * non buffered writes of the non-aligned data.  By doing non-buffered
+	 * writes, we avoid the problem of crossing a block (sector) boundary
+	 * with buffered writes.
+	 */
+	buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1));
+	if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */
+		buf_count = 0;
+	}
+	if (buf_count > count) { /* not a full buffers worth of data to write */
+		buf_count = count;
+	}
+	count -= buf_count;
+
+	PRINTF("%s:%d: Write buffer alignment count = %ld\n",
+		   __FUNCTION__, __LINE__, buf_count);
+	while (buf_count-- >= 1) {
+		if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0)  {
+			return (rc);
+		}
+	}
+
+	PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count);
+	if (count == 0) { /* all done */
+		PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n",
+			   __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE);
+		return (rc);
+	}
+
+	/*
+	 * Now that we are write buffer aligned, write full or partial buffers.
+	 * The fact that we are write buffer aligned automatically avoids
+	 * crossing a block address during a write buffer operation.
+	 */
+	bufs = count / FLASH_WRITE_BUF_SIZE;
+	PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__,
+		   bufs, bufs);
+	while (bufs >= 1) {
+		rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE);
+		if (rc != 0) {
+			PRINTF("%s:%d: ** Error writing buf %d\n",
+				   __FUNCTION__, __LINE__, bufs);
+			return (rc);
+		}
+		bufs--;
+		sp += FLASH_WRITE_BUF_SIZE;
+		dp += FLASH_WRITE_BUF_SIZE;
+	}
+
+	/*
+	 * Do the leftovers
+	 */
+	i = count % FLASH_WRITE_BUF_SIZE;
+	PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i);
+	if (i > 0) {
+		rc = write_flash_buffer8(info_p, sp, dp, i);
+	}
+
+	sp = (vu_char*)info_p->start[0];
+	*sp = SCS_READ_CMD;
+	return (rc);
+
+#else
+	wp = addr;
+	while (count-- >= 1) {
+		if((rc = write_data8(info_p, wp++, *src_p++)) != 0)
+			return (rc);
+	}
+	return 0;
+#endif
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_data8 (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)dest;
+	vu_char status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = SCS_PROGRAM_CMD;
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & SCS_SR7) != SCS_SR7) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = SCS_READ_CMD;
+			return (1);
+		}
+	}
+	*addr = SCS_READ_CMD;
+	return (0);
+}
+
+/* vim: set ts=4 sw=4 tw=78: */
diff --git a/u-boot/board/gen860t/fpga.c b/u-boot/board/gen860t/fpga.c
new file mode 100644
index 0000000..d42c500
--- /dev/null
+++ b/u-boot/board/gen860t/fpga.c
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the GEN860T computer
+ */
+
+#include <common.h>
+#include <virtex2.h>
+#include <command.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#if 0
+#define GEN860T_FPGA_DEBUG
+#endif
+
+#ifdef GEN860T_FPGA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+/*
+ * Port bit numbers for the Selectmap controls
+ */
+#define FPGA_INIT_BIT_NUM		22	/* PB22 */
+#define FPGA_RESET_BIT_NUM		11	/* PC11 */
+#define FPGA_DONE_BIT_NUM		16	/* PB16 */
+#define FPGA_PROGRAM_BIT_NUM	7	/* PA7  */
+
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ */
+Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_init_fn,
+	fpga_err_fn,
+	fpga_done_fn,
+	fpga_clk_fn,
+	fpga_cs_fn,
+	fpga_wr_fn,
+	fpga_read_data_fn,
+	fpga_write_data_fn,
+	fpga_busy_fn,
+	fpga_abort_fn,
+	fpga_post_config_fn
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	{Xilinx_Virtex2,
+	 slave_selectmap,
+	 XILINX_XC2V3000_SIZE,
+	 (void *) &fpga_fns,
+	 0}
+};
+
+/*
+ * Display FPGA revision information
+ */
+void print_fpga_revision (void)
+{
+	vu_long *rev_p = (vu_long *) 0x60000008;
+
+	printf ("FPGA Revision 0x%.8lx"
+		" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
+		*rev_p,
+		((*rev_p >> 28) & 0xf),
+		((*rev_p >> 20) & 0xff),
+		((*rev_p >> 12) & 0xff),
+		((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
+}
+
+
+/*
+ * Perform a simple test of the FPGA to processor interface using the FPGA's
+ * inverting bus test register.  The great thing about doing a read/write
+ * test on a register that inverts it's contents is that you avoid any
+ * problems with bus charging.
+ * Return 0 on failure, 1 on success.
+ */
+int test_fpga_ibtr (void)
+{
+	vu_long *ibtr_p = (vu_long *) 0x60000010;
+	vu_long readback;
+	vu_long compare;
+	int i;
+	int j;
+	int k;
+	int pass = 1;
+
+	static const ulong bitpattern[] = {
+		0xdeadbeef,	/* magic ID pattern for debug   */
+		0x00000001,	/* single bit                                   */
+		0x00000003,	/* two adjacent bits                    */
+		0x00000007,	/* three adjacent bits                  */
+		0x0000000F,	/* four adjacent bits                   */
+		0x00000005,	/* two non-adjacent bits                */
+		0x00000015,	/* three non-adjacent bits              */
+		0x00000055,	/* four non-adjacent bits               */
+		0xaaaaaaaa,	/* alternating 1/0                              */
+	};
+
+	for (i = 0; i < 1024; i++) {
+		for (j = 0; j < 31; j++) {
+			for (k = 0;
+			     k < sizeof (bitpattern) / sizeof (bitpattern[0]);
+			     k++) {
+				*ibtr_p = compare = (bitpattern[k] << j);
+				readback = *ibtr_p;
+				if (readback != ~compare) {
+					printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
+					pass = 0;
+					break;
+				}
+			}
+			if (!pass)
+				break;
+		}
+		if (!pass)
+			break;
+	}
+	if (pass) {
+		printf ("FPGA inverting bus test passed\n");
+		print_fpga_revision ();
+	} else {
+		printf ("** FPGA inverting bus test failed\n");
+	}
+	return pass;
+}
+
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void fpga_reset (int assert)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	if (assert) {
+		immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
+		PRINTF ("deasserted\n");
+	}
+}
+
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void fpga_selectmap_init (void)
+{
+	PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
+		__LINE__);
+	fpga_pgm_fn (FALSE, FALSE, 0);	/* make sure program pin is inactive */
+}
+
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int gen860t_init_fpga (void)
+{
+	int i;
+
+	PRINTF ("%s:%d: Initialize FPGA interface\n",
+		__FUNCTION__, __LINE__);
+	fpga_init ();
+	fpga_selectmap_init ();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_xilinx, &fpga[i]);
+	}
+	return 1;
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int fpga_pgm_fn (int assert, int flush, int cookie)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		immap->im_ioport.iop_padat &=
+			~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_padat |=
+			(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("deasserted\n");
+	}
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn (int cookie)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
+		PRINTF ("high\n");
+		return 0;
+	} else {
+		PRINTF ("low\n");
+		return 1;
+	}
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn (int cookie)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
+		PRINTF ("high\n");
+		return FPGA_SUCCESS;
+	} else {
+		PRINTF ("low\n");
+		return FPGA_FAIL;
+	}
+}
+
+
+/*
+ * Read FPGA SelectMap data.
+ */
+int fpga_read_data_fn (unsigned char *data, int cookie)
+{
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
+
+	*data = *p;
+#if 0
+	PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
+#endif
+	return (int) data;
+}
+
+
+/*
+ * Write data to the FPGA SelectMap port
+ */
+int fpga_write_data_fn (unsigned char data, int flush, int cookie)
+{
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
+
+#if 0
+	PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
+#endif
+	*p = data;
+	return (int) data;
+}
+
+
+/*
+ * Abort and FPGA operation
+ */
+int fpga_abort_fn (int cookie)
+{
+	PRINTF ("%s:%d: FPGA program sequence aborted\n",
+		__FUNCTION__, __LINE__);
+	return FPGA_FAIL;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int fpga_pre_config_fn (int cookie)
+{
+	PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int fpga_post_config_fn (int cookie)
+{
+	int rc;
+
+	PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	udelay (1000);
+	fpga_reset (FALSE);
+	udelay (1000);
+
+	/*
+	 * Use the FPGA,s inverting bus test register to do a simple test of the
+	 * processor interface.
+	 */
+	rc = test_fpga_ibtr ();
+	return rc;
+}
+
+
+/*
+ * Clock, chip select and write signal assert functions and error check
+ * and busy functions.  These are only stubs because the GEN860T selectmap
+ * interface handles sequencing of control signals automatically (it uses
+ * a memory-mapped interface to the FPGA SelectMap port).  The design of
+ * the interface guarantees that the SelectMap port cannot be overrun so
+ * no busy check is needed.  A configuration error is signalled by INIT
+ * going low during configuration, so there is no need for a separate error
+ * function.
+ */
+int fpga_clk_fn (int assert_clk, int flush, int cookie)
+{
+	return assert_clk;
+}
+
+int fpga_cs_fn (int assert_cs, int flush, int cookie)
+{
+	return assert_cs;
+}
+
+int fpga_wr_fn (int assert_write, int flush, int cookie)
+{
+	return assert_write;
+}
+
+int fpga_err_fn (int cookie)
+{
+	return 0;
+}
+
+int fpga_busy_fn (int cookie)
+{
+	return 0;
+}
+#endif
diff --git a/u-boot/board/gen860t/fpga.h b/u-boot/board/gen860t/fpga.h
new file mode 100644
index 0000000..18deb73
--- /dev/null
+++ b/u-boot/board/gen860t/fpga.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the GEN860T computer
+ */
+
+extern int gen860t_init_fpga(void);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
diff --git a/u-boot/board/gen860t/gen860t.c b/u-boot/board/gen860t/gen860t.c
new file mode 100644
index 0000000..d175858
--- /dev/null
+++ b/u-boot/board/gen860t/gen860t.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <virtex2.h>
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include "beeper.h"
+#include "fpga.h"
+#include "ioport.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
+#include <net.h>
+#endif
+
+#if 0
+#define GEN860T_DEBUG
+#endif
+
+#ifdef GEN860T_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+/*
+ * The following UPM init tables were generated automatically by
+ * Motorola's MCUINIT program. See the README file for UPM to
+ * SDRAM pin assignments if you want to type this data into
+ * MCUINIT in order to reverse engineer the waveforms.
+ */
+
+/*
+ * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
+ * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
+ * NOTE that unused areas of the table are used to hold NOP, precharge
+ * and mode register set sequences.
+ *
+ */
+#define	UPMA_NOP_ADDR			0x5
+#define	UPMA_PRECHARGE_ADDR		0x6
+#define UPMA_MRS_ADDR			0x12
+
+#define UPM_SINGLE_READ_ADDR	0x00
+#define UPM_BURST_READ_ADDR		0x08
+#define UPM_SINGLE_WRITE_ADDR	0x18
+#define UPM_BURST_WRITE_ADDR	0x20
+#define	UPM_REFRESH_ADDR		0x30
+
+const uint sdram_upm_table[] = {
+	/* single read   (offset 0x00 in upm ram) */
+	0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
+	0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
+	/* burst read    (offset 0x08 in upm ram) */
+	0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
+	0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
+	0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
+	0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
+	/* single write  (offset 0x18 in upm ram) */
+	0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* burst write   (offset 0x20 in upm ram) */
+	0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
+	0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* refresh       (offset 0x30 in upm ram) */
+	0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
+	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* exception     (offset 0x3C in upm ram) */
+};
+
+const uint selectmap_upm_table[] = {
+	/* single read   (offset 0x00 in upm ram) */
+	0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
+	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* burst read    (offset 0x08 in upm ram) */
+	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* single write  (offset 0x18 in upm ram) */
+	0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* burst write   (offset 0x20 in upm ram) */
+	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* refresh       (offset 0x30 in upm ram) */
+	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* exception     (offset 0x3C in upm ram) */
+	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+/*
+ * Check board identity.  Always successful (gives information only)
+ */
+int checkboard (void)
+{
+	char *s;
+	char buf[64];
+	int i;
+
+	i = getenv_f("board_id", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
+
+	if (s) {
+		printf ("%s ", s);
+	} else {
+		printf ("<unknown> ");
+	}
+
+	i = getenv_f("serial#", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
+
+	if (s) {
+		printf ("S/N %s\n", s);
+	} else {
+		printf ("S/N <unknown>\n");
+	}
+
+	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
+	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
+	return (0);
+}
+
+/*
+ * Initialize SDRAM
+ */
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	upmconfig (UPMA,
+		   (uint *) sdram_upm_table,
+		   sizeof (sdram_upm_table) / sizeof (uint)
+		);
+
+	/*
+	 * Setup MAMR register
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	/*
+	 * Map CS1* to SDRAM bank
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
+
+	/*
+	 * Perform SDRAM initialization sequence:
+	 * 1. Apply at least one NOP command
+	 * 2. 100 uS delay (JEDEC standard says 200 uS)
+	 * 3. Issue 4 precharge commands
+	 * 4. Perform two refresh cycles
+	 * 5. Program mode register
+	 *
+	 * Program SDRAM for standard operation, sequential burst, burst length
+	 * of 4, CAS latency of 2.
+	 */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
+	udelay (200);
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
+
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (2) | UPM_REFRESH_ADDR;
+
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (1) | UPMA_MRS_ADDR;
+
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
+	/*
+	 * Enable refresh
+	 */
+	memctl->memc_mamr |= MAMR_PTAE;
+
+	return (SDRAM_SIZE);
+}
+
+/*
+ * Disk On Chip (DOC) Millenium initialization.
+ * The DOC lives in the CS2* space
+ */
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	printf ("Probing at 0x%.8x: ", DOC_BASE);
+	doc_probe (DOC_BASE);
+}
+#endif
+
+/*
+ * Miscellaneous intialization
+ */
+int misc_init_r (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	/*
+	 * Set up UPMB to handle the Virtex FPGA SelectMap interface
+	 */
+	upmconfig (UPMB, (uint *) selectmap_upm_table,
+		   sizeof (selectmap_upm_table) / sizeof (uint));
+
+	memctl->memc_mbmr = 0x0;
+
+	config_mpc8xx_ioports (immr);
+
+#if defined(CONFIG_CMD_MII)
+	mii_init ();
+#endif
+
+#if defined(CONFIG_FPGA)
+	gen860t_init_fpga ();
+#endif
+	return 0;
+}
+
+/*
+ * Final init hook before entering command loop.
+ */
+int last_stage_init (void)
+{
+#if !defined(CONFIG_SC)
+	char buf[256];
+	int i;
+
+	/*
+	 * Turn the beeper volume all the way down in case this is a warm boot.
+	 */
+	set_beeper_volume (-64);
+	init_beeper ();
+
+	/*
+	 * Read the environment to see what to do with the beeper
+	 */
+	i = getenv_f("beeper", buf, sizeof (buf));
+	if (i > 0) {
+		do_beeper (buf);
+	}
+#endif
+	return 0;
+}
+
+/*
+ * Stub to make POST code happy.  Can't self-poweroff, so just hang.
+ */
+void board_poweroff (void)
+{
+	puts ("### Please power off the board ###\n");
+	while (1);
+}
diff --git a/u-boot/board/gen860t/ioport.c b/u-boot/board/gen860t/ioport.c
new file mode 100644
index 0000000..8d46925
--- /dev/null
+++ b/u-boot/board/gen860t/ioport.c
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include "ioport.h"
+
+#if 0
+#define IOPORT_DEBUG
+#endif
+
+#ifdef  IOPORT_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+/*
+ * The ioport configuration table.
+ */
+const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
+    /*
+	 * Port A configuration
+	 * Pin	Signal					Type	Active	Initial state
+	 * PA7	fpgaProgramLowOut		Out		Low			High
+	 * PA1	fpgaCoreVoltageFailLow	In		Low			N/A
+	 */
+    {	/*	    conf ppar psor pdir podr pdat pint	   function		*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
+	/* PA15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA11 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA10 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA9  */ { 1,   0,   0,   1,   0,   0,   0 }, /* grn bicolor LED 1*/
+	/* PA8  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 1*/
+	/* PA7  */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaProgramLow	*/
+	/* PA6  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA5  */ { 1,   0,   0,   1,   0,   0,   0 }, /* grn bicolor LED 0*/
+	/* PA4  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 0*/
+	/* PA3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA2  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PA1  */ { 1,   0,   0,   0,   0,   0,   0 }, /*	fpgaCoreVoltageFail*/
+#else
+	/* PA1  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
+	/* PA0  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+    },
+
+	/*
+	 * Port B configuration
+	 * Pin		Signal			Type		Active		Initial state
+	 * PB14		docBusyLowIn	In			Low			X
+	 * PB15		gpio1Sig		Out			High		Low
+	 * PB16		fpgaDoneBi		In			High		X
+	 * PB17		swBitOkLowOut	Out			Low			High
+	 * PB19		speakerVolSig	Out/Hi-Z	High/Low	High (Hi-Z)
+	 * PB22		fpgaInitLowBi	In			Low			X
+	 * PB23		batteryOkSig	In			High		X
+	 * PB31		pulseCatcherClr	Out			High		0
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint	  function			*/
+#if !defined(CONFIG_SC)
+	/* PB31 */ { 0,	  0,   0,   0,   0,   0,   0 }, /*	*/
+#else
+	/* PB31 */ { 1,   0,   0,   1,   0,   0,   0 }, /* pulseCatcherClr	*/
+#endif
+	/* PB30 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB29 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB28 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB27 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB26 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB25 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB24 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PB23 */ { 1,   0,   0,   0,   0,   0,   0 }, /* batteryOk		*/
+#else
+	/* PB23 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
+	/* PB22 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaInitLowBi	*/
+	/* PB21 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB20 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PB19 */ { 1,   0,   0,   1,   1,   1,   0 }, /* speakerVol		*/
+#else
+	/* PB19 */ { 0,   0,   0,   1,   1,   1,   0 }, /*	*/
+#endif
+	/* PB18 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB17 */ { 1,   0,   0,   1,   0,   1,   0 }, /* swBitOkLow		*/
+	/* PB16 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaDone			*/
+	/* PB15 */ { 1,   0,   0,   1,   0,   0,   0 }, /* gpio1			*/
+#if !defined(CONFIG_SC)
+	/* PB14 */ { 1,   0,   0,   0,   0,   0,   0 }  /* docBusyLow		*/
+#else
+	/* PB14 */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+#endif
+	},
+
+	/*
+	 * Port C configuration
+	 * Pin		Signal				Type	Active		Initial state
+	 * PC4		i2cBus1EnSig		Out		High		High
+	 * PC5		i2cBus2EnSig		Out		High		High
+	 * PC6		gpio0Sig			Out		High		Low
+	 * PC8		i2cBus3EnSig		Out		High		High
+	 * PC10		i2cBus4EnSig		Out		High		High
+	 * PC11		fpgaResetLowOut		Out		Low			High
+	 * PC12		systemBitOkIn		In		High		X
+	 * PC15		selfDreqLow			In		Low			X
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint	  function			*/
+	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PC15 */ { 1,   0,   0,   0,   0,   0,   0 }, /* selfDreqLowIn	*/
+	/* PC14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PC13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PC12 */ { 1,   0,   0,   0,   0,   0,   0 }, /* systemBitOkIn	*/
+#else
+	/* PC12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
+	/* PC11 */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaResetLowOut	*/
+#if !defined(CONFIG_SC)
+	/* PC10 */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus4EnSig		*/
+#else
+	/* PC10 */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
+	/* PC9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PC8  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus3EnSig		*/
+#else
+	/* PC8  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
+	/* PC7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PC6  */ { 1,   0,   0,   1,   0,   1,   0 }, /* gpio0			*/
+#if !defined(CONFIG_SC)
+	/* PC5  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus2EnSig		*/
+	/* PC4  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus1EnSig		*/
+#else
+	/* PC5  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+	/* PC4  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+	},
+
+	/*
+	 * Port D configuration
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint	   function			*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD11 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD10 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD8  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD6  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD5  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD4  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+	}
+};
+
+/*
+ * Configure the MPC8XX I/O ports per the ioport configuration table
+ * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c)
+ */
+void config_mpc8xx_ioports (volatile immap_t * immr)
+{
+	int portnum;
+
+	for (portnum = 0; portnum < NUM_PORTS; portnum++) {
+		uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
+		uint podr = 0, pdat = 0, pint = 0;
+		uint msk = 1;
+		mpc8xx_iop_conf_t *iopc =
+			(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
+		mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;
+
+		/*
+		 * For all ports except port B, ignore the two don't care entries
+		 * in the configuration tables.
+		 */
+		if (portnum != 1) {
+			iopc = (mpc8xx_iop_conf_t *) &
+				iop_conf_tab[portnum][2];
+		}
+
+		/*
+		 * NOTE: index 0 refers to pin 17, index 17 refers to pin 0
+		 */
+		while (iopc < eiopc) {
+			if (iopc->conf) {
+				pmsk |= msk;
+				if (iopc->ppar)
+					ppar |= msk;
+				if (iopc->psor)
+					psor |= msk;
+				if (iopc->pdir)
+					pdir |= msk;
+				if (iopc->podr)
+					podr |= msk;
+				if (iopc->pdat)
+					pdat |= msk;
+				if (iopc->pint)
+					pint |= msk;
+			}
+			msk <<= 1;
+			iopc++;
+		}
+
+		PRINTF ("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__,
+			portnum);
+#ifdef IOPORT_DEBUG
+		switch (portnum) {
+		case 0:
+			printf ("(A)\n");
+			break;
+		case 1:
+			printf ("(B)\n");
+			break;
+		case 2:
+			printf ("(C)\n");
+			break;
+		case 3:
+			printf ("(D)\n");
+			break;
+		default:
+			printf ("(?)\n");
+			break;
+		}
+#endif
+		PRINTF ("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
+			"  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
+			ppar, pdir, podr, pdat, psor, pint, pmsk);
+
+		/*
+		 * Have to handle the ioports on a port-by-port basis since there
+		 * are three different flavors.
+		 */
+		if (pmsk != 0) {
+			uint tpmsk = ~pmsk;
+
+			if (0 == portnum) {	/* port A */
+				immr->im_ioport.iop_papar &= tpmsk;
+				immr->im_ioport.iop_padat =
+					(immr->im_ioport.
+					 iop_padat & tpmsk) | pdat;
+				immr->im_ioport.iop_padir =
+					(immr->im_ioport.
+					 iop_padir & tpmsk) | pdir;
+				immr->im_ioport.iop_paodr =
+					(immr->im_ioport.
+					 iop_paodr & tpmsk) | podr;
+				immr->im_ioport.iop_papar |= ppar;
+			} else if (1 == portnum) {	/* port B */
+				immr->im_cpm.cp_pbpar &= tpmsk;
+				immr->im_cpm.cp_pbdat =
+					(immr->im_cpm.
+					 cp_pbdat & tpmsk) | pdat;
+				immr->im_cpm.cp_pbdir =
+					(immr->im_cpm.
+					 cp_pbdir & tpmsk) | pdir;
+				immr->im_cpm.cp_pbodr =
+					(immr->im_cpm.
+					 cp_pbodr & tpmsk) | podr;
+				immr->im_cpm.cp_pbpar |= ppar;
+			} else if (2 == portnum) {	/* port C */
+				immr->im_ioport.iop_pcpar &= tpmsk;
+				immr->im_ioport.iop_pcdat =
+					(immr->im_ioport.
+					 iop_pcdat & tpmsk) | pdat;
+				immr->im_ioport.iop_pcdir =
+					(immr->im_ioport.
+					 iop_pcdir & tpmsk) | pdir;
+				immr->im_ioport.iop_pcint =
+					(immr->im_ioport.
+					 iop_pcint & tpmsk) | pint;
+				immr->im_ioport.iop_pcso =
+					(immr->im_ioport.
+					 iop_pcso & tpmsk) | psor;
+				immr->im_ioport.iop_pcpar |= ppar;
+			} else if (3 == portnum) {	/* port D */
+				immr->im_ioport.iop_pdpar &= tpmsk;
+				immr->im_ioport.iop_pddat =
+					(immr->im_ioport.
+					 iop_pddat & tpmsk) | pdat;
+				immr->im_ioport.iop_pddir =
+					(immr->im_ioport.
+					 iop_pddir & tpmsk) | pdir;
+				immr->im_ioport.iop_pdpar |= ppar;
+			}
+		}
+	}
+
+	PRINTF ("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
+		"  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
+		immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
+	PRINTF ("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
+		"  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
+		immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
+		immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
+	PRINTF ("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
+		"  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
+		__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
+		immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
+		immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
+	PRINTF ("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
+		"  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
+		immr->im_ioport.iop_pddat);
+}
diff --git a/u-boot/board/gen860t/ioport.h b/u-boot/board/gen860t/ioport.h
new file mode 100644
index 0000000..3af0bc9
--- /dev/null
+++ b/u-boot/board/gen860t/ioport.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define NUM_PORTS	4
+#define PORT_BITS	18
+
+/*
+ * This structure provides configuration information for one port pin.
+ * We include all fields needed to initialize any of the ioports.
+ */
+typedef struct {
+    unsigned char conf:1;	/* If 1, configure this port		*/
+    unsigned char ppar:1;	/* Port Pin Assignment Register		*/
+    unsigned char psor:1;	/* Port Special Options Register	*/
+    unsigned char pdir:1;	/* Port Data Direction Register		*/
+    unsigned char podr:1;	/* Port Open Drain Register			*/
+    unsigned char pdat:1;	/* Port Data Register				*/
+    unsigned char pint:1;	/* Port Interrupt Register			*/
+} mpc8xx_iop_conf_t;
+
+extern void config_mpc8xx_ioports(volatile immap_t *immr);
diff --git a/u-boot/board/gen860t/u-boot-flashenv.lds b/u-boot/board/gen860t/u-boot-flashenv.lds
new file mode 100644
index 0000000..cda6c47
--- /dev/null
+++ b/u-boot/board/gen860t/u-boot-flashenv.lds
@@ -0,0 +1,107 @@
+/*
+ * Linker command file for the GEN860T board when the environment is
+ * stored in flash memory.
+ *
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /*
+   * Read-only sections, merged into text segment:
+   */
+  . = + SIZEOF_HEADERS;
+  .text :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /*
+   * Read-write section, merged into data segment:
+   */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data:
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+
+  .ppcenv:
+  {
+    . = env_offset;
+    common/env_embedded.o
+  }
+}
diff --git a/u-boot/board/gen860t/u-boot.lds b/u-boot/board/gen860t/u-boot.lds
new file mode 100644
index 0000000..1729c17
--- /dev/null
+++ b/u-boot/board/gen860t/u-boot.lds
@@ -0,0 +1,100 @@
+/*
+ * Linker command file for the GEN860T board.
+ *
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /*
+   * Read-only sections, merged into text segment:
+   */
+  . = + SIZEOF_HEADERS;
+  .text :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /*
+   * Read-write section, merged into data segment:
+   */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/genietv/Makefile b/u-boot/board/genietv/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/genietv/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/genietv/flash.c b/u-boot/board/genietv/flash.c
new file mode 100644
index 0000000..5313ad8
--- /dev/null
+++ b/u-boot/board/genietv/flash.c
@@ -0,0 +1,469 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	/* Detect size */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* Setup offsets */
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	size_b1 = 0 ;
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Fix this to support variable sector sizes
+*/
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK)
+	{
+		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	if (info->size >> 20) {
+	    printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+	} else {
+	    printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10,
+		info->sector_count);
+	}
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	putc ('\n');
+	return;
+}
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr;
+	char value;
+
+	caddr = (volatile unsigned char *)addr ;
+
+	/* Write auto select command: read Manufacturer ID */
+
+#if 0
+	printf("Base address is: %08x\n", caddr);
+#endif
+
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	value = caddr[0];
+
+#if 0
+	printf("Manufact ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case 0x1: /* AMD_MANUFACT */
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case 0x4: /* FUJ_MANUFACT */
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = caddr[1];			/* device ID		*/
+#if 0
+	printf("Device ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;				/* => 512Kb		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		caddr = (volatile unsigned char *)info->start[0];
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile unsigned char *)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+
+	while ((addr[0] & 0xFF) != 0xFF)
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
+				*cdest,*cdata;
+	ulong start;
+	int flag, count = 4 ;
+
+	cdest = (volatile unsigned char *)dest ;
+	cdata = (volatile unsigned char *)&data ;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	while(count--)
+	{
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    addr[0x0555] = 0xAA;
+	    addr[0x02AA] = 0x55;
+	    addr[0x0555] = 0xA0;
+
+	    *cdest = *cdata;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((*cdest ^ *cdata) & 0x80)
+	    {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	    }
+
+	    cdata++ ;
+	    cdest++ ;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/genietv/genietv.c b/u-boot/board/genietv/genietv.c
new file mode 100644
index 0000000..0a015ea
--- /dev/null
+++ b/u-boot/board/genietv/genietv.c
@@ -0,0 +1,360 @@
+/*
+ * genietv/genietv.c
+ *
+ * The GENIETV is using the following physical memorymap (copied from
+ * the FADS configuration):
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * 02800000 -> 0287ffff : flash      connected to CS0
+ * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
+ *
+ * CS pins are connected as follows:
+ *
+ * CS0 -512Kb boot flash
+ * CS1 - SDRAM #1
+ * CS2 - SDRAM #2
+ * CS3 - Flash #1
+ * CS4 - Flash #2
+ * CS5 - LON (if present)
+ * CS6 - PCMCIA #1
+ * CS7 - PCMCIA #2
+ *
+ * Ports are configured as follows:
+ *
+ * PA7 - SDRAM banks enable
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define CONFIG_SYS_PA7		0x0100
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMB RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00,
+	0x1FFDDC47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMB RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMB RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMB RAM)
+	 */
+	0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMB RAM)
+	 */
+	0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMB RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMB RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity
+ */
+
+int checkboard (void)
+{
+	puts ("Board: GenieTV\n");
+	return 0;
+}
+
+#if 0
+static void PrintState (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &im->im_memctl;
+
+	printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
+		memctl->memc_or0);
+	printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
+		memctl->memc_or1);
+	printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
+		memctl->memc_or2);
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &im->im_memctl;
+	long int size_b0, size_b1, size8;
+
+	/* Enable SDRAM */
+
+	/* Configuring PA7 for general purpouse output pin */
+	im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7;	/* 0 = general purpouse */
+	im->im_ioport.iop_padir |= CONFIG_SYS_PA7;	/* 1 = output */
+
+	/* Enable SDRAM - PA7 = 1 */
+	im->im_ioport.iop_padat |= CONFIG_SYS_PA7;	/* value of PA7 */
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;
+
+	upmconfig (UPMB, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+
+	memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 =
+		((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
+
+	memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br2 =
+		((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
+
+	/* perform SDRAM initialization sequence */
+	memctl->memc_mar = 0x00000088;
+
+	memctl->memc_mcr = 0x80802105;	/* SDRAM bank 0 */
+
+	memctl->memc_mcr = 0x80804105;	/* SDRAM bank 1 */
+
+	/* Execute refresh 8 times */
+	memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
+
+	memctl->memc_mcr = 0x80802130;	/* SDRAM bank 0 - execute twice */
+
+	memctl->memc_mcr = 0x80804130;	/* SDRAM bank 1 - execute twice */
+
+	/* Execute refresh 4 times */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+
+#if 0
+	PrintState ();
+#endif
+/*    printf ("\nChecking bank1..."); */
+	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	size_b0 = size8;
+
+/*    printf ("\nChecking bank2..."); */
+	size_b1 =
+		dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+
+	if (size_b1 > 0) {
+		/*
+		 * Position Bank 1 immediately above Bank 0
+		 */
+		memctl->memc_or2 =
+			((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+			((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
+			(size_b0 & BR_BA_MSK);
+	} else {
+		/*
+		 * No bank 1
+		 *
+		 * invalidate bank
+		 */
+		memctl->memc_br2 = 0;
+		/* adjust refresh rate depending on SDRAM type, one bank */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
+	}
+
+	/* If no memory detected, disable SDRAM */
+	if ((size_b0 + size_b1) == 0) {
+		printf ("disabling SDRAM!\n");
+		/* Disable SDRAM - PA7 = 1 */
+		im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7;	/* value of PA7 */
+	}
+/*	else */
+/*    printf("done! (%08lx)\n", size_b0 + size_b1); */
+
+#if 0
+	PrintState ();
+#endif
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mbmr_value, long int *base,
+			   long int maxsize)
+{
+	long size;
+
+	/*memctl->memc_mbmr = mbmr_value; */
+
+	size = get_ram_size (base, maxsize);
+
+	if (size) {
+/*      printf("(%08lx)", size); */
+	} else {
+		printf ("(0)");
+	}
+
+	return (size);
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+
+#ifdef	CONFIG_SYS_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init (void)
+{
+	volatile pcmconf8xx_t *pcmp;
+	uint v, slota, slotb;
+
+	/*
+	 ** Enable the PCMCIA for a Flash card.
+	 */
+	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
+
+#if 0
+	pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
+	pcmp->pcmc_por0 = 0xc00ff05d;
+#endif
+
+	/* Set all slots to zero by default. */
+	pcmp->pcmc_pgcra = 0;
+	pcmp->pcmc_pgcrb = 0;
+#ifdef PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0x40;
+#endif
+#ifdef PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0x40;
+#endif
+
+	/* Check if any PCMCIA card is luged in. */
+	slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
+	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
+
+	if (!(slota || slotb)) {
+		printf ("No card present\n");
+#ifdef PCMCIA_SLOT_A
+		pcmp->pcmc_pgcra = 0;
+#endif
+#ifdef PCMCIA_SLOT_B
+		pcmp->pcmc_pgcrb = 0;
+#endif
+		return -1;
+	} else
+		printf ("Unknown card (");
+
+	v = 0;
+
+	switch ((pcmp->pcmc_pipr >> 14) & 3) {
+	case 0x00:
+		printf ("5V");
+		v = 5;
+		break;
+	case 0x01:
+		printf ("5V and 3V");
+		v = 3;
+		break;
+	case 0x03:
+		printf ("5V, 3V and x.xV");
+		v = 3;
+		break;
+	}
+
+	switch (v) {
+	case 3:
+		printf ("; using 3V");
+		/* Enable 3 volt Vcc. */
+
+		break;
+
+	default:
+		printf ("; unknown voltage");
+		return -1;
+	}
+	printf (")\n");
+	/* disable pcmcia reset after a while */
+
+	udelay (20);
+
+	pcmp->pcmc_pgcrb = 0;
+
+	/* If you using a real hd you should give a short
+	 * spin-up time. */
+#ifdef CONFIG_DISK_SPINUP_TIME
+	udelay (CONFIG_DISK_SPINUP_TIME);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/genietv/genietv.h b/u-boot/board/genietv/genietv.h
new file mode 100644
index 0000000..7c95b56
--- /dev/null
+++ b/u-boot/board/genietv/genietv.h
@@ -0,0 +1,25 @@
+/*
+ * The GENIETV is using the following physical memorymap (copied from
+ * the FADS configuration):
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * 02800000 -> 0287ffff : flash      connected to CS0
+ * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
+ *
+ * CS pins are connected as follows:
+ *
+ * CS0 -512Kb boot flash
+ * CS1 - SDRAM #1
+ * CS2 - SDRAM #2
+ * CS3 - Flash #1
+ * CS4 - Flash #2
+ * CS5 - LON (if present)
+ * CS6 - PCMCIA #1
+ * CS7 - PCMCIA #2
+ *
+ * Ports are configured as follows:
+ *
+ * PA7 - SDRAM banks enable
+ */
diff --git a/u-boot/board/genietv/u-boot.lds b/u-boot/board/genietv/u-boot.lds
new file mode 100644
index 0000000..6b45ea0
--- /dev/null
+++ b/u-boot/board/genietv/u-boot.lds
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    lib/libgeneric.o			(.text*)
+    net/libnet.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    board/genietv/libgenietv.o		(.text*)
+    arch/powerpc/lib/libpowerpc.o	(.text*)
+    *(.text.do_load_serial*)
+    *(.text.do_mem_*)
+    *(.text.do_bootm*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/env_embedded.o (.ppcenv)
+  }
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/genietv/u-boot.lds.debug b/u-boot/board/genietv/u-boot.lds.debug
new file mode 100644
index 0000000..60936aa
--- /dev/null
+++ b/u-boot/board/genietv/u-boot.lds.debug
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    arch/powerpc/lib/ppcstring.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/env_embedded.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/goldelico/beagle-expander/Makefile b/u-boot/board/goldelico/beagle-expander/Makefile
new file mode 100644
index 0000000..f75a580
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= beagleexpander.o ../gta04b2/COM37H3M05DTC.o ../gta04b2/trf7960.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/beagle-expander/beagleexpander.c b/u-boot/board/goldelico/beagle-expander/beagleexpander.c
new file mode 100644
index 0000000..bd58b1f
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/beagleexpander.c
@@ -0,0 +1,24 @@
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "../../ti/beagle/beagle.h"
+#include "beagleexpander.h"
+
+// make us initialize using both pinmux sets
+
+void muxinit(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_EXPANDER();
+}
+
+#undef MUX_BEAGLE
+#define MUX_BEAGLE() muxinit()
+
+// take the original beagle.c code
+#include "../../ti/beagle/beagle.c"
diff --git a/u-boot/board/goldelico/beagle-expander/beagleexpander.h b/u-boot/board/goldelico/beagle-expander/beagleexpander.h
new file mode 100644
index 0000000..049d999
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/beagleexpander.h
@@ -0,0 +1,30 @@
+// all pins on BB expansion connector
+
+// GPIO -> BB-Pin -> Expander function
+
+#define MUX_BEAGLE_EXPANDER() \
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M1)) /*GPIO_130 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | EN  | M4)) /*GPIO_130 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | EN  | M1)) /*GPIO_131 -> MCSPI3-SIMO -> TRF*/\
+MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | EN  | M4)) /*GPIO_131 -> MCSPI3-SIMO -> TRF*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M1)) /*GPIO_132 -> MCSPI3-SOMI -> TRF*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132 -> MCSPI3-SOMI -> TRF*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133 -> UART3-RX (software)*/\
+MUX_VAL(CP(MMC2_DAT2),		(IDIS | PTU | EN  | M4)) /*GPIO_134 -> UART3-TX (software)*/\
+MUX_VAL(CP(MMC2_DAT3),		(IDIS | PTU | EN  | M1)) /*GPIO_135 -> MCSPI3-CS0*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTD | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTU | EN  | M4)) /*GPIO_138 - UART3-RTS (software) */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - UART3-CTS (software) */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | EN  | M4)) /*GPIO_143 - UART2-RX */\
+MUX_VAL(CP(UART2_CTS),		(IDIS | PTU | EN  | M4)) /*GPIO_144 - UART2-CTS */\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTU | EN  | M4)) /*GPIO_145 - UART2-RTS */\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTU | EN  | M4)) /*GPIO_146 - UART2-TX */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | EN  | M4)) /*GPIO_156 - KEYIRQ -> TRF IRQ */\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - Display STBY */\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | EN  | M4)) /*GPIO_159 - McBSP1-DR -> TRF EN2 */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS */\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | EN  | M4)) /*GPIO_161 - McBSP1-FSX -> TRF EN */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - McBSP1-CLKX -> UART3 Powerdown */
+
diff --git a/u-boot/board/goldelico/beagle-expander/config.mk b/u-boot/board/goldelico/beagle-expander/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-expander/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/beagle-hybrid/Makefile b/u-boot/board/goldelico/beagle-hybrid/Makefile
new file mode 100644
index 0000000..d249281
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= beaglehyb.o ../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/beagle-hybrid/beaglehyb.c b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.c
new file mode 100644
index 0000000..7fbe8d2
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.c
@@ -0,0 +1,24 @@
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "../../ti/beagle/beagle.h"
+#include "beaglehyb.h"
+
+// make us initialize using both pinmux sets
+
+void muxinit(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_HYBRID();
+}
+
+#undef MUX_BEAGLE
+#define MUX_BEAGLE() muxinit()
+
+// take the original beagle.c code
+#include "../../ti/beagle/beagle.c"
diff --git a/u-boot/board/goldelico/beagle-hybrid/beaglehyb.h b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.h
new file mode 100644
index 0000000..71470f8
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/beaglehyb.h
@@ -0,0 +1,18 @@
+#define MUX_BEAGLE_HYBRID() \
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | DIS  | M4)) /*GPIO_138 - EXT-ANT */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - RS232 EXT */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - DOUT */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M4)) /*GPIO_159 - DIN - pulled up */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M4)) /*GPIO_161 - CS */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - SCL */
diff --git a/u-boot/board/goldelico/beagle-hybrid/config.mk b/u-boot/board/goldelico/beagle-hybrid/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/beagle-hybrid/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/gta04/COMMANDS b/u-boot/board/goldelico/gta04/COMMANDS
new file mode 100644
index 0000000..01fa68e
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/COMMANDS
@@ -0,0 +1,22 @@
+new uBoot commands:
+
+status in[it]		setup GPIOs
+status ge[t]		get button status
+status se[t] hh		set LEDs to lower 4 bit
+status se[t]		increment last state, i.e. make LEDs count
+status mi[rror]		read button status and mirror to LEDs until a key is pressed
+status bl[ink]		blink LEDs
+
+lcm in[it]			initialize subsystem (DSS, GPIOs etc.)
+lcm ba[cklight] dd	set backlight level (0..255)
+lcm po[wer] dd		set power level (0..2)
+lcm on				set lcm on
+lcm of[f]			set lcm off
+
+gps on | of[f]		control GPS receiver (and initialize UART)
+gps re[ad]			read GPS NMEA from UART until a key is pressed
+
+tsc init			initialize/enable TSC2007 through I2C2
+tsc get				read current ADC values (incl. internal temp and AUX/photosensor)
+tsc lo[op]			read x/y coordinates
+tsc ch[oose]		somehow allow to define receptive fields and use the result to select different boot options
diff --git a/u-boot/board/goldelico/gta04/Makefile b/u-boot/board/goldelico/gta04/Makefile
new file mode 100644
index 0000000..5afd6df
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= gta04.o ../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o  ../gta04/systest.o ../gta04/commands.o ../gta04/i2c1-fix.o ../gta04/ulpi-phy.o  ../gta04/twl4030-additions.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/gta04/TD028TTEC1.c b/u-boot/board/goldelico/gta04/TD028TTEC1.c
new file mode 100644
index 0000000..94667a3
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/TD028TTEC1.c
@@ -0,0 +1,260 @@
+/* u-boot driver for the tpo TD028TTEC1 LCM
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* modified by hns@goldelico.com
+ * now is just a SPI/GPIO driver to the serial interface of the TD028TTEC1
+ 
+ *** should all this code be moved to drivers/misc or drivers/video ?
+ 
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "TD028TTEC1.h"
+
+#ifdef CONFIG_OMAP3_BEAGLE
+
+#ifdef CONFIG_OMAP3_GTA04
+
+#define GPIO_CS		19
+#define GPIO_SCL	12
+#define GPIO_DIN	18
+#define GPIO_DOUT	20
+
+#else	/* Beagle Hybrid */
+
+#define GPIO_CS		161
+#define GPIO_SCL	162
+#define GPIO_DIN	159
+#define GPIO_DOUT	158
+
+#endif
+
+#define SPI_READ()      (omap_get_gpio_datain(GPIO_DIN))
+#define SPI_CS(bit) 	(omap_set_gpio_dataout(GPIO_CS, bit))
+#define SPI_SDA(bit)    (omap_set_gpio_dataout(GPIO_DOUT, bit))
+#define SPI_SCL(bit)    (omap_set_gpio_dataout(GPIO_SCL, bit))
+
+#elif !defined(CONFIG_GTA02_REVISION)	/* GTA01 */
+
+#define GTA01_SCLK	(1 << 7) 	/* GPG7 */
+#define GTA01_MOSI	(1 << 6)	/* GPG6 */
+#define GTA01_MISO	(1 << 5)	/* GPG5 */
+#define GTA01_CS	(1 << 3)	/* GPG3 */
+
+#define SPI_READ        ((immr->GPGDAT & GTA01_MISO) != 0)
+
+#define SPI_CS(bit) 	if (bit) gpio->GPGDAT |= GTA01_CS; \
+			else gpio->GPGDAT &= ~GTA01_CS
+
+#define SPI_SDA(bit)    if (bit) gpio->GPGDAT |=  GTA01_MOSI; \
+			else    gpio->GPGDAT &= ~GTA01_MOSI
+
+#define SPI_SCL(bit)    if (bit) gpio->GPGDAT |=  GTA01_SCLK; \
+			else    gpio->GPGDAT &= ~GTA01_SCLK
+
+#else /* GTA02 */
+
+extern void smedia3362_spi_cs(int);
+extern void smedia3362_spi_sda(int);
+extern void smedia3362_spi_scl(int);
+extern void smedia3362_lcm_reset(int);
+
+#define SPI_READ	$not$implemented$
+#define SPI_CS(b)   smedia3362_spi_cs(b)
+#define SPI_SDA(b)  smedia3362_spi_sda(b)
+#define SPI_SCL(b)  smedia3362_spi_scl(b)
+   
+#endif
+
+
+/* 150uS minimum clock cycle, we have two of this plus our other
+ * instructions */
+
+#define SPI_DELAY()	udelay(150)
+
+static int jbt_spi_xfer(int wordnum, int bitlen, u_int16_t *dout)
+{
+#if !defined(_BEAGLE_)
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+#endif
+	u_int16_t tmpdout = 0;
+	int   i, j;
+
+//	DEBUGP("spi_xfer: dout %08X wordnum %u bitlen %d\n",
+//		*(uint *)dout, wordnum, bitlen);
+
+	SPI_CS(0);
+
+	for (i = 0; i < wordnum; i ++) {
+		tmpdout = dout[i];
+
+		for (j = 0; j < bitlen; j++) {
+			SPI_SCL(0);
+			if (tmpdout & (1 << (bitlen-1))) {
+				SPI_SDA(1);
+//				DEBUGPC("1");
+//				VERIFY(1);
+			} else {
+				SPI_SDA(0);
+//				DEBUGPC("0");
+//				VERIFY(0);
+			}
+			SPI_DELAY();
+			SPI_SCL(1);
+			SPI_DELAY();
+			tmpdout <<= 1;
+		}
+//		DEBUGPC(" ");
+	}
+//	DEBUGPC("\n");
+
+	SPI_CS(1);
+
+	return 0;
+}
+
+#define JBT_COMMAND	0x000
+#define JBT_DATA	0x100
+
+int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg)
+{
+	int rc;
+	
+	jbt->tx_buf[0] = JBT_COMMAND | reg;
+	
+	rc = jbt_spi_xfer(1, 9, jbt->tx_buf);
+	
+	return rc;
+}
+
+
+int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data)
+{
+	int rc;
+	
+	jbt->tx_buf[0] = JBT_COMMAND | reg;
+	jbt->tx_buf[1] = JBT_DATA | data;
+	
+	rc = jbt_spi_xfer(2, 9, jbt->tx_buf);
+	
+	return rc;
+}
+
+int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data)
+{
+	int rc;
+	
+	jbt->tx_buf[0] = JBT_COMMAND | reg;
+	jbt->tx_buf[1] = JBT_DATA | (data >> 8);
+	jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
+	
+	rc = jbt_spi_xfer(3, 9, jbt->tx_buf);
+	
+	return rc;
+}
+
+int jbt_check(void)
+{ // check if we have connectivity
+#if defined(_BEAGLE_)
+	int err;
+	int i;
+	int failed=0;
+	int cnt0 = 0;
+	int cnt1 = 0;
+
+#if 0
+	printf("jbt_reg_init()\n");
+#endif
+	err = omap_request_gpio(GPIO_CS);
+	SPI_CS(1);	// unselect
+	err |= omap_request_gpio(GPIO_SCL);
+	SPI_SCL(1);	// default
+	err |= omap_request_gpio(GPIO_DOUT);
+	SPI_SDA(0);
+	err |= omap_request_gpio(GPIO_DIN);
+	if(err)
+		{
+		printf("jbt_reg_init() - could not get GPIOs\n");
+		return 1;
+		}
+#if 1		// should have already been done by MUX settings!
+	omap_set_gpio_direction(GPIO_CS, 0);	// output
+	omap_set_gpio_direction(GPIO_SCL, 0);	// output
+	omap_set_gpio_direction(GPIO_DOUT, 0);	// output
+	omap_set_gpio_direction(GPIO_DIN, 1);	// input (for reading back)
+#endif
+	
+	//	omap_free_gpio(GPIO_DIN);
+	//	omap_free_gpio(GPIO_DOUT);
+	//	omap_free_gpio(GPIO_CS);
+	//	omap_free_gpio(GPIO_SCL);
+	
+	for(i=0; i<16; i++)
+		{ // check for connection between GPIO158 -> GPIO159; since we have 10 kOhm pse. make sure that the PUP/PDN is disabled on DIN in the MUX config!
+			int bit=i&1;
+			SPI_SDA(bit);	// write bit
+			SPI_DELAY();
+#if 0
+			printf("bit: %d out: %d in: %d (%d)\n", bit, omap_get_gpio_datain(GPIO_DOUT), omap_get_gpio_datain(GPIO_DIN), SPI_READ());
+#endif
+			if(SPI_READ() != bit)	// did not read back
+				failed++;
+			if(SPI_READ())
+				cnt1++;
+			else
+				cnt0++;
+		}	
+	if(failed > 0)
+		{
+		printf("DISPLAY:    ");
+		if(cnt0 == 0)
+			printf("DIN (GPIO%d) stuck at 0\n", GPIO_DIN);
+		else if(cnt1 == 0)
+			printf("DIN (GPIO%d) stuck at 1\n", GPIO_DIN);
+		else 
+			printf("DIN-DOUT (GPIO%d- (GPIO%d)) connetion broken\n", GPIO_DIN, GPIO_DOUT);
+		return 1;
+		}
+#endif
+	return 0;
+}
+
+int jbt_reg_init(void)
+{
+	
+	if(jbt_check())
+		return 1;	// some error
+	/* according to data sheet: wait 50ms (Tpos of LCM). However, 50ms
+	 * seems unreliable with later LCM batches, increasing to 90ms */
+	udelay(90000);
+	printf("did jbt_reg_init()\n");
+	return 0;
+}
+
+
diff --git a/u-boot/board/goldelico/gta04/TD028TTEC1.h b/u-boot/board/goldelico/gta04/TD028TTEC1.h
new file mode 100644
index 0000000..19bcc07
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/TD028TTEC1.h
@@ -0,0 +1,22 @@
+#ifndef _TD028TTEC1_H
+#define _TD028TTEC1_H
+
+#define _BEAGLE_
+
+#define JBT_TX_BUF_SIZE
+struct jbt_info {
+	u_int16_t tx_buf[4];
+	struct spi_device *spi_dev;
+	int state;
+};
+
+#define JBT_COMMAND	0x000
+#define JBT_DATA	0x100
+
+int jbt_reg_init(void);
+int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg);
+int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data);
+int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data);
+int jbt_check(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/backlight.c b/u-boot/board/goldelico/gta04/backlight.c
new file mode 100644
index 0000000..76b6e43
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/backlight.c
@@ -0,0 +1,113 @@
+/* u-boot driver for the GTA04 backlight
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "backlight.h"
+
+#if defined(CONFIG_OMAP3_GTA04)
+
+#define GPIO_BACKLIGHT		57	/* = GPT11_PWM */
+#define GPT_BACKLIGHT		OMAP34XX_GPT11
+
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+
+#define GPIO_BACKLIGHT		145	/* = GPT10_PWM */
+#define GPT_BACKLIGHT		OMAP34XX_GPT10
+
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+
+#define GPIO_BACKLIGHT		146	/* = GPT11_PWM (instead of UART2-TX) */
+#define GPT_BACKLIGHT		OMAP34XX_GPT11
+
+#else
+
+#error undefined CONFIG
+
+#endif
+
+#define USE_PWM	0
+
+void backlight_set_level(int level)	// 0..255
+{
+#if USE_PWM
+	struct gptimer *gpt_base = (struct gptimer *)GPT_BACKLIGHT;
+	// 	writel(value, &gpt_base->registername);
+#else
+	omap_set_gpio_dataout(GPIO_BACKLIGHT, level >= 128);	// for simplicity we just have on/off
+	level=(level >= 128)?255:0;
+#endif
+	printf("lcm backlight level set to %d (0..255)\n", level);
+}
+
+int backlight_init(void)
+{
+#if USE_PWM
+	struct gptimer *gpt_base = (struct gptimer *)GPT_BACKLIGHT;
+#if defined(CONFIG_OMAP3_GTA04)
+	MUX_VAL(CP(GPMC_NCS6),		(IEN | PTD | DIS | M3)) /* GPT_11 - Backlight enable*/\
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M2)) /* switch to GPT10 */
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M2)) /* switch to GPT11 */
+#else	
+#error undefined CONFIG
+#endif
+	// 	writel(value, &gpt_base->registername);
+	// program registers for generating a 100-1000 Hz PWM signal
+	// or PWM synchronized to VSYNC (to avoid flicker)
+	printf("did backlight_init() on PWM\n");
+
+#error todo
+	
+#else
+#if defined(CONFIG_OMAP3_GTA04)
+	MUX_VAL(CP(GPMC_NCS6),		(IEN | PTD | DIS | M4)) /*GPIO_57 - Backlight enable*/
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/
+#else	
+#error undefined CONFIG
+#endif
+	if(omap_request_gpio(GPIO_BACKLIGHT) == 0)	// 0 == ok
+		{
+		omap_set_gpio_direction(GPIO_BACKLIGHT, 0);		// output
+		printf("did backlight_init() on GPIO_%d\n", GPIO_BACKLIGHT);		
+		}
+	else
+		{
+		printf("backlight_init() on GPIO_%d failed\n", GPIO_BACKLIGHT);		
+		}
+
+#endif
+
+	return 0;
+}
+
+
diff --git a/u-boot/board/goldelico/gta04/backlight.h b/u-boot/board/goldelico/gta04/backlight.h
new file mode 100644
index 0000000..5c299d9
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/backlight.h
@@ -0,0 +1,7 @@
+#ifndef _BACKLIGHT_H
+#define _BACKLIGHT_H
+
+void backlight_set_level(int level);	// 0..255
+int backlight_init(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/commands.c b/u-boot/board/goldelico/gta04/commands.c
new file mode 100644
index 0000000..eb75c1f
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/commands.c
@@ -0,0 +1,782 @@
+/* u-boot extended commands for flash
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+
+#include "backlight.h"
+#include "dssfb.h"
+#include "jbt6k74.h"
+#include "status.h"
+#include "gps.h"
+#include "tsc2007.h"
+#include "shutdown.h"
+#include "systest.h"
+#include "twl4030-additions.h"
+
+/* LCM commands */
+
+static int do_lcd_color(int argc, char *const argv[])
+{
+	unsigned int color;
+	if (argc < 3) {
+		printf ("lcm color: missing color (0..ffffff).\n");
+		return (-1);
+	}
+	color=simple_strtoul(argv[2], NULL, 16);
+	omap3_set_color(color);
+	return 0;
+}
+
+static int do_lcd_framebuffer(int argc, char *const argv[])
+{
+	void *addr;
+	if (argc < 3) {
+		printf ("lcm fb: missing address.\n");
+		return (-1);
+	}
+	addr=(void *) simple_strtoul(argv[2], NULL, 16);
+	omap3_dss_set_fb(addr);
+	return 0;
+}
+
+static int do_lcd_backlight(int argc, char *const argv[])
+{
+	unsigned char level;
+	if (argc < 3) {
+		printf ("lcm backlight: missing level (0..255).\n");
+		return (-1);
+	}
+	level=simple_strtoul(argv[2], NULL, 10);
+	backlight_set_level(level);
+	return 0;
+}
+
+static char *lcdmodel="td028";
+
+static int do_lcd_power(int argc, char *const argv[])
+{
+	if(strcmp(lcdmodel, "td028") == 0)
+		{
+		int state=JBT_STATE_NORMAL;
+		if (argc < 3)
+			{
+			printf ("lcm power: missing state (0..2).\n");
+			return (-1);
+			}
+		state=simple_strtoul(argv[2], NULL, 10);
+		if(state > 2)
+			{
+			printf ("lcm power: invalid state (0..2).\n");
+			return (-1);
+			}
+		jbt6k74_enter_state(state);
+		printf("lcm state set to %s\n", jbt_state());	
+		}
+	return 0;
+}
+
+static int do_lcd_onoff(int argc, char *const argv[], int flag)
+{
+	if(strcmp(lcdmodel, "td028") == 0)
+		jbt6k74_display_onoff(flag);
+	else
+		jbt6k74_display_onoff(flag);
+	printf("display power %s\n", flag?"on":"off");
+	return 0;
+}
+
+static int do_lcd_init(int argc, char *const argv[])
+{
+	// check argv for user specified lcdmodel
+	return board_video_init(NULL);
+}
+
+static int do_lcd_start(int argc, char *const argv[])
+{
+	// check argv for user specified lcdmodel
+	if(board_video_init(NULL))
+		return 1;
+	if(strcmp(lcdmodel, "td028") == 0)
+		{
+		jbt6k74_enter_state(2);
+		jbt6k74_display_onoff(1);
+		backlight_set_level(255);		
+		}
+	return 0;
+}
+
+static int do_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("lcm: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("ba", argv[1], 2) == 0) {
+		return do_lcd_backlight (argc, argv);
+	} else if (strncmp ("po", argv[1], 2) == 0) {
+		return do_lcd_power (argc, argv);
+	} else if (strncmp ("of", argv[1], 2) == 0) {
+		return do_lcd_onoff (argc, argv, 0);
+	} else if (strncmp ("on", argv[1], 2) == 0) {
+		return do_lcd_onoff (argc, argv, 1);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_lcd_init (argc, argv);
+	} else if (strncmp ("co", argv[1], 2) == 0) {
+		return do_lcd_color (argc, argv);
+	} else if (strncmp ("fb", argv[1], 2) == 0) {
+		return do_lcd_framebuffer (argc, argv);
+	} else if (strncmp ("st", argv[1], 2) == 0) {
+		return do_lcd_start (argc, argv);
+	} else {
+		printf ("lcm: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+U_BOOT_CMD(lcm, 3, 0, do_lcd, "LCM sub-system",
+		   "init [model] - initialize DSS, GPIOs and LCM controller\n"
+		   "backlight level - set backlight level\n"
+		   "off - switch off\n"
+		   "on - switch on\n"
+		   "power mode - set power mode\n"
+		   "start [model] - initialize, switch on power and enable backlight\n"
+		   "color hhhhhh - switch color (can be used without init)\n"
+		   "fb address - set framebuffer address (can be used without init)\n"
+		   );
+
+/* TSC commands */
+
+static int do_tsc_init(int argc, char *const argv[])
+{
+	tsc2007_init();
+	return 0;
+}
+
+static int do_tsc_get(int argc, char *const argv[])
+{
+	print_adc();
+	printf("\n");
+	return 0;
+}
+
+static int do_tsc_loop(int argc, char *const argv[])
+{
+	printf("permanently reading ADCs of TSC.\n"
+		   "Press any key to stop\n\n");
+	while (!tstc() && (status_get_buttons()&0x09) == 0)
+		{
+			print_adc();
+			printf("\r");
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+static int do_tsc_gloop(int argc, char *const argv[])
+{
+	unsigned short *fb=(void *) 0x81000000;	// base address to be used as RGB16 framebuffer
+	printf("permanently reading ADCs of TSC to framebuffer.\n"
+		   "Press any key to stop\n\n");
+	omap3_dss_set_fb(fb);
+	while (!tstc() && (status_get_buttons()&0x09) == 0)
+		{
+		int i;
+		for(i=0; i<8; i++)
+			{
+			int val=(480*read_adc(i))/4096;
+			int x, y;
+			printf("%d: %d\n", i, val);
+			for(y=16*i; y<16*i+16; y++)
+				{ // draw colored bar depending on current value
+					for(x=0; x<480; x++)
+						fb[x+480*y]=(x < val)?0xfc00:0x03ff;
+				}
+			}
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+
+
+static int tsc_choice=0;
+
+static int do_tsc_selection(int argc, char *const argv[])
+{ // tsc selection number
+	if (argc != 3)
+		{
+			printf ("tsc selection: missing number of selection to check for.\n");
+			return (-1);
+		}
+	return tsc_choice == simple_strtoul(argv[2], NULL, 10)?0:1;
+}
+
+static int do_tsc_choose(int argc, char *const argv[])
+{ // tsc choose cols rows
+	int cols;
+	int rows;
+	int x;
+	int y;
+	tsc_choice=0;	// reset choice
+	if (argc != 4)
+		{
+			printf ("tsc choose: missing number of cols and rows.\n");
+			return (-1);
+		}
+	cols=simple_strtoul(argv[2], NULL, 10);
+	rows=simple_strtoul(argv[3], NULL, 10);
+	printf("Choosing by waiting for touch.\n");
+	for(y=0; y<rows; y++)
+		for(x=0; x<cols; x++)
+			printf("%d%s", 1+x+y*cols, (x+1==cols)?"\n":" ");
+	printf("Press touch or any key to stop\n\n");
+	while (!tstc())
+		{
+			if(pendown(NULL, NULL) && pendown(&x, &y))
+				{ // still pressed - should now be stable
+#if 0
+					printf("xy: %d/%d\n", x, y);
+					printf("xy: %d/%d\n", x*cols, y*rows);
+#endif
+					x=(x*cols)/4096;
+					y=((4095-y)*rows)/4096;	// (0,0) is lower left corner in our hardware
+					tsc_choice=1+x+y*cols;	// return 1..rows*cols
+#if 0
+					while(pendown(NULL, NULL))
+						{ // wait for pen-up
+							if(tstc())
+								break;
+						}
+#endif
+					if(tstc())
+						break;
+#if 1
+					printf("did choose %d/%d -> %d\n", x, y, tsc_choice);
+#endif
+					return 0;
+				}
+		}
+	if(tstc())
+		getc();
+	return 0;
+}
+
+static int do_tsc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("tsc: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("ge", argv[1], 2) == 0) {
+		return do_tsc_get (argc, argv);
+	} else if (strncmp ("lo", argv[1], 2) == 0) {
+		return do_tsc_loop (argc, argv);
+	} else if (strncmp ("gl", argv[1], 2) == 0) {
+		return do_tsc_gloop (argc, argv);
+	} else if (strncmp ("ch", argv[1], 2) == 0) {
+		return do_tsc_choose (argc, argv);
+	} else if (strncmp ("se", argv[1], 2) == 0) {
+		return do_tsc_selection (argc, argv);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_tsc_init (argc, argv);
+	} else {
+		printf ("tsc: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+
+U_BOOT_CMD(tsc, 4, 0, do_tsc, "TSC2007 sub-system",
+		   "in[it] - initialize TSC2007\n"
+		   "ge[t] - read ADCs\n"
+		   "lo[op] - loop and display x/y coordinates\n"
+		   "gl[oop] - loop and draw to framebuffer\n"
+		   "ch[oose] cols rows - choose item\n"
+		   "se[lection] p - check if item p (1 .. cols*rows) was selected\n"
+		   );
+
+/** Status commands */
+
+static int do_status_init(int argc, char *const argv[])
+{
+	status_init();
+	return 0;
+}
+
+static void print_buttons(int status)
+{
+	printf("AUX: %s Power: %s Antenna: %s Pen: %s", (status&0x01)?"on":"off", (status&0x08)?"on":"off", (status&0x02)?"EXT":"INT", (status&0x10)?"1":"0");
+}
+
+static int do_status_check(int argc, char *const argv[])
+{ // can be used in if construct
+	int state=status_get_buttons();
+	if (argc < 3)
+		{
+			printf ("status check: missing mask.\n");
+			return (-1);
+		}
+	state &= simple_strtoul(argv[2], NULL, 16);
+	return (state != 0)?0:1;
+}
+
+static int do_status_get(int argc, char *const argv[])
+{
+	int status=status_get_buttons();
+	printf("button status: %02x\n", status);
+	print_buttons(status);
+	printf("\n");
+	return 0;
+}
+
+static int do_status_set(int argc, char *const argv[])
+{ // status set hh
+	static int state;
+	if(argc == 2)
+		state++;
+	else
+		state=simple_strtoul(argv[2], NULL, 16);
+	status_set_status(state);
+	return 0;
+}
+
+static int do_status_loop(int argc, char *const argv[])
+{
+	printf("mirroring buttons to LEDs.\n"
+		   "Press any key to stop\n\n");
+	while (!tstc() && !pendown(NULL, NULL))
+		{
+			int state=status_get_buttons();
+			print_buttons(state);
+			printf("\r");
+			status_set_status(state);	// mirror to LEDs
+			udelay(100000);	// 0.1 seconds
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+static int do_status_blink(int argc, char *const argv[])
+{
+	int value=0;
+	printf("blinking LEDs.\n"
+		   "Press any key to stop\n\n");
+	while (!tstc() && !pendown(NULL, NULL))
+		{
+			status_set_status(value++);	// mirror to LEDs
+			udelay(100000);	// 0.1 seconds
+		}
+	if(tstc())
+		getc();
+	return 0;
+}
+
+static int do_status_flash(int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 3) {
+		printf ("status flash: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[2]);
+	if (strncmp ("of", argv[2], 2) == 0) {
+		return status_set_flash (0);
+	} else if (strncmp ("on", argv[2], 2) == 0) {
+		return status_set_flash (1);
+	} else if (strncmp ("fl", argv[2], 2) == 0) {
+		return status_set_flash (2);
+	} else {
+		printf ("status: unknown operation: %s\n", argv[1]);
+		return 1;
+	}
+	return (0);
+}
+
+static int do_status_vibra(int argc, char *const argv[])
+{
+	static int value;
+	if (argc < 3) {
+		printf ("status vibra: missing value.\n");
+		return (-1);
+	}
+	value=simple_strtol(argv[2], NULL, 10);
+	return status_set_vibra(value);
+}
+
+static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("status: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("ge", argv[1], 2) == 0) {
+		return do_status_get (argc, argv);
+	} else if (strncmp ("se", argv[1], 2) == 0) {
+		return do_status_set (argc, argv);
+	} else if (strncmp ("mi", argv[1], 2) == 0) {
+		return do_status_loop (argc, argv);
+	} else if (strncmp ("bl", argv[1], 2) == 0) {
+		return do_status_blink (argc, argv);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_status_init (argc, argv);
+	} else if (strncmp ("ch", argv[1], 2) == 0) {
+		return do_status_check (argc, argv);
+	} else if (strncmp ("fl", argv[1], 2) == 0) {
+		return do_status_flash (argc, argv);
+	} else if (strncmp ("vi", argv[1], 2) == 0) {
+		return do_status_vibra (argc, argv);
+	} else {
+		printf ("status: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+
+U_BOOT_CMD(status, 3, 0, do_status, "LED and Buttons sub-system",
+		   "in[it] - initialize GPIOs\n"
+		   "ge[t] - print button status\n"
+		   "ch[eck] - check button status\n"
+		   "se[t] value - set LEDs state\n"
+		   "mi[rror] - read buttons and mirror to LEDs\n"
+		   "bl[ink] - blink LEDs\n"
+		   "fl[ash] of[f] | on | fl[ash] - control torch / flashlight\n"
+		   "vi[bra] -256..256 - run vibracall motor\n"
+		   );
+
+/** GPS commands */
+
+static int do_gps_init(int argc, char *const argv[])
+{
+	return gps_init();
+}
+
+static int do_gps_on(int argc, char *const argv[])
+{
+	// should we better send a single ongoing pulse of at least 2 32 kHz cycles?
+	gps_on();
+	printf("GPS on\n");
+	return 0;
+}
+
+static int do_gps_off(int argc, char *const argv[])
+{
+	gps_off();
+	printf("GPS off\n");
+	return 0;
+}
+
+static int do_gps_echo(int argc, char *const argv[])
+{
+	gps_echo();
+	return 0;
+}
+
+// FIXME: "gps cmd" to send a string
+
+static int do_gps(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	
+	if (argc < 2) {
+		printf ("gps: missing subcommand.\n");
+		return (-1);
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("on", argv[1], 2) == 0) {
+		return do_gps_on (argc, argv);
+	} else if (strncmp ("of", argv[1], 2) == 0) {
+		return do_gps_off (argc, argv);
+	} else if (strncmp ("in", argv[1], 2) == 0) {
+		return do_gps_init (argc, argv);
+	} else if (strncmp ("ec", argv[1], 2) == 0) {
+		return do_gps_echo (argc, argv);
+	} else {
+		printf ("gps: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+
+U_BOOT_CMD(gps, 3, 0, do_gps, "GPS sub-system",
+		   "init - initialize GPIOs\n"
+		   "on - enable GPS\n"
+		   "off - disable GPS\n"
+		   "cmd string - send string\n"
+		   "echo - echo GPS out to console\n"
+		   );
+
+#include "ulpi-phy.h"
+
+static int do_systest_all(int argc, char *const argv[])
+{
+	unsigned short *fb=(void *) 0x81000000;	// base address to be used as RGB16 framebuffer
+	printf("permanently doing complete systest.\n"
+		   "Press any key to stop\n\n");
+	omap3_dss_set_fb(fb);
+	audiotest_init(0);
+	while (!tstc() && (status_get_buttons()&0x09) == 0)
+		{
+		int i;
+		for(i=0; i<8; i++)
+			{
+			int val=(480*read_adc(i))/4096;
+			int x, y;
+			printf("%d: %d\n", i, val);
+			for(y=16*i; y<16*i+16; y++)
+				{ // draw colored bar depending on current value
+					for(x=0; x<480; x++)
+						fb[x+480*y]=(x < val)?0xfc00:0x03ff;
+				}
+			}
+		// show hardware test results (chip availability)
+		// continue to play some sound every loop...
+		}
+	if(tstc())
+		getc();
+	printf("\n");
+	return 0;
+}
+
+static int do_systest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	if(argc >= 2) {
+		if (strncmp ("au", argv[1], 2) == 0) {
+			return audiotest(0);
+		}
+		if (strncmp ("al", argv[1], 2) == 0) {
+			return do_systest_all (argc, argv);
+		}
+		if (strncmp ("ir", argv[1], 2) == 0) {
+			return irdatest();
+		}
+		if (strncmp ("wl", argv[1], 2) == 0) {
+			return wlanbttest(1);
+		}
+		if (strncmp ("wp", argv[1], 2) == 0) {
+			return wlanbttest(0);	// just power on
+		}
+		if (strncmp ("ch", argv[1], 2) == 0) {
+			return twl4030_init_battery_charging();
+		}
+		if (strncmp ("gp", argv[1], 2) == 0) {
+			return gpiotest();
+		}
+	}
+	if(argc == 3) {
+		if (strncmp ("ot", argv[1], 2) == 0) {
+			return OTGchargepump(simple_strtoul(argv[2], NULL, 10));			
+		}
+		if (strncmp ("ul", argv[1], 2) == 0) {
+			int port=simple_strtoul(argv[2], NULL, 10);	/* 0, 1, ... */
+			int reg;
+			for(reg=0; reg <= 0x3f; reg++)
+				printf("ulpi reg %02x: %02x\n", reg, ulpi_direct_access(port, reg, 0, 0));
+		}
+	}
+	return systest();
+}
+
+U_BOOT_CMD(systest, 3, 0, do_systest, "System Test",
+		   "al[l] - graphical test mode\n"
+		   "au[dio] - test audio\n"
+		   "ir[da] - test IrDA\n"
+		   "gp[io] - test some GPIOs\n"
+		   "wl[anbt] - test WLAN/BT module\n"
+		   "wp - apply power to WLAN/BT module\n"
+		   "ch[arging] - init and test BCI/BKBAT\n"
+		   "ot[g] n - enable/disable OTG charge pump\n"
+		   "ul[pi] n - read ULPI register n\n"
+		   "<no args> - test presence of I2C devices and some TPS65950 registers\n"
+		   );
+
+
+static int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	backlight_set_level(0);
+	jbt6k74_enter_state(0);
+	jbt6k74_display_onoff(0);
+	shutdown();	// finally shut down power
+	printf ("failed to power down\n");
+	return (0);
+}
+
+U_BOOT_CMD(poweroff, 2, 0, do_poweroff, "Poweroff",
+		   "");
+
+static int do_suspend(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	backlight_set_level(0);
+	jbt6k74_enter_state(0);
+	jbt6k74_display_onoff(0);
+	suspend();	// put CPU in sleep mode so that it can be waked up by pressing the AUX button or other events
+	printf ("suspend finished\n");
+	return (0);
+}
+
+U_BOOT_CMD(suspend, 2, 0, do_suspend, "Suspend",
+		   "");
+
+
+static int do_mux(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int cols=0;
+	char *addr=(char *) 0x48002030;
+	printf("PADCONF [0:15] [16:31]\n");
+	while(addr < (char *) 0x48002A28) {
+		u16 mux=*(u16 *) addr;
+		if(cols == 0)
+			printf("%08x", (unsigned int) addr);			
+		printf(" %c%d%c", (mux&8)?((mux&0x10?'U':'D')):' ', (mux&7), (mux&0x100)?'I':'O');
+		addr+=2;
+		if(addr == (char *) 0x48002262)
+			addr= (char *) 0x480025D8, cols=1;	// skip block and force new line
+		if(addr == (char *) 0x480025FC)
+			addr= (char *) 0x48002A00, cols=1;	// skip block and force new line
+		if(++cols == 2) {
+			printf("\n");
+			cols=0;
+		}
+	}
+	if(cols != 0)
+		printf("\n");
+	return (0);
+}
+
+U_BOOT_CMD(mux, 2, 0, do_mux, "Pinmux", "");
+
+
+static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int g;
+	if(argc == 3) {
+		if (strncmp ("on", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_dataout(g, 1);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+		else if (strncmp ("of", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_dataout(g, 0);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+		else if (strncmp ("in", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_direction(g, 1);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+		else if (strncmp ("ou", argv[1], 2) == 0) {
+			g=simple_strtoul(argv[2], NULL, 10);
+			omap_request_gpio(g);
+			omap_set_gpio_direction(g, 0);
+			//			omap_free_gpio(g); - switches back to input
+			return 0;
+		}
+	}
+	if(argc == 1 || argc == 3)
+		{ // no arguments or from..to
+			int i=0;
+			int end=6*32;
+			int n=10;	// number of columns
+			int col=0;
+			if(argc == 3) {
+				i=simple_strtoul(argv[1], NULL, 10);
+				end=simple_strtoul(argv[2], NULL, 10)+1;	// include
+			}
+			for(; i<end; i++)
+				{
+				if(col == 0)
+					printf("%03d", i);
+				printf(" %d", omap_get_gpio_datain(i));
+				if(++col == n)
+					printf("\n"), col=0;
+				}
+			if(col != 0)
+				printf("\n");	// last line		
+		}
+	else if(argc == 2) { // n only
+		if(omap_get_gpio_datain(simple_strtoul(argv[1], NULL, 10)))
+			{
+			printf("1\n");
+			return 1;
+			}
+		else
+			{
+			printf("0\n");
+			return 0;
+			}
+		}
+	else {
+		printf ("gpio: unknown subcommand.\n");
+		return (-1);
+	}
+
+	return (0);
+}
+
+U_BOOT_CMD(gpio, 3, 0, do_gpio, "GPIO sub-system",
+		   " - print all\n"
+		   "n - print and return state\n"
+		   "m n - print state in given range\n"
+		   "on n - set to 1\n"
+		   "of[f] n - set to 0\n"
+		   "in n - switch to input\n"
+		   "ou[t] n - switch to out (does not change pinmux!)\n"
+		   );
diff --git a/u-boot/board/goldelico/gta04/config.mk b/u-boot/board/goldelico/gta04/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/gta04/dssfb.c b/u-boot/board/goldelico/gta04/dssfb.c
new file mode 100644
index 0000000..4eff169
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/dssfb.c
@@ -0,0 +1,257 @@
+/* u-boot driver for the DSS and framebuffer
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include "dssfb.h"
+
+#if 0
+#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args);
+#define DEBUGPC(x, args...) printf(x, ## args);
+#define VERIFY(VAL) if(SPI_READ() != (VAL)) { printf("expected: %d found: %d\n", VAL, SPI_READ()); return 1; }
+#else
+#define DEBUGP(x, args...) do { } while (0)
+#define DEBUGPC(x, args...) do { } while (0)
+#define VERIFY(VAL) if(SPI_READ() != (VAL)) { return 1; }
+#endif
+
+void omap3_dss_go(void)
+{ // push changes from shadow register to display controller
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+
+	u32 l = 0;
+	l = readl(&dispc->control);
+	l |= GO_LCD | GO_DIG;
+	writel(l, &dispc->control);
+	while((readl(&dispc->control) & (GO_LCD | GO_DIG)) != 0)
+		udelay(1000);	// udelay(1000) until the bit(s) are reset by Hardware!
+	DEBUGP("omap3_dss_go() dispc_control: %08x\n", readl(&dispc->control));
+}
+
+struct gfx_regs 
+{
+	u32 gfx_ba[2];				/* 80 */
+	u32 gfx_position;			/* 88 */
+	u32 gfx_size;				/* 8c */
+	u32 reserved1[4];			
+	u32 gfx_attributes;			/* a0 */
+#define GFX_ENABLE 0x0001
+	u32 gfx_fifo_threshold;		/* a4 */
+	u32 gfx_fifo_size_status;	/* a8 */
+	u32 gfx_row_inc;			/* ac */
+	u32 gfx_pixel_inc;			/* b0 */
+	u32 gfx_window_skip;		/* b4 */
+	u32 gfx_table_ba;			/* b8 */
+};
+
+#define OMAP3_GFX_BASE (0x48050480)
+
+int omap3_dss_enable_fb(int flag)
+{
+	struct gfx_regs *gfx = (struct gfx_regs *) OMAP3_GFX_BASE;
+	u32 l = readl(&gfx->gfx_attributes);
+	if(flag)
+		l |= GFX_ENABLE;
+	else
+		l &= ~GFX_ENABLE;
+	DEBUGP("write %x to gfx_attibutes: %08x\n", l, &gfx->gfx_attributes);
+	writel(l, &gfx->gfx_attributes);
+	omap3_dss_go();
+	DEBUGP("framebuffer enabled: %d\n", flag);
+	DEBUGP("gfx_attibutes: %08x\n", readl(&gfx->gfx_attributes));
+	return 0;
+}
+
+int omap3_dss_set_fb(void *addr)
+{ // set framebuffer address
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+	struct gfx_regs *gfx = (struct gfx_regs *) OMAP3_GFX_BASE;
+	if(addr != NULL)
+		{
+			//			u32 l = readl(&dispc->control);
+			//			l |= GO_LCD | GO_DIG;
+			//			writel(l, &dispc->control);
+			//			printf("write %x to gfx_attibutes: %08x\n", l, &gfx->gfx_attributes);
+			//			writel(l, &gfx->gfx_attributes);
+			//			printf("gfx_ba[0]: %08x\n", &gfx->gfx_ba[0]);
+			writel((u32) addr, &gfx->gfx_ba[0]);
+			writel((u32) addr, &gfx->gfx_ba[1]);
+			//			printf("framebuffer address: %08x\n", addr);
+			writel(0, &gfx->gfx_position);
+			//			printf("size_lcd: %08x\n", readl(&dispc->size_lcd));
+			writel(readl(&dispc->size_lcd), &gfx->gfx_size);
+			writel(0x008c, &gfx->gfx_attributes);	// 16x32 bit bursts + RGB16?
+			writel(((0x3fc << 16) + (0x3bc)), &gfx->gfx_fifo_threshold);	// high & low
+			writel(1024, &gfx->gfx_fifo_size_status);	// FIFO size in bytes
+			writel(1, &gfx->gfx_row_inc);
+			writel(1, &gfx->gfx_pixel_inc);
+			writel(0, &gfx->gfx_window_skip);
+			writel(0x807ff000, &gfx->gfx_table_ba);
+			omap3_dss_enable_fb(1);
+#if DEBUG
+			{
+				u32 addr;
+				for(addr=0x48050010; addr <= 0x48050010; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x48050040; addr <= 0x48050058; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x48050410; addr <= 0x48050414; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x48050444; addr <= 0x4805048c; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+				for(addr=0x480504a0; addr <= 0x480504b8; addr+=4)
+					printf("%08x: %08x\n", addr, readl(addr));
+			}
+#endif
+		}
+	else
+		{ // disable
+			omap3_dss_enable_fb(0);
+		}
+	return 0;
+}
+
+int omap3_set_color(u32 color)
+{
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+	writel(color, &dispc->default_color0);
+	omap3_dss_go();
+	printf("background color: %06x\n", color);
+	return 0;
+}
+
+/*
+ * Display Configuration
+ */
+
+#define DVI_BEAGLE_ORANGE_COL		0x00FF8000
+#define VENC_HEIGHT			0x00ef
+#define VENC_WIDTH			0x027f
+
+/*
+ * Configure VENC in DSS for Beagle to generate Color Bar
+ *
+ * Kindly refer to OMAP TRM for definition of these values.
+ */
+static const struct venc_regs venc_config_std_tv = {
+	.status					= 0x0000001B,
+	.f_control				= 0x00000040,
+	.vidout_ctrl				= 0x00000000,
+	.sync_ctrl				= 0x00008000,
+	.llen					= 0x00008359,
+	.flens					= 0x0000020C,
+	.hfltr_ctrl				= 0x00000000,
+	.cc_carr_wss_carr			= 0x043F2631,
+	.c_phase				= 0x00000024,
+	.gain_u					= 0x00000130,
+	.gain_v					= 0x00000198,
+	.gain_y					= 0x000001C0,
+	.black_level				= 0x0000006A,
+	.blank_level				= 0x0000005C,
+	.x_color				= 0x00000000,
+	.m_control				= 0x00000001,
+	.bstamp_wss_data			= 0x0000003F,
+	.s_carr					= 0x21F07C1F,
+	.line21					= 0x00000000,
+	.ln_sel					= 0x00000015,
+	.l21__wc_ctl				= 0x00001400,
+	.htrigger_vtrigger			= 0x00000000,
+	.savid__eavid				= 0x069300F4,
+	.flen__fal				= 0x0016020C,
+	.lal__phase_reset			= 0x00060107,
+	.hs_int_start_stop_x			= 0x008D034E,
+	.hs_ext_start_stop_x			= 0x000F0359,
+	.vs_int_start_x				= 0x01A00000,
+	.vs_int_stop_x__vs_int_start_y		= 0x020501A0,
+	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
+	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
+	.vs_ext_stop_y				= 0x00000006,
+	.avid_start_stop_x			= 0x03480079,
+	.avid_start_stop_y			= 0x02040024,
+	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
+	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
+	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
+	.tvdetgp_int_start_stop_x		= 0x00140001,
+	.tvdetgp_int_start_stop_y		= 0x00010001,
+	.gen_ctrl				= 0x00FF0000,
+	.output_control				= 0x0000000D,
+	.dac_b__dac_c				= 0x00000000
+};
+
+/*
+ * Configure Timings for DVI D
+ */
+static const struct panel_config dvid_cfg = {
+	.timing_h	= 0x0ff03f31, /* Horizantal timing */
+	.timing_v	= 0x01400504, /* Vertical timing */
+	.pol_freq	= 0x00007028, /* Pol Freq */
+	.divisor	= 0x00010006, /* 72Mhz Pixel Clock */
+	.lcd_size	= 0x02ff03ff, /* 1024x768 */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BEAGLE_ORANGE_COL /* ORANGE */
+};
+
+void dssfb_init(const struct panel_config *lcm_cfg)
+{
+#ifdef CONFIG_OMAP3_GTA04A2	/* delayed on GTA04A2 */
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	printf("prcm base = %p\n", (void *) prcm_base);
+	printf("ick_dss_on\n");
+	sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
+	sdelay(1000);
+	printf("fck_dss_on\n");
+	sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
+	sdelay(1000);
+//	printf("fck_cam_on\n");
+//	sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
+//	printf("ick_cam_on\n");
+//	sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+	sdelay(1000);
+#else
+	// FIXME: restore original code
+#endif
+	printf("dss panel config\n");	
+	omap3_dss_panel_config(lcm_cfg);	// set new config
+	printf("dss enable\n");
+	omap3_dss_enable();	// and (re)enable
+}
+
+/*
+ * Configure DSS to display background color on DVID
+ * Configure VENC to display color bar on S-Video
+ */
+void display_init(void)
+{
+	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
+	omap3_dss_panel_config(&dvid_cfg);
+}
+
diff --git a/u-boot/board/goldelico/gta04/dssfb.h b/u-boot/board/goldelico/gta04/dssfb.h
new file mode 100644
index 0000000..a71b193
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/dssfb.h
@@ -0,0 +1,34 @@
+/* u-boot driver for the DSS and framebuffer
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/arch/dss.h>
+
+void dssfb_init(const struct panel_config *lcm_cfg);
+
+void omap3_dss_go(void);
+
+int omap3_dss_enable_fb(int flag);
+
+int omap3_dss_set_fb(void *addr);	// set framebuffer address
+
+int omap3_set_color(u32 color);	// set background color
diff --git a/u-boot/board/goldelico/gta04/gps.c b/u-boot/board/goldelico/gta04/gps.c
new file mode 100644
index 0000000..7f74dc8
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gps.c
@@ -0,0 +1,136 @@
+/* u-boot driver for the GTA04 LEDs and Buttons
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include "gps.h"
+
+#ifdef CONFIG_OMAP3_GTA04
+
+#define GPIO_GPSEXT		144		// external GPS antenna plugged in
+#define GPIO_GPS_ON		145		// reset for GPS module
+
+#else /* Beagle Hybrid */
+
+#define GPIO_GPSEXT		138		// external GPS antenna plugged in
+#define GPIO_GPS_ON		156
+
+#endif
+
+int gps_init(void)
+{
+	extern int get_board_revision(void);
+#define REVISION_XM 0
+	if(get_board_revision() == REVISION_XM) {
+		/* Set VAUX1 to 3.3V for GTA04E display board */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
+							TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		udelay(5000);
+	}
+#ifdef CONFIG_OMAP3_GTA04
+	/* ext. GPS Ant VSIM = 2.8 V (3.0V) */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VSIM_VSEL_28*/ 0x04 /* 0x05 */,
+							TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	udelay(5000);
+#endif
+	
+	omap_request_gpio(GPIO_GPS_ON);
+	omap_set_gpio_direction(GPIO_GPS_ON, 0);		// output
+	omap_request_gpio(GPIO_GPSEXT);
+	omap_set_gpio_direction(GPIO_GPSEXT, 1);		// input
+	return 0;
+}
+
+void gps_on(void)
+{
+	omap_set_gpio_dataout(GPIO_GPS_ON, 1);
+	if(omap_get_gpio_datain(GPIO_GPSEXT))
+		printf("external antenna\n");
+	else
+		printf("internal antenna\n");
+}
+
+void gps_off(void)
+{
+	omap_set_gpio_dataout(GPIO_GPS_ON, 0);
+}
+
+static int lastant=-1;
+static long timer;
+
+#define TIMEOUT 2	// in seconds
+
+void gps_echo(void)
+{
+	#define MODE_X_DIV 16
+	int baudrate=9600;
+	int divisor=(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * baudrate);
+	NS16550_reinit((NS16550_t)CONFIG_SYS_NS16550_COM2, divisor);	// initialize UART
+	while (1)
+		{ // echo in both directions
+			int ant=omap_get_gpio_datain(GPIO_GPSEXT);
+			if(ant != lastant)
+				{ // changed
+					if(ant)
+						printf("external antenna\n");
+					else
+						printf("internal antenna\n");
+					lastant=ant;
+				}
+			if(NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2))
+				{
+				putc(NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2));	// from GPS to console
+				timer=0;	// data received
+				}
+			if(tstc())
+				{
+				int c=getc();
+				if(c == 0x03)	// ctrl-C
+					break;
+				// NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, c);
+				break;
+				}
+			if(timer++ > 2*10000)
+				{ // timeout - try to wakeup/reset the chip
+					printf("no data: on-off impulse\n");
+					omap_set_gpio_dataout(GPIO_GPS_ON, 1);
+					udelay(5000);
+					omap_set_gpio_dataout(GPIO_GPS_ON, 1);
+					timer=0;
+				}
+			udelay(100);	// 10 kHz @ 9 kbit/s
+		}
+	printf("\n");
+}
+
diff --git a/u-boot/board/goldelico/gta04/gps.h b/u-boot/board/goldelico/gta04/gps.h
new file mode 100644
index 0000000..937beb0
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gps.h
@@ -0,0 +1,11 @@
+#ifndef _GPS_H
+#define _GPS_H
+
+int gps_init(void);
+
+void gps_on(void);
+void gps_off(void);
+
+void gps_echo(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/gta04.c b/u-boot/board/goldelico/gta04/gta04.c
new file mode 100644
index 0000000..e9bdd87
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gta04.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Authos:
+ *  Nikolaus Schaller <hns@goldelico.com>
+ *  adapted to GTA04
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "gta04.h"
+
+#if 1	/* testing tool; you can call notify() anywhere even before initialization to see how far the code comes */
+
+/******************************************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ *****************************************************************************/
+static inline void mydelay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+					  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+static inline void myudelay(unsigned long us)
+{
+	mydelay(us * 200); /* approximate */
+}
+
+#define BLON()	MUX_VAL(CP(GPMC_NCS6),      (IEN | PTU | EN  | M4)) /*GPT_PWM11/GPIO57*/
+#define BLOFF()	MUX_VAL(CP(GPMC_NCS6),      (IEN | PTD | EN  | M4)) /*GPT_PWM11/GPIO57*/
+
+void notify(int number)
+{ // flash LCD backlight
+	BLOFF();
+	myudelay(200*1000);
+	BLON();
+	myudelay(50*1000);	// flash
+	BLOFF();
+	myudelay(1500*1000);
+}
+
+#endif
+
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_GTA04;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+	
+	return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ *		C1/2/3, C4 or xM. This can be done by reading
+ *		the level of GPIO173, GPIO172 and GPIO171. This should
+ *		result in
+ *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ */
+int get_board_revision(void)
+{
+	return 6;	// configure pinmux for C1/2/3
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+
+#define TCA6507_BUS			(2-1)	// I2C2
+#define TCA6507_ADDRESS		0x45
+
+/* register numbers */
+#define TCA6507_SELECT0						0
+#define TCA6507_SELECT1						1
+#define TCA6507_SELECT2						2
+
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+	/* ITG3200 & HMC5883L VAUX2 = 2.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX2_VSEL_28*/ 0x09,
+							TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	/* Camera VAUX3 = 2.5V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX3_VSEL_25*/ 0x02,
+							TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, 0x40);	// pull down reset for WLAN&BT chip
+	i2c_set_bus_num(0);	// write I2C1
+
+#if 0 // FIXME: enable only on demand if we want to test BT/WIFI - and apply RESET
+	/* Bluetooth VAUX4 = 3.3V -- CHECKME: 3.3 V is not officially supported! We use 0x09 = 2.8V here*/
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX4_DEDICATED,
+							/*TWL4030_PM_RECEIVER_VAUX4_VSEL_33*/ 0x09,
+							TWL4030_PM_RECEIVER_VAUX4_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+#endif
+
+	/* make dependent on CPU type */
+	setenv("mpurate", "600");
+	setenv("mpurate", "800");
+
+	twl4030_power_init();
+	
+	// we have no LEDs on TPS on GTA04
+	// but a power on/off button (8 seconds)
+	twl4030_power_reset_init();
+
+#if 0
+	// FIXME: check this!!!
+	
+	/* Configure GPIOs to output */
+	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+			 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+	
+	/* Set GPIOs */
+	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
+		   &gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		   GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+#endif
+	
+#if 1	// duplicate with twl4030-additions
+	
+#define TWL4030_BB_CFG_BBCHEN		(1 << 4)
+#define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
+#define TWL4030_BB_CFG_BBISEL_500UA	2
+	
+	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+						 TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
+						 TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+#endif
+	
+	dieid_num_r();
+
+#if 0	// check if watchdog is switched off
+	{	
+		struct _watchdog {
+			u32 widr;	/* 0x00 r */
+			u8 res1[0x0c];
+			u32 wd_sysconfig;	/* 0x10 rw */
+			u32 ws_sysstatus;	/* 0x14 r */
+			u32 wisr;
+			u32 wier;
+			u8 res2[0x04];
+			u32 wclr;	/* 0x24 rw */
+			u32 wcrr;
+			u32 wldr;
+			u32 wtgr;
+			u32 wwps;	/* 0x34 r */
+			u8 res3[0x10];
+			u32 wspr;	/* 0x48 rw */
+		};
+		struct _watchdog *wd2_base = (struct watchdog *)WD2_BASE;
+		struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+		printf("idlest_wkup = %08x\n", readl(&prcm_base->idlest_wkup));
+		printf("widr = %08x\n", readl(&wd2_base->widr));
+		printf("wd_sysconfig = %08x\n", readl(&wd2_base->wd_sysconfig));
+		printf("ws_sysstatus = %08x\n", readl(&wd2_base->ws_sysstatus));
+		printf("wisr = %08x\n", readl(&wd2_base->wisr));
+		printf("wier = %08x\n", readl(&wd2_base->wier));
+		printf("wclr = %08x\n", readl(&wd2_base->wclr));
+		printf("wcrr = %08x\n", readl(&wd2_base->wcrr));
+		printf("wldr = %08x\n", readl(&wd2_base->wldr));
+		printf("wtgr = %08x\n", readl(&wd2_base->wtgr));
+		printf("wwps = %08x\n", readl(&wd2_base->wwps));
+		printf("wspr = %08x\n", readl(&wd2_base->wspr));
+				  
+		writel(WD_UNLOCK2, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK1, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK2, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK1, &wd2_base->wspr);
+		myudelay(100);
+		writel(WD_UNLOCK2, &wd2_base->wspr);
+
+		myudelay(10000); // so that we can see if the counter counts...
+		
+		printf("idlest_wkup = %08x\n", readl(&prcm_base->idlest_wkup));
+		printf("widr = %08x\n", readl(&wd2_base->widr));
+		printf("wd_sysconfig = %08x\n", readl(&wd2_base->wd_sysconfig));
+		printf("ws_sysstatus = %08x\n", readl(&wd2_base->ws_sysstatus));
+		printf("wisr = %08x\n", readl(&wd2_base->wisr));
+		printf("wier = %08x\n", readl(&wd2_base->wier));
+		printf("wclr = %08x\n", readl(&wd2_base->wclr));
+		printf("wcrr = %08x\n", readl(&wd2_base->wcrr));
+		printf("wldr = %08x\n", readl(&wd2_base->wldr));
+		printf("wtgr = %08x\n", readl(&wd2_base->wtgr));
+		printf("wwps = %08x\n", readl(&wd2_base->wwps));
+		printf("wspr = %08x\n", readl(&wd2_base->wspr));
+
+		writel(readl(&wd2_base->wtgr) + 1, &wd2_base->wtgr);
+		
+		printf("idlest_wkup = %08x\n", readl(&prcm_base->idlest_wkup));
+		printf("widr = %08x\n", readl(&wd2_base->widr));
+		printf("wd_sysconfig = %08x\n", readl(&wd2_base->wd_sysconfig));
+		printf("ws_sysstatus = %08x\n", readl(&wd2_base->ws_sysstatus));
+		printf("wisr = %08x\n", readl(&wd2_base->wisr));
+		printf("wier = %08x\n", readl(&wd2_base->wier));
+		printf("wclr = %08x\n", readl(&wd2_base->wclr));
+		printf("wcrr = %08x\n", readl(&wd2_base->wcrr));
+		printf("wldr = %08x\n", readl(&wd2_base->wldr));
+		printf("wtgr = %08x\n", readl(&wd2_base->wtgr));
+		printf("wwps = %08x\n", readl(&wd2_base->wwps));
+		printf("wspr = %08x\n", readl(&wd2_base->wspr));
+		
+	}
+#endif				  
+				  
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_GTA04();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/goldelico/gta04/gta04.h b/u-boot/board/goldelico/gta04/gta04.h
new file mode 100644
index 0000000..bd56326
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/gta04.h
@@ -0,0 +1,601 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _GTA04_H_
+#define _GTA04_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"GTA04",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/* BeagleBoard revisions */
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM	0x0
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_BEAGLE() \
+/*SDRC*/\
+MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+/*GPMC*/\
+MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
+MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+/*DSS*/\
+MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/*CAMERA*/\
+MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+/*Audio Interface */\
+MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/*Expansion card */\
+MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+/*Wireless LAN */\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+/*Bluetooth*/\
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+/*Modem Interface */\
+MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+/*Serial Interface*/\
+MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+/* USB EHCI (port 2) */\
+MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
+MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
+MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
+MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
+MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
+MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
+MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB2_STP*/\
+MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+/*Control and debug */\
+MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+MUX_VAL(CP(SYS_CLKREQ),		(IEN  | /*PTD*/PTU | /*DIS*/EN | M0)) /*SYS_CLKREQ*/\
+MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*GPIO_9 / SYS_OFF_MODE*/\
+MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4)) /*GPIO_10 / SYS_CLKOUT1*/\
+MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+/* should be removed or initialized correctly from the beginning since it may result in a glitch on these pins that we use as GPIOs */\
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_SIMO*/\
+MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_SOMI*/\
+MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_CS0*/\
+MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M1)) /*MCSPI3_CLK*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+/* end remove */\
+MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_BEAGLE_C() \
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#define MUX_BEAGLE_XM() \
+MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | EN  | M4)) /*GPIO_56*/\
+MUX_VAL(CP(GPMC_WAIT0),		(IDIS | PTU | EN  | M4)) /*GPIO_63*/\
+MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTU | EN  | M4)) /*GPIO_129*/\
+MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
+#define MUX_TINCANTOOLS_ZIPPY() \
+MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | EN  | M1)) /*MCSPI4_CLK*/\
+MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | EN  | M1)) /*MCSPI4_SIMO*/\
+MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
+MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | EN  | M1)) /*MCSPI4_CS0*/\
+MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
+MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),      (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_141*/
+
+#define MUX_TINCANTOOLS_TRAINER() \
+MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTU | EN  | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_141*/\
+MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_162*/
+
+#define MUX_KBADC_BEAGLEFPGA() \
+MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | DIS | M1)) /*MCSPI4_CLK*/\
+MUX_VAL(CP(MCBSP1_DX),      (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
+MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTU | EN  | M1)) /*MCSPI4_SOMI*/\
+MUX_VAL(CP(MCBSP1_FSX),     (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable (i.e. output only; IEN means bidirectional mode)
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0 (as defined by pin name)
+ * M4	- Mode 4 (GPIO)
+ */
+
+#if defined(CONFIG_I2C_OMAP_GTA04A2)
+
+#define MUX_BEAGLE_GTA04() \
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_12 - Display serial clock*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_13 - IrDA FIR-SEL*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M4)) /*GPIO_18 - Display DIN*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_19 - Display chip select*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_20 - Display DOUT*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21 - RS232 enable*/\
+MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | DIS | M4)) /*GPIO_57/GPT_11 - Backlight enable*/\
+MUX_VAL(CP(GPMC_WAIT3),		(IDIS | PTU | DIS | M4)) /*GPIO_65 - AUX IN/OUT*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTU | EN  | M4)) /*GPIO_112 - Video Out Enable --- FIXME: this is a Input Only!*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTU | DIS | M4)) /*GPIO_113 - Barometer INT*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTU | DIS | M4)) /*GPIO_114 - Accel1 INT*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTU | DIS | M4)) /*GPIO_115 - Accel2 INT*/\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*GPIO_136 - MMC2_DIR_DAT0 */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*GPIO_137 - MMC2_DIR_DAT1 */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*GPIO_138 - MMC2_DIR_CMD */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*GPIO_139 - MMC2_DIR_CLKIN */\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTU | DIS | M0)) /*GPIO_146 - GPS_TX */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M0)) /*GPIO_147 - GPS_RX */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M0)) /*GPIO_156 - FM TRX*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M0)) /*GPIO_157 -  */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M0)) /*GPIO_158 -  */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M0)) /*GPIO_159 -  */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | EN  | M4)) /*GPIO_160 - PENIRQ*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M0)) /*GPIO_161 -  */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M0)) /*GPIO_162 -  */\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP4_CLKX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DR*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_FSX*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173 - Version sense*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M4)) /*GPIO_174 - USB-PHY-RESET*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTU | DIS | M4)) /*GPIO_175/MMC3CMD - WAKE_WWAN */\
+MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176/MMC3CLK - 3G_WOE */\
+
+#else 	// GTA04A3ff has some improved mux assignments
+
+#define MUX_BEAGLE_GTA04() \
+/*GPIO10 - Keyboard Controller INT - n/a*/\
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_12 - Display serial clock*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_13 - RS232 enable*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M4)) /*GPIO_18 - Display DIN*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_19 - Display chip select*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_20 - Display DOUT*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21 - RS232 EXT line*/\
+MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_22 - MSECURE*/\
+MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M4)) /*GPIO_23 - Video Out Enable*/\
+MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTD | DIS | M4)) /*GPIO_54 - PoP Temp INT*/\
+MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M4)) /*GPIO_55 - AUX Out enable*/\
+MUX_VAL(CP(GPMC_NCS5),		(IEN  | PTD | DIS | M4)) /*GPIO_56 - Gyro INT*/\
+MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M4)) /*GPIO_57(GPT_11) - Backlight enable*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTU | EN  | M4)) /*GPIO_112 - Compass DRDY*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTU | DIS | M4)) /*GPIO_113 - Barometer EOC*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTU | DIS | M4)) /*GPIO_114 - Accel2 INT*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTU | DIS | M4)) /*GPIO_115 - Accel1 INT*/\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*GPIO_136 -> MMC2_DIR_DAT0 */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*GPIO_137 -> MMC2_DIR_DAT1 */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*GPIO_138 -> MMC2_DIR_CMD */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*GPIO_139 -> MMC2_DIR_CLKIN */\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTU | DIS | M0)) /*GPIO_146 -> GPS_TX */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M0)) /*GPIO_147 -> GPS_RX */\
+MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX -> Bluetooth HCI */\
+MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS -> Bluetooth HCI */ \
+MUX_VAL(CP(UART1_CTS),		(IEN  | PTD | DIS | M0)) /*UART1_CTS -> Bluetooth HCI */ \
+MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX -> Bluetooth HCI */\
+MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3 -> Bluetooth PCM */\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /**/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M0)) /**/\
+MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /**/\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M0)) /*GPIO_156 -> FM TRX*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M0)) /*GPIO_157 -> MCBSP1_FSR */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M0)) /*GPIO_158 -> MCBSP1_DX */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M0)) /*GPIO_159 -> MCBSP1_DR */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M4)) /*GPIO_160 - PENIRQ*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M0)) /*GPIO_161 -> MCBSP1_FSX */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M0)) /*GPIO_162 -> MCBSP1_CLKX */\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP4_CLKX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DR*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_DX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*MCBSP4_FSX*/\
+MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*GPIO_170 -> HDQ*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172 - Version sense*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173 - Version sense*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTU | EN  | M4)) /*GPIO_174 - USB-PHY-RESET*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | DIS | M4)) /*GPIO_175/MMC3CMD - WAKE_WWAN/ON_KEY */\
+MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176/MMC3CLK - 3G_WOE/ KEY_IRQ */\
+MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTD | DIS | M4)) /*GPIO_186 - WWAN_RESET (GTA04A4ff) */\
+
+#if 0 // test HSUSB2 wiring
+/* USB EHCI (port 2) */\
+MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | EN | M4)) /*GPIO177 - HSUSB2_DATA2*/\
+MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | EN | M4)) /*GPIO178 - HSUSB2_DATA7*/\
+MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | EN | M4)) /*GPIO179 - HSUSB2_DATA4*/\
+MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | EN | M4)) /*GPIO180 - HSUSB2_DATA5*/\
+MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | EN | M4)) /*GPIO181 - HSUSB2_DATA6*/\
+MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | EN | M4)) /*GPIO182 - HSUSB2_DATA3*/\
+MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | EN | M4)) /*GPIO24 - HSUSB2_CLK*/\
+MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTU | EN | M4)) /*GPIO25 - HSUSB2_STP*/\
+MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | EN | M4)) /*GPIO26 - HSUSB2_DIR*/\
+MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | EN | M4)) /*GPIO27 - HSUSB2_NXT*/\
+MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN | M4)) /*GPIO28 - HSUSB2_DATA0*/\
+MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN | M4)) /*GPIO29 - HSUSB2_DATA1*/\
+
+#endif
+
+#endif
+
+#endif	/* _GTA04_H_ */
diff --git a/u-boot/board/goldelico/gta04/i2c1-fix.c b/u-boot/board/goldelico/gta04/i2c1-fix.c
new file mode 100644
index 0000000..2e21acc
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/i2c1-fix.c
@@ -0,0 +1,291 @@
+/* u-boot driver for the layout issue of the I2C1 on the GTA04A2 board
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * fragments taken from http://www.koders.com/c/fidDC48AC380BE8326E4C3F14F8195BBDB8ED713932.aspx?s=%22Cam%22#L4
+ * see: // see http://www.cc5x.de/I2C.html
+ *
+ */
+
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/i2c.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OMAP3_GTA04A2
+
+/* #error this is for GTA04A2 only */
+
+#include "../../../drivers/i2c/omap24xx_i2c.h"
+
+/* this is a bit-bang driver for the I2C1
+ since the GTA04A2 board has swapped SCL and SDA.
+ We can access these lines in System Test Mode
+ through the I2C_SYSTEST register in ST_EN mode
+ */
+
+#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
+#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
+
+#define KBIT	100
+
+static inline void delay_full_clock(void)
+{
+	udelay(1000/KBIT);
+}
+static inline void delay_half_clock(void)
+{
+	udelay(500/KBIT);
+}
+static inline void delay_quarter_clock(void)
+{
+	udelay(250/KBIT);
+}
+
+static inline void setscl(struct i2c *base, int state)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			if (state) {
+				base->systest |= I2C_SYSTEST_SDA_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SDA_O;
+			}			
+		}
+	else
+		{		
+			if (state) {
+				base->systest |= I2C_SYSTEST_SCL_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SCL_O;
+			}
+		}
+}
+
+static inline void setsda(struct i2c *base, int state)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			if (state) {
+				base->systest |= I2C_SYSTEST_SCL_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SCL_O;
+			}
+		}
+	else
+		{
+			if (state) {
+				base->systest |= I2C_SYSTEST_SDA_O;
+			} else {
+				base->systest &= ~I2C_SYSTEST_SDA_O;
+			}
+		}
+} 
+
+static inline int getscl(struct i2c *base)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			return (base->systest & I2C_SYSTEST_SDA_I) ? 1 : 0;
+		}
+	else
+		return (base->systest & I2C_SYSTEST_SCL_I) ? 1 : 0;
+}
+
+static inline int getsda(struct i2c *base)
+{
+	if(base == (struct i2c *)I2C_BASE1)
+		{ // swap SCL&SDA on I2C1 due to hardware bug
+			return (base->systest & I2C_SYSTEST_SCL_I) ? 1 : 0;			
+		}
+	else
+		return (base->systest & I2C_SYSTEST_SDA_I) ? 1 : 0;
+}
+
+static inline void busidle(struct i2c *base)
+{
+	/*
+	 * float the SCL and SDA lines. The lines have pull-ups
+	 */
+	setscl(base, 1);
+	setsda(base, 1);
+}
+
+static inline void start(struct i2c *base)
+{
+	busidle(base);
+	delay_full_clock();
+	setsda(base, 0);	// switch data during SCL=H -> this is START
+	delay_quarter_clock();
+	setscl(base, 0);	// switch clock -> prepare for bits
+	//	printf("start\n");
+}
+
+static inline void stop(struct i2c *base)
+{
+	setsda(base, 0);	// set next data bit
+	delay_quarter_clock();
+	setscl(base, 1);	// this is like sending a 0 bit
+	delay_half_clock();
+	setsda(base, 1);	// but switch data during clock -> STOP
+	delay_quarter_clock();
+}
+
+static inline void write_bit(struct i2c *base, int bit)
+{
+//	printf("write bit %d\n", bit);
+	setsda(base, bit);
+	delay_quarter_clock();
+	setscl(base, 1);
+	delay_half_clock();
+	setscl(base, 0);
+	delay_quarter_clock();
+}
+
+static inline int read_bit(struct i2c *base)
+{
+	int bit;
+	setsda(base, 1);	// so that we can read from the OC line...
+	delay_quarter_clock();
+	setscl(base, 1);
+	delay_half_clock();
+	setscl(base, 0);
+	bit = getsda(base);
+	delay_quarter_clock();
+//	printf("read bit %d\n", bit);
+	return bit;
+}
+
+static int write_byte(struct i2c *base, int byte)
+{
+	int i;
+	
+	for (i=7; i>=0; i--)
+		write_bit(base, (byte & (1<<i)) != 0);
+	return read_bit(base) == 0; // ok (1) if NACK is asserted
+}
+
+static int read_byte(struct i2c *base)
+{
+	int i;
+	u8 byte=0;
+		
+	for (i=7; i>=0; i--)
+		byte = (byte << 1) | read_bit(base);
+	return byte;
+}
+
+int i2c_bitbang_probe(struct i2c *base, unchar devaddr)
+{
+//	printf("i2c probe %02x SDA %d SCL %d\n", devaddr, getsda(base), getscl(base));
+	start(base);
+	if (write_byte(base, (devaddr<<1))) { // write probe
+		stop(base);	// send stop condition
+		return 0;	// ok
+	}
+	stop(base);	// send stop condition
+	return 1;	// fail
+}
+
+int i2c_bitbang_write_byte (struct i2c *base, u8 devaddr, u8 regoffset, u8 value)
+{
+//	printf("i2c-bb write dev=%02x regoffset=%02x value=%02x\n", devaddr, regoffset, value);
+	start(base);
+	if (write_byte(base, (devaddr<<1))) { // send chip address for write command
+		if (write_byte(base, regoffset)) { // send register offset
+			if (write_byte(base, value)) { // send value
+				stop(base);	// send stop condition
+				return 0;	// ok
+			}
+		}
+	}
+	stop(base);	// send stop condition
+	return 1;	// fail
+}
+
+int i2c_bitbang_read_byte (struct i2c *base, u8 devaddr, u8 regoffset, u8 * value)
+{
+//	printf("i2c-bb read dev=%02x regoffset=%02x ", devaddr, regoffset);
+	start(base);
+	if (write_byte(base, (devaddr<<1))) { // send chip address for write command
+		if (write_byte(base, regoffset)) { // send register offset - this defines where we want to read
+			start(base);	// repeated start
+			if (write_byte(base, (devaddr<<1) | 1)) { // send chip address for read command
+				*value = read_byte(base);
+//				printf("%02x\n", *value);
+				write_bit(base, 1);	// NAK
+				stop(base);	// send stop condition
+				return 0;	// ok
+			}
+			else {
+//				printf(" 2nd chip address error ");
+			}
+		}
+		else {
+//			printf(" offset error ");
+		}
+	}
+	else {
+//		printf(" chip address error ");
+	}
+
+	stop(base);	// send stop condition
+	return 1;	// fail
+}
+
+void i2c_bitbang_init(struct i2c *base)
+{
+	writew(I2C_SYSTEST_ST_EN | I2C_SYSTEST_FREE | (3 << I2C_SYSTEST_TMODE_SHIFT), &base->systest);
+	busidle(base);
+//	printf("i2c-bb init base=%08x\n", base);
+#if OLD
+	printf("I2C_SYSTEST1 *0x4807003C = %04x\n", readw(0x4807003C));
+	printf("I2C_SYSTEST2 *0x4807203C = %04x\n", readw(0x4807203C));
+	printf("I2C_SYSTEST3 *0x4806003C = %04x\n", readw(0x4806003C));
+	setscl(base, 0);
+	delay_full_clock();
+	printf("I2C_SYSTEST2 *0x4807203C = %04x\n", readw(0x4807203C));
+	setscl(base, 1);
+	delay_full_clock();
+	printf("I2C_SYSTEST2 *0x4807203C = %04x\n", readw(0x4807203C));
+#endif
+}
+
+
+void i2c_bitbang_close(struct i2c *base)
+{
+	busidle(base);	
+	base->systest = 0; // get out of test mode
+}
+
+#else
+
+/* not required */
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/jbt6k74.c b/u-boot/board/goldelico/gta04/jbt6k74.c
new file mode 100644
index 0000000..fcc7615
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/jbt6k74.c
@@ -0,0 +1,380 @@
+/* u-boot driver for the tpo JBT6K74-AS LCM ASIC
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* modified by hns@goldelico.com
+ * to separate jbt commands from communication (throgh SPI or GPIOs)
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/arch/dss.h>
+#include <twl4030.h>
+#include "dssfb.h"
+#include "jbt6k74.h"
+
+// FIXME: we have somehow mixed up the file names...
+
+// configure beagle board DSS for the TD28TTEC1
+
+#define DVI_BACKGROUND_COLOR		0x00fadc29	// rgb(250, 220, 41)
+
+#define DSS1_FCLK		432000000	// compare table 4-32. figure 15-65 - but there are other factors
+#define DSS1_FCLK3730	108000000	// compare table 3-34, figure 7-63 - but there are other factors
+#define PIXEL_CLOCK		22000000	// approx. 22 MHz (will be divided from 432 MHz)
+
+// all values are min ratings
+
+#define VDISP	640				// vertical active area
+#define VFP		4				// vertical front porch
+#define VS		2				// VSYNC pulse width (negative going)
+#define VBP		2				// vertical back porch
+#define VDS		(VS+VBP)		// vertical data start
+#define VBL		(VS+VBP+VFP)	// vertical blanking period
+#define VP		(VDISP+VBL)		// vertical cycle
+
+#define HDISP	480				// horizontal active area
+#define HFP		24				// horizontal front porch
+#define HS		8				// HSYNC pulse width (negative going)
+#define HBP		8				// horizontal back porch
+#define HDS		(HS+HBP)		// horizontal data start
+#define HBL		(HS+HBP+HFP)	// horizontal blanking period
+#define HP		(HDISP+HBL)		// horizontal cycle
+
+#if 0
+#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args);
+#define DEBUGPC(x, args...) printf(x, ## args);
+#else
+#define DEBUGP(x, args...) do { } while (0)
+#define DEBUGPC(x, args...) do { } while (0)
+#endif
+
+static /*const*/ struct panel_config lcm_cfg = 
+{
+	.timing_h	= ((HBP-1)<<20) | ((HFP-1)<<8) | ((HS-1)<<0), /* Horizantal timing */
+	.timing_v	= ((VBP+0)<<20) | ((VFP+0)<<8) | ((VS-1)<<0), /* Vertical timing */
+	.pol_freq	= (1<<17)|(0<<16)|(0<<15)|(1<<14)|(1<<13)|(1<<12)|0x28,    /* Pol Freq */
+	.divisor	= (0x0001<<16)|(DSS1_FCLK/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */
+	.lcd_size	= ((HDISP-1)<<0) | ((VDISP-1)<<16), /* as defined by LCM */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BACKGROUND_COLOR
+};
+
+
+enum jbt_register {
+	JBT_REG_SLEEP_IN		= 0x10,
+	JBT_REG_SLEEP_OUT		= 0x11,
+
+	JBT_REG_DISPLAY_OFF		= 0x28,
+	JBT_REG_DISPLAY_ON		= 0x29,
+
+	JBT_REG_RGB_FORMAT		= 0x3a,
+	JBT_REG_QUAD_RATE		= 0x3b,
+
+	JBT_REG_POWER_ON_OFF		= 0xb0,
+	JBT_REG_BOOSTER_OP		= 0xb1,
+	JBT_REG_BOOSTER_MODE		= 0xb2,
+	JBT_REG_BOOSTER_FREQ		= 0xb3,
+	JBT_REG_OPAMP_SYSCLK		= 0xb4,
+	JBT_REG_VSC_VOLTAGE		= 0xb5,
+	JBT_REG_VCOM_VOLTAGE		= 0xb6,
+	JBT_REG_EXT_DISPL		= 0xb7,
+	JBT_REG_OUTPUT_CONTROL		= 0xb8,
+	JBT_REG_DCCLK_DCEV		= 0xb9,
+	JBT_REG_DISPLAY_MODE1		= 0xba,
+	JBT_REG_DISPLAY_MODE2		= 0xbb,
+	JBT_REG_DISPLAY_MODE		= 0xbc,
+	JBT_REG_ASW_SLEW		= 0xbd,
+	JBT_REG_DUMMY_DISPLAY		= 0xbe,
+	JBT_REG_DRIVE_SYSTEM		= 0xbf,
+
+	JBT_REG_SLEEP_OUT_FR_A		= 0xc0,
+	JBT_REG_SLEEP_OUT_FR_B		= 0xc1,
+	JBT_REG_SLEEP_OUT_FR_C		= 0xc2,
+	JBT_REG_SLEEP_IN_LCCNT_D	= 0xc3,
+	JBT_REG_SLEEP_IN_LCCNT_E	= 0xc4,
+	JBT_REG_SLEEP_IN_LCCNT_F	= 0xc5,
+	JBT_REG_SLEEP_IN_LCCNT_G	= 0xc6,
+
+	JBT_REG_GAMMA1_FINE_1		= 0xc7,
+	JBT_REG_GAMMA1_FINE_2		= 0xc8,
+	JBT_REG_GAMMA1_INCLINATION	= 0xc9,
+	JBT_REG_GAMMA1_BLUE_OFFSET	= 0xca,
+
+	JBT_REG_BLANK_CONTROL		= 0xcf,
+	JBT_REG_BLANK_TH_TV		= 0xd0,
+	JBT_REG_CKV_ON_OFF		= 0xd1,
+	JBT_REG_CKV_1_2			= 0xd2,
+	JBT_REG_OEV_TIMING		= 0xd3,
+	JBT_REG_ASW_TIMING_1		= 0xd4,
+	JBT_REG_ASW_TIMING_2		= 0xd5,
+
+	JBT_REG_HCLOCK_VGA		= 0xec,
+	JBT_REG_HCLOCK_QVGA		= 0xed,
+
+};
+
+static const char *jbt_state_names[] = {
+	[JBT_STATE_DEEP_STANDBY]	= "deep-standby",
+	[JBT_STATE_SLEEP]		= "sleep",
+	[JBT_STATE_NORMAL]		= "normal",
+};
+
+static struct jbt_info _jbt, *jbt = &_jbt;
+
+const char *jbt_state(void)
+{
+	return jbt_state_names[jbt->state];
+}
+
+static int jbt_init_regs(struct jbt_info *jbt)
+{
+	int rc;
+
+	DEBUGP("entering\n");
+
+	rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
+	rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
+	rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
+	rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
+	rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
+	rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
+	rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
+	/*
+	 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
+	 * to avoid red / blue flicker
+	 */
+	rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
+	rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
+
+	rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
+	rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
+	rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
+
+	rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+
+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
+	rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
+	rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+	rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+
+	rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
+	rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
+
+	rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
+	rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
+	rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
+
+#if 0
+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+#endif
+
+	if(rc)
+		printf("jbt_init_regs() failed\n");
+	else
+		printf("did jbt_init_regs()\n");
+	return rc;
+}
+
+static int standby_to_sleep(struct jbt_info *jbt)
+{
+	int rc;
+
+	DEBUGP("entering\n");
+
+	/* three times command zero */
+	rc = jbt_reg_write_nodata(jbt, 0x00);
+	udelay(1000);
+	rc = jbt_reg_write_nodata(jbt, 0x00);
+	udelay(1000);
+	rc = jbt_reg_write_nodata(jbt, 0x00);
+	udelay(1000);
+
+	/* deep standby out */
+	rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
+
+	return rc;
+}
+
+static int sleep_to_normal(struct jbt_info *jbt)
+{
+	int rc;
+	DEBUGP("entering\n");
+
+	/* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
+	rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
+
+	/* Quad mode off */
+	rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
+
+	/* AVDD on, XVDD on */
+	rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
+
+	/* Output control */
+	rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
+
+	/* Sleep mode off */
+	rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
+
+	/* at this point we have like 50% grey */
+
+	/* initialize register set */
+	rc |= jbt_init_regs(jbt);
+	return rc;
+}
+
+static int normal_to_sleep(struct jbt_info *jbt)
+{
+	int rc;
+	DEBUGP("entering\n");
+
+	rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+	rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
+	rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
+
+	return rc;
+}
+
+static int sleep_to_standby(struct jbt_info *jbt)
+{
+	DEBUGP("entering\n");
+	return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
+}
+
+/* frontend function */
+int jbt6k74_enter_state(enum jbt_state new_state)
+{
+	int rc = -EINVAL;
+
+	DEBUGP("entering(old_state=%u, new_state=%u)\n", jbt->state, new_state);
+
+	switch (jbt->state) {
+	case JBT_STATE_DEEP_STANDBY:
+		switch (new_state) {
+		case JBT_STATE_DEEP_STANDBY:
+			rc = 0;
+			break;
+		case JBT_STATE_SLEEP:
+			rc = standby_to_sleep(jbt);
+			break;
+		case JBT_STATE_NORMAL:
+			/* first transition into sleep */
+			rc = standby_to_sleep(jbt);
+			/* then transition into normal */
+			rc |= sleep_to_normal(jbt);
+			break;
+		}
+		break;
+	case JBT_STATE_SLEEP:
+		switch (new_state) {
+		case JBT_STATE_SLEEP:
+			rc = 0;
+			break;
+		case JBT_STATE_DEEP_STANDBY:
+			rc = sleep_to_standby(jbt);
+			break;
+		case JBT_STATE_NORMAL:
+			rc = sleep_to_normal(jbt);
+			break;
+		}
+		break;
+	case JBT_STATE_NORMAL:
+		switch (new_state) {
+		case JBT_STATE_NORMAL:
+			rc = 0;
+			break;
+		case JBT_STATE_DEEP_STANDBY:
+			/* first transition into sleep */
+			rc = normal_to_sleep(jbt);
+			/* then transition into deep standby */
+			rc |= sleep_to_standby(jbt);
+			break;
+		case JBT_STATE_SLEEP:
+			rc = normal_to_sleep(jbt);
+			break;
+		}
+		break;
+	}
+	if(rc)
+		printf("jbt6k74_enter_state() failed.\n");
+	else
+		jbt->state=new_state;
+	return rc;
+}
+
+int jbt6k74_display_onoff(int on)
+{
+	DEBUGP("entering\n");
+	if (on)
+		return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
+	else
+		return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+}
+
+int board_video_init(GraphicDevice *pGD)
+{
+	extern int get_board_revision(void);
+	backlight_init();	// initialize backlight
+#define REVISION_XM 0
+	if(get_board_revision() == REVISION_XM) {
+		/* Set VAUX1 to 3.3V for GTA04E display board */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
+								/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
+								TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
+								TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		udelay(5000);
+	}
+	if(jbt_reg_init())	// initialize SPI
+		{
+		printf("No LCM connected\n");
+		return 1;
+		}
+	if (get_cpu_family() == CPU_OMAP36XX)
+		lcm_cfg.divisor	= (0x0001<<16)|(DSS1_FCLK3730/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */
+	dssfb_init(&lcm_cfg);
+	
+	printf("did board_video_init()\n");
+	return 0;
+}
+
diff --git a/u-boot/board/goldelico/gta04/jbt6k74.h b/u-boot/board/goldelico/gta04/jbt6k74.h
new file mode 100644
index 0000000..170873f
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/jbt6k74.h
@@ -0,0 +1,19 @@
+#ifndef _JBT6K74_H
+#define _JBT6K74_H
+
+#include <video_fb.h>
+#include "TD028TTEC1.h"
+#include "backlight.h"
+
+enum jbt_state {
+	JBT_STATE_DEEP_STANDBY,
+	JBT_STATE_SLEEP,
+	JBT_STATE_NORMAL,
+};
+
+int jbt6k74_display_onoff(int on);
+int jbt6k74_enter_state(enum jbt_state new_state);
+const char *jbt_state(void);
+int board_video_init(GraphicDevice *pGD);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/shutdown.c b/u-boot/board/goldelico/gta04/shutdown.c
new file mode 100644
index 0000000..1ebe661
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/shutdown.c
@@ -0,0 +1,63 @@
+/* u-boot driver for the GTA04 shutdown
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <twl4030.h>
+#include "shutdown.h"
+
+void shutdown(void)
+{
+	u8 val = 0;
+	if(i2c_set_bus_num(0))
+		{
+		printf ("could not select I2C1\n");
+		return;
+		}
+	printf("shutting down by writing DEVOFF register of TPS65950\n");
+	if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
+							TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+		printf("Error:TWL4030: failed to read the power register\n");
+		printf("Could not initialize hardware reset\n");
+	} else {
+		val |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
+		if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
+								 TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+			printf("Error:TWL4030: failed to write the power register\n");
+			printf("Could not initialize hardware reset\n");
+		}
+	}
+	// CHECKME: do we have to write PM_MASTER_P2 and _P3?
+}
+
+void suspend(void)
+{
+	// enable the AUX button interrupt for Wakeup
+	// suspend (sleep) the CPU
+	// the TPS should remain powered on
+}
diff --git a/u-boot/board/goldelico/gta04/shutdown.h b/u-boot/board/goldelico/gta04/shutdown.h
new file mode 100644
index 0000000..b1638ea
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/shutdown.h
@@ -0,0 +1,30 @@
+/* u-boot extended commands for GTA04
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SHUTDOWN_H
+#define _SHUTDOWN_H
+
+void shutdown(void);
+void suspend(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/status.c b/u-boot/board/goldelico/gta04/status.c
new file mode 100644
index 0000000..aebd95e
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/status.c
@@ -0,0 +1,289 @@
+/* u-boot driver for the GTA04 LEDs and Buttons
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include "status.h"
+
+#if defined(CONFIG_OMAP3_GTA04)
+
+// no need to probe for LED controller (compiler should optimize unnecessary code)
+#define hasTCA6507 (1==1)
+
+#else
+
+static int hasTCA6507=0;
+
+#endif
+
+#define TWL4030_I2C_BUS		(1-1)	// I2C1
+#define TCA6507_BUS			(2-1)	// I2C2
+#define TCA6507_ADDRESS		0x45
+
+/* register numbers */
+#define TCA6507_SELECT0						0
+#define TCA6507_SELECT1						1
+#define TCA6507_SELECT2						2
+#define TCA6507_FADE_ON_TIME				3
+#define TCA6507_FULLY_ON_TIME				4
+#define TCA6507_FADR_OFF_TIME				5
+#define TCA6507_FIRST_FULLY_OFF_TIME		6
+#define TCA6507_SECOND_FULLY_OFF_TIME		7
+#define TCA6507_MAXIMUM_INTENSITY			8
+#define TCA6507_ONE_SHOT_MASTER_INTENSITY	9
+#define TCA6507_INITIALIZATION				10
+
+#define TCA6507_AUTO_INCREMENT				16
+
+// we can't include "beagle.h"
+/* BeagleBoard revisions */
+extern int get_board_revision(void); 
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM	0x0
+
+static int isXM = 0;
+
+#if defined(CONFIG_OMAP3_GTA04)
+
+#define GPIO_AUX		7		// AUX/User button
+#define GPIO_POWER		-1		// N/A on GTA04 (access through TPS65950)
+#define GPIO_GPSEXT		144		// external GPS antenna is plugged in
+#define GPIO_PENIRQ		160		// TSC must be set up to provide PENIRQ
+
+#elif defined(CONFIG_OMAP3_BEAGLE_HYBRID)
+
+#define GPIO_AUX		136		// AUX/User button
+#define GPIO_POWER		137		// POWER button
+#define GPIO_GPSEXT		138		// external GPS antenna is plugged in
+#define GPIO_PENIRQ		157		// TSC must be set up to provide PENIRQ
+
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+
+#define GPIO_AUX		136		// AUX/User button
+#define GPIO_POWER		137		// POWER button
+#define GPIO_GPSEXT		138		// external GPS antenna is plugged in
+#define GPIO_PENIRQ		157		// TSC must be set up to provide PENIRQ
+
+#else
+
+#error unknown config
+
+#endif
+
+#define GPIO_LED_AUX_RED		(isXM?88:70)		// AUX
+#define GPIO_LED_AUX_GREEN		(isXM?89:71)		// AUX
+#define GPIO_LED_POWER_RED		78					// Power
+#define GPIO_LED_POWER_GREEN	79					// Power
+#define GPIO_LED_VIBRA			(isXM?2:88)			// Vibracall motor
+#define GPIO_LED_UNUSED			(isXM?3:89)			// unused
+
+static int status;
+
+void status_set_status(int value)
+{
+	status=value;
+	if(!hasTCA6507) {
+		omap_set_gpio_dataout(GPIO_LED_AUX_RED, (value&(1 << 0)));
+		omap_set_gpio_dataout(GPIO_LED_AUX_GREEN, (value&(1 << 1)));
+		omap_set_gpio_dataout(GPIO_LED_POWER_RED, (value&(1 << 3)));
+		omap_set_gpio_dataout(GPIO_LED_POWER_GREEN, (value&(1 << 4)));
+		omap_set_gpio_dataout(GPIO_LED_VIBRA, (value&(1 << 6)));
+		omap_set_gpio_dataout(GPIO_LED_UNUSED, (value&(1 << 7)));
+		}
+	else {
+		value &= 0x3f;	// 6 LEDs only - 7th is reserved to reset the WLAN/BT chip
+		i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+		// we could write a autoincrement address and all 3 bytes in a single message
+		// we could set the TCA to do smooth transitions
+		i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+		i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+		i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, value);	// 1 = on
+	}
+}
+
+int status_get_buttons(void)
+{ // convert button state into led state
+#if defined(CONFIG_OMAP3_GTA04)
+	u8 val;
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// read I2C1
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, TWL4030_PM_MASTER_STS_HW_CONDITIONS);	// read state of power button (bit 0) from TPS65950
+	return ((omap_get_gpio_datain(GPIO_AUX)) << 0) |
+		((omap_get_gpio_datain(GPIO_GPSEXT)) << 1) |
+		(((val&0x01) != 0) << 3) |
+		((omap_get_gpio_datain(GPIO_PENIRQ)) << 4);
+#elif defined(CONFIG_OMAP3_BEAGLE_EXPANDER)
+	return
+		((omap_get_gpio_datain(GPIO_AUX)) << 0) |
+		((0) << 1) |
+		((!omap_get_gpio_datain(GPIO_POWER)) << 3) |
+		((omap_get_gpio_datain(GPIO_PENIRQ)) << 4);
+#else
+	return
+		((!omap_get_gpio_datain(GPIO_AUX)) << 0) |
+		((omap_get_gpio_datain(GPIO_GPSEXT)) << 1) |
+		((!omap_get_gpio_datain(GPIO_POWER)) << 3) |
+		((omap_get_gpio_datain(GPIO_PENIRQ)) << 4);
+#endif
+}
+
+int status_init(void)
+{
+	isXM = (get_board_revision() == REVISION_XM);
+#if !defined(CONFIG_OMAP3_GTA04)
+	if(i2c_set_bus_num(TCA6507_BUS))
+		{
+		printf ("could not select I2C2\n");
+		return 1;
+		}
+	hasTCA6507 = !i2c_probe(TCA6507_ADDRESS);
+#endif
+	
+	if(!hasTCA6507) {
+		if(isXM) { // XM has scrambled dss assignment with respect to default ball name
+			MUX_VAL(CP(DSS_DATA18),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA19),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA8),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA9),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(SYS_BOOT0),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(SYS_BOOT1),		(IEN | PTD | EN | M4)); /*GPIO */
+		}
+		else {
+			MUX_VAL(CP(DSS_DATA0),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA1),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA8),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA9),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA16),		(IEN | PTD | EN | M4)); /*GPIO */
+			MUX_VAL(CP(DSS_DATA17),		(IEN | PTD | EN | M4)); /*GPIO */
+		}
+		
+		omap_request_gpio(GPIO_LED_AUX_GREEN);
+		omap_request_gpio(GPIO_LED_AUX_RED);
+		omap_request_gpio(GPIO_LED_POWER_GREEN);
+		omap_request_gpio(GPIO_LED_POWER_RED);
+		omap_request_gpio(GPIO_LED_VIBRA);
+		omap_request_gpio(GPIO_LED_UNUSED);
+		omap_request_gpio(GPIO_POWER);
+	}
+	else {
+		// initialize I2C controller
+	}
+	
+	omap_request_gpio(GPIO_AUX);
+	omap_request_gpio(GPIO_GPSEXT);
+	omap_request_gpio(GPIO_PENIRQ);
+	
+	if(!hasTCA6507) {
+		omap_set_gpio_direction(GPIO_LED_AUX_GREEN, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_AUX_RED, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_POWER_GREEN, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_POWER_RED, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_VIBRA, 0);		// output
+		omap_set_gpio_direction(GPIO_LED_UNUSED, 0);		// output
+		omap_set_gpio_direction(GPIO_POWER, 1);		// input
+		}
+	
+	omap_set_gpio_direction(GPIO_AUX, 1);		// input
+#ifndef CONFIG_OMAP3_GTA04
+	omap_set_gpio_direction(GPIO_POWER, 1);		// input
+#endif
+	omap_set_gpio_direction(GPIO_GPSEXT, 1);	// input
+
+	// when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); ?
+	printf("did init LED driver for %s\n", hasTCA6507?"TCA6507":"GPIOs");
+
+	return 0;
+}
+
+int status_set_flash (int mode)
+{ // 0: off, 1: torch, 2: flash
+	if(i2c_set_bus_num(TCA6507_BUS))
+		{
+		printf ("could not select I2C2\n");
+		return 1;
+		}
+	// initialize if needed
+	// set flash controller mode
+	return 0;
+}
+
+int status_set_vibra (int value)
+{ // 0: off otherwise msb controls left/right (2's complement)
+	unsigned char byte;
+	if(i2c_set_bus_num(TWL4030_I2C_BUS))
+		{
+		printf ("could not select I2C1\n");
+		return 1;
+		}
+	
+	// program Audio controller (see document SWCU050D)
+	
+	byte = 0x00;						// LEDAON=LEDBON=0
+	i2c_write(0x4A, 0xEE, 1, &byte, 1);	// LEDEN
+	byte = value != 0 ? 0x03 : 0x00;	// 8 kHz, Codec on (if value != 0), Option 1:RX and TX stereo audio path
+	i2c_write(0x49, 0x01, 1, &byte, 1);	// CODEC_MODE
+	byte = 0x16;						// APLL_EN enabled, 26 MHz
+	i2c_write(0x49, 0x3a, 1, &byte, 1);	// APLL_CTL
+	byte = 0x04;						// use PWM
+	i2c_write(0x4B, 0x60, 1, &byte, 1);	// VIBRATOR_CFG
+	byte = value > 0?0x01:0x03;			// use VIBRADIR, local driver, enable
+	i2c_write(0x49, 0x45, 1, &byte, 1);	// VIBRATOR_CFG
+	byte = 256-(value>=0?value:-value);	// PWM turnon value
+	if(byte == 0) byte = 0x01;			// 0x00 is forbidden!
+	i2c_write(0x49, 0x46, 1, &byte, 1);	// VIBRA_SEL
+
+	// do we have to set some Audio PLL frequency (number 6 & 7?)
+
+	/*
+	 To use the vibrator H-bridge:
+	 1. Disable LEDA: Set the LEDEN[0]LEDAON bit to logic 0.
+	 2. Disable LEDB: Set the LEDEN[1]LEDBON bit to logic 0.
+	 3. Turn on the codec:
+	 Set the CODEC_MODE[1] CODECPDZ bit to 1.
+	 The H-bridge vibrator can get its operation from the following sources:
+	 •	An audio channel can provide the stimulus.
+	 •	A PWM in the audio subchip can generate the signal.
+	 If an audio channel provides the motivating force for the vibrator (for example: the audio right 1 channel):
+	 1. Set the VIBR_CTL[4]VIBRA_SEL bit to 1.
+	 2. Set the VIBR_CTL[5]VIBRA_DIR_SEL bit to 1.
+	 3. Set the VIBR_CTL[3:2]VIBRA_AUDIO_SEL bit field to 0x1 (audio right 1 channel).
+	 4. Select the use of the SIGN bit to determine the output phase to VIBRA_P and VIBRA_M. 
+	 5. Set the VIBRA_CTL[0]VIBRA_EN bit to 1 (power to the H-bridge is driven by audiodata).
+	 Notes:
+	 •	If audio data drives the vibrator H-bridge, set the VIBRA_SET register to 0xFF.
+	 •	The direction of the vibrator H-bridge controlled by the VIBRA_DIR bit can be changed
+	 on the fly.
+	 6. Set the audio PLL input frequency: The APLL_CTL APLL_INFREQ bitfield=0x6.
+	 7. Enable the audio PLL: The APLL_CTL APLL_ENbit=1.
+	 Note:	Do not enable LEDA/B and the H-vibrator simultaneously.
+	 */
+	return 0;	
+}
diff --git a/u-boot/board/goldelico/gta04/status.h b/u-boot/board/goldelico/gta04/status.h
new file mode 100644
index 0000000..5bed2e2
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/status.h
@@ -0,0 +1,12 @@
+#ifndef _STATUS_H
+#define _STATUS_H
+
+int status_init (void);
+
+void status_set_status (int value);
+int status_get_buttons (void);
+
+int status_set_flash (int mode);	// 0: off, 1: torch, 2: flash
+int status_set_vibra (int value);	// 0: off, >0 / <0 determines polarity . -255 ... +255
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/systest.c b/u-boot/board/goldelico/gta04/systest.c
new file mode 100644
index 0000000..5df301c
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/systest.c
@@ -0,0 +1,850 @@
+/* u-boot driver for the GTA04 shutdown
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <ns16550.h>
+#include "systest.h"
+#include "TD028TTEC1.h"
+#include "ulpi-phy.h"
+#include "status.h"
+#include "tsc2007.h"
+#include "twl4030-additions.h"
+
+#define TWL4030_I2C_BUS			(1-1)
+
+int bt_hci(int msg)
+{
+#define MODE_X_DIV 16
+	int baudrate=9600;
+	int divisor=(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * baudrate);
+	char send[]={
+		0x01,	// command
+#define OGF 0x01
+#define OCF 0x0002	// HCI_Inquiry_Cancel
+#define OP ((OGF<<10)+OCF)
+		OP&0xff, OP>>8
+	};
+	NS16550_reinit((NS16550_t)CONFIG_SYS_NS16550_COM1, divisor);	// initialize UART
+	int i;
+	int bytes=0;
+	long timer=(1*1000*1000)/40;	// 1 second total timeout
+#if 1 // GPIO test for UART lines
+	if(msg)
+		{ // print states of UART lines
+			MUX_VAL(CP(UART1_TX),		(IEN  | PTU | EN | M4)) /*UART1_TX -> Bluetooth HCI */\
+			MUX_VAL(CP(UART1_RTS),		(IEN  | PTU | EN | M4)) /*UART1_RTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | EN | M4)) /*UART1_CTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_RX),		(IEN  | PTU | EN | M4)) /*UART1_RX -> Bluetooth HCI */
+
+			MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+			MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+			MUX_VAL(CP(UART2_TX),		(IEN  | PTU | DIS | M4)) /*GPIO_146 - GPS_TX */\
+			MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M4)) /*GPIO_147 - GPS_RX */\
+			
+			udelay(100);
+			
+			omap_request_gpio(148);
+			omap_request_gpio(149);
+			omap_request_gpio(150);
+			omap_request_gpio(151);
+			omap_set_gpio_direction(148, 1);	// 1=input
+			omap_set_gpio_direction(149, 1);	// 1=input
+			omap_set_gpio_direction(150, 1);	// 1=input
+			omap_set_gpio_direction(151, 1);	// 1=input
+			printf("UART1 RTS: %d\n", omap_get_gpio_datain(149));
+			printf("UART1 CTS: %d\n", omap_get_gpio_datain(150));
+			printf("UART1 TX:  %d\n", omap_get_gpio_datain(148));
+			printf("UART1 RX:  %d\n", omap_get_gpio_datain(151));
+			
+			omap_request_gpio(144);
+			omap_request_gpio(145);
+			omap_request_gpio(146);
+			omap_request_gpio(147);
+			omap_set_gpio_direction(144, 1);	// 1=input
+			omap_set_gpio_direction(145, 1);	// 1=input
+			omap_set_gpio_direction(146, 1);	// 1=input
+			omap_set_gpio_direction(147, 1);	// 1=input
+			printf("UART2 RTS: %d\n", omap_get_gpio_datain(145));
+			printf("UART2 CTS: %d\n", omap_get_gpio_datain(144));
+			printf("UART2 TX:  %d\n", omap_get_gpio_datain(146));
+			printf("UART2 RX:  %d\n", omap_get_gpio_datain(147));
+			
+			MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX -> Bluetooth HCI */\
+			MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_CTS),		(IEN  | PTD | DIS | M0)) /*UART1_CTS -> Bluetooth HCI */ \
+			MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX -> Bluetooth HCI */\
+
+			MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_144 - ext Ant */\
+			MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145 - GPS ON(0)/OFF(1)*/\
+			MUX_VAL(CP(UART2_TX),		(IDIS | PTU | DIS | M0)) /*GPIO_146 - GPS_TX */\
+			MUX_VAL(CP(UART2_RX),		(IEN  | PTU | DIS | M0)) /*GPIO_147 - GPS_RX */\
+			udelay(100);
+		}
+#endif
+	if(msg)
+		printf("HCI send:");
+	for (i=0; i<sizeof(send); i++)
+		{ // send bytes on HCI port
+			if(msg)
+				printf(" %02x", send[i]);
+			NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, send[i]);
+		}
+	if(msg)
+		printf("\n");
+	if(msg)
+		printf("HCI receive:");
+	while (timer-- > 0)
+		{ //
+			if(NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM1))
+				{ // byte received
+					int c=NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM1);
+					if(msg)
+						printf(" %02x", c);	// from GPS to console
+					bytes++;	// one more received
+				}
+			udelay(40);	// 115200 bit/s is approx. 86 us per byte 
+		}
+	if(bytes == 0)
+		{
+		if(msg)
+			printf(" timed out\n");
+		return 0;			
+		}
+	if(msg)
+		printf("\n");
+	return 1;
+}
+
+int systest(void)
+{
+	int r;
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// I2C1
+	printf("TPS65950:      %s\n", !(r=i2c_probe(TWL4030_CHIP_USB))?"found":"-");	// responds on 4 addresses 0x48..0x4b
+	if(!r)
+		{ // was ok, ask for details
+		u8 val;
+		u8 val2;
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, TWL4030_PM_MASTER_STS_HW_CONDITIONS);
+		printf("  STS_HW_CON: %02x", val);	// decode bits
+		if(val & 0x80) printf(" VBUS");
+		if(val & 0x08) printf(" NRESWARM");
+		if(val & 0x04) printf(" USB");
+		if(val & 0x02) printf(" CHG");
+		if(val & 0x01) printf(" PWRON");
+		printf("\n");
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, 0x2e);
+		printf("  PWR_ISR1:   %02x", val);
+		// decode bits
+		printf("\n");
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &val, TWL4030_PM_MASTER_SC_DETECT1);
+		printf("  SC_DETECT:  1:%02x", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &val, TWL4030_PM_MASTER_SC_DETECT1);
+		printf(" 2:%02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, 0x82);
+		printf("  BCIMFSTS2:  %02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, 0x83);
+		printf("  BCIMFSTS3:  %02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, 0x84);
+		printf("  BCIMFSTS4:  %02x\n", val);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x57);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x58);
+		printf("  BTEMP:   %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x59);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x5a);
+		printf("  USBVBUS: %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x5b);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x5c);
+		printf("  ICHG:    %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x5d);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x5e);
+		printf("  VCHG:    %d\n", (val2<<2)+(val>>6));
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, 0x5f);
+		twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val2, 0x60);
+		printf("  VBAT:    %d\n", (val2<<2)+(val>>6));
+		}
+	i2c_set_bus_num(1);	// I2C2
+	printf("TSC2007:       %s\n", !i2c_probe(0x48)?"found":"-");
+	printf("TCA6507:       %s\n", !i2c_probe(0x45)?"found":"-");
+	printf("LIS302 TOP:    %s\n", !i2c_probe(0x1c)?"found":"-");
+	printf("LIS302 BOTTOM: %s\n", !i2c_probe(0x1d)?"found":"-");
+	printf("LSM303:        %s\n", !i2c_probe(0x19)?"found":"-");
+	printf("HMC58xx:       %s\n", !i2c_probe(0x1e)?"found":"-");
+	printf("BMA180:        %s\n", !i2c_probe(0x41)?"found":"-");
+	printf("BMP085:        %s\n", !i2c_probe(0x77)?"found":"-");
+	printf("ITG3200:       %s\n", !i2c_probe(0x68)?"found":"-");
+	printf("Si47xx:        %s\n", !i2c_probe(0x11)?"found":"-");
+	printf("TCA8418:       %s\n", !i2c_probe(0x64)?"found":"-");
+	printf("OV9655:        %s\n", !i2c_probe(0x30)?"found":"-");
+	printf("TPS61050:      %s\n", !i2c_probe(0x33)?"found":"-");
+	printf("EEPROM:        %s\n", !i2c_probe(0x50)?"found":"-");
+	printf("VCNL4000:      %s\n", !i2c_probe(0x13)?"found":"-");
+	i2c_set_bus_num(2);	// I2C3
+	/* nothing to check */
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// I2C1
+	if(!jbt_check())
+	    printf("DISPLAY:       ok\n");
+	else
+		printf("DISPLAY:       failed\n");
+#if HAVE_ULPI_TEST
+	printf("PHY-WWAN:      %s\n", (ulpi_direct_access(1, 1, 0, 0) == 0x04)?"found":"-");	// read reg 1 (vendor id) of HSUSB2
+#endif
+	// LEDs
+	// GPS/UART
+	// RAM-Test
+	// NAND-Test
+	// Buttons
+	// Power
+	// real Display communication
+	// PCM
+	// OTG USB
+	// Charger
+	// internal USB
+	// UMTS Module
+	printf("BT HCI:        %s\n", bt_hci(0)?"found":"-");
+	return (0);
+}
+
+/* audio test taken from BeagleBoard B validation U-Boot (1.3.3) */
+/* http://code.google.com/p/beagleboard/wiki/BeagleSourceCode */
+
+static ushort tone[] = {
+	0x0ce4, 0x0ce4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+	0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+	0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+	0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+	0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+	0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+	0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+	0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+	0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+	0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+	0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000,
+	0x0CE4, 0x0CE4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+	0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+	0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+	0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+	0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+	0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+	0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+	0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+	0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+	0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+	0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000,
+	0x0CE4, 0x0CE4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+	0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+	0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+	0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+	0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+	0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+	0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+	0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+	0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+	0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+	0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000
+};
+
+int audiotest_init(int channel)
+{
+	
+	unsigned char byte;
+	
+	printf("Test Audio Tone on Speaker\n");
+	printf("Initializing over I2C1");
+	i2c_set_bus_num(TWL4030_I2C_BUS);	// I2C1
+	
+	// program Audio controller (see document SWCU050D)
+	
+	// ??? VAUX3 is not connected on BB ???
+	// so what is the setting for 2.8V good for?
+/*	
+	byte = 0x20;						// RES_TYPE2=2, RES_TYPE=0
+	i2c_write(0x4B, 0x7A, 1, &byte, 1);	// VAUX3_DEV_GRP
+	byte = 0x03;						// no trim, 2.8V
+	i2c_write(0x4B, 0x7D, 1, &byte, 1);	// VAUX3_DEDICATED
+
+	
+	byte = 0xE0;						// DEV_GRP belongs to all device groups
+	i2c_write(0x4B, 0x8E, 1, &byte, 1);	// VPLL2_DEV_GRP
+	byte = 0x05;						// 1.8V
+	i2c_write(0x4B, 0x91, 1, &byte, 1);	// VPLL2_DEDICATED
+ */
+	
+	byte = 0x03;						// 8 kHz, Codec on, Option 1:RX and TX stereo audio path
+	i2c_write(0x49, 0x01, 1, &byte, 1);	// CODEC_MODE
+	byte = 0xc0;						// Audio RX Right2 enable, Left 2 enable
+	i2c_write(0x49, 0x02, 1, &byte, 1);	// OPTION
+/*
+	byte = 0x00;
+	i2c_write(0x49, 0x03, 1, &byte, 1);	// ?
+ */
+	byte = 0x00;
+	i2c_write(0x49, 0x04, 1, &byte, 1);	// MICBIAS_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x05, 1, &byte, 1);	// ANAMICL
+	byte = 0x00;
+	i2c_write(0x49, 0x06, 1, &byte, 1);	// ANAMICR
+	byte = 0x00;
+	i2c_write(0x49, 0x07, 1, &byte, 1);	// AVADC_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x08, 1, &byte, 1);	// ADCMICSEL
+	byte = 0x00;
+	i2c_write(0x49, 0x09, 1, &byte, 1);	// DIGMIXING
+	byte = 0x00;
+	i2c_write(0x49, 0x0a, 1, &byte, 1);	// ATXL1PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x0b, 1, &byte, 1);	// ATXR1PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x0c, 1, &byte, 1);	// AVTXL2PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x0d, 1, &byte, 1);	// AVTXR2PGA
+	byte = 0x01;						// TDM/CODEC master mode, 16 bit sample/word, codec mode format, clk256 disabled, Application mode
+	i2c_write(0x49, 0x0e, 1, &byte, 1);	// AUDIO_IF
+	byte = 0x00;
+	i2c_write(0x49, 0x0f, 1, &byte, 1);	// VOICE_IF
+	byte = 0x00;
+	i2c_write(0x49, 0x10, 1, &byte, 1);	// ARXR1PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x11, 1, &byte, 1);	// ARXL1PGA
+	byte = 0x6c;						// ARXR2PGA_CGAIN=6 dB, ARXR2PGA_FGAIN=-31 dB
+	i2c_write(0x49, 0x12, 1, &byte, 1);	// ARXR2PGA
+	byte = 0x6c;						// ARXL2PGA_CGAIN=6 dB, ARXR2PGA_FGAIN=-31 dB
+	i2c_write(0x49, 0x13, 1, &byte, 1);	// ARXL2PGA
+	byte = 0x00;
+	i2c_write(0x49, 0x14, 1, &byte, 1);	// VRXPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x15, 1, &byte, 1);	// VSTPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x16, 1, &byte, 1);	// VRX2ARXPGA
+	byte = 0x0c;						// VDAC_EN off, ADACL2_EN & ADACR2_EN on, ADACL1_EN & ADACR1_EN off
+	i2c_write(0x49, 0x17, 1, &byte, 1);	// AVDAC_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x18, 1, &byte, 1);	// ARX2VTXPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x19, 1, &byte, 1);	// ARXL1_APGA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x1a, 1, &byte, 1);	// ARXR1_APGA_CTL
+	byte = 0x2b;						// 2 dB, no FM loop, Digital-Analog path enable, Analog PGA application mode
+	i2c_write(0x49, 0x1b, 1, &byte, 1);	// ARXL2_APGA_CTL
+	byte = 0x2b;						// 2 dB, no FM loop, Digital-Analog path enable, Analog PGA application mode
+	i2c_write(0x49, 0x1c, 1, &byte, 1);	// ARXR2_APGA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x1d, 1, &byte, 1);	// ATX2ARXPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x1e, 1, &byte, 1);	// BT_IF
+	byte = 0x00;
+	i2c_write(0x49, 0x1f, 1, &byte, 1);	// BTPGA
+	byte = 0x00;
+	i2c_write(0x49, 0x20, 1, &byte, 1);	// BTSTPGA
+	byte = 0x34;						// 0 dB, EAR_AL2_EN
+	i2c_write(0x49, 0x21, 1, &byte, 1);	// EAR_CTL
+	byte = 0x24;						// HSOR_AR2_EN, HSOL_AL2_EN
+	i2c_write(0x49, 0x22, 1, &byte, 1);	// HS_SEL
+	byte = 0x0a;						// HSR_GAIN & HSL_GAIN = 0 dB
+	i2c_write(0x49, 0x23, 1, &byte, 1);	// HS_GAIN_SET
+	byte = 0x42;						// VMID_EN enable, ramp down 20ms
+	i2c_write(0x49, 0x24, 1, &byte, 1);	// HS_POPN_SET
+	byte = 0x00;
+	i2c_write(0x49, 0x25, 1, &byte, 1);	// PREDL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x26, 1, &byte, 1);	// PREDR_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x27, 1, &byte, 1);	// PRECKL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x28, 1, &byte, 1);	// PRECKR_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x29, 1, &byte, 1);	// HFL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2a, 1, &byte, 1);	// HFR_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2b, 1, &byte, 1);	// ALC_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2c, 1, &byte, 1);	// ALC_SET1
+	byte = 0x00;
+	i2c_write(0x49, 0x2d, 1, &byte, 1);	// ALC_SET2
+	byte = 0x00;
+	i2c_write(0x49, 0x2e, 1, &byte, 1);	// BOOST_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x2f, 1, &byte, 1);	// SOFTVOL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x30, 1, &byte, 1);	// DTMF_FREQSEL
+	byte = 0x00;
+	i2c_write(0x49, 0x31, 1, &byte, 1);	// DTMF_TONEXT1H
+	byte = 0x00;
+	i2c_write(0x49, 0x32, 1, &byte, 1);	// DTMF_TONEXT1L
+	byte = 0x00;
+	i2c_write(0x49, 0x33, 1, &byte, 1);	// DTMF_TONEXT2H
+	byte = 0x00;
+	i2c_write(0x49, 0x34, 1, &byte, 1);	// DTMF_TONEXT2L
+	byte = 0x00;
+	i2c_write(0x49, 0x35, 1, &byte, 1);	// DTMF_TONOFF
+	byte = 0x00;
+	i2c_write(0x49, 0x36, 1, &byte, 1);	// DTMF_WANONOFF
+	byte = 0x00;
+	i2c_write(0x49, 0x37, 1, &byte, 1);	// I2S_RX_SCRAMBLE_H
+	byte = 0x00;
+	i2c_write(0x49, 0x38, 1, &byte, 1);	// I2S_RX_SCRAMBLE_M
+	byte = 0x00;
+	i2c_write(0x49, 0x39, 1, &byte, 1);	// I2S_RX_SCRAMBLE_L
+//	byte = 0x15;						// APLL_EN enabled, 19.2 MHz
+	byte = 0x16;						// APLL_EN enabled, 26 MHz
+	i2c_write(0x49, 0x3a, 1, &byte, 1);	// APLL_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x3b, 1, &byte, 1);	// DTMF_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x3c, 1, &byte, 1);	// DTMF_PGA_CTL2
+	byte = 0x00;
+	i2c_write(0x49, 0x3d, 1, &byte, 1);	// DTMF_PGA_CTL1
+	byte = 0x00;
+	i2c_write(0x49, 0x3e, 1, &byte, 1);	// MISC_SET_1
+	byte = 0x00;
+	i2c_write(0x49, 0x3f, 1, &byte, 1);	// PCMBTMUX
+/*
+	byte = 0x00;
+	i2c_write(0x49, 0x40, 1, &byte, 1);	// ?
+	byte = 0x00;
+	i2c_write(0x49, 0x41, 1, &byte, 1);	// ?
+	byte = 0x00;
+	i2c_write(0x49, 0x42, 1, &byte, 1);	// ?
+	byte = 0x00;
+	i2c_write(0x49, 0x43, 1, &byte, 1);	// ?
+ */
+	byte = 0x00;
+	i2c_write(0x49, 0x44, 1, &byte, 1);	// RX_PATH_SEL
+	byte = 0x00;
+	i2c_write(0x49, 0x45, 1, &byte, 1);	// VDL_APGA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x46, 1, &byte, 1);	// VIBRA_CTL
+	byte = 0x00;
+	i2c_write(0x49, 0x47, 1, &byte, 1);	// VIBRA_SET
+	byte = 0x00;
+	i2c_write(0x49, 0x48, 1, &byte, 1);	// ANAMIC_GAIN
+	byte = 0x00;
+	i2c_write(0x49, 0x49, 1, &byte, 1);	// MISC_SET_2
+
+	// check for errors...
+	
+	// initialize McBSP2 and fill with data ???
+	
+	*((uint *) 0x4902208c) = 0x00000208;	// MCBSPLP_SYSCONFIG_REG
+	*((uint *) 0x49022090) = 0x00000000;	// MCBSPLP_THRSH2_REG
+	*((uint *) 0x49022094) = 0x00000000;	// MCBSPLP_THRSH1_REG
+	*((uint *) 0x490220ac) = 0x00001008;	// MCBSPLP_XCCR_REG
+	*((uint *) 0x490220b0) = 0x00000808;	// MCBSPLP_RCCR_REG
+	*((uint *) 0x49022018) = 0x00000000;	// MCBSPLP_RCR2_REG
+	*((uint *) 0x4902201c) = 0x00000000;	// MCBSPLP_RCR1_REG
+	*((uint *) 0x49022020) = 0x00000000;	// MCBSPLP_XCR2_REG
+	*((uint *) 0x49022024) = 0x00000000;	// MCBSPLP_XCR1_REG
+	*((uint *) 0x49022028) = 0x00000000;	// MCBSPLP_SRGR2_REG
+	*((uint *) 0x4902202c) = 0x00000000;	// MCBSPLP_SRGR1_REG
+	*((uint *) 0x49022048) = 0x00000083;	// MCBSPLP_PCR_REG	/ SCLKME, CLKXP, CLKRP
+	*((uint *) 0x49022010) = 0x00000200;	// MCBSPLP_SPCR2_REG / FREE, !XRST
+	*((uint *) 0x49022014) = 0x00000000;	// MCBSPLP_SPCR1_REG / !RRST
+//	*((uint *) 0x4902207c) = 0x00000023;	// MCBSPLP_REV_REG (is read only???)
+	*((uint *) 0x49022010) = 0x00000201;	// MCBSPLP_SPCR2_REG / FREE, XRST
+	*((uint *) 0x49022008) = 0x000056f3;	// MCBSPLP_DXR_REG - write first byte
+	printf("  ... complete\n");
+	return 0;
+
+}
+
+int audiotest_send(void)
+{
+	int count = 0;
+	printf("Sending data");
+
+	for (count = 0; count < 50; count++) {
+		int bytes;
+		for (bytes = 0; bytes < sizeof(tone) / 2; bytes++) {
+			*((uint *) 0x49022008) = tone[bytes];	// MCBSPLP_DXR_REG
+			udelay(100);
+		}
+	}
+	printf("  ... complete\n");
+
+	return 0;
+}
+
+int audiotest(int channel)
+{
+	return audiotest_init(channel) || audiotest_send();
+}
+
+#define RS232_ENABLE	13
+#define RS232_RX		165	// UART3
+#define RS232_TX		166	// UART3
+
+int irdatest(void)
+{
+#ifdef CONFIG_OMAP3_GTA04
+	printf("Stop through touch screen or AUX button - RS232 is disabled\n");
+	udelay(50000);	// wait until RS232 is finished
+	// switch RS232_ENABLE to IrDA through Pull-Down and RXTX to GPIO mode
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M4)); /*UART3_RX_IRRX*/
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M4)); /*UART3_TX_IRTX*/
+	omap_request_gpio(RS232_RX);
+	omap_set_gpio_direction(RS232_RX, 1);	// 1=input
+	omap_request_gpio(RS232_TX);
+	omap_set_gpio_direction(RS232_TX, 0);
+	omap_set_gpio_dataout(RS232_TX, 0);	// set TX=low to select SIR mode
+	udelay(10);
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTD | EN  | M4)); /*GPIO_13 - RS232 enable*/
+	udelay(1000);
+	while(!pendown(NULL, NULL) && (status_get_buttons()&0x09) == 0)
+		{
+		// make IrDA blink
+		omap_set_gpio_dataout(RS232_TX, 1);
+		udelay(150);
+		omap_set_gpio_dataout(RS232_TX, 0);
+		udelay(150);
+		if(!omap_get_gpio_datain(RS232_RX))	// RX is active low
+			status_set_status(0x018);	// echo IrDA sensor status to red power button led
+		else
+			status_set_status(0x000);
+		}
+	// switch back to UART mode
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)); /*UART3_RX_IRRX*/
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M4)); /*GPIO_13 - RS232 enable*/
+	udelay(1000);
+	printf("done.\n");
+	return 0;
+#else
+	printf("n/a\n");
+	return 1;
+#endif
+}
+
+#ifdef CONFIG_OMAP3_GTA04
+int wlabbtpower(void)
+{ /* Bluetooth VAUX4 = 3.3V -- CHECKME: 3.3 V is not officially supported by TPS! We use 0x09 = 2.8V here*/
+#define TCA6507_BUS			(2-1)	// I2C2
+#define TCA6507_ADDRESS		0x45
+	
+	/* register numbers */
+#define TCA6507_SELECT0						0
+#define TCA6507_SELECT1						1
+#define TCA6507_SELECT2						2
+	
+	printf("activate WiFi/BT reset\n");
+	i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, 0x40);	// pull down reset for WLAN&BT chip
+	i2c_set_bus_num(0);	// write I2C1
+	printf("power on VAUX4\n");
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX4_DEDICATED,
+							/* 2.8V: */ 0x09 /* 3.15V: 0x0c */,
+							TWL4030_PM_RECEIVER_VAUX4_DEV_GRP,
+							TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	udelay(20*1000);	// wait a little until power stabilizes
+	printf("release WiFi/BT reset\n");
+	i2c_set_bus_num(TCA6507_BUS);	// write I2C2
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT0, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT1, 0);
+	i2c_reg_write(TCA6507_ADDRESS, TCA6507_SELECT2, 0);	// release reset for WLAN&BT chip
+	i2c_set_bus_num(0);	// write I2C1
+	return 0;
+}
+#endif
+
+int wlanbttest(int test)
+{ /* Bluetooth VAUX4 = 3.3V -- CHECKME: 3.3 V is not officially supported! We use 0x09 = 2.8V here*/
+#ifdef CONFIG_OMAP3_GTA04
+	wlabbtpower();
+	if(test)
+		{
+		// now, we should be able to test the UART for the BT part...
+		return !bt_hci(1);
+		}
+	return 0;
+#else
+	printf("n/a\n");
+	return 1;
+#endif
+}
+
+int OTGchargepump(int enable)
+{
+	if(enable)
+		twl4030_i2c_write_u8(TWL4030_CHIP_USB, 0x20, TWL4030_USB_OTG_CTRL_SET);
+	else
+		twl4030_i2c_write_u8(TWL4030_CHIP_USB, 0x20, TWL4030_USB_OTG_CTRL_CLR);
+	return 0;
+}
+
+static struct
+{
+	int gpio;
+	int inputonly;		// can't switch to output mode (Table 2-24. General-Purpose IOs Signals Description)
+	char *name;
+	unsigned offset;	// PIN-MUX control address -> writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+} gpiotable[] = {
+	{ 7, 0, "AUX button", CP(SYS_BOOT5) },
+	
+	{ 10, 0, "A3: KEYIRQ / A4: 3G_WAKE", CP(SYS_CLKOUT1) },
+	
+	{ 12, 0, "Display SCL", CP(ETK_CLK_ES2) },
+	
+	// CHECKME: doesn't this interfere with RS232 operation?
+	//	{ 13, 1, "RS232 enable", CP(ETK_CTL_ES2) }, 
+	
+	{ 18, 0, "Display DR", CP(ETK_D4_ES2) },
+	{ 19, 0, "Display XCS", CP(ETK_D5_ES2) },
+	{ 20, 0, "Display DX", CP(ETK_D6_ES2) },
+	{ 21, 0, "RS232 EXT", CP(ETK_D7_ES2) },
+	
+	{ 23, 0, "Video out en", CP(ETK_D9_ES2) },
+	{ 24, 0, "HSUSB2_CLK", CP(ETK_D10_ES2) },
+	{ 25, 0, "HSUSB2_STP", CP(ETK_D11_ES2) },
+	{ 26, 0, "HSUSB2_DIR", CP(ETK_D12_ES2) },
+	{ 27, 0, "HSUSB2_NXT", CP(ETK_D13_ES2) },
+	{ 28, 0, "HSUSB2_DATA0", CP(ETK_D14_ES2) },
+	{ 29, 0, "HSUSB2_DATA1", CP(ETK_D15_ES2) },
+	
+	{ 54, 0, "PoP Temp", CP(GPMC_NCS3) },
+	{ 55, 0, "Audio out en", CP(GPMC_NCS4) },
+	{ 56, 0, "Gyro int", CP(GPMC_NCS5) },	
+	{ 57, 0, "Backlight en", CP(GPMC_NCS6) },
+	
+	{ 66, 0, "PCLK", CP(DSS_PCLK) },
+	{ 67, 0, "HSYNC", CP(DSS_HSYNC) },
+	{ 68, 0, "VSYNC", CP(DSS_VSYNC) },
+	{ 69, 0, "DE", CP(DSS_ACBIAS) },
+	{ 70, 0, "DSS0", CP(DSS_DATA0) },
+	{ 71, 0, "DSS1", CP(DSS_DATA1) },
+	{ 72, 0, "DSS2", CP(DSS_DATA2) },
+	{ 73, 0, "DSS3", CP(DSS_DATA3) },
+	{ 74, 0, "DSS4", CP(DSS_DATA4) },
+	{ 75, 0, "DSS5", CP(DSS_DATA5) },
+	{ 76, 0, "DSS6", CP(DSS_DATA6) },
+	{ 77, 0, "DSS7", CP(DSS_DATA7) },
+	{ 78, 0, "DSS8", CP(DSS_DATA8) },
+	{ 79, 0, "DSS9", CP(DSS_DATA9) },
+	{ 80, 0, "DSS10", CP(DSS_DATA10) },
+	{ 81, 0, "DSS11", CP(DSS_DATA11) },
+	{ 82, 0, "DSS12", CP(DSS_DATA12) },
+	{ 83, 0, "DSS13", CP(DSS_DATA13) },
+	{ 84, 0, "DSS14", CP(DSS_DATA14) },
+	{ 85, 0, "DSS15", CP(DSS_DATA15) },
+	{ 86, 0, "DSS16", CP(DSS_DATA16) },
+	{ 87, 0, "DSS17", CP(DSS_DATA17) },
+	{ 88, 0, "DSS18", CP(DSS_DATA18) },
+	{ 89, 0, "DSS19", CP(DSS_DATA19) },
+	{ 90, 0, "DSS20", CP(DSS_DATA20) },
+	{ 91, 0, "DSS21", CP(DSS_DATA21) },
+	{ 92, 0, "DSS22", CP(DSS_DATA22) },
+	{ 93, 0, "DSS23", CP(DSS_DATA23) },
+	{ 94, 0, "CAM_HS", CP(CAM_HS) },
+	{ 95, 0, "CAM_VS", CP(CAM_VS) },
+	{ 96, 0, "CAM_XCLKA", CP(CAM_XCLKA) },
+	{ 97, 0, "CAM_PCLK", CP(CAM_PCLK) },
+	{ 98, 0, "CAM_RESET", CP(CAM_FLD) },
+	{ 99, 1, "CAM_D0", CP(CAM_D0) },
+	{ 100, 1, "CAM_D1", CP(CAM_D1) },
+	{ 101, 0, "CAM_D2", CP(CAM_D2) },
+	{ 102, 0, "CAM_D3", CP(CAM_D3) },
+	{ 103, 0, "CAM_D4", CP(CAM_D4) },
+	{ 104, 0, "CAM_D5", CP(CAM_D5) },
+	{ 105, 1, "CAM_D6", CP(CAM_D6) },
+	{ 106, 1, "CAM_D7", CP(CAM_D7) },
+	{ 107, 1, "CAM_D8", CP(CAM_D8) },
+	{ 108, 1, "CAM_D9", CP(CAM_D9) },
+	{ 109, 0, "CAM_D10", CP(CAM_D10) },
+	{ 110, 0, "CAM_D11", CP(CAM_D11) },
+	{ 111, 0, "CAM_XCLKB", CP(CAM_XCLKB) },
+	{ 112, 1, "Compass rdy", CP(CSI2_DX0) },
+	{ 113, 1, "Baro EOC", CP(CSI2_DY0) },
+	{ 114, 1, "Accel2 int", CP(CSI2_DX1) },
+	{ 115, 1, "Accel1 int", CP(CSI2_DY1) },
+	{ 116, 0, "Audio_FSX", CP(MCBSP2_FSX) },
+	{ 117, 0, "Audio_CLKX", CP(MCBSP2_CLKX) },
+	{ 118, 0, "Audio_DR", CP(MCBSP2_DR) },
+	{ 119, 0, "Audio_DX", CP(MCBSP2_DX) },
+
+	/*	this are duplicate GPIOs with MMC1
+	{ 120, 0, "HSUSB0_CLK", CP(HSUSB0_CLK) },
+	{ 121, 0, "HSUSB0_STP", CP(HSUSB0_STP) },
+	{ 122, 0, "HSUSB0_DIR", CP(HSUSB0_DIR) },
+	
+	{ 124, 0, "HSUSB0_NXT", CP(HSUSB0_NXT) },
+	{ 125, 0, "HSUSB0_DATA0", CP(HSUSB0_DATA0) },
+	 */
+
+	{ 126, 0, "CAM_STROBE", CP(CAM_STROBE) },
+	
+	/*	this are duplicate GPIOs with MMC2
+	 { 130, 0, "HSUSB0_DATA1", CP(HSUSB0_DATA1) },
+	 { 131, 0, "HSUSB0_DATA2", CP(HSUSB0_DATA2) },
+	 */
+	
+	{ 130, 0, "MMC2_CLK", CP(MMC2_CLK) },
+	{ 131, 0, "MMC2_CMD", CP(MMC2_CMD) },
+	{ 132, 0, "MMC2_DAT0", CP(MMC2_DAT0) },
+	{ 133, 0, "MMC2_DAT1", CP(MMC2_DAT1) },
+	{ 134, 0, "MMC2_DAT2", CP(MMC2_DAT2) },
+	{ 135, 0, "MMC2_DAT3", CP(MMC2_DAT3) },
+	{ 136, 0, "MMC2_DIR_DAT0", CP(MMC2_DAT4) },
+	{ 137, 0, "MMC2_DIR_DAT1", CP(MMC2_DAT5) },
+	{ 138, 0, "MMC2_DIR_CMD", CP(MMC2_DAT6) },
+	{ 139, 0, "MMC2_DIR_CLKIN", CP(MMC2_DAT7) },	
+	{ 140, 0, "BT_DX", CP(MCBSP3_DX) },
+	{ 141, 0, "BT_DR", CP(MCBSP3_DR) },
+	{ 142, 0, "BT_CLKX", CP(MCBSP3_CLKX) },
+	{ 143, 0, "BT_FSX", CP(MCBSP3_FSX) },
+	{ 144, 0, "Ext Ant", CP(UART2_CTS) },
+//	{ 145, 0, "GPS enable", CP(UART2_RTS) },	// should remain disabled!
+	{ 146, 0, "GPS_TX", CP(UART2_TX) },
+	{ 147, 0, "GPS_RX", CP(UART2_RX) },
+	{ 148, 0, "BT_TX", CP(UART1_TX) },
+	{ 149, 0, "BT_RTS", CP(UART1_RTS) },
+	{ 150, 0, "BT_CTS", CP(UART1_CTS) },
+	{ 151, 0, "BT_RX", CP(UART1_RX) },
+	{ 152, 0, "WWAN_CLKX", CP(MCBSP4_CLKX) },
+	{ 153, 0, "WWAN_DR", CP(MCBSP4_DR) },
+	{ 154, 0, "WWAN_DX", CP(MCBSP4_DX) },
+	{ 155, 0, "WWAN_FSX", CP(MCBSP4_FSX) },
+	{ 156, 0, "FM_CLKR", CP(MCBSP1_CLKR) },
+	{ 157, 0, "FM_FSR", CP(MCBSP1_FSR) },
+	{ 158, 0, "FM_DX", CP(MCBSP1_DX) },
+	{ 159, 0, "FM_DR", CP(MCBSP1_DR) },
+	{ 160, 0, "PENIRQ", CP(MCBSP_CLKS) },
+	{ 161, 0, "FM_FSX", CP(MCBSP1_FSX) },
+	{ 162, 0, "FM_CLKX", CP(MCBSP1_CLKX) },
+		
+	{ 167, 0, "CAM_PWDN", CP(CAM_WEN) },
+	
+	{ 169, 0, "HSUSB0_DATA3", CP(HSUSB0_DATA3) },
+
+	{ 171, 0, "Revision 0x1", CP(MCSPI1_CLK) },
+	{ 172, 0, "Revision 0x2", CP(MCSPI1_SIMO) },
+	{ 173, 0, "Revision 0x4", CP(MCSPI1_SOMI) },
+//	{ 174, 0, "USB3322 reset", CP(MCSPI1_CS0) },	// should remain in reset state
+	{ 175, 0, "A3: HOST_WAKE / A4:spare", CP(MCSPI1_CS1) },
+	{ 176, 0, "A3: 3G_WAKE / A4: KEYIRQ", CP(MCSPI1_CS2) },
+	{ 177, 0, "HSUSB2_DATA2", CP(MCSPI1_CS3) },
+	{ 178, 0, "HSUSB2_DATA7", CP(MCSPI2_CLK) },
+	{ 179, 0, "HSUSB2_DATA4", CP(MCSPI2_SIMO) },
+	{ 180, 0, "HSUSB2_DATA5", CP(MCSPI2_SOMI) },
+	{ 181, 0, "HSUSB2_DATA6", CP(MCSPI2_CS0) },
+	{ 182, 0, "HSUSB2_DATA3", CP(MCSPI2_CS1) },
+	
+	{ 186, 0, "A3: spare / A4: ON_KEY", CP(SYS_CLKOUT2) },
+	
+	{ 188, 0, "HSUSB0_DATA4", CP(HSUSB0_DATA4) },
+	{ 189, 0, "HSUSB0_DATA5", CP(HSUSB0_DATA5) },
+	{ 190, 0, "HSUSB0_DATA6", CP(HSUSB0_DATA6) },
+	{ 191, 0, "HSUSB0_DATA7", CP(HSUSB0_DATA7) },
+	
+};
+
+
+int gpiotest(void)
+{
+	int i;
+	printf("testing GPIOs for stuck-at, floating and shorts\n");
+	omap_set_gpio_direction(174, 0);	// switch to output
+	omap_set_gpio_dataout(174, 0); // activate reset of USB3322
+	// Camera reset?
+	// WLAN-Reset?
+	// switch off GPS (if on)
+	for(i=0; i<sizeof(gpiotable)/sizeof(gpiotable[0]); i++)
+		{
+		int g=gpiotable[i].gpio;
+		omap_request_gpio(g);
+		omap_set_gpio_direction(g, 1);	// make them all inputs
+		if(gpiotable[i].offset)
+			writew((IEN  | PTD | DIS | M4), OMAP34XX_CTRL_BASE + (gpiotable[i].offset));	// make input GPIO w/o pullup/down
+		udelay(100);
+		}
+	for(i=0; i<sizeof(gpiotable)/sizeof(gpiotable[0]); i++)
+		{ // loop over all inputs
+			int g=gpiotable[i].gpio;
+			char *n=gpiotable[i].name;
+			int j;
+			for(j=0; j<sizeof(gpiotable)/sizeof(gpiotable[0]); j++)
+				{ // check for shorts with other GPIOs switched to output
+					int gj=gpiotable[j].gpio;
+					char *nj=gpiotable[j].name;
+					int valdn, valup; 
+					int stuck=0;	// if known to be stuck
+					int follows=0;	// if known to follow
+					if(!gpiotable[j].inputonly)
+						{ // test with active I/O
+							omap_set_gpio_direction(gj, 0);	// switch to output
+							udelay(100);
+							omap_set_gpio_dataout(gj, 0); // set other output to 0
+							udelay(100);
+							valdn=omap_get_gpio_datain(g);	// read value of input GPIO under test
+							omap_set_gpio_dataout(gj, 1); // set other output to 1
+							udelay(100);
+							valup=omap_get_gpio_datain(g);	// read value of input GPIO under test
+							omap_set_gpio_direction(gj, 1);	// switch back to input
+							udelay(300);
+							if(valdn == 0 && valup == 1)
+								{ // our input follows the other in output mode
+								if(i != j)
+									printf("GPIO %d (%s) follows GPIO %d (%s)\n", g, n, gj, nj), follows=1;
+								}
+							else if(i == j)
+								{ // output does *not* read back the input value -> shorted
+									if(valdn == 0 && valup == 0)
+										printf("GPIO %d (%s) stuck at 0\n", g, n), stuck=1;
+									else if(valdn == 1 && valup == 1)
+										printf("GPIO %d (%s) stuck at 1\n", g, n), stuck=1;
+								}
+						}
+					writew((IEN  | PTD | EN | M4), OMAP34XX_CTRL_BASE + (gpiotable[j].offset));	// make other GPIO input with pulldown
+					udelay(300);
+					valdn=omap_get_gpio_datain(g);	// read value of GPIO under test
+					writew((IEN  | PTU | EN | M4), OMAP34XX_CTRL_BASE + (gpiotable[j].offset));	// make other GPIO input with pullup
+					udelay(300);
+					valup=omap_get_gpio_datain(g);	// read value of GPIO under test
+					writew((IEN  | PTD | DIS | M4), OMAP34XX_CTRL_BASE + (gpiotable[j].offset)); // make other GPIO w/o pullup/down
+					udelay(100);
+					if(valdn == 0 && valup == 1)
+						{ // follows the other pull-up/down
+							if(i == j)
+								printf("GPIO %d (%s) floating\n", g, n);	// follows our own pull-up/down
+							else if(!follows)
+								printf("GPIO %d (%s) weakly follows GPIO %d (%s)\n", g, n, gj, nj, gpiotable[j].inputonly?" (strong not tested)":"");	// -> GPIOs are connected with low to high resistance
+						}
+					else if(i == j && !stuck)
+						{
+						if(valdn == 0 && valup == 0)
+							printf("GPIO %d (%s) weak 0%s\n", g, n, gpiotable[j].inputonly?" (strong not tested)":"");
+						else if(valdn == 1 && valup == 1)
+							printf("GPIO %d (%s) weak 1%s\n", g, n, gpiotable[j].inputonly?" (strong not tested)":"");
+						}
+				}
+		}											 
+	return 0;
+}
+	
diff --git a/u-boot/board/goldelico/gta04/systest.h b/u-boot/board/goldelico/gta04/systest.h
new file mode 100644
index 0000000..4126b3b
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/systest.h
@@ -0,0 +1,36 @@
+/* u-boot extended commands for GTA04
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SYSTEST_H
+#define _SYSTEST_H
+
+int systest(void);
+int audiotest_init(int channel);
+int audiotest_send(void);
+int audiotest(int channel);
+int irdatest(void);
+int wlanbttest(int serial);
+int OTGchargepump(int enable);
+int gpiotest(void);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/tsc2007.c b/u-boot/board/goldelico/gta04/tsc2007.c
new file mode 100644
index 0000000..b2a0cfa
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/tsc2007.c
@@ -0,0 +1,181 @@
+/* u-boot driver for the TSC2007 connected to I2C2
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "tsc2007.h"
+
+#define TSC2007_BUS 2	// I2C2
+#define TSC2007_ADDRESS 0x48
+
+// command byte definitions:
+// channel selection and power down
+
+#define TSC2007_TEMP0	0x00
+#define TSC2007_AUX		0x20
+#define TSC2007_TEMP1	0x40
+#define TSC2007_ACTX	0x80
+#define TSC2007_ACTY	0x90
+#define TSC2007_ACTXY	0xA0
+#define TSC2007_X		0xc0
+#define TSC2007_Y		0xd0
+#define TSC2007_Z1		0xe0
+#define TSC2007_Z2		0xf0
+
+#define TSC2007_POWER_DOWN		0x00	// must be sent once after power up
+#define TSC2007_ADC_ON			0x04
+#define TSC2007_ADC_OFF_PENIRQ	0x08
+
+#define TSC2007_12Bit2MHz		0x00
+#define TSC2007_8Bit4MHz		0x02
+
+// setup command
+
+#define TSC2007_SETUP		0xb0
+
+#define TSC2007_USE_MAV		0x00
+#define TSC2007_BYPASS_MAV	0x02
+
+#define TSC2007_50kPUP		0x00
+#define TSC2007_90kPUP		0x01
+
+/*
+ int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+ int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+*/
+
+static int didNotInit=1;
+
+int tsc2007_cmd(int cmd)
+{ // send command
+	unsigned char buf[16];
+	buf[0]=cmd;
+	if (i2c_write(TSC2007_ADDRESS, cmd, 1, buf, 0))	// write 1 byte command
+		{
+			printf ("Error writing the TSC.\n");
+			return 1;
+		}
+	return 0;
+}
+
+int tsc2007_init(void)
+{
+	if(i2c_set_bus_num(TSC2007_BUS-1))
+		{
+			printf ("could not select I2C2\n");
+			return 1;
+		}
+	
+	if(i2c_probe(TSC2007_ADDRESS))
+		{
+		printf ("could not probe TSC2007\n");
+		return 1;		
+		}
+	
+	didNotInit = tsc2007_cmd(TSC2007_SETUP|TSC2007_USE_MAV|TSC2007_50kPUP);
+	didNotInit |= tsc2007_cmd(TSC2007_POWER_DOWN);
+	
+	if(didNotInit)
+		printf("did tsc2007_init() failed.\n");
+	else
+		printf("did tsc2007_init()\n");
+
+	return 0;
+}
+
+int read_adc(int adcnum)
+{ // read ADC and return value in range 0..4095
+	unsigned char c;
+	unsigned char buf[16];
+	static int cmd[]={ 
+		TSC2007_X,
+		TSC2007_Y,
+		TSC2007_Z1,
+		TSC2007_Z2,
+		TSC2007_TEMP0,
+		TSC2007_TEMP1,
+		TSC2007_AUX,
+		TSC2007_AUX
+	};
+	if(didNotInit)
+		return -1;
+	if(i2c_get_bus_num() != TSC2007_BUS-1 && i2c_set_bus_num(TSC2007_BUS-1))
+		{
+		printf ("could not select I2C2\n");
+		return -1;
+		}
+	c=cmd[adcnum%8] | TSC2007_ADC_ON | TSC2007_12Bit2MHz;
+//	printf("send %02x\n", c);
+	if (i2c_read(TSC2007_ADDRESS, c, 1, buf, 1))
+		{
+			printf ("Error reading the TSC.\n");
+			return -1;
+		}
+	return ((unsigned)buf[0]) << 4;	// read 1 byte only
+	
+//	return (buf[0]<<4)+(buf[1]>>4);	// 12 bit
+}
+
+void print_adc(void)
+{
+	printf("0:%04u 1:%04u 2:%04u 3:%04u 4:%04u 5:%04u 6:%04u 7:%04u",
+		   read_adc(0),
+		   read_adc(1),
+		   read_adc(2),
+		   read_adc(3),
+		   read_adc(4),
+		   read_adc(5),
+		   read_adc(6),
+		   read_adc(7));
+}
+
+int pendown(int *x, int *y)
+{
+#if 1
+	int z;
+	int xx;
+	int yy;
+	xx=read_adc(0);
+	yy=read_adc(1);
+	z=read_adc(2);	// read Z
+	if(z < 0)
+		return 0;	// read error
+#if 0
+	printf("z=%04d x:%04d y:%04d\n", z, xx, yy);
+#endif
+	if(x) *x=xx;
+	if(y) *y=yy;
+	udelay(10000);	// reduce I2C traffic and debounce...
+	return z > 200;	// was pressed
+#else
+	// must be in PENIRQ mode...
+	return (status_get_buttons() & (1 << 4)) == 0;
+#endif
+}
+
diff --git a/u-boot/board/goldelico/gta04/tsc2007.h b/u-boot/board/goldelico/gta04/tsc2007.h
new file mode 100644
index 0000000..476d253
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/tsc2007.h
@@ -0,0 +1,9 @@
+#ifndef _TSC2007_H
+#define _TSC2007_H
+
+int tsc2007_init(void);
+int read_adc(int adcnum);
+void print_adc(void);
+int pendown(int *x, int *y);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/twl4030-additions.c b/u-boot/board/goldelico/gta04/twl4030-additions.c
new file mode 100644
index 0000000..89d94f2
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/twl4030-additions.c
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ *
+ * (C) Copyright 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * this patch was found here: https://gforge.ti.com/gf/project/omapandroid/mailman/?action=ListThreads&mailman_id=22&_forum_action=ForumMessageBrowse&thread_id=1252
+ *
+ */
+#include <twl4030.h>
+#include "twl4030-additions.h"
+
+/*
+ * Battery
+ */
+
+#define mdelay(n) ({ unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static inline int clear_n_set(u8 chip_no, u8 clear, u8 set, u8 reg)
+{
+	int ret;
+	u8 val = 0;
+	
+	/* Gets the initial register value */
+	ret = twl4030_i2c_read_u8(chip_no, &val, reg);
+	if (ret) {
+		printf("a\n");
+		return ret;
+	}
+	
+	/* Clearing all those bits to clear */
+	val &= ~(clear);
+	
+	/* Setting all those bits to set */
+	val |= set;
+	
+	/* Update the register */
+	ret = twl4030_i2c_write_u8(chip_no, val, reg);
+	if (ret) {
+		printf("b\n");
+		return ret;
+	}
+	return 0;
+}
+
+/*
+ * Disable/Enable AC Charge funtionality.
+ */
+static int twl4030_ac_charger_enable(int enable)
+{
+	int ret;
+	
+	if (enable) {
+		/* forcing the field BCIAUTOAC (BOOT_BCI[0]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, 0,
+						  +	 (CONFIG_DONE | BCIAUTOWEN | BCIAUTOAC),
+						  +	 REG_BOOT_BCI);
+		if (ret)
+			return ret;
+	} else {
+		/* forcing the field BCIAUTOAC (BOOT_BCI[0]) to 0 */
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOAC,
+						  +	 (CONFIG_DONE | BCIAUTOWEN),
+						  +	 REG_BOOT_BCI);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
+/*
+ * Disable/Enable USB Charge funtionality.
+ */
+static int twl4030_usb_charger_enable(int enable)
+{
+	u8 value;
+	int ret;
+	
+	if (enable) {
+		/* enable access to BCIIREF1 */
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7,
+								   +	 REG_BCIMFKEY);
+		if (ret)
+			return ret;
+		
+		/* set charging current = 852mA */
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xFF,
+								   +	 REG_BCIIREF1);
+		if (ret)
+			return ret;
+		
+		/* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, 0,
+						  +	 (CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB),
+						  +	 REG_BOOT_BCI);
+		if (ret)
+			return ret;
+		
+		/* Enabling interfacing with usb thru OCP */
+		ret = clear_n_set(TWL4030_CHIP_USB, 0, PHY_DPLL_CLK,
+						  +	 REG_PHY_CLK_CTRL);
+		if (ret)
+			return ret;
+		
+		value = 0;
+		
+		while (!(value & PHY_DPLL_CLK)) {
+			udelay(10);
+			ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &value,
+									  +	 REG_PHY_CLK_CTRL_STS);
+			if (ret)
+				return ret;
+		}
+		
+		/* OTG_EN (POWER_CTRL[5]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_USB, 0, OTG_EN,
+						  +	 REG_POWER_CTRL);
+		if (ret)
+			return ret;
+		
+		mdelay(50);
+		
+		/* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */
+		ret = clear_n_set(TWL4030_CHIP_MAIN_CHARGE, 0,
+						  +	 USBFASTMCHG, REG_BCIMFSTS4);
+		if (ret)
+			return ret;
+	} else {
+		ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOUSB,
+						  +	 (CONFIG_DONE | BCIAUTOWEN), REG_BOOT_BCI);
+		if (ret)
+			return ret;
+	}
+	
+	return 0;
+}
+
+/*
+ * Setup the twl4030 MADC module to measure the backup
+ * battery voltage.
+ */
+static int twl4030_madc_setup(void)
+{
+	int ret = 0;
+	
+	/* turning MADC clocks on */
+	ret = clear_n_set(TWL4030_CHIP_INTBR, 0,
+					  +	 (MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN), REG_GPBR1);
+	if (ret)
+		return ret;
+	
+	/* turning adc_on */
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MADC, MADC_ON,
+							   +	 REG_CTRL1);
+	if (ret)
+		return ret;
+	
+	/* setting MDC channel 9 to trigger by SW1 */
+	ret = clear_n_set(TWL4030_CHIP_MADC, 0, SW1_CH9_SEL,
+					  +	 REG_SW1SELECT_MSB);
+	
+	return ret;
+}
+
+/*
+ * Charge backup battery through main battery
+ */
+static int twl4030_charge_backup_battery(void)
+{
+	int ret;
+	
+	ret = clear_n_set(TWL4030_CHIP_PM_RECIEVER, 0xff,
+					  +	 (BBCHEN | BBSEL_3200mV | BBISEL_500uA), REG_BB_CFG);
+	if (ret)
+		return ret;
+	
+	return 0;
+}
+
+/*
+ * Helper function to read a 2-byte register on BCI module
+ */
+static int read_bci_val(u8 reg)
+{
+	int ret = 0, temp = 0;
+	u8 val;
+	
+	/* reading MSB */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, reg + 1);
+	if (ret)
+		return ret;
+	
+	temp = ((int)(val & 0x03)) << 8;
+	
+	/* reading LSB */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, reg);
+	if (ret)
+		return ret;
+	
+	return temp + val;
+}
+
+/*
+ * Triggers the sw1 request for the twl4030 module to measure the sw1 selected
+ * channels
+ */
+static int twl4030_madc_sw1_trigger(void)
+{
+	u8 val;
+	int ret;
+	
+	/* Triggering SW1 MADC convertion */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, REG_CTRL_SW1);
+	if (ret)
+		return ret;
+	
+	val |= SW1_TRIGGER;
+	
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MADC, val, REG_CTRL_SW1);
+	if (ret)
+		return ret;
+	
+	/* Waiting until the SW1 conversion ends*/
+	val = BUSY;
+	
+	while (!((val & EOC_SW1) && (!(val & BUSY)))) {
+		ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val,
+								  +	 REG_CTRL_SW1);
+		if (ret)
+			return ret;
+		mdelay(10);
+	}
+	
+	return 0;
+}
+
+/*
+ * Return battery voltage
+ */
+static int twl4030_get_battery_voltage(void)
+{
+	int volt;
+	
+	volt = read_bci_val(T2_BATTERY_VOLT);
+	return (volt * 588) / 100;
+}
+
+/*
+ * Return battery temperature (uncalibrated)
+ * current = 10uA, full scale 1023 = 1.5V; prescaler=1
+ * 10k @ 25C -> 0.1V -> 68
+ * 26.6k @ 0C -> 0.26V -> 182
+ */
+
+#define R0C	26600
+#define R25C 10000
+
+#define VSTEP ((15*10000)/1023))
+#define VAL0C (R0C/VSTEP)
+#define VAL25C (R25C/VSTEP)
+
+static int twl4030_get_battery_temperature(void)
+{
+	int temperature;
+	
+	temperature = read_bci_val(T2_BATTERY_TEMP);
+	return ((R0C - temperature) * 25) / (R0C - R25C);	// CHECKME
+//	return ((182 - temperature) * 25) / (182 - 68);	// CHECKME
+}
+
+/*
+ * Return battery current
+ */
+static int twl4030_get_battery_current(void)
+{
+	int current;
+	
+	/* from linux driver
+	 int curr;
+	 int ret;
+	 u8 bcictl1;
+	 
+	 curr = twl4030bci_read_adc_val(TWL4030_BCIICHG);
+	 if (curr < 0)
+	 return curr;
+	 
+	 ret = twl4030_bci_read(TWL4030_BCICTL1, &bcictl1);
+	 if (ret)
+	 return ret;
+	 
+	 ret = (curr * 16618 - 850 * 10000) / 10;
+	 if (bcictl1 & TWL4030_CGAIN)
+	 ret *= 2;
+	 
+	 return ret;
+*/	 
+	
+	current = read_bci_val(T2_BATTERY_CUR);
+	return ((current - 512) * 1) / 1;	// FIXME
+}
+
+/*
+ * Return the battery backup voltage
+ */
+static int twl4030_get_backup_battery_voltage(void)
+{
+	int ret, temp;
+	u8 volt;
+	
+	/* trigger MADC convertion */
+	twl4030_madc_sw1_trigger();
+	
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &volt, REG_GPCH9 + 1);
+	if (ret)
+		return ret;
+	
+	temp = ((int) volt) << 2;
+	
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &volt, REG_GPCH9);
+	if (ret)
+		return ret;
+	
+	temp = temp + ((int) ((volt & MADC_LSB_MASK) >> 6));
+	
+	return (temp * 441) / 100;
+}
+
+/*
+ * Return the AC power supply voltage
+ */
+static int twl4030_get_ac_charger_voltage(void)
+{
+	int volt = read_bci_val(T2_BATTERY_ACVOLT);
+	return (volt * 735) / 100;
+}
+
+/*
+ * Return the USB power supply voltage
+ */
+static int twl4030_get_usb_charger_voltage(void)
+{
+	int volt = read_bci_val(T2_BATTERY_USBVOLT);
+	return (volt * 2058) / 300;
+}
+
+/*
+ * Battery charging main function called from board-specific file
+ */
+
+int twl4030_init_battery_charging(void)
+{
+	u8 batstsmchg, batstspchg, hwsts;
+	int battery_volt = 0, charger_present = 0;
+	int ret = 0;
+	
+#ifdef CONFIG_3430ZOOM2
+	/* For Zoom2 enable Main charge Automatic mode:
+	 * by enabling MADC clocks
+	 */
+	
+	/* Enable AC charging */
+	ret = clear_n_set(TWL4030_CHIP_INTBR, 0,
+					  +	 (MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN), REG_GPBR1);
+	
+	udelay(100);
+	
+	
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7,
+							   +	 REG_BCIMFKEY);
+	/* set MAX charging current */
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xFF,
+							   +	 REG_BCIIREF1);
+		
+	/* Done for Zoom2 */
+	return 0;
+#endif
+	
+	/* check for battery presence */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &batstsmchg,
+							  +	 REG_BCIMFSTS3);
+	if (ret)
+		return ret;
+	
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_PRECHARGE, &batstspchg,
+							  +	 REG_BCIMFSTS1);
+	if (ret)
+		return ret;
+	
+	if (!((batstspchg & BATSTSPCHG) || (batstsmchg & BATSTSMCHG))) {
+		printf("no battery\n");
+		return ret;	/* no battery */		
+	}
+	
+	ret = twl4030_madc_setup();
+	if (ret) {
+		printf("twl4030 madc setup error %d\n", ret);
+		return ret;
+	}
+	/* backup battery charges through main battery */
+	ret = twl4030_charge_backup_battery();
+	if (ret) {
+		printf("backup battery charging error\n");
+		return ret;
+	}
+	
+	// SPLITME here - up to here it is init, all below can be a systest user command
+	
+	/* check for charger presence */
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &hwsts,
+							  +	 REG_STS_HW_CONDITIONS);
+	if (ret)
+		return ret;
+	
+	if (hwsts & STS_CHG) {
+		printf("AC charger detected\n");
+		ret = twl4030_ac_charger_enable(1);
+		if (ret)
+			return ret;
+		charger_present = 1;
+	} else {
+		if (hwsts & STS_VBUS) {
+			printf("USB charger detected\n");
+			charger_present = 1;
+		}
+		/* usb charging is enabled regardless of the whether the
+		 * charger is attached, otherwise the main battery voltage
+		 * cannot be read
+		 */
+		ret = twl4030_usb_charger_enable(1);
+		if (ret)
+			return ret;
+	}
+	battery_volt = twl4030_get_battery_voltage();
+	printf("Main battery charge:    %d mV\n", battery_volt);
+	printf("Battery temperature:    %d C\n", twl4030_get_battery_temperature());
+	printf("Backup battery voltage: %d mV\n", twl4030_get_backup_battery_voltage());
+	printf("AC charger voltage:     %d mV\n", twl4030_get_ac_charger_voltage());
+	printf("USB charger voltage:    %d mV\n", twl4030_get_usb_charger_voltage());
+	printf("Charging current:       %d mA\n", twl4030_get_battery_current());
+	return ret;
+}
+
+#if (defined(CONFIG_TWL4030_KEYPAD) && (CONFIG_TWL4030_KEYPAD))
+/*
+ * Keypad
+ */
+int twl4030_keypad_init(void)
+{
+	int ret = 0;
+	u8 ctrl;
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, KEYPAD_KEYP_CTRL_REG);
+	if (!ret) {
+		ctrl |= CTRL_KBD_ON | CTRL_SOFT_NRST;
+		ctrl &= ~CTRL_SOFTMODEN;
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, KEYPAD_KEYP_CTRL_REG);
+	}
+	return ret;
+}
+
+int twl4030_keypad_reset(void)
+{
+	int ret = 0;
+	u8 ctrl;
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, KEYPAD_KEYP_CTRL_REG);
+	if (!ret) {
+		ctrl &= ~CTRL_SOFT_NRST;
+		ret = twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, KEYPAD_KEYP_CTRL_REG);
+	}
+	return ret;
+}
+
+int twl4030_keypad_keys_pressed(unsigned char *key1, unsigned char *key2)
+{
+	int ret = 0;
+	u8 cb, c, rb, r;
+	for (cb = 0; cb < 8; cb++) {
+		c = 0xff & ~(1 << cb);
+		twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, c, KEYPAD_KBC_REG);
+		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &r, KEYPAD_KBR_REG);
+		for (rb = 0; rb < 8; rb++) {
+			if (!(r & (1 << rb))) {
+				if (!ret)
+					*key1 = cb << 3 | rb;
+				else if (1 == ret)
+					*key2 = cb << 3 | rb;
+				ret++;
+			}
+		}
+	}
+	return ret;
+}
+
+#endif
diff --git a/u-boot/board/goldelico/gta04/twl4030-additions.h b/u-boot/board/goldelico/gta04/twl4030-additions.h
new file mode 100644
index 0000000..4ddd8e2
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/twl4030-additions.h
@@ -0,0 +1,203 @@
+/*
+   * (C) Copyright 2009
+   * Windriver, <www.windriver.com>
+   * Tom Rix <Tom.Rix@windriver.com>
+   *
+   * This program is free software; you can redistribute it and/or
+   * modify it under the terms of the GNU General Public License as
+   * published by the Free Software Foundation; either version 2 of
+   * the License, or (at your option) any later version.
+   *
+   * This program is distributed in the hope that it will be useful,
+   * but WITHOUT ANY WARRANTY; without even the implied warranty of
+   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+   * GNU General Public License for more details.
+   *
+   * You should have received a copy of the GNU General Public License
+   * along with this program; if not, write to the Free Software
+   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+   * MA 02111-1307 USA
+   */
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB ID */
+#define TWL4030_CHIP_USB	 0x48
+/* AUD ID */
+#define TWL4030_CHIP_AUDIO_VOICE	0x49
+#define TWL4030_CHIP_GPIO	 0x49
+#define TWL4030_CHIP_INTBR	 0x49
+#define TWL4030_CHIP_PIH	 0x49
+#define TWL4030_CHIP_TEST	 0x49
+/* AUX ID */
+#define TWL4030_CHIP_KEYPAD	 0x4a
+#define TWL4030_CHIP_MADC	 0x4a
+#define TWL4030_CHIP_INTERRUPTS	 0x4a
+#define TWL4030_CHIP_LED	 0x4a
+#define TWL4030_CHIP_MAIN_CHARGE	0x4a
+#define TWL4030_CHIP_PRECHARGE	 0x4a
+#define TWL4030_CHIP_PWM0	 0x4a
+#define TWL4030_CHIP_PWM1	 0x4a
+#define TWL4030_CHIP_PWMA	 0x4a
+#define TWL4030_CHIP_PWMB	 0x4a
+/* POWER ID */
+#define TWL4030_CHIP_BACKUP	 0x4b
+#define TWL4030_CHIP_INT	 0x4b
+#define TWL4030_CHIP_PM_MASTER	 0x4b
+#define TWL4030_CHIP_PM_RECIEVER	0x4b
+#define TWL4030_CHIP_RTC	 0x4b
+#define TWL4030_CHIP_SECURED_REG	0x4b
+
+/* Register base addresses */
+
+/* USB ID */
+#define TWL4030_BASEADD_USB	 0x0000
+/* AUD ID */
+#define TWL4030_BASEADD_AUDIO_VOICE	0x0000
+#define TWL4030_BASEADD_GPIO	 0x0098
+#define TWL4030_BASEADD_INTBR	 0x0085
+#define TWL4030_BASEADD_PIH	 0x0080
+#define TWL4030_BASEADD_TEST	 0x004C
+/* AUX ID */
+#define TWL4030_BASEADD_INTERRUPTS	0x00B9
+#define TWL4030_BASEADD_LED	 0x00EE
+#define TWL4030_BASEADD_MADC	 0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE	0x0074
+#define TWL4030_BASEADD_PRECHARGE	0x00AA
+#define TWL4030_BASEADD_PWM0	 0x00F8
+#define TWL4030_BASEADD_PWM1	 0x00FB
+#define TWL4030_BASEADD_PWMA	 0x00EF
+#define TWL4030_BASEADD_PWMB	 0x00F1
+#define TWL4030_BASEADD_KEYPAD	 0x00D2
+/* POWER ID */
+#define TWL4030_BASEADD_BACKUP	 0x0014
+#define TWL4030_BASEADD_INT	 0x002E
+#define TWL4030_BASEADD_PM_MASTER	0x0036
+#define TWL4030_BASEADD_PM_RECIEVER	0x005B
+#define TWL4030_BASEADD_RTC	 0x001C
+#define TWL4030_BASEADD_SECURED_REG	0x0000
+
+/* Register addresses */
+
+#define REG_STS_HW_CONDITIONS	(TWL4030_BASEADD_PM_MASTER + 0x0F)
+#define STS_VBUS	 0x080
+#define STS_CHG	 0x02
+#define REG_BCICTL1 (TWL4030_BASEADD_PM_MASTER + 0x023)
+#define REG_BCICTL2 (TWL4030_BASEADD_PM_MASTER + 0x024)
+#define CGAIN	 0x020
+#define ITHEN	 0x010
+#define ITHSENS	 0x007
+#define REG_BCIMFTH1	 (TWL4030_BASEADD_PM_MASTER + 0x016)
+#define REG_BCIMFTH2	 (TWL4030_BASEADD_PM_MASTER + 0x017)
+#define BCIAUTOWEN	 (TWL4030_BASEADD_PM_MASTER + 0x020)
+#define CONFIG_DONE	 0x010
+#define BCIAUTOUSB	 0x002
+#define BCIAUTOAC	 0x001
+#define BCIMSTAT_MASK	 0x03F
+#define REG_BOOT_BCI	 (TWL4030_BASEADD_PM_MASTER + 0x007)
+
+#define REG_GPBR1	 (TWL4030_BASEADD_INTBR + 0x0c)
+#define MADC_HFCLK_EN	 0x80
+#define DEFAULT_MADC_CLK_EN	0x10
+
+#define REG_CTRL1	 (TWL4030_BASEADD_MADC + 0x00)
+#define MADC_ON	 0x01
+#define REG_SW1SELECT_MSB	0x07
+#define SW1_CH9_SEL	 0x02
+#define REG_CTRL_SW1	 (TWL4030_BASEADD_MADC + 0x012)
+#define SW1_TRIGGER	 0x020
+#define EOC_SW1	 0x002
+#define BUSY	 0x001
+#define REG_GPCH9	 (TWL4030_BASEADD_MADC + 0x049)
+
+#define REG_BCIMSTATEC	 (TWL4030_BASEADD_MAIN_CHARGE + 0x002)
+#define REG_BCIMFSTS2	 (TWL4030_BASEADD_MAIN_CHARGE + 0x00E)
+#define REG_BCIMFSTS3 (TWL4030_BASEADD_MAIN_CHARGE + 0x00F)
+#define REG_BCIMFSTS4	 (TWL4030_BASEADD_MAIN_CHARGE + 0x010)
+#define REG_BCIMFKEY	 (TWL4030_BASEADD_MAIN_CHARGE + 0x011)
+#define REG_BCIIREF1	 (TWL4030_BASEADD_MAIN_CHARGE + 0x027)
+
+#define REG_BCIMFSTS1	 (TWL4030_BASEADD_PRECHARGE + 0x001)
+#define USBFASTMCHG	 0x004
+#define BATSTSPCHG	 0x004
+#define BATSTSMCHG	 0x040
+#define VBATOV4	 0x020
+#define VBATOV3	 0x010
+#define VBATOV2	 0x008
+#define VBATOV1	 0x004
+#define MADC_LSB_MASK	 0xC0
+#define REG_BB_CFG	 (TWL4030_BASEADD_PM_RECIEVER + 0x12)
+#define BBCHEN	 0x10
+#define	 BBSEL_2500mV	 0x00
+#define	 BBSEL_3000mV	 0x04
+#define	 BBSEL_3100mV	 0x08
+#define	 BBSEL_3200mV	 0x0C
+#define	 BBISEL_25uA	 0x00
+#define	 BBISEL_150uA	 0x01
+#define	 BBISEL_500uA	 0x02
+#define	 BBISEL_1000uA	 0x03
+
+#define REG_POWER_CTRL	 (TWL4030_BASEADD_USB + 0x0AC)
+#define REG_POWER_CTRL_SET (TWL4030_BASEADD_USB + 0x0AD)
+#define REG_POWER_CTRL_CLR	(TWL4030_BASEADD_USB + 0x0AE)
+#define OTG_EN	 0x020
+#define REG_PHY_CLK_CTRL	(TWL4030_BASEADD_USB + 0x0FE)
+#define REG_PHY_CLK_CTRL_STS (TWL4030_BASEADD_USB + 0x0FF)
+#define PHY_DPLL_CLK	 0x01
+
+/* TWL4030 battery measuring parameters */
+#define T2_BATTERY_VOLT	 (TWL4030_BASEADD_MAIN_CHARGE + 0x04)
+#define T2_BATTERY_TEMP	 (TWL4030_BASEADD_MAIN_CHARGE + 0x06)
+#define T2_BATTERY_CUR	 (TWL4030_BASEADD_MAIN_CHARGE + 0x08)
+#define T2_BATTERY_ACVOLT	(TWL4030_BASEADD_MAIN_CHARGE + 0x0A)
+#define T2_BATTERY_USBVOLT	(TWL4030_BASEADD_MAIN_CHARGE + 0x0C)
+
+/* Keypad */
+#define KEYPAD_KEYP_CTRL_REG 0xD2
+#define KEYPAD_KEY_DEB_REG 0xD3
+#define KEYPAD_LONG_KEY_REG1 0xD4
+#define KEYPAD_LK_PTV_REG 0xD5
+#define KEYPAD_TIME_OUT_REG1 0xD6
+#define KEYPAD_TIME_OUT_REG2 0xD7
+#define KEYPAD_KBC_REG 0xD8
+#define KEYPAD_KBR_REG 0xD9
+#define KEYPAD_KEYP_SMS 0xDA
+#define KEYPAD_FULL_CODE_7_0 0xDB
+#define KEYPAD_FULL_CODE_15_8 0xDC
+#define KEYPAD_FULL_CODE_23_16 0xDD
+#define KEYPAD_FULL_CODE_31_24 0xDE
+#define KEYPAD_FULL_CODE_39_32 0xDF
+#define KEYPAD_FULL_CODE_47_40 0xE0
+#define KEYPAD_FULL_CODE_55_48 0xE1
+#define KEYPAD_FULL_CODE_63_56 0xE2
+#define KEYPAD_KEYP_ISR1 0xE3
+#define KEYPAD_KEYP_IMR1 0xE4
+#define KEYPAD_KEYP_ISR2 0xE5
+#define KEYPAD_KEYP_IMR2 0xE6
+#define KEYPAD_KEYP_SIR 0xE7
+#define KEYPAD_KEYP_EDR 0xE8
+#define KEYPAD_KEYP_SIH_CTRL 0xE9
+
+#define CTRL_KBD_ON (1 << 6)
+#define CTRL_RP_EN (1 << 5)
+#define CTRL_TOLE_EN (1 << 4)
+#define CTRL_TOE_EN (1 << 3)
+#define CTRL_LK_EN (1 << 2)
+#define CTRL_SOFTMODEN (1 << 1)
+#define CTRL_SOFT_NRST (1 << 0)
+
+int twl4030_init_battery_charging(void);
+
+/* Declarations for users of the keypad, stubs for everyone else. */
+#if (defined(CONFIG_TWL4030_KEYPAD) && (CONFIG_TWL4030_KEYPAD))
+int twl4030_keypad_init(void);
+int twl4030_keypad_reset(void);
+int twl4030_keypad_keys_pressed(unsigned char *key1, unsigned char *key2);
+#else
+#define twl4030_keypad_init() 0
+#define twl4030_keypad_reset() 0
+#define twl4030_keypad_keys_pressed(a, b) 0
+#endif
diff --git a/u-boot/board/goldelico/gta04/ulpi-phy.c b/u-boot/board/goldelico/gta04/ulpi-phy.c
new file mode 100644
index 0000000..15986e5
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/ulpi-phy.c
@@ -0,0 +1,73 @@
+/* u-boot driver to access ULPI PHY registers through EHCI controller
+ *
+ * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG
+ * Author: H. Nikolaus Schaller <hns@goldelico.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* FIXME 
+ * needs to enable clock USBHOST_FCLK etc.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "ulpi-phy.h"
+
+#define EHCI_BASE			(0x480648A4)
+
+#define	EHCI_INSNREG05_ULPI				(0xA4)
+#define	EHCI_INSNREG05_ULPI_CONTROL_SHIFT		31
+#define	EHCI_INSNREG05_ULPI_PORTSEL_SHIFT		24
+#define	EHCI_INSNREG05_ULPI_OPSEL_SHIFT			22
+#define	EHCI_INSNREG05_ULPI_REGADD_SHIFT		16
+#define	EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT		8
+#define	EHCI_INSNREG05_ULPI_WRDATA_SHIFT		0
+
+/* read/write Registers in ULPI-PHY */
+
+u8 ulpi_direct_access(u8 port, u8 reg, int write, u8 value)
+{
+#if 0	// FIXME: we need to have the clocks and the EHCI controller enabled!
+	u32 val;
+	u32 cmd = (((u32)value) << EHCI_INSNREG05_ULPI_WRDATA_SHIFT); /* value to write */
+	if(reg > 0x3f || reg == 0x2f)
+		cmd |= (((u32)reg & 0xff) << EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT) | (0x2f << EHCI_INSNREG05_ULPI_REGADD_SHIFT);	/* extended address */
+	else
+		cmd |= (((u32)reg & 0x3f) << EHCI_INSNREG05_ULPI_REGADD_SHIFT);
+	cmd |= ((write? 0x02 : 0x03) << EHCI_INSNREG05_ULPI_OPSEL_SHIFT);
+	cmd |= (((u32)(port+1) & 3) << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT);	/* port counts 0,1,2 */
+	cmd |= (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT);	/* Start */
+	
+	writel(cmd, EHCI_BASE + EHCI_INSNREG05_ULPI);	/* write EHCI_INSNREG05_ULPI */
+	
+	// do {
+	udelay(100);	/* wait a little */
+	val = readl(EHCI_BASE + EHCI_INSNREG05_ULPI);	/* read EHCI_INSNREG05_ULPI */
+	/* do we need a timepout if the PHY chip is not present? */
+	// } while(!(val & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
+	return val;
+#else
+	return 0;
+#endif
+}
diff --git a/u-boot/board/goldelico/gta04/ulpi-phy.h b/u-boot/board/goldelico/gta04/ulpi-phy.h
new file mode 100644
index 0000000..7443c37
--- /dev/null
+++ b/u-boot/board/goldelico/gta04/ulpi-phy.h
@@ -0,0 +1,6 @@
+#ifndef _ULPI_PHY_H
+#define _ULPI_PHY_H
+
+u8 ulpi_direct_access(u8 port, u8 reg, int write, u8 value);
+
+#endif
diff --git a/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.c b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.c
new file mode 100644
index 0000000..e2b4d49
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.c
@@ -0,0 +1,142 @@
+/* u-boot driver for the OrtusTech COM37H3M05DTC LCM
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <twl4030.h>
+#include "../gta04/dssfb.h"
+#include "../gta04/jbt6k74.h"	// FIXME: change to display.h and make it more generic
+#include "COM37H3M05DTC.h"
+
+#ifdef CONFIG_OMAP3_BEAGLE_EXPANDER
+#define GPIO_STBY 158
+#else
+#define GPIO_STBY 20
+#endif
+
+// configure beagle board DSS for the COM37H3M05DTC
+
+#define DVI_BACKGROUND_COLOR		0x00fadc29	// rgb(250, 220, 41)
+
+#define DSS1_FCLK	432000000	// see figure 15-65
+#define PIXEL_CLOCK	22400000	// approx. 22.4 MHz (will be divided from 432 MHz)
+
+// all values are min ratings
+
+#define VDISP	640				// vertical active area
+#define VFP		2				// vertical front porch
+#define VS		1				// VSYNC pulse width (negative going)
+#define VBP		3				// vertical back porch
+#define VDS		(VS+VBP)		// vertical data start
+#define VBL		(VS+VBP+VFP)	// vertical blanking period
+#define VP		(VDISP+VBL)		// vertical cycle
+
+#define HDISP	480				// horizontal active area
+#define HFP		2				// horizontal front porch
+#define HS		2				// HSYNC pulse width (negative going)
+#define HBP		9				// horizontal back porch
+#define HDS		(HS+HBP)		// horizontal data start
+#define HBL		(HS+HBP+HFP)	// horizontal blanking period
+#define HP		(HDISP+HBL)		// horizontal cycle
+
+static const struct panel_config lcm_cfg = 
+{
+	.timing_h	= ((HBP-1)<<20) | ((HFP-1)<<8) | ((HS-1)<<0), /* Horizantal timing */
+	.timing_v	= ((VBP+0)<<20) | ((VFP+0)<<8) | ((VS-1)<<0), /* Vertical timing */
+	// negative clock edge
+	// negative sync pulse
+	// positive DE pulse
+	.pol_freq	= (1<<17)|(1<<16)|(0<<15)|(0<<14)|(1<<13)|(1<<12)|0x28,    /* Pol Freq */
+	.divisor	= (0x0001<<16)|(DSS1_FCLK/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */
+	.lcd_size	= ((HDISP-1)<<0) | ((VDISP-1)<<16), /* as defined by LCM */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BACKGROUND_COLOR
+};
+
+int jbt_reg_init(void)
+{
+	omap_request_gpio(GPIO_STBY);
+	omap_set_gpio_direction(GPIO_STBY, 0);		// output
+	return 0;
+}
+
+int jbt_check(void)
+{
+	return 0;
+}
+
+const char *jbt_state(void)
+{
+	return "?";
+}
+
+/* frontend function */
+int jbt6k74_enter_state(enum jbt_state new_state)
+{
+	return 0;
+}
+
+int jbt6k74_display_onoff(int on)
+{
+	omap_set_gpio_dataout(GPIO_STBY, on?1:0);	// on = no STBY
+	return 0;
+}
+
+int board_video_init(GraphicDevice *pGD)
+{
+	extern int get_board_revision(void);
+	
+	// FIXME: here we should pass down the GPIO(s)
+	
+	backlight_init();	// initialize backlight
+#define REVISION_XM 0
+	if(get_board_revision() == REVISION_XM) {
+		/* Set VAUX1 to 3.3V for GTA04E display board */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
+								/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
+								TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
+								TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		udelay(5000);
+	}
+	
+	// FIXME: here we should init the TSC and pass down the GPIO numbers and resistance values
+	
+	if(jbt_reg_init())	// initialize SPI
+		{
+		printf("No LCM connected\n");
+		return 1;
+		}
+	
+	dssfb_init(&lcm_cfg);
+	
+	printf("did board_video_init()\n");
+	return 0;
+}
+
diff --git a/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.h b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.h
new file mode 100644
index 0000000..87c7b57
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/COM37H3M05DTC.h
@@ -0,0 +1,6 @@
+#ifndef _COM37H3M05DTC_H
+#define _COM37H3M05DTC_H
+
+#define _BEAGLE_
+
+#endif
diff --git a/u-boot/board/goldelico/gta04b2/Makefile b/u-boot/board/goldelico/gta04b2/Makefile
new file mode 100644
index 0000000..9cecfa8
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= gta04b2.o COM37H3M05DTC.o trf7960.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o ../gta04/ulpi-phy.o  ../gta04/twl4030-additions.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/gta04b2/config.mk b/u-boot/board/goldelico/gta04b2/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/gta04b2/gta04b2.c b/u-boot/board/goldelico/gta04b2/gta04b2.c
new file mode 100644
index 0000000..3675a89
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/gta04b2.c
@@ -0,0 +1,24 @@
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "../gta04/gta04.h"
+#include "gta04b2.h"
+
+// make us initialize using both pinmux sets
+
+void muxinit(void)
+{
+	MUX_BEAGLE();
+	MUX_BEAGLE_EXPANDER();
+}
+
+#undef MUX_BEAGLE
+#define MUX_BEAGLE() muxinit()
+
+// take the original beagle.c code
+#include "../gta04/gta04.c"
diff --git a/u-boot/board/goldelico/gta04b2/gta04b2.h b/u-boot/board/goldelico/gta04b2/gta04b2.h
new file mode 100644
index 0000000..668f5f9
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/gta04b2.h
@@ -0,0 +1,34 @@
+// all pins on GTA04 expansion connector
+
+// GPIO -> GTA04-Pin -> Expander function
+
+#define MUX_BEAGLE_EXPANDER() \
+
+// FIXME: clean up so that we have the right PinMuxes
+#if 0
+
+MUX_VAL(CP(ETK_D0),		(IEN  | PTD | EN  | M1)) /*GPIO_17 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | EN  | M4)) /*GPIO_130 -> MCSPI3-CLK -> TRF*/\
+MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | EN  | M4)) /*GPIO_131 -> MCSPI3-SIMO -> TRF*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132 -> MCSPI3-SOMI -> TRF*/\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - Display STBY */\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | EN  | M4)) /*GPIO_159 - McBSP1-DR -> TRF EN2 */\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | EN  | M4)) /*GPIO_161 - McBSP1-FSX -> TRF EN */\
+
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133 -> UART3-RX (software)*/\
+MUX_VAL(CP(MMC2_DAT2),		(IDIS | PTU | EN  | M4)) /*GPIO_134 -> UART3-TX (software)*/\
+MUX_VAL(CP(MMC2_DAT3),		(IDIS | PTU | EN  | M1)) /*GPIO_135 -> MCSPI3-CS0*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTD | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTU | EN  | M4)) /*GPIO_138 - UART3-RTS (software) */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - UART3-CTS (software) */\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTU | EN  | M4)) /*GPIO_143 - UART2-RX */\
+MUX_VAL(CP(UART2_CTS),		(IDIS | PTU | EN  | M4)) /*GPIO_144 - UART2-CTS */\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTU | EN  | M4)) /*GPIO_145 - UART2-RTS */\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTU | EN  | M4)) /*GPIO_146 - UART2-TX */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | EN  | M4)) /*GPIO_156 - KEYIRQ -> TRF IRQ */\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - McBSP1-CLKX -> UART3 Powerdown */
+
+#endif
diff --git a/u-boot/board/goldelico/gta04b2/trf7960.c b/u-boot/board/goldelico/gta04b2/trf7960.c
new file mode 100644
index 0000000..fd90792
--- /dev/null
+++ b/u-boot/board/goldelico/gta04b2/trf7960.c
@@ -0,0 +1,945 @@
+/*
+ * (C) Copyright 2011
+ * H. Nikolaus Schaller, Golden Delicious Computers, hns@goldelico.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <spi.h>
+#include <asm/arch/gpio.h>
+#include <malloc.h>
+
+/* board specific configuration */
+
+struct trf7960 {
+	/*
+	 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+	 * with different number of chip selects (CS, channels):
+	 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+	 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+	 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+	 * McSPI4 has 1 CS (bus 3, cs 0)
+	 */
+	int bus;
+	int cs;
+	int clock;
+	int irq;	/* GPIO that receives IRQ; use -1 if we have no IRQ */
+	int en;		/* GPIO that controls EN; use -1 if hardwired */
+	int en2;	/* GPIO that controls EN2; use -1 if hardwired (use same if both are parallel) */
+	int vio;	/* specify 10*VIO i.e. 18 for 1.8V, 33 for 3.3V */
+	struct spi_slave *slave;
+	/* internal */
+	int done;	/* done interrupt flag */
+	uchar *datapointer;	/* RX/TX data pointer */
+	int bytes;		/* number of remaining bytes to transmit (may be negative) */
+};
+
+/* low level functions */
+
+#define TRF7960_REG_CSC		0x00	/* Chip Status control (R/W) */
+#define TRF7960_REG_ISOC	0x01	/* ISO control (R/W) */
+#define TRF7960_REG_ISO14443BTXOPT	0x02	/* TX Options (R/W) */
+#define TRF7960_REG_ISO14443AHBROPT	0x03	/* High Bitrate Options (R/W) */
+#define TRF7960_REG_TXTIMERMSB	0x04	/* TX Timer (R/W) */
+#define TRF7960_REG_TXTIMERLSB	0x05	/* TX Timer (R/W) */
+#define TRF7960_REG_TXPULSEC	0x06	/* TX Pulse Lenght control (R/W) */
+#define TRF7960_REG_RXNRWAIT	0x07	/* RX no response wait (R/W) */
+#define TRF7960_REG_RXWAIT	0x08	/* RX wait time (after TX) (R/W) */
+#define TRF7960_REG_MODCLK	0x09	/* Modulator and SYS_CLK (R/W) */
+#define TRF7960_REG_RXSPECIAL	0x0a	/* RX special setting (R/W) */
+#define TRF7960_REG_REGIO	0x0b	/* Regulator and IO control (R/W) */
+#define TRF7960_REG_IRQ	0x0c	/* IRQ status (R) */
+#define TRF7960_REG_IRQMASK	0x0d	/* Collision position (MSB) and Interrupt Mask (R/W) */
+#define TRF7960_REG_COLLISION	0x0e	/* Collision position (LSB) (R) */
+#define TRF7960_REG_RSSI	0x0f	/* RSSI levels and oscillator status (R) */
+#define TRF7960_REG_FIFO_STATUS	0x1c	/* FIFO status (R) */
+#define TRF7960_REG_FIFO_TXLEN1	0x1d	/* TX length byte 1 (R/W) */
+#define TRF7960_REG_FIFO_TXLEN2	0x1e	/* TX length byte 2 (R/W) */
+#define TRF7960_REG_FIFO_DATA	0x1f	/* FIFO I/O register (R/W) */
+
+/* FIXME: add bit masks for these registers */
+
+#define TRF7960_CMD_IDLE	0x00
+#define TRF7960_CMD_INIT	0x03
+#define TRF7960_CMD_RESET	0x0f		/* reset FIFO */
+#define TRF7960_CMD_TX_NOCRC	0x10
+#define TRF7960_CMD_TX_CRC	0x11	/* TX with CRC */
+#define TRF7960_CMD_TX_DELAYED_NOCRC	0x12
+#define TRF7960_CMD_TX_DELAYED_CRC	0x13
+#define TRF7960_CMD_TX_NEXT_SLOT	0x14	/* send EOF / next slot */
+#define TRF7960_CMD_RX_BLOCK	0x16	/* block receiver */
+#define TRF7960_CMD_RX_ENABLE	0x17	/* enable receiver */
+#define TRF7960_CMD_TEST_RF_INT	0x18
+#define TRF7960_CMD_TEST_RF_EXT	0x19
+#define TRF7960_CMD_RX_GAIN_ADJUST	0x1a
+
+/* first byte sent through SPI */
+#define TRF7960_COMMAND		0x80
+#define TRF7960_ADDRESS		0x00	/* combine with READ/WRITE and optionally CONTINUE */
+#define TRF7960_READ		0x40
+#define TRF7960_WRITE		0x00
+#define TRF7960_CONTINUE	0x20
+
+/* power modes (increasing power demand) */
+#define TRF7960_POWER_DOWN	0
+#define TRF7960_POWER_60kHz	1		/* VDD_X available, 60 kHz */
+#define TRF7960_POWER_STANDBY	2	/* 13.56 MHz osc. on, SYS_CLK available; regulators in low power */
+#define TRF7960_POWER_ACTIVE	3	/* 13.56 MHz osc. on, SYS_CLK available; regulators active */
+#define TRF7960_POWER_RX	4	/* RX active */
+#define TRF7960_POWER_RXTX_HALF	5	/* RX+TX active; half power mode */
+#define TRF7960_POWER_RXTX_FULL	6	/* RX+TX active; full power mode */
+
+/* protocols */
+#define TRF7960_PROTOCOL_ISO15693_LBR_1SC_4		0x00
+#define TRF7960_PROTOCOL_ISO15693_LBR_1SC_256	0x01
+#define TRF7960_PROTOCOL_ISO15693_HBR_1SC_4		0x02
+#define TRF7960_PROTOCOL_ISO15693_HBR_1SC_256	0x03
+#define TRF7960_PROTOCOL_ISO15693_LBR_2SC_4		0x04
+#define TRF7960_PROTOCOL_ISO15693_LBR_2SC_256	0x05
+#define TRF7960_PROTOCOL_ISO15693_HBR_2SC_4		0x06
+#define TRF7960_PROTOCOL_ISO15693_HBR_2SC_256	0x07
+#define TRF7960_PROTOCOL_ISO14443A_BR_106	0x08
+#define TRF7960_PROTOCOL_ISO14443A_BR_212	0x09
+#define TRF7960_PROTOCOL_ISO14443A_BR_424	0x0a
+#define TRF7960_PROTOCOL_ISO14443A_BR_848	0x0b
+#define TRF7960_PROTOCOL_ISO14443B_BR_106	0x0c
+#define TRF7960_PROTOCOL_ISO14443B_BR_212	0x0d
+#define TRF7960_PROTOCOL_ISO14443B_BR_424	0x0e
+#define TRF7960_PROTOCOL_ISO14443B_BR_848	0x0f
+#define TRF7960_PROTOCOL_TAGIT	0x13
+
+/* */
+
+#if 1	/* fix HW problem with TRF7960 being in "SPI without SS" mode */
+
+#define spi_xfer bitbang_spi_xfer
+#define spi_claim_bus(X)
+#define spi_release_bus(X)
+
+#define McSPI3_CLK	130
+#define McSPI3_SIMO	131
+#define McSPI3_SOMI	132
+
+#define HALFBIT 1	/* 1us gives approx. 500kHz clock */
+
+static int bitbang_spi_xfer(struct spi_slave *slave, int bitlen, uchar writeBuffer[], uchar readBuffer[], int flags)
+{ /* generates bitlen+2 clock pulses */
+	static int first=1;
+	int bit;
+	uchar wb=0;
+	uchar rb=0;
+	if(first) { /* if not correctly done by pinmux */
+		omap_set_gpio_direction(McSPI3_CLK, 0);
+		omap_set_gpio_direction(McSPI3_SIMO, 0);
+		omap_set_gpio_direction(McSPI3_SOMI, 1);
+		omap_set_gpio_dataout(McSPI3_CLK, 0);
+		omap_set_gpio_dataout(McSPI3_SIMO, 0);	/* send out constant 0 bits (idle command) */
+		first=0;
+		udelay(100);
+	}
+#if 0
+	printf("bitbang_spi_xfer %d bits\n", bitlen);
+#endif
+	if(flags & SPI_XFER_BEGIN) {
+		omap_set_gpio_dataout(McSPI3_CLK, 1);
+		udelay(HALFBIT);	/* may be optional (>50ns) */
+		omap_set_gpio_dataout(McSPI3_SIMO, 1);	/* start condition (data transision while clock=1) */
+		udelay(HALFBIT);		
+	}
+	omap_set_gpio_dataout(McSPI3_CLK, 0);
+	for(bit=0; bit < bitlen; bit++)
+		{ /* write data */
+			if(bit%8 == 0)
+				wb=writeBuffer[bit/8];
+			omap_set_gpio_dataout(McSPI3_SIMO, (wb&0x80)?1:0);	/* send MSB first */
+			wb <<= 1;
+			udelay(HALFBIT);
+			omap_set_gpio_dataout(McSPI3_CLK, 1);
+			udelay(HALFBIT);
+			omap_set_gpio_dataout(McSPI3_CLK, 0);
+			rb = (rb<<1) | omap_get_gpio_datain(McSPI3_SOMI);	/* sample on falling edge and receive MSB first */
+			if(bit%8 == 7)
+				readBuffer[bit/8]=rb;
+		}
+	if(flags & SPI_XFER_END) {
+		omap_set_gpio_dataout(McSPI3_SIMO, 1);	/* set data to 1 */
+		udelay(HALFBIT);
+		omap_set_gpio_dataout(McSPI3_CLK, 1);
+		udelay(HALFBIT);
+		omap_set_gpio_dataout(McSPI3_SIMO, 0);	/* stop condition (data transision while clock=1) */
+		udelay(HALFBIT);	/* may be optional (>50ns) */
+		omap_set_gpio_dataout(McSPI3_CLK, 0);
+		udelay(HALFBIT);
+	}
+	return 0;
+}
+
+#endif
+					 
+static inline int readRegister(struct trf7960 *device, uchar addr)
+{
+	uchar writeBuffer[2];
+	uchar readBuffer[2];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_READ | addr;
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 16, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return readBuffer[1];
+}
+
+static inline int writeRegister(struct trf7960 *device, uchar addr, uchar byte)
+{
+	uchar writeBuffer[2];
+	uchar readBuffer[2];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_WRITE | addr;
+	writeBuffer[1] = byte;
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 2*8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return 0;
+}
+
+static inline int sendCommand(struct trf7960 *device, uchar cmd)
+{
+	uchar writeBuffer[1];
+	uchar readBuffer[1];
+	writeBuffer[0] = TRF7960_COMMAND | cmd;
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return 0;
+}
+
+/* mid level  (should be partially mapped to sysfs) */
+
+int resetIRQ(struct trf7960 *device)
+{
+	uchar writeBuffer[3];
+	uchar readBuffer[3];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_IRQ;
+	writeBuffer[1] = 0;	// dummy read
+	writeBuffer[2] = 0;	// dummy read
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 3*8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+#if 0
+	{
+	int i;
+	for(i=0; i<3; i++)
+		printf("rb[i]=%02x\n", readBuffer[i]);
+	}
+#endif
+	return readBuffer[1];
+}
+
+int getCollisionPosition(struct trf7960 *device)
+{
+	uchar writeBuffer[3];
+	uchar readBuffer[3];
+	writeBuffer[0] = TRF7960_ADDRESS | TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_IRQMASK;
+	writeBuffer[1] = 0;	// dummy read
+	writeBuffer[2] = 0;	// dummy read
+	spi_claim_bus(device->slave);
+	if(spi_xfer(device->slave, 3*8, writeBuffer, readBuffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+	spi_release_bus(device->slave);
+	return ((readBuffer[1]&0xc0)<<2) | readBuffer[2];	// combine into 10 bits
+}
+
+/* how to handle spi_claim_bus during irq handler? */
+
+int prepareIrq(struct trf7960 *device, uchar *data, unsigned int bytes)
+{
+#if 1
+	printf("prepareIrq data=%p bytes=%u\n", data, bytes);
+#endif
+#if 0
+	{
+	//	uchar irq=readRegister(device, TRF7960_REG_IRQ);
+	uchar irq=resetIRQ(device);
+	printf("    irq-status=%02x\n", irq);		
+	}
+#endif
+#if 0
+	while(device->irq >= 0 && omap_get_gpio_datain(device->irq)) {
+		printf("prepareIrq: IRQ pin already active!\n");
+		resetIRQ(device);
+	}
+#endif
+	device->done=0;	/* not yet done */
+	device->datapointer=data;
+	device->bytes=bytes;
+	/* enable IRQ */
+	return 0;
+}
+
+void handleInterrupt(struct trf7960 *device)
+{ /* process interrupt */
+	unsigned char buffer[12];
+//	uchar irq=readRegister(device, TRF7960_REG_IRQ);
+	uchar irq=resetIRQ(device);
+	if(!irq)
+		return;	/* false alarm or waitIrq */
+	if(device->done)
+		return;	/* unprocessed previous interrupt */
+#if 0
+	printf("handleirq %02x\n", irq);
+#endif
+	device->done=irq;	/* set done flag with interrupt flags */
+#if 0	// read again test (did a read reset the IRQ flags?)
+	irq=readRegister(device, TRF7960_REG_IRQ);
+	printf("handleirq %02x %02x\n", device->done, irq);
+	irq=device->done;	/* restore */
+#endif
+#if 0
+	udelay(5);
+	if(device->irq >= 0 && omap_get_gpio_datain(device->irq))
+		printf("  IRQ pin still/again active!\n");
+#endif
+	if(irq & 0x80) { /* end of TX */
+#if 1
+		printf("handleirq end of TX %02x\n", irq);
+#endif
+		sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */
+		return;
+		}
+	if(irq & 0x02) { /* collision occurred */
+		int position;
+#if 1
+		printf("handleirq collision %02x\n", irq);
+#endif
+		// FIXME: combine into single message
+		sendCommand(device, TRF7960_CMD_RX_BLOCK);	/* block RX */
+		position=getCollisionPosition(device);
+#if 1
+		printf("position=%d\n", position);
+#endif
+		// number of valid bytes is collpos - 32
+		// read bytes
+		// handle broken byte
+		sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */
+	}
+	else if(irq & 0x40) { /* end of RX */
+		uchar fifosr=readRegister(device, TRF7960_REG_FIFO_STATUS);
+		uchar unread=(fifosr&0xf) + 1;
+#if 1
+		printf("handleirq end of RX %02x fifosr=%02x unread=%d\n", irq, fifosr, unread);
+#endif
+		int n = device->bytes <= unread ? device->bytes : unread;	/* limit to remaining bytes in FIFO or buffer */
+		buffer[0] = TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_FIFO_DATA;	/* continuous read from FIFO */
+		memset(&buffer[1], 0, sizeof(buffer)/sizeof(buffer[0])-1);	/* clear buffer so that we don't write garbage */
+		if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(2 + n), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)	/* we need 8 more clocks to receive the last byte */
+			return;	/* spi error */
+		memcpy(device->datapointer, &buffer[1], n);	/* buffer[0] are the first 8 bits shifted out while we did send the command */
+		device->datapointer += n;
+		device->bytes -= n;
+#if 1
+		if(device->bytes > 0)
+			printf("  remaining buffer=%d\n", device->bytes);
+#endif
+		// handle broken byte
+		sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */		
+	}
+	else if(irq & 0x20) { /* FIFO interrupt */
+		int n = device->bytes <= 9 ? device->bytes : 9;	/* limit to 9 bytes */
+#if 1
+		printf("handleirq fifo request %02x (%d bytes remaining)\n", irq, device->bytes);
+#endif
+		if(n > 0) {
+			if(irq & 0x80) { /* write next n bytes to FIFO (up to 9 or as defined by bytes) */
+#if 1
+				printf("write more (%d)\n", n);
+#endif
+				buffer[0] = TRF7960_WRITE | TRF7960_CONTINUE | TRF7960_REG_FIFO_DATA;	/* continuous write to FIFO */
+				memcpy(&buffer[1], device->datapointer, n);
+				if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(1 + n), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+					return;	/* spi error */
+				device->datapointer += n;
+				device->bytes -= n;				
+			} else { /* read next 9 bytes from FIFO in one sequence */
+#if 1
+				printf("read more (%d)\n", n);
+#endif
+				buffer[0] = TRF7960_READ | TRF7960_CONTINUE | TRF7960_REG_FIFO_DATA;	/* continuous read from FIFO */
+				memset(&buffer[1], 0, sizeof(buffer)/sizeof(buffer[0])-1);	/* clear buffer so that we don't write garbage */
+				if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(2 + n), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)	/* we need 8 more clocks to receive the last byte */
+					return;	/* spi error */
+				memcpy(device->datapointer, &buffer[1], n);	/* buffer[0] are the first 8 bits shifted out while we did send the command */
+				device->datapointer += n;
+				device->bytes -= n;
+			}
+			device->done=0;	/* don't notify successful data trandfer as 'done' status */
+		}
+		// else some error (FIFO interrupt but no data available or buffer is full
+	}
+}
+
+void waitIrq(struct trf7960 *device)
+{ /* wait for IRQ */
+#if 0
+	printf("waitIrq %d\n", device->irq);
+#endif
+	if(device->irq >= 0)	{ /* check IRQ pin */
+		int cnt=2000;	// software timeout
+		while(!omap_get_gpio_datain(device->irq) && cnt-- > 0)
+			udelay(500); /* wait for IRQ pin */
+		handleInterrupt(device);
+	}
+	else { /* poll interrupt register to check for interrupts */
+		while(!device->done)
+			handleInterrupt(device);
+	}
+#if 0
+	printf("waitIrq -> %02x\n", device->done);
+#endif
+}
+
+int setPowerMode(struct trf7960 *device, int mode)
+{ /* control power modes */
+	int status = 0;
+#if 1
+	printf("setPowerMode %d\n", mode);
+#endif
+	if(mode < TRF7960_POWER_DOWN || mode > TRF7960_POWER_RXTX_FULL)
+		return -1;
+	if(device->en >= 0)
+		omap_set_gpio_direction(device->en, 0);		/* make output */
+	if(device->en2 >= 0)
+		omap_set_gpio_direction(device->en2, 0);	/* make output */
+	if(device->irq >= 0)
+		omap_set_gpio_direction(device->irq, 1);	/* make input */
+	if(mode == TRF7960_POWER_DOWN) {
+		if(device->slave) {
+			spi_free_slave(device->slave);
+			device->slave = NULL;
+		}
+		if(device->en >= 0)
+			omap_set_gpio_dataout(device->en, 0);
+		if(device->en2 >= 0 && device->en != device->en2)
+			omap_set_gpio_dataout(device->en2, 0);	/* not tied togehter */
+	}
+	else if(mode == TRF7960_POWER_60kHz) {
+		if(device->en >= 0 && device->en2 >= 0 && device->en == device->en2)
+			return -1;	/* can't control them separately */
+		if(device->en >= 0)
+			omap_set_gpio_dataout(device->en, 0);
+		if(device->en2 >= 0)
+			omap_set_gpio_dataout(device->en2, 1);
+	}
+	else {
+		if(device->en >= 0)
+			omap_set_gpio_dataout(device->en, 1);
+		if(!device->slave) {
+			device->slave = spi_setup_slave(device->bus, device->cs, device->clock, SPI_MODE_0);
+			if(!device->slave)
+				return -1;	// failed			
+		}
+		udelay(1000);	/* wait until we can read/write */
+		status = readRegister(device, TRF7960_REG_CSC);
+#if 1
+		printf("CSC = %02x\n", status);
+#endif
+		if(status < 0)
+			return status;	/* some error */
+		switch(mode) {
+			case TRF7960_POWER_STANDBY:
+				status |= 0x80;
+				break;
+			case TRF7960_POWER_ACTIVE:
+				status &= 0x5d;
+				break;
+			case TRF7960_POWER_RX:
+				status &= 0x5d;
+				status |= 0x02;
+				break;
+			case TRF7960_POWER_RXTX_HALF:
+				status &= 0x4f;
+				status |= 0x20;
+				break;
+			case TRF7960_POWER_RXTX_FULL:
+				status &= 0x4f;
+				status |= 0x30;
+				break;
+			default:
+				return -1;
+		}
+#if 1
+		printf("   => %02x\n", status);
+#endif
+		status = writeRegister(device, TRF7960_REG_CSC, status);
+		// init other registers (only if previous mode was 0 or 1)
+		if(device->vio < 27)
+			; /* set bit 5 in Reg #0x0b to decrease output resistance for low voltage I/O */
+		udelay(5000);	/* wait until reader has recovered (should depend on previous and current mode) */
+	}
+	return status;
+}
+
+int chooseProtocol(struct trf7960 *device, int protocol)
+{
+#if 1
+	printf("chooseProtocol %d\n", protocol);
+#endif
+	if((protocol < 0 || protocol >15) && protocol != 0x13)
+		return -1;
+	protocol |= readRegister(device, TRF7960_REG_CSC) & 0x80;	/* keep no RX CRC mode */
+	return writeRegister(device, TRF7960_REG_ISOC, protocol);
+}
+
+/* high level functions (protocol handlers) */
+/* the meaning of the flags and command codes in ISO15693 mode are described in TI document sloa141.pdf */
+
+int scanInventory(struct trf7960 *device, uchar flags, uchar length, void (*found)(struct trf7960 *device, uint64_t uid, int rssi))
+{ /* poll for tag uids and resolve collisions */
+	static uchar buffer[32];	/* shared rx/tx buffer */
+	uchar collisionslots[16];	/* up to 16 collision slots */
+	int collisions = 0;
+	uchar mask[8];	/* up to 8 mask bytes */
+	int slot;
+	int slots = (flags & (1<<5)) ? 1 : 16;	/* multislot flag */
+	
+	int masksize = (length + 7) / 8;	/* add one mask byte for each started 8 bits */
+	int pdusize = 3 + masksize;			/* flags byte + command byte + mask length byte + mask bytes */
+	
+	int protocol = readRegister(device, TRF7960_REG_ISOC) & 0x1f;
+
+	if((protocol & 0x18) == TRF7960_PROTOCOL_ISO15693_LBR_1SC_4)
+		;	/* ISO15693 */
+	// FIXME: implement different algorithms for other protocols
+	if((protocol & 0x1c) == TRF7960_PROTOCOL_ISO14443A_BR_106)
+		return -1;	/* ISO14443A */
+	if((protocol & 0x1c) == TRF7960_PROTOCOL_ISO14443B_BR_106)
+		return -1;	/* ISO14443B */
+	if(protocol == TRF7960_PROTOCOL_TAGIT)
+		return -1;	/* Tag-It */
+	if(protocol >= 0x10)
+		return -1;	/* undefined */
+#if 1
+	printf("inventoryRequest\n");
+#endif
+	spi_claim_bus(device->slave);
+	
+	if(writeRegister(device, TRF7960_REG_IRQMASK, 0x3f))	/* enable no-response interrupt */
+		return -1;
+
+	// write modulator control
+	/* writeRegister(device, TRF... 0x09, something); */
+	// set rxnoresponse timeout to 0x2f if bit1 is 0 (low data rate), 0x13 else (high data rate)
+	
+	buffer[0] = TRF7960_COMMAND | TRF7960_CMD_RESET;	/* reset FIFO */
+	buffer[1] = TRF7960_COMMAND | TRF7960_CMD_TX_CRC;	/* start TX with CRC */
+	buffer[2] = 0x3d;	/* continuous write to register 0x1d */
+	
+	buffer[5] = flags;	/* ISO15693 flags */
+	buffer[6] = 0x01;	/* ISO15693 inventory command */
+	if(flags & (1<<4)) { /* AFI */
+		buffer[7] = 0;	/* insert AFI value */
+		buffer[8] = length;	/* mask length in bits */
+		memcpy(&buffer[9], mask, masksize);	/* append mask */
+		pdusize++;
+	}
+	else {
+		buffer[7] = length;	/* mask length in bits */
+		memcpy(&buffer[8], mask, masksize);	/* append mask */		
+	}
+	buffer[3] = pdusize >> 8;
+	buffer[4] = pdusize << 4;
+	prepareIrq(device, &buffer[5+12], pdusize-12);
+	if(pdusize > 12)
+		pdusize=12; /* limit initial transmission - remainder is sent by interrupt handler */
+#if 0
+	printf("length = %d\n", length);
+	printf("masksize = %d\n", masksize);
+	printf("pdusize = %d\n", pdusize);
+	printf("bitsize = %d\n", 8*sizeof(buffer[0])*(5 + pdusize));
+#endif
+	if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(5 + pdusize), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0)
+		return -1;
+#if 0
+	printf("cmd sent\n");
+#endif
+	waitIrq(device);	/* wait for TX interrupt */
+#if 0
+	printf("tx done %02x\n", device->done);
+#endif
+	if(!(device->done & 0x80)) {
+#if 1
+		printf(" unknown TX interrupt %02x\n", device->done);
+#endif
+		return -1;
+	}
+	collisions=0;
+	for(slot=0; slot < slots; slot++) { /* repeat for all time slots */
+		int rssi;
+#if 0
+		printf("slot %d\n", slot);
+#endif
+		prepareIrq(device, buffer, 10);	/* prepare for RX of tag id (2 bytes status + 8 bytes UID) */
+		waitIrq(device);	/* wait for RX interrupt */
+#if 1
+		printf("rx[%d] done %02x", slot, device->done);
+#endif
+		rssi = readRegister(device, TRF7960_REG_RSSI) & 0x3f;
+#if 0
+		printf(" rssi=%02o", rssi);	/* print 2 octal digits for AUX and Active channel */
+#endif
+		if(device->done & 0x02) { /* collision */
+#if 1
+			printf(" collision\n");
+#endif
+			collisionslots[collisions++]=slot;	/* remember slot number */
+		}
+		else if(device->done & 0x01) {
+			/* ignore no response timeout */
+#if 1
+			printf(" no response\n");
+#endif
+		}
+		/* check for other errors */
+		else if(device->done & 0x40) { /* RX done - FIFO already reset */
+			union {
+				uint64_t uid;
+				char b[sizeof(uint64_t)];
+			} uid;
+#if 0
+			printf(" valid id received\n");
+#endif
+			// buffer[0] and buffer[1] appear to be status flags and 00 if ok
+			memcpy(uid.b, &buffer[2], sizeof(uid.uid));	/* extract UID */
+			(*found)(device, le64_to_cpu(uid.uid), rssi);	/* notify caller */
+		}
+		else {
+#if 1
+			printf(" unknown condition %02x\n", device->done);
+#endif
+			break;	/* unknown interrupt reason */
+		}
+		if(!(device->done & 0x40))
+			sendCommand(device, TRF7960_CMD_RESET);	/* reset FIFO */
+		if(slots == 16) { /* send EOF only in ISO15693 multislot Inventory command */
+			sendCommand(device, TRF7960_CMD_RX_BLOCK);
+			sendCommand(device, TRF7960_CMD_RX_ENABLE);
+			sendCommand(device, TRF7960_CMD_TX_NEXT_SLOT);
+		}
+	}
+	if(slots == 16 ) {
+		int i;
+#if 1
+		printf("did have %d collisions\n", collisions);
+#endif
+		for(i=0; i<collisions; i++) { /* loop over all slots with collision */
+			// generate new mask (increased length by 4) from collision slot numbers
+			// inventoryRequest(new mask, length+4)
+		}
+	}
+	// FIXME: how to handle collision in single slot mode?
+	// disable irq
+	spi_release_bus(device->slave);
+	return 0;
+}
+
+int readBlocks(struct trf7960 *device, uchar flags, uint64_t uid, uchar firstBlock, uchar blocks, uchar *data)
+{ /* read single/multiple blocks */
+	static uchar buffer[32];	/* shared rx/tx buffer */
+	char *rxbuf;
+	int pdusize = 4 + (uid?sizeof(uid):0);			/* flags byte + command byte + optional uid + firstblock + #blocks */
+#if 1
+	printf("readBlocks\n");
+#endif
+	if(blocks == 0)
+		return 0;	/* no blocks */
+	spi_claim_bus(device->slave);
+	
+	if(writeRegister(device, TRF7960_REG_IRQMASK, 0x3f))	/* enable no-response interrupt */
+		return -1;
+	
+	rxbuf=malloc(2+32*blocks);	// allocate enough memory for storing 32*blocks bytes
+	if(!rxbuf)
+		return -1;	// can't allocate
+
+	buffer[0] = TRF7960_COMMAND | TRF7960_CMD_RESET;	/* reset FIFO */
+	buffer[1] = TRF7960_COMMAND | TRF7960_CMD_TX_CRC;	/* start TX with CRC */
+	buffer[2] = 0x3d;	/* continuous write to register 0x1d */
+	
+	buffer[5] = flags;	/* ISO15693 flags */
+	buffer[6] = blocks > 1 ? 0x23 : 0x20;	/* ISO15693 read single or multiple blocks command */
+	if(uid) { /* include uid if not 0LL */
+		union {
+			uint64_t uid;
+			char b[sizeof(uint64_t)];
+		} uid2;
+		uid2.uid=cpu_to_le64(uid);
+		memcpy(&buffer[7], uid2.b, sizeof(uid2.b));
+		pdusize=2+8+1;
+		buffer[15]=firstBlock;
+		if(blocks > 1) {
+			buffer[16]=blocks-1;
+			pdusize++;
+		}
+	} else { /* no UID */
+		pdusize=2+1;
+		buffer[7]=firstBlock;
+		if(blocks > 1) {
+			buffer[8]=blocks-1;
+			pdusize++;
+		}
+	}
+	buffer[3] = pdusize >> 8;
+	buffer[4] = pdusize << 4;
+	prepareIrq(device, &buffer[5+12], pdusize-12);
+	if(pdusize > 12)
+		pdusize=12; /* limit initial transmission - remainder is sent by interrupt handler */
+#if 1
+	printf("firstBlock = %d\n", firstBlock);
+	printf("blocks = %d\n", blocks);
+	printf("pdusize = %d\n", pdusize);
+	printf("bitsize = %d\n", 8*sizeof(buffer[0])*(5 + pdusize));
+#endif
+	if(spi_xfer(device->slave, 8*sizeof(buffer[0])*(5 + pdusize), buffer, buffer, SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+		free(rxbuf);
+		return -1;
+	}
+#if 1
+	printf("cmd sent\n");
+#endif
+	waitIrq(device);	/* wait for TX interrupt */
+#if 1
+	printf("tx done %02x\n", device->done);
+#endif
+	if(!device->done & 0x80) {
+#if 1
+		printf(" unknown TX interrupt %02x\n", device->done);
+#endif
+		free(rxbuf);
+		return -1;
+	}
+	// FIXME: the first bytes received are not data bytes but the received PDU!
+	// should we introduce some chained mbuf scheme???
+	prepareIrq(device, rxbuf, 2+32*blocks);	/* prepare for receiving n*32 bytes RX */
+	waitIrq(device);	/* wait for RX interrupt */
+	// check for standard RX done or Collision or timeout or other errors
+#if 1
+	printf("rx done %02x\n", device->done);
+	if(device->done & 0x01)
+		printf("  timeout\n");
+	if(device->done & 0x02)
+		printf("  collision\n");
+#endif
+	if(rxbuf[0] != 0)
+		printf("  rx flags %02x\n", rxbuf[0]);
+	// if ok, read the flags byte from the received PDU to determine potential errors
+	memcpy(data, rxbuf+2, 32*blocks);	// copy payload
+	free(rxbuf);
+	return 0;
+}
+
+int writeBlocks(struct trf7960 *device, uchar flags, uint64_t uid, uchar firstBlock, uchar blocks, uchar *data)
+{ /* write single/multiple blocks */
+	return -1;
+}
+ 
+/* this all below belongs to GUI/board driver */
+
+/* define BeagleBoard + Expander hardware IF */
+
+struct trf7960 rfid_board = {
+	.bus = 2,	/* McSPI3 */
+	.cs = 0,	/* CS0 */
+	.clock = 1000000,	/* clock speed */
+	.irq = 156,	/* KEYIRQ/GPIO156 */
+	.en = 161,
+	.en2 = 159,
+	.vio = 18	/* we use 1.8V IO */
+};
+
+static int numfound;
+
+static void found(struct trf7960 *device, uint64_t uid, int rssi)
+{
+	extern void status_set_status(int value);
+//	int i;
+	numfound++;
+	printf("UID = %llX", uid);
+//	for(i=0; i < 8; i++)
+//		printf("%02x", (uid>>(8*(7-i))));
+	printf(" rssi = %d/%d\n", rssi/8, rssi%8);
+}
+
+static int do_rfid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int len;
+	static int statusinit;
+	extern void status_set_status(int value);
+	extern int status_init(void);
+	
+	if (argc < 2) {
+		printf ("rfid: missing subcommand.\n");
+		return (-1);
+	}
+	
+	if (!statusinit) { // initialize status LEDs for scan/loop subcommands
+		status_init();
+		statusinit=1;
+	}
+	
+	len = strlen (argv[1]);
+	if (strncmp ("po", argv[1], 2) == 0) {
+		return setPowerMode(&rfid_board, simple_strtoul(argv[2], NULL, 10)) < 0?1:0;
+		
+#if 1
+	} else if (strncmp ("re", argv[1], 2) == 0) {
+		int r;
+		for(r=0; r <= 0x1f; r++)
+			printf("%02x: %02x\n", r, readRegister(&rfid_board, r));
+	} else if (strncmp ("co", argv[1], 2) == 0) {
+		return 1;
+	} else if (strncmp ("rw", argv[1], 2) == 0) {
+#define MAX_SPI_BYTES 32
+		static int   		bitlen;
+		static uchar 		dout[MAX_SPI_BYTES];
+		static uchar 		din[MAX_SPI_BYTES];
+		char  *cp = 0;
+		uchar tmp;
+		int   j;
+		int   rcode = 0;
+		if (argc >= 3)
+			bitlen = simple_strtoul(argv[2], NULL, 10);
+		if (argc >= 4) {
+			cp = argv[3];
+			for(j = 0; *cp; j++, cp++) {
+				tmp = *cp - '0';
+				if(tmp > 9)
+					tmp -= ('A' - '0') - 10;
+				if(tmp > 15)
+					tmp -= ('a' - 'A');
+				if(tmp > 15) {
+					printf("Hex conversion error on %c\n", *cp);
+					return 1;
+				}
+				if((j % 2) == 0)
+					dout[j / 2] = (tmp << 4);
+				else
+					dout[j / 2] |= tmp;
+			}
+		}
+		if ((bitlen < 0) || (bitlen >  (MAX_SPI_BYTES * 8))) {
+			printf("Invalid bitlen %d\n", bitlen);
+			return 1;
+		}
+		
+		if(spi_xfer(rfid_board.slave, bitlen, dout, din,
+					SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+			printf("Error during SPI transaction\n");
+			rcode = 1;
+		} else {
+			for(j = 0; j < ((bitlen + 7) / 8); j++) {
+				printf("%02X", din[j]);
+			}
+			printf("\n");
+		}		
+#endif
+	} else if (strncmp ("sc", argv[1], 2) == 0) {
+		numfound=0;
+		setPowerMode(&rfid_board, TRF7960_POWER_RXTX_FULL);
+		chooseProtocol(&rfid_board, 0x02);	/* ISO15693 26kbps one-sub 1-out-of-4 (default) */
+		scanInventory(&rfid_board, 0x06 /* 0x26 1slot */, 0, &found);
+		setPowerMode(&rfid_board, TRF7960_POWER_STANDBY);
+		status_set_status(numfound > 0?0x3f:0x00);	/* LEDs on/off */
+	} else if (strncmp ("lo", argv[1], 2) == 0) {
+		setPowerMode(&rfid_board, TRF7960_POWER_RXTX_FULL);
+		chooseProtocol(&rfid_board, 0x02);	/* ISO15693 26kbps one-sub 1-out-of-4 (default) */
+		while(!tstc()) { // scan until key is pressed
+			numfound=0;
+			scanInventory(&rfid_board, 0x06 /* 0x26 1slot */, 0, &found);
+			status_set_status(numfound);	/* LEDs binary count */
+			udelay(300*1000);	// wait 0.3 seconds
+		}
+		setPowerMode(&rfid_board, TRF7960_POWER_STANDBY);
+		if(tstc())
+			getc();
+	} else if (strncmp ("rb", argv[1], 2) == 0) { // read block
+		uint64_t uid=0;	/* set by =uid (hex) */
+		uchar firstBlock=0;	/* set by next parameter */
+		uchar blocks=1;	/* set by +n parameter (decimal) */
+		uchar *data;
+		int r;
+		int i=2;
+		if(argv[i] && argv[i][0] == '=') {
+			uid=simple_strtoull(argv[i]+1, NULL, 16);
+			i++;
+		}
+		if(argv[i] && argv[i][0] == '+') {
+			blocks=simple_strtoul(argv[i]+1, NULL, 10);
+			i++;
+		}
+		if(argv[i]) {
+			firstBlock=simple_strtoul(argv[i], NULL, 10);
+			i++;
+		}
+		data=malloc(32*blocks);	// allocate enough memory for storing 32*blocks bytes!
+		if(!data) {
+			printf ("rfid %s: can't allocate buffer for %d blocks\n", argv[1], blocks);			
+			return (1);
+		}
+		setPowerMode(&rfid_board, TRF7960_POWER_RXTX_FULL);
+		chooseProtocol(&rfid_board, 0x02);	/* ISO15693 26kbps one-sub 1-out-of-4 (default) */
+		r=readBlocks(&rfid_board, uid > 0?0x16:0x06, uid, firstBlock, blocks, data);
+		printf("r=%d\n", r);
+		for(i=0; i<blocks; i++) { // print data (hex)
+			int b;
+			for(b=0; b<32; b++) {
+				if(b%16 == 0) {
+					if(b == 0)
+						printf("%03d: ", firstBlock+i);
+					else
+						printf("     ");					
+				}
+				printf("%02x", data[32*i+b]);
+				if(b%16 == 15)
+					printf("\n");
+			}
+		}
+		setPowerMode(&rfid_board, TRF7960_POWER_STANDBY);
+		free(data);
+	} else if (strncmp ("wb", argv[1], 2) == 0) {
+		// FIXME: write block
+	} else {
+		printf ("rfid: unknown operation: %s\n", argv[1]);
+	}
+	
+	return (0);
+}
+
+U_BOOT_CMD(
+	rfid,	5,	1,	do_rfid,
+	"RFID utility command",
+	"po[wer] n - set power state (0=off, 1=60kHz, 2=standby, 3=active, 4=rx, 5=half, 6=full)\n"
+	"re[gisters] - read registers\n"
+    "rw [bitlen [hexvalue]] - read/write SPI data block\n"
+    "sc[an] - scan inventory\n"
+	"lo[op] - permanently scan inventory until key is pressed\n"
+    "rb[lock] [=uid] [+n] [first] - read n (default=1) 32 byte block(s) starting at first\n"
+    "wb[lock] [=uid] [+n] first hexvalue - write n (default=1) 32 byte block(s) starting at first\n"
+);
diff --git a/u-boot/board/goldelico/panda-hybrid/Makefile b/u-boot/board/goldelico/panda-hybrid/Makefile
new file mode 100644
index 0000000..849e243
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= pandahyb.o 
+#../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/systest.o ../gta04/commands.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/goldelico/panda-hybrid/config.mk b/u-boot/board/goldelico/panda-hybrid/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/goldelico/panda-hybrid/pandahyb.c b/u-boot/board/goldelico/panda-hybrid/pandahyb.c
new file mode 100644
index 0000000..1ff467a
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/pandahyb.c
@@ -0,0 +1,31 @@
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include "../../ti/panda/panda.h"
+#include "pandahyb.h"
+
+/*
+ somehow redefine:
+ const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4 Panda\n"
+};
+*/
+
+// tamper with set_muxconf_regs() to extend its functionality
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_inherited(void);
+
+void set_muxconf_regs(void)
+{
+	set_muxconf_regs_inherited();	// call "superclass method"
+	do_set_mux(CONTROL_PADCONF_CORE, hybrid_padconf_array,
+			   sizeof(hybrid_padconf_array) /
+			   sizeof(struct pad_conf_entry));
+	
+}
+
+// rename original definition in panda.c
+#define set_muxconf_regs set_muxconf_regs_inherited
+
+#include "../../ti/panda/panda.c"
diff --git a/u-boot/board/goldelico/panda-hybrid/pandahyb.h b/u-boot/board/goldelico/panda-hybrid/pandahyb.h
new file mode 100644
index 0000000..4501239
--- /dev/null
+++ b/u-boot/board/goldelico/panda-hybrid/pandahyb.h
@@ -0,0 +1,32 @@
+// FIXME: Panda has a different initialization scheme!
+// we have to extend const struct pad_conf_entry core_padconf_array[]
+
+#include <asm/io.h>
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry hybrid_padconf_array[] = {
+	// add entries
+};
+	
+#if 0
+
+#define MUX_BEAGLE_HYBRID() \
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*GPIO_130 -> MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*GPIO_131 -> MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*GPIO_132 -> MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*GPIO_133 -> MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*GPIO_134 -> MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*GPIO_135 -> MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136 - AUX */\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137 - POWER */\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | DIS  | M4)) /*GPIO_138 - EXT-ANT */\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139 - RS232 EXT */\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156 - GPS ON(0)/OFF(1)*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTU | EN  | M4)) /*GPIO_157 - PENIRQ */\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | EN  | M4)) /*GPIO_158 - DOUT */\
+MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTU | DIS | M4)) /*GPIO_159 - DIN - pulled up */\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTU | EN  | M4)) /*GPIO_161 - CS */\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | EN  | M4)) /*GPIO_162 - SCL */
+
+#endif
diff --git a/u-boot/board/gth2/Makefile b/u-boot/board/gth2/Makefile
new file mode 100644
index 0000000..77965fb
--- /dev/null
+++ b/u-boot/board/gth2/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o ee_access.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gth2/config.mk b/u-boot/board/gth2/config.mk
new file mode 100644
index 0000000..c905049
--- /dev/null
+++ b/u-boot/board/gth2/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+#  AMD Alchemy AU1000, MIPS32 core
+#
+
+ifeq ($(TBASE),0)
+CONFIG_SYS_TEXT_BASE = 0
+else
+ifeq ($(TBASE),1)
+CONFIG_SYS_TEXT_BASE = 0xbfc10070
+else
+ifeq ($(TBASE),2)
+CONFIG_SYS_TEXT_BASE = 0xbfc30070
+else
+## Only to make ordinary make work
+CONFIG_SYS_TEXT_BASE = 0x90000000
+endif
+endif
+endif
diff --git a/u-boot/board/gth2/ee_access.c b/u-boot/board/gth2/ee_access.c
new file mode 100644
index 0000000..d4798c4
--- /dev/null
+++ b/u-boot/board/gth2/ee_access.c
@@ -0,0 +1,347 @@
+/* Module for handling DALLAS DS2438, smart battery monitor
+   Chip can store up to 40 bytes of user data in EEPROM,
+   perform temp, voltage and current measurements.
+   Chip also contains a unique serial number.
+
+   Always read/write LSb first
+
+   For documentaion, see data sheet for DS2438, 2438.pdf
+
+   By Thomas.Lange@corelatus.com 001025
+
+   Copyright (C) 2000-2005 Corelatus AB */
+
+/* This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/io.h>
+#include "ee_dev.h"
+#include "ee_access.h"
+
+/* static int Debug = 1; */
+#undef E_DEBUG
+#define E_DEBUG(fmt,args...) /* */
+/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
+
+/* We dont have kernel functions */
+#define printk printf
+#define KERN_DEBUG
+#define KERN_ERR
+#define EIO 1
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
+
+static u8 crc_lookup[256] = {
+	0,	94,	188,	226,	97,	63,	221,	131,
+	194,	156,	126,	32,	163,	253,	31,	65,
+	157,	195,	33,	127,	252,	162,	64,	30,
+	95,	1,	227,	189,	62,	96,	130,	220,
+	35,	125,	159,	193,	66,	28,	254,	160,
+	225,	191,	93,	3,	128,	222,	60,	98,
+	190,	224,	2,	92,	223,	129,	99,	61,
+	124,	34,	192,	158,	29,	67,	161,	255,
+	70,	24,	250,	164,	39,	121,	155,	197,
+	132,	218,	56,	102,	229,	187,	89,	7,
+	219,	133,	103,	57,	186,	228,	6,	88,
+	25,	71,	165,	251,	120,	38,	196,	154,
+	101,	59,	217,	135,	4,	90,	184,	230,
+	167,	249,	27,	69,	198,	152,	122,	36,
+	248,	166,	68,	26,	153,	199,	37,	123,
+	58,	100,	134,	216,	91,	5,	231,	185,
+	140,	210,	48,	110,	237,	179,	81,	15,
+	78,	16,	242,	172,	47,	113,	147,	205,
+	17,	79,	173,	243,	112,	46,	204,	146,
+	211,	141,	111,	49,	178,	236,	14,	80,
+	175,	241,	19,	77,	206,	144,	114,	44,
+	109,	51,	209,	143,	12,	82,	176,	238,
+	50,	108,	142,	208,	83,	13,	239,	177,
+	240,	174,	76,	18,	145,	207,	45,	115,
+	202,	148,	118,	40,	171,	245,	23,	73,
+	8,	86,	180,	234,	105,	55,	213,	139,
+	87,	9,	235,	181,	54,	104,	138,	212,
+	149,	203,	41,	119,	244,	170,	72,	22,
+	233,	183,	85,	11,	136,	214,	52,	106,
+	43,	117,	151,	201,	74,	20,	246,	168,
+	116,	42,	200,	150,	21,	75,	169,	247,
+	182,	232,	10,	84,	215,	137,	107,	53
+};
+
+static void
+write_gpio_data(int value ){
+	if(value){
+		/* Tristate */
+		gpio_tristate(GPIO_EEDQ);
+	}
+	else{
+		/* Drive 0 */
+		gpio_clear(GPIO_EEDQ);
+	}
+}
+
+static u8 make_new_crc( u8 Old_crc, u8 New_value ){
+	/* Compute a new checksum with new byte, using previous checksum as input
+	   See DS app note 17, understanding and using cyclic redundancy checks...
+	   Also see DS2438, page 11 */
+	return( crc_lookup[Old_crc ^ New_value ]);
+}
+
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
+	/* Check if the checksum for this buffer is correct */
+	u8 Curr_crc=0;
+	int i;
+	u8 *Curr_byte = Buffer;
+
+	for(i=0;i<Len;i++){
+		Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
+		Curr_byte++;
+	}
+	E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
+
+	if(Curr_crc == Crc){
+		/* Good */
+		return(TRUE);
+	}
+	printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
+	return(FALSE);
+}
+
+static void
+set_idle(void){
+	/* Send idle and keep start time
+	   Continous 1 is idle */
+	WRITE_PORT(1);
+}
+
+
+static int
+do_cpu_reset(void){
+	/* Release reset and verify that chip responds with presence pulse */
+	int Retries=0;
+	while(Retries<15){
+		udelay(RESET_LOW_TIME);
+
+		/* Send reset */
+		WRITE_PORT(0);
+		udelay(RESET_LOW_TIME);
+
+		/* Release reset */
+		WRITE_PORT(1);
+
+		/* Wait for EEPROM to drive output */
+		udelay(PRESENCE_TIMEOUT);
+		if(!READ_PORT){
+			/* Ok, EEPROM is driving a 0 */
+			E_DEBUG("Presence detected\n");
+			if(Retries){
+				E_DEBUG("Retries %d\n",Retries);
+			}
+			/* Make sure chip releases pin */
+			udelay(PRESENCE_LOW_TIME);
+			return 0;
+		}
+		Retries++;
+	}
+
+	printk(KERN_ERR"eeprom did not respond when releasing reset\n");
+
+	/* Make sure chip releases pin */
+	udelay(PRESENCE_LOW_TIME);
+
+	/* Set to idle again */
+	set_idle();
+
+	return(-EIO);
+}
+
+static u8
+read_cpu_byte(void){
+	/* Read a single byte from EEPROM
+	   Read LSb first */
+	int i;
+	int Value;
+	u8 Result=0;
+	u32 Flags;
+
+	E_DEBUG("Reading byte\n");
+
+	for(i=0;i<8;i++){
+		/* Small delay between pulses */
+		udelay(1);
+
+#ifdef __KERNEL__
+		/* Disable irq */
+		save_flags(Flags);
+		cli();
+#endif
+
+		/* Pull down pin short time to start read
+		   See page 26 in data sheet */
+
+		WRITE_PORT(0);
+		udelay(READ_LOW);
+		WRITE_PORT(1);
+
+		/* Wait for chip to drive pin */
+		udelay(READ_TIMEOUT);
+
+		Value = READ_PORT;
+		if(Value)
+			Value=1;
+
+#ifdef __KERNEL__
+		/* Enable irq */
+		restore_flags(Flags);
+#endif
+
+		/* Wait for chip to release pin */
+		udelay(TOTAL_READ_LOW-READ_TIMEOUT);
+
+		/* LSb first */
+		Result|=Value<<i;
+		/* E_DEBUG("Read %d\n",Value); */
+
+	}
+
+	E_DEBUG("Read byte 0x%x\n",Result);
+
+	return(Result);
+}
+
+static void
+write_cpu_byte(u8 Byte){
+	/* Write a single byte to EEPROM
+	   Write LSb first */
+	int i;
+	int Value;
+	u32 Flags;
+
+	E_DEBUG("Writing byte 0x%x\n",Byte);
+
+	for(i=0;i<8;i++){
+		/* Small delay between pulses */
+		udelay(1);
+		Value = Byte&1;
+
+#ifdef __KERNEL__
+		/* Disable irq */
+		save_flags(Flags);
+		cli();
+#endif
+
+		/* Pull down pin short time for a 1, long time for a 0
+		   See page 26 in data sheet */
+
+		WRITE_PORT(0);
+		if(Value){
+			/* Write a 1 */
+			udelay(WRITE_1_LOW);
+		}
+		else{
+			/* Write a 0 */
+			udelay(WRITE_0_LOW);
+		}
+
+		WRITE_PORT(1);
+
+#ifdef __KERNEL__
+		/* Enable irq */
+		restore_flags(Flags);
+#endif
+
+		if(Value)
+			/* Wait for chip to read the 1 */
+			udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
+
+		/* E_DEBUG("Wrote %d\n",Value); */
+		Byte>>=1;
+	}
+}
+
+int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
+	/* Execute this command string, including
+	   giving reset and setting to idle after command
+	   if Rx_len is set, we read out data from EEPROM */
+	int i;
+
+	E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
+
+	if(do_cpu_reset()){
+		/* Failed! */
+		return(-EIO);
+	}
+
+	if(Send_skip)
+		/* Always send SKIP_ROM first to tell chip we are sending a command,
+		   except when we read out rom data for chip */
+		write_cpu_byte(SKIP_ROM);
+
+	/* Always have Tx data */
+	for(i=0;i<Tx_len;i++){
+		write_cpu_byte(Tx[i]);
+	}
+
+	if(Rx_len){
+		for(i=0;i<Rx_len;i++){
+			Rx[i]=read_cpu_byte();
+		}
+	}
+
+	set_idle();
+
+	E_DEBUG("Command done\n");
+
+	return(0);
+}
+
+int ee_init_cpu_data(void){
+	int i;
+	u8 Tx[10];
+
+	/* Leave it floting since altera is driving the same pin */
+	set_idle();
+
+	/* Copy all User EEPROM data to scratchpad */
+	for(i=0;i<USER_PAGES;i++){
+		Tx[0]=RECALL_MEMORY;
+		Tx[1]=EE_USER_PAGE_0+i;
+		if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+	}
+
+	/* Make sure chip doesnt store measurements in NVRAM */
+	Tx[0]=WRITE_SCRATCHPAD;
+	Tx[1]=0; /* Page */
+	Tx[2]=9;
+	if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
+
+	Tx[0]=COPY_SCRATCHPAD;
+	if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+
+	for(i=0;i<10;i++){
+		udelay(1000);
+	}
+
+	return(0);
+}
diff --git a/u-boot/board/gth2/ee_access.h b/u-boot/board/gth2/ee_access.h
new file mode 100644
index 0000000..926199d
--- /dev/null
+++ b/u-boot/board/gth2/ee_access.h
@@ -0,0 +1,30 @@
+/* By Thomas.Lange@Corelatus.com 001025 */
+
+/* Definitions for EEPROM/VOLT METER  DS2438 */
+/* Copyright (C) 2000-2005 Corelatus AB */
+
+#ifndef INCeeaccessh
+#define INCeeaccessh
+
+#include <asm/types.h>
+#include "ee_dev.h"
+
+int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
+int ee_init_cpu_data(void);
+
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
+
+/* Defs for altera reg */
+#define EE_WRITE_SHIFT 8 /* bits to shift left */
+#define EE_READ_SHIFT 16 /* bits to shift left */
+#define EE_DONE  0x80000000
+#define EE_BUSY  0x40000000
+#define EE_ERROR 0x20000000
+
+/* Commands */
+#define EE_CMD_NOP      0
+#define EE_CMD_INIT_RES 1
+#define EE_CMD_WR_BYTE  2
+#define EE_CMD_RD_BYTE  3
+
+#endif /* INCeeaccessh */
diff --git a/u-boot/board/gth2/ee_dev.h b/u-boot/board/gth2/ee_dev.h
new file mode 100644
index 0000000..89ef2f8
--- /dev/null
+++ b/u-boot/board/gth2/ee_dev.h
@@ -0,0 +1,96 @@
+/* By Thomas.Lange@Corelatus.com 001025 */
+/* Definitions for EEPROM/VOLT METER  DS2438 */
+/* Copyright (C) 2000-2005 Corelatus AB */
+
+/* This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef INCeedevh
+#define INCeedevh
+
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
+
+/* MIPS */
+#define WRITE_PORT(Value) write_gpio_data(Value)
+
+#define READ_PORT (gpio_read()&GPIO_EEDQ)
+
+/* 64 bytes chip */
+#define EE_CHIP_SIZE 64
+
+/* Board with new current resistor */
+#define EE_GTH_0304 1
+
+/* new dsp and 64 MB SDRAM */
+#define EE_DSP_64 0x10
+
+/* microsecs */
+/* Pull line down at least this long for reset pulse */
+#define RESET_LOW_TIME    490
+
+/* Read presence pulse after we release reset pulse */
+#define PRESENCE_TIMEOUT  100
+#define PRESENCE_LOW_TIME 200
+
+#define WRITE_0_LOW 60
+#define WRITE_1_LOW 1
+#define TOTAL_WRITE_LOW 60
+
+#define READ_LOW        1
+#define READ_TIMEOUT   10
+#define TOTAL_READ_LOW 70
+
+/* Rom function commands */
+#define READ_ROM   0x33
+#define MATCH_ROM  0x55
+#define SKIP_ROM   0xCC
+#define SEARCH_ROM 0xF0
+
+
+/* Memory_command_function */
+#define WRITE_SCRATCHPAD 0x4E
+#define READ_SCRATCHPAD  0xBE
+#define COPY_SCRATCHPAD  0x48
+#define RECALL_MEMORY    0xB8
+#define CONVERT_TEMP     0x44
+#define CONVERT_VOLTAGE  0xB4
+
+/* Chip is divided in 8 pages, 8 bytes each */
+
+#define EE_PAGE_SIZE 8
+
+/* All chip data we want are in page 0 */
+
+/* Bytes in page 0 */
+#define EE_P0_STATUS   0
+#define EE_P0_TEMP_LSB 1
+#define EE_P0_TEMP_MSB 2
+#define EE_P0_VOLT_LSB 3
+#define EE_P0_VOLT_MSB 4
+#define EE_P0_CURRENT_LSB 5
+#define EE_P0_CURRENT_MSB 6
+
+
+/* 40 byte user data is located at page 3-7 */
+#define EE_USER_PAGE_0 3
+#define USER_PAGES 5
+
+/* Layout of gth user pages usage */
+/* Bytes 0-16   ethernet addr in ascii ( len 17 ) */
+
+#define EE_ETHERNET_OFFSET       0
+
+#endif /* INCeedevh */
diff --git a/u-boot/board/gth2/flash.c b/u-boot/board/gth2/flash.c
new file mode 100644
index 0000000..1b3c43c
--- /dev/null
+++ b/u-boot/board/gth2/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	printf ("Skipping flash_init\n");
+	return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	printf ("write_buff not implemented\n");
+	return (-1);
+}
diff --git a/u-boot/board/gth2/gth2.c b/u-boot/board/gth2/gth2.c
new file mode 100644
index 0000000..8c3b55a
--- /dev/null
+++ b/u-boot/board/gth2/gth2.c
@@ -0,0 +1,437 @@
+/*
+ * (C) Copyright 2005
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/addrspace.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+#include <watchdog.h>
+
+#include "ee_access.h"
+
+static int wdi_status = 0;
+
+#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
+
+
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
+
+void inline log_serial_char(char c){
+	char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
+	int serial_log_offset;
+	u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
+
+	serial_log_offset = *serial_log_offsetp;
+
+	*(serial_log_buffer + serial_log_offset) = c;
+
+	serial_log_offset++;
+
+	if(serial_log_offset >= 4096){
+		serial_log_offset = 4;
+	}
+	*serial_log_offsetp = serial_log_offset;
+}
+
+void init_log_serial(void){
+	char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
+	u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
+
+	/* Copy buffer from last run */
+	memcpy(serial_log_buffer + 4096,
+	       serial_log_buffer,
+	       4096);
+
+	memset(serial_log_buffer, 0, 4096);
+
+	*serial_log_offsetp = 4;
+}
+
+
+void hw_watchdog_reset(void){
+	volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
+	volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
+	if(wdi_status){
+		*sys_outputset = GPIO_CPU_LED|GPIO_WDI;
+		wdi_status = 0;
+	}
+	else{
+		*sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
+		wdi_status = 1;
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+
+	WATCHDOG_RESET();
+
+	return (SDRAM_SIZE);
+}
+
+/* In arch/mips/cpu/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+void set_ledcard(u32 value){
+	/* Clock 24 bits to led card */
+	int i;
+	volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
+	volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
+
+	/* Start with known values */
+	*sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
+
+	for(i=0;i<24;i++){
+		if(value&0x00800000){
+			*sys_outputset = GPIO_LEDD;
+		}
+		else{
+			*sys_outputclr = GPIO_LEDD;
+		}
+		udelay(1);
+		*sys_outputset = GPIO_LEDCLK;
+		udelay(1);
+		*sys_outputclr = GPIO_LEDCLK;
+		udelay(1);
+
+		value<<=1;
+	}
+	/* Data is enable output */
+	*sys_outputset = GPIO_LEDD;
+}
+
+int checkboard (void)
+{
+	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+	volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
+	volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
+	u32 proc_id;
+
+	WATCHDOG_RESET();
+
+	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+	proc_id = read_c0_prid();
+
+	switch (proc_id >> 24) {
+	case 0:
+		puts ("Board: GTH2\n");
+		printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	default:
+		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+	}
+
+	set_io_port_base(0);
+
+#ifdef CONFIG_IDE_PCMCIA
+	/* PCMCIA is on a 36 bit physical address.
+	   We need to map it into a 32 bit addresses */
+	write_one_tlb(20,                 /* index */
+		      0x01ffe000,         /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
+		      0x3C000017,         /* Lo0 */
+		      0x3C200017);        /* Lo1 */
+
+	write_one_tlb(21,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
+		      0x3D000017,           /* Lo0 */
+		      0x3D200017);          /* Lo1 */
+
+	write_one_tlb(22,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
+		      0x3E000017,           /* Lo0 */
+		      0x3E200017);          /* Lo1 */
+
+#endif	/* CONFIG_IDE_PCMCIA */
+
+	/* Wait for GPIO ports to become stable */
+	udelay(5000); /* FIXME */
+
+	/* Release reset of ethernet PHY chips */
+	/* Always do this, because linux does not know about it */
+	*sys_outputset = GPIO_ERESET;
+
+	/* Kill FPGA:s */
+	*sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
+	udelay(2);
+	*sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
+
+	/* Turn front led yellow */
+	set_ledcard(0x00100000);
+
+	return 0;
+}
+
+#define POWER_OFFSET    0xF0000
+#define SW_WATCHDOG_REASON 13
+
+#define BOOTDATA_OFFSET 0xF8000
+#define MAX_ATTEMPTS 5
+
+#define FAILSAFE_BOOT 1
+#define SYSTEM_BOOT   2
+#define SYSTEM2_BOOT  3
+
+#define WRITE_FLASH16(a, d)      \
+do                              \
+{                               \
+  *((volatile u16 *) (a)) = (d);\
+ } while(0)
+
+static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
+{
+	u16 data;
+	volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
+
+	switch(System){
+	case FAILSAFE_BOOT:
+		printf ("Setting failsafe boot in flash\n");
+		break;
+	case SYSTEM_BOOT:
+		printf ("Setting system boot in flash\n");
+		break;
+	case SYSTEM2_BOOT:
+		printf ("Setting system2 boot in flash\n");
+		break;
+	default:
+		printf ("Invalid system data %u, setting failsafe\n", System);
+		System = FAILSAFE_BOOT;
+	}
+
+	if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
+		printf ("Invalid boot count %u, setting 1\n", Count);
+		Count = 1;
+	}
+
+	printf ("Boot attempt %d\n", Count);
+
+	data = (System << 8) | Count;
+	/* AMD 16 bit */
+	WRITE_FLASH16 (&flash[0x555], 0xAAAA);
+	WRITE_FLASH16 (&flash[0x2AA], 0x5555);
+	WRITE_FLASH16 (&flash[0x555], 0xA0A0);
+
+	WRITE_FLASH16 (addr, data);
+}
+
+static int random_system(void){
+	/* EEPROM read failed. Just try to choose one
+	   system release and hope it works */
+
+	/* FIXME */
+	return(SYSTEM_BOOT);
+}
+
+static int switch_system(int old_system){
+	u8 Rx[10];
+	u8 Tx[5];
+	int valid_release;
+
+	if(old_system==FAILSAFE_BOOT){
+		/* Find out which system release to use */
+
+		/* Copy from nvram to scratchpad */
+		Tx[0] = RECALL_MEMORY;
+		Tx[1] = 7; /* Page */
+		if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
+			printf ("EE user page 7 recall failed\n");
+			return (random_system());
+		}
+
+		Tx[0] = READ_SCRATCHPAD;
+		if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
+			printf ("EE user page 7 read failed\n");
+			return (random_system());
+		}
+		/* Crc in 9:th byte */
+		if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
+			printf ("EE read failed, page 7. CRC error\n");
+			return (random_system());
+		}
+
+		valid_release = Rx[7];
+		if((valid_release==0xFF)|
+		   ((valid_release&1) == 0)){
+			return(SYSTEM_BOOT);
+		}
+		else{
+			return(SYSTEM2_BOOT);
+		}
+	}
+	else{
+		return(FAILSAFE_BOOT);
+	}
+}
+
+static void check_boot_tries (void)
+{
+	/* Count the number of boot attemps
+	   switch system if too many */
+
+	int i;
+	volatile u16 *addr;
+	volatile u16 data;
+	u8 system = FAILSAFE_BOOT;
+	u8 count;
+
+	addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
+
+	if (*addr == 0xFFFF) {
+		printf ("*** No bootdata exists. ***\n");
+		write_bootdata (addr, FAILSAFE_BOOT, 1);
+	} else {
+		/* Search for latest written bootdata */
+		i = 0;
+		while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
+			addr++;
+			i++;
+		}
+		if (i >= 8000) {
+			/* Whoa, dont write any more */
+			printf ("*** No bootdata found. Not updating flash***\n");
+		} else {
+			/* See how many times we have tried to boot real system */
+			data = *addr;
+			system = data >> 8;
+			count = data & 0xFF;
+			if ((system != SYSTEM_BOOT) &
+			    (system != SYSTEM2_BOOT) &
+			    (system != FAILSAFE_BOOT)) {
+				printf ("*** Wrong system %d\n", system);
+				system = FAILSAFE_BOOT;
+				count = 1;
+			} else {
+				switch (count) {
+				case 0:
+				case 1:
+				case 2:
+				case 3:
+				case 4:
+					/* Try same system again if needed */
+					count++;
+					break;
+
+				case 5:
+					/* Switch system and reset tries */
+					count = 1;
+					system = switch_system(system);
+					printf ("***Too many boot attempts, switching system***\n");
+					break;
+				default:
+					/* Switch system, start over and hope it works */
+					printf ("***Unexpected data on addr 0x%x, %u***\n",
+						(u32) addr, data);
+					count = 1;
+					system = switch_system(system);
+				}
+			}
+			write_bootdata (addr + 1, system, count);
+		}
+	}
+	switch(system){
+	case FAILSAFE_BOOT:
+		printf ("Booting failsafe system\n");
+		setenv ("bootargs", "panic=1 root=/dev/hda7");
+		setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
+		break;
+
+	case SYSTEM_BOOT:
+		printf ("Using normal system\n");
+		setenv ("bootargs", "panic=1 root=/dev/hda4");
+		setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
+		break;
+
+	case SYSTEM2_BOOT:
+		printf ("Using normal system2\n");
+		setenv ("bootargs", "panic=1 root=/dev/hda9");
+		setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
+		break;
+	default:
+		printf ("Invalid system %d\n", system);
+		printf ("Hanging\n");
+		while(1);
+	}
+}
+
+int misc_init_r(void){
+	u8 Rx[80];
+	u8 Tx[5];
+	int page;
+	int read = 0;
+
+	WATCHDOG_RESET();
+
+	if (ee_init_cpu_data ()) {
+		printf ("EEPROM init failed\n");
+		return (0);
+	}
+
+	/* Check which release to boot */
+	check_boot_tries ();
+
+	/* Read the pages where ethernet address is stored */
+
+	for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
+		/* Copy from nvram to scratchpad */
+		Tx[0] = RECALL_MEMORY;
+		Tx[1] = page;
+		if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
+			printf ("EE user page %d recall failed\n", page);
+			return (0);
+		}
+
+		Tx[0] = READ_SCRATCHPAD;
+		if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
+			printf ("EE user page %d read failed\n", page);
+			return (0);
+		}
+		/* Crc in 9:th byte */
+		if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
+			printf ("EE read failed, page %d. CRC error\n", page);
+			return (0);
+		}
+		read += 8;
+	}
+
+	/* Add eos after eth addr */
+	Rx[17] = 0;
+
+	printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
+
+	if ((Rx[2] != ':') |
+	    (Rx[5] != ':') |
+	    (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
+		printf ("*** ethernet addr invalid, using default ***\n");
+	} else {
+		setenv ("ethaddr", (char *)Rx);
+	}
+	return (0);
+}
diff --git a/u-boot/board/gth2/lowlevel_init.S b/u-boot/board/gth2/lowlevel_init.S
new file mode 100644
index 0000000..bc31c00
--- /dev/null
+++ b/u-boot/board/gth2/lowlevel_init.S
@@ -0,0 +1,457 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define CP0_Config0		$16
+#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)
+#define GPIO_RJ1LY     (1<<22)
+#define GPIO_CFRESET   (1<<10)
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+	/* No workaround if running from ram */
+	lui	t0, 0xffc0
+	lui	t3, 0xbfc0
+	and	t1, ra, t0
+	bne	t1, t3, noCacheJump
+	nop
+
+	/*** From AMD YAMON ***/
+	/*
+	 * Step 8) Initialize the caches
+	 */
+	li		t0, (16*1024)
+	li		t1, 32
+	li		t2, 0x80000000
+	addu	t3, t0, t2
+cacheloop:
+	cache	0, 0(t2)
+	cache	1, 0(t2)
+	addu	t2, t1
+	bne		t2, t3, cacheloop
+	nop
+
+	/* Save return address */
+	move		t3, ra
+
+	/* Run from cacheable space now */
+	bal		cachehere
+	nop
+cachehere:
+	li		t1, ~0x20000000 /* convert to KSEG0 */
+	and		t0, ra, t1
+	addi	t0, 5*4			/* 5 insns beyond cachehere */
+	jr		t0
+	nop
+
+	/* Restore return address */
+	move		ra, t3
+
+	/*
+	 * Step 9) Initialize the TLB
+	 */
+	li		t0, 0			# index value
+	li		t1, 0x00000000		# entryhi value
+	li		t2, 32			# 32 entries
+
+tlbloop:
+	/* Probe TLB for matching EntryHi */
+	mtc0	t1, CP0_ENTRYHI
+	tlbp
+	nop
+
+	/* Examine Index[P], 1=no matching entry */
+	mfc0	t3, CP0_INDEX
+	li	t4, 0x80000000
+	and	t3, t4, t3
+	addiu	t1, t1, 1		# increment t1 (asid)
+	beq	zero, t3, tlbloop
+	nop
+
+	/* Initialize the TLB entry */
+	mtc0	t0, CP0_INDEX
+	mtc0	zero, CP0_ENTRYLO0
+	mtc0	zero, CP0_ENTRYLO1
+	mtc0	zero, CP0_PAGEMASK
+	tlbwi
+
+	/* Do it again */
+	addiu	t0, t0, 1
+	bne	t0, t2, tlbloop
+	nop
+
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12.5 MHz crystal */
+	li	t0, SYS_CPUPLL
+	li	t1, 0x28  /* CPU clock, 500 MHz */
+	sw	t1, 0(t0)
+	sync
+	nop
+	nop
+
+	/* wait 1mS for clocks to settle */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+	/* Setup AUX PLL */
+	li	t0, SYS_AUXPLL
+	li	t1, 0
+	sw	t1, 0(t0) /* aux pll */
+	sync
+
+	/*  Static memory controller */
+	/* RCE0 - can not change while fetching, do so from icache */
+	move		t2, ra /* Store return address */
+	bal		getAddr
+	nop
+
+getAddr:
+	move		t1, ra
+	move		ra, t2 /* Move return addess back */
+
+	cache	0x14,0(t1)
+	cache	0x14,32(t1)
+	/*** /From YAMON ***/
+
+noCacheJump:
+
+	/*  Static memory controller */
+
+	/* RCE0 AMD 29LV800 Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000243
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7 /* FIXME */
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11E03F80
+	sw	t1, 0(t0)
+
+	/* RCE1 PCMCIA 250ns */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000002
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x280E3E07
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x10000000
+	sw	t1, 0(t0)
+
+	/* RCE2 CP Altera */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000280 /* BE, EW */
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x0303000c
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f80 /* 1 MB */
+	sw	t1, 0(t0)
+
+	/* RCE3 DP Altera */
+	li	t0, MEM_STCFG3
+	li	t1, 0x00000280 /* BE, EW */
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0x0303000c
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0x10e03f80 /* 1 MB */
+	sw	t1, 0(t0)
+
+	sync
+
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+
+/* SDCS 0 SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x592CD1
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+/* 64 MB SDRAM at addr 0 */
+	li	t0, MEM_SDADDR0
+	li	t1, 0x001003F0
+	sw	t1, 0(t0)
+
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x880007A1 /* Disable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x8A0007A1 /* Enable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+	/* Setup GPIO pins */
+
+	li	t0, SYS_PINFUNC
+	li	t1, 0x00007025 /* 0x8080 */
+	sw	t1, 0(t0)
+
+	li	t0, SYS_TRIOUTCLR
+	li	t1, 0xFFFFFFFF /* 0x1FFF */
+	sw	t1, 0(t0)
+
+	/* Turn yellow front led on */
+	/* Release reset on CF */
+	li	t0, SYS_OUTPUTCLR
+	li	t1, GPIO_RJ1LG
+	sw	t1, 0(t0)
+	li	t0, SYS_OUTPUTSET
+	li	t1, GPIO_RJ1LY|GPIO_CFRESET
+	sw	t1, 0(t0)
+	sync
+	j clearmem
+	nop
+
+#if 0
+	.globl	memtest
+#endif
+memtest:
+	/* Fill memory with address */
+	li	t0, 0x80000000
+	li	t1, 0xFFF000 /* 64 MB */
+mt0:	sw	t0, 0(t0)
+	add	t1, -1
+	add	t0, 4
+	bne	t1, zero, mt0
+	nop
+	nop
+	/* Verify addr */
+	li	t0, 0x80000000
+	li	t1, 0xFFF000 /* 64 MB */
+mt1:	lw	t2, 0(t0)
+	bne	t0, t2, memhang
+	add	t1, -1
+	add	t0, 4
+	bne	t1, zero, mt1
+	nop
+	nop
+#if 0
+	.globl	clearmem
+#endif
+clearmem:
+		/* Clear memory */
+	li	t0, 0x80000000
+	li	t1, 0xFFF000 /* 64 MB */
+mtc:	sw	zero, 0(t0)
+	add	t1, -1
+	add	t0, 4
+	bne	t1, zero, mtc
+	nop
+	nop
+memtestend:
+	jr	ra
+	nop
+
+memhang:
+	b	memhang
+	nop
diff --git a/u-boot/board/gth2/u-boot.lds b/u-boot/board/gth2/u-boot.lds
new file mode 100644
index 0000000..aeb0fcc
--- /dev/null
+++ b/u-boot/board/gth2/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/gw8260/Makefile b/u-boot/board/gw8260/Makefile
new file mode 100644
index 0000000..82a8068
--- /dev/null
+++ b/u-boot/board/gw8260/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= gw8260.o flash.o
+SOBJS   :=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/gw8260/flash.c b/u-boot/board/gw8260/flash.c
new file mode 100644
index 0000000..6035f69
--- /dev/null
+++ b/u-boot/board/gw8260/flash.c
@@ -0,0 +1,523 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Oliver Brown <oliverb@alumni.utexas.net>
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*********************************************************************/
+/* DESCRIPTION:
+ *   This file contains the flash routines for the GW8260 board.
+ *
+ *
+ *
+ * MODULE DEPENDENCY:
+ *   None
+ *
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *
+ *   Only supports the following flash devices:
+ *     AMD 29F080B
+ *     AMD 29F016D
+ *
+ * Copyright (c) 2001, Advent Networks, Inc.
+ *
+ */
+/*********************************************************************/
+
+#include <common.h>
+#include <mpc8260.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*********************************************************************/
+/*		      functions					     */
+/*********************************************************************/
+
+/*********************************************************************/
+/* NAME: flash_init() -	 initializes flash banks		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function initializes the flash bank(s).		     */
+/*								     */
+/* RETURNS:							     */
+/*   The size in bytes of the flash				     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* for now, only support the 4 MB Flash SIMM */
+    size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+
+    /*
+     * protect monitor and environment sectors
+     */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);  /*size*/
+}
+
+/*********************************************************************/
+/* NAME: flash_print_info() - prints flash imformation		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function prints the flash information.		     */
+/*								     */
+/* INPUTS:							     */
+/*   flash_info_t *info - flash information structure		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays flash information to console			     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch ((info->flash_id >> 16) & 0xff) {
+    case 0x1:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F080B:
+	printf ("AM29F080B (8 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	    printf ("\n	  ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "	   "
+	    );
+    }
+    printf ("\n");
+    return;
+}
+
+/*********************************************************************/
+/*   The following code cannot be run from FLASH!		     */
+/*********************************************************************/
+
+/*********************************************************************/
+/* NAME: flash_get_size() - detects the flash size		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   1) Reads vendor ID and devices ID from the flash devices.	     */
+/*   2) Initializes flash info struct.				     */
+/*   3) Return the flash size					     */
+/*								     */
+/* INPUTS:							     */
+/*   vu_long *addr	- pointer to start of flash		     */
+/*   flash_info_t *info - flash information structure		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   Size of the flash in bytes, or 0 if device id is unknown.	     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   Only supports the following devices:			     */
+/*     AM29F080D						     */
+/*     AM29F016D						     */
+/*								     */
+/*********************************************************************/
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    vu_long vendor, devid;
+    ulong base = (ulong)addr;
+
+    /*printf("addr   = %08lx\n", (unsigned long)addr); */
+
+    /* Reset and Write auto select command: read Manufacturer ID */
+    addr[0x0000] = 0xf0f0f0f0;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x90909090;
+    udelay (1000);
+
+    vendor = addr[0];
+    /*printf("vendor = %08lx\n", vendor); */
+    if (vendor != 0x01010101) {
+	info->size = 0;
+	goto out;
+    }
+
+    devid = addr[1];
+    /*printf("devid  = %08lx\n", devid); */
+
+    if ((devid & 0xff) == AMD_ID_F080B) {
+	info->flash_id	   = (vendor & 0xff) << 16 | AMD_ID_F080B;
+	/* we have 16 sectors with 64KB each x 4 */
+	info->sector_count = 16;
+	info->size	   = 4 * info->sector_count * 64*1024;
+    } else if ((devid & 0xff) == AMD_ID_F016D){
+	info->flash_id	   = (vendor & 0xff) << 16 | AMD_ID_F016D;
+	/* we have 32 sectors with 64KB each x 4 */
+	info->sector_count = 32;
+	info->size	   = 4 * info->sector_count * 64*1024;
+    } else {
+	info->size = 0;
+	goto out;
+    }
+    /*printf("sector count = %08x\n", info->sector_count); */
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr = (volatile unsigned long *)(info->start[i]);
+	info->protect[i] = addr[2] & 1;
+    }
+
+    /* reset command */
+    addr = (vu_long *)info->start[0];
+
+  out:
+    addr[0] = 0xf0f0f0f0;
+
+    /*printf("size = %08x\n", info->size); */
+    return info->size;
+}
+
+/*********************************************************************/
+/* NAME: flash_erase() - erases flash by sector			     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function erases flash sectors starting for s_first to	     */
+/*   s_last.							     */
+/*								     */
+/* INPUTS:							     */
+/*   flash_info_t *info - flash information structure		     */
+/*   int s_first - first sector to erase			     */
+/*   int s_last	 - last sector to erase				     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   Returns 0 for success, 1 for failure.			     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*********************************************************************/
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x80808080;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    udelay (100);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while ((addr[0] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+  DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;   /* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*********************************************************************/
+/* NAME: write_buff() - writes a buffer to flash		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function copies a buffer, *src, to flash.		     */
+/*								     */
+/* INPUTS:							     */
+/*  flash_info_t *info - flash information structure		     */
+/*  uchar *src - pointer to buffer to write to flash		     */
+/*  ulong addr - address to start write at			     */
+/*  ulong cnt - number of bytes to write to flash		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 - OK							     */
+/*   1 - write timeout						     */
+/*   2 - Flash not erased					     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*********************************************************************/
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i = 0, cp = wp; i < l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; (i < 4) && (cnt > 0); ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; (cnt == 0) && (i < 4); ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i = 0; i < 4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; (i < 4); ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*********************************************************************/
+/* NAME: write_word() - writes a word to flash			     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This writes a single word to flash.			     */
+/*								     */
+/* INPUTS:							     */
+/*  flash_info_t *info - flash information structure		     */
+/*  ulong dest - address to write				     */
+/*  ulong data - data to write					     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 - OK							     */
+/*   1 - write timeout						     */
+/*   2 - Flash not erased					     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*********************************************************************/
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0xA0A0A0A0;
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+/*********************************************************************/
+/*			   End of flash.c			     */
+/*********************************************************************/
diff --git a/u-boot/board/gw8260/gw8260.c b/u-boot/board/gw8260/gw8260.c
new file mode 100644
index 0000000..28f5ca9
--- /dev/null
+++ b/u-boot/board/gw8260/gw8260.c
@@ -0,0 +1,659 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Oliver Brown <oliverb@alumni.utexas.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*********************************************************************/
+/* DESCRIPTION:
+ *   This file contains the board routines for the GW8260 board.
+ *
+ * MODULE DEPENDENCY:
+ *   None
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *   None
+ *
+ * Copyright (c) 2001, Advent Networks, Inc.
+ */
+/*********************************************************************/
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   0,	 0,   1,   0,	0   }, /* TP14		*/
+	/* PA30 */ {   1,   1,	 1,   1,   0,	0   }, /* US_RTS	*/
+	/* PA29 */ {   1,   0,	 0,   1,   0,	1   }, /* LSSI_DATA	*/
+	/* PA28 */ {   1,   0,	 0,   1,   0,	1   }, /* LSSI_CLK	*/
+	/* PA27 */ {   1,   0,	 0,   1,   0,	0   }, /* TP12		*/
+	/* PA26 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_STATUS	*/
+	/* PA25 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_CLOCK	*/
+	/* PA24 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_CONFIG	*/
+	/* PA23 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_DONE	*/
+	/* PA22 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_DATA	*/
+	/* PA21 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD3	*/
+	/* PA20 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD2	*/
+	/* PA19 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD1	*/
+	/* PA18 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD0	*/
+	/* PA17 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD0	*/
+	/* PA16 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD1	*/
+	/* PA15 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD2	*/
+	/* PA14 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD3	*/
+	/* PA13 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE7	*/
+	/* PA12 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE6	*/
+	/* PA11 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE5	*/
+	/* PA10 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE4	*/
+	/* PA9	*/ {   1,   0,	 0,   1,   0,	0   }, /* SPARE3	*/
+	/* PA8	*/ {   1,   0,	 0,   1,   0,	0   }, /* SPARE2	*/
+	/* PA7	*/ {   1,   0,	 0,   0,   0,	0   }, /* LSSI_IN	*/
+	/* PA6	*/ {   1,   0,	 0,   1,   0,	0   }, /* SPARE0	*/
+	/* PA5	*/ {   1,   0,	 0,   1,   0,	0   }, /* DEMOD_RESET_	*/
+	/* PA4	*/ {   1,   0,	 0,   1,   0,	0   }, /* MOD_RESET_	*/
+	/* PA3	*/ {   1,   0,	 0,   1,   0,	0   }, /* IO_RESET	*/
+	/* PA2	*/ {   1,   0,	 0,   1,   0,	0   }, /* TX_ENABLE	*/
+	/* PA1	*/ {   1,   0,	 0,   0,   0,	0   }, /* RX_LOCK	*/
+	/* PA0	*/ {   1,   0,	 0,   1,   0,	1   }  /* MPC_RESET_	*/
+    },
+
+    /* Port B configuration */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FETH0_TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_COL   */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_CRS   */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD3  */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD2  */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD1  */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD0  */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD0  */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD1  */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD2  */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD3  */
+	/* PB17 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RX_DV */
+	/* PB16 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RX_ER */
+	/* PB15 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TX_ER */
+	/* PB14 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TX_EN */
+	/* PB13 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_COL   */
+	/* PB12 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_CRS   */
+	/* PB11 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD3  */
+	/* PB10 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD2  */
+	/* PB9	*/ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD1  */
+	/* PB8	*/ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD0  */
+	/* PB7	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD0  */
+	/* PB6	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD1  */
+	/* PB5	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD2  */
+	/* PB4	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD3  */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   0,	 0,   1,   0,	1   }, /* FAST_RESET_	*/
+	/* PC30 */ {   1,   0,	 0,   1,   0,	1   }, /* FAST_PAUSE_	*/
+	/* PC29 */ {   1,   0,	 0,   1,   0,	0   }, /* FAST_SLEW1	*/
+	/* PC28 */ {   1,   0,	 0,   1,   0,	0   }, /* FAST_SLEW0	*/
+	/* PC27 */ {   1,   0,	 0,   1,   0,	0   }, /* TP13		*/
+	/* PC26 */ {   1,   0,	 0,   0,   0,	0   }, /* RXDECDFLG	*/
+	/* PC25 */ {   1,   0,	 0,   0,   0,	0   }, /* RXACQFAIL	*/
+	/* PC24 */ {   1,   0,	 0,   0,   0,	0   }, /* RXACQFLG	*/
+	/* PC23 */ {   1,   0,	 0,   1,   0,	0   }, /* WD_TCL	*/
+	/* PC22 */ {   1,   0,	 0,   1,   0,	0   }, /* WD_EN		*/
+	/* PC21 */ {   1,   0,	 0,   1,   0,	0   }, /* US_TXCLK	*/
+	/* PC20 */ {   1,   0,	 0,   0,   0,	0   }, /* DS_RXCLK	*/
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RX_CLK	*/
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_TX_CLK	*/
+	/* PC17 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RX_CLK	*/
+	/* PC16 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_TX_CLK	*/
+	/* PC15 */ {   1,   0,	 0,   1,   0,	0   }, /* TX_SHUTDOWN_	*/
+	/* PC14 */ {   1,   0,	 0,   0,   0,	0   }, /* RS_232_DTR_	*/
+	/* PC13 */ {   1,   0,	 0,   0,   0,	0   }, /* TXERR		*/
+	/* PC12 */ {   1,   0,	 0,   1,   0,	1   }, /* FETH1_MDDIS	*/
+	/* PC11 */ {   1,   0,	 0,   1,   0,	1   }, /* FETH0_MDDIS	*/
+	/* PC10 */ {   1,   0,	 0,   1,   0,	0   }, /* MDC		*/
+	/* PC9	*/ {   1,   0,	 0,   1,   1,	1   }, /* MDIO		*/
+	/* PC8	*/ {   1,   0,	 0,   1,   1,	1   }, /* SER_NUM	*/
+	/* PC7	*/ {   1,   1,	 0,   0,   0,	0   }, /* US_CTS	*/
+	/* PC6	*/ {   1,   1,	 0,   0,   0,	0   }, /* DS_CD_	*/
+	/* PC5	*/ {   1,   0,	 0,   1,   0,	0   }, /* FETH1_PWRDWN	*/
+	/* PC4	*/ {   1,   0,	 0,   1,   0,	0   }, /* FETH0_PWRDWN	*/
+	/* PC3	*/ {   1,   0,	 0,   1,   0,	0   }, /* MPULED3	*/
+	/* PC2	*/ {   1,   0,	 0,   1,   0,	0   }, /* MPULED2	*/
+	/* PC1	*/ {   1,   0,	 0,   1,   0,	0   }, /* MPULED1	*/
+	/* PC0	*/ {   1,   0,	 0,   1,   0,	1   }, /* MPULED0	*/
+    },
+
+    /* Port D */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD30 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD29 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD28 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD27 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD26 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD25 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD24 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD23 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD22 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD21 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD20 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD19 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD18 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD17 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD16 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD15 */ {   1,   1,	 1,   0,   1,	1   }, /*  SDRAM_SDA	*/
+	/* PD14 */ {   1,   1,	 1,   0,   1,	1   }, /*  SDRAM_SCL	*/
+	/* PD13 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED7	*/
+	/* PD12 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED6	*/
+	/* PD11 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED5	*/
+	/* PD10 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED4	*/
+	/* PD9	*/ {   1,   1,	 0,   1,   0,	0   }, /*  RS232_TXD	*/
+	/* PD8	*/ {   1,   1,	 0,   0,   0,	0   }, /*  RD232_RXD	*/
+	/* PD7	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD6	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD5	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD4	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/*********************************************************************/
+/* NAME: checkboard() -	 Displays the board type and serial number   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays the board type and serial number			     */
+/*								     */
+/* RETURNS:							     */
+/*   Always returns 1						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int checkboard (void)
+{
+	char *str;
+
+	puts ("Board: Advent Networks gw8260\n");
+
+	str = getenv ("serial#");
+	if (str != NULL) {
+		printf ("SN:    %s\n", str);
+	}
+	return 0;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST)
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
+
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CONFIG_SYS_SDRAM_BASE;
+	const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
+
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE;
+	const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM ... ");
+	}
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	if (rundata == 1) {
+		if (mem_test_data () == 1) {
+			return 1;
+		}
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		if (mem_test_address () == 1) {
+			return 1;
+		}
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		if (mem_test_walk () == 1) {
+			return 1;
+		}
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed");
+	}
+	return 0;
+
+}
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/*********************************************************************/
+/* NAME: initdram() -  initializes SDRAM controller		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Initializes the MPC8260's SDRAM controller.		     */
+/*								     */
+/* INPUTS:							     */
+/*   CONFIG_SYS_IMMR	    -  MPC8260 Internal memory map		     */
+/*   CONFIG_SYS_SDRAM_BASE -  Physical start address of SDRAM		     */
+/*   CONFIG_SYS_PSDMR -       SDRAM mode register			     */
+/*   CONFIG_SYS_MPTPR -       Memory refresh timer prescaler register	     */
+/*   CONFIG_SYS_SDRAM0_SIZE - SDRAM size				     */
+/*								     */
+/* RETURNS:							     */
+/*   SDRAM size in bytes					     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+	ulong psdmr = CONFIG_SYS_PSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr = c;
+	}
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/* return total ram size */
+	return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
+}
+
+/*********************************************************************/
+/*			   End of gw8260.c			     */
+/*********************************************************************/
diff --git a/u-boot/board/hermes/Makefile b/u-boot/board/hermes/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/hermes/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/hermes/flash.c b/u-boot/board/hermes/flash.c
new file mode 100644
index 0000000..888231c
--- /dev/null
+++ b/u-boot/board/hermes/flash.c
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	uchar value;
+	vu_char *caddr = (vu_char *)addr;
+	ulong base = (ulong)addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0AAA] = 0xAA;
+	caddr[0x0555] = 0x55;
+	caddr[0x0AAA] = 0x90;
+
+	value = caddr[0];
+	switch (value) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = caddr[2];			/* device ID		*/
+
+	switch (value) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[4] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *)info->start[0];
+
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0AAA] = 0xAA;
+	addr[0x0555] = 0x55;
+	addr[0x0AAA] = 0x80;
+	addr[0x0AAA] = 0xAA;
+	addr[0x0555] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char*)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_char*)(info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *)info->start[0];
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0AAA] = 0xAA;
+	addr[0x0555] = 0x55;
+	addr[0x0AAA] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/hermes/hermes.c b/u-boot/board/hermes/hermes.c
new file mode 100644
index 0000000..9a3e5f6
--- /dev/null
+++ b/u-boot/board/hermes/hermes.c
@@ -0,0 +1,606 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static ulong board_init (void);
+static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
+							uchar * msg);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,					/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1fe77c35, 0xffaffc34, 0x1fa57c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
+	0xf0afcc00, 0xe1bb8c06, 0x1ff77c47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7ffffc07,					/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (HERMES...)
+ *
+ * Return code for board revision and network speed
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+	char *e;
+
+	puts ("Board: ");
+
+	if (!s || strncmp (s, "HERMES", 6)) {
+		puts ("### No HW ID - assuming HERMES-PRO");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+	gd->board_type = board_init ();
+
+	printf ("  Rev. %ld.x\n", (gd->board_type >> 16));
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = 0x0400;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 1 to the SDRAM banks at preliminary address
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	/* HERMES-PRO boards have only one bank SDRAM */
+
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mamr = 0xD0802114;
+	memctl->memc_mcr = 0x80002105;
+	udelay (1);
+	memctl->memc_mamr = 0xD0802118;
+	memctl->memc_mcr = 0x80002130;
+	udelay (1);
+	memctl->memc_mamr = 0xD0802114;
+	memctl->memc_mcr = 0x80002106;
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {					/* back to 8 columns            */
+		size = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	udelay (10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define	PB_LED_3	0x00020000	/* Status LED's */
+#define PB_LED_2	0x00010000
+#define PB_LED_1	0x00008000
+#define PB_LED_0	0x00004000
+
+#define PB_LED_ALL	(PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
+
+#define	PC_REP_SPD1	0x00000800
+#define PC_REP_SPD0	0x00000400
+
+#define PB_RESET_2081	0x00000020	/* Reset PEB2081 */
+
+#define PB_MAI_4	0x00000010	/* Configuration */
+#define PB_MAI_3	0x00000008
+#define PB_MAI_2	0x00000004
+#define PB_MAI_1	0x00000002
+#define PB_MAI_0	0x00000001
+
+#define PB_MAI_ALL	(PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
+
+
+#define	PC_REP_MGRPRS	0x0200
+#define PC_REP_SPD	0x0040		/* Select 100 Mbps */
+#define PC_REP_RES	0x0004
+#define PC_BIT14	0x0002		/* ??? */
+#define PC_BIT15	0x0001		/* ??? ENDSL ?? */
+
+/* ------------------------------------------------------------------------- */
+
+static ulong board_init (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	ulong reg, revision, speed = 100;
+	int ethspeed;
+	char *s;
+
+	if ((s = getenv ("ethspeed")) != NULL) {
+		if (strcmp (s, "100") == 0) {
+			ethspeed = 100;
+		} else if (strcmp (s, "10") == 0) {
+			ethspeed = 10;
+		} else {
+			ethspeed = 0;
+		}
+	} else {
+		ethspeed = 0;
+	}
+
+	/* Configure Port B Output Pins => 0x0003cc3F */
+	reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
+			PB_MAI_ALL;
+	immr->im_cpm.cp_pbpar &= ~reg;
+	immr->im_cpm.cp_pbodr &= ~reg;
+	immr->im_cpm.cp_pbdat &= ~reg;	/* all 0 */
+	immr->im_cpm.cp_pbdir |= reg;
+
+	/* Check hardware revision */
+	if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
+		/*
+		 * Revision 3.x hardware
+		 */
+		revision = 3;
+
+		immr->im_ioport.iop_pcdat = 0x0240;
+		immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14);	/* = 0x0246 */
+		immr->im_ioport.iop_pcdat |= PC_REP_RES;
+	} else {
+		immr->im_ioport.iop_pcdat = 0x0002;
+		immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15);	/* = 0x0207 */
+
+		if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
+			/*
+			 * Revision 2.x hardware: PC9 connected to PB21
+			 */
+			revision = 2;
+
+			if (ethspeed == 0) {
+				/* both 10 and 100 Mbps allowed:
+				 * select 10 Mbps and autonegotiation
+				 */
+				puts ("  [10+100]");
+				immr->im_cpm.cp_pbdat = 0;	/* SPD1:SPD0 = 0:0 - autonegot. */
+				speed = 10;
+			} else if (ethspeed == 10) {
+				/* we are asked for 10 Mbps,
+				 * so select 10 Mbps
+				 */
+				puts ("  [10]");
+				immr->im_cpm.cp_pbdat = 0;	/* ??? */
+				speed = 10;
+			} else {
+				/* anything else:
+				 * select 100 Mbps
+				 */
+				puts ("  [100]");
+				immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
+				/* SPD1:SPD0 = 1:1 - 100 Mbps */
+				speed = 100;
+			}
+			immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
+
+			/* must be run from RAM  */
+			/* start_lxt980 (speed); */
+		/*************************/
+		} else {
+			/*
+			 * Revision 1.x hardware
+			 */
+			revision = 1;
+
+			immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14;	/* = 0x0202 */
+			immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15);	/* = 0x0247 */
+
+			if (ethspeed == 0) {
+				/* both 10 and 100 Mbps allowed:
+				 * select 100 Mbps and autonegotiation
+				 */
+				puts ("  [10+100]");
+				immr->im_cpm.cp_pbdat = 0;	/* SPD1:SPD0 = 0:0 - autonegot. */
+				immr->im_ioport.iop_pcdat |= PC_REP_SPD;
+			} else if (ethspeed == 10) {
+				/* we are asked for 10 Mbps,
+				   * so select 10 Mbps
+				 */
+				puts ("  [10]");
+				immr->im_cpm.cp_pbdat = PC_REP_SPD0;	/* SPD1:SPD0 = 0:1 - 10 Mbps */
+			} else {
+				/* anything else:
+				   * select 100 Mbps
+				 */
+				puts ("  [100]");
+				immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
+				/* SPD1:SPD0 = 1:1 - 100 Mbps */
+				immr->im_ioport.iop_pcdat |= PC_REP_SPD;
+			}
+
+			immr->im_ioport.iop_pcdat |= PC_REP_RES;
+		}
+	}
+	SHOW_BOOT_PROGRESS (0x00);
+
+	return ((revision << 16) | (speed & 0xFFFF));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define SCC_SM		1			/* Index => SCC2 */
+#define	PROFF		PROFF_SCC2
+
+#define SMI_MSGLEN	8			/* Length of SMI Messages        */
+
+#define PHYGPCR_ADDR	0x109	/* Port Enable               */
+#define PHYPCR_ADDR	0x132		/* PHY Port Control Reg. (port 1)    */
+#define LEDPCR_ADDR	0x141		/* LED Port Control Reg.         */
+#define RPRESET_ADDR	0x144	/* Repeater Reset            */
+
+#define PHYPCR_SPEED	0x2000	/* on for 100 Mbps, off for 10 Mbps  */
+#define PHYPCR_AN	0x1000		/* on to enable  Auto-Negotiation    */
+#define PHYPCR_REST_AN	0x0200	/* on to restart Auto-Negotiation    */
+#define PHYPCR_FDX	0x0100		/* on for Full Duplex, off for HDX   */
+#define PHYPCR_COLT	0x0080		/* on to enable COL signal test      */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Must run from RAM:
+ * uses parameter RAM area which is used for stack while running from ROM
+ */
+void hermes_start_lxt980 (int speed)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
+	volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
+	volatile cbd_t *bd;
+	volatile hdlc_pram_t *hp;
+	uchar smimsg[SMI_MSGLEN];
+	ushort phypcrval;
+	uint bd_off;
+	int pnr;
+
+	printf ("LXT9880: %3d Mbps\n", speed);
+
+	immr->im_ioport.iop_paodr |= 0x0008;	/* init PAODR: PA12 (TXD2) open drain */
+	immr->im_ioport.iop_papar |= 0x400c;	/* init PAPAR: TXD2, RXD2, BRGO4 */
+	immr->im_ioport.iop_padir &= 0xbff3;	/* init PADIR: BRGO4 */
+	immr->im_ioport.iop_padir |= 0x4000;
+
+	/* get temporary BD; no need for permanent alloc */
+	bd_off = dpram_base_align (8);
+
+	bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
+
+	bd->cbd_bufaddr = 0;
+	bd->cbd_datlen = 0;
+	bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
+
+	/* init. baudrate generator BRG4 */
+	cp->cp_brgc4 = (0x00010000 | (50 << 1));	/* output 1 MHz */
+
+	cp->cp_sicr &= 0xFFFF00FF;	/* SICR: mask SCC2 */
+	cp->cp_sicr |= 0x00001B00;	/* SICR: SCC2 clk BRG4 */
+
+	/* init SCC_SM register */
+	sp->scc_psmr = 0x0000;		/* init PSMR: no additional flags */
+	sp->scc_todr = 0x0000;
+	sp->scc_dsr = 0x7e7e;
+
+	/* init. SCC_SM parameter area */
+	hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
+
+	hp->tbase = bd_off;			/* offset from beginning of DPRAM */
+
+	hp->rfcr = 0x18;
+	hp->tfcr = 0x18;
+	hp->mrblr = 10;
+
+	hp->c_mask = 0x0000f0b8;
+	hp->c_pres = 0x0000ffff;
+
+	hp->disfc = 0;
+	hp->crcec = 0;
+	hp->abtsc = 0;
+	hp->nmarc = 0;
+	hp->retrc = 0;
+
+	hp->mflr = 10;
+
+	hp->rfthr = 1;
+
+	hp->hmask = 0;
+	hp->haddr1 = 0;
+	hp->haddr2 = 0;
+	hp->haddr3 = 0;
+	hp->haddr4 = 0;
+
+	cp->cp_cpcr = SCC_SM << 6 | 0x0001;	/* SCC_SM: init TX/RX params */
+	while (cp->cp_cpcr & CPM_CR_FLG);
+
+	/* clear all outstanding SCC events */
+	sp->scc_scce = ~0;
+
+	/* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
+	sp->scc_gsmrh = 0;
+	sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
+			SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
+
+#if 0
+	smimsg[0] = 0x00;			/* CHIP/HUB ID */
+	smimsg[1] = 0x38;			/* WRITE CMD */
+	smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
+	smimsg[3] = RPRESET_ADDR >> 4;
+	smimsg[4] = 0x01;
+	smimsg[5] = 0x00;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+#endif
+
+	smimsg[0] = 0x7f;			/* BROADCAST */
+	smimsg[1] = 0x34;			/* ASSIGN HUB ID */
+	smimsg[2] = 0x00;
+	smimsg[3] = 0x00;
+	smimsg[4] = 0x00;			/* HUB ID = 0 */
+	smimsg[5] = 0x00;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	smimsg[0] = 0x7f;			/* BROADCAST */
+	smimsg[1] = 0x3c;			/* SET ARBOUT TO 0 */
+	smimsg[2] = 0x00;			/* ADDRESS = 0 */
+	smimsg[3] = 0x00;
+	smimsg[4] = 0x00;			/* DATA = 0 */
+	smimsg[5] = 0x00;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	if (speed == 100) {
+		phypcrval = PHYPCR_SPEED;	/* 100 MBIT, disable autoneg. */
+	} else {
+		phypcrval = 0;			/* 10 MBIT, disable autoneg. */
+	}
+
+	/* send MSGs */
+	for (pnr = 0; pnr < 8; pnr++) {
+		smimsg[0] = 0x00;		/* CHIP/HUB ID */
+		smimsg[1] = 0x38;		/* WRITE CMD */
+		smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
+		smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
+		smimsg[4] = (unsigned char) (phypcrval & 0xff);
+		smimsg[5] = (unsigned char) (phypcrval >> 8);
+		smimsg[6] = 0x00;
+		smimsg[7] = 0x00;
+
+		send_smi_frame (sp, bd, smimsg);
+	}
+
+	smimsg[0] = 0x00;			/* CHIP/HUB ID */
+	smimsg[1] = 0x38;			/* WRITE CMD */
+	smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
+	smimsg[3] = PHYGPCR_ADDR >> 4;
+	smimsg[4] = 0xff;			/* enable port 1-8 */
+	smimsg[5] = 0x01;			/* enable MII1 (0x01) */
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	smimsg[0] = 0x00;			/* CHIP/HUB ID */
+	smimsg[1] = 0x38;			/* WRITE CMD */
+	smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
+	smimsg[3] = LEDPCR_ADDR >> 4;
+	smimsg[4] = 0xaa;			/* Port 1-8 Conf.bits = 10 (Hardware control) */
+	smimsg[5] = 0xaa;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	/*
+	 * Disable Transmitter (so that we can free the BD, too)
+	 */
+	sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
+							uchar * msg)
+{
+#ifdef DEBUG
+	unsigned hub, chip, cmd, length, addr;
+
+	hub = msg[0] & 0x1F;
+	chip = msg[0] >> 5;
+	cmd = msg[1] & 0x1F;
+	length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
+	addr = (msg[2] >> 4) | (msg[3] << 4);
+
+	printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
+			"%02x %02x %02x %02x\n",
+			hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
+#endif /* DEBUG */
+
+	bd->cbd_bufaddr = (uint) msg;
+	bd->cbd_datlen = SMI_MSGLEN;
+	bd->cbd_sc |= BD_SC_READY;
+
+	/* wait for msg transmitted */
+	while ((sp->scc_scce & 0x0002) == 0);
+	/* clear all events */
+	sp->scc_scce = ~0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void show_boot_progress (int status)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	if (status < -32) status = -1;	/* let things compatible */
+	status ^= 0x0F;
+	status = (status & 0x0F) << 14;
+	immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/hermes/u-boot.lds b/u-boot/board/hermes/u-boot.lds
new file mode 100644
index 0000000..456140d
--- /dev/null
+++ b/u-boot/board/hermes/u-boot.lds
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    board/hermes/libhermes.o		(.text*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/hermes/u-boot.lds.debug b/u-boot/board/hermes/u-boot.lds.debug
new file mode 100644
index 0000000..7038ebc
--- /dev/null
+++ b/u-boot/board/hermes/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    arch/powerpc/lib/ppcstring.o	(.text)
+    arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+    arch/powerpc/lib/time.o		(.text)
+    arch/powerpc/lib/ticks.o		(.text)
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/hidden_dragon/Makefile b/u-boot/board/hidden_dragon/Makefile
new file mode 100644
index 0000000..befc92a
--- /dev/null
+++ b/u-boot/board/hidden_dragon/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS =  $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/hidden_dragon/README b/u-boot/board/hidden_dragon/README
new file mode 100644
index 0000000..529fe2b
--- /dev/null
+++ b/u-boot/board/hidden_dragon/README
@@ -0,0 +1,60 @@
+U-Boot for Hidden Dragon board
+------------------------------
+
+Hidden Dragon is a MPC824x-based board by Motorola. For the most
+part it is similar to Sandpoint8245 board. So unless otherwise
+mentioned, the codes in this directory are adapted from ../sandpoint
+directory.
+
+Apparently there are very few of this board out there. Even Motorola
+website does not have any info on it.
+
+RAM:
+  start = 0x0000 0000
+  size	= 0x0200 0000 (32 MB)
+
+Flash:
+  BANK ONE:
+    start = 0xFFE0 0000
+    size  = 0x0020 0000 (2 MB)
+    flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
+    flash sectors = 16K, 2x8K, 32K, 31x64K
+
+  BANK TWO:
+    NONE
+
+The processor interrupt vectors reside on the first 256 bytes
+starting from address 0xFFF00000. The "reset vector" (first
+instruction executed after reset) is located on 0xFFF0 0100.
+
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is located in flash separately from
+U-Boot, at the second sector of the first flash bank, starting from
+0xFFE04000 until 0xFFE06000 (8KB).
+
+Network:
+  - RTL8139 chip on the base board	  (SUPPORTED)
+  - RTL8129 chip on the processor board	  (NOT SUPPORTED)
+
+Serial:
+  - Two NS16550 compatible UART on the processor board	(SUPPORTED)
+  - One NS16550 compatible UART on the base board	(UNTESTED)
+
+Misc:
+  VIA686A PCI SuperIO peripheral controller
+  - 2 USB ports		    (UNTESTED)
+  - 2 PS2 ports		    (UNTESTED)
+  - Parallel port	    (UNTESTED)
+  - IDE & floppy interface  (UNTESTED)
+
+  S3 Savage4 video card	    (UNTESTED)
+
+TODO:
+-----
+- Support for the VIA686A based peripherals
+- The RTL8139 driver frequently gives rx error.
+- Support for RTL8129 network controller. (Why is the support removed from
+  rtl8139.c driver?)
+
+(C) Copyright 2004
+Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
diff --git a/u-boot/board/hidden_dragon/early_init.S b/u-boot/board/hidden_dragon/early_init.S
new file mode 100644
index 0000000..61b4b55
--- /dev/null
+++ b/u-boot/board/hidden_dragon/early_init.S
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
+		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CONFIG_SYS_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr
diff --git a/u-boot/board/hidden_dragon/flash.c b/u-boot/board/hidden_dragon/flash.c
new file mode 100644
index 0000000..2ce1dc4
--- /dev/null
+++ b/u-boot/board/hidden_dragon/flash.c
@@ -0,0 +1,575 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <w83c553f.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+	__attribute__ ((const));
+
+typedef struct {
+	FLASH_WORD_SIZE extval;
+	unsigned short intval;
+} map_entry;
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B, FLASH_AM040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for (p = &chip_map[0];
+	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+		if (p->extval == chip) {
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+
+	/* find vendor id */
+	for (p = &mfct_map[0];
+	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+		if (p->extval == mfct) {
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+
+	return result;
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	/* Enable writes to Hidden Dragon flash */
+	{
+		register unsigned char temp;
+
+		CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				  temp);
+		temp &= ~0x20;	/* clear BIOSWP bit */
+		CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				   temp);
+	}
+
+	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE *const flash =
+			(FLASH_WORD_SIZE *) base_address;
+
+		flash[0xAAA << (3 * i)] = 0xaa;
+		flash[0x555 << (3 * i)] = 0x55;
+		flash[0xAAA << (3 * i)] = 0x90;
+		__asm__ __volatile__ ("sync");
+
+		pflinfo->flash_id =
+			flash_id (flash[0x0], flash[0x2 + 14 * i]);
+
+		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			pflinfo->size = 0x00080000;
+			pflinfo->sector_count = 8;
+			for (j = 0; j < 8; j++) {
+				pflinfo->start[j] =
+					base_address + 0x00010000 * j;
+				pflinfo->protect[j] = flash[(j << 16) | 0x2];
+			}
+			break;
+		case FLASH_STM800AB:
+			pflinfo->size = 0x00100000;
+			pflinfo->sector_count = 19;
+			pflinfo->start[0] = base_address;
+			pflinfo->start[1] = base_address + 0x4000;
+			pflinfo->start[2] = base_address + 0x6000;
+			pflinfo->start[3] = base_address + 0x8000;
+			for (j = 1; j < 16; j++) {
+				pflinfo->start[j + 3] =
+					base_address + 0x00010000 * j;
+			}
+			break;
+		default:
+			/* The chip used is not listed in flash_id
+			   TODO: Change this to explicitly detect the flash type
+			 */
+			{
+				int sector_addr = base_address;
+
+				pflinfo->size = 0x00200000;
+				pflinfo->sector_count = 35;
+				pflinfo->start[0] = sector_addr;
+				sector_addr += 0x4000;	/* 16K */
+				pflinfo->start[1] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[2] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[3] = sector_addr;
+				sector_addr += 0x8000;	/* 32K */
+
+				for (j = 4; j < 35; j++) {
+					pflinfo->start[j] = sector_addr;
+					sector_addr += 0x10000;	/* 64K */
+				}
+			}
+			break;
+		}
+		/* Protect monitor and environment sectors
+		 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR,
+			       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+			       &flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__ ("sync");
+	}
+
+	/* only have 1 bank */
+	return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+		"  Size: %lu KB in %d Sectors\n",
+		mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+		     (flash != (unsigned long *) info->start[i] + size)
+		     && erased; flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+			(i % 5) ? "" : "\n   ",
+			info->start[i],
+			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] +
+						    ((info->start[sect] -
+						      info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+						       info->
+						       start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+				     info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/hidden_dragon/hidden_dragon.c b/u-boot/board/hidden_dragon/hidden_dragon.c
new file mode 100644
index 0000000..027aa45
--- /dev/null
+++ b/u-boot/board/hidden_dragon/hidden_dragon.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <netdev.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Hidden Dragon "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	/* TODO: Implement board test */
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_hidden_dragon_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_hidden_dragon_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/hidden_dragon/speed.h b/u-boot/board/hidden_dragon/speed.h
new file mode 100644
index 0000000..3f32a14
--- /dev/null
+++ b/u-boot/board/hidden_dragon/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK			CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/u-boot/board/hymod/Makefile b/u-boot/board/hymod/Makefile
new file mode 100644
index 0000000..6b56f33
--- /dev/null
+++ b/u-boot/board/hymod/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/hymod/bsp.c b/u-boot/board/hymod/bsp.c
new file mode 100644
index 0000000..9a92941
--- /dev/null
+++ b/u-boot/board/hymod/bsp.c
@@ -0,0 +1,403 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <asm/iopin_8260.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*-----------------------------------------------------------------------
+ * Board Special Commands: FPGA load/store, EEPROM erase
+ */
+
+#if defined(CONFIG_CMD_BSP)
+
+#define LOAD_SUCCESS		0
+#define LOAD_FAIL_NOCONF	1
+#define LOAD_FAIL_NOINIT	2
+#define LOAD_FAIL_NODONE	3
+
+#define STORE_SUCCESS		0
+
+/*
+ * Programming the Hymod FPGAs
+ *
+ * The 8260 io port config table is set up so that the INIT pin is
+ * held Low (Open Drain output 0) - this will delay the automatic
+ * Power-On config until INIT is released (by making it an input).
+ *
+ * If the FPGA has been programmed before, then the assertion of PROGRAM
+ * will initiate configuration (i.e. it begins clearing the RAM).
+ *
+ * When the FPGA is ready to receive configuration data (either after
+ * releasing INIT after Power-On, or after asserting PROGRAM), it will
+ * pull INIT high.
+ *
+ * Notes from Paul Dunn:
+ *
+ *  1. program pin should be forced low for >= 300ns
+ *     (about 20 bus clock cycles minimum).
+ *
+ *  2. then wait for init to go high, which signals
+ *     that the FPGA has cleared its internal memory
+ *     and is ready to load
+ *
+ *  3. perform load writes of entire config file
+ *
+ *  4. wait for done to go high, which should be
+ *     within a few bus clock cycles. If done has not
+ *     gone high after reasonable period, then load
+ *     has not worked (wait several ms?)
+ */
+
+int
+fpga_load (int mezz, uchar *addr, ulong size)
+{
+	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
+	xlx_info_t *fp;
+	xlx_iopins_t *fpgaio;
+	volatile uchar *fpgabase;
+	volatile uint cnt;
+	uchar *eaddr = addr + size;
+	int result;
+
+	if (mezz)
+		fp = &cp->mezz.xlx[0];
+	else
+		fp = &cp->main.xlx[0];
+
+	if (!fp->mmap.prog.exists)
+		return (LOAD_FAIL_NOCONF);
+
+	fpgabase = (uchar *)fp->mmap.prog.base;
+	fpgaio = &fp->iopins;
+
+	/* set enable HIGH if required */
+	if (fpgaio->enable_pin.flag)
+		iopin_set_high (&fpgaio->enable_pin);
+
+	/* ensure INIT is released (set it to be an input) */
+	iopin_set_in (&fpgaio->init_pin);
+
+	/* toggle PROG Low then High (will already be Low after Power-On) */
+	iopin_set_low (&fpgaio->prog_pin);
+	udelay (1);	/* minimum 300ns - 1usec should do it */
+	iopin_set_high (&fpgaio->prog_pin);
+
+	/* wait for INIT High */
+	cnt = 0;
+	while (!iopin_is_high (&fpgaio->init_pin))
+		if (++cnt == 10000000) {
+			result = LOAD_FAIL_NOINIT;
+			goto done;
+		}
+
+	/* write configuration data */
+	while (addr < eaddr)
+		*fpgabase = *addr++;
+
+	/* wait for DONE High */
+	cnt = 0;
+	while (!iopin_is_high (&fpgaio->done_pin))
+		if (++cnt == 100000000) {
+			result = LOAD_FAIL_NODONE;
+			goto done;
+		}
+
+	/* success */
+	result = LOAD_SUCCESS;
+
+  done:
+
+	if (fpgaio->enable_pin.flag)
+		iopin_set_low (&fpgaio->enable_pin);
+
+	return (result);
+}
+
+/* ------------------------------------------------------------------------- */
+int
+do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar *addr, *save_addr;
+	ulong size;
+	int mezz, arg, result;
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strcmp (argv[1], "info") == 0) {
+			printf ("\nHymod FPGA Info...\n");
+			printf ("\t\t\t\tAddress\t\tSize\n");
+			printf ("\tMain Configuration:\t0x%08x\t%d\n",
+				FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
+			printf ("\tMain Register:\t\t0x%08x\t%d\n",
+				FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
+			printf ("\tMain Port:\t\t0x%08x\t%d\n",
+				FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
+			printf ("\tMezz Configuration:\t0x%08x\t%d\n",
+				FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
+			return 0;
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[1], "store") == 0) {
+			addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
+
+			save_addr = addr;
+#if 0
+			/* fpga readback unimplemented */
+			while (more readback data)
+				*addr++ = *fpga;
+			result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
+#else
+			result = STORE_SUCCESS;
+#endif
+
+			if (result == STORE_SUCCESS) {
+				printf ("SUCCEEDED (%d bytes)\n",
+					addr - save_addr);
+				return 0;
+			} else
+				printf ("FAILED (%d bytes)\n",
+					addr - save_addr);
+			return 1;
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[1], "tftp") == 0) {
+			copy_filename (BootFile, argv[2], sizeof (BootFile));
+			load_addr = simple_strtoul (argv[3], NULL, 16);
+			NetBootFileXferSize = 0;
+
+			if (NetLoop (TFTP) <= 0) {
+				printf ("tftp transfer failed - aborting "
+					"fgpa load\n");
+				return 1;
+			}
+
+			if (NetBootFileXferSize == 0) {
+				printf ("can't determine file size - "
+					"aborting fpga load\n");
+				return 1;
+			}
+
+			printf ("File transfer succeeded - "
+				"beginning fpga load...");
+
+			result = fpga_load (0, (uchar *) load_addr,
+				NetBootFileXferSize);
+
+			if (result == LOAD_SUCCESS) {
+				printf ("SUCCEEDED\n");
+				return 0;
+			} else if (result == LOAD_FAIL_NOCONF)
+				printf ("FAILED (no CONF)\n");
+			else if (result == LOAD_FAIL_NOINIT)
+				printf ("FAILED (no INIT)\n");
+			else
+				printf ("FAILED (no DONE)\n");
+			return 1;
+
+		}
+		/* fall through ... */
+
+	case 5:
+		if (strcmp (argv[1], "load") == 0) {
+			if (argc == 5) {
+				if (strcmp (argv[2], "main") == 0)
+					mezz = 0;
+				else if (strcmp (argv[2], "mezz") == 0)
+					mezz = 1;
+				else {
+					printf ("FPGA type must be either "
+						"`main' or `mezz'\n");
+					return 1;
+				}
+				arg = 3;
+			} else {
+				mezz = 0;
+				arg = 2;
+			}
+
+			addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
+			size = (ulong) simple_strtoul (argv[arg], NULL, 16);
+
+			result = fpga_load (mezz, addr, size);
+
+			if (result == LOAD_SUCCESS) {
+				printf ("SUCCEEDED\n");
+				return 0;
+			} else if (result == LOAD_FAIL_NOCONF)
+				printf ("FAILED (no CONF)\n");
+			else if (result == LOAD_FAIL_NOINIT)
+				printf ("FAILED (no INIT)\n");
+			else
+				printf ("FAILED (no DONE)\n");
+			return 1;
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	return cmd_usage(cmdtp);
+}
+U_BOOT_CMD(
+	fpga,	6,	1,	do_fpga,
+	"FPGA sub-system",
+	"load [type] addr size\n"
+	"  - write the configuration data at memory address `addr',\n"
+	"    size `size' bytes, into the FPGA of type `type' (either\n"
+	"    `main' or `mezz', default `main'). e.g.\n"
+	"        `fpga load 100000 7d8f'\n"
+	"    loads the main FPGA with config data at address 100000\n"
+	"    HEX, size 7d8f HEX (32143 DEC) bytes\n"
+	"fpga tftp file addr\n"
+	"  - transfers `file' from the tftp server into memory at\n"
+	"    address `addr', then writes the entire file contents\n"
+	"    into the main FPGA\n"
+	"fpga store addr\n"
+	"  - read configuration data from the main FPGA (the mezz\n"
+	"    FPGA is write-only), into address `addr'. There must be\n"
+	"    enough memory available at `addr' to hold all the config\n"
+	"    data - the size of which is determined by VC:???\n"
+	"fpga info\n"
+	"  - print information about the Hymod FPGA, namely the\n"
+	"    memory addresses at which the four FPGA local bus\n"
+	"    address spaces appear in the physical address space"
+);
+/* ------------------------------------------------------------------------- */
+int
+do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar data[HYMOD_EEPROM_SIZE];
+	uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
+
+	switch (argc) {
+
+	case 1:
+		addr |= HYMOD_EEOFF_MAIN;
+		break;
+
+	case 2:
+		if (strcmp (argv[1], "main") == 0) {
+			addr |= HYMOD_EEOFF_MAIN;
+			break;
+		}
+		if (strcmp (argv[1], "mezz") == 0) {
+			addr |= HYMOD_EEOFF_MEZZ;
+			break;
+		}
+		/* fall through ... */
+
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	memset (data, 0, HYMOD_EEPROM_SIZE);
+
+	eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
+
+	return 0;
+}
+U_BOOT_CMD(
+	eeclear,	1,	0,	do_eecl,
+	"Clear the eeprom on a Hymod board",
+	"[type]\n"
+	"  - write zeroes into the EEPROM on the board of type `type'\n"
+	"    (`type' is either `main' or `mezz' - default `main')\n"
+	"    Note: the EEPROM write enable jumper must be installed"
+);
+
+/* ------------------------------------------------------------------------- */
+
+int
+do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#if 0
+	int rc;
+#endif
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+	extern void eth_loopback_test (void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+	printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
+
+#if 0
+	/* Load FPGA with test program */
+
+	printf ("Loading test FPGA program ...");
+
+	rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
+
+	switch (rc) {
+
+	case LOAD_SUCCESS:
+		printf (" SUCCEEDED\n");
+		break;
+
+	case LOAD_FAIL_NOCONF:
+		printf (" FAILED (no configuration space defined)\n");
+		return 1;
+
+	case LOAD_FAIL_NOINIT:
+		printf (" FAILED (timeout - no INIT signal seen)\n");
+		return 1;
+
+	case LOAD_FAIL_NODONE:
+		printf (" FAILED (timeout - no DONE signal seen)\n");
+		return 1;
+
+	default:
+		printf (" FAILED (unknown return code from fpga_load\n");
+		return 1;
+	}
+
+	/* run Local Bus <=> Xilinx tests */
+
+	/* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
+
+	/* run SDRAM test */
+#endif
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+	/* run Ethernet test */
+	eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/hymod/config.mk b/u-boot/board/hymod/config.mk
new file mode 100644
index 0000000..ae766bc
--- /dev/null
+++ b/u-boot/board/hymod/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# HYMOD boards
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+
+OBJCFLAGS = --remove-section=.ppcenv
+
+LDSCRIPT := $(SRCTREE)/board/hymod/u-boot.lds
diff --git a/u-boot/board/hymod/eeprom.c b/u-boot/board/hymod/eeprom.c
new file mode 100644
index 0000000..4d48d7d
--- /dev/null
+++ b/u-boot/board/hymod/eeprom.c
@@ -0,0 +1,694 @@
+/*
+ * (C) Copyright 2001
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+
+/* imports from fetch.c */
+extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
+
+/* imports from input.c */
+extern int hymod_get_serno (const char *);
+
+/* this is relative to the root of the server's tftp directory */
+static char *def_bddb_cfgdir = "/hymod/bddb";
+
+static int
+hymod_eeprom_load (int which, hymod_eeprom_t *ep)
+{
+	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
+		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
+	unsigned offset = 0;
+	uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp;
+	hymod_eehdr_t hdr;
+	ulong len, crc;
+
+	memset (ep, 0, sizeof *ep);
+
+	eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr));
+	offset += sizeof (hdr);
+
+	if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER ||
+	  (len = hdr.len) > HYMOD_EEPROM_MAXLEN)
+	    return (0);
+
+	eeprom_read (dev_addr, offset, data, len);
+	offset += len;
+
+	eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
+	offset += sizeof (ulong);
+
+	if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
+		return (0);
+
+	ep->ver = hdr.ver;
+	dp = data; edp = dp + len;
+
+	for (;;) {
+		ulong rtyp;
+		uchar rlen, *rdat;
+
+		rtyp = *dp++;
+		if ((rtyp & 0x80) == 0)
+			rlen = *dp++;
+		else {
+			uchar islarge = rtyp & 0x40;
+
+			rtyp = ((rtyp & 0x3f) << 8) | *dp++;
+			if (islarge) {
+				rtyp = (rtyp << 8) | *dp++;
+				rtyp = (rtyp << 8) | *dp++;
+			}
+
+			rlen = *dp++;
+			rlen = (rlen << 8) | *dp++;
+			if (islarge) {
+				rlen = (rlen << 8) | *dp++;
+				rlen = (rlen << 8) | *dp++;
+			}
+		}
+
+		if (rtyp == 0)
+			break;
+
+		rdat = dp;
+		dp += rlen;
+
+		if (dp > edp)	/* error? */
+			break;
+
+		switch (rtyp) {
+
+		case HYMOD_EEREC_SERNO:		/* serial number */
+			if (rlen == sizeof (ulong))
+				ep->serno = \
+					((ulong)rdat[0] << 24) | \
+					((ulong)rdat[1] << 16) | \
+					((ulong)rdat[2] << 8) | \
+					(ulong)rdat[3];
+			break;
+
+		case HYMOD_EEREC_DATE:		/* date */
+			if (rlen == sizeof (hymod_date_t)) {
+				ep->date.year = ((ushort)rdat[0] << 8) | \
+					(ushort)rdat[1];
+				ep->date.month = rdat[2];
+				ep->date.day = rdat[3];
+			}
+			break;
+
+		case HYMOD_EEREC_BATCH:		/* batch */
+			if (rlen <= HYMOD_MAX_BATCH)
+				memcpy (ep->batch, rdat, ep->batchlen = rlen);
+			break;
+
+		case HYMOD_EEREC_TYPE:		/* board type */
+			if (rlen == 1)
+				ep->bdtype = *rdat;
+			break;
+
+		case HYMOD_EEREC_REV:		/* board revision */
+			if (rlen == 1)
+				ep->bdrev = *rdat;
+			break;
+
+		case HYMOD_EEREC_SDRAM:		/* sdram size(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->sdramsz[i] = rdat[i];
+				ep->nsdram = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_FLASH:		/* flash size(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->flashsz[i] = rdat[i];
+				ep->nflash = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_ZBT:		/* zbt ram size(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->zbtsz[i] = rdat[i];
+				ep->nzbt = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_XLXTYP:	/* xilinx fpga type(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].type = rdat[i];
+				ep->nxlx = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_XLXSPD:	/* xilinx fpga speed(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].speed = rdat[i];
+			}
+			break;
+
+		case HYMOD_EEREC_XLXTMP:	/* xilinx fpga temperature(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].temp = rdat[i];
+			}
+			break;
+
+		case HYMOD_EEREC_XLXGRD:	/* xilinx fpga grade(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].grade = rdat[i];
+			}
+			break;
+
+		case HYMOD_EEREC_CPUTYP:	/* CPU type */
+			if (rlen == 1)
+				ep->mpc.type = *rdat;
+			break;
+
+		case HYMOD_EEREC_CPUSPD:	/* CPU speed */
+			if (rlen == 1)
+				ep->mpc.cpuspd = *rdat;
+			break;
+
+		case HYMOD_EEREC_CPMSPD:	/* CPM speed */
+			if (rlen == 1)
+				ep->mpc.cpmspd = *rdat;
+			break;
+
+		case HYMOD_EEREC_BUSSPD:	/* bus speed */
+			if (rlen == 1)
+				ep->mpc.busspd = *rdat;
+			break;
+
+		case HYMOD_EEREC_HSTYPE:	/* hs-serial chip type */
+			if (rlen == 1)
+				ep->hss.type = *rdat;
+			break;
+
+		case HYMOD_EEREC_HSCHIN:	/* num hs-serial input chans */
+			if (rlen == 1)
+				ep->hss.nchin = *rdat;
+			break;
+
+		case HYMOD_EEREC_HSCHOUT:	/* num hs-serial output chans */
+			if (rlen == 1)
+				ep->hss.nchout = *rdat;
+			break;
+
+		default:	/* ignore */
+			break;
+		}
+	}
+
+	return (1);
+}
+
+/* maps an ascii "name=value" into a binary eeprom data record */
+typedef
+	struct _eerec_map {
+		char *name;
+		uint type;
+		uchar *(*handler) \
+			(struct _eerec_map *, uchar *, uchar *, uchar *);
+		uint length;
+		uint maxlen;
+	}
+eerec_map_t;
+
+static uchar *
+uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	char *eval;
+	ulong lval;
+
+	lval = simple_strtol ((char *)val, &eval, 10);
+
+	if ((uchar *)eval == val || *eval != '\0') {
+		printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
+		return (NULL);
+	}
+
+	if (dp + 2 + rp->length > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = rp->length;
+
+	switch (rp->length) {
+
+	case 1:
+		if (lval >= 256) {
+			printf ("%s rec value (%lu) out of range (0-255)\n",
+				rp->name, lval);
+			return (NULL);
+		}
+		*dp++ = lval;
+		break;
+
+	case 2:
+		if (lval >= 65536) {
+			printf ("%s rec value (%lu) out of range (0-65535)\n",
+				rp->name, lval);
+			return (NULL);
+		}
+		*dp++ = lval >> 8;
+		*dp++ = lval;
+		break;
+
+	case 4:
+		*dp++ = lval >> 24;
+		*dp++ = lval >> 16;
+		*dp++ = lval >> 8;
+		*dp++ = lval;
+		break;
+
+	default:
+		printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length);
+		return (NULL);
+	}
+
+	return (dp);
+}
+
+static uchar *
+date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	hymod_date_t date;
+	char *p = (char *)val;
+	char *ep;
+	ulong lval;
+
+	lval = simple_strtol (p, &ep, 10);
+	if (ep == p || *ep++ != '-') {
+bad_date:
+		printf ("%s rec (%s) is not a valid date\n", rp->name, val);
+		return (NULL);
+	}
+	if (lval >= 65536)
+		goto bad_date;
+	date.year = lval;
+
+	lval = simple_strtol (p = ep, &ep, 10);
+	if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
+		goto bad_date;
+	date.month = lval;
+
+	lval = simple_strtol (p = ep, &ep, 10);
+	if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
+		goto bad_date;
+	date.day = lval;
+
+	if (dp + 2 + rp->length > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = rp->length;
+	*dp++ = date.year >> 8;
+	*dp++ = date.year;
+	*dp++ = date.month;
+	*dp++ = date.day;
+
+	return (dp);
+}
+
+static uchar *
+string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	uint len;
+
+	if ((len = strlen ((char *)val)) > rp->maxlen) {
+		printf ("%s rec (%s) string is too long (%d>%d)\n",
+			rp->name, val, len, rp->maxlen);
+		return (NULL);
+	}
+
+	if (dp + 2 + len > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = len;
+	memcpy (dp, val, len);
+	dp += len;
+
+	return (dp);
+}
+
+static uchar *
+bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	uchar bytes[HYMOD_MAX_BYTES], nbytes, *p;
+	char *ep;
+
+	for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
+		ulong lval;
+
+		lval = simple_strtol ((char *)p, &ep, 10);
+		if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
+		    lval >= 256) {
+			printf ("%s rec (%s) byte array has invalid uint\n",
+				rp->name, val);
+			return (NULL);
+		}
+		if (nbytes >= HYMOD_MAX_BYTES) {
+			printf ("%s rec (%s) byte array too long\n",
+				rp->name, val);
+			return (NULL);
+		}
+		bytes[nbytes++] = lval;
+
+		if (*ep != '\0')
+			ep++;
+	}
+
+	if (dp + 2 + nbytes > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = nbytes;
+	memcpy (dp, bytes, nbytes);
+	dp += nbytes;
+
+	return (dp);
+}
+
+static eerec_map_t eerec_map[] = {
+	/* name      type                 handler         len max             */
+	{ "serno",   HYMOD_EEREC_SERNO,   uint_handler,   4,  0               },
+	{ "date",    HYMOD_EEREC_DATE,    date_handler,   4,  0               },
+	{ "batch",   HYMOD_EEREC_BATCH,   string_handler, 0,  HYMOD_MAX_BATCH },
+	{ "type",    HYMOD_EEREC_TYPE,    uint_handler,   1,  0               },
+	{ "rev",     HYMOD_EEREC_REV,     uint_handler,   1,  0               },
+	{ "sdram",   HYMOD_EEREC_SDRAM,   bytes_handler,  0,  HYMOD_MAX_SDRAM },
+	{ "flash",   HYMOD_EEREC_FLASH,   bytes_handler,  0,  HYMOD_MAX_FLASH },
+	{ "zbt",     HYMOD_EEREC_ZBT,     bytes_handler,  0,  HYMOD_MAX_ZBT   },
+	{ "xlxtyp",  HYMOD_EEREC_XLXTYP,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "xlxspd",  HYMOD_EEREC_XLXSPD,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "xlxtmp",  HYMOD_EEREC_XLXTMP,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "xlxgrd",  HYMOD_EEREC_XLXGRD,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "cputyp",  HYMOD_EEREC_CPUTYP,  uint_handler,   1,  0               },
+	{ "cpuspd",  HYMOD_EEREC_CPUSPD,  uint_handler,   1,  0               },
+	{ "cpmspd",  HYMOD_EEREC_CPMSPD,  uint_handler,   1,  0               },
+	{ "busspd",  HYMOD_EEREC_BUSSPD,  uint_handler,   1,  0               },
+	{ "hstype",  HYMOD_EEREC_HSTYPE,  uint_handler,   1,  0               },
+	{ "hschin",  HYMOD_EEREC_HSCHIN,  uint_handler,   1,  0               },
+	{ "hschout", HYMOD_EEREC_HSCHOUT, uint_handler,   1,  0               },
+};
+
+static int neerecs = sizeof eerec_map / sizeof eerec_map[0];
+
+static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp;
+
+static int
+eerec_callback (uchar *name, uchar *val)
+{
+	eerec_map_t *rp;
+
+	for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
+		if (strcmp ((char *)name, rp->name) == 0)
+			break;
+
+	if (rp >= &eerec_map[neerecs])
+		return (0);
+
+	if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL)
+		return (0);
+
+	return (1);
+}
+
+static int
+hymod_eeprom_fetch(int which, char *filename, ulong addr)
+{
+	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
+		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
+	hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0];
+	ulong crc;
+
+	memset (hp, 0, sizeof *hp);
+	hp->id = HYMOD_EEPROM_ID;
+	hp->ver = HYMOD_EEPROM_VER;
+
+	dp = sdp = (uchar *)(hp + 1);
+	edp = dp + HYMOD_EEPROM_MAXLEN;
+
+	if (fetch_and_parse (filename, addr, eerec_callback) == 0)
+		return (0);
+
+	hp->len = dp - sdp;
+
+	crc = crc32 (0, data, dp - data);
+	memcpy (dp, &crc, sizeof (ulong));
+	dp += sizeof (ulong);
+
+	eeprom_write (dev_addr, 0, data, dp - data);
+
+	return (1);
+}
+
+static char *type_vals[] = {
+	"NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY"
+};
+
+static char *xlxtyp_vals[] = {
+	"NONE", "XCV300E", "XCV400E", "XCV600E"
+};
+
+static char *xlxspd_vals[] = {
+	"NONE", "6", "7", "8"
+};
+
+static char *xlxtmp_vals[] = {
+	"NONE", "COM", "IND"
+};
+
+static char *xlxgrd_vals[] = {
+	"NONE", "NORMAL", "ENGSAMP"
+};
+
+static char *cputyp_vals[] = {
+	"NONE", "MPC8260"
+};
+
+static char *clk_vals[] = {
+	"NONE", "33", "66", "100", "133", "166", "200"
+};
+
+static char *hstype_vals[] = {
+	"NONE", "AMCC-S2064A"
+};
+
+static void
+print_mem (char *l, char *s, uchar n, uchar a[])
+{
+	if (n > 0) {
+		if (n == 1)
+			printf ("%s%dMB %s", s, 1 << (a[0] - 20), l);
+		else {
+			ulong t = 0;
+			int i;
+
+			for (i = 0; i < n; i++)
+				t += 1 << (a[i] - 20);
+
+			printf ("%s%luMB %s (%d banks:", s, t, l, n);
+
+			for (i = 0; i < n; i++)
+				printf ("%dMB%s",
+					1 << (a[i] - 20),
+					(i == n - 1) ? ")" : ",");
+		}
+	}
+	else
+		printf ("%sNO %s", s, l);
+}
+
+void
+hymod_eeprom_print (hymod_eeprom_t *ep)
+{
+	int i;
+
+	printf ("         Hymod %s board, rev %03d\n",
+		type_vals[ep->bdtype], ep->bdrev);
+
+	printf ("         serial #: %010lu, date %04d-%02d-%02d",
+		ep->serno, ep->date.year, ep->date.month, ep->date.day);
+	if (ep->batchlen > 0)
+		printf (", batch \"%.*s\"", ep->batchlen, ep->batch);
+	puts ("\n");
+
+	switch (ep->bdtype) {
+
+	case HYMOD_BDTYPE_IO:
+	case HYMOD_BDTYPE_CLP:
+	case HYMOD_BDTYPE_DSP:
+		printf ("         Motorola %s CPU, speeds: %s/%s/%s",
+		    cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd],
+		    clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]);
+
+		print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz);
+
+		print_mem ("FLASH", ", ", ep->nflash, ep->flashsz);
+
+		puts ("\n");
+
+		print_mem ("ZBT", "         ", ep->nzbt, ep->zbtsz);
+
+		if (ep->nxlx > 0) {
+			hymod_xlx_t *xp;
+
+			if (ep->nxlx == 1) {
+				xp = &ep->xlx[0];
+				printf (", Xilinx %s FPGA (%s/%s/%s)",
+					xlxtyp_vals[xp->type],
+					xlxspd_vals[xp->speed],
+					xlxtmp_vals[xp->temp],
+					xlxgrd_vals[xp->grade]);
+			}
+			else {
+				printf (", %d Xilinx FPGAs (", ep->nxlx);
+				for (i = 0; i < ep->nxlx; i++) {
+					xp = &ep->xlx[i];
+					printf ("%s[%s/%s/%s]%s",
+					    xlxtyp_vals[xp->type],
+					    xlxspd_vals[xp->speed],
+					    xlxtmp_vals[xp->temp],
+					    xlxgrd_vals[xp->grade],
+					    (i == ep->nxlx - 1) ? ")" : ", ");
+				}
+			}
+		}
+		else
+			puts(", NO FPGAs");
+
+		puts ("\n");
+
+		if (ep->hss.type > 0)
+			printf ("         High Speed Serial: "
+				"%s, %d input%s, %d output%s\n",
+				hstype_vals[ep->hss.type],
+				ep->hss.nchin,
+				(ep->hss.nchin == 1 ? "" : "s"),
+				ep->hss.nchout,
+				(ep->hss.nchout == 1 ? "" : "s"));
+		break;
+
+	case HYMOD_BDTYPE_INPUT:
+	case HYMOD_BDTYPE_ALTINPUT:
+	case HYMOD_BDTYPE_DISPLAY:
+		break;
+
+	default:
+		/* crap! */
+		printf ("         UNKNOWN BOARD TYPE: %d\n", ep->bdtype);
+		break;
+	}
+}
+
+int
+hymod_eeprom_read (int which, hymod_eeprom_t *ep)
+{
+	char *label = which ? "mezzanine" : "main";
+	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
+		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
+	char filename[50], prompt[50], *dir;
+	int serno, count = 0, rc;
+
+	rc = eeprom_probe (dev_addr, 0);
+
+	if (rc > 0) {
+		printf ("*** probe for eeprom failed with code %d\n", rc);
+		return (0);
+	}
+
+	if (rc < 0)
+		return (rc);
+
+	sprintf (prompt, "Enter %s board serial number: ", label);
+
+	if ((dir = getenv ("bddb_cfgdir")) == NULL)
+		dir = def_bddb_cfgdir;
+
+	for (;;) {
+		int rc;
+
+		if (hymod_eeprom_load (which, ep))
+			return (1);
+
+		printf ("*** %s board EEPROM contents are %sinvalid\n",
+			label, count == 0 ? "" : "STILL ");
+
+		puts ("*** will fetch from server (Ctrl-C to abort)\n");
+
+		serno = hymod_get_serno (prompt);
+
+		if (serno < 0) {
+			if (serno == -1)
+				puts ("\n*** interrupted!");
+			else
+				puts ("\n*** timeout!");
+			puts (" - ignoring eeprom contents\n");
+			return (0);
+		}
+
+		sprintf (filename, "%s/%010d.cfg", dir, serno);
+
+		printf ("*** fetching %s board EEPROM contents from server\n",
+			label);
+
+		rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR);
+
+		if (rc == 0) {
+			puts ("*** fetch failed - ignoring eeprom contents\n");
+			return (0);
+		}
+
+		count++;
+	}
+}
diff --git a/u-boot/board/hymod/env.c b/u-boot/board/hymod/env.c
new file mode 100644
index 0000000..c0e2cd5
--- /dev/null
+++ b/u-boot/board/hymod/env.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2003
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* imports from fetch.c */
+extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
+
+/* this is relative to the root of the server's tftp directory */
+static char *def_global_env_path = "/hymod/global_env";
+
+static int
+env_callback (uchar *name, uchar *value)
+{
+	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
+	char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver;
+	int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
+
+	nn = (char *)name;
+
+	if (*nn == '-') {
+		override = 0;
+		nn++;
+	}
+
+	while (*nn == ' ' || *nn == '\t')
+		nn++;
+
+	if ((nnl = strlen (nn)) == 0) {
+		printf ("Empty name in global env file\n");
+		return (0);
+	}
+
+	if ((c = nn[nnl - 1]) == '+' || c == '-') {
+		if (c == '+')
+			append = 1;
+		else
+			remove = 1;
+		nn[--nnl] = '\0';
+	}
+
+	while (nnl > 0 && ((c = nn[nnl - 1]) == ' ' || c == '\t'))
+		nn[--nnl] = '\0';
+	if (nnl == 0) {
+		printf ("Empty name in global env file\n");
+		return (0);
+	}
+
+	p = (char *)value;
+	q = nv;
+
+	while ((c = *p) == ' ' || c == '\t')
+		p++;
+
+	nvl = strlen (p);
+	while (nvl > 0 && ((c = p[nvl - 1]) == ' ' || c == '\t'))
+		p[--nvl] = '\0';
+
+	while ((*q = *p++) != '\0') {
+		if (*q == '%') {
+			switch (*p++) {
+
+			case '\0':	/* whoops - back up */
+				p--;
+				break;
+
+			case '%':	/* a single percent character */
+				q++;
+				break;
+
+			case 's':	/* main board serial number as string */
+				q += sprintf (q, "%010lu",
+					cp->main.eeprom.serno);
+				break;
+
+			case 'S':	/* main board serial number as number */
+				q += sprintf (q, "%lu", cp->main.eeprom.serno);
+				break;
+
+			default:	/* ignore any others */
+				break;
+			}
+		}
+		else
+			q++;
+	}
+
+	if ((nvl = q - nv) == 0) {
+		setenv (nn, NULL);
+		return (1);
+	}
+
+	if ((curver = getenv ("global_env_version")) == NULL)
+		curver = "unknown";
+
+	if ((newver = getenv ("new_genv_version")) == NULL || \
+	    strcmp (curver, newver) == 0) {
+		if (strcmp (nn, "version") == 0)
+			setenv ("new_genv_version", nv);
+		return (1);
+	}
+
+	if ((p = getenv (nn)) != NULL) {
+
+		strcpy (ov, p);
+		ovl = strlen (ov);
+
+		if (append) {
+
+			if (strstr (ov, nv) == NULL) {
+
+				printf ("Appending '%s' to env var '%s'\n",
+					nv, nn);
+
+				while (nvl >= 0) {
+					nv[ovl + 1 + nvl] = nv[nvl];
+					nvl--;
+				}
+
+				nv[ovl] = ' ';
+
+				while (--ovl >= 0)
+					nv[ovl] = ov[ovl];
+
+				setenv (nn, nv);
+			}
+
+			return (1);
+		}
+
+		if (remove) {
+
+			if (strstr (ov, nv) != NULL) {
+
+				printf ("Removing '%s' from env var '%s'\n",
+					nv, nn);
+
+				while ((p = strstr (ov, nv)) != NULL) {
+					q = p + nvl;
+					if (*q == ' ')
+						q++;
+					strcpy(p, q);
+				}
+
+				setenv (nn, ov);
+			}
+
+			return (1);
+		}
+
+		if (!override || strcmp (ov, nv) == 0)
+			return (1);
+
+		printf ("Re-setting env cmd '%s' from '%s' to '%s'\n",
+			nn, ov, nv);
+	}
+	else
+		printf ("Setting env cmd '%s' to '%s'\n", nn, nv);
+
+	setenv (nn, nv);
+	return (1);
+}
+
+void
+hymod_check_env (void)
+{
+	char *p, *path, *curver, *newver;
+	int firsttime = 0, needsave = 0;
+
+	if (getenv ("global_env_loaded") == NULL) {
+		puts ("*** global environment has never been loaded\n");
+		puts ("*** fetching from server");
+		firsttime = 1;
+	}
+	else if ((p = getenv ("always_check_env")) != NULL &&
+	    strcmp (p, "yes") == 0)
+		puts ("*** checking for updated global environment");
+	else
+		return;
+
+	puts (" (Control-C to Abort)\n");
+
+	if ((path = getenv ("global_env_path")) == NULL || *path == '\0')
+		path = def_global_env_path;
+
+	if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) {
+		puts ("*** Fetch of global environment failed!\n");
+		return;
+	}
+
+	if ((newver = getenv ("new_genv_version")) == NULL) {
+		puts ("*** Version number not set - contents ignored!\n");
+		return;
+	}
+
+	if ((curver = getenv ("global_env_version")) == NULL || \
+	    strcmp (curver, newver) != 0) {
+		setenv ("global_env_version", newver);
+		needsave = 1;
+	}
+	else
+		printf ("*** Global environment up-to-date (ver %s)\n", curver);
+
+	setenv ("new_genv_version", NULL);
+
+	if (firsttime) {
+		setenv ("global_env_loaded", "yes");
+		needsave = 1;
+	}
+
+	if (needsave)
+		puts ("\n*** Remember to run the 'saveenv' "
+			"command to save the changes\n\n");
+}
diff --git a/u-boot/board/hymod/fetch.c b/u-boot/board/hymod/fetch.c
new file mode 100644
index 0000000..e121d55
--- /dev/null
+++ b/u-boot/board/hymod/fetch.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+
+/* imports from input.c */
+extern int hymod_get_ethaddr (void);
+
+int
+fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *))
+{
+	char *ethaddr;
+	uchar *fp, *efp;
+	int rc, count = 0;
+
+	while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') {
+
+		printf ("*** Ethernet address is%s not set\n",
+			count == 0 ? "" : " STILL");
+
+		if ((rc = hymod_get_ethaddr ()) < 0) {
+			if (rc == -1)
+				puts ("\n*** interrupted!");
+			else
+				puts ("\n*** timeout!");
+			printf (" - fetch of '%s' aborted\n", fn);
+			return (0);
+		}
+
+		count++;
+	}
+
+	copy_filename (BootFile, fn, sizeof (BootFile));
+	load_addr = addr;
+	NetBootFileXferSize = 0;
+
+	if (NetLoop (TFTP) == 0) {
+		printf ("tftp transfer of file '%s' failed\n", fn);
+		return (0);
+	}
+
+	if (NetBootFileXferSize == 0) {
+		printf ("can't determine size of file '%s'\n", fn);
+		return (0);
+	}
+
+	fp = (uchar *)load_addr;
+	efp = fp + NetBootFileXferSize;
+
+	do {
+		uchar *name, *value;
+
+		if (*fp == '#' || *fp == '\n') {
+			/* skip this line */
+			while (fp < efp && *fp++ != '\n')
+				;
+			continue;
+		}
+
+		name = fp;
+
+		while (fp < efp && *fp != '=' && *fp != '\n')
+			fp++;
+		if (fp >= efp)
+			break;
+		if (*fp == '\n') {
+			fp++;
+			continue;
+		}
+		*fp++ = '\0';
+
+		value = fp;
+
+		while (fp < efp && *fp != '\n')
+			fp++;
+		if (fp[-1] == '\r')
+			fp[-1] = '\0';
+		*fp++ = '\0';	/* ok if we go off the end here */
+
+		if ((*cback)(name, value) == 0)
+			return (0);
+
+	} while (fp < efp);
+
+	return (1);
+}
diff --git a/u-boot/board/hymod/flash.c b/u-boot/board/hymod/flash.c
new file mode 100644
index 0000000..e2cf38c
--- /dev/null
+++ b/u-boot/board/hymod/flash.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <board/hymod/flash.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * probe for flash bank at address "base" and store info about it
+ * in the flash_info entry "fip". Fatal error if nothing there.
+ */
+static void
+bank_probe (flash_info_t *fip, volatile bank_addr_t base)
+{
+	volatile bank_addr_t addr;
+	bank_word_t word;
+	int i;
+
+	/* reset the flash */
+	*base = BANK_CMD_RST;
+
+	/* put flash into read id mode */
+	*base = BANK_CMD_RD_ID;
+
+	/* check the manufacturer id - must be intel */
+	word = *BANK_REG_MAN_CODE (base);
+	if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff))
+		panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx",
+			(unsigned long)word, (unsigned long)base);
+
+	/* check the device id */
+	word = *BANK_REG_DEV_CODE (base);
+	switch (word) {
+
+	case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5;
+		fip->sector_count = 32;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5;
+		fip->sector_count = 64;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A;
+		fip->sector_count = 32;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A;
+		fip->sector_count = 64;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A;
+		fip->sector_count = 128;
+		break;
+
+	default:
+		panic ("\nbad device code (0x%08lx) at addr 0x%08lx",
+			(unsigned long)word, (unsigned long)base);
+	}
+
+	if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT)
+		panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
+			fip->sector_count, (unsigned long)base);
+
+	addr = base;
+	for (i = 0; i < fip->sector_count; i++) {
+		fip->start[i] = (unsigned long)addr;
+		fip->protect[i] = 0;
+		addr = BANK_ADDR_NEXT_BLK (addr);
+	}
+
+	fip->size = (bank_size_t)addr - (bank_size_t)base;
+
+	/* reset the flash */
+	*base = BANK_CMD_RST;
+}
+
+static void
+bank_reset (flash_info_t *info, int sect)
+{
+	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
+
+#ifdef FLASH_DEBUG
+	printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr);
+#endif
+
+	*addr = BANK_CMD_RST;
+}
+
+static void
+bank_erase_init (flash_info_t *info, int sect)
+{
+	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf ("erasing sector %d, addr = 0x%08lx\n",
+		sect, (unsigned long)addr);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts ();
+
+#ifdef FLASH_DEBUG
+	printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr);
+#endif
+	*addr = BANK_CMD_ERASE1;
+	*addr = BANK_CMD_ERASE2;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+}
+
+static int
+bank_erase_poll (flash_info_t *info, int sect)
+{
+	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
+	bank_word_t stat = *addr;
+
+#ifdef FLASH_DEBUG
+	printf ("checking status at addr 0x%08lx [0x%08lx]\n",
+		(unsigned long)addr, (unsigned long)stat);
+#endif
+
+	if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) {
+		if ((stat & BANK_STAT_ERR) != 0) {
+			printf ("failed on sector %d [0x%08lx] at "
+				"address 0x%08lx\n", sect,
+				(unsigned long)stat, (unsigned long)addr);
+			*addr = BANK_CMD_CLR_STAT;
+			return (-1);
+		}
+		else
+			return (1);
+	}
+	else
+		return (0);
+}
+
+static int
+bank_write_word (volatile bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf ("flash program failed [0x%08lx] at address 0x%08lx\n",
+			(unsigned long)stat, (unsigned long)addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE);
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
+	(void)flash_protect (FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#if defined(CONFIG_SYS_FLASH_ENV_ADDR)
+	(void)flash_protect (FLAG_PROTECT_SET,
+		      CONFIG_SYS_FLASH_ENV_ADDR,
+#if defined(CONFIG_SYS_FLASH_ENV_BUF)
+		      CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1,
+#else
+		      CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1,
+#endif
+		      &flash_info[0]);
+#endif
+
+	return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J5:	printf ("28F320J5 (32 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F640J5:	printf ("28F640J5 (64 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F320J3A:	printf ("28F320J3A (32 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F320J3A (128 Mbit, 2 x 16bit)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+	int rcode = 0;
+
+#ifdef FLASH_DEBUG
+	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info (info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sector%s will not be erased\n",
+			prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init (info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer (start);
+
+			do {
+				now = get_timer (start);
+
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					rcode = 1;
+					break;
+				}
+
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) { /* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll (info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					rcode = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset (info, sect);
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Program failed
+ */
+static int
+write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(ulong *)dest & data) != data)
+		return (2);
+
+	return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Program failed
+ */
+
+int
+write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/hymod/flash.h b/u-boot/board/hymod/flash.h
new file mode 100644
index 0000000..ee047fe
--- /dev/null
+++ b/u-boot/board/hymod/flash.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/* Commands */
+#define ISF_CMD_RST		0xFF		/* reset flash */
+#define ISF_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define ISF_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define ISF_CMD_RD_STAT		0x70		/* read the status register */
+#define ISF_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define ISF_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define ISF_CMD_PROG		0x40		/* program word command */
+#define ISF_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define ISF_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define ISF_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define ISF_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define ISF_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define ISF_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define ISF_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define ISF_STAT_DPS		0x02		/* Device Protect Status */
+#define ISF_STAT_VPPS		0x08		/* VPP Status */
+#define ISF_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define ISF_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define ISF_STAT_ESS		0x40		/* Erase Suspend Status */
+#define ISF_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define ISF_STAT_ERR		(ISF_STAT_VPPS | ISF_STAT_DPS | \
+				    ISF_STAT_ECLBS | ISF_STAT_PSLBS)
+
+/* register addresses, valid only following an ISF_CMD_RD_ID command */
+#define ISF_REG_MAN_CODE	0x00		/* manufacturer code */
+#define ISF_REG_DEV_CODE	0x01		/* device code */
+#define ISF_REG_BLK_LCK		0x02		/* block lock configuration */
+#define ISF_REG_MST_LCK		0x03		/* master lock configuration */
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * this code requires that the flash on any Hymod board appear as a bank
+ * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase
+ * sectors (or blocks), running in x16 bit mode and connected side-by-side
+ * to make a 32-bit wide bus.
+ */
+
+typedef unsigned long bank_word_t;
+typedef bank_word_t bank_blk_t[64 * 1024];
+
+#define BANK_FILL_WORD(b)	(((bank_word_t)(b) << 16) | (bank_word_t)(b))
+
+#ifdef EXAMPLE
+
+/* theoretically the following examples should also work */
+
+/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */
+typedef unsigned char bank_word_t;
+typedef bank_word_t bank_blk_t[128 * 1024];
+#define BANK_FILL_WORD(b)	((bank_word_t)(b))
+
+/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */
+typedef unsigned long long bank_word_t;
+typedef bank_word_t bank_blk_t[32 * 1024];
+#define BANK_FILL_WORD(b)	( \
+				    ((bank_word_t)(b) << 48) \
+				    ((bank_word_t)(b) << 32) \
+				    ((bank_word_t)(b) << 16) \
+				    ((bank_word_t)(b) <<  0) \
+				)
+
+#endif /* EXAMPLE */
+
+/* the sizes of these two types should probably be the same */
+typedef bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(sizeof (bank_word_t) - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	(((bank_size_t)(s) + sizeof (bank_word_t) - 1) \
+				    & ~(sizeof (bank_word_t) - 1))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(sizeof (bank_blk_t) - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	(((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \
+				    & ~(sizeof (bank_blk_t) - 1))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	((bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o)))
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    sizeof (bank_word_t))
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    sizeof (bank_blk_t))
+
+/* get bank address of register r given a bank base address a and block num b */
+#define BANK_ADDR_REG(a, b, r)	BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \
+				    (bank_size_t)(b) * sizeof (bank_blk_t)), \
+					(bank_size_t)(r) * sizeof (bank_word_t))
+
+/* make a bank word value for each StrataFlash value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(ISF_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(ISF_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(ISF_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(ISF_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(ISF_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(ISF_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(ISF_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(ISF_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(ISF_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(ISF_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(ISF_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(ISF_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(ISF_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(ISF_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(ISF_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(ISF_STAT_ERR)
+
+/* make a bank register address for each StrataFlash register address */
+
+#define BANK_REG_MAN_CODE(a)	BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE)
+#define BANK_REG_DEV_CODE(a)	BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE)
+#define BANK_REG_BLK_LCK(a, b)	BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK)
+#define BANK_REG_MST_LCK(a)	BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK)
diff --git a/u-boot/board/hymod/global_env b/u-boot/board/hymod/global_env
new file mode 100644
index 0000000..f61d080
--- /dev/null
+++ b/u-boot/board/hymod/global_env
@@ -0,0 +1,161 @@
+# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE
+
+# (C) Copyright 2001
+# Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# global_env
+#
+# file used by Hymod boards to initialise the u-boot non-volatile
+# environment when u-boot is first run (it determines this by the
+# absence of the environment variable "global_env_loaded")
+#
+# format of this file is:
+#
+#	1. blank lines and lines beginning with '#' are ignored
+#	2. all other lines must have the form <name>=<value>
+#	3. if a percent appears anywhere, it is replaced like so:
+#
+#		%s	serial number of the main board (10 digit zero filled)
+#		%S	serial number of the main board (plain number)
+#		%%	a percentage character
+#		... otherwise the %x is discarded
+#
+# if first character in <name> is a dash ('-'), then an existing env var
+# will not be overwritten (the dash is removed). i.e. it is only set if
+# it does not exist
+#
+# if last character in <name> is a plus ('+'), then <value> will be appended
+# to any existing env var (the plus is ignored). Duplicates of <value> are
+# removed.
+#
+# similarly, if the last character in <name> is a minus ('-'), then any
+# occurences of <value> in the current value of <name> will removed (the
+# minus is ignored).
+#
+# leading and trailing whitespace is removed in both <name> and <value>
+# (after processing any initial or final plus/minus in <name>).
+#
+
+# MISCELLANEOUS PARAMETERS
+
+# version must always come first
+version=4
+
+# set the ip address based on the main board serial number
+ipaddr=192.168.1.%S
+serverip=192.168.1.254
+
+# stop auto execute after tftp (not a very good name really)
+autostart=no
+
+# setting this to "yes" forces the global_env file to be loaded and processed
+# if the current version is different to the version in the file
+always_check_env=no
+
+# BOOTING COMMANDS AND PARAMETERS
+
+# command to run when "auto-booting"
+bootcmd=bootm 40080000
+
+# how long the "countdown" to automatically running "bootcmd" is
+bootdelay=2
+
+# how long before it "times out" console input and attempts to run "bootcmd"
+bootretry=5
+
+# arguments passed to the boot program (i.e. linux kernel) via register 6
+# the linux kernel (v2.4) uses the following registers:
+#	r3 - address of board information structure
+#	r4 - address of initial ramdisk image (0 means no initrd)
+#	r5 - size of initial ramdisk image
+#	r6 - address of command line string
+-bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro
+
+# these four are for hymod linux integrated into our Sun network
+bootargs+=serialno=%S
+bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4
+bootargs+=nfsclient
+bootargs+=automount
+
+# start a web server by default
+bootargs+=webserver
+
+# give negotiation time to finish
+bootargs+=netsleep=5
+
+# then our ciscos don't pass packets for 25-30 secs after that, so
+# pinging the server until it responds prevents network connections
+# from failing...
+bootargs+=netping
+
+# these are old bootargs - we don't need them anymore
+bootargs-=preload=unix,i2c-cpm,i2c-dev
+bootargs-=ramdisk_size=32768
+bootargs-=ramdisk_size=24576
+
+# FLASH MANIPULATION COMMANDS
+
+#
+# 16M flash, 64 x 256K sectors, mapped at address 0x40000000
+#
+# Sector(s)	Address		Size	Description
+#
+#  0 -  0	0x40000000	256K	boot code
+#  1 -  1	0x40040000	256K	non volatile environment
+#  2 -  4	0x40080000	768K	linux kernel image
+#  5 -  7	0x40140000	768K	alternate linux kernel image
+#  8 - 47	0x40200000	 10M	linux initial ramdisk image
+# 48 - 63	0x40c00000	  4M	ramdisk image for applications
+#
+
+fetchboot=tftp 100000 /hymod/u-boot.bin
+eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0
+copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0
+cmpboot=cmp.b 100000 40000000 40000
+newboot=run fetchboot eraseboot copyboot cmpboot
+
+fetchlinux=tftp 100000 /hymod/linux.bin
+eraselinux=erase 1:2-4
+copylinux=cp.b 100000 40080000 ${filesize}
+cmplinux=cmp.b 100000 40080000 ${filesize}
+newlinux=run fetchlinux eraselinux copylinux cmplinux
+
+fetchaltlinux=tftp 100000 /hymod/altlinux.bin
+erasealtlinux=erase 1:5-7
+copyaltlinux=cp.b 100000 40140000 ${filesize}
+cmpaltlinux=cmp.b 100000 40140000 ${filesize}
+newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux
+
+fetchroot=tftp 100000 /hymod/root.bin
+eraseroot=erase 1:8-47
+copyroot=cp.b 100000 40200000 ${filesize}
+cmproot=cmp.b 100000 40200000 ${filesize}
+newroot=run fetchroot eraseroot copyroot cmproot
+
+fetchard=tftp 100000 /hymod/apprd.bin
+eraseard=erase 1:48-63
+copyard=cp.b 100000 40c00000 ${filesize}
+cmpard=cmp.b 100000 40c00000 ${filesize}
+newapprd=run fetchard eraseard copyard cmpard
+
+# pass above map to linux mtd driver
+bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod)
diff --git a/u-boot/board/hymod/hymod.c b/u-boot/board/hymod/hymod.c
new file mode 100644
index 0000000..2af3049
--- /dev/null
+++ b/u-boot/board/hymod/hymod.c
@@ -0,0 +1,537 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <mpc8260_irq.h>
+#include <ioports.h>
+#include <i2c.h>
+#include <asm/iopin_8260.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/* imports from eeprom.c */
+extern int hymod_eeprom_read (int, hymod_eeprom_t *);
+extern void hymod_eeprom_print (hymod_eeprom_t *);
+
+/* imports from env.c */
+extern void hymod_check_env (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  1,  1,  0,  0,  0   },	/* PA31: FCC1 MII COL */
+		{   1,  1,  1,  0,  0,  0   },	/* PA30: FCC1 MII CRS */
+		{   1,  1,  1,  1,  0,  0   },	/* PA29: FCC1 MII TX_ER */
+		{   1,  1,  1,  1,  0,  0   },	/* PA28: FCC1 MII TX_EN */
+		{   1,  1,  1,  0,  0,  0   },	/* PA27: FCC1 MII RX_DV */
+		{   1,  1,  1,  0,  0,  0   },	/* PA26: FCC1 MII RX_ER */
+		{   1,  0,  0,  1,  0,  0   },	/* PA25: FCC2 MII MDIO */
+		{   1,  0,  0,  1,  0,  0   },	/* PA24: FCC2 MII MDC */
+		{   1,  0,  0,  1,  0,  0   },	/* PA23: FCC3 MII MDIO */
+		{   1,  0,  0,  1,  0,  0   },	/* PA22: FCC3 MII MDC */
+		{   1,  1,  0,  1,  0,  0   },	/* PA21: FCC1 MII TxD[3] */
+		{   1,  1,  0,  1,  0,  0   },	/* PA20: FCC1 MII TxD[2] */
+		{   1,  1,  0,  1,  0,  0   },	/* PA19: FCC1 MII TxD[1] */
+		{   1,  1,  0,  1,  0,  0   },	/* PA18: FCC1 MII TxD[0] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA17: FCC1 MII RxD[3] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA16: FCC1 MII RxD[2] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA15: FCC1 MII RxD[1] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA14: FCC1 MII RxD[0] */
+		{   1,  0,  0,  1,  0,  0   },	/* PA13: FCC1 MII MDIO */
+		{   1,  0,  0,  1,  0,  0   },	/* PA12: FCC1 MII MDC */
+		{   1,  0,  0,  1,  0,  0   },	/* PA11: SEL_CD */
+		{   1,  0,  0,  0,  0,  0   },	/* PA10: FLASH STS1 */
+		{   1,  0,  0,  0,  0,  0   },	/* PA09: FLASH STS0 */
+		{   1,  0,  0,  0,  0,  0   },	/* PA08: FLASH ~PE */
+		{   1,  0,  0,  0,  0,  0   },	/* PA07: WATCH ~HRESET */
+		{   1,  0,  0,  0,  1,  0   },	/* PA06: VC DONE */
+		{   1,  0,  0,  1,  1,  0   },	/* PA05: VC INIT */
+		{   1,  0,  0,  1,  0,  0   },	/* PA04: VC ~PROG */
+		{   1,  0,  0,  1,  0,  0   },	/* PA03: VM ENABLE */
+		{   1,  0,  0,  0,  1,  0   },	/* PA02: VM DONE */
+		{   1,  0,  0,  1,  1,  0   },	/* PA01: VM INIT */
+		{   1,  0,  0,  1,  0,  0   }	/* PA00: VM ~PROG */
+	},
+
+	/* Port B configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  1,  0,  1,  0,  0   },	/* PB31: FCC2 MII TX_ER */
+		{   1,  1,  0,  0,  0,  0   },	/* PB30: FCC2 MII RX_DV */
+		{   1,  1,  1,  1,  0,  0   },	/* PB29: FCC2 MII TX_EN */
+		{   1,  1,  0,  0,  0,  0   },	/* PB28: FCC2 MII RX_ER */
+		{   1,  1,  0,  0,  0,  0   },	/* PB27: FCC2 MII COL */
+		{   1,  1,  0,  0,  0,  0   },	/* PB26: FCC2 MII CRS */
+		{   1,  1,  0,  1,  0,  0   },	/* PB25: FCC2 MII TxD[3] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB24: FCC2 MII TxD[2] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB23: FCC2 MII TxD[1] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB22: FCC2 MII TxD[0] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB21: FCC2 MII RxD[0] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB20: FCC2 MII RxD[1] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB19: FCC2 MII RxD[2] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB18: FCC2 MII RxD[3] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB17: FCC3 MII RX_DV */
+		{   1,  1,  0,  0,  0,  0   },	/* PB16: FCC3 MII RX_ER */
+		{   1,  1,  0,  1,  0,  0   },	/* PB15: FCC3 MII TX_ER */
+		{   1,  1,  0,  1,  0,  0   },	/* PB14: FCC3 MII TX_EN */
+		{   1,  1,  0,  0,  0,  0   },	/* PB13: FCC3 MII COL */
+		{   1,  1,  0,  0,  0,  0   },	/* PB12: FCC3 MII CRS */
+		{   1,  1,  0,  0,  0,  0   },	/* PB11: FCC3 MII RxD[3] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB10: FCC3 MII RxD[2] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB09: FCC3 MII RxD[1] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB08: FCC3 MII RxD[0] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB07: FCC3 MII TxD[3] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB06: FCC3 MII TxD[2] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB05: FCC3 MII TxD[1] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB04: FCC3 MII TxD[0] */
+		{   0,  0,  0,  0,  0,  0   },	/* PB03: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PB02: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PB01: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   }	/* PB00: pin doesn't exist */
+	},
+
+	/* Port C configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  0,  0,  0,  0,  0   },	/* PC31: MEZ ~IACK */
+		{   0,  0,  0,  0,  0,  0   },	/* PC30: ? */
+		{   1,  1,  0,  0,  0,  0   },	/* PC29: CLK SCCx */
+		{   1,  1,  0,  0,  0,  0   },	/* PC28: CLK4 */
+		{   1,  1,  0,  0,  0,  0   },	/* PC27: CLK SCCF */
+		{   1,  1,  0,  0,  0,  0   },	/* PC26: CLK 32K */
+		{   1,  1,  0,  0,  0,  0   },	/* PC25: BRG4/CLK7 */
+		{   0,  0,  0,  0,  0,  0   },	/* PC24: ? */
+		{   1,  1,  0,  0,  0,  0   },	/* PC23: CLK SCCx */
+		{   1,  1,  0,  0,  0,  0   },	/* PC22: FCC1 MII RX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC21: FCC1 MII TX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC20: CLK SCCF */
+		{   1,  1,  0,  0,  0,  0   },	/* PC19: FCC2 MII RX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC18: FCC2 MII TX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC17: FCC3 MII RX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC16: FCC3 MII TX_CLK */
+		{   1,  0,  0,  0,  0,  0   },	/* PC15: SCC1 UART ~CTS */
+		{   1,  0,  0,  0,  0,  0   },	/* PC14: SCC1 UART ~CD */
+		{   1,  0,  0,  0,  0,  0   },	/* PC13: SCC2 UART ~CTS */
+		{   1,  0,  0,  0,  0,  0   },	/* PC12: SCC2 UART ~CD */
+		{   1,  0,  0,  1,  0,  0   },	/* PC11: SCC1 UART ~DTR */
+		{   1,  0,  0,  1,  0,  0   },	/* PC10: SCC1 UART ~DSR */
+		{   1,  0,  0,  1,  0,  0   },	/* PC09: SCC2 UART ~DTR */
+		{   1,  0,  0,  1,  0,  0   },	/* PC08: SCC2 UART ~DSR */
+		{   1,  0,  0,  0,  0,  0   },	/* PC07: TEMP ~ALERT */
+		{   1,  0,  0,  0,  0,  0   },	/* PC06: FCC3 INT */
+		{   1,  0,  0,  0,  0,  0   },	/* PC05: FCC2 INT */
+		{   1,  0,  0,  0,  0,  0   },	/* PC04: FCC1 INT */
+		{   0,  1,  1,  1,  0,  0   },	/* PC03: SDMA IDMA2 ~DACK */
+		{   0,  1,  1,  0,  0,  0   },	/* PC02: SDMA IDMA2 ~DONE */
+		{   0,  1,  0,  0,  0,  0   },	/* PC01: SDMA IDMA2 ~DREQ */
+		{   1,  1,  0,  1,  0,  0   }	/* PC00: BRG7 */
+	},
+
+	/* Port D configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  1,  0,  0,  0,  0   },	/* PD31: SCC1 UART RxD */
+		{   1,  1,  1,  1,  0,  0   },	/* PD30: SCC1 UART TxD */
+		{   1,  0,  0,  1,  0,  0   },	/* PD29: SCC1 UART ~RTS */
+		{   1,  1,  0,  0,  0,  0   },	/* PD28: SCC2 UART RxD */
+		{   1,  1,  0,  1,  0,  0   },	/* PD27: SCC2 UART TxD */
+		{   1,  0,  0,  1,  0,  0   },	/* PD26: SCC2 UART ~RTS */
+		{   1,  0,  0,  0,  0,  0   },	/* PD25: SCC1 UART ~RI */
+		{   1,  0,  0,  0,  0,  0   },	/* PD24: SCC2 UART ~RI */
+		{   1,  0,  0,  1,  0,  0   },	/* PD23: CLKGEN PD */
+		{   1,  0,  0,  0,  0,  0   },	/* PD22: USER3 */
+		{   1,  0,  0,  0,  0,  0   },	/* PD21: USER2 */
+		{   1,  0,  0,  0,  0,  0   },	/* PD20: USER1 */
+		{   1,  1,  1,  0,  0,  0   },	/* PD19: SPI ~SEL */
+		{   1,  1,  1,  0,  0,  0   },	/* PD18: SPI CLK */
+		{   1,  1,  1,  0,  0,  0   },	/* PD17: SPI MOSI */
+		{   1,  1,  1,  0,  0,  0   },	/* PD16: SPI MISO */
+		{   1,  1,  1,  0,  1,  0   },	/* PD15: I2C SDA */
+		{   1,  1,  1,  0,  1,  0   },	/* PD14: I2C SCL */
+		{   1,  0,  0,  1,  0,  1   },	/* PD13: TEMP ~STDBY */
+		{   1,  0,  0,  1,  0,  1   },	/* PD12: FCC3 ~RESET */
+		{   1,  0,  0,  1,  0,  1   },	/* PD11: FCC2 ~RESET */
+		{   1,  0,  0,  1,  0,  1   },	/* PD10: FCC1 ~RESET */
+		{   1,  0,  0,  0,  0,  0   },	/* PD09: PD9 */
+		{   1,  0,  0,  0,  0,  0   },	/* PD08: PD8 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD07: PD7 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD06: PD6 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD05: PD5 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD04: PD4 */
+		{   0,  0,  0,  0,  0,  0   },	/* PD03: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PD02: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PD01: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   }	/* PD00: pin doesn't exist */
+	}
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * AMI FS6377 Clock Generator configuration table
+ *
+ * the "fs6377_regs[]" table entries correspond to FS6377 registers
+ * 0 - 15 (total of 16 bytes).
+ *
+ * the data is written to the FS6377 via the i2c bus using address in
+ * "fs6377_addr" (address is 7 bits - R/W bit not included).
+ *
+ * The fs6377 has four clock outputs: A, B, C and D.
+ *
+ * Outputs C and D can each provide two different clock outputs C1/D1 or
+ * C2/D2 depending on the state of the SEL_CD input which is connected to
+ * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
+ * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
+ *
+ * PA11 defaults to output low (or 0) in the i/o port config table above.
+ *
+ * Output A provides a 100MHz for the High Speed Serial chips. Output B
+ * provides a 3.6864MHz clock for more accurate asynchronous serial bit
+ * rates. Output C is routed to the mezzanine connector but is currently
+ * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
+ * alt-input and display mezzanine boards for their video chips. The
+ * alt-input board requires a clock of 24.576MHz and this is available on
+ * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
+ * is available on D2 (PA11=SEL_CD=1).
+ *
+ * So the default is a clock suitable for the alt-input board. PA11 is toggled
+ * later in misc_init_r(), if a display board is detected.
+ */
+
+uchar fs6377_addr = 0x5c;
+
+uchar fs6377_regs[16] = {
+	 12,  75,  64,  25, 144, 128,  25, 192,
+	  0,  16, 135, 192, 224,  64,  64, 192
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * special board initialisation, after clocks and timebase have been
+ * set up but before environment and serial are initialised.
+ *
+ * added so that very early initialisations can be done using the i2c
+ * driver (which requires the clocks, to calculate the dividers, and
+ * the timebase, for udelay())
+ */
+
+int
+board_postclk_init (void)
+{
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/*
+	 * Initialise the FS6377 clock chip
+	 *
+	 * the secondary address is the register number from where to
+	 * start the write - I want to write all the registers
+	 *
+	 * don't bother checking return status - we have no console yet
+	 * to print it on, nor any RAM to store it in - it will be obvious
+	 * if this doesn't work
+	 */
+	(void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
+					sizeof (fs6377_regs));
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity: Hardwired to HYMOD
+ */
+
+int
+checkboard (void)
+{
+	puts ("Board: HYMOD\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * miscellaneous (early - while running in flash) initialisations.
+ */
+
+#define _NOT_USED_	0xFFFFFFFF
+
+uint upmb_table[] = {
+	/* Read Single Beat (RSS) - offset 0x00 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Read Burst (RBS) - offset 0x08 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Single Beat (WSS) - offset 0x18 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Burst (WSS) - offset 0x20 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Refresh Timer (PTS) - offset 0x30 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Exception Condition (EXS) - offset 0x3c */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+uint upmc_table[] = {
+	/* Read Single Beat (RSS) - offset 0x00 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Read Burst (RBS) - offset 0x08 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Single Beat (WSS) - offset 0x18 */
+	0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
+	0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Burst (WSS) - offset 0x20 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Refresh Timer (PTS) - offset 0x30 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Exception Condition (EXS) - offset 0x3c */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+int
+misc_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	printf ("UPMs:  ");
+
+	upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
+	memctl->memc_mbmr = CONFIG_SYS_MBMR;
+
+	upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
+	memctl->memc_mcmr = CONFIG_SYS_MCMR;
+
+	printf ("configured\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t
+initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+	ulong psdmr = CONFIG_SYS_PSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are conÞgured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	return (CONFIG_SYS_SDRAM_SIZE << 20);
+}
+
+/* ------------------------------------------------------------------------- */
+/* miscellaneous initialisations after relocation into ram (misc_init_r)     */
+/*									     */
+/* loads the data in the main board and mezzanine board eeproms into	     */
+/* the hymod configuration struct stored in the board information area.	     */
+/*									     */
+/* if the contents of either eeprom is invalid, prompts for a serial	     */
+/* number (and an ethernet address if required) then fetches a file	     */
+/* containing information to be stored in the eeprom from the tftp server    */
+/* (the file name is based on the serial number and a built-in path)	     */
+
+int
+last_stage_init (void)
+{
+	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
+	int rc;
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+	/*
+	 * we use the readline () function, but we also want
+	 * command timeout enabled
+	 */
+	init_cmd_timeout ();
+#endif
+
+	memset ((void *) cp, 0, sizeof (*cp));
+
+	/* set up main board config info */
+
+	rc = hymod_eeprom_read (0, &cp->main.eeprom);
+
+	puts ("EEPROM:main...");
+	if (rc < 0)
+		puts ("NOT PRESENT\n");
+	else if (rc == 0)
+		puts ("INVALID\n");
+	else {
+		cp->main.eeprom.valid = 1;
+
+		printf ("OK (ver %u)\n", cp->main.eeprom.ver);
+		hymod_eeprom_print (&cp->main.eeprom);
+
+		/*
+		 * hard-wired assumption here: all hymod main boards will have
+		 * one xilinx fpga, with the interrupt line connected to IRQ2
+		 *
+		 * One day, this might be based on the board type
+		 */
+
+		cp->main.xlx[0].mmap.prog.exists = 1;
+		cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
+		cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
+
+		cp->main.xlx[0].mmap.reg.exists = 1;
+		cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
+		cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
+
+		cp->main.xlx[0].mmap.port.exists = 1;
+		cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
+		cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
+
+		cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
+		cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
+		cp->main.xlx[0].iopins.prog_pin.flag = 1;
+		cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
+		cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
+		cp->main.xlx[0].iopins.init_pin.flag = 1;
+		cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
+		cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
+		cp->main.xlx[0].iopins.done_pin.flag = 1;
+#ifdef FPGA_MAIN_ENABLE_PORT
+		cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
+		cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
+		cp->main.xlx[0].iopins.enable_pin.flag = 1;
+#endif
+
+		cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
+	}
+
+	/* set up mezzanine board config info */
+
+	rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
+
+	puts ("EEPROM:mezz...");
+	if (rc < 0)
+		puts ("NOT PRESENT\n");
+	else if (rc == 0)
+		puts ("INVALID\n");
+	else {
+		cp->main.eeprom.valid = 1;
+
+		printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
+		hymod_eeprom_print (&cp->mezz.eeprom);
+	}
+
+	cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
+
+	hymod_check_env ();
+
+	return (0);
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timebase)
+{
+#ifdef CONFIG_SYS_HYMOD_DBLEDS
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8260_t *iop = &immr->im_ioport;
+	static int shift = 0;
+
+	if ((timestamp % CONFIG_SYS_HZ) == 0) {
+		if (++shift > 3)
+			shift = 0;
+		iop->iop_pdatd =
+				(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
+	}
+#endif /* CONFIG_SYS_HYMOD_DBLEDS */
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
diff --git a/u-boot/board/hymod/hymod.h b/u-boot/board/hymod/hymod.h
new file mode 100644
index 0000000..9d8d662
--- /dev/null
+++ b/u-boot/board/hymod/hymod.h
@@ -0,0 +1,322 @@
+/*
+ * (C) Copyright 2001
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _HYMOD_H_
+#define _HYMOD_H_
+
+#include <linux/config.h>
+#ifdef CONFIG_8260
+#include <asm/iopin_8260.h>
+#endif
+
+/*
+ * hymod configuration data - passed by boot code via the board information
+ * structure (only U-Boot has support for this at the moment)
+ *
+ * there are three types of data passed up from the boot monitor. the first
+ * (type hymod_eeprom_t) is the eeprom data that was read off both the main
+ * (or mother) board and the mezzanine board (if any). this data defines how
+ * many Xilinx fpgas are on each board, and their types (among other things).
+ * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
+ * in the physical address space the various Xilinx fpga access regions have
+ * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
+ * one per Xilinx fpga) defines which io port pins are connected to the various
+ * signals required to program a Xilinx fpga.
+ *
+ * A ram/flash "bank" refers to memory controlled by the same chip select.
+ *
+ * the eeprom contents are defined as in technical note #2 - basically,
+ * a header, zero or more records in no particular order, and a 32 bit crc
+ * a record is 1 or more type bytes, a length byte and "length" bytes.
+ */
+
+#define HYMOD_EEPROM_ID		0xAA	/* eeprom id byte */
+#define HYMOD_EEPROM_VER	1	/* eeprom contents version (0-127) */
+#define HYMOD_EEPROM_SIZE	256	/* number of bytes in the eeprom */
+
+/* eeprom header */
+typedef
+    struct {
+	unsigned char id;		/* eeprom id byte */
+	unsigned char :1;
+	unsigned char ver:7;		/* eeprom contents version number */
+	unsigned long len;		/* total # of bytes btw hdr and crc */
+    }
+hymod_eehdr_t;
+
+/* maximum number of bytes available for eeprom data records */
+#define HYMOD_EEPROM_MAXLEN	(HYMOD_EEPROM_SIZE \
+					- sizeof (hymod_eehdr_t) \
+					- sizeof (unsigned long))
+
+/* eeprom data record */
+typedef
+    union {
+	struct {
+	    unsigned char topbit:1;
+	    unsigned char type:7;
+	    unsigned char len;
+	    unsigned char data[1];	/* variable length */
+	} small;
+	struct {
+	    unsigned short topbit:1;
+	    unsigned short nxtbit:1;
+	    unsigned short type:14;
+	    unsigned short len;
+	    unsigned char data[1];	/* variable length */
+	} medium;
+	struct {
+	    unsigned long topbit:1;
+	    unsigned long nxtbit:1;
+	    unsigned long type:30;
+	    unsigned long len;
+	    unsigned char data[1];	/* variable length */
+	} large;
+    }
+hymod_eerec_t;
+
+#define HYMOD_EEOFF_MAIN	0x00	/* i2c addr offset for main eeprom */
+#define HYMOD_EEOFF_MEZZ	0x04	/* i2c addr offset for mezz eepomr */
+
+/* eeprom record types */
+#define HYMOD_EEREC_SERNO	1	/* serial number */
+#define HYMOD_EEREC_DATE	2	/* date */
+#define HYMOD_EEREC_BATCH	3	/* batch id */
+#define HYMOD_EEREC_TYPE	4	/* board type */
+#define HYMOD_EEREC_REV		5	/* revision number */
+#define HYMOD_EEREC_SDRAM	6	/* sdram sizes */
+#define HYMOD_EEREC_FLASH	7	/* flash sizes */
+#define HYMOD_EEREC_ZBT		8	/* zbt ram sizes */
+#define HYMOD_EEREC_XLXTYP	9	/* Xilinx fpga types */
+#define HYMOD_EEREC_XLXSPD	10	/* Xilinx fpga speeds */
+#define HYMOD_EEREC_XLXTMP	11	/* Xilinx fpga temperatures */
+#define HYMOD_EEREC_XLXGRD	12	/* Xilinx fpga grades */
+#define HYMOD_EEREC_CPUTYP	13	/* Motorola CPU type */
+#define HYMOD_EEREC_CPUSPD	14	/* CPU speed */
+#define HYMOD_EEREC_BUSSPD	15	/* bus speed */
+#define HYMOD_EEREC_CPMSPD	16	/* CPM speed */
+#define HYMOD_EEREC_HSTYPE	17	/* high-speed serial chip type */
+#define HYMOD_EEREC_HSCHIN	18	/* high-speed serial input channels */
+#define HYMOD_EEREC_HSCHOUT	19	/* high-speed serial output channels */
+
+/* some dimensions */
+#define HYMOD_MAX_BATCH		32	/* max no. of bytes in batch id */
+#define HYMOD_MAX_SDRAM		4	/* max sdram "banks" on any board */
+#define HYMOD_MAX_FLASH		4	/* max flash "banks" on any board */
+#define HYMOD_MAX_ZBT		16	/* max ZBT rams on any board */
+#define HYMOD_MAX_XLX		4	/* max Xilinx fpgas on any board */
+
+#define HYMOD_MAX_BYTES		16	/* enough to store any bytes array */
+
+/* board types */
+#define HYMOD_BDTYPE_NONE	0	/* information not present */
+#define HYMOD_BDTYPE_IO		1	/* I/O main board */
+#define HYMOD_BDTYPE_CLP	2	/* CLP main board */
+#define HYMOD_BDTYPE_DSP	3	/* DSP main board */
+#define HYMOD_BDTYPE_INPUT	4	/* video input mezzanine board */
+#define HYMOD_BDTYPE_ALTINPUT	5	/* video input mezzanine board */
+#define HYMOD_BDTYPE_DISPLAY	6	/* video display mezzanine board */
+#define HYMOD_BDTYPE_MAX	7	/* first invalid value */
+
+/* Xilinx fpga types */
+#define HYMOD_XTYP_NONE		0	/* information not present */
+#define HYMOD_XTYP_XCV300E	1	/* Xilinx Virtex 300 */
+#define HYMOD_XTYP_XCV400E	2	/* Xilinx Virtex 400 */
+#define HYMOD_XTYP_XCV600E	3	/* Xilinx Virtex 600 */
+#define HYMOD_XTYP_MAX		4	/* first invalid value */
+
+/* Xilinx fpga speeds */
+#define HYMOD_XSPD_NONE		0	/* information not present */
+#define HYMOD_XSPD_SIX		1
+#define HYMOD_XSPD_SEVEN	2
+#define HYMOD_XSPD_EIGHT	3
+#define HYMOD_XSPD_MAX		4	/* first invalid value */
+
+/* Xilinx fpga temperatures */
+#define HYMOD_XTMP_NONE		0	/* information not present */
+#define HYMOD_XTMP_COM		1
+#define HYMOD_XTMP_IND		2
+#define HYMOD_XTMP_MAX		3	/* first invalid value */
+
+/* Xilinx fpga grades */
+#define HYMOD_XTMP_NONE		0	/* information not present */
+#define HYMOD_XTMP_NORMAL	1
+#define HYMOD_XTMP_ENGSAMP	2
+#define HYMOD_XTMP_MAX		3	/* first invalid value */
+
+/* CPU types */
+#define HYMOD_CPUTYPE_NONE	0	/* information not present */
+#define HYMOD_CPUTYPE_MPC8260	1	/* Motorola MPC8260 embedded powerpc */
+#define HYMOD_CPUTYPE_MAX	2	/* first invalid value */
+
+/* CPU/BUS/CPM clock speeds */
+#define HYMOD_CLKSPD_NONE	0	/* information not present */
+#define HYMOD_CLKSPD_33MHZ	1
+#define HYMOD_CLKSPD_66MHZ	2
+#define HYMOD_CLKSPD_100MHZ	3
+#define HYMOD_CLKSPD_133MHZ	4
+#define HYMOD_CLKSPD_166MHZ	5
+#define HYMOD_CLKSPD_200MHZ	6
+#define HYMOD_CLKSPD_MAX	7	/* first invalid value */
+
+/* high speed serial chip types */
+#define HYMOD_HSSTYPE_NONE	0	/* information not present */
+#define HYMOD_HSSTYPE_AMCC52064	1
+#define HYMOD_HSSTYPE_MAX	2	/* first invalid value */
+
+/* a date (yyyy-mm-dd) */
+typedef
+    struct {
+	unsigned short year;
+	unsigned char month;
+	unsigned char day;
+    }
+hymod_date_t;
+
+/* describes a Xilinx fpga */
+typedef
+    struct {
+	unsigned char type;		/* chip type */
+	unsigned char speed;		/* chip speed rating */
+	unsigned char temp;		/* chip temperature rating */
+	unsigned char grade;		/* chip grade */
+    }
+hymod_xlx_t;
+
+/* describes a Motorola embedded processor */
+typedef
+    struct {
+	unsigned char type;		/* CPU type */
+	unsigned char cpuspd;		/* speed of the PowerPC core */
+	unsigned char busspd;		/* speed of the system and 60x bus */
+	unsigned char cpmspd;		/* speed of the CPM co-processor */
+    }
+hymod_mpc_t;
+
+/* info about high-speed (1Gbit) serial interface */
+typedef
+    struct {
+	unsigned char type;		/* high-speed serial chip type */
+	unsigned char nchin;		/* number of input channels mounted */
+	unsigned char nchout;		/* number of output channels mounted */
+    }
+hymod_hss_t;
+
+/*
+ * this defines the contents of the serial eeprom that exists on every
+ * hymod board, including mezzanine boards (the serial eeprom will be
+ * faked for early development boards that don't have one)
+ */
+
+typedef
+    struct {
+	unsigned char valid:1;		/* contents of this struct is valid */
+	unsigned char ver:7;		/* eeprom contents version */
+	unsigned char bdtype;		/* board type */
+	unsigned char bdrev;		/* board revision */
+	unsigned char batchlen;		/* length of batch string below */
+	unsigned long serno;		/* serial number */
+	hymod_date_t date;		/* manufacture date */
+	unsigned char batch[32];	/* manufacturer specific batch id */
+	unsigned char nsdram;		/* # of ram "banks" */
+	unsigned char nflash;		/* # of flash "banks" */
+	unsigned char nzbt;		/* # of ZBT rams */
+	unsigned char nxlx;		/* # of Xilinx fpgas */
+	unsigned char sdramsz[HYMOD_MAX_SDRAM];	/* log2 of sdram size */
+	unsigned char flashsz[HYMOD_MAX_FLASH];	/* log2 of flash size */
+	unsigned char zbtsz[HYMOD_MAX_ZBT];	/* log2 of ZBT ram size */
+	hymod_xlx_t xlx[HYMOD_MAX_XLX];	/* Xilinx fpga info */
+	hymod_mpc_t mpc;		/* Motorola MPC CPU info */
+	hymod_hss_t hss;		/* high-speed serial info */
+    }
+hymod_eeprom_t;
+
+/*
+ * this defines a region in the processor's physical address space
+ */
+typedef
+    struct {
+	unsigned long exists:1;		/* 1 if the region exists, 0 if not */
+	unsigned long size:31;		/* size in bytes */
+	unsigned long base;		/* base address */
+    }
+xlx_prgn_t;
+
+/*
+ * this defines where the various Xilinx fpga access regions are mapped
+ * into the physical address space of the processor
+ */
+typedef
+    struct {
+	xlx_prgn_t prog;		/* program access region */
+	xlx_prgn_t reg;			/* register access region */
+	xlx_prgn_t port;		/* port access region */
+    }
+xlx_mmap_t;
+
+/*
+ * this defines which 8260 i/o port pins are connected to the various
+ * signals required for programming a Xilinx fpga
+ */
+typedef
+    struct {
+	iopin_t prog_pin;		/* assert for >= 300ns to program */
+	iopin_t init_pin;		/* goes high when fpga is cleared */
+	iopin_t done_pin;		/* goes high when program is done */
+	iopin_t enable_pin;		/* some fpgas need enabling */
+    }
+xlx_iopins_t;
+
+/* all info about one Xilinx chip */
+typedef
+    struct {
+	xlx_mmap_t mmap;
+	xlx_iopins_t iopins;
+	unsigned long irq:8;		/* h/w intr req number for this fpga */
+    }
+xlx_info_t;
+
+/* all info about one hymod board */
+typedef
+    struct {
+	hymod_eeprom_t eeprom;
+	xlx_info_t xlx[HYMOD_MAX_XLX];
+    }
+hymod_board_t;
+
+/*
+ * this defines the configuration information of a hymod board-set
+ * (main board + possible mezzanine board). In future, there may be
+ * more than one mezzanine board (stackable?) - if so, add a "mezz2"
+ * field, and so on... or make mezz an array?
+ */
+typedef
+    struct {
+	unsigned long ver:8;		/* version control */
+	hymod_board_t main;		/* main board info */
+	hymod_board_t mezz;		/* mezzanine board info */
+	unsigned long crc;		/* ensures kernel and boot prom agree */
+    }
+hymod_conf_t;
+
+#endif /* _HYMOD_H_ */
diff --git a/u-boot/board/hymod/input.c b/u-boot/board/hymod/input.c
new file mode 100644
index 0000000..998132d
--- /dev/null
+++ b/u-boot/board/hymod/input.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2003
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* imports from common/main.c */
+extern char console_buffer[CONFIG_SYS_CBSIZE];
+
+int
+hymod_get_serno (const char *prompt)
+{
+	for (;;) {
+		int n, serno;
+		char *p;
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+		reset_cmd_timeout ();
+#endif
+
+		n = readline (prompt);
+
+		if (n < 0)
+			return (n);
+
+		if (n == 0)
+			continue;
+
+		serno = (int) simple_strtol (console_buffer, &p, 10);
+
+		if (p > console_buffer && *p == '\0' && serno > 0)
+			return (serno);
+
+		printf ("Invalid number (%s) - please re-enter\n",
+			console_buffer);
+	}
+}
+
+int
+hymod_get_ethaddr (void)
+{
+	for (;;) {
+		int n;
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+		reset_cmd_timeout ();
+#endif
+
+		n = readline ("Enter board ethernet address: ");
+
+		if (n < 0)
+			return (n);
+
+		if (n == 0)
+			continue;
+
+		if (n == 17) {
+			int i;
+			char *p, *q;
+			uchar ea[6];
+
+			/* see if it looks like an ethernet address */
+
+			p = console_buffer;
+
+			for (i = 0; i < 6; i++) {
+				char term = (i == 5 ? '\0' : ':');
+
+				ea[i] = simple_strtol (p, &q, 16);
+
+				if ((q - p) != 2 || *q++ != term)
+					break;
+
+				p = q;
+			}
+
+			if (i == 6) {
+				/* it looks ok - set it */
+				printf ("Setting ethernet addr to %s\n",
+					console_buffer);
+
+				setenv ("ethaddr", console_buffer);
+
+				puts ("Remember to do a 'saveenv' to "
+					"make it permanent\n");
+
+				return (0);
+			}
+		}
+
+		printf ("Invalid ethernet addr (%s) - please re-enter\n",
+			console_buffer);
+	}
+}
diff --git a/u-boot/board/hymod/u-boot.lds b/u-boot/board/hymod/u-boot.lds
new file mode 100644
index 0000000..0897715
--- /dev/null
+++ b/u-boot/board/hymod/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8260/start.o	(.text)
+/*
+    common/dlmalloc.o	(.text)
+    arch/powerpc/lib/ppcstring.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = env_offset;
+*/
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/env_embedded.o (.ppcenv)
+  }
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/hymod/u-boot.lds.debug b/u-boot/board/hymod/u-boot.lds.debug
new file mode 100644
index 0000000..c218905
--- /dev/null
+++ b/u-boot/board/hymod/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ibf-dsp561/Makefile b/u-boot/board/ibf-dsp561/Makefile
new file mode 100644
index 0000000..0d17676
--- /dev/null
+++ b/u-boot/board/ibf-dsp561/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ibf-dsp561/config.mk b/u-boot/board/ibf-dsp561/config.mk
new file mode 100644
index 0000000..80b527c
--- /dev/null
+++ b/u-boot/board/ibf-dsp561/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.5
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/ibf-dsp561/ibf-dsp561.c b/u-boot/board/ibf-dsp561/ibf-dsp561.c
new file mode 100644
index 0000000..d2ac7a5
--- /dev/null
+++ b/u-boot/board/ibf-dsp561/ibf-dsp561.c
@@ -0,0 +1,26 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 I-SYST.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: I-SYST IBF-DSP561 Micromodule\n");
+	printf("       Support: http://www.i-syst.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AX88180
+int board_eth_init(bd_t *bis)
+{
+	return ax88180_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/icecube/Makefile b/u-boot/board/icecube/Makefile
new file mode 100644
index 0000000..d45db9f
--- /dev/null
+++ b/u-boot/board/icecube/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/icecube/flash.c b/u-boot/board/icecube/flash.c
new file mode 100644
index 0000000..7a433b3
--- /dev/null
+++ b/u-boot/board/icecube/flash.c
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_FLASH_CFI_DRIVER
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(ulong);
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		size += flash_info[i].size;
+		flashbase += 0x800000;
+	}
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+
+	flash_afterinit(size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size &&
+			info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		fmt = "29LV065 (64 Mbit, uniform sectors)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	FPWV* addr2;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = (ulong)addr + (i * 0x10000);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* test for real flash at bank 1 */
+	addr2 = (FPW *)((ulong)addr | 0x800000);
+	if (addr2 != addr &&
+		((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
+		/* Seems 2 banks are the same space (8Mb chip is installed,
+		 * J24 in default position (CS0)). Disable this (first) bank.
+		 */
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+	}
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/u-boot/board/icecube/icecube.c b/u-boot/board/icecube/icecube.c
new file mode 100644
index 0000000..a9e4448
--- /dev/null
+++ b/u-boot/board/icecube/icecube.c
@@ -0,0 +1,341 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+#include <netdev.h>
+
+#if defined(CONFIG_LITE5200B)
+#include "mt46v32m16.h"
+#else
+# if defined(CONFIG_MPC5200_DDR)
+#  include "mt46v16m16-75.h"
+# else
+#include "mt48lc16m16a2-75.h"
+# endif
+#endif
+
+#ifdef CONFIG_LITE5200B_PM
+/* u-boot part of low-power mode implementation */
+#define SAVED_ADDR (*(void **)0x00000000)
+#define PSC2_4 0x02
+
+void lite5200b_wakeup(void)
+{
+	unsigned char wakeup_pin;
+	void (*linux_wakeup)(void);
+
+	/* check PSC2_4, if it's down "QT" is signaling we have a wakeup
+	 * from low power mode */
+	*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
+	__asm__ volatile ("sync");
+
+	wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
+	if (wakeup_pin & PSC2_4)
+		return;
+
+	/* acknowledge to "QT"
+	 * by holding pin at 1 for 10 uS */
+	*(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
+	__asm__ volatile ("sync");
+	*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
+	__asm__ volatile ("sync");
+	udelay(10);
+
+	/* put ram out of self-refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000;	/* mode_en */
+	__asm__ volatile ("sync");
+	*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000;	/* cke ref_en */
+	__asm__ volatile ("sync");
+	*(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000;	/* !mode_en */
+	__asm__ volatile ("sync");
+	udelay(10); /* wait a bit */
+
+	/* jump back to linux kernel code */
+	linux_wakeup = SAVED_ADDR;
+	printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
+			(unsigned long)linux_wakeup);
+	linux_wakeup();
+}
+#else
+#define lite5200b_wakeup()
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	lite5200b_wakeup();
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+#if defined (CONFIG_LITE5200B)
+	puts ("Board: Freescale Lite5200B\n");
+#else
+	puts ("Board: Motorola MPC5200 (IceCube)\n");
+#endif
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x800000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/icecube/mt46v16m16-75.h b/u-boot/board/icecube/mt46v16m16-75.h
new file mode 100644
index 0000000..eb85740
--- /dev/null
+++ b/u-boot/board/icecube/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/icecube/mt46v32m16.h b/u-boot/board/icecube/mt46v32m16.h
new file mode 100644
index 0000000..519bf6d
--- /dev/null
+++ b/u-boot/board/icecube/mt46v32m16.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/icecube/mt48lc16m16a2-75.h b/u-boot/board/icecube/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/icecube/mt48lc16m16a2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/icu862/Makefile b/u-boot/board/icu862/Makefile
new file mode 100644
index 0000000..b49f26d
--- /dev/null
+++ b/u-boot/board/icu862/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/icu862/flash.c b/u-boot/board/icu862/flash.c
new file mode 100644
index 0000000..2afeff4
--- /dev/null
+++ b/u-boot/board/icu862/flash.c
@@ -0,0 +1,617 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0,
+			size_b0 >> 20);
+	}
+
+	if (FLASH_BASE1_PRELIM != 0x0) {
+		size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+		if (size_b1 > size_b0) {
+			printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)"
+				" > Bank 0 (0x%08lx = %ld MB)\n",
+				size_b1, size_b1 >> 20,
+				size_b0, size_b0 >> 20);
+
+			flash_info[0].flash_id	= FLASH_UNKNOWN;
+			flash_info[1].flash_id	= FLASH_UNKNOWN;
+			flash_info[0].sector_count	= -1;
+			flash_info[1].sector_count	= -1;
+			flash_info[0].size		= 0;
+			flash_info[1].size		= 0;
+			return (0);
+		}
+	} else {
+		size_b1 = 0;
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	/* ICU862 Board has only one Flash Bank */
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+		((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) {
+		/* set sector offsets for uniform sector type	*/
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00040000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	puts ("AMD ");		break;
+	case FLASH_MAN_FUJ:	puts ("FUJITSU ");	break;
+	case FLASH_MAN_BM:	puts ("BRIGHT MICRO ");	break;
+	default:		puts ("Unknown Vendor "); break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	puts ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	puts ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	puts ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	puts ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM033C:	puts ("AM29LV033C (32 Mbit)\n");
+				break;
+	default:		puts ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+
+	puts ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+#if 0
+	ulong base = (ulong)addr;
+#endif
+	uchar value;
+
+	/* Write auto select command: read Manufacturer ID */
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x90909090;
+#endif
+
+	value = addr[0];
+
+	switch (value + (value << 16)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch ((unsigned long)value) {
+	case AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	case AMD_ID_LV033C:
+		info->flash_id += FLASH_AM033C;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;				/* => 16Mb		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+#if 0
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#else
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+#if 1
+		/* We don't know why it happens, but on ICU Board	*
+		 * for AMD29033C flash we need to resend the command of	*
+		 * reading flash protection for upper 8 Mb of flash	*/
+		if ( i == 32 ) {
+			addr[0x0555] = 0xAAAAAAAA;
+			addr[0x02AA] = 0x55555555;
+			addr[0x0555] = 0x90909090;
+		}
+#endif
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+#if 0
+		*addr = 0x00F000F0;	/* reset bank */
+#else
+		*addr = 0xF0F0F0F0;	/* reset bank */
+#endif
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			puts ("- missing\n");
+		} else {
+			puts ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		puts ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		puts ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x80808080;
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+#endif
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+#if 0
+			addr[0] = 0x00300030;
+#else
+			addr[0] = 0x30303030;
+#endif
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+#if 0
+	while ((addr[0] & 0x00800080) != 0x00800080)
+#else
+	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+#endif
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			puts ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#if 0
+	addr[0] = 0x00F000F0;	/* reset bank */
+#else
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+#endif
+
+	puts (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0xA0A0A0A0;
+#endif
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+#if 0
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+#else
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+#endif
+	{
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/icu862/icu862.c b/u-boot/board/icu862/icu862.c
new file mode 100644
index 0000000..b99d256
--- /dev/null
+++ b/u-boot/board/icu862/icu862.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory            (0x40000000)
+ *  CS1 - SDRAM                   (0x00000000}
+ *  CS2 - S/UNI Ultra ATM155
+ *  CS3 - IDT 77106 ATM25
+ *  CS4 - DSP HPI
+ *  CS5 - E1/T1 Interface device
+ *  CS6 - PCMCIA device
+ *  CS7 - PCMCIA device
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: ICU862 Board\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {					/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;					/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/u-boot/board/icu862/pcmcia.c b/u-boot/board/icu862/pcmcia.c
new file mode 100644
index 0000000..a4c0b54
--- /dev/null
+++ b/u-boot/board/icu862/pcmcia.c
@@ -0,0 +1,268 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "ICU862"
+
+static void cfg_port_B (void)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	uint reg;
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/*
+	* Configure Port B for TPS2205 PC-Card Power-Interface Switch
+	*
+	* Switch off all voltages, assert shutdown
+	*/
+	reg  = cp->cp_pbdat;
+	reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC |	/* VAVPP => Hi-Z */
+			TPS2205_VCC3    | TPS2205_VCC5    |	/* VAVCC => Hi-Z */
+			TPS2205_SHDN);				/* enable switch */
+	cp->cp_pbdat = reg;
+
+	cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
+
+	reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
+	cp->cp_pbdir = reg | TPS2205_OUTPUTS;
+
+	debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
+	       cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, pipr, mask;
+	int i;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
+	cfg_port_B ();
+
+	/*
+	* Configure SIUMCR to enable PCMCIA port B
+	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	*/
+	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+	*/
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	pipr = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       pipr,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+	reg  = cp->cp_pbdat;
+	if ((pipr & mask) == mask) {
+		reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC |	/* VAVPP => Hi-Z */
+				TPS2205_VCC3);				/* 3V off	*/
+		reg &= ~(TPS2205_VCC5);				/* 5V on	*/
+		puts (" 5.0V card found: ");
+	} else {
+		reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC |	/* VAVPP => Hi-Z */
+				TPS2205_VCC5);				/* 5V off	*/
+		reg &= ~(TPS2205_VCC3);				/* 3V on	*/
+		puts (" 3.3V card found: ");
+	}
+
+	debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
+	       reg,
+	       (reg & TPS2205_VCC3)    ? "off" : "on",
+	       (reg & TPS2205_VCC5)    ? "off" : "on",
+	       (reg & TPS2205_VPP_PGM) ? "off" : "on",
+	       (reg & TPS2205_VPP_VCC) ? "off" : "on" );
+
+	cp->cp_pbdat = reg;
+
+	/*  Wait 500 ms; use this to check for over-current */
+	for (i=0; i<5000; ++i) {
+		if ((cp->cp_pbdat & TPS2205_OC) == 0) {
+			printf ("   *** Overcurrent - Safety shutdown ***\n");
+			cp->cp_pbdat &= ~(TPS2205_SHDN);
+			return (1);
+		}
+		udelay (100);
+	}
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* Shut down */
+	cp->cp_pbdat &= ~(TPS2205_SHDN);
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("voltage_set: "
+			PCMCIA_BOARD_MSG
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	* Disable PCMCIA buffers (isolate the interface)
+	* and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Configure Port C pins for
+	* 5 Volts Enable and 3 Volts enable,
+	* Turn all power pins to Hi-Z
+	*/
+	debug ("PCMCIA power OFF\n");
+	cfg_port_B ();	/* Enables switch, but all in Hi-Z */
+
+	reg  = cp->cp_pbdat;
+
+	switch(vcc) {
+		case  0:			break;	/* Switch off		*/
+		case 33: reg &= ~TPS2205_VCC3;	break;	/* Switch on 3.3V	*/
+		case 50: reg &= ~TPS2205_VCC5;	break;	/* Switch on 5.0V	*/
+		default:			goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+	       pcmp->pcmc_pipr,
+	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+	cp->cp_pbdat = reg;
+
+#ifdef DEBUG
+{
+	char *s;
+
+	if ((reg & TPS2205_VCC3) == 0) {
+		s = "at 3.3V";
+	} else if ((reg & TPS2205_VCC5) == 0) {
+		s = "at 5.0V";
+	} else {
+		s = "down";
+	}
+	printf ("PCMCIA powered %s\n", s);
+}
+#endif
+
+done:
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/icu862/u-boot.lds b/u-boot/board/icu862/u-boot.lds
new file mode 100644
index 0000000..08dfaee
--- /dev/null
+++ b/u-boot/board/icu862/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/icu862/u-boot.lds.debug b/u-boot/board/icu862/u-boot.lds.debug
new file mode 100644
index 0000000..9c1e3ec
--- /dev/null
+++ b/u-boot/board/icu862/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/idmr/Makefile b/u-boot/board/idmr/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/idmr/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/idmr/config.mk b/u-boot/board/idmr/config.mk
new file mode 100644
index 0000000..95b0f9e
--- /dev/null
+++ b/u-boot/board/idmr/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xff800000
diff --git a/u-boot/board/idmr/flash.c b/u-boot/board/idmr/flash.c
new file mode 100644
index 0000000..57c9948
--- /dev/null
+++ b/u-boot/board/idmr/flash.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE 0x800000
+#define EN29LV640 0x227e227e
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (EN29LV640 & FLASH_TYPEMASK):
+		printf ("EN29LV640 (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:
+	return;
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(EN29LV640 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + 0x10000 * j;
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	printf("Waiting 10 ms...");
+	 udelay (10000);
+
+/*	for (i = 0; i < 10 * 1000 * 1000; ++i)
+		asm(" nop");
+*/
+
+	printf("done\n");
+	if (iflag)
+		enable_interrupts ();
+
+
+	return rc;
+}
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/u-boot/board/idmr/idmr.c b/u-boot/board/idmr/idmr.c
new file mode 100644
index 0000000..6829913
--- /dev/null
+++ b/u-boot/board/idmr/idmr.c
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard (void) {
+	puts ("Board: iDMR\n");
+	return 0;
+};
+
+phys_size_t initdram (int board_type) {
+	int i;
+
+	/*
+	 * After reset, CS0 is configured to cover entire address space. We
+	 * need to configure it to its proper values, so that writes to
+	 * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
+	 * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
+	 */
+
+	/* Flash chipselect, CS0 */
+	/* ;CSAR0: Flash at 0xFF800000 */
+	mbar_writeShort(0x0080, 0xFF80);
+
+	/* CSCR0: Flash 6 waits, 16bit */
+	mbar_writeShort(0x008A, 0x1980);
+
+	/* CSMR0: Flash 8MB, R/W, valid */
+	mbar_writeLong(0x0084, 0x007F0001);
+
+
+	/*
+	 * SDRAM configuration proper
+	 */
+
+	/*
+	 * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
+	 * not enable data pins D[15:0], as we have 16 bit port to SDRAM
+	 */
+	mbar_writeByte(MCF_GPIO_PAR_AD,
+			MCF_GPIO_AD_ADDR23 |
+			MCF_GPIO_AD_ADDR22 |
+			MCF_GPIO_AD_ADDR21);
+
+	/* No need to configure BS pins - reset values are OK */
+
+	/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
+	mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
+
+	/* SDRAM Control Pin Assignment Reg. */
+	mbar_writeByte(MCF_GPIO_PAR_SDRAM,
+			MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
+			MCF_GPIO_SDRAM_SDWE |
+			MCF_GPIO_SDRAM_SCAS |
+			MCF_GPIO_SDRAM_SRAS |
+			MCF_GPIO_SDRAM_SCKE |
+			MCF_GPIO_SDRAM_SDCS_01);
+
+	/*
+	 * Wait 100us.  We run the bus at 50MHz, one cycle is 20ns. So 5
+	 * iterations will do, but we do 10 just to be safe.
+	 */
+	for (i = 0; i < 10; ++i)
+		asm(" nop");
+
+
+	/* 1. Initialize DRAM Control Register: DCR */
+	mbar_writeShort(MCF_SDRAMC_DCR,
+			MCF_SDRAMC_DCR_RTIM(0x10) |	/* 65ns */
+			MCF_SDRAMC_DCR_RC(0x60));	/* 1562 cycles */
+
+
+	/*
+	 * 2. Initialize DACR0
+	 *
+	 * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
+	 * CBM: cmd at A20, bank select bits 21 and up
+	 * PS: 16 bit
+	 */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
+			MCF_SDRAMC_DACRn_BA(0x00) |
+			MCF_SDRAMC_DACRn_CASL(0x03) |
+			MCF_SDRAMC_DACRn_CBM(0x03) |
+			MCF_SDRAMC_DACRn_PS(0x03));
+
+	/* Initialize DMR0 */
+	mbar_writeLong(MCF_SDRAMC_DMR0,
+			MCF_SDRAMC_DMRn_BAM_16M |
+			MCF_SDRAMC_DMRn_V);
+
+
+	/* 3. Set IP bit in DACR to initiate PALL command */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_IP);
+
+	/* Write to this block to initiate precharge */
+	*(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
+
+	/*
+	 * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
+	 * wait a wee longer, just to be safe.
+	 */
+	for (i = 0; i < 5; ++i)
+		asm(" nop");
+
+
+	/* 4. Set RE bit in DACR */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_RE);
+
+	/*
+	 * Wait for at least 8 auto refresh cycles to occur, i.e. at least
+	 * 781 bus cycles.
+	 */
+	for (i = 0; i < 1000; ++i)
+		asm(" nop");
+
+	/* Finish the configuration by issuing the MRS */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_MRS);
+
+	/*
+	 * Write to the SDRAM Mode Register A0-A11 = 0x400
+	 *
+	 * Write Burst Mode = Programmed Burst Length
+	 * Op Mode = Standard Op
+	 * CAS Latency = 3
+	 * Burst Type = Sequential
+	 * Burst Length = 1
+	 */
+	*(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/u-boot/board/idmr/u-boot.lds b/u-boot/board/idmr/u-boot.lds
new file mode 100644
index 0000000..9878ec1
--- /dev/null
+++ b/u-boot/board/idmr/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+GROUP(libgcc.o)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/m68k/cpu/mcf52x2/start.o		(.text)
+    arch/m68k/lib/traps.o		(.text)
+    arch/m68k/cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ids8247/Makefile b/u-boot/board/ids8247/Makefile
new file mode 100644
index 0000000..2b702ce
--- /dev/null
+++ b/u-boot/board/ids8247/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ids8247/ids8247.c b/u-boot/board/ids8247/ids8247.c
new file mode 100644
index 0000000..d621833
--- /dev/null
+++ b/u-boot/board/ids8247/ids8247.c
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
+	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
+#else /* normal I/O port pins */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
+#endif
+	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
+	/* PA21 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
+	/* PA15 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
+	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
+	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
+	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
+	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII TX_CLK */
+	/* PC22 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII RX_CLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
+	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
+	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
+	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
+	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
+	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
+	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
+	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
+	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
+	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
+	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
+	/* PD7	*/ {   1,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: IDS 8247\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int misc_init_r (void)
+{
+	gd->bd->bi_flashstart = 0xff800000;
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <asm/io.h>
+
+static u8 hwctl;
+
+static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE ) {
+			hwctl |= 0x1;
+			writeb(0x00, (this->IO_ADDR_W + 0x0a));
+		} else {
+			hwctl &= ~0x1;
+			writeb(0x00, (this->IO_ADDR_W + 0x08));
+		}
+		if ( ctrl & NAND_ALE ) {
+			hwctl |= 0x2;
+			writeb(0x00, (this->IO_ADDR_W + 0x09));
+		} else {
+			hwctl &= ~0x2;
+			writeb(0x00, (this->IO_ADDR_W + 0x08));
+		}
+		if ( (ctrl & NAND_NCE) != NAND_NCE)
+			writeb(0x00, (this->IO_ADDR_W + 0x0c));
+		else
+			writeb(0x00, (this->IO_ADDR_W + 0x08));
+	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+
+}
+
+static u_char ids_nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	return readb(this->IO_ADDR_R);
+}
+
+static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	struct nand_chip *nand = mtd->priv;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (hwctl & 0x1)
+			writeb(buf[i], (nand->IO_ADDR_W + 0x02));
+		else if (hwctl & 0x2)
+			writeb(buf[i], (nand->IO_ADDR_W + 0x01));
+		else
+			writeb(buf[i], nand->IO_ADDR_W);
+	}
+}
+
+static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	struct nand_chip *this = mtd->priv;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		buf[i] = readb(this->IO_ADDR_R);
+	}
+}
+
+static int ids_nand_dev_ready(struct mtd_info *mtd)
+{
+	/* constant delay (see also tR in the datasheet) */
+	udelay(12);
+	return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	/* Reference hardware control function */
+	nand->cmd_ctrl  = ids_nand_hwctrl;
+	nand->read_byte  = ids_nand_read_byte;
+	nand->write_buf  = ids_nand_write_buf;
+	nand->read_buf   = ids_nand_read_buf;
+	nand->dev_ready  = ids_nand_dev_ready;
+	nand->chip_delay = 12;
+
+	return 0;
+}
+
+#endif	/* CONFIG_CMD_NAND */
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup( blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/u-boot/board/impa7/Makefile b/u-boot/board/impa7/Makefile
new file mode 100644
index 0000000..79b12a2
--- /dev/null
+++ b/u-boot/board/impa7/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= impa7.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/impa7/config.mk b/u-boot/board/impa7/config.mk
new file mode 100644
index 0000000..15e7f04
--- /dev/null
+++ b/u-boot/board/impa7/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xc1780000
diff --git a/u-boot/board/impa7/flash.c b/u-boot/board/impa7/flash.c
new file mode 100644
index 0000000..d0c5880
--- /dev/null
+++ b/u-boot/board/impa7/flash.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x20000
+#define PARAM_SECT_SIZE 0x4000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F320B3T & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else if (i == 1)
+			flashbase = PHYS_FLASH_2;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 7) {
+				flash_info[i].start[j] =
+					flashbase + j * PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 7) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F320B3T & FLASH_TYPEMASK):
+		printf ("28F320F3B (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			*addr = 0x00200020;	/* erase setup */
+			*addr = 0x00D000D0;	/* erase confirm */
+
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = 0x00B000B0;	/* suspend erase */
+					*addr = 0x00FF00FF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			*addr = 0x00FF00FF;	/* reset to read mode */
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong barf;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* clear status register command */
+	*addr = 0x00500050;
+
+	/* program set-up command */
+	*addr = 0x00400040;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* read status register command */
+	*addr = 0x00700070;
+
+	/* wait while polling the status register */
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0x00B000B0;
+			goto outahere;
+		}
+
+		if (*addr & 0x003A003A) {	/* check for error */
+			barf = *addr;
+			if (barf & 0x003A0000) {
+				barf >>= 16;
+			} else {
+				barf &= 0x0000003A;
+			}
+			printf ("\nFlash write error %02lx at address %08lx\n", barf, (unsigned long) dest);
+			if (barf & 0x0002) {
+				printf ("Block locked, not erased.\n");
+				rc = ERR_NOT_ERASED;
+				goto outahere;
+			}
+			if (barf & 0x0010) {
+				printf ("Programming error.\n");
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (barf & 0x0008) {
+				printf ("Vpp Low error.\n");
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+	}
+
+
+      outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/impa7/impa7.c b/u-boot/board/impa7/impa7.c
new file mode 100644
index 0000000..205b1b3
--- /dev/null
+++ b/u-boot/board/impa7/impa7.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <clps7111.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number of EP7111 */
+	gd->bd->bi_arch_number = MACH_TYPE_EDB7211;
+
+	/* location of boot parameters for EP7111 */
+	gd->bd->bi_boot_params = 0xc0020100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/impa7/lowlevel_init.S b/u-boot/board/impa7/lowlevel_init.S
new file mode 100644
index 0000000..7ce10a2
--- /dev/null
+++ b/u-boot/board/impa7/lowlevel_init.S
@@ -0,0 +1,85 @@
+/*
+ * Memory Setup stuff - taken from ???
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+SYSCON2:	.long	0x80001100
+MEMCFG1:	.long	0x80000180
+MEMCFG2:	.long	0x800001C0
+DRFPR:		.long	0x80000200
+
+syscon2_mask:	.long	0x00000004
+memcfg1_val:	.long	0x160c1414
+memcfg2_mask:	.long	0x0000ffff @ only set lower 16 bits
+memcfg2_val:	.long	0x00000000 @ upper 16 bits are reserved for CS7 + CS6
+drfpr_val:	.long	0x00000081
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	/*
+	 * DRFPR
+	 * 64kHz DRAM refresh
+	 */
+	ldr	r0, DRFPR
+	ldr	r1, drfpr_val
+	str	r1, [r0]
+
+	/*
+	 * SYSCON2: clear bit 2, DRAM is 32 bits wide
+	 */
+	ldr	r0, SYSCON2
+	ldr	r2, [r0]
+	ldr	r1, syscon2_mask
+	bic	r2, r2, r1
+	str	r2, [r0]
+
+	/*
+	 * MEMCFG1
+	 * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
+	 * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
+	 * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
+	 */
+	ldr	r0, MEMCFG1
+	ldr	r1, memcfg1_val
+	str	r1, [r0]
+
+	/*
+	 * MEMCFG2
+	 * Setting up ? with 0
+	 *
+	 */
+	ldr	r0, MEMCFG2
+	ldr	r2, [r0]
+	ldr	r1, memcfg2_mask
+	bic	r2, r2, r1
+	ldr	r1, memcfg2_val
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/imx31_phycore/Makefile b/u-boot/board/imx31_phycore/Makefile
new file mode 100644
index 0000000..4fd4864
--- /dev/null
+++ b/u-boot/board/imx31_phycore/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= imx31_phycore.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/imx31_phycore/config.mk b/u-boot/board/imx31_phycore/config.mk
new file mode 100644
index 0000000..0131edf
--- /dev/null
+++ b/u-boot/board/imx31_phycore/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x87f00000
diff --git a/u-boot/board/imx31_phycore/imx31_phycore.c b/u-boot/board/imx31_phycore/imx31_phycore.c
new file mode 100644
index 0000000..3d7b7f7
--- /dev/null
+++ b/u-boot/board/imx31_phycore/imx31_phycore.c
@@ -0,0 +1,140 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <s6e63d6.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init (void)
+{
+	__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+	__REG(CSCR_L(0)) = 0x10000d03;
+	__REG(CSCR_A(0)) = 0x00720900;
+
+	__REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
+	__REG(CSCR_L(1)) = 0x444a4541;
+	__REG(CSCR_A(1)) = 0x44443302;
+
+	__REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
+	__REG(CSCR_L(4)) = 0x22252521;
+	__REG(CSCR_A(4)) = 0x22220a00;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* setup pins for I2C2 (for EEPROM, RTC) */
+	mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
+	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
+
+	gd->bd->bi_arch_number = MACH_TYPE_PCM037;	/* board id for linux */
+	gd->bd->bi_boot_params = (0x80000100);		/* adress of boot parameters */
+
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+	struct s6e63d6 data = {
+		/*
+		 * See comment in mxc_spi.c::decode_cs() for .cs field format.
+		 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
+		 * 2 of the SPI controller #1, since it is unused.
+		 */
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+		.id = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
+int checkboard (void)
+{
+	printf("Board: Phytec phyCore i.MX31\n");
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/imx31_phycore/lowlevel_init.S b/u-boot/board/imx31_phycore/lowlevel_init.S
new file mode 100644
index 0000000..c5d6eb0
--- /dev/null
+++ b/u-boot/board/imx31_phycore/lowlevel_init.S
@@ -0,0 +1,104 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	REG	CCM_CCMR, 0x074B0BF5
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	REG	CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |	PDR0_MCU_PODF(0)
+
+	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
+
+	REG	0x43FAC26C, 0 /* SDCLK */
+	REG	0x43FAC270, 0 /* CAS */
+	REG	0x43FAC274, 0 /* RAS */
+	REG	0x43FAC27C, 0x1000 /* CS2 (CSD0) */
+	REG	0x43FAC284, 0 /* DQM3 */
+	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	REG	0x43FAC28C, 0
+	REG	0x43FAC290, 0
+	REG	0x43FAC294, 0
+	REG	0x43FAC298, 0
+	REG	0x43FAC29C, 0
+	REG	0x43FAC2A0, 0
+	REG	0x43FAC2A4, 0
+	REG	0x43FAC2A8, 0
+	REG	0x43FAC2AC, 0
+	REG	0x43FAC2B0, 0
+	REG	0x43FAC2B4, 0
+	REG	0x43FAC2B8, 0
+	REG	0x43FAC2BC, 0
+	REG	0x43FAC2C0, 0
+	REG	0x43FAC2C4, 0
+	REG	0x43FAC2C8, 0
+	REG	0x43FAC2CC, 0
+	REG	0x43FAC2D0, 0
+	REG	0x43FAC2D4, 0
+	REG	0x43FAC2D8, 0
+	REG	0x43FAC2DC, 0
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x006ac73a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+	mov	pc, lr
diff --git a/u-boot/board/incaip/Makefile b/u-boot/board/incaip/Makefile
new file mode 100644
index 0000000..f1594a2
--- /dev/null
+++ b/u-boot/board/incaip/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/incaip/config.mk b/u-boot/board/incaip/config.mk
new file mode 100644
index 0000000..7ef5a66
--- /dev/null
+++ b/u-boot/board/incaip/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INCA-IP board with MIPS 4Kc CPU core
+#
+
+# ROM version
+CONFIG_SYS_TEXT_BASE = 0xB0000000
+
+# RAM version
+#CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/u-boot/board/incaip/flash.c b/u-boot/board/incaip/flash.c
new file mode 100644
index 0000000..cc11e24
--- /dev/null
+++ b/u-boot/board/incaip/flash.c
@@ -0,0 +1,671 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/inca-ip.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#if 0
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+#else
+#define FLASH_CYCLE1	0x0554
+#define FLASH_CYCLE2	0x02ab
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
+		ulong * buscon = (ulong *)
+			((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
+
+		/* Disable write protection */
+		*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
+
+#if 1
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+#endif
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[1] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	/* write one word to the flash */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		res = write_word_amd(info, (FPWV *)addr, data);
+		break;
+	case FLASH_MAN_INTEL:
+		res = write_word_intel(info, (FPWV *)addr, data);
+		break;
+	default:
+		/* unknown flash type, error! */
+		printf ("missing or unknown FLASH type\n");
+		res = 1;	/* not really a timeout, but gives error */
+		break;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+    FPWV *base;		/* first address in flash bank	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+
+    base = (FPWV *)(info->start[0]);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+    base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+    base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    /* data polling for D7 */
+    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00F000F0;	/* reset bank */
+	    res = 1;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+    *dest = (FPW)0x00400040;	/* program setup		*/
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
+	    res = 1;
+	}
+    }
+
+    if (res == 0 && (*dest & (FPW)0x00100010))
+	res = 1;	/* write failed, time out error is close enough	*/
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+    return (res);
+}
diff --git a/u-boot/board/incaip/incaip.c b/u-boot/board/incaip/incaip.c
new file mode 100644
index 0000000..3b30970
--- /dev/null
+++ b/u-boot/board/incaip/incaip.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/addrspace.h>
+#include <asm/inca-ip.h>
+#include <asm/io.h>
+#include <asm/reboot.h>
+
+extern uint incaip_get_cpuclk(void);
+
+void _machine_restart(void)
+{
+	*INCA_IP_WDT_RST_REQ = 0x3f;
+}
+
+static ulong max_sdram_size(void)
+{
+	/* The only supported SDRAM data width is 16bit.
+	 */
+#define CONFIG_SYS_DW	2
+
+	/* The only supported number of SDRAM banks is 4.
+	 */
+#define CONFIG_SYS_NB	4
+
+	ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
+	int   cols   = cfgpb0 & 0xF;
+	int   rows   = (cfgpb0 & 0xF0) >> 4;
+	ulong size   = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
+
+	return size;
+}
+
+phys_size_t initdram(int board_type)
+{
+	int   rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
+	ulong size, max_size       = 0;
+	ulong our_address;
+
+	asm volatile ("move %0, $25" : "=r" (our_address) :);
+
+		/* Can't probe for RAM size unless we are running from Flash.
+		 */
+	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
+	{
+		return max_sdram_size();
+	}
+
+	for (cols = 0x8; cols <= 0xC; cols++)
+	{
+		for (rows = 0xB; rows <= 0xD; rows++)
+		{
+			*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
+			                           (rows << 4) | cols;
+			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+			                                     max_sdram_size());
+
+			if (size > max_size)
+			{
+				best_val = *INCA_IP_SDRAM_MC_CFGPB0;
+				max_size = size;
+			}
+		}
+	}
+
+	*INCA_IP_SDRAM_MC_CFGPB0 = best_val;
+	return max_size;
+}
+
+int checkboard (void)
+{
+	unsigned long chipid = *INCA_IP_WDT_CHIPID;
+	int part_num;
+
+	puts ("Board: INCA-IP ");
+	part_num = (chipid >> 12) & 0xffff;
+	switch (part_num) {
+	case 0xc0:
+		printf ("Standard Version, ");
+		break;
+	case 0xc1:
+		printf ("Basic Version, ");
+		break;
+	default:
+		printf ("Unknown Part Number 0x%x ", part_num);
+		break;
+	}
+
+	printf ("Chip V1.%ld, ", (chipid >> 28));
+
+	printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+
+	set_io_port_base(0);
+
+	return 0;
+}
+
+#if defined(CONFIG_INCA_IP_SWITCH)
+int board_eth_init(bd_t *bis)
+{
+	return inca_switch_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/incaip/lowlevel_init.S b/u-boot/board/incaip/lowlevel_init.S
new file mode 100644
index 0000000..b765795
--- /dev/null
+++ b/u-boot/board/incaip/lowlevel_init.S
@@ -0,0 +1,303 @@
+/*
+ *  Memory sub-system initialization code for INCA-IP development board.
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/regdef.h>
+
+
+#define EBU_MODUL_BASE		0xB8000200
+#define EBU_CLC(value)		0x0000(value)
+#define EBU_CON(value)		0x0010(value)
+#define EBU_ADDSEL0(value)	0x0020(value)
+#define EBU_ADDSEL1(value)	0x0024(value)
+#define EBU_ADDSEL2(value)	0x0028(value)
+#define EBU_BUSCON0(value)	0x0060(value)
+#define EBU_BUSCON1(value)	0x0064(value)
+#define EBU_BUSCON2(value)	0x0068(value)
+
+#define MC_MODUL_BASE		0xBF800000
+#define MC_ERRCAUSE(value)	0x0100(value)
+#define MC_ERRADDR(value)	0x0108(value)
+#define MC_IOGP(value)		0x0800(value)
+#define MC_SELFRFSH(value)	0x0A00(value)
+#define MC_CTRLENA(value)	0x1000(value)
+#define MC_MRSCODE(value)	0x1008(value)
+#define MC_CFGDW(value)		0x1010(value)
+#define MC_CFGPB0(value)	0x1018(value)
+#define MC_LATENCY(value)	0x1038(value)
+#define MC_TREFRESH(value)	0x1040(value)
+
+#define CGU_MODUL_BASE		0xBF107000
+#define CGU_PLL1CR(value)	0x0008(value)
+#define CGU_DIVCR(value)	0x0010(value)
+#define CGU_MUXCR(value)	0x0014(value)
+#define CGU_PLL1SR(value)	0x000C(value)
+
+	.set	noreorder
+
+
+/*
+ * void ebu_init(long)
+ *
+ * a0 has the clock value we are going to run at
+ */
+	.globl	ebu_init
+	.ent	ebu_init
+ebu_init:
+__ebu_init:
+
+	li	t1, EBU_MODUL_BASE
+	li	t2, 0xA0000041
+	sw	t2, EBU_ADDSEL0(t1)
+	li	t2, 0xA0800041
+	sw	t2, EBU_ADDSEL2(t1)
+	li	t2, 0xBE0000F1
+	sw	t2, EBU_ADDSEL1(t1)
+
+	li	t3, 100000000
+	beq	a0, t3, 1f
+	nop
+	li	t3, 133000000
+	beq	a0, t3, 2f
+	nop
+	li	t3, 150000000
+	beq	a0, t3, 2f
+	nop
+	b	3f
+	nop
+
+	/* 100 MHz */
+1:
+	li	t2, 0x8841417D
+	sw	t2, EBU_BUSCON0(t1)
+	sw	t2, EBU_BUSCON2(t1)
+	li	t2, 0x684142BD
+	b	3f
+	sw	t2, EBU_BUSCON1(t1)	/* delay slot */
+
+	/* 133 or 150 MHz */
+2:
+	li	t2, 0x8841417E
+	sw	t2, EBU_BUSCON0(t1)
+	sw	t2, EBU_BUSCON2(t1)
+	li	t2, 0x684143FD
+	sw	t2, EBU_BUSCON1(t1)
+3:
+	jr	ra
+	nop
+
+	.end	ebu_init
+
+
+/*
+ * void cgu_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	cgu_init
+	.ent	cgu_init
+cgu_init:
+__cgu_init:
+
+	li	t1, CGU_MODUL_BASE
+
+	li	t3, 100000000
+	beq	a0, t3, 1f
+	nop
+	li	t3, 133000000
+	beq	a0, t3, 2f
+	nop
+	li	t3, 150000000
+	beq	a0, t3, 3f
+	nop
+	b	5f
+	nop
+
+	/* 100 MHz clock */
+1:
+	li	t2, 0x80000014
+	sw	t2, CGU_DIVCR(t1)
+	li	t2, 0x80000000
+	sw	t2, CGU_MUXCR(t1)
+	li	t2, 0x800B0001
+	b	5f
+	sw	t2, CGU_PLL1CR(t1)	/* delay slot */
+
+	/* 133 MHz clock */
+2:
+	li	t2, 0x80000054
+	sw	t2, CGU_DIVCR(t1)
+	li	t2, 0x80000000
+	sw	t2, CGU_MUXCR(t1)
+	li	t2, 0x800B0001
+	b	5f
+	sw	t2, CGU_PLL1CR(t1)	/* delay slot */
+
+	/* 150 MHz clock */
+3:
+	li	t2, 0x80000017
+	sw	t2, CGU_DIVCR(t1)
+	li	t2, 0xC00B0001
+	sw	t2, CGU_PLL1CR(t1)
+	li	t3, 0x80000000
+4:
+	lw	t2, CGU_PLL1SR(t1)
+	and	t2, t2, t3
+	beq	t2, zero, 4b
+	nop
+	li	t2, 0x80000001
+	sw	t2, CGU_MUXCR(t1)
+5:
+	jr	ra
+	nop
+
+	.end	cgu_init
+
+
+/*
+ * void sdram_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	sdram_init
+	.ent	sdram_init
+sdram_init:
+__sdram_init:
+
+	li	t1, MC_MODUL_BASE
+
+#if 0
+	/* Disable memory controller before changing any of its registers */
+	sw	zero, MC_CTRLENA(t1)
+#endif
+
+	li	t2, 100000000
+	beq	a0, t2, 1f
+	nop
+	li	t2, 133000000
+	beq	a0, t2, 2f
+	nop
+	li	t2, 150000000
+	beq	a0, t2, 3f
+	nop
+	b	5f
+	nop
+
+	/* 100 MHz clock */
+1:
+	/* Set clock ratio (clkrat=1:1, rddel=3) */
+	li	t2, 0x00000003
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 100MHz) */
+	li	t2, 0x0000061A
+	b	4f
+	sw	t2, MC_TREFRESH(t1)
+
+	/* 133 MHz clock */
+2:
+	/* Set clock ratio (clkrat=1:1, rddel=3) */
+	li	t2, 0x00000003
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 133MHz) */
+	li	t2, 0x00000822
+	b	4f
+	sw	t2, MC_TREFRESH(t1)
+
+	/* 150 MHz clock */
+3:
+	/* Set clock ratio (clkrat=3:2, rddel=4) */
+	li	t2, 0x00000014
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 150MHz) */
+	li	t2, 0x00000927
+	sw	t2, MC_TREFRESH(t1)
+
+4:
+	/* Clear Error log registers */
+	sw	zero, MC_ERRCAUSE(t1)
+	sw	zero, MC_ERRADDR(t1)
+
+	/* Clear Power-down registers */
+	sw	zero, MC_SELFRFSH(t1)
+
+	/* Set CAS Latency */
+	li	t2, 0x00000020		/* CL = 2 */
+	sw	t2, MC_MRSCODE(t1)
+
+	/* Set word width to 16 bit */
+	li	t2, 0x2
+	sw	t2, MC_CFGDW(t1)
+
+	/* Set CS0 to SDRAM parameters */
+	li	t2, 0x000014C9
+	sw	t2, MC_CFGPB0(t1)
+
+	/* Set SDRAM latency parameters */
+	li	t2, 0x00026325		/* BC PC100 */
+	sw	t2, MC_LATENCY(t1)
+
+5:
+	/* Finally enable the controller */
+	li	t2, 0x00000001
+	sw	t2, MC_CTRLENA(t1)
+
+	jr	ra
+	nop
+
+	.end	sdram_init
+
+
+	.globl	lowlevel_init
+	.ent	lowlevel_init
+lowlevel_init:
+
+	/* Disable Watchdog.
+	 */
+	la	t9, disable_incaip_wdt
+	jalr	t9
+	nop
+
+	/* EBU, CGU and SDRAM Initialization.
+	 */
+	li	a0, CONFIG_CPU_CLOCK_RATE
+	move	t0, ra
+
+	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
+	 * modify t0 and a0.
+	 */
+	bal	__cgu_init
+	nop
+	bal	__ebu_init
+	nop
+	bal	__sdram_init
+	nop
+	move	ra, t0
+
+	jr	ra
+	nop
+
+	.end	lowlevel_init
diff --git a/u-boot/board/incaip/u-boot.lds b/u-boot/board/incaip/u-boot.lds
new file mode 100644
index 0000000..3c4fbe3
--- /dev/null
+++ b/u-boot/board/incaip/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/inka4x0/Makefile b/u-boot/board/inka4x0/Makefile
new file mode 100644
index 0000000..6ec04b8
--- /dev/null
+++ b/u-boot/board/inka4x0/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2009
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o inkadiag.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/inka4x0/hyb25d512160bf-5.h b/u-boot/board/inka4x0/hyb25d512160bf-5.h
new file mode 100644
index 0000000..7eb1f50
--- /dev/null
+++ b/u-boot/board/inka4x0/hyb25d512160bf-5.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/inka4x0/inka4x0.c b/u-boot/board/inka4x0/inka4x0.c
new file mode 100644
index 0000000..fc498d6
--- /dev/null
+++ b/u-boot/board/inka4x0/inka4x0.c
@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2008-2009
+ * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
+ *
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_DDR_MT46V16M16)
+#include "mt46v16m16-75.h"
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
+#include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+	/* precharge all banks */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32(&sdram->mode, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
+#endif
+
+	/* precharge all banks */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* auto refresh */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+	/* set mode register */
+	out_be32(&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	volatile struct mpc5xxx_cdm     *cdm =
+		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	long test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
+	out_be32(&mm->sdram1, 0x40000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32(&sdram->config1, SDRAM_CONFIG1);
+	out_be32(&sdram->config2, SDRAM_CONFIG2);
+
+#if SDRAM_DDR
+	/* set tap delay */
+	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32(&mm->sdram0, 0x13 +
+			 __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32(&mm->sdram0, 0); /* disabled */
+	}
+
+	out_be32(&mm->sdram1, dramsize); /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mm->sdram0) & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: INKA 4X0\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT (CS0) cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
+}
+
+int misc_init_f (void)
+{
+	volatile struct mpc5xxx_gpio	*gpio    =
+		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
+	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	volatile struct mpc5xxx_gpt	*gpt;
+	char tmp[10];
+	int i, br;
+
+	i = getenv_f("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CONFIG_SYS_BRIGHTNESS;
+	if (br > 255)
+		br = 255;
+
+	/* Initialize GPIO output pins.
+	 */
+	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
+	for (i = 0; i <= 5; i++) {
+		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
+		out_be32(&gpt->emsr, 0x34);
+	}
+
+	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
+	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
+	out_be32(&gpt->emsr,  0);		/* Disable */
+	out_be32(&gpt->cir,   0x020000fe);
+	out_be32(&gpt->pwmcr, (br << 16));
+	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */
+
+	/* Configure PSC3_6,7 as GPIO output */
+	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
+	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
+
+	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
+	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
+				     MPC5XXX_GPIO_WKUP_7 |
+				     MPC5XXX_GPIO_WKUP_PSC3_9);
+	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
+				     MPC5XXX_GPIO_WKUP_7 |
+				     MPC5XXX_GPIO_WKUP_PSC3_9);
+
+	/* Set LR mirror bit because it is low-active */
+	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
+
+	/* Reset Coral-P graphics controller */
+	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
+
+	/* Enable display backlight */
+	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
+	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
+	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
+	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
+
+	/*
+	 * Configure three wire serial interface to RTC (PSC1_4,
+	 * PSC2_4, PSC3_4, PSC3_5)
+	 */
+	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
+				     MPC5XXX_GPIO_WKUP_PSC2_4);
+	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
+				     MPC5XXX_GPIO_WKUP_PSC2_4);
+	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
+	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
+				     MPC5XXX_GPIO_SINT_PSC3_5);
+	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
+				     MPC5XXX_GPIO_SINT_PSC3_5);
+	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
+	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
+
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/u-boot/board/inka4x0/inkadiag.c b/u-boot/board/inka4x0/inkadiag.c
new file mode 100644
index 0000000..cf82f61
--- /dev/null
+++ b/u-boot/board/inka4x0/inkadiag.c
@@ -0,0 +1,480 @@
+/*
+ * (C) Copyright 2008, 2009 Andreas Pfefferle,
+ *     DENX Software Engineering, ap@denx.de.
+ * (C) Copyright 2009 Detlev Zundel,
+ *     DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <config.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include <command.h>
+
+/* This is needed for the includes in ns16550.h */
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#include <ns16550.h>
+
+#define GPIO_BASE		((u_char *)CONFIG_SYS_CS3_START)
+
+#define DIGIN_TOUCHSCR_MASK	0x00003000	/* Inputs 12-13 */
+#define DIGIN_KEYB_MASK		0x00010000	/* Input 16 */
+
+#define DIGIN_DRAWER_SW1	0x00400000	/* Input 22 */
+#define DIGIN_DRAWER_SW2	0x00800000	/* Input 23 */
+
+#define DIGIO_LED0		0x00000001	/* Output 0 */
+#define DIGIO_LED1		0x00000002	/* Output 1 */
+#define DIGIO_LED2		0x00000004	/* Output 2 */
+#define DIGIO_LED3		0x00000008	/* Output 3 */
+#define DIGIO_LED4		0x00000010	/* Output 4 */
+#define DIGIO_LED5		0x00000020	/* Output 5 */
+
+#define DIGIO_DRAWER1		0x00000100	/* Output 8 */
+#define DIGIO_DRAWER2		0x00000200	/* Output 9 */
+
+#define SERIAL_PORT_BASE	((u_char *)CONFIG_SYS_CS2_START)
+
+#define PSC_OP1_RTS	0x01
+#define PSC_OP0_RTS	0x01
+
+/*
+ * Table with supported baudrates (defined in inka4x0.h)
+ */
+static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+#define	N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
+
+static unsigned int inka_digin_get_input(void)
+{
+	return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
+		in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
+}
+
+#define LED_HIGH(NUM)							\
+	do {								\
+		setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+	} while (0)
+
+#define LED_LOW(NUM)							\
+	do {								\
+		clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+	} while (0)
+
+#define CHECK_LED(NUM) \
+    do { \
+	    if (state & (1 << NUM)) {		\
+		    LED_HIGH(NUM);		\
+	    } else {				\
+		    LED_LOW(NUM);		\
+	    }					\
+    } while (0)
+
+static void inka_digio_set_output(unsigned int state, int which)
+{
+	volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (which == 0) {
+		/* other */
+		CHECK_LED(0);
+		CHECK_LED(1);
+		CHECK_LED(2);
+		CHECK_LED(3);
+		CHECK_LED(4);
+		CHECK_LED(5);
+	} else {
+		if (which == 1) {
+			/* drawer1 */
+			if (state) {
+				clrbits_be32(&gpio->simple_dvo, 0x1000);
+				udelay(1);
+				setbits_be32(&gpio->simple_dvo, 0x1000);
+			} else {
+				setbits_be32(&gpio->simple_dvo, 0x1000);
+				udelay(1);
+				clrbits_be32(&gpio->simple_dvo, 0x1000);
+			}
+		}
+		if (which == 2) {
+			/* drawer 2 */
+			if (state) {
+				clrbits_be32(&gpio->simple_dvo, 0x2000);
+				udelay(1);
+				setbits_be32(&gpio->simple_dvo, 0x2000);
+			} else {
+				setbits_be32(&gpio->simple_dvo, 0x2000);
+				udelay(1);
+				clrbits_be32(&gpio->simple_dvo, 0x2000);
+			}
+		}
+	}
+	udelay(1);
+}
+
+static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[]) {
+	unsigned int state, val;
+
+	switch (argc) {
+	case 3:
+		/* Write a value */
+		val = simple_strtol(argv[2], NULL, 16);
+
+		if (strcmp(argv[1], "drawer1") == 0) {
+			inka_digio_set_output(val, 1);
+		} else if (strcmp(argv[1], "drawer2") == 0) {
+			inka_digio_set_output(val, 2);
+		} else if (strcmp(argv[1], "other") == 0)
+			inka_digio_set_output(val, 0);
+		else {
+			printf("Invalid argument: %s\n", argv[1]);
+			return -1;
+		}
+		/* fall through */
+	case 2:
+		/* Read a value */
+		state = inka_digin_get_input();
+
+		if (strcmp(argv[1], "drawer1") == 0) {
+			val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
+		} else if (strcmp(argv[1], "drawer2") == 0) {
+			val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
+		} else if (strcmp(argv[1], "other") == 0) {
+			val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
+				| (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
+		} else {
+			printf("Invalid argument: %s\n", argv[1]);
+			return -1;
+		}
+		printf("exit code: 0x%X\n", val);
+		return 0;
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return -1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
+{
+	unsigned long baseclk;
+	int div;
+
+	/* reset PSC */
+	out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+	/* select clock sources */
+
+	out_be16(&psc->psc_clock_select, 0);
+	baseclk = (gd->ipb_clk + 16) / 32;
+
+	/* switch to UART mode */
+	out_be32(&psc->sicr, 0);
+
+	/* configure parity, bit length and so on */
+
+	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+	out_8(&psc->mode, PSC_MODE_ONE_STOP);
+
+	/* set up UART divisor */
+	div = (baseclk + (baudrate / 2)) / baudrate;
+	out_8(&psc->ctur, (div >> 8) & 0xff);
+	out_8(&psc->ctlr, div & 0xff);
+
+	/* disable all interrupts */
+	out_be16(&psc->psc_imr, 0);
+
+	/* reset and enable Rx/Tx */
+	out_8(&psc->command, PSC_RST_RX);
+	out_8(&psc->command, PSC_RST_TX);
+	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	return 0;
+}
+
+static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
+{
+	/* Wait 1 second for last character to go. */
+	int i = 0;
+
+	while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
+		udelay(10);
+	psc->psc_buffer_8 = c;
+
+}
+
+static int ser_getc(volatile struct mpc5xxx_psc *psc)
+{
+	/* Wait for a character to arrive. */
+	int i = 0;
+
+	while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
+		udelay(10);
+
+	return in_8(&psc->psc_buffer_8);
+}
+
+static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[]) {
+	volatile struct NS16550 *uart;
+	volatile struct mpc5xxx_psc *psc;
+	unsigned int num, mode;
+	int combrd, baudrate, i, j, len;
+	int address;
+
+	if (argc < 5)
+		return cmd_usage(cmdtp);
+
+	argc--;
+	argv++;
+
+	num = simple_strtol(argv[0], NULL, 0);
+	if (num < 0 || num > 11) {
+		printf("invalid argument for num: %d\n", num);
+		return -1;
+	}
+
+	mode = simple_strtol(argv[1], NULL, 0);
+
+	combrd = 0;
+	baudrate = simple_strtoul(argv[2], NULL, 10);
+	for (i=0; i<N_BAUDRATES; ++i) {
+		if (baudrate == baudrate_table[i])
+			break;
+	}
+	if (i == N_BAUDRATES) {
+		printf("## Baudrate %d bps not supported\n",
+		       baudrate);
+		return 1;
+	}
+	combrd = 115200 / baudrate;
+
+	uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
+
+	printf("Testing uart %d.\n\n", num);
+
+	if ((num >= 0) && (num <= 7)) {
+		if (mode & 1) {
+			/* turn on 'loopback' mode */
+			out_8(&uart->mcr, UART_MCR_LOOP);
+		} else {
+			/*
+			 * establish the UART's operational parameters
+			 * set DLAB=1, so rbr accesses DLL
+			 */
+			out_8(&uart->lcr, UART_LCR_DLAB);
+			/* set baudrate */
+			out_8(&uart->rbr, combrd);
+			/* set data-format: 8-N-1 */
+			out_8(&uart->lcr, UART_LCR_WLS_8);
+		}
+
+		if (mode & 2) {
+			/* set request to send */
+			out_8(&uart->mcr, UART_MCR_RTS);
+			udelay(10);
+			/* check clear to send */
+			if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
+				return -1;
+		}
+		if (mode & 4) {
+			/* set data terminal ready */
+			out_8(&uart->mcr, UART_MCR_DTR);
+			udelay(10);
+			/* check data set ready and carrier detect */
+			if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
+			    != (UART_MSR_DSR | UART_MSR_DCD))
+				return -1;
+		}
+
+		/* write each message-character, read it back, and display it */
+		for (i = 0, len = strlen(argv[3]); i < len; ++i) {
+			j = 0;
+			while ((in_8(&uart->lsr) & UART_LSR_THRE) ==	0x00) {
+				if (j++ > CONFIG_SYS_HZ)
+					break;
+				udelay(10);
+			}
+			out_8(&uart->rbr, argv[3][i]);
+			j = 0;
+			while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
+				if (j++ > CONFIG_SYS_HZ)
+					break;
+				udelay(10);
+			}
+			printf("%c", in_8(&uart->rbr));
+		}
+		printf("\n\n");
+		out_8(&uart->mcr, 0x00);
+	} else {
+		address = 0;
+
+		switch (num) {
+		case 8:
+			address = MPC5XXX_PSC6;
+			break;
+		case 9:
+			address = MPC5XXX_PSC3;
+			break;
+		case 10:
+			address = MPC5XXX_PSC2;
+			break;
+		case 11:
+			address = MPC5XXX_PSC1;
+			break;
+		}
+		psc = (struct mpc5xxx_psc *)address;
+		ser_init(psc, simple_strtol(argv[2], NULL, 0));
+		if (mode & 2) {
+			/* set request to send */
+			out_8(&psc->op0, PSC_OP0_RTS);
+			udelay(10);
+			/* check clear to send */
+			if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
+				return -1;
+		}
+		len = strlen(argv[3]);
+		for (i = 0; i < len; ++i) {
+			ser_putc(psc, argv[3][i]);
+			printf("%c", ser_getc(psc));
+		}
+		printf("\n\n");
+	}
+	return 0;
+}
+
+#define BUZZER_GPT	(MPC5XXX_GPT + 0x60)	/* GPT6 */
+static void buzzer_turn_on(unsigned int freq)
+{
+	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+	const u32 prescale = gd->ipb_clk / freq / 128;
+	const u32 count = 128;
+	const u32 width = 64;
+
+	gpt->cir = (prescale << 16) | count;
+	gpt->pwmcr = width << 16;
+	gpt->emsr = 3;		/* Timer enabled for PWM */
+}
+
+static void buzzer_turn_off(void)
+{
+	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+	gpt->emsr = 0;
+}
+
+static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[]) {
+
+	unsigned int period, freq;
+	int prev, i;
+
+	if (argc != 3)
+		return cmd_usage(cmdtp);
+
+	argc--;
+	argv++;
+
+	period = simple_strtol(argv[0], NULL, 0);
+	if (!period)
+		printf("Zero period is senseless\n");
+	argc--;
+	argv++;
+
+	freq = simple_strtol(argv[0], NULL, 0);
+	/* avoid zero prescale in buzzer_turn_on() */
+	if (freq > gd->ipb_clk / 128) {
+		printf("%dHz exceeds maximum (%ldHz)\n", freq,
+		       gd->ipb_clk / 128);
+	} else if (!freq)
+		printf("Zero frequency is senseless\n");
+	else
+		buzzer_turn_on(freq);
+
+	clear_ctrlc();
+	prev = disable_ctrlc(0);
+
+	printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
+
+	i = 0;
+	while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
+		udelay(period);
+
+	clear_ctrlc();
+	disable_ctrlc(prev);
+
+	buzzer_turn_off();
+
+	return 0;
+}
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+cmd_tbl_t cmd_inkadiag_sub[] = {
+	U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
+	 "<drawer1|drawer2|other> [value] - get or set specified signal"),
+	U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
+	 "<num> <mode> <baudrate> <msg>  - test uart num [0..11] in mode\n"
+	 "and baudrate with msg"),
+	U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
+	 "<period> <freq> - turn buzzer on for period ms with freq hz"),
+	U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
+	 "[command] - get help for command"),
+};
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
+			    int argc, char * const argv[]) {
+	extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
+			     cmd_tbl_t *cmdtp, int flag,
+			     int argc, char * const argv[]);
+	/* do_help prints command name - we prepend inkadiag to our subcommands! */
+#ifdef CONFIG_SYS_LONGHELP
+	puts ("inkadiag ");
+#endif
+	return _do_help(&cmd_inkadiag_sub[0],
+		ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
+}
+
+static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[]) {
+	cmd_tbl_t *c;
+
+	c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
+
+	if (c) {
+		argc--;
+		argv++;
+		return c->cmd(c, flag, argc, argv);
+	} else {
+		/* Unrecognized command */
+		return cmd_usage(cmdtp);
+	}
+}
+
+U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
+	   "inkadiag - inka diagnosis\n",
+	   "[inkadiag what ...]\n"
+	   "    - perform a diagnosis on inka hardware\n"
+	   "'inkadiag' performs hardware tests.");
diff --git a/u-boot/board/inka4x0/k4h511638c.h b/u-boot/board/inka4x0/k4h511638c.h
new file mode 100644
index 0000000..70cc405
--- /dev/null
+++ b/u-boot/board/inka4x0/k4h511638c.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/inka4x0/mt46v16m16-75.h b/u-boot/board/inka4x0/mt46v16m16-75.h
new file mode 100644
index 0000000..a78e50e
--- /dev/null
+++ b/u-boot/board/inka4x0/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/inka4x0/mt46v32m16-75.h b/u-boot/board/inka4x0/mt46v32m16-75.h
new file mode 100644
index 0000000..7eb1f50
--- /dev/null
+++ b/u-boot/board/inka4x0/mt46v32m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/inka4x0/mt48lc16m16a2-75.h b/u-boot/board/inka4x0/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/inka4x0/mt48lc16m16a2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/innokom/Makefile b/u-boot/board/innokom/Makefile
new file mode 100644
index 0000000..054175f
--- /dev/null
+++ b/u-boot/board/innokom/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= innokom.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/innokom/flash.c b/u-boot/board/innokom/flash.c
new file mode 100644
index 0000000..8c95341
--- /dev/null
+++ b/u-boot/board/innokom/flash.c
@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2002
+ * Auerswald GmbH & Co KG, Germany
+ * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+/* Debugging macros ------------------------------------------------------  */
+
+#undef FLASH_DEBUG
+
+/* Some debug macros */
+#if (FLASH_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if FLASH_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef FLASH_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+/* ------------------------------------------------------------------------ */
+
+/* Development system: we have only 16 MB Flash                             */
+#ifdef CONFIG_MTD_INNOKOM_16MB
+#define FLASH_BANK_SIZE 0x01000000	/* 16 MB (during development)       */
+#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
+#endif
+
+/* Production system: we have 64 MB Flash                                   */
+#ifdef CONFIG_MTD_INNOKOM_64MB
+#define FLASH_BANK_SIZE 0x04000000	/* 64 MB                            */
+#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
+#endif
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/**
+ * flash_init: - initialize data structures for flash chips
+ *
+ * @return: size of the flash
+ */
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+
+		switch (i) {
+			case 0:
+				flashbase = PHYS_FLASH_1;
+				break;
+			default:
+				panic("configured too many flash banks!\n");
+				break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect u-boot sectors */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + (256*1024) - 1,
+			&flash_info[0]);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+
+/**
+ * flash_print_info: - print information about the flash situation
+ *
+ * @param info:
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i, j;
+
+	for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
+
+		switch (info->flash_id & FLASH_VENDMASK) {
+
+			case (INTEL_MANUFACT & FLASH_VENDMASK):
+				printf("Intel: ");
+				break;
+			default:
+				printf("Unknown Vendor ");
+				break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+
+			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+				printf("28F128J3 (128Mbit)\n");
+				break;
+			default:
+				printf("Unknown Chip Type\n");
+				return;
+		}
+
+		printf("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+		printf("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) printf ("\n   ");
+
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}
+}
+
+
+/**
+ * flash_erase: - erase flash sectors
+ *
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) prot++;
+	}
+
+	if (prot) return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+		PRINTK("\n");
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			u16 * volatile addr = (u16 * volatile)(info->start[sect]);
+
+			PRINTK("unlocking sector\n");
+			*addr = 0x0060;
+			*addr = 0x00d0;
+			*addr = 0x00ff;
+
+			PRINTK("erasing sector\n");
+			*addr = 0x0020;
+			PRINTK("confirming erase\n");
+			*addr = 0x00D0;
+
+			while ((*addr & 0x0080) != 0x0080) {
+				PRINTK(".");
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = 0x00B0; /* suspend erase*/
+					*addr = 0x00FF; /* read mode    */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			PRINTK("clearing status register\n");
+			*addr = 0x0050;
+			PRINTK("resetting to read mode");
+			*addr = 0x00FF;
+		}
+
+		printf("ok.\n");
+	}
+
+	if (ctrlc()) printf("User Interrupt!\n");
+
+	outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked(10000);
+
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+
+/**
+ * write_word: - copy memory to flash
+ *
+ * @param info:
+ * @param dest:
+ * @param data:
+ * @return:
+ */
+
+static int write_word (flash_info_t *info, ulong dest, ushort data)
+{
+	volatile u16 *addr = (u16 *)dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts();
+
+	/* clear status register command */
+	*addr = 0x50;
+
+	/* program set-up command */
+	*addr = 0x40;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while(((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			*addr = 0xB0; /* suspend program command */
+			goto outahere;
+		}
+	}
+
+	if(val & 0x1A) {	/* check for error */
+		printf("\nFlash write error %02x at address %08lx\n",
+			(int)val, (unsigned long)dest);
+		if(val & (1<<3)) {
+			printf("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if(val & (1<<1)) {
+			printf("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if(val & (1<<4)) {
+			printf("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+	outahere:
+
+	*addr = 0xFF; /* read array command */
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr:	where to copy to
+ * @param cnt:	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+		for (; i<2 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((ushort*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 8);
+	}
+
+	return write_word(info, wp, data);
+}
diff --git a/u-boot/board/innokom/innokom.c b/u-boot/board/innokom/innokom.c
new file mode 100644
index 0000000..e658c35
--- /dev/null
+++ b/u-boot/board/innokom/innokom.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
+ * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
+ * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ * The Innokom board has GPIO70 connected to SCLK which can be toggled
+ * until all chips think that their current cycles are finished.
+ */
+int i2c_init_board(void)
+{
+	int i, icr;
+
+	/* disable I2C controller first, otherwhise it thinks we want to    */
+	/* talk to the slave port...                                        */
+	icr = readl(ICR);
+	writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
+
+	/* set gpio pin low _before_ we change direction to output          */
+	writel(GPIO_bit(70), GPCR(70));
+
+	/* now toggle between output=low and high-impedance                 */
+	for (i = 0; i < 20; i++) {
+		writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70));  /* output */
+		udelay(10);
+		writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input  */
+		udelay(10);
+	}
+
+	writel(icr, ICR);
+
+	return 0;
+}
+
+
+/**
+ * misc_init_r: - misc initialisation routines
+ */
+
+int misc_init_r(void)
+{
+	char *str;
+
+	/* determine if the software update key is pressed during startup   */
+	if (readl(GPLR0) & 0x00000800) {
+		printf("using bootcmd_normal (sw-update button not pressed)\n");
+		str = getenv("bootcmd_normal");
+	} else {
+		printf("using bootcmd_update (sw-update button pressed)\n");
+		str = getenv("bootcmd_update");
+	}
+
+	setenv("bootcmd",str);
+
+	return 0;
+}
+
+
+/**
+ * board_init: - setup some data structures
+ *
+ * @return: 0 in case of success
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
+	gd->bd->bi_boot_params = 0xa0000100;
+	gd->bd->bi_baudrate = CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+/**
+ * innokom_set_led: - switch LEDs on or off
+ *
+ * @param led:   LED to switch (0,1,2)
+ * @param state: switch on (1) or off (0)
+ */
+
+void innokom_set_led(int led, int state)
+{
+	switch(led) {
+/*
+		case 0: if (state==1) {
+				GPCR0 |= CSB226_USER_LED0;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED0;
+			}
+			break;
+
+		case 1: if (state==1) {
+				GPCR0 |= CSB226_USER_LED1;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED1;
+			}
+			break;
+
+		case 2: if (state==1) {
+				GPCR0 |= CSB226_USER_LED2;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED2;
+			}
+			break;
+*/
+	}
+
+	return;
+}
+
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	switch(status) {
+/*
+		case  1: csb226_set_led(0,1); break;
+		case  5: csb226_set_led(1,1); break;
+		case 15: csb226_set_led(2,1); break;
+*/
+	}
+
+	return;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ip04/Makefile b/u-boot/board/ip04/Makefile
new file mode 100644
index 0000000..06b8217
--- /dev/null
+++ b/u-boot/board/ip04/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2010 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ip04/config.mk b/u-boot/board/ip04/config.mk
new file mode 100644
index 0000000..fc818fb
--- /dev/null
+++ b/u-boot/board/ip04/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf532-0.5
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/ip04/ip04.c b/u-boot/board/ip04/ip04.c
new file mode 100644
index 0000000..c8ae512
--- /dev/null
+++ b/u-boot/board/ip04/ip04.c
@@ -0,0 +1,42 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2007 David Rowe,
+ *           (c) 2006 Ivan Danov
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/net.h>
+
+int checkboard(void)
+{
+	printf("Board: IP04 IP-PBX\n");
+	printf("       http://www.rowetel.com/ucasterisk/ip04.html\n");
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+
+int misc_init_r(void)
+{
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/ip860/Makefile b/u-boot/board/ip860/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/ip860/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ip860/flash.c b/u-boot/board/ip860/flash.c
new file mode 100644
index 0000000..6491af2
--- /dev/null
+++ b/u-boot/board/ip860/flash.c
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	bcsr->bd_ctrl |= BD_CTRL_FLWE;
+
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br1 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* all possible flash types
+	 * (28F016SV, 28F160S3, 28F320S3)
+	 * have the same erase block size: 64 kB per chip,
+	 * of 128 kB per bank
+	 */
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += 0x00020000;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+
+	value = addr[0];
+	switch (value) {
+	case (MT_MANUFACT & 0x00FF00FF):	/* MT or => Intel */
+	case (INTEL_ALT_MANU & 0x00FF00FF):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 2x4 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + (i * 0x00020000);
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			/* Resume Command, as per errata update */
+			*addr = 0xD0D0D0D0;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+		}
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x00400040) {
+printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/ip860/ip860.c b/u-boot/board/ip860/ip860.c
new file mode 100644
index 0000000..adff2b2
--- /dev/null
+++ b/u-boot/board/ip860/ip860.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+unsigned long ip860_get_dram_size(void);
+unsigned long ip860_get_clk_freq (void);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,					/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7ffffc07,					/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+/* ------------------------------------------------------------------------- */
+int board_early_init_f(void)
+{
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
+    memctl->memc_or4 = CONFIG_SYS_OR4;
+    memctl->memc_br4 = CONFIG_SYS_BR4;
+
+    return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (IP860...)
+ */
+
+int checkboard (void)
+{
+	unsigned char *s, *e;
+	unsigned char buf[64];
+	int i;
+
+	puts ("Board: ");
+
+	i = getenv_f("serial#", (char *)buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
+
+	if (!s || strncmp ((char *)s, "IP860", 5)) {
+		puts ("### No HW ID - assuming IP860");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+	ulong refresh_val;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	if (ip860_get_clk_freq() == 50000000)
+	{
+		memctl->memc_mptpr = 0x0400;
+		refresh_val = 0xC3000000;
+	}
+	else
+	{
+		memctl->memc_mptpr = 0x0200;
+		refresh_val = 0x9C000000;
+	}
+
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 to the SDRAM address
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
+
+	/* IP860 boards have only one bank SDRAM */
+
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mamr = 0x00804114 | refresh_val;
+	memctl->memc_mcr  = 0x80004105;	/* run precharge pattern from loc 5 */
+	udelay(1);
+	memctl->memc_mamr = 0x00804118 | refresh_val;
+	memctl->memc_mcr  = 0x80004130;	/* run refresh pattern 8 times */
+
+
+	udelay (1000);
+
+	/*
+	 * Check SDRAM Memory Size
+	 */
+	if (ip860_get_dram_size() == 16)
+		size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
+	else
+		size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	udelay (10000);
+
+	/*
+	 * Also, map other memory to correct position
+	 */
+
+#if (defined(CONFIG_SYS_OR1) && defined(CONFIG_SYS_BR1_PRELIM))
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
+#endif
+
+#if defined(CONFIG_SYS_OR3) && defined(CONFIG_SYS_BR3)
+	memctl->memc_or3 = CONFIG_SYS_OR3;
+	memctl->memc_br3 = CONFIG_SYS_BR3;
+#endif
+
+#if defined(CONFIG_SYS_OR4) && defined(CONFIG_SYS_BR4)
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
+#endif
+
+#if defined(CONFIG_SYS_OR5) && defined(CONFIG_SYS_BR5)
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
+#endif
+
+#if defined(CONFIG_SYS_OR6) && defined(CONFIG_SYS_BR6)
+	memctl->memc_or6 = CONFIG_SYS_OR6;
+	memctl->memc_br6 = CONFIG_SYS_BR6;
+#endif
+
+#if defined(CONFIG_SYS_OR7) && defined(CONFIG_SYS_BR7)
+	memctl->memc_or7 = CONFIG_SYS_OR7;
+	memctl->memc_br7 = CONFIG_SYS_BR7;
+#endif
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	ulong mask = PB_ENET_RESET | PB_ENET_JABD;
+	ulong reg;
+
+	/* Make sure PHY is not in low-power mode */
+	immr->im_cpm.cp_pbpar &= ~(mask);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(mask);	/* active output */
+
+	/* Set  JABD low  (no JABber Disable),
+	 * and RESET high (Reset PHY)
+	 */
+	reg = immr->im_cpm.cp_pbdat;
+	reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET;
+	immr->im_cpm.cp_pbdat = reg;
+
+	/* now drive outputs */
+	immr->im_cpm.cp_pbdir |= mask;	/* output */
+	udelay (1000);
+	/*
+	   * Release RESET signal
+	 */
+	immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET);
+	udelay (1000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+unsigned long ip860_get_clk_freq(void)
+{
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	ulong temp;
+	uchar sysclk;
+
+	if ((bcsr->bd_status & 0x80) == 0x80)	/* bd_rev valid ? */
+		sysclk = (bcsr->bd_rev & 0x18) >> 3;
+	else
+		sysclk = 0x00;
+
+	switch (sysclk)
+	{
+		case 0x00:
+			temp = 50000000;
+			break;
+
+		case 0x01:
+			temp = 80000000;
+			break;
+
+		default:
+			temp = 50000000;
+			break;
+	}
+
+	return (temp);
+
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+unsigned long ip860_get_dram_size(void)
+{
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	ulong temp;
+	uchar dram_size;
+
+	if ((bcsr->bd_status & 0x80) == 0x80)	/* bd_rev valid ? */
+		dram_size = (bcsr->bd_rev & 0xE0) >> 5;
+	else
+		dram_size = 0x00;	/* default is 16 MB */
+
+	switch (dram_size)
+	{
+		case 0x00:
+			temp = 16;
+			break;
+
+		case 0x01:
+			temp = 32;
+			break;
+
+		default:
+			temp = 16;
+			break;
+	}
+
+	return (temp);
+
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/ip860/u-boot.lds b/u-boot/board/ip860/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/ip860/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ip860/u-boot.lds.debug b/u-boot/board/ip860/u-boot.lds.debug
new file mode 100644
index 0000000..0c0bbb8
--- /dev/null
+++ b/u-boot/board/ip860/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    arch/powerpc/lib/ppcstring.o	(.text)
+    arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+    arch/powerpc/lib/time.o		(.text)
+    arch/powerpc/lib/ticks.o		(.text)
+/**
+    . = env_offset;
+    common/env_embedded.o(.text)
+**/
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ipek01/Makefile b/u-boot/board/ipek01/Makefile
new file mode 100644
index 0000000..16f0c6b
--- /dev/null
+++ b/u-boot/board/ipek01/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ipek01/ipek01.c b/u-boot/board/ipek01/ipek01.c
new file mode 100644
index 0000000..85cd0a0
--- /dev/null
+++ b/u-boot/board/ipek01/ipek01.c
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+/* mt46v16m16-75 */
+#ifdef CONFIG_MPC5200_DDR
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+#else
+#error SDRAM is not supported on this board
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* set mode register: extended mode */
+	out_be32 (&sdram->mode, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* auto refresh */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+	/* set mode register */
+	out_be32 (&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
+	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32 (&sdram->config1, SDRAM_CONFIG1);
+	out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+	/* set tap delay */
+	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start (0);
+	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start (1);
+	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start (0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		out_be32 (&mmap_ctl->sdram0,
+			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
+	else
+		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	out_be32 (&sdram->sdelay, 0x04);
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: IPEK01 \n");
+	return 0;
+}
+
+void flash_preinit (void)
+{
+	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
+}
+
+void flash_afterinit (ulong start, ulong size)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_BOOT_ROM)
+	/* adjust mapping */
+	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
+	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
+#else
+	/* adjust mapping */
+	out_be32 (&mmap_ctl->boot_start, START_REG (start));
+	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
+	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
+	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
+#endif
+}
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	return (0);
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init (struct pci_controller *);
+
+void pci_init_board (void)
+{
+	pci_mpc5xxx_init (&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t * bd)
+{
+	ft_cpu_setup (blob, bd);
+	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_VIDEO
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs[] = {
+	{0x0100, 0x00000900},
+	{0x0020, 0x80190257},
+	{0x0024, 0x00000000},
+	{0x0028, 0x00000000},
+	{0x002c, 0x00000000},
+	{0x0110, 0x00000000},
+	{0x0114, 0x00000000},
+	{0x0118, 0x02570320},
+	{0x0004, 0x041f0000},
+	{0x0008, 0x031f031f},
+	{0x000c, 0x067f0347},
+	{0x0010, 0x02780000},
+	{0x0014, 0x0257025c},
+	{0x0018, 0x00000000},
+	{0x001c, 0x02570320},
+	{0x0100, 0x80010900},
+	{0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+	return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
+		return 0;
+
+	mb862xx.winSizeX = 800;
+	mb862xx.winSizeY = 600;
+	mb862xx.gdfIndex = GDF_15BIT_555RGB;
+	mb862xx.gdfBytesPP = 2;
+
+	return CONFIG_SYS_LIME_BASE;
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1)
+		strcpy (info, " Board: IPEK01");
+	else
+		info[0] = '\0';
+}
+#endif
+#endif /* CONFIG_VIDEO */
diff --git a/u-boot/board/iphase4539/Makefile b/u-boot/board/iphase4539/Makefile
new file mode 100644
index 0000000..89d3524
--- /dev/null
+++ b/u-boot/board/iphase4539/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/iphase4539/flash.c b/u-boot/board/iphase4539/flash.c
new file mode 100644
index 0000000..3dfee1f
--- /dev/null
+++ b/u-boot/board/iphase4539/flash.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Adapted for Interphase 4539 by Wolfgang Grandegger <wg@denx.de>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+extern int hwc_flash_size(void);
+static ulong flash_get_size (u32 addr, flash_info_t *info);
+static int flash_get_offsets (u32 base, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_reset (u32 addr);
+
+#define out8(a,v) *(volatile unsigned char*)(a) = v
+#define in8(a)	  *(volatile unsigned char*)(a)
+#define in32(a)	  *(volatile unsigned long*)(a)
+#define iobarrier_rw() eieio()
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long flash_size = 0;
+	unsigned long bank_size;
+	unsigned int bank = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = 0;
+		flash_info[i].size = 0;
+	}
+
+	/* Initialise the BOOT Flash */
+	if (bank == CONFIG_SYS_MAX_FLASH_BANKS) {
+		puts ("Warning: not all Flashes are initialised !");
+		return flash_size;
+	}
+
+	bank_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info + bank);
+	if (bank_size) {
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MAX_FLASH_SIZE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			      flash_info + bank);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			      flash_info + bank);
+#endif
+
+		/* HWC protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_FLASH_BASE,
+			      CONFIG_SYS_FLASH_BASE + 0x10000 - 1,
+			      flash_info + bank);
+
+		flash_size += bank_size;
+		bank++;
+	} else {
+		puts ("Warning: the BOOT Flash is not initialised !");
+	}
+
+	return flash_size;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (u32 addr, flash_info_t *info)
+{
+	volatile uchar value;
+#if 0
+	int i;
+#endif
+
+	/* Write auto select command: read Manufacturer ID */
+	out8(addr + 0x0555, 0xAA);
+	iobarrier_rw();
+	udelay(10);
+	out8(addr + 0x02AA, 0x55);
+	iobarrier_rw();
+	udelay(10);
+	out8(addr + 0x0555, 0x90);
+	iobarrier_rw();
+	udelay(10);
+
+	value = in8(addr);
+	iobarrier_rw();
+	udelay(10);
+	switch (value | (value << 16)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		flash_reset (addr);
+		return 0;
+	}
+
+	value = in8(addr + 1);			/* device ID		*/
+	iobarrier_rw();
+
+	switch (value) {
+	case AMD_ID_LV033C:
+		info->flash_id += FLASH_AM033C;
+		info->size = hwc_flash_size();
+		if (info->size > CONFIG_SYS_MAX_FLASH_SIZE) {
+			printf("U-Boot supports only %d MB\n",
+			       CONFIG_SYS_MAX_FLASH_SIZE);
+			info->size = CONFIG_SYS_MAX_FLASH_SIZE;
+		}
+		info->sector_count = info->size / 0x10000;
+		break;				/* => 4 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		flash_reset (addr);
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (!flash_get_offsets (addr, info)) {
+		flash_reset (addr);
+		return 0;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		value = in8(info->start[i] + 2);
+		iobarrier_rw();
+		info->protect[i] = (value & 1) != 0;
+	}
+#endif
+
+	/*
+	 * Reset bank to read mode
+	 */
+	flash_reset (addr);
+
+	return (info->size);
+}
+
+static int flash_get_offsets (u32 base, flash_info_t *info)
+{
+	unsigned int i, size;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM033C:
+		/* set sector offsets for uniform sector type	*/
+		size = info->size / info->sector_count;
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + i * size;
+		}
+		break;
+	default:
+		return 0;
+	}
+
+	return 1;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile u32 addr = info->start[0];
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if (s_first < 0 || s_first > s_last) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN ||
+	    info->flash_id > FLASH_AMD_COMP) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x80);
+	iobarrier_rw();
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = info->start[sect];
+			out8(addr, 0x30);
+			iobarrier_rw();
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = info->start[l_sect];
+	while ((in8(addr) & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+		iobarrier_rw();
+	}
+
+DONE:
+	/* reset to read mode */
+	flash_reset (info->start[0]);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile u32 addr = info->start[0];
+	ulong start;
+	int flag, i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((in32(dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x20);
+	iobarrier_rw();
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		out8(addr, 0xA0);
+		iobarrier_rw();
+		out8(dest+i, data_ch[i]);
+		iobarrier_rw();
+		udelay(10); /* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	out8(addr, 0x90);
+	iobarrier_rw();
+	out8(addr, 0x00);
+	iobarrier_rw();
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+		iobarrier_rw();
+	}
+
+	flash_reset (addr);
+
+	return (0);
+}
+
+/*
+ * Reset bank to read mode
+ */
+static void flash_reset (u32 addr)
+{
+	out8(addr, 0xF0);	/* reset bank */
+	iobarrier_rw();
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM033C:	printf ("AM29LV033C (32 Mbit, uniform sectors)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size % 0x100000 == 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size / 0x100000, info->sector_count);
+	}
+	else if (info->size % 0x400 == 0) {
+		printf ("  Size: %ld KB in %d Sectors\n",
+			info->size / 0x400, info->sector_count);
+	}
+	else {
+		printf ("  Size: %ld B in %d Sectors\n",
+			info->size, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
diff --git a/u-boot/board/iphase4539/iphase4539.c b/u-boot/board/iphase4539/iphase4539.c
new file mode 100644
index 0000000..7fec2cc
--- /dev/null
+++ b/u-boot/board/iphase4539/iphase4539.c
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/io.h>
+#include <asm/immap_8260.h>
+
+int hwc_flash_size (void);
+int hwc_local_sdram_size (void);
+int hwc_main_sdram_size (void);
+int hwc_serial_number (void);
+int hwc_mac_address (char *str);
+int hwc_manufact_date (char *str);
+int seeprom_read (int addr, uchar * data, int size);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ *
+ * The port definitions are taken from the old firmware (see
+ * also SYS/H/4539.H):
+ *
+ *        ppar      psor        pdir       podr       pdat
+ * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0
+ * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290
+ * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d
+ * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 1, 0, 0, 0, 0},		/* PA31 FCC1_TXENB  SLAVE */
+	 {0, 1, 0, 1, 0, 0},		/* PA30 FCC1_TXCLAV SLAVE */
+	 {0, 1, 0, 1, 0, 0},		/* PA29 FCC1_TXSOC */
+	 {0, 1, 0, 0, 0, 0},		/* PA28 FCC1_RXENB  SLAVE */
+	 {0, 1, 0, 0, 0, 0},		/* PA27 FCC1_RXSOC */
+	 {0, 1, 0, 1, 0, 0},		/* PA26 FCC1_RXCLAV SLAVE */
+	 {0, 1, 0, 1, 0, 1},		/* PA25 FCC1_TXD0 */
+	 {0, 1, 0, 1, 0, 1},		/* PA24 FCC1_TXD1 */
+	 {0, 1, 0, 1, 0, 1},		/* PA23 FCC1_TXD2 */
+	 {0, 1, 0, 1, 0, 1},		/* PA22 FCC1_TXD3 */
+	 {0, 1, 0, 1, 0, 1},		/* PA21 FCC1_TXD4 */
+	 {0, 1, 0, 1, 0, 1},		/* PA20 FCC1_TXD5 */
+	 {0, 1, 0, 1, 0, 1},		/* PA19 FCC1_TXD6 */
+	 {0, 1, 0, 1, 0, 1},		/* PA18 FCC1_TXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PA17 FCC1_RXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PA16 FCC1_RXD6 */
+	 {0, 1, 0, 0, 0, 0},		/* PA15 FCC1_RXD5 */
+	 {0, 1, 0, 0, 0, 0},		/* PA14 FCC1_RXD4 */
+	 {0, 1, 0, 0, 0, 0},		/* PA13 FCC1_RXD3 */
+	 {0, 1, 0, 0, 0, 0},		/* PA12 FCC1_RXD2 */
+	 {0, 1, 0, 0, 0, 0},		/* PA11 FCC1_RXD1 */
+	 {0, 1, 0, 0, 0, 0},		/* PA10 FCC1_RXD0 */
+	 {0, 1, 1, 1, 0, 1},		/* PA9  TDMA1_L1TXD */
+	 {0, 1, 1, 0, 0, 0},		/* PA8  TDMA1_L1RXD */
+	 {0, 0, 0, 0, 0, 0},		/* PA7  CONFIG0 */
+	 {0, 1, 1, 0, 0, 1},		/* PA6  TDMA1_L1RSYNC */
+	 {0, 0, 0, 1, 0, 0},		/* PA5  FCC2:RxAddr[2] */
+	 {0, 0, 0, 1, 0, 0},		/* PA4  FCC2:RxAddr[1] */
+	 {0, 0, 0, 1, 0, 0},		/* PA3  FCC2:RxAddr[0] */
+	 {0, 0, 0, 1, 0, 0},		/* PA2  FCC2:TxAddr[0] */
+	 {0, 0, 0, 1, 0, 0},		/* PA1  FCC2:TxAddr[1] */
+	 {0, 0, 0, 1, 0, 0}			/* PA0  FCC2:TxAddr[2] */
+	 },
+	/* Port B configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 0, 0, 1, 0, 0},		/* PB31 FCC2_RXSOC */
+	 {0, 0, 0, 1, 0, 0},		/* PB30 FCC2_TXSOC */
+	 {0, 0, 0, 1, 0, 0},		/* PB29 FCC2_RXCLAV */
+	 {0, 0, 0, 0, 0, 0},		/* PB28 CONFIG2 */
+	 {0, 1, 1, 0, 0, 1},		/* PB27 FCC2_TXD0 */
+	 {0, 1, 1, 0, 0, 0},		/* PB26 FCC2_TXD1 */
+	 {0, 0, 0, 1, 0, 0},		/* PB25 FCC2_TXD4 */
+	 {0, 1, 1, 0, 0, 1},		/* PB24 FCC2_TXD5 */
+	 {0, 0, 0, 1, 0, 0},		/* PB23 FCC2_TXD6 */
+	 {0, 1, 0, 1, 0, 1},		/* PB22 FCC2_TXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PB21 FCC2_RXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PB20 FCC2_RXD6 */
+	 {0, 1, 0, 0, 0, 0},		/* PB19 FCC2_RXD5 */
+	 {0, 0, 0, 1, 0, 0},		/* PB18 FCC2_RXD4 */
+	 {1, 1, 0, 0, 0, 0},		/* PB17 FCC3_RX_DV */
+	 {1, 1, 0, 0, 0, 0},		/* PB16 FCC3_RX_ER */
+	 {1, 1, 0, 1, 0, 0},		/* PB15 FCC3_TX_ER */
+	 {1, 1, 0, 1, 0, 0},		/* PB14 FCC3_TX_EN */
+	 {1, 1, 0, 0, 0, 0},		/* PB13 FCC3_COL */
+	 {1, 1, 0, 0, 0, 0},		/* PB12 FCC3_CRS */
+	 {1, 1, 0, 0, 0, 0},		/* PB11 FCC3_RXD3 */
+	 {1, 1, 0, 0, 0, 0},		/* PB10 FCC3_RXD2 */
+	 {1, 1, 0, 0, 0, 0},		/* PB9  FCC3_RXD1 */
+	 {1, 1, 0, 0, 0, 0},		/* PB8  FCC3_RXD0 */
+	 {1, 1, 0, 1, 0, 1},		/* PB7  FCC3_TXD0 */
+	 {1, 1, 0, 1, 0, 1},		/* PB6  FCC3_TXD1 */
+	 {1, 1, 0, 1, 0, 1},		/* PB5  FCC3_TXD2 */
+	 {1, 1, 0, 1, 0, 1},		/* PB4  FCC3_TXD3 */
+	 {0, 0, 0, 0, 0, 0},		/* PB3  */
+	 {0, 0, 0, 0, 0, 0},		/* PB2  */
+	 {0, 0, 0, 0, 0, 0},		/* PB1  */
+	 {0, 0, 0, 0, 0, 0},		/* PB0  */
+	 },
+	/* Port C configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 1, 0, 0, 0, 1},		/* PC31 CLK1 */
+	 {0, 0, 0, 1, 0, 0},		/* PC30 U1MASTER_N */
+	 {0, 1, 0, 0, 0, 1},		/* PC29 CLK3 */
+	 {0, 0, 0, 1, 0, 1},		/* PC28 -MT90220_RST */
+	 {0, 1, 0, 0, 0, 1},		/* PC27 CLK5 */
+	 {0, 0, 0, 1, 0, 1},		/* PC26 -QUADFALC_RST */
+	 {0, 1, 1, 1, 0, 1},		/* PC25 BRG4 */
+	 {1, 0, 0, 1, 0, 0},		/* PC24 MDIO */
+	 {1, 0, 0, 1, 0, 0},		/* PC23 MDC */
+	 {0, 1, 0, 0, 0, 1},		/* PC22 CLK10 */
+	 {0, 0, 0, 1, 0, 0},		/* PC21  */
+	 {0, 1, 0, 0, 0, 1},		/* PC20 CLK12 */
+	 {0, 1, 0, 0, 0, 1},		/* PC19 CLK13 */
+	 {1, 1, 0, 0, 0, 1},		/* PC18 CLK14 */
+	 {0, 1, 0, 0, 0, 0},		/* PC17 CLK15 */
+	 {1, 1, 0, 0, 0, 1},		/* PC16 CLK16 */
+	 {0, 1, 1, 0, 0, 0},		/* PC15 FCC1_TXADDR0 SLAVE */
+	 {0, 1, 1, 0, 0, 0},		/* PC14 FCC1_RXADDR0 SLAVE */
+	 {0, 1, 1, 0, 0, 0},		/* PC13 FCC1_TXADDR1 SLAVE */
+	 {0, 1, 1, 0, 0, 0},		/* PC12 FCC1_RXADDR1 SLAVE */
+	 {0, 0, 0, 1, 0, 0},		/* PC11 FCC2_RXD2 */
+	 {0, 0, 0, 1, 0, 0},		/* PC10 FCC2_RXD3 */
+	 {0, 0, 0, 1, 0, 1},		/* PC9  LTMODE */
+	 {0, 0, 0, 1, 0, 1},		/* PC8  SELSYNC */
+	 {0, 1, 1, 0, 0, 0},		/* PC7  FCC1_TXADDR2 SLAVE  */
+	 {0, 1, 1, 0, 0, 0},		/* PC6  FCC1_RXADDR2 SLAVE */
+	 {0, 0, 0, 1, 0, 0},		/* PC5  FCC2_TXCLAV MASTER */
+	 {0, 0, 0, 1, 0, 0},		/* PC4  FCC2_RXENB MASTER */
+	 {0, 0, 0, 1, 0, 0},		/* PC3  FCC2_TXD2 */
+	 {0, 0, 0, 1, 0, 0},		/* PC2  FCC2_TXD3 */
+	 {0, 0, 0, 0, 0, 1},		/* PC1  PTMC -PTEENB */
+	 {0, 0, 0, 1, 0, 1},		/* PC0  COMCLK_N */
+	 },
+	/* Port D configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 0, 0, 1, 0, 1},		/* PD31 -CAM_RST */
+	 {0, 0, 0, 1, 0, 0},		/* PD30 FCC2_TXENB */
+	 {0, 1, 1, 0, 0, 0},		/* PD29 FCC1_RXADDR3 SLAVE */
+	 {0, 1, 1, 0, 0, 1},		/* PD28 TDMC1_L1TXD */
+	 {0, 1, 1, 0, 0, 0},		/* PD27 TDMC1_L1RXD */
+	 {0, 1, 1, 0, 0, 1},		/* PD26 TDMC1_L1RSYNC */
+	 {0, 0, 0, 1, 0, 1},		/* PD25 LED0 -OFF */
+	 {0, 0, 0, 1, 0, 1},		/* PD24 LED5 -OFF */
+	 {1, 0, 0, 1, 0, 1},		/* PD23 -LXT971_RST */
+	 {0, 1, 1, 0, 0, 1},		/* PD22 TDMA2_L1TXD */
+	 {0, 1, 1, 0, 0, 0},		/* PD21 TDMA2_L1RXD */
+	 {0, 1, 1, 0, 0, 1},		/* PD20 TDMA2_L1RSYNC */
+	 {0, 0, 0, 1, 0, 0},		/* PD19 FCC2_TXADDR3 */
+	 {0, 0, 0, 1, 0, 0},		/* PD18 FCC2_RXADDR3 */
+	 {0, 1, 0, 1, 0, 0},		/* PD17 BRG2 */
+	 {0, 0, 0, 1, 0, 0},		/* PD16  */
+	 {0, 0, 0, 1, 0, 0},		/* PD15 PT2TO1 */
+	 {0, 0, 0, 1, 0, 1},		/* PD14 PT4TO3 */
+	 {0, 0, 0, 1, 0, 1},		/* PD13 -SWMODE */
+	 {0, 0, 0, 1, 0, 1},		/* PD12 -PTMODE */
+	 {0, 0, 0, 1, 0, 0},		/* PD11 FCC2_RXD0 */
+	 {0, 0, 0, 1, 0, 0},		/* PD10 FCC2_RXD1 */
+	 {1, 1, 0, 1, 0, 1},		/* PD9  SMC1_SMTXD */
+	 {1, 1, 0, 0, 0, 1},		/* PD8  SMC1_SMRXD */
+	 {0, 1, 1, 0, 0, 0},		/* PD7  FCC1_TXADDR3 SLAVE */
+	 {0, 0, 0, 1, 0, 0},		/* PD6  IMAMODE */
+	 {0, 0, 0, 0, 0, 0},		/* PD5  CONFIG2 */
+	 {0, 1, 0, 1, 0, 0},		/* PD4  BRG8 */
+	 {0, 0, 0, 0, 0, 0},		/* PD3  */
+	 {0, 0, 0, 0, 0, 0},		/* PD2  */
+	 {0, 0, 0, 0, 0, 0},		/* PD1  */
+	 {0, 0, 0, 0, 0, 0},		/* PD0  */
+	 }
+};
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *base;
+	ulong maxsize;
+	int i;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	immap->im_siu_conf.sc_ppc_acr = 0x00000026;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_lcl_acr = 0x00000000;
+	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_tescr1 = 0x00004000;
+	immap->im_siu_conf.sc_ltescr1 = 0x00004000;
+
+	/* Init Main SDRAM */
+#define OP_VALUE   0x404A241A
+#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
+	base = (uchar *) CONFIG_SYS_SDRAM_BASE;
+	memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
+	*base = 0xFF;
+	memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_psdmr = 0x18000000 | OP_VALUE_M;
+	*(base + 0x110) = 0xFF;
+	memctl->memc_psdmr = OP_VALUE;
+	memctl->memc_lsdmr = 0x4086A522;
+	*base = 0xFF;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
+
+	maxsize = get_ram_size((long *)base, maxsize);
+
+	memctl->memc_or1 |= ~(maxsize - 1);
+
+	if (maxsize != hwc_main_sdram_size ())
+		printf ("Oops: memory test has not found all memory!\n");
+#endif
+
+	icache_enable ();
+	/* return total ram size of SDRAM */
+	return (maxsize);
+}
+
+int checkboard (void)
+{
+	char string[32];
+
+	hwc_manufact_date (string);
+
+	printf ("Board: Interphase 4539 (#%d %s)\n",
+		hwc_serial_number (),
+		string);
+
+#ifdef DEBUG
+	printf ("Manufacturing date: %s\n", string);
+	printf ("Serial number     : %d\n", hwc_serial_number ());
+	printf ("FLASH size        : %d MB\n", hwc_flash_size () >> 20);
+	printf ("Main SDRAM size   : %d MB\n", hwc_main_sdram_size () >> 20);
+	printf ("Local SDRAM size  : %d MB\n", hwc_local_sdram_size () >> 20);
+	hwc_mac_address (string);
+	printf ("MAC address       : %s\n", string);
+#endif
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	char *s, str[32];
+	int num;
+
+	if ((s = getenv ("serial#")) == NULL &&
+		(num = hwc_serial_number ()) != -1) {
+		sprintf (str, "%06d", num);
+		setenv ("serial#", str);
+	}
+	if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) {
+		setenv ("ethaddr", str);
+	}
+	return (0);
+}
+
+/***************************************************************
+ * We take some basic Hardware Configuration Parameter from the
+ * Serial EEPROM conected to the PSpan bridge. We keep it as
+ * simple as possible.
+ */
+int hwc_flash_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte >> 2) & 0x3) {
+		case 0x1:
+			return 0x0400000;
+			break;
+		case 0x2:
+			return 0x0800000;
+			break;
+		case 0x3:
+			return 0x1000000;
+		default:
+			return 0x0100000;
+		}
+	}
+	return -1;
+}
+int hwc_local_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte & 0x03)) {
+		case 0x1:
+			return 0x0800000;
+		case 0x2:
+			return 0x1000000;
+		default:
+			return 0;			/* not present */
+		}
+	}
+	return -1;
+}
+int hwc_main_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
+		return 0x1000000 << ((byte >> 5) & 0x7);
+	}
+	return -1;
+}
+int hwc_serial_number (void)
+{
+	int sn = -1;
+
+	if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
+		sn = cpu_to_le32 (sn);
+	}
+	return sn;
+}
+int hwc_mac_address (char *str)
+{
+	char mac[6];
+
+	if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
+		sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
+				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	} else {
+		strcpy (str, "ERROR");
+		return -1;
+	}
+	return 0;
+}
+int hwc_manufact_date (char *str)
+{
+	uchar byte;
+	int value;
+
+	if (seeprom_read (0x92, &byte, sizeof (byte)))
+		goto out;
+	value = byte;
+	if (seeprom_read (0x93, &byte, sizeof (byte)))
+		goto out;
+	value += byte << 8;
+	sprintf (str, "%02d/%02d/%04d",
+			 value & 0x1F, (value >> 5) & 0xF,
+			 1980 + ((value >> 9) & 0x1FF));
+	return 0;
+
+  out:
+	strcpy (str, "ERROR");
+	return -1;
+}
+
+#define PSPAN_ADDR      0xF0020000
+#define EEPROM_REG      0x408
+#define EEPROM_READ_CMD 0xA000
+#define PSPAN_WRITE(a,v) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
+#define PSPAN_READ(a) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
+
+int seeprom_read (int addr, uchar * data, int size)
+{
+	ulong val, cmd;
+	int i;
+
+	for (i = 0; i < size; i++) {
+
+		cmd = EEPROM_READ_CMD;
+		cmd |= ((addr + i) << 24) & 0xff000000;
+
+		/* Wait for ACT to authorize write */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Write command */
+		PSPAN_WRITE (EEPROM_REG, cmd);
+
+		/* Wait for data to be valid */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+		/* Do it twice, first read might be erratic */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Read error */
+		if (val & 0x00000040) {
+			return -1;
+		} else {
+			data[i] = (val >> 16) & 0xff;
+		}
+	}
+	return 0;
+}
diff --git a/u-boot/board/isee/igep0020/Makefile b/u-boot/board/isee/igep0020/Makefile
new file mode 100644
index 0000000..678a682
--- /dev/null
+++ b/u-boot/board/isee/igep0020/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= igep0020.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/isee/igep0020/config.mk b/u-boot/board/isee/igep0020/config.mk
new file mode 100644
index 0000000..7964621
--- /dev/null
+++ b/u-boot/board/isee/igep0020/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
+#
+# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/isee/igep0020/igep0020.c b/u-boot/board/isee/igep0020/igep0020.c
new file mode 100644
index 0000000..36cc924
--- /dev/null
+++ b/u-boot/board/isee/igep0020/igep0020.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0020.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPMC definitions for LAN9221 chips */
+static const u32 gpmc_lan_config[] = {
+    NET_LAN9221_GPMC_CONFIG1,
+    NET_LAN9221_GPMC_CONFIG2,
+    NET_LAN9221_GPMC_CONFIG3,
+    NET_LAN9221_GPMC_CONFIG4,
+    NET_LAN9221_GPMC_CONFIG5,
+    NET_LAN9221_GPMC_CONFIG6,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+			GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 64 as output pin and send a magic pulse through it */
+	if (!omap_request_gpio(64)) {
+		omap_set_gpio_direction(64, 0);
+		omap_set_gpio_dataout(64, 1);
+		udelay(1);
+		omap_set_gpio_dataout(64, 0);
+		udelay(1);
+		omap_set_gpio_dataout(64, 1);
+	}
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEFAULT();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/isee/igep0020/igep0020.h b/u-boot/board/isee/igep0020/igep0020.h
new file mode 100644
index 0000000..c08d758
--- /dev/null
+++ b/u-boot/board/isee/igep0020/igep0020.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0020_H_
+#define _IGEP0020_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"IGEP v2 board",
+	"ONENAND",
+};
+
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00080701
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x08030703
+#define NET_LAN9221_GPMC_CONFIG5    0x00060908
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+static void setup_net_chip(void);
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
+	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
+	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
+	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
+	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
+	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
+	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
+	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
+	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
+	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
+	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
+	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
+	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
+	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
+	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
+	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
+	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
+	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
+	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/u-boot/board/isee/igep0030/Makefile b/u-boot/board/isee/igep0030/Makefile
new file mode 100644
index 0000000..d208872
--- /dev/null
+++ b/u-boot/board/isee/igep0030/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= igep0030.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/isee/igep0030/config.mk b/u-boot/board/isee/igep0030/config.mk
new file mode 100644
index 0000000..059a878
--- /dev/null
+++ b/u-boot/board/isee/igep0030/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
+#
+# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/isee/igep0030/igep0030.c b/u-boot/board/isee/igep0030/igep0030.c
new file mode 100644
index 0000000..6a92735
--- /dev/null
+++ b/u-boot/board/isee/igep0030/igep0030.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0030.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_IGEP0030;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEFAULT();
+}
diff --git a/u-boot/board/isee/igep0030/igep0030.h b/u-boot/board/isee/igep0030/igep0030.h
new file mode 100644
index 0000000..b7ce5aa
--- /dev/null
+++ b/u-boot/board/isee/igep0030/igep0030.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0030_H_
+#define _IGEP0030_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 IGEP module",
+	"ONENAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEFAULT()\
+	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
+	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
+	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
+	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
+	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
+	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
+	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
+	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
+	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
+	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
+	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
+	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
+	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
+	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
+	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
+	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
+	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
+	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
+	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
+	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/u-boot/board/ispan/Makefile b/u-boot/board/ispan/Makefile
new file mode 100644
index 0000000..70205f1
--- /dev/null
+++ b/u-boot/board/ispan/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ispan/ispan.c b/u-boot/board/ispan/ispan.c
new file mode 100644
index 0000000..9254e0a
--- /dev/null
+++ b/u-boot/board/ispan/ispan.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Interphase iSPAN Communications Controllers
+ * (453x and others). Tested on 4532.
+ *
+ * Derived from iSPAN 4539 port (iphase4539) by
+ * Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/io.h>
+
+/*
+ * I/O Ports configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 SMTXD */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 SMRXD */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7 */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5 */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4 */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3 */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2 */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0 */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
+	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
+	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
+	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
+	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
+	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
+	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
+	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
+	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
+	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
+	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
+	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
+	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
+	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
+	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22 */
+	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21 */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19 */
+	/* PC18 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
+	/* PC16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8  */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7  */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6  */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5  */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4  */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3  */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2  */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1  */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }  /* PC0  */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31 */
+	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30 */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29 */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28 */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27 */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26 */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25 */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24 */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23 */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22 */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21 */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20 */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19 */
+	/* PD18 */ { 0,          1,   1,   0,   0,   0 }, /* SPICLK  */
+	/* PD17 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMOSI */
+	/* PD16 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMISO */
+	/* PD15 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SDA */
+	/* PD14 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SCL */
+	/* PD13 */ { 1,          0,   0,   0,   0,   0 }, /* MII MDIO */
+	/* PD12 */ { 1,          0,   0,   1,   0,   0 }, /* MII MDC  */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11 */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10 */
+	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 SMTXD */
+	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 SMRXD */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7 */
+	/* PD6  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
+	/* PD5  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4 */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    }
+};
+
+#define PSPAN_ADDR      0xF0020000
+#define EEPROM_REG      0x408
+#define EEPROM_READ_CMD 0xA000
+#define PSPAN_WRITE(a,v) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
+#define PSPAN_READ(a) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
+
+static int seeprom_read (int addr, uchar * data, int size)
+{
+	ulong val, cmd;
+	int i;
+
+	for (i = 0; i < size; i++) {
+
+		cmd = EEPROM_READ_CMD;
+		cmd |= ((addr + i) << 24) & 0xff000000;
+
+		/* Wait for ACT to authorize write */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Write command */
+		PSPAN_WRITE (EEPROM_REG, cmd);
+
+		/* Wait for data to be valid */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+		/* Do it twice, first read might be erratic */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Read error */
+		if (val & 0x00000040) {
+			return -1;
+		} else {
+			data[i] = (val >> 16) & 0xff;
+		}
+	}
+	return 0;
+}
+
+/***************************************************************
+ * We take some basic Hardware Configuration Parameter from the
+ * Serial EEPROM conected to the PSpan bridge. We keep it as
+ * simple as possible.
+ */
+#ifdef DEBUG
+static int hwc_flash_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte >> 2) & 0x3) {
+		case 0x1:
+			return 0x0400000;
+			break;
+		case 0x2:
+			return 0x0800000;
+			break;
+		case 0x3:
+			return 0x1000000;
+		default:
+			return 0x0100000;
+		}
+	}
+	return -1;
+}
+
+static int hwc_local_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte & 0x03)) {
+		case 0x1:
+			return 0x0800000;
+		case 0x2:
+			return 0x1000000;
+		default:
+			return 0;			/* not present */
+		}
+	}
+	return -1;
+}
+#endif	/* DEBUG */
+
+static int hwc_main_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
+		return 0x1000000 << ((byte >> 5) & 0x7);
+	}
+	return -1;
+}
+
+static int hwc_serial_number (void)
+{
+	int sn = -1;
+
+	if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
+		sn = cpu_to_le32 (sn);
+	}
+	return sn;
+}
+
+static int hwc_mac_address (char *str)
+{
+	char mac[6];
+
+	if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
+		sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
+				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	} else {
+		strcpy (str, "ERROR");
+		return -1;
+	}
+	return 0;
+}
+
+static int hwc_manufact_date (char *str)
+{
+	uchar byte;
+	int value;
+
+	if (seeprom_read (0x92, &byte, sizeof (byte)))
+		goto out;
+	value = byte;
+	if (seeprom_read (0x93, &byte, sizeof (byte)))
+		goto out;
+	value += byte << 8;
+	sprintf (str, "%02d/%02d/%04d",
+			 value & 0x1F, (value >> 5) & 0xF,
+			 1980 + ((value >> 9) & 0x1FF));
+	return 0;
+
+out:
+	strcpy (str, "ERROR");
+	return -1;
+}
+
+static int hwc_board_type (char **str)
+{
+	ushort id = 0;
+
+	if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
+		switch (id) {
+		case 0x9080:
+			*str = "4532-002";
+			break;
+		case 0x9081:
+			*str = "4532-001";
+			break;
+		case 0x9082:
+			*str = "4532-000";
+			break;
+		default:
+			*str = "Unknown";
+		}
+	} else {
+		*str = "Unknown";
+	}
+
+	return id;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long maxsize = hwc_main_sdram_size();
+
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *base;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x00000026;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_lcl_acr  = 0x00000000;
+	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+	immap->im_siu_conf.sc_ltescr1  = 0x00004000;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
+	memctl->memc_psrt  = CONFIG_SYS_PSRT;
+	memctl->memc_or1   = CONFIG_SYS_60x_OR;
+	memctl->memc_br1   = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
+
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
+	*base = 0xFF;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
+	*base = 0xFF;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
+
+	/* Initialise local bus SDRAM */
+	base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
+	memctl->memc_lsrt  = CONFIG_SYS_LSRT;
+	memctl->memc_or2   = CONFIG_SYS_LOC_OR;
+	memctl->memc_br2   = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
+
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
+	*base = 0xFF;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
+	*base = 0xFF;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
+
+	maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
+
+	memctl->memc_or1 |= ~(maxsize - 1);
+
+	if (maxsize != hwc_main_sdram_size())
+		puts("Oops: memory test has not found all memory!\n");
+#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
+
+	/* Return total RAM size (size of 60x SDRAM) */
+	return maxsize;
+}
+
+int checkboard(void)
+{
+	char string[32], *id;
+
+	hwc_manufact_date(string);
+	hwc_board_type(&id);
+	printf("Board: Interphase iSPAN %s (#%d %s)\n",
+	       id, hwc_serial_number(), string);
+#ifdef DEBUG
+	printf("Manufacturing date: %s\n", string);
+	printf("Serial number     : %d\n", hwc_serial_number());
+	printf("FLASH size        : %d MB\n", hwc_flash_size() >> 20);
+	printf("Main SDRAM size   : %d MB\n", hwc_main_sdram_size() >> 20);
+	printf("Local SDRAM size  : %d MB\n", hwc_local_sdram_size() >> 20);
+	hwc_mac_address(string);
+	printf("MAC address       : %s\n", string);
+#endif
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char *s, str[32];
+	int num;
+
+	if ((s = getenv("serial#")) == NULL &&
+	    (num = hwc_serial_number()) != -1) {
+		sprintf(str, "%06d", num);
+		setenv("serial#", str);
+	}
+	if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
+		setenv("ethaddr", str);
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/ivm/Makefile b/u-boot/board/ivm/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/ivm/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ivm/flash.c b/u-boot/board/ivm/flash.c
new file mode 100644
index 0000000..cf309d7
--- /dev/null
+++ b/u-boot/board/ivm/flash.c
@@ -0,0 +1,598 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
+				BR_MS_GPCM | BR_PS_16 | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_MT:
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00020000);
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	    }
+	    return;
+
+	case FLASH_MAN_SST:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + (i * 0x00002000);
+	    }
+	    return;
+
+	case FLASH_MAN_AMD:
+	case FLASH_MAN_FUJ:
+
+	    /* set up sector start address table */
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	    }
+	    return;
+	default:
+	    printf ("Don't know sector ofsets for flash type 0x%lx\n",
+		info->flash_id);
+	    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_SST200A:	printf ("39xF200A (2M = 128K x 16)\n");
+				break;
+	case FLASH_SST400A:	printf ("39xF400A (4M = 256K x 16)\n");
+				break;
+	case FLASH_SST800A:	printf ("39xF800A (8M = 512K x 16)\n");
+				break;
+	case FLASH_STM800AB:	printf ("M29W800AB (8M = 512K x 16)\n");
+				break;
+	case FLASH_28F008S5:	printf ("28F008S5 (1M = 64K x 16)\n");
+				break;
+	case FLASH_28F400_T:	printf ("28F400B3 (4Mbit, top boot sector)\n");
+				break;
+	case FLASH_28F400_B:	printf ("28F400B3 (4Mbit, bottom boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	ushort value;
+	vu_short *saddr = (vu_short *)addr;
+
+	/* Read Manufacturer ID */
+	saddr[0] = 0x0090;
+	value = saddr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (SST_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (STM_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (MT_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_MT;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		saddr[0] = 0x00FF;		/* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = saddr[1];			/* device ID		*/
+
+	switch (value) {
+	case (AMD_ID_LV400T & 0xFFFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & 0xFFFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & 0xFFFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & 0xFFFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160T & 0xFFFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & 0xFFFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFFFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & 0xFFFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	case (SST_ID_xF200A & 0xFFFF):
+		info->flash_id += FLASH_SST200A;
+		info->sector_count = 64;	/* 39xF200A ID ( 2M = 128K x 16	) */
+		info->size = 0x00080000;
+		break;
+	case (SST_ID_xF400A & 0xFFFF):
+		info->flash_id += FLASH_SST400A;
+		info->sector_count = 128;	/* 39xF400A ID ( 4M = 256K x 16	) */
+		info->size = 0x00100000;
+		break;
+	case (SST_ID_xF800A & 0xFFFF):
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 256;	/* 39xF800A ID ( 8M = 512K x 16	) */
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (STM_ID_x800AB & 0xFFFF):
+		info->flash_id += FLASH_STM800AB;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (MT_ID_28F400_T & 0xFFFF):
+		info->flash_id += FLASH_28F400_T;
+		info->sector_count = 7;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+	case (MT_ID_28F400_B & 0xFFFF):
+		info->flash_id += FLASH_28F400_B;
+		info->sector_count = 7;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		saddr[0] = 0x00FF;		/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	saddr[0] = 0x00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) {
+		printf ("Can erase only MT flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *)(info->start[sect]);
+			unsigned short status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = 0x0050;	/* clear status register */
+			*addr = 0x0020;	/* erase setup */
+			*addr = 0x00D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & 0x0080) != 0x0080) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00FF;	/* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = 0x00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	2	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short *)dest;
+	ushort sdata = (ushort)data;
+	ushort status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & sdata) != sdata) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = 0x0040;		/* write setup */
+	*addr = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & 0x0080) != 0x0080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = 0x00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0x00FF;		/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/ivm/ivm.c b/u-boot/board/ivm/ivm.c
new file mode 100644
index 0000000..9bec198
--- /dev/null
+++ b/u-boot/board/ivm/ivm.c
@@ -0,0 +1,352 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+#ifdef CONFIG_STATUS_LED
+# include <status_led.h>
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*
+ * 50 MHz SHARC access using UPM A
+ */
+const uint sharc_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+/*
+ * 50 MHz SDRAM access using UPM B
+ */
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45,	/* last */
+	_NOT_USED_,
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
+	0xE1BBBC04, 0x1FF77C45,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
+	0xFFFFFC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+#ifdef CONFIG_IVMS8
+	puts ("Board: IVMS8\n");
+#endif
+#ifdef CONFIG_IVML24
+	puts ("Board: IVM-L8/24\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	long int size_b0;
+
+	/* enable SDRAM clock ("switch on" SDRAM) */
+	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE);	/* active output */
+	immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE;	/* output */
+	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE;	/* assert SDRAM CLKE */
+	udelay (1);
+
+	/*
+	 * Map controller bank 1 for ELIC SACCO
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
+
+	/*
+	 * Map controller bank 2 for ELIC EPIC
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
+
+	/*
+	 * Configure UPMA for SHARC
+	 */
+	upmconfig (UPMA, (uint *) sharc_table,
+		   sizeof (sharc_table) / sizeof (uint));
+
+#if defined(CONFIG_IVML24)
+	/*
+	 * Map controller bank 4 for HDLC Address space
+	 */
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
+#endif
+
+	/*
+	 * Map controller bank 5 for SHARC
+	 */
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
+
+	memctl->memc_mamr = 0x00001000;
+
+	/*
+	 * Configure UPMB for SDRAM
+	 */
+	upmconfig (UPMB, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;	/* refresh not enabled yet */
+
+	udelay (200);
+	memctl->memc_mcr = 0x80806105;	/* precharge */
+	udelay (1);
+	memctl->memc_mcr = 0x80806106;	/* load mode register */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+
+	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+	size_b0 =
+		dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	memctl->memc_mbmr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy (void)
+{
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* De-assert Ethernet Powerdown */
+	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* active output */
+	immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN;	/* output */
+	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* Enable PHY power */
+	udelay (1000);
+
+	/*
+	 * RESET is implemented by a positive pulse of at least 1 us
+	 * at the reset pin.
+	 *
+	 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
+	 *
+	 * Note: The RESET pin is high active, but there is an
+	 *       inverter on the SPD823TS board...
+	 */
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
+	/* assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
+	udelay (10);
+	/* de-assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
+	udelay (10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void show_boot_progress (int status)
+{
+#if defined(CONFIG_STATUS_LED)
+# if defined(STATUS_LED_YELLOW)
+	status_led_set (STATUS_LED_YELLOW,
+			(status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
+# endif	/* STATUS_LED_YELLOW */
+# if defined(STATUS_LED_BOOT)
+	if (status == 6)
+		status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+# endif	/* STATUS_LED_BOOT */
+#endif /* CONFIG_STATUS_LED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void ide_set_reset (int on)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/*
+	 * Configure PC for IDE Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+	} else {		/* release RESET */
+		immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
+	}
+
+	/* program port pin as GPIO output */
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/ivm/u-boot.lds b/u-boot/board/ivm/u-boot.lds
new file mode 100644
index 0000000..f4c6c98
--- /dev/null
+++ b/u-boot/board/ivm/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ivm/u-boot.lds.debug b/u-boot/board/ivm/u-boot.lds.debug
new file mode 100644
index 0000000..6bcf167
--- /dev/null
+++ b/u-boot/board/ivm/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ixdp425/Makefile b/u-boot/board/ixdp425/Makefile
new file mode 100644
index 0000000..4ba0383
--- /dev/null
+++ b/u-boot/board/ixdp425/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ixdp425.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ixdp425/config.mk b/u-boot/board/ixdp425/config.mk
new file mode 100644
index 0000000..509c894
--- /dev/null
+++ b/u-boot/board/ixdp425/config.mk
@@ -0,0 +1,2 @@
+#
+CONFIG_SYS_TEXT_BASE = 0x00f80000
diff --git a/u-boot/board/ixdp425/flash.c b/u-boot/board/ixdp425/flash.c
new file mode 100644
index 0000000..f1d9190
--- /dev/null
+++ b/u-boot/board/ixdp425/flash.c
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			x
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb()	__asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/ixdp425/ixdp425.c b/u-boot/board/ixdp425/ixdp425.c
new file mode 100644
index 0000000..43ac8f6
--- /dev/null
+++ b/u-boot/board/ixdp425/ixdp425.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/arch/ixp425.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init (void)
+{
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+#ifdef CONFIG_IXDPG425
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
+
+	/*
+	 * Get realtek RTL8305 switch and SLIC out of reset
+	 */
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SWITCH_RESET_N);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SWITCH_RESET_N);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);
+
+	/*
+	 * Setup GPIO's for PCI INTA & INTB
+	 */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);
+
+	/*
+	 * Setup GPIO's for 33MHz clock output
+	 */
+	*IXP425_GPIO_GPCLKR = 0x01FF01FF;
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+#endif
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+#ifdef CONFIG_IXDPG425
+	puts("Board: IXDPG425 - Intel Network Gateway Reference Platform");
+#else
+	puts("Board: IXDP425 - Intel Development Platform");
+#endif
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+extern struct pci_controller hose;
+extern void pci_ixp_init(struct pci_controller * hose);
+
+void pci_init_board(void)
+{
+	extern void pci_ixp_init (struct pci_controller *hose);
+
+	pci_ixp_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/jornada/Makefile b/u-boot/board/jornada/Makefile
new file mode 100644
index 0000000..e017692
--- /dev/null
+++ b/u-boot/board/jornada/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2004 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= jornada.o
+SOBJS	:= setup.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/jornada/jornada.c b/u-boot/board/jornada/jornada.c
new file mode 100644
index 0000000..fab1068
--- /dev/null
+++ b/u-boot/board/jornada/jornada.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
+	gd->bd->bi_boot_params = 0xc0000100;
+
+
+	/*
+	 * Turn on flashing.
+	 * Would be nice to have some protection but
+	 * that would have to be implemented in the
+	 * flash init function, which isnt possible yet.
+	 */
+	PPSR |= (1 << 7);
+	PPDR |= (1 << 7);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}
diff --git a/u-boot/board/jornada/setup.S b/u-boot/board/jornada/setup.S
new file mode 100644
index 0000000..cdf5f54
--- /dev/null
+++ b/u-boot/board/jornada/setup.S
@@ -0,0 +1,210 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04
+#define MDCAS01		0x08
+#define MDCAS02		0x0C
+#define MSC0		0x10
+#define MSC1		0x14
+#define MECR		0x18
+#define MDREFR		0x1C
+#define MDCAS20		0x20
+#define MDCAS21		0x24
+#define MDCAS22		0x28
+#define MSC2		0x2C
+#define SMCNFG		0x30
+
+#define GPDR	0x04
+#define GPSR	0x08
+#define GPCR	0x0C
+#define GAFR	0x1C
+
+#define PPDR	0x00
+#define PPSR	0x04
+#define PPAR	0x08
+
+#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
+#define MDREFR_DRI(n_)   ((n_ & (0x00000fff)) << 4)
+#define MDREFR_K0DB2 (1 << 18)
+#define MDREFR_K1DB2 (1 << 22)
+#define MDREFR_K2DB2 (1 << 26)
+
+#define MDREFR_K0RUN (1 << 17)
+#define MDREFR_K1RUN (1 << 21)
+#define MDREFR_K2RUN (1 << 25)
+
+#define MDREFR_SLFRSH (1 << 31)
+#define MDREFR_E1PIN  (1 << 20)
+
+#define PSSR    0x04
+#define PSSR_DH 0x00000008
+#define POSR    0x08
+#define RCSR    0x04
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+PWR_BASE:	.word	0x90020000
+RST_BASE:	.long	0x90030000
+PPC_BASE:	.long	0x90060000
+GPIO_BASE:	.long	0x90040000
+IC_BASE:	.word	0x90050000
+
+cpuspeed:	.word	0xa0
+/* calculated from old blob bootloader */
+mdcnfg:	.long	0x00037267	/* mdcnfg  0x00037267 */
+mdcas00:	.long	0x5555557f	/* mdcas00 0x5555557f */
+mdcas01:	.long	0x55555555	/* mdcas01 0x55555555 */
+mdcas02:	.long	0x55555555	/* mdcas02 0x55555555 */
+msc0:	.long	0xfff04f78		/* msc0    0xfff04f78 */
+msc1:	.long	0xfff8fff0		/* msc1    0xfff8fff0 */
+mecr:	.long	0x98c698c6	/* mecr    0x98c698c6 */
+mdrefr:	.long	0x067600c7	/* mdrefr  0x04340327 */
+mdcas20:	.long	0xd1284142	/* mdcas20 0xd1284142 */
+mdcas21:	.long	0x72249529	/* mdcas21 0x72249529 */
+mdcas22:	.long	0x78414351	/* mdcas22 0x78414351 */
+msc2:	.long	0x201d2959		/* msc2    0x201d2959 */
+smcnfg:	.long	0x00000000	/* smcnfg  0x00000000 */
+
+pin_set_out:	.long	0x37ff70
+pin_set_dir:	.long	0x11480
+
+gpdr_set:	.long	0x0B3A0900
+gpsr_set:	.long	0x02100800
+gpcr_set:	.long	0x092A0100
+gafr_set:	.long	0x08600000
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+	/* this is required for flashing */
+	ldr	r0, PPC_BASE
+	ldr	r1, pin_set_out
+	str	r1, [r0, #PPSR]
+	ldr	r1, pin_set_dir
+	str	r1, [r0, #PPDR]
+
+	/* Setting up the memory and stuff */
+	/***********************************/
+
+	ldr	r0, MEM_BASE
+
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+
+	/* clear kxDB2 */
+	ldr	r2, [r0, #MDREFR]
+	bic	r2, r2, #MDREFR_K0DB2
+	bic	r2, r2, #MDREFR_K1DB2
+	bic	r2, r2, #MDREFR_K2DB2
+	str	r2, [r0, #MDREFR]
+
+	ldr	r2, [r0, #MDREFR]
+	orr r2, r2, #MDREFR_TRASR(7)
+
+	mov r4, #0x2000
+	spin:	subs	r4, r4, #1
+	bne	spin
+
+	ldr	r1, PWR_BASE
+	mov	r2, #PSSR_DH
+	str	r2, [r1, #PSSR]
+
+	ldr	r2, [r0, #MDREFR]
+	bic	r2, r2, #MDREFR_K0DB2
+	bic	r2, r2, #MDREFR_K1DB2
+	bic	r2, r2, #MDREFR_K2DB2
+	str	r2, [r0, #MDREFR]
+
+	ldr	r2, [r0, #MDREFR]
+	orr	r2, r2, #MDREFR_TRASR(7)
+	orr	r2, r2, #MDREFR_DRI(12)
+	orr	r2, r2, #MDREFR_K0DB2
+	orr	r2, r2, #MDREFR_K1DB2
+	orr	r2, r2, #MDREFR_K2DB2
+	str	r2, [r0, #MDREFR]
+
+	ldr	r2, [r0, #MDREFR]
+	orr	r2, r2, #MDREFR_K0RUN
+	orr	r2, r2, #MDREFR_K1RUN
+	orr	r2, r2, #MDREFR_K2RUN
+	str	r2, [r0, #MDREFR]
+
+	ldr	r2, [r0, #MDREFR]
+	bic	r2, r2, #MDREFR_SLFRSH
+	str	r2, [r0, #MDREFR]
+
+	ldr	r2, [r0, #MDREFR]
+	orr	r2, r2, #MDREFR_E1PIN
+	str	r2, [r0, #MDREFR]
+
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r3, [r2]
+.endr
+
+	ldr	r2, [r0, #MDCNFG]
+	orr	r2, r2, #0x00000003
+	orr	r2, r2, #0x00030000
+	str	r2, [r0, #MDCNFG]
+
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	mov	pc, lr
diff --git a/u-boot/board/jornada/u-boot.lds b/u-boot/board/jornada/u-boot.lds
new file mode 100644
index 0000000..de6101e
--- /dev/null
+++ b/u-boot/board/jornada/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/u-boot/board/jse/Makefile b/u-boot/board/jse/Makefile
new file mode 100644
index 0000000..a3050c7
--- /dev/null
+++ b/u-boot/board/jse/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2004 Picture Elements, Inc.
+# Stephen Williams <steve@icarus.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o sdram.o flash.o host_bridge.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/jse/README.txt b/u-boot/board/jse/README.txt
new file mode 100644
index 0000000..84497db
--- /dev/null
+++ b/u-boot/board/jse/README.txt
@@ -0,0 +1,48 @@
+JSE Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Memory Bank 1 -- SystemACE Controller
+-------------------------------------
+
+0xf0000000 - 0xf00fffff
+
+The SystemACE chip is along on peripheral bank CS#1. We don't need
+much space, but 1Meg is the smallest we can configure the chip to
+allocate. We need it far away from the flash region, because this
+region is set to be non-cached.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+SDRAM
+-----
+
+0x00000000 - 0x07ffffff  (128 MBytes)
diff --git a/u-boot/board/jse/flash.c b/u-boot/board/jse/flash.c
new file mode 100644
index 0000000..5735f19
--- /dev/null
+++ b/u-boot/board/jse/flash.c
@@ -0,0 +1,520 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#if CONFIG_SYS_MAX_FLASH_BANKS != 1
+#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+
+	/* Init: no FLASHes known */
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	/* Setup offsets */
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM,
+			      FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+			      &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+/*
+ * This implementation assumes that the flash chips are uniform sector
+ * devices. This is true for all likely JSE devices.
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	unsigned idx;
+	unsigned long sector_size = info->size / info->sector_count;
+
+	for (idx = 0; idx < info->sector_count; idx += 1) {
+		info->start[idx] = base + (idx * sector_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("ST Micro ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	  /* (Reduced table of only parts expected in JSE boards.) */
+	switch (info->flash_id) {
+	case FLASH_MAN_AMD | FLASH_AM040:
+		printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_MAN_STM | FLASH_AM040:
+		printf ("MM29W040W (512 Kbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		printf("Unknown flash manufacturer code: 0x%x\n", value);
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID		*/
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 512 ko */
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	  /* Calculate the sector offsets (Use JSE Optimized code). */
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf ("Erasing sector %p\n", addr2);	/* CLH */
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7 (info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	    (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/jse/host_bridge.c b/u-boot/board/jse/host_bridge.c
new file mode 100644
index 0000000..363be97
--- /dev/null
+++ b/u-boot/board/jse/host_bridge.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id:$"
+
+# include  <common.h>
+# include  <pci.h>
+# include  "jse_priv.h"
+
+/*
+ * The JSE board has an Intel 21555 non-transparent bridge for
+ * communication with the host. We need to render it harmless on the
+ * JSE side, but leave it alone on the host (primary) side. Normally,
+ * this will all be done before the host BIOS can gain access to the
+ * board, due to the Primary Access Lockout bit.
+ *
+ * The host_bridge_init function is called as a late initialization
+ * function, after most of the board is set up, including a PCI scan.
+ */
+
+void host_bridge_init (void)
+{
+	/* The bridge chip is at a fixed location. */
+	pci_dev_t dev = PCI_BDF (0, 10, 0);
+
+	/* Set PCI Class code --
+	   The primary side sees this class code at 0x08 in the
+	   primary config space. This must be something other then a
+	   bridge, or MS Windows starts doing weird stuff to me. */
+	pci_write_config_dword (dev, 0x48, 0x04800000);
+
+	/* Set subsystem ID --
+	   The primary side sees this value at 0x2c. We set it here so
+	   that the host can tell what sort of device this is:
+	   We are a Picture Elements [0x12c5] JSE [0x008a]. */
+	pci_write_config_dword (dev, 0x6c, 0x008a12c5);
+
+	/* Downstream (Primary-to-Secondary) BARs are set up mostly
+	   off. We need only the Memory-0 Bar so that the host can get
+	   at the CSR region to set up tables and the lot. */
+
+	/* Downstream Memory 0 setup (4K for CSR) */
+	pci_write_config_dword (dev, 0xac, 0xfffff000);
+	/* Downstream Memory 1 setup (off) */
+	pci_write_config_dword (dev, 0xb0, 0x00000000);
+	/* Downstream Memory 2 setup (off) */
+	pci_write_config_dword (dev, 0xb4, 0x00000000);
+	/* Downstream Memory 3 setup (off) */
+	pci_write_config_dword (dev, 0xb8, 0x00000000);
+
+	/* Upstream (Secondary-to-Primary) BARs are used to get at
+	   host memory from the JSE card. Create two regions: a small
+	   one to manage individual word reads/writes, and a larger
+	   one for doing bulk frame moves. */
+
+	/* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
+	pci_write_config_dword (dev, 0xc4, 0xfffff000);
+	/* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
+	pci_write_config_dword (dev, 0xc8, 0xfffff000);
+
+	/* Upstream Memory 2 (BAR4) uses page translation, and is set
+	   up in CCR1. Configure for 4K pages. */
+
+	/* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
+	   bit as well, so we are done configuring after this
+	   point. Therefore, this must be the last step.
+
+	   CC1[15:12]= 0  (disable I2O message unit)
+	   CC1[11:8] = 0x5 (4K page size)
+	   CC0[11]   = 1  (Secondary Clock Disable: disable clock)
+	   CC0[10]   = 0  (Primary Access Lockout: allow primary access)
+	 */
+	pci_write_config_dword (dev, 0xcc, 0x05000800);
+}
diff --git a/u-boot/board/jse/init.S b/u-boot/board/jse/init.S
new file mode 100644
index 0000000..bccc7e0
--- /dev/null
+++ b/u-boot/board/jse/init.S
@@ -0,0 +1,97 @@
+/*------------------------------------------------------------------------+ */
+/* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------- */
+
+/*------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*                                    */
+/*                                    */
+/* The layout for the PEI JSE board:  */
+/*	Bank 0 - Flash and SRAM       */
+/*	Bank 1 - SystemACE            */
+/*	Bank 2 - not used             */
+/*	Bank 3 - not used             */
+/*	Bank 4 - not used             */
+/*	Bank 5 - not used             */
+/*	Bank 6 - not used             */
+/*	Bank 7 - not used             */
+/*------------------------------------------------------------------------- */
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	/*----------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing */
+	/* bank 0 timings. 200usec should be enough. */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*----------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+	/*----------------------------------------------------------------- */
+	/* Memory Bank 0 (Flash) initialization */
+	/*----------------------------------------------------------------- */
+
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,0x9B01
+	ori     r4,r4,0x5480
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,0xFFF1           /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   EBC0_CFGDATA,r4
+
+	blr
diff --git a/u-boot/board/jse/jse.c b/u-boot/board/jse/jse.c
new file mode 100644
index 0000000..f5c52c9
--- /dev/null
+++ b/u-boot/board/jse/jse.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+# include  <common.h>
+# include  <asm/ppc4xx.h>
+# include  <asm/processor.h>
+# include  <asm/io.h>
+# include  "jse_priv.h"
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+int board_early_init_f (void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the JSE board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED/UNUSED
+   |       IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
+   |       IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
+   |       IRQ 31 (EXT IRQ 6) (unused)
+   +-------------------------------------------------------------------------*/
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF87);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/* Configure the interface to the SystemACE MCU port.
+	   The SystemACE is fast, but there is no reason to have
+	   excessivly tight timings. So the settings are slightly
+	   generous. */
+
+	/* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
+	   WBN=0, WBF=1, TH=0,  RE=0,  SOR=0, BEM=0, PEN=0 */
+	mtdcr (EBC0_CFGADDR, PB1AP);
+	mtdcr (EBC0_CFGDATA, 0x01011000);
+
+	/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
+	mtdcr (EBC0_CFGADDR, PB1CR);
+	mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
+
+	/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
+	/* CPC0_CR1 |= PCIPW */
+	mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+	return board_early_init_f ();
+}
+
+#endif
+
+/*
+ * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
+ * also in the init_sequence array) but later. Many more things are
+ * configured, but we are still running from flash.
+ */
+int checkboard (void)
+{
+	unsigned vers, status;
+
+	/* check that the SystemACE chip is alive. */
+	printf ("ACE:   ");
+	vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
+	printf ("SystemACE %u.%u (build %u)",
+		(vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
+
+	status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
+#ifdef DEBUG
+	printf (" STATUS=0x%08x", status);
+#endif
+	/* If the flash card is present and there is an initial error,
+	   then force a restart of the program. */
+	if (status & 0x00000010) {
+		printf (" CFDETECT");
+
+		if (status & 0x04) {
+			/* CONTROLREG = CFGPROG */
+			writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+			udelay (500);
+			/* CONTROLREG = CFGRESET */
+			writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+			udelay (500);
+			writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+			/* CONTROLREG = CFGSTART */
+			writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+
+			status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
+		}
+	}
+
+	/* Wait for the SystemACE to program its chain of devices. */
+	while ((status & 0x84) == 0x00) {
+		udelay (500);
+		status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
+	}
+
+	if (status & 0x04)
+		printf (" CFG-ERROR");
+	if (status & 0x80)
+		printf (" CFGDONE");
+
+	printf ("\n");
+
+	/* Force /RTS to active. The board it not wired quite
+	   correctly to use cts/rtc flow control, so just force the
+	   /RST active and forget about it. */
+	writeb (readb (0xef600404) | 0x03, 0xef600404);
+
+	printf ("JSE:   ready\n");
+
+	return 0;
+}
+
+/* **** No more functions called by board_init_f. **** */
+
+/*
+ * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
+ * point, basic setup is done, U-Boot has been moved into SDRAM and
+ * PCI has been set up. From here we done late setup.
+ */
+int misc_init_r (void)
+{
+	host_bridge_init ();
+	return 0;
+}
diff --git a/u-boot/board/jse/jse_priv.h b/u-boot/board/jse/jse_priv.h
new file mode 100644
index 0000000..ed4894b
--- /dev/null
+++ b/u-boot/board/jse/jse_priv.h
@@ -0,0 +1,25 @@
+#ifndef __jse_priv_H
+#define __jse_prov_H
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+extern void host_bridge_init(void);
+
+#endif
diff --git a/u-boot/board/jse/sdram.c b/u-boot/board/jse/sdram.c
new file mode 100644
index 0000000..8ce8798
--- /dev/null
+++ b/u-boot/board/jse/sdram.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+# define SDRAM_LEN 0x08000000
+
+/*
+ * this is even after checkboard. It returns the size of the SDRAM
+ * that we have installed. This function is called by board_init_f
+ * in arch/powerpc/lib/board.c to initialize the memory and return what I
+ * found.
+ */
+phys_size_t initdram (int board_type)
+{
+	/* Configure the SDRAMS */
+
+	/* disable memory controller */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+	udelay (500);
+
+	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
+	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
+
+	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
+	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
+
+	/* Clear SDRAM0_ECCCFG (disable ECC) */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
+	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
+
+	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	mtdcr (SDRAM0_CFGDATA, 0x010a4016);
+
+	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	mtdcr (SDRAM0_CFGDATA, 0x00084001);
+
+	/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	mtdcr (SDRAM0_CFGDATA, 0x04084001);
+
+	/* Memory Bank 2 Config ==  BE=0 */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+	/* Memory Bank 3 Config ==  BE=0 */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+	/* refresh timer = 0x400  */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	mtdcr (SDRAM0_CFGDATA, 0x04000000);
+
+	/* Power management idle timer set to the default. */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
+	mtdcr (SDRAM0_CFGDATA, 0x07c00000);
+
+	udelay (500);
+
+	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	mtdcr (SDRAM0_CFGDATA, 0x80e00000);
+
+	return SDRAM_LEN;
+}
+
+/*
+ * The U-Boot core, as part of the initialization to prepare for
+ * loading the monitor into SDRAM, requests of this function that the
+ * memory be tested. Return 0 if the memory tests OK.
+ */
+int testdram (void)
+{
+	unsigned long idx;
+	unsigned val;
+	unsigned errors;
+	volatile unsigned long *sdram;
+
+#ifdef DEBUG
+	printf ("SDRAM Controller Registers --\n");
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	val = mfdcr (SDRAM0_CFGDATA);
+	printf ("    SDRAM0_CFG   : 0x%08x\n", val);
+
+	mtdcr (SDRAM0_CFGADDR, 0x24);
+	val = mfdcr (SDRAM0_CFGDATA);
+	printf ("    SDRAM0_STATUS: 0x%08x\n", val);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	val = mfdcr (SDRAM0_CFGDATA);
+	printf ("    SDRAM0_B0CR  : 0x%08x\n", val);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	val = mfdcr (SDRAM0_CFGDATA);
+	printf ("    SDRAM0_B1CR  : 0x%08x\n", val);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	val = mfdcr (SDRAM0_CFGDATA);
+	printf ("    SDRAM0_TR    : 0x%08x\n", val);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	val = mfdcr (SDRAM0_CFGDATA);
+	printf ("    SDRAM0_RTR   : 0x%08x\n", val);
+#endif
+
+	/* Wait for memory to be ready by testing MRSCMPbit
+	   bit. Really, there should already have been plenty of time,
+	   given it was started long ago. But, best to check. */
+	for (idx = 0; idx < 1000000; idx += 1) {
+		mtdcr (SDRAM0_CFGADDR, 0x24);
+		val = mfdcr (SDRAM0_CFGDATA);
+		if (val & 0x80000000)
+			break;
+	}
+
+	if (!(val & 0x80000000)) {
+		printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
+		return 1;
+	}
+
+	/* Start memory test. */
+	printf ("test: %u MB - ", SDRAM_LEN / 1048576);
+
+	sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
+
+	printf ("write - ");
+	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+		sdram[idx + 0] = idx;
+		sdram[idx + 1] = ~idx;
+	}
+
+	printf ("read - ");
+	errors = 0;
+	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+		if (sdram[idx + 0] != idx)
+			errors += 1;
+		if (sdram[idx + 1] != ~idx)
+			errors += 1;
+		if (errors > 0)
+			break;
+	}
+
+	if (errors > 0) {
+		printf ("NOT OK\n");
+		printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
+			sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
+		return 1;
+	}
+
+	printf ("ok\n");
+	return 0;
+}
diff --git a/u-boot/board/jupiter/Makefile b/u-boot/board/jupiter/Makefile
new file mode 100644
index 0000000..6a6ad8d
--- /dev/null
+++ b/u-boot/board/jupiter/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/jupiter/jupiter.c b/u-boot/board/jupiter/jupiter.c
new file mode 100644
index 0000000..967aabd
--- /dev/null
+++ b/u-boot/board/jupiter/jupiter.c
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+
+#define SDRAM_DDR	0
+#if 1
+/* Settings Icecube */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+#else
+/*Settings Jupiter UB 1.0.0 */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0xD04F0000
+#define SDRAM_CONFIG1	0xf7277f00
+#define SDRAM_CONFIG2	0x88b70004
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sauter (Jupiter)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+int board_early_init_r (void)
+{
+	flash_preinit ();
+	return 0;
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x1000000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+}
+
+int update_flash_size (int flash_size)
+{
+	flash_afterinit (flash_size);
+	return 0;
+}
+
+int board_early_init_f (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/u-boot/board/karo/tx25/Makefile b/u-boot/board/karo/tx25/Makefile
new file mode 100644
index 0000000..8350788
--- /dev/null
+++ b/u-boot/board/karo/tx25/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= tx25.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/karo/tx25/config.mk b/u-boot/board/karo/tx25/config.mk
new file mode 100644
index 0000000..18b2883
--- /dev/null
+++ b/u-boot/board/karo/tx25/config.mk
@@ -0,0 +1,5 @@
+ifdef CONFIG_NAND_SPL
+CONFIG_SYS_TEXT_BASE = 0x810c0000
+else
+CONFIG_SYS_TEXT_BASE = 0x81200000
+endif
diff --git a/u-boot/board/karo/tx25/lowlevel_init.S b/u-boot/board/karo/tx25/lowlevel_init.S
new file mode 100644
index 0000000..823df10
--- /dev/null
+++ b/u-boot/board/karo/tx25/lowlevel_init.S
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/macro.h>
+
+.macro init_aips
+	write32	0x43f00000, 0x77777777
+	write32	0x43f00004, 0x77777777
+	write32	0x43f00000, 0x77777777
+	write32	0x53f00004, 0x77777777
+.endm
+
+.macro init_max
+	write32	0x43f04000, 0x43210
+	write32	0x43f04100, 0x43210
+	write32	0x43f04200, 0x43210
+	write32	0x43f04300, 0x43210
+	write32	0x43f04400, 0x43210
+
+	write32	0x43f04010, 0x10
+	write32	0x43f04110, 0x10
+	write32	0x43f04210, 0x10
+	write32	0x43f04310, 0x10
+	write32	0x43f04410, 0x10
+
+	write32	0x43f04800, 0x0
+	write32	0x43f04900, 0x0
+	write32	0x43f04a00, 0x0
+	write32	0x43f04b00, 0x0
+	write32	0x43f04c00, 0x0
+.endm
+
+.macro init_m3if
+	write32 0xb8003000, 0x1
+.endm
+
+.macro init_clocks
+	/*
+	 * clocks
+	 *
+	 * first enable CLKO debug output
+	 * 0x40000000 enables the debug CLKO signal
+	 * 0x05000000 sets CLKO divider to 6
+	 * 0x00600000 makes CLKO parent clk the USB clk
+	 */
+	write32	0x53f80064, 0x45600000
+	write32	0x53f80008, 0x20034000
+
+	/*
+	 * enable all implemented clocks in all three
+	 * clock control registers
+	 */
+	write32	0x53f8000c, 0x1fffffff
+	write32	0x53f80010, 0xffffffff
+	write32	0x53f80014, 0xfdfff
+.endm
+
+.macro init_ddrtype
+	/*
+	 * ddr_type is 3.3v SDRAM
+	 */
+	write32	0x43fac454, 0x800
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_sdram_bank bankaddr, ctl, cfg
+	ldr	r0, =0xb8001000
+	ldr	r2, =\bankaddr
+	/*
+	 * reset SDRAM controller
+	 * then wait for initialization to complete
+	 */
+	ldr	r1, =(1 << 1)
+	str	r1, [r0, #0x10]
+1:	ldr	r3, [r0, #0x10]
+	tst	r3, #(1 << 31)
+	beq	1b
+
+	ldr	r1, =0x95728
+	str	r1, [r0, #\cfg]		/* config */
+
+	ldr	r1, =0x92116480		/* control | precharge */
+	str	r1, [r0, #\ctl]		/* write command to controller */
+	str	r1, [r2, #0x400]	/* command encoded in address */
+
+	ldr	r1, =0xa2116480		/* auto refresh */
+	str	r1, [r0, #\ctl]
+	ldrb	r3, [r2]		/* read dram twice to auto refresh */
+	ldrb	r3, [r2]
+
+	ldr	r1, =0xb2116480		/* control | load mode */
+	str	r1, [r0, #\ctl]		/* write command to controller */
+	strb	r1, [r2, #0x33]		/* command encoded in address */
+
+	ldr	r1, =0x82116480		/* control  | normal (0)*/
+	str	r1, [r0, #\ctl]		/* write command to controller */
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+	init_aips
+	init_max
+	init_m3if
+	init_clocks
+
+	init_sdram_bank 0x80000000, 0x0, 0x4
+
+	init_sdram_bank 0x90000000, 0x8, 0xc
+	mov	pc, lr
diff --git a/u-boot/board/karo/tx25/tx25.c b/u-boot/board/karo/tx25/tx25.c
new file mode 100644
index 0000000..dc57d5c
--- /dev/null
+++ b/u-boot/board/karo/tx25/tx25.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ *   Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ *   Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ *   RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx25-pinmux.h>
+
+static void mdelay(int n)
+{
+	while (n-- > 0)
+		udelay(1000);
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FEC_MXC
+void tx25_fec_init(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 val;
+	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+	struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
+	struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
+	u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
+
+	debug("tx25_fec_init\n");
+	/*
+	 * fec pin init is generic
+	 */
+	mx25_fec_init_pins();
+
+	/*
+	 * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+	 *
+	 * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
+	 * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
+	 */
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+	writel(gpio_mux_mode, &muxctl->pad_d13);
+	writel(gpio_mux_mode, &muxctl->pad_d11);
+
+	writel(0x0, &padctl->pad_d13);
+	writel(0x0, &padctl->pad_d11);
+
+	/* drop PHY power and assert reset (low) */
+	val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9));
+	writel(val, &gpio4->dr);
+	val = readl(&gpio4->dir) | (1 << 7) | (1 << 9);
+	writel(val, &gpio4->dir);
+
+	mdelay(5);
+
+	debug("resetting phy\n");
+
+	/* turn on PHY power leaving reset asserted */
+	val = readl(&gpio4->dr) | 1 << 9;
+	writel(val, &gpio4->dr);
+
+	mdelay(10);
+
+	/*
+	 * Setup some strapping pins that are latched by the PHY
+	 * as reset goes high.
+	 *
+	 * Set PHY mode to 111
+	 *  mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
+	 *  mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
+	 *  mode2 is tied high so nothing to do
+	 *
+	 * Turn on RMII mode
+	 *  RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
+	 */
+	/*
+	 * save three current mux modes and set each to gpio mode
+	 */
+	saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
+	saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
+	saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
+
+	writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
+	writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
+	writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
+
+	/*
+	 * set each to 1 and make each an output
+	 */
+	val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12);
+	writel(val, &gpio3->dr);
+	val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12);
+	writel(val, &gpio3->dir);
+
+	mdelay(22);		/* this value came from RedBoot */
+
+	/*
+	 * deassert PHY reset
+	 */
+	val = readl(&gpio4->dr) | 1 << 7;
+	writel(val, &gpio4->dr);
+	writel(val, &gpio4->dr);
+
+	mdelay(5);
+
+	/*
+	 * set FEC pins back
+	 */
+	writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
+	writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
+	writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
+}
+#else
+#define tx25_fec_init()
+#endif
+
+int board_init()
+{
+#ifdef CONFIG_MXC_UART
+	extern void mx25_uart_init_pins(void);
+
+	mx25_uart_init_pins();
+#endif
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_TX25;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	return 0;
+}
+
+int board_late_init(void)
+{
+	tx25_fec_init();
+	return 0;
+}
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+			PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+			PHYS_SDRAM_2_SIZE);
+#else
+
+#endif
+}
+
+int checkboard(void)
+{
+	printf("KARO TX25\n");
+	return 0;
+}
diff --git a/u-boot/board/kb9202/Makefile b/u-boot/board/kb9202/Makefile
new file mode 100644
index 0000000..49be161
--- /dev/null
+++ b/u-boot/board/kb9202/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Adapted for KwikByte KB920x boards - APR2005
+#
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= kb9202.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/kb9202/config.mk b/u-boot/board/kb9202/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/u-boot/board/kb9202/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/u-boot/board/kb9202/kb9202.c b/u-boot/board/kb9202/kb9202.c
new file mode 100644
index 0000000..3164cc5
--- /dev/null
+++ b/u-boot/board/kb9202/kb9202.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+#include <netdev.h>
+#if defined(CONFIG_DRIVER_ETHER)
+#include <at91rm9200_net.h>
+#include <lxt971a.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void lowlevel_init(void) {
+	/* Required by assembly functions - do nothing	*/
+}
+
+int board_init (void)
+{
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	gd->bd->bi_arch_number = MACH_TYPE_KB9200;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+
+unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac);
+UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac);
+UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac);
+UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status);
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = lxt972_InitPhy;
+	p_phyops->IsPhyConnected = lxt972_IsPhyConnected;
+	p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed;
+	p_phyops->AutoNegotiate = lxt972_AutoNegotiate;
+}
+
+#endif
+#endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/u-boot/board/keymile/common/common.c b/u-boot/board/keymile/common/common.c
new file mode 100644
index 0000000..7b4eefd
--- /dev/null
+++ b/u-boot/board/keymile/common/common.c
@@ -0,0 +1,597 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_MGCOGE)
+#include <mpc8260.h>
+#endif
+#include <ioports.h>
+#include <malloc.h>
+#include <hush.h>
+#include <net.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "../common/common.h"
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#include <i2c.h>
+
+extern int i2c_soft_read_pin (void);
+
+int ivm_calc_crc (unsigned char *buf, int len)
+{
+	const unsigned short crc_tab[16] = {
+		0x0000, 0xCC01, 0xD801, 0x1400,
+		0xF001, 0x3C00, 0x2800, 0xE401,
+		0xA001, 0x6C00, 0x7800, 0xB401,
+		0x5000, 0x9C01, 0x8801, 0x4400};
+
+	unsigned short crc     = 0;   /* final result */
+	unsigned short r1      = 0;   /* temp */
+	unsigned char  byte    = 0;   /* input buffer */
+	int	i;
+
+	/* calculate CRC from array data */
+	for (i = 0; i < len; i++) {
+		byte = buf[i];
+
+		/* lower 4 bits */
+		r1 = crc_tab[crc & 0xF];
+		crc = ((crc) >> 4) & 0x0FFF;
+		crc = crc ^ r1 ^ crc_tab[byte & 0xF];
+
+		/* upper 4 bits */
+		r1 = crc_tab[crc & 0xF];
+		crc = (crc >> 4) & 0x0FFF;
+		crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
+	}
+	return crc;
+}
+
+static int  ivm_set_value (char *name, char *value)
+{
+	char tempbuf[256];
+
+	if (value != NULL) {
+		sprintf (tempbuf, "%s=%s", name, value);
+		return set_local_var (tempbuf, 0);
+	} else {
+		unset_local_var (name);
+	}
+	return 0;
+}
+
+static int ivm_get_value (unsigned char *buf, int len, char *name, int off,
+				int check)
+{
+	unsigned short	val;
+	unsigned char	valbuf[30];
+
+	if ((buf[off + 0] != buf[off + 2]) &&
+	    (buf[off + 2] != buf[off + 4])) {
+		printf ("%s Error corrupted %s\n", __FUNCTION__, name);
+		val = -1;
+	} else {
+		val = buf[off + 0] + (buf[off + 1] << 8);
+		if ((val == 0) && (check == 1))
+			val = -1;
+	}
+	sprintf ((char *)valbuf, "%x", val);
+	ivm_set_value (name, (char *)valbuf);
+	return val;
+}
+
+#define INVENTORYBLOCKSIZE	0x100
+#define INVENTORYDATAADDRESS	0x21
+#define INVENTORYDATASIZE	(INVENTORYBLOCKSIZE - INVENTORYDATAADDRESS - 3)
+
+#define IVM_POS_SHORT_TEXT		0
+#define IVM_POS_MANU_ID			1
+#define IVM_POS_MANU_SERIAL		2
+#define IVM_POS_PART_NUMBER		3
+#define IVM_POS_BUILD_STATE		4
+#define IVM_POS_SUPPLIER_PART_NUMBER	5
+#define IVM_POS_DELIVERY_DATE		6
+#define IVM_POS_SUPPLIER_BUILD_STATE	7
+#define IVM_POS_CUSTOMER_ID		8
+#define IVM_POS_CUSTOMER_PROD_ID	9
+#define IVM_POS_HISTORY			10
+#define IVM_POS_SYMBOL_ONLY		11
+
+static char convert_char (char c)
+{
+	return (c < ' ' || c > '~') ? '.' : c;
+}
+
+static int ivm_findinventorystring (int type,
+					unsigned char* const string,
+					unsigned long maxlen,
+					unsigned char *buf)
+{
+	int xcode = 0;
+	unsigned long cr = 0;
+	unsigned long addr = INVENTORYDATAADDRESS;
+	unsigned long size = 0;
+	unsigned long nr = type;
+	int stop = 0; 	/* stop on semicolon */
+
+	memset(string, '\0', maxlen);
+	switch (type) {
+		case IVM_POS_SYMBOL_ONLY:
+			nr = 0;
+			stop= 1;
+		break;
+		default:
+			nr = type;
+			stop = 0;
+	}
+
+	/* Look for the requested number of CR. */
+	while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
+		if ((buf[addr] == '\r')) {
+			cr++;
+		}
+		addr++;
+	}
+
+	/* the expected number of CR was found until the end of the IVM
+	 *  content --> fill string */
+	if (addr < INVENTORYDATASIZE) {
+		/* Copy the IVM string in the corresponding string */
+		for (; (buf[addr] != '\r')			&&
+			((buf[addr] != ';') ||  (!stop))	&&
+			(size < (maxlen - 1)			&&
+			(addr < INVENTORYDATASIZE)); addr++)
+		{
+			size += sprintf((char *)string + size, "%c",
+						convert_char (buf[addr]));
+		}
+
+		/* copy phase is done: check if everything is ok. If not,
+		 * the inventory data is most probably corrupted: tell
+		 * the world there is a problem! */
+		if (addr == INVENTORYDATASIZE) {
+			xcode = -1;
+			printf ("Error end of string not found\n");
+		} else if ((size >= (maxlen - 1)) &&
+			   (buf[addr] != '\r')) {
+			xcode = -1;
+			printf ("string too long till next CR\n");
+		}
+	} else {
+		/* some CR are missing...
+		 * the inventory data is most probably corrupted */
+		xcode = -1;
+		printf ("not enough cr found\n");
+	}
+	return xcode;
+}
+
+#define GET_STRING(name, which, len) \
+	if (ivm_findinventorystring (which, valbuf, len, buf) == 0) { \
+		ivm_set_value (name, (char *)valbuf); \
+	}
+
+static int ivm_check_crc (unsigned char *buf, int block)
+{
+	unsigned long	crc;
+	unsigned long	crceeprom;
+
+	crc = ivm_calc_crc (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+	crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
+			buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
+	if (crc != crceeprom) {
+		if (block == 0)
+			printf ("Error CRC Block: %d EEprom: calculated: \
+			%lx EEprom: %lx\n", block, crc, crceeprom);
+		return -1;
+	}
+	return 0;
+}
+
+static int ivm_analyze_block2 (unsigned char *buf, int len)
+{
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+	unsigned long	count;
+
+	/* IVM_MacAddress */
+	sprintf ((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X",
+			buf[1],
+			buf[2],
+			buf[3],
+			buf[4],
+			buf[5],
+			buf[6]);
+	ivm_set_value ("IVM_MacAddress", (char *)valbuf);
+	if (getenv ("ethaddr") == NULL)
+		setenv ((char *)"ethaddr", (char *)valbuf);
+	/* IVM_MacCount */
+	count = (buf[10] << 24) +
+		   (buf[11] << 16) +
+		   (buf[12] << 8)  +
+		    buf[13];
+	if (count == 0xffffffff)
+		count = 1;
+	sprintf ((char *)valbuf, "%lx", count);
+	ivm_set_value ("IVM_MacCount", (char *)valbuf);
+	return 0;
+}
+
+int ivm_analyze_eeprom (unsigned char *buf, int len)
+{
+	unsigned short	val;
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+	unsigned char	*tmp;
+
+	if (ivm_check_crc (buf, 0) != 0)
+		return -1;
+
+	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1);
+	val = ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1);
+	if (val != 0xffff) {
+		sprintf ((char *)valbuf, "%x", ((val /100) % 10));
+		ivm_set_value ("IVM_HWVariant", (char *)valbuf);
+		sprintf ((char *)valbuf, "%x", (val % 100));
+		ivm_set_value ("IVM_HWVersion", (char *)valbuf);
+	}
+	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0);
+
+	GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
+	GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
+	tmp = (unsigned char *) getenv("IVM_DeviceName");
+	if (tmp) {
+		int	len = strlen ((char *)tmp);
+		int	i = 0;
+
+		while (i < len) {
+			if (tmp[i] == ';') {
+				ivm_set_value ("IVM_ShortText", (char *)&tmp[i + 1]);
+				break;
+			}
+			i++;
+		}
+		if (i >= len)
+			ivm_set_value ("IVM_ShortText", NULL);
+	} else {
+		ivm_set_value ("IVM_ShortText", NULL);
+	}
+	GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
+	GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
+	GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
+	GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
+	GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
+	GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
+	GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
+	GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
+	GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
+
+	if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+		return 0;
+	ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
+
+	return 0;
+}
+
+int ivm_read_eeprom (void)
+{
+#if defined(CONFIG_I2C_MUX)
+	I2C_MUX_DEVICE *dev = NULL;
+#endif
+	uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+	uchar	*buf;
+	unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
+
+#if defined(CONFIG_I2C_MUX)
+	/* First init the Bus, select the Bus */
+#if defined(CONFIG_SYS_I2C_IVM_BUS)
+	dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
+#else
+	buf = (unsigned char *) getenv ("EEprom_ivm");
+	if (buf != NULL)
+		dev = i2c_mux_ident_muxstring (buf);
+#endif
+	if (dev == NULL) {
+		printf ("Error couldnt add Bus for IVM\n");
+		return -1;
+	}
+	i2c_set_bus_num (dev->busid);
+#endif
+
+	buf = (unsigned char *) getenv ("EEprom_ivm_addr");
+	if (buf != NULL)
+		dev_addr = simple_strtoul ((char *)buf, NULL, 16);
+
+	if (i2c_read(dev_addr, 0, 1, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) {
+		printf ("Error reading EEprom\n");
+		return -2;
+	}
+
+	return ivm_analyze_eeprom (i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+}
+
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
+#define DELAY_ABORT_SEQ		62
+#define DELAY_HALF_PERIOD	(500 / (CONFIG_SYS_I2C_SPEED / 1000))
+
+#if defined(CONFIG_MGCOGE)
+#define SDA_MASK	0x00010000
+#define SCL_MASK	0x00020000
+static void set_pin (int state, unsigned long mask)
+{
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+
+	if (state)
+		iop->pdat |= (mask);
+	else
+		iop->pdat &= ~(mask);
+
+	iop->pdir |= (mask);
+}
+
+static int get_pin (unsigned long mask)
+{
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+
+	iop->pdir &= ~(mask);
+	return (0 != (iop->pdat & (mask)));
+}
+
+static void set_sda (int state)
+{
+	set_pin (state, SDA_MASK);
+}
+
+static void set_scl (int state)
+{
+	set_pin (state, SCL_MASK);
+}
+
+static int get_sda (void)
+{
+	return get_pin (SDA_MASK);
+}
+
+static int get_scl (void)
+{
+	return get_pin (SCL_MASK);
+}
+
+#if defined(CONFIG_HARD_I2C)
+static void setports (int gpio)
+{
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+
+	if (gpio) {
+		iop->ppar &= ~(SDA_MASK | SCL_MASK);
+		iop->podr &= ~(SDA_MASK | SCL_MASK);
+	} else {
+		iop->ppar |= (SDA_MASK | SCL_MASK);
+		iop->pdir &= ~(SDA_MASK | SCL_MASK);
+		iop->podr |= (SDA_MASK | SCL_MASK);
+	}
+}
+#endif
+#endif
+
+#if defined(CONFIG_KM8XX)
+static void set_sda (int state)
+{
+	I2C_SDA(state);
+}
+
+static void set_scl (int state)
+{
+	I2C_SCL(state);
+}
+
+static int get_sda (void)
+{
+	return I2C_READ;
+}
+
+static int get_scl (void)
+{
+	int	val;
+
+	*(unsigned short *)(I2C_BASE_DIR) &=  ~SCL_CONF;
+	udelay (1);
+	val = *(unsigned char *)(I2C_BASE_PORT);
+
+	return ((val & SCL_BIT) == SCL_BIT);
+}
+#endif
+
+#if !defined(CONFIG_KMETER1)
+static void writeStartSeq (void)
+{
+	set_sda (1);
+	udelay (DELAY_HALF_PERIOD);
+	set_scl (1);
+	udelay (DELAY_HALF_PERIOD);
+	set_sda (0);
+	udelay (DELAY_HALF_PERIOD);
+	set_scl (0);
+	udelay (DELAY_HALF_PERIOD);
+}
+
+/* I2C is a synchronous protocol and resets of the processor in the middle
+   of an access can block the I2C Bus until a powerdown of the full unit is
+   done. This function toggles the SCL until the SCL and SCA line are
+   released, but max. 16 times, after this a I2C start-sequence is sent.
+   This I2C Deblocking mechanism was developed by Keymile in association
+   with Anatech and Atmel in 1998.
+ */
+static int i2c_make_abort (void)
+{
+	int	scl_state = 0;
+	int	sda_state = 0;
+	int	i = 0;
+	int	ret = 0;
+
+	if (!get_sda ()) {
+		ret = -1;
+		while (i < 16) {
+			i++;
+			set_scl (0);
+			udelay (DELAY_ABORT_SEQ);
+			set_scl (1);
+			udelay (DELAY_ABORT_SEQ);
+			scl_state = get_scl ();
+			sda_state = get_sda ();
+			if (scl_state && sda_state) {
+				ret = 0;
+				break;
+			}
+		}
+	}
+	if (ret == 0) {
+		for (i =0; i < 5; i++) {
+			writeStartSeq ();
+		}
+	}
+	get_sda ();
+	return ret;
+}
+#endif
+
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ */
+void i2c_init_board(void)
+{
+#if defined(CONFIG_KMETER1)
+	struct fsl_i2c *dev;
+	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+	uchar	dummy;
+
+	out_8 (&dev->cr, (I2C_CR_MSTA));
+	out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	dummy = in_8(&dev->dr);
+	dummy = in_8(&dev->dr);
+	if (dummy != 0xff) {
+		dummy = in_8(&dev->dr);
+	}
+	out_8 (&dev->cr, (I2C_CR_MEN));
+	out_8 (&dev->cr, 0x00);
+	out_8 (&dev->cr, (I2C_CR_MEN));
+
+#else
+#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
+
+	/* disable I2C controller first, otherwhise it thinks we want to    */
+	/* talk to the slave port...                                        */
+	i2c->i2c_i2mod &= ~0x01;
+
+	/* Set the PortPins to GPIO */
+	setports (1);
+#endif
+
+	/* Now run the AbortSequence() */
+	i2c_make_abort ();
+
+#if defined(CONFIG_HARD_I2C)
+	/* Set the PortPins back to use for I2C */
+	setports (0);
+#endif
+#endif
+}
+#endif
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int fdt_set_node_and_value (void *blob,
+				char *nodename,
+				char *regname,
+				void *var,
+				int size)
+{
+	int ret = 0;
+	int nodeoffset = 0;
+
+	nodeoffset = fdt_path_offset (blob, nodename);
+	if (nodeoffset >= 0) {
+		ret = fdt_setprop (blob, nodeoffset, regname, var,
+					size);
+		if (ret < 0)
+			printf("ft_blob_update(): cannot set %s/%s "
+				"property err:%s\n", nodename, regname,
+				fdt_strerror (ret));
+	} else {
+		printf("ft_blob_update(): cannot find %s node "
+			"err:%s\n", nodename, fdt_strerror (nodeoffset));
+	}
+	return ret;
+}
+int fdt_get_node_and_value (void *blob,
+				char *nodename,
+				char *propname,
+				void **var)
+{
+	int len;
+	int nodeoffset = 0;
+
+	nodeoffset = fdt_path_offset (blob, nodename);
+	if (nodeoffset >= 0) {
+		*var = (void *)fdt_getprop (blob, nodeoffset, propname, &len);
+		if (len == 0) {
+			/* no value */
+			printf ("%s no value\n", __FUNCTION__);
+			return -1;
+		} else if (len > 0) {
+			return len;
+		} else {
+			printf ("libfdt fdt_getprop(): %s\n",
+				fdt_strerror(len));
+			return -2;
+		}
+	} else {
+		printf("%s: cannot find %s node err:%s\n", __FUNCTION__,
+			nodename, fdt_strerror (nodeoffset));
+		return -3;
+	}
+}
+#endif
+
+#if !defined(CONFIG_MACH_SUEN3)
+int ethernet_present (void)
+{
+	return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
+}
+#endif
+
+int board_eth_init (bd_t *bis)
+{
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+	(void)keymile_hdlc_enet_initialize (bis);
+#endif
+	if (ethernet_present ()) {
+		return -1;
+	}
+	return 0;
+}
diff --git a/u-boot/board/keymile/common/common.h b/u-boot/board/keymile/common/common.h
new file mode 100644
index 0000000..a38c727
--- /dev/null
+++ b/u-boot/board/keymile/common/common.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __KEYMILE_COMMON_H
+#define __KEYMILE_COMMON_H
+
+int ethernet_present (void);
+int ivm_read_eeprom (void);
+
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+int keymile_hdlc_enet_initialize (bd_t *bis);
+#endif
+
+int fdt_set_node_and_value (void *blob,
+			char *nodename,
+			char *regname,
+			void *var,
+			int size);
+int fdt_get_node_and_value (void *blob,
+				char *nodename,
+				char *propname,
+				void **var);
+#endif /* __KEYMILE_COMMON_H */
diff --git a/u-boot/board/keymile/common/keymile_hdlc_enet.c b/u-boot/board/keymile/common/keymile_hdlc_enet.c
new file mode 100644
index 0000000..a545211
--- /dev/null
+++ b/u-boot/board/keymile/common/keymile_hdlc_enet.c
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on arch/powerpc/cpu/mpc8260/ether_scc.c.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+#ifdef TEST_IT
+#include <command.h>
+#endif
+
+#include "keymile_hdlc_enet.h"
+
+extern char keymile_slot;	/* our slot number in the backplane */
+
+/* Allow up to about 50 ms for sending */
+#define TOUT_LOOP	50000
+
+/*
+ * Since, except during initialization, ethact is always HDLC
+ * while we're in the driver, just use serial_printf() everywhere for
+ * output.  This avoids possible conflicts when netconsole is being
+ * used.
+ */
+#define dprintf(fmt, args...)	serial_printf(fmt, ##args)
+
+/* Cannot use the storage from net.c because we allocate larger buffers */
+static volatile uchar MyPktBuf[HDLC_PKTBUFSRX * PKT_MAXBLR_SIZE + PKTALIGN];
+static volatile uchar *MyRxPackets[HDLC_PKTBUFSRX]; /* Receive packet */
+
+static unsigned int keymile_rxIdx;	/* index of the current RX buffer */
+
+static IPaddr_t cachedNumbers[CACHEDNUMBERS]; /* 4 bytes per entry */
+void initCachedNumbers(int);
+
+/*
+  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+typedef volatile struct CommonBufferDescriptor {
+    cbd_t txbd;			/* Tx BD */
+    cbd_t rxbd[HDLC_PKTBUFSRX];	/* Rx BD */
+} RTXBD;
+
+/*
+ * This must be extern because it is allocated in DPRAM using CPM-sepcific
+ * code.
+ */
+static RTXBD *rtx;
+
+static int keymile_hdlc_enet_send(struct eth_device *, volatile void *, int);
+static int keymile_hdlc_enet_recv(struct eth_device *);
+void keymile_hdlc_enet_init_bds(RTXBD *);
+extern int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
+extern void keymile_hdlc_enet_halt(struct eth_device *);
+
+/* flags in the buffer descriptor not defined anywhere else */
+#define BD_SC_CT	BD_SC_CD
+#define BD_SC_CR	0x04
+#define BD_SC_DE	0x80
+#ifndef BD_SC_TC
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#endif
+#define BD_SC_FIRST	BD_SC_TC
+#define BD_SC_STATS (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_CR | BD_SC_CD \
+		| BD_SC_OV | BD_SC_DE)
+
+#if defined(TEST_RX) || defined(TEST_TX) || defined(TEST_IT)
+static void hexdump(unsigned char *buf, int len)
+{
+	int i;
+	const int bytesPerLine = 32;
+
+	if (len > 4 * bytesPerLine)
+		len = 4 * bytesPerLine;
+	dprintf("\t address: %08x\n", (unsigned int)buf);
+	for (i = 0; i < len; i++) {
+		if (i % bytesPerLine == 0)
+			dprintf("%04x: ", (unsigned short)i);
+		dprintf("%02x ", buf[i]);
+		if ((i + 1) % bytesPerLine == 0) {
+			dprintf("\n");
+			continue;
+		}
+		if ((i + 1) % 8 == 0)
+			printf(" ");
+	}
+	if (len % bytesPerLine)
+		dprintf("\n");
+}
+#endif
+
+int keymile_hdlc_enet_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+
+	dev = (struct eth_device *) malloc(sizeof *dev);
+	memset(dev, 0, sizeof *dev);
+#ifdef TEST_IT
+	seth = dev;
+#endif
+
+	sprintf(dev->name, "HDLC");
+	dev->init   = keymile_hdlc_enet_init;
+	dev->halt   = keymile_hdlc_enet_halt;
+	dev->send   = keymile_hdlc_enet_send;
+	dev->recv   = keymile_hdlc_enet_recv;
+
+	eth_register(dev);
+
+	return 1;
+}
+
+/*
+ * This is called from the board-specific driver after rtx is allocated.
+ */
+void keymile_hdlc_enet_init_bds(RTXBD *board_rtx)
+{
+	volatile cbd_t *bdp;
+	int i;
+
+	rtx = board_rtx;
+	keymile_rxIdx = 0;
+	/*
+	 * Initialize the buffer descriptors.
+	 */
+	bdp = &rtx->txbd;
+	bdp->cbd_sc = 0;
+	bdp->cbd_bufaddr = 0;
+	bdp->cbd_sc = BD_SC_WRAP;
+
+	/*
+	 *	Setup RX packet buffers, aligned correctly.
+	 *	Borrowed from net/net.c.
+	 */
+	MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
+	MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
+	for (i = 1; i < HDLC_PKTBUFSRX; i++)
+		MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
+
+	bdp = &rtx->rxbd[0];
+	for (i = 0; i < HDLC_PKTBUFSRX; i++) {
+		bdp->cbd_sc = BD_SC_EMPTY;
+		/* Leave space at the start for INET header. */
+		bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
+			INET_HDR_ALIGN);
+		bdp++;
+	}
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+}
+
+/*
+ * This returns the current port number for NETCONSOLE.  If nc_port
+ * in netconsole.c weren't declared static we wouldn't need this.
+ */
+static short get_netcons_port(void)
+{
+	char *p;
+	short nc_port;
+
+	nc_port = 6666; /* default */
+
+	p = getenv("ncip");
+	if (p != NULL) {
+		p = strchr(p, ':');
+		if (p != NULL)
+			nc_port = simple_strtoul(p + 1, NULL, 10);
+	}
+
+	return htons(nc_port);
+}
+
+/*
+ * Read the port numbers from the variables
+ */
+void initCachedNumbers(int verbose)
+{
+	char *str;
+	ushort port;
+
+	/* already in network order */
+	cachedNumbers[IP_ADDR] = getenv_IPaddr("ipaddr");
+	/* already in network order */
+	cachedNumbers[IP_SERVER] = getenv_IPaddr("serverip");
+	str = getenv("tftpsrcp");
+	if (str != NULL) {
+		/* avoid doing htons() again and again */
+		port = htons((ushort)simple_strtol(str, NULL, 10));
+		cachedNumbers[TFTP_SRC_PORT] = port;
+	} else
+		/* this can never be a valid port number */
+		cachedNumbers[TFTP_SRC_PORT] = (ulong)-1;
+	str = getenv("tftpdstp");
+	if (str != NULL) {
+		/* avoid doing htons() again and again */
+		port = htons((ushort)simple_strtol(str, NULL, 10));
+		cachedNumbers[TFTP_DST_PORT] = port;
+	} else
+		/* this is the default value */
+		cachedNumbers[TFTP_DST_PORT] = htons(WELL_KNOWN_PORT);
+	/* already in network order */
+	cachedNumbers[NETCONS_PORT] = get_netcons_port();
+	if (verbose) {
+		dprintf("\nIP Number Initialization:\n");
+		dprintf(" ip address          %08lx\n", cachedNumbers[IP_ADDR]);
+		dprintf(" server ip address   %08lx\n",
+			cachedNumbers[IP_SERVER]);
+		dprintf(" tftp client port    %ld\n",
+			cachedNumbers[TFTP_SRC_PORT]);
+		dprintf(" tftp server port    %ld\n",
+			cachedNumbers[TFTP_DST_PORT]);
+		dprintf(" netcons port        %ld\n",
+			cachedNumbers[NETCONS_PORT]);
+		dprintf(" slot number (hex)   %02x\n", keymile_slot);
+	}
+}
+
+static void keymile_hdlc_enet_doarp(volatile void *packet, int len)
+{
+	ARP_t *arp;
+	IPaddr_t src_ip; /* U-Boot's IP */
+	IPaddr_t dest_ip; /* the mgcoge's IP */
+	unsigned char *packet_copy = malloc(len);
+
+	/*
+	 * Handling an ARP request means that a new transfer has started.
+	 * Update our cached parameters now.
+	 */
+	initCachedNumbers(0); /* may reinit port numbers */
+
+	/* special handling required for ARP */
+	arp = (ARP_t *)(packet + ETHER_HDR_SIZE);
+	/*
+	 *	XXXX
+	 * This is pretty dirty!  NetReceive only uses
+	 * a few fields when handling an ARP reply, so
+	 * we only modify those here.  This could
+	 * result in catastrophic failure at a later
+	 * time if the handler is modified!
+	 */
+	arp->ar_op = htons(ARPOP_REPLY);
+	/* save his/our IP */
+	src_ip = NetReadIP(&arp->ar_data[6]);
+	dest_ip = NetReadIP(&arp->ar_data[16]);
+	/* copy target IP to source IP */
+	NetCopyIP(&arp->ar_data[6], &dest_ip);
+	/* copy our IP to the right place */
+	NetCopyIP(&arp->ar_data[16], &src_ip);
+	/* always use 0x7f as the MAC for the coge */
+	arp->ar_data[0] = HDLC_UACUA;
+	/*
+	 * copy the packet
+	 * if NetReceive wants to write to stdout, it may overwrite packet
+	 * especially if stdout is set to nc!
+	 *
+	 * However, if the malloc() above fails then we can still try the
+	 * original packet, rather than causing the transfer to fail.
+	 */
+	if (packet_copy != NULL) {
+		memcpy(packet_copy, (char *)packet, len);
+		NetReceive(packet_copy, len);
+		free(packet_copy);
+	} else
+		NetReceive(packet, len);
+}
+
+/*
+ * NOTE all callers ignore the returned value!
+ * At the moment this only handles ARP Requests, TFTP and NETCONSOLE.
+ */
+static int keymile_hdlc_enet_send(struct eth_device *dev, volatile void *packet,
+	int len)
+{
+	int j;
+	uint data_addr;
+	int data_len;
+	struct icn_hdr header;
+	struct icn_frame *frame;
+	Ethernet_t *et;
+	ARP_t *arp;
+	IP_t *ip;
+
+	if (len > (MAX_FRAME_LENGTH - sizeof(header)))
+		return -1;
+
+	frame = NULL;
+	et = NULL;
+	arp = NULL;
+	ip = NULL;
+
+	j = 0;
+	while ((rtx->txbd.cbd_sc & BD_SC_READY) && (j < TOUT_LOOP)) {
+		/* will also trigger Wd if needed, but maybe too often  */
+		udelay(1);
+		j++;
+	}
+	if (j >= TOUT_LOOP) {
+		dprintf("TX not ready sc %x\n", rtx->txbd.cbd_sc);
+		return -1;
+	}
+
+	/*
+	 * First check for an ARP Request since this requires special handling.
+	 */
+	if (len >= (ARP_HDR_SIZE + ETHER_HDR_SIZE)) {
+		et = (Ethernet_t *)packet;
+		arp = (ARP_t *)(((char *)et) + ETHER_HDR_SIZE);
+		/* ARP and REQUEST? */
+		if (et->et_protlen == PROT_ARP &&
+			arp->ar_op == htons(ARPOP_REQUEST)) {
+			/* just short-circuit the request on the U-Boot side */
+			keymile_hdlc_enet_doarp(packet, len);
+			return 0;
+		}
+	}
+
+	/*
+	 * GJ - I suppose the assumption here that len will always be
+	 * > INET_HDR_SIZE is alright as long as the network stack
+	 * isn't changed.
+	 * Do not send INET header.
+	 */
+	data_len = len + sizeof(header) - INET_HDR_SIZE;
+	frame = (struct icn_frame *) (((char *)packet) + INET_HDR_SIZE -
+		sizeof(header));
+
+#ifdef TEST_TX
+	printf("frame: %08x, ", frame);
+	hexdump((unsigned char *)packet, data_len + INET_HDR_SIZE);
+#endif
+
+	data_addr = (uint)frame;
+	if (len >= (IP_HDR_SIZE + ETHER_HDR_SIZE))
+		ip = (IP_t *)(packet + ETHER_HDR_SIZE);
+	/* Is it TFTP? TFTP always uses UDP and the cached dport */
+	if (ip != NULL && ip->ip_p == IPPROTO_UDP && ip->udp_dst ==
+			(ushort)cachedNumbers[TFTP_DST_PORT]) {
+		/* just in case the port wasn't set in the environment */
+		if (cachedNumbers[TFTP_SRC_PORT] == (ulong)-1)
+			cachedNumbers[TFTP_SRC_PORT] = ip->udp_src;
+		frame->hdr.application = MGS_TFTP;
+	}
+	/*
+	 * Is it NETCONSOLE?  NETCONSOLE always uses UDP.
+	 */
+	else if (ip != NULL && ip->ip_p == IPPROTO_UDP
+		&& ip->udp_dst == (ushort)cachedNumbers[NETCONS_PORT]) {
+			frame->hdr.application = MGS_NETCONS;
+	} else {
+		/* reject unknown packets */
+		/* may do some check on frame->hdr.application */
+		dprintf("Unknown packet type in %s, rejected\n",
+			__func__);
+		return -1;
+	}
+	/*
+	 * Could extract the target's slot ID from its MAC here,
+	 * but u-boot only wants to talk to the active server.
+	 *
+	 * avoid setting new source address when moving to another slot
+	 */
+	frame->hdr.src_addr = keymile_slot;
+	frame->hdr.dest_addr = HDLC_UACUA;
+#ifdef TEST_TX
+	{
+		dprintf("TX: ");
+		hexdump((unsigned char *)data_addr, data_len);
+	}
+#endif
+
+	flush_cache(data_addr, data_len);
+	rtx->txbd.cbd_bufaddr = data_addr;
+	rtx->txbd.cbd_datlen = data_len;
+	rtx->txbd.cbd_sc |= (BD_SC_READY | BD_SC_TC | BD_SC_LAST | BD_SC_WRAP);
+
+	while ((rtx->txbd.cbd_sc & BD_SC_READY) && (j < TOUT_LOOP)) {
+		/* will also trigger Wd if needed, but maybe too often  */
+		udelay(1);
+		j++;
+	}
+	if (j >= TOUT_LOOP)
+		dprintf("TX timeout\n");
+#ifdef ET_DEBUG
+	dprintf("cycles: %d    status: %x\n", j, rtx->txbd.cbd_sc);
+#endif
+	j = (rtx->txbd.cbd_sc & BD_SC_STATS); /* return only status bits */
+	return j;
+}
+
+/*
+ * During a receive, the RxIdx points to the current incoming buffer.
+ * When we update through the ring, if the next incoming buffer has
+ * not been given to the system, we just set the empty indicator,
+ * effectively tossing the packet.
+ */
+static int keymile_hdlc_enet_recv(struct eth_device *dev)
+{
+	int length;
+	unsigned char app;
+	struct icn_frame *fp;
+	Ethernet_t *ep;
+	IP_t *ip;
+
+	for (;;) {
+		if (rtx->rxbd[keymile_rxIdx].cbd_sc & BD_SC_EMPTY) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
+
+		length = rtx->rxbd[keymile_rxIdx].cbd_datlen;
+#ifdef TEST_RX
+		dprintf("packet %d bytes long\n", length);
+#endif
+
+		/*
+		 * BD_SC_BR -> LG bit
+		 * BD_SC_FR -> NO bit
+		 * BD_SC_PR -> AB bit
+		 * BD_SC_NAK -> CR bit
+		 * 0x80 -> DE bit
+		 */
+		if (rtx->rxbd[keymile_rxIdx].cbd_sc & BD_SC_STATS) {
+#ifdef ET_DEBUG
+			dprintf("err: %x\n", rtx->rxbd[keymile_rxIdx].cbd_sc);
+#endif
+		} else if (length > MAX_FRAME_LENGTH) { /* can't happen */
+#ifdef ET_DEBUG
+			dprintf("err: packet too big\n");
+#endif
+		} else {
+			fp = (struct icn_frame *)(MyRxPackets[keymile_rxIdx] +
+				INET_HDR_ALIGN - INET_HDR_SIZE);
+#ifdef TEST_RX
+			dprintf("RX %d: ", keymile_rxIdx);
+			hexdump((unsigned char *)MyRxPackets[keymile_rxIdx],
+				INET_HDR_ALIGN + INET_HDR_SIZE + 4);
+#endif
+			/* copy icn header to the beginning */
+			memcpy(fp, ((char *)fp + INET_HDR_SIZE),
+				sizeof(struct icn_hdr));
+			app = fp->hdr.application;
+			if (app == MGS_NETCONS || app == MGS_TFTP) {
+				struct icn_hdr *ih = &fp->hdr;
+				unsigned char icn_src_addr = ih->src_addr;
+				unsigned char icn_dest_addr = ih->dest_addr;
+
+				/*
+				 * expand header by INET_HDR_SIZE
+				 */
+				length += INET_HDR_SIZE;
+				/* initalize header */
+				memset((char *)fp->data, 0x00, INET_HDR_SIZE);
+				ep = (Ethernet_t *)fp->data;
+				/* set MACs */
+				ep->et_dest[0] = icn_dest_addr;
+				ep->et_src[0] = icn_src_addr;
+				ep->et_protlen = htons(PROT_IP);
+				/* set ip stuff */
+				ip = (IP_t *)(fp->data + ETHER_HDR_SIZE);
+				/* set ip addresses */
+				ip->ip_src = cachedNumbers[IP_SERVER];
+				ip->ip_dst = cachedNumbers[IP_ADDR];
+				/* ip length */
+				ip->ip_len = htons(length - ETHER_HDR_SIZE -
+					REMOVE);
+				/* ip proto */
+				ip->ip_p = IPPROTO_UDP;
+				switch (app) {
+				case MGS_TFTP:
+					/* swap src/dst port numbers */
+					ip->udp_src = (ushort)
+						cachedNumbers[TFTP_DST_PORT];
+					ip->udp_dst = (ushort)
+						cachedNumbers[TFTP_SRC_PORT];
+					ip->udp_len = ip->ip_len -
+						IP_HDR_SIZE_NO_UDP;
+					ip->udp_xsum = 0;
+					break;
+				case MGS_NETCONS:
+					ip->udp_src = (ushort)
+						cachedNumbers[NETCONS_PORT];
+					/*
+					 * in drivers/net/netconsole.c src port
+					 * equals dest port
+					 */
+					ip->udp_dst = ip->udp_src;
+					ip->udp_len = ip->ip_len -
+						IP_HDR_SIZE_NO_UDP;
+					ip->udp_xsum = 0;
+					break;
+				}
+				/* ip version */
+				ip->ip_hl_v = (0x40) | (0x0f &
+					(IP_HDR_SIZE_NO_UDP / 4));
+				ip->ip_tos = 0;
+				ip->ip_id = 0;
+				/* flags, fragment offset */
+				ip->ip_off = htons(0x4000);
+				ip->ip_ttl = 255; /* time to live */
+				/* have to fixup the checksum */
+				ip->ip_sum = ~NetCksum((uchar *)ip,
+					IP_HDR_SIZE_NO_UDP / 2);
+				/*
+				 * Pass the packet up to the protocol layers
+				 * but remove dest_addr, src_addr, application
+				 * and the CRC.
+				 */
+#ifdef TEST_RX
+				hexdump((unsigned char *)fp->data,
+					INET_HDR_SIZE + 4);
+#endif
+				NetReceive(fp->data, length - REMOVE);
+			} else {
+				/*
+				 * the other application types are not yet
+				 * supported by u-boot.
+				 */
+				/* normally drop it */
+#ifdef TEST_NO
+				/* send it anyway */
+				fp = (struct icn_frame *)
+					(MyRxPackets[keymile_rxIdx] +
+						INET_HDR_ALIGN);
+				NetReceive(fp->data, length - REMOVE);
+#endif
+			}
+		}
+
+		/* Give the buffer back to the SCC. */
+		rtx->rxbd[keymile_rxIdx].cbd_datlen = 0;
+
+		/* wrap around buffer index when necessary */
+		if ((keymile_rxIdx + 1) >= HDLC_PKTBUFSRX) {
+			rtx->rxbd[HDLC_PKTBUFSRX - 1].cbd_sc =
+				(BD_SC_WRAP | BD_SC_EMPTY);
+			keymile_rxIdx = 0;
+		} else {
+			rtx->rxbd[keymile_rxIdx].cbd_sc = BD_SC_EMPTY;
+			keymile_rxIdx++;
+		}
+	}
+	return length;
+}
+
+#ifdef TEST_IT
+/* simple send test routine */
+int hdlc_enet_stest(struct cmd_tbl_s *a, int b, int c, char **d)
+{
+	unsigned char pkt[2];
+	int ret;
+
+	dprintf("enter stest\n");
+	/* may have to initialize things */
+	if (seth->state != ETH_STATE_ACTIVE) {
+		/* the bd_t* is not used */
+		if (seth->init(seth, NULL) >= 0)
+			seth->state = ETH_STATE_ACTIVE;
+	}
+	pkt[0] = 0xea;
+	pkt[1] = 0xae;
+	ret = keymile_hdlc_enet_send(seth, pkt, 2);
+	dprintf("return from send %x\n", ret);
+	dprintf("exit stest\n");
+	return ret;
+}
+U_BOOT_CMD(
+	stest, 1, 1, hdlc_enet_stest,
+	"simple send test for hdlc_enet",
+	""
+);
+/* simple receive test routine */
+int hdlc_enet_rtest(struct cmd_tbl_s *a, int b, int c, char **d)
+{
+	int ret;
+
+	dprintf("enter rtest\n");
+	/* may have to initialize things */
+	if (seth->state != ETH_STATE_ACTIVE) {
+		/* the bd_t* is not used */
+		if (seth->init(seth, NULL) >= 0)
+			seth->state = ETH_STATE_ACTIVE;
+	}
+	ret = keymile_hdlc_enet_recv(seth);
+	dprintf("return from recv %x\n", ret);
+	dprintf("exit rtest\n");
+	return ret;
+}
+U_BOOT_CMD(
+	rtest, 1, 1, hdlc_enet_rtest,
+	"simple receive test for hdlc_enet",
+	""
+);
+#endif
+
+#endif /* CONFIG_KEYMILE_HDLC_ENET */
diff --git a/u-boot/board/keymile/common/keymile_hdlc_enet.h b/u-boot/board/keymile/common/keymile_hdlc_enet.h
new file mode 100644
index 0000000..db1560f
--- /dev/null
+++ b/u-boot/board/keymile/common/keymile_hdlc_enet.h
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _KEYMILE_HDLC_ENET_H_
+#define _KEYMILE_HDLC_ENET_H_
+
+/* Unfortuantely, we have do this to get the flag defines in the cbd_t */
+#ifdef CONFIG_KM8XX
+#include <commproc.h>
+#endif
+#ifdef CONFIG_MGCOGE
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#endif
+
+/*
+ * Defines for the ICN protocol used for communication over HDLC
+ * on the backplane between MGSUVDs and MGCOGEs.
+ */
+
+/*
+ * MAC which is reserved for communication (0x00 - 0xff in the last byte,
+ * which is the slot number)
+ */
+
+/*
+ * A DLL frame looks like this:
+ *  8 bit  |  8 bit     |  8 bit |  8 bit     | n * 8 bit| 16 bit|  8 bit
+ *  opening| destination| source | application|  data    |  FCS  | closing
+ *   flag  |  address   | address|            |          |       |  flag
+ *  (HW)      (APP)       (APP)      (APP)       (APP)      (HW)   (HW)
+ */
+
+/*
+ * The opening flag, the FCS and the closing flag are set by the hardware so
+ * they are not reflected in this struct.
+ */
+struct icn_hdr {
+	unsigned char dest_addr;
+	unsigned char src_addr;
+	unsigned char application;
+} __attribute__((packed));
+
+#define ICNHDR_LEN	(sizeof(struct icn_hdr))
+#define CRC_LEN		(sizeof(short))
+/* bytes to remove from packet before sending it upstream */
+#define REMOVE		(ICNHDR_LEN + CRC_LEN)
+
+struct icn_frame {
+	struct icn_hdr hdr;
+	unsigned char data[0];	/* a place holder */
+} __attribute__((packed));
+
+/* Address field */
+#define HDLC_UUA	0x00 /* Unicast Unit Address */
+#define HDLC_UUA_MASK	0x3f /* the last 6 bits contain the slot number */
+#define SET_HDLC_UUA(x) ((HDLC_UUA | ((x) & HDLC_UUA_MASK)))
+#define HDLC_UACUA	0x7f /* Unicast Active Control Unit Address */
+#define HDLC_BCAST	0xff /* broadcast */
+
+/* Application field */
+#define MGS_UUSP	0x00
+#define MGS_UREP	0x01
+#define MGS_IUP		0x02
+#define MGS_UTA		0x03
+#define MGS_MDS		0x04
+#define MGS_ITIME	0x05
+/* added by DENX */
+#define MGS_NETCONS	0x06	/* netconsole */
+#define MGS_TFTP	0x07
+
+/* Useful defines for buffer sizes, etc. */
+#define HDLC_PKTBUFSRX		32
+#define MAX_FRAME_LENGTH	1500 /* ethernet frame size */
+			 /*   14        +    28     */
+#define INET_HDR_SIZE	(ETHER_HDR_SIZE + IP_HDR_SIZE)
+#define INET_HDR_ALIGN	(((INET_HDR_SIZE + PKTALIGN - 1) / PKTALIGN) * PKTALIGN)
+/* INET_HDR_SIZE is stripped off */
+#define PKT_MAXBLR_SIZE	(MAX_FRAME_LENGTH + INET_HDR_ALIGN)
+
+/*
+ * It is too slow to read always the port numbers and IP addresses from the
+ * string variables.
+ * cachedNumbers is meant to cache it.
+ * THIS IS ONLY A SPEED IMPROVEMENT!
+ */
+enum {
+	IP_ADDR = 0,	/* getenv_IPaddr("serverip"); */
+	IP_SERVER,	/* getenv_IPaddr("ipaddr"); */
+	TFTP_SRC_PORT,	/* simple_strtol(getenv("tftpsrcp"), NULL, 10); */
+	TFTP_DST_PORT,	/* simple_strtol(getenv("tftpdstp"), NULL, 10); */
+	NETCONS_PORT,	/* simple_strtol(getenv("ncip"), NULL, 10); */
+	CACHEDNUMBERS
+};
+
+#define WELL_KNOWN_PORT 69	/* Well known TFTP port # */
+
+/* define this to create a test commend (htest) */
+#undef TEST_IT
+#ifdef TEST_IT
+/* have to save a copy of the eth_device for the test command's use */
+struct eth_device *seth;
+#endif
+/* define this for outputting of received packets */
+#undef TEST_RX
+/* define this for outputting of packets being sent */
+#undef TEST_TX
+
+#endif /* _KEYMILE_HDLC_ENET_H_ */
diff --git a/u-boot/board/keymile/km_arm/Makefile b/u-boot/board/keymile/km_arm/Makefile
new file mode 100644
index 0000000..6bcfb25
--- /dev/null
+++ b/u-boot/board/keymile/km_arm/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/keymile/km_arm/km_arm.c b/u-boot/board/keymile/km_arm/km_arm.c
new file mode 100644
index 0000000..2e20644
--- /dev/null
+++ b/u-boot/board/keymile/km_arm/km_arm.c
@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <nand.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int	io_dev;
+extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
+
+/* Multi-Purpose Pins Functionality configuration */
+u32 kwmpp_config[] = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_PEX_RST_OUTn,
+#if defined(CONFIG_SOFT_I2C)
+	MPP8_GPIO,		/* SDA */
+	MPP9_GPIO,		/* SCL */
+#endif
+#if defined(CONFIG_HARD_I2C)
+	MPP8_TW_SDA,
+	MPP9_TW_SCK,
+#endif
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP12_GPO,		/* Reserved */
+	MPP13_UART1_TXD,
+	MPP14_UART1_RXD,
+	MPP15_GPIO,		/* Not used */
+	MPP16_GPIO,		/* Not used */
+	MPP17_GPIO,		/* Reserved */
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,
+	MPP27_GPIO,
+	MPP28_GPIO,
+	MPP29_GPIO,
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPIO,
+	MPP34_GPIO,		/* CDL1 (input) */
+	MPP35_GPIO,		/* CDL2 (input) */
+	MPP36_GPIO,		/* MAIN_IRQ (input) */
+	MPP37_GPIO,		/* BOARD_LED */
+	MPP38_GPIO,		/* Piggy3 LED[1] */
+	MPP39_GPIO,		/* Piggy3 LED[2] */
+	MPP40_GPIO,		/* Piggy3 LED[3] */
+	MPP41_GPIO,		/* Piggy3 LED[4] */
+	MPP42_GPIO,		/* Piggy3 LED[5] */
+	MPP43_GPIO,		/* Piggy3 LED[6] */
+	MPP44_GPIO,		/* Piggy3 LED[7] */
+	MPP45_GPIO,		/* Piggy3 LED[8] */
+	MPP46_GPIO,		/* Reserved */
+	MPP47_GPIO,		/* Reserved */
+	MPP48_GPIO,		/* Reserved */
+	MPP49_GPIO,		/* SW_INTOUTn */
+	0
+};
+
+int ethernet_present(void)
+{
+	uchar	buf;
+	int	ret = 0;
+
+	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
+		printf ("%s: Error reading Boco\n", __FUNCTION__);
+		return -1;
+	}
+	if ((buf & 0x40) == 0x40) {
+		ret = 1;
+	}
+	return ret;
+}
+
+int misc_init_r(void)
+{
+	I2C_MUX_DEVICE	*i2cdev;
+	char *str;
+	int mach_type;
+
+	/* add I2C Bus for I/O Expander */
+	i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
+	io_dev = i2cdev->busid;
+	puts("Piggy:");
+	if (ethernet_present() == 0)
+		puts (" not");
+	puts(" present\n");
+
+	str = getenv("mach_type");
+	if (str != NULL) {
+		mach_type = simple_strtoul(str, NULL, 10);
+		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
+		gd->bd->bi_arch_number = mach_type;
+	}
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	u32 tmp;
+
+	kirkwood_mpp_conf(kwmpp_config);
+
+	/*
+	 * The FLASH_GPIO_PIN switches between using a
+	 * NAND or a SPI FLASH. Set this pin on start
+	 * to NAND mode.
+	 */
+	tmp = readl(KW_GPIO0_BASE);
+	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+	tmp = readl(KW_GPIO0_BASE + 4);
+	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+	printf("KM: setting NAND mode\n");
+
+#if defined(CONFIG_SOFT_I2C)
+	/* init the GPIO for I2C Bitbang driver */
+	kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
+	kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
+	kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
+	kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
+#endif
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	kw_gpio_set_valid(SUEN3_ENV_WP, 38);
+	kw_gpio_direction_output(SUEN3_ENV_WP, 1);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_SF)
+int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 tmp;
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	if ((strcmp(argv[1], "off") == 0)) {
+		printf("SPI FLASH disabled, NAND enabled\n");
+		/* Multi-Purpose Pins Functionality configuration */
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+
+		kirkwood_mpp_conf(kwmpp_config);
+		tmp = readl(KW_GPIO0_BASE);
+		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+	} else if ((strcmp(argv[1], "on") == 0)) {
+		printf("SPI FLASH enabled, NAND disabled\n");
+		/* Multi-Purpose Pins Functionality configuration */
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;
+
+		kirkwood_mpp_conf(kwmpp_config);
+		tmp = readl(KW_GPIO0_BASE);
+		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
+	} else {
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	spitoggle,	2,	0,	do_spi_toggle,
+	"En-/disable SPI FLASH access",
+	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
+	);
+#endif
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	/* Fix this */
+	gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
+				kw_sdram_bs(0));
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
+						       kw_sdram_bs(i));
+	}
+}
+
+/* Configure and enable MV88E1118 PHY */
+void reset_phy(void)
+{
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* reset the phy */
+	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store (ulong a)
+{
+	volatile ulong *save_addr;
+	volatile ulong size = 0;
+	int i;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		size += gd->bd->bi_dram[i].size;
+	}
+	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+	writel(a, save_addr);
+	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
+}
+
+ulong bootcount_load (void)
+{
+	volatile ulong *save_addr;
+	volatile ulong size = 0;
+	int i;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		size += gd->bd->bi_dram[i].size;
+	}
+	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
+		return 0;
+	else
+		return readl(save_addr);
+}
+#endif
+
+#if defined(CONFIG_SOFT_I2C)
+void set_sda (int state)
+{
+	I2C_ACTIVE;
+	I2C_SDA(state);
+}
+
+void set_scl (int state)
+{
+	I2C_SCL(state);
+}
+
+int get_sda (void)
+{
+	I2C_TRISTATE;
+	return I2C_READ;
+}
+
+int get_scl (void)
+{
+	return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	kw_gpio_set_value(SUEN3_ENV_WP, !state);
+
+	return !kw_gpio_get_value(SUEN3_ENV_WP);
+}
+#endif
diff --git a/u-boot/board/keymile/km_arm/kwbimage.cfg b/u-boot/board/keymile/km_arm/kwbimage.cfg
new file mode 100644
index 0000000..26d6aa0
--- /dev/null
+++ b/u-boot/board/keymile/km_arm/kwbimage.cfg
@@ -0,0 +1,175 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01111111	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	1, NF_IO[2]
+# bit 7-4:   MPPSel1	1, NF_IO[3]
+# bit 12-8:  MPPSel2	1, NF_IO[4]
+# bit 15-12: MPPSel3	1, NF_IO[5]
+# bit 19-16: MPPSel4	1, NF_IO[6]
+# bit 23-20: MPPSel5	1, NF_IO[7]
+# bit 27-24: MPPSel6	1, SYSRST_O
+# bit 31-28: MPPSel7	0, GPO[7]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   MPPSel16	0, GPIO[16]
+# bit 7-4:   MPPSel17	0, GPIO[17]
+# bit 12-8:  MPPSel18	1, NF_IO[0]
+# bit 15-12: MPPSel19	1, NF_IO[1]
+# bit 19-16: MPPSel20	0, GPIO[20]
+# bit 23-20: MPPSel21	0, GPIO[21]
+# bit 27-24: MPPSel22	0, GPIO[22]
+# bit 31-28: MPPSel23	0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+DATA 0xFFD20134 0xBBBBBBBB	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x00BBBBBB	# L2 RAM Timing 1 Register
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+#Dram initalization
+DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register
+# bit13-0:  0x400 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36343000	# DDR Controller Control Low
+# bit 3-0:  0 reserved
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302544B	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000032	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000642	#  DDR Mode
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    1,  DDR ODT control lsd disabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  0  , no sample stage
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00000000	#  DDR ODT Control (Low)
+# bit3-0:  0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E90F	# CPU ODT Control
+# bit3-0:  F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit9-8:  1, ODTEn, never active
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/u-boot/board/keymile/kmeter1/Makefile b/u-boot/board/keymile/kmeter1/Makefile
new file mode 100644
index 0000000..2fa84f3
--- /dev/null
+++ b/u-boot/board/keymile/kmeter1/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/keymile/kmeter1/kmeter1.c b/u-boot/board/keymile/kmeter1/kmeter1.c
new file mode 100644
index 0000000..bbcaf5d
--- /dev/null
+++ b/u-boot/board/keymile/kmeter1/kmeter1.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <pci.h>
+#include <libfdt.h>
+
+#include "../common/common.h"
+
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* port pin dir open_drain assign */
+
+	/* MDIO */
+	{0,  1, 3, 0, 2}, /* MDIO */
+	{0,  2, 1, 0, 1}, /* MDC */
+
+	/* UCC4 - UEC */
+	{1, 14, 1, 0, 1}, /* TxD0 */
+	{1, 15, 1, 0, 1}, /* TxD1 */
+	{1, 20, 2, 0, 1}, /* RxD0 */
+	{1, 21, 2, 0, 1}, /* RxD1 */
+	{1, 18, 1, 0, 1}, /* TX_EN */
+	{1, 26, 2, 0, 1}, /* RX_DV */
+	{1, 27, 2, 0, 1}, /* RX_ER */
+	{1, 24, 2, 0, 1}, /* COL */
+	{1, 25, 2, 0, 1}, /* CRS */
+	{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
+	{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
+
+	/* DUART - UART2 */
+	{5,  0, 1, 0, 2}, /* UART2_SOUT */
+	{5,  2, 1, 0, 1}, /* UART2_RTS */
+	{5,  3, 2, 0, 2}, /* UART2_SIN */
+	{5,  1, 2, 0, 3}, /* UART2_CTS */
+
+	/* END of table */
+	{0,  0, 0, 0, QE_IOP_TAB_END},
+};
+
+static int board_init_i2c_busses (void)
+{
+	I2C_MUX_DEVICE *dev = NULL;
+	uchar	*buf;
+
+	/* Set up the Bus for the DTTs */
+	buf = (unsigned char *) getenv ("dtt_bus");
+	if (buf != NULL)
+		dev = i2c_mux_ident_muxstring (buf);
+	if (dev == NULL) {
+		printf ("Error couldn't add Bus for DTT\n");
+		printf ("please setup dtt_bus to where your\n");
+		printf ("DTT is found.\n");
+	}
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	unsigned short	svid;
+
+	/*
+	 * Because of errata in the UCCs, we have to write to the reserved
+	 * registers to slow the clocks down.
+	 */
+	svid =  SVR_REV(mfspr (SVR));
+	switch (svid) {
+	case 0x0020:
+		setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
+		break;
+	case 0x0021:
+		clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
+			0x00000050, 0x000000a0);
+		break;
+	}
+	/* enable the PHY on the PIGGY */
+	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
+	/* enable the Unit LED (green) */
+	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x00002), 0x01);
+	/* take FE/GbE PHYs out of reset */
+	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x0000f), 0x1c);
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* add board specific i2c busses */
+	board_init_i2c_busses ();
+	return 0;
+}
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	udelay (200);
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	msize = CONFIG_SYS_DDR_SIZE << 20;
+	disable_addr_trans ();
+	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+	enable_addr_trans ();
+	msize /= (1024 * 1024);
+	if (CONFIG_SYS_DDR_SIZE != msize) {
+		for (ddr_size = msize << 20, ddr_size_log2 = 0;
+		     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
+			if (ddr_size & 1)
+				return -1;
+		im->sysconf.ddrlaw[0].ar =
+		    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+		im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
+	}
+
+	return msize;
+}
+
+phys_size_t initdram (int board_type)
+{
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	extern void ddr_enable_ecc (unsigned int dram_size);
+#endif
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+	msize = fixed_sdram ();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize DDR ECC byte
+	 */
+	ddr_enable_ecc (msize * 1024 * 1024);
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+int checkboard (void)
+{
+	puts ("Board: Keymile kmeter1");
+	if (ethernet_present ())
+		puts (" with PIGGY.");
+	puts ("\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+/*
+ * update property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+  /* no board specific update */
+}
+
+
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+	ft_blob_update (blob, bd);
+}
+#endif
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+extern int ivm_read_eeprom (void);
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+#endif
diff --git a/u-boot/board/keymile/mgcoge/Makefile b/u-boot/board/keymile/mgcoge/Makefile
new file mode 100644
index 0000000..3308621
--- /dev/null
+++ b/u-boot/board/keymile/mgcoge/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
+		mgcoge_hdlc_enet.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/keymile/mgcoge/mgcoge.c b/u-boot/board/keymile/mgcoge/mgcoge.c
new file mode 100644
index 0000000..5c9496c
--- /dev/null
+++ b/u-boot/board/keymile/mgcoge/mgcoge.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2007 - 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <malloc.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#include <i2c.h>
+#endif
+
+#include "../common/common.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf	ppar psor pdir podr pdat */
+	/* PA31 */ { 0,		 0,   0,   0,	0,   0 }, /* PA31	     */
+	/* PA30 */ { 0,		 0,   0,   0,	0,   0 }, /* PA30	     */
+	/* PA29 */ { 0,		 0,   0,   0,	0,   0 }, /* PA29	     */
+	/* PA28 */ { 0,		 0,   0,   0,	0,   0 }, /* PA28	     */
+	/* PA27 */ { 0,		 0,   0,   0,	0,   0 }, /* PA27	     */
+	/* PA26 */ { 0,		 0,   0,   0,	0,   0 }, /* PA26	     */
+	/* PA25 */ { 0,		 0,   0,   0,	0,   0 }, /* PA25	     */
+	/* PA24 */ { 0,		 0,   0,   0,	0,   0 }, /* PA24	     */
+	/* PA23 */ { 0,		 0,   0,   0,	0,   0 }, /* PA23	     */
+	/* PA22 */ { 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
+	/* PA21 */ { 0,		 0,   0,   0,	0,   0 }, /* PA21	     */
+	/* PA20 */ { 0,		 0,   0,   0,	0,   0 }, /* PA20	     */
+	/* PA19 */ { 0,		 0,   0,   0,	0,   0 }, /* PA19	     */
+	/* PA18 */ { 0,		 0,   0,   0,	0,   0 }, /* PA18	     */
+	/* PA17 */ { 0,		 0,   0,   0,	0,   0 }, /* PA17	     */
+	/* PA16 */ { 0,		 0,   0,   0,	0,   0 }, /* PA16	     */
+	/* PA15 */ { 0,		 0,   0,   0,	0,   0 }, /* PA15	     */
+	/* PA14 */ { 0,		 0,   0,   0,	0,   0 }, /* PA14	     */
+	/* PA13 */ { 0,		 0,   0,   0,	0,   0 }, /* PA13	     */
+	/* PA12 */ { 0,		 0,   0,   0,	0,   0 }, /* PA12	     */
+	/* PA11 */ { 0,		 0,   0,   0,	0,   0 }, /* PA11	     */
+	/* PA10 */ { 0,		 0,   0,   0,	0,   0 }, /* PA10	     */
+	/* PA9	*/ { 1,		 1,   0,   1,	0,   0 }, /* SMC2 TxD	     */
+	/* PA8	*/ { 1,		 1,   0,   0,	0,   0 }, /* SMC2 RxD	     */
+	/* PA7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA7	     */
+	/* PA6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA6	     */
+	/* PA5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA5	     */
+	/* PA4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA4	     */
+	/* PA3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA3	     */
+	/* PA2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA2	     */
+	/* PA1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA1	     */
+	/* PA0	*/ { 0,		 0,   0,   0,	0,   0 }  /* PA0	     */
+    },
+
+    /* Port B */
+    {	/*	      conf	ppar psor pdir podr pdat */
+	/* PB31 */ { 0,		 0,   0,   0,	0,   0 }, /* PB31	     */
+	/* PB30 */ { 0,		 0,   0,   0,	0,   0 }, /* PB30	     */
+	/* PB29 */ { 0,		 0,   0,   0,	0,   0 }, /* PB29	     */
+	/* PB28 */ { 0,		 0,   0,   0,	0,   0 }, /* PB28	     */
+	/* PB27 */ { 0,		 0,   0,   0,	0,   0 }, /* PB27	     */
+	/* PB26 */ { 0,		 0,   0,   0,	0,   0 }, /* PB26	     */
+	/* PB25 */ { 0,		 0,   0,   0,	0,   0 }, /* PB25	     */
+	/* PB24 */ { 0,		 0,   0,   0,	0,   0 }, /* PB24	     */
+	/* PB23 */ { 0,		 0,   0,   0,	0,   0 }, /* PB23	     */
+	/* PB22 */ { 0,		 0,   0,   0,	0,   0 }, /* PB22	     */
+	/* PB21 */ { 0,		 0,   0,   0,	0,   0 }, /* PB21	     */
+	/* PB20 */ { 0,		 0,   0,   0,	0,   0 }, /* PB20	     */
+	/* PB19 */ { 0,		 0,   0,   0,	0,   0 }, /* PB19	     */
+	/* PB18 */ { 0,		 0,   0,   0,	0,   0 }, /* PB18	     */
+	/* PB17 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB9	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB8	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB6	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB5	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB4	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {	/*	      conf	ppar psor pdir podr pdat */
+	/* PC31 */ { 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
+	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
+	/* PC29 */ { 0,		 0,   0,   0,	0,   0 }, /* PC29	     */
+	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
+	/* PC27 */ { 0,		 0,   0,   0,	0,   0 }, /* PC27	     */
+	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
+	/* PC25 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4 RxClk      */
+	/* PC24 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4 TxClk      */
+	/* PC23 */ { 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
+	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
+	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
+	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
+	/* PC19 */ { 0,		 0,   0,   0,	0,   0 }, /* PC19	     */
+	/* PC18 */ { 0,		 0,   0,   0,	0,   0 }, /* PC18	     */
+	/* PC17 */ { 0,		 0,   0,   0,	0,   0 }, /* PC17	     */
+	/* PC16 */ { 0,		 0,   0,   0,	0,   0 }, /* PC16	     */
+	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
+	/* PC14 */ { 0,		 0,   0,   0,	0,   0 }, /* PC14	     */
+	/* PC13 */ { 0,		 0,   0,   0,	0,   0 }, /* PC13	     */
+	/* PC12 */ { 0,		 0,   0,   0,	0,   0 }, /* PC12	     */
+	/* PC11 */ { 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
+	/* PC10 */ { 0,		 0,   0,   0,	0,   0 }, /* PC10	     */
+	/* PC9	*/ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: CTS	     */
+	/* PC8	*/ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: CD	     */
+	/* PC7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
+	/* PC6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
+	/* PC5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
+	/* PC4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
+	/* PC3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
+	/* PC2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
+	/* PC1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
+	/* PC0	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
+    },
+
+    /* Port D */
+    {	/*	      conf	ppar psor pdir podr pdat */
+	/* PD31 */ { 0,		 0,   0,   0,	0,   0 }, /* PD31	     */
+	/* PD30 */ { 0,		 0,   0,   0,	0,   0 }, /* PD30	     */
+	/* PD29 */ { 0,		 0,   0,   0,	0,   0 }, /* PD29	     */
+	/* PD28 */ { 0,		 0,   0,   0,	0,   0 }, /* PD28	     */
+	/* PD27 */ { 0,		 0,   0,   0,	0,   0 }, /* PD27	     */
+	/* PD26 */ { 0,		 0,   0,   0,	0,   0 }, /* PD26	     */
+	/* PD25 */ { 0,		 0,   0,   0,	0,   0 }, /* PD25	     */
+	/* PD24 */ { 0,		 0,   0,   0,	0,   0 }, /* PD24	     */
+	/* PD23 */ { 0,		 0,   0,   0,	0,   0 }, /* PD23	     */
+	/* PD22 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: RXD	     */
+	/* PD21 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC4: TXD	     */
+	/* PD20 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC4: RTS	     */
+	/* PD19 */ { 0,		 0,   0,   0,	0,   0 }, /* PD19	     */
+	/* PD18 */ { 0,		 0,   0,   0,	0,   0 }, /* PD18	     */
+	/* PD17 */ { 0,		 0,   0,   0,	0,   0 }, /* PD17	     */
+	/* PD16 */ { 0,		 0,   0,   0,	0,   0 }, /* PD16	     */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ { 1,		 1,   1,   0,	1,   0 }, /* I2C SDA	     */
+	/* PD14 */ { 1,		 1,   1,   0,	1,   0 }, /* I2C SCL	     */
+#else
+	/* PD15 */ { 1,		 0,   0,   0,	1,   1 }, /* PD15	     */
+	/* PD14 */ { 1,		 0,   0,   1,	1,   1 }, /* PD14	     */
+#endif
+	/* PD13 */ { 0,		 0,   0,   0,	0,   0 }, /* PD13	     */
+	/* PD12 */ { 0,		 0,   0,   0,	0,   0 }, /* PD12	     */
+	/* PD11 */ { 0,		 0,   0,   0,	0,   0 }, /* PD11	     */
+	/* PD10 */ { 0,		 0,   0,   0,	0,   0 }, /* PD10	     */
+	/* PD9	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD9	     */
+	/* PD8	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD8	     */
+	/* PD7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD7	     */
+	/* PD6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD6	     */
+	/* PD5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD5	     */
+	/* PD4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD4	     */
+	/* PD3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
+    }
+};
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size ((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int checkboard(void)
+{
+	puts ("Board: Keymile mgcoge");
+	if (ethernet_present ())
+		puts (" with PIGGY.");
+	puts ("\n");
+	return 0;
+}
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r (void)
+{
+	/* setup the UPIOx */
+	/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
+	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
+	/* SCC4 enable, halfduplex, FCC1 powerdown */
+	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
+	return 0;
+}
+
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/u-boot/board/keymile/mgcoge/mgcoge_hdlc_enet.c b/u-boot/board/keymile/mgcoge/mgcoge_hdlc_enet.c
new file mode 100644
index 0000000..98f68a6
--- /dev/null
+++ b/u-boot/board/keymile/mgcoge/mgcoge_hdlc_enet.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on arch/powerpc/cpu/mpc8260/ether_scc.c.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+
+#include "../common/keymile_hdlc_enet.h"
+
+char keymile_slot;	/* our slot number in the backplane */
+
+/*
+ * Since, except during initialization, ethact is always HDLC ETHERNET
+ * while we're in the driver, just use serial_printf() everywhere for
+ * output.  This avoids possible conflicts when netconsole is being
+ * used.
+ */
+#define dprintf(fmt, args...)	serial_printf(fmt, ##args)
+
+static int already_inited;
+
+/*
+  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+typedef volatile struct CommonBufferDescriptor {
+    cbd_t txbd;			/* Tx BD */
+    cbd_t rxbd[HDLC_PKTBUFSRX];	/* Rx BD */
+} RTXBD;
+
+static RTXBD *rtx;
+
+int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
+void keymile_hdlc_enet_halt(struct eth_device *);
+extern void keymile_hdlc_enet_init_bds(RTXBD *);
+extern void initCachedNumbers(int);
+
+/* Use SCC1 */
+#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
+#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
+#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
+					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
+#define CMXSCR_VALUE		(CMXSCR_RS1CS_CLK11|CMXSCR_TS1CS_CLK11)
+#define MGC_PROFF_HDLC	PROFF_SCC1
+#define MGC_SCC_HDLC	0	/* Index, not number! */
+
+int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis)
+{
+	/* int i; */
+	uint dpr;
+	/* volatile cbd_t *bdp; */
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile cpm8260_t *cp = &(im->im_cpm);
+	volatile scc_t *sccp;
+	volatile scc_hdlc_t *hpr;
+	volatile iop8260_t *iop;
+
+	if (already_inited)
+		return 0;
+
+	hpr = (scc_hdlc_t *)(&im->im_dprambase[MGC_PROFF_HDLC]);
+	sccp = (scc_t *)(&im->im_scc[MGC_SCC_HDLC]);
+	iop = &im->im_ioport;
+
+	/*
+	 * Disable receive and transmit just in case.
+	 */
+	sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	/*
+	 * Avoid exhausting DPRAM, which would cause a panic.
+	 */
+	if (rtx == NULL) {
+		/* dpr is an offset into dpram */
+		dpr = m8260_cpm_dpalloc(sizeof(RTXBD), 8);
+		rtx = (RTXBD *)&im->im_dprambase[dpr];
+	}
+
+	/* We need the slot number for addressing. */
+	keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE +
+		CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK;
+	/*
+	 * Be consistent with the Linux driver and set
+	 * only enetaddr[0].
+	 *
+	 * Always add 1 to the slot number so that
+	 * there are no problems with an ethaddr which
+	 * is all 0s.  This should be acceptable because
+	 * a board should never have a slot number of 255,
+	 * which is the broadcast address.  The HDLC addressing
+	 * uses only the slot number.
+	 */
+	dev->enetaddr[0] = keymile_slot + 1;
+#ifdef TEST_IT
+	dprintf("slot %d\n", keymile_slot);
+#endif
+
+	/* use pd30, pd31 pins for TXD1, RXD1 respectively */
+	iop->iop_ppard |= (0x80000000 >> 30) | (0x80000000 >> 31);
+	iop->iop_pdird |= (0x80000000 >> 30);
+	iop->iop_psord |= (0x80000000 >> 30);
+
+	/* use pc21 as CLK11 */
+	iop->iop_pparc |= (0x80000000 >> 21);
+	iop->iop_pdirc &= ~(0x80000000 >> 21);
+	iop->iop_psorc &= ~(0x80000000 >> 21);
+
+	/* use pc15 as CTS1 */
+	iop->iop_pparc |= (0x80000000 >> 15);
+	iop->iop_pdirc &= ~(0x80000000 >> 15);
+	iop->iop_psorc &= ~(0x80000000 >> 15);
+
+	/*
+	 * SI clock routing
+	 * use CLK11
+	 * this also connects SCC1 to NMSI
+	 */
+	im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
+		CMXSCR_VALUE;
+
+	/* keymile_rxIdx = 0; */
+
+	/*
+	 * Initialize function code registers for big-endian.
+	 */
+	hpr->sh_genscc.scc_rfcr = CPMFCR_EB;
+	hpr->sh_genscc.scc_tfcr = CPMFCR_EB;
+
+	/*
+	 * Set maximum bytes per receive buffer.
+	 */
+	hpr->sh_genscc.scc_mrblr = MAX_FRAME_LENGTH;
+
+	/* Setup CRC generator values for HDLC */
+	hpr->sh_cmask = 0x0000F0B8;
+	hpr->sh_cpres = 0x0000FFFF;
+
+	/* Initialize all error counters to 0 */
+	hpr->sh_disfc = 0;
+	hpr->sh_crcec = 0;
+	hpr->sh_abtsc = 0;
+	hpr->sh_nmarc = 0;
+	hpr->sh_retrc = 0;
+
+	/* Set maximum frame length size */
+	hpr->sh_mflr = MAX_FRAME_LENGTH;
+
+	/* set to 1 for per frame processing change later if needed */
+	hpr->sh_rfthr = 1;
+
+	hpr->sh_hmask = 0xff;
+
+	hpr->sh_haddr2 = SET_HDLC_UUA(keymile_slot);
+	hpr->sh_haddr3 = hpr->sh_haddr2;
+	hpr->sh_haddr4 = hpr->sh_haddr2;
+	/* broadcast */
+	hpr->sh_haddr1 = HDLC_BCAST;
+
+	hpr->sh_genscc.scc_rbase = (unsigned int) &rtx->rxbd[0];
+	hpr->sh_genscc.scc_tbase = (unsigned int) &rtx->txbd;
+
+#if 0
+	/*
+	 * Initialize the buffer descriptors.
+	 */
+	bdp = &rtx->txbd;
+	bdp->cbd_sc = 0;
+	bdp->cbd_bufaddr = 0;
+	bdp->cbd_sc = BD_SC_WRAP;
+
+	/*
+	 *	Setup RX packet buffers, aligned correctly.
+	 *	Borrowed from net/net.c.
+	 */
+	MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
+	MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
+	for (i = 1; i < HDLC_PKTBUFSRX; i++)
+		MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
+
+	bdp = &rtx->rxbd[0];
+	for (i = 0; i < HDLC_PKTBUFSRX; i++) {
+		bdp->cbd_sc = BD_SC_EMPTY;
+		/* Leave space at the start for INET header. */
+		bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
+			INET_HDR_ALIGN);
+		bdp++;
+	}
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+#else
+	keymile_hdlc_enet_init_bds(rtx);
+#endif
+
+	/* Let's re-initialize the channel now.	 We have to do it later
+	 * than the manual describes because we have just now finished
+	 * the BD initialization.
+	 */
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
+					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+	while (cp->cp_cpcr & CPM_CR_FLG);
+
+	sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC;
+	/* CTSS=1 */
+	sccp->scc_gsmrh = SCC_GSMRH_CTSS;
+	/* NOF=0, RTE=1, DRT=0, BUS=1 */
+	sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10));
+
+/* loopback for local testing */
+#ifdef GJTEST
+	dprintf("LOOPBACK!\n");
+	sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
+#endif
+
+	/*
+	 * Disable all interrupts and clear all pending
+	 * events.
+	 */
+	sccp->scc_sccm = 0;
+	sccp->scc_scce = 0xffff;
+
+	/*
+	 * And last, enable the transmit and receive processing.
+	 */
+	sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name,
+		MGC_SCC_HDLC + 1);
+
+	/*
+	 * We may not get an ARP packet because ARP was already done on
+	 * a different interface, so initialize the cached values now.
+	 */
+	initCachedNumbers(1);
+
+	already_inited = 1;
+
+	return 0;
+}
+
+void keymile_hdlc_enet_halt(struct eth_device *dev)
+{
+#if 0 /* just return, but keep this for reference */
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* maybe should do a graceful stop here? */
+	immr->im_scc[MGC_SCC_HDLC].scc_gsmrl &=
+		~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+}
+
+#endif /* CONFIG_MGCOGE_HDLC_ENET */
diff --git a/u-boot/board/korat/Makefile b/u-boot/board/korat/Makefile
new file mode 100644
index 0000000..6781596
--- /dev/null
+++ b/u-boot/board/korat/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/korat/config.mk b/u-boot/board/korat/config.mk
new file mode 100644
index 0000000..63e84dc
--- /dev/null
+++ b/u-boot/board/korat/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# Korat (PPC440EPx) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(emul),1)
+PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
+endif
+
+ifndef CONFIG_KORAT_PERMANENT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
+endif
diff --git a/u-boot/board/korat/init.S b/u-boot/board/korat/init.S
new file mode 100644
index 0000000..3741277
--- /dev/null
+++ b/u-boot/board/korat/init.S
@@ -0,0 +1,96 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.  They are
+	 * generated dynamically in the SPD DDR2 detection routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
+		  AC_RWX | SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
+
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
+
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
+
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
+
+	/* TLB-entry for EBC */
+	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
+	tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
+
+	/*TLB-entry PCI registers*/
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
+
+	/* TLB-entry PCI IO Space - from sr@denx.de */
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
+
+	tlbtab_end
+
+#if defined(CONFIG_KORAT_PERMANENT)
+	.globl	korat_branch_absolute
+korat_branch_absolute:
+	mtlr	r3
+	blr
+#endif
diff --git a/u-boot/board/korat/korat.c b/u-boot/board/korat/korat.c
new file mode 100644
index 0000000..4f0513a
--- /dev/null
+++ b/u-boot/board/korat/korat.c
@@ -0,0 +1,644 @@
+/*
+ * (C) Copyright 2007-2010
+ * Larry Johnson, lrj@acm.org
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <asm/ppc440.h>
+#include <asm/bitops.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-uic.h>
+#include <asm/processor.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size(ulong base, int banknum);
+
+#if defined(CONFIG_KORAT_PERMANENT)
+void korat_buzzer(int const on)
+{
+	if (on) {
+		out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
+		      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
+	} else {
+		out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
+		      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
+	}
+}
+#endif
+
+int board_early_init_f(void)
+{
+	uint32_t sdr0_pfc1, sdr0_pfc2;
+	uint32_t reg;
+	int eth;
+
+#if defined(CONFIG_KORAT_PERMANENT)
+	unsigned mscount;
+
+	extern void korat_branch_absolute(uint32_t addr);
+
+	for (mscount = 0;  mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
+		udelay(1000);
+		if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
+			/* This call does not return. */
+			korat_branch_absolute(
+				CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
+		}
+	}
+	korat_buzzer(1);
+	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
+		udelay(1000);
+
+	korat_buzzer(0);
+#endif
+
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Take sim card reader and CF controller out of reset.  Also enable PHY
+	 * auto-detect until board-specific PHY resets are available.
+	 */
+	out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
+
+	/* Configure the two Ethernet PHYs.  For each PHY, configure for fiber
+	 * if the SFP module is present, and for copper if it is not present.
+	 */
+	for (eth = 0; eth < 2; ++eth) {
+		if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
+			/* SFP module not present: configure PHY for copper. */
+			/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
+			out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
+			      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
+			      0x06 << (4 * eth));
+		} else {
+			/* SFP module present: configure PHY for fiber and
+			   enable output */
+			gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
+			gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
+		}
+	}
+	/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
+
+	/* Wait 1 ms, then enable Fiber signal detect to PHYs. */
+	udelay(1000);
+	out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
+	      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
+
+	/* select Ethernet (and optionally IIC1) pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_4;
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* PCI arbiter enabled */
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+	return 0;
+}
+
+/*
+ * The boot flash on CS0 normally has its write-enable pin disabled, and so will
+ * not respond to CFI commands.  This routine therefore fills in the flash
+ * information for the boot flash.  (The flash at CS1 operates normally.)
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	uint32_t addr;
+	int i;
+
+	if (1 != banknum)
+		return 0;
+
+	info->size		= CONFIG_SYS_FLASH0_SIZE;
+	info->sector_count	= CONFIG_SYS_FLASH0_SIZE / 0x20000;
+	info->flash_id		= 0x01000000;
+	info->portwidth		= 2;
+	info->chipwidth		= 2;
+	info->buffer_size	= 32;
+	info->erase_blk_tout	= 16384;
+	info->write_tout	= 2;
+	info->buffer_write_tout	= 5;
+	info->vendor		= 2;
+	info->cmd_reset		= 0x00F0;
+	info->interface		= 2;
+	info->legacy_unlock	= 0;
+	info->manufacturer_id	= 1;
+	info->device_id		= 0x007E;
+
+#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
+	info->device_id2	= 0x2101;
+#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
+	info->device_id2	= 0x2301;
+#else
+#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
+#endif
+
+	info->ext_addr		= 0x0040;
+	info->cfi_version	= 0x3133;
+	info->cfi_offset	= 0x0055;
+	info->addr_unlock1	= 0x00000555;
+	info->addr_unlock2	= 0x000002AA;
+	info->name		= "CFI conformant";
+	for (i = 0, addr = -info->size;
+	     i < info->sector_count;
+	     ++i, addr += 0x20000) {
+		info->start[i] = addr;
+		info->protect[i] = 0x00;
+	}
+	return 1;
+}
+
+static int man_data_read(unsigned int addr)
+{
+	/*
+	 * Read an octet of data from address "addr" in the manufacturer's
+	 * information serial EEPROM, or -1 on error.
+	 */
+	u8 data[2];
+
+	if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
+	    0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
+		debug("man_data_read(0x%02X) failed\n", addr);
+		return -1;
+	}
+	debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
+	return data[0];
+}
+
+static unsigned int man_data_field_addr(unsigned int const field)
+{
+	/*
+	 * The manufacturer's information serial EEPROM contains a sequence of
+	 * zero-delimited fields.  Return the starting address of field "field",
+	 * or 0 on error.
+	 */
+	unsigned addr, i;
+
+	if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
+		/* Only format "A" is currently supported */
+		return 0;
+
+	for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
+		if ('\0' == man_data_read(addr))
+			++i;
+	}
+	return (addr < 256) ? addr : 0;
+}
+
+static char *man_data_read_field(char s[], unsigned const field,
+				 unsigned const length)
+{
+	/*
+	 * Place the null-terminated contents of field "field" of length
+	 * "length" from the manufacturer's information serial EEPROM into
+	 * string "s[length + 1]" and return a pointer to s, or return 0 on
+	 * error. In either case the original contents of s[] is not preserved.
+	 */
+	unsigned addr, i;
+
+	addr = man_data_field_addr(field);
+	if (0 == addr || addr + length >= 255)
+		return 0;
+
+	for (i = 0; i < length; ++i) {
+		int const c = man_data_read(addr++);
+
+		if (c <= 0)
+			return 0;
+
+		s[i] = (char)c;
+	}
+	if (0 != man_data_read(addr))
+		return 0;
+
+	s[i] = '\0';
+	return s;
+}
+
+static void set_serial_number(void)
+{
+	/*
+	 * If the environmental variable "serial#" is not set, try to set it
+	 * from the manufacturer's information serial EEPROM.
+	 */
+	char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
+
+	if (getenv("serial#"))
+		return;
+
+	if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
+		return;
+
+	s[MAN_INFO_LENGTH] = '-';
+	if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
+				 MAN_MAC_ADDR_LENGTH))
+		return;
+
+	setenv("serial#", s);
+}
+
+static void set_mac_addresses(void)
+{
+	/*
+	 * If the environmental variables "ethaddr" and/or "eth1addr" are not
+	 * set, try to set them from the manufacturer's information serial
+	 * EEPROM.
+	 */
+
+#if MAN_MAC_ADDR_LENGTH % 2 != 0
+#error MAN_MAC_ADDR_LENGTH must be an even number
+#endif
+
+	char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
+	char *src;
+	char *dst;
+
+	if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
+		return;
+
+	if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
+				     MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
+		return;
+
+	for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
+		*dst++ = *src++;
+		*dst++ = *src++;
+		*dst++ = ':';
+	}
+	if (0 == getenv("ethaddr"))
+		setenv("ethaddr", s);
+
+	if (0 == getenv("eth1addr")) {
+		++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
+		setenv("eth1addr", s);
+	}
+}
+
+int misc_init_r(void)
+{
+	uint32_t pbcr;
+	int size_val;
+	uint32_t reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
+	char const *const act = getenv("usbact");
+	char const *const usbcf = getenv("korat_usbcf");
+
+	/*
+	 * Re-do FLASH1 sizing and adjust flash start and offset.
+	 */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
+	gd->bd->bi_flashoffset = 0;
+
+	mtdcr(EBC0_CFGADDR, PB1CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(flash1_size) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB1CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+	/*
+	 * Re-do FLASH1 sizing and adjust flash offset to reserve space for
+	 * environment
+	 */
+	gd->bd->bi_flashoffset =
+		CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
+
+	mtdcr(EBC0_CFGADDR, PB1CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB1CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+#if defined(CONFIG_KORAT_PERMANENT)
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+			    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+			    flash_info + 1);
+#else
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+			    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+			    flash_info);
+#endif
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+			    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			    flash_info);
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			    flash_info);
+
+	/*
+	 * USB suff...
+	 */
+	/*
+	 * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
+	 * ("pci") for the CompactFlash.
+	 */
+	if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
+		/*
+		 * If environment variable "usbcf" is defined and set to "ppc",
+		 * then connect the CompactFlash controller to the PowerPC USB
+		 * port.
+		 */
+		printf("Attaching CompactFlash controller to PPC USB\n");
+		out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
+		      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
+	} else {
+		if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
+			printf("Warning: \"korat_usbcf\" is not set to a legal "
+			       "value (\"ppc\" or \"pci\")\n");
+
+		printf("Attaching CompactFlash controller to PCI USB\n");
+	}
+	if (act == NULL || strcmp(act, "hostdev") == 0) {
+		/* SDR Setting */
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+		/*
+		 * An 8-bit/60MHz interface is the only possible alternative
+		 * when connecting the Device to the PHY
+		 */
+		usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+		/*
+		 * To enable the USB 2.0 Device function
+		 * through the UTMI interface
+		 */
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
+
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		/* clear resets */
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay(1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	} else if (strcmp(act, "dev") == 0) {
+		/*-------------------PATCH-------------------------------*/
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x672c6000);
+
+		udelay(1000);
+		mtsdr(SDR0_SRST0, 0x00000080);
+
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x60206000);
+
+		*(unsigned int *)(0xe0000350) = 0x00000001;
+
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x60306000);
+		/*-------------------PATCH-------------------------------*/
+
+		/* SDR Setting */
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+		/* clear resets */
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay(1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Device(int phy)\n");
+	}
+
+	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
+	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+	mtsdr(SDR0_SRST1, reg);
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+	set_serial_number();
+	set_mac_addresses();
+	gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char const *const s = getenv("serial#");
+	u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
+
+	printf("Board: Korat, Rev. %X", rev);
+	if (s)
+		printf(", serial# %s", s);
+
+	printf(".\n       Ethernet PHY 0: ");
+	if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
+		printf("fiber");
+	else
+		printf("copper");
+
+	printf(", PHY 1: ");
+	if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
+		printf("fiber");
+	else
+		printf("copper");
+
+	printf(".\n");
+#if defined(CONFIG_KORAT_PERMANENT)
+	printf("       Executing permanent copy of U-Boot.\n");
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
+}
+#endif
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/* First do 440EP(x) common setup */
+	__pci_target_init(hose);
+
+	/*
+	 * Set up Configuration registers for on-board NEC uPD720101 USB
+	 * controller.
+	 */
+	pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[4];
+	int rc;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR mapping */
+	val[0] = 1;				/* chip select number */
+	val[1] = 0;				/* always 0 */
+	val[2] = gd->bd->bi_flashstart;
+	val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
+	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+				  val, sizeof(val), 1);
+	if (rc)
+		printf("Unable to update property NOR mapping, err=%s\n",
+		       fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/korat/u-boot-F7FC.lds b/u-boot/board/korat/u-boot-F7FC.lds
new file mode 100644
index 0000000..4d73180
--- /dev/null
+++ b/u-boot/board/korat/u-boot-F7FC.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xF7FBFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xF7FBF000 :
+  {
+    arch/powerpc/cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/kup/Makefile b/u-boot/board/kup/Makefile
new file mode 100644
index 0000000..5caae89
--- /dev/null
+++ b/u-boot/board/kup/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o kup.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/kup/common/flash.c b/u-boot/board/kup/common/flash.c
new file mode 100644
index 0000000..134a9d5
--- /dev/null
+++ b/u-boot/board/kup/common/flash.c
@@ -0,0 +1,515 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+#define CONFIG_FLASH_16BIT
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	vu_short *s_addr=(vu_short*)addr;
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x0090;
+
+	value = s_addr[0];
+	value = value|(value<<16);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = s_addr[1];
+	value = value|(value<<16);
+
+		switch (value) {
+	case FUJI_ID_29F800BA:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	/* set sector offsets for bottom boot block type	*/
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+		info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
+
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		s_addr = (volatile unsigned short *)(info->start[i]);
+		info->protect[i] = s_addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		s_addr = (volatile unsigned short *)info->start[0];
+		*s_addr = 0x00F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect;
+	ulong start, now, last;
+#ifdef CONFIG_FLASH_16BIT
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+/*#ifndef CONFIG_FLASH_16BIT
+	ulong type;
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return;
+	}
+#endif*/
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+#ifdef CONFIG_FLASH_16BIT
+			vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
+#else
+			vu_long	*sect_addr = (vu_long*)(info->start[sect]);
+#endif
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+#ifdef CONFIG_FLASH_16BIT
+
+			/*printf("\ns_sect_addr=%x",s_sect_addr);*/
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_addr[0x5555] = 0x0080;
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_sect_addr[0] = 0x0030;
+#else
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			addr[0x5555] = 0x00800080;
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			sect_addr[0] = 0x00300030;
+#endif
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+#ifdef CONFIG_FLASH_16BIT
+			while ((s_sect_addr[0] & 0x0080) != 0x0080) {
+#else
+			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
+#endif
+				if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+		}
+	}
+
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#ifdef CONFIG_FLASH_16BIT
+	s_addr[0] = 0x00F0;	/* reset bank */
+#else
+	addr[0] = 0x00F000F0;	/* reset bank */
+#endif
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+
+#ifdef CONFIG_FLASH_16BIT
+	vu_short high_data;
+	vu_short low_data;
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+#ifdef CONFIG_FLASH_16BIT
+	/* Write the 16 higher-bits */
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	high_data = ((data>>16) & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+
+	*((vu_short *)dest) = high_data;
+
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+
+	/* Write the 16 lower-bits */
+#endif
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#ifdef CONFIG_FLASH_16BIT
+	dest += 0x2;
+	low_data = (data & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+	*((vu_short *)dest) = low_data;
+
+#else
+	addr[0x5555] = 0x00AA00AA;
+	addr[0x2AAA] = 0x00550055;
+	addr[0x5555] = 0x00A000A0;
+	*((vu_long *)dest) = data;
+#endif
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+#ifdef CONFIG_FLASH_16BIT
+	while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
+#else
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+#endif
+
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/kup/common/kup.c b/u-boot/board/kup/common/kup.c
new file mode 100644
index 0000000..38259a5
--- /dev/null
+++ b/u-boot/board/kup/common/kup.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "kup.h"
+#include <asm/io.h>
+
+
+int misc_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile sysconf8xx_t *siu = &immap->im_siu_conf;
+
+	while (in_be32(&siu->sc_sipend) & 0x20000000) {
+		debug("waiting for 5V VCC\n");
+	}
+
+	/* RS232 / RS485 default is RS232 */
+	clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485);
+	clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485);
+	clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485);
+	setbits_be16(&immap->im_ioport.iop_padir, PA_RS485);
+
+	/* IO Reset min 1 msec */
+	setbits_be16(&immap->im_ioport.iop_padat,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	clrbits_be16(&immap->im_ioport.iop_papar,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	clrbits_be16(&immap->im_ioport.iop_paodr,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	setbits_be16(&immap->im_ioport.iop_padir,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	udelay(1000);
+	clrbits_be16(&immap->im_ioport.iop_padat,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	return (0);
+}
+
+#ifdef CONFIG_IDE_LED
+void ide_led(uchar led, uchar status)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* We have one led for both pcmcia slots */
+	if (status)
+		clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW);
+	else
+		setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW);
+}
+#endif
+
+void poweron_key(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1);
+	clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1);
+
+	if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1))
+		setenv("key1", "off");
+	else
+		setenv("key1", "on");
+}
diff --git a/u-boot/board/kup/common/kup.h b/u-boot/board/kup/common/kup.h
new file mode 100644
index 0000000..455848c
--- /dev/null
+++ b/u-boot/board/kup/common/kup.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KUP_H
+#define __KUP_H
+
+#define PA_8	0x0080
+#define PA_9	0x0040
+#define PA_10	0x0020
+#define PA_11	0x0010
+#define PA_12	0x0008
+
+#define PB_14	0x00020000
+#define PB_15	0x00010000
+#define PB_16	0x00008000
+#define PB_17	0x00004000
+
+#define PC_4	0x0800
+#define PC_5	0x0400
+#define PC_9	0x0040
+
+#define PA_RS485	PA_11	/* SCC1: 0=RS232 1=RS485 */
+#define PA_LED_YELLOW	PA_8
+#define PA_RESET_IO_01	PA_9	/* Reset left IO */
+#define PA_RESET_IO_02	PA_10	/* Reset right IO */
+#define PB_PROG_IO_01	PB_15	/* Program left IO */
+#define PB_PROG_IO_02	PB_16	/* Program right IO */
+#define BP_USB_VCC	PB_14	/* VCC for USB devices 0=vcc on, 1=vcc off */
+#define PB_LCD_PWM	PB_17	/* PB 17 */
+#define PC_SWITCH1	PC_9	/* Reboot switch */
+
+
+extern void poweron_key(void);
+extern void load_sernum_ethaddr(void);
+
+#endif	/* __KUP_H */
diff --git a/u-boot/board/kup/common/load_sernum_ethaddr.c b/u-boot/board/kup/common/load_sernum_ethaddr.c
new file mode 100644
index 0000000..741e9a5
--- /dev/null
+++ b/u-boot/board/kup/common/load_sernum_ethaddr.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The KUP Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset CONFIG_SYS_HWINFO_OFFSET
+ * - size CONFIG_SYS_HWINFO_SIZE
+ *
+ * Internal structure:
+ * - sequence of ASCII character lines
+ * - fields separated by <CR><LF>
+ * - last field terminated by NUL character (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) MAC Address
+ * 3) ....
+ */
+
+
+#define ETHADDR_TOKEN "ethaddr="
+#define LCD_TOKEN "lcd="
+
+void load_sernum_ethaddr (void)
+{
+	unsigned char *hwi;
+	char *var;
+	unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE];
+	char *p;
+
+	hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
+	if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) {
+		printf ("HardwareInfo not found!\n");
+		return;
+	}
+	memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE);
+
+	/*
+	 ** ethaddr
+	 */
+	var = strstr ((char *)hwi_stack, ETHADDR_TOKEN);
+	if (var) {
+		var += sizeof (ETHADDR_TOKEN) - 1;
+		p = strchr (var, '\r');
+		if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) {
+			*p = '\0';
+			setenv ("ethaddr", var);
+			*p = '\r';
+		}
+	}
+	/*
+	 ** lcd
+	 */
+	var = strstr ((char *)hwi_stack, LCD_TOKEN);
+	if (var) {
+		var += sizeof (LCD_TOKEN) - 1;
+		p = strchr (var, '\r');
+		if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) {
+			*p = '\0';
+			setenv ("lcd", var);
+			*p = '\r';
+		}
+	}
+}
diff --git a/u-boot/board/kup/common/pcmcia.c b/u-boot/board/kup/common/pcmcia.c
new file mode 100644
index 0000000..ce6b186
--- /dev/null
+++ b/u-boot/board/kup/common/pcmcia.c
@@ -0,0 +1,225 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "KUP"
+
+#define KUP4K_PCMCIA_B_3V3 (0x00020000)
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, mask;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/*
+	* Configure SIUMCR to enable PCMCIA port B
+	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	*/
+	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(slot);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(slot) = reg;
+	udelay(2500);
+
+	/*
+	* Configure Port B pins for
+	* 3 Volts enable
+	*/
+	if (slot) { /* Slot A is built-in */
+		cp->cp_pbdir |=  KUP4K_PCMCIA_B_3V3;
+		cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+		/* remove all power */
+		cp->cp_pbdat |=  KUP4K_PCMCIA_B_3V3; /* active low */
+	}
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On.
+	*/
+	printf("%s  Slot %c:", slot ? "" : "\n", 'A' + slot);
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	reg  = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       reg,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+	if ((reg & mask) == mask) {
+		puts (" 5.0V card found: NOT SUPPORTED !!!\n");
+	} else {
+		if(slot)
+			cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+		puts (" 3.3V card found: ");
+	}
+#if 0
+	/*  VCC switch error flag, PCMCIA slot INPACK_ pin */
+	cp->cp_pbdir &= ~(0x0020 | 0x0010);
+	cp->cp_pbpar &= ~(0x0020 | 0x0010);
+	udelay(500000);
+#endif
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(slot);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(slot) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/* remove all power */
+	if (slot)
+		cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(slot) = reg;
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("voltage_set: "	\
+			PCMCIA_BOARD_MSG	\
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	if (!slot) /* Slot A is not configurable */
+		return 0;
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/*
+	* Disable PCMCIA buffers (isolate the interface)
+	* and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(slot);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(slot) = reg;
+	udelay(500);
+
+	debug ("PCMCIA power OFF\n");
+	/*
+	* Configure Port B pins for
+	* 3 Volts enable
+	*/
+	cp->cp_pbdir |=  KUP4K_PCMCIA_B_3V3;
+	cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+	/* remove all power */
+	cp->cp_pbdat |=  KUP4K_PCMCIA_B_3V3; /* active low */
+
+	switch(vcc) {
+		case  0:		break;
+		case 33:
+			cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+			debug ("PCMCIA powered at 3.3V\n");
+			break;
+		case 50:
+			debug ("PCMCIA: 5Volt vcc not supported\n");
+			break;
+		default:
+			puts("PCMCIA: vcc not supported");
+			break;
+	}
+	udelay(10000);
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+	       pcmp->pcmc_pipr,
+	       (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
+			       ? "only 5 V --> NOT SUPPORTED"
+	: "can do 3.3V");
+
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(slot);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(slot) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/kup/kup4k/Makefile b/u-boot/board/kup/kup4k/Makefile
new file mode 100644
index 0000000..e519b83
--- /dev/null
+++ b/u-boot/board/kup/kup4k/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/kup/kup4k/kup4k.c b/u-boot/board/kup/kup4k/kup4k.c
new file mode 100644
index 0000000..267821c
--- /dev/null
+++ b/u-boot/board/kup/kup4k/kup4k.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <libfdt.h>
+#include <mpc8xx.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include "../common/kup.h"
+#include <asm/io.h>
+
+static unsigned char swapbyte(unsigned char c);
+static int read_diag(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ----------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47,		/* last */
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ----------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
+
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch)
+	 */
+	out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
+	out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
+
+	/*
+	 * Init ChipSelect #5 (S1D13768)
+	 */
+	out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
+	out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
+
+	tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
+	rev = (tmp & 0xF8) >> 3;
+	mod = (tmp & 0x07);
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (read_diag())
+		gd->flags &= ~GD_FLG_SILENT;
+
+	printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
+	/*
+	 * TI Application report: Before using the IO as an input,
+	 * a high must be written to the IO first
+	 */
+	pcf = 0xFF;
+	i2c_write(0x21, 0, 0 , &pcf, 1);
+	if (i2c_read(0x21, 0, 0, &pcf, 1)) {
+		puts("n/a\n");
+	} else {
+		ak_rev = (pcf & 0xF8) >> 3;
+		ak_mod = (pcf & 0x07);
+		printf("%d.%d\n", ak_rev, ak_mod);
+	}
+	return 0;
+}
+
+/* ----------------------------------------------------------------------- */
+
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size = 0;
+	uchar *latch,rev,mod,tmp;
+
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
+	 * Rev 1..6 -> 48 MB RAM;   Rev >= 7 -> 96 MB
+	 */
+	out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
+	out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
+
+	latch = (uchar *)0x90000200;
+	tmp = swapbyte(*latch);
+	rev = (tmp & 0xF8) >> 3;
+	mod = (tmp & 0x07);
+
+	upmconfig(UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+
+	out_be32(&memctl->memc_mar, 0x00000088);
+	/* no refresh yet */
+	if(rev >= 7) {
+		out_be32(&memctl->memc_mamr,
+				 CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
+	} else {
+		out_be32(&memctl->memc_mamr,
+				 CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
+	}
+
+	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	/* SDRAM bank 0 */
+	out_be32(&memctl->memc_mcr, 0x80002105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 1 */
+	out_be32(&memctl->memc_mcr, 0x80004105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 2 */
+	out_be32(&memctl->memc_mcr, 0x80006105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
+	udelay(1000);
+
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+	udelay(1000);
+	if(rev >= 7) {
+		size = 32 * 3 * 1024 * 1024;
+		out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
+		out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
+		out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
+		out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
+		out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
+		out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
+	} else {
+		size = 16 * 3 * 1024 * 1024;
+		out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
+		out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
+		out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
+		out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
+		out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
+		out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
+	}
+	return (size);
+}
+
+/* ----------------------------------------------------------------------- */
+
+
+int misc_init_r(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#ifdef CONFIG_IDE_LED
+	/* Configure PA8 as output port */
+	setbits_be16(&immap->im_ioport.iop_padir, PA_8);
+	setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
+	clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
+	setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
+#endif
+	load_sernum_ethaddr();
+	setenv("hw","4k");
+	poweron_key();
+	return (0);
+}
+
+
+static int read_diag(void)
+{
+	int diag;
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4);	/* input */
+	clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4);	/* gpio */
+	setbits_be16(&immr->im_ioport.iop_pcdir, PC_5);	/* output */
+	clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4);	/* gpio */
+	setbits_be16(&immr->im_ioport.iop_pcdat, PC_5);	/* 1 */
+	udelay(500);
+	if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
+		clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
+		udelay(500);
+		if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
+			diag = 0;
+		else
+			diag = 1;
+	} else {
+		diag = 0;
+	}
+	clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5);	/* input */
+	return (diag);
+}
+
+static unsigned char swapbyte(unsigned char c)
+{
+	unsigned char result = 0;
+	int i = 0;
+
+	for(i = 0; i < 8; ++i) {
+		result = result << 1;
+		result |= (c & 1);
+		c = c >> 1;
+	}
+	return result;
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/u-boot/board/kup/kup4k/u-boot.lds b/u-boot/board/kup/kup4k/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/kup/kup4k/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/kup/kup4k/u-boot.lds.debug b/u-boot/board/kup/kup4k/u-boot.lds.debug
new file mode 100644
index 0000000..a78d0b7
--- /dev/null
+++ b/u-boot/board/kup/kup4k/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/kup/kup4x/Makefile b/u-boot/board/kup/kup4x/Makefile
new file mode 100644
index 0000000..e519b83
--- /dev/null
+++ b/u-boot/board/kup/kup4x/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/kup/kup4x/kup4x.c b/u-boot/board/kup/kup4x/kup4x.c
new file mode 100644
index 0000000..1686eff
--- /dev/null
+++ b/u-boot/board/kup/kup4x/kup4x.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <post.h>
+#include "../common/kup.h"
+#include <asm/io.h>
+
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47,		/* last */
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	uchar latch, rev, mod;
+
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch)
+	 */
+	out_be32(&memctl->memc_or4, 0xFFFF8926);
+	out_be32(&memctl->memc_br4, 0x90000401);
+
+	latch = in_8( (unsigned char *) LATCH_ADDR);
+	rev = (latch & 0xF8) >> 3;
+	mod = (latch & 0x03);
+
+	printf("Board: KUP4X Rev %d.%d\n", rev, mod);
+
+	return 0;
+}
+
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+
+	out_be32(&memctl->memc_mar, 0x00000088);
+
+	out_be32(&memctl->memc_mamr,
+		 CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	/* SDRAM bank 0 */
+	out_be32(&memctl->memc_mcr, 0x80002105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 1 */
+	out_be32(&memctl->memc_mcr, 0x80004105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 2 */
+	out_be32(&memctl->memc_mcr, 0x80006105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 3 */
+	out_be32(&memctl->memc_mcr, 0x8000C105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
+
+	udelay(1000);
+	/* 4 x 16 MB */
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+	udelay(1000);
+	out_be32(&memctl->memc_or1, 0xFF000A00);
+	out_be32(&memctl->memc_br1, 0x00000081);
+	out_be32(&memctl->memc_or2, 0xFE000A00);
+	out_be32(&memctl->memc_br2, 0x01000081);
+	out_be32(&memctl->memc_or3, 0xFD000A00);
+	out_be32(&memctl->memc_br3, 0x02000081);
+	out_be32(&memctl->memc_or6, 0xFC000A00);
+	out_be32(&memctl->memc_br6, 0x03000081);
+	udelay(10000);
+
+	return (4 * 16 * 1024 * 1024);
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#ifdef CONFIG_IDE_LED
+	/* Configure PA8 as output port */
+	setbits_be16(&immap->im_ioport.iop_padir, PA_8);
+	setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
+	clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
+	setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
+#endif
+	load_sernum_ethaddr();
+	setenv("hw", "4x");
+	poweron_key();
+	return 0;
+}
diff --git a/u-boot/board/kup/kup4x/u-boot.lds b/u-boot/board/kup/kup4x/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/kup/kup4x/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/kup/kup4x/u-boot.lds.debug b/u-boot/board/kup/kup4x/u-boot.lds.debug
new file mode 100644
index 0000000..a78d0b7
--- /dev/null
+++ b/u-boot/board/kup/kup4x/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/lantec/Makefile b/u-boot/board/lantec/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/lantec/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lantec/flash.c b/u-boot/board/lantec/flash.c
new file mode 100644
index 0000000..97ed054
--- /dev/null
+++ b/u-boot/board/lantec/flash.c
@@ -0,0 +1,625 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Derived from ../tqm8xx/flash.c
+ * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG]
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE5_PRELIM);
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE5_PRELIM, &flash_info[1]);
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	DEBUGF ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
+				BR_MS_GPCM | BR_PS_32 | BR_V;
+
+	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_PS_32 | BR_V;
+
+		DEBUGF("## BR5: 0x%08x    OR5: 0x%08x\n",
+			memctl->memc_br5, memctl->memc_or5);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br5 = 0;		/* invalidate bank */
+		memctl->memc_or5 = 0;		/* invalidate bank */
+
+		DEBUGF("## DISABLE BR5: 0x%08x    OR5: 0x%08x\n",
+			memctl->memc_br5, memctl->memc_or5);
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/lantec/lantec.c b/u-boot/board/lantec/lantec.c
new file mode 100644
index 0000000..6d3486c
--- /dev/null
+++ b/u-boot/board/lantec/lantec.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2001
+ * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
+ * Bruno Achauer, Exet AG, bruno@exet-ag.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1ff77c35, 0xefeabc34, 0x1fb57c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc07,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7ffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0;
+	int i;
+
+	/*
+	 * Configure UPMA for SDRAM
+	 */
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
+
+	/* burst length=4, burst type=sequential, CAS latency=2 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	/* initialize memory address register */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
+
+	/* mode initialization (offset 5) */
+	udelay (200);		/* 0x80006105 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+	udelay (1);		/* 0x80006130 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+	udelay (1);		/* 0x80006130 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+
+	udelay (1);		/* 0x80006106 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
+
+	udelay (200);
+
+	/* Need at least 10 DRAM accesses to stabilize */
+	for (i = 0; i < 10; ++i) {
+		volatile unsigned long *addr =
+			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
+		unsigned long val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+	size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
+			     (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	udelay (1000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
diff --git a/u-boot/board/lantec/u-boot.lds b/u-boot/board/lantec/u-boot.lds
new file mode 100644
index 0000000..00af669
--- /dev/null
+++ b/u-boot/board/lantec/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    net/libnet.o			(.text*)
+    arch/powerpc/lib/libpowerpc.o	(.text*)
+    drivers/rtc/librtc.o		(.text*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/lantec/u-boot.lds.debug b/u-boot/board/lantec/u-boot.lds.debug
new file mode 100644
index 0000000..deea7e2
--- /dev/null
+++ b/u-boot/board/lantec/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/lart/Makefile b/u-boot/board/lart/Makefile
new file mode 100644
index 0000000..463bc0b
--- /dev/null
+++ b/u-boot/board/lart/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= lart.o flash.o
+SOBJS	:= flashasm.o lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lart/config.mk b/u-boot/board/lart/config.mk
new file mode 100644
index 0000000..b6b5e4d
--- /dev/null
+++ b/u-boot/board/lart/config.mk
@@ -0,0 +1,23 @@
+#
+# LART board with SA1100 cpu
+#
+# see http://www.lart.tudelft.nl/ for more information on LART
+#
+
+#
+# LART has 4 banks of 8 MB DRAM
+#
+# c000'0000
+# c100'0000
+# c800'0000
+# c900'0000
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c178'0000, the upper 1 MB of second bank
+#
+# download areas is c800'0000
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0xc1780000
diff --git a/u-boot/board/lart/flash.c b/u-boot/board/lart/flash.c
new file mode 100644
index 0000000..29a331e
--- /dev/null
+++ b/u-boot/board/lart/flash.c
@@ -0,0 +1,474 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x20000
+#define PARAM_SECT_SIZE 0x4000
+
+/* puzzle magic for lart
+ * data_*_flash are def'd in flashasm.S
+ */
+
+extern u32 data_from_flash(u32);
+extern u32 data_to_flash(u32);
+
+#define PUZZLE_FROM_FLASH(x)	data_from_flash((x))
+#define PUZZLE_TO_FLASH(x)	data_to_flash((x))
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+    {
+	ulong flashbase = 0;
+	flash_info[i].flash_id =
+	  (INTEL_MANUFACT & FLASH_VENDMASK) |
+	  (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+	if (i == 0)
+	  flashbase = PHYS_FLASH_1;
+	else
+	  panic("configured too many flash banks!\n");
+	for (j = 0; j < flash_info[i].sector_count; j++)
+	{
+	    if (j <= 7)
+	    {
+		flash_info[i].start[j] = flashbase + j * PARAM_SECT_SIZE;
+	    }
+	    else
+	    {
+		flash_info[i].start[j] = flashbase + (j - 7)*MAIN_SECT_SIZE;
+	    }
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    switch (info->flash_id & FLASH_VENDMASK)
+    {
+    case (INTEL_MANUFACT & FLASH_VENDMASK):
+	printf("Intel: ");
+	break;
+    default:
+	printf("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK)
+    {
+    case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
+	printf("2x 28F160F3B (16Mbit)\n");
+	break;
+    default:
+	printf("Unknown Chip Type\n");
+	goto Done;
+	break;
+    }
+
+    printf("  Size: %ld MB in %d Sectors\n",
+	   info->size >> 20, info->sector_count);
+
+    printf("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; i++)
+    {
+	if ((i % 5) == 0)
+	{
+	    printf ("\n   ");
+	}
+	printf (" %08lX%s", info->start[i],
+		info->protect[i] ? " (RO)" : "     ");
+    }
+    printf ("\n");
+
+Done:
+    ;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT)
+	{
+		printf ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY)
+	{
+		printf ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR)
+	{
+		printf ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR)
+	{
+		printf ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR)
+	{
+		printf ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR)
+	{
+		printf ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR)
+	{
+		printf ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND)
+	{
+		printf ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND)
+	{
+		printf ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    ulong result;
+    int iflag, cflag, prot, sect;
+    int rc = ERR_OK;
+
+    /* first look for protection bits */
+
+    if (info->flash_id == FLASH_UNKNOWN)
+	return ERR_UNKNOWN_FLASH_TYPE;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	return ERR_INVAL;
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) !=
+	(INTEL_MANUFACT & FLASH_VENDMASK)) {
+	return ERR_UNKNOWN_FLASH_VENDOR;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+    if (prot)
+	return ERR_PROTECTED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+    {
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	if (info->protect[sect] == 0)
+	{	/* not protected */
+	    vu_long *addr = (vu_long *)(info->start[sect]);
+
+	    *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
+	    *addr = PUZZLE_TO_FLASH(CMD_ERASE_SETUP);
+	    *addr = PUZZLE_TO_FLASH(CMD_ERASE_CONFIRM);
+
+	    /* wait until flash is ready */
+	    do
+	    {
+		/* check timeout */
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+		{
+		    *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
+		    result = BIT_TIMEOUT;
+		    break;
+		}
+
+		result = PUZZLE_FROM_FLASH(*addr);
+	    }  while (~result & BIT_BUSY);
+
+	    *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+	    if ((rc = flash_error(result)) != ERR_OK)
+		goto outahere;
+
+	    printf("ok.\n");
+	}
+	else /* it was protected */
+	{
+	    printf("protected!\n");
+	}
+    }
+
+    if (ctrlc())
+      printf("User Interrupt!\n");
+
+outahere:
+    /* allow flash to settle - wait 10 ms */
+    udelay_masked(10000);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long *)dest;
+    ulong result;
+    int rc = ERR_OK;
+    int cflag, iflag;
+
+    /* Check if Flash is (sufficiently) erased
+     */
+    result = PUZZLE_FROM_FLASH(*addr);
+    if ((result & data) != data)
+	return ERR_NOT_ERASED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
+    *addr = PUZZLE_TO_FLASH(CMD_PROGRAM);
+    *addr = data;
+
+    /* arm simple, non interrupt dependent timer */
+    reset_timer_masked();
+
+    /* wait until flash is ready */
+    do
+    {
+	/* check timeout */
+	if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+	{
+	    *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
+	    result = BIT_TIMEOUT;
+	    break;
+	}
+
+	result = PUZZLE_FROM_FLASH(*addr);
+    }  while (~result & BIT_BUSY);
+
+    *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+    rc = flash_error(result);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int l;
+    int i, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data >> 8) | (*src++ << 24);
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = *((vu_long*)src);
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	src += 4;
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data >> 8) | (*src++ << 24);
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data >> 8) | (*(uchar *)cp << 24);
+    }
+
+    return write_word(info, wp, data);
+}
diff --git a/u-boot/board/lart/flashasm.S b/u-boot/board/lart/flashasm.S
new file mode 100644
index 0000000..9021972
--- /dev/null
+++ b/u-boot/board/lart/flashasm.S
@@ -0,0 +1,177 @@
+/*
+ * flashasm.S: flash magic for LART
+ *
+ * Copyright (C) 1999 2000 2001 Jan-Derk bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+.text
+
+
+.globl	data_to_flash
+.globl	data_from_flash
+	/* Subroutine that takes data in r0 and formats it so it will be in */
+	/* the correct order for the internal flash */
+	/* used for LART only */
+data_to_flash:
+	mov	r1, #0x0
+
+	tst	r0, #0x00000001
+	orrne	r1, r1, #0x00001000
+	tst	r0, #0x00000002
+	orrne	r1, r1, #0x00004000
+	tst	r0, #0x00000004
+	orrne	r1, r1, #0x00000800
+	tst	r0, #0x00000008
+	orrne	r1, r1, #0x00000200
+	tst	r0, #0x00000010
+	orrne	r1, r1, #0x00000001
+	tst	r0, #0x00000020
+	orrne	r1, r1, #0x00000004
+	tst	r0, #0x00000040
+	orrne	r1, r1, #0x00000080
+	tst	r0, #0x00000080
+	orrne	r1, r1, #0x00000020
+
+	tst	r0, #0x00000100
+	orrne	r1, r1, #0x00002000
+	tst	r0, #0x00000200
+	orrne	r1, r1, #0x00008000
+	tst	r0, #0x00000400
+	orrne	r1, r1, #0x00000400
+	tst	r0, #0x00000800
+	orrne	r1, r1, #0x00000100
+	tst	r0, #0x00001000
+	orrne	r1, r1, #0x00000002
+	tst	r0, #0x00002000
+	orrne	r1, r1, #0x00000008
+	tst	r0, #0x00004000
+	orrne	r1, r1, #0x00000040
+	tst	r0, #0x00008000
+	orrne	r1, r1, #0x00000010
+
+	tst	r0, #0x00010000
+	orrne	r1, r1, #0x00100000
+	tst	r0, #0x00020000
+	orrne	r1, r1, #0x00400000
+	tst	r0, #0x00040000
+	orrne	r1, r1, #0x00080000
+	tst	r0, #0x00080000
+	orrne	r1, r1, #0x00020000
+	tst	r0, #0x00100000
+	orrne	r1, r1, #0x01000000
+	tst	r0, #0x00200000
+	orrne	r1, r1, #0x04000000
+	tst	r0, #0x00400000
+	orrne	r1, r1, #0x80000000
+	tst	r0, #0x00800000
+	orrne	r1, r1, #0x20000000
+
+	tst	r0, #0x01000000
+	orrne	r1, r1, #0x00200000
+	tst	r0, #0x02000000
+	orrne	r1, r1, #0x00800000
+	tst	r0, #0x04000000
+	orrne	r1, r1, #0x00040000
+	tst	r0, #0x08000000
+	orrne	r1, r1, #0x00010000
+	tst	r0, #0x10000000
+	orrne	r1, r1, #0x02000000
+	tst	r0, #0x20000000
+	orrne	r1, r1, #0x08000000
+	tst	r0, #0x40000000
+	orrne	r1, r1, #0x40000000
+	tst	r0, #0x80000000
+	orrne	r1, r1, #0x10000000
+
+	mov	r0, r1
+	mov	pc, lr
+
+	/* Takes data received from the flash, and unshuffles it. */
+data_from_flash:
+	mov	r1, #0x00
+
+	tst	r0, #0x00000001
+	orrne	r1, r1, #0x00000010
+	tst	r0, #0x00000002
+	orrne	r1, r1, #0x00001000
+	tst	r0, #0x00000004
+	orrne	r1, r1, #0x00000020
+	tst	r0, #0x00000008
+	orrne	r1, r1, #0x00002000
+	tst	r0, #0x00000010
+	orrne	r1, r1, #0x00008000
+	tst	r0, #0x00000020
+	orrne	r1, r1, #0x00000080
+	tst	r0, #0x00000040
+	orrne	r1, r1, #0x00004000
+	tst	r0, #0x00000080
+	orrne	r1, r1, #0x00000040
+
+	tst	r0, #0x00000100
+	orrne	r1, r1, #0x00000800
+	tst	r0, #0x00000200
+	orrne	r1, r1, #0x00000008
+	tst	r0, #0x00000400
+	orrne	r1, r1, #0x00000400
+	tst	r0, #0x00000800
+	orrne	r1, r1, #0x00000004
+	tst	r0, #0x00001000
+	orrne	r1, r1, #0x00000001
+	tst	r0, #0x00002000
+	orrne	r1, r1, #0x00000100
+	tst	r0, #0x00004000
+	orrne	r1, r1, #0x00000002
+	tst	r0, #0x00008000
+	orrne	r1, r1, #0x00000200
+
+	tst	r0, #0x00010000
+	orrne	r1, r1, #0x08000000
+	tst	r0, #0x00020000
+	orrne	r1, r1, #0x00080000
+	tst	r0, #0x00040000
+	orrne	r1, r1, #0x04000000
+	tst	r0, #0x00080000
+	orrne	r1, r1, #0x00040000
+	tst	r0, #0x00100000
+	orrne	r1, r1, #0x00010000
+	tst	r0, #0x00200000
+	orrne	r1, r1, #0x01000000
+	tst	r0, #0x00400000
+	orrne	r1, r1, #0x00020000
+	tst	r0, #0x00800000
+	orrne	r1, r1, #0x02000000
+
+	tst	r0, #0x01000000
+	orrne	r1, r1, #0x00100000
+	tst	r0, #0x02000000
+	orrne	r1, r1, #0x10000000
+	tst	r0, #0x04000000
+	orrne	r1, r1, #0x00200000
+	tst	r0, #0x08000000
+	orrne	r1, r1, #0x20000000
+	tst	r0, #0x10000000
+	orrne	r1, r1, #0x80000000
+	tst	r0, #0x20000000
+	orrne	r1, r1, #0x00800000
+	tst	r0, #0x40000000
+	orrne	r1, r1, #0x40000000
+	tst	r0, #0x80000000
+	orrne	r1, r1, #0x00400000
+
+	mov	r0, r1
+	mov	pc, lr
diff --git a/u-boot/board/lart/lart.c b/u-boot/board/lart/lart.c
new file mode 100644
index 0000000..a0b459f
--- /dev/null
+++ b/u-boot/board/lart/lart.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of LART-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_LART;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	bd_t *bd = gd->bd;
+
+	bd->bi_dram[0].start = PHYS_SDRAM_1;
+	bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	bd->bi_dram[1].start = PHYS_SDRAM_2;
+	bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	bd->bi_dram[2].start = PHYS_SDRAM_3;
+	bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	bd->bi_dram[3].start = PHYS_SDRAM_4;
+	bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/lart/lowlevel_init.S b/u-boot/board/lart/lowlevel_init.S
new file mode 100644
index 0000000..db9fd63
--- /dev/null
+++ b/u-boot/board/lart/lowlevel_init.S
@@ -0,0 +1,94 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+#define	MDCNFG	0x00
+#define MDCAS0	0x04
+#define MDCAS1	0x08
+#define MDCAS2	0x0c
+#define MSC0	0x10
+#define MSC1	0x14
+#define MECR	0x18
+
+mdcas0:		.long	0xc71c703f
+mdcas1:		.long	0xffc71c71
+mdcas2:		.long	0xffffffff
+/* mdcnfg:		.long   0x0bb2bcbf */
+mdcnfg:		.long	0x0334b22f	@ alt
+/* mcs0:		.long   0xfff8fff8 */
+msc0:		.long	0xad8c4888	@ alt
+mecr:		.long	0x00060006
+/* mecr:		.long	0x994a994a	@ alt */
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	r0, MEM_BASE
+
+	/* Setup the flash memory */
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+
+	/* Set up the DRAM */
+
+	/* MDCAS0 */
+	ldr	r1, mdcas0
+	str	r1, [r0, #MDCAS0]
+
+	/* MDCAS1 */
+	ldr	r1, mdcas1
+	str	r1, [r0, #MDCAS1]
+
+	/* MDCAS2 */
+	ldr	r1, mdcas2
+	str	r1, [r0, #MDCAS2]
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Set up PCMCIA space */
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	/* Load something to activate bank */
+	ldr	r1, MEM_START
+
+.rept	8
+	ldr	r0, [r1]
+.endr
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/linkstation/Makefile b/u-boot/board/linkstation/Makefile
new file mode 100644
index 0000000..55674b7
--- /dev/null
+++ b/u-boot/board/linkstation/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+OBJS	= $(BOARD).o ide.o hwctl.o avr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(OBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/linkstation/avr.c b/u-boot/board/linkstation/avr.c
new file mode 100644
index 0000000..ec6d400
--- /dev/null
+++ b/u-boot/board/linkstation/avr.c
@@ -0,0 +1,293 @@
+/*
+ * avr.c
+ *
+ * AVR functions
+ *
+ * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <ns16550.h>
+#include <stdio_dev.h>
+
+/* Button codes from the AVR */
+#define PWRR			0x20		/* Power button release	*/
+#define PWRP			0x21		/* Power button push	*/
+#define RESR			0x22		/* Reset button release	*/
+#define RESP			0x23		/* Reset button push	*/
+#define AVRINIT			0x33		/* Init complete	*/
+#define AVRRESET		0x31		/* Reset request	*/
+
+/* LED commands */
+#define PWRBLINKSTRT		'['		/* Blink power LED	*/
+#define PWRBLINKSTOP		'Z'		/* Solid power LED	*/
+#define HDDLEDON		'W'		/* HDD LED on		*/
+#define HDDLEDOFF		'V'		/* HDD LED off		*/
+#define HDDBLINKSTRT		'Y'		/* HDD LED start blink	*/
+#define HDDBLINKSTOP		'X'		/* HDD LED stop blink	*/
+
+/* Timings for LEDs blinking to show choice */
+#define PULSETIME		250		/* msecs		*/
+#define LONGPAUSE		(5 * PULSETIME)
+
+/* Button press times */
+#define PUSHHOLD		1000		/* msecs		*/
+#define NOBUTTON		(6 * (LONGPAUSE+PULSETIME))
+
+/* Boot and console choices */
+#define MAX_BOOT_CHOICE		3
+
+static char *consoles[] = {
+	"serial",
+#if defined(CONFIG_NETCONSOLE)
+	"nc",
+#endif
+};
+#define MAX_CONS_CHOICE		(sizeof(consoles)/sizeof(char *))
+
+#if !defined(CONFIG_NETCONSOLE)
+#define DEF_CONS_CHOICE		0
+#else
+#define DEF_CONS_CHOICE		1
+#endif
+
+#define perror(fmt, args...) printf("%s: " fmt, __FUNCTION__ , ##args)
+
+extern void miconCntl_SendCmd(unsigned char dat);
+extern void miconCntl_DisWDT(void);
+
+static int boot_stop;
+
+static int boot_choice = 1;
+static int cons_choice = DEF_CONS_CHOICE;
+
+static char envbuffer[16];
+
+void init_AVR_DUART (void)
+{
+	NS16550_t AVR_port = (NS16550_t) CONFIG_SYS_NS16550_COM2;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / 9600;
+
+	/*
+	 * AVR port init sequence taken from
+	 * the original Linkstation init code
+	 * Normal U-Boot serial reinit doesn't
+	 * work because the AVR uses even parity
+	 */
+	AVR_port->lcr = 0x00;
+	AVR_port->ier = 0x00;
+	AVR_port->lcr = UART_LCR_BKSE;
+	AVR_port->dll = clock_divisor & 0xff;
+	AVR_port->dlm = (clock_divisor >> 8) & 0xff;
+	AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS;
+	AVR_port->mcr = 0x00;
+	AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR;
+
+	miconCntl_DisWDT();
+
+	boot_stop = 0;
+	miconCntl_SendCmd(PWRBLINKSTRT);
+}
+
+static inline int avr_tstc(void)
+{
+	return (NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2));
+}
+
+static inline char avr_getc(void)
+{
+	return (NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2));
+}
+
+static int push_timeout(char button_code)
+{
+	ulong push_start = get_timer(0);
+	while (get_timer(push_start) <= PUSHHOLD)
+		if (avr_tstc() && avr_getc() == button_code)
+			return 0;
+	return 1;
+}
+
+static void next_boot_choice(void)
+{
+	ulong return_start;
+	ulong pulse_start;
+	int on_times;
+	int button_on;
+	int led_state;
+	char c;
+
+	button_on = 0;
+	return_start = get_timer(0);
+
+	on_times = boot_choice;
+	led_state = 0;
+	miconCntl_SendCmd(HDDLEDOFF);
+	pulse_start = get_timer(0);
+
+	while (get_timer(return_start) <= NOBUTTON || button_on) {
+		if (avr_tstc()) {
+			c = avr_getc();
+			if (c == PWRP)
+				button_on = 1;
+			else if (c == PWRR) {
+				button_on = 0;
+				return_start = get_timer(0);
+				if (++boot_choice > MAX_BOOT_CHOICE)
+					boot_choice = 1;
+				sprintf(envbuffer, "bootcmd%d", boot_choice);
+				if (getenv(envbuffer)) {
+					sprintf(envbuffer, "run bootcmd%d", boot_choice);
+					setenv("bootcmd", envbuffer);
+				}
+				on_times = boot_choice;
+				led_state = 1;
+				miconCntl_SendCmd(HDDLEDON);
+				pulse_start = get_timer(0);
+			} else {
+				perror("Unexpected code: 0x%02X\n", c);
+			}
+		}
+		if (on_times && get_timer(pulse_start) > PULSETIME) {
+			if (led_state == 1) {
+				--on_times;
+				led_state = 0;
+				miconCntl_SendCmd(HDDLEDOFF);
+			} else {
+				led_state = 1;
+				miconCntl_SendCmd(HDDLEDON);
+			}
+			pulse_start = get_timer(0);
+		}
+		if (!on_times && get_timer(pulse_start) > LONGPAUSE) {
+			on_times = boot_choice;
+			led_state = 1;
+			miconCntl_SendCmd(HDDLEDON);
+			pulse_start = get_timer(0);
+		}
+	}
+	if (led_state)
+		miconCntl_SendCmd(HDDLEDOFF);
+}
+
+void next_cons_choice(int console)
+{
+	ulong return_start;
+	ulong pulse_start;
+	int on_times;
+	int button_on;
+	int led_state;
+	char c;
+
+	button_on = 0;
+	cons_choice = console;
+	return_start = get_timer(0);
+
+	on_times = cons_choice+1;
+	led_state = 1;
+	miconCntl_SendCmd(HDDLEDON);
+	pulse_start = get_timer(0);
+
+	while (get_timer(return_start) <= NOBUTTON || button_on) {
+		if (avr_tstc()) {
+			c = avr_getc();
+			if (c == RESP)
+				button_on = 1;
+			else if (c == RESR) {
+				button_on = 0;
+				return_start = get_timer(0);
+				cons_choice = (cons_choice + 1) % MAX_CONS_CHOICE;
+				console_assign(stdin, consoles[cons_choice]);
+				console_assign(stdout, consoles[cons_choice]);
+				console_assign(stderr, consoles[cons_choice]);
+				on_times = cons_choice+1;
+				led_state = 0;
+				miconCntl_SendCmd(HDDLEDOFF);
+				pulse_start = get_timer(0);
+			} else {
+				perror("Unexpected code: 0x%02X\n", c);
+			}
+		}
+		if (on_times && get_timer(pulse_start) > PULSETIME) {
+			if (led_state == 0) {
+				--on_times;
+				led_state = 1;
+				miconCntl_SendCmd(HDDLEDON);
+			} else {
+				led_state = 0;
+				miconCntl_SendCmd(HDDLEDOFF);
+			}
+			pulse_start = get_timer(0);
+		}
+		if (!on_times && get_timer(pulse_start) > LONGPAUSE) {
+			on_times = cons_choice+1;
+			led_state = 0;
+			miconCntl_SendCmd(HDDLEDOFF);
+			pulse_start = get_timer(0);
+		}
+	}
+	if (led_state);
+	miconCntl_SendCmd(HDDLEDOFF);
+}
+
+int avr_input(void)
+{
+	char avr_button;
+
+	if (!avr_tstc())
+		return 0;
+
+	avr_button = avr_getc();
+	switch (avr_button) {
+	case PWRP:
+		if (push_timeout(PWRR)) {
+			/* Timeout before power button release */
+			boot_stop = ~boot_stop;
+			if (boot_stop)
+				miconCntl_SendCmd(PWRBLINKSTOP);
+			else
+				miconCntl_SendCmd(PWRBLINKSTRT);
+			/* Wait for power button release */
+			while (avr_getc() != PWRR)
+				;
+		} else
+			/* Power button released */
+			next_boot_choice();
+		break;
+	case RESP:
+		/* Wait for Reset button release */
+		while (avr_getc() != RESR)
+			;
+		next_cons_choice(cons_choice);
+		break;
+	case AVRINIT:
+		return 0;
+	default:
+		perror("Unexpected code: 0x%02X\n", avr_button);
+		return 0;
+	}
+	if (boot_stop)
+		return (-3);
+	else
+		return (-2);
+}
+
+void avr_StopBoot(void)
+{
+	boot_stop = ~0;
+	miconCntl_SendCmd(PWRBLINKSTOP);
+}
diff --git a/u-boot/board/linkstation/hwctl.c b/u-boot/board/linkstation/hwctl.c
new file mode 100644
index 0000000..9fd56ae
--- /dev/null
+++ b/u-boot/board/linkstation/hwctl.c
@@ -0,0 +1,135 @@
+/*
+ * hwctl.c
+ *
+ * LinkStation HW Control Driver
+ *
+ * Copyright (C) 2001-2004  BUFFALO INC.
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ * Drivers based on or derived from this code fall under the GPL and must
+ * retain the authorship, copyright and license notice.  This file is not
+ * a complete program and may only be used when the entire operating
+ * system is licensed under the GPL.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#define mdelay(n)	udelay((n)*1000)
+
+#define AVR_PORT CONFIG_SYS_NS16550_COM2
+
+/* 2005.5.10 BUFFALO add */
+/*--------------------------------------------------------------*/
+static inline void miconCntl_SendUart(unsigned char dat)
+{
+	out_8((unsigned char *)AVR_PORT, dat);
+	mdelay(1);
+}
+
+/*--------------------------------------------------------------*/
+void miconCntl_SendCmd(unsigned char dat)
+{
+	int i;
+
+	for (i=0; i<4; i++){
+		miconCntl_SendUart(dat);
+	}
+}
+
+/*--------------------------------------------------------------*/
+void miconCntl_FanLow(void)
+{
+#ifdef CONFIG_HTGL
+	miconCntl_SendCmd(0x5C);
+#endif
+}
+
+/*--------------------------------------------------------------*/
+void miconCntl_FanHigh(void)
+{
+#ifdef CONFIG_HTGL
+	miconCntl_SendCmd(0x5D);
+#endif
+}
+
+/*--------------------------------------------------------------*/
+/* 1000Mbps */
+void miconCntl_Eth1000M(int up)
+{
+#ifdef CONFIG_HTGL
+	if (up)
+		miconCntl_SendCmd(0x93);
+	else
+		miconCntl_SendCmd(0x92);
+#else
+	if (up)
+		miconCntl_SendCmd(0x5D);
+	else
+		miconCntl_SendCmd(0x5C);
+#endif
+}
+
+/*--------------------------------------------------------------*/
+/* 100Mbps */
+void miconCntl_Eth100M(int up)
+{
+#ifdef CONFIG_HTGL
+	if (up)
+		miconCntl_SendCmd(0x91);
+	else
+		miconCntl_SendCmd(0x90);
+#else
+	if (up)
+		miconCntl_SendCmd(0x5C);
+#endif
+}
+
+/*--------------------------------------------------------------*/
+/* 10Mbps */
+void miconCntl_Eth10M(int up)
+{
+#ifdef CONFIG_HTGL
+	if (up)
+		miconCntl_SendCmd(0x8F);
+	else
+		miconCntl_SendCmd(0x8E);
+#else
+	if (up)
+		miconCntl_SendCmd(0x5C);
+#endif
+}
+
+/*--------------------------------------------------------------*/
+/*  */
+void miconCntl_5f(void)
+{
+	miconCntl_SendCmd(0x5F);
+	mdelay(100);
+}
+
+/*--------------------------------------------------------------*/
+/* "reboot start" signal */
+void miconCntl_Reboot(void)
+{
+	miconCntl_SendCmd(0x43);
+}
+
+/*--------------------------------------------------------------*/
+/* Disable watchdog timer */
+void miconCntl_DisWDT(void)
+{
+	miconCntl_SendCmd(0x41); /* A */
+	miconCntl_SendCmd(0x46); /* F */
+	miconCntl_SendCmd(0x4A); /* J */
+	miconCntl_SendCmd(0x3E); /* > */
+	miconCntl_SendCmd(0x56); /* V */
+	miconCntl_SendCmd(0x3E); /* > */
+	miconCntl_SendCmd(0x5A); /* Z */
+	miconCntl_SendCmd(0x56); /* V */
+	miconCntl_SendCmd(0x4B); /* K */
+}
diff --git a/u-boot/board/linkstation/ide.c b/u-boot/board/linkstation/ide.c
new file mode 100644
index 0000000..568fdf5
--- /dev/null
+++ b/u-boot/board/linkstation/ide.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* ide.c - ide support functions */
+
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+#define IT8212_PCI_CpuCONTROL		0x5e
+#define IT8212_PCI_PciModeCONTROL	0x50
+#define IT8212_PCI_IdeIoCONFIG		0x40
+#define IT8212_PCI_IdeBusSkewCONTROL	0x4c
+#define IT8212_PCI_IdeDrivingCURRENT	0x42
+
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
+extern struct pci_controller hose;
+
+int ide_preinit (void)
+{
+	int status;
+	pci_dev_t devbusfn;
+	int l;
+
+	status = 1;
+	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
+		ide_bus_offset[l] = -ATA_STATUS;
+	}
+	devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0);
+	if (devbusfn == -1)
+		devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0);
+	if (devbusfn != -1) {
+		u32 ide_bus_offset32;
+
+		status = 0;
+
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+							   &ide_bus_offset32);
+		ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe;
+		ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
+							 ide_bus_offset[0] & 0xfffffffe,
+							 PCI_REGION_IO);
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2,
+				      (u32 *) &ide_bus_offset[1]);
+		ide_bus_offset[1] &= 0xfffffffe;
+		ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
+							 ide_bus_offset[1] & 0xfffffffe,
+							 PCI_REGION_IO);
+	}
+
+	if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) {
+		pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01);
+		pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00);
+		pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047);
+#ifdef CONFIG_IT8212_SECONDARY_ENABLE
+		pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3);
+#else
+		pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031);
+#endif
+		pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204);
+/* __LS_COMMENT__ BUFFALO changed 2004.11.10  changed for EMI */
+		pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */
+/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */
+/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */
+/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */
+/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */
+		pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00);
+	}
+
+	return (status);
+}
+
+void ide_set_reset (int flag) {
+	return;
+}
+
+#endif /* CONFIG_CMD_IDE */
diff --git a/u-boot/board/linkstation/linkstation.c b/u-boot/board/linkstation/linkstation.c
new file mode 100644
index 0000000..e564e50
--- /dev/null
+++ b/u-boot/board/linkstation/linkstation.c
@@ -0,0 +1,137 @@
+/*
+ * linkstation.c
+ *
+ * Misc LinkStation specific functions
+ *
+ * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <version.h>
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <netdev.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void init_AVR_DUART(void);
+
+int checkboard (void)
+{
+	char *p;
+	bd_t *bd = gd->bd;
+
+	init_AVR_DUART();
+
+	if ((p = getenv ("console_nr")) != NULL) {
+		unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
+
+		bd->bi_baudrate &= ~3;
+		bd->bi_baudrate |= con_nr & 3;
+	}
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE));
+}
+
+/*
+ * Initialize PCI Devices
+ */
+#ifdef CONFIG_PCI
+
+#ifndef CONFIG_PCI_PNP
+
+static struct pci_config_table pci_linkstation_config_table[] = {
+	/* vendor, device, class */
+	/* bus, dev, func */
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x0b, 0,		/* AN983B or RTL8110S  */
+								/* ethernet controller */
+	  pci_cfgfunc_config_device, { PCI_ETH_IOADDR,
+				       PCI_ETH_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x0c, 0,		/* SII680 or IT8211AF */
+								/* ide controller     */
+	  pci_cfgfunc_config_device, { PCI_IDE_IOADDR,
+				       PCI_IDE_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x0e, 0,		/* D720101 USB controller, 1st USB 1.1 */
+	  pci_cfgfunc_config_device, { PCI_USB0_IOADDR,
+				       PCI_USB0_MEMADDR,
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x0e, 1,		/* D720101 USB controller, 2nd USB 1.1 */
+	  pci_cfgfunc_config_device, { PCI_USB1_IOADDR,
+				       PCI_USB1_MEMADDR,
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x0e, 2,		/* D720101 USB controller, USB 2.0 */
+	  pci_cfgfunc_config_device, { PCI_USB2_IOADDR,
+				       PCI_USB2_MEMADDR,
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_linkstation_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+
+	/* Reset USB 1.1 */
+	/* Haven't seen any change without these on a HG, maybe it is
+	 * needed on other models */
+	out_le32((volatile unsigned*)(PCI_USB0_MEMADDR + 8), 1);
+	out_le32((volatile unsigned*)(PCI_USB1_MEMADDR + 8), 1);
+}
+#endif /* CONFIG_PCI */
+
+#define UART_DCR       0x80004511
+int board_early_init_f (void)
+{
+	/* set DUART mode */
+	out_8((volatile u8*)UART_DCR, 1);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/logicpd/am3517evm/Makefile b/u-boot/board/logicpd/am3517evm/Makefile
new file mode 100644
index 0000000..83fab0e
--- /dev/null
+++ b/u-boot/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,46 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= am3517evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/logicpd/am3517evm/am3517evm.c b/u-boot/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 0000000..bbb6e83
--- /dev/null
+++ b/u-boot/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
diff --git a/u-boot/board/logicpd/am3517evm/am3517evm.h b/u-boot/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 0000000..3d74ef1
--- /dev/null
+++ b/u-boot/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,445 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"AM3517EVM Board",
+	"NAND",
+};
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	 /*sdrc_strben_dly1*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	/* WriteProtect */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	/*SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/u-boot/board/logicpd/am3517evm/config.mk b/u-boot/board/logicpd/am3517evm/config.mk
new file mode 100644
index 0000000..71ec5d0
--- /dev/null
+++ b/u-boot/board/logicpd/am3517evm/config.mk
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/logicpd/imx27lite/Makefile b/u-boot/board/logicpd/imx27lite/Makefile
new file mode 100644
index 0000000..944434b
--- /dev/null
+++ b/u-boot/board/logicpd/imx27lite/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= imx27lite.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/logicpd/imx27lite/config.mk b/u-boot/board/logicpd/imx27lite/config.mk
new file mode 100644
index 0000000..018d920
--- /dev/null
+++ b/u-boot/board/logicpd/imx27lite/config.mk
@@ -0,0 +1,5 @@
+# with relocation CONFIG_SYS_TEXT_BASE can be anything, and making it 0
+# makes relative and absolute relocation fixups interchangeable.
+#CONFIG_SYS_TEXT_BASE = 0
+
+CONFIG_SYS_TEXT_BASE = 0xc0000000
diff --git a/u-boot/board/logicpd/imx27lite/imx27lite.c b/u-boot/board/logicpd/imx27lite/imx27lite.c
new file mode 100644
index 0000000..6eb5cc2
--- /dev/null
+++ b/u-boot/board/logicpd/imx27lite/imx27lite.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+	struct system_control_regs *sc_regs =
+		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+#endif
+
+	gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_MXC_UART
+	mx27_uart_init_pins();
+#endif
+#ifdef CONFIG_FEC_MXC
+	mx27_fec_init_pins();
+	imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
+	writel(readl(&regs->port[PORTC].dr) | (1 << 31),
+				&regs->port[PORTC].dr);
+#endif
+#ifdef CONFIG_MXC_MMC
+#if defined(CONFIG_MAGNESIUM)
+	mx27_sd1_init_pins();
+#else
+	mx27_sd2_init_pins();
+#endif
+#endif
+
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+	/*
+	 * set in FMCR NF_FMS Bit(5) to 1
+	 * (NAND Flash with 2 Kbyte page size)
+	 */
+	writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
+#endif
+	return 0;
+}
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+			PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+			PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+int checkboard(void)
+{
+	puts ("Board: ");
+	puts(CONFIG_BOARDNAME);
+	return 0;
+}
diff --git a/u-boot/board/logicpd/imx27lite/lowlevel_init.S b/u-boot/board/logicpd/imx27lite/lowlevel_init.S
new file mode 100644
index 0000000..e2cdecb
--- /dev/null
+++ b/u-boot/board/logicpd/imx27lite/lowlevel_init.S
@@ -0,0 +1,170 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+SOC_ESDCTL_BASE_W:	.word	IMX_ESD_BASE
+SOC_SI_ID_REG_W:	.word	IMX_SYSTEM_CTL_BASE
+SDRAM_ESDCFG_T1_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(0)
+SDRAM_ESDCFG_T2_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(3)
+SDRAM_PRECHARGE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
+				 ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_AUTOREF_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
+				 ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_LOADMODE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
+				 ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_NORMAL_CMD_W:	.word	SDRAM_ESDCTL_REGISTER_VAL
+
+.macro init_aipi
+	/*
+	 * setup AIPI1 and AIPI2
+	 */
+	write32 AIPI1_PSR0, AIPI1_PSR0_VAL
+	write32 AIPI1_PSR1, AIPI1_PSR1_VAL
+	write32 AIPI2_PSR0, AIPI2_PSR0_VAL
+	write32 AIPI2_PSR1, AIPI2_PSR1_VAL
+
+.endm /* init_aipi */
+
+.macro init_clock
+	ldr r0, =CSCR
+	/* disable MPLL/SPLL first */
+	ldr r1, [r0]
+	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+	str r1, [r0]
+
+	write32 MPCTL0, MPCTL0_VAL
+	write32 SPCTL0, SPCTL0_VAL
+
+	write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
+
+	/*
+	 * add some delay here
+	 */
+	wait_timer 0x1000
+
+	/* peripheral clock divider */
+	write32 PCDR0, PCDR0_VAL
+	write32 PCDR1, PCDR1_VAL
+
+	/* Configure PCCR0 and PCCR1 */
+	write32 PCCR0, PCCR0_VAL
+	write32 PCCR1, PCCR1_VAL
+
+.endm /* init_clock */
+
+.macro sdram_init
+	ldr r0, SOC_ESDCTL_BASE_W
+	mov r2, #PHYS_SDRAM_1
+
+	/* Do initial reset */
+	mov r1, #ESDMISC_MDDR_DL_RST
+	str r1, [r0, #ESDMISC_ROF]
+
+	/* Hold for more than 200ns */
+	wait_timer 0x10000
+
+	/* Activate LPDDR iface */
+	mov r1, #ESDMISC_MDDREN
+	str r1, [r0, #ESDMISC_ROF]
+
+	/* Check The chip version TO1 or TO2 */
+	ldr r1, SOC_SI_ID_REG_W
+	ldr r1, [r1]
+	ands r1, r1, #0xF0000000
+	/* add Latency on CAS only for TO2 */
+	ldreq r1, SDRAM_ESDCFG_T2_W
+	ldrne r1, SDRAM_ESDCFG_T1_W
+	str r1, [r0, #ESDCFG0_ROF]
+
+	/* Run initialization sequence */
+	ldr r1, SDRAM_PRECHARGE_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_AUTOREF_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_LOADMODE_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+	ldrb r1, [r3]
+
+	ldr r1, SDRAM_NORMAL_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+	/* 2nd sdram */
+	mov r2, #PHYS_SDRAM_2
+
+	/* Check The chip version TO1 or TO2 */
+	ldr r1, SOC_SI_ID_REG_W
+	ldr r1, [r1]
+	ands r1, r1, #0xF0000000
+	/* add Latency on CAS only for TO2 */
+	ldreq r1, SDRAM_ESDCFG_T2_W
+	ldrne r1, SDRAM_ESDCFG_T1_W
+	str r1, [r0, #ESDCFG1_ROF]
+
+	/* Run initialization sequence */
+	ldr r1, SDRAM_PRECHARGE_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_AUTOREF_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_LOADMODE_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+	ldrb r1, [r3]
+
+	ldr r1, SDRAM_NORMAL_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
+
+.endm /* sdram_init */
+
+.globl	lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+	init_aipi
+
+	init_clock
+
+	sdram_init
+
+	mov	pc,r10
diff --git a/u-boot/board/logicpd/imx31_litekit/Makefile b/u-boot/board/logicpd/imx31_litekit/Makefile
new file mode 100644
index 0000000..e604c31
--- /dev/null
+++ b/u-boot/board/logicpd/imx31_litekit/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= imx31_litekit.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/logicpd/imx31_litekit/config.mk b/u-boot/board/logicpd/imx31_litekit/config.mk
new file mode 100644
index 0000000..a7887ba
--- /dev/null
+++ b/u-boot/board/logicpd/imx31_litekit/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0xa0000000
diff --git a/u-boot/board/logicpd/imx31_litekit/imx31_litekit.c b/u-boot/board/logicpd/imx31_litekit/imx31_litekit.c
new file mode 100644
index 0000000..a07ba0e
--- /dev/null
+++ b/u-boot/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -0,0 +1,93 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+void
+dram_init_banksize (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+int board_init (void)
+{
+	__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+	__REG(CSCR_L(0)) = 0xa0330d01;
+	__REG(CSCR_A(0)) = 0x00220800;
+
+	__REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
+	__REG(CSCR_L(4)) = 0x444a4541;
+	__REG(CSCR_A(4)) = 0x44443302;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* SPI2 */
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX31LITE; /* board id for linux */
+	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf("Board: i.MX31 Litekit\n");
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/logicpd/imx31_litekit/lowlevel_init.S b/u-boot/board/logicpd/imx31_litekit/lowlevel_init.S
new file mode 100644
index 0000000..0003a42
--- /dev/null
+++ b/u-boot/board/logicpd/imx31_litekit/lowlevel_init.S
@@ -0,0 +1,103 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	REG	CCM_CCMR, 0x074B0BF5
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+
+	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+	REG	0x43FAC26C, 0 /* SDCLK */
+	REG	0x43FAC270, 0 /* CAS */
+	REG	0x43FAC274, 0 /* RAS */
+	REG	0x43FAC27C, 0x1000 /* CS2 (CSD0) */
+	REG	0x43FAC284, 0 /* DQM3 */
+	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	REG	0x43FAC28C, 0
+	REG	0x43FAC290, 0
+	REG	0x43FAC294, 0
+	REG	0x43FAC298, 0
+	REG	0x43FAC29C, 0
+	REG	0x43FAC2A0, 0
+	REG	0x43FAC2A4, 0
+	REG	0x43FAC2A8, 0
+	REG	0x43FAC2AC, 0
+	REG	0x43FAC2B0, 0
+	REG	0x43FAC2B4, 0
+	REG	0x43FAC2B8, 0
+	REG	0x43FAC2BC, 0
+	REG	0x43FAC2C0, 0
+	REG	0x43FAC2C4, 0
+	REG	0x43FAC2C8, 0
+	REG	0x43FAC2CC, 0
+	REG	0x43FAC2D0, 0
+	REG	0x43FAC2D4, 0
+	REG	0x43FAC2D8, 0
+	REG	0x43FAC2DC, 0
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x006ac73a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+	mov	pc, lr
diff --git a/u-boot/board/logicpd/zoom1/Makefile b/u-boot/board/logicpd/zoom1/Makefile
new file mode 100644
index 0000000..75085b4
--- /dev/null
+++ b/u-boot/board/logicpd/zoom1/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= zoom1.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/logicpd/zoom1/config.mk b/u-boot/board/logicpd/zoom1/config.mk
new file mode 100644
index 0000000..e89de31
--- /dev/null
+++ b/u-boot/board/logicpd/zoom1/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006-2008
+# Texas Instruments, <www.ti.com>
+#
+# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/logicpd/zoom1/zoom1.c b/u-boot/board/logicpd/zoom1/zoom1.c
new file mode 100644
index 0000000..7ef13cc
--- /dev/null
+++ b/u-boot/board/logicpd/zoom1/zoom1.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Nishanth Menon <nm@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "zoom1.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure zoom board specific configurations
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+	dieid_num_r();
+
+	/*
+	 * Board Reset
+	 * The board is reset by holding the red button on the
+	 * top right front face for eight seconds.
+	 */
+	twl4030_power_reset_init();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	/* platform specific muxes */
+	MUX_ZOOM1_MDK();
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/logicpd/zoom1/zoom1.h b/u-boot/board/logicpd/zoom1/zoom1.h
new file mode 100644
index 0000000..9058d1f
--- /dev/null
+++ b/u-boot/board/logicpd/zoom1/zoom1.h
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Derived from: board/omap3/beagle/beagle.h
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BOARD_ZOOM1_H_
+#define _BOARD_ZOOM1_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Zoom MDK Rev 1",
+	"NAND",
+};
+
+/*
+ * IEN	- Input Enable
+ * IDIS	- Input Disable
+ * PTD	- Pull type Down
+ * PTU	- Pull type Up
+ * DIS	- Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ZOOM1_MDK() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /*GPMC_nCS6*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M7)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTD | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/
+
+#endif /* _BOARD_ZOOM_H_ */
diff --git a/u-boot/board/logicpd/zoom2/Makefile b/u-boot/board/logicpd/zoom2/Makefile
new file mode 100644
index 0000000..17f595e
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+COBJS-y += debug_board.o
+COBJS-y += zoom2_serial.o
+COBJS-$(CONFIG_STATUS_LED) += led.o
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/logicpd/zoom2/config.mk b/u-boot/board/logicpd/zoom2/config.mk
new file mode 100644
index 0000000..9f3f57d
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# Texas Instruments, <www.ti.com>
+#
+# Zoom II uses OMAP3 (ARM-CortexA8) CPU
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 0x80000000 (bank0)
+# 0xA0000000 (bank1)
+# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/logicpd/zoom2/debug_board.c b/u-boot/board/logicpd/zoom2/debug_board.c
new file mode 100644
index 0000000..a4ddf29
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/debug_board.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/gpio.h>
+
+#define DEBUG_BOARD_CONNECTED		1
+#define DEBUG_BOARD_NOT_CONNECTED	0
+
+static int debug_board_connected = DEBUG_BOARD_CONNECTED;
+
+static void zoom2_debug_board_detect (void)
+{
+	int val = 0;
+
+	if (!omap_request_gpio(158)) {
+		/*
+		 * GPIO to query for debug board
+		 * 158 db board query
+		 */
+		omap_set_gpio_direction(158, 1);
+		val = omap_get_gpio_datain(158);
+		omap_free_gpio(158);
+	}
+
+	if (!val)
+		debug_board_connected = DEBUG_BOARD_NOT_CONNECTED;
+}
+
+int zoom2_debug_board_connected (void)
+{
+	static int first_time = 1;
+
+	if (first_time) {
+		zoom2_debug_board_detect ();
+		first_time = 0;
+	}
+	return debug_board_connected;
+}
diff --git a/u-boot/board/logicpd/zoom2/led.c b/u-boot/board/logicpd/zoom2/led.c
new file mode 100644
index 0000000..4e14c58
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/led.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+
+static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+
+/*
+ * GPIO LEDs
+ * 173 red
+ * 154 blue
+ * 61  blue2
+ */
+#define ZOOM2_LED_RED	173
+#define ZOOM2_LED_BLUE	154
+#define ZOOM2_LED_BLUE2	61
+
+void red_LED_off (void)
+{
+	/* red */
+	if (!omap_request_gpio(ZOOM2_LED_RED)) {
+		omap_set_gpio_direction(ZOOM2_LED_RED, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_RED, 0);
+	}
+	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void blue_LED_off (void)
+{
+	/* blue */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE, 0);
+	}
+
+	/* blue 2 */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE2)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE2, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE2, 0);
+	}
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
+}
+
+void red_LED_on (void)
+{
+	blue_LED_off ();
+
+	/* red */
+	if (!omap_request_gpio(ZOOM2_LED_RED)) {
+		omap_set_gpio_direction(ZOOM2_LED_RED, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_RED, 1);
+	}
+	saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void blue_LED_on (void)
+{
+	red_LED_off ();
+
+	/* blue */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE, 1);
+	}
+
+	/* blue 2 */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE2)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE2, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE2, 1);
+	}
+
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void __led_init (led_id_t mask, int state)
+{
+	__led_set (mask, state);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
+			blue_LED_off ();
+		else
+			blue_LED_on ();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_LED_off ();
+		else
+			red_LED_on ();
+	}
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == state)
+			blue_LED_on ();
+		else
+			blue_LED_off ();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_LED_on ();
+		else
+			red_LED_off ();
+	}
+}
diff --git a/u-boot/board/logicpd/zoom2/zoom2.c b/u-boot/board/logicpd/zoom2/zoom2.c
new file mode 100644
index 0000000..76793e4
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/zoom2.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Derived from Zoom1 code by
+ *	Nishanth Menon <nm@ti.com>
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "zoom2.h"
+#include "zoom2_serial.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This the the zoom2, board specific, gpmc configuration for the
+ * quad uart on the debug board.   The more general gpmc configurations
+ * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c
+ *
+ * The details of the setting of the serial gpmc setup are not available.
+ * The values were provided by another party.
+ */
+static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
+	0x00011000,
+	0x001F1F01,
+	0x00080803,
+	0x1D091D09,
+	0x041D1F1F,
+	0x1D0904C4, 0
+};
+
+/* Used to track the revision of the board */
+static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN;
+
+/*
+ * Routine: zoom2_get_revision
+ * Description: Return the revision of the Zoom2 this code is running on.
+ */
+zoom2_revision zoom2_get_revision(void)
+{
+	return revision;
+}
+
+/*
+ * Routine: zoom2_identify
+ * Description: Detect which version of Zoom2 we are running on.
+ */
+void zoom2_identify(void)
+{
+	/*
+	 * To check for production board vs beta board,
+	 * check if gpio 94 is clear.
+	 *
+	 * No way yet to check for alpha board identity.
+	 * Alpha boards were produced in very limited quantities
+	 * and they are not commonly used.  They are mentioned here
+	 * only for completeness.
+	 */
+	if (!omap_request_gpio(94)) {
+		unsigned int val;
+
+		omap_set_gpio_direction(94, 1);
+		val = omap_get_gpio_datain(94);
+		omap_free_gpio(94);
+
+		if (val)
+			revision = ZOOM2_REVISION_BETA;
+		else
+			revision = ZOOM2_REVISION_PRODUCTION;
+	}
+
+	printf("Board revision ");
+	switch (revision) {
+	case ZOOM2_REVISION_PRODUCTION:
+		printf("Production\n");
+		break;
+	case ZOOM2_REVISION_BETA:
+		printf("Beta\n");
+		break;
+	default:
+		printf("Unknown\n");
+		break;
+	}
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init (void)
+{
+	u32 *gpmc_config;
+
+	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */
+
+	/* Configure console support on zoom2 */
+	gpmc_config = gpmc_serial_TL16CP754C;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3],
+			SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
+
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure zoom board specific configurations
+ */
+int misc_init_r(void)
+{
+	zoom2_identify();
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+	dieid_num_r();
+
+	/*
+	 * Board Reset
+	 * The board is reset by holding the the large button
+	 * on the top right side of the main board for
+	 * eight seconds.
+	 *
+	 * There are reported problems of some beta boards
+	 * continously resetting.  For those boards, disable resetting.
+	 */
+	if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision())
+		twl4030_power_reset_init();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs (void)
+{
+	/* platform specific muxes */
+	MUX_ZOOM2 ();
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/logicpd/zoom2/zoom2.h b/u-boot/board/logicpd/zoom2/zoom2.h
new file mode 100644
index 0000000..f39685b
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/zoom2.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Derived from: board/omap3/zoom1/zoom1.h
+ * Nishanth Menon <nm@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BOARD_ZOOM2_H_
+#define _BOARD_ZOOM2_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Zoom2 ",
+	"NAND",
+};
+
+typedef enum {
+	ZOOM2_REVISION_UNKNOWN = 0,
+	ZOOM2_REVISION_ALPHA,
+	ZOOM2_REVISION_BETA,
+	ZOOM2_REVISION_PRODUCTION
+} zoom2_revision;
+
+zoom2_revision zoom2_get_revision(void);
+
+/*
+ * IEN	- Input Enable
+ * IDIS	- Input Disable
+ * PTD	- Pull type Down
+ * PTU	- Pull type Up
+ * DIS	- Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ZOOM2() \
+ /* SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M7)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTU | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTD | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT1 */\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT2 */\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT3 */\
+/* IDCC modem Power On */\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTU | EN  | M4)) /* GPIO_110 */\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTU | EN  | M4)) /* GPIO_103 */\
+/* GPMC CS7 has LAN9211 device */\
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(MCBSP1_DX),		(IEN  | PTD | DIS | M4)) /* LAN9221 */\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | EN  | M0)) /* MCSPI1_CS2 */\
+/* GPMC CS3 has Serial TL16CP754C device */\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS3 */\
+/* Toggle Reset pin of TL16CP754C device */\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTU | EN  | M4)) /* GPIO_152 */\
+ udelay(10);\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | EN  | M4)) /* GPIO_152 */\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */\
+/* LEDS */\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M4)) /* GPIO_173 red  */\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | EN  | M4)) /* GPIO_154 blue */\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | EN  | M4)) /* GPIO_61 blue2 */
+
+#endif /* _BOARD_ZOOM2_H_ */
diff --git a/u-boot/board/logicpd/zoom2/zoom2_serial.c b/u-boot/board/logicpd/zoom2/zoom2_serial.c
new file mode 100644
index 0000000..fcfe624
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/zoom2_serial.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c
+ *
+ */
+
+#include <common.h>
+#include <serial.h>
+#include <ns16550.h>
+#include <asm/arch/cpu.h>
+#include "zoom2_serial.h"
+
+int quad_init_dev (unsigned long base)
+{
+	/*
+	 * The Quad UART is on the debug board.
+	 * Check if the debug board is attached before using the UART
+	 */
+	if (zoom2_debug_board_connected ()) {
+		NS16550_t com_port = (NS16550_t) base;
+		int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 /
+			CONFIG_BAUDRATE;
+
+		/*
+		 * Zoom2 has a board specific initialization of its UART.
+		 * This generic initialization has been copied from
+		 * drivers/serial/ns16550.c. The macros have been expanded.
+		 *
+		 * Do the following instead of
+		 *
+		 * NS16550_init (com_port, clock_divisor);
+		 */
+		com_port->ier = 0x00;
+
+		/*
+		 * On Zoom2 board Set pre-scalar to 1
+		 * CLKSEL is GND => MCR[7] is 1 => preslr is 4
+		 * So change the prescl to 1
+		 */
+		com_port->lcr = 0xBF;
+		com_port->fcr |= 0x10;
+		com_port->mcr &= 0x7F;
+
+		/* This is generic ns16550.c setup */
+		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
+		com_port->dll = 0;
+		com_port->dlm = 0;
+		com_port->lcr = UART_LCR_8N1;
+		com_port->mcr = UART_MCR_DTR | UART_MCR_RTS;
+		com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR |
+			UART_FCR_TXSR;
+		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
+		com_port->dll = baud_divisor & 0xff;
+		com_port->dlm = (baud_divisor >> 8) & 0xff;
+		com_port->lcr = UART_LCR_8N1;
+	}
+	/*
+	 * We have to lie here, otherwise the board init code will hang
+	 * on the check
+	 */
+	return 0;
+}
+
+void quad_putc_dev (unsigned long base, const char c)
+{
+	if (zoom2_debug_board_connected ()) {
+
+		if (c == '\n')
+			quad_putc_dev (base, '\r');
+
+		NS16550_putc ((NS16550_t) base, c);
+	} else {
+		usbtty_putc(c);
+	}
+}
+
+void quad_puts_dev (unsigned long base, const char *s)
+{
+	if (zoom2_debug_board_connected ()) {
+		while ((s != NULL) && (*s != '\0'))
+			quad_putc_dev (base, *s++);
+	} else {
+		usbtty_puts(s);
+	}
+}
+
+int quad_getc_dev (unsigned long base)
+{
+	if (zoom2_debug_board_connected ())
+		return NS16550_getc ((NS16550_t) base);
+
+	return usbtty_getc();
+}
+
+int quad_tstc_dev (unsigned long base)
+{
+	if (zoom2_debug_board_connected ())
+		return NS16550_tstc ((NS16550_t) base);
+
+	return usbtty_tstc();
+}
+
+void quad_setbrg_dev (unsigned long base)
+{
+	if (zoom2_debug_board_connected ()) {
+
+		int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 /
+			CONFIG_BAUDRATE;
+
+		NS16550_reinit ((NS16550_t) base, clock_divisor);
+	}
+}
+
+QUAD_INIT (0)
+QUAD_INIT (1)
+QUAD_INIT (2)
+QUAD_INIT (3)
diff --git a/u-boot/board/logicpd/zoom2/zoom2_serial.h b/u-boot/board/logicpd/zoom2/zoom2_serial.h
new file mode 100644
index 0000000..a6d2427
--- /dev/null
+++ b/u-boot/board/logicpd/zoom2/zoom2_serial.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef ZOOM2_SERIAL_H
+#define ZOOM2_SERIAL_H
+
+extern int zoom2_debug_board_connected (void);
+
+#define SERIAL_TL16CP754C_BASE	0x10000000	/* Zoom2 Serial chip address */
+
+#define QUAD_BASE_0	SERIAL_TL16CP754C_BASE
+#define QUAD_BASE_1	(SERIAL_TL16CP754C_BASE + 0x100)
+#define QUAD_BASE_2	(SERIAL_TL16CP754C_BASE + 0x200)
+#define QUAD_BASE_3	(SERIAL_TL16CP754C_BASE + 0x300)
+
+#define S(a) #a
+#define N(a) S(quad##a)
+#define U(a) S(UART##a)
+
+#define QUAD_INIT(n)				\
+int quad_init_##n(void)				\
+{						\
+	return quad_init_dev(QUAD_BASE_##n);	\
+}						\
+void quad_setbrg_##n(void)			\
+{						\
+	quad_setbrg_dev(QUAD_BASE_##n);		\
+}						\
+void quad_putc_##n(const char c)		\
+{						\
+	quad_putc_dev(QUAD_BASE_##n, c);	\
+}						\
+void quad_puts_##n(const char *s)		\
+{						\
+	quad_puts_dev(QUAD_BASE_##n, s);	\
+}						\
+int quad_getc_##n(void)				\
+{						\
+	return quad_getc_dev(QUAD_BASE_##n);	\
+}						\
+int quad_tstc_##n(void)				\
+{						\
+	return quad_tstc_dev(QUAD_BASE_##n);	\
+}						\
+struct serial_device zoom2_serial_device##n =	\
+{						\
+	N(n),					\
+	U(n),					\
+	quad_init_##n,				\
+	NULL,					\
+	quad_setbrg_##n,			\
+	quad_getc_##n,				\
+	quad_tstc_##n,				\
+	quad_putc_##n,				\
+	quad_puts_##n,				\
+};
+
+#endif /* ZOOM2_SERIAL_H */
diff --git a/u-boot/board/lpc2292sodimm/Makefile b/u-boot/board/lpc2292sodimm/Makefile
new file mode 100644
index 0000000..c1a5b0b
--- /dev/null
+++ b/u-boot/board/lpc2292sodimm/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= flash.o lpc2292sodimm.o
+SOBJTS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJTS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJTS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lpc2292sodimm/config.mk b/u-boot/board/lpc2292sodimm/config.mk
new file mode 100644
index 0000000..4891792
--- /dev/null
+++ b/u-boot/board/lpc2292sodimm/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+#CONFIG_SYS_TEXT_BASE = 0x0
+CONFIG_SYS_TEXT_BASE = 0x81500000
diff --git a/u-boot/board/lpc2292sodimm/flash.c b/u-boot/board/lpc2292sodimm/flash.c
new file mode 100644
index 0000000..fd5389f
--- /dev/null
+++ b/u-boot/board/lpc2292sodimm/flash.c
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c by
+ * Gary Jennejohn <garyj@denx,de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#define SST_BASEADDR 0x80000000
+#define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555 << 1)))
+#define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1)))
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
+extern int lpc2292_flash_erase(flash_info_t *, int, int);
+extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong);
+
+/*-----------------------------------------------------------------------
+ *
+ */
+void write_word_sst(ulong addr, ushort data)
+{
+	ushort tmp;
+
+	*SST_ADDR1 = 0x00AA;
+	*SST_ADDR2 = 0x0055;
+	*SST_ADDR1 = 0x00A0;
+	*((volatile ushort*)addr) = data;
+	/* do data polling */
+	do {
+		tmp = *((volatile ushort*)addr);
+	} while (tmp != data);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int j, k;
+	ulong size = 0;
+	ulong flashbase = 0;
+
+	flash_info[0].flash_id = (PHILIPS_LPC2292 & FLASH_VENDMASK);
+	flash_info[0].size = 0x003E000;	/* 256 - 8 KB */
+	flash_info[0].sector_count = 17;
+	memset (flash_info[0].protect, 0, 17);
+	flashbase = 0x00000000;
+	for (j = 0, k = 0; j < 8; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	for (j = 0; j < 2; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00010000;
+	}
+	for (j = 0; j < 7; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	size += flash_info[0].size;
+
+	flash_info[1].flash_id = (SST_MANUFACT & FLASH_VENDMASK);
+	flash_info[1].size = 0x00200000; /* 2 MB */
+	flash_info[1].sector_count = 512;
+	memset (flash_info[1].protect, 0, 512);
+	flashbase = SST_BASEADDR;
+	for (j=0; j<512; j++) {
+		flash_info[1].start[j] = flashbase;
+		flashbase += 0x1000;	/* 4 KB sectors */
+	}
+	size += flash_info[1].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect (FLAG_PROTECT_SET,
+		 0x0,
+		 0x0 + monitor_flash_len - 1,
+		 &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		 CONFIG_ENV_ADDR,
+		 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		 &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int erased = 0;
+	unsigned long j;
+	unsigned long count;
+	unsigned char *p;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (SST_MANUFACT & FLASH_VENDMASK):
+		printf("SST: ");
+		break;
+	case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+		printf("Philips: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+	  info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		if (i < (info->sector_count - 1)) {
+			count = info->start[i+1] - info->start[i];
+		}
+		else {
+			count = info->start[0] + info->size - info->start[i];
+		}
+		p = (unsigned char*)(info->start[i]);
+		erased = 1;
+		for (j = 0; j < count; j++) {
+			if (*p != 0xFF) {
+				erased = 0;
+				break;
+			}
+			p++;
+		}
+		printf (" %08lX%s%s", info->start[i], info->protect[i] ? " RO" : "   ",
+			erased ? " E" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase_sst (flash_info_t * info, int s_first, int s_last)
+{
+	int i;
+
+	for (i = s_first; i <= s_last; i++) {
+		*SST_ADDR1 = 0x00AA;
+		*SST_ADDR2 = 0x0055;
+		*SST_ADDR1 = 0x0080;
+		*SST_ADDR1 = 0x00AA;
+		*SST_ADDR2 = 0x0055;
+		*((volatile ushort*)(info->start[i])) = 0x0030;
+		/* wait for erase to finish */
+		udelay(25000);
+	}
+
+	return ERR_OK;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (SST_MANUFACT & FLASH_VENDMASK):
+			return flash_erase_sst(info, s_first, s_last);
+		case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+			return lpc2292_flash_erase(info, s_first, s_last);
+		default:
+			return ERR_PROTECTED;
+	}
+	return ERR_PROTECTED;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ *
+ * cnt is in bytes
+ */
+
+int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ushort tmp;
+	ulong i;
+	uchar* src_org;
+	uchar* dst_org;
+	ulong cnt_org = cnt;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar*)addr;
+
+	if (addr & 1) {		/* if odd address */
+		tmp = *((uchar*)(addr - 1)); /* little endian */
+		tmp |= (*src << 8);
+		write_word_sst(addr - 1, tmp);
+		addr += 1;
+		cnt -= 1;
+		src++;
+	}
+	while (cnt > 1) {
+		tmp = ((*(src+1)) << 8) + (*src); /* little endian */
+		write_word_sst(addr, tmp);
+		addr += 2;
+		src += 2;
+		cnt -= 2;
+	}
+	if (cnt > 0) {
+		tmp = (*((uchar*)(addr + 1))) << 8;
+		tmp |= *src;
+		write_word_sst(addr, tmp);
+	}
+
+	for (i = 0; i < cnt_org; i++) {
+		if (*dst_org != *src_org) {
+			printf("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	return ret;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (SST_MANUFACT & FLASH_VENDMASK):
+			return write_buff_sst(info, src, addr, cnt);
+		case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+			return lpc2292_write_buff(info, src, addr, cnt);
+		default:
+			return ERR_PROG_ERROR;
+	}
+	return ERR_PROG_ERROR;
+}
diff --git a/u-boot/board/lpc2292sodimm/lowlevel_init.S b/u-boot/board/lpc2292sodimm/lowlevel_init.S
new file mode 100644
index 0000000..f579a1a
--- /dev/null
+++ b/u-boot/board/lpc2292sodimm/lowlevel_init.S
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+/* some parameters for the board */
+/* setting up the memory */
+#define	SRAM_START	0x40000000
+#define	SRAM_SIZE	0x00004000
+#define BCFG0_VALUE	0x1000ffef
+#define BCFG1_VALUE	0x10001C61
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+MEMMAP_ADR:
+	.word	MEMMAP
+BCFG0_ADR:
+	.word	BCFG0
+_BCFG0_VALUE:
+	.word	BCFG0_VALUE
+BCFG1_ADR:
+	.word	BCFG1
+_BCFG1_VALUE:
+	.word	BCFG1_VALUE
+PINSEL2_ADR:
+	.word	PINSEL2
+PINSEL2_MASK:
+	.word	0x00000000
+PINSEL2_VALUE:
+	.word	0x0F800914
+
+.extern _start
+
+.globl lowlevel_init
+lowlevel_init:
+	/* set up memory control register for bank 0 */
+	ldr r0, _BCFG0_VALUE
+	ldr r1, BCFG0_ADR
+	str r0, [r1]
+
+	/* set up memory control register for bank 1 */
+	ldr	r0, _BCFG1_VALUE
+	ldr	r1, BCFG1_ADR
+	str	r0, [r1]
+
+	/* set up PINSEL2 for bus-pins */
+	ldr	r0, PINSEL2_ADR
+	ldr	r1, [r0]
+	ldr	r2, PINSEL2_MASK
+	ldr	r3, PINSEL2_VALUE
+	and	r1, r1, r2
+	orr	r1, r1, r3
+	str	r1, [r0]
+
+	/* move vectors to beginning of SRAM */
+	mov	r2, #SRAM_START
+	mov	r0, #0 /*_start*/
+	ldmneia r0!, {r3-r10}
+	stmneia r2!, {r3-r10}
+	ldmneia r0, {r3-r9}
+	stmneia r2, {r3-r9}
+
+	/* Set-up MEMMAP register, so vectors are taken from SRAM */
+	ldr	r0, MEMMAP_ADR
+	mov	r1, #0x02	/* vectors re-mapped to static RAM */
+	str	r1, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/lpc2292sodimm/lpc2292sodimm.c b/u-boot/board/lpc2292sodimm/lpc2292sodimm.c
new file mode 100644
index 0000000..9c2d1af
--- /dev/null
+++ b/u-boot/board/lpc2292sodimm/lpc2292sodimm.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number MACH_TYPE_ARMADILLO - not official*/
+	gd->bd->bi_arch_number = 83;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/u-boot/board/lpd7a40x/Makefile b/u-boot/board/lpd7a40x/Makefile
new file mode 100644
index 0000000..3aeb2fb
--- /dev/null
+++ b/u-boot/board/lpd7a40x/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= lpd7a40x.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lpd7a40x/config.mk b/u-boot/board/lpd7a40x/config.mk
new file mode 100644
index 0000000..003e707
--- /dev/null
+++ b/u-boot/board/lpd7a40x/config.mk
@@ -0,0 +1,38 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine
+# w/Sharp LH7A400 SoC (ARM920T) cpu
+#
+
+#
+# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000
+#
+# Linux-Kernel is @ 0xC0008000, entry 0xc0008000
+# params @ 0xc0000100
+# optionally with a ramdisk at 0xc0300000
+#
+# we load ourself to 0xc1fc0000 (32M - 256K)
+#
+# download area is 0xc0f00000
+#
+
+CONFIG_SYS_TEXT_BASE = 0xc1fc0000
+#CONFIG_SYS_TEXT_BASE = 0x00000000
diff --git a/u-boot/board/lpd7a40x/flash.c b/u-boot/board/lpd7a40x/flash.c
new file mode 100644
index 0000000..a3ba75b
--- /dev/null
+++ b/u-boot/board/lpd7a40x/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+#define FLASH_BANK_SIZE 0x1000000	/* 16MB (2 x 8 MB) */
+#define MAIN_SECT_SIZE  0x40000		/* 256KB (2 x 128kB) */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT     & FLASH_VENDMASK) |
+			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = CONFIG_SYS_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase;
+
+			/* uniform sector size */
+			flashbase += MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+		printf ("2x 28F640J3A (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT) {
+		puts ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY) {
+		puts ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR) {
+		puts ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR) {
+		puts ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR) {
+		puts ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR) {
+		puts ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR) {
+		puts ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND) {
+		puts ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND) {
+		puts ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result, result1;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+			ulong bsR7, bsR7_2, bsR5, bsR5_2;
+
+			/* *addr = CMD_STATUS_RESET; */
+			*addr = CMD_ERASE_SETUP;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			do {
+				/* check timeout */
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = CMD_STATUS_RESET;
+					result = BIT_TIMEOUT;
+					break;
+				}
+
+				*addr = CMD_STATUS_READ;
+				result = *addr;
+				bsR7 = result & (1 << 7);
+				bsR7_2 = result & (1 << 23);
+			} while (!bsR7 | !bsR7_2);
+
+			*addr = CMD_STATUS_READ;
+			result1 = *addr;
+			bsR5 = result1 & (1 << 5);
+			bsR5_2 = result1 & (1 << 21);
+#ifdef SAMSUNG_FLASH_DEBUG
+			printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+			if (bsR5 != 0 && bsR5_2 != 0)
+				printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+#endif
+
+			*addr = CMD_READ_ARRAY;
+			*addr = CMD_RESUME;
+
+			if ((rc = flash_error (result)) != ERR_OK)
+				goto outahere;
+#if 0
+			printf ("ok.\n");
+		} else {		/* it was protected */
+
+			printf ("protected!\n");
+#endif
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* *addr = CMD_STATUS_RESET; */
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	do {
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			*addr = CMD_SUSPEND;
+			result = BIT_TIMEOUT;
+			break;
+		}
+
+		*addr = CMD_STATUS_READ;
+		result = *addr;
+	} while (~result & BIT_BUSY);
+
+	/* *addr = CMD_READ_ARRAY; */
+	*addr = CMD_STATUS_READ;
+	result = *addr;
+
+	rc = flash_error (result);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	*addr = CMD_READ_ARRAY;
+	*addr = CMD_RESUME;
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/lpd7a40x/lowlevel_init.S b/u-boot/board/lpd7a40x/lowlevel_init.S
new file mode 100644
index 0000000..de34fc6
--- /dev/null
+++ b/u-boot/board/lpd7a40x/lowlevel_init.S
@@ -0,0 +1,212 @@
+/*
+ * Memory Setup - initialize memory controller(s) for devices required
+ *                to boot and relocate
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* memory controller */
+#define BCRX_DEFAULT	(0x0000fbe0)
+#define BCRX_MW_8	(0x00000000)
+#define BCRX_MW_16	(0x10000000)
+#define BCRX_MW_32	(0x20000000)
+#define BCRX_PME	(0x08000000)
+#define BCRX_WP		(0x04000000)
+#define BCRX_WST2_SHIFT	(11)
+#define BCRX_WST1_SHIFT	(5)
+#define BCRX_IDCY_SHIFT	(0)
+
+/* Bank0 Async Flash */
+#define BCR0		(0x80002000)
+#define BCR0_FLASH	(BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
+
+/* Bank1 Open */
+#define BCR1	(0x80002004)
+
+/* Bank2 Not used (EEPROM?) */
+#define BCR2	(0x80002008)
+
+/* Bank3 Not used */
+#define BCR3	(0x8000200C)
+
+/* Bank4 PC Card1 */
+
+/* Bank5 PC Card2 */
+
+/* Bank6 CPLD IO Controller Peripherals (slow) */
+#define BCR6		(0x80002018)
+#define BCR6_CPLD_SLOW	(BCRX_DEFAULT | BCRX_MW_16)
+
+/* Bank7 CPLD IO Controller Peripherals (fast) */
+#define BCR7		(0x8000201C)
+#define BCR7_CPLD_FAST	(BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
+
+/* SDRAM */
+#define GBLCNFG		(0x80002404)
+#define GC_CKE		(0x80000000)
+#define GC_CKSD		(0x40000000)
+#define GC_LCR		(0x00000040)
+#define GC_SMEMBURST	(0x00000020)
+#define GC_MRS		(0x00000002)
+#define GC_INIT		(0x00000001)
+
+#define GC_CMD_NORMAL		(GC_CKE)
+#define GC_CMD_MODE		(GC_CKE | GC_MRS)
+#define GC_CMD_SYNCFLASH_LOAD	(GC_CKE | GC_MRS | GC_LCR)
+#define GC_CMD_PRECHARGEALL	(GC_CKE | GC_INIT)
+#define GC_CMD_NOP		(GC_CKE | GC_INIT | GC_MRS)
+
+#define RFSHTMR		(0x80002408)
+#define RFSHTMR_INIT	(10)	/* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
+#define RFSHTMR_NORMAL	(1500)	/* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
+
+#define SDCSCX_BASE		(0x80002410)
+#define SDCSCX_DEFAULT		(0x01220008)
+#define SDCSCX_AUTOPC		(0x01000000)
+#define SDCSCX_RAS2CAS_2	(0x00200000)
+#define SDCSCX_RAS2CAS_3	(0x00300000)
+#define SDCSCX_WBL		(0x00080000)
+#define SDCSCX_CASLAT_8		(0x00070000)
+#define SDCSCX_CASLAT_7		(0x00060000)
+#define SDCSCX_CASLAT_6		(0x00050000)
+#define SDCSCX_CASLAT_5		(0x00040000)
+#define SDCSCX_CASLAT_4		(0x00030000)
+#define SDCSCX_CASLAT_3		(0x00020000)
+#define SDCSCX_CASLAT_2		(0x00010000)
+#define SDCSCX_2KPAGE		(0x00000040)
+#define SDCSCX_SROMLL		(0x00000020)
+#define SDCSCX_SROM512		(0x00000010)
+#define SDCSCX_4BNK		(0x00000008)
+#define SDCSCX_2BNK		(0x00000000)
+#define SDCSCX_EBW_16		(0x00000004)
+#define SDCSCX_EBW_32		(0x00000000)
+
+#define SDRAM_BASE		(0xC0000000)
+#define SDCSC_BANK_OFFSET	(0x10000000)
+
+/*
+ * The SDRAM DEVICE MODE PROGRAMMING VALUE
+ */
+#define BURST_LENGTH_4		(2 << 10)
+#define BURST_LENGTH_8		(3 << 10)
+#define WBURST_LENGTH_BL	(0 << 19)
+#define WBURST_LENGTH_SINGLE	(1 << 19)
+#define CAS_2			(2 << 14)
+#define CAS_3			(3 << 14)
+#define BAT_SEQUENTIAL		(0 << 13)
+#define BAT_INTERLEAVED		(1 << 13)
+#define OPM_NORMAL		(0 << 17)
+#define SDRAM_DEVICE_MODE	(WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
+
+
+#define TIMER1_BASE	(0x80000C00)
+
+/*
+ * special lookup flags
+ */
+#define DO_MEM_DELAY	1
+#define DO_MEM_READ	2
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r9, lr	@ save return address
+
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads INITMEM_DATA out of FLASH rather than memory ! */
+	/*   r0 = current word pointer */
+	/*   r1 = end word location, one word past last actual word */
+	/*   r3 = address for writes, special lookup flags */
+	/*   r4 = value for writes, delay constants, or read addresses */
+	/*   r2 = location for mem reads */
+
+	ldr	r0, =INITMEM_DATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r1, r0, #112
+
+mem_loop:
+	cmp	r1, r0
+	moveq	pc, r9		@ Done
+
+	ldr	r3, [r0], #4	@ Fetch Destination Register Address, or 1 for delay
+	ldr	r4, [r0], #4	@ value
+
+	cmp	r3, #DO_MEM_DELAY
+	bleq	mem_delay
+	beq	mem_loop
+	cmp	r3, #DO_MEM_READ
+	ldreq	r2, [r4]
+	beq	mem_loop
+	str	r4, [r3]	@ normal register/ram store
+	b	mem_loop
+
+mem_delay:
+	ldr	r5, =TIMER1_BASE
+	mov	r6, r4, LSR #1	@ timer resolution is ~2us
+	str	r6, [r5]
+	mov	r6, #0x88	@ using 508.469KHz clock, enable
+	str	r6, [r5, #8]
+0:	ldr	r6, [r5, #4]	@ timer value
+	cmp	r6, #0
+	bne	0b
+	mov	r6, #0		@ disable timer
+	str	r6, [r5, #8]
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+INITMEM_DATA:
+	.word	BCR0
+	.word	BCR0_FLASH
+	.word	BCR6
+	.word	BCR6_CPLD_SLOW
+	.word	BCR7
+	.word	BCR7_CPLD_FAST
+	.word	SDCSCX_BASE
+	.word	(SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
+	.word	GBLCNFG
+	.word	GC_CMD_NOP
+	.word	DO_MEM_DELAY
+	.word	200
+	.word	GBLCNFG
+	.word	GC_CMD_PRECHARGEALL
+	.word	RFSHTMR
+	.word	RFSHTMR_INIT
+	.word	DO_MEM_DELAY
+	.word	8
+	.word	RFSHTMR
+	.word	RFSHTMR_NORMAL
+	.word	GBLCNFG
+	.word	GC_CMD_MODE
+	.word	DO_MEM_READ
+	.word	(SDRAM_BASE | SDRAM_DEVICE_MODE)
+	.word	GBLCNFG
+	.word	GC_CMD_NORMAL
+	.word	SDCSCX_BASE
+	.word	(SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
diff --git a/u-boot/board/lpd7a40x/lpd7a40x.c b/u-boot/board/lpd7a40x/lpd7a40x.c
new file mode 100644
index 0000000..437dad0
--- /dev/null
+++ b/u-boot/board/lpd7a40x/lpd7a40x.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#if defined(CONFIG_LH7A400)
+#include <lh7a400.h>
+#elif defined(CONFIG_LH7A404)
+#include <lh7a404.h>
+#else
+#error "No CPU defined!"
+#endif
+#include <asm/mach-types.h>
+
+#include <lpd7a400_cpld.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* set up the I/O ports */
+
+	/* enable flash programming */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN;
+
+	/* Auto wakeup, LCD disable, WLAN enable */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &=
+		~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE);
+
+	/* Status LED 2 on (leds are active low) */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) =
+		(EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2);
+
+#if defined(CONFIG_LH7A400)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A400;
+#elif defined(CONFIG_LH7A404)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A404;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/lubbock/Makefile b/u-boot/board/lubbock/Makefile
new file mode 100644
index 0000000..60ac9cf
--- /dev/null
+++ b/u-boot/board/lubbock/Makefile
@@ -0,0 +1,50 @@
+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= lubbock.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lubbock/flash.c b/u-boot/board/lubbock/flash.c
new file mode 100644
index 0000000..a4b201e
--- /dev/null
+++ b/u-boot/board/lubbock/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/lubbock/lubbock.c b/u-boot/board/lubbock/lubbock.c
new file mode 100644
index 0000000..f791c5b
--- /dev/null
+++ b/u-boot/board/lubbock/lubbock.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/lwmon/Makefile b/u-boot/board/lwmon/Makefile
new file mode 100644
index 0000000..b49f26d
--- /dev/null
+++ b/u-boot/board/lwmon/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lwmon/README.keybd b/u-boot/board/lwmon/README.keybd
new file mode 100644
index 0000000..54f0aeb
--- /dev/null
+++ b/u-boot/board/lwmon/README.keybd
@@ -0,0 +1,126 @@
+
+Tastaturabfrage:
+
+Die Implementierung / Decodierung beruht auf den Angaben aus dem  Do-
+kument  "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde-
+re Tabelle 3 im Kapitel 4.3 Tastencodes. In  U-Boot  werden  die  vom
+Keyboard-Controller  gelesenen Daten hexadezimal codiert in der auto-
+matisch angelegten Environment-Variablen "keybd" übergeben. Ist  kei-
+ne Taste gedrückt worden, steht dort:
+
+	keybd=000000000000000000
+
+Der decodierte Tastencode ("keybd") kann mit den  "bootargs"  an  den
+Linux-Kernel  übergeben  und  dort z. B. in einem Device-Treiber oder
+einer Applikation ausgewertet werden.
+
+
+Sonderfunktionen beim Booten:
+
+Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten-
+kombinationen definieren, die Sonderfunktionen auslösen,  wenn  diese
+Tasten beim Booten (Reset) gedrückt sind.
+
+Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so  wird
+in  U-Boot noch vor dem Start des "Countdown" und somit vor jedem an-
+deren Kommando der Inhalt einer dieser Taste  bzw.  Tastenkombination
+zugeordneten Environment-Variablen ausführen.
+
+
+Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver-
+standen, die als Suffix an den Namen "key_magic" angefügt werden  und
+so  die  Namen  der  Environment-Variablen  definieren, mit denen die
+Tasten (-kombinationen) festgelegt werden:
+
+Ist "magic_keys" NICHT definiert, so wird nur die in der Environment-
+Variablen "key_magic" codierte  Tasten  (-kombination)  geprüft,  und
+ggf.  der  Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge-
+nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie-
+sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando-
+interpretation beginnt).
+
+Enthält "magic_keys" z. B.  die  Zeichenkette  "0123CB*",  so  werden
+nacheinander folgende Aktionen ausgeführt:
+
+	prüfe Tastencode	ggf. führe aus Kommando
+	in Variable		in Variable
+	-----------------------------------
+	key_magic0	==>	key_cmd0
+	key_magic1	==>	key_cmd1
+	key_magic2	==>	key_cmd2
+	key_magic3	==>	key_cmd3
+	key_magicC	==>	key_cmdC
+	key_magicB	==>	key_cmdB
+	key_magicA	==>	key_cmdA
+	key_magic*	==>	key_cmd*
+
+Hinweis: sobald ein aktivierter Tastencode erkannt  wurde,  wird  die
+Bearbeitung  abgebrochen; es wird daher höchstens eines der definier-
+ten Kommandos ausgeführt, wobei die Priorität durch  die  Suchreihen-
+folge  festgelegt wird, also durch die Reihenfolge der Zeichen in der
+Varuiablen "magic_keys".
+
+
+Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um
+eine Funktion auszulösen, erfolgt nach der Tastaturtabelle.
+
+Die Definitionen
+
+	=> setenv key_magic0 3a+3b
+	=> setenv key_cmd0 setenv bootdelay 30
+
+bedeuten dementsprechend, daß die Tasten mit den  Codes  0x3A  (Taste
+"F1")  und 0x3B (Taste "F2") gleichzeitig gedrückt werden müssen. Sie
+können dort eine beliebige  Tastenkombination  eintragen  (jeweils  2
+Zeichen für die Hex-Codes der Tasten, und '+' als Trennzeichen).
+
+Wird die eingestellte Tastenkombination erkannt, so  wird  in  U-Boot
+noch  vor  dem Start des "Countdown" und somit vor jedem anderen Kom-
+mando das angebene Kommando ausgeführt und  somit  ein  langes  Boot-
+Delay eingetragen.
+
+Praktisch könnten Sie also in U-Boot "bootdelay"  auf  0  setzen  und
+somit  stets  ohne  jede  User-Interaktion automatisch booten, außer,
+wenn die beiden Tasten "F1" und "F2"  beim  Booten  gedrückt  werden:
+dann würde ein Boot-Delay von 30 Sekunden eingefügt.
+
+
+Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson-
+dere Bedeutung zu: die dadurch definierte  Key-Sequenz  schaltet  den
+Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite-
+ren  Meldungen  von  U-Boot  über  das LCD-Display ausgegeben werden;
+außerdem kann man durch das mit dieser  Tastenkombination  verknüpfte
+Kommando  z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display
+legen, so daß der Boot-Vorgang direkt und  ohne  weitere  Hilfsmittel
+analysiert werden kann.
+
+Beispiel:
+
+In U-Boot werden folgende Environment-Variablen gesetzt und abgespei-
+chert:
+
+(1)	=> setenv magic_keys 01234#X
+(2)	=> setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate}
+(3)	=> setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath}
+(4)	=> setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1
+(5)	=> setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate}
+(6)	=> setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm
+
+Hierbei wird die Linux Commandline (in der Variablen  "bootargs")  im
+Boot-Kommando  "bootcmd"  (6)  schrittweise zusammengesetzt: zunächst
+werden die für Root-Filesystem über NFS erforderlichen  Optionen  ge-
+setzt  ("run  nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an-
+gefügt ("run addip", vgl. (4)),  und  schließlich  die  Systemconsole
+definiert ("run addfb").
+
+Dabei wird im Normalfall die Definition (5)  verwendt;  wurde  aller-
+dings  beim  Reset die entsprechende Taste gedrückt gehalten, so wird
+diese Definition bei der Ausführung des in (2) definierten  Kommandos
+überschrieben,  so  daß  Linux die Bootmeldungen auch über das Frame-
+buffer-Device (=LCD-Display) ausgibt.
+
+Beachten Sie die Verdoppelung der '\'-Escapes in der  Definition  von
+"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter-
+pretiert  wird:  das  erste  Mal  bei der Eingabe von "key_cmd#", das
+zweite Mal, wenn der String (als  Inhalt  von  "preboot")  ausgeführt
+wird.
diff --git a/u-boot/board/lwmon/flash.c b/u-boot/board/lwmon/flash.c
new file mode 100644
index 0000000..f71cc24
--- /dev/null
+++ b/u-boot/board/lwmon/flash.c
@@ -0,0 +1,648 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	debug  ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
+				OR_CSNT_SAM | OR_ACS_DIV1;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
+					OR_CSNT_SAM | OR_ACS_DIV1;
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+					BR_PS_32 | BR_V;
+
+		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+		memctl->memc_or1 = 0;		/* invalidate bank */
+
+		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += 0x00020000 * 2;		/* 128k * 2 chips per bank */
+	    }
+	    return;
+
+	default:
+	    printf ("Don't know sector ofsets for flash type 0x%lx\n",
+		info->flash_id);
+	    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320J3A (32Mbit = 128K x 32)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64Mbit = 128K x 64)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128J3A (128Mbit = 128K x 128)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	ulong value;
+
+	/* Read Manufacturer ID */
+	addr[0] = 0x00900090;
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000 * 2;
+		break;				/* =>  8 MB		*/
+
+	case INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000 * 2;
+		break;				/* => 16 MB		*/
+
+	case INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000 * 2;
+		break;				/* => 32 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = 0x00600060;	/* clear lock bit setup */
+			*addr = 0x00D000D0;	/* clear lock bit confirm */
+
+			udelay (1000);
+			/* This takes awfully long - up to 50 ms and more */
+			while (((status = *addr) & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00FF00FF; /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+				udelay (1000);	/* to trigger the watchdog */
+			}
+
+			*addr = 0x00500050;	/* clear status register */
+			*addr = 0x00200020;	/* erase setup */
+			*addr = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00B000B0; /* suspend erase	  */
+					*addr = 0x00FF00FF; /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+				udelay (1000);	/* to trigger the watchdog */
+			}
+
+			*addr = 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	4	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while(cnt >= FLASH_WIDTH) {
+		i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ?
+		    (cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE;
+		if((rc = write_data_buf(info, wp, src,i)) != 0)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Check flash status, returns:
+ * 0 - OK
+ * 1 - timeout
+ */
+static int flash_status_check(vu_long *addr, ulong tout, char * prompt)
+{
+	ulong status;
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(((status = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > tout) {
+			printf("Flash %s timeout at address %p\n", prompt, addr);
+			*addr = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = 0x00400040;		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) {
+		return (1);
+	}
+
+	*addr = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/*-----------------------------------------------------------------------
+ * Write a buffer to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ */
+static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+	vu_long *addr = (vu_long *)dest;
+	int sector;
+	int cnt;
+	int retcode;
+	vu_long * src = (vu_long *)cp;
+	vu_long * dst = (vu_long *)dest;
+
+	/* find sector */
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(dest >= info->start[sector])
+			break;
+	}
+
+	*addr = 0x00500050;		/* clear status */
+	*addr = 0x00e800e8;		/* write buffer */
+
+	if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
+					 "write to buffer")) == 0) {
+		cnt = len / FLASH_WIDTH;
+		*addr = (cnt-1) | ((cnt-1) << 16);
+		while(cnt-- > 0) {
+			*dst++ = *src++;
+		}
+		*addr = 0x00d000d0;		/* write buffer confirm */
+		retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
+						 "buffer write");
+	}
+	*addr = 0x00FF00FF;	/* restore read mode */
+	*addr = 0x00500050;	/* clear status */
+	return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/lwmon/lwmon.c b/u-boot/board/lwmon/lwmon.c
new file mode 100644
index 0000000..9d6c21f
--- /dev/null
+++ b/u-boot/board/lwmon/lwmon.c
@@ -0,0 +1,1087 @@
+/***********************************************************************
+ *
+M* Modul:         lwmon.c
+M*
+M* Content:       LWMON specific U-Boot commands.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ *
+D* Design:        wd@denx.de
+C* Coding:        wd@denx.de
+V* Verification:  dzu@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ ***********************************************************************/
+
+/*---------------------------- Headerfiles ----------------------------*/
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <i2c.h>
+#include <command.h>
+#include <malloc.h>
+#include <post.h>
+#include <serial.h>
+
+#include <linux/types.h>
+#include <linux/string.h>	/* for strdup */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*------------------------ Local prototypes ---------------------------*/
+static long int dram_size (long int, long int *, long int);
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+
+/*--------------------- Local macros and constants --------------------*/
+#define	_NOT_USED_	0xFFFFFFFF
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+extern void disable_putc(void);
+#endif /* CONFIG_MODEM_SUPPORT */
+
+/*
+ * 66 MHz SDRAM access using UPM A
+ */
+const uint sdram_table[] =
+{
+#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E)
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+	0x1FF5FC47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+#endif
+#ifdef CONFIG_SYS_MEMORY_7E
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_,
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
+	0xE1BAFC04, 0x1FF5FC47, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+#endif
+};
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+/***********************************************************************
+F* Function:     int checkboard (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int - 0 is always returned
+ *
+Z* Intention:    This function is the checkboard() method implementation
+Z*               for the lwmon board.  Only a standard message is printed.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int checkboard (void)
+{
+	puts ("Board: LICCON Konsole LCD3\n");
+	return (0);
+}
+
+/***********************************************************************
+F* Function:     phys_size_t initdram (int board_type) P*A*Z*
+ *
+P* Parameters:   int board_type
+P*                - Usually type of the board - ignored here.
+P*
+P* Returnvalue:  long int
+P*                - Size of initialized memory
+ *
+Z* Intention:    This function is the initdram() method implementation
+Z*               for the lwmon board.
+Z*               The memory controller is initialized to access the
+Z*               DRAM.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	long int size_b0;
+	long int size8, size9;
+	int i;
+
+	/*
+	 * Configure UPMA for SDRAM
+	 */
+	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/* burst length=4, burst type=sequential, CAS latency=2 */
+	memctl->memc_mar = CONFIG_SYS_MAR;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	/* initialize memory address register */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
+
+	/* mode initialization (offset 5) */
+	udelay (200);				/* 0x80006105 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+	udelay (1);				/* 0x80006130 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+	udelay (1);				/* 0x80006130 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+
+	udelay (1);				/* 0x80006106 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
+
+	udelay (200);
+
+	/* Need at least 10 DRAM accesses to stabilize */
+	for (i = 0; i < 10; ++i) {
+		volatile unsigned long *addr =
+			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
+		unsigned long val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE;
+		udelay (500);
+	} else {			/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
+		udelay (500);
+	}
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
+			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
+	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	udelay (1000);
+
+	return (size_b0);
+}
+
+/***********************************************************************
+F* Function:     static long int dram_size (long int mamr_value,
+F*                                          long int *base,
+F*                                          long int maxsize) P*A*Z*
+ *
+P* Parameters:   long int mamr_value
+P*                - Value for MAMR for the test
+P*               long int *base
+P*                - Base address for the test
+P*               long int maxsize
+P*                - Maximum size to test for
+P*
+P* Returnvalue:  long int
+P*                - Size of probed memory
+ *
+Z* Intention:    Check memory range for valid RAM. A simple memory test
+Z*               determines the actually available RAM size between
+Z*               addresses `base' and `base + maxsize'. Some (not all)
+Z*               hardware errors are detected:
+Z*                - short between address lines
+Z*                - short between data lines
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifndef	PB_ENET_TENA
+# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+#endif
+
+/***********************************************************************
+F* Function:     int board_early_init_f (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    This function is the board_early_init_f() method implementation
+Z*               for the lwmon board.
+Z*               Disable Ethernet TENA on Port B.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int board_early_init_f (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* Disable Ethernet TENA on Port B
+	 * Necessary because of pull up in COM3 port.
+	 *
+	 * This is just a preliminary fix, intended to turn off TENA
+	 * as soon as possible to avoid noise on the network. Once
+	 * I²C is running we will make sure the interface is
+	 * correctly initialized.
+	 */
+	immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA;
+	immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;
+	immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA;	/* set to 0 = disabled */
+	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/***********************************************************************
+F* Function:     void reset_phy (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  none
+ *
+Z* Intention:    Reset the PHY.  In the lwmon case we do this by the
+Z*               signaling the PIC I/O expander.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+void reset_phy (void)
+{
+	uchar c;
+
+#ifdef DEBUG
+	printf ("### Switch on Ethernet for SCC2 ###\n");
+#endif
+	c = pic_read (0x61);
+#ifdef DEBUG
+	printf ("Old PIC read: reg_61 = 0x%02x\n", c);
+#endif
+	c |= 0x40;					/* disable COM3 */
+	c &= ~0x80;					/* enable Ethernet */
+	pic_write (0x61, c);
+#ifdef DEBUG
+	c = pic_read (0x61);
+	printf ("New PIC read: reg_61 = 0x%02x\n", c);
+#endif
+	udelay (1000);
+}
+
+
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define	KEYBD_CMD_READ_KEYS	0x01
+#define KEYBD_CMD_READ_VERSION	0x02
+#define KEYBD_CMD_READ_STATUS	0x03
+#define KEYBD_CMD_RESET_ERRORS	0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK	0x3F
+#define	KEYBD_STATUS_H_RESET	0x20
+#define KEYBD_STATUS_BROWNOUT	0x10
+#define KEYBD_STATUS_WD_RESET	0x08
+#define KEYBD_STATUS_OVERLOAD	0x04
+#define KEYBD_STATUS_ILLEGAL_WR	0x02
+#define KEYBD_STATUS_ILLEGAL_RD	0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN	2	/* version information */
+#define	KEYBD_DATALEN		9	/* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function:     int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    This function is the board_postclk_init() method implementation
+Z*               for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+	kbd_init();
+
+#ifdef CONFIG_MODEM_SUPPORT
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		gd->do_mdm_init = 1;
+	}
+#endif
+
+	return (0);
+}
+
+struct serial_device * default_serial_console (void)
+{
+	return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
+}
+
+static void kbd_init (void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar tmp_data[KEYBD_DATALEN];
+	uchar val, errcd;
+	int i;
+
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	gd->kbd_status = 0;
+
+	/* Forced by PIC. Delays <= 175us loose */
+	udelay(1000);
+
+	/* Read initial keyboard error code */
+	val = KEYBD_CMD_READ_STATUS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, &errcd, 1);
+	/* clear unused bits */
+	errcd &= KEYBD_STATUS_MASK;
+	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+	if (errcd) {
+		gd->kbd_status |= errcd << 8;
+	}
+	/* Reset error code and verify */
+	val = KEYBD_CMD_RESET_ERRORS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	udelay(1000);	/* delay NEEDED by keyboard PIC !!! */
+
+	val = KEYBD_CMD_READ_STATUS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, &val, 1);
+
+	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
+	if (val) {			/* permanent error, report it */
+		gd->kbd_status |= val;
+		return;
+	}
+
+	/*
+	 * Read current keyboard state.
+	 *
+	 * After the error reset it may take some time before the
+	 * keyboard PIC picks up a valid keyboard scan - the total
+	 * scan time is approx. 1.6 ms (information by Martin Rajek,
+	 * 28 Sep 2002). We read a couple of times for the keyboard
+	 * to stabilize, using a big enough delay.
+	 * 10 times should be enough. If the data is still changing,
+	 * we use what we get :-(
+	 */
+
+	memset (tmp_data, 0xFF, KEYBD_DATALEN);	/* impossible value */
+	for (i=0; i<10; ++i) {
+		val = KEYBD_CMD_READ_KEYS;
+		i2c_write (kbd_addr, 0, 0, &val, 1);
+		i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+		if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+			/* consistent state, done */
+			break;
+		}
+		/* remeber last state, delay, and retry */
+		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+		udelay (5000);
+	}
+}
+
+/***********************************************************************
+F* Function:     int misc_init_r (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned, even in the case of a keyboard
+P*                    error.
+ *
+Z* Intention:    This function is the misc_init_r() method implementation
+Z*               for the lwmon board.
+Z*               The keyboard controller is initialized and the result
+Z*               of a read copied to the environment variable "keybd".
+Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z*               this key, and if found display to the LCD will be enabled.
+Z*               The keys in "keybd" are checked against the magic
+Z*               keycommands defined in the environment.
+Z*               See also key_match().
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r (void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar kbd_init_status = gd->kbd_status >> 8;
+	uchar kbd_status = gd->kbd_status;
+	uchar val;
+	char *str;
+	int i;
+
+	if (kbd_init_status) {
+		printf ("KEYBD: Error %02X\n", kbd_init_status);
+	}
+	if (kbd_status) {		/* permanent error, report it */
+		printf ("*** Keyboard error code %02X ***\n", kbd_status);
+		sprintf (keybd_env, "%02X", kbd_status);
+		setenv ("keybd", keybd_env);
+		return 0;
+	}
+
+	/*
+	 * Now we know that we have a working  keyboard,  so  disable
+	 * all output to the LCD except when a key press is detected.
+	 */
+
+	if ((console_assign (stdout, "serial") < 0) ||
+		(console_assign (stderr, "serial") < 0)) {
+		printf ("Can't assign serial port as output device\n");
+	}
+
+	/* Read Version */
+	val = KEYBD_CMD_READ_VERSION;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+	/* Read current keyboard state */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+	}
+	setenv ("keybd", keybd_env);
+
+	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+	if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {	/* set debug mode */
+		if ((console_assign (stdout, "lcd") < 0) ||
+			(console_assign (stderr, "lcd") < 0)) {
+			printf ("Can't assign LCD display as output device\n");
+		}
+	}
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+	return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+	uchar compare[KEYBD_DATALEN-1];
+	char *nxt;
+	int i;
+
+	/* Don't include modifier byte */
+	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+		uchar c;
+		int k;
+
+		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+		if (str == (uchar *)nxt) {	/* invalid character */
+			break;
+		}
+
+		/*
+		 * Check if this key matches the input.
+		 * Set matches to zero, so they match only once
+		 * and we can find duplicates or extra keys
+		 */
+		for (k = 0; k < sizeof(compare); ++k) {
+			if (compare[k] == '\0')	/* only non-zero entries */
+				continue;
+			if (c == compare[k]) {	/* found matching key */
+				compare[k] = '\0';
+				break;
+			}
+		}
+		if (k == sizeof(compare)) {
+			return -1;		/* unmatched key */
+		}
+	}
+
+	/*
+	 * A full match leaves no keys in the `compare' array,
+	 */
+	for (i = 0; i < sizeof(compare); ++i) {
+		if (compare[i])
+		{
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/***********************************************************************
+F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters:   uchar *kbd_data
+P*                - The keys to match against our magic definitions
+P*
+P* Returnvalue:  uchar *
+P*                - != NULL: Pointer to the corresponding command(s)
+P*                     NULL: No magic is about to happen
+ *
+Z* Intention:    Check if pressed key(s) match magic sequence,
+Z*               and return the command string associated with that key(s).
+Z*
+Z*               If no key press was decoded, NULL is returned.
+Z*
+Z*               Note: the first character of the argument will be
+Z*                     overwritten with the "magic charcter code" of the
+Z*                     decoded key(s), or '\0'.
+Z*
+Z*               Note: the string points to static environment data
+Z*                     and must be saved before you call any function that
+Z*                     modifies the environment.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	uchar *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+#if 0
+		printf ("### Check magic \"%s\"\n", magic);
+#endif
+		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+			cmd = getenv (cmd_name);
+#if 0
+			printf ("### Set PREBOOT to $(%s): \"%s\"\n",
+					cmd_name, cmd ? cmd : "<<NULL>>");
+#endif
+			*kbd_data = *suffix;
+			return ((uchar *)cmd);
+		}
+	}
+#if 0
+	printf ("### Delete PREBOOT\n");
+#endif
+	*kbd_data = '\0';
+	return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+#ifdef CONFIG_LCD_INFO
+#include <lcd.h>
+#include <version.h>
+#include <timestamp.h>
+
+void lcd_show_board_info(void)
+{
+	char temp[32];
+
+	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
+	lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
+	lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
+#ifdef CONFIG_LCD_INFO_BELOW_LOGO
+	lcd_printf ("MPC823 CPU at %s MHz\n",
+		strmhz(temp, gd->cpu_clk));
+	lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
+		gd->ram_size >> 20,
+		gd->bd->bi_flashsize >> 20 );
+#else
+	/* leave one blank line */
+	lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
+		strmhz(temp, gd->cpu_clk),
+		gd->ram_size >> 20,
+		gd->bd->bi_flashsize >> 20 );
+#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
+}
+#endif /* CONFIG_LCD_INFO */
+
+/*---------------Board Special Commands: PIC read/write ---------------*/
+
+#if defined(CONFIG_CMD_BSP)
+/***********************************************************************
+F* Function:     int do_pic (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char * const argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0  The command was handled successfully
+P*                  1  An error occurred
+ *
+Z* Intention:    Implement the "pic [read|write]" commands.
+Z*               The read subcommand takes one argument, the register,
+Z*               whereas the write command takes two, the register and
+Z*               the new value.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar reg, val;
+
+	switch (argc) {
+	case 3:					/* PIC read reg */
+		if (strcmp (argv[1], "read") != 0)
+			break;
+
+		reg = simple_strtoul (argv[2], NULL, 16);
+
+		printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg));
+
+		return 0;
+	case 4:					/* PIC write reg val */
+		if (strcmp (argv[1], "write") != 0)
+			break;
+
+		reg = simple_strtoul (argv[2], NULL, 16);
+		val = simple_strtoul (argv[3], NULL, 16);
+
+		printf ("PIC write: reg %02x val 0x%02x: %02x => ",
+				reg, val, pic_read (reg));
+		pic_write (reg, val);
+		printf ("%02x\n\n", pic_read (reg));
+		return 0;
+	default:
+		break;
+	}
+	return cmd_usage(cmdtp);
+}
+U_BOOT_CMD(
+	pic,	4,	1,	do_pic,
+	"read and write PIC registers",
+	"read  reg      - read PIC register `reg'\n"
+	"pic write reg val  - write value `val' to PIC register `reg'"
+);
+
+/***********************************************************************
+F* Function:     int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char * const argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    Implement the "kbd" command.
+Z*               The keyboard status is read.  The result is printed on
+Z*               the console and written into the "keybd" environment
+Z*               variable.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar val;
+	int i;
+
+#if 0 /* Done in kbd_init */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+		printf (" %02x", kbd_data[i]);
+	}
+	putc ('\n');
+	setenv ("keybd", keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
+	"read keyboard status",
+	""
+);
+
+/* Read and set LSB switch */
+#define CONFIG_SYS_PC_TXD1_ENA		0x0008		/* PC.12 */
+
+/***********************************************************************
+F* Function:     int do_lsb (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char * const argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0  The command was handled successfully
+P*                  1  An error occurred
+ *
+Z* Intention:    Implement the "lsb [on|off]" commands.
+Z*               The lsb is switched according to the first parameter by
+Z*               by signaling the PIC I/O expander.
+Z*               Called with no arguments, the current setting is
+Z*               printed.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar val;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	switch (argc) {
+	case 1:					/* lsb - print setting */
+		val = pic_read (0x60);
+		printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff");
+		return 0;
+	case 2:					/* lsb on or lsb off - set switch */
+		val = pic_read (0x60);
+
+		if (strcmp (argv[1], "on") == 0) {
+			val |= 0x20;
+			immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
+		} else if (strcmp (argv[1], "off") == 0) {
+			val &= ~0x20;
+			immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
+		} else {
+			break;
+		}
+		pic_write (0x60, val);
+		return 0;
+	default:
+		break;
+	}
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	lsb,	2,	1,	do_lsb,
+	"check and set LSB switch",
+	"on  - switch LSB on\n"
+	"lsb off - switch LSB off\n"
+	"lsb     - print current setting"
+);
+
+#endif
+
+/*----------------------------- Utilities -----------------------------*/
+/***********************************************************************
+F* Function:     uchar pic_read (uchar reg) P*A*Z*
+ *
+P* Parameters:   uchar reg
+P*                - Register to read
+P*
+P* Returnvalue:  uchar
+P*                - Value read from register
+ *
+Z* Intention:    Read a register from the PIC I/O expander.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+uchar pic_read (uchar reg)
+{
+	return (i2c_reg_read (CONFIG_SYS_I2C_PICIO_ADDR, reg));
+}
+
+/***********************************************************************
+F* Function:     void pic_write (uchar reg, uchar val) P*A*Z*
+ *
+P* Parameters:   uchar reg
+P*                - Register to read
+P*               uchar val
+P*                - Value to write
+P*
+P* Returnvalue:  none
+ *
+Z* Intention:    Write to a register on the PIC I/O expander.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+void pic_write (uchar reg, uchar val)
+{
+	i2c_reg_write (CONFIG_SYS_I2C_PICIO_ADDR, reg, val);
+}
+
+/*---------------------- Board Control Functions ----------------------*/
+/***********************************************************************
+F* Function:     void board_poweroff (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  none
+ *
+Z* Intention:    Turn off the battery power and loop endless, so this
+Z*               should better be the last function you call...
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+void board_poweroff (void)
+{
+    /* Turn battery off */
+    ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
+
+    while (1);
+}
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0);
+}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
diff --git a/u-boot/board/lwmon/pcmcia.c b/u-boot/board/lwmon/pcmcia.c
new file mode 100644
index 0000000..ad2e60d
--- /dev/null
+++ b/u-boot/board/lwmon/pcmcia.c
@@ -0,0 +1,240 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+#include <i2c.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "LWMON"
+
+/* #define's for MAX1604 Power Switch */
+#define MAX1604_OP_SUS		0x80
+#define MAX1604_VCCBON		0x40
+#define MAX1604_VCC_35		0x20
+#define MAX1604_VCCBHIZ		0x10
+#define MAX1604_VPPBON		0x08
+#define MAX1604_VPPBPBPGM	0x04
+#define MAX1604_VPPBHIZ		0x02
+/* reserved			0x01	*/
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, mask;
+	uchar val;
+
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	/* Switch on PCMCIA port in PIC register 0x60 */
+	reg = pic_read  (0x60);
+	debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+	reg &= ~0x10;
+	/* reg |= 0x08; Vpp not needed */
+	pic_write (0x60, reg);
+#ifdef DEBUG
+	reg = pic_read  (0x60);
+	printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+#endif
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/*
+	 * Configure SIUMCR to enable PCMCIA port B
+	 * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	 */
+	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	 * Disable interrupts, DMA, and PCMCIA buffers
+	 * (isolate the interface) and assert RESET signal
+	 */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	 * Make sure there is a card in the slot, then configure the interface.
+	 */
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+		__LINE__,__FUNCTION__,
+		&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	 * Power On.
+	 */
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	reg  = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+		reg,
+		(reg&PCMCIA_VS1(slot))?"n":"ff",
+		(reg&PCMCIA_VS2(slot))?"n":"ff");
+	if ((reg & mask) == mask) {
+		val = 0;		/* VCCB3/5 = 0 ==> use Vx = 5.0 V */
+		puts (" 5.0V card found: ");
+	} else {
+		val = MAX1604_VCC_35;	/* VCCB3/5 = 1 ==> use Vy = 3.3 V */
+		puts (" 3.3V card found: ");
+	}
+
+	/*  switch VCC on */
+	val |= MAX1604_OP_SUS | MAX1604_VCCBON;
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+
+	udelay(500000);
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+	uchar val;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* remove all power, put output in high impedance state */
+	val  = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	/* Switch off PCMCIA port in PIC register 0x60 */
+	reg = pic_read  (0x60);
+	debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+	reg |=  0x10;
+	reg &= ~0x08;
+	pic_write (0x60, reg);
+#ifdef DEBUG
+	reg = pic_read  (0x60);
+	printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+#endif
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+	uchar val;
+
+	debug ("voltage_set: "
+		PCMCIA_BOARD_MSG
+		" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+		'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	 * Disable PCMCIA buffers (isolate the interface)
+	 * and assert RESET signal
+	 */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	 * Turn off all power (switch to high impedance)
+	 */
+	debug ("PCMCIA power OFF\n");
+	val  = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+
+	val = 0;
+	switch(vcc) {
+	case  0:			break;
+	case 33: val = MAX1604_VCC_35;	break;
+	case 50:			break;
+	default:			goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+		pcmp->pcmc_pipr,
+		(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	if (val) {
+		debug ("PCMCIA powered at %sV\n",
+			(val & MAX1604_VCC_35) ? "3.3" : "5.0");
+	} else {
+		debug ("PCMCIA powered down\n");
+	}
+
+done:
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+		slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/lwmon/u-boot.lds b/u-boot/board/lwmon/u-boot.lds
new file mode 100644
index 0000000..dd9be60
--- /dev/null
+++ b/u-boot/board/lwmon/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/lwmon/u-boot.lds.debug b/u-boot/board/lwmon/u-boot.lds.debug
new file mode 100644
index 0000000..131ad23
--- /dev/null
+++ b/u-boot/board/lwmon/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/lwmon5/Makefile b/u-boot/board/lwmon5/Makefile
new file mode 100644
index 0000000..f7fef96
--- /dev/null
+++ b/u-boot/board/lwmon5/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o kbd.o sdram.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/lwmon5/config.mk b/u-boot/board/lwmon5/config.mk
new file mode 100644
index 0000000..648fa3d
--- /dev/null
+++ b/u-boot/board/lwmon5/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# lwmon5 (440EPx)
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/lwmon5/init.S b/u-boot/board/lwmon5/init.S
new file mode 100644
index 0000000..2014cd7
--- /dev/null
+++ b/u-boot/board/lwmon5/init.S
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
+
+	/* TLB-entry for the FPGA Chip select 2 */
+	tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
+
+	/* TLB-entry for the FPGA Chip select 3 */
+	tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
+
+	/* TLB-entry for the LIME Controller */
+	tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I)
+
+	/*TLB-entry PCI registers*/
+	tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG)
+
+	/* TLB-entry for peripherals */
+	tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	tlbtab_end
diff --git a/u-boot/board/lwmon5/kbd.c b/u-boot/board/lwmon5/kbd.c
new file mode 100644
index 0000000..5231c7a
--- /dev/null
+++ b/u-boot/board/lwmon5/kbd.c
@@ -0,0 +1,503 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <i2c.h>
+#include <command.h>
+#include <post.h>
+#include <serial.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h>	/* for strdup */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+/*--------------------- Local macros and constants --------------------*/
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*------------------------- dspic io expander -----------------------*/
+#define DSPIC_PON_STATUS_REG	0x80A
+#define DSPIC_PON_INV_STATUS_REG 0x80C
+#define DSPIC_PON_KEY_REG	0x810
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define	KEYBD_CMD_READ_KEYS	0x01
+#define KEYBD_CMD_READ_VERSION	0x02
+#define KEYBD_CMD_READ_STATUS	0x03
+#define KEYBD_CMD_RESET_ERRORS	0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK	0x3F
+#define	KEYBD_STATUS_H_RESET	0x20
+#define KEYBD_STATUS_BROWNOUT	0x10
+#define KEYBD_STATUS_WD_RESET	0x08
+#define KEYBD_STATUS_OVERLOAD	0x04
+#define KEYBD_STATUS_ILLEGAL_WR	0x02
+#define KEYBD_STATUS_ILLEGAL_RD	0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN	2	/* version information */
+
+/*
+ * This is different from the "old" lwmon dsPIC kbd controller
+ * implementation. Now the controller still answers with 9 bytes,
+ * but the last 3 bytes are always "0x06 0x07 0x08". So we just
+ * set the length to compare to 6 instead of 9.
+ */
+#define	KEYBD_DATALEN		6	/* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function:     int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    This function is the board_postclk_init() method implementation
+Z*               for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+	kbd_init();
+
+	return (0);
+}
+
+static void kbd_init (void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar tmp_data[KEYBD_DATALEN];
+	uchar val, errcd;
+	int i;
+
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	gd->kbd_status = 0;
+
+	/* Forced by PIC. Delays <= 175us loose */
+	udelay(1000);
+
+	/* Read initial keyboard error code */
+	val = KEYBD_CMD_READ_STATUS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, &errcd, 1);
+	/* clear unused bits */
+	errcd &= KEYBD_STATUS_MASK;
+	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+	if (errcd) {
+		gd->kbd_status |= errcd << 8;
+	}
+	/* Reset error code and verify */
+	val = KEYBD_CMD_RESET_ERRORS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	udelay(1000);	/* delay NEEDED by keyboard PIC !!! */
+
+	val = KEYBD_CMD_READ_STATUS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, &val, 1);
+
+	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
+	if (val) {			/* permanent error, report it */
+		gd->kbd_status |= val;
+		return;
+	}
+
+	/*
+	 * Read current keyboard state.
+	 *
+	 * After the error reset it may take some time before the
+	 * keyboard PIC picks up a valid keyboard scan - the total
+	 * scan time is approx. 1.6 ms (information by Martin Rajek,
+	 * 28 Sep 2002). We read a couple of times for the keyboard
+	 * to stabilize, using a big enough delay.
+	 * 10 times should be enough. If the data is still changing,
+	 * we use what we get :-(
+	 */
+
+	memset (tmp_data, 0xFF, KEYBD_DATALEN);	/* impossible value */
+	for (i=0; i<10; ++i) {
+		val = KEYBD_CMD_READ_KEYS;
+		i2c_write (kbd_addr, 0, 0, &val, 1);
+		i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+		if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+			/* consistent state, done */
+			break;
+		}
+		/* remeber last state, delay, and retry */
+		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+		udelay (5000);
+	}
+}
+
+
+/* Read a register from the dsPIC. */
+int _dspic_read(ushort reg, ushort *data)
+{
+	uchar buf[sizeof(*data)];
+	int rval;
+
+	if (i2c_read(dspic_addr, reg, 2, buf, 2))
+		return -1;
+
+	rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
+	*data = (buf[0] << 8) | buf[1];
+
+	return rval;
+}
+
+
+/***********************************************************************
+F* Function:     int misc_init_r (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned, even in the case of a keyboard
+P*                    error.
+ *
+Z* Intention:    This function is the misc_init_r() method implementation
+Z*               for the lwmon board.
+Z*               The keyboard controller is initialized and the result
+Z*               of a read copied to the environment variable "keybd".
+Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z*               this key, and if found display to the LCD will be enabled.
+Z*               The keys in "keybd" are checked against the magic
+Z*               keycommands defined in the environment.
+Z*               See also key_match().
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r_kbd (void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar kbd_init_status = gd->kbd_status >> 8;
+	uchar kbd_status = gd->kbd_status;
+	uchar val;
+	ushort data, inv_data;
+	char *str;
+	int i;
+
+	if (kbd_init_status) {
+		printf ("KEYBD: Error %02X\n", kbd_init_status);
+	}
+	if (kbd_status) {		/* permanent error, report it */
+		printf ("*** Keyboard error code %02X ***\n", kbd_status);
+		sprintf (keybd_env, "%02X", kbd_status);
+		setenv ("keybd", keybd_env);
+		return 0;
+	}
+
+	/*
+	 * Now we know that we have a working  keyboard,  so  disable
+	 * all output to the LCD except when a key press is detected.
+	 */
+
+	if ((console_assign (stdout, "serial") < 0) ||
+		(console_assign (stderr, "serial") < 0)) {
+		printf ("Can't assign serial port as output device\n");
+	}
+
+	/* Read Version */
+	val = KEYBD_CMD_READ_VERSION;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+	/* Read current keyboard state */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	/* read out start key from bse01 received via can */
+	_dspic_read(DSPIC_PON_STATUS_REG, &data);
+	/* check highbyte from status register */
+	if (data > 0xFF) {
+		_dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
+
+		/* check inverse data */
+		if ((data+inv_data) == 0xFFFF) {
+			/* don't overwrite local key */
+			if (kbd_data[1] == 0) {
+				/* read key value */
+				_dspic_read(DSPIC_PON_KEY_REG, &data);
+				str = (char *)&data;
+				/* swap bytes */
+				kbd_data[1] = str[1];
+				kbd_data[2] = str[0];
+				printf("CAN received startkey: 0x%X\n", data);
+			}
+		}
+	}
+
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+	}
+
+	setenv ("keybd", keybd_env);
+
+	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+	if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {	/* set debug mode */
+		if ((console_assign (stdout, "lcd") < 0) ||
+			(console_assign (stderr, "lcd") < 0)) {
+			printf ("Can't assign LCD display as output device\n");
+		}
+	}
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+	return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+	uchar compare[KEYBD_DATALEN-1];
+	char *nxt;
+	int i;
+
+	/* Don't include modifier byte */
+	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+		uchar c;
+		int k;
+
+		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+		if (str == (uchar *)nxt) {	/* invalid character */
+			break;
+		}
+
+		/*
+		 * Check if this key matches the input.
+		 * Set matches to zero, so they match only once
+		 * and we can find duplicates or extra keys
+		 */
+		for (k = 0; k < sizeof(compare); ++k) {
+			if (compare[k] == '\0')	/* only non-zero entries */
+				continue;
+			if (c == compare[k]) {	/* found matching key */
+				compare[k] = '\0';
+				break;
+			}
+		}
+		if (k == sizeof(compare)) {
+			return -1;		/* unmatched key */
+		}
+	}
+
+	/*
+	 * A full match leaves no keys in the `compare' array,
+	 */
+	for (i = 0; i < sizeof(compare); ++i) {
+		if (compare[i])
+		{
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/***********************************************************************
+F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters:   uchar *kbd_data
+P*                - The keys to match against our magic definitions
+P*
+P* Returnvalue:  uchar *
+P*                - != NULL: Pointer to the corresponding command(s)
+P*                     NULL: No magic is about to happen
+ *
+Z* Intention:    Check if pressed key(s) match magic sequence,
+Z*               and return the command string associated with that key(s).
+Z*
+Z*               If no key press was decoded, NULL is returned.
+Z*
+Z*               Note: the first character of the argument will be
+Z*                     overwritten with the "magic charcter code" of the
+Z*                     decoded key(s), or '\0'.
+Z*
+Z*               Note: the string points to static environment data
+Z*                     and must be saved before you call any function that
+Z*                     modifies the environment.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	uchar *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+		debug ("### Check magic \"%s\"\n", magic);
+		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+			cmd = getenv (cmd_name);
+			debug ("### Set PREBOOT to $(%s): \"%s\"\n",
+					cmd_name, cmd ? cmd : "<<NULL>>");
+			*kbd_data = *suffix;
+			return ((uchar *)cmd);
+		}
+	}
+	debug ("### Delete PREBOOT\n");
+	*kbd_data = '\0';
+	return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+/***********************************************************************
+F* Function:     int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char * const argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    Implement the "kbd" command.
+Z*               The keyboard status is read.  The result is printed on
+Z*               the console and written into the "keybd" environment
+Z*               variable.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar val;
+	int i;
+
+#if 0 /* Done in kbd_init */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+		printf (" %02x", kbd_data[i]);
+	}
+	putc ('\n');
+	setenv ("keybd", keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
+	"read keyboard status",
+	""
+);
+
+/*----------------------------- Utilities -----------------------------*/
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
diff --git a/u-boot/board/lwmon5/lwmon5.c b/u-boot/board/lwmon5/lwmon5.c
new file mode 100644
index 0000000..dd275bf
--- /dev/null
+++ b/u-boot/board/lwmon5/lwmon5.c
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2007-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <post.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
+
+ulong flash_get_size(ulong base, int banknum);
+int misc_init_r_kbd(void);
+
+int board_early_init_f(void)
+{
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	/* PLB Write pipelining disabled. Denali Core workaround */
+	mtdcr(PLB4A0_ACR, 0xDE000000);
+	mtdcr(PLB4A1_ACR, 0xDE000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
+	mtdcr(UIC0ER, 0x00000000);  /* disable all */
+	mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
+	mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
+	mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(UIC0SR, 0xffffffff);  /* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
+	mtdcr(UIC1ER, 0x00000000);  /* disable all */
+	mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
+	mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
+	mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
+	mtdcr(UIC2ER, 0x00000000);  /* disable all */
+	mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
+	mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
+	mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
+
+	/* Trace Pins are disabled. SDR0_PFC0 Register */
+	mtsdr(SDR0_PFC0, 0x0);
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	/* SMII via ZMII */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_6;
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_6;
+
+	/* enable SPI (SCP) */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	mtsdr(SDR0_PFC4, 0x80000000);
+
+	/* PCI arbiter disabled */
+	/* PCI Host Configuration disbaled */
+	mfsdr(SDR0_PCI0, reg);
+	reg = 0;
+	mtsdr(SDR0_PCI0, 0x00000000 | reg);
+
+	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
+
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
+	/* enable the LSB transmitter */
+	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+	/* enable the CAN transmitter */
+	gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
+
+	reg = 0; /* reuse as counter */
+	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
+			& ~CONFIG_SYS_DSPIC_TEST_MASK);
+	while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
+		udelay(1000);
+	}
+	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
+		/* set "boot error" flag */
+		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
+			CONFIG_SYS_DSPIC_TEST_MASK);
+	}
+#endif
+
+	/*
+	 * Reset PHY's:
+	 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
+	 * upon reset, and with the first reset upon powerup, the addresses are
+	 * not latched reliable, since the IRQ line is multiplexed with an
+	 * MDIO address. A 2nd reset at this time will make sure, that the
+	 * correct address is latched.
+	 */
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+	udelay(1000);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
+	udelay(1000);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+
+	return 0;
+}
+
+/*
+ * Override weak default with board specific version
+ */
+phys_addr_t cfi_flash_bank_addr(int bank)
+{
+	return lwmon5_cfi_flash_bank_addr[bank];
+}
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+	return flash_info[idx].size;
+}
+
+int board_early_init_r(void)
+{
+	u32 val0, val1;
+
+	/*
+	 * lwmon5 is manufactured in 2 different board versions:
+	 * The lwmon5a board has 64MiB NOR flash instead of the
+	 * 128MiB of the original lwmon5. Unfortunately the CFI driver
+	 * will report 2 banks of 64MiB even for the smaller flash
+	 * chip, since the bank is mirrored. To fix this, we bring
+	 * one bank into CFI query mode and read its response. This
+	 * enables us to detect the real number of flash devices/
+	 * banks which will be used later on by the common CFI driver.
+	 */
+
+	/* Put bank 0 into CFI command mode and read */
+	out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
+	val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
+	val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
+
+	/* Reset flash again out of query mode */
+	out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
+
+	/* When not identical, we have 2 different flash devices/banks */
+	if (val0 != val1)
+		return 0;
+
+	/*
+	 * Now we're sure that we're running on a LWMON5a board with
+	 * only 64MiB NOR flash in one bank:
+	 *
+	 * Set flash base address and bank count for CFI driver probing.
+	 */
+	cfi_flash_num_flash_banks = 1;
+	lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 pbcr;
+	int size_val = 0;
+	u32 reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1, sdr0_srst;
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	mfebc(PB0CR, pbcr);
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtebc(PB0CR, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
+		      &flash_info[cfi_flash_num_flash_banks - 1]);
+
+	/* Env protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+		      CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[cfi_flash_num_flash_banks - 1]);
+
+	/*
+	 * USB suff...
+	 */
+
+	/* Reset USB */
+	/* Reset of USB2PHY0 must be active at least 10 us  */
+	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
+	udelay(2000);
+
+	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
+	      SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
+	      SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
+	udelay(2000);
+
+	/* Errata CHIP_6 */
+
+	/* 1. Set internal PHY configuration */
+	/* SDR Setting */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_USB0, usb2d0cr);
+	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+
+	/*
+	 * An 8-bit/60MHz interface is the only possible alternative
+	 * when connecting the Device to the PHY
+	 */
+	usb2h0cr   = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+	usb2h0cr   = usb2h0cr |  SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+	mtsdr(SDR0_USB0, usb2d0cr);
+	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	/* 2. De-assert internal PHY reset */
+	mfsdr(SDR0_SRST1, sdr0_srst);
+	sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
+	mtsdr(SDR0_SRST1, sdr0_srst);
+
+	/* 3. Wait for more than 1 ms */
+	udelay(2000);
+
+	/* 4. De-assert USB 2.0 Host main reset */
+	mfsdr(SDR0_SRST0, sdr0_srst);
+	sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
+	mtsdr(SDR0_SRST0, sdr0_srst);
+	udelay(1000);
+
+	/* 5. De-assert reset of OPB2 cores */
+	mfsdr(SDR0_SRST1, sdr0_srst);
+	sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
+	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
+	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
+	mtsdr(SDR0_SRST1, sdr0_srst);
+	udelay(1000);
+
+	/* 6. Set EHCI Configure FLAG */
+
+	/* 7. Reassert internal PHY reset: */
+	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
+	udelay(1000);
+
+	/*
+	 * Clear resets
+	 */
+	mtsdr(SDR0_SRST1, 0x00000000);
+	mtsdr(SDR0_SRST0, 0x00000000);
+
+	printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+	/*
+	 * Init matrix keyboard
+	 */
+	misc_init_r_kbd();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: lwmon5");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+void hw_watchdog_reset(void)
+{
+	int val;
+#if defined(CONFIG_WD_MAX_RATE)
+	unsigned long long ct = get_ticks();
+
+	/*
+	 * Don't allow watch-dog triggering more frequently than
+	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
+	 */
+	if (ct >= gd->wdt_last) {
+		if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
+			return;
+	} else {
+		/* Time base counter had been reset */
+		if (((unsigned long long)(-1) - gd->wdt_last + ct) <
+		    CONFIG_WD_MAX_RATE)
+			return;
+	}
+	gd->wdt_last = get_ticks();
+#endif
+
+	/*
+	 * Toggle watchdog output
+	 */
+	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
+	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
+}
+
+int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	if ((strcmp(argv[1], "on") == 0))
+		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
+	else if ((strcmp(argv[1], "off") == 0))
+		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
+	else
+		return cmd_usage(cmdtp);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	eepromwp,	2,	0,	do_eeprom_wp,
+	"eeprom write protect off/on",
+	"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
+);
+
+#if defined(CONFIG_VIDEO)
+#include <video_fb.h>
+#include <mb862xx.h>
+
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs [] = {
+	{ 0x0100, 0x00000f00 },
+	{ 0x0020, 0x801401df },
+	{ 0x0024, 0x00000000 },
+	{ 0x0028, 0x00000000 },
+	{ 0x002c, 0x00000000 },
+	{ 0x0110, 0x00000000 },
+	{ 0x0114, 0x00000000 },
+	{ 0x0118, 0x01df0280 },
+	{ 0x0004, 0x031f0000 },
+	{ 0x0008, 0x027f027f },
+	{ 0x000c, 0x015f028f },
+	{ 0x0010, 0x020c0000 },
+	{ 0x0014, 0x01df01ea },
+	{ 0x0018, 0x00000000 },
+	{ 0x001c, 0x01e00280 },
+	{ 0x0100, 0x80010f00 },
+	{ 0x0, 0x0 }
+};
+
+const gdc_regs *board_get_regs(void)
+{
+	return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init(void)
+{
+	/*
+	 * Reset Lime controller
+	 */
+	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+	udelay(500);
+	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+	mb862xx.winSizeX = 640;
+	mb862xx.winSizeY = 480;
+	mb862xx.gdfBytesPP = 2;
+	mb862xx.gdfIndex = GDF_15BIT_555RGB;
+
+	return CONFIG_SYS_LIME_BASE_0;
+}
+
+#define DEFAULT_BRIGHTNESS	0x64
+
+static void board_backlight_brightness(int brightness)
+{
+	if (brightness > 0) {
+		/* pwm duty, lamp on */
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
+	} else {
+		/* lamp off */
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
+	}
+}
+
+void board_backlight_switch(int flag)
+{
+	char * param;
+	int rc;
+
+	if (flag) {
+		param = getenv("brightness");
+		rc = param ? simple_strtol(param, NULL, 10) : -1;
+		if (rc < 0)
+			rc = DEFAULT_BRIGHTNESS;
+	} else {
+		rc = 0;
+	}
+	board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str(int line_number, char *info)
+{
+	if (line_number == 1)
+		strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
+	else
+		info [0] = '\0';
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+#endif /* CONFIG_VIDEO */
+
+void board_reset(void)
+{
+	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
+}
diff --git a/u-boot/board/lwmon5/sdram.c b/u-boot/board/lwmon5/sdram.c
new file mode 100644
index 0000000..b64b35a
--- /dev/null
+++ b/u-boot/board/lwmon5/sdram.c
@@ -0,0 +1,258 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/ppc440.h>
+#include <watchdog.h>
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CONFIG_4xx_DCACHE
+#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
+#endif
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+extern void dcbz_area(u32 start_address, u32 num_bytes);
+
+static u32 is_ecc_enabled(void)
+{
+	u32 val;
+
+	mfsdram(DDR0_22, val);
+	val &= DDR0_22_CTRL_RAW_MASK;
+	if (val)
+		return 1;
+	else
+		return 0;
+}
+
+void board_add_ram_info(int use_default)
+{
+	PPC4xx_SYS_INFO board_cfg;
+	u32 val;
+
+	if (is_ecc_enabled())
+		puts(" (ECC");
+	else
+		puts(" (ECC not");
+
+	get_sys_info(&board_cfg);
+	printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+	mfsdram(DDR0_03, val);
+	val = DDR0_03_CASLAT_DECODE(val);
+	printf(", CL%d)", val);
+}
+
+#ifdef CONFIG_DDR_ECC
+static void wait_ddr_idle(void)
+{
+	/*
+	 * Controller idle status cannot be determined for Denali
+	 * DDR2 code. Just return here.
+	 */
+}
+
+static void program_ecc(u32 start_address,
+			u32 num_bytes,
+			u32 tlb_word2_i_value)
+{
+	u32 val;
+	u32 current_addr = start_address;
+	u32 size;
+	int bytes_remaining;
+
+	sync();
+	wait_ddr_idle();
+
+	/*
+	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
+	 * bytes of SDRAM.
+	 */
+	bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
+
+	/*
+	 * We have to write the ECC bytes by zeroing and flushing in smaller
+	 * steps, since the whole 256MByte takes too long for the external
+	 * watchdog.
+	 */
+	while (bytes_remaining > 0) {
+		size = min((64 << 20), bytes_remaining);
+
+		/* Write zero's to SDRAM */
+		dcbz_area(current_addr, size);
+
+		/* Write modified dcache lines back to memory */
+		clean_dcache_range(current_addr, current_addr + size);
+
+		current_addr += 64 << 20;
+		bytes_remaining -= 64 << 20;
+		WATCHDOG_RESET();
+	}
+
+	sync();
+	wait_ddr_idle();
+
+	/* Clear error status */
+	mfsdram(DDR0_00, val);
+	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+	/* Set 'int_mask' parameter to functionnal value */
+	mfsdram(DDR0_01, val);
+	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
+
+	sync();
+	wait_ddr_idle();
+}
+#endif
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+	/* CL=4 */
+	mtsdram(DDR0_02, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+	mtsdram(DDR0_04, 0x0B030300);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0003C812);
+	mtsdram(DDR0_07, 0x00090100);
+	mtsdram(DDR0_08, 0x03c80001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000100);
+	mtsdram(DDR0_11, 0x000CC800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x1e000000);
+	mtsdram(DDR0_18, 0x1e1e1e1e);
+	mtsdram(DDR0_19, 0x1e1e1e1e);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
+#else
+	mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+	mtsdram(DDR0_23, 0x01000000);
+	mtsdram(DDR0_24, 0x01010001);
+
+	mtsdram(DDR0_26, 0x2D93028A);
+	mtsdram(DDR0_27, 0x0784682B);
+
+	mtsdram(DDR0_28, 0x00000080);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000008);
+
+	mtsdram(DDR0_43, 0x050A0200);
+	mtsdram(DDR0_44, 0x00000005);
+	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+
+	denali_wait_for_dlllock();
+
+#if defined(CONFIG_DDR_DATA_EYE)
+	/* -----------------------------------------------------------+
+	 * Perform data eye search if requested.
+	 * ----------------------------------------------------------*/
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+		    TLB_WORD2_I_ENABLE);
+	denali_core_search_data_eye();
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif
+
+	/*
+	 * Program tlb entries for this size (dynamic)
+	 */
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+		    MY_TLB_WORD2_I_ENABLE);
+
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+	/*
+	 * If ECC is enabled, initialize the parity bits.
+	 */
+	program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
+	/*
+	 * Setup 2nd TLB with same physical address but different virtual address
+	 * with cache enabled. This is done for fast ECC generation.
+	 */
+	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+	/*
+	 * If ECC is enabled, initialize the parity bits.
+	 */
+	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+	/*
+	 * Now after initialization (auto-calibration and ECC generation)
+	 * remove the TLB entries with caches enabled and program again with
+	 * desired cache functionality
+	 */
+	remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
+
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+}
diff --git a/u-boot/board/m501sk/Makefile b/u-boot/board/m501sk/Makefile
new file mode 100644
index 0000000..439e99f
--- /dev/null
+++ b/u-boot/board/m501sk/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS  := m501sk.o eeprom.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/m501sk/config.mk b/u-boot/board/m501sk/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/u-boot/board/m501sk/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/u-boot/board/m501sk/eeprom.c b/u-boot/board/m501sk/eeprom.c
new file mode 100644
index 0000000..d1a46f3
--- /dev/null
+++ b/u-boot/board/m501sk/eeprom.c
@@ -0,0 +1,102 @@
+/*
+ * Add by Alan Lu, 07-29-2005
+ * For ATMEL AT24C16 EEPROM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#ifdef CONFIG_SYS_EEPROM_AT24C16
+#undef DEBUG
+
+void eeprom_init(void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+}
+
+int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer,
+			unsigned cnt)
+{
+	int page, count = 0, i = 0;
+	page = offset / 0x100;
+	i = offset % 0x100;
+
+	while (count < cnt) {
+		if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+			return 1;
+		if (i > 0xff) {
+			page++;
+			i = 0;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ *   0x00000nxx for EEPROM address selectors and page number at n.
+ */
+int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
+			unsigned cnt)
+{
+	int page, i = 0, count = 0;
+
+	page = offset / 0x100;
+	i = offset % 0x100;
+
+	while (count < cnt) {
+		if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+			return 1;
+		if (i > 0xff) {
+			page++;
+			i = 0;
+		}
+	}
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SPI
+int eeprom_probe(unsigned dev_addr, unsigned offset)
+{
+	unsigned char chip;
+
+	/* Probe the chip address */
+#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
+	chip = offset >> 8; /* block number */
+#else
+	chip = offset >> 16; /* block number */
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+
+	chip |= dev_addr; /* insert device address */
+	return (i2c_probe(chip));
+}
+#endif
+#endif
diff --git a/u-boot/board/m501sk/m501sk.c b/u-boot/board/m501sk/m501sk.c
new file mode 100644
index 0000000..c995768
--- /dev/null
+++ b/u-boot/board/m501sk/m501sk.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2008
+ * Based on modifications by Alan Lu / Artila
+ * Author : Timo Tuunainen / Sysart
+			Kimmo Leppala / Sysart
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#if defined(CONFIG_DRIVER_ETHER)
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#endif
+
+#include "m501sk.h"
+#include "net.h"
+
+#ifdef CONFIG_M501SK
+
+void m501sk_gpio_init(void)
+{
+	AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) |
+		1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
+		1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
+
+	AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) |
+		1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
+		1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
+
+	AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96);
+	AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96);
+	AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32);
+	AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32);
+	AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8);
+
+	/* Power OFF all USART's LEDs */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+	AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+	AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+}
+
+uchar m501sk_gpio_set(M501SK_PIO io)
+{
+	uchar status = 0xff;
+	switch (io) {
+	case M501SK_DEBUG_LED1:
+	case M501SK_DEBUG_LED2:
+	case M501SK_DEBUG_LED3:
+	case M501SK_DEBUG_LED4:
+	case M501SK_READY_LED:
+		AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96);
+		status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
+		break;
+	case M501SK_BUZZER:
+		AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32);
+		status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
+		break;
+	}
+	return status;
+}
+
+uchar m501sk_gpio_clear(M501SK_PIO io)
+{
+	uchar status = 0xff;
+	switch (io) {
+	case M501SK_DEBUG_LED1:
+	case M501SK_DEBUG_LED2:
+	case M501SK_DEBUG_LED3:
+	case M501SK_DEBUG_LED4:
+	case M501SK_READY_LED:
+		AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96);
+		status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
+		break;
+	case M501SK_BUZZER:
+		AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32);
+		status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
+		break;
+	}
+	return status;
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+	gd->bd->bi_arch_number = MACH_TYPE_M501;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	m501sk_gpio_init();
+
+	/* Do interrupt init here, because flash needs timers */
+	timer_init();
+	flash_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i = 0;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	for (i = 0; i < 500; i++) {
+		m501sk_gpio_clear(M501SK_DEBUG_LED3);
+		m501sk_gpio_clear(M501SK_BUZZER);
+		udelay(250);
+		m501sk_gpio_set(M501SK_DEBUG_LED3);
+		m501sk_gpio_set(M501SK_BUZZER);
+		udelay(80);
+	}
+	m501sk_gpio_clear(M501SK_BUZZER);
+	m501sk_gpio_clear(M501SK_DEBUG_LED3);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_CMD_NET)
+	eth_init(gd->bd);
+	eth_halt();
+#endif
+
+	/* Protect U-Boot, kernel & ramdisk memory addresses */
+	run_command("protect on 10000000 1041ffff", 0);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+/*
+ * Name:
+ *     at91rm9200_GetPhyInterface
+ * Description:
+ *     Initialise the interface functions to the PHY
+ * Arguments:
+ *     None
+ * Return value:
+ *     None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
+#endif /* CONFIG_M501SK */
diff --git a/u-boot/board/m501sk/m501sk.h b/u-boot/board/m501sk/m501sk.h
new file mode 100644
index 0000000..51d10f5
--- /dev/null
+++ b/u-boot/board/m501sk/m501sk.h
@@ -0,0 +1,167 @@
+/*
+ * linux/include/asm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __M501SK_H
+#define __M501SK_H
+
+#ifndef __ASSEMBLY__
+#include <asm/arch-at91rm9200/AT91RM9200.h>
+#else
+#include <asm/arch-at91rm9200/AT91RM9200_inc.h>
+#endif
+
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */
+#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */
+#define AT91C_PA5_TXD3 ((unsigned int) 1 <<  5) /* USART 3 TxD */
+#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */
+
+/* ========== Register definition for PIOD peripheral ========== */
+#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */
+#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */
+#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */
+#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */
+#define AT91C_PIOD_IMR  ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */
+#define AT91C_PIOD_IER  ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */
+#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */
+#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */
+#define AT91C_PIOD_PER  ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */
+#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */
+#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */
+#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */
+#define AT91C_PIOD_ISR  ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */
+#define AT91C_PIOD_IDR  ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */
+#define AT91C_PIOD_PDR  ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */
+#define AT91C_PIOD_ODR  ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */
+#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */
+#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */
+#define AT91C_PIOD_ASR  ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */
+#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */
+#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */
+#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */
+#define AT91C_PIOD_PSR  ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */
+#define AT91C_PIOD_OER  ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */
+#define AT91C_PIOD_OSR  ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */
+#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */
+#define AT91C_PIOD_BSR  ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */
+#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */
+#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */
+
+#define AT91C_PIO_PD0   ((unsigned int) 1 <<  0) /* Pin Controlled by PD0 */
+#define AT91C_PD0_ETX0  ((unsigned int) AT91C_PIO_PD0) /*  Enet MAC Tx Data 0*/
+#define AT91C_PIO_PD1   ((unsigned int) 1 <<  1) /* Pin Controlled by PD1 */
+#define AT91C_PD1_ETX1  ((unsigned int) AT91C_PIO_PD1) /*  Enet MAC Tx Data 1*/
+#define AT91C_PIO_PD10  ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */
+#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/
+#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */
+#define AT91C_PIO_PD11  ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */
+#define AT91C_PD11_     ((unsigned int) AT91C_PIO_PD11) /*   */
+#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */
+#define AT91C_PIO_PD12  ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */
+#define AT91C_PD12_     ((unsigned int) AT91C_PIO_PD12) /*   */
+#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */
+#define AT91C_PIO_PD13  ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */
+#define AT91C_PD13_     ((unsigned int) AT91C_PIO_PD13) /*   */
+#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */
+#define AT91C_PIO_PD14  ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */
+#define AT91C_PD14_     ((unsigned int) AT91C_PIO_PD14) /*   */
+#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */
+#define AT91C_PIO_PD15  ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */
+#define AT91C_PD15_TD0  ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */
+#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */
+#define AT91C_PIO_PD16  ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */
+#define AT91C_PD16_TD1  ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */
+#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */
+#define AT91C_PIO_PD17  ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */
+#define AT91C_PD17_TD2  ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */
+#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */
+#define AT91C_PIO_PD18  ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */
+#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /*  SPI Perip CS 1 */
+#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */
+#define AT91C_PIO_PD19  ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */
+#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /*  SPI Perip CS 2 */
+#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */
+#define AT91C_PIO_PD2   ((unsigned int) 1 <<  2) /* Pin Controlled by PD2 */
+#define AT91C_PD2_ETX2  ((unsigned int) AT91C_PIO_PD2) /*  Ethernet MAC TxD 2 */
+#define AT91C_PIO_PD20  ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */
+#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */
+#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */
+#define AT91C_PIO_PD21  ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */
+#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */
+#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */
+#define AT91C_PIO_PD22  ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */
+#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /*  Usart 0 RTS */
+#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */
+#define AT91C_PIO_PD23  ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */
+#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */
+#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */
+#define AT91C_PIO_PD24  ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */
+#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /*  USART 3 RTS */
+#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */
+#define AT91C_PIO_PD25  ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */
+#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */
+#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */
+#define AT91C_PIO_PD26  ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */
+#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */
+#define AT91C_PIO_PD27  ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */
+#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */
+#define AT91C_PIO_PD3   ((unsigned int) 1 <<  3) /* Pin Controlled by PD3 */
+#define AT91C_PD3_ETX3  ((unsigned int) AT91C_PIO_PD3) /*  Enet MAC TxD 3 */
+#define AT91C_PIO_PD4   ((unsigned int) 1 <<  4) /* Pin Controlled by PD4 */
+#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */
+#define AT91C_PIO_PD5   ((unsigned int) 1 <<  5) /* Pin Controlled by PD5 */
+#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /*  Enet MAC TxCE */
+#define AT91C_PIO_PD6   ((unsigned int) 1 <<  6) /* Pin Controlled by PD6 */
+#define AT91C_PD6_DTXD  ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */
+#define AT91C_PIO_PD7   ((unsigned int) 1 <<  7) /* Pin Controlled by PD7 */
+#define AT91C_PD7_PCK0  ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/
+#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */
+#define AT91C_PIO_PD8   ((unsigned int) 1 <<  8) /* Pin Controlled by PD8 */
+#define AT91C_PD8_PCK1  ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/
+#define AT91C_PD8_TCLK  ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */
+#define AT91C_PIO_PD9   ((unsigned int) 1 <<  9) /* Pin Controlled by PD9 */
+#define AT91C_PD9_PCK2  ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */
+#define AT91C_PD9_TPS0  ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */
+#define AT91C_PIO_PB6   ((unsigned int) 1 <<  6) /* Pin Controlled by PB6 */
+#define AT91C_PIO_PC5   ((unsigned int) 1 <<  5)
+#define AT91C_PIO_PC14  ((unsigned int) 1 <<  14) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PC15  ((unsigned int) 1 <<  15) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PA19  ((unsigned int) 1 <<  19) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB2   ((unsigned int) 1 <<  2) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB8   ((unsigned int) 1 <<  8)
+#define AT91C_PIO_PB9   ((unsigned int) 1 <<  9)
+#define AT91C_PIO_PB10  ((unsigned int) 1 <<  10)
+#define AT91C_PIO_PB11  ((unsigned int) 1 <<  11)
+#define AT91C_PIO_PB17  ((unsigned int) 1 <<  17)
+#define AT91C_PIO_PB28  ((unsigned int) 1 <<  28)
+#define AT91C_PIO_PB29  ((unsigned int) 1 <<  29)
+
+typedef enum {
+	M501SK_BUZZER = 38,
+	M501SK_DEBUG_LED1 = 96,
+	M501SK_DEBUG_LED2,
+	M501SK_DEBUG_LED3,
+	M501SK_DEBUG_LED4,
+	M501SK_READY_LED = 102,
+} M501SK_PIO;
+
+void m501sk_gpio_init(void);
+uchar m501sk_gpio_set(M501SK_PIO io);
+uchar m501sk_gpio_clear(M501SK_PIO io);
+
+#endif
diff --git a/u-boot/board/manroland/hmi1001/Makefile b/u-boot/board/manroland/hmi1001/Makefile
new file mode 100644
index 0000000..d3c31d6
--- /dev/null
+++ b/u-boot/board/manroland/hmi1001/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/manroland/hmi1001/hmi1001.c b/u-boot/board/manroland/hmi1001/hmi1001.c
new file mode 100644
index 0000000..9cbed4b
--- /dev/null
+++ b/u-boot/board/manroland/hmi1001/hmi1001.c
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2003-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <malloc.h>
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+	uint svr, pvr;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: HMI1001\n");
+	return 0;
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[]		= "key_magic";
+static uchar kbd_command_prefix[]	= "key_cmd";
+
+#define S1_ROT	0xf0
+#define S2_Q	0x40
+#define S2_M	0x20
+
+struct kbd_data_t {
+	char s1;
+	char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+	kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE));
+	kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE));
+
+	return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+	char s1 = str[0];
+	char s2;
+
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (((S1_ROT & kbd_data->s1) >> 4) != s1)
+		return -1;
+
+	s2 = (S2_Q | S2_M) & kbd_data->s2;
+
+	switch (str[1]) {
+	case 'q':
+	case 'Q':
+		if (s2 == S2_Q)
+			return -1;
+		break;
+	case 'm':
+	case 'M':
+		if (s2 == S2_M)
+			return -1;
+		break;
+	case '\0':
+		if (s2 == (S2_Q | S2_M))
+			return 0;
+	default:
+		return -1;
+	}
+
+	if (str[2])
+		return -1;
+
+	return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can be appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix = kbd_magic_keys; *suffix ||
+		     suffix == kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv (cmd_name);
+
+			return (cmd);
+		}
+	}
+
+	return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PREBOOT
+	struct kbd_data_t kbd_data;
+	/* Decode keys */
+	char *str = strdup (key_match (get_keys (&kbd_data)));
+	/* Set or delete definition */
+	setenv ("preboot", str);
+	free (str);
+#endif /* CONFIG_PREBOOT */
+
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
+	return 0;
+}
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/u-boot/board/manroland/mucmc52/Makefile b/u-boot/board/manroland/mucmc52/Makefile
new file mode 100644
index 0000000..a3b4e4c
--- /dev/null
+++ b/u-boot/board/manroland/mucmc52/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2008
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/manroland/mucmc52/mucmc52.c b/u-boot/board/manroland/mucmc52/mucmc52.c
new file mode 100644
index 0000000..66973f0
--- /dev/null
+++ b/u-boot/board/manroland/mucmc52/mucmc52.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
+		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
+		(SDRAM_MODE | 0x04000000));
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
+		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
+		(SDRAM_CONTROL | hi_addr_bit));
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start (0);
+	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start (0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
+			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+		out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start (0);
+	test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+	if (!dramsize) {
+		sdram_start (1);
+		test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+	}
+	if (test1 > test2) {
+		sdram_start (0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
+			(dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+	} else {
+		out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	 /*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: MUC.MC-52 HW WDT ");
+#if defined(CONFIG_HW_WATCHDOG)
+	puts ("enabled\n");
+#else
+	puts ("disabled\n");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[]		= "key_magic";
+static uchar kbd_command_prefix[]	= "key_cmd";
+
+#define S1_ROT	0xf0
+#define S2_Q	0x40
+#define S2_M	0x20
+
+struct kbd_data_t {
+	char s1;
+	char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+	kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
+	kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
+
+	return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+	char s1 = str[0];
+	char s2;
+
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (((S1_ROT & kbd_data->s1) >> 4) != s1)
+		return -1;
+
+	s2 = (S2_Q | S2_M) & kbd_data->s2;
+
+	switch (str[1]) {
+	case 'q':
+	case 'Q':
+		if (s2 == S2_Q)
+			return -1;
+		break;
+	case 'm':
+	case 'M':
+		if (s2 == S2_M)
+			return -1;
+		break;
+	case '\0':
+		if (s2 == (S2_Q | S2_M))
+			return 0;
+	default:
+		return -1;
+	}
+
+	if (str[2])
+		return -1;
+
+	return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can be appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix = kbd_magic_keys; *suffix ||
+		     suffix == kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv (cmd_name);
+
+			return (cmd);
+		}
+	}
+
+	return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PREBOOT
+	struct kbd_data_t kbd_data;
+	/* Decode keys */
+	char *str = strdup (key_match (get_keys (&kbd_data)));
+	/* Set or delete definition */
+	setenv ("preboot", str);
+	free (str);
+#endif /* CONFIG_PREBOOT */
+
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
+
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
+	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
+	out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
+	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
+		STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
+	out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
+		STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
+	return 0;
+}
+
+int last_stage_init (void)
+{
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
+
+	return 0;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+#define GPT_OUT_0	0x00000027
+#define GPT_OUT_1	0x00000037
+void hw_watchdog_reset (void)
+{
+	/* Trigger HW Watchdog with TIMER_0 */
+	out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
+	out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init (struct pci_controller *);
+
+void pci_init_board (void)
+{
+	pci_mpc5xxx_init (&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/manroland/uc100/Makefile b/u-boot/board/manroland/uc100/Makefile
new file mode 100644
index 0000000..c1a385b
--- /dev/null
+++ b/u-boot/board/manroland/uc100/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+#COBJS	= $(BOARD).o flash.o pcmcia.o
+COBJS	= $(BOARD).o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/manroland/uc100/pcmcia.c b/u-boot/board/manroland/uc100/pcmcia.c
new file mode 100644
index 0000000..ad25678
--- /dev/null
+++ b/u-boot/board/manroland/uc100/pcmcia.c
@@ -0,0 +1,198 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if (defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "UC100"
+
+/*
+ * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
+ *         This leads to board-hangup! (sr, 8 Dez. 2004)
+ */
+static void cfg_ports (void)
+{
+	volatile immap_t	*immap;
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	* Configure Port A for MAX1602 PC-Card Power-Interface Switch
+	*/
+	immap->im_ioport.iop_padat &= ~0x8000;	/* set port x output to low */
+	immap->im_ioport.iop_padir |= 0x8000;	/* enable port x as output */
+
+	debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
+	       immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
+	       immap->im_ioport.iop_padat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, mask;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+	cfg_ports ();
+
+	/*
+	* Configure SIUMCR to enable PCMCIA port B
+	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	*/
+	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On.
+	*/
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	reg  = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       reg,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+	if ((reg & mask) == mask) {
+		puts (" 5.0V card found: ");
+	} else {
+		puts (" 3.3V card found: ");
+	}
+
+	/*  switch VCC on */
+	immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
+
+	udelay(10000);
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* switch VCC off */
+	immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("voltage_set: "
+			PCMCIA_BOARD_MSG
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	* Disable PCMCIA buffers (isolate the interface)
+	* and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Configure Port C pins for
+	* 5 Volts Enable and 3 Volts enable,
+	* Turn all power pins to Hi-Z
+	*/
+	debug ("PCMCIA power OFF\n");
+	cfg_ports ();	/* Enables switch, but all in Hi-Z */
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/manroland/uc100/u-boot.lds b/u-boot/board/manroland/uc100/u-boot.lds
new file mode 100644
index 0000000..dc83071
--- /dev/null
+++ b/u-boot/board/manroland/uc100/u-boot.lds
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/manroland/uc100/uc100.c b/u-boot/board/manroland/uc100/uc100.c
new file mode 100644
index 0000000..959b2ad
--- /dev/null
+++ b/u-boot/board/manroland/uc100/uc100.c
@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/*********************************************************************/
+/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B)     */
+/*********************************************************************/
+const uint sdram_init_upm_table[] = {
+	/* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
+	/* NOP    - Precharge - AutoRefr  - NOP       - NOP        */
+	/* NOP    - AutoRefr  - NOP                                */
+	/* NOP    - NOP       - LoadModeR - NOP       - Active     */
+	/* Position of Single Read                                 */
+	0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
+	0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
+
+	/* Burst Read. (offset 8 in UPMA RAM)     */
+	/* Cycle lent for Initialisation WV */
+	0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Single Write. (offset 18 in UPMA RAM) */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Burst Write. (offset 20 in UPMA RAM) */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh  (offset 30 in UPMA RAM) */
+	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
+	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception. (offset 3c in UPMA RAM) */
+	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+/*********************************************************************/
+/* UPMA initilization table.                                         */
+/*********************************************************************/
+const uint sdram_upm_table[] = {
+	/* single read. (offset 0 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     /* 0x05-0x07 new WV */
+
+	/* Burst Read. (offset 8 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
+	0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Single Write. (offset 18 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Burst Write. (offset 20 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
+	0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh  (offset 30 in UPMA RAM) */
+	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
+	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception. (offset 3c in UPMA RAM) */
+	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
+};
+
+/*********************************************************************/
+/* UPMB initilization table.                                         */
+/*********************************************************************/
+const uint mpm_upm_table[] = {
+	/*  single read. (offset 0 in upm RAM) */
+	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
+	0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* burst read. (Offset 8 in upm RAM)   */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* single write. (Offset 0x18 in upm RAM) */
+	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
+	0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*  burst write. (Offset 0x20 in upm RAM) */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh cycle, offset 0x30 */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception, 0ffset 0x3C */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+
+int board_switch(void)
+{
+	volatile pcmconf8xx_t	*pcmp;
+
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	return ((pcmp->pcmc_pipr >> 24) & 0xf);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming UC100");
+	} else {
+		puts(str);
+	}
+
+	printf (" (SWITCH=%1X)\n", board_switch());
+
+	return 0;
+}
+
+
+/*
+ * Initialize SDRAM
+ */
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/*---------------------------------------------------------------------*/
+	/* Initialize the UPMA/UPMB registers with the appropriate table.      */
+	/*---------------------------------------------------------------------*/
+	upmconfig (UPMA, (uint *) sdram_init_upm_table,
+		   sizeof (sdram_init_upm_table) / sizeof (uint));
+	upmconfig (UPMB, (uint *) mpm_upm_table,
+		   sizeof (mpm_upm_table) / sizeof (uint));
+
+	/*---------------------------------------------------------------------*/
+	/* Memory Periodic Timer Prescaler: divide by 16                       */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
+
+	/*---------------------------------------------------------------------*/
+	/* Initialize the Memory Controller registers, MPTPR, Chip Select 1    */
+	/* for SDRAM                                                           */
+	/*                                                                     */
+	/* NOTE: The refresh rate in MAMR reg is set according to the lowest   */
+	/*       clock rate (16.67MHz) to allow proper operation for all ADS   */
+	/*       clock frequencies.                                            */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	/*-------------------------------------------------------------------*/
+	/* Wait at least 200 usec for DRAM to stabilize, this magic number   */
+	/* obtained from the init code.                                      */
+	/*-------------------------------------------------------------------*/
+	udelay(200);
+
+	memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
+
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+
+	/*---------------------------------------------------------------------*/
+	/* run MRS command in location 5-8 of UPMB.                            */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_mar = 0x88;
+	/* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
+
+	memctl->memc_mcr = 0x80002100;
+	/* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
+
+	udelay(200);
+
+	/*---------------------------------------------------------------------*/
+	/* Initialisation for normal access WV                                 */
+	/*---------------------------------------------------------------------*/
+
+	/*---------------------------------------------------------------------*/
+	/* Initialize the UPMA register with the appropriate table.            */
+	/*---------------------------------------------------------------------*/
+	upmconfig (UPMA, (uint *) sdram_upm_table,
+		   sizeof (sdram_upm_table) / sizeof (uint));
+
+	/*---------------------------------------------------------------------*/
+	/* rerstore MBMR value (4-beat refresh burst.)                         */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
+
+	udelay(200);
+
+	return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
+}
+
+
+int misc_init_r (void)
+{
+	uchar val;
+
+	/*
+	 * Make sure that RTC has clock output enabled (triggers watchdog!)
+	 */
+	val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
+	val |= 0x80;
+	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
+
+	/*
+	 * Configure PHY to setup LED's correctly and use 100MBit, FD
+	 */
+	mii_init();
+
+	/* disable auto-negotiation, 100mbit, full-duplex */
+	fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100);
+
+	/* set LED's to Link, Transmit, Receive           */
+	fec8xx_miiphy_write(NULL,  0, MII_NWAYTEST, 0x4122);
+
+	return 0;
+}
diff --git a/u-boot/board/manroland/uc101/Makefile b/u-boot/board/manroland/uc101/Makefile
new file mode 100644
index 0000000..d3c31d6
--- /dev/null
+++ b/u-boot/board/manroland/uc101/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/manroland/uc101/uc101.c b/u-boot/board/manroland/uc101/uc101.c
new file mode 100644
index 0000000..c7dfb7b
--- /dev/null
+++ b/u-boot/board/manroland/uc101/uc101.c
@@ -0,0 +1,381 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <malloc.h>
+
+/* some SIMPLE GPIO Pins */
+#define GPIO_USB_8	(31-12)
+#define GPIO_USB_7	(31-13)
+#define GPIO_USB_6	(31-14)
+#define GPIO_USB_0	(31-15)
+#define GPIO_PSC3_7	(31-18)
+#define GPIO_PSC3_6	(31-19)
+#define GPIO_PSC3_1	(31-22)
+#define GPIO_PSC3_0	(31-23)
+
+/* some simple Interrupt GPIO Pins */
+#define GPIO_PSC3_8	2
+#define GPIO_USB1_9	3
+
+#define GPT_OUT_0	0x00000027
+#define GPT_OUT_1	0x00000037
+#define	GPT_DISABLE	0x00000000	/* GPT pin disabled */
+
+#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
+				pgpio->simple_ddr |= (1 << n); \
+				pgpio->simple_gpioe |= (1 << n); \
+				}
+
+#define GP_SIMP_ENABLE_I(n) {	pgpio->simple_ddr |= ~(1 << n); \
+				pgpio->simple_gpioe |= (1 << n); \
+				}
+
+#define GP_SIMP_SET_O(n, v)  (pgpio->simple_dvo = v ? \
+				(pgpio->simple_dvo | (1 << n)) : \
+				(pgpio->simple_dvo & ~(1 << n)) )
+
+#define GP_SIMP_GET_O(n)  ((pgpio->simple_dvo >> n) & 1)
+#define GP_SIMP_GET_I(n)  ((pgpio->simple_ival >> n) & 1)
+
+#define GP_SINT_SET_O(n, v)  (pgpio->sint_dvo = v ? \
+				(pgpio->sint_dvo | (1 << n)) : \
+				(pgpio->sint_dvo & ~(1 << n)) )
+
+#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
+				pgpio->sint_ddr |= (1 << n); \
+				GP_SINT_SET_O(n, v); \
+				pgpio->sint_gpioe |= (1 << n); \
+				}
+
+#define GP_SINT_ENABLE_I(n) {	pgpio->sint_ddr |= ~(1 << n); \
+				pgpio->sint_gpioe |= (1 << n); \
+				}
+
+#define GP_SINT_GET_O(n)  ((pgpio->sint_ival >> n) & 1)
+#define GP_SINT_GET_I(n)  ((pgpio-ntt_ival >> n) & 1)
+
+#define GP_TIMER_ENABLE_O(n, v) ( \
+	((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
+				GPT_OUT_1 : \
+				GPT_OUT_0 )
+
+#define GP_TIMER_SET_O(n, v)	GP_TIMER_ENABLE_O(n, v)
+
+#define GP_TIMER_GET_O(n, v) ( \
+	(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
+
+#define GP_TIMER_GET_I(n, v) ( \
+	(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: MAN UC101\n");
+	/* clear the Display */
+	*(char *)(CONFIG_SYS_DISP_CWORD) = 0x80;
+	return 0;
+}
+
+static void init_ports (void)
+{
+	volatile struct mpc5xxx_gpio *pgpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	GP_SIMP_ENABLE_I(GPIO_USB_8);	/* HEX Bit 3 */
+	GP_SIMP_ENABLE_I(GPIO_USB_7);	/* HEX Bit 2 */
+	GP_SIMP_ENABLE_I(GPIO_USB_6);	/* HEX Bit 1 */
+	GP_SIMP_ENABLE_I(GPIO_USB_0);	/* HEX Bit 0 */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_0);	/* Switch Menue A */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_1);	/* Switch Menue B */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_6);	/* Switch Cold_Warm */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_7);	/* Switch Restart */
+	GP_SINT_ENABLE_O(GPIO_PSC3_8, 0);	/* LED H2 */
+	GP_SINT_ENABLE_O(GPIO_USB1_9, 0);	/* LED H3 */
+	GP_TIMER_ENABLE_O(4, 0);	/* LED H4 */
+	GP_TIMER_ENABLE_O(5, 0);	/* LED H5 */
+	GP_TIMER_ENABLE_O(3, 0);	/* LED HB */
+	GP_TIMER_ENABLE_O(1, 0);	/* RES_COLDSTART */
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[]		= "key_magic";
+static uchar kbd_command_prefix[]	= "key_cmd";
+
+struct kbd_data_t {
+	char s1;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+	volatile struct mpc5xxx_gpio *pgpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
+			GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
+			GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
+			GP_SIMP_GET_I(GPIO_USB_0) << 0;
+	return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+	char s1 = str[0];
+
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (s1 != kbd_data->s1) return -1;
+	return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can be appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix = kbd_magic_keys; *suffix ||
+		     suffix == kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv (cmd_name);
+
+			return (cmd);
+		}
+	}
+
+	return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r (void)
+{
+	/* Init the I/O ports */
+	init_ports ();
+
+#ifdef CONFIG_PREBOOT
+	struct kbd_data_t kbd_data;
+	/* Decode keys */
+	char *str = strdup (key_match (get_keys (&kbd_data)));
+	/* Set or delete definition */
+	setenv ("preboot", str);
+	free (str);
+#endif /* CONFIG_PREBOOT */
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
+	/* Interbus enable it here ?? */
+	*(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
+	return 0;
+}
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	/* Trigger HW Watchdog with TIMER_0 */
+	*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
+	*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/matrix_vision/common/Makefile b/u-boot/board/matrix_vision/common/Makefile
new file mode 100644
index 0000000..2ad54a0
--- /dev/null
+++ b/u-boot/board/matrix_vision/common/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS-y	= mv_common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/matrix_vision/common/mv_common.c b/u-boot/board/matrix_vision/common/mv_common.c
new file mode 100644
index 0000000..0afc535
--- /dev/null
+++ b/u-boot/board/matrix_vision/common/mv_common.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <environment.h>
+#include <fpga.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char* entries_to_keep[] = {
+	"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
+	"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
+	"static_ipaddr", "static_netmask", "static_gateway",
+	"syslog", "watchdog", "netboot", "evo8serialnumber" };
+
+#define MV_MAX_ENV_ENTRY_LENGTH	64
+#define MV_KEEP_ENTRIES		ARRAY_SIZE(entries_to_keep)
+
+void mv_reset_environment(void)
+{
+	int i;
+	char *s[MV_KEEP_ENTRIES];
+	char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
+
+	printf("\n*** RESET ENVIRONMENT ***\n");
+
+	memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
+	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
+		s[i] = getenv(entries_to_keep[i]);
+		if (s[i]) {
+			printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
+			strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
+		}
+	}
+
+	gd->env_valid = 0;
+	env_relocate();
+
+	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
+		if (s[i]) {
+			printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
+			setenv(entries_to_keep[i], s[i]);
+		}
+	}
+
+	saveenv();
+}
+
+int mv_load_fpga(void)
+{
+	int result;
+	size_t data_size = 0;
+	void *fpga_data = NULL;
+	char *datastr = getenv("fpgadata");
+	char *sizestr = getenv("fpgadatasize");
+
+	if (getenv("skip_fpga")) {
+		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+		return -1;
+	}
+	printf("loading FPGA\n");
+
+	if (datastr)
+		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+	if (sizestr)
+		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+	if (!data_size) {
+		printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
+		return -1;
+	}
+
+	result = fpga_load(0, fpga_data, data_size);
+	if (!result)
+		show_boot_progress(0);
+
+	return result;
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+	char *ptr;
+
+	/* DHCP vendor-class-identifier = 60 */
+	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* DHCP_CLIENT_IDENTIFIER = 61 */
+	if ((ptr = getenv("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+
+	return e;
+}
+
+u8 *dhcp_vendorex_proc(u8 *popt)
+{
+	return NULL;
+}
diff --git a/u-boot/board/matrix_vision/common/mv_common.h b/u-boot/board/matrix_vision/common/mv_common.h
new file mode 100644
index 0000000..046c038
--- /dev/null
+++ b/u-boot/board/matrix_vision/common/mv_common.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2008 Matrix Vision GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern int mv_load_fpga(void);
+extern void mv_reset_environment(void);
diff --git a/u-boot/board/matrix_vision/mvbc_p/Makefile b/u-boot/board/matrix_vision/mvbc_p/Makefile
new file mode 100644
index 0000000..9ee0895
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	        $(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/matrix_vision/mvbc_p/fpga.c b/u-boot/board/matrix_vision/mvbc_p/fpga.c
new file mode 100644
index 0000000..3ed46fe
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/fpga.c
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)	printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	passive_serial,
+	Altera_EP2C8_SIZE,
+	(void *) &altera_fns,
+	NULL,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvbc_p_init_fpga(void)
+{
+	fpga_debug("Initialize FPGA interface\n");
+	fpga_init();
+	fpga_add(fpga_altera, &cyclone2);
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	u32 dvo = gpio->simple_dvo;
+
+	fpga_debug("SET config : %s\n", assert ? "low" : "high");
+	if (assert)
+		dvo |= FPGA_CONFIG;
+	else
+		dvo &= ~FPGA_CONFIG;
+
+	if (flush)
+		gpio->simple_dvo = dvo;
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	int result = 0;
+
+	udelay(10);
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio->simple_ival & FPGA_CONF_DONE) {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	int result = 0;
+
+	fpga_debug("STATUS check ... ");
+	if (gpio->sint_ival & FPGA_STATUS) {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	u32 dvo = gpio->simple_dvo;
+
+	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+	if (assert_clk)
+		dvo |= FPGA_CCLK;
+	else
+		dvo &= ~FPGA_CCLK;
+
+	if (flush)
+		gpio->simple_dvo = dvo;
+
+	return assert_clk;
+}
+
+static inline int _write_fpga(u8 val)
+{
+	int i;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+	u32 dvo = gpio->simple_dvo;
+
+	for (i=0; i<8; i++) {
+		dvo &= ~FPGA_CCLK;
+		gpio->simple_dvo = dvo;
+		dvo &= ~FPGA_DIN;
+		if (val & 1)
+			dvo |= FPGA_DIN;
+		gpio->simple_dvo = dvo;
+		dvo |= FPGA_CCLK;
+		gpio->simple_dvo = dvo;
+		val >>= 1;
+	}
+
+	return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+	unsigned char *data = (unsigned char *) buf;
+	int i;
+
+	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+	for (i = 0; i < len; i++)
+		_write_fpga(data[i]);
+	fpga_debug("\n");
+
+	return FPGA_SUCCESS;
+}
diff --git a/u-boot/board/matrix_vision/mvbc_p/fpga.h b/u-boot/board/matrix_vision/mvbc_p/fpga.h
new file mode 100644
index 0000000..3723073
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvbc_p_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c
new file mode 100644
index 0000000..4392176
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2007
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+	long hi_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+	/* auto refresh */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
+
+	/* set mode register */
+	out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1,
+	      test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+	/* setup config registers */
+	out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	if (dramsize > 0)
+		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1);
+	else
+		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
+
+	return dramsize;
+}
+
+void mvbc_init_gpio(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	printf("Ports : 0x%08x\n", gpio->port_config);
+	printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
+
+	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+	out_be32(&gpio->simple_ode, SIMPLE_ODE);
+	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+	out_8(&gpio->sint_ode, SINT_ODE);
+	out_8(&gpio->sint_ddr, SINT_DDR);
+	out_8(&gpio->sint_dvo, SINT_DVO);
+	out_8(&gpio->sint_inten, SINT_INTEN);
+	out_be16(&gpio->sint_itype, SINT_ITYPE);
+	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+	out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
+	out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
+	out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
+	out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
+
+	printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
+	printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (!s) {
+		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+			return 0;
+		udelay(50000);
+		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+			return 0;
+		udelay(50000);
+		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+			return 0;
+	}
+	printf(" === FACTORY RESET ===\n");
+	mv_reset_environment();
+	saveenv();
+
+	return -1;
+}
+
+int checkboard(void)
+{
+	mvbc_init_gpio();
+	printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
+		size));
+	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
+		size));
+	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
+		size));
+	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
+		size));
+}
+
+void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line = 0xff;
+	char *s = getenv("pci_latency");
+	u32 base;
+	u8 val = 0;
+
+	if (s)
+		val = simple_strtoul(s, NULL, 16);
+
+	if (PCI_BUS(dev) == 0) {
+		switch (PCI_DEV (dev)) {
+		case 0xa: /* FPGA */
+			line = 3;
+			pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
+			printf("found FPGA - enable arbitration\n");
+			writel(0x03, (u32*)(base + 0x80c0));
+			writel(0xf0, (u32*)(base + 0x8080));
+			if (val)
+				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
+			break;
+		case 0xb: /* LAN */
+			line = 2;
+			if (val)
+				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
+			break;
+		case 0x1a:
+			break;
+		default:
+			printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
+			break;
+		}
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
+	}
+}
+
+struct pci_controller hose = {
+	fixup_irq:pci_mvbc_fixup_irq
+};
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	mvbc_p_init_fpga();
+	mv_load_fpga();
+	pci_mpc5xxx_init(&hose);
+}
+
+void show_boot_progress(int val)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	switch(val) {
+	case 0: /* FPGA ok */
+		setbits_be32(&gpio->simple_dvo, LED_G0);
+		break;
+	case 65:
+		setbits_be32(&gpio->simple_dvo, LED_G1);
+		break;
+	case 12:
+		setbits_be32(&gpio->simple_dvo, LED_Y);
+		break;
+	case 15:
+		setbits_be32(&gpio->simple_dvo, LED_R);
+		break;
+	default:
+		break;
+	}
+
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h
new file mode 100644
index 0000000..be1542b
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h
@@ -0,0 +1,43 @@
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define LED_G0          MPC5XXX_GPIO_SIMPLE_PSC2_0
+#define LED_G1          MPC5XXX_GPIO_SIMPLE_PSC2_1
+#define LED_Y           MPC5XXX_GPIO_SIMPLE_PSC2_2
+#define LED_R           MPC5XXX_GPIO_SIMPLE_PSC2_3
+#define ARB_X_EN        MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define FPGA_DIN        MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK       MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_CONF_DONE  MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG     MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS     MPC5XXX_GPIO_SINT_PSC3_4
+
+#define MAN_RST         MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS           MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI          MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT     MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define FACT_RST        MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY       MPC5XXX_GPIO_WKUP_7
+
+#define SIMPLE_DDR      (LED_G0 | LED_G1 | LED_Y | LED_R | \
+			 FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
+#define SIMPLE_DVO      (FPGA_CONFIG)
+#define SIMPLE_ODE      (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
+#define SIMPLE_GPIOEN   (LED_G0 | LED_G1 | LED_Y | LED_R | \
+			 FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
+			 WD_WDI | COP_PRESENT)
+
+#define SINT_ODE        0
+#define SINT_DDR        0
+#define SINT_DVO        0
+#define SINT_INTEN      0
+#define SINT_ITYPE      0
+#define SINT_GPIOEN     (FPGA_STATUS)
+
+#define WKUP_ODE        (MAN_RST)
+#define WKUP_DIR        (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_DO         (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_EN         (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
+
+#endif
diff --git a/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript
new file mode 100644
index 0000000..9b21f30
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript
@@ -0,0 +1,48 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
+setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${oprofile} = yes;
+then
+setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
+fi
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip
+      run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  run set_static_ip set_static_nm set_static_gw set_ip
+  echo "=== bootfromflash ==="
+  run cpdtb rundtb bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/u-boot/board/matrix_vision/mvblm7/Makefile b/u-boot/board/matrix_vision/mvblm7/Makefile
new file mode 100644
index 0000000..2ee74e0
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o pci.o fpga.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+	@mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/matrix_vision/mvblm7/bootscript b/u-boot/board/matrix_vision/mvblm7/bootscript
new file mode 100644
index 0000000..dc385fd
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/bootscript
@@ -0,0 +1,43 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip
+      run getdtb rundtb bootfromnet ramparam addcons bootdtb
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  run set_static_ip set_static_nm set_static_gw set_ip
+  echo "=== bootfromflash ==="
+  run cpdtb rundtb bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/u-boot/board/matrix_vision/mvblm7/fpga.c b/u-boot/board/matrix_vision/mvblm7/fpga.c
new file mode 100644
index 0000000..7b03d6f
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/fpga.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvblm7.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	passive_serial,
+	Altera_EP2C20_SIZE,
+	(void *) &altera_fns,
+	NULL,
+	0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_init_fpga(void)
+{
+	fpga_debug("Initialize FPGA interface\n");
+	fpga_init();
+	fpga_add(fpga_altera, &cyclone2);
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	u32 dvo = gpio->dat;
+
+	fpga_debug("SET config : %s\n", assert ? "low" : "high");
+	if (assert)
+		dvo |= FPGA_CONFIG;
+	else
+		dvo &= ~FPGA_CONFIG;
+
+	if (flush)
+		gpio->dat = dvo;
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	udelay(10);
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio->dat & FPGA_CONF_DONE)  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	fpga_debug("STATUS check ... ");
+	if (gpio->dat & FPGA_STATUS)  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	u32 dvo = gpio->dat;
+
+	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+	if (assert_clk)
+		dvo |= FPGA_CCLK;
+	else
+		dvo &= ~FPGA_CCLK;
+
+	if (flush)
+		gpio->dat = dvo;
+
+	return assert_clk;
+}
+
+static inline int _write_fpga(u8 val, int dump)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int i;
+	u32 dvo = gpio->dat;
+
+	if (dump)
+		fpga_debug("  %02x -> ", val);
+	for (i = 0; i < 8; i++) {
+		dvo &= ~FPGA_CCLK;
+		gpio->dat = dvo;
+		dvo &= ~FPGA_DIN;
+		if (dump)
+			fpga_debug("%d ", val&1);
+		if (val & 1)
+			dvo |= FPGA_DIN;
+		gpio->dat = dvo;
+		dvo |= FPGA_CCLK;
+		gpio->dat = dvo;
+		val >>= 1;
+	}
+	if (dump)
+		fpga_debug("\n");
+
+	return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+	unsigned char *data = (unsigned char *) buf;
+	int i;
+
+	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+	for (i = 0; i < len; i++)
+		_write_fpga(data[i], 0);
+	fpga_debug("\n");
+
+	return FPGA_SUCCESS;
+}
diff --git a/u-boot/board/matrix_vision/mvblm7/fpga.h b/u-boot/board/matrix_vision/mvblm7/fpga.h
new file mode 100644
index 0000000..19277eb
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblm7_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/u-boot/board/matrix_vision/mvblm7/mvblm7.c b/u-boot/board/matrix_vision/mvblm7/mvblm7.c
new file mode 100644
index 0000000..6a4ed52
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/mvblm7.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <spi.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "../common/mv_common.h"
+#include "mvblm7.h"
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+	char *s = getenv("ddr_size");
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	if (s) {
+		u32 env_ddr_size = simple_strtoul(s, NULL, 10);
+		if (env_ddr_size == 512)
+			msize = 512;
+	}
+
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1)
+			return -1;
+	}
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+		LAWAR_SIZE);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+
+	asm("sync;isync");
+	udelay(600);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	asm("sync;isync");
+	udelay(500);
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+	msize = fixed_sdram();
+
+	/* return total bus RAM size(bytes) */
+	return msize * 1024 * 1024;
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		mv_reset_environment();
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Matrix Vision mvBlueLYNX-M7\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_HARD_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat &= ~MVBLM7_MMC_CS;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat |= ~MVBLM7_MMC_CS;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+
+#endif
diff --git a/u-boot/board/matrix_vision/mvblm7/mvblm7.h b/u-boot/board/matrix_vision/mvblm7/mvblm7.h
new file mode 100644
index 0000000..de9fec7
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/mvblm7.h
@@ -0,0 +1,20 @@
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define MV_GPIO
+
+#define FPGA_CONFIG     0x80000000
+#define FPGA_CCLK       0x40000000
+#define FPGA_DIN        0x20000000
+#define FPGA_STATUS     0x10000000
+#define FPGA_CONF_DONE  0x08000000
+
+#define WD_WDI          0x00400000
+#define WD_TS           0x00200000
+#define MAN_RST         0x00100000
+
+#define MV_GPIO_DAT	(WD_TS)
+#define MV_GPIO_OUT	(FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
+#define MV_GPIO_ODE	(FPGA_CONFIG|MAN_RST)
+
+#endif
diff --git a/u-boot/board/matrix_vision/mvblm7/pci.c b/u-boot/board/matrix_vision/mvblm7/pci.c
new file mode 100644
index 0000000..921e80b
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvblm7/pci.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fpga.h>
+#include "mvblm7.h"
+#include "fpga.h"
+#include "../common/mv_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	int i;
+	volatile immap_t *immr;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile gpio83xx_t *gpio;
+	volatile clk83xx_t *clk;
+	volatile law83xx_t *pci_law;
+	struct pci_region *reg[] = { pci_regions };
+
+	immr = (immap_t *) CONFIG_SYS_IMMR;
+	clk = (clk83xx_t *) &immr->clk;
+	pci_ctrl = immr->pci_ctrl;
+	pci_law = immr->sysconf.pcilaw;
+	gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
+
+	gpio->dat = MV_GPIO_DAT;
+	gpio->odr = MV_GPIO_ODE;
+	gpio->dir = MV_GPIO_OUT;
+
+	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
+		immr->sysconf.sicrl);
+
+	mvblm7_init_fpga();
+	mv_load_fpga();
+
+	gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+
+	/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
+	clk->occr = 0xc0000000;
+
+	pci_ctrl[0].gcr = 0;
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+
+	for (i = 0; i < 1000; ++i)
+		udelay(1000);
+
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
diff --git a/u-boot/board/matrix_vision/mvsmr/Makefile b/u-boot/board/matrix_vision/mvsmr/Makefile
new file mode 100644
index 0000000..8ee556c
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	        $(call cmd_link_o_target, $(OBJS))
+	@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/matrix_vision/mvsmr/bootscript b/u-boot/board/matrix_vision/mvsmr/bootscript
new file mode 100644
index 0000000..02c802c
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/bootscript
@@ -0,0 +1,42 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
+setenv bootfromflash run flashkernel cpird addcons boot24
+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
+if test ${console} = yes;
+then
+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
+else
+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
+fi
+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
+setenv set_static_nm 'setenv netmask ${static_netmask}'
+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
+if test ${servicemode} != yes;
+then
+  echo "=== forced flash mode ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+fi
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip bootfromnet addcons boot24
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  echo "=== bootfromflash ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/u-boot/board/matrix_vision/mvsmr/fpga.c b/u-boot/board/matrix_vision/mvsmr/fpga.c
new file mode 100644
index 0000000..6320a69
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/fpga.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	0
+};
+
+Xilinx_desc spartan3 = {
+	Xilinx_Spartan2,
+	slave_serial,
+	XILINX_XC3S200_SIZE,
+	(void *) &fpga_fns,
+	0,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvsmr_init_fpga(void)
+{
+	fpga_init();
+	fpga_add(fpga_xilinx, &spartan3);
+
+	return 1;
+}
+
+int fpga_init_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
+		return 0;
+
+	return 1;
+}
+
+int fpga_done_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	int result = 0;
+
+	udelay(10);
+	if (in_be32(&gpio->simple_ival) & FPGA_DONE)
+		result = 1;
+
+	return result;
+}
+
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (!assert)
+		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+	else
+		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return assert;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_clk)
+		setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+
+	return assert_clk;
+}
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_write)
+		setbits_be32(&gpio->simple_dvo, FPGA_DIN);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
+
+	return assert_write;
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return 0;
+}
diff --git a/u-boot/board/matrix_vision/mvsmr/fpga.h b/u-boot/board/matrix_vision/mvsmr/fpga.h
new file mode 100644
index 0000000..ee690e6
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvsmr_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_pre_config_fn(int cookie);
diff --git a/u-boot/board/matrix_vision/mvsmr/mvsmr.c b/u-boot/board/matrix_vision/mvsmr/mvsmr.c
new file mode 100644
index 0000000..69655c4
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/mvsmr.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_DDR	1
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0xd3722930
+#define SDRAM_CONFIG2	0x46770000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start(int hi_addr)
+{
+	long hi_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
+		hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* set mode register: extended mode */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* auto refresh */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
+		hi_bit);
+
+	/* set mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1,
+	      test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+	/* setup config registers */
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	if (dramsize > 0)
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1);
+	else
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
+
+	return dramsize;
+}
+
+void mvsmr_init_gpio(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	printf("Ports : 0x%08x\n", gpio->port_config);
+	printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
+
+	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+	out_be32(&gpio->simple_ode, SIMPLE_ODE);
+	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+	out_8(&gpio->sint_ode, SINT_ODE);
+	out_8(&gpio->sint_ddr, SINT_DDR);
+	out_8(&gpio->sint_dvo, SINT_DVO);
+	out_8(&gpio->sint_inten, SINT_INTEN);
+	out_be16(&gpio->sint_itype, SINT_ITYPE);
+	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+	out_8(&wu_gpio->ode, WKUP_ODE);
+	out_8(&wu_gpio->ddr, WKUP_DIR);
+	out_8(&wu_gpio->dvo, WKUP_DO);
+	out_8(&wu_gpio->enable, WKUP_EN);
+
+	out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
+	out_be32(&timers->gpt1.emsr, 0x00000234);
+	out_be32(&timers->gpt2.emsr, 0x00000234);
+	out_be32(&timers->gpt3.emsr, 0x00000234);
+	out_be32(&timers->gpt4.emsr, 0x00000234);
+	out_be32(&timers->gpt5.emsr, 0x00000234);
+	out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
+	out_be32(&timers->gpt7.emsr, 0x00000024);
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		printf(" === FACTORY RESET ===\n");
+		mv_reset_environment();
+		saveenv();
+	}
+
+	return -1;
+}
+
+void mvsmr_get_dbg_present(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
+		setenv("dbg_present", "no\0");
+		setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
+	} else {
+		setenv("dbg_present", "yes\0");
+		setenv("bootstopkey", "s\0");
+		setbits_8(&psc->command, PSC_RX_ENABLE);
+	}
+}
+
+void mvsmr_get_service_mode(void)
+{
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & SERVICE_MODE)
+		setenv("servicemode", "no\0");
+	else
+		setenv("servicemode", "yes\0");
+}
+
+int mvsmr_get_mac(void)
+{
+	unsigned char mac[6];
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
+		setenv("lan_present", "no\0");
+		return -1;
+	} else
+		setenv("lan_present", "yes\0");
+
+	i2c_read(0x50, 0, 1, mac, 6);
+
+	eth_setenv_enetaddr("ethaddr", mac);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	mvsmr_init_gpio();
+	printf("Board: Matrix Vision mvSMR\n");
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+	out_be32((u32 *)MPC5XXX_BOOTCS_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_CS0_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+	out_be32((u32 *)MPC5XXX_CS0_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	mvsmr_get_dbg_present();
+	mvsmr_get_service_mode();
+	mvsmr_init_fpga();
+	mv_load_fpga();
+	pci_mpc5xxx_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (!mvsmr_get_mac())
+		return cpu_eth_init(bis);
+
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/matrix_vision/mvsmr/mvsmr.h b/u-boot/board/matrix_vision/mvsmr/mvsmr.h
new file mode 100644
index 0000000..b8320f1
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/mvsmr.h
@@ -0,0 +1,43 @@
+#include <pci.h>
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+#define FPGA_DIN	MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG	MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS	MPC5XXX_GPIO_SINT_PSC3_4
+#define S_FPGA_DIN	MPC5XXX_GPIO_SINT_PSC3_5
+#define S_FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_6
+#define S_FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_7
+#define S_FPGA_CONFIG	MPC5XXX_GPIO_SINT_PSC3_8
+#define S_FPGA_STATUS	MPC5XXX_GPIO_WKUP_PSC3_9
+
+#define MAN_RST		MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS		MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI		MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT	MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define SERVICE_MODE	MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY	MPC5XXX_GPIO_WKUP_7
+#define UART_EN1	MPC5XXX_GPIO_WKUP_PSC1_4
+#define LAN_PRSNT	MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define SIMPLE_DDR	(FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
+			 S_FPGA_CCLK)
+#define SIMPLE_DVO	(FPGA_CONFIG)
+#define SIMPLE_ODE	(FPGA_CONFIG)
+#define SIMPLE_GPIOEN	(FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
+			 S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
+
+#define SINT_ODE	0x1
+#define SINT_DDR	0x3
+#define SINT_DVO	0x1
+#define SINT_INTEN	0
+#define SINT_ITYPE	0
+#define SINT_GPIOEN	(FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
+
+#define WKUP_ODE	(MAN_RST | S_FPGA_STATUS)
+#define WKUP_DIR	(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_DO		(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_EN		(MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
+			 FLASH_RBY | UART_EN1 | LAN_PRSNT)
diff --git a/u-boot/board/matrix_vision/mvsmr/u-boot.lds b/u-boot/board/matrix_vision/mvsmr/u-boot.lds
new file mode 100644
index 0000000..074a482
--- /dev/null
+++ b/u-boot/board/matrix_vision/mvsmr/u-boot.lds
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010
+ * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the first two sectors (=8KB) of our S29GL flash chip */
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
+    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
+    board/matrix_vision/common/libmatrix_vision.o (.text*)
+
+    /* This is only needed to force failure if size of above code will ever */
+    /* increase and grow into reserved space. */
+    . = ALIGN(0x2000);	/* location counter has to be 0x4000 now */
+    . += 0x4000;	/* ->0x8000, i.e. move to env_offset */
+
+    . = env_offset;	/* ld error as soon as above ALIGN misplaces lc */
+    common/env_embedded.o        (.ppcenv)
+
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mbx8xx/Makefile b/u-boot/board/mbx8xx/Makefile
new file mode 100644
index 0000000..a98a017
--- /dev/null
+++ b/u-boot/board/mbx8xx/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o vpd.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mbx8xx/csr.h b/u-boot/board/mbx8xx/csr.h
new file mode 100644
index 0000000..d1a58b6
--- /dev/null
+++ b/u-boot/board/mbx8xx/csr.h
@@ -0,0 +1,60 @@
+#ifndef __csr_h
+#define __csr_h
+
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Control and Status Register definitions for the MBX
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* bits for control register #1 / status register #1 */
+#define CSR1_ETEN       0x80    /* Ethernet Transceiver Enabled             */
+#define CSR1_ELEN       0x40    /* Ethernet XCVR in Internal Loopback       */
+#define CSR1_EAEN       0x20    /* Auto selection TP/AUI Enabled            */
+#define CSR1_TPEN       0x10    /* TP manually selected                     */
+#define CSR1_FDDIS      0x08    /* Full Duplex Mode disabled                */
+#define CSR1_FCTEN      0x04    /* Collision Testing of XCVR disabled       */
+#define CSR1_COM1EN     0x02    /* COM1 signals routed to RS232 Transceiver */
+#define CSR1_XCVRDIS    0x01    /* Onboard RS232 Transceiver Disabled       */
+
+/* bits for control register #2 */
+#define CR2_VDDSEL      0xC0    /* PCMCIA Supply Voltage                    */
+#define CR2_VPPSEL      0x30    /* PCMCIA Programming Voltage               */
+#define CR2_BRDFAIL     0x08    /* Board fail                               */
+#define CR2_SWS1        0x04    /* Software Status #2 LED                   */
+#define CR2_SWS2        0x02    /* Software Status #2 LED                   */
+#define CR2_QSPANRST    0x01    /* Reset QSPAN                              */
+
+/* bits for status register #2 */
+#define SR2_VDDSEL      0xC0    /* PCMCIA Supply Voltage                    */
+#define SR2_VPPSEL      0x30    /* PCMCIA Programming Voltage               */
+#define SR2_BATGD       0x08    /* Low Voltage indication for onboard bat   */
+#define SR2_NVBATGD     0x04    /* Low Voltage indication for NVRAM         */
+#define SR2_RDY         0x02    /* Flash programming status bit             */
+#define SR2_FT          0x01    /* Reserved for Factory test purposes       */
+
+#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE))
+#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1))
+
+#endif /* __csr_h */
diff --git a/u-boot/board/mbx8xx/dimm.h b/u-boot/board/mbx8xx/dimm.h
new file mode 100644
index 0000000..b40f112
--- /dev/null
+++ b/u-boot/board/mbx8xx/dimm.h
@@ -0,0 +1,98 @@
+#ifndef __dimm_h
+#define __dimm_h
+
+/*
+ * Module name: %M%
+ * Description:
+ * Serial Presence Detect Definitions Module
+ * SCCS identification: %I%
+ * Branch: %B%
+ * Sequence: %S%
+ * Date newest applied delta was created (MM/DD/YY): %G%
+ * Time newest applied delta was created (HH:MM:SS): %U%
+ * SCCS file name %F%
+ * Fully qualified SCCS file name:
+ * %P%
+ * Copyright:
+ * (C) COPYRIGHT MOTOROLA, INC. 1996
+ * ALL RIGHTS RESERVED
+ * Notes:
+ * 1. All data was taken from an IBM application note titled
+ * "Serial Presence Detect Definitions".
+ * History:
+ * Date Who
+ *
+ * 10/24/96 Rob Baxter
+ * Initial release.
+ *
+ */
+
+/*
+ * serial PD byte assignment address map (256 byte EEPROM)
+ */
+typedef struct dimm
+{
+	uchar n_bytes; /* 00 number of bytes written/used */
+	uchar t_bytes; /* 01 total number of bytes in serial PD device */
+	uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */
+	uchar n_row; /* 03 number of rows */
+	uchar n_col; /* 04 number of columns */
+	uchar n_banks; /* 05 number of banks */
+	uchar data_w_lo; /* 06 data width */
+	uchar data_w_hi; /* 07 data width */
+	uchar ifl; /* 08 interface levels */
+	uchar a_ras; /* 09 RAS access */
+	uchar a_cas; /* 0A CAS access */
+	uchar ct; /* 0B configuration type (non-parity/parity/ECC) */
+	uchar refresh_rt; /* 0C refresh rate/type */
+	uchar p_dram_o; /* 0D primary DRAM organization */
+	uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */
+	uchar reserved[17]; /* 0F reserved fields for future offerings */
+	uchar ss_info[32]; /* 20 superset information (may be used in the future) */
+	uchar m_info[64]; /* 40 manufacturer information (optional) */
+	uchar unused[128]; /* 80 unused storage locations */
+} dimm_t;
+
+/*
+ * memory type definitions
+ */
+#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */
+#define DIMM_MT_EDO 2 /* EDO (extended data out) */
+#define DIMM_MT_PN 3 /* pipelined nibble */
+#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */
+
+/*
+ * row addresses definitions
+ */
+#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */
+#define DIMM_RA_MASK 0x7f /* number of row addresses mask */
+
+/*
+ * module interface levels definitions
+ */
+#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */
+#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */
+#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */
+#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */
+#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */
+
+/*
+ * DIMM configuration type definitions
+ */
+#define DIMM_CT_NONE 0 /* none */
+#define DIMM_CT_PARITY 1 /* parity */
+#define DIMM_CT_ECC 2 /* ECC */
+
+/*
+ * row addresses definitions
+ */
+#define DIMM_RRT_SR (1<<7) /* self refresh flag */
+#define DIMM_RRT_MASK 0x7f /* refresh rate mask */
+#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */
+#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */
+#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */
+#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */
+#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */
+#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */
+
+#endif /* __dimm_h */
diff --git a/u-boot/board/mbx8xx/flash.c b/u-boot/board/mbx8xx/flash.c
new file mode 100644
index 0000000..2ec420d
--- /dev/null
+++ b/u-boot/board/mbx8xx/flash.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AM290[48]0B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "vpd.h"
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size, totsize;
+    int i;
+    ulong addr;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    totsize = 0;
+    addr = 0xfc000000;
+    for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+	size = flash_get_size((vu_long *)addr, &flash_info[i]);
+	if (flash_info[i].flash_id == FLASH_UNKNOWN)
+	  break;
+	totsize += size;
+	addr += size;
+    }
+
+    addr = 0xfe000000;
+    for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+
+	size = flash_get_size((vu_long *)addr, &flash_info[i]);
+	if (flash_info[i].flash_id == FLASH_UNKNOWN)
+	  break;
+	totsize += size;
+	addr += size;
+    }
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+    /* monitor protection ON by default */
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+    return (totsize);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id >> 16) {
+    case 0x1:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F080B:
+	printf ("AM29F080B (8 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	  printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+
+    /* Write auto select command: read Manufacturer ID */
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x90909090;
+
+    vendor = addr[0];
+    devid = addr[1] & 0xff;
+
+    /* only support AMD */
+    if (vendor != 0x01010101) {
+	return 0;
+    }
+
+    vendor &= 0xf;
+    devid &= 0xff;
+
+    if (devid == AMD_ID_F040B) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 8;
+	info->size         = info->sector_count * 0x10000;
+    }
+    else if (devid == AMD_ID_F080B) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 16;
+	info->size         = 4 * info->sector_count * 0x10000;
+    }
+    else if (devid == AMD_ID_F016D) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 32;
+	info->size         = 4 * info->sector_count * 0x10000;
+    }
+    else {
+	printf ("## Unknown Flash Type: %08lx\n", devid);
+	return 0;
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr = (volatile unsigned long *)(info->start[i]);
+	info->protect[i] = addr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0;	/* reset bank */
+    }
+
+    return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0XAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x80808080;
+    addr[0x0555] = 0XAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while ((addr[0] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0xA0A0A0A0;
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/mbx8xx/mbx8xx.c b/u-boot/board/mbx8xx/mbx8xx.c
new file mode 100644
index 0000000..255796b
--- /dev/null
+++ b/u-boot/board/mbx8xx/mbx8xx.c
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Board specific routines for the MBX
+ *
+ * - initialisation
+ * - interface to VPD data (mac address, clock speeds)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+#include <net.h>
+#include "dimm.h"
+#include "vpd.h"
+#include "csr.h"
+
+/* ------------------------------------------------------------------------- */
+
+static const uint sdram_table_40[] = {
+	/* DRAM - single read. (offset 0 in upm RAM)
+	 */
+	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
+	0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst read. (offset 8 in upm RAM)
+	 */
+	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
+	0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
+	0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - single write. (offset 18 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst write. (offset 20 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* refresh  (offset 30 in upm RAM)
+	 */
+	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
+	0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* exception. (offset 3c in upm RAM)
+	 */
+	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
+};
+
+static const uint sdram_table_50[] = {
+	/* DRAM - single read. (offset 0 in upm RAM)
+	 */
+	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
+	0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst read. (offset 8 in upm RAM)
+	 */
+	0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
+  /*	0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04,	*/
+	0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
+	0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
+  /*	0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005,	*/
+	0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
+
+	/* DRAM - single write. (offset 18 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
+	0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst write. (offset 20 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* refresh  (offset 30 in upm RAM)
+	 */
+	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
+	0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* exception. (offset 3c in upm RAM)
+	 */
+	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
+};
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned int get_reffreq(void);
+static unsigned int board_get_cpufreq(void);
+
+void mbx_init (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	ulong speed, refclock, plprcr, sccr;
+	ulong br0_32 = memctl->memc_br0 & 0x400;
+
+	/* real-time clock status and control register */
+	immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
+	immr->im_sit.sit_rtcsc = 0x00C3;
+
+	/* SIEL and SIMASK Registers (see MBX PRG 2-3) */
+	immr->im_siu_conf.sc_simask = 0x00000000;
+	immr->im_siu_conf.sc_siel = 0xAAAA0000;
+	immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
+
+	/*
+	 * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
+	 * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
+	 * 2. RAM  Specs (see dimm.h)
+	 * 2. DIMM Specs (see dimm.h)
+	 */
+	vpd_init ();
+
+	/* system clock and reset control register */
+	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+	sccr = immr->im_clkrst.car_sccr;
+	sccr &= SCCR_MASK;
+	sccr |= CONFIG_SYS_SCCR;
+	immr->im_clkrst.car_sccr = sccr;
+
+	speed = board_get_cpufreq ();
+	refclock = get_reffreq ();
+
+#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
+	plprcr = CONFIG_SYS_PLPRCR;
+#else
+	plprcr = immr->im_clkrst.car_plprcr;
+	plprcr &= PLPRCR_MF_MSK;	/* isolate MF field */
+	plprcr |= CONFIG_SYS_PLPRCR;		/* reset control bits   */
+#endif
+
+#ifdef CONFIG_SYS_USE_OSCCLK			/* See doc/README.MBX ! */
+	plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
+#endif
+
+	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+	immr->im_clkrst.car_plprcr = plprcr;
+
+	/*
+	 * preliminary setup of memory controller:
+	 * - map Flash, otherwise configuration/status
+	 *    registers won't be accessible when read
+	 *    by board_init_f.
+	 * - map NVRAM and configuation/status registers.
+	 * - map pci registers.
+	 * - DON'T map ram yet, this is done in initdram().
+	 */
+	switch (speed / 1000000) {
+	case 40:
+		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
+		memctl->memc_or0 = 0xFF800930;
+		memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920;
+		memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
+		break;
+	case 50:
+		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
+		memctl->memc_or0 = 0xFF800940;
+		memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930;
+		memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
+		break;
+	default:
+		hang ();
+		break;
+	}
+#ifdef CONFIG_USE_PCI
+	memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR;
+	memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001;
+	memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR;
+	memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001;
+#endif
+	/*
+	 * FIXME: I do not understand why I have to call this to
+	 * initialise the control register here before booting from
+	 * the PCMCIA card but if I do not the Linux kernel falls
+	 * over in a big heap. If you can answer this question I
+	 * would like to know about it.
+	 */
+	board_ether_init();
+}
+
+void board_serial_init (void)
+{
+	MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS);
+}
+
+void board_ether_init (void)
+{
+	MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
+	MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
+}
+
+static unsigned int board_get_cpufreq (void)
+{
+#ifndef CONFIG_8xx_GCLK_FREQ
+	vpd_packet_t *packet;
+
+	packet = vpd_find_packet (VPD_PID_ICS);
+	return *((ulong *) packet->data);
+#else
+	return((unsigned int)CONFIG_8xx_GCLK_FREQ );
+#endif /* CONFIG_8xx_GCLK_FREQ */
+}
+
+static unsigned int get_reffreq (void)
+{
+	vpd_packet_t *packet;
+
+	packet = vpd_find_packet (VPD_PID_RCS);
+	return *((ulong *) packet->data);
+}
+
+static void board_get_enetaddr(uchar *addr)
+{
+	int i;
+	vpd_packet_t *packet;
+
+	packet = vpd_find_packet (VPD_PID_EA);
+	for (i = 0; i < 6; i++)
+		addr[i] = packet->data[i];
+}
+
+int misc_init_r(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	vpd_packet_t *packet;
+	int i;
+	const char *const fmt =
+		"\n	 *** Warning: Low Battery Status - %s Battery ***";
+
+	puts ("Board: ");
+
+	packet = vpd_find_packet (VPD_PID_PID);
+	for (i = 0; i < packet->size; i++) {
+		serial_putc (packet->data[i]);
+	}
+	packet = vpd_find_packet (VPD_PID_MT);
+	for (i = 0; i < packet->size; i++) {
+		serial_putc (packet->data[i]);
+	}
+	serial_putc ('(');
+	packet = vpd_find_packet (VPD_PID_FAN);
+	for (i = 0; i < packet->size; i++) {
+		serial_putc (packet->data[i]);
+	}
+	serial_putc (')');
+
+	if (!(MBX_CSR2 & SR2_BATGD))
+		printf (fmt, "On-Board");
+	if (!(MBX_CSR2 & SR2_NVBATGD))
+		printf (fmt, "NVRAM");
+
+	serial_putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static ulong get_ramsize (dimm_t * dimm)
+{
+	ulong size = 0;
+
+	if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3
+		|| dimm->fmt == 4) {
+		size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks *
+			((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8);
+	}
+
+	return size;
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long ram_sz = 0;
+	unsigned long dimm_sz = 0;
+	dimm_t vpd_dimm, vpd_dram;
+	unsigned int speed = board_get_cpufreq () / 1000000;
+
+	if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) {
+		dimm_sz = get_ramsize (&vpd_dimm);
+	}
+	if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) {
+		ram_sz = get_ramsize (&vpd_dram);
+	}
+
+	/*
+	 * Only initialize memory controller when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		ulong dimm_bank;
+		ulong br0_32 = memctl->memc_br0 & 0x400;
+
+		switch (speed) {
+		case 40:
+			upmconfig (UPMA, (uint *) sdram_table_40,
+					   sizeof (sdram_table_40) / sizeof (uint));
+			memctl->memc_mptpr = 0x0200;
+			memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
+			memctl->memc_or7 = 0xff800930;
+			memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
+			break;
+		case 50:
+			upmconfig (UPMA, (uint *) sdram_table_50,
+					   sizeof (sdram_table_50) / sizeof (uint));
+			memctl->memc_mptpr = 0x0200;
+			memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
+			memctl->memc_or7 = 0xff800940;
+			memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
+			break;
+		default:
+			hang ();
+			break;
+		}
+
+		/* now map ram and dimm, largest one first */
+		dimm_bank = dimm_sz / 2;
+		if (!dimm_sz) {
+			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+			memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
+			memctl->memc_br2 = 0;
+			memctl->memc_br3 = 0;
+		} else if (ram_sz > dimm_bank) {
+			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+			memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
+			memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81;
+			memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \
+								     | 0x81;
+		} else {
+			memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81;
+			memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81;
+			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+			memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81;
+		}
+	}
+
+	return ram_sz + dimm_sz;
+}
diff --git a/u-boot/board/mbx8xx/pcmcia.c b/u-boot/board/mbx8xx/pcmcia.c
new file mode 100644
index 0000000..e672d8c
--- /dev/null
+++ b/u-boot/board/mbx8xx/pcmcia.c
@@ -0,0 +1,162 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#include "csr.h"
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+/* A lot of this has been taken from the RPX code in this file it works from me.
+   I have added the voltage selection for the MBX board. */
+
+/* MBX voltage bit in control register #2 */
+#define CR2_VPP12       ((uchar)0x10)
+#define CR2_VPPVDD      ((uchar)0x20)
+#define CR2_VDD5        ((uchar)0x40)
+#define CR2_VDD3        ((uchar)0x80)
+
+#define PCMCIA_BOARD_MSG "MBX860"
+
+int pcmcia_voltage_set (int slot, int vcc, int vpp)
+{
+	uchar reg = 0;
+
+	debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	       'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
+
+	switch (vcc) {
+		case 0:
+			break;
+		case 33:
+			reg |= CR2_VDD3;
+			break;
+		case 50:
+			reg |= CR2_VDD5;
+			break;
+		default:
+			return 1;
+	}
+
+	switch (vpp) {
+		case 0:
+			break;
+		case 33:
+		case 50:
+			if (vcc == vpp) {
+				reg |= CR2_VPPVDD;
+			} else {
+				return 1;
+			}
+			break;
+		case 120:
+			reg |= CR2_VPP12;
+			break;
+		default:
+			return 1;
+	}
+
+	/* first, turn off all power */
+	MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
+
+	/* enable new powersettings */
+	MBX_CSR2 |= reg;
+	debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
+
+	return (0);
+}
+
+int pcmcia_hardware_enable (int slot)
+{
+	volatile immap_t *immap;
+	volatile cpm8xx_t *cp;
+	volatile pcmconf8xx_t *pcmp;
+	volatile sysconf8xx_t *sysp;
+	uint reg, mask;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
+	       'A' + slot);
+
+	udelay (10000);
+
+	immap = (immap_t *) CONFIG_SYS_IMMR;
+	sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
+	cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm));
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;	/* active low  */
+	PCMCIA_PGCRX (_slot_) = reg;
+	udelay (500);
+
+	/* remove all power */
+	pcmcia_voltage_set (slot, 0, 0);
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On.
+	*/
+	mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
+	reg = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
+	       (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
+	       (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
+
+	if ((reg & mask) == mask) {
+		pcmcia_voltage_set (_slot_, 50, 0);
+		printf (" 5.0V card found: ");
+	} else {
+		pcmcia_voltage_set (_slot_, 33, 0);
+		printf (" 3.3V card found: ");
+	}
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg = PCMCIA_PGCRX (_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;	/* active low  */
+	PCMCIA_PGCRX (_slot_) = reg;
+
+	udelay (250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+	}
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable (int slot)
+{
+	return 0;	/* No hardware to disable */
+}
+#endif
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/mbx8xx/u-boot.lds b/u-boot/board/mbx8xx/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/mbx8xx/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mbx8xx/u-boot.lds.debug b/u-boot/board/mbx8xx/u-boot.lds.debug
new file mode 100644
index 0000000..a7a67a9
--- /dev/null
+++ b/u-boot/board/mbx8xx/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mbx8xx/vpd.c b/u-boot/board/mbx8xx/vpd.c
new file mode 100644
index 0000000..1c99fd6
--- /dev/null
+++ b/u-boot/board/mbx8xx/vpd.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Code in faintly related to linux/arch/powerpc/8xx_io:
+ * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
+ *
+ * This file implements functions to read the MBX's Vital Product Data
+ * (VPD). I can't use the more general i2c code in mpc8xx/... since I need
+ * the VPD at a time where there is no RAM available yet. Hence the VPD is
+ * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD).
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef CONFIG_8xx
+#include <commproc.h>
+#endif
+#include "vpd.h"
+
+/* Location of receive/transmit buffer descriptors
+ * Allocate one transmit bd and one receive bd.
+ * IIC_BD_FREE points to free bd space which we'll use as tx buffer.
+ */
+#define IIC_BD_TX1     (BD_IIC_START + 0*sizeof(cbd_t))
+#define IIC_BD_TX2     (BD_IIC_START + 1*sizeof(cbd_t))
+#define IIC_BD_RX      (BD_IIC_START + 2*sizeof(cbd_t))
+#define IIC_BD_FREE    (BD_IIC_START + 3*sizeof(cbd_t))
+
+/* FIXME -- replace 0x2000 with offsetof */
+#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD))
+
+/* transmit/receive buffers */
+#define IIC_RX_LENGTH 128
+
+#define WITH_MICROCODE_PATCH
+
+vpd_packet_t * vpd_find_packet(u_char ident)
+{
+    vpd_packet_t *packet;
+    vpd_t *vpd = VPD_P;
+
+    packet = (vpd_packet_t *)&vpd->packets;
+    while ((packet->identifier != ident) && packet->identifier != 0xFF)
+    {
+	packet = (vpd_packet_t *)((char *)packet + packet->size + 2);
+    }
+    return packet;
+}
+
+void vpd_init(void)
+{
+    volatile immap_t  *im = (immap_t *)CONFIG_SYS_IMMR;
+    volatile cpm8xx_t *cp = &(im->im_cpm);
+    volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
+    volatile iic_t *iip;
+#ifdef WITH_MICROCODE_PATCH
+    ulong reloc = 0;
+#endif
+
+    iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+
+    /*
+     * kludge: when running from flash, no microcode patch can be
+     * installed. However, the DPMEM usually contains non-zero
+     * garbage at the relocatable patch base location, so lets clear
+     * it now. This way the rest of the code can support the microcode
+     * patch dynamically.
+     */
+    if ((ulong)vpd_init & 0xff000000)
+      iip->iic_rpbase = 0;
+
+#ifdef WITH_MICROCODE_PATCH
+    /* Check for and use a microcode relocation patch. */
+    if ((reloc = iip->iic_rpbase))
+      iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
+#endif
+    /* Initialize Port B IIC pins */
+    cp->cp_pbpar |= 0x00000030;
+    cp->cp_pbdir |= 0x00000030;
+    cp->cp_pbodr |= 0x00000030;
+
+    i2c->i2c_i2mod = 0x04;  /* filter clock */
+    i2c->i2c_i2add = 0x34;	/* select an arbitrary (unique) address */
+    i2c->i2c_i2brg = 0x07;  /* make clock run maximum slow	*/
+    i2c->i2c_i2cmr = 0x00;  /* disable interrupts */
+    i2c->i2c_i2cer = 0x1f;  /* clear events */
+    i2c->i2c_i2com = 0x01;  /* configure i2c to work as master */
+
+    if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE)
+    {
+	hang();
+    }
+}
+
+
+/* Read from I2C.
+ * This is a two step process.  First, we send the "dummy" write
+ * to set the device offset for the read.  Second, we perform
+ * the read operation.
+ */
+int vpd_read(uint iic_device, uchar *buf, int count, int offset)
+{
+    volatile immap_t  *im = (immap_t *)CONFIG_SYS_IMMR;
+    volatile cpm8xx_t *cp = &(im->im_cpm);
+    volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
+    volatile iic_t *iip;
+    volatile cbd_t *tbdf1, *tbdf2, *rbdf;
+    uchar *tb;
+    uchar event;
+#ifdef WITH_MICROCODE_PATCH
+    ulong reloc = 0;
+#endif
+
+    iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+#ifdef WITH_MICROCODE_PATCH
+    /* Check for and use a microcode relocation patch. */
+    if ((reloc = iip->iic_rpbase))
+      iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
+#endif
+    tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1];
+    tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2];
+    rbdf  = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX];
+
+    /* Send a "dummy write" operation.  This is a write request with
+     * only the offset sent, followed by another start condition.
+     * This will ensure we start reading from the first location
+     * of the EEPROM.
+     */
+    tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE];
+    tb[0] = iic_device & 0xfe;	/* device address */
+    tb[1] = offset;	        /* offset */
+    tbdf1->cbd_bufaddr = (uint)tb;
+    tbdf1->cbd_datlen = 2;
+    tbdf1->cbd_sc = 0x8400;
+
+    tb += 2;
+    tb[0] = iic_device | 1;	/* device address */
+    tbdf2->cbd_bufaddr = (uint)tb;
+    tbdf2->cbd_datlen = count+1;
+    tbdf2->cbd_sc = 0xbc00;
+
+    rbdf->cbd_bufaddr = (uint)buf;
+    rbdf->cbd_datlen = 0;
+    rbdf->cbd_sc = 0xb000;
+
+    iip->iic_tbase = IIC_BD_TX1;
+    iip->iic_tbptr = IIC_BD_TX1;
+    iip->iic_rbase = IIC_BD_RX;
+    iip->iic_rbptr = IIC_BD_RX;
+    iip->iic_rfcr = 0x15;
+    iip->iic_tfcr = 0x15;
+    iip->iic_mrblr = count;
+    iip->iic_rstate = 0;
+    iip->iic_tstate = 0;
+
+    i2c->i2c_i2cer = 0x1f;  /* clear event mask */
+    i2c->i2c_i2mod |= 1;    /* enable iic operation */
+    i2c->i2c_i2com |= 0x80;	/* start master */
+
+    /* wait for IIC transfer */
+    do {
+	__asm__ volatile ("eieio");
+	event = i2c->i2c_i2cer;
+    } while (event == 0);
+
+    if ((event & 0x10) || (event & 0x04)) {
+	count = -1;
+	goto bailout;
+    }
+
+bailout:
+    i2c->i2c_i2mod &= ~1;   /* turn off iic operation */
+    i2c->i2c_i2cer = 0x1f;  /* clear event mask */
+
+    return count;
+}
diff --git a/u-boot/board/mbx8xx/vpd.h b/u-boot/board/mbx8xx/vpd.h
new file mode 100644
index 0000000..1d9eb7f
--- /dev/null
+++ b/u-boot/board/mbx8xx/vpd.h
@@ -0,0 +1,119 @@
+#ifndef __vpd_h
+#define __vpd_h
+
+/*
+ * Module name: %M%
+ * Description:
+ * Vital Product Data (VPD) Header Module
+ * SCCS identification: %I%
+ * Branch: %B%
+ * Sequence: %S%
+ * Date newest applied delta was created (MM/DD/YY): %G%
+ * Time newest applied delta was created (HH:MM:SS): %U%
+ * SCCS file name %F%
+ * Fully qualified SCCS file name:
+ * %P%
+ * Copyright:
+ * (C) COPYRIGHT MOTOROLA, INC. 1996
+ * ALL RIGHTS RESERVED
+ * Notes:
+ * History:
+ * Date Who
+ *
+ * 10/24/96 Rob Baxter
+ * Initial release.
+ *
+ */
+
+#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */
+
+/*
+ * packet tuple identifiers
+ *
+ * 0x0D - 0xBF reserved
+ * 0xC0 - 0xFE user defined
+ */
+#define VPD_PID_GI   0x00 /* guaranteed illegal */
+#define VPD_PID_PID  0x01 /* product identifier (ASCII) */
+#define VPD_PID_FAN  0x02 /* factory assembly-number (ASCII) */
+#define VPD_PID_SN   0x03 /* serial-number (ASCII) */
+#define VPD_PID_PCO  0x04 /* product configuration options(binary) */
+#define VPD_PID_ICS  0x05 /* internal clock speed in HZ (integer) */
+#define VPD_PID_ECS  0x06 /* external clock speed in HZ (integer) */
+#define VPD_PID_RCS  0x07 /* reference clock speed in HZ(integer) */
+#define VPD_PID_EA   0x08 /* ethernet address (binary) */
+#define VPD_PID_MT   0x09 /* microprocessor type (ASCII) */
+#define VPD_PID_CRC  0x0A /* EEPROM CRC (integer) */
+#define VPD_PID_FMC  0x0B /* FLASH memory configuration (binary) */
+#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */
+#define VPD_PID_TERM 0xFF /* termination */
+
+/*
+ * VPD structure (format)
+ */
+#define VPD_EYE_SIZE 8 /* eyecatcher size */
+typedef struct vpd_header
+{
+	uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */
+	ushort size; /* size of EEPROM */
+} vpd_header_t;
+
+#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t))
+typedef struct vpd
+{
+	vpd_header_t header; /* header */
+	uchar packets[VPD_DATA_SIZE]; /* data */
+} vpd_t;
+
+/*
+ * packet tuple structure (format)
+ */
+typedef struct vpd_packet
+{
+    uchar identifier; /* identifier (PIDs above) */
+    uchar size;       /* size of the following data area */
+    uchar data[1];    /* data (size is dependent upon PID) */
+} vpd_packet_t;
+
+/*
+ * MBX product configuration options bit definitions
+ *
+ * Notes:
+ * 1. The bit numbering is reversed in perspective with the C compiler.
+ */
+#define PCO_BBRAM    (1<<0)  /* battery-backed RAM (BBRAM) and socket */
+#define PCO_BOOTROM  (1<<1)  /* boot ROM and socket (i.e., socketed FLASH) */
+#define PCO_KAPWR    (1<<2)  /* keep alive power source (lithium battey) and control circuit */
+#define PCO_ENET_TP  (1<<3)  /* ethernet twisted pair (TP) connector (RJ45) */
+#define PCO_ENET_AUI (1<<4)  /* ethernet attachment unit interface (AUI) header */
+#define PCO_PCMCIA   (1<<5)  /* PCMCIA socket */
+#define PCO_DIMM     (1<<6)  /* DIMM module socket */
+#define PCO_DTT      (1<<7)  /* digital thermometer and thermostat (DTT) device */
+#define PCO_LCD      (1<<8)  /* liquid crystal display (LCD) device */
+#define PCO_PCI      (1<<9)  /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */
+#define PCO_PCIO     (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */
+#define PCO_EIDE     (1<<11) /* enhanced IDE (EIDE) header */
+#define PCO_FDC      (1<<12) /* floppy disk controller (FDC) header */
+#define PCO_LPT_8XX  (1<<13) /* parallel port header via MPC8xx */
+#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */
+
+/*
+ * FLASH memory configuration packet data
+ */
+typedef struct vpd_fmc
+{
+    ushort mid; /* manufacturer's idenitfier */
+    ushort did; /* manufacturer's device idenitfier */
+    uchar ddw;  /* device data width (e.g., 8-bits, 16-bits) */
+    uchar nod;  /* number of devices present */
+    uchar noc;  /* number of columns */
+    uchar cw;   /* column width in bits */
+    uchar wedw; /* write/erase data width */
+} vpd_fmc_t;
+
+/* function prototypes */
+extern void vpd_init(void);
+extern int  vpd_read(uint iic_device, uchar *buf, int count, int offset);
+extern      vpd_packet_t *vpd_find_packet(u_char ident);
+
+#endif /* __vpd_h */
diff --git a/u-boot/board/mcc200/Makefile b/u-boot/board/mcc200/Makefile
new file mode 100644
index 0000000..e0a24b1
--- /dev/null
+++ b/u-boot/board/mcc200/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o lcd.o auto_update.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mcc200/auto_update.c b/u-boot/board/mcc200/auto_update.c
new file mode 100644
index 0000000..49213d0
--- /dev/null
+++ b/u-boot/board/mcc200/auto_update.c
@@ -0,0 +1,544 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <part.h>
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+#include <hush.h>
+#endif
+
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CONFIG_SYS_HUSH_PARSER
+#error "must define CONFIG_SYS_HUSH_PARSER"
+#endif
+
+#if !defined(CONFIG_CMD_FAT)
+#error "must define CONFIG_CMD_FAT"
+#endif
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_FIRMWARE	"u-boot.img"
+#define AU_KERNEL	"kernel.img"
+#define AU_ROOTFS	"rootfs.img"
+
+struct flash_layout {
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#define AU_FL_FIRMWARE_ST	0xfC000000
+#define AU_FL_FIRMWARE_ND	0xfC03FFFF
+#define AU_FL_KERNEL_ST		0xfC0C0000
+#define AU_FL_KERNEL_ND		0xfC1BFFFF
+#define AU_FL_ROOTFS_ST		0xFC1C0000
+#define AU_FL_ROOTFS_ND		0xFCFBFFFF
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_FIRMWARE	0
+#define IDX_KERNEL	1
+#define IDX_ROOTFS	2
+
+/* max. number of files which could interest us */
+#define AU_MAXFILES 3
+
+/* pointers to file names */
+char *aufile[AU_MAXFILES] = {
+	AU_FIRMWARE,
+	AU_KERNEL,
+	AU_ROOTFS
+};
+
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES] = {
+	(AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST,
+	(AU_FL_KERNEL_ND   + 1) - AU_FL_KERNEL_ST,
+	(AU_FL_ROOTFS_ND   + 1) - AU_FL_ROOTFS_ST,
+};
+
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES] = {
+	{ AU_FL_FIRMWARE_ST,	AU_FL_FIRMWARE_ND, },
+	{ AU_FL_KERNEL_ST,	AU_FL_KERNEL_ND,   },
+	{ AU_FL_ROOTFS_ST,	AU_FL_ROOTFS_ND,   },
+};
+
+ulong totsize;
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x00200000)
+
+/* the root file system is the largest image */
+#define MAX_LOADSZ ausize[IDX_ROOTFS]
+
+/*i2c address of the keypad status*/
+#define I2C_PSOC_KEYPAD_ADDR	0x53
+
+/* keypad mask */
+#define KEYPAD_ROW	2
+#define KEYPAD_COL	2
+#define KEYPAD_MASK_LO	((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF)
+#define KEYPAD_MASK_HI	((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8)
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+extern int u_boot_hush_start(void);
+#ifdef CONFIG_PROGRESSBAR
+extern void show_progress(int, int);
+extern void lcd_puts (char *);
+extern void lcd_enable(void);
+#endif
+
+int au_check_cksum_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	if (nbytes != image_get_image_size (hdr)) {
+		printf ("Image %s bad total SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the data CRC */
+	if (!image_check_dcrc (hdr)) {
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int au_check_header_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum, fsize;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC);
+	printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM);
+	printf("size %#x %#lx ", image_get_data_size (hdr), nbytes);
+	printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL);
+#endif
+	if (nbytes < image_get_header_size ()) {
+		printf ("Image %s bad header SIZE\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
+		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* check the hdr CRC */
+	if (!image_check_hcrc (hdr)) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	if ((idx == IDX_ROOTFS) &&
+			(!image_check_type (hdr, IH_TYPE_RAMDISK) &&
+			!image_check_type (hdr, IH_TYPE_FILESYSTEM))) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* recycle checksum */
+	checksum = image_get_data_size (hdr);
+
+	fsize = checksum + image_get_header_size ();
+	/* for kernel and ramdisk the image header must also fit into flash */
+	if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK))
+		checksum += image_get_header_size ();
+
+	/* check the size does not exceed space in flash. HUSH scripts */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* Update with the real filesize */
+	ausize[idx] = fsize;
+
+	return checksum; /* return size to be written to flash */
+}
+
+int au_do_update(int idx, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* execute a script */
+	if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
+		addr = (char *)((char *)hdr + image_get_header_size ());
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[image_get_data_size (hdr)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		return 0;
+	}
+
+	start = aufl_layout[idx].start;
+	end = aufl_layout[idx].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		flash_sect_protect(0, start, end);
+	}
+
+	/*
+	 * erase the address range.
+	 */
+	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+	flash_sect_erase(start, end);
+	wait_ms(100);
+#ifdef CONFIG_PROGRESSBAR
+	show_progress(end - start, totsize);
+#endif
+
+	/* strip the header - except for the kernel and ramdisk */
+	if (image_check_type (hdr, IH_TYPE_KERNEL) ||
+			image_check_type (hdr, IH_TYPE_RAMDISK)) {
+		addr = (char *)hdr;
+		off = image_get_header_size ();
+		nbytes = image_get_image_size (hdr);
+	} else {
+		addr = (char *)((char *)hdr + image_get_header_size ());
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = image_get_data_size (hdr);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+	rc = flash_write(addr, start, nbytes);
+	if (rc != 0) {
+		printf("Flashing failed due to error %d\n", rc);
+		return -1;
+	}
+
+#ifdef CONFIG_PROGRESSBAR
+	show_progress(nbytes, totsize);
+#endif
+
+	/* check the data CRC of the copy */
+	if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) !=
+	    image_get_dcrc (hdr)) {
+		printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE)
+		flash_sect_protect(1, start, end);
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+
+#if 0 /* disable key-press detection to speed up boot-up time */
+	uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
+
+	/*
+	 * Read keypad status
+	 */
+	i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
+	wait_ms(500);
+	i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
+
+	/*
+	 * Check keypad
+	 */
+	if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
+	      (keypad_status1[1] != keypad_status2[1])) {
+		return 0;
+	}
+
+#endif
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(0);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		res = -1;
+		goto xit;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		res = -1;
+		goto xit;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		res = -1;
+		goto xit;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = -1;
+	end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+		aufl_layout[IDX_FIRMWARE].start = start;
+		aufl_layout[IDX_FIRMWARE].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_KERNEL] = (end + 1) - start;
+		aufl_layout[IDX_KERNEL].start = start;
+		aufl_layout[IDX_KERNEL].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("rootfs_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("rootfs_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_ROOTFS] = (end + 1) - start;
+		aufl_layout[IDX_ROOTFS].start = start;
+		aufl_layout[IDX_ROOTFS].end = end;
+	}
+
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+
+	/* validate the images first */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		ulong imsize;
+		/* just read the header */
+		sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ());
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, image_get_header_size ());
+		if (sz <= 0 || sz < image_get_header_size ()) {
+			debug ("%s not found\n", aufile[i]);
+			ausize[i] = 0;
+			continue;
+		}
+		/* au_check_header_valid() updates ausize[] */
+		if ((imsize = au_check_header_valid(i, sz)) < 0) {
+			debug ("%s header not valid\n", aufile[i]);
+			continue;
+		}
+		/* totsize accounts for image size and flash erase size */
+		totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start));
+	}
+
+#ifdef CONFIG_PROGRESSBAR
+	if (totsize) {
+		lcd_puts(" Update in progress\n");
+		lcd_enable();
+	}
+#endif
+
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES && totsize; i++) {
+		if (!ausize[i]) {
+			continue;
+		}
+		sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]);
+
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, image_get_header_size ());
+
+		if (sz != ausize[i]) {
+			printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz);
+			continue;
+		}
+
+		if (sz <= 0 || sz <= image_get_header_size ()) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			debug ("%s checksum not valid\n", aufile[i]);
+			continue;
+		}
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < (AU_MAXFILES + 1));
+		if (cnt < (AU_MAXFILES + 1))
+#else
+		} while (res < 0);
+#endif
+	}
+
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+#ifdef CONFIG_PROGRESSBAR
+	if (totsize) {
+		if (!res) {
+			lcd_puts("\n  Update completed\n");
+		} else {
+			lcd_puts("\n   Update error\n");
+		}
+		lcd_enable();
+	}
+#endif
+ xit:
+	usb_stop();
+	return res;
+}
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/u-boot/board/mcc200/lcd.c b/u-boot/board/mcc200/lcd.c
new file mode 100644
index 0000000..726366d
--- /dev/null
+++ b/u-boot/board/mcc200/lcd.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <mpc5xxx.h>
+
+#ifdef CONFIG_LCD
+
+#undef SWAPPED_LCD /* For the previous h/w version */
+/*
+ *  The name of the device used for communication
+ * with the PSoC.
+ */
+#define PSOC_PSC	MPC5XXX_PSC2
+#define PSOC_BAUD	230400UL
+
+#define RTS_ASSERT	1
+#define RTS_NEGATE	0
+#define CTS_ASSERT	1
+#define CTS_NEGATE	0
+
+/*
+ * Dimensions in pixels
+ */
+#define LCD_WIDTH	160
+#define LCD_HEIGHT	100
+
+/*
+ * Dimensions in bytes
+ */
+#define LCD_BUF_SIZE	((LCD_WIDTH*LCD_HEIGHT)>>3)
+
+#if LCD_BPP != LCD_MONOCHROME
+#error "MCC200 support only monochrome displays (1 bpp)!"
+#endif
+
+#define PSOC_RETRIES	10	/* each of PSOC_WAIT_TIME */
+#define PSOC_WAIT_TIME	10	/* usec */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * LCD information
+ */
+vidinfo_t panel_info = {
+	LCD_WIDTH, LCD_HEIGHT, LCD_BPP
+};
+
+int lcd_line_length;
+
+int lcd_color_fg;
+int lcd_color_bg;
+
+/*
+ * Frame buffer memory information
+ */
+void *lcd_base;			/* Start of framebuffer memory  */
+void *lcd_console_address;	/* Start of console buffer      */
+
+short console_col = 0;
+short console_row = 0;
+
+/*
+ *  The device we use to communicate with PSoC
+ */
+int serial_inited = 0;
+
+/*
+ * Exported functions
+ */
+void lcd_initcolregs (void);
+void lcd_ctrl_init (void *lcdbase);
+void lcd_enable (void);
+
+/*
+ *  Imported functions to support the PSoC protocol
+ */
+extern int serial_init_dev (unsigned long dev_base);
+extern void serial_setrts_dev (unsigned long dev_base, int s);
+extern int serial_getcts_dev (unsigned long dev_base);
+extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
+
+/*
+ *  Just stubs for our driver, needed for compiling compabilty with
+ * the common LCD driver code.
+ */
+void lcd_initcolregs (void)
+{
+}
+
+void lcd_ctrl_init (void *lcdbase)
+{
+}
+
+/*
+ * Function sends the contents of the frame-buffer to the LCD
+ */
+void lcd_enable (void)
+{
+	int i, retries, fb_size;
+
+	if (!serial_inited) {
+		unsigned long baud;
+
+		baud = gd->baudrate;
+		gd->baudrate = PSOC_BAUD;
+		serial_init_dev(PSOC_PSC);
+		gd->baudrate = baud;
+		serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+		serial_inited = 1;
+	}
+
+	/*
+	 *  Implement PSoC communication protocol:
+	 * 1. Assert RTS, wait CTS assertion
+	 * 2. Transmit data
+	 * 3. Negate RTS, wait CTS negation
+	 */
+
+	/* 1 */
+	serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+	for (retries = PSOC_RETRIES; retries; retries--) {
+		if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
+			break;
+		udelay (PSOC_WAIT_TIME);
+	}
+	if (!retries) {
+		printf ("%s Error: PSoC doesn't respond on "
+			"RTS ASSERT\n",	__FUNCTION__);
+	}
+
+	/* 2 */
+	fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
+
+#if !defined(SWAPPED_LCD)
+	for (i=0; i<fb_size; i++) {
+		serial_putc_raw_dev (PSOC_PSC, ((char *)lcd_base)[i]);
+	}
+#else
+    {
+	int x, y, pwidth;
+	char *p = (char *)lcd_base;
+
+	pwidth = ((panel_info.vl_col+7) >> 3);
+	for (y=0; y<panel_info.vl_row; y++) {
+		i = y * pwidth;
+		for (x=0; x<pwidth; x+=5) {
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
+		}
+	}
+    }
+#endif
+
+	/* 3 */
+	serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
+	for (retries = PSOC_RETRIES; retries; retries--) {
+		if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
+			break;
+		udelay (PSOC_WAIT_TIME);
+	}
+
+	return;
+}
+#ifdef CONFIG_PROGRESSBAR
+
+#define FONT_WIDTH      8 /* the same as VIDEO_FONT_WIDTH in video_font.h */
+void show_progress (int size, int tot)
+{
+	int cnt;
+	int i;
+	static int rc = 0;
+
+	rc += size;
+
+	cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot;
+
+	rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH);
+
+	for (i = 0; i < cnt; i++) {
+		lcd_putc(0xdc);
+	}
+
+	if (cnt) {
+		lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */
+	}
+}
+
+#endif
+#endif /* CONFIG_LCD */
diff --git a/u-boot/board/mcc200/mcc200.c b/u-boot/board/mcc200/mcc200.c
new file mode 100644
index 0000000..9fa1d3a
--- /dev/null
+++ b/u-boot/board/mcc200/mcc200.c
@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+
+/* Two MT48LC8M32B2 for 32 MB */
+/* #include "mt48lc8m32b2-6-7.h" */
+
+/* One MT48LC16M32S2 for 64 MB */
+/* #include "mt48lc16m32s2-75.h" */
+#if defined (CONFIG_MCC200_SDRAM)
+#include "mt48lc16m16a2-75.h"
+#else
+#include "mt46v16m16-75.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
+extern int do_auto_update(void);
+ulong flash_get_size (ulong base, int banknum);
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	udelay(10);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_PRS200)
+	puts ("Board: PRS200\n");
+#else
+	puts ("Board: MCC200\n");
+#endif
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	ulong flash_sup_end, snum;
+
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if boot FLASH isn't max size
+	 */
+	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
+		/* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(gd->bd->bi_flashstart);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
+
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
+
+		/*
+		 * Re-do flash protection upon new addresses
+		 */
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       gd->bd->bi_flashstart, 0xffffffff,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR,
+			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Redundant environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR_REDUND,
+			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+	}
+
+	if (gd->bd->bi_flashsize > (32 << 20)) {
+		/* Unprotect the upper bank of the Flash */
+		*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       flash_info[0].start[0] + flash_info[0].size / 2,
+			       (flash_info[0].start[0] - 1) + flash_info[0].size,
+			       &flash_info[0]);
+		*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
+		printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
+		flash_info[0].size = 32 << 20;
+		for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
+			flash_info[0].start[snum] < flash_sup_end;
+			snum++);
+		flash_info[0].sector_count = snum;
+	}
+
+#ifdef CONFIG_AUTO_UPDATE
+	do_auto_update();
+#endif
+	return (0);
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+}
+#endif
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
diff --git a/u-boot/board/mcc200/mt46v16m16-75.h b/u-boot/board/mcc200/mt46v16m16-75.h
new file mode 100644
index 0000000..423febe
--- /dev/null
+++ b/u-boot/board/mcc200/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/mcc200/mt48lc16m16a2-75.h b/u-boot/board/mcc200/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/mcc200/mt48lc16m16a2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/mcc200/mt48lc16m32s2-75.h b/u-boot/board/mcc200/mt48lc16m32s2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/mcc200/mt48lc16m32s2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/mcc200/mt48lc8m32b2-6-7.h b/u-boot/board/mcc200/mt48lc8m32b2-6-7.h
new file mode 100644
index 0000000..13aebbd
--- /dev/null
+++ b/u-boot/board/mcc200/mt48lc8m32b2-6-7.h
@@ -0,0 +1,12 @@
+/*
+ * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE	0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
+#define SDRAM_CONTROL	0x504f0000 /* Control Register MBAR + 0x0104 */
+#define SDRAM_CONFIG1	0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
+#define SDRAM_CONFIG2	0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
diff --git a/u-boot/board/mercury/mpq101/Makefile b/u-boot/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/u-boot/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mercury/mpq101/law.c b/u-boot/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..0e23a6a
--- /dev/null
+++ b/u-boot/board/mercury/mpq101/law.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/mercury/mpq101/mpq101.c b/u-boot/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..e02e87f
--- /dev/null
+++ b/u-boot/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/u-boot/board/mercury/mpq101/tlb.c b/u-boot/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..fd2eaec
--- /dev/null
+++ b/u-boot/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/mercury/mpq101/u-boot.lds b/u-boot/board/mercury/mpq101/u-boot.lds
new file mode 100644
index 0000000..4f4dda5
--- /dev/null
+++ b/u-boot/board/mercury/mpq101/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { common/env_embedded.o (.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/micronas/vct/Makefile b/u-boot/board/micronas/vct/Makefile
new file mode 100644
index 0000000..a7748fe
--- /dev/null
+++ b/u-boot/board/micronas/vct/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+COBJS-y += ebi.o
+COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
+COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
+COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
+COBJS-y += gpio.o
+COBJS-y += top.o
+COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/micronas/vct/bcu.h b/u-boot/board/micronas/vct/bcu.h
new file mode 100644
index 0000000..cac31f2
--- /dev/null
+++ b/u-boot/board/micronas/vct/bcu.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BCU_H
+#define _BCU_H
+
+enum bcu_tags {
+	BCU_VBV1		= 0,
+	BCU_VBV2		= 1,
+	BCU_BSS1		= 2,
+	BCU_BSS2		= 3,
+	BCU_TSD_TXT		= 4,
+	BCU_TSD_SUBTITLES	= 5,
+	BCU_TSD_PES_0		= 6,
+	BCU_TSD_PES_1		= 7,
+	BCU_TSD_PES_2		= 8,
+	BCU_TSD_PES_3		= 9,
+	BCU_TSIO_RECORD_0	= 10,
+	BCU_TSIO_RECORD_1	= 11,
+	BCU_TSIO_PLAYBACK_0	= 12,
+	BCU_TSIO_PLAYBACK_1	= 13,
+	BCU_SECURE_BUFFER	= 14,
+	BCU_PCM1		= 15,
+	BCU_PCM2		= 16,
+	BCU_BSS_COPY		= 17,
+	BCU_BSS_EXT1		= 18,
+	BCU_BSS_EXT2		= 19,
+	BCU_PCM_JINGLE		= 20,
+	BCU_EBI_CPU_BUFFER	= 21,
+	BCU_PCM_DELAY		= 22,
+	BCU_FH_BUFFER_0		= 23,
+	BCU_FH_BUFFER_1		= 24,
+	BCU_TSD_SECTION_0	= 25,
+	BCU_TSD_SECTION_1	= 26,
+	BCU_TSD_SECTION_2	= 27,
+	BCU_TSD_SECTION_3	= 28,
+	BCU_TSD_SECTION_4	= 29,
+	BCU_TSD_SECTION_5	= 30,
+	BCU_TSD_SECTION_6	= 31,
+	BCU_TSD_SECTION_7	= 32,
+	BCU_TSD_SECTION_8	= 33,
+	BCU_TSD_SECTION_9	= 34,
+	BCU_TSD_SECTION_10	= 35,
+	BCU_TSD_SECTION_11	= 36,
+	BCU_TSD_SECTION_12	= 37,
+	BCU_TSD_SECTION_13	= 38,
+	BCU_TSD_SECTION_14	= 39,
+	BCU_TSD_SECTION_15	= 40,
+	BCU_TSD_SECTION_16	= 41,
+	BCU_TSD_SECTION_17	= 42,
+	BCU_TSD_SECTION_18	= 43,
+	BCU_TSD_SECTION_19	= 44,
+	BCU_TSD_SECTION_20	= 45,
+	BCU_TSD_SECTION_21	= 46,
+	BCU_TSD_SECTION_22	= 47,
+	BCU_TSD_SECTION_23	= 48,
+	BCU_TSD_SECTION_24	= 49,
+	BCU_TSD_SECTION_25	= 50,
+	BCU_TSD_SECTION_26	= 51,
+	BCU_TSD_SECTION_27	= 52,
+	BCU_TSD_SECTION_28	= 53,
+	BCU_TSD_SECTION_29	= 54,
+	BCU_TSD_SECTION_30	= 55,
+	BCU_TSD_SECTION_31	= 56,
+	BCU_TSD_SECTION_32	= 57,
+	BCU_TSD_SECTION_33	= 58,
+	BCU_TSD_SECTION_34	= 59,
+	BCU_TSD_SECTION_35	= 60,
+	BCU_TSD_SECTION_36	= 61,
+	BCU_TSD_SECTION_37	= 62,
+	BCU_TSD_SECTION_38	= 63,
+	BCU_TSD_SECTION_39	= 64,
+	BCU_TSD_SECTION_40	= 65,
+	BCU_TSD_SECTION_41	= 66,
+	BCU_TSD_SECTION_42	= 67,
+	BCU_TSD_SECTION_43	= 68,
+	BCU_TSD_SECTION_44	= 69,
+	BCU_TSD_SECTION_45	= 70,
+	BCU_TSD_SECTION_46	= 71,
+	BCU_TSD_SECTION_47	= 72,
+	BCU_TSD_SECTION_48	= 73,
+	BCU_TSD_SECTION_49	= 74,
+	BCU_TSD_SECTION_50	= 75,
+	BCU_TSD_SECTION_51	= 76,
+	BCU_TSD_SECTION_52	= 77,
+	BCU_TSD_SECTION_53	= 78,
+	BCU_TSIO_RECORD_2	= 79,
+	BCU_TSIO_RECORD_3	= 80,
+	BCU_TSIO_RECORD_4	= 81,
+	BCU_TSIO_RECORD_5	= 82,
+	BCU_TSIO_RECORD_6	= 83,
+	BCU_TSIO_RECORD_7	= 84,
+	BCU_TSIO_RECORD_8	= 85,
+	BCU_TSIO_RECORD_9	= 86,
+	BCU_PCM_DELAY_LINEAR	= 87,
+	BCU_VD_MASTER_USER_DATA	= 88,
+	BCU_VD_SLAVE_USER_DATA	= 89,
+	BCU_VD_MASTER_REF0	= 90,
+	BCU_VD_MASTER_REF1	= 91,
+	BCU_VD_SLAVE_REF0	= 92,
+	BCU_VD_SLAVE_REF1	= 93,
+	BCU_VD_MASTER_DISP0_Y	= 94,
+	BCU_VD_MASTER_DISP1_Y	= 95,
+	BCU_VD_MASTER_DISP2_Y	= 96,
+	BCU_VD_MASTER_DISP0_C	= 97,
+	BCU_VD_MASTER_DISP1_C	= 98,
+	BCU_VD_MASTER_DISP2_C	= 99,
+	BCU_VD_SLAVE_DISP0_Y	= 100,
+	BCU_VD_SLAVE_DISP1_Y	= 101,
+	BCU_VD_SLAVE_DISP2_Y	= 102,
+	BCU_VD_SLAVE_DISP0_C	= 103,
+	BCU_VD_SLAVE_DISP1_C	= 104,
+	BCU_VD_SLAVE_DISP2_C	= 105,
+	BCU_CLUT_BUFFER_0	= 106,
+	BCU_CLUT_BUFFER_1	= 107,
+	BCU_OSD_FRAME_BUFFER_0	= 108,
+	BCU_OSD_FRAME_BUFFER_1	= 109,
+	BCU_GRAPHIC_FRAME_BUFFER0 = 110,
+	BCU_GRAPHIC_FRAME_BUFFER1 = 111,
+	BCU_DVP_VBI_REINSERTION	= 112,
+	BCU_DVP_OSD_FRAME_BUFFER0 = 113,
+	BCU_DVP_OSD_FRAME_BUFFER1 = 114,
+	BCU_GAI_BUFFER		= 115,
+	BCU_GA_SRC_BUFFER_0	= 116,
+	BCU_GA_SRC_BUFFER_1	= 117,
+	BCU_USB_BUFFER_0	= 118,
+	BCU_USB_BUFFER_1	= 119,
+	BCU_FE_3DCOMB_0		= 120,
+	BCU_FE_3DCOMB_1		= 121,
+	BCU_FE_3DCOMB_2		= 122,
+	BCU_FE_3DCOMB_3		= 123,
+	BCU_TNR_BUFFER_0	= 124,
+	BCU_TNR_BUFFER_1	= 125,
+	BCU_TNR_BUFFER_2	= 126,
+	BCU_MVAL_BUFFER		= 127,
+	BCU_RC_BUFFER_0		= 128,
+	BCU_RC_BUFFER_1		= 129,
+	BCU_RC_BUFFER_2		= 130,
+	BCU_RC_BUFFER_3		= 131,
+	BCU_PIP_BUFFER_0	= 132,
+	BCU_PIP_BUFFER_1	= 133,
+	BCU_PIP_BUFFER_2	= 134,
+	BCU_PIP_BUFFER_3	= 135,
+	BCU_EWARP_BUFFER	= 136,
+	BCU_OSD_BUFFER_0	= 137,
+	BCU_OSD_BUFFER_1	= 138,
+	BCU_GLOBAL_BUFFER_0	= 139,
+	BCU_GLOBAL_BUFFER_1	= 140,
+	BCU_MAX			= 141
+};
+
+#endif /* _BCU_H */
diff --git a/u-boot/board/micronas/vct/config.mk b/u-boot/board/micronas/vct/config.mk
new file mode 100644
index 0000000..ae7c58f
--- /dev/null
+++ b/u-boot/board/micronas/vct/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# vct_xxx boards with MIPS 4Kc CPU core
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0x87000000
+endif
diff --git a/u-boot/board/micronas/vct/dcgu.c b/u-boot/board/micronas/vct/dcgu.c
new file mode 100644
index 0000000..b2e86b7
--- /dev/null
+++ b/u-boot/board/micronas/vct/dcgu.c
@@ -0,0 +1,258 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Original Author Guenter Gebhardt
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+
+#include "vct.h"
+
+int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
+{
+	u32 enable;
+	union dcgu_clk_en1 en1;
+	union dcgu_clk_en2 en2;
+
+	switch (setup) {
+	case DCGU_SWITCH_ON:
+		enable = 1;
+		break;
+	case DCGU_SWITCH_OFF:
+		enable = 0;
+		break;
+	default:
+		printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
+		       setup);
+		return -EINVAL;
+	}
+
+	if (module == DCGU_HW_MODULE_CPU)
+		en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
+	else
+		en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
+
+	switch (module) {
+	case DCGU_HW_MODULE_MSMC:
+		en1.bits.en_clkmsmc = enable;
+		break;
+	case DCGU_HW_MODULE_SSI_S:
+		en1.bits.en_clkssi_s = enable;
+		break;
+	case DCGU_HW_MODULE_SSI_M:
+		en1.bits.en_clkssi_m = enable;
+		break;
+	case DCGU_HW_MODULE_SMC:
+		en1.bits.en_clksmc = enable;
+		break;
+	case DCGU_HW_MODULE_EBI:
+		en1.bits.en_clkebi = enable;
+		break;
+	case DCGU_HW_MODULE_USB_PLL:
+		en1.bits.en_usbpll = enable;
+		break;
+	case DCGU_HW_MODULE_USB_60:
+		en1.bits.en_clkusb60 = enable;
+		break;
+	case DCGU_HW_MODULE_USB_24:
+		en1.bits.en_clkusb24 = enable;
+		break;
+	case DCGU_HW_MODULE_UART_2:
+		en1.bits.en_clkuart2 = enable;
+		break;
+	case DCGU_HW_MODULE_UART_1:
+		en1.bits.en_clkuart1 = enable;
+		break;
+	case DCGU_HW_MODULE_PERI:
+		en1.bits.en_clkperi20 = enable;
+		break;
+	case DCGU_HW_MODULE_CPU:
+		en2.bits.en_clkcpu = enable;
+		break;
+	case DCGU_HW_MODULE_I2S:
+		en1.bits.en_clk_i2s_dly = enable;
+		break;
+	case DCGU_HW_MODULE_ABP_SCC:
+		en1.bits.en_clk_scc_abp = enable;
+		break;
+	case DCGU_HW_MODULE_SPDIF:
+		en1.bits.en_clk_dtv_spdo = enable;
+		break;
+	case DCGU_HW_MODULE_AD:
+		en1.bits.en_clkad = enable;
+		break;
+	case DCGU_HW_MODULE_MVD:
+		en1.bits.en_clkmvd = enable;
+		break;
+	case DCGU_HW_MODULE_TSD:
+		en1.bits.en_clktsd = enable;
+		break;
+	case DCGU_HW_MODULE_GA:
+		en1.bits.en_clkga = enable;
+		break;
+	case DCGU_HW_MODULE_DVP:
+		en1.bits.en_clkdvp = enable;
+		break;
+	case DCGU_HW_MODULE_MR2:
+		en1.bits.en_clkmr2 = enable;
+		break;
+	case DCGU_HW_MODULE_MR1:
+		en1.bits.en_clkmr1 = enable;
+		break;
+	default:
+		printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
+		       __LINE__, module);
+		return -EINVAL;
+	}
+
+	/*
+	 * The reg_read() following the reg_write() below forces the write to
+	 * be really done on the bus.
+	 * Otherwise the clock may not be switched on when this API function
+	 * returns, which may cause an bus error if a registers of the hardware
+	 * module connected to the clock is accessed.
+	 */
+	if (module == DCGU_HW_MODULE_CPU) {
+		reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
+		en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
+	} else {
+		reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
+		en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
+	}
+
+	return 0;
+}
+
+int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
+{
+	union dcgu_reset_unit1 val;
+	u32 enable;
+
+	switch (setup) {
+	case DCGU_SWITCH_ON:
+		enable = 1;
+		break;
+	case DCGU_SWITCH_OFF:
+		enable = 0;
+		break;
+	default:
+		printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
+		       setup);
+		return -EINVAL;
+	}
+
+	val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
+	switch (module) {
+	case DCGU_HW_MODULE_MSMC:
+		val.bits.swreset_clkmsmc = enable;
+		break;
+	case DCGU_HW_MODULE_SSI_S:
+		val.bits.swreset_clkssi_s = enable;
+		break;
+	case DCGU_HW_MODULE_SSI_M:
+		val.bits.swreset_clkssi_m = enable;
+		break;
+	case DCGU_HW_MODULE_SMC:
+		val.bits.swreset_clksmc = enable;
+		break;
+	case DCGU_HW_MODULE_EBI:
+		val.bits.swreset_clkebi = enable;
+		break;
+	case DCGU_HW_MODULE_USB_60:
+		val.bits.swreset_clkusb60 = enable;
+		break;
+	case DCGU_HW_MODULE_USB_24:
+		val.bits.swreset_clkusb24 = enable;
+		break;
+	case DCGU_HW_MODULE_UART_2:
+		val.bits.swreset_clkuart2 = enable;
+		break;
+	case DCGU_HW_MODULE_UART_1:
+		val.bits.swreset_clkuart1 = enable;
+		break;
+	case DCGU_HW_MODULE_PWM:
+		val.bits.swreset_pwm = enable;
+		break;
+	case DCGU_HW_MODULE_GPT:
+		val.bits.swreset_gpt = enable;
+		break;
+	case DCGU_HW_MODULE_I2C2:
+		val.bits.swreset_i2c2 = enable;
+		break;
+	case DCGU_HW_MODULE_I2C1:
+		val.bits.swreset_i2c1 = enable;
+		break;
+	case DCGU_HW_MODULE_GPIO2:
+		val.bits.swreset_gpio2 = enable;
+		break;
+	case DCGU_HW_MODULE_GPIO1:
+		val.bits.swreset_gpio1 = enable;
+		break;
+	case DCGU_HW_MODULE_CPU:
+		val.bits.swreset_clkcpu = enable;
+		break;
+	case DCGU_HW_MODULE_I2S:
+		val.bits.swreset_clk_i2s_dly = enable;
+		break;
+	case DCGU_HW_MODULE_ABP_SCC:
+		val.bits.swreset_clk_scc_abp = enable;
+		break;
+	case DCGU_HW_MODULE_SPDIF:
+		val.bits.swreset_clk_dtv_spdo = enable;
+		break;
+	case DCGU_HW_MODULE_AD:
+		val.bits.swreset_clkad = enable;
+		break;
+	case DCGU_HW_MODULE_MVD:
+		val.bits.swreset_clkmvd = enable;
+		break;
+	case DCGU_HW_MODULE_TSD:
+		val.bits.swreset_clktsd = enable;
+		break;
+	case DCGU_HW_MODULE_TSIO:
+		val.bits.swreset_clktsio = enable;
+		break;
+	case DCGU_HW_MODULE_GA:
+		val.bits.swreset_clkga = enable;
+		break;
+	case DCGU_HW_MODULE_MPC:
+		val.bits.swreset_clkmpc = enable;
+		break;
+	case DCGU_HW_MODULE_CVE:
+		val.bits.swreset_clkcve = enable;
+		break;
+	case DCGU_HW_MODULE_DVP:
+		val.bits.swreset_clkdvp = enable;
+		break;
+	case DCGU_HW_MODULE_MR2:
+		val.bits.swreset_clkmr2 = enable;
+		break;
+	case DCGU_HW_MODULE_MR1:
+		val.bits.swreset_clkmr1 = enable;
+		break;
+	default:
+		printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
+		       __LINE__, module);
+		return -EINVAL;
+	}
+	reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
+
+	return 0;
+}
diff --git a/u-boot/board/micronas/vct/dcgu.h b/u-boot/board/micronas/vct/dcgu.h
new file mode 100644
index 0000000..ca129c0
--- /dev/null
+++ b/u-boot/board/micronas/vct/dcgu.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DCGU_H
+#define _DCGU_H
+
+enum dcgu_switch {
+	DCGU_SWITCH_OFF,	/* Switch off				*/
+	DCGU_SWITCH_ON		/* Switch on				*/
+};
+
+enum dcgu_hw_module {
+	DCGU_HW_MODULE_DCGU,	/* Selects digital clock gen. unit	*/
+
+	DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface	*/
+	DCGU_HW_MODULE_SCI,	/* Selects SCI target agent port modules*/
+
+	DCGU_HW_MODULE_MR1,	/* Selects first MPEG reader module	*/
+	DCGU_HW_MODULE_MR2,	/* Selects second MPEG reader module	*/
+	DCGU_HW_MODULE_MVD,	/* Selects MPEG video decoder module	*/
+	DCGU_HW_MODULE_DVP,	/* Selects dig video processing module	*/
+	DCGU_HW_MODULE_CVE,	/* Selects color video encoder module	*/
+	DCGU_HW_MODULE_VID_ENC,	/* Selects video encoder module		*/
+
+	DCGU_HW_MODULE_SSI_S,	/* Selects slave sync serial interface	*/
+	DCGU_HW_MODULE_SSI_M,	/* Selects master sync serial interface	*/
+
+	DCGU_HW_MODULE_GA,	/* Selects graphics accelerator module	*/
+	DCGU_HW_MODULE_DGPU,	/* Selects digital graphics processing	*/
+
+	DCGU_HW_MODULE_UART_1,	/* Selects first UART module		*/
+	DCGU_HW_MODULE_UART_2,	/* Selects second UART module		*/
+
+	DCGU_HW_MODULE_AD,	/* Selects audio decoder module		*/
+	DCGU_HW_MODULE_ABP_DTV,	/* Selects audio baseband processing	*/
+	DCGU_HW_MODULE_ABP_SCC,	/* Selects audio base band processor SCC*/
+	DCGU_HW_MODULE_SPDIF,	/* Selects sony philips digital interf.	*/
+
+	DCGU_HW_MODULE_TSIO,	/* Selects trasnport stream input/output*/
+	DCGU_HW_MODULE_TSD,	/* Selects trasnport stream decoder	*/
+	DCGU_HW_MODULE_TSD_KEY,	/* Selects trasnport stream decoder key	*/
+
+	DCGU_HW_MODULE_USBH,	/* Selects USB hub module		*/
+	DCGU_HW_MODULE_USB_PLL,	/* Selects USB phase locked loop module	*/
+	DCGU_HW_MODULE_USB_60,	/* Selects USB 60 module		*/
+	DCGU_HW_MODULE_USB_24,	/* Selects USB 24 module		*/
+
+	DCGU_HW_MODULE_PERI,	/* Selects all mod connected to clkperi20*/
+	DCGU_HW_MODULE_WDT,	/* Selects wtg timer mod con to clkperi20*/
+	DCGU_HW_MODULE_I2C1,	/* Selects first I2C mod con to clkperi20*/
+	DCGU_HW_MODULE_I2C2,	/* Selects 2nd I2C mod con to clkperi20	*/
+	DCGU_HW_MODULE_GPIO1,	/* Selects gpio module 1		*/
+	DCGU_HW_MODULE_GPIO2,	/* Selects gpio module 2		*/
+
+	DCGU_HW_MODULE_GPT,	/* Selects gpt mod connected to clkperi20*/
+	DCGU_HW_MODULE_PWM,	/* Selects pwm mod connected to clkperi20*/
+
+	DCGU_HW_MODULE_MPC,	/* Selects multi purpose cipher module	*/
+	DCGU_HW_MODULE_MPC_KEY,	/* Selects multi purpose cipher key	*/
+
+	DCGU_HW_MODULE_COM,	/* Selects COM unit module		*/
+	DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module		*/
+	DCGU_HW_MODULE_FWSRAM,	/* Selects firmware SRAM module		*/
+
+	DCGU_HW_MODULE_EBI,	/* Selects external bus interface module*/
+	DCGU_HW_MODULE_I2S,	/* Selects integrated interchip sound	*/
+	DCGU_HW_MODULE_MSMC,	/* Selects memory stick and mmc module	*/
+	DCGU_HW_MODULE_SMC,	/* Selects smartcard interface module	*/
+
+	DCGU_HW_MODULE_IRQC,	/* Selects interrupt C module		*/
+	DCGU_HW_MODULE_TOP,	/* Selects top level pinmux module	*/
+	DCGU_HW_MODULE_SRAM,	/* Selects SRAM module			*/
+	DCGU_HW_MODULE_EIC,	/* Selects External Interrupt controller*/
+	DCGU_HW_MODULE_CPU,	/* Selects CPU subsystem module		*/
+	DCGU_HW_MODULE_SCC,	/* Selects SCC module			*/
+	DCGU_HW_MODULE_MM,	/* Selects Memory Manager module	*/
+	DCGU_HW_MODULE_BCU,	/* Selects Buffer Configuration Unit	*/
+	DCGU_HW_MODULE_FH,	/* Selects FIFO Handler module		*/
+	DCGU_HW_MODULE_IMU,	/* Selects Interrupt Management Unit	*/
+	DCGU_HW_MODULE_MDU,	/* Selects MCI Debug Unit module	*/
+	DCGU_HW_MODULE_SI2OCP	/* Selects Standard Interface to OCP bridge*/
+};
+
+union dcgu_clk_en1 {
+	u32 reg;
+	struct {
+		u32 res1:8;		/* reserved			*/
+		u32 en_clkmsmc:1;	/* Enable bit for clkmsmc (#)	*/
+		u32 en_clkssi_s:1;	/* Enable bit for clkssi_s (#)	*/
+		u32 en_clkssi_m:1;	/* Enable bit for clkssi_m (#)	*/
+		u32 en_clksmc:1;	/* Enable bit for clksmc (#)	*/
+		u32 en_clkebi:1;	/* Enable bit for clkebi (#)	*/
+		u32 en_usbpll:1;	/* Enable bit for the USB PLL	*/
+		u32 en_clkusb60:1;	/* Enable bit for clkusb60 (#)	*/
+		u32 en_clkusb24:1;	/* Enable bit for clkusb24 (#)	*/
+		u32 en_clkuart2:1;	/* Enable bit for clkuart2 (#)	*/
+		u32 en_clkuart1:1;	/* Enable bit for clkuart1 (#)	*/
+		u32 en_clkperi20:1;	/* Enable bit for clkperi20 (#)	*/
+		u32 res2:3;		/* reserved			*/
+		u32 en_clk_i2s_dly:1;	/* Enable bit for clk_scc_abp	*/
+		u32 en_clk_scc_abp:1;	/* Enable bit for clk_scc_abp	*/
+		u32 en_clk_dtv_spdo:1;	/* Enable bit for clk_dtv_spdo	*/
+		u32 en_clkad:1;		/* Enable bit for clkad (#)	*/
+		u32 en_clkmvd:1;	/* Enable bit for clkmvd (#)	*/
+		u32 en_clktsd:1;	/* Enable bit for clktsd (#)	*/
+		u32 en_clkga:1;		/* Enable bit for clkga (#)	*/
+		u32 en_clkdvp:1;	/* Enable bit for clkdvp (#)	*/
+		u32 en_clkmr2:1;	/* Enable bit for clkmr2 (#)	*/
+		u32 en_clkmr1:1;	/* Enable bit for clkmr1 (#)	*/
+	} bits;
+};
+
+union dcgu_clk_en2 {
+	u32 reg;
+	struct {
+		u32 res1:31;		/* reserved			*/
+		u32 en_clkcpu:1;	/* Enable bit for clkcpu	*/
+	} bits;
+};
+
+union dcgu_reset_unit1 {
+	u32 reg;
+	struct {
+		u32 res1:1;
+		u32 swreset_clkmsmc:1;
+		u32 swreset_clkssi_s:1;
+		u32 swreset_clkssi_m:1;
+		u32 swreset_clksmc:1;
+		u32 swreset_clkebi:1;
+		u32 swreset_clkusb60:1;
+		u32 swreset_clkusb24:1;
+		u32 swreset_clkuart2:1;
+		u32 swreset_clkuart1:1;
+		u32 swreset_pwm:1;
+		u32 swreset_gpt:1;
+		u32 swreset_i2c2:1;
+		u32 swreset_i2c1:1;
+		u32 swreset_gpio2:1;
+		u32 swreset_gpio1:1;
+		u32 swreset_clkcpu:1;
+		u32 res2:2;
+		u32 swreset_clk_i2s_dly:1;
+		u32 swreset_clk_scc_abp:1;
+		u32 swreset_clk_dtv_spdo:1;
+		u32 swreset_clkad:1;
+		u32 swreset_clkmvd:1;
+		u32 swreset_clktsd:1;
+		u32 swreset_clktsio:1;
+		u32 swreset_clkga:1;
+		u32 swreset_clkmpc:1;
+		u32 swreset_clkcve:1;
+		u32 swreset_clkdvp:1;
+		u32 swreset_clkmr2:1;
+		u32 swreset_clkmr1:1;
+	} bits;
+};
+
+int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
+int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
+
+#endif /* _DCGU_H */
diff --git a/u-boot/board/micronas/vct/ebi.c b/u-boot/board/micronas/vct/ebi.c
new file mode 100644
index 0000000..8e93f69
--- /dev/null
+++ b/u-boot/board/micronas/vct/ebi.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+int ebi_initialize(void)
+{
+#if defined(CONFIG_VCT_NOR)
+	if (ebi_init_nor_flash())
+		return -1;
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+	if (ebi_init_onenand())
+		return -1;
+#endif
+
+#if defined(CONFIG_DRIVER_SMC911X)
+	if (ebi_init_smc911x())
+		return -1;
+#endif
+
+	reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100);
+
+	ebi_wait();
+
+	return 0;
+}
diff --git a/u-boot/board/micronas/vct/ebi.h b/u-boot/board/micronas/vct/ebi.h
new file mode 100644
index 0000000..69456bd
--- /dev/null
+++ b/u-boot/board/micronas/vct/ebi.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EBI__
+#define __EBI__
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+#define EXT_DEVICE_CHANNEL_3	(0x30000000)
+#define EXT_DEVICE_CHANNEL_2	(0x20000000)
+#define EXT_DEVICE_CHANNEL_1	(0x10000000)
+#define EXT_CPU_ACCESS_ACTIVE	(0x00000001)
+#define EXT_DMA_ACCESS_ACTIVE	(1 << 14)
+#define EXT_CPU_IORDY_SL	(0x00000001)
+
+#define EBI_CPU_WRITE		(1 << 31)
+#define EBI_CPU_ID_SHIFT	(28)
+#define EBI_CPU_ADDR_MASK	~(~0UL << EBI_CPU_ID_SHIFT)
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
+#define ADDR_LATCH_ENABLE	0
+#define ADDR_ACTIVATION		4
+#define CHIP_SELECT_START	8
+#define OUTPUT_ENABLE_START	12
+#define WAIT_TIME		28
+#define READ_DURATION		20
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
+#define OUTPUT_ENABLE_END	0
+#define CHIP_SELECT_END		4
+#define ADDR_DEACTIVATION	8
+#define RECOVER_TIME		12
+#define ACK_TIME		20
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG1 */
+#define EBI_EXTERNAL_DATA_8	(1 <<  8)
+#define EBI_EXT_ADDR_SHIFT	(1 << 22)
+#define EBI_EXTERNAL_DATA_16	EBI_EXT_ADDR_SHIFT
+#define EBI_CHIP_SELECT_1	0x2
+#define EBI_CHIP_SELECT_2	0x4
+#define EBI_BUSY_EN_RD		(1 << 12)
+#define DIR_ACCESS_WRITE	(1 << 20)
+#define DIR_ACCESS_MASK		(1 << 20)
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG2 */
+#define ADDRESS_INCREMENT_ON	0x0
+#define ADDRESS_INCREMENT_OFF	0x100
+#define QUEUE_LENGTH_1		0x40
+#define QUEUE_LENGTH_2		0x80
+#define QUEUE_LENGTH_3		0xC0
+#define QUEUE_LENGTH_4		0
+#define CPU_TRANSFER_SIZE_32	0
+#define CPU_TRANSFER_SIZE_16	0x10
+#define CPU_TRANSFER_SIZE_8	0x20
+#define READ_ENDIANNESS_ABCD	0
+#define READ_ENDIANNESS_DCBA	0x4
+#define READ_ENDIANNESS_BADC	0x8
+#define READ_ENDIANNESS_CDAB	0xC
+#define WRITE_ENDIANNESS_ABCD	0
+#define WRITE_ENDIANNESS_DCBA	0x1
+#define WRITE_ENDIANNESS_BADC	0x2
+#define WRITE_ENDIANNESS_CDAB	0x3
+
+/* various bits in configuration register EBI_CTRL_SIG_ACTLV */
+#define IORDY_ACTIVELEVEL_HIGH	(1 << 14)
+#define ALE_ACTIVELEVEL_HIGH	(1 <<  8)
+
+/* bits in register EBI_SIG_LEVEL */
+#define IORDY_LEVEL_MASK	1
+
+static inline void ebi_wait(void)
+{
+	while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
+		;	/* wait */
+}
+
+#endif
diff --git a/u-boot/board/micronas/vct/ebi_nor_flash.c b/u-boot/board/micronas/vct/ebi_nor_flash.c
new file mode 100644
index 0000000..ae87643
--- /dev/null
+++ b/u-boot/board/micronas/vct/ebi_nor_flash.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+static u32 ebi_read(u32 addr)
+{
+	addr &= ~0xFC000000;
+
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr);
+	ebi_wait();
+
+	return reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+}
+
+static int ebi_write_u16(u32 addr, u32 data, int fetchIO)
+{
+	u32 val = (data << 16);
+
+	addr &= ~0xFC000000;
+
+	ebi_wait();
+
+	reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val);
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+		  EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr);
+	ebi_wait();
+
+	if (fetchIO) {
+		u32 counter = 0;
+		while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) {
+			if (counter++ > 0xFFFFFF)
+				return 1;
+		}
+	}
+
+	return 0;
+}
+
+static u16 ebi_read_u16(u32 addr)
+{
+	return ((ebi_read(addr) >> 16) & 0xFFFF);
+}
+
+static u8 ebi_read_u8(u32 addr)
+{
+	u32 val = ebi_read(addr) >> 16;
+
+	if (addr & 0x1)
+		return val & 0xff;
+	else
+		return (val >> 8) & 0xff;
+}
+
+/*
+ * EBI initialization for NOR FLASH access
+ */
+int ebi_init_nor_flash(void)
+{
+	reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
+
+	reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002);
+	reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
+
+	reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113);
+	reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000);
+	reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113);
+	reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011);
+	reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
+
+	return 0;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ */
+void flash_write8(u8 value, void *addr)
+{
+	ebi_write_u16((u32)addr, value, 0);
+}
+
+void flash_write16(u16 value, void *addr)
+{
+	ebi_write_u16((u32)addr, value, 0);
+}
+
+u8 flash_read8(void *addr)
+{
+	return ebi_read_u8((u32)addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	return ebi_read_u16((u32)addr);
+}
+
+u32 flash_read32(void *addr)
+{
+	return ((u32)ebi_read_u16((u32)addr) << 16) |
+		ebi_read_u16((u32)addr + 2);
+}
+
+void *board_flash_read_memcpy(void *dest, const void *src, size_t count)
+{
+	u16 *tmp = (u16 *)dest, *s = (u16 *)src;
+	int i;
+
+	for (i = 0; i < count; i += 2)
+		*tmp++ = flash_read16(s++);
+
+	return dest;
+}
diff --git a/u-boot/board/micronas/vct/ebi_onenand.c b/u-boot/board/micronas/vct/ebi_onenand.c
new file mode 100644
index 0000000..1e8afa6
--- /dev/null
+++ b/u-boot/board/micronas/vct/ebi_onenand.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include "vct.h"
+
+#define BURST_SIZE_WORDS		4
+
+static u16 ebi_nand_read_word(void __iomem *addr)
+{
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr));
+	ebi_wait();
+
+	return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16;
+}
+
+static void ebi_nand_write_word(u16 data, void __iomem * addr)
+{
+	ebi_wait();
+	reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16));
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+		  EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr);
+	ebi_wait();
+}
+
+/*
+ * EBI initialization for OneNAND FLASH access
+ */
+int ebi_init_onenand(void)
+{
+	reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
+
+	reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002);
+	reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
+
+	reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002);
+	reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */
+
+	reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000);
+	reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000);
+	reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223);
+	reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220);
+	reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000);
+	reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000);
+	reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000);
+	reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200);
+
+	reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
+	reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+	reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000);
+	reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+	/* prepare DMA configuration for EBI */
+	reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00);
+
+	/* READ only no byte order change, TAG 1 used */
+	reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004);
+
+	reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */
+	reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1);
+	reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2);
+	reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3);
+
+	return 0;
+}
+
+static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len)
+{
+	void *ret = dst;
+	u16 *d = dst;
+	u16 *s = (u16 *)src;
+
+	len >>= 1;
+	while (len-- > 0)
+		*d++ = ebi_nand_read_word(s++);
+
+	return ret;
+}
+
+static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len)
+{
+	void *ret = dst;
+	u32 *d = (u32 *)dst;
+	u32 s = (u32)src;
+	u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int);
+	u32 n_blocks = len / bytes_per_block;
+	u32 block = 0;
+	u32 burst_word;
+
+	for (block = 0; block < n_blocks; block++) {
+		/* Trigger read channel 3 */
+		reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+			  (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block))));
+		/* Poll status to see whether read has finished */
+		ebi_wait();
+
+		/* Squirrel the data away in a safe place */
+		for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++)
+			*d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+	}
+
+	return ret;
+}
+
+static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len)
+{
+	void *ret = dst;
+	u16 *d = dst;
+	u16 *s = (u16 *)src;
+
+	len >>= 1;
+	while (len-- > 0)
+		ebi_nand_write_word(*s++, d++);
+
+	return ret;
+}
+
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == ONENAND_DATARAM)
+			return mtd->writesize;
+		if (area == ONENAND_SPARERAM)
+			return mtd->oobsize;
+	}
+
+	return 0;
+}
+
+static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+			      unsigned char *buffer, int offset,
+			      size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	if (count < 4)
+		memcpy_16_from_onenand(buffer, bufferram + offset, count);
+	else
+		memcpy_32_from_onenand(buffer, bufferram + offset, count);
+
+	return 0;
+}
+
+static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+			       const unsigned char *buffer, int offset,
+			       size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	memcpy_16_to_onenand(bufferram + offset, buffer, count);
+
+	return 0;
+}
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *chip = mtd->priv;
+
+	/*
+	 * Insert board specific OneNAND access functions
+	 */
+	chip->read_word = ebi_nand_read_word;
+	chip->write_word = ebi_nand_write_word;
+
+	chip->read_bufferram = ebi_read_bufferram;
+	chip->write_bufferram = ebi_write_bufferram;
+}
diff --git a/u-boot/board/micronas/vct/ebi_smc911x.c b/u-boot/board/micronas/vct/ebi_smc911x.c
new file mode 100644
index 0000000..c9ef33d
--- /dev/null
+++ b/u-boot/board/micronas/vct/ebi_smc911x.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "vct.h"
+
+/*
+ * EBI initialization for SMC911x access
+ */
+int ebi_init_smc911x(void)
+{
+	reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020);
+	reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+
+	reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100);
+	reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111);
+
+	reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000);
+	reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+	reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100);
+	reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110);
+
+	return 0;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/net/smc911x.c
+ */
+u32 smc911x_reg_read(struct eth_device *dev, u32 addr)
+{
+	volatile u32 data;
+
+	addr += dev->iobase;
+	reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+	ebi_wait();
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
+	ebi_wait();
+	data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+
+	return (data);
+}
+
+void smc911x_reg_write(struct eth_device *dev, u32 addr, u32 data)
+{
+	addr += dev->iobase;
+	reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+	ebi_wait();
+	reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+		  EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
+	ebi_wait();
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 data)
+{
+	addr += dev->iobase;
+	reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
+	ebi_wait();
+	reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+		  EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
+	ebi_wait();
+
+	return;
+}
+
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+	volatile u32 data;
+
+	addr += dev->iobase;
+	reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
+	ebi_wait();
+	reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
+	ebi_wait();
+	data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+
+	return data;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_DRIVER_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/micronas/vct/ehci.c b/u-boot/board/micronas/vct/ehci.c
new file mode 100644
index 0000000..d04bdce
--- /dev/null
+++ b/u-boot/board/micronas/vct/ehci.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Original Author Guenter Gebhardt
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include "vct.h"
+
+int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
+{
+	int retval;
+	u32 val;
+	u32 addr;
+
+	dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
+	dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
+	dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
+	dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
+	dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
+
+	/* Wait until (DCGU_USBPHY_STAT == 7) */
+	addr = DCGU_USBPHY_STAT(DCGU_BASE);
+	val = reg_read(addr);
+	while (val != 7)
+		val = reg_read(addr);
+
+	dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
+	dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
+
+	retval = scc_reset(SCC_USB_RW, 0);
+	if (retval) {
+		printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
+		return retval;
+	} else {
+		retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
+		if (retval) {
+			printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
+			       retval);
+			return retval;
+		}
+	}
+
+	if (!retval) {
+		/*
+		 * For the AGU bypass, where the  SCC client provides full
+		 * physical address
+		 */
+		scc_set_usb_address_generation_mode(1);
+		scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
+			      USE_NO_FH, DMA_READ, 0);
+		scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
+			      USE_NO_FH, DMA_WRITE, 0);
+		scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
+			      USE_NO_FH, DMA_WRITE, 0);
+		scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
+			      USE_NO_FH, DMA_READ, 0);
+
+		/* Enable memory interface */
+		scc_enable(SCC_USB_RW, 1);
+
+		/* Start (start_cmd=0) DMAs */
+		scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
+		scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
+	} else {
+		printf("Cannot configure USB memory channel.\n");
+		printf("USB can not access RAM. SCC configuration failed.\n");
+		return retval;
+	}
+
+	/* Wait a short while */
+	udelay(300000);
+
+	reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
+
+	/* Set EHCI structures and DATA in RAM */
+	reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
+	/* Set USBMODE to bigendian and set host mode */
+	reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
+
+	/*
+	 * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
+	 * 512 byte USB transfers on the bulk pipe to work properly.
+	 * Set USBH_BURSTSIZE to 0x00001c1c
+	 */
+	reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
+
+	/* Insert access register addresses */
+	*hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
+	*hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
+
+	return 0;
+}
diff --git a/u-boot/board/micronas/vct/gpio.c b/u-boot/board/micronas/vct/gpio.c
new file mode 100644
index 0000000..2c113be
--- /dev/null
+++ b/u-boot/board/micronas/vct/gpio.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+/*
+ * Find out to which of the 2 gpio modules the pin specified in the
+ * argument belongs:
+ * GPIO_MODULE yields 0 for pins  0 to 31,
+ *                    1 for pins 32 to 63
+ */
+#define GPIO_MODULE(pin)	((pin) >> 5)
+
+/*
+ * Bit position within a 32-bit peripheral register (where every
+ * bit is one bitslice)
+ */
+#define MASK(pin)		(1 << ((pin) & 0x1F))
+#define BASE_ADDR(mod)		module_base[mod]
+
+/*
+ * Lookup table for transforming gpio module number 0 to 2 to
+ * address offsets
+ */
+static u32 module_base[] = {
+	GPIO1_BASE,
+	GPIO2_BASE
+};
+
+static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask)
+{
+	reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask);
+}
+
+int vct_gpio_dir(int pin, int dir)
+{
+	u32 gpio_base;
+
+	gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+
+	if (dir == 0)
+		clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0);
+	else
+		clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin));
+
+	return 0;
+}
+
+void vct_gpio_set(int pin, int val)
+{
+	u32 gpio_base;
+
+	gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+
+	if (val == 0)
+		clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0);
+	else
+		clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin));
+}
+
+int vct_gpio_get(int pin)
+{
+	u32 gpio_base;
+	u32 value;
+
+	gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+	value = reg_read(GPIO_EXT_PORTA(gpio_base));
+
+	return ((value & MASK(pin)) ? 1 : 0);
+}
diff --git a/u-boot/board/micronas/vct/scc.c b/u-boot/board/micronas/vct/scc.c
new file mode 100644
index 0000000..0368183
--- /dev/null
+++ b/u-boot/board/micronas/vct/scc.c
@@ -0,0 +1,669 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+
+#include "vct.h"
+
+/*
+ * List of statically defined buffers per SCC.
+ * The first entry in the table is the number of fixed buffers
+ * followed by the list of buffer IDs
+ */
+static u32 buffer_list_0[] = { 6, 120, 121, 122, 123, 139, 140 };
+static u32 buffer_list_1[] = { 6, 120, 121, 122, 123, 139, 140 };
+static u32 buffer_list_2[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_3[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_4[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_5[] = { 3, 127, 139, 140 };
+static u32 buffer_list_6[] = { 3, 127, 139, 140 };
+static u32 buffer_list_7[] = { 6, 128, 129, 130, 131, 139, 140 };
+static u32 buffer_list_8[] = { 6, 128, 129, 130, 131, 139, 140 };
+static u32 buffer_list_9[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_10[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_11[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_12[] = { 6, 132, 133, 134, 135, 139, 140 };
+static u32 buffer_list_13[] = { 6, 132, 133, 134, 135, 139, 140 };
+static u32 buffer_list_14[] = { 4, 137, 138, 139, 140 };
+static u32 buffer_list_15[] = { 6, 136, 136, 137, 138, 139, 140 };
+
+/** Issue#7674 (new) - DP/DVP buffer assignment */
+static u32 buffer_list_16[] = { 6, 106, 108, 109, 107, 139, 140 };
+static u32 buffer_list_17[] = { 6, 106, 110, 107, 111, 139, 140 };
+static u32 buffer_list_18[] = { 6, 106, 113, 107, 114, 139, 140 };
+static u32 buffer_list_19[] = { 3, 112, 139, 140 };
+static u32 buffer_list_20[] = { 35, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				79, 80, 81, 82, 83, 84, 85, 86, 139, 140 };
+static u32 buffer_list_21[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				139, 140 };
+static u32 buffer_list_22[] = { 81, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+				37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+				61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+				73, 74, 75, 76, 77, 78, 139, 140 };
+static u32 buffer_list_23[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				88, 89, 139, 140 };
+static u32 buffer_list_24[] = { 6, 90, 91, 92, 93, 139, 140 };
+static u32 buffer_list_25[] = { 18, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
+				100, 101, 102, 103, 104, 105, 139, 140 };
+static u32 buffer_list_26[] = { 5, 94, 95, 96, 139, 140 };
+static u32 buffer_list_27[] = { 5, 97, 98, 99, 139, 140 };
+static u32 buffer_list_28[] = { 5, 100, 101, 102, 139, 140 };
+static u32 buffer_list_29[] = { 5, 103, 104, 105, 139, 140 };
+static u32 buffer_list_30[] = { 10, 108, 109, 110, 111, 113, 114, 116, 117,
+				139, 140 };
+static u32 buffer_list_31[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
+				115, 116, 117, 139, 140 };
+static u32 buffer_list_32[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
+				115, 116, 117, 139, 140 };
+static u32 buffer_list_33[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				139, 140 };
+static u32 buffer_list_34[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				139, 140 };
+static u32 buffer_list_35[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				87, 139, 140 };
+static u32 buffer_list_36[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				87, 139, 140 };
+static u32 buffer_list_37[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				139, 140 };
+static u32 buffer_list_38[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				118, 119, 139, 140 };
+static u32 buffer_list_39[] = { 91, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+				13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+				25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+				37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+				61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+				73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+				85, 86, 118, 119, 139, 140 };
+static u32 buffer_list_40[] = { 0 };
+
+/*
+ * List of statically defined vcid.csize values.
+ * The first entry in the table is the number of possible csize values
+ * followed by the list of data path values in bits.
+ */
+static u32 csize_list_0[] = { 2, 0, 1 };
+static u32 csize_list_1[] = { 2, 0, 1 };
+static u32 csize_list_2[] = { 1, 1 };
+static u32 csize_list_3[] = { 1, 1 };
+static u32 csize_list_4[] = { 1, 1 };
+static u32 csize_list_5[] = { 1, 0 };
+static u32 csize_list_6[] = { 1, 0 };
+static u32 csize_list_7[] = { 1, 1 };
+static u32 csize_list_8[] = { 1, 1 };
+static u32 csize_list_9[] = { 1, 1 };
+static u32 csize_list_10[] = { 1, 1 };
+static u32 csize_list_11[] = { 1, 1 };
+static u32 csize_list_12[] = { 1, 1 };
+static u32 csize_list_13[] = { 1, 1 };
+static u32 csize_list_14[] = { 1, 2 };
+static u32 csize_list_15[] = { 1, 4 };
+static u32 csize_list_16[] = { 3, 0, 1, 2 };
+static u32 csize_list_17[] = { 3, 0, 1, 2 };
+static u32 csize_list_18[] = { 3, 0, 1, 2 };
+static u32 csize_list_19[] = { 1, 2 };
+static u32 csize_list_20[] = { 1, 0 };
+static u32 csize_list_21[] = { 1, 0 };
+static u32 csize_list_22[] = { 1, 2 };
+static u32 csize_list_23[] = { 1, 3 };
+static u32 csize_list_24[] = { 1, 3 };
+static u32 csize_list_25[] = { 1, 3 };
+static u32 csize_list_26[] = { 1, 0 };
+static u32 csize_list_27[] = { 1, 0 };
+static u32 csize_list_28[] = { 1, 0 };
+static u32 csize_list_29[] = { 1, 0 };
+static u32 csize_list_30[] = { 1, 2 };
+static u32 csize_list_31[] = { 1, 2 };
+static u32 csize_list_32[] = { 1, 2 };
+static u32 csize_list_33[] = { 1, 2 };
+static u32 csize_list_34[] = { 1, 2 };
+static u32 csize_list_35[] = { 1, 2 };
+static u32 csize_list_36[] = { 1, 2 };
+static u32 csize_list_37[] = { 2, 0, 1 };
+static u32 csize_list_38[] = { 1, 2 };
+static u32 csize_list_39[] = { 1, 3 };
+static u32 csize_list_40[] = { 1, 3 };
+
+/*
+ * SCC_Configuration table
+ */
+static const struct scc_descriptor scc_descriptor_table[] = {
+/* scn  scc_name  profile  SCC  scc_id  mci_id  rd  wr   m   p fh  si cfg sta */
+	{"fe_", "fe_3dcomb_wr", STRM_P, SCC0_BASE, 0, 0, 0, 4, 1, 1, 0, 0, 0, 1,
+	 buffer_list_0, csize_list_0},
+	{"fe_", "fe_3dcomb_rd", STRM_P, SCC1_BASE, 1, 18, 4, 0, 1, 1, 0, 1, 0,
+	 1, buffer_list_1, csize_list_1},
+	{"di_", "di_tnr_wr", STRM_P, SCC2_BASE, 2, 1, 0, 3, 1, 1, 0, 2, 0, 1,
+	 buffer_list_2, csize_list_2},
+	{"di_", "di_tnr_field_rd", STRM_P, SCC3_BASE, 3, 19, 3, 0, 1, 1, 0, 3,
+	 0, 1, buffer_list_3, csize_list_3},
+	{"di_", "di_tnr_frame_rd", STRM_P, SCC4_BASE, 4, 20, 3, 0, 1, 1, 0, 4,
+	 0, 1, buffer_list_4, csize_list_4},
+	{"di_", "di_mval_wr", STRM_P, SCC5_BASE, 5, 2, 0, 1, 1, 1, 0, 5, 0, 1,
+	 buffer_list_5, csize_list_5},
+	{"di_", "di_mval_rd", STRM_P, SCC6_BASE, 6, 21, 1, 0, 1, 1, 0, 6, 0, 1,
+	 buffer_list_6, csize_list_6},
+	{"rc_", "rc_frame_wr", STRM_P, SCC7_BASE, 7, 3, 0, 4, 1, 1, 0, 7, 0, 1,
+	 buffer_list_7, csize_list_7},
+	{"rc_", "rc_frame0_rd", STRM_P, SCC8_BASE, 8, 22, 4, 0, 1, 1, 0, 8, 0,
+	 1, buffer_list_8, csize_list_8},
+	{"opt", "opt_field0_rd", STRM_P, SCC9_BASE, 9, 23, 3, 0, 1, 1, 0, 9, 0,
+	 1, buffer_list_9, csize_list_9},
+	{"opt", "opt_field1_rd", STRM_P, SCC10_BASE, 10, 24, 3, 0, 1, 1, 0, 10,
+	 0, 1, buffer_list_10, csize_list_10},
+	{"opt", "opt_field2_rd", STRM_P, SCC11_BASE, 11, 25, 3, 0, 1, 1, 0, 11,
+	 0, 1, buffer_list_11, csize_list_11},
+	{"pip", "pip_frame_wr", STRM_P, SCC12_BASE, 12, 4, 0, 4, 1, 1, 0, 12, 0,
+	 1, buffer_list_12, csize_list_12},
+	{"pip", "pip_frame_rd", STRM_P, SCC13_BASE, 13, 26, 4, 0, 1, 1, 0, 13,
+	 0, 1, buffer_list_13, csize_list_13},
+	{"dp_", "dp_agpu_rd", STRM_P, SCC14_BASE, 14, 27, 2, 0, 2, 1, 0, 14, 0,
+	 1, buffer_list_14, csize_list_14},
+	{"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0,
+	 buffer_list_15, csize_list_15},
+	{"dp_", "dp_osd_rd", STRM_P, SCC16_BASE, 16, 28, 3, 0, 2, 1, 0, 15, 0,
+	 1, buffer_list_16, csize_list_16},
+	{"dp_", "dp_graphic_rd", STRM_P, SCC17_BASE, 17, 29, 3, 0, 2, 1, 0, 16,
+	 0, 1, buffer_list_17, csize_list_17},
+	{"dvp", "dvp_osd_rd", STRM_P, SCC18_BASE, 18, 30, 2, 0, 2, 1, 0, 17, 0,
+	 1, buffer_list_18, csize_list_18},
+	{"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0,
+	 0, buffer_list_19, csize_list_19},
+	{"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0,
+	 buffer_list_20, csize_list_20},
+	{"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0,
+	 buffer_list_21, csize_list_21},
+	{"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0,
+	 buffer_list_22, csize_list_22},
+	{"vd_", "vd_ud_st_rw", SRMD, SCC23_BASE, 23, 12, 2, 2, 0, 0, 1, -1, 0,
+	 0, buffer_list_23, csize_list_23},
+	{"vd_", "vd_frr_rd", SRMD, SCC24_BASE, 24, 33, 4, 0, 0, 0, 0, -1, 0, 0,
+	 buffer_list_24, csize_list_24},
+	{"vd_", "vd_frw_disp_wr", SRMD, SCC25_BASE, 25, 7, 0, 16, 0, 0, 0, -1,
+	 0, 0, buffer_list_25, csize_list_25},
+	{"mr_", "mr_vd_m_y_rd", STRM_P, SCC26_BASE, 26, 34, 3, 0, 2, 1, 0, 18,
+	 0, 1, buffer_list_26, csize_list_26},
+	{"mr_", "mr_vd_m_c_rd", STRM_P, SCC27_BASE, 27, 35, 3, 0, 2, 1, 0, 19,
+	 0, 1, buffer_list_27, csize_list_27},
+	{"mr_", "mr_vd_s_y_rd", STRM_P, SCC28_BASE, 28, 36, 3, 0, 2, 1, 0, 20,
+	 0, 1, buffer_list_28, csize_list_28},
+	{"mr_", "mr_vd_s_c_rd", STRM_P, SCC29_BASE, 29, 37, 3, 0, 2, 1, 0, 21,
+	 0, 1, buffer_list_29, csize_list_29},
+	{"ga_", "ga_wr", STRM_P, SCC30_BASE, 30, 8, 0, 1, 1, 1, 0, -1, 1, 1,
+	 buffer_list_30, csize_list_30},
+	{"ga_", "ga_src1_rd", STRM_P, SCC31_BASE, 31, 38, 1, 0, 1, 1, 0, -1, 1,
+	 1, buffer_list_31, csize_list_31},
+	{"ga_", "ga_src2_rd", STRM_P, SCC32_BASE, 32, 39, 1, 0, 1, 1, 0, -1, 1,
+	 1, buffer_list_32, csize_list_32},
+	{"ad_", "ad_rd", STRM_D, SCC33_BASE, 33, 40, 2, 0, 0, 1, 1, -1, 0, 0,
+	 buffer_list_33, csize_list_33},
+	{"ad_", "ad_wr", STRM_D, SCC34_BASE, 34, 9, 0, 3, 0, 1, 1, -1, 0, 0,
+	 buffer_list_34, csize_list_34},
+	{"abp", "abp_rd", STRM_D, SCC35_BASE, 35, 41, 5, 0, 0, 1, 1, -1, 0, 0,
+	 buffer_list_35, csize_list_35},
+	{"abp", "abp_wr", STRM_D, SCC36_BASE, 36, 10, 0, 3, 0, 1, 1, -1, 0, 0,
+	 buffer_list_36, csize_list_36},
+	{"ebi", "ebi_rw", STRM_P, SCC37_BASE, 37, 13, 4, 4, 2, 1, 1, -1, 0, 0,
+	 buffer_list_37, csize_list_37},
+	{"usb", "usb_rw", SRMD, SCC38_BASE, 38, 14, 1, 1, 0, 0, 1, -1, 0, 0,
+	 buffer_list_38, csize_list_38},
+	{"cpu", "cpu1_spdma_rw", SRMD, SCC39_BASE, 39, 15, 1, 1, 0, 0, 1, -1, 0,
+	 0, buffer_list_39, csize_list_39},
+	{"cpu", "cpu1_bridge_rw", SRMD, SCC40_BASE, 40, 16, 0, 0, 0, 0, 0, -1,
+	 0, 0, buffer_list_40, csize_list_40},
+};
+
+/* DMA state structures for read and write channels for each SCC */
+
+static struct scc_dma_state scc_state_rd_0[] = { {-1} };
+static struct scc_dma_state scc_state_wr_0[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_1[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_1[] = { {-1} };
+static struct scc_dma_state scc_state_rd_2[] = { {-1} };
+static struct scc_dma_state scc_state_wr_2[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_3[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_3[] = { {-1} };
+static struct scc_dma_state scc_state_rd_4[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_4[] = { {-1} };
+static struct scc_dma_state scc_state_rd_5[] = { {-1} };
+static struct scc_dma_state scc_state_wr_5[] = { {0} };
+static struct scc_dma_state scc_state_rd_6[] = { {0} };
+static struct scc_dma_state scc_state_wr_6[] = { {-1} };
+static struct scc_dma_state scc_state_rd_7[] = { {-1} };
+static struct scc_dma_state scc_state_wr_7[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_8[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_8[] = { {-1} };
+static struct scc_dma_state scc_state_rd_9[] = { {0}, {0}, {0}, };
+static struct scc_dma_state scc_state_wr_9[] = { {-1} };
+static struct scc_dma_state scc_state_rd_10[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_10[] = { {-1} };
+static struct scc_dma_state scc_state_rd_11[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_11[] = { {-1} };
+static struct scc_dma_state scc_state_rd_12[] = { {-1} };
+static struct scc_dma_state scc_state_wr_12[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_13[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_13[] = { {-1} };
+static struct scc_dma_state scc_state_rd_14[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_14[] = { {-1} };
+static struct scc_dma_state scc_state_rd_15[] = { {0} };
+static struct scc_dma_state scc_state_wr_15[] = { {0} };
+static struct scc_dma_state scc_state_rd_16[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_16[] = { {-1} };
+static struct scc_dma_state scc_state_rd_17[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_17[] = { {-1} };
+static struct scc_dma_state scc_state_rd_18[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_18[] = { {-1} };
+static struct scc_dma_state scc_state_rd_19[] = { {0} };
+static struct scc_dma_state scc_state_wr_19[] = { {-1} };
+static struct scc_dma_state scc_state_rd_20[] = { {-1} };
+static struct scc_dma_state scc_state_wr_20[] = {
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_21[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_21[] = { {-1} };
+static struct scc_dma_state scc_state_rd_22[] = { {-1} };
+static struct scc_dma_state scc_state_wr_22[] = {
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_23[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_23[] = { {0}, {0} };
+static struct scc_dma_state scc_state_rd_24[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_24[] = { {-1} };
+static struct scc_dma_state scc_state_rd_25[] = { {-1} };
+static struct scc_dma_state scc_state_wr_25[] = {
+	{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+	{0}, {0} };
+static struct scc_dma_state scc_state_rd_26[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_26[] = { {-1} };
+static struct scc_dma_state scc_state_rd_27[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_27[] = { {-1} };
+static struct scc_dma_state scc_state_rd_28[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_28[] = { {-1} };
+static struct scc_dma_state scc_state_rd_29[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_29[] = { {-1} };
+static struct scc_dma_state scc_state_rd_30[] = { {-1} };
+static struct scc_dma_state scc_state_wr_30[] = { {0} };
+static struct scc_dma_state scc_state_rd_31[] = { {0} };
+static struct scc_dma_state scc_state_wr_31[] = { {-1} };
+static struct scc_dma_state scc_state_rd_32[] = { {0} };
+static struct scc_dma_state scc_state_wr_32[] = { {-1} };
+static struct scc_dma_state scc_state_rd_33[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_33[] = { {-1} };
+static struct scc_dma_state scc_state_rd_34[] = { {-1} };
+static struct scc_dma_state scc_state_wr_34[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_35[] = { {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_35[] = { {-1} };
+static struct scc_dma_state scc_state_rd_36[] = { {-1} };
+static struct scc_dma_state scc_state_wr_36[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_37[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_37[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_38[] = { {0} };
+static struct scc_dma_state scc_state_wr_38[] = { {0} };
+static struct scc_dma_state scc_state_rd_39[] = { {0} };
+static struct scc_dma_state scc_state_wr_39[] = { {0} };
+static struct scc_dma_state scc_state_rd_40[] = { {-1} };
+static struct scc_dma_state scc_state_wr_40[] = { {-1} };
+
+/* DMA state references to access from the driver */
+static struct scc_dma_state *scc_state_rd[] = {
+	scc_state_rd_0,
+	scc_state_rd_1,
+	scc_state_rd_2,
+	scc_state_rd_3,
+	scc_state_rd_4,
+	scc_state_rd_5,
+	scc_state_rd_6,
+	scc_state_rd_7,
+	scc_state_rd_8,
+	scc_state_rd_9,
+	scc_state_rd_10,
+	scc_state_rd_11,
+	scc_state_rd_12,
+	scc_state_rd_13,
+	scc_state_rd_14,
+	scc_state_rd_15,
+	scc_state_rd_16,
+	scc_state_rd_17,
+	scc_state_rd_18,
+	scc_state_rd_19,
+	scc_state_rd_20,
+	scc_state_rd_21,
+	scc_state_rd_22,
+	scc_state_rd_23,
+	scc_state_rd_24,
+	scc_state_rd_25,
+	scc_state_rd_26,
+	scc_state_rd_27,
+	scc_state_rd_28,
+	scc_state_rd_29,
+	scc_state_rd_30,
+	scc_state_rd_31,
+	scc_state_rd_32,
+	scc_state_rd_33,
+	scc_state_rd_34,
+	scc_state_rd_35,
+	scc_state_rd_36,
+	scc_state_rd_37,
+	scc_state_rd_38,
+	scc_state_rd_39,
+	scc_state_rd_40,
+};
+
+static struct scc_dma_state *scc_state_wr[] = {
+	scc_state_wr_0,
+	scc_state_wr_1,
+	scc_state_wr_2,
+	scc_state_wr_3,
+	scc_state_wr_4,
+	scc_state_wr_5,
+	scc_state_wr_6,
+	scc_state_wr_7,
+	scc_state_wr_8,
+	scc_state_wr_9,
+	scc_state_wr_10,
+	scc_state_wr_11,
+	scc_state_wr_12,
+	scc_state_wr_13,
+	scc_state_wr_14,
+	scc_state_wr_15,
+	scc_state_wr_16,
+	scc_state_wr_17,
+	scc_state_wr_18,
+	scc_state_wr_19,
+	scc_state_wr_20,
+	scc_state_wr_21,
+	scc_state_wr_22,
+	scc_state_wr_23,
+	scc_state_wr_24,
+	scc_state_wr_25,
+	scc_state_wr_26,
+	scc_state_wr_27,
+	scc_state_wr_28,
+	scc_state_wr_29,
+	scc_state_wr_30,
+	scc_state_wr_31,
+	scc_state_wr_32,
+	scc_state_wr_33,
+	scc_state_wr_34,
+	scc_state_wr_35,
+	scc_state_wr_36,
+	scc_state_wr_37,
+	scc_state_wr_38,
+	scc_state_wr_39,
+	scc_state_wr_40,
+};
+
+static u32 scc_takeover_mode = SCC_TO_IMMEDIATE;
+
+/* Change mode of the SPDMA for given direction */
+static u32 scc_agu_mode_sp = AGU_BYPASS;
+
+/* Change mode of the USB for given direction */
+static u32 scc_agu_mode_usb = AGU_BYPASS;
+
+static union scc_softwareconfiguration scc_software_configuration[SCC_MAX];
+
+static u32 dma_fsm[4][4] = {
+	/* DMA_CMD_RESET  DMA_CMD_SETUP    DMA_CMD_START    DMA_CMD_STOP */
+	/* DMA_STATE_RESET */
+	{DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_ERROR, DMA_STATE_ERROR},
+	/* DMA_STATE_SETUP */
+	{DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_START, DMA_STATE_SETUP},
+	/* DMA_STATE_START */
+	{DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_START, DMA_STATE_SETUP},
+	/* DMA_STATE_ERROR */
+	{DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_ERROR, DMA_STATE_ERROR},
+};
+
+static void dma_state_process(struct scc_dma_state *dma_state, u32 cmd)
+{
+	dma_state->dma_status = dma_fsm[dma_state->dma_status][cmd];
+	dma_state->dma_cmd = cmd;
+}
+
+static void dma_state_process_dma_command(struct scc_dma_state *dma_state,
+					  u32 dma_cmd)
+{
+	dma_state->dma_cmd = dma_cmd;
+	switch (dma_cmd) {
+	case DMA_START:
+	case DMA_START_FH_RESET:
+		dma_state_process(dma_state, DMA_CMD_START);
+		break;
+	case DMA_STOP:
+		dma_state_process(dma_state, DMA_CMD_STOP);
+		break;
+	default:
+		break;
+	}
+}
+
+static void scc_takeover_dma(enum scc_id id, u32 dma_id, u32 drs)
+{
+	union scc_cmd dma_cmd;
+
+	dma_cmd.reg = 0;
+
+	/* Prepare the takeover for the DMA channel */
+	dma_cmd.bits.action = DMA_TAKEOVER;
+	dma_cmd.bits.id = dma_id;
+	dma_cmd.bits.rid = TO_DMA_CFG;	/* this is DMA_CFG register takeover */
+	if (drs == DMA_WRITE)
+		dma_cmd.bits.drs = DMA_WRITE;
+
+	reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
+}
+
+int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs)
+{
+	union scc_cmd dma_cmd;
+	struct scc_dma_state *dma_state;
+
+	if ((id >= SCC_MAX) || (id < 0))
+		return -EINVAL;
+
+	dma_cmd.reg = 0;
+
+	/* Prepare the takeover for the DMA channel */
+	dma_cmd.bits.action = cmd;
+	dma_cmd.bits.id = dma_id;
+	if (drs == DMA_WRITE) {
+		dma_cmd.bits.drs = DMA_WRITE;
+		dma_state = &scc_state_wr[id][dma_id];
+	} else {
+		dma_state = &scc_state_rd[id][dma_id];
+	}
+
+	dma_state->scc_id = id;
+	dma_state->dma_id = dma_id;
+	dma_state_process_dma_command(dma_state, cmd);
+
+	reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
+
+	return 0;
+}
+
+int scc_set_usb_address_generation_mode(u32 agu_mode)
+{
+	if (AGU_ACTIVE == agu_mode) {
+		/* Ensure both DMAs are stopped */
+		scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_WRITE);
+		scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_READ);
+	} else {
+		agu_mode = AGU_BYPASS;
+	}
+
+	scc_agu_mode_usb = agu_mode;
+
+	return 0;
+}
+
+int scc_setup_dma(enum scc_id id, u32 buffer_tag,
+		  u32 type, u32 fh_mode, u32 drs, u32 dma_id)
+{
+	struct scc_dma_state *dma_state;
+	int return_value = 0;
+	union scc_dma_cfg dma_cfg;
+	u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+	u32 tag_count, t, t_valid;
+
+	if ((id >= SCC_MAX) || (id < 0))
+		return -EINVAL;
+
+	/* if the register is only configured by hw, cannot write! */
+	if (1 == scc_descriptor_table[id].hw_dma_cfg)
+		return -EACCES;
+
+	if (DMA_WRITE == drs) {
+		if (dma_id >= scc_descriptor_table[id].p_dma_channels_wr)
+			return -EINVAL;
+		dma_state = &scc_state_wr[id][dma_id];
+	} else {
+		if (dma_id >= scc_descriptor_table[id].p_dma_channels_rd)
+			return -EINVAL;
+		dma_state = &scc_state_rd[id][dma_id];
+	}
+
+	/* Compose the DMA configuration register */
+	tag_count = buffer_tag_list[0];
+	t_valid = 0;
+	for (t = 1; t <= tag_count; t++) {
+		if (buffer_tag == buffer_tag_list[t]) {
+			/* Tag found - validate */
+			t_valid = 1;
+			break;
+		}
+	}
+
+	if (!t_valid)
+		return -EACCES;
+
+	/*
+	 * Read the register first -- two functions write into the register
+	 * it does not make sense to read the DMA config back, because there
+	 * are two register configuration sets (drs)
+	 */
+	dma_cfg.reg = 0;
+	dma_cfg.bits.buffer_id = buffer_tag;
+	dma_state_process(dma_state, DMA_CMD_SETUP);
+
+	/*
+	 * This is Packet CFG set select - usable for TSIO, EBI and those SCCs
+	 * which habe 2 packet configs
+	 */
+	dma_cfg.bits.packet_cfg_id =
+		scc_software_configuration[id].bits.packet_select;
+
+	if (type == DMA_CYCLIC)
+		dma_cfg.bits.buffer_type = 1;
+	else
+		dma_cfg.bits.buffer_type = 0;
+
+	if (fh_mode == USE_FH)
+		dma_cfg.bits.fh_mode = 1;
+	else
+		dma_cfg.bits.fh_mode = 0;
+
+	if (id == SCC_CPU1_SPDMA_RW)
+		dma_cfg.bits.agu_mode = scc_agu_mode_sp;
+
+	if (id == SCC_USB_RW)
+		dma_cfg.bits.agu_mode = scc_agu_mode_usb;
+
+	reg_write(SCC_DMA_CFG(scc_descriptor_table[id].base_address),
+		  dma_cfg.reg);
+
+	/* The DMA_CFG needs a takeover! */
+	if (SCC_TO_IMMEDIATE == scc_takeover_mode)
+		scc_takeover_dma(id, dma_id, drs);
+
+	/* if (buffer_tag is not used) */
+	dma_state->buffer_tag = buffer_tag;
+
+	dma_state->scc_id = id;
+	dma_state->dma_id = dma_id;
+
+	return return_value;
+}
+
+int scc_enable(enum scc_id id, u32 value)
+{
+	if ((id >= SCC_MAX) || (id < 0))
+		return -EINVAL;
+
+	if (value == 0) {
+		scc_software_configuration[id].bits.enable_status = 0;
+	} else {
+		value = 1;
+		scc_software_configuration[id].bits.enable_status = 1;
+	}
+	reg_write(SCC_ENABLE(scc_descriptor_table[id].base_address), value);
+
+	return 0;
+}
+
+static inline void ehb(void)
+{
+	__asm__ __volatile__(
+		"	.set	mips32r2	\n"
+		"	ehb			\n"
+		"	.set	mips0		\n");
+}
+
+int scc_reset(enum scc_id id, u32 value)
+{
+	if ((id >= SCC_MAX) || (id < 0))
+		return -EINVAL;
+
+	/* Invert value to the strait logic from the negative hardware logic */
+	if (value == 0)
+		value = 1;
+	else
+		value = 0;
+
+	/* Write the value to the register */
+	reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value);
+
+	/* sync flush */
+	asm("sync");	/* request bus write queue flush */
+	ehb();		/* wait until previous bus commit instr has finished */
+	asm("nop");	/* wait for flush to occur */
+	asm("nop");	/* wait for flush to occur */
+
+	udelay(100);
+
+	return 0;
+}
diff --git a/u-boot/board/micronas/vct/scc.h b/u-boot/board/micronas/vct/scc.h
new file mode 100644
index 0000000..8415167
--- /dev/null
+++ b/u-boot/board/micronas/vct/scc.h
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCC_H
+#define _SCC_H
+
+#define DMA_READ		0	/* SCC read  DMA		*/
+#define DMA_WRITE		1	/* SCC write DMA		*/
+
+#define DMA_LINEAR		0	/* DMA linear buffer access method */
+#define DMA_CYCLIC		1	/* DMA cyclic buffer access method */
+
+#define DMA_START		0	/* DMA command - start DMA	*/
+#define DMA_STOP		1	/* DMA command - stop  DMA	*/
+#define DMA_START_FH_RESET	2	/* DMA command - start DMA reset FH */
+#define DMA_TAKEOVER		15	/* DMA command - commit the DMA conf */
+
+#define AGU_ACTIVE		0	/* enable AGU address calculation */
+#define AGU_BYPASS		1	/* set AGU to bypass mode	*/
+
+#define USE_NO_FH		0	/* order the DMA to not use FH	*/
+#define USE_FH			1	/* order the DMA to work with FH*/
+
+#define SCC_DBG_IDLE		0	/* DEBUG status (idle interfaces) */
+#define SCC_DBG_SYNC_RES	0x0001	/* synchronuous reset		*/
+
+#define SCC_TO_IMMEDIATE	1	/* takeover command issued immediately*/
+#define TO_DMA_CFG		2	/* takeover command for the DMA config*/
+
+#define DMA_CMD_RESET		0
+#define DMA_CMD_SETUP		1
+#define DMA_CMD_START		2
+#define DMA_CMD_STOP		3
+
+#define DMA_STATE_RESET		0
+#define DMA_STATE_SETUP		1
+#define DMA_STATE_START		2
+#define DMA_STATE_ERROR		3
+
+#define SRMD			0
+#define STRM_D			1
+#define STRM_P			2
+
+/*
+ * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks)
+ */
+#define RESET_TIME		2	/* cycle calc see in SCC_Reset	*/
+
+struct scc_descriptor {
+	char *pu_name;		/* PU identifier			*/
+	char *scc_instance;	/* SCC Name				*/
+	u32 profile;		/* SCC VCI_D profile			*/
+
+	u32 base_address;	/* base address of the SCC unit reg shell*/
+
+	/* SCS Interconnect configuration */
+	u32 p_scc_id;		/* instance number of SCC unit		*/
+	u32 p_mci_id;		/* memory channel ID			*/
+
+	/* DMA Registers configuration */
+	u32 p_dma_channels_rd;	/* Number of Read DMA channels		*/
+	u32 p_dma_channels_wr;	/* Number of Write DMA channels		*/
+
+	u32 p_dma_packet_desc;	/* Number of packet descriptors		*/
+	u32 p_dma_mci_desc;	/* Number of MCI_CFG Descriptors	*/
+
+	int use_fh;		/* the flag tells if SCC uses an FH	*/
+
+	int p_si2ocp_id;	/* instance number of SI2OCP unit	*/
+	int hw_dma_cfg;		/* HW or SW DMA config flag		*/
+	int hw_dma_start;	/* HW or SW DMA start/stop flag		*/
+
+	u32 *buffer_tag_list;	/* list of the buffer tags available	*/
+	u32 *csize_list;	/* list of the valid CSIZE values	*/
+};
+
+struct scc_dma_state {
+	u32 scc_id:8;		/* SCC id				*/
+	u32 dma_id:8;		/* DMA id, used for match with array idx*/
+	u32 buffer_tag:8;	/* mem buf tag, assigned to this DMA	*/
+	u32 dma_status:2;	/* state of DMA, of the DMA_STATE_ const*/
+	u32 dma_drs:2;		/* DMA dir, either DMA_READ or DMA_WRITE*/
+	u32 dma_cmd:4;		/* last executed command on this DMA	*/
+};
+
+union scc_cmd {
+	u32 reg;
+	struct {
+		u32 res1:19;	/* reserved				*/
+		u32 drs:1;	/* DMA Register Set			*/
+		u32 rid:2;	/* Register Identifier			*/
+		u32 id:6;	/* DMA Identifier			*/
+		u32 action:4;	/* DMA Command encoding			*/
+	} bits;
+};
+
+union scc_dma_cfg {
+	u32 reg;
+	struct {
+		u32 res1:17;		/* reserved			*/
+		u32 agu_mode:1;		/* AGU Mode			*/
+		u32 res2:1;		/* reserved			*/
+		u32 fh_mode:1;		/* Fifo Handler			*/
+		u32 buffer_type:1;	/* Defines type of mem buffers	*/
+		u32 mci_cfg_id:1;	/* MCI_CFG register selector	*/
+		u32 packet_cfg_id:1;	/* PACKET_CFG register selector	*/
+		u32 buffer_id:8;	/* DMA Buffer Identifier	*/
+	} bits;
+};
+
+union scc_debug {
+	u32 reg;
+	struct {
+		u32 res1:20;	/* reserved				*/
+		u32 arg:8;	/* SCC Debug Command Argument (#)	*/
+		u32 cmd:4;	/* SCC Debug Command Register		*/
+	} bits;
+};
+
+union scc_softwareconfiguration {
+	u32 reg;
+	struct {
+		u32 res1:28;		/* reserved			*/
+		u32 clock_status:1;	/* clock on/off			*/
+		u32 packet_select:1;	/* active SCC packet id		*/
+		u32 enable_status:1;	/* enabled [1/0]		*/
+		u32 active_status:1;	/* 1=active  0=reset		*/
+	} bits;
+};
+
+/*
+ * System on Chip Channel ID
+ */
+enum scc_id {
+	SCC_NULL = -1,		/* illegal SCC identifier		*/
+	SCC_FE_3DCOMB_WR,	/* SCC_FE_3DCOMB Write channel		*/
+	SCC_FE_3DCOMB_RD,	/* SCC_FE_3DCOMB Read channel		*/
+	SCC_DI_TNR_WR,		/* SCC_DI_TNR Write channel		*/
+	SCC_DI_TNR_FIELD_RD,	/* SCC_DI_TNR_FIELD Read channel	*/
+	SCC_DI_TNR_FRAME_RD,	/* SCC_DI_TNR_FRAME Read channel	*/
+	SCC_DI_MVAL_WR,		/* SCC_DI_MVAL Write channel		*/
+	SCC_DI_MVAL_RD,		/* SCC_DI_MVAL Read channel		*/
+	SCC_RC_FRAME_WR,	/* SCC_RC_FRAME Write channel		*/
+	SCC_RC_FRAME0_RD,	/* SCC_RC_FRAME0 Read channel		*/
+	SCC_OPT_FIELD0_RD,	/* SCC_OPT_FIELD0 Read channel		*/
+	SCC_OPT_FIELD1_RD,	/* SCC_OPT_FIELD1 Read channel		*/
+	SCC_OPT_FIELD2_RD,	/* SCC_OPT_FIELD2 Read channel		*/
+	SCC_PIP_FRAME_WR,	/* SCC_PIP_FRAME Write channel		*/
+	SCC_PIP_FRAME_RD,	/* SCC_PIP_FRAME Read channel		*/
+	SCC_DP_AGPU_RD,		/* SCC_DP_AGPU Read channel		*/
+	SCC_EWARP_RW,		/* SCC_EWARP Read/Write channel		*/
+	SCC_DP_OSD_RD,		/* SCC_DP_OSD Read channel		*/
+	SCC_DP_GRAPHIC_RD,	/* SCC_DP_GRAPHIC Read channel		*/
+	SCC_DVP_OSD_RD,		/* SCC_DVP_OSD Read channel		*/
+	SCC_DVP_VBI_RD,		/* SCC_DVP_VBI Read channel		*/
+	SCC_TSIO_WR,		/* SCC_TSIO Write channel		*/
+	SCC_TSIO_RD,		/* SCC_TSIO Read channel		*/
+	SCC_TSD_WR,		/* SCC_TSD Write channel		*/
+	SCC_VD_UD_ST_RW,	/* SCC_VD_UD_ST Read/Write channel	*/
+	SCC_VD_FRR_RD,		/* SCC_VD_FRR Read channel		*/
+	SCC_VD_FRW_DISP_WR,	/* SCC_VD_FRW_DISP Write channel	*/
+	SCC_MR_VD_M_Y_RD,	/* SCC_MR_VD_M_Y Read channel		*/
+	SCC_MR_VD_M_C_RD,	/* SCC_MR_VD_M_C Read channel		*/
+	SCC_MR_VD_S_Y_RD,	/* SCC_MR_VD_S_Y Read channel		*/
+	SCC_MR_VD_S_C_RD,	/* SCC_MR_VD_S_C Read channel		*/
+	SCC_GA_WR,		/* SCC_GA Write channel			*/
+	SCC_GA_SRC1_RD,		/* SCC_GA_SRC1 Read channel		*/
+	SCC_GA_SRC2_RD,		/* SCC_GA_SRC2 Read channel		*/
+	SCC_AD_RD,		/* SCC_AD Read channel			*/
+	SCC_AD_WR,		/* SCC_AD Write channel			*/
+	SCC_ABP_RD,		/* SCC_ABP Read channel			*/
+	SCC_ABP_WR,		/* SCC_ABP Write channel		*/
+	SCC_EBI_RW,		/* SCC_EBI Read/Write channel		*/
+	SCC_USB_RW,		/* SCC_USB Read/Write channel		*/
+	SCC_CPU1_SPDMA_RW,	/* SCC_CPU1_SPDMA Read/Write channel	*/
+	SCC_CPU1_BRIDGE_RW,	/* SCC_CPU1_BRIDGE Read/Write channel	*/
+	SCC_MAX			/* maximum limit on the SCC id		*/
+};
+
+int scc_set_usb_address_generation_mode(u32 agu_mode);
+int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs);
+int scc_setup_dma(enum scc_id id, u32 buffer_tag,
+		  u32 type, u32 fh_mode, u32 drs, u32 dma_id);
+int scc_enable(enum scc_id id, u32 value);
+int scc_reset(enum scc_id id, u32 value);
+
+#endif /* _SCC_H */
diff --git a/u-boot/board/micronas/vct/smc_eeprom.c b/u-boot/board/micronas/vct/smc_eeprom.c
new file mode 100644
index 0000000..b5a5521
--- /dev/null
+++ b/u-boot/board/micronas/vct/smc_eeprom.c
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright 2005, Seagate Technology LLC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+
+#include "vct.h"
+
+#define SMSC9118_BASE		CONFIG_DRIVER_SMC911X_BASE
+#define BYTE_TEST		(SMSC9118_BASE + 0x64)
+#define GPIO_CFG		(SMSC9118_BASE + 0x88)
+#define MAC_CSR_CMD		(SMSC9118_BASE + 0xA4)
+#define  MAC_CSR_CMD_CSR_BUSY	(0x80000000)
+#define  MAC_CSR_CMD_RNW	(0x40000000)
+#define  MAC_RD_CMD(reg)	((reg & 0x000000FF) |			\
+				 (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW))
+#define  MAC_WR_CMD(reg)	((reg & 0x000000FF) |		\
+				 (MAC_CSR_CMD_CSR_BUSY))
+#define MAC_CSR_DATA		(SMSC9118_BASE + 0xA8)
+#define E2P_CMD			(SMSC9118_BASE + 0xB0)
+#define  E2P_CMD_EPC_BUSY_	(0x80000000UL)	/* Self Clearing */
+#define  E2P_CMD_EPC_CMD_	(0x70000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_READ_	(0x00000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_EWDS_	(0x10000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_EWEN_	(0x20000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_WRITE_	(0x30000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_WRAL_	(0x40000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_ERASE_	(0x50000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_ERAL_	(0x60000000UL)	/* R/W */
+#define  E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL)	/* R/W */
+#define  E2P_CMD_EPC_TIMEOUT_	(0x00000200UL)	/* R */
+#define  E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */
+#define  E2P_CMD_EPC_ADDR_	(0x000000FFUL)	/* R/W */
+#define E2P_DATA		(SMSC9118_BASE + 0xB4)
+
+#define MAC_ADDRH		(0x2)
+#define MAC_ADDRL		(0x3)
+
+#define MAC_TIMEOUT		200
+
+#define HIBYTE(word)		((u8)(((u16)(word)) >> 8))
+#define LOBYTE(word)		((u8)(((u16)(word)) & 0x00FFU))
+#define HIWORD(dword)		((u16)(((u32)(dword)) >> 16))
+#define LOWORD(dword)		((u16)(((u32)(dword)) & 0x0000FFFFUL))
+
+static int mac_busy(int req_to)
+{
+	int timeout = req_to;
+
+	while (timeout--) {
+		if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
+			goto done;
+	}
+	return 1;		/* Timeout */
+
+done:
+	return 0;		/* No timeout */
+}
+
+static ulong get_mac_reg(int reg)
+{
+	ulong reg_val = 0xffffffff;
+
+	if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) {
+		printf("get_mac_reg: previous command not complete\n");
+		goto done;
+	}
+
+	smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg));
+	udelay(10000);
+
+	if (mac_busy(MAC_TIMEOUT) == 1) {
+		printf("get_mac_reg: timeout waiting for response from MAC\n");
+		goto done;
+	}
+
+	reg_val = smc911x_reg_read(MAC_CSR_DATA);
+
+done:
+	return (reg_val);
+}
+
+static ulong eeprom_enable_access(void)
+{
+	ulong gpio;
+
+	gpio = smc911x_reg_read(GPIO_CFG);
+	debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio,
+	      (gpio & 0xFF0FFFFFUL));
+
+	smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL));
+	return gpio;
+}
+
+static void eeprom_disable_access(ulong gpio)
+{
+	debug("%s: gpio= 0x%08lx\n", __func__, gpio);
+	smc911x_reg_write(GPIO_CFG, gpio);
+}
+
+static int eeprom_is_mac_address_loaded(void)
+{
+	int ret;
+
+	ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_;
+	debug("%s: ret = %x\n", __func__, ret);
+
+	return ret;
+}
+
+static int eeprom_read_location(unchar address, u8 *data)
+{
+	ulong timeout = 100000;
+	ulong temp = 0;
+
+	if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) {
+		printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp);
+		return 0;
+	}
+
+	smc911x_reg_write(E2P_CMD,
+			  (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ |
+			   ((ulong) address)));
+
+	while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+		udelay(10);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		printf("Timeout\n");
+		return 0;
+	}
+	(*data) = (unchar) (smc911x_reg_read(E2P_DATA));
+	debug("%s: ret = %x\n", __func__, (*data));
+
+	return 1;
+}
+
+static int eeprom_enable_erase_and_write(void)
+{
+	ulong timeout = 100000;
+
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+		printf("%s: Busy at start\n", __func__);
+		return 0;
+	}
+	smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_));
+
+	while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+		udelay(10);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		printf("Timeout[1]\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+static int eeprom_disable_erase_and_write(void)
+{
+	ulong timeout = 100000;
+
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+		printf("%s: Busy at start\n", __func__);
+		return 0;
+	}
+	smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_));
+
+	while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+		udelay(10);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		printf("Timeout[2]\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+static int eeprom_write_location(unchar address, unchar data)
+{
+	ulong timeout = 100000;
+
+	debug("%s: address: %x data = %x\n", __func__, address, data);
+
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+		printf("%s: Busy at start\n", __func__);
+		return 0;
+	}
+
+	smc911x_reg_write(E2P_DATA, ((ulong) data));
+	smc911x_reg_write(E2P_CMD,
+			  (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ |
+			   ((ulong) address)));
+
+	while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+		udelay(10);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		printf("Timeout[3]\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+static int eeprom_erase_all(void)
+{
+	ulong timeout = 100000;
+
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+		printf("%s: Busy at start\n", __func__);
+		return 0;
+	}
+
+	smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_));
+
+	while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+		udelay(10);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		printf("Timeout[4]\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+static int eeprom_reload(void)
+{
+	ulong timeout = 100000;
+
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+		printf("%s: Busy at start\n", __func__);
+		return -1;
+	}
+	smc911x_reg_write(E2P_CMD,
+			  (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
+
+	while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+		udelay(10);
+		timeout--;
+	}
+
+	if (timeout == 0)
+		return 0;
+
+	return 1;
+}
+
+static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32)
+{
+	int result = 0;
+
+	debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32);
+
+	if (!eeprom_enable_erase_and_write())
+		goto DONE;
+	if (!eeprom_erase_all())
+		goto DONE;
+	if (!eeprom_write_location(0, 0xA5))
+		goto DONE;
+	if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32))))
+		goto DONE;
+	if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32))))
+		goto DONE;
+	if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32))))
+		goto DONE;
+	if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32))))
+		goto DONE;
+	if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16))))
+		goto DONE;
+	if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16))))
+		goto DONE;
+	if (!eeprom_disable_erase_and_write())
+		goto DONE;
+
+	result = 1;
+
+DONE:
+	return result;
+}
+
+static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unchar data = 0, index = 0;
+	ulong gpio_old_val;
+
+	gpio_old_val = eeprom_enable_access();
+
+	printf("EEPROM content: \n");
+	for (index = 0; index < 8; index++) {
+		if (eeprom_read_location(index, &data))
+			printf("%02x ", data);
+		else
+			printf("FAILED");
+	}
+
+	eeprom_disable_access(gpio_old_val);
+	printf("\n");
+
+	return 0;
+}
+
+static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	eeprom_erase_all();
+
+	return 0;
+}
+
+static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong hi16, lo32;
+	unchar ethaddr[6], i;
+	ulong gpio;
+	char *tmp, *end;
+
+	tmp = argv[1];
+	for (i = 0; i < 6; i++) {
+		ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+		if (tmp)
+			tmp = (*end) ? end + 1 : end;
+	}
+
+	hi16 = (ethaddr[5] << 8) | (ethaddr[4]);
+	lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) |
+		(ethaddr[1] << 8) | (ethaddr[0]);
+
+	gpio = eeprom_enable_access();
+
+	eeprom_save_mac_address(hi16, lo32);
+
+	eeprom_reload();
+
+	/* Check new values */
+	if (eeprom_is_mac_address_loaded()) {
+		ulong mac_hi16, mac_lo32;
+
+		mac_hi16 = get_mac_reg(MAC_ADDRH);
+		mac_lo32 = get_mac_reg(MAC_ADDRL);
+		printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32);
+	} else {
+		printf("Address is not reloaded \n");
+	}
+	eeprom_disable_access(gpio);
+
+	return 0;
+}
+
+U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all,
+	   "smcee   - Erase content of SMC EEPROM",);
+
+U_BOOT_CMD(smced, 1, 0, do_eeprom_dump,
+	   "smced   - Dump content of SMC EEPROM",);
+
+U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac,
+	   "smcew   - Write MAC address to SMC EEPROM\n",
+	   "aa:bb:cc:dd:ee:ff  new mac address");
diff --git a/u-boot/board/micronas/vct/top.c b/u-boot/board/micronas/vct/top.c
new file mode 100644
index 0000000..0923954
--- /dev/null
+++ b/u-boot/board/micronas/vct/top.c
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "vct.h"
+
+typedef union _TOP_PINMUX_t
+{
+	u32 reg;
+	struct {
+		u32 res		: 24;   /* reserved		*/
+		u32 drive	:  2;   /* Driver strength	*/
+		u32 slew	:  1;   /* Slew rate		*/
+		u32 strig	:  1;   /* Schmitt trigger input*/
+		u32 pu_pd	:  2;   /* Pull up/ pull down	*/
+		u32 funsel	:  2;   /* Pin function		*/
+	} Bits;
+} TOP_PINMUX_t;
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+
+static TOP_PINMUX_t top_read_pin(int pin)
+{
+	TOP_PINMUX_t reg;
+
+	switch (pin) {
+	case 2:
+	case 3:
+	case 6:
+	case 9:
+		reg.reg = 0xdeadbeef;
+		break;
+	case 4:
+		reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
+		break;
+	case 5:
+		reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
+		break;
+	case 7:
+		reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
+		break;
+	case 8:
+		reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
+		break;
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+	case 16:
+		reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
+				   ((pin - 10) * 4));
+		break;
+	default:
+		reg.reg = reg_read(TOP_BASE + (pin * 4));
+		break;
+	}
+
+	return reg;
+}
+
+static void top_write_pin(int pin, TOP_PINMUX_t reg)
+{
+
+	switch (pin) {
+	case 4:
+		reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
+		break;
+	case 5:
+		reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
+		break;
+	case 7:
+		reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
+		break;
+	case 8:
+		reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
+		break;
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+	case 16:
+		reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
+			  ((pin - 10) * 4), reg.reg);
+		break;
+	default:
+		reg_write(TOP_BASE + (pin * 4), reg.reg);
+		break;
+	}
+}
+
+int top_set_pin(int pin, int func)
+{
+	TOP_PINMUX_t reg;
+
+	/* check global range */
+	if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
+		return -1;  /* pin number or function out of valid range */
+
+	/* check undefined values; */
+	if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
+		return -1;  /* pin number out of valid range */
+
+	reg = top_read_pin(pin);
+	reg.Bits.funsel = func;
+	top_write_pin(pin, reg);
+
+	return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VCT_PLATINUMAVC)
+
+int top_set_pin(int pin, int func)
+{
+	TOP_PINMUX_t reg;
+
+	/* check global range */
+	if ((pin < 0) || (pin > 158))
+		return -1;	/* pin number or function out of valid range */
+
+	reg.reg = reg_read(TOP_BASE + (pin * 4));
+	reg.Bits.funsel = func;
+	reg_write(TOP_BASE + (pin * 4), reg.reg);
+
+	return 0;
+}
+
+#endif
+
+void vct_pin_mux_initialize(void)
+{
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+	top_set_pin(34, 01);	/* EBI_CS0	*/
+	top_set_pin(33, 01);	/* EBI_CS1	*/
+	top_set_pin(32, 01);	/* EBI_CS2	*/
+	top_set_pin(100, 02);	/* EBI_CS3	*/
+	top_set_pin(101, 02);	/* EBI_CS4	*/
+	top_set_pin(102, 02);	/* EBI_CS5	*/
+	top_set_pin(103, 02);	/* EBI_CS6	*/
+	top_set_pin(104, 02);	/* EBI_CS7	top_set_pin(104,03); EBI_GENIO3 */
+	top_set_pin(35, 01);	/* EBI_ALE	*/
+	top_set_pin(36, 01);	/* EBI_ADDR15	*/
+	top_set_pin(37, 01);	/* EBI_ADDR14	top_set_pin(78,03); EBI_ADDR14 */
+	top_set_pin(38, 01);	/* EBI_ADDR13	*/
+	top_set_pin(39, 01);	/* EBI_ADDR12	*/
+	top_set_pin(40, 01);	/* EBI_ADDR11	*/
+	top_set_pin(41, 01);	/* EBI_ADDR10	*/
+	top_set_pin(42, 01);	/* EBI_ADDR9	*/
+	top_set_pin(43, 01);	/* EBI_ADDR8	*/
+	top_set_pin(44, 01);	/* EBI_ADDR7	*/
+	top_set_pin(45, 01);	/* EBI_ADDR6	*/
+	top_set_pin(46, 01);	/* EBI_ADDR5	*/
+	top_set_pin(47, 01);	/* EBI_ADDR4	*/
+	top_set_pin(48, 01);	/* EBI_ADDR3	*/
+	top_set_pin(49, 01);	/* EBI_ADDR2	*/
+	top_set_pin(50, 01);	/* EBI_ADDR1	*/
+	top_set_pin(51, 01);	/* EBI_ADDR0	*/
+	top_set_pin(52, 01);	/* EBI_DIR	*/
+	top_set_pin(53, 01);	/* EBI_DAT15	top_set_pin(81,01); EBI_DAT15 */
+	top_set_pin(54, 01);	/* EBI_DAT14	top_set_pin(82,01); EBI_DAT14 */
+	top_set_pin(55, 01);	/* EBI_DAT13	top_set_pin(83,01); EBI_DAT13 */
+	top_set_pin(56, 01);	/* EBI_DAT12	top_set_pin(84,01); EBI_DAT12 */
+	top_set_pin(57, 01);	/* EBI_DAT11	top_set_pin(85,01); EBI_DAT11 */
+	top_set_pin(58, 01);	/* EBI_DAT10	top_set_pin(86,01); EBI_DAT10 */
+	top_set_pin(59, 01);	/* EBI_DAT9	top_set_pin(87,01); EBI_DAT9 */
+	top_set_pin(60, 01);	/* EBI_DAT8	top_set_pin(88,01); EBI_DAT8 */
+	top_set_pin(61, 01);	/* EBI_DAT7	*/
+	top_set_pin(62, 01);	/* EBI_DAT6	*/
+	top_set_pin(63, 01);	/* EBI_DAT5	*/
+	top_set_pin(64, 01);	/* EBI_DAT4	*/
+	top_set_pin(65, 01);	/* EBI_DAT3	*/
+	top_set_pin(66, 01);	/* EBI_DAT2	*/
+	top_set_pin(67, 01);	/* EBI_DAT1	*/
+	top_set_pin(68, 01);	/* EBI_DAT0	*/
+	top_set_pin(69, 01);	/* EBI_IORD	*/
+	top_set_pin(70, 01);	/* EBI_IOWR	*/
+	top_set_pin(71, 01);	/* EBI_WE	*/
+	top_set_pin(72, 01);	/* EBI_OE	*/
+	top_set_pin(73, 01);	/* EBI_IORDY	*/
+	top_set_pin(95, 02);	/* EBI_EBI_DMACK*/
+	top_set_pin(112, 02);	/* EBI_IRQ0	*/
+	top_set_pin(111, 02);	/* EBI_IRQ1	top_set_pin(111,03); EBI_DMARQ */
+	top_set_pin(107, 02);	/* EBI_IRQ2	*/
+	top_set_pin(108, 02);	/* EBI_IRQ3	*/
+	top_set_pin(30, 01);	/* EBI_GENIO1   top_set_pin(99,03); EBI_GENIO1 */
+	top_set_pin(31, 01);	/* EBI_GENIO2   top_set_pin(98,03); EBI_GENIO2 */
+	top_set_pin(105, 02);	/* EBI_GENIO3   top_set_pin(104,03); EBI_GENIO3 */
+	top_set_pin(106, 02);	/* EBI_GENIO4   top_set_pin(144,02); EBI_GENIO4 */
+	top_set_pin(109, 02);	/* EBI_GENIO5   top_set_pin(142,02); EBI_GENIO5 */
+	top_set_pin(110, 02);	/* EBI_BURST_CLK	*/
+#endif
+
+#if defined(CONFIG_VCT_PLATINUMAVC)
+	top_set_pin(19, 01);	/* EBI_CS0	*/
+	top_set_pin(18, 01);	/* EBI_CS1	*/
+	top_set_pin(17, 01);	/* EBI_CS2	*/
+	top_set_pin(92, 02);	/* EBI_CS3	*/
+	top_set_pin(93, 02);	/* EBI_CS4	*/
+	top_set_pin(95, 02);	/* EBI_CS6	*/
+	top_set_pin(96, 02);	/* EBI_CS7	top_set_pin(104,03); EBI_GENIO3 */
+	top_set_pin(20, 01);	/* EBI_ALE	*/
+	top_set_pin(21, 01);	/* EBI_ADDR15	*/
+	top_set_pin(22, 01);	/* EBI_ADDR14	top_set_pin(78,03); EBI_ADDR14 */
+	top_set_pin(23, 01);	/* EBI_ADDR13	*/
+	top_set_pin(24, 01);	/* EBI_ADDR12	*/
+	top_set_pin(25, 01);	/* EBI_ADDR11	*/
+	top_set_pin(26, 01);	/* EBI_ADDR10	*/
+	top_set_pin(27, 01);	/* EBI_ADDR9	*/
+	top_set_pin(28, 01);	/* EBI_ADDR8	*/
+	top_set_pin(29, 01);	/* EBI_ADDR7	*/
+	top_set_pin(30, 01);	/* EBI_ADDR6	*/
+	top_set_pin(31, 01);	/* EBI_ADDR5	*/
+	top_set_pin(32, 01);	/* EBI_ADDR4	*/
+	top_set_pin(33, 01);	/* EBI_ADDR3	*/
+	top_set_pin(34, 01);	/* EBI_ADDR2	*/
+	top_set_pin(35, 01);	/* EBI_ADDR1	*/
+	top_set_pin(36, 01);	/* EBI_ADDR0	*/
+	top_set_pin(37, 01);	/* EBI_DIR	*/
+	top_set_pin(38, 01);	/* EBI_DAT15	top_set_pin(81,01); EBI_DAT15 */
+	top_set_pin(39, 01);	/* EBI_DAT14	top_set_pin(82,01); EBI_DAT14 */
+	top_set_pin(40, 01);	/* EBI_DAT13	top_set_pin(83,01); EBI_DAT13 */
+	top_set_pin(41, 01);	/* EBI_DAT12	top_set_pin(84,01); EBI_DAT12 */
+	top_set_pin(42, 01);	/* EBI_DAT11	top_set_pin(85,01); EBI_DAT11 */
+	top_set_pin(43, 01);	/* EBI_DAT10	top_set_pin(86,01); EBI_DAT10 */
+	top_set_pin(44, 01);	/* EBI_DAT9	top_set_pin(87,01); EBI_DAT9 */
+	top_set_pin(45, 01);	/* EBI_DAT8	top_set_pin(88,01); EBI_DAT8 */
+	top_set_pin(46, 01);	/* EBI_DAT7	*/
+	top_set_pin(47, 01);	/* EBI_DAT6	*/
+	top_set_pin(48, 01);	/* EBI_DAT5	*/
+	top_set_pin(49, 01);	/* EBI_DAT4	*/
+	top_set_pin(50, 01);	/* EBI_DAT3	*/
+	top_set_pin(51, 01);	/* EBI_DAT2	*/
+	top_set_pin(52, 01);	/* EBI_DAT1	*/
+	top_set_pin(53, 01);	/* EBI_DAT0	*/
+	top_set_pin(54, 01);	/* EBI_IORD	*/
+	top_set_pin(55, 01);	/* EBI_IOWR	*/
+	top_set_pin(56, 01);	/* EBI_WE	*/
+	top_set_pin(57, 01);	/* EBI_OE	*/
+	top_set_pin(58, 01);	/* EBI_IORDY	*/
+	top_set_pin(87, 02);	/* EBI_EBI_DMACK*/
+	top_set_pin(106, 02);	/* EBI_IRQ0	*/
+	top_set_pin(105, 02);	/* EBI_IRQ1	top_set_pin(111,03); EBI_DMARQ */
+	top_set_pin(101, 02);	/* EBI_IRQ2	*/
+	top_set_pin(102, 02);	/* EBI_IRQ3	*/
+	top_set_pin(15, 01);	/* EBI_GENIO1   top_set_pin(99,03); EBI_GENIO1 */
+	top_set_pin(16, 01);	/* EBI_GENIO2   top_set_pin(98,03); EBI_GENIO2 */
+	top_set_pin(99, 02);	/* EBI_GENIO3   top_set_pin(104,03); EBI_GENIO3 */
+	top_set_pin(100, 02);	/* EBI_GENIO4   top_set_pin(144,02); EBI_GENIO4 */
+	top_set_pin(103, 02);	/* EBI_GENIO5   top_set_pin(142,02); EBI_GENIO5 */
+	top_set_pin(104, 02);	/* EBI_BURST_CLK	*/
+#endif
+
+	/* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
+	top_set_pin(0, 2);	/* SCL2 on GPIO 11 */
+	top_set_pin(1, 2);	/* SDA2 on GPIO 10 */
+
+	/* UART pins */
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+	top_set_pin(141, 1);
+	top_set_pin(143, 1);
+#endif
+#if defined(CONFIG_VCT_PLATINUMAVC)
+	top_set_pin(107, 1);
+	top_set_pin(109, 1);
+#endif
+}
diff --git a/u-boot/board/micronas/vct/u-boot.lds b/u-boot/board/micronas/vct/u-boot.lds
new file mode 100644
index 0000000..b90b186
--- /dev/null
+++ b/u-boot/board/micronas/vct/u-boot.lds
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	. = ALIGN(4);
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	. = ALIGN(4);
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	. = ALIGN(4);
+	.bss (NOLOAD)  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/u-boot/board/micronas/vct/vct.c b/u-boot/board/micronas/vct/vct.c
new file mode 100644
index 0000000..7fc3507
--- /dev/null
+++ b/u-boot/board/micronas/vct/vct.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include "vct.h"
+
+#if defined(CONFIG_VCT_PREMIUM)
+#define BOARD_NAME	"PremiumD"
+#elif defined(CONFIG_VCT_PLATINUM)
+#define BOARD_NAME	"PlatinumD"
+#elif defined(CONFIG_VCT_PLATINUMAVC)
+#define BOARD_NAME	"PlatinumAVC"
+#else
+#error "vct: No board variant defined!"
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+#define BOARD_NAME_ADD	" OneNAND"
+#else
+#define BOARD_NAME_ADD	" NOR"
+#endif
+
+int board_early_init_f(void)
+{
+	/*
+	 * First initialize the PIN mulitplexing
+	 */
+	vct_pin_mux_initialize();
+
+	/*
+	 * Init the EBI very early so that FLASH can be accessed
+	 */
+	ebi_initialize();
+
+	return 0;
+}
+
+void _machine_restart(void)
+{
+	reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
+	reg_write(WDT_TORR(WDT_BASE), 0x00);
+	reg_write(WDT_CR(WDT_BASE), 0x1D);
+
+	/*
+	 * Now wait for the watchdog to trigger the reset
+	 */
+	udelay(1000000);
+}
+
+/*
+ * SDRAM is already configured by the bootstrap code, only return the
+ * auto-detected size here
+ */
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+			    CONFIG_SYS_MBYTES_SDRAM << 20);
+}
+
+int checkboard(void)
+{
+	u32 config0 = read_c0_prid();
+	char *s = getenv("serial#");
+
+	if ((config0 & 0xff0000) == PRID_COMP_LEGACY
+	    && (config0 & 0xff00) == PRID_IMP_LX4280) {
+		puts("Board: MDED \n");
+		printf("CPU:   LX4280 id: 0x%02x, rev: 0x%02x\n",
+		       (config0 >> 8) & 0xFF, config0 & 0xFF);
+	} else if ((config0 & 0xff0000) == PRID_COMP_MIPS
+		   && (config0 & 0xff00) == PRID_IMP_VGC) {
+		u32 jedec_id = *((u32 *) 0xBEBC71A0);
+		if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
+			puts("Board: VGCA \n");
+		} else if ((((jedec_id) >> 12) & 0xFF) == 0x48
+			   || (((jedec_id) >> 12) & 0xFF) == 0x49) {
+			puts("Board: VGCB \n");
+		}
+		printf("CPU:   MIPS 4K id: 0x%02x, rev: 0x%02x\n",
+		       (config0 >> 8) & 0xFF, config0 & 0xFF);
+	} else if (config0 == 0x19378) {
+		printf("CPU:   MIPS 24K id: 0x%02x, rev: 0x%02x\n",
+		       (config0 >> 8) & 0xFF, config0 & 0xFF);
+	} else {
+		printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
+		       config0);
+	}
+
+	printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/micronas/vct/vct.h b/u-boot/board/micronas/vct/vct.h
new file mode 100644
index 0000000..f1a4851
--- /dev/null
+++ b/u-boot/board/micronas/vct/vct.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+
+#include "bcu.h"
+#include "dcgu.h"
+#include "ebi.h"
+#include "scc.h"
+
+#ifdef CONFIG_VCT_PREMIUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR	0xbf800000
+#define TOP_BASE		0x000c8000
+
+#include "vcth/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#include "vcth/reg_scc.h"
+#include "vcth/reg_usbh.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR	0xbf800000
+#define TOP_BASE		0x000c8000
+
+#include "vcth2/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#include "vcth/reg_scc.h"
+#include "vcth/reg_usbh.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUMAVC
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR	0xbdc00000
+#define TOP_BASE		0x00050000
+
+#include "vctv/reg_ebi.h"
+#include "vctv/reg_dcgu.h"
+#include "vctv/reg_wdt.h"
+#include "vctv/reg_gpio.h"
+#endif
+
+#ifndef _VCT_H
+#define _VCT_H
+
+/*
+ * Defines
+ */
+#define PRID_COMP_LEGACY	0x000000
+#define PRID_COMP_MIPS		0x010000
+#define PRID_IMP_LX4280		0xc200
+#define PRID_IMP_VGC		0x9000
+
+/*
+ * Prototypes
+ */
+int ebi_initialize(void);
+int ebi_init_nor_flash(void);
+int ebi_init_onenand(void);
+int ebi_init_smc911x(void);
+u32 smc911x_reg_read(u32 addr);
+void smc911x_reg_write(u32 addr, u32 data);
+int top_set_pin(int pin, int func);
+void vct_pin_mux_initialize(void);
+
+/*
+ * static inlines
+ */
+static inline void reg_write(u32 addr, u32 data)
+{
+	__raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+}
+
+static inline u32 reg_read(u32 addr)
+{
+	return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+}
+
+#endif /* _VCT_H */
diff --git a/u-boot/board/micronas/vct/vcth/reg_dcgu.h b/u-boot/board/micronas/vct/vcth/reg_dcgu.h
new file mode 100644
index 0000000..6ac0ddd
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_dcgu.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008-2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DCGU_BASE		0x00084000
+
+/* Relative offsets of the register adresses */
+
+#define DCGU_CLK_EN1_OFFS	0x00000010
+#define DCGU_CLK_EN1(base)	((base) + DCGU_CLK_EN1_OFFS)
+#define DCGU_CLK_EN2_OFFS	0x00000014
+#define DCGU_CLK_EN2(base)	((base) + DCGU_CLK_EN2_OFFS)
+#define DCGU_RESET_UNIT1_OFFS	0x00000018
+#define DCGU_RESET_UNIT1(base)	((base) + DCGU_RESET_UNIT1_OFFS)
+#define DCGU_USBPHY_STAT_OFFS	0x00000054
+#define DCGU_USBPHY_STAT(base)	((base) + DCGU_USBPHY_STAT_OFFS)
+#define DCGU_EN_WDT_RESET_OFFS	0x00000064
+#define DCGU_EN_WDT_RESET(base)	((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT		0x1909
diff --git a/u-boot/board/micronas/vct/vcth/reg_ebi.h b/u-boot/board/micronas/vct/vcth/reg_ebi.h
new file mode 100644
index 0000000..7a1e115
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_ebi.h
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE			0x00000000
+
+/*  Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS		0x00000000
+#define EBI_CPU_IO_ACCS(base)		((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS		0x00000004
+#define EBI_IO_ACCS_DATA(base)		((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CTRL_OFFS			0x00000008
+#define EBI_CTRL(base)			((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS		0x00000010
+#define EBI_IRQ_MASK(base)		((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS		0x00000030
+#define EBI_TAG1_SYS_ID(base)		((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS		0x00000040
+#define EBI_TAG2_SYS_ID(base)		((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS		0x00000050
+#define EBI_TAG3_SYS_ID(base)		((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS		0x00000060
+#define EBI_TAG4_SYS_ID(base)		((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS		0x00000070
+#define EBI_GEN_DMA_CTRL(base)		((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS			0x00000080
+#define EBI_STATUS(base)		((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS		0x00000084
+#define EBI_STATUS_DMA_CNT(base)	((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS		0x00000088
+#define EBI_SIG_LEVEL(base)		((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS		0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base)	((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_EXT_ADDR_OFFS		0x000000A0
+#define EBI_EXT_ADDR(base)		((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS		0x000000B0
+#define EBI_IRQ_STATUS(base)		((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS	0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base)	((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS		0x00000104
+#define EBI_DEV1_EXT_ACC(base)		((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS		0x00000108
+#define EBI_DEV1_CONFIG1(base)		((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS		0x0000010C
+#define EBI_DEV1_CONFIG2(base)		((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS	0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) 	((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS	0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base)	((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS	0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base)	((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS	0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base)	((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS		0x00000124
+#define EBI_DEV1_TIM1_RD1(base)		((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS		0x00000128
+#define EBI_DEV1_TIM1_RD2(base)		((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS		0x0000012C
+#define EBI_DEV1_TIM1_WR1(base)		((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS		0x00000130
+#define EBI_DEV1_TIM1_WR2(base)		((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS		0x00000134
+#define EBI_DEV1_TIM_EXT(base)		((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS	0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base)	((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS	0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base)	((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS		0x00000140
+#define EBI_DEV1_TIM3_DMA1(base)	((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS		0x00000144
+#define EBI_DEV1_TIM3_DMA2(base)	((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS	0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base)	((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS	0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base)	((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS		0x00000204
+#define EBI_DEV2_EXT_ACC(base)		((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS		0x00000208
+#define EBI_DEV2_CONFIG1(base)		((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS		0x0000020C
+#define EBI_DEV2_CONFIG2(base)		((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS	0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base)	((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS	0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base)	((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS	0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base)	((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS	0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base)	((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS		0x00000224
+#define EBI_DEV2_TIM1_RD1(base)		((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS		0x00000228
+#define EBI_DEV2_TIM1_RD2(base)		((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS		0x0000022C
+#define EBI_DEV2_TIM1_WR1(base)		((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS		0x00000230
+#define EBI_DEV2_TIM1_WR2(base)		((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS		0x00000234
+#define EBI_DEV2_TIM_EXT(base)		((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS	0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base)	((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS	0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base)	((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS		0x00000240
+#define EBI_DEV2_TIM3_DMA1(base)	((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS		0x00000244
+#define EBI_DEV2_TIM3_DMA2(base)	((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS	0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base)	((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS	0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base)	((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS		0x00000304
+#define EBI_DEV3_EXT_ACC(base)		((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS		0x00000308
+#define EBI_DEV3_CONFIG1(base)		((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS		0x0000030C
+#define EBI_DEV3_CONFIG2(base)		((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS	0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base)	((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS	0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base)	((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS	0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base)	((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS	0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base)	((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS		0x00000324
+#define EBI_DEV3_TIM1_RD1(base)		((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS		0x00000328
+#define EBI_DEV3_TIM1_RD2(base)		((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS		0x0000032C
+#define EBI_DEV3_TIM1_WR1(base)		((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS		0x00000330
+#define EBI_DEV3_TIM1_WR2(base)		((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS		0x00000334
+#define EBI_DEV3_TIM_EXT(base)		((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS	0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base)	((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS	0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base)	((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS		0x00000340
+#define EBI_DEV3_TIM3_DMA1(base)	((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS		0x00000344
+#define EBI_DEV3_TIM3_DMA2(base)	((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS	0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base)	((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS	0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base)	((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS		0x00000404
+#define EBI_DEV4_EXT_ACC(base)		((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS		0x00000408
+#define EBI_DEV4_CONFIG1(base)		((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS		0x0000040C
+#define EBI_DEV4_CONFIG2(base)		((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS	0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base)	((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS	0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base)	((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS	0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base)	((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS	0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base)	((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS		0x00000424
+#define EBI_DEV4_TIM1_RD1(base)		((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS		0x00000428
+#define EBI_DEV4_TIM1_RD2(base)		((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS		0x0000042C
+#define EBI_DEV4_TIM1_WR1(base)		((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS		0x00000430
+#define EBI_DEV4_TIM1_WR2(base)		((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS		0x00000434
+#define EBI_DEV4_TIM_EXT(base)		((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS	0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base)	((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS	0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base)	((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS		0x00000440
+#define EBI_DEV4_TIM3_DMA1(base)	((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS		0x00000444
+#define EBI_DEV4_TIM3_DMA2(base)	((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS	0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base)	((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS		0x00000904
+#define EBI_CNT_FL_PROGR(base)		((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS	0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base)	((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS		0x00000914
+#define EBI_CNT_WAIT_RDY(base)		((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS		0x00000918
+#define EBI_CNT_ACK(base)		((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS		0x00000A00
+#define EBI_GENIO1_CONFIG1(base)	((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS		0x00000A04
+#define EBI_GENIO1_CONFIG2(base)	((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS		0x00000A08
+#define EBI_GENIO1_CONFIG3(base)	((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS		0x00000A10
+#define EBI_GENIO2_CONFIG1(base)	((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS		0x00000A14
+#define EBI_GENIO2_CONFIG2(base)	((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS		0x00000A18
+#define EBI_GENIO2_CONFIG3(base)	((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS		0x00000A20
+#define EBI_GENIO3_CONFIG1(base)	((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS		0x00000A24
+#define EBI_GENIO3_CONFIG2(base)	((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS		0x00000A28
+#define EBI_GENIO3_CONFIG3(base)	((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS		0x00000A30
+#define EBI_GENIO4_CONFIG1(base)	((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS		0x00000A34
+#define EBI_GENIO4_CONFIG2(base)	((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS		0x00000A38
+#define EBI_GENIO4_CONFIG3(base)	((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS		0x00000A40
+#define EBI_GENIO5_CONFIG1(base)	((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS		0x00000A44
+#define EBI_GENIO5_CONFIG2(base)	((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS		0x00000A48
+#define EBI_GENIO5_CONFIG3(base)	((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/u-boot/board/micronas/vct/vcth/reg_fwsram.h b/u-boot/board/micronas/vct/vcth/reg_fwsram.h
new file mode 100644
index 0000000..19afb6b
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_fwsram.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Premium & Platinum register addresses/definitions seem to be
+ * identical, so we only need to use one file for both platforms.
+ */
+
+#ifndef _REG_FWSRAM_H_
+#define _REG_FWSRAM_H_
+
+#define FWSRAM_BASE			0x00030000
+
+/*  Relative offsets of the register adresses */
+
+#define FWSRAM_SR_ADDR_OFFSET_OFFS	0x00002000
+#define FWSRAM_SR_ADDR_OFFSET(base)	((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
+#define FWSRAM_TOP_BOOT_LOG_OFFS	0x00002004
+#define FWSRAM_TOP_BOOT_LOG(base)	((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
+#define FWSRAM_TOP_ROM_KBIST_OFFS	0x00002008
+#define FWSRAM_TOP_ROM_KBIST(base)	((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
+#define FWSRAM_TOP_CID1_H_OFFS		0x0000200C
+#define FWSRAM_TOP_CID1_H(base)		((base) + FWSRAM_TOP_CID1_H_OFFS)
+#define FWSRAM_TOP_CID1_L_OFFS		0x00002010
+#define FWSRAM_TOP_CID1_L(base)		((base) + FWSRAM_TOP_CID1_L_OFFS)
+#define FWSRAM_TOP_CID2_H_OFFS		0x00002014
+#define FWSRAM_TOP_CID2_H(base)		((base) + FWSRAM_TOP_CID2_H_OFFS)
+#define FWSRAM_TOP_CID2_L_OFFS		0x00002018
+#define FWSRAM_TOP_CID2_L(base)		((base) + FWSRAM_TOP_CID2_L_OFFS)
+#define FWSRAM_TOP_TDO_CFG_OFFS		0x0000203C
+#define FWSRAM_TOP_TDO_CFG(base)	((base) + FWSRAM_TOP_TDO_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_0_CFG_OFFS	0x00002040
+#define FWSRAM_TOP_GPIO2_0_CFG(base)	((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_1_CFG_OFFS	0x00002044
+#define FWSRAM_TOP_GPIO2_1_CFG(base)	((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_2_CFG_OFFS	0x00002048
+#define FWSRAM_TOP_GPIO2_2_CFG(base)	((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_3_CFG_OFFS	0x0000204C
+#define FWSRAM_TOP_GPIO2_3_CFG(base)	((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_4_CFG_OFFS	0x00002050
+#define FWSRAM_TOP_GPIO2_4_CFG(base)	((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_5_CFG_OFFS	0x00002054
+#define FWSRAM_TOP_GPIO2_5_CFG(base)	((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_6_CFG_OFFS	0x00002058
+#define FWSRAM_TOP_GPIO2_6_CFG(base)	((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_7_CFG_OFFS	0x0000205C
+#define FWSRAM_TOP_GPIO2_7_CFG(base)	((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
+#define FWSRAM_TOP_SCL_CFG_OFFS		0x00002060
+#define FWSRAM_TOP_SCL_CFG(base)	((base) + FWSRAM_TOP_SCL_CFG_OFFS)
+#define FWSRAM_TOP_SDA_CFG_OFFS		0x00002064
+#define FWSRAM_TOP_SDA_CFG(base)	((base) + FWSRAM_TOP_SDA_CFG_OFFS)
+#define FWSRAM_NO_MCM_FLASH_OFFS	0x00002068
+#define FWSRAM_NO_MCM_FLASH(base)	((base) + FWSRAM_NO_MCM_FLASH_OFFS)
+
+#endif
diff --git a/u-boot/board/micronas/vct/vcth/reg_gpio.h b/u-boot/board/micronas/vct/vcth/reg_gpio.h
new file mode 100644
index 0000000..7ada9c9
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO1_BASE		0x00088000
+#define GPIO2_BASE		0x0008c000
+
+/* Instances */
+#define GPIO_INSTANCES		2
+
+/*  Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS	0x00000000
+#define GPIO_SWPORTA_DR(base)	((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS	0x00000004
+#define GPIO_SWPORTA_DDR(base)	((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS	0x00000050
+#define GPIO_EXT_PORTA(base)	((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/u-boot/board/micronas/vct/vcth/reg_scc.h b/u-boot/board/micronas/vct/vcth/reg_scc.h
new file mode 100644
index 0000000..5e4bfc5
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_scc.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_SCC_PREMIUM_H_
+#define _REG_SCC_PREMIUM_H_
+
+#define SCC0_BASE		0x00110000
+#define SCC1_BASE		0x00110080
+#define SCC2_BASE		0x00110100
+#define SCC3_BASE		0x00110180
+#define SCC4_BASE		0x00110200
+#define SCC5_BASE		0x00110280
+#define SCC6_BASE		0x00110300
+#define SCC7_BASE		0x00110380
+#define SCC8_BASE		0x00110400
+#define SCC9_BASE		0x00110480
+#define SCC10_BASE		0x00110500
+#define SCC11_BASE		0x00110580
+#define SCC12_BASE		0x00110600
+#define SCC13_BASE		0x00110680
+#define SCC14_BASE		0x00110700
+#define SCC15_BASE		0x00110780
+#define SCC16_BASE		0x00110800
+#define SCC17_BASE		0x00110880
+#define SCC18_BASE		0x00110900
+#define SCC19_BASE		0x00110980
+#define SCC20_BASE		0x00110a00
+#define SCC21_BASE		0x00110a80
+#define SCC22_BASE		0x00110b00
+#define SCC23_BASE		0x00110b80
+#define SCC24_BASE		0x00110c00
+#define SCC25_BASE		0x00110c80
+#define SCC26_BASE		0x00110d00
+#define SCC27_BASE		0x00110d80
+#define SCC28_BASE		0x00110e00
+#define SCC29_BASE		0x00110e80
+#define SCC30_BASE		0x00110f00
+#define SCC31_BASE		0x00110f80
+#define SCC32_BASE		0x00111000
+#define SCC33_BASE		0x00111080
+#define SCC34_BASE		0x00111100
+#define SCC35_BASE		0x00111180
+#define SCC36_BASE		0x00111200
+#define SCC37_BASE		0x00111280
+#define SCC38_BASE		0x00111300
+#define SCC39_BASE		0x00111380
+#define SCC40_BASE		0x00111400
+
+/*  Relative offsets of the register adresses */
+
+#define SCC_ENABLE_OFFS		0x00000000
+#define SCC_ENABLE(base)	((base) + SCC_ENABLE_OFFS)
+#define SCC_RESET_OFFS		0x00000004
+#define SCC_RESET(base)		((base) + SCC_RESET_OFFS)
+#define SCC_VCID_OFFS		0x00000008
+#define SCC_VCID(base)		((base) + SCC_VCID_OFFS)
+#define SCC_MCI_CFG_OFFS	0x0000000C
+#define SCC_MCI_CFG(base)	((base) + SCC_MCI_CFG_OFFS)
+#define SCC_PACKET_CFG1_OFFS	0x00000010
+#define SCC_PACKET_CFG1(base)	((base) + SCC_PACKET_CFG1_OFFS)
+#define SCC_PACKET_CFG2_OFFS	0x00000014
+#define SCC_PACKET_CFG2(base)	((base) + SCC_PACKET_CFG2_OFFS)
+#define SCC_PACKET_CFG3_OFFS	0x00000018
+#define SCC_PACKET_CFG3(base)	((base) + SCC_PACKET_CFG3_OFFS)
+#define SCC_DMA_CFG_OFFS	0x0000001C
+#define SCC_DMA_CFG(base)	((base) + SCC_DMA_CFG_OFFS)
+#define SCC_CMD_OFFS		0x00000020
+#define SCC_CMD(base)		((base) + SCC_CMD_OFFS)
+#define SCC_PRIO_OFFS		0x00000024
+#define SCC_PRIO(base)		((base) + SCC_PRIO_OFFS)
+#define SCC_DEBUG_OFFS		0x00000028
+#define SCC_DEBUG(base)		((base) + SCC_DEBUG_OFFS)
+#define SCC_STATUS_OFFS		0x0000002C
+#define SCC_STATUS(base)	((base) + SCC_STATUS_OFFS)
+#define SCC_IMR_OFFS		0x00000030
+#define SCC_IMR(base)		((base) + SCC_IMR_OFFS)
+#define SCC_ISR_OFFS		0x00000034
+#define SCC_ISR(base)		((base) + SCC_ISR_OFFS)
+#define SCC_DMA_OFFSET_OFFS	0x00000038
+#define SCC_DMA_OFFSET(base)	((base) + SCC_DMA_OFFSET_OFFS)
+#define SCC_RS_CTLSTS_OFFS	0x0000003C
+#define SCC_RS_CTLSTS(base)	((base) + SCC_RS_CTLSTS_OFFS)
+
+#endif
diff --git a/u-boot/board/micronas/vct/vcth/reg_usbh.h b/u-boot/board/micronas/vct/vcth/reg_usbh.h
new file mode 100644
index 0000000..9187a34
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_usbh.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define USBH_BASE		0x00080000
+
+/* Relative offsets of the register adresses */
+
+#define USBH_CAPLENGTH_OFFS	0x00000100
+#define USBH_CAPLENGTH(base)	((base) + USBH_CAPLENGTH_OFFS)
+#define USBH_USBCMD_OFFS	0x00000140
+#define USBH_USBCMD(base)	((base) + USBH_USBCMD_OFFS)
+#define USBH_BURSTSIZE_OFFS	0x00000160
+#define USBH_BURSTSIZE(base)	((base) + USBH_BURSTSIZE_OFFS)
+#define USBH_USBMODE_OFFS	0x000001A8
+#define USBH_USBMODE(base)	((base) + USBH_USBMODE_OFFS)
+#define USBH_USBHMISC_OFFS	0x00000200
+#define USBH_USBHMISC(base)	((base) + USBH_USBHMISC_OFFS)
diff --git a/u-boot/board/micronas/vct/vcth/reg_wdt.h b/u-boot/board/micronas/vct/vcth/reg_wdt.h
new file mode 100644
index 0000000..a9b4bf0
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth/reg_wdt.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define WDT_BASE		0x000b0000
+#define WDT_CR_OFFS		0x00000000
+#define WDT_CR(base)		((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS		0x00000004
+#define WDT_TORR(base)		((base) + WDT_TORR_OFFS)
diff --git a/u-boot/board/micronas/vct/vcth2/reg_ebi.h b/u-boot/board/micronas/vct/vcth2/reg_ebi.h
new file mode 100644
index 0000000..37f0711
--- /dev/null
+++ b/u-boot/board/micronas/vct/vcth2/reg_ebi.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE			0x00000000
+
+/*  Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS		0x00000000
+#define EBI_CPU_IO_ACCS(base)		((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS		0x00000004
+#define EBI_IO_ACCS_DATA(base)		((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS		0x00000008
+#define EBI_CPU_IO_ACCS2(base)		((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS		0x0000000C
+#define EBI_IO_ACCS2_DATA(base)		((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS			0x00000010
+#define EBI_CTRL(base)			((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS		0x00000018
+#define EBI_IRQ_MASK(base)		((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS		0x0000001C
+#define EBI_IRQ_MASK2(base)		((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS		0x00000030
+#define EBI_TAG1_SYS_ID(base)		((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS		0x00000040
+#define EBI_TAG2_SYS_ID(base)		((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS		0x00000050
+#define EBI_TAG3_SYS_ID(base)		((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS		0x00000060
+#define EBI_TAG4_SYS_ID(base)		((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS		0x00000070
+#define EBI_GEN_DMA_CTRL(base)		((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS			0x00000080
+#define EBI_STATUS(base)		((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS		0x00000084
+#define EBI_STATUS_DMA_CNT(base)	((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS		0x00000088
+#define EBI_SIG_LEVEL(base)		((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS		0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base)	((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS		0x00000090
+#define EBI_CRC_GEN(base)		((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS		0x000000A0
+#define EBI_EXT_ADDR(base)		((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS		0x000000B0
+#define EBI_IRQ_STATUS(base)		((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS		0x000000B4
+#define EBI_IRQ_STATUS2(base)		((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS	0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base)	((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS	0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base)	((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS			0x000000D0
+#define EBI_ECC0(base)			((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS			0x000000D4
+#define EBI_ECC1(base)			((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS			0x000000D8
+#define EBI_ECC2(base)			((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS			0x000000DC
+#define EBI_ECC3(base)			((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS	0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base)	((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS		0x00000104
+#define EBI_DEV1_EXT_ACC(base)		((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS		0x00000108
+#define EBI_DEV1_CONFIG1(base)		((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS		0x0000010C
+#define EBI_DEV1_CONFIG2(base)		((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS	0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base)	((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS	0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base)	((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS	0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base)	((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS	0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base)	((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS	0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base)	((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS		0x00000124
+#define EBI_DEV1_TIM1_RD1(base)		((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS		0x00000128
+#define EBI_DEV1_TIM1_RD2(base)		((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS		0x0000012C
+#define EBI_DEV1_TIM1_WR1(base)		((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS		0x00000130
+#define EBI_DEV1_TIM1_WR2(base)		((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS		0x00000134
+#define EBI_DEV1_TIM_EXT(base)		((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS	0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base)	((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS	0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base)	((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS		0x00000140
+#define EBI_DEV1_TIM3_DMA1(base)	((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS		0x00000144
+#define EBI_DEV1_TIM3_DMA2(base)	((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS	0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base)	((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS	0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base)	((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS	0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base)	((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS	0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base)	((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS		0x00000204
+#define EBI_DEV2_EXT_ACC(base)		((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS		0x00000208
+#define EBI_DEV2_CONFIG1(base)		((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS		0x0000020C
+#define EBI_DEV2_CONFIG2(base)		((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS	0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base)	((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS	0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base)	((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS	0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base)	((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS	0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base)	((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS	0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base)	((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS		0x00000224
+#define EBI_DEV2_TIM1_RD1(base)		((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS		0x00000228
+#define EBI_DEV2_TIM1_RD2(base)		((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS		0x0000022C
+#define EBI_DEV2_TIM1_WR1(base)		((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS		0x00000230
+#define EBI_DEV2_TIM1_WR2(base)		((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS		0x00000234
+#define EBI_DEV2_TIM_EXT(base)		((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS	0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base)	((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS	0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base)	((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS		0x00000240
+#define EBI_DEV2_TIM3_DMA1(base)	((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS		0x00000244
+#define EBI_DEV2_TIM3_DMA2(base)	((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS	0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base)	((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS	0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base)	((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS	0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base)	((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS	0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base)	((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS		0x00000304
+#define EBI_DEV3_EXT_ACC(base)		((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS		0x00000308
+#define EBI_DEV3_CONFIG1(base)		((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS		0x0000030C
+#define EBI_DEV3_CONFIG2(base)		((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS	0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base)	((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS	0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base)	((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS	0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base)	((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS	0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base)	((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS	0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base)	((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS		0x00000324
+#define EBI_DEV3_TIM1_RD1(base)		((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS		0x00000328
+#define EBI_DEV3_TIM1_RD2(base)		((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS		0x0000032C
+#define EBI_DEV3_TIM1_WR1(base)		((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS		0x00000330
+#define EBI_DEV3_TIM1_WR2(base)		((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS		0x00000334
+#define EBI_DEV3_TIM_EXT(base)		((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS	0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base)	((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS	0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base)	((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS		0x00000340
+#define EBI_DEV3_TIM3_DMA1(base)	((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS		0x00000344
+#define EBI_DEV3_TIM3_DMA2(base)	((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS	0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base)	((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS	0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base)	((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS	0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base)	((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS	0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base)	((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS		0x00000404
+#define EBI_DEV4_EXT_ACC(base)		((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS		0x00000408
+#define EBI_DEV4_CONFIG1(base)		((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS		0x0000040C
+#define EBI_DEV4_CONFIG2(base)		((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS	0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base)	((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS	0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base)	((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS	0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base)	((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS	0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base)	((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS	0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base)	((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS		0x00000424
+#define EBI_DEV4_TIM1_RD1(base)		((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS		0x00000428
+#define EBI_DEV4_TIM1_RD2(base)		((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS		0x0000042C
+#define EBI_DEV4_TIM1_WR1(base)		((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS		0x00000430
+#define EBI_DEV4_TIM1_WR2(base)		((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS		0x00000434
+#define EBI_DEV4_TIM_EXT(base)		((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS	0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base)	((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS	0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base)	((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS		0x00000440
+#define EBI_DEV4_TIM3_DMA1(base)	((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS		0x00000444
+#define EBI_DEV4_TIM3_DMA2(base)	((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS	0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base)	((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS	0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base)	((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS	0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base)	((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS		0x00000900
+#define EBI_INTERLEAVE_CNT(base)	((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS		0x00000904
+#define EBI_CNT_FL_PROGR(base)		((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS	0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base)	((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS		0x00000914
+#define EBI_CNT_WAIT_RDY(base)		((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS		0x00000918
+#define EBI_CNT_ACK(base)		((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS		0x00000A00
+#define EBI_GENIO1_CONFIG1(base)	((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS		0x00000A04
+#define EBI_GENIO1_CONFIG2(base)	((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS		0x00000A08
+#define EBI_GENIO1_CONFIG3(base)	((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS		0x00000A10
+#define EBI_GENIO2_CONFIG1(base)	((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS		0x00000A14
+#define EBI_GENIO2_CONFIG2(base)	((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS		0x00000A18
+#define EBI_GENIO2_CONFIG3(base)	((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS		0x00000A20
+#define EBI_GENIO3_CONFIG1(base)	((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS		0x00000A24
+#define EBI_GENIO3_CONFIG2(base)	((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS		0x00000A28
+#define EBI_GENIO3_CONFIG3(base)	((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS		0x00000A30
+#define EBI_GENIO4_CONFIG1(base)	((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS		0x00000A34
+#define EBI_GENIO4_CONFIG2(base)	((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS		0x00000A38
+#define EBI_GENIO4_CONFIG3(base)	((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS		0x00000A40
+#define EBI_GENIO5_CONFIG1(base)	((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS		0x00000A44
+#define EBI_GENIO5_CONFIG2(base)	((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS		0x00000A48
+#define EBI_GENIO5_CONFIG3(base)	((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/u-boot/board/micronas/vct/vctv/reg_dcgu.h b/u-boot/board/micronas/vct/vctv/reg_dcgu.h
new file mode 100644
index 0000000..6f5c968
--- /dev/null
+++ b/u-boot/board/micronas/vct/vctv/reg_dcgu.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DCGU_BASE		0x0004c000
+#define DCGU_EN_WDT_RESET_OFFS	0x000000FC
+#define DCGU_EN_WDT_RESET(base)	((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT		0x1909
diff --git a/u-boot/board/micronas/vct/vctv/reg_ebi.h b/u-boot/board/micronas/vct/vctv/reg_ebi.h
new file mode 100644
index 0000000..82f345e
--- /dev/null
+++ b/u-boot/board/micronas/vct/vctv/reg_ebi.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PLATINUMAVC_H_
+#define _REG_EBI_PLATINUMAVC_H_
+
+#define EBI_BASE			0x00014000
+
+/*  Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS		0x00000000
+#define EBI_CPU_IO_ACCS(base)		((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS		0x00000004
+#define EBI_IO_ACCS_DATA(base)		((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS		0x00000008
+#define EBI_CPU_IO_ACCS2(base)		((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS		0x0000000C
+#define EBI_IO_ACCS2_DATA(base)		((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS			0x00000010
+#define EBI_CTRL(base)			((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS		0x00000018
+#define EBI_IRQ_MASK(base)		((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS		0x0000001C
+#define EBI_IRQ_MASK2(base)		((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS		0x00000030
+#define EBI_TAG1_SYS_ID(base)		((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS		0x00000040
+#define EBI_TAG2_SYS_ID(base)		((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS		0x00000050
+#define EBI_TAG3_SYS_ID(base)		((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS		0x00000060
+#define EBI_TAG4_SYS_ID(base)		((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS		0x00000070
+#define EBI_GEN_DMA_CTRL(base)		((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS			0x00000080
+#define EBI_STATUS(base)		((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS		0x00000084
+#define EBI_STATUS_DMA_CNT(base)	((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS		0x00000088
+#define EBI_SIG_LEVEL(base)		((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS		0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base)	((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS		0x00000090
+#define EBI_CRC_GEN(base)		((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS		0x000000A0
+#define EBI_EXT_ADDR(base)		((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS		0x000000B0
+#define EBI_IRQ_STATUS(base)		((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS		0x000000B4
+#define EBI_IRQ_STATUS2(base)		((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS	0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base)	((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS	0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base)	((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS			0x000000D0
+#define EBI_ECC0(base)			((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS			0x000000D4
+#define EBI_ECC1(base)			((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS			0x000000D8
+#define EBI_ECC2(base)			((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS			0x000000DC
+#define EBI_ECC3(base)			((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS	0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base)	((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS		0x00000104
+#define EBI_DEV1_EXT_ACC(base)		((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS		0x00000108
+#define EBI_DEV1_CONFIG1(base)		((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS		0x0000010C
+#define EBI_DEV1_CONFIG2(base)		((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS	0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base)	((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS	0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base)	((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS	0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base)	((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS	0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base)	((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS	0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base)	((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS		0x00000124
+#define EBI_DEV1_TIM1_RD1(base)		((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS		0x00000128
+#define EBI_DEV1_TIM1_RD2(base)		((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS		0x0000012C
+#define EBI_DEV1_TIM1_WR1(base)		((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS		0x00000130
+#define EBI_DEV1_TIM1_WR2(base)		((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS		0x00000134
+#define EBI_DEV1_TIM_EXT(base)		((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS	0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base)	((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS	0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base)	((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS		0x00000140
+#define EBI_DEV1_TIM3_DMA1(base)	((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS		0x00000144
+#define EBI_DEV1_TIM3_DMA2(base)	((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS	0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base)	((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS	0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base)	((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS	0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base)	((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS	0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base)	((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS		0x00000204
+#define EBI_DEV2_EXT_ACC(base)		((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS		0x00000208
+#define EBI_DEV2_CONFIG1(base)		((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS		0x0000020C
+#define EBI_DEV2_CONFIG2(base)		((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS	0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base)	((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS	0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base)	((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS	0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base)	((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS	0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base)	((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS	0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base)	((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS		0x00000224
+#define EBI_DEV2_TIM1_RD1(base)		((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS		0x00000228
+#define EBI_DEV2_TIM1_RD2(base)		((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS		0x0000022C
+#define EBI_DEV2_TIM1_WR1(base)		((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS		0x00000230
+#define EBI_DEV2_TIM1_WR2(base)		((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS		0x00000234
+#define EBI_DEV2_TIM_EXT(base)		((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS	0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base)	((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS	0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base)	((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS		0x00000240
+#define EBI_DEV2_TIM3_DMA1(base)	((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS		0x00000244
+#define EBI_DEV2_TIM3_DMA2(base)	((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS	0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base)	((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS	0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base)	((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS	0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base)	((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS	0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base)	((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS		0x00000304
+#define EBI_DEV3_EXT_ACC(base)		((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS		0x00000308
+#define EBI_DEV3_CONFIG1(base)		((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS		0x0000030C
+#define EBI_DEV3_CONFIG2(base)		((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS	0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base)	((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS	0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base)	((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS	0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base)	((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS	0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base)	((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS	0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base)	((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS		0x00000324
+#define EBI_DEV3_TIM1_RD1(base)		((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS		0x00000328
+#define EBI_DEV3_TIM1_RD2(base)		((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS		0x0000032C
+#define EBI_DEV3_TIM1_WR1(base)		((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS		0x00000330
+#define EBI_DEV3_TIM1_WR2(base)		((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS		0x00000334
+#define EBI_DEV3_TIM_EXT(base)		((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS	0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base)	((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS	0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base)	((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS		0x00000340
+#define EBI_DEV3_TIM3_DMA1(base)	((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS		0x00000344
+#define EBI_DEV3_TIM3_DMA2(base)	((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS	0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base)	((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS	0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base)	((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS	0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base)	((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS	0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base)	((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS		0x00000404
+#define EBI_DEV4_EXT_ACC(base)		((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS		0x00000408
+#define EBI_DEV4_CONFIG1(base)		((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS		0x0000040C
+#define EBI_DEV4_CONFIG2(base)		((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS	0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base)	((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS	0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base)	((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS	0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base)	((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS	0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base)	((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS	0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base)	((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS		0x00000424
+#define EBI_DEV4_TIM1_RD1(base)		((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS		0x00000428
+#define EBI_DEV4_TIM1_RD2(base)		((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS		0x0000042C
+#define EBI_DEV4_TIM1_WR1(base)		((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS		0x00000430
+#define EBI_DEV4_TIM1_WR2(base)		((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS		0x00000434
+#define EBI_DEV4_TIM_EXT(base)		((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS	0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base)	((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS	0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base)	((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS		0x00000440
+#define EBI_DEV4_TIM3_DMA1(base)	((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS		0x00000444
+#define EBI_DEV4_TIM3_DMA2(base)	((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS	0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base)	((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS	0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base)	((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS	0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base)	((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS		0x00000900
+#define EBI_INTERLEAVE_CNT(base)	((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS		0x00000904
+#define EBI_CNT_FL_PROGR(base)		((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS	0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base)	((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS		0x00000914
+#define EBI_CNT_WAIT_RDY(base)		((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS		0x00000918
+#define EBI_CNT_ACK(base)		((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS		0x00000A00
+#define EBI_GENIO1_CONFIG1(base)	((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS		0x00000A04
+#define EBI_GENIO1_CONFIG2(base)	((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS		0x00000A08
+#define EBI_GENIO1_CONFIG3(base)	((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS		0x00000A10
+#define EBI_GENIO2_CONFIG1(base)	((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS		0x00000A14
+#define EBI_GENIO2_CONFIG2(base)	((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS		0x00000A18
+#define EBI_GENIO2_CONFIG3(base)	((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS		0x00000A20
+#define EBI_GENIO3_CONFIG1(base)	((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS		0x00000A24
+#define EBI_GENIO3_CONFIG2(base)	((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS		0x00000A28
+#define EBI_GENIO3_CONFIG3(base)	((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS		0x00000A30
+#define EBI_GENIO4_CONFIG1(base)	((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS		0x00000A34
+#define EBI_GENIO4_CONFIG2(base)	((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS		0x00000A38
+#define EBI_GENIO4_CONFIG3(base)	((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS		0x00000A40
+#define EBI_GENIO5_CONFIG1(base)	((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS		0x00000A44
+#define EBI_GENIO5_CONFIG2(base)	((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS		0x00000A48
+#define EBI_GENIO5_CONFIG3(base)	((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/u-boot/board/micronas/vct/vctv/reg_gpio.h b/u-boot/board/micronas/vct/vctv/reg_gpio.h
new file mode 100644
index 0000000..24eb8e9
--- /dev/null
+++ b/u-boot/board/micronas/vct/vctv/reg_gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO1_BASE		0x00044000
+#define GPIO2_BASE		0x00048000
+
+/* Instances */
+#define GPIO_INSTANCES		2
+
+/*  Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS	0x00000000
+#define GPIO_SWPORTA_DR(base)	((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS	0x00000004
+#define GPIO_SWPORTA_DDR(base)	((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS	0x00000050
+#define GPIO_EXT_PORTA(base)	((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/u-boot/board/micronas/vct/vctv/reg_wdt.h b/u-boot/board/micronas/vct/vctv/reg_wdt.h
new file mode 100644
index 0000000..04842e5
--- /dev/null
+++ b/u-boot/board/micronas/vct/vctv/reg_wdt.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define WDT_BASE		0x00040000
+#define WDT_CR_OFFS		0x00000000
+#define WDT_CR(base)		((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS		0x00000004
+#define WDT_TORR(base)		((base) + WDT_TORR_OFFS)
diff --git a/u-boot/board/mimc/mimc200/Makefile b/u-boot/board/mimc/mimc200/Makefile
new file mode 100644
index 0000000..7fbd20d
--- /dev/null
+++ b/u-boot/board/mimc/mimc200/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mimc/mimc200/config.mk b/u-boot/board/mimc/mimc200/config.mk
new file mode 100644
index 0000000..ea76d05
--- /dev/null
+++ b/u-boot/board/mimc/mimc200/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE		= 0x00000000
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
diff --git a/u-boot/board/mimc/mimc200/mimc200.c b/u-boot/board/mimc/mimc200/mimc200.c
new file mode 100644
index 0000000..470adba
--- /dev/null
+++ b/u-boot/board/mimc/mimc200/mimc200.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <atmel_lcdc.h>
+#include <lcd.h>
+
+#include "../../../arch/avr32/cpu/hsmc3.h"
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
+		.phys		= (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+#if defined(CONFIG_LCD)
+/* 480x272x16 @ 72 Hz */
+vidinfo_t panel_info = {
+	.vl_col			= 480,		/* Number of columns */
+	.vl_row			= 272,		/* Number of rows */
+	.vl_clk			= 5000000,	/* pixel clock in ps */
+	.vl_sync		= ATMEL_LCDC_INVCLK_INVERTED |
+				  ATMEL_LCDC_INVLINE_INVERTED |
+				  ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix		= LCD_COLOR16,	/* Bits per pixel, BPP = 2^n */
+	.vl_tft			= 1,		/* 0 = passive, 1 = TFT */
+	.vl_hsync_len		= 42,		/* Length of horizontal sync */
+	.vl_left_margin		= 1,		/* Time from sync to picture */
+	.vl_right_margin	= 1,		/* Time from picture to sync */
+	.vl_vsync_len		= 1,		/* Length of vertical sync */
+	.vl_upper_margin	= 12,		/* Time from sync to picture */
+	.vl_lower_margin	= 1,		/* Time from picture to sync */
+	.mmio			= LCDC_BASE,	/* Memory mapped registers */
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_16BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 6,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 6,
+	.txsr		= 6,
+	/* 15.6 us */
+	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	/* Enable 26 address bits and NCS2 */
+	portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+	/* de-assert "force sys reset" pin */
+	portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
+			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
+
+	/* init custom i/o */
+	/* cpu type inputs */
+	portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
+			PORTMUX_DIR_INPUT);
+	/* main board type inputs */
+	portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
+			PORTMUX_DIR_INPUT);
+	/* DEBUG input (use weak pullup) */
+	portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
+			PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
+
+	/* are we suppressing the console ? */
+	if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
+		gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
+
+	/* reset phys */
+	portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
+	portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
+			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
+
+	udelay(5000);
+
+	/* release phys reset */
+	gpio_set_value(GPIO_PIN_PC(18), 0);	/* PHY RESET (Release)	*/
+
+	/* setup Data Flash chip select (NCS2) */
+	hsmc3_writel(MODE2, 0x20121003);
+	hsmc3_writel(CYCLE2, 0x000a0009);
+	hsmc3_writel(PULSE2, 0x0a060806);
+	hsmc3_writel(SETUP2, 0x00030102);
+
+	/* setup FRAM chip select (NCS3) */
+	hsmc3_writel(MODE3, 0x10120001);
+	hsmc3_writel(CYCLE3, 0x001e001d);
+	hsmc3_writel(PULSE3, 0x08040704);
+	hsmc3_writel(SETUP3, 0x02050204);
+
+#if defined(CONFIG_MACB)
+	/* init macb0 pins */
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+#if defined(CONFIG_LCD)
+	portmux_enable_lcdc(1);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = uncached(EBI_SDRAM_BASE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	gd->bd->bi_phy_id[1] = 0x03;
+	return 0;
+}
+
+int board_postclk_init(void)
+{
+	/* Use GCLK0 as 10MHz output */
+	gclk_enable_output(0, PORTMUX_DRIVE_LOW);
+	gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
+	return 0;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return (bus == 0) && (cs == 0);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/mimc/mimc200/u-boot.lds b/u-boot/board/mimc/mimc200/u-boot.lds
new file mode 100644
index 0000000..a7243f2
--- /dev/null
+++ b/u-boot/board/mimc/mimc200/u-boot.lds
@@ -0,0 +1,72 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/u-boot/board/miromico/hammerhead/Makefile b/u-boot/board/miromico/hammerhead/Makefile
new file mode 100644
index 0000000..43f0b50
--- /dev/null
+++ b/u-boot/board/miromico/hammerhead/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2008 Miromico AG
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/miromico/hammerhead/config.mk b/u-boot/board/miromico/hammerhead/config.mk
new file mode 100644
index 0000000..ea76d05
--- /dev/null
+++ b/u-boot/board/miromico/hammerhead/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE		= 0x00000000
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
diff --git a/u-boot/board/miromico/hammerhead/hammerhead.c b/u-boot/board/miromico/hammerhead/hammerhead.c
new file mode 100644
index 0000000..78f4fd4
--- /dev/null
+++ b/u-boot/board/miromico/hammerhead/hammerhead.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Mostly copied form atmel ATNGW100 sources
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/memory-map.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = uncached(EBI_SDRAM_BASE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+		       actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	return 0;
+}
+
+int board_postclk_init(void)
+{
+	/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
+	gclk_enable_output(3, PORTMUX_DRIVE_LOW);
+	gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
+	return 0;
+}
diff --git a/u-boot/board/miromico/hammerhead/u-boot.lds b/u-boot/board/miromico/hammerhead/u-boot.lds
new file mode 100644
index 0000000..a7243f2
--- /dev/null
+++ b/u-boot/board/miromico/hammerhead/u-boot.lds
@@ -0,0 +1,72 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/u-boot/board/ml2/Makefile b/u-boot/board/ml2/Makefile
new file mode 100644
index 0000000..67de4f9
--- /dev/null
+++ b/u-boot/board/ml2/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o serial.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ml2/flash.c b/u-boot/board/ml2/flash.c
new file mode 100644
index 0000000..c125d41
--- /dev/null
+++ b/u-boot/board/ml2/flash.c
@@ -0,0 +1,300 @@
+/*
+ * flash.c: Support code for the flash chips on the Xilinx ML2 board
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire program
+ * is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <configs/ML2.h>
+
+#define FLASH_BANK_SIZE (64*1024*1024)
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define SECT_SIZE		(512*1024)
+
+#define CMD_READ_ARRAY	0x00FF00FF00FF00FULL
+#define CMD_IDENTIFY        0x0090009000900090ULL
+#define CMD_ERASE_SETUP     0x0020002000200020ULL
+#define CMD_ERASE_CONFIRM   0x00D000D000D000D0ULL
+#define CMD_PROGRAM     0x0040004000400040ULL
+#define CMD_RESUME      0x00D000D000D000D0ULL
+#define CMD_SUSPEND     0x00B000B000B000B0ULL
+#define CMD_STATUS_READ     0x0070007000700070ULL
+#define CMD_STATUS_RESET    0x0050005000500050ULL
+
+#define BIT_BUSY        0x0080008000800080ULL
+#define BIT_ERASE_SUSPEND   0x004000400400040ULL
+#define BIT_ERASE_ERROR     0x0020002000200020ULL
+#define BIT_PROGRAM_ERROR   0x0010001000100010ULL
+#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL
+#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL
+#define BIT_PROTECT_ERROR   0x0002000200020002ULL
+#define BIT_UNDEFINED       0x0001000100010001ULL
+
+#define BIT_SEQUENCE_ERROR  0x0030003000300030ULL
+
+#define BIT_TIMEOUT     0x80000000
+
+
+inline void eieio(void) {
+
+	__asm__ __volatile__ ("eieio" : : : "memory");
+
+}
+
+ulong flash_init(void) {
+
+	int i, j;
+	ulong size = 0;
+
+	for(i=0;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) |
+								 (INTEL_ID_28F128J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i==0)
+			flashbase = CONFIG_SYS_FLASH_BASE;
+		else
+			panic("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++)
+				flash_info[i].start[j]=flashbase + j * SECT_SIZE;
+
+		size += flash_info[i].size;
+	}
+
+	return size;
+}
+
+void flash_print_info  (flash_info_t *info) {
+
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf("Intel: ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
+			printf("4x 28F128J3A (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf (" %08lX%s", info->start[i],
+				 info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+int flash_error (unsigned long long code) {
+
+	if (code & BIT_TIMEOUT) {
+		printf ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	if (~code & BIT_BUSY) {
+		printf ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_VPP_RANGE_ERROR) {
+		printf ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_PROTECT_ERROR) {
+		printf ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_SEQUENCE_ERROR) {
+		printf ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_ERASE_ERROR) {
+		printf ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_PROGRAM_ERROR) {
+		printf ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_ERASE_SUSPEND) {
+		printf ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_PROGRAM_SUSPEND) {
+		printf ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	return ERR_OK;
+
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+
+	int rc = ERR_OK;
+	int sect;
+	unsigned long long result;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last))
+		return ERR_INVAL;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			return ERR_PROTECTED;
+
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+		volatile unsigned long long *addr=
+									(unsigned long long *)(info->start[sect]);
+
+		printf("Erasing sector %2d ... ", sect);
+
+		*addr=CMD_STATUS_RESET;
+		eieio();
+		*addr=CMD_ERASE_SETUP;
+		eieio();
+		*addr=CMD_ERASE_CONFIRM;
+		eieio();
+
+		do {
+			result = *addr;
+		} while(~result & BIT_BUSY);
+
+		*addr=CMD_READ_ARRAY;
+
+		if ((rc = flash_error(result)) == ERR_OK)
+			printf("ok.\n");
+		else
+			break;
+	}
+
+	if (ctrlc())
+		printf("User Interrupt!\n");
+
+	return rc;
+}
+
+static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
+
+	volatile unsigned long long *addr=(unsigned long long *)dest;
+	unsigned long long result;
+	int rc = ERR_OK;
+
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	*addr=CMD_STATUS_RESET;
+	eieio();
+	*addr=CMD_PROGRAM;
+	eieio();
+	*addr=data;
+	eieio();
+
+	do {
+		result = *addr;
+	} while(~result & BIT_BUSY);
+
+	*addr=CMD_READ_ARRAY;
+
+	rc = flash_error(result);
+
+	return rc;
+
+}
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+
+	ulong cp, wp;
+	unsigned long long data;
+	int l;
+	int i,rc;
+
+	wp=(addr & ~7);
+
+	if((l=addr-wp) != 0) {
+		data=0;
+		for(i=0,cp=wp;i<l;++i,++cp)
+			data = (data >> 8) | (*(uchar *)cp << 24);
+
+		for (; i<8 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+
+		for (; i<8; ++i, ++cp)
+			data = (data >> 8) | (*(uchar *)cp << 24);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return rc;
+
+		wp+=8;
+	}
+
+	while(cnt>=8) {
+		data = *((unsigned long long *)src);
+		if ((rc = write_word(info, wp, data)) != 0)
+			return rc;
+		src+=8;
+		wp+=8;
+		cnt-=8;
+	}
+
+	if(cnt == 0)
+		return ERR_OK;
+
+	data = 0;
+	for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i<8; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	return write_word(info, wp, data);
+
+}
diff --git a/u-boot/board/ml2/init.S b/u-boot/board/ml2/init.S
new file mode 100644
index 0000000..91d053c
--- /dev/null
+++ b/u-boot/board/ml2/init.S
@@ -0,0 +1,30 @@
+/*
+ * init.S: Stubs for U-Boot initialization
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	blr
diff --git a/u-boot/board/ml2/ml2.c b/u-boot/board/ml2/ml2.c
new file mode 100644
index 0000000..981e1de
--- /dev/null
+++ b/u-boot/board/ml2/ml2.c
@@ -0,0 +1,66 @@
+/*
+ * ml2.c: U-Boot platform support for Xilinx ML2 board
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * Derived from : Other platform support files in this tree
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+	char *e;
+
+	if (!s || strncmp (s, "ML2", 9)) {
+		printf ("### No HW ID - assuming ML2");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+
+	putc ('\n');
+
+	return (0);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+	return 32 * 1024 * 1024;
+}
+
+int testdram (void)
+{
+	printf ("test: xxx MB - ok\n");
+
+	return (0);
+}
diff --git a/u-boot/board/ml2/serial.c b/u-boot/board/ml2/serial.c
new file mode 100644
index 0000000..d9113ab
--- /dev/null
+++ b/u-boot/board/ml2/serial.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2002
+ * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <configs/ML2.h>
+
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+#include <ns16550.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
+	(NS16550_t) CONFIG_SYS_NS16550_COM2
+};
+#endif
+
+int serial_init (void)
+{
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	(void) NS16550_init (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	(void) NS16550_init (COM_PORTS[1], clock_divisor);
+#endif
+	return 0;
+
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
+
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/u-boot/board/ml2/u-boot.lds b/u-boot/board/ml2/u-boot.lds
new file mode 100644
index 0000000..b6c0715
--- /dev/null
+++ b/u-boot/board/ml2/u-boot.lds
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ml2/u-boot.lds.debug b/u-boot/board/ml2/u-boot.lds.debug
new file mode 100644
index 0000000..0e9cdcf
--- /dev/null
+++ b/u-boot/board/ml2/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/modnet50/Makefile b/u-boot/board/modnet50/Makefile
new file mode 100644
index 0000000..d5a541f
--- /dev/null
+++ b/u-boot/board/modnet50/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= modnet50.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/modnet50/config.mk b/u-boot/board/modnet50/config.mk
new file mode 100644
index 0000000..4e4d305
--- /dev/null
+++ b/u-boot/board/modnet50/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x00f00000
+#CROSS_COMPILE = arm-elf-
diff --git a/u-boot/board/modnet50/flash.c b/u-boot/board/modnet50/flash.c
new file mode 100644
index 0000000..4c31143
--- /dev/null
+++ b/u-boot/board/modnet50/flash.c
@@ -0,0 +1,536 @@
+/*
+ * (C) Copyright 2002
+ * MAZeT GmbH <www.mazet.de>
+ * Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
+ *
+ * The most stuff comes from PPCBoot and Linux.
+ *
+ * IMMS gGmbH <www.imms.de>
+ * Thomas Elste <info@elste.org>
+ *
+ * Modifications for ModNET50 Board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/netarm_registers.h>
+
+#define SCR   (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_SYSTEM_CONTROL))
+
+#define ALIGN_ABORT_OFF		SCR = SCR & ~NETARM_GEN_SYS_CFG_ALIGN_ABORT
+#define ALIGN_ABORT_ON		SCR = SCR |  NETARM_GEN_SYS_CFG_ALIGN_ABORT
+
+#define PROG_ADDR		(0x555*2)
+#define SETUP_ADDR		(0x555*2)
+#define ID_ADDR			(0x555*2)
+#define UNLOCK_ADDR1		(0x555*2)
+#define UNLOCK_ADDR2		(0x2AA*2)
+
+#define UNLOCK_CMD1		(0xAA)
+#define UNLOCK_CMD2		(0x55)
+#define ERASE_SUSPEND_CMD	(0xB0)
+#define ERASE_RESUME_CMD	(0x30)
+#define RESET_CMD		(0xF0)
+#define ID_CMD			(0x90)
+#define SECERASE_CMD		(0x30)
+#define CHIPERASE_CMD		(0x10)
+#define PROG_CMD		(0xa0)
+#define SETUP_CMD		(0x80)
+
+#define DQ2			(0x04)
+#define DQ3			(DQ2*2)
+#define DQ5			(DQ3*4)
+#define DQ6			(DQ5*2)
+
+#define WRITE_UNLOCK(addr) { \
+  *(volatile __u16*)(addr + UNLOCK_ADDR1) = (__u16)UNLOCK_CMD1; \
+  *(volatile __u16*)(addr + UNLOCK_ADDR2) = (__u16)UNLOCK_CMD2; \
+}
+
+#define CONFIG_AM29_RESERVED	(0)
+#define K			(1024)
+#define MB			(4)
+
+#define CELL_SIZE		(64*K)
+#define DEVICE_SIZE		(MB*K*K)
+#define CELLS_PER_DEVICE	(DEVICE_SIZE/CELL_SIZE)
+#define RESERVED_CELLS		(CONFIG_AM29_RESERVED*K)/CELL_SIZE
+#define MAX_FLASH_DEVICES	(1)
+#define AVAIL_SIZE		(DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE)
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static __u16 toggling_bits;
+
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	__u16 flashtest;
+
+	/* Write auto select command sequence and test FLASH answer */
+	WRITE_UNLOCK (baseaddr);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD;
+	flashtest /* manufacturer ID */  = *(volatile __u16 *) (baseaddr);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD;
+
+	switch ((__u32) ((flashtest << 16) + flashtest)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD & FLASH_VENDMASK;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ & FLASH_VENDMASK;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash */
+	}
+
+	/* Write auto select command sequence and test FLASH answer */
+	WRITE_UNLOCK (baseaddr);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD;
+	flashtest /* device ID */  = *(volatile __u16 *) (baseaddr + 2);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD;
+
+	/* toggling_bits = (flashtest == TOSHIBA)?(DQ6):(DQ2|DQ6); */
+	toggling_bits = (DQ2 | DQ6);
+
+	switch ((__u32) ((flashtest << 16) + flashtest)) {
+	case AMD_ID_LV160B:
+		info->flash_id +=
+			(FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK;
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		info->size = CONFIG_SYS_FLASH_SIZE;
+		/* 1*16K Boot Block
+		   2*8K Parameter Block
+		   1*32K Small Main Block */
+		info->start[0] = baseaddr;
+		info->start[1] = baseaddr + 0x4000;
+		info->start[2] = baseaddr + 0x6000;
+		info->start[3] = baseaddr + 0x8000;
+		for (i = 1; i < info->sector_count; i++)
+			info->start[3 + i] = baseaddr + i * CONFIG_SYS_MAIN_SECT_SIZE;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* no or unknown flash */
+	}
+
+	for (i = 0; i < info->sector_count; i++) {
+		/* Write auto select command sequence and test FLASH answer */
+		WRITE_UNLOCK (info->start[i]);
+		*(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) ID_CMD;
+		flashtest /* protected verify */  = *(volatile __u16 *) (info->start[i] + 4);
+		*(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) RESET_CMD;
+		if (flashtest & 0x0001) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_init (void)
+{
+	ulong size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+	size = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("Fujitsu ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case (FLASH_AM160LV | FLASH_AM160B):
+		printf ("29LV160BE (1M x 16, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" S%02d @ 0x%08lX%s", i,
+			info->start[i], info->protect[i] ? " !" : "  ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+	int sect, prot = 0;
+
+	for (sect = s_first; sect <= s_last; sect++)
+		if (info->protect[sect])
+			prot++;
+	if (prot)
+		printf ("- can't erase %d protected sectors\n", prot);
+	return prot;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_check_erase_amd (ulong start)
+{
+	__u16 v1, v2;
+
+	v1 = *(volatile __u16 *) (start);
+	v2 = *(volatile __u16 *) (start);
+
+	if (((v1 ^ v2) & toggling_bits) == toggling_bits) {
+		if (((v1 | v2) & DQ5) == DQ5) {
+			printf ("[DQ5] ");
+			/* OOPS: exceeded timing limits */
+
+			v1 = *(volatile __u16 *) (start);
+			v2 = *(volatile __u16 *) (start);
+
+			if (((v1 ^ v2) & toggling_bits) == toggling_bits) {
+
+				printf ("[%s] ",
+					((toggling_bits & (DQ2 | DQ6)) ==
+					 (DQ2 | DQ6)) ? "DQ2,DQ6" : "DQ6");
+
+				/* OOPS: there is an erasure in progress,
+				 *       try to reset chip */
+				*(volatile __u16 *) (start) =
+					(__u16) RESET_CMD;
+
+				return 1;	/* still busy */
+			}
+		}
+		return 1;	/* still busy */
+	}
+	return 0;		/* be free */
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, sect, setup_offset = 0;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("- missing\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return ERR_INVAL;
+	}
+
+	if (flash_check_protection (info, s_first, s_last))
+		return ERR_PROTECTED;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_FUJ:
+	case FLASH_MAN_AMD:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_AM160LV | FLASH_AM160B):
+			setup_offset = UNLOCK_ADDR1;	/* just the adress for setup_cmd differs */
+		case FLASH_AMDL323B:
+			/*
+			 * Disable interrupts which might cause a timeout
+			 * here. Remember that our exception vectors are
+			 * at address 0 in the flash, and we don't want a
+			 * (ticker) exception to happen while the flash
+			 * chip is in programming mode.
+			 */
+			flag = disable_interrupts ();
+			/* Start erase on unprotected sectors */
+			for (sect = s_first; sect <= s_last && !ctrlc ();
+			     sect++) {
+				printf ("Erasing sector %2d ... ", sect);
+
+				if (info->protect[sect] == 0) {
+					/* not protected */
+					/* Write sector erase command sequence */
+					WRITE_UNLOCK (info->start[0]);
+					*(volatile __u16 *) (info->start[0] +
+							     setup_offset) =
+						(__u16) SETUP_CMD;
+					WRITE_UNLOCK (info->start[0]);
+					*(volatile __u16 *) (info->
+							     start[sect]) =
+						(__u16) SECERASE_CMD;
+
+					/* wait some time */
+					reset_timer_masked ();
+					while (get_timer_masked () < 1000) {
+					}
+
+					/* arm simple, non interrupt dependent timer */
+					reset_timer_masked ();
+					while (flash_check_erase_amd (info->start[sect])) {
+						if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+							printf ("timeout!\n");
+							/* OOPS: reach timeout,
+							 * try to reset chip
+							 */
+							*(volatile __u16 *) (info-> start[sect]) = (__u16) RESET_CMD;
+							rc = ERR_TIMOUT;
+							goto outahere_323B;
+						}
+					}
+					printf ("ok.\n");
+				} else {
+					printf ("protected!\n");
+				}
+			}
+			if (ctrlc ())
+				printf ("User Interrupt!\n");
+outahere_323B:
+			/* allow flash to settle - wait 10 ms */
+			udelay_masked (10000);
+			if (flag)
+				enable_interrupts ();
+			return rc;
+		default:
+			printf ("- unknown chip type\n");
+			return ERR_UNKNOWN_FLASH_TYPE;
+		}
+		break;
+	default:
+		printf ("- unknown vendor ");
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_check_write_amd (ulong dest)
+{
+	__u16 v1, v2;
+
+	v1 = *(volatile __u16 *) (dest);
+	v2 = *(volatile __u16 *) (dest);
+
+	/* DQ6 toggles during write */
+	if (((v1 ^ v2) & DQ6) == DQ6) {
+		if (((v1 | v2) & DQ5) == DQ5) {
+			printf ("[DQ5] @ %08lX\n", dest);
+
+			/* OOPS: exceeded timing limits,
+			 *       try to reset chip */
+			*(volatile __u16 *) (dest) = (__u16) RESET_CMD;
+			return 0;	/* be free */
+		}
+		return 1;	/* still busy */
+	}
+
+	return 0;		/* be free */
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(__u16 *) (dest) & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Write program command sequence */
+	WRITE_UNLOCK (info->start[0]);
+
+	/* Flash dependend program seqence */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_FUJ:
+	case FLASH_MAN_AMD:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_AM160LV | FLASH_AM160B):
+			*(volatile __u16 *) (info->start[0] + UNLOCK_ADDR1) =
+				(__u16) PROG_CMD;
+			*(volatile __u16 *) (dest) = (__u16) data;
+			break;
+		case FLASH_AMDL323B:
+			*(volatile __u16 *) (dest) = (__u16) PROG_CMD;
+			*(volatile __u16 *) (dest) = (__u16) data;
+			break;
+		}
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	while (flash_check_write_amd (dest)) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			printf ("timeout! @ %08lX\n", dest);
+			/* OOPS: reach timeout,
+			 *       try to reset chip */
+			*(volatile __u16 *) (dest) = (__u16) RESET_CMD;
+
+			rc = ERR_TIMOUT;
+			goto outahere_323B;
+		}
+	}
+
+	/* Check if Flash was (accurately) written */
+	if (*(__u16 *) (dest) != data)
+		rc = ERR_PROG_ERROR;
+
+outahere_323B:
+	if (flag)
+		enable_interrupts ();
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((ushort *) src);
+		if ((rc = write_word (info, wp, data)) != 0)
+			return (rc);
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/modnet50/lowlevel_init.S b/u-boot/board/modnet50/lowlevel_init.S
new file mode 100644
index 0000000..52ef2a8
--- /dev/null
+++ b/u-boot/board/modnet50/lowlevel_init.S
@@ -0,0 +1,204 @@
+/*
+ * Memory Setup stuff - taken from Linux
+ *
+ * Copyright (c) 2002	Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
+ * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/netarm_registers.h>
+
+
+/* some parameters for the board */
+#define FLASH_90ns_WAIT_STATES	((NETARM_PLL_COUNT_VAL + 2) / 3)
+#define FLASH_70ns_WAIT_STATES	4
+
+#define NETARM_MMAP_CS0_BASE	(PHYS_FLASH_1)
+#if 1
+#define NETARM_MMAP_CS0_MASK	(~(PHYS_FLASH_1_SIZE - 1))
+#else
+#define NETARM_MMAP_CS0_MASK	(~(1000000 - 1))
+#endif
+#define NETARM_MMAP_CS1_BASE	(PHYS_SDRAM_1)
+#define NETARM_MMAP_CS1_MASK	(~(PHYS_SDRAM_1_SIZE - 1))
+#define NETARM_MMAP_CS2_BASE	(PHYS_SDRAM_2)
+#define NETARM_MMAP_CS2_MASK	(~(PHYS_SDRAM_2_SIZE - 1))
+#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
+#define NETARM_MMAP_CS3_BASE	(PHYS_NVRAM_1)
+#define NETARM_MMAP_CS3_MASK	(~(PHYS_NVRAM_SIZE - 1))
+#endif
+#define NETARM_MMAP_CS4_BASE	(PHYS_EXT_1)
+#define NETARM_MMAP_CS4_MASK	(~(PHYS_EXT_SIZE - 1))
+
+/* setting up the memory */
+.globl lowlevel_init
+lowlevel_init:
+
+#if defined(CONFIG_MODNET50)
+	ldr	pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - CONFIG_SYS_TEXT_BASE)
+
+_jump_to_high:
+	/*
+	 * MEM Config Reg
+	 * ---------------------------------------------------
+	 */
+	ldr	r0, =NETARM_MEM_MODULE_BASE
+	ldr	r1, =(	NETARM_MEM_REFR_PERIOD_USEC(16) | \
+			NETARM_MEM_CFG_REFRESH_EN | \
+			NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
+	str	r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
+
+
+memsetup_cs0:
+	/*
+	 * Base Addr / Option Reg 0 (Flash)
+	 * ---------------------------------------------------
+	 */
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
+			NETARM_MEM_BAR_DRAM_FP | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_BAL | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
+
+	/* trust that the bus size for flash was strapped correctly */
+	/* this saves the bus width in r2 and then ORs it back in */
+	/* it's pretty safe assumption, otherwise it wouldn't boot */
+	ldr	r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
+	and	r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
+
+/*	just a test: assume 32 bit flash mem */
+/*	mov	r2, #NETARM_MEM_OPT_32BIT */
+
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
+			NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
+			NETARM_MEM_OPT_BCYC_4 | \
+			NETARM_MEM_OPT_BSIZE_16 | \
+			NETARM_MEM_OPT_16BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+
+	orr	r1, r1, r2
+	str	r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
+
+
+memsetup_cs1:
+	/*
+	 * Base Addr / Option Reg 1 (DRAM #1)
+	 * ---------------------------------------------------
+	 */
+#ifdef CONFIG_NETARM_NET40_REV2
+	/* we have to config SDRAM in burst mode */
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
+			NETARM_MEM_OPT_BCYC_2 | \
+			NETARM_MEM_OPT_BSIZE_16 | \
+			NETARM_MEM_OPT_WAIT_STATES(0) | \
+			NETARM_MEM_OPT_32BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+	str	r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
+
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
+			NETARM_MEM_BAR_DRAM_SYNC | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
+			NETARM_MEM_BAR_DRAM_SEL | \
+			NETARM_MEM_BAR_BURST_EN | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
+#else
+	/* we have to config FPDRAM in burst mode with smaller burst access size */
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
+			NETARM_MEM_OPT_BCYC_2 | \
+			NETARM_MEM_OPT_BSIZE_16 | \
+			NETARM_MEM_OPT_WAIT_STATES(0) | \
+			NETARM_MEM_OPT_32BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+	str	r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
+
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
+			NETARM_MEM_BAR_DRAM_SYNC | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
+			NETARM_MEM_BAR_DRAM_SEL | \
+			NETARM_MEM_BAR_BURST_EN | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
+
+#endif /* CONFIG_NETARM_NET40_REV2 */
+
+
+memsetup_cs3:
+	/*
+	 * Base Addr / Option Reg 3 (EEPROM, NVRAM)
+	 * ---------------------------------------------------
+	 */
+#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
+			NETARM_MEM_OPT_BCYC_3 | \
+			NETARM_MEM_OPT_BSIZE_2 | \
+			NETARM_MEM_OPT_WAIT_STATES(10) | \
+			NETARM_MEM_OPT_8BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+	str	r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
+
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
+			NETARM_MEM_BAR_DRAM_FP | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_BAL | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
+#else
+	/* we don't need EEPROM --> no config */
+	ldr	r1, =( 0 )
+	str	r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
+
+	ldr	r1, =( 0 )
+	str	r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
+#endif
+
+
+#else
+/*
+#error "missing CONFIG_MODNET50 (see your config.h)"
+*/
+#endif /* CONFIG_MODNET50 */
+
+
+lowlevel_init_end:
+	/*
+	 * manipulate address in lr and ip to match new
+	 * address space
+	 */
+	ldr	r3, =(NETARM_MMAP_CS0_BASE)
+	mov	r0, lr
+	add	r0, r3, r0
+	mov	lr, r0
+	mov	r0, ip
+	add	r0, r3, r0
+	mov	ip, r0
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/modnet50/modnet50.c b/u-boot/board/modnet50/modnet50.c
new file mode 100644
index 0000000..4544069
--- /dev/null
+++ b/u-boot/board/modnet50/modnet50.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* address for the kernel command line */
+	gd->bd->bi_boot_params = 0x800;
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	if (CONFIG_NR_DRAM_BANKS == 2) {
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+		gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	}
+	return (0);
+}
diff --git a/u-boot/board/mosaixtech/icon/Makefile b/u-boot/board/mosaixtech/icon/Makefile
new file mode 100644
index 0000000..39cff51
--- /dev/null
+++ b/u-boot/board/mosaixtech/icon/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2009-2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mosaixtech/icon/chip_config.c b/u-boot/board/mosaixtech/icon/chip_config.c
new file mode 100644
index 0000000..b9dd447
--- /dev/null
+++ b/u-boot/board/mosaixtech/icon/chip_config.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"400-133", "CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"500-166", "CPU: 500 PLB: 166 OPB:  83 EBC:  83",
+		{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"533-133", "CPU: 533 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"667-133", "CPU: 667 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"667-166", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
+		{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"800-160", "CPU: 800 PLB: 160 OPB:  53 EBC:  17",
+		{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/mosaixtech/icon/config.mk b/u-boot/board/mosaixtech/icon/config.mk
new file mode 100644
index 0000000..bce3514
--- /dev/null
+++ b/u-boot/board/mosaixtech/icon/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2009-2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/mosaixtech/icon/icon.c b/u-boot/board/mosaixtech/icon/icon.c
new file mode 100644
index 0000000..e09dbc3
--- /dev/null
+++ b/u-boot/board/mosaixtech/icon/icon.c
@@ -0,0 +1,388 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	unsigned long mfr;
+
+	/*
+	 * Interrupt controller setup for the ICON 440SPe board.
+	 *
+	 *--------------------------------------------------------------------
+	 * IRQ    | Source                            | Pol.  | Sensi.| Crit.
+	 *--------+-----------------------------------+-------+-------+-------
+	 * IRQ 00 | UART0                             | High  | Level | Non
+	 * IRQ 01 | UART1                             | High  | Level | Non
+	 * IRQ 02 | IIC0                              | High  | Level | Non
+	 * IRQ 03 | IIC1                              | High  | Level | Non
+	 * IRQ 04 | PCI0X0 MSG IN                     | High  | Level | Non
+	 * IRQ 05 | PCI0X0 CMD Write                  | High  | Level | Non
+	 * IRQ 06 | PCI0X0 Power Mgt                  | High  | Level | Non
+	 * IRQ 07 | PCI0X0 VPD Access                 | Rising| Edge  | Non
+	 * IRQ 08 | PCI0X0 MSI level 0                | High  | Lvl/ed| Non
+	 * IRQ 09 | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non
+	 * IRQ 10 | UIC2 Non-critical Int.            | NA    | NA    | Non
+	 * IRQ 11 | UIC2 Critical Interrupt           | NA    | NA    | Crit
+	 * IRQ 12 | PCI Express MSI Level 0           | Rising| Edge  | Non
+	 * IRQ 13 | PCI Express MSI Level 1           | Rising| Edge  | Non
+	 * IRQ 14 | PCI Express MSI Level 2           | Rising| Edge  | Non
+	 * IRQ 15 | PCI Express MSI Level 3           | Rising| Edge  | Non
+	 * IRQ 16 | UIC3 Non-critical Int.            | NA    | NA    | Non
+	 * IRQ 17 | UIC3 Critical Interrupt           | NA    | NA    | Crit
+	 * IRQ 18 | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non
+	 * IRQ 19 | DMA Channel 0 FIFO Full           | High  | Level | Non
+	 * IRQ 20 | DMA Channel 0 Stat FIFO           | High  | Level | Non
+	 * IRQ 21 | DMA Channel 1 FIFO Full           | High  | Level | Non
+	 * IRQ 22 | DMA Channel 1 Stat FIFO           | High  | Level | Non
+	 * IRQ 23 | I2O Inbound Doorbell              | High  | Level | Non
+	 * IRQ 24 | Inbound Post List FIFO Not Empt   | High  | Level | Non
+	 * IRQ 25 | I2O Region 0 LL PLB Write         | High  | Level | Non
+	 * IRQ 26 | I2O Region 1 LL PLB Write         | High  | Level | Non
+	 * IRQ 27 | I2O Region 0 HB PLB Write         | High  | Level | Non
+	 * IRQ 28 | I2O Region 1 HB PLB Write         | High  | Level | Non
+	 * IRQ 29 | GPT Down Count Timer              | Rising| Edge  | Non
+	 * IRQ 30 | UIC1 Non-critical Int.            | NA    | NA    | Non
+	 * IRQ 31 | UIC1 Critical Interrupt           | NA    | NA    | Crit.
+	 *--------------------------------------------------------------------
+	 * IRQ 32 | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non
+	 * IRQ 33 | MAL Serr                          | High  | Level | Non
+	 * IRQ 34 | MAL Txde                          | High  | Level | Non
+	 * IRQ 35 | MAL Rxde                          | High  | Level | Non
+	 * IRQ 36 | DMC CE or DMC UE                  | High  | Level | Non
+	 * IRQ 37 | EBC or UART2                      | High  |Lvl Edg| Non
+	 * IRQ 38 | MAL TX EOB                        | High  | Level | Non
+	 * IRQ 39 | MAL RX EOB                        | High  | Level | Non
+	 * IRQ 40 | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non
+	 * IRQ 41 | PCIX0 MSI level 2                 | High  |Lvl Edg| Non
+	 * IRQ 42 | PCIX0 MSI level 3                 | High  |Lvl Edg| Non
+	 * IRQ 43 | L2 Cache                          | Risin | Edge  | Non
+	 * IRQ 44 | GPT Compare Timer 0               | Risin | Edge  | Non
+	 * IRQ 45 | GPT Compare Timer 1               | Risin | Edge  | Non
+	 * IRQ 46 | GPT Compare Timer 2               | Risin | Edge  | Non
+	 * IRQ 47 | GPT Compare Timer 3               | Risin | Edge  | Non
+	 * IRQ 48 | GPT Compare Timer 4               | Risin | Edge  | Non
+	 * IRQ 49 | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non
+	 * IRQ 50 | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non
+	 * IRQ 51 | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non
+	 * IRQ 52 | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non
+	 * IRQ 53 | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non
+	 * IRQ 54 | DMA Error                         | High  | Level | Non
+	 * IRQ 55 | DMA I2O Error                     | High  | Level | Non
+	 * IRQ 56 | Serial ROM                        | High  | Level | Non
+	 * IRQ 57 | PCIX0 Error                       | High  | Edge  | Non
+	 * IRQ 58 | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non
+	 * IRQ 59 | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non
+	 * IRQ 60 | EMAC0 Interrupt                   | High  | Level | Non
+	 * IRQ 61 | EMAC0 Wake-up                     | High  | Level | Non
+	 * IRQ 62 | Reserved                          | High  | Level | Non
+	 * IRQ 63 | XOR                               | High  | Level | Non
+	 *--------------------------------------------------------------------
+	 * IRQ 64 | PE0 AL                            | High  | Level | Non
+	 * IRQ 65 | PE0 VPD Access                    | Risin | Edge  | Non
+	 * IRQ 66 | PE0 Hot Reset Request             | Risin | Edge  | Non
+	 * IRQ 67 | PE0 Hot Reset Request             | Falli | Edge  | Non
+	 * IRQ 68 | PE0 TCR                           | High  | Level | Non
+	 * IRQ 69 | PE0 BusMaster VCO                 | Falli | Edge  | Non
+	 * IRQ 70 | PE0 DCR Error                     | High  | Level | Non
+	 * IRQ 71 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 72 | PE1 AL                            | High  | Level | Non
+	 * IRQ 73 | PE1 VPD Access                    | Risin | Edge  | Non
+	 * IRQ 74 | PE1 Hot Reset Request             | Risin | Edge  | Non
+	 * IRQ 75 | PE1 Hot Reset Request             | Falli | Edge  | Non
+	 * IRQ 76 | PE1 TCR                           | High  | Level | Non
+	 * IRQ 77 | PE1 BusMaster VCO                 | Falli | Edge  | Non
+	 * IRQ 78 | PE1 DCR Error                     | High  | Level | Non
+	 * IRQ 79 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 80 | PE2 AL                            | High  | Level | Non
+	 * IRQ 81 | PE2 VPD Access                    | Risin | Edge  | Non
+	 * IRQ 82 | PE2 Hot Reset Request             | Risin | Edge  | Non
+	 * IRQ 83 | PE2 Hot Reset Request             | Falli | Edge  | Non
+	 * IRQ 84 | PE2 TCR                           | High  | Level | Non
+	 * IRQ 85 | PE2 BusMaster VCO                 | Falli | Edge  | Non
+	 * IRQ 86 | PE2 DCR Error                     | High  | Level | Non
+	 * IRQ 87 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 88 | External IRQ(5)                   | Progr | Progr | Non
+	 * IRQ 89 | External IRQ 4 - Ethernet         | Progr | Progr | Non
+	 * IRQ 90 | External IRQ 3 - PCI-X            | Progr | Progr | Non
+	 * IRQ 91 | External IRQ 2 - PCI-X            | Progr | Progr | Non
+	 * IRQ 92 | External IRQ 1 - PCI-X            | Progr | Progr | Non
+	 * IRQ 93 | External IRQ 0 - PCI-X            | Progr | Progr | Non
+	 * IRQ 94 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 95 | Reserved                          | N/A   | N/A   | Non
+	 *--------------------------------------------------------------------
+	 * IRQ 96 | PE0 INTA                          | High  | Level | Non
+	 * IRQ 97 | PE0 INTB                          | High  | Level | Non
+	 * IRQ 98 | PE0 INTC                          | High  | Level | Non
+	 * IRQ 99 | PE0 INTD                          | High  | Level | Non
+	 * IRQ 100| PE1 INTA                          | High  | Level | Non
+	 * IRQ 101| PE1 INTB                          | High  | Level | Non
+	 * IRQ 102| PE1 INTC                          | High  | Level | Non
+	 * IRQ 103| PE1 INTD                          | High  | Level | Non
+	 * IRQ 104| PE2 INTA                          | High  | Level | Non
+	 * IRQ 105| PE2 INTB                          | High  | Level | Non
+	 * IRQ 106| PE2 INTC                          | High  | Level | Non
+	 * IRQ 107| PE2 INTD                          | Risin | Edge  | Non
+	 * IRQ 108| PCI Express MSI Level 4           | Risin | Edge  | Non
+	 * IRQ 109| PCI Express MSI Level 5           | Risin | Edge  | Non
+	 * IRQ 110| PCI Express MSI Level 6           | Risin | Edge  | Non
+	 * IRQ 111| PCI Express MSI Level 7           | Risin | Edge  | Non
+	 * IRQ 116| PCI Express MSI Level 12          | Risin | Edge  | Non
+	 * IRQ 112| PCI Express MSI Level 8           | Risin | Edge  | Non
+	 * IRQ 113| PCI Express MSI Level 9           | Risin | Edge  | Non
+	 * IRQ 114| PCI Express MSI Level 10          | Risin | Edge  | Non
+	 * IRQ 115| PCI Express MSI Level 11          | Risin | Edge  | Non
+	 * IRQ 117| PCI Express MSI Level 13          | Risin | Edge  | Non
+	 * IRQ 118| PCI Express MSI Level 14          | Risin | Edge  | Non
+	 * IRQ 119| PCI Express MSI Level 15          | Risin | Edge  | Non
+	 * IRQ 120| PCI Express MSI Level 16          | Risin | Edge  | Non
+	 * IRQ 121| PCI Express MSI Level 17          | Risin | Edge  | Non
+	 * IRQ 122| PCI Express MSI Level 18          | Risin | Edge  | Non
+	 * IRQ 123| PCI Express MSI Level 19          | Risin | Edge  | Non
+	 * IRQ 124| PCI Express MSI Level 20          | Risin | Edge  | Non
+	 * IRQ 125| PCI Express MSI Level 21          | Risin | Edge  | Non
+	 * IRQ 126| PCI Express MSI Level 22          | Risin | Edge  | Non
+	 * IRQ 127| PCI Express MSI Level 23          | Risin | Edge  | Non
+	 */
+
+	/*
+	 * Put UICs in PowerPC 440SPe mode.
+	 * Initialise UIC registers. Clear all interrupts. Disable all
+	 * interrupts. Set critical interrupt values. Set interrupt polarities.
+	 * Set interrupt trigger levels. Make bit 0 High priority. Clear all
+	 * interrupts again.
+	 */
+	mtdcr(UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC3CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC3PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr(UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC3SR, 0x00000000);	/* clear all  interrupts*/
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all  interrupts*/
+
+	mtdcr(UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr(UIC2CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC2PR, 0xebebebff);	/* Set Interrupt Polarities*/
+	mtdcr(UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* Clear all interrupts*/
+	mtdcr(UIC1ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr(UIC1CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels*/
+	mtdcr(UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC1SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all interrupts*/
+
+	mtdcr(UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all int. excepted cascade */
+	mtdcr(UIC0CR, 0x00104001);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC0PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr(UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC0SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all interrupts*/
+
+	mfsdr(SDR0_MFR, mfr);
+	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
+	mtsdr(SDR0_MFR, mfr);
+
+	mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
+
+	out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
+	out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+	 * boot EBC mapping only supports a maximum of 16MBytes
+	 * (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfc00.0000 -> 4.ec00.0000
+	 */
+
+	/* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
+	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+		    CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: ICON");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ *
+ * Tested successfully with the following SODIMM:
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ *
+ * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
+ * directly after power-up. Only after running for more than 10 minutes
+ * real stable auto-calibration windows could be found.
+ */
+u32 ddr_wrdtr(u32 default_val)
+{
+	return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
+}
+
+u32 ddr_clktr(u32 default_val)
+{
+	return SDRAM_CLKTR_CLKP_180_DEG_ADV;
+}
+
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
+{
+	/* Only 2 PCIe ports used on ICON, so the last one is 1 */
+	return 1;
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+static const SMI_REGS sm502_init_regs[] = {
+	{0x00004, 0x0},
+	{0x00040, 0x00021847},
+	{0x00044, 0x091a0a01}, /* 24 MHz pixclk */
+	{0x00054, 0x0},
+	{0x00048, 0x00021847},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x80004, 0xc428bb17},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a0280},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e7},
+	{0x80200, 0x00010000},
+	{0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */
+	{0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */
+	{0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
+	{0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */
+	{0, 0}
+};
+
+/*
+ * Return a pointer to the register initialization table.
+ */
+const SMI_REGS *board_get_regs(void)
+{
+	return sm502_init_regs;
+}
+
+int board_get_width(void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height(void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str(int line_number, char *info)
+{
+	if (line_number == 1)
+		strcpy(info, " Board: ICON");
+	else
+		info[0] = '\0';
+}
+#endif
+
+#endif /* CONFIG_VIDEO_SM501 */
diff --git a/u-boot/board/mosaixtech/icon/init.S b/u-boot/board/mosaixtech/icon/init.S
new file mode 100644
index 0000000..a0168b5
--- /dev/null
+++ b/u-boot/board/mosaixtech/icon/init.S
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ */
+
+	.section .bootpg,"ax"
+
+	.globl tlbtab
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I.
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+		 4, AC_RWX | SA_G) /* TLB 0 */
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
+		 AC_RWX | SA_I)
+
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
+		 CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/motionpro/Makefile b/u-boot/board/motionpro/Makefile
new file mode 100644
index 0000000..f5d88bb
--- /dev/null
+++ b/u-boot/board/motionpro/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/motionpro/motionpro.c b/u-boot/board/motionpro/motionpro.c
new file mode 100644
index 0000000..47ef6e5
--- /dev/null
+++ b/u-boot/board/motionpro/motionpro.c
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
+ * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
+ * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
+ * Also changed the refresh for 100MHz operation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <miiphy.h>
+#include <libfdt.h>
+
+#if defined(CONFIG_STATUS_LED)
+#include <status_led.h>
+#endif /* CONFIG_STATUS_LED */
+
+/* Kollmorgen DPR initialization data */
+struct init_elem {
+	unsigned long addr;
+	unsigned len;
+	char *data;
+	} init_seq[] = {
+		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
+		{0x500003F0, 2, "\x00\x00"},
+		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
+	};
+
+/*
+ * Initialize Kollmorgen DPR
+ */
+static void kollmorgen_init(void)
+{
+	unsigned i, j;
+	vu_char *p;
+
+	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
+		p = (vu_char *)init_seq[i].addr;
+		for (j = 0; j < init_seq[i].len; ++j)
+			*(p + j) = *(init_seq[i].data + j);
+	}
+
+	printf("DPR:   Kollmorgen DPR initialized\n");
+}
+
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
+
+	/* Initialize Kollmorgen DPR */
+	kollmorgen_init();
+
+	return 0;
+}
+
+
+/*
+ * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
+ * PHY goes into FX mode.  To take it out of the FX mode and switch into
+ * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
+ * Register.
+ */
+void reset_phy(void)
+{
+	unsigned short mode_control;
+
+	miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
+	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
+			mode_control & 0xfffe);
+	return;
+}
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+						hi_addr_bit;
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+						hi_addr_bit;
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+						hi_addr_bit;
+
+	/* auto refresh, second time */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+						hi_addr_bit;
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+}
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* According to AN3221 (MPC5200B SDRAM Initialization and
+	 * Configuration), the SDelay register must be written a value of
+	 * 0x00000004 as the first step of the SDRAM contorller configuration.
+	 */
+	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+
+	/* configure SDRAM start/end for detection */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 and disable it */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
+
+#else /* !CONFIG_SYS_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/* return total ram size */
+	return dramsize;
+}
+
+
+int checkboard(void)
+{
+	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
+	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
+	return 0;
+}
+
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+
+#if defined(CONFIG_STATUS_LED)
+void __led_init(led_id_t regaddr, int state)
+{
+	*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
+
+	if (state == STATUS_LED_ON)
+		*((vu_long *) regaddr) |= LED_ON;
+	else
+		*((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_set(led_id_t regaddr, int state)
+{
+	if (state == STATUS_LED_ON)
+		*((vu_long *) regaddr) |= LED_ON;
+	else
+		*((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_toggle(led_id_t regaddr)
+{
+	*((vu_long *) regaddr) ^= LED_ON;
+}
+#endif /* CONFIG_STATUS_LED */
diff --git a/u-boot/board/mousse/Makefile b/u-boot/board/mousse/Makefile
new file mode 100644
index 0000000..346f779
--- /dev/null
+++ b/u-boot/board/mousse/Makefile
@@ -0,0 +1,44 @@
+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o m48t59y.o pci.o flash.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mousse/README b/u-boot/board/mousse/README
new file mode 100644
index 0000000..d5dda7a
--- /dev/null
+++ b/u-boot/board/mousse/README
@@ -0,0 +1,346 @@
+
+U-Boot for MOUSSE/MPC8240 (KAHLUA)
+----------------------------------
+James Dougherty (jfd@broadcom.com), 09/10/01
+
+The Broadcom/Vooha Mousse board is a 3U Compact PCI system board
+which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard
+DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH.
+See also: http://www.vooha.com/
+
+* NVRAM setenv/printenv/savenv supported.
+* Date Command
+* Serial Console support
+* Network support
+* FLASH of kernel images is supported.
+* FLASH of U-Boot to onboard and PLCC boot region.
+* Kernel command line options from NVRAM is supported.
+* IP PNP options supported.
+
+U-Boot Loading...
+
+
+U-Boot 1.0.5 (Sep 10 2001 - 00:22:25)
+
+CPU:   MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)
+Built: Sep 10 2001 at 01:01:50
+MPLD:  Revision 127
+Local Bus:  33 MHz
+RTC:   M48T589 TOD/NVRAM (8176) bytes
+  Current date/time: 9/10/2001 0:18:52
+DRAM:  64 MB
+FLASH:  1.960 MB
+PCI:    scanning bus0 ...
+  bus dev fn venID devID class  rev MBAR0    MBAR1    IPIN ILINE
+  00  00  00 1057  0003  060000 11  00000008 00000000 01   00
+  00  0d  00 1011  0019  020000 41  80000001 80000000 01   01
+  00  0e  00 105a  4d38  018000 01  a0000001 a0001001 01   03
+In:    serial
+Out:   serial
+Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+
+I. Root FileSystem/IP Configuration
+
+bootcmd=tftp 100000 vmlinux.img;bootm
+bootdelay=3
+baudrate=9600
+ipaddr=<IP ADDRESS>
+netmask=<NETMASK>
+hostname=<NAME>
+serverip=<NFS SERVER IP ADDRESS>
+ethaddr=00:00:10:20:30:44
+nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs
+gateway=<IP ADDRESS>
+root=/dev/nfs
+stdin=serial
+stdout=serial
+stderr=serial
+
+NVRAM environment variables.
+
+use the command:
+
+setenv <attribute> <value>
+
+type "saveenv" to write to NVRAM.
+
+
+II. To boot from a hard drive:
+
+setenv root /dev/hda1
+
+
+III. IP options which configure the network:
+
+ipaddr=<IP ADDRESS OF MACHINE>
+netmask=<NETMASK>
+hostname=mousse
+ethaddr=00:00:10:20:30:44
+gateway=<IP ADDRESS OF GATEWAY/ROUTER>
+
+
+IV. IP Options which configure NFS Root/Boot Support
+
+root=/dev/nfs
+serverip=<NFS SERVER IP ADDRESS>
+nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs
+
+V. U-Boot Image Support
+
+The U-Boot boot loader assumes that after you build
+your kernel (vmlinux), you will create a U-Boot image
+using the following commands or script:
+
+#!/bin/csh
+/bin/touch vmlinux.img
+/bin/rm vmlinux.img
+set path=($TOOLBASE/bin $path)
+set path=($U_BOOT/tools $path)
+powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin
+gzip -vf vmlinux.bin
+mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img
+ls -l vmlinux.img
+
+
+VI. ONBOARD FLASH Support
+
+FLASH support is provided for the onboard FLASH chip Bootrom area.
+U-Boot is loaded into either the ROM boot region of the FLASH chip,
+after first being boot-strapped from a pre-progammed AMD29F040 PLCC
+bootrom. The PLCC needs to be programmed with a ROM burner using
+AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record)
+images.
+
+The PLCC overlays this same region of flash as the onboard FLASH,
+the jumper J100 is a chip-select for which flash chip you want to
+progam. When jumper J100 is connected to pins 2-3, you boot from
+PLCC FLASH.
+
+To bringup a system, simply flash a flash an AMD29F040 PLCC
+bootrom, and put this in the PLCC socket. Move jumper J100 to
+pins 2-3 and boot from the PLCC.
+
+
+Now, while the system is running, move Jumper J100 to
+pins 1-2 and follow the procedure below to FLASH a bootrom
+(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB):
+
+tftp 100000 u-boot.bin
+protect off FFF00000 FFF7FFFF
+erase FFF00000 FFF7FFFF
+cp.b 100000 FFF00000 \${filesize}\
+
+
+Here is an example:
+
+=>tftp 100000 u-boot.bin
+eth_halt
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 123220 (1e154 hex)
+eth_halt
+=>protect off FFF00000 FFF7FFFF
+Un-Protected 8 sectors
+=>erase FFF00000 FFF7FFFF
+Erase Flash from 0xfff00000 to 0xfff7ffff
+Erase FLASH[PLCC_BOOT] -8 sectors:........ done
+Erased 8 sectors
+=>cp.b 100000 FFF00000 1e154
+Copy to Flash... FLASH[PLCC_BOOT]:..done
+=>
+
+
+B. FLASH RAMDISK REGION
+
+FLASH support is provided for an Onboard 512K RAMDISK region.
+
+TThe following commands will FLASH a bootrom (u-boot.bin) image
+into the onboard FLASH region (AMD29LV160DB 2MB FLASH):
+
+tftp 100000 u-boot.bin
+protect off FFF80000 FFFFFFFF
+erase FFF80000 FFFFFFFF
+cp.b 100000 FFF80000 \${filesize}\
+
+
+C. FLASH KERNEL REGION (960KB)
+
+FLASH support is provided for the 960KB onboard FLASH1 segment.
+This allows flashing of kernel images which U-Boot can load
+and run (standalone) from the onboard FLASH chip. It also assumes
+
+The following commands will FLASH a kernel image to 0xffe10000
+
+tftp 100000 vmlinux.img
+protect off FFE10000 FFEFFFFF
+erase FFE10000 FFEFFFFF
+cp.b 100000 FFE10000 \${filesize}\
+reset
+
+Here is an example:
+
+
+=>tftp 100000 vmlinux.img
+eth_halt
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+TFTP from server 209.128.93.133; our IP address is 209.128.93.138
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: #####################################################################################################################################################
+done
+Bytes transferred = 760231 (b99a7 hex)
+eth_halt
+=>protect off FFE10000 FFEFFFFF
+Un-Protected 15 sectors
+=>erase FFE10000 FFEFFFFF
+Erase Flash from 0xffe10000 to 0xffefffff
+Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done
+Erased 15 sectors
+=>cp.b 100000 FFE10000 b99a7
+Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done
+=>
+
+
+When finished, use the command:
+
+bootm ffe10000
+
+to start the kernel.
+
+Finally, to make this the default boot command, use
+the following commands:
+
+setenv bootcmd bootm ffe10000
+savenv
+
+to make it automatically boot the kernel from FLASH.
+
+
+To go back to development mode (NFS boot)
+
+setenv bootcmd tftp 100000 vmlinux.img\;bootm
+savenv
+
+
+=>tftp 100000 vmlinux.img
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: ####################################################################################################################################################
+done
+Bytes transferred = 752717 (b7c4d hex)
+eth_halt
+=>protect off FFE10000 FFEFFFFF
+Un-Protected 15 sectors
+=>erase FFE10000 FFEFFFFF
+Erase Flash from 0xffe10000 to 0xffefffff
+Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done
+Erased 15 sectors
+=>cp.b 100000 FFE10000 b7c4d
+Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done
+=>bootm ffe10000
+## Booting image at ffe10000 ...
+   Image Name:   vmlinux.bin.gz
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    752653 Bytes = 735 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Total memory = 64MB; using 0kB for hash table (at 00000000)
+Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001
+cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f
+Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com)
+IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44>
+NOTICE: mounting root file system via NFS
+On node 0 totalpages: 16384
+zone(0): 16384 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+time_init: decrementer frequency = 16.665914 MHz
+time_init: MPC8240 PCI Bus frequency = 33.331828 MHz
+Calibrating delay loop... 133.12 BogoMIPS
+Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem)
+Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
+Inode-cache hash table entries: 4096 (order: 3, 32768 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd v1.8
+pty: 256 Unix98 ptys configured
+block: queued sectors max/low 41394kB/13798kB, 128 slots per queue
+Uniform Multi-Platform E-IDE driver Revision: 6.31
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PDC20262: IDE controller on PCI bus 00 dev 70
+PDC20262: chipset revision 1
+PDC20262: not 100% native mode: will probe irqs later
+PDC20262: ROM enabled at 0x000d0000
+PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
+PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE
+PDC20262: irq=3 dev->irq=3
+    ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA
+    ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio
+hda: WDC WD300AB-00BVA0, ATA DISK drive
+hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive
+ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3
+ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3
+hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66)
+hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache
+Uniform CD-ROM driver Revision: 3.12
+Partition check:
+ /dev/ide/host0/bus0/target0/lun0: p1 p2
+hd: unable to get major 3 for hard disk
+udf: registering filesystem
+loop: loaded (max 8 devices)
+Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
+ttyS00 at 0xffe08080 (irq = 4) is a ST16650
+Linux Tulip driver version 0.9.13a (January 20, 2001)
+eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1.
+eth0:  MII transceiver #0 config 3000 status 7829 advertising 01e1.
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 4096 bind 4096)
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au)
+devfs: boot_options: 0x0
+VFS: Mounted root (nfs filesystem).
+Mounted devfs on /dev
+Freeing unused kernel memory: 88k init 4k openfirmware
+eth0: Setting full-duplex based on MII#0 link partner capability of 45e1.
+INIT: version 2.78 booting
+INIT: Entering runlevel: 2
+
+
+Welcome to Linux/PPC
+MPC8240/MOUSSE
+
+
+mousse login: root
+Password:
+PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0)
+Last login: Thu Sep  6 00:16:51 2001 on console
+
+
+Welcome to Linux/PPC
+MPC8240/MOUSSE
+
+
+mousse#
diff --git a/u-boot/board/mousse/flash.c b/u-boot/board/mousse/flash.c
new file mode 100644
index 0000000..d729f33
--- /dev/null
+++ b/u-boot/board/mousse/flash.c
@@ -0,0 +1,939 @@
+/*
+ * MOUSSE/MPC8240 Board definitions.
+ * Flash Routines for MOUSSE onboard AMD29LV106DB devices
+ *
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include "mousse.h"
+#include "flash.h"
+
+int flashLibDebug = 0;
+int flashLibInited = 0;
+
+#define OK  0
+#define ERROR -1
+#define STATUS int
+#define PRINTF			if (flashLibDebug) printf
+#if 0
+#define PRIVATE			static
+#else
+#define PRIVATE
+#endif
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define SLEEP_DELAY    166
+#define FLASH_SECTOR_SIZE   (64*1024)
+/***********************************************************************
+ *
+ * Virtual Flash Devices on Mousse board
+ *
+ * These must be kept in sync with the definitions in flashLib.h.
+ *
+ ***********************************************************************/
+
+PRIVATE flash_dev_t flashDev[] = {
+    /* Bank 0 sector SA0 (16 kB) */
+    {	"SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sector SA1 (8 kB) */
+    {	"SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sector SA2 (8 kB) */
+    {	"SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sector SA3 is occluded by Mousse I/O devices */
+    /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB)  */
+    {	"KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */
+    /* This is where the Kahlua boot vector and boot ROM code resides. */
+    {	"BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sectors SA27-SA34 (512 kB) */
+    {	"RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+};
+
+int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0]));
+
+#define DEV(no)			(&flashDev[no])
+#define DEV_NO(dev)		((dev) - flashDev)
+
+/***********************************************************************
+ *
+ * Private Flash Routines
+ *
+ ***********************************************************************/
+
+/*
+ * The convention is:
+ *
+ * "addr" is always the PROM raw address, which is the address of an
+ * 8-bit quantity for flash 0 and 16-bit quantity for flash 1.
+ *
+ * "pos" is always a logical byte position from the PROM beginning.
+ */
+
+#define FLASH0_ADDR(dev, addr) \
+	((unsigned char *) ((dev)->base + (addr)))
+
+#define FLASH0_WRITE(dev, addr, value) \
+	(*FLASH0_ADDR(dev, addr) = (value))
+
+#define FLASH0_READ(dev, addr) \
+	(*FLASH0_ADDR(dev, addr))
+
+PRIVATE int flashCheck (flash_dev_t * dev)
+{
+	if (!flashLibInited) {
+		printf ("flashCheck: flashLib not initialized\n");
+		return ERROR;
+	}
+
+	if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) {
+		printf ("flashCheck: Bad dev parameter\n");
+		return ERROR;
+	}
+
+	if (!dev->found) {
+		printf ("flashCheck: Device %d not available\n", DEV_NO (dev));
+		return ERROR;
+	}
+
+	return OK;
+}
+
+PRIVATE void flashReset (flash_dev_t * dev)
+{
+	PRINTF ("flashReset: dev=%d\n", DEV_NO (dev));
+
+	if (dev->bank == FLASH0_BANK) {
+		FLASH0_WRITE (dev, 0x555, 0xaa);
+		FLASH0_WRITE (dev, 0xaaa, 0x55);
+		FLASH0_WRITE (dev, 0x555, 0xf0);
+	}
+
+	udelay (SLEEP_DELAY);
+
+	PRINTF ("flashReset: done\n");
+}
+
+PRIVATE int flashProbe (flash_dev_t * dev)
+{
+	int rv, deviceID, vendorID;
+
+	PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev));
+
+	if (dev->bank != FLASH0_BANK) {
+		rv = ERROR;
+		goto DONE;
+	}
+
+	FLASH0_WRITE (dev, 0xaaa, 0xaa);
+	FLASH0_WRITE (dev, 0x555, 0x55);
+	FLASH0_WRITE (dev, 0xaaa, 0x90);
+
+	udelay (SLEEP_DELAY);
+
+	vendorID = FLASH0_READ (dev, 0);
+	deviceID = FLASH0_READ (dev, 2);
+
+	FLASH0_WRITE (dev, 0, 0xf0);
+
+	PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID);
+
+	if (vendorID == dev->vendorID && deviceID == dev->deviceID)
+		rv = OK;
+	else
+		rv = ERROR;
+
+  DONE:
+	PRINTF ("flashProbe: rv=%d\n", rv);
+
+	return rv;
+}
+
+PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase)
+{
+	int rv = ERROR;
+	int i, data;
+	int polls;
+
+#if 0
+	PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n",
+		DEV_NO (dev), addr, expect, erase);
+#endif
+
+	if (dev->bank != FLASH0_BANK) {
+		rv = ERROR;
+		goto done;
+	}
+
+	if (erase)
+		polls = FLASH_ERASE_SECTOR_TIMEOUT;	/* Ticks */
+	else
+		polls = FLASH_PROGRAM_POLLS;	/* Loops */
+
+	for (i = 0; i < polls; i++) {
+		if (erase)
+			udelay (SLEEP_DELAY);
+
+		data = FLASH0_READ (dev, addr);
+
+		if (((data ^ expect) & 0x80) == 0) {
+			rv = OK;
+			goto done;
+		}
+
+		if (data & 0x20) {
+			/*
+			 * If the 0x20 bit has come on, it could actually be because
+			 * the operation succeeded, so check the done bit again.
+			 */
+
+			data = FLASH0_READ (dev, addr);
+
+			if (((data ^ expect) & 0x80) == 0) {
+				rv = OK;
+				goto done;
+			}
+
+			printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n",
+					DEV_NO (dev), addr);
+
+			flashReset (dev);
+			rv = ERROR;
+			goto done;
+		}
+	}
+
+	printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n",
+		erase ? "erasing sector" : "programming byte",
+		DEV_NO (dev), addr);
+
+  done:
+
+#if 0
+	PRINTF ("flashWait: rv=%d\n", rv);
+#endif
+
+	return rv;
+}
+
+/***********************************************************************
+ *
+ * Public Flash Routines
+ *
+ ***********************************************************************/
+
+STATUS flashLibInit (void)
+{
+	int i;
+
+	PRINTF ("flashLibInit: devices=%d\n", flashDevCount);
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		/*
+		 * For bank 1, probe both without and with byte swappage,
+		 * so that this module works on both old and new Mousse boards.
+		 */
+
+		flashReset (dev);
+
+		if (flashProbe (dev) != ERROR)
+			dev->found = 1;
+
+		flashReset (dev);
+
+		if (flashProbe (dev) != ERROR)
+			dev->found = 1;
+
+		dev->swap = 0;
+
+		if (dev->found) {
+			PRINTF ("\n  FLASH %s[%d]: iobase=0x%x - %d sectors %d KB",
+				flashDev[i].name, i, flashDev[i].base,
+				flashDev[i].sectors,
+				(flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024);
+
+		}
+	}
+
+	flashLibInited = 1;
+
+	PRINTF ("flashLibInit: done\n");
+
+	return OK;
+}
+
+STATUS flashEraseSector (flash_dev_t * dev, int sector)
+{
+	int pos, addr;
+
+	PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	if (sector < 0 || sector >= dev->sectors) {
+		printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector);
+		return ERROR;
+	}
+
+	pos = FLASH_SECTOR_POS (dev, sector);
+
+	if (dev->bank != FLASH0_BANK) {
+		return ERROR;
+	}
+
+	addr = pos;
+
+	FLASH0_WRITE (dev, 0xaaa, 0xaa);
+	FLASH0_WRITE (dev, 0x555, 0x55);
+	FLASH0_WRITE (dev, 0xaaa, 0x80);
+	FLASH0_WRITE (dev, 0xaaa, 0xaa);
+	FLASH0_WRITE (dev, 0x555, 0x55);
+	FLASH0_WRITE (dev, addr, 0x30);
+
+	return flashWait (dev, addr, 0xff, 1);
+}
+
+/*
+ * Note: it takes about as long to flash all sectors together with Chip
+ * Erase as it does to flash them one at a time (about 30 seconds for 2
+ * MB).  Also since we want to be able to treat subsets of sectors as if
+ * they were complete devices, we don't use Chip Erase.
+ */
+
+STATUS flashErase (flash_dev_t * dev)
+{
+	int sector;
+
+	PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	for (sector = 0; sector < dev->sectors; sector++) {
+		if (flashEraseSector (dev, sector) == ERROR)
+			return ERROR;
+	}
+	return OK;
+}
+
+/*
+ * Read and write bytes
+ */
+
+STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len)
+{
+	int addr, words;
+
+	PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n",
+		DEV_NO (dev), pos, (int) buf, len);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) {
+		printf ("flashRead: Position out of range "
+			"(dev: %d, pos: 0x%x, len: 0x%x)\n",
+			DEV_NO (dev), pos, len);
+		return ERROR;
+	}
+
+	if (len == 0)
+		return OK;
+
+	if (dev->bank == FLASH0_BANK) {
+		addr = pos;
+		words = len;
+
+		PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n",
+			(int) buf, (int) FLASH0_ADDR (dev, pos), len);
+
+		memcpy (buf, FLASH0_ADDR (dev, addr), words);
+
+	}
+	PRINTF ("flashRead: rv=OK\n");
+
+	return OK;
+}
+
+STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len)
+{
+	int addr, words;
+
+	PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n",
+		DEV_NO (dev), pos, (int) buf, len);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) {
+		printf ("flashWrite: Position out of range "
+			"(dev: %d, pos: 0x%x, len: 0x%x)\n",
+			DEV_NO (dev), pos, len);
+		return ERROR;
+	}
+
+	if (len == 0)
+		return OK;
+
+	if (dev->bank == FLASH0_BANK) {
+		unsigned char tmp;
+
+		addr = pos;
+		words = len;
+
+		while (words--) {
+			tmp = *buf;
+			if (~FLASH0_READ (dev, addr) & tmp) {
+				printf ("flashWrite: Attempt to program 0 to 1 "
+					"(dev: %d, addr: 0x%x, data: 0x%x)\n",
+					DEV_NO (dev), addr, tmp);
+				return ERROR;
+			}
+			FLASH0_WRITE (dev, 0xaaa, 0xaa);
+			FLASH0_WRITE (dev, 0x555, 0x55);
+			FLASH0_WRITE (dev, 0xaaa, 0xa0);
+			FLASH0_WRITE (dev, addr, tmp);
+			if (flashWait (dev, addr, tmp, 0) < 0)
+				return ERROR;
+			buf++;
+			addr++;
+		}
+	}
+
+	PRINTF ("flashWrite: rv=OK\n");
+
+	return OK;
+}
+
+/*
+ * flashWritable returns TRUE if a range contains all F's.
+ */
+
+STATUS flashWritable (flash_dev_t * dev, int pos, int len)
+{
+	int addr, words;
+	int rv = ERROR;
+
+	PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n",
+			DEV_NO (dev), pos, len);
+
+	if (flashCheck (dev) == ERROR)
+		goto done;
+
+	if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) {
+		printf ("flashWritable: Position out of range "
+			"(dev: %d, pos: 0x%x, len: 0x%x)\n",
+			DEV_NO (dev), pos, len);
+		goto done;
+	}
+
+	if (len == 0) {
+		rv = 1;
+		goto done;
+	}
+
+	if (dev->bank == FLASH0_BANK) {
+		addr = pos;
+		words = len;
+
+		while (words--) {
+			if (FLASH0_READ (dev, addr) != 0xff) {
+				rv = 0;
+				goto done;
+			}
+			addr++;
+		}
+	}
+
+	rv = 1;
+
+  done:
+	PRINTF ("flashWrite: rv=%d\n", rv);
+	return rv;
+}
+
+
+/*
+ * NOTE: the below code cannot run from FLASH!!!
+ */
+/***********************************************************************
+ *
+ * Flash Diagnostics
+ *
+ ***********************************************************************/
+
+STATUS flashDiag (flash_dev_t * dev)
+{
+	unsigned int *buf = 0;
+	int i, len, sector;
+	int rv = ERROR;
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	printf ("flashDiag: Testing device %d, "
+		"base: 0x%x, %d sectors @ %d kB = %d kB\n",
+		DEV_NO (dev), dev->base,
+		dev->sectors,
+		1 << (dev->lgSectorSize - 10),
+		dev->sectors << (dev->lgSectorSize - 10));
+
+	len = 1 << dev->lgSectorSize;
+
+	printf ("flashDiag: Erasing\n");
+
+	if (flashErase (dev) == ERROR) {
+		printf ("flashDiag: Erase failed\n");
+		goto done;
+	}
+	printf ("%d bytes requested ...\n", len);
+	buf = malloc (len);
+	printf ("allocated %d bytes ...\n", len);
+	if (buf == 0) {
+		printf ("flashDiag: Out of memory\n");
+		goto done;
+	}
+
+	/*
+	 * Write unique counting pattern to each sector
+	 */
+
+	for (sector = 0; sector < dev->sectors; sector++) {
+		printf ("flashDiag: Write sector %d\n", sector);
+
+		for (i = 0; i < len / 4; i++)
+			buf[i] = sector << 24 | i;
+
+		if (flashWrite (dev,
+				sector << dev->lgSectorSize,
+				(char *) buf, len) == ERROR) {
+			printf ("flashDiag: Write failed (dev: %d, sector: %d)\n",
+				DEV_NO (dev), sector);
+			goto done;
+		}
+	}
+
+	/*
+	 * Verify
+	 */
+
+	for (sector = 0; sector < dev->sectors; sector++) {
+		printf ("flashDiag: Verify sector %d\n", sector);
+
+		if (flashRead (dev,
+				   sector << dev->lgSectorSize,
+				   (char *) buf, len) == ERROR) {
+			printf ("flashDiag: Read failed (dev: %d, sector: %d)\n",
+				DEV_NO (dev), sector);
+			goto done;
+		}
+
+		for (i = 0; i < len / 4; i++) {
+			if (buf[i] != (sector << 24 | i)) {
+				printf ("flashDiag: Verify error "
+					"(dev: %d, sector: %d, offset: 0x%x)\n",
+					DEV_NO (dev), sector, i);
+				printf ("flashDiag: Expected 0x%08x, got 0x%08x\n",
+					sector << 24 | i, buf[i]);
+
+				goto done;
+			}
+		}
+	}
+
+	printf ("flashDiag: Erasing\n");
+
+	if (flashErase (dev) == ERROR) {
+		printf ("flashDiag: Final erase failed\n");
+		goto done;
+	}
+
+	rv = OK;
+
+  done:
+	if (buf)
+		free (buf);
+
+	if (rv == OK)
+		printf ("flashDiag: Device %d passed\n", DEV_NO (dev));
+	else
+		printf ("flashDiag: Device %d failed\n", DEV_NO (dev));
+
+	return rv;
+}
+
+STATUS flashDiagAll (void)
+{
+	int i;
+	int rv = OK;
+
+	PRINTF ("flashDiagAll: devices=%d\n", flashDevCount);
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		if (dev->found && flashDiag (dev) == ERROR)
+			rv = ERROR;
+	}
+
+	if (rv == OK)
+		printf ("flashDiagAll: Passed\n");
+	else
+		printf ("flashDiagAll: Failed because of earlier errors\n");
+
+	return OK;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	flash_dev_t *dev = NULL;
+
+	flashLibInit ();
+
+	/*
+	 * Provide info for FLASH (up to 960K) of Kernel Image data.
+	 */
+	dev = FLASH_DEV_BANK0_LOW;
+	flash_info[FLASH_BANK_KERNEL].flash_id =
+			(dev->vendorID << 16) | dev->deviceID;
+	flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors;
+	flash_info[FLASH_BANK_KERNEL].size =
+			flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE;
+	flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base;
+	size += flash_info[FLASH_BANK_KERNEL].size;
+
+	/*
+	 * Provide info for 512K PLCC FLASH ROM (U-Boot)
+	 */
+	dev = FLASH_DEV_BANK0_BOOT;
+	flash_info[FLASH_BANK_BOOT].flash_id =
+			(dev->vendorID << 16) | dev->deviceID;
+	flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors;
+	flash_info[FLASH_BANK_BOOT].size =
+			flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE;
+	flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base;
+	size += flash_info[FLASH_BANK_BOOT].size;
+
+
+	/*
+	 * Provide info for 512K FLASH0 segment (U-Boot)
+	 */
+	dev = FLASH_DEV_BANK0_HIGH;
+	flash_info[FLASH_BANK_AUX].flash_id =
+			(dev->vendorID << 16) | dev->deviceID;
+	flash_info[FLASH_BANK_AUX].sector_count = dev->sectors;
+	flash_info[FLASH_BANK_AUX].size =
+			flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE;
+	flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base;
+	size += flash_info[FLASH_BANK_AUX].size;
+
+
+	return size;
+}
+
+/*
+ * Get flash device from U-Boot flash info.
+ */
+flash_dev_t *getFlashDevFromInfo (flash_info_t * info)
+{
+	int i;
+
+	if (!info)
+		return NULL;
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		if (dev->found && (dev->base == info->start[0]))
+			return dev;
+	}
+	printf ("ERROR: notice, no FLASH mapped at address 0x%x\n",
+			(unsigned int) info->start[0]);
+	return NULL;
+}
+
+ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	int i;
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		if (dev->found) {
+			if (dev->base == (unsigned int) addr) {
+				info->flash_id = (dev->vendorID << 16) | dev->deviceID;
+				info->sector_count = dev->sectors;
+				info->size = info->sector_count * FLASH_SECTOR_SIZE;
+				return dev->sectors * FLASH_SECTOR_SIZE;
+			}
+		}
+	}
+	return 0;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	unsigned int chip;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+	chip = (unsigned int) info->flash_id & 0x000000ff;
+
+	switch (chip) {
+
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+
+	case AMD_ID_LV160B:
+	case FLASH_AM160LV:
+	case 0x49:
+		printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type:0x%x\n", chip);
+		break;
+	}
+
+	printf ("  Size: %ld bytes in %d Sectors\n",
+		info->size, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE,
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+
+/*
+ * Erase a range of flash sectors.
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	int prot, sect, l_sect;
+	flash_dev_t *dev = NULL;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Start erase on unprotected sectors */
+	dev = getFlashDevFromInfo (info);
+	if (dev) {
+		printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors);
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (vu_long *) (dev->base);
+				/*   printf("erase_sector: sector=%d, addr=0x%x\n",
+				   sect, addr); */
+				printf (".");
+				if (ERROR == flashEraseSector (dev, sect)) {
+					printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name);
+					return 1;
+				}
+			}
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+
+	flash_dev_t *dev = getFlashDevFromInfo (info);
+	int addr = dest - info->start[0];
+
+	if (!dev)
+		return 1;
+
+	if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) {
+		printf ("ERROR: could not write to addr=0x%x, data=0x%x\n",
+			(unsigned int) addr, (unsigned) data);
+		return 1;
+	}
+
+	if ((addr % FLASH_SECTOR_SIZE) == 0)
+		printf (".");
+
+
+	PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n",
+		(unsigned) info->start[0],
+		(unsigned) dest,
+		(unsigned) (dest - info->start[0]), (unsigned) data);
+
+	return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	flash_dev_t *dev = getFlashDevFromInfo (info);
+
+	if (dev) {
+		printf ("FLASH[%s]:", dev->name);
+		wp = (addr & ~3);	/* get lower word aligned address */
+
+		/*
+		 * handle unaligned start bytes
+		 */
+		if ((l = addr - wp) != 0) {
+			data = 0;
+			for (i = 0, cp = wp; i < l; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+			for (; i < 4 && cnt > 0; ++i) {
+				data = (data << 8) | *src++;
+				--cnt;
+				++cp;
+			}
+			for (; cnt == 0 && i < 4; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+			if ((rc = write_word (info, wp, data)) != 0) {
+				return (rc);
+			}
+			wp += 4;
+		}
+
+		/*
+		 * handle word aligned part
+		 */
+		while (cnt >= 4) {
+			data = 0;
+			for (i = 0; i < 4; ++i) {
+				data = (data << 8) | *src++;
+			}
+			if ((rc = write_word (info, wp, data)) != 0) {
+				return (rc);
+			}
+			wp += 4;
+			cnt -= 4;
+		}
+
+		if (cnt == 0) {
+			return (0);
+		}
+
+		/*
+		 * handle unaligned tail bytes
+		 */
+		data = 0;
+		for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+			data = (data << 8) | *src++;
+			--cnt;
+		}
+		for (; i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		return (write_word (info, wp, data));
+	}
+	return 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/mousse/flash.h b/u-boot/board/mousse/flash.h
new file mode 100644
index 0000000..b7e4619
--- /dev/null
+++ b/u-boot/board/mousse/flash.h
@@ -0,0 +1,78 @@
+#ifndef	FLASH_LIB_H
+#define	FLASH_LIB_H
+
+#include <common.h>
+
+/* PIO operations max */
+#define	FLASH_PROGRAM_POLLS		100000
+
+/* 10 Seconds default */
+#define	FLASH_ERASE_SECTOR_TIMEOUT	(10*1000 /*SEC*/ )
+
+/* Flash device info structure */
+typedef struct flash_dev_s {
+    char        name[24];               /* Bank Name */
+    int		bank;			/* Bank 0 or 1 */
+    unsigned int base;			/* Base address */
+    int		sectors;		/* Sector count */
+    int		lgSectorSize;		/* Log2(usable bytes/sector) */
+    int		vendorID;		/* Expected vendor ID */
+    int		deviceID;		/* Expected device ID */
+    int		found;			/* Set if found by flashLibInit */
+    int		swap;			/* Set for bank 1 if byte swap req'd */
+} flash_dev_t;
+
+#define FLASH_MAX_POS(dev) \
+	((dev)->sectors << (dev)->lgSectorSize)
+
+#define FLASH_SECTOR_POS(dev, sector) \
+	((sector) << (dev)->lgSectorSize)
+
+/* AMD 29F040 */
+#define FLASH0_BANK			0
+#define FLASH0_VENDOR_ID		0x01
+#define FLASH0_DEVICE_ID		0x49
+
+/* AMD29LV160DB */
+#define FLASH1_BANK			1
+#define FLASH1_VENDOR_ID		0x0001
+#define FLASH1_DEVICE_ID		0x2249
+
+extern	flash_dev_t			flashDev[];
+extern	int				flashDevCount;
+
+/*
+ * Device pointers
+ *
+ * These must be kept in sync with the table in flashLib.c.
+ */
+#define FLASH_DEV_BANK0_SA0		(&flashDev[0])
+#define FLASH_DEV_BANK0_SA1		(&flashDev[1])
+#define FLASH_DEV_BANK0_SA2		(&flashDev[2])
+#define FLASH_DEV_BANK0_LOW		(&flashDev[3]) /* 960K */
+#define FLASH_DEV_BANK0_BOOT		(&flashDev[4]) /* PLCC */
+#define FLASH_DEV_BANK0_HIGH		(&flashDev[5]) /* 512K PLCC shadow */
+
+unsigned long flash_init(void);
+int flashEraseSector(flash_dev_t *dev, int sector);
+int flashErase(flash_dev_t *dev);
+int flashRead(flash_dev_t *dev, int pos, char *buf, int len);
+int flashWrite(flash_dev_t *dev, int pos, char *buf, int len);
+int flashWritable(flash_dev_t *dev, int pos, int len);
+int flashDiag(flash_dev_t *dev);
+int flashDiagAll(void);
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+void flash_print_info  (flash_info_t *info);
+int  flash_erase (flash_info_t *info, int s_first, int s_last);
+int  write_buff  (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+/*
+ * Flash info indices.
+ */
+#define FLASH_BANK_KERNEL 0
+#define FLASH_BANK_BOOT   1
+#define FLASH_BANK_AUX    2
+#define FIRST_SECTOR      0
+
+#endif	/* !FLASH_LIB_H */
diff --git a/u-boot/board/mousse/m48t59y.c b/u-boot/board/mousse/m48t59y.c
new file mode 100644
index 0000000..beb26fe
--- /dev/null
+++ b/u-boot/board/mousse/m48t59y.c
@@ -0,0 +1,324 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
+ * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
+ * registers which are used to set/get the internal date/time functions.
+ *
+ * This module implements Y2K compliance by taking full year numbers
+ * and translating back and forth from the TOD 2-digit year.
+ *
+ * NOTE: for proper interaction with an operating system, the TOD should
+ * be used to store Universal Coordinated Time (GMT) and timezone
+ * conversions should be used.
+ *
+ * Here is a diagram of the memory layout:
+ *
+ * +---------------------------------------------+ 0xffe0a000
+ * | Non-volatile memory                         | .
+ * |                                             | .
+ * | (8176 bytes of Non-volatile memory)         | .
+ * |                                             | .
+ * +---------------------------------------------+ 0xffe0bff0
+ * | Flags                                       |
+ * +---------------------------------------------+ 0xffe0bff1
+ * | Unused                                      |
+ * +---------------------------------------------+ 0xffe0bff2
+ * | Alarm Seconds                               |
+ * +---------------------------------------------+ 0xffe0bff3
+ * | Alarm Minutes                               |
+ * +---------------------------------------------+ 0xffe0bff4
+ * | Alarm Date                                  |
+ * +---------------------------------------------+ 0xffe0bff5
+ * | Interrupts                                  |
+ * +---------------------------------------------+ 0xffe0bff6
+ * | WatchDog                                    |
+ * +---------------------------------------------+ 0xffe0bff7
+ * | Calibration                                 |
+ * +---------------------------------------------+ 0xffe0bff8
+ * | Seconds                                     |
+ * +---------------------------------------------+ 0xffe0bff9
+ * | Minutes                                     |
+ * +---------------------------------------------+ 0xffe0bffa
+ * | Hours                                       |
+ * +---------------------------------------------+ 0xffe0bffb
+ * | Day                                         |
+ * +---------------------------------------------+ 0xffe0bffc
+ * | Date                                        |
+ * +---------------------------------------------+ 0xffe0bffd
+ * | Month                                       |
+ * +---------------------------------------------+ 0xffe0bffe
+ * | Year (2 digits only)                        |
+ * +---------------------------------------------+ 0xffe0bfff
+ */
+#include <common.h>
+#include <rtc.h>
+#include "mousse.h"
+
+/*
+ * Imported from mousse.h:
+ *
+ *   TOD_REG_BASE		Base of m48t59y TOD registers
+ *   SYS_TOD_UNPROTECT()	Disable NVRAM write protect
+ *   SYS_TOD_PROTECT()		Re-enable NVRAM write protect
+ */
+
+#define YEAR		0xf
+#define MONTH		0xe
+#define DAY		0xd
+#define DAY_OF_WEEK	0xc
+#define HOUR		0xb
+#define MINUTE		0xa
+#define SECOND		0x9
+#define CONTROL		0x8
+#define WATCH		0x7
+#define INTCTL		0x6
+#define WD_DATE		0x5
+#define WD_HOUR		0x4
+#define WD_MIN		0x3
+#define WD_SEC		0x2
+#define _UNUSED		0x1
+#define FLAGS		0x0
+
+#define M48_ADDR	((volatile unsigned char *) TOD_REG_BASE)
+
+int m48_tod_init(void)
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] = 0;
+    M48_ADDR[WATCH] = 0;
+    M48_ADDR[INTCTL] = 0;
+
+    /*
+     * If the oscillator is currently stopped (as on a new part shipped
+     * from the factory), start it running.
+     *
+     * Here is an example of the TOD bytes on a brand new M48T59Y part:
+     *		00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
+     */
+
+    if (M48_ADDR[SECOND] & 0x80)
+	M48_ADDR[SECOND] = 0;
+
+    /* Is battery low */
+    if ( M48_ADDR[FLAGS] & 0x10) {
+	 printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
+    }
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * m48_tod_set
+ */
+
+static int to_bcd(int value)
+{
+    return value / 10 * 16 + value % 10;
+}
+
+static int from_bcd(int value)
+{
+    return value / 16 * 10 + value % 16;
+}
+
+static int day_of_week(int y, int m, int d)	/* 0-6 ==> Sun-Sat */
+{
+    static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
+    y -= m < 3;
+    return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_set(int year,		/* 1980-2079 */
+		int month,		/* 01-12 */
+		int day,		/* 01-31 */
+		int hour,		/* 00-23 */
+		int minute,		/* 00-59 */
+		int second)		/* 00-59 */
+
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x80;	/* Set WRITE bit */
+
+    M48_ADDR[YEAR] = to_bcd(year % 100);
+    M48_ADDR[MONTH] = to_bcd(month);
+    M48_ADDR[DAY] = to_bcd(day);
+    M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
+    M48_ADDR[HOUR] = to_bcd(hour);
+    M48_ADDR[MINUTE] = to_bcd(minute);
+    M48_ADDR[SECOND] = to_bcd(second);
+
+    M48_ADDR[CONTROL] &= ~0x80;	/* Clear WRITE bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_get(int *year,		/* 1980-2079 */
+		int *month,		/* 01-12 */
+		int *day,		/* 01-31 */
+		int *hour,		/* 00-23 */
+		int *minute,		/* 00-59 */
+		int *second)		/* 00-59 */
+{
+    int y;
+
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x40;	/* Set READ bit */
+
+    y = from_bcd(M48_ADDR[YEAR]);
+    *year = y < 80 ? 2000 + y : 1900 + y;
+    *month = from_bcd(M48_ADDR[MONTH]);
+    *day = from_bcd(M48_ADDR[DAY]);
+    /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
+    *hour = from_bcd(M48_ADDR[HOUR]);
+    *minute = from_bcd(M48_ADDR[MINUTE]);
+    *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
+
+    M48_ADDR[CONTROL] &= ~0x40;	/* Clear READ bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+int m48_tod_get_second(void)
+{
+    return from_bcd(M48_ADDR[SECOND] & 0x7f);
+}
+
+/*
+ * Watchdog function
+ *
+ *  If usec is 0, the watchdog timer is disarmed.
+ *
+ *  If usec is non-zero, the watchdog timer is armed (or re-armed) for
+ *    approximately usec microseconds (if the exact requested usec is
+ *    not supported by the chip, the next higher available value is used).
+ *
+ *  Minimum watchdog timeout = 62500 usec
+ *  Maximum watchdog timeout = 124 sec (124000000 usec)
+ */
+
+void m48_watchdog_arm(int usec)
+{
+    int		mpy, res;
+
+    SYS_TOD_UNPROTECT();
+
+    if (usec == 0) {
+	res = 0;
+	mpy = 0;
+    } else if (usec < 2000000) {	/* Resolution: 1/16s if below 2s */
+	res = 0;
+	mpy = (usec + 62499) / 62500;
+    } else if (usec < 8000000) {	/* Resolution: 1/4s if below 8s */
+	res = 1;
+	mpy = (usec + 249999) / 250000;
+    } else if (usec < 32000000) {	/* Resolution: 1s if below 32s */
+	res = 2;
+	mpy = (usec + 999999) / 1000000;
+    } else {				/* Resolution: 4s up to 124s */
+	res = 3;
+	mpy = (usec + 3999999) / 4000000;
+	if (mpy > 31)
+	    mpy = 31;
+    }
+
+    M48_ADDR[WATCH] = (0x80 |		/* Steer to RST signal (IRQ = N/C) */
+		       mpy << 2 |
+		       res);
+
+    SYS_TOD_PROTECT();
+}
+
+/*
+ * U-Boot RTC support.
+ */
+int
+rtc_get( struct rtc_time *tmp )
+{
+	m48_tod_get(&tmp->tm_year,
+		    &tmp->tm_mon,
+		    &tmp->tm_mday,
+		    &tmp->tm_hour,
+		    &tmp->tm_min,
+		    &tmp->tm_sec);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+#ifdef RTC_DEBUG
+	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
+#endif
+
+	return 0;
+}
+
+int rtc_set( struct rtc_time *tmp )
+{
+	m48_tod_set(tmp->tm_year,		/* 1980-2079 */
+		    tmp->tm_mon,		/* 01-12 */
+		    tmp->tm_mday,              /* 01-31 */
+		    tmp->tm_hour,		/* 00-23 */
+		    tmp->tm_min,		/* 00-59 */
+		    tmp->tm_sec);		/* 00-59 */
+
+#ifdef RTC_DEBUG
+	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+	return 0;
+}
+
+void
+rtc_reset (void)
+{
+  m48_tod_init();
+}
diff --git a/u-boot/board/mousse/m48t59y.h b/u-boot/board/mousse/m48t59y.h
new file mode 100644
index 0000000..717300d
--- /dev/null
+++ b/u-boot/board/mousse/m48t59y.h
@@ -0,0 +1,57 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M48_T59_Y_H
+#define __M48_T59_Y_H
+
+/*
+ * M48 T59Y -Timekeeping Battery backed SRAM.
+ */
+
+int m48_tod_init(void);
+
+int m48_tod_set(int year,
+		int month,
+		int day,
+		int hour,
+		int minute,
+		int second);
+
+int m48_tod_get(int *year,
+		int *month,
+		int *day,
+		int *hour,
+		int *minute,
+		int *second);
+
+int m48_tod_get_second(void);
+
+void m48_watchdog_arm(int usec);
+
+#endif /*!__M48_T59_Y_H */
diff --git a/u-boot/board/mousse/mousse.c b/u-boot/board/mousse/mousse.c
new file mode 100644
index 0000000..bd8d1c6
--- /dev/null
+++ b/u-boot/board/mousse/mousse.c
@@ -0,0 +1,93 @@
+/*
+ * MOUSSE Board Support
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty, jfd@cs.stanford.edu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <timestamp.h>
+
+#include "mousse.h"
+#include "m48t59y.h"
+#include <pci.h>
+
+
+int checkboard (void)
+{
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+
+	puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n");
+	printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
+	printf ("MPLD:  Revision %d\n", SYS_REVID_GET ());
+	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
+
+	return 0;
+}
+
+int checkflash (void)
+{
+	printf ("checkflash\n");
+	flash_init ();
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return CONFIG_SYS_RAM_SIZE;
+}
+
+
+void get_tod (void)
+{
+	int year, month, day, hour, minute, second;
+
+	m48_tod_get (&year, &month, &day, &hour, &minute, &second);
+
+	printf ("  Current date/time: %d/%d/%d %d:%d:%d \n",
+		month, day, year, hour, minute, second);
+
+}
+
+/*
+ * EPIC, PCI, and I/O devices.
+ * Initialize Mousse Platform, probe for PCI devices,
+ * Query configuration parameters if not set.
+ */
+int misc_init_f (void)
+{
+	m48_tod_init ();	/* Init SGS M48T59Y TOD/NVRAM */
+	printf ("RTC:   M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE);
+	get_tod ();
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/mousse/mousse.h b/u-boot/board/mousse/mousse.h
new file mode 100644
index 0000000..10a0062
--- /dev/null
+++ b/u-boot/board/mousse/mousse.h
@@ -0,0 +1,259 @@
+/*
+ * MOUSSE/MPC8240 Board definitions.
+ * For more info, see http://www.vooha.com/
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MOUSSE_H
+#define __MOUSSE_H
+
+/* System addresses */
+
+#define PCI_SPECIAL_BASE	0xfe000000
+#define PCI_SPECIAL_SIZE	0x01000000
+
+/* PORTX Device Addresses for Mousse */
+
+#define PORTX_DEV_BASE		0xff000000
+#define PORTX_DEV_SIZE		0x01000000
+
+#define ENET_DEV_BASE		0x80000000
+
+#define PLD_REG_BASE		(PORTX_DEV_BASE | 0xe09000)
+#define PLD_REG(off)		(*(volatile unsigned char *) \
+				 (PLD_REG_BASE + (off)))
+
+#define PLD_REVID_B1		0x7f
+#define PLD_REVID_B2		0x01
+
+/* MPLD */
+#define SYS_HARD_RESET()	{ for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
+#define SYS_REVID_GET()		((int) PLD_REG(0) & 0x7f)
+#define SYS_LED_OFF()		(PLD_REG(1) |= 0x80)
+#define SYS_LED_ON()		(PLD_REG(1) &= ~0x80)
+#define SYS_WATCHDOG_IRQ3()	(PLD_REG(2) |= 0x80)
+#define SYS_WATCHDOG_RESET()	(PLD_REG(2) &= ~0x80)
+#define SYS_TOD_PROTECT()	(PLD_REG(3) |= 0x80)
+#define SYS_TOD_UNPROTECT()	(PLD_REG(3) &= ~0x80)
+
+/* SGS M48T59Y */
+#define TOD_BASE		(PORTX_DEV_BASE | 0xe0a000)
+#define TOD_REG_BASE		(TOD_BASE | 0x1ff0)
+#define TOD_NVRAM_BASE		TOD_BASE
+#define TOD_NVRAM_SIZE		0x1ff0
+#define TOD_NVRAM_LIMIT		(TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
+
+/* NS16552 SIO */
+#define SERIAL_BASE(_x)		(PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80))
+#define N_SIO_CHANNELS		2
+#define N_COM_PORTS		N_SIO_CHANNELS
+
+/*
+ * On-board Dec21143 PCI Ethernet
+ * Note: The PCI MBAR chosen here was used from MPC8240UM which states
+ * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS]
+ * is set, then PCI memory maps 1-1 with this address range in the
+ * correct byte order.
+ */
+#define PCI_ENET_IOADDR		0x80000000
+#define PCI_ENET_MEMADDR	0x80000000
+
+/*
+ * Flash Memory Layout
+ *
+ *    2 MB Flash Bank 0 runs in 8-bit mode.  In Flash Bank 0, the 32 kB
+ *    sector SA3 is obscured by the 32 kB serial/TOD access space, and
+ *    the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC
+ *    containing the fixed boot ROM.  (If the 512 kB PLCC is
+ *    deconfigured by jumper, this window to Flash Bank 0 becomes
+ *    visible, but it still contains the fixed boot code and should be
+ *    considered read-only).  Flash Bank 0 sectors SA0 (16 kB), SA1 (8
+ *    kB), and SA2 (8 kB) are currently unused.
+ *
+ *    2 MB Flash Bank 1 runs in 16-bit mode.  Flash Bank 1 is fully
+ *    usable, but it's a 16-bit wide device on a 64-bit bus.  Therefore
+ *    16-bit words only exist at addresses that are multiples of 8.  All
+ *    PROM data and control addresses must be multiplied by 8.
+ *
+ *    See flashMap.c for description of flash filesystem layout.
+ */
+
+/*
+ * FLASH memory address space: 8-bit wide FLASH memory spaces.
+ */
+#define FLASH0_SEG0_START	0xffe00000	 /* Baby 32Kb segment */
+#define FLASH0_SEG0_END		0xffe07fff	 /* 16 kB + 8 kB + 8 kB */
+#define FLASH0_SEG0_SIZE	0x00008000	 /*   (sectors SA0-SA2) */
+
+#define FLASH0_SEG1_START	0xffe10000	 /* 1MB - 64Kb FLASH0 seg */
+#define FLASH0_SEG1_END		0xffefffff	 /* 960 kB */
+#define FLASH0_SEG1_SIZE	0x000f0000
+
+#define FLASH0_SEG2_START	0xfff00000	 /* Boot Loader stored here */
+#define FLASH0_SEG2_END		0xfff7ffff	 /* 512 kB FLASH0/PLCC seg */
+#define FLASH0_SEG2_SIZE	0x00080000
+
+#define FLASH0_SEG3_START	0xfff80000	 /* 512 kB FLASH0 seg */
+#define FLASH0_SEG3_END		0xffffffff
+#define FLASH0_SEG3_SIZE	0x00080000
+
+/* Where Kahlua starts */
+#define FLASH_RESET_VECT	0xfff00100
+
+/*
+ * CHRP / PREP (MAP A/B) definitions.
+ */
+
+#define PREP_REG_ADDR		0x80000cf8	/* MPC107 Config, Map A */
+#define PREP_REG_DATA		0x80000cfc	/* MPC107 Config, Map A */
+/* MPC107 (MPC8240 internal EUMBBAR mapped) */
+#define CHRP_REG_ADDR		0xfec00000	/* MPC106 Config, Map B */
+#define CHRP_REG_DATA		0xfee00000	/* MPC106 Config, Map B */
+
+/*
+ * Mousse PCI IDSEL Assignments (Device Number)
+ */
+#define MOUSSE_IDSEL_ENET	13		/* On-board 21143 Ethernet */
+#define MOUSSE_IDSEL_LPCI	14		/* On-board PCI slot */
+#define MOUSSE_IDSEL_82371	15		/* That other thing */
+#define MOUSSE_IDSEL_CPCI2	31		/* CPCI slot 2 */
+#define MOUSSE_IDSEL_CPCI3	30		/* CPCI slot 3 */
+#define MOUSSE_IDSEL_CPCI4	29		/* CPCI slot 4 */
+#define MOUSSE_IDSEL_CPCI5	28		/* CPCI slot 5 */
+#define MOUSSE_IDSEL_CPCI6	27		/* CPCI slot 6 */
+
+/*
+ * Mousse Interrupt Mapping:
+ *
+ *	IRQ1	Enet (intA|intB|intC|intD)
+ *	IRQ2	CPCI intA (See below)
+ *	IRQ3	Local PCI slot intA|intB|intC|intD
+ *	IRQ4	COM1 Serial port (Actually higher addressed port on duart)
+ *
+ * PCI Interrupt Mapping in CPCI chassis:
+ *
+ *		   |	       CPCI Slot
+ *		   | 1 (CPU)	2	3	4	5	6
+ *	-----------+--------+-------+-------+-------+-------+-------+
+ *	  intA	   |	X		X		X
+ *	  intB	   |		X		X		X
+ *	  intC	   |	X		X		X
+ *	  intD	   |		X		X		X
+ */
+
+
+#define EPIC_VECTOR_EXT0	0
+#define EPIC_VECTOR_EXT1	1
+#define EPIC_VECTOR_EXT2	2
+#define EPIC_VECTOR_EXT3	3
+#define EPIC_VECTOR_EXT4	4
+#define EPIC_VECTOR_TM0		16
+#define EPIC_VECTOR_TM1		17
+#define EPIC_VECTOR_TM2		18
+#define EPIC_VECTOR_TM3		19
+#define EPIC_VECTOR_I2C		20
+#define EPIC_VECTOR_DMA0	21
+#define EPIC_VECTOR_DMA1	22
+#define EPIC_VECTOR_I2O		23
+
+
+#define INT_VEC_IRQ0		0
+#define INT_NUM_IRQ0		INT_VEC_IRQ0
+#define MOUSSE_IRQ_ENET		EPIC_VECTOR_EXT1	/* Hardwired */
+#define MOUSSE_IRQ_CPCI		EPIC_VECTOR_EXT2	/* Hardwired */
+#define MOUSSE_IRQ_LPCI		EPIC_VECTOR_EXT3	/* Hardwired */
+#define MOUSSE_IRQ_DUART	EPIC_VECTOR_EXT4	/* Hardwired */
+
+/* Onboard DEC 21143 Ethernet */
+#define PCI_ENET_MEMADDR	0x80000000
+#define PCI_ENET_IOADDR		0x80000000
+
+/* Some other PCI device */
+#define PCI_SLOT_MEMADDR	0x81000000
+#define PCI_SLOT_IOADDR		0x81000000
+
+/* Promise ATA66 PCI Device (ATA controller) */
+#define PROMISE_MBAR0  0xa0000000
+#define PROMISE_MBAR1  (PROMISE_MBAR0 + 0x1000)
+#define PROMISE_MBAR2  (PROMISE_MBAR0 + 0x2000)
+#define PROMISE_MBAR3  (PROMISE_MBAR0 + 0x3000)
+#define PROMISE_MBAR4  (PROMISE_MBAR0 + 0x4000)
+#define PROMISE_MBAR5  (PROMISE_MBAR0 + 0x5000)
+
+/* ATA/66 Controller offsets */
+#define CONFIG_SYS_ATA_BASE_ADDR     PROMISE_MBAR0
+#define CONFIG_SYS_IDE_MAXBUS	       2 /* ide0/ide1 */
+#define CONFIG_SYS_IDE_MAXDEVICE      2 /* 2 drives per controller */
+#define CONFIG_SYS_ATA_IDE0_OFFSET    0
+#define CONFIG_SYS_ATA_IDE1_OFFSET    0x3000
+/*
+ * Definitions for accessing IDE controller registers
+ */
+#define CONFIG_SYS_ATA_DATA_OFFSET    0
+#define CONFIG_SYS_ATA_REG_OFFSET     0
+#define CONFIG_SYS_ATA_ALT_OFFSET    (0x1000)
+
+/*
+ * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
+ * are defined in config.h and Makefile.
+ * All definitions for these constants must be identical.
+ */
+#define ROM_BASE_ADRS		0xfff00000	/* base address of ROM */
+#define ROM_TEXT_ADRS		(ROM_BASE_ADRS+0x0100) /* with PC & SP */
+#define ROM_WARM_ADRS		(ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
+#define ROM_SIZE		0x00080000	/* 512KB ROM space */
+#define RAM_LOW_ADRS		0x00010000   /* RAM address for vxWorks */
+#define RAM_HIGH_ADRS		0x00c00000   /* RAM address for bootrom */
+
+/*
+ *  NVRAM configuration
+ *  NVRAM is implemented via the SGS Thomson M48T59Y
+ *  64Kbit (8Kbx8) Timekeeper SRAM.
+ *  This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information.
+ */
+
+#define NV_RAM_ADRS		TOD_NVRAM_BASE
+#define NV_RAM_INTRVL		1
+#define NV_RAM_WR_ENBL		SYS_TOD_UNPROTECT()
+#define NV_RAM_WR_DSBL		SYS_TOD_PROTECT()
+
+#define NV_OFF_BOOT0		0x0000	/* Boot string 0 (256b) */
+#define NV_OFF_BOOT1		0x0100	/* Boot string 1 (256b) */
+#define NV_OFF_BOOT2		0x0200	/* Boot string 2 (256b)*/
+#define NV_OFF_MACADDR		0x0400	/* 21143 MAC address (6b) */
+#define NV_OFF_ACTIVEBOOT	0x0406	/* Active boot string, 0 to 2 (1b) */
+#define NV_OFF_UNUSED1		0x0407	/* Unused (1b) */
+#define NV_OFF_BINDFIX		0x0408	/* See sysLib.c:sysBindFix() (1b) */
+#define NV_OFF_UNUSED2		0x0409	/* Unused (7b) */
+#define NV_OFF_TIMEZONE		0x0410	/* TIMEZONE env var (64b) */
+#define NV_OFF_VXWORKS_END	0x07FF	/* 2047 VxWorks Total */
+#define NV_OFF_U_BOOT		0x0800	/* 2048 U-Boot boot-loader */
+#define NV_OFF_U_BOOT_ADDR	(TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/
+#define NV_U_BOOT_ENV_SIZE	2048	/* 2K - U-Boot Total */
+#define NV_OFF__next_free	(NV_U_BOOT_ENVSIZE +1)
+#define NV_RAM_SIZE		8176	/* NVRAM End */
+
+#endif /* __MOUSSE_H */
diff --git a/u-boot/board/mousse/pci.c b/u-boot/board/mousse/pci.c
new file mode 100644
index 0000000..4f39398
--- /dev/null
+++ b/u-boot/board/mousse/pci.c
@@ -0,0 +1,283 @@
+/*
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge
+ */
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+#include "mousse.h"
+
+/*
+ * Promise ATA/66 support.
+ */
+#define XFER_PIO_4	0x0C	/* 0000|1100 */
+#define XFER_PIO_3	0x0B	/* 0000|1011 */
+#define XFER_PIO_2	0x0A	/* 0000|1010 */
+#define XFER_PIO_1	0x09	/* 0000|1001 */
+#define XFER_PIO_0	0x08	/* 0000|1000 */
+#define XFER_PIO_SLOW	0x00	/* 0000|0000 */
+
+/* Promise Regs */
+#define REG_A		0x01
+#define REG_B		0x02
+#define REG_C		0x04
+#define REG_D		0x08
+
+void
+pdc202xx_decode_registers (unsigned char registers, unsigned char value)
+{
+	unsigned char	bit = 0, bit1 = 0, bit2 = 0;
+	switch(registers) {
+		case REG_A:
+			bit2 = 0;
+			printf("  A Register ");
+			if (value & 0x80) printf("SYNC_IN ");
+			if (value & 0x40) printf("ERRDY_EN ");
+			if (value & 0x20) printf("IORDY_EN ");
+			if (value & 0x10) printf("PREFETCH_EN ");
+			if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; }
+			if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; }
+			if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; }
+			if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; }
+			printf("PIO(A) = %d ", bit2);
+			break;
+		case REG_B:
+			bit1 = 0;bit2 = 0;
+			printf("  B Register ");
+			if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; }
+			if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; }
+			if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; }
+			printf("DMA(B) = %d ", bit1 >> 5);
+			if (value & 0x10) printf("PIO_FORCED/PB4 ");
+			if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; }
+			if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; }
+			if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; }
+			if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; }
+			printf("PIO(B) = %d ", bit2);
+			break;
+		case REG_C:
+			bit2 = 0;
+			printf("  C Register ");
+			if (value & 0x80) printf("DMARQp ");
+			if (value & 0x40) printf("IORDYp ");
+			if (value & 0x20) printf("DMAR_EN ");
+			if (value & 0x10) printf("DMAW_EN ");
+
+			if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; }
+			if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; }
+			if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; }
+			if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; }
+			printf("DMA(C) = %d ", bit2);
+			break;
+		case REG_D:
+			printf("  D Register ");
+			break;
+		default:
+			return;
+	}
+	printf("\n        %s ", (registers & REG_D) ? "DP" :
+				(registers & REG_C) ? "CP" :
+				(registers & REG_B) ? "BP" :
+				(registers & REG_A) ? "AP" : "ERROR");
+	for (bit=128;bit>0;bit/=2)
+		printf("%s", (value & bit) ? "1" : "0");
+	printf("\n");
+}
+
+/*
+ * Promise ATA/66 Support: configure Promise ATA66 card in specified mode.
+ */
+int
+pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed)
+{
+	unsigned short		drive_conf;
+	int			err = 0;
+	unsigned char			drive_pci, AP, BP, CP, DP;
+	unsigned char			TA = 0, TB = 0;
+
+	switch (drive) {
+		case 0: drive_pci = 0x60; break;
+		case 1: drive_pci = 0x64; break;
+		case 2: drive_pci = 0x68; break;
+		case 3: drive_pci = 0x6c; break;
+		default: return -1;
+	}
+
+	pci_read_config_word(dev, drive_pci, &drive_conf);
+	pci_read_config_byte(dev, (drive_pci), &AP);
+	pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
+	pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
+
+	if ((AP & 0x0F) || (BP & 0x07)) {
+	  /* clear PIO modes of lower 8421 bits of A Register */
+	  pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
+	  pci_read_config_byte(dev, (drive_pci), &AP);
+
+	  /* clear PIO modes of lower 421 bits of B Register */
+	  pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
+	  pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+
+	  pci_read_config_byte(dev, (drive_pci), &AP);
+	  pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	}
+
+	pci_read_config_byte(dev, (drive_pci), &AP);
+	pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
+
+	switch(speed) {
+		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
+		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
+		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
+		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
+		case XFER_PIO_0:
+		default:		TA = 0x09; TB = 0x13; break;
+	}
+
+	pci_write_config_byte(dev, (drive_pci), AP|TA);
+	pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
+
+	pci_read_config_byte(dev, (drive_pci), &AP);
+	pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
+	pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
+
+
+#ifdef PDC202XX_DEBUG
+	pdc202xx_decode_registers(REG_A, AP);
+	pdc202xx_decode_registers(REG_B, BP);
+	pdc202xx_decode_registers(REG_C, CP);
+	pdc202xx_decode_registers(REG_D, DP);
+#endif
+	return err;
+}
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+
+void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned int line;
+
+	switch(PCI_DEV(dev)) {
+	case 0x0d:
+		line = 0x00000101;
+		break;
+
+	case 0x0e:
+	default:
+		line = 0x00000303;
+		break;
+	}
+
+	pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line);
+}
+
+void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev,
+			       struct pci_config_table *_)
+{
+	unsigned short vendorId;
+	unsigned int mbar0, cmd;
+	int bar, a;
+
+	pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId);
+
+	if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){
+		/* PDC 202xx card is handled differently, it is a bootable
+		 * device and needs all 5 MBAR's configured
+		 */
+		for(bar = 0; bar < 5; bar++){
+			pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
+			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0);
+			pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
+#ifdef DEBUG
+			printf("  ATA_bar[%d] = %dbytes\n", bar,
+			       ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+#endif
+		}
+
+		/* Program all BAR's */
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_2,	PROMISE_MBAR2);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_3,	PROMISE_MBAR3);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_4,	PROMISE_MBAR4);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_5,	PROMISE_MBAR5);
+
+		for(bar = 0; bar < 5; bar++){
+			pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
+#ifdef DEBUG
+			printf("  ATA_bar[%d]@0x%x\n", bar, mbar0);
+#endif
+		}
+
+		/* Enable ROM Expansion base */
+		pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1);
+
+		/* Io enable, Memory enable, master enable */
+		pci_read_config_dword(dev, PCI_COMMAND, &cmd);
+		cmd &= ~0xffff0000;
+		cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+		pci_write_config_dword(dev, PCI_COMMAND, cmd);
+
+		/* Breath some life into the controller */
+		for( a = 0; a < 4; a++)
+			pdc202xx_tune_chipset(dev, a, XFER_PIO_0);
+	}
+}
+
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00,
+	  pci_mousse_setup_pdc202xx },
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00,
+	  pci_cfgfunc_config_device, {PCI_ENET_IOADDR,
+				      PCI_ENET_MEMADDR,
+				      PCI_COMMAND_MEMORY |
+				      PCI_COMMAND_MASTER}},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, {PCI_SLOT_IOADDR,
+				      PCI_SLOT_MEMADDR,
+				      PCI_COMMAND_MEMORY |
+				      PCI_COMMAND_MASTER}},
+#endif
+	{ }
+};
+
+struct pci_controller hose = {
+	config_table: pci_sandpoint_config_table,
+	fixup_irq: pci_mousse_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/u-boot/board/mousse/u-boot.lds b/u-boot/board/mousse/u-boot.lds
new file mode 100644
index 0000000..4cfb95c
--- /dev/null
+++ b/u-boot/board/mousse/u-boot.lds
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/powerpc/cpu/mpc824x/start.o	(.text*)
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mousse/u-boot.lds.ram b/u-boot/board/mousse/u-boot.lds.ram
new file mode 100644
index 0000000..449d064
--- /dev/null
+++ b/u-boot/board/mousse/u-boot.lds.ram
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+MEMORY {
+	ram  (!rx) : org = 0x00000000 , LENGTH = 8M
+	code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000)
+	rom   (rx) : org = 0xfff00000 , LENGTH = 512K
+}
+
+SECTIONS
+{
+  _f_init = .;
+  PROVIDE(_f_init = .);
+  _f_init_rom = .;
+  PROVIDE(_f_init_rom = .);
+
+  .init : {
+      arch/powerpc/cpu/mpc824x/start.o	(.text)
+      *(.init)
+  } > ram
+  _init_size = SIZEOF(.init);
+  PROVIDE(_init_size = SIZEOF(.init));
+
+  ENTRY(_start)
+
+/*  _ftext = .;
+  _ftext_rom = .;
+  _text_size = SIZEOF(.text);
+ */
+  .text : {
+      *(.text)
+      *(.got1)
+      } > ram
+  .rodata : { *(.rodata) } > ram
+  .dtors : { *(.dtors) } > ram
+  .data : { *(.data) } > ram
+  .sdata : { *(.sdata) } > ram
+  .sdata2 : { *(.sdata2)
+      *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+    } > ram
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .sbss : { *(.sbss) } > ram
+  .sbss2 : { *(.sbss2) } > ram
+  .bss : { *(.bss) } > ram
+  .debug : { *(.debug) } > ram
+  .line : { *(.line) } > ram
+  .symtab : { *(.symtab) } > ram
+  .shrstrtab : { *(.shstrtab) } > ram
+  .strtab : { *(.strtab) } > ram
+ /* .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  } > ram
+  */
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+   __start___ex_table = .;
+    __ex_table : { *(__ex_table) } > ram
+    __stop___ex_table = .;
+
+
+  .ppcenv	:
+  {
+    common/env_embedded.o (.ppcenv)
+  } > ram
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mousse/u-boot.lds.rom b/u-boot/board/mousse/u-boot.lds.rom
new file mode 100644
index 0000000..4f42b32
--- /dev/null
+++ b/u-boot/board/mousse/u-boot.lds.rom
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    arch/powerpc/cpu/mpc824x/start.o	(.text)
+	 common/board.o (.text)
+    arch/powerpc/lib/ppcstring.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    lib/zlib.o		(.text)
+
+		. = env_offset;
+    common/env_embedded.o (.text)
+
+		*(.text)
+
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mp2usb/Makefile b/u-boot/board/mp2usb/Makefile
new file mode 100644
index 0000000..335734a
--- /dev/null
+++ b/u-boot/board/mp2usb/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mp2usb.o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mp2usb/config.mk b/u-boot/board/mp2usb/config.mk
new file mode 100644
index 0000000..948e4ff
--- /dev/null
+++ b/u-boot/board/mp2usb/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE = 0x27F00000
+## For testing: load at 0x20100000 and "go" at 0x201000A4
+#CONFIG_SYS_TEXT_BASE = 0x20100000
diff --git a/u-boot/board/mp2usb/flash.c b/u-boot/board/mp2usb/flash.c
new file mode 100644
index 0000000..21a8ef9
--- /dev/null
+++ b/u-boot/board/mp2usb/flash.c
@@ -0,0 +1,552 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define PHYS_FLASH_SECT_SIZE	0x00020000 /* 128 KB sectors (x1) */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			__swab16(x)
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM	0x00100010
+#define INTEL_ERASE	0x00200020
+#define INTEL_PROG	0x00400040
+#define INTEL_CLEAR	0x00500050
+#define INTEL_LOCKBIT	0x00600060
+#define INTEL_PROTECT	0x00010001
+#define INTEL_STATUS	0x00700070
+#define INTEL_READID	0x00900090
+#define INTEL_SUSPEND	0x00B000B0
+#define INTEL_CONFIRM	0x00D000D0
+#define INTEL_RESET	0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED	0x00800080
+#define INTEL_OK	0x00800080
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) INTEL_RESET;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) INTEL_RESET;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+	int cflag, iflag;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	/* Disable interrupts which might cause a timeout here */
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) INTEL_CLEAR;	/* clear status register */
+			*addr = (FPW) INTEL_ERASE;	/* erase setup */
+			*addr = (FPW) INTEL_CONFIRM;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) INTEL_SUSPEND;	/* suspend erase     */
+					*addr = (FPW) INTEL_RESET;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPWV)INTEL_CLEAR;	/* clear status register cmd.   */
+			*addr = (FPWV)INTEL_RESET;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	/* get lower word aligned address */
+	wp = (addr & ~1);
+	port_width = 2;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int cflag, iflag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
+		return (2);
+	}
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	/* Disable interrupts which might cause a timeout here */
+	iflag = disable_interrupts ();
+
+	*addr = (FPW) INTEL_PROG;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) INTEL_RESET;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int i;
+	int rc = 0;
+	FPWV *addr = (FPWV *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = (FPW) INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = (FPW) INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = (FPW) INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = (FPW) INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = (FPW) INTEL_CONFIRM;	/* clear */
+	}
+
+	reset_timer_masked ();
+
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != (FPW) INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				reset_timer_masked ();
+				addr = (FPWV *) (info->start[i]);
+				*addr = (FPW) INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = (FPW) INTEL_PROTECT;	/* set */
+				while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED)
+				{
+					if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = (FPW) INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/u-boot/board/mp2usb/mp2usb.c b/u-boot/board/mp2usb/mp2usb.c
new file mode 100644
index 0000000..e5eba6b
--- /dev/null
+++ b/u-boot/board/mp2usb/mp2usb.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <netdev.h>
+#include <asm/io.h>
+#if defined(CONFIG_DRIVER_ETHER)
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#endif
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of MP2USB-Board. */
+	gd->bd->bi_arch_number = MACH_TYPE_MP2USB;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif
+#endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/u-boot/board/mpc8308_p1m/Makefile b/u-boot/board/mpc8308_p1m/Makefile
new file mode 100644
index 0000000..241a557
--- /dev/null
+++ b/u-boot/board/mpc8308_p1m/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mpc8308_p1m/mpc8308_p1m.c b/u-boot/board/mpc8308_p1m/mpc8308_p1m.c
new file mode 100644
index 0000000..d92833b
--- /dev/null
+++ b/u-boot/board/mpc8308_p1m/mpc8308_p1m.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: MPC8308 P1M\n");
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/u-boot/board/mpc8308_p1m/sdram.c b/u-boot/board/mpc8308_p1m/sdram.c
new file mode 100644
index 0000000..a6e44e6
--- /dev/null
+++ b/u-boot/board/mpc8308_p1m/sdram.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This files is  mostly identical to the original from
+ * board/freescale/mpc8308rdb/sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/u-boot/board/mpl/common/common_util.c b/u-boot/board/mpl/common/common_util.c
new file mode 100644
index 0000000..d3300ed
--- /dev/null
+++ b/u-boot/board/mpl/common/common_util.c
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <video_fb.h>
+#include "common_util.h"
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <i2c.h>
+#include <pci.h>
+#include <malloc.h>
+#include <bzlib.h>
+
+#ifdef CONFIG_PIP405
+#include "../pip405/pip405.h"
+#include <asm/4xx_pci.h>
+#endif
+#ifdef CONFIG_MIP405
+#include "../mip405/mip405.h"
+#include <asm/4xx_pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PATI)
+#define FIRM_START 0xFFF00000
+#endif
+
+extern int mem_test(ulong start, ulong ramsize, int quiet);
+
+#define I2C_BACKUP_ADDR 0x7C00		/* 0x200 bytes for backup */
+#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN	/* ugly, but it works for now */
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+static int
+mpl_prg(uchar *src, ulong size)
+{
+	ulong start;
+	flash_info_t *info;
+	int i, rc;
+#if defined(CONFIG_PATI)
+	int start_sect;
+#endif
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+	char *copystr = (char *)src;
+	ulong *magic = (ulong *)src;
+#endif
+
+	info = &flash_info[0];
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+	if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
+		puts("Bad Magic number\n");
+		return -1;
+	}
+	/* some more checks before we delete the Flash... */
+	/* Checking the ISO_STRING prevents to program a
+	 * wrong Firmware Image into the flash.
+	 */
+	i = 4; /* skip Magic number */
+	while (1) {
+		if (strncmp(&copystr[i], "MEV-", 4) == 0)
+			break;
+		if (i++ >= 0x100) {
+			puts("Firmware Image for unknown Target\n");
+			return -1;
+		}
+	}
+	/* we have the ISO STRING, check */
+	if (strncmp(&copystr[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) {
+		printf("Wrong Firmware Image: %s\n", &copystr[i]);
+		return -1;
+	}
+#if !defined(CONFIG_PATI)
+	start = 0 - size;
+	for (i = info->sector_count-1; i > 0; i--) {
+		info->protect[i] = 0; /* unprotect this sector */
+		if (start >= info->start[i])
+			break;
+	}
+	/* set-up flash location */
+	/* now erase flash */
+	printf("Erasing at %lx (sector %d) (start %lx)\n",
+				start,i,info->start[i]);
+	if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) {
+		puts("ERROR ");
+		flash_perror(rc);
+		return (1);
+	}
+
+#else /* #if !defined(CONFIG_PATI */
+	start = FIRM_START;
+	start_sect = -1;
+	for (i = 0; i < info->sector_count; i++) {
+		if (start < info->start[i]) {
+			start_sect = i - 1;
+			break;
+		}
+	}
+
+	info->protect[i - 1] = 0;	/* unprotect this sector */
+	for (; i < info->sector_count; i++) {
+		if ((start + size) < info->start[i])
+			break;
+		info->protect[i] = 0;	/* unprotect this sector */
+	}
+
+	i--;
+	/* set-up flash location */
+	/* now erase flash */
+	printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n",
+		start, start + size, start_sect, i,
+		info->start[start_sect], info->start[i]);
+	if ((rc = flash_erase (info, start_sect, i)) != 0) {
+		puts ("ERROR ");
+		flash_perror (rc);
+		return (1);
+	}
+#endif /* defined(CONFIG_PATI) */
+
+#elif defined(CONFIG_VCMA9)
+	start = 0;
+	for (i = 0; i <info->sector_count; i++) {
+		info->protect[i] = 0; /* unprotect this sector */
+		if (size < info->start[i])
+		    break;
+	}
+	/* set-up flash location */
+	/* now erase flash */
+	printf("Erasing at %lx (sector %d) (start %lx)\n",
+				start,0,info->start[0]);
+	if ((rc = flash_erase (info, 0, i)) != 0) {
+		puts("ERROR ");
+		flash_perror(rc);
+		return (1);
+	}
+
+#endif
+	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
+		(ulong)src, size);
+	if ((rc = flash_write ((char *)src, start, size)) != 0) {
+		puts("ERROR ");
+		flash_perror(rc);
+		return (1);
+	}
+	puts("OK programming done\n");
+	return 0;
+}
+
+
+static int
+mpl_prg_image(uchar *ld_addr)
+{
+	unsigned long len;
+	uchar *data;
+	image_header_t *hdr = (image_header_t *)ld_addr;
+	int rc;
+
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	if (!image_check_magic (hdr)) {
+		puts("Bad Magic Number\n");
+		return 1;
+	}
+	image_print_contents (hdr);
+	if (!image_check_os (hdr, IH_OS_U_BOOT)) {
+		puts("No U-Boot Image\n");
+		return 1;
+	}
+	if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+		puts("No Firmware Image\n");
+		return 1;
+	}
+	if (!image_check_hcrc (hdr)) {
+		puts("Bad Header Checksum\n");
+		return 1;
+	}
+	puts("Verifying Checksum ... ");
+	if (!image_check_dcrc (hdr)) {
+		puts("Bad Data CRC\n");
+		return 1;
+	}
+	puts("OK\n");
+
+	data = (uchar *)image_get_data (hdr);
+	len = image_get_data_size (hdr);
+
+	if (image_get_comp (hdr) != IH_COMP_NONE) {
+		uchar *buf;
+		/* reserve space for uncompressed image */
+		if ((buf = malloc(IMAGE_SIZE)) == NULL) {
+			puts("Insufficient space for decompression\n");
+			return 1;
+		}
+
+		switch (image_get_comp (hdr)) {
+		case IH_COMP_GZIP:
+			puts("Uncompressing (GZIP) ... ");
+			rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
+			if (rc != 0) {
+				puts("GUNZIP ERROR\n");
+				free(buf);
+				return 1;
+			}
+			puts("OK\n");
+			break;
+#ifdef CONFIG_BZIP2
+		case IH_COMP_BZIP2:
+			puts("Uncompressing (BZIP2) ... ");
+			{
+			uint retlen = IMAGE_SIZE;
+			rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen,
+				(char *)data, len, 0, 0);
+			len = retlen;
+			}
+			if (rc != BZ_OK) {
+				printf ("BUNZIP2 ERROR: %d\n", rc);
+				free(buf);
+				return 1;
+			}
+			puts("OK\n");
+			break;
+#endif
+		default:
+			printf ("Unimplemented compression type %d\n",
+				image_get_comp (hdr));
+			free(buf);
+			return 1;
+		}
+
+		rc = mpl_prg(buf, len);
+		free(buf);
+	} else {
+		rc = mpl_prg(data, len);
+	}
+
+	return(rc);
+}
+
+#if !defined(CONFIG_PATI)
+void get_backup_values(backup_t *buf)
+{
+	i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
+}
+
+void set_backup_values(int overwrite)
+{
+	backup_t back;
+	int i;
+
+	get_backup_values(&back);
+	if(!overwrite) {
+		if(strncmp(back.signature,"MPL\0",4)==0) {
+			puts("Not possible to write Backup\n");
+			return;
+		}
+	}
+	memcpy(back.signature,"MPL\0",4);
+	i = getenv_f("serial#",back.serial_name,16);
+	if(i < 0) {
+		puts("Not possible to write Backup\n");
+		return;
+	}
+	back.serial_name[16]=0;
+	i = getenv_f("ethaddr",back.eth_addr,20);
+	if(i < 0) {
+		puts("Not possible to write Backup\n");
+		return;
+	}
+	back.eth_addr[20]=0;
+	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+}
+
+void clear_env_values(void)
+{
+	backup_t back;
+	unsigned char env_crc[4];
+
+	memset(&back,0xff,sizeof(backup_t));
+	memset(env_crc,0x00,4);
+	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
+}
+
+/*
+ * check crc of "older" environment
+ */
+int check_env_old_size(ulong oldsize)
+{
+	ulong crc, len, new;
+	unsigned off;
+	uchar buf[64];
+
+	/* read old CRC */
+	eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
+		     CONFIG_ENV_OFFSET,
+		     (uchar *)&crc, sizeof(ulong));
+
+	new = 0;
+	len = oldsize;
+	off = sizeof(long);
+	len = oldsize-off;
+	while (len > 0) {
+		int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+
+		eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
+		new = crc32 (new, buf, n);
+		len -= n;
+		off += n;
+	}
+
+	return (crc == new);
+}
+
+static ulong oldsizes[] = {
+	0x200,
+	0x800,
+	0
+};
+
+void copy_old_env(ulong size)
+{
+	uchar name_buf[64];
+	uchar value_buf[0x800];
+	uchar c;
+	ulong len;
+	unsigned off;
+	uchar *name, *value;
+
+	name = &name_buf[0];
+	value = &value_buf[0];
+	len=size;
+	off = sizeof(long);
+	while (len > off) {
+		eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
+		if(c != '=') {
+			*name++=c;
+			off++;
+		}
+		else {
+			*name++='\0';
+			off++;
+			do {
+				eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
+				*value++=c;
+				off++;
+				if(c == '\0')
+					break;
+			} while(len > off);
+			name = &name_buf[0];
+			value = &value_buf[0];
+			if(strncmp((char *)name,"baudrate",8)!=0) {
+				setenv((char *)name,(char *)value);
+			}
+
+		}
+	}
+}
+
+
+void check_env(void)
+{
+	char *s;
+	int i=0;
+	char buf[32];
+	backup_t back;
+
+	s=getenv("serial#");
+	if(!s) {
+		while(oldsizes[i]) {
+			if(check_env_old_size(oldsizes[i]))
+				break;
+			i++;
+		}
+		if(!oldsizes[i]) {
+			/* no old environment has been found */
+			get_backup_values (&back);
+			if (strncmp (back.signature, "MPL\0", 4) == 0) {
+				sprintf (buf, "%s", back.serial_name);
+				setenv ("serial#", buf);
+				sprintf (buf, "%s", back.eth_addr);
+				setenv ("ethaddr", buf);
+				printf ("INFO:  serial# and ethaddr recovered, use saveenv\n");
+				return;
+			}
+		}
+		else {
+			copy_old_env(oldsizes[i]);
+			puts("INFO:  old environment ajusted, use saveenv\n");
+		}
+	}
+	else {
+		/* check if back up is set */
+		get_backup_values(&back);
+		if(strncmp(back.signature,"MPL\0",4)!=0) {
+			set_backup_values(0);
+		}
+	}
+}
+
+#endif /* #if !defined(CONFIG_PATI) */
+
+int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong ld_addr;
+	int result;
+#if !defined(CONFIG_PATI)
+	ulong size = IMAGE_SIZE;
+	ulong src = MULTI_PURPOSE_SOCKET_ADDR;
+	backup_t back;
+#endif
+
+	if (strcmp(argv[1], "flash") == 0)
+	{
+#if defined(CONFIG_CMD_FDC)
+		if (strcmp(argv[2], "floppy") == 0) {
+			char *local_args[3];
+			extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
+			puts("\nupdating bootloader image from floppy\n");
+			local_args[0] = argv[0];
+			if(argc==4) {
+				local_args[1] = argv[3];
+				local_args[2] = NULL;
+				ld_addr=simple_strtoul(argv[3], NULL, 16);
+				result=do_fdcboot(cmdtp, 0, 2, local_args);
+			}
+			else {
+				local_args[1] = NULL;
+				ld_addr=CONFIG_SYS_LOAD_ADDR;
+				result=do_fdcboot(cmdtp, 0, 1, local_args);
+			}
+			result=mpl_prg_image((uchar *)ld_addr);
+			return result;
+		}
+#endif
+		if (strcmp(argv[2], "mem") == 0) {
+			if(argc==4) {
+				ld_addr=simple_strtoul(argv[3], NULL, 16);
+			}
+			else {
+				ld_addr=load_addr;
+			}
+			printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
+			result=mpl_prg_image((uchar *)ld_addr);
+			return result;
+		}
+#if !defined(CONFIG_PATI)
+		if (strcmp(argv[2], "mps") == 0) {
+			puts("\nupdating bootloader image from MPS\n");
+			result=mpl_prg((uchar *)src,size);
+			return result;
+		}
+#endif /* #if !defined(CONFIG_PATI)	*/
+	}
+#if !defined(CONFIG_PATI)
+	if (strcmp(argv[1], "clearenvvalues") == 0)
+	{
+		if (strcmp(argv[2], "yes") == 0)
+		{
+			clear_env_values();
+			return 0;
+		}
+	}
+	if (strcmp(argv[1], "getback") == 0) {
+		get_backup_values(&back);
+		back.signature[3]=0;
+		back.serial_name[16]=0;
+		back.eth_addr[20]=0;
+		printf("GetBackUp: signature: %s\n",back.signature);
+		printf("           serial#:   %s\n",back.serial_name);
+		printf("           ethaddr:   %s\n",back.eth_addr);
+		return 0;
+	}
+	if (strcmp(argv[1], "setback") == 0) {
+		set_backup_values(1);
+		return 0;
+	}
+#endif
+	return cmd_usage(cmdtp);
+}
+
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+  doc_probe(MULTI_PURPOSE_SOCKET_ADDR);
+}
+#endif
+
+
+#ifdef CONFIG_VIDEO
+/******************************************************
+ * Routines to display the Board information
+ * to the screen (since the VGA will be initialized as last,
+ * we must resend the infos)
+ */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice ctfb;
+extern int get_boot_mode(void);
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	PPC4xx_SYS_INFO sys_info;
+	char rev;
+	int i,boot;
+	unsigned long pvr;
+	char buf[64];
+	char buf1[32], buf2[32], buf3[32], buf4[32];
+	char cpustr[16];
+	char *s, *e, bc;
+	switch (line_number)
+	{
+	case 2:
+		/* CPU and board infos */
+		pvr=get_pvr();
+		get_sys_info (&sys_info);
+		switch (pvr) {
+			case PVR_405GP_RB: rev='B'; break;
+			case PVR_405GP_RC: rev='C'; break;
+			case PVR_405GP_RD: rev='D'; break;
+			case PVR_405GP_RE: rev='E'; break;
+			case PVR_405GPR_RB: rev='B'; break;
+			default:           rev='?'; break;
+		}
+		if(pvr==PVR_405GPR_RB)
+			sprintf(cpustr,"PPC405GPr %c",rev);
+		else
+			sprintf(cpustr,"PPC405GP %c",rev);
+		/* Board info */
+		i=0;
+		s=getenv ("serial#");
+#ifdef CONFIG_PIP405
+		if (!s || strncmp (s, "PIP405", 6)) {
+			sprintf(buf,"### No HW ID - assuming PIP405");
+		}
+#endif
+#ifdef CONFIG_MIP405
+		if (!s || strncmp (s, "MIP405", 6)) {
+			sprintf(buf,"### No HW ID - assuming MIP405");
+		}
+#endif
+		else {
+			for (e = s; *e; ++e) {
+				if (*e == ' ')
+					break;
+			}
+			for (; s < e; ++s) {
+				if (*s == '_') {
+					++s;
+					break;
+				}
+				buf[i++] = *s;
+			}
+			sprintf(&buf[i]," SN ");
+			i+=4;
+			for (; s < e; ++s) {
+				buf[i++] = *s;
+			}
+			buf[i++]=0;
+		}
+		sprintf (info," %s %s %s MHz (%s/%s/%s MHz)",
+			buf, cpustr,
+			strmhz (buf1, gd->cpu_clk),
+			strmhz (buf2, sys_info.freqPLB),
+			strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv),
+			strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv));
+		return;
+	case 3:
+		/* Memory Info */
+		boot = get_boot_mode();
+		bc = in8 (CONFIG_PORT_ADDR);
+		sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
+			gd->bd->bi_memsize / 0x100000,
+			gd->bd->bi_flashsize / 0x100000,
+			bc,
+			(boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
+			ctfb.modeIdent);
+		return;
+	case 1:
+		sprintf	(buf, "%s",CONFIG_IDENT_STRING);
+		sprintf (info, " %s", &buf[1]);
+		return;
+    }
+    /* no more info lines */
+    *info = 0;
+    return;
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+#endif /* CONFIG_VIDEO */
diff --git a/u-boot/board/mpl/common/common_util.h b/u-boot/board/mpl/common/common_util.h
new file mode 100644
index 0000000..29cd14f
--- /dev/null
+++ b/u-boot/board/mpl/common/common_util.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _COMMON_UTIL_H_
+#define _COMMON_UTIL_H_
+
+typedef struct {
+	char signature[4];
+	char serial_name[17];	/* "MIP405_1000xxxxx" */
+	char eth_addr[21];	/* "00:60:C2:0a:00:00" */
+} backup_t;
+
+void get_backup_values(backup_t *buf);
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
+#define BOOT_MPS	0x01
+#define BOOT_PCI	0x02
+#endif
+
+void check_env(void);
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void);
+#endif
+
+#endif /* _COMMON_UTIL_H_ */
diff --git a/u-boot/board/mpl/common/flash.c b/u-boot/board/mpl/common/flash.c
new file mode 100644
index 0000000..61f031a
--- /dev/null
+++ b/u-boot/board/mpl/common/flash.c
@@ -0,0 +1,886 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Modified 3/7/2001
+ * - adapted for pip405, Denis Peter, MPL AG Switzerland
+ * TODO:
+ * clean-up
+ */
+
+#include <common.h>
+
+#if !defined(CONFIG_PATI)
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include "common_util.h"
+#if defined(CONFIG_MIP405)
+#include "../mip405/mip405.h"
+#endif
+#if defined(CONFIG_PIP405)
+#include "../pip405/pip405.h"
+#endif
+#include <asm/4xx_pci.h>
+#else /* defined(CONFIG_PATI) */
+#include <mpc5xx.h>
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned short
+
+#define FALSE           0
+#define TRUE            1
+
+#if !defined(CONFIG_PATI)
+
+/*-----------------------------------------------------------------------
+ * Some CS switching routines:
+ *
+ * On PIP/MIP405 we have 3 (4) possible boot mode
+ *
+ * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from MPS   (Flash CS = CS1, MPS CS = CS0)
+ * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from PCI with MPS map   (Flash CS = CS1, MPS CS = CS0)
+ * The flash init is the first board specific routine which is called
+ * after code relocation (running from SDRAM)
+ * The first thing we do is to map the Flash CS to the Flash area and
+ * the MPS CS to the MPS area. Since the flash size is unknown at this
+ * point, we use the max flash size and the lowest flash address as base.
+ *
+ * After flash detection we adjust the size of the CS area accordingly.
+ * The board_init_r will fill in wrong values in the board init structure,
+ * but this will be fixed in the misc_init_r routine:
+ * bd->bi_flashstart=0-flash_info[0].size
+ * bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN
+ * bd->bi_flashoffset=0
+ *
+ */
+int get_boot_mode(void)
+{
+	unsigned long pbcr;
+	int res = 0;
+	pbcr = mfdcr (CPC0_PSR);
+	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
+		/* boot via MPS or MPS mapping */
+		res = BOOT_MPS;
+	if(pbcr & PSR_ROM_LOC)
+		/* boot via PCI.. */
+		res |= BOOT_PCI;
+	 return res;
+}
+
+/* Map the flash high (in boot area)
+   This code can only be executed from SDRAM (after relocation).
+*/
+void setup_cs_reloc(void)
+{
+	int mode;
+	/* Since we are relocated, we can set-up the CS finaly
+	 * but first of all, switch off PCI mapping (in case it was a PCI boot) */
+	out32r(PMM0MA,0L);
+	icache_enable (); /* we are relocated */
+	/* get boot mode */
+	mode=get_boot_mode();
+	/* we map the flash high in every case */
+	/* first findout on which cs the flash is */
+	if(mode & BOOT_MPS) {
+		/* map flash high on CS1 and MPS on CS0 */
+		mtdcr (EBC0_CFGADDR, PB0AP);
+		mtdcr (EBC0_CFGDATA, MPS_AP);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		mtdcr (EBC0_CFGDATA, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (EBC0_CFGADDR, PB1AP);
+		mtdcr (EBC0_CFGDATA, FLASH_AP);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		mtdcr (EBC0_CFGDATA, FLASH_CR_B);
+	}
+	else {
+		/* map flash high on CS0 and MPS on CS1 */
+		mtdcr (EBC0_CFGADDR, PB1AP);
+		mtdcr (EBC0_CFGDATA, MPS_AP);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		mtdcr (EBC0_CFGDATA, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (EBC0_CFGADDR, PB0AP);
+		mtdcr (EBC0_CFGDATA, FLASH_AP);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		mtdcr (EBC0_CFGDATA, FLASH_CR_B);
+	}
+}
+
+#endif /* #if !defined(CONFIG_PATI) */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+#if !defined(CONFIG_PATI)
+	unsigned long size_b1,flashcr,size_reg;
+	int mode;
+	extern char version_string;
+	char *p = &version_string;
+
+	/* Since we are relocated, we can set-up the CS finally */
+	setup_cs_reloc();
+	/* get and display boot mode */
+	mode=get_boot_mode();
+	if(mode & BOOT_PCI)
+		printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ?
+			"MPS" : "Flash");
+	else
+		printf("(%s Boot) ",(mode & BOOT_MPS) ?
+			"MPS" : "Flash");
+#endif /* #if !defined(CONFIG_PATI) */
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_MONITOR_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+	/* protect the bootloader */
+	/* Monitor protection ON by default */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			&flash_info[0]);
+#endif
+#if !defined(CONFIG_PATI)
+	/* protect reset vector */
+	flash_info[0].protect[flash_info[0].sector_count-1] = 1;
+	size_b1 = 0 ;
+	flash_info[0].size = size_b0;
+	/* set up flash cs according to the size */
+	size_reg=(flash_info[0].size >>20);
+	switch (size_reg) {
+		case 0:
+		case 1: i=0; break; /* <= 1MB */
+		case 2: i=1; break; /* = 2MB */
+		case 4: i=2; break; /* = 4MB */
+		case 8: i=3; break; /* = 8MB */
+		case 16: i=4; break; /* = 16MB */
+		case 32: i=5; break; /* = 32MB */
+		case 64: i=6; break; /* = 64MB */
+		case 128: i=7; break; /*= 128MB */
+		default:
+			printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
+			while(1);
+	}
+	if(mode & BOOT_MPS) {
+		/* flash is on CS1 */
+		mtdcr(EBC0_CFGADDR, PB1CR);
+		flashcr = mfdcr (EBC0_CFGDATA);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (i << 17); /* size addr */
+		mtdcr(EBC0_CFGADDR, PB1CR);
+		mtdcr(EBC0_CFGDATA, flashcr);
+	}
+	else {
+		/* flash is on CS0 */
+		mtdcr(EBC0_CFGADDR, PB0CR);
+		flashcr = mfdcr (EBC0_CFGDATA);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (i << 17); /* size addr */
+		mtdcr(EBC0_CFGADDR, PB0CR);
+		mtdcr(EBC0_CFGDATA, flashcr);
+	}
+#if 0
+	/* enable this (PIP405/MIP405 only) if you want to test if
+	   the relocation has be done ok.
+	   This will disable both Chipselects */
+	mtdcr (EBC0_CFGADDR, PB0CR);
+	mtdcr (EBC0_CFGDATA, 0L);
+	mtdcr (EBC0_CFGADDR, PB1CR);
+	mtdcr (EBC0_CFGDATA, 0L);
+	printf("CS0 & CS1 switched off for test\n");
+#endif
+	/* patch version_string */
+	for(i=0;i<0x100;i++) {
+		if(*p=='\n') {
+			*p=0;
+			break;
+		}
+		p++;
+	}
+#else /* #if !defined(CONFIG_PATI) */
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif /* #if !defined(CONFIG_PATI) */
+	return (size_b0);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_INTEL320T:	printf ("TE28F320C3 (32 Mbit, top sector size)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640U (64 Mbit, uniform sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		*/
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+
+*/
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[0];
+	/*	printf("flash_get_size value: %x\n",value); */
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+	value = addr2[1];			/* device ID		*/
+	/*	printf("Device value %x\n",value);		    */
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#if 0	/* enable when device IDs are available */
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#endif
+	case (FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (FLASH_WORD_SIZE)INTEL_ID_28F320C3T:
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+
+	case (FLASH_WORD_SIZE)SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* base address calculation */
+	base=0-info->size;
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	     (info->flash_id  == FLASH_AM040) ||
+	     (info->flash_id  == FLASH_AM640U)){
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+	else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++)
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+		else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			if(info->sector_count==71) {
+
+				info->start[i--] = base + info->size - 0x00002000;
+				info->start[i--] = base + info->size - 0x00004000;
+				info->start[i--] = base + info->size - 0x00006000;
+				info->start[i--] = base + info->size - 0x00008000;
+				info->start[i--] = base + info->size - 0x0000A000;
+				info->start[i--] = base + info->size - 0x0000C000;
+				info->start[i--] = base + info->size - 0x0000E000;
+				for (; i >= 0; i--)
+					info->start[i] = base + i * 0x000010000;
+			}
+			else {
+				info->start[i--] = base + info->size - 0x00004000;
+				info->start[i--] = base + info->size - 0x00006000;
+				info->start[i--] = base + info->size - 0x00008000;
+				for (; i >= 0; i--)
+					info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return ERR_OK;
+}
+
+int intel_wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last, status;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	status = addr[0] & (FLASH_WORD_SIZE)0x00280028;
+	/* clear status register */
+	addr[0] = (FLASH_WORD_SIZE)0x00500050;
+	/* check status for block erase fail and VPP low */
+	return (status == 0 ? ERR_OK : ERR_NOT_ERASED);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i, rcode = 0;
+
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			/*  printf("Erasing sector %p\n", addr2); */ /* CLH */
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+				rcode |= wait_for_DQ7(info, sect);
+			}
+			else {
+				if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+					addr2[0] = (FLASH_WORD_SIZE)0x00600060;  /* unlock sector */
+					addr2[0] = (FLASH_WORD_SIZE)0x00D000D0;  /* sector erase */
+					intel_wait_for_DQ7(info, sect);
+					addr2[0] = (FLASH_WORD_SIZE)0x00200020;  /* sector erase */
+					addr2[0] = (FLASH_WORD_SIZE)0x00D000D0;  /* sector erase */
+					rcode |= intel_wait_for_DQ7(info, sect);
+				}
+				else {
+					addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+					addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+					addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+					addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+					addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+					addr2[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+					rcode |= wait_for_DQ7(info, sect);
+				}
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			/*   wait_for_DQ7(info, sect); */
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7(info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	if (!rcode)
+	    printf (" done\n");
+
+	return rcode;
+}
+
+
+void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt)
+{
+	int i;
+	volatile FLASH_WORD_SIZE *addr2;
+	long c;
+	c= (long)cnt;
+	for(i=info->sector_count-1;i>0;i--)
+	{
+		if(addr>=info->start[i])
+			break;
+	}
+	do {
+		addr2 = (FLASH_WORD_SIZE *)(info->start[i]);
+		addr2[0] = (FLASH_WORD_SIZE)0x00600060;  /* unlock sector setup */
+		addr2[0] = (FLASH_WORD_SIZE)0x00D000D0;  /* unlock sector */
+		intel_wait_for_DQ7(info, i);
+		i++;
+		c-=(info->start[i]-info->start[i-1]);
+	}while(c>0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+		unlock_intel_sectors(info,addr,cnt);
+	}
+	wp = (addr & ~3);	/* get lower word aligned address */
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		if((wp % 0x10000)==0)
+			printf("."); /* show Progress */
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	rc=write_word(info, wp, data);
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000;
+
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (volatile FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2;
+	ulong start;
+	ulong *data_p;
+	int flag;
+	int i;
+
+	data_p = &data;
+	data2 = (volatile FLASH_WORD_SIZE *)data_p;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *)dest) &
+		(FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	{
+		if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+			/* intel style writting */
+			dest2[i] = (FLASH_WORD_SIZE)0x00500050;
+			dest2[i] = (FLASH_WORD_SIZE)0x00400040;
+			*read_val++ = data2[i];
+			dest2[i] = data2[i];
+			if (flag)
+				enable_interrupts();
+			/* data polling for D7 */
+			start = get_timer (0);
+			udelay(10);
+			while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080)
+			{
+				if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+					return (1);
+			}
+			dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */
+			udelay(10);
+			dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */
+			if(dest2[i]!=data2[i])
+				printf("Error at %p 0x%04X != 0x%04X\n",&dest2[i],dest2[i],data2[i]);
+		}
+		else {
+			addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+			dest2[i] = data2[i];
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+			/* data polling for D7 */
+			start = get_timer (0);
+			while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+				(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+				if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+					return (1);
+				}
+			}
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/mpl/common/isa.c b/u-boot/board/mpl/common/isa.c
new file mode 100644
index 0000000..5d467b4
--- /dev/null
+++ b/u-boot/board/mpl/common/isa.c
@@ -0,0 +1,494 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <stdio_dev.h>
+#include "isa.h"
+#include "piix4_pci.h"
+#include "kbd.h"
+#include "video.h"
+
+
+#undef	ISA_DEBUG
+
+#ifdef	ISA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#ifndef	TRUE
+#define TRUE            1
+#endif
+#ifndef FALSE
+#define FALSE           0
+#endif
+
+#if defined(CONFIG_PIP405)
+
+extern int drv_isa_kbd_init (void);
+
+/* fdc (logical device 0) */
+const SIO_LOGDEV_TABLE sio_fdc[] = {
+	{0x60, 3},			/* set IO to FDPort (3F0) */
+	{0x61, 0xF0},		/* set IO to FDPort (3F0) */
+	{0x70, 06},			/* set IRQ 6 for FDPort */
+	{0x74, 02},			/* set DMA 2 for FDPort */
+	{0xF0, 0x05},		/* set to PS2 type */
+	{0xF1, 0x00},	  /* default value */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* paralell port (logical device 3) */
+const SIO_LOGDEV_TABLE sio_pport[] = {
+	{0x60, 3},			/* set IO to PPort (378) */
+	{0x61, 0x78},		/* set IO to PPort (378) */
+	{0x70, 07},			/* set IRQ 7 for PPort */
+	{0xF1, 00},			/* set PPort to normal */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* paralell port (logical device 3) Floppy assigned to lpt */
+const SIO_LOGDEV_TABLE sio_pport_fdc[] = {
+	{0x60, 3},			/* set IO to PPort (378) */
+	{0x61, 0x78},		/* set IO to PPort (378) */
+	{0x70, 07},			/* set IRQ 7 for PPort */
+	{0xF1, 02},			/* set PPort to Floppy */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* uart 1 (logical device 4) */
+const SIO_LOGDEV_TABLE sio_com1[] = {
+	{0x60, 3},			/* set IO to COM1 (3F8) */
+	{0x61, 0xF8},		/* set IO to COM1 (3F8) */
+	{0x70, 04},			/* set IRQ 4 for COM1 */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* uart 2 (logical device 5) */
+const SIO_LOGDEV_TABLE sio_com2[] = {
+	{0x60, 2},			/* set IO to COM2 (2F8) */
+	{0x61, 0xF8},		/* set IO to COM2 (2F8) */
+	{0x70, 03},			/* set IRQ 3 for COM2 */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+
+/* keyboard controller (logical device 7) */
+const SIO_LOGDEV_TABLE sio_keyboard[] = {
+	{0x70, 1},			/* set IRQ 1 for keyboard */
+	{0x72, 12},			/* set IRQ 12 for mouse */
+	{0xF0, 0},			/* disable Port92 (this is a PowerPC!!) */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+
+
+/*******************************************************************************
+* Config SuperIO FDC37C672
+********************************************************************************/
+unsigned char open_cfg_super_IO(int address)
+{
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
+	if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
+		return TRUE;
+	else
+		return FALSE;
+}
+
+void close_cfg_super_IO(int address)
+{
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
+}
+
+
+unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
+{
+	/* assuming config reg is open */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+	return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1);
+}
+
+void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
+{
+	/* assuming config reg is open */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
+}
+
+void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
+{
+	while (ldt->index != 0xFF) {
+		write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val);
+		ldt++;
+	} /* endwhile */
+}
+
+void isa_sio_loadtable(void)
+{
+	char *s = getenv("floppy");
+	/* setup Floppy device 0*/
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
+	/* setup parallel port device 3 */
+	if(s && !strncmp(s, "lpt", 3)) {
+		printf("SIO:   Floppy assigned to LPT\n");
+		/* floppy is assigned to the LPT */
+		isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3);
+	}
+	else {
+		/*printf("Floppy assigned to internal port\n");*/
+		isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3);
+	}
+	/* setup Com1 port device 4 */
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4);
+	/* setup Com2 port device 5 */
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5);
+	/* setup keyboards device 7 */
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7);
+}
+
+
+void isa_sio_setup(void)
+{
+	if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE)
+	{
+		isa_sio_loadtable();
+		close_cfg_super_IO(0x3F0);
+	}
+}
+#endif
+
+/******************************************************************************
+ * IRQ Controller
+ * we use the Vector mode
+ */
+
+struct	isa_irq_action {
+	 interrupt_handler_t *handler;
+	 void *arg;
+	 int count;
+};
+
+static struct isa_irq_action isa_irqs[16];
+
+
+/*
+ * This contains the irq mask for both 8259A irq controllers,
+ */
+static unsigned int cached_irq_mask = 0xfff9;
+
+#define cached_imr1	(unsigned char)cached_irq_mask
+#define cached_imr2	(unsigned char)(cached_irq_mask>>8)
+#define IMR_1		CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
+#define IMR_2		CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
+#define ICW1_1	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
+#define ICW1_2	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
+#define ICW2_1	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
+#define ICW2_2	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
+#define ICW3_1	ICW2_1
+#define ICW3_2	ICW2_2
+#define ICW4_1	ICW2_1
+#define ICW4_2	ICW2_2
+#define ISR_1		ICW1_1
+#define ISR_2		ICW1_2
+
+
+void disable_8259A_irq(unsigned int irq)
+{
+	unsigned int mask = 1 << irq;
+
+	cached_irq_mask |= mask;
+	if (irq & 8)
+		out8(IMR_2,cached_imr2);
+	else
+		out8(IMR_1,cached_imr1);
+}
+
+void enable_8259A_irq(unsigned int irq)
+{
+	unsigned int mask = ~(1 << irq);
+
+	cached_irq_mask &= mask;
+	if (irq & 8)
+		out8(IMR_2,cached_imr2);
+	else
+		out8(IMR_1,cached_imr1);
+}
+/*
+int i8259A_irq_pending(unsigned int irq)
+{
+	unsigned int mask = 1<<irq;
+	int ret;
+
+	if (irq < 8)
+		ret = inb(0x20) & mask;
+	else
+		ret = inb(0xA0) & (mask >> 8);
+	spin_unlock_irqrestore(&i8259A_lock, flags);
+
+	return ret;
+}
+*/
+
+/*
+ * This function assumes to be called rarely. Switching between
+ * 8259A registers is slow.
+ */
+int i8259A_irq_real(unsigned int irq)
+{
+	int value;
+	int irqmask = 1<<irq;
+
+	if (irq < 8) {
+		out8(ISR_1,0x0B);		/* ISR register */
+		value = in8(ISR_1) & irqmask;
+		out8(ISR_1,0x0A);		/* back to the IRR register */
+		return value;
+	}
+	out8(ISR_2,0x0B);		/* ISR register */
+	value = in8(ISR_2) & (irqmask >> 8);
+	out8(ISR_2,0x0A);		/* back to the IRR register */
+	return value;
+}
+
+/*
+ * Careful! The 8259A is a fragile beast, it pretty
+ * much _has_ to be done exactly like this (mask it
+ * first, _then_ send the EOI, and the order of EOI
+ * to the two 8259s is important!
+ */
+void mask_and_ack_8259A(unsigned int irq)
+{
+	unsigned int irqmask = 1 << irq;
+	unsigned int temp_irqmask = cached_irq_mask;
+	/*
+	 * Lightweight spurious IRQ detection. We do not want
+	 * to overdo spurious IRQ handling - it's usually a sign
+	 * of hardware problems, so we only do the checks we can
+	 * do without slowing down good hardware unnecesserily.
+	 *
+	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
+	 * usually resulting from the 8259A-1|2 PICs) occur
+	 * even if the IRQ is masked in the 8259A. Thus we
+	 * can check spurious 8259A IRQs without doing the
+	 * quite slow i8259A_irq_real() call for every IRQ.
+	 * This does not cover 100% of spurious interrupts,
+	 * but should be enough to warn the user that there
+	 * is something bad going on ...
+	 */
+	if (temp_irqmask & irqmask)
+		goto spurious_8259A_irq;
+	temp_irqmask |= irqmask;
+
+handle_real_irq:
+	if (irq & 8) {
+		in8(IMR_2);		/* DUMMY - (do we need this?) */
+		out8(IMR_2,(unsigned char)(temp_irqmask>>8));
+		out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */
+		out8(ISR_1,0x62);	/* 'Specific EOI' to master-IRQ2 */
+		out8(IMR_2,cached_imr2); /* turn it on again */
+	} else {
+		in8(IMR_1);		/* DUMMY - (do we need this?) */
+		out8(IMR_1,(unsigned char)temp_irqmask);
+		out8(ISR_1,0x60+irq);	/* 'Specific EOI' to master */
+		out8(IMR_1,cached_imr1); /* turn it on again */
+	}
+
+	return;
+
+spurious_8259A_irq:
+	/*
+	 * this is the slow path - should happen rarely.
+	 */
+	if (i8259A_irq_real(irq))
+		/*
+		 * oops, the IRQ _is_ in service according to the
+		 * 8259A - not spurious, go handle it.
+		 */
+		goto handle_real_irq;
+
+	{
+		static int spurious_irq_mask;
+		/*
+		 * At this point we can be sure the IRQ is spurious,
+		 * lets ACK and report it. [once per IRQ]
+		 */
+		if (!(spurious_irq_mask & irqmask)) {
+			PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq);
+			spurious_irq_mask |= irqmask;
+		}
+		/* irq_err_count++; */
+		/*
+		 * Theoretically we do not have to handle this IRQ,
+		 * but in Linux this does not cause problems and is
+		 * simpler for us.
+		 */
+		goto handle_real_irq;
+	}
+}
+
+void init_8259A(void)
+{
+	out8(IMR_1,0xff);	/* mask all of 8259A-1 */
+	out8(IMR_2,0xff);	/* mask all of 8259A-2 */
+
+	out8(ICW1_1,0x11);	/* ICW1: select 8259A-1 init */
+	out8(ICW2_1,0x20 + 0);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
+	out8(ICW3_1,0x04);	/* 8259A-1 (the master) has a slave on IR2 */
+	out8(ICW4_1,0x01);	/* master expects normal EOI */
+	out8(ICW1_2,0x11);	/* ICW2: select 8259A-2 init */
+	out8(ICW2_2,0x20 + 8);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
+	out8(ICW3_2,0x02);	/* 8259A-2 is a slave on master's IR2 */
+	out8(ICW4_2,0x01);	/* (slave's support for AEOI in flat mode
+				    is to be investigated) */
+	udelay(10000);		/* wait for 8259A to initialize */
+	out8(IMR_1,cached_imr1);	/* restore master IRQ mask */
+	udelay(10000);		/* wait for 8259A to initialize */
+	out8(IMR_2,cached_imr2);	/* restore slave IRQ mask */
+}
+
+
+#define PCI_INT_ACK_ADDR 0xEED00000
+
+int handle_isa_int(void)
+{
+	unsigned long irqack;
+	unsigned char isr1,isr2,irq;
+	/* first we acknokledge the int via the PCI bus */
+	irqack=in32(PCI_INT_ACK_ADDR);
+	/* now we get the ISRs */
+	isr2=in8(ISR_2);
+	isr1=in8(ISR_1);
+	irq=(unsigned char)irqack;
+	irq-=32;
+/*	if((irq==7)&&((isr1&0x80)==0)) {
+		PRINTF("IRQ7 detected but not in ISR\n");
+	}
+	else {
+*/		/* we should handle cascaded interrupts here also */
+	{
+/*		printf("ISA Irq %d\n",irq); */
+		isa_irqs[irq].count++;
+		if(irq!=2) { /* just swallow the cascade irq 2 */
+			if (isa_irqs[irq].handler != NULL)
+				(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
+			else {
+				PRINTF ("bogus interrupt vector 0x%x\n", irq);
+			}
+		}
+	}
+	/* issue EOI instruction to clear the IRQ */
+	mask_and_ack_8259A(irq);
+	return 0;
+}
+
+
+/******************************************************************
+ * Install and free an ISA interrupt handler.
+ */
+
+void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+	if (isa_irqs[vec].handler != NULL) {
+		printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+			vec, (uint)handler, (uint)isa_irqs[vec].handler);
+	}
+	isa_irqs[vec].handler = handler;
+	isa_irqs[vec].arg     = arg;
+	enable_8259A_irq(vec);
+	PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
+
+}
+
+void isa_irq_free_handler(int vec)
+{
+	disable_8259A_irq(vec);
+	isa_irqs[vec].handler = NULL;
+	isa_irqs[vec].arg     = NULL;
+	PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
+
+}
+
+/****************************************************************************/
+void isa_init_irq_contr(void)
+{
+	int i;
+	/* disable all Interrupts */
+	/* first write icws controller 1 */
+	for(i=0;i<16;i++)
+	{
+		isa_irqs[i].handler=NULL;
+		isa_irqs[i].arg=NULL;
+		isa_irqs[i].count=0;
+	}
+	init_8259A();
+	out8(IMR_2,0xFF);
+}
+/*************************************************************************/
+
+void isa_show_irq(void)
+{
+	int vec;
+
+	printf ("\nISA Interrupt-Information:\n");
+	printf ("Nr  Routine   Arg       Count\n");
+
+	for (vec=0; vec<16; vec++) {
+		if (isa_irqs[vec].handler != NULL) {
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec,
+				(ulong)isa_irqs[vec].handler,
+				(ulong)isa_irqs[vec].arg,
+				isa_irqs[vec].count);
+		}
+	}
+}
+
+int isa_irq_get_count(int vec)
+{
+	return(isa_irqs[vec].count);
+}
+
+/******************************************************************
+ * Init the ISA bus and devices.
+ */
+
+#if defined(CONFIG_PIP405)
+
+int isa_init(void)
+{
+	isa_sio_setup();
+	isa_init_irq_contr();
+	drv_isa_kbd_init();
+	return 0;
+}
+#endif
diff --git a/u-boot/board/mpl/common/isa.h b/u-boot/board/mpl/common/isa.h
new file mode 100644
index 0000000..28ed219
--- /dev/null
+++ b/u-boot/board/mpl/common/isa.h
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ISA_H_
+#define _ISA_H_
+/* Super IO */
+#define SIO_CFG_PORT	0x3F0	/* Config Port Address */
+
+#if defined(CONFIG_PIP405)
+/* table fore SIO initialization */
+typedef struct {
+	const uchar index;
+	const uchar val;
+} SIO_LOGDEV_TABLE;
+
+typedef struct {
+	const uchar ldev;
+	const SIO_LOGDEV_TABLE *ldev_table;
+} SIO_TABLE;
+
+
+unsigned char open_cfg_super_IO(int address);
+unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr);
+void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
+void close_cfg_super_IO(int address);
+void isa_sio_setup(void);
+#endif
+
+void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
+void isa_irq_free_handler(int vec);
+int handle_isa_int(void);
+void isa_init_irq_contr(void);
+void isa_show_irq(void);
+int isa_irq_get_count(int vec);
+
+
+#endif
diff --git a/u-boot/board/mpl/common/kbd.c b/u-boot/board/mpl/common/kbd.c
new file mode 100644
index 0000000..b0a9620
--- /dev/null
+++ b/u-boot/board/mpl/common/kbd.c
@@ -0,0 +1,645 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Source partly derived from:
+ * linux/drivers/char/pc_keyb.c
+ *
+ *
+ */
+#include <common.h>
+#include <asm/processor.h>
+#include <stdio_dev.h>
+#include "isa.h"
+#include "kbd.h"
+
+
+unsigned char kbd_read_status(void);
+unsigned char kbd_read_input(void);
+void kbd_send_data(unsigned char data);
+void disable_8259A_irq(unsigned int irq);
+void enable_8259A_irq(unsigned int irq);
+
+/* used only by send_data - set by keyboard_interrupt */
+
+
+#undef KBG_DEBUG
+
+#ifdef KBG_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#define KBD_STAT_KOBF		0x01
+#define KBD_STAT_IBF		0x02
+#define KBD_STAT_SYS		0x04
+#define KBD_STAT_CD		0x08
+#define KBD_STAT_LOCK		0x10
+#define KBD_STAT_MOBF		0x20
+#define KBD_STAT_TI_OUT		0x40
+#define KBD_STAT_PARERR		0x80
+
+#define KBD_INIT_TIMEOUT	1000	/* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT		250	/* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT		2000	/* Timeout in ms for keyboard command acknowledge */
+/*
+ *	Keyboard Controller Commands
+ */
+
+#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
+					   initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
+
+/*
+ *	Keyboard Commands
+ */
+
+#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE		0xF5	/* Disable scanning */
+#define KBD_CMD_RESET		0xFF	/* Reset */
+
+/*
+ *	Keyboard Replies
+ */
+
+#define KBD_REPLY_POR		0xAA	/* Power on reset */
+#define KBD_REPLY_ACK		0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */
+
+/*
+ *	Status Register Bits
+ */
+
+#define KBD_STAT_OBF		0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
+#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO		0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR		0x80	/* Parity error */
+
+#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
+
+/*
+ *	Controller Mode Register Bits
+ */
+
+#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS		0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
+#define KBD_MODE_KCC		0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU		0x80
+
+
+#define KDB_DATA_PORT		0x60
+#define KDB_COMMAND_PORT	0x64
+
+#define	LED_SCR			0x01	/* scroll lock led */
+#define	LED_CAP			0x04	/* caps lock led */
+#define	LED_NUM			0x02	/* num lock led */
+
+#define	KBD_BUFFER_LEN		0x20	/* size of the keyboardbuffer */
+
+
+static volatile char kbd_buffer[KBD_BUFFER_LEN];
+static volatile int in_pointer = 0;
+static volatile int out_pointer = 0;
+
+
+static unsigned char num_lock = 0;
+static unsigned char caps_lock = 0;
+static unsigned char scroll_lock = 0;
+static unsigned char shift = 0;
+static unsigned char ctrl = 0;
+static unsigned char alt = 0;
+static unsigned char e0 = 0;
+static unsigned char leds = 0;
+
+#define DEVNAME "kbd"
+
+/* Simple translation table for the keys */
+
+static unsigned char kbd_plain_xlate[] = {
+	0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t',	/* 0x00 - 0x0f */
+	 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's',	/* 0x10 - 0x1f */
+	 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v',	/* 0x20 - 0x2f */
+	 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+static unsigned char kbd_shift_xlate[] = {
+	0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t',	/* 0x00 - 0x0f */
+	 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S',	/* 0x10 - 0x1f */
+	 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V',	/* 0x20 - 0x2f */
+	 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+static unsigned char kbd_ctrl_xlate[] = {
+	0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t',	/* 0x00 - 0x0f */
+	0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13,	/* 0x10 - 0x1f */
+	0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16,	/* 0x20 - 0x2f */
+	0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+/******************************************************************
+ * Init
+ ******************************************************************/
+int isa_kbd_init(void)
+{
+	char* result;
+	result=kbd_initialize();
+	if(result==NULL) {
+		PRINTF("AT Keyboard initialized\n");
+		irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
+		isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
+		return (1);
+	} else {
+		printf("%s\n",result);
+		return (-1);
+	}
+}
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console (void);
+#else
+int overwrite_console (void)
+{
+	return (0);
+}
+#endif
+
+int drv_isa_kbd_init (void)
+{
+	int error;
+	struct stdio_dev kbddev ;
+	char *stdinname  = getenv ("stdin");
+
+	if(isa_kbd_init()==-1)
+		return -1;
+	memset (&kbddev, 0, sizeof(kbddev));
+	strcpy(kbddev.name, DEVNAME);
+	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	kbddev.putc = NULL ;
+	kbddev.puts = NULL ;
+	kbddev.getc = kbd_getc ;
+	kbddev.tstc = kbd_testc ;
+
+	error = stdio_register (&kbddev);
+	if(error==0) {
+		/* check if this is the standard input device */
+		if(strcmp(stdinname,DEVNAME)==0) {
+			/* reassign the console */
+			if(overwrite_console()) {
+				return 1;
+			}
+			error=console_assign(stdin,DEVNAME);
+			if(error==0)
+				return 1;
+			else
+				return error;
+		}
+		return 1;
+	}
+	return error;
+}
+
+/******************************************************************
+ * Queue handling
+ ******************************************************************/
+/* puts character in the queue and sets up the in and out pointer */
+void kbd_put_queue(char data)
+{
+	if((in_pointer+1)==KBD_BUFFER_LEN) {
+		if(out_pointer==0) {
+			return; /* buffer full */
+		} else{
+			in_pointer=0;
+		}
+	} else {
+		if((in_pointer+1)==out_pointer)
+			return; /* buffer full */
+		in_pointer++;
+	}
+	kbd_buffer[in_pointer]=data;
+	return;
+}
+
+/* test if a character is in the queue */
+int kbd_testc(void)
+{
+	if(in_pointer==out_pointer)
+		return(0); /* no data */
+	else
+		return(1);
+}
+/* gets the character from the queue */
+int kbd_getc(void)
+{
+	char c;
+	while(in_pointer==out_pointer);
+	if((out_pointer+1)==KBD_BUFFER_LEN)
+		out_pointer=0;
+	else
+		out_pointer++;
+	c=kbd_buffer[out_pointer];
+	return (int)c;
+
+}
+
+
+/* set LEDs */
+
+void kbd_set_leds(void)
+{
+	if(caps_lock==0)
+		leds&=~LED_CAP; /* switch caps_lock off */
+	else
+		leds|=LED_CAP; /* switch on LED */
+	if(num_lock==0)
+		leds&=~LED_NUM; /* switch LED off */
+	else
+		leds|=LED_NUM;  /* switch on LED */
+	if(scroll_lock==0)
+		leds&=~LED_SCR; /* switch LED off */
+	else
+		leds|=LED_SCR; /* switch on LED */
+	kbd_send_data(KBD_CMD_SET_LEDS);
+	kbd_send_data(leds);
+}
+
+
+void handle_keyboard_event (unsigned char scancode)
+{
+	unsigned char keycode;
+
+	/*  Convert scancode to keycode */
+	PRINTF ("scancode %x\n", scancode);
+	if (scancode == 0xe0) {
+		e0 = 1;		/* special charakters */
+		return;
+	}
+	if (e0 == 1) {
+		e0 = 0;		/* delete flag */
+		if (!(((scancode & 0x7F) == 0x38) ||	/* the right ctrl key */
+		      ((scancode & 0x7F) == 0x1D) ||	/* the right alt key */
+		      ((scancode & 0x7F) == 0x35) ||	/* the right '/' key */
+		      ((scancode & 0x7F) == 0x1C)))
+			/* the right enter key */
+			/* we swallow unknown e0 codes */
+			return;
+	}
+	/* special cntrl keys */
+	switch (scancode) {
+	case 0x2A:
+	case 0x36:		/* shift pressed */
+		shift = 1;
+		return;		/* do nothing else */
+	case 0xAA:
+	case 0xB6:		/* shift released */
+		shift = 0;
+		return;		/* do nothing else */
+	case 0x38:		/* alt pressed */
+		alt = 1;
+		return;		/* do nothing else */
+	case 0xB8:		/* alt released */
+		alt = 0;
+		return;		/* do nothing else */
+	case 0x1d:		/* ctrl pressed */
+		ctrl = 1;
+		return;		/* do nothing else */
+	case 0x9d:		/* ctrl released */
+		ctrl = 0;
+		return;		/* do nothing else */
+	case 0x46:		/* scrollock pressed */
+		scroll_lock = ~scroll_lock;
+		kbd_set_leds ();
+		return;		/* do nothing else */
+	case 0x3A:		/* capslock pressed */
+		caps_lock = ~caps_lock;
+		kbd_set_leds ();
+		return;
+	case 0x45:		/* numlock pressed */
+		num_lock = ~num_lock;
+		kbd_set_leds ();
+		return;
+	case 0xC6:		/* scroll lock released */
+	case 0xC5:		/* num lock released */
+	case 0xBA:		/* caps lock released */
+		return;		/* just swallow */
+	}
+	if ((scancode & 0x80) == 0x80)	/* key released */
+		return;
+	/* now, decide which table we need */
+	if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) {	/* scancode not in list */
+		PRINTF ("unkown scancode %X\n", scancode);
+		return;		/* swallow it */
+	}
+	/* setup plain code first */
+	keycode = kbd_plain_xlate[scancode];
+	if (caps_lock == 1) {	/* caps_lock is pressed, overwrite plain code */
+		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown caps-locked scancode %X\n", scancode);
+			return;	/* swallow it */
+		}
+		keycode = kbd_shift_xlate[scancode];
+		if (keycode < 'A') {	/* we only want the alphas capital */
+			keycode = kbd_plain_xlate[scancode];
+		}
+	}
+	if (shift == 1) {	/* shift overwrites caps_lock */
+		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown shifted scancode %X\n", scancode);
+			return;	/* swallow it */
+		}
+		keycode = kbd_shift_xlate[scancode];
+	}
+	if (ctrl == 1) {	/* ctrl overwrites caps_lock and shift */
+		if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown ctrl scancode %X\n", scancode);
+			return;	/* swallow it */
+		}
+		keycode = kbd_ctrl_xlate[scancode];
+	}
+	/* check if valid keycode */
+	if (keycode == 0xff) {
+		PRINTF ("unkown scancode %X\n", scancode);
+		return;		/* swallow unknown codes */
+	}
+
+	kbd_put_queue (keycode);
+	PRINTF ("%x\n", keycode);
+}
+
+/*
+ * This reads the keyboard status port, and does the
+ * appropriate action.
+ *
+ */
+unsigned char handle_kbd_event(void)
+{
+	unsigned char status = kbd_read_status();
+	unsigned int work = 10000;
+
+	while ((--work > 0) && (status & KBD_STAT_OBF)) {
+		unsigned char scancode;
+
+		scancode = kbd_read_input();
+
+		/* Error bytes must be ignored to make the
+		   Synaptics touchpads compaq use work */
+		/* Ignore error bytes */
+		if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
+		{
+			if (status & KBD_STAT_MOUSE_OBF)
+				; /* not supported: handle_mouse_event(scancode); */
+			else
+				handle_keyboard_event(scancode);
+		}
+		status = kbd_read_status();
+	}
+	if (!work)
+		PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
+	return status;
+}
+
+
+/******************************************************************************
+ * Lowlevel Part of keyboard section
+ */
+unsigned char kbd_read_status(void)
+{
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+}
+
+unsigned char kbd_read_input(void)
+{
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+}
+
+void kbd_write_command(unsigned char cmd)
+{
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+}
+
+void kbd_write_output(unsigned char data)
+{
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+}
+
+int kbd_read_data(void)
+{
+	int val;
+	unsigned char status;
+
+	val = -1;
+	status = kbd_read_status();
+	if (status & KBD_STAT_OBF) {
+		val = kbd_read_input();
+		if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
+			val = -2;
+	}
+	return val;
+}
+
+int kbd_wait_for_input(void)
+{
+	unsigned long timeout;
+	int val;
+
+	timeout = KBD_TIMEOUT;
+	val=kbd_read_data();
+	while(val < 0)
+	{
+		if(timeout--==0)
+			return -1;
+		udelay(1000);
+		val=kbd_read_data();
+	}
+	return val;
+}
+
+
+int kb_wait(void)
+{
+	unsigned long timeout = KBC_TIMEOUT * 10;
+
+	do {
+		unsigned char status = handle_kbd_event();
+		if (!(status & KBD_STAT_IBF))
+			return 0; /* ok */
+		udelay(1000);
+		timeout--;
+	} while (timeout);
+	return 1;
+}
+
+void kbd_write_command_w(int data)
+{
+	if(kb_wait())
+		PRINTF("timeout in kbd_write_command_w\n");
+	kbd_write_command(data);
+}
+
+void kbd_write_output_w(int data)
+{
+	if(kb_wait())
+		PRINTF("timeout in kbd_write_output_w\n");
+	kbd_write_output(data);
+}
+
+void kbd_send_data(unsigned char data)
+{
+	unsigned char status;
+	disable_8259A_irq(1); /* disable interrupt */
+	kbd_write_output_w(data);
+	status = kbd_wait_for_input();
+	if (status == KBD_REPLY_ACK)
+		enable_8259A_irq(1); /* enable interrupt */
+}
+
+
+char * kbd_initialize(void)
+{
+	int status;
+
+	in_pointer = 0; /* delete in Buffer */
+	out_pointer = 0;
+	/*
+	 * Test the keyboard interface.
+	 * This seems to be the only way to get it going.
+	 * If the test is successful a x55 is placed in the input buffer.
+	 */
+	kbd_write_command_w(KBD_CCMD_SELF_TEST);
+	if (kbd_wait_for_input() != 0x55)
+		return "Kbd:   failed self test";
+	/*
+	 * Perform a keyboard interface test.  This causes the controller
+	 * to test the keyboard clock and data lines.  The results of the
+	 * test are placed in the input buffer.
+	 */
+	kbd_write_command_w(KBD_CCMD_KBD_TEST);
+	if (kbd_wait_for_input() != 0x00)
+		return "Kbd:   interface failed self test";
+	/*
+	 * Enable the keyboard by allowing the keyboard clock to run.
+	 */
+	kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
+	status = kbd_wait_for_input();
+	/*
+	 * Reset keyboard. If the read times out
+	 * then the assumption is that no keyboard is
+	 * plugged into the machine.
+	 * This defaults the keyboard to scan-code set 2.
+	 *
+	 * Set up to try again if the keyboard asks for RESEND.
+	 */
+	do {
+		kbd_write_output_w(KBD_CMD_RESET);
+		status = kbd_wait_for_input();
+		if (status == KBD_REPLY_ACK)
+			break;
+		if (status != KBD_REPLY_RESEND) {
+			PRINTF("status: %X\n",status);
+			return "Kbd:   reset failed, no ACK";
+		}
+	} while (1);
+	if (kbd_wait_for_input() != KBD_REPLY_POR)
+		return "Kbd:   reset failed, no POR";
+
+	/*
+	 * Set keyboard controller mode. During this, the keyboard should be
+	 * in the disabled state.
+	 *
+	 * Set up to try again if the keyboard asks for RESEND.
+	 */
+	do {
+		kbd_write_output_w(KBD_CMD_DISABLE);
+		status = kbd_wait_for_input();
+		if (status == KBD_REPLY_ACK)
+			break;
+		if (status != KBD_REPLY_RESEND)
+			return "Kbd:   disable keyboard: no ACK";
+	} while (1);
+
+	kbd_write_command_w(KBD_CCMD_WRITE_MODE);
+	kbd_write_output_w(KBD_MODE_KBD_INT
+			      | KBD_MODE_SYS
+			      | KBD_MODE_DISABLE_MOUSE
+			      | KBD_MODE_KCC);
+
+	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
+	kbd_write_command_w(KBD_CCMD_READ_MODE);
+	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
+		/*
+		 * If the controller does not support conversion,
+		 * Set the keyboard to scan-code set 1.
+		 */
+		kbd_write_output_w(0xF0);
+		kbd_wait_for_input();
+		kbd_write_output_w(0x01);
+		kbd_wait_for_input();
+	}
+	kbd_write_output_w(KBD_CMD_ENABLE);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   enable keyboard: no ACK";
+
+	/*
+	 * Finally, set the typematic rate to maximum.
+	 */
+	kbd_write_output_w(KBD_CMD_SET_RATE);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   Set rate: no ACK";
+	kbd_write_output_w(0x00);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   Set rate: no ACK";
+	return NULL;
+}
+
+void kbd_interrupt(void)
+{
+	handle_kbd_event();
+}
diff --git a/u-boot/board/mpl/common/kbd.h b/u-boot/board/mpl/common/kbd.h
new file mode 100644
index 0000000..229ba61
--- /dev/null
+++ b/u-boot/board/mpl/common/kbd.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _KBD_H_
+#define _KBD_H_
+
+extern int kbd_testc(void);
+extern int kbd_getc(void);
+extern void kbd_interrupt(void);
+extern char *kbd_initialize(void);
+
+unsigned char kbd_is_init(void);
+#define KBD_INTERRUPT 1
+#endif
diff --git a/u-boot/board/mpl/common/pci.c b/u-boot/board/mpl/common/pci.c
new file mode 100644
index 0000000..f9bb6ab
--- /dev/null
+++ b/u-boot/board/mpl/common/pci.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------+
+|       This source code is dual-licensed.  You may use it under the terms of
+|       the GNU General Public License version 2, or under the license below.
+|
+|       This source code has been made available to you by IBM on an AS-IS
+|       basis.  Anyone receiving this source is licensed under IBM
+|       copyrights to use it in any way he or she deems fit, including
+|       copying it, modifying it, compiling it, and redistributing it either
+|       with or without modifications.  No license under IBM patents or
+|       patent applications is to be implied by the copyright license.
+|
+|       Any user of this software should understand that IBM cannot provide
+|       technical support for this software and will not be responsible for
+|       any consequences resulting from the use of this software.
+|
+|       Any person who transfers this source code or any derivative work
+|       must include the IBM copyright notice, this paragraph, and the
+|       preceding two paragraphs in the transferred software.
+|
+|       COPYRIGHT   I B M   CORPORATION 1995
+|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++-----------------------------------------------------------------------------*/
+/*
+ * Adapted for PIP405 03.07.01
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * TODO: Clean-up
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "isa.h"
+
+#ifdef CONFIG_405GP
+#ifdef CONFIG_PCI
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#include "piix4_pci.h"
+#include "pci_parts.h"
+
+void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
+			   struct pci_config_table *entry)
+{
+	struct pci_pip405_config_entry *table;
+	int i;
+
+	table = (struct pci_pip405_config_entry*) entry->priv[0];
+
+	for (i=0; table[i].width; i++)
+	{
+#ifdef DEBUG
+		printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
+		       table[i].index, table[i].val, table[i].width);
+#endif
+
+		switch(table[i].width)
+		{
+		case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
+		case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
+		case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
+		}
+	}
+}
+
+
+static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = 0xff;
+	unsigned char pin;
+	/*
+	 * Write pci interrupt line register
+	 */
+	if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
+		return;
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
+	if ((pin == 0) || (pin > 4))
+	    return;
+
+	int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+#ifdef DEBUG
+	printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
+	       PCI_DEV(dev),dev,int_line,int_line);
+#endif
+}
+
+extern void pci_405gp_init(struct pci_controller *hose);
+
+
+static struct pci_controller hose = {
+  config_table: pci_pip405_config_table,
+  fixup_irq: pci_pip405_fixup_irq,
+};
+
+
+void pci_init_board(void)
+{
+	/*we want the ptrs to RAM not flash (ie don't use init list)*/
+	hose.fixup_irq    = pci_pip405_fixup_irq;
+	hose.config_table = pci_pip405_config_table;
+#ifdef DEBUG
+	printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
+#endif
+	pci_405gp_init(&hose);
+}
+
+#endif /* CONFIG_PCI */
+#endif /* CONFIG_405GP */
diff --git a/u-boot/board/mpl/common/pci_parts.h b/u-boot/board/mpl/common/pci_parts.h
new file mode 100644
index 0000000..7bca961
--- /dev/null
+++ b/u-boot/board/mpl/common/pci_parts.h
@@ -0,0 +1,193 @@
+ /*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _PCI_PARTS_H_
+#define _PCI_PARTS_H_
+
+
+/* Board specific file containing:
+ * - PCI Memory Mapping
+ * - PCI IO Mapping
+ * - PCI Interrupt Mapping
+ */
+
+/* PIP405 PCI INT Routing:
+ *                      IRQ0  VECTOR
+ * PIXX4 IDSEL  = AD16  INTA#  28 (Function 2 USB is INTD# = 31)
+ * VGA   IDSEL  = AD17  INTB#  29
+ * SCSI  IDSEL  = AD18  INTC#  30
+ * PC104 IDSEL0 = AD20  INTA#  28
+ * PC104 IDSEL1 = AD21  INTB#  29
+ * PC104 IDSEL2 = AD22  INTC#  30
+ * PC104 IDSEL3 = AD23  INTD#  31
+ *
+ * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
+ *              ^         ^         ^     ^   ^
+ *             31        23        15    10   7
+ * E = Enabled
+ * B = Bussnumber
+ * D = Devicenumber (Device0 = AD10)
+ * F = Functionnumber
+ * R = Registernumber
+ *
+ * Device = (busdevfunc>>11) + 10
+ * Vector = devicenumber % 4 + 28
+ *
+ */
+#define PCI_HIGHEST_ON_BOARD_ID	19
+/*#define PCI_DEV_NUMBER(x)	(((x>>11) & 0x1f) + 10) */
+#define PCI_IRQ_VECTOR(x)	((PCI_DEV(x) + 10) % 4) + 28
+
+
+/* PCI Device List for PIP405 */
+
+/* Mapping:
+ * +-------------+------------+------------+--------------------------------+
+ * ¦ PCI MemAddr | PCI IOAddr | Local Addr | Device / Function              |
+ * +-------------+------------+------------+--------------------------------+
+ * |  0x00000000 |            | 0xA0000000 | ISA Memory (hard wired)        |
+ * |  0x00FFFFFF |            | 0xA0FFFFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ * |             | 0x00000000 | 0xE8000000 | ISA IO (hard wired)            |
+ * |             | 0x0000FFFF | 0xE800FFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ * |  0x80000000 |            | 0x80000000 | VGA Controller Memory          |
+ * |  0x80FFFFFF |            | 0x80FFFFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ * |  0x81000000 |            | 0x81000000 | SCSI Controller Memory         |
+ * |  0x81FFFFFF |            | 0x81FFFFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ */
+
+struct pci_pip405_config_entry {
+	int		index;	/* address */
+	unsigned long	val;	/* value */
+	int		width;	/* data size */
+};
+
+extern void pci_pip405_write_regs(struct pci_controller *,
+				  pci_dev_t,
+				  struct pci_config_table *);
+
+/* PIIX4 ISA Bridge Function 0 */
+static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
+	{PCI_CFG_PIIX4_SERIRQ,	0xD0,		1}, /* enable Continous SERIRQ Pin */
+	{PCI_CFG_PIIX4_GENCFG,	0x00018041,	4}, /* enable SERIRQs, ISA, PNP, GPI11 */
+	{PCI_CFG_PIIX4_TOM,	0xFE,		1}, /* Top of Memory		*/
+	{PCI_CFG_PIIX4_XBCS,	0x02C4,		2}, /* disable all peri CS	*/
+	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC		*/
+#if defined(CONFIG_PIP405)
+	{PCI_CFG_PIIX4_MBDMA,	0x82,		1}, /* set MBDMA0 to DMA 2	*/
+	{PCI_CFG_PIIX4_MBDMA+1,	0x83,		1}, /* set MBDMA1 to DMA 3	*/
+#endif
+	{PCI_CFG_PIIX4_DLC,	0x0,		1}, /* disable passive release feature */
+	{ }					    /* end of device table	*/
+};
+
+/* PIIX4 IDE Controller Function 1 */
+static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+	{PCI_CFG_PIIX4_BMIBA,	0x0001000,	4}, /* set BMI to a valid address */
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access	*/
+#if !defined(CONFIG_MIP405T)
+	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
+#else
+	{PCI_CFG_PIIX4_IDETIM,	0x00008000,	4}, /* enable IDE channel0	*/
+#endif
+	{ }					    /* end of device table	*/
+};
+
+/* PIIX4 USB Controller Function 2 */
+static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
+#if !defined(CONFIG_MIP405T)
+	{PCI_INTERRUPT_LINE,	31,		1}, /* Int vector = 31		*/
+	{PCI_BASE_ADDRESS_4,	0x0000E001,	4}, /* Set IO Address to 0xe000 to 0xe01F */
+	{PCI_LATENCY_TIMER,	0x80,		1}, /* Latency Timer 0x80	*/
+	{0xC0,			0x2000,		2}, /* Legacy support		*/
+	{PCI_COMMAND,		0x0005,		2}, /* enable IO access and Master */
+#endif
+	{ }					    /* end of device table	*/
+};
+
+/* PIIX4 Power Management Function 3 */
+static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
+	{PCI_CFG_PIIX4_PMBA,	0x00004000,	4}, /* set PMBA to "valid" value */
+	{PCI_CFG_PIIX4_SMBBA,	0x00005000,	4}, /* set SMBBA to "valid" value */
+	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access	*/
+	{ }					    /* end of device table	*/
+};
+/* PPC405 Dummy only used to prevent autosetup on this host bridge */
+static struct pci_pip405_config_entry ppc405_dummy[] = {
+	{ }					    /* end of device table	*/
+};
+
+void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
+			 struct pci_config_table *entry);
+
+
+static struct pci_config_table pci_pip405_config_table[]={
+	{PCI_VENDOR_ID_IBM,			/* 405 dummy */
+	 PCI_DEVICE_ID_IBM_405GP,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 0,
+	 pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 ISA Bridge Function 0 */
+	 PCI_DEVICE_ID_INTEL_82371AB_0,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 0,
+	 pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 IDE Controller Function 1 */
+	 PCI_DEVICE_ID_INTEL_82371AB,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 1,
+	 pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 USB Controller Function 2 */
+	 PCI_DEVICE_ID_INTEL_82371AB_2,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 2,
+	 pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 USB Controller Function 3 */
+	 PCI_DEVICE_ID_INTEL_82371AB_3,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 3,
+	 pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
+
+	{PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_CLASS_DISPLAY_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_405gp_setup_vga},
+
+	{PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_CLASS_NOT_DEFINED_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_405gp_setup_vga},
+
+	{ }
+};
+#endif /* _PCI_PARTS_H_ */
diff --git a/u-boot/board/mpl/common/piix4_pci.h b/u-boot/board/mpl/common/piix4_pci.h
new file mode 100644
index 0000000..0ff802e
--- /dev/null
+++ b/u-boot/board/mpl/common/piix4_pci.h
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+/***************************************************************************
+* Defines PIIX4 Config Registers
+****************************************************************************/
+
+/* Function 0 ISA Bridge */
+#define	PCI_CFG_PIIX4_IORT		0x4C	/* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define	PCI_CFG_PIIX4_XBCS		0x4E	/* 16 bit XBus Chip select reg (default 0x0003) */
+#define	PCI_CFG_PIIX4_PIRQC		0x60  /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define	PCI_CFG_PIIX4_SERIRQ	0x64
+#define	PCI_CFG_PIIX4_TOM			0x69
+#define	PCI_CFG_PIIX4_MSTAT		0x6A
+#define	PCI_CFG_PIIX4_MBDMA		0x76
+#define	PCI_CFG_PIIX4_APICBS	0x80
+#define	PCI_CFG_PIIX4_DLC			0x82
+#define	PCI_CFG_PIIX4_PDMACFG	0x90
+#define	PCI_CFG_PIIX4_DDMABS	0x92
+#define	PCI_CFG_PIIX4_GENCFG	0xB0
+#define	PCI_CFG_PIIX4_RTCCFG	0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA	0x00
+#define PIIX4_ISA_DMA1_CH0CA	0x01
+#define PIIX4_ISA_DMA1_CH1BA	0x02
+#define PIIX4_ISA_DMA1_CH1CA	0x03
+#define PIIX4_ISA_DMA1_CH2BA	0x04
+#define PIIX4_ISA_DMA1_CH2CA	0x05
+#define PIIX4_ISA_DMA1_CH3BA	0x06
+#define PIIX4_ISA_DMA1_CH3CA	0x07
+#define PIIX4_ISA_DMA1_CMDST	0x08
+#define PIIX4_ISA_DMA1_REQ		0x09
+#define PIIX4_ISA_DMA1_WSBM		0x0A
+#define PIIX4_ISA_DMA1_CH_MOD	0x0B
+#define PIIX4_ISA_DMA1_CLR_PT	0x0C
+#define PIIX4_ISA_DMA1_M_CLR	0x0D
+#define PIIX4_ISA_DMA1_CLR_M	0x0E
+#define PIIX4_ISA_DMA1_RWAMB	0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA	0xC0
+#define PIIX4_ISA_DMA2_CH0CA	0xC1
+#define PIIX4_ISA_DMA2_CH1BA	0xC2
+#define PIIX4_ISA_DMA2_CH1CA	0xC3
+#define PIIX4_ISA_DMA2_CH2BA	0xC4
+#define PIIX4_ISA_DMA2_CH2CA	0xC5
+#define PIIX4_ISA_DMA2_CH3BA	0xC6
+#define PIIX4_ISA_DMA2_CH3CA	0xC7
+#define PIIX4_ISA_DMA2_CMDST	0xD0
+#define PIIX4_ISA_DMA2_REQ		0xD2
+#define PIIX4_ISA_DMA2_WSBM		0xD4
+#define PIIX4_ISA_DMA2_CH_MOD	0xD6
+#define PIIX4_ISA_DMA2_CLR_PT	0xD8
+#define PIIX4_ISA_DMA2_M_CLR	0xDA
+#define PIIX4_ISA_DMA2_CLR_M	0xDC
+#define PIIX4_ISA_DMA2_RWAMB	0xDE
+
+#define PIIX4_ISA_INT1_ICW1		0x20
+#define PIIX4_ISA_INT1_OCW2		0x20
+#define PIIX4_ISA_INT1_OCW3		0x20
+#define PIIX4_ISA_INT1_ICW2		0x21
+#define PIIX4_ISA_INT1_ICW3		0x21
+#define PIIX4_ISA_INT1_ICW4		0x21
+#define PIIX4_ISA_INT1_OCW1		0x21
+
+#define PIIX4_ISA_INT1_ELCR		0x4D0
+
+#define PIIX4_ISA_INT2_ICW1		0xA0
+#define PIIX4_ISA_INT2_OCW2		0xA0
+#define PIIX4_ISA_INT2_OCW3		0xA0
+#define PIIX4_ISA_INT2_ICW2		0xA1
+#define PIIX4_ISA_INT2_ICW3		0xA1
+#define PIIX4_ISA_INT2_ICW4		0xA1
+#define PIIX4_ISA_INT2_OCW1		0xA1
+#define PIIX4_ISA_INT2_IMR		0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR		0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST	0x40
+#define PIIX4_ISA_TMR1_CNT_ST	0x41
+#define PIIX4_ISA_TMR2_CNT_ST	0x42
+#define PIIX4_ISA_TMR_TCW			0x43
+
+#define PIIX4_ISA_RST_XBUS		0x60
+
+#define PIIX4_ISA_NMI_CNT_ST	0x61
+#define PIIX4_ISA_NMI_ENABLE	0x70
+
+#define PIIX4_ISA_RTC_INDEX		0x70
+#define PIIX4_ISA_RTC_DATA		0x71
+#define PIIX4_ISA_RTCEXT_IND	0x70
+#define PIIX4_ISA_RTCEXT_DATA	0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG	0x81
+#define PIIX4_ISA_DMA1_CH3LPG	0x82
+#define PIIX4_ISA_DMA1_CH1LPG	0x83
+#define PIIX4_ISA_DMA1_CH0LPG	0x87
+#define PIIX4_ISA_DMA2_CH2LPG	0x89
+#define PIIX4_ISA_DMA2_CH3LPG	0x8A
+#define PIIX4_ISA_DMA2_CH1LPG	0x8B
+#define PIIX4_ISA_DMA2_LPGRFR	0x8F
+
+#define PIIX4_ISA_PORT_92			0x92
+
+#define PIIX4_ISA_APM_CONTRL	0xB2
+#define PIIX4_ISA_APM_STATUS	0xB3
+
+#define PIIX4_ISA_COCPU_ERROR	0xF0
+
+/* Function 1 IDE Controller */
+#define	PCI_CFG_PIIX4_BMIBA		0x20
+#define	PCI_CFG_PIIX4_IDETIM	0x40
+#define	PCI_CFG_PIIX4_SIDETIM	0x44
+#define	PCI_CFG_PIIX4_UDMACTL	0x48
+#define	PCI_CFG_PIIX4_UDMATIM 0x4A
+
+/* Function 2 USB Controller */
+#define	PCI_CFG_PIIX4_SBRNUM	0x60
+#define	PCI_CFG_PIIX4_LEGSUP	0xC0
+
+/* Function 3 Power Management */
+#define	PCI_CFG_PIIX4_PMBA		0x40
+#define	PCI_CFG_PIIX4_CNTA		0x44
+#define	PCI_CFG_PIIX4_CNTB		0x48
+#define	PCI_CFG_PIIX4_GPICTL	0x4C
+#define	PCI_CFG_PIIX4_DEVRESD	0x50
+#define	PCI_CFG_PIIX4_DEVACTA	0x54
+#define	PCI_CFG_PIIX4_DEVACTB	0x58
+#define	PCI_CFG_PIIX4_DEVRESA	0x5C
+#define	PCI_CFG_PIIX4_DEVRESB	0x60
+#define	PCI_CFG_PIIX4_DEVRESC	0x64
+#define	PCI_CFG_PIIX4_DEVRESE	0x68
+#define	PCI_CFG_PIIX4_DEVRESF	0x6C
+#define	PCI_CFG_PIIX4_DEVRESG	0x70
+#define	PCI_CFG_PIIX4_DEVRESH	0x74
+#define	PCI_CFG_PIIX4_DEVRESI	0x78
+#define	PCI_CFG_PIIX4_PMMISC	0x80
+#define	PCI_CFG_PIIX4_SMBBA	0x90
+
+
+#endif
diff --git a/u-boot/board/mpl/common/usb_uhci.c b/u-boot/board/mpl/common/usb_uhci.c
new file mode 100644
index 0000000..a009437
--- /dev/null
+++ b/u-boot/board/mpl/common/usb_uhci.c
@@ -0,0 +1,1169 @@
+/*
+ * Part of this code has been derived from linux:
+ * Universal Host Controller Interface driver for USB (take II).
+ *
+ * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
+ *               Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
+ *               Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
+ *               Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
+ * (c) 2000      Yggdrasil Computing, Inc. (port of new PCI interface support
+ *               from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
+ * (C) 2000      David Brownell, david-b@pacbell.net (usb-ohci.c)
+ *
+ * HW-initalization based on material of
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ * (C) Copyright 1999 Johannes Erdfelt
+ * (C) Copyright 1999 Randy Dunlap
+ * (C) Copyright 1999 Gregory P. Smith
+ *
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ */
+
+/**********************************************************************
+ * How it works:
+ * -------------
+ * The framelist / Transfer descriptor / Queue Heads are similar like
+ * in the linux usb_uhci.c.
+ *
+ * During initialization, the following skeleton is allocated in init_skel:
+ *
+ *         framespecific           |           common chain
+ *
+ * framelist[]
+ * [  0 ]-----> TD ---------\
+ * [  1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
+ *   ...        TD ---------/
+ * [1023]-----> TD --------/
+ *
+ *              ^^             ^^         ^^          ^^          ^^
+ *              7 TDs for      1 TD for   Start of    Start of    End Chain
+ *              INT (2-128ms)  1ms-INT    CTRL Chain  BULK Chain
+ *
+ *
+ * Since this is a bootloader, the isochronous transfer descriptor have been removed.
+ *
+ * Interrupt Transfers.
+ * --------------------
+ * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * will be inserted after the appropriate (depending the interval setting) skeleton TD.
+ * If an interrupt has been detected the dev->irqhandler is called. The status and number
+ * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
+ * the interrupt TD will be reactivated.
+ *
+ * Control Transfers
+ * -----------------
+ * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ * Bulk Transfers
+ * --------------
+ * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_USB_UHCI
+
+#include <usb.h>
+#include "usb_uhci.h"
+
+#define USB_MAX_TEMP_TD      128  /* number of temporary TDs for bulk and control transfers */
+#define USB_MAX_TEMP_INT_TD  32   /* number of temporary TDs for Interrupt transfers */
+
+
+#undef USB_UHCI_DEBUG
+
+#ifdef	USB_UHCI_DEBUG
+#define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define USB_UHCI_PRINTF(fmt,args...)
+#endif
+
+
+static int irqvec = -1;            /* irq vector, if -1 uhci is stopped / reseted */
+unsigned int usb_base_addr;       /* base address */
+
+static uhci_td_t td_int[8];        /* Interrupt Transfer descriptors */
+static uhci_qh_t qh_cntrl;         /* control Queue Head */
+static uhci_qh_t qh_bulk;          /*  bulk Queue Head */
+static uhci_qh_t qh_end;           /* end Queue Head */
+static uhci_td_t td_last;          /* last TD (linked with end chain) */
+
+/* temporary tds */
+static uhci_td_t tmp_td[USB_MAX_TEMP_TD];          /* temporary bulk/control td's  */
+static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD];  /* temporary interrupt td's  */
+
+static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
+
+static struct virt_root_hub rh;   /* struct for root hub */
+
+/**********************************************************************
+ * some forward decleration
+ */
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+						void *buffer, int transfer_len,struct devrequest *setup);
+
+/* fill a td with the approproiate data. Link, status, info and buffer
+ * are used by the USB controller itselfes, dev is used to identify the
+ * "connected" device
+ */
+void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
+					unsigned long info, unsigned long buffer, unsigned long dev)
+{
+	td->link=swap_32(link);
+	td->status=swap_32(status);
+	td->info=swap_32(info);
+	td->buffer=swap_32(buffer);
+	td->dev_ptr=dev;
+}
+
+/* fill a qh with the approproiate data. Head and element are used by the USB controller
+ * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
+ * Please note, that after completion of the td chain, the entry element is removed /
+ * marked invalid by the USB controller.
+ */
+void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
+{
+	qh->head=swap_32(head);
+	qh->element=swap_32(element);
+	qh->dev_ptr=0L;
+}
+
+/* get the status of a td->status
+ */
+unsigned long usb_uhci_td_stat(unsigned long status)
+{
+	unsigned long result=0;
+	result |= (status & TD_CTRL_NAK)      ? USB_ST_NAK_REC : 0;
+	result |= (status & TD_CTRL_STALLED)  ? USB_ST_STALLED : 0;
+	result |= (status & TD_CTRL_DBUFERR)  ? USB_ST_BUF_ERR : 0;
+	result |= (status & TD_CTRL_BABBLE)   ? USB_ST_BABBLE_DET : 0;
+	result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
+	result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
+	result |= (status & TD_CTRL_ACTIVE)   ? USB_ST_NOT_PROC : 0;
+	return result;
+}
+
+/* get the status and the transfered len of a td chain.
+ * called from the completion handler
+ */
+int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
+{
+	unsigned long temp,info;
+	unsigned long stat;
+	uhci_td_t *mytd=td;
+
+	if(dev->devnum==rh.devnum)
+		return 0;
+	dev->act_len=0;
+	stat=0;
+	do {
+		temp=swap_32((unsigned long)mytd->status);
+		stat=usb_uhci_td_stat(temp);
+		info=swap_32((unsigned long)mytd->info);
+		if(((info & 0xff)!= USB_PID_SETUP) &&
+				(((info >> 21) & 0x7ff)!= 0x7ff) &&
+				(temp & 0x7FF)!=0x7ff)
+		{  /* if not setup and not null data pack */
+			dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+		}
+		if(stat) {           /* status no ok */
+			dev->status=stat;
+			return -1;
+		}
+		temp=swap_32((unsigned long)mytd->link);
+		mytd=(uhci_td_t *)(temp & 0xfffffff0);
+	}while((temp & 0x1)==0); /* process all TDs */
+	dev->status=stat;
+	return 0; /* Ok */
+}
+
+
+/*-------------------------------------------------------------------
+ *                         LOW LEVEL STUFF
+ *          assembles QHs und TDs for control, bulk and iso
+ *-------------------------------------------------------------------*/
+
+/* Submits a control message. That is a Setup, Data and Status transfer.
+ * Routine does not wait for completion.
+ */
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+										int transfer_len,struct devrequest *setup)
+{
+	unsigned long destination, status;
+	int maxsze = usb_maxpacket(dev, pipe);
+	unsigned long dataptr;
+	int len;
+	int pktsze;
+	int i=0;
+
+	if (!maxsze) {
+		USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
+		return -1;
+	}
+	if(((pipe>>8)&0x7f)==rh.devnum) {
+		/* this is the root hub -> redirect it */
+		return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
+	}
+	USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
+	/* The "pipe" thing contains the destination in bits 8--18 */
+	destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
+	/*  Build the TD for the control request, try forever, 8 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
+#if 0
+	{
+		char *sp=(char *)setup;
+		printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
+		    sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
+	}
+#endif
+	dataptr = (unsigned long)buffer;
+	len=transfer_len;
+
+	/* If direction is "send", change the frame from SETUP (0x2D)
+	   to OUT (0xE1). Else change it from SETUP to IN (0x69). */
+	destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
+	while (len > 0) {
+		/* data stage */
+		pktsze = len;
+		i++;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		destination ^= 1 << TD_TOKEN_TOGGLE;	/* toggle DATA0/1 */
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+
+		dataptr += pktsze;
+		len -= pktsze;
+	}
+
+	/*  Build the final TD for control status */
+	/* It's only IN if the pipe is out AND we aren't expecting data */
+
+	destination &= ~UHCI_PID;
+	if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
+		destination |= USB_PID_IN;
+	else
+		destination |= USB_PID_OUT;
+	destination |= 1 << TD_TOKEN_TOGGLE;	/* End in Data1 */
+	i++;
+	status &=~TD_CTRL_SPD;
+	/* no limit on errors on final packet , 0 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
+	tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);	/* queue status td */
+	/*	usb_show_td(i+1);*/
+	USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
+	/* first mark the control QH element terminated */
+	qh_cntrl.element=0xffffffffL;
+	/* set qh active */
+	qh_cntrl.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
+	return 0;
+}
+
+/*-------------------------------------------------------------------
+ * Prepare TDs for bulk transfers.
+ */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
+{
+	unsigned long destination, status,info;
+	unsigned long dataptr;
+	int maxsze = usb_maxpacket(dev, pipe);
+	int len;
+	int i=0;
+
+	if(transfer_len < 0) {
+		printf("Negative transfer length in submit_bulk\n");
+		return -1;
+	}
+	if (!maxsze)
+		return -1;
+	/* The "pipe" thing contains the destination in bits 8--18. */
+	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/*	((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
+	/* Build the TDs for the bulk request */
+	len = transfer_len;
+	dataptr = (unsigned long)buffer;
+	do {
+		int pktsze = len;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		/* pktsze bytes of data  */
+		info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
+			(usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
+
+		if((len-pktsze)==0)
+			status |= TD_CTRL_IOC;	/* last one generates INT */
+
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		if(i>0)
+			tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+		i++;
+		dataptr += pktsze;
+		len -= pktsze;
+		usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+	} while (len > 0);
+	/* first mark the bulk QH element terminated */
+	qh_bulk.element=0xffffffffL;
+	/* set qh active */
+	qh_bulk.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
+	return 0;
+}
+
+
+/* search a free interrupt td
+ */
+uhci_td_t *uhci_alloc_int_td(void)
+{
+	int i;
+	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+		if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
+			return &tmp_int_td[i];
+	}
+	return NULL;
+}
+
+#if 0
+void uhci_show_temp_int_td(void)
+{
+	int i;
+	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+		if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
+			printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
+	}
+	printf("all others temp_tds are free\n");
+}
+#endif
+/*-------------------------------------------------------------------
+ * submits USB interrupt (ie. polling ;-)
+ */
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
+{
+	int nint, n;
+	unsigned long status, destination;
+	unsigned long info,tmp;
+	uhci_td_t *mytd;
+	if (interval < 0 || interval >= 256)
+		return -1;
+
+	if (interval == 0)
+		nint = 0;
+	else {
+		for (nint = 0, n = 1; nint <= 8; nint++, n += n)	/* round interval down to 2^n */
+		 {
+			if(interval < n) {
+				interval = n / 2;
+				break;
+			}
+		}
+		nint--;
+	}
+
+	USB_UHCI_PRINTF("Rounded interval to %i, chain  %i\n", interval, nint);
+	mytd=uhci_alloc_int_td();
+	if(mytd==NULL) {
+		printf("No free INT TDs found\n");
+		return -1;
+	}
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
+/*		(urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
+*/
+
+	destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
+
+	info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
+	tmp = swap_32(td_int[nint].link);
+	usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
+	/* Link it */
+	tmp = swap_32((unsigned long)mytd);
+	td_int[nint].link=tmp;
+
+	usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+
+	return 0;
+}
+
+/**********************************************************************
+ * Low Level functions
+ */
+
+
+void reset_hc(void)
+{
+
+	/* Global reset for 100ms */
+	out16r( usb_base_addr + USBPORTSC1,0x0204);
+	out16r( usb_base_addr + USBPORTSC2,0x0204);
+	out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
+	/* Turn off all interrupts */
+	out16r(usb_base_addr + USBINTR,0);
+	wait_ms(50);
+	out16r( usb_base_addr + USBCMD,0);
+	wait_ms(10);
+}
+
+void start_hc(void)
+{
+	int timeout = 1000;
+
+	while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
+		if (!--timeout) {
+			printf("USBCMD_HCRESET timed out!\n");
+			break;
+		}
+	}
+	/* Turn on all interrupts */
+	out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
+	/* Start at frame 0 */
+	out16r(usb_base_addr + USBFRNUM,0);
+	/* set Framebuffer base address */
+	out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
+	/* Run and mark it configured with a 64-byte max packet */
+	out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
+}
+
+/* Initialize the skeleton
+ */
+void usb_init_skel(void)
+{
+	unsigned long temp;
+	int n;
+
+	for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
+		tmp_int_td[n].dev_ptr=0L; /* no devices connected */
+	/* last td */
+	usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
+  /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
+	/* End Queue Header */
+	usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
+	/* Bulk Queue Header */
+	temp=(unsigned long)&qh_end;
+	usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+	/* Control Queue Header */
+	temp=(unsigned long)&qh_bulk;
+	usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+	/* 1ms Interrupt td */
+	temp=(unsigned long)&qh_cntrl;
+	usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
+	temp=(unsigned long)&td_int[0];
+	for(n=1; n<8; n++)
+		usb_fill_td(&td_int[n],temp,0,0,0,0L);
+	for (n = 0; n < 1024; n++) {
+	/* link all framelist pointers to one of the interrupts */
+		int m, o;
+		if ((n&127)==127)
+			framelist[n]= swap_32((unsigned long)&td_int[0]);
+		else
+			for (o = 1, m = 2; m <= 128; o++, m += m)
+				if ((n & (m - 1)) == ((m - 1) / 2))
+						framelist[n]= swap_32((unsigned long)&td_int[o]);
+	}
+}
+
+/* check the common skeleton for completed transfers, and update the status
+ * of the "connected" device. Called from the IRQ routine.
+ */
+void usb_check_skel(void)
+{
+	struct usb_device *dev;
+	/* start with the control qh */
+	if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev=(struct usb_device *)qh_cntrl.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_cntrl.dev_ptr=0;
+		}
+	}
+	/* now process the bulk */
+	if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev=(struct usb_device *)qh_bulk.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_bulk.dev_ptr=0;
+		}
+	}
+}
+
+/* check the interrupt chain, ubdate the status of the appropriate device,
+ * call the appropriate irqhandler and reactivate the TD if the irqhandler
+ * returns with 1
+ */
+void usb_check_int_chain(void)
+{
+	int i,res;
+	unsigned long link,status;
+	struct usb_device *dev;
+	uhci_td_t *td,*prevtd;
+
+	for(i=0;i<8;i++) {
+		prevtd = &td_int[i]; /* the first previous td is the skeleton td */
+		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
+		td=(uhci_td_t *)link; /* assign it */
+		/* all interrupt TDs are finally linked to the td_int[0].
+		 * so we process all until we find the td_int[0].
+		 * if int0 chain points to a QH, we're also done
+	   */
+		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
+					((i==0) && !(swap_32(td->link) &  UHCI_PTR_QH)))
+		{
+			/* check if a device is assigned with this td */
+			status=swap_32(td->status);
+			if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
+				/* td is not active and a device is assigned -> call irqhandler */
+				dev=(struct usb_device *)td->dev_ptr;
+				dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+				dev->irq_status=usb_uhci_td_stat(status); /* get status */
+				res=dev->irq_handle(dev); /* call irqhandler */
+				if(res==1) {
+					/* reactivate */
+					status|=TD_CTRL_ACTIVE;
+					td->status=swap_32(status);
+					prevtd=td; /* previous td = this td */
+				}
+				else {
+					prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
+					/* remove device pointer */
+					td->dev_ptr=0L;
+				}
+			} /* if we call the irq handler */
+			link=swap_32(td->link) & 0xfffffff0; /* next in chain */
+			td=(uhci_td_t *)link; /* assign it */
+		} /* process all td in this int chain */
+	} /* next interrupt chain */
+}
+
+
+/* usb interrupt service routine.
+ */
+void handle_usb_interrupt(void)
+{
+	unsigned short status;
+
+	/*
+	 * Read the interrupt status, and write it back to clear the
+	 * interrupt cause
+	 */
+
+	status = in16r(usb_base_addr + USBSTS);
+
+	if (!status)		/* shared interrupt, not mine */
+		return;
+	if (status != 1) {
+		/* remove host controller halted state */
+		if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
+			out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
+		}
+	}
+	usb_check_int_chain(); /* call interrupt handlers for int tds */
+	usb_check_skel(); /* call completion handler for common transfer routines */
+	out16r(usb_base_addr+USBSTS,status);
+}
+
+
+/* init uhci
+ */
+int usb_lowlevel_init(void)
+{
+	unsigned char temp;
+	int	busdevfunc;
+
+	busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
+	if(busdevfunc==-1) {
+		printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
+		return -1;
+	}
+	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
+	irqvec = temp;
+	irq_free_handler(irqvec);
+	USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec);
+	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
+	USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
+	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
+	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
+	usb_base_addr&=0xFFFFFFF0;
+	usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
+	rh.devnum = 0;
+	usb_init_skel();
+	reset_hc();
+	start_hc();
+	irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
+	return 0;
+}
+
+/* stop uhci
+ */
+int usb_lowlevel_stop(void)
+{
+	if(irqvec==-1)
+		return 1;
+	irq_free_handler(irqvec);
+	reset_hc();
+	irqvec = -1;
+	return 0;
+}
+
+/*******************************************************************************************
+ * Virtual Root Hub
+ * Since the uhci does not have a real HUB, we simulate one ;-)
+ */
+#undef	USB_RH_DEBUG
+
+#ifdef	USB_RH_DEBUG
+#define	USB_RH_PRINTF(fmt,args...)	printf (fmt ,##args)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
+static void usb_display_Req(unsigned short req);
+#else
+#define USB_RH_PRINTF(fmt,args...)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
+static void usb_display_Req(unsigned short req) {}
+#endif
+
+static unsigned char root_hub_dev_des[] =
+{
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x00,			/*  __u16 bcdUSB; v1.0 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x01,			/*  __u8  iManufacturer; */
+	0x00,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static unsigned char root_hub_config_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+     /* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+     /* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x08,			/*  __u16 ep_wMaxPacketSize; 8 Bytes */
+	0x00,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+
+static unsigned char root_hub_hub_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x29,			/*  __u8  bDescriptorType; Hub-descriptor */
+	0x02,			/*  __u8  bNbrPorts; */
+	0x00,			/* __u16  wHubCharacteristics; */
+	0x00,
+	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
+	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
+	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'U',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+
+/*
+ * Root Hub Control Pipe (interrupt Pipes are not supported)
+ */
+
+
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
+{
+	void *data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int status = 0;
+	int stat = 0;
+	int i;
+
+	unsigned short cstatus;
+
+	unsigned short bmRType_bReq;
+	unsigned short wValue;
+	unsigned short wIndex;
+	unsigned short wLength;
+
+	if (usb_pipeint(pipe)) {
+		printf("Root-Hub submit IRQ: NOT implemented\n");
+#if 0
+		uhci->rh.urb = urb;
+		uhci->rh.send = 1;
+		uhci->rh.interval = urb->interval;
+		rh_init_int_timer (urb);
+#endif
+		return 0;
+	}
+	bmRType_bReq = cmd->requesttype | cmd->request << 8;
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+	usb_display_Req(bmRType_bReq);
+	for (i = 0; i < 8; i++)
+		rh.c_p_r[i] = 0;
+	USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
+	     dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
+
+	switch (bmRType_bReq) {
+		/* Request Destination:
+		   without flags: Device,
+		   RH_INTERFACE: interface,
+		   RH_ENDPOINT: endpoint,
+		   RH_CLASS means HUB here,
+		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
+		 */
+
+	case RH_GET_STATUS:
+		*(unsigned short *) data = swap_16(1);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		*(unsigned long *) data = swap_32(0);
+		len=4;
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+
+		status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
+		cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
+			((status & USBPORTSC_PEC) >> (3 - 1)) |
+			(rh.c_p_r[wIndex - 1] << (0 + 4));
+		status = (status & USBPORTSC_CCS) |
+			((status & USBPORTSC_PE) >> (2 - 1)) |
+			((status & USBPORTSC_SUSP) >> (12 - 2)) |
+			((status & USBPORTSC_PR) >> (9 - 4)) |
+			(1 << 8) |	/* power on ** */
+			((status & USBPORTSC_LSDA) << (-8 + 9));
+
+		*(unsigned short *) data = swap_16(status);
+		*(unsigned short *) (data + 2) = swap_16(cstatus);
+		len=4;
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		switch (wValue) {
+		case (RH_ENDPOINT_STALL):
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		switch (wValue) {
+		case (RH_C_HUB_OVER_CURRENT):
+			len=0;	/* hub power over current ** */
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_C_PORT_CONNECTION):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_CSC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PEC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_SUSPEND):
+/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
+			len=0;
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			len=0;
+			break;
+		case (RH_C_PORT_RESET):
+			rh.c_p_r[wIndex - 1] = 0;
+			len=0;
+			break;
+		}
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_RESET):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) & ~USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			udelay(10);
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) | 0xa;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_SET_ADDRESS:
+		rh.devnum = wValue;
+		len=0;
+		break;
+	case RH_GET_DESCRIPTOR:
+		switch ((wValue & 0xff00) >> 8) {
+		case (0x01):	/* device descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_dev_des, len);
+			break;
+		case (0x02):	/* configuration descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_config_des, len);
+			break;
+		case (0x03):	/*string descriptors */
+			if(wValue==0x0300) {
+				i=sizeof(root_hub_str_index0);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index0, len);
+				break;
+			}
+			if(wValue==0x0301) {
+				i=sizeof(root_hub_str_index1);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index1, len);
+				break;
+			}
+			stat = USB_ST_STALLED;
+		}
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		root_hub_hub_des[2] = 2;
+		i=sizeof(root_hub_hub_des);
+		status= i > wLength ? wLength : i;
+		len = leni > status ? status : leni;
+		memcpy (data, root_hub_hub_des, len);
+		break;
+	case RH_GET_CONFIGURATION:
+		*(unsigned char *) data = 0x01;
+		len = 1;
+		break;
+	case RH_SET_CONFIGURATION:
+		len=0;
+		break;
+	default:
+		stat = USB_ST_STALLED;
+	}
+	USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
+	     in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
+	dev->act_len=len;
+	dev->status=stat;
+	return stat;
+
+}
+
+/********************************************************************************
+ * Some Debug Routines
+ */
+
+#ifdef	USB_RH_DEBUG
+
+static void usb_display_Req(unsigned short req)
+{
+	USB_RH_PRINTF("- Root-Hub Request: ");
+	switch (req) {
+	case RH_GET_STATUS:
+		USB_RH_PRINTF("Get Status ");
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		USB_RH_PRINTF("Get Status Interface ");
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		USB_RH_PRINTF("Get Status Endpoint ");
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class");
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class Others");
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		USB_RH_PRINTF("Clear Feature Endpoint ");
+		break;
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Class ");
+		break;
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Other Class ");
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Set Feature Other Class ");
+		break;
+	case RH_SET_ADDRESS:
+		USB_RH_PRINTF("Set Address ");
+		break;
+	case RH_GET_DESCRIPTOR:
+		USB_RH_PRINTF("Get Descriptor ");
+		break;
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		USB_RH_PRINTF("Get Descriptor Class ");
+		break;
+	case RH_GET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	case RH_SET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	default:
+		USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
+	}
+	USB_RH_PRINTF("\n");
+
+}
+
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
+{
+	switch (wValue) {
+		case (RH_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
+			break;
+		case (RH_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
+			break;
+		case (RH_PORT_POWER):
+			USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
+			break;
+		case (RH_C_PORT_CONNECTION):
+			USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_RESET):
+			USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
+			break;
+		default:
+			USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
+			break;
+	}
+}
+
+#endif
+
+
+#ifdef	USB_UHCI_DEBUG
+
+static int usb_display_td(uhci_td_t *td)
+{
+	unsigned long tmp;
+	int valid;
+
+	printf("TD at %p:\n",td);
+
+	tmp=swap_32(td->link);
+	printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
+		((tmp & 0x4)==0x4) ? "Depth" : "Breath",
+		((tmp & 0x2)==0x2) ? "QH" : "TD",
+		((tmp & 0x1)==0x1) ? "invalid" : "valid");
+	valid=((tmp & 0x1)==0x0);
+	tmp=swap_32(td->status);
+	printf("     %s %ld Errors %s %s %s \n     %s %s %s %s %s %s\n     Len 0x%lX\n",
+		(((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
+		((tmp>>28)&0x3),
+		(((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
+		(((tmp>>25)&0x1)==0x1) ? "ISO " : "",
+		(((tmp>>24)&0x1)==0x1) ? "IOC " : "",
+		(((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
+		(((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
+		(((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
+		(((tmp>>20)&0x1)==0x1) ? "Babble" : "",
+		(((tmp>>19)&0x1)==0x1) ? "NAK" : "",
+		(((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
+		(tmp&0x7ff));
+	tmp=swap_32(td->info);
+	printf("     MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
+	printf("     %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
+		((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
+	tmp=swap_32(td->buffer);
+	printf("     Buffer 0x%08lX\n",tmp);
+	printf("     DEV %08lX\n",td->dev_ptr);
+	return valid;
+}
+
+
+void usb_show_td(int max)
+{
+	int i;
+	if(max>0) {
+		for(i=0;i<max;i++) {
+			usb_display_td(&tmp_td[i]);
+		}
+	}
+	else {
+		i=0;
+		do {
+			printf("tmp_td[%d]\n",i);
+		}while(usb_display_td(&tmp_td[i++]));
+	}
+}
+
+
+#endif
+#endif /* CONFIG_USB_UHCI */
+
+/* EOF */
diff --git a/u-boot/board/mpl/common/usb_uhci.h b/u-boot/board/mpl/common/usb_uhci.h
new file mode 100644
index 0000000..af80837
--- /dev/null
+++ b/u-boot/board/mpl/common/usb_uhci.h
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_UHCI_H_
+#define _USB_UHCI_H_
+
+
+/* Command register */
+#define USBCMD		0
+#define   USBCMD_RS       0x0001	/* Run/Stop */
+#define   USBCMD_HCRESET  0x0002	/* Host reset */
+#define   USBCMD_GRESET   0x0004	/* Global reset */
+#define   USBCMD_EGSM     0x0008	/* Global Suspend Mode */
+#define   USBCMD_FGR      0x0010	/* Force Global Resume */
+#define   USBCMD_SWDBG    0x0020	/* SW Debug mode */
+#define   USBCMD_CF       0x0040	/* Config Flag (sw only) */
+#define   USBCMD_MAXP     0x0080	/* Max Packet (0 = 32, 1 = 64) */
+
+/* Status register */
+#define USBSTS		2
+#define   USBSTS_USBINT   0x0001	/* Interrupt due to IOC */
+#define   USBSTS_ERROR    0x0002	/* Interrupt due to error */
+#define   USBSTS_RD       0x0004	/* Resume Detect */
+#define   USBSTS_HSE      0x0008	/* Host System Error - basically PCI problems */
+#define   USBSTS_HCPE     0x0010	/* Host Controller Process Error - the scripts were buggy */
+#define   USBSTS_HCH      0x0020	/* HC Halted */
+
+/* Interrupt enable register */
+#define USBINTR		4
+#define   USBINTR_TIMEOUT 0x0001	/* Timeout/CRC error enable */
+#define   USBINTR_RESUME  0x0002	/* Resume interrupt enable */
+#define   USBINTR_IOC     0x0004	/* Interrupt On Complete enable */
+#define   USBINTR_SP      0x0008	/* Short packet interrupt enable */
+
+#define USBFRNUM      6
+#define USBFLBASEADD  8
+#define USBSOF        12
+
+/* USB port status and control registers */
+#define USBPORTSC1	16
+#define USBPORTSC2	18
+#define   USBPORTSC_CCS   0x0001	/* Current Connect Status ("device present") */
+#define   USBPORTSC_CSC   0x0002	/* Connect Status Change */
+#define   USBPORTSC_PE    0x0004	/* Port Enable */
+#define   USBPORTSC_PEC   0x0008	/* Port Enable Change */
+#define   USBPORTSC_LS    0x0030	/* Line Status */
+#define   USBPORTSC_RD    0x0040	/* Resume Detect */
+#define   USBPORTSC_LSDA  0x0100	/* Low Speed Device Attached */
+#define   USBPORTSC_PR    0x0200	/* Port Reset */
+#define   USBPORTSC_SUSP  0x1000	/* Suspend */
+
+/* Legacy support register */
+#define USBLEGSUP 0xc0
+#define USBLEGSUP_DEFAULT 0x2000	/* only PIRQ enable set */
+
+#define UHCI_NULL_DATA_SIZE 0x7ff	/* for UHCI controller TD */
+#define UHCI_PID            0xff	/* PID MASK */
+
+#define UHCI_PTR_BITS       0x000F
+#define UHCI_PTR_TERM       0x0001
+#define UHCI_PTR_QH         0x0002
+#define UHCI_PTR_DEPTH      0x0004
+
+/* for TD <status>: */
+#define TD_CTRL_SPD         (1 << 29)	/* Short Packet Detect */
+#define TD_CTRL_C_ERR_MASK  (3 << 27)	/* Error Counter bits */
+#define TD_CTRL_LS          (1 << 26)	/* Low Speed Device */
+#define TD_CTRL_IOS         (1 << 25)	/* Isochronous Select */
+#define TD_CTRL_IOC         (1 << 24)	/* Interrupt on Complete */
+#define TD_CTRL_ACTIVE      (1 << 23)	/* TD Active */
+#define TD_CTRL_STALLED     (1 << 22)	/* TD Stalled */
+#define TD_CTRL_DBUFERR     (1 << 21)	/* Data Buffer Error */
+#define TD_CTRL_BABBLE      (1 << 20)	/* Babble Detected */
+#define TD_CTRL_NAK         (1 << 19)	/* NAK Received */
+#define TD_CTRL_CRCTIMEO    (1 << 18)	/* CRC/Time Out Error */
+#define TD_CTRL_BITSTUFF    (1 << 17)	/* Bit Stuff Error */
+#define TD_CTRL_ACTLEN_MASK 0x7ff	/* actual length, encoded as n - 1 */
+
+#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
+				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
+
+#define TD_TOKEN_TOGGLE		19
+
+/* ------------------------------------------------------------------------------------
+   Virtual Root HUB
+   ------------------------------------------------------------------------------------ */
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+/* Our Vendor Specific feature */
+#define RH_REMOVE_EP               0x00
+
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+
+/* Transfer descriptor structure */
+typedef struct {
+	unsigned long link;     /* next td/qh (LE)*/
+	unsigned long status;   /* status of the td */
+	unsigned long info;     /* Max Lenght / Endpoint / device address and PID */
+	unsigned long buffer;   /* pointer to data buffer (LE) */
+	unsigned long dev_ptr;  /* pointer to the assigned device (BE) */
+	unsigned long res[3];   /* reserved (TDs must be 8Byte aligned) */
+} uhci_td_t, *puhci_td_t;
+
+/* Queue Header structure */
+typedef struct {
+	unsigned long head;       /* Next QH (LE)*/
+	unsigned long element;		/* Queue element pointer (LE) */
+	unsigned long res[5];     /* reserved */
+	unsigned long dev_ptr;    /* if 0 no tds have been assigned to this qh */
+} uhci_qh_t, *puhci_qh_t;
+
+struct virt_root_hub {
+	int devnum;		            /* Address of Root Hub endpoint */
+	int numports;             /* number of ports */
+	int c_p_r[8];             /* C_PORT_RESET */
+};
+
+
+#endif /* _USB_UHCI_H_ */
diff --git a/u-boot/board/mpl/mip405/Makefile b/u-boot/board/mpl/mip405/Makefile
new file mode 100644
index 0000000..042cd83
--- /dev/null
+++ b/u-boot/board/mpl/mip405/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
+			../common/usb_uhci.o ../common/common_util.o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mpl/mip405/cmd_mip405.c b/u-boot/board/mpl/mip405/cmd_mip405.c
new file mode 100644
index 0000000..f7cc37b
--- /dev/null
+++ b/u-boot/board/mpl/mip405/cmd_mip405.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for MIP405
+ */
+
+#include <common.h>
+#include <command.h>
+#include "mip405.h"
+#include "../common/common_util.h"
+
+
+extern void print_mip405_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+
+	ulong led_on;
+
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_mip405_info();
+		return 0;
+	}
+	if (strcmp(argv[1], "led") == 0)
+	{
+		led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
+		user_led0(led_on);
+		return 0;
+	}
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+U_BOOT_CMD(
+	mip405,	8,	1,	do_mip405,
+	"MIP405 specific Cmds",
+	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+	"mip405 flash mps - updates U-Boot with image from MPS\n"
+	"mip405 info      - displays board information\n"
+	"mip405 led <on>  - switches LED on (on=1) or off (on=0)"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/mpl/mip405/init.S b/u-boot/board/mpl/mip405/init.S
new file mode 100644
index 0000000..39a1d68
--- /dev/null
+++ b/u-boot/board/mpl/mip405/init.S
@@ -0,0 +1,221 @@
+/*------------------------------------------------------------------------------+
+ *      This source code is dual-licensed.  You may use it under the terms of
+ *      the GNU General Public License version 2, or under the license below.
+ *
+ *      This source code has been made available to you by IBM on an AS-IS
+ *      basis.  Anyone receiving this source is licensed under IBM
+ *      copyrights to use it in any way he or she deems fit, including
+ *      copying it, modifying it, compiling it, and redistributing it either
+ *      with or without modifications.  No license under IBM patents or
+ *      patent applications is to be implied by the copyright license.
+ *
+ *      Any user of this software should understand that IBM cannot provide
+ *      technical support for this software and will not be responsible for
+ *      any consequences resulting from the use of this software.
+ *
+ *      Any person who transfers this source code or any derivative work
+ *      must include the IBM copyright notice, this paragraph, and the
+ *      preceding two paragraphs in the transferred software.
+ *
+ *      COPYRIGHT   I B M   CORPORATION 1995
+ *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-------------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Function:     ext_bus_cntlr_init
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *	Bank 0 - Flash or Multi Purpose Socket
+ *	Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
+ *	Bank 2 - UART 1 (set in C-Code)
+ *	Bank 3 - UART 2 (set in C-Code)
+ *	Bank 4 - not used
+ *	Bank 5 - not used
+ *	Bank 6 - not used
+ *	Bank 7 - PLD Register
+ *-----------------------------------------------------------------------------*/
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <configs/MIP405.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+#include "mip405.h"
+
+
+  .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+  mflr   r4                      /* save link register */
+  mfdcr  r3,CPC0_PSR                /* get strapping reg */
+  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
+  bnelr                          /* jump back if PCI boot */
+
+  bl      ..getAddr
+..getAddr:
+  mflr    r3                      /* get address of ..getAddr */
+  mtlr    r4                      /* restore link register */
+  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
+  mtctr   r4                      /* 14 cache lines to fit this function */
+				   /* in cache (gives us 8x14=112 instrctns) */
+..ebcloop:
+  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+  addi    r3,r3,32								/* move to next cache line */
+  bdnz    ..ebcloop               /* continue for 14 cache lines */
+
+   /*-------------------------------------------------------------------
+    * Delay to ensure all accesses to ROM are complete before changing
+    * bank 0 timings.
+    *------------------------------------------------------------------- */
+	addis	r3,0,0x0
+  ori     r3,r3,0xA000
+  mtctr   r3
+..spinlp:
+  bdnz    ..spinlp                /* spin loop */
+
+	/*-----------------------------------------------------------------------
+	 * decide boot up mode
+	 *----------------------------------------------------------------------- */
+	addi		r4,0,PB0CR
+	mtdcr		EBC0_CFGADDR,r4
+	mfdcr		r4,EBC0_CFGDATA
+
+	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
+	beq		0f				/* jump if 8 bit bus width */
+
+	/* setup 16 bit things
+   *-----------------------------------------------------------------------
+   * Memory Bank 0 (16 Bit Flash) initialization
+   *---------------------------------------------------------------------- */
+
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,(FLASH_AP_B)@h
+	ori     r4,r4,(FLASH_AP_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(FLASH_CR_B)@h
+	ori     r4,r4,(FLASH_CR_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+	b				1f
+
+0:
+
+	/* 8Bit boot mode: */
+	/*-----------------------------------------------------------------------
+	* Memory Bank 0 Multi Purpose Socket initialization
+	*----------------------------------------------------------------------- */
+	/* 0x7F8FFE80 slowest boot */
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,(MPS_AP_B)@h
+	ori     r4,r4,(MPS_AP_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(MPS_CR_B)@h
+	ori     r4,r4,(MPS_CR_B)@l
+
+	mtdcr   EBC0_CFGDATA,r4
+
+
+1:
+  /*-----------------------------------------------------------------------
+   * Memory Bank 2-3-4-5-6 (not used) initialization
+   *-----------------------------------------------------------------------*/
+  addi    r4,0,PB1CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB2CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB3CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB4CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB5CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB6CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB7CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+  nop				/* pass2 DCR errata #8 */
+  blr
+
+#if defined(CONFIG_BOOT_PCI)
+    .section .bootpg,"ax"
+    .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+  /* first handle errata #68 / PCI_18 */
+  iccci   r0, r0          /* invalidate I-cache */
+  lis     r31, 0
+  mticcr  r31             /* ICCR = 0 (all uncachable) */
+  isync
+
+  mfccr0  r28             /* set CCR0[24] = 1 */
+  ori     r28, r28, 0x0080
+  mtccr0  r28
+
+  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+  lis     r28, 0xEF40
+  addi    r28, r28, 0x0004
+  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
+  lis     r29, 0xFFF8     /* open 512 kByte */
+  addi    r29, r29, 0x0001/* and enable this region */
+  stwbrx  r29, r0, r28    /* write PMM0MA */
+
+  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
+  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
+
+  lis     r31, 0x8000     /* set en bit bus 0 */
+  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+  stwbrx  r31, r0, r28    /* write it */
+
+  lwbrx   r31, r0, r29    /* load XBCS register */
+  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+  stwbrx  r31, r0, r29    /* write back XBCS register */
+
+  nop
+  nop
+  b	_start		/* normal start */
+#endif
diff --git a/u-boot/board/mpl/mip405/mip405.c b/u-boot/board/mpl/mip405/mip405.c
new file mode 100644
index 0000000..e93d994
--- /dev/null
+++ b/u-boot/board/mpl/mip405/mip405.c
@@ -0,0 +1,805 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+/*
+ * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
+ *
+ * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
+ * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
+ * parameters from the datasheet are:
+ * Tclk = 7.5ns (CL = 2)
+ * Trp = 15ns
+ * Trc = 60ns
+ * Trcd = 15ns
+ * Trfc = 66ns
+ *
+ * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
+ * period is 10ns and the parameters needed for the Timing Register are:
+ * CASL = CL = 2 clock cycles
+ * PTA = Trp = 15ns / 10ns = 2 clock cycles
+ * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
+ * LDF = 2 clock cycles (but can be extended to meet board-level timing)
+ * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
+ * RCD = Trcd = 15ns / 10ns= 2 clock cycles
+ *
+ * The actual bit settings in the register would be:
+ *
+ * CASL = 0b01
+ * PTA = 0b01
+ * CTP = 0b10
+ * LDF = 0b01
+ * RFTA = 0b011
+ * RCD = 0b01
+ *
+ * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
+ * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
+ * defined as Trc rather than Trfc.
+ * When using DIMM modules, most but not all of the required timing parameters can be read
+ * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
+ * are not available from the EEPROM
+ */
+
+#include <common.h>
+#include "mip405.h"
+#include <asm/processor.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <miiphy.h>
+#include "../common/common_util.h"
+#include <stdio_dev.h>
+#include <i2c.h>
+#include <rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SDRAM_DEBUG
+#define ENABLE_ECC /* for ecc boards */
+#define FALSE           0
+#define TRUE            1
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+	long int quot;		/* Quotient	*/
+	long int rem;		/* Remainder	*/
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+# define __ldiv_t_defined	1
+#endif
+
+
+#define PLD_PART_REG		PER_PLD_ADDR + 0
+#define PLD_VERS_REG		PER_PLD_ADDR + 1
+#define PLD_BOARD_CFG_REG	PER_PLD_ADDR + 2
+#define PLD_IRQ_REG		PER_PLD_ADDR + 3
+#define PLD_COM_MODE_REG	PER_PLD_ADDR + 4
+#define PLD_EXT_CONF_REG	PER_PLD_ADDR + 5
+
+#define MEGA_BYTE (1024*1024)
+
+typedef struct {
+	unsigned char boardtype; /* Board revision and Population Options */
+	unsigned char cal;		/* cas Latency (will be programmend as cal-1) */
+	unsigned char trp;		/* datain27 in clocks */
+	unsigned char trcd;		/* datain29 in clocks */
+	unsigned char tras;		/* datain30 in clocks */
+	unsigned char tctp;		/* tras - trcd in clocks */
+	unsigned char am;		/* Address Mod (will be programmed as am-1) */
+	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+	unsigned char ecc;		/* if true, ecc is enabled */
+} sdram_t;
+#if defined(CONFIG_MIP405T)
+const sdram_t sdram_table[] = {
+	{ 0x0F,	/* MIP405T Rev A, 64MByte -1 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		2,	/* Address Mode = 2 (12x9x4) */
+		3,	/* size value (32MByte) */
+		0},	/* ECC disabled */
+	{ 0xff, /* terminator */
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff }
+};
+#else
+const sdram_t sdram_table[] = {
+	{ 0x0f,	/* Rev A, 128MByte -1 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x07,	/* Rev A, 64MByte -2 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		2,	/* Address Mode = 2 */
+		4,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x03,	/* Rev A, 128MByte -4 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x1f,	/* Rev B, 128MByte -3 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x2f,	/* Rev C, 128MByte -3 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0xff, /* terminator */
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff }
+};
+#endif /*CONFIG_MIP405T */
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+#endif
+	serial_puts ("\n");
+	serial_puts (s);
+	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+	for (;;);
+}
+
+
+unsigned char get_board_revcfg (void)
+{
+	out8 (PER_BOARD_ADDR, 0);
+	return (in8 (PER_BOARD_ADDR));
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+
+int init_sdram (void)
+{
+	unsigned long	tmp, baseaddr;
+	unsigned short	i;
+	unsigned char	trp_clocks,
+			trcd_clocks,
+			tras_clocks,
+			trc_clocks,
+			tctp_clocks;
+	unsigned char	cal_val;
+	unsigned char	bc;
+	unsigned long	sdram_tim, sdram_bank;
+
+	/*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+	/* set up the pld */
+	mtdcr (EBC0_CFGADDR, PB7AP);
+	mtdcr (EBC0_CFGDATA, PLD_AP);
+	mtdcr (EBC0_CFGADDR, PB7CR);
+	mtdcr (EBC0_CFGDATA, PLD_CR);
+	/* THIS IS OBSOLETE */
+	/* set up the board rev reg*/
+	mtdcr (EBC0_CFGADDR, PB5AP);
+	mtdcr (EBC0_CFGDATA, BOARD_AP);
+	mtdcr (EBC0_CFGADDR, PB5CR);
+	mtdcr (EBC0_CFGDATA, BOARD_CR);
+#ifdef SDRAM_DEBUG
+	/* get all informations from PLD */
+	serial_puts ("\nPLD Part  0x");
+	bc = in8 (PLD_PART_REG);
+	write_hex (bc);
+	serial_puts ("\nPLD Vers  0x");
+	bc = in8 (PLD_VERS_REG);
+	write_hex (bc);
+	serial_puts ("\nBoard Rev 0x");
+	bc = in8 (PLD_BOARD_CFG_REG);
+	write_hex (bc);
+	serial_puts ("\n");
+#endif
+	/* check board */
+	bc = in8 (PLD_PART_REG);
+#if defined(CONFIG_MIP405T)
+	if((bc & 0x80)==0)
+		SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
+#else
+	if((bc & 0x80)==0x80)
+		SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
+#endif
+	/* set-up the chipselect machine */
+	mtdcr (EBC0_CFGADDR, PB0CR);		/* get cs0 config reg */
+	tmp = mfdcr (EBC0_CFGDATA);
+	if ((tmp & 0x00002000) == 0) {
+		/* MPS Boot, set up the flash */
+		mtdcr (EBC0_CFGADDR, PB1AP);
+		mtdcr (EBC0_CFGDATA, FLASH_AP);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		mtdcr (EBC0_CFGDATA, FLASH_CR);
+	} else {
+		/* Flash boot, set up the MPS */
+		mtdcr (EBC0_CFGADDR, PB1AP);
+		mtdcr (EBC0_CFGDATA, MPS_AP);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		mtdcr (EBC0_CFGDATA, MPS_CR);
+	}
+	/* set up UART0 (CS2) and UART1 (CS3) */
+	mtdcr (EBC0_CFGADDR, PB2AP);
+	mtdcr (EBC0_CFGDATA, UART0_AP);
+	mtdcr (EBC0_CFGADDR, PB2CR);
+	mtdcr (EBC0_CFGDATA, UART0_CR);
+	mtdcr (EBC0_CFGADDR, PB3AP);
+	mtdcr (EBC0_CFGDATA, UART1_AP);
+	mtdcr (EBC0_CFGADDR, PB3CR);
+	mtdcr (EBC0_CFGDATA, UART1_CR);
+	bc = in8 (PLD_BOARD_CFG_REG);
+#ifdef SDRAM_DEBUG
+	serial_puts ("\nstart SDRAM Setup\n");
+	serial_puts ("\nBoard Rev: ");
+	write_hex (bc);
+	serial_puts ("\n");
+#endif
+	i = 0;
+	baseaddr = CONFIG_SYS_SDRAM_BASE;
+	while (sdram_table[i].sz != 0xff) {
+		if (sdram_table[i].boardtype == bc)
+			break;
+		i++;
+	}
+	if (sdram_table[i].boardtype != bc)
+		SDRAM_err ("No SDRAM table found for this board!!!\n");
+#ifdef SDRAM_DEBUG
+	serial_puts (" found table ");
+	write_hex (i);
+	serial_puts (" \n");
+#endif
+	/* since the ECC initialisation needs some time,
+	 * we show that we're alive
+	 */
+	if (sdram_table[i].ecc)
+		serial_puts ("\nInitializing SDRAM, Please stand by");
+	cal_val = sdram_table[i].cal - 1;	/* Cas Latency */
+	trp_clocks = sdram_table[i].trp;	/* 20ns / 7.5 ns datain[27] */
+	trcd_clocks = sdram_table[i].trcd;	/* 20ns /7.5 ns (datain[29]) */
+	tras_clocks = sdram_table[i].tras;	/* 44ns /7.5 ns  (datain[30]) */
+	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+	tctp_clocks = sdram_table[i].tctp;	/* 44 - 20ns = 24ns */
+	/* trc_clocks is sum of trp_clocks + tras_clocks */
+	trc_clocks = trp_clocks + tras_clocks;
+	/* get SDRAM timing register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
+	/* insert CASL value */
+	sdram_tim |= ((unsigned long) (cal_val)) << 23;
+	/* insert PTA value */
+	sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
+	/* insert CTP value */
+	sdram_tim |=
+			((unsigned long) (trc_clocks - trp_clocks -
+							  trcd_clocks)) << 16;
+	/* insert LDF (always 01) */
+	sdram_tim |= ((unsigned long) 0x01) << 14;
+	/* insert RFTA value */
+	sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
+	/* insert RCD value */
+	sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+	tmp = ((unsigned long) (sdram_table[i].am - 1) << 13);	/* AM = 3 */
+	/* insert SZ value; */
+	tmp |= ((unsigned long) sdram_table[i].sz << 17);
+	/* get SDRAM bank 0 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+	sdram_bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("sdtr: ");
+	write_4hex (sdram_tim);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM timing register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	mtdcr (SDRAM0_CFGDATA, sdram_tim);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("mb0cf: ");
+	write_4hex (sdram_bank);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM bank 0 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	mtdcr (SDRAM0_CFGDATA, sdram_bank);
+
+	if (get_bus_freq (tmp) > 110000000) {	/* > 110MHz */
+		/* get SDRAM refresh interval register */
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+		tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
+		tmp |= 0x07F00000;
+	} else {
+		/* get SDRAM refresh interval register */
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+		tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
+		tmp |= 0x05F00000;
+	}
+	/* write SDRAM refresh interval register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	mtdcr (SDRAM0_CFGDATA, tmp);
+	/* enable ECC if used */
+#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
+	if (sdram_table[i].ecc) {
+		/* disable checking for all banks */
+		unsigned long	*p;
+#ifdef SDRAM_DEBUG
+		serial_puts ("disable ECC.. ");
+#endif
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+		tmp = mfdcr (SDRAM0_CFGDATA);
+		tmp &= 0xff0fffff;		/* disable all banks */
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+		/* set up SDRAM Controller with ECC enabled */
+#ifdef SDRAM_DEBUG
+		serial_puts ("setup SDRAM Controller.. ");
+#endif
+		mtdcr (SDRAM0_CFGDATA, tmp);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+		tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+		mtdcr (SDRAM0_CFGDATA, tmp);
+		udelay (600);
+#ifdef SDRAM_DEBUG
+		serial_puts ("fill the memory..\n");
+#endif
+		serial_puts (".");
+		/* now, fill all the memory */
+		tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
+		p = (unsigned long) 0;
+		while ((unsigned long) p < tmp) {
+			*p++ = 0L;
+			if (!((unsigned long) p % 0x00800000))	/* every 8MByte */
+				serial_puts (".");
+		}
+		/* enable bank 0 */
+		serial_puts (".");
+#ifdef SDRAM_DEBUG
+		serial_puts ("enable ECC\n");
+#endif
+		udelay (400);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+		tmp = mfdcr (SDRAM0_CFGDATA);
+		tmp |= 0x00800000;		/* enable bank 0 */
+		mtdcr (SDRAM0_CFGDATA, tmp);
+		udelay (400);
+	} else
+#endif
+	{
+		/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+		tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+		mtdcr (SDRAM0_CFGDATA, tmp);
+		udelay (400);
+	}
+	serial_puts ("\n");
+	return (0);
+}
+
+int board_early_init_f (void)
+{
+	init_sdram ();
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the PIP405 board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for MIP405 board:
+   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
+   |       the Interrupt Controller in the South Bridge has caused the
+   |       interrupt. The IC must be read to determine which device
+   |       caused the interrupt.
+   |
+   +-------------------------------------------------------------------------*/
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	return 0;
+}
+
+
+/*
+ * Get some PLD Registers
+ */
+
+unsigned short get_pld_parvers (void)
+{
+	unsigned short result;
+	unsigned char rc;
+
+	rc = in8 (PLD_PART_REG);
+	result = (unsigned short) rc << 8;
+	rc = in8 (PLD_VERS_REG);
+	result |= rc;
+	return result;
+}
+
+
+void user_led0 (unsigned char on)
+{
+	if (on)
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
+	else
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
+}
+
+
+void ide_set_reset (int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset)
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
+	else {
+		udelay (10000);
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
+	}
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
+{
+#if !defined(CONFIG_MIP405T)
+	unsigned char bc,rc,tmp;
+	int i;
+
+	bc = in8 (PLD_BOARD_CFG_REG);
+	tmp = ~bc;
+	tmp &= 0xf;
+	rc = 0;
+	for (i = 0; i < 4; i++) {
+		rc <<= 1;
+		rc += (tmp & 0x1);
+		tmp >>= 1;
+	}
+	rc++;
+	if((  (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
+	   || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
+		&& (rc==0x1))     /* Population Option 1 is a -3 */
+		rc=3;
+	*pcbrev=(bc >> 4) & 0xf;
+	*var=rc;
+#else
+	unsigned char bc;
+	bc = in8 (PLD_BOARD_CFG_REG);
+	*pcbrev=(bc >> 4) & 0xf;
+	*var=16-(bc & 0xf);
+#endif
+}
+
+/*
+ * Check Board Identity:
+ */
+/* serial String: "MIP405_1000" OR "MIP405T_1000" */
+#if !defined(CONFIG_MIP405T)
+#define BOARD_NAME	"MIP405"
+#else
+#define BOARD_NAME	"MIP405T"
+#endif
+
+int checkboard (void)
+{
+	char s[50];
+	unsigned char bc, var;
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	puts ("Board: ");
+	get_pcbrev_var(&bc,&var);
+	i = getenv_f("serial#", (char *)s, 32);
+	if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming " BOARD_NAME);
+			printf ("-%d Rev %c", var, 'A' + bc);
+		} else {
+			b->serial_name[sizeof(BOARD_NAME)-1] = 0;
+			printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
+					'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
+		}
+	} else {
+		s[sizeof(BOARD_NAME)-1] = 0;
+		printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
+				&s[sizeof(BOARD_NAME)]);
+	}
+	bc = in8 (PLD_EXT_CONF_REG);
+	printf (" Boot Config: 0x%x\n", bc);
+	return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+phys_size_t initdram (int board_type)
+{
+
+	unsigned long bank_reg[4], tmp, bank_size;
+	int i, ds;
+	unsigned long TotalSize;
+
+	ds = 0;
+	/* since the DRAM controller is allready set up, calculate the size with the
+	   bank registers    */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
+	TotalSize = 0;
+	for (i = 0; i < 4; i++) {
+		if ((bank_reg[i] & 0x1) == 0x1) {
+			tmp = (bank_reg[i] >> 17) & 0x7;
+			bank_size = 4 << tmp;
+			TotalSize += bank_size;
+		} else
+			ds = 1;
+	}
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+	tmp = mfdcr (SDRAM0_CFGDATA);
+
+	if (!tmp)
+		printf ("No ");
+	printf ("ECC ");
+
+	test_dram (TotalSize * MEGA_BYTE);
+	return (TotalSize * MEGA_BYTE);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+#ifdef SDRAM_DEBUG
+	mem_test (0L, ramsize, 1);
+#endif
+	/* not yet implemented */
+	return (1);
+}
+
+/* used to check if the time in RTC is valid */
+static unsigned long start;
+static struct rtc_time tm;
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
+	/* check, if RTC is running */
+	rtc_get (&tm);
+	start=get_timer(0);
+	/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+	if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
+	       mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
+
+	return (0);
+}
+
+
+void print_mip405_rev (void)
+{
+	unsigned char part, vers, pcbrev, var;
+
+	get_pcbrev_var(&pcbrev,&var);
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	printf ("Rev:   " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
+			var, pcbrev + 'A', part & 0x7F, vers);
+}
+
+
+extern int mk_date (char *, struct rtc_time *);
+
+int last_stage_init (void)
+{
+	unsigned long stop;
+	struct rtc_time newtm;
+	char *s;
+
+	/* write correct LED configuration */
+	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
+		printf ("Error writing to the PHY\n");
+	}
+	/* since LED/CFG2 is not connected on the -2,
+	 * write to correct capability information */
+	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
+		printf ("Error writing to the PHY\n");
+	}
+	print_mip405_rev ();
+	stdio_print_current_devices ();
+	check_env ();
+	/* check if RTC time is valid */
+	stop=get_timer(start);
+	while(stop<1200) {   /* we wait 1.2 sec to check if the RTC is running */
+		udelay(1000);
+		stop=get_timer(start);
+	}
+	rtc_get (&newtm);
+	if(tm.tm_sec==newtm.tm_sec) {
+		s=getenv("defaultdate");
+		if(!s)
+			mk_date ("010112001970", &newtm);
+		else
+			if(mk_date (s, &newtm)!=0) {
+				printf("RTC: Bad date format in defaultdate\n");
+				return 0;
+			}
+		rtc_reset ();
+		rtc_set(&newtm);
+	}
+	return 0;
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+	return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0);	/* return TRUE if console should be overwritten */
+}
+
+
+/************************************************************************
+* Print MIP405 Info
+************************************************************************/
+void print_mip405_info (void)
+{
+	unsigned char part, vers, cfg, irq_reg, com_mode, ext;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	irq_reg = in8 (PLD_IRQ_REG);
+	com_mode = in8 (PLD_COM_MODE_REG);
+	ext = in8 (PLD_EXT_CONF_REG);
+
+	printf ("PLD Part %d version %d\n", part & 0x7F, vers);
+	printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
+	printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
+			(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
+	printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
+	printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
+#if !defined(CONFIG_MIP405T)
+	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
+			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
+			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
+			(ext >> 6) & 0x1, (ext >> 7) & 0x1);
+	printf ("SER1 uses handshakes %s\n",
+			(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
+#else
+	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
+			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
+			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
+			(ext >> 6) & 0x1,(ext >> 7) & 0x1);
+#endif
+	printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
+	printf ("IRQs:\n");
+	printf ("  PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
+#if !defined(CONFIG_MIP405T)
+	printf ("  UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
+	printf ("  UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
+#endif
+	printf ("  PIIX SMI:  %s\n", (irq_reg & 0x10) ? "inactive" : "active");
+	printf ("  PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
+	printf ("  PIIX NMI:  %s\n", (irq_reg & 0x4) ? "inactive" : "active");
+}
diff --git a/u-boot/board/mpl/mip405/mip405.h b/u-boot/board/mpl/mip405/mip405.h
new file mode 100644
index 0000000..fd7e78a
--- /dev/null
+++ b/u-boot/board/mpl/mip405/mip405.h
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for MIP405
+ *****************************************************************************/
+#ifndef __ASSEMBLY__
+/*int switch_cs(unsigned char boot);*/
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void user_led0(unsigned char on);
+
+
+#endif
+/* timings */
+/* PLD (CS7) */
+#define PLD_BME	0	/* Burst disable */
+#define PLD_TWE	5	/* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define PLD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define PLD_OEN	1	/* Cycles from CS low to OE low   */
+#define PLD_WBN	1	/* Cycles from CS low to WE low   */
+#define PLD_WBF	1	/* Cycles from WE high to CS high */
+#define PLD_TH	2	/* Number of hold cycles after transfer */
+#define PLD_RE	0	/* Ready disabled */
+#define PLD_SOR	1	/* Sample on Ready disabled */
+#define PLD_BEM	0	/* Byte Write only active on Write cycles */
+#define PLD_PEN	0	/* Parity disable */
+#define PLD_AP	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
+					(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define PLD_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define PLD_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define PLD_BW	0	/* 16Bit */
+#define PLD_CR	((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
+
+
+/* timings */
+
+#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
+/* Dummy CS to get the board revision */
+#define BOARD_BME	0	/* Burst disable */
+#define BOARD_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define BOARD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define BOARD_OEN	1	/* Cycles from CS low to OE low   */
+#define BOARD_WBN	1	/* Cycles from CS low to WE low   */
+#define BOARD_WBF	1	/* Cycles from WE high to CS high */
+#define BOARD_TH	2	/* Number of hold cycles after transfer */
+#define BOARD_RE	0	/* Ready disabled */
+#define BOARD_SOR	1	/* Sample on Ready disabled */
+#define BOARD_BEM	0	/* Byte Write only active on Write cycles */
+#define BOARD_PEN	0	/* Parity disable */
+#define BOARD_AP	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
+					(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define BOARD_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define BOARD_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define BOARD_BW	0	/* 16Bit */
+#define BOARD_CR	((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
+
+
+/* UART0 CS2 */
+#define UART0_BME	0	/* Burst disable */
+#define UART0_TWE	7	/* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
+#define UART0_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define UART0_OEN	1	/* Cycles from CS low to OE low   */
+#define UART0_WBN	1	/* Cycles from CS low to WE low   */
+#define UART0_WBF	1	/* Cycles from WE high to CS high */
+#define UART0_TH	2	/* Number of hold cycles after transfer */
+#define UART0_RE	0	/* Ready disabled */
+#define UART0_SOR	1	/* Sample on Ready disabled */
+#define UART0_BEM	0	/* Byte Write only active on Write cycles */
+#define UART0_PEN	0	/* Parity disable */
+#define UART0_AP	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
+					(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define UART0_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define UART0_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define UART0_BW	0	/* 8Bit */
+#define UART0_CR	((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
+
+/* UART1 CS3 */
+#define UART1_AP UART0_AP /* same timing as UART0 */
+#define UART1_CR	((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
+
+
+/* Flash CS0 or CS 1 */
+/* 0x7F8FFE80 slowest timing at all... */
+#define FLASH_BME_B	1	/* Burst enable */
+#define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
+#define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define FLASH_BME	0	/* Burst disable */
+#define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define FLASH_OEN	1	/* Cycles from CS low to OE low   */
+#define FLASH_WBN	1	/* Cycles from CS low to WE low   */
+#define FLASH_WBF	1	/* Cycles from WE high to CS high */
+#define FLASH_TH	2	/* Number of hold cycles after transfer */
+#define FLASH_RE	0	/* Ready disabled */
+#define FLASH_SOR	1	/* Sample on Ready disabled */
+#define FLASH_BEM	0	/* Byte Write only active on Write cycles */
+#define FLASH_PEN	0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define FLASH_AP	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+/* Access Parameter Register for Boot */
+#define FLASH_AP_B	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define FLASH_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define FLASH_BW	1	/* 16Bit */
+/* CR register for Boot */
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+/* CR register for non Boot */
+#define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+
+/* MPS CS1 or CS0 */
+/* Boot CS: */
+#define MPS_BME_B	1	/* Burst enable */
+#define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
+#define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define MPS_BME		0	/* Burst disable */
+#define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define MPS_OEN		1	/* Cycles from CS low to OE low   */
+#define MPS_WBN		1	/* Cycles from CS low to WE low   */
+#define MPS_WBF		1	/* Cycles from WE high to CS high */
+#define MPS_TH		2	/* Number of hold cycles after transfer */
+#define MPS_RE		0	/* Ready disabled */
+#define MPS_SOR		1	/* Sample on Ready disabled */
+#define MPS_BEM		0	/* Byte Write only active on Write cycles */
+#define MPS_PEN		0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define MPS_AP		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+/* Access Parameter Register for Boot */
+#define MPS_AP_B		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define MPS_BU		3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define MPS_BW		0	/* 8Bit */
+/* CR register for Boot */
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+/* CR register for non Boot */
+#define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/u-boot/board/mpl/pati/Makefile b/u-boot/board/mpl/pati/Makefile
new file mode 100644
index 0000000..937dfec
--- /dev/null
+++ b/u-boot/board/mpl/pati/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:=  pati.o ../common/flash.o cmd_pati.o ../common/common_util.o
+#### cmd_pati.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mpl/pati/cmd_pati.c b/u-boot/board/mpl/pati/cmd_pati.c
new file mode 100644
index 0000000..aba11d5
--- /dev/null
+++ b/u-boot/board/mpl/pati/cmd_pati.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Adapted for PATI
+ */
+
+#include <common.h>
+#include <command.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+#include "pci_eeprom.h"
+
+extern void show_pld_regs(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern void user_led0(int led_on);
+extern void user_led1(int led_on);
+
+/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
+extern void pci_con_disc(void);
+extern void pci_con_connect(void);
+#endif
+
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+unsigned long get32(unsigned long addr)
+{
+	unsigned long *p=(unsigned long *)addr;
+	return *p;
+}
+
+void set32(unsigned long addr,unsigned long data)
+{
+	unsigned long *p=(unsigned long *)addr;
+	*p=data;
+}
+
+#define PCICFG_GET_REG(x)	(get32((x) + PCI_CONFIG_BASE))
+#define PCICFG_SET_REG(x,y)	(set32((x) + PCI_CONFIG_BASE,(y)))
+
+
+/******************************************************************************
+ * reload_pci_eeprom
+ ******************************************************************************/
+
+static void reload_pci_eeprom(void)
+{
+	unsigned long reg;
+	/* Set Bit 29 and clear it again */
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	udelay(1);
+	/* set it*/
+	reg|=(1<<29);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	/* EECLK @ 33MHz = 125kHz
+	 * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
+	 * use 20msec
+	 */
+	udelay(20000); /* wait 20ms */
+	reg &= ~(1<<29); /* set it low */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * clock_pci_eeprom
+ ******************************************************************************/
+
+static void clock_pci_eeprom(void)
+{
+	unsigned long reg;
+	/* clock is low, data is valid */
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	udelay(1);
+	/* set clck high */
+	reg|=(1<<24);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+	reg &= ~(1<<24); /* set clock low */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * send_pci_eeprom_cmd
+ ******************************************************************************/
+static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
+{
+	unsigned long reg;
+	int i;
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	/* Clear all EEPROM bits */
+	reg &= ~(0xF << 24);
+	/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+	/* Enable EEPROM Chip Select */
+	reg |= (1 << 25);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	/* Send EEPROM command - one bit at a time */
+	for (i = (int)(len-1); i >= 0; i--) {
+		/* Check if current bit is 0 or 1 */
+		if (cmd & (1 << i))
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+		else
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+		clock_pci_eeprom();
+	}
+}
+
+/******************************************************************************
+ * write_pci_eeprom_offs
+ ******************************************************************************/
+static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
+{
+	unsigned long reg;
+	int bitpos, cmdshft, cmdlen, timeout;
+	/* we're using the Eeprom 93CS66 */
+	cmdshft  = 2;
+	cmdlen = EE66_CMD_LEN;
+	/* Send Write_Enable command to EEPROM */
+	send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
+	/* Send EEPROM Write command and offset to EEPROM */
+	send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	/* Clear all EEPROM bits */
+	reg &= ~(0xF << 24);
+	/* Make sure EEDO Input is disabled for some PLX chips */
+	reg &= ~(1 << 31);
+	/* Enable EEPROM Chip Select */
+	reg |= (1 << 25);
+	/* Write 16-bit value to EEPROM - one bit at a time */
+	for (bitpos = 15; bitpos >= 0; bitpos--) {
+		/* Get bit value and shift into result */
+		if (value & (1 << bitpos))
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+		else
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
+		clock_pci_eeprom();
+	} /* for */
+	/* Deselect Chip */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
+	/* Re-select Chip */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
+	/* A small delay is needed to let EEPROM complete */
+	timeout = 0;
+	do {
+		udelay(10);
+		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+		timeout++;
+	} while (((reg & (1 << 27)) == 0) && timeout < 20000);
+	/* Send Write_Disable command to EEPROM */
+	send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
+	/* Clear Chip Select and all other EEPROM bits */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * read_pci_eeprom_offs
+ ******************************************************************************/
+static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
+{
+	unsigned long reg;
+	int bitpos, cmdshft, cmdlen;
+	/* we're using the Eeprom 93CS66 */
+	cmdshft  = 2;
+	cmdlen = EE66_CMD_LEN;
+	/* Send EEPROM read command and offset to EEPROM */
+	send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
+	/* Set EEPROM write output bit */
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	/* Set EEDO Input enable */
+	reg |= (1 << 31);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
+	/* Get 16-bit value from EEPROM - one bit at a time */
+	for (bitpos = 0; bitpos < 16; bitpos++) {
+		clock_pci_eeprom();
+		udelay(10);
+		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+		/* Get bit value and shift into result */
+		if (reg & (1 << 27))
+			*pvalue = (unsigned short)((*pvalue << 1) | 1);
+		else
+			*pvalue = (unsigned short)(*pvalue << 1);
+	}
+	/* Clear EEDO Input enable */
+	reg &= ~(1 << 31);
+	/* Clear Chip Select and all other EEPROM bits */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * EEPROM read/writes
+******************************************************************************/
+
+#undef EEPROM_DBG
+static int pati_pci_eeprom_erase(void)
+{
+	int i;
+	printf("Erasing EEPROM ");
+	for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
+		write_pci_eeprom_offs(i,0xffff);
+		if((i%0x10))
+			printf(".");
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+static int pati_pci_eeprom_prg(void)
+{
+	int i;
+	i=0;
+	printf("Programming EEPROM ");
+	while(pati_eeprom[i].offset<0xffff) {
+		write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
+		#ifdef EEPROM_DBG
+		printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
+		#else
+		if((i%0x10))
+			printf(".");
+		#endif
+		i++;
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
+{
+	int i;
+	unsigned short value;
+	unsigned short *buffer =(unsigned short *)addr;
+	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+		size = PATI_EEPROM_LAST_OFFSET - offset;
+	}
+	printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
+	for( i = offset; i< (offset + size); i+=2) {
+		value = *buffer++;
+		write_pci_eeprom_offs(i,value);
+		#ifdef EEPROM_DBG
+		printf("0x%04X: 0x%04X\n",i, value);
+		#else
+		if((i%0x10))
+			printf(".");
+		#endif
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
+{
+	int i;
+	unsigned short value = 0;
+	unsigned short *buffer =(unsigned short *)addr;
+	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+		size = PATI_EEPROM_LAST_OFFSET - offset;
+	}
+	printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
+	for( i = offset; i< (offset + size); i+=2) {
+		read_pci_eeprom_offs(i,&value);
+		*buffer++=value;
+		#ifdef EEPROM_DBG
+		printf("0x%04X: 0x%04X\n",i, value);
+		#else
+		if((i%0x10))
+			printf(".");
+		#endif
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+/******************************************************************************
+ * PCI Bridge Registers Dump
+*******************************************************************************/
+static void display_pci_regs(void)
+{
+	printf(" PCI9056_SPACE0_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
+	printf(" PCI9056_SPACE0_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
+	printf(" PCI9056_LOCAL_DMA_ARBIT  %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
+	printf(" PCI9056_ENDIAN_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
+	printf(" PCI9056_EXP_ROM_RANGE    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
+	printf(" PCI9056_EXP_ROM_REMAP    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
+	printf(" PCI9056_SPACE0_ROM_DESC  %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
+	printf(" PCI9056_DM_RANGE         %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
+	printf(" PCI9056_DM_MEM_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
+	printf(" PCI9056_DM_IO_BASE       %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
+	printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
+	printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
+	printf(" PCI9056_SPACE1_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
+	printf(" PCI9056_SPACE1_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
+	printf(" PCI9056_SPACE1_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
+	printf(" PCI9056_DM_DAC           %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
+	printf(" PCI9056_MAILBOX0         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
+	printf(" PCI9056_MAILBOX1         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
+	printf(" PCI9056_MAILBOX2         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
+	printf(" PCI9056_MAILBOX3         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
+	printf(" PCI9056_MAILBOX4         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
+	printf(" PCI9056_MAILBOX5         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
+	printf(" PCI9056_MAILBOX6         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
+	printf(" PCI9056_MAILBOX7         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
+	printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
+	printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
+	printf(" PCI9056_INT_CTRL_STAT    %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
+	printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
+	printf(" PCI9056_PERM_VENDOR_ID   %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
+	printf(" PCI9056_REVISION_ID      %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
+	printf(" \n");
+	printf(" PCI9056_VENDOR_ID        %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
+	printf(" PCI9056_COMMAND          %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
+	printf(" PCI9056_REVISION         %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
+	printf(" PCI9056_CACHE_SIZE       %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
+	printf(" PCI9056_RTR_BASE         %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
+	printf(" PCI9056_RTR_IO_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
+	printf(" PCI9056_LOCAL_BASE0      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
+	printf(" PCI9056_LOCAL_BASE1      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
+	printf(" PCI9056_UNUSED_BASE1     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
+	printf(" PCI9056_UNUSED_BASE2     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
+	printf(" PCI9056_CIS_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
+	printf(" PCI9056_SUB_ID           %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
+	printf(" PCI9056_EXP_ROM_BASE     %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
+	printf(" PCI9056_CAP_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
+	printf(" PCI9056_INT_LINE         %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
+	printf(" PCI9056_PM_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
+	printf(" PCI9056_PM_CSR           %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
+	printf(" PCI9056_HS_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
+	printf(" PCI9056_VPD_CAP_ID       %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
+	printf(" PCI9056_VPD_DATA         %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
+}
+
+
+int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (strcmp(argv[1], "info") == 0)
+	{
+		show_pld_regs();
+		return 0;
+	}
+	if (strcmp(argv[1], "pci") == 0)
+	{
+		display_pci_regs();
+		return 0;
+	}
+	if (strcmp(argv[1], "led") == 0)
+	{
+		int led_nr,led_on;
+		led_nr = (int)simple_strtoul(argv[2], NULL, 10);
+		led_on = (int)simple_strtoul(argv[3], NULL, 10);
+		if(!led_nr)
+			user_led0(led_on);
+		else
+			user_led1(led_on);
+		return 0;
+	}
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
+	if (strcmp(argv[1], "con") == 0) {
+		pci_con_connect();
+		return 0;
+	}
+	if (strcmp(argv[1], "disc") == 0) {
+		pci_con_disc();
+		return 0;
+	}
+#endif
+	if (strcmp(argv[1], "eeprom") == 0) {
+		unsigned long addr;
+		int size, offset;
+		offset = 0;
+		size = PATI_EEPROM_LAST_OFFSET;
+		if(argc>2) {
+			if(argc>3) {
+				addr = simple_strtoul(argv[3], NULL, 16);
+				if(argc>4)
+					offset = (int) simple_strtoul(argv[4], NULL, 16);
+				if(argc>5)
+					size = (int) simple_strtoul(argv[5], NULL, 16);
+				if (strcmp(argv[2], "read") == 0) {
+					return (pati_pci_eeprom_read(offset, addr, size));
+				}
+				if (strcmp(argv[2], "write") == 0) {
+					return (pati_pci_eeprom_write(offset, addr, size));
+				}
+			}
+			if (strcmp(argv[2], "prg") == 0) {
+				return (pati_pci_eeprom_prg());
+			}
+			if (strcmp(argv[2], "era") == 0) {
+				return (pati_pci_eeprom_erase());
+			}
+			if (strcmp(argv[2], "reload") == 0) {
+				reload_pci_eeprom();
+				return 0;
+			}
+
+
+		}
+	}
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+	pati,	8,	1,	do_pati,
+	"PATI specific Cmds",
+	"info - displays board information\n"
+	"pati pci  - displays PCI registers\n"
+	"pati led <nr> <on> \n"
+	"          - switch LED <nr> <on>\n"
+	"pati flash mem [SrcAddr]\n"
+	"          - updates U-Boot with image in memory\n"
+	"pati eeprom <cmd> - PCI EEPROM sub-system\n"
+	"    read <addr> <offset> <size>\n"
+	"          - read PCI EEPROM to <addr> from <offset> <size> words\n"
+	"    write <addr> <offset> <size>\n"
+	"          - write PCI EEPROM from <addr> to <offset> <size> words\n"
+	"    prg   - programm PCI EEPROM with default values\n"
+	"    era   - erase PCI EEPROM (write all word to 0xffff)\n"
+	"    reload- Reload PCI Bridge with EEPROM Values\n"
+	"    NOTE: <addr> must start on word boundary\n"
+	"          <offset> and <size> must be even byte values"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/mpl/pati/pati.c b/u-boot/board/mpl/pati/pati.c
new file mode 100644
index 0000000..7f1164a
--- /dev/null
+++ b/u-boot/board/mpl/pati/pati.c
@@ -0,0 +1,616 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ * Atapted for PATI
+ * Denis Peter, d.peter@mpl.ch
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/***********************************************************************************
+ * Bits for the SDRAM controller
+ * -----------------------------
+ *
+ * CAL:	CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
+ *	the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
+ *	controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
+ * RCD:	RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
+ *	tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
+ * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
+ *	If set to 1 tWR must be equal or less 50ns.
+ * RP:	Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
+ *	25ns. If set to 1 tRP must be equal or less 50ns.
+ * RC:	Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
+ *	or less 75ns. If set to 1 tRC must be equal or less 100ns.
+ * LMR:	Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
+ *	is the Load Mode Register Command.
+ * IIP:	Init in progress. Set to 1 for starting the init sequence
+ *	(Precharge All). As long this bit is set, the Precharge All is still in progress.
+ *	After command has completed, wait at least for 8 refresh (200usec) before proceed.
+ **********************************************************************************/
+
+#include <common.h>
+#include <mpc5xx.h>
+#include <stdio_dev.h>
+#include <pci_ids.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+#  define SYM_CHAR "_"
+#else /* No leading character on symbols */
+#  define SYM_CHAR
+#endif
+
+#undef SDRAM_DEBUG
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+		asm (".globl " GEN_SYMNAME(name)); \
+		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+
+/************************************************************************
+ * Early debug routines
+ */
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+#if defined(SDRAM_DEBUG)
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+unsigned long in32(unsigned long addr)
+{
+	unsigned long *p=(unsigned long *)addr;
+	return *p;
+}
+
+void out32(unsigned long addr,unsigned long data)
+{
+	unsigned long *p=(unsigned long *)addr;
+	*p=data;
+}
+
+typedef struct {
+	unsigned short boardtype; /* Board revision and Population Options */
+	unsigned char cal;		/* cas Latency  0:CAL=2 1:CAL=3 */
+	unsigned char rcd;		/* ras to cas delay  0:<25ns 1:<50ns*/
+	unsigned char wrec;		/* write recovery 0:<25ns 1:<50ns */
+	unsigned char pr;		/* Precharge Command Time 0:<25ns 1:<50ns */
+	unsigned char rc;		/* Auto Refresh to Active Time 0:<75ns 1:<100ns */
+	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+} sdram_t;
+
+const sdram_t sdram_table[] = {
+	{ 0x0000,	/* PATI Rev A, 16MByte -1 Board */
+		1,	/* Case Latenty = 3 */
+		0,	/* ras to cas delay  0 (20ns) */
+		0,	/* write recovery 0:<25ns 1:<50ns*/
+		0,	/* Precharge Command Time 0 (20ns) */
+		0,	/* Auto Refresh to Active Time 0 (68) */
+		2	/* log binary => Size 2 = 16MByte, 1=8 */
+	},
+	{ 0xffff, /* terminator */
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff }
+};
+
+
+extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
+
+/*
+ * Get RAM size.
+ */
+phys_size_t initdram(int board_type)
+{
+	unsigned char board_rev;
+	unsigned long reg;
+	unsigned long lmr;
+	int i,timeout;
+
+#if defined(SDRAM_DEBUG)
+	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+	puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
+	puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
+	puts("\nSDRAM  part  0x"); write_4hex(SDRAM_PART(reg));
+	puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	puts("\nBoard rev.   0x"); write_4hex(SYSCNTR_BREV(reg));
+   putc('\n');
+#endif
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	board_rev=(unsigned char)(SYSCNTR_BREV(reg));
+	i=0;
+	while(1) {
+		if(sdram_table[i].boardtype==0xffff) {
+			puts("ERROR, found no table for Board 0x");
+			write_hex(board_rev);
+			while(1);
+		}
+		if(sdram_table[i].boardtype==(unsigned char)board_rev)
+			break;
+		i++;
+	}
+	/* Set CAL, RCD, WREQ, PR and RC Bits */
+#if defined(SDRAM_DEBUG)
+	puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
+#endif
+	/* mask bits */
+	reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
+				SET_REG_BIT(1,SDRAM_PR)  |  SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR)  |
+				SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
+	/* set bits */
+	reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
+			  SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
+			  SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
+			  SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
+			  SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
+
+	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+	/* step 2 set IIP */
+#if defined(SDRAM_DEBUG)
+	puts("step 2 set IIP\n");
+#endif
+	/* step 2 set IIP */
+	reg |= SET_REG_BIT(1,SDRAM_IIP);
+	timeout=0;
+	while (timeout!=0xffff) {
+		__asm__ volatile("eieio");
+		reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+		if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
+			break;
+		timeout++;
+		udelay(1);
+	}
+	/* wait for at least 8 refresh */
+	udelay(1000);
+	/* set LMR */
+	reg |= SET_REG_BIT(1,SDRAM_LMR);
+	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+	__asm__ volatile("eieio");
+	lmr=0x00000002; /* sequential burst 4 data */
+	if(sdram_table[i].cal==1)
+		lmr|=0x00000030; /* cal = 3 */
+	else
+		lmr|=0000000020; /* cal = 2 */
+	/* rest standard operation programmed write burst length */
+	/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
+	lmr<<=2;
+	in32(CONFIG_SYS_SDRAM_BASE + lmr);
+	/* ok, we're done, return SDRAM size */
+	return ((0x400000 << sdram_table[i].sz));		/* log2 value of 4MByte  */
+}
+
+
+void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
+{
+	unsigned long reg;
+	reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
+	reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
+			   SET_REG_BIT(1,SYSCNTR_FL_VPP) |
+				SET_REG_BIT(1,SYSCNTR_FL_WP));
+
+	reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
+			   SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
+				SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
+	out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
+	udelay(100);
+}
+
+
+void show_pld_regs(void)
+{
+	unsigned long reg,reg1;
+	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+	printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
+	printf("SDRAM  part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	printf("Board rev.  %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
+	printf("Waitstates  %ld\n",GET_SYSCNTR_FLWAIT(reg));
+	printf("SDRAM:      CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n            RC=%ld  LMR=%ld IIP=%ld\n",
+		GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
+		GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
+		GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
+		GET_REG_BIT(reg,SDRAM_IIP));
+	reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
+	reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
+	printf("HW Config:  FLAG=%ld IP=%ld  index=%ld PRPM=%ld\n            ICW=%ld  ISB=%ld BDIS=%ld  PCIM=%ld\n",
+		GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
+		GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
+		GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
+		GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
+	printf("Switches:   MUX=%ld PCI_DIS=%ld Boot_EN=%ld  Config=%ld\n",GET_SDRAM_MUX(reg),
+		GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
+		GET_SYSCNTR_CFG(reg1));
+	printf("Misc:       RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
+		GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
+		GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
+}
+
+
+/****************************************************************
+ * Setting IOs
+ * -----------
+ * GPIO6 is User LED1
+ * GPIO7 is Interrupt PLX (Output)
+ * GPIO5 is User LED0
+ * GPIO2 is PLX USERi (Output)
+ * GPIO1 is PLX Interrupt (Input)
+ ****************************************************************/
+ void init_ios(void)
+ {
+	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+	unsigned long reg;
+	reg=sysconf->sc_sgpiocr; /* Data direction register */
+	reg &= ~0x67000000;
+	reg |= 0x27000000; /* set outpupts */
+	sysconf->sc_sgpiocr=reg; /* Data direction register */
+	reg=sysconf->sc_sgpiodt2; /* Data register */
+	/* set output to 0 */
+	reg &= ~0x27000000;
+	/* set IRQ and USERi to 1 */
+	reg |= 0x28000000;
+	sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led0(int led_on)
+{
+	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+	unsigned long reg;
+	reg=sysconf->sc_sgpiodt2; /* Data register */
+	if(led_on)	/* set output to 1 */
+		reg |= 0x04000000;
+	else
+		reg &= ~0x04000000;
+	sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led1(int led_on)
+{
+	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+	unsigned long reg;
+	reg=sysconf->sc_sgpiodt2; /* Data register */
+	if(led_on)	/* set output to 1 */
+		reg |= 0x02000000;
+	else
+		reg &= ~0x02000000;
+	sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+
+/****************************************************************
+ * Last Stage Init
+ ****************************************************************/
+int last_stage_init (void)
+{
+	init_ios();
+	return 0;
+}
+
+/****************************************************************
+ * Check the board
+ ****************************************************************/
+
+#define BOARD_NAME	"PATI"
+
+int checkboard (void)
+{
+	char s[50];
+	ulong reg;
+	char rev;
+	int i;
+
+	puts ("\nBoard: ");
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	rev=(char)(SYSCNTR_BREV(reg)+'A');
+	i = getenv_f("serial#", s, 32);
+	if ((i == -1)) {
+		puts ("### No HW ID - assuming " BOARD_NAME);
+		printf(" Rev. %c\n",rev);
+	}
+	else {
+		s[sizeof(BOARD_NAME)-1] = 0;
+		printf ("%s-1 Rev %c SN: %s\n", s,rev,
+				&s[sizeof(BOARD_NAME)]);
+	}
+	set_flash_vpp(1,0,0); /* set Flash VPP */
+	return 0;
+}
+
+
+#ifdef CONFIG_SYS_PCI_CON_DEVICE
+/************************************************************************
+ * PCI Communication
+ *
+ * Alive (Pinging):
+ * ----------------
+ * PCI Host sends message ALIVE, Local acknowledges with ALIVE
+ *
+ * PCI_CON console over PCI:
+ * -------------------------
+ * Local side:
+ *     - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
+ *       data is avaible (PCIMSG_CONN)
+ *     - uses PCI9056_MAILBOX1 to send data
+ *     - uses PCI9056_MAILBOX0 to receive data
+ * PCI side:
+ *     - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
+ *       data is avaible (PCIMSG_CONN)
+ *     - uses PCI9056_MAILBOX0 to send data
+ *     - uses PCI9056_MAILBOX1 to receive data
+ *
+ * How it works:
+ *     Send:
+ *     - check if PCICON_TRANSMIT_REG is empty
+ *     - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
+ *     - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
+ *       is waiting
+ *     Receive:
+ *     - get an interrupt via the PCICON_ACK_REG register message
+ *       PCIMSG_CONN
+ *     - write the data from the PCICON_RECEIVE_REG into the receive
+ *       buffer and if the receive buffer is not full, clear the
+ *       PCICON_RECEIVE_REG (this allows the counterpart to write more data)
+ *     - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
+ *
+ *     The PCICON_RECEIVE_REG must be cleared by the routine which reads
+ *     the receive buffer if the buffer is not full any more
+ *
+ */
+
+#undef PCI_CON_DEBUG
+
+#ifdef	PCI_CON_DEBUG
+#define	PCI_CON_PRINTF(fmt,args...)	serial_printf (fmt ,##args)
+#else
+#define PCI_CON_PRINTF(fmt,args...)
+#endif
+
+
+/*********************************************************
+ * we work only with a receive buffer on eiter side.
+ * Transmit buffer is free, if mailbox is cleared.
+ * Transmit character is or'ed with 0x80000000
+ * PATI receive register MAILBOX0
+ * PATI transmit register MAILBOX1
+ *********************************************************/
+#define PCICON_RECEIVE_REG	PCI9056_MAILBOX0
+#define PCICON_TRANSMIT_REG	PCI9056_MAILBOX1
+#define PCICON_DBELL_REG	PCI9056_LOC_TO_PCI_DBELL
+#define PCICON_ACK_REG		PCI9056_PCI_TO_LOC_DBELL
+
+
+#define PCIMSG_ALIVE		0x1
+#define PCIMSG_CONN		0x2
+#define PCIMSG_DISC		0x3
+#define PCIMSG_CON_DATA	0x5
+
+
+#define PCICON_GET_REG(x)	(in32(x + PCI_CONFIG_BASE))
+#define PCICON_SET_REG(x,y)	(out32(x + PCI_CONFIG_BASE,y))
+#define PCICON_TX_FLAG		0x80000000
+
+
+#define REC_BUFFER_SIZE	0x100
+int recbuf[REC_BUFFER_SIZE];
+static int r_ptr = 0;
+int w_ptr;
+struct stdio_dev pci_con_dev;
+int conn=0;
+int buff_full=0;
+
+void pci_con_put_it(const char c)
+{
+	/* Test for completition */
+	unsigned long reg;
+	do {
+		reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
+	}while(reg);
+	reg=PCICON_TX_FLAG + c;
+	PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
+	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
+}
+
+void pci_con_putc(const char c)
+{
+	pci_con_put_it(c);
+	if(c == '\n')
+		pci_con_put_it('\r');
+}
+
+
+int pci_con_getc(void)
+{
+	int res;
+	int diff;
+	while(r_ptr==(volatile int)w_ptr);
+	res=recbuf[r_ptr++];
+	if(r_ptr==REC_BUFFER_SIZE)
+		r_ptr=0;
+	if(w_ptr<r_ptr)
+		diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+	else
+		diff=r_ptr-w_ptr;
+	if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
+		/* clear Mail box */
+			buff_full=0;
+			PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+	}
+	return res;
+}
+
+int pci_con_tstc(void)
+{
+	if(r_ptr==(volatile int)w_ptr)
+		return 0;
+	return 1;
+}
+
+void pci_con_puts (const char *s)
+{
+	while (*s) {
+		pci_con_putc(*s);
+		++s;
+	}
+}
+
+void pci_con_init (void)
+{
+	w_ptr = 0;
+	r_ptr = 0;
+	PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+	conn=1;
+}
+
+/*******************************************
+ * IRQ routine
+ ******************************************/
+int pci_dorbell_irq(void)
+{
+	unsigned long reg,data;
+	int diff;
+	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+	PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
+	if(reg & (1<<20) ) {
+		/* read doorbell */
+		reg=PCICON_GET_REG(PCICON_ACK_REG);
+		switch(reg) {
+			case PCIMSG_ALIVE:
+				PCI_CON_PRINTF(" Alive\n");
+				PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
+				break;
+			case PCIMSG_CONN:
+				PCI_CON_PRINTF(" Conn %d",conn);
+				w_ptr = 0;
+				r_ptr = 0;
+				buff_full=0;
+				PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+				conn=1;
+				PCI_CON_PRINTF(" ... %d\n",conn);
+				break;
+			case PCIMSG_CON_DATA:
+				data=PCICON_GET_REG(PCICON_RECEIVE_REG);
+				recbuf[w_ptr++]=(int)(data&0xff);
+				PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
+					r_ptr,w_ptr,recbuf[w_ptr-1]);
+				if(w_ptr==REC_BUFFER_SIZE)
+					w_ptr=0;
+				if(w_ptr<r_ptr)
+					diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+				else
+					diff=r_ptr-w_ptr;
+				if(diff>(REC_BUFFER_SIZE-4))
+					buff_full=1;
+				else
+					/* clear Mail box */
+					PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+				break;
+			default:
+				serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
+		}
+		/* clear IRQ */
+		PCICON_SET_REG(PCICON_ACK_REG,~0L);
+	}
+	return 0;
+}
+
+void pci_con_connect(void)
+{
+	unsigned long reg;
+	conn=0;
+	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+	/* default 0x0f010180 */
+	reg &= 0xff000000;
+	reg |= 0x00030000; /* enable local dorbell */
+	reg |= 0x00000300; /* enable PCI dorbell */
+	PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
+	irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
+	memset (&pci_con_dev, 0, sizeof (pci_con_dev));
+	strcpy (pci_con_dev.name, "pci_con");
+	pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	pci_con_dev.putc = pci_con_putc;
+	pci_con_dev.puts = pci_con_puts;
+	pci_con_dev.getc = pci_con_getc;
+	pci_con_dev.tstc = pci_con_tstc;
+	stdio_register (&pci_con_dev);
+	printf("PATI ready for PCI connection, type ctrl-c for exit\n");
+	do {
+		udelay(10);
+		if((volatile int)conn)
+			break;
+		if(ctrlc()) {
+			irq_free_handler(0x2);
+			return;
+		}
+	}while(1);
+	console_assign(stdin,"pci_con");
+	console_assign(stderr,"pci_con");
+	console_assign(stdout,"pci_con");
+}
+
+void pci_con_disc(void)
+{
+	console_assign(stdin,"serial");
+	console_assign(stderr,"serial");
+	console_assign(stdout,"serial");
+	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
+	/* reconnection */
+	irq_free_handler(0x02);
+	pci_con_connect();
+}
+#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/u-boot/board/mpl/pati/pati.h b/u-boot/board/mpl/pati/pati.h
new file mode 100644
index 0000000..86c7a41
--- /dev/null
+++ b/u-boot/board/mpl/pati/pati.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter@mpl.ch
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/************************************************************************
+ * MACROS and register definitions for PATI Registers
+ ************************************************************************/
+#ifndef __PATI_H_
+#define __PATI_H_	1
+
+#define PLD_PART_ID		0x0
+#define PLD_BOARD_TIMING	0x4
+#define PLD_CONF_REG1		0x8
+#define PLD_CONF_REG2		0xC
+#define PLD_CONF_RES		0x10
+
+#define SET_REG_BIT(y,x) (y<<(31-x))
+#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
+
+/* SDRAM Controller PLD_PART_ID */
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_PART3	9
+#define SDRAM_PART2	10
+#define SDRAM_PART1	11
+#define SDRAM_PART0	12
+#define SDRAM_ID3	13
+#define SDRAM_ID2	14
+#define SDRAM_ID1	19
+#define SDRAM_ID0	31
+
+#define SDRAM_PART(x)	(	\
+	(GET_REG_BIT(x,SDRAM_PART3)<<3) |\
+	(GET_REG_BIT(x,SDRAM_PART2)<<2) |\
+	(GET_REG_BIT(x,SDRAM_PART1)<<1) |\
+	(GET_REG_BIT(x,SDRAM_PART0)))
+
+#define SDRAM_ID(x)	(	\
+	(GET_REG_BIT(x,SDRAM_ID3)<<3) |\
+	(GET_REG_BIT(x,SDRAM_ID2)<<2) |\
+	(GET_REG_BIT(x,SDRAM_ID1)<<1) |\
+	(GET_REG_BIT(x,SDRAM_ID0)))
+
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_PART4	0
+#define SYSCNTR_PART3	1
+#define SYSCNTR_PART2	3
+#define SYSCNTR_PART1	4
+#define SYSCNTR_PART0	5
+#define SYSCNTR_ID4	16
+#define SYSCNTR_ID3	20
+#define SYSCNTR_ID2	28
+#define SYSCNTR_ID1	29
+#define SYSCNTR_ID0	30
+
+#define SYSCNTR_PART(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
+	(GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
+	(GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_PART0)))
+
+#define SYSCNTR_ID(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
+	(GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
+	(GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_ID0)))
+
+/* SDRAM Controller PLD_BOARD_TIMING */
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_CAL	9
+#define SDRAM_RCD	10
+#define SDRAM_WREQ	11
+#define SDRAM_PR	12
+#define SDRAM_RC	13
+#define SDRAM_LMR	14
+#define SDRAM_IIP	19
+#define SDRAM_RES0	31
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BREV0	0
+#define SYSCNTR_BREV1	1
+#define SYSCNTR_BREV2	3
+#define SYSCNTR_BREV3	4
+#define SYSCNTR_RES0	5
+#define SYSCNTR_RES1	16
+#define SYSCNTR_RES2	20
+#define SYSCNTR_FLWAIT2	28
+#define SYSCNTR_FLWAIT1	29
+#define SYSCNTR_FLWAIT0	30
+
+#define SYSCNTR_BREV(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
+	(GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_BREV0)))
+
+#define GET_SYSCNTR_FLWAIT(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
+
+#define SET_SYSCNTR_FLWAIT(x)	(	\
+	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
+	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
+	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
+
+/* SDRAM Controller REG 2*/
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_MUX0	9
+#define SDRAM_MUX1	10
+#define SDRAM_PDIS	11
+#define SDRAM_RES1	12
+#define SDRAM_RES2	13
+#define SDRAM_RES3	14
+#define SDRAM_RES4	19
+#define SDRAM_RIP	31
+
+#define GET_SDRAM_MUX(x)	(	\
+	(GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
+	(GET_REG_BIT(x,SDRAM_MUX0)))
+
+
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_FLAG	0
+#define SYSCNTR_IP	1
+#define SYSCNTR_BIND2	3
+#define SYSCNTR_BIND1	4
+#define SYSCNTR_BIND0	5
+#define SYSCNTR_PRM	16
+#define SYSCNTR_ICW	20
+#define SYSCNTR_ISB2	28
+#define SYSCNTR_ISB1	29
+#define SYSCNTR_ISB0	30
+
+#define GET_SYSCNTR_BOOTIND(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_BIND0)))
+
+#define SET_SYSCNTR_BOOTIND(x)	(	\
+	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
+	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
+	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
+
+#define GET_SYSCNTR_ISB(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
+	(GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
+	(GET_REG_BIT(x,SYSCNTR_ISB0)))
+
+#define SET_SYSCNTR_ISB(x)	(	\
+	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
+	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
+	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
+
+/* SDRAM Controller REG 3*/
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_RES5	9
+#define SDRAM_CFG1	10
+#define SDRAM_CFG2	11
+#define SDRAM_CFG3	12
+#define SDRAM_RES6	13
+#define SDRAM_CFG5	14
+#define SDRAM_CFG6	19
+#define SDRAM_RES7	31
+
+#define GET_SDRAM_CFG(x)	(	\
+	(GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
+	(GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
+	(GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
+	(GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
+	(GET_REG_BIT(x,SDRAM_CFG1)))
+
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BDIS	0
+#define SYSCNTR_PCIM	1
+#define SYSCNTR_CFG0	3
+#define SYSCNTR_CFG1	4
+#define SYSCNTR_CFG2	5
+#define SYSCNTR_CFG3	16
+#define SYSCNTR_BOOTEN	20
+#define SYSCNTR_CPU_VPP	28
+#define SYSCNTR_FL_VPP	29
+#define SYSCNTR_FL_WP	30
+
+#define GET_SYSCNTR_CFG(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
+	(GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
+	(GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
+	(GET_REG_BIT(x,SYSCNTR_CFG0)))
+
+
+/***************************************************************
+ * MISC Defines
+ ***************************************************************/
+
+#define PCI_VENDOR_ID_MPL	0x18E6
+#define PCI_DEVICE_ID_PATI	0x00DA
+
+#if defined(CONFIG_MIP405)
+#define PATI_FIRMWARE_START_OFFSET	0x00300000
+#define PATI_ISO_STRING  "MEV-10084-001"
+#endif
+
+#define PATI_ENDIAN_MODE	0x3E
+
+/*******************************************
+ * PATI Mapping:
+ * -------------
+ * PCI Map:
+ * -------
+ * All addreses are mapped into the memory area
+ * (IO Area on some areas may also be possible)
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr:  configurable
+ * - pci_space1_addr	  configurable
+ *
+ * Local Map:
+ * ----------
+ * Local addresses (Remap)
+ * - SDRAM      0x06000000 Size 16MByte mask 0xff000000
+ * - EPLD CFG   0x07000000 Size 512Bytes
+ * - FLASH      0x03000000 Size up to 8MByte
+ * - CPU        0x01000000 Size 4MByte (only accessable if special configured)
+ *
+ * Implemention:
+ * -------------
+ * To prevent using large resources reservation on the host following
+ * PCI mapping is choosed:
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr:  configured to the EPLD Config Area size 256Bytes
+ * - pci_space1_addr:  configured to the SDRAM Area size 1MBytes, this
+ *                     space is used to switch between SDRAM, Flash and CPU
+ *
+ */
+
+/* Attribute definitions */
+#define PATI_BUS_SIZE_8		0
+#define PATI_BUS_SIZE_16	1
+#define PATI_BUS_SIZE_32	3
+
+#define PATI_SPACE0_MASK	(0xFEFFFE00)  /* Mask Attributes */
+#define PATI_SPACE1_MASK	(0x00000000)  /* Mask Attributes */
+
+#define PATI_EXTRA_LONG_EEPROM	1
+
+#define SPACE0_TA_ENABLE (1<<6)
+#define SPACE1_TA_ENABLE (1<<6)
+
+/* Config Area */
+#define PATI_LOC_CFG_ADDR		0x07000000		/* Local Address */
+#define PATI_LOC_CFG_MASK		0xFFFFFF00		/* 256 Bytes */
+/* Attributes */
+#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_CFG_BURST		0			/* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE		1			/* Enable TA */
+
+#define PATI_LOC_CFG_SPACE0_ATTR  ( \
+		PATI_LOC_CFG_BUS_SIZE | \
+		(PATI_LOC_CFG_TA_ENABLE << 6) | \
+		(PATI_LOC_CFG_NO_PREFETCH << 8) | \
+		(PATI_LOC_CFG_BURST << 24) | \
+		(PATI_EXTRA_LONG_EEPROM << 25))
+
+/* should never be used */
+#define PATI_LOC_CFG_SPACE1_ATTR  ( \
+		PATI_LOC_CFG_BUS_SIZE | \
+		(PATI_LOC_CFG_TA_ENABLE << 6) | \
+		(PATI_LOC_CFG_NO_PREFETCH << 9) | \
+		(PATI_LOC_CFG_BURST << 8))
+
+
+/* SDRAM Area */
+#define PATI_LOC_SDRAM_ADDR		0x06000000		/* Local Address */
+#define PATI_LOC_SDRAM_MASK		0xFFF00000		/* 1MByte */
+/* Attributes */
+#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_SDRAM_BURST		0			/* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH	0			/* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE	1			/* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
+		PATI_LOC_SDRAM_BUS_SIZE | \
+		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+		(PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
+		(PATI_LOC_SDRAM_BURST << 24) | \
+		(PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_SDRAM_SPACE1_ATTR  ( \
+		PATI_LOC_SDRAM_BUS_SIZE | \
+		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+		(PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
+		(PATI_LOC_SDRAM_BURST << 8))
+
+
+/* Flash Area */
+#define PATI_LOC_FLASH_ADDR		0x03000000		/* Local Address */
+#define PATI_LOC_FLASH_MASK		0xFFF00000		/* 1MByte */
+/* Attributes */
+#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16	/* 16 Bit */
+#define PATI_LOC_FLASH_BURST		0			/* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE	1			/* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_FLASH_SPACE0_ATTR  ( \
+		PATI_LOC_FLASH_BUS_SIZE | \
+		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
+		(PATI_LOC_FLASH_NO_PREFETCH << 8) | \
+		(PATI_LOC_FLASH_BURST << 24) | \
+		(PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_FLASH_SPACE1_ATTR  ( \
+		PATI_LOC_FLASH_BUS_SIZE | \
+		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
+		(PATI_LOC_FLASH_NO_PREFETCH << 9) | \
+		(PATI_LOC_FLASH_BURST << 8))
+
+
+/* CPU Area */
+#define PATI_LOC_CPU_ADDR		0x01000000		/* Local Address */
+#define PATI_LOC_CPU_MASK		0xFFF00000		/* 1Mbyte */
+/* Attributes */
+#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_CPU_BURST		0			/* No Burst */
+#define PATI_LOC_CPU_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_CPU_TA_ENABLE		1			/* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_CPU_SPACE0_ATTR  ( \
+		PATI_LOC_CPU_BUS_SIZE | \
+		(PATI_LOC_CPU_TA_ENABLE << 6) | \
+		(PATI_LOC_CPU_NO_PREFETCH << 8) | \
+		(PATI_LOC_CPU_BURST << 24) | \
+		(PATI_EXTRA_CPU_EEPROM << 25))
+
+#define PATI_LOC_CPU_SPACE1_ATTR  ( \
+		PATI_LOC_CPU_BUS_SIZE | \
+		(PATI_LOC_CPU_TA_ENABLE << 6) | \
+		(PATI_LOC_CPU_NO_PREFETCH << 9) | \
+		(PATI_LOC_CPU_BURST << 8))
+
+/***************************************************
+ * Hardware Config word definition
+ ***************************************************/
+#define BOOT_EXT_FLASH		0x00000000
+#define BOOT_INT_FLASH		0x00000004
+#define BOOT_FROM_PCI		0x00000006
+#define BOOT_FROM_SDRAM		0x00000005
+
+#define ENABLE_INT_ARB		0x00000008
+
+#define INITIAL_IRQ_PREF	0x00000010
+
+#define INITIAL_MEM_0M		0x00000000
+#define INITIAL_MEM_4M		0x00000080
+#define INITIAL_MEM_8M		0x00000040
+#define INITIAL_MEM_12M		0x000000C0
+#define INITIAL_MEM_16M		0x00000020
+#define INITIAL_MEM_20M		0x000000A0
+#define INITIAL_MEM_24M		0x00000060
+#define INITIAL_MEM_28M		0x000000E0
+/* CONF */
+#define INTERNAL_HWCONF		0x00000100
+/* PRPM */
+#define LOCAL_CPU_SLAVE		0x00000200
+/* BDIS */
+#define DISABLE_MEM_CNTR	0x00000400
+/* PCIM */
+#define PCI_MASTER_ONLY		0x00000800
+
+
+#define PATI_HW_START		((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
+#define PATI_HW_PCI_ONLY	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_ACC		((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_SLAVE	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+
+/***************************************************
+ * Direct Master Config
+ ***************************************************/
+#define PATI_DMASTER_PCI_ADDR		0x01000000
+#define PATI_BUS_MASTER 1
+
+
+#define PATI_DMASTER_MASK		0xFFF00000  /* 1MByte */
+#define PATI_DMASTER_ADDR		0x01000000  /* Local Address */
+
+#define PATI_DMASTER_MEMORY_EN		0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD		0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD	0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_PRE_SIZE_CNTRL_0	0x00000000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_4	0x00000008
+#define PATI_DMASTER_PRE_SIZE_CNTRL_8	0x00001000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_16	0x00001008
+#define PATI_DMASTER_REL_PCI		0x00000000
+#define PATI_DMASTER_NOT_REL_PCI	0x00000010
+#define PATI_DMASTER_WR_INVAL		0x00000200
+#define PATI_DMASTER_NOT_WR_INVAL	0x00000000
+#define PATI_DMASTER_PRE_LIMIT		0x00000800
+#define PATI_DMASTER_PRE_CONT		0x00000000
+#define PATI_DMASTER_DELAY_WR_0		0x00000000
+#define PATI_DMASTER_DELAY_WR_4		0x00004000
+#define PATI_DMASTER_DELAY_WR_8		0x00008000
+#define PATI_DMASTER_DELAY_WR_16	0x0000C000
+
+#define PATI_DMASTER_PCI_ADDR_MASK	0xFFFF0000
+
+#define PATI_DMASTER_ATTR	\
+	PATI_DMASTER_MEMORY_EN | \
+	PATI_DMASTER_READ_AHEAD | \
+	PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
+	PATI_DMASTER_REL_PCI | \
+	PATI_DMASTER_NOT_WR_INVAL | \
+	PATI_DMASTER_PRE_LIMIT | \
+	PATI_DMASTER_DELAY_WR_0
+
+
+#endif /* #ifndef __PATI_H_ */
diff --git a/u-boot/board/mpl/pati/pci_eeprom.h b/u-boot/board/mpl/pati/pci_eeprom.h
new file mode 100644
index 0000000..af34b86
--- /dev/null
+++ b/u-boot/board/mpl/pati/pci_eeprom.h
@@ -0,0 +1,91 @@
+
+#ifndef __PCI_EEPROM_H_
+#define __PCI_EEPROM_H_	1
+
+#include "pati.h"
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+/**********************************************
+*               Definitions
+**********************************************/
+#define EE46_CMD_LEN    9       /* Bits in instructions */
+#define EE56_CMD_LEN    11      /* Bits in instructions */
+#define EE66_CMD_LEN    11      /* Bits in instructions */
+#define EE_READ         0x0180  /* 01 1000 0000 read instruction */
+#define EE_WRITE        0x0140  /* 01 0100 0000 write instruction */
+#define EE_WREN         0x0130  /* 01 0011 0000 write enable instruction */
+#define EE_WRALL        0x0110  /* 01 0001 0000 write all registers */
+#define EE_PRREAD       0x0180  /* 01 1000 0000 read address stored in Protect Register */
+#define EE_PRWRITE      0x0140  /* 01 0100 0000 write the address into PR */
+#define EE_WDS          0x0100  /* 01 0000 0000 write disable instruction */
+#define EE_PREN         0x0130  /* 01 0011 0000 protect enable instruction */
+#define EE_PRCLEAR      0x01FF  /* 01 1111 1111 clear protect register instr */
+#define EE_PRDS         0x0100  /* 01 0000 0000 ONE TIME ONLY, permenant */
+
+/***************************************************
+ * EEPROM
+ ***************************************************/
+#define LOW_WORD(x)	(((x) & 0xFFFF))
+#define HIGH_WORD(x)	(((x) >> 16) & 0xFFFF)
+
+typedef struct pci_eeprom_t {
+	unsigned short offset;
+	unsigned short value;
+} pci_eeprom;
+
+static pci_eeprom pati_eeprom[] = {
+	{ 0x00,PCI_DEVICE_ID_PATI },	/* PCI Device ID PCIIDR[31:16] */
+	{ 0x02,PCI_VENDOR_ID_MPL },	/* PCI Vendor ID PCIIDR[15:0] */
+	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC },	/* PCI Class Code PCICCR[23:8] */
+	{ 0x06,0x00BA },	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+	{ 0x08,0x0007 },	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+	{ 0x0A,0x0100 },	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+	{ 0x0C,0x0000 },	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+	{ 0x0E,0x0000 },	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+	{ 0x10,0x0000 },	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+	{ 0x12,0x0000 },	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) },	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) },	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) },	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 },	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+	{ 0x1C,0x0000 },	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+	{ 0x1E,0x0000 },	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+	{ 0x20,0x0030 },	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+	{ 0x22,0x0510 },	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+	{ 0x24,0x0000 },	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+	{ 0x26,0x0000 },	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
+	{ 0x28,0x0000 },	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+	{ 0x2A,0x0000 },	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) },	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) },	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) },	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) },	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) },	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) },	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+	{ 0x38,0x0000 },	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+	{ 0x3A,0x0000 },	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+	{ 0x3C,0x0000 },	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+	{ 0x3E,0x0000 },	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+	{ 0x40,0x0000 },	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+	{ 0x42,0x0000 },	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+	{ 0x44,0x0000 },	/* PCI Subsystem ID PCISID[15:0] */
+	{ 0x46,0x0000 },	/* PCI Subsystem Vendor ID PCISVID[15:0] */
+	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) },	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) },	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) },	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 },	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+	{ 0x54,0x0000 },	/* Hot Swap Control/Status (Reserved) Reserved */
+	{ 0x56,0x0000 },	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+	{ 0x58,0x0000 },	/* Reserved Reserved */
+	{ 0x5A,0x0000 },	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+	{ 0x5C,0x0000 },	/* Power Management Capabilities PMC[15:9, 2:0] */
+	{ 0x5E,0x0000 },	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+	{ 0x60,0x0000 },	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+	{ 0x62,0x0000 },	/* Power Management Control/Status PMCSR[14:8] */
+	{ 0xFFFF,0xFFFF}	/* terminaror */
+};
+#define PATI_EEPROM_LAST_OFFSET	0x64
+#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/u-boot/board/mpl/pati/plx9056.h b/u-boot/board/mpl/pati/plx9056.h
new file mode 100644
index 0000000..cd4df18
--- /dev/null
+++ b/u-boot/board/mpl/pati/plx9056.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter@mpl.ch
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* PLX9096 register definitions
+*/
+#ifndef __PLX9056_H_
+#define __PLX9056_H_	1
+
+#include <pci.h>
+
+#ifdef PLX9056_LOC
+#define LOCAL_OFFSET					0x080
+/* PCI Config regs */
+#else
+#define LOCAL_OFFSET					0x000
+#endif
+
+#define PCI9056_VENDOR_ID            PCI_VENDOR_ID
+/*#define PCI9656_DEVICE_ID            PCI_DEVICE_ID */
+#define PCI9056_COMMAND              PCI_COMMAND
+/*#define PCI9656_STATUS               PCI_STATUS */
+#define PCI9056_REVISION             PCI_REVISION_ID
+
+#define PCI9056_CACHE_SIZE           PCI_CACHE_LINE_SIZE
+#define PCI9056_RTR_BASE             PCI_BASE_ADDRESS_0
+#define PCI9056_RTR_IO_BASE          PCI_BASE_ADDRESS_1
+#define PCI9056_LOCAL_BASE0          PCI_BASE_ADDRESS_2
+#define PCI9056_LOCAL_BASE1          PCI_BASE_ADDRESS_3
+#define PCI9056_UNUSED_BASE1         PCI_BASE_ADDRESS_4
+#define PCI9056_UNUSED_BASE2         PCI_BASE_ADDRESS_5
+#define PCI9056_CIS_PTR              PCI_CARDBUS_CIS
+#define PCI9056_SUB_ID               PCI_SUBSYSTEM_VENDOR_ID
+#define PCI9056_EXP_ROM_BASE         PCI_ROM_ADDRESS
+#define PCI9056_CAP_PTR              PCI_CAPABILITY_LIST
+#define PCI9056_INT_LINE             PCI_INTERRUPT_LINE
+
+#if defined(PLX9056_LOC)
+    #define PCI9056_PM_CAP_ID            0x180
+    #define PCI9056_PM_CSR               0x184
+    #define PCI9056_HS_CAP_ID            0x188
+    #define PCI9056_VPD_CAP_ID           0x18C
+    #define PCI9056_VPD_DATA             0x190
+#endif
+
+
+#define PCI_DEVICE_ID_PLX9056		0x9056
+
+/* Local Configuration Registers Accessible via the PCI Base address + Variable */
+#define PCI9056_SPACE0_RANGE         (0x000 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_REMAP         (0x004 + LOCAL_OFFSET)
+#define PCI9056_LOCAL_DMA_ARBIT      (0x008 + LOCAL_OFFSET)
+#define PCI9056_ENDIAN_DESC          (0x00c + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_RANGE        (0x010 + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_REMAP        (0x014 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_ROM_DESC      (0x018 + LOCAL_OFFSET)
+#define PCI9056_DM_RANGE             (0x01c + LOCAL_OFFSET)
+#define PCI9056_DM_MEM_BASE          (0x020 + LOCAL_OFFSET)
+#define PCI9056_DM_IO_BASE           (0x024 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_MEM_REMAP     (0x028 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_IO_CONFIG     (0x02c + LOCAL_OFFSET)
+#define PCI9056_SPACE1_RANGE         (0x0f0 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_REMAP         (0x0f4 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_DESC          (0x0f8 + LOCAL_OFFSET)
+#define PCI9056_DM_DAC               (0x0fc + LOCAL_OFFSET)
+
+#ifdef PLX9056_LOC
+#define PCI9056_ARBITER_CTRL         0x1A0
+#define PCI9056_ABORT_ADDRESS        0x1A4
+#endif
+
+/* Runtime registers  PCI Address + LOCAL_OFFSET */
+#ifdef PLX9056_LOC
+#define PCI9056_MAILBOX0				0x0C0
+#define PCI9056_MAILBOX1				0x0C4
+#else
+#define PCI9056_MAILBOX0				0x078
+#define PCI9056_MAILBOX1				0x07c
+#endif
+
+#define PCI9056_MAILBOX2				(0x048 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX3				(0x04c + LOCAL_OFFSET)
+#define PCI9056_MAILBOX4				(0x050 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX5				(0x054 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX6				(0x058 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX7				(0x05c + LOCAL_OFFSET)
+#define PCI9056_PCI_TO_LOC_DBELL		(0x060 + LOCAL_OFFSET)
+#define PCI9056_LOC_TO_PCI_DBELL		(0x064 + LOCAL_OFFSET)
+#define PCI9056_INT_CTRL_STAT			(0x068 + LOCAL_OFFSET)
+#define PCI9056_EEPROM_CTRL_STAT		(0x06c + LOCAL_OFFSET)
+#define PCI9056_PERM_VENDOR_ID		(0x070 + LOCAL_OFFSET)
+#define PCI9056_REVISION_ID			(0x074 + LOCAL_OFFSET)
+
+#endif /* #ifndef __PLX9056_H_ */
diff --git a/u-boot/board/mpl/pip405/Makefile b/u-boot/board/mpl/pip405/Makefile
new file mode 100644
index 0000000..8b4bbc5
--- /dev/null
+++ b/u-boot/board/mpl/pip405/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o \
+	  ../common/flash.o cmd_pip405.o ../common/pci.o \
+	  ../common/isa.o ../common/kbd.o \
+	  ../common/usb_uhci.o \
+	  ../common/common_util.o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mpl/pip405/cmd_pip405.c b/u-boot/board/mpl/pip405/cmd_pip405.c
new file mode 100644
index 0000000..554c8d1
--- /dev/null
+++ b/u-boot/board/mpl/pip405/cmd_pip405.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for PIP405
+ */
+
+#include <common.h>
+#include <command.h>
+#include "pip405.h"
+#include "../common/common_util.h"
+
+
+extern void print_pip405_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+
+	ulong led_on,led_nr;
+
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_pip405_info();
+		return 0;
+	}
+	if (strcmp(argv[1], "led") == 0)
+	{
+		led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
+		led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
+		if(!led_nr)
+			user_led0(led_on);
+		else
+			user_led1(led_on);
+		return 0;
+	}
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+U_BOOT_CMD(
+	pip405,	6,	1,	do_pip405,
+	"PIP405 specific Cmds",
+	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+	"pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
+	"pip405 flash mps - updates U-Boot with image from MPS"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/mpl/pip405/init.S b/u-boot/board/mpl/pip405/init.S
new file mode 100644
index 0000000..b77517f
--- /dev/null
+++ b/u-boot/board/mpl/pip405/init.S
@@ -0,0 +1,218 @@
+/*------------------------------------------------------------------------------+
+ *      This source code is dual-licensed.  You may use it under the terms of
+ *      the GNU General Public License version 2, or under the license below.
+ *
+ *      This source code has been made available to you by IBM on an AS-IS
+ *      basis.  Anyone receiving this source is licensed under IBM
+ *      copyrights to use it in any way he or she deems fit, including
+ *      copying it, modifying it, compiling it, and redistributing it either
+ *      with or without modifications.  No license under IBM patents or
+ *      patent applications is to be implied by the copyright license.
+ *
+ *      Any user of this software should understand that IBM cannot provide
+ *      technical support for this software and will not be responsible for
+ *      any consequences resulting from the use of this software.
+ *
+ *      Any person who transfers this source code or any derivative work
+ *      must include the IBM copyright notice, this paragraph, and the
+ *      preceding two paragraphs in the transferred software.
+ *
+ *      COPYRIGHT   I B M   CORPORATION 1995
+ *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-------------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Function:     ext_bus_cntlr_init
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *	Bank 0 - Flash or Multi Purpose Socket
+ *	Bank 1 - Multi Purpose Socket or Flash
+ *	Bank 2 - not used
+ *	Bank 3 - not used
+ *	Bank 4 - not used
+ *	Bank 5 - not used
+ *	Bank 6 - used to switch on the 12V for the Multipurpose socket
+ *	Bank 7 - Config Register
+ *-----------------------------------------------------------------------------*/
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <configs/PIP405.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+#include "pip405.h"
+
+  .globl ext_bus_cntlr_init
+ ext_bus_cntlr_init:
+  mflr   r4                      /* save link register */
+  mfdcr  r3,CPC0_PSR                /* get strapping reg */
+  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
+  bnelr                          /* jump back if PCI boot */
+
+  bl      ..getAddr
+..getAddr:
+  mflr    r3                      /* get address of ..getAddr */
+  mtlr    r4                      /* restore link register */
+  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
+  mtctr   r4                      /* 14 cache lines to fit this function */
+				   /* in cache (gives us 8x14=112 instrctns) */
+..ebcloop:
+  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+  addi    r3,r3,32								/* move to next cache line */
+  bdnz    ..ebcloop               /* continue for 14 cache lines */
+
+   /*-------------------------------------------------------------------
+    * Delay to ensure all accesses to ROM are complete before changing
+    * bank 0 timings.
+    *------------------------------------------------------------------- */
+	addis	r3,0,0x0
+  ori     r3,r3,0xA000
+  mtctr   r3
+..spinlp:
+  bdnz    ..spinlp                /* spin loop */
+
+	/*-----------------------------------------------------------------------
+	 * decide boot up mode
+	 *----------------------------------------------------------------------- */
+	addi		r4,0,PB0CR
+	mtdcr		EBC0_CFGADDR,r4
+	mfdcr		r4,EBC0_CFGDATA
+
+	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
+	beq		0f				/* jump if 8 bit bus width */
+
+	/* setup 16 bit things
+   *-----------------------------------------------------------------------
+   * Memory Bank 0 (16 Bit Flash) initialization
+   *---------------------------------------------------------------------- */
+
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,(FLASH_AP_B)@h
+	ori     r4,r4,(FLASH_AP_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(FLASH_CR_B)@h
+	ori     r4,r4,(FLASH_CR_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+	b				1f
+
+0:
+	/* 8Bit boot mode: */
+	/*-----------------------------------------------------------------------
+	* Memory Bank 0 Multi Purpose Socket initialization
+	*----------------------------------------------------------------------- */
+	/* 0x7F8FFE80 slowest boot */
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
+	addis   r4,0,(MPS_AP_B)@h
+	ori     r4,r4,(MPS_AP_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(MPS_CR_B)@h
+	ori     r4,r4,(MPS_CR_B)@l
+	mtdcr   EBC0_CFGDATA,r4
+
+
+1:
+  /*-----------------------------------------------------------------------
+   * Memory Bank 2-3-4-5-6 (not used) initialization
+   *-----------------------------------------------------------------------*/
+  addi    r4,0,PB1CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB2CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB3CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB4CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB5CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB6CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+
+  addi    r4,0,PB7CR
+  mtdcr   EBC0_CFGADDR,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   EBC0_CFGDATA,r4
+  nop				/* pass2 DCR errata #8 */
+  blr
+
+#if defined(CONFIG_BOOT_PCI)
+    .section .bootpg,"ax"
+    .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+  /* first handle errata #68 / PCI_18 */
+  iccci   r0, r0          /* invalidate I-cache */
+  lis     r31, 0
+  mticcr  r31             /* ICCR = 0 (all uncachable) */
+  isync
+
+  mfccr0  r28             /* set CCR0[24] = 1 */
+  ori     r28, r28, 0x0080
+  mtccr0  r28
+
+  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+  lis     r28, 0xEF40
+  addi    r28, r28, 0x0004
+  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
+  lis     r29, 0xFFF8     /* open 512 kByte */
+  addi    r29, r29, 0x0001/* and enable this region */
+  stwbrx  r29, r0, r28    /* write PMM0MA */
+
+  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
+  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
+
+  lis     r31, 0x8000     /* set en bit bus 0 */
+  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+  stwbrx  r31, r0, r28    /* write it */
+
+  lwbrx   r31, r0, r29    /* load XBCS register */
+  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+  stwbrx  r31, r0, r29    /* write back XBCS register */
+
+  nop
+  nop
+  b	_start		/* normal start */
+#endif
diff --git a/u-boot/board/mpl/pip405/pip405.c b/u-boot/board/mpl/pip405/pip405.c
new file mode 100644
index 0000000..7b48c06
--- /dev/null
+++ b/u-boot/board/mpl/pip405/pip405.c
@@ -0,0 +1,955 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include "pip405.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <stdio_dev.h>
+#include "../common/isa.h"
+#include "../common/common_util.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SDRAM_DEBUG
+
+#define FALSE           0
+#define TRUE            1
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+	long int quot;		/* Quotient */
+	long int rem;		/* Remainder    */
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+
+# define __ldiv_t_defined	1
+#endif
+
+
+typedef enum {
+	SDRAM_NO_ERR,
+	SDRAM_SPD_COMM_ERR,
+	SDRAM_SPD_CHKSUM_ERR,
+	SDRAM_UNSUPPORTED_ERR,
+	SDRAM_UNKNOWN_ERR
+} SDRAM_ERR;
+
+typedef struct {
+	const unsigned char mode;
+	const unsigned char row;
+	const unsigned char col;
+	const unsigned char bank;
+} SDRAM_SETUP;
+
+static const SDRAM_SETUP sdram_setup_table[] = {
+	{1, 11, 9, 2},
+	{1, 11, 10, 2},
+	{2, 12, 9, 4},
+	{2, 12, 10, 4},
+	{3, 13, 9, 4},
+	{3, 13, 10, 4},
+	{3, 13, 11, 4},
+	{4, 12, 8, 2},
+	{4, 12, 8, 4},
+	{5, 11, 8, 2},
+	{5, 11, 8, 4},
+	{6, 13, 8, 2},
+	{6, 13, 8, 4},
+	{7, 13, 9, 2},
+	{7, 13, 10, 2},
+	{0, 0, 0, 0}
+};
+
+static const unsigned char cal_indextable[] = {
+	9, 23, 25
+};
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns.ns/4 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+	unsigned short ns, ns4;
+
+	/* isolate upper 6 bits */
+	ns = (spd_byte >> 2) & 0x3F;
+	/* isloate lower 2 bits */
+	ns4 = (spd_byte & 0x03);
+
+	return (ns * 100 + ns4 * 25);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+#endif
+	serial_puts ("\n");
+	serial_puts (s);
+	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+	for (;;);
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+int board_early_init_f (void)
+{
+	unsigned char dataout[1];
+	unsigned char datain[128];
+	unsigned long sdram_size = 0;
+	SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
+	unsigned long memclk;
+	unsigned long tmemclk = 0;
+	unsigned long tmp, bank, baseaddr, bank_size;
+	unsigned short i;
+	unsigned char rows, cols, banks, sdram_banks, density;
+	unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
+			trc_clocks, tctp_clocks;
+	unsigned char cal_index, cal_val, spd_version, spd_chksum;
+	unsigned char buf[8];
+	/* set up the config port */
+	mtdcr (EBC0_CFGADDR, PB7AP);
+	mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
+	mtdcr (EBC0_CFGADDR, PB7CR);
+	mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
+
+	memclk = get_bus_freq (tmemclk);
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+#ifdef SDRAM_DEBUG
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+	serial_puts ("\nstart SDRAM Setup\n");
+#endif
+
+	/* Read Serial Presence Detect Information */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	dataout[0] = 0;
+	for (i = 0; i < 128; i++)
+		datain[i] = 127;
+	i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
+#ifdef SDRAM_DEBUG
+	serial_puts ("\ni2c_read returns ");
+	write_hex (i);
+	serial_puts ("\n");
+#endif
+
+#ifdef SDRAM_DEBUG
+	for (i = 0; i < 128; i++) {
+		write_hex (datain[i]);
+		serial_puts (" ");
+		if (((i + 1) % 16) == 0)
+			serial_puts ("\n");
+	}
+	serial_puts ("\n");
+#endif
+	spd_chksum = 0;
+	for (i = 0; i < 63; i++) {
+		spd_chksum += datain[i];
+	}							/* endfor */
+	if (datain[63] != spd_chksum) {
+#ifdef SDRAM_DEBUG
+		serial_puts ("SPD chksum: 0x");
+		write_hex (datain[63]);
+		serial_puts (" != calc. chksum: 0x");
+		write_hex (spd_chksum);
+		serial_puts ("\n");
+#endif
+		SDRAM_err ("SPD checksum Error");
+	}
+	/* SPD seems to be ok, use it */
+
+	/* get SPD version */
+	spd_version = datain[62];
+
+	/* do some sanity checks on the kind of RAM */
+	if ((datain[0] < 0x80) ||	/* less than 128 valid bytes in SPD */
+		(datain[2] != 0x04) ||	/* if not SDRAM */
+		(!((datain[6] == 0x40) || (datain[6] == 0x48))) ||	/* or not (64 Bit or 72 Bit)  */
+		(datain[7] != 0x00) || (datain[8] != 0x01) ||	/* or not LVTTL signal levels */
+		(datain[126] == 0x66))	/* or a 66MHz modules */
+		SDRAM_err ("unsupported SDRAM");
+#ifdef SDRAM_DEBUG
+	serial_puts ("SDRAM sanity ok\n");
+#endif
+
+	/* get number of rows/cols/banks out of byte 3+4+5 */
+	rows = datain[3];
+	cols = datain[4];
+	banks = datain[5];
+
+	/* get number of SDRAM banks out of byte 17 and
+	   supported CAS latencies out of byte 18 */
+	sdram_banks = datain[17];
+	supported_cal = datain[18] & ~0x81;
+
+	while (t->mode != 0) {
+		if ((t->row == rows) && (t->col == cols)
+			&& (t->bank == sdram_banks))
+			break;
+		t++;
+	}							/* endwhile */
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("rows: ");
+	write_hex (rows);
+	serial_puts (" cols: ");
+	write_hex (cols);
+	serial_puts (" banks: ");
+	write_hex (banks);
+	serial_puts (" mode: ");
+	write_hex (t->mode);
+	serial_puts ("\n");
+#endif
+	if (t->mode == 0)
+		SDRAM_err ("unsupported SDRAM");
+	/* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
+#ifdef SDRAM_DEBUG
+	serial_puts ("tRP: ");
+	write_hex (datain[27]);
+	serial_puts ("\ntRCD: ");
+	write_hex (datain[29]);
+	serial_puts ("\ntRAS: ");
+	write_hex (datain[30]);
+	serial_puts ("\n");
+#endif
+
+	trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
+	tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
+	density = datain[31];
+
+	/* trc_clocks is sum of trp_clocks + tras_clocks */
+	trc_clocks = trp_clocks + tras_clocks;
+	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+	tctp_clocks =
+			((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
+			 (tmemclk - 1)) / tmemclk;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("c_RP: ");
+	write_hex (trp_clocks);
+	serial_puts ("\nc_RCD: ");
+	write_hex (trcd_clocks);
+	serial_puts ("\nc_RAS: ");
+	write_hex (tras_clocks);
+	serial_puts ("\nc_RC: (RP+RAS): ");
+	write_hex (trc_clocks);
+	serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
+	write_hex (tctp_clocks);
+	serial_puts ("\nt_CTP: RAS - RCD: ");
+	write_hex ((unsigned
+				char) ((NSto10PS (datain[30]) -
+						NSto10PS (datain[29])) >> 8));
+	write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
+	serial_puts ("\ntmemclk: ");
+	write_hex ((unsigned char) (tmemclk >> 8));
+	write_hex ((unsigned char) (tmemclk));
+	serial_puts ("\n");
+#endif
+
+
+	cal_val = 255;
+	for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
+		/* is this CAS latency supported ? */
+		if ((supported_cal >> i) & 0x01) {
+			buf[0] = datain[cal_indextable[cal_index]];
+			if (cal_index < 2) {
+				if (NS10to10PS (buf[0], spd_version) <= tmemclk)
+					cal_val = i;
+			} else {
+				/* SPD bytes 25+26 have another format */
+				if (NS4to10PS (buf[0], spd_version) <= tmemclk)
+					cal_val = i;
+			}	/* endif */
+			cal_index++;
+		}	/* endif */
+	}	/* endfor */
+#ifdef SDRAM_DEBUG
+	serial_puts ("CAL: ");
+	write_hex (cal_val + 1);
+	serial_puts ("\n");
+#endif
+
+	if (cal_val == 255)
+		SDRAM_err ("unsupported SDRAM");
+
+	/* get SDRAM timing register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
+	/* insert CASL value */
+/*  tmp |= ((unsigned long)cal_val) << 23; */
+	tmp |= ((unsigned long) cal_val) << 23;
+	/* insert PTA value */
+	tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
+	/* insert CTP value */
+/*  tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
+	tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
+	/* insert LDF (always 01) */
+	tmp |= ((unsigned long) 0x01) << 14;
+	/* insert RFTA value */
+	tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
+	/* insert RCD value */
+	tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("sdtr: ");
+	write_4hex (tmp);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM timing register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	mtdcr (SDRAM0_CFGDATA, tmp);
+	baseaddr = CONFIG_SYS_SDRAM_BASE;
+	bank_size = (((unsigned long) density) << 22) / 2;
+	/* insert AM value */
+	tmp = ((unsigned long) t->mode - 1) << 13;
+	/* insert SZ value; */
+	switch (bank_size) {
+	case 0x00400000:
+		tmp |= ((unsigned long) 0x00) << 17;
+		break;
+	case 0x00800000:
+		tmp |= ((unsigned long) 0x01) << 17;
+		break;
+	case 0x01000000:
+		tmp |= ((unsigned long) 0x02) << 17;
+		break;
+	case 0x02000000:
+		tmp |= ((unsigned long) 0x03) << 17;
+		break;
+	case 0x04000000:
+		tmp |= ((unsigned long) 0x04) << 17;
+		break;
+	case 0x08000000:
+		tmp |= ((unsigned long) 0x05) << 17;
+		break;
+	case 0x10000000:
+		tmp |= ((unsigned long) 0x06) << 17;
+		break;
+	default:
+		SDRAM_err ("unsupported SDRAM");
+	}	/* endswitch */
+	/* get SDRAM bank 0 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+	bank |= (baseaddr | tmp | 0x01);
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank0: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+	serial_puts (" mb0cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+	baseaddr += bank_size;
+	sdram_size += bank_size;
+
+	/* write SDRAM bank 0 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	mtdcr (SDRAM0_CFGDATA, bank);
+
+	/* get SDRAM bank 1 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+	sdram_size = 0;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank1: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+#endif
+	if (banks == 2) {
+		bank |= (baseaddr | tmp | 0x01);
+		baseaddr += bank_size;
+		sdram_size += bank_size;
+	}	/* endif */
+#ifdef SDRAM_DEBUG
+	serial_puts (" mb1cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+	/* write SDRAM bank 1 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	mtdcr (SDRAM0_CFGDATA, bank);
+
+	/* get SDRAM bank 2 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+
+	bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank2: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+	serial_puts (" mb2cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+
+	baseaddr += bank_size;
+	sdram_size += bank_size;
+
+	/* write SDRAM bank 2 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	mtdcr (SDRAM0_CFGDATA, bank);
+
+	/* get SDRAM bank 3 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank3: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+#endif
+
+	if (banks == 2) {
+		bank |= (baseaddr | tmp | 0x01);
+		baseaddr += bank_size;
+		sdram_size += bank_size;
+	}
+	/* endif */
+#ifdef SDRAM_DEBUG
+	serial_puts (" mb3cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM bank 3 register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	mtdcr (SDRAM0_CFGDATA, bank);
+
+
+	/* get SDRAM refresh interval register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
+
+	if (tmemclk < NSto10PS (16))
+		tmp |= 0x05F00000;
+	else
+		tmp |= 0x03F80000;
+
+	/* write SDRAM refresh interval register */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	mtdcr (SDRAM0_CFGDATA, tmp);
+
+	/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	mtdcr (SDRAM0_CFGDATA, tmp);
+
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the PIP405 board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for PIP405 board:
+   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
+   |       the Interrupt Controller in the South Bridge has caused the
+   |       interrupt. The IC must be read to determine which device
+   |       caused the interrupt.
+   |
+   +-------------------------------------------------------------------------*/
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char s[50];
+	unsigned char bc;
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	puts ("Board: ");
+
+	i = getenv_f("serial#", (char *)s, 32);
+	if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming PIP405");
+		} else {
+			b->serial_name[6] = 0;
+			printf ("%s SN: %s", b->serial_name,
+				&b->serial_name[7]);
+		}
+	} else {
+		s[6] = 0;
+		printf ("%s SN: %s", s, &s[7]);
+	}
+	bc = in8 (CONFIG_PORT_ADDR);
+	printf (" Boot Config: 0x%x\n", bc);
+	return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+phys_size_t initdram (int board_type)
+{
+	unsigned long bank_reg[4], tmp, bank_size;
+	int i, ds;
+	unsigned long TotalSize;
+
+	ds = 0;
+	/* since the DRAM controller is allready set up,
+	 * calculate the size with the bank registers
+	 */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
+	TotalSize = 0;
+	for (i = 0; i < 4; i++) {
+		if ((bank_reg[i] & 0x1) == 0x1) {
+			tmp = (bank_reg[i] >> 17) & 0x7;
+			bank_size = 4 << tmp;
+			TotalSize += bank_size;
+		} else
+			ds = 1;
+	}
+	if (ds == 1)
+		printf ("single-sided DIMM ");
+	else
+		printf ("double-sided DIMM ");
+	test_dram (TotalSize * 1024 * 1024);
+	/* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
+	(void) get_clocks();
+	if (gd->cpu_clk > 220000000)
+		TotalSize /= 2;
+	return (TotalSize * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+	/* not yet implemented */
+	return (1);
+}
+
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
+	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+	if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
+	       mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
+
+	return (0);
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+	return (in8 (CONFIG_PORT_ADDR) & 0x1);	/* return TRUE if console should be overwritten */
+}
+
+
+extern int isa_init (void);
+
+
+void print_pip405_rev (void)
+{
+	unsigned char part, vers, cfg;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	printf ("Rev:   PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
+			16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
+			vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
+}
+
+extern void check_env(void);
+
+
+int last_stage_init (void)
+{
+	print_pip405_rev ();
+	isa_init ();
+	stdio_print_current_devices ();
+	check_env();
+	return 0;
+}
+
+/************************************************************************
+* Print PIP405 Info
+************************************************************************/
+void print_pip405_info (void)
+{
+	unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
+			compwr, nicvga, scsirst;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	ledu = in8 (PLD_LED_USER_REG);
+	sysman = in8 (PLD_SYS_MAN_REG);
+	flashcom = in8 (PLD_FLASH_COM_REG);
+	can = in8 (PLD_CAN_REG);
+	serpwr = in8 (PLD_SER_PWR_REG);
+	compwr = in8 (PLD_COM_PWR_REG);
+	nicvga = in8 (PLD_NIC_VGA_REG);
+	scsirst = in8 (PLD_SCSI_RST_REG);
+	printf ("PLD Part %d version %d\n",
+		part & 0xf, vers & 0xf);
+	printf ("PLD Part %d version %d\n",
+		(part >> 4) & 0xf, (vers >> 4) & 0xf);
+	printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
+	printf ("Population Options %d %d %d %d\n",
+		(cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
+		(cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
+	printf ("User LED0 %s User LED1 %s\n",
+		((ledu & 0x1) == 0x1) ? "on" : "off",
+		((ledu & 0x2) == 0x2) ? "on" : "off");
+	printf ("Additionally Options %d %d\n",
+		(ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
+	printf ("User Config Switch %d %d %d %d\n",
+		(ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
+		(ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
+	switch (sysman & 0x3) {
+	case 0:
+		printf ("PCI Clocks are running\n");
+		break;
+	case 1:
+		printf ("PCI Clocks are stopped in POS State\n");
+		break;
+	case 2:
+		printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
+		break;
+	case 3:
+		printf ("PCI Clocks are stopped\n");
+		break;
+	}
+	switch ((sysman >> 2) & 0x3) {
+	case 0:
+		printf ("Main Clocks are running\n");
+		break;
+	case 1:
+		printf ("Main Clocks are stopped in POS State\n");
+		break;
+	case 2:
+	case 3:
+		printf ("PCI Clocks are stopped\n");
+		break;
+	}
+	printf ("INIT asserts %sINT2# (SMI)\n",
+			((sysman & 0x10) == 0x10) ? "" : "not ");
+	printf ("INIT asserts %sINT1# (NMI)\n",
+			((sysman & 0x20) == 0x20) ? "" : "not ");
+	printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
+	printf ("SER1 is routed to %s\n",
+			((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
+	printf ("COM2 is routed to %s\n",
+			((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
+	printf ("RS485 is configured as %s duplex\n",
+			((flashcom & 0x4) == 0x4) ? "full" : "half");
+	printf ("RS485 is connected to %s\n",
+			((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
+	printf ("SER1 uses handshakes %s\n",
+			((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
+	printf ("Bootflash is %swriteprotected\n",
+			((flashcom & 0x20) == 0x20) ? "not " : "");
+	printf ("Bootflash VPP is %s\n",
+			((flashcom & 0x40) == 0x40) ? "on" : "off");
+	printf ("Bootsector is %swriteprotected\n",
+			((flashcom & 0x80) == 0x80) ? "not " : "");
+	switch ((can) & 0x3) {
+	case 0:
+		printf ("CAN Controller is on address 0x1000..0x10FF\n");
+		break;
+	case 1:
+		printf ("CAN Controller is on address 0x8000..0x80FF\n");
+		break;
+	case 2:
+		printf ("CAN Controller is on address 0xE000..0xE0FF\n");
+		break;
+	case 3:
+		printf ("CAN Controller is disabled\n");
+		break;
+	}
+	switch ((can >> 2) & 0x3) {
+	case 0:
+		printf ("CAN Controller Reset is ISA Reset\n");
+		break;
+	case 1:
+		printf ("CAN Controller Reset is ISA Reset and POS State\n");
+		break;
+	case 2:
+	case 3:
+		printf ("CAN Controller is in reset\n");
+		break;
+	}
+	if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
+		printf ("CAN Interrupt is disabled\n");
+	else
+		printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
+	switch (serpwr & 0x3) {
+	case 0:
+		printf ("SER0 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("SER0 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SER0 Drivers are disabled\n");
+		break;
+	}
+	switch ((serpwr >> 2) & 0x3) {
+	case 0:
+		printf ("SER1 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("SER1 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SER1 Drivers are disabled\n");
+		break;
+	}
+	switch (compwr & 0x3) {
+	case 0:
+		printf ("COM1 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("COM1 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("COM1 Drivers are disabled\n");
+		break;
+	}
+	switch ((compwr >> 2) & 0x3) {
+	case 0:
+		printf ("COM2 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("COM2 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("COM2 Drivers are disabled\n");
+		break;
+	}
+	switch ((nicvga) & 0x3) {
+	case 0:
+		printf ("PHY is running\n");
+		break;
+	case 1:
+		printf ("PHY is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("PHY is in Power save mode\n");
+		break;
+	}
+	switch ((nicvga >> 2) & 0x3) {
+	case 0:
+		printf ("VGA is running\n");
+		break;
+	case 1:
+		printf ("VGA is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("VGA is in Power save mode\n");
+		break;
+	}
+	printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
+	printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
+	printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
+			(nicvga >> 7) & 0x1);
+	switch ((scsirst) & 0x3) {
+	case 0:
+		printf ("SCSI Controller is running\n");
+		break;
+	case 1:
+		printf ("SCSI Controller is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SCSI Controller is in Power save mode\n");
+		break;
+	}
+	printf ("SCSI termination is %s\n",
+			((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
+	printf ("SCSI Controller is %sreseted\n",
+			((scsirst & 0x10) == 0x10) ? "" : "not ");
+	printf ("IDE disks are %sreseted\n",
+			((scsirst & 0x20) == 0x20) ? "" : "not ");
+	printf ("ISA Bus is %sreseted\n",
+			((scsirst & 0x40) == 0x40) ? "" : "not ");
+	printf ("Super IO is %sreseted\n",
+			((scsirst & 0x80) == 0x80) ? "" : "not ");
+}
+
+void user_led0 (unsigned char on)
+{
+	if (on == TRUE)
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
+	else
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
+}
+
+void user_led1 (unsigned char on)
+{
+	if (on == TRUE)
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
+	else
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
+}
+
+void ide_set_reset (int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	unsigned char resreg;
+
+	resreg = in8 (PLD_SCSI_RST_REG);
+	if (idereset == 1)
+		resreg |= 0x20;
+	else {
+		udelay(10000);
+		resreg &= 0xdf;
+	}
+	out8 (PLD_SCSI_RST_REG, resreg);
+}
diff --git a/u-boot/board/mpl/pip405/pip405.h b/u-boot/board/mpl/pip405/pip405.h
new file mode 100644
index 0000000..704ab2c
--- /dev/null
+++ b/u-boot/board/mpl/pip405/pip405.h
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for PIP405
+ *****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void print_pip405_info(void);
+
+void user_led0(unsigned char on);
+void user_led1(unsigned char on);
+
+
+#define PLD_BASE_ADDRESS		CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
+#define PLD_PART_REG			PLD_BASE_ADDRESS + 0
+#define PLD_VERS_REG			PLD_BASE_ADDRESS + 1
+#define PLD_BOARD_CFG_REG		PLD_BASE_ADDRESS + 2
+#define PLD_LED_USER_REG		PLD_BASE_ADDRESS + 3
+#define PLD_SYS_MAN_REG			PLD_BASE_ADDRESS + 4
+#define PLD_FLASH_COM_REG		PLD_BASE_ADDRESS + 5
+#define PLD_CAN_REG			PLD_BASE_ADDRESS + 6
+#define PLD_SER_PWR_REG			PLD_BASE_ADDRESS + 7
+#define PLD_COM_PWR_REG			PLD_BASE_ADDRESS + 8
+#define PLD_NIC_VGA_REG			PLD_BASE_ADDRESS + 9
+#define PLD_SCSI_RST_REG		PLD_BASE_ADDRESS + 0xA
+
+#define PIIX4_VENDOR_ID			0x8086
+#define PIIX4_IDE_DEV_ID		0x7111
+
+#endif
+
+/* timings */
+
+/* CS Config register (CS7) */
+#define CONFIG_PORT_BME	0	/* Burst disable */
+#define CONFIG_PORT_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define CONFIG_PORT_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define CONFIG_PORT_OEN	1	/* Cycles from CS low to OE low   */
+#define CONFIG_PORT_WBN	1	/* Cycles from CS low to WE low   */
+#define CONFIG_PORT_WBF	1	/* Cycles from WE high to CS high */
+#define CONFIG_PORT_TH	2	/* Number of hold cycles after transfer */
+#define CONFIG_PORT_RE	0	/* Ready disabled */
+#define CONFIG_PORT_SOR	1	/* Sample on Ready disabled */
+#define CONFIG_PORT_BEM	0	/* Byte Write only active on Write cycles */
+#define CONFIG_PORT_PEN	0	/* Parity disable */
+#define CONFIG_PORT_AP	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+				(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define CONFIG_PORT_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define CONFIG_PORT_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define CONFIG_PORT_BW	0	/* 16Bit */
+#define CONFIG_PORT_CR	((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
+
+/* Flash CS0 or CS 1 */
+/* 0x7F8FFE80 slowest timing at all... */
+#define FLASH_BME_B	1	/* Burst enable */
+#define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
+#define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define FLASH_BME	0	/* Burst disable */
+#define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define FLASH_OEN	1	/* Cycles from CS low to OE low   */
+#define FLASH_WBN	1	/* Cycles from CS low to WE low   */
+#define FLASH_WBF	1	/* Cycles from WE high to CS high */
+#define FLASH_TH	2	/* Number of hold cycles after transfer */
+#define FLASH_RE	0	/* Ready disabled */
+#define FLASH_SOR	1	/* Sample on Ready disabled */
+#define FLASH_BEM	0	/* Byte Write only active on Write cycles */
+#define FLASH_PEN	0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define FLASH_AP	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+/* Access Parameter Register for Boot */
+#define FLASH_AP_B	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define FLASH_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define FLASH_BW	1	/* 16Bit */
+/* CR register for Boot */
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+/* CR register for non Boot */
+#define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+
+/* MPS CS1 or CS0 */
+/* Boot CS: */
+#define MPS_BME_B	1	/* Burst enable */
+#define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
+#define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define MPS_BME		0	/* Burst disable */
+#define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define MPS_OEN		1	/* Cycles from CS low to OE low   */
+#define MPS_WBN		1	/* Cycles from CS low to WE low   */
+#define MPS_WBF		1	/* Cycles from WE high to CS high */
+#define MPS_TH		2	/* Number of hold cycles after transfer */
+#define MPS_RE		0	/* Ready disabled */
+#define MPS_SOR		1	/* Sample on Ready disabled */
+#define MPS_BEM		0	/* Byte Write only active on Write cycles */
+#define MPS_PEN		0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define MPS_AP		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+/* Access Parameter Register for Boot */
+#define MPS_AP_B	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define MPS_BU		3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define MPS_BW		0	/* 8Bit */
+/* CR register for Boot */
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+/* CR register for non Boot */
+#define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/u-boot/board/mpl/pip405/u-boot.lds.debug b/u-boot/board/mpl/pip405/u-boot.lds.debug
new file mode 100644
index 0000000..0e9cdcf
--- /dev/null
+++ b/u-boot/board/mpl/pip405/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mpl/vcma9/Makefile b/u-boot/board/mpl/vcma9/Makefile
new file mode 100644
index 0000000..27cef1d
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= vcma9.o flash.o cmd_vcma9.o
+COBJS	+= ../common/common_util.o
+
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mpl/vcma9/cmd_vcma9.c b/u-boot/board/mpl/vcma9/cmd_vcma9.c
new file mode 100644
index 0000000..0d5f46e
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/cmd_vcma9.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * adapted for VCMA9
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+#if defined(CONFIG_CS8900)
+#include <../drivers/net/cs8900.h>
+
+static uchar cs8900_chksum(ushort data)
+{
+	return((data >> 8) & 0x00FF) + (data & 0x00FF);
+}
+
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void print_vcma9_info(void);
+extern int vcma9_cantest(int);
+extern int vcma9_nandtest(void);
+extern int vcma9_nanderase(void);
+extern int vcma9_nandread(ulong);
+extern int vcma9_nandwrite(ulong);
+extern int vcma9_dactest(int);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/* ------------------------------------------------------------------------- */
+
+int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct eth_device *dev;
+	char cs8900_name[10];
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_vcma9_info();
+		return 0;
+	}
+#if defined(CONFIG_CS8900)
+	if (strcmp(argv[1], "cs8900") == 0) {
+		sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME);
+		dev = eth_get_dev_by_name(cs8900_name);
+		if (!dev) {
+			printf("Couldn't find CS8900 driver");
+			return 0;
+		}
+		if (strcmp(argv[2], "read") == 0) {
+			uchar addr; ushort data;
+
+			addr = simple_strtoul(argv[3], NULL, 16);
+			cs8900_e2prom_read(dev, addr, &data);
+			printf("0x%2.2X: 0x%4.4X\n", addr, data);
+		} else if (strcmp(argv[2], "write") == 0) {
+			uchar addr; ushort data;
+
+			addr = simple_strtoul(argv[3], NULL, 16);
+			data = simple_strtoul(argv[4], NULL, 16);
+			cs8900_e2prom_write(dev, addr, data);
+		} else if (strcmp(argv[2], "setaddr") == 0) {
+			uchar addr, i, csum; ushort data;
+			uchar ethaddr[6];
+
+			/* check for valid ethaddr */
+			if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
+				addr = 1;
+				data = 0x2158;
+				cs8900_e2prom_write(dev, addr, data);
+				csum = cs8900_chksum(data);
+				addr++;
+				for (i = 0; i < 6; i+=2) {
+					data = ethaddr[i+1] << 8 |
+					       ethaddr[i];
+					cs8900_e2prom_write(dev, addr, data);
+					csum += cs8900_chksum(data);
+					addr++;
+				}
+				/* calculate header link byte */
+				data = 0xA100 | (addr * 2);
+				cs8900_e2prom_write(dev, 0, data);
+				csum += cs8900_chksum(data);
+				/* write checksum word */
+				cs8900_e2prom_write(dev, addr, (0 - csum) << 8);
+			} else {
+				puts("\nplease defined 'ethaddr'\n");
+			}
+		} else if (strcmp(argv[2], "dump") == 0) {
+			uchar addr = 0, endaddr, csum; ushort data;
+
+			puts("Dump of CS8900 config device: ");
+			cs8900_e2prom_read(dev, addr, &data);
+			if ((data & 0xE000) == 0xA000) {
+				endaddr = (data & 0x00FF) / 2;
+				csum = cs8900_chksum(data);
+				for (addr = 1; addr <= endaddr; addr++) {
+					cs8900_e2prom_read(dev, addr, &data);
+					printf("\n0x%2.2X: 0x%4.4X", addr, data);
+					csum += cs8900_chksum(data);
+				}
+				printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
+			} else {
+				puts("no valid config found");
+			}
+			puts("\n");
+		}
+
+		return 0;
+	}
+#endif
+#if 0
+	if (strcmp(argv[1], "cantest") == 0) {
+		if (argc >= 3)
+			vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+			vcma9_cantest(0);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandtest") == 0) {
+		vcma9_nandtest();
+		return 0;
+	}
+	if (strcmp(argv[1], "nanderase") == 0) {
+		vcma9_nanderase();
+		return 0;
+	}
+	if (strcmp(argv[1], "nandread") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandread(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandwrite") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandwrite(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "dactest") == 0) {
+		if (argc >= 3)
+			vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+		vcma9_dactest(0);
+		return 0;
+	}
+#endif
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+	vcma9, 6, 1, do_vcma9,
+	"VCMA9 specific commands",
+	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory"
+);
diff --git a/u-boot/board/mpl/vcma9/config.mk b/u-boot/board/mpl/vcma9/config.mk
new file mode 100644
index 0000000..e345913
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2002, 2003
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# MPL VCMA9 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.mpl.ch/ for more information about the MPL VCMA9
+#
+
+#
+# MPL VCMA9 has 1 bank of minimal 16 MB DRAM
+# from 0x30000000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3040'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3080'0000
+#
+
+
+#CONFIG_SYS_TEXT_BASE = 0x30F80000
+CONFIG_SYS_TEXT_BASE = 0x33F80000
diff --git a/u-boot/board/mpl/vcma9/flash.c b/u-boot/board/mpl/vcma9/flash.c
new file mode 100644
index 0000000..7abf9cf
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/flash.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+
+#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x000000F0
+#define CMD_UNLOCK1		0x000000AA
+#define CMD_UNLOCK2		0x00000055
+#define CMD_ERASE_SETUP		0x00000080
+#define CMD_ERASE_CONFIRM	0x00000030
+#define CMD_PROGRAM		0x000000A0
+#define CMD_UNLOCK_BYPASS	0x00000020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE		0x00000080
+#define BIT_RDY_MASK		0x00000080
+#define BIT_PROGRAM_ERROR	0x00000020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+			flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 3) {
+				/* 1st one is 16 KB */
+				if (j == 0) {
+					flash_info[i].start[j] =
+						flashbase + 0;
+				}
+
+				/* 2nd and 3rd are both 8 KB */
+				if ((j == 1) || (j == 2)) {
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + (j -
+								      1) *
+						0x2000;
+				}
+
+				/* 4th 32 KB */
+				if (j == 3) {
+					flash_info[i].start[j] =
+						flashbase + 0x8000;
+				}
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 3) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		puts ("AMD: ");
+		break;
+	default:
+		puts ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV400B & FLASH_TYPEMASK):
+		puts ("1x Amd29LV400BB (4Mbit)\n");
+		break;
+	case (AMD_ID_LV800B & FLASH_TYPEMASK):
+		puts ("1x Amd29LV800BB (8Mbit)\n");
+		break;
+	default:
+		puts ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	puts ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			puts ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	puts ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ushort result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip = TMO;
+					break;
+				}
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip = READY;
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip = ERR;
+
+			} while (!chip);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			puts ("ok.\n");
+		} else {	/* it was protected */
+
+			puts ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		puts ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest;
+	ushort result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			chip = ERR | TMO;
+			break;
+		}
+		if (!chip && ((result & 0x80) == (data & 0x80)))
+			chip = READY;
+
+		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip = READY;
+			else
+				chip = ERR;
+		}
+
+	} while (!chip);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	int l;
+	int i, rc;
+	ushort data;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_hword (info, wp, data);
+}
diff --git a/u-boot/board/mpl/vcma9/lowlevel_init.S b/u-boot/board/mpl/vcma9/lowlevel_init.S
new file mode 100644
index 0000000..062e868
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/lowlevel_init.S
@@ -0,0 +1,212 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+#define BWSCON		0x48000000
+#define PLD_BASE	0x2C000000
+#define SDRAM_REG	0x2C000106
+
+/* BWSCON */
+#define DW8			(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
+
+/* BANKSIZE */
+#define BURST_EN		(0x1<<7)
+
+#define B1_BWSCON		(DW16)
+#define B2_BWSCON		(DW32)
+#define B3_BWSCON		(DW32)
+#define B4_BWSCON		(DW16 + WAIT + UBLB)
+#define B5_BWSCON		(DW8 + UBLB)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
+
+/* BANK0CON */
+#define B0_Tacs			0x0	/*  0clk */
+#define B0_Tcos			0x1	/*  1clk */
+/*#define B0_Tcos		0x0	  0clk */
+#define B0_Tacc			0x7	/*  14clk */
+/*#define B0_Tacc		0x5	  8clk */
+#define B0_Tcoh			0x0	/*  0clk */
+#define B0_Tah			0x0	/*  0clk */
+#define B0_Tacp			0x0     /* page mode is not used */
+#define B0_PMC			0x0	/* page mode disabled */
+
+/* BANK1CON */
+#define B1_Tacs			0x0	/*  0clk */
+#define B1_Tcos			0x1	/*  1clk */
+/*#define B1_Tcos		0x0	  0clk */
+#define B1_Tacc			0x7	/*  14clk */
+/*#define B1_Tacc		0x5	  8clk */
+#define B1_Tcoh			0x0	/*  0clk */
+#define B1_Tah			0x0	/*  0clk */
+#define B1_Tacp			0x0     /* page mode is not used */
+#define B1_PMC			0x0	/* page mode disabled */
+
+#define B2_Tacs			0x3	/*  4clk */
+#define B2_Tcos			0x3	/*  4clk */
+#define B2_Tacc			0x7     /* 14clk */
+#define B2_Tcoh			0x3	/*  4clk */
+#define B2_Tah			0x3	/*  4clk */
+#define B2_Tacp			0x0	/* page mode is not used */
+#define B2_PMC			0x0     /* page mode disabled */
+
+#define B3_Tacs			0x3	/*  4clk */
+#define B3_Tcos			0x3	/*  4clk */
+#define B3_Tacc			0x7     /* 14clk */
+#define B3_Tcoh			0x3	/*  4clk */
+#define B3_Tah			0x3	/*  4clk */
+#define B3_Tacp			0x0	/* page mode is not used */
+#define B3_PMC			0x0     /* page mode disabled */
+
+#define B4_Tacs			0x3	/*  4clk */
+#define B4_Tcos			0x1	/*  1clk */
+#define B4_Tacc			0x7	/* 14clk */
+#define B4_Tcoh			0x1	/*  1clk */
+#define B4_Tah			0x0	/*  0clk */
+#define B4_Tacp			0x0     /* page mode is not used */
+#define B4_PMC			0x0	/* page mode disabled */
+
+#define B5_Tacs			0x0	/*  0clk */
+#define B5_Tcos			0x3	/*  4clk */
+#define B5_Tacc			0x5	/*  8clk */
+#define B5_Tcoh			0x2	/*  2clk */
+#define B5_Tah			0x1	/*  1clk */
+#define B5_Tacp			0x0     /* page mode is not used */
+#define B5_PMC			0x0	/* page mode disabled */
+
+#define B6_MT			0x3	/* SDRAM */
+#define B6_Trcd			0x1	/* 3clk */
+#define B6_SCAN			0x2	/* 10bit */
+
+#define B7_MT			0x3	/* SDRAM */
+#define B7_Trcd			0x1	/* 3clk */
+#define B7_SCAN			0x2	/* 10bit */
+
+/* REFRESH parameter */
+#define REFEN			0x1	/* Refresh enable */
+#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x0	/* 2clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr			0x2	/* 3clk */
+#define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =CSDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #CSDATA_END-CSDATA
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* PLD access is now possible */
+	/* r0 == SDRAMDATA */
+	/* r1 == SDRAM controller regs */
+	ldr	r2, =PLD_BASE
+	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
+	mov	r4, #SDRAMDATA1_END-SDRAMDATA
+	/* calculate start and end point */
+	mla	r0, r3, r4, r0
+	add     r2, r0, r4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+CSDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+CSDATA_END:
+
+SDRAMDATA:
+/* 4Mx8x4 */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+SDRAMDATA1_END:
+
+/* 8Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+
+/* 2Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+
+/* 4Mx8x2 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
diff --git a/u-boot/board/mpl/vcma9/vcma9.c b/u-boot/board/mpl/vcma9/vcma9.c
new file mode 100644
index 0000000..978e6fd
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/vcma9.c
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include <stdio_dev.h>
+#include <i2c.h>
+
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	struct s3c24x0_clock_power * const clk_power =
+					s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	clk_power->locktime = 0xFFFFFF;
+
+	/* configure MPLL */
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (4000);
+
+	/* configure UPLL */
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (8000);
+
+	/* set up the I/O ports */
+	gpio->gpacon = 0x007FFFFF;
+	gpio->gpbcon = 0x002AAAAA;
+	gpio->gpbup = 0x000002BF;
+	gpio->gpccon = 0xAAAAAAAA;
+	gpio->gpcup = 0x0000FFFF;
+	gpio->gpdcon = 0xAAAAAAAA;
+	gpio->gpdup = 0x0000FFFF;
+	gpio->gpecon = 0xAAAAAAAA;
+	gpio->gpeup = 0x000037F7;
+	gpio->gpfcon = 0x00000000;
+	gpio->gpfup = 0x00000000;
+	gpio->gpgcon = 0xFFEAFF5A;
+	gpio->gpgup = 0x0000F0DC;
+	gpio->gphcon = 0x0028AAAA;
+	gpio->gphup = 0x00000656;
+
+	/* setup correct IRQ modes for NIC */
+	/* rising edge mode */
+	gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
+
+	/* select USB port 2 to be host or device (fix to host for now) */
+	gpio->misccr |= 0x08;
+
+	/* init serial */
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->have_console = 1;
+	serial_init();
+
+	/* arch number of VCMA9-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x30000100;
+
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+
+/*
+ * NAND flash initialization.
+ */
+#if defined(CONFIG_CMD_NAND)
+extern ulong
+nand_probe(ulong physadr);
+
+
+static inline void NF_Reset(void)
+{
+    int i;
+
+    NF_SetCE(NFCE_LOW);
+    NF_Cmd(0xFF);		/* reset command */
+    for(i = 0; i < 10; i++);	/* tWB = 100ns. */
+    NF_WaitRB();		/* wait 200~500us; */
+    NF_SetCE(NFCE_HIGH);
+}
+
+
+static inline void NF_Init(void)
+{
+#if 0 /* a little bit too optimistic */
+#define TACLS   0
+#define TWRPH0  3
+#define TWRPH1  0
+#else
+#define TACLS   0
+#define TWRPH0  4
+#define TWRPH1  2
+#endif
+
+    NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
+    /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
+    /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
+    /* En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1 */
+
+    NF_Reset();
+}
+
+void
+nand_init(void)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	NF_Init();
+#ifdef DEBUG
+	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
+#endif
+	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
+}
+#endif
+
+/*
+ * Get some Board/PLD Info
+ */
+
+static u8 Get_PLD_ID(void)
+{
+	VCMA9_PLD * const pld = VCMA9_get_base_PLD();
+
+	return(pld->ID);
+}
+
+static u8 Get_PLD_BOARD(void)
+{
+	VCMA9_PLD * const pld = VCMA9_get_base_PLD();
+
+	return(pld->BOARD);
+}
+
+static u8 Get_PLD_SDRAM(void)
+{
+	VCMA9_PLD * const pld = VCMA9_get_base_PLD();
+
+	return(pld->SDRAM);
+}
+
+static u8 Get_PLD_Version(void)
+{
+	return((Get_PLD_ID() >> 4) & 0x0F);
+}
+
+static u8 Get_PLD_Revision(void)
+{
+	return(Get_PLD_ID() & 0x0F);
+}
+
+#if 0	/* not used */
+static int Get_Board_Config(void)
+{
+	u8 config = Get_PLD_BOARD() & 0x03;
+
+	if (config == 3)
+	    return 1;
+	else
+	    return 0;
+}
+#endif
+
+static uchar Get_Board_PCB(void)
+{
+	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
+}
+
+static u8 Get_SDRAM_ChipNr(void)
+{
+	switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
+		case 0: return 4;
+		case 1: return 1;
+		case 2: return 2;
+		default: return 0;
+	}
+}
+
+static ulong Get_SDRAM_ChipSize(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return 16 * (1024*1024);
+		case 1: return 32 * (1024*1024);
+		case 2: return  8 * (1024*1024);
+		case 3: return  8 * (1024*1024);
+		default: return 0;
+	}
+}
+static const char * Get_SDRAM_ChipGeom(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return "4Mx8x4";
+		case 1: return "8Mx8x4";
+		case 2: return "2Mx8x4";
+		case 3: return "4Mx8x2";
+		default: return "unknown";
+	}
+}
+
+static void Show_VCMA9_Info(char *board_name, char *serial)
+{
+	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
+		board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
+	printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+	char s[50];
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	i = getenv_f("serial#", s, 32);
+	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming VCMA9");
+		} else {
+			b->serial_name[5] = 0;
+			Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
+		}
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
+	/*printf("\n");*/
+	return(0);
+}
+
+
+int last_stage_init(void)
+{
+	checkboard();
+	stdio_print_current_devices();
+	check_env();
+	return 0;
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+#if !CONFIG_USB_KEYBOARD
+int overwrite_console(void)
+{
+	/* return TRUE if console should be overwritten */
+	return 0;
+}
+#endif
+
+/************************************************************************
+* Print VCMA9 Info
+************************************************************************/
+void print_vcma9_info(void)
+{
+	char s[50];
+	int i;
+
+	if ((i = getenv_f("serial#", s, 32)) < 0) {
+		puts ("### No HW ID - assuming VCMA9");
+		printf("i %d", i*24);
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/mpl/vcma9/vcma9.h b/u-boot/board/mpl/vcma9/vcma9.h
new file mode 100644
index 0000000..94fd2fa
--- /dev/null
+++ b/u-boot/board/mpl/vcma9/vcma9.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002, 2003
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for VCMA9
+ *****************************************************************************/
+
+#include <asm/arch/s3c24x0_cpu.h>
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void print_vcma9_info(void);
+
+#if defined(CONFIG_CMD_NAND)
+typedef enum {
+	NFCE_LOW,
+	NFCE_HIGH
+} NFCE_STATE;
+
+static inline void NF_Conf(u16 conf)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	nand->NFCONF = conf;
+}
+
+static inline void NF_Cmd(u8 cmd)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	nand->NFCMD = cmd;
+}
+
+static inline void NF_CmdW(u8 cmd)
+{
+	NF_Cmd(cmd);
+	udelay(1);
+}
+
+static inline void NF_Addr(u8 addr)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	nand->NFADDR = addr;
+}
+
+static inline void NF_SetCE(NFCE_STATE s)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	switch (s) {
+		case NFCE_LOW:
+			nand->NFCONF &= ~(1<<11);
+			break;
+
+		case NFCE_HIGH:
+			nand->NFCONF |= (1<<11);
+			break;
+	}
+}
+
+static inline void NF_WaitRB(void)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	while (!(nand->NFSTAT & (1<<0)));
+}
+
+static inline void NF_Write(u8 data)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	nand->NFDATA = data;
+}
+
+static inline u8 NF_Read(void)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	return(nand->NFDATA);
+}
+
+static inline void NF_Init_ECC(void)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	nand->NFCONF |= (1<<12);
+}
+
+static inline u32 NF_Read_ECC(void)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	return(nand->NFECC);
+}
+
+#endif
+
+/* VCMA9 PLD regsiters */
+typedef struct {
+	u8	ID;
+	u8	NIC;
+	u8	CAN;
+	u8	MISC;
+	u8	GPCD;
+	u8	BOARD;
+	u8	SDRAM;
+} /*__attribute__((__packed__))*/ VCMA9_PLD;
+
+#define VCMA9_PLD_BASE	0x2C000100
+static inline VCMA9_PLD *VCMA9_get_base_PLD(void)
+{
+	return (VCMA9_PLD * const)VCMA9_PLD_BASE;
+}
diff --git a/u-boot/board/mpr2/Makefile b/u-boot/board/mpr2/Makefile
new file mode 100644
index 0000000..b9c45b9
--- /dev/null
+++ b/u-boot/board/mpr2/Makefile
@@ -0,0 +1,58 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# (C) Copyright 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mpr2.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mpr2/lowlevel_init.S b/u-boot/board/mpr2/lowlevel_init.S
new file mode 100644
index 0000000..0f7a892
--- /dev/null
+++ b/u-boot/board/mpr2/lowlevel_init.S
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * board/mpr2/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+/*
+ * Set frequency multipliers and dividers in FRQCR.
+ */
+	write16	WTCSR_A, WTCSR_D
+
+	write16	WTCNT_A, WTCNT_D
+
+	write16	FRQCR_A, FRQCR_D
+
+/*
+ * Setup CS0 (Flash).
+ */
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+/*
+ * Setup CS3 (SDRAM).
+ */
+	write32	CS3BCR_A, CS3BCR_D
+
+	write32	CS3WCR_A, CS3WCR_D
+
+	write32	SDCR_A, SDCR_D1
+
+	write32	RTCSR_A, RTCSR_D
+
+	write32	RTCNT_A, RTCNT_D
+
+	write32	RTCOR_A, RTCOR_D
+
+	write32	SDCR_A, SDCR_D2
+
+	mov.l	SDMR3_A, r1
+	mov.l	SDMR3_D, r0
+	add	r0, r1
+	mov	#0, r0
+	mov.w	r0, @r1
+
+	rts
+	nop
+
+	.align 4
+
+/*
+ * Configuration for MPR2 A.3 through A.7
+ */
+
+/*
+ * PLL Settings
+ */
+FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
+WTCNT_D:	.word	0x5A00		/* start counting at zero */
+WTCSR_D:	.word	0xA507		/* divide by 4096 */
+.align 2
+/*
+ * Spansion S29GL256N11 @ 48 MHz
+ */
+/* 1 idle cycle inserted, normal space, 16 bit */
+CS0BCR_D:	.long	0x12490400
+/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0WCR_D:	.long	0x00000340
+
+/*
+ * Samsung K4S511632B-UL75 @ 48 MHz
+ * Micron MT48LC32M16A2-75 @ 48 MHz
+ */
+/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3BCR_D:	.long	0x10004400
+/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+CS3WCR_D:	.long	0x00000091
+/* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D1:	.long	0x00000012
+SDCR_D2:	.long	0x00000812	/* refresh */
+RTCSR_D:	.long	0xA55A0008	/* 1/4, once */
+RTCNT_D:	.long	0xA55A005D	/* count 93 */
+RTCOR_D:	.long	0xa55a005d	/* count 93 */
+/* mode register CL2, burst read and SINGLE WRITE */
+SDMR3_D:	.long	0x440
+
+/*
+ * Registers
+ */
+
+FRQCR_A:	.long	0xA415FF80
+WTCNT_A:	.long	0xA415FF84
+WTCSR_A:	.long	0xA415FF86
+
+#define BSC_BASE	0xA4FD0000
+CS0BCR_A:	.long	BSC_BASE + 0x04
+CS3BCR_A:	.long	BSC_BASE + 0x0C
+CS0WCR_A:	.long	BSC_BASE + 0x24
+CS3WCR_A:	.long	BSC_BASE + 0x2C
+SDCR_A:		.long	BSC_BASE + 0x44
+RTCSR_A:	.long	BSC_BASE + 0x48
+RTCNT_A:	.long	BSC_BASE + 0x4C
+RTCOR_A:	.long	BSC_BASE + 0x50
+SDMR3_A:	.long	BSC_BASE + 0x5000
diff --git a/u-boot/board/mpr2/mpr2.c b/u-boot/board/mpr2/mpr2.c
new file mode 100644
index 0000000..4881859
--- /dev/null
+++ b/u-boot/board/mpr2/mpr2.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * board/mpr2/mpr2.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: MPR2\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * For MPR2 A.3 through A.7
+	 */
+
+	/* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
+	__raw_writel(0x36db0400, CS2BCR);    /* 4 idle cycles, normal space, 16 bit data bus */
+	__raw_writel(0x000003c0, CS2WCR);    /* (WR:8), no ext. wait */
+
+	/* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
+	__raw_writel(0x00000200, CS4BCR);    /* no idle cycles, normal space, 8 bit data bus */
+	__raw_writel(0x00100981, CS4WCR);    /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+	/* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
+	__raw_writel(0x00000200, CS5ABCR);   /* no idle cycles, normal space, 8 bit data bus */
+	__raw_writel(0x00100981, CS5AWCR);   /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+	/* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
+	__raw_writel(0x00000200, CS5BBCR);   /* no idle cycles, normal space, 8 bit data bus */
+	__raw_writel(0x00100981, CS5BWCR);   /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+	/* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
+	__raw_writel(0x00000200, CS6ABCR);   /* no idle cycles, normal space, 8 bit data bus */
+	__raw_writel(0x001009C1, CS6AWCR);   /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
+
+	/* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
+	__raw_writew(0xAABC, PSELA);  /*    10        10        10        10       10    11    11             00 */
+
+	/* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
+	__raw_writew(0x3C00, PSELB);  /*       0           0         11         11        0        0  00000000 */
+
+	/* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
+	__raw_writew(0x0000, PSELC);  /*     00         00         00         00  00000000 */
+
+	/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
+	__raw_writew(0x0000, PSELD);  /*     0         00        00          00        00          00        00         00         0 */
+
+	/* OTH:  (00) Other fuction
+	 * GPO:  (01) General Purpose Output
+	 * GPI:  (11) General Purpose Input
+	 * GPI+: (10) General Purpose Input with internal pull-up
+	 *-------------------------------------------------------
+	 * A7 GPO(LED8);     A6 GPO(LED7);     A5 GPO(LED6);        A4 GPO(LED5);
+	 * A3 GPO(LED4);     A2 GPO(LED3);     A1 GPO(LED2);        A0 GPO(LED1); */
+	__raw_writew(0x5555, PACR);   /* 01 01 01 01 01 01 01 01 */
+
+	/* B7 GPO(RST4);     B6 GPO(RST3);     B5 GPO(RST2);        B4 GPO(RST1);
+	 * B3 GPO(PB3);      B2 GPO(PB2);      B1 GPO(PB1);         B0 GPO(PB0); */
+	__raw_writew(0x5555, PBCR);   /* 01 01 01 01 01 01 01 01 */
+
+	/* C7 GPO(PC7);      C6 GPO(PC6);      C5 GPO(PC5);         C4 GPO(PC4);
+	 * C3 LCD_DATA3;     C2 LCD_DATA2;     C1 LCD_DATA1;        C0 LCD_DATA0; */
+	__raw_writew(0x5500, PCCR);   /* 01 01 01 01 00 00 00 00 */
+
+	/* D7 GPO(PD7);      D6 GPO(PD6);      D5 GPO(PD5);         D4 GPO(PD4);
+	 * D3 GPO(PD3);      D2 GPO(PD2);      D1 GPO(PD1);         D0 GPO(PD0); */
+	__raw_writew(0x5555, PDCR);   /* 01 01 01 01 01 01 01 01 */
+
+	/* E7 (x);           E6 GPI(nu);       E5 GPI(nu);          E4 LCD_M_DISP;
+	 * E3 LCD_CL1;       E2 LCD_CL2;       E1 LCD_DON;          E0 LCD_FLM; */
+	__raw_writew(0x2800, PECR);   /* 00 10 10 00 00 00 00 00 */
+
+	/* F7 (x);           F6 DA1(VLCD);     F5 DA0(nc);          F4 AN3;
+	 * F3 AN2(MID_AD);   F2 AN1(EARTH_AD); F1 AN0(TEMP);        F0 GPI+(nc); */
+	__raw_writew(0x0002, PFCR);   /* 00 00 00 00 00 00 00 10 */
+
+	/* G7 (x);          G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
+	 * G3 GPI(KEY1);     G2 GPO(LED11);      G1 GPO(LED10);     G0 GPO(LED9); */
+	__raw_writew(0x03D5, PGCR);   /* 00 00 00 11 11 01 01 01 */
+
+	/* H7 (x);            H6 /RAS(BRAS);      H5 /CAS(BCAS);    H4 CKE(BCKE);
+	 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR;      H0 USB1_PWR; */
+	__raw_writew(0x0050, PHCR);   /* 00 00 00 00 01 01 00 00 */
+
+	/* J7 (x);           J6 AUDCK;         J5 ASEBRKAK;         J4 AUDATA3;
+	 * J3 AUDATA2;       J2 AUDATA1;       J1 AUDATA0;          J0 AUDSYNC; */
+	__raw_writew(0x0000, PJCR);   /* 00 00 00 00 00 00 00 00 */
+
+	/* K7 (x);           K6 (x);           K5 (x);              K4 (x)
+	 * K3 PINT7(/PWR2);  K2 PINT6(/PWR1);  K1 PINT5(nc);        K0 PINT4(FLASH_READY); */
+	__raw_writew(0x00FB, PKCR);   /* 00 00 00 00 11 11 10 11 */
+
+	/* L7 TRST;          L6 TMS;           L5 TDO;              L4 TDI;
+	 * L3 TCK;           L2 (x);           L1 (x);              L0 (x); */
+	__raw_writew(0x0000, PLCR);    /* 00 00 00 00 00 00 00 00 */
+
+	/* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH);  M5 GPO(LAN_SPEED);   M4 GPO(LAN_RESET);
+	 * M3 GPO(BUZZER);      M2 GPO(LCD_BL);      M1 CS5B(CAN3_CS);    M0 GPI+(nc); */
+	__raw_writew(0x5552, PMCR);   /* 01 01 01 01 01 01 00 10 */
+	__raw_writeb(0xF0, PMDR);     /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
+
+	/* P7 (x);           P6 (x);           P5 (x);              P4 GPO(on pullup);
+	 * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ);   P0 IRQ0(CAN1_IRQ); */
+	__raw_writew(0x0100, PPCR);   /* 00 00 00 01 00 00 00 00 */
+	__raw_writeb(0x10, PPDR);     /* no current flow through pullup */
+
+	/* R7 A25;           R6 A24;           R5 A23;              R4 A22;
+	 * R3 A21;           R2 A20;           R1 A19;              R0 A0; */
+	__raw_writew(0x0000, PRCR);   /* 00 00 00 00 00 00 00 00 */
+
+	/* S7 (x);              S6 (x);        S5 (x);              S4 GPO(EEPROM_CS2);
+	 * S3 GPO(EEPROM_CS1);  S2 SIOF0_TXD;  S1 SIOF0_RXD;        S0 SIOF0_SCK; */
+	__raw_writew(0x0140, PSCR);   /* 00 00 00 01 01 00 00 00 */
+
+	/* T7 (x);           T6 (x);           T5 (x);              T4 COM1_CTS;
+	 * T3 COM1_RTS;      T2 COM1_TXD;      T1 COM1_RXD;         T0 GPO(WDOG); */
+	__raw_writew(0x0001, PTCR);   /* 00 00 00 00 00 00 00 01 */
+
+	/* U7 (x);           U6 (x);           U5 (x);              U4 GPI+(/AC_FAULT);
+	 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD;     U1 TOUCH_RXD;        U0 TOUCH_SCK; */
+	__raw_writew(0x0240, PUCR);   /* 00 00 00 10 01 00 00 00 */
+
+	/* V7 (x);           V6 (x);           V5 (x);              V4 GPO(MID2);
+	 * V3 GPO(MID1);     V2 CARD_TxD;      V1 CARD_RxD;         V0 GPI+(/BAT_FAULT); */
+	__raw_writew(0x0142, PVCR);   /* 00 00 00 01 01 00 00 10 */
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
diff --git a/u-boot/board/ms7720se/Makefile b/u-boot/board/ms7720se/Makefile
new file mode 100644
index 0000000..0bf7743
--- /dev/null
+++ b/u-boot/board/ms7720se/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7720se/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ms7720se.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ms7720se/lowlevel_init.S b/u-boot/board/ms7720se/lowlevel_init.S
new file mode 100644
index 0000000..3df25b6
--- /dev/null
+++ b/u-boot/board/ms7720se/lowlevel_init.S
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write16	WTCSR_A, WTCSR_D
+
+	write16	WTCNT_A, WTCNT_D
+
+	write16	FRQCR_A, FRQCR_D
+
+	write16	UCLKCR_A, UCLKCR_D
+
+	write32	CMNCR_A, CMNCR_D
+
+	write32	CMNCR_A, CMNCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS2BCR_A, CS2BCR_D
+
+	write32	CS3BCR_A, CS3BCR_D
+
+	write32	CS4BCR_A, CS4BCR_D
+
+	write32	CS5ABCR_A, CS5ABCR_D
+
+	write32	CS5BBCR_A, CS5BBCR_D
+
+	write32	CS6ABCR_A, CS6ABCR_D
+
+	write32	CS6BBCR_A, CS6BBCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+	write32	CS2WCR_A, CS2WCR_D
+
+	write32	CS3WCR_A, CS3WCR_D
+
+	write32	CS4WCR_A, CS4WCR_D
+
+	write32	CS5AWCR_A, CS5AWCR_D
+
+	write32	CS5BWCR_A, CS5BWCR_D
+
+	write32	CS6AWCR_A, CS6AWCR_D
+
+	write32	CS6BWCR_A, CS6BWCR_D
+
+	write32	SDCR_A, SDCR_D1
+
+	write32	RTCSR_A, RTCSR_D
+
+	write32	RTCNT_A RTCNT_D
+
+	write32	RTCOR_A, RTCOR_D
+
+	write32	SDCR_A, SDCR_D2
+
+	write16	SDMR3_A, SDMR3_D
+
+	write16	PCCR_A, PCCR_D
+
+	write16	PDCR_A, PDCR_D
+
+	write16	PECR_A, PECR_D
+
+	write16	PGCR_A, PGCR_D
+
+	write16	PHCR_A, PHCR_D
+
+	write16	PPCR_A, PPCR_D
+
+	write16	PTCR_A, PTCR_D
+
+	write16	PVCR_A, PVCR_D
+
+	write16	PSELA_A, PSELA_D
+
+	write32	CCR_A, CCR_D
+
+	write8	LED_A, LED_D
+
+	rts
+	 nop
+
+	.align 4
+
+FRQCR_A:	.long	0xA415FF80	/* FRQCR Address */
+WTCNT_A:	.long	0xA415FF84
+WTCSR_A:	.long	0xA415FF86
+UCLKCR_A:	.long	0xA40A0008
+FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
+WTCNT_D:	.word	0x5A00
+WTCSR_D:	.word	0xA506
+UCLKCR_D:	.word	0xA5C0
+
+#define BSC_BASE	0xA4FD0000
+CMNCR_A:	.long	BSC_BASE
+CS0BCR_A:	.long	BSC_BASE + 0x04
+CS2BCR_A:	.long	BSC_BASE + 0x08
+CS3BCR_A:	.long	BSC_BASE + 0x0C
+CS4BCR_A:	.long	BSC_BASE + 0x10
+CS5ABCR_A:	.long	BSC_BASE + 0x14
+CS5BBCR_A:	.long	BSC_BASE + 0x18
+CS6ABCR_A:	.long	BSC_BASE + 0x1C
+CS6BBCR_A:	.long	BSC_BASE + 0x20
+CS0WCR_A:	.long	BSC_BASE + 0x24
+CS2WCR_A:	.long	BSC_BASE + 0x28
+CS3WCR_A:	.long	BSC_BASE + 0x2C
+CS4WCR_A:	.long	BSC_BASE + 0x30
+CS5AWCR_A:	.long	BSC_BASE + 0x34
+CS5BWCR_A:	.long	BSC_BASE + 0x38
+CS6AWCR_A:	.long	BSC_BASE + 0x3C
+CS6BWCR_A:	.long	BSC_BASE + 0x40
+SDCR_A:		.long	BSC_BASE + 0x44
+RTCSR_A:	.long	BSC_BASE + 0x48
+RTCNT_A:	.long	BSC_BASE + 0x4C
+RTCOR_A:	.long	BSC_BASE + 0x50
+SDMR3_A:	.long	BSC_BASE + 0x58C0
+
+CMNCR_D:	.long	0x00000010
+CS0BCR_D:	.long	0x36DB0400
+CS2BCR_D:	.long	0x36DB0400
+CS3BCR_D:	.long	0x36DB4600
+CS4BCR_D:	.long	0x36DB0400
+CS5ABCR_D:	.long	0x36DB0400
+CS5BBCR_D:	.long	0x36DB0200
+CS6ABCR_D:	.long	0x36DB0400
+CS6BBCR_D:	.long	0x36DB0400
+CS0WCR_D:	.long	0x00000B01
+CS2WCR_D:	.long	0x00000500
+CS3WCR_D:	.long	0x00006D1B
+CS4WCR_D:	.long	0x00000500
+CS5AWCR_D:	.long	0x00000500
+CS5BWCR_D:	.long	0x00000500
+CS6AWCR_D:	.long	0x00000500
+CS6BWCR_D:	.long	0x00000500
+SDCR_D1:	.long	0x00000011
+RTCSR_D:	.long	0xA55A0010
+RTCNT_D:	.long	0xA55A001F
+RTCOR_D:	.long	0xA55A001F
+SDMR3_D:	.word	0x0000
+.align 2
+SDCR_D2:	.long	0x00000811
+
+#define PFC_BASE	0xA4050100
+PCCR_A:		.long	PFC_BASE + 0x04
+PDCR_A:		.long	PFC_BASE + 0x06
+PECR_A:		.long	PFC_BASE + 0x08
+PGCR_A:		.long	PFC_BASE + 0x0C
+PHCR_A:		.long	PFC_BASE + 0x0E
+PPCR_A:		.long	PFC_BASE + 0x18
+PTCR_A:		.long	PFC_BASE + 0x1E
+PVCR_A:		.long	PFC_BASE + 0x22
+PSELA_A:	.long	PFC_BASE + 0x24
+
+PCCR_D:		.word	0x0000
+PDCR_D:		.word	0x0000
+PECR_D:		.word	0x0000
+PGCR_D:		.word	0x0000
+PHCR_D:		.word	0x0000
+PPCR_D:		.word	0x00AA
+PTCR_D:		.word	0x0280
+PVCR_D:		.word	0x0000
+PSELA_D:	.word	0x0000
+.align 2
+
+CCR_A:		.long	0xFFFFFFEC
+!CCR_D:		.long	0x0000000D
+CCR_D:		.long	0x0000000B
+
+LED_A:		.long	0xB6800000
+LED_D:		.long	0xFF
diff --git a/u-boot/board/ms7720se/ms7720se.c b/u-boot/board/ms7720se/ms7720se.c
new file mode 100644
index 0000000..ab7c338
--- /dev/null
+++ b/u-boot/board/ms7720se/ms7720se.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7720se/ms7720se.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LED_BASE	0xB0800000
+
+int checkboard(void)
+{
+	puts("BOARD: Hitachi UL MS7720SE\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+	outw(value & 0xFF, LED_BASE);
+}
diff --git a/u-boot/board/ms7722se/Makefile b/u-boot/board/ms7722se/Makefile
new file mode 100644
index 0000000..fc8ae21
--- /dev/null
+++ b/u-boot/board/ms7722se/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ms7722se.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ms7722se/lowlevel_init.S b/u-boot/board/ms7722se/lowlevel_init.S
new file mode 100644
index 0000000..1cb57e7
--- /dev/null
+++ b/u-boot/board/ms7722se/lowlevel_init.S
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	/*
+	 * Cache Control Register
+	 * Instruction Cache Invalidate
+	 */
+	write32	CCR_A, CCR_D
+
+	/*
+	 * Address of MMU Control Register
+	 * TI == TLB Invalidate bit
+	 */
+	write32	MMUCR_A, MMUCR_D
+
+	/* Address of Power Control Register 0 */
+	write32	MSTPCR0_A, MSTPCR0_D
+
+	/* Address of Power Control Register 2 */
+	write32	MSTPCR2_A, MSTPCR2_D
+
+	write16	SBSCR_A, SBSCR_D
+
+	write16	PSCR_A, PSCR_D
+
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+!	write16	RWTCSR_A, RWTCSR_D_1	/* 0xA507 -> timer_STOP/WDT_CLK=max */
+
+	/* 0xA4520000 (Watchdog Count Register) */
+	write16	RWTCNT_A, RWTCNT_D	/*0x5A00 -> Clear */
+
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+	write16	RWTCSR_A, RWTCSR_D_2	/* 0xA504 -> timer_STOP/CLK=500ms */
+
+	/* 0xA4150000 Frequency control register */
+	write32	FRQCR_A, FRQCR_D
+
+	write32	CCR_A, CCR_D_2
+
+bsc_init:
+
+	write16	PSELA_A, PSELA_D
+
+	write16	DRVCR_A, DRVCR_D
+
+	write16	PCCR_A, PCCR_D
+
+	write16	PECR_A, PECR_D
+
+	write16	PJCR_A, PJCR_D
+
+	write16	PXCR_A, PXCR_D
+
+	write32	CMNCR_A, CMNCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS2BCR_A, CS2BCR_D
+
+	write32	CS4BCR_A, CS4BCR_D
+
+	write32	CS5ABCR_A, CS5ABCR_D
+
+	write32	CS5BBCR_A, CS5BBCR_D
+
+	write32	CS6ABCR_A, CS6ABCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+	write32	CS2WCR_A, CS2WCR_D
+
+	write32	CS4WCR_A, CS4WCR_D
+
+	write32	CS5AWCR_A, CS5AWCR_D
+
+	write32	CS5BWCR_A, CS5BWCR_D
+
+	write32	CS6AWCR_A, CS6AWCR_D
+
+	! SDRAM initialization
+	write32	SDCR_A, SDCR_D
+
+	write32	SDWCR_A, SDWCR_D
+
+	write32	SDPCR_A, SDPCR_D
+
+	write32	RTCOR_A, RTCOR_D
+
+	write32	RTCSR_A, RTCSR_D
+
+	write8	SDMR3_A, SDMR3_D
+
+	! BL bit off (init = ON) (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	mov	#0, r0
+
+	.align	2
+
+CCR_A:		.long	CCR
+MMUCR_A:	.long	MMUCR
+MSTPCR0_A:	.long	MSTPCR0
+MSTPCR2_A:	.long	MSTPCR2
+SBSCR_A:	.long	SBSCR
+PSCR_A:		.long	PSCR
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+
+CCR_D:		.long	0x00000800
+CCR_D_2:	.long	0x00000103
+MMUCR_D:	.long	0x00000004
+MSTPCR0_D:	.long	0x00001001
+MSTPCR2_D:	.long	0xffffffff
+FRQCR_D:	.long	0x07022538
+
+PSELA_A:	.long	0xa405014E
+PSELA_D:	.word	0x0A10
+	.align 2
+
+DRVCR_A:	.long	0xa405018A
+DRVCR_D:	.word	0x0554
+	.align 2
+
+PCCR_A:		.long	0xa4050104
+PCCR_D:		.word	0x8800
+	.align 2
+
+PECR_A:		.long	0xa4050108
+PECR_D:		.word	0x0000
+	.align 2
+
+PJCR_A:		.long	0xa4050110
+PJCR_D:		.word	0x1000
+	.align 2
+
+PXCR_A:		.long	0xa4050148
+PXCR_D:		.word	0x0AAA
+	.align 2
+
+CMNCR_A:	.long	CMNCR
+CMNCR_D:	.long	0x00000013
+CS0BCR_A:	.long	CS0BCR		! Flash bank 1
+CS0BCR_D:	.long	0x24920400
+CS2BCR_A:	.long	CS2BCR		! SRAM
+CS2BCR_D:	.long	0x24920400
+CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
+CS4BCR_D:	.long	0x24920400
+CS5ABCR_A:	.long	CS5ABCR		! Ext slot
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_A:	.long	CS5BBCR		! USB controller
+CS5BBCR_D:	.long	0x24920400
+CS6ABCR_A:	.long	CS6ABCR		! Ethernet
+CS6ABCR_D:	.long	0x24920400
+
+CS0WCR_A:	.long	CS0WCR
+CS0WCR_D:	.long	0x00000300
+CS2WCR_A:	.long	CS2WCR
+CS2WCR_D:	.long	0x00000300
+CS4WCR_A:	.long	CS4WCR
+CS4WCR_D:	.long	0x00000300
+CS5AWCR_A:	.long	CS5AWCR
+CS5AWCR_D:	.long	0x00000300
+CS5BWCR_A:	.long	CS5BWCR
+CS5BWCR_D:	.long	0x00000300
+CS6AWCR_A:	.long	CS6AWCR
+CS6AWCR_D:	.long	0x00000300
+
+SDCR_A:		.long	SBSC_SDCR
+SDCR_D:		.long	0x00020809
+SDWCR_A:	.long	SBSC_SDWCR
+SDWCR_D:	.long	0x00164d0d
+SDPCR_A:	.long	SBSC_SDPCR
+SDPCR_D:	.long	0x00000087
+RTCOR_A:	.long	SBSC_RTCOR
+RTCOR_D:	.long	0xA55A0034
+RTCSR_A:	.long	SBSC_RTCSR
+RTCSR_D:	.long	0xA55A0010
+SDMR3_A:	.long	0xFE500180
+SDMR3_D:	.long	0x0
+
+	.align	1
+
+SBSCR_D:	.word	0x0040
+PSCR_D:		.word	0x0000
+RWTCSR_D_1:	.word	0xA507
+RWTCSR_D_2:	.word	0xA507
+RWTCNT_D:	.word	0x5A00
+	.align	2
+
+SR_MASK_D:	.long	0xEFFFFF0F
diff --git a/u-boot/board/ms7722se/ms7722se.c b/u-boot/board/ms7722se/ms7722se.c
new file mode 100644
index 0000000..4e67ac6
--- /dev/null
+++ b/u-boot/board/ms7722se/ms7722se.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/ms7722se.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LED_BASE	0xB0800000
+
+int checkboard(void)
+{
+	puts("BOARD: Hitachi UL MS7722SE\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Setup PTXMD[1:0] for /CS6A */
+	outw(inw(PXCR) & ~0xf000, PXCR);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+	writew(value & 0xFF, LED_BASE);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ms7750se/Makefile b/u-boot/board/ms7750se/Makefile
new file mode 100644
index 0000000..8f1b459
--- /dev/null
+++ b/u-boot/board/ms7750se/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ms7750se.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ms7750se/lowlevel_init.S b/u-boot/board/ms7750se/lowlevel_init.S
new file mode 100644
index 0000000..3041e64
--- /dev/null
+++ b/u-boot/board/ms7750se/lowlevel_init.S
@@ -0,0 +1,159 @@
+/*
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#ifdef CONFIG_CPU_SH7751
+#define BCR2_D_VALUE	0x2FFC		/* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE	0x02770771	/* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MARUBUN_PCCARD
+#define WCR2_D_VALUE	0xFFFE4FE7	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
+					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#else /* CONFIG_MARUBUN_PCCARD */
+#define WCR2_D_VALUE	0x7FFE4FE7	/* A6:3  A6B:7 A5:15 A5B:7 A4:15
+					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#endif /* CONFIG_MARUBUN_PCCARD */
+#define WCR3_D_VALUE	0x01777771	/* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+					   A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA50D		/* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS	0xFF940088	/* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE	0x100901B4	/* SDRAM 32-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE	0x500901B4	/* Same w/MRSET now 1 (mode reg cmd) */
+#else /* CONFIG_CPU_SH7751 */
+#define BCR2_D_VALUE	0x2E3C		/* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE	0x02720777	/* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE	0xFFFE4FFF	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
+					   A3:2  A2:15 A1:15 A0:15 A0B:7  */
+#define WCR3_D_VALUE	0x01717771	/* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+					   A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA510		/* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS	0xFF940110	/* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE	0x8801001C	/* SDRAM 64-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE	0xC801001C	/* Same w/MRSET now 1 (mode reg cmd) */
+#endif /* CONFIG_CPU_SH7751 */
+
+	.global lowlevel_init
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write32	CCR_A, CCR_D_DISABLE
+
+init_bsc:
+	write16	FRQCR_A, FRQCR_D
+
+	write32	BCR1_A, BCR1_D
+
+	write16	BCR2_A, BCR2_D
+
+	write32	WCR1_A, WCR1_D
+
+	write32	WCR2_A, WCR2_D
+
+	write32	WCR3_A, WCR3_D
+
+	write32	MCR_A, MCR_D1
+
+	/* Set SDRAM mode */
+	write8	SDMR3_A, SDMR3_D
+
+	! Do you need PCMCIA setting?
+	! If so, please add the lines here...
+
+	write16	RTCNT_A, RTCNT_D
+
+	write16	RTCOR_A, RTCOR_D
+
+	write16	RTCSR_A, RTCSR_D
+
+	write16	RFCR_A, RFCR_D
+
+	/* Wait DRAM refresh 30 times */
+	mov	#30, r3
+1:
+	mov.w	@r1, r0
+	extu.w	r0, r2
+	cmp/hi	r3, r2
+	bf	1b
+
+	write32	MCR_A, MCR_D2
+
+	/* Set SDRAM mode */
+	write8	SDMR3_A, SDMR3_D
+
+	rts
+	nop
+
+	.align	2
+
+CCR_A:		 .long	CCR
+CCR_D_DISABLE:	.long	0x0808
+FRQCR_A:	.long	FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_TYPE_R
+		.word	0x0e1a	/* 12:3:3 */
+#else	/* CONFIG_CPU_TYPE_R */
+#ifdef CONFIG_GOOD_SESH4
+		.word	0x00e13	/* 6:2:1 */
+#else
+		.word	0x00e23	/* 6:1:1 */
+#endif
+.align 2
+#endif	/* CONFIG_CPU_TYPE_R */
+
+BCR1_A:		.long	BCR1
+BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
+BCR2_A:		.long	BCR2
+BCR2_D:		.long	BCR2_D_VALUE	/* Bus width settings */
+WCR1_A:		.long	WCR1
+WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
+WCR2_A:		.long	WCR2
+WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
+WCR3_A:		.long	WCR3
+WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
+RTCSR_A:	.long	RTCSR
+RTCSR_D:	.word	0xA518		/* RTCSR Write Code A5h Data 18h */
+.align 2
+RTCNT_A:	.long	RTCNT
+RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
+.align 2
+RTCOR_A:	.long	RTCOR
+RTCOR_D:	.word	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+.align 2
+SDMR3_A:	.long	SDMR3_ADDRESS
+SDMR3_D:	.long	0x00
+MCR_A:		.long	MCR
+MCR_D1:		.long	MCR_D1_VALUE
+MCR_D2:		.long	MCR_D2_VALUE
+RFCR_A:		.long	RFCR
+RFCR_D:		.word	0xA400		/* RFCR Write Code A4h Data 00h */
+.align 2
diff --git a/u-boot/board/ms7750se/ms7750se.c b/u-boot/board/ms7750se/ms7750se.c
new file mode 100644
index 0000000..9370af3
--- /dev/null
+++ b/u-boot/board/ms7750se/ms7750se.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
diff --git a/u-boot/board/muas3001/Makefile b/u-boot/board/muas3001/Makefile
new file mode 100644
index 0000000..f219cf9
--- /dev/null
+++ b/u-boot/board/muas3001/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/muas3001/muas3001.c b/u-boot/board/muas3001/muas3001.c
new file mode 100644
index 0000000..e0a7f32
--- /dev/null
+++ b/u-boot/board/muas3001/muas3001.c
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { 0,          0,   0,   0,   0,   0 }, /* PA31            */
+	/* PA30 */ { 0,          0,   0,   0,   0,   0 }, /* PA30            */
+	/* PA29 */ { 1,          1,   1,   1,   0,   0 }, /* FCC1 TXER */
+	/* PA28 */ { 1,          1,   1,   1,   0,   0 }, /* FCC1 TXEN */
+	/* PA27 */ { 1,          1,   1,   0,   0,   0 }, /* FCC1 RXDV */
+	/* PA26 */ { 1,          1,   1,   0,   0,   0 }, /* FCC1 RXER */
+	/* PA25 */ { 1,          0,   0,   1,   0,   0 }, /* ETH_PWRDWN      */
+	/* PA24 */ { 1,          0,   0,   1,   0,   1 }, /* ETH_RESET       */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
+	/* PA21 */ { 1,          1,   0,   1,   0,   0 }, /* FCC1 TXD3 */
+	/* PA20 */ { 1,          1,   0,   1,   0,   0 }, /* FCC1 TXD2 */
+	/* PA19 */ { 1,          1,   0,   1,   0,   0 }, /* FCC1 TXD1 */
+	/* PA18 */ { 1,          1,   0,   1,   0,   0 }, /* FCC1 TXD0 */
+	/* PA17 */ { 1,          1,   0,   0,   0,   0 }, /* FCC1 RXD0 */
+	/* PA16 */ { 1,          1,   0,   0,   0,   0 }, /* FCC1 RXD1 */
+	/* PA15 */ { 1,          1,   0,   0,   0,   0 }, /* FCC1 RXD2 */
+	/* PA14 */ { 1,          1,   0,   0,   0,   0 }, /* FCC1 RXD3 */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 1,          0,   0,   1,   0,   0 }, /* ETH_SLEEP       */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 1,          0,   0,   1,   0,   0 }, /* MDIO            */
+	/* PA9  */ { 1,          0,   0,   1,   0,   0 }, /* MDC             */
+	/* PA8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { 0,          0,   0,   0,   0,   0 }, /* PB31            */
+	/* PB30 */ { 0,          0,   0,   0,   0,   0 }, /* PB30            */
+	/* PB29 */ { 0,          0,   0,   0,   0,   0 }, /* PB29            */
+	/* PB28 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+	/* PB27 */ { 0,          0,   0,   0,   0,   0 }, /* PB27            */
+	/* PB26 */ { 0,          0,   0,   0,   0,   0 }, /* PB26            */
+	/* PB25 */ { 0,          0,   0,   0,   0,   0 }, /* PB25            */
+	/* PB24 */ { 0,          0,   0,   0,   0,   0 }, /* PB24            */
+	/* PB23 */ { 0,          0,   0,   0,   0,   0 }, /* PB23            */
+	/* PB22 */ { 0,          0,   0,   0,   0,   0 }, /* PB22            */
+	/* PB21 */ { 0,          0,   0,   0,   0,   0 }, /* PB21            */
+	/* PB20 */ { 0,          0,   0,   0,   0,   0 }, /* PB20            */
+	/* PB19 */ { 0,          0,   0,   0,   0,   0 }, /* PB19            */
+	/* PB18 */ { 0,          0,   0,   0,   0,   0 }, /* PB18            */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 RxD        */
+	/* PB14 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 RxD        */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 1,          1,   1,   1,   0,   0 }, /* SCC2 TxD        */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 1,          1,   1,   1,   0,   0 }, /* SCC3 TxD        */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 1,          1,   1,   1,   0,   0 }, /* Timer1 OUT      */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22            */
+	/* PC21 */ { 1,          1,   0,   0,   0,   0 }, /* FCC RxCLK 11    */
+	/* PC20 */ { 1,          1,   0,   0,   0,   0 }, /* FCC TxCLK 12    */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
+	/* PC18 */ { 0,          0,   0,   0,   0,   0 }, /* PC18            */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 1,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 1,          0,   0,   1,   0,   0 }, /* TX OUTPUT SLEW1 */
+	/* PC11 */ { 1,          0,   0,   1,   0,   0 }, /* TX OUTPUT SLEW0 */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* SPA_TX_EN       */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8             */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5             */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4             */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30            */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: RXD       */
+	/* PD21 */ { 1,          1,   0,   1,   0,   0 }, /* SCC4: TXD       */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
+	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
+#else
+	/* PD15 */ { 1,          0,   0,   0,   1,   1 }, /* PD15            */
+	/* PD14 */ { 1,          0,   0,   1,   1,   1 }, /* PD14            */
+#endif
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size ((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	long psize;
+#ifndef CONFIG_SYS_RAMBOOT
+	long sizelittle, sizebig;
+#endif
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	if (sizelittle < sizebig) {
+		psize = sizebig;
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int checkboard (void)
+{
+	puts ("Board: MUAS3001\n");
+
+	return 0;
+}
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r (void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+	int ret, nodeoffset = 0;
+	ulong flash_data[4] = {0};
+	ulong	speed = 0;
+
+	/* update Flash addr, size */
+	flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+	flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
+	nodeoffset = fdt_path_offset (blob, "/localbus");
+	if (nodeoffset >= 0) {
+		ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
+					sizeof (flash_data));
+	if (ret < 0)
+		printf ("ft_blob_update): cannot set /localbus/ranges "
+			"property err:%s\n", fdt_strerror(ret));
+	} else {
+		/* memory node is required in dts */
+		printf ("ft_blob_update(): cannot find /localbus node "
+			"err:%s\n", fdt_strerror (nodeoffset));
+	}
+
+	/* baudrate */
+	nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial");
+	if (nodeoffset >= 0) {
+		speed = cpu_to_be32 (bd->bi_baudrate);
+		ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed,
+					sizeof (unsigned long));
+	if (ret < 0)
+		printf ("ft_blob_update): cannot set /soc/cpm/serial/current-speed "
+			"property err:%s\n", fdt_strerror (ret));
+	} else {
+		/* baudrate is required in dts */
+		printf ("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node "
+			"err:%s\n", fdt_strerror (nodeoffset));
+	}
+}
+
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+	ft_blob_update (blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/u-boot/board/munices/Makefile b/u-boot/board/munices/Makefile
new file mode 100644
index 0000000..5c7f947
--- /dev/null
+++ b/u-boot/board/munices/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/munices/mt48lc16m16a2-75.h b/u-boot/board/munices/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/munices/mt48lc16m16a2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/munices/munices.c b/u-boot/board/munices/munices.c
new file mode 100644
index 0000000..c1207f1
--- /dev/null
+++ b/u-boot/board/munices/munices.c
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include "mt48lc16m16a2-75.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR && SDRAM_TAPDELAY
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	sdram_start(1);
+	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: MUNICes\n");
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/u-boot/board/munices/u-boot.lds b/u-boot/board/munices/u-boot.lds
new file mode 100644
index 0000000..4e27bc9
--- /dev/null
+++ b/u-boot/board/munices/u-boot.lds
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.got1)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/musenki/Makefile b/u-boot/board/musenki/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/musenki/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/musenki/README b/u-boot/board/musenki/README
new file mode 100644
index 0000000..084ab54
--- /dev/null
+++ b/u-boot/board/musenki/README
@@ -0,0 +1,298 @@
+U-Boot for a Musenki M-3/M-1 board
+---------------------------
+
+Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each.
+
+In board's notation, bank 0 is the one at the address of 0xFF800000
+and bank 1 is the one at the address of 0xFF000000.
+
+On power-up the processor jumps to the address of 0xFFF00100, the last
+megabyte of the bank 0 of flash.
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0xFFF00000.  The environment space is located in flash separately from
+U-Boot, at the address of 0xFF800000.
+
+There is a Davicom 9102A on-board, but I don't have it working yet.
+
+U-Boot test results
+--------------------
+
+x.x Operation on all available serial consoles
+
+x.x.x CONFIG_CONS_INDEX 1
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> help
+base    - print or set address offset
+bdinfo  - print Board Info structure
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+cmp     - memory compare
+coninfo - print console devices and informations
+cp      - memory copy
+crc32   - checksum calculation
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+iminfo  - print header information for application image
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loop    - infinite loop on address range
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+source  - run script from memory
+tftpboot- boot image via network using TFTP protocol
+	       and env variables ipaddr and serverip
+version - print monitor version
+?       - alias for 'help'
+
+
+x.x.x CONFIG_CONS_INDEX 2
+
+**** NOT TESTED ****
+
+x.x Flash Driver Operation
+
+
+Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=>
+=> md ff800000
+ff800000: 46989bf8 626f6f74 636d643d 626f6f74    F...bootcmd=boot
+ff800010: 6d204646 38323030 30300062 6f6f7464    m FF820000.bootd
+ff800020: 656c6179 3d350062 61756472 6174653d    elay=5.baudrate=
+ff800030: 39363030 00636c6f 636b735f 696e5f6d    9600.clocks_in_m
+ff800040: 687a3d31 00737464 696e3d73 65726961    hz=1.stdin=seria
+ff800050: 6c007374 646f7574 3d736572 69616c00    l.stdout=serial.
+ff800060: 73746465 72723d73 65726961 6c006970    stderr=serial.ip
+ff800070: 61646472 3d313932 2e313638 2e302e34    addr=192.168.0.4
+ff800080: 32007365 72766572 69703d31 39322e31    2.serverip=192.1
+ff800090: 36382e30 2e380000 00000000 00000000    68.0.8..........
+ff8000a0: 00000000 00000000 00000000 00000000    ................
+ff8000b0: 00000000 00000000 00000000 00000000    ................
+ff8000c0: 00000000 00000000 00000000 00000000    ................
+ff8000d0: 00000000 00000000 00000000 00000000    ................
+ff8000e0: 00000000 00000000 00000000 00000000    ................
+ff8000f0: 00000000 00000000 00000000 00000000    ................
+=> protect off ff800000 ff81ffff
+Un-Protected 1 sectors
+=> erase ff800000 ff81ffff
+Erase Flash from 0xff800000 to 0xff81ffff
+ done
+Erased 1 sectors
+=> md ff800000
+ff800000: ffffffff ffffffff ffffffff ffffffff    ................
+ff800010: ffffffff ffffffff ffffffff ffffffff    ................
+ff800020: ffffffff ffffffff ffffffff ffffffff    ................
+ff800030: ffffffff ffffffff ffffffff ffffffff    ................
+ff800040: ffffffff ffffffff ffffffff ffffffff    ................
+ff800050: ffffffff ffffffff ffffffff ffffffff    ................
+ff800060: ffffffff ffffffff ffffffff ffffffff    ................
+ff800070: ffffffff ffffffff ffffffff ffffffff    ................
+ff800080: ffffffff ffffffff ffffffff ffffffff    ................
+ff800090: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000f0: ffffffff ffffffff ffffffff ffffffff    ................
+
+x.x.x Information
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> flinfo
+
+Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32)
+  Size: 4 MB in 32 Sectors
+  Sector Start Addresses:
+    FF800000 (RO) FF820000      FF840000      FF860000      FF880000
+    FF8A0000      FF8C0000      FF8E0000      FF900000      FF920000
+    FF940000      FF960000      FF980000      FF9A0000      FF9C0000
+    FF9E0000      FFA00000      FFA20000      FFA40000      FFA60000
+    FFA80000      FFAA0000      FFAC0000      FFAE0000      FFB00000
+    FFB20000      FFB40000      FFB60000      FFB80000      FFBA0000
+    FFBC0000      FFBE0000
+
+Bank # 2: missing or unknown FLASH type
+=>
+
+
+x.x.x Flash Programming
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=> protect off ff800000 ff81ffff
+Un-Protected 1 sectors
+=> cp 0 ff800000 20
+Copy to Flash... done
+=> md ff800000
+ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc    7.3.3.3L3.1.3.5.
+ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc    3...0.....3.1.6.
+ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec    3.;.1.3.....3.3.
+ff800030: 234c33ec 32cc22cc 33883bdc 534433cc    #L3.2.".3.;.SD3.
+ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc    3.0.1.2.3.3.3.3.
+ff800050: 33cc13dc 334c534c b1c433d8 128c13cc    3...3LSL..3.....
+ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc    7.6.3.3.......w.
+ff800070: 314c0adc 139c30ed 33cc334c 33c833ec    1L....0.3.3L3.3.
+ff800080: ffffffff ffffffff ffffffff ffffffff    ................
+ff800090: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000f0: ffffffff ffffffff ffffffff ffffffff    ................
+
+
+x.x.x Storage of environment variables in flash
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> printenv
+bootcmd=bootm FF820000
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 106/16380 bytes
+=> setenv myvar 1234
+=> saveenv
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=> reset
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> printenv
+bootcmd=bootm FF820000
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+myvar=1234
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 117/16380 bytes
+
+x.x Image Download and run over serial port
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> loads
+## Ready for S-Record download ...
+
+## First Load Addr = 0x00040000
+## Last  Load Addr = 0x00050177
+## Total Size      = 0x00010178 = 65912 Bytes
+## Start Addr      = 0x00040004
+=> go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+
+
+x.x Image download and run over ethernet interface
+
+untested (not working yet, actually)
diff --git a/u-boot/board/musenki/flash.c b/u-boot/board/musenki/flash.c
new file mode 100644
index 0000000..40965be
--- /dev/null
+++ b/u-boot/board/musenki/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, uchar *dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*
+ * don't ask.  its stupid, but more than one soul has had to live with this mistake
+ * "swaptab[i]" is the value of "i" with the bits reversed.
+ */
+
+#define  MUSENKI_BROKEN_FLASH 1
+
+#ifdef MUSENKI_BROKEN_FLASH
+unsigned char swaptab[256] = {
+  0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+  0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+  0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+  0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+  0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+  0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+  0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+  0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+  0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+  0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+  0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+  0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+  0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+  0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+  0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+  0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+  0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+  0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+  0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+  0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+  0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+  0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+  0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+  0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+  0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+  0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+  0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+  0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+  0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+  0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+  0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+  0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
+};
+
+#define BS(b)     (swaptab[b])
+
+#else
+
+#define BS(b)     (b)
+
+#endif
+
+#define BYTEME(x) ((x) & 0xFF)
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE1_PRELIM);
+	size_b1 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len);
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE);
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		flash_info[1].size = size_b1;
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += 0x00020000;		/* 128k per bank */
+	    }
+	    return;
+
+	default:
+	    printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
+	    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320J3A (32Mbit = 128K x 32)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64Mbit = 128K x 64)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128J3A (128Mbit = 128K x 128)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+	vu_char manuf, device;
+
+	addr[0] = BS(0x90);
+	manuf = BS(addr[0]);
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf);
+
+	switch (manuf) {
+	case BYTEME(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case BYTEME(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case BYTEME(SST_MANUFACT):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case BYTEME(STM_MANUFACT):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case BYTEME(INTEL_MANUFACT):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = BS(0xFF);		/* restore read mode, (yes, BS is a NOP) */
+		return 0;			/* no or unknown flash	*/
+	}
+
+	device = BS(addr[2]);			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device);
+
+	switch (device) {
+	case BYTEME(INTEL_ID_28F320J3A):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* =>  4 MB		*/
+
+	case BYTEME(INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case BYTEME(INTEL_ID_28F128J3A):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = BS(0xFF);		/* restore read mode (yes, a NOP) */
+		return 0;			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = BS(0xFF);		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_char *addr = (vu_char *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = BS(0x50);	/* clear status register */
+			*addr = BS(0x20);	/* erase setup */
+			*addr = BS(0xD0);	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = BS(0xB0); /* suspend erase	  */
+					*addr = BS(0xFF); /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = BS(0xFF);	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	1	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	uchar *wp = (uchar *)addr;
+	int rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	while (cnt > 0) {
+		if ((rc = write_data(info, wp, *src)) != 0) {
+			return rc;
+		}
+		wp++;
+		src++;
+		cnt--;
+	}
+
+	return cnt;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, uchar *dest, uchar data)
+{
+	vu_char *addr = (vu_char *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((BS(*addr) & data) != data) {
+		return 2;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = BS(0x40);		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	start = get_timer (0);
+
+	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = BS(0xFF);	/* restore read mode */
+			return 1;
+		}
+	}
+
+	*addr = BS(0xFF);	/* restore read mode */
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/musenki/musenki.c b/u-boot/board/musenki/musenki.c
new file mode 100644
index 0000000..30b95ce
--- /dev/null
+++ b/u-boot/board/musenki/musenki.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <netdev.h>
+
+int checkboard (void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+
+}
+
+#if 0	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+#if 0
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  0x0, 0x0, 0x0, /* unknown eth0 divice */
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  0x0, 0x0, 0x0, /* unknown eth1 device */
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+#endif
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/mvblue/Makefile b/u-boot/board/mvblue/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/mvblue/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mvblue/flash.c b/u-boot/board/mvblue/flash.c
new file mode 100644
index 0000000..2d6acf5
--- /dev/null
+++ b/u-boot/board/mvblue/flash.c
@@ -0,0 +1,583 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2001-2003
+ *
+ * Changes for MATRIX Vision mvBLUE devices
+ * MATRIX Vision GmbH / hg,as info@matrix-vision.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+
+#if 0
+	#define mvdebug(p) printf ##p
+#else
+	#define mvdebug(p)
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define FLASH_BUS_WIDTH		8
+
+#if (FLASH_BUS_WIDTH==32)
+	#define FLASH_DATA_MASK 0xffffffff
+	#define FLASH_SHIFT 1
+	#define FDT	vu_long
+#elif (FLASH_BUS_WIDTH==16)
+	#define FLASH_DATA_MASK 0xff
+	#define FLASH_SHIFT 0
+	#define FDT	vu_short
+#elif (FLASH_BUS_WIDTH==8)
+	#define FLASH_DATA_MASK 0xff
+	#define FLASH_SHIFT 0
+	#define FDT	vu_char
+#else
+	#error FLASH_BUS_WIDTH undefined
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *address, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)0xffc00000, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH : Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	flash_get_offsets (0xffc00000, &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	/* monitor protection OFF by default */
+	flash_protect ( FLAG_PROTECT_CLEAR, 0xffc00000, 0x2000, flash_info );
+
+	return size_b0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE)
+	{	/* bottom boot sector types - these are the useful ones! */
+		/* set sector offsets for bottom boot block type */
+		if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B)
+		{	/* AMDLV320B has 8 x 8k bottom boot sectors */
+			for (i = 0; i < 8; i++)												/* +8k		*/
+				info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+			for (; i < info->sector_count; i++)									/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT);
+		}
+		else
+		{	/* other types have 4 bottom boot sectors (16,8,8,32) */
+			i = 0;
+			info->start[i++] = base +  0x00000000;								/* -		*/
+			info->start[i++] = base + (0x00004000 << FLASH_SHIFT);				/* +16k		*/
+			info->start[i++] = base + (0x00006000 << FLASH_SHIFT);				/* +8k		*/
+			info->start[i++] = base + (0x00008000 << FLASH_SHIFT);				/* +8k		*/
+			info->start[i++] = base + (0x00010000 << FLASH_SHIFT);				/* +32k		*/
+			for (; i < info->sector_count; i++)									/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT);
+		}
+	}
+	else
+	{	/* top boot sector types - not so useful */
+		/* set sector offsets for top boot block type */
+		if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T)
+		{	/* AMDLV320T has 8 x 8k top boot sectors */
+			for (i = 0; i < info->sector_count - 8; i++)						/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+			for (; i < info->sector_count; i++)									/* +8k		*/
+				info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+		}
+		else
+		{	/* other types have 4 top boot sectors (32,8,8,16) */
+			for (i = 0; i < info->sector_count - 4; i++)						/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+
+			info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT);	/* -32k		*/
+			info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT);	/* -8k		*/
+			info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT);	/* -8k		*/
+			info->start[i]   = base + info->size - (0x00004000 << FLASH_SHIFT);	/* -16k		*/
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");	break;
+	case FLASH_MAN_STM:	printf ("ST ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_STMW320DB:	printf ("M29W320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_STMW320DT:	printf ("M29W320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#define	AMD_ID_LV160T_MVS	(AMD_ID_LV160T & FLASH_DATA_MASK)
+#define AMD_ID_LV160B_MVS	(AMD_ID_LV160B & FLASH_DATA_MASK)
+#define AMD_ID_LV320T_MVS	(AMD_ID_LV320T & FLASH_DATA_MASK)
+#define AMD_ID_LV320B_MVS	(AMD_ID_LV320B & FLASH_DATA_MASK)
+#define STM_ID_W320DT_MVS	(STM_ID_29W320DT & FLASH_DATA_MASK)
+#define STM_ID_W320DB_MVS	(STM_ID_29W320DB & FLASH_DATA_MASK)
+#define AMD_MANUFACT_MVS	(AMD_MANUFACT  & FLASH_DATA_MASK)
+#define FUJ_MANUFACT_MVS	(FUJ_MANUFACT  & FLASH_DATA_MASK)
+#define STM_MANUFACT_MVS	(STM_MANUFACT  & FLASH_DATA_MASK)
+
+#if (FLASH_BUS_WIDTH >= 16)
+	#define AUTOSELECT_ADDR1	0x0555
+	#define AUTOSELECT_ADDR2	0x02AA
+	#define AUTOSELECT_ADDR3	AUTOSELECT_ADDR1
+#else
+	#define AUTOSELECT_ADDR1	0x0AAA
+	#define AUTOSELECT_ADDR2	0x0555
+	#define AUTOSELECT_ADDR3	AUTOSELECT_ADDR1
+#endif
+
+#define AUTOSELECT_DATA1	(0x00AA00AA & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA2	(0x00550055 & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA3	(0x00900090 & FLASH_DATA_MASK)
+
+#define RESET_BANK_DATA		(0x00F000F0 & FLASH_DATA_MASK)
+
+
+static ulong flash_get_size (vu_long *address, flash_info_t *info)
+{
+	short i;
+	FDT value;
+	FDT *addr = (FDT *)address;
+
+	ulong base = (ulong)address;
+	addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1;
+	addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2;
+	addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3;
+	__asm__ __volatile__("sync");
+
+	udelay(180);
+
+	value = addr[0];			/* manufacturer ID	*/
+	switch (value) {
+	case AMD_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case STM_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+#if (FLASH_BUS_WIDTH >= 16)
+	value = addr[1];			/* device ID		*/
+#else
+	value = addr[2];			/* device ID		*/
+#endif
+
+	switch (value) {
+	case AMD_ID_LV160T_MVS:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 37;
+		info->size = (0x00200000 << FLASH_SHIFT);
+		break;				/* => 2 or 4 MB		*/
+
+	case AMD_ID_LV160B_MVS:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 37;
+		info->size = (0x00200000 << FLASH_SHIFT);
+		break;				/* => 2 or 4 MB		*/
+
+	case AMD_ID_LV320T_MVS:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8 MB		*/
+
+	case AMD_ID_LV320B_MVS:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8MB		*/
+
+	case STM_ID_W320DT_MVS:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8 MB		*/
+
+	case STM_ID_W320DB_MVS:
+		info->flash_id += FLASH_STMW320DB;
+		info->sector_count = 67;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	flash_get_offsets (base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (FDT *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (FDT *)info->start[0];
+		*addr = RESET_BANK_DATA;	/* reset bank */
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+#if (FLASH_BUS_WIDTH >= 16)
+	#define ERASE_ADDR1 0x0555
+	#define ERASE_ADDR2 0x02AA
+#else
+	#define ERASE_ADDR1 0x0AAA
+	#define ERASE_ADDR2 0x0555
+#endif
+
+#define ERASE_ADDR3 ERASE_ADDR1
+#define ERASE_ADDR4 ERASE_ADDR1
+#define ERASE_ADDR5 ERASE_ADDR2
+
+#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK)
+#define ERASE_DATA4 ERASE_DATA1
+#define ERASE_DATA5 ERASE_DATA2
+
+#define ERASE_SECTOR_DATA	(0x00300030 & FLASH_DATA_MASK)
+#define ERASE_CHIP_DATA		(0x00100010 & FLASH_DATA_MASK)
+#define ERASE_CONFIRM_DATA	(0x00800080 & FLASH_DATA_MASK)
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FDT *addr = (FDT *)(info->start[0]);
+
+	int prot, sect, l_sect, flag;
+	ulong start, now, last;
+
+	__asm__ __volatile__ ("sync");
+	addr[0] = 0xf0;
+	udelay(1000);
+
+	printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] );
+	printf("             last  = %d @ 0x%08lx\n", s_last , info->start[s_last ] );
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[ERASE_ADDR1] = ERASE_DATA1;
+	addr[ERASE_ADDR2] = ERASE_DATA2;
+	addr[ERASE_ADDR3] = ERASE_DATA3;
+	addr[ERASE_ADDR4] = ERASE_DATA4;
+	addr[ERASE_ADDR5] = ERASE_DATA5;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {
+			addr = (FDT *)(info->start[sect]);
+			addr[0] = ERASE_SECTOR_DATA;
+			l_sect = sect;
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (FDT *)(info->start[l_sect]);
+
+	while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#define BUFF_INC 4
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt));
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt));
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<BUFF_INC && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<BUFF_INC; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += BUFF_INC;
+	}
+
+	/*
+	 * handle (half)word aligned part
+	 */
+	mvdebug ((" handle word aligned part (cnt = 0x%08lx)\n", cnt));
+	while (cnt >= BUFF_INC) {
+		data = 0;
+		for (i=0; i<BUFF_INC; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += BUFF_INC;
+		cnt -= BUFF_INC;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	mvdebug ((" handle unaligned tail bytes (cnt = 0x%08lx)\n", cnt));
+	data = 0;
+	for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<BUFF_INC; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+#if (FLASH_BUS_WIDTH >= 16)
+	#define WRITE_ADDR1 0x0555
+	#define WRITE_ADDR2 0x02AA
+#else
+	#define WRITE_ADDR1 0x0AAA
+	#define WRITE_ADDR2 0x0555
+	#define WRITE_ADDR3 WRITE_ADDR1
+#endif
+
+#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK)
+
+#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_char (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		printf(" *** ERROR: Flash not erased !\n");
+		return (2);
+	}
+	flag = disable_interrupts();
+
+	addr[WRITE_ADDR1] = WRITE_DATA1;
+	addr[WRITE_ADDR2] = WRITE_DATA2;
+	addr[WRITE_ADDR3] = WRITE_DATA3;
+	*((vu_char *)dest) = data;
+
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	addr = (vu_char *)dest;
+	while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			printf(" *** ERROR: Flash write timeout !");
+			return (1);
+		}
+	}
+	mvdebug (("-write_byte\n"));
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	int i,
+		result = 0;
+
+	mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest));
+	for ( i=0; (i < 4) && (result == 0); i++, dest+=1 )
+		result = write_char (info, dest, (data >> (8*(3-i))) & 0xff );
+	mvdebug (("-write_word\n"));
+	return result;
+}
+/*---------------------------------------------------------------- */
diff --git a/u-boot/board/mvblue/mvblue.c b/u-boot/board/mvblue/mvblue.c
new file mode 100644
index 0000000..69abb06
--- /dev/null
+++ b/u-boot/board/mvblue/mvblue.c
@@ -0,0 +1,254 @@
+/*
+ * GNU General Public License for more details.
+ *
+ * MATRIX Vision GmbH / June 2002-Nov 2003
+ * Andre Schwarz
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <netdev.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_BoardType (void);
+
+#define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
+						      | ((d&0x1f)<<11) \
+						      | ((f&0x7)<<7)   \
+						      | (r&0xfc) )
+
+int mv_pci_read (int bus, int dev, int func, int reg)
+{
+	*(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
+	asm ("sync");
+	return cpu_to_le32 (*(u32 *) (0xfee00cfc));
+}
+
+u32 get_BoardType ()
+{
+	return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
+}
+
+void init_2nd_DUART (void)
+{
+	NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE;
+
+	*(u8 *) (0xfc004511) = 0x1;
+	NS16550_init (console, clock_divisor);
+}
+void hw_watchdog_reset (void)
+{
+	if (get_BoardType () == 0) {
+		*(u32 *) (0xff000005) = 0;
+		asm ("sync");
+	}
+}
+int checkboard (void)
+{
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+	u32 BoardType = get_BoardType ();
+	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
+	char *p;
+	bd_t *bd = gd->bd;
+
+	hw_watchdog_reset ();
+
+	printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
+	printf ("       Found %s running at %s MHz memory clock.\n",
+		BoardName[BoardType], strmhz (buf, busfreq));
+
+	init_2nd_DUART ();
+
+	if ((p = getenv ("console_nr")) != NULL) {
+		unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
+
+		bd->bi_baudrate &= ~3;
+		bd->bi_baudrate |= con_nr & 3;
+	}
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1,  mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+	char *ptr;
+
+	/* DHCP vendor-class-identifier = 60 */
+	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* my DHCP_CLIENT_IDENTIFIER = 61 */
+	if ((ptr = getenv ("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	return e;
+}
+
+u8 *dhcp_vendorex_proc (u8 * popt)
+{
+	return NULL;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Initialize PCI Devices
+ */
+#ifdef CONFIG_PCI
+void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
+{
+	u32 cnt;
+
+	printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
+		PCI_FUNC (dev));
+	for (cnt = 0; cnt < 6; cnt++)
+		pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
+					     0x0);
+	printf ("done\n");
+}
+
+void duart_setup (u32 base, u16 divisor)
+{
+	printf ("duart setup ...");
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07);
+	printf ("done\n");
+}
+
+void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
+					 pci_dev_t bridge, unsigned char irq)
+{
+	pci_dev_t d;
+	unsigned char bus;
+	unsigned short vendor, class;
+
+	pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
+	for (d = PCI_BDF (bus, 0, 0);
+	     d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
+			  PCI_MAX_PCI_FUNCTIONS - 1);
+	     d += PCI_BDF (0, 0, 1)) {
+		pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
+		if (vendor != 0xffff && vendor != 0x0000) {
+			pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
+						   &class);
+			if (class == PCI_CLASS_BRIDGE_PCI)
+				pci_mvblue_fixup_irq_behind_bridge (hose, d,
+								    irq);
+			else
+				pci_hose_write_config_byte (hose, d,
+							    PCI_INTERRUPT_LINE,
+							    irq);
+		}
+	}
+}
+
+#define MV_MAX_PCI_BUSSES	3
+#define SLOT0_IRQ	3
+#define SLOT1_IRQ	4
+void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line = 0xff;
+	unsigned short class;
+
+	if (PCI_BUS (dev) == 0) {
+		switch (PCI_DEV (dev)) {
+		case 0xd:
+			if (get_BoardType () == 0) {
+				line = 1;
+			} else
+				/* mvBL */
+				line = 2;
+			break;
+		case 0xe:
+			/* mvBB: IDE */
+			line = 2;
+			pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
+			break;
+		case 0xf:
+			/* mvBB: Slot0 (Grabber) */
+			pci_hose_read_config_word (hose, dev,
+						   PCI_CLASS_DEVICE, &class);
+			if (class == PCI_CLASS_BRIDGE_PCI) {
+				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
+								    SLOT0_IRQ);
+				line = 0xff;
+			} else
+				line = SLOT0_IRQ;
+			break;
+		case 0x10:
+			/* mvBB: Slot1 */
+			pci_hose_read_config_word (hose, dev,
+						   PCI_CLASS_DEVICE, &class);
+			if (class == PCI_CLASS_BRIDGE_PCI) {
+				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
+								    SLOT1_IRQ);
+				line = 0xff;
+			} else
+				line = SLOT1_IRQ;
+			break;
+		default:
+			printf ("***pci_scan: illegal dev = 0x%08x\n",
+				PCI_DEV (dev));
+			line = 0xff;
+			break;
+		}
+		pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
+					    line);
+	}
+}
+
+struct pci_controller hose = {
+	fixup_irq:pci_mvblue_fixup_irq
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
diff --git a/u-boot/board/mvblue/u-boot.lds b/u-boot/board/mvblue/u-boot.lds
new file mode 100644
index 0000000..ad06af0
--- /dev/null
+++ b/u-boot/board/mvblue/u-boot.lds
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2001-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/powerpc/cpu/mpc824x/start.o		(.text*)
+    lib/libgeneric.o				(.text*)
+    net/libnet.o				(.text*)
+    drivers/pci/libpci.o			(.text*)
+    arch/powerpc/cpu/mpc824x/libmpc824x.o	(.text*)
+    board/mvblue/libmvblue.o			(.text*)
+    arch/powerpc/lib/libpowerpc.o		(.text*)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv*)
+
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/mx1ads/Makefile b/u-boot/board/mx1ads/Makefile
new file mode 100644
index 0000000..20d7b86
--- /dev/null
+++ b/u-boot/board/mx1ads/Makefile
@@ -0,0 +1,55 @@
+#
+# board/mx1ads/Makefile
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx1ads.o syncflash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mx1ads/config.mk b/u-boot/board/mx1ads/config.mk
new file mode 100644
index 0000000..2bc5b15
--- /dev/null
+++ b/u-boot/board/mx1ads/config.mk
@@ -0,0 +1,25 @@
+#
+# board/mx1ads/config.mk
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CONFIG_SYS_TEXT_BASE = 0x08400000
diff --git a/u-boot/board/mx1ads/lowlevel_init.S b/u-boot/board/mx1ads/lowlevel_init.S
new file mode 100644
index 0000000..a7400b3
--- /dev/null
+++ b/u-boot/board/mx1ads/lowlevel_init.S
@@ -0,0 +1,81 @@
+/*
+ * board/mx1ads/lowlevel_init.S
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#define SDCTL0			0x221000
+#define SDCTL1			0x221004
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+/* memory controller init		*/
+
+	ldr  r1, =SDCTL0
+
+/*  Set Precharge Command		*/
+
+	ldr  r3, =0x92120200
+/*	ldr  r3, =0x92120251
+*/
+	str  r3, [r1]
+
+/* Issue Precharge All Commad		*/
+	ldr  r3, =0x8200000
+	ldr  r2, [r3]
+
+/* Set AutoRefresh Command		*/
+	ldr  r3, =0xA2120200
+	str  r3, [r1]
+
+/* Issue AutoRefresh Command		*/
+	ldr  r3, =0x8000000
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+
+/* Set Mode Register			*/
+	ldr  r3, =0xB2120200
+	str  r3, [r1]
+
+/* Issue Mode Register Command		*/
+	ldr  r3, =0x08111800	/* Mode Register Value		*/
+	ldr  r2, [r3]
+
+/* Set Normal Mode			*/
+	ldr  r3, =0x82124200
+	str  r3, [r1]
+
+/* everything is fine now		*/
+	mov	pc, lr
diff --git a/u-boot/board/mx1ads/mx1ads.c b/u-boot/board/mx1ads/mx1ads.c
new file mode 100644
index 0000000..f8ce210
--- /dev/null
+++ b/u-boot/board/mx1ads/mx1ads.c
@@ -0,0 +1,181 @@
+/*
+ * board/mx1ads/mx1ads.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+#if 0
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+void SetAsynchMode (void)
+{
+	__asm__ ("mrc p15,0,r0,c1,c0,0 \n"
+		 "mov r2, #0xC0000000 \n"
+		 "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
+}
+
+static u32 mc9328sid;
+
+int board_init (void)
+{
+	volatile unsigned int tmp;
+
+	mc9328sid = SIDR;
+
+	GPCR = 0x000003AB;	/* I/O pad driving strength     */
+
+	/*	MX1_CS1U	= 0x00000A00;	*/ /* SRAM initialization          */
+/*	MX1_CS1L	= 0x11110601;	*/
+
+	MPCTL0 = 0x04632410;	/* setting for 150 MHz MCU PLL CLK      */
+
+/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
+ * BCLK divider to 2 (i.e. BCLK to 48 MHz)
+ */
+	CSCR = 0xAF000403;
+
+	CSCR |= 0x00200000;	/* Trigger the restart bit(bit 21)      */
+	CSCR &= 0xFFFF7FFF;	/* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+
+/* setup cs4 for cs8900 ethernet */
+
+	CS4U = 0x00000F00;	/* Initialize CS4 for CS8900 ethernet   */
+	CS4L = 0x00001501;
+
+	GIUS (0) &= 0xFF3FFFFF;
+	GPR (0) &= 0xFF3FFFFF;
+
+	tmp = *(unsigned int *) (0x1500000C);
+	tmp = *(unsigned int *) (0x1500000C);
+
+	SetAsynchMode ();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
+
+	gd->bd->bi_boot_params = 0x08000100;	/* adress of boot parameters    */
+
+	icache_enable ();
+	dcache_enable ();
+
+/* set PERCLKs				*/
+	PCDR = 0x00000055;	/* set PERCLKS                          */
+
+/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
+ * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
+ * all sources selected as normal interrupt
+ */
+
+/*	MX1_INTTYPEH = 0;
+	MX1_INTTYPEL = 0;
+*/
+	return 0;
+}
+
+int board_late_init (void)
+{
+
+	setenv ("stdout", "serial");
+	setenv ("stderr", "serial");
+
+	switch (mc9328sid) {
+	case 0x0005901d:
+		printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
+			mc9328sid);
+		break;
+	case 0x04d4c01d:
+		printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
+			mc9328sid);
+		break;
+	case 0x00d4c01d:
+		printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
+			mc9328sid);
+		break;
+
+	default:
+		printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
+			mc9328sid);
+		break;
+	}
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/mx1ads/syncflash.c b/u-boot/board/mx1ads/syncflash.c
new file mode 100644
index 0000000..47f613c
--- /dev/null
+++ b/u-boot/board/mx1ads/syncflash.c
@@ -0,0 +1,322 @@
+/*
+ * board/mx1ads/syncflash.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
+
+typedef unsigned long * p_u32;
+
+/* 4Mx16x2 IAM=0 CSD1 */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*  Following Setting is for CSD1	*/
+#define SFCTL			0x00221004
+#define reg_SFCTL		__REG(SFCTL)
+
+#define SYNCFLASH_A10		(0x00100000)
+
+#define CMD_NORMAL		(0x81020300)			/* Normal Mode			*/
+#define CMD_PREC		(CMD_NORMAL + 0x10000000)	/* Precharge Command		*/
+#define CMD_AUTO		(CMD_NORMAL + 0x20000000)	/* Auto Refresh Command		*/
+#define CMD_LMR			(CMD_NORMAL + 0x30000000)	/* Load Mode Register Command	*/
+#define CMD_LCR			(CMD_NORMAL + 0x60000000)	/* LCR Command			*/
+#define CMD_PROGRAM		(CMD_NORMAL + 0x70000000)
+
+#define MODE_REG_VAL		(CONFIG_SYS_FLASH_BASE+0x0008CC00)	/* Cas Latency 3		*/
+
+/* LCR Command */
+#define LCR_READSTATUS		(0x0001C000)			/* 0x70				*/
+#define LCR_ERASE_CONFIRM	(0x00008000)			/* 0x20				*/
+#define LCR_ERASE_NVMODE	(0x0000C000)			/* 0x30				*/
+#define LCR_PROG_NVMODE		(0x00028000)			/* 0xA0				*/
+#define LCR_SR_CLEAR		(0x00014000)			/* 0x50				*/
+
+/* Get Status register			*/
+u32 SF_SR(void) {
+	u32 tmp,tmp1;
+
+	reg_SFCTL	= CMD_PROGRAM;
+	tmp		= __REG(CONFIG_SYS_FLASH_BASE);
+
+	reg_SFCTL	= CMD_NORMAL;
+
+	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode		*/
+	tmp1		= __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
+
+	return tmp;
+}
+
+/* check if SyncFlash is ready		*/
+u8 SF_Ready(void) {
+	u32 tmp;
+
+	tmp	= SF_SR();
+
+	if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
+		printf ("SyncFlash Error code %08x\n",tmp);
+	};
+
+	if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
+		printf ("SyncFlash Error code %08x\n",tmp);
+	};
+
+	if (tmp == 0x00800080)		/* Test Bit 7 of SR	*/
+		return 1;
+	else
+		return 0;
+}
+
+/* Issue the precharge all command		*/
+void SF_PrechargeAll(void) {
+
+	u32 tmp;
+
+	reg_SFCTL	= CMD_PREC;			/* Set Precharge Command	*/
+	tmp		= __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+}
+
+/* set SyncFlash to normal mode			*/
+void SF_Normal(void) {
+
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_NORMAL;
+}
+
+/* Erase SyncFlash				*/
+void SF_Erase(u32 RowAddress) {
+	u32 tmp;
+
+	reg_SFCTL	= CMD_NORMAL;
+	tmp		= __REG(RowAddress);
+
+	reg_SFCTL	= CMD_PREC;
+	tmp		= __REG(RowAddress);
+
+	reg_SFCTL	= CMD_LCR;			/* Set LCR mode		*/
+	__REG(RowAddress + LCR_ERASE_CONFIRM)	= 0;	/* Issue Erase Setup Command	*/
+
+	reg_SFCTL	= CMD_NORMAL;			/* return to Normal mode	*/
+	__REG(RowAddress)	= 0xD0D0D0D0;		/* Confirm			*/
+
+	while(!SF_Ready());
+}
+
+void SF_NvmodeErase(void) {
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
+	__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
+
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
+	__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm		*/
+
+	while(!SF_Ready());
+}
+
+void SF_NvmodeWrite(void) {
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
+	__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
+
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
+	__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0;	/* Confirm not needed	*/
+}
+
+/****************************************************************************************/
+
+ulong flash_init(void) {
+	int i, j;
+	u32 tmp;
+
+/* Turn on CSD1 for negating RESETSF of SyncFLash */
+
+	reg_SFCTL	|= 0x80000000;		/* enable CSD1 for SyncFlash		*/
+	udelay(200);
+
+	reg_SFCTL	= CMD_LMR;		/* Set Load Mode Register Command	*/
+	tmp		= __REG(MODE_REG_VAL);	/* Issue Load Mode Register Command	*/
+
+	SF_Normal();
+
+	i = 0;
+
+	flash_info[i].flash_id	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
+
+	flash_info[i].size	= FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+
+	for (j = 0; j < flash_info[i].sector_count; j++) {
+		flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
+	}
+
+	flash_protect(FLAG_PROTECT_SET,
+		CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		&flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		CONFIG_ENV_ADDR,
+		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		&flash_info[0]);
+
+	return FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t *info) {
+
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (FLASH_MAN_MT & FLASH_VENDMASK):
+			printf("Micron: ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
+			printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
+			break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses: ");
+
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+
+/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last))
+		return ERR_INVAL;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf("protected!\n");
+		return ERR_PROTECTED;
+	}
+/*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+	cflag = icache_status();
+	icache_disable();
+	iflag = disable_interrupts();
+
+/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+/* arm simple, non interrupt dependent timer */
+
+		reset_timer_masked();
+
+		SF_NvmodeErase();
+		SF_NvmodeWrite();
+
+		SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
+		SF_Normal();
+
+		printf("ok.\n");
+	}
+
+	if (ctrlc())
+		printf("User Interrupt!\n");
+
+	if (iflag)
+		enable_interrupts();
+
+	if (cflag)
+		icache_enable();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+	int i;
+
+	for(i = 0; i < cnt; i += 4) {
+
+		SF_PrechargeAll();
+
+		reg_SFCTL	= CMD_PROGRAM;		/* Enter SyncFlash Program mode */
+		__REG(addr + i) = __REG((u32)src  + i);
+
+		while(!SF_Ready());
+	}
+
+	SF_Normal();
+
+	return ERR_OK;
+}
diff --git a/u-boot/board/mx1fs2/Makefile b/u-boot/board/mx1fs2/Makefile
new file mode 100644
index 0000000..c55b695
--- /dev/null
+++ b/u-boot/board/mx1fs2/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx1fs2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/mx1fs2/config.mk b/u-boot/board/mx1fs2/config.mk
new file mode 100644
index 0000000..eb4d046
--- /dev/null
+++ b/u-boot/board/mx1fs2/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of IMX sources
+#
+# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+CONFIG_SYS_TEXT_BASE = 0x08f00000
diff --git a/u-boot/board/mx1fs2/flash.c b/u-boot/board/mx1fs2/flash.c
new file mode 100644
index 0000000..da4ebe6
--- /dev/null
+++ b/u-boot/board/mx1fs2/flash.c
@@ -0,0 +1,849 @@
+/*
+ * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) 2003 August Hoeraendl, Logotronic GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef CONFIG_FLASH_16BIT
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
+#define MAIN_SECT_SIZE  MX1FS2_FLASH_SECT_SIZE
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips   */
+
+/*
+ * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+#if 0
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+#endif
+static void flash_reset(flash_info_t * info);
+static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+#define write_word(in, de, da)   write_word_amd(in, de, da)
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t * info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+ulong
+flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+		    (FLASH_MAN_AMD & FLASH_VENDMASK) |
+		    (FLASH_AM640U & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = MX1FS2_FLASH_BASE;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_FLASH_BASE,
+		      CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
+		      &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_reset(flash_info_t * info)
+{
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector  */
+		int sect_size;	/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set sector offsets for bottom boot block type        */
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	}
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_BM:
+		printf("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt, bootletter, boottype);
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		printf(" %08lX%s", info->start[i],
+		       info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#if 0
+ulong
+flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW) 0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[1]) {
+
+		case (FPW) AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* => no or unknown flash */
+		}
+
+	flash_get_offsets((ulong) addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+#endif /* 0 */
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void
+flash_sync_real_protect(flash_info_t * info)
+{
+	FPWV *addr = (FPWV *) (info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW) 0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			 * D0 = 1 for each device if protected.
+			 * If at least one device is protected the sector is marked
+			 * protected, but mixed protected and  unprotected devices
+			 * within a sector should never happen.
+			 */
+			sect = (FPWV *) (info->start[i]);
+			info->protect[i] =
+			    (sect[2] & (FPW) (0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			base[0x0555] = (FPW) 0x00800080;	/* erase mode */
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode   */
+	}
+
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int
+bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof (data), left -= sizeof (data) - bytes) {
+
+		bytes = addr & (sizeof (data) - 1);
+		addr &= ~(sizeof (data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof (data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr:	where to copy to
+ * @param cnt:	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/* handle unaligned start bytes */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/* handle word aligned part */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((FPW *) src);
+		if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+			return (rc);
+		}
+		src += sizeof (FPW);
+		wp += sizeof (FPW);
+		cnt -= sizeof (FPW);
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word(info, (FPWV *)wp, data);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_amd(flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+	base[0x0555] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			printf("SHA timeout\n");
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_intel(flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+	*dest = (FPW) 0x00400040;	/* program setup                */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW) 0x00100010))
+		res = 1;	/* write failed, time out error is close enough */
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+
+	return (res);
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int
+flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset(info);	/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset(info);	/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect(info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/u-boot/board/mx1fs2/intel.h b/u-boot/board/mx1fs2/intel.h
new file mode 100644
index 0000000..8db5dd4
--- /dev/null
+++ b/u-boot/board/mx1fs2/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif				/* FLASH_INTEL_H */
diff --git a/u-boot/board/mx1fs2/lowlevel_init.S b/u-boot/board/mx1fs2/lowlevel_init.S
new file mode 100644
index 0000000..56a4819
--- /dev/null
+++ b/u-boot/board/mx1fs2/lowlevel_init.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+	ldr		r0,	=PCDR
+	ldr		r1,	=CONFIG_SYS_PCDR_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 0 */
+
+	ldr		r0,	=MPCTL0
+	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 1 */
+
+	ldr		r0,	=MPCTL1
+	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
+	str		r1,   [r0]
+
+/* set mpll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<21)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+/* set System PLL Control Register 0 */
+
+	ldr		r0,	=SPCTL0
+	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
+	str		r1,   [r0]
+
+/* set System PLL Control Register 1 */
+
+	ldr		r0,	=SPCTL1
+	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
+	str		r1,   [r0]
+
+/* set spll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<22)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+	ldr		r0,   =CSCR
+	ldr		r1,   =CONFIG_SYS_CSCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,   =GPCR
+	ldr		r1,   =CONFIG_SYS_GPCR_VAL
+	str		r1,   [r0]
+
+/*
+ * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ * this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+ *
+ * Slapping this into my bootloader does the trick...
+ *
+ * MRC p15,0,r0,c1,c0,0    ; read core configuration register
+ * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
+ * register
+ *
+ */
+	MRC p15,0,r0,c1,c0,0
+/*	ORR r0,r0,#0xC0000000 async mode */
+/*	ORR r0,r0,#0x40000000 sync mode */
+	ORR r0,r0,#0xC0000000
+	MCR p15,0,r0,c1,c0,0
+
+	ldr		r0,	=GIUS(0)
+	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=FMCR
+	ldr		r1,	=CONFIG_SYS_FMCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0U
+	ldr		r1,	=CONFIG_SYS_CS0U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0L
+	ldr		r1,	=CONFIG_SYS_CS0L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1U
+	ldr		r1,	=CONFIG_SYS_CS1U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1L
+	ldr		r1,	=CONFIG_SYS_CS1L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4U
+	ldr		r1,	=CONFIG_SYS_CS4U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4L
+	ldr		r1,	=CONFIG_SYS_CS4L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5U
+	ldr		r1,	=CONFIG_SYS_CS5U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5L
+	ldr		r1,	=CONFIG_SYS_CS5L_VAL
+	str		r1,   [r0]
+
+/* SDRAM Setup */
+
+	ldr  r1,=0x00221000   /* adr of SDCTRL0			*/
+	ldr  r0,=0x92120200
+	str  r0,[r1,#0]       /* put in precharge command mode    */
+	ldr  r2,=0x08200000   /* adr for precharge cmd	   */
+	ldr  r0,[r2,#0]       /* precharge			   */
+	ldr  r0,=0xA2120200
+	ldr  r2,=0x08000000   /* start of SDRAM		   */
+	str  r0,[r1,#0]       /* put in auto-refresh mode	   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,=0xB2120200
+	ldr  r2,=0x08111800
+	str  r0,[r1,#0]       /* setup for mode register of SDRAM */
+	ldr  r0,[r2,#0]       /* program mode register	   */
+	ldr  r0,=0x82124267
+	str  r0,[r1,#0]       /* back to normal operation	   */
+
+	mov	pc,r10
diff --git a/u-boot/board/mx1fs2/mx1fs2.c b/u-boot/board/mx1fs2/mx1fs2.c
new file mode 100644
index 0000000..90a33c2
--- /dev/null
+++ b/u-boot/board/mx1fs2/mx1fs2.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+
+extern void imx_gpio_mode(int gpio_mode);
+
+static void logo_init(void)
+{
+	imx_gpio_mode(PD15_PF_LD0);
+	imx_gpio_mode(PD16_PF_LD1);
+	imx_gpio_mode(PD17_PF_LD2);
+	imx_gpio_mode(PD18_PF_LD3);
+	imx_gpio_mode(PD19_PF_LD4);
+	imx_gpio_mode(PD20_PF_LD5);
+	imx_gpio_mode(PD21_PF_LD6);
+	imx_gpio_mode(PD22_PF_LD7);
+	imx_gpio_mode(PD23_PF_LD8);
+	imx_gpio_mode(PD24_PF_LD9);
+	imx_gpio_mode(PD25_PF_LD10);
+	imx_gpio_mode(PD26_PF_LD11);
+	imx_gpio_mode(PD27_PF_LD12);
+	imx_gpio_mode(PD28_PF_LD13);
+	imx_gpio_mode(PD29_PF_LD14);
+	imx_gpio_mode(PD30_PF_LD15);
+	imx_gpio_mode(PD14_PF_FLM_VSYNC);
+	imx_gpio_mode(PD13_PF_LP_HSYNC);
+	imx_gpio_mode(PD6_PF_LSCLK);
+	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR);
+	imx_gpio_mode(PD11_PF_CONTRAST);
+	imx_gpio_mode(PD10_PF_SPL_SPR);
+
+	LCDC_RMCR = 0x00000000;
+	LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5);
+	LCDC_HCR = HCR_H_WIDTH(2);
+	LCDC_VCR = VCR_V_WIDTH(2);
+
+	LCDC_PWMR = 0x00000380;   /* contrast to 0x80 middle (is best !!!) */
+	LCDC_SSA  = 0x10040000;   /* image in flash */
+
+	LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240);   /* screen size */
+
+	LCDC_VPW  = 0x000000A0;   /* Virtual Page Width Register */
+	LCDC_POS  = 0x00000000;   /* panning offset 0 (0 pixel offset) */
+
+	/* disable Cursor */
+	LCDC_CPOS  = 0x00000000;
+
+	/* fixed burst length */
+	LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2);
+
+	/* enable LCD */
+	DR(3)   |= 0x00001000;
+	LCDC_RMCR = RMCR_LCDC_EN;
+
+}
+
+int
+board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX1FS2;
+	gd->bd->bi_boot_params = 0x08000100;
+serial_init();
+	logo_init();
+	return 0;
+}
+
+int
+dram_init(void)
+{
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+	gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
+	gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;
+#endif
+	return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ */
+
+void
+show_boot_progress(int status)
+{
+	/* We use this as a hook to disable serial ports just before booting
+	 * This way we suppress the "uncompressing linux..." message
+	 */
+#ifdef CONFIG_SILENT_CONSOLE
+	if( status == 8) {
+		if( getenv("silent") != NULL ) {
+			*(volatile unsigned long *)0x206080 &= ~1;
+			*(volatile unsigned long *)0x207080 &= ~1;
+		}
+	}
+#endif
+	return;
+}
diff --git a/u-boot/board/netphone/Makefile b/u-boot/board/netphone/Makefile
new file mode 100644
index 0000000..24c79a6
--- /dev/null
+++ b/u-boot/board/netphone/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o phone_console.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netphone/flash.c b/u-boot/board/netphone/flash.c
new file mode 100644
index 0000000..349d98e
--- /dev/null
+++ b/u-boot/board/netphone/flash.c
@@ -0,0 +1,529 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+#if CONFIG_NETPHONE_VERSION == 2
+	unsigned long size1;
+#endif
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+#if CONFIG_NETPHONE_VERSION == 2
+	size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
+	if (size1 > 0) {
+		if (flash_info[1].flash_id == FLASH_UNKNOWN)
+			printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
+
+		/* Remap FLASH according to real size */
+		memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
+		memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
+
+		/* Re-do sizing to get full correct info */
+		size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
+
+		flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
+
+		size += size1;
+	} else
+		memctl->memc_br4 &= ~BR_V;
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/netphone/netphone.c b/u-boot/board/netphone/netphone.c
new file mode 100644
index 0000000..7fea71b
--- /dev/null
+++ b/u-boot/board/netphone/netphone.c
@@ -0,0 +1,706 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <sed156x.h>
+#include <status_led.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+#if CONFIG_NETPHONE_VERSION == 2
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+#endif
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
+				BMCR_RESET | BMCR_ANENABLE);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(3) | _BW(14) | _BW(15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_DIRVAL	0
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define PC_GP_INMASK	_BW(12)
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(13) | _BW(15))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PC_GP_INMASK	(_BW(13) | _BW(15))
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(12))
+#endif
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	(_BW(10) | _BW(11))
+#define PC_SP_DIRVAL	0
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define PE_GP_INMASK	_B(31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PE_GP_INMASK	_BR(28, 31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27))
+#endif
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* NAND chip select */
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#elif CONFIG_NETPHONE_VERSION == 2
+	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
+	memctl->memc_mamr = 0;	/* all clear */
+#endif
+
+	/* DSP chip select */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_br4 &= ~BR_V;
+#endif
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+
+	return 0;
+}
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ;	/* poll */
+
+/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+	if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
+		--left_to_poll;
+}
+
+extern void phone_console_do_poll(void);
+
+static void do_poll(void)
+{
+	unsigned int base;
+
+	while (left_to_poll <= 0) {
+		phone_console_do_poll();
+		base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
+		do {
+			left_to_poll = base;
+		} while (base != left_to_poll);
+	}
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+	do_poll();
+}
+
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+	return drv_phone_init();
+}
+
+int last_stage_init(void)
+{
+	int i;
+
+#if CONFIG_NETPHONE_VERSION == 2
+	/* assert peripheral reset */
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	for (i = 0; i < 10; i++)
+		udelay(1000);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+#endif
+	reset_phys();
+
+	/* check in order to enable the local console */
+	left_to_poll = PHONE_CONSOLE_POLL_HZ;
+	i = CONFIG_SYS_HZ * 2;
+	while (i > 0) {
+
+		if (tstc()) {
+			getc();
+			break;
+		}
+
+		do_poll();
+
+		if (drv_phone_use_me()) {
+			status_led_set(0, STATUS_LED_ON);
+			while (!drv_phone_is_idle()) {
+				do_poll();
+				udelay(1000000 / CONFIG_SYS_HZ);
+			}
+
+			console_assign(stdin, "phone");
+			console_assign(stdout, "phone");
+			console_assign(stderr, "phone");
+			setenv("bootdelay", "-1");
+			break;
+		}
+
+		udelay(1000000 / CONFIG_SYS_HZ);
+		i--;
+		left_to_poll--;
+	}
+	left_to_poll = PHONE_CONSOLE_POLL_HZ;
+
+	return 0;
+}
diff --git a/u-boot/board/netphone/phone_console.c b/u-boot/board/netphone/phone_console.c
new file mode 100644
index 0000000..3d82e04
--- /dev/null
+++ b/u-boot/board/netphone/phone_console.c
@@ -0,0 +1,1144 @@
+/*
+ * (C) Copyright 2004 Intracom S.A.
+ * Pantelis Antoniou <panto@intracom.gr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * phone_console.c
+ *
+ * A phone based console
+ *
+ * Virtual display of 80x24 characters.
+ * The actual display is much smaller and panned to show the virtual one.
+ * Input is made by a numeric keypad utilizing the input method of
+ * mobile phones. Sorry no T9 lexicons...
+ *
+ */
+
+#include <common.h>
+
+#include <version.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#include <sed156x.h>
+
+/*************************************************************************************************/
+
+#define ROWS	24
+#define COLS	80
+
+#define REFRESH_HZ		(CONFIG_SYS_HZ/50)	/* refresh every 20ms */
+#define BLINK_HZ		(CONFIG_SYS_HZ/2)	/* cursor blink every 500ms */
+
+/*************************************************************************************************/
+
+#define DISPLAY_BACKLIT_PORT	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat
+#define DISPLAY_BACKLIT_MASK	0x0010
+
+/*************************************************************************************************/
+
+#define KP_STABLE_HZ		(CONFIG_SYS_HZ/100)	/* stable for 10ms */
+#define KP_REPEAT_DELAY_HZ	(CONFIG_SYS_HZ/4)	/* delay before repeat 250ms */
+#define KP_REPEAT_HZ		(CONFIG_SYS_HZ/20)	/* repeat every 50ms */
+#define KP_FORCE_DELAY_HZ	(CONFIG_SYS_HZ/2)	/* key was force pressed */
+#define KP_IDLE_DELAY_HZ	(CONFIG_SYS_HZ/2)	/* key was released and idle */
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_RXD_MASK 0x0008
+
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_TXD_MASK 0x0004
+
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_CLK_MASK 0x0001
+#elif CONFIG_NETPHONE_VERSION == 2
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_RXD_MASK 0x00000008
+
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_TXD_MASK 0x00000004
+
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_CLK_MASK 0x00000002
+#endif
+
+#define KP_CS_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat)
+#define KP_CS_MASK	0x00000010
+
+#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK)
+
+#define KP_SPI_TXD(x) \
+	do { \
+		if (x) \
+			KP_SPI_TXD_PORT |=  KP_SPI_TXD_MASK; \
+		else \
+			KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \
+	} while(0)
+
+#define KP_SPI_CLK(x) \
+	do { \
+		if (x) \
+			KP_SPI_CLK_PORT |=  KP_SPI_CLK_MASK; \
+		else \
+			KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \
+	} while(0)
+
+#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK)
+
+#define KP_SPI_BIT_DELAY()	/* no delay */
+
+#define KP_CS(x) \
+	do { \
+		if (x) \
+			KP_CS_PORT |=  KP_CS_MASK; \
+		else \
+			KP_CS_PORT &= ~KP_CS_MASK; \
+	} while(0)
+
+#define KP_ROWS 7
+#define KP_COLS 4
+
+#define KP_ROWS_MASK	((1 << KP_ROWS) - 1)
+#define KP_COLS_MASK	((1 << KP_COLS) - 1)
+
+#define SCAN		0
+#define SCAN_FILTER	1
+#define SCAN_COL	2
+#define SCAN_COL_FILTER 3
+#define PRESSED		4
+
+#define KP_F1	0	/* leftmost dot (tab)	*/
+#define KP_F2	1	/* middle left dot	*/
+#define KP_F3	2	/* up			*/
+#define KP_F4	3	/* middle right dot	*/
+#define KP_F5	4	/* rightmost dot	*/
+#define KP_F6	5	/* C			*/
+#define KP_F7	6	/* left			*/
+#define KP_F8	7	/* down			*/
+#define KP_F9	8	/* right		*/
+#define KP_F10	9	/* enter		*/
+#define KP_F11	10	/* R			*/
+#define KP_F12	11	/* save			*/
+#define KP_F13	12	/* redial		*/
+#define KP_F14	13	/* speaker		*/
+#define KP_F15	14	/* unused		*/
+#define KP_F16	15	/* unused		*/
+
+#define KP_RELEASE		-1	/* key depressed				*/
+#define KP_FORCE		-2	/* key was pressed for more than force hz	*/
+#define KP_IDLE			-3	/* key was released and idle			*/
+
+#define KP_1	'1'
+#define KP_2	'2'
+#define KP_3	'3'
+#define KP_4	'4'
+#define KP_5	'5'
+#define KP_6	'6'
+#define KP_7	'7'
+#define KP_8	'8'
+#define KP_9	'9'
+#define KP_0	'0'
+#define KP_STAR '*'
+#define KP_HASH '#'
+
+/*************************************************************************************************/
+
+static int curs_disabled;
+static int curs_col, curs_row;
+static int disp_col, disp_row;
+
+static int width, height;
+
+/* the simulated vty buffer */
+static char vty_buf[ROWS * COLS];
+static char last_visible_buf[ROWS * COLS];	/* worst case */
+static char *last_visible_curs_ptr;
+static int last_visible_curs_rev;
+static int blinked_state;
+static int last_input_mode;
+static int refresh_time;
+static int blink_time;
+static char last_fast_punct;
+
+/*************************************************************************************************/
+
+#define IM_SMALL	0
+#define IM_CAPITAL	1
+#define IM_NUMBER	2
+
+static int input_mode;
+static char fast_punct;
+static int tab_indicator;
+static const char *fast_punct_list = ",.:;*";
+
+static const char *input_mode_txt[] = { "abc", "ABC", "123" };
+
+static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|";
+static const char *whspace = " 0\n";
+/* per mode character select (for 2-9) */
+static const char *digits_sel[2][8] = {
+	{	/* small */
+		"abc2",					/* 2 */
+		"def3",					/* 3 */
+		"ghi4",					/* 4 */
+		"jkl5",					/* 5 */
+		"mno6",					/* 6 */
+		"pqrs7",				/* 7 */
+		"tuv8",					/* 8 */
+		"wxyz9",				/* 9 */
+	}, {	/* capital */
+		"ABC2",					/* 2 */
+		"DEF3",					/* 3 */
+		"GHI4",					/* 4 */
+		"JKL5",					/* 5 */
+		"MNO6",					/* 6 */
+		"PQRS7",				/* 7 */
+		"TUV8",					/* 8 */
+		"WXYZ9",				/* 9 */
+	}
+};
+
+/*****************************************************************************/
+
+static void update(void);
+static void ensure_visible(int col, int row, int dx, int dy);
+
+static void console_init(void)
+{
+	curs_disabled = 0;
+	curs_col = 0;
+	curs_row = 0;
+
+	disp_col = 0;
+	disp_row = 0;
+
+	input_mode = IM_SMALL;
+	fast_punct = ',';
+	last_fast_punct = '\0';
+	refresh_time = REFRESH_HZ;
+	blink_time = BLINK_HZ;
+
+	memset(vty_buf, ' ', sizeof(vty_buf));
+
+	memset(last_visible_buf, ' ', sizeof(last_visible_buf));
+	last_visible_curs_ptr = NULL;
+	last_input_mode = -1;
+	last_visible_curs_rev = 0;
+
+	blinked_state = 0;
+
+	sed156x_init();
+	width = sed156x_text_width;
+	height = sed156x_text_height - 1;
+
+	tab_indicator = 0;
+}
+
+/*****************************************************************************/
+
+void phone_putc(const char c);
+
+/*****************************************************************************/
+
+static int  queued_char = -1;
+static int  enabled = 0;
+
+/*****************************************************************************/
+
+/* flush buffers */
+int phone_start(void)
+{
+	console_init();
+
+	update();
+	sed156x_sync();
+
+	enabled = 1;
+	queued_char = 'U' - '@';
+
+	/* backlit on */
+	DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK;
+
+	return 0;
+}
+
+int phone_stop(void)
+{
+	enabled = 0;
+
+	sed156x_clear();
+	sed156x_sync();
+
+	/* backlit off */
+	DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK;
+
+	return 0;
+}
+
+void phone_puts(const char *s)
+{
+	int count = strlen(s);
+
+	while (count--)
+		phone_putc(*s++);
+}
+
+int phone_tstc(void)
+{
+	return queued_char >= 0 ? 1 : 0;
+}
+
+int phone_getc(void)
+{
+	int r;
+
+	if (queued_char < 0)
+		return -1;
+
+	r = queued_char;
+	queued_char = -1;
+
+	return r;
+}
+
+/*****************************************************************************/
+
+int drv_phone_init(void)
+{
+	struct stdio_dev console_dev;
+
+	console_init();
+
+	memset(&console_dev, 0, sizeof(console_dev));
+	strcpy(console_dev.name, "phone");
+	console_dev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	console_dev.start = phone_start;
+	console_dev.stop = phone_stop;
+	console_dev.putc = phone_putc;	/* 'putc' function */
+	console_dev.puts = phone_puts;	/* 'puts' function */
+	console_dev.tstc = phone_tstc;	/* 'tstc' function */
+	console_dev.getc = phone_getc;	/* 'getc' function */
+
+	if (stdio_register(&console_dev) == 0)
+		return 1;
+
+	return 0;
+}
+
+static int use_me;
+
+int drv_phone_use_me(void)
+{
+	return use_me;
+}
+
+static void kp_do_poll(void);
+
+void phone_console_do_poll(void)
+{
+	int i, x, y;
+
+	kp_do_poll();
+
+	if (enabled) {
+		/* do the blink */
+		blink_time -= PHONE_CONSOLE_POLL_HZ;
+		if (blink_time <= 0) {
+			blink_time += BLINK_HZ;
+			if (last_visible_curs_ptr) {
+				i = last_visible_curs_ptr - last_visible_buf;
+				x = i % width; y = i / width;
+				sed156x_reverse_at(x, y, 1);
+				last_visible_curs_rev ^= 1;
+			}
+		}
+
+		/* do the refresh */
+		refresh_time -= PHONE_CONSOLE_POLL_HZ;
+		if (refresh_time <= 0) {
+			refresh_time += REFRESH_HZ;
+			sed156x_sync();
+		}
+	}
+
+}
+
+static int last_scancode = -1;
+static int forced_scancode = 0;
+static int input_state = -1;
+static int input_scancode = -1;
+static int input_selected_char = -1;
+static char input_covered_char;
+
+static void putchar_at_cursor(char c)
+{
+	vty_buf[curs_row * COLS + curs_col] = c;
+	ensure_visible(curs_col, curs_row, 1, 1);
+}
+
+static char getchar_at_cursor(void)
+{
+	return vty_buf[curs_row * COLS + curs_col];
+}
+
+static void queue_input_char(char c)
+{
+	if (c <= 0)
+		return;
+
+	queued_char = c;
+}
+
+static void terminate_input(void)
+{
+	if (input_state < 0)
+		return;
+
+	if (input_selected_char >= 0)
+		queue_input_char(input_selected_char);
+
+	input_state = -1;
+	input_selected_char = -1;
+	putchar_at_cursor(input_covered_char);
+
+	curs_disabled = 0;
+	blink_time = BLINK_HZ;
+	update();
+}
+
+static void handle_enabled_scancode(int scancode)
+{
+	char c;
+	int new_disp_col, new_disp_row;
+	const char *sel;
+
+
+	switch (scancode) {
+
+			/* key was released */
+		case KP_RELEASE:
+			forced_scancode = 0;
+			break;
+
+			/* key was forced */
+		case KP_FORCE:
+
+			switch (last_scancode) {
+				case '#':
+					if (input_mode == IM_NUMBER) {
+						input_mode = IM_CAPITAL;
+						/* queue backspace to erase # */
+						queue_input_char('\b');
+					} else {
+						input_mode = IM_NUMBER;
+						fast_punct = '*';
+					}
+					update();
+					break;
+
+				case '0': case '1':
+				case '2': case '3': case '4': case '5':
+				case '6': case '7': case '8': case '9':
+
+					if (input_state < 0)
+						break;
+
+					input_selected_char = last_scancode;
+					putchar_at_cursor((char)input_selected_char);
+					terminate_input();
+
+					break;
+
+				default:
+					break;
+			}
+
+			break;
+
+			/* release and idle */
+		case KP_IDLE:
+			input_scancode = -1;
+			if (input_state < 0)
+				break;
+			terminate_input();
+			break;
+
+			/* change input mode */
+		case '#':
+			if (last_scancode == '#')	/* no repeat */
+				break;
+
+			if (input_mode == IM_NUMBER) {
+				input_scancode = scancode;
+				input_state = 0;
+				input_selected_char = scancode;
+				input_covered_char = getchar_at_cursor();
+				putchar_at_cursor((char)input_selected_char);
+				terminate_input();
+				break;
+			}
+
+			if (input_mode == IM_SMALL)
+				input_mode = IM_CAPITAL;
+			else
+				input_mode = IM_SMALL;
+
+			update();
+			break;
+
+		case '*':
+			/* no repeat */
+			if (last_scancode == scancode)
+				break;
+
+			if (input_state >= 0)
+				terminate_input();
+
+			input_scancode = fast_punct;
+			input_state = 0;
+			input_selected_char = input_scancode;
+			input_covered_char = getchar_at_cursor();
+			putchar_at_cursor((char)input_selected_char);
+			terminate_input();
+
+			break;
+
+		case '0': case '1':
+		case '2': case '3': case '4': case '5':
+		case '6': case '7': case '8': case '9':
+
+			/* no repeat */
+			if (last_scancode == scancode)
+				break;
+
+			if (input_mode == IM_NUMBER) {
+				input_scancode = scancode;
+				input_state = 0;
+				input_selected_char = scancode;
+				input_covered_char = getchar_at_cursor();
+				putchar_at_cursor((char)input_selected_char);
+				terminate_input();
+				break;
+			}
+
+			if (input_state >= 0 && input_scancode != scancode)
+				terminate_input();
+
+			if (input_state < 0) {
+				curs_disabled = 1;
+				input_scancode = scancode;
+				input_state = 0;
+				input_covered_char = getchar_at_cursor();
+			} else
+				input_state++;
+
+			if (scancode == '0')
+				sel = whspace;
+			else if (scancode == '1')
+				sel = punct;
+			else
+				sel = digits_sel[input_mode][scancode - '2'];
+			c = *(sel + input_state);
+			if (c == '\0') {
+				input_state = 0;
+				c = *sel;
+			}
+
+			input_selected_char = (int)c;
+			putchar_at_cursor((char)input_selected_char);
+			update();
+
+			break;
+
+			/* move visible display */
+		case KP_F3: case KP_F8: case KP_F7: case KP_F9:
+
+			new_disp_col = disp_col;
+			new_disp_row = disp_row;
+
+			switch (scancode) {
+					/* up */
+				case KP_F3:
+					if (new_disp_row <= 0)
+						break;
+					new_disp_row--;
+					break;
+
+					/* down */
+				case KP_F8:
+					if (new_disp_row >= ROWS - height)
+						break;
+					new_disp_row++;
+					break;
+
+					/* left */
+				case KP_F7:
+					if (new_disp_col <= 0)
+						break;
+					new_disp_col--;
+					break;
+
+					/* right */
+				case KP_F9:
+					if (new_disp_col >= COLS - width)
+						break;
+					new_disp_col++;
+					break;
+			}
+
+			/* no change? */
+			if (disp_col == new_disp_col && disp_row == new_disp_row)
+				break;
+
+			disp_col = new_disp_col;
+			disp_row = new_disp_row;
+			update();
+
+			break;
+
+		case KP_F6:	/* backspace */
+			/* inputing something; no backspace sent, just cancel input */
+			if (input_state >= 0) {
+				input_selected_char = -1;	/* cancel */
+				terminate_input();
+				break;
+			}
+			queue_input_char('\b');
+			break;
+
+		case KP_F10:	/* enter */
+			/* inputing something; first cancel input */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('\r');
+			break;
+
+		case KP_F11:	/* R -> Ctrl-C (abort) */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('C' - 'Q');	/* ctrl-c */
+			break;
+
+		case KP_F5:	/* F% -> Ctrl-U (clear line) */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('U' - 'Q');	/* ctrl-c */
+			break;
+
+
+		case KP_F1:	/* tab */
+			/* inputing something; first cancel input */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('\t');
+			break;
+
+		case KP_F2:	/* change fast punct */
+			sel = strchr(fast_punct_list, fast_punct);
+			if (sel == NULL)
+				sel = &fast_punct_list[0];
+			sel++;
+			if (*sel == '\0')
+				sel = &fast_punct_list[0];
+			fast_punct = *sel;
+			update();
+			break;
+
+
+	}
+
+	if (scancode != KP_FORCE && scancode != KP_IDLE)	/* don't record forced or idle scancode */
+		last_scancode = scancode;
+}
+
+static void scancode_action(int scancode)
+{
+#if 0
+	if (scancode == KP_RELEASE)
+		printf(" RELEASE\n");
+	else if (scancode == KP_FORCE)
+		printf(" FORCE\n");
+	else if (scancode == KP_IDLE)
+		printf(" IDLE\n");
+	else if (scancode < 32)
+		printf(" F%d", scancode + 1);
+	else
+		printf(" %c", (char)scancode);
+	printf("\n");
+#endif
+
+	if (enabled) {
+		handle_enabled_scancode(scancode);
+		return;
+	}
+
+	if (scancode == KP_FORCE && last_scancode == '*')
+		use_me = 1;
+
+	last_scancode = scancode;
+}
+
+/**************************************************************************************/
+
+/* update the display; make sure to update only the differences */
+static void update(void)
+{
+	int i;
+	char *s, *e, *t, *r, *b, *cp;
+
+	if (input_mode != last_input_mode)
+		sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3);
+
+	if (tab_indicator == 0) {
+		sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2);
+		tab_indicator = 1;
+	}
+
+	if (fast_punct != last_fast_punct)
+		sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1);
+
+	if (curs_disabled ||
+		curs_col < disp_col || curs_col >= (disp_col + width) ||
+		curs_row < disp_row || curs_row >= (disp_row + height)) {
+		cp = NULL;
+	} else
+		cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col);
+
+
+	/* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */
+
+	/* clear previous cursor */
+	if (last_visible_curs_ptr && last_visible_curs_rev == 0) {
+		i = last_visible_curs_ptr - last_visible_buf;
+		sed156x_reverse_at(i % width, i / width, 1);
+	}
+
+	b = vty_buf + disp_row * COLS + disp_col;
+	t = last_visible_buf;
+	for (i = 0; i < height; i++) {
+		s = b;
+		e = b + width;
+		/* update only the differences */
+		do {
+			while (s < e && *s == *t) {
+				s++;
+				t++;
+			}
+			if (s == e)	/* no more */
+				break;
+
+			/* find run */
+			r = s;
+			while (s < e && *s != *t)
+				*t++ = *s++;
+
+			/* and update */
+			sed156x_output_at(r - b, i, r, s - r);
+
+		} while (s < e);
+
+		b += COLS;
+	}
+
+	/* set cursor */
+	if (cp) {
+		last_visible_curs_ptr = cp;
+		i = last_visible_curs_ptr - last_visible_buf;
+		sed156x_reverse_at(i % width, i / width, 1);
+		last_visible_curs_rev = 0;
+	} else {
+		last_visible_curs_ptr = NULL;
+	}
+
+	last_input_mode = input_mode;
+	last_fast_punct = fast_punct;
+}
+
+/* ensure visibility; the trick is to minimize the screen movement */
+static void ensure_visible(int col, int row, int dx, int dy)
+{
+	int x1, y1, x2, y2, a1, b1, a2, b2;
+
+	/* clamp visible region */
+	if (col < 0) {
+		dx -= col;
+		col = 0;
+		if (dx <= 0)
+			dx = 1;
+	}
+
+	if (row < 0) {
+		dy -= row;
+		row = 0;
+		if (dy <= 0)
+			dy = 1;
+	}
+
+	if (col + dx > COLS)
+		dx = COLS - col;
+
+	if (row + dy > ROWS)
+		dy = ROWS - row;
+
+
+	/* move to easier to use vars */
+	x1 = disp_col;	 y1 = disp_row;
+	x2 = x1 + width; y2 = y1 + height;
+	a1 = col;	 b1 = row;
+	a2 = a1 + dx;	 b2 = b1 + dy;
+
+	/* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
+
+	if (a2 > x2) {
+		/* move to the right */
+		x2 = a2;
+		x1 = x2 - width;
+		if (x1 < 0) {
+			x1 = 0;
+			x2 = width;
+		}
+	} else if (a1 < x1) {
+		/* move to the left */
+		x1 = a1;
+		x2 = x1 + width;
+		if (x2 > COLS) {
+			x2 = COLS;
+			x1 = x2 - width;
+		}
+	}
+
+	if (b2 > y2) {
+		/* move down */
+		y2 = b2;
+		y1 = y2 - height;
+		if (y1 < 0) {
+			y1 = 0;
+			y2 = height;
+		}
+	} else if (b1 < y1) {
+		/* move up */
+		y1 = b1;
+		y2 = y1 + width;
+		if (y2 > ROWS) {
+			y2 = ROWS;
+			y1 = y2 - height;
+		}
+	}
+
+	/* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
+
+	/* no movement? */
+	if (disp_col == x1 && disp_row == y1)
+		return;
+
+	disp_col = x1;
+	disp_row = y1;
+}
+
+/**************************************************************************************/
+
+static void newline(void)
+{
+	curs_col = 0;
+	if (curs_row + 1 < ROWS)
+		curs_row++;
+	else {
+		memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1));
+		memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS);
+	}
+}
+
+void phone_putc(const char c)
+{
+	int i;
+
+	if (input_mode != -1) {
+		input_selected_char = -1;
+		terminate_input();
+	}
+
+	curs_disabled = 1;
+	update();
+
+	blink_time = BLINK_HZ;
+
+	switch (c) {
+		case '\a':		/* ignore bell		  */
+		case '\r':		/* ignore carriage return */
+			break;
+
+		case '\n':		/* next line */
+			newline();
+			ensure_visible(curs_col, curs_row, 1, 1);
+			break;
+
+		case 9: /* tab 8 */
+			/* move to tab */
+			i = curs_col;
+			i |=  0x0008;
+			i &= ~0x0007;
+
+			if (i < COLS)
+				curs_col = i;
+			else
+				newline();
+
+			ensure_visible(curs_col, curs_row, 1, 1);
+			break;
+
+		case 8:		/* backspace */
+			if (curs_col <= 0)
+				break;
+			curs_col--;
+
+			/* make sure that we see a couple of characters before */
+			if (curs_col > 4)
+				ensure_visible(curs_col - 4, curs_row, 4, 1);
+			else
+				ensure_visible(curs_col, curs_row, 1, 1);
+
+			break;
+
+		default:		/* draw the char */
+			putchar_at_cursor(c);
+
+			/*
+			 * check for newline
+			 */
+			if (curs_col + 1 < COLS)
+				curs_col++;
+			else
+				newline();
+
+			ensure_visible(curs_col, curs_row, 1, 1);
+
+			break;
+	}
+
+	curs_disabled = 0;
+	blink_time = BLINK_HZ;
+	update();
+}
+
+/**************************************************************************************/
+
+static inline unsigned int kp_transfer(unsigned int val)
+{
+	unsigned int rx;
+	int b;
+
+	rx = 0; b = 8;
+	while (--b >= 0) {
+		KP_SPI_TXD(val & 0x80);
+		val <<= 1;
+		KP_SPI_CLK_TOGGLE();
+		KP_SPI_BIT_DELAY();
+		rx <<= 1;
+		if (KP_SPI_RXD())
+			rx |= 1;
+		KP_SPI_CLK_TOGGLE();
+		KP_SPI_BIT_DELAY();
+	}
+
+	return rx;
+}
+
+unsigned int kp_data_transfer(unsigned int val)
+{
+	KP_SPI_CLK(1);
+	KP_CS(0);
+	val = kp_transfer(val);
+	KP_CS(1);
+
+	return val;
+}
+
+unsigned int kp_get_col_mask(unsigned int row_mask)
+{
+	unsigned int val, col_mask;
+
+	val = 0x80 | (row_mask & 0x7F);
+	(void)kp_data_transfer(val);
+#if CONFIG_NETPHONE_VERSION == 1
+	col_mask = kp_data_transfer(val) & 0x0F;
+#elif CONFIG_NETPHONE_VERSION == 2
+	col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f;
+	/* XXX FUCK FUCK FUCK FUCK FUCK!!!! */
+	col_mask = ((col_mask & 0x08) >> 3) |	/* BKBR1 */
+		   ((col_mask & 0x04) << 1) |	/* BKBR2 */
+		    (col_mask & 0x02) |		/* BKBR3 */
+		   ((col_mask & 0x01) << 2);	/* BKBR4 */
+
+#endif
+	/* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */
+
+	return col_mask;
+}
+
+/**************************************************************************************/
+
+static const int kp_scancodes[KP_ROWS * KP_COLS] = {
+	KP_F1,	 KP_F3,	  KP_F4,  KP_F2,
+	KP_F6,	 KP_F8,	  KP_F9,  KP_F7,
+	KP_1,	 KP_3,	  KP_F11, KP_2,
+	KP_4,	 KP_6,	  KP_F12, KP_5,
+	KP_7,	 KP_9,	  KP_F13, KP_8,
+	KP_STAR, KP_HASH, KP_F14, KP_0,
+	KP_F5,	 KP_F15,  KP_F16, KP_F10,
+};
+
+static const int kp_repeats[KP_ROWS * KP_COLS] = {
+	0, 1, 0, 0,
+	0, 1, 1, 1,
+	1, 1, 0, 1,
+	1, 1, 0, 1,
+	1, 1, 0, 1,
+	1, 1, 0, 1,
+	0, 0, 0, 1,
+};
+
+static int kp_state = SCAN;
+static int kp_last_col_mask;
+static int kp_cur_row, kp_cur_col;
+static int kp_scancode;
+static int kp_stable;
+static int kp_repeat;
+static int kp_repeat_time;
+static int kp_force_time;
+static int kp_idle_time;
+
+static void kp_do_poll(void)
+{
+	unsigned int col_mask;
+	int col;
+
+	switch (kp_state) {
+		case SCAN:
+			if (kp_idle_time > 0) {
+				kp_idle_time -= PHONE_CONSOLE_POLL_HZ;
+				if (kp_idle_time <= 0)
+					scancode_action(KP_IDLE);
+			}
+
+			col_mask = kp_get_col_mask(KP_ROWS_MASK);
+			if (col_mask == KP_COLS_MASK)
+				break;	/* nothing */
+			kp_last_col_mask = col_mask;
+			kp_stable = 0;
+			kp_state = SCAN_FILTER;
+			break;
+
+		case SCAN_FILTER:
+			col_mask = kp_get_col_mask(KP_ROWS_MASK);
+			if (col_mask != kp_last_col_mask) {
+				kp_state = SCAN;
+				break;
+			}
+
+			kp_stable += PHONE_CONSOLE_POLL_HZ;
+			if (kp_stable < KP_STABLE_HZ)
+				break;
+
+			kp_cur_row = 0;
+			kp_stable = 0;
+			kp_state = SCAN_COL;
+
+			(void)kp_get_col_mask(1 << kp_cur_row);
+			break;
+
+		case SCAN_COL:
+			col_mask = kp_get_col_mask(1 << kp_cur_row);
+			if (col_mask == KP_COLS_MASK) {
+				if (++kp_cur_row >= KP_ROWS) {
+					kp_state = SCAN;
+					break;
+				}
+				kp_get_col_mask(1 << kp_cur_row);
+				break;
+			}
+			kp_last_col_mask = col_mask;
+			kp_stable = 0;
+			kp_state = SCAN_COL_FILTER;
+			break;
+
+		case SCAN_COL_FILTER:
+			col_mask = kp_get_col_mask(1 << kp_cur_row);
+			if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) {
+				kp_state = SCAN;
+				break;
+			}
+
+			kp_stable += PHONE_CONSOLE_POLL_HZ;
+			if (kp_stable < KP_STABLE_HZ)
+				break;
+
+			for (col = 0; col < KP_COLS; col++)
+				if ((col_mask & (1 << col)) == 0)
+					break;
+			kp_cur_col = col;
+			kp_state = PRESSED;
+			kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col];
+			kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col];
+
+			if (kp_repeat)
+				kp_repeat_time = KP_REPEAT_DELAY_HZ;
+			kp_force_time = KP_FORCE_DELAY_HZ;
+
+			scancode_action(kp_scancode);
+
+			break;
+
+		case PRESSED:
+			col_mask = kp_get_col_mask(1 << kp_cur_row);
+			if (col_mask != kp_last_col_mask) {
+				kp_state = SCAN;
+				scancode_action(KP_RELEASE);
+				kp_idle_time = KP_IDLE_DELAY_HZ;
+				break;
+			}
+
+			if (kp_repeat) {
+				kp_repeat_time -= PHONE_CONSOLE_POLL_HZ;
+				if (kp_repeat_time <= 0) {
+					kp_repeat_time += KP_REPEAT_HZ;
+					scancode_action(kp_scancode);
+				}
+			}
+
+			if (kp_force_time > 0) {
+				kp_force_time -= PHONE_CONSOLE_POLL_HZ;
+				if (kp_force_time <= 0)
+					scancode_action(KP_FORCE);
+			}
+
+			break;
+	}
+}
+
+/**************************************************************************************/
+
+int drv_phone_is_idle(void)
+{
+	return kp_state == SCAN;
+}
diff --git a/u-boot/board/netphone/u-boot.lds b/u-boot/board/netphone/u-boot.lds
new file mode 100644
index 0000000..684ab81
--- /dev/null
+++ b/u-boot/board/netphone/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text	:
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netphone/u-boot.lds.debug b/u-boot/board/netphone/u-boot.lds.debug
new file mode 100644
index 0000000..df7b6ad
--- /dev/null
+++ b/u-boot/board/netphone/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netstal/common/fixed_sdram.c b/u-boot/board/netstal/common/fixed_sdram.c
new file mode 100644
index 0000000..51b34b2
--- /dev/null
+++ b/u-boot/board/netstal/common/fixed_sdram.c
@@ -0,0 +1,105 @@
+/*
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
+ *    Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include  <asm/ppc4xx.h>
+#include  <asm/processor.h>
+#include  "nm.h"
+
+#if defined(DEBUG)
+void show_sdram_registers(void)
+{
+	u32 value;
+
+	printf("SDRAM Controller Registers --\n");
+	mfsdram(SDRAM0_CFG, value);
+	printf("    SDRAM0_CFG   : 0x%08x\n", value);
+	mfsdram(SDRAM0_STATUS, value);
+	printf("    SDRAM0_STATUS: 0x%08x\n", value);
+	mfsdram(SDRAM0_B0CR, value);
+	printf("    SDRAM0_B0CR  : 0x%08x\n", value);
+	mfsdram(SDRAM0_B1CR, value);
+	printf("    SDRAM0_B1CR  : 0x%08x\n", value);
+	mfsdram(SDRAM0_TR, value);
+	printf("    SDRAM0_TR    : 0x%08x\n", value);
+	mfsdram(SDRAM0_RTR, value);
+	printf("    SDRAM0_RTR   : 0x%08x\n", value);
+}
+#endif
+
+long int init_ppc405_sdram(unsigned int dram_size)
+{
+#ifdef DEBUG
+	printf(__FUNCTION__);
+#endif
+	/* disable memory controller */
+	mtsdram(SDRAM0_CFG, 0x00000000);
+
+	udelay (500);
+
+	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+	mtsdram(SDRAM0_BESR0, 0xffffffff);
+
+	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+	mtsdram(SDRAM0_BESR1, 0xffffffff);
+
+	/* Clear SDRAM0_ECCCFG (disable ECC) */
+	mtsdram(SDRAM0_ECCCFG, 0x00000000);
+
+	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+	mtsdram(SDRAM0_ECCESR, 0xffffffff);
+
+	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
+	 */
+	mtsdram(SDRAM0_TR, 0x008a4015);
+
+	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
+	 * and refresh timer
+	 */
+	switch (dram_size >> 20) {
+	case 32:
+		mtsdram(SDRAM0_B0CR, 0x00062001);
+		mtsdram(SDRAM0_RTR,   0x07F00000);
+		break;
+	case 64:
+		mtsdram(SDRAM0_B0CR, 0x00084001);
+		mtsdram(SDRAM0_RTR,   0x04100000);
+		break;
+	case 128:
+		mtsdram(SDRAM0_B0CR, 0x000A4001);
+		mtsdram(SDRAM0_RTR,   0x04100000);
+		break;
+	default:
+		printf("Invalid memory size of %d MB given\n", dram_size >> 20);
+	}
+
+	/* Power management idle timer set to the default. */
+	mtsdram(SDRAM0_PMIT, 0x07c00000);
+
+	udelay (500);
+
+	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
+	mtsdram(SDRAM0_CFG, 0x90800000);
+
+#ifdef DEBUG
+	printf("%s: done\n", __FUNCTION__);
+#endif
+	return dram_size;
+}
diff --git a/u-boot/board/netstal/common/nm.h b/u-boot/board/netstal/common/nm.h
new file mode 100644
index 0000000..3dff1d6
--- /dev/null
+++ b/u-boot/board/netstal/common/nm.h
@@ -0,0 +1,44 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ *    Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+extern void hcu_led_set(u32 value);
+extern u32 get_serial_number(void);
+extern u32 hcu_get_slot(void);
+extern int board_with_pci(void);
+extern void nm_show_print(int generation, int index, int hw_capabilities);
+extern void set_params_for_sw_install(int install_requested, char *board_name );
+extern void common_misc_init_r(void);
+
+enum {
+	/* HW_GENERATION_HCU1/2 is no longer supported */
+	HW_GENERATION_HCU3  = 0x10,
+	HW_GENERATION_HCU4  = 0x20,
+	HW_GENERATION_HCU5  = 0x30,
+	HW_GENERATION_MCU   = 0x08,
+	HW_GENERATION_MCU20 = 0x0a,
+	HW_GENERATION_MCU25 = 0x09,
+};
+
+#ifdef CONFIG_405GP
+#if defined(DEBUG)
+void show_sdram_registers(void);
+#endif
+long int init_ppc405_sdram(unsigned int dram_size);
+#endif
diff --git a/u-boot/board/netstal/common/nm_bsp.c b/u-boot/board/netstal/common/nm_bsp.c
new file mode 100644
index 0000000..237f4ed
--- /dev/null
+++ b/u-boot/board/netstal/common/nm_bsp.c
@@ -0,0 +1,117 @@
+/*
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
+ *    Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include "nm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DEFAULT_ETH_ADDR  "ethaddr"
+
+typedef struct {u8	id;	char *name;} generation_info;
+
+generation_info generations[6] = {
+	{HW_GENERATION_HCU3,	"HCU3"},
+	{HW_GENERATION_HCU4,	"HCU4"},
+	{HW_GENERATION_HCU5,	"HCU5"},
+	{HW_GENERATION_MCU,	"MCU"},
+	{HW_GENERATION_MCU20,	"MCU20"},
+	{HW_GENERATION_MCU25,	"MCU25"},
+};
+
+void nm_show_print(int generation, int index, int hw_capabilities)
+{
+	int j;
+	char *generationName=0;
+
+	/* reset ANSI terminal color mode */
+	printf("\x1B""[0m""Netstal Maschinen AG: ");
+	for (j=0; j < (sizeof(generations)/sizeof(generations[0])); j++) {
+		if (generations[j].id == generation) {
+			generationName = generations[j].name;
+			break;
+		}
+	}
+	printf("%s: index %d HW 0x%x\n", generationName, index, hw_capabilities);
+	for (j = 0;j < 6; j++) {
+		hcu_led_set(1 << j);
+		udelay(200 * 1000);
+	}
+}
+
+void set_params_for_sw_install(int install_requested, char *board_name )
+{
+	if (install_requested) {
+		char string[128];
+
+		printf("\n\n%s SW-Installation: %d patching boot parameters\n",
+		       board_name, install_requested);
+		setenv("bootdelay", "0");
+		setenv("loadaddr", "0x01000000");
+		setenv("serverip", "172.25.1.1");
+		setenv("bootcmd", "run install");
+		sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; "
+			"tftp ${loadaddr} installer/%s_sw_inst; "
+			"run boot_sw_inst", board_name);
+		setenv("install", string);
+		sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst "
+			"e=${ipaddr} h=${serverip} f=0x1000; "
+			"bootvx ${loadaddr}%c",
+			board_name, board_name, 0);
+		setenv("boot_sw_inst", string);
+	}
+}
+
+void common_misc_init_r(void)
+{
+	IPaddr_t ipaddr;
+	char *ipstring;
+	uchar ethaddr[6];
+
+	if (!eth_getenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr)) {
+		/* Must be in sync with CONFIG_ETHADDR */
+		u32 serial = get_serial_number();
+		ethaddr[0] = 0x00;
+		ethaddr[1] = 0x60;
+		ethaddr[2] = 0x13;
+		ethaddr[3] = (serial >> 16) & 0xff;
+		ethaddr[4] = (serial >>  8) & 0xff;
+		ethaddr[5] = hcu_get_slot();
+		eth_setenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr);
+	}
+
+	/* IP-Adress update */
+	ipstring = getenv("ipaddr");
+	if (ipstring == 0)
+		ipaddr = string_to_ip("172.25.1.99");
+	else
+		ipaddr = string_to_ip(ipstring);
+	if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
+		char tmp[22];
+
+		ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
+		ip_to_string (ipaddr, tmp);
+		printf("%s: enforce %s\n",  __FUNCTION__, tmp);
+		setenv("ipaddr", tmp);
+		saveenv();
+	}
+}
diff --git a/u-boot/board/netstal/hcu4/Makefile b/u-boot/board/netstal/hcu4/Makefile
new file mode 100644
index 0000000..a983de9
--- /dev/null
+++ b/u-boot/board/netstal/hcu4/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007-2008 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o \
+	../common/fixed_sdram.o \
+	../common/nm_bsp.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netstal/hcu4/README.txt b/u-boot/board/netstal/hcu4/README.txt
new file mode 100644
index 0000000..1e9c64a
--- /dev/null
+++ b/u-boot/board/netstal/hcu4/README.txt
@@ -0,0 +1,59 @@
+HCU4 Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+0x70000000
+
+Chip-Select 3: CAN Interface
+----------------------------
+0x7800000
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+Our IO-Bus (slow version)
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+Our IO-Bus (fast, but not yet use)
+
+
+Memory Bank 1 -- SDRAM
+-------------------------------------
+
+0x00000000 - 0x1ffffff   # Default 32 MB
diff --git a/u-boot/board/netstal/hcu4/config.mk b/u-boot/board/netstal/hcu4/config.mk
new file mode 100644
index 0000000..fd3e889
--- /dev/null
+++ b/u-boot/board/netstal/hcu4/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+#     Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: HCU4 boards
+#
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
diff --git a/u-boot/board/netstal/hcu4/hcu4.c b/u-boot/board/netstal/hcu4/hcu4.c
new file mode 100644
index 0000000..aaf3616
--- /dev/null
+++ b/u-boot/board/netstal/hcu4/hcu4.c
@@ -0,0 +1,198 @@
+/*
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
+ *    Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include  <common.h>
+#include  <asm/ppc4xx.h>
+#include  <asm/processor.h>
+#include  <asm/io.h>
+#include  <asm/u-boot.h>
+#include  "../common/nm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HCU_MACH_VERSIONS_REGISTER	(0x7C000000 + 0xF00000)
+#define HCU_SLOT_ADDRESS		(0x7C000000 + 0x400000)
+#define HCU_DIGITAL_IO_REGISTER		(0x7C000000 + 0x500000)
+#define HCU_SW_INSTALL_REQUESTED	0x10
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+/* Attention: If you want 1 microsecs times from the external oscillator
+ * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
+ * 0x00804051 causes problems with u-boot and linux!
+ */
+#define CPC0_CR0_VALUE	0x0030103c
+#define CPC0_CR1_VALUE	0x00004051
+
+int board_early_init_f (void)
+{
+	/*
+	 * Interrupt controller setup for the HCU4 board.
+	 * Note: IRQ 0-15  405GP internally generated; high; level sensitive
+	 *       IRQ 16    405GP internally generated; low; level sensitive
+	 *      IRQ 17-24 RESERVED/UNUSED
+	 *      IRQ 31 (EXT IRQ 6) (unused)
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
+	mtdcr(CPC0_ECR, 0x60606000);
+	mtdcr(CPC0_EIRR, 0x7C000000);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+	return board_early_init_f ();
+}
+#endif
+
+int sys_install_requested(void)
+{
+	u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER);
+	return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0;
+}
+
+int checkboard (void)
+{
+	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
+	u16 generation = boardVersReg & 0xf0;
+	u16 index      = boardVersReg & 0x0f;
+
+	/* Cannot be done in board_early_init */
+	mtdcr(CPC0_CR0,  CPC0_CR0_VALUE);
+
+	/* Force /RTS to active. The board it not wired quite
+	 *  correctly to use cts/rtc flow control, so just force the
+	 *  /RST active and forget about it.
+	 */
+	writeb (readb (0xef600404) | 0x03, 0xef600404);
+	nm_show_print(generation, index, 0);
+
+	return 0;
+}
+
+u32 hcu_led_get(void)
+{
+	return (~(in_be32((u32 *)GPIO0_OR)) >> 23) & 0xff;
+}
+
+/*
+ * hcu_led_set  value to be placed into the LEDs (max 6 bit)
+ */
+void hcu_led_set(u32 value)
+{
+	u32   tmp = ~value;
+
+	tmp = (tmp << 23) | 0x7FFFFF;
+	out_be32((u32 *)GPIO0_OR, tmp);
+}
+
+/*
+ * hcu_get_slot
+ */
+u32 hcu_get_slot(void)
+{
+	u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS);
+	return slot & 0x7f;
+}
+
+/*
+ * get_serial_number
+ */
+u32 get_serial_number(void)
+{
+	u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
+
+	if (serial == 0xffffffff)
+		return 0;
+
+	return serial;
+}
+
+
+/*
+ * misc_init_r.
+ */
+
+int misc_init_r(void)
+{
+	common_misc_init_r();
+	set_params_for_sw_install( sys_install_requested(), "hcu4" );
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	long dram_size = 0;
+	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
+	u16 generation = boardVersReg & 0xf0;
+	u16 index      = boardVersReg & 0x0f;
+
+	if (generation == HW_GENERATION_HCU3 && index < 0xf)
+		dram_size = 32 << 20;	/* 32 MB - RAM */
+	else
+		dram_size = 64 << 20;	/* 64 MB - RAM */
+	init_ppc405_sdram(dram_size);
+
+#ifdef DEBUG
+	show_sdram_registers();
+#endif
+
+	return dram_size;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = 1;
+		info->chipwidth = 1;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/u-boot/board/netstal/hcu5/Makefile b/u-boot/board/netstal/hcu5/Makefile
new file mode 100644
index 0000000..280c2f6
--- /dev/null
+++ b/u-boot/board/netstal/hcu5/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2007-2008 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o \
+	sdram.o \
+	../common/nm_bsp.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netstal/hcu5/README.txt b/u-boot/board/netstal/hcu5/README.txt
new file mode 100644
index 0000000..c5737d0
--- /dev/null
+++ b/u-boot/board/netstal/hcu5/README.txt
@@ -0,0 +1,171 @@
+HCU5 configuration details and startup sequence
+
+(C) Copyright 2007 Netstal Maschinen AG
+    Niklaus Giger (Niklaus.Giger@netstal.com)
+
+TODO:
+-----
+- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
+     - Does not occur if both EMAC are connected
+- Fix RTS/CTS problem (HW?)
+  CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
+  Switching to interrupt driven serial input mode
+
+Caveats:
+--------
+Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
+see hcu5.c.
+
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xe0010000- 0xe0013fff   CONFIG_SYS_OCM_BASE
+The 440EPx includes a 16K on-chip memory that can be placed however
+software chooses.
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC440EPX
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+Not used
+
+Chip-Select 3: CAN Interface
+----------------------------
+0xc800000: 2 Intel 82527 CAN-Controller
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+0xcc00000: Netstal specific IO-Bus
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+0xce00000: Netstal specific IO-Bus (fast, but not yet used)
+
+
+Memory Bank 1 -- DDR2
+-------------------------------------
+
+0x00000000 - 0xfffffff   # Default 256 MB
+
+PCI ??
+
+USB ??
+Only USB_STORAGE is enabled to load vxWorks
+from a memory stick.
+
+System-LEDs ??? (Analog zu HCU4 ???)
+
+Startup sequence
+----------------
+
+(arch/powerpc/cpu/ppc4xx/resetvec.S)
+depending on configs option
+call _start_440 _start_pci oder _start
+
+(arch/powerpc/cpu/ppc4xx/start.S)
+
+_start_440:
+	initialize register like
+	CCR0
+	debug
+	setup interrupt vectors
+	configure cache regions
+	clear and setup TLB
+	enable internal RAM
+	jump start_ram
+	which in turn will jump to start
+_start:
+	Clear and set up some registers.
+	Debug setup
+	Setup the internal SRAM
+	Setup the stack in internal SRAM
+    setup stack pointer (r1)
+    setup GOT
+	call cpu_init_f	/* run low-level CPU init code	   (from Flash) */
+
+    call cpu_init_f
+    board_init_f: (arch/powerpc/lib\board.c)
+	init_sequence defines a list of function to be called
+	    board_early_init_f: (board/netstal/hcu5/hcu5.c)
+		We are using Bootstrap-Option A
+		if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
+		Setup the GPIO pins
+		Setup the interrupt controller polarities, triggers, etc.
+		Ethernet, PCI, USB enable
+		setup BOOT FLASH (Chip timing)
+	    init_baudrate,
+	    serial_init
+	    checkcpu
+	    misc_init_f #ifdef
+	    init_func_i2c #ifdef
+	    post_init_f  #ifdef
+	    init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
+		(EYE function removed!!)
+	    test_dram call
+
+	 * Reserve memory at end of RAM for (top down in that order):
+	 *  - kernel log buffer
+	 *  - protected RAM
+	 *  - LCD framebuffer
+	 *  - monitor code
+	 *  - board info struct
+	Save local variables to board info struct
+	call relocate_code() does not return
+	relocate_code: (arch/powerpc/cpu/ppc4xx/start.S)
+-------------------------------------------------------
+From now on our copy is in RAM and we will run from there,
+	starting with board_init_r
+-------------------------------------------------------
+    board_init_r: (arch/powerpc/lib\board.c)
+	setup bd function pointers
+	trap_init
+	flash_init: (board/netstal/hcu5/flash.c)
+		/* setup for u-boot erase, update */
+	setup bd flash info
+	cpu_init_r: (arch/powerpc/cpu/ppc4xx/cpu_init.c)
+	    peripheral chip select in using defines like
+	    CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
+	mem_malloc_init
+	malloc_bin_reloc
+	spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
+	env_relocated
+	misc_init_r(bd): (board/netstal/hcu5.c)
+	    ethaddr mit serial number ergänzen
+    Then we will somehow go into the command loop
+
+Most of the HW specific code for the HCU5 may be found in
+include/configs/hcu5.h
+board/netstal/hcu5/*
+arch/powerpc/cpu/ppc4xx/*
+arch/powerpc/lib/*
+include/ppc440.h
+
+Drivers for serial etc are found under drivers/
+
+Don't ask question if you did not look at the README !!
+Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there.
diff --git a/u-boot/board/netstal/hcu5/config.mk b/u-boot/board/netstal/hcu5/config.mk
new file mode 100644
index 0000000..f641d54
--- /dev/null
+++ b/u-boot/board/netstal/hcu5/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+#     Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: HCU5 boards
+#
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
diff --git a/u-boot/board/netstal/hcu5/hcu5.c b/u-boot/board/netstal/hcu5/hcu5.c
new file mode 100644
index 0000000..f94d05b
--- /dev/null
+++ b/u-boot/board/netstal/hcu5/hcu5.c
@@ -0,0 +1,414 @@
+/*
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
+ *    Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include <asm/io.h>
+#include <asm/4xx_pci.h>
+
+#include  "../common/nm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#undef BOOTSTRAP_OPTION_A_ACTIVE
+
+#define SDR0_CP440		0x0180
+
+#define SYSTEM_RESET		0x30000000
+#define CHIP_RESET		0x20000000
+
+#define SDR0_ECID0		0x0080
+#define SDR0_ECID1		0x0081
+#define SDR0_ECID2		0x0082
+#define SDR0_ECID3		0x0083
+
+#define SYS_IO_ADDRESS			(CONFIG_SYS_CS_2 + 0x00e00000)
+#define SYS_SLOT_ADDRESS		(CONFIG_SYS_CPLD + 0x00400000)
+#define HCU_DIGITAL_IO_REGISTER	(CONFIG_SYS_CPLD + 0x0500000)
+#define HCU_SW_INSTALL_REQUESTED	0x10
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+int board_early_init_f(void)
+{
+
+#ifdef BOOTSTRAP_OPTION_A_ACTIVE
+	/* Booting with Bootstrap Option A
+	 * First boot, with CPR0_ICFG_RLI_MASK == 0
+	 * no we setup varios boot strapping register,
+	 * then we do reset the PPC440 using a chip reset
+	 * Unfortunately, we cannot use this option, as Nto1 is not set
+	 * with Bootstrap Option A and cannot be changed later on by SW
+	 * There are no other possible boostrap options with a 8 bit ROM
+	 * See Errata (Version 1.04) CHIP_9
+	 */
+
+	u32 cpr0icfg;
+	u32 dbcr;
+
+	mfcpr(CPR0_ICFG, cpr0icfg);
+	if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
+		mtcpr(CPR0_MALD,   0x02000000);
+		mtcpr(CPR0_OPBD,   0x02000000);
+	        mtcpr(CPR0_PERD,   0x05000000);  /* 1:5 */
+		mtcpr(CPR0_PLLC,   0x40000238);
+		mtcpr(CPR0_PLLD,   0x01010414);
+		mtcpr(CPR0_PRIMAD, 0x01000000);
+		mtcpr(CPR0_PRIMBD, 0x01000000);
+		mtcpr(CPR0_SPCID,  0x03000000);
+		mtsdr(SDR0_PFC0,   0x00003E00);  /* [CTE] = 0 */
+		mtsdr(SDR0_CP440,  0x0EAAEA02);  /* [Nto1] = 1*/
+		mtcpr(CPR0_ICFG,   cpr0icfg | CPR0_ICFG_RLI_MASK);
+
+		/*
+		 * Initiate system reset in debug control register DBCR
+		 */
+		dbcr = mfspr(SPRN_DBCR0);
+		mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
+	}
+	mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
+#endif
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+	/*
+	 * Setup the GPIO pins
+	 */
+	out32(GPIO0_OR, 0x00000000);
+	out32(GPIO0_TCR, 0x7C2FF1CF);
+	out32(GPIO0_OSRL, 0x40055000);
+	out32(GPIO0_OSRH, 0x00000000);
+	out32(GPIO0_TSRL, 0x40055000);
+	out32(GPIO0_TSRH, 0x00000400);
+	out32(GPIO0_ISR1L, 0x40000000);
+	out32(GPIO0_ISR1H, 0x00000000);
+	out32(GPIO0_ISR2L, 0x00000000);
+	out32(GPIO0_ISR2H, 0x00000000);
+	out32(GPIO0_ISR3L, 0x00000000);
+	out32(GPIO0_ISR3H, 0x00000000);
+
+	out32(GPIO1_OR, 0x00000000);
+	out32(GPIO1_TCR, 0xC6007FFF);
+	out32(GPIO1_OSRL, 0x00140000);
+	out32(GPIO1_OSRH, 0x00000000);
+	out32(GPIO1_TSRL, 0x00000000);
+	out32(GPIO1_TSRH, 0x00000000);
+	out32(GPIO1_ISR1L, 0x05415555);
+	out32(GPIO1_ISR1H, 0x40000000);
+	out32(GPIO1_ISR2L, 0x00000000);
+	out32(GPIO1_ISR2H, 0x00000000);
+	out32(GPIO1_ISR3L, 0x00000000);
+	out32(GPIO1_ISR3H, 0x00000000);
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtsdr(SDR0_PFC0, 0x00003E00);	/* Pin function:  */
+	mtsdr(SDR0_PFC1, 0x00848000);	/* Pin function: UART0 has 4 pins */
+
+	/* setup BOOT FLASH */
+	mtsdr(SDR0_CUST0, 0xC0082350);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init(void)
+{
+	return board_early_init_f();
+}
+
+#endif
+
+int sys_install_requested(void)
+{
+	u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
+	return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
+}
+
+int checkboard(void)
+{
+	u16 *hwVersReg    = (u16 *) HCU_HW_VERSION_REGISTER;
+	u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
+	u16 generation = in_be16(boardVersReg) & 0xf0;
+	u16 index      = in_be16(boardVersReg) & 0x0f;
+	u32 ecid0, ecid1, ecid2, ecid3;
+
+	nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
+	mfsdr(SDR0_ECID0, ecid0);
+	mfsdr(SDR0_ECID1, ecid1);
+	mfsdr(SDR0_ECID2, ecid2);
+	mfsdr(SDR0_ECID3, ecid3);
+
+	printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
+
+	return 0;
+}
+
+u32 hcu_led_get(void)
+{
+	return in16(SYS_IO_ADDRESS) & 0x3f;
+}
+
+/*
+ * hcu_led_set  value to be placed into the LEDs (max 6 bit)
+ */
+void hcu_led_set(u32 value)
+{
+	out16(SYS_IO_ADDRESS, value);
+}
+
+/*
+ * get_serial_number
+ */
+u32 get_serial_number(void)
+{
+	u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
+
+	if (in_be32(serial) == 0xffffffff)
+		return 0;
+
+	return in_be32(serial);
+}
+
+
+/*
+ * hcu_get_slot
+ */
+u32 hcu_get_slot(void)
+{
+	u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
+	return in_be16(slot) & 0x7f;
+}
+
+
+/*
+ * misc_init_r.
+ */
+int misc_init_r(void)
+{
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+#endif
+#endif
+
+	/*
+	 * USB stuff...
+	 */
+
+	/* SDR Setting */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_USB2D0CR, usb2d0cr);
+	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+
+	/* An 8-bit/60MHz interface is the only possible alternative
+	 *  when connecting the Device to the PHY
+	 */
+	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+
+	/* To enable the USB 2.0 Device function through the UTMI interface */
+	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
+
+	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
+
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+	mtsdr(SDR0_USB2D0CR, usb2d0cr);
+	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	/*clear resets*/
+	udelay(1000);
+	mtsdr(SDR0_SRST1, 0x00000000);
+	udelay(1000);
+	mtsdr(SDR0_SRST0, 0x00000000);
+	printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	common_misc_init_r();
+	set_params_for_sw_install( sys_install_requested(), "hcu5" );
+	/* We cannot easily enable trace before, as there are other
+	 * routines messing around with sdr0_pfc1. And I do not need it.
+	 */
+	if (mfspr(SPRN_DBCR0) & 0x80000000) {
+		/* External debugger alive
+		 * enable trace facilty for Lauterbach
+		 * CCR0[DTB]=0		Enable broadcast of trace information
+		 * SDR0_PFC0[TRE]	Trace signals are enabled instead of
+		 *			GPIO49-63
+		 */
+	        mtspr(SPRN_CCR0, mfspr(SPRN_CCR0)  &~ (CCR0_DTB));
+		mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
+	}
+	return 0;
+}
+#ifdef CONFIG_PCI
+int board_with_pci(void)
+{
+	u32 reg;
+
+	mfsdr(SDR0_PCI0, reg);
+	return (reg & SDR0_PCI0_PAE_MASK);
+}
+
+/*
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	if (!board_with_pci()) { return 0; }
+
+	/*
+	 * Set priority for all PLB3 devices to 0.
+	 * Set PLB3 arbiter to fair mode.
+	 */
+	mfsdr(SDR0_AMP1, addr);
+	mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(PLB3A0_ACR);
+	mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
+
+	/*
+	 * Set priority for all PLB4 devices to 0.
+	 */
+	mfsdr(SDR0_AMP0, addr);
+	mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(PLB4A0_ACR) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(PLB4A0_ACR, addr);  /* Sequoia */
+
+	/*
+	 * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
+	 * Workaround: Disable write pipelining to DDR SDRAM by setting
+	 * PLB4A0_ACR[WRP] = 0.
+	 */
+	mtdcr(PLB4A0_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
+
+	/* Segment1 */
+	mtdcr(PLB4A1_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
+
+	return board_with_pci();
+}
+
+/*
+ * Override weak default pci_master_init()
+ */
+void pci_master_init(struct pci_controller *hose)
+{
+	if (!board_with_pci())
+		return;
+
+	__pci_master_init(hose);
+}
+#endif	 /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = 1;
+		info->chipwidth = 1;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/u-boot/board/netstal/hcu5/init.S b/u-boot/board/netstal/hcu5/init.S
new file mode 100644
index 0000000..45e63dd
--- /dev/null
+++ b/u-boot/board/netstal/hcu5/init.S
@@ -0,0 +1,106 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
+	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
+	/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
+		AC_RWX | SA_IG )
+
+	/* TLB#2: TLB-entry for EBC */
+	tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
+
+	/*
+	 * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
+	 * off to use the speed up boot process. It is patched after relocation
+	 * to enable SA_I
+	 */
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
+		AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	/* TLB#4: */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
+		AC_RW | SA_IG )
+	/* TLB#5: */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
+		AC_RW | SA_IG )
+	/* TLB#6: */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
+		AC_RW | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	/* TLB#7: */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
+		AC_RWX | SA_IG )
+
+	/*TLB-entry PCI registers*/
+	/* TLB#8: */
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
+
+	/* TLB-entry for peripherals */
+	/* TLB#9: */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	/*		CAN */
+	/* TLB#10: */
+	tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
+
+	/* TLB#11:  CPLD and IMC-Standard 32 MB */
+	tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
+
+	/* TLB#12: */
+	tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
+		AC_RWX | SA_IG )
+
+	 /*		IMC-Fast 32 MB */
+	/* TLB#13: */
+	tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
+	/* TLB#14: */
+	tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
+		AC_RWX | SA_IG )
+
+	tlbtab_end
diff --git a/u-boot/board/netstal/hcu5/sdram.c b/u-boot/board/netstal/hcu5/sdram.c
new file mode 100644
index 0000000..e5ac46b
--- /dev/null
+++ b/u-boot/board/netstal/hcu5/sdram.c
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2007
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/ppc440.h>
+
+void hcu_led_set(u32 value);
+void dcbz_area(u32 start_address, u32 num_bytes);
+
+#define ECC_RAM				0x03267F0B
+#define NO_ECC_RAM			0x00267F0B
+
+#define HCU_HW_SDRAM_CONFIG_MASK	0x7
+
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
+	/* disable caching on DDR2 */
+
+void board_add_ram_info(int use_default)
+{
+	PPC4xx_SYS_INFO board_cfg;
+	u32 val;
+
+	mfsdram(DDR0_22, val);
+	val &= DDR0_22_CTRL_RAW_MASK;
+	switch (val) {
+	case DDR0_22_CTRL_RAW_ECC_DISABLE:
+		puts(" (ECC disabled");
+		break;
+	case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
+		puts(" (ECC check only");
+		break;
+	case DDR0_22_CTRL_RAW_NO_ECC_RAM:
+		puts(" (no ECC ram");
+		break;
+	case DDR0_22_CTRL_RAW_ECC_ENABLE:
+		puts(" (ECC enabled");
+		break;
+	}
+
+	get_sys_info(&board_cfg);
+	printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+	mfsdram(DDR0_03, val);
+	val = DDR0_03_CASLAT_DECODE(val);
+	printf(", CL%d)", val);
+}
+
+/*--------------------------------------------------------------------
+ * wait_for_dlllock.
+ *--------------------------------------------------------------------*/
+static int wait_for_dlllock(void)
+{
+	unsigned long val;
+	int wait = 0;
+
+	/* -----------------------------------------------------------+
+	 * Wait for the DCC master delay line to finish calibration
+	 * ----------------------------------------------------------*/
+	mtdcr(SDRAM0_CFGADDR, DDR0_17);
+	val = DDR0_17_DLLLOCKREG_UNLOCKED;
+
+	while (wait != 0xffff) {
+		val = mfdcr(SDRAM0_CFGDATA);
+		if ((val & DDR0_17_DLLLOCKREG_MASK) ==
+		    DDR0_17_DLLLOCKREG_LOCKED)
+			/* dlllockreg bit on */
+			return 0;
+		else
+			wait++;
+	}
+	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+	debug("Waiting for dlllockreg bit to raise\n");
+
+	return -1;
+}
+
+/***********************************************************************
+ *
+ * sdram_panic -- Panic if we cannot configure the sdram correctly
+ *
+ ************************************************************************/
+void sdram_panic(const char *reason)
+{
+	printf("\n%s: reason %s",  __FUNCTION__,  reason);
+	hcu_led_set(0xff);
+	while (1) {
+	}
+	/* Never return */
+}
+
+#ifdef CONFIG_DDR_ECC
+void blank_string(int size)
+{
+	int i;
+
+	for (i=0; i<size; i++)
+		putc('\b');
+	for (i=0; i<size; i++)
+		putc(' ');
+	for (i=0; i<size; i++)
+		putc('\b');
+}
+/*---------------------------------------------------------------------------+
+ * program_ecc.
+ *---------------------------------------------------------------------------*/
+static void program_ecc(unsigned long start_address, unsigned long num_bytes)
+{
+	u32 val;
+	char str[] = "ECC generation -";
+#if defined(CONFIG_PRAM)
+	u32 *magicPtr;
+	u32 magic;
+
+	if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
+		/* only if no external debugger is alive!
+		 * Check whether vxWorks is using EDR logging, if yes zero
+		 * also PostMortem and user reserved memory
+		 */
+		magicPtr = (u32 *)(start_address + num_bytes -
+				(CONFIG_PRAM*1024) + sizeof(u32));
+		magic = in_be32(magicPtr);
+		debug("%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
+		      __FUNCTION__, CONFIG_PRAM,
+		      magicPtr, magic);
+		if (magic == 0xbeefbabe) {
+			printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
+			num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
+		}
+	}
+#endif
+
+	sync();
+
+	puts(str);
+
+	/* ECC bit set method for cached memory */
+	/* Fast method, no noticeable delay */
+	dcbz_area(start_address, num_bytes);
+	/* Write modified dcache lines back to memory */
+	clean_dcache_range(start_address, start_address + num_bytes);
+	blank_string(strlen(str));
+
+	/* Clear error status */
+	mfsdram(DDR0_00, val);
+	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+	/*
+	 * Clear possible ECC errors
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
+
+	/* Set 'int_mask' parameter to functionnal value */
+	mfsdram(DDR0_01, val);
+	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
+			  DDR0_01_INT_MASK_ALL_OFF));
+
+	return;
+}
+#endif
+
+
+/***********************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+	unsigned int dram_size = 0;
+
+	mtsdram(DDR0_02, 0x00000000);
+
+	/* Values must be kept in sync with Excel-table <<A0001492.>> ! */
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030602);
+	mtsdram(DDR0_04, 0x0A020200);
+	mtsdram(DDR0_05, 0x02020307);
+	switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
+	case 1:
+		dram_size = 256 * 1024 * 1024 ;
+		mtsdram(DDR0_06, 0x0102C812);  /* 256MB RAM */
+		mtsdram(DDR0_11, 0x0014C800);  /* 256MB RAM */
+		mtsdram(DDR0_43, 0x030A0200);  /* 256MB RAM */
+		break;
+	case 0:
+	default:
+		dram_size = 128 * 1024 * 1024 ;
+		mtsdram(DDR0_06, 0x0102C80D);  /* 128MB RAM */
+		mtsdram(DDR0_11, 0x000FC800);  /* 128MB RAM */
+		mtsdram(DDR0_43, 0x030A0300);  /* 128MB RAM */
+		break;
+	}
+	mtsdram(DDR0_07, 0x00090100);
+
+	/*
+	 * TCPD=200 cycles of clock input is required to lock the DLL.
+	 * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
+	 */
+	mtsdram(DDR0_08, 0x02C80001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000100);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x1D000000);
+	mtsdram(DDR0_18, 0x1D1D1D1D);
+	mtsdram(DDR0_19, 0x1D1D1D1D);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+	mtsdram(DDR0_22, ECC_RAM);
+#else
+	mtsdram(DDR0_22, NO_ECC_RAM);
+#endif
+
+	mtsdram(DDR0_23, 0x00000000);
+	mtsdram(DDR0_24, 0x01020001);
+	mtsdram(DDR0_26, 0x2D930517);
+	mtsdram(DDR0_27, 0x00008236);
+	mtsdram(DDR0_28, 0x00000000);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000006);
+	mtsdram(DDR0_44, 0x00000003);
+	mtsdram(DDR0_02, 0x00000001);
+	wait_for_dlllock();
+	mtsdram(DDR0_00, 0x40000000);  /* Zero init bit */
+
+	/*
+	 * Program tlb entries for this size (dynamic)
+	 */
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
+	program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Setup 2nd TLB with same physical address but different virtual
+	 * address with cache enabled. This is done for fast ECC generation.
+	 */
+	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
+
+#ifdef CONFIG_DDR_ECC
+	/*
+	 * If ECC is enabled, initialize the parity bits.
+	 */
+	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
+#endif
+
+	return (dram_size);
+}
diff --git a/u-boot/board/netstal/mcu25/Makefile b/u-boot/board/netstal/mcu25/Makefile
new file mode 100644
index 0000000..a983de9
--- /dev/null
+++ b/u-boot/board/netstal/mcu25/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007-2008 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o \
+	../common/fixed_sdram.o \
+	../common/nm_bsp.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netstal/mcu25/README.txt b/u-boot/board/netstal/mcu25/README.txt
new file mode 100644
index 0000000..d25fddd
--- /dev/null
+++ b/u-boot/board/netstal/mcu25/README.txt
@@ -0,0 +1,59 @@
+MCU25 Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+0x70000000
+
+Chip-Select 3: CAN Interface
+----------------------------
+0x7800000
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+Our IO-Bus (slow version)
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+Our IO-Bus (fast, but not yet use)
+
+
+Memory Bank 1 -- SDRAM
+-------------------------------------
+
+0x00000000 - 0x2ffffff   # Default 64 MB
diff --git a/u-boot/board/netstal/mcu25/config.mk b/u-boot/board/netstal/mcu25/config.mk
new file mode 100644
index 0000000..61dc091
--- /dev/null
+++ b/u-boot/board/netstal/mcu25/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+#     Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: MCU25 board
+#
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
diff --git a/u-boot/board/netstal/mcu25/mcu25.c b/u-boot/board/netstal/mcu25/mcu25.c
new file mode 100644
index 0000000..36fb388
--- /dev/null
+++ b/u-boot/board/netstal/mcu25/mcu25.c
@@ -0,0 +1,197 @@
+/*
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
+ *    Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include  <common.h>
+#include  <asm/ppc4xx.h>
+#include  <asm/processor.h>
+#include  <asm/io.h>
+#include  <asm/u-boot.h>
+#include  "../common/nm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MCU25_SLOT_ADDRESS		(0x7A000000 + 0x0A)
+#define MCU25_DIGITAL_IO_REGISTER	(0x7A000000 + 0xc0)
+
+#define MCU25_LED_REGISTER_ADDRESS	(0x7C000000 + 0x10)
+#define MCU25_VERSIONS_REGISTER	(0x7C000000 + 0x0C)
+#define MCU25_IO_CONFIGURATION		(0x7C000000 + 0x0e)
+#define MCU_SW_INSTALL_REQUESTED	0x08
+
+#define SDRAM_LEN	(32 << 20)	/* 32 MB - RAM */
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+/* Attention: If you want 1 microsecs times from the external oscillator
+ * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
+ * 0x00804051 causes problems with u-boot and linux!
+ */
+#define CPC0_CR0_VALUE	0x0007F03C
+#define CPC0_CR1_VALUE	0x00004051
+
+int board_early_init_f (void)
+{
+	/* Documented in A-1171
+	 *
+	 * Interrupt controller setup for the MCU25 board.
+	 * Note: IRQ 0-15  405GP internally generated; high; level sensitive
+	 *       IRQ 16    405GP internally generated; low; level sensitive
+	 *      IRQ 17-24 RESERVED/UNUSED
+	 *      IRQ 31 (EXT IRQ 6) (unused)
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
+	mtdcr(CPC0_ECR, 0x60606000);
+	mtdcr(CPC0_EIRR, 0x7C000000);
+	out32(GPIO0_OR,		CONFIG_SYS_GPIO0_OR );
+	out32(GPIO0_TCR,	CONFIG_SYS_GPIO0_TCR);
+	out32(GPIO0_ODR,	CONFIG_SYS_GPIO0_ODR);
+	mtspr(SPRN_CCR0,      0x00700000);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+	return board_early_init_f ();
+}
+#endif
+
+int sys_install_requested(void)
+{
+	u16 ioValue = in_be16((u16 *)MCU25_DIGITAL_IO_REGISTER);
+	return (ioValue & MCU_SW_INSTALL_REQUESTED) != 0;
+}
+
+int checkboard (void)
+{
+	u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER);
+	u16 hwConfig   = in_be16((u16 *)MCU25_IO_CONFIGURATION);
+	u16 generation = boardVersReg & 0x0f;
+	u16 index      = boardVersReg & 0xf0;
+
+	/* Cannot be done in board_early_init */
+	mtdcr(CPC0_CR0,  CPC0_CR0_VALUE);
+
+	/* Force /RTS to active. The board it not wired quite
+	 * correctly to use cts/rtc flow control, so just force the
+	 * /RST active and forget about it.
+	 */
+	writeb (readb (0xef600404) | 0x03, 0xef600404);
+	nm_show_print(generation, index, hwConfig);
+	return 0;
+}
+
+u32 hcu_led_get(void)
+{
+	return in_be16((u16 *)MCU25_LED_REGISTER_ADDRESS) & 0x3ff;
+}
+
+/*
+ * hcu_led_set  value to be placed into the LEDs (max 6 bit)
+ */
+void hcu_led_set(u32 value)
+{
+   out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value);
+}
+
+/*
+ * hcu_get_slot
+ */
+u32 hcu_get_slot(void)
+{
+	u16 slot = in_be16((u16 *)MCU25_SLOT_ADDRESS);
+	return slot & 0x7f;
+}
+
+/*
+ * get_serial_number
+ */
+u32 get_serial_number(void)
+{
+	u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
+
+	if (serial == 0xffffffff)
+		return 0;
+
+	return serial;
+}
+
+
+/*
+ * misc_init_r.
+ */
+
+int misc_init_r(void)
+{
+	common_misc_init_r();
+	set_params_for_sw_install( sys_install_requested(), "mcu25" );
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned int dram_size = 64*1024*1024;
+	init_ppc405_sdram(dram_size);
+
+#ifdef DEBUG
+	show_sdram_registers();
+#endif
+
+	return dram_size;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = 1;
+		info->chipwidth = 1;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/u-boot/board/netstar/Makefile b/u-boot/board/netstar/Makefile
new file mode 100644
index 0000000..7230a2f
--- /dev/null
+++ b/u-boot/board/netstar/Makefile
@@ -0,0 +1,95 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= netstar.o
+SOBJS	:= setup.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+LOAD_ADDR = 0x10400000
+
+#########################################################################
+
+all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
+		$(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+$(obj)eeprom_start.o:
+	echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
+
+$(obj)eeprom:		$(obj)eeprom_start.o $(obj)eeprom.o
+	$(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
+		-L$(obj)../../examples/standalone -lstubs \
+		$(PLATFORM_LIBS)
+
+$(obj)eeprom.srec:	$(obj)eeprom
+	$(OBJCOPY) -S -O srec $(<:.o=) $@
+
+$(obj)eeprom.bin:	$(obj)eeprom
+	$(OBJCOPY) -S -O binary $< $@
+
+$(obj)crcek.srec:	$(obj)crcek.o
+	$(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^
+	$(OBJCOPY) -S -O srec $(<:.o=) $@
+
+$(obj)crcek.bin:	$(obj)crcek.srec
+	$(OBJCOPY) -I srec -O binary $< $@
+
+$(obj)crcit:		$(obj)crcit.o $(obj)crc32.o
+	$(HOSTCC) $(HOSTCFLAGS) -o $@ $^
+
+$(obj)crcit.o:		crcit.c
+	$(HOSTCC) $(HOSTCFLAGS) -o $@ -c $<
+
+$(obj)crc32.o:		$(SRCTREE)/lib/crc32.c
+	$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \
+		-o $@ -c $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) \
+		$(obj)eeprom_start.o $(obj)eeprom.o \
+		$(obj)eeprom $(obj)eeprom.srec 	$(obj)eeprom.bin \
+		$(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netstar/config.mk b/u-boot/board/netstar/config.mk
new file mode 100644
index 0000000..9e1446e
--- /dev/null
+++ b/u-boot/board/netstar/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing CONFIG_SYS_TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX CONFIG_SYS_TEXT_BASE = 0x20012000
+CONFIG_SYS_TEXT_BASE = 0x13FC0000
diff --git a/u-boot/board/netstar/crcek.S b/u-boot/board/netstar/crcek.S
new file mode 100644
index 0000000..af35662
--- /dev/null
+++ b/u-boot/board/netstar/crcek.S
@@ -0,0 +1,241 @@
+/**
+ * (C) Copyright 2005
+ * 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2.
+ *
+ * Image layout looks like following:
+ *	u32 - size
+ *	u32 - version
+ *	... - data
+ *	u32 - crc32
+ */
+
+#include <config.h>
+#include "crcek.h"
+
+/**
+ * do_crc32 - calculate CRC32 of given buffer
+ * r0 - crc
+ * r1 - pointer to buffer
+ * r2 - buffer len
+ */
+	.macro	do_crc32
+	ldr	r5, FFFFFFFF
+	eor	r0, r0, r5
+	adr	r3, CRC32_TABLE
+1:
+	ldrb    r4, [r1], #1
+	eor	r4, r4, r0
+	and	r4, r4, #0xff
+	ldr	r4, [r3, r4, lsl#2]
+	eor	r0, r4, r0, lsr#8
+	subs	r2, r2, #0x1
+	bne	1b
+	eor	r0, r0, r5
+	.endm
+
+	.macro crcuj, offset, size
+	mov	r0, #0
+	ldr	r1, \offset
+	ldr	r2, [r1], #4
+	cmp	r2, r0		@ no data, no problem
+	beq	2f
+	tst	r2, #3		@ unaligned size
+	bne	2f
+	ldr	r3, \size
+	cmp	r2, r3		@ bogus size
+	bhi	2f
+	do_crc32
+	ldr	r1, [r1]
+2:
+	cmp	r0, r1
+	.endm
+
+	.macro wait, reg
+	mov	\reg, #0x100000
+3:
+	subs	\reg, \reg, #0x1
+	bne	3b
+	.endm
+
+.text
+.globl crcek
+crcek:
+	/* Enable I-cache */
+	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
+	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
+	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
+	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
+	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
+	mov	r1, #0x00
+	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
+	nop
+	nop
+	nop
+	nop
+
+	/* Setup clocking mode */
+	ldr	r0, MPU_CLKM_BASE		@ base of CLOCK unit
+	ldrh	r1, [r0, #0x18]			@ ARM_SYST - get reset status
+	bic	r1, r1, #(7 << 11)		@ clear clock select
+	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
+	mov	r2, #0
+loop:
+	cmp	r2, #1				@ this loop will wait for at least 100 cycles
+	streqh	r1, [r0, #0x18]			@ before issuing next request from MPU
+	add	r2, r2, #1			@ on the 1st run code is loaded into I-cache
+	cmp	r2, #16				@ and second run will set clocking mode
+	bne	loop
+	nop
+
+	/* Setup clock dividers */
+	ldr	r1, CKCTL_VAL
+	orr	r1, r1, #0x2000			@ enable DSP clock
+	strh	r1, [r0]			@ setup clock divisors
+
+	/* Setup DPLL to generate requested freq */
+	ldr	r0, DPLL1_BASE			@ base of DPLL1 register
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+	strh	r1, [r0]			@ write
+
+locking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #0x01
+	beq	locking				@ while LOCK not set
+
+	/* Enable clock */
+	ldr	r0, MPU_CLKM_BASE		@ base of CLOCK unit
+	mov	r1, #(1 << 10)			@ disable idle mode do not check
+						@ nWAKEUP pin, other remain active
+	strh	r1, [r0, #0x04]
+	ldr	r1, EN_CLK_VAL
+	strh	r1, [r0, #0x08]
+	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
+	strh	r1, [r0, #0x0c]			@ max delayed ( 32 x CLKIN )
+
+
+	mov	r6, #0
+	crcuj	_LOADER1_OFFSET, _LOADER_SIZE
+	bne	crc1_bad
+	orr	r6, r6, #1
+crc1_bad:
+	crcuj	_LOADER2_OFFSET, _LOADER_SIZE
+	bne	crc2_bad
+	orr	r6, r6, #2
+crc2_bad:
+	ldr	r3, _LOADER1_OFFSET
+	ldr	r4, _LOADER2_OFFSET
+	teq	r6, #3
+	bne	one_is_bad	@ one of them (or both) has bad crc
+	ldr	r1, [r3, #4]
+	ldr	r2, [r4, #4]
+	cmp	r1, r2		@ boot 2nd loader if versions differ
+	beq	boot_1st
+	b	boot_2nd
+one_is_bad:
+	tst	r6, #1
+	bne	boot_1st
+	tst	r6, #2
+	bne	boot_2nd
+@ We are doomed, so let user know.
+hell:
+	ldr	r0, GPIO_BASE	@ configure GPIO pins
+	ldr	r1, GPIO_DIRECTION
+	strh	r1, [r0, #0x08]
+blink_loop:
+	mov	r1, #0x08
+	strh    r1, [r0, #0x04]
+	wait	r3
+	mov	r1, #0x10
+	strh    r1, [r0, #0x04]
+	wait	r3
+	b blink_loop
+boot_1st:
+	add	pc, r3, #8
+boot_2nd:
+	add	pc, r4, #8
+
+_LOADER_SIZE:
+	.word LOADER_SIZE - 8	@ minus size and crc32
+_LOADER1_OFFSET:
+	.word LOADER1_OFFSET
+_LOADER2_OFFSET:
+	.word LOADER2_OFFSET
+
+FFFFFFFF:
+	.word 0xffffffff
+CRC32_TABLE:
+	.word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419
+	.word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4
+	.word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07
+	.word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de
+	.word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856
+	.word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9
+	.word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4
+	.word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b
+	.word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3
+	.word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a
+	.word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599
+	.word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924
+	.word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190
+	.word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f
+	.word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e
+	.word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01
+	.word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed
+	.word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950
+	.word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3
+	.word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2
+	.word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a
+	.word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5
+	.word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010
+	.word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f
+	.word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17
+	.word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6
+	.word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615
+	.word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8
+	.word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344
+	.word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb
+	.word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a
+	.word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5
+	.word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1
+	.word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c
+	.word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef
+	.word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236
+	.word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe
+	.word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31
+	.word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c
+	.word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713
+	.word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b
+	.word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242
+	.word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1
+	.word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c
+	.word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278
+	.word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7
+	.word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66
+	.word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9
+	.word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605
+	.word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8
+	.word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b
+	.word 0x2d02ef8d
+
+GPIO_BASE:
+	.word 0xfffce000
+MPU_CLKM_BASE:
+	.word 0xfffece00
+DPLL1_BASE:
+	.word 0xfffecf00
+
+CKCTL_VAL:
+	.word OMAP5910_ARM_CKCTL
+EN_CLK_VAL:
+	.word OMAP5910_ARM_EN_CLK
+GPIO_DIRECTION:
+	.word 0x0000ffe7
+
+.end
diff --git a/u-boot/board/netstar/crcek.h b/u-boot/board/netstar/crcek.h
new file mode 100644
index 0000000..30c0860
--- /dev/null
+++ b/u-boot/board/netstar/crcek.h
@@ -0,0 +1,3 @@
+#define LOADER_SIZE	(448 * 1024)
+#define LOADER1_OFFSET	(128 * 1024)
+#define LOADER2_OFFSET	(LOADER1_OFFSET + LOADER_SIZE)
diff --git a/u-boot/board/netstar/crcit.c b/u-boot/board/netstar/crcit.c
new file mode 100644
index 0000000..a162649
--- /dev/null
+++ b/u-boot/board/netstar/crcit.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2005
+ * 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include "crcek.h"
+
+extern uint32_t crc32(uint32_t, const unsigned char *, uint);
+
+static uint32_t data[LOADER_SIZE/4 + 3];
+
+static int do_crc(char *path, unsigned version)
+{
+	uint32_t *p;
+	ssize_t size;
+	int fd;
+
+	fd = open(path, O_RDONLY);
+	if (fd == -1) {
+		perror("Error opening file");
+		return EXIT_FAILURE;
+	}
+	p = data + 2;
+	size = read(fd, p, LOADER_SIZE + 4);
+	if (size == -1) {
+		perror("Error reading file");
+		return EXIT_FAILURE;
+	}
+	if (size > LOADER_SIZE) {
+		fprintf(stderr, "File too large\n");
+		return EXIT_FAILURE;
+	}
+	size  = (size + 3) & ~3;	/* round up to 4 bytes */
+	size += 4;			/* add size of version field */
+	data[0] = size;
+	data[1] = version;
+	data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size);
+	close(fd);
+
+	if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) {
+		perror("Error writing file");
+		return EXIT_FAILURE;
+	}
+
+	return EXIT_SUCCESS;
+}
+
+int main(int argc, char * const *argv)
+{
+	if (argc == 2) {
+		return do_crc(argv[1], 0);
+	} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
+		char *endptr, *nptr = argv[2];
+		unsigned ver = strtoul(nptr, &endptr, 0);
+		if (*nptr != '\0' && *endptr == '\0')
+			return do_crc(argv[3], ver);
+	}
+	fprintf(stderr, "Usage: crcit [-v version] <image>\n");
+
+	return EXIT_FAILURE;
+}
diff --git a/u-boot/board/netstar/eeprom.c b/u-boot/board/netstar/eeprom.c
new file mode 100644
index 0000000..aa375a4
--- /dev/null
+++ b/u-boot/board/netstar/eeprom.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <timestamp.h>
+#include <net.h>
+#include "../drivers/net/smc91111.h"
+
+static struct eth_device dev = {
+	.iobase = CONFIG_SMC91111_BASE
+};
+
+static u16 read_eeprom_reg(u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_RELOAD, CTL_REG);
+
+	timeout = 100;
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout reading register %02x\n", reg);
+		return 0;
+	}
+
+	return SMC_inw(&dev, GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+
+	SMC_outw(&dev, value, GP_REG);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_STORE, CTL_REG);
+
+	timeout = 100;
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout writing register %02x\n", reg);
+		return 0;
+	}
+
+	return 1;
+}
+
+static int write_data(u16 *buf, int len)
+{
+	u16 reg = 0x23;
+
+	while (len--)
+		write_eeprom_reg(*buf++, reg++);
+
+	return 0;
+}
+
+static int verify_macaddr(char *s)
+{
+	u16 reg;
+	int i, err = 0;
+
+	puts("HWaddr: ");
+	for (i = 0; i < 3; i++) {
+		reg = read_eeprom_reg(0x20 + i);
+		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+		if (s)
+			err |= reg != ((u16 *)s)[i];
+	}
+
+	return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+	int i;
+	char *e, eaddr[6];
+
+	/* turn string into mac value */
+	for (i = 0; i < 6; i++) {
+		eaddr[i] = simple_strtoul(s, &e, 16);
+		s = (*e) ? e+1 : e;
+	}
+
+	for (i = 0; i < 3; i++)
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+	return 0;
+}
+
+static int parse_element(char *s, unsigned char *buf, int len)
+{
+	int cnt;
+	char *p, num[3];
+	unsigned char id;
+
+	id = simple_strtoul(s, &p, 16);
+	if (*p++ != ':')
+		return -1;
+	cnt = 2;
+	num[2] = 0;
+	for (; *p; p += 2) {
+		if (p[1] == 0)
+			return -2;
+		if (cnt + 3 > len)
+			return -3;
+		num[0] = p[0];
+		num[1] = p[1];
+		buf[cnt++] = simple_strtoul(num, NULL, 16);
+	}
+	buf[0] = id;
+	buf[1] = cnt - 2;
+
+	return cnt;
+}
+
+int eeprom(int argc, char * const argv[])
+{
+	int i, len, ret;
+	unsigned char buf[58], *p;
+
+	app_startup(argv);
+	i = get_version();
+	if (i != XF_VERSION) {
+		printf("Using ABI version %d, but U-Boot provides %d\n",
+			XF_VERSION, i);
+		return 1;
+	}
+
+	if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
+		puts("SMSC91111 not found\n");
+		return 2;
+	}
+
+	/* Called without parameters - print MAC address */
+	if (argc < 2) {
+		verify_macaddr(NULL);
+		return 0;
+	}
+
+	/* Print help message */
+	if (argv[1][1] == 'h') {
+		puts("NetStar EEPROM writer\n"
+			"Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
+			"Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+		return 0;
+	}
+
+	/* Try to parse information elements */
+	len = sizeof(buf);
+	p = buf;
+	for (i = 2; i < argc; i++) {
+		ret = parse_element(argv[i], p, len);
+		switch (ret) {
+		case -1:
+			printf("Element %d: malformed\n", i - 1);
+			return 3;
+		case -2:
+			printf("Element %d: odd character count\n", i - 1);
+			return 3;
+		case -3:
+			puts("Out of EEPROM memory\n");
+			return 3;
+		default:
+			p += ret;
+			len -= ret;
+		}
+	}
+
+	/* First argument (MAC) is mandatory */
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		puts("*** HWaddr does not match! ***\n");
+		return 4;
+	}
+
+	while (len--)
+		*p++ = 0;
+
+	write_data((u16 *)buf, sizeof(buf) >> 1);
+
+	return 0;
+}
diff --git a/u-boot/board/netstar/netstar.c b/u-boot/board/netstar/netstar.c
new file mode 100644
index 0000000..df1704b
--- /dev/null
+++ b/u-boot/board/netstar/netstar.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <flash.h>
+#include <nand.h>
+
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of NetStar board */
+	gd->bd->bi_arch_number = MACH_TYPE_NETSTAR;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	/* Take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete. */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+	udelay(10);	/* doesn't work before timer_init call */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+	udelay(500);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_RTC_DS1307)
+	/* enable trickle charge */
+	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0x10, 0xaa);
+#endif
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_CMD_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t * info)
+{
+	if (banknum == 0) {	/* AM29LV800 boot flash */
+		info->portwidth = FLASH_CFI_16BIT;
+		info->chipwidth = FLASH_CFI_BY16;
+		info->interface = FLASH_CFI_X16;
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+/*
+ *	hardware specific access to control-lines
+ *
+ *	NAND_NCE: bit 0 - don't care
+ *	NAND_CLE: bit 1 -> bit 1  (0x0002)
+ *	NAND_ALE: bit 2 -> bit 2  (0x0004)
+ */
+static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+	unsigned int ctrl)
+{
+	struct nand_chip *chip = mtd->priv;
+	unsigned long mask;
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+	if (ctrl & NAND_ALE)
+		mask |= 0x04;
+	writeb(cmd, (unsigned long)chip->IO_ADDR_W | mask);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = netstar_nand_hwcontrol;
+	nand->chip_delay = 400;
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/netstar/setup.S b/u-boot/board/netstar/setup.S
new file mode 100644
index 0000000..72e1811
--- /dev/null
+++ b/u-boot/board/netstar/setup.S
@@ -0,0 +1,284 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE:		.word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE:	.word 0xfffbc800
+OMAP5910_MPU_TC_BASE:		.word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE:		.word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE:	.word 0xfffe0800
+OMAP5910_DPLL1_BASE:		.word 0xfffecf00
+OMAP5910_GPIO_BASE:		.word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE:	.word 0xfffec800
+OMAP5910_MPUI_BASE:		.word 0xfffec900
+
+_OMAP5910_ARM_CKCTL:		.word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK:		.word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL:		.word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG:		.word 0x00009090
+VAL_EMIFS_CS1_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS2_CONFIG:		.word 0x0000a0a1
+VAL_EMIFS_CS3_CONFIG:		.word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT:		.word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+				/*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
+
+#if (PHYS_SDRAM_1_SIZE == SZ_32M)
+VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+#else
+VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+#endif
+
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
+VAL_EMIFF_MRS:			.word 0x00000037
+
+/*
+ * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+	.word 0x0000ff6f
+/*
+ * Disable everything (green LED is connected via invertor)
+ */
+GPIO_OUTPUT:
+	.word 0x00000010
+
+MUX_CONFIG_BASE:
+	.word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+	.align 4
+	.word 0x00000000	@ FUNC_MUX_CTRL_0
+	.word 0x00000000	@ FUNC_MUX_CTRL_1
+	.word 0x00000000	@ FUNC_MUX_CTRL_2
+	.word 0x00000000	@ FUNC_MUX_CTRL_3
+	.word 0x00000000	@ FUNC_MUX_CTRL_4
+	.word 0x02080480	@ FUNC_MUX_CTRL_5
+	.word 0x0100001c	@ FUNC_MUX_CTRL_6
+	.word 0x0004800b	@ FUNC_MUX_CTRL_7
+	.word 0x10001200	@ FUNC_MUX_CTRL_8
+	.word 0x01201012	@ FUNC_MUX_CTRL_9
+	.word 0x02082248	@ FUNC_MUX_CTRL_A
+	.word 0x00000248	@ FUNC_MUX_CTRL_B
+	.word 0x12240000	@ FUNC_MUX_CTRL_C
+	.word 0x00002000	@ FUNC_MUX_CTRL_D
+	.word 0x00000000	@ PULL_DWN_CTRL_0
+	.word 0x00000800	@ PULL_DWN_CTRL_1
+	.word 0x01801000	@ PULL_DWN_CTRL_2
+	.word 0x00000000	@ PULL_DWN_CTRL_3
+	.word 0x00000000	@ GATE_INH_CTRL_0
+	.word 0x00000000	@ VOLTAGE_CTRL_0
+	.word 0x00000000	@ TEST_DBG_CTRL_0
+	.word 0x00000006	@ MOD_CONF_CTRL_0
+	.word 0x0000eaef	@ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+	.align 1
+	.byte 0x00		@ FUNC_MUX_CTRL_0
+	.byte 0x04		@ FUNC_MUX_CTRL_1
+	.byte 0x08		@ FUNC_MUX_CTRL_2
+	.byte 0x10		@ FUNC_MUX_CTRL_3
+	.byte 0x14		@ FUNC_MUX_CTRL_4
+	.byte 0x18		@ FUNC_MUX_CTRL_5
+	.byte 0x1c		@ FUNC_MUX_CTRL_6
+	.byte 0x20		@ FUNC_MUX_CTRL_7
+	.byte 0x24		@ FUNC_MUX_CTRL_8
+	.byte 0x28		@ FUNC_MUX_CTRL_9
+	.byte 0x2c		@ FUNC_MUX_CTRL_A
+	.byte 0x30		@ FUNC_MUX_CTRL_B
+	.byte 0x34		@ FUNC_MUX_CTRL_C
+	.byte 0x38		@ FUNC_MUX_CTRL_D
+	.byte 0x40		@ PULL_DWN_CTRL_0
+	.byte 0x44		@ PULL_DWN_CTRL_1
+	.byte 0x48		@ PULL_DWN_CTRL_2
+	.byte 0x4c		@ PULL_DWN_CTRL_3
+	.byte 0x50		@ GATE_INH_CTRL_0
+	.byte 0x60		@ VOLTAGE_CTRL_0
+	.byte 0x70		@ TEST_DBG_CTRL_0
+	.byte 0x80		@ MOD_CONF_CTRL_0
+	.byte 0x0c		@ COMP_MODE_CTRL_0
+	.byte 0xff
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Improve performance a bit... */
+	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
+	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
+	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
+	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
+	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
+	mov	r1, #0x00
+	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
+	nop
+	nop
+	nop
+	nop
+
+	/* Setup clocking mode */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	ldrh	r1, [r0, #0x18]			@ ARM_SYST - get reset status
+	bic	r1, r1, #(7 << 11)		@ clear clock select
+	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
+	mov	r2, #0
+loop:
+	cmp	r2, #1				@ this loop will wait for at least 100 cycles
+	streqh	r1, [r0, #0x18]			@ before issuing next request from MPU
+	add	r2, r2, #1			@ on the 1st run code is loaded into I-cache
+	cmp	r2, #16				@ and second run will set clocking mode
+	bne	loop
+	nop
+
+	/* Setup clock dividers */
+	ldr	r1, _OMAP5910_ARM_CKCTL
+	orr	r1, r1, #0x2000			@ enable DSP clock
+	strh	r1, [r0]			@ setup clock divisors
+
+	/* Setup DPLL to generate requested freq */
+	ldr	r0, OMAP5910_DPLL1_BASE		@ base of DPLL1 register
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+	strh	r1, [r0]			@ write
+
+locking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #0x01
+	beq	locking				@ while LOCK not set
+
+	/* Enable clock */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	mov	r1, #(1 << 10)			@ disable idle mode do not check
+						@ nWAKEUP pin, other remain active
+	strh	r1, [r0, #0x04]
+	ldr	r1, _OMAP5910_ARM_EN_CLK
+	strh	r1, [r0, #0x08]
+	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
+	strh	r1, [r0, #0x0c]			@ max delayed ( 32 x CLKIN )
+
+	/* Configure 5910 pins functions to match our board. */
+	ldr     r0, MUX_CONFIG_BASE
+	adr	r1, MUX_CONFIG_VALUES
+	adr	r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+	ldrb	r3, [r2], #1
+	ldr	r4, [r1], #4
+	cmp	r3, #0xff
+	strne	r4, [r0, r3]
+	bne	next_mux_cfg
+
+	/* Configure GPIO pins (also disables Green LED) */
+	ldr	r0, OMAP5910_GPIO_BASE
+	ldr	r1, GPIO_OUTPUT
+	strh    r1, [r0, #0x04]
+	ldr	r1, GPIO_DIRECTION
+	strh	r1, [r0, #0x08]
+
+	/* EnablePeripherals */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ CLOCK unit
+	mov	r1, #0x0001			@ Peripheral enable
+	strh	r1, [r0, #0x14]
+
+	/* Program LED Pulse Generator */
+	ldr	r0, OMAP5910_LPG1_BASE		@ 1st LED Pulse Generator
+	mov	r1, #0x7F			@ Set obscure frequency in
+	strb	r1, [r0, #0x00]			@ LCR
+	mov	r1, #0x01			@ Enable clock (CLK_EN) in
+	strb    r1, [r0, #0x04]			@ PMR
+
+	/* TIPB Lock UART1 */
+	ldr	r0, OMAP5910_TIPB_SWITCHES_BASE	@ prepare base of TIPB switches
+	mov	r1, #1				@ ARM allocated
+	strh	r1, [r0,#0x04]			@ clear IRQ line and status bits
+	strh	r1, [r0,#0x00]
+	ldrh	r1, [r0,#0x04]
+
+	/* Disable watchdog */
+	ldr	r0, OMAP5910_MPU_WD_TIMER_BASE
+	mov	r1, #0xf5
+	strh	r1, [r0, #0x8]
+	mov	r1, #0xa0
+	strh	r1, [r0, #0x8]
+
+	/* Enable MCLK */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE
+	mov	r1, #0x6
+	strh	r1, [r0, #0x34]
+	strh	r1, [r0, #0x34]
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
+
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
+
+ulocking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #1
+	beq	ulocking			@ while LOCK not set
+
+	/* EMIF init */
+	ldr	r0, OMAP5910_MPU_TC_BASE
+	ldrh	r1, [r0, #0x0c]			@ EMIFS_CONFIG_REG
+	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x0c]
+
+	ldr	r1, VAL_EMIFS_CS0_CONFIG
+	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
+	ldr	r1, VAL_EMIFS_CS1_CONFIG
+	str	r1, [r0, #0x14]			@ EMIFS_CS1_CONFIG
+	ldr	r1, VAL_EMIFS_CS2_CONFIG
+	str	r1, [r0, #0x18]			@ EMIFS_CS2_CONFIG
+	ldr	r1, VAL_EMIFS_CS3_CONFIG
+	str	r1, [r0, #0x1c]			@ EMIFS_CS3_CONFIG
+	ldr	r1, VAL_EMIFS_DYN_WAIT
+	str	r1, [r0, #0x40]			@ EMIFS_CFG_DYN_WAIT
+
+	/* Setup SDRAM */
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG
+	str	r1, [r0, #0x20]			@ EMIFF_SDRAM_CONFIG
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG2
+	str	r1, [r0, #0x3c]			@ EMIFF_SDRAM_CONFIG2
+	ldr	r1, VAL_EMIFF_MRS
+	str	r1, [r0, #0x24]			@ EMIFF_MRS
+	/* SDRAM needs 100us to stabilize */
+	mov	r0, #0x4000
+sdelay:
+	subs	r0, r0, #0x1
+	bne	sdelay
+
+	/* back to arch calling code */
+	mov	pc, lr
+.end
diff --git a/u-boot/board/netta/Makefile b/u-boot/board/netta/Makefile
new file mode 100644
index 0000000..878151c
--- /dev/null
+++ b/u-boot/board/netta/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o dsp.o codec.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netta/codec.c b/u-boot/board/netta/codec.c
new file mode 100644
index 0000000..844aa18
--- /dev/null
+++ b/u-boot/board/netta/codec.c
@@ -0,0 +1,1484 @@
+/*
+ * CODEC
+ */
+
+#include <common.h>
+#include <post.h>
+
+#include "mpc8xx.h"
+
+/***********************************************/
+
+#define MAX_DUSLIC	4
+
+#define NUM_CHANNELS	2
+#define MAX_SLICS	(MAX_DUSLIC * NUM_CHANNELS)
+
+/***********************************************/
+
+#define SOP_READ_CH_0		0xC4  /* Read SOP Register for Channel A  */
+#define SOP_READ_CH_1		0xCC  /* Read SOP Register for Channel B  */
+#define SOP_WRITE_CH_0		0x44  /* Write SOP Register for Channel A */
+#define SOP_WRITE_CH_1		0x4C  /* Write SOP Register for Channel B */
+
+#define COP_READ_CH_0		0xC5
+#define COP_READ_CH_1		0xCD
+#define COP_WRITE_CH_0		0x45
+#define COP_WRITE_CH_1		0x4D
+
+#define POP_READ_CH_0		0xC6
+#define POP_READ_CH_1		0xCE
+#define POP_WRITE_CH_0		0x46
+#define POP_WRITE_CH_1		0x4E
+
+#define RST_CMD_DUSLIC_CHIP	0x40  /* OR 0x48 */
+#define RST_CMD_DUSLIC_CH_A	0x41
+#define RST_CMD_DUSLIC_CH_B	0x49
+
+#define PCM_RESYNC_CMD_CH_A	0x42
+#define PCM_RESYNC_CMD_CH_B	0x4A
+
+#define ACTIVE_HOOK_LEV_4	0
+#define ACTIVE_HOOK_LEV_12	1
+
+#define SLIC_P_NORMAL		0x01
+
+/************************************************/
+
+#define CODSP_WR	0x00
+#define CODSP_RD	0x80
+#define CODSP_OP	0x40
+#define CODSP_ADR(x)	(((unsigned char)(x) & 7) << 3)
+#define CODSP_M(x)	((unsigned char)(x) & 7)
+#define CODSP_CMD(x)	((unsigned char)(x) & 7)
+
+/************************************************/
+
+/* command indication ops */
+#define CODSP_M_SLEEP_PWRDN	7
+#define CODSP_M_PWRDN_HIZ	0
+#define CODSP_M_ANY_ACT		2
+#define CODSP_M_RING		5
+#define CODSP_M_ACT_MET		6
+#define CODSP_M_GND_START	4
+#define CODSP_M_RING_PAUSE	1
+
+/* single byte commands */
+#define CODSP_CMD_SOFT_RESET	CODSP_CMD(0)
+#define CODSP_CMD_RESET_CH	CODSP_CMD(1)
+#define CODSP_CMD_RESYNC	CODSP_CMD(2)
+
+/* two byte commands */
+#define CODSP_CMD_SOP		CODSP_CMD(4)
+#define CODSP_CMD_COP		CODSP_CMD(5)
+#define CODSP_CMD_POP		CODSP_CMD(6)
+
+/************************************************/
+
+/* read as 4-bytes */
+#define CODSP_INTREG_INT_CH	0x80000000
+#define CODSP_INTREG_HOOK	0x40000000
+#define CODSP_INTREG_GNDK	0x20000000
+#define CODSP_INTREG_GNDP	0x10000000
+#define CODSP_INTREG_ICON	0x08000000
+#define CODSP_INTREG_VRTLIM	0x04000000
+#define CODSP_INTREG_OTEMP	0x02000000
+#define CODSP_INTREG_SYNC_FAIL	0x01000000
+#define CODSP_INTREG_LM_THRES	0x00800000
+#define CODSP_INTREG_READY	0x00400000
+#define CODSP_INTREG_RSTAT	0x00200000
+#define CODSP_INTREG_LM_OK	0x00100000
+#define CODSP_INTREG_IO4_DU	0x00080000
+#define CODSP_INTREG_IO3_DU	0x00040000
+#define CODSP_INTREG_IO2_DU	0x00020000
+#define CODSP_INTREG_IO1_DU	0x00010000
+#define CODSP_INTREG_DTMF_OK	0x00008000
+#define CODSP_INTREG_DTMF_KEY4	0x00004000
+#define CODSP_INTREG_DTMF_KEY3	0x00002000
+#define CODSP_INTREG_DTMF_KEY2	0x00001000
+#define CODSP_INTREG_DTMF_KEY1	0x00000800
+#define CODSP_INTREG_DTMF_KEY0	0x00000400
+#define CODSP_INTREG_UTDR_OK	0x00000200
+#define CODSP_INTREG_UTDX_OK	0x00000100
+#define CODSP_INTREG_EDSP_FAIL	0x00000080
+#define CODSP_INTREG_CIS_BOF	0x00000008
+#define CODSP_INTREG_CIS_BUF	0x00000004
+#define CODSP_INTREG_CIS_REQ	0x00000002
+#define CODSP_INTREG_CIS_ACT	0x00000001
+
+/************************************************/
+
+/* ======== SOP REG ADDRESSES =======*/
+
+#define REVISION_ADDR		0x00
+#define PCMC1_ADDR		0x05
+#define XCR_ADDR		0x06
+#define INTREG1_ADDR		0x07
+#define INTREG2_ADDR		0x08
+#define INTREG3_ADDR		0x09
+#define INTREG4_ADDR		0x0A
+#define LMRES1_ADDR		0x0D
+#define MASK_ADDR		0x11
+#define IOCTL3_ADDR		0x14
+#define BCR1_ADDR		0x15
+#define BCR2_ADDR		0x16
+#define BCR3_ADDR		0x17
+#define BCR4_ADDR		0x18
+#define BCR5_ADDR		0x19
+#define DSCR_ADDR		0x1A
+#define LMCR1_ADDR		0x1C
+#define LMCR2_ADDR		0x1D
+#define LMCR3_ADDR		0x1E
+#define OFR1_ADDR		0x1F
+#define PCMR1_ADDR		0x21
+#define PCMX1_ADDR		0x25
+#define TSTR3_ADDR		0x2B
+#define TSTR4_ADDR		0x2C
+#define TSTR5_ADDR		0x2D
+
+/* ========= POP REG ADDRESSES ========*/
+
+#define CIS_DAT_ADDR		0x00
+
+#define LEC_LEN_ADDR		0x3A
+#define LEC_POWR_ADDR		0x3B
+#define LEC_DELP_ADDR		0x3C
+#define LEC_DELQ_ADDR		0x3D
+#define LEC_GAIN_XI_ADDR	0x3E
+#define LEC_GAIN_RI_ADDR	0x3F
+#define LEC_GAIN_XO_ADDR	0x40
+#define LEC_RES_1_ADDR		0x41
+#define LEC_RES_2_ADDR		0x42
+
+#define NLP_POW_LPF_ADDR	0x30
+#define NLP_POW_LPS_ADDR	0x31
+#define NLP_BN_LEV_X_ADDR	0x32
+#define NLP_BN_LEV_R_ADDR	0x33
+#define NLP_BN_INC_ADDR		0x34
+#define NLP_BN_DEC_ADDR		0x35
+#define NLP_BN_MAX_ADDR		0x36
+#define NLP_BN_ADJ_ADDR		0x37
+#define NLP_RE_MIN_ERLL_ADDR	0x38
+#define NLP_RE_EST_ERLL_ADDR	0x39
+#define NLP_SD_LEV_X_ADDR	0x3A
+#define NLP_SD_LEV_R_ADDR	0x3B
+#define NLP_SD_LEV_BN_ADDR	0x3C
+#define NLP_SD_LEV_RE_ADDR	0x3D
+#define NLP_SD_OT_DT_ADDR	0x3E
+#define NLP_ERL_LIN_LP_ADDR	0x3F
+#define NLP_ERL_LEC_LP_ADDR	0x40
+#define NLP_CT_LEV_RE_ADDR	0x41
+#define NLP_CTRL_ADDR		0x42
+
+#define UTD_CF_H_ADDR		0x4B
+#define UTD_CF_L_ADDR		0x4C
+#define UTD_BW_H_ADDR		0x4D
+#define UTD_BW_L_ADDR		0x4E
+#define UTD_NLEV_ADDR		0x4F
+#define UTD_SLEV_H_ADDR		0x50
+#define UTD_SLEV_L_ADDR		0x51
+#define UTD_DELT_ADDR		0x52
+#define UTD_RBRK_ADDR		0x53
+#define UTD_RTIME_ADDR		0x54
+#define UTD_EBRK_ADDR		0x55
+#define UTD_ETIME_ADDR		0x56
+
+#define DTMF_LEV_ADDR		0x30
+#define DTMF_TWI_ADDR		0x31
+#define DTMF_NCF_H_ADDR		0x32
+#define DTMF_NCF_L_ADDR		0x33
+#define DTMF_NBW_H_ADDR		0x34
+#define DTMF_NBW_L_ADDR		0x35
+#define DTMF_GAIN_ADDR		0x36
+#define DTMF_RES1_ADDR		0x37
+#define DTMF_RES2_ADDR		0x38
+#define DTMF_RES3_ADDR		0x39
+
+#define CIS_LEV_H_ADDR		0x43
+#define CIS_LEV_L_ADDR		0x44
+#define CIS_BRS_ADDR		0x45
+#define CIS_SEIZ_H_ADDR		0x46
+#define CIS_SEIZ_L_ADDR		0x47
+#define CIS_MARK_H_ADDR		0x48
+#define CIS_MARK_L_ADDR		0x49
+#define CIS_LEC_MODE_ADDR	0x4A
+
+/*=====================================*/
+
+#define HOOK_LEV_ACT_START_ADDR 0x89
+#define RO1_START_ADDR		0x70
+#define RO2_START_ADDR		0x95
+#define RO3_START_ADDR		0x96
+
+#define TG1_FREQ_START_ADDR	0x38
+#define TG1_GAIN_START_ADDR	0x39
+#define TG1_BANDPASS_START_ADDR 0x3B
+#define TG1_BANDPASS_END_ADDR	0x3D
+
+#define TG2_FREQ_START_ADDR	0x40
+#define TG2_GAIN_START_ADDR	0x41
+#define TG2_BANDPASS_START_ADDR 0x43
+#define TG2_BANDPASS_END_ADDR	0x45
+
+/*====================================*/
+
+#define PCM_HW_B		0x80
+#define PCM_HW_A		0x00
+#define PCM_TIME_SLOT_0		0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
+#define PCM_TIME_SLOT_1		0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
+#define PCM_TIME_SLOT_4		0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
+
+#define	 RX_LEV_ADDR	0x28
+#define	 TX_LEV_ADDR	0x30
+#define	 Ik1_ADDR	0x83
+
+#define	 AR_ROW		3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 AX_ROW		6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 DCF_ROW	0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
+
+/* Mark the start byte of Duslic parameters that we use with configurator */
+#define	 Ik1_START_BYTE		3
+#define	 RX_LEV_START_BYTE	0
+#define	 TX_LEV_START_BYTE	0
+
+/************************************************/
+
+#define INTREG4_CIS_ACT		(1 << 0)
+
+#define BCR1_SLEEP		0x20
+#define BCR1_REVPOL		0x10
+#define BCR1_ACTR		0x08
+#define BCR1_ACTL		0x04
+#define BCR1_SLIC_MASK		0x03
+
+#define BCR2_HARD_POL_REV	0x40
+#define BCR2_TTX		0x20
+#define BCR2_TTX_12K		0x10
+#define BCR2_HIMAN		0x08
+#define BCR2_PDOT		0x01
+
+#define BCR3_PCMX_EN		(1 << 4)
+
+#define BCR5_DTMF_EN		(1 << 0)
+#define BCR5_DTMF_SRC		(1 << 1)
+#define BCR5_LEC_EN		(1 << 2)
+#define BCR5_LEC_OUT		(1 << 3)
+#define BCR5_CIS_EN		(1 << 4)
+#define BCR5_CIS_AUTO		(1 << 5)
+#define BCR5_UTDX_EN		(1 << 6)
+#define BCR5_UTDR_EN		(1 << 7)
+
+#define DSCR_TG1_EN		(1 << 0)
+#define DSCR_TG2_EN		(1 << 1)
+#define DSCR_PTG		(1 << 2)
+#define DSCR_COR8		(1 << 3)
+#define DSCR_DG_KEY(x)		(((x) & 0x0F) << 4)
+
+#define CIS_LEC_MODE_CIS_V23	(1 << 0)
+#define CIS_LEC_MODE_CIS_FRM	(1 << 1)
+#define CIS_LEC_MODE_NLP_EN	(1 << 2)
+#define CIS_LEC_MODE_UTDR_SUM	(1 << 4)
+#define CIS_LEC_MODE_UTDX_SUM	(1 << 5)
+#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
+#define CIS_LEC_MODE_LEC_ADAPT	(1 << 7)
+
+#define TSTR4_COR_64		(1 << 5)
+
+#define TSTR3_AC_DLB_8K		(1 << 2)
+#define TSTR3_AC_DLB_32K	(1 << 3)
+#define TSTR3_AC_DLB_4M		(1 << 5)
+
+
+#define LMCR1_TEST_EN		(1 << 7)
+#define LMCR1_LM_EN		(1 << 6)
+#define LMCR1_LM_THM		(1 << 5)
+#define LMCR1_LM_ONCE		(1 << 2)
+#define LMCR1_LM_MASK		(1 << 1)
+
+#define LMCR2_LM_RECT			(1 << 5)
+#define LMCR2_LM_SEL_VDD		0x0D
+#define LMCR2_LM_SEL_IO3		0x0A
+#define LMCR2_LM_SEL_IO4		0x0B
+#define LMCR2_LM_SEL_IO4_MINUS_IO3	0x0F
+
+#define LMCR3_RTR_SEL		(1 << 6)
+
+#define LMCR3_RNG_OFFSET_NONE	0x00
+#define LMCR3_RNG_OFFSET_1	0x01
+#define LMCR3_RNG_OFFSET_2	0x02
+#define LMCR3_RNG_OFFSET_3	0x03
+
+#define TSTR5_DC_HOLD		(1 << 3)
+
+/************************************************/
+
+#define TARGET_ONHOOK_BATH_x100		4600	/* 46.0 Volt */
+#define TARGET_ONHOOK_BATL_x100		2500	/* 25.0 Volt */
+#define TARGET_V_DIVIDER_RATIO_x100	21376L	/* (R1+R2)/R2 = 213.76 */
+#define DIVIDER_RATIO_ACCURx100		(22 * 100)
+#define V_AD_x10000			10834L	/* VAD = 1.0834 */
+#define TARGET_VDDx100			330	/* VDD = 3.3 * 10 */
+#define VDD_MAX_DIFFx100		20	/* VDD Accur = 0.2*100 */
+
+#define RMS_MULTIPLIERx100		111	/* pi/(2xsqrt(2)) = 1.11*/
+#define K_INTDC_RECT_ON			4	/* When Rectifier is ON this value is necessary(2^4) */
+#define K_INTDC_RECT_OFF		2	/* 2^2 */
+#define RNG_FREQ			25
+#define SAMPLING_FREQ			(2000L)
+#define N_SAMPLES			(SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
+#define HOOK_THRESH_RING_START_ADDR	0x8B
+#define RING_PARAMS_START_ADDR		0x70
+
+#define V_OUT_BATH_MAX_DIFFx100		300	/* 3.0 x100 */
+#define V_OUT_BATL_MAX_DIFFx100		400	/* 4.0 x100 */
+#define MAX_V_RING_MEANx100		50
+#define TARGET_V_RING_RMSx100		2720
+#define V_RMS_RING_MAX_DIFFx100		250
+
+#define LM_OK_SRC_IRG_2			(1 << 4)
+
+/************************************************/
+
+#define PORTB		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define PORTC		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define PORTD		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
+
+#define _PORTD_SET(mask, state) \
+	do { \
+		if (state) \
+			PORTD |= mask; \
+		else \
+			PORTD &= ~mask; \
+	} while (0)
+
+#define _PORTB_SET(mask, state) \
+	do { \
+		if (state) \
+			PORTB |= mask; \
+		else \
+			PORTB &= ~mask; \
+	} while (0)
+
+#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
+#define _PORTB_GET(mask) (!!(PORTB & mask))
+
+#define _PORTC_GET(mask) (!!(PORTC & mask))
+
+/* port B */
+#define SPI_RXD		(1 << (31 - 28))
+#define SPI_TXD		(1 << (31 - 29))
+#define SPI_CLK		(1 << (31 - 30))
+
+/* port C */
+#define COM_HOOK1	(1 << (15 - 9))
+#define COM_HOOK2	(1 << (15 - 10))
+
+#ifndef CONFIG_NETTA_SWAPHOOK
+
+#define COM_HOOK3	(1 << (15 - 11))
+#define COM_HOOK4	(1 << (15 - 12))
+
+#else
+
+#define COM_HOOK3	(1 << (15 - 12))
+#define COM_HOOK4	(1 << (15 - 11))
+
+#endif
+
+/* port D */
+#define SPIENC1		(1 << (15 - 9))
+#define SPIENC2		(1 << (15 - 10))
+#define SPIENC3		(1 << (15 - 11))
+#define SPIENC4		(1 << (15 - 14))
+
+#define SPI_DELAY() udelay(1)
+
+static inline unsigned int __SPI_Transfer(unsigned int tx)
+{
+	unsigned int rx;
+	int b;
+
+	rx = 0; b = 8;
+	while (--b >= 0) {
+		_PORTB_SET(SPI_TXD, tx & 0x80);
+		tx <<= 1;
+		_PORTB_TGL(SPI_CLK);
+		SPI_DELAY();
+		rx <<= 1;
+		rx |= _PORTB_GET(SPI_RXD);
+		_PORTB_TGL(SPI_CLK);
+		SPI_DELAY();
+	}
+
+	return rx;
+}
+
+static const char *codsp_dtmf_map = "D1234567890*#ABC";
+
+static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
+static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
+
+static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
+{
+	unsigned int rx;
+	int i;
+
+	/* just some sanity checks */
+	if (cmd == 0 || cmdlen < 0)
+		return -1;
+
+	_PORTD_SET(spienc_mask_tab[duslic_id], 0);
+
+	/* first 2 bytes are without response */
+	i = 2;
+	while (i-- > 0 && cmdlen-- > 0)
+		__SPI_Transfer(*cmd++);
+
+	while (cmdlen-- > 0) {
+		rx = __SPI_Transfer(*cmd++);
+		if (res != 0 && reslen-- > 0)
+			*res++ = (unsigned char)rx;
+	}
+	if (res != 0) {
+		while (reslen-- > 0)
+			*res++ = __SPI_Transfer(0xFF);
+	}
+
+	_PORTD_SET(spienc_mask_tab[duslic_id], 1);
+
+	return 0;
+}
+
+/****************************************************************************/
+
+void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
+{
+	unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_reset_chip(int duslic_id)
+{
+	static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_reset_channel(int duslic_id, int channel)
+{
+	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_resync_channel(int duslic_id, int channel)
+{
+	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+/****************************************************************************/
+
+void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = val;
+
+	codsp_send(duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char)(val >> 8);
+	cmd[3] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
+{
+	unsigned char cmd[5];
+
+	cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char)(val >> 24);
+	cmd[3] = (unsigned char)(val >> 16);
+	cmd[4] = (unsigned char)(val >> 8);
+	cmd[5] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 6, 0, 0);
+}
+
+unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[3];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 2);
+
+	return res[1];
+}
+
+unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short)res[1] << 8) | res[2];
+}
+
+unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[5];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 5);
+
+	return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
+}
+
+/****************************************************************************/
+
+void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
+{
+	unsigned char cmd[10];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	memcpy(cmd + 2, block, 8);
+	codsp_send(duslic_id, cmd, 10, 0, 0);
+}
+
+void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	cmd[2] = val;
+	codsp_send(duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	cmd[2] = (unsigned char)(val >> 8);
+	cmd[3] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
+{
+	unsigned char cmd[2];
+	unsigned char res[9];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	codsp_send(duslic_id, cmd, 2, res, 9);
+	memcpy(block, res + 1, 8);
+}
+
+unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
+{
+	unsigned char cmd[2];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	codsp_send(duslic_id, cmd, 2, res, 2);
+	return res[1];
+}
+
+unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+
+	codsp_send(duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short)res[1] << 8) | res[2];
+}
+
+/****************************************************************************/
+
+#define MAX_POP_BLOCK	50
+
+void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
+			    const unsigned char *block, int len)
+{
+	unsigned char cmd[2 + MAX_POP_BLOCK];
+
+	if (len > MAX_POP_BLOCK)	/* truncate */
+		len = MAX_POP_BLOCK;
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = addr;
+	memcpy (cmd + 2, block, len);
+	codsp_send (duslic_id, cmd, 2 + len, 0, 0);
+}
+
+void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
+			   unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = val;
+
+	codsp_send (duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
+			    unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char) (val >> 8);
+	cmd[3] = (unsigned char) val;
+
+	codsp_send (duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
+			  unsigned int val)
+{
+	unsigned char cmd[5];
+
+	cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char) (val >> 24);
+	cmd[3] = (unsigned char) (val >> 16);
+	cmd[4] = (unsigned char) (val >> 8);
+	cmd[5] = (unsigned char) val;
+
+	codsp_send (duslic_id, cmd, 6, 0, 0);
+}
+
+unsigned char codsp_read_pop_char (int duslic_id, int channel,
+				   unsigned char regno)
+{
+	unsigned char cmd[3];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 2);
+
+	return res[1];
+}
+
+unsigned short codsp_read_pop_short (int duslic_id, int channel,
+				     unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short) res[1] << 8) | res[2];
+}
+
+unsigned int codsp_read_pop_int (int duslic_id, int channel,
+				 unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[5];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 5);
+
+	return (((unsigned int) res[1] << 24) |
+		((unsigned int) res[2] << 16) |
+		((unsigned int) res[3] <<  8) |
+		res[4] );
+}
+/****************************************************************************/
+
+struct _coeffs {
+	unsigned char addr;
+	unsigned char values[8];
+};
+
+struct _coeffs ac_coeffs[11] = {
+	{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
+	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
+	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter	      */
+	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter	      */
+	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter	      */
+	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter	      */
+	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter	      */
+	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter	      */
+	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
+	{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
+	{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} }  /* 0x10 TH-Filter part 3 */
+};
+
+struct _coeffs ac_coeffs_0dB[11] = {
+	{ 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
+	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
+	{ 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
+	{ 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
+	{ 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
+	{ 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
+	{ 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
+	{ 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
+	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
+	{ 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
+	{ 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
+};
+
+struct _coeffs dc_coeffs[9] = {
+	{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter     */
+	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing	      */
+	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters	      */
+	{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels      */
+	{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator   */
+	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX	      */
+	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1	      */
+	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2	      */
+	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} }  /* 0x98 Reserved	      */
+};
+
+void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
+{
+	int i;
+
+	for (i = 0; i < tab_size; i++)
+	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
+}
+
+#define SS_OPEN_CIRCUIT			0
+#define SS_RING_PAUSE			1
+#define SS_ACTIVE			2
+#define SS_ACTIVE_HIGH			3
+#define SS_ACTIVE_RING			4
+#define SS_RINGING			5
+#define SS_ACTIVE_WITH_METERING		6
+#define SS_ONHOOKTRNSM			7
+#define SS_STANDBY			8
+#define SS_MAX				8
+
+static void codsp_set_slic(int duslic_id, int channel, int state)
+{
+	unsigned char v;
+
+	v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
+
+	switch (state) {
+
+		case SS_ACTIVE:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_ACTIVE_HIGH:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_ACTIVE_RING:
+		case SS_ONHOOKTRNSM:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_STANDBY:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
+			break;
+
+		case SS_OPEN_CIRCUIT:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
+			break;
+
+		case SS_RINGING:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
+			break;
+
+		case SS_RING_PAUSE:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
+			break;
+	}
+}
+
+const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
+const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
+
+void retrieve_slic_state(int slic_id)
+{
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+
+	/* Retrieve the state of the SLICs */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
+
+	/* Program Default Hook Ring thresholds */
+	codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
+
+	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
+	codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
+
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	udelay(40000);
+}
+
+int wait_level_metering_finish(int duslic_id, int channel)
+{
+	int cnt;
+
+	for (cnt = 0; cnt < 1000 &&
+		(codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
+
+	return cnt != 1000;
+}
+
+int measure_on_hook_voltages(int slic_id, long *vdd,
+		long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
+{
+	short LM_Result, Offset_Compensation;	/* Signed 16 bit */
+	long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
+	unsigned char err_mask = 0;
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+	int i;
+
+	/* measure VDD */
+	/* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
+	codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
+
+	/* Activate Test Mode ==> To Enable DC Hold !!! */
+	/* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
+	/* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+	VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ;	/* VDDx100 */
+
+	*vdd = VDD;
+
+	VDD_diff = VDD - TARGET_VDDx100;
+
+	if (VDD_diff < 0)
+		VDD_diff = -VDD_diff;
+
+	if (VDD_diff > VDD_MAX_DIFFx100)
+		err_mask |= 1;
+
+	Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
+
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
+
+	udelay(40000);
+
+	codsp_write_sop_char(duslic_id, channel,
+		LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
+
+	V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+	*v_oh_H = V_out;
+
+	Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
+
+	if (Vout_diff < 0)
+		Vout_diff = -Vout_diff;
+
+	if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
+		err_mask |= 2;
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
+
+	udelay(40000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+
+	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
+
+	V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+	*v_oh_L = V_out;
+
+	Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
+
+	if (Vout_diff < 0)
+		Vout_diff = -Vout_diff;
+
+	if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
+		err_mask |= 4;
+
+	/* perform ring tests */
+
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
+
+	/* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
+	codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
+
+	/* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
+
+	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
+	for(i = 0; i < sizeof(Max_HookRingTh); i++)
+		codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
+
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
+
+	/* select source for the levelmeter to be IO4-IO3 */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
+
+	udelay(40000);
+
+	/* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
+	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
+
+	udelay(10000);
+
+	/* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
+	codsp_write_sop_char(duslic_id, channel,
+			LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
+
+	if (wait_level_metering_finish(duslic_id, channel)) {
+
+		udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
+
+		/* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
+		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
+
+		/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+
+		/* Now programm Integrator Offset Registers !!! */
+		codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
+
+		codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
+
+		udelay(40000);
+
+		/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+		codsp_write_sop_char(duslic_id, channel,
+				LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+		udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
+
+		/* Poll the LM_OK bit to see when Integration Result is Ready */
+		if (wait_level_metering_finish(duslic_id, channel)) {
+
+			udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
+
+			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
+			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+			V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ;  /* Vin x 10000*/
+
+			V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+			if (V_out < 0)
+				V_out= -V_out;
+
+			if (V_out > MAX_V_RING_MEANx100)
+				err_mask |= 8;
+
+			*ring_mean_v = V_out;
+		} else {
+			err_mask |= 8;
+			*ring_mean_v = 0;
+		}
+	} else {
+		err_mask |= 8;
+		*ring_mean_v = 0;
+	}
+
+	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+		LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
+
+	/* Now Enable Rectifier */
+	/* select source for the levelmeter to be IO4-IO3 */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
+		LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
+
+	/* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
+	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
+
+	udelay(40000);
+
+	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+			LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+	udelay(40000);
+
+	/* Poll the LM_OK bit to see when Integration Result is Ready */
+	if (wait_level_metering_finish(duslic_id, channel)) {
+
+		udelay(10000);
+
+		/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+		/*				    ==>After that Result Regs will be updated every 500us !!!) */
+		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
+
+		/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+
+		/* Now programm Integrator Offset Registers !!! */
+		codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
+
+		/* Be sure that a Ring is generated !!!! */
+		codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
+
+		udelay(40000);
+
+		/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+				LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+		udelay(40000);
+
+		/* Poll the LM_OK bit to see when Integration Result is Ready */
+		if (wait_level_metering_finish(duslic_id, channel)) {
+
+			udelay(10000);
+
+			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
+			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+			V_in = (-1) *  ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ;  /* Vin x 10000*/
+
+			V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ;	/* Vout_RMS x100 */
+			if (V_out < 0)
+				V_out = -V_out;
+
+			Vout_diff = (V_out - TARGET_V_RING_RMSx100);
+
+			if (Vout_diff < 0)
+				Vout_diff = -Vout_diff;
+
+			if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
+				err_mask |= 16;
+
+			*ring_rms_v = V_out;
+		} else {
+			err_mask |= 16;
+			*ring_rms_v = 0;
+		}
+	} else {
+		err_mask |= 16;
+		*ring_rms_v = 0;
+	}
+	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	retrieve_slic_state(slic_id);
+
+	return(err_mask);
+}
+
+int test_dtmf(int slic_id)
+{
+	unsigned char code;
+	unsigned char b;
+	unsigned int intreg;
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+
+	for (code = 0; code < 16; code++) {
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+			(b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
+		udelay(80000);
+
+		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
+		if ((intreg & CODSP_INTREG_INT_CH) == 0)
+			break;
+
+		if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
+				codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
+			break;
+
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+
+		udelay(80000);
+
+		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
+	}
+
+	if (code != 16) {
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+		return(1);
+	}
+
+	return(0);
+}
+
+void data_up_persist_time(int duslic_id, int channel, int time_ms)
+{
+	unsigned char b;
+
+	b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
+	b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
+	codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
+}
+
+static void program_dtmf_params(int duslic_id, int channel)
+{
+	unsigned char b;
+
+	codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
+	codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
+	codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
+
+	b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
+	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
+}
+
+static void codsp_channel_full_reset(int duslic_id, int channel)
+{
+
+	program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
+	program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
+
+	/* program basic configuration registers */
+	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
+	codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
+	codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
+	codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
+
+	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04);		/* PG */
+
+	program_dtmf_params(duslic_id, channel);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);	/* RingTRip_SEL */
+
+	data_up_persist_time(duslic_id, channel, 4);
+
+	codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF);     /* All interrupts masked */
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
+}
+
+static int codsp_chip_full_reset(int duslic_id)
+{
+	int i, cnt;
+	int intreg[NUM_CHANNELS];
+	unsigned char pcm_resync;
+	unsigned char revision;
+
+	codsp_reset_chip(duslic_id);
+
+	udelay(2000);
+
+	for (i = 0; i < NUM_CHANNELS; i++)
+		intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
+
+	udelay(1500);
+
+	if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
+		printf("_HOOK(%d) stayed low\n", duslic_id);
+		return -1;
+	}
+
+	for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
+		if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
+			pcm_resync |= 1 << i;
+	}
+
+	for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
+		for (i = 0; i < NUM_CHANNELS; i++)
+			codsp_resync_channel(duslic_id, i);
+
+		udelay(2000);
+
+		pcm_resync = 0;
+
+		for (i = 0; i < NUM_CHANNELS; i++) {
+			if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
+				pcm_resync |= 1 << i;
+		}
+	}
+
+	if (cnt == 5) {
+		printf("PCM_Resync(%u) not completed\n", duslic_id);
+		return -2;
+	}
+
+	revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
+	printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
+
+	codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80);	/* EDSP_EN */
+
+	for (i = 0; i < NUM_CHANNELS; i++) {
+		codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
+		codsp_channel_full_reset(duslic_id, i);
+	}
+
+	return 0;
+}
+
+int slic_self_test(int duslic_mask)
+{
+	int slic;
+	int i;
+	int r;
+	long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
+	const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
+	int error = 0;
+
+	for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
+		if (duslic_mask & (1 << (slic >> 1))) {
+			r = measure_on_hook_voltages(slic, &vdd,
+				&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
+
+			printf("SLIC %u measured voltages (x100):\n\t"
+				    "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
+				    slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
+
+			if (r != 0)
+				error |= 1 << slic;
+
+			for (i = 0; i < 5; i++)
+				if (r & (1 << i))
+					printf("\t%s out of range\n", err_txt[i]);
+		}
+	}
+
+	for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
+		if (duslic_mask & (1 << (slic >> 1))) {
+			printf("SLIC %u VOICE PATH...CHECKING", slic);
+			printf("\rSLIC %u VOICE PATH...%s\n", slic,
+				(r = test_dtmf(slic)) != 0 ? "FAILED  " : "PASSED  ");
+
+			if (r != 0)
+				error |= 1 << slic;
+		}
+	}
+
+	return(error);
+}
+
+#if defined(CONFIG_NETTA_ISDN)
+
+#define SPIENS1		(1 << (31 - 15))
+#define SPIENS2		(1 << (31 - 19))
+
+static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
+int s_initialized = 0;
+
+static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
+{
+	unsigned int rx, v;
+
+	_PORTB_SET(spiens_mask_tab[s_id], 0);
+
+	rx = __SPI_Transfer(address);
+
+	switch (address & 0xF0) {
+	case 0x60:	/* write byte register */
+	case 0x70:
+		rx = __SPI_Transfer(value);
+		break;
+
+	case 0xE0:	/* read R6 register */
+		v = __SPI_Transfer(0);
+
+		rx = (rx << 8) | v;
+
+		break;
+
+	case 0xF0:	/* read byte register */
+		rx = __SPI_Transfer(0);
+
+		break;
+	}
+
+	_PORTB_SET(spiens_mask_tab[s_id], 1);
+
+	return rx;
+}
+
+static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+	unsigned int v;
+
+	address = 0x70 | (regno & 15);
+	val &= 0xff;
+
+	v = s_transfer_internal(s_id, address, val);
+}
+
+static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+	unsigned int v;
+
+	address = 0x70 | (regno & 15);
+	val &= 0xff;
+
+	v = s_transfer_internal(s_id, address, val);
+}
+
+static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+	unsigned int v;
+
+	address = (regno & 7) << 4;
+	val &= 0xf;
+
+	v = s_transfer_internal(s_id, address | val, 0x00);
+}
+
+#define BR7_IFR			0x08	/* IDL2 free run */
+#define BR7_ICSLSB		0x04	/* IDL2 clock speed LSB */
+
+#define BR15_OVRL_REG_EN	0x80
+#define OR7_D3VR		0x80	/* disable 3V regulator */
+
+#define OR8_TEME		0x10	/* TE mode enable */
+#define OR8_MME			0x08	/* master mode enable */
+
+void s_initialize(void)
+{
+	int s_id;
+
+	for (s_id = 0; s_id < 2; s_id++) {
+		s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
+		s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
+		s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
+		s_write_OR(s_id, 7, OR7_D3VR);
+		s_write_OR(s_id, 6, 0);
+		s_write_BR(s_id, 15, 0);
+		s_write_NR(s_id, 3, 0);
+	}
+}
+
+#endif
+
+int board_post_codec(int flags)
+{
+	int j;
+	int r;
+	int duslic_mask;
+
+	printf("board_post_dsp\n");
+
+#if defined(CONFIG_NETTA_ISDN)
+	if (s_initialized == 0) {
+		s_initialize();
+		s_initialized = 1;
+
+		printf("s_initialized\n");
+
+		udelay(20000);
+	}
+#endif
+	duslic_mask = 0;
+
+	for (j = 0; j < MAX_DUSLIC; j++) {
+		if (codsp_chip_full_reset(j) < 0)
+			printf("Error initializing DuSLIC#%d\n", j);
+		else
+			duslic_mask |= 1 << j;
+	}
+
+	if (duslic_mask != 0) {
+		printf("Testing SLICs...\n");
+
+		r = slic_self_test(duslic_mask);
+		for (j = 0; j < MAX_SLICS; j++) {
+			if (duslic_mask & (1 << (j >> 1)))
+				printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
+		}
+	}
+	printf("DuSLIC self test finished\n");
+
+	return 0;	/* return -1 on error */
+}
diff --git a/u-boot/board/netta/dsp.c b/u-boot/board/netta/dsp.c
new file mode 100644
index 0000000..cd57647
--- /dev/null
+++ b/u-boot/board/netta/dsp.c
@@ -0,0 +1,1208 @@
+/*
+ * Intracom TI6711/TI6412 DSP
+ */
+
+#include <common.h>
+#include <post.h>
+
+#include "mpc8xx.h"
+
+struct ram_range {
+	u32 start;
+	u32 size;
+};
+
+#if defined(CONFIG_NETTA_6412)
+
+static const struct ram_range int_ram[] = {
+	{ 0x00000000U, 0x00040000U },
+};
+
+static const struct ram_range ext_ram[] = {
+	{ 0x80000000U, 0x00100000U },
+};
+
+static const struct ram_range ranges[] = {
+	{ 0x00000000U, 0x00040000U },
+	{ 0x80000000U, 0x00100000U },
+};
+
+static inline u16 bit_invert(u16 d)
+{
+	register u8 i;
+	register u16 r;
+	register u16 bit;
+
+	r = 0;
+	for (i = 0; i < 16; i++) {
+		bit = d & (1 << i);
+		if (bit != 0)
+			r |= 1 << (15 - i);
+	}
+	return r;
+}
+
+#else
+
+static const struct ram_range int_ram[] = {
+	{ 0x00000000U, 0x00010000U },
+};
+
+static const struct ram_range ext_ram[] = {
+	{ 0x80000000U, 0x00100000U },
+};
+
+static const struct ram_range ranges[] = {
+	{ 0x00000000U, 0x00010000U },
+	{ 0x80000000U, 0x00100000U },
+};
+
+#endif
+
+/*******************************************************************************************************/
+
+static inline int addr_in_int_ram(u32 addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
+		if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
+			return 1;
+
+	return 0;
+}
+
+static inline int addr_in_ext_ram(u32 addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
+		if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
+			return 1;
+
+	return 0;
+}
+
+/*******************************************************************************************************/
+
+#define DSP_HPIC	0x0
+#define DSP_HPIA	0x4
+#define DSP_HPID1	0x8
+#define DSP_HPID2	0xC
+
+static u32 dummy_delay;
+static volatile u32 *ti6711_delay = &dummy_delay;
+
+static inline void dsp_go_slow(void)
+{
+	volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
+#if defined(CONFIG_NETTA_6412)
+	memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
+#else
+	memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
+#endif
+	memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
+
+	ti6711_delay = (u32 *)DUMMY_BASE;
+}
+
+static inline void dsp_go_fast(void)
+{
+	volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
+#if defined(CONFIG_NETTA_6412)
+	memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
+#else
+	memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
+#endif
+	memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
+
+	ti6711_delay = &dummy_delay;
+}
+
+/*******************************************************************************************************/
+
+static inline void dsp_delay(void)
+{
+	/* perform ti6711_delay chip select read to have a small delay */
+	(void) *(volatile u32 *)ti6711_delay;
+}
+
+static inline u16 dsp_read_hpic(void)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*((volatile u16 *)DSP_BASE));
+#else
+	return *((volatile u16 *)DSP_BASE);
+#endif
+}
+
+static inline void dsp_write_hpic(u16 val)
+{
+#if defined(CONFIG_NETTA_6412)
+	*((volatile u16 *)DSP_BASE) = bit_invert(val);
+#else
+	*((volatile u16 *)DSP_BASE) = val;
+#endif
+}
+
+static inline void dsp_reset(void)
+{
+#if defined(CONFIG_NETTA_6412)
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
+	udelay(500);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
+	udelay(500);
+#else
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
+	udelay(250);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
+	udelay(250);
+#endif
+}
+
+static inline u32 dsp_read_hpic_word(u32 addr)
+{
+	u32 val;
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+
+	val = ((u32) bit_invert(p[0]) << 16);
+	/* dsp_delay(); */
+
+	val |= bit_invert(p[1]);
+	/* dsp_delay(); */
+#else
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+
+	val = ((u32) p[0] << 16);
+	dsp_delay();
+
+	val |= p[1];
+	dsp_delay();
+#endif
+	return val;
+}
+
+static inline u16 dsp_read_hpic_hi_hword(u32 addr)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
+#else
+	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+#endif
+}
+
+static inline u16 dsp_read_hpic_lo_hword(u32 addr)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
+#else
+	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
+#endif
+}
+
+static inline void dsp_wait_hrdy(void)
+{
+	int i;
+
+	i = 0;
+#if defined(CONFIG_NETTA_6412)
+	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+		dsp_delay();
+		i++;
+	}
+}
+
+static inline void dsp_write_hpic_word(u32 addr, u32 val)
+{
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+	p[0] = bit_invert((u16)(val >> 16));
+	/* dsp_delay(); */
+
+	p[1] = bit_invert((u16)val);
+	/* dsp_delay(); */
+#else
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+	p[0] = (u16)(val >> 16);
+	dsp_delay();
+
+	p[1] = (u16)val;
+	dsp_delay();
+#endif
+}
+
+static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
+{
+#if defined(CONFIG_NETTA_6412)
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
+#else
+
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
+#endif
+}
+
+static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
+{
+#if defined(CONFIG_NETTA_6412)
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
+#else
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
+#endif
+}
+
+/********************************************************************/
+
+static inline void c62_write_word(u32 addr, u32 val)
+{
+	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+
+	dsp_wait_hrdy();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+
+	/* dsp_wait_hrdy();
+	dsp_delay(); */
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+}
+
+static u32 c62_read_word(u32 addr)
+{
+	u32 val;
+
+	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+
+	/* FETCH */
+#if defined(CONFIG_NETTA_6412)
+	dsp_write_hpic_word(DSP_HPIC, 0x00100010);
+#else
+	dsp_write_hpic(0x10);
+	dsp_delay();
+#endif
+	dsp_wait_hrdy();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+
+	/* dsp_wait_hrdy();
+	dsp_delay(); */
+#endif
+	val |= dsp_read_hpic_lo_hword(DSP_HPID2);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	return val;
+}
+
+static inline void c62_read(u32 addr, u32 *buffer, int numdata)
+{
+	int i;
+
+	if (numdata <= 0)
+		return;
+
+	for (i = 0; i < numdata; i++) {
+		*buffer++ = c62_read_word(addr);
+		addr += 4;
+	}
+}
+
+static inline u32 c62_checksum(u32 addr, int numdata)
+{
+	int i;
+	u32 chksum;
+
+	chksum = 0;
+	for (i = 0; i < numdata; i++) {
+		chksum += c62_read_word(addr);
+		addr += 4;
+	}
+
+	return chksum;
+}
+
+static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
+{
+	int i;
+
+	if (numdata <= 0)
+		return;
+
+	for (i = 0; i < numdata; i++) {
+		c62_write_word(addr, *buffer++);
+		addr += 4;
+	}
+}
+
+static inline int c62_write_word_validated(u32 addr, u32 val)
+{
+	c62_write_word(addr, val);
+	return c62_read_word(addr) == val ? 0 : -1;
+}
+
+static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
+{
+	int i, r;
+
+	if (numdata <= 0)
+		return 0;
+
+	for (i = 0; i < numdata; i++) {
+		r = c62_write_word_validated(addr, *buffer++);
+		if (r < 0)
+			return r;
+		addr += 4;
+	}
+	return 0;
+}
+
+#if defined(CONFIG_NETTA_6412)
+
+#define DRAM_REGS_BASE	0x1800000
+
+#define GBLCTL	DRAM_REGS_BASE
+#define CECTL1	(DRAM_REGS_BASE + 0x4)
+#define CECTL0	(DRAM_REGS_BASE + 0x8)
+#define CECTL2	(DRAM_REGS_BASE + 0x10)
+#define CECTL3	(DRAM_REGS_BASE + 0x14)
+#define SDCTL	(DRAM_REGS_BASE + 0x18)
+#define SDTIM	(DRAM_REGS_BASE + 0x1C)
+#define SDEXT	(DRAM_REGS_BASE + 0x20)
+#define SESEC1	(DRAM_REGS_BASE + 0x44)
+#define SESEC0	(DRAM_REGS_BASE + 0x48)
+#define SESEC2	(DRAM_REGS_BASE + 0x50)
+#define SESEC3	(DRAM_REGS_BASE + 0x54)
+
+#define MAR128	0x1848200
+#define MAR129	0x1848204
+
+void dsp_dram_initialize(void)
+{
+	c62_write_word(GBLCTL, 0x120E4);
+	c62_write_word(CECTL1, 0x18);
+	c62_write_word(CECTL0, 0xD0);
+	c62_write_word(CECTL2, 0x18);
+	c62_write_word(CECTL3, 0x18);
+	c62_write_word(SDCTL, 0x47115000);
+	c62_write_word(SDTIM, 1536);
+	c62_write_word(SDEXT, 0x534A9);
+#if 0
+	c62_write_word(SESEC1, 0);
+	c62_write_word(SESEC0, 0);
+	c62_write_word(SESEC2, 0);
+	c62_write_word(SESEC3, 0);
+#endif
+	c62_write_word(MAR128, 1);
+	c62_write_word(MAR129, 0);
+}
+
+#endif
+
+static inline void dsp_init_hpic(void)
+{
+	int i;
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	dsp_go_fast();
+#else
+	dsp_go_slow();
+#endif
+	i = 0;
+#if defined(CONFIG_NETTA_6412)
+	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+		dsp_delay();
+		i++;
+	}
+
+	if (i == 1000)
+		printf("HRDY stuck\n");
+
+	dsp_delay();
+
+	/* write control register */
+	p = (volatile u16 *)DSP_BASE;
+	p[0] = 0x0000;
+	dsp_delay();
+	p[1] = 0x0000;
+	dsp_delay();
+
+#if !defined(CONFIG_NETTA_6412)
+	dsp_go_fast();
+#endif
+}
+
+/***********************************************************************************************************/
+
+#if !defined(CONFIG_NETTA_6412)
+
+static const u8 bootstrap_rbin[5084] = {
+	0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
+	0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x03, 0x62,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x10, 0x5a,
+	0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64,
+	0x02, 0x00, 0x00, 0xaa, 0x02, 0x10, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x9f, 0x7a,
+	0x30, 0x00, 0x08, 0x10, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
+	0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x00, 0x02, 0xd6, 0xc8,
+	0x00, 0x10, 0x02, 0xf4, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x03, 0x1a, 0xf7, 0xca, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
+	0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0xcf, 0x5a,
+	0x02, 0x90, 0x02, 0xf6, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x96, 0x10, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x02, 0x90, 0x10, 0x5a, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
+	0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x03, 0x18, 0x2f, 0xda,
+	0x03, 0x10, 0x02, 0xf6, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x03, 0x1a, 0x10, 0x8a, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x19, 0x2e, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x03, 0x00, 0x00, 0xaa,
+	0x02, 0x98, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0xbf, 0x7a, 0x22, 0x90, 0x02, 0xe6,
+	0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xd6, 0x8a, 0x22, 0x90, 0x02, 0xf6,
+	0x22, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xf7, 0x8a,
+	0x22, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x80, 0x4f, 0x58, 0x02, 0x00, 0x12, 0x2a,
+	0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x95, 0x8c, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x12, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x11, 0xad, 0xca, 0x02, 0x00, 0x02, 0x76, 0x92, 0x00, 0x12, 0x2a,
+	0x92, 0x00, 0xc8, 0x6a, 0x92, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x92, 0x95, 0x6b, 0xca, 0x92, 0x90, 0x02, 0xf6, 0x80, 0x00, 0x12, 0x28,
+	0x80, 0x00, 0xc8, 0x68, 0x82, 0x00, 0x02, 0x66, 0x80, 0x00, 0x12, 0x28,
+	0x80, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x82, 0x11, 0x6b, 0x8a,
+	0x82, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x95, 0x4a, 0xca,
+	0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x12, 0x28, 0x90, 0x00, 0xc8, 0x68,
+	0x92, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x92, 0x11, 0x29, 0xca,
+	0x92, 0x00, 0x02, 0x76, 0x82, 0x00, 0x12, 0x2a, 0x82, 0x00, 0xc8, 0x6a,
+	0x82, 0x10, 0x02, 0xe6, 0x80, 0x00, 0x12, 0x28, 0x80, 0x00, 0xc8, 0x68,
+	0x00, 0x00, 0x20, 0x00, 0x82, 0x11, 0x29, 0x8a, 0x82, 0x00, 0x02, 0x76,
+	0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0x08, 0xca, 0x02, 0x00, 0x02, 0x76,
+	0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0x6f, 0x5a, 0x02, 0x90, 0x02, 0xf6,
+	0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x0e, 0xff, 0x5a, 0x02, 0x00, 0x02, 0x76,
+	0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x10, 0x02, 0xe4,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x83, 0xbf, 0x5a, 0x02, 0x90, 0x02, 0xf6,
+	0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x0f, 0xdf, 0x5a, 0x02, 0x00, 0x02, 0x76,
+	0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x12, 0xf7, 0xca, 0x02, 0x00, 0x02, 0x76,
+	0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x96, 0xd6, 0xca, 0x02, 0x90, 0x02, 0xf6,
+	0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66,
+	0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x10, 0x85, 0xca, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x04, 0x2a,
+	0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x95, 0xca,
+	0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x02, 0x0f, 0xdf, 0x5a,
+	0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x96, 0x10, 0xca,
+	0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0xef, 0xca,
+	0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x95, 0xae, 0xca, 0x02, 0x90, 0x02, 0xf6,
+	0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x10, 0x02, 0xe6,
+	0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x10, 0x21, 0x0a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x06, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x06, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x01, 0x8d, 0xae, 0xc8,
+	0x01, 0x8d, 0x0c, 0x88, 0x01, 0x80, 0x02, 0x74, 0x00, 0x00, 0x06, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x06, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca,
+	0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x00, 0x02, 0x31, 0xc8, 0x00, 0x02, 0x10, 0x88,
+	0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x74, 0xca, 0x02, 0x90, 0x02, 0xf6,
+	0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x80, 0x02, 0x66,
+	0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x08, 0x2a,
+	0x02, 0x00, 0xc8, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x21, 0x0a,
+	0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xae, 0xc8, 0x00, 0x01, 0x0c, 0x88,
+	0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc8, 0x68,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca, 0x02, 0x00, 0x02, 0x76,
+	0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6,
+	0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x96, 0x31, 0xca, 0x02, 0x96, 0x10, 0x8a, 0x02, 0x90, 0x02, 0xf6,
+	0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x10, 0x02, 0xe6,
+	0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x12, 0x74, 0xca, 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x08, 0x2a,
+	0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
+	0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x52, 0x8a,
+	0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x1b, 0x10, 0x90, 0x19, 0x2e, 0x28,
+	0x90, 0x00, 0x00, 0x68, 0x90, 0x00, 0x02, 0x64, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x0a, 0x28, 0x01, 0x8f, 0xbd, 0x88,
+	0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x74, 0x00, 0x00, 0x0a, 0x28,
+	0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a,
+	0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x9c, 0x88,
+	0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x00, 0x10, 0x02, 0xe4, 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x1b, 0xc8, 0x00, 0x02, 0x17, 0x88,
+	0x00, 0x10, 0x02, 0xf4, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc8, 0x6a,
+	0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x00, 0x00, 0x01, 0x82, 0x42, 0x64,
+	0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x00, 0x00,
+	0x02, 0x10, 0x07, 0xca, 0x02, 0x0c, 0x9f, 0xfa, 0x02, 0x00, 0x02, 0x76,
+	0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x80, 0x58, 0x03, 0x00, 0x10, 0x2a,
+	0x02, 0x04, 0x03, 0xe2, 0x02, 0x18, 0x56, 0x15, 0x02, 0x93, 0xcf, 0x5a,
+	0x00, 0x94, 0x03, 0xa2, 0x02, 0x18, 0x56, 0x14, 0x00, 0x00, 0x20, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x02, 0x98, 0x56, 0x15, 0x00, 0x90, 0x4a, 0x58,
+	0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59, 0x00, 0x00, 0x06, 0x12,
+	0x00, 0x90, 0x4a, 0x59, 0x02, 0x98, 0x56, 0x15, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x1b, 0x40, 0x5b, 0x03, 0x80, 0x00, 0xf9, 0x02, 0x00, 0x00, 0xa9,
+	0x81, 0x98, 0xa0, 0x14, 0x01, 0x20, 0x00, 0x59, 0x04, 0x04, 0x01, 0xa1,
+	0x20, 0x00, 0x02, 0x13, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x10, 0x6c, 0xe1,
+	0x00, 0x94, 0x4a, 0x59, 0x02, 0x98, 0x56, 0x14, 0xa3, 0x9c, 0x0f, 0xf9,
+	0x20, 0x03, 0xe0, 0x5b, 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59,
+	0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x4a, 0x59, 0xa0, 0x10, 0x6c, 0xe0,
+	0xa3, 0x9c, 0x0f, 0xf9, 0x81, 0x98, 0x60, 0x14, 0x04, 0x04, 0x00, 0x59,
+	0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x4a, 0x59, 0xa0, 0x10, 0x6c, 0xe0,
+	0xa3, 0x9c, 0x0f, 0xf9, 0x81, 0x98, 0x20, 0x14, 0x02, 0x84, 0x00, 0x59,
+	0x01, 0x20, 0x01, 0xa0, 0xa0, 0x10, 0x6c, 0xe0, 0x01, 0x14, 0x01, 0xa1,
+	0xa3, 0x9c, 0x0f, 0xf8, 0x00, 0x90, 0x03, 0xa2, 0xa0, 0x10, 0x6c, 0xe0,
+	0xa3, 0x9c, 0x0f, 0xf8, 0x02, 0x00, 0x0c, 0x2b, 0x00, 0x00, 0x00, 0xa8,
+	0x02, 0x00, 0xc8, 0x6b, 0x00, 0x00, 0x01, 0xe8, 0x00, 0x10, 0x02, 0xf4,
+	0x02, 0x00, 0x0e, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x03, 0x90, 0x02, 0xf4,
+	0x00, 0x00, 0x10, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x03, 0x80, 0x02, 0x74,
+	0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x2e, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x80, 0x2f, 0x58,
+	0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x95, 0x8c, 0xca, 0x02, 0x90, 0x02, 0xf6,
+	0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x02, 0x00, 0x02, 0x66,
+	0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0xad, 0xca, 0x02, 0x00, 0x02, 0x76,
+	0x92, 0x00, 0x12, 0x2a, 0x92, 0x00, 0xc6, 0x6a, 0x92, 0x90, 0x02, 0xe6,
+	0x00, 0x00, 0x60, 0x00, 0x92, 0x95, 0x6b, 0xca, 0x92, 0x90, 0x02, 0xf6,
+	0x80, 0x00, 0x12, 0x28, 0x80, 0x00, 0xc6, 0x68, 0x82, 0x00, 0x02, 0x66,
+	0x80, 0x00, 0x12, 0x28, 0x80, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x82, 0x11, 0x6b, 0x8a, 0x82, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x95, 0x4a, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x12, 0x28,
+	0x90, 0x00, 0xc6, 0x68, 0x92, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00,
+	0x92, 0x11, 0x29, 0xca, 0x92, 0x00, 0x02, 0x76, 0x82, 0x00, 0x12, 0x2a,
+	0x82, 0x00, 0xc6, 0x6a, 0x82, 0x10, 0x02, 0xe6, 0x80, 0x00, 0x12, 0x28,
+	0x80, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, 0x82, 0x11, 0x29, 0x8a,
+	0x82, 0x00, 0x02, 0x76, 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0x08, 0xca,
+	0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0x6f, 0x5a,
+	0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x02, 0x0e, 0xff, 0x5a,
+	0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x02, 0x83, 0xbf, 0x5a,
+	0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x02, 0x0f, 0xdf, 0x5a,
+	0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x02, 0x12, 0xf7, 0xca,
+	0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x96, 0xd6, 0xca,
+	0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x85, 0xca, 0x02, 0x00, 0x02, 0x76,
+	0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x02, 0x80, 0x02, 0x66,
+	0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x96, 0x95, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x0f, 0xdf, 0x5a, 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x04, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x96, 0x10, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x11, 0xef, 0xca, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x04, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x95, 0xae, 0xca,
+	0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x21, 0x0a, 0x02, 0x00, 0x02, 0x76,
+	0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x01, 0x8d, 0xae, 0xc8, 0x01, 0x8d, 0x0c, 0x88, 0x01, 0x80, 0x02, 0x74,
+	0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x02, 0x00, 0x02, 0x66,
+	0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x10, 0xa7, 0xca, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x06, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x06, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x02, 0x31, 0xc8,
+	0x00, 0x02, 0x10, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x06, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x06, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x74, 0xca,
+	0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6,
+	0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6,
+	0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x10, 0x21, 0x0a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x08, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x08, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xae, 0xc8,
+	0x00, 0x01, 0x0c, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x08, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca,
+	0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x31, 0xca, 0x02, 0x96, 0x10, 0x8a,
+	0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
+	0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x12, 0x74, 0xca, 0x02, 0x00, 0x02, 0x76,
+	0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6,
+	0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x19, 0x90,
+	0x90, 0x19, 0x2e, 0x28, 0x90, 0x00, 0x00, 0x68, 0x90, 0x00, 0x02, 0x64,
+	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x0a, 0x28,
+	0x01, 0x8f, 0xbd, 0x88, 0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x74,
+	0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64,
+	0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x03, 0x9c, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0a, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x00, 0x10, 0x02, 0xe4, 0x02, 0x00, 0x0a, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x1b, 0xc8,
+	0x00, 0x02, 0x17, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x19, 0x2e, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x00, 0x00,
+	0x01, 0x82, 0x22, 0x64, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68,
+	0x00, 0x00, 0x00, 0x00, 0x02, 0x10, 0x07, 0xca, 0x02, 0x0c, 0x9f, 0xfa,
+	0x02, 0x00, 0x02, 0x76, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x80, 0x58,
+	0x03, 0x00, 0x10, 0x2a, 0x02, 0x04, 0x03, 0xe3, 0x00, 0x00, 0x00, 0x00,
+	0x02, 0x18, 0x56, 0x15, 0x02, 0x93, 0xcf, 0x5a, 0x00, 0x94, 0x03, 0xa2,
+	0x02, 0x18, 0x56, 0x14, 0x00, 0x00, 0x20, 0x00, 0x02, 0x98, 0x56, 0x15,
+	0x00, 0x90, 0x2a, 0x58, 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59,
+	0x00, 0x00, 0x04, 0x12, 0x00, 0x90, 0x2a, 0x59, 0x02, 0x98, 0x56, 0x14,
+	0x00, 0x1b, 0x40, 0x5b, 0x03, 0x80, 0x00, 0xf9, 0x02, 0x00, 0x00, 0xa9,
+	0x81, 0x98, 0xa0, 0x14, 0x01, 0x20, 0x00, 0x59, 0x04, 0x04, 0x01, 0xa1,
+	0x20, 0x00, 0x00, 0x12, 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x94, 0x2a, 0x59,
+	0x02, 0x98, 0x56, 0x15, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0xa3, 0x9c, 0x0f, 0xf9, 0x20, 0x03, 0xe0, 0x5b, 0x81, 0x98, 0xa0, 0x14,
+	0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x2a, 0x59,
+	0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x9c, 0x0f, 0xf9,
+	0x81, 0x98, 0x60, 0x14, 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0,
+	0x00, 0x94, 0x2a, 0x59, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf9,
+	0x81, 0x98, 0x20, 0x14, 0x02, 0x84, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0,
+	0xa0, 0x10, 0x6c, 0xe0, 0x01, 0x14, 0x01, 0xa1, 0xa3, 0x9c, 0x0f, 0xf8,
+	0x00, 0x90, 0x03, 0xa2, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf8,
+	0x02, 0x00, 0x0c, 0x2b, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0xc6, 0x6b,
+	0x00, 0x00, 0x01, 0xe8, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0e, 0x2a,
+	0x02, 0x00, 0xc6, 0x6a, 0x03, 0x90, 0x02, 0xf4, 0x00, 0x00, 0x10, 0x28,
+	0x00, 0x00, 0xc6, 0x68, 0x03, 0x80, 0x02, 0x74, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc0, 0x69,
+	0x02, 0x00, 0x10, 0x2a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x01, 0xbc, 0x54, 0xf6, 0x02, 0x04, 0x03, 0xe2,
+	0x02, 0x13, 0xcf, 0x5a, 0x00, 0x90, 0x03, 0xa2, 0x02, 0x18, 0x50, 0x2a,
+	0x02, 0x00, 0x00, 0x6a, 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x30, 0x2a,
+	0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x17, 0xb4, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x3c, 0x2a,
+	0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x04, 0x29,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x69, 0x02, 0x00, 0x10, 0x2a,
+	0x02, 0x00, 0x02, 0x76, 0x00, 0x14, 0x4e, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x52, 0x2a, 0x01, 0x80, 0x00, 0x6a,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x11, 0x94, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x5e, 0x2a, 0x01, 0x80, 0x00, 0x6a,
+	0x00, 0x00, 0x40, 0x00, 0x02, 0x11, 0x4c, 0x2a, 0x02, 0x00, 0x00, 0x6a,
+	0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x6c, 0x2a, 0x01, 0x80, 0x00, 0x6a,
+	0x02, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x20, 0x00, 0x00, 0x11, 0x4c, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x7a, 0x2a,
+	0x01, 0x80, 0x00, 0x6a, 0x02, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x04, 0x03, 0xe2, 0x00, 0x12, 0x00, 0x28, 0x02, 0x00, 0x9f, 0xfa,
+	0x00, 0x90, 0x03, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x01, 0xbc, 0x52, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x07, 0xae, 0xfe, 0x2a, 0x07, 0x80, 0x00, 0x6a,
+	0x00, 0x10, 0x00, 0x28, 0x02, 0x80, 0x13, 0xa2, 0x0f, 0xff, 0xe3, 0x12,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x30, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x20, 0x90,
+	0x01, 0x04, 0x2a, 0x58, 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x0a, 0x10,
+	0x00, 0x00, 0x80, 0x00, 0x02, 0x00, 0x00, 0xfa, 0x02, 0x00, 0xc0, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x03, 0x00, 0x08, 0x2a, 0x00, 0x00, 0x40, 0x00,
+	0x02, 0x94, 0xcd, 0xfa, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x00, 0xf8,
+	0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
+	0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, 0x0f, 0xff, 0xfa, 0x90,
+	0x00, 0x00, 0x80, 0x00, 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb,
+	0x01, 0x80, 0x00, 0xf8, 0x01, 0x90, 0x02, 0xf4, 0x02, 0x60, 0x80, 0x2a,
+	0x02, 0x00, 0xdb, 0xeb, 0x02, 0x00, 0x04, 0x28, 0x02, 0x10, 0x02, 0xf4,
+	0x02, 0x00, 0x22, 0x66, 0x02, 0x60, 0x88, 0x28, 0x02, 0x00, 0xdb, 0xe8,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, 0x02, 0x80, 0x42, 0x66,
+	0x02, 0x60, 0x8a, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0xc2, 0x66, 0x02, 0x60, 0x92, 0x28,
+	0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76,
+	0x02, 0x80, 0x62, 0x66, 0x02, 0x60, 0x8c, 0x2a, 0x02, 0x00, 0xdb, 0xea,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x82, 0x66,
+	0x02, 0x60, 0x8e, 0x28, 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x10, 0x02, 0x76, 0x00, 0x00, 0xa2, 0x64, 0x02, 0x60, 0x90, 0x2a,
+	0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x02, 0xf4,
+	0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x01, 0x90, 0x02, 0xf4,
+	0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, 0x00, 0x00, 0x00, 0xa8,
+	0x00, 0x10, 0x02, 0xf4, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19, 0x2a, 0x2a,
+	0x02, 0x84, 0x20, 0xfb, 0x02, 0x00, 0x00, 0x6a, 0x02, 0x90, 0x02, 0xf6,
+	0x02, 0x98, 0xe0, 0x2a, 0x02, 0x19, 0x2c, 0x2a, 0x02, 0x00, 0x00, 0x6b,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a,
+	0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa,
+	0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68,
+	0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12,
+	0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65,
+	0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79,
+	0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59,
+	0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64,
+	0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78,
+	0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
+	0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
+	0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
+	0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
+	0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
+	0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
+	0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
+	0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static int load_bootstrap(void)
+{
+	const u8 *s = bootstrap_rbin;
+	u32 l = sizeof(bootstrap_rbin);
+	const u8 *data, *hdr, *h;
+	u32 chksum, chksum2;
+	int i, j, rangenr;
+	u32 start, length;
+
+	if (l < 12) {
+		printf("bootstrap image corrupted. (too short header)\n");
+		return -1;
+	}
+
+	chksum  = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] <<  8) |  (u32)s[ 7];
+	rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] <<  8) |  (u32)s[11];
+	s += 12; l -= 12;
+
+	hdr = s;
+	s += 8 * rangenr; l -= 8 * rangenr;
+	data = s;
+
+	/* validate bootstrap image */
+	h = hdr; s = data; chksum2 = 0;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+
+		/* too short */
+		if (l < length) {
+			printf("bootstrap image corrupted. (too short data)\n");
+			return -1;
+		}
+		l -= length;
+
+		j = (int)length / 4;
+		while (j-- > 0) {
+			chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] <<  8) |  (u32)s[3];
+			s += 4;
+		}
+	}
+
+	/* checksum must match */
+	if (chksum != chksum2) {
+		printf("bootstrap image corrupted. (checksum error)\n");
+		return -1;
+	}
+
+	/* nothing must be left */
+	if (l != 0) {
+		printf("bootstrap image corrupted. (garbage at the end)\n");
+		return -1;
+	}
+
+	/* write the image */
+	h = hdr;
+	s = data;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+		c62_write(start, (u32 *)s, length / 4);
+		s += length;
+	}
+
+	/* and now validate checksum */
+	h = hdr;
+	s = data;
+	chksum2 = 0;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+		chksum2 += c62_checksum(start, length / 4);
+		s += length;
+	}
+
+	/* checksum must match */
+	if (chksum != chksum2) {
+		printf("bootstrap in DSP memory is corrupted\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+struct host_init {
+	u32 master_mode;
+	struct {
+		u8 port_id;
+		u8 slot_id;
+	} ch_serial_map[32];
+	u32 clk_divider[2];
+	/* pll */
+	u32 initmode;
+	u32 pllm;
+	u32 div[4];
+	u32 oscdiv1;
+	u32 unused[10];
+};
+
+const struct host_init hi_default = {
+	.master_mode	=
+#if !defined(CONFIG_NETTA_ISDN)
+		-1,
+#else
+		0,
+#endif
+
+	.ch_serial_map	= {
+		[ 0]	= { .port_id = 2, .slot_id = 16 },
+		[ 1]	= { .port_id = 2, .slot_id = 17 },
+		[ 2]	= { .port_id = 2, .slot_id = 18 },
+		[ 3]	= { .port_id = 2, .slot_id = 19 },
+		[ 4]	= { .port_id = 2, .slot_id = 20 },
+		[ 5]	= { .port_id = 2, .slot_id = 21 },
+		[ 6]	= { .port_id = 2, .slot_id = 22 },
+		[ 7]	= { .port_id = 2, .slot_id = 23 },
+		[ 8]	= { .port_id = 2, .slot_id = 24 },
+		[ 9]	= { .port_id = 2, .slot_id = 25 },
+		[10]	= { .port_id = 2, .slot_id = 26 },
+		[11]	= { .port_id = 2, .slot_id = 27 },
+		[12]	= { .port_id = 2, .slot_id = 28 },
+		[13]	= { .port_id = 2, .slot_id = 29 },
+		[14]	= { .port_id = 2, .slot_id = 30 },
+		[15]	= { .port_id = 2, .slot_id = 31 },
+	},
+
+	/*
+	   dsp_clk(xin, pllm)         = xin * pllm
+	   serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
+	 */
+
+	.clk_divider	= {
+		[0]	= 47,		/* must be 2048Hz */
+		[1]	= 47,
+	},
+
+	.initmode	= 1,
+	.pllm		=
+#if !defined(CONFIG_NETTA_ISDN)
+	8,		/* for =~ 25MHz 8 */
+#else
+	4,
+#endif
+	.div		= {
+		[0]	= 0x8000,
+		[1]	= 0x8000,	/* for =~ 25MHz 0x8000 */
+		[2]	= 0x8001,	/* for =~ 25MHz 0x8001 */
+		[3]	= 0x8001,	/* for =~ 25MHz 0x8001 */
+	},
+
+	.oscdiv1	= 0,
+};
+
+static void hi_write(const struct host_init *hi)
+{
+	u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
+	u32 *s;
+	u32 chksum;
+	int i;
+
+	memset(hi_buf, 0, sizeof(hi_buf));
+
+	s = hi_buf;
+	s++;
+	*s++ = hi->master_mode;
+	for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
+		*s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
+				((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
+
+	for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
+		*s++ = hi->clk_divider[i];
+
+	*s++ = hi->initmode;
+	*s++ = hi->pllm;
+	for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
+		*s++ = hi->div[i];
+	*s++ = hi->oscdiv1;
+
+	chksum = 0;
+	for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
+		chksum += hi_buf[i];
+	hi_buf[0] = -chksum;
+
+	c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
+}
+
+static void run_bootstrap(void)
+{
+	dsp_go_slow();
+
+	hi_write(&hi_default);
+
+	/* signal interrupt */
+	dsp_write_hpic(0x0002);
+	dsp_delay();
+
+	dsp_go_fast();
+}
+
+#endif
+
+/***********************************************************************************************************/
+
+int board_post_dsp(int flags)
+{
+	u32 ramS, ramE;
+	u32 data, data2;
+	int i, j, k;
+#if !defined(CONFIG_NETTA_6412)
+	int r;
+#endif
+	dsp_reset();
+	dsp_init_hpic();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_go_slow();
+#endif
+	data = 0x11223344;
+	dsp_write_hpic_word(DSP_HPIA, data);
+	data2 = dsp_read_hpic_word(DSP_HPIA);
+	if (data2 !=   0x11223344) {
+		printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
+		goto err;
+	}
+
+	data = 0xFFEEDDCC;
+	dsp_write_hpic_word(DSP_HPIA, data);
+	data2 = dsp_read_hpic_word(DSP_HPIA);
+	if (data2 != 0xFFEEDDCC) {
+		printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
+		goto err;
+	}
+#if defined(CONFIG_NETTA_6412)
+	dsp_dram_initialize();
+#else
+	r = load_bootstrap();
+	if (r < 0) {
+		printf("BOOTSTRAP: ** ERROR ** failed to load\n");
+		goto err;
+	}
+
+	run_bootstrap();
+
+	dsp_go_fast();
+#endif
+	printf("    ");
+
+	/* test RAMs */
+	for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
+
+		ramS = ranges[k].start;
+		ramE = ranges[k].start + ranges[k].size;
+
+		for (j = 0; j < 3; j++) {
+
+			printf("\b\b\b\bR%d.%d", k, j);
+
+			for (i = ramS; i < ramE; i += 4) {
+
+				data = 0;
+				switch (j) {
+					case 0: data = 0xAA55AA55; break;
+					case 1: data = 0x55AA55AA; break;
+					case 2: data = (u32)i;     break;
+				}
+
+				c62_write_word(i, data);
+				data2 = c62_read_word(i);
+				if (data != data2) {
+					printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
+					goto err;
+				}
+			}
+		}
+	}
+
+	printf("\b\b\b\b    \b\b\b\bOK\n");
+#if !defined(CONFIG_NETTA_6412)
+	/* XXX assume that this works */
+	load_bootstrap();
+	run_bootstrap();
+	dsp_go_fast();
+#endif
+	return 0;
+
+err:
+	return -1;
+}
+
+int board_dsp_reset(void)
+{
+#if !defined(CONFIG_NETTA_6412)
+	int r;
+#endif
+	dsp_reset();
+	dsp_init_hpic();
+#if defined(CONFIG_NETTA_6412)
+	dsp_dram_initialize();
+#else
+	dsp_go_slow();
+	r = load_bootstrap();
+	if (r < 0)
+		return r;
+
+	run_bootstrap();
+	dsp_go_fast();
+#endif
+	return 0;
+}
diff --git a/u-boot/board/netta/flash.c b/u-boot/board/netta/flash.c
new file mode 100644
index 0000000..565fd67
--- /dev/null
+++ b/u-boot/board/netta/flash.c
@@ -0,0 +1,508 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/netta/netta.c b/u-boot/board/netta/netta.c
new file mode 100644
index 0000000..d15dc9b
--- /dev/null
+++ b/u-boot/board/netta/netta.c
@@ -0,0 +1,574 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NETTA"
+#if defined(CONFIG_NETTA_ISDN)
+			" with ISDN support"
+#endif
+#if defined(CONFIG_NETTA_6412)
+			" (DSP:TI6412)"
+#else
+			" (DSP:TI6711)"
+#endif
+			"\n"
+			);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define A10_AAAA	0x00000000
+#define A10_AAA0	0x00200000
+#define A10_AAA1	0x00300000
+#define A10_000A	0x00800000
+#define A10_0000	0x00A00000
+#define A10_0001	0x00B00000
+#define A10_111A	0x00C00000
+#define A10_1110	0x00E00000
+#define A10_1111	0x00F00000
+
+#define RAS_0000	0x00000000
+#define RAS_0001	0x00040000
+#define RAS_1110	0x00080000
+#define RAS_1111	0x000C0000
+
+#define CAS_0000	0x00000000
+#define CAS_0001	0x00010000
+#define CAS_1110	0x00020000
+#define CAS_1111	0x00030000
+
+#define WE_0000		0x00000000
+#define WE_0001		0x00004000
+#define WE_1110		0x00008000
+#define WE_1111		0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+/* #define CAS_LATENCY	3 */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+#if 0
+	printf("check 0\n");
+	check_ram(( 0 << 20), (2 << 20));
+	printf("check 16\n");
+	check_ram((16 << 20), (2 << 20));
+	printf("check 32\n");
+	check_ram((32 << 20), (2 << 20));
+	printf("check 48\n");
+	check_ram((48 << 20), (2 << 20));
+#endif
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+	return(0);
+}
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
+				BMCR_RESET | BMCR_ANENABLE);
+		udelay(10000);
+	}
+}
+
+extern int board_dsp_reset(void);
+
+int last_stage_init(void)
+{
+	int r;
+
+	reset_phys();
+	r = board_dsp_reset();
+	if (r < 0)
+		printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	(_BWR(3) | _BWR(7, 9) | _BW(11))
+#define PA_GP_OUTMASK	(_BW(6) | _BW(10) | _BWR(12, 15))
+#define PA_SP_MASK	(_BWR(0, 2) | _BWR(4, 5))
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(13) | _BWR(14, 15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	(_B(28) | _B(31))
+#define PB_GP_OUTMASK	(_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_DIRVAL	0
+
+#define PC_GP_INMASK	(_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
+#define PC_GP_OUTMASK	(_BW(6) | _BW(12))
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	_BW(7)
+#define PC_GP_OUTVAL	(_BW(6) | _BW(12))
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+
+#if defined(CONFIG_NETTA_6412)
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
+
+#else
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11))
+
+#endif
+
+#define PD_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* CS1: NAND chip select */
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#if !defined(CONFIG_NETTA_6412)
+	/* CS2: DSP */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#else
+	/* CS6: DSP */
+	memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#endif
+	/* CS4: External register chip select */
+	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
+	memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	/* CS5: dummy for accurate delay */
+	memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
+	memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	ioport->iop_pddat	= PD_GP_OUTVAL;
+	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
+	ioport->iop_pdpar	= PD_SP_MASK;
+
+	/* ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7)); */
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+
+int pcmcia_init(void)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
diff --git a/u-boot/board/netta/pcmcia.c b/u-boot/board/netta/pcmcia.c
new file mode 100644
index 0000000..ed58f2c
--- /dev/null
+++ b/u-boot/board/netta/pcmcia.c
@@ -0,0 +1,370 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+#define PCMCIA_BOARD_MSG "NETTA"
+
+static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
+
+static void cfg_vppd(int no)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+		return;
+
+	mask = vppd_masks[no];
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_vppd(int no, int what)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+		return;
+
+	mask = vppd_masks[no];
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
+
+static void cfg_vccd(int no)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+		return;
+
+	mask = vccd_masks[no];
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_vccd(int no, int what)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+		return;
+
+	mask = vccd_masks[no];
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short oc_mask = _BW(8);
+
+static void cfg_oc(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask = oc_mask;
+
+	immap->im_ioport.iop_pcdir &= ~mask;
+	immap->im_ioport.iop_pcso  &= ~mask;
+	immap->im_ioport.iop_pcint &= ~mask;
+	immap->im_ioport.iop_pcpar &= ~mask;
+}
+
+static int get_oc(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask = oc_mask;
+	int what;
+
+	what = !!(immap->im_ioport.iop_pcdat & mask);;
+	return what;
+}
+
+static const unsigned short shdn_mask = _BW(12);
+
+static void cfg_shdn(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	mask = shdn_mask;
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_shdn(int what)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	mask = shdn_mask;
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static void cfg_ports (void)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+
+	cfg_vppd(0); cfg_vppd(1);	/* VPPD0,VPPD1 VAVPP => Hi-Z */
+	cfg_vccd(0); cfg_vccd(1);	/* 3V and 5V off */
+	cfg_shdn();
+	cfg_oc();
+
+	/*
+	* Configure Port A for TPS2211 PC-Card Power-Interface Switch
+	*
+	* Switch off all voltages, assert shutdown
+	*/
+	set_vppd(0, 1); set_vppd(1, 1);
+	set_vccd(0, 0); set_vccd(1, 0);
+	set_shdn(1);
+
+	udelay(100000);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, pipr, mask;
+	int i;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+	cfg_ports ();
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(500);
+
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+	*/
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	pipr = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       pipr,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+	if ((pipr & mask) == mask) {
+		set_vppd(0, 1); set_vppd(1, 1);		/* VAVPP => Hi-Z */
+		set_vccd(0, 0); set_vccd(1, 1);		/* 5V on, 3V off */
+		puts (" 5.0V card found: ");
+	} else {
+		set_vppd(0, 1); set_vppd(1, 1);		/* VAVPP => Hi-Z */
+		set_vccd(0, 1); set_vccd(1, 0);		/* 5V off, 3V on */
+		puts (" 3.3V card found: ");
+	}
+
+	/*  Wait 500 ms; use this to check for over-current */
+	for (i=0; i<5000; ++i) {
+		if (!get_oc()) {
+			printf ("   *** Overcurrent - Safety shutdown ***\n");
+			set_vccd(0, 0); set_vccd(1, 0);		/* VAVPP => Hi-Z */
+			return (1);
+		}
+		udelay (100);
+	}
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	/* All voltages off / Hi-Z */
+	set_vppd(0, 1); set_vppd(1, 1);
+	set_vccd(0, 1); set_vccd(1, 1);
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+	ushort sreg;
+
+	debug ("voltage_set: "
+			PCMCIA_BOARD_MSG
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	* Disable PCMCIA buffers (isolate the interface)
+	* and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Configure Port C pins for
+	* 5 Volts Enable and 3 Volts enable,
+	* Turn all power pins to Hi-Z
+	*/
+	debug ("PCMCIA power OFF\n");
+	cfg_ports ();	/* Enables switch, but all in Hi-Z */
+
+	sreg  = immap->im_ioport.iop_pcdat;
+	set_vppd(0, 1); set_vppd(1, 1);
+
+	switch(vcc) {
+		case  0:
+			break;	/* Switch off		*/
+
+		case 33:
+			set_vccd(0, 1); set_vccd(1, 0);
+			break;
+
+		case 50:
+			set_vccd(0, 0); set_vccd(1, 1);
+			break;
+
+		default:
+			goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+	       pcmp->pcmc_pipr,
+	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+done:
+			debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/u-boot/board/netta/u-boot.lds b/u-boot/board/netta/u-boot.lds
new file mode 100644
index 0000000..684ab81
--- /dev/null
+++ b/u-boot/board/netta/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text	:
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netta/u-boot.lds.debug b/u-boot/board/netta/u-boot.lds.debug
new file mode 100644
index 0000000..df7b6ad
--- /dev/null
+++ b/u-boot/board/netta/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netta2/Makefile b/u-boot/board/netta2/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/netta2/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netta2/flash.c b/u-boot/board/netta2/flash.c
new file mode 100644
index 0000000..53a4e1e
--- /dev/null
+++ b/u-boot/board/netta2/flash.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/netta2/netta2.c b/u-boot/board/netta2/netta2.c
new file mode 100644
index 0000000..ff713d9
--- /dev/null
+++ b/u-boot/board/netta2/netta2.c
@@ -0,0 +1,640 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+#if CONFIG_NETTA2_VERSION == 2
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+#endif
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
+				BMCR_RESET | BMCR_ANENABLE);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(3) | _BW(14) | _BW(15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_DIRVAL	0
+
+#if CONFIG_NETTA2_VERSION == 1
+#define PC_GP_INMASK	_BW(12)
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(13) | _BW(15))
+#elif CONFIG_NETTA2_VERSION == 2
+#define PC_GP_INMASK	(_BW(13) | _BW(15))
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(12))
+#endif
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	(_BW(10) | _BW(11))
+#define PC_SP_DIRVAL	0
+
+#if CONFIG_NETTA2_VERSION == 1
+#define PE_GP_INMASK	_B(31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
+#elif CONFIG_NETTA2_VERSION == 2
+#define PE_GP_INMASK	_BR(28, 31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27))
+#endif
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* NAND chip select */
+#if CONFIG_NETTA2_VERSION == 1
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#elif CONFIG_NETTA2_VERSION == 2
+	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
+	memctl->memc_mamr = 0;	/* all clear */
+#endif
+
+	/* DSP chip select */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+#if CONFIG_NETTA2_VERSION == 1
+	memctl->memc_br4 &= ~BR_V;
+#endif
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+
+	return 0;
+}
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int last_stage_init(void)
+{
+#if CONFIG_NETTA2_VERSION == 2
+	int i;
+#endif
+
+#if CONFIG_NETTA2_VERSION == 2
+	/* assert peripheral reset */
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	for (i = 0; i < 10; i++)
+		udelay(1000);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+#endif
+	reset_phys();
+
+	return 0;
+}
diff --git a/u-boot/board/netta2/u-boot.lds b/u-boot/board/netta2/u-boot.lds
new file mode 100644
index 0000000..684ab81
--- /dev/null
+++ b/u-boot/board/netta2/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text	:
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netta2/u-boot.lds.debug b/u-boot/board/netta2/u-boot.lds.debug
new file mode 100644
index 0000000..df7b6ad
--- /dev/null
+++ b/u-boot/board/netta2/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netvia/Makefile b/u-boot/board/netvia/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/netvia/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/netvia/flash.c b/u-boot/board/netvia/flash.c
new file mode 100644
index 0000000..b987434
--- /dev/null
+++ b/u-boot/board/netvia/flash.c
@@ -0,0 +1,511 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/netvia/netvia.c b/u-boot/board/netvia/netvia.c
new file mode 100644
index 0000000..5606996
--- /dev/null
+++ b/u-boot/board/netvia/netvia.c
@@ -0,0 +1,417 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetVia board
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+
+/****************************************************************/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+/* last value written to the external register; we cannot read back */
+unsigned int last_er_val;
+#endif
+
+/****************************************************************/
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define A10_AAAA	0x00000000
+#define A10_AAA0	0x00200000
+#define A10_AAA1	0x00300000
+#define A10_000A	0x00800000
+#define A10_0000	0x00A00000
+#define A10_0001	0x00B00000
+#define A10_111A	0x00C00000
+#define A10_1110	0x00E00000
+#define A10_1111	0x00F00000
+
+#define RAS_0000	0x00000000
+#define RAS_0001	0x00040000
+#define RAS_1110	0x00080000
+#define RAS_1111	0x000C0000
+
+#define CAS_0000	0x00000000
+#define CAS_0001	0x00010000
+#define CAS_1110	0x00020000
+#define CAS_1111	0x00030000
+
+#define WE_0000		0x00000000
+#define WE_0001		0x00004000
+#define WE_1110		0x00008000
+#define WE_1111		0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+const uint sdram_table[0x40] = {
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
+
+	/* REG */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ETX ID string (ETX_xxx...)
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+	printf ("NETVIA v1\n");
+#else
+	printf ("NETVIA v2+\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+#define MAR_SDRAM_INIT		0x000000C8LU
+
+#define MCR_OP(x)		((unsigned long)((x) & 3) << (31-1))
+#define MCR_OP_MASK		MCR_OP(3)
+
+#define MCR_UM(x)		((unsigned long)((x) & 1) << (31 - 8))
+#define MCR_UM_MASK		MCR_UM(1)
+#define MCR_UM_UPMA		MCR_UM(0)
+#define MCR_UM_UPMB		MCR_UM(1)
+
+#define MCR_MB(x)		((unsigned long)((x) & 7) << (31 - 18))
+#define MCR_MB_MASK		MCR_MB(7)
+#define MCR_MB_CS(x)		MCR_MB(x)
+
+#define MCR_MCLF(x)		((unsigned long)((x) & 15) << (31 - 23))
+#define MCR_MCLF_MASK		MCR_MCLF(15)
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+    /*
+     * Map controller bank 3 to the SDRAM bank at preliminary address.
+     */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C);	/* precharge all			*/
+	udelay(1);
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0)		*/
+	udelay(1);
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E);	/* exception program (write mar) */
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(1000);
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
+
+	size = SDRAM_MAX_SIZE;
+
+	udelay(10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+	last_er_val = 0xffffffff;
+#endif
+	return(0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(5) | _BWR(14, 15))
+#define PA_SP_MASK	(_BW(4) | _BWR(6, 13))
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	_BW(5)
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_MASK	_BR(22, 25)
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_DIRVAL	0
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+
+#define PC_GP_INMASK	(_BWR(5, 7) | _BWR(9, 10) | _BW(13))
+#define PC_GP_OUTMASK	_BW(12)
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	0
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+#define PD_GP_OUTVAL	(_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
+#define PD_SP_DIRVAL	0
+
+#elif CONFIG_NETVIA_VERSION >= 2
+
+#define PC_GP_INMASK	(_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
+#define PC_GP_OUTMASK	(_BW(6) | _BW(12))
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	_BW(7)
+#define PC_GP_OUTVAL	(_BW(6) | _BW(12))
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+#define PD_GP_OUTVAL	(_BW(3) | _BW(5) | _BW(9) | _BW(11))
+#define PD_SP_DIRVAL	0
+
+#else
+#error Unknown NETVIA board version.
+#endif
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* DSP0 chip select */
+	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+	/* DSP1 chip select */
+	memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+	/* FPGA chip select */
+	memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
+	memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+	/* NAND chip select */
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+	/* kill this chip select */
+	memctl->memc_br2 &= ~BR_V;	/* invalid */
+
+	/* external reg chip select */
+	memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
+	memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+#endif
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	ioport->iop_pddat	= PD_GP_OUTVAL;
+	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
+	ioport->iop_pdpar	= PD_SP_MASK;
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+	/* external register init */
+	*(volatile uint *)ER_BASE = 0xFFFFFFFF;
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/netvia/u-boot.lds b/u-boot/board/netvia/u-boot.lds
new file mode 100644
index 0000000..684ab81
--- /dev/null
+++ b/u-boot/board/netvia/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text	:
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/netvia/u-boot.lds.debug b/u-boot/board/netvia/u-boot.lds.debug
new file mode 100644
index 0000000..58202dc
--- /dev/null
+++ b/u-boot/board/netvia/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ns9750dev/Makefile b/u-boot/board/ns9750dev/Makefile
new file mode 100644
index 0000000..7794fbd
--- /dev/null
+++ b/u-boot/board/ns9750dev/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ns9750dev.o flash.o led.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ns9750dev/config.mk b/u-boot/board/ns9750dev/config.mk
new file mode 100644
index 0000000..e5d8702
--- /dev/null
+++ b/u-boot/board/ns9750dev/config.mk
@@ -0,0 +1,16 @@
+#######################################################################
+#
+# Copyright (C) 2004 by FS Forth-Systeme GmbH.
+# Markus Pietrek <mpietrek@fsforth.de>
+#
+# @TODO
+# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
+# optionally with a ramdisk at 0080'0000
+#
+# we load ourself to 0078'0000
+#
+# download area is 0060'0000
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0x00780000
diff --git a/u-boot/board/ns9750dev/flash.c b/u-boot/board/ns9750dev/flash.c
new file mode 100644
index 0000000..5b56b98
--- /dev/null
+++ b/u-boot/board/ns9750dev/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/ns9750dev/led.c b/u-boot/board/ns9750dev/led.c
new file mode 100644
index 0000000..b85c869
--- /dev/null
+++ b/u-boot/board/ns9750dev/led.c
@@ -0,0 +1,46 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Defines helper functions for toggeling LEDs
+ * @Usage:
+ * @References: [1]
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifdef CONFIG_STATUS_LED
+
+#include <ns9750_bbus.h>
+
+static inline void __led_init( led_id_t mask, int state )
+{
+	XXXX;
+}
+
+static inline void __led_toggle( led_id_t mask )
+{
+}
+
+static inline void __led_set( led_id_t mask, int state )
+{
+}
+
+#endif /* CONFIG_STATUS_LED */
diff --git a/u-boot/board/ns9750dev/lowlevel_init.S b/u-boot/board/ns9750dev/lowlevel_init.S
new file mode 100644
index 0000000..ba5ff81
--- /dev/null
+++ b/u-boot/board/ns9750dev/lowlevel_init.S
@@ -0,0 +1,298 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for the NS9750 DevBoard by
+ * (C) Copyright 2004 by FS Forth-Systeme GmbH.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ *	        [2] ns9750_a.cmd from MAJIC configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_NS9750DEV)
+# ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#  include <./ns9750_sys.h>
+#  include <./ns9750_mem.h>
+# endif
+#endif
+
+/***********************************************************************
+ * @Function: write_register_block
+ * @Return: nothing
+ * @Descr: Copies the register block of register_offset:register value to
+ *         the registers at base r0. The block is assumed to start in RAM at r1
+ *         and end at r2. The linked RAM base address of U-Boot is assumed to be
+ *	   in r5 while the ROM base address we are running from is r6
+ *         Uses r3 and r4 as tempory registers
+ ***********************************************************************/
+
+.macro	write_register_block
+	@@ map the addresses to high memory
+	sub	r1, r1, r5
+	add	r1, r1, r6
+	sub	r2, r2, r5
+	add	r2, r2, r6
+
+	@@ copy all
+1:
+	@@ Write register/value pair starting at [r1] to register base r0
+	ldr	r3, [r1], #4
+	ldr	r4, [r1], #4
+	str	r4, [r0,r3]
+	cmp	r1, r2
+	blt	1b
+.endm
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	@ sdram load addr from config.mk
+_PHYS_FLASH:
+	.word	PHYS_FLASH_1    @ real flash address (without mirroring)
+_CAS_LATENCY:
+	.word	0x00022000	@ for CAS2 latency
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+
+	/* U-Boot may be linked to RAM at 0x780000. But this code will run in
+	   flash from 0x0. But in order to enable RAM we have to disable the
+	   mirror bit, therefore we have to jump to our real flash address
+	   beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
+	   _run_at_real_flash_address may be 0x500003b0 while be linked to
+	   0x7803b0. So we must modify our linked addresses */
+
+	@@ branch to high memory address, away from 0x0
+	ldr	r5, _TEXT_BASE
+	ldr	r6, _PHYS_FLASH
+	ldr	r0, =_run_at_real_flash_address
+	sub	r0, r0, r5
+	add	r0, r0, r6
+	mov	pc, r0
+	nop			@ for pipelining
+
+_run_at_real_flash_address:
+	@@ now we are running > PHYS_FLASH_1, safe to enable memory controller
+
+	@@ Write Memory Configuration Registers
+
+	ldr	r0, _NS9750_MEM_MODULE_BASE
+	ldr	r1, =_MEM_CONFIG_START
+	ldr	r2, =_MEM_CONFIG_END
+
+	write_register_block
+
+	@@ Give SDRAM some time to settle
+	@@ @TODO. According to [2] it should be 2 AHB cycles. Check
+
+	ldr	r1, =0x50
+_sdram_settle:
+	subs	r1, r1, #1
+	bne	_sdram_settle
+
+_enable_mappings:
+	@@ Enable SDRAM Mode
+
+	ldr	r1, =_MEM_MODE_START
+	ldr	r2, =_MEM_MODE_END
+
+	write_register_block
+
+	ldr	r3, _CAS_LATENCY @ perform one read from SDRAM
+	ldr	r3, [r3]
+
+	@@ Enable SDRAM and memory mappings
+
+	ldr	r1, =_MEM_ENABLE_START
+	ldr	r2, =_MEM_ENABLE_END
+
+	write_register_block
+
+	@@ Activate AHB monitor
+
+	ldr	r0, =NS9750_SYS_MODULE_BASE
+	ldr	r1, =_AHB_MONITOR_START
+	ldr	r2, =_AHB_MONITOR_END
+
+	write_register_block
+_relocate_lr:
+	/* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
+	   PHYS_FLASH. */
+	mov	r1, ip
+	add	r1, r1, r6
+	mov	ip, r1
+
+	mov	r1, lr
+	add	r1, r1, r6
+	mov	lr, r1
+
+	@@ back to arch calling code
+	mov	pc,	lr
+
+	.ltorg
+
+_NS9750_MEM_MODULE_BASE:
+	.word	NS9750_MEM_MODULE_BASE
+
+_MEM_CONFIG_START:
+	/* Table of 2 32bit entries. First word is register address offset
+	   relative to NS9750_MEM_MODULE_BASE, second one is value. They are
+	   written in order of appearance */
+
+	@@ Register values taken from [2]
+	.word	NS9750_MEM_CTRL
+	.word	NS9750_MEM_CTRL_E
+
+	.word	NS9750_MEM_DYN_REFRESH
+	.word	(0x6 & NS9750_MEM_DYN_REFRESH_MA)
+
+	.word	NS9750_MEM_DYN_READ_CFG
+	.word	(0x1 & NS9750_MEM_DYN_READ_CFG_MA)
+
+	.word	NS9750_MEM_DYN_TRP
+	.word	(0x1 & NS9750_MEM_DYN_TRP_MA)
+
+	.word	NS9750_MEM_DYN_TRAS
+	.word	(0x4 & NS9750_MEM_DYN_TRAS_MA)
+
+	.word	NS9750_MEM_DYN_TAPR
+	.word	(0x1 & NS9750_MEM_DYN_TRAS_MA)
+
+	.word	NS9750_MEM_DYN_TDAL
+	.word	(0x5 & NS9750_MEM_DYN_TDAL_MA)
+
+	.word	NS9750_MEM_DYN_TWR
+	.word	(0x1 & NS9750_MEM_DYN_TWR_MA)
+
+	.word	NS9750_MEM_DYN_TRC
+	.word	(0x6 & NS9750_MEM_DYN_TRC_MA)
+
+	.word	NS9750_MEM_DYN_TRFC
+	.word	(0x6 & NS9750_MEM_DYN_TRFC_MA)
+
+	.word	NS9750_MEM_DYN_TRRD
+	.word	(0x1 & NS9750_MEM_DYN_TRRD_MA)
+
+	.word	NS9750_MEM_DYN_TMRD
+	.word	(0x1 & NS9750_MEM_DYN_TMRD_MA)
+
+	@@ CS 4
+	.word	NS9750_MEM_DYN_CFG(0)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(0)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	@@ CS 5
+	.word	NS9750_MEM_DYN_CFG(1)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(1)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	@@ CS 6
+	.word	NS9750_MEM_DYN_CFG(2)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(2)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	@@ CS 7
+	.word	NS9750_MEM_DYN_CFG(3)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(3)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	.word	NS9750_MEM_DYN_CTRL
+	.word	(NS9750_MEM_DYN_CTRL_I_PALL | \
+		 NS9750_MEM_DYN_CTRL_SR | \
+		 NS9750_MEM_DYN_CTRL_CE )
+
+	.word	NS9750_MEM_DYN_REFRESH
+	.word	(0x1 & NS9750_MEM_DYN_REFRESH_MA)
+	@@ No further register settings after refresh
+_MEM_CONFIG_END:
+
+_MEM_MODE_START:
+	.word	NS9750_MEM_DYN_REFRESH
+	.word	(0x30 & NS9750_MEM_DYN_REFRESH_MA)
+
+	.word	NS9750_MEM_DYN_CTRL
+	.word	(NS9750_MEM_DYN_CTRL_I_MODE | \
+		 NS9750_MEM_DYN_CTRL_SR | \
+		 NS9750_MEM_DYN_CTRL_CE )
+_MEM_MODE_END:
+
+_MEM_ENABLE_START:
+	.word	NS9750_MEM_DYN_CTRL
+	.word	(NS9750_MEM_DYN_CTRL_I_NORMAL | \
+		 NS9750_MEM_DYN_CTRL_SR | \
+		 NS9750_MEM_DYN_CTRL_CE )
+
+	@@ CS 4
+	.word	NS9750_MEM_DYN_CFG(0)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	@@ CS 5
+	.word	NS9750_MEM_DYN_CFG(1)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	@@ CS 6
+	.word	NS9750_MEM_DYN_CFG(2)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	@@ CS 7
+	.word	NS9750_MEM_DYN_CFG(3)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+_MEM_ENABLE_END:
+
+_AHB_MONITOR_START:
+	.word	NS9750_SYS_AHB_TIMEOUT
+	.word	0x01000100	@ @TODO not calculated yet
+
+	.word	NS9750_SYS_AHB_MON
+	.word	(NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
+		 NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
+_AHB_MONITOR_END:
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/u-boot/board/ns9750dev/ns9750dev.c b/u-boot/board/ns9750dev/ns9750dev.c
new file mode 100644
index 0000000..fc46244
--- /dev/null
+++ b/u-boot/board/ns9750dev/ns9750dev.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * derived from omap1610innovator.c
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_NS9750DEV)
+# include <./configs/ns9750dev.h>
+# include <./ns9750_bbus.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void flash__init( void );
+void ether__init( void );
+
+static inline void delay( unsigned long loops )
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+
+/***********************************************************************
+ * @Function: board_init
+ * @Return: 0
+ * @Descr: Enables BBUS modules and other devices
+ ***********************************************************************/
+
+int board_init( void )
+{
+	/* Active BBUS modules */
+	*get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;
+
+#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new
+	/* arch number of OMAP 1510-Board */
+	/* to be changed for OMAP 1610 Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable();
+
+	flash__init();
+	ether__init();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
diff --git a/u-boot/board/nvidia/common/board.c b/u-boot/board/nvidia/common/board.c
new file mode 100644
index 0000000..b2c412c
--- /dev/null
+++ b/u-boot/board/nvidia/common/board.c
@@ -0,0 +1,193 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct tegra2_sysinfo sysinfo = {
+	CONFIG_TEGRA2_BOARD_STRING
+};
+
+/*
+ * Routine: timer_init
+ * Description: init the timestamp and lastinc value
+ */
+int timer_init(void)
+{
+	reset_timer();
+	return 0;
+}
+
+/*
+ * Routine: clock_init_uart
+ * Description: init the PLL and clock for the UART(s)
+ */
+static void clock_init_uart(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	static int pllp_init_done;
+	u32 reg;
+
+	if (!pllp_init_done) {
+		/* Override pllp setup for 216MHz operation. */
+		reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
+		reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
+		writel(reg, &clkrst->crc_pllp_base);
+
+		reg |= PLL_ENABLE;
+		writel(reg, &clkrst->crc_pllp_base);
+
+		reg &= ~PLL_BYPASS;
+		writel(reg, &clkrst->crc_pllp_base);
+
+		pllp_init_done++;
+	}
+
+	/* Now do the UART reset/clock enable */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+	/* Assert Reset to UART */
+	reg = readl(&clkrst->crc_rst_dev_l);
+	reg |= SWR_UARTA_RST;		/* SWR_UARTA_RST = 1 */
+	writel(reg, &clkrst->crc_rst_dev_l);
+
+	/* Enable clk to UART */
+	reg = readl(&clkrst->crc_clk_out_enb_l);
+	reg |= CLK_ENB_UARTA;		/* CLK_ENB_UARTA = 1 */
+	writel(reg, &clkrst->crc_clk_out_enb_l);
+
+	/* Enable pllp_out0 to UART */
+	reg = readl(&clkrst->crc_clk_src_uarta);
+	reg &= 0x3FFFFFFF;	/* UARTA_CLK_SRC = 00, PLLP_OUT0 */
+	writel(reg, &clkrst->crc_clk_src_uarta);
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reg = readl(&clkrst->crc_rst_dev_l);
+	reg &= ~SWR_UARTA_RST;		/* SWR_UARTA_RST = 0 */
+	writel(reg, &clkrst->crc_rst_dev_l);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+	/* Assert Reset to UART */
+	reg = readl(&clkrst->crc_rst_dev_u);
+	reg |= SWR_UARTD_RST;		/* SWR_UARTD_RST = 1 */
+	writel(reg, &clkrst->crc_rst_dev_u);
+
+	/* Enable clk to UART */
+	reg = readl(&clkrst->crc_clk_out_enb_u);
+	reg |= CLK_ENB_UARTD;		/* CLK_ENB_UARTD = 1 */
+	writel(reg, &clkrst->crc_clk_out_enb_u);
+
+	/* Enable pllp_out0 to UART */
+	reg = readl(&clkrst->crc_clk_src_uartd);
+	reg &= 0x3FFFFFFF;	/* UARTD_CLK_SRC = 00, PLLP_OUT0 */
+	writel(reg, &clkrst->crc_clk_src_uartd);
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reg = readl(&clkrst->crc_rst_dev_u);
+	reg &= ~SWR_UARTD_RST;		/* SWR_UARTD_RST = 0 */
+	writel(reg, &clkrst->crc_rst_dev_u);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for the UART(s)
+ */
+static void pin_mux_uart(void)
+{
+	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 reg;
+
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+	reg = readl(&pmt->pmt_ctl_c);
+	reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
+	writel(reg, &pmt->pmt_ctl_c);
+
+	reg = readl(&pmt->pmt_tri_a);
+	reg &= ~Z_IRRX;		/* Z_IRRX = normal (0) */
+	reg &= ~Z_IRTX;		/* Z_IRTX = normal (0) */
+	writel(reg, &pmt->pmt_tri_a);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+	reg = readl(&pmt->pmt_ctl_b);
+	reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
+	writel(reg, &pmt->pmt_ctl_b);
+
+	reg = readl(&pmt->pmt_tri_a);
+	reg &= ~Z_GMC;		/* Z_GMC = normal (0) */
+	writel(reg, &pmt->pmt_tri_a);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: clock_init
+ * Description: Do individual peripheral clock reset/enables
+ */
+void clock_init(void)
+{
+	clock_init_uart();
+}
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pin_mux_uart();
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	/* boot param addr */
+	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+	/* board id for Linux */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* Initialize peripheral clocks */
+	clock_init();
+
+	/* Initialize periph pinmuxes */
+	pinmux_init();
+
+	return 0;
+}
+
diff --git a/u-boot/board/nvidia/harmony/Makefile b/u-boot/board/nvidia/harmony/Makefile
new file mode 100644
index 0000000..3a146cb
--- /dev/null
+++ b/u-boot/board/nvidia/harmony/Makefile
@@ -0,0 +1,50 @@
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= ../common/board.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/nvidia/seaboard/Makefile b/u-boot/board/nvidia/seaboard/Makefile
new file mode 100644
index 0000000..3a146cb
--- /dev/null
+++ b/u-boot/board/nvidia/seaboard/Makefile
@@ -0,0 +1,50 @@
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= ../common/board.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/nx823/Makefile b/u-boot/board/nx823/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/nx823/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/nx823/flash.c b/u-boot/board/nx823/flash.c
new file mode 100644
index 0000000..336e704
--- /dev/null
+++ b/u-boot/board/nx823/flash.c
@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#endif
+
+#define FPW		FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F320J3A:
+				printf ("28F320J3A\n"); break;
+   case FLASH_28F640J3A:
+				printf ("28F640J3A\n"); break;
+   case FLASH_28F128J3A:
+				printf ("28F128J3A\n"); break;
+	default:		printf ("Unknown Chip Type\n"); break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0x00AA00AA;
+	addr[0x2AAA] = (FPW)0x00550055;
+	addr[0x5555] = (FPW)0x00900090;
+
+	value = addr[0];
+
+   switch (value) {
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+   switch (value) {
+   case (FPW)INTEL_ID_28F320J3A:
+      info->flash_id += FLASH_28F320J3A;
+      info->sector_count = 32;
+      info->size = 0x00400000;
+      break;            /* => 4 MB     */
+
+   case (FPW)INTEL_ID_28F640J3A:
+      info->flash_id += FLASH_28F640J3A;
+      info->sector_count = 64;
+      info->size = 0x00800000;
+      break;            /* => 8 MB     */
+
+   case (FPW)INTEL_ID_28F128J3A:
+      info->flash_id += FLASH_28F128J3A;
+      info->sector_count = 128;
+      info->size = 0x01000000;
+      break;            /* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = (FPW)0x00500050;	/* clear status register */
+			*addr = (FPW)0x00200020;	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW)0x00B000B0; /* suspend erase	  */
+					*addr = (FPW)0x00FF00FF; /* reset to read mode */
+					rcode = 1;
+					break;
+				}
+
+				/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = (FPW)0x00FF00FF;	/* reset to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/* save sernum if needed */
+	if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE)
+	{
+		u_long dest = CONFIG_SYS_FLASH_SN_BASE;
+		u_short *sn = (u_short *)gd->bd->bi_sernum;
+
+		printf("(saving sernum)");
+		for (i=0; i<4; i++)
+		{
+			if ((rc = write_data(info, dest, sn[i])) != 0) {
+				return (rc);
+			}
+			dest += port_width;
+		}
+	}
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800)
+		{
+			putc('.');
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x00400040;		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW)0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
diff --git a/u-boot/board/nx823/nx823.c b/u-boot/board/nx823/nx823.c
new file mode 100644
index 0000000..7867fff
--- /dev/null
+++ b/u-boot/board/nx823/nx823.c
@@ -0,0 +1,390 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mpc8xx.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static long int dram_size (long int, long int *, long int);
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+#if (MPC8XX_SPEED <= 50000000L)
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
+	0xFFFFFFFF,
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FE7F434, 0xEFABE834, 0x1FA7D435,
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
+#else
+
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
+	0x1FF7F447,
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+	printf ("Board: Nexus NX823");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Up to 2 Banks of 64Mbit x 2 devices
+	 * Initial builds only have 1
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	udelay (200);
+
+	/*
+	 * Map controller SDRAM bank 1
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 1 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns     */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {		/* back to 8 columns                    */
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	/*
+	 * Check Bank 1 Memory Size
+	 * use current column settings
+	 * [9 column SDRAM may also be used in 8 column mode,
+	 *  but then only half the real size will be used.]
+	 */
+	size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
+			     SDRAM_MAX_SIZE);
+/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or2 =
+			((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or1 =
+				((-size_b0) & 0xFFFF0000) |
+				CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br1 =
+				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+				 BR_V)
+				+ size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br1 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {		/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or1 =
+			((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br1 =
+			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or2 =
+				((-size_b1) & 0xFFFF0000) |
+				CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br2 =
+				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+				 BR_V)
+				+ size_b0;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+int misc_init_r (void)
+{
+	int i;
+	char tmp[50];
+	uchar ethaddr[6];
+	bd_t *bd = gd->bd;
+	ulong *my_sernum = (unsigned long *)&bd->bi_sernum;
+
+	/* load unique serial number */
+	for (i = 0; i < 8; ++i)
+		bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
+
+	/* save env variables according to sernum */
+	sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
+	setenv ("serial#", tmp);
+
+	if (!eth_getenv_enetaddr("ethaddr", ethaddr)) {
+		ethaddr[0] = 0x10;
+		ethaddr[1] = 0x20;
+		ethaddr[2] = 0x30;
+		ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
+		ethaddr[4] = bd->bi_sernum[5];
+		ethaddr[5] = bd->bi_sernum[6];
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/nx823/u-boot.lds b/u-boot/board/nx823/u-boot.lds
new file mode 100644
index 0000000..4a96388
--- /dev/null
+++ b/u-boot/board/nx823/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2001-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/nx823/u-boot.lds.debug b/u-boot/board/nx823/u-boot.lds.debug
new file mode 100644
index 0000000..99098bf
--- /dev/null
+++ b/u-boot/board/nx823/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/o2dnt/Makefile b/u-boot/board/o2dnt/Makefile
new file mode 100644
index 0000000..3c99739
--- /dev/null
+++ b/u-boot/board/o2dnt/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/o2dnt/flash.c b/u-boot/board/o2dnt/flash.c
new file mode 100644
index 0000000..9f30880
--- /dev/null
+++ b/u-boot/board/o2dnt/flash.c
@@ -0,0 +1,587 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * flash_real_protect() routine based on boards/alaska/flash.c
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Intel-compatible flash commands */
+#define INTEL_ERASE	0x20
+#define INTEL_PROGRAM	0x40
+#define INTEL_CLEAR	0x50
+#define INTEL_LOCKBIT	0x60
+#define INTEL_PROTECT	0x01
+#define INTEL_STATUS	0x70
+#define INTEL_READID	0x90
+#define INTEL_READID	0x90
+#define INTEL_SUSPEND	0xB0
+#define INTEL_CONFIRM	0xD0
+#define INTEL_RESET	0xFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED	0x80
+#define INTEL_OK	0x80
+
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define FPW		FLASH_PORT_WIDTH
+#define FPWV		FLASH_PORT_WIDTHV
+#define	FLASH_ID_MASK	0xFF
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(ulong);
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Query flash chip */
+	flash_info[0].size =
+		flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	size += flash_info[0].size;
+
+	/* get the h/w and s/w protection status in sync */
+	flash_sync_real_protect(&flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+			flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+
+	flash_afterinit(size);
+	return (size ? size : 1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) INTEL_RESET;	/* Intel Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size &&
+				info->start[0] <= base &&
+				base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:
+			printf ("INTEL ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_28F128J3A:
+			fmt = "28F128J3 (128 Mbit, uniform sectors)\n";
+			break;
+		default:
+			fmt = "Unknown Chip Type\n";
+			break;
+	}
+
+	printf (fmt, bootletter, boottype);
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20,
+			info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW) INTEL_READID;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+		case (uchar)INTEL_MANUFACT:
+			info->flash_id = FLASH_MAN_INTEL;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	/* Strataflash is configurable to 8/16bit Bus,
+	 * but the Query-Structure is Word-orientated */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch ((FPW)addr[2]) {
+			case (FPW)INTEL_ID_28F128J3:
+				info->flash_id += FLASH_28F128J3A;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+				for( i = 0; i < info->sector_count; i++ )
+					info->start[i] = (ulong)addr + (i * 0x20000);
+				break;				/* => Intel Strataflash 16MB */
+			default:
+				printf("Flash_id != %xd\n", (FPW)addr[2]);
+				info->flash_id = FLASH_UNKNOWN;
+				info->sector_count = 0;
+				info->size = 0;
+				return (0);			/* => no or unknown flash */
+		}
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_28F128J3A:
+			break;
+		case FLASH_UNKNOWN:
+		default:
+			printf ("Can't erase unknown flash type %08lx - aborted\n",
+					info->flash_id);
+			return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!",
+				prot);
+
+	printf ("\n");
+	last = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		*addr = (FPW) INTEL_CLEAR; /* clear status register */
+		*addr = (FPW) INTEL_ERASE; /* erase setup */
+		*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 80us for Intel - let's wait 1 ms */
+		udelay (1000);
+
+		while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) INTEL_SUSPEND;/* suspend erase */
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode */
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0;	/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	/* number of bytes to program in current word		*/
+	int left;	/* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+			left > 0 && res == 0;
+			addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits  */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+			case FLASH_MAN_INTEL:
+				res = write_data(info, (FPWV *)addr, data);
+				break;
+			default:
+				/* unknown flash type, error! */
+				printf ("missing or unknown FLASH type\n");
+				res = 1;	/* not really a timeout, but gives error */
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, FPWV *dest, FPW data)
+{
+	FPWV *addr = dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) INTEL_PROGRAM;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) INTEL_RESET;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+	if (flag)
+		enable_interrupts();
+
+	return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	FPWV *addr = (FPWV *) (info->start[sector]);
+	int flag = disable_interrupts ();
+
+	*addr = INTEL_CLEAR;	/* Clear status register    */
+	if (prot) {		/* Set sector lock bit      */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
+		*addr = INTEL_PROTECT;	/* set                      */
+	} else {		/* Clear sector lock bit    */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
+		*addr = INTEL_CONFIRM;	/* clear                    */
+	}
+
+	start = get_timer (0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+			printf ("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
+			(uint) addr, (uint) * addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (info->protect[i]) {
+				start = get_timer (0);
+				addr = (FPWV *) (info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
+				*addr = INTEL_PROTECT;	/* set              */
+				while ((*addr & INTEL_FINISHED) !=
+				       INTEL_FINISHED) {
+					if (get_timer (start) >
+					    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+						printf ("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts ();
+
+	*addr = INTEL_RESET;	/* Reset to read array mode */
+
+	return rc;
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 4 for 8-bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 4;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
diff --git a/u-boot/board/o2dnt/o2dnt.c b/u-boot/board/o2dnt/o2dnt.c
new file mode 100644
index 0000000..c72a741
--- /dev/null
+++ b/u-boot/board/o2dnt/o2dnt.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#define SDRAM_MODE      0x00CD0000
+#define SDRAM_CONTROL   0x504F0000
+#define SDRAM_CONFIG1   0xD2322800
+#define SDRAM_CONFIG2   0x8AD70000
+
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	else
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: O2DNT\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x800000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
+
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/overo/Makefile b/u-boot/board/overo/Makefile
new file mode 100644
index 0000000..22ba774
--- /dev/null
+++ b/u-boot/board/overo/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= overo.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+#########################################################################
+sinclude $(obj).depend
diff --git a/u-boot/board/overo/config.mk b/u-boot/board/overo/config.mk
new file mode 100644
index 0000000..e7c471c
--- /dev/null
+++ b/u-boot/board/overo/config.mk
@@ -0,0 +1,28 @@
+#
+# Overo uses OMAP3 (ARM-CortexA8) cpu
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/overo/overo.c b/u-boot/board/overo/overo.c
new file mode 100644
index 0000000..4eafdb1
--- /dev/null
+++ b/u-boot/board/overo/overo.c
@@ -0,0 +1,351 @@
+/*
+ * Maintainer : Steve Sakoman <steve@sakoman.com>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "overo.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TWL4030_I2C_BUS			0
+#define EXPANSION_EEPROM_I2C_BUS	2
+#define EXPANSION_EEPROM_I2C_ADDRESS	0x51
+
+#define GUMSTIX_SUMMIT			0x01000200
+#define GUMSTIX_TOBI			0x02000200
+#define GUMSTIX_TOBI_DUO		0x03000200
+#define GUMSTIX_PALO35			0x04000200
+#define GUMSTIX_PALO43			0x05000200
+#define GUMSTIX_CHESTNUT43		0x06000200
+#define GUMSTIX_PINTO			0x07000200
+#define GUMSTIX_GALLOP43		0x08000200
+
+#define ETTUS_USRP_E			0x01000300
+
+#define GUMSTIX_NO_EEPROM		0xffffffff
+
+static struct {
+	unsigned int device_vendor;
+	unsigned char revision;
+	unsigned char content;
+	char fab_revision[8];
+	char env_var[16];
+	char env_setting[64];
+} expansion_config;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif
+
+/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
+static const u32 gpmc_lan_config[] = {
+    NET_LAN9221_GPMC_CONFIG1,
+    NET_LAN9221_GPMC_CONFIG2,
+    NET_LAN9221_GPMC_CONFIG3,
+    NET_LAN9221_GPMC_CONFIG4,
+    NET_LAN9221_GPMC_CONFIG5,
+    NET_LAN9221_GPMC_CONFIG6,
+    /*CONFIG7- computed as params */
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OVERO;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+int get_board_revision(void)
+{
+	int revision;
+
+	if (!omap_request_gpio(112) &&
+	    !omap_request_gpio(113) &&
+	    !omap_request_gpio(115)) {
+
+		omap_set_gpio_direction(112, 1);
+		omap_set_gpio_direction(113, 1);
+		omap_set_gpio_direction(115, 1);
+
+		revision = omap_get_gpio_datain(115) << 2 |
+			   omap_get_gpio_datain(113) << 1 |
+			   omap_get_gpio_datain(112);
+
+		omap_free_gpio(112);
+		omap_free_gpio(113);
+		omap_free_gpio(115);
+	} else {
+		printf("Error: unable to acquire board revision GPIOs\n");
+		revision = -1;
+	}
+
+	return revision;
+}
+
+/*
+ * Routine: get_sdio2_config
+ * Description: Return information about the wifi module connection
+ *              Returns 0 if the module connects though a level translator
+ *              Returns 1 if the module connects directly
+ */
+int get_sdio2_config(void)
+{
+	int sdio_direct;
+
+	if (!omap_request_gpio(130) && !omap_request_gpio(139)) {
+
+		omap_set_gpio_direction(130, 0);
+		omap_set_gpio_direction(139, 1);
+
+		sdio_direct = 1;
+		omap_set_gpio_dataout(130, 0);
+		if (omap_get_gpio_datain(139) == 0) {
+			omap_set_gpio_dataout(130, 1);
+			if (omap_get_gpio_datain(139) == 1)
+				sdio_direct = 0;
+		}
+
+		omap_free_gpio(130);
+		omap_free_gpio(139);
+	} else {
+		printf("Error: unable to acquire sdio2 clk GPIOs\n");
+		sdio_direct = -1;
+	}
+
+	return sdio_direct;
+}
+
+/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ *		bus 2 for the availability of an AT24C01B serial EEPROM.
+ *		returns the device_vendor field from the EEPROM
+ */
+unsigned int get_expansion_id(void)
+{
+	i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+
+	/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
+	if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+		i2c_set_bus_num(TWL4030_I2C_BUS);
+		return GUMSTIX_NO_EEPROM;
+	}
+
+	/* read configuration data */
+	i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+		 sizeof(expansion_config));
+
+	i2c_set_bus_num(TWL4030_I2C_BUS);
+
+	return expansion_config.device_vendor;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+
+	printf("Board revision: %d\n", get_board_revision());
+
+	switch (get_sdio2_config()) {
+	case 0:
+		printf("Tranceiver detected on mmc2\n");
+		MUX_OVERO_SDIO2_TRANSCEIVER();
+		break;
+	case 1:
+		printf("Direct connection on mmc2\n");
+		MUX_OVERO_SDIO2_DIRECT();
+		break;
+	default:
+		printf("Unable to detect mmc2 connection type\n");
+	}
+
+	switch (get_expansion_id()) {
+	case GUMSTIX_SUMMIT:
+		printf("Recognized Summit expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		setenv("defaultdisplay", "dvi");
+		break;
+	case GUMSTIX_TOBI:
+		printf("Recognized Tobi expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		setenv("defaultdisplay", "dvi");
+		break;
+	case GUMSTIX_TOBI_DUO:
+		printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		break;
+	case GUMSTIX_PALO35:
+		printf("Recognized Palo35 expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		setenv("defaultdisplay", "lcd35");
+		break;
+	case GUMSTIX_PALO43:
+		printf("Recognized Palo43 expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		setenv("defaultdisplay", "lcd43");
+		break;
+	case GUMSTIX_CHESTNUT43:
+		printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		setenv("defaultdisplay", "lcd43");
+		break;
+	case GUMSTIX_PINTO:
+		printf("Recognized Pinto expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		break;
+	case GUMSTIX_GALLOP43:
+		printf("Recognized Gallop43 expansion board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		setenv("defaultdisplay", "lcd43");
+		break;
+	case ETTUS_USRP_E:
+		printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		MUX_USRP_E();
+		setenv("defaultdisplay", "dvi");
+		break;
+	case GUMSTIX_NO_EEPROM:
+		printf("No EEPROM on expansion board\n");
+		break;
+	default:
+		printf("Unrecognized expansion board\n");
+	}
+
+	if (expansion_config.content == 1)
+		setenv(expansion_config.env_var, expansion_config.env_setting);
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_OVERO();
+}
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *	      Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* first lan chip */
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+			GPMC_SIZE_16M);
+
+	/* second lan chip */
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
+			GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 64 as output pin and send a magic pulse through it */
+	if (!omap_request_gpio(64)) {
+		omap_set_gpio_direction(64, 0);
+		omap_set_gpio_dataout(64, 1);
+		udelay(1);
+		omap_set_gpio_dataout(64, 0);
+		udelay(1);
+		omap_set_gpio_dataout(64, 1);
+	}
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/overo/overo.h b/u-boot/board/overo/overo.h
new file mode 100644
index 0000000..68e1243
--- /dev/null
+++ b/u-boot/board/overo/overo.h
@@ -0,0 +1,426 @@
+/*
+ * (C) Copyright 2008
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OVERO_H_
+#define _OVERO_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"Gumstix Overo board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00080701
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x08030703
+#define NET_LAN9221_GPMC_CONFIG5    0x00060908
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_OVERO() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | EN  | M4)) /*GPIO_54*/\
+								 /* - MMC1_WP*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+								 /* - SMSC911X_NRES*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | DIS | M4)) /*GPIO_65*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M0)) /*CAM_WEN*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | EN  | M4)) /*GPIO_112*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | EN  | M4)) /*GPIO_113*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M4)) /*GPIO_114*/\
+								 /* - PEN_DOWN*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | EN  | M4)) /*GPIO_115*/\
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IEN  | PTU | DIS | M4)) /*GPIO_149*/ \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP4_CLKX*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*McBSP4_DR*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M0)) /*McBSP4_DX*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP4_FSX*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /*McBSP1_CLKR*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTD | DIS | M0)) /*McBSP1_FSR*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IEN  | PTD | DIS | M0)) /*McBSP1_DX*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) /*McBSP1_DR*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP1_FSX*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP1_CLKX*/\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IEN  | PTU | EN  | M4)) /*GPIO_164 W2W_*/\
+								 /* BT_NRESET*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M4)) /*GPIO_168*/\
+								 /* - USBH_CPEN*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+								 /* - USBH_RESET*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*HDQ_SIO*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO */\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI */\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176 */\
+								 /* - LAN_INTR */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CLK*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_14*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN  | M4)) /*GPIO_15 - X_GATE*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_16*/\
+								 /* - W2W_NRESET*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_22*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_23*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DIR*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_NXT*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
+ /* die to die */\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_OVERO_SDIO2_DIRECT() \
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT4*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT5*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT6*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | EN  | M4)) /*GPIO_126*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_127*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_128*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_129*/
+
+#define MUX_OVERO_SDIO2_TRANSCEIVER() \
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_126*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_127*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_128*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_129*/
+
+#define MUX_USRP_E() \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M4)) /*GPIO_173 */\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M4)) /*GPIO_175 */\
+
+#endif
diff --git a/u-boot/board/oxc/Makefile b/u-boot/board/oxc/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/oxc/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/oxc/flash.c b/u-boot/board/oxc/flash.c
new file mode 100644
index 0000000..36e0fca
--- /dev/null
+++ b/u-boot/board/oxc/flash.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for STM29W320DB/STM29W800D flash chips
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /*
+     * We use the following trick here: since flash is cyclically
+     * mapped in the 0xFF800000-0xFFFFFFFF area, we detect the type
+     * and the size of flash using 0xFF800000 as the base address,
+     * and then call flash_get_size() again to fill flash_info.
+     */
+    size = flash_get_size((vu_char *)CONFIG_SYS_FLASH_PRELIMBASE, &flash_info[0]);
+    if (size)
+    {
+	flash_get_size((vu_char *)(-size), &flash_info[0]);
+    }
+
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_PRELIMBASE)
+    /* monitor protection ON by default */
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_STM:
+	printf ("ST ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case FLASH_STM320DB:
+	printf ("M29W320DB (32 Mbit)\n");
+	break;
+    case FLASH_STM800DB:
+	printf ("M29W800DB (8 Mbit, bottom boot block)\n");
+	break;
+    case FLASH_STM800DT:
+	printf ("M29W800DT (8 Mbit, top boot block)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld KB in %d Sectors\n",
+	    info->size >> 10, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+    short i;
+    uchar vendor, devid;
+    ulong base = (ulong)addr;
+
+    /* Write auto select command: read Manufacturer ID */
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+    addr[0x0AAA] = 0x90;
+
+    udelay(1000);
+
+    vendor = addr[0];
+    devid = addr[2];
+
+    /* only support STM */
+    if ((vendor << 16) != FLASH_MAN_STM) {
+	return 0;
+    }
+
+    if (devid == FLASH_STM320DB) {
+	/* MPC8240 can address maximum 2Mb of flash, that is why the MSB
+	 * lead is grounded and we can access only 2 first Mb */
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 32;
+	info->size         = info->sector_count * 0x10000;
+	for (i = 0; i < info->sector_count; i++) {
+	    info->start[i] = base + i * 0x10000;
+	}
+    }
+    else if (devid == FLASH_STM800DB) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 19;
+	info->size         = 0x100000;
+	info->start[0]     = 0x0000;
+	info->start[1]     = 0x4000;
+	info->start[2]     = 0x6000;
+	info->start[3]     = 0x8000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i-3) * 0x10000;
+	}
+    }
+    else if (devid == FLASH_STM800DT) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 19;
+	info->size         = 0x100000;
+	for (i = 0; i < info->sector_count-4; i++) {
+	    info->start[i] = base + i * 0x10000;
+	}
+	info->start[i]     = base + i * 0x10000;
+	info->start[i+1]   = base + i * 0x10000 + 0x8000;
+	info->start[i+2]   = base + i * 0x10000 + 0xa000;
+	info->start[i+3]   = base + i * 0x10000 + 0xc000;
+    }
+    else {
+	return 0;
+    }
+
+    /* mark all sectors as unprotected */
+    for (i = 0; i < info->sector_count; i++) {
+	info->protect[i] = 0;
+    }
+
+    /* Issue the reset command */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	addr[0] = 0xF0;	/* reset bank */
+    }
+
+    return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_char *addr = (vu_char *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+    addr[0x0AAA] = 0x80;
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_char *)(info->start[sect]);
+	    addr[0] = 0x30;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_char *)(info->start[l_sect]);
+    while ((addr[0] & 0x80) != 0x80) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned char *)info->start[0];
+    addr[0] = 0xF0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    int rc;
+
+    while (cnt > 0) {
+	if ((rc = write_byte(info, addr, *src)) != 0) {
+	    return (rc);
+	}
+	addr++;
+	src++;
+	cnt--;
+    }
+
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+    vu_char *addr = (vu_char *)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_char *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+    addr[0x0AAA] = 0xA0;
+
+    *((vu_char *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/oxc/oxc.c b/u-boot/board/oxc/oxc.c
new file mode 100644
index 0000000..1a2bdf4
--- /dev/null
+++ b/u-boot/board/oxc/oxc.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+	puts (	"Board: OXC8240\n" );
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+#ifndef CONFIG_SYS_RAMBOOT
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+#else
+	/* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */
+	return (16 << 20);
+#endif
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_oxc_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x14, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x15, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_oxc_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_early_init_f (void)
+{
+	*(volatile unsigned char *)(CONFIG_SYS_CPLD_RESET) = 0x89;
+	return 0;
+}
+
+#ifdef CONFIG_WATCHDOG
+void oxc_wdt_reset(void)
+{
+	*(volatile unsigned char *)(CONFIG_SYS_CPLD_WATCHDOG) = 0xff;
+}
+
+void watchdog_reset(void)
+{
+	int re_enable = disable_interrupts();
+
+	oxc_wdt_reset();
+	if (re_enable)
+		enable_interrupts();
+}
+#endif
+
+static int oxc_get_expander(unsigned char addr, unsigned char * val)
+{
+	return i2c_read(addr, 0, 0, val, 1);
+}
+
+static int oxc_set_expander(unsigned char addr, unsigned char val)
+{
+	return i2c_write(addr, 0, 0, &val, 1);
+}
+
+static int expander0alive = 0;
+
+#ifdef CONFIG_SHOW_ACTIVITY
+static int ledtoggle = 0;
+static int ledstatus = 1;
+
+void oxc_toggle_activeled(void)
+{
+	ledtoggle++;
+}
+
+void board_show_activity (ulong timestamp)
+{
+	if ((timestamp % (CONFIG_SYS_HZ / 10)) == 0)
+		oxc_toggle_activeled ();
+}
+
+void show_activity(int arg)
+{
+	static unsigned char led = 0;
+	unsigned char val;
+
+	if (!expander0alive) return;
+
+	if ((ledtoggle > (2 * arg)) && ledstatus) {
+		led ^= 0x80;
+		oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val);
+		udelay(200);
+		oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, (val & 0x7F) | led);
+		ledtoggle = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int arg)
+{
+	unsigned char val;
+
+	if (!expander0alive) return;
+
+	if (arg > 0 && ledstatus) {
+		ledstatus = 0;
+		oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val);
+		udelay(200);
+		oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, val | 0x80);
+	} else if (arg < 0) {
+		oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val);
+		udelay(200);
+		oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, val & 0x7F);
+		ledstatus = 1;
+	}
+}
+#endif
+
+int misc_init_r (void)
+{
+	/* check whether the i2c expander #0 is accessible */
+	if (!oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, 0x7F)) {
+		udelay(200);
+		expander0alive = 1;
+	}
+
+#ifdef CONFIG_SYS_OXC_GENERATE_IP
+	{
+		char str[32];
+		unsigned long ip = CONFIG_SYS_OXC_IPMASK;
+		bd_t *bd = gd->bd;
+
+		if (expander0alive) {
+			unsigned char val;
+
+			if (!oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val)) {
+				ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2);
+			}
+		}
+
+		if ((ip & 0xff) < 3) {
+			/* if fail, set x.x.x.254 */
+			ip = (ip & 0xffffff00) | 0xfe;
+		}
+
+		bd->bi_ip_addr = ip;
+		sprintf(str, "%ld.%ld.%ld.%ld",
+			(bd->bi_ip_addr & 0xff000000) >> 24,
+			(bd->bi_ip_addr & 0x00ff0000) >> 16,
+			(bd->bi_ip_addr & 0x0000ff00) >> 8,
+			(bd->bi_ip_addr & 0x000000ff));
+		setenv("ipaddr", str);
+		printf("ip:    %s\n", str);
+	}
+#endif
+	return (0);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/palmld/Makefile b/u-boot/board/palmld/Makefile
new file mode 100644
index 0000000..29cdaee
--- /dev/null
+++ b/u-boot/board/palmld/Makefile
@@ -0,0 +1,47 @@
+#
+# Palm LifeDrive Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= palmld.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/palmld/palmld.c b/u-boot/board/palmld/palmld.c
new file mode 100644
index 0000000..5588fe7
--- /dev/null
+++ b/u-boot/board/palmld/palmld.c
@@ -0,0 +1,79 @@
+/*
+ * Palm LifeDrive Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of PalmLD */
+	gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* Set PWM for LCD */
+	writel(0x7, PWM_CTRL0);
+	writel(0x16c, PWM_PERVAL0);
+	writel(0x11a, PWM_PWDUTY0);
+
+	return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+	return &serial_ffuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	info->portwidth = FLASH_CFI_16BIT;
+	info->chipwidth = FLASH_CFI_BY16;
+	info->interface = FLASH_CFI_X16;
+	return 1;
+}
diff --git a/u-boot/board/palmtc/Makefile b/u-boot/board/palmtc/Makefile
new file mode 100644
index 0000000..15ef659
--- /dev/null
+++ b/u-boot/board/palmtc/Makefile
@@ -0,0 +1,48 @@
+#
+# Palm Tungsten|C Support
+#
+# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= palmtc.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/palmtc/palmtc.c b/u-boot/board/palmtc/palmtc.c
new file mode 100644
index 0000000..25186ae
--- /dev/null
+++ b/u-boot/board/palmtc/palmtc.c
@@ -0,0 +1,70 @@
+/*
+ * Palm Tungsten|C Support
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* Arch number of Palm Tungsten|C */
+	gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
+
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* Set PWM for LCD */
+	writel(0x5f, PWM_CTRL1);
+	writel(0x3ff, PWM_PERVAL1);
+	writel(892, PWM_PWDUTY1);
+
+	return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+	return &serial_ffuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
diff --git a/u-boot/board/pandora/Makefile b/u-boot/board/pandora/Makefile
new file mode 100644
index 0000000..0308681
--- /dev/null
+++ b/u-boot/board/pandora/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= pandora.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pandora/pandora.c b/u-boot/board/pandora/pandora.c
new file mode 100644
index 0000000..992e9f7
--- /dev/null
+++ b/u-boot/board/pandora/pandora.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2008
+ * Grazvydas Ignotas <notasas@gmail.com>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "pandora.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TWL4030_BB_CFG_BBCHEN		(1 << 4)
+#define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
+#define TWL4030_BB_CFG_BBISEL_500UA	2
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+	struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
+
+	/* Configure GPIOs to output */
+	writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
+	writel(~GPIO22, &gpio4_base->oe);	/* 118 */
+	writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31),
+		&gpio5_base->oe);	/* 128, 129, 156-159 */
+	writel(~GPIO4, &gpio6_base->oe);	/* 164 */
+
+	/* Set GPIOs */
+	writel(GPIO28, &gpio5_base->setdataout);
+	writel(GPIO4, &gpio6_base->setdataout);
+
+	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+		TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
+		TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_PANDORA();
+}
diff --git a/u-boot/board/pandora/pandora.h b/u-boot/board/pandora/pandora.h
new file mode 100644
index 0000000..f0ad16b
--- /dev/null
+++ b/u-boot/board/pandora/pandora.h
@@ -0,0 +1,402 @@
+/*
+ * (C) Copyright 2008
+ * Grazvydas Ignotas <notasas@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PANDORA_H_
+#define _PANDORA_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Pandora",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_PANDORA() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*GPIO based game buttons*/\
+	MUX_VAL(CP(CAM_XCLKA),		(IEN  | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTD | DIS | M4)) /*GPIO_97 - L2*/\
+	MUX_VAL(CP(CAM_FLD),		(IEN  | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M4)) /*GPIO_100 - START*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M4)) /*GPIO_101 - Y*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M4)) /*GPIO_102 - L1*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M4)) /*GPIO_105 - R1*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M4)) /*GPIO_106 - B*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M4)) /*GPIO_107 - R2*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M4)) /*GPIO_109 - X*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M4)) /*GPIO_110 - UP*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | DIS | M4)) /*GPIO_111 - A*/\
+ /*Audio Interface To External DAC (Headphone, Speakers)*/\
+	MUX_VAL(CP(MCBSP2_FSX),		(IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | DIS | M0)) /*McBSP_CLKS*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_118*/\
+								 /* - nPOWERDOWN_DAC*/\
+ /*Expansion card 1*/\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
+ /*Expansion card 2*/\
+	MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
+ /*SDIO Interface to WIFI Module*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTD | DIS | M2)) /*MMC3_CLK*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
+ /*Audio Interface To Bluetooth chip*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
+ /*Digital Interface to Bluetooth (UART)*/\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | EN  | M0)) /*UART1_CTS*/\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+ /*Audio Interface to Triton2 chip (TPS65950)*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP4_CLKX*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*McBSP4_DR*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP4_FSX*/\
+ /*GPIO definitions for muxed pins on AV connector*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | EN  | M4)) /*GPIO_144,*/\
+								 /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | EN  | M4)) /*GPIO_145,*/\
+								 /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | EN  | M4)) /*GPIO_146,*/\
+								 /*UART2_TX*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M4)) /*GPIO_147,*/\
+								 /*UART2_RX*/\
+ /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
+ /*RX pulled up to avoid noise when nothing is connected to serial port*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX*/\
+ /*LEDs (Controlled by OMAP)*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IDIS | PTD | DIS | M4)) /*GPIO_128*/\
+								 /* - LED_MMC1*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTD | DIS | M4)) /*GPIO_129*/\
+								 /* - LED_MMC2*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+								 /* - LED_BT*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+								 /* - LED_WIFI*/\
+ /*Switches*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176*/\
+								 /* - nHOLD_SWITCH*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M4)) /*GPIO_108*/\
+								 /* - nLID_SWITCH*/\
+ /*External IRQs*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTD | DIS | M4)) /*GPIO_94*/\
+								 /* - nTOUCH_IRQ*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M4)) /*GPIO_21*/\
+								 /* - WIFI_IRQ*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M4)) /*GPIO_161*/\
+								 /* - nIRQ_NUB1*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_162*/\
+								 /* - nIRQ_NUB2*/\
+ /*Various other stuff*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | DIS | M4)) /*GPIO_163*/\
+								 /* - nOC_USB5*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M4)) /*GPIO_22*/\
+								 /* - MSECURE*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M4)) /*GPIO_115*/\
+								 /* - POP_OVERHEAT*/\
+ /*External Resets and Enables*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_14*/\
+								 /* - nHDPHN_SHUTDOWN*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_15*/\
+								 /* - nBT_SHUTDOWN*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_23*/\
+								 /* - nWIFI_RESET*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)) /*GPIO_157*/\
+								 /* - nLCD_RESET*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+								 /* - RESET_NUBS*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M4)) /*GPIO_164*/\
+								 /* - EN_USB_5V*/\
+ /*Spare GPIOs*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTD | EN  | M4)) /*GPIO_58*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTD | EN  | M4)) /*GPIO_64*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTD | EN  | M4)) /*GPIO_65*/\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M4)) /*GPIO_95*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | EN  | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTD | EN  | M4)) /*GPIO_170*/\
+ /*HS USB OTG Port (connects to HSUSB0)*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ /*I2C Ports*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL - T2_CTRL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA - T2_CTRL*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL - NUBS*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA - NUBS*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL - T2_SR*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA - T2_SR*/\
+ /*Serial Interface (Touch, LCD control)*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IDIS | PTU | EN  | M0)) /*McSPI1_CS0 - TOUCH*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTU | EN  | M0)) /*McSPI1_CS1 - LCD*/\
+ /*HS USB HOST Port (connects to HSUSB2)*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | EN  | M3)) /*USB_HOST_STP*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_DIR*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_NXT*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D0*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D1*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D2*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D3*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D6*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D7*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_16*/\
+								 /* - nRESET_USB_HOST*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | DIS | M4)) /*GPIO_8*/\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ /*JTAG*/\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ /*Die to Die stuff*/\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm*/\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq*/\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/u-boot/board/pb1x00/Makefile b/u-boot/board/pb1x00/Makefile
new file mode 100644
index 0000000..f1594a2
--- /dev/null
+++ b/u-boot/board/pb1x00/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pb1x00/README b/u-boot/board/pb1x00/README
new file mode 100644
index 0000000..b1e9494
--- /dev/null
+++ b/u-boot/board/pb1x00/README
@@ -0,0 +1,63 @@
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+########     NOTE!!!!!!   #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/u-boot/board/pb1x00/config.mk b/u-boot/board/pb1x00/config.mk
new file mode 100644
index 0000000..6f3dc08
--- /dev/null
+++ b/u-boot/board/pb1x00/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy Pb1x00, MIPS32 core
+#
+
+# ROM version
+#CONFIG_SYS_TEXT_BASE = 0xbfc00000
+
+# SDRAM version
+CONFIG_SYS_TEXT_BASE = 0x83800000
diff --git a/u-boot/board/pb1x00/flash.c b/u-boot/board/pb1x00/flash.c
new file mode 100644
index 0000000..a2fed1d
--- /dev/null
+++ b/u-boot/board/pb1x00/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	printf ("Skipping flash_init\n");
+	return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	printf ("write_buff not implemented\n");
+	return (-1);
+}
diff --git a/u-boot/board/pb1x00/lowlevel_init.S b/u-boot/board/pb1x00/lowlevel_init.S
new file mode 100644
index 0000000..b145e43
--- /dev/null
+++ b/u-boot/board/pb1x00/lowlevel_init.S
@@ -0,0 +1,391 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR		0xB1900000
+#define sys_endian		0x0038
+#define CP0_Config0		$16
+#define MEM_1MS			((396000000/1000000) * 1000)
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/*
+	 * Step 1) Establish CPU endian mode.
+	 * NOTE: A fair amount of code is necessary on the Pb1000 to
+	 * obtain the value of Switch S8.1 which is used to determine
+	 * endian at run-time.
+	 */
+
+	/* RCE1 */
+	li		t0, MEM_STCFG1
+	li		t1, 0x00000083
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STTIME1
+	li		t1, 0x33030A10
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STADDR1
+	li		t1, 0x11803E40
+	sw		t1, 0(t0)
+
+	/* Set DSTRB bits so switch will read correctly */
+	li		t1, 0xBE00000C
+	lw		t2, 0(t1)
+	or		t2, t2, 0x00000300
+	sw		t2, 0(t1)
+
+	/* Check switch setting */
+	li		t1, 0xBE000014
+	lw		t2, 0(t1)
+	and		t2, t2, 0x00000100
+	bne		t2, zero, big_endian
+	nop
+
+little_endian:
+
+	/* Change Au1 core to little endian */
+	li	t0, AU1500_SYS_ADDR
+	li	t1, 1
+	sw	t1, sys_endian(t0)
+	mfc0	t2, CP0_CONFIG
+	mtc0	t2, CP0_CONFIG
+	nop
+	nop
+
+	/* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12 MHz crystal */
+	li	t0, SYS_CPUPLL
+	li	t1, 0x21  /* 396 MHz */
+	sw	t1, 0(t0)
+	sync
+	nop
+	nop
+
+	/* wait 1mS for clocks to settle */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+	/* Setup AUX PLL */
+	li	t0, SYS_AUXPLL
+	li	t1, 8 /* 96 MHz */
+	sw	t1, 0(t0) /* aux pll */
+	sync
+
+	/*  Static memory controller */
+
+	/* RCE0 8MB AMD29D323 Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00001403
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME0
+	li	t1, 0xFFFFFFDD
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11F83FE0
+	sw	t1, 0(t0)
+
+	/* RCE1 CPLD Board Logic */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000083
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x33030A10
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x11803E40
+	sw	t1, 0(t0)
+
+	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000004
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x08061908
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x12A03FC0
+	sw	t1, 0(t0)
+
+	/* RCE3 PCMCIA 250ns */
+	li	t0, MEM_STCFG3
+	li	t1, 0x00000002
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0x280E3E07
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0x10000000
+	sw	t1, 0(t0)
+
+	sync
+
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+	/*
+	 * Skip memory setup if we are running from memory
+	 */
+	li		t0, 0x90000000
+	sub		t0, ra, t0
+	bltz		t0, skip_memsetup
+	nop
+
+	/*
+	 * SDCS0 - Not used, for SMROM
+	 * SDCS1 - 32MB Micron 48LCBM16A2
+	 * SDCS2 - 32MB Micron 48LCBM16A2
+	 */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x00552229
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x00552229
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0x001003F8
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0x001023F8
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x74000c30 /* Disable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x76000c30 /* Enable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+skip_memsetup:
+
+	li	t0, SYS_PINFUNC
+	li	t1, 0/*0x00008080*/
+	sw	t1, 0(t0)
+
+	/*
+	li	t0, SYS_TRIOUTCLR
+	li	t1, 0x00001FFF
+	sw	t1, 0(t0)
+
+	li	t0, SYS_OUTPUTCLR
+	li	t1, 0x00008000
+	sw	t1, 0(t0)
+	*/
+	sync
+
+	jr	ra
+	nop
diff --git a/u-boot/board/pb1x00/pb1x00.c b/u-boot/board/pb1x00/pb1x00.c
new file mode 100644
index 0000000..2510ddf
--- /dev/null
+++ b/u-boot/board/pb1x00/pb1x00.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+
+phys_size_t initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN		0x0010
+#define BCSR_PCMCIA_PC0RST		0x0080
+
+/* In arch/mips/cpu/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+#if defined(CONFIG_IDE_PCMCIA) && 0
+	u16 status;
+#endif
+	/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
+	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+	u32 proc_id;
+
+	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+	proc_id = read_c0_prid();
+
+	switch (proc_id >> 24) {
+	case 0:
+		puts ("Board: Pb1000\n");
+		printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 1:
+		puts ("Board: Pb1500\n");
+		printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 2:
+		puts ("Board: Pb1100\n");
+		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	default:
+		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+	}
+
+	set_io_port_base(0);
+
+#if defined(CONFIG_IDE_PCMCIA) && 0
+	/* Enable 3.3 V on slot 0 ( VCC )
+	   No 5V */
+	status = 4;
+	*pcmcia_bcsr = status;
+
+	status |= BCSR_PCMCIA_PC0DRVEN;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(300*1000);
+
+	status |= BCSR_PCMCIA_PC0RST;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(100*1000);
+
+	/* PCMCIA is on a 36 bit physical address.
+	   We need to map it into a 32 bit addresses */
+
+#if 0
+	/* We dont need theese unless we run whole pcmcia package */
+	write_one_tlb(20,                 /* index */
+		      0x01ffe000,         /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
+		      0x3C000017,         /* Lo0 */
+		      0x3C200017);        /* Lo1 */
+
+	write_one_tlb(21,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
+		      0x3D000017,           /* Lo0 */
+		      0x3D200017);          /* Lo1 */
+#endif	/* 0 */
+	write_one_tlb(22,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
+		      0x3E000017,           /* Lo0 */
+		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */
+
+	return 0;
+}
diff --git a/u-boot/board/pb1x00/u-boot.lds b/u-boot/board/pb1x00/u-boot.lds
new file mode 100644
index 0000000..358cc54
--- /dev/null
+++ b/u-boot/board/pb1x00/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/pcippc2/Makefile b/u-boot/board/pcippc2/Makefile
new file mode 100644
index 0000000..6f0a928
--- /dev/null
+++ b/u-boot/board/pcippc2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o cpc710_pci.o flash.o sconsole.o \
+	  fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
+
+SOBJS	=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pcippc2/cpc710.h b/u-boot/board/pcippc2/cpc710.h
new file mode 100644
index 0000000..8167270
--- /dev/null
+++ b/u-boot/board/pcippc2/cpc710.h
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPC710_H_
+#define _CPC710_H_
+
+/* Revision */
+#define CPC710_TYPE_100	0x80
+#define CPC710_TYPE_100P	0x90
+
+/* System control area */
+#define HW_PHYS_SCA		0xff000000
+
+#define HW_SCA_CPC0		0x000000
+#define HW_SCA_SDRAM0		0x000000
+#define HW_SCA_DMA0		0x1C0000
+
+#define HW_PHYS_CPC0		(HW_PHYS_SCA + HW_SCA_CPC0)
+#define HW_PHYS_SDRAM0		(HW_PHYS_SCA + HW_SCA_SDRAM0)
+
+#define HW_CPC0_PCICNFR		0x000c
+#define HW_CPC0_RSTR		0x0010
+#define HW_CPC0_SPOR		0x00e8
+#define HW_CPC0_UCTL		0x1000
+#define HW_CPC0_SIOC0		0x1020
+#define HW_CPC0_ABCNTL		0x1030
+#define HW_CPC0_SESR		0x1060
+#define HW_CPC0_SEAR		0x1070
+#define HW_CPC0_PGCHP		0x1100
+#define HW_CPC0_RGBAN0		0x1110
+#define HW_CPC0_RGBAN1		0x1120
+
+#define HW_CPC0_GPDIR		0x1130
+#define HW_CPC0_GPIN		0x1140
+#define HW_CPC0_GPOUT		0x1150
+
+#define HW_CPC0_ATAS		0x1160
+
+#define HW_CPC0_PCIBAR		0x200018
+#define HW_CPC0_PCIENB		0x201000
+
+#define HW_SDRAM0_MCCR		0x1200
+#define HW_SDRAM0_MESR		0x1220
+#define HW_SDRAM0_MEAR		0x1230
+
+#define HW_SDRAM0_MCER0		0x1300
+#define HW_SDRAM0_MCER1		0x1310
+#define HW_SDRAM0_MCER2		0x1320
+#define HW_SDRAM0_MCER3		0x1330
+#define HW_SDRAM0_MCER4		0x1340
+#define HW_SDRAM0_MCER5		0x1350
+#define HW_SDRAM0_MCER6		0x1360
+#define HW_SDRAM0_MCER7		0x1370
+
+#define HW_BRIDGE_PCIDG		0xf6120
+#define HW_BRIDGE_INTACK	0xf7700
+#define HW_BRIDGE_PIBAR		0xf7800
+#define HW_BRIDGE_PMBAR		0xf7810
+#define HW_BRIDGE_CRR		0xf7ef0
+#define HW_BRIDGE_PR		0xf7f20
+#define HW_BRIDGE_ACR		0xf7f30
+#define HW_BRIDGE_MSIZE		0xf7f40
+#define HW_BRIDGE_IOSIZE	0xf7f60
+#define HW_BRIDGE_SMBAR		0xf7f80
+#define HW_BRIDGE_SIBAR		0xf7fc0
+#define HW_BRIDGE_CFGADDR	0xf8000
+#define HW_BRIDGE_CFGDATA	0xf8010
+#define HW_BRIDGE_PSSIZE	0xf8100
+#define HW_BRIDGE_BARPS		0xf8120
+#define HW_BRIDGE_PSBAR		0xf8140
+
+/* Configuration space registers */
+#define CPC710_BUS_NUMBER	0x40
+#define CPC710_SUB_BUS_NUMBER	0x41
+
+#endif
diff --git a/u-boot/board/pcippc2/cpc710_init_ram.c b/u-boot/board/pcippc2/cpc710_init_ram.c
new file mode 100644
index 0000000..8945351
--- /dev/null
+++ b/u-boot/board/pcippc2/cpc710_init_ram.c
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "pcippc2.h"
+#include "i2c.h"
+
+typedef struct cpc710_mem_org_s {
+	u8 rows;
+	u8 cols;
+	u8 banks2;
+	u8 org;
+} cpc710_mem_org_t;
+
+static int cpc710_compute_mcer (u32 * mcer,
+				unsigned long *size, unsigned int sdram);
+static int cpc710_eeprom_checksum (unsigned int sdram);
+static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset);
+
+static u32 cpc710_mcer_mem[] = {
+	0x000003f3,		/* 18 lines,    4 Mb */
+	0x000003e3,		/* 19 lines,    8 Mb */
+	0x000003c3,		/* 20 lines,   16 Mb */
+	0x00000383,		/* 21 lines,   32 Mb */
+	0x00000303,		/* 22 lines,   64 Mb */
+	0x00000203,		/* 23 lines,  128 Mb */
+	0x00000003,		/* 24 lines,  256 Mb */
+	0x00000002,		/* 25 lines,  512 Mb */
+	0x00000001		/* 26 lines, 1024 Mb */
+};
+static cpc710_mem_org_t cpc710_mem_org[] = {
+	{0x0c, 0x09, 0x02, 0x00},	/* 0000: 12/ 9/2 */
+	{0x0d, 0x09, 0x02, 0x00},	/* 0000: 13/ 9/2 */
+	{0x0d, 0x0a, 0x02, 0x00},	/* 0000: 13/10/2 */
+	{0x0d, 0x0b, 0x02, 0x00},	/* 0000: 13/11/2 */
+	{0x0d, 0x0c, 0x02, 0x00},	/* 0000: 13/12/2 */
+	{0x0e, 0x0c, 0x02, 0x00},	/* 0000: 14/12/2 */
+	{0x0b, 0x08, 0x02, 0x01},	/* 0001: 11/ 8/2 */
+	{0x0b, 0x09, 0x01, 0x02},	/* 0010: 11/ 9/1 */
+	{0x0b, 0x0a, 0x01, 0x03},	/* 0011: 11/10/1 */
+	{0x0c, 0x08, 0x02, 0x04},	/* 0100: 12/ 8/2 */
+	{0x0c, 0x0a, 0x02, 0x05},	/* 0101: 12/10/2 */
+	{0x0d, 0x08, 0x01, 0x06},	/* 0110: 13/ 8/1 */
+	{0x0d, 0x08, 0x02, 0x07},	/* 0111: 13/ 8/2 */
+	{0x0d, 0x09, 0x01, 0x08},	/* 1000: 13/ 9/1 */
+	{0x0d, 0x0a, 0x01, 0x09},	/* 1001: 13/10/1 */
+	{0x0b, 0x08, 0x01, 0x0a},	/* 1010: 11/ 8/1 */
+	{0x0c, 0x08, 0x01, 0x0b},	/* 1011: 12/ 8/1 */
+	{0x0c, 0x09, 0x01, 0x0c},	/* 1100: 12/ 9/1 */
+	{0x0e, 0x09, 0x02, 0x0d},	/* 1101: 14/ 9/2 */
+	{0x0e, 0x0a, 0x02, 0x0e},	/* 1110: 14/10/2 */
+	{0x0e, 0x0b, 0x02, 0x0f}	/* 1111: 14/11/2 */
+};
+
+unsigned long cpc710_ram_init (void)
+{
+	unsigned long memsize = 0;
+	unsigned long bank_size;
+	u32 mcer;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* Clear memory banks
+	 */
+	out32 (REG (SDRAM0, MCER0), 0);
+	out32 (REG (SDRAM0, MCER1), 0);
+	out32 (REG (SDRAM0, MCER2), 0);
+	out32 (REG (SDRAM0, MCER3), 0);
+	out32 (REG (SDRAM0, MCER4), 0);
+	out32 (REG (SDRAM0, MCER5), 0);
+	out32 (REG (SDRAM0, MCER6), 0);
+	out32 (REG (SDRAM0, MCER7), 0);
+	iobarrier_rw ();
+
+	/* Disable memory
+	 */
+	out32 (REG (SDRAM0, MCCR), 0x13b06000);
+	iobarrier_rw ();
+#endif
+
+	/* Only the first memory bank is initialised now
+	 */
+	if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
+		puts ("Unsupported SDRAM type !\n");
+		hang ();
+	}
+	memsize += bank_size;
+#ifndef CONFIG_SYS_RAMBOOT
+	/* Enable bank, zero start
+	 */
+	out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
+	iobarrier_rw ();
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* Enable memory
+	 */
+	out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
+
+	/* Wait until initialisation finished
+	 */
+	while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
+		iobarrier_rw ();
+	}
+
+	/* Clear Memory Error Status and Address registers
+	 */
+	out32 (REG (SDRAM0, MESR), 0);
+	out32 (REG (SDRAM0, MEAR), 0);
+	iobarrier_rw ();
+
+	/* ECC is not configured now
+	 */
+#endif
+
+	/* Memory size counter
+	 */
+	out32 (REG (CPC0, RGBAN1), memsize);
+
+	return memsize;
+}
+
+static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram)
+{
+	u8 rows;
+	u8 cols;
+	u8 banks2;
+	unsigned int lines;
+	u32 mc = 0;
+	unsigned int i;
+	cpc710_mem_org_t *org = 0;
+
+	if (!i2c_reset ()) {
+		puts ("Can't reset I2C!\n");
+		hang ();
+	}
+
+	if (!cpc710_eeprom_checksum (sdram)) {
+		puts ("Invalid EEPROM checksum !\n");
+		hang ();
+	}
+
+	rows = cpc710_eeprom_read (sdram, 3);
+	cols = cpc710_eeprom_read (sdram, 4);
+	/* Can be 2 or 4 banks; divide by 2
+	 */
+	banks2 = cpc710_eeprom_read (sdram, 17) / 2;
+
+	lines = rows + cols + banks2;
+
+	if (lines < 18 || lines > 26) {
+		/* Unsupported configuration
+		 */
+		return 0;
+	}
+
+	mc |= cpc710_mcer_mem[lines - 18] << 6;
+
+	for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t);
+	     i++) {
+		cpc710_mem_org_t *corg = cpc710_mem_org + i;
+
+		if (corg->rows == rows && corg->cols == cols
+		    && corg->banks2 == banks2) {
+			org = corg;
+
+			break;
+		}
+	}
+
+	if (!org) {
+		/* Unsupported configuration
+		 */
+		return 0;
+	}
+
+	mc |= (u32) org->org << 2;
+
+	/* Supported configuration
+	 */
+	*mcer = mc;
+	*size = 1l << (lines + 4);
+
+	return 1;
+}
+
+static int cpc710_eeprom_checksum (unsigned int sdram)
+{
+	u8 sum = 0;
+	unsigned int i;
+
+	for (i = 0; i < 63; i++) {
+		sum += cpc710_eeprom_read (sdram, i);
+	}
+
+	return sum == cpc710_eeprom_read (sdram, 63);
+}
+
+static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset)
+{
+	u8 dev = (sdram << 1) | 0xa0;
+	u8 data;
+
+	if (!i2c_read_byte (&data, dev, offset)) {
+		puts ("I2C error !\n");
+		hang ();
+	}
+
+	return data;
+}
diff --git a/u-boot/board/pcippc2/cpc710_pci.c b/u-boot/board/pcippc2/cpc710_pci.c
new file mode 100644
index 0000000..ccd18e1
--- /dev/null
+++ b/u-boot/board/pcippc2/cpc710_pci.c
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "hardware.h"
+#include "pcippc2.h"
+
+struct pci_controller local_hose, cpci_hose;
+
+static u32	cpc710_mapped_ram;
+
+  /* Enable PCI retry timeouts
+   */
+void cpc710_pci_enable_timeout (void)
+{
+  out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), 0x32000000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
+  iobarrier_rw();
+}
+
+void cpc710_pci_init (void)
+{
+  u32			sdram_size = pcippc2_sdram_size();
+
+  cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ?
+		      sdram_size : PCI_MEMORY_MAXSIZE;
+
+    /* Select the local PCI
+     */
+  out32(REG(CPC0, PCICNFR), 0x80000002);
+  iobarrier_rw();
+
+  out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS);
+  iobarrier_rw();
+
+    /* Enable PCI bridge address decoding
+     */
+  out32(REG(CPC0, PCIENB), 0x80000000);
+  iobarrier_rw();
+
+    /* Select the CPCI bridge
+     */
+  out32(REG(CPC0, PCICNFR), 0x80000003);
+  iobarrier_rw();
+
+  out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS);
+  iobarrier_rw();
+
+    /* Enable PCI bridge address decoding
+     */
+  out32(REG(CPC0, PCIENB), 0x80000000);
+  iobarrier_rw();
+
+    /* Disable configuration accesses
+     */
+  out32(REG(CPC0, PCICNFR), 0x80000000);
+  iobarrier_rw();
+
+    /* Initialise the local PCI
+     */
+  out32(BRIDGE(LOCAL, CRR), 0x7c000000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PCIDG), 0x40000000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS);
+  out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS);
+  out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS);
+  out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS);
+  out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PR), 0x00ffe000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, ACR), 0xfe000000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24);
+  out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24);
+  out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
+  iobarrier_rw();
+
+    /* Initialise the CPCI bridge
+     */
+  out32(BRIDGE(CPCI, CRR), 0x7c000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PCIDG), 0xC0000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS);
+  out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS);
+  out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS);
+  out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS);
+  out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PR), 0x80ffe000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, ACR), 0xdf000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24);
+  out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24);
+  out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
+  iobarrier_rw();
+
+    /* Local PCI
+     */
+
+  out32(BRIDGE(LOCAL, CFGADDR), 0x04000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), 0x56010000);
+  iobarrier_rw();
+
+  out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
+  iobarrier_rw();
+
+    /* Set bus and subbus numbers
+     */
+  out32(BRIDGE(LOCAL, CFGADDR), 0x40000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
+  iobarrier_rw();
+
+  out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
+  iobarrier_rw();
+    /* PCI retry timeouts will be enabled later
+     */
+  out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
+  iobarrier_rw();
+
+    /* CPCI
+     */
+
+    /* Set bus and subbus numbers
+     */
+  out32(BRIDGE(CPCI, CFGADDR), 0x40000080);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x01010000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x04000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x56010000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x0c000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
+  iobarrier_rw();
+
+    /* Write to the PSBAR */
+  out32(BRIDGE(CPCI, CFGADDR), 0x10000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS));
+  iobarrier_rw();
+
+    /* Set bus and subbus numbers
+     */
+  out32(BRIDGE(CPCI, CFGADDR), 0x40000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
+    /* PCI retry timeouts will be enabled later
+     */
+  out32(BRIDGE(CPCI, CFGDATA), 0x00000000);
+  iobarrier_rw();
+
+    /* Remove reset on the PCI buses
+     */
+  out32(BRIDGE(LOCAL, CRR), 0xfc000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CRR), 0xfc000000);
+  iobarrier_rw();
+
+  local_hose.first_busno = 0;
+  local_hose.last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(local_hose.regions + 0,
+		 PCI_MEMORY_BUS,
+		 PCI_MEMORY_PHYS,
+		 PCI_MEMORY_MAXSIZE,
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+  /* PCI memory space */
+  pci_set_region(local_hose.regions + 1,
+		 BRIDGE_LOCAL_MEM_BUS,
+		 BRIDGE_LOCAL_MEM_PHYS,
+		 BRIDGE_LOCAL_MEM_SIZE,
+		 PCI_REGION_MEM);
+
+  /* PCI I/O space */
+  pci_set_region(local_hose.regions + 2,
+		 BRIDGE_LOCAL_IO_BUS,
+		 BRIDGE_LOCAL_IO_PHYS,
+		 BRIDGE_LOCAL_IO_SIZE,
+		 PCI_REGION_IO);
+
+  local_hose.region_count = 3;
+
+  pci_setup_indirect(&local_hose,
+		     BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR,
+		     BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA);
+
+  pci_register_hose(&local_hose);
+
+  /* Initialize PCI32 bus registers */
+  pci_hose_write_config_byte(&local_hose,
+			  PCI_BDF(local_hose.first_busno,0,0),
+			  CPC710_BUS_NUMBER,
+			  local_hose.first_busno);
+  pci_hose_write_config_byte(&local_hose,
+			  PCI_BDF(local_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  local_hose.last_busno);
+
+  local_hose.last_busno = pci_hose_scan(&local_hose);
+
+  /* Write out correct max subordinate bus number for local hose */
+  pci_hose_write_config_byte(&local_hose,
+			  PCI_BDF(local_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  local_hose.last_busno);
+
+  cpci_hose.first_busno = local_hose.last_busno + 1;
+  cpci_hose.last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(cpci_hose.regions + 0,
+		 PCI_MEMORY_BUS,
+		 PCI_MEMORY_PHYS,
+		 PCI_MEMORY_MAXSIZE,
+		 PCI_REGION_SYS_MEMORY);
+
+  /* PCI memory space */
+  pci_set_region(cpci_hose.regions + 1,
+		 BRIDGE_CPCI_MEM_BUS,
+		 BRIDGE_CPCI_MEM_PHYS,
+		 BRIDGE_CPCI_MEM_SIZE,
+		 PCI_REGION_MEM);
+
+  /* PCI I/O space */
+  pci_set_region(cpci_hose.regions + 2,
+		 BRIDGE_CPCI_IO_BUS,
+		 BRIDGE_CPCI_IO_PHYS,
+		 BRIDGE_CPCI_IO_SIZE,
+		 PCI_REGION_IO);
+
+  cpci_hose.region_count = 3;
+
+  pci_setup_indirect(&cpci_hose,
+		     BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR,
+		     BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA);
+
+  pci_register_hose(&cpci_hose);
+
+  /* Initialize PCI64 bus registers */
+  pci_hose_write_config_byte(&cpci_hose,
+			  PCI_BDF(cpci_hose.first_busno,0,0),
+			  CPC710_BUS_NUMBER,
+			  cpci_hose.first_busno);
+  pci_hose_write_config_byte(&cpci_hose,
+			  PCI_BDF(cpci_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  cpci_hose.last_busno);
+
+  cpci_hose.last_busno = pci_hose_scan(&cpci_hose);
+
+  /* Write out correct max subordinate bus number for cpci hose */
+  pci_hose_write_config_byte(&cpci_hose,
+			  PCI_BDF(cpci_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  cpci_hose.last_busno);
+}
diff --git a/u-boot/board/pcippc2/cpc710_pci.h b/u-boot/board/pcippc2/cpc710_pci.h
new file mode 100644
index 0000000..24d0db6
--- /dev/null
+++ b/u-boot/board/pcippc2/cpc710_pci.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPC710_PCI_H_
+#define _CPC710_PCI_H_
+
+#define PCI_MEMORY_PHYS		0x00000000
+#define PCI_MEMORY_BUS		0x80000000
+#define PCI_MEMORY_MAXSIZE      0x20000000
+
+#define BRIDGE_CPCI_PHYS	0xff500000
+#define BRIDGE_CPCI_MEM_SIZE	0x08000000
+#define BRIDGE_CPCI_MEM_PHYS    0xf0000000
+#define BRIDGE_CPCI_MEM_BUS     0x00000000
+#define BRIDGE_CPCI_IO_SIZE	0x02000000
+#define BRIDGE_CPCI_IO_PHYS     0xfc000000
+#define BRIDGE_CPCI_IO_BUS      0x00000000
+
+#define BRIDGE_LOCAL_PHYS	0xff400000
+#define BRIDGE_LOCAL_MEM_SIZE	0x04000000
+#define BRIDGE_LOCAL_MEM_PHYS   0xf8000000
+#define BRIDGE_LOCAL_MEM_BUS    0x40000000
+#define BRIDGE_LOCAL_IO_SIZE	0x01000000
+#define BRIDGE_LOCAL_IO_PHYS    0xfe000000
+#define BRIDGE_LOCAL_IO_BUS     0x04000000
+
+#define BRIDGE(r, x)		(BRIDGE_##r##_PHYS + HW_BRIDGE_##x)
+
+#define PCI_LATENCY_TIMER_VAL	0xff
+
+#endif
diff --git a/u-boot/board/pcippc2/flash.c b/u-boot/board/pcippc2/flash.c
new file mode 100644
index 0000000..ec604e0
--- /dev/null
+++ b/u-boot/board/pcippc2/flash.c
@@ -0,0 +1,573 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static ulong flash_get_size (ulong addr, flash_info_t *info);
+static int flash_get_offsets (ulong base, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_reset (ulong addr);
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long flash_size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = 0;
+		flash_info[i].size = 0;
+	}
+
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
+
+	flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
+
+	DEBUGF("## Flash bank size: %08lx\n", flash_size);
+
+	if (flash_size) {
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			      &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			      &flash_info[0]);
+#endif
+
+	} else {
+		puts ("Warning: the BOOT Flash is not initialised !");
+	}
+
+	return flash_size;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (ulong addr, flash_info_t *info)
+{
+	short i;
+	uchar value;
+
+	/* Write auto select command: read Manufacturer ID */
+	out8(addr + 0x0555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x02AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x0555, 0x90);
+	iobarrier_rw();
+
+	value = in8(addr);
+	iobarrier_rw();
+
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
+
+	switch (value | (value << 16)) {
+		case AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+
+		case STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			flash_reset (addr);
+			return 0;
+	}
+
+	value = in8(addr + 1);			/* device ID		*/
+	iobarrier_rw();
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
+
+	switch ((ulong)value) {
+		case AMD_ID_F040B:
+			DEBUGF("Am29F040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		case AMD_ID_LV040B:
+			DEBUGF("Am29LV040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		case AMD_ID_LV400T:
+			DEBUGF("Am29LV400T\n");
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;			/* => 1 MB		*/
+
+		case AMD_ID_LV400B:
+			DEBUGF("Am29LV400B\n");
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;			/* => 1 MB		*/
+
+		case AMD_ID_LV800T:
+			DEBUGF("Am29LV800T\n");
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;			/* => 2 MB		*/
+
+		case AMD_ID_LV800B:
+			DEBUGF("Am29LV400B\n");
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;			/* => 2 MB		*/
+
+		case AMD_ID_LV160T:
+			DEBUGF("Am29LV160T\n");
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;			/* => 4 MB		*/
+
+		case AMD_ID_LV160B:
+			DEBUGF("Am29LV160B\n");
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;			/* => 4 MB		*/
+
+		case AMD_ID_LV320T:
+			DEBUGF("Am29LV320T\n");
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;			/* => 8 MB		*/
+
+#if 0
+		/* Has the same ID as AMD_ID_LV320T, to be fixed */
+		case AMD_ID_LV320B:
+			DEBUGF("Am29LV320B\n");
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;			/* => 8 MB		*/
+#endif
+
+		case AMD_ID_LV033C:
+			DEBUGF("Am29LV033C\n");
+			info->flash_id += FLASH_AM033C;
+			info->sector_count = 64;
+			info->size = 0x01000000;
+			break;			/* => 16Mb		*/
+
+		case STM_ID_F040B:
+			DEBUGF("M29F040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			flash_reset (addr);
+			return (0);		/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	if (! flash_get_offsets (addr, info)) {
+		flash_reset (addr);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		value = in8(info->start[i] + 2);
+		iobarrier_rw();
+		info->protect[i] = (value & 1) != 0;
+	}
+
+	/*
+	 * Reset bank to read mode
+	 */
+	flash_reset (addr);
+
+	return (info->size);
+}
+
+static int flash_get_offsets (ulong base, flash_info_t *info)
+{
+	unsigned int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			/* set sector offsets for uniform sector type	*/
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base + i * info->size /
+				                            info->sector_count;
+			}
+			break;
+		default:
+			return 0;
+	}
+
+	return 1;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile ulong addr = info->start[0];
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if (s_first < 0 || s_first > s_last) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x80);
+	iobarrier_rw();
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = info->start[sect];
+			out8(addr, 0x30);
+			iobarrier_rw();
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = info->start[l_sect];
+
+	DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
+
+	while ((in8(addr) & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			flash_reset (info->start[0]);
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+		iobarrier_rw();
+	}
+
+DONE:
+	/* reset to read mode */
+	flash_reset (info->start[0]);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile ulong addr = info->start[0];
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((in32(dest) & data) != data) {
+		return (2);
+	}
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		int flag = disable_interrupts();
+
+		out8(addr + 0x555, 0xAA);
+		iobarrier_rw();
+		out8(addr + 0x2AA, 0x55);
+		iobarrier_rw();
+		out8(addr + 0x555, 0xA0);
+		iobarrier_rw();
+		out8(dest+i, data_ch[i]);
+		iobarrier_rw();
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				flash_reset (addr);
+				return (1);
+			}
+			iobarrier_rw();
+		}
+	}
+
+	flash_reset (addr);
+	return (0);
+}
+
+/*
+ * Reset bank to read mode
+ */
+static void flash_reset (ulong addr)
+{
+	out8(addr, 0xF0);	/* reset bank */
+	iobarrier_rw();
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_STM:	printf ("SGS THOMSON ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size % 0x100000 == 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size / 0x100000, info->sector_count);
+	} else if (info->size % 0x400 == 0) {
+		printf ("  Size: %ld KB in %d Sectors\n",
+		        info->size / 0x400, info->sector_count);
+	} else {
+		printf ("  Size: %ld B in %d Sectors\n",
+		        info->size, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
diff --git a/u-boot/board/pcippc2/fpga_serial.c b/u-boot/board/pcippc2/fpga_serial.c
new file mode 100644
index 0000000..5f89d9b
--- /dev/null
+++ b/u-boot/board/pcippc2/fpga_serial.c
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "fpga_serial.h"
+#include "hardware.h"
+#include "pcippc2.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+  /* 8 data, 1 stop, no parity
+   */
+#define LCRVAL		0x03
+  /* RTS/DTR
+   */
+#define MCRVAL		0x03
+  /* Clear & enable FIFOs
+   */
+#define FCRVAL		0x07
+
+static void fpga_serial_wait (void);
+static void fpga_serial_print (char c);
+
+void fpga_serial_init (int baudrate)
+{
+	int clock_divisor = 115200 / baudrate;
+
+	out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
+	iobarrier_rw ();
+
+	fpga_serial_wait ();
+
+	out8 (UART (IER), 0);
+	out8 (UART (LCR), LCRVAL | 0x80);
+	iobarrier_rw ();
+	out8 (UART (DLL), clock_divisor & 0xff);
+	out8 (UART (DLM), clock_divisor >> 8);
+	iobarrier_rw ();
+	out8 (UART (LCR), LCRVAL);
+	iobarrier_rw ();
+	out8 (UART (MCR), MCRVAL);
+	out8 (UART (FCR), FCRVAL);
+	iobarrier_rw ();
+}
+
+void fpga_serial_putc (char c)
+{
+	if (c) {
+		fpga_serial_print (c);
+	}
+}
+
+void fpga_serial_puts (const char *s)
+{
+	while (*s) {
+		fpga_serial_print (*s++);
+	}
+}
+
+int fpga_serial_getc (void)
+{
+	while ((in8 (UART (LSR)) & 0x01) == 0);
+
+	return in8 (UART (RBR));
+}
+
+int fpga_serial_tstc (void)
+{
+	return (in8 (UART (LSR)) & 0x01) != 0;
+}
+
+void fpga_serial_setbrg (void)
+{
+	int clock_divisor = 115200 / gd->baudrate;
+
+	fpga_serial_wait ();
+
+	out8 (UART (LCR), LCRVAL | 0x80);
+	iobarrier_rw ();
+	out8 (UART (DLL), clock_divisor & 0xff);
+	out8 (UART (DLM), clock_divisor >> 8);
+	iobarrier_rw ();
+	out8 (UART (LCR), LCRVAL);
+	iobarrier_rw ();
+}
+
+static void fpga_serial_wait (void)
+{
+	while ((in8 (UART (LSR)) & 0x40) == 0);
+}
+
+static void fpga_serial_print (char c)
+{
+	if (c == '\n') {
+		while ((in8 (UART (LSR)) & 0x20) == 0);
+
+		out8 (UART (THR), '\r');
+		iobarrier_rw ();
+	}
+
+	while ((in8 (UART (LSR)) & 0x20) == 0);
+
+	out8 (UART (THR), c);
+	iobarrier_rw ();
+
+	if (c == '\n') {
+		fpga_serial_wait ();
+	}
+}
diff --git a/u-boot/board/pcippc2/fpga_serial.h b/u-boot/board/pcippc2/fpga_serial.h
new file mode 100644
index 0000000..5275014
--- /dev/null
+++ b/u-boot/board/pcippc2/fpga_serial.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FPGA_SERIAL_H_
+#define _FPGA_SERIAL_H_
+
+extern void	fpga_serial_init	(int);
+extern void	fpga_serial_putc	(char);
+extern void	fpga_serial_puts	(const char *);
+extern int	fpga_serial_getc	(void);
+extern int	fpga_serial_tstc	(void);
+extern void	fpga_serial_setbrg	(void);
+
+#endif
diff --git a/u-boot/board/pcippc2/hardware.h b/u-boot/board/pcippc2/hardware.h
new file mode 100644
index 0000000..489929d
--- /dev/null
+++ b/u-boot/board/pcippc2/hardware.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _HARDWARE_H_
+#define _HARDWARE_H_
+
+#include "cpc710.h"
+#include "cpc710_pci.h"
+#include "pcippc2_fpga.h"
+#include "ns16550.h"
+
+#define REG(r, x)	(HW_PHYS_##r + HW_##r##_##x)
+
+  /* Address map:
+   *
+   * 0x00000000-0x20000000	SDRAM
+   * 0x40000000-0x00008000	Init RAM in the CPU DCache
+   * 0xf0000000-0xf8000000	CPCI MEM
+   * 0xf8000000-0xfc000000	Local PCI MEM
+   * 0xfc000000-0xfe000000	CPCI I/O
+   * 0xfe000000-0xff000000	Local PCI I/O
+   * 0xff000000-0xff201000	System configuration space
+   * 0xff400000-0xff500000	Local PCI bridge space
+   * 0xff500000-0xff600000	CPCI bridge space
+   * 0xfff00000-0xfff80000	Boot Flash
+   */
+
+#endif
diff --git a/u-boot/board/pcippc2/i2c.c b/u-boot/board/pcippc2/i2c.c
new file mode 100644
index 0000000..ab52562
--- /dev/null
+++ b/u-boot/board/pcippc2/i2c.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "hardware.h"
+#include "i2c.h"
+
+static void		i2c_start	(void);
+static void		i2c_stop	(void);
+static int		i2c_write	(u8		data);
+static void		i2c_read	(u8 *		data);
+
+static inline void	i2c_port_start  (void);
+static inline void	i2c_clock	(unsigned int	val);
+static inline void	i2c_data	(unsigned int	val);
+static inline unsigned int
+			i2c_in		(void);
+static inline void	i2c_write_bit	(unsigned int	val);
+static inline unsigned int
+			i2c_read_bit	(void);
+
+static inline void	i2c_udelay	(unsigned int	time);
+
+int i2c_read_byte (
+  u8 *			data,
+  u8			dev,
+  u8			offset)
+{
+  int			err = 0;
+
+  i2c_start();
+
+  err = ! i2c_write(dev);
+
+  if (! err)
+  {
+    err = ! i2c_write(offset);
+  }
+
+  if (! err)
+  {
+    i2c_start();
+  }
+
+  if (! err)
+  {
+    err = ! i2c_write(dev | 0x01);
+  }
+
+  if (! err)
+  {
+    i2c_read(data);
+  }
+
+  i2c_stop();
+
+  return ! err;
+}
+
+static inline void i2c_udelay (
+  unsigned int		time)
+{
+  int			v;
+
+  asm volatile("mtdec %0" : : "r" (time * ((CONFIG_SYS_BUS_CLK / 4) / 1000000)));
+
+  do
+  {
+    asm volatile("isync; mfdec %0" : "=r" (v));
+  } while (v >= 0);
+}
+
+  /* Low-level hardware access
+   */
+
+#define BIT_GPDATA		0x80000000
+#define BIT_GPCLK		0x40000000
+
+static inline void i2c_port_start (void)
+{
+  out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~(BIT_GPCLK | BIT_GPDATA));
+  out32(REG(CPC0, GPOUT), in32(REG(CPC0, GPOUT)) & ~(BIT_GPCLK | BIT_GPDATA));
+  iobarrier_rw();
+
+  i2c_udelay(1);
+}
+
+static inline void i2c_clock (
+  unsigned int		val)
+{
+  if (val)
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPCLK);
+  }
+  else
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPCLK);
+  }
+
+  iobarrier_rw();
+
+  i2c_udelay(1);
+}
+
+static inline void i2c_data (
+  unsigned int		val)
+{
+  if (val)
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPDATA);
+  }
+  else
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPDATA);
+  }
+
+  iobarrier_rw();
+
+  i2c_udelay(1);
+}
+
+static inline unsigned int i2c_in (void)
+{
+  unsigned int		val = ((in32(REG(CPC0, GPIN)) & BIT_GPDATA) != 0)?1:0;
+
+  iobarrier_rw();
+
+  return val;
+}
+
+
+  /* Protocol implementation
+   */
+
+static inline void i2c_write_bit (
+  unsigned int		val)
+{
+  i2c_data(val);
+  i2c_udelay(10);
+  i2c_clock(1);
+  i2c_udelay(10);
+  i2c_clock(0);
+  i2c_udelay(10);
+}
+
+static inline unsigned int i2c_read_bit (void)
+{
+  unsigned int		val;
+
+  i2c_data(1);
+  i2c_udelay(10);
+
+  i2c_clock(1);
+  i2c_udelay(10);
+
+  val = i2c_in();
+
+  i2c_clock(0);
+  i2c_udelay(10);
+
+  return val;
+}
+
+unsigned int i2c_reset (void)
+{
+  unsigned int		val;
+  int i;
+
+  i2c_port_start();
+
+  i=0;
+  do {
+    i2c_udelay(10);
+    i2c_clock(0);
+    i2c_udelay(10);
+    i2c_clock(1);
+    i2c_udelay(10);
+    val = i2c_in();
+    i++;
+  }  while ((i<9)&&(val==0));
+  return (val);
+}
+
+
+static void i2c_start (void)
+{
+  i2c_data(1);
+  i2c_clock(1);
+  i2c_udelay(10);
+  i2c_data(0);
+  i2c_udelay(10);
+  i2c_clock(0);
+  i2c_udelay(10);
+}
+
+static void i2c_stop (void)
+{
+  i2c_data(0);
+  i2c_udelay(10);
+  i2c_clock(1);
+  i2c_udelay(10);
+  i2c_data(1);
+  i2c_udelay(10);
+}
+
+static int i2c_write (
+  u8			data)
+{
+  unsigned int		i;
+
+  for (i = 0; i < 8; i++)
+  {
+    i2c_write_bit(data >> 7);
+    data <<= 1;
+  }
+
+  return i2c_read_bit() == 0;
+}
+
+static void i2c_read (
+  u8 *			data)
+{
+  unsigned int		i;
+  u8			val = 0;
+
+  for (i = 0; i < 8; i++)
+  {
+    val <<= 1;
+    val |= i2c_read_bit();
+  }
+
+  *data = val;
+  i2c_write_bit(1); /* NoAck */
+}
diff --git a/u-boot/board/pcippc2/i2c.h b/u-boot/board/pcippc2/i2c.h
new file mode 100644
index 0000000..1224b42
--- /dev/null
+++ b/u-boot/board/pcippc2/i2c.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#include <common.h>
+
+extern int	i2c_read_byte	(u8 *		data,
+				 u8		dev,
+				 u8 offset);
+
+extern unsigned int i2c_reset (void);
+
+
+#endif
diff --git a/u-boot/board/pcippc2/ns16550.h b/u-boot/board/pcippc2/ns16550.h
new file mode 100644
index 0000000..7023f13
--- /dev/null
+++ b/u-boot/board/pcippc2/ns16550.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NS16550_H_
+#define _NS16550_H_
+
+#define NS16550_RBR	0x00
+#define NS16550_IER	0x01
+#define NS16550_FCR	0x02
+#define NS16550_LCR	0x03
+#define NS16550_MCR	0x04
+#define NS16550_LSR	0x05
+#define NS16550_MSR	0x06
+#define NS16550_SCR	0x07
+
+#define NS16550_THR	NS16550_RBR
+#define NS16550_IIR	NS16550_FCR
+#define NS16550_DLL	NS16550_RBR
+#define NS16550_DLM	NS16550_IER
+
+#endif
diff --git a/u-boot/board/pcippc2/pcippc2.c b/u-boot/board/pcippc2/pcippc2.c
new file mode 100644
index 0000000..4a91458
--- /dev/null
+++ b/u-boot/board/pcippc2/pcippc2.c
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <linux/mtd/doc2000.h>
+#include <watchdog.h>
+#include <pci.h>
+#include <netdev.h>
+
+#include "hardware.h"
+#include "pcippc2.h"
+#include "sconsole.h"
+#include "fpga_serial.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_WATCHDOG)
+
+static int pcippc2_wdt_init_done = 0;
+
+void pcippc2_wdt_init (void);
+
+#endif
+
+  /* Check board identity
+   */
+int checkboard (void)
+{
+#ifdef CONFIG_PCIPPC2
+	puts ("Board: Gespac PCIPPC-2\n");
+#else
+	puts ("Board: Gespac PCIPPC-6\n");
+#endif
+	return 0;
+}
+
+  /* RAM size is stored in CPC0_RGBAN1
+   */
+u32 pcippc2_sdram_size (void)
+{
+	return in32 (REG (CPC0, RGBAN1));
+}
+
+phys_size_t initdram (int board_type)
+{
+	return cpc710_ram_init ();
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	out32 (REG (CPC0, SPOR), 0);
+	iobarrier_rw ();
+	while (1);
+	/* notreached */
+	return (-1);
+}
+
+int board_early_init_f (void)
+{
+	out32 (REG (CPC0, RSTR), 0xC0000000);
+	iobarrier_rw ();
+
+	out32 (REG (CPC0, RSTR), 0xF0000000);
+	iobarrier_rw ();
+
+	out32 (REG (CPC0, UCTL), 0x00F80000);
+
+	out32 (REG (CPC0, SIOC0), 0x30000000);
+
+	out32 (REG (CPC0, ABCNTL), 0x00000000);
+
+	out32 (REG (CPC0, SESR), 0x00000000);
+	out32 (REG (CPC0, SEAR), 0x00000000);
+
+	/* Detect IBM Avignon CPC710 Revision */
+	if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
+		out32 (REG (CPC0, PGCHP), 0xA0000040);
+	else
+		out32 (REG (CPC0, PGCHP), 0x80800040);
+
+
+	out32 (REG (CPC0, ATAS), 0x709C2508);
+
+	iobarrier_rw ();
+
+	return 0;
+}
+
+void after_reloc (ulong dest_addr)
+{
+	/* Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *)gd, dest_addr);
+}
+
+int misc_init_r (void)
+{
+	pcippc2_fpga_init ();
+
+	pcippc2_cpci3264_init ();
+
+#if defined(CONFIG_WATCHDOG)
+	pcippc2_wdt_init ();
+#endif
+
+	fpga_serial_init (sconsole_get_baudrate ());
+
+	sconsole_putc   = fpga_serial_putc;
+	sconsole_puts   = fpga_serial_puts;
+	sconsole_getc   = fpga_serial_getc;
+	sconsole_tstc   = fpga_serial_tstc;
+	sconsole_setbrg = fpga_serial_setbrg;
+
+	sconsole_flush ();
+	return (0);
+}
+
+void pci_init_board (void)
+{
+	cpc710_pci_init ();
+
+	/* FPGA requires no retry timeouts to be enabled
+	 */
+	cpc710_pci_enable_timeout ();
+}
+
+#ifdef CONFIG_CMD_DOC
+void doc_init (void)
+{
+	doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
+}
+#endif
+
+void pcippc2_cpci3264_init (void)
+{
+  pci_dev_t		bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
+
+  if (bdf == -1)
+  {
+    puts("Unable to find FPGA !\n");
+    hang();
+  }
+
+	if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
+	/* 32-bits Compact PCI bus - LSB bit */
+	{
+		iobarrier_rw();
+		out32(BRIDGE(CPCI, PCIDG), 0x40000000);	/* 32-bits bridge, Pipeline */
+		iobarrier_rw();
+	}
+}
+
+#if defined(CONFIG_WATCHDOG)
+
+void pcippc2_wdt_init (void)
+{
+	out16r (FPGA (WDT, PROG), 0xffff);
+	out8 (FPGA (WDT, CTRL), 0x1);
+
+	pcippc2_wdt_init_done = 1;
+}
+
+void pcippc2_wdt_done (void)
+{
+	out8 (FPGA (WDT, CTRL), 0x0);
+
+	pcippc2_wdt_init_done = 0;
+}
+
+void pcippc2_wdt_reset (void)
+{
+	if (pcippc2_wdt_init_done == 1)
+		out8 (FPGA (WDT, REFRESH), 0x56);
+}
+
+void watchdog_reset (void)
+{
+	int re_enable = disable_interrupts ();
+
+	pcippc2_wdt_reset ();
+	if (re_enable)
+		enable_interrupts ();
+}
+
+#if defined(CONFIG_CMD_BSP)
+int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	switch (argc) {
+	case 1:
+		printf ("Watchdog timer status is %s\n",
+			pcippc2_wdt_init_done == 1 ? "on" : "off");
+
+		return 0;
+	case 2:
+		if (!strcmp(argv[1],"on")) {
+			pcippc2_wdt_init();
+			printf("Watchdog timer now is on\n");
+
+			return 0;
+
+		} else if (!strcmp(argv[1],"off")) {
+			pcippc2_wdt_done();
+			printf("Watchdog timer now is off\n");
+
+			return 0;
+
+		} else
+			break;
+	default:
+		break;
+	}
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	wd,	2,	1,	do_wd,
+	"check and set watchdog",
+	"on   - switch watchDog on\n"
+	"wd off  - switch watchdog off\n"
+	"wd      - print current status"
+);
+
+#endif
+#endif	/* CONFIG_WATCHDOG */
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/pcippc2/pcippc2.h b/u-boot/board/pcippc2/pcippc2.h
new file mode 100644
index 0000000..a1366ef
--- /dev/null
+++ b/u-boot/board/pcippc2/pcippc2.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCIPPC2_H_
+#define _PCIPPC2_H_
+
+#include <config.h>
+#include <common.h>
+
+#include "hardware.h"
+
+#define FPGA(r, p)	(pcippc2_fpga0_phys + HW_FPGA0_##r##_##p)
+#define UART(r)		(pcippc2_fpga0_phys + HW_FPGA0_UART1 + NS16550_##r * 4)
+#define RTC(r)		(pcippc2_fpga1_phys + HW_FPGA1_RTC + r)
+
+extern u32		pcippc2_fpga0_phys;
+extern u32		pcippc2_fpga1_phys;
+
+extern u32	pcippc2_sdram_size		(void);
+
+extern void	pcippc2_fpga_init		(void);
+
+extern void	pcippc2_cpci3264_init	(void);
+
+extern void	cpc710_pci_init			(void);
+extern void	cpc710_pci_enable_timeout	(void);
+
+extern unsigned long
+		cpc710_ram_init			(void);
+
+#endif
diff --git a/u-boot/board/pcippc2/pcippc2_fpga.c b/u-boot/board/pcippc2/pcippc2_fpga.c
new file mode 100644
index 0000000..7f6739d
--- /dev/null
+++ b/u-boot/board/pcippc2/pcippc2_fpga.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "pci.h"
+
+#include "hardware.h"
+#include "pcippc2.h"
+
+u32		pcippc2_fpga0_phys;
+u32		pcippc2_fpga1_phys;
+
+void pcippc2_fpga_init (void)
+{
+  pci_dev_t		bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
+  unsigned int		addr;
+  u16			cmd;
+
+  if (bdf == -1)
+  {
+    puts("Unable to find FPGA !\n");
+    hang();
+  }
+
+  pci_read_config_word(bdf, PCI_COMMAND, &cmd);
+  if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))
+  {
+    puts("FPGA is not configured !\n");
+    hang();
+  }
+
+  pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr);
+  if (addr & 0x1)
+  {
+      /* IO space
+       */
+    pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc);
+  }
+  else
+  {
+      /* Memory space
+       */
+    pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0);
+  }
+
+  pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+  if (addr & 0x1)
+  {
+      /* IO space
+       */
+    pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc);
+  }
+  else
+  {
+      /* Memory space
+       */
+    pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0);
+  }
+
+    /* Interrupts are not used
+     */
+  out32(FPGA(INT, INTR_MASK), 0xffffffff);
+  iobarrier_rw();
+}
diff --git a/u-boot/board/pcippc2/pcippc2_fpga.h b/u-boot/board/pcippc2/pcippc2_fpga.h
new file mode 100644
index 0000000..850c331
--- /dev/null
+++ b/u-boot/board/pcippc2/pcippc2_fpga.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCIPPC2_FPGA_H_
+#define _PCIPPC2_FPGA_H_
+
+#define FPGA_VENDOR_ID			0x1310
+#define FPGA_DEVICE_ID			0x000d
+
+#define HW_FPGA0_INT			0x0000
+#define HW_FPGA0_BOARD		0x0060
+#define HW_FPGA0_UART1			0x0080
+#define HW_FPGA0_UART2			0x0100
+#define HW_FPGA0_RTC			0x2000
+#define HW_FPGA0_DOC			0x4000
+#define HW_FPGA1_RTC			0x0000
+#define HW_FPGA1_DOC			0x4000
+
+#define HW_FPGA0_INT_INTR_MASK		0x30
+#define HW_FPGA0_INT_INTR_STATUS	0x34
+#define HW_FPGA0_INT_INTR_EOI		0x40
+#define HW_FPGA0_INT_SERIAL_CONFIG	0x5c
+
+#define HW_FPGA0_WDT_CTRL		0x44
+#define HW_FPGA0_WDT_PROG		0x48
+#define HW_FPGA0_WDT_VAL		0x4c
+#define HW_FPGA0_WDT_REFRESH		0x50
+
+#endif
diff --git a/u-boot/board/pcippc2/sconsole.c b/u-boot/board/pcippc2/sconsole.c
new file mode 100644
index 0000000..6ef38f4
--- /dev/null
+++ b/u-boot/board/pcippc2/sconsole.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+
+#include "sconsole.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void	(*sconsole_putc) (char) = 0;
+void	(*sconsole_puts) (const char *) = 0;
+int	(*sconsole_getc) (void) = 0;
+int	(*sconsole_tstc) (void) = 0;
+void	(*sconsole_setbrg) (void) = 0;
+
+int serial_init (void)
+{
+	sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+	sb->pos  = 0;
+	sb->size = 0;
+	sb->baud = gd->baudrate;
+	sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+
+	return (0);
+}
+
+void serial_putc (char c)
+{
+	if (sconsole_putc) {
+		(*sconsole_putc) (c);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		if (c) {
+			sb->data[sb->pos++] = c;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+void serial_puts (const char *s)
+{
+	if (sconsole_puts) {
+		(*sconsole_puts) (s);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		while (*s) {
+			sb->data[sb->pos++] = *s++;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+int serial_getc (void)
+{
+	if (sconsole_getc) {
+		return (*sconsole_getc) ();
+	} else {
+		return 0;
+	}
+}
+
+int serial_tstc (void)
+{
+	if (sconsole_tstc) {
+		return (*sconsole_tstc) ();
+	} else {
+		return 0;
+	}
+}
+
+void serial_setbrg (void)
+{
+	if (sconsole_setbrg) {
+		(*sconsole_setbrg) ();
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		sb->baud = gd->baudrate;
+	}
+}
+
+int sconsole_get_baudrate (void)
+{
+	sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+	return sb->baud;
+}
+
+void sconsole_flush (void)
+{
+	if (sconsole_putc) {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+		unsigned int end = sb->pos < sb->size
+				? sb->pos + sb->max_size - sb->size
+				: sb->pos - sb->size;
+
+		while (sb->size) {
+			(*sconsole_putc) (sb->data[end++]);
+			if (end == sb->max_size) {
+				end = 0;
+			}
+			sb->size--;
+		}
+	}
+}
diff --git a/u-boot/board/pcippc2/sconsole.h b/u-boot/board/pcippc2/sconsole.h
new file mode 100644
index 0000000..ff0ccab
--- /dev/null
+++ b/u-boot/board/pcippc2/sconsole.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCONSOLE_H_
+#define _SCONSOLE_H_
+
+#include <config.h>
+
+typedef struct sconsole_buffer_s {
+	unsigned long size;
+	unsigned long max_size;
+	unsigned long pos;
+	unsigned long baud;
+	char data[1];
+} sconsole_buffer_t;
+
+#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
+
+extern void	(* sconsole_putc)	(char);
+extern void	(* sconsole_puts)	(const char *);
+extern int	(* sconsole_getc)	(void);
+extern int	(* sconsole_tstc)	(void);
+extern void	(* sconsole_setbrg)	(void);
+
+extern void	sconsole_flush		(void);
+extern int	sconsole_get_baudrate	(void);
+
+#endif
diff --git a/u-boot/board/pcs440ep/Makefile b/u-boot/board/pcs440ep/Makefile
new file mode 100644
index 0000000..8708834
--- /dev/null
+++ b/u-boot/board/pcs440ep/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pcs440ep/config.mk b/u-boot/board/pcs440ep/config.mk
new file mode 100644
index 0000000..23631c5
--- /dev/null
+++ b/u-boot/board/pcs440ep/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PCS440EP board
+#
+
+# Check the U-Boot Image with a SHA1 checksum
+ALL += $(obj)u-boot.sha1
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/pcs440ep/flash.c b/u-boot/board/pcs440ep/flash.c
new file mode 100644
index 0000000..f90a221
--- /dev/null
+++ b/u-boot/board/pcs440ep/flash.c
@@ -0,0 +1,623 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifndef CONFIG_SYS_FLASH_READ0
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*
+ * Functions
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	return (size_b0 + size_b1);
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("ST Micro");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	case FLASH_MAN_MX:	printf ("MXIC "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_SST020:	printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+		break;
+	case STM_ID_M29W040B:	printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CONFIG_SYS_FLASH_READ0];
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID	*/
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;		/* => 0.5 MB	*/
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 0,5 MB */
+		break;
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
+		info->flash_id += FLASH_SST020;
+		info->sector_count = 64;
+		info->size = 0x00040000;
+		break;				/* => 256 kB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
+		info->flash_id += FLASH_SST040;
+		info->sector_count = 128;
+		info->size = 0x00080000;
+		break;				/* => 512 kB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00001000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+
+				/* re-enable interrupts if necessary */
+				if (flag) {
+					enable_interrupts();
+					flag = 0;
+				}
+
+				/* data polling for D7 */
+				start = get_timer (0);
+				while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+				       (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+						return (1);
+				}
+			} else {
+				if (sect == s_first) {
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				}
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			}
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i)
+			data = (data << 8) | *src++;
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *)cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/pcs440ep/init.S b/u-boot/board/pcs440ep/init.S
new file mode 100644
index 0000000..6bd8852
--- /dev/null
+++ b/u-boot/board/pcs440ep/init.S
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
+
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR detection
+	 * routine.
+	 */
+
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
+
+	/* PCI */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
+
+	/* USB 2.0 Device */
+	tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
+
+	tlbtab_end
diff --git a/u-boot/board/pcs440ep/pcs440ep.c b/u-boot/board/pcs440ep/pcs440ep.c
new file mode 100644
index 0000000..70d8fe2
--- /dev/null
+++ b/u-boot/board/pcs440ep/pcs440ep.c
@@ -0,0 +1,715 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <malloc.h>
+#include <command.h>
+#include <crc.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <status_led.h>
+#include <sha1.h>
+#include <asm/io.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+unsigned char	sha1_checksum[SHA1_SUM_LEN];
+
+/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
+unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+			      0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
+
+static void set_leds (int val)
+{
+	out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
+}
+
+#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
+
+void __led_init (led_id_t mask, int state)
+{
+	int	val = GET_LEDS;
+
+	if (state == STATUS_LED_ON)
+		val |= mask;
+	else
+		val &= ~mask;
+	set_leds (val);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	int	val = GET_LEDS;
+
+	if (state == STATUS_LED_ON)
+		val |= mask;
+	else if (state == STATUS_LED_OFF)
+		val &= ~mask;
+	set_leds (val);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	int	val = GET_LEDS;
+
+	val ^= mask;
+	set_leds (val);
+}
+
+static void status_led_blink (void)
+{
+	int	i;
+	int	val = GET_LEDS;
+
+	/* set all LED which are on, to state BLINKING */
+	for (i = 0; i < 4; i++) {
+		if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING);
+		else status_led_set (3 - i, STATUS_LED_OFF);
+		val = val >> 1;
+	}
+}
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress (int val)
+{
+	/* find all valid Codes for val in README */
+	if (val == -30) return;
+	if (val < 0) {
+		/* smthing goes wrong */
+		status_led_blink ();
+		return;
+	}
+	switch (val) {
+		case 1:
+			/* validating Image */
+			status_led_set (0, STATUS_LED_OFF);
+			status_led_set (1, STATUS_LED_ON);
+			status_led_set (2, STATUS_LED_ON);
+			break;
+		case 15:
+			/* booting */
+			status_led_set (0, STATUS_LED_ON);
+			status_led_set (1, STATUS_LED_ON);
+			status_led_set (2, STATUS_LED_ON);
+			break;
+#if 0
+		case 64:
+			/* starting Ethernet configuration */
+			status_led_set (0, STATUS_LED_OFF);
+			status_led_set (1, STATUS_LED_OFF);
+			status_led_set (2, STATUS_LED_ON);
+			break;
+#endif
+		case 80:
+			/* loading Image */
+			status_led_set (0, STATUS_LED_ON);
+			status_led_set (1, STATUS_LED_OFF);
+			status_led_set (2, STATUS_LED_ON);
+			break;
+	}
+}
+#endif
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	set_leds(0);			/* display boot info counter */
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	reg = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
+
+	/*--------------------------------------------------------------------
+	 * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
+	 * via define from board config file.
+	 *-------------------------------------------------------------------*/
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(UIC0PR, 0xfffffe1f);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(SDR0_PFC0, 0x00000000);	/* Pin function: enable GPIO49-63 */
+	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins, select IRQ5 */
+
+	return 0;
+}
+
+#define EEPROM_LEN	256
+static void load_ethaddr(void)
+{
+	int	ok_ethaddr, ok_eth1addr;
+	int	ret;
+	uchar	buf[EEPROM_LEN];
+	char	*use_eeprom;
+	u16	checksumcrc16 = 0;
+
+	/* If the env is sane, then nothing for us to do */
+	ok_ethaddr = eth_getenv_enetaddr("ethaddr", buf);
+	ok_eth1addr = eth_getenv_enetaddr("eth1addr", buf);
+	if (ok_ethaddr && ok_eth1addr)
+		return;
+
+	/* read the MACs from EEprom */
+	status_led_set (0, STATUS_LED_ON);
+	status_led_set (1, STATUS_LED_ON);
+	ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, buf, EEPROM_LEN);
+	if (ret == 0) {
+		checksumcrc16 = cyg_crc16 (buf, EEPROM_LEN - 2);
+		/* check, if the EEprom is programmed:
+		 * - The Prefix(Byte 0,1,2) is equal to "ATR"
+		 * - The checksum, stored in the last 2 Bytes, is correct
+		 */
+		if ((strncmp ((char *)buf,"ATR",3) != 0) ||
+		    ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
+		    ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
+			/* EEprom is not programmed */
+			printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
+		} else {
+			/* get the MACs */
+			if (!ok_ethaddr)
+				eth_setenv_enetaddr("ethaddr", &buf[3]);
+			if (!ok_eth1addr)
+				eth_setenv_enetaddr("eth1addr", &buf[9]);
+			return;
+		}
+	}
+
+	/* some error reading the EEprom */
+	if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
+		/* dont use bootcmd */
+		setenv("bootdelay", "-1");
+		return;
+	}
+	/* == default ? use standard */
+	if (strncmp (use_eeprom, "default", 7) == 0) {
+		return;
+	}
+	/* Env doesnt exist -> hang */
+	status_led_blink ();
+	/* here we do this "handy" because we have no interrupts
+	   at this time */
+	puts ("### EEPROM ERROR ### Please RESET the board ###\n");
+	for (;;) {
+		__led_toggle (12);
+		udelay (100000);
+	}
+	return;
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[]		= "key_magic";
+static uchar kbd_command_prefix[]	= "key_cmd";
+
+struct kbd_data_t {
+	char s1;
+	char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+	char *val;
+	unsigned long tmp;
+
+	/* use the DIPs for some bootoptions */
+	val = getenv (ENV_NAME_DIP);
+	tmp = simple_strtoul (val, NULL, 16);
+
+	kbd_data->s2 = (tmp & 0x0f);
+	kbd_data->s1 = (tmp & 0xf0) >> 4;
+	return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+	char s1 = str[0];
+
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (s1 != kbd_data->s1) return -1;
+
+	s1 = str[1];
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (s1 != kbd_data->s2) return -1;
+	return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can be appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix = kbd_magic_keys; *suffix ||
+		     suffix == kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+		if (compare_magic (kbd_data, getenv (magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv (cmd_name);
+
+			return (cmd);
+		}
+	}
+	return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+static int pcs440ep_readinputs (void)
+{
+	int	i;
+	char	value[20];
+
+	/* read the inputs and set the Envvars */
+	/* Revision Level Bit 26 - 29 */
+	i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
+	i = swapbits[i];
+	sprintf (value, "%02x", i);
+	setenv (ENV_NAME_REVLEV, value);
+	/* Solder Switch Bit 30 - 33 */
+	i = (in32 (GPIO0_IR) & 0x00000003) << 2;
+	i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
+	i = swapbits[i];
+	sprintf (value, "%02x", i);
+	setenv (ENV_NAME_SOLDER, value);
+	/* DIP Switch Bit 49 - 56 */
+	i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
+	i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
+	sprintf (value, "%02x", i);
+	setenv (ENV_NAME_DIP, value);
+	return 0;
+}
+
+
+#if defined(CONFIG_SHA1_CHECK_UB_IMG)
+/*************************************************************************
+ * calculate a SHA1 sum for the U-Boot image in Flash.
+ *
+ ************************************************************************/
+static int pcs440ep_sha1 (int docheck)
+{
+	unsigned char *data;
+	unsigned char *ptroff;
+	unsigned char output[20];
+	unsigned char org[20];
+	int	i, len = CONFIG_SHA1_LEN;
+
+	memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
+	data = (unsigned char *)CONFIG_SYS_LOAD_ADDR;
+	ptroff = &data[len + SHA1_SUM_POS];
+
+	for (i = 0; i < SHA1_SUM_LEN; i++) {
+		org[i] = ptroff[i];
+		ptroff[i] = 0;
+	}
+
+	sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
+
+	if (docheck == 2) {
+		for (i = 0; i < 20 ; i++) {
+			printf("%02X ", output[i]);
+		}
+		printf("\n");
+	}
+	if (docheck == 1) {
+		for (i = 0; i < 20 ; i++) {
+			if (org[i] != output[i]) return 1;
+		}
+	}
+	return 0;
+}
+
+/*************************************************************************
+ * do some checks after the SHA1 checksum from the U-Boot Image was
+ * calculated.
+ *
+ ************************************************************************/
+static void pcs440ep_checksha1 (void)
+{
+	int	ret;
+	char	*cs_test;
+
+	status_led_set (0, STATUS_LED_OFF);
+	status_led_set (1, STATUS_LED_OFF);
+	status_led_set (2, STATUS_LED_ON);
+	ret = pcs440ep_sha1 (1);
+	if (ret == 0) return;
+
+	if ((cs_test = getenv ("cs_test")) == NULL) {
+		/* Env doesnt exist -> hang */
+		status_led_blink ();
+		/* here we do this "handy" because we have no interrupts
+		   at this time */
+		puts ("### SHA1 ERROR ### Please RESET the board ###\n");
+		for (;;) {
+			__led_toggle (2);
+			udelay (100000);
+		}
+	}
+
+	if (strncmp (cs_test, "off", 3) == 0) {
+		printf ("SHA1 U-Boot sum NOT ok!\n");
+		setenv ("bootdelay", "-1");
+	}
+}
+#else
+static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
+#endif
+
+int misc_init_r (void)
+{
+	uint pbcr;
+	int size_val = 0;
+
+	load_ethaddr();
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[1]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+			    &flash_info[1]);
+
+	pcs440ep_readinputs ();
+	pcs440ep_checksha1 ();
+#ifdef CONFIG_PREBOOT
+	{
+		struct kbd_data_t kbd_data;
+		/* Decode keys */
+		char *str = strdup (key_match (get_keys (&kbd_data)));
+		/* Set or delete definition */
+		setenv ("preboot", str);
+		free (str);
+	}
+#endif /* CONFIG_PREBOOT */
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: PCS440EP");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+void spd_ddr_init_hang (void)
+{
+	status_led_set (0, STATUS_LED_OFF);
+	status_led_set (1, STATUS_LED_ON);
+	/* we cannot use hang() because we are still running from
+	   Flash, and so the status_led driver is not initialized */
+	puts ("### SDRAM ERROR ### Please RESET the board ###\n");
+	for (;;) {
+		__led_toggle (4);
+		udelay (100000);
+	}
+}
+
+phys_size_t initdram (int board_type)
+{
+	long dram_size = 0;
+
+	status_led_set (0, STATUS_LED_ON);
+	status_led_set (1, STATUS_LED_OFF);
+	dram_size = spd_sdram();
+	status_led_set (0, STATUS_LED_OFF);
+	status_led_set (1, STATUS_LED_ON);
+	if (dram_size == 0) {
+		hang();
+	}
+
+	return dram_size;
+}
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
+
+/*************************************************************************
+ * "led" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int	rcode = 0, i;
+	ulong	pattern = 0;
+
+	pattern = simple_strtoul (argv[1], NULL, 16);
+	if (pattern > 0x400) {
+		int	val = GET_LEDS;
+		printf ("led: %x\n", val);
+		return rcode;
+	}
+	if (pattern > 0x200) {
+		status_led_blink ();
+		hang ();
+		return rcode;
+	}
+	if (pattern > 0x100) {
+		status_led_blink ();
+		return rcode;
+	}
+	pattern &= 0x0f;
+	for (i = 0; i < 4; i++) {
+		if (pattern & 0x01) status_led_set (i, STATUS_LED_ON);
+		else status_led_set (i, STATUS_LED_OFF);
+		pattern = pattern >> 1;
+	}
+	return rcode;
+}
+
+U_BOOT_CMD(
+	led,	2,	1,	do_led,
+	"set the DIAG-LED",
+	"[bitmask] 0x01 = DIAG 1 on\n"
+	"              0x02 = DIAG 2 on\n"
+	"              0x04 = DIAG 3 on\n"
+	"              0x08 = DIAG 4 on\n"
+	"              > 0x100 set the LED, who are on, to state blinking"
+);
+
+#if defined(CONFIG_SHA1_CHECK_UB_IMG)
+/*************************************************************************
+ * "sha1" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int	rcode = -1;
+
+	if (argc < 2) {
+usage:
+		return cmd_usage(cmdtp);
+	}
+
+	if (argc >= 3) {
+		unsigned char *data;
+		unsigned char output[20];
+		int	len;
+		int	i;
+
+		data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
+		len = simple_strtoul (argv[2], NULL, 16);
+		sha1_csum (data, len, (unsigned char *)output);
+		printf ("U-Boot sum:\n");
+		for (i = 0; i < 20 ; i++) {
+			printf ("%02X ", output[i]);
+		}
+		printf ("\n");
+		if (argc == 4) {
+			data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
+			memcpy (data, output, 20);
+		}
+		return 0;
+	}
+	if (argc == 2) {
+		char *ptr = argv[1];
+		if (*ptr != '-') goto usage;
+		ptr++;
+		if ((*ptr == 'c') || (*ptr == 'C')) {
+			rcode = pcs440ep_sha1 (1);
+			printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
+		} else if ((*ptr == 'p') || (*ptr == 'P')) {
+			rcode = pcs440ep_sha1 (2);
+		} else {
+			rcode = pcs440ep_sha1 (0);
+		}
+		return rcode;
+	}
+	return rcode;
+}
+
+U_BOOT_CMD(
+	sha1,	4,	1,	do_sha1,
+	"calculate the SHA1 Sum",
+	"address len [addr]  calculate the SHA1 sum [save at addr]\n"
+	"     -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
+	"     -c check the U-Boot image in flash"
+);
+#endif
+
+#if defined (CONFIG_CMD_IDE)
+/* These addresses need to be shifted one place to the left
+ * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
+ * These values are shifted
+ */
+extern ulong *ide_bus_offset;
+void inline ide_outb(int dev, int port, unsigned char val)
+{
+	debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+		dev, port, val, (ATA_CURR_BASE(dev)+port));
+
+	out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
+}
+unsigned char inline ide_inb(int dev, int port)
+{
+	uchar val;
+	val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
+	debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+		dev, port, (ATA_CURR_BASE(dev)+port), val);
+	return (val);
+}
+#endif
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit (void)
+{
+	/* Set True IDE Mode */
+	out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
+	out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+	out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
+	udelay (100000);
+	return 0;
+}
+#endif
+
+#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+	if (idereset == 0) {
+		out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+	} else {
+		out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
+	}
+	udelay (10000);
+}
+#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
diff --git a/u-boot/board/pdm360ng/Makefile b/u-boot/board/pdm360ng/Makefile
new file mode 100644
index 0000000..1b3d530
--- /dev/null
+++ b/u-boot/board/pdm360ng/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pdm360ng/pdm360ng.c b/u-boot/board/pdm360ng/pdm360ng.c
new file mode 100644
index 0000000..2082ad4
--- /dev/null
+++ b/u-boot/board/pdm360ng/pdm360ng.c
@@ -0,0 +1,688 @@
+/*
+ * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
+ *
+ * (C) Copyright 2009-2010
+ * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#include <flash.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <serial.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];
+ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Initialize Local Window for FLASH-Bank1 access (CS1)
+	 */
+	out_be32(&im->sysconf.lpcs1aw,
+		CSAW_START(CONFIG_SYS_FLASH1_BASE) |
+		CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+
+	/*
+	 * Local Window for MRAM access (CS2)
+	 */
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_MRAM_BASE) |
+		CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+
+	sync_law(&im->sysconf.lpcs2aw);
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+	out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	return 0;
+}
+
+sdram_conf_t mddrc_config[] = {
+	{
+		(512 << 20),	/* 512 MB RAM configuration */
+		{
+			CONFIG_SYS_MDDRC_SYS_CFG,
+			CONFIG_SYS_MDDRC_TIME_CFG0,
+			CONFIG_SYS_MDDRC_TIME_CFG1,
+			CONFIG_SYS_MDDRC_TIME_CFG2
+		}
+	},
+	{
+		(128 << 20),	/* 128 MB RAM configuration */
+		{
+			CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
+			CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
+			CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
+			CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
+		}
+	},
+};
+
+phys_size_t initdram (int board_type)
+{
+	int i;
+	u32 msize = 0;
+	u32 pdm360ng_init_seq[] = {
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_MICRON_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_EM3,
+		CONFIG_SYS_DDRCMD_EN_DLL,
+		CONFIG_SYS_DDRCMD_RES_DLL,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_MICRON_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+		CONFIG_SYS_DDRCMD_OCD_EXIT,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
+		msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
+				    ARRAY_SIZE(pdm360ng_init_seq));
+		if (msize == mddrc_config[i].size)
+			break;
+	}
+
+	return msize;
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
+static int set_lcd_brightness(char *);
+#endif
+
+int misc_init_r(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Re-configure flash setup using auto-detected info
+	 */
+	if (flash_info[1].size > 0) {
+		out_be32(&im->sysconf.lpcs1aw,
+			CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
+			CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
+				  flash_info[1].size));
+		sync_law(&im->sysconf.lpcs1aw);
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
+	} else {
+		/* Disable Bank 1 */
+		out_be32(&im->sysconf.lpcs1aw, 0x01000100);
+		sync_law(&im->sysconf.lpcs1aw);
+	}
+
+	out_be32(&im->sysconf.lpcs0aw,
+		CSAW_START(gd->bd->bi_flashstart) |
+		CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
+	sync_law(&im->sysconf.lpcs0aw);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size (gd->bd->bi_flashstart, 0);
+
+	/*
+	 * Re-do flash protection upon new addresses
+	 */
+	flash_protect (FLAG_PROTECT_CLEAR,
+		       gd->bd->bi_flashstart, 0xffffffff,
+		       &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+		       &flash_info[0]);
+
+	/* Environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	/* Redundant environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR_REDUND,
+		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[0]);
+#endif
+
+#ifdef CONFIG_FSL_DIU_FB
+#if defined(CONFIG_SERIAL_MULTI)
+	set_lcd_brightness(0);
+#endif
+	/* Switch LCD-Backlight and LVDS-Interface on */
+	setbits_be32(&im->gpio.gpdir, 0x01040000);
+	clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
+#endif
+
+#if defined(CONFIG_HARD_I2C)
+	if (!getenv("ethaddr")) {
+		uchar buf[6];
+		uchar ifm_oui[3] = { 0, 2, 1, };
+		int ret;
+
+		/* I2C-0 for on-board eeprom */
+		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
+
+		/* Read ethaddr from EEPROM */
+		ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
+			       CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
+		if (ret != 0) {
+			printf("Error: Unable to read MAC from I2C"
+				" EEPROM at address %02X:%02X\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR,
+				CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
+			return 1;
+		}
+
+		/* Owned by IFM ? */
+		if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
+			printf("Illegal MAC address in EEPROM: %pM\n", buf);
+			return 1;
+		}
+
+		eth_setenv_enetaddr("ethaddr", buf);
+	}
+#endif /* defined(CONFIG_HARD_I2C) */
+
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/* FUNC1=LPC_CS4 */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO10 */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC1=CAN3_TX */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO14 */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
+	/* DIU_LD22-DIU_LD23 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
+	/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
+	/* VIU_DATA0-VIU_DATA2 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=FEC_TXD_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
+	/* VIU_DATA3, VIU_DATA4 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
+	/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
+	/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
+	/* DIU_LD00-DIU_LD21 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
+	/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=CAN3_RX */
+	{
+		offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* Sets lowest slew on 2 CAN_TX Pins*/
+	{
+		offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
+	/* CAN4_TX, CAN4_RX */
+	{
+		offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
+	/* GPIO8, GPIO9 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
+	/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
+	/* FEC_RXD_3, FEC_RXD_2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO17 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
+	/* GPIO2, GPIO20, GPIO21 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=VIU_PIX_CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
+	/* GPIO24, GPIO25 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC1=NFC_CE2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
+	/* VIU_DATA5-VIU_DATA9 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
+	/* LPC_TSIZ1-LPC_TSIZ2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=LPC_TS */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO16 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
+	/* GPIO18-GPIO19, GPT7/GPIO7 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO0/GPT0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
+	/* GPIO11, GPIO2, GPIO12, GPIO13 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=DIU_DE */
+	{
+		offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+int checkboard (void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	puts("Board: PDM360NG\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
+	setbits_be32(&im->io_ctrl.io_control_gp,
+		     (1 << 0) |   /* GP_MUX7->GPIO7 */
+		     (1 << 5));	  /* GP_MUX2->GPIO2 */
+
+	/* configure GPIO24 (VIU_CE), output/high */
+	setbits_be32(&im->gpio.gpdir, 0x80);
+	setbits_be32(&im->gpio.gpdat, 0x80);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
+	{ "cfi-flash",		MTD_DEV_TYPE_NOR,  },
+};
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ *     ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
+ * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
+ * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
+ * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
+ * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
+ * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
+ * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+	0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
+	0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
+	0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
+	0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
+	0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
+	0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
+	0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
+	0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
+	0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
+	0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
+	0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+	0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
+};
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[8];
+	int rc, i = 0;
+
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+#if defined(CONFIG_VIDEO)
+	fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
+#endif
+
+	/* Fixup NOR FLASH mapping */
+	val[i++] = 0;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = gd->bd->bi_flashstart;
+	val[i++] = gd->bd->bi_flashsize;
+
+	/* Fixup MRAM mapping */
+	val[i++] = 2;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = CONFIG_SYS_MRAM_BASE;
+	val[i++] = CONFIG_SYS_MRAM_SIZE;
+
+	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+				  val, i * sizeof(u32), 1);
+	if (rc)
+		printf("Unable to update localbus ranges, err=%s\n",
+		       fdt_strerror(rc));
+
+	/* Fixup reg property in NOR Flash node */
+	i = 0;
+	val[i++] = 0;			/* always 0 */
+	val[i++] = 0;			/* start at offset 0 */
+	val[i++] = flash_info[0].size;	/* size of Bank 0 */
+
+	/* Second Bank available? */
+	if (flash_info[1].size > 0) {
+		val[i++] = 0;			/* always 0 */
+		val[i++] = flash_info[0].size;	/* offset of Bank 1 */
+		val[i++] = flash_info[1].size;	/* size of Bank 1 */
+	}
+
+	rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
+				  val, i * sizeof(u32), 1);
+	if (rc)
+		printf("Unable to update flash reg property, err=%s\n",
+		       fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SERIAL_MULTI)
+/*
+ * If argument is NULL, set the LCD brightness to the
+ * value from "brightness" environment variable. Set
+ * the LCD brightness to the value specified by the
+ * argument otherwise. Default brightness is zero.
+ */
+#define MAX_BRIGHTNESS	99
+static int set_lcd_brightness(char *brightness)
+{
+	struct stdio_dev *cop_port;
+	char *env;
+	char cmd_buf[20];
+	int val = 0;
+	int cs = 0;
+	int len, i;
+
+	if (brightness) {
+		val = simple_strtol(brightness, NULL, 10);
+	} else {
+		env = getenv("brightness");
+		if (env)
+			val = simple_strtol(env, NULL, 10);
+	}
+
+	if (val < 0)
+		val = 0;
+
+	if (val > MAX_BRIGHTNESS)
+		val = MAX_BRIGHTNESS;
+
+	sprintf(cmd_buf, "$SB;%04d;", val);
+
+	len = strlen(cmd_buf);
+	for (i = 1; i <= len; i++)
+		cs += cmd_buf[i];
+
+	cs = (~cs + 1) & 0xff;
+	sprintf(cmd_buf + len, "%02X\n", cs);
+
+	/* IO Coprocessor communication */
+	cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+	if (!cop_port) {
+		printf("Error: Can't open IO Coprocessor port.\n");
+		return -1;
+	}
+
+	debug("%s: cmd: %s", __func__, cmd_buf);
+	write_port(cop_port, cmd_buf);
+	/*
+	 * Wait for transmission and maybe response data
+	 * before closing the port.
+	 */
+	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+	memset(cmd_buf, 0, sizeof(cmd_buf));
+	len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
+	if (len)
+		printf("Error: %s\n", cmd_buf);
+
+	close_port(4);
+
+	return 0;
+}
+
+static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
+			      int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	return set_lcd_brightness(argv[1]);
+}
+
+U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
+	"set LCD brightness",
+	"<brightness> - set LCD backlight level to <brightness>.\n"
+);
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/u-boot/board/phytec/pcm030/Makefile b/u-boot/board/phytec/pcm030/Makefile
new file mode 100644
index 0000000..f5d88bb
--- /dev/null
+++ b/u-boot/board/phytec/pcm030/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/phytec/pcm030/mt46v32m16-75.h b/u-boot/board/phytec/pcm030/mt46v32m16-75.h
new file mode 100644
index 0000000..d69c09c
--- /dev/null
+++ b/u-boot/board/phytec/pcm030/mt46v32m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * Eric Schumann, Phytec Messtechnik
+ * adapted for mt46v32m16-75 DDR-RAM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x71500F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x47770000
+
+#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/u-boot/board/phytec/pcm030/pcm030.c b/u-boot/board/phytec/pcm030/pcm030.c
new file mode 100644
index 0000000..77ce389
--- /dev/null
+++ b/u-boot/board/phytec/pcm030/pcm030.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#include "mt46v32m16-75.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	volatile struct mpc5xxx_cdm *cdm =
+		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+#ifdef SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32 (&sdram->mode, (SDRAM_EMODE));
+
+	/* set mode register: reset DLL */
+	out_be32 (&sdram->mode,
+		(SDRAM_MODE | 0x04000000));
+#endif
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+	/* auto refresh */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
+
+	/* set mode register */
+	out_be32 (&sdram->mode, (SDRAM_MODE));
+
+	/* normal operation */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | hi_addr_bit));
+
+	/* set CDM clock enable register, set MPC5200B SDRAM bus */
+	/* to reduced driver strength */
+	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make
+ *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
+ *	work if CONFIG_SYS_SDRAM_BASE
+ *	is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	volatile struct mpc5xxx_cdm *cdm =
+		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+							 /* 256MB at 0x0 */
+	out_be32 (&mm->sdram0, 0x0000001b);
+							 /* disabled */
+	out_be32 (&mm->sdram1, 0x10000000);
+
+	/* setup config registers */
+	out_be32 (&sdram->config1, SDRAM_CONFIG1);
+	out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
+	/* set tap delay */
+	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32 (&mm->sdram0,
+			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+							/* disabled */
+		out_be32 (&mm->sdram0, 0);
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mm->sdram0) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+	puts("Board: phyCORE-MPC5200B-tiny\n");
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t * bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC2_4	0x02000000UL
+
+void init_ide_reset(void)
+{
+	volatile struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	debug("init_ide_reset\n");
+
+	/* Configure PSC2_4 as GPIO output for ATA reset */
+	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
+	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
+	/* Deassert reset */
+	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else
+		setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+}
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/u-boot/board/pleb2/Makefile b/u-boot/board/pleb2/Makefile
new file mode 100644
index 0000000..9b076f5
--- /dev/null
+++ b/u-boot/board/pleb2/Makefile
@@ -0,0 +1,50 @@
+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= pleb2.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pleb2/flash.c b/u-boot/board/pleb2/flash.c
new file mode 100644
index 0000000..a8897dc
--- /dev/null
+++ b/u-boot/board/pleb2/flash.c
@@ -0,0 +1,814 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+/* environment.h defines the various CONFIG_ENV_... values in terms
+ * of whichever ones are given in the configuration file.
+ */
+#include <environment.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static void flash_reset (flash_info_t * info);
+static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data);
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+static void flash_sync_real_protect (flash_info_t * info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b;
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",
+			size_b);
+	}
+
+	/* Do this again (was done already in flast_get_size), just
+	 * in case we move it when remap the FLASH.
+	 */
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+	/* read the hardware protection status (if any) into the
+	 * protection array in flash_info.
+	 */
+	flash_sync_real_protect (&flash_info[0]);
+#endif
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_ADDR
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR_REDUND,
+		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[0]);
+#endif
+
+	return (size_b);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset (flash_info_t * info)
+{
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector  */
+		int sect_size;	/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set sector offsets for bottom boot block type        */
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (top boot sector type) */
+		for (i = 0; i < info->sector_count - 3; i++)
+			info->start[i] = base + (i * sect_size);
+		i = info->sector_count - 1;
+		info->start[i--] =
+			base + (info->size - 0x00004000) * (sizeof (FPW) / 2);
+		info->start[i--] =
+			base + (info->size - 0x00006000) * (sizeof (FPW) / 2);
+		info->start[i--] =
+			base + (info->size - 0x00008000) * (sizeof (FPW) / 2);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		fmt = "29LV800B%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW) 0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[1]) {
+
+		case (FPW) AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MiB        */
+
+		case (FPW) AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* => no or unknown flash */
+		}
+
+	flash_get_offsets ((ulong) addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset (info);
+
+	return (info->size);
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	FPWV *addr = (FPWV *) (info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW) 0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			 * D0 = 1 for each device if protected.
+			 * If at least one device is protected the sector is marked
+			 * protected, but mixed protected and  unprotected devices
+			 * within a sector should never happen.
+			 */
+			sect = (FPWV *) (info->start[i]);
+			info->protect[i] =
+				(sect[2] & (FPW) (0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset (info);
+		break;
+
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	reset_timer_masked ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		reset_timer_masked ();
+		last = 0;
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			base[0x0555] = (FPW) 0x00800080;	/* erase mode */
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now =
+			     get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+
+				flash_reset (info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1 * CONFIG_SYS_HZ) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+
+		flash_reset (info);	/* reset to read mode   */
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof (data), left -= sizeof (data) - bytes) {
+
+		bytes = addr & (sizeof (data) - 1);
+		addr &= ~(sizeof (data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
+		for (i = 0; i < sizeof (data); i++) {
+			data >>= 8;
+			if (i < bytes || i - bytes >= left)
+				data += (*((uchar *) addr + i)) << 24;
+			else
+				data += (*src++) << 24;
+		}
+#else
+		for (i = 0; i < sizeof (data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+#endif
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd (info, (FPWV *) addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel (info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
+{
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *) (info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+	base[0x0555] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	reset_timer_masked ();
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data)
+{
+	int flag;
+	int res = 0;		/* result, assume success       */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+	*dest = (FPW) 0x00400040;	/* program setup                */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	reset_timer_masked ();
+
+	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW) 0x00100010))
+		res = 1;	/* write failed, time out error is close enough */
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+
+	return (res);
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset (info);	/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset (info);	/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect (info);
+		break;
+
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/u-boot/board/pleb2/pleb2.c b/u-boot/board/pleb2/pleb2.c
new file mode 100644
index 0000000..5a16cc7
--- /dev/null
+++ b/u-boot/board/pleb2/pleb2.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
diff --git a/u-boot/board/pm520/Makefile b/u-boot/board/pm520/Makefile
new file mode 100644
index 0000000..d45db9f
--- /dev/null
+++ b/u-boot/board/pm520/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pm520/flash.c b/u-boot/board/pm520/flash.c
new file mode 100644
index 0000000..64c8624
--- /dev/null
+++ b/u-boot/board/pm520/flash.c
@@ -0,0 +1,668 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			(x)
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			(x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT		0x00890089
+#define INTEL_ALT		0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM		0x00100010
+#define INTEL_ERASE		0x00200020
+#define INTEL_CLEAR		0x00500050
+#define INTEL_LOCKBIT		0x00600060
+#define INTEL_PROTECT		0x00010001
+#define INTEL_STATUS		0x00700070
+#define INTEL_READID		0x00900090
+#define INTEL_CONFIRM		0x00D000D0
+#define INTEL_RESET		0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED		0x00800080
+#define INTEL_OK		0x00800080
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(ulong, ulong);
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+	flash_preinit();
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			memset(&flash_info[i], 0, sizeof(flash_info_t));
+			flash_get_size ((FPW *) flashbase, &flash_info[i]);
+			flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+
+		/* get the h/w and s/w protection status in sync */
+		flash_sync_real_protect(&flash_info[i]);
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#ifndef CONFIG_BOOT_ROM
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+#endif
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+#endif
+
+	flash_afterinit(flash_info[0].start[0], flash_info[0].size);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256J3A:
+		printf ("28F256J3A\n");
+		break;
+
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	udelay(100);
+
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F256J3A:
+		info->flash_id += FLASH_28F256J3A;
+		/* In U-Boot we support only 32 MB (no bank-switching) */
+		info->sector_count = 256 / 2;
+		info->size =  0x04000000 / 2;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000;
+		break;				/* => 16 MB     */
+
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x800000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000;
+		break;				/* => 8 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+
+	case FLASH_28F256J3A:
+	case FLASH_28F128J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F320J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 2 for 16 bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 2;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t *info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	start = get_timer(0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 * WARNING: code below re-locks sectors only for one bank (info).
+	 * This causes problems on boards where several banks share
+	 * the same chip, as sectors in othere banks will be unlocked
+	 * but not re-locked. It works fine on pm520 though, as there
+	 * is only one chip and one bank.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				start = get_timer(0);
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+				{
+					if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+		/*
+		 * get the s/w sector protection status in sync with the h/w,
+		 * in case something went wrong during the re-locking.
+		 */
+		flash_sync_real_protect(info); /* resets flash to read  mode */
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/u-boot/board/pm520/mt46v16m16-75.h b/u-boot/board/pm520/mt46v16m16-75.h
new file mode 100644
index 0000000..423febe
--- /dev/null
+++ b/u-boot/board/pm520/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/u-boot/board/pm520/mt48lc16m16a2-75.h b/u-boot/board/pm520/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..1547725
--- /dev/null
+++ b/u-boot/board/pm520/mt48lc16m16a2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/pm520/pm520.c b/u-boot/board/pm520/pm520.c
new file mode 100644
index 0000000..d691434
--- /dev/null
+++ b/u-boot/board/pm520/pm520.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: MicroSys PM520 \n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong start, ulong size)
+{
+#if defined(CONFIG_BOOT_ROM)
+	/* adjust mapping */
+	*(vu_long *)MPC5XXX_CS1_START =
+			START_REG(start);
+	*(vu_long *)MPC5XXX_CS1_STOP =
+			STOP_REG(start, size);
+#else
+	/* adjust mapping */
+	*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(start);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(start, size);
+#endif
+}
+
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	return (0);
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+}
+#endif
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/pm826/Makefile b/u-boot/board/pm826/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/pm826/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pm826/flash.c b/u-boot/board/pm826/flash.c
new file mode 100644
index 0000000..010f59a
--- /dev/null
+++ b/u-boot/board/pm826/flash.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write query command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00980098;
+	baseaddr[1] = 0x00980098;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3 or 640C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/* protect monitor and environment sectors
+	 */
+
+#ifndef CONFIG_BOOT_ROM
+	/* If U-Boot is  booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE
+	 * but we shouldn't protect it.
+	 */
+
+# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+# endif
+#endif	/* CONFIG_BOOT_ROM */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+		start = get_timer (0);
+		last = start;
+		if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+			flag = disable_interrupts ();
+
+			/* Erase the block
+			 */
+			addr[0] = 0x00200020;
+			addr[1] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			addr[1] = 0x00D000D0;
+
+			/* re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			last = start;
+			while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+				if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout (erase suspended!)\n");
+					/* Suspend erase
+					 */
+					addr[0] = 0x00B000B0;
+					addr[1] = 0x00B000B0;
+					goto DONE;
+				}
+				/* show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* every second */
+					serial_putc ('.');
+					last = now;
+				}
+			}
+			if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+				printf ("*** ERROR: erase failed!\n");
+				goto DONE;
+			}
+		}
+		/* Clear status register and reset to read mode
+		 */
+		addr[0] = 0x00500050;
+		addr[1] = 0x00500050;
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, cc = cnt, res = 0;
+
+
+	for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+		l = (addr & 3);
+		addr &= ~3;
+
+		for (i = 0; i < 4; i++) {
+			v = (v << 8) + (i < l || i - l >= cc ?
+				*((unsigned char *) addr + i) : *src++);
+		}
+
+		if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+			break;
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
diff --git a/u-boot/board/pm826/pm826.c b/u-boot/board/pm826/pm826.c
new file mode 100644
index 0000000..19e7a00
--- /dev/null
+++ b/u-boot/board/pm826/pm826.c
@@ -0,0 +1,335 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+#include <netdev.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* PA25 */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* PA22 */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* PA13 */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* PA12 */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* PA11 */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* PA10 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* PA9 */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* PA8 */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
+	/* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+#else
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
+#endif
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PB14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC3 RXD */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   1,   1,   1,   0,   0   }, /* SCC3 TXD */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DCD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 DCD */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 CTS */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 DCD */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 CTS */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 DCD */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* PD30 */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 RTS */
+	/* PD22 */ {   1,   1,   0,   0,   0,   0   }, /* SCC4 RXD */
+	/* PD21 */ {   1,   1,   0,   1,   0,   0   }, /* SCC4 TXD */
+	/* PD20 */ {   0,   0,   1,   1,   0,   0   }, /* SCC4 RTS */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* PD9 */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* PD8 */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: PM826\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong size8, size9;
+#endif
+	ulong psize = 32 * 1024 * 1024;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+#endif
+	return (psize);
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/pm828/Makefile b/u-boot/board/pm828/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/pm828/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pm828/flash.c b/u-boot/board/pm828/flash.c
new file mode 100644
index 0000000..4958a95
--- /dev/null
+++ b/u-boot/board/pm828/flash.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write query command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00980098;
+	baseaddr[1] = 0x00980098;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3 or 640c3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/* protect monitor and environment sectors
+	 */
+
+#ifndef CONFIG_BOOT_ROM
+	/* If U-Boot is  booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE
+	 * but we shouldn't protect it.
+	 */
+
+# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+# endif
+#endif	/* CONFIG_BOOT_ROM */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+		start = get_timer (0);
+		last = start;
+		if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+			flag = disable_interrupts ();
+
+			/* Erase the block
+			 */
+			addr[0] = 0x00200020;
+			addr[1] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			addr[1] = 0x00D000D0;
+
+			/* re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			last = start;
+			while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+				if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout (erase suspended!)\n");
+					/* Suspend erase
+					 */
+					addr[0] = 0x00B000B0;
+					addr[1] = 0x00B000B0;
+					goto DONE;
+				}
+				/* show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* every second */
+					serial_putc ('.');
+					last = now;
+				}
+			}
+			if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+				printf ("*** ERROR: erase failed!\n");
+				goto DONE;
+			}
+		}
+		/* Clear status register and reset to read mode
+		 */
+		addr[0] = 0x00500050;
+		addr[1] = 0x00500050;
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, cc = cnt, res = 0;
+
+
+	for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+		l = (addr & 3);
+		addr &= ~3;
+
+		for (i = 0; i < 4; i++) {
+			v = (v << 8) + (i < l || i - l >= cc ?
+				*((unsigned char *) addr + i) : *src++);
+		}
+
+		if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+			break;
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
diff --git a/u-boot/board/pm828/pm828.c b/u-boot/board/pm828/pm828.c
new file mode 100644
index 0000000..4a3b2fd
--- /dev/null
+++ b/u-boot/board/pm828/pm828.c
@@ -0,0 +1,368 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+#include <netdev.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* PA25 */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* PA22 */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* PA13 */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* PA12 */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* PA11 */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* PA10 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* PA9 */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* PA8 */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
+	/* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+#else
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
+#endif
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PB14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC3 RXD */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   1,   1,   1,   0,   0   }, /* SCC3 TXD */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DCD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 DCD */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 CTS */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 DCD */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 CTS */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 DCD */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* PD30 */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 RTS */
+	/* PD22 */ {   1,   1,   0,   0,   0,   0   }, /* SCC4 RXD */
+	/* PD21 */ {   1,   1,   0,   1,   0,   0   }, /* SCC4 TXD */
+	/* PD20 */ {   0,   0,   1,   1,   0,   0   }, /* SCC4 RTS */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* PD9 */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* PD8 */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: PM828\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile ulong cnt, val;
+	volatile ulong *addr;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	int i;
+	ulong save[32];				/* to make test non-destructive */
+	ulong maxsize;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	/*
+	 * Check memory range for valid RAM. A simple memory test determines
+	 * the actually available RAM size between addresses `base' and
+	 * `base + maxsize'. Some (not all) hardware errors are detected:
+	 * - short between address lines
+	 * - short between data lines
+	 */
+	i = 0;
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			/* Write the actual size to ORx
+			 */
+			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong size8, size9;
+#endif
+	ulong psize = 32 * 1024 * 1024;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+#endif
+	return (psize);
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/pn62/Makefile b/u-boot/board/pn62/Makefile
new file mode 100644
index 0000000..eb17b5c
--- /dev/null
+++ b/u-boot/board/pn62/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o cmd_pn62.o misc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pn62/cmd_pn62.c b/u-boot/board/pn62/cmd_pn62.c
new file mode 100644
index 0000000..939cb4a
--- /dev/null
+++ b/u-boot/board/pn62/cmd_pn62.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <command.h>
+#include "pn62.h"
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Command led: controls the various LEDs 0..11 on the PN62 card.
+ */
+int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	unsigned int number, function;
+
+	if (argc != 3)
+		return cmd_usage(cmdtp);
+
+	number = simple_strtoul(argv[1], NULL, 10);
+	if (number > PN62_LED_MAX)
+		return 1;
+
+	function = simple_strtoul(argv[2], NULL, 16);
+	set_led(number, function);
+	return 0;
+}
+U_BOOT_CMD(
+	led    ,	3,	1,	do_led,
+	"set LED 0..11 on the PN62 board",
+	"i fun"
+	"    - set 'i'th LED to function 'fun'"
+);
+
+/*
+ * Command loadpci: loads a image over PCI.
+ */
+#define CMD_MOVE_WINDOW 0x1
+#define CMD_BOOT_IMAGE  0x2
+
+int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+    char *s;
+    ulong addr = 0, count = 0;
+    u32 off;
+    int cmd, rcode = 0;
+
+    /* pre-set load_addr */
+    if ((s = getenv("loadaddr")) != NULL) {
+	addr = simple_strtoul(s, NULL, 16);
+    }
+
+    switch (argc) {
+    case 1:
+	break;
+    case 2:
+	addr = simple_strtoul(argv[1], NULL, 16);
+	break;
+    default:
+	return cmd_usage(cmdtp);
+    }
+
+    printf ("## Ready for image download ...\n");
+
+    show_startup_phase(12);
+
+    while (1) {
+	/* Alive indicator */
+	i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
+
+	/* Toggle status LEDs */
+	cmd = (count / 200) % 4; /* downscale */
+	set_led(4, cmd == 0 ? LED_1 : LED_0);
+	set_led(5, cmd == 1 ? LED_1 : LED_0);
+	set_led(6, cmd == 2 ? LED_1 : LED_0);
+	set_led(7, cmd == 3 ? LED_1 : LED_0);
+	udelay(1000);
+	count++;
+
+	cmd = i2155x_read_scrapad(BOOT_CMD);
+
+	if (cmd == BOOT_CMD_MOVE) {
+	    off = i2155x_read_scrapad(BOOT_DATA);
+	    off += addr;
+	    i2155x_set_bar_base(3, off);
+	    printf ("## BAR3 Addr moved = 0x%08x\n", off);
+	    i2155x_write_scrapad(BOOT_CMD, ~cmd);
+	    show_startup_phase(13);
+	}
+	else if (cmd == BOOT_CMD_BOOT) {
+	    set_led(4, LED_1);
+	    set_led(5, LED_1);
+	    set_led(6, LED_1);
+	    set_led(7, LED_1);
+
+	    i2155x_write_scrapad(BOOT_CMD, ~cmd);
+	    show_startup_phase(14);
+	    break;
+	}
+
+	/* Abort if ctrl-c was pressed */
+	if (ctrlc()) {
+	    printf("\nAbort\n");
+	    return 0;
+	}
+
+    }
+
+    /* Repoint to the default shared memory */
+    i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
+
+    load_addr = addr;
+    printf ("## Start Addr      = 0x%08lx\n", addr);
+
+    show_startup_phase(15);
+
+    /* Loading ok, check if we should attempt an auto-start */
+    if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
+	char *local_args[2];
+	local_args[0] = argv[0];
+	local_args[1] = NULL;
+
+	printf ("Automatic boot of image at addr 0x%08lX ...\n",
+		load_addr);
+	rcode = do_bootm (cmdtp, 0, 1, local_args);
+    }
+
+    return rcode;
+}
+
+U_BOOT_CMD(
+	loadpci,	2,	1,	do_loadpci,
+	"load binary file over PCI",
+	"[addr]\n"
+	"    - load binary file over PCI to address 'addr'"
+);
+
+#endif
diff --git a/u-boot/board/pn62/misc.c b/u-boot/board/pn62/misc.c
new file mode 100644
index 0000000..dcb2db5
--- /dev/null
+++ b/u-boot/board/pn62/misc.c
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "pn62.h"
+
+typedef struct {
+    pci_dev_t    devno;
+    volatile u32 *csr;
+
+} i2155x_t;
+
+static i2155x_t i2155x = { 0, NULL };
+
+static struct pci_device_id i2155x_ids[] = {
+    { 0x1011, 0x0046 },		/* i21554 */
+    { 0x8086, 0xb555 }		/* i21555 */
+};
+
+int i2155x_init(void)
+{
+    pci_dev_t devno;
+    u32 val;
+    int i;
+
+    /*
+     * Find the Intel bridge.
+     */
+    if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
+	printf("Error: Intel bridge 2155x not found!\n");
+	return -1;
+    }
+    i2155x.devno = devno;
+
+    /*
+     * Get auto-configured base address for CSR access.
+     */
+    pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
+    if (val & PCI_BASE_ADDRESS_SPACE_IO) {
+	val &= PCI_BASE_ADDRESS_IO_MASK;
+	i2155x.csr = (volatile u32 *)(_IO_BASE + val);
+    } else {
+	val &= PCI_BASE_ADDRESS_MEM_MASK;
+	i2155x.csr =  (volatile u32 *)val;
+    }
+
+    /*
+     * Translate downstream memory 2 (bar3) to base of shared memory.
+     */
+    i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
+
+    /*
+     * Enable memory space, I/O space and bus master bits
+     * in both Primary and Secondary command registers.
+     */
+    val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
+    pci_write_config_word(devno, 0x44, val);
+    pci_write_config_word(devno, 0x04, val);
+
+    /*
+     * Clear scratchpad registers.
+     */
+    for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
+	i2155x_write_scrapad(i, 0x0);
+    }
+
+    /*
+     * Set interrupt line for Linux.
+     */
+    pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
+
+    return 0;
+}
+
+/*
+ * Access the Scratchpad registers 0..7 of the Intel bridge.
+ */
+void i2155x_write_scrapad(int idx, u32 val)
+{
+    if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
+	out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
+    else
+	printf("i2155x_write_scrapad: invalid index\n");
+}
+
+u32 i2155x_read_scrapad(int idx)
+{
+    if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
+	return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
+    else
+	printf("i2155x_read_scrapad: invalid index\n");
+    return -1;
+}
+
+void i2155x_set_bar_base(int bar, u32 base)
+{
+    if (bar >= 2 && bar <= 4) {
+	pci_write_config_dword(i2155x.devno,
+			       I2155X_BAR2_BASE + (bar - 2) * 4,
+			       base);
+    }
+}
+
+/*
+ * Read Vital Product Data (VPD) from the Serial EPROM attached
+ * to the Intel bridge.
+ */
+int i2155x_read_vpd(int offset, int size, unsigned char *data)
+{
+    int i, n;
+    u16 val16;
+
+    for (i = 0; i < size; i++) {
+	pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
+			      offset + i - I2155X_VPD_START);
+	for (n = 10000; n > 0; n--) {
+	    pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
+	    if ((val16 & 0x8000) != 0) /* wait for completion */
+		break;
+	    udelay(100);
+	}
+	if (n == 0) {
+	    printf("i2155x_read_vpd: TIMEOUT\n");
+	    return -1;
+	}
+
+	pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
+    }
+
+    return i;
+}
+
+static struct pci_device_id am79c95x_ids [] = {
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
+	{ }
+};
+
+
+/*
+ * Initialize the AMD ethernet controllers.
+ */
+int am79c95x_init(void)
+{
+    pci_dev_t devno;
+    int i;
+
+    /*
+     * Set interrupt line for Linux.
+     */
+    for (i = 0; i < 2; i++) {
+	if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
+	    break;
+	pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
+    }
+    if (i < 2)
+	printf("Error: Only %d AMD Ethernet Controller found!\n", i);
+
+    return 0;
+}
+
+
+void set_led(unsigned int number, unsigned int function)
+{
+    volatile u8 *addr;
+
+    if ((number >= 0) && (number < PN62_LED_MAX) &&
+	(function >= 0) && (function <= LED_LAST_FUNCTION)) {
+	addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
+	out_8(addr, function&0xff);
+    }
+}
+
+/*
+ * Show fatal error indicated by Kinght Rider(tm) effect
+ * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
+ * Note: this function will not terminate.
+ */
+void fatal_error(unsigned int error_code)
+{
+    int i, d;
+
+    for (i = 0; i < 12; i++) {
+	set_led(i, LED_0);
+    }
+
+    /*
+     * Write error code.
+     */
+    set_led(8,  (error_code & 0x01) ? LED_1 : LED_0);
+    set_led(9,  (error_code & 0x02) ? LED_1 : LED_0);
+    set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
+    set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
+
+    /*
+     * Yay - Knight Rider effect!
+     */
+    while(1) {
+	unsigned int delay = 2000;
+
+	for (i = 0; i < 8; i++) {
+	    set_led(i, LED_1);
+	    for (d = 0; d < delay; d++);
+	    set_led(i, LED_0);
+	}
+
+	for (i = 7; i > 0; i--) {
+	    set_led(i, LED_1);
+	    for (d = 0; d < delay; d++);
+	    set_led(i, LED_0);
+	}
+    }
+}
diff --git a/u-boot/board/pn62/pn62.c b/u-boot/board/pn62/pn62.c
new file mode 100644
index 0000000..676f8d3
--- /dev/null
+++ b/u-boot/board/pn62/pn62.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <net.h>
+#include <pci.h>
+#include <netdev.h>
+
+#include "pn62.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_serial_number (char *string, int size);
+static void get_mac_address(int id, u8 *mac);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress (int phase)
+{
+	/*
+	 * Show phases of the bootm command on the front panel
+	 * LEDs and the scratchpad register #3 as well. We use
+	 * blinking LEDs for logical "1".
+	 */
+	if (phase > 0) {
+		set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
+		set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
+		set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
+		set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
+	}
+	i2155x_write_scrapad (BOOT_STATUS, phase);
+	if (phase < 0)
+		i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
+}
+#endif
+
+void show_startup_phase (int phase)
+{
+	/*
+	 * Show the phase of U-Boot startup on the front panel
+	 * LEDs and the scratchpad register #3 as well.
+	 */
+	if (phase > 0) {
+		set_led (8, (phase & 0x1) ? LED_1 : LED_0);
+		set_led (9, (phase & 0x2) ? LED_1 : LED_0);
+		set_led (10, (phase & 0x4) ? LED_1 : LED_0);
+		set_led (11, (phase & 0x8) ? LED_1 : LED_0);
+	}
+	i2155x_write_scrapad (BOOT_STATUS, phase);
+	if (phase < 0)
+		i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
+}
+
+int checkboard (void)
+{
+	show_startup_phase (1);
+	puts ("Board: PN62\n");
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	show_startup_phase (2);
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg (MEAR1);
+	emear1 = mpc824x_mpc107_getreg (EMEAR1);
+	mear1 = (mear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg (MEAR1, mear1);
+	mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices. We rely on auto-configuration.
+ */
+#ifndef CONFIG_PCI_PNP
+#error "CONFIG_PCI_PNP is not defined, please correct!"
+#endif
+
+struct pci_controller hose = {
+};
+
+void pci_init_board (void)
+{
+	show_startup_phase (4);
+	pci_mpc824x_init (&hose);
+
+	show_startup_phase (5);
+	i2155x_init ();
+	show_startup_phase (6);
+	am79c95x_init ();
+	show_startup_phase (7);
+}
+
+int misc_init_r (void)
+{
+	char str[20];
+	u8 mac[6];
+
+	show_startup_phase (8);
+	/*
+	 * Get serial number and ethernet addresses if not already defined
+	 * and update the board info structure and the environment.
+	 */
+	if (getenv ("serial#") == NULL &&
+		get_serial_number (str, strlen (str)) > 0) {
+		setenv ("serial#", str);
+	}
+	show_startup_phase (9);
+
+	if (!eth_getenv_enetaddr("ethaddr", mac)) {
+		get_mac_address(0, mac);
+		eth_setenv_enetaddr("ethaddr", mac);
+	}
+	show_startup_phase (10);
+
+#ifdef CONFIG_HAS_ETH1
+	if (!eth_getenv_enetaddr("eth1addr", mac)) {
+		get_mac_address(1, mac);
+		eth_setenv_enetaddr("eth1addr", mac);
+	}
+#endif /* CONFIG_HAS_ETH1 */
+	show_startup_phase (11);
+
+	/* Tell everybody that U-Boot is up and runnig */
+	i2155x_write_scrapad (0, 0x12345678);
+	return (0);
+}
+
+static int get_serial_number (char *string, int size)
+{
+	int i;
+	char c;
+
+	if (size < I2155X_VPD_SN_SIZE)
+		size = I2155X_VPD_SN_SIZE;
+	for (i = 0; i < (size - 1); i++) {
+		i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
+		if (c == '\0')
+			break;
+		string[i] = c;
+	}
+	string[i] = '\0';			/* make sure it's terminated */
+
+	return i;
+}
+
+static void get_mac_address(int id, u8 *mac)
+{
+	i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/pn62/pn62.h b/u-boot/board/pn62/pn62.h
new file mode 100644
index 0000000..f356a40
--- /dev/null
+++ b/u-boot/board/pn62/pn62.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PN62_H_
+#define _PN62_H_
+
+/*
+ * Definitions for the Intel Bridge 21554 or 21555.
+ */
+#define I2155X_VPD_ADDR		0xe6
+#define I2155X_VPD_DATA		0xe8
+
+#define I2155X_VPD_START	0x80
+#define I2155X_VPD_SN_START	0x80
+#define I2155X_VPD_SN_SIZE	0x10
+#define I2155X_VPD_MAC0_START	0x90
+#define I2155X_VPD_MAC1_START	0x96
+
+#define I2155X_SCRAPAD_ADDR	0xa8
+#define I2155X_SCRAPAD_MAX	8
+
+#define I2155X_BAR2_BASE	0x98
+#define I2155X_BAR3_BASE	0x9c
+#define I2155X_BAR4_BASE	0xa0
+
+#define I2155X_BAR2_SETUP	0xb0
+#define I2155X_BAR3_SETUP	0xb4
+#define I2155X_BAR4_SETUP	0xb8
+
+/*
+ * Interrupt request numbers
+ */
+#define PN62_IRQ_HOST		0x0
+#define PN62_IRQ_PLX9054	0x1
+#define PN62_IRQ_ETH0		0x2
+#define PN62_IRQ_ETH1		0x3
+#define PN62_IRQ_COM1		0x4
+#define PN62_IRQ_COM2		0x4
+
+/*
+ * Miscellaneous definitons.
+ */
+#define PN62_SMEM_DEFAULT	0x1f00000
+
+/*
+ * Definitions for boot protocol using Scratchpad registers.
+ */
+#define BOOT_DONE		0
+#define BOOT_DONE_CLEAR		0x00dead00
+#define BOOT_DONE_ERROR		0xbad0dead
+#define BOOT_DONE_U_BOOT	0x12345678
+#define BOOT_DONE_LINUX		0x87654321
+#define BOOT_CMD		1
+#define BOOT_CMD_MOVE		0x1
+#define BOOT_CMD_BOOT		0x2
+#define BOOT_DATA		2
+#define BOOT_PROTO		3
+#define BOOT_PROTO_READY	0x23456789
+#define BOOT_PROTO_CLEAR	0x00000000
+#define BOOT_STATUS		4
+
+/*
+ * LED Definitions:
+ */
+#define PN62_LED_BASE		0xff800300
+#define PN62_LED_MAX		12
+
+/*
+ * LED0 - 7 mounted on top of board, D1 - D8
+ * LED8 - 11 upper four LEDs on the front panel of the board.
+ */
+#define LED_0			0x00	/* OFF */
+#define LED_1			0x01	/* ON */
+#define LED_SLOW_CLOCK		0x02	/* SLOW 1Hz ish */
+#define LED_nSLOW_CLOCK		0x03	/* inverse of above */
+#define LED_WATCHDOG_OUT	0x06	/* Reset Watchdog level */
+#define LED_WATCHDOG_CLOCK	0x07	/* clock to watchdog */
+
+/*
+ * LED's currently setup in AMD79C973 device as the following:
+ * LED0 100Mbit
+ * LED1 LNKSE
+ * LED2 TX Activity
+ * LED3 RX Activity
+ */
+#define LED_E0_LED0		0x08	/* Ethernet Port 0 LED 0 */
+#define LED_E0_LED1		0x09	/* Ethernet Port 0 LED 1 */
+#define LED_E0_LED2		0x0A	/* Ethernet Port 0 LED 2 */
+#define LED_E0_LED3		0x0B	/* Ethernet Port 0 LED 3 */
+#define LED_E1_LED0		0x0C	/* Ethernet Port 1 LED 0 */
+#define LED_E1_LED1		0x0D	/* Ethernet Port 1 LED 1 */
+#define LED_E1_LED2		0x0E	/* Ethernet Port 1 LED 2 */
+#define LED_E1_LED3		0x0F	/* Ethernet Port 1 LED 3 */
+#define LED_STROBE0		0x10	/* Processor Strobe 0 */
+#define LED_STROBE1		0x11	/* Processor Strobe 1 */
+#define LED_STROBE2		0x12	/* Processor Strobe 2 */
+#define LED_STROBE3		0x13	/* Processor Strobe 3 */
+#define LED_STROBE4		0x14	/* Processor Strobe 4 */
+#define LED_STROBE5		0x15	/* Processor Strobe 5 */
+#define LED_STROBE6		0x16	/* Processor Strobe 6 */
+#define LED_STROBE7		0x17	/* Processor Strobe 7 */
+#define LED_HOST_STROBE0	0x18	/* Host strobe 0 */
+#define LED_HOST_STROBE1	0x19	/* Host strobe 1 */
+#define LED_HOST_STROBE2	0x1A	/* Host strobe 2 */
+#define LED_HOST_STROBE3	0x1B	/* Host strobe 3 */
+#define LED_HOST_STROBE4	0x1C	/* Host strobe 4 */
+#define LED_HOST_STROBE5	0x1D	/* Host strobe 5 */
+#define LED_HOST_STROBE6	0x1E	/* Host strobe 6 */
+#define LED_HOST_STROBE7	0x1F	/* Host strobe 7 */
+#define LED_MPC_INT0		0x20	/* MPC8240 INT 0 */
+#define LED_MPC_INT1		0x21	/* MPC8240 INT 1 */
+#define	LED_MPC_INT2		0x22	/* MPC8240 INT 2 */
+#define	LED_MPC_INT3		0x23	/* MPC8240 INT 3 */
+#define	LED_MPC_INT4		0x24	/* MPC8240 INT 4 */
+#define	LED_UART0_CS		0x25	/* UART 0 Chip Select */
+#define	LED_UART1_CS		0x26	/* UART 1 Chip Select */
+#define	LED_SRAM_CS		0x27	/* SRAM Chip Select */
+#define	LED_SRAM_WR		0x28	/* SRAM WR Signal */
+#define	LED_SRAM_RD		0x29	/* SRAM RD Signal */
+#define	LED_MPC_RCS0		0x2A	/* MPC8240 RCS0 Signal */
+#define	LED_S_PCI_FRAME		0x2B	/* Secondary PCI Frame Signal */
+#define	LED_MPC_CS0		0x2C	/* MPC8240 CS0 Signal */
+#define	LED_HOST_INT		0x2D	/* MPC8240 to Host Interrupt signal */
+#define LED_LAST_FUNCTION	LED_HOST_INT	/* last function */
+
+/*
+ * Forward declarations
+ */
+int  i2155x_init	 (void);
+void i2155x_write_scrapad(int idx, u32 val);
+u32  i2155x_read_scrapad (int idx);
+void i2155x_set_bar_base (int bar, u32 addr);
+int  i2155x_read_vpd	 (int offset, int size, unsigned char *data);
+
+int  am79c95x_init	 (void);
+
+void set_led		 (unsigned int number, unsigned int function);
+void fatal_error	 (unsigned int error_code);
+void show_startup_phase  (int phase);
+
+
+#endif /* _PN62_H_ */
diff --git a/u-boot/board/ppmc7xx/Makefile b/u-boot/board/ppmc7xx/Makefile
new file mode 100644
index 0000000..ff27a20
--- /dev/null
+++ b/u-boot/board/ppmc7xx/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= init.o
+
+COBJS	:= ppmc7xx.o pci.o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ppmc7xx/flash.c b/u-boot/board/ppmc7xx/flash.c
new file mode 100644
index 0000000..e724227
--- /dev/null
+++ b/u-boot/board/ppmc7xx/flash.c
@@ -0,0 +1,494 @@
+/*
+ * flash.c
+ * -------
+ *
+ * Flash programming routines for the Wind River PPMC 74xx/7xx
+ * based on flash.c from the TQM8260 board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+
+#define DWORD unsigned long long
+
+/* Local function prototypes */
+static int	write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
+static void	write_via_fpu (volatile DWORD* addr, DWORD* data);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	unsigned long msr;
+	DWORD cmd_reset = 0x00F000F000F000F0LL;
+
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		msr = get_msr ();
+		set_msr (msr | MSR_FP);
+
+		write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
+
+		set_msr (msr);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	int i;
+	unsigned long msr;
+	DWORD flashtest;
+	DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+							0x0090009000900090LL };
+
+	/* Enable FPU */
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
+
+	/* Write auto-select command sequence */
+	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
+	write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
+	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
+
+	/* Restore FPU */
+	set_msr (msr);
+
+	/* Read manufacturer ID */
+	flashtest = *(volatile DWORD*)baseaddr;
+	switch ((int)flashtest) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		/* No, faulty or unknown flash */
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);
+	}
+
+	/* Read device ID */
+	flashtest = *(volatile DWORD*)(baseaddr + 8);
+	switch ((long)flashtest) {
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00400000;
+		break;
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;
+		break;
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00800000;
+		break;
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00800000;
+		break;
+	case AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;
+	default:
+		/* Unknown flash type */
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);
+	}
+
+	if ((long)flashtest == AMD_ID_LV640U) {
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+	} else {
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+	size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned long msr;
+	DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+						   0x0080008000800080LL, 0x00AA00AA00AA00AALL,
+						   0x0055005500550055LL, 0x0030003000300030LL };
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Enable FPU */
+	msr = get_msr();
+	set_msr ( msr | MSR_FP );
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* Restore FPU */
+	set_msr (msr);
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
+				!= 0x0080008000800080LL )
+	{
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start;
+	unsigned long msr;
+	int flag, i;
+	DWORD data;
+	DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+						   0x00A000A000A000A0LL };
+
+	for (data = 0, i = 0; i < 8; i++)
+		data = (data << 8) + *pdata++;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(DWORD*)dest & data) != data) {
+		return (2);
+	}
+
+	/* Enable FPU */
+	msr = get_msr();
+	set_msr( msr | MSR_FP );
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
+	write_via_fpu ((DWORD*)dest, &data );
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* Restore FPU */
+	set_msr(msr);
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (*(volatile DWORD*)dest != data ) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (volatile DWORD* addr, DWORD* data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+	__asm__ __volatile__ ("eieio");
+}
diff --git a/u-boot/board/ppmc7xx/init.S b/u-boot/board/ppmc7xx/init.S
new file mode 100644
index 0000000..99a818a
--- /dev/null
+++ b/u-boot/board/ppmc7xx/init.S
@@ -0,0 +1,336 @@
+/*
+ * init.S
+ * ------
+ *
+ * Wind River PPMC 7xx/74xx init code.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ *
+ * NOTE: The following code was generated automatically by Workbench
+ *       from the ppmc7400_107.reg register file.
+ */
+
+#include <ppc_asm.tmpl>
+
+
+.globl board_asm_init
+board_asm_init:
+
+      lis    r4,0xFEC0
+      ori    r4,r4,0x0000
+      lis    r5,0xFEE0
+      ori    r5,r5,0x0000
+      lis    r3,0x8000          # ADDR_00
+      ori    r3,r3,0x0000
+      stwbrx    r3,0,r4
+      li     r3,0x1057          # VENDOR
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_02
+      ori    r3,r3,0x0002
+      stwbrx    r3,0,r4
+      li     r3,0x0004          # ID
+      li    r8, 0x2
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_04
+      ori    r3,r3,0x0004
+      stwbrx    r3,0,r4
+      li     r3,0x0006          # PCICMD
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_06
+      ori    r3,r3,0x0006
+      stwbrx    r3,0,r4
+      li     r3,0x00A0          # PCISTAT
+      li    r8, 0x2
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_08
+      ori    r3,r3,0x0008
+      stwbrx    r3,0,r4
+      li     r3,0x10            # REVID
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_09
+      ori    r3,r3,0x0009
+      stwbrx    r3,0,r4
+      li     r3,0x00            # PROGIR
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_0A
+      ori    r3,r3,0x000A
+      stwbrx    r3,0,r4
+      li     r3,0x00            # SUBCCODE
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_0B
+      ori    r3,r3,0x000B
+      stwbrx    r3,0,r4
+      li     r3,0x06            # PBCCR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_0C
+      ori    r3,r3,0x000C
+      stwbrx    r3,0,r4
+      li     r3,0x08            # PCLSR
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_0D
+      ori    r3,r3,0x000D
+      stwbrx    r3,0,r4
+      li     r3,0x00            # PLTR
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_0E
+      ori    r3,r3,0x000E
+      stwbrx    r3,0,r4
+      li     r3,0x00            # HEADTYPE
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_0F
+      ori    r3,r3,0x000F
+      stwbrx    r3,0,r4
+      li     r3,0x00            # BISTCTRL
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_10
+      ori    r3,r3,0x0010
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # LMBAR
+      ori    r3,r3,0x0008
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_14
+      ori    r3,r3,0x0014
+      stwbrx    r3,0,r4
+      lis    r3,0xF000          # PCSRBAR
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_3C
+      ori    r3,r3,0x003C
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ILR
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_3D
+      ori    r3,r3,0x003D
+      stwbrx    r3,0,r4
+      li     r3,0x01            # INTPIN
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_3E
+      ori    r3,r3,0x003E
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MIN_GNT
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_3F
+      ori    r3,r3,0x003F
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MAX_LAT
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_40
+      ori    r3,r3,0x0040
+      stwbrx    r3,0,r4
+      li     r3,0x00            # BUSNB
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_41
+      ori    r3,r3,0x0041
+      stwbrx    r3,0,r4
+      li     r3,0x00            # SBUSNB
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_46
+      ori    r3,r3,0x0046
+      stwbrx    r3,0,r4
+#      li     r3,0xE080          # PCIARB
+      li     r3,-0x1F80          # PCIARB
+      li    r8, 0x2
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_70
+      ori    r3,r3,0x0070
+      stwbrx    r3,0,r4
+      li     r3,0x0000          # PMCR1
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_72
+      ori    r3,r3,0x0072
+      stwbrx    r3,0,r4
+      li     r3,0xC0            # PMCR2
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_73
+      ori    r3,r3,0x0073
+      stwbrx    r3,0,r4
+      li     r3,0xEF            # ODCR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_74
+      ori    r3,r3,0x0074
+      stwbrx    r3,0,r4
+      li     r3,0x7D00          # CLKDCR
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_76
+      ori    r3,r3,0x0076
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MDCR
+      stb    r3,0x2(r5)
+      lis    r6,0xFCE0
+      ori    r6,r6,0x0000       # r6 is the EUMBAR Base Address
+      lis    r3,0x8000          # ADDR_78
+      ori    r3,r3,0x0078
+      stwbrx    r3,0,r4
+      lis    r3,0xFCE0          # EUMBBAR
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_80
+      ori    r3,r3,0x0080
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # MSADDR1
+      ori    r3,r3,0x4000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_84
+      ori    r3,r3,0x0084
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # MSADDR2
+      ori    r3,r3,0xFFFF
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_88
+      ori    r3,r3,0x0088
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EMSADDR1
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_8C
+      ori    r3,r3,0x008C
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EMSADDR2
+      ori    r3,r3,0x0303
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_90
+      ori    r3,r3,0x0090
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # EMEADDR1
+      ori    r3,r3,0x7F3F
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_94
+      ori    r3,r3,0x0094
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # EMEADDR2
+      ori    r3,r3,0xFFFF
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_98
+      ori    r3,r3,0x0098
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EXTEMEM1
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_9C
+      ori    r3,r3,0x009C
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EXTEMEM2
+      ori    r3,r3,0x0303
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_A0
+      ori    r3,r3,0x00A0
+      stwbrx    r3,0,r4
+      li     r3,0x03            # MEMBNKEN
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_A3
+      ori    r3,r3,0x00A3
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MEMPMODE
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_B8
+      ori    r3,r3,0x00B8
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ECCCNT
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_B9
+      ori    r3,r3,0x00B9
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ECCTRG
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_C0
+      ori    r3,r3,0x00C0
+      stwbrx    r3,0,r4
+      li     r3,0xFF            # ERRENR1
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_C1
+      ori    r3,r3,0x00C1
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ERRDR1
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_C3
+      ori    r3,r3,0x00C3
+      stwbrx    r3,0,r4
+      li     r3,0x50            # IPBESR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_C4
+      ori    r3,r3,0x00C4
+      stwbrx    r3,0,r4
+      li     r3,0xBF            # ERRENR2
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_C5
+      ori    r3,r3,0x00C5
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ERRDR2
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_C7
+      ori    r3,r3,0x00C7
+      stwbrx    r3,0,r4
+      li     r3,0x00            # PCIBESR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_C8
+      ori    r3,r3,0x00C8
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # BERRADDR
+      ori    r3,r3,0xE0FE
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_E0
+      ori    r3,r3,0x00E0
+      stwbrx    r3,0,r4
+      li     r3,0xC0            # AMBOR
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_F4
+      ori    r3,r3,0x00F4
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # MCCR2
+      ori    r3,r3,0x020C
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_F8
+      ori    r3,r3,0x00F8
+      stwbrx    r3,0,r4
+      lis    r3,0x0230          # MCCR3
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_FC
+      ori    r3,r3,0x00FC
+      stwbrx    r3,0,r4
+      lis    r3,0x2532          # MCCR4
+      ori    r3,r3,0x2220
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_F0
+      ori    r3,r3,0x00F0
+      stwbrx    r3,0,r4
+      lis    r3,0xFFC8          # MCCR1
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_A8
+      ori    r3,r3,0x00A8
+      stwbrx    r3,0,r4
+      lis    r3,0xFF14          # PICR1
+      ori    r3,r3,0x1CC8
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_AC
+      ori    r3,r3,0x00AC
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # PICR2
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+
+      blr
diff --git a/u-boot/board/ppmc7xx/pci.c b/u-boot/board/ppmc7xx/pci.c
new file mode 100644
index 0000000..2948531
--- /dev/null
+++ b/u-boot/board/ppmc7xx/pci.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
+	CONFIG_SYS_PCI_MEMORY_SIZE,
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/u-boot/board/ppmc7xx/ppmc7xx.c b/u-boot/board/ppmc7xx/ppmc7xx.c
new file mode 100644
index 0000000..432d366
--- /dev/null
+++ b/u-boot/board/ppmc7xx/ppmc7xx.c
@@ -0,0 +1,112 @@
+/*
+ * ppmc7xx.c
+ * ---------
+ *
+ * Main board-specific routines for Wind River PPMC 7xx/74xx board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+
+
+/* Define some MPC107 (memory controller) registers */
+#define MPC107_EUMB_GCR         0xfce41020
+#define MPC107_EUMB_IACKR       0xfce600a0
+
+
+/* Function prototypes */
+extern void _start(void);
+
+
+/*
+ * initdram()
+ *
+ * This function normally initialises the (S)DRAM of the system. For this board
+ * the SDRAM was already initialised by board_asm_init (see init.S) so we just
+ * return the size of RAM.
+ */
+phys_size_t initdram( int board_type )
+{
+    return CONFIG_SYS_SDRAM_SIZE;
+}
+
+
+/*
+ * after_reloc()
+ *
+ * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
+ * us an opportunity to do some additional setup before the rest of the system
+ * is initialised. We don't need to do anything, so we just call board_init_r()
+ * which should never return.
+ */
+void after_reloc( ulong dest_addr, gd_t* gd )
+{
+	/* Jump to the main U-Boot board init code */
+	board_init_r( gd, dest_addr );
+}
+
+
+/*
+ * checkboard()
+ *
+ * We could do some board level checks here, such as working out what version
+ * it is, but for this board we simply display it's name (on the console).
+ */
+int checkboard( void )
+{
+    puts( "Board: Wind River PPMC 7xx/74xx\n" );
+    return 0;
+}
+
+
+/*
+ * misc_init_r
+ *
+ * Used for other setup which needs to be done late in the bring-up phase.
+ */
+int misc_init_r( void )
+{
+	/* Reset the EPIC and clear pending interrupts */
+	out32r(MPC107_EUMB_GCR, 0xa0000000);
+	while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
+	out32r( MPC107_EUMB_GCR, 0x20000000 );
+	while( in32r( MPC107_EUMB_IACKR ) != 0xff );
+
+	/* Enable the I-Cache */
+	icache_enable();
+
+	return 0;
+}
+
+
+/*
+ * do_reset()
+ *
+ * Shell command to reset the board.
+ */
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf( "Resetting...\n" );
+
+	/* Disabe and invalidate cache */
+	icache_disable();
+	dcache_disable();
+
+	/* Jump to cold reset point (in RAM) */
+	_start();
+
+	/* Should never get here */
+	while(1)
+		;
+
+	return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/ppmc8260/Makefile b/u-boot/board/ppmc8260/Makefile
new file mode 100644
index 0000000..0141ea6
--- /dev/null
+++ b/u-boot/board/ppmc8260/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ppmc8260.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ppmc8260/ppmc8260.c b/u-boot/board/ppmc8260/ppmc8260.c
new file mode 100644
index 0000000..bf0188c
--- /dev/null
+++ b/u-boot/board/ppmc8260/ppmc8260.c
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_A1:L1TSYNC */
+	/* PA6  */ {   1,   0,   0,   1,   0,   0   }, /* TDN_A1:L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_A1:L1CLK0 */
+	/* PB15 */ {   1,   0,   0,   1,   0,   1   }, /* /FETHRST */
+	/* PB14 */ {   1,   0,   0,   1,   0,   0   }, /* FETHDIS */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_B1:L1CLK0 */
+	/* PB11 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1TXD */
+	/* PB10 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1RXD */
+	/* PB9  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1TSYNC */
+	/* PB8  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1RSYNC */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
+	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* CLK4 */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   1,   1,   0,   0,   0,   0   }, /* CLK7 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   1,   0,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* PC22 */
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC23 */
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[0] */
+	/* PC14 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[0] */
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[1] */
+	/* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[1] */
+	/* PC11 */ {   1,   1,   0,   1,   0,   0   }, /* TDM_D1:L1CLK0 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[2]*/
+	/* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[2] */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DACK */
+	/* PC2  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DONE */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DREQ */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DREQ */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   0,   0,   0,   0,   0   }, /* PD31 */
+	/* PD30 */ {   0,   0,   0,   0,   0,   0   }, /* PD30 */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[3] */
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_C1:L1RSYNC */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1TXD */
+	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1RXD */
+	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1TSYNC */
+	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1RSYNC*/
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1:TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1:RXD */
+	/* PD7  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1:SMSYN */
+	/* PD6  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DACK */
+	/* PD5  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DONE */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Wind River PPMC8260\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0xff;
+	volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE);
+	volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE);
+	ulong psdmr = CONFIG_SYS_PSDMR;
+	volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE);
+	ulong lsdmr = CONFIG_SYS_LSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr0++ = c;
+	*ramaddr1++ = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr0++ = c;
+		*ramaddr1++ = c;
+	}
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110);
+	ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110);
+	*ramaddr0 = c;
+	*ramaddr1 = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr0 = c;
+	*ramaddr1 = c;
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
+	*ramaddr2++ = c;
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr2++ = c;
+	}
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
+	*ramaddr2++ = c;
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr2 = c;
+#endif
+
+	/* return total ram size */
+	return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+#ifdef CONFIG_SYS_LED_BASE
+	uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
+	uchar ss;
+	uchar tmp[64];
+	int res;
+
+	if ((ds != 0) && (ds != 0xff)) {
+		res = getenv_f("ethaddr", (char *)tmp, sizeof (tmp));
+		if (res > 0) {
+			ss = ((ds >> 4) & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[15] = ss;
+
+			ss = (ds & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[16] = ss;
+
+			tmp[17] = '\0';
+			setenv ("ethaddr", (char *)tmp);
+			/* set the led to show the address */
+			*((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
+		}
+	}
+#endif /* CONFIG_SYS_LED_BASE */
+	return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/u-boot/board/ppmc8260/strataflash.c b/u-boot/board/ppmc8260/strataflash.c
new file mode 100644
index 0000000..cc91627
--- /dev/null
+++ b/u-boot/board/ppmc8260/strataflash.c
@@ -0,0 +1,752 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CONFIG_SYS_FLASH_BASE;
+	size = 0;
+
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CONFIG_SYS_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+	/* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : " "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+		        retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/u-boot/board/prodrive/alpr/Makefile b/u-boot/board/prodrive/alpr/Makefile
new file mode 100644
index 0000000..66ff738
--- /dev/null
+++ b/u-boot/board/prodrive/alpr/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o fpga.o nand.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/prodrive/alpr/alpr.c b/u-boot/board/prodrive/alpr/alpr.c
new file mode 100644
index 0000000..1784982
--- /dev/null
+++ b/u-boot/board/prodrive/alpr/alpr.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <asm/ppc4xx-emac.h>
+#include <miiphy.h>
+#include <asm/processor.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int alpr_fpga_init(void);
+
+int board_early_init_f (void)
+{
+	/*-------------------------------------------------------------------------
+	 * Initialize EBC CONFIG
+	 *-------------------------------------------------------------------------*/
+	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (UIC1PR, 0xfffffe03);	/* per manual */
+	mtdcr (UIC1TR, 0x01c00000);	/* per manual */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC0SR, 0xfc000000); /* clear all */
+	mtdcr (UIC0ER, 0x00000000); /* disable all */
+	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000); /* */
+	mtdcr (UIC0TR, 0x00000000); /* */
+	mtdcr (UIC0VR, 0x00000001); /* */
+
+	/* Setup shutdown/SSD empty interrupt as inputs */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
+
+	/* Setup GPIO/IRQ multiplexing */
+	mtsdr(SDR0_PFC0, 0x01a33e00);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	unsigned short reg;
+
+	/*
+	 * Configure LED's of both Marvell 88E1111 PHY's
+	 *
+	 * This has to be done after the 4xx ethernet driver is loaded,
+	 * so "last_stage_init()" is the right place.
+	 */
+	miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
+	reg |= 0x0001;
+	miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
+	miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
+	reg |= 0x0001;
+	miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
+
+	return 0;
+}
+
+static int board_rev(void)
+{
+	/* Setup as input */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
+
+	return (in32(GPIO0_IR) >> 16) & 0x3;
+}
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: ALPR");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	printf(" (Rev. %d)\n", board_rev());
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Override weak pci_pre_init()
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+	if (__pci_pre_init(hose) == 0)
+		return 0;
+
+	/* FPGA Init */
+	alpr_fpga_init();
+
+	return 1;
+}
+
+/*************************************************************************
+ * Override weak is_pci_host()
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+static void wait_for_pci_ready(void)
+{
+	/*
+	 * Configure EREADY as input
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
+	udelay(1000);
+
+	for (;;) {
+		if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
+			return;
+	}
+
+}
+
+int is_pci_host(struct pci_controller *hose)
+{
+	wait_for_pci_ready();
+	return 1;		/* return 1 for host controller */
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 PCI Master configuration.
+	  | Map PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r( PCIL0_POM0SA, 0 ); /* disable */
+	out32r( PCIL0_POM1SA, 0 ); /* disable */
+	out32r( PCIL0_POM2SA, 0 ); /* disable */
+
+	out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_POM0LAH, 0x00000003);	/* PMM0 Local Address */
+	out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_POM0PCIAH, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
+
+	out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIL0_POM1LAH, 0x00000003);	/* PMM0 Local Address */
+	out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_POM1PCIAH, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
+}
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
diff --git a/u-boot/board/prodrive/alpr/config.mk b/u-boot/board/prodrive/alpr/config.mk
new file mode 100644
index 0000000..7be81f3
--- /dev/null
+++ b/u-boot/board/prodrive/alpr/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/prodrive/alpr/fpga.c b/u-boot/board/prodrive/alpr/fpga.c
new file mode 100644
index 0000000..93f2449
--- /dev/null
+++ b/u-boot/board/prodrive/alpr/fpga.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Altera FPGA configuration support for the ALPR computer from prodrive
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#ifdef FPGA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+static unsigned long regval;
+
+#define SET_GPIO_REG_0(reg, bit) {				\
+		regval = in32(reg);				\
+		regval &= ~(0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
+
+#define SET_GPIO_REG_1(reg, bit) {				\
+		regval = in32(reg);				\
+		regval |= (0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
+
+#define	SET_GPIO_0(bit)		SET_GPIO_REG_0(GPIO0_OR, bit)
+#define	SET_GPIO_1(bit)		SET_GPIO_REG_1(GPIO0_OR, bit)
+
+#define FPGA_PRG		(0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
+#define FPGA_CONFIG		(0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
+#define FPGA_DATA		(0x80000000 >> CONFIG_SYS_GPIO_DATA)
+#define FPGA_CLK		(0x80000000 >> CONFIG_SYS_GPIO_CLK)
+#define OLD_VAL			(FPGA_PRG | FPGA_CONFIG)
+
+#define SET_FPGA(data)		out32(GPIO0_OR, data)
+
+#define FPGA_WRITE_1 {							\
+		SET_FPGA(OLD_VAL | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 {							\
+		SET_FPGA(OLD_VAL | 0        | 0        );   /* set data to 0  */ \
+		SET_FPGA(OLD_VAL | FPGA_CLK | 0        );}  /* set data to 1  */
+
+/* Plattforminitializations */
+/* Here we have to set the FPGA Chain */
+/* PROGRAM_PROG_EN	= HIGH */
+/* PROGRAM_SEL_DPR	= LOW */
+int fpga_pre_fn (int cookie)
+{
+	unsigned long	reg;
+
+	reg = in32(GPIO0_IR);
+	/* Enable the FPGA Chain */
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
+	SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
+
+	/* initialize the GPIO Pins */
+	/* output */
+	SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
+
+	/* output */
+	SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
+
+	/* First we set STATUS to 0 then as an input */
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+
+	/* output */
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
+
+	/* input */
+	SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
+
+	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
+	return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int fpga_config_fn (int assert_config, int flush, int cookie)
+{
+	if (assert_config) {
+		SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
+	} else {
+		SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
+	}
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int fpga_status_fn (int cookie)
+{
+	unsigned long	reg;
+
+	reg = in32(GPIO0_IR);
+	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
+		PRINTF("STATUS = HIGH\n");
+		return FPGA_FAIL;
+	}
+	PRINTF("STATUS = LOW\n");
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int fpga_done_fn (int cookie)
+{
+	unsigned long	reg;
+	reg = in32(GPIO0_IR);
+	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
+		PRINTF("CONF_DON = HIGH\n");
+		return FPGA_FAIL;
+	}
+	PRINTF("CONF_DON = LOW\n");
+	return FPGA_SUCCESS;
+}
+
+/* writes the complete buffer to the FPGA
+   writing the complete buffer in one function is much faster,
+   then calling it for every bit */
+int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	unsigned char *data = (unsigned char *) buf;
+	unsigned char val=0;
+	int		i;
+	int len_40 = len / 40;
+
+	while (bytecount < len) {
+		val = data[bytecount++];
+		i = 8;
+		do {
+			if (val & 0x01) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			val >>= 1;
+			i --;
+		} while (i > 0);
+
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+		if (bytecount % len_40 == 0) {
+			putc ('.');		/* let them know we are alive */
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc ())
+				return FPGA_FAIL;
+#endif
+		}
+#endif
+	}
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int fpga_abort_fn (int cookie)
+{
+	SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int fpga_post_fn (int cookie)
+{
+	return fpga_abort_fn (cookie);
+}
+
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ */
+Altera_CYC2_Passive_Serial_fns fpga_fns = {
+	fpga_pre_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_write_fn,
+	fpga_abort_fn,
+	fpga_post_fn
+};
+
+Altera_desc fpga[CONFIG_FPGA_COUNT] = {
+	{Altera_CYC2,
+	 passive_serial,
+	 Altera_EP2C35_SIZE,
+	 (void *) &fpga_fns,
+	 NULL,
+	 0}
+};
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int alpr_fpga_init (void)
+{
+	int i;
+
+	PRINTF ("%s:%d: Initialize FPGA interface\n", __FUNCTION__, __LINE__);
+	fpga_init ();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_altera, &fpga[i]);
+	}
+	return 1;
+}
+
+#endif
diff --git a/u-boot/board/prodrive/alpr/init.S b/u-boot/board/prodrive/alpr/init.S
new file mode 100644
index 0000000..d9961dd
--- /dev/null
+++ b/u-boot/board/prodrive/alpr/init.S
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+#ifdef CONFIG_4xx_DCACHE
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
+#else
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
+#endif
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+
+	/* PCI */
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
+
+	/* NAND */
+	tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
+	tlbtab_end
diff --git a/u-boot/board/prodrive/alpr/nand.c b/u-boot/board/prodrive/alpr/nand.c
new file mode 100644
index 0000000..b18c96b
--- /dev/null
+++ b/u-boot/board/prodrive/alpr/nand.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <asm/processor.h>
+#include <nand.h>
+
+struct alpr_ndfc_regs {
+	u8 cmd[4];
+	u8 addr_wait;
+	u8 term;
+	u8 dummy;
+	u8 dummy2;
+	u8 data;
+};
+
+static u8 hwctl;
+static struct alpr_ndfc_regs *alpr_ndfc = NULL;
+
+#define readb(addr)	(u8)(*(volatile u8 *)(addr))
+#define writeb(d,addr)	*(volatile u8 *)(addr) = ((u8)(d))
+
+/*
+ * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices.  The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately.  We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access.
+ *
+ * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
+ */
+static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
+		if ( (ctrl & NAND_NCE) != NAND_NCE)
+			writeb(0x00, &(alpr_ndfc->term));
+	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static u_char alpr_nand_read_byte(struct mtd_info *mtd)
+{
+	return readb(&(alpr_ndfc->data));
+}
+
+static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	struct nand_chip *nand = mtd->priv;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (hwctl & 0x1)
+			 /*
+			  * IO_ADDR_W used as CMD[i] reg to support multiple NAND
+			  * chips.
+			  */
+			writeb(buf[i], nand->IO_ADDR_W);
+		else if (hwctl & 0x2)
+			writeb(buf[i], &(alpr_ndfc->addr_wait));
+		else
+			writeb(buf[i], &(alpr_ndfc->data));
+	}
+}
+
+static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		buf[i] = readb(&(alpr_ndfc->data));
+	}
+}
+
+static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != readb(&(alpr_ndfc->data)))
+			return i;
+
+	return 0;
+}
+
+static int alpr_nand_dev_ready(struct mtd_info *mtd)
+{
+	volatile u_char val;
+
+	/*
+	 * Blocking read to wait for NAND to be ready
+	 */
+	val = readb(&(alpr_ndfc->addr_wait));
+
+	/*
+	 * Return always true
+	 */
+	return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	/* Reference hardware control function */
+	nand->cmd_ctrl  = alpr_nand_hwcontrol;
+	nand->read_byte  = alpr_nand_read_byte;
+	nand->write_buf  = alpr_nand_write_buf;
+	nand->read_buf   = alpr_nand_read_buf;
+	nand->verify_buf = alpr_nand_verify_buf;
+	nand->dev_ready  = alpr_nand_dev_ready;
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/prodrive/common/flash.c b/u-boot/board/prodrive/common/flash.c
new file mode 100644
index 0000000..c42fa83
--- /dev/null
+++ b/u-boot/board/prodrive/common/flash.c
@@ -0,0 +1,560 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*
+ * Functions
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("ST ");			break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_SST020:	printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CONFIG_SYS_FLASH_READ0];
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
+		info->flash_id += FLASH_SST020;
+		info->sector_count = 64;
+		info->size = 0x00040000;
+		break;				/* => 256 kB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
+		info->flash_id += FLASH_SST040;
+		info->sector_count = 128;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00001000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+
+				/* re-enable interrupts if necessary */
+				if (flag) {
+					enable_interrupts();
+					flag = 0;
+				}
+
+				/* data polling for D7 */
+				start = get_timer (0);
+				while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+				       (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+						return (1);
+				}
+			} else {
+				if (sect == s_first) {
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				}
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			}
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i)
+			data = (data << 8) | *src++;
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *)cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/prodrive/common/fpga.c b/u-boot/board/prodrive/common/fpga.c
new file mode 100644
index 0000000..14bff07
--- /dev/null
+++ b/u-boot/board/prodrive/common/fpga.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001-2004
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define FPGA_PRG		CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/
+#define FPGA_CLK		CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output)    */
+#define FPGA_DATA		CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output)  */
+#define FPGA_DONE		CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input)   */
+#define FPGA_INIT		CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input)   */
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+
+#ifndef OLD_VAL
+# define OLD_VAL		0
+#endif
+
+#if 0 /* test-only */
+#define FPGA_WRITE_1 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set clock to 0 */ \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set clock to 0 */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | 0        );  /* set data to 0  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0        );  /* set clock to 1 */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+#else
+#define FPGA_WRITE_1 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | 0        );   /* set data to 0  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0        );}  /* set data to 1  */
+#endif
+
+static int fpga_boot(unsigned char *fpgadata, int size)
+{
+	int i,index,len;
+	int count;
+	int j;
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = fpgadata[index];
+		DBG("FPGA: %s\n", &(fpgadata[index+1]));
+		index += len+3;
+	}
+
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
+		    (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
+			break; /* preamble found */
+		else
+			index++;
+	}
+
+	DBG("FPGA: configdata starts at position 0x%x\n",index);
+	DBG("FPGA: length of fpga-data %d\n", size-index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);            /* set pins to high */
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA(0 | FPGA_CLK | FPGA_DATA);             /* set prog active */
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (FPGA_INIT_STATE) {
+		udelay(1000); /* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	/* deassert PROGRAM* */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);           /* set prog inactive */
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(FPGA_INIT_STATE)) {
+		udelay(1000); /* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	DBG("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i=index; i<size; i++) {
+		for (j=0; j<8; j++) {
+			if ((fpgadata[i] & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			fpgadata[i] <<= 1;
+		}
+	}
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(FPGA_DONE_STATE)) {
+		udelay(1000); /* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/u-boot/board/prodrive/p3mx/64460.h b/u-boot/board/prodrive/p3mx/64460.h
new file mode 100644
index 0000000..8bb0ebf
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/64460.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64460.
+ */
+
+#ifndef __64460_H__
+#define __64460_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64460_H__ */
diff --git a/u-boot/board/prodrive/p3mx/Makefile b/u-boot/board/prodrive/p3mx/Makefile
new file mode 100644
index 0000000..59dc27d
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../Marvell/common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	= misc.o
+COBJS	= $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
+		../../Marvell/common/i2c.o ../../Marvell/common/memory.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/prodrive/p3mx/eth.h b/u-boot/board/prodrive/p3mx/eth.h
new file mode 100644
index 0000000..aab32d2
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/u-boot/board/prodrive/p3mx/misc.S b/u-boot/board/prodrive/p3mx/misc.S
new file mode 100644
index 0000000..233fd83
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/misc.S
@@ -0,0 +1,245 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../../Marvell/include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CONFIG_SYS_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
+	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
+	rlwinm  r3, r3, 16, 16, 31
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTEGRATED_SRAM_BASE_ADDR
+	stwbrx  r3, r5, r4
+
+2:	lwbrx	r6, r5, r4
+	cmp	cr0, r3, r6
+	bne	2b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
diff --git a/u-boot/board/prodrive/p3mx/mpsc.c b/u-boot/board/prodrive/p3mx/mpsc.c
new file mode 100644
index 0000000..cc05b45
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/mpsc.c
@@ -0,0 +1,1013 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../../Marvell/include/memory.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+	/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+	/*  Enable MPSC-Window0 for DRAM Bank 0 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(0),
+				   memoryGetBankSize(0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+	/*  Enable MPSC-Window1 for DRAM Bank 1 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64460_SDMA_DRAM_CS_1_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(1),
+				   memoryGetBankSize(1)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+	/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64460_SDMA_DRAM_CS_2_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(2),
+				   memoryGetBankSize(2)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+	/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64460_SDMA_DRAM_CS_3_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(3),
+				   memoryGetBankSize(3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+	/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+	/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+	/* Setup MPSC internal address space base address	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
+
+	/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+	/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64460 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/u-boot/board/prodrive/p3mx/mpsc.h b/u-boot/board/prodrive/p3mx/mpsc.h
new file mode 100644
index 0000000..aa0f862
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../../Marvell/include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/u-boot/board/prodrive/p3mx/mv_eth.c b/u-boot/board/prodrive/p3mx/mv_eth.c
new file mode 100644
index 0000000..fac7633
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/mv_eth.c
@@ -0,0 +1,3344 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ 3 the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <miiphy.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* PHY DFCDL Registers */
+#define ETH_PHY_DFCDL_CONFIG0_REG	0x2100
+#define ETH_PHY_DFCDL_CONFIG1_REG	0x2104
+#define ETH_PHY_DFCDL_ADDR_REG		0x2110
+#define ETH_PHY_DFCDL_DATA0_REG		0x2114
+
+#define PHY_AUTONEGOTIATE_TIMEOUT	4000	/* 4000 ms autonegotiate timeout */
+#define PHY_UPDATE_TIMEOUT		10000
+
+#undef MV64460_CHECKSUM_OFFLOAD
+/*************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64460_RX_QUEUE_FILL_ON_TASK
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64460_INTERNAL_SRAM_SIZE	_256K
+#define EXTRA_BYTES 32
+#define WRAP	   ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64460_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64460 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+/* Static function declarations */
+static int mv64460_eth_real_open (struct eth_device *eth);
+static int mv64460_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64460_eth_update_stat (struct eth_device *dev);
+bool db64460_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64460_eth_receive (struct eth_device *dev);
+
+int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+int mv_miiphy_read(const char *devname, unsigned char phy_addr,
+		   unsigned char phy_reg, unsigned short *value);
+int mv_miiphy_write(const char *devname, unsigned char phy_addr,
+		    unsigned char phy_reg, unsigned short value);
+
+int phy_setup_aneg (char *devname, unsigned char addr);
+
+#ifndef	 UPDATE_STATS_BY_SOFTWARE
+static void mv64460_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64460_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+/**********************************************************************
+ * mv64460_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+void mv64460_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64460_eth
+ *
+ **********************************************************************/
+int db64460_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64460_eth_start (dev));
+}
+
+int db64460_eth_poll (struct eth_device *dev)
+{
+	return mv64460_eth_receive (dev);
+}
+
+int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64460_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64460_eth_disable (struct eth_device *dev)
+{
+	mv64460_eth_stop (dev);
+}
+
+#define DFCDL(write,read)   ((write << 6) | read)
+unsigned int  ethDfcdls[] = {
+	DFCDL(0,0),	DFCDL(1,1),	DFCDL(2,2),	DFCDL(3,3),
+	DFCDL(4,4),	DFCDL(5,5),	DFCDL(6,6),	DFCDL(7,7),
+	DFCDL(8,8),	DFCDL(9,9),	DFCDL(10,10),	DFCDL(11,11),
+	DFCDL(12,12),	DFCDL(13,13),	DFCDL(14,14),	DFCDL(15,15),
+	DFCDL(16,16),	DFCDL(17,17),	DFCDL(18,18),	DFCDL(19,19),
+	DFCDL(20,20),	DFCDL(21,21),	DFCDL(22,22),	DFCDL(23,23),
+	DFCDL(24,24),	DFCDL(25,25),	DFCDL(26,26),	DFCDL(27,27),
+	DFCDL(28,28),	DFCDL(29,29),	DFCDL(30,30),	DFCDL(31,31),
+	DFCDL(32,32),	DFCDL(33,33),	DFCDL(34,34),	DFCDL(35,35),
+	DFCDL(36,36),	DFCDL(37,37),	DFCDL(38,38),	DFCDL(39,39),
+	DFCDL(40,40),	DFCDL(41,41),	DFCDL(42,42),	DFCDL(43,43),
+	DFCDL(44,44),	DFCDL(45,45),	DFCDL(46,46),	DFCDL(47,47),
+	DFCDL(48,48),	DFCDL(49,49),	DFCDL(50,50),	DFCDL(51,51),
+	DFCDL(52,52),	DFCDL(53,53),	DFCDL(54,54),	DFCDL(55,55),
+	DFCDL(56,56),	DFCDL(57,57),	DFCDL(58,58),	DFCDL(59,59),
+	DFCDL(60,60),	DFCDL(61,61),	DFCDL(62,62),	DFCDL(63,63),
+};
+
+void mv_eth_phy_init (void)
+{
+	int i;
+
+	MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0);
+
+	for (i = 0; i < 64; i++) {
+		MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]);
+	}
+
+	MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000);
+}
+
+void mv6446x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	/* P3M750 only
+	 * Set RGMII clock drives strength
+	 */
+	temp = MV_REG_READ(0x20A0);
+	temp |= 0x04000080;
+	MV_REG_WRITE(0x20A0, temp);
+
+	mv_eth_phy_init();
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+		case 1:
+			s = "eth1addr";
+			break;
+		case 2:
+			s = "eth2addr";
+			break;
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64460_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64460_eth_transmit;
+		dev->recv = (void *) db64460_eth_poll;
+
+		ethernet_private = calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *)ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private = calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64460_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64460_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+		case 1:
+			s = "eth1addr";
+			break;
+		case 2:
+			s = "eth2addr";
+			break;
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64460_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64460_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+		miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write);
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64460_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64460_eth_open (struct eth_device *dev)
+{
+	return (mv64460_eth_real_open (dev));
+}
+
+/* Helper function for mv64460_eth_open */
+static int mv64460_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status;
+	ushort reg_short;
+	int speed;
+	int duplex;
+	int i;
+	int reg;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x1 + (port_num << 1);
+	reg = ethernet_private->port_phy_addr;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+
+#if defined(CONFIG_PHY_RESET)
+	/*
+	 * Reset the phy, only if its the first time through
+	 * otherwise, just check the speeds & feeds
+	 */
+	if (port_private->first_init == 0) {
+		port_private->first_init = 1;
+		ethernet_phy_reset (port_num);
+
+		/* Start/Restart autonegotiation */
+		phy_setup_aneg (dev->name, reg);
+		udelay (1000);
+	}
+#endif /* defined(CONFIG_PHY_RESET) */
+
+	miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
+
+	/*
+	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+	 */
+	if ((reg_short & BMSR_ANEGCAPABLE)
+	    && !(reg_short & BMSR_ANEGCOMPLETE)) {
+		puts ("Waiting for PHY auto negotiation to complete");
+		i = 0;
+		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
+			/*
+			 * Timeout reached ?
+			 */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts (" TIMEOUT !\n");
+				break;
+			}
+
+			if ((i++ % 1000) == 0) {
+				putc ('.');
+			}
+			udelay (1000);	/* 1 ms */
+			miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
+
+		}
+		puts (" done\n");
+		udelay (500000);	/* another 500 ms (results in faster booting) */
+	}
+
+	speed = miiphy_speed (dev->name, reg);
+	duplex = miiphy_duplex (dev->name, reg);
+
+	printf ("ENET Speed is %d Mbps - %s duplex connection\n",
+		(int) speed, (duplex == HALF) ? "HALF" : "FULL");
+
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+static int mv64460_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64460_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64460_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64460_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64460_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64460_eth_stop */
+
+static int mv64460_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64460_eth_free_tx_rings (dev);
+	mv64460_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef	 UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64460_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+/**********************************************************************
+ * mv64460_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *	   dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		return 1;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+	return 0;	/* success */
+}
+
+/**********************************************************************
+ * mv64460_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *	   max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64460_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) {
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+			if(pkt_info.buf_ptr != 0){
+				for(i=0; i < pkt_info.byte_cnt; i++){
+					if((i % 4) == 0){
+						printf("\n0x");
+					}
+					printf("%02x", ((char*)pkt_info.buf_ptr)[i]);
+				}
+				printf("\n");
+			}
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf ("RX: pkt_info.buf_ptr =	%x\n", pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX: Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64460_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64460_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64460_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+/**********************************************************************
+ * mv64460_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef	 UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64460_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64460_eth_start (struct eth_device *dev)
+{
+	return (mv64460_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *	 This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *	 Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *	 port_num	      User Ethernet port number.
+ *	 port_phy_addr		    User PHY address of Ethernet port.
+ *	 port_mac_addr[6]	    User defined port MAC address.
+ *	 port_config	      User port configuration value.
+ *	 port_config_extend    User port config extend value.
+ *	 port_sdma_config      User port SDMA config value.
+ *	 port_serial_control   User port serial control value.
+ *	 *port_virt_to_phys ()	User function to cast virtual addr to CPU bus addr.
+ *	 *port_private	      User scratch pad for user specific data structures.
+ *
+ *	 This driver introduce a set of default values:
+ *	 PORT_CONFIG_VALUE	     Default port configuration value
+ *	 PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *	 PORT_SDMA_CONFIG_VALUE	     Default sdma control value
+ *	 PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address	       - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*	This function prepares the ethernet port to start its activity:
+*	1) Completes the ethernet port driver struct initialization toward port
+*	    start routine.
+*	2) Resets the device to a quiescent state in case of warm reboot.
+*	3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*	4) Clean MAC tables. The reset status of those tables is unknown.
+*	5) Set PHY address.
+*	Note: Call this routine prior to eth_port_start routine and after setting
+*	user values in the user fields of Ethernet port control struct (i.e.
+*	port_phy_addr).
+*
+* INPUT:
+*	ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR	*/
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64460_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*	This routine prepares the Ethernet port for Rx and Tx activity:
+*	1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*	    has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*	    for Tx and ether_init_rx_desc_ring for Rx)
+*	2. Initialize and enable the Ethernet configuration port by writing to
+*	    the port's configuration and command registers.
+*	3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*	After completing these steps, the ethernet port SDMA can starts to
+*	perform Rx and Tx activities.
+*
+*	Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*	to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*	ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*	ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*	Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*	false if the port PHY is not up.
+*	true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num	  Port number.
+*	char *	      p_addr		Address to be set
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*	To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	} else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*	Go through all the DA filter tables (Unicast, Special Multicast & Other
+*	Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*	Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*	None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*	This function clears all MIB counters of a specific ethernet port.
+*	A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*	After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*	MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*	This function reads a MIB counter of a specific ethernet port.
+*	NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*	following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*	register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*	ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*	unsigned int mib_offset	  MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*	After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*	MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*	This routine set the ethernet port PHY address according to given
+*	parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*	Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*	None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *	 This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 None.
+ *
+ * RETURN:
+ *	 PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/***********************************************************/
+/* (Re)start autonegotiation				   */
+/***********************************************************/
+int phy_setup_aneg (char *devname, unsigned char addr)
+{
+	unsigned short ctl, adv;
+
+	/* Setup standard advertise */
+	miiphy_read (devname, addr, MII_ADVERTISE, &adv);
+	adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
+		LPA_100FULL | LPA_100HALF | LPA_10FULL |
+		LPA_10HALF);
+	miiphy_write (devname, addr, MII_ADVERTISE, adv);
+
+	miiphy_read (devname, addr, MII_CTRL1000, &adv);
+	adv |= (0x0300);
+	miiphy_write (devname, addr, MII_CTRL1000, adv);
+
+	/* Start/Restart aneg */
+	miiphy_read (devname, addr, MII_BMCR, &ctl);
+	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
+	miiphy_write (devname, addr, MII_BMCR, ctl);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *	 This routine utilize the SMI interface to reset the ethernet port PHY.
+ *	 The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data);
+	phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */
+	eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data);
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ *	This routine resets the chip by aborting any SDMA engine activity and
+ *	clearing the MIB counters. The Receiver and the Transmit unit are in
+ *	idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 Channel activity is halted.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *	 This function sets specified bits in the given ethernet
+ *	 configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	unsigned int	value	32 bit value.
+ *
+ * OUTPUT:
+ *	The set bits in the value parameter are set in the configuration
+ *	register.
+ *
+ * RETURN:
+ *	None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *	 This function resets specified bits in the given Ethernet
+ *	 configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	unsigned int	value	32 bit value.
+ *
+ * OUTPUT:
+ *	The set bits in the value parameter are reset in the configuration
+ *	register.
+ *
+ * RETURN:
+ *	None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *	 This function returns the configuration register value of the given
+ *	 ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 None.
+ *
+ * RETURN:
+ *	 Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *	 This routine utilize the SMI interface to interact with the PHY in
+ *	 order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	 unsigned int	phy_reg	  PHY register address offset.
+ *	 unsigned int	*value	 Register value buffer.
+ *
+ * OUTPUT:
+ *	 Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *	 false if the PHY is busy or read data is not in valid state.
+ *	 true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+int mv_miiphy_read(const char *devname, unsigned char phy_addr,
+		   unsigned char phy_reg, unsigned short *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return 0;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *	 This routine utilize the SMI interface to interact with the PHY in
+ *	 order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	unsigned int   phy_reg	 PHY register address offset.
+ *	unsigned int	value	Register value.
+ *
+ * OUTPUT:
+ *	Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *	false if the PHY is busy.
+ *	true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+int mv_miiphy_write(const char *devname, unsigned char phy_addr,
+		    unsigned char phy_reg, unsigned short value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return 0;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *	 This function configures the address decode parameters for the Gigabit
+ *	 Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	 ETH_WIN_PARAM	*param	 Address decode parameter struct.
+ *
+ * OUTPUT:
+ *	 An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *	 This function prepares a Rx chained list of descriptors and packet
+ *	 buffers in a form of a ring. The routine must be called after port
+ *	 initialization routine and before port start routine.
+ *	 The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *	 devices in the system (i.e. DRAM). This function uses the ethernet
+ *	 struct 'virtual to physical' routine (set by the user) to set the ring
+ *	 with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue	 Number of Rx queue.
+ *	int			rx_desc_num	  Number of Rx descriptors
+ *	int			rx_buff_size	  Size of Rx buffer
+ *	unsigned int	rx_desc_base_addr  Rx descriptors memory area base addr.
+ *	unsigned int	rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *	The routine updates the Ethernet port control struct with information
+ *	regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *	false if the given descriptors memory area is not aligned according to
+ *	Ethernet SDMA specifications.
+ *	true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.	    */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *	 This function prepares a Tx chained list of descriptors and packet
+ *	 buffers in a form of a ring. The routine must be called after port
+ *	 initialization routine and before port start routine.
+ *	 The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *	 devices in the system (i.e. DRAM). This function uses the ethernet
+ *	 struct 'virtual to physical' routine (set by the user) to set the ring
+ *	 with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue	 Number of Tx queue.
+ *	int			tx_desc_num	  Number of Tx descriptors
+ *	int			tx_buff_size	  Size of Tx buffer
+ *	unsigned int	tx_desc_base_addr  Tx descriptors memory area base addr.
+ *	unsigned int	tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *	The routine updates the Ethernet port control struct with information
+ *	regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *	false if the given descriptors memory area is not aligned according to
+ *	Ethernet SDMA specifications.
+ *	true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *	supports transmitting of a packet spaned over multiple buffers. The
+ *	routine updates 'curr' and 'first' indexes according to the packet
+ *	segment passed to the routine. In case the packet segment is first,
+ *	the 'first' index is update. In any case, the 'curr' index is updated.
+ *	If the routine get into Tx resource error it assigns 'curr' index as
+ *	'first'. This way the function can abort Tx process of multiple
+ *	descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue	 Number of Tx queue.
+ *	PKT_INFO	*p_pkt_info	  User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory	 */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *	It uses the 'first' index to support Tx desc return in case a transmit
+ *	of a packet spanned over multiple buffer still in process.
+ *	In case the Tx queue was in "resource error" condition, where there are
+ *	no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue	 Number of Tx queue.
+ *	PKT_INFO	*p_pkt_info	  User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *	If the routine exhausts Rx ring resources then the resource error flag
+ *	is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue	 Number of Rx queue.
+ *	PKT_INFO	*p_pkt_info	  User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers					    */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *	next 'used' descriptor and attached the returned buffer to it.
+ *	In case the Rx ring was in "resource error" condition, where there are
+ *	no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue	 Number of Rx queue.
+ *	PKT_INFO	*p_pkt_info	  Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num	   Ethernet port number
+ *	unsigned int t_clk	  t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay	 Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num	   Ethernet port number
+ *	unsigned int t_clk	  t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay	 Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *	 This function supports the eight bytes limitation on Tx buffer size.
+ *	 The routine will zero eight bytes starting from the destination address
+ *	 followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *	 unsigned int src_addr	  32 bit source address.
+ *	 unsigned int dst_addr	  32 bit destination address.
+ *	 int	    byte_count	  Number of bytes to copy.
+ *
+ * OUTPUT:
+ *	 See description.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/u-boot/board/prodrive/p3mx/mv_eth.h b/u-boot/board/prodrive/p3mx/mv_eth.h
new file mode 100644
index 0000000..af15274
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/mv_eth.h
@@ -0,0 +1,840 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64460_ETH_H__
+#define __DB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include <asm/errno.h>
+#include "../../Marvell/include/core.h"
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64460_TX_QUEUE_NUM 1
+#define MV64460_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#else
+#define MV64460_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#else
+#define MV64460_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64460_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64460_TX_BUFFER_SIZE 1600
+#endif
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64460_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+    /* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+    int first_init;
+};
+
+int mv64460_eth_init (struct eth_device *dev);
+int mv64460_eth_stop (struct eth_device *dev);
+int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64460_eth0_poll(); */
+
+int mv64460_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64460_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64460_ETH_ */
diff --git a/u-boot/board/prodrive/p3mx/mv_regs.h b/u-boot/board/prodrive/p3mx/mv_regs.h
new file mode 100644
index 0000000..068590f
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/mv_regs.h
@@ -0,0 +1,1125 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64460r.h - GT-64460 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64460
+
+/* Supported by the Atlantis */
+#define MV64460_INCLUDE_PCI_1
+#define MV64460_INCLUDE_PCI_0_ARBITER
+#define MV64460_INCLUDE_PCI_1_ARBITER
+#define MV64460_INCLUDE_SNOOP_SUPPORT
+#define MV64460_INCLUDE_P2P
+#define MV64460_INCLUDE_ETH_PORT_2
+#define MV64460_INCLUDE_CPU_MAPPING
+#define MV64460_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64460_CS_0_BASE_ADDR					    0x008
+#define MV64460_CS_0_SIZE					    0x010
+#define MV64460_CS_1_BASE_ADDR					    0x208
+#define MV64460_CS_1_SIZE					    0x210
+#define MV64460_CS_2_BASE_ADDR					    0x018
+#define MV64460_CS_2_SIZE					    0x020
+#define MV64460_CS_3_BASE_ADDR					    0x218
+#define MV64460_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64460_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64460_PCI_0_IO_SIZE					    0x050
+#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64460_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64460_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64460_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64460_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64460_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64460_PCI_1_IO_SIZE					    0x098
+#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64460_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64460_CPU_CONFIG					    0x000
+#define MV64460_CPU_MODE					    0x120
+#define MV64460_CPU_MASTER_CONTROL				    0x160
+#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64460_SMP_WHO_AM_I					    0x200
+#define MV64460_SMP_CPU0_DOORBELL				    0x214
+#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64460_SMP_CPU1_DOORBELL				    0x224
+#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64460_SMP_SEMAPHOR0					    0x244
+#define MV64460_SMP_SEMAPHOR1					    0x24c
+#define MV64460_SMP_SEMAPHOR2					    0x254
+#define MV64460_SMP_SEMAPHOR3					    0x25c
+#define MV64460_SMP_SEMAPHOR4					    0x264
+#define MV64460_SMP_SEMAPHOR5					    0x26c
+#define MV64460_SMP_SEMAPHOR6					    0x274
+#define MV64460_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64460_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64460_CPU_ERROR_DATA_LOW				    0x128
+#define MV64460_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64460_CPU_ERROR_PARITY				    0x138
+#define MV64460_CPU_ERROR_CAUSE					    0x140
+#define MV64460_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64460_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64460_SRAM_CONFIG					    0x380
+#define MV64460_SRAM_TEST_MODE					    0X3F4
+#define MV64460_SRAM_ERROR_CAUSE				    0x388
+#define MV64460_SRAM_ERROR_ADDR					    0x390
+#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64460_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64460_SDRAM_CONFIG					    0x1400
+#define MV64460_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64460_D_UNIT_MMASK					    0x14B0
+#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64460_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64460_SDRAM_OPERATION					    0x1418
+#define MV64460_SDRAM_MODE					    0x141c
+#define MV64460_EXTENDED_DRAM_MODE				    0x1420
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64460_SDRAM_ERROR_ADDR				    0x1450
+#define MV64460_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64460_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64460_SDRAM_ECC_CONTROL				    0x1454
+#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64460_DFCDL_CONFIG0					    0x1480
+#define MV64460_DFCDL_CONFIG1					    0x1484
+#define MV64460_DLL_WRITE					    0x1488
+#define MV64460_DLL_READ					    0x148c
+#define MV64460_SRAM_ADDR					    0x1490
+#define MV64460_SRAM_DATA0					    0x1494
+#define MV64460_SRAM_DATA1					    0x1498
+#define MV64460_SRAM_DATA2					    0x149c
+#define MV64460_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64460_DUNIT_DEBUG_LOW					    0x1460
+#define MV64460_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64460_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64460_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64460_DEVICE_ERROR_DATA				    0x4dc
+#define MV64460_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64460_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64460_PCI_0_COMMAND					    0xc00
+#define MV64460_PCI_1_COMMAND					    0xc80
+#define MV64460_PCI_0_MODE					    0xd00
+#define MV64460_PCI_1_MODE					    0xd80
+#define MV64460_PCI_0_RETRY					    0xc04
+#define MV64460_PCI_1_RETRY					    0xc84
+#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64460_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64460_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64460_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_SERR_MASK					    0xc28
+#define MV64460_PCI_1_SERR_MASK					    0xca8
+#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64460_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64460_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_MMASK					    0X1D24
+#define MV64460_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64460_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64460_PCI_VPD_ADDR					    0x048
+#define MV64460_PCI_VPD_DATA					    0x04c
+#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64460_PCI_X_COMMAND					    0x060
+#define MV64460_PCI_X_STATUS					    0x064
+#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64460_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64460_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64460_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64460_ETH_PHY_ADDR_REG				    0x2000
+#define MV64460_ETH_SMI_REG					    0x2004
+#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64460_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64460_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64460_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64460_ETH_BAR_0					    0x2200
+#define MV64460_ETH_BAR_1					    0x2208
+#define MV64460_ETH_BAR_2					    0x2210
+#define MV64460_ETH_BAR_3					    0x2218
+#define MV64460_ETH_BAR_4					    0x2220
+#define MV64460_ETH_BAR_5					    0x2228
+#define MV64460_ETH_SIZE_REG_0					    0x2204
+#define MV64460_ETH_SIZE_REG_1					    0x220c
+#define MV64460_ETH_SIZE_REG_2					    0x2214
+#define MV64460_ETH_SIZE_REG_3					    0x221c
+#define MV64460_ETH_SIZE_REG_4					    0x2224
+#define MV64460_ETH_SIZE_REG_5					    0x222c
+#define MV64460_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64460_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64460_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64460_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64460_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64460_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64460_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64460_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64460_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64460_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64460_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64460_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64460_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64460_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64460_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64460_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64460_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64460_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64460_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64460_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64460_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64460_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64460_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64460_CUNIT_SIZE0					    0xf204
+#define MV64460_CUNIT_SIZE1					    0xf20c
+#define MV64460_CUNIT_SIZE2					    0xf214
+#define MV64460_CUNIT_SIZE3					    0xf21c
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64460_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64460_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64460_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64460_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64460_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64460_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64460_CUNIT_CONFIG_REG				    0xb40c
+#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64460_CUNIT_DEBUG_LOW					    0xf340
+#define MV64460_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64460_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64460_MPSC_ROUTING_REG				    0xb400
+#define MV64460_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64460_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64460_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64460_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64460_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64460_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64460_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64460_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64460_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64460_SDMA_CAUSE_REG					    0xb800
+#define MV64460_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64460_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64460_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64460_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64460_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64460_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64460_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64460_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64460_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64460_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64460_SDMA_SRAM_TARGET				    0x0003
+#define MV64460_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64460_PCI_0_TARGET					    0x0003
+#define MV64460_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64460_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64460_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64460_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64460_BRG_CAUSE_REG					    0xb834
+#define MV64460_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64460_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64460_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64460_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64460_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64460_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64460_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64460_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64460_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64460_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64460_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64460_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64460_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64460_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64460_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64460_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64460_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64460_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64460_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64460_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64460_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64460_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64460_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64460_DMA_SIZE_REG0					    0xa04
+#define MV64460_DMA_SIZE_REG1					    0xa0c
+#define MV64460_DMA_SIZE_REG2					    0xa14
+#define MV64460_DMA_SIZE_REG3					    0xa1c
+#define MV64460_DMA_SIZE_REG4					    0xa24
+#define MV64460_DMA_SIZE_REG5					    0xa2c
+#define MV64460_DMA_SIZE_REG6					    0xa34
+#define MV64460_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64460_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64460_DMA_ARBITER_CONTROL				    0x860
+#define MV64460_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64460_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64460_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64460_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64460_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64460_DMA_ERROR_ADDR					    0x8c8
+#define MV64460_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64460_DMA_DEBUG_LOW					    0x8e0
+#define MV64460_DMA_DEBUG_HIGH					    0x8e4
+#define MV64460_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64460_TIMER_COUNTER0					    0x850
+#define MV64460_TIMER_COUNTER1					    0x854
+#define MV64460_TIMER_COUNTER2					    0x858
+#define MV64460_TIMER_COUNTER3					    0x85C
+#define MV64460_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64460_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64460_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64460_I2C_SLAVE_ADDR					    0xc000
+#define MV64460_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64460_I2C_DATA					    0xc004
+#define MV64460_I2C_CONTROL					    0xc008
+#define MV64460_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64460_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_GPP_IO_CONTROL					    0xf100
+#define MV64460_GPP_LEVEL_CONTROL				    0xf110
+#define MV64460_GPP_VALUE					    0xf104
+#define MV64460_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64460_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64460_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64460_GPP_VALUE_SET					    0xf118
+#define MV64460_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64460_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64460_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64460_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64460_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64460_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64460_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64460_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64460_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64460_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64460_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64460_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_MPP_CONTROL0					    0xf000
+#define MV64460_MPP_CONTROL1					    0xf004
+#define MV64460_MPP_CONTROL2					    0xf008
+#define MV64460_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64460_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64460_SERIAL_INIT_CONTROL				    0xf328
+#define MV64460_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64460rh */
diff --git a/u-boot/board/prodrive/p3mx/p3mx.c b/u-boot/board/prodrive/p3mx/p3mx.c
new file mode 100644
index 0000000..05eca52
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/p3mx.c
@@ -0,0 +1,852 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ *	Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
+ *	Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
+ * modifications for the P3M750 by roel.loeffen@prodrive.nl
+ */
+
+/*
+ * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+#include <i2c.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "64460.h"
+#include "mv_regs.h"
+#include "p3mx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern flash_info_t flash_info[];
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+int display_mem_map (void);
+void set_led(int);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, */
+					/* FuncNum 10:8, RegNum 7:2 */
+
+	/*
+	 * In PCIX mode devices provide their own bus and device numbers.
+	 * We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the
+	 * bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
+		(1 << 18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen:
+	 * add write to pci remap registers for 64460.
+	 * in 64360 when writing to pci base go and overide remap automaticaly,
+	 * in 64460 it doesn't
+	 */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+	/* ronen:
+	 * update the pci internal registers base address.
+	 */
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CONFIG_SYS_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+	/* set the SINGLE_CPU bit  see MV64460 */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+	tmp |= CPU_CONF_PIPELINE;
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	/* set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in >MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+
+	/* Device and Boot bus settings
+	 */
+	memoryMapDeviceSpace(DEVICE0, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
+	memoryMapDeviceSpace(DEVICE1, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
+	memoryMapDeviceSpace(DEVICE2, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
+	memoryMapDeviceSpace(DEVICE3, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
+
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
+
+	gt_cpu_config();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+
+	set_led(LED_RED);
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	u8 val;
+
+	icache_enable ();
+#ifdef CONFIG_SYS_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+	/*
+	 * Enable trickle changing in RTC upon powerup
+	 * No diode, 250 ohm series resistor
+	 */
+	val = 0xa5;
+	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
+
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
+
+/*	display_mem_map(); */
+
+	/* now, jump to the main U-Boot board init code */
+	set_led(LED_GREEN);
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/*
+ * Check Board Identity:
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: %s", CONFIG_SYS_BOARD_NAME);
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+void set_led(int col)
+{
+	int tmp;
+	int on_pin;
+	int off_pin;
+
+	/* Program Mpp[22] as Gpp[22]
+	 * Program Mpp[23] as Gpp[23]
+	 */
+	tmp = GTREGREAD(MPP_CONTROL2);
+	tmp &= 0x00ffffff;
+	GT_REG_WRITE(MPP_CONTROL2,tmp);
+
+	/* Program Gpp[22] and Gpp[23] as output
+	 */
+	tmp = GTREGREAD(GPP_IO_CONTROL);
+	tmp |= 0x00C00000;
+	GT_REG_WRITE(GPP_IO_CONTROL, tmp);
+
+	/* Program Gpp[22] and Gpp[23] as active high
+	 */
+	tmp = GTREGREAD(GPP_LEVEL_CONTROL);
+	tmp &= 0xff3fffff;
+	GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
+
+	switch(col) {
+	default:
+	case LED_OFF :
+		on_pin  = 0;
+		off_pin = ((1 << 23) | (1 << 22));
+		break;
+	case LED_RED :
+		on_pin  = (1 << 23);
+		off_pin = (1 << 22);
+		break;
+	case LED_GREEN :
+		on_pin  = (1 << 22);
+		off_pin = (1 << 23);
+		break;
+	case LED_ORANGE :
+		on_pin  = ((1 << 23) | (1 << 22));
+		off_pin = 0;
+		break;
+	}
+
+	/* Set output Gpp[22] and Gpp[23]
+	 */
+	tmp = GTREGREAD(GPP_VALUE);
+	tmp |= on_pin;
+	tmp &= ~off_pin;
+	GT_REG_WRITE(GPP_VALUE, tmp);
+}
+
+int display_mem_map (void)
+{
+	int i;
+	unsigned int base, size, width;
+#ifdef CONFIG_PCI
+	int j;
+#endif
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0)
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+	}
+#ifdef CONFIG_PCI
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		/* ronen currently only first PCI MEM is used 3 */
+		for (j = 0; j <= PCI_REGION0; j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
+				j, base, size >> 20);
+		}
+	}
+#endif /* of CONFIG_PCI */
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
+		base, size >> 20, width);
+
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CONFIG_SYS_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+	     : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
+
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++)
+		pmem[i] = i;
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
+
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata    = 0;
+	int runaddress = 0;
+	int runwalk    = 0;
+
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+#endif
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  "
+			"(don't panic... that will take a moment !!!!)\n",
+			CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
+		printf ("passed\n");
+	return 0;
+
+}
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
diff --git a/u-boot/board/prodrive/p3mx/p3mx.h b/u-boot/board/prodrive/p3mx/p3mx.h
new file mode 100644
index 0000000..1caae6b
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/p3mx.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2005
+ *
+ * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3MX_H__
+#define __P3MX_H__
+
+#define LED_OFF		1
+#define LED_GREEN	2
+#define LED_RED		3
+#define LED_ORANGE	4
+
+#endif /* __P3MX_H__ */
diff --git a/u-boot/board/prodrive/p3mx/pci.c b/u-boot/board/prodrive/p3mx/pci.c
new file mode 100644
index 0000000..e36b676
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/pci.c
@@ -0,0 +1,1025 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+
+#ifdef CONFIG_PCI_PNP
+void pciauto_config_init(struct pci_controller *hose);
+int  pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+#endif
+
+#include "../../Marvell/include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+	unsigned int base;
+	unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*		    - Make sure the GT is configured as a master before writing
+*		      to another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*		   (or any other PCI device spec)
+*	    pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*		    - Make sure the GT is configured as a master before reading
+*		      from another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			spec)
+*	    pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*				the agent is placed on another Bus. For more
+*				information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*	    GT spec (or any other PCI device spec).
+*	    unsigned int pciDevNum - The device number needs to be addressed.
+*	    unsigned int busNum - On which bus does the Target agent connect
+*				  to.
+*	    unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*				the agent target locate on another PCI bus.
+*			      - Make sure the GT is configured as a master
+*				before reading from another device on the PCI.
+*			      - The function takes care of Big/Little endian
+*				conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			 spec). (configuration register offset.)
+*	    pciDevNum: The device number needs to be addressed.
+*	    busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*	    - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*			  feature bits given as an input.
+*			- Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*	  unsigned int features - See file: pci.h there are defintion for those
+*				  region features.
+*	  unsigned int baseAddress - The region base Address.
+*	  unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*			    to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*	    PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*	    PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*	    PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*	    PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*	    PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*	    PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*		       disable the park on last mechanism for each agent.
+*		       disabling this option for all agents results parking
+*		       on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*	  PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*	  PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*	  PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*	  PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*	  PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*	  PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*			respond to grant assertion within a window specified in
+*			the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*			grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*			    Detection mechanism.
+*			    NOTE: This operation may cause a dead lock on the
+*			    pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*		  For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*				       Boundry.
+*	   unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*				       Boundry.
+*	   unsigned int busNum - The CPI bus number to which the PCI interface
+*				       is connected.
+*	   unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*			   supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*	  snoopType - There is four optional Types:
+*			 1. No Snoop.
+*			 2. Snoop to WT region.
+*			 3. Snoop to WB region.
+*			 4. Snoop & Invalidate to WB region.
+*	  baseAddress - Base Address of this region.
+*	  regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					     0x0);
+		pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					    &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					     bar_value);
+	}
+}
+
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+			      pci_dev_t dev, struct pci_config_table *entry)
+{
+	u32		  bar_value, pci_response;
+
+	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+	pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+	pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+	gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+	gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+	unsigned char	  data;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return(0);
+		}
+	data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+	return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+	unsigned int	  off;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return;
+	}
+	off = data;
+	off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+	in8(off);
+	return;
+}
+#endif
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260	*/
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+	{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+#ifdef CONFIG_PCI_PNP
+	unsigned int bar;
+#endif
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+#ifdef CONFIG_USE_CPCIDVI
+	gt_cpcidvi_rom.init = 0;
+	gt_cpcidvi_rom.base = 0;
+#endif
+
+	pci0_hose.config_table = gt_config_table;
+	pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+	gt_config_table[0].config_device =  gt_setup_cpcidvi;
+#endif
+	gt_config_table[1].config_device =  gt_setup_ide;
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci0_hose);
+	pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+#endif
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci1_hose);
+	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
+#endif
+	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
+#endif /* of CONFIG_PCI */
diff --git a/u-boot/board/prodrive/p3mx/ppc_error_no.h b/u-boot/board/prodrive/p3mx/ppc_error_no.h
new file mode 100644
index 0000000..53687c8
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/ppc_error_no.h
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
+ */
+#ifndef _MV_PPC_ERRNO_H
+#define _MV_PPC_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Arg list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+#define	EDEADLOCK	58	/* File locking deadlock error */
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS	512
+#define ERESTARTNOINTR	513
+#define ERESTARTNOHAND	514	/* restart if no handler.. */
+#define ENOIOCTLCMD	515	/* No ioctl command */
+
+#define _LAST_ERRNO	515
+
+#endif
diff --git a/u-boot/board/prodrive/p3mx/sdram_init.c b/u-boot/board/prodrive/p3mx/sdram_init.c
new file mode 100644
index 0000000..bac6c12
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/sdram_init.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64460 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ *************************************************************************/
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../../Marvell/common/i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+#define MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit (void);	/* setup delay line of Mv64460 */
+int mvDmaIsChannelActive (int);
+int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
+int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
+
+#define D_CACHE_FLUSH_LINE(addr, offset)				\
+	{								\
+		__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+	}
+
+int memory_map_bank (unsigned int bankNo,
+		     unsigned int bankBase, unsigned int bankLength)
+{
+#if defined (MAP_PCI) && defined (CONFIG_PCI)
+	PCI_HOST host;
+#endif
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+#if defined (MAP_PCI) && defined (CONFIG_PCI)
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+#endif
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			DP (printf
+			    ("Found %08x  at Address %08x (failure)\n",
+			     (unsigned int) val, (unsigned int) addr));
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+
+	return maxsize;
+}
+
+#define SDRAM_NORMAL			0x0
+#define SDRAM_PRECHARGE_ALL		0x1
+#define SDRAM_REFRESH_ALL		0x2
+#define SDRAM_MODE_REG_SETUP		0x3
+#define SDRAM_XTEN_MODE_REG_SETUP	0x4
+#define SDRAM_NOP			0x5
+#define SDRAM_SELF_REFRESH		0x7
+
+phys_size_t initdram (int board_type)
+{
+	int tmp;
+	int start;
+	ulong size;
+	ulong memSpaceAttr;
+	ulong dest;
+
+	/* first disable all banks */
+	memory_map_bank(0, 0, 0);
+	memory_map_bank(1, 0, 0);
+	memory_map_bank(2, 0, 0);
+	memory_map_bank(3, 0, 0);
+
+	/* calibrate delay lines */
+	set_dfcdlInit();
+
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP);		/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* SDRAM controller configuration */
+#ifdef CONFIG_MV64460_ECC
+	GT_REG_WRITE(MV64460_SDRAM_CONFIG,		0x58201400);	/* 0x1400 */
+#else
+	GT_REG_WRITE(MV64460_SDRAM_CONFIG,		0x58200400);	/* 0x1400 */
+#endif
+	GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW,	0xC3000540);	/* 0x1404  */
+	GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH,	0x0300F777);	/* 0x1424 */
+	GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW,	0x01712220);	/* 0x1408 */
+	GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D);	/* 0x140C */
+	GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL,	0x00000012);	/* 0x1410 */
+	GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL,	0x00000001);	/* 0x1414 */
+
+	/* SDRAM drive strength */
+	GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
+	GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
+	GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000);	    /* 0x14C4 */
+	GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008);	    /* 0x14C4 */
+
+	/* setup SDRAM device registers */
+
+	/* precharge all */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* enable DLL */
+	GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000);			/* 0x1420 */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* reset DLL */
+	GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132);	/* 0x141C */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* precharge all */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* wait for 2 auto refresh commands */
+	udelay(20);
+
+	/* un-reset DLL */
+	GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032);	/* 0x141C */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* wait 200 cycles */
+	udelay(2);  /* FIXME  make this dynamic for the system clock */
+
+	/* SDRAM init done */
+	memory_map_bank(0, CONFIG_SYS_SDRAM_BASE,  (256 << 20));
+#ifdef CONFIG_SYS_SDRAM1_BASE
+	memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
+#endif
+
+	/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
+	 */
+	tmp = GTREGREAD(MV64460_D_UNIT_MMASK);				/* 0x14B0 */
+	GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
+
+	start = (0 << 20);
+#ifdef CONFIG_P3M750
+	size = (512 << 20);
+#elif defined (CONFIG_P3M7448)
+	size = (128 << 20);
+#endif
+
+#ifdef CONFIG_MV64460_ECC
+	memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
+	mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
+	for (dest = start; dest < start + size; dest += _8M) {
+		mvDmaTransfer (0, start, dest, _8M,
+			       BIT8 /*DMA_DTL_128BYTES */  |
+			       BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
+			       BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
+		while (mvDmaIsChannelActive (0));
+	}
+#endif
+
+	return (size);
+}
+
+void board_add_ram_info(int use_default)
+{
+	u32 val;
+
+	puts(" (CL=");
+	switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
+	case 0x2:
+		puts("2");
+		break;
+	case 0x3:
+		puts("3");
+		break;
+	case 0x5:
+		puts("1.5");
+		break;
+	case 0x6:
+		puts("2.5");
+		break;
+	}
+
+	val = GTREGREAD(MV64460_SDRAM_CONFIG);
+
+	puts(", ECC ");
+	if (val & 0x00001000)
+		puts("enabled)");
+	else
+		puts("not enabled)");
+}
+
+/*
+ * mvDmaIsChannelActive - Check if IDMA channel is active
+ *
+ * channel	= IDMA channel number from 0 to 7
+ */
+int mvDmaIsChannelActive (int channel)
+{
+	ulong data;
+
+	data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
+	if (data & BIT14)	/* activity status */
+		return 1;
+
+	return 0;
+}
+
+/*
+ * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
+ *			 map.
+ *
+ * memSpace	= IDMA memory window number from 0 to 7
+ * trg_if	= Target interface:
+ *		  0x0 DRAM
+ *		  0x1 Device Bus
+ *		  0x2 Integrated SDRAM (or CPU bus 60x only)
+ *		  0x3 PCI0
+ *		  0x4 PCI1
+ * attr		= IDMA attributes (see MV datasheet)
+ * base_addr	= Sets up memory window for transfers
+ *
+ */
+int mvDmaSetMemorySpace (ulong memSpace,
+			 ulong trg_if,
+			 ulong attr, ulong base_addr, ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (base_addr % size != 0)
+		return 0;
+
+	if (size >= 0x10000) {	 /* 64K */
+		size &= 0xffff0000;
+		base_addr = (base_addr & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
+			      (base_addr | trg_if | attr));
+		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
+			      (temp & ~(BIT0 << memSpace)));
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
+ *		   DMA channels.
+ *
+ * channel	= IDMA channel number from 0 to 3
+ * destAddr	= Destination address
+ * sourceAddr	= Source address
+ * size		= Size in bytes
+ * command	= See MV datasheet
+ *
+ */
+int mvDmaTransfer (int channel, ulong sourceAddr,
+		   ulong destAddr, ulong size, ulong command)
+{
+	ulong engOffReg = 0;	/* Engine Offset Register */
+
+	if (size > 0xffff)
+		command = command | BIT31;	/* DMA_16M_DESCRIPTOR_MODE */
+	command = command | ((command >> 6) & 0x7);
+	engOffReg = channel * 4;
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
+	command = command |
+		BIT12	|			/* DMA_CHANNEL_ENABLE */
+		BIT9;				/* DMA_NON_CHAIN_MODE */
+	/* Activate DMA channel By writting to mvDmaControlRegister */
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
+	return 1;
+}
+
+/****************************************************************************************
+ *			       SDRAM INIT						*
+ *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+ *		 This procedure fits only the Atlantis					*
+ *											*
+ ***************************************************************************************/
+
+/****************************************************************************************
+ *			       DFCDL initialize MV643xx Design Considerations		*
+ *											*
+ ***************************************************************************************/
+int set_dfcdlInit (void)
+{
+	int i;
+
+	/* Values from MV64460 User Manual */
+	unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
+				     0x000000c4, 0x00000105, 0x00000146, 0x00000187,
+				     0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
+				     0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
+				     0x000003d0, 0x00000411, 0x00000452, 0x00000493,
+				     0x000004d4, 0x00000515, 0x00000556, 0x00000597,
+				     0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
+				     0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
+				     0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
+				     0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
+				     0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
+				     0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
+				     0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
+				     0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
+				     0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
+				     0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
+
+	for (i = 0; i < 64; i++)
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+	return (0);
+}
diff --git a/u-boot/board/prodrive/p3mx/serial.c b/u-boot/board/prodrive/p3mx/serial.c
new file mode 100644
index 0000000..e1af37e
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/serial.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * modified for cpci750 board by
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for esd cpci750 board
+ */
+
+/* supports the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../../Marvell/include/memory.h"
+#include "serial.h"
+
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int serial_init (void)
+{
+	mpsc_init (gd->baudrate);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/u-boot/board/prodrive/p3mx/serial.h b/u-boot/board/prodrive/p3mx/serial.h
new file mode 100644
index 0000000..c7fc8c1
--- /dev/null
+++ b/u-boot/board/prodrive/p3mx/serial.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/u-boot/board/prodrive/p3p440/Makefile b/u-boot/board/prodrive/p3p440/Makefile
new file mode 100644
index 0000000..5b0ffc2
--- /dev/null
+++ b/u-boot/board/prodrive/p3p440/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/prodrive/p3p440/config.mk b/u-boot/board/prodrive/p3p440/config.mk
new file mode 100644
index 0000000..9eac8b9
--- /dev/null
+++ b/u-boot/board/prodrive/p3p440/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/prodrive/p3p440/init.S b/u-boot/board/prodrive/p3p440/init.S
new file mode 100644
index 0000000..6230695
--- /dev/null
+++ b/u-boot/board/prodrive/p3p440/init.S
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+    tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+    tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
+    tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+    tlbtab_end
diff --git a/u-boot/board/prodrive/p3p440/p3p440.c b/u-boot/board/prodrive/p3p440/p3p440.c
new file mode 100644
index 0000000..020f66d
--- /dev/null
+++ b/u-boot/board/prodrive/p3p440/p3p440.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#include "p3p440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void set_led(int color)
+{
+	switch (color) {
+	case LED_OFF:
+		out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
+		break;
+
+	case LED_GREEN:
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
+		break;
+
+	case LED_RED:
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
+		break;
+
+	case LED_ORANGE:
+		out32(GPIO0_OR,  in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
+		break;
+	}
+}
+
+static int is_monarch(void)
+{
+	out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
+	udelay(1000);
+
+	if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
+		return 0;
+	else
+		return 1;
+}
+
+static void wait_for_pci_ready(void)
+{
+	/*
+	 * Configure EREADY_IO as input
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
+	udelay(1000);
+
+	for (;;) {
+		if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
+			return;
+	}
+
+}
+
+int board_early_init_f(void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	reg = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
+
+	/*--------------------------------------------------------------------
+	 * Setup pin multiplexing (GPIO/IRQ...)
+	 *-------------------------------------------------------------------*/
+	mtdcr(CPC0_GPIO, 0x03F01F80);
+
+	out32(GPIO0_ODR, 0x00000000);	/* no open drain pins      */
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
+	out32(GPIO0_OR,  CONFIG_SYS_GPIO_RDY);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: P3P440");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	if (is_monarch()) {
+		puts(", Monarch");
+	} else {
+		puts(", None-Monarch");
+	}
+
+	putc('\n');
+
+	return (0);
+}
+
+int misc_init_r (void)
+{
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if only one FLASH bank is available
+	 */
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+		mtebc(PB1CR, 0);			/* disable cs */
+		mtebc(PB1AP, 0);
+		mtebc(PB2CR, 0);			/* disable cs */
+		mtebc(PB2AP, 0);
+		mtebc(PB3CR, 0);			/* disable cs */
+		mtebc(PB3AP, 0);
+	}
+
+	return 0;
+}
+
+/*************************************************************************
+ * Override weak is_pci_host()
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	if (is_monarch()) {
+		wait_for_pci_ready();
+		return 1;		/* return 1 for host controller */
+	} else {
+		return 0;		/* return 0 for adapter controller */
+	}
+}
+#endif				/* defined(CONFIG_PCI) */
diff --git a/u-boot/board/prodrive/p3p440/p3p440.h b/u-boot/board/prodrive/p3p440/p3p440.h
new file mode 100644
index 0000000..47e9018
--- /dev/null
+++ b/u-boot/board/prodrive/p3p440/p3p440.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3P440_H__
+#define __P3P440_H__
+
+#define CONFIG_SYS_GPIO_RDY	(0x80000000 >> 11)
+#define CONFIG_SYS_MONARCH_IO	(0x80000000 >> 18)
+#define CONFIG_SYS_EREADY_IO	(0x80000000 >> 20)
+#define CONFIG_SYS_LED_GREEN	(0x80000000 >> 21)
+#define CONFIG_SYS_LED_RED	(0x80000000 >> 22)
+
+#define LED_OFF		1
+#define LED_GREEN	2
+#define LED_RED		3
+#define LED_ORANGE	4
+
+long int fixed_sdram(void);
+
+#endif /* __P3P440_H__ */
diff --git a/u-boot/board/prodrive/pdnb3/Makefile b/u-boot/board/prodrive/pdnb3/Makefile
new file mode 100644
index 0000000..40a6fd2
--- /dev/null
+++ b/u-boot/board/prodrive/pdnb3/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= flash.o pdnb3.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/prodrive/pdnb3/config.mk b/u-boot/board/prodrive/pdnb3/config.mk
new file mode 100644
index 0000000..817541f
--- /dev/null
+++ b/u-boot/board/prodrive/pdnb3/config.mk
@@ -0,0 +1,2 @@
+#
+CONFIG_SYS_TEXT_BASE = 0x01f00000
diff --git a/u-boot/board/prodrive/pdnb3/flash.c b/u-boot/board/prodrive/pdnb3/flash.c
new file mode 100644
index 0000000..fe8d100
--- /dev/null
+++ b/u-boot/board/prodrive/pdnb3/flash.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ixp425.h>
+
+#if !defined(CONFIG_FLASH_CFI_DRIVER)
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*
+ * Prototypes
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+
+static inline ulong ld(ulong x)
+{
+	ulong k = 0;
+
+	while (x >>= 1)
+		++k;
+
+	return k;
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN)
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+
+	/* Reconfigure CS0 to actual FLASH size */
+	*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
+
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+	/* Environment protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+	/* Redundant environment protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR_REDUND,
+		      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+	flash_info[0].size = size;
+
+	return size;
+}
+
+#endif /* CONFIG_FLASH_CFI_DRIVER */
diff --git a/u-boot/board/prodrive/pdnb3/nand.c b/u-boot/board/prodrive/pdnb3/nand.c
new file mode 100644
index 0000000..2efe027
--- /dev/null
+++ b/u-boot/board/prodrive/pdnb3/nand.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+
+struct pdnb3_ndfc_regs {
+	uchar cmd;
+	uchar wait;
+	uchar addr;
+	uchar term;
+	uchar data;
+};
+
+static u8 hwctl;
+static struct pdnb3_ndfc_regs *pdnb3_ndfc;
+
+#define readb(addr)	*(volatile u_char *)(addr)
+#define readl(addr)	*(volatile u_long *)(addr)
+#define writeb(d,addr)	*(volatile u_char *)(addr) = (d)
+
+/*
+ * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices.  The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately.  We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access.
+ *
+ * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
+ */
+static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
+		if ( (ctrl & NAND_NCE) != NAND_NCE)
+			writeb(0x00, &(pdnb3_ndfc->term));
+	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+
+static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
+{
+	return readb(&(pdnb3_ndfc->data));
+}
+
+static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (hwctl & 0x1)
+			writeb(buf[i], &(pdnb3_ndfc->cmd));
+		else if (hwctl & 0x2)
+			writeb(buf[i], &(pdnb3_ndfc->addr));
+		else
+			writeb(buf[i], &(pdnb3_ndfc->data));
+	}
+}
+
+static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+
+	if (len % 4) {
+		for (i = 0; i < len; i++)
+			buf[i] = readb(&(pdnb3_ndfc->data));
+	} else {
+		ulong *ptr = (ulong *)buf;
+		int count = len >> 2;
+
+		for (i = 0; i < count; i++)
+			*ptr++ = readl(&(pdnb3_ndfc->data));
+	}
+}
+
+static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != readb(&(pdnb3_ndfc->data)))
+			return i;
+
+	return 0;
+}
+
+static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
+{
+	volatile u_char val;
+
+	/*
+	 * Blocking read to wait for NAND to be ready
+	 */
+	val = readb(&(pdnb3_ndfc->wait));
+
+	/*
+	 * Return always true
+	 */
+	return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	/* Set address of NAND IO lines (Using Linear Data Access Region) */
+	nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
+	nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
+	/* Reference hardware control function */
+	nand->cmd_ctrl   = pdnb3_nand_hwcontrol;
+	nand->read_byte  = pdnb3_nand_read_byte;
+	nand->write_buf  = pdnb3_nand_write_buf;
+	nand->read_buf   = pdnb3_nand_read_buf;
+	nand->verify_buf = pdnb3_nand_verify_buf;
+	nand->dev_ready  = pdnb3_nand_dev_ready;
+	return 0;
+}
+#endif
diff --git a/u-boot/board/prodrive/pdnb3/pdnb3.c b/u-boot/board/prodrive/pdnb3/pdnb3.c
new file mode 100644
index 0000000..928dd22
--- /dev/null
+++ b/u-boot/board/prodrive/pdnb3/pdnb3.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* predefine these here for FPGA programming (before including fpga.c) */
+#define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
+#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
+#define OLD_VAL		old_val
+
+static unsigned long old_val = 0;
+
+/*
+ * include common fpga code (for prodrive boards)
+ */
+#include "../common/fpga.c"
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* arch number of PDNB3 */
+	gd->bd->bi_arch_number = MACH_TYPE_PDNB3;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
+
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
+
+	/*
+	 * Setup GPIO's for FPGA programming
+	 */
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
+
+	/*
+	 * Setup GPIO's for interrupts
+	 */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
+
+	/*
+	 * Setup GPIO's for 33MHz clock output
+	 */
+	*IXP425_GPIO_GPCLKR = 0x01FF0000;
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
+
+	/*
+	 * Setup other chip select's
+	 */
+	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: PDNB3");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+int do_fpga_boot(unsigned char *fpgadata)
+{
+	unsigned char *dst;
+	int status;
+	int index;
+	int i;
+	ulong len = CONFIG_SYS_MALLOC_LEN;
+
+	/*
+	 * Setup GPIO's for FPGA programming
+	 */
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
+
+	/*
+	 * Save value so no readback is required upon programming
+	 */
+	old_val = *IXP425_GPIO_GPOUTR;
+
+	/*
+	 * First try to decompress fpga image (gzip compressed?)
+	 */
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf("Error: Image has to be gzipp'ed!\n");
+		return -1;
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=5; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA
+	 */
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
+	udelay(10);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
+
+	return (0);
+}
+
+int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	return do_fpga_boot((unsigned char *)addr);
+}
+
+U_BOOT_CMD(
+	fpga,     2,     0,      do_fpga,
+	"boot FPGA",
+	"address size\n    - boot FPGA with gzipped image at <address>"
+);
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+extern struct pci_controller hose;
+extern void pci_ixp_init(struct pci_controller * hose);
+
+void pci_init_board(void)
+{
+	extern void pci_ixp_init (struct pci_controller *hose);
+
+	pci_ixp_init(&hose);
+}
+#endif
diff --git a/u-boot/board/psyent/common/AMDLV065D.c b/u-boot/board/psyent/common/AMDLV065D.c
new file mode 100644
index 0000000..72b0a9f
--- /dev/null
+++ b/u-boot/board/psyent/common/AMDLV065D.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#if defined(CONFIG_NIOS)
+#include <nios.h>
+#else
+#include <asm/io.h>
+#endif
+
+#define SECTSZ		(64 * 1024)
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = CONFIG_SYS_FLASH_SIZE;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CONFIG_SYS_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+		fli->protect[i] = 1;
+	}
+
+	return (CONFIG_SYS_FLASH_SIZE);
+}
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	int erased;
+	unsigned long *addr;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		erased = 1;
+		addr = (unsigned long *) info->start[i];
+		for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+			if ( readl(addr++) != (unsigned long)-1) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	unsigned char *addr = (unsigned char *) info->start[0];
+	unsigned char *addr2;
+	int prot, sect;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (unsigned char *) info->start[sect];
+			writeb (0xaa, addr);
+			writeb (0x55, addr);
+			writeb (0x80, addr);
+			writeb (0xaa, addr);
+			writeb (0x55, addr);
+			writeb (0x30, addr2);
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait.
+			 */
+			start = get_timer (0);
+			while ( readb (addr2) != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+		}
+	}
+	printf ("\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((readb (dst) & b) != b) {
+			printf ("%02x : %02x\n", readb (dst), b);
+			return (2);
+		}
+
+		writeb (0xaa, cmd);
+		writeb (0x55, cmd);
+		writeb (0xa0, cmd);
+		writeb (dst, b);
+
+		/* Verify write */
+		start = get_timer (0);
+		while (readb (dst) != b) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/psyent/pci5441/Makefile b/u-boot/board/psyent/pci5441/Makefile
new file mode 100644
index 0000000..1cfe9e5
--- /dev/null
+++ b/u-boot/board/psyent/pci5441/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COMOBJS := ../common/AMDLV065D.o
+
+COBJS	:= $(BOARD).o $(COMOBJS)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/psyent/pci5441/config.mk b/u-boot/board/psyent/pci5441/config.mk
new file mode 100644
index 0000000..863a4cb
--- /dev/null
+++ b/u-boot/board/psyent/pci5441/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x018e0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/u-boot/board/psyent/pci5441/pci5441.c b/u-boot/board/psyent/pci5441/pci5441.c
new file mode 100644
index 0000000..0afef6f
--- /dev/null
+++ b/u-boot/board/psyent/pci5441/pci5441.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Psyent PCI-5441\n");
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return (0);
+}
diff --git a/u-boot/board/psyent/pk1c20/Makefile b/u-boot/board/psyent/pk1c20/Makefile
new file mode 100644
index 0000000..4677809
--- /dev/null
+++ b/u-boot/board/psyent/pk1c20/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COMOBJS := ../common/AMDLV065D.o
+
+COBJS	:= $(BOARD).o led.o $(COMOBJS)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/psyent/pk1c20/config.mk b/u-boot/board/psyent/pk1c20/config.mk
new file mode 100644
index 0000000..3913a24
--- /dev/null
+++ b/u-boot/board/psyent/pk1c20/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/u-boot/board/psyent/pk1c20/led.c b/u-boot/board/psyent/pk1c20/led.c
new file mode 100644
index 0000000..d019735
--- /dev/null
+++ b/u-boot/board/psyent/pk1c20/led.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+#include <status_led.h>
+
+/* The LED port is configured as output only, so we
+ * must track the state manually.
+ */
+static led_id_t val = 0;
+
+void __led_init (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (val, &pio->data);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (val, &pio->data);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+
+	val ^= mask;
+	writel (val, &pio->data);
+}
diff --git a/u-boot/board/psyent/pk1c20/pk1c20.c b/u-boot/board/psyent/pk1c20/pk1c20.c
new file mode 100644
index 0000000..0a24866
--- /dev/null
+++ b/u-boot/board/psyent/pk1c20/pk1c20.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Psyent PK-1C20\n");
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/purple/Makefile b/u-boot/board/purple/Makefile
new file mode 100644
index 0000000..10e566d
--- /dev/null
+++ b/u-boot/board/purple/Makefile
@@ -0,0 +1,46 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o sconsole.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/purple/config.mk b/u-boot/board/purple/config.mk
new file mode 100644
index 0000000..404c3fb
--- /dev/null
+++ b/u-boot/board/purple/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Purple board with MIPS 5Kc CPU core
+#
+
+# ROM version
+CONFIG_SYS_TEXT_BASE = 0xB0000000
+
+# RAM version
+#CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/u-boot/board/purple/flash.c b/u-boot/board/purple/flash.c
new file mode 100644
index 0000000..5cee35e
--- /dev/null
+++ b/u-boot/board/purple/flash.c
@@ -0,0 +1,595 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/inca-ip.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg))
+
+/* FLASH29 command register addresses */
+
+#define FLASH29_REG_FIRST_CYCLE		FLASH29_REG_ADRS (0x1555)
+#define FLASH29_REG_SECOND_CYCLE	FLASH29_REG_ADRS (0x2aaa)
+#define FLASH29_REG_THIRD_CYCLE		FLASH29_REG_ADRS (0x3555)
+#define	FLASH29_REG_FOURTH_CYCLE	FLASH29_REG_ADRS (0x4555)
+#define	FLASH29_REG_FIFTH_CYCLE		FLASH29_REG_ADRS (0x5aaa)
+#define	FLASH29_REG_SIXTH_CYCLE		FLASH29_REG_ADRS (0x6555)
+
+/* FLASH29 command definitions */
+
+#define	FLASH29_CMD_FIRST		0xaaaaaaaa
+#define	FLASH29_CMD_SECOND		0x55555555
+#define	FLASH29_CMD_FOURTH		0xaaaaaaaa
+#define	FLASH29_CMD_FIFTH		0x55555555
+#define	FLASH29_CMD_SIXTH		0x10101010
+
+#define	FLASH29_CMD_SECTOR		0x30303030
+#define	FLASH29_CMD_PROGRAM		0xa0a0a0a0
+#define	FLASH29_CMD_CHIP_ERASE		0x80808080
+#define	FLASH29_CMD_READ_RESET		0xf0f0f0f0
+#define	FLASH29_CMD_AUTOSELECT		0x90909090
+#define FLASH29_CMD_READ		0x70707070
+
+#define IN_RAM_CMD_READ		0x1
+#define IN_RAM_CMD_WRITE	0x2
+
+#define FLASH_WRITE_CMD	((ulong)(flash_write_cmd) & 0x7)+0xbf008000
+#define FLASH_READ_CMD  ((ulong)(flash_read_cmd) & 0x7)+0xbf008000
+
+typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs);
+typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen);
+typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value);
+
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static int write_word(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+static void load_cmd(ulong cmd);
+static ulong in_ram_cmd = 0;
+
+
+/******************************************************************************
+*
+* Don't change the program architecture
+* This architecture assure the program
+* can be relocated to scratch ram
+*/
+static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
+{
+	int i,j;
+	FPW temp,temp1;
+	FPWV *str;
+
+	str = (FPWV *)string;
+
+	j=  strLen/4;
+
+	if(cmd == FLASH29_CMD_AUTOSELECT)
+	   {
+	    *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
+	    *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_AUTOSELECT;
+	   }
+
+	if(cmd == FLASH29_CMD_READ)
+	   {
+	    i = 0;
+	    while(i<j)
+	    {
+		temp = *pFA++;
+		temp1 = *(int *)0xa0000000;
+		*(int *)0xbf0081f8 = temp1 + temp;
+		*str++ = temp;
+		i++;
+	    }
+	   }
+
+	 if(cmd == FLASH29_CMD_READ_RESET)
+	 {
+	    *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
+	    *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_READ_RESET;
+	 }
+
+	*(int *)0xbf0081f8 = *(int *)0xa0000000;	/* dummy read switch back to sdram interface */
+}
+
+/******************************************************************************
+*
+* Don't change the program architecture
+* This architecture assure the program
+* can be relocated to scratch ram
+*/
+static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
+{
+	*(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
+	*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+
+	if (cmd == FLASH29_CMD_SECTOR)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_CHIP_ERASE;
+	    *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
+	    *(FLASH29_REG_FIFTH_CYCLE)  = FLASH29_CMD_FIFTH;
+	    *pFA		        = FLASH29_CMD_SECTOR;
+	   }
+
+	if (cmd == FLASH29_CMD_SIXTH)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_CHIP_ERASE;
+	    *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
+	    *(FLASH29_REG_FIFTH_CYCLE)  = FLASH29_CMD_FIFTH;
+	    *(FLASH29_REG_SIXTH_CYCLE)  = FLASH29_CMD_SIXTH;
+	   }
+
+	if (cmd == FLASH29_CMD_PROGRAM)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_PROGRAM;
+	    *pFA = value;
+	   }
+
+	if (cmd == FLASH29_CMD_READ_RESET)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_READ_RESET;
+	   }
+
+	*(int *)0xbf0081f8 = *(int *)0xa0000000;	/* dummy read switch back to sdram interface */
+}
+
+static void load_cmd(ulong cmd)
+{
+	ulong *src;
+	ulong *dst;
+	FUNCPTR_CP absEntry;
+	ulong func;
+
+	if (in_ram_cmd & cmd) return;
+
+	if (cmd == IN_RAM_CMD_READ)
+	{
+		func = (ulong)flash_read_cmd;
+	}
+	else
+	{
+		func = (ulong)flash_write_cmd;
+	}
+
+	src = (ulong *)(func & 0xfffffff8);
+	dst = (ulong *)0xbf008000;
+	absEntry = (FUNCPTR_CP)(0xbf0081d0);
+	absEntry(src,dst,0x38);
+
+	in_ram_cmd = cmd;
+}
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	load_cmd(IN_RAM_CMD_READ);
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = PHYS_FLASH_1;
+		ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
+
+		/* Disable write protection */
+		*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
+
+#if 1
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+#endif
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) {
+
+		int bootsect_size[4];	/* number of bytes/boot sector  */
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size[0] = 0x00008000;
+		bootsect_size[1] = 0x00004000;
+		bootsect_size[2] = 0x00004000;
+		bootsect_size[3] = 0x00010000;
+		sect_size =        0x00020000;
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			base += i < 4 ? bootsect_size[i] : sect_size;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:
+		fmt = "29LV160B%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	FUNCPTR_RD absEntry;
+	FPW retValue;
+	int flag;
+
+	load_cmd(IN_RAM_CMD_READ);
+	absEntry = (FUNCPTR_RD)FLASH_READ_CMD;
+
+	flag = disable_interrupts();
+	absEntry(FLASH29_CMD_AUTOSELECT,0,0,0);
+	if (flag) enable_interrupts();
+
+	udelay(100);
+
+	flag = disable_interrupts();
+	absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue));
+	absEntry(FLASH29_CMD_READ_RESET,0,0,0);
+	if (flag) enable_interrupts();
+
+	udelay(100);
+
+	switch (retValue) {
+
+	case (FPW)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	ulong start, now, last;
+	FUNCPTR_WR absEntry;
+
+	load_cmd(IN_RAM_CMD_WRITE);
+	absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		absEntry(FLASH29_CMD_SECTOR, addr, 0);
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		while ((now = get_timer(start)) <= CONFIG_SYS_FLASH_ERASE_TOUT) {
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		flag = disable_interrupts();
+		absEntry(FLASH29_CMD_READ_RESET,0,0);
+		if (flag)
+			enable_interrupts();
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	res = write_word(info, (FPWV *)addr, data);
+    }
+
+    return (res);
+}
+
+static int write_word (flash_info_t *info, FPWV *dest, FPW data)
+{
+    int res = 0;	/* result, assume success	*/
+    FUNCPTR_WR absEntry;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    if (info->start[0] != PHYS_FLASH_1)
+    {
+	return (3);
+    }
+
+    load_cmd(IN_RAM_CMD_WRITE);
+    absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
+
+    flag = disable_interrupts();
+    absEntry(FLASH29_CMD_PROGRAM,dest,data);
+    if (flag) enable_interrupts();
+
+    udelay(100);
+
+    flag = disable_interrupts();
+    absEntry(FLASH29_CMD_READ_RESET,0,0);
+    if (flag) enable_interrupts();
+
+    return (res);
+}
diff --git a/u-boot/board/purple/lowlevel_init.S b/u-boot/board/purple/lowlevel_init.S
new file mode 100644
index 0000000..1bd3edb
--- /dev/null
+++ b/u-boot/board/purple/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ *  Memory sub-system initialization code for PURPLE development board.
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/regdef.h>
+
+#define MC_IOGP	0xBF800800
+
+	.globl	lowlevel_init
+lowlevel_init:
+	li	t0, MC_IOGP
+	li	t1, 0xf24
+	sw	t1, 0(t0)
+	jr	ra
+	nop
diff --git a/u-boot/board/purple/purple.c b/u-boot/board/purple/purple.c
new file mode 100644
index 0000000..4e9e700
--- /dev/null
+++ b/u-boot/board/purple/purple.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/inca-ip.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#include "sconsole.h"
+
+#define cache_unroll(base,op)		\
+	__asm__ __volatile__("		\
+		.set noreorder;		\
+		.set mips3;		\
+		cache %1, (%0);		\
+		.set mips0;		\
+		.set reorder"		\
+		:			\
+		: "r" (base),		\
+		  "i" (op));
+
+typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs);
+
+extern void	asc_serial_init		(void);
+extern void	asc_serial_putc		(char);
+extern void	asc_serial_puts		(const char *);
+extern int	asc_serial_getc		(void);
+extern int	asc_serial_tstc		(void);
+extern void	asc_serial_setbrg	(void);
+
+void _machine_restart(void)
+{
+	void (*f)(void) = (void *) 0xbfc00000;
+
+	f();
+}
+
+static void sdram_timing_init (ulong size)
+{
+	register uint pass;
+	register uint done;
+	register uint count;
+	register uint p0, p1, p2, p3, p4;
+	register uint addr;
+
+#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3;
+#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3;
+
+	done = 0;
+	p0 = 2;
+	while (p0 < 4 && done == 0) {
+	    p1 = 0;
+	    while (p1 < 2 && done == 0) {
+		p2 = 0;
+		while (p2 < 2 && done == 0) {
+		    p3 = 0;
+		    while (p3 < 16 && done == 0) {
+			count = 0;
+			p4 = 0;
+			while (p4 < 32 && done == 0) {
+			    WRITE_MC_IOGP_1;
+
+			    for (addr = CKSEG1 + 0x4000;
+				 addr < CKSEG1ADDR (size);
+				 addr = addr + 4) {
+					*(uint *) addr = 0xaa55aa55;
+			    }
+
+			    pass = 1;
+
+			    for (addr = CKSEG1 + 0x4000;
+				 addr < CKSEG1ADDR (size) && pass == 1;
+				 addr = addr + 4) {
+					if (*(uint *) addr != 0xaa55aa55)
+						pass = 0;
+			    }
+
+			    if (pass == 1) {
+				count++;
+			    } else {
+				count = 0;
+			    }
+
+			    if (count == 32) {
+				WRITE_MC_IOGP_2;
+				done = 1;
+			    }
+			    p4++;
+			}
+			p3++;
+		    }
+		    p2++;
+		}
+		p1++;
+	    }
+	    p0++;
+	    if (p0 == 1)
+		p0++;
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	/* The only supported number of SDRAM banks is 4.
+	 */
+#define CONFIG_SYS_NB	4
+
+	ulong	cfgpb0	= *INCA_IP_SDRAM_MC_CFGPB0;
+	ulong	cfgdw	= *INCA_IP_SDRAM_MC_CFGDW;
+	int	cols	= cfgpb0 & 0xF;
+	int	rows	= (cfgpb0 & 0xF0) >> 4;
+	int	dw	= cfgdw & 0xF;
+	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
+	void (*  sdram_init) (ulong);
+
+	sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
+
+	sdram_init(0x10000);
+
+	return size;
+}
+
+int checkboard (void)
+{
+
+	unsigned long chipid = *(unsigned long *)0xB800C800;
+
+	printf ("Board: Purple PLB 2800 chip version %ld, ", chipid & 0xF);
+
+	printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
+
+	set_io_port_base(0);
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	asc_serial_init ();
+
+	sconsole_putc   = asc_serial_putc;
+	sconsole_puts   = asc_serial_puts;
+	sconsole_getc   = asc_serial_getc;
+	sconsole_tstc   = asc_serial_tstc;
+	sconsole_setbrg = asc_serial_setbrg;
+
+	sconsole_flush ();
+	return (0);
+}
+
+/*******************************************************************************
+*
+* copydwords - copy one buffer to another a long at a time
+*
+* This routine copies the first <nlongs> longs from <source> to <destination>.
+*/
+static void copydwords (ulong *source, ulong *destination, ulong nlongs)
+{
+	ulong temp,temp1;
+	ulong *dstend = destination + nlongs;
+
+	while (destination < dstend) {
+		temp = *source++;
+		/* dummy read from sdram */
+		temp1 = *(ulong *)0xa0000000;
+		/* avoid optimization from compliler */
+		*(ulong *)0xbf0081f8 = temp1 + temp;
+		*destination++ = temp;
+
+	}
+}
+
+/*******************************************************************************
+*
+* copyLongs - copy one buffer to another a long at a time
+*
+* This routine copies the first <nlongs> longs from <source> to <destination>.
+*/
+static void copyLongs (ulong *source, ulong *destination, ulong nlongs)
+{
+	FUNCPTR absEntry;
+
+	absEntry = (FUNCPTR)(0xbf008000+((ulong)copydwords & 0x7));
+	absEntry(source, destination, nlongs);
+}
+
+/*******************************************************************************
+*
+* programLoad - load program into ram
+*
+* This routine load copydwords into ram
+*
+*/
+static void programLoad(void)
+{
+	FUNCPTR absEntry;
+	ulong *src,*dst;
+
+	src = (ulong *)(CONFIG_SYS_TEXT_BASE + 0x428);
+	dst = (ulong *)0xbf0081d0;
+
+	absEntry = (FUNCPTR)(CONFIG_SYS_TEXT_BASE + 0x400);
+	absEntry(src,dst,0x6);
+
+	src = (ulong *)((ulong)copydwords & 0xfffffff8);
+	dst = (ulong *)0xbf008000;
+
+	absEntry(src,dst,0x38);
+}
+
+/*******************************************************************************
+*
+* copy_code - copy u-boot image from flash to RAM
+*
+* This routine is needed to solve flash problems on this board
+*
+*/
+void copy_code (ulong dest_addr)
+{
+	extern long uboot_end_data;
+	unsigned long start;
+	unsigned long end;
+
+	/* load copydwords into ram
+	 */
+	programLoad();
+
+	/* copy u-boot code
+	 */
+	copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
+		  (ulong *)dest_addr,
+		  ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
+
+
+	/* flush caches
+	 */
+
+	start = CKSEG0;
+	end = start + CONFIG_SYS_DCACHE_SIZE;
+	while(start < end) {
+		cache_unroll(start,Index_Writeback_Inv_D);
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	start = CKSEG0;
+	end = start + CONFIG_SYS_ICACHE_SIZE;
+	while(start < end) {
+		cache_unroll(start,Index_Invalidate_I);
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+#ifdef CONFIG_PLB2800_ETHER
+int board_eth_init(bd_t *bis)
+{
+	return plb2800_eth_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/purple/sconsole.c b/u-boot/board/purple/sconsole.c
new file mode 100644
index 0000000..cd9d871
--- /dev/null
+++ b/u-boot/board/purple/sconsole.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+
+#include "sconsole.h"
+
+void	(*sconsole_putc) (char) = 0;
+void	(*sconsole_puts) (const char *) = 0;
+int	(*sconsole_getc) (void) = 0;
+int	(*sconsole_tstc) (void) = 0;
+void	(*sconsole_setbrg) (void) = 0;
+
+int serial_init (void)
+{
+	sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+	sb->pos  = 0;
+	sb->size = 0;
+	sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+
+	return (0);
+}
+
+void serial_putc (char c)
+{
+	if (sconsole_putc) {
+		(*sconsole_putc) (c);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		if (c) {
+			sb->data[sb->pos++] = c;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+void serial_puts (const char *s)
+{
+	if (sconsole_puts) {
+		(*sconsole_puts) (s);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		while (*s) {
+			sb->data[sb->pos++] = *s++;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+int serial_getc (void)
+{
+	if (sconsole_getc) {
+		return (*sconsole_getc) ();
+	} else {
+		return 0;
+	}
+}
+
+int serial_tstc (void)
+{
+	if (sconsole_tstc) {
+		return (*sconsole_tstc) ();
+	} else {
+		return 0;
+	}
+}
+
+void serial_setbrg (void)
+{
+	if (sconsole_setbrg) {
+		(*sconsole_setbrg) ();
+	}
+}
+
+void sconsole_flush (void)
+{
+	if (sconsole_putc) {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+		unsigned int end = sb->pos < sb->size
+				? sb->pos + sb->max_size - sb->size
+				: sb->pos - sb->size;
+
+		while (sb->size) {
+			(*sconsole_putc) (sb->data[end++]);
+			if (end == sb->max_size) {
+				end = 0;
+			}
+			sb->size--;
+		}
+	}
+}
diff --git a/u-boot/board/purple/sconsole.h b/u-boot/board/purple/sconsole.h
new file mode 100644
index 0000000..baed5fb
--- /dev/null
+++ b/u-boot/board/purple/sconsole.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCONSOLE_H_
+#define _SCONSOLE_H_
+
+#include <config.h>
+
+typedef struct sconsole_buffer_s {
+	unsigned long size;
+	unsigned long max_size;
+	unsigned long pos;
+	char data[1];
+} sconsole_buffer_t;
+
+#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
+
+extern void	(* sconsole_putc)	(char);
+extern void	(* sconsole_puts)	(const char *);
+extern int	(* sconsole_getc)	(void);
+extern int	(* sconsole_tstc)	(void);
+extern void	(* sconsole_setbrg)	(void);
+
+extern void	sconsole_flush		(void);
+
+#endif
diff --git a/u-boot/board/purple/u-boot.lds b/u-boot/board/purple/u-boot.lds
new file mode 100644
index 0000000..719f268
--- /dev/null
+++ b/u-boot/board/purple/u-boot.lds
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  arch/mips/cpu/start.o		(.text)
+	  board/purple/lowlevel_init.o	(.text)
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o	(.ppcenv)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/pxa255_idp/Makefile b/u-boot/board/pxa255_idp/Makefile
new file mode 100644
index 0000000..dbde833
--- /dev/null
+++ b/u-boot/board/pxa255_idp/Makefile
@@ -0,0 +1,50 @@
+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= pxa_idp.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/pxa255_idp/README b/u-boot/board/pxa255_idp/README
new file mode 100644
index 0000000..0cc2f2a
--- /dev/null
+++ b/u-boot/board/pxa255_idp/README
@@ -0,0 +1,11 @@
+Tested:
+
+- MMC
+- Ethernet
+- BL console (on serial port connector J5)
+- flash support
+
+Todo:
+
+- display support
+- PCMCIA support
diff --git a/u-boot/board/pxa255_idp/idp_notes.txt b/u-boot/board/pxa255_idp/idp_notes.txt
new file mode 100644
index 0000000..4746748
--- /dev/null
+++ b/u-boot/board/pxa255_idp/idp_notes.txt
@@ -0,0 +1,46 @@
+Notes on the Vibren PXA255 IDP.
+
+Chip select usage:
+
+CS0 - flash
+CS1 - alt flash (Mdoc or main flash)
+CS2 - high speed expansion bus
+CS3 - Media Q, low speed exp bus
+CS4 - low speed exp bus
+CS5 - low speed exp bus
+  - IDE: offset 0x03000000 (abs: 0x17000000)
+  - Eth: offset 0x03400000 (abs: 0x17400000)
+  - core voltage latch: offset 0x03800000 (abs: 0x17800000)
+  - CPLD: offset 0x03C00000 (abs: 0x17C00000)
+
+PCMCIA Power control
+
+MAX1602EE w/ code pulled high (Cirrus code)
+vx = 5v
+vy = 3v
+
+			Bit pattern
+			PWR 3,2,1,0
+vcc	     vpp	A1VCC  A0VCC   A1VPP   A0VPP
+=====================================================
+0	     0            0      0       0       0	0x0
+3 (vy)	     0            1      0       1       1	0xB
+3 (vy)	     3 (vy)       1      0       0       1	0x9
+3 (vy)	     12(12in)     1      0       1       0	0xA
+5 (vx)	     0            0      1       1       1	0x7
+5 (vx)	     5 (vx)       0      1       0       1	0x5
+5 (vx	     12(12in)     0      1       1       0	0x6
+
+Display power sequencing:
+
+- VDD applied
+- within 1sec, activate scanning signals
+- wait at least 50mS - scanning signals must be active before activating DISP
+
+Signal mapping:
+Schematic            LV8V31 signal name
+=========================================
+LCD_ENAVLCD		DISP
+LCD_PWR			Applies VDD to board
+
+Both of the above signals are controlled by the CPLD
diff --git a/u-boot/board/pxa255_idp/pxa_idp.c b/u-boot/board/pxa255_idp/pxa_idp.c
new file mode 100644
index 0000000..804d09c
--- /dev/null
+++ b/u-boot/board/pxa255_idp/pxa_idp.c
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Support for Accelent/Vibren PXA255 IDP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <command.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* turn on serial ports */
+	*(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
+
+	/* set PWM for LCD */
+	/* a value that works is 60Hz, 77% duty cycle */
+	writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+	writel(0x3f, PWM_CTRL0);
+	writel(0x3ff, PWM_PERVAL0);
+	writel(792, PWM_PWDUTY0);
+
+	/* clear reset to AC97 codec */
+	writel(readl(CKEN) | CKEN2_AC97, CKEN);
+	writel(GCR_COLD_RST, GCR);
+
+	/* enable LCD backlight */
+	/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
+
+	/* test display */
+	/* lcd_puts("This is a test\nTest #2\n"); */
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef DEBUG_BLINKC_ENABLE
+
+void delay_c(void)
+{
+	/* reset OSCR to 0 */
+	writel(0, OSCR);
+	while (readl(OSCR) > 0x10000)
+		;
+
+	while (readl(OSCR) < 0xd4000)
+		;
+}
+
+void blink_c(void)
+{
+	int led_bit = (1<<10);
+
+	writel(led_bit, GPDR0);
+	writel(led_bit, GPCR0);
+	delay_c();
+	writel(led_bit, GPSR0);
+	delay_c();
+	writel(led_bit, GPCR0);
+}
+
+int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("IDPCMD started\n");
+	return 0;
+}
+
+U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
+	   "custom IDP command",
+	   "no args at this time"
+);
+
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/pxa255_idp/pxa_reg_calcs.out b/u-boot/board/pxa255_idp/pxa_reg_calcs.out
new file mode 100644
index 0000000..39295fb
--- /dev/null
+++ b/u-boot/board/pxa255_idp/pxa_reg_calcs.out
@@ -0,0 +1,119 @@
+gafr0_l: 0x80001005
+gafr0_u: 0xa5128012
+gafr1_l: 0x699a9558
+gafr1_u: 0xaaa5aa6a
+gafr2_l: 0xaaaaaaaa
+gafr2_u: 0x2
+gpcr0: 0x1800400
+gpcr1: 0x0
+gpcr2: 0x0
+gpdr0: 0xc1818440
+gpdr1: 0xfcffab82
+gpdr2: 0x1ffff
+gpsr0: 0x8000
+gpsr1: 0x3f0002
+gpsr2: 0x1c000
+
+
+#define CONFIG_SYS_GAFR0_L_VAL	0x80001005
+#define CONFIG_SYS_GAFR0_U_VAL	0xa5128012
+#define CONFIG_SYS_GAFR1_L_VAL	0x699a9558
+#define CONFIG_SYS_GAFR1_U_VAL	0xaaa5aa6a
+#define CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	0x2
+#define CONFIG_SYS_GPCR0_VAL	0x1800400
+#define CONFIG_SYS_GPCR1_VAL	0x0
+#define CONFIG_SYS_GPCR2_VAL	0x0
+#define CONFIG_SYS_GPDR0_VAL	0xc1818440
+#define CONFIG_SYS_GPDR1_VAL	0xfcffab82
+#define CONFIG_SYS_GPDR2_VAL	0x1ffff
+#define CONFIG_SYS_GPSR0_VAL	0x8000
+#define CONFIG_SYS_GPSR1_VAL	0x3f0002
+#define CONFIG_SYS_GPSR2_VAL	0x1c000
+
+
+GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
+GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
+GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
+GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
+GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
+GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
+GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
+GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
+GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
+GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
+GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
+GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
+GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
+GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
+GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
+GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
+GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
+GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
+GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
+GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
+GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
+GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
+GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
+GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
+GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
+GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
+GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
+GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
+GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
+GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
+GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
+GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
+GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
+GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
+GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
+GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
+GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
+GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
+GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
+GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
+GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
+GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
+GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
+GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
+GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
+GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
+GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
+GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
+GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
+GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
+GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
+GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
+GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
+GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
+GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
+GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
+GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
+GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
+GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
+GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
+GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
+GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
+GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
+GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
+GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
+GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
+GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
+GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
+GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
+GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
+GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
+GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
+GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
+GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
+GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
+GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
+GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
+GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
+GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
+GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
+GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
+GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
diff --git a/u-boot/board/pxa255_idp/pxa_reg_calcs.py b/u-boot/board/pxa255_idp/pxa_reg_calcs.py
new file mode 100644
index 0000000..2f89e31
--- /dev/null
+++ b/u-boot/board/pxa255_idp/pxa_reg_calcs.py
@@ -0,0 +1,311 @@
+#!/usr/bin/python
+
+# (C) Copyright 2004
+# BEC Systems <http://bec-systems.com>
+# Cliff Brake <cliff.brake@gmail.com>
+
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+# calculations for PXA255 registers
+
+class gpio:
+	dir = '0'
+	set = '0'
+	clr = '0'
+	alt = '0'
+	desc = ''
+
+	def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+		self.dir = dir
+		self.set = set
+		self.clr = clr
+		self.alt = alt
+		self.desc = desc
+		
+
+# the following is a dictionary of all GPIOs in the system
+# the key is the GPIO number
+
+
+pxa255_alt_func = {
+	0: ['gpio', 'none', 'none', 'none'],
+	1: ['gpio', 'gpio reset', 'none', 'none'],
+	2: ['gpio', 'none', 'none', 'none'],
+	3: ['gpio', 'none', 'none', 'none'],
+	4: ['gpio', 'none', 'none', 'none'],
+	5: ['gpio', 'none', 'none', 'none'],
+	6: ['gpio', 'MMC clk', 'none', 'none'],
+	7: ['gpio', '48MHz clock', 'none', 'none'],
+	8: ['gpio', 'MMC CS0', 'none', 'none'],
+	9: ['gpio', 'MMC CS1', 'none', 'none'],
+	10: ['gpio', 'RTC Clock', 'none', 'none'],
+	11: ['gpio', '3.6MHz', 'none', 'none'],
+	12: ['gpio', '32KHz', 'none', 'none'],
+	13: ['gpio', 'none', 'MBGNT', 'none'],
+	14: ['gpio', 'MBREQ', 'none', 'none'],
+	15: ['gpio', 'none', 'nCS_1', 'none'],
+	16: ['gpio', 'none', 'PWM0', 'none'],
+	17: ['gpio', 'none', 'PWM1', 'none'],
+	18: ['gpio', 'RDY', 'none', 'none'],
+	19: ['gpio', 'DREQ[1]', 'none', 'none'],
+	20: ['gpio', 'DREQ[0]', 'none', 'none'],
+	21: ['gpio', 'none', 'none', 'none'],
+	22: ['gpio', 'none', 'none', 'none'],
+	23: ['gpio', 'none', 'SSP SCLK', 'none'],
+	24: ['gpio', 'none', 'SSP SFRM', 'none'],
+	25: ['gpio', 'none', 'SSP TXD', 'none'],
+	26: ['gpio', 'SSP RXD', 'none', 'none'],
+	27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
+	28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
+	29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
+	30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
+	31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
+	32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
+	33: ['gpio', 'none', 'nCS_5', 'none'],
+	34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
+	35: ['gpio', 'FF CTS', 'none', 'none'],
+	36: ['gpio', 'FF DCD', 'none', 'none'],
+	37: ['gpio', 'FF DSR', 'none', 'none'],
+	38: ['gpio', 'FF RI', 'none', 'none'],
+	39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
+	40: ['gpio', 'none', 'FF DTR', 'none'],
+	41: ['gpio', 'none', 'FF RTS', 'none'],
+	42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
+	43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
+	44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
+	45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
+	46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
+	47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
+	48: ['gpio', 'HW TXD', 'nPOE', 'none'],
+	49: ['gpio', 'HW RXD', 'nPWE', 'none'],
+	50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
+	51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
+	52: ['gpio', 'none', 'nPCE[1]', 'none'],
+	53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
+	54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
+	55: ['gpio', 'none', 'nPREG', 'none'],
+	56: ['gpio', 'nPWAIT', 'none', 'none'],
+	57: ['gpio', 'nIOIS16', 'none', 'none'],
+	58: ['gpio', 'none', 'LDD[0]', 'none'],
+	59: ['gpio', 'none', 'LDD[1]', 'none'],
+	60: ['gpio', 'none', 'LDD[2]', 'none'],
+	61: ['gpio', 'none', 'LDD[3]', 'none'],
+	62: ['gpio', 'none', 'LDD[4]', 'none'],
+	63: ['gpio', 'none', 'LDD[5]', 'none'],
+	64: ['gpio', 'none', 'LDD[6]', 'none'],
+	65: ['gpio', 'none', 'LDD[7]', 'none'],
+	66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
+	67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
+	68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
+	69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
+	70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
+	71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
+	72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
+	73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
+	74: ['gpio', 'none', 'LCD_FCLK', 'none'],
+	75: ['gpio', 'none', 'LCD_LCLK', 'none'],
+	76: ['gpio', 'none', 'LCD_PCLK', 'none'],
+	77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
+	78: ['gpio', 'none', 'nCS_2', 'none'],
+	79: ['gpio', 'none', 'nCS_3', 'none'],
+	80: ['gpio', 'none', 'nCS_4', 'none'],
+	81: ['gpio', 'NSSPSCLK', 'none', 'none'],
+	82: ['gpio', 'NSSPSFRM', 'none', 'none'],
+	83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+	84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+}
+
+
+#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+
+gpio_list = []
+
+for i in range(0,85):
+	gpio_list.append(gpio())
+
+#chip select GPIOs
+gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
+gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
+gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
+gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
+gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
+gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
+gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
+gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
+gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
+gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
+
+# PCMCIA stuff
+gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
+gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
+gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
+gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
+gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
+gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
+gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
+gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
+gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
+gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
+
+# SSP port
+gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
+gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
+gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
+gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
+gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
+
+# audio codec
+gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
+gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
+gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
+gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
+gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
+
+# serial ports
+gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
+gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
+gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
+gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
+gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
+gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
+gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
+gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
+
+gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
+gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
+gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
+gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
+
+gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
+gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
+
+# misc GPIO signals
+gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
+gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
+gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
+gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
+gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
+gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
+gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
+gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
+gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
+gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
+gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
+gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
+gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
+gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
+gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
+
+# LCD GPIOs
+gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
+gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
+gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
+gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
+gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
+gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
+gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
+gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
+gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
+gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
+gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
+gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
+gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
+gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
+gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
+gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
+gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
+gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
+gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
+gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
+
+# calculate registers
+pxa_regs = {
+	'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
+	'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
+	'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
+	'gafr0_l':0, 'gafr0_u':0,
+	'gafr1_l':0, 'gafr1_u':0,
+	'gafr2_l':0, 'gafr2_u':0,
+}
+
+# U-boot define names
+uboot_reg_names = {
+	'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
+	'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
+	'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
+	'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
+	'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
+	'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
+}
+
+# bit mappings
+
+bit_mappings = [
+
+{ 'gpio':(0,32),  'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
+{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
+{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
+{ 'gpio':(0,16),  'shift':2, 'regs':{'alt':'gafr0_l'} },
+{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
+{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
+{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
+{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
+{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
+
+]
+
+def stuff_bits(bit_mapping, gpio_list):
+	gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
+
+	for gpio in gpios:
+		for reg in bit_mapping['regs'].keys():
+			value = eval( 'gpio_list[gpio].%s' % (reg) )
+			if ( value ):
+				# we have a high bit
+				bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
+				bit = value << (bit_shift)
+				pxa_regs[bit_mapping['regs'][reg]] |= bit
+
+for i in bit_mappings:
+	stuff_bits(i, gpio_list)
+
+# now print out all regs
+registers = pxa_regs.keys()
+registers.sort()
+for reg in registers:
+	print '%s: 0x%x' % (reg, pxa_regs[reg])
+
+# print define to past right into U-Boot source code
+
+print 
+print 
+
+for reg in registers:
+	print '#define %s	0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
+
+# print all GPIOS
+print
+print
+
+for i in range(len(gpio_list)):
+	gpio_i = gpio_list[i]
+	alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
+	print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
+
+
diff --git a/u-boot/board/qemu-mips/Makefile b/u-boot/board/qemu-mips/Makefile
new file mode 100644
index 0000000..6251bb8
--- /dev/null
+++ b/u-boot/board/qemu-mips/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	 $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/qemu-mips/README b/u-boot/board/qemu-mips/README
new file mode 100644
index 0000000..565241b
--- /dev/null
+++ b/u-boot/board/qemu-mips/README
@@ -0,0 +1,15 @@
+By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01
+----------------------------------------
+Qemu is a full system emulator. See
+
+http://www.nongnu.org/qemu/
+
+Limitations & comments
+----------------------
+Supports the "-m mips" configuration of qemu: serial,NE2000,IDE.
+Support is big endian only for now (or at least this is what I tested).
+Derived from au1x00 with a lot of things cut out.
+
+Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
+recent qemu versions. When using emulated flash, launch with
+-pflash <filename> and erase mips_bios.bin.
diff --git a/u-boot/board/qemu-mips/config.mk b/u-boot/board/qemu-mips/config.mk
new file mode 100644
index 0000000..27cd34a
--- /dev/null
+++ b/u-boot/board/qemu-mips/config.mk
@@ -0,0 +1,10 @@
+#
+# Qemu -M mips system emulator
+# See http://fabrice.bellard.free.fr/qemu
+#
+
+# ROM version
+CONFIG_SYS_TEXT_BASE = 0xbfc00000
+
+# RAM version
+#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/u-boot/board/qemu-mips/lowlevel_init.S b/u-boot/board/qemu-mips/lowlevel_init.S
new file mode 100644
index 0000000..b0f7072
--- /dev/null
+++ b/u-boot/board/qemu-mips/lowlevel_init.S
@@ -0,0 +1,40 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set K0=3)
+	 */
+	li	t1, 0x00000003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+	jr	ra
+	nop
diff --git a/u-boot/board/qemu-mips/qemu-mips.c b/u-boot/board/qemu-mips/qemu-mips.c
new file mode 100644
index 0000000..7a69a00
--- /dev/null
+++ b/u-boot/board/qemu-mips/qemu-mips.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2007
+ * Vlad Lungu vlad.lungu@windriver.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+
+phys_size_t initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return MEM_SIZE*1024*1024;
+}
+
+int checkboard(void)
+{
+	u32 proc_id;
+	u32 config1;
+
+	proc_id = read_c0_prid();
+	printf("Board: Qemu -M mips CPU: ");
+	switch (proc_id) {
+	case 0x00018000:
+		printf("4Kc");
+		break;
+	case 0x00018400:
+		printf("4KEcR1");
+		break;
+	case 0x00019000:
+		printf("4KEc");
+		break;
+	case 0x00019300:
+		config1 = read_c0_config1();
+		if (config1 & 1)
+			printf("24Kf");
+		else
+			printf("24Kc");
+		break;
+	case 0x00019500:
+		printf("34Kf");
+		break;
+	case 0x00000400:
+		printf("R4000");
+		break;
+	case 0x00018100:
+		config1 = read_c0_config1();
+		if (config1 & 1)
+			printf("5Kf");
+		else
+			printf("5Kc");
+		break;
+	case 0x000182a0:
+		printf("20Kc");
+		break;
+
+	default:
+		printf("unknown");
+	}
+	printf(" proc_id=0x%x\n", proc_id);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	set_io_port_base(0);
+	return 0;
+}
diff --git a/u-boot/board/qemu-mips/u-boot.lds b/u-boot/board/qemu-mips/u-boot.lds
new file mode 100644
index 0000000..bd16786
--- /dev/null
+++ b/u-boot/board/qemu-mips/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) +0x7ff0;
+
+	.got  : {
+	__got_start = .;
+		*(.got)
+	__got_end = .;
+	}
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	. = .;
+	.u_boot_cmd : {
+	__u_boot_cmd_start = .;
+	*(.u_boot_cmd)
+	__u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/quad100hd/Makefile b/u-boot/board/quad100hd/Makefile
new file mode 100644
index 0000000..4ceb344
--- /dev/null
+++ b/u-boot/board/quad100hd/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o nand.o
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/quad100hd/nand.c b/u-boot/board/quad100hd/nand.c
new file mode 100644
index 0000000..a222099
--- /dev/null
+++ b/u-boot/board/quad100hd/nand.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#if defined(CONFIG_CMD_NAND)
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+static void quad100hd_hwcontrol(struct mtd_info *mtd,
+				int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
+		gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
+		gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int quad100hd_nand_ready(struct mtd_info *mtd)
+{
+	return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
+}
+
+/*
+ * Main initialization routine
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	/* Set address of hardware control function */
+	nand->cmd_ctrl = quad100hd_hwcontrol;
+	nand->dev_ready = quad100hd_nand_ready;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	/* 15 us command delay time */
+	nand->chip_delay =  20;
+
+	/* Return happy */
+	return 0;
+}
+#endif /* CONFIG_CMD_NAND */
diff --git a/u-boot/board/quad100hd/quad100hd.c b/u-boot/board/quad100hd/quad100hd.c
new file mode 100644
index 0000000..2f72d2b
--- /dev/null
+++ b/u-boot/board/quad100hd/quad100hd.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on board/icecube/icecube.c from PPCBoot
+ * (C) Copyright 2003 Intrinsyc Software
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* taken from PPCBoot */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7FFE);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+	mtdcr(CPC0_SRR, 0x00040000);   /* Hold PCI bridge in reset */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+#ifdef DISPLAY_BOARD_INFO
+	sys_info_t sysinfo;
+#endif
+
+	puts("Board: Quad100hd");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+#ifdef DISPLAY_BOARD_INFO
+	/* taken from ppcboot */
+	get_sys_info(&sysinfo);
+
+	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
+	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
+		1000000));
+	printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+#endif
+
+	return 0;
+}
diff --git a/u-boot/board/quantum/Makefile b/u-boot/board/quantum/Makefile
new file mode 100644
index 0000000..d44a260
--- /dev/null
+++ b/u-boot/board/quantum/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o fpga.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/quantum/fpga.c b/u-boot/board/quantum/fpga.c
new file mode 100644
index 0000000..092aaab
--- /dev/null
+++ b/u-boot/board/quantum/fpga.c
@@ -0,0 +1,263 @@
+/*
+ * (C) Copyright 2001-2003
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* The DEBUG define must be before common to enable debugging */
+#undef DEBUG
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include "fpga.h"
+/* ------------------------------------------------------------------------- */
+
+#define MAX_ONES               226
+
+/* MPC850 port D */
+#define PD(bit) (1 << (15 - (bit)))
+# define FPGA_INIT             PD(11)	/* FPGA init pin (ppc input)     */
+# define FPGA_PRG              PD(12)	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              PD(13)	/* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             PD(14)	/* FPGA data pin (ppc output)    */
+# define FPGA_DONE             PD(15)	/* FPGA done pin (ppc input)     */
+
+
+/* DDR 0 - input, 1 - output */
+#define FPGA_INIT_PDDIR          FPGA_PRG | FPGA_CLK | FPGA_DATA	/* just set outputs */
+
+
+#define SET_FPGA(data)         immr->im_ioport.iop_pddat = (data)
+#define GET_FPGA               immr->im_ioport.iop_pddat
+
+#define FPGA_WRITE_1 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);}	/* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);}	/* set data to 1  */
+
+
+int fpga_boot (unsigned char *fpgadata, int size)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	int i, index, len;
+	int count;
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	int j;
+	unsigned char data;
+#else
+	unsigned char b;
+	int bit;
+#endif
+
+	debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size);
+
+	/* display infos on fpgaimage */
+	printf ("FPGA:");
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf (" %s", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+	printf ("\n");
+
+
+	index = 0;
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	debug ("FPGA: configdata starts at position 0x%x\n", index);
+	debug ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR;
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (GET_FPGA & FPGA_INIT) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(GET_FPGA & FPGA_INIT)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	debug ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+		if ((i % 1024) == 0)
+			printf ("%6d out of %6d\r", i, size);	/* let them know we are alive */
+#endif
+
+		data = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			if ((data & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			data <<= 1;
+		}
+	}
+	/* add some 0xff to the end of the file */
+	for (i = 0; i < 8; i++) {
+		data = 0xff;
+		for (j = 0; j < 8; j++) {
+			if ((data & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			data <<= 1;
+		}
+	}
+#else
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif
+	debug ("\n\n");
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(GET_FPGA & FPGA_DONE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	debug ("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/u-boot/board/quantum/fpga.h b/u-boot/board/quantum/fpga.h
new file mode 100644
index 0000000..79b73b5
--- /dev/null
+++ b/u-boot/board/quantum/fpga.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the QUANTUM computer
+ */
+int fpga_boot(unsigned char *fpgadata, int size);
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
diff --git a/u-boot/board/quantum/quantum.c b/u-boot/board/quantum/quantum.c
new file mode 100644
index 0000000..d94b5d7
--- /dev/null
+++ b/u-boot/board/quantum/quantum.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "fpga.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+unsigned long flash_init (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 * (Initialization code at 0x36)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board QUANTUM, Serial No: ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+	putc ('\n');
+	return (0);		/* success */
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+			   SDRAM_MAX_SIZE);
+	/*
+	 * Final mapping:
+	 */
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	udelay (1000);
+
+	return (size9);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile ulong *addr;
+	ulong cnt, val, size;
+	ulong save[32];		/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *)(base + cnt);	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = (volatile ulong *)base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
+		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+			addr = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *)(base + cnt);	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long);
+			     cnt <<= 1) {
+				addr = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
+		}
+	}
+	return (maxsize);
+}
+
+/*
+ * Miscellaneous intialization
+ */
+int misc_init_r (void)
+{
+	char *fpga_data_str = getenv ("fpgadata");
+	char *fpga_size_str = getenv ("fpgasize");
+	void *fpga_data;
+	int fpga_size;
+	int status;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	int flash_size;
+
+	/* Remap FLASH according to real size */
+	flash_size = flash_init ();
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	if (fpga_data_str && fpga_size_str) {
+		fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
+		fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
+
+		status = fpga_boot (fpga_data, fpga_size);
+		if (status != 0) {
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+		}
+	}
+	return 0;
+}
diff --git a/u-boot/board/quantum/u-boot.lds b/u-boot/board/quantum/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/quantum/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/quantum/u-boot.lds.debug b/u-boot/board/quantum/u-boot.lds.debug
new file mode 100644
index 0000000..f212fab
--- /dev/null
+++ b/u-boot/board/quantum/u-boot.lds.debug
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/r360mpi/Makefile b/u-boot/board/r360mpi/Makefile
new file mode 100644
index 0000000..4072ef7
--- /dev/null
+++ b/u-boot/board/r360mpi/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o pcmcia.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/r360mpi/flash.c b/u-boot/board/r360mpi/flash.c
new file mode 100644
index 0000000..45cccf7
--- /dev/null
+++ b/u-boot/board/r360mpi/flash.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CONFIG_SYS_FLASH_BASE,
+				CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	FPW value;
+
+	/* Make sure Block Lock Bits get cleared */
+	addr[0] = (FPW) 0x00FF00FF;
+	addr[0] = (FPW) 0x00600060;
+	addr[0] = (FPW) 0x00D000D0;
+	addr[0] = (FPW) 0x00FF00FF;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	value = addr[1];			/* device ID        */
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
diff --git a/u-boot/board/r360mpi/pcmcia.c b/u-boot/board/r360mpi/pcmcia.c
new file mode 100644
index 0000000..85da41b
--- /dev/null
+++ b/u-boot/board/r360mpi/pcmcia.c
@@ -0,0 +1,236 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "R360MPI"
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, mask;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+	/*
+	* Configure SIUMCR to enable PCMCIA port B
+	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	*/
+	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	* Disable interrupts, DMA, and PCMCIA buffers
+	* (isolate the interface) and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Configure Ports A, B & C pins for
+	* 5 Volts Enable and 3 Volts enable
+	*/
+	immap->im_ioport.iop_pcpar &= ~(0x0400);
+	immap->im_ioport.iop_pcso  &= ~(0x0400);/*
+	immap->im_ioport.iop_pcdir |= 0x0400;*/
+
+	immap->im_ioport.iop_papar &= ~(0x0200);/*
+	immap->im_ioport.iop_padir |= 0x0200;*/
+#if 0
+	immap->im_ioport.iop_pbpar &= ~(0xC000);
+	immap->im_ioport.iop_pbdir &= ~(0xC000);
+#endif
+	/* remove all power */
+
+	immap->im_ioport.iop_pcdat |= 0x0400;
+	immap->im_ioport.iop_padat |= 0x0200;
+
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	* Power On.
+	*/
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	reg  = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       reg,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+	if ((reg & mask) == mask) {
+		immap->im_ioport.iop_pcdat &= ~(0x4000);
+		puts (" 5.0V card found: ");
+	} else {
+		immap->im_ioport.iop_padat &= ~(0x0002);
+		puts (" 3.3V card found: ");
+	}
+	immap->im_ioport.iop_pcdir |= 0x0400;
+	immap->im_ioport.iop_padir |= 0x0200;
+#if 0
+	/*  VCC switch error flag, PCMCIA slot INPACK_ pin */
+	cp->cp_pbdir &= ~(0x0020 | 0x0010);
+	cp->cp_pbpar &= ~(0x0020 | 0x0010);
+	udelay(500000);
+#endif
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* remove all power */
+	immap->im_ioport.iop_pcdat |= 0x0400;
+	immap->im_ioport.iop_padat |= 0x0200;
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("voltage_set: "
+			PCMCIA_BOARD_MSG
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	* Disable PCMCIA buffers (isolate the interface)
+	* and assert RESET signal
+	*/
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	* Configure Ports A & C pins for
+	* 5 Volts Enable and 3 Volts enable,
+	* Turn off all power
+	*/
+	debug ("PCMCIA power OFF\n");
+	immap->im_ioport.iop_pcpar &= ~(0x0400);
+	immap->im_ioport.iop_pcso  &= ~(0x0400);/*
+	immap->im_ioport.iop_pcdir |= 0x0400;*/
+
+	immap->im_ioport.iop_papar &= ~(0x0200);/*
+	immap->im_ioport.iop_padir |= 0x0200;*/
+
+	immap->im_ioport.iop_pcdat |= 0x0400;
+	immap->im_ioport.iop_padat |= 0x0200;
+
+	reg = 0;
+	switch(vcc) {
+		case  0:		break;
+		case 33: reg |= 0x0200;	break;
+		case 50: reg |= 0x0400;	break;
+		default:		goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+	       pcmp->pcmc_pipr,
+	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+	if (reg & 0x0200)
+		immap->im_ioport.iop_pcdat &= !reg;
+	if (reg & 0x0400)
+		immap->im_ioport.iop_padat &= !reg;
+	immap->im_ioport.iop_pcdir |= 0x0200;
+	immap->im_ioport.iop_padir |= 0x0400;
+	if (reg) {
+		debug ("PCMCIA powered at %sV\n",
+		       (reg&0x0400) ? "5.0" : "3.3");
+	} else {
+		debug ("PCMCIA powered down\n");
+	}
+
+done:
+			debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CCONFIG_PCMCIA */
diff --git a/u-boot/board/r360mpi/r360mpi.c b/u-boot/board/r360mpi/r360mpi.c
new file mode 100644
index 0000000..b5315ad
--- /dev/null
+++ b/u-boot/board/r360mpi/r360mpi.c
@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+#include <i2c.h>
+
+#include <commproc.h>
+#include <command.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h>       /* for strdup */
+
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory		(0x40000000)
+ *  CS1 - FLASH memory		(0x????????)
+ *  CS2 - SDRAM			(0x00000000)
+ *  CS3 -
+ *  CS4 -
+ *  CS5 -
+ *  CS6 - PCMCIA device
+ *  CS7 - PCMCIA device
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[]=
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: R360 MPI Board\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 2 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 2 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {			/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;		/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+#ifdef CONFIG_CAN_DRIVER
+	/* Initialize OR3 / BR3 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */
+	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
+
+	/* Initialize MBMR */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
+
+	/* Initialize UPMB for CAN: single read */
+	memctl->memc_mdr = 0xFFFFC004;
+	memctl->memc_mcr = 0x0100 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFD004;
+	memctl->memc_mcr = 0x0101 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFC000;
+	memctl->memc_mcr = 0x0102 | UPMB;
+
+	memctl->memc_mdr = 0x3FFFC004;
+	memctl->memc_mcr = 0x0103 | UPMB;
+
+	memctl->memc_mdr = 0xFFFFDC05;
+	memctl->memc_mcr = 0x0104 | UPMB;
+
+	/* Initialize UPMB for CAN: single write */
+	memctl->memc_mdr = 0xFFFCC004;
+	memctl->memc_mcr = 0x0118 | UPMB;
+
+	memctl->memc_mdr = 0xCFFCD004;
+	memctl->memc_mcr = 0x0119 | UPMB;
+
+	memctl->memc_mdr = 0x0FFCC000;
+	memctl->memc_mcr = 0x011A | UPMB;
+
+	memctl->memc_mdr = 0x7FFCC004;
+	memctl->memc_mcr = 0x011B | UPMB;
+
+	memctl->memc_mdr = 0xFFFDCC05;
+	memctl->memc_mcr = 0x011C | UPMB;
+#endif
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value,
+			   long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void r360_i2c_lcd_write (uchar data0, uchar data1)
+{
+	if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
+		printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*-----------------------------------------------------------------------
+ * Keyboard Controller
+ */
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_KEY_MAX	16				/* maximum key number */
+#define KEYBD_DATALEN	((KEYBD_KEY_MAX + 7) / 8)	/* normal key scan data */
+
+static uchar *key_match (uchar *);
+
+int misc_init_r (void)
+{
+	char kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	char *str;
+	int i;
+
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
+
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+	}
+	setenv ("keybd", keybd_env);
+
+	str = strdup ((char *)key_match ((uchar *)keybd_env));	/* decode keys */
+
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Check if pressed key(s) match magic sequence,
+ * and return the command string associated with that key(s).
+ *
+ * If no key press was decoded, NULL is returned.
+ *
+ * Note: the first character of the argument will be overwritten with
+ * the "magic charcter code" of the decoded key(s), or '\0'.
+ *
+ *
+ * Note: the string points to static environment data and must be
+ * saved before you call any function that modifies the environment.
+ */
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static uchar *key_match (uchar * kbd_str)
+{
+	uchar magic[sizeof (kbd_magic_prefix) + 1];
+	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+	uchar *str, *suffix;
+	uchar *kbd_magic_keys;
+	char *cmd;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
+		/* loop over all magic keys;
+		 * use '\0' suffix in case of empty string
+		 */
+		for (suffix = kbd_magic_keys;
+		     *suffix || suffix == kbd_magic_keys;
+		     ++suffix) {
+			sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
+
+#if 0
+			printf ("### Check magic \"%s\"\n", magic);
+#endif
+
+			if ((str = (uchar *)getenv ((char *)magic)) != 0) {
+
+#if 0
+				printf ("### Compare \"%s\" \"%s\"\n",
+					kbd_str, str);
+#endif
+				if (strcmp ((char *)kbd_str, (char *)str) == 0) {
+					sprintf ((char *)cmd_name, "%s%c",
+						 kbd_command_prefix,
+						 *suffix);
+
+					if ((cmd = getenv ((char *)cmd_name)) != 0) {
+#if 0
+						printf ("### Set PREBOOT to $(%s): \"%s\"\n",
+							cmd_name, cmd);
+#endif
+						return ((uchar *)cmd);
+					}
+				}
+			}
+		}
+	}
+#if 0
+	printf ("### Delete PREBOOT\n");
+#endif
+	*kbd_str = '\0';
+	return (NULL);
+}
+#endif	/* CONFIG_PREBOOT */
+
+/* Read Keyboard status */
+int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar keybd_env[2 * KEYBD_DATALEN + 1];
+	int i;
+
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/* Read keys */
+	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
+		printf (" %02x", kbd_data[i]);
+	}
+	putc ('\n');
+	setenv ("keybd", (char *)keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
+	"read keyboard status",
+	""
+);
diff --git a/u-boot/board/r360mpi/u-boot.lds b/u-boot/board/r360mpi/u-boot.lds
new file mode 100644
index 0000000..a18c515
--- /dev/null
+++ b/u-boot/board/r360mpi/u-boot.lds
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+  . = ALIGN(128 * 1024);
+  .ppcenv	:
+  {
+    common/env_embedded.o (.ppcenv)
+  }
+}
diff --git a/u-boot/board/rattler/Makefile b/u-boot/board/rattler/Makefile
new file mode 100644
index 0000000..9079aad
--- /dev/null
+++ b/u-boot/board/rattler/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/rattler/rattler.c b/u-boot/board/rattler/rattler.c
new file mode 100644
index 0000000..80f57dc
--- /dev/null
+++ b/u-boot/board/rattler/rattler.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Rattler boards family.
+ * Tested on Rattler8248.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 1,          0,   0,   1,   0,   1 }, /* Eth PHYs reset  */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK10) */
+	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
+	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK15) */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
+	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+	/* PD15 */ { 0,          0,   0,   0,   0,   0 }, /* PD15            */
+	/* PD14 */ { 0,          0,   0,   0,   0,   0 }, /* PD14            */
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+phys_size_t initdram(int board_type)
+{
+	long int msize = CONFIG_SYS_SDRAM_SIZE;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
+	uchar c = 0xFF;
+	uint psdmr = CONFIG_SYS_PSDMR;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
+	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
+	return 0;
+}
diff --git a/u-boot/board/rbc823/Makefile b/u-boot/board/rbc823/Makefile
new file mode 100644
index 0000000..72bbc2f
--- /dev/null
+++ b/u-boot/board/rbc823/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o kbd.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/rbc823/flash.c b/u-boot/board/rbc823/flash.c
new file mode 100644
index 0000000..cb1e089
--- /dev/null
+++ b/u-boot/board/rbc823/flash.c
@@ -0,0 +1,469 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	/* Detect size */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* Setup offsets */
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	size_b1 = 0 ;
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Fix this to support variable sector sizes
+*/
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK)
+	{
+		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	if (info->size >> 20) {
+	    printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+	} else {
+	    printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10,
+		info->sector_count);
+	}
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	putc ('\n');
+	return;
+}
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr;
+	char value;
+
+	caddr = (volatile unsigned char *)addr ;
+
+	/* Write auto select command: read Manufacturer ID */
+
+#if 0
+	printf("Base address is: %08x\n", caddr);
+#endif
+
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	value = caddr[0];
+
+#if 0
+	printf("Manufact ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case 0x01: /*AMD_MANUFACT*/
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case 0x04: /*FUJ_MANUFACT*/
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = caddr[1];			/* device ID		*/
+#if 0
+	printf("Device ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;				/* => 512Kb		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		caddr = (volatile unsigned char *)info->start[0];
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile unsigned char *)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+
+	while ((addr[0] & 0xFF) != 0xFF)
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
+				*cdest,*cdata;
+	ulong start;
+	int flag, count = 4 ;
+
+	cdest = (volatile unsigned char *)dest ;
+	cdata = (volatile unsigned char *)&data ;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	while(count--)
+	{
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    addr[0x0555] = 0xAA;
+	    addr[0x02AA] = 0x55;
+	    addr[0x0555] = 0xA0;
+
+	    *cdest = *cdata;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((*cdest ^ *cdata) & 0x80)
+	    {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	    }
+
+	    cdata++ ;
+	    cdest++ ;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/rbc823/kbd.c b/u-boot/board/rbc823/kbd.c
new file mode 100644
index 0000000..853cbde
--- /dev/null
+++ b/u-boot/board/rbc823/kbd.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Modified by Udi Finkelstein
+ *
+ * This file includes communication routines for SMC1 that can run even if
+ * SMC2 have already been initialized.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <commproc.h>
+#include <stdio_dev.h>
+#include <lcd.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	SMC_INDEX	0
+#define PROFF_SMC	PROFF_SMC1
+#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
+
+#define RBC823_KBD_BAUDRATE	38400
+#define CPM_KEYBOARD_BASE	0x1000
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+void smc1_setbrg (void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+
+	/* Set up the baud rate generator.
+	 * See 8xx_io/commproc.c for details.
+	 *
+	 * Wire BRG2 to SMC1, BRG1 to SMC2
+	 */
+
+	cp->cp_simode = 0x00001000;
+
+	cp->cp_brgc2 =
+		(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
+}
+
+int smc1_init (void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile smc_t *sp;
+	volatile smc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	uint	dpaddr;
+
+	/* initialize pointers to SMC */
+
+	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
+	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+
+	/* Enable SDMA.
+	*/
+	im->im_siu_conf.sc_sdcr = 1;
+
+	/* clear error conditions */
+#ifdef	CONFIG_SYS_SDSR
+	im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
+#else
+	im->im_sdma.sdma_sdsr = 0x83;
+#endif
+
+	/* clear SDMA interrupt mask */
+#ifdef	CONFIG_SYS_SDMR
+	im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
+#else
+	im->im_sdma.sdma_sdmr = 0x00;
+#endif
+
+	/* Use Port B for SMC1 instead of other functions.
+	*/
+	cp->cp_pbpar |=  0x000000c0;
+	cp->cp_pbdir &= ~0x000000c0;
+	cp->cp_pbodr &= ~0x000000c0;
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+
+#ifdef CONFIG_SYS_ALLOC_DPRAM
+	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+#else
+	dpaddr = CPM_KEYBOARD_BASE ;
+#endif
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * For now, this address seems OK, but it may have to
+	 * change with newer versions of the firmware.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = 0;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = 0;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->smc_rbase = dpaddr;
+	up->smc_tbase = dpaddr+sizeof(cbd_t);
+	up->smc_rfcr = SMC_EB;
+	up->smc_tfcr = SMC_EB;
+
+	/* Set UART mode, 8 bit, no parity, one stop.
+	 * Enable receive and transmit.
+	 */
+	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->smc_smcm = 0;
+	sp->smc_smce = 0xff;
+
+	/* Set up the baud rate generator.
+	*/
+	smc1_setbrg ();
+
+	/* Make the first buffer the only buffer.
+	*/
+	tbdf->cbd_sc |= BD_SC_WRAP;
+	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+
+	/* Single character receive.
+	*/
+	up->smc_mrblr = 1;
+	up->smc_maxidl = 0;
+
+	/* Initialize Tx/Rx parameters.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+
+	return (0);
+}
+
+void smc1_putc(const char c)
+{
+	volatile cbd_t		*tbdf;
+	volatile char		*buf;
+	volatile smc_uart_t	*up;
+	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
+
+	/* Wait for last character to go.
+	*/
+
+	buf = (char *)tbdf->cbd_bufaddr;
+
+	*buf = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+	__asm__("eieio");
+
+	while (tbdf->cbd_sc & BD_SC_READY) {
+		WATCHDOG_RESET ();
+		__asm__("eieio");
+	}
+}
+
+int smc1_getc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile unsigned char	*buf;
+	volatile smc_uart_t	*up;
+	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+	unsigned char		c;
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	/* Wait for character to show up.
+	*/
+	buf = (unsigned char *)rbdf->cbd_bufaddr;
+
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		WATCHDOG_RESET ();
+
+	c = *buf;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return(c);
+}
+
+int smc1_tstc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile smc_uart_t	*up;
+	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+}
+
+/* search for keyboard and register it if found */
+int drv_keyboard_init(void)
+{
+	int error = 0;
+	struct stdio_dev kbd_dev;
+
+	if (0) {
+		/* register the keyboard */
+		memset (&kbd_dev, 0, sizeof(struct stdio_dev));
+		strcpy(kbd_dev.name, "kbd");
+		kbd_dev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+		kbd_dev.putc = NULL;
+		kbd_dev.puts = NULL;
+		kbd_dev.getc = smc1_getc;
+		kbd_dev.tstc = smc1_tstc;
+		error = stdio_register (&kbd_dev);
+	} else {
+		lcd_is_enabled = 0;
+		lcd_disable();
+	}
+	return error;
+}
diff --git a/u-boot/board/rbc823/rbc823.c b/u-boot/board/rbc823/rbc823.c
new file mode 100644
index 0000000..e10d9f9
--- /dev/null
+++ b/u-boot/board/rbc823/rbc823.c
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+#include <linux/mtd/doc2000.h>
+
+extern int kbd_init(void);
+extern int drv_kbd_init(void);
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x1FF7FC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+const uint static_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
+	0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
+	0xFFFFFC04, 0xFFFFFC05, /* last */
+	                        _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
+	0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	if (!s || strncmp (s, "TQM8", 4)) {
+		printf ("### No HW ID - assuming RBC823\n");
+		return (0);
+	}
+
+	puts (s);
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * 1 Bank of 64Mbit x 2 devices
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	udelay (200);
+
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80008105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+	udelay (200);
+	memctl->memc_mcr = 0x80008130;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
+			   SDRAM_MAX_SIZE);
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns     */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {		/* back to 8 columns                    */
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/* SDRAM Bank 0 is bigger - map first       */
+
+	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+#ifdef CONFIG_CMD_DOC
+void doc_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig (UPMB, (uint *) static_table,
+		   sizeof (static_table) / sizeof (uint));
+	memctl->memc_mbmr = MAMR_DSA_1_CYCL;
+
+	doc_probe (FLASH_BASE1_PRELIM);
+}
+#endif
diff --git a/u-boot/board/rbc823/u-boot.lds b/u-boot/board/rbc823/u-boot.lds
new file mode 100644
index 0000000..77f592e
--- /dev/null
+++ b/u-boot/board/rbc823/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    lib/libgeneric.o			(.text*)
+    net/libnet.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    arch/powerpc/lib/libpowerpc.o	(.text*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/renesas/MigoR/Makefile b/u-boot/board/renesas/MigoR/Makefile
new file mode 100644
index 0000000..3529810
--- /dev/null
+++ b/u-boot/board/renesas/MigoR/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= migo_r.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/MigoR/lowlevel_init.S b/u-boot/board/renesas/MigoR/lowlevel_init.S
new file mode 100644
index 0000000..e32a7af
--- /dev/null
+++ b/u-boot/board/renesas/MigoR/lowlevel_init.S
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2007-2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	write32	CCR_A, CCR_D		! Address of Cache Control Register
+					! Instruction Cache Invalidate
+
+	write32	MMUCR_A, MMUCR_D	! Address of MMU Control Register
+					! TI == TLB Invalidate bit
+
+	write32	MSTPCR0_A, MSTPCR0_D	! Address of Power Control Register 0
+
+	write32	MSTPCR2_A, MSTPCR2_D	! Address of Power Control Register 2
+
+	write16	PFC_PULCR_A, PFC_PULCR_D
+
+	write16	PFC_DRVCR_A, PFC_DRVCR_D
+
+	write16	SBSCR_A, SBSCR_D
+
+	write16	PSCR_A, PSCR_D
+
+	write16	RWTCSR_A, RWTCSR_D_1	! 0xA4520004 (Watchdog Control / Status Register)
+					! 0xA507 -> timer_STOP / WDT_CLK = max
+
+	write16	RWTCNT_A, RWTCNT_D	! 0xA4520000 (Watchdog Count Register)
+					! 0x5A00 -> Clear
+
+	write16	RWTCSR_A, RWTCSR_D_2	! 0xA4520004 (Watchdog Control / Status Register)
+					! 0xA504 -> timer_STOP / CLK = 500ms
+
+	write32	DLLFRQ_A, DLLFRQ_D	! 20080115
+					! 20080115
+
+	write32	FRQCR_A, FRQCR_D	! 0xA4150000 Frequency control register
+					! 20080115
+
+	write32	CCR_A, CCR_D_2		! Address of Cache Control Register
+					! ??
+
+bsc_init:
+	write32	CMNCR_A, CMNCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS4BCR_A, CS4BCR_D
+
+	write32	CS5ABCR_A, CS5ABCR_D
+
+	write32	CS5BBCR_A, CS5BBCR_D
+
+	write32	CS6ABCR_A, CS6ABCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+	write32	CS4WCR_A, CS4WCR_D
+
+	write32	CS5AWCR_A, CS5AWCR_D
+
+	write32	CS5BWCR_A, CS5BWCR_D
+
+	write32	CS6AWCR_A, CS6AWCR_D
+
+	! SDRAM initialization
+	write32	SDCR_A, SDCR_D
+
+	write32	SDWCR_A, SDWCR_D
+
+	write32	SDPCR_A, SDPCR_D
+
+	write32	RTCOR_A, RTCOR_D
+
+	write32	RTCNT_A, RTCNT_D
+
+	write32	RTCSR_A, RTCSR_D
+
+	write32	RFCR_A, RFCR_D
+
+	write8	SDMR3_A, SDMR3_D
+
+	! BL bit off (init = ON) (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	mov	#0, r0
+
+	.align	4
+
+CCR_A:		.long	CCR
+MMUCR_A:	.long	MMUCR
+MSTPCR0_A:	.long	MSTPCR0
+MSTPCR2_A:	.long	MSTPCR2
+PFC_PULCR_A:	.long	PULCR
+PFC_DRVCR_A:	.long	DRVCR
+SBSCR_A:	.long	SBSCR
+PSCR_A:		.long	PSCR
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+PLLCR_A:	.long	PLLCR
+DLLFRQ_A:	.long	DLLFRQ
+
+CCR_D:		.long	0x00000800
+CCR_D_2:	.long	0x00000103
+MMUCR_D:	.long	0x00000004
+MSTPCR0_D:	.long	0x00001001
+MSTPCR2_D:	.long	0xffffffff
+PFC_PULCR_D:	.long	0x6000
+PFC_DRVCR_D:	.long	0x0464
+FRQCR_D:	.long	0x07033639
+PLLCR_D:	.long	0x00005000
+DLLFRQ_D:	.long	0x000004F6
+
+CMNCR_A:	.long	CMNCR
+CMNCR_D:	.long	0x0000001B
+CS0BCR_A:	.long	CS0BCR
+CS0BCR_D:	.long	0x24920400
+CS4BCR_A:	.long	CS4BCR
+CS4BCR_D:	.long	0x00003400
+CS5ABCR_A:	.long	CS5ABCR
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_A:	.long	CS5BBCR
+CS5BBCR_D:	.long	0x24920400
+CS6ABCR_A:	.long	CS6ABCR
+CS6ABCR_D:	.long	0x24920400
+
+CS0WCR_A:	.long	CS0WCR
+CS0WCR_D:	.long	0x00000380
+CS4WCR_A:	.long	CS4WCR
+CS4WCR_D:	.long	0x00110080
+CS5AWCR_A:	.long	CS5AWCR
+CS5AWCR_D:	.long	0x00000300
+CS5BWCR_A:	.long	CS5BWCR
+CS5BWCR_D:	.long	0x00000300
+CS6AWCR_A:	.long	CS6AWCR
+CS6AWCR_D:	.long	0x00000300
+
+SDCR_A:		.long	SBSC_SDCR
+SDCR_D:		.long	0x80160809
+SDWCR_A:	.long	SBSC_SDWCR
+SDWCR_D:	.long	0x0014450C
+SDPCR_A:	.long	SBSC_SDPCR
+SDPCR_D:	.long	0x00000087
+RTCOR_A:	.long	SBSC_RTCOR
+RTCNT_A:	.long	SBSC_RTCNT
+RTCNT_D:	.long	0xA55A0012
+RTCOR_D:	.long	0xA55A001C
+RTCSR_A:	.long	SBSC_RTCSR
+RFCR_A:		.long	SBSC_RFCR
+RFCR_D:		.long	0xA55A0221
+RTCSR_D:	.long	0xA55A009a
+SDMR3_A:	.long	0xFE581180
+SDMR3_D:	.long	0x0
+
+SR_MASK_D:	.long	0xEFFFFF0F
+
+	.align	2
+
+SBSCR_D:	.word	0x0044
+PSCR_D:		.word	0x0000
+RWTCSR_D_1:	.word	0xA507
+RWTCSR_D_2:	.word	0xA504
+RWTCNT_D:	.word	0x5A00
diff --git a/u-boot/board/renesas/MigoR/migo_r.c b/u-boot/board/renesas/MigoR/migo_r.c
new file mode 100644
index 0000000..75b653f
--- /dev/null
+++ b/u-boot/board/renesas/MigoR/migo_r.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/migo_r.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas MigoR\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/renesas/ap325rxa/Makefile b/u-boot/board/renesas/ap325rxa/Makefile
new file mode 100644
index 0000000..5a2a0f3
--- /dev/null
+++ b/u-boot/board/renesas/ap325rxa/Makefile
@@ -0,0 +1,51 @@
+#########################################################################
+#
+# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/ap325rxa/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ap325rxa.o cpld-ap325rxa.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/ap325rxa/ap325rxa.c b/u-boot/board/renesas/ap325rxa/ap325rxa.c
new file mode 100644
index 0000000..758e6f4
--- /dev/null
+++ b/u-boot/board/renesas/ap325rxa/ap325rxa.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PRI control register */
+#define PRPRICR5	0xFF800048 /* LMB */
+#define PRPRICR5_D	0x2a
+
+/* FPGA control */
+#define FPGA_NAND_CTL	0xB410020C
+#define FPGA_NAND_RST	0x0008
+#define FPGA_NAND_INIT	0x0000
+#define FPGA_NAND_RST_WAIT	10000
+
+/* I/O port data */
+#define PACR_D	0x0000
+#define PBCR_D	0x0000
+#define PCCR_D	0x1000
+#define PDCR_D	0x0000
+#define PECR_D	0x0410
+#define PFCR_D	0xffff
+#define PGCR_D	0x0000
+#define PHCR_D	0x5011
+#define PJCR_D	0x4400
+#define PKCR_D	0x7c00
+#define PLCR_D	0x0000
+#define PMCR_D	0x0000
+#define PNCR_D	0x0000
+#define PQCR_D	0x0000
+#define PRCR_D	0x0000
+#define PSCR_D	0x0000
+#define PTCR_D	0x0010
+#define PUCR_D	0x0fff
+#define PVCR_D	0xffff
+#define PWCR_D	0x0000
+#define PXCR_D	0x7500
+#define PYCR_D	0x0000
+#define PZCR_D	0x5540
+
+/* Pin Function Controler data */
+#define PSELA_D	0x1410
+#define PSELB_D	0x0140
+#define PSELC_D	0x0000
+#define PSELD_D	0x0400
+
+/* I/O Buffer Hi-Z data */
+#define	HIZCRA_D	0x0000
+#define HIZCRB_D	0x1000
+#define HIZCRC_D	0x0000
+#define HIZCRD_D	0x0000
+
+/* Module select reg data */
+#define MSELCRA_D	0x0014
+#define MSELCRB_D	0x0018
+
+/* Module Stop reg Data */
+#define MSTPCR2_D	0xFFD9F280
+
+/* CPLD loader */
+extern void init_cpld(void);
+
+int checkboard(void)
+{
+	puts("BOARD: AP325RXA\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Pin Function Controler Init */
+	outw(PSELA_D, PSELA);
+	outw(PSELB_D, PSELB);
+	outw(PSELC_D, PSELC);
+	outw(PSELD_D, PSELD);
+
+	/* I/O Buffer Hi-Z Init */
+	outw(HIZCRA_D, HIZCRA);
+	outw(HIZCRB_D, HIZCRB);
+	outw(HIZCRC_D, HIZCRC);
+	outw(HIZCRD_D, HIZCRD);
+
+	/* Module select reg Init */
+	outw(MSELCRA_D, MSELCRA);
+	outw(MSELCRB_D, MSELCRB);
+
+	/* Module Stop reg Init */
+	outl(MSTPCR2_D, MSTPCR2);
+
+	/* I/O ports */
+	outw(PACR_D, PACR);
+	outw(PBCR_D, PBCR);
+	outw(PCCR_D, PCCR);
+	outw(PDCR_D, PDCR);
+	outw(PECR_D, PECR);
+	outw(PFCR_D, PFCR);
+	outw(PGCR_D, PGCR);
+	outw(PHCR_D, PHCR);
+	outw(PJCR_D, PJCR);
+	outw(PKCR_D, PKCR);
+	outw(PLCR_D, PLCR);
+	outw(PMCR_D, PMCR);
+	outw(PNCR_D, PNCR);
+	outw(PQCR_D, PQCR);
+	outw(PRCR_D, PRCR);
+	outw(PSCR_D, PSCR);
+	outw(PTCR_D, PTCR);
+	outw(PUCR_D, PUCR);
+	outw(PVCR_D, PVCR);
+	outw(PWCR_D, PWCR);
+	outw(PXCR_D, PXCR);
+	outw(PYCR_D, PYCR);
+	outw(PZCR_D, PZCR);
+
+	/* PRI control register Init */
+	outl(PRPRICR5_D, PRPRICR5);
+
+	/* cpld init */
+	init_cpld();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+void ide_set_reset(int idereset)
+{
+	outw(FPGA_NAND_RST, FPGA_NAND_CTL);	/* NAND RESET */
+	udelay(FPGA_NAND_RST_WAIT);
+	outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c b/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c
new file mode 100644
index 0000000..16fadcb
--- /dev/null
+++ b/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c
@@ -0,0 +1,206 @@
+/***************************************************************
+ * Project:
+ *	  CPLD SlaveSerial Configuration via embedded microprocessor.
+ *
+ * Copyright info:
+ *
+ *	  This is free software; you can redistribute it and/or modify
+ *	  it as you like.
+ *
+ *	  This program is distributed in the hope that it will be useful,
+ *	  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *	  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Description:
+ *
+ *      This is the main source file that will allow a microprocessor
+ *      to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
+ *      and Spartan-II devices via the SlaveSerial Configuration Mode.
+ *      This code is discussed in Xilinx Application Note, XAPP502.
+ *
+ * History:
+ *	  3-October-2001  MN/MP  - Created
+ *	  20-August-2008  Renesas Solutions - Modified to SH7723
+ ****************************************************************/
+
+#include <common.h>
+
+/* Serial */
+#define SCIF_BASE 0xffe00000 /* SCIF0 */
+#define SCSMR	(vu_short *)(SCIF_BASE + 0x00)
+#define SCBRR	(vu_char *)(SCIF_BASE + 0x04)
+#define SCSCR	(vu_short *)(SCIF_BASE + 0x08)
+#define SC_TDR	(vu_char *)(SCIF_BASE + 0x0C)
+#define SC_SR	(vu_short *)(SCIF_BASE + 0x10)
+#define SCFCR	(vu_short *)(SCIF_BASE + 0x18)
+#define	RFCR	(vu_long *)0xFE400020
+
+#define SCSCR_INIT		0x0038
+#define SCSCR_CLR		0x0000
+#define SCFCR_INIT		0x0006
+#define SCSMR_INIT		0x0080
+#define RFCR_CLR		0xA400
+#define SCI_TD_E		0x0020
+#define SCI_TDRE_CLEAR	0x00df
+
+#define BPS_SETTING_VALUE	1 /* 12.5MHz */
+#define WAIT_RFCR_COUNTER	500
+
+/* CPLD data size */
+#define CPLD_DATA_SIZE	169216
+
+/* out */
+#define CPLD_PFC_ADR	((vu_short *)0xA4050112)
+
+#define CPLD_PROG_ADR	((vu_char *)0xA4050132)
+#define CPLD_PROG_DAT	0x80
+
+/* in */
+#define CPLD_INIT_ADR	((vu_char *)0xA4050132)
+#define CPLD_INIT_DAT	0x40
+#define CPLD_DONE_ADR	((vu_char *)0xA4050132)
+#define CPLD_DONE_DAT	0x20
+
+#define	HIZCRB			((vu_short *)0xA405015A)
+
+/* data */
+#define CPLD_NOMAL_START	0xA0A80000
+#define CPLD_SAFE_START		0xA0AC0000
+#define MODE_SW				(vu_char *)0xA405012A
+
+static void init_cpld_loader(void)
+{
+
+	*SCSCR = SCSCR_CLR;
+	*SCFCR = SCFCR_INIT;
+	*SCSMR = SCSMR_INIT;
+
+	*SCBRR = BPS_SETTING_VALUE;
+
+	*RFCR = RFCR_CLR; /* Refresh counter clear */
+
+	while (*RFCR < WAIT_RFCR_COUNTER)
+		;
+
+	*SCFCR = 0x0; /* RTRG=00, TTRG=00 */
+				  /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
+	*SCSCR = SCSCR_INIT;
+}
+
+static int check_write_ready(void)
+{
+	u16 status = *SC_SR;
+	return status & SCI_TD_E;
+}
+
+static void write_cpld_data(char ch)
+{
+	while (!check_write_ready())
+		;
+
+	*SC_TDR = ch;
+	*SC_SR;
+	*SC_SR = SCI_TDRE_CLEAR;
+}
+
+static int delay(void)
+{
+	int i;
+	int c = 0;
+	for (i = 0; i < 200; i++) {
+		c = *(volatile int *)0xa0000000;
+	}
+	return c;
+}
+
+/***********************************************************************
+ *
+ * Function:     slave_serial
+ *
+ * Description:  Initiates SlaveSerial Configuration.
+ *               Calls ShiftDataOut() to output serial data
+ *
+ ***********************************************************************/
+static void slave_serial(void)
+{
+	int i;
+	unsigned char *flash;
+
+	*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+	delay();
+
+	/*
+	 * Toggle Program Pin by Toggling Program_OE bit
+	 * This is accomplished by writing to the Program Register in the CPLD
+	 *
+	 * NOTE: The Program_OE bit should be driven high to bring the Virtex
+	 *      Program Pin low. Likewise, it should be driven low
+	 *      to bring the Virtex Program Pin to High-Z
+	 */
+
+	*CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
+	delay();
+
+	/*
+	 * Bring Program High-Z
+	 * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
+	 */
+
+	/* Program_OE bit Low brings the Virtex Program Pin to High Z: */
+	*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+
+	while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
+		delay();
+
+	/* Begin Slave-Serial Configuration */
+	flash = (unsigned char *)CPLD_NOMAL_START;
+
+	for (i = 0; i < CPLD_DATA_SIZE; i++)
+		write_cpld_data(*flash++);
+}
+
+/***********************************************************************
+ *
+ * Function: check_done_bit
+ *
+ * Description: This function takes monitors the CPLD Input Register
+ * 		   by checking the status of the DONE bit in that Register.
+ *               By doing so, it monitors the Xilinx Virtex device's DONE
+ *               Pin to see if configuration bitstream has been properly
+ *               loaded
+ *
+ ***********************************************************************/
+static void check_done_bit(void)
+{
+	while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
+		;
+}
+
+/***********************************************************************
+ *
+ * Function: init_cpld
+ *
+ * Description: Begins Slave Serial configuration of Xilinx FPGA
+ *
+ ***********************************************************************/
+void init_cpld(void)
+{
+	/* Init serial device */
+	init_cpld_loader();
+
+	if (*CPLD_DONE_ADR & CPLD_DONE_DAT)	/* Already DONE */
+		return;
+
+	*HIZCRB = 0x0000;
+	*CPLD_PFC_ADR = 0x7c00;			/* FPGA PROG = OUTPUT */
+
+	/* write CPLD data from NOR flash to device */
+	slave_serial();
+
+	/*
+	 * Monitor the DONE bit in the CPLD Input Register to see if
+	 * configuration successful
+	 */
+
+	check_done_bit();
+}
diff --git a/u-boot/board/renesas/ap325rxa/lowlevel_init.S b/u-boot/board/renesas/ap325rxa/lowlevel_init.S
new file mode 100644
index 0000000..04cfef1
--- /dev/null
+++ b/u-boot/board/renesas/ap325rxa/lowlevel_init.S
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/ap325rxa/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	write16	DRVCRA_A, DRVCRA_D
+
+	write16	DRVCRB_A, DRVCRB_D
+
+	write16	RWTCSR_A, RWTCSR_D1
+
+	write16	RWTCNT_A, RWTCNT_D
+
+	write16	RWTCSR_A, RWTCSR_D2
+
+	write32	FRQCR_A, FRQCR_D
+
+	write32	CMNCR_A, CMNCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS4BCR_A, CS4BCR_D
+
+	write32	CS5ABCR_A, CS5ABCR_D
+
+	write32	CS5BBCR_A, CS5BBCR_D
+
+	write32	CS6ABCR_A, CS6ABCR_D
+
+	write32	CS6BBCR_A, CS6BBCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+	write32	CS4WCR_A, CS4WCR_D
+
+	write32	CS5AWCR_A, CS5AWCR_D
+
+	write32	CS5BWCR_A, CS5BWCR_D
+
+	write32	CS6AWCR_A, CS6AWCR_D
+
+	write32	CS6BWCR_A, CS6BWCR_D
+
+	write32	SBSC_SDCR_A, SBSC_SDCR_D1
+
+	write32	SBSC_SDWCR_A, SBSC_SDWCR_D
+
+	write32	SBSC_SDPCR_A, SBSC_SDPCR_D
+
+	write32	SBSC_RTCSR_A, SBSC_RTCSR_D
+
+	write32	SBSC_RTCNT_A, SBSC_RTCNT_D
+
+	write32	SBSC_RTCOR_A, SBSC_RTCOR_D
+
+	write8	SBSC_SDMR3_A1, SBSC_SDMR3_D
+
+	write8	SBSC_SDMR3_A2, SBSC_SDMR3_D
+
+	mov.l	SLEEP_CNT, r1
+2:	tst	r1, r1
+	nop
+	bf/s	2b
+	dt	r1
+
+	write8	SBSC_SDMR3_A3, SBSC_SDMR3_D
+
+	write32	SBSC_SDCR_A, SBSC_SDCR_D2
+
+	write32	CCR_A, CCR_D
+
+	! BL bit off (init = ON) (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	 mov	#0, r0
+
+	.align	2
+
+DRVCRA_A:	.long	DRVCRA
+DRVCRB_A:	.long	DRVCRB
+DRVCRA_D:	.word	0x4555
+DRVCRB_D:	.word	0x0005
+
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+RWTCSR_D1:	.word	0xa507
+RWTCSR_D2:	.word	0xa504
+RWTCNT_D:	.word	0x5a00
+.align 2
+FRQCR_D:	.long	0x0b04474a
+
+SBSC_SDCR_A:	.long	SBSC_SDCR
+SBSC_SDWCR_A:	.long	SBSC_SDWCR
+SBSC_SDPCR_A:	.long	SBSC_SDPCR
+SBSC_RTCSR_A:	.long	SBSC_RTCSR
+SBSC_RTCNT_A:	.long	SBSC_RTCNT
+SBSC_RTCOR_A:	.long	SBSC_RTCOR
+SBSC_SDMR3_A1:	.long	0xfe510000
+SBSC_SDMR3_A2:	.long	0xfe500242
+SBSC_SDMR3_A3:	.long	0xfe5c0042
+
+SBSC_SDCR_D1:	.long	0x92810112
+SBSC_SDCR_D2:	.long	0x92810912
+SBSC_SDWCR_D:	.long	0x05162482
+SBSC_SDPCR_D:	.long	0x00300087
+SBSC_RTCSR_D:	.long	0xa55a0212
+SBSC_RTCNT_D:	.long	0xa55a0000
+SBSC_RTCOR_D:	.long	0xa55a0040
+SBSC_SDMR3_D:	.long	0x00
+
+CMNCR_A:	.long	CMNCR
+CS0BCR_A:	.long	CS0BCR
+CS4BCR_A:	.long	CS4BCR
+CS5ABCR_A:	.long	CS5ABCR
+CS5BBCR_A:	.long	CS5BBCR
+CS6ABCR_A:	.long	CS6ABCR
+CS6BBCR_A:	.long	CS6BBCR
+CS0WCR_A:	.long	CS0WCR
+CS4WCR_A:	.long	CS4WCR
+CS5AWCR_A:	.long	CS5AWCR
+CS5BWCR_A:	.long	CS5BWCR
+CS6AWCR_A:	.long	CS6AWCR
+CS6BWCR_A:	.long	CS6BWCR
+
+CMNCR_D:	.long	0x00000013
+CS0BCR_D:	.long	0x24920400
+CS4BCR_D:	.long	0x24920400
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_D:	.long	0x7fff0600
+CS6ABCR_D:	.long	0x24920400
+CS6BBCR_D:	.long	0x24920600
+CS0WCR_D:	.long	0x00000480
+CS4WCR_D:	.long	0x00000480
+CS5AWCR_D:	.long	0x00000380
+CS5BWCR_D:	.long	0x00000080
+CS6AWCR_D:	.long	0x00000300
+CS6BWCR_D:	.long	0x00000540
+
+CCR_A:		.long	0xff00001c
+CCR_D:		.long	0x0000090d
+
+SLEEP_CNT:	.long	0x00000800
+SR_MASK_D:	.long	0xEFFFFF0F
diff --git a/u-boot/board/renesas/r2dplus/Makefile b/u-boot/board/renesas/r2dplus/Makefile
new file mode 100644
index 0000000..7d92354
--- /dev/null
+++ b/u-boot/board/renesas/r2dplus/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= r2dplus.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/r2dplus/lowlevel_init.S b/u-boot/board/renesas/r2dplus/lowlevel_init.S
new file mode 100644
index 0000000..f3392f0
--- /dev/null
+++ b/u-boot/board/renesas/r2dplus/lowlevel_init.S
@@ -0,0 +1,118 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global lowlevel_init
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write32	CCR_A, CCR_D_D
+
+	write32	MMUCR_A, MMUCR_D
+
+	write32	BCR1_A, BCR1_D
+
+	write16	BCR2_A, BCR2_D
+
+	write16	BCR3_A, BCR3_D
+
+	write32	BCR4_A, BCR4_D
+
+	write32	WCR1_A, WCR1_D
+
+	write32	WCR2_A, WCR2_D
+
+	write32	WCR3_A, WCR3_D
+
+	write16	PCR_A, PCR_D
+
+	write16	LED_A, LED_D
+
+	write32	MCR_A, MCR_D1
+
+	write16	RTCNT_A, RTCNT_D
+
+	write16	RTCOR_A, RTCOR_D
+
+	write16	RFCR_A, RFCR_D
+
+	write16	RTCSR_A, RTCSR_D
+
+	write8	SDMR3_A, SDMR3_D0
+
+	/* Wait DRAM refresh 30 times */
+	mov.l	RFCR_A, r1
+	mov	#30, r3
+1:
+	mov.w	@r1, r0
+	extu.w	r0, r2
+	cmp/hi	r3, r2
+	bf	1b
+
+	write32	MCR_A, MCR_D2
+
+	write8	SDMR3_A, SDMR3_D1
+
+	write32	IRLMASK_A, IRLMASK_D
+
+	write32	CCR_A, CCR_D_E
+
+	rts
+	nop
+
+	.align	2
+CCR_A:		.long	CCR		/* Cache Control Register */
+CCR_D_D:	.long	0x0808		/* Flush the cache, disable */
+CCR_D_E:	.long	0x8000090B
+
+FRQCR_A:	.long	FRQCR		/* FRQCR Address */
+FRQCR_D:	.long	0x00000e0a	/* 03/07/15 modify */
+BCR1_A:		.long	BCR1		/* BCR1 Address */
+BCR1_D:		.long	0x00180008
+BCR2_A:		.long	BCR2		/* BCR2 Address */
+BCR2_D:		.long	0xabe8
+BCR3_A:		.long	BCR3		/* BCR3 Address */
+BCR3_D:		.long	0x0000
+BCR4_A:		.long	BCR4		/* BCR4 Address */
+BCR4_D:		.long	0x00000010
+WCR1_A:		.long	WCR1		/* WCR1 Address */
+WCR1_D:		.long	0x33343333
+WCR2_A:		.long	WCR2		/* WCR2 Address */
+WCR2_D:		.long	0xcff86fbf
+WCR3_A:		.long	WCR3		/* WCR3 Address */
+WCR3_D:		.long	0x07777707
+LED_A:		.long	0x04000036	/* LED Address */
+LED_D:		.long	0xFF		/* LED Data */
+RTCNT_A:	.long	RTCNT		/* RTCNT Address */
+RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
+.align 2
+RTCOR_A:	.long	RTCOR		/* RTCOR Address */
+RTCOR_D:	.word	0xA534		/* RTCOR Write Code */
+.align 2
+RTCSR_A:	.long	RTCSR		/* RTCSR Address */
+RTCSR_D:	.word	0xA510		/* RTCSR Write Code */
+.align 2
+SDMR3_A:	.long	0xFF9400CC	/* SDMR3 Address */
+SDMR3_D0:	.long	0x55
+SDMR3_D1:	.long	0x00
+MCR_A:		.long	MCR		/* MCR Address */
+MCR_D1:		.long	0x081901F4	/* MRSET:'0' */
+MCR_D2:		.long	0x481901F4	/* MRSET:'1' */
+RFCR_A:		.long	RFCR		/* RFCR Address */
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
+PCR_A:		.long	PCR		/* PCR Address */
+PCR_D:		.long	0x0000
+MMUCR_A:	.long	MMUCR		/* MMUCCR Address */
+MMUCR_D:	.long	0x00000000	/* MMUCCR Data */
+IRLMASK_A:	.long	0xA4000000	/* IRLMASK Address */
+IRLMASK_D:	.long	0x00000000	/* IRLMASK Data */
diff --git a/u-boot/board/renesas/r2dplus/r2dplus.c b/u-boot/board/renesas/r2dplus/r2dplus.c
new file mode 100644
index 0000000..b70395d
--- /dev/null
+++ b/u-boot/board/renesas/r2dplus/r2dplus.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Solutions R2D Plus\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#define FPGA_BASE		0xA4000000
+#define FPGA_CFCTL		(FPGA_BASE + 0x04)
+#define CFCTL_EN		(0x432)
+#define FPGA_CFPOW		(FPGA_BASE + 0x06)
+#define CFPOW_ON		(0x02)
+#define FPGA_CFCDINTCLR	(FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN	(0x01)
+
+void ide_set_reset(int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset) {
+		outw(CFCTL_EN, FPGA_CFCTL);	/* CF enable */
+		outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+		outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
+	}
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+	pci_sh7751_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/renesas/r7780mp/Makefile b/u-boot/board/renesas/r7780mp/Makefile
new file mode 100644
index 0000000..14c5e42
--- /dev/null
+++ b/u-boot/board/renesas/r7780mp/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r7780mp/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= r7780mp.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/r7780mp/lowlevel_init.S b/u-boot/board/renesas/r7780mp/lowlevel_init.S
new file mode 100644
index 0000000..bbea621
--- /dev/null
+++ b/u-boot/board/renesas/r7780mp/lowlevel_init.S
@@ -0,0 +1,371 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * u-boot/board/r7780mp/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
+					/* Instruction Cache Invalidate */
+
+	write32	FRQCR_A, FRQCR_D	/* Frequency control register */
+
+	/* pin_multi_setting */
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1
+
+	write32	BBG_PMSR1_A, BBG_PMSR1_D
+
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2
+
+	write32	BBG_PMSR2_A, BBG_PMSR2_D
+
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3
+
+	write32	BBG_PMSR3_A, BBG_PMSR3_D
+
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4
+
+	write32	BBG_PMSR4_A, BBG_PMSR4_D
+
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG
+
+	write32	BBG_PMSRG_A, BBG_PMSRG_D
+
+	/* cpg_setting */
+	write32	FRQCR_A, FRQCR_D
+
+	write32	DLLCSR_A, DLLCSR_D
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* wait 200us */
+	mov.l	REPEAT0_R3, r3
+	mov	#0, r2
+repeat0:
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat0
+	nop
+
+	/* bsc_setting */
+	write32	MMSELR_A, MMSELR_D
+
+	write32	BCR_A, BCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS1BCR_A, CS1BCR_D
+
+	write32	CS2BCR_A, CS2BCR_D
+
+	write32	CS4BCR_A, CS4BCR_D
+
+	write32	CS5BCR_A, CS5BCR_D
+
+	write32	CS6BCR_A, CS6BCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+	write32	CS1WCR_A, CS1WCR_D
+
+	write32	CS2WCR_A, CS2WCR_D
+
+	write32	CS4WCR_A, CS4WCR_D
+
+	write32	CS5WCR_A, CS5WCR_D
+
+	write32	CS6WCR_A, CS6WCR_D
+
+	write32	CS5PCR_A, CS5PCR_D
+
+	write32	CS6PCR_A, CS6PCR_D
+
+	/* ddr_setting */
+	/* wait 200us */
+	mov.l	REPEAT0_R3, r3
+	mov	#0, r2
+repeat1:
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat1
+	nop
+
+	mov.l	MIM_U_A, r0
+	mov.l	MIM_U_D, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	mov.l	MIM_L_A, r0
+	mov.l	MIM_L_D0, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	mov.l	STR_L_A, r0
+	mov.l	STR_L_D, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	mov.l	SDR_L_A, r0
+	mov.l	SDR_L_D, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+	nop
+
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D0, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D1, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	EMRS_A, r0
+	mov.l	EMRS_D, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	MRS1_A, r0
+	mov.l	MRS1_D, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D2, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D3, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D4, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	MRS2_A, r0
+	mov.l	MRS2_D, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	nop
+	nop
+	nop
+
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D5, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	/* wait 200us */
+	mov.l	REPEAT0_R1, r3
+	mov	#0, r2
+repeat2:
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat2
+
+	synco
+
+	mov.l	MIM_L_A, r0
+	mov.l	MIM_L_D1, r1
+	synco
+	mov.l	r1, @r0
+	synco
+
+	rts
+	nop
+	.align	4
+
+RWTCSR_D_1:		.word	0xA507
+RWTCSR_D_2:		.word	0xA507
+RWTCNT_D:		.word	0x5A00
+	.align	2
+
+BBG_PMMR_A:		.long	0xFF800010
+BBG_PMSR1_A:		.long	0xFF800014
+BBG_PMSR2_A:		.long	0xFF800018
+BBG_PMSR3_A:		.long	0xFF80001C
+BBG_PMSR4_A:		.long	0xFF800020
+BBG_PMSRG_A:		.long	0xFF800024
+
+BBG_PMMR_D_PMSR1:	.long	0xffffbffd
+BBG_PMSR1_D:		.long	0x00004002
+BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
+BBG_PMSR2_D:		.long	0x03de5800
+BBG_PMMR_D_PMSR3:	.long	0xfffffff8
+BBG_PMSR3_D:		.long	0x00000007
+BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
+BBG_PMSR4_D:		.long	0x20020006
+BBG_PMMR_D_PMSRG:	.long	0xffffffff
+BBG_PMSRG_D:		.long	0x00000000
+
+FRQCR_A:		.long	FRQCR
+DLLCSR_A:		.long	0xffc40010
+FRQCR_D:		.long	0x40233035
+DLLCSR_D:		.long	0x00000000
+
+/* for DDR-SDRAM */
+MIM_U_A:		.long	MIM_1
+MIM_L_A:		.long	MIM_2
+SCR_U_A:		.long	SCR_1
+SCR_L_A:		.long	SCR_2
+STR_U_A:		.long	STR_1
+STR_L_A:		.long	STR_2
+SDR_U_A:		.long	SDR_1
+SDR_L_A:		.long	SDR_2
+
+EMRS_A:			.long	0xFEC02000
+MRS1_A:			.long	0xFEC00B08
+MRS2_A:			.long	0xFEC00308
+
+MIM_U_D:		.long	0x00004000
+MIM_L_D0:		.long	0x03e80009
+MIM_L_D1:		.long	0x03e80209
+SCR_L_D0:		.long	0x3
+SCR_L_D1:		.long	0x2
+SCR_L_D2:		.long	0x2
+SCR_L_D3:		.long	0x4
+SCR_L_D4:		.long	0x4
+SCR_L_D5:		.long	0x0
+STR_L_D:		.long	0x000f0000
+SDR_L_D:		.long	0x00000400
+EMRS_D:			.long	0x0
+MRS1_D:			.long	0x0
+MRS2_D:			.long	0x0
+
+/* Cache Controller */
+CCR_A:			.long	CCR
+MMUCR_A:		.long	MMUCR
+RWTCNT_A:		.long	WTCNT
+
+CCR_D:			.long	0x0000090b
+CCR_D_2:		.long	0x00000103
+MMUCR_D:		.long	0x00000004
+MSTPCR0_D:		.long	0x00001001
+MSTPCR2_D:		.long	0xffffffff
+
+/* local Bus State Controller */
+MMSELR_A:		.long	MMSELR
+BCR_A:			.long	BCR
+CS0BCR_A:		.long	CS0BCR
+CS1BCR_A:		.long	CS1BCR
+CS2BCR_A:		.long	CS2BCR
+CS4BCR_A:		.long	CS4BCR
+CS5BCR_A:		.long	CS5BCR
+CS6BCR_A:		.long	CS6BCR
+CS0WCR_A:		.long	CS0WCR
+CS1WCR_A:		.long	CS1WCR
+CS2WCR_A:		.long	CS2WCR
+CS4WCR_A:		.long	CS4WCR
+CS5WCR_A:		.long	CS5WCR
+CS6WCR_A:		.long	CS6WCR
+CS5PCR_A:		.long	CS5PCR
+CS6PCR_A:		.long	CS6PCR
+
+MMSELR_D:		.long	0xA5A50003
+BCR_D:			.long	0x00000000
+CS0BCR_D:		.long	0x77777770
+CS1BCR_D:		.long	0x77777670
+CS2BCR_D:		.long	0x77777770
+CS4BCR_D:		.long	0x77777770
+CS5BCR_D:		.long	0x77777670
+CS6BCR_D:		.long	0x77777770
+CS0WCR_D:		.long	0x00020006
+CS1WCR_D:		.long	0x00232304
+CS2WCR_D:		.long	0x7777770F
+CS4WCR_D:		.long	0x7777770F
+CS5WCR_D:		.long	0x00101006
+CS6WCR_D:		.long	0x77777703
+CS5PCR_D:		.long	0x77000000
+CS6PCR_D:		.long	0x77000000
+
+REPEAT0_R3:		.long	0x00002000
+REPEAT0_R1:		.long	0x0000200
diff --git a/u-boot/board/renesas/r7780mp/r7780mp.c b/u-boot/board/renesas/r7780mp/r7780mp.c
new file mode 100644
index 0000000..0b80099
--- /dev/null
+++ b/u-boot/board/renesas/r7780mp/r7780mp.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <netdev.h>
+#include "r7780mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+#if defined(CONFIG_R7780MP)
+	puts("BOARD: Renesas Solutions R7780MP\n");
+#else
+	puts("BOARD: Renesas Solutions R7780RP\n");
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* SCIF Enable */
+	writew(0x0, PHCR);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+
+}
+
+void ide_set_reset(int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset) {
+		writew(0x432, FPGA_CFCTL);
+#if defined(CONFIG_R7780MP)
+		writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
+#else
+		writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
+#endif
+		writew(0x01, FPGA_CFCDINTCLR);
+	}
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+	pci_sh7780_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/renesas/r7780mp/r7780mp.h b/u-boot/board/renesas/r7780mp/r7780mp.h
new file mode 100644
index 0000000..476a413
--- /dev/null
+++ b/u-boot/board/renesas/r7780mp/r7780mp.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/board/r7780mp/r7780mp.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_R7780MP_R7780MP_H_
+#define _BOARD_R7780MP_R7780MP_H_
+
+/* R7780MP's FPGA register map */
+#define FPGA_BASE          0xa4000000
+#define FPGA_IRLMSK        (FPGA_BASE + 0x00)
+#define FPGA_IRLMON        (FPGA_BASE + 0x02)
+#define FPGA_IRLPRI1       (FPGA_BASE + 0x04)
+#define FPGA_IRLPRI2       (FPGA_BASE + 0x06)
+#define FPGA_IRLPRI3       (FPGA_BASE + 0x08)
+#define FPGA_IRLPRI4       (FPGA_BASE + 0x0A)
+#define FPGA_RSTCTL        (FPGA_BASE + 0x0C)
+#define FPGA_PCIBD         (FPGA_BASE + 0x0E)
+#define FPGA_PCICD         (FPGA_BASE + 0x10)
+#define FPGA_EXTGIO        (FPGA_BASE + 0x16)
+#define FPGA_IVDRMON       (FPGA_BASE + 0x18)
+#define FPGA_IVDRCR        (FPGA_BASE + 0x1A)
+#define FPGA_OBLED         (FPGA_BASE + 0x1C)
+#define FPGA_OBSW          (FPGA_BASE + 0x1E)
+#define FPGA_TPCTL         (FPGA_BASE + 0x100)
+#define FPGA_TPDCKCTL      (FPGA_BASE + 0x102)
+#define FPGA_TPCLR         (FPGA_BASE + 0x104)
+#define FPGA_TPXPOS        (FPGA_BASE + 0x106)
+#define FPGA_TPYPOS        (FPGA_BASE + 0x108)
+#define FPGA_DBSW          (FPGA_BASE + 0x200)
+#define FPGA_VERSION       (FPGA_BASE + 0x700)
+#define FPGA_CFCTL         (FPGA_BASE + 0x300)
+#define FPGA_CFPOW         (FPGA_BASE + 0x302)
+#define FPGA_CFCDINTCLR    (FPGA_BASE + 0x304)
+#define FPGA_PMR           (FPGA_BASE + 0x900)
+
+#endif /* _BOARD_R7780RP_R7780RP_H_ */
diff --git a/u-boot/board/renesas/rsk7203/Makefile b/u-boot/board/renesas/rsk7203/Makefile
new file mode 100644
index 0000000..f908ba0
--- /dev/null
+++ b/u-boot/board/renesas/rsk7203/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+# Copyright (C) 2008 Renesas Solutions Corp.
+#
+# u-boot/board/rsk7203/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).o
+
+OBJS	:= rsk7203.o
+SOBJS	:= lowlevel_init.o
+
+LIB	:= $(addprefix $(obj),$(LIB))
+OBJS	:= $(addprefix $(obj),$(OBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/rsk7203/lowlevel_init.S b/u-boot/board/renesas/rsk7203/lowlevel_init.S
new file mode 100644
index 0000000..30ef5ab
--- /dev/null
+++ b/u-boot/board/renesas/rsk7203/lowlevel_init.S
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	/* Cache setting */
+	write32	CCR1_A ,CCR1_D
+
+	/* ConfigurePortPins */
+	write16	PECRL3_A, PECRL3_D
+
+	write16	PCCRL4_A, PCCRL4_D0
+
+	write16	PECRL4_A, PECRL4_D0
+
+	write16	PEIORL_A, PEIORL_D0
+
+	write16	PCIORL_A, PCIORL_D
+
+	write16	PFCRH2_A, PFCRH2_D
+
+	write16	PFCRH3_A, PFCRH3_D
+
+	write16	PFCRH1_A, PFCRH1_D
+
+	write16	PFIORH_A, PFIORH_D
+
+	write16	PECRL1_A, PECRL1_D0
+
+	write16	PEIORL_A, PEIORL_D1
+
+	/* Configure Operating Frequency */
+	write16	WTCSR_A, WTCSR_D0
+
+	write16	WTCSR_A, WTCSR_D1
+
+	write16	WTCNT_A, WTCNT_D
+
+	/* Set clock mode*/
+	write16	FRQCR_A, FRQCR_D
+
+	/* Configure Bus And Memory */
+init_bsc_cs0:
+	write16	PCCRL4_A, PCCRL4_D1
+
+	write16	PECRL1_A, PECRL1_D1
+
+	write32	CMNCR_A, CMNCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+init_bsc_cs1:
+	write16	PECRL4_A, PECRL4_D1
+
+	write32	CS1WCR_A, CS1WCR_D
+
+init_sdram:
+	write16	PCCRL2_A, PCCRL2_D
+
+	write16	PCCRL4_A, PCCRL4_D2
+
+	write16	PCCRL1_A, PCCRL1_D
+
+	write16	PCCRL3_A, PCCRL3_D
+
+	write32	CS3BCR_A, CS3BCR_D
+
+	write32	CS3WCR_A, CS3WCR_D
+
+	write32	SDCR_A, SDCR_D
+
+	write32	RTCOR_A, RTCOR_D
+
+	write32	RTCSR_A, RTCSR_D
+
+	/* wait 200us */
+	mov.l	REPEAT_D, r3
+	mov	#0, r2
+repeat0:
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat0
+	nop
+
+	mov.l	SDRAM_MODE, r1
+	mov	#0, r0
+	mov.l	r0, @r1
+
+	nop
+	rts
+
+	.align 4
+
+CCR1_A:		.long CCR1
+CCR1_D:		.long 0x0000090B
+PCCRL4_A:	.long 0xFFFE3910
+PCCRL4_D0:	.word 0x0000
+.align 2
+PECRL4_A:	.long 0xFFFE3A10
+PECRL4_D0:	.word 0x0000
+.align 2
+PECRL3_A:	.long 0xFFFE3A12
+PECRL3_D:	.word 0x0000
+.align 2
+PEIORL_A:	.long 0xFFFE3A06
+PEIORL_D0:	.word 0x1C00
+PEIORL_D1:	.word 0x1C02
+PCIORL_A:	.long 0xFFFE3906
+PCIORL_D:	.word 0x4000
+.align 2
+PFCRH2_A:	.long 0xFFFE3A8C
+PFCRH2_D:	.word 0x0000
+.align 2
+PFCRH3_A:	.long 0xFFFE3A8A
+PFCRH3_D:	.word 0x0000
+.align 2
+PFCRH1_A:	.long 0xFFFE3A8E
+PFCRH1_D:	.word 0x0000
+.align 2
+PFIORH_A:	.long 0xFFFE3A84
+PFIORH_D:	.word 0x0729
+.align 2
+PECRL1_A:	.long 0xFFFE3A16
+PECRL1_D0:	.word 0x0033
+.align 2
+
+
+WTCSR_A:	.long 0xFFFE0000
+WTCSR_D0:	.word 0xA518
+WTCSR_D1:	.word 0xA51D
+WTCNT_A:	.long 0xFFFE0002
+WTCNT_D:	.word 0x5A84
+.align 2
+FRQCR_A:	.long 0xFFFE0010
+FRQCR_D:	.word 0x0104
+.align 2
+
+PCCRL4_D1:	.word 0x0010
+PECRL1_D1:	.word 0x0133
+
+CMNCR_A:	.long 0xFFFC0000
+CMNCR_D:	.long 0x00001810
+CS0BCR_A:	.long 0xFFFC0004
+CS0BCR_D:	.long 0x10000400
+CS0WCR_A:	.long 0xFFFC0028
+CS0WCR_D:	.long 0x00000B41
+PECRL4_D1:	.word 0x0100
+.align 2
+CS1WCR_A:	.long 0xFFFC002C
+CS1WCR_D:	.long 0x00000B01
+PCCRL4_D2:	.word 0x0011
+.align 2
+PCCRL3_A:	.long 0xFFFE3912
+PCCRL3_D:	.word 0x0011
+.align 2
+PCCRL2_A:	.long 0xFFFE3914
+PCCRL2_D:	.word 0x1111
+.align 2
+PCCRL1_A:	.long 0xFFFE3916
+PCCRL1_D:	.word 0x1010
+PDCRL4_A:	.long 0xFFFE3990
+PDCRL4_D:	.word 0x0011
+.align 2
+PDCRL3_A:	.long 0xFFFE3992
+PDCRL3_D:	.word 0x00011
+.align 2
+PDCRL2_A:	.long 0xFFFE3994
+PDCRL2_D:	.word 0x1111
+.align 2
+PDCRL1_A:	.long 0xFFFE3996
+PDCRL1_D:	.word 0x1000
+.align 2
+CS3BCR_A:	.long 0xFFFC0010
+CS3BCR_D:	.long 0x00004400
+CS3WCR_A:	.long 0xFFFC0034
+CS3WCR_D:	.long 0x00002892
+SDCR_A:		.long 0xFFFC004C
+SDCR_D:		.long 0x00000809
+RTCOR_A:	.long 0xFFFC0058
+RTCOR_D:	.long 0xA55A0041
+RTCSR_A:	.long 0xFFFC0050
+RTCSR_D:	.long 0xa55a0010
+
+SDRAM_MODE:	.long 0xFFFC5040
+REPEAT_D:	.long 0x00009C40
diff --git a/u-boot/board/renesas/rsk7203/rsk7203.c b/u-boot/board/renesas/rsk7203/rsk7203.c
new file mode 100644
index 0000000..06552c0
--- /dev/null
+++ b/u-boot/board/renesas/rsk7203/rsk7203.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * u-boot/board/rsk7203/rsk7203.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Technology RSK7203\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+/*
+ * The RSK board has the SMSC9118 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+	volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
+	return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+				| swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
+{
+	addr += dev->iobase;
+	*(volatile u16 *)(addr + 2) = swab16((u16)val);
+	*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/renesas/sh7757lcr/Makefile b/u-boot/board/renesas/sh7757lcr/Makefile
new file mode 100644
index 0000000..e2e46ba
--- /dev/null
+++ b/u-boot/board/renesas/sh7757lcr/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2011  Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sh7757lcr.o spi-boot.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(obj).depend $(COBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/u-boot/board/renesas/sh7757lcr/lowlevel_init.S b/u-boot/board/renesas/sh7757lcr/lowlevel_init.S
new file mode 100644
index 0000000..ab1aa49
--- /dev/null
+++ b/u-boot/board/renesas/sh7757lcr/lowlevel_init.S
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro	or32, addr, data
+	mov.l \addr, r1
+	mov.l \data, r0
+	mov.l @r1, r2
+	or    r2, r0
+	mov.l r0, @r1
+.endm
+
+.macro	wait_DBCMD
+	mov.l	DBWAIT_A, r0
+	mov.l	@r0, r1
+.endm
+
+	.global lowlevel_init
+	.section	.spiboot1.text
+	.align  2
+
+lowlevel_init:
+
+	/*------- GPIO -------*/
+	write8 PGDR_A,	PGDR_D	/* eMMC power off */
+
+	write16 PACR_A,	PACR_D
+	write16 PBCR_A,	PBCR_D
+	write16 PCCR_A,	PCCR_D
+	write16 PDCR_A,	PDCR_D
+	write16 PECR_A,	PECR_D
+	write16 PFCR_A,	PFCR_D
+	write16 PGCR_A,	PGCR_D
+	write16 PHCR_A,	PHCR_D
+	write16 PICR_A,	PICR_D
+	write16 PJCR_A,	PJCR_D
+	write16 PKCR_A,	PKCR_D
+	write16 PLCR_A,	PLCR_D
+	write16 PMCR_A,	PMCR_D
+	write16 PNCR_A,	PNCR_D
+	write16 POCR_A,	POCR_D
+	write16 PQCR_A,	PQCR_D
+	write16 PRCR_A,	PRCR_D
+	write16 PSCR_A,	PSCR_D
+	write16 PTCR_A,	PTCR_D
+	write16 PUCR_A,	PUCR_D
+	write16 PVCR_A,	PVCR_D
+	write16 PWCR_A,	PWCR_D
+	write16 PXCR_A,	PXCR_D
+	write16 PYCR_A,	PYCR_D
+	write16 PZCR_A,	PZCR_D
+	write16 PSEL0_A, PSEL0_D
+	write16 PSEL1_A, PSEL1_D
+	write16 PSEL2_A, PSEL2_D
+	write16 PSEL3_A, PSEL3_D
+	write16 PSEL4_A, PSEL4_D
+	write16 PSEL5_A, PSEL5_D
+	write16 PSEL6_A, PSEL6_D
+	write16 PSEL7_A, PSEL7_D
+	write16 PSEL8_A, PSEL8_D
+
+	bra	exit_gpio
+	nop
+
+	.align	4
+
+/*------- GPIO -------*/
+PGDR_A:		.long	0xffec0040
+PACR_A:		.long	0xffec0000
+PBCR_A:		.long	0xffec0002
+PCCR_A:		.long	0xffec0004
+PDCR_A:		.long	0xffec0006
+PECR_A:		.long	0xffec0008
+PFCR_A:		.long	0xffec000a
+PGCR_A:		.long	0xffec000c
+PHCR_A:		.long	0xffec000e
+PICR_A:		.long	0xffec0010
+PJCR_A:		.long	0xffec0012
+PKCR_A:		.long	0xffec0014
+PLCR_A:		.long	0xffec0016
+PMCR_A:		.long	0xffec0018
+PNCR_A:		.long	0xffec001a
+POCR_A:		.long	0xffec001c
+PQCR_A:		.long	0xffec0020
+PRCR_A:		.long	0xffec0022
+PSCR_A:		.long	0xffec0024
+PTCR_A:		.long	0xffec0026
+PUCR_A:		.long	0xffec0028
+PVCR_A:		.long	0xffec002a
+PWCR_A:		.long	0xffec002c
+PXCR_A:		.long	0xffec002e
+PYCR_A:		.long	0xffec0030
+PZCR_A:		.long	0xffec0032
+PSEL0_A:	.long	0xffec0070
+PSEL1_A:	.long	0xffec0072
+PSEL2_A:	.long	0xffec0074
+PSEL3_A:	.long	0xffec0076
+PSEL4_A:	.long	0xffec0078
+PSEL5_A:	.long	0xffec007a
+PSEL6_A:	.long	0xffec007c
+PSEL7_A:	.long	0xffec0082
+PSEL8_A:	.long	0xffec0084
+
+PGDR_D:		.long	0x80
+PACR_D:		.long	0x0000
+PBCR_D:		.long	0x0001
+PCCR_D:		.long	0x0000
+PDCR_D:		.long	0x0000
+PECR_D:		.long	0x0000
+PFCR_D:		.long	0x0000
+PGCR_D:		.long	0x0000
+PHCR_D:		.long	0x0000
+PICR_D:		.long	0x0000
+PJCR_D:		.long	0x0000
+PKCR_D:		.long	0x0003
+PLCR_D:		.long	0x0000
+PMCR_D:		.long	0x0000
+PNCR_D:		.long	0x0000
+POCR_D:		.long	0x0000
+PQCR_D:		.long	0xc000
+PRCR_D:		.long	0x0000
+PSCR_D:		.long	0x0000
+PTCR_D:		.long	0x0000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+PUCR_D:		.long	0x0055
+#else
+PUCR_D:		.long	0x0000
+#endif
+PVCR_D:		.long	0x0000
+PWCR_D:		.long	0x0000
+PXCR_D:		.long	0x0000
+PYCR_D:		.long	0x0000
+PZCR_D:		.long	0x0000
+PSEL0_D:	.long	0xfe00
+PSEL1_D:	.long	0x0000
+PSEL2_D:	.long	0x3000
+PSEL3_D:	.long	0xff00
+PSEL4_D:	.long	0x771f
+PSEL5_D:	.long	0x0ffc
+PSEL6_D:	.long	0x00ff
+PSEL7_D:	.long	0xfc00
+PSEL8_D:	.long	0x0000
+
+	.align	2
+
+exit_gpio:
+	mov	#0, r14
+	mova	2f, r0
+	mov.l	PC_MASK, r1
+	tst	r0, r1
+	bf	2f
+
+	bra	exit_pmb
+	nop
+
+	.align	2
+
+/* If CPU runs on SDRAM, PC is 0x8???????. */
+PC_MASK:	.long	0x20000000
+
+2:
+	mov	#1, r14
+
+	mov.l	EXPEVT_A, r0
+	mov.l	@r0, r0
+	mov.l	EXPEVT_POWER_ON_RESET, r1
+	cmp/eq	r0, r1
+	bt	1f
+
+	/*
+	 * If EXPEVT value is manual reset or tlb multipul-hit,
+	 * initialization of DDR3IF is not necessary.
+	 */
+	bra	exit_ddr
+	nop
+
+1:
+	/* For Core Reset */
+	mov.l	DBACEN_A, r0
+	mov.l	@r0, r0
+	cmp/eq	#0, r0
+	bt	3f
+
+	/*
+	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+	 * initialization of DDR3-SDRAM.
+	 */
+	bra	exit_ddr
+	nop
+
+3:
+	/*------- DDR3IF -------*/
+	/* oscillation stabilization time */
+	wait_timer	WAIT_OSC_TIME
+
+	/* step 3 */
+	write32 DBCMD_A, DBCMD_RSTL_VAL
+	wait_timer	WAIT_30US
+
+	/* step 4 */
+	write32 DBCMD_A, DBCMD_PDEN_VAL
+
+	/* step 5 */
+	write32 DBKIND_A, DBKIND_D
+
+	/* step 6 */
+	write32 DBCONF_A, DBCONF_D
+	write32 DBTR0_A, DBTR0_D
+	write32 DBTR1_A, DBTR1_D
+	write32 DBTR2_A, DBTR2_D
+	write32 DBTR3_A, DBTR3_D
+	write32 DBTR4_A, DBTR4_D
+	write32 DBTR5_A, DBTR5_D
+	write32 DBTR6_A, DBTR6_D
+	write32 DBTR7_A, DBTR7_D
+	write32 DBTR8_A, DBTR8_D
+	write32 DBTR9_A, DBTR9_D
+	write32 DBTR10_A, DBTR10_D
+	write32 DBTR11_A, DBTR11_D
+	write32 DBTR12_A, DBTR12_D
+	write32 DBTR13_A, DBTR13_D
+	write32 DBTR14_A, DBTR14_D
+	write32 DBTR15_A, DBTR15_D
+	write32 DBTR16_A, DBTR16_D
+	write32 DBTR17_A, DBTR17_D
+	write32 DBTR18_A, DBTR18_D
+	write32 DBTR19_A, DBTR19_D
+	write32 DBRNK0_A, DBRNK0_D
+
+	/* step 7 */
+	write32 DBPDCNT3_A, DBPDCNT3_D
+
+	/* step 8 */
+	write32 DBPDCNT1_A, DBPDCNT1_D
+	write32 DBPDCNT2_A, DBPDCNT2_D
+	write32 DBPDLCK_A, DBPDLCK_D
+	write32 DBPDRGA_A, DBPDRGA_D
+	write32 DBPDRGD_A, DBPDRGD_D
+
+	/* step 9 */
+	wait_timer	WAIT_30US
+
+	/* step 10 */
+	write32 DBPDCNT0_A, DBPDCNT0_D
+
+	/* step 11 */
+	wait_timer	WAIT_30US
+	wait_timer	WAIT_30US
+
+	/* step 12 */
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	wait_DBCMD
+
+	/* step 13 */
+	write32 DBCMD_A, DBCMD_RSTH_VAL
+	wait_DBCMD
+
+	/* step 14 */
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+
+	/* step 15 */
+	write32 DBCMD_A, DBCMD_PDXT_VAL
+
+	/* step 16 */
+	write32 DBCMD_A, DBCMD_MRS2_VAL
+
+	/* step 17 */
+	write32 DBCMD_A, DBCMD_MRS3_VAL
+
+	/* step 18 */
+	write32 DBCMD_A, DBCMD_MRS1_VAL
+
+	/* step 19 */
+	write32 DBCMD_A, DBCMD_MRS0_VAL
+
+	/* step 20 */
+	write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+	write32 DBCMD_A, DBCMD_REF_VAL
+	write32 DBCMD_A, DBCMD_REF_VAL
+	wait_DBCMD
+
+	/* step 21 */
+	write32 DBADJ0_A, DBADJ0_D
+	write32 DBADJ1_A, DBADJ1_D
+	write32 DBADJ2_A, DBADJ2_D
+
+	/* step 22 */
+	write32 DBRFCNF0_A, DBRFCNF0_D
+	write32 DBRFCNF1_A, DBRFCNF1_D
+	write32 DBRFCNF2_A, DBRFCNF2_D
+
+	/* step 23 */
+	write32 DBCALCNF_A, DBCALCNF_D
+
+	/* step 24 */
+	write32 DBRFEN_A, DBRFEN_D
+	write32 DBCMD_A, DBCMD_SRXT_VAL
+
+	/* step 25 */
+	write32 DBACEN_A, DBACEN_D
+
+	/* step 26 */
+	wait_DBCMD
+
+	/* enable DDR-ECC */
+	write32 ECD_ECDEN_A, ECD_ECDEN_D
+	write32 ECD_INTSR_A, ECD_INTSR_D
+	write32 ECD_SPACER_A, ECD_SPACER_D
+	write32 ECD_MCR_A, ECD_MCR_D
+
+	bra	exit_ddr
+	nop
+
+	.align 4
+
+EXPEVT_A:		.long	0xff000024
+EXPEVT_POWER_ON_RESET:	.long	0x00000000
+
+/*------- DDR3IF -------*/
+DBCMD_A:	.long	0xfe800018
+DBKIND_A:	.long	0xfe800020
+DBCONF_A:	.long	0xfe800024
+DBTR0_A:	.long	0xfe800040
+DBTR1_A:	.long	0xfe800044
+DBTR2_A:	.long	0xfe800048
+DBTR3_A:	.long	0xfe800050
+DBTR4_A:	.long	0xfe800054
+DBTR5_A:	.long	0xfe800058
+DBTR6_A:	.long	0xfe80005c
+DBTR7_A:	.long	0xfe800060
+DBTR8_A:	.long	0xfe800064
+DBTR9_A:	.long	0xfe800068
+DBTR10_A:	.long	0xfe80006c
+DBTR11_A:	.long	0xfe800070
+DBTR12_A:	.long	0xfe800074
+DBTR13_A:	.long	0xfe800078
+DBTR14_A:	.long	0xfe80007c
+DBTR15_A:	.long	0xfe800080
+DBTR16_A:	.long	0xfe800084
+DBTR17_A:	.long	0xfe800088
+DBTR18_A:	.long	0xfe80008c
+DBTR19_A:	.long	0xfe800090
+DBRNK0_A:	.long	0xfe800100
+DBPDCNT0_A:	.long	0xfe800200
+DBPDCNT1_A:	.long	0xfe800204
+DBPDCNT2_A:	.long	0xfe800208
+DBPDCNT3_A:	.long	0xfe80020c
+DBPDLCK_A:	.long	0xfe800280
+DBPDRGA_A:	.long	0xfe800290
+DBPDRGD_A:	.long	0xfe8002a0
+DBADJ0_A:	.long	0xfe8000c0
+DBADJ1_A:	.long	0xfe8000c4
+DBADJ2_A:	.long	0xfe8000c8
+DBRFCNF0_A:	.long	0xfe8000e0
+DBRFCNF1_A:	.long	0xfe8000e4
+DBRFCNF2_A:	.long	0xfe8000e8
+DBCALCNF_A:	.long	0xfe8000f4
+DBRFEN_A:	.long	0xfe800014
+DBACEN_A:	.long	0xfe800010
+DBWAIT_A:	.long	0xfe80001c
+
+WAIT_OSC_TIME:	.long	6000
+WAIT_30US:	.long	13333
+
+DBCMD_RSTL_VAL:	.long	0x20000000
+DBCMD_PDEN_VAL:	.long	0x1000d73c
+DBCMD_WAIT_VAL:	.long	0x0000d73c
+DBCMD_RSTH_VAL:	.long	0x2100d73c
+DBCMD_PDXT_VAL:	.long	0x110000c8
+DBCMD_MRS0_VAL:	.long	0x28000930
+DBCMD_MRS1_VAL:	.long	0x29000004
+DBCMD_MRS2_VAL:	.long	0x2a000008
+DBCMD_MRS3_VAL:	.long	0x2b000000
+DBCMD_ZQCL_VAL:	.long	0x03000200
+DBCMD_REF_VAL:	.long	0x0c000000
+DBCMD_SRXT_VAL:	.long	0x19000000
+DBKIND_D:	.long	0x00000007
+DBCONF_D:	.long	0x0f030a01
+DBTR0_D:	.long	0x00000007
+DBTR1_D:	.long	0x00000006
+DBTR2_D:	.long	0x00000000
+DBTR3_D:	.long	0x00000007
+DBTR4_D:	.long	0x00070007
+DBTR5_D:	.long	0x0000001b
+DBTR6_D:	.long	0x00000014
+DBTR7_D:	.long	0x00000005
+DBTR8_D:	.long	0x00000015
+DBTR9_D:	.long	0x00000006
+DBTR10_D:	.long	0x00000008
+DBTR11_D:	.long	0x00000007
+DBTR12_D:	.long	0x0000000e
+DBTR13_D:	.long	0x00000056
+DBTR14_D:	.long	0x00000006
+DBTR15_D:	.long	0x00000004
+DBTR16_D:	.long	0x00150002
+DBTR17_D:	.long	0x000c0017
+DBTR18_D:	.long	0x00000200
+DBTR19_D:	.long	0x00000040
+DBRNK0_D:	.long	0x00000001
+DBPDCNT0_D:	.long	0x00000001
+DBPDCNT1_D:	.long	0x00000001
+DBPDCNT2_D:	.long	0x00000000
+DBPDCNT3_D:	.long	0x00004010
+DBPDLCK_D:	.long	0x0000a55a
+DBPDRGA_D:	.long	0x00000028
+DBPDRGD_D:	.long	0x00017100
+
+DBADJ0_D:	.long	0x00000000
+DBADJ1_D:	.long	0x00000000
+DBADJ2_D:	.long	0x18061806
+DBRFCNF0_D:	.long	0x000001ff
+DBRFCNF1_D:	.long	0x08001000
+DBRFCNF2_D:	.long	0x00000000
+DBCALCNF_D:	.long	0x0000ffff
+DBRFEN_D:	.long	0x00000001
+DBACEN_D:	.long	0x00000001
+
+/*------- DDR-ECC -------*/
+ECD_ECDEN_A:	.long	0xffc1012c
+ECD_ECDEN_D:	.long	0x00000001
+ECD_INTSR_A:	.long	0xfe900024
+ECD_INTSR_D:	.long	0xffffffff
+ECD_SPACER_A:	.long	0xfe900018
+ECD_SPACER_D:	.long	SH7757LCR_SDRAM_ECC_SETTING
+ECD_MCR_A:	.long	0xfe900010
+ECD_MCR_D:	.long	0x00000001
+
+	.align 2
+exit_ddr:
+
+#if defined(CONFIG_SH_32BIT)
+	/*------- set PMB -------*/
+	write32	PASCR_A,	PASCR_29BIT_D
+	write32	MMUCR_A,	MMUCR_D
+
+	/*****************************************************************
+	 * ent	virt		phys		v	sz	c	wt
+	 * 0	0xa0000000	0x00000000	1	128M	0	1
+	 * 1	0xa8000000	0x48000000	1	128M	0	1
+	 * 5	0x88000000	0x48000000	1	128M	1	1
+	 */
+	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
+	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
+	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
+	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
+	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
+	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
+
+	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
+
+	write32	PASCR_A,	PASCR_INIT
+	mov.l	DUMMY_ADDR, r0
+	icbi	@r0
+#endif	/* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+	/* CPU is running on ILRAM? */
+	mov	r14, r0
+	tst	#1, r0
+	bt	1f
+
+	mov.l	_bss_start, r15
+	mov.l	_spiboot_main, r0
+100:	bsrf	r0
+	nop
+
+	.align	2
+_spiboot_main:	.long	(spiboot_main - (100b + 4))
+_bss_start:	.long	bss_start
+
+1:
+
+	write32	CCR_A,	CCR_D
+
+	rts
+	 nop
+
+	.align 4
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D:	.long	0x00000000
+
+PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
+
+/*						ppn   ub v s1 s0  c  wt */
+PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A:		.long	0xff000070
+DUMMY_ADDR:		.long	0xa0000000
+PASCR_29BIT_D:		.long	0x00000000
+PASCR_INIT:		.long	0x80000080
+MMUCR_A:		.long	0xff000010
+MMUCR_D:		.long	0x00000004	/* clear ITLB */
+#endif	/* CONFIG_SH_32BIT */
+
+CCR_A:		.long	CCR
+CCR_D:		.long	CCR_CACHE_INIT
diff --git a/u-boot/board/renesas/sh7757lcr/sh7757lcr.c b/u-boot/board/renesas/sh7757lcr/sh7757lcr.c
new file mode 100644
index 0000000..a62be24
--- /dev/null
+++ b/u-boot/board/renesas/sh7757lcr/sh7757lcr.c
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+	puts("BOARD: R0P7757LC0030RL board\n");
+
+	return 0;
+}
+
+static void init_gctrl(void)
+{
+	struct gctrl_regs *gctrl = GCTRL_BASE;
+	unsigned long graofst;
+
+	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+	writel(graofst | 0x20000f00, &gctrl->gracr3);
+}
+
+static int init_pcie_bridge_from_spi(void *buf, size_t size)
+{
+	struct spi_flash *spi;
+	int ret;
+	unsigned long pcie_addr;
+
+	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (!spi) {
+		printf("%s: spi_flash probe error.\n", __func__);
+		return 1;
+	}
+
+	if (is_sh7757_b0())
+		pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
+	else
+		pcie_addr = SH7757LCR_PCIEBRG_ADDR;
+
+	ret = spi_flash_read(spi, pcie_addr, size, buf);
+	if (ret) {
+		printf("%s: spi_flash read error.\n", __func__);
+		spi_flash_free(spi);
+		return 1;
+	}
+	spi_flash_free(spi);
+
+	return 0;
+}
+
+static void init_pcie_bridge(void)
+{
+	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
+	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+	int i;
+	unsigned char *data;
+	unsigned short tmp;
+	unsigned long pcie_size;
+
+	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
+		return;
+
+	if (is_sh7757_b0())
+		pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
+	else
+		pcie_size = SH7757LCR_PCIEBRG_SIZE;
+
+	data = malloc(pcie_size);
+	if (!data) {
+		printf("%s: malloc error.\n", __func__);
+		return;
+	}
+	if (init_pcie_bridge_from_spi(data, pcie_size)) {
+		free(data);
+		return;
+	}
+
+	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
+	    data[3] == 0xff) {
+		free(data);
+		printf("%s: skipped initialization\n", __func__);
+		return;
+	}
+
+	writew(0xa501, &pciebrg->ctrl_h8s);	/* reset */
+	writew(0x0000, &pciebrg->cp_ctrl);
+	writew(0x0000, &pciebrg->cp_addr);
+
+	for (i = 0; i < pcie_size; i += 2) {
+		tmp = (data[i] << 8) | data[i + 1];
+		writew(tmp, &pciebrg->cp_data);
+	}
+
+	writew(0xa500, &pciebrg->ctrl_h8s);	/* start */
+	if (!is_sh7757_b0())
+		writel(0x00000001, &pcie_setup->pbictl3);
+
+	free(data);
+}
+
+static void init_usb_phy(void)
+{
+	struct usb_common_regs *common0 = USB0_COMMON_BASE;
+	struct usb_common_regs *common1 = USB1_COMMON_BASE;
+	struct usb0_phy_regs *phy = USB0_PHY_BASE;
+	struct usb1_port_regs *port = USB1_PORT_BASE;
+	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+	writew(0x0100, &phy->reset);		/* set reset */
+	/* port0 = USB0, port1 = USB1 */
+	writew(0x0002, &phy->portsel);
+	writel(0x0001, &port->port1sel);	/* port1 = Host */
+	writew(0x0111, &phy->reset);		/* clear reset */
+
+	writew(0x4000, &common0->suspmode);
+	writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+	writel(0x00000000, &align->ehcidatac);
+	writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void set_mac_to_sh_eth_register(int channel, char *mac_string)
+{
+	struct ether_mac_regs *ether;
+	unsigned char mac[6];
+	unsigned long val;
+
+	eth_parse_enetaddr(mac_string, mac);
+
+	if (!channel)
+		ether = ETHER0_MAC_BASE;
+	else
+		ether = ETHER1_MAC_BASE;
+
+	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+	writel(val, &ether->mahr);
+	val = (mac[4] << 8) | mac[5];
+	writel(val, &ether->malr);
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+	struct ether_mac_regs *ether;
+	unsigned char mac[6];
+	unsigned long val;
+
+	eth_parse_enetaddr(mac_string, mac);
+
+	if (!channel)
+		ether = GETHER0_MAC_BASE;
+	else
+		ether = GETHER1_MAC_BASE;
+
+	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+	writel(val, &ether->mahr);
+	val = (mac[4] << 8) | mac[5];
+	writel(val, &ether->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent	virt		phys		v	sz	c	wt
+ * 0	0xa0000000	0x40000000	1	128M	0	1
+ * 1	0xa8000000	0x48000000	1	128M	0	1
+ * 2	0xb0000000	0x50000000	1	128M	0	1
+ * 3	0xb8000000	0x58000000	1	128M	0	1
+ * 4	0x80000000	0x40000000	1	128M	1	1
+ * 5	0x88000000	0x48000000	1	128M	1	1
+ * 6	0x90000000	0x50000000	1	128M	1	1
+ * 7	0x98000000	0x58000000	1	128M	1	1
+ */
+static void set_pmb_on_board_init(void)
+{
+	struct mmu_regs *mmu = MMU_BASE;
+
+	/* clear ITLB */
+	writel(0x00000004, &mmu->mmucr);
+
+	/* delete PMB for SPIBOOT */
+	writel(0, PMB_ADDR_BASE(0));
+	writel(0, PMB_DATA_BASE(0));
+
+	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+	/*			ppn  ub v s1 s0  c  wt */
+	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+	struct gether_control_regs *gether = GETHER_CONTROL_BASE;
+
+	set_pmb_on_board_init();
+
+	/* enable RMII's MDIO (disable GRMII's MDIO) */
+	writel(0x00030000, &gether->gbecont);
+
+	init_gctrl();
+	init_usb_phy();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	printf("    Physical address\n");
+	printf("    0x%08x - 0x%08x : Accessible Space as ECC Area\n",
+		SH7757LCR_SDRAM_PHYS_TOP,
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
+	printf("    0x%08x - 0x%08x : No Access Area\n",
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
+	printf("    0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
+			SH7757LCR_SDRAM_DVC_SIZE - 1);
+	printf("    0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
+		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
+
+	return 0;
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+	struct spi_flash *spi;
+	int ret;
+
+	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (spi == NULL) {
+		printf("%s: spi_flash probe error.\n", __func__);
+		return 1;
+	}
+
+	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
+	if (ret) {
+		printf("%s: spi_flash read error.\n", __func__);
+		spi_flash_free(spi);
+		return 1;
+	}
+	spi_flash_free(spi);
+
+	return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
+		SH7757LCR_ETHERNET_MAC_SIZE);
+	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */
+
+	return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+	char mac_string[64];
+	char env_string[64];
+	int i;
+	unsigned char *buf;
+
+	buf = malloc(256);
+	if (!buf) {
+		printf("%s: malloc error.\n", __func__);
+		return;
+	}
+	get_sh_eth_mac_raw(buf, 256);
+
+	/* Fast Ethernet */
+	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
+		get_sh_eth_mac(i, mac_string, buf);
+		if (i == 0)
+			setenv("ethaddr", mac_string);
+		else {
+			sprintf(env_string, "eth%daddr", i);
+			setenv(env_string, mac_string);
+		}
+
+		set_mac_to_sh_eth_register(i, mac_string);
+	}
+
+	/* Gigabit Ethernet */
+	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
+		get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
+		sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
+		setenv(env_string, mac_string);
+
+		set_mac_to_sh_giga_eth_register(i, mac_string);
+	}
+
+	free(buf);
+}
+
+static void init_pcie(void)
+{
+	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
+
+	writel(0x00000ff2, &pcie_setup->ladmsk0);
+	writel(0x00000001, &pcie_setup->barmap);
+	writel(0xffcaa000, &pcie_setup->lad0);
+	writel(0x00030000, &pcie_sysbus->endictl0);
+	writel(0x00000003, &pcie_sysbus->endictl1);
+	writel(0x00000004, &pcie_setup->pbictl2);
+}
+
+static void finish_spiboot(void)
+{
+	struct gctrl_regs *gctrl = GCTRL_BASE;
+	/*
+	 *  SH7757 B0 does not use LBSC.
+	 *  So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
+	 *  This setting is not cleared by manual reset, So we have to set it
+	 *  to 0.
+	 */
+	writel(0x00000000, &gctrl->spibootcan);
+}
+
+int board_late_init(void)
+{
+	init_ethernet_mac();
+	init_pcie_bridge();
+	init_pcie();
+	finish_spiboot();
+
+	return 0;
+}
+
+int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct gctrl_regs *gctrl = GCTRL_BASE;
+	unsigned long graofst;
+
+	writel(0xfedcba98, &gctrl->wprotect);
+	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+	writel(graofst | 0xa0000f00, &gctrl->gracr3);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	sh_g200,	1,	1,	do_sh_g200,
+	"enable sh-g200",
+	"enable SH-G200 bus (disable PCIe-G200)"
+);
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i, ret;
+	char mac_string[256];
+	struct spi_flash *spi;
+	unsigned char *buf;
+
+	if (argc != 5) {
+		buf = malloc(256);
+		if (!buf) {
+			printf("%s: malloc error.\n", __func__);
+			return 1;
+		}
+
+		get_sh_eth_mac_raw(buf, 256);
+
+		/* print current MAC address */
+		for (i = 0; i < 4; i++) {
+			get_sh_eth_mac(i, mac_string, buf);
+			if (i < 2)
+				printf(" ETHERC ch%d = %s\n", i, mac_string);
+			else
+				printf("GETHERC ch%d = %s\n", i-2, mac_string);
+		}
+		free(buf);
+		return 0;
+	}
+
+	/* new setting */
+	memset(mac_string, 0xff, sizeof(mac_string));
+	sprintf(mac_string, "%s\t%s\t%s\t%s",
+		argv[1], argv[2], argv[3], argv[4]);
+
+	/* write MAC data to SPI rom */
+	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (!spi) {
+		printf("%s: spi_flash probe error.\n", __func__);
+		return 1;
+	}
+
+	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+				SH7757LCR_SPI_SECTOR_SIZE);
+	if (ret) {
+		printf("%s: spi_flash erase error.\n", __func__);
+		return 1;
+	}
+
+	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+				sizeof(mac_string), mac_string);
+	if (ret) {
+		printf("%s: spi_flash write error.\n", __func__);
+		spi_flash_free(spi);
+		return 1;
+	}
+	spi_flash_free(spi);
+
+	puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	write_mac,	5,	1,	do_write_mac,
+	"write MAC address for ETHERC/GETHERC",
+	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/u-boot/board/renesas/sh7757lcr/spi-boot.c b/u-boot/board/renesas/sh7757lcr/spi-boot.c
new file mode 100644
index 0000000..823844e
--- /dev/null
+++ b/u-boot/board/renesas/sh7757lcr/spi-boot.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License.  See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS	0x4ef80000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+#define CONFIG_SPI_ADDR		0x00010000
+#else
+#define CONFIG_SPI_ADDR		0x00000000
+#endif
+#define CONFIG_SPI_LENGTH	0x00030000
+#define CONFIG_RAM_BOOT		0x8ef80000
+
+#define SPIWDMADR	0xFE001018
+#define SPIWDMCNTR	0xFE001020
+#define SPIDMCOR	0xFE001028
+#define SPIDMINTSR	0xFE001188
+#define SPIDMINTMR	0xFE001190
+
+#define SPIDMINTSR_DMEND	0x00000004
+
+#define TBR	0xFE002000
+#define RBR	0xFE002000
+
+#define CR1	0xFE002008
+#define CR2	0xFE002010
+#define CR3	0xFE002018
+#define CR4	0xFE002020
+
+/* CR1 */
+#define SPI_TBE		0x80
+#define SPI_TBF		0x40
+#define SPI_RBE		0x20
+#define SPI_RBF		0x10
+#define SPI_PFONRD	0x08
+#define SPI_SSDB	0x04
+#define SPI_SSD		0x02
+#define SPI_SSA		0x01
+
+/* CR2 */
+#define SPI_RSTF	0x80
+#define SPI_LOOPBK	0x40
+#define SPI_CPOL	0x20
+#define SPI_CPHA	0x10
+#define SPI_L1M0	0x08
+
+/* CR4 */
+#define SPI_TBEI	0x80
+#define SPI_TBFI	0x40
+#define SPI_RBEI	0x20
+#define SPI_RBFI	0x10
+#define SPI_SSS		0x01
+
+#define spi_write(val, addr)	(*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr)		(*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ	0x03
+
+#define __uses_spiboot2	__attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+	spi_write(0xfe, CR1);
+
+	spi_write(0, SPIDMCOR);
+	spi_write(0x00, CR1);
+
+	spi_write(spi_read(CR2) | SPI_RSTF, CR2);	/* fifo reset */
+	spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+					   unsigned long len)
+{
+	spi_write(M25_READ, TBR);
+	spi_write((addr >> 16) & 0xFF, TBR);
+	spi_write((addr >> 8) & 0xFF, TBR);
+	spi_write(addr & 0xFF, TBR);
+
+	spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+	spi_write((unsigned long)buf, SPIWDMADR);
+	spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+	spi_write(1, SPIDMCOR);
+
+	spi_write(0xff, CR3);
+	spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+	spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+	while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+		;
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+	void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+	spi_reset();
+	spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+			CONFIG_SPI_LENGTH);
+
+	_start();
+}
+
diff --git a/u-boot/board/renesas/sh7757lcr/u-boot.lds b/u-boot/board/renesas/sh7757lcr/u-boot.lds
new file mode 100644
index 0000000..a88d781
--- /dev/null
+++ b/u-boot/board/renesas/sh7757lcr/u-boot.lds
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2011
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	 * entry and reloct_dst will be provided via ldflags
+	 */
+	. = .;
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		arch/sh/cpu/sh4/start.o		(.text)
+		*(.spiboot1.text)
+		*(.spiboot2.text)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss (NOLOAD) :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
diff --git a/u-boot/board/renesas/sh7763rdp/Makefile b/u-boot/board/renesas/sh7763rdp/Makefile
new file mode 100644
index 0000000..5f37700
--- /dev/null
+++ b/u-boot/board/renesas/sh7763rdp/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+# Copyright (C) 2007 Kenati Technologies, Inc.
+#
+# board/sh7763rdp/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sh7763rdp.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/sh7763rdp/lowlevel_init.S b/u-boot/board/renesas/sh7763rdp/lowlevel_init.S
new file mode 100644
index 0000000..5b18200
--- /dev/null
+++ b/u-boot/board/renesas/sh7763rdp/lowlevel_init.S
@@ -0,0 +1,274 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ * Copyright (C) 2007 Kenati Technologies, Inc.
+ *
+ * board/sh7763rdp/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write32	WDTCSR_A, WDTCSR_D	/* Watchdog Control / Status Register */
+
+	write32	WDTST_A, WDTST_D	/* Watchdog Stop Time Register */
+
+	write32	WDTBST_A, WDTBST_D	/*
+					 * 0xFFCC0008
+					 * Watchdog Base Stop Time Register
+					 */
+
+	write32	CCR_A, CCR_CACHE_ICI_D	/* Address of Cache Control Register */
+					/* Instruction Cache Invalidate */
+
+	write32	MMUCR_A, MMU_CONTROL_TI_D	/* MMU Control Register */
+						/* TI == TLB Invalidate bit */
+
+	write32	MSTPCR0_A, MSTPCR0_D	/* Address of Power Control Register 0 */
+
+	write32	MSTPCR1_A, MSTPCR1_D	/* Address of Power Control Register 1 */
+
+	write32	RAMCR_A, RAMCR_D
+
+	mov.l	MMSELR_A, r1
+	mov.l	MMSELR_D, r0
+	synco
+	mov.l	r0, @r1
+
+	mov.l	@r1, r2		/* execute two reads after setting MMSELR */
+	mov.l	@r1, r2
+	synco
+
+	/* issue memory read */
+	mov.l	DDRSD_START_A, r1	/* memory address to read*/
+	mov.l	@r1, r0
+	synco
+
+	write32	MIM8_A, MIM8_D
+
+	write32	MIMC_A, MIMC_D1
+
+	write32	STRC_A, STRC_D
+
+	write32	SDR4_A, SDR4_D
+
+	write32	MIMC_A, MIMC_D2
+
+	nop
+	nop
+	nop
+
+	write32	SCR4_A, SCR4_D3
+
+	write32	SCR4_A, SCR4_D2
+
+	write32	SDMR02000_A, SDMR02000_D
+
+	write32	SDMR00B08_A, SDMR00B08_D
+
+	write32	SCR4_A, SCR4_D2
+
+	write32	SCR4_A, SCR4_D4
+
+	nop
+	nop
+	nop
+	nop
+
+	write32	SCR4_A, SCR4_D4
+
+	nop
+	nop
+	nop
+	nop
+
+	write32	SDMR00308_A, SDMR00308_D
+
+	write32	MIMC_A, MIMC_D3
+
+	mov.l	SCR4_A, r1
+	mov.l	SCR4_D1, r0
+	mov.l	DELAY60_D, r3
+
+delay_loop_60:
+	mov.l	r0, @r1
+	dt	r3
+	bf	delay_loop_60
+	nop
+
+	write32	CCR_A, CCR_CACHE_D_2	/* Address of Cache Control Register */
+
+bsc_init:
+	write32	BCR_A, BCR_D
+
+	write32	CS0BCR_A, CS0BCR_D
+
+	write32	CS1BCR_A, CS1BCR_D
+
+	write32	CS2BCR_A, CS2BCR_D
+
+	write32	CS4BCR_A, CS4BCR_D
+
+	write32	CS5BCR_A, CS5BCR_D
+
+	write32	CS6BCR_A, CS6BCR_D
+
+	write32	CS0WCR_A, CS0WCR_D
+
+	write32	CS1WCR_A, CS1WCR_D
+
+	write32	CS2WCR_A, CS2WCR_D
+
+	write32	CS4WCR_A, CS4WCR_D
+
+	write32	CS5WCR_A, CS5WCR_D
+
+	write32	CS6WCR_A, CS6WCR_D
+
+	write32	CS5PCR_A, CS5PCR_D
+
+	write32	CS6PCR_A, CS6PCR_D
+
+	mov.l	DELAY200_D, r3
+
+delay_loop_200:
+	dt	r3
+	bf	delay_loop_200
+	nop
+
+	write16	PSEL0_A, PSEL0_D
+
+	write16	PSEL1_A, PSEL1_D
+
+	write32	ICR0_A, ICR0_D
+
+	stc sr, r0	/* BL bit off(init=ON) */
+	mov.l	SR_MASK_D, r1
+	and r1, r0
+	ldc r0, sr
+
+	rts
+	nop
+
+	.align	2
+
+DELAY60_D:	.long	60
+DELAY200_D:	.long	17800
+
+CCR_A:		.long	0xFF00001C
+MMUCR_A:	.long	0xFF000010
+RAMCR_A:	.long	0xFF000074
+
+/* Low power mode control */
+MSTPCR0_A:	.long	0xFFC80030
+MSTPCR1_A:	.long	0xFFC80038
+
+/* RWBT */
+WDTST_A:	.long	0xFFCC0000
+WDTCSR_A:	.long	0xFFCC0004
+WDTBST_A:	.long	0xFFCC0008
+
+/* BSC */
+MMSELR_A:	.long	0xFE600020
+BCR_A:		.long	0xFF801000
+CS0BCR_A:	.long	0xFF802000
+CS1BCR_A:	.long	0xFF802010
+CS2BCR_A:	.long	0xFF802020
+CS4BCR_A:	.long	0xFF802040
+CS5BCR_A:	.long	0xFF802050
+CS6BCR_A:	.long	0xFF802060
+CS0WCR_A:	.long	0xFF802008
+CS1WCR_A:	.long	0xFF802018
+CS2WCR_A:	.long	0xFF802028
+CS4WCR_A:	.long	0xFF802048
+CS5WCR_A:	.long	0xFF802058
+CS6WCR_A:	.long	0xFF802068
+CS5PCR_A:	.long	0xFF802070
+CS6PCR_A:	.long	0xFF802080
+DDRSD_START_A:	.long	0xAC000000
+
+/* INTC */
+ICR0_A:		.long	0xFFD00000
+
+/* DDR I/F */
+MIM8_A:		.long	0xFE800008
+MIMC_A:		.long	0xFE80000C
+SCR4_A:		.long	0xFE800014
+STRC_A:		.long	0xFE80001C
+SDR4_A:		.long	0xFE800034
+SDMR00308_A:	.long	0xFE900308
+SDMR00B08_A:	.long	0xFE900B08
+SDMR02000_A:	.long	0xFE902000
+
+/* GPIO */
+PSEL0_A:	.long	0xFFEF0070
+PSEL1_A:	.long	0xFFEF0072
+
+CCR_CACHE_ICI_D:.long	0x00000800
+CCR_CACHE_D_2:	.long	0x00000103
+MMU_CONTROL_TI_D:.long	0x00000004
+RAMCR_D:	.long	0x00000200
+MSTPCR0_D:	.long	0x00000000
+MSTPCR1_D:	.long	0x00000000
+
+MMSELR_D:	.long	0xa5a50000
+BCR_D:		.long	0x00000000
+CS0BCR_D:	.long	0x77777770
+CS1BCR_D:	.long	0x77777670
+CS2BCR_D:	.long	0x77777670
+CS4BCR_D:	.long	0x77777670
+CS5BCR_D:	.long	0x77777670
+CS6BCR_D:	.long	0x77777670
+CS0WCR_D:	.long	0x7777770F
+CS1WCR_D:	.long	0x22000002
+CS2WCR_D:	.long	0x7777770F
+CS4WCR_D:	.long	0x7777770F
+CS5WCR_D:	.long	0x7777770F
+CS6WCR_D:	.long	0x7777770F
+CS5PCR_D:	.long	0x77000000
+CS6PCR_D:	.long	0x77000000
+ICR0_D:		.long	0x00E00000
+MIM8_D:		.long	0x00000000
+MIMC_D1:	.long	0x01d10008
+MIMC_D2:	.long	0x01d10009
+MIMC_D3:	.long	0x01d10209
+SCR4_D1:	.long	0x00000001
+SCR4_D2:	.long	0x00000002
+SCR4_D3:	.long	0x00000003
+SCR4_D4:	.long	0x00000004
+STRC_D:		.long	0x000f3980
+SDR4_D:		.long	0x00000300
+SDMR00308_D:	.long	0x00000000
+SDMR00B08_D:	.long	0x00000000
+SDMR02000_D:	.long	0x00000000
+PSEL0_D:	.word	0x00000001
+PSEL1_D:	.word	0x00000244
+SR_MASK_D:	.long	0xEFFFFF0F
+WDTST_D:	.long	0x5A000FFF
+WDTCSR_D:	.long	0xA5000000
+WDTBST_D:	.long	0x55000000
diff --git a/u-boot/board/renesas/sh7763rdp/sh7763rdp.c b/u-boot/board/renesas/sh7763rdp/sh7763rdp.c
new file mode 100644
index 0000000..9f44b9a
--- /dev/null
+++ b/u-boot/board/renesas/sh7763rdp/sh7763rdp.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ * Copyright (C) 2007 Kenati Technologies, Inc.
+ *
+ * board/sh7763rdp/sh7763rdp.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPU_CMDREG	0xB1000006
+#define PDCR        0xffef0006
+#define PECR        0xffef0008
+#define PFCR        0xffef000a
+#define PGCR        0xffef000c
+#define PHCR        0xffef000e
+#define PJCR        0xffef0012
+#define PKCR        0xffef0014
+#define PLCR        0xffef0016
+#define PMCR        0xffef0018
+#define PSEL1       0xffef0072
+#define PSEL2       0xffef0074
+#define PSEL3       0xffef0076
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas SH7763 RDP\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	vu_short dat;
+
+	/* Enable mode */
+	writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
+
+	/* GPIO Setting (eth1) */
+	dat = inw(PSEL1);
+	writew(((dat & ~0xff00) | 0x2400), PSEL1);
+	writew(0, PFCR);
+	writew(0, PGCR);
+	writew(0, PHCR);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
diff --git a/u-boot/board/renesas/sh7785lcr/Makefile b/u-boot/board/renesas/sh7785lcr/Makefile
new file mode 100644
index 0000000..e404fa6
--- /dev/null
+++ b/u-boot/board/renesas/sh7785lcr/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2008  Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sh7785lcr.o selfcheck.o rtl8169_mac.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/renesas/sh7785lcr/lowlevel_init.S b/u-boot/board/renesas/sh7785lcr/lowlevel_init.S
new file mode 100644
index 0000000..24a0ecd
--- /dev/null
+++ b/u-boot/board/renesas/sh7785lcr/lowlevel_init.S
@@ -0,0 +1,376 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#include <asm/processor.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	wait_timer	WAIT_200US
+	wait_timer	WAIT_200US
+
+	/*------- LBSC -------*/
+	write32 MMSELR_A,	MMSELR_D
+
+	/*------- DBSC2 -------*/
+	write32 DBSC2_DBCONF_A,	DBSC2_DBCONF_D
+	write32 DBSC2_DBTR0_A,	DBSC2_DBTR0_D
+	write32 DBSC2_DBTR1_A,	DBSC2_DBTR1_D
+	write32 DBSC2_DBTR2_A,	DBSC2_DBTR2_D
+	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D1
+	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D2
+	wait_timer	WAIT_200US
+
+	write32 DBSC2_DBDICODTOCD_A,	DBSC2_DBDICODTOCD_D
+	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_CKE_H
+	wait_timer	WAIT_200US
+	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS2
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS3
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_1
+	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
+	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
+	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_2
+	wait_timer	WAIT_200US
+
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_2
+	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
+
+	write32 DBSC2_DBEN_A,		DBSC2_DBEN_D
+	write32 DBSC2_DBRFCNT1_A,	DBSC2_DBRFCNT1_D
+	write32 DBSC2_DBRFCNT2_A,	DBSC2_DBRFCNT2_D
+	write32 DBSC2_DBRFCNT0_A,	DBSC2_DBRFCNT0_D
+	wait_timer	WAIT_200US
+
+	/*------- GPIO -------*/
+	write16 PACR_A,	PXCR_D
+	write16 PBCR_A,	PXCR_D
+	write16 PCCR_A,	PXCR_D
+	write16 PDCR_A,	PXCR_D
+	write16 PECR_A,	PXCR_D
+	write16 PFCR_A,	PXCR_D
+	write16 PGCR_A,	PXCR_D
+	write16 PHCR_A,	PHCR_D
+	write16 PJCR_A,	PJCR_D
+	write16 PKCR_A,	PKCR_D
+	write16 PLCR_A,	PXCR_D
+	write16 PMCR_A,	PMCR_D
+	write16 PNCR_A,	PNCR_D
+	write16 PPCR_A,	PXCR_D
+	write16 PQCR_A,	PXCR_D
+	write16 PRCR_A,	PXCR_D
+
+	write8	PEPUPR_A,	PEPUPR_D
+	write8	PHPUPR_A,	PHPUPR_D
+	write8	PJPUPR_A,	PJPUPR_D
+	write8	PKPUPR_A,	PKPUPR_D
+	write8	PLPUPR_A,	PLPUPR_D
+	write8	PMPUPR_A,	PMPUPR_D
+	write8	PNPUPR_A,	PNPUPR_D
+	write16	PPUPR1_A,	PPUPR1_D
+	write16	PPUPR2_A,	PPUPR2_D
+	write16	P1MSELR_A,	P1MSELR_D
+	write16	P2MSELR_A,	P2MSELR_D
+
+	/*------- LBSC -------*/
+	write32	BCR_A,		BCR_D
+	write32	CS0BCR_A,	CS0BCR_D
+	write32	CS0WCR_A,	CS0WCR_D
+	write32	CS1BCR_A,	CS1BCR_D
+	write32	CS1WCR_A,	CS1WCR_D
+	write32	CS4BCR_A,	CS4BCR_D
+	write32	CS4WCR_A,	CS4WCR_D
+
+	mov.l	PASCR_A, r0
+	mov.l	@r0, r2
+	mov.l	PASCR_32BIT_MODE, r1
+	tst	r1, r2
+	bt	lbsc_29bit
+
+	write32	CS2BCR_A,	CS_USB_BCR_D
+	write32	CS2WCR_A,	CS_USB_WCR_D
+	write32	CS3BCR_A,	CS_SD_BCR_D
+	write32	CS3WCR_A,	CS_SD_WCR_D
+	write32	CS5BCR_A,	CS_I2C_BCR_D
+	write32	CS5WCR_A,	CS_I2C_WCR_D
+	write32	CS6BCR_A,	CS0BCR_D
+	write32	CS6WCR_A,	CS0WCR_D
+	bra	lbsc_end
+	 nop
+
+lbsc_29bit:
+	write32	CS5BCR_A,	CS_USB_BCR_D
+	write32	CS5WCR_A,	CS_USB_WCR_D
+	write32	CS6BCR_A,	CS_SD_BCR_D
+	write32	CS6WCR_A,	CS_SD_WCR_D
+
+lbsc_end:
+#if defined(CONFIG_SH_32BIT)
+	/*------- set PMB -------*/
+	write32	PASCR_A,	PASCR_29BIT_D
+	write32	MMUCR_A,	MMUCR_D
+
+	/*****************************************************************
+	 * ent	virt		phys		v	sz	c	wt
+	 * 0	0xa0000000	0x00000000	1	64M	0	0
+	 * 1	0xa4000000	0x04000000	1	16M	0	0
+	 * 2	0xa6000000	0x08000000	1	16M	0	0
+	 * 9	0x88000000	0x48000000	1	128M	1	1
+	 * 10	0x90000000	0x50000000	1	128M	1	1
+	 * 11	0x98000000	0x58000000	1	128M	1	1
+	 * 13	0xa8000000	0x48000000	1	128M	0	0
+	 * 14	0xb0000000	0x50000000	1	128M	0	0
+	 * 15	0xb8000000	0x58000000	1	128M	0	0
+	 */
+	write32	PMB_ADDR_FLASH_A,	PMB_ADDR_FLASH_D
+	write32	PMB_DATA_FLASH_A,	PMB_DATA_FLASH_D
+	write32	PMB_ADDR_CPLD_A,	PMB_ADDR_CPLD_D
+	write32	PMB_DATA_CPLD_A,	PMB_DATA_CPLD_D
+	write32	PMB_ADDR_USB_A,		PMB_ADDR_USB_D
+	write32	PMB_DATA_USB_A,		PMB_DATA_USB_D
+	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
+	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
+	write32	PMB_ADDR_DDR_C2_A,	PMB_ADDR_DDR_C2_D
+	write32	PMB_DATA_DDR_C2_A,	PMB_DATA_DDR_C2_D
+	write32	PMB_ADDR_DDR_C3_A,	PMB_ADDR_DDR_C3_D
+	write32	PMB_DATA_DDR_C3_A,	PMB_DATA_DDR_C3_D
+	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
+	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
+	write32	PMB_ADDR_DDR_N2_A,	PMB_ADDR_DDR_N2_D
+	write32	PMB_DATA_DDR_N2_A,	PMB_DATA_DDR_N2_D
+	write32	PMB_ADDR_DDR_N3_A,	PMB_ADDR_DDR_N3_D
+	write32	PMB_DATA_DDR_N3_A,	PMB_DATA_DDR_N3_D
+
+	write32	PASCR_A,	PASCR_INIT
+	mov.l	DUMMY_ADDR, r0
+	icbi	@r0
+#endif
+
+	write32	CCR_A,	CCR_D
+
+	rts
+	nop
+
+	.align 4
+
+/*------- GPIO -------*/
+/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
+PXCR_D:		.word	0x0000
+
+PHCR_D:		.word	0x00c0
+PJCR_D:		.word	0xc3fc
+PKCR_D:		.word	0x03ff
+PMCR_D:		.word	0xffff
+PNCR_D:		.word	0xf0c3
+
+PEPUPR_D:	.long	0xff
+PHPUPR_D:	.long	0x00
+PJPUPR_D:	.long	0x00
+PKPUPR_D:	.long	0x00
+PLPUPR_D:	.long	0x00
+PMPUPR_D:	.long	0xfc
+PNPUPR_D:	.long	0x00
+PPUPR1_D:	.word	0xffbf
+PPUPR2_D:	.word	0xff00
+P1MSELR_D:	.word	0x3780
+P2MSELR_D:	.word	0x0000
+
+#define GPIO_BASE	0xffe70000
+PACR_A:		.long	GPIO_BASE + 0x00
+PBCR_A:		.long	GPIO_BASE + 0x02
+PCCR_A:		.long	GPIO_BASE + 0x04
+PDCR_A:		.long	GPIO_BASE + 0x06
+PECR_A:		.long	GPIO_BASE + 0x08
+PFCR_A:		.long	GPIO_BASE + 0x0a
+PGCR_A:		.long	GPIO_BASE + 0x0c
+PHCR_A:		.long	GPIO_BASE + 0x0e
+PJCR_A:		.long	GPIO_BASE + 0x10
+PKCR_A:		.long	GPIO_BASE + 0x12
+PLCR_A:		.long	GPIO_BASE + 0x14
+PMCR_A:		.long	GPIO_BASE + 0x16
+PNCR_A:		.long	GPIO_BASE + 0x18
+PPCR_A:		.long	GPIO_BASE + 0x1a
+PQCR_A:		.long	GPIO_BASE + 0x1c
+PRCR_A:		.long	GPIO_BASE + 0x1e
+PEPUPR_A:	.long	GPIO_BASE + 0x48
+PHPUPR_A:	.long	GPIO_BASE + 0x4e
+PJPUPR_A:	.long	GPIO_BASE + 0x50
+PKPUPR_A:	.long	GPIO_BASE + 0x52
+PLPUPR_A:	.long	GPIO_BASE + 0x54
+PMPUPR_A:	.long	GPIO_BASE + 0x56
+PNPUPR_A:	.long	GPIO_BASE + 0x58
+PPUPR1_A:	.long	GPIO_BASE + 0x60
+PPUPR2_A:	.long	GPIO_BASE + 0x62
+P1MSELR_A:	.long	GPIO_BASE + 0x80
+P2MSELR_A:	.long	GPIO_BASE + 0x82
+
+MMSELR_A:      .long   0xfc400020
+#if defined(CONFIG_SH_32BIT)
+MMSELR_D:      .long   0xa5a50005
+#else
+MMSELR_D:      .long   0xa5a50002
+#endif
+
+/*------- DBSC2 -------*/
+#define DBSC2_BASE	0xfe800000
+DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
+DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
+DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
+DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
+DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
+DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
+DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
+DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
+DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
+DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
+DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
+DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
+DBSC2_DBDICODTOCD_A:.long	DBSC2_BASE + 0x54
+DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
+DDR_DUMMY_ACCESS_A:	.long	0x40000000
+
+DBSC2_DBCONF_D:		.long	0x00630002
+DBSC2_DBTR0_D:		.long	0x050b1f04
+DBSC2_DBTR1_D:		.long	0x00040204
+DBSC2_DBTR2_D:		.long	0x02100308
+DBSC2_DBFREQ_D1:	.long	0x00000000
+DBSC2_DBFREQ_D2:	.long	0x00000100
+DBSC2_DBDICODTOCD_D:.long	0x000f0907
+
+DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
+DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
+DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
+
+DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
+DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
+DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
+DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
+DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
+DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
+
+DBSC2_DBEN_D:		.long	0x00000001
+
+DBSC2_DBPDCNT0_D3:	.long	0x00000080
+DBSC2_DBRFCNT1_D:	.long	0x00000926
+DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
+DBSC2_DBRFCNT0_D:	.long	0x00010000
+
+WAIT_200US:    .long   33333
+
+/*------- LBSC -------*/
+PASCR_A:		.long	0xff000070
+PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */
+
+BCR_A:		.long	BCR
+CS0BCR_A:	.long	CS0BCR
+CS0WCR_A:	.long	CS0WCR
+CS1BCR_A:	.long	CS1BCR
+CS1WCR_A:	.long	CS1WCR
+CS2BCR_A:	.long	CS2BCR
+CS2WCR_A:	.long	CS2WCR
+CS3BCR_A:	.long	CS3BCR
+CS3WCR_A:	.long	CS3WCR
+CS4BCR_A:	.long	CS4BCR
+CS4WCR_A:	.long	CS4WCR
+CS5BCR_A:	.long	CS5BCR
+CS5WCR_A:	.long	CS5WCR
+CS6BCR_A:	.long	CS6BCR
+CS6WCR_A:	.long	CS6WCR
+
+BCR_D:		.long	0x80000003
+CS0BCR_D:	.long	0x22222340
+CS0WCR_D:	.long	0x00111118
+CS1BCR_D:	.long	0x11111100
+CS1WCR_D:	.long	0x33333303
+CS4BCR_D:	.long	0x11111300
+CS4WCR_D:	.long	0x00101012
+
+/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
+CS_USB_BCR_D:	.long	0x11111200
+CS_USB_WCR_D:	.long	0x00020004
+
+/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
+CS_SD_BCR_D:	.long	0x00000300
+CS_SD_WCR_D:	.long	0x00030108
+
+/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
+CS_I2C_BCR_D:	.long	0x11111100
+CS_I2C_WCR_D:	.long	0x00000003
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_FLASH_A:	.long	PMB_ADDR_BASE(0)
+PMB_ADDR_CPLD_A:	.long	PMB_ADDR_BASE(1)
+PMB_ADDR_USB_A:		.long	PMB_ADDR_BASE(2)
+PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(9)
+PMB_ADDR_DDR_C2_A:	.long	PMB_ADDR_BASE(10)
+PMB_ADDR_DDR_C3_A:	.long	PMB_ADDR_BASE(11)
+PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(13)
+PMB_ADDR_DDR_N2_A:	.long	PMB_ADDR_BASE(14)
+PMB_ADDR_DDR_N3_A:	.long	PMB_ADDR_BASE(15)
+
+PMB_ADDR_FLASH_D:	.long	mk_pmb_addr_val(0xa0)
+PMB_ADDR_CPLD_D:	.long	mk_pmb_addr_val(0xa4)
+PMB_ADDR_USB_D:		.long	mk_pmb_addr_val(0xa6)
+PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_C2_D:	.long	mk_pmb_addr_val(0x90)
+PMB_ADDR_DDR_C3_D:	.long	mk_pmb_addr_val(0x98)
+PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
+PMB_ADDR_DDR_N2_D:	.long	mk_pmb_addr_val(0xb0)
+PMB_ADDR_DDR_N3_D:	.long	mk_pmb_addr_val(0xb8)
+
+PMB_DATA_FLASH_A:	.long	PMB_DATA_BASE(0)
+PMB_DATA_CPLD_A:	.long	PMB_DATA_BASE(1)
+PMB_DATA_USB_A:		.long	PMB_DATA_BASE(2)
+PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(9)
+PMB_DATA_DDR_C2_A:	.long	PMB_DATA_BASE(10)
+PMB_DATA_DDR_C3_A:	.long	PMB_DATA_BASE(11)
+PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(13)
+PMB_DATA_DDR_N2_A:	.long	PMB_DATA_BASE(14)
+PMB_DATA_DDR_N3_A:	.long	PMB_DATA_BASE(15)
+
+/*						ppn   ub v s1 s0  c  wt */
+PMB_DATA_FLASH_D:	.long	mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
+PMB_DATA_CPLD_D:	.long	mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
+PMB_DATA_USB_D:		.long	mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
+PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_C2_D:	.long	mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_C3_D:	.long	mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_N2_D:	.long	mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_N3_D:	.long	mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
+
+DUMMY_ADDR:	.long	0xa0000000
+PASCR_29BIT_D:	.long	0x00000000
+PASCR_INIT:	.long	0x80000080	/* check booting mode */
+MMUCR_A:	.long	0xff000010
+MMUCR_D:	.long	0x00000004	/* clear ITLB */
+#endif	/* CONFIG_SH_32BIT */
+
+CCR_A:		.long	0xff00001c
+CCR_D:		.long	0x0000090b
diff --git a/u-boot/board/renesas/sh7785lcr/rtl8169.h b/u-boot/board/renesas/sh7785lcr/rtl8169.h
new file mode 100644
index 0000000..ca9c0bd
--- /dev/null
+++ b/u-boot/board/renesas/sh7785lcr/rtl8169.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define PCIREG_8(_adr)	(*(volatile unsigned char *)(_adr))
+#define PCIREG_32(_adr)	(*(volatile unsigned long *)(_adr))
+#define PCI_PAR		PCIREG_32(0xfe0401c0)
+#define PCI_PDR		PCIREG_32(0xfe040220)
+#define PCI_CR		PCIREG_32(0xfe040100)
+#define PCI_CONF1	PCIREG_32(0xfe040004)
+
+#define HIGH		1
+#define LOW		0
+
+#define PCI_PROG		0x80
+#define PCI_EEP_ADDRESS		(unsigned short)0x0007
+#define PCI_MAC_ADDRESS_SIZE	3
+
+#define TIME1	100
+#define TIME2	20000
+
+#define BIT_DUMMY	0
+#define MAC_EEP_READ	1
+#define MAC_EEP_WRITE	2
+#define MAC_EEP_ERACE	3
+#define MAC_EEP_EWEN	4
+#define MAC_EEP_EWDS	5
+
+/* RTL8169 */
+const unsigned short EEPROM_W_Data_8169_A[] = {
+	0x8129, 0x10ec, 0x8169, 0x1154, 0x032b,
+	0x4020, 0xa101
+};
+const unsigned short EEPROM_W_Data_8169_B[] = {
+	0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+};
diff --git a/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c b/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c
new file mode 100644
index 0000000..e15013f
--- /dev/null
+++ b/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "rtl8169.h"
+
+static unsigned char *PCI_MEMR;
+
+static void mac_delay(unsigned int cnt)
+{
+	udelay(cnt);
+}
+
+static void mac_pci_setup(void)
+{
+	unsigned long pci_data;
+
+	PCI_PAR = 0x00000010;
+	PCI_PDR = 0x00001000;
+	PCI_PAR = 0x00000004;
+	pci_data = PCI_PDR;
+	PCI_PDR = pci_data | 0x00000007;
+	PCI_PAR = 0x00000010;
+
+	PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0);
+}
+
+static void EECS(int level)
+{
+	unsigned char data = *PCI_MEMR;
+
+	if (level)
+		*PCI_MEMR = data | 0x08;
+	else
+		*PCI_MEMR = data & 0xf7;
+}
+
+static void EECLK(int level)
+{
+	unsigned char data = *PCI_MEMR;
+
+	if (level)
+		*PCI_MEMR = data | 0x04;
+	else
+		*PCI_MEMR = data & 0xfb;
+}
+
+static void EEDI(int level)
+{
+	unsigned char data = *PCI_MEMR;
+
+	if (level)
+		*PCI_MEMR = data | 0x02;
+	else
+		*PCI_MEMR = data & 0xfd;
+}
+
+static inline void sh7785lcr_bitset(unsigned short bit)
+{
+	if (bit)
+		EEDI(HIGH);
+	else
+		EEDI(LOW);
+
+	EECLK(LOW);
+	mac_delay(TIME1);
+	EECLK(HIGH);
+	mac_delay(TIME1);
+	EEDI(LOW);
+}
+
+static inline unsigned char sh7785lcr_bitget(void)
+{
+	unsigned char bit;
+
+	EECLK(LOW);
+	mac_delay(TIME1);
+	bit = *PCI_MEMR & 0x01;
+	EECLK(HIGH);
+	mac_delay(TIME1);
+
+	return bit;
+}
+
+static inline void sh7785lcr_setcmd(unsigned char command)
+{
+	sh7785lcr_bitset(BIT_DUMMY);
+	switch (command) {
+	case MAC_EEP_READ:
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(0);
+		break;
+	case MAC_EEP_WRITE:
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(0);
+		sh7785lcr_bitset(1);
+		break;
+	case MAC_EEP_ERACE:
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(1);
+		break;
+	case MAC_EEP_EWEN:
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(0);
+		sh7785lcr_bitset(0);
+		break;
+	case MAC_EEP_EWDS:
+		sh7785lcr_bitset(1);
+		sh7785lcr_bitset(0);
+		sh7785lcr_bitset(0);
+		break;
+	default:
+		break;
+	}
+}
+
+static inline unsigned short sh7785lcr_getdt(void)
+{
+	unsigned short data = 0;
+	int i;
+
+	sh7785lcr_bitget();			/* DUMMY */
+	for (i = 0 ; i < 16 ; i++) {
+		data <<= 1;
+		data |= sh7785lcr_bitget();
+	}
+	return data;
+}
+
+static inline void sh7785lcr_setadd(unsigned short address)
+{
+	sh7785lcr_bitset(address & 0x0020);	/* A5 */
+	sh7785lcr_bitset(address & 0x0010);	/* A4 */
+	sh7785lcr_bitset(address & 0x0008);	/* A3 */
+	sh7785lcr_bitset(address & 0x0004);	/* A2 */
+	sh7785lcr_bitset(address & 0x0002);	/* A1 */
+	sh7785lcr_bitset(address & 0x0001);	/* A0 */
+}
+
+static inline void sh7785lcr_setdata(unsigned short data)
+{
+	sh7785lcr_bitset(data & 0x8000);
+	sh7785lcr_bitset(data & 0x4000);
+	sh7785lcr_bitset(data & 0x2000);
+	sh7785lcr_bitset(data & 0x1000);
+	sh7785lcr_bitset(data & 0x0800);
+	sh7785lcr_bitset(data & 0x0400);
+	sh7785lcr_bitset(data & 0x0200);
+	sh7785lcr_bitset(data & 0x0100);
+	sh7785lcr_bitset(data & 0x0080);
+	sh7785lcr_bitset(data & 0x0040);
+	sh7785lcr_bitset(data & 0x0020);
+	sh7785lcr_bitset(data & 0x0010);
+	sh7785lcr_bitset(data & 0x0008);
+	sh7785lcr_bitset(data & 0x0004);
+	sh7785lcr_bitset(data & 0x0002);
+	sh7785lcr_bitset(data & 0x0001);
+}
+
+static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address,
+			 unsigned int count)
+{
+	unsigned int i;
+
+	for (i = 0; i < count; i++) {
+		EECS(HIGH);
+		EEDI(LOW);
+		mac_delay(TIME1);
+
+		sh7785lcr_setcmd(MAC_EEP_WRITE);
+		sh7785lcr_setadd(address++);
+		sh7785lcr_setdata(*(data + i));
+
+		EECLK(LOW);
+		EEDI(LOW);
+		EECS(LOW);
+		mac_delay(TIME2);
+	}
+}
+
+static void sh7785lcr_macerase(void)
+{
+	unsigned int i;
+	unsigned short pci_address = 7;
+
+	for (i = 0; i < 3; i++) {
+		EECS(HIGH);
+		EEDI(LOW);
+		mac_delay(TIME1);
+		sh7785lcr_setcmd(MAC_EEP_ERACE);
+		sh7785lcr_setadd(pci_address++);
+		mac_delay(TIME1);
+		EECLK(LOW);
+		EEDI(LOW);
+		EECS(LOW);
+	}
+
+	mac_delay(TIME2);
+
+	printf("\n\nErace End\n");
+	for (i = 0; i < 10; i++)
+		mac_delay(TIME2);
+}
+
+static void sh7785lcr_macwrite(unsigned short *data)
+{
+	sh7785lcr_macerase();
+
+	sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7);
+	sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
+	sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54);
+}
+
+void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count)
+{
+	unsigned int i;
+	unsigned short wk;
+
+	for (i = 0 ; i < count; i++) {
+		EECS(HIGH);
+		EEDI(LOW);
+		mac_delay(TIME1);
+		sh7785lcr_setcmd(MAC_EEP_READ);
+		sh7785lcr_setadd(address++);
+		wk = sh7785lcr_getdt();
+
+		*buf++ = (unsigned char)(wk & 0xff);
+		*buf++ = (unsigned char)((wk >> 8) & 0xff);
+		EECLK(LOW);
+		EEDI(LOW);
+		EECS(LOW);
+	}
+}
+
+static void sh7785lcr_macadrd(unsigned char *buf)
+{
+	*PCI_MEMR = PCI_PROG;
+
+	sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
+}
+
+static void sh7785lcr_eepewen(void)
+{
+	*PCI_MEMR = PCI_PROG;
+	mac_delay(TIME1);
+	EECS(LOW);
+	EECLK(LOW);
+	EEDI(LOW);
+	EECS(HIGH);
+	mac_delay(TIME1);
+
+	sh7785lcr_setcmd(MAC_EEP_EWEN);
+	sh7785lcr_bitset(1);
+	sh7785lcr_bitset(1);
+	sh7785lcr_bitset(BIT_DUMMY);
+	sh7785lcr_bitset(BIT_DUMMY);
+	sh7785lcr_bitset(BIT_DUMMY);
+	sh7785lcr_bitset(BIT_DUMMY);
+
+	EECLK(LOW);
+	EEDI(LOW);
+	EECS(LOW);
+	mac_delay(TIME1);
+}
+
+void mac_write(unsigned short *data)
+{
+	mac_pci_setup();
+	sh7785lcr_eepewen();
+	sh7785lcr_macwrite(data);
+}
+
+void mac_read(void)
+{
+	unsigned char data[6];
+
+	mac_pci_setup();
+	sh7785lcr_macadrd(data);
+	printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		data[0], data[1], data[2], data[3], data[4], data[5]);
+}
+
+int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	unsigned char mac[6];
+	char *s, *e;
+
+	if (argc != 2)
+		return cmd_usage(cmdtp);
+
+	s = argv[1];
+
+	for (i = 0; i < 6; i++) {
+		mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+	mac_write((unsigned short *)mac);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	setmac,	2,	1,	do_set_mac,
+	"write MAC address for RTL8110SCL",
+	"\n"
+	"setmac <mac address> - write MAC address for RTL8110SCL"
+);
+
+int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 1)
+		return cmd_usage(cmdtp);
+
+	mac_read();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	printmac,	1,	1,	do_print_mac,
+	"print MAC address for RTL8110",
+	"\n"
+	"    - print MAC address for RTL8110"
+);
diff --git a/u-boot/board/renesas/sh7785lcr/selfcheck.c b/u-boot/board/renesas/sh7785lcr/selfcheck.c
new file mode 100644
index 0000000..6d92c83
--- /dev/null
+++ b/u-boot/board/renesas/sh7785lcr/selfcheck.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+
+#if defined(CONFIG_CPU_32BIT)
+#define NOCACHE_OFFSET		0x00000000
+#else
+#define NOCACHE_OFFSET		0xa0000000
+#endif
+#define PLD_LEDCR		(0x04000008 + NOCACHE_OFFSET)
+#define PLD_SWSR		(0x0400000a + NOCACHE_OFFSET)
+#define PLD_VERSR		(0x0400000c + NOCACHE_OFFSET)
+
+#define SM107_DEVICEID		(0x13e00060 + NOCACHE_OFFSET)
+
+static void wait_ms(unsigned long time)
+{
+	while (time--)
+		udelay(1000);
+}
+
+static void test_pld(void)
+{
+	printf("PLD version = %04x\n", readb(PLD_VERSR));
+}
+
+static void test_sm107(void)
+{
+	printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID));
+}
+
+static void test_led(void)
+{
+	printf("turn on LEDs 3, 5, 7, 9\n");
+	writeb(0x55, PLD_LEDCR);
+	wait_ms(2000);
+	printf("turn on LEDs 4, 6, 8, 10\n");
+	writeb(0xaa, PLD_LEDCR);
+	wait_ms(2000);
+	writeb(0x00, PLD_LEDCR);
+}
+
+static void test_dipsw(void)
+{
+	printf("Please DIPSW set = B'0101\n");
+	while (readb(PLD_SWSR) != 0x05) {
+		if (ctrlc())
+			return;
+	}
+	printf("Please DIPSW set = B'1010\n");
+	while (readb(PLD_SWSR) != 0x0A) {
+		if (ctrlc())
+			return;
+	}
+	printf("DIPSW OK\n");
+}
+
+static void test_net(void)
+{
+	unsigned long data;
+
+	writel(0x80000000, 0xfe0401c0);
+	data = readl(0xfe040220);
+	if (data == 0x816910ec)
+		printf("Ethernet OK\n");
+	else
+		printf("Ethernet NG, data = %08x\n", (unsigned int)data);
+}
+
+static void test_sata(void)
+{
+	unsigned long data;
+
+	writel(0x80000800, 0xfe0401c0);
+	data = readl(0xfe040220);
+	if (data == 0x35121095)
+		printf("SATA OK\n");
+	else
+		printf("SATA NG, data = %08x\n", (unsigned int)data);
+}
+
+static void test_pci(void)
+{
+	writel(0x80001800, 0xfe0401c0);
+	printf("PCI CN1 ID = %08x\n", readl(0xfe040220));
+
+	writel(0x80001000, 0xfe0401c0);
+	printf("PCI CN2 ID = %08x\n", readl(0xfe040220));
+}
+
+int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *cmd;
+
+	if (argc != 2)
+		return cmd_usage(cmdtp);
+
+	cmd = argv[1];
+	switch (cmd[0]) {
+	case 'a':	/* all */
+		test_pld();
+		test_led();
+		test_dipsw();
+		test_sm107();
+		test_net();
+		test_sata();
+		test_pci();
+		break;
+	case 'p':	/* pld or pci */
+		if (cmd[1] == 'l')
+			test_pld();
+		else
+			test_pci();
+		break;
+	case 'l':	/* led */
+		test_led();
+		break;
+	case 'd':	/* dipsw */
+		test_dipsw();
+		break;
+	case 's':	/* sm107 or sata */
+		if (cmd[1] == 'm')
+			test_sm107();
+		else
+			test_sata();
+		break;
+	case 'n':	/* net */
+		test_net();
+		break;
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	hwtest,	2,	1,	do_hw_test,
+	"hardware test for R0P7785LC0011RL board",
+	"\n"
+	"hwtest all   - test all hardware\n"
+	"hwtest pld   - output PLD version\n"
+	"hwtest led   - turn on LEDs\n"
+	"hwtest dipsw - test DIP switch\n"
+	"hwtest sm107 - output SM107 version\n"
+	"hwtest net   - check RTL8110 ID\n"
+	"hwtest sata  - check SiI3512 ID\n"
+	"hwtest pci   - output PCI slot device ID"
+);
diff --git a/u-boot/board/renesas/sh7785lcr/sh7785lcr.c b/u-boot/board/renesas/sh7785lcr/sh7785lcr.c
new file mode 100644
index 0000000..904e755
--- /dev/null
+++ b/u-boot/board/renesas/sh7785lcr/sh7785lcr.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+	pci_sh7780_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_SH_32BIT)
+int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	/* clear ITLB */
+	writel(0x00000004, 0xff000010);
+
+	/* delete PMB for peripheral */
+	writel(0, PMB_ADDR_BASE(0));
+	writel(0, PMB_DATA_BASE(0));
+	writel(0, PMB_ADDR_BASE(1));
+	writel(0, PMB_DATA_BASE(1));
+	writel(0, PMB_ADDR_BASE(2));
+	writel(0, PMB_DATA_BASE(2));
+
+	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
+	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
+	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
+	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pmb,	1,	1,	do_pmb,
+	"pmb     - PMB setting\n",
+	"\n"
+	"    - PMB setting for all SDRAM mapping"
+);
+#endif
diff --git a/u-boot/board/rmu/Makefile b/u-boot/board/rmu/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/rmu/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/rmu/flash.c b/u-boot/board/rmu/flash.c
new file mode 100644
index 0000000..283b19d
--- /dev/null
+++ b/u-boot/board/rmu/flash.c
@@ -0,0 +1,540 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug ("\n## Get flash bank size @ 0x%08x\n", FLASH_BASE_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE_PRELIM, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	debug  ("## Before remap:  BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+	debug ("Protect redundand environment: %08lx ... %08lx\n",
+		(ulong)CONFIG_ENV_ADDR_REDUND,
+		(ulong)CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR_REDUND,
+		      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	debug ("## Final Flash bank size: %08lx\n", size_b0);
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0xAAAAAAAA ;
+	addr[0x555] = 0x55555555 ;
+	addr[0xAAA] = 0x90909090 ;
+
+	value = addr[0] ;
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/*%%% Size doubled by yooth */
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+	case (AMD_ID_LV320T & 0x00FF00FF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & 0x00FF00FF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/rmu/rmu.c b/u-boot/board/rmu/rmu.c
new file mode 100644
index 0000000..cd02b9c
--- /dev/null
+++ b/u-boot/board/rmu/rmu.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 * (Initialization code at 0x36)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RMU\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
+	 */
+
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	udelay (1000);
+
+	return (size9);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/u-boot/board/rmu/u-boot.lds b/u-boot/board/rmu/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/rmu/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/rmu/u-boot.lds.debug b/u-boot/board/rmu/u-boot.lds.debug
new file mode 100644
index 0000000..f212fab
--- /dev/null
+++ b/u-boot/board/rmu/u-boot.lds.debug
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/ronetix/pm9261/Makefile b/u-boot/board/ronetix/pm9261/Makefile
new file mode 100644
index 0000000..4b49808
--- /dev/null
+++ b/u-boot/board/ronetix/pm9261/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ronetix/pm9261/led.c b/u-boot/board/ronetix/pm9261/led.c
new file mode 100644
index 0000000..ff21ce6
--- /dev/null
+++ b/u-boot/board/ronetix/pm9261/led.c
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable clock */
+	writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer);
+
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/u-boot/board/ronetix/pm9261/partition.c b/u-boot/board/ronetix/pm9261/partition.c
new file mode 100644
index 0000000..cc6cbef
--- /dev/null
+++ b/u-boot/board/ronetix/pm9261/partition.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
+};
+
+#endif
diff --git a/u-boot/board/ronetix/pm9261/pm9261.c b/u-boot/board/ronetix/pm9261/pm9261.c
new file mode 100644
index 0000000..e0f44dd
--- /dev/null
+++ b/u-boot/board/ronetix/pm9261/pm9261.c
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9261_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	writel(1 << AT91SAM9261_ID_PIOA |
+		1 << AT91SAM9261_ID_PIOC,
+		&pmc->pcer);
+
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
+}
+#endif
+
+
+#ifdef CONFIG_DRIVER_DM9000
+static void pm9261_dm9000_hw_init(void)
+{
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Configure SMC CS2 for DM9000 */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[2].mode);
+
+	/* Configure Interrupt pin as input, no pull-up */
+	writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
+	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9261_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
+}
+
+static void pm9261_lcd_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
+	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
+	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
+	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
+	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
+	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */
+
+	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
+
+	gd->fb_base = AT91SAM9261_SRAM_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size, flash_size, dataflash_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2009 Ronetix GmbH\n");
+	lcd_printf ("support@ronetix.at\n");
+	lcd_printf ("%s CPU at %s MHz",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+
+	dataflash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+				dataflash_info[i].Device.pages_size;
+
+	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+			"%ld MB DataFlash\n",
+		dram_size >> 20,
+		nand_size >> 20,
+		flash_size >> 20,
+		dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable Ctrlc */
+	console_init_f();
+
+	writel(1 << AT91SAM9261_ID_PIOA |
+		1 << AT91SAM9261_ID_PIOC,
+		&pmc->pcer);
+
+	/* arch number of PM9261-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	pm9261_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	pm9261_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	pm9261_lcd_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+	char buf[32];
+
+	printf ("Board : Ronetix PM9261\n");
+	printf ("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf ("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf ("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/ronetix/pm9263/Makefile b/u-boot/board/ronetix/pm9263/Makefile
new file mode 100644
index 0000000..2fc9fb4
--- /dev/null
+++ b/u-boot/board/ronetix/pm9263/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += pm9263.o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ronetix/pm9263/led.c b/u-boot/board/ronetix/pm9263/led.c
new file mode 100644
index 0000000..4e585a4
--- /dev/null
+++ b/u-boot/board/ronetix/pm9263/led.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable clock */
+	writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer);
+
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/u-boot/board/ronetix/pm9263/partition.c b/u-boot/board/ronetix/pm9263/partition.c
new file mode 100644
index 0000000..95ac398
--- /dev/null
+++ b/u-boot/board/ronetix/pm9263/partition.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR,   0, ""},
+};
+
+#endif
diff --git a/u-boot/board/ronetix/pm9263/pm9263.c b/u-boot/board/ronetix/pm9263/pm9263.c
new file mode 100644
index 0000000..ec9f865
--- /dev/null
+++ b/u-boot/board/ronetix/pm9263/pm9263.c
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9263_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9263_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/*
+	 * PB27 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
+	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
+
+	/* Enable clock */
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PC25) => PHY normal mode (not Test mode)
+	 *	ERX0 (PE25) => PHY ADDR0
+	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+
+	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
+}
+
+#ifdef CONFIG_LCD_IN_PSRAM
+
+#define PSRAM_CRE_PIN	AT91_PIO_PORTB, 29
+#define PSRAM_CTRL_REG	(PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
+
+/* Initialize the PSRAM memory */
+static int pm9263_lcd_hw_psram_init(void)
+{
+	volatile uint16_t x;
+	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC1_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+
+	/* Enable CS3  3.3v, no pull-ups */
+	csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
+		AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
+
+	writel(csa, &matrix->csa[1]);
+
+	/* Configure SMC1 CS0 for PSRAM - 16-bit */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[0].setup);
+
+	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+		AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
+		&smc->cs[0].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+		&smc->cs[0].cycle);
+
+	writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
+		&smc->cs[0].mode);
+
+	/* setup PB29 as output */
+	at91_set_pio_output(PSRAM_CRE_PIN, 1);
+
+	at91_set_pio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */
+
+	/* PSRAM: write BCR */
+	x = readw(PSRAM_CTRL_REG);
+	x = readw(PSRAM_CTRL_REG);
+	writew(1, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+	writew(0x9d4f, PSRAM_CTRL_REG);	/* write the BCR */
+
+	/* write RCR of the PSRAM */
+	x = readw(PSRAM_CTRL_REG);
+	x = readw(PSRAM_CTRL_REG);
+	writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+	/* set RCR; 0x10-async mode,0x90-page mode */
+	writew(0x90, PSRAM_CTRL_REG);
+
+	/*
+	 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
+	 * MT45W2M16B - CRE must be 0
+	 * MT45W2M16A - CRE must be 1
+	 */
+	writew(0x1234, PHYS_PSRAM);
+	writew(0x5678, PHYS_PSRAM + 2);
+
+	/* test if the chip is MT45W2M16B */
+	if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
+		/* try with CRE=1 (MT45W2M16A) */
+		at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
+
+		/* write RCR of the PSRAM */
+		x = readw(PSRAM_CTRL_REG);
+		x = readw(PSRAM_CTRL_REG);
+		writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+		/* set RCR;0x10-async mode,0x90-page mode */
+		writew(0x90, PSRAM_CTRL_REG);
+
+
+		writew(0x1234, PHYS_PSRAM);
+		writew(0x5678, PHYS_PSRAM+2);
+		if ((readw(PHYS_PSRAM) != 0x1234)
+		  || (readw(PHYS_PSRAM + 2) != 0x5678))
+			return 1;
+
+	}
+
+	/* Bus matrix */
+	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
+	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
+
+	return 0;
+}
+#endif
+
+static void pm9263_lcd_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
+
+	/* Power Control */
+	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);	/* power down */
+
+#ifdef CONFIG_LCD_IN_PSRAM
+	/* initialize te PSRAM */
+	int stat = pm9263_lcd_hw_psram_init();
+
+	gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE;
+#else
+	gd->fb_base = AT91SAM9263_SRAM0_BASE;
+#endif
+
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size, flash_size, dataflash_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2009 Ronetix GmbH\n");
+	lcd_printf ("support@ronetix.at\n");
+	lcd_printf ("%s CPU at %s MHz",
+		CONFIG_SYS_AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+
+	dataflash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+				dataflash_info[i].Device.pages_size;
+
+	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+			"4 MB PSRAM, %ld MB DataFlash\n",
+		dram_size >> 20,
+		nand_size >> 20,
+		flash_size >> 20,
+		dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable Ctrlc */
+	console_init_f();
+
+	writel((1 << AT91SAM9263_ID_PIOA) |
+		(1 << AT91SAM9263_ID_PIOCDE) |
+		(1 << AT91SAM9263_ID_PIOB),
+		&pmc->pcer);
+
+	/* arch number of AT91SAM9263EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	pm9263_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	pm9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	pm9263_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+	char *ss;
+
+	printf ("Board : Ronetix PM9263\n");
+
+	switch (gd->fb_base) {
+	case PHYS_PSRAM:
+		ss = "(PSRAM)";
+		break;
+
+	case AT91SAM9263_SRAM0_BASE:
+		ss = "(Internal SRAM)";
+		break;
+
+	default:
+		ss = "";
+		break;
+	}
+	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
+
+	printf ("\n");
+	return 0;
+}
+#endif
diff --git a/u-boot/board/ronetix/pm9g45/Makefile b/u-boot/board/ronetix/pm9g45/Makefile
new file mode 100644
index 0000000..cb01262
--- /dev/null
+++ b/u-boot/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += pm9g45.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ronetix/pm9g45/pm9g45.c b/u-boot/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 0000000..79b7c9d
--- /dev/null
+++ b/u-boot/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t	*smc	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_matrix_t	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->ccr[6]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(3),
+		&smc->cs[3].mode);
+
+	writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/*
+	 * PD2 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
+	at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
+
+	/* Enable clock */
+	writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA15) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA12) => PHY ADDR0
+	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable Ctrlc */
+	console_init_f();
+
+	writel((1 << AT91SAM9G45_ID_PIOA) |
+		(1 << AT91SAM9G45_ID_PIOB) |
+		(1 << AT91SAM9G45_ID_PIOC) |
+		(1 << AT91SAM9G45_ID_PIODE), &pmc->pcer);
+
+	/* arch number of AT91SAM9M10G45EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_MACB
+	pm9g45_macb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/rpxsuper/Makefile b/u-boot/board/rpxsuper/Makefile
new file mode 100644
index 0000000..73450ac
--- /dev/null
+++ b/u-boot/board/rpxsuper/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= rpxsuper.o flash.o mii_phy.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/rpxsuper/flash.c b/u-boot/board/rpxsuper/flash.c
new file mode 100644
index 0000000..be29b65
--- /dev/null
+++ b/u-boot/board/rpxsuper/flash.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD 29F080B devices
+ * Added support for 64bit and AMD 29DL323B
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/io.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define RD_SWP32(x) in_le32((volatile u32*)x)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* for now, only support the 4 MB Flash SIMM */
+    size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+
+    /*
+     * protect monitor and environment sectors
+     */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case (AMD_MANUFACT & FLASH_VENDMASK):
+	printf ("AMD ");
+	break;
+    case (FUJ_MANUFACT & FLASH_VENDMASK):
+	printf ("FUJITSU ");
+	break;
+    case (SST_MANUFACT & FLASH_VENDMASK):
+	printf ("SST ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case (AMD_ID_DL323B & FLASH_TYPEMASK):
+	printf("AM29DL323B (32 MBit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; ++i) {
+	if ((i % 5) == 0) printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    vu_long vendor[2], devid[2];
+    ulong base = (ulong)addr;
+
+    /* Reset and Write auto select command: read Manufacturer ID */
+    addr[0] = 0xf0f0f0f0;
+    addr[2 * 0x0555] = 0xAAAAAAAA;
+    addr[2 * 0x02AA] = 0x55555555;
+    addr[2 * 0x0555] = 0x90909090;
+    addr[1] = 0xf0f0f0f0;
+    addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+    addr[2 * 0x02AA + 1] = 0x55555555;
+    addr[2 * 0x0555 + 1] = 0x90909090;
+    udelay (1000);
+
+    vendor[0] = RD_SWP32(&addr[0]);
+    vendor[1] = RD_SWP32(&addr[1]);
+    if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) {
+	info->size = 0;
+	goto out;
+    }
+
+    devid[0] = RD_SWP32(&addr[2]);
+    devid[1] = RD_SWP32(&addr[3]);
+
+    if (devid[0] == AMD_ID_DL323B) {
+	/*
+	* we have 2 Banks
+	* Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte
+	* Bank 2 (48 Sectors): 23-70=64kbyte
+	*/
+	info->flash_id     = (AMD_MANUFACT & FLASH_VENDMASK) |
+			     (AMD_ID_DL323B & FLASH_TYPEMASK);
+	info->sector_count = 71;
+	info->size         = 4 * (8 * 8 + 63 * 64) * 1024;
+    }
+    else {
+	info->size = 0;
+	goto out;
+    }
+
+    /* set up sector start address table */
+    for (i = 0; i < 8; i++) {
+	info->start[i] = base + (i * 0x8000);
+    }
+    for (i = 8; i < info->sector_count; i++) {
+	info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000;
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* read sector protection at sector address */
+	addr = (volatile unsigned long *)(info->start[i]);
+	addr[2 * 0x0555] = 0xAAAAAAAA;
+	addr[2 * 0x02AA] = 0x55555555;
+	addr[2 * 0x0555] = 0x90909090;
+	addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+	addr[2 * 0x02AA + 1] = 0x55555555;
+	addr[2 * 0x0555 + 1] = 0x90909090;
+	udelay (1000);
+	base = RD_SWP32(&addr[4]);
+	base |= RD_SWP32(&addr[5]);
+	info->protect[i] = base & 0x00010001 ? 1 : 0;
+    }
+    addr = (vu_long*)info->start[0];
+
+out:
+    /* reset command */
+    addr[0] = 0xf0f0f0f0;
+    addr[1] = 0xf0f0f0f0;
+
+    return info->size;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[2 * 0x0555] = 0xAAAAAAAA;
+    addr[2 * 0x02AA] = 0x55555555;
+    addr[2 * 0x0555] = 0x80808080;
+    addr[2 * 0x0555] = 0xAAAAAAAA;
+    addr[2 * 0x02AA] = 0x55555555;
+    addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+    addr[2 * 0x02AA + 1] = 0x55555555;
+    addr[2 * 0x0555 + 1] = 0x80808080;
+    addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+    addr[2 * 0x02AA + 1] = 0x55555555;
+    udelay (100);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    addr[1] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while (	(addr[0] & 0x80808080) != 0x80808080 ||
+		(addr[1] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;	/* reset bank */
+    addr[1] = 0xF0F0F0F0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    if ((dest & 0x00000004) == 0) {
+	addr[2 * 0x0555] = 0xAAAAAAAA;
+	addr[2 * 0x02AA] = 0x55555555;
+	addr[2 * 0x0555] = 0xA0A0A0A0;
+    }
+    else {
+	addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+	addr[2 * 0x02AA + 1] = 0x55555555;
+	addr[2 * 0x0555 + 1] = 0xA0A0A0A0;
+    }
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/rpxsuper/mii_phy.c b/u-boot/board/rpxsuper/mii_phy.c
new file mode 100644
index 0000000..12e23f4
--- /dev/null
+++ b/u-boot/board/rpxsuper/mii_phy.c
@@ -0,0 +1,107 @@
+#include <common.h>
+#include <mii_phy.h>
+#include "rpxsuper.h"
+
+#define MII_MDIO	0x01
+#define MII_MDCK	0x02
+#define MII_MDIR	0x04
+
+void
+mii_discover_phy(void)
+{
+    int known;
+    unsigned short phy_reg;
+    unsigned long phy_id;
+
+    known = 0;
+    printf("Discovering phy @ 0: ");
+    phy_id = mii_phy_read(2) << 16;
+    phy_id |= mii_phy_read(3);
+    if ((phy_id & 0xFFFFFC00) == 0x00137800) {
+	printf("Level One ");
+	if ((phy_id & 0x000003F0) == 0xE0) {
+	    printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
+	    known = 1;
+	}
+	else printf("unknown type\n");
+    }
+    else printf("unknown OUI = 0x%08lX\n", phy_id);
+
+    phy_reg = mii_phy_read(1);
+    if (!(phy_reg & 0x0004)) printf("Link is down\n");
+    if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
+    if (phy_reg & 0x0002) printf("Jabber condition detected\n");
+    if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
+
+    if (known) {
+	phy_reg = mii_phy_read(17);
+	if (phy_reg & 0x0400)
+	    printf("Phy operating at %d MBit/s in %s-duplex mode\n",
+		phy_reg & 0x4000 ? 100 : 10,
+		phy_reg & 0x0200 ? "full" : "half");
+	else
+	    printf("bad link!!\n");
+/*
+left  off: no link, green 100MBit, yellow 10MBit
+right off: no activity, green full-duplex, yellow half-duplex
+*/
+	mii_phy_write(20, 0x0452);
+    }
+}
+
+unsigned short
+mii_phy_read(unsigned short reg)
+{
+    int i;
+    unsigned short tmp, val = 0, adr = 0;
+    t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+
+    tmp = 0x6002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    regs->bcsr4 |= MII_MDIR;
+    for (i = 0; i < 16; i++) {
+	val <<= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
+	if (regs->bcsr4 & MII_MDIO) val |= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
+    }
+    return val;
+}
+
+void
+mii_phy_write(unsigned short reg, unsigned short val)
+{
+    int i;
+    unsigned short tmp, adr = 0;
+    t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+
+    tmp = 0x5002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	val <<= 1;
+    }
+}
diff --git a/u-boot/board/rpxsuper/readme b/u-boot/board/rpxsuper/readme
new file mode 100644
index 0000000..21267bd
--- /dev/null
+++ b/u-boot/board/rpxsuper/readme
@@ -0,0 +1,30 @@
+Hi,
+
+so this is the port to the Embedded Planet RPX Super Board.
+
+ATTENTION
+This code is only tested on the AY-Version, which is an early release with some
+hardware bugs. The main problem is that this board uses the default Hard Reset
+Configuration Word and not the 4 bytes located at start of FLASH because at
+0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be
+carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low
+byte.
+
+The icache can only manually be enabled after reset.
+The FLASH and main SDRAM is working with icache enabled.
+The local SDRAM can only be used as data memory when icache is enabled.
+If U-Boot runs in local SDRAM, TFTP does not work.
+The functions in mii_phy.c are all working. Call mii_phy_discover() out of
+eth_init() and solve the linker error.
+I2C, RTC/NVRAM and PCMCIA are not working yet.
+
+TODO
+The 32MB local SDRAM is working but not shown in the startup messages of
+U-Boot. If you locate U-Boot or any other program to this area it won't run.
+Turning the ichache off does not solve this problem.
+
+As I won't buy another RPX Super there might be some little work to do for you
+getting this U-Boot port running on the final board.
+
+
+frank.morauf@salzbrenner.com
diff --git a/u-boot/board/rpxsuper/rpxsuper.c b/u-boot/board/rpxsuper/rpxsuper.c
new file mode 100644
index 0000000..aa59803
--- /dev/null
+++ b/u-boot/board/rpxsuper/rpxsuper.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "rpxsuper.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   1,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   0,   0,   0   }, /* PA6 */
+	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   1,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   1,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   1,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   1,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PC26 */ {   1,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   1,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   1,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   1,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+	/* PC15 */ {   1,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   1,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   1,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   1,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   1,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   1,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   1,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   0,   0,   0,   0,   0   }, /* PD26 */
+	/* PD25 */ {   1,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   1,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   1,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   1,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   1,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   1,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   1,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   1,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD17 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   1,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   1,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   1,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   1,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Setup CS4 to enable the Board Control/Status registers.
+ * Otherwise the smcs won't work.
+*/
+int board_early_init_f (void)
+{
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+    memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+    memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+    regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */
+    regs->bcsr2 = 0x20;	/* mut be written to enable writing FLASH */
+    return 0;
+}
+
+void
+reset_phy(void)
+{
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+    regs->bcsr4 = 0xC3;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+    printf ("Board: Embedded Planet RPX Super, Revision %d\n",
+	regs->bcsr0 >> 4);
+
+    return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram(int board_type)
+{
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+    volatile uchar c = 0, *ramaddr;
+    ulong psdmr, lsdmr, bcr;
+    long size = 0;
+    int i;
+
+    psdmr = CONFIG_SYS_PSDMR;
+    lsdmr = CONFIG_SYS_LSDMR;
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+     */
+
+    size = CONFIG_SYS_SDRAM0_SIZE;
+    bcr = immap->im_siu_conf.sc_bcr;
+    immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM);
+
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+    ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE);
+    memctl->memc_psrt = CONFIG_SYS_PSRT;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+
+    immap->im_siu_conf.sc_bcr = bcr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*    size += CONFIG_SYS_SDRAM1_SIZE; */
+    ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE);
+    memctl->memc_lsrt = CONFIG_SYS_LSRT;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+#endif
+
+    /* return total ram size */
+    return (size * 1024 * 1024);
+}
diff --git a/u-boot/board/rpxsuper/rpxsuper.h b/u-boot/board/rpxsuper/rpxsuper.h
new file mode 100644
index 0000000..af31060
--- /dev/null
+++ b/u-boot/board/rpxsuper/rpxsuper.h
@@ -0,0 +1,25 @@
+#ifndef __RPX8260_H__
+#define __RPX8260_H__
+
+typedef struct tt_rpx_regs
+{
+    volatile unsigned char bcsr0;
+    volatile unsigned char bcsr1;
+    volatile unsigned char bcsr2;
+    volatile unsigned char bcsr3;
+    volatile unsigned char bcsr4;
+    volatile unsigned char bcsr5;
+    volatile unsigned char bcsr6;
+    volatile unsigned char bcsr7;
+    volatile unsigned char bcsr8;
+    volatile unsigned char bcsr9;
+    volatile unsigned char bcsr10;
+    volatile unsigned char bcsr11;
+    volatile unsigned char bcsr12;
+    volatile unsigned char bcsr13;
+    volatile unsigned char bcsr14;
+    volatile unsigned char bcsr15;
+} t_rpx_regs;
+typedef t_rpx_regs* tp_rpx_regs;
+
+#endif
diff --git a/u-boot/board/rsdproto/Makefile b/u-boot/board/rsdproto/Makefile
new file mode 100644
index 0000000..d297622
--- /dev/null
+++ b/u-boot/board/rsdproto/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= rsdproto.o flash.o
+SOBJS	:= flash_asm.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/rsdproto/flash.c b/u-boot/board/rsdproto/flash.c
new file mode 100644
index 0000000..e99c2a6
--- /dev/null
+++ b/u-boot/board/rsdproto/flash.c
@@ -0,0 +1,402 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AM290[48]0B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* flash hardware ids */
+#define VENDOR_AMD     0x0001
+#define AMD_29DL323C_B 0x2253
+
+/* Define this to include autoselect sequence in flash_init(). Does NOT
+ * work when executing from flash itself, so this should be turned
+ * on only when debugging the RAM version.
+ */
+#undef WITH_AUTOSELECT
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if 1
+#define D(x)
+#else
+#define D(x) printf x
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static unsigned char write_ull(flash_info_t *info,
+			       unsigned long address,
+			       volatile unsigned long long data);
+
+/* from flash_asm.S */
+extern void ull_write(unsigned long long volatile *address,
+		      unsigned long long volatile *data);
+extern void ull_read(unsigned long long volatile *address,
+		     unsigned long long volatile *data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    int i;
+    ulong addr;
+
+#ifdef WITH_AUTOSELECT
+	{
+		unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH;
+		unsigned long long f_command, vendor, device;
+		/* Perform Autoselect */
+		f_command	= 0x00AA00AA00AA00AAULL;
+		ull_write(&f_addr[0x555], &f_command);
+		f_command	= 0x0055005500550055ULL;
+		ull_write(&f_addr[0x2AA], &f_command);
+		f_command	= 0x0090009000900090ULL;
+		ull_write(&f_addr[0x555], &f_command);
+		ull_read(&f_addr[0], &vendor);
+		vendor &= 0xffff;
+		ull_read(&f_addr[1], &device);
+		device &= 0xffff;
+		f_command	= 0x00F000F000F000F0ULL;
+		ull_write(&f_addr[0x555], &f_command);
+		if (vendor != VENDOR_AMD || device != AMD_29DL323C_B)
+		  return 0;
+	}
+#endif
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+	/* 1st bank: 8 x 32 KB sectors */
+	flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+	flash_info[0].sector_count = 8;
+	flash_info[0].size = flash_info[0].sector_count * 32 * 1024;
+	addr = PHYS_FLASH;
+    for(i = 0; i < flash_info[0].sector_count; i++) {
+		flash_info[0].start[i] = addr;
+		addr += flash_info[0].size / flash_info[0].sector_count;
+	}
+	/* 1st bank: 63 x 256 KB sectors */
+	flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+	flash_info[1].sector_count = 63;
+	flash_info[1].size = flash_info[1].sector_count * 256 * 1024;
+    for(i = 0; i < flash_info[1].sector_count; i++) {
+		flash_info[1].start[i] = addr;
+		addr += flash_info[1].size / flash_info[1].sector_count;
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[1]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		      &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		      &flash_info[1]);
+#endif
+
+    return flash_info[0].size + flash_info[1].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+    }
+
+    switch (info->flash_id >> 16) {
+    case VENDOR_AMD:
+		printf ("AMD ");
+		break;
+    default:
+		printf ("Unknown Vendor ");
+		break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_29DL323C_B:
+		printf ("AM29DL323CB (32 Mbit)\n");
+		break;
+    default:
+		printf ("Unknown Chip Type\n");
+		break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+		  printf ("\n   ");
+		printf (" %08lX%s",
+				info->start[i],
+				info->protect[i] ? " (RO)" : "     "
+				);
+    }
+    printf ("\n");
+    return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    int flag, prot, sect, l_sect;
+    ulong start;
+	unsigned long long volatile *f_addr;
+	unsigned long long volatile f_command;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+    }
+    if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+    } else {
+		printf ("\n");
+    }
+
+	f_addr	= (unsigned long long *)info->start[0];
+	f_command	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+	f_command	= 0x0080008000800080ULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (l_sect = -1, sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			f_addr	=
+			  (unsigned long long *)(info->start[sect]);
+			f_command	= 0x0030003000300030ULL;
+			ull_write(f_addr, &f_command);
+			l_sect = sect;
+		}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+	start = get_timer (0);
+	do
+	{
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
+		{	/* write reset command, command address is unimportant */
+			/* this command turns the flash back to read mode     */
+			f_addr =
+			  (unsigned long long *)(info->start[l_sect]);
+			f_command	= 0x00F000F000F000F0ULL;
+			ull_write(f_addr, &f_command);
+			printf (" timeout\n");
+			return 1;
+	}
+	} while(*f_addr != 0xFFFFFFFFFFFFFFFFULL);
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    unsigned long cp, wp;
+	unsigned long long data;
+    int i, l, rc;
+
+    wp = (addr & ~7);	/* get lower long long aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<8 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<8; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_ull(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+    }
+
+    /*
+     * handle long long aligned part
+     */
+    while (cnt >= 8) {
+		data = 0;
+		for (i=0; i<8; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_ull(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp  += 8;
+		cnt -= 8;
+    }
+
+    if (cnt == 0) {
+		return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+    }
+    for (; i<8; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return write_ull(info, wp, data);
+}
+
+/*---------------------------------------------------------------------------
+*
+* FUNCTION NAME:  write_ull
+*
+* DESCRIPTION:   writes 8 bytes to flash
+*
+* EXTERNAL EFFECT: nothing
+*
+* PARAMETERS:   32 bit long pointer to address, 64 bit long pointer to data
+*
+* RETURNS:	0 if OK, 1 if timeout, 4 if parameter error
+*--------------------------------------------------------------------------*/
+
+static unsigned char write_ull(flash_info_t *info,
+							   unsigned long address,
+							   volatile unsigned long long data)
+{
+	static unsigned long long f_command;
+	static unsigned long long *f_addr;
+	ulong start;
+
+	/* address muss be 8-aligned! */
+	if (address & 0x7)
+	  return ERR_ALIGN;
+
+	f_addr	= (unsigned long long *)info->start[0];
+	f_command	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+	f_command	= 0x00A000A000A000A0ULL;
+	ull_write(&f_addr[0x555], &f_command);
+
+	f_addr	= (unsigned long long *)address;
+	f_command	= data;
+	ull_write(f_addr, &f_command);
+
+	start = get_timer (0);
+	do
+	{
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+		{
+			/* write reset command, command address is unimportant */
+			/* this command turns the flash back to read mode     */
+			f_addr	= (unsigned long long *)info->start[0];
+			f_command	= 0x00F000F000F000F0ULL;
+			ull_write(f_addr, &f_command);
+			return ERR_TIMOUT;
+		}
+	} while(*((unsigned long long *)address) != data);
+
+	return 0;
+}
diff --git a/u-boot/board/rsdproto/flash_asm.S b/u-boot/board/rsdproto/flash_asm.S
new file mode 100644
index 0000000..557cac0
--- /dev/null
+++ b/u-boot/board/rsdproto/flash_asm.S
@@ -0,0 +1,39 @@
+/*
+ * -*- mode:c -*-
+ *
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * void ull_write(unsigned long long volatile *address,
+ *                unsigned long long volatile *data)
+ * r3 = address
+ * r4 = data
+ *
+ * void ull_read(unsigned long long volatile *address,
+ *                unsigned long long volatile *data)
+ * r3 = address
+ * r4 = data
+ *
+ * Uses the floating point unit to read and write 64 bit wide
+ * data (unsigned long long) on the 60x bus. This is necessary
+ * because all 4 flash chips use the /WE line from byte lane 0
+ *
+ * IMPORTANT: data should always be 8-aligned, otherwise an exception will
+ * occur.
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+	.globl	ull_write
+ull_write:
+	lfd		0,0(r4)
+	stfd	0,0(r3)
+	blr
+
+	.globl	ull_read
+ull_read:
+	lfd		0, 0(r3)
+	stfd	0, 0(r4)
+	blr
diff --git a/u-boot/board/rsdproto/rsdproto.c b/u-boot/board/rsdproto/rsdproto.c
new file mode 100644
index 0000000..10759b7
--- /dev/null
+++ b/u-boot/board/rsdproto/rsdproto.c
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+#include <bcd.h>
+
+/* define to initialise the SDRAM on the local bus */
+#undef INIT_LOCAL_BUS_SDRAM
+
+/* I2C Bus adresses for PPC & Protocol board */
+#define PPC8260_I2C_ADR		0x30	/*(0)011.0000 */
+#define LM84_PPC_I2C_ADR	0x2A	/*(0)010.1010 */
+#define LM84_SHARC_I2C_ADR	0x29	/*(0)010.1001 */
+#define VIRTEX_I2C_ADR		0x25	/*(0)010.0101 */
+#define X24645_PPC_I2C_ADR	0x00	/*(0)00X.XXXX  -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
+#define RS5C372_PPC_I2C_ADR	0x32	/*(0)011.0010  -> this adress is programmed by the manufacturer and cannot be changed !!! */
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   },
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* ETHRXCLK: CLK14 */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART CD/ */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDC: GP */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDIO: GP */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+struct tm {
+	unsigned int tm_sec;
+	unsigned int tm_min;
+	unsigned int tm_hour;
+	unsigned int tm_wday;
+	unsigned int tm_mday;
+	unsigned int tm_mon;
+	unsigned int tm_year;
+};
+
+void read_RS5C372_time (struct tm *timedate)
+{
+	unsigned char buffer[8];
+
+	if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
+		timedate->tm_sec = bcd2bin (buffer[0]);
+		timedate->tm_min = bcd2bin (buffer[1]);
+		timedate->tm_hour = bcd2bin (buffer[2]);
+		timedate->tm_wday = bcd2bin (buffer[3]);
+		timedate->tm_mday = bcd2bin (buffer[4]);
+		timedate->tm_mon = bcd2bin (buffer[5]);
+		timedate->tm_year = bcd2bin (buffer[6]) + 2000;
+	} else {
+		/*printf("i2c error %02x\n", rc); */
+		memset (timedate, 0, sizeof (struct tm));
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+int read_LM84_temp (int address)
+{
+	unsigned char buffer[8];
+	/*int rc;*/
+
+	if (! i2c_read (address, 0, 1, buffer, 1)) {
+		return (int) buffer[0];
+	} else {
+		/*printf("i2c error %02x\n", rc); */
+		return -42;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	struct tm timedate;
+	unsigned int ppctemp, prottemp;
+
+	puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
+
+	/* initialise i2c */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	read_RS5C372_time (&timedate);
+	printf ("  Time:  %02d:%02d:%02d\n",
+			timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
+	printf ("  Date:  %02d-%02d-%04d\n",
+			timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
+	ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
+	prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
+	printf ("  Temp:  PPC %d C, Protocol Board %d C\n",
+			ppctemp, prottemp);
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations while still
+ * running in flash
+ */
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifdef INIT_LOCAL_BUS_SDRAM
+	volatile uchar *ramaddr8;
+#endif
+	volatile ulong *ramaddr32;
+	ulong sdmr;
+	int i;
+
+	/*
+	 * Only initialize SDRAM when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		immap->im_siu_conf.sc_ppc_acr = 0x02;
+		immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+		immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+		immap->im_siu_conf.sc_lcl_acr = 0x02;
+		immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+		immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+		/*
+		 * Program local/60x bus Transfer Error Status and Control Regs:
+		 * Disable parity errors
+		 */
+		immap->im_siu_conf.sc_tescr1 = 0x00040000;
+		immap->im_siu_conf.sc_ltescr1 = 0x00040000;
+
+		/*
+		 * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
+		 *
+		 * The appropriate BRx/ORx registers have already
+		 * been set when we get here (see cpu_init_f). The
+		 * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+		 */
+		memctl->memc_mptpr = 0x2000;
+		memctl->memc_mar = 0x0200;
+#ifdef INIT_LOCAL_BUS_SDRAM
+		/* initialise local bus ram
+		 *
+		 * (using the PSRMR_ definitions is NOT an error here
+		 * - the LSDMR has the same fields as the PSDMR!)
+		 */
+		memctl->memc_lsrt = 0x0b;
+		memctl->memc_lurt = 0x00;
+		ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
+		sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
+		*ramaddr = 0xff;
+		for (i = 0; i < 8; i++) {
+			memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
+			*ramaddr = 0xff;
+		}
+		memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
+		*ramaddr = 0xff;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
+#endif
+		/* initialise 60x bus ram */
+		memctl->memc_psrt = 0x0b;
+		memctl->memc_purt = 0x08;
+		ramaddr32 = (ulong *) PHYS_SDRAM_60X;
+		sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
+		ramaddr32[0] = 0x00ff00ff;
+		ramaddr32[1] = 0x00ff00ff;
+		memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++) {
+			ramaddr32[0] = 0x00ff00ff;
+			ramaddr32[1] = 0x00ff00ff;
+		}
+		memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
+		ramaddr32[0] = 0x00ff00ff;
+		ramaddr32[1] = 0x00ff00ff;
+		memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	}
+
+	/* return the size of the 60x bus ram */
+	return PHYS_SDRAM_60X_SIZE;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations after monitor
+ * has been relocated into ram
+ */
+
+int misc_init_r (void)
+{
+	printf ("misc_init_r\n");
+	return (0);
+}
diff --git a/u-boot/board/rsdproto/u-boot.lds b/u-boot/board/rsdproto/u-boot.lds
new file mode 100644
index 0000000..7763c7f
--- /dev/null
+++ b/u-boot/board/rsdproto/u-boot.lds
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.got1)
+    /*. = env_offset; */
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/sacsng/Makefile b/u-boot/board/sacsng/Makefile
new file mode 100644
index 0000000..eae0f02
--- /dev/null
+++ b/u-boot/board/sacsng/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sacsng.o flash.o clkinit.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sacsng/clkinit.c b/u-boot/board/sacsng/clkinit.c
new file mode 100644
index 0000000..4a7f362
--- /dev/null
+++ b/u-boot/board/sacsng/clkinit.c
@@ -0,0 +1,1025 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#include <configs/sacsng.h>
+
+#include "clkinit.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int Daq64xSampling = 0;
+
+
+void Daq_BRG_Reset(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr |=  CPM_BRG_RST;
+     *brg_ptr &= ~CPM_BRG_RST;
+}
+
+void Daq_BRG_Disable(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr &= ~CPM_BRG_EN;
+}
+
+void Daq_BRG_Enable(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr |= CPM_BRG_EN;
+}
+
+uint Daq_BRG_Get_Div16(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     if (*brg_ptr & CPM_BRG_DIV16) {
+	 /* DIV16 active */
+	 return (TRUE);
+     }
+     else {
+	 /* DIV16 inactive */
+	 return (FALSE);
+     }
+}
+
+void Daq_BRG_Set_Div16(uint brg, uint div16)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     if (div16) {
+	 /* DIV16 active */
+	 *brg_ptr |=  CPM_BRG_DIV16;
+     }
+     else {
+	 /* DIV16 inactive */
+	 *brg_ptr &= ~CPM_BRG_DIV16;
+     }
+}
+
+uint Daq_BRG_Get_Count(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+     uint brg_cnt;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     /* Get the clock divider
+      *
+      * Note: A clock divider of 0 means divide by 1,
+      *       therefore we need to add 1 to the count.
+      */
+     brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
+     brg_cnt++;
+     if (*brg_ptr & CPM_BRG_DIV16) {
+	 brg_cnt *= 16;
+     }
+
+    return (brg_cnt);
+}
+
+void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     /*
+      * Note: A clock divider of 0 means divide by 1,
+      *	 therefore we need to subtract 1 from the count.
+      */
+     if (brg_cnt > 4096) {
+	 /* Prescale = Divide by 16 */
+	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK)   |
+	     (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
+	 *brg_ptr |= CPM_BRG_DIV16;
+     }
+     else {
+	 /* Prescale = Divide by 1 */
+	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+	     ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
+	 *brg_ptr &= ~CPM_BRG_DIV16;
+     }
+}
+
+uint Daq_BRG_Get_ExtClk(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
+}
+
+char* Daq_BRG_Get_ExtClk_Description(uint brg)
+{
+     uint extc;
+
+     extc = Daq_BRG_Get_ExtClk(brg);
+
+     switch (brg + 1) {
+	 case 1:
+	 case 2:
+	 case 5:
+	 case 6: {
+	     switch (extc) {
+		 case 0: {
+		     return ("BRG_INT");
+		 }
+		 case 1: {
+		     return ("CLK3");
+		 }
+		 case 2: {
+		     return ("CLK5");
+		 }
+	     }
+	     return ("??1245??");
+	 }
+	 case 3:
+	 case 4:
+	 case 7:
+	 case 8: {
+	     switch (extc) {
+		 case 0: {
+		     return ("BRG_INT");
+		 }
+		 case 1: {
+		     return ("CLK9");
+		 }
+		 case 2: {
+		     return ("CLK15");
+		 }
+	     }
+	     return ("??3478??");
+	 }
+     }
+     return ("??9876??");
+}
+
+void Daq_BRG_Set_ExtClk(uint brg, uint extc)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
+		((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
+}
+
+uint Daq_BRG_Rate(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+     uint brg_cnt;
+     uint brg_freq = 0;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     brg_ptr += brg;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg_ptr += (brg - 4);
+     }
+
+    brg_cnt = Daq_BRG_Get_Count(brg);
+
+    switch (Daq_BRG_Get_ExtClk(brg)) {
+	case CPM_BRG_EXTC_CLK3:
+	case CPM_BRG_EXTC_CLK5: {
+	    brg_freq = brg_cnt;
+	    break;
+	}
+	default: {
+	    brg_freq = (uint)BRG_INT_CLK / brg_cnt;
+	}
+    }
+    return (brg_freq);
+}
+
+uint Daq_Get_SampleRate(void)
+{
+     /*
+      * Read the BRG's to return the actual sample rate.
+      */
+     return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
+}
+
+void Daq_Init_Clocks(int sample_rate, int sample_64x)
+{
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
+    uint mclk_divisor; /* MCLK divisor */
+    int  flag;         /* Interrupt state */
+
+    /* Save off the clocking data */
+    Daq64xSampling = sample_64x;
+
+    /*
+     * Limit the sample rate to some sensible values.
+     */
+    if (sample_rate > MAX_64x_SAMPLE_RATE) {
+	sample_rate = MAX_64x_SAMPLE_RATE;
+    }
+    if (sample_rate < MIN_SAMPLE_RATE) {
+	sample_rate = MIN_SAMPLE_RATE;
+    }
+
+    /*
+     * Initialize the MCLK/SCLK/LRCLK baud rate generators.
+     */
+
+    /* Setup MCLK */
+    Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+#   else
+	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
+#   endif
+
+    /* Setup LRCLK */
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+#   else
+	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
+#   endif
+
+    /*
+     * Dynamically adjust MCLK based on the new sample rate.
+     */
+
+    /* Compute the divisors */
+    mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
+
+    /*
+     * Disable interrupt and save the current state
+     */
+    flag = disable_interrupts();
+
+    /* Setup MCLK */
+    Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
+#   endif
+
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(LRCLK_BRG,
+			  mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
+#   endif
+
+    /*
+     * Restore the Interrupt state
+     */
+     if (flag) {
+	 enable_interrupts();
+     }
+
+    /* Enable the clock drivers */
+    iopa->pdat &= ~SLRCLK_EN_MASK;
+}
+
+void Daq_Stop_Clocks(void)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flag;           /* Interrupt flags */
+#endif
+
+#   ifdef TIGHTEN_UP_BRG_TIMING
+	/*
+	 * Obtain MCLK BRG reset/disabled value
+	 */
+#       if (MCLK_BRG == 0)
+	    mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 1)
+	    mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 2)
+	    mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 3)
+	    mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 4)
+	    mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 5)
+	    mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 6)
+	    mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 7)
+	    mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain SCLK BRG reset/disabled value
+	 */
+#       if (SCLK_BRG == 0)
+	    sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 1)
+	    sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 2)
+	    sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 3)
+	    sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 4)
+	    sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 5)
+	    sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 6)
+	    sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 7)
+	    sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain LRCLK BRG reset/disabled value
+	 */
+#       if (LRCLK_BRG == 0)
+	    lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+	/*
+	 * Set reset on MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg;
+#       endif
+
+	/*
+	 * Set reset on SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg;
+#       endif
+
+	/*
+	 * Set reset on LRCLK BRG
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = lrclk_brg;
+#       endif
+
+	/*
+	 * Clear reset on MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Clear reset on SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Clear reset on LRCLK BRG
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+	}
+#   else
+	/*
+	 * Reset the clocks
+	 */
+	Daq_BRG_Reset(MCLK_BRG);
+	Daq_BRG_Reset(SCLK_BRG);
+	Daq_BRG_Reset(LRCLK_BRG);
+#   endif
+}
+
+void Daq_Start_Clocks(int sample_rate)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
+    register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
+    uint          lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flags;          /* Interrupt flags */
+    uint          sclk_cnt;       /* SCLK count */
+    uint          delay_cnt;      /* Delay count */
+#endif
+
+#   ifdef TIGHTEN_UP_BRG_TIMING
+	/*
+	 * Obtain the enabled MCLK BRG value
+	 */
+#       if (MCLK_BRG == 0)
+	    mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 1)
+	    mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 2)
+	    mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 3)
+	    mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 4)
+	    mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 5)
+	    mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 6)
+	    mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 7)
+	    mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain the enabled SCLK BRG value
+	 */
+#       if (SCLK_BRG == 0)
+	    sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 1)
+	    sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 2)
+	    sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 3)
+	    sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 4)
+	    sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 5)
+	    sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 6)
+	    sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 7)
+	    sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain the enabled LRCLK BRG value
+	 */
+#       if (LRCLK_BRG == 0)
+	    lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/* Save off the real LRCLK value */
+	real_lrclk_brg = lrclk_brg;
+
+	/* Obtain the current SCLK count */
+	sclk_cnt  = ((sclk_brg & 0x00001FFE) >> 1) + 1;
+
+	/* Compute the delay as a function of SCLK count */
+	delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
+	if (DaqSampleRate == 43402) {
+	  delay_cnt++;
+	}
+
+	/* Clear out the count */
+	temp_lrclk_brg = sclk_brg & ~0x00001FFE;
+
+	/* Insert the count */
+	temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;
+
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+	/*
+	 * Enable MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg;
+#       endif
+
+	/*
+	 * Enable SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg;
+#       endif
+
+	/*
+	 * Enable LRCLK BRG (1st time - temporary)
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = temp_lrclk_brg;
+#       endif
+
+	/*
+	 * Enable LRCLK BRG (2nd time - permanent)
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = real_lrclk_brg;
+#       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+	}
+#   else
+	/*
+	 * Enable the clocks
+	 */
+	Daq_BRG_Enable(LRCLK_BRG);
+	Daq_BRG_Enable(SCLK_BRG);
+	Daq_BRG_Enable(MCLK_BRG);
+#   endif
+}
+
+void Daq_Display_Clocks(void)
+
+{
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+    uint mclk_divisor; /* Detected MCLK divisor */
+    uint sclk_divisor; /* Detected SCLK divisor */
+
+    printf("\nBRG:\n");
+    if (immr->im_brgc4 != 0) {
+	printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  MCLK\n",
+	       immr->im_brgc4,
+	       (uint)&(immr->im_brgc4),
+	       Daq_BRG_Get_Count(3),
+	       Daq_BRG_Get_ExtClk(3),
+	       Daq_BRG_Get_ExtClk_Description(3));
+    }
+    if (immr->im_brgc8 != 0) {
+	printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCLK\n",
+	       immr->im_brgc8,
+	       (uint)&(immr->im_brgc8),
+	       Daq_BRG_Get_Count(7),
+	       Daq_BRG_Get_ExtClk(7),
+	       Daq_BRG_Get_ExtClk_Description(7));
+    }
+    if (immr->im_brgc6 != 0) {
+	printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  LRCLK\n",
+	       immr->im_brgc6,
+	       (uint)&(immr->im_brgc6),
+	       Daq_BRG_Get_Count(5),
+	       Daq_BRG_Get_ExtClk(5),
+	       Daq_BRG_Get_ExtClk_Description(5));
+    }
+    if (immr->im_brgc1 != 0) {
+	printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC1\n",
+	       immr->im_brgc1,
+	       (uint)&(immr->im_brgc1),
+	       Daq_BRG_Get_Count(0),
+	       Daq_BRG_Get_ExtClk(0),
+	       Daq_BRG_Get_ExtClk_Description(0));
+    }
+    if (immr->im_brgc2 != 0) {
+	printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC2\n",
+	       immr->im_brgc2,
+	       (uint)&(immr->im_brgc2),
+	       Daq_BRG_Get_Count(1),
+	       Daq_BRG_Get_ExtClk(1),
+	       Daq_BRG_Get_ExtClk_Description(1));
+    }
+    if (immr->im_brgc3 != 0) {
+	printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCC1\n",
+	       immr->im_brgc3,
+	       (uint)&(immr->im_brgc3),
+	       Daq_BRG_Get_Count(2),
+	       Daq_BRG_Get_ExtClk(2),
+	       Daq_BRG_Get_ExtClk_Description(2));
+    }
+    if (immr->im_brgc5 != 0) {
+	printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+	       immr->im_brgc5,
+	       (uint)&(immr->im_brgc5),
+	       Daq_BRG_Get_Count(4),
+	       Daq_BRG_Get_ExtClk(4),
+	       Daq_BRG_Get_ExtClk_Description(4));
+    }
+    if (immr->im_brgc7 != 0) {
+	printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+	       immr->im_brgc7,
+	       (uint)&(immr->im_brgc7),
+	       Daq_BRG_Get_Count(6),
+	       Daq_BRG_Get_ExtClk(6),
+	       Daq_BRG_Get_ExtClk_Description(6));
+    }
+
+#   ifdef RUN_SCLK_ON_BRG_INT
+	mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
+#   else
+	mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
+#   endif
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
+#   else
+	sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
+#   endif
+
+    printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
+    printf("\tMCLK  %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
+	   Daq_BRG_Rate(MCLK_BRG),
+	   mclk_divisor,
+	   mclk_divisor * sclk_divisor);
+#   ifdef RUN_SCLK_ON_BRG_INT
+	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
+	       Daq_BRG_Rate(SCLK_BRG),
+	       sclk_divisor);
+#   else
+	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
+	       Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
+	       sclk_divisor);
+#   endif
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	printf("\tLRCLK %8d Hz\n",
+	       Daq_BRG_Rate(LRCLK_BRG));
+#   else
+#       ifdef RUN_SCLK_ON_BRG_INT
+	    printf("\tLRCLK %8d Hz\n",
+		   Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
+#       else
+	    printf("\tLRCLK %8d Hz\n",
+		   Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
+#       endif
+#   endif
+    printf("\n");
+}
diff --git a/u-boot/board/sacsng/clkinit.h b/u-boot/board/sacsng/clkinit.h
new file mode 100644
index 0000000..011638f
--- /dev/null
+++ b/u-boot/board/sacsng/clkinit.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */
+
+#define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */
+#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
+#define MAX_64x_SAMPLE_RATE  86805 /* Maximum  64x sample rate */
+
+#define KHZ          ((uint)1000)
+#define MHZ          ((uint)(1000 * KHZ))
+
+#define MCLK_BRG     3        /* MCLK, Master CLocK for the A/D & D/A   */
+#define SCLK_BRG     7        /* SCLK, Sample CLocK for the A/D & D/A   */
+#define LRCLK_BRG    5        /* LRCLK, L/R CLocK for the A/D & D/A     */
+			      /*   0 == BRG1 (used for SMC1)            */
+			      /*   1 == BRG2 (used for SMC2)            */
+			      /*   2 == BRG3 (used for SCC1)            */
+			      /*   3 == BRG4 (MCLK)                     */
+			      /*   4 == BRG5                            */
+			      /*   5 == BRG6 (LRCLK)                    */
+			      /*   6 == BRG7                            */
+			      /*   7 == BRG8 (SCLK)                     */
+
+#define MCLK_DIVISOR  4       /*  SCLK = MCLK / MCLK_DIVISOR */
+#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
+			      /* LRCLK = SCLK / SCLK_DIVISOR */
+
+#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing      */
+#define RUN_SCLK_ON_BRG_INT      /* Run SCLK on BRG_INT instead of MCLK   */
+				 /* The 8260 (Mask B.3) seems to have     */
+				 /* problems generating SCLK from MCLK    */
+				 /* via CLK9.                             */
+#define RUN_LRCLK_ON_BRG_INT     /* Run LRCLK on BRG_INT instead of SCLK  */
+				 /* The 8260 (Mask B.3) seems to have     */
+				 /* problems generating LRCLK from SCLK   */
+
+#define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
+				   /* to wait for the clock to stabilize  */
+
+#define CPM_CLK      (gd->bd->bi_cpmfreq)
+#define DFBRG        4
+#define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
+			      /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
+			      /* BRG = CPM * 2 / 4                */
+			      /* BRG = CPM / 2                    */
+
+#define CPM_BRG_EXTC_MASK	((uint)0x0000C000)
+#define CPM_BRG_EXTC_SHIFT      14
+
+#define CPM_BRG_DIV16_MASK	((uint)0x00000001)
+#define CPM_BRG_DIV16_SHIFT     1
+
+#define CPM_BRG_EXTC_BRGCLK     0
+#define CPM_BRG_EXTC_CLK3       1
+#define CPM_BRG_EXTC_CLK9       CPM_BRG_EXTC_CLK3
+#define CPM_BRG_EXTC_CLK5       2
+#define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5
+
+#define IM_BRGC1 ((uint *)0xf00119f0)
+#define IM_BRGC2 ((uint *)0xf00119f4)
+#define IM_BRGC3 ((uint *)0xf00119f8)
+#define IM_BRGC4 ((uint *)0xf00119fc)
+#define IM_BRGC5 ((uint *)0xf00115f0)
+#define IM_BRGC6 ((uint *)0xf00115f4)
+#define IM_BRGC7 ((uint *)0xf00115f8)
+#define IM_BRGC8 ((uint *)0xf00115fc)
+
+/*
+ * External declarations
+ */
+
+extern int Daq64xSampling;
+
+extern void Daq_BRG_Reset(uint brg);
+extern void Daq_BRG_Run(uint brg);
+
+extern void Daq_BRG_Disable(uint brg);
+extern void Daq_BRG_Enable(uint brg);
+
+extern uint Daq_BRG_Get_Div16(uint brg);
+extern void Daq_BRG_Set_Div16(uint brg, uint div16);
+
+extern uint Daq_BRG_Get_Count(uint brg);
+extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
+
+extern uint Daq_BRG_Get_ExtClk(uint brg);
+extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
+extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
+
+extern uint Daq_BRG_Rate(uint brg);
+
+extern uint Daq_Get_SampleRate(void);
+
+extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
+extern void Daq_Stop_Clocks(void);
+extern void Daq_Start_Clocks(int sample_rate);
+extern void Daq_Display_Clocks(void);
diff --git a/u-boot/board/sacsng/flash.c b/u-boot/board/sacsng/flash.c
new file mode 100644
index 0000000..8b30f50
--- /dev/null
+++ b/u-boot/board/sacsng/flash.c
@@ -0,0 +1,523 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <configs/sacsng.h>
+
+
+#undef  DEBUG
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+#endif
+
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_short *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	/*
+	 * We only report the primary flash for U-Boot's use.
+	 */
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	short i;
+	ushort value;
+	ulong  base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	addr[0x0555] = 0x9090;
+	__asm__ __volatile__(" sync\n ");
+
+	value = addr[0];
+#ifdef DEBUG
+	printf("Flash manufacturer 0x%04X\n", value);
+#endif
+
+	if(value == (ushort)AMD_MANUFACT) {
+		info->flash_id = FLASH_MAN_AMD;
+	} else if (value == (ushort)FUJ_MANUFACT) {
+		info->flash_id = FLASH_MAN_FUJ;
+	} else {
+#ifdef DEBUG
+		printf("Unknown flash manufacturer 0x%04X\n", value);
+#endif
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+#ifdef DEBUG
+	printf("Flash type 0x%04X\n", value);
+#endif
+
+	if(value == (ushort)AMD_ID_LV400T) {
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 0.5 MB		*/
+	} else if(value == (ushort)AMD_ID_LV400B) {
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 0.5 MB		*/
+	} else if(value == (ushort)AMD_ID_LV800T) {
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB		*/
+	} else if(value == (ushort)AMD_ID_LV800B) {
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB		*/
+	} else if(value == (ushort)AMD_ID_LV160T) {
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB		*/
+	} else if(value == (ushort)AMD_ID_LV160B) {
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB		*/
+	} else if(value == (ushort)AMD_ID_LV320T) {
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;	/* => 4 MB		*/
+	} else if(value == (ushort)AMD_ID_LV320B) {
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;	/* => 4 MB		*/
+	} else {
+#ifdef DEBUG
+		printf("Unknown flash type 0x%04X\n", value);
+		info->size = CONFIG_SYS_FLASH_SIZE;
+#else
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+#endif
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 3) * 0x00010000);
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned short *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned short *)info->start[0];
+
+	}
+
+	addr[0] = 0xF0F0;	/* reset bank */
+	__asm__ __volatile__(" sync\n ");
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	addr[0x0555] = 0x8080;
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	__asm__ __volatile__(" sync\n ");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x3030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_short*)(info->start[l_sect]);
+	while ((addr[0] & 0x0080) != 0x0080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			addr[0] = 0xF0F0;	/* reset bank */
+			__asm__ __volatile__(" sync\n ");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short*)info->start[0];
+	addr[0] = 0xF0F0;	/* reset bank */
+	__asm__ __volatile__(" sync\n ");
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start;
+	int flag;
+	int j;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((*(vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* The original routine was designed to write 32 bit words to
+	 * 32 bit wide memory.	We have 16 bit wide memory so we do
+	 * two writes.	We write the LSB first at dest+2 and then the
+	 * MSB at dest (lousy big endian).
+	 */
+	dest += 2;
+	for(j = 0; j < 2; j++) {
+		addr[0x0555] = 0xAAAA;
+		addr[0x02AA] = 0x5555;
+		addr[0x0555] = 0xA0A0;
+		__asm__ __volatile__(" sync\n ");
+
+		*((vu_short *)dest) = (ushort)data;
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while (*(vu_short *)dest != (ushort)data) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+		dest -= 2;
+		data >>= 16;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/sacsng/ioconfig.h b/u-boot/board/sacsng/ioconfig.h
new file mode 100644
index 0000000..be1ce7c
--- /dev/null
+++ b/u-boot/board/sacsng/ioconfig.h
@@ -0,0 +1,217 @@
+/*
+ * I/O Port configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#ifdef SKIP
+#undef SKIP
+#endif
+
+#ifdef CONF
+#undef CONF
+#endif
+
+#ifdef DIN
+#undef DIN
+#endif
+
+#ifdef DOUT
+#undef DOUT
+#endif
+
+#ifdef GPIO
+#undef GPIO
+#endif
+
+#ifdef SPEC
+#undef SPEC
+#endif
+
+#ifdef ACTV
+#undef ACTV
+#endif
+
+#ifdef OPEN
+#undef OPEN
+#endif
+
+#define SKIP 0  /* SKIP over this port */
+#define CONF 1  /* CONFiguration the port */
+
+#define DIN  0  /* PDIRx 0: Direction IN  */
+#define DOUT 1  /* PDIRx 1: Direction OUT */
+
+#define GPIO 0  /* PPARx 0: General Purpose I/O */
+#define SPEC 1  /* PPARx 1: dedicated to a peripheral function, */
+		/*          i.e. the port has a SPECial use. */
+
+#define ACTV 0  /* PODRx 0: ACTiVely driven as an output */
+#define OPEN 1  /* PODRx 1: OPEN-drain driver */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	     conf  ppar  psor  pdir  podr  pdat */
+	/* PA31 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS8*        */
+	/* PA30 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS7*        */
+	/* PA29 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS6*        */
+	/* PA28 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS5*        */
+	/* PA27 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS4*        */
+	/* PA26 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS3*        */
+	/* PA25 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS2*        */
+	/* PA24 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS1*        */
+	/* PA23 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* ODIS_EN*       */
+	/* PA22 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED2_EN*     */
+	/* PA21 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED1_EN*     */
+	/* PA20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED3_EN*      */
+	/* PA19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED2_EN*      */
+	/* PA18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* PLED1_EN*      */
+	/* PA17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PA16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* DAC_RST*       */
+	/* PA15 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH34SDATA_PU   */
+	/* PA14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH12SDATA_PU   */
+	/* PA13 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SLRCLK_EN*     */
+	/* PA12 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4ACDC*    */
+	/* PA11 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4TEDS*    */
+	/* PA10 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4XTDS*    */
+	/* PA9  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3ACDC*    */
+	/* PA8  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3TEDS*    */
+	/* PA7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3XTDS*    */
+	/* PA6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2ACDC*    */
+	/* PA5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2TEDS*    */
+	/* PA4  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2XTDS*    */
+	/* PA3  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PA2  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1ACDC*    */
+	/* PA1  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1TEDS*    */
+	/* PA0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }  /* MTRX_1XTDS*    */
+    },
+
+    /* Port B configuration */
+    {	/*	     conf  ppar  psor  pdir  podr  pdat */
+	/* PB31 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_ER */
+	/* PB30 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_DV */
+	/* PB29 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_EN */
+	/* PB28 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_ER */
+	/* PB27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_COL   */
+	/* PB26 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_CRS   */
+	/* PB25 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD3  */
+	/* PB24 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD2  */
+	/* PB23 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD1  */
+	/* PB22 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD0  */
+	/* PB21 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD0  */
+	/* PB20 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD1  */
+	/* PB19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD2  */
+	/* PB18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD3  */
+	/* PB17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB14 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDC1,   BSDATA_ADC12 */
+	/* PB13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB12 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCC1, LRCLK  */
+	/* PB11 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1TXDD1,   RSDATA_DAC12 */
+	/* PB10 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDD1,   BSDATA_ADC34 */
+	/* PB9  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB8  */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCD1, LRCLK  */
+	/* PB7  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* XCITE_SHDN     */
+	/* PB5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* TRIGGER        */
+	/* PB4  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* ARM            */
+	/* PB3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar  psor  pdir  podr  pdat */
+	/* PC31 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC30 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC29 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK3,  MCLK    */
+	/* PC28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
+#ifdef QQQ
+	/* PC28 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
+#endif
+	/* PC27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK5,  SCLK    */
+	/* PC26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC25 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK7,  SCLK    */
+	/* PC24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC23 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK9,  MCLK    */
+	/* PC22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC21 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO6 (LRCLK)  */
+	/* PC20 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK13, MII_RXCLK  */
+	/* PC18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK14, MII_TXCLK  */
+	/* PC17 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO8 (SCLK)   */
+	/* PC16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC15 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC2_TX        */
+	/* PC14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB3      */
+	/* PC11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* TDM_STRB4      */
+	/* PC9  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN3      */
+	/* PC8  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN2      */
+	/* PC7  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN1      */
+	/* PC6  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC5  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN2*      */
+	/* PC4  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN1*      */
+	/* PC3  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* MUSH_STAT      */
+	/* PC2  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* OUTDRV_STAT    */
+	/* PC1  */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* PHY_MDIO       */
+	/* PC0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PHY_MDC        */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar  psor  pdir  podr  pdat */
+	/* PD31 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SCC1_RX        */
+	/* PD30 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SCC1_TX        */
+	/* PD29 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD27 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD25 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD23 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD21 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_ADC_CS*    */
+	/* PD19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_DAC_CS*    */
+#if defined(CONFIG_SOFT_SPI)
+	/* PD18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_CLK        */
+	/* PD17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
+	/* PD16 */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* SPI_MISO       */
+#else
+	/* PD18 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_CLK        */
+	/* PD17 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
+	/* PD16 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* SPI_MISO       */
+#endif
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* I2C_SCL        */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SCL        */
+#else /* normal I/O port pins */
+	/* PD15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SCL        */
+#endif
+#endif
+	/* PD13 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB1      */
+	/* PD12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB2      */
+	/* PD11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* BRGO4 (MCLK)   */
+	/* PD9  */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC1_TX        */
+	/* PD8  */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SMC1_RX        */
+	/* PD7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD4  */ { CONF, SPEC,   1,  DOUT, ACTV,   1   }, /* SMC2_RX        */
+	/* PD3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
+    }
+};
diff --git a/u-boot/board/sacsng/sacsng.c b/u-boot/board/sacsng/sacsng.c
new file mode 100644
index 0000000..61cab87
--- /dev/null
+++ b/u-boot/board/sacsng/sacsng.c
@@ -0,0 +1,869 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Gerald Van Baren <vanbaren@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+#include <spi.h>
+#include <command.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+#include "clkinit.h"
+#include "ioconfig.h" /* I/O configuration table */
+
+/*
+ * PBI Page Based Interleaving
+ *   PSDMR_PBI page based interleaving
+ *   0         bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ *   (this can help with marginal board layouts)
+ *   PSDMR_EAMUX  adds a clock
+ *   0            no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ *   PSDMR_BUFCMD adds a clock
+ *   0            no extra clock
+ */
+#define CONFIG_PBI		PSDMR_PBI
+#define PESSIMISTIC_SDRAM	0
+#define EAMUX			0	/* EST requires EAMUX */
+#define BUFCMD			0
+
+/*
+ * ADC/DAC Defines:
+ */
+#define INITIAL_SAMPLE_RATE 10016     /* Initial Daq sample rate */
+#define INITIAL_RIGHT_JUST  0         /* Initial DAC right justification */
+#define INITIAL_MCLK_DIVIDE 0         /* Initial MCLK Divide */
+#define INITIAL_SAMPLE_64X  1         /* Initial  64x clocking mode */
+#define INITIAL_SAMPLE_128X 0         /* Initial 128x clocking mode */
+
+/*
+ * ADC Defines:
+ */
+#define I2C_ADC_1_ADDR 0x0E           /* I2C Address of the ADC #1 */
+#define I2C_ADC_2_ADDR 0x0F           /* I2C Address of the ADC #2 */
+
+#define ADC_SDATA1_MASK 0x00020000    /* PA14 - CH12SDATA_PU   */
+#define ADC_SDATA2_MASK 0x00010000    /* PA15 - CH34SDATA_PU   */
+
+#define ADC_VREF_CAP   100            /* VREF capacitor in uF */
+#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
+#define ADC_SDATA_DELAY    100        /* ADC SDATA release delay in usec */
+#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
+				      /* Wait at least 4100 LRCLK's */
+
+#define ADC_REG1_FRAME_START    0x80  /* Frame start */
+#define ADC_REG1_GROUND_CAL     0x40  /* Ground calibration enable */
+#define ADC_REG1_ANA_MOD_PDOWN  0x20  /* Analog modulator section in power down */
+#define ADC_REG1_DIG_MOD_PDOWN  0x10  /* Digital modulator section in power down */
+
+#define ADC_REG2_128x           0x80  /* Oversample at 128x */
+#define ADC_REG2_CAL            0x40  /* System calibration enable */
+#define ADC_REG2_CHANGE_SIGN    0x20  /* Change sign enable */
+#define ADC_REG2_LR_DISABLE     0x10  /* Left/Right output disable */
+#define ADC_REG2_HIGH_PASS_DIS  0x08  /* High pass filter disable */
+#define ADC_REG2_SLAVE_MODE     0x04  /* Slave mode */
+#define ADC_REG2_DFS            0x02  /* Digital format select */
+#define ADC_REG2_MUTE           0x01  /* Mute */
+
+#define ADC_REG7_ADDR_ENABLE    0x80  /* Address enable */
+#define ADC_REG7_PEAK_ENABLE    0x40  /* Peak enable */
+#define ADC_REG7_PEAK_UPDATE    0x20  /* Peak update */
+#define ADC_REG7_PEAK_FORMAT    0x10  /* Peak display format */
+#define ADC_REG7_DIG_FILT_PDOWN 0x04  /* Digital filter power down enable */
+#define ADC_REG7_FIR2_IN_EN     0x02  /* External FIR2 input enable */
+#define ADC_REG7_PSYCHO_EN      0x01  /* External pyscho filter input enable */
+
+/*
+ * DAC Defines:
+ */
+
+#define I2C_DAC_ADDR 0x11             /* I2C Address of the DAC */
+
+#define DAC_RST_MASK 0x00008000       /* PA16 - DAC_RST*  */
+#define DAC_RESET_DELAY    100        /* DAC reset delay in usec */
+#define DAC_INITIAL_DELAY 5000        /* DAC initialization delay in usec */
+
+#define DAC_REG1_AMUTE   0x80         /* Auto-mute */
+
+#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit  */
+#define DAC_REG1_I2S_24_BIT       (1 << 4) /* Fmt 1: I2S up to 24 bit       */
+#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
+#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
+#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
+#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
+
+#define DAC_REG1_DEM_NO           (0 << 2) /* No      De-emphasis  */
+#define DAC_REG1_DEM_44KHZ        (1 << 2) /* 44.1KHz De-emphasis  */
+#define DAC_REG1_DEM_48KHZ        (2 << 2) /* 48KHz   De-emphasis  */
+#define DAC_REG1_DEM_32KHZ        (3 << 2) /* 32KHz   De-emphasis  */
+
+#define DAC_REG1_SINGLE 0             /*   4- 50KHz sample rate  */
+#define DAC_REG1_DOUBLE 1             /*  50-100KHz sample rate  */
+#define DAC_REG1_QUAD   2             /* 100-200KHz sample rate  */
+#define DAC_REG1_DSD    3             /* Direct Stream Data, DSD */
+
+#define DAC_REG5_INVERT_A   0x80      /* Invert channel A */
+#define DAC_REG5_INVERT_B   0x40      /* Invert channel B */
+#define DAC_REG5_I2C_MODE   0x20      /* Control port (I2C) mode */
+#define DAC_REG5_POWER_DOWN 0x10      /* Power down mode */
+#define DAC_REG5_MUTEC_A_B  0x08      /* Mutec A=B */
+#define DAC_REG5_FREEZE     0x04      /* Freeze */
+#define DAC_REG5_MCLK_DIV   0x02      /* MCLK divide by 2 */
+#define DAC_REG5_RESERVED   0x01      /* Reserved */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+    printf ("SACSng\n");
+
+    return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram(int board_type)
+{
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+    volatile uchar c = 0;
+    volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+    uint  psdmr = CONFIG_SYS_PSDMR;
+    int   i;
+    uint   psrt = 14;					/* for no SPD */
+    uint   chipselects = 1;				/* for no SPD */
+    uint   sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024;	/* for no SPD */
+    uint   or = CONFIG_SYS_OR2_PRELIM;				/* for no SPD */
+#ifdef SDRAM_SPD_ADDR
+    uint   data_width;
+    uint   rows;
+    uint   banks;
+    uint   cols;
+    uint   caslatency;
+    uint   width;
+    uint   rowst;
+    uint   sdam;
+    uint   bsma;
+    uint   sda10;
+    u_char spd_size;
+    u_char data;
+    u_char cksum;
+    int    j;
+#endif
+
+#ifdef SDRAM_SPD_ADDR
+    /* Keep the compiler from complaining about potentially uninitialized vars */
+    data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
+
+    /*
+     * Read the SDRAM SPD EEPROM via I2C.
+     */
+    i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+    spd_size = data;
+    cksum    = data;
+    for(j = 1; j < 64; j++) {	/* read only the checksummed bytes */
+	/* note: the I2C address autoincrements when alen == 0 */
+	i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+	     if(j ==  5) chipselects = data & 0x0F;
+	else if(j ==  6) data_width  = data;
+	else if(j ==  7) data_width |= data << 8;
+	else if(j ==  3) rows        = data & 0x0F;
+	else if(j ==  4) cols        = data & 0x0F;
+	else if(j == 12) {
+	    /*
+	     * Refresh rate: this assumes the prescaler is set to
+	     * approximately 1uSec per tick.
+	     */
+	    switch(data & 0x7F) {
+		default:
+		case 0:  psrt =  14 ; /*  15.625uS */  break;
+		case 1:  psrt =   2;  /*   3.9uS   */  break;
+		case 2:  psrt =   6;  /*   7.8uS   */  break;
+		case 3:  psrt =  29;  /*  31.3uS   */  break;
+		case 4:  psrt =  60;  /*  62.5uS   */  break;
+		case 5:  psrt = 120;  /* 125uS     */  break;
+	    }
+	}
+	else if(j == 17) banks       = data;
+	else if(j == 18) {
+	    caslatency = 3; /* default CL */
+#if(PESSIMISTIC_SDRAM)
+		 if((data & 0x04) != 0) caslatency = 3;
+	    else if((data & 0x02) != 0) caslatency = 2;
+	    else if((data & 0x01) != 0) caslatency = 1;
+#else
+		 if((data & 0x01) != 0) caslatency = 1;
+	    else if((data & 0x02) != 0) caslatency = 2;
+	    else if((data & 0x04) != 0) caslatency = 3;
+#endif
+	    else {
+		printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+			data);
+	    }
+	}
+	else if(j == 63) {
+	    if(data != cksum) {
+		printf ("WARNING: Configuration data checksum failure:"
+			" is 0x%02x, calculated 0x%02x\n",
+			data, cksum);
+	    }
+	}
+	cksum += data;
+    }
+
+    /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+    if(caslatency < 2) {
+	printf("WARNING: CL was %d, forcing to 2\n", caslatency);
+	caslatency = 2;
+    }
+    if(rows > 14) {
+	printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
+	rows = 14;
+    }
+    if(cols > 11) {
+	printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
+	cols = 11;
+    }
+
+    if((data_width != 64) && (data_width != 72))
+    {
+	printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+	    data_width);
+    }
+    width = 3;		/* 2^3 = 8 bytes = 64 bits wide */
+    /*
+     * Convert banks into log2(banks)
+     */
+    if     (banks == 2)	banks = 1;
+    else if(banks == 4)	banks = 2;
+    else if(banks == 8)	banks = 3;
+
+    sdram_size = 1 << (rows + cols + banks + width);
+
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+    rowst = 32 - (rows + banks + cols + width);
+#endif
+
+    or = ~(sdram_size - 1)    |	/* SDAM address mask	*/
+	  ((banks-1) << 13)   |	/* banks per device	*/
+	  (rowst << 9)        |	/* rowst		*/
+	  ((rows - 9) << 6);	/* numr			*/
+
+    memctl->memc_or2 = or;
+
+    /*
+     * SDAM specifies the number of columns that are multiplexed
+     * (reference AN2165/D), defined to be (columns - 6) for page
+     * interleave, (columns - 8) for bank interleave.
+     *
+     * BSMA is 14 - max(rows, cols).  The bank select lines come
+     * into play above the highest "address" line going into the
+     * the SDRAM.
+     */
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    sdam = cols - 8;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam + 2;
+#else
+    sdam = cols - 6;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_16_CLK       |\
+	     PSDMR_PRETOACT_8W       |\
+	     PSDMR_ACTTORW_8W        |\
+	     PSDMR_WRC_4C            |\
+	     PSDMR_EAMUX             |\
+	     PSDMR_BUFCMD)           |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#else
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_7_CLK        |\
+	     PSDMR_PRETOACT_3W       |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_ACTTORW_2W        |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_WRC_1C            |	/* 1 clock + 7nSec */
+	     EAMUX                   |\
+	     BUFCMD)                 |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#endif
+#endif
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     * Quote from Micron MT48LC8M16A2 data sheet:
+     *
+     *  "...the SDRAM requires a 100uS delay prior to issuing any
+     *  command other than a COMMAND INHIBIT or NOP.  Starting at some
+     *  point during this 100uS period and continuing at least through
+     *  the end of this period, COMMAND INHIBIT or NOP commands should
+     *  be applied."
+     *
+     *  "Once the 100uS delay has been satisfied with at least one COMMAND
+     *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
+     *  should be applied.  All banks must then be precharged, thereby
+     *  placing the device in the all banks idle state."
+     *
+     *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
+     *  performed.  After the AUTO REFRESH cycles are complete, the
+     *  SDRAM is ready for mode register programming."
+     *
+     *  (/emphasis/ mine, gvb)
+     *
+     *  The way I interpret this, Micron start up sequence is:
+     *  1. Issue a PRECHARGE-BANK command (initial precharge)
+     *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+     *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+     *  4. Issue a MODE-SET command to initialize the mode register
+     *
+     *  --------
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+     */
+
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+    memctl->memc_psrt  = psrt;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+
+    /*
+     * Do it a second time for the second set of chips if the DIMM has
+     * two chip selects (double sided).
+     */
+    if(chipselects > 1) {
+	ramaddr += sdram_size;
+
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
+	memctl->memc_or3 = or;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+	    *ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+    }
+
+    /* return total ram size */
+    return (sdram_size * chipselects);
+}
+
+/*-----------------------------------------------------------------------
+ * Board Control Functions
+ */
+void board_poweroff (void)
+{
+    while (1);		/* hang forever */
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r(void)
+{
+    /*
+     * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
+     */
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
+    volatile ioport_t *iop  = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
+
+    int  reg;          /* I2C register value */
+    char *ep;          /* Environment pointer */
+    char str_buf[12] ; /* sprintf output buffer */
+    int  sample_rate;  /* ADC/DAC sample rate */
+    int  sample_64x;   /* Use  64/4 clocking for the ADC/DAC */
+    int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
+    int  right_just;   /* Is the data to the DAC right justified? */
+    int  mclk_divide;  /* MCLK Divide */
+    int  quiet;        /* Quiet or minimal output mode */
+
+    quiet = 0;
+    if ((ep = getenv("quiet")) != NULL) {
+	quiet = simple_strtol(ep, NULL, 10);
+    }
+    else {
+	setenv("quiet", "0");
+    }
+
+    /*
+     * SACSng custom initialization:
+     *    Start the ADC and DAC clocks, since the Crystal parts do not
+     *    work on the I2C bus until the clocks are running.
+     */
+
+    sample_rate = INITIAL_SAMPLE_RATE;
+    if ((ep = getenv("DaqSampleRate")) != NULL) {
+	sample_rate = simple_strtol(ep, NULL, 10);
+    }
+
+    sample_64x  = INITIAL_SAMPLE_64X;
+    sample_128x = INITIAL_SAMPLE_128X;
+    if ((ep = getenv("Daq64xSampling")) != NULL) {
+	sample_64x = simple_strtol(ep, NULL, 10);
+	if (sample_64x) {
+	    sample_128x = 0;
+	}
+	else {
+	    sample_128x = 1;
+	}
+    }
+    else {
+	if ((ep = getenv("Daq128xSampling")) != NULL) {
+	    sample_128x = simple_strtol(ep, NULL, 10);
+	    if (sample_128x) {
+		sample_64x = 0;
+	    }
+	    else {
+		sample_64x = 1;
+	    }
+	}
+    }
+
+    /*
+     * Stop the clocks and wait for at least 1 LRCLK period
+     * to make sure the clocking has really stopped.
+     */
+    Daq_Stop_Clocks();
+    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+    /*
+     * Initialize the clocks with the new rates
+     */
+    Daq_Init_Clocks(sample_rate, sample_64x);
+    sample_rate = Daq_Get_SampleRate();
+
+    /*
+     * Start the clocks and wait for at least 1 LRCLK period
+     * to make sure the clocking has become stable.
+     */
+    Daq_Start_Clocks(sample_rate);
+    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+    sprintf(str_buf, "%d", sample_rate);
+    setenv("DaqSampleRate", str_buf);
+
+    if (sample_64x) {
+	setenv("Daq64xSampling",  "1");
+	setenv("Daq128xSampling", NULL);
+    }
+    else {
+	setenv("Daq64xSampling",  NULL);
+	setenv("Daq128xSampling", "1");
+    }
+
+    /*
+     * Display the ADC/DAC clocking information
+     */
+    if (!quiet) {
+	Daq_Display_Clocks();
+    }
+
+    /*
+     * Determine the DAC data justification
+     */
+
+    right_just = INITIAL_RIGHT_JUST;
+    if ((ep = getenv("DaqDACRightJustified")) != NULL) {
+	right_just = simple_strtol(ep, NULL, 10);
+    }
+
+    sprintf(str_buf, "%d", right_just);
+    setenv("DaqDACRightJustified", str_buf);
+
+    /*
+     * Determine the DAC MCLK Divide
+     */
+
+    mclk_divide = INITIAL_MCLK_DIVIDE;
+    if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
+	mclk_divide = simple_strtol(ep, NULL, 10);
+    }
+
+    sprintf(str_buf, "%d", mclk_divide);
+    setenv("DaqDACMClockDivide", str_buf);
+
+    /*
+     * Initializing the I2C address in the Crystal A/Ds:
+     *
+     * 1) Wait for VREF cap to settle (10uSec per uF)
+     * 2) Release pullup on SDATA
+     * 3) Write the I2C address to register 6
+     * 4) Enable address matching by setting the MSB in register 7
+     */
+
+    if (!quiet) {
+	printf("Initializing the ADC...\n");
+    }
+    udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */
+
+    iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
+    udelay(ADC_SDATA_DELAY);		/* arbitrary settling time */
+
+    i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR);	/* set address */
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x07,         /* turn on ADDREN */
+		  ADC_REG7_ADDR_ENABLE);
+
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
+		  (sample_64x ? 0 : ADC_REG2_128x) |
+		  ADC_REG2_HIGH_PASS_DIS |
+		  ADC_REG2_SLAVE_MODE);
+
+    reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
+    if(reg != I2C_ADC_1_ADDR)
+	printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
+	       reg, I2C_ADC_1_ADDR);
+
+    iopa->pdat &= ~ADC_SDATA2_MASK;	/* release SDATA2 */
+    udelay(ADC_SDATA_DELAY);		/* arbitrary settling time */
+
+    i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);	/* set address (do not set ADDREN yet) */
+
+    i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
+		  (sample_64x ? 0 : ADC_REG2_128x) |
+		  ADC_REG2_HIGH_PASS_DIS |
+		  ADC_REG2_SLAVE_MODE);
+
+    reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
+    if(reg != I2C_ADC_2_ADDR)
+	printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
+	       reg, I2C_ADC_2_ADDR);
+
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
+		  ADC_REG1_FRAME_START |
+		  ADC_REG1_GROUND_CAL);
+
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
+		  (sample_64x ? 0 : ADC_REG2_128x) |
+		  ADC_REG2_CAL |
+		  ADC_REG2_HIGH_PASS_DIS |
+		  ADC_REG2_SLAVE_MODE);
+
+    udelay(ADC_CAL_DELAY);		/* a minimum of 4100 LRCLKs */
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00);	/* remove GNDCAL */
+
+    /*
+     * Now that we have synchronized the ADC's, enable address
+     * selection on the second ADC as well as the first.
+     */
+    i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
+
+    /*
+     * Initialize the Crystal DAC
+     *
+     * Two of the config lines are used for I2C so we have to set them
+     * to the proper initialization state without inadvertantly
+     * sending an I2C "start" sequence.  When we bring the I2C back to
+     * the normal state, we send an I2C "stop" sequence.
+     */
+    if (!quiet) {
+	printf("Initializing the DAC...\n");
+    }
+
+    /*
+     * Bring the I2C clock and data lines low for initialization
+     */
+    I2C_SCL(0);
+    I2C_DELAY;
+    I2C_SDA(0);
+    I2C_ACTIVE;
+    I2C_DELAY;
+
+    /* Reset the DAC */
+    iopa->pdat &= ~DAC_RST_MASK;
+    udelay(DAC_RESET_DELAY);
+
+    /* Release the DAC reset */
+    iopa->pdat |=  DAC_RST_MASK;
+    udelay(DAC_INITIAL_DELAY);
+
+    /*
+     * Cause the DAC to:
+     *     Enable control port (I2C mode)
+     *     Going into power down
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		  DAC_REG5_I2C_MODE |
+		  DAC_REG5_POWER_DOWN);
+
+    /*
+     * Cause the DAC to:
+     *     Enable control port (I2C mode)
+     *     Going into power down
+     *         . MCLK divide by 1
+     *         . MCLK divide by 2
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		  DAC_REG5_I2C_MODE |
+		  DAC_REG5_POWER_DOWN |
+		  (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+    /*
+     * Cause the DAC to:
+     *     Auto-mute disabled
+     *         . Format 0, left  justified 24 bits
+     *         . Format 3, right justified 24 bits
+     *     No de-emphasis
+     *         . Single speed mode
+     *         . Double speed mode
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x01,
+		  (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
+				DAC_REG1_LEFT_JUST_24_BIT) |
+		  DAC_REG1_DEM_NO |
+		  (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
+
+    sprintf(str_buf, "%d",
+	    sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
+    setenv("DaqDACFunctionalMode", str_buf);
+
+    /*
+     * Cause the DAC to:
+     *     Enable control port (I2C mode)
+     *     Remove power down
+     *         . MCLK divide by 1
+     *         . MCLK divide by 2
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		  DAC_REG5_I2C_MODE |
+		  (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+    /*
+     * Create a I2C stop condition:
+     *     low->high on data while clock is high.
+     */
+    I2C_SCL(1);
+    I2C_DELAY;
+    I2C_SDA(1);
+    I2C_DELAY;
+    I2C_TRISTATE;
+
+    if (!quiet) {
+	printf("\n");
+    }
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+    /*
+     * Run the Ethernet loopback test
+     */
+    eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+    /*
+     * Turn off the RED fail LED now that we are up and running.
+     */
+    status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+#endif
+
+    return 0;
+}
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+/*
+ * Show boot status: flash the LED if something goes wrong, indicating
+ * that last thing that worked and thus, by implication, what is broken.
+ *
+ * This stores the last OK value in RAM so this will not work properly
+ * before RAM is initialized.  Since it is being used for indicating
+ * boot status (i.e. after RAM is initialized), that is OK.
+ */
+static void flash_code(uchar number, uchar modulo, uchar digits)
+{
+    int   j;
+
+    /*
+     * Recursively do upper digits.
+     */
+    if(digits > 1) {
+	flash_code(number / modulo, modulo, digits - 1);
+    }
+
+    number = number % modulo;
+
+    /*
+     * Zero is indicated by one long flash (dash).
+     */
+    if(number == 0) {
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+	udelay(1000000);
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+	udelay(200000);
+    } else {
+	/*
+	 * Non-zero is indicated by short flashes, one per count.
+	 */
+	for(j = 0; j < number; j++) {
+	    status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+	    udelay(100000);
+	    status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+	    udelay(200000);
+	}
+    }
+    /*
+     * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
+     */
+    udelay(700000);
+}
+
+static int last_boot_progress;
+
+void show_boot_progress (int status)
+{
+    int i,j;
+    if(status > 0) {
+	last_boot_progress = status;
+    } else {
+	/*
+	 * If a specific failure code is given, flash this code
+	 * else just use the last success code we've seen
+	 */
+	if(status < -1)
+	    last_boot_progress = -status;
+
+	/*
+	 * Flash this code 5 times
+	 */
+	for(j=0; j<5; j++) {
+	    /*
+	     * Houston, we have a problem.
+	     * Blink the last OK status which indicates where things failed.
+	     */
+	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    flash_code(last_boot_progress, 5, 3);
+
+	    /*
+	     * Delay 5 seconds between repetitions,
+	     * with the fault LED blinking
+	     */
+	    for(i=0; i<5; i++) {
+		status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+		udelay(500000);
+		status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+		udelay(500000);
+	    }
+	}
+
+	/*
+	 * Reset the board to retry initialization.
+	 */
+	do_reset (NULL, 0, 0, NULL);
+    }
+}
+#endif /* CONFIG_SHOW_BOOT_PROGRESS */
+
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#if defined(CONFIG_CMD_SPI)
+
+#define SPI_ADC_CS_MASK	0x00000800
+#define SPI_DAC_CS_MASK	0x00001000
+
+static const u32 cs_mask[] = {
+    SPI_ADC_CS_MASK,
+    SPI_DAC_CS_MASK,
+};
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+    return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+    volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
+
+    iopd->pdat &= ~cs_mask[slave->cs];
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+    volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
+
+    iopd->pdat |= cs_mask[slave->cs];
+}
+
+#endif
+
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/u-boot/board/samsung/goni/Makefile b/u-boot/board/samsung/goni/Makefile
new file mode 100644
index 0000000..edc4665
--- /dev/null
+++ b/u-boot/board/samsung/goni/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= goni.o onenand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/samsung/goni/config.mk b/u-boot/board/samsung/goni/config.mk
new file mode 100644
index 0000000..e4581ca
--- /dev/null
+++ b/u-boot/board/samsung/goni/config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (C) 2010 Samsung Electronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x50000000 (256MiB)
+#
+CONFIG_SYS_TEXT_BASE = 0x34800000
diff --git a/u-boot/board/samsung/goni/goni.c b/u-boot/board/samsung/goni/goni.c
new file mode 100644
index 0000000..581935d
--- /dev/null
+++ b/u-boot/board/samsung/goni/goni.c
@@ -0,0 +1,98 @@
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct s5pc110_gpio *s5pc110_gpio;
+
+int board_init(void)
+{
+	/* Set Initial global variables */
+	s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
+
+	gd->bd->bi_arch_number = MACH_TYPE_GONI;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
+			PHYS_SDRAM_3_SIZE;
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board:\tGoni\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i;
+
+	/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
+	gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
+
+	/*
+	 * MMC0 GPIO
+	 * GPG0[0]	SD_0_CLK
+	 * GPG0[1]	SD_0_CMD
+	 * GPG0[2]	SD_0_CDn	-> Not used
+	 * GPG0[3:6]	SD_0_DATA[0:3]
+	 */
+	for (i = 0; i < 7; i++) {
+		if (i == 2)
+			continue;
+		/* GPG0[0:6] special function 2 */
+		gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
+		/* GPG0[0:6] pull disable */
+		gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
+		/* GPG0[0:6] drv 4x */
+		gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
+	}
+
+	return s5p_mmc_init(0, 4);
+}
+#endif
diff --git a/u-boot/board/samsung/goni/lowlevel_init.S b/u-boot/board/samsung/goni/lowlevel_init.S
new file mode 100644
index 0000000..30a5835
--- /dev/null
+++ b/u-boot/board/samsung/goni/lowlevel_init.S
@@ -0,0 +1,585 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has S5PC100 GPIO base, 0xE0300000
+ * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
+ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
+ */
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r11, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r7, =S5PC100_GPIO_BASE
+	ldr	r8, =S5PC100_GPIO_BASE
+	/* Read CPU ID */
+	ldr	r2, =S5PC110_PRO_ID
+	ldr	r0, [r2]
+	mov	r1, #0x00010000
+	and	r0, r0, r1
+	cmp	r0, r5
+	beq	100f
+	ldr	r8, =S5PC110_GPIO_BASE
+100:
+	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
+	cmp	r7, r8
+	beq	skip_check_didle			@ Support C110 only
+
+	ldr	r0, =S5PC110_RST_STAT
+	ldr	r1, [r0]
+	and	r1, r1, #0x000D0000
+	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
+	beq	didle_wakeup
+	cmp	r7, r8
+
+skip_check_didle:
+	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
+	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
+	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
+	orr	r1, r1, #(0x1 << 4)
+	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
+#ifdef CONFIG_ONENAND_IPL
+	orr	r1, r1, #(1 << 1)			@ 1 * 1-bit
+#else
+	bic	r1, r1, #(1 << 1)
+#endif
+	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
+
+	/* Don't setup at s5pc100 */
+	beq	100f
+
+	/*
+	 * Initialize Async Register Setting for EVT1
+	 * Because we are setting EVT1 as the default value of EVT0,
+	 * setting EVT0 as well does not make things worse.
+	 * Thus, for the simplicity, we set for EVT0, too
+	 *
+	 * The "Async Registers" are:
+	 *	0xE0F0_0000
+	 *	0xE1F0_0000
+	 *	0xF180_0000
+	 *	0xF190_0000
+	 *	0xF1A0_0000
+	 *	0xF1B0_0000
+	 *	0xF1C0_0000
+	 *	0xF1D0_0000
+	 *	0xF1E0_0000
+	 *	0xF1F0_0000
+	 *	0xFAF0_0000
+	 */
+	ldr     r0, =0xe0f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xe1f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1800000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1900000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1a00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1b00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1c00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1d00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1e00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xfaf00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	/*
+	 * Diable ABB block to reduce sleep current at low temperature
+	 * Note that it's hidden register setup don't modify it
+	 */
+	ldr	r0, =0xE010C300
+	ldr	r1, =0x00800000
+	str	r1, [r0]
+
+100:
+	/* IO retension release */
+	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
+	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
+	ldr	r1, [r0]
+	ldreq	r2, =(1 << 31)				@ IO_RET_REL
+	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+	orr	r1, r1, r2
+	/* Do not release retention here for S5PC110 */
+	streq	r1, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Disable Watchdog */
+	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
+	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
+	str	r5, [r0]
+
+	/* setting SRAM */
+	ldreq	r0, =S5PC100_SROMC_BASE
+	ldrne	r0, =S5PC110_SROMC_BASE
+	ldr	r1, =0x9
+	str	r1, [r0]
+#endif
+
+	/* S5PC100 has 3 groups of interrupt sources */
+	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
+	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
+	add	r1, r0, #0x00100000
+	add	r2, r0, #0x00200000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@ INTENCLEAR
+	str	r3, [r1, #0x14]				@ INTENCLEAR
+	str	r3, [r2, #0x14]				@ INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@ INTSELECT
+	str	r5, [r1, #0xc]				@ INTSELECT
+	str	r5, [r2, #0xc]				@ INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@ INTADDRESS
+	str	r5, [r1, #0xf00]			@ INTADDRESS
+	str	r5, [r2, #0xf00]			@ INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+	/* for UART */
+	bl	uart_asm_init
+
+	bl	internal_ram_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+	/* init system clock */
+	bl	system_clock_init
+
+	/* OneNAND Sync Read Support at S5PC110 only
+	 * RM[15]	: Sync Read
+	 * BRWL[14:12]	: 7 CLK
+	 * BL[11:9]	: Continuous
+	 * VHF[3]	: Very High Frequency Enable (Over 83MHz)
+	 * HF[2]	: High Frequency Enable (Over 66MHz)
+	 * WM[1]	: Sync Write
+	 */
+	cmp	r7, r8
+	ldrne	r1, =0xE006
+	ldrne	r0, =0xB001E442
+	strneh	r1, [r0]
+
+	/*
+	 * GCE[26]	: Gated Clock Enable
+	 * RPE[17]	: Enables Read Prefetch
+	 */
+	ldrne	r1, =((1 << 26) | (1 << 17) | 0xE006)
+	ldrne	r0, =0xB0600000
+	strne	r1, [r0, #0x100]			@ ONENAND_IF_CTRL
+	ldrne	r1, =0x1212
+	strne	r1, [r0, #0x108]
+
+	/* Board detection to set proper memory configuration */
+	cmp	r7, r8
+	moveq	r9, #1		/* r9 has 1Gib default at s5pc100 */
+	movne	r9, #2		/* r9 has 2Gib default at s5pc110 */
+
+	ldr	r2, =0xE0200200
+	ldr	r4, [r2, #0x48]
+
+	bic	r1, r4, #(0x3F << 4)	/* PULLUP_DISABLE: 3 * 2-bit */
+	bic	r1, r1, #(0x3 << 2)	/* PULLUP_DISABLE: 2 * 2-bit */
+	bic	r1, r1, #(0x3 << 14)	/* PULLUP_DISABLE: 2 * 2-bit */
+	str	r1, [r2, #0x48]
+	/* For write completion */
+	nop
+	nop
+
+	ldr	r3, [r2, #0x44]
+	and	r1, r3, #(0x7 << 2)
+	mov	r1, r1, lsr #2
+	cmp	r1, #0x5
+	moveq	r9, #3
+	cmp	r1, #0x6
+	moveq	r9, #1
+	cmp	r1, #0x7
+	moveq	r9, #2
+	and	r0, r3, #(0x1 << 1)
+	mov	r0, r0, lsr #1
+	orr	r1, r1, r0, lsl #3
+	cmp	r1, #0x8
+	moveq	r9, #3
+	and	r1, r3, #(0x7 << 2)
+	mov	r1, r1, lsr #2
+	and	r0, r3, #(0x1 << 7)
+	mov	r0, r0, lsr #7
+	orr	r1, r1, r0, lsl #3
+	cmp	r1, #0x9
+	moveq	r9, #3
+	str	r4, [r2, #0x48]		/* Restore PULLUP configuration */
+
+	bl	mem_ctrl_asm_init
+
+	/* Wakeup support. Don't know if it's going to be used, untested. */
+	ldreq	r0, =S5PC100_RST_STAT
+	ldrne	r0, =S5PC110_RST_STAT
+	ldr	r1, [r0]
+	biceq	r1, r1, #0xfffffff7
+	moveq	r2, #(1 << 3)
+	bicne	r1, r1, #0xfffeffff
+	movne	r2, #(1 << 16)
+	cmp	r1, r2
+	bne	1f
+wakeup:
+	/* turn off L2 cache */
+	bl	l2_cache_disable
+
+	cmp	r7, r8
+	ldreq	r0, =0xC100
+	ldrne	r0, =0xC110
+
+	/* invalidate L2 cache also */
+	bl	invalidate_dcache
+
+	/* turn on L2 cache */
+	bl	l2_cache_enable
+
+	cmp	r7, r8
+	/* Load return address and jump to kernel */
+	ldreq	r0, =S5PC100_INFORM0
+	ldrne	r0, =S5PC110_INFORM0
+
+	/* r1 = physical address of s5pc1xx_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel (sleep-s5pc1xx.S) */
+	mov	pc, r1
+	nop
+	nop
+#else
+	cmp	r7, r8
+	/* Clear wakeup status register */
+	ldreq	r0, =S5PC100_WAKEUP_STAT
+	ldrne	r0, =S5PC110_WAKEUP_STAT
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* IO retension release */
+	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
+	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
+	ldr	r1, [r0]
+	ldreq	r2, =(1 << 31)				@ IO_RET_REL
+	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+	orr	r1, r1, r2
+	str	r1, [r0]
+
+#endif
+	b	1f
+
+didle_wakeup:
+	/* Wait when APLL is locked */
+	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
+lockloop:
+	ldr	r1, [r0]
+	and	r1, r1, #(1 << 29)
+	cmp	r1, #(1 << 29)
+	bne	lockloop
+
+	ldr	r0, =S5PC110_INFORM0
+	ldr	r1, [r0]
+	mov	pc, r1
+	nop
+	nop
+	nop
+	nop
+	nop
+
+1:
+	mov	lr, r11
+	mov	pc, lr
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+100:
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
+	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
+	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
+	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
+
+	/* S5P_APLL_CON */
+	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
+	str	r1, [r0, #0x100]
+	/* S5P_MPLL_CON */
+	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+	str	r1, [r0, #0x104]
+	/* S5P_EPLL_CON */
+	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+	str	r1, [r0, #0x108]
+	/* S5P_HPLL_CON */
+	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
+	str	r1, [r0, #0x10C]
+
+	ldr     r1, [r0, #0x300]
+	ldr     r2, =0x00003fff
+	bic     r1, r1, r2
+	ldr     r2, =0x00011301
+
+	orr	r1, r1, r2
+	str	r1, [r0, #0x300]
+	ldr     r1, [r0, #0x304]
+	ldr     r2, =0x00011110
+	orr     r1, r1, r2
+	str     r1, [r0, #0x304]
+	ldr     r1, =0x00000001
+	str     r1, [r0, #0x308]
+
+	/* Set Source Clock */
+	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
+	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
+
+	b	200f
+110:
+	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
+
+	/* Set OSC_FREQ value */
+	ldr	r1, =0xf
+	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
+
+	/* Set MTC_STABLE value */
+	ldr	r1, =0xffffffff
+	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
+
+	/* Set CLAMP_STABLE value */
+	ldr	r1, =0x3ff03ff
+	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
+
+	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Clock divider */
+	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
+	str	r1, [r0, #0x300]
+	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
+	str	r1, [r0, #0x310]
+
+	/* Set Lock Time */
+	ldr	r1, =0x2cf			@ Locktime : 30us
+	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
+	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
+	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
+
+	/* S5PC110_APLL_CON */
+	ldr	r1, =0x80C80601			@ 800MHz
+	str	r1, [r0, #0x100]
+	/* S5PC110_MPLL_CON */
+	ldr	r1, =0x829B0C01			@ 667MHz
+	str	r1, [r0, #0x108]
+	/* S5PC110_EPLL_CON */
+	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
+	str	r1, [r0, #0x110]
+	/* S5PC110_VPLL_CON */
+	ldr	r1, =0x806C0603			@  54MHz
+	str	r1, [r0, #0x120]
+
+	/* Set Source Clock */
+	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
+	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
+
+	/* OneDRAM(DMC0) clock setting */
+	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
+	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
+	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
+	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
+
+	/* XCLKOUT = XUSBXTI 24MHz */
+	add	r2, r0, #0xE000			@ S5PC110_OTHERS
+	ldr     r1, [r2]
+	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
+	str	r1, [r2]
+
+	/* CLK_IP0 */
+	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
+	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
+
+	/* CLK_IP1 */
+	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
+						@ NANDXL[24]
+	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
+
+	/* CLK_IP2 */
+	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
+						@ HOSTIF[10] HSMMC0[16]
+						@ HSMMC2[18] VIC[27:24]
+	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
+
+	/* CLK_IP3 */
+	ldr	r1, =0x8eff038c			@ I2C[8:6]
+						@ SYSTIMER[16] UART0[17]
+						@ UART1[18] UART2[19]
+						@ UART3[20] WDT[22]
+						@ PWM[23] GPIO[26] SYSCON[27]
+	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
+
+	/* CLK_IP4 */
+	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
+	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
+
+200:
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+internal_ram_init:
+	ldreq	r0, =0xE3800000
+	ldrne	r0, =0xF1500000
+	ldr	r1, =0x0
+	str	r1, [r0]
+
+	mov	pc, lr
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	/* set GPIO to enable UART0-UART4 */
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
+	ldr	r1, =0x00002222
+	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+
+	/* UART_SEL GPK0[5] at S5PC100 */
+	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
+	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
+	orr	r1, r1, #(0x1 << 20)		@ Output
+	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
+	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
+	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
+	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+
+	b	200f
+110:
+	/*
+	 * Note that the following address
+	 * 0xE020'0360 is reserved address at S5PC100
+	 */
+	/* UART_SEL MP0_5[7] at S5PC110 */
+	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
+	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
+	orr	r1, r1, #(0x1 << 28)		@ Output
+	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
+	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
+	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
+	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+200:
+	mov	pc, lr
+#endif
diff --git a/u-boot/board/samsung/goni/mem_setup.S b/u-boot/board/samsung/goni/mem_setup.S
new file mode 100644
index 0000000..c4d2845
--- /dev/null
+++ b/u-boot/board/samsung/goni/mem_setup.S
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	cmp	r7, r8
+
+	ldreq	r0, =S5PC100_DMC_BASE			@ 0xE6000000
+	ldrne	r0, =S5PC110_DMC0_BASE			@ 0xF0000000
+	ldrne	r6, =S5PC110_DMC1_BASE			@ 0xF1400000
+
+	/* DLL parameter setting */
+	ldr	r1, =0x50101000
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+	ldr	r1, =0x000000f4
+	str	r1, [r0, #0x01C]			@ PHYCONTROL1_OFFSET
+	strne	r1, [r6, #0x01C]			@ PHYCONTROL1_OFFSET
+	ldreq	r1, =0x0
+	streq	r1, [r0, #0x020]			@ PHYCONTROL2_OFFSET
+
+	/* DLL on */
+	ldr	r1, =0x50101002
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	/* DLL start */
+	ldr	r1, =0x50101003
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	mov	r2, #0x4000
+wait:	subs	r2, r2, #0x1
+	cmp	r2, #0x0
+	bne	wait
+
+	cmp	r7, r8
+	/* Force value locking for DLL off */
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	/* DLL off */
+	ldr	r1, =0x50101009
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	/* auto refresh off */
+	ldr	r1, =0xff001010 | (1 << 7)
+	ldr	r2, =0xff001010 | (1 << 7)
+	str	r1, [r0, #0x000]			@ CONCONTROL_OFFSET
+	strne	r2, [r6, #0x000]			@ CONCONTROL_OFFSET
+
+	/*
+	 * Burst Length 4, 2 chips, 32-bit, LPDDR
+	 * OFF: dynamic self refresh, force precharge, dynamic power down off
+	 */
+	ldr	r1, =0x00212100
+	ldr	r2, =0x00212100
+	str	r1, [r0, #0x004]			@ MEMCONTROL_OFFSET
+	strne	r2, [r6, #0x004]			@ MEMCONTROL_OFFSET
+
+	/*
+	 * Note:
+	 * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
+	 * So finally Bank1 OneDRAM should address start at at 0x3000'0000
+	 */
+
+	/*
+	 * DMC0: CS0 : S5PC100/S5PC110
+	 * 0x30 -> 0x30000000
+	 * 0xf8 -> 0x37FFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	ldr	r3, =0x30f80222
+	ldr	r4, =0x40f00222
+swap_memory:
+	str	r3, [r0, #0x008]			@ MEMCONFIG0_OFFSET
+	str	r4, [r0, #0x00C]			@ dummy write
+
+	/*
+	 * DMC1: CS0 : S5PC110
+	 * 0x40 -> 0x40000000
+	 * 0xf8 -> 0x47FFFFFF (1Gib)
+	 * 0x40 -> 0x40000000
+	 * 0xf0 -> 0x4FFFFFFF (2Gib)
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits  - Col (1Gib)
+	 * [11:8 ] 3: 10 bits - Col (2Gib)
+	 * [ 7:4 ] 2: 14 bits - Row
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	/* Default : 2GiB */
+	ldr	r4, =0x40f01322				@ 2Gib: MCP B
+	ldr	r5, =0x50f81312				@ dummy: MCP D
+	cmp	r9, #1
+	ldreq	r4, =0x40f81222				@ 1Gib: MCP A
+	cmp	r9, #3
+	ldreq	r5, =0x50f81312				@ 2Gib + 1Gib: MCP D
+	cmp	r9, #4
+	ldreq	r5, =0x50f01312				@ 2Gib + 2Gib: MCP E
+
+	cmp	r7, r8
+	strne	r4, [r6, #0x008]			@ MEMCONFIG0_OFFSET
+	strne	r5, [r6, #0x00C]			@ MEMCONFIG1_OFFSET
+
+	/*
+	 * DMC0: CS1: S5PC100
+	 * 0x38 -> 0x38000000
+	 * 0xf8 -> 0x3fFFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	eoreq	r3, r3, #0x08000000
+	streq	r3, [r0, #0xc]				@ MEMCONFIG1_OFFSET
+
+	ldr	r1, =0x20000000
+	str	r1, [r0, #0x014]			@ PRECHCONFIG_OFFSET
+	strne	r1, [r0, #0x014]			@ PRECHCONFIG_OFFSET
+	strne	r1, [r6, #0x014]			@ PRECHCONFIG_OFFSET
+
+	/*
+	 * S5PC100:
+	 * DMC:  CS0: 166MHz
+	 *       CS1: 166MHz
+	 * S5PC110:
+	 * DMC0: CS0: 166MHz
+	 * DMC1: CS0: 200MHz
+	 *
+	 * 7.8us * 200MHz %LE %LONG1560(0x618)
+	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
+	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
+	 * 7.8us * 100MHz %LE %LONG780(0x30C),
+	 */
+	ldr	r1, =0x0000050E
+	str	r1, [r0, #0x030]			@ TIMINGAREF_OFFSET
+	ldrne	r1, =0x00000618
+	strne	r1, [r6, #0x030]			@ TIMINGAREF_OFFSET
+
+	ldr	r1, =0x14233287
+	str	r1, [r0, #0x034]			@ TIMINGROW_OFFSET
+	ldrne	r1, =0x182332c8
+	strne	r1, [r6, #0x034]			@ TIMINGROW_OFFSET
+
+	ldr	r1, =0x12130005
+	str	r1, [r0, #0x038]			@ TIMINGDATA_OFFSET
+	ldrne	r1, =0x13130005
+	strne	r1, [r6, #0x038]			@ TIMINGDATA_OFFSET
+
+	ldr	r1, =0x0E140222
+	str	r1, [r0, #0x03C]			@ TIMINGPOWER_OFFSET
+	ldrne	r1, =0x0E180222
+	strne	r1, [r6, #0x03C]			@ TIMINGPOWER_OFFSET
+
+	/* chip0 Deselect */
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 PALL */
+	ldr	r1, =0x01000000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 REFA */
+	ldr	r1, =0x05000000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+	/* chip0 REFA */
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 MRS */
+	ldr	r1, =0x00000032
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 EMRS */
+	ldr	r1, =0x00020020
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 Deselect */
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 PALL */
+	ldr	r1, =0x01100000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 REFA */
+	ldr	r1, =0x05100000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+	/* chip1 REFA */
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 MRS */
+	ldr	r1, =0x00100032
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 EMRS */
+	ldr	r1, =0x00120020
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* auto refresh on */
+	ldr	r1, =0xFF002030 | (1 << 7)
+	str	r1, [r0, #0x000]			@ CONCONTROL_OFFSET
+	strne	r1, [r6, #0x000]			@ CONCONTROL_OFFSET
+
+	/* PwrdnConfig */
+	ldr	r1, =0x00100002
+	str	r1, [r0, #0x028]			@ PWRDNCONFIG_OFFSET
+	strne	r1, [r6, #0x028]			@ PWRDNCONFIG_OFFSET
+
+	ldr	r1, =0x00212113
+	str	r1, [r0, #0x004]			@ MEMCONTROL_OFFSET
+	strne	r1, [r6, #0x004]			@ MEMCONTROL_OFFSET
+
+	/* Skip when S5PC110 */
+	bne	1f
+
+	/* Check OneDRAM access area at s5pc100 */
+	ldreq	r3, =0x38f80222
+	ldreq	r1, =0x37ffff00
+	str	r3, [r1]
+	ldr	r2, [r1]
+	cmp	r2, r3
+	beq	swap_memory
+1:
+	mov	pc, lr
+
+	.ltorg
diff --git a/u-boot/board/samsung/goni/onenand.c b/u-boot/board/samsung/goni/onenand.c
new file mode 100644
index 0000000..8d3769b
--- /dev/null
+++ b/u-boot/board/samsung/goni/onenand.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+#include <onenand_uboot.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
diff --git a/u-boot/board/samsung/smdk2400/Makefile b/u-boot/board/samsung/smdk2400/Makefile
new file mode 100644
index 0000000..0c45d02
--- /dev/null
+++ b/u-boot/board/samsung/smdk2400/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= smdk2400.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/samsung/smdk2400/config.mk b/u-boot/board/samsung/smdk2400/config.mk
new file mode 100644
index 0000000..4c27dc3
--- /dev/null
+++ b/u-boot/board/samsung/smdk2400/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SAMSUNG board with S3C2400X (ARM920T) CPU
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SAMSUNG has 1 bank of 32 MB DRAM
+#
+# 0C00'0000 to 0E00'0000
+#
+# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000
+# optionally with a ramdisk at 0c80'0000
+#
+# we load ourself to 0CF80000 (must be high enough not to be
+# overwritten by the uncompessing Linux kernel)
+#
+# download area is 0C80'0000
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0x0CF80000
diff --git a/u-boot/board/samsung/smdk2400/flash.c b/u-boot/board/samsung/smdk2400/flash.c
new file mode 100644
index 0000000..fb69c21
--- /dev/null
+++ b/u-boot/board/samsung/smdk2400/flash.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+#define FLASH_BANK_SIZE 0x1000000	/* 2 x   8 MB */
+#define MAIN_SECT_SIZE  0x40000		/* 2 x 128 kB */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT     & FLASH_VENDMASK) |
+			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = CONFIG_SYS_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase;
+
+			/* uniform sector size */
+			flashbase += MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+		printf ("2x 28F640J3A (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT) {
+		puts ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY) {
+		puts ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR) {
+		puts ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR) {
+		puts ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR) {
+		puts ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR) {
+		puts ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR) {
+		puts ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND) {
+		puts ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND) {
+		puts ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result, result1;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+			ulong bsR7, bsR7_2, bsR5, bsR5_2;
+
+			/* *addr = CMD_STATUS_RESET; */
+			*addr = CMD_ERASE_SETUP;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			do {
+				/* check timeout */
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					*addr = CMD_STATUS_RESET;
+					result = BIT_TIMEOUT;
+					break;
+				}
+
+				*addr = CMD_STATUS_READ;
+				result = *addr;
+				bsR7 = result & (1 << 7);
+				bsR7_2 = result & (1 << 23);
+			} while (!bsR7 | !bsR7_2);
+
+			*addr = CMD_STATUS_READ;
+			result1 = *addr;
+			bsR5 = result1 & (1 << 5);
+			bsR5_2 = result1 & (1 << 21);
+#ifdef SAMSUNG_FLASH_DEBUG
+			printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+			if (bsR5 != 0 && bsR5_2 != 0)
+				printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+#endif
+
+			*addr = CMD_READ_ARRAY;
+			*addr = CMD_RESUME;
+
+			if ((rc = flash_error (result)) != ERR_OK)
+				goto outahere;
+#if 0
+			printf ("ok.\n");
+		} else {		/* it was protected */
+
+			printf ("protected!\n");
+#endif
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* *addr = CMD_STATUS_RESET; */
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	do {
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			*addr = CMD_SUSPEND;
+			result = BIT_TIMEOUT;
+			break;
+		}
+
+		*addr = CMD_STATUS_READ;
+		result = *addr;
+	} while (~result & BIT_BUSY);
+
+	/* *addr = CMD_READ_ARRAY; */
+	*addr = CMD_STATUS_READ;
+	result = *addr;
+
+	rc = flash_error (result);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	*addr = CMD_READ_ARRAY;
+	*addr = CMD_RESUME;
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/u-boot/board/samsung/smdk2400/lowlevel_init.S b/u-boot/board/samsung/smdk2400/lowlevel_init.S
new file mode 100644
index 0000000..c275c07
--- /dev/null
+++ b/u-boot/board/samsung/smdk2400/lowlevel_init.S
@@ -0,0 +1,163 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung development board by
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * S3C2400 specific tweaks.
+ *
+ */
+
+/* memory controller */
+#define BWSCON 0x14000000
+#define BANKCON3 0x14000010	/* for cs8900, ethernet */
+
+/* Bank0 */
+#define B0_Tacs	0x0	/* 0 clk */
+#define B0_Tcos	0x0	/* 0 clk */
+#define B0_Tacc	0x7	/* 14 clk */
+#define B0_Tcoh	0x0	/* 0 clk */
+#define B0_Tah	0x0	/* 0 clk */
+#define B0_Tacp	0x0
+#define B0_PMC	0x0	/* normal */
+
+/* Bank1 */
+#define B1_Tacs	0x0	/* 0 clk */
+#define B1_Tcos	0x0	/* 0 clk */
+#define B1_Tacc	0x7	/* 14 clk */
+#define B1_Tcoh	0x0	/* 0 clk */
+#define B1_Tah	0x0	/* 0 clk */
+#define B1_Tacp	0x0
+#define B1_PMC	0x0	/* normal */
+
+/* Bank2 */
+#define B2_Tacs	0x0	/* 0 clk */
+#define B2_Tcos	0x0	/* 0 clk */
+#define B2_Tacc	0x7	/* 14 clk */
+#define B2_Tcoh	0x0	/* 0 clk */
+#define B2_Tah	0x0	/* 0 clk */
+#define B2_Tacp	0x0
+#define B2_PMC	0x0	/* normal */
+
+/* Bank3 - setup for the cs8900 */
+#define B3_Tacs	0x0	/* 0 clk */
+#define B3_Tcos	0x3	/* 4 clk */
+#define B3_Tacc	0x7	/* 14 clk */
+#define B3_Tcoh	0x1	/* 1 clk */
+#define B3_Tah	0x0	/* 0 clk */
+#define B3_Tacp	0x3	/* 6 clk */
+#define B3_PMC	0x0	/* normal */
+
+/* Bank4 */
+#define B4_Tacs	0x0	/* 0 clk */
+#define B4_Tcos	0x0	/* 0 clk */
+#define B4_Tacc	0x7	/* 14 clk */
+#define B4_Tcoh	0x0	/* 0 clk */
+#define B4_Tah	0x0	/* 0 clk */
+#define B4_Tacp	0x0
+#define B4_PMC	0x0	/* normal */
+
+/* Bank5 */
+#define B5_Tacs	0x0	/* 0 clk */
+#define B5_Tcos	0x0	/* 0 clk */
+#define B5_Tacc	0x7	/* 14 clk */
+#define B5_Tcoh	0x0	/* 0 clk */
+#define B5_Tah	0x0	/* 0 clk */
+#define B5_Tacp	0x0
+#define B5_PMC	0x0	/* normal */
+
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x1	/* 3clk */
+#define	B6_SCAN	0x1	/* 9 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x1	/* 3clk */
+#define	B7_SCAN	0x1	/* 9 bit */
+
+/* refresh parameter */
+#define REFEN	0x1	/* enable refresh */
+#define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
+#define Trp	0x0	/* 2 clk */
+#define Trc	0x3	/* 7 clk */
+#define Tchr	0x2	/* 3 clk */
+
+#define REFCNT	1113	/* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #52
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+	.word	0x2211d114	/* d->Ethernet, BUSWIDTH=32 */
+	.word	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
+	.word	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
+	.word	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
+	.word	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
+	.word	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
+	.word	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
+	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
+	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
+	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+	.word	0x30	/* MRSR6, CL=3clk */
+	.word	0x30	/* MRSR7 */
diff --git a/u-boot/board/samsung/smdk2400/smdk2400.c b/u-boot/board/samsung/smdk2400/smdk2400.c
new file mode 100644
index 0000000..895bd77
--- /dev/null
+++ b/u-boot/board/samsung/smdk2400/smdk2400.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+int mdm_init (bd_t *);
+extern void disable_putc(void);
+extern void enable_putc(void);
+extern int hwflow_onoff(int);
+extern int do_mdm_init; /* defined in common/main.c */
+#endif /* CONFIG_MODEM_SUPPORT */
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	struct s3c24x0_clock_power * const clk_power =
+					s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* change the clock to be 50 MHz 1:1:1 */
+	clk_power->mpllcon = 0x5c042;
+	clk_power->clkdivn = 0;
+	/* set up the I/O ports */
+	gpio->pacon = 0x3ffff;
+	gpio->pbcon = 0xaaaaaaaa;
+	gpio->pbup = 0xffff;
+	gpio->pecon = 0x0;
+	gpio->peup = 0x0;
+#ifdef CONFIG_HWFLOW
+	/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
+	/*   10,   10,   00,   00,    10,   00,    10 */
+	gpio->pfcon = 0xa22;
+	/* Disable pull-up on Rx, Tx, CTS and RTS pins */
+	gpio->pfup = 0x35;
+#else
+	/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
+	/*   00,   00,   00,   00,    10,   00,    10 */
+	gpio->pfcon = 0x22;
+	/* Disable pull-up on Rx and Tx pins */
+	gpio->pfup = 0x5;
+#endif	/* CONFIG_HWFLOW */
+	gpio->pgcon = 0x0;
+	gpio->pgup = 0x0;
+	gpio->opencr = 0x0;
+
+	/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
+	gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x0C000100;
+
+#ifdef CONFIG_MODEM_SUPPORT
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		do_mdm_init = 1;
+	}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	int rc;
+	if (1) {	/* check for button push here, now just return 1 */
+		rc = 1;
+	}
+
+	return rc;
+}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/samsung/smdk2410/Makefile b/u-boot/board/samsung/smdk2410/Makefile
new file mode 100644
index 0000000..bda8898
--- /dev/null
+++ b/u-boot/board/samsung/smdk2410/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= smdk2410.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/samsung/smdk2410/config.mk b/u-boot/board/samsung/smdk2410/config.mk
new file mode 100644
index 0000000..c8d1b1f
--- /dev/null
+++ b/u-boot/board/samsung/smdk2410/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SMDK2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0x33F80000
diff --git a/u-boot/board/samsung/smdk2410/flash.c b/u-boot/board/samsung/smdk2410/flash.c
new file mode 100644
index 0000000..132d752
--- /dev/null
+++ b/u-boot/board/samsung/smdk2410/flash.c
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+
+#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x000000F0
+#define CMD_UNLOCK1		0x000000AA
+#define CMD_UNLOCK2		0x00000055
+#define CMD_ERASE_SETUP		0x00000080
+#define CMD_ERASE_CONFIRM	0x00000030
+#define CMD_PROGRAM		0x000000A0
+#define CMD_UNLOCK_BYPASS	0x00000020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE		0x00000080
+#define BIT_RDY_MASK		0x00000080
+#define BIT_PROGRAM_ERROR	0x00000020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+			flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 3) {
+				/* 1st one is 16 KB */
+				if (j == 0) {
+					flash_info[i].start[j] =
+						flashbase + 0;
+				}
+
+				/* 2nd and 3rd are both 8 KB */
+				if ((j == 1) || (j == 2)) {
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + (j -
+								      1) *
+						0x2000;
+				}
+
+				/* 4th 32 KB */
+				if (j == 3) {
+					flash_info[i].start[j] =
+						flashbase + 0x8000;
+				}
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 3) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV400B & FLASH_TYPEMASK):
+		printf ("1x Amd29LV400BB (4Mbit)\n");
+		break;
+	case (AMD_ID_LV800B & FLASH_TYPEMASK):
+		printf ("1x Amd29LV800BB (8Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ushort result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip = TMO;
+					break;
+				}
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip = READY;
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip = ERR;
+
+			} while (!chip);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest;
+	ushort result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			chip = ERR | TMO;
+			break;
+		}
+		if (!chip && ((result & 0x80) == (data & 0x80)))
+			chip = READY;
+
+		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip = READY;
+			else
+				chip = ERR;
+		}
+
+	} while (!chip);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	int l;
+	int i, rc;
+	ushort data;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_hword (info, wp, data);
+}
diff --git a/u-boot/board/samsung/smdk2410/lowlevel_init.S b/u-boot/board/samsung/smdk2410/lowlevel_init.S
new file mode 100644
index 0000000..a2bf570
--- /dev/null
+++ b/u-boot/board/samsung/smdk2410/lowlevel_init.S
@@ -0,0 +1,167 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON	0x48000000
+
+/* BWSCON */
+#define DW8			(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
+
+#define B1_BWSCON		(DW32)
+#define B2_BWSCON		(DW16)
+#define B3_BWSCON		(DW16 + WAIT + UBLB)
+#define B4_BWSCON		(DW16)
+#define B5_BWSCON		(DW16)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
+
+/* BANK0CON */
+#define B0_Tacs			0x0	/*  0clk */
+#define B0_Tcos			0x0	/*  0clk */
+#define B0_Tacc			0x7	/* 14clk */
+#define B0_Tcoh			0x0	/*  0clk */
+#define B0_Tah			0x0	/*  0clk */
+#define B0_Tacp			0x0
+#define B0_PMC			0x0	/* normal */
+
+/* BANK1CON */
+#define B1_Tacs			0x0	/*  0clk */
+#define B1_Tcos			0x0	/*  0clk */
+#define B1_Tacc			0x7	/* 14clk */
+#define B1_Tcoh			0x0	/*  0clk */
+#define B1_Tah			0x0	/*  0clk */
+#define B1_Tacp			0x0
+#define B1_PMC			0x0
+
+#define B2_Tacs			0x0
+#define B2_Tcos			0x0
+#define B2_Tacc			0x7
+#define B2_Tcoh			0x0
+#define B2_Tah			0x0
+#define B2_Tacp			0x0
+#define B2_PMC			0x0
+
+#define B3_Tacs			0x0	/*  0clk */
+#define B3_Tcos			0x3	/*  4clk */
+#define B3_Tacc			0x7	/* 14clk */
+#define B3_Tcoh			0x1	/*  1clk */
+#define B3_Tah			0x0	/*  0clk */
+#define B3_Tacp			0x3     /*  6clk */
+#define B3_PMC			0x0	/* normal */
+
+#define B4_Tacs			0x0	/*  0clk */
+#define B4_Tcos			0x0	/*  0clk */
+#define B4_Tacc			0x7	/* 14clk */
+#define B4_Tcoh			0x0	/*  0clk */
+#define B4_Tah			0x0	/*  0clk */
+#define B4_Tacp			0x0
+#define B4_PMC			0x0	/* normal */
+
+#define B5_Tacs			0x0	/*  0clk */
+#define B5_Tcos			0x0	/*  0clk */
+#define B5_Tacc			0x7	/* 14clk */
+#define B5_Tcoh			0x0	/*  0clk */
+#define B5_Tah			0x0	/*  0clk */
+#define B5_Tacp			0x0
+#define B5_PMC			0x0	/* normal */
+
+#define B6_MT			0x3	/* SDRAM */
+#define B6_Trcd			0x1
+#define B6_SCAN			0x1	/* 9bit */
+
+#define B7_MT			0x3	/* SDRAM */
+#define B7_Trcd			0x1	/* 3clk */
+#define B7_SCAN			0x1	/* 9bit */
+
+/* REFRESH parameter */
+#define REFEN			0x1	/* Refresh enable */
+#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x0	/* 2clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr			0x2	/* 3clk */
+#define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #13*4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32
+    .word 0x30
+    .word 0x30
diff --git a/u-boot/board/samsung/smdk2410/smdk2410.c b/u-boot/board/samsung/smdk2410/smdk2410.c
new file mode 100644
index 0000000..76a24bb
--- /dev/null
+++ b/u-boot/board/samsung/smdk2410/smdk2410.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	struct s3c24x0_clock_power * const clk_power =
+					s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	clk_power->locktime = 0xFFFFFF;
+
+	/* configure MPLL */
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (4000);
+
+	/* configure UPLL */
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (8000);
+
+	/* set up the I/O ports */
+	gpio->gpacon = 0x007FFFFF;
+	gpio->gpbcon = 0x00044555;
+	gpio->gpbup = 0x000007FF;
+	gpio->gpccon = 0xAAAAAAAA;
+	gpio->gpcup = 0x0000FFFF;
+	gpio->gpdcon = 0xAAAAAAAA;
+	gpio->gpdup = 0x0000FFFF;
+	gpio->gpecon = 0xAAAAAAAA;
+	gpio->gpeup = 0x0000FFFF;
+	gpio->gpfcon = 0x000055AA;
+	gpio->gpfup = 0x000000FF;
+	gpio->gpgcon = 0xFF95FFBA;
+	gpio->gpgup = 0x0000FFFF;
+	gpio->gphcon = 0x002AFAAA;
+	gpio->gphup = 0x000007FF;
+
+	/* arch number of SMDK2410-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x30000100;
+
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/samsung/smdk6400/.gitignore b/u-boot/board/samsung/smdk6400/.gitignore
new file mode 100644
index 0000000..25ab492
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/.gitignore
@@ -0,0 +1,5 @@
+#
+# Generated files
+#
+
+/config.tmp
diff --git a/u-boot/board/samsung/smdk6400/Makefile b/u-boot/board/samsung/smdk6400/Makefile
new file mode 100644
index 0000000..40bf57e
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= smdk6400.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/samsung/smdk6400/config.mk b/u-boot/board/samsung/smdk6400/config.mk
new file mode 100644
index 0000000..90cbcf2
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+
+# On SMDK6400 we use the 64 MB SDRAM bank at
+#
+# 0x50000000 to 0x58000000
+#
+# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
+#
+# we load ourselves to 0x57e00000 without MMU
+# with MMU, load address is changed to 0xc7e00000
+#
+# download area is 0x5000c000
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef CONFIG_NAND_SPL
+CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
+else
+CONFIG_SYS_TEXT_BASE = 0
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot-nand.lds
diff --git a/u-boot/board/samsung/smdk6400/lowlevel_init.S b/u-boot/board/samsung/smdk6400/lowlevel_init.S
new file mode 100644
index 0000000..f7ce176
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/lowlevel_init.S
@@ -0,0 +1,323 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/arch/s3c6400.h>
+
+#ifdef CONFIG_SERIAL1
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
+#elif defined(CONFIG_SERIAL2)
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
+#else
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
+#endif
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r12, lr
+
+	/* LED on only #8 */
+	ldr	r0, =ELFIN_GPIO_BASE
+	ldr	r1, =0x55540000
+	str	r1, [r0, #GPNCON_OFFSET]
+
+	ldr	r1, =0x55555555
+	str	r1, [r0, #GPNPUD_OFFSET]
+
+	ldr	r1, =0xf000
+	str	r1, [r0, #GPNDAT_OFFSET]
+
+	/* Disable Watchdog */
+	ldr	r0, =0x7e000000		@0x7e004000
+	orr	r0, r0, #0x4000
+	mov	r1, #0
+	str	r1, [r0]
+
+	/* External interrupt pending clear */
+	ldr	r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET)	/*EINTPEND*/
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	ldr	r0, =ELFIN_VIC0_BASE_ADDR	@0x71200000
+	ldr	r1, =ELFIN_VIC1_BASE_ADDR	@0x71300000
+
+	/* Disable all interrupts (VIC0 and VIC1) */
+	mvn	r3, #0x0
+	str	r3, [r0, #oINTMSK]
+	str	r3, [r1, #oINTMSK]
+
+	/* Set all interrupts as IRQ */
+	mov	r3, #0x0
+	str	r3, [r0, #oINTMOD]
+	str	r3, [r1, #oINTMOD]
+
+	/* Pending Interrupt Clear */
+	mov	r3, #0x0
+	str	r3, [r0, #oVECTADDR]
+	str	r3, [r1, #oVECTADDR]
+
+	/* init system clock */
+	bl system_clock_init
+
+#ifndef CONFIG_NAND_SPL
+	/* for UART */
+	bl uart_asm_init
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+	/* simple init for NAND */
+	bl nand_asm_init
+#endif
+
+	/* Memory subsystem address 0x7e00f120 */
+	ldr	r0, =ELFIN_MEM_SYS_CFG
+
+	/* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
+	mov	r1, #S3C64XX_MEM_SYS_CFG_NAND
+	str	r1, [r0]
+
+	bl	mem_ctrl_asm_init
+
+/* Wakeup support. Don't know if it's going to be used, untested. */
+	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+	ldr	r1, [r0]
+	bic	r1, r1, #0xfffffff7
+	cmp	r1, #0x8
+	beq	wakeup_reset
+
+1:
+	mov	lr, r12
+	mov	pc, lr
+
+wakeup_reset:
+
+	/* Clear wakeup status register */
+	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* LED test */
+	ldr	r0, =ELFIN_GPIO_BASE
+	ldr	r1, =0x3000
+	str	r1, [r0, #GPNDAT_OFFSET]
+
+	/* Load return address and jump to kernel */
+	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+	/* r1 = physical address of s3c6400_cpu_resume function */
+	ldr	r1, [r0]
+	/* Jump to kernel (sleep-s3c6400.S) */
+	mov	pc, r1
+	nop
+	nop
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r0, =ELFIN_CLOCK_POWER_BASE	/* 0x7e00f000 */
+
+#ifdef CONFIG_SYNC_MODE
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	mov	r2, #0x40
+	orr	r1, r1, r2
+	str	r1, [r0, #OTHERS_OFFSET]
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	ldr	r2, =0x80
+	orr	r1, r1, r2
+	str	r1, [r0, #OTHERS_OFFSET]
+
+check_syncack:
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r2, =0xf00
+	and	r1, r1, r2
+	cmp	r1, #0xf00
+	bne	check_syncack
+#else	/* ASYNC Mode */
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/*
+	 * This was unconditional in original Samsung sources, but it doesn't
+	 * seem to make much sense on S3C6400.
+	 */
+#ifndef CONFIG_S3C6400
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	bic	r1, r1, #0xC0
+	orr	r1, r1, #0x40
+	str	r1, [r0, #OTHERS_OFFSET]
+
+wait_for_async:
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	and	r1, r1, #0xf00
+	cmp	r1, #0x0
+	bne	wait_for_async
+#endif
+
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	bic	r1, r1, #0x40
+	str	r1, [r0, #OTHERS_OFFSET]
+#endif
+
+	mov	r1, #0xff00
+	orr	r1, r1, #0xff
+	str	r1, [r0, #APLL_LOCK_OFFSET]
+	str	r1, [r0, #MPLL_LOCK_OFFSET]
+
+	/* Set Clock Divider */
+	ldr	r1, [r0, #CLK_DIV0_OFFSET]
+	bic	r1, r1, #0x30000
+	bic	r1, r1, #0xff00
+	bic	r1, r1, #0xff
+	ldr	r2, =CLK_DIV_VAL
+	orr	r1, r1, r2
+	str	r1, [r0, #CLK_DIV0_OFFSET]
+
+	ldr	r1, =APLL_VAL
+	str	r1, [r0, #APLL_CON_OFFSET]
+	ldr	r1, =MPLL_VAL
+	str	r1, [r0, #MPLL_CON_OFFSET]
+
+	/* FOUT of EPLL is 96MHz */
+	ldr	r1, =0x200203
+	str	r1, [r0, #EPLL_CON0_OFFSET]
+	ldr	r1, =0x0
+	str	r1, [r0, #EPLL_CON1_OFFSET]
+
+	/* APLL, MPLL, EPLL select to Fout */
+	ldr	r1, [r0, #CLK_SRC_OFFSET]
+	orr	r1, r1, #0x7
+	str	r1, [r0, #CLK_SRC_OFFSET]
+
+	/* wait at least 200us to stablize all clock */
+	mov	r1, #0x10000
+1:	subs	r1, r1, #1
+	bne	1b
+
+	/* Synchronization for VIC port */
+#if defined(CONFIG_SYNC_MODE)
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	orr	r1, r1, #0x20
+	str	r1, [r0, #OTHERS_OFFSET]
+#elif !defined(CONFIG_S3C6400)
+	/* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	bic	r1, r1, #0x20
+	str	r1, [r0, #OTHERS_OFFSET]
+#endif
+	mov	pc, lr
+
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	/* set GPIO to enable UART */
+	ldr	r0, =ELFIN_GPIO_BASE
+	ldr	r1, =0x220022
+	str	r1, [r0, #GPACON_OFFSET]
+	mov	pc, lr
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+/*
+ * NAND Interface init for SMDK6400
+ */
+nand_asm_init:
+	ldr	r0, =ELFIN_NAND_BASE
+	ldr	r1, [r0, #NFCONF_OFFSET]
+	orr	r1, r1, #0x70
+	orr	r1, r1, #0x7700
+	str	r1, [r0, #NFCONF_OFFSET]
+
+	ldr	r1, [r0, #NFCONT_OFFSET]
+	orr	r1, r1, #0x07
+	str	r1, [r0, #NFCONT_OFFSET]
+
+	mov	pc, lr
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+/*
+ * MMU Table for SMDK6400
+ */
+
+	/* form a first-level section entry */
+.macro FL_SECTION_ENTRY base,ap,d,c,b
+	.word (\base << 20) | (\ap << 10) | \
+	      (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
+.endm
+
+.section .mmudata, "a"
+	.align 14
+	/* the following alignment creates the mmu table at address 0x4000. */
+	.globl mmu_table
+mmu_table:
+	.set __base, 0
+	/* 1:1 mapping for debugging */
+	.rept 0xA00
+	FL_SECTION_ENTRY __base, 3, 0, 0, 0
+	.set __base, __base + 1
+	.endr
+
+	/* access is not allowed. */
+	.rept 0xC00 - 0xA00
+	.word 0x00000000
+	.endr
+
+	/* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
+	.set __base, 0x500
+	.rept 0xC80 - 0xC00
+	FL_SECTION_ENTRY __base, 3, 0, 1, 1
+	.set __base, __base + 1
+	.endr
+
+	/* access is not allowed. */
+	.rept 0x1000 - 0xc80
+	.word 0x00000000
+	.endr
+#endif
diff --git a/u-boot/board/samsung/smdk6400/smdk6400.c b/u-boot/board/samsung/smdk6400/smdk6400.c
new file mode 100644
index 0000000..35aa40b
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/smdk6400.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/s3c6400.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+#define CS8900_Tacs	0x0	/* 0clk		address set-up		*/
+#define CS8900_Tcos	0x4	/* 4clk		chip selection set-up	*/
+#define CS8900_Tacc	0xE	/* 14clk	access cycle		*/
+#define CS8900_Tcoh	0x1	/* 1clk		chip selection hold	*/
+#define CS8900_Tah	0x4	/* 4clk		address holding time	*/
+#define CS8900_Tacp	0x6	/* 6clk		page mode access cycle	*/
+#define CS8900_PMC	0x0	/* normal(1data)page mode configuration	*/
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b"
+			  : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+static void cs8900_pre_init(void)
+{
+	SROM_BW_REG &= ~(0xf << 4);
+	SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
+	SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
+			(CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
+			(CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
+}
+
+int board_init(void)
+{
+	cs8900_pre_init();
+
+	/* NOR-flash in SROM0 */
+
+	/* Enable WAIT */
+	SROM_BW_REG |= 4 | 8 | 1;
+
+	gd->bd->bi_arch_number = MACH_TYPE;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board:   SMDK6400\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+ulong virt_to_phy_smdk6400(ulong addr)
+{
+	if ((0xc0000000 <= addr) && (addr < 0xc8000000))
+		return addr - 0xc0000000 + 0x50000000;
+	else
+		printf("do not support this address : %08lx\n", addr);
+
+	return addr;
+}
+#endif
+
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_16BIT;
+		info->chipwidth = FLASH_CFI_BY16;
+		info->interface = FLASH_CFI_X16;
+		return 1;
+	} else
+		return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/samsung/smdk6400/smdk6400_nand_spl.c b/u-boot/board/samsung/smdk6400/smdk6400_nand_spl.c
new file mode 100644
index 0000000..a023284
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/smdk6400_nand_spl.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void board_init_f(unsigned long bootflag)
+{
+	relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+			CONFIG_SYS_TEXT_BASE);
+}
diff --git a/u-boot/board/samsung/smdk6400/u-boot-nand.lds b/u-boot/board/samsung/smdk6400/u-boot-nand.lds
new file mode 100644
index 0000000..29a4f61
--- /dev/null
+++ b/u-boot/board/samsung/smdk6400/u-boot-nand.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  arch/arm/cpu/arm1176/start.o	(.text)
+	  arch/arm/cpu/arm1176/s3c64xx/cpu_init.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.mmudata : { *(.mmudata) }
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/u-boot/board/samsung/smdkc100/Makefile b/u-boot/board/samsung/smdkc100/Makefile
new file mode 100644
index 0000000..61d4b25
--- /dev/null
+++ b/u-boot/board/samsung/smdkc100/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= smdkc100.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/samsung/smdkc100/config.mk b/u-boot/board/samsung/smdkc100/config.mk
new file mode 100644
index 0000000..3a08bb1
--- /dev/null
+++ b/u-boot/board/samsung/smdkc100/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2008 # Samsung Elecgtronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x48000000 (128MiB)
+#
+CONFIG_SYS_TEXT_BASE = 0x34800000
diff --git a/u-boot/board/samsung/smdkc100/lowlevel_init.S b/u-boot/board/samsung/smdkc100/lowlevel_init.S
new file mode 100644
index 0000000..6d18835
--- /dev/null
+++ b/u-boot/board/samsung/smdkc100/lowlevel_init.S
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r9, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r8, =S5PC100_GPIO_BASE
+
+	/* Disable Watchdog */
+	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
+	orr	r0, r0, #0x0
+	str	r5, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+	/* setting SRAM */
+	ldr	r0, =S5PC100_SROMC_BASE
+	ldr	r1, =0x9
+	str	r1, [r0]
+#endif
+
+	/* S5PC100 has 3 groups of interrupt sources */
+	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
+	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
+	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@INTENCLEAR
+	str	r3, [r1, #0x14]				@INTENCLEAR
+	str	r3, [r2, #0x14]				@INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@INTSELECT
+	str	r5, [r1, #0xc]				@INTSELECT
+	str	r5, [r2, #0xc]				@INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@INTADDRESS
+	str	r5, [r1, #0xf00]			@INTADDRESS
+	str	r5, [r2, #0xf00]			@INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+	/* for UART */
+	bl uart_asm_init
+
+	/* for TZPC */
+	bl tzpc_asm_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+	/* init system clock */
+	bl	system_clock_init
+
+	bl	mem_ctrl_asm_init
+
+	/* Wakeup support. Don't know if it's going to be used, untested. */
+	ldr	r0, =S5PC100_RST_STAT
+	ldr	r1, [r0]
+	bic	r1, r1, #0xfffffff7
+	cmp	r1, #0x8
+	beq	wakeup_reset
+#endif
+
+1:
+	mov	lr, r9
+	mov	pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+	/* Clear wakeup status register */
+	ldr	r0, =S5PC100_WAKEUP_STAT
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* Load return address and jump to kernel */
+	ldr	r0, =S5PC100_INFORM0
+
+	/* r1 = physical address of s5pc100_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel (sleep.S) */
+	mov	pc, r1
+	nop
+	nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Clock divider */
+	ldr	r1, =0x00011110
+	str	r1, [r8, #0x304]
+	ldr	r1, =0x1
+	str	r1, [r8, #0x308]
+	ldr	r1, =0x00011301
+	str	r1, [r8, #0x300]
+
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r8, #0x000]		@ APLL_LOCK
+	str	r1, [r8, #0x004]		@ MPLL_LOCK
+	str	r1, [r8, #0x008]		@ EPLL_LOCK
+	str	r1, [r8, #0x00C]		@ HPLL_LOCK
+
+	/* APLL_CON */
+	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+	str	r1, [r8, #0x100]
+	/* MPLL_CON */
+	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+	str	r1, [r8, #0x104]
+	/* EPLL_CON */
+	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+	str	r1, [r8, #0x108]
+	/* HPLL_CON */
+	ldr	r1, =0x80600603
+	str	r1, [r8, #0x10C]
+
+	/* Set Source Clock */
+	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
+	str	r1, [r8, #0x200]		@ CLK_SRC0
+
+	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
+	str	r1, [r8, #0x204]		@ CLK_SRC1
+
+	ldr	r1, =0x9000			@ ARMCLK/4
+	str	r1, [r8, #0x400]		@ CLK_OUT
+
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ GPA0_CON
+	ldr	r1, =0x00022222
+	str	r1, [r0, #0x20]			@ GPA1_CON
+
+	mov	pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+	ldr	r0, =0xE3800000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+
+	ldr	r0, =0xE2800000
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+	str	r1, [r0, #0x81C]
+
+	ldr	r0, =0xE2900000
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+
+	mov	pc, lr
+#endif
diff --git a/u-boot/board/samsung/smdkc100/mem_setup.S b/u-boot/board/samsung/smdkc100/mem_setup.S
new file mode 100644
index 0000000..94a701d
--- /dev/null
+++ b/u-boot/board/samsung/smdkc100/mem_setup.S
@@ -0,0 +1,197 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
+ *
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Inki Dae <inki.dae@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	ldr	r6, =S5PC100_DMC_BASE			@ 0xE6000000
+
+	/* DLL parameter setting */
+	ldr	r1, =0x50101000
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+	ldr	r1, =0xf4
+	str	r1, [r6, #0x01C]			@ PHYCONTROL1
+	ldr	r1, =0x0
+	str	r1, [r6, #0x020]			@ PHYCONTROL2
+
+	/* DLL on */
+	ldr	r1, =0x50101002
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* DLL start */
+	ldr	r1, =0x50101003
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* Force value locking for DLL off */
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* DLL off */
+	ldr	r1, =0x50101001
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* auto refresh off */
+	ldr	r1, =0xff001010
+	str	r1, [r6, #0x000]			@ CONCONTROL
+
+	/*
+	 * Burst Length 4, 2 chips, 32-bit, LPDDR
+	 * OFF: dynamic self refresh, force precharge, dynamic power down off
+	 */
+	ldr	r1, =0x00212100
+	str	r1, [r6, #0x004]			@ MEMCONTROL
+
+	/*
+	 * Note:
+	 * If Bank0 has OneDRAM we place it at 0x2800'0000
+	 * So finally Bank1 should address start at at 0x2000'0000
+	 */
+	mov	r4, #0x0
+
+swap_memory:
+	/*
+	 * Bank0
+	 * 0x30 -> 0x30000000
+	 * 0xf8 -> 0x37FFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	ldr	r1, =0x30f80222
+	/* if r4 is 1, swap the bank */
+	cmp	r4, #0x1
+	orreq	r1, r1, #0x08000000
+	str	r1, [r6, #0x008]			@ MEMCONFIG0
+
+	/*
+	 * Bank1
+	 * 0x38 -> 0x38000000
+	 * 0xf8 -> 0x3fFFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	ldr	r1, =0x38f80222
+	/* if r4 is 1, swap the bank */
+	cmp	r4, #0x1
+	biceq	r1, r1, #0x08000000
+	str	r1, [r6, #0x00c]			@ MEMCONFIG1
+
+	ldr	r1, =0x20000000
+	str	r1, [r6, #0x014]			@ PRECHCONFIG
+
+	/*
+	 * FIXME: Please verify these values
+	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
+	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
+	 * 7.8us * 100MHz %LE %LONG780(0x30C),
+	 * 7.8us * 20MHz  %LE %LONG156(0x9C),
+	 * 7.8us * 10MHz  %LE %LONG78(0x4E)
+	 */
+	ldr	r1, =0x0000050e
+	str	r1, [r6, #0x030]			@ TIMINGAREF
+
+	/* 166 MHz */
+	ldr	r1, =0x0c233287
+	str	r1, [r6, #0x034]			@ TIMINGROW
+
+	/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+	ldr	r1, =0x32330303
+	str	r1, [r6, #0x038]			@ TIMINGDATA
+
+	/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
+	ldr	r1, =0x04141433
+	str	r1, [r6, #0x03C]			@ TIMINGPOWER
+
+	/* chip0 Deselect */
+	ldr	r1, =0x07000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 PALL */
+	ldr	r1, =0x01000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 REFA */
+	ldr	r1, =0x05000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+	/* chip0 REFA */
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+	ldr	r1, =0x00000032
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 Deselect */
+	ldr	r1, =0x07100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 PALL */
+	ldr	r1, =0x01100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 REFA */
+	ldr	r1, =0x05100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+	/* chip1 REFA */
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+	ldr	r1, =0x00100032
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* auto refresh on */
+	ldr	r1, =0xff002030
+	str	r1, [r6, #0x000]			@ CONCONTROL
+
+	/* PwrdnConfig */
+	ldr	r1, =0x00100002
+	str	r1, [r6, #0x028]			@ PWRDNCONFIG
+
+	/* BL%LE %LONG */
+	ldr	r1, =0xff212100
+	str	r1, [r6, #0x004]			@ MEMCONTROL
+
+
+	/* Try to test memory area */
+	cmp	r4, #0x1
+	beq	1f
+
+	mov	r4, #0x1
+	ldr	r1, =0x37ffff00
+	str	r4, [r1]
+	str	r4, [r1, #0x4]				@ dummy write
+	ldr	r0, [r1]
+	cmp	r0, r4
+	bne	swap_memory
+
+1:
+	mov	pc, lr
+
+	.ltorg
diff --git a/u-boot/board/samsung/smdkc100/onenand.c b/u-boot/board/samsung/smdkc100/onenand.c
new file mode 100644
index 0000000..501855e
--- /dev/null
+++ b/u-boot/board/samsung/smdkc100/onenand.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct s5pc100_clock *clk =
+			(struct s5pc100_clock *)samsung_get_base_clock();
+	struct samsung_onenand *onenand;
+	int value;
+
+	this->base = (void *)S5PC100_ONENAND_BASE;
+	onenand = (struct samsung_onenand *)this->base;
+
+	/* D0 Domain memory clock gating */
+	value = readl(&clk->gate_d01);
+	value &= ~(1 << 2);		/* CLK_ONENANDC */
+	value |= (1 << 2);
+	writel(value, &clk->gate_d01);
+
+	value = readl(&clk->src0);
+	value &= ~(1 << 24);		/* MUX_1nand: 0 from HCLKD0 */
+	value &= ~(1 << 20);		/* MUX_HREF: 0 from FIN_27M */
+	writel(value, &clk->src0);
+
+	value = readl(&clk->div1);
+	value &= ~(3 << 16);		/* PCLKD1_RATIO */
+	value |= (1 << 16);
+	writel(value, &clk->div1);
+
+	writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+	while (!(readl(&onenand->int_err_stat) & RST_CMP))
+		continue;
+
+	writel(RST_CMP, &onenand->int_err_ack);
+
+	/*
+	 * Access_Clock [2:0]
+	 * 166 MHz, 134 Mhz : 3
+	 * 100 Mhz, 60 Mhz  : 2
+	 */
+	writel(0x3, &onenand->acc_clock);
+
+	writel(INT_ERR_ALL, &onenand->int_err_mask);
+	writel(1 << 0, &onenand->int_pin_en);	/* Enable */
+
+	value = readl(&onenand->int_err_mask);
+	value &= ~RDY_ACT;
+	writel(value, &onenand->int_err_mask);
+
+	s3c_onenand_init(mtd);
+}
diff --git a/u-boot/board/samsung/smdkc100/smdkc100.c b/u-boot/board/samsung/smdkc100/smdkc100.c
new file mode 100644
index 0000000..d3189f6
--- /dev/null
+++ b/u-boot/board/samsung/smdkc100/smdkc100.c
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/smc.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+	u32 smc_bw_conf, smc_bc_conf;
+
+	struct s5pc100_gpio *const gpio =
+		(struct s5pc100_gpio *)samsung_get_base_gpio();
+
+	/* gpio configuration GPK0CON */
+	gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+
+	/* Ethernet needs bus width of 16 bits */
+	smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+	smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
+			| SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+			| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+	/* Select and configure the SROMC bank */
+	s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
+int board_init(void)
+{
+	smc9115_pre_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board:\tSMDKC100\n");
+	return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/samsung/universal_c210/Makefile b/u-boot/board/samsung/universal_c210/Makefile
new file mode 100644
index 0000000..0200220
--- /dev/null
+++ b/u-boot/board/samsung/universal_c210/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2010 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= universal.o onenand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/samsung/universal_c210/lowlevel_init.S b/u-boot/board/samsung/universal_c210/lowlevel_init.S
new file mode 100644
index 0000000..67635bb
--- /dev/null
+++ b/u-boot/board/samsung/universal_c210/lowlevel_init.S
@@ -0,0 +1,395 @@
+/*
+ * Lowlevel setup for universal board based on S5PC210
+ *
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r11, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r7, =S5PC210_GPIO_PART1_BASE
+	ldr	r6, =S5PC210_GPIO_PART2_BASE
+
+	/* System Timer */
+	ldr	r0, =S5PC210_SYSTIMER_BASE
+	ldr	r1, =0x5000
+	str	r1, [r0, #0x0]
+	ldr	r1, =0xffffffff
+	str	r1, [r0, #0x8]
+	ldr	r1, =0x49
+	str	r1, [r0, #0x4]
+
+	/* PMIC manual reset */
+	/* nPOWER: XEINT_23: GPX2[7] */
+	add	r0, r6, #0xC40			@ S5PC210_GPIO_X2_OFFSET
+	ldr	r1, [r0, #0x0]
+	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
+	orr	r1, r1, #(0x1 << 28)		@ Output
+	str	r1, [r0, #0x0]
+
+	ldr	r1, [r0, #0x4]
+	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
+	str	r1, [r0, #0x4]
+
+	/* init system clock */
+	bl	system_clock_init
+
+	/* Disable Watchdog */
+	ldr	r0, =S5PC210_WATCHDOG_BASE		@0x10060000
+	str	r5, [r0]
+
+	/* UART */
+	bl	uart_asm_init
+
+	/* PMU init */
+	bl	system_power_init
+
+	bl	tzpc_init
+
+	mov	lr, r11
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	/*
+	 * setup UART0-UART4 GPIOs (part1)
+	 * GPA1CON[3] = I2C_3_SCL (3)
+	 * GPA1CON[2] = I2C_3_SDA (3)
+	 */
+	mov	r0, r7
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x00]			@ S5PC210_GPIO_A0_OFFSET
+	ldr	r1, =0x00223322
+	str	r1, [r0, #0x20]			@ S5PC210_GPIO_A1_OFFSET
+
+	/* UART_SEL GPY4[7] (part2) at S5PC210 */
+	add	r0, r6, #0x1A0			@ S5PC210_GPIO_Y4_OFFSET
+	ldr	r1, [r0, #0x0]
+	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
+	orr	r1, r1, #(0x1 << 28)
+	str	r1, [r0, #0x0]
+
+	ldr	r1, [r0, #0x8]
+	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
+	orr	r1, r1, #(0x3 << 14)		@ Pull-up enabled
+	str	r1, [r0, #0x8]
+
+	ldr	r1, [r0, #0x4]
+	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
+	str	r1, [r0, #0x4]
+
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+system_clock_init:
+	ldr	r0, =S5PC210_CLOCK_BASE
+
+	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
+	ldr	r1, =0x0101
+	ldr	r2, =0x14200			@ CLK_SRC_CPU
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+1:	subs	r1, r1, #1
+	bne	1b
+
+	/*
+	 * CLK_SRC_TOP0
+	 * MUX_ONENAND_SEL[28]	0: DOUT133, 1: DOUT166
+	 * MUX_VPLL_SEL[8]	0: FINPLL,  1: FOUTVPLL
+	 * MUX_EPLL_SEL[4]	0: FINPLL,  1: FOUTEPLL
+	 */
+	ldr	r1, =0x10000110
+	ldr	r2, =0x0C210			@ CLK_SRC_TOP
+	str	r1, [r0, r2]
+
+	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+	ldr	r1, =0x0066666
+	ldr	r2, =0x0C240			@ CLK_SRC_FSYS
+	str	r1, [r0, r2]
+	/* UART[0:5], PWM: SCLKMPLL(6) */
+	ldr	r1, =0x6666666
+	ldr	r2, =0x0C250			@ CLK_SRC_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
+	ldr	r1, =0x0133730
+	ldr	r2, =0x14500			@ CLK_DIV_CPU0
+	str	r1, [r0, r2]
+	/* CPU1: COPY, HPM */
+	ldr	r1, =0x03
+	ldr	r2, =0x14504			@ CLK_DIV_CPU1
+	str	r1, [r0, r2]
+	/* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
+	ldr	r1, =0x13111113
+	ldr	r2, =0x10500			@ CLK_DIV_DMC0
+	str	r1, [r0, r2]
+	/* DMC1: PWI, DVSEM, DPM */
+	ldr	r1, =0x01010100
+	ldr	r2, =0x10504			@ CLK_DIV_DMC1
+	str	r1, [r0, r2]
+	/* LEFTBUS: GDL, GPL */
+	ldr	r1, =0x13
+	ldr	r2, =0x04500			@ CLK_DIV_LEFTBUS
+	str	r1, [r0, r2]
+	/* RIGHHTBUS: GDR, GPR */
+	ldr	r1, =0x13
+	ldr	r2, =0x08500			@ CLK_DIV_RIGHTBUS
+	str	r1, [r0, r2]
+	/*
+	 * CLK_DIV_TOP
+	 * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
+	 * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
+	 */
+	ldr	r1, =0x00005473
+	ldr	r2, =0x0C510			@ CLK_DIV_TOP
+	str	r1, [r0, r2]
+	/* MMC[0:1] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C544			@ CLK_DIV_FSYS1
+	str	r1, [r0, r2]
+	/* MMC[2:3] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
+	str	r1, [r0, r2]
+	/* MMC4 */
+	ldr	r1, =0x000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C54C			@ CLK_DIV_FSYS3
+	str	r1, [r0, r2]
+	/* UART[0:5] */
+	ldr	r1, =0x774777
+	ldr	r2, =0x0C550			@ CLK_DIV_PERIL0
+	str	r1, [r0, r2]
+	/* SLIMBUS: ???, PWM */
+	ldr	r1, =0x8
+	ldr	r2, =0x0C55C			@ CLK_DIV_PERIL3
+	str	r1, [r0, r2]
+
+	/* PLL Setting */
+	ldr	r1, =0x1C20
+	ldr	r2, =0x14000			@ APLL_LOCK
+	str	r1, [r0, r2]
+	ldr	r2, =0x14008			@ MPLL_LOCK
+	str	r1, [r0, r2]
+	ldr	r2, =0x0C010			@ EPLL_LOCK
+	str	r1, [r0, r2]
+	ldr	r2, =0x0C020			@ VPLL_LOCK
+	str	r1, [r0, r2]
+
+	/* APLL */
+	ldr	r1, =0x8000001c
+	ldr	r2, =0x14104			@ APLL_CON1
+	str	r1, [r0, r2]
+	ldr	r1, =0x80c80601			@ 800MHz
+	ldr	r2, =0x14100			@ APLL_CON0
+	str	r1, [r0, r2]
+	/* MPLL */
+	ldr	r1, =0x8000001C
+	ldr	r2, =0x1410C			@ MPLL_CON1
+	str	r1, [r0, r2]
+	ldr	r1, =0x80c80601			@ 800MHz
+	ldr	r2, =0x14108			@ MPLL_CON0
+	str	r1, [r0, r2]
+	/* EPLL */
+	ldr	r1, =0x0
+	ldr	r2, =0x0C114			@ EPLL_CON1
+	str	r1, [r0, r2]
+	ldr	r1, =0x80300302			@ 96MHz
+	ldr	r2, =0x0C110			@ EPLL_CON0
+	str	r1, [r0, r2]
+	/* VPLL */
+	ldr	r1, =0x11000400
+	ldr	r2, =0x0C124			@ VPLL_CON1
+	str	r1, [r0, r2]
+	ldr	r1, =0x80350302			@ 108MHz
+	ldr	r2, =0x0C120			@ VPLL_CON0
+	str	r1, [r0, r2]
+
+	/*
+	 * SMMUJPEG[11], JPEG[6], CSIS1[5]		: 0111 1001
+	 * Turn off all
+	 */
+	ldr	r1, =0xFFF80000
+	ldr	r2, =0x0C920			@ CLK_GATE_IP_CAM
+	str	r1, [r0, r2]
+
+	/* Turn off all */
+	ldr	r1, =0xFFFFFFC0
+	ldr	r2, =0x0C924			@ CLK_GATE_IP_VP
+	str	r1, [r0, r2]
+
+	/* Turn off all */
+	ldr	r1, =0xFFFFFFE0
+	ldr	r2, =0x0C928			@ CLK_GATE_IP_MFC
+	str	r1, [r0, r2]
+
+	/* Turn off all */
+	ldr	r1, =0xFFFFFFFC
+	ldr	r2, =0x0C92C			@ CLK_GATE_IP_G3D
+	str	r1, [r0, r2]
+
+	/* Turn off all */
+	ldr	r1, =0xFFFFFC00
+	ldr	r2, =0x0C930			@ CLK_GATE_IP_IMAGE
+	str	r1, [r0, r2]
+
+	/* DSIM0[3], MDNIE0[2], MIE0[1]			: 0001 */
+	ldr	r1, =0xFFFFFFF1
+	ldr	r2, =0x0C934			@ CLK_GATE_IP_LCD0
+	str	r1, [r0, r2]
+
+	/* Turn off all */
+	ldr	r1, =0xFFFFFFC0
+	ldr	r2, =0x0C938			@ CLK_GATE_IP_LCD1
+	str	r1, [r0, r2]
+
+	/*
+	 * SMMUPCIE[18], NFCON[16]			: 1111 1010
+	 * PCIE[14],  SATA[10], SDMMC43[9:8]		: 1011 1000
+	 * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2]	: 1010 0011
+	 */
+	ldr	r1, =0xFFFAB8A3
+	ldr	r2, =0x0C940			@ CLK_GATE_IP_FSYS
+	str	r1, [r0, r2]
+
+	/* Turn off all */
+	ldr	r1, =0xFFFFFFFC
+	ldr	r2, =0x0C94C			@ CLK_GATE_IP_GPS
+	str	r1, [r0, r2]
+
+	/*
+	 * AC97[27], SPDIF[26], SLIMBUS[25]		: 1111 0001
+	 * I2C2[8]					: 1111 1110
+	 */
+	ldr	r1, =0xF1FFFEFF
+	ldr	r2, =0x0C950			@ CLK_GATE_IP_PERIL
+	str	r1, [r0, r2]
+
+	/*
+	 * KEYIF[16]					: 1111 1110
+	 */
+	ldr	r1, =0xFFFEFFFF
+	ldr	r2, =0x0C960			@ CLK_GATE_IP_PERIR
+	str	r1, [r0, r2]
+
+	/* LCD1[5], G3D[3], MFC[2], TV[1]		: 1101 0001 */
+	ldr	r1, =0xFFFFFFD1
+	ldr	r2, =0x0C970			@ CLK_GATE_BLOCK
+	str	r1, [r0, r2]
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+system_power_init:
+	ldr	r0, =S5PC210_POWER_BASE		@ 0x10020000
+
+	ldr	r2, =0x330C			@ PS_HOLD_CONTROL
+	ldr	r1, [r0, r2]
+	orr	r1, r1, #(0x3 << 8)		@ Data High, Output En
+	str	r1, [r0, r2]
+
+	/* Power Down */
+	add	r2, r0, #0x3000
+	str	r5, [r2, #0xC20]		@ TV_CONFIGURATION
+	str	r5, [r2, #0xC40]		@ MFC_CONFIGURATION
+	str	r5, [r2, #0xC60]		@ G3D_CONFIGURATION
+	str	r5, [r2, #0xCA0]		@ LCD1_CONFIGURATION
+	str	r5, [r2, #0xCE0]		@ GPS_CONFIGURATION
+
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+tzpc_init:
+	ldr	r0, =0x10110000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10120000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10130000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10140000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10150000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	mov	pc, lr
diff --git a/u-boot/board/samsung/universal_c210/onenand.c b/u-boot/board/samsung/universal_c210/onenand.c
new file mode 100644
index 0000000..20e1dc5
--- /dev/null
+++ b/u-boot/board/samsung/universal_c210/onenand.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
diff --git a/u-boot/board/samsung/universal_c210/universal.c b/u-boot/board/samsung/universal_c210/universal.c
new file mode 100644
index 0000000..b65bc6e
--- /dev/null
+++ b/u-boot/board/samsung/universal_c210/universal.c
@@ -0,0 +1,250 @@
+/*
+ *  Copyright (C) 2010 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+unsigned int board_rev;
+
+u32 get_board_rev(void)
+{
+	return board_rev;
+}
+
+static int get_hwrev(void)
+{
+	return board_rev & 0xFF;
+}
+
+static void check_hw_revision(void);
+
+int board_init(void)
+{
+	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	check_hw_revision();
+	printf("HW Revision:\t0x%x\n", board_rev);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
+		get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static unsigned short get_adc_value(int channel)
+{
+	struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
+	unsigned short ret = 0;
+	unsigned int reg;
+	unsigned int loop = 0;
+
+	writel(channel & 0xF, &adc->adcmux);
+	writel((1 << 14) | (49 << 6), &adc->adccon);
+	writel(1000 & 0xffff, &adc->adcdly);
+	writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
+	udelay(10);
+	writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
+	udelay(10);
+
+	do {
+		udelay(1);
+		reg = readl(&adc->adccon);
+	} while (!(reg & (1 << 15)) && (loop++ < 1000));
+
+	ret = readl(&adc->adcdat0) & 0xFFF;
+
+	return ret;
+}
+
+static unsigned int get_hw_revision(void)
+{
+	int hwrev, mode0, mode1;
+
+	mode0 = get_adc_value(1);		/* HWREV_MODE0 */
+	mode1 = get_adc_value(2);		/* HWREV_MODE1 */
+
+	/*
+	 * XXX Always set the default hwrev as the latest board
+	 * ADC = (voltage) / 3.3 * 4096
+	 */
+	hwrev = 3;
+
+#define IS_RANGE(x, min, max)	((x) > (min) && (x) < (max))
+	if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x0;		/* 0.01V	0.01V */
+	if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x1;		/* 610mV	0.01V */
+	if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x2;		/* 1.16V	0.01V */
+	if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x3;		/* 1.79V	0.01V */
+#undef IS_RANGE
+
+	debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
+
+	return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+	int hwrev;
+
+	hwrev = get_hw_revision();
+
+	board_rev |= hwrev;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board:\tUniversal C210\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	switch (get_hwrev()) {
+	case 0:
+		/*
+		 * Set the low to enable LDO_EN
+		 * But when you use the test board for eMMC booting
+		 * you should set it HIGH since it removes the inverter
+		 */
+		/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+		gpio_direction_output(&gpio1->e3, 6, 0);
+		break;
+	default:
+		/*
+		 * Default reset state is High and there's no inverter
+		 * But set it as HIGH to ensure
+		 */
+		/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+		gpio_direction_output(&gpio1->e1, 3, 1);
+		break;
+	}
+
+	/*
+	 * eMMC GPIO:
+	 * SDR 8-bit@48MHz at MMC0
+	 * GPK0[0]	SD_0_CLK(2)
+	 * GPK0[1]	SD_0_CMD(2)
+	 * GPK0[2]	SD_0_CDn	-> Not used
+	 * GPK0[3:6]	SD_0_DATA[0:3](2)
+	 * GPK1[3:6]	SD_0_DATA[0:3](3)
+	 *
+	 * DDR 4-bit@26MHz at MMC4
+	 * GPK0[0]	SD_4_CLK(3)
+	 * GPK0[1]	SD_4_CMD(3)
+	 * GPK0[2]	SD_4_CDn	-> Not used
+	 * GPK0[3:6]	SD_4_DATA[0:3](3)
+	 * GPK1[3:6]	SD_4_DATA[4:7](4)
+	 */
+	for (i = 0; i < 7; i++) {
+		if (i == 2)
+			continue;
+		/* GPK0[0:6] special function 2 */
+		gpio_cfg_pin(&gpio2->k0, i, 0x2);
+		/* GPK0[0:6] pull disable */
+		gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
+		/* GPK0[0:6] drv 4x */
+		gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
+	}
+
+	for (i = 3; i < 7; i++) {
+		/* GPK1[3:6] special function 3 */
+		gpio_cfg_pin(&gpio2->k1, i, 0x3);
+		/* GPK1[3:6] pull disable */
+		gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
+		/* GPK1[3:6] drv 4x */
+		gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
+	}
+
+	/* T-flash detect */
+	gpio_cfg_pin(&gpio2->x3, 4, 0xf);
+	gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+
+	/*
+	 * MMC device init
+	 * mmc0	 : eMMC (8-bit buswidth)
+	 * mmc2	 : SD card (4-bit buswidth)
+	 */
+	err = s5p_mmc_init(0, 8);
+
+	/*
+	 * Check the T-flash  detect pin
+	 * GPX3[4] T-flash detect pin
+	 */
+	if (!gpio_get_value(&gpio2->x3, 4)) {
+		/*
+		 * SD card GPIO:
+		 * GPK2[0]	SD_2_CLK(2)
+		 * GPK2[1]	SD_2_CMD(2)
+		 * GPK2[2]	SD_2_CDn	-> Not used
+		 * GPK2[3:6]	SD_2_DATA[0:3](2)
+		 */
+		for (i = 0; i < 7; i++) {
+			if (i == 2)
+				continue;
+			/* GPK2[0:6] special function 2 */
+			gpio_cfg_pin(&gpio2->k2, i, 0x2);
+			/* GPK2[0:6] pull disable */
+			gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			/* GPK2[0:6] drv 4x */
+			gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+		}
+		err = s5p_mmc_init(2, 4);
+	}
+
+	return err;
+
+}
+#endif
diff --git a/u-boot/board/sandburst/common/flash.c b/u-boot/board/sandburst/common/flash.c
new file mode 100644
index 0000000..c65cb96
--- /dev/null
+++ b/u-boot/board/sandburst/common/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Ported from Ebony flash support
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{0xfff80000}	/* Boot Flash */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size(
+			(vu_long *)flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i]<<20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	 /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		{
+			if (*flash++ != 0xffffffff)
+			{
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   "
+				);
+			}
+		printf ("\n");
+		return;
+	}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[1];			/* device ID		*/
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000; /* => 512 kb */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id  == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* reset to return to reading data */
+	addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			DEBUGF("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;	 /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00300030;	 /* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/sandburst/common/ppc440gx_i2c.c b/u-boot/board/sandburst/common/ppc440gx_i2c.c
new file mode 100644
index 0000000..85b63fc
--- /dev/null
+++ b/u-boot/board/sandburst/common/ppc440gx_i2c.c
@@ -0,0 +1,510 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from arch/powerpc/cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation.
+ */
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <i2c.h>
+#include <command.h>
+#include "ppc440gx_i2c.h"
+#include <asm/io.h>
+
+#ifdef CONFIG_I2C_BUS1
+
+#define IIC_OK		0
+#define IIC_NOK		1
+#define IIC_NOK_LA	2		/* Lost arbitration */
+#define IIC_NOK_ICT	3		/* Incomplete transfer */
+#define IIC_NOK_XFRA	4		/* Transfer aborted */
+#define IIC_NOK_DATA	5		/* No data in buffer */
+#define IIC_NOK_TOUT	6		/* Transfer timeout */
+
+#define IIC_TIMEOUT 1			/* 1 second */
+#if defined(CONFIG_SYS_I2C_NOPROBES)
+static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
+#endif
+
+static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;
+
+static void _i2c_bus1_reset (void)
+{
+	int i, status;
+
+	/* Reset status register */
+	/* write 1 in SCMP and IRQA to clear these fields */
+	out_8 (IIC_STS1, 0x0A);
+
+	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
+	out_8 (IIC_EXTSTS1, 0x8F);
+	__asm__ volatile ("eieio");
+
+	/*
+	 * Get current state, reset bus
+	 * only if no transfers are pending.
+	 */
+	i = 10;
+	do {
+		/* Get status */
+		status = in_8 (IIC_STS1);
+		udelay (500);			/* 500us */
+		i--;
+	} while ((status & IIC_STS_PT) && (i > 0));
+	/* Soft reset controller */
+	status = in_8 (IIC_XTCNTLSS1);
+	out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
+	__asm__ volatile ("eieio");
+
+	/* make sure where in initial state, data hi, clock hi */
+	out_8 (IIC_DIRECTCNTL1, 0xC);
+	for (i = 0; i < 10; i++) {
+		if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
+			/* clock until we get to known state */
+			out_8 (IIC_DIRECTCNTL1, 0x8);	/* clock lo */
+			udelay (100);		/* 100us */
+			out_8 (IIC_DIRECTCNTL1, 0xC);	/* clock hi */
+			udelay (100);		/* 100us */
+		} else {
+			break;
+		}
+	}
+	/* send start condition */
+	out_8 (IIC_DIRECTCNTL1, 0x4);
+	udelay (1000);				/* 1ms */
+	/* send stop condition */
+	out_8 (IIC_DIRECTCNTL1, 0xC);
+	udelay (1000);				/* 1ms */
+	/* Unreset controller */
+	out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
+	udelay (1000);				/* 1ms */
+}
+
+void i2c1_init (int speed, int slaveadd)
+{
+	sys_info_t sysInfo;
+	unsigned long freqOPB;
+	int val, divisor;
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+	/* call board specific i2c bus reset routine before accessing the   */
+	/* environment, which might be in a chip on that bus. For details   */
+	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	i2c_init_board();
+#endif
+
+	/* Handle possible failed I2C state */
+	/* FIXME: put this into i2c_init_board()? */
+	_i2c_bus1_reset ();
+
+	/* clear lo master address */
+	out_8 (IIC_LMADR1, 0);
+
+	/* clear hi master address */
+	out_8 (IIC_HMADR1, 0);
+
+	/* clear lo slave address */
+	out_8 (IIC_LSADR1, 0);
+
+	/* clear hi slave address */
+	out_8 (IIC_HSADR1, 0);
+
+	/* Clock divide Register */
+	/* get OPB frequency */
+	get_sys_info (&sysInfo);
+	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
+	/* set divisor according to freqOPB */
+	divisor = (freqOPB - 1) / 10000000;
+	if (divisor == 0)
+		divisor = 1;
+	out_8 (IIC_CLKDIV1, divisor);
+
+	/* no interrupts */
+	out_8 (IIC_INTRMSK1, 0);
+
+	/* clear transfer count */
+	out_8 (IIC_XFRCNT1, 0);
+
+	/* clear extended control & stat */
+	/* write 1 in SRC SRS SWC SWS to clear these fields */
+	out_8 (IIC_XTCNTLSS1, 0xF0);
+
+	/* Mode Control Register
+	   Flush Slave/Master data buffer */
+	out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+	__asm__ volatile ("eieio");
+
+
+	val = in_8(IIC_MDCNTL1);
+	__asm__ volatile ("eieio");
+
+	/* Ignore General Call, slave transfers are ignored,
+	   disable interrupts, exit unknown bus state, enable hold
+	   SCL
+	   100kHz normaly or FastMode for 400kHz and above
+	*/
+
+	val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+	if( speed >= 400000 ){
+		val |= IIC_MDCNTL_FSM;
+	}
+	out_8 (IIC_MDCNTL1, val);
+
+	/* clear control reg */
+	out_8 (IIC_CNTL1, 0x00);
+	__asm__ volatile ("eieio");
+
+}
+
+/*
+  This code tries to use the features of the 405GP i2c
+  controller. It will transfer up to 4 bytes in one pass
+  on the loop. It only does out_8(lbz) to the buffer when it
+  is possible to do out16(lhz) transfers.
+
+  cmd_type is 0 for write 1 for read.
+
+  addr_len can take any value from 0-255, it is only limited
+  by the char, we could make it larger if needed. If it is
+  0 we skip the address write cycle.
+
+  Typical case is a Write of an addr followd by a Read. The
+  IBM FAQ does not cover this. On the last byte of the write
+  we don't set the creg CHT bit, and on the first bytes of the
+  read we set the RPST bit.
+
+  It does not support address only transfers, there must be
+  a data part. If you want to write the address yourself, put
+  it in the data pointer.
+
+  It does not support transfer to/from address 0.
+
+  It does not check XFRCNT.
+*/
+static
+int i2c_transfer1(unsigned char cmd_type,
+		  unsigned char chip,
+		  unsigned char addr[],
+		  unsigned char addr_len,
+		  unsigned char data[],
+		  unsigned short data_len )
+{
+	unsigned char* ptr;
+	int reading;
+	int tran,cnt;
+	int result;
+	int status;
+	int i;
+	uchar creg;
+
+	if( data == 0 || data_len == 0 ){
+		/*Don't support data transfer of no length or to address 0*/
+		printf( "i2c_transfer: bad call\n" );
+		return IIC_NOK;
+	}
+	if( addr && addr_len ){
+		ptr = addr;
+		cnt = addr_len;
+		reading = 0;
+	}else{
+		ptr = data;
+		cnt = data_len;
+		reading = cmd_type;
+	}
+
+	/*Clear Stop Complete Bit*/
+	out_8(IIC_STS1,IIC_STS_SCMP);
+	/* Check init */
+	i=10;
+	do {
+		/* Get status */
+		status = in_8(IIC_STS1);
+		__asm__ volatile("eieio");
+		i--;
+	} while ((status & IIC_STS_PT) && (i>0));
+
+	if (status & IIC_STS_PT) {
+		result = IIC_NOK_TOUT;
+		return(result);
+	}
+	/*flush the Master/Slave Databuffers*/
+	out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+	/*need to wait 4 OPB clocks? code below should take that long*/
+
+	/* 7-bit adressing */
+	out_8(IIC_HMADR1,0);
+	out_8(IIC_LMADR1, chip);
+	__asm__ volatile("eieio");
+
+	tran = 0;
+	result = IIC_OK;
+	creg = 0;
+
+	while ( tran != cnt && (result == IIC_OK)) {
+		int  bc,j;
+
+		/* Control register =
+		   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+		   Transfer is a sequence of transfers
+		*/
+		creg |= IIC_CNTL_PT;
+
+		bc = (cnt - tran) > 4 ? 4 :
+			cnt - tran;
+		creg |= (bc-1)<<4;
+		/* if the real cmd type is write continue trans*/
+		if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+			creg |= IIC_CNTL_CHT;
+
+		if (reading)
+			creg |= IIC_CNTL_READ;
+		else {
+			for(j=0; j<bc; j++) {
+				/* Set buffer */
+				out_8(IIC_MDBUF1,ptr[tran+j]);
+				__asm__ volatile("eieio");
+			}
+		}
+		out_8(IIC_CNTL1, creg );
+		__asm__ volatile("eieio");
+
+		/* Transfer is in progress
+		   we have to wait for upto 5 bytes of data
+		   1 byte chip address+r/w bit then bc bytes
+		   of data.
+		   udelay(10) is 1 bit time at 100khz
+		   Doubled for slop. 20 is too small.
+		*/
+		i=2*5*8;
+		do {
+			/* Get status */
+			status = in_8(IIC_STS1);
+			__asm__ volatile("eieio");
+			udelay (10);
+			i--;
+		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
+			 && (i>0));
+
+		if (status & IIC_STS_ERR) {
+			result = IIC_NOK;
+			status = in_8 (IIC_EXTSTS1);
+			/* Lost arbitration? */
+			if (status & IIC_EXTSTS_LA)
+				result = IIC_NOK_LA;
+			/* Incomplete transfer? */
+			if (status & IIC_EXTSTS_ICT)
+				result = IIC_NOK_ICT;
+			/* Transfer aborted? */
+			if (status & IIC_EXTSTS_XFRA)
+				result = IIC_NOK_XFRA;
+		} else if ( status & IIC_STS_PT) {
+			result = IIC_NOK_TOUT;
+		}
+		/* Command is reading => get buffer */
+		if ((reading) && (result == IIC_OK)) {
+			/* Are there data in buffer */
+			if (status & IIC_STS_MDBS) {
+				/*
+				  even if we have data we have to wait 4OPB clocks
+				  for it to hit the front of the FIFO, after that
+				  we can just read. We should check XFCNT here and
+				  if the FIFO is full there is no need to wait.
+				*/
+				udelay (1);
+				for(j=0;j<bc;j++) {
+					ptr[tran+j] = in_8(IIC_MDBUF1);
+					__asm__ volatile("eieio");
+				}
+			} else
+				result = IIC_NOK_DATA;
+		}
+		creg = 0;
+		tran+=bc;
+		if( ptr == addr && tran == cnt ) {
+			ptr = data;
+			cnt = data_len;
+			tran = 0;
+			reading = cmd_type;
+			if( reading )
+				creg = IIC_CNTL_RPST;
+		}
+	}
+	return (result);
+}
+
+int i2c_probe1 (uchar chip)
+{
+	uchar buf[1];
+
+	buf[0] = 0;
+
+	/*
+	 * What is needed is to send the chip address and verify that the
+	 * address was <ACK>ed (i.e. there was a chip at that address which
+	 * drove the data line low).
+	 */
+	return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
+}
+
+
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	uchar xaddr[4];
+	int ret;
+
+	if ( alen > 4 ) {
+		printf ("I2C read: addr len %d not supported\n", alen);
+		return 1;
+	}
+
+	if ( alen > 0 ) {
+		xaddr[0] = (addr >> 24) & 0xFF;
+		xaddr[1] = (addr >> 16) & 0xFF;
+		xaddr[2] = (addr >> 8) & 0xFF;
+		xaddr[3] = addr & 0xFF;
+	}
+
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	if( alen > 0 )
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+	if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+		printf( "I2c read: failed %d\n", ret);
+		return 1;
+	}
+	return 0;
+}
+
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	uchar xaddr[4];
+
+	if ( alen > 4 ) {
+		printf ("I2C write: addr len %d not supported\n", alen);
+		return 1;
+
+	}
+	if ( alen > 0 ) {
+		xaddr[0] = (addr >> 24) & 0xFF;
+		xaddr[1] = (addr >> 16) & 0xFF;
+		xaddr[2] = (addr >> 8) & 0xFF;
+		xaddr[3] = addr & 0xFF;
+	}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	if( alen > 0 )
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+
+	return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
+{
+	uchar buf;
+
+	i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
+
+	return(buf);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write1(i2c_addr, reg, 1, &val, 1);
+}
+
+
+int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int j;
+#if defined(CONFIG_SYS_I2C_NOPROBES)
+	int k, skip;
+#endif
+
+	puts ("Valid chip addresses:");
+	for(j = 0; j < 128; j++) {
+#if defined(CONFIG_SYS_I2C_NOPROBES)
+		skip = 0;
+		for (k = 0; k < sizeof(i2c_no_probes); k++){
+			if (j == i2c_no_probes[k]){
+				skip = 1;
+				break;
+			}
+		}
+		if (skip)
+			continue;
+#endif
+		if(i2c_probe1(j) == 0) {
+			printf(" %02X", j);
+		}
+	}
+	putc ('\n');
+
+#if defined(CONFIG_SYS_I2C_NOPROBES)
+	puts ("Excluded chip addresses:");
+	for( k = 0; k < sizeof(i2c_no_probes); k++ )
+		printf(" %02X", i2c_no_probes[k] );
+	putc ('\n');
+#endif
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	iprobe1,	1,	1,	do_i2c1_probe,
+	"probe to discover valid I2C chip addresses",
+	""
+);
+
+#endif	/* CONFIG_I2C_BUS1 */
diff --git a/u-boot/board/sandburst/common/ppc440gx_i2c.h b/u-boot/board/sandburst/common/ppc440gx_i2c.h
new file mode 100644
index 0000000..7496db4
--- /dev/null
+++ b/u-boot/board/sandburst/common/ppc440gx_i2c.h
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from i2c driver for ppc4xx by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <i2c.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
+#define	   I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
+#define    IIC_MDBUF1	(&i2c->mdbuf)
+#define    IIC_SDBUF1	(&i2c->sdbuf)
+#define    IIC_LMADR1	(&i2c->lmadr)
+#define    IIC_HMADR1	(&i2c->hmadr)
+#define    IIC_CNTL1	(&i2c->cntl)
+#define    IIC_MDCNTL1	(&i2c->mdcntl)
+#define    IIC_STS1	(&i2c->sts)
+#define    IIC_EXTSTS1	(&i2c->extsts)
+#define    IIC_LSADR1	(&i2c->lsadr)
+#define    IIC_HSADR1	(&i2c->hsadr)
+#define    IIC_CLKDIV1	(&i2c->clkdiv)
+#define    IIC_INTRMSK1	(&i2c->intrmsk)
+#define    IIC_XFRCNT1	(&i2c->xfrcnt)
+#define    IIC_XTCNTLSS1	(&i2c->xtcntlss)
+#define    IIC_DIRECTCNTL1 (&i2c->directcntl)
+
+void i2c1_init (int speed, int slaveadd);
+int i2c_probe1 (uchar chip);
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
+
+#endif	/* CONFIG_HARD_I2C */
diff --git a/u-boot/board/sandburst/common/sb_common.c b/u-boot/board/sandburst/common/sb_common.c
new file mode 100644
index 0000000..6b91074
--- /dev/null
+++ b/u-boot/board/sandburst/common/sb_common.c
@@ -0,0 +1,364 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+#include "sb_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+long int fixed_sdram (void);
+
+/*************************************************************************
+ *  metrobox_get_master
+ *
+ *  PRI_N - active low signal.	If the GPIO pin is low we are the master
+ *
+ ************************************************************************/
+int sbcommon_get_master(void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
+
+	if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
+		return 0;
+	}
+	else {
+		return 1;
+	}
+}
+
+/*************************************************************************
+ *  metrobox_secondary_present
+ *
+ *  Figure out if secondary/slave board is present
+ *
+ ************************************************************************/
+int sbcommon_secondary_present(void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
+
+	if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
+		return 0;
+	else
+		return 1;
+}
+
+/*************************************************************************
+ *  sbcommon_get_serial_number
+ *
+ *  Retrieve the board serial number via the mac address in eeprom
+ *
+ ************************************************************************/
+unsigned short sbcommon_get_serial_number(void)
+{
+	unsigned char buff[0x100];
+	unsigned short sernum;
+
+	/* Get the board serial number from eeprom */
+	/* Initialize I2C */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM */
+	i2c_read (0x50, 0, 1, buff, 0x100);
+
+	memcpy(&sernum, &buff[0xF4], 2);
+	sernum /= 32;
+
+	return (sernum);
+}
+
+/*************************************************************************
+ *  sbcommon_fans
+ *
+ *  Spin up fans 2 & 3 to get some air moving.	OS will take care
+ *  of the rest.  This is mostly a precaution...
+ *
+ *  Assumes i2c bus 1 is ready.
+ *
+ ************************************************************************/
+void sbcommon_fans(void)
+{
+	/*
+	 * Attempt to turn on 2 of the fans...
+	 * Need to go through the bridge
+	 */
+	puts ("FANS:  ");
+
+	/* select fan4 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x08); /* val = bus 4 */
+
+	/* Turn on FAN 4 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 4 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	/* select fan3 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x04); /* val = bus 3 */
+
+	/* Turn on FAN 3 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 3 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	/* select fan2 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x02); /* val = bus 4 */
+
+	/* Turn on FAN 2 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 2 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	/* select fan1 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x01); /* val = bus 0 */
+
+	/* Turn on FAN 1 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 1 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	puts ("on\n");
+
+	return;
+
+}
+
+/*************************************************************************
+ *  initdram
+ *
+ *  Initialize sdram
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+/*************************************************************************
+ *  testdram
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("Testing SDRAM: ");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("OK\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:	128 MB, non-ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (SDRAM0_SLIO, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (SDRAM0_WDDCTR, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (SDRAM0_CLKTR, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (SDRAM0_TR0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3			    */
+	mtsdram (SDRAM0_TR1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (SDRAM0_RTR, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)	    */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	for (;;) {
+		mfsdram (SDRAM0_MCSTS, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB			    */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+/*************************************************************************
+ *  board_get_enetaddr
+ *
+ *  Get the ethernet MAC address for the management ethernet from the
+ *  strap EEPROM.  Note that is the BASE address for the range of
+ *  external ethernet MACs on the board.  The base + 31 is the actual
+ *  mgmt mac address.
+ *
+ ************************************************************************/
+
+void board_get_enetaddr(int macaddr_idx, uchar *enet)
+{
+	int i;
+	unsigned short tmp;
+	unsigned char buff[0x100], *cp;
+
+	if (0 == macaddr_idx) {
+
+		/* Initialize I2C */
+		i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+		/* Read 256 bytes in EEPROM */
+		i2c_read (0x50, 0, 1, buff, 0x100);
+
+		cp = &buff[0xF0];
+
+		for (i = 0; i < 6; i++,cp++)
+			enet[i] = *cp;
+
+		memcpy(&tmp, &enet[4], 2);
+		tmp += 31;
+		memcpy(&enet[4], &tmp, 2);
+
+	} else {
+		enet[0] = 0x02;
+		enet[1] = 0x00;
+		enet[2] = 0x00;
+		enet[3] = 0x00;
+		enet[4] = 0x00;
+		if (1 == sbcommon_get_master() ) {
+			/* Master/Primary card */
+			enet[5] = 0x01;
+		} else {
+			/* Slave/Secondary card */
+			enet [5] = 0x02;
+		}
+	}
+
+	return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+#endif
diff --git a/u-boot/board/sandburst/common/sb_common.h b/u-boot/board/sandburst/common/sb_common.h
new file mode 100644
index 0000000..e652ba8
--- /dev/null
+++ b/u-boot/board/sandburst/common/sb_common.h
@@ -0,0 +1,77 @@
+#ifndef __SBCOMMON_H__
+#define __SBCOMMON_H__
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+
+/*
+ * GPIO Settings
+ */
+/* Chassis settings */
+#define SBCOMMON_GPIO_PRI_N		0x00001000  /* 0 = Chassis Master, 1 = Slave */
+#define SBCOMMON_GPIO_SEC_PRES		0x00000800  /* 1 = Other board present */
+
+/* Debug LEDs */
+#define SBCOMMON_GPIO_DBGLED_0		0x00000400
+#define SBCOMMON_GPIO_DBGLED_1		0x00000200
+#define SBCOMMON_GPIO_DBGLED_2		0x00100000
+#define SBCOMMON_GPIO_DBGLED_3		0x00000100
+
+#define SBCOMMON_GPIO_DBGLEDS		(SBCOMMON_GPIO_DBGLED_0 | \
+					 SBCOMMON_GPIO_DBGLED_1 | \
+					 SBCOMMON_GPIO_DBGLED_2 | \
+					 SBCOMMON_GPIO_DBGLED_3)
+
+#define SBCOMMON_GPIO_SYS_FAULT		0x00000080
+#define SBCOMMON_GPIO_SYS_OTEMP		0x00000040
+#define SBCOMMON_GPIO_SYS_STATUS	0x00000020
+
+#define SBCOMMON_GPIO_SYS_LEDS		(SBCOMMON_GPIO_SYS_STATUS)
+
+#define SBCOMMON_GPIO_LEDS		(SBCOMMON_GPIO_DBGLED_0 | \
+					 SBCOMMON_GPIO_DBGLED_1 | \
+					 SBCOMMON_GPIO_DBGLED_2 | \
+					 SBCOMMON_GPIO_DBGLED_3 | \
+					 SBCOMMON_GPIO_SYS_STATUS)
+
+typedef struct ppc440_gpio_regs {
+	volatile unsigned long out;
+	volatile unsigned long tri_state;
+	volatile unsigned long dummy[4];
+	volatile unsigned long open_drain;
+	volatile unsigned long in;
+}  __attribute__((packed)) ppc440_gpio_regs_t;
+
+int sbcommon_get_master(void);
+int sbcommon_secondary_present(void);
+unsigned short sbcommon_get_serial_number(void);
+void sbcommon_fans(void);
+void board_get_enetaddr(int macaddr_idx, uchar *enet);
+
+#endif /* __SBCOMMON_H__ */
diff --git a/u-boot/board/sandburst/karef/Makefile b/u-boot/board/sandburst/karef/Makefile
new file mode 100644
index 0000000..d447140
--- /dev/null
+++ b/u-boot/board/sandburst/karef/Makefile
@@ -0,0 +1,68 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+# Travis B. Sawyer
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+	../common/sb_common.o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sandburst/karef/config.mk b/u-boot/board/sandburst/karef/config.mk
new file mode 100644
index 0000000..85fccd8
--- /dev/null
+++ b/u-boot/board/sandburst/karef/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandburst Corporation Metrobox Reference Design
+# Travis B. Sawyer
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/sandburst/karef/hal_ka_of_auto.h b/u-boot/board/sandburst/karef/hal_ka_of_auto.h
new file mode 100644
index 0000000..cc501c9
--- /dev/null
+++ b/u-boot/board/sandburst/karef/hal_ka_of_auto.h
@@ -0,0 +1,324 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_of
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_OF_AUTO_H
+#define HAL_KA_OF_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'ofem'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define OFEM_BLOCK_ADDR_BIT_L 6
+#define OFEM_BLOCK_ADDR_BIT_H 9
+#define OFEM_BLOCK_ADDR_WIDTH 4
+
+#define  OFEM_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define OFEM_REG_ADDR_BIT_L 2
+#define OFEM_REG_ADDR_BIT_H 5
+#define OFEM_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_REVISION_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_REVISION_MSB     31
+#define SAND_HAL_KA_OF_OFEM_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET    0x004
+#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_RESET_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_RESET_MSB     31
+#define SAND_HAL_KA_OF_OFEM_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET    0x018
+#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_CNTL_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_CNTL_MSB     31
+#define SAND_HAL_KA_OF_OFEM_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET    0x01c
+#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB     31
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET    0x008
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB     31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET    0x00c
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET    0x010
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB     31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET    0x014
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB     31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT    0x00000024
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB    7
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB    0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK    0x000000c0
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB    7
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB    6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK    0x00000030
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB    5
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB    4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK    0x0000000c
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB    3
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB    2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK    0x00000003
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB    1
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB    0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK    0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK    0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
diff --git a/u-boot/board/sandburst/karef/hal_ka_sc_auto.h b/u-boot/board/sandburst/karef/hal_ka_sc_auto.h
new file mode 100644
index 0000000..db1cec2
--- /dev/null
+++ b/u-boot/board/sandburst/karef/hal_ka_sc_auto.h
@@ -0,0 +1,836 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_sc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_SC_AUTO_H
+#define HAL_KA_SC_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'scan'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define SCAN_BLOCK_ADDR_BIT_L 7
+#define SCAN_BLOCK_ADDR_BIT_H 9
+#define SCAN_BLOCK_ADDR_WIDTH 3
+
+#define  SCAN_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define SCAN_REG_ADDR_BIT_L 2
+#define SCAN_REG_ADDR_BIT_H 6
+#define SCAN_REG_ADDR_WIDTH 5
+
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_REVISION_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_REVISION_MSB     31
+#define SAND_HAL_KA_SC_SCAN_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET    0x004
+#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_RESET_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_RESET_MSB     31
+#define SAND_HAL_KA_SC_SCAN_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET    0x008
+#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_STATUS_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_STATUS_MSB     31
+#define SAND_HAL_KA_SC_SCAN_STATUS_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET    0x01c
+#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CNTL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CNTL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET    0x020
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET    0x024
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET    0x028
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET    0x02c
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET    0x030
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET    0x034
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET    0x038
+#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET    0x03c
+#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET    0x040
+#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET    0x044
+#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET    0x048
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET    0x04c
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET    0x050
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET    0x054
+#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_MISC_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_MISC_MSB     31
+#define SAND_HAL_KA_SC_SCAN_MISC_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET    0x00c
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET    0x010
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET    0x014
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET    0x018
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT    0x00000023
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB    7
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB    0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK    0x00000080
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK    0x000000c0
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB    7
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB    6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK    0x00000030
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB    5
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB    4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK    0x0000000c
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB    3
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB    2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK    0x00000003
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB    1
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB    0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK    0x0000f000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB    15
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB    12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK    0x00000300
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB    9
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB    8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK    0x000000f0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB    7
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB    4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK    0x00000003
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB    1
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK    0x04000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK    0x03000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB    25
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB    24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK    0x00100000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK    0x00080000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK    0x00040000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK    0x00020000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK    0x00010000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK    0x00001000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK    0x00000800
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK    0x00000018
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB    4
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB    3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK    0x00002000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK    0x00001000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK    0x00000800
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK    0x00000080
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK    0x00000007
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB    2
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB    0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
diff --git a/u-boot/board/sandburst/karef/init.S b/u-boot/board/sandburst/karef/init.S
new file mode 100644
index 0000000..11ab5af
--- /dev/null
+++ b/u-boot/board/sandburst/karef/init.S
@@ -0,0 +1,56 @@
+/*
+*  Copyright (C) 2005 Sandburst Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+/*
+ * Ported from Ebony init.S by Travis B. Sawyer
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+	tlbtab_end
diff --git a/u-boot/board/sandburst/karef/karef.c b/u-boot/board/sandburst/karef/karef.c
new file mode 100644
index 0000000..6457f9b
--- /dev/null
+++ b/u-boot/board/sandburst/karef/karef.c
@@ -0,0 +1,617 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *  Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "karef.h"
+#include "karef_version.h"
+#include <timestamp.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/sb_common.h"
+#include "../common/ppc440gx_i2c.h"
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+#include <net.h>
+#endif
+
+void fpga_init (void);
+
+KAREF_BOARD_ID_ST board_id_as[] =
+{
+	{"Undefined"},			     /* Not specified */
+	{"Kamino Reference Design"},
+	{"Reserved"},			     /* Reserved for future use */
+	{"Reserved"},			     /* Reserved for future use */
+};
+
+KAREF_BOARD_ID_ST ofem_board_id_as[] =
+{
+	{"Undefined"},
+	{"1x10 + 10x2"},
+	{"Reserved"},
+	{"Reserved"},
+};
+
+/*************************************************************************
+ *  board_early_init_f
+ *
+ *  Setup chip selects, initialize the Opto-FPGA, initialize
+ *  interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	/* Enable GPIO interrupts */
+	mtsdr(SDR0_PFC0, 0x00103E00);
+
+	/* Setup access for LEDs, and system topology info */
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
+	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
+
+	/* Turn on all the leds for now */
+	gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+	/*--------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------*/
+	mtebc(EBC0_CFG,
+	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
+	      EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------+
+	  | 1/2 MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB0AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+	/*--------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB1AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(PB2AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | KaRef Scan FPGA. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB5AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
+	  | Initialize bank 4 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB4AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
+	      EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | OFEM FPGA  Initialize bank 5 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB3AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+
+	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(PB6AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | BME-32. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB7AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 +-------------------------------------------------------------------*/
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000000);	/* all non- critical */
+	mtdcr (UIC1PR, 0xfffffe03);	/* polarity */
+	mtdcr (UIC1TR, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffc8ff);	/* polarity */
+	mtdcr (UIC2TR, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffff83ff);	/* polarity */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all */
+	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000);
+	mtdcr (UIC0TR, 0x00000000);
+	mtdcr (UIC0VR, 0x00000001);
+
+	fpga_init();
+
+	return 0;
+}
+
+
+/*************************************************************************
+ *  checkboard
+ *
+ *  Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	unsigned char brd_rev, brd_id;
+	unsigned short sernum;
+	unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
+	unsigned char ofem_brd_rev, ofem_brd_id;
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+
+	karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+	ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
+
+	scan_id = (unsigned char)((karef_ps->revision_ul &
+				   SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
+
+	scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
+				   >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
+
+	brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
+
+	brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
+				 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
+
+	ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+				      >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+
+	ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
+				       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
+
+	if (0xF != ofem_brd_id) {
+		ofem_id = (unsigned char)((ofem_ps->revision_ul &
+					   SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
+					  >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
+
+		ofem_rev = (unsigned char)((ofem_ps->revision_ul &
+					    SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
+					   >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
+	}
+
+	get_sys_info (&sysinfo);
+
+	sernum = sbcommon_get_serial_number();
+
+	printf ("Board: Sandburst Corporation Kamino Reference Design "
+		"Serial Number: %d\n", sernum);
+	printf ("%s\n", KAREF_U_BOOT_REL_STR);
+
+	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
+	if (sbcommon_get_master()) {
+		printf("Slot 0 - Master\nSlave board");
+		if (sbcommon_secondary_present())
+			printf(" present\n");
+		else
+			printf(" not detected\n");
+	} else {
+		printf("Slot 1 - Slave\n\n");
+	}
+
+	printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
+	printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
+	if(0xF != ofem_brd_id) {
+		printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
+		printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
+	}
+
+	/* Fix the ack in the bme 32 */
+	udelay(5000);
+	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
+	asm("eieio");
+
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_f
+ *
+ *  Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+	/* Turn on i2c bus 1 */
+	puts ("I2C1:  ");
+	i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	puts ("ready\n");
+
+	/* Turn on fans 3 & 4 */
+	sbcommon_fans();
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_r
+ *
+ *  Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+	unsigned short sernum;
+	char envstr[255];
+	uchar enetaddr[6];
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+
+	if(NULL != getenv("secondserial")) {
+		puts("secondserial is set, switching to second serial port\n");
+		setenv("stderr", "serial1");
+		setenv("stdout", "serial1");
+		setenv("stdin", "serial1");
+	}
+
+	setenv("ubrelver", KAREF_U_BOOT_REL_STR);
+
+	memset(envstr, 0, 255);
+	sprintf (envstr, "Built %s %s by %s",
+		 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
+	setenv("bldstr", envstr);
+	saveenv();
+
+	if( getenv("autorecover")) {
+		setenv("autorecover", NULL);
+		saveenv();
+		sernum = sbcommon_get_serial_number();
+
+		printf("\nSetting up environment for automatic filesystem recovery\n");
+		/*
+		 * Setup default bootargs
+		 */
+		memset(envstr, 0, 255);
+
+		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+			"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+			sernum, sernum);
+		setenv("bootargs", envstr);
+
+		/*
+		 * Setup Default boot command
+		 */
+		setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+		       "fatload ide 0 8100000 pramdisk;"
+		       "bootm 8000000 8100000");
+
+		printf("Done.  Please type allow the system to continue to boot\n");
+	}
+
+	if( getenv("fakeled")) {
+		karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
+		ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
+		karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
+		setenv("bootdelay", "-1");
+		saveenv();
+		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+	}
+
+#ifdef CONFIG_HAS_ETH0
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(0, enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+	if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+		board_get_enetaddr(1, enetaddr);
+		eth_setenv_enetaddr("eth1addr", enetaddr);
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH2
+	if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
+		board_get_enetaddr(2, enetaddr);
+		eth_setenv_enetaddr("eth2addr", enetaddr);
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH3
+	if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
+		board_get_enetaddr(3, enetaddr);
+		eth_setenv_enetaddr("eth3addr", enetaddr);
+	}
+#endif
+
+	return (0);
+}
+
+/*************************************************************************
+ *  ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	KAREF_FPGA_REGS_ST *karef_ps;
+	/* TODO: ide reset */
+	karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+
+	if (on) {
+		karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+	} else {
+		karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ *  fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+	unsigned char ofem_id;
+	unsigned long tmp;
+
+	/* Ensure we have power all around */
+	udelay(500);
+
+	karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+	tmp =
+		SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
+
+	karef_ps->reset_ul = tmp;
+
+	/*
+	 * Wait a bit to allow the ofem fpga to get its brains
+	 */
+	udelay(5000);
+
+	/*
+	 * Check to see if the ofem is there
+	 */
+	ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+	if(0xF != ofem_id) {
+		tmp =
+			SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
+			SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
+			SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
+
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
+		ofem_ps->reset_ul = tmp;
+
+		ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
+	}
+
+	karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
+
+	asm("eieio");
+
+	return;
+}
+
+int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	memset(envstr, 0, 255);
+	/*
+	 * Setup our ip address
+	 */
+	sprintf(envstr, "10.100.70.%d", sernum);
+
+	setenv("ipaddr", envstr);
+	/*
+	 * Setup the host ip address
+	 */
+	setenv("serverip", "10.100.17.10");
+
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+		"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
+		"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
+		"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
+		sernum, sernum, sernum);
+
+	setenv("bootargs_nfs", envstr);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup CF bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+		sernum, sernum);
+
+	setenv("bootargs_cf", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
+	setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
+
+	/*
+	 * Setup compact flash boot command
+	 */
+	setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
+
+	saveenv();
+
+	return(1);
+}
+
+int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	printf("\nSetting up environment for filesystem recovery\n");
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
+		sernum, sernum);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+
+	setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+	       "fatload ide 0 8100000 pramdisk;"
+	       "bootm 8000000 8100000");
+
+	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
+	       " please type fsrecover.sh<cr>\n");
+
+	return(1);
+}
+
+U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
+	   "Set environment to factory defaults", "");
+
+U_BOOT_CMD(karecover, 1, 1, karefRecover,
+	   "Set environment to allow for fs recovery", "");
diff --git a/u-boot/board/sandburst/karef/karef.h b/u-boot/board/sandburst/karef/karef.h
new file mode 100644
index 0000000..5de7cb5
--- /dev/null
+++ b/u-boot/board/sandburst/karef/karef.h
@@ -0,0 +1,76 @@
+#ifndef __KAREF_H__
+#define __KAREF_H__
+/*
+ * (C) Copyright 2005
+ * Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Ka Reference Design OFEM FPGA Registers & definitions */
+#include "hal_ka_sc_auto.h"
+#include "hal_ka_of_auto.h"
+
+typedef struct karef_board_id_s {
+	const char name[40];
+} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
+
+/* SCAN FPGA */
+typedef struct karef_fpga_regs_s
+{
+    volatile unsigned long revision_ul;       /* Read Only  */
+    volatile unsigned long reset_ul;          /* Read/Write */
+    volatile unsigned long interrupt_ul;      /* Read Only  */
+    volatile unsigned long mask_ul;           /* Read/Write */
+    volatile unsigned long scratch_ul;        /* Read/Write */
+    volatile unsigned long scrmask_ul;        /* Read/Write */
+    volatile unsigned long status_ul;         /* Read Only  */
+    volatile unsigned long control_ul;        /* Read/Write */
+    volatile unsigned long boardinfo_ul;      /* Read Only  */
+    volatile unsigned long scan_from0_ul;     /* Read Only  */
+    volatile unsigned long scan_from1_ul;     /* Read Only  */
+    volatile unsigned long scan_to0_ul;       /* Read/Write */
+    volatile unsigned long scan_to1_ul;       /* Read/Write */
+    volatile unsigned long scan_control_ul;   /* Read/Write */
+    volatile unsigned long pll_control_ul;    /* Read/Write */
+    volatile unsigned long core_clock_cnt_ul; /* Read/Write */
+    volatile unsigned long dr_clock_cnt_ul;   /* Read/Write */
+    volatile unsigned long spi_clock_cnt_ul;  /* Read/Write */
+    volatile unsigned long brdout_data_ul;    /* Read/Write */
+    volatile unsigned long brdout_enable_ul;  /* Read/Write */
+    volatile unsigned long brdin_data_ul;     /* Read Only  */
+    volatile unsigned long misc_ul;           /* Read/Write */
+} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
+
+/* OFEM FPGA */
+typedef struct ofem_fpga_regs_s
+{
+    volatile unsigned long revision_ul;       /* Read Only  */
+    volatile unsigned long reset_ul;          /* Read/Write */
+    volatile unsigned long interrupt_ul;      /* Read Only  */
+    volatile unsigned long mask_ul;           /* Read/Write */
+    volatile unsigned long scratch_ul;        /* Read/Write */
+    volatile unsigned long scrmask_ul;        /* Read/Write */
+    volatile unsigned long control_ul;        /* Read/Write */
+    volatile unsigned long mac_flow_ctrl_ul;  /* Read/Write */
+} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
+
+
+#endif /* __KAREF_H__ */
diff --git a/u-boot/board/sandburst/karef/karef_version.h b/u-boot/board/sandburst/karef/karef_version.h
new file mode 100644
index 0000000..9960b9a
--- /dev/null
+++ b/u-boot/board/sandburst/karef/karef_version.h
@@ -0,0 +1,26 @@
+#ifndef _KAREF_VERSION_H_
+#define _KAREF_VERSION_H_
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *  Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
+#endif
diff --git a/u-boot/board/sandburst/karef/u-boot.lds.debug b/u-boot/board/sandburst/karef/u-boot.lds.debug
new file mode 100644
index 0000000..6b31b1e
--- /dev/null
+++ b/u-boot/board/sandburst/karef/u-boot.lds.debug
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/sandburst/karef/init.o (.text)
+    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
+    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
+    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
+    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
+    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
+    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
+    drivers/net/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+    lib/zlib.o		(.text)
+
+/*    common/env_embedded.o(.text) */
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/sandburst/metrobox/Makefile b/u-boot/board/sandburst/metrobox/Makefile
new file mode 100644
index 0000000..e98c989
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/Makefile
@@ -0,0 +1,66 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+	../common/sb_common.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sandburst/metrobox/config.mk b/u-boot/board/sandburst/metrobox/config.mk
new file mode 100644
index 0000000..8407381
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/sandburst/metrobox/hal_xc_auto.h b/u-boot/board/sandburst/metrobox/hal_xc_auto.h
new file mode 100644
index 0000000..c99b38c
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/hal_xc_auto.h
@@ -0,0 +1,553 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip xc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_XC_AUTO_H
+#define HAL_XC_AUTO_H
+
+/* ----------------------------------------------------------------
+ * For block: 'xcvr_cntl'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
+#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
+#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
+
+#define  XCVR_CNTL_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define XCVR_CNTL_REG_ADDR_BIT_L 2
+#define XCVR_CNTL_REG_ADDR_BIT_H 5
+#define XCVR_CNTL_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET    0x004
+#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET    0x008
+#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET    0x01c
+#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET    0x020
+#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET    0x024
+#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET    0x00c
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET    0x010
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET    0x014
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET    0x018
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK    0x00020000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT    17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB    17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB    17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK    0x00010000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT    16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB    16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB    16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK    0x00008000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT    15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB    15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB    15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK    0x00004000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT    14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB    14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB    14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK    0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT    13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB    13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB    13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK    0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT    11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB    11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK    0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT    9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB    9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK    0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB    8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK    0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT    7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB    7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK    0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB    6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK    0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT    5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB    5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK    0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT    3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB    3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK    0x00000300
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK    0x000000c0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK    0x00000030
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK    0x0000000c
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK    0x000000f0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK    0x00000003
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK    0x00000f00
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK    0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK    0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK    0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK    0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK    0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK    0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK    0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_XC_AUTO_H */
diff --git a/u-boot/board/sandburst/metrobox/init.S b/u-boot/board/sandburst/metrobox/init.S
new file mode 100644
index 0000000..be3f885
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/init.S
@@ -0,0 +1,54 @@
+/*
+*  Copyright (C) 2005
+*  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+	tlbtab_end
diff --git a/u-boot/board/sandburst/metrobox/metrobox.c b/u-boot/board/sandburst/metrobox/metrobox.c
new file mode 100644
index 0000000..76d8293
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/metrobox.c
@@ -0,0 +1,583 @@
+/*
+ *  Copyright (c) 2005
+ *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "metrobox.h"
+#include "metrobox_version.h"
+#include <timestamp.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/ppc440gx_i2c.h"
+#include "../common/sb_common.h"
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+#include <net.h>
+#endif
+
+void fpga_init (void);
+
+METROBOX_BOARD_ID_ST board_id_as[] =
+{	{"Undefined"},			    /* Not specified */
+	{"2x10Gb"},			    /* 2 ports, 10 GbE */
+	{"20x1Gb"},			    /* 20 ports, 1 GbE */
+	{"Reserved"},			     /* Reserved for future use */
+};
+
+/*************************************************************************
+ *  board_early_init_f
+ *
+ *  Setup chip selects, initialize the Opto-FPGA, initialize
+ *  interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	/* Enable GPIO interrupts */
+	mtsdr(SDR0_PFC0, 0x00103E00);
+
+	/* Setup access for LEDs, and system topology info */
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
+	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
+
+	/* Turn on all the leds for now */
+	gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+	/*--------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------*/
+	mtebc(EBC0_CFG,
+	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
+	      EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------+
+	  | 1/2 MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB0AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+	/*--------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB1AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(PB2AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | OPTO & OFEM FPGA. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB3AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | MAC A for metrobox
+	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
+	  | Initialize bank 4 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB4AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Metrobox MAC B  Initialize bank 5 with default values.
+	  | KA REF FPGA	 Initialize bank 5 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB5AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(PB6AP,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | BME-32. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(PB7AP,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 +-------------------------------------------------------------------*/
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000000);	/* all non- critical */
+	mtdcr (UIC1PR, 0xfffffe03);	/* polarity */
+	mtdcr (UIC1TR, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffc8ff);	/* polarity */
+	mtdcr (UIC2TR, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffff83ff);	/* polarity */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all */
+	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000);
+	mtdcr (UIC0TR, 0x00000000);
+	mtdcr (UIC0VR, 0x00000001);
+
+	fpga_init();
+
+	return 0;
+}
+
+/*************************************************************************
+ *  checkboard
+ *
+ *  Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	unsigned char brd_rev, brd_id;
+	unsigned short sernum;
+	unsigned char opto_rev, opto_id;
+	OPTO_FPGA_REGS_ST *opto_ps;
+
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
+
+	opto_rev = (unsigned char)((opto_ps->revision_ul &
+				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+	opto_id = (unsigned char)((opto_ps->revision_ul &
+				   SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
+				  >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
+
+	brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
+				   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
+				  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
+
+	brd_id = (unsigned char)((opto_ps->boardinfo_ul &
+				  SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
+				 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
+
+	get_sys_info (&sysinfo);
+
+	sernum = sbcommon_get_serial_number();
+	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
+	printf ("%s\n", METROBOX_U_BOOT_REL_STR);
+
+	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
+	if (sbcommon_get_master()) {
+		printf("Slot 0 - Master\nSlave board");
+		if (sbcommon_secondary_present())
+			printf(" present\n");
+		else
+			printf(" not detected\n");
+	} else {
+		printf("Slot 1 - Slave\n\n");
+	}
+
+	printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
+	printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);
+
+	/* Fix the ack in the bme 32 */
+	udelay(5000);
+	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
+	asm("eieio");
+
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_f
+ *
+ *  Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+	/* Turn on i2c bus 1 */
+	puts ("I2C1:  ");
+	i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	puts ("ready\n");
+
+	/* Turn on fans */
+	sbcommon_fans();
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_r
+ *
+ *  Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+	unsigned short sernum;
+	char envstr[255];
+	uchar enetaddr[6];
+	unsigned char opto_rev;
+	OPTO_FPGA_REGS_ST *opto_ps;
+
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
+
+	if(NULL != getenv("secondserial")) {
+	    puts("secondserial is set, switching to second serial port\n");
+	    setenv("stderr", "serial1");
+	    setenv("stdout", "serial1");
+	    setenv("stdin", "serial1");
+	}
+
+	setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
+
+	memset(envstr, 0, 255);
+	sprintf (envstr, "Built %s %s by %s",
+		 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
+	setenv("bldstr", envstr);
+	saveenv();
+
+	if( getenv("autorecover")) {
+		setenv("autorecover", NULL);
+		saveenv();
+		sernum = sbcommon_get_serial_number();
+
+		printf("\nSetting up environment for automatic filesystem recovery\n");
+		/*
+		 * Setup default bootargs
+		 */
+		memset(envstr, 0, 255);
+		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+			"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+			sernum, sernum);
+		setenv("bootargs", envstr);
+
+		/*
+		 * Setup Default boot command
+		 */
+		setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+		       "fatload ide 0 8100000 pramdisk;"
+		       "bootm 8000000 8100000");
+
+		printf("Done.  Please type allow the system to continue to boot\n");
+	}
+
+	if( getenv("fakeled")) {
+		setenv("bootdelay", "-1");
+		saveenv();
+		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+		opto_rev = (unsigned char)((opto_ps->revision_ul &
+					    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+					   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+		if(0x12 <= opto_rev) {
+			opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
+		}
+	}
+
+#ifdef CONFIG_HAS_ETH0
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(0, enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+	if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+		board_get_enetaddr(1, enetaddr);
+		eth_setenv_enetaddr("eth1addr", enetaddr);
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH2
+	if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
+		board_get_enetaddr(2, enetaddr);
+		eth_setenv_enetaddr("eth2addr", enetaddr);
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH3
+	if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
+		board_get_enetaddr(3, enetaddr);
+		eth_setenv_enetaddr("eth3addr", enetaddr);
+	}
+#endif
+
+	return (0);
+}
+
+/*************************************************************************
+ *  ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	OPTO_FPGA_REGS_ST *opto_ps;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
+
+	if (on) {		/* assert RESET */
+	    opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+	} else {		/* release RESET */
+	    opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ *  fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+	OPTO_FPGA_REGS_ST *opto_ps;
+	unsigned char opto_rev;
+	unsigned long tmp;
+
+	/* Ensure we have power all around */
+	udelay(500);
+
+	/*
+	 * Take appropriate hw bits out of reset
+	 */
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
+
+	tmp =
+	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
+	opto_ps->reset_ul = tmp;
+	/*
+	 * Turn on the 'Slow Blink' for the System Error Led.
+	 * Ensure FPGA rev is up to at least rev 0x12
+	 */
+	opto_rev = (unsigned char)((opto_ps->revision_ul &
+				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+	if(0x12 <= opto_rev) {
+	    opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
+	}
+
+	asm("eieio");
+
+	return;
+}
+
+int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	memset(envstr, 0, 255);
+	/*
+	 * Setup our ip address
+	 */
+	sprintf(envstr, "10.100.60.%d", sernum);
+
+	setenv("ipaddr", envstr);
+	/*
+	 * Setup the host ip address
+	 */
+	setenv("serverip", "10.100.17.10");
+
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+		"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
+		"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
+		":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
+		sernum, sernum, sernum);
+
+	setenv("bootargs_nfs", envstr);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup CF bootargs
+	 */
+	memset(envstr, 0, 255);
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+		sernum, sernum);
+
+	setenv("bootargs_cf", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
+	setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
+
+	/*
+	 * Setup compact flash boot command
+	 */
+	setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
+
+	saveenv();
+
+
+	return(1);
+}
+
+int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	printf("\nSetting up environment for filesystem recovery\n");
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
+		sernum, sernum);
+
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+	       "fatload ide 0 8100000 pramdisk;"
+	       "bootm 8000000 8100000");
+
+	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
+	       " please type fsrecover.sh<cr>\n");
+
+	return(1);
+}
+
+U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
+	   "Set environment to factory defaults", "");
+
+U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
+	   "Set environment to allow for fs recovery", "");
diff --git a/u-boot/board/sandburst/metrobox/metrobox.h b/u-boot/board/sandburst/metrobox/metrobox.h
new file mode 100644
index 0000000..3f28f00
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/metrobox.h
@@ -0,0 +1,45 @@
+#ifndef __METROBOX_H__
+#define __METROBOX_H__
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct metrobox_board_id_s {
+	const char name[40];
+} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
+
+
+/* Metrobox Opto-FPGA registers and definitions */
+#include "hal_xc_auto.h"
+typedef struct opto_fpga_regs_s {
+	volatile unsigned long revision_ul;	/* Read Only  */
+	volatile unsigned long reset_ul;	/* Read/Write */
+	volatile unsigned long status_ul;	/* Read Only  */
+	volatile unsigned long interrupt_ul;	/* Read Only  */
+	volatile unsigned long mask_ul;	/* Read/Write */
+	volatile unsigned long scratch_ul;	/* Read/Write */
+	volatile unsigned long scrmask_ul;	/* Read/Write */
+	volatile unsigned long control_ul;	/* Read/Write */
+	volatile unsigned long boardinfo_ul;	/* Read Only  */
+} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
+
+#endif /* __METROBOX_H__ */
diff --git a/u-boot/board/sandburst/metrobox/metrobox_version.h b/u-boot/board/sandburst/metrobox/metrobox_version.h
new file mode 100644
index 0000000..1b6fee5
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/metrobox_version.h
@@ -0,0 +1,27 @@
+#ifndef _METROBOX_VERSION_H_
+#define _METROBOX_VERSION_H_
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
+
+#endif
diff --git a/u-boot/board/sandburst/metrobox/u-boot.lds.debug b/u-boot/board/sandburst/metrobox/u-boot.lds.debug
new file mode 100644
index 0000000..2fb3ad9
--- /dev/null
+++ b/u-boot/board/sandburst/metrobox/u-boot.lds.debug
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/sandburst/metrobox/init.o (.text)
+    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
+    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
+    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
+    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
+    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
+    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
+    drivers/net/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+    lib/zlib.o		(.text)
+
+/*    common/env_embedded.o(.text) */
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/sandpoint/Makefile b/u-boot/board/sandpoint/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/sandpoint/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sandpoint/README b/u-boot/board/sandpoint/README
new file mode 100644
index 0000000..9e48168
--- /dev/null
+++ b/u-boot/board/sandpoint/README
@@ -0,0 +1,15 @@
+This port of U-Boot will run on a Motorola Sandpoint 3 development
+system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a
+snapshot of work in progress and far from being completed. In order
+to run it on the target system, it has to be downloaded using the
+DINK32 monitor program that came with your Sandpoint system. Please
+note that DINK32 does not accept the S-Record file created by the
+U-Boot build process unmodified, because it contains CR/LF line
+terminators. You have to strip the CR characters first. There is a
+tiny script named 'dinkdl' I created for this purpose.
+
+The Sandpoint port is based on the work of Rob Taylor, who does not
+seem to maintain it any more. I can be reached by mail as
+tkoeller@gmx.net.
+
+Thomas Koeller
diff --git a/u-boot/board/sandpoint/dinkdl b/u-boot/board/sandpoint/dinkdl
new file mode 100644
index 0000000..f281452
--- /dev/null
+++ b/u-boot/board/sandpoint/dinkdl
@@ -0,0 +1,2 @@
+#! /bin/bash
+tr -d "\r" <$1 >/dev/tts/1
diff --git a/u-boot/board/sandpoint/early_init.S b/u-boot/board/sandpoint/early_init.S
new file mode 100644
index 0000000..61b4b55
--- /dev/null
+++ b/u-boot/board/sandpoint/early_init.S
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
+		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CONFIG_SYS_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr
diff --git a/u-boot/board/sandpoint/flash.c b/u-boot/board/sandpoint/flash.c
new file mode 100644
index 0000000..e366cc6
--- /dev/null
+++ b/u-boot/board/sandpoint/flash.c
@@ -0,0 +1,764 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <w83c553f.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#if 0
+static void flash_get_offsets (ulong base, flash_info_t *info);
+#endif /* 0 */
+
+/*flash command address offsets*/
+
+#if 0
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+#else
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+#endif
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+#if 0
+static int byte_parity_odd(unsigned char x) __attribute__ ((const));
+#endif /* 0 */
+static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
+
+typedef struct
+{
+  FLASH_WORD_SIZE extval;
+  unsigned short intval;
+} map_entry;
+
+#if 0
+static int
+byte_parity_odd(unsigned char x)
+{
+  x ^= x >> 4;
+  x ^= x >> 2;
+  x ^= x >> 1;
+  return (x & 0x1) != 0;
+}
+#endif /* 0 */
+
+
+static unsigned long
+flash_id(unsigned char mfct, unsigned char chip)
+{
+  static const map_entry mfct_map[] =
+    {
+      {(FLASH_WORD_SIZE) AMD_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+      {(FLASH_WORD_SIZE) FUJ_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+      {(FLASH_WORD_SIZE) STM_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+      {(FLASH_WORD_SIZE) MT_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+      {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+      {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+    };
+
+  static const map_entry chip_map[] =
+  {
+    {AMD_ID_F040B,	FLASH_AM040},
+    {(FLASH_WORD_SIZE) STM_ID_x800AB,	FLASH_STM800AB}
+  };
+
+  const map_entry *p;
+  unsigned long result = FLASH_UNKNOWN;
+
+  /* find chip id */
+  for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+    if(p->extval == chip)
+    {
+      result = FLASH_VENDMASK | p->intval;
+      break;
+    }
+
+  /* find vendor id */
+  for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+    if(p->extval == mfct)
+    {
+      result &= ~FLASH_VENDMASK;
+      result |= (unsigned long) p->intval << 16;
+      break;
+    }
+
+  return result;
+}
+
+
+unsigned long
+flash_init(void)
+{
+  unsigned long i;
+  unsigned char j;
+  static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
+
+  /* Init: no FLASHes known */
+  for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+  {
+    flash_info_t * const pflinfo = &flash_info[i];
+    pflinfo->flash_id = FLASH_UNKNOWN;
+    pflinfo->size = 0;
+    pflinfo->sector_count = 0;
+  }
+
+  /* Enable writes to Sandpoint flash */
+  {
+    register unsigned char temp;
+    CONFIG_READ_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
+    temp &= ~0x20; /* clear BIOSWP bit */
+    CONFIG_WRITE_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
+  }
+
+  for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++)
+  {
+    flash_info_t * const pflinfo = &flash_info[i];
+    const unsigned long base_address = flash_banks[i];
+    volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
+#if 0
+    volatile FLASH_WORD_SIZE * addr2;
+#endif
+#if 0
+    /* write autoselect sequence */
+    flash[0x5555] = 0xaa;
+    flash[0x2aaa] = 0x55;
+    flash[0x5555] = 0x90;
+#else
+    flash[0xAAA << (3 * i)] = 0xaa;
+    flash[0x555 << (3 * i)] = 0x55;
+    flash[0xAAA << (3 * i)] = 0x90;
+#endif
+    __asm__ __volatile__("sync");
+
+#if 0
+    pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
+#else
+    pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]);
+#endif
+
+    switch(pflinfo->flash_id & FLASH_TYPEMASK)
+    {
+      case FLASH_AM040:
+	pflinfo->size = 0x00080000;
+	pflinfo->sector_count = 8;
+	for(j = 0; j < 8; j++)
+	{
+	  pflinfo->start[j] = base_address + 0x00010000 * j;
+	  pflinfo->protect[j] = flash[(j << 16) | 0x2];
+	}
+	break;
+      case FLASH_STM800AB:
+	pflinfo->size = 0x00100000;
+	pflinfo->sector_count = 19;
+	pflinfo->start[0] = base_address;
+	pflinfo->start[1] = base_address + 0x4000;
+	pflinfo->start[2] = base_address + 0x6000;
+	pflinfo->start[3] = base_address + 0x8000;
+	for(j = 1; j < 16; j++)
+	{
+	  pflinfo->start[j+3] = base_address + 0x00010000 * j;
+	}
+#if 0
+	/* check for protected sectors */
+	for (j = 0; j < pflinfo->sector_count; j++) {
+	  /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	  /* D0 = 1 if protected */
+	  addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]);
+	    if (pflinfo->flash_id & FLASH_MAN_SST)
+	      pflinfo->protect[j] = 0;
+	    else
+	      pflinfo->protect[j] = addr2[2] & 1;
+	}
+#endif
+	break;
+    }
+    /* Protect monitor and environment sectors
+     */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		CONFIG_SYS_MONITOR_BASE,
+		CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		&flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+    flash_protect(FLAG_PROTECT_SET,
+		CONFIG_ENV_ADDR,
+		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		&flash_info[0]);
+#endif
+
+    /* reset device to read mode */
+    flash[0x0000] = 0xf0;
+    __asm__ __volatile__("sync");
+  }
+
+    return flash_info[0].size + flash_info[1].size;
+}
+
+#if 0
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+    int i;
+
+    /* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST)
+	  {
+	    for (i = 0; i < info->sector_count; i++)
+	      info->start[i] = base + (i * 0x00010000);
+	  }
+	else
+    if (info->flash_id & FLASH_BTYPE) {
+	/* set sector offsets for bottom boot block type    */
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
+    } else {
+	/* set sector offsets for top boot block type       */
+	i = info->sector_count - 1;
+	info->start[i--] = base + info->size - 0x00004000;
+	info->start[i--] = base + info->size - 0x00006000;
+	info->start[i--] = base + info->size - 0x00008000;
+	for (; i >= 0; i--) {
+	    info->start[i] = base + i * 0x00010000;
+	}
+    }
+
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t *info)
+{
+  static const char unk[] = "Unknown";
+  const char *mfct = unk, *type = unk;
+  unsigned int i;
+
+  if(info->flash_id != FLASH_UNKNOWN)
+  {
+    switch(info->flash_id & FLASH_VENDMASK)
+    {
+      case FLASH_MAN_AMD:	mfct = "AMD";				break;
+      case FLASH_MAN_FUJ:	mfct = "FUJITSU";			break;
+      case FLASH_MAN_STM:	mfct = "STM";				break;
+      case FLASH_MAN_SST:	mfct = "SST";				break;
+      case FLASH_MAN_BM:	mfct = "Bright Microelectonics";	break;
+      case FLASH_MAN_INTEL:	mfct = "Intel";				break;
+    }
+
+    switch(info->flash_id & FLASH_TYPEMASK)
+    {
+      case FLASH_AM040:		type = "AM29F040B (512K * 8, uniform sector size)";	break;
+      case FLASH_AM400B:	type = "AM29LV400B (4 Mbit, bottom boot sect)";		break;
+      case FLASH_AM400T:	type = "AM29LV400T (4 Mbit, top boot sector)";		break;
+      case FLASH_AM800B:	type = "AM29LV800B (8 Mbit, bottom boot sect)";		break;
+      case FLASH_AM800T:	type = "AM29LV800T (8 Mbit, top boot sector)";		break;
+      case FLASH_AM160T:	type = "AM29LV160T (16 Mbit, top boot sector)";		break;
+      case FLASH_AM320B:	type = "AM29LV320B (32 Mbit, bottom boot sect)";	break;
+      case FLASH_AM320T:	type = "AM29LV320T (32 Mbit, top boot sector)";		break;
+      case FLASH_STM800AB:	type = "M29W800AB (8 Mbit, bottom boot sect)";		break;
+      case FLASH_SST800A:	type = "SST39LF/VF800 (8 Mbit, uniform sector size)";	break;
+      case FLASH_SST160A:	type = "SST39LF/VF160 (16 Mbit, uniform sector size)";	break;
+    }
+  }
+
+  printf(
+    "\n  Brand: %s Type: %s\n"
+    "  Size: %lu KB in %d Sectors\n",
+    mfct,
+    type,
+    info->size >> 10,
+    info->sector_count
+  );
+
+  printf ("  Sector Start Addresses:");
+
+  for (i = 0; i < info->sector_count; i++)
+  {
+    unsigned long size;
+    unsigned int erased;
+    unsigned long * flash = (unsigned long *) info->start[i];
+
+    /*
+     * Check if whole sector is erased
+     */
+    size =
+      (i != (info->sector_count - 1)) ?
+      (info->start[i + 1] - info->start[i]) >> 2 :
+      (info->start[0] + info->size - info->start[i]) >> 2;
+
+    for(
+      flash = (unsigned long *) info->start[i], erased = 1;
+      (flash != (unsigned long *) info->start[i] + size) && erased;
+      flash++
+    )
+      erased = *flash == ~0x0UL;
+
+    printf(
+      "%s %08lX %s %s",
+      (i % 5) ? "" : "\n   ",
+      info->start[i],
+      erased ? "E" : " ",
+      info->protect[i] ? "RO" : "  "
+    );
+  }
+
+  puts("\n");
+  return;
+}
+
+#if 0
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong
+flash_get_size (vu_long *addr, flash_info_t *info)
+{
+   short i;
+    FLASH_WORD_SIZE value;
+    ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+    printf("flash_get_size: \n");
+    /* Write auto select command: read Manufacturer ID */
+    eieio();
+    addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA;
+    addr2[ADDR1] = (FLASH_WORD_SIZE)0x55;
+    addr2[ADDR0] = (FLASH_WORD_SIZE)0x90;
+    value = addr2[0];
+
+    switch (value) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+	info->flash_id = FLASH_MAN_FUJ;
+	break;
+    case (FLASH_WORD_SIZE)SST_MANUFACT:
+	info->flash_id = FLASH_MAN_SST;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+    printf("recognised manufacturer");
+
+    value = addr2[ADDR3];          /* device ID        */
+	debug ("\ndev_code=%x\n", value);
+
+    switch (value) {
+    case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+	info->flash_id += FLASH_AM400T;
+	info->sector_count = 11;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB        */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+	info->flash_id += FLASH_AM400B;
+	info->sector_count = 11;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB        */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+	info->flash_id += FLASH_AM800T;
+	info->sector_count = 19;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+	info->flash_id += FLASH_AM800B;
+	info->sector_count = 19;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+	info->flash_id += FLASH_AM160T;
+	info->sector_count = 35;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+	info->flash_id += FLASH_AM160B;
+	info->sector_count = 35;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)SST_ID_xF800A:
+	info->flash_id += FLASH_SST800A;
+	info->sector_count = 16;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
+
+    case (FLASH_WORD_SIZE)SST_ID_xF160A:
+	info->flash_id += FLASH_SST160A;
+	info->sector_count = 32;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id += FLASH_AM040;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+    printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size);
+    /* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST)
+	  {
+	    for (i = 0; i < info->sector_count; i++)
+	      info->start[i] = base + (i * 0x00010000);
+	  }
+	else
+    if (info->flash_id & FLASH_BTYPE) {
+	/* set sector offsets for bottom boot block type    */
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
+    } else {
+	/* set sector offsets for top boot block type       */
+	i = info->sector_count - 1;
+	info->start[i--] = base + info->size - 0x00004000;
+	info->start[i--] = base + info->size - 0x00006000;
+	info->start[i--] = base + info->size - 0x00008000;
+	for (; i >= 0; i--) {
+	    info->start[i] = base + i * 0x00010000;
+	}
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if (info->flash_id & FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+       addr2 = (FLASH_WORD_SIZE *)info->start[0];
+	*addr2 = (FLASH_WORD_SIZE)0x00F000F0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+#endif
+
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    unsigned char sh8b;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Check the ROM CS */
+    if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
+      sh8b = 3;
+    else
+      sh8b = 0;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+				(info->start[sect] - info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST)
+			  {
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+			    addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			    udelay(30000);  /* wait 30 ms */
+			  }
+			else
+			  addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+			(info->start[l_sect] - info->start[0]) << sh8b));
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+    unsigned char sh8b;
+
+    /* Check the ROM CS */
+    if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
+      sh8b = 3;
+    else
+      sh8b = 0;
+
+    dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
+				info->start[0]);
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i << sh8b] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/sandpoint/sandpoint.c b/u-boot/board/sandpoint/sandpoint.c
new file mode 100644
index 0000000..bb01d73
--- /dev/null
+++ b/u-boot/board/sandpoint/sandpoint.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <netdev.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Sandpoint "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" Unity ##Test not implemented yet##\n");
+	return 0;
+}
+
+#if 0	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+phys_size_t initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/sandpoint/speed.h b/u-boot/board/sandpoint/speed.h
new file mode 100644
index 0000000..3f32a14
--- /dev/null
+++ b/u-boot/board/sandpoint/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK			CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/u-boot/board/sandpoint/u-boot.lds b/u-boot/board/sandpoint/u-boot.lds
new file mode 100644
index 0000000..59c8627
--- /dev/null
+++ b/u-boot/board/sandpoint/u-boot.lds
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2001-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc824x/start.o	(.text*)
+    *(.text.v*printf)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv*)
+
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/sbc2410x/Makefile b/u-boot/board/sbc2410x/Makefile
new file mode 100644
index 0000000..2b3b781
--- /dev/null
+++ b/u-boot/board/sbc2410x/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sbc2410x.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc2410x/config.mk b/u-boot/board/sbc2410x/config.mk
new file mode 100644
index 0000000..bc01a2d
--- /dev/null
+++ b/u-boot/board/sbc2410x/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SMDK2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+
+CONFIG_SYS_TEXT_BASE = 0x33F80000
diff --git a/u-boot/board/sbc2410x/flash.c b/u-boot/board/sbc2410x/flash.c
new file mode 100644
index 0000000..abb0935
--- /dev/null
+++ b/u-boot/board/sbc2410x/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define CMD_READ_ARRAY		0x000000F0
+#define CMD_UNLOCK1		0x000000AA
+#define CMD_UNLOCK2		0x00000055
+#define CMD_ERASE_SETUP		0x00000080
+#define CMD_ERASE_CONFIRM	0x00000030
+#define CMD_PROGRAM		0x000000A0
+#define CMD_UNLOCK_BYPASS	0x00000020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE		0x00000080
+#define BIT_RDY_MASK		0x00000080
+#define BIT_PROGRAM_ERROR	0x00000020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+			flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 3) {
+				/* 1st one is 16 KB */
+				if (j == 0) {
+					flash_info[i].start[j] =
+						flashbase + 0;
+				}
+
+				/* 2nd and 3rd are both 8 KB */
+				if ((j == 1) || (j == 2)) {
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + (j -
+								      1) *
+						0x2000;
+				}
+
+				/* 4th 32 KB */
+				if (j == 3) {
+					flash_info[i].start[j] =
+						flashbase + 0x8000;
+				}
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 3) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV400B & FLASH_TYPEMASK):
+		printf ("1x Amd29LV400BB (4Mbit)\n");
+		break;
+	case (AMD_ID_LV800B & FLASH_TYPEMASK):
+		printf ("1x Amd29LV800BB (8Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ushort result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () >
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip = TMO;
+					break;
+				}
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip = READY;
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip = ERR;
+
+			} while (!chip);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest;
+	ushort result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			chip = ERR | TMO;
+			break;
+		}
+		if (!chip && ((result & 0x80) == (data & 0x80)))
+			chip = READY;
+
+		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip = READY;
+			else
+				chip = ERR;
+		}
+
+	} while (!chip);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	int l;
+	int i, rc;
+	ushort data;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_hword (info, wp, data);
+}
diff --git a/u-boot/board/sbc2410x/lowlevel_init.S b/u-boot/board/sbc2410x/lowlevel_init.S
new file mode 100644
index 0000000..3de9166
--- /dev/null
+++ b/u-boot/board/sbc2410x/lowlevel_init.S
@@ -0,0 +1,163 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/*
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
+ */
+
+#define BWSCON	0x48000000
+
+/* BWSCON */
+#define DW8			(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
+
+#define B1_BWSCON		(DW16)
+#define B2_BWSCON		(DW16)
+#define B3_BWSCON		(DW16 + WAIT + UBLB)
+#define B4_BWSCON		(DW16)
+#define B5_BWSCON		(DW16)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
+
+#define B0_Tacs			0x0
+#define B0_Tcos			0x0
+#define B0_Tacc			0x7
+#define B0_Tcoh			0x0
+#define B0_Tah			0x0
+#define B0_Tacp			0x0
+#define B0_PMC			0x0
+
+#define B1_Tacs			0x0
+#define B1_Tcos			0x0
+#define B1_Tacc			0x7
+#define B1_Tcoh			0x0
+#define B1_Tah			0x0
+#define B1_Tacp			0x0
+#define B1_PMC			0x0
+
+#define B2_Tacs			0x0
+#define B2_Tcos			0x0
+#define B2_Tacc			0x7
+#define B2_Tcoh			0x0
+#define B2_Tah			0x0
+#define B2_Tacp			0x0
+#define B2_PMC			0x0
+
+#define B3_Tacs			0xc
+#define B3_Tcos			0x7
+#define B3_Tacc			0xf
+#define B3_Tcoh			0x1
+#define B3_Tah			0x0
+#define B3_Tacp			0x0
+#define B3_PMC			0x0
+
+#define B4_Tacs			0x0
+#define B4_Tcos			0x0
+#define B4_Tacc			0x7
+#define B4_Tcoh			0x0
+#define B4_Tah			0x0
+#define B4_Tacp			0x0
+#define B4_PMC			0x0
+
+#define B5_Tacs			0xc
+#define B5_Tcos			0x7
+#define B5_Tacc			0xf
+#define B5_Tcoh			0x1
+#define B5_Tah			0x0
+#define B5_Tacp			0x0
+#define B5_PMC			0x0
+
+#define B6_MT			0x3	/* SDRAM */
+#define B6_Trcd			0x1
+#define B6_SCAN			0x1	/* 9bit */
+
+#define B7_MT			0x3	/* SDRAM */
+#define B7_Trcd			0x1	/* 3clk */
+#define B7_SCAN			0x1	/* 9bit */
+
+/* REFRESH parameter */
+#define REFEN			0x1	/* Refresh enable */
+#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x0	/* 2clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr			0x2	/* 3clk */
+#define REFCNT			0x0459
+/**************************************/
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #13*4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0xb2
+    .word 0x30
+    .word 0x30
diff --git a/u-boot/board/sbc2410x/sbc2410x.c b/u-boot/board/sbc2410x/sbc2410x.c
new file mode 100644
index 0000000..c82382d
--- /dev/null
+++ b/u-boot/board/sbc2410x/sbc2410x.c
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <linux/mtd/nand.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0x5c
+#define M_PDIV	0x4
+#define M_SDIV	0x0
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	struct s3c24x0_clock_power * const clk_power =
+					s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	clk_power->locktime = 0xFFFFFF;
+
+	/* configure MPLL */
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (4000);
+
+	/* configure UPLL */
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (8000);
+
+	/* set up the I/O ports */
+	gpio->gpacon = 0x007FFFFF;
+	gpio->gpbcon = 0x00044556;
+	gpio->gpbup = 0x000007FF;
+	gpio->gpccon = 0xAAAAAAAA;
+	gpio->gpcup = 0x0000FFFF;
+	gpio->gpdcon = 0xAAAAAAAA;
+	gpio->gpdup = 0x0000FFFF;
+	gpio->gpecon = 0xAAAAAAAA;
+	gpio->gpeup = 0x0000FFFF;
+	gpio->gpfcon = 0x000055AA;
+	gpio->gpfup = 0x000000FF;
+	gpio->gpgcon = 0xFF95FF3A;
+	gpio->gpgup = 0x0000FFFF;
+	gpio->gphcon = 0x0016FAAA;
+	gpio->gphup = 0x000007FF;
+
+	gpio->extint0 = 0x22222222;
+	gpio->extint1 = 0x22222222;
+	gpio->extint2 = 0x22222222;
+
+	/* arch number of SMDK2410-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x30000100;
+
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NAND)
+extern ulong nand_probe(ulong physadr);
+
+static inline void NF_Reset(void)
+{
+	int i;
+
+	NF_SetCE(NFCE_LOW);
+	NF_Cmd(0xFF);		/* reset command */
+	for(i = 0; i < 10; i++);	/* tWB = 100ns. */
+	NF_WaitRB();		/* wait 200~500us; */
+	NF_SetCE(NFCE_HIGH);
+}
+
+static inline void NF_Init(void)
+{
+#if 1
+#define TACLS   0
+#define TWRPH0  3
+#define TWRPH1  0
+#else
+#define TACLS   0
+#define TWRPH0  4
+#define TWRPH1  2
+#endif
+
+	NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
+	/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
+	/* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
+	/* En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1 */
+
+	NF_Reset();
+}
+
+void nand_init(void)
+{
+	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
+
+	NF_Init();
+#ifdef DEBUG
+	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
+#endif
+	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/sbc405/Makefile b/u-boot/board/sbc405/Makefile
new file mode 100644
index 0000000..0f53340
--- /dev/null
+++ b/u-boot/board/sbc405/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o strataflash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc405/sbc405.c b/u-boot/board/sbc405/sbc405.c
new file mode 100644
index 0000000..4efc410
--- /dev/null
+++ b/u-boot/board/sbc405/sbc405.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <spd_sdram.h>
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000);
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming sbc405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 64 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/sbc405/strataflash.c b/u-boot/board/sbc405/strataflash.c
new file mode 100644
index 0000000..e5863d6
--- /dev/null
+++ b/u-boot/board/sbc405/strataflash.c
@@ -0,0 +1,793 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CONFIG_SYS_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CONFIG_SYS_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       - CONFIG_SYS_MONITOR_LEN,
+		       - 1, &flash_info[1]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/u-boot/board/sbc8240/Makefile b/u-boot/board/sbc8240/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/sbc8240/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc8240/README b/u-boot/board/sbc8240/README
new file mode 100644
index 0000000..71595b4
--- /dev/null
+++ b/u-boot/board/sbc8240/README
@@ -0,0 +1,140 @@
+The supported features of the SBC8240/8245 board are:
+    8240 or 8245 processor
+    66MHz & 100MHz bus speed
+    Decrementer timer
+    1 UART channel (Console channel)
+    8240 Interrupt Controller
+    8240 PCI bridge
+    8240 Memory Controller
+    SDRAM (16, 64 MB Memory DIMM)
+    FLASH 512K On board
+    FLASH 4MB On board
+
+
+Memory Map from CPU point of view:
+
+    Start	 Size	Access to
+    -----------------------------------------------------
+    0x00000000	 64MB	SDRAM DIMM
+    0xFF000000	  4MB	On Board FLASH
+    0xFFF00000	512K	On Board FLASH or SRAM (Configured by jumper)
+    0xFFE00000	  8K	EEPROM
+    0xFFE80000	  8Bit	LED
+    0xFFF80000	  8Bit	UART
+
+
+Setting the board Jumpers & Switches:
+
+   In order to get the board running with the default configuration the
+   jumpers need to be set as follows:
+
+  General Jumpers:
+    ____________________________________________
+   |   Jumpers	 |   Jumpers	|    Jumpers	|
+   |-------------|--------------|---------------|
+   |JP1	    1-2	 | JP14	   1-2	| JP27	  1-2	|
+   |JP5	    Open | JP15	   1-2	| JP28	  2-3	|
+   |JP8	    1-2	 | JP16	   1-2	| JP33	  Open	|
+   |JP9	    1-2	 | JP17	   1-2	| JP37	  Close |
+   |JP10    1-2	 | JP18	   1-2	|		|
+   |JP11    2-3	 | JP19	   1-2	|		|
+   |JP12    1-2	 | JP20	   1-2	|		|
+   |JP13    1-2	 | JP25	   Open |		|
+   |_____________|______________|_______________|
+
+  Bus speed Jumpers:
+    _________________________
+   | 100MHz Bus | 66 MHz Bus |
+   |------------|------------|
+   | JP2    1-2 | JP2	 1-2 |
+   | JP3    1-2 | JP3	 2-3 |
+   | JP4    1-2 | JP4	 2-3 |
+   | JP6    1-2 | JP6	 2-3 |
+   | JP7    1-2 | JP7	 1-2 |
+   |____________|____________|
+
+
+U-Boot 1.1.2 (Jun 24 2004 - 17:01:04)
+
+CPU:   MPC8240 Revision 1.1 at 247.500 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: sbc8240 Revision 255 Local Bus at 99 MHz
+DRAM:  64 MB
+FLASH: 512 kB
+	00  11	8086  1229  0200  00
+In:    serial
+Out:   serial
+Err:   serial
+Net:   i82559#0
+
+Welcome to U-Boot for the sbc8240
+
+Type ? or help to get on-line help
+
+Hit any key to stop autoboot:  0
+=> printenv
+bootcmd=version;echo;tftpboot $loadaddr $loadfile;bootvx
+bootdelay=5
+baudrate=9600
+ethaddr=DE:AD:BE:EF:01:01
+ipaddr=192.168.193.102
+preboot=echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type "? or help" to get on-line help;echo
+netmask=255.255.255.248
+clocks_in_mhz=1
+bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei
+ipaddr=192.168.193.102
+loadfile=vxWorks.st
+loadaddr=0x01000000
+net_load=tftpboot $loadaddr $loadfile
+serverip=192.168.193.99
+ethact=i82559#0
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 631/16380 bytes
+=> boot
+
+U-Boot 1.1.2 (Jun 24 2004 - 17:01:04)
+
+Using i82559#0 device
+TFTP from server 192.168.193.99; our IP address is 192.168.193.102
+Filename 'vxWorks.st'.
+Load address: 0x1000000
+Loading: #################################################################
+	 #################################################################
+	 ##############################################################
+done
+Bytes transferred = 979927 (ef3d7 hex)
+## Ethernet MAC address not copied to NV RAM
+Loading .text @ 0x00100000 (758848 bytes)
+Loading .data @ 0x001b9440 (79904 bytes)
+Clearing .bss @ 0x001ccc60 (20288 bytes)
+## Using bootline (@ 0x4200): $fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei
+## Starting vxWorks at 0x00100000 ...
+
+Adding 2845 symbols for standalone.
+
+
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+      ]]]]]]]]]]]  ]]]]	    ]]]]]]]]]]	     ]]		     ]]]]	  (R)
+ ]     ]]]]]]]]]  ]]]]]]     ]]]]]]]]	    ]]		     ]]]]
+ ]]	]]]]]]]	 ]]]]]]]]     ]]]]]] ]	   ]]		     ]]]]
+ ]]]	 ]]]]] ]    ]]]	 ]     ]]]] ]]]	  ]]]]]]]]]  ]]]] ]] ]]]]  ]]	]]]]]
+ ]]]]	  ]]]  ]]    ]	]]]	]] ]]]]] ]]]]]]	  ]] ]]]]]]] ]]]] ]]   ]]]]
+ ]]]]]	   ]  ]]]]     ]]]]]	  ]]]]]]]] ]]]]	  ]] ]]]]    ]]]]]]]	]]]]
+ ]]]]]]	     ]]]]]     ]]]]]]	 ]  ]]]]]  ]]]]	  ]] ]]]]    ]]]]]]]]	 ]]]]
+ ]]]]]]]    ]]]]]  ]	]]]]]]	]    ]]]   ]]]]	  ]] ]]]]    ]]]] ]]]]	  ]]]]
+ ]]]]]]]]  ]]]]]  ]]]	 ]]]]]]]      ]	    ]]]]]]]  ]]]]    ]]]]  ]]]] ]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]	     Development System
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]	   VxWorks version 5.5.1
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]	  KERNEL: WIND version 2.6
+ ]]]]]]]]]]]]]]]]]]]]]]]]]	 Copyright Wind River Systems, Inc., 1984-2003
+
+			       CPU: MPC8240 -- Wind River BSP. SBC8240 Board.  Processor #0.
+			      Memory Size: 0x2000000.  BSP version 1.2/28.
+
+->
diff --git a/u-boot/board/sbc8240/flash.c b/u-boot/board/sbc8240/flash.c
new file mode 100644
index 0000000..a095753
--- /dev/null
+++ b/u-boot/board/sbc8240/flash.c
@@ -0,0 +1,638 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if CONFIG_SYS_MAX_FLASH_BANKS != 1
+#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+
+	/* Init: no FLASHes known */
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	/* Setup offsets */
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM,
+			      FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+			      &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+#if 0				/* enable when device IDs are available */
+	case (FLASH_WORD_SIZE) AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#endif
+	case (FLASH_WORD_SIZE) SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf ("Erasing sector %p\n", addr2);	/* CLH */
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7 (info, l_sect);
+
+      DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/sbc8240/sbc8240.c b/u-boot/board/sbc8240/sbc8240.c
new file mode 100644
index 0000000..01abe26
--- /dev/null
+++ b/u-boot/board/sbc8240/sbc8240.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <pci.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOARD_REV_REG 0xFE80002B
+
+int checkboard (void)
+{
+	char  revision = *(volatile char *)(BOARD_REV_REG);
+	char  buf[32];
+
+	puts ("Board: sbc8240 ");
+	printf("Revision %d ", revision);
+	printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk));
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1,  mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+#ifdef CONFIG_SYS_LED_BASE
+	*((unsigned char *) (CONFIG_SYS_LED_BASE)) = 0xFF;
+#endif /* CONFIG_SYS_LED_BASE */
+
+	return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/sbc8260/Makefile b/u-boot/board/sbc8260/Makefile
new file mode 100644
index 0000000..f1d86fc
--- /dev/null
+++ b/u-boot/board/sbc8260/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sbc8260.o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc8260/flash.c b/u-boot/board/sbc8260/flash.c
new file mode 100644
index 0000000..645c67f
--- /dev/null
+++ b/u-boot/board/sbc8260/flash.c
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD 29F080B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* for now, only support the 4 MB Flash SIMM */
+    size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+
+    /*
+     * protect monitor and environment sectors
+     */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch ((info->flash_id >> 16) & 0xff) {
+    case 0x1:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F080B:
+	printf ("AM29F080B (8 Mbit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	  printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    vu_long vendor, devid;
+    ulong base = (ulong)addr;
+
+/*    printf("addr   = %08lx\n", (unsigned long)addr); */
+
+    /* Reset and Write auto select command: read Manufacturer ID */
+    addr[0] = 0xf0f0f0f0;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x90909090;
+    udelay (1000);
+
+    vendor = addr[0];
+/*    printf("vendor = %08lx\n", vendor); */
+    if (vendor != 0x01010101) {
+	info->size = 0;
+	goto out;
+    }
+
+    devid = addr[1];
+/*    printf("devid  = %08lx\n", devid); */
+
+    if ((devid & 0xff) == AMD_ID_F080B) {
+	info->flash_id     = (vendor & 0xff) << 16 | AMD_ID_F080B;
+	/* we have 16 sectors with 64KB each x 4 */
+	info->sector_count = 16;
+	info->size         = 4 * info->sector_count * 64*1024;
+    }
+    else {
+	info->size = 0;
+	goto out;
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr = (volatile unsigned long *)(info->start[i]);
+	info->protect[i] = addr[2] & 1;
+    }
+
+    /* reset command */
+    addr = (vu_long *)info->start[0];
+
+out:
+    addr[0] = 0xf0f0f0f0;
+
+    return info->size;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x80808080;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    udelay (100);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while ((addr[0] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0xA0A0A0A0;
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/sbc8260/sbc8260.c b/u-boot/board/sbc8260/sbc8260.c
new file mode 100644
index 0000000..33ce1a4
--- /dev/null
+++ b/u-boot/board/sbc8260/sbc8260.c
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   1,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   1,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   1,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   0,   0,   1,   0,   0   }, /* PB17 */
+	/* PB16 */ {   1,   0,   0,   1,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   0,   0,   1,   0,   0   }, /* PB15 */
+	/* PB14 */ {   1,   0,   0,   1,   0,   0   }, /* PB14 */
+	/* PB13 */ {   1,   0,   0,   1,   0,   0   }, /* PB13 */
+	/* PB12 */ {   1,   0,   0,   1,   0,   0   }, /* PB12 */
+	/* PB11 */ {   1,   0,   0,   1,   0,   0   }, /* PB11 */
+	/* PB10 */ {   1,   0,   0,   1,   0,   0   }, /* PB10 */
+	/* PB9  */ {   1,   0,   0,   1,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   0,   0,   1,   0,   0   }, /* PB8 */
+	/* PB7  */ {   1,   0,   0,   1,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   0,   0,   1,   0,   0   }, /* PB6 */
+	/* PB5  */ {   1,   0,   0,   1,   0,   0   }, /* PB5 */
+	/* PB4  */ {   1,   0,   0,   1,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   1,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   1,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   1,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   1,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   1,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   1,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   1,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   1,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   1,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   1,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   1,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   1,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   1,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   1,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   1,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   1,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   1,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   1,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   1,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   1,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   1,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   0,   0,   1,   0,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   0,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   1,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   1,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   1,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: EST SBC8260\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+	ulong psdmr = CONFIG_SYS_PSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/* return total ram size */
+	return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+#ifdef CONFIG_SYS_LED_BASE
+	uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
+	uchar ss;
+	uchar tmp[64];
+	int res;
+
+	if ((ds != 0) && (ds != 0xff)) {
+		res = getenv_f("ethaddr", tmp, sizeof (tmp));
+		if (res > 0) {
+			ss = ((ds >> 4) & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[15] = ss;
+
+			ss = (ds & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[16] = ss;
+
+			tmp[17] = '\0';
+			setenv ("ethaddr", tmp);
+			/* set the led to show the address */
+			*((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
+		}
+	}
+#endif /* CONFIG_SYS_LED_BASE */
+	return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/u-boot/board/sbc8349/Makefile b/u-boot/board/sbc8349/Makefile
new file mode 100644
index 0000000..24c7b98
--- /dev/null
+++ b/u-boot/board/sbc8349/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (c) 2006 Wind River Systems, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc8349/pci.c b/u-boot/board/sbc8349/pci.c
new file mode 100644
index 0000000..e06874c
--- /dev/null
+++ b/u-boot/board/sbc8349/pci.c
@@ -0,0 +1,88 @@
+/*
+ * pci.c -- WindRiver SBC8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Enable all 8 PCI_CLK_OUTPUTS */
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	mpc83xx_pci_init(1, reg);
+}
diff --git a/u-boot/board/sbc8349/sbc8349.c b/u-boot/board/sbc8349/sbc8349.c
new file mode 100644
index 0000000..50fae7c
--- /dev/null
+++ b/u-boot/board/sbc8349/sbc8349.c
@@ -0,0 +1,242 @@
+/*
+ * sbc8349.c -- WindRiver SBC8349 board support.
+ * Copyright (c) 2006-2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f (void)
+{
+	return 0;
+}
+#endif
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currently any ddr size other than 256 is not supported
+#endif
+	im->ddr.csbnds[2].csbnds = 0x0000000f;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.cs_config[0] = 0;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| SDRAM_CFG_SDRAM_TYPE_DDR1;
+#if defined (CONFIG_DDR_32BIT)
+	/* for 32-bit mode burst length is 8 */
+	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	return msize;
+}
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	puts("Board: Wind River SBC834x\n");
+	return 0;
+}
+
+/*
+ * if board is fitted with SDRAM
+ */
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/* setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733; mode register write operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+	puts("   SDRAM on Local Bus: Disabled in config\n");
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/sbc8548/Makefile b/u-boot/board/sbc8548/Makefile
new file mode 100644
index 0000000..f68ec8d
--- /dev/null
+++ b/u-boot/board/sbc8548/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8548 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc8548/ddr.c b/u-boot/board/sbc8548/ddr.c
new file mode 100644
index 0000000..ab64fa8
--- /dev/null
+++ b/u-boot/board/sbc8548/ddr.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/sbc8548/law.c b/u-boot/board/sbc8548/law.c
new file mode 100644
index 0000000..5fa9db0
--- /dev/null
+++ b/u-boot/board/sbc8548/law.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	0x0fff_ffff	DDR			256M
+ * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M
+ * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M
+ * 0xe000_0000	0xe000_ffff	CCSR			1M
+ * 0xe200_0000	0xe27f_ffff	PCI1 IO			8M
+ * 0xe280_0000	0xe2ff_ffff	PCIe IO			8M
+ * 0xf000_0000	0xf7ff_ffff	SDRAM			128M
+ * 0xf8b0_0000	0xf80f_ffff	EEPROM			1M
+ * 0xfb80_0000	0xff7f_ffff	FLASH (2nd bank)	64M
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M
+ *
+ * Notes:
+ *	CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *	If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
+#endif
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/sbc8548/sbc8548.c b/u-boot/board/sbc8548/sbc8548.c
new file mode 100644
index 0000000..e1a3ea3
--- /dev/null
+++ b/u-boot/board/sbc8548/sbc8548.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
+ *
+ * Copyright 2007 Embedded Specialties, Inc.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <netdev.h>
+#include <tsec.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
+
+	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
+			in_8(rev) >> 4);
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
+	if (clkdiv == 16) {
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+	} else if (clkdiv == 8) {
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+	} else if (clkdiv == 4) {
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+	}
+
+	setbits_be32(&lbc->lcrr, 0x00030000);
+
+	asm("sync;isync;msync");
+
+	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
+	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
+
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	asm("msync");
+
+	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	asm("msync");
+
+	/*
+	 * MPC8548 uses "new" 15-16 style addressing.
+	 */
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define CONFIG_SYS_DDR_CONTROL 0xc300c000
+/*************************************************************************
+ *  fixed_sdram init -- doesn't use serial presence detect.
+ *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ ************************************************************************/
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+	out_be32(&ddr->cs0_bnds, 0x0000007f);
+	out_be32(&ddr->cs1_bnds, 0x008000ff);
+	out_be32(&ddr->cs2_bnds, 0x00000000);
+	out_be32(&ddr->cs3_bnds, 0x00000000);
+	out_be32(&ddr->cs0_config, 0x80010101);
+	out_be32(&ddr->cs1_config, 0x80010101);
+	out_be32(&ddr->cs2_config, 0x00000000);
+	out_be32(&ddr->cs3_config, 0x00000000);
+	out_be32(&ddr->timing_cfg_3, 0x00000000);
+	out_be32(&ddr->timing_cfg_0, 0x00220802);
+	out_be32(&ddr->timing_cfg_1, 0x38377322);
+	out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
+	out_be32(&ddr->sdram_cfg, 0x4300C000);
+	out_be32(&ddr->sdram_cfg_2, 0x24401000);
+	out_be32(&ddr->sdram_mode, 0x23C00542);
+	out_be32(&ddr->sdram_mode_2, 0x00000000);
+	out_be32(&ddr->sdram_interval, 0x05080100);
+	out_be32(&ddr->sdram_md_cntl, 0x00000000);
+	out_be32(&ddr->sdram_data_init, 0x00000000);
+	out_be32(&ddr->sdram_clk_cntl, 0x03800000);
+	asm("sync;isync;msync");
+	udelay(500);
+
+	#if defined (CONFIG_DDR_ECC)
+	  /* Enable ECC checking */
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
+	#else
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	#endif
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif	/* CONFIG_PCI1 */
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 porpllsr = in_be32(&gur->porpllsr);
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */
+
+		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33000000) ? "33" :
+			(pci_speed == 66000000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
+
+	fsl_pcie_init_board(first_free_busno);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	tsec_standard_init(bis);
+	pci_eth_init(bis);
+	return 0;	/* otherwise cpu_eth_init gets run */
+}
+
+int last_stage_init(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_FSL_PCI_INIT
+	FT_FSL_PCI_SETUP;
+#endif
+}
+#endif
diff --git a/u-boot/board/sbc8548/tlb.c b/u-boot/board/sbc8548/tlb.c
new file mode 100644
index 0000000..bb4c052
--- /dev/null
+++ b/u-boot/board/sbc8548/tlb.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	56M	8MB -> 64MB of user flash
+	 * 0xff800000	8M	boot FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
+		      CONFIG_SYS_ALT_FLASH + 0x800000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000	512M	PCIe MEM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLB 2:	64M	Non-cacheable, guarded
+	 * 0xe0000000	1M	CCSRBAR
+	 * 0xe2000000	8M	PCI1 IO
+	 * 0xe2800000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 3:	64M	Cacheable, non-guarded
+	 * 0xf0000000	64M	LBC SDRAM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 3, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 4:	64M	Cacheable, non-guarded
+	 * 0xf4000000	64M	LBC SDRAM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 5:	16M	Cacheable, non-guarded
+	 * 0xf8000000	1M	7-segment LED display
+	 * 0xf8100000	1M	User switches
+	 * 0xf8300000	1M	Board revision
+	 * 0xf8b00000	1M	EEPROM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 6:	4M	Non-cacheable, guarded
+	 * 0xfb800000	4M	1st 4MB block of 64MB user FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_4M, 1),
+
+	/*
+	 * TLB 7:	4M	Non-cacheable, guarded
+	 * 0xfbc00000	4M	2nd 4MB block of 64MB user FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
+		      CONFIG_SYS_ALT_FLASH + 0x400000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_4M, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/sbc8560/Makefile b/u-boot/board/sbc8560/Makefile
new file mode 100644
index 0000000..a402ee4
--- /dev/null
+++ b/u-boot/board/sbc8560/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8560 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc8560/ddr.c b/u-boot/board/sbc8560/ddr.c
new file mode 100644
index 0000000..7850794
--- /dev/null
+++ b/u-boot/board/sbc8560/ddr.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/sbc8560/law.c b/u-boot/board/sbc8560/law.c
new file mode 100644
index 0000000..4e6baed
--- /dev/null
+++ b/u-boot/board/sbc8560/law.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(512M) -or- larger
+ * c000_0000-cfff_ffff: PCI(256M)
+ * d000_0000-dfff_ffff: RapidIO(256M)
+ * e000_0000-ffff_ffff: localbus(512M)
+ *   e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
+ *   e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
+ *   e800_0000-efff_ffff: LBC 128M, nothing here
+ *   f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
+ *   f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
+ *   f800_0000-fdff_ffff: LBC 64M, nothing here
+ *   fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
+ *   fd00_0000-fdff_ffff: LBC 16M, nothing here
+ *   fe00_0000-feff_ffff: LBC 16M, nothing here
+ *   ff00_0000-ff6f_ffff: LBC 7M, nothing here
+ *   ff70_0000-ff7f_ffff: CCSRBAR 1M
+ *   ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/sbc8560/sbc8560.c b/u-boot/board/sbc8560/sbc8560.c
new file mode 100644
index 0000000..c5fe92e
--- /dev/null
+++ b/u-boot/board/sbc8560/sbc8560.c
@@ -0,0 +1,370 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
+	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_PCI)
+    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr[0] &= ~0x20;
+	udelay(2);
+	bcsr[0] |= 0x20;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr[0] &= ~0x10;
+	udelay(2);
+	bcsr[0] |= 0x10;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+
+	get_sys_info (&sysinfo);
+
+#ifdef CONFIG_SBC8560
+	printf ("Board: Wind River SBC8560 Board\n");
+#else
+	printf ("Board: Wind River SBC8540 Board\n");
+#endif
+	printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
+	printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
+	printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
+	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
+		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %s MHz\n",
+			strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+phys_size_t fixed_sdram(void)
+{
+
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000
+
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+#if (CONFIG_SYS_SDRAM_SIZE == 512)
+	ddr->cs0_bnds		= 0x0000000f;
+#else
+	ddr->cs0_bnds		= 0x00000007;
+#endif
+	ddr->cs1_bnds		= 0x0010001f;
+	ddr->cs2_bnds		= 0x00000000;
+	ddr->cs3_bnds		= 0x00000000;
+	ddr->cs0_config		= 0x80000102;
+	ddr->cs1_config		= 0x80000102;
+	ddr->cs2_config		= 0x00000000;
+	ddr->cs3_config		= 0x00000000;
+	ddr->timing_cfg_1	= 0x37334321;
+	ddr->timing_cfg_2	= 0x00000800;
+	ddr->sdram_cfg		= 0x42000000;
+	ddr->sdram_mode		= 0x00000022;
+	ddr->sdram_interval	= 0x05200100;
+	ddr->err_sbe		= 0x00ff0000;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+#ifdef CONFIG_PCI
+	const char *path;
+#endif
+
+	ft_cpu_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/u-boot/board/sbc8560/tlb.c b/u-boot/board/sbc8560/tlb.c
new file mode 100644
index 0000000..fe0ac76
--- /dev/null
+++ b/u-boot/board/sbc8560/tlb.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+/* TLB for CCSRBAR (IMMR) */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+/* TLB for Local Bus stuff, just map the whole 512M */
+/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
+
+	SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_16K, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/sbc8641d/Makefile b/u-boot/board/sbc8641d/Makefile
new file mode 100644
index 0000000..433c132
--- /dev/null
+++ b/u-boot/board/sbc8641d/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sbc8641d/ddr.c b/u-boot/board/sbc8641d/ddr.c
new file mode 100644
index 0000000..23497f9
--- /dev/null
+++ b/u-boot/board/sbc8641d/ddr.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+		if (ctrl_num == 0 && i == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		}
+		if (ctrl_num == 1 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS3;
+		}
+		if (ctrl_num == 1 && i == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS4;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/sbc8641d/law.c b/u-boot/board/sbc8641d/law.c
new file mode 100644
index 0000000..14259d6
--- /dev/null
+++ b/u-boot/board/sbc8641d/law.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW (Local Access Window) configuration:
+ *
+ * 0x0000_0000	DDR			256M
+ * 0x1000_0000	DDR2			256M
+ * 0x8000_0000	PCIE1 MEM		512M
+ * 0xa000_0000	PCIE2 MEM		512M
+ * 0xc000_0000	RapidIO			512M
+ * 0xe200_0000	PCIE1 IO		16M
+ * 0xe300_0000	PCIE2 IO		16M
+ * 0xf800_0000	CCSRBAR			2M
+ * 0xfe00_0000	FLASH (boot bank)	32M
+ *
+ */
+
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+#endif
+	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/sbc8641d/sbc8641d.c b/u-boot/board/sbc8641d/sbc8641d.c
new file mode 100644
index 0000000..5c30b26
--- /dev/null
+++ b/u-boot/board/sbc8641d/sbc8641d.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman joe.hamman@embeddedspecialties.com
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+long int fixed_sdram (void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Wind River SBC8641D\n");
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+	puts ("    DDR: ");
+	return dram_size;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	puts ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	puts ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	puts ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int fixed_sdram (void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
+	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
+	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+
+	asm ("sync;isync");
+
+	udelay (500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
+	asm ("sync; isync");
+
+	udelay (500);
+	ddr = &immap->im_ddr2;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
+	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
+	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
+	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
+	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
+	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
+	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
+	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
+	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
+
+	asm ("sync;isync");
+
+	udelay (500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
+	asm ("sync; isync");
+
+	udelay (500);
+#endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif				/* !defined(CONFIG_SPD_EEPROM) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+}
+#endif
+
+void sbc8641d_reset_board (void)
+{
+	puts ("Resetting board....\n");
+}
+
+/*
+ * get_board_sys_clk
+ *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long get_board_sys_clk (ulong dummy)
+{
+	int i;
+	ulong val = 0;
+
+	i = 5;
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33000000;
+		break;
+	case 1:
+		val = 40000000;
+		break;
+	case 2:
+		val = 50000000;
+		break;
+	case 3:
+		val = 66000000;
+		break;
+	case 4:
+		val = 83000000;
+		break;
+	case 5:
+		val = 100000000;
+		break;
+	case 6:
+		val = 134000000;
+		break;
+	case 7:
+		val = 166000000;
+		break;
+	}
+
+	return val;
+}
+
+void board_reset(void)
+{
+#ifdef CONFIG_SYS_RESET_ADDRESS
+	ulong addr = CONFIG_SYS_RESET_ADDRESS;
+
+	/* flush and disable I/D cache */
+	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
+	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
+	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
+	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("mtspr	1008, 4");
+	__asm__ __volatile__ ("isync");
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("mtspr	1008, 5");
+	__asm__ __volatile__ ("isync");
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * SRR0 has system reset vector, SRR1 has default MSR value
+	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+	 */
+	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
+	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
+	__asm__ __volatile__ ("mtspr	27, 4");
+	__asm__ __volatile__ ("rfi");
+#endif
+}
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/sc3/Makefile b/u-boot/board/sc3/Makefile
new file mode 100644
index 0000000..48f5cf6
--- /dev/null
+++ b/u-boot/board/sc3/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o sc3nand.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sc3/init.S b/u-boot/board/sc3/init.S
new file mode 100644
index 0000000..d374db4
--- /dev/null
+++ b/u-boot/board/sc3/init.S
@@ -0,0 +1,385 @@
+/*------------------------------------------------------------------------------+
+ *
+ *	 This souce code has been made available to you by EuroDesign
+ *	 (www.eurodsn.de). It's based on the original IBM source code, so
+ *	 this follows:
+ *
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.  Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.  No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *------------------------------------------------------------------------------- */
+
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/**
+ * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
+ *
+ * IMPORTANT: For pass1 this code must run from cache since you can not
+ * reliably change a peripheral banks timing register (pbxap) while running
+ * code from that bank. For ex., since we are running from ROM on bank 0, we
+ * can NOT execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Bank 0 - Boot-Flash
+ * Bank 1 - NAND-Flash
+ * Bank 2 - ISA bus
+ * Bank 3 - Second Flash
+ * Bank 4 - USB controller
+ */
+	.globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+/*
+ * We need the current boot up configuration to set correct
+ * timings into internal flash and external flash
+ */
+		mfdcr r24,CPC0_PSR		/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
+						   0 0 -> 8 bit external ROM
+						   0 1 -> 16 bit internal ROM */
+		addi r4,0,2
+		srw r24,r24,r4				/* shift right r24 two positions */
+		andi. r24,r24,0x06000
+/*
+ * All calculations are based on 33MHz EBC clock.
+ *
+ * First, create a "very slow" timing (~250ns) with burst mode enabled
+ * This is need for the external flash access
+ */
+		lis r25,0x0800
+		ori r25,r25,0x0280			/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
+/*
+ * Second, create a fast timing:
+ * 90ns first cycle - 3 clock access
+ * and 90ns burst cycle, plus 1 clock after the last access
+ * This is used for the internal access
+ */
+		lis r26,0x8900
+		ori r26,r26,0x0280			/* 1000 1001 0xxx 0000 0000 0010 100x xxxx
+/*
+ * We can't change settings on CS# if we currently use them.
+ * -> load a few instructions into cache and run this code from cache
+ */
+		mflr r4					/* save link register */
+		bl ..getAddr
+..getAddr:
+		mflr r3					/* get address of ..getAddr */
+		mtlr r4					/* restore link register */
+		addi r4,0,14				/* set ctr to 10; used to prefetch */
+		mtctr r4				/* 10 cache lines to fit this function
+							in cache (gives us 8x10=80 instructions) */
+..ebcloop:
+		icbt r0,r3				/* prefetch cache line for addr in r3 */
+		addi r3,r3,32				/* move to next cache line */
+		bdnz ..ebcloop				/* continue for 10 cache lines */
+/*
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ */
+		lis r3,0x0
+		ori r3,r3,0xA000			/* ensure 200usec have passed since reset */
+		mtctr r3
+..spinlp:
+		bdnz ..spinlp				/* spin loop */
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 0 (BOOT-ROM) initialization
+ * 0xFFEF00000....0xFFFFFFF
+ * We only have to change the timing. Mapping is ok by boot-strapping
+ *----------------------------------------------------------------------- */
+
+		li r4,PB1AP				/* PB0AP=Peripheral Bank 0 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
+
+		mr r4,r26				/* assume internal fast flash is boot flash */
+		cmpwi r24,0x2000			/* assumption true? ... */
+		beq 1f					/* ...yes! */
+		mr r4,r25				/* ...no, use the slow variant */
+		mr r25,r26				/* use this for the other flash */
+1:
+		mtdcr EBC0_CFGDATA,r4			/* change timing now */
+
+		li r4,PB0CR				/* PB0CR=Peripheral Bank 0 Control Register */
+		mtdcr EBC0_CFGADDR,r4
+		mfdcr r4,EBC0_CFGDATA
+		lis r3,0x0001
+		ori r3,r3,0x8000			/* allow reads and writes */
+		or r4,r4,r3
+		mtdcr EBC0_CFGDATA,r4
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 3 (Second-Flash) initialization
+ * 0xF0000000...0xF01FFFFF -> 2MB
+ *----------------------------------------------------------------------- */
+
+		li r4,PB3AP				/* Peripheral Bank 1 Access Parameter */
+		mtdcr EBC0_CFGADDR,r4
+		mtdcr EBC0_CFGDATA,r2			/* change timing */
+
+		li r4,PB3CR				/* Peripheral Bank 1 Configuration Registers */
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0xF003
+		ori r4,r4,0x8000
+/*
+ * Consider boot configuration
+ */
+		xori r24,r24,0x2000			/* invert current bus width */
+		or r4,r4,r24
+		mtdcr EBC0_CFGDATA,r4
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 1 (NAND-Flash) initialization
+ * 0x77D00000...0x77DFFFFF -> 1MB
+ * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
+ * - the setup time is 0ns
+ * - the hold time is 15ns
+ * ->
+ *   - TWT = 0
+ *   - CSN = 0
+ *   - OEN = 0
+ *   - WBN = 0
+ *   - WBF = 0
+ *   - TH  = 1
+ * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
+ *----------------------------------------------------------------------- */
+
+		li r4,PB1AP				/* Peripheral Bank 1 Access Parameter */
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0x0000
+		ori r4,r4,0x0200
+		mtdcr EBC0_CFGDATA,r4
+
+		li r4,PB1CR				/* Peripheral Bank 1 Configuration Registers */
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0x77D1
+		ori r4,r4,0x8000
+		mtdcr EBC0_CFGDATA,r4
+
+
+/* USB init (without acceleration) */
+#ifndef CONFIG_ISP1161_PRESENT
+		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
+		lis r4,0x0180
+		ori r4,r4,0x5940
+		mtdcr EBC0_CFGDATA,r4
+#endif
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
+ * 0x78000000...0x7BFFFFFF -> 64 MB
+ * Wir arbeiten bei 33 MHz -> 30ns
+ *-----------------------------------------------------------------------
+
+ A7 (ppc notation) or A24 (standard notation) decides about
+ the type of access:
+ A7/A24=0 -> memory cycle
+ A7/ /A24=1 -> I/O cycle
+*/
+		li r4,PB2AP				/* PB2AP=Peripheral Bank 2 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
+/*
+ We emulate an ISA access
+
+ 1. Address active
+ 2. wait 0 EBC clocks -> CSN=0
+ 3. set CS#
+ 4. wait 0 EBC clock -> OEN/WBN=0
+ 5. set OE#/WE#
+ 6. wait 4 clocks (ca. 90ns) and for Ready signal
+ 7. hold for 4 clocks -> TH=4
+*/
+
+#if 1
+/* faster access to isa-bus */
+		lis r4,0x0180
+		ori r4,r4,0x5940
+#else
+		lis r4,0x0100
+		ori r4,r4,0x0340
+#endif
+		mtdcr EBC0_CFGDATA,r4
+
+#ifdef IDE_USES_ISA_EMULATION
+		li r25,PB5AP				/* PB5AP=Peripheral Bank 5 Access Parameters */
+		mtdcr EBC0_CFGADDR,r25
+		mtdcr EBC0_CFGDATA,r4
+#endif
+
+		li r25,PB6AP				/* PB6AP=Peripheral Bank 6 Access Parameters */
+		mtdcr EBC0_CFGADDR,r25
+		mtdcr EBC0_CFGDATA,r4
+		li r25,PB7AP				/* PB7AP=Peripheral Bank 7 Access Parameters */
+		mtdcr EBC0_CFGADDR,r25
+		mtdcr EBC0_CFGDATA,r4
+
+		li r25,PB2CR				/* PB2CR=Peripheral Bank 2 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
+
+		lis r4,0x780B
+		ori r4,r4,0xA000
+		mtdcr EBC0_CFGDATA,r4
+/*
+ * the other areas are only 1MiB in size
+ */
+		lis r4,0x7401
+		ori r4,r4,0xA000
+
+		li r25,PB6CR				/* PB6CR=Peripheral Bank 6 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
+		lis r4,0x7401
+		ori r4,r4,0xA000
+		mtdcr EBC0_CFGDATA,r4
+
+		li r25,PB7CR				/* PB7CR=Peripheral Bank 7 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
+		lis r4,0x7411
+		ori r4,r4,0xA000
+		mtdcr EBC0_CFGDATA,r4
+
+#ifndef CONFIG_ISP1161_PRESENT
+		li r25,PB4CR				/* PB4CR=Peripheral Bank 4 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
+		lis r4,0x7421
+		ori r4,r4,0xA000
+		mtdcr EBC0_CFGDATA,r4
+#endif
+#ifdef IDE_USES_ISA_EMULATION
+		li r25,PB5CR				/* PB5CR=Peripheral Bank 5 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
+		lis r4,0x0000
+		ori r4,r4,0x0000
+		mtdcr EBC0_CFGDATA,r4
+#endif
+
+/*-----------------------------------------------------------------------
+ * Memory bank 4: USB controller Philips ISP6111
+ * 0x77C00000 ... 0x77CFFFFF
+ *
+ * The chip is connected to:
+ * - CPU CS#4
+ * - CPU IRQ#2
+ * - CPU DMA 3
+ *
+ * Timing:
+ * - command to first data: 300ns. Software must ensure this timing!
+ * - Write pulse: 26ns
+ * - Read pulse: 33ns
+ * - read cycle time: 150ns
+ * - write cycle time: 140ns
+ *
+ * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
+ *
+ *			  |- 300ns --|
+ *		  |---- 420ns ---|---- 420ns ---| cycle
+ * CS ############:###____#######:###____#######
+ * OE ############:####___#######:####___#######
+ * WE ############:####__########:####__########
+ *
+ * ----> 2 clocks RD/WR pulses: 60ns
+ * ----> CSN: 3 clock, 90ns
+ * ----> OEN: 1 clocks (read cycle)
+ * ----> WBN: 1 clocks (write cycle)
+ * ----> WBE: 2 clocks
+ * ----> TH: 7 clock, 210ns
+ * ----> TWT: 7 clocks
+ *----------------------------------------------------------------------- */
+
+#ifdef CONFIG_ISP1161_PRESENT
+
+		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0x030D
+		ori r4,r4,0x5E80
+		mtdcr EBC0_CFGDATA,r4
+
+		li r4,PB4CR				/* PB2CR=Peripheral Bank 4 Configuration Register */
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0x77C1
+		ori r4,r4,0xA000
+		mtdcr EBC0_CFGDATA,r4
+
+#endif
+
+#ifndef IDE_USES_ISA_EMULATION
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 5 used for IDE access
+ *
+ * Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
+ *  70		165		30		PIO-Mode 0, [ns]
+ *   3		  6		 1		[Cycles] ----> AP=0x040C0200
+ *  50		125		20	   PIO-Mode 1, [ns]
+ *   2		  5		 1		[Cycles] ----> AP=0x03080200
+ *  30		100		15	   PIO-Mode 2, [ns]
+ *   1		  4		 1		[Cycles] ----> AP=0x02040200
+ *  30		 80		10	   PIO-Mode 3, [ns]
+ *   1		  3		 1		[Cycles] ----> AP=0x01840200
+ *  25		 70		10	   PIO-Mode 4, [ns]
+ *   1		  3		 1		[Cycles] ----> AP=0x01840200
+ *
+ *----------------------------------------------------------------------- */
+
+		li r4,PB5AP
+		mtdcr EBC0_CFGADDR,r4
+		lis r4,0x040C
+		ori r4,r4,0x0200
+		mtdcr EBC0_CFGDATA,r4
+
+		li r4,PB5CR			/* PB2CR=Peripheral Bank 2 Configuration Register */
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0x7A01
+		ori r4,r4,0xA000
+		mtdcr EBC0_CFGDATA,r4
+#endif
+/*
+ * External Peripheral Control Register
+ */
+		li r4,EBC0_CFG
+		mtdcr EBC0_CFGADDR,r4
+
+		lis r4,0xB84E
+		ori r4,r4,0xF000
+		mtdcr EBC0_CFGDATA,r4
+/*
+ * drive POST code
+ */
+		lis r4,0x7900
+		ori r4,r4,0x0080
+		li r3,0x0001
+		stb r3,0(r4)			/* 01 -> external bus controller is initialized */
+		nop				/* pass2 DCR errata #8 */
+		blr
diff --git a/u-boot/board/sc3/sc3.c b/u-boot/board/sc3/sc3.c
new file mode 100644
index 0000000..f148ad6
--- /dev/null
+++ b/u-boot/board/sc3/sc3.c
@@ -0,0 +1,787 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
+ *
+ * (C) Copyright 2003
+ * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
+ * Derived from walnut.c
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * $Log:$
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "sc3.h"
+#include <pci.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <netdev.h>
+
+#undef writel
+#undef writeb
+#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+
+/* write only register to configure things in our CPLD */
+#define CPLD_CONTROL_1	0x79000102
+#define CPLD_VERSION	0x79000103
+
+#define	IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
+
+static struct pci_controller hose={0,};
+
+/************************************************************
+ * Standard definition
+ ************************************************************/
+
+/* CPC0_CR0        Function                                 ISA bus
+	-  GPIO0
+	-  GPIO1      -> Output: NAND-Command Latch Enable
+	-  GPIO2      -> Output: NAND Address Latch Enable
+	-  GPIO3      -> IRQ input                               ISA-IRQ #5 (through CPLD)
+	-  GPIO4      -> Output: NAND-Chip Enable
+	-  GPIO5      -> IRQ input                               ISA-IRQ#7 (through CPLD)
+	-  GPIO6      -> IRQ input                               ISA-IRQ#9 (through CPLD)
+	-  GPIO7      -> IRQ input                               ISA-IRQ#10 (through CPLD)
+	-  GPIO8      -> IRQ input                               ISA-IRQ#11 (through CPLD)
+	-  GPIO9      -> IRQ input                               ISA-IRQ#12 (through CPLD)
+	- GPIO10/CS1# -> CS1# NAND                               ISA-CS#0
+	- GPIO11/CS2# -> CS2# ISA emulation                      ISA-CS#1
+	- GPIO12/CS3# -> CS3# 2nd Flash-Bank                     ISA-CS#2 or ISA-CS#7
+	- GPIO13/CS4# -> CS4# USB HC or ISA emulation            ISA-CS#3
+	- GPIO14/CS5# -> CS5# Boosted IDE access                 ISA-CS#4
+	- GPIO15/CS6# -> CS6# ISA emulation                      ISA-CS#5
+	- GPIO16/CS7# -> CS7# ISA emulation                      ISA-CS#6
+	- GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line         ISA-IRQ#3
+	- GPIO18/IRQ1 -> IRQ input                               ISA-IRQ#14
+	- GPIO19/IRQ2 -> IRQ input or USB                        ISA-IRQ#4
+	- GPIO20/IRQ3 -> IRQ input                               PCI-IRQ#D
+	- GPIO21/IRQ4 -> IRQ input                               PCI-IRQ#C
+	- GPIO22/IRQ5 -> IRQ input                               PCI-IRQ#B
+	- GPIO23/IRQ6 -> IRQ input                               PCI-IRQ#A
+	- GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
+*/
+/*
+| CPLD register: io-space at offset 0x102 (write only)
+| 0
+| 1
+| 2 0=CS#4 USB CS#, 1=ISA or GP bus
+| 3
+| 4
+| 5
+| 6 1=enable faster IDE access
+| 7
+*/
+#define USB_CHIP_ENABLE 0x04
+#define IDE_BOOSTING 0x40
+
+/* --------------- USB stuff ------------------------------------- */
+#ifdef CONFIG_ISP1161_PRESENT
+/**
+ * initUsbHost- Initialize the Philips isp1161 HC part if present
+ * @cpldConfig: Pointer to value in write only CPLD register
+ *
+ * Initialize the USB host controller if present and fills the
+ * scratch register to inform the driver about used resources
+ */
+
+static void initUsbHost (unsigned char *cpldConfig)
+{
+	int i;
+	unsigned long usbBase;
+	/*
+	 * Read back where init.S has located the USB chip
+	 */
+	mtdcr (0x012, 0x04);
+	usbBase = mfdcr (0x013);
+	if (!(usbBase & 0x18000))	/* enabled? */
+		return;
+	usbBase &= 0xFFF00000;
+
+	/*
+	 * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
+	 */
+	writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
+
+	/*
+	 * first check: is the controller assembled?
+	 */
+	hcWriteWord (usbBase, 0x5555, HcScratch);
+	if (hcReadWord (usbBase, HcScratch) == 0x5555) {
+		hcWriteWord (usbBase, 0xAAAA, HcScratch);
+		if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
+			if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
+				return;	/* this is not our controller */
+		/*
+		 * try a software reset. This needs up to 10 seconds (see datasheet)
+		 */
+			hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
+			for (i = 1000; i > 0; i--) {	/* loop up to 10 seconds */
+				udelay (10);
+				if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
+					break;
+			}
+
+			if (!i)
+				return;  /* the controller doesn't responding. Broken? */
+		/*
+		 * OK. USB controller is ready. Initialize it in such way the later driver
+		 * can us it (without any knowing about specific implementation)
+		 */
+			hcWriteDWord (usbBase, 0x00000000, HcControl);
+		/*
+		 * disable all interrupt sources. Because we
+		 * don't know where we come from (hard reset, cold start, soft reset...)
+		 */
+			hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
+		/*
+		 * our current setup hardware configuration
+		 * - every port power supply can switched indepently
+		 * - every port can signal overcurrent
+		 * - every port is "outside" and the devices are removeable
+		 */
+			hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
+			hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
+		/*
+		 * don't forget to switch off power supply of each port
+		 * The later running driver can reenable them to find and use
+		 * the (maybe) connected devices.
+		 *
+		 */
+			hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
+			hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
+			hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
+			hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
+			hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
+			hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
+		/*
+		 * controller is present and usable
+		 */
+			*cpldConfig |= USB_CHIP_ENABLE;
+		}
+	}
+}
+#endif
+
+#if defined(CONFIG_START_IDE)
+int board_start_ide(void)
+{
+	if (IS_CAMERON) {
+		puts ("no IDE on cameron board.\n");
+		return 0;
+	}
+	return 1;
+}
+#endif
+
+static int sc3_cameron_init (void)
+{
+	/* Set up the Memory Controller for the CAMERON version */
+	mtebc (PB4AP, 0x01805940);
+	mtebc (PB4CR, 0x7401a000);
+	mtebc (PB5AP, 0x01805940);
+	mtebc (PB5CR, 0x7401a000);
+	mtebc (PB6AP, 0x0);
+	mtebc (PB6CR, 0x0);
+	mtebc (PB7AP, 0x0);
+	mtebc (PB7CR, 0x0);
+	return 0;
+}
+
+void sc3_read_eeprom (void)
+{
+	uchar i2c_buffer[18];
+
+	i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
+	i2c_buffer[9] = 0;
+	setenv ("serial#", (char *)i2c_buffer);
+
+	/* read mac-address from eeprom */
+	i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
+	i2c_buffer[17] = 0;
+	i2c_buffer[16] = i2c_buffer[14];
+	i2c_buffer[15] = i2c_buffer[13];
+	i2c_buffer[14] = ':';
+	i2c_buffer[13] = i2c_buffer[12];
+	i2c_buffer[12] = i2c_buffer[11];
+	i2c_buffer[11] = ':';
+	i2c_buffer[8] = ':';
+	i2c_buffer[5] = ':';
+	i2c_buffer[2] = ':';
+	setenv ("ethaddr", (char *)i2c_buffer);
+}
+
+int board_early_init_f (void)
+{
+	/* write only register to configure things in our CPLD */
+	unsigned char cpldConfig_1=0x00;
+
+/*-------------------------------------------------------------------------+
+| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
+|
+| Note: IRQ 0  UART 0, active high; level sensitive
+|       IRQ 1  UART 1, active high; level sensitive
+|       IRQ 2  IIC, active high; level sensitive
+|       IRQ 3  Ext. master, rising edge, edge sensitive
+|       IRQ 4  PCI, active high; level sensitive
+|       IRQ 5  DMA Channel 0, active high; level sensitive
+|       IRQ 6  DMA Channel 1, active high; level sensitive
+|       IRQ 7  DMA Channel 2, active high; level sensitive
+|       IRQ 8  DMA Channel 3, active high; level sensitive
+|       IRQ 9  Ethernet Wakeup, active high; level sensitive
+|       IRQ 10 MAL System Error (SERR), active high; level sensitive
+|       IRQ 11 MAL Tx End of Buffer, active high; level sensitive
+|       IRQ 12 MAL Rx End of Buffer, active high; level sensitive
+|       IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
+|       IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
+|       IRQ 15 Ethernet, active high; level sensitive
+|       IRQ 16 External PCI SERR, active high; level sensitive
+|       IRQ 17 ECC Correctable Error, active high; level sensitive
+|       IRQ 18 PCI Power Management, active high; level sensitive
+|
+|       IRQ 19 (EXT IRQ7 405GPr only)
+|       IRQ 20 (EXT IRQ8 405GPr only)
+|       IRQ 21 (EXT IRQ9 405GPr only)
+|       IRQ 22 (EXT IRQ10 405GPr only)
+|       IRQ 23 (EXT IRQ11 405GPr only)
+|       IRQ 24 (EXT IRQ12 405GPr only)
+|
+|       IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
+|       IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
+|       IRQ 27 (EXT IRQ 2) USB controller
+|       IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
+|       IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
+|       IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
+|       IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
+|
+| Direct Memory Access Controller Signal Polarities
+|       DRQ0 active high (like ISA)
+|       ACK0 active low (like ISA)
+|       EOT0 active high (like ISA)
+|       DRQ1 active high (like ISA)
+|       ACK1 active low (like ISA)
+|       EOT1 active high (like ISA)
+|       DRQ2 active high (like ISA)
+|       ACK2 active low (like ISA)
+|       EOT2 active high (like ISA)
+|       DRQ3 active high (like ISA)
+|       ACK3 active low (like ISA)
+|       EOT3 active high (like ISA)
+|
++-------------------------------------------------------------------------*/
+
+	writeb (cpldConfig_1, CPLD_CONTROL_1);	/* disable everything in CPLD */
+
+	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
+
+	if (IS_CAMERON) {
+		sc3_cameron_init();
+		mtdcr (0x0B6, 0x18000000);
+		mtdcr (UIC0PR, 0xFFFFFFF0);
+		mtdcr (UIC0TR, 0x10001030);
+	} else {
+		mtdcr (0x0B6, 0x0000000);
+		mtdcr (UIC0PR, 0xFFFFFFE0);
+		mtdcr (UIC0TR, 0x10000020);
+	}
+	mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
+
+	/* setup other implementation specific details */
+	mtdcr (CPC0_ECR, 0x60606000);
+
+	mtdcr (CPC0_CR1, 0x000042C0);
+
+	if (IS_CAMERON) {
+		mtdcr (CPC0_CR0, 0x01380000);
+		/* Setup the GPIOs */
+		writel (0x08008000, 0xEF600700);	/* Output states */
+		writel (0x00000000, 0xEF600718);	/* Open Drain control */
+		writel (0x68098000, 0xEF600704);	/* Output control */
+	} else {
+		mtdcr (CPC0_CR0,0x00080000);
+		/* Setup the GPIOs */
+		writel (0x08000000, 0xEF600700);	/* Output states */
+		writel (0x14000000, 0xEF600718);	/* Open Drain control */
+		writel (0x7C000000, 0xEF600704);	/* Output control */
+	}
+
+	/* Code decompression disabled */
+	mtdcr (DCP0_CFGADDR, KCONF);
+	mtdcr (DCP0_CFGDATA, 0x2B);
+
+	/* CPC0_ER: enable sleep mode of (currently) unused components */
+	/* CPC0_FR: force unused components into sleep mode */
+	mtdcr (CPC0_ER, 0x3F800000);
+	mtdcr (CPC0_FR, 0x14000000);
+
+	/* set PLB priority */
+	mtdcr (PLB0_ACR, 0x08000000);
+
+	/* --------------- DMA stuff ------------------------------------- */
+	mtdcr (0x126, 0x49200000);
+
+#ifndef IDE_USES_ISA_EMULATION
+	cpldConfig_1 |= IDE_BOOSTING;	/* enable faster IDE */
+	/* cpldConfig |= 0x01; */	/* enable 8.33MHz output, if *not* present on your baseboard */
+	writeb (cpldConfig_1, CPLD_CONTROL_1);
+#endif
+
+#ifdef CONFIG_ISP1161_PRESENT
+	initUsbHost (&cpldConfig_1);
+	writeb (cpldConfig_1, CPLD_CONTROL_1);
+#endif
+	/* FIXME: for what must we do this */
+	*(unsigned long *)0x79000080 = 0x0001;
+	return(0);
+}
+
+int misc_init_r (void)
+{
+	char *s1;
+	int i, xilinx_val;
+	volatile char *xilinx_adr;
+	xilinx_adr = (char *)0x79000102;
+
+	*xilinx_adr = 0x00;
+
+/* customer settings ***************************************** */
+/*
+	s1 = getenv ("function");
+	if (s1) {
+		if (!strcmp (s1, "Rosho")) {
+			printf ("function 'Rosho' activated\n");
+			*xilinx_adr = 0x40;
+		}
+		else {
+			printf (">>>>>>>>>> function %s not recognized\n",s1);
+		}
+	}
+*/
+
+/* individual settings ***************************************** */
+	if ((s1 = getenv ("xilinx"))) {
+		i=0;
+		xilinx_val = 0;
+		while (i < 3 && s1[i]) {
+			if (s1[i] >= '0' && s1[i] <= '9')
+				xilinx_val = (xilinx_val << 4) + s1[i] - '0';
+			else
+				if (s1[i] >= 'A' && s1[i] <= 'F')
+					xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
+				else
+					if (s1[i] >= 'a' && s1[i] <= 'f')
+						xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
+					else {
+						xilinx_val = -1;
+						break;
+					}
+			i++;
+		}
+		if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
+			printf ("Xilinx: set to %s\n", s1);
+			*xilinx_adr = (unsigned char) xilinx_val;
+		} else
+			printf ("Xilinx: rejected value %s\n", s1);
+	}
+	return 0;
+}
+
+/* -------------------------------------------------------------------------
+ * printCSConfig
+ *
+ * Print some informations about chips select configurations
+ * Only used while debugging.
+ *
+ * Params:
+ * - No. of CS pin
+ * - AP of this CS
+ * - CR of this CS
+ *
+ * Returns
+ * nothing
+   ------------------------------------------------------------------------- */
+
+#ifdef SC3_DEBUGOUT
+static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
+{
+	const char *bsize[4] = {"8","16","32","?"};
+	const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
+	const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
+
+#define CYCLE 30  /* time of one clock (based on 33MHz) */
+
+	printf("\nCS#%d",reg);
+	if (!(cr & 0x00018000))
+		puts(" unused");
+	else {
+		if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
+			puts(" Address is not multiple of bank size!");
+
+		printf("\n -%s bit device",
+			bsize[(cr & 0x00006000) >> 13]);
+		printf(" at 0x%08lX", cr & 0xFFF00000U);
+		printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
+		printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
+		if (ap & 0x80000000) {
+			printf("\n -Burst device (%luns/%luns)",
+				(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
+				(((ap & 0x03800000) >> 23) + 1) * CYCLE);
+		} else {
+			printf("\n -Non burst device, active cycle %luns",
+				(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
+			printf("\n -Address setup %luns",
+				((ap & 0xC0000) >> 18) * CYCLE);
+			printf("\n -CS active to RD %luns/WR %luns",
+				((ap & 0x30000) >> 16) * CYCLE,
+				((ap & 0xC000) >> 14) * CYCLE);
+			printf("\n -WR to CS inactive %luns",
+				((ap & 0x3000) >> 12) * CYCLE);
+			printf("\n -Hold after access %luns",
+				((ap & 0xE00) >> 9) * CYCLE);
+			printf("\n -Ready is %sabled",
+				ap & 0x100 ? "en" : "dis");
+		}
+	}
+}
+#endif
+
+#ifdef SC3_DEBUGOUT
+
+static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
+				PB5AP, PB6AP, PB7AP};
+static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
+				PB5CR, PB6CR, PB7CR};
+
+static int show_reg (int nr)
+{
+	unsigned long ul1, ul2;
+
+	mtdcr (EBC0_CFGADDR, ap[nr]);
+	ul1 = mfdcr (EBC0_CFGDATA);
+	mtdcr (EBC0_CFGADDR, cr[nr]);
+	ul2 = mfdcr(EBC0_CFGDATA);
+	printCSConfig(nr, ul1, ul2);
+	return 0;
+}
+#endif
+
+int checkboard (void)
+{
+#ifdef SC3_DEBUGOUT
+	unsigned long ul1;
+	int	i;
+
+	for (i = 0; i < 8; i++) {
+		show_reg (i);
+	}
+
+	mtdcr (EBC0_CFGADDR, EBC0_CFG);
+	ul1 = mfdcr (EBC0_CFGDATA);
+
+	puts ("\nGeneral configuration:\n");
+
+	if (ul1 & 0x80000000)
+		printf(" -External Bus is always driven\n");
+
+	if (ul1 & 0x400000)
+		printf(" -CS signals are always driven\n");
+
+	if (ul1 & 0x20000)
+		printf(" -PowerDown after %lu clocks\n",
+			(ul1 & 0x1F000) >> 7);
+
+	switch (ul1 & 0xC0000)
+	{
+	case 0xC0000:
+		printf(" -No external master present\n");
+		break;
+	case 0x00000:
+		printf(" -8 bit external master present\n");
+		break;
+	case 0x40000:
+		printf(" -16 bit external master present\n");
+		break;
+	case 0x80000:
+		printf(" -32 bit external master present\n");
+		break;
+	}
+
+	switch (ul1 & 0x300000)
+	{
+	case 0x300000:
+		printf(" -Prefetch: Illegal setting!\n");
+		break;
+	case 0x000000:
+		printf(" -1 doubleword prefetch\n");
+		break;
+	case 0x100000:
+		printf(" -2 doublewords prefetch\n");
+		break;
+	case 0x200000:
+		printf(" -4 doublewords prefetch\n");
+		break;
+	}
+	putc ('\n');
+#endif
+	printf("Board: SolidCard III %s %s version.\n",
+		(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
+	return 0;
+}
+
+static int printSDRAMConfig(char reg, unsigned long cr)
+{
+	const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
+#ifdef SC3_DEBUGOUT
+	const char *basize[8]=
+		{"4", "8", "16", "32", "64", "128", "256", "Reserved"};
+
+	printf("SDRAM bank %d",reg);
+
+	if (!(cr & 0x01))
+		puts(" disabled\n");
+	else {
+		printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
+		printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
+	}
+#endif
+
+	if (cr & 0x01)
+		return(bisize[(cr & 0xE0000) >> 17]);
+
+	return 0;
+}
+
+#ifdef SC3_DEBUGOUT
+static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
+#endif
+
+phys_size_t initdram (int board_type)
+{
+	unsigned int mems=0;
+	unsigned long ul1;
+
+#ifdef SC3_DEBUGOUT
+	unsigned long ul2;
+	int	i;
+
+	puts("\nSDRAM configuration:\n");
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
+
+	if (!(ul1 & 0x80000000)) {
+		puts(" Controller disabled\n");
+		return 0;
+	}
+	for (i = 0; i < 4; i++) {
+		mtdcr (SDRAM0_CFGADDR, mbcf[i]);
+		ul1 = mfdcr (SDRAM0_CFGDATA);
+		mems += printSDRAMConfig (i, ul1);
+	}
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
+
+	printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
+	printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
+	printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
+	printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
+	printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
+	printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
+	puts ("Misc:\n");
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
+	printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
+
+	mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
+	ul2=mfdcr(SDRAM0_CFGDATA);
+
+	mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
+	ul1=mfdcr(SDRAM0_CFGDATA);
+
+	if (ul1 & 0x20000000)
+		printf(" -Power Down after: %luns\n",
+			((ul2 & 0xFFC00000) >> 22) * 7);
+	else
+		puts(" -Power Down disabled\n");
+
+	if (ul1 & 0x40000000)
+		printf(" -Self refresh feature active\n");
+	else
+		puts(" -Self refresh disabled\n");
+
+	if (ul1 & 0x10000000)
+		puts(" -ECC enabled\n");
+	else
+		puts(" -ECC disabled\n");
+
+	if (ul1 & 0x8000000)
+		puts(" -Using registered SDRAM\n");
+
+	if (!(ul1 & 0x6000000))
+		puts(" -Using 32 bit data width\n");
+	else
+		puts(" -Illegal data width!\n");
+
+	if (ul1 & 0x400000)
+		puts(" -ECC drivers inactive\n");
+	else
+		puts(" -ECC drivers active\n");
+
+	if (ul1 & 0x200000)
+		puts(" -Memory lines always active outputs\n");
+	else
+		puts(" -Memory lines only at write cycles active outputs\n");
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
+	ul1 = mfdcr (SDRAM0_CFGDATA);
+	if (ul1 & 0x80000000)
+		puts(" -SDRAM Controller ready\n");
+	else
+		puts(" -SDRAM Controller not ready\n");
+
+	if (ul1 & 0x4000000)
+		puts(" -SDRAM in self refresh mode!\n");
+
+	return (mems * 1024 * 1024);
+#else
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	ul1 = mfdcr (SDRAM0_CFGDATA);
+	mems = printSDRAMConfig (0, ul1);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	ul1 = mfdcr (SDRAM0_CFGDATA);
+	mems += printSDRAMConfig (1, ul1);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
+	mems += printSDRAMConfig (2, ul1);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
+	mems += printSDRAMConfig (3, ul1);
+
+	return (mems * 1024 * 1024);
+#endif
+}
+
+static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+/*-------------------------------------------------------------------------+
+ |             ,-.     ,-.        ,-.        ,-.        ,-.
+ |   INTD# ----|B|-----|P|-.    ,-|P|-.    ,-| |-.    ,-|G|
+ |             |R|     |C|  \  /  |C|  \  /  |E|  \  /  |r|
+ |   INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
+ |             |D|     |0|  \/    |0|  \/    |h|  \/    |f|
+ |   INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
+ |             |E|     |+| /\     |+| /\     |r| /\     |k|
+ |   INTA# ----| |-----| |-  `----| |-  `----| |-  `----| |
+ |             `-'     `-'        `-'        `-'        `-'
+ |   Slot      0       10         11         12         13
+ |   REQ#              0          1          2          *
+ |   GNT#              0          1          2          *
+ +-------------------------------------------------------------------------*/
+	unsigned char int_line = 0xff;
+
+	switch (PCI_DEV(dev)) {
+	case 10:
+		int_line = 31; /* INT A */
+		POST_OUT(0x42);
+		break;
+
+	case 11:
+		int_line = 30; /* INT B */
+		POST_OUT(0x43);
+		break;
+
+	case 12:
+		int_line = 29; /* INT C */
+		POST_OUT(0x44);
+		break;
+
+	case 13:
+		int_line = 28; /* INT D */
+		POST_OUT(0x45);
+		break;
+	}
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+extern void pci_405gp_init(struct pci_controller *hose);
+extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
+extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
+/*
+ * The following table is used when there is a special need to setup a PCI device.
+ * For every PCI device found in this table is called the given init function with given
+ * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
+ * parameters!
+ *
+*/
+static struct pci_config_table pci_solidcard3_config_table[] =
+{
+/* Host to PCI Bridge device (405GP) */
+	{
+		vendor: 0x1014,
+		device: 0x0156,
+		class: PCI_CLASS_BRIDGE_HOST,
+		bus: 0,
+		dev: 0,
+		func: 0,
+		config_device: pci_405gp_setup_bridge
+	},
+	{ }
+};
+
+/*-------------------------------------------------------------------------+
+ | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
+ |
+ | Init the PCI part of the SolidCard III
+ |
+ | Params:
+ * - Pointer to current PCI hose
+ * - Current Device
+ *
+ * Returns
+ * nothing
+ +-------------------------------------------------------------------------*/
+
+void pci_init_board(void)
+{
+	POST_OUT(0x41);
+/*
+ * we want the ptrs to RAM not flash (ie don't use init list)
+ */
+	hose.fixup_irq    = pci_solidcard3_fixup_irq;
+	hose.config_table = pci_solidcard3_config_table;
+	pci_405gp_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/sc3/sc3.h b/u-boot/board/sc3/sc3.h
new file mode 100644
index 0000000..060aece
--- /dev/null
+++ b/u-boot/board/sc3/sc3.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**
+ * hcWriteWord - write a 16 bit value into the USB controller
+ * @base: base address to access the chip registers
+ * @value: 16 bit value to write into register @offset
+ * @offset: register to write the @value into
+ *
+ */
+static void inline hcWriteWord (unsigned long base, unsigned int value,
+				unsigned int offset)
+{
+	out_le16 ((volatile u16*)(base + 2), offset | 0x80);
+	out_le16 ((volatile u16*)base, value);
+}
+
+/**
+ * hcWriteDWord - write a 32 bit value into the USB controller
+ * @base: base address to access the chip registers
+ * @value: 32 bit value to write into register @offset
+ * @offset: register to write the @value into
+ *
+ */
+
+static void inline hcWriteDWord (unsigned long base, unsigned long value,
+				unsigned int offset)
+{
+	out_le16 ((volatile u16*)(base + 2), offset | 0x80);
+	out_le16 ((volatile u16*)base, value);
+	out_le16 ((volatile u16*)base, value >> 16);
+}
+
+/**
+ * hcReadWord - read a 16 bit value from the USB controller
+ * @base: base address to access the chip registers
+ * @offset: register to read from
+ *
+ * Returns the readed register value
+ */
+
+static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
+{
+	out_le16 ((volatile u16*)(base + 2), offset);
+	return (in_le16 ((volatile u16*)base));
+}
+
+/**
+ * hcReadDWord - read a 32 bit value from the USB controller
+ * @base: base address to access the chip registers
+ * @offset: register to read from
+ *
+ * Returns the readed register value
+ */
+
+static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
+{
+	unsigned long val, val16;
+
+	out_le16 ((volatile u16*)(base + 2), offset);
+	val = in_le16((volatile u16*)base);
+	val16 = in_le16((volatile u16*)base);
+	return (val | (val16 << 16));
+}
+
+/* control and status registers isp1161 */
+#define HcRevision		0x00
+#define HcControl		0x01
+#define HcCommandStatus		0x02
+#define HcInterruptStatus	0x03
+#define HcInterruptEnable	0x04
+#define HcInterruptDisable	0x05
+#define HcFmInterval		0x0D
+#define HcFmRemaining		0x0E
+#define HcFmNumber		0x0F
+#define HcLSThreshold		0x11
+#define HcRhDescriptorA		0x12
+#define HcRhDescriptorB		0x13
+#define HcRhStatus		0x14
+#define HcRhPortStatus1		0x15
+#define HcRhPortStatus2		0x16
+
+#define HcHardwareConfiguration 0x20
+#define HcDMAConfiguration	0x21
+#define HcTransferCounter	0x22
+#define HcuPInterrupt		0x24
+#define HcuPInterruptEnable	0x25
+#define HcChipID		0x27
+#define HcScratch		0x28
+#define HcSoftwareReset		0x29
+#define HcITLBufferLength	0x2A
+#define HcATLBufferLength	0x2B
+#define HcBufferStatus		0x2C
+#define HcReadBackITL0Length	0x2D
+#define HcReadBackITL1Length	0x2E
+#define HcITLBufferPort		0x40
+#define HcATLBufferPort		0x41
diff --git a/u-boot/board/sc3/sc3nand.c b/u-boot/board/sc3/sc3nand.c
new file mode 100644
index 0000000..62b40f1
--- /dev/null
+++ b/u-boot/board/sc3/sc3nand.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/processor.h>
+
+#define readb(addr)	*(volatile u_char *)(addr)
+#define readl(addr)	*(volatile u_long *)(addr)
+#define writeb(d,addr)	*(volatile u_char *)(addr) = (d)
+
+#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
+#define SC3_NAND_CLE 30	/* GPIO PIN 2 */
+#define SC3_NAND_CE  27 /* GPIO PIN 5 */
+
+static void *sc3_io_base;
+static void *sc3_control_base = (void *)0xEF600700;
+
+static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			set_bit (SC3_NAND_CLE, sc3_control_base);
+		else
+			clear_bit (SC3_NAND_CLE, sc3_control_base);
+		if ( ctrl & NAND_ALE )
+			set_bit (SC3_NAND_ALE, sc3_control_base);
+		else
+			clear_bit (SC3_NAND_ALE, sc3_control_base);
+		if ( ctrl & NAND_NCE )
+			set_bit (SC3_NAND_CE, sc3_control_base);
+		else
+			clear_bit (SC3_NAND_CE, sc3_control_base);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int sc3_nand_dev_ready(struct mtd_info *mtd)
+{
+	if (!(readl(sc3_control_base + 0x1C) & 0x4000))
+		return 0;
+	return 1;
+}
+
+static void sc3_select_chip(struct mtd_info *mtd, int chip)
+{
+	clear_bit (SC3_NAND_CE, sc3_control_base);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
+	/* Set address of NAND IO lines (Using Linear Data Access Region) */
+	nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
+	nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
+	/* Reference hardware control function */
+	nand->cmd_ctrl  = sc3_nand_hwcontrol;
+	nand->dev_ready  = sc3_nand_dev_ready;
+	nand->select_chip = sc3_select_chip;
+	return 0;
+}
+#endif
diff --git a/u-boot/board/sc3/u-boot.lds b/u-boot/board/sc3/u-boot.lds
new file mode 100644
index 0000000..9b1a39b
--- /dev/null
+++ b/u-boot/board/sc3/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/sc3/init.o	(.text)
+    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
+    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
+    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
+    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
+    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
+    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+    lib/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/env_embedded.o(.text)*/
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/scb9328/Makefile b/u-boot/board/scb9328/Makefile
new file mode 100644
index 0000000..a980f76
--- /dev/null
+++ b/u-boot/board/scb9328/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= scb9328.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/scb9328/config.mk b/u-boot/board/scb9328/config.mk
new file mode 100644
index 0000000..7c5e067
--- /dev/null
+++ b/u-boot/board/scb9328/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of scb93328 sources
+#
+# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+CONFIG_SYS_TEXT_BASE = 0x08f00000
diff --git a/u-boot/board/scb9328/flash.c b/u-boot/board/scb9328/flash.c
new file mode 100644
index 0000000..c6f94ae
--- /dev/null
+++ b/u-boot/board/scb9328/flash.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This code was inspired by Marius Groeger and Kyle Harris code
+ * available in other board ports for U-Boot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#include <common.h>
+#include "intel.h"
+
+
+/*
+ * This code should handle CFI FLASH memory device. This code is very
+ * minimalistic approach without many essential error handling code as well.
+ * Because U-Boot actually is missing smart handling of FLASH device,
+ * we just set flash_id to anything else to FLASH_UNKNOW, so common code
+ * can call us without any restrictions.
+ * TODO: Add CFI Query, to be able to determine FLASH device.
+ * TODO: Add error handling code
+ * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
+ *       hopefully may work with other configurations.
+ */
+
+#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
+#  define FLASH_BUS vu_char
+#  define FLASH_BUS_RET u_char
+#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  else
+#    error "With 8bit bus only one chip is allowed"
+#  endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
+#  define FLASH_BUS vu_short
+#  define FLASH_BUS_RET u_short
+#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+#    define FLASH_CMD( x ) (( x << 8 )| x )
+#  else
+#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
+#  endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
+#  define FLASH_BUS vu_long
+#  define FLASH_BUS_RET u_long
+#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+#    define FLASH_CMD( x ) (( x << 16 )| x )
+#  elif ( SCB9328_FLASH_INTERLEAVE == 4 )
+#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
+#  else
+#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
+#  endif
+
+#else
+#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
+#endif
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static FLASH_BUS_RET flash_status_reg (void)
+{
+
+	FLASH_BUS *addr = (FLASH_BUS *) 0;
+
+	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+
+	return *addr;
+}
+
+static int flash_ready (ulong timeout)
+{
+	int ok = 1;
+
+	reset_timer_masked ();
+	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
+		   FLASH_CMD (CFI_INTEL_SR_READY)) {
+		if (get_timer_masked () > timeout && timeout != 0) {
+			ok = 0;
+			break;
+		}
+	}
+	return ok;
+}
+
+#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
+#  error "SCB9328 platform has only one flash bank!"
+#endif
+
+
+ulong flash_init (void)
+{
+	int i;
+	unsigned long address = SCB9328_FLASH_BASE;
+
+	flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
+	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	flash_info[0].flash_id = INTEL_MANUFACT;
+	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
+		flash_info[0].start[i] = address;
+#ifdef SCB9328_FLASH_UNLOCK
+		/* Some devices are hw locked after start. */
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
+		flash_ready (0);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+#endif
+		address += SCB9328_FLASH_SECT_SIZE;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CONFIG_SYS_FLASH_BASE,
+				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+				   &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CONFIG_ENV_ADDR,
+				   CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return SCB9328_FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	printf (" Intel vendor\n");
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if (!(i % 5)) {
+			printf ("\n");
+		}
+
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, non_protected = 0, sector;
+	int rc = ERR_OK;
+
+	FLASH_BUS *address;
+
+	for (sector = s_first; sector <= s_last; sector++) {
+		if (!info->protect[sector]) {
+			non_protected++;
+		}
+	}
+
+	if (!non_protected) {
+		return ERR_PROTECTED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+
+	/* Start erase on unprotected sectors */
+	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
+		if (info->protect[sector]) {
+			printf ("Protected sector %2d skipping...\n", sector);
+			continue;
+		} else {
+			printf ("Erasing sector %2d ... ", sector);
+		}
+
+		address = (FLASH_BUS *) (info->start[sector]);
+
+		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
+		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
+		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
+			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+			printf ("ok.\n");
+		} else {
+			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+			rc = ERR_TIMOUT;
+			printf ("timeout! Aborting...\n");
+			break;
+		}
+		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
+{
+	FLASH_BUS *address = (FLASH_BUS *) dest;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*address & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts ();
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
+	*address = data;
+
+	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
+		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+		rc = ERR_TIMOUT;
+		printf ("timeout! Aborting...\n");
+	}
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong read_addr, write_addr;
+	FLASH_BUS data;
+	int i, result = ERR_OK;
+
+
+	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
+	write_addr = read_addr;
+	if (read_addr != addr) {
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (read_addr < addr || cnt == 0) {
+				data |= *((uchar *) read_addr) << i * 8;
+			} else {
+				data |= (*src++) << i * 8;
+				cnt--;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+	}
+	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
+		if ((result = write_data (info, write_addr,
+								  *((FLASH_BUS *) src))) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+		src += sizeof (FLASH_BUS);
+	}
+	if (cnt > 0) {
+		read_addr = write_addr;
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (cnt > 0) {
+				data |= (*src++) << i * 8;
+				cnt--;
+			} else {
+				data |= *((uchar *) read_addr) << i * 8;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != 0) {
+			return result;
+		}
+	}
+	return ERR_OK;
+}
diff --git a/u-boot/board/scb9328/intel.h b/u-boot/board/scb9328/intel.h
new file mode 100644
index 0000000..77498b6
--- /dev/null
+++ b/u-boot/board/scb9328/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff --git a/u-boot/board/scb9328/lowlevel_init.S b/u-boot/board/scb9328/lowlevel_init.S
new file mode 100644
index 0000000..8e6a49e
--- /dev/null
+++ b/u-boot/board/scb9328/lowlevel_init.S
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+	ldr		r0,	=PCDR
+	ldr		r1,	=CONFIG_SYS_PCDR_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 0 */
+
+	ldr		r0,	=MPCTL0
+	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
+	str		r1,   [r0]
+
+/* set mpll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<21)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+/* set System PLL Control Register 0 */
+
+	ldr		r0,	=SPCTL0
+	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
+	str		r1,   [r0]
+
+/* set spll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<22)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+	ldr		r0,   =CSCR
+	ldr		r1,   =CONFIG_SYS_CSCR_VAL
+	str		r1,   [r0]
+
+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ *this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+
+ * Slapping this into my bootloader does the trick...
+
+ * MRC p15,0,r0,c1,c0,0    ; read core configuration register
+ * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
+ * register
+ */
+	MRC p15,0,r0,c1,c0,0
+	ORR r0,r0,#0xC0000000
+	MCR p15,0,r0,c1,c0,0
+
+	ldr		r0,	=GPR(0)
+	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GIUS(0)
+	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
+	str		r1,   [r0]
+
+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+
+	ldr		r0,	=FMCR
+	ldr		r1,	=CONFIG_SYS_FMCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0U
+	ldr		r1,	=CONFIG_SYS_CS0U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0L
+	ldr		r1,	=CONFIG_SYS_CS0L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1U
+	ldr		r1,	=CONFIG_SYS_CS1U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1L
+	ldr		r1,	=CONFIG_SYS_CS1L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS2U
+	ldr		r1,	=CONFIG_SYS_CS2U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS2L
+	ldr		r1,	=CONFIG_SYS_CS2L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS3U
+	ldr		r1,	=CONFIG_SYS_CS3U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS3L
+	ldr		r1,	=CONFIG_SYS_CS3L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4U
+	ldr		r1,	=CONFIG_SYS_CS4U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4L
+	ldr		r1,	=CONFIG_SYS_CS4L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5U
+	ldr		r1,	=CONFIG_SYS_CS5U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5L
+	ldr		r1,	=CONFIG_SYS_CS5L_VAL
+	str		r1,   [r0]
+
+/* SDRAM Setup */
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =PRECHARGE_CMD
+	str		r1,   [r0]
+
+	ldr		r0, =0x08200000
+	ldr		r1, =0x0 /* Issue Precharge all Command */
+	str		r1,   [r0]
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =AUTOREFRESH_CMD
+	str		r1,   [r0]
+
+	ldr		r0, =0x08000000
+	ldr		r1, =0x0 /* Issue AutoRefresh Command */
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =0xb10a8300
+	str		r1,   [r0]
+
+	ldr		r0, =0x08223000 /* CAS Latency 2 */
+	ldr		r1, =0x0   /* Issue Mode Register Command, Burst Length = 8 */
+	str		r1,   [r0]
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
+	str		r1,   [r0]
+
+	mov	pc,r10
diff --git a/u-boot/board/scb9328/scb9328.c b/u-boot/board/scb9328/scb9328.c
new file mode 100644
index 0000000..428e8c9
--- /dev/null
+++ b/u-boot/board/scb9328/scb9328.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
+	gd->bd->bi_boot_params = 0x08000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+	gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
+	gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+	gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
+	gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 2 )
+	gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
+	gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 3 )
+	gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
+	gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE;
+#endif
+	return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	return;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/shannon/Makefile b/u-boot/board/shannon/Makefile
new file mode 100644
index 0000000..23ac987
--- /dev/null
+++ b/u-boot/board/shannon/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= shannon.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/shannon/config.mk b/u-boot/board/shannon/config.mk
new file mode 100644
index 0000000..6afa2d3
--- /dev/null
+++ b/u-boot/board/shannon/config.mk
@@ -0,0 +1,23 @@
+#
+# LART board with SA1100 cpu
+#
+# see http://www.lart.tudelft.nl/ for more information on LART
+#
+
+#
+# Tuxscreen has 4 banks of 4 MB DRAM each
+#
+# c000'0000
+# c800'0000
+# d000'0000
+# d800'0000
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to d838'0000, the upper 1 MB of the last (4th) bank
+#
+# download areas is c800'0000
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0xd8380000
diff --git a/u-boot/board/shannon/flash.c b/u-boot/board/shannon/flash.c
new file mode 100644
index 0000000..0455afa
--- /dev/null
+++ b/u-boot/board/shannon/flash.c
@@ -0,0 +1,473 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+#define FLASH_BANK_SIZE 0x400000	/* 4 MB */
+#define MAIN_SECT_SIZE  0x20000		/* 128 KB */
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00F000F0
+#define CMD_UNLOCK1		0x00AA00AA
+#define CMD_UNLOCK2		0x00550055
+#define CMD_ERASE_SETUP		0x00800080
+#define CMD_ERASE_CONFIRM	0x00300030
+#define CMD_PROGRAM		0x00A000A0
+#define CMD_UNLOCK_BYPASS	0x00200020
+
+#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2)))
+#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2)))
+
+#define BIT_ERASE_DONE		0x00800080
+#define BIT_RDY_MASK		0x00800080
+#define BIT_PROGRAM_ERROR	0x00200020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+    {
+	ulong flashbase = 0;
+	flash_info[i].flash_id =
+	  (AMD_MANUFACT & FLASH_VENDMASK) |
+	  (AMD_ID_LV160B & FLASH_TYPEMASK);
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+	if (i == 0)
+	  flashbase = PHYS_FLASH_1;
+	else
+	  panic("configured too many flash banks!\n");
+	for (j = 0; j < flash_info[i].sector_count; j++)
+	{
+
+	    if (j <= 3)
+	    {
+		/* 1st one is 32 KB */
+		if (j == 0)
+		{
+			flash_info[i].start[j] = flashbase + 0;
+		}
+
+		/* 2nd and 3rd are both 16 KB */
+		if ((j == 1) || (j == 2))
+		{
+			flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000;
+		}
+
+		/* 4th 64 KB */
+		if (j == 3)
+		{
+			flash_info[i].start[j] = flashbase + 0x10000;
+		}
+	    }
+	    else
+	    {
+		flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
+	    }
+	}
+	size += flash_info[i].size;
+    }
+
+    /*
+     * Protect monitor and environment sectors
+     * Inferno is complicated, it's hardware locked
+     */
+#ifdef CONFIG_INFERNO
+    /* first one, 0x00000 to 0x07fff */
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_FLASH_BASE + 0x00000,
+		  CONFIG_SYS_FLASH_BASE + 0x08000 - 1,
+		  &flash_info[0]);
+
+    /* third to 10th, 0x0c000 - 0xdffff */
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_FLASH_BASE + 0x0c000,
+		  CONFIG_SYS_FLASH_BASE + 0xe0000 - 1,
+		  &flash_info[0]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CONFIG_ENV_ADDR,
+		  CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    switch (info->flash_id & FLASH_VENDMASK)
+    {
+    case (AMD_MANUFACT & FLASH_VENDMASK):
+	printf("AMD: ");
+	break;
+    default:
+	printf("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK)
+    {
+    case (AMD_ID_LV160B & FLASH_TYPEMASK):
+	printf("2x Amd29F160BB (16Mbit)\n");
+	break;
+    default:
+	printf("Unknown Chip Type\n");
+	goto Done;
+	break;
+    }
+
+    printf("  Size: %ld MB in %d Sectors\n",
+	   info->size >> 20, info->sector_count);
+
+    printf("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; i++)
+    {
+	if ((i % 5) == 0)
+	{
+	    printf ("\n   ");
+	}
+	printf (" %08lX%s", info->start[i],
+		info->protect[i] ? " (RO)" : "     ");
+    }
+    printf ("\n");
+
+Done:
+    ;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    ulong result;
+    int iflag, cflag, prot, sect;
+    int rc = ERR_OK;
+    int chip1, chip2;
+
+    /* first look for protection bits */
+
+    if (info->flash_id == FLASH_UNKNOWN)
+	return ERR_UNKNOWN_FLASH_TYPE;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	return ERR_INVAL;
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) !=
+	(AMD_MANUFACT & FLASH_VENDMASK)) {
+	return ERR_UNKNOWN_FLASH_VENDOR;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+    if (prot)
+	return ERR_PROTECTED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+    {
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	if (info->protect[sect] == 0)
+	{	/* not protected */
+	    vu_long *addr = (vu_long *)(info->start[sect]);
+
+	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	    MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	    *addr = CMD_ERASE_CONFIRM;
+
+	    /* wait until flash is ready */
+	    chip1 = chip2 = 0;
+
+	    do
+	    {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+		{
+		    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+		    chip1 = TMO;
+		    break;
+		}
+
+		if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+			chip1 = READY;
+
+		if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+			chip1 = ERR;
+
+		if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
+			chip2 = READY;
+
+		if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
+			chip2 = ERR;
+
+	    }  while (!chip1 || !chip2);
+
+	    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+	    if (chip1 == ERR || chip2 == ERR)
+	    {
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	    }
+	    if (chip1 == TMO)
+	    {
+		rc = ERR_TIMOUT;
+		goto outahere;
+	    }
+
+	    printf("ok.\n");
+	}
+	else /* it was protected */
+	{
+	    printf("protected!\n");
+	}
+    }
+
+    if (ctrlc())
+      printf("User Interrupt!\n");
+
+outahere:
+    /* allow flash to settle - wait 10 ms */
+    udelay_masked(10000);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long *)dest;
+    ulong result;
+    int rc = ERR_OK;
+    int cflag, iflag;
+    int chip1, chip2;
+
+    /*
+     * Check if Flash is (sufficiently) erased
+     */
+    result = *addr;
+    if ((result & data) != data)
+	return ERR_NOT_ERASED;
+
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+    MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+    *addr = CMD_PROGRAM;
+    *addr = data;
+
+    /* arm simple, non interrupt dependent timer */
+    reset_timer_masked();
+
+    /* wait until flash is ready */
+    chip1 = chip2 = 0;
+    do
+    {
+	result = *addr;
+
+	/* check timeout */
+	if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+	{
+	    chip1 = ERR | TMO;
+	    break;
+	}
+	if (!chip1 && ((result & 0x80) == (data & 0x80)))
+		chip1 = READY;
+
+	if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
+	{
+		result = *addr;
+
+		if ((result & 0x80) == (data & 0x80))
+			chip1 = READY;
+		else
+			chip1 = ERR;
+	}
+
+	if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
+		chip2 = READY;
+
+	if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR))
+	{
+		result = *addr;
+
+		if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
+			chip2 = READY;
+		else
+			chip2 = ERR;
+	}
+
+    }  while (!chip1 || !chip2);
+
+    *addr = CMD_READ_ARRAY;
+
+    if (chip1 == ERR || chip2 == ERR || *addr != data)
+	rc = ERR_PROG_ERROR;
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int l;
+    int i, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data >> 8) | (*src++ << 24);
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = *((vu_long*)src);
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	src += 4;
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data >> 8) | (*src++ << 24);
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data >> 8) | (*(uchar *)cp << 24);
+    }
+
+    return write_word(info, wp, data);
+}
diff --git a/u-boot/board/shannon/inferno.header b/u-boot/board/shannon/inferno.header
new file mode 100644
index 0000000..28ee85a
--- /dev/null
+++ b/u-boot/board/shannon/inferno.header
diff --git a/u-boot/board/shannon/lowlevel_init.S b/u-boot/board/shannon/lowlevel_init.S
new file mode 100644
index 0000000..0655c42
--- /dev/null
+++ b/u-boot/board/shannon/lowlevel_init.S
@@ -0,0 +1,92 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+#define	MDCNFG	0x00
+#define MDCAS0	0x04
+#define MDCAS1	0x08
+#define MDCAS2	0x0c
+#define MSC0	0x10
+#define MSC1	0x14
+#define MECR	0x18
+
+mdcas0:		.long	0xc71c703f @ cccccccf
+mdcas1:		.long	0xffc71c71 @ fffffffc
+mdcas2:		.long	0xffffffff @ ffffffff
+mdcnfg:		.long	0x0334b21f @ 9326991f
+msc0:		.long   0xfff84458 @ 42304230
+msc1:		.long	0xffffffff @ 20182018
+mecr:		.long	0x7fff7fff @ 01000000
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	r0, MEM_BASE
+
+	/* Setup the flash memory */
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+
+	/* Set up the DRAM */
+
+	/* MDCAS0 */
+	ldr	r1, mdcas0
+	str	r1, [r0, #MDCAS0]
+
+	/* MDCAS1 */
+	ldr	r1, mdcas1
+	str	r1, [r0, #MDCAS1]
+
+	/* MDCAS2 */
+	ldr	r1, mdcas2
+	str	r1, [r0, #MDCAS2]
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Set up PCMCIA space */
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	/* Load something to activate bank */
+	ldr	r1, MEM_START
+
+.rept	8
+	ldr	r0, [r1]
+.endr
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/shannon/shannon.c b/u-boot/board/shannon/shannon.c
new file mode 100644
index 0000000..8cd1fc3
--- /dev/null
+++ b/u-boot/board/shannon/shannon.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* memory and cpu-speed are setup before relocation */
+	/* but if we use InfernoLoader, we must do some inits here */
+
+#ifdef CONFIG_INFERNO
+	{
+	unsigned long temp;
+	__asm__ __volatile__(/* disable MMU, enable icache */
+			     "mrc p15, 0, %0, c1, c0\n"
+			     "bic %0, %0, #0x00002000\n"
+			     "bic %0, %0, #0x0000000f\n"
+			     "orr %0, %0, #0x00001000\n"
+			     "orr %0, %0, #0x00000002\n"
+			     "mcr p15, 0, %0, c1, c0\n"
+			     /* flush caches */
+			     "mov %0, #0\n"
+			     "mcr p15, 0, %0, c7, c7, 0\n"
+			     "mcr p15, 0, %0, c8, c7, 0\n"
+			     : "=r" (temp)
+			     :
+			     : "memory");
+	/* setup PCMCIA timing */
+	temp = 0xa0000018;
+	*(unsigned long *)temp = 0x00060006;
+
+	}
+#endif /* CONFIG_INFERNO */
+
+	/* arch number for shannon */
+	gd->bd->bi_arch_number = MACH_TYPE_SHANNON;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
+    defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
+	bd_t *bd = gd->bd;
+#endif
+
+#ifdef PHYS_SDRAM_1
+	bd->bi_dram[0].start = PHYS_SDRAM_1;
+	bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#endif
+
+#ifdef PHYS_SDRAM_2
+	bd->bi_dram[1].start = PHYS_SDRAM_2;
+	bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+
+#ifdef PHYS_SDRAM_3
+	bd->bi_dram[2].start = PHYS_SDRAM_3;
+	bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+
+#ifdef PHYS_SDRAM_4
+	bd->bi_dram[3].start = PHYS_SDRAM_4;
+	bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
+
+	return (0);
+}
diff --git a/u-boot/board/sheldon/simpc8313/Makefile b/u-boot/board/sheldon/simpc8313/Makefile
new file mode 100644
index 0000000..f18aded
--- /dev/null
+++ b/u-boot/board/sheldon/simpc8313/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sheldon/simpc8313/config.mk b/u-boot/board/sheldon/simpc8313/config.mk
new file mode 100644
index 0000000..d1b4e2e
--- /dev/null
+++ b/u-boot/board/sheldon/simpc8313/config.mk
@@ -0,0 +1,5 @@
+ifdef CONFIG_NAND_LP
+PAD_TO = 0xFFF20000
+else
+PAD_TO = 0xFFF04000
+endif
diff --git a/u-boot/board/sheldon/simpc8313/sdram.c b/u-boot/board/sheldon/simpc8313/sdram.c
new file mode 100644
index 0000000..ba59943
--- /dev/null
+++ b/u-boot/board/sheldon/simpc8313/sdram.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ * Copyright (C) Sheldon Instruments, Inc. 2008
+ *
+ * Author: Ron Madrid <info@sheldoninst.com>
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static long fixed_sdram(void);
+
+#if defined(CONFIG_NAND_SPL)
+void si_wait_i2c(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+
+	while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
+		;
+
+	__raw_writeb(0x00, &im->i2c[0].sr);
+
+	sync();
+
+	return;
+}
+
+void si_read_i2c(u32 lbyte, int count, u8 *buffer)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 i;
+	u8 chip = 0x50 << 1; /* boot sequencer I2C */
+	u32 ubyte = (lbyte & 0xff00) >> 8;
+
+	lbyte &= 0xff;
+
+	/*
+	 * Set up controller
+	 */
+	__raw_writeb(0x3f, &im->i2c[0].fdr);
+	__raw_writeb(0x00, &im->i2c[0].adr);
+	__raw_writeb(0x00, &im->i2c[0].sr);
+	__raw_writeb(0x00, &im->i2c[0].dr);
+
+	while (__raw_readb(&im->i2c[0].sr) & 0x20)
+		;
+
+	/*
+	 * Writing address to device
+	 */
+	__raw_writeb(0xb0, &im->i2c[0].cr);
+	sync();
+	__raw_writeb(chip, &im->i2c[0].dr);
+	si_wait_i2c();
+
+	__raw_writeb(0xb0, &im->i2c[0].cr);
+	sync();
+	__raw_writeb(ubyte, &im->i2c[0].dr);
+	si_wait_i2c();
+
+	__raw_writeb(lbyte, &im->i2c[0].dr);
+	si_wait_i2c();
+
+	__raw_writeb(0xb4, &im->i2c[0].cr);
+	sync();
+	__raw_writeb(chip + 1, &im->i2c[0].dr);
+	si_wait_i2c();
+
+	__raw_writeb(0xa0, &im->i2c[0].cr);
+	sync();
+
+	/*
+	 * Dummy read
+	 */
+	__raw_readb(&im->i2c[0].dr);
+
+	si_wait_i2c();
+
+	/*
+	 * Read actual data
+	 */
+	for (i = 0; i < count; i++)
+	{
+		if (i == (count - 2))	/* Reached next to last byte, No ACK */
+			__raw_writeb(0xa8, &im->i2c[0].cr);
+		if (i == (count - 1))	/* Reached last byte, STOP */
+			__raw_writeb(0x88, &im->i2c[0].cr);
+
+		/* Read byte of data */
+		buffer[i] = __raw_readb(&im->i2c[0].dr);
+
+		if (i == (count - 1))
+			break;
+		si_wait_i2c();
+	}
+
+	return;
+}
+#endif /* CONFIG_NAND_SPL */
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize;
+
+	if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
+
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
+	__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
+	sync();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+/*************************************************************************
+ *  fixed sdram init -- reads values from boot sequencer I2C
+ ************************************************************************/
+static long fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msizelog2, msize = 1;
+#if defined(CONFIG_NAND_SPL)
+	u32 i;
+	const u8 bytecount = 135;
+	u8 buffer[bytecount];
+	u32 addr, data;
+
+	si_read_i2c(0, bytecount, buffer);
+
+	for (i = 18; i < bytecount; i += 7){
+		addr = (u32)buffer[i];
+		addr <<= 8;
+		addr |= (u32)buffer[i + 1];
+		addr <<= 2;
+		data = (u32)buffer[i + 2];
+		data <<= 8;
+		data |= (u32)buffer[i + 3];
+		data <<= 8;
+		data |= (u32)buffer[i + 4];
+		data <<= 8;
+		data |= (u32)buffer[i + 5];
+
+		__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
+	}
+
+	sync();
+
+	/* enable DDR controller */
+	__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
+#endif /* (CONFIG_NAND_SPL) */
+
+	msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
+	msize <<= (msizelog2 - 20);
+
+	return msize;
+}
diff --git a/u-boot/board/sheldon/simpc8313/simpc8313.c b/u-boot/board/sheldon/simpc8313/simpc8313.c
new file mode 100644
index 0000000..9126c42
--- /dev/null
+++ b/u-boot/board/sheldon/simpc8313/simpc8313.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ * Copyright (C) Sheldon Instruments, Inc. 2008
+ *
+ * Author: Ron Madrid <info@sheldoninst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_NAND_SPL
+int checkboard(void)
+{
+	puts("Board: Sheldon Instruments SIMPC8313\n");
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
+
+/*
+ * Miscellaneous late-boot configurations
+ */
+int misc_init_r(void)
+{
+	int rc = 0;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	fsl_lbc_t *lbus = &immap->im_lbc;
+	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */
+
+	/* UPM Table Configuration Code */
+	static uint UPMATable[] = {
+		/* Read Single-Beat (RSS) */
+		0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Read Burst (RBS) */
+		0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
+		0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Write Single-Beat (WSS) */
+		0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Write Burst (WBS) */
+		0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
+		0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
+		0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Refresh Timer (RTS) */
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Exception Condition (EXS) */
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
+	};
+
+	upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
+
+	/* Set LUPWAIT to be active low and enabled */
+	out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+#else /* CONFIG_NAND_SPL */
+void board_init_f(ulong bootflag)
+{
+	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+				CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
+				  CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+#endif
diff --git a/u-boot/board/shmin/Makefile b/u-boot/board/shmin/Makefile
new file mode 100644
index 0000000..06888cd
--- /dev/null
+++ b/u-boot/board/shmin/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2010 Nobuhiro Iwamatsu
+# Copyright (C) 2008 Renesas Solutions Corp.
+#
+# u-boot/board/shmin/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).o
+
+OBJS	:= shmin.o
+SOBJS	:= lowlevel_init.o
+
+LIB	:= $(addprefix $(obj),$(LIB))
+OBJS	:= $(addprefix $(obj),$(OBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/shmin/lowlevel_init.S b/u-boot/board/shmin/lowlevel_init.S
new file mode 100644
index 0000000..b29da35
--- /dev/null
+++ b/u-boot/board/shmin/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	/* Use setting of original bootloader */
+	rts
+	nop
+	.align 2
diff --git a/u-boot/board/shmin/shmin.c b/u-boot/board/shmin/shmin.c
new file mode 100644
index 0000000..8742f10
--- /dev/null
+++ b/u-boot/board/shmin/shmin.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2007 - 2010
+ *     Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2000-2003
+ *     Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * board/shmin/shmin.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	puts("BOARD: T-SH7706LAN ");
+	if(readb(0xb0008006) == 0xab)
+		puts("v2\n");
+	else
+		puts("v1\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	writew(0x2980, BCR2);
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+
+}
+
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	int sect[] = CONFIG_SYS_ATMEL_SECT;
+	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
+		int i, j, k;
+
+	if (base != CONFIG_SYS_ATMEL_BASE)
+		return 0;
+
+	info->flash_id			= 0x01000000;
+	info->portwidth			= 1;
+	info->chipwidth			= 1;
+	info->buffer_size		= 1;
+	info->erase_blk_tout	= 16384;
+	info->write_tout		= 2;
+	info->buffer_write_tout	= 5;
+	info->vendor			= 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
+	info->cmd_reset			= 0x00F0;
+	info->interface			= FLASH_CFI_X8;
+	info->legacy_unlock		= 0;
+	info->manufacturer_id	= (u16) ATM_MANUFACT;
+	info->device_id			= ATM_ID_LV040;
+	info->device_id2		= 0;
+	info->ext_addr			= 0;
+	info->cfi_version		= 0x3133;
+	info->cfi_offset		= 0x0000;
+	info->addr_unlock1		= 0x00000555;
+	info->addr_unlock2		= 0x000002AA;
+	info->name				= "CFI conformant";
+	info->size				= 0;
+	info->sector_count		= CONFIG_SYS_ATMEL_TOTALSECT;
+	info->start[0] = base;
+
+	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
+		info->size += sect[i] * sectsz[i];
+		for (j = 0; j < sect[i]; j++, k++) {
+			info->start[k + 1] = info->start[k] + sectsz[i];
+			info->protect[k] = 0;
+		}
+	}
+
+	return 1;
+}
+#endif /* CONFIG_FLASH_CFI_LEGACY */
diff --git a/u-boot/board/siemens/IAD210/IAD210.c b/u-boot/board/siemens/IAD210/IAD210.c
new file mode 100644
index 0000000..7325a93
--- /dev/null
+++ b/u-boot/board/siemens/IAD210/IAD210.c
@@ -0,0 +1,299 @@
+/*
+ * (C) Copyright 2001
+ * Paul Geerinckx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <net.h>
+#include "atm.h"
+#include <i2c.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+/* used PLD registers */
+#  define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
+#  define PLD_EXT_RES  (unsigned char *) (0x10000000 + 10)
+#  define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
+#  define PLD_EXT_LED  (unsigned char *) (0x10000000 + 12)
+#  define PLD_EXT_X21  (unsigned char *) (0x10000000 + 13)
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47,	/* last */
+	_NOT_USED_,
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0xFFFAF834, 0xFFE5B435,	/* last */
+	_NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
+	0xF0AFFC00, 0xF0AAF800, 0xF1A5E447,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xFE29B300, 0xF1A27304, 0xFFA5F747,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF1AAF804, 0xFFA5F447,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
+	0xFFAFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * MRS sequence  (Offset 38 in UPMA RAM)
+	 */
+	0xFFAAB834, 0xFFA57434, 0xFFAFFC05,	/* last */
+	_NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0xFFAFFC04, 0xFFAFFC05,	/* last */
+	_NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile iop8xx_t *iop = &immap->im_ioport;
+	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+	long int size;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM precharge */
+	udelay (1);
+	memctl->memc_mcr = 0x80004030;	/* SDRAM 16x autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80004138;	/* SDRAM upload parameters */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 */
+	size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
+			  SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR;
+	udelay (1000);
+
+	/*
+	 * Final mapping
+	 */
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
+
+	udelay (10000);
+
+	/* prepare pin multiplexing for fast ethernet */
+
+	atmLoad ();
+	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
+	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
+
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	return (0);
+}
+
+void board_serial_init (void)
+{
+	;			/* nothing to do here */
+}
+
+void board_ether_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *iop = &immap->im_ioport;
+	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+
+	atmLoad ();
+	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
+	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
+}
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile iop8xx_t *iop = &immap->im_ioport;
+
+	/* configure the LED timing output pins - port A pin 4 */
+	iop->iop_papar = 0x0800;
+	iop->iop_padir = 0x0800;
+
+	/* start timer 2 for the 4hz LED blink rate */
+	timers->cpmt_tmr2 = 0xff2c;	/* 4HZ for 64MHz */
+	timers->cpmt_trr2 = 0x000003d0;	/* clk/16 , prescale=256 */
+	timers->cpmt_tgcr = 0x00000810;	/* run timer 2 */
+
+	/* chip select for PLD access */
+	memctl->memc_br6 = 0x10000401;
+	memctl->memc_or6 = 0xFC000908;
+
+	/* PLD initial values ( set LEDs, remove reset on LXT) */
+
+	*PLD_GCR1_REG = 0x06;
+	*PLD_EXT_RES = 0xC0;
+	*PLD_EXT_FETH = 0x40;
+	*PLD_EXT_LED = 0xFF;
+	*PLD_EXT_X21 = 0x04;
+	return 0;
+}
+
+static void board_get_enetaddr(uchar *addr)
+{
+	int i;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	unsigned int rccrtmp;
+
+	char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
+
+	for (i = 0; i < 6; i++)
+		addr[i] = default_mac_addr[i];
+
+	printf ("There is an error in the i2c driver .. /n");
+	printf ("You need to fix it first....../n");
+
+	rccrtmp = cpm->cp_rccr;
+	cpm->cp_rccr |= 0x0020;
+
+	i2c_reg_read (0xa0, 0);
+	printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
+		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
+
+	cpm->cp_rccr = rccrtmp;
+}
+
+int misc_init_r(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
diff --git a/u-boot/board/siemens/IAD210/Makefile b/u-boot/board/siemens/IAD210/Makefile
new file mode 100644
index 0000000..bb81507
--- /dev/null
+++ b/u-boot/board/siemens/IAD210/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o atm.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/siemens/IAD210/atm.c b/u-boot/board/siemens/IAD210/atm.c
new file mode 100644
index 0000000..e599c10
--- /dev/null
+++ b/u-boot/board/siemens/IAD210/atm.c
@@ -0,0 +1,652 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+#include "atm.h"
+#include <linux/stddef.h>
+
+#define SYNC __asm__("sync")
+#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
+
+#define FALSE  1
+#define TRUE   0
+#define OK     0
+#define ERROR -1
+
+struct atm_connection_t g_conn[NUM_CONNECTIONS] =
+{
+  { NULL, 10, NULL, 10,  NULL, NULL, NULL, NULL }, /* OAM  */
+};
+
+struct atm_driver_t g_atm =
+{
+  FALSE,   /* loaded */
+  FALSE,   /* started */
+  NULL,    /* csram */
+  0,       /* csram_size */
+  NULL,    /* am_top */
+  NULL,    /* ap_top */
+  NULL,    /* int_reload_ptr */
+  NULL,    /* int_serv_ptr */
+  NULL,    /* rbd_base_ptr */
+  NULL,    /* tbd_base_ptr */
+  0        /* linerate */
+};
+
+char csram[1024]; /* more than enough for doing nothing*/
+
+int    atmLoad(void);
+void   atmUnload(void);
+int    atmMemInit(void);
+void   atmIntInit(void);
+void   atmApcInit(void);
+void   atmAmtInit(void);
+void   atmCpmInit(void);
+void   atmUtpInit(void);
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmLoad
+ *
+ * DESCRIPTION: Basic ATM initialization.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: OK or ERROR
+ *
+ ****************************************************************************/
+int atmLoad()
+{
+  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
+  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+  volatile iop8xx_t      *iop    = &immap->im_ioport;
+
+  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
+  immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
+  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
+
+  if ( atmMemInit() != OK ) return ERROR;
+
+  atmIntInit();
+  atmApcInit();
+  atmAmtInit();
+  atmCpmInit();
+  atmUtpInit();
+
+  g_atm.loaded = TRUE;
+
+  return OK;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmUnload
+ *
+ * DESCRIPTION: Disables ATM and UTOPIA.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmUnload()
+{
+  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
+  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+  volatile iop8xx_t      *iop    = &immap->im_ioport;
+
+  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
+  immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC;  /* Disable SCC4 */
+  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
+  g_atm.loaded = FALSE;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmMemInit
+ *
+ * DESCRIPTION:
+ *
+ * The ATM driver uses the following resources:
+ *
+ * A. Memory in DPRAM to hold
+ *
+ *     1/ CT          = Connection Table ( RCT & TCT )
+ *     2/ TCTE        = Transmit Connection Table Extension
+ *     3/ MPHYPT      = Multi-PHY Pointing Table
+ *     4/ APCP        = APC Parameter Table
+ *     5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
+ *     6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
+ *     7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
+ *     8/ TQ          = Transmit Queue
+ *     9/ AM          = Address Matching Table
+ *    10/ AP          = Address Pointing Table
+ *
+ * B. Memory in cache safe RAM to hold
+ *
+ *     1/ INT         = Interrupt Queue
+ *     2/ RBD         = Receive Buffer Descriptors
+ *     3/ TBD         = Transmit Buffer Descriptors
+ *
+ * This function
+ * 1. clears the ATM DPRAM area,
+ * 2. Allocates and clears cache safe memory,
+ * 3. Initializes 'g_conn'.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: OK or ERROR
+ *
+ ****************************************************************************/
+int atmMemInit()
+{
+  int i;
+  unsigned immr = CONFIG_SYS_IMMR;
+  int total_num_rbd = 0;
+  int total_num_tbd = 0;
+
+  memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
+
+  g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
+
+  for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
+    total_num_rbd += g_conn[i].num_rbd;
+    total_num_tbd += g_conn[i].num_tbd;
+  }
+
+  g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
+
+  g_atm.csram = &csram[0];
+  memset(&(g_atm.csram), 0x00, g_atm.csram_size);
+
+  g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4);
+  g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
+  g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
+
+  g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
+  g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
+  g_conn[0].ct_ptr = CT_PTR(immr);
+  g_conn[0].tcte_ptr = TCTE_PTR(immr);
+
+  return OK;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmIntInit
+ *
+ * DESCRIPTION:
+ *
+ * Initialization of the MPC860 ESAR Interrupt Queue.
+ * This function
+ * - clears all entries in the INT,
+ * - sets the WRAP bit of the last INT entry,
+ * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
+ *   to the first INT entry.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARKS:
+ *
+ * - The INT resides in external cache safe memory.
+ * - The base address of the INT is stored in g_atm.int_reload_ptr.
+ * - The number of entries in the INT is given by NUM_INT_ENTRIES.
+ * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
+ *
+ ****************************************************************************/
+void atmIntInit()
+{
+  int i;
+  for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
+  g_atm.int_reload_ptr[i] = INT_WRAP;
+  g_atm.int_serv_ptr = g_atm.int_reload_ptr;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmApcInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the following ATM Pace Controller related
+ * data structures:
+ *
+ * - 1 MPHY Pointing Table (contains only one entry)
+ * - 3 APC Parameter Tables (one PHY with 3 priorities)
+ * - 3 APC Tables (one table for each priority)
+ * - 1 Transmit Queue (one transmit queue per PHY)
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmApcInit()
+{
+  int i;
+  /* unsigned immr = CONFIG_SYS_IMMR; */
+  uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
+  struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
+  uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
+  uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
+  /***************************************************/
+  /* Initialize MPHY Pointing Table (only one entry) */
+  /***************************************************/
+  *mphypt_ptr = APCP_BASE;
+
+  /********************************************/
+  /* Initialize APC parameters for priority 1 */
+  /********************************************/
+  apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
+  apcp_ptr->apct_end1  =  APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
+  apcp_ptr->apct_ptr1  =  APCT_PRIO_1_BASE;
+  apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
+  apcp_ptr->etqbase    = TQ_BASE;
+  apcp_ptr->etqend     =  TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
+  apcp_ptr->etqaptr    = TQ_BASE;
+  apcp_ptr->etqtptr    = TQ_BASE;
+  apcp_ptr->apc_mi     = 8;
+  apcp_ptr->ncits      = 0x0100;   /* NCITS = 1 */
+  apcp_ptr->apcnt      = 0;
+  apcp_ptr->reserved1  = 0;
+  apcp_ptr->eapcst     = 0x2009;  /* LAST, ESAR, MPHY */
+  apcp_ptr->ptp_counter = 0;
+  apcp_ptr->ptp_txch   = 0;
+  apcp_ptr->reserved2  = 0;
+
+
+  /***************************************************/
+  /* Initialize APC Tables with empty slots (0xFFFF) */
+  /***************************************************/
+  for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
+
+  /************************/
+  /* Clear Transmit Queue */
+  /************************/
+  for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmAmtInit
+ *
+ * DESCRIPTION:
+ *
+ * This function clears the first entry in the Address Matching Table and
+ * lets the first entry in the Address Pointing table point to the first
+ * entry in the TCT table (i.e. the raw cell channel).
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARKS:
+ *
+ * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
+ * RAM are initialized by atmCpmInit().
+ *
+ ****************************************************************************/
+void atmAmtInit()
+{
+  unsigned immr = CONFIG_SYS_IMMR;
+
+  g_atm.am_top = AM_PTR(immr);
+  g_atm.ap_top = AP_PTR(immr);
+
+  *(g_atm.ap_top--) = CT_BASE;
+  *(g_atm.am_top--) = 0;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmCpmInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the Utopia Interface Parameter RAM Map
+ * (SCC4, ATM Protocol) of the Communication Processor Modudule.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmCpmInit()
+{
+  unsigned immr = CONFIG_SYS_IMMR;
+
+  memset((char *)immr + 0x3F00, 0x00, 0xC0);
+
+  /*-----------------------------------------------------------------*/
+  /* RBDBASE - Receive buffer descriptors base address               */
+  /* The RBDs reside in cache safe external memory.                  */
+  /*-----------------------------------------------------------------*/
+  *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
+
+  /*-----------------------------------------------------------------*/
+  /* SRFCR - SAR receive function code                               */
+  /* 0-2 rsvd = 000                                                  */
+  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
+  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
+  /*                when the SDMA channel accesses memory.           */
+  /*-----------------------------------------------------------------*/
+  *SRFCR(immr) = 0x18;
+
+  /*-----------------------------------------------------------------*/
+  /* SRSTATE - SAR receive status                                    */
+  /* 0 EXT  = 0 Extended mode off.                                   */
+  /* 1 ACP  = 0 Valid only if EXT = 1.                               */
+  /* 2 EC   = 0 Standard 53-byte ATM cell.                           */
+  /* 3 SNC  = 0 In sync. Must be set to 0 during initialization.     */
+  /* 4 ESAR = 1 Enhanced SAR functionality enabled.                  */
+  /* 5 MCF  = 1 Management Cell Filter active.                       */
+  /* 6 SER  = 0 UTOPIA mode.                                         */
+  /* 7 MPY  = 1 Multiple PHY mode.                                   */
+  /*-----------------------------------------------------------------*/
+  *SRSTATE(immr) = 0x0D;
+
+  /*-----------------------------------------------------------------*/
+  /* MRBLR - Maximum receive buffer length register.                 */
+  /* Must be cleared for ATM operation (see also SMRBLR).            */
+  /*-----------------------------------------------------------------*/
+  *MRBLR(immr) = 0;
+
+  /*-----------------------------------------------------------------*/
+  /* RSTATE - SCC internal receive state parameters                  */
+  /* The first byte must be initialized with the value of SRFCR.     */
+  /*-----------------------------------------------------------------*/
+  *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
+
+  /*-----------------------------------------------------------------*/
+  /* STFCR - SAR transmit function code                              */
+  /* 0-2 rsvd = 000                                                  */
+  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
+  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
+  /*                when the SDMA channel accesses memory.           */
+  /*-----------------------------------------------------------------*/
+  *STFCR(immr) = 0x18;
+
+  /*-----------------------------------------------------------------*/
+  /* SRSTATE - SAR transmit status                                   */
+  /* 0 EXT  = 0 : Extended mode off                                  */
+  /* 1 rsvd = 0 :                                                    */
+  /* 2 EC   = 0 : Standard 53-byte ATM cell                          */
+  /* 3 rsvd = 0 :                                                    */
+  /* 4 ESAR = 1 : Enhanced SAR functionality enabled                 */
+  /* 5 rsvd = 0 :                                                    */
+  /* 6 SER  = 0 : UTOPIA mode                                        */
+  /* 7 MPY  = 1 : Multiple PHY mode                                  */
+  /*-----------------------------------------------------------------*/
+  *STSTATE(immr) = 0x09;
+
+  /*-----------------------------------------------------------------*/
+  /* TBDBASE - Transmit buffer descriptors base address              */
+  /* The TBDs reside in cache safe external memory.                  */
+  /*-----------------------------------------------------------------*/
+  *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
+
+  /*-----------------------------------------------------------------*/
+  /* TSTATE - SCC internal transmit state parameters                 */
+  /* The first byte must be initialized with the value of STFCR.     */
+  /*-----------------------------------------------------------------*/
+  *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
+
+  /*-----------------------------------------------------------------*/
+  /* CTBASE - Connection table base address                          */
+  /* Offset from the beginning of DPRAM (64-byte aligned).           */
+  /*-----------------------------------------------------------------*/
+  *CTBASE(immr) = CT_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* INTBASE - Interrupt queue base pointer.                         */
+  /* The interrupt queue resides in cache safe external memory.      */
+  /*-----------------------------------------------------------------*/
+  *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
+
+  /*-----------------------------------------------------------------*/
+  /* INTPTR - Pointer into interrupt queue.                          */
+  /* Initialize to INTBASE.                                          */
+  /*-----------------------------------------------------------------*/
+  *INTPTR(immr) = *INTBASE(immr);
+
+  /*-----------------------------------------------------------------*/
+  /* C_MASK - Constant mask for CRC32                                */
+  /* Must be initialized to 0xDEBB20E3.                              */
+  /*-----------------------------------------------------------------*/
+  *C_MASK(immr) = 0xDEBB20E3;
+
+  /*-----------------------------------------------------------------*/
+  /* INT_ICNT - Interrupt threshold value                            */
+  /*-----------------------------------------------------------------*/
+  *INT_ICNT(immr) = 1;
+
+  /*-----------------------------------------------------------------*/
+  /* INT_CNT - Interrupt counter                                     */
+  /* Initalize to INT_ICNT. Decremented for each interrupt entry     */
+  /* reported in the interrupt queue. On zero an interrupt is        */
+  /* signaled to the host by setting the GINT bit in the event       */
+  /* register. The counter is reinitialized with INT_ICNT.           */
+  /*-----------------------------------------------------------------*/
+  *INT_CNT(immr) = *INT_ICNT(immr);
+
+  /*-----------------------------------------------------------------*/
+  /* SMRBLR - SAR maximum receive buffer length register.            */
+  /* Must be a multiple of 48 bytes. Common for all ATM connections. */
+  /*-----------------------------------------------------------------*/
+  *SMRBLR(immr) = SAR_RXB_SIZE;
+
+  /*-----------------------------------------------------------------*/
+  /* APCST - APC status register.                                    */
+  /* 0     rsvd 0                                                    */
+  /* 1-2   CSER 11  Initialize with the same value as NSER.          */
+  /* 3-4   NSER 11  Next serial or UTOPIA channel.                   */
+  /* 5-7   rsvd 000                                                  */
+  /* 8-10  rsvd 000                                                  */
+  /* 11    rsvd 0                                                    */
+  /* 12    ESAR 1   UTOPIA Level 2 MPHY enabled.                     */
+  /* 13    DIS  0   APC disable. Must be initiazed to 0.             */
+  /* 14    PL2  0   Not used.                                        */
+  /* 15    MPY  1   Multiple PHY mode on.                            */
+  /*-----------------------------------------------------------------*/
+  *APCST(immr) = 0x7809;
+
+  /*-----------------------------------------------------------------*/
+  /* APCPTR - Pointer to the APC parameter table                     */
+  /* In MPHY master mode this parameter points to the MPHY pointing  */
+  /* table. 2-byte aligned.                                          */
+  /*-----------------------------------------------------------------*/
+  *APCPTR(immr) = MPHYPT_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* HMASK - Header mask                                             */
+  /* Each incoming cell is masked with HMASK before being compared   */
+  /* to the entries in the address matching table.                   */
+  /*-----------------------------------------------------------------*/
+  *HMASK(immr) = AM_HMASK;
+
+  /*-----------------------------------------------------------------*/
+  /* AMBASE - Address matching table base address                    */
+  /*-----------------------------------------------------------------*/
+  *AMBASE(immr) = AM_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* AMEND - Address matching table end address                      */
+  /*-----------------------------------------------------------------*/
+  *AMEND(immr) = AM_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* APBASE - Address pointing table base address                    */
+  /*-----------------------------------------------------------------*/
+  *APBASE(immr) = AP_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* MPHYST - MPHY status register                                   */
+  /* 0-1   rsvd  00                                                  */
+  /* 2-6   NMPHY 00000 1 PHY                                         */
+  /* 7-9   rsvd  000                                                 */
+  /* 10-14 CMPHY 00000 Initialize with same value as NMPHY           */
+  /*-----------------------------------------------------------------*/
+  *MPHYST(immr) = 0x0000;
+
+  /*-----------------------------------------------------------------*/
+  /* TCTEBASE - Transmit connection table extension base address     */
+  /* Offset from the beginning of DPRAM (32-byte aligned).           */
+  /*-----------------------------------------------------------------*/
+  *TCTEBASE(immr) = TCTE_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* Clear not used registers.                                       */
+  /*-----------------------------------------------------------------*/
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmUtpInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the ATM interface for
+ *
+ * - UTOPIA mode
+ * - muxed bus
+ * - master operation
+ * - multi PHY (because of a bug in the MPC860P rev. E.0)
+ * - internal clock = SYSCLK / 2
+ *
+ * EXTERNAL EFFECTS:
+ *
+ * After calling this function, the MPC860ESAR UTOPIA bus is
+ * active and uses the following ports/pins:
+ *
+ * Port    Pin  Signal   Description
+ * ------  ---  -------  -------------------------------------------
+ * PB[15]  R17  TxClav   Transmit cell available input/output signal
+ * PC[15]  D16  RxClav   Receive cell available input/output signal
+ * PD[15]  U17  UTPB[0]  UTOPIA bus bit 0 input/output signal
+ * PD[14]  V19  UTPB[1]  UTOPIA bus bit 1 input/output signal
+ * PD[13]  V18  UTPB[2]  UTOPIA bus bit 2 input/output signal
+ * PD[12]  R16  UTPB[3]  UTOPIA bus bit 3 input/output signal
+ * PD[11]  T16  RXENB    Receive enable input/output signal
+ * PD[10]  W18  TXENB    Transmit enable input/output signal
+ * PD[9]   V17  UTPCLK   UTOPIA clock input/output signal
+ * PD[7]   T15  UTPB[4]  UTOPIA bus bit 4 input/output signal
+ * PD[6]   V16  UTPB[5]  UTOPIA bus bit 5 input/output signal
+ * PD[5]   U15  UTPB[6]  UTOPIA bus bit 6 input/output signal
+ * PD[4]   U16  UTPB[7]  UTOPIA bus bit 7 input/output signal
+ * PD[3]   W16  SOC      Start of cell input/output signal
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARK:
+ *
+ * The ATM parameters and data structures must be configured before
+ * initializing the UTOPIA port. The UTOPIA port activates immediately
+ * upon initialization, and if its associated data structures are not
+ * initialized, the CPM will lock up.
+ *
+ ****************************************************************************/
+void atmUtpInit()
+{
+  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
+  volatile iop8xx_t      *iop    = &immap->im_ioport;
+  volatile car8xx_t	 *car    = &immap->im_clkrst;
+  volatile cpm8xx_t	 *cpm    = &immap->im_cpm;
+  int flag;
+
+  flag = disable_interrupts();
+
+  /*-----------------------------------------------------------------*/
+  /* SCCR - System Clock Control Register                            */
+  /*                                                                 */
+  /* The UTOPIA clock can be selected to be internal clock or        */
+  /* external clock (selected by the UTOPIA mode register).          */
+  /* In case of internal clock, the UTOPIA clock is derived from     */
+  /* the system frequency divided by two dividers.                   */
+  /* Bits 27-31 of the SCCR register are defined to control the      */
+  /* UTOPIA clock.                                                   */
+  /*                                                                 */
+  /* SCCR[27:29] DFUTP  Division factor. Divide the system clock     */
+  /*                    by 2^DFUTP.                                  */
+  /* SCCR[30:31] DFAUTP Additional division factor. Divide the       */
+  /*                    system clock by the following value:         */
+  /*                    00 = divide by 1                             */
+  /*                    00 = divide by 3                             */
+  /*                    10 = divide by 5                             */
+  /*                    11 = divide by 7                             */
+  /*                                                                 */
+  /* Note that the UTOPIA clock must be programmed as to operate     */
+  /* within the range SYSCLK/10 .. 50MHz.                            */
+  /*-----------------------------------------------------------------*/
+  car->car_sccr &= 0xFFFFFFE0;
+  car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
+
+  /*-----------------------------------------------------------------*/
+  /* RCCR - RISC Controller Configuration Register                   */
+  /*                                                                 */
+  /* RCCR[8]     DR1M IDMA Request 0 Mode                            */
+  /*                  0 = edge sensitive                             */
+  /*                  1 = level sensitive                            */
+  /* RCCR[9]     DR0M IDMA Request 0 Mode                            */
+  /*                  0 = edge sensitive                             */
+  /*                  1 = level sensitive                            */
+  /* RCCR[10:11] DRQP IDMA Request Priority                          */
+  /*                  00 = IDMA req. have more prio. than SCCs       */
+  /*                  01 = IDMA req. have less prio. then SCCs       */
+  /*                  10 = IDMA requests have the lowest prio.       */
+  /*                  11 = reserved                                  */
+  /*                                                                 */
+  /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
+  /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
+  /* higher priority.                                                */
+  /*-----------------------------------------------------------------*/
+  cpm->cp_rccr &= 0xFF0F;
+  cpm->cp_rccr |= 0x00D0;
+
+  /*-----------------------------------------------------------------*/
+  /* Port B - TxClav Signal                                          */
+  /*-----------------------------------------------------------------*/
+  cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
+  cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
+
+  /*-----------------------------------------------------------------*/
+  /* UTOPIA Mode Register                                            */
+  /*                                                                 */
+  /* - muxed bus (master operation only)                             */
+  /* - multi PHY (because of a bug in the MPC860P rev.E.0)           */
+  /* - internal clock                                                */
+  /* - no loopback                                                   */
+  /* - do no activate statistical counters                           */
+  /*-----------------------------------------------------------------*/
+  iop->utmode = 0x00000004; SYNC;
+
+  /*-----------------------------------------------------------------*/
+  /* Port D - UTOPIA Data and Control Signals                        */
+  /*                                                                 */
+  /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals       */
+  /* 11    RXENB     UTOPIA receive enable input/output signal       */
+  /* 10    TXENB     UTOPIA transmit enable input/output signal      */
+  /* 9     TUPCLK    UTOPIA clock input/output signal                */
+  /* 8     MII-MDC   Used by MII in simult. MII and UTOPIA operation */
+  /* 7-4   UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals       */
+  /* 3     SOC       UTOPIA Start of cell input/output signal        */
+  /* 2               Reserved                                        */
+  /* 1               Enable UTOPIA mode                              */
+  /* 0               Enable SAR                                      */
+  /*-----------------------------------------------------------------*/
+  iop->iop_pdpar |= 0xDF7F; SYNC;
+  iop->iop_pddir &= 0x2080; SYNC;
+
+  /*-----------------------------------------------------------------*/
+  /* Port C - RxClav Signal                                          */
+  /*-----------------------------------------------------------------*/
+  iop->iop_pcpar  |= 0x0001; /* PCPAR[15] = 1 */
+  iop->iop_pcdir  &= 0xFFFE; /* PCDIR[15] = 0 */
+  iop->iop_pcso   &= 0xFFFE; /* PCSO[15]  = 0 */
+
+  if (flag)
+    enable_interrupts();
+}
diff --git a/u-boot/board/siemens/IAD210/atm.h b/u-boot/board/siemens/IAD210/atm.h
new file mode 100644
index 0000000..cd5b45e
--- /dev/null
+++ b/u-boot/board/siemens/IAD210/atm.h
@@ -0,0 +1,287 @@
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned int uint32;
+typedef volatile unsigned char vuint8;
+typedef volatile unsigned short vuint16;
+typedef volatile unsigned int vuint32;
+
+
+#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000
+
+#define ATM_DPRAM_BEGIN  (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000)
+#define NUM_CONNECTIONS  1
+#define SAR_RXB_SIZE     1584
+#define AM_HMASK         0x0FFFFFF0
+
+#define NUM_CT_ENTRIES           (NUM_CONNECTIONS)
+#define NUM_TCTE_ENTRIES         (NUM_CONNECTIONS)
+#define NUM_AM_ENTRIES           (NUM_CONNECTIONS+1)
+#define NUM_AP_ENTRIES           (NUM_CONNECTIONS+1)
+#define NUM_MPHYPT_ENTRIES       1
+#define NUM_APCP_ENTRIES         1
+#define NUM_APCT_PRIO_1_ENTRIES  146	/* Determines minimum rate */
+#define NUM_TQ_ENTRIES           12
+
+#define SIZE_OF_CT_ENTRY         64
+#define SIZE_OF_TCTE_ENTRY       32
+#define SIZE_OF_AM_ENTRY         4
+#define SIZE_OF_AP_ENTRY         2
+#define SIZE_OF_MPHYPT_ENTRY     2
+#define SIZE_OF_APCP_ENTRY       32
+#define SIZE_OF_APCT_ENTRY       2
+#define SIZE_OF_TQ_ENTRY         2
+
+#define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0)	/*64 */
+#define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY)	/*32 */
+#define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)	/*32 */
+#define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY)	/*4 */
+#define AM_BASE           (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
+#define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY)	/*2 */
+#define AP_BASE           (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
+#define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY)	/*2 */
+#define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY)	/*2 */
+#define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY)	/*2 */
+#define ATM_DPRAM_SIZE    ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
+
+#define CT_PTR(base)      ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
+#define TCTE_PTR(base)    ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
+#define AM_PTR(base)      ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
+#define AP_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
+#define MPHYPT_PTR(base)  ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
+#define APCP_PTR(base)    ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
+#define APCT1_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
+#define APCT2_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
+#define APCT3_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
+#define TQ_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
+
+/* SAR registers */
+#define RBDBASE(base)	  ((vuint32 *)(base + 0x3F00))	/* Base address of RxBD-List */
+#define SRFCR(base)	  ((vuint8 *)(base + 0x3F04))	/* DMA Receive function code */
+#define SRSTATE(base)	  ((vuint8 *)(base + 0x3F05))	/* DMA Receive status */
+#define MRBLR(base)	  ((vuint16 *)(base + 0x3F06))	/* Init to 0 for ATM */
+#define RSTATE(base)	  ((vuint32 *)(base + 0x3F08))	/* Do not write to */
+#define R_CNT(base)	  ((vuint16 *)(base + 0x3F10))	/* Do not write to */
+#define STFCR(base)	  ((vuint8 *)(base + 0x3F12))	/* DMA Transmit function code */
+#define STSTATE(base)	  ((vuint8 *)(base + 0x3F13))	/* DMA Transmit status */
+#define TBDBASE(base)	  ((vuint32 *)(base + 0x3F14))	/* Base address of TxBD-List */
+#define TSTATE(base)	  ((vuint32 *)(base + 0x3F18))	/* Do not write to */
+#define COMM_CH(base)	  ((vuint16 *)(base + 0x3F1C))	/* Command channel */
+#define STCHNUM(base)	  ((vuint16 *)(base + 0x3F1E))	/* Do not write to */
+#define T_CNT(base)	  ((vuint16 *)(base + 0x3F20))	/* Do not write to */
+#define CTBASE(base)	  ((vuint16 *)(base + 0x3F22))	/* Base address of Connection-table */
+#define ECTBASE(base)	  ((vuint32 *)(base + 0x3F24))	/* Valid only for external Conn.-table */
+#define INTBASE(base)	  ((vuint32 *)(base + 0x3F28))	/* Base address of Interrupt-table */
+#define INTPTR(base)	  ((vuint32 *)(base + 0x3F2C))	/* Pointer to Interrupt-queue */
+#define C_MASK(base)	  ((vuint32 *)(base + 0x3F30))	/* CRC-mask */
+#define SRCHNUM(base)	  ((vuint16 *)(base + 0x3F34))	/* Do not write to */
+#define INT_CNT(base)	  ((vuint16 *)(base + 0x3F36))	/* Interrupt-Counter */
+#define INT_ICNT(base)	  ((vuint16 *)(base + 0x3F38))	/* Interrupt threshold */
+#define TSTA(base)	  ((vuint16 *)(base + 0x3F3A))	/* Time-stamp-address */
+#define OLDLEN(base)	  ((vuint16 *)(base + 0x3F3C))	/* Do not write to */
+#define SMRBLR(base)	  ((vuint16 *)(base + 0x3F3E))	/* SAR max RXBuffer length */
+#define EHEAD(base)	  ((vuint32 *)(base + 0x3F40))	/* Valid for serial mode */
+#define EPAYLOAD(base)	  ((vuint32 *)(base + 0x3F44))	/* Valid for serial mode */
+#define TQBASE(base)	  ((vuint16 *)(base + 0x3F48))	/* Base address of Tx queue */
+#define TQEND(base)	  ((vuint16 *)(base + 0x3F4A))	/* End address of Tx queue */
+#define TQAPTR(base)	  ((vuint16 *)(base + 0x3F4C))	/* TQ APC pointer */
+#define TQTPTR(base)	  ((vuint16 *)(base + 0x3F4E))	/* TQ Tx pointer */
+#define APCST(base)	  ((vuint16 *)(base + 0x3F50))	/* APC status */
+#define APCPTR(base)	  ((vuint16 *)(base + 0x3F52))	/* APC parameter pointer */
+#define HMASK(base)	  ((vuint32 *)(base + 0x3F54))	/* Header mask */
+#define AMBASE(base)	  ((vuint16 *)(base + 0x3F58))	/* Address match table base */
+#define AMEND(base)	  ((vuint16 *)(base + 0x3F5A))	/* Address match table end */
+#define APBASE(base)	  ((vuint16 *)(base + 0x3F5C))	/* Address match parameter */
+#define FLBASE(base)	  ((vuint32 *)(base + 0x3F54))	/* First-level table base */
+#define SLBASE(base)	  ((vuint32 *)(base + 0x3F58))	/* Second-level table base */
+#define FLMASK(base)	  ((vuint16 *)(base + 0x3F5C))	/* First-level mask */
+#define ECSIZE(base)	  ((vuint16 *)(base + 0x3F5E))	/* Valid for extended mode */
+#define APCT_REAL(base)	  ((vuint32 *)(base + 0x3F60))	/* APC 32 bit counter */
+#define R_PTR(base)	  ((vuint32 *)(base + 0x3F64))	/* Do not write to */
+#define RTEMP(base)	  ((vuint32 *)(base + 0x3F68))	/* Do not write to */
+#define T_PTR(base)	  ((vuint32 *)(base + 0x3F6C))	/* Do not write to */
+#define TTEMP(base)	  ((vuint32 *)(base + 0x3F70))	/* Do not write to */
+
+/* ESAR registers */
+#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80))	/* Perf.Mon.Timestamp */
+#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84))	/* Perf.Mon.Template */
+#define PMPTR(base)       ((vuint16 *)(base + 0x3F88))	/* Perf.Mon.Table */
+#define PMCHANNEL(base)	  ((vuint16 *)(base + 0x3F8A))	/* Perf.Mon.Channel */
+#define MPHYST(base)	  ((vuint16 *)(base + 0x3F90))	/* Multi-PHY Status */
+#define TCTEBASE(base)	  ((vuint16 *)(base + 0x3F92))	/* Internal TCT Extension Base */
+#define ETCTEBASE(base)	  ((vuint32 *)(base + 0x3F94))	/* External TCT Extension Base */
+#define COMM_CH2(base)	  ((vuint32 *)(base + 0x3F98))	/* 2nd command channel word */
+#define STATBASE(base)	  ((vuint16 *)(base + 0x3F9C))	/* Statistics table pointer */
+
+/* UTOPIA Mode Register */
+#define UTMODE(base)      (CAST(vuint32 *)(base + 0x0978))
+
+/* SAR commands */
+#define TRANSMIT_CHANNEL_ACTIVATE_CMD   0x0FC1
+#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
+#define STOP_TRANSMIT_CMD               0x2FC1
+#define RESTART_TRANSMIT_CMD            0x3FC1
+#define STOP_RECEIVE_CMD                0x4FC1
+#define RESTART_RECEIVE_CMD             0x5FC1
+#define APC_BYPASS_CMD                  0x6FC1
+#define MEM_WRITE_CMD                   0x7FC1
+#define CPCR_FLG                        0x0001
+
+/* INT flags */
+#define INT_VALID	0x80000000
+#define INT_WRAP	0x40000000
+#define INT_APCO	0x00800000
+#define INT_TQF		0x00200000
+#define INT_RXF		0x00080000
+#define INT_BSY		0x00040000
+#define INT_TXB		0x00020000
+#define INT_RXB		0x00010000
+
+#define NUM_INT_ENTRIES   80
+#define SIZE_OF_INT_ENTRY 4
+
+struct apc_params_t {
+	vuint16 apct_base1;	/* APC Table - First Priority Base pointer */
+	vuint16 apct_end1;	/* First APC Table - Length */
+	vuint16 apct_ptr1;	/* First APC Table Pointer */
+	vuint16 apct_sptr1;	/* APC Table First Priority Service pointer */
+	vuint16 etqbase;	/* Enhanced Transmit Queue Base pointer */
+	vuint16 etqend;		/* Enhanced Transmit Queue End pointer */
+	vuint16 etqaptr;	/* Enhanced Transmit Queue APC pointer */
+	vuint16 etqtptr;	/* Enhanced Transmit Queue Transmitter pointer */
+	vuint16 apc_mi;		/* APC - Max Iteration */
+	vuint16 ncits;		/* Number of Cells In TimeSlot  */
+	vuint16 apcnt;		/* APC - N Timer */
+	vuint16 reserved1;	/* reserved */
+	vuint16 eapcst;		/* APC status */
+	vuint16 ptp_counter;	/* PTP queue length */
+	vuint16 ptp_txch;	/* PTP channel */
+	vuint16 reserved2;	/* reserved */
+};
+
+struct ct_entry_t {
+	/* RCT */
+	unsigned fhnt:1;
+	unsigned pm_rct:1;
+	unsigned reserved0:6;
+	unsigned hec:1;
+	unsigned clp:1;
+	unsigned cng_ncrc:1;
+	unsigned inf_rct:1;
+	unsigned cngi_ptp:1;
+	unsigned cdis_rct:1;
+	unsigned aal_rct:2;
+	uint16 rbalen;
+	uint32 rcrc;
+	uint32 rb_ptr;
+	uint16 rtmlen;
+	uint16 rbd_ptr;
+	uint16 rbase;
+	uint16 tstamp;
+	uint16 imask;
+	unsigned ft:2;
+	unsigned nim:1;
+	unsigned reserved1:2;
+	unsigned rpmt:6;
+	unsigned reserved2:5;
+	uint8 reserved3[8];
+	/* TCT */
+	unsigned reserved4:1;
+	unsigned pm_tct:1;
+	unsigned reserved5:6;
+	unsigned pc:1;
+	unsigned reserved6:2;
+	unsigned inf_tct:1;
+	unsigned cr10:1;
+	unsigned cdis_tct:1;
+	unsigned aal_tct:2;
+	uint16 tbalen;
+	uint32 tcrc;
+	uint32 tb_ptr;
+	uint16 ttmlen;
+	uint16 tbd_ptr;
+	uint16 tbase;
+	unsigned reserved7:5;
+	unsigned tpmt:6;
+	unsigned reserved8:3;
+	unsigned avcf:1;
+	unsigned act:1;
+	uint32 chead;
+	uint16 apcl;
+	uint16 apcpr;
+	unsigned out:1;
+	unsigned bnr:1;
+	unsigned tservice:2;
+	unsigned apcp:12;
+	uint16 apcpf;
+};
+
+struct tcte_entry_t {
+	unsigned res1:4;
+	unsigned scr:12;
+	uint16 scrf;
+	uint16 bt;
+	uint16 buptrh;
+	uint32 buptrl;
+	unsigned vbr2:1;
+	unsigned res2:15;
+	uint16 oobr;
+	uint16 res3[8];
+};
+
+#define SIZE_OF_RBD  12
+#define SIZE_OF_TBD  12
+
+struct atm_bd_t {
+	vuint16 flags;
+	vuint16 length;
+	unsigned char *buffer_ptr;
+	vuint16 cpcs_uu_cpi;
+	vuint16 reserved;
+};
+
+/* BD flags */
+#define EMPTY		0x8000
+#define READY		0x8000
+#define WRAP		0x2000
+#define INTERRUPT	0x1000
+#define LAST		0x0800
+#define FIRST		0x0400
+#define OAM             0x0400
+#define CONTINUOUS	0x0200
+#define HEC_ERROR	0x0080
+#define CELL_LOSS	0x0040
+#define CONGESTION	0x0020
+#define ABORT		0x0010
+#define LEN_ERROR	0x0002
+#define CRC_ERROR	0x0001
+
+struct atm_connection_t {
+	struct atm_bd_t *rbd_ptr;
+	int num_rbd;
+	struct atm_bd_t *tbd_ptr;
+	int num_tbd;
+	struct ct_entry_t *ct_ptr;
+	struct tcte_entry_t *tcte_ptr;
+	void *drv;
+	void (*notify) (void *drv, int event);
+};
+
+struct atm_driver_t {
+	int loaded;
+	int started;
+	char *csram;
+	int csram_size;
+	uint32 *am_top;
+	uint16 *ap_top;
+	uint32 *int_reload_ptr;
+	uint32 *int_serv_ptr;
+	struct atm_bd_t *rbd_base_ptr;
+	struct atm_bd_t *tbd_base_ptr;
+	unsigned linerate_in_bps;
+};
+
+extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
+extern struct atm_driver_t g_atm;
+
+extern int atmLoad (void);
+extern void atmUnload (void);
diff --git a/u-boot/board/siemens/IAD210/flash.c b/u-boot/board/siemens/IAD210/flash.c
new file mode 100644
index 0000000..c262e0f
--- /dev/null
+++ b/u-boot/board/siemens/IAD210/flash.c
@@ -0,0 +1,502 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  unsigned long size;
+  int i;
+
+  /* Init: no FLASHes known */
+  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+    flash_info[i].flash_id = FLASH_UNKNOWN;
+  }
+
+  /* Static FLASH Bank configuration here - FIXME XXX */
+
+  size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+  if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+    printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+  }
+
+
+  /* Remap FLASH according to real size */
+  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+  /* Re-do sizing to get full correct info */
+  size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+  flash_info[0].size = size;
+
+  return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+  int i;
+
+  /* set up sector start address table */
+  if (info->flash_id & FLASH_BTYPE) {
+    /* set sector offsets for bottom boot block type	*/
+    info->start[0] = base + 0x00000000;
+    info->start[1] = base + 0x00008000;
+    info->start[2] = base + 0x0000C000;
+    info->start[3] = base + 0x00010000;
+    for (i = 4; i < info->sector_count; i++) {
+      info->start[i] = base + (i * 0x00020000) - 0x00060000;
+    }
+  } else {
+    /* set sector offsets for top boot block type		*/
+    i = info->sector_count - 1;
+    info->start[i--] = base + info->size - 0x00008000;
+    info->start[i--] = base + info->size - 0x0000C000;
+    info->start[i--] = base + info->size - 0x00010000;
+    for (; i >= 0; i--) {
+      info->start[i] = base + i * 0x00020000;
+    }
+  }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+  int i;
+
+  if (info->flash_id == FLASH_UNKNOWN) {
+    printf ("missing or unknown FLASH type\n");
+    return;
+  }
+
+  switch (info->flash_id & FLASH_VENDMASK) {
+  case FLASH_MAN_AMD:	printf ("AMD ");		break;
+  case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+  default:		printf ("Unknown Vendor ");	break;
+  }
+
+  switch (info->flash_id & FLASH_TYPEMASK) {
+  case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+    break;
+  case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+    break;
+  case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+    break;
+  case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+    break;
+  default:		printf ("Unknown Chip Type\n");
+    break;
+  }
+
+  printf ("  Size: %ld MB in %d Sectors\n",
+	  info->size >> 20, info->sector_count);
+
+  printf ("  Sector Start Addresses:");
+  for (i=0; i<info->sector_count; ++i) {
+    if ((i % 5) == 0)
+      printf ("\n   ");
+    printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+	    );
+  }
+  printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+  short i;
+  ulong value;
+  ulong base = (ulong)addr;
+
+
+  /* Write auto select command: read Manufacturer ID */
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00900090;
+
+  value = addr[0];
+
+  switch (value) {
+  case AMD_MANUFACT:
+    info->flash_id = FLASH_MAN_AMD;
+    break;
+  case FUJ_MANUFACT:
+    info->flash_id = FLASH_MAN_FUJ;
+    break;
+  default:
+    info->flash_id = FLASH_UNKNOWN;
+    info->sector_count = 0;
+    info->size = 0;
+    return (0);			/* no or unknown flash	*/
+  }
+
+  value = addr[1];			/* device ID		*/
+
+  switch (value) {
+  case AMD_ID_LV400T:
+    info->flash_id += FLASH_AM400T;
+    info->sector_count = 11;
+    info->size = 0x00100000;
+    break;				/* => 1 MB		*/
+
+  case AMD_ID_LV400B:
+    info->flash_id += FLASH_AM400B;
+    info->sector_count = 11;
+    info->size = 0x00100000;
+    break;				/* => 1 MB		*/
+
+  case AMD_ID_LV800T:
+    info->flash_id += FLASH_AM800T;
+    info->sector_count = 19;
+    info->size = 0x00200000;
+    break;				/* => 2 MB		*/
+
+  case AMD_ID_LV800B:
+    info->flash_id += FLASH_AM800B;
+    info->sector_count = 19;
+    info->size = 0x00200000;
+    break;				/* => 2 MB		*/
+
+  case AMD_ID_LV160T:
+    info->flash_id += FLASH_AM160T;
+    info->sector_count = 35;
+    info->size = 0x00400000;
+    break;				/* => 4 MB		*/
+
+  case AMD_ID_LV160B:
+    info->flash_id += FLASH_AM160B;
+    info->sector_count = 35;
+    info->size = 0x00400000;
+    break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+  case AMD_ID_LV320T:
+    info->flash_id += FLASH_AM320T;
+    info->sector_count = 67;
+    info->size = 0x00800000;
+    break;				/* => 8 MB		*/
+
+  case AMD_ID_LV320B:
+    info->flash_id += FLASH_AM320B;
+    info->sector_count = 67;
+    info->size = 0x00800000;
+    break;				/* => 8 MB		*/
+#endif
+  default:
+    info->flash_id = FLASH_UNKNOWN;
+    return (0);			/* => no or unknown flash */
+
+  }
+
+  /* set up sector start address table */
+  if (info->flash_id & FLASH_BTYPE) {
+    /* set sector offsets for bottom boot block type	*/
+    info->start[0] = base + 0x00000000;
+    info->start[1] = base + 0x00008000;
+    info->start[2] = base + 0x0000C000;
+    info->start[3] = base + 0x00010000;
+    for (i = 4; i < info->sector_count; i++) {
+      info->start[i] = base + (i * 0x00020000) - 0x00060000;
+    }
+  } else {
+    /* set sector offsets for top boot block type		*/
+    i = info->sector_count - 1;
+    info->start[i--] = base + info->size - 0x00008000;
+    info->start[i--] = base + info->size - 0x0000C000;
+    info->start[i--] = base + info->size - 0x00010000;
+    for (; i >= 0; i--) {
+      info->start[i] = base + i * 0x00020000;
+    }
+  }
+
+  /* check for protected sectors */
+  for (i = 0; i < info->sector_count; i++) {
+    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+    /* D0 = 1 if protected */
+    addr = (volatile unsigned long *)(info->start[i]);
+    info->protect[i] = addr[2] & 1;
+  }
+
+  /*
+   * Prevent writes to uninitialized FLASH.
+   */
+  if (info->flash_id != FLASH_UNKNOWN) {
+    addr = (volatile unsigned long *)info->start[0];
+
+    *addr = 0x00F000F0;	/* reset bank */
+  }
+
+  return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  int flag, prot, sect, l_sect;
+  ulong start, now, last;
+
+  if ((s_first < 0) || (s_first > s_last)) {
+    if (info->flash_id == FLASH_UNKNOWN) {
+      printf ("- missing\n");
+    } else {
+      printf ("- no sectors to erase\n");
+    }
+    return 1;
+  }
+
+  if ((info->flash_id == FLASH_UNKNOWN) ||
+      (info->flash_id > FLASH_AMD_COMP)) {
+    printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+    return 1;
+  }
+
+  prot = 0;
+  for (sect=s_first; sect<=s_last; ++sect) {
+    if (info->protect[sect]) {
+      prot++;
+    }
+  }
+
+  if (prot) {
+    printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+  } else {
+    printf ("\n");
+  }
+
+  l_sect = -1;
+
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00800080;
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+
+  /* Start erase on unprotected sectors */
+  for (sect = s_first; sect<=s_last; sect++) {
+    if (info->protect[sect] == 0) {	/* not protected */
+      addr = (vu_long*)(info->start[sect]);
+      addr[0] = 0x00300030;
+      l_sect = sect;
+    }
+  }
+
+  /* re-enable interrupts if necessary */
+  if (flag)
+    enable_interrupts();
+
+  /* wait at least 80us - let's wait 1 ms */
+  udelay (1000);
+
+  /*
+   * We wait for the last triggered sector
+   */
+  if (l_sect < 0)
+    goto DONE;
+
+  start = get_timer (0);
+  last  = start;
+  addr = (vu_long*)(info->start[l_sect]);
+  while ((addr[0] & 0x00800080) != 0x00800080) {
+    if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+      printf ("Timeout\n");
+      return 1;
+    }
+    /* show that we're waiting */
+    if ((now - last) > 1000) {	/* every second */
+      putc ('.');
+      last = now;
+    }
+  }
+
+ DONE:
+  /* reset to read mode */
+  addr = (volatile unsigned long *)info->start[0];
+  addr[0] = 0x00F000F0;	/* reset bank */
+
+  printf (" done\n");
+  return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+  ulong cp, wp, data;
+  int i, l, rc;
+
+  wp = (addr & ~3);	/* get lower word aligned address */
+
+  /*
+   * handle unaligned start bytes
+   */
+  if ((l = addr - wp) != 0) {
+    data = 0;
+    for (i=0, cp=wp; i<l; ++i, ++cp) {
+      data = (data << 8) | (*(uchar *)cp);
+    }
+    for (; i<4 && cnt>0; ++i) {
+      data = (data << 8) | *src++;
+      --cnt;
+      ++cp;
+    }
+    for (; cnt==0 && i<4; ++i, ++cp) {
+      data = (data << 8) | (*(uchar *)cp);
+    }
+
+    if ((rc = write_word(info, wp, data)) != 0) {
+      return (rc);
+    }
+    wp += 4;
+  }
+
+  /*
+   * handle word aligned part
+   */
+  while (cnt >= 4) {
+    data = 0;
+    for (i=0; i<4; ++i) {
+      data = (data << 8) | *src++;
+    }
+    if ((rc = write_word(info, wp, data)) != 0) {
+      return (rc);
+    }
+    wp  += 4;
+    cnt -= 4;
+  }
+
+  if (cnt == 0) {
+    return (0);
+  }
+
+  /*
+   * handle unaligned tail bytes
+   */
+  data = 0;
+  for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+    data = (data << 8) | *src++;
+    --cnt;
+  }
+  for (; i<4; ++i, ++cp) {
+    data = (data << 8) | (*(uchar *)cp);
+  }
+
+  return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  ulong start;
+  int flag;
+
+  /* Check if Flash is (sufficiently) erased */
+  if ((*((vu_long *)dest) & data) != data) {
+    return (2);
+  }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00A000A0;
+
+  *((vu_long *)dest) = data;
+
+  /* re-enable interrupts if necessary */
+  if (flag)
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+    if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+      return (1);
+    }
+  }
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/siemens/IAD210/u-boot.lds b/u-boot/board/siemens/IAD210/u-boot.lds
new file mode 100644
index 0000000..0514f5a
--- /dev/null
+++ b/u-boot/board/siemens/IAD210/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    net/libnet.o			(.text*)
+    drivers/rtc/librtc.o		(.text*)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/siemens/SCM/Makefile b/u-boot/board/siemens/SCM/Makefile
new file mode 100644
index 0000000..3871079
--- /dev/null
+++ b/u-boot/board/siemens/SCM/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+$(shell mkdir -p $(obj)../../tqc/tqm8xx)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= scm.o flash.o fpga_scm.o ../common/fpga.o \
+	  ../../tqc/tqm8xx/load_sernum_ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/siemens/SCM/flash.c b/u-boot/board/siemens/SCM/flash.c
new file mode 100644
index 0000000..4a6d538
--- /dev/null
+++ b/u-boot/board/siemens/SCM/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD devices on the TQM8260 board
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
+		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
+	flashtest_l = V_ULONG (baseaddr + 4);
+
+	switch ((int) flashtest_h) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash     */
+	}
+
+	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
+	flashtest_l = V_ULONG (baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+	} else {
+		switch (flashtest_h) {
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_DL322T:
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL322B:
+			info->flash_id += FLASH_AMDL322B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323T:
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323B:
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_LV640U:
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x02000000;
+			break;			/* 4 * 8 MB = 32 MB */
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);		/* no or unknown flash     */
+		}
+	}
+
+	if (flashtest_h == AMD_ID_LV640U) {
+
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+
+	} else {
+
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
+			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG (info->start[sect]) = 0x00300030;
+			V_ULONG (info->start[sect] + 4) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start, cl, ch;
+	int flag, i;
+
+	for (ch = 0, i = 0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word    */
+	for (cl = 0, i = 0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & ch) != ch
+		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest) = ch;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest + 4) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
+		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/u-boot/board/siemens/SCM/fpga_scm.c b/u-boot/board/siemens/SCM/fpga_scm.c
new file mode 100644
index 0000000..acd9c15
--- /dev/null
+++ b/u-boot/board/siemens/SCM/fpga_scm.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8260.h>
+#include <common.h>
+#include "../common/fpga.h"
+
+fpga_t fpga_list[] = {
+	{"FIOX", CONFIG_SYS_FIOX_BASE,
+	 CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE}
+	,
+	{"FDOHM", CONFIG_SYS_FDOHM_BASE,
+	 CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE}
+};
+int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
+
+
+ulong fpga_control (fpga_t * fpga, int cmd)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	switch (cmd) {
+	case FPGA_INIT_IS_HIGH:
+		immr->im_ioport.iop_pdird &= ~fpga->init_mask;	/* input */
+		return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
+
+	case FPGA_INIT_SET_LOW:
+		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
+		immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
+		break;
+
+	case FPGA_INIT_SET_HIGH:
+		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
+		immr->im_ioport.iop_pdatd |= fpga->init_mask;
+		break;
+
+	case FPGA_PROG_SET_LOW:
+		immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
+		break;
+
+	case FPGA_PROG_SET_HIGH:
+		immr->im_ioport.iop_pdatd |= fpga->prog_mask;
+		break;
+
+	case FPGA_DONE_IS_HIGH:
+		return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
+
+	case FPGA_READ_MODE:
+		break;
+
+	case FPGA_LOAD_MODE:
+		break;
+
+	case FPGA_GET_ID:
+		if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) {
+			ulong ver =
+				*(volatile ulong *) (fpga->conf_base + 0x10);
+			return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
+		} else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) {
+			return (*(volatile ushort *) fpga->conf_base) & 0xff;
+		} else {
+			return *(volatile ulong *) fpga->conf_base;
+		}
+
+	case FPGA_INIT_PORTS:
+		immr->im_ioport.iop_ppard &= ~fpga->init_mask;	/* INIT I/O */
+		immr->im_ioport.iop_psord &= ~fpga->init_mask;
+		immr->im_ioport.iop_pdird &= ~fpga->init_mask;
+
+		immr->im_ioport.iop_ppard &= ~fpga->prog_mask;	/* PROG Output */
+		immr->im_ioport.iop_psord &= ~fpga->prog_mask;
+		immr->im_ioport.iop_pdird |= fpga->prog_mask;
+
+		immr->im_ioport.iop_ppard &= ~fpga->done_mask;	/* DONE Input */
+		immr->im_ioport.iop_psord &= ~fpga->done_mask;
+		immr->im_ioport.iop_pdird &= ~fpga->done_mask;
+
+		break;
+
+	}
+	return 0;
+}
diff --git a/u-boot/board/siemens/SCM/scm.c b/u-boot/board/siemens/SCM/scm.c
new file mode 100644
index 0000000..926e491
--- /dev/null
+++ b/u-boot/board/siemens/SCM/scm.c
@@ -0,0 +1,540 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include "scm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void config_scoh_cs(void);
+extern int  fpga_init(void);
+
+#if 0
+#define DEBUGF(fmt,args...)   printf (fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1]*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA9  */ {   1,   1,   1,   1,   0,   0   }, /* TDM_A1 L1TXD0 */
+	/* PA8  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RXD0 */
+	/* PA7  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1TSYNC */
+	/* PA6  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RSYNC */
+	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* FIOX_FPGA_PR */
+	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* DOHM_FPGA_PR */
+	/* PA3  */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK4 */
+	/* PA2  */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK4 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   },
+	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* BUSY */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MIN */
+	/* PB30 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MAJ */
+	/* PB29 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MIN */
+	/* PB28 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MAJ */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB25 */ {   1,   0,   0,   1,   0,   0   }, /* LED_GREEN_L */
+	/* PB24 */ {   1,   0,   0,   1,   0,   0   }, /* LED_RED_L */
+	/* PB23 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TXD */
+	/* PB22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RXD */
+	/* PB21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TSYNC */
+	/* PB20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RSYNC */
+	/* PB19 */ {   1,   0,   0,   0,   0,   0   }, /* UID */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK1 */
+	/* PC30 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK1 */
+	/* PC29 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK3 */
+	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK3 */
+	/* PC27 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK2 */
+	/* PC26 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK2 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   },
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC18 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* RES_PHY_L */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC9  */ {   0,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TSYNC */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* FEP_RDY */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* UC4_ALARM_L */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* UC3_ALARM_L */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* UC2_ALARM_L */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* RES_MISC_L */
+	/* PC2  */ {   0,   0,   0,   1,   0,   0   }, /* RES_OH_L */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* RES_DOHM_L */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* RES_FIOX_L */
+    },
+
+    /* Port D configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_F */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_F */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_D */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_D */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TXD */
+	/* PD21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RXD */
+	/* PD20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RSYNC */
+	/* PD19 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPISEL */
+	/* PD18 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPICLK */
+	/* PD17 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSI */
+	/* PD16 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSO */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TXD */
+	/* PD12 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RXD */
+	/* PD11 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TSYNC */
+	/* PD10 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RSYNC */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   },
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   },
+	/* PD5  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_F */
+	/* PD4  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_D */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "TQM8260", 7)) {
+		puts ("### No HW ID - assuming TQM8260\n");
+		return (0);
+	}
+
+	puts (str);
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+/*
+ * Test Power-On-Reset.
+ */
+int power_on_reset (void)
+{
+	/* Test Reset Status Register */
+	return gd->reset_status & RSR_CSRS ? 0 : 1;
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#if 0							/* Just for debugging */
+#define	prt_br_or(brX,orX) do {				\
+    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
+    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
+    printf ("\n"					\
+	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
+	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
+	start, start+sizem, (sizem+1)>>20);		\
+    } while (0)
+	prt_br_or (br0, or0);
+	prt_br_or (br1, or1);
+	prt_br_or (br2, or2);
+	prt_br_or (br3, or3);
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+	/* Local SDRAM setup:
+	 */
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
+	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+
+	if (size8 < size9) {
+		lsize = size9;
+		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
+	} else {
+		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
+						  (uchar *) SDRAM_BASE2_PRELIM);
+		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
+	}
+
+#if 0
+	/* Set up BR2 so that the local SDRAM goes
+	 * right after the 60x SDRAM
+	 */
+	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CONFIG_SYS_SDRAM_BASE + psize);
+#endif
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	config_scoh_cs ();
+
+	return (psize);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void config_scoh_cs (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
+	volatile uint tmp, i;
+
+	/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
+	memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
+	memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
+	/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
+	memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
+	memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
+
+	/* Initialize MAMR to write in the array at address 0x0 */
+	memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
+
+	/* Initialize UPMA for CAN: single read */
+	memctl->memc_mdr = 0xcffeec00;
+	udelay (1);					/* Necessary to have the data correct in the UPM array!!!! */
+	/* The read on the CAN controller write the data of mdr in UPMA array. */
+	/* The index to the array will be incremented automatically
+	   through this read */
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcfc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcfc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0xfffdec07;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+
+	/* Initialize MAMR to write in the array at address 0x18 */
+	memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
+
+	/* Initialize UPMA for CAN: single write */
+	memctl->memc_mdr = 0xfcffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00fffc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00fffc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x30ffec07;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	/* Initialize MAMR */
+	memctl->memc_mamr = MxMR_GPL_x4DIS;	/* GPL_B4 ouput line Disable */
+
+
+	/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
+	memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
+	memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
+	/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
+	memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
+	memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
+
+	/* Initialize OR7 / BR7 for the Glue Logic */
+	memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
+	memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
+
+	/* Initialize OR8 / BR8 for the DOH Logic */
+	memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
+	memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
+
+	DEBUGF ("OR0 %08x   BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
+	DEBUGF ("OR1 %08x   BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
+	DEBUGF ("OR2 %08x   BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
+	DEBUGF ("OR3 %08x   BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
+	DEBUGF ("OR4 %08x   BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
+	DEBUGF ("OR5 %08x   BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
+	DEBUGF ("OR6 %08x   BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
+	DEBUGF ("OR7 %08x   BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
+	DEBUGF ("OR8 %08x   BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
+
+	DEBUGF ("UPMA  addr 0x0\n");
+	memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
+	for (i = 0; i < 0x8; i++) {
+		tmp = can->cpu_interface;
+		udelay (1);
+		DEBUGF (" %08x ", memctl->memc_mdr);
+	}
+	DEBUGF ("\nUPMA  addr 0x18\n");
+	memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
+	for (i = 0; i < 0x8; i++) {
+		tmp = can->cpu_interface;
+		udelay (1);
+		DEBUGF (" %08x ", memctl->memc_mdr);
+	}
+	DEBUGF ("\n");
+	memctl->memc_mamr = MxMR_GPL_x4DIS;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r (void)
+{
+	fpga_init ();
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/siemens/SCM/scm.h b/u-boot/board/siemens/SCM/scm.h
new file mode 100644
index 0000000..cb5e03e
--- /dev/null
+++ b/u-boot/board/siemens/SCM/scm.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SCM_H
+#define __SCM_H
+
+/*----------------*/
+/* CAN Structures */
+/*----------------*/
+
+/* Message */
+struct can_msg {
+    uchar	ctrl_0;
+    uchar	ctrl_1;
+    uchar	arbit_0;
+    uchar	arbit_1;
+    uchar	arbit_2;
+    uchar	arbit_3;
+    uchar	config;
+    uchar	data[8];
+} __attribute__ ((packed));
+
+typedef struct can_msg can_msg_t;
+
+/* CAN Register */
+typedef struct can_reg {
+    uchar	ctrl;
+    uchar	status;
+    uchar	cpu_interface;
+    uchar	resv0;
+    ushort	high_speed_rd;
+    ushort	gbl_mask_std;
+    uint	gbl_mask_extd;
+    uint	msg15_mask;
+    can_msg_t	msg1;
+    uchar	clkout;
+    can_msg_t	msg2;
+    uchar	bus_config;
+    can_msg_t	msg3;
+    uchar	bit_timing_0;
+    can_msg_t	msg4;
+    uchar	bit_timing_1;
+    can_msg_t	msg5;
+    uchar	interrupt;
+    can_msg_t	msg6;
+    uchar	resv1;
+    can_msg_t	msg7;
+    uchar	resv2;
+    can_msg_t	msg8;
+    uchar	resv3;
+    can_msg_t	msg9;
+    uchar	p1conf;
+    can_msg_t	msg10;
+    uchar	p2conf;
+    can_msg_t	msg11;
+    uchar	p1in;
+    can_msg_t	msg12;
+    uchar	p2in;
+    can_msg_t	msg13;
+    uchar	p1out;
+    can_msg_t	msg14;
+    uchar	p2out;
+    can_msg_t	msg15;
+    uchar	ser_res_addr;
+    uchar	resv_cs[0x8000-0x100];	/* 0x8000 is the min size for CS */
+} can_reg_t;
+
+
+#endif /* __SCM_H */
diff --git a/u-boot/board/siemens/SMN42/Makefile b/u-boot/board/siemens/SMN42/Makefile
new file mode 100644
index 0000000..c054a3e
--- /dev/null
+++ b/u-boot/board/siemens/SMN42/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= flash.o smn42.o
+SOBJTS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJTS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJTS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/siemens/SMN42/config.mk b/u-boot/board/siemens/SMN42/config.mk
new file mode 100644
index 0000000..4891792
--- /dev/null
+++ b/u-boot/board/siemens/SMN42/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+#CONFIG_SYS_TEXT_BASE = 0x0
+CONFIG_SYS_TEXT_BASE = 0x81500000
diff --git a/u-boot/board/siemens/SMN42/flash.c b/u-boot/board/siemens/SMN42/flash.c
new file mode 100644
index 0000000..fc91574
--- /dev/null
+++ b/u-boot/board/siemens/SMN42/flash.c
@@ -0,0 +1,475 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * (C) Copyright 2007 Gary Jennejohn garyj@denx.de
+ * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c.
+ * Heavily modified to support the SMN42 board from Siemens
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <asm/arch/hardware.h>
+
+static unsigned long flash_addr_table[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS_LIST;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
+extern int lpc2292_flash_erase(flash_info_t *, int, int);
+extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong);
+static unsigned long ext_flash_init(void);
+static int ext_flash_erase(flash_info_t *, int, int);
+static int ext_write_buff(flash_info_t *, uchar *, ulong, ulong);
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int j, k;
+	ulong size = 0;
+	ulong flashbase = 0;
+
+	flash_info[0].flash_id = PHILIPS_LPC2292;
+	flash_info[0].size = 0x003E000;	/* 256 - 8 KB */
+	flash_info[0].sector_count = 17;
+	memset (flash_info[0].protect, 0, 17);
+	flashbase = 0x00000000;
+	for (j = 0, k = 0; j < 8; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	for (j = 0; j < 2; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00010000;
+	}
+	for (j = 0; j < 7; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	size += flash_info[0].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect (FLAG_PROTECT_SET,
+		 0x0,
+		 0x0 + monitor_flash_len - 1,
+		 &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		 CONFIG_ENV_ADDR,
+		 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		 &flash_info[0]);
+
+	size += ext_flash_init();
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int erased = 0;
+	unsigned long j;
+	unsigned long count;
+	unsigned char *p;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+		printf("Philips: ");
+		break;
+	case FLASH_MAN_AMD:
+		printf("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
+		printf("LPC2292 internal flash\n");
+		break;
+	case FLASH_S29GL128N:
+		printf ("S29GL128N (128 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+	  info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		if (i < (info->sector_count - 1)) {
+			count = info->start[i+1] - info->start[i];
+		}
+		else {
+			count = info->start[0] + info->size - info->start[i];
+		}
+		p = (unsigned char*)(info->start[i]);
+		erased = 1;
+		for (j = 0; j < count; j++) {
+			if (*p != 0xFF) {
+				erased = 0;
+				break;
+			}
+			p++;
+		}
+		printf (" %08lX%s%s", info->start[i], info->protect[i] ? " RO" : "   ",
+			erased ? " E" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
+			return lpc2292_flash_erase(info, s_first, s_last);
+		case FLASH_S29GL128N:
+			return ext_flash_erase(info, s_first, s_last);
+		default:
+			return ERR_PROTECTED;
+	}
+	return ERR_PROTECTED;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
+			return lpc2292_write_buff(info, src, addr, cnt);
+		case FLASH_S29GL128N:
+			return ext_write_buff(info, src, addr, cnt);
+		default:
+			return ERR_PROG_ERROR;
+	}
+	return ERR_PROG_ERROR;
+}
+
+/*--------------------------------------------------------------------------
+ * From here on is code for the external S29GL128N taken from cam5200_flash.c
+ */
+
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+int ext_flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect, ret;
+
+	ret = 0;
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			ret = wait_for_DQ7_32(info, sect);
+			if (ret) {
+				ret = ERR_PROTECTED;
+				break;
+			}
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	if (ret)
+		printf(" error\n");
+	else
+		printf(" done\n");
+	return ret;
+}
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_MIRROR:
+			value = addr2[14];
+			switch(value) {
+				case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_2:
+					value = addr2[15];
+					if (value != (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_3) {
+						info->flash_id = FLASH_UNKNOWN;
+					} else {
+						info->flash_id += FLASH_S29GL128N;
+						info->sector_count = 128;
+						info->size = 0x01000000;
+					}
+					break;
+				default:
+					info->flash_id = FLASH_UNKNOWN;
+					return(0);
+			}
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00020000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static unsigned long ext_flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i+1, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+static int write_word(flash_info_t * info, ulong dest, ushort data)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) &data;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & *data2) != *data2) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+	*dest2 = *data2;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*dest2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(*data2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			printf("WRITE_TOUT\n");
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * This is taken from the original flash.c for the LPC2292 SODIMM board
+ * and modified to suit.
+ */
+
+int ext_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ushort tmp;
+	ulong i;
+	uchar* src_org;
+	uchar* dst_org;
+	ulong cnt_org = cnt;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar*)addr;
+
+	if (addr & 1) {		/* if odd address */
+		tmp = *((uchar*)(addr - 1)); /* little endian */
+		tmp |= (*src << 8);
+		if (write_word(info, addr - 1, tmp))
+			return ERR_PROG_ERROR;
+		addr += 1;
+		cnt -= 1;
+		src++;
+	}
+	while (cnt > 1) {
+		tmp = ((*(src+1)) << 8) + (*src); /* little endian */
+		if (write_word(info, addr, tmp))
+			return ERR_PROG_ERROR;
+		addr += 2;
+		src += 2;
+		cnt -= 2;
+	}
+	if (cnt > 0) {
+		tmp = (*((uchar*)(addr + 1))) << 8;
+		tmp |= *src;
+		if (write_word(info, addr, tmp))
+			return ERR_PROG_ERROR;
+	}
+
+	for (i = 0; i < cnt_org; i++) {
+		if (*dst_org != *src_org) {
+			printf("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	return ret;
+}
diff --git a/u-boot/board/siemens/SMN42/lowlevel_init.S b/u-boot/board/siemens/SMN42/lowlevel_init.S
new file mode 100644
index 0000000..44e209b
--- /dev/null
+++ b/u-boot/board/siemens/SMN42/lowlevel_init.S
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * Slight modifications made to support the SMN42 board from Siemens.
+ * 2007 Gary Jennejohn garyj@denx.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+/* some parameters for the board */
+/* setting up the CPU-internal memory */
+#define	SRAM_START	0x40000000
+#define	SRAM_SIZE	0x00004000
+#define BCFG0_VALUE	0x1000ffef
+#define BCFG1_VALUE	0x10005D2F
+#define BCFG2_VALUE	0x10005D2F
+/*
+ * For P0.18 to set ZZ to the SRAMs to 1. Also set P0.2 (SCL) and P0.3 (SDA)
+ * for the bit-banger I2C driver correctly.
+ */
+#define   IO0_VALUE   0x4000C
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+MEMMAP_ADR:
+	.word	MEMMAP
+BCFG0_ADR:
+	.word BCFG0
+_BCFG0_VALUE:
+	.word BCFG0_VALUE
+BCFG1_ADR:
+	.word	BCFG1
+_BCFG1_VALUE:
+	.word	BCFG1_VALUE
+BCFG2_ADR:
+	.word	BCFG2
+_BCFG2_VALUE:
+	.word	BCFG2_VALUE
+IO0DIR_ADR:
+	.word	IO0DIR
+_IO0DIR_VALUE:
+	.word	IO0_VALUE
+IO0SET_ADR:
+	.word	IO0SET
+_IO0SET_VALUE:
+	.word	IO0_VALUE
+PINSEL2_ADR:
+	.word	PINSEL2
+PINSEL2_MASK:
+	.word	0x00000000
+PINSEL2_VALUE:
+	.word	0x0F804914
+
+.extern _start
+
+.globl lowlevel_init
+lowlevel_init:
+	/* set up memory control register for bank 0 */
+	ldr r0, _BCFG0_VALUE
+	ldr r1, BCFG0_ADR
+	str r0, [r1]
+
+	/* set up memory control register for bank 1 */
+	ldr	r0, _BCFG1_VALUE
+	ldr	r1, BCFG1_ADR
+	str	r0, [r1]
+
+	/* set up memory control register for bank 2 */
+	ldr	r0, _BCFG2_VALUE
+	ldr	r1, BCFG2_ADR
+	str	r0, [r1]
+
+	/* set IO0DIR to make P0.2, P0.3  and P0.18 outputs */
+	ldr	r0, _IO0DIR_VALUE
+	ldr	r1, IO0DIR_ADR
+	str	r0, [r1]
+
+	/* set P0.18 to 1 */
+	ldr	r0, _IO0SET_VALUE
+	ldr	r1, IO0SET_ADR
+	str	r0, [r1]
+
+	/* set up PINSEL2 for bus-pins */
+	ldr	r0, PINSEL2_ADR
+	ldr	r1, [r0]
+	ldr	r2, PINSEL2_MASK
+	ldr	r3, PINSEL2_VALUE
+	and	r1, r1, r2
+	orr	r1, r1, r3
+	str	r1, [r0]
+
+	/* move vectors to beginning of SRAM */
+	mov	r2, #SRAM_START
+	mov	r0, #0 /*_start*/
+	ldmneia r0!, {r3-r10}
+	stmneia r2!, {r3-r10}
+	ldmneia r0, {r3-r9}
+	stmneia r2, {r3-r9}
+
+	/* Set-up MEMMAP register, so vectors are taken from SRAM */
+	ldr	r0, MEMMAP_ADR
+	mov	r1, #0x02	/* vectors re-mapped to static RAM */
+	str	r1, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/u-boot/board/siemens/SMN42/smn42.c b/u-boot/board/siemens/SMN42/smn42.c
new file mode 100644
index 0000000..52d1d7e
--- /dev/null
+++ b/u-boot/board/siemens/SMN42/smn42.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * (C) Copyright 2007 Gary Jennejohn <garyj@denx.de>
+ * Siemens board SMN42
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number MACH_TYPE_ARMADILLO - not official*/
+	gd->bd->bi_arch_number = 83;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x00000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/u-boot/board/siemens/common/README b/u-boot/board/siemens/common/README
new file mode 100644
index 0000000..7f1c8cd
--- /dev/null
+++ b/u-boot/board/siemens/common/README
@@ -0,0 +1,27 @@
+CCM/SCM-Ergaenzungen fuer U-Boot und Linux:
+-------------------------------------------
+
+Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
+
+  => help fpga
+  fpga fpga status [name] - print FPGA status
+  fpga reset  [name] - reset FPGA
+  fpga load [name] addr - load FPGA configuration data
+
+Der Name kann beim CCM-Module auch weggelassen werden.
+Die Laengenangabe und damit "puma_len" ist nicht mehr
+noetig:
+
+  => fpga load puma 40600000
+  FPGA load PUMA: addr 40600000: (00000005)... done
+
+Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
+geben werden:
+
+  => printenv addmtd
+  addmtd=setenv bootargs ${bootargs}
+    mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
+
+Die Portierung auf SMC ist natuerlich noch nicht getestet.
+
+Wolfgang Grandegger (04.06.2002)
diff --git a/u-boot/board/siemens/common/fpga.c b/u-boot/board/siemens/common/fpga.c
new file mode 100644
index 0000000..ef8bfde
--- /dev/null
+++ b/u-boot/board/siemens/common/fpga.c
@@ -0,0 +1,369 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <common.h>
+
+#include "fpga.h"
+
+int  power_on_reset(void);
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+
+static int fpga_get_version(fpga_t* fpga, char* name)
+{
+    char vname[12];
+    /*
+     * Net-list string format:
+     *     "vvvvvvvvddddddddn...".
+     *     Version Date    Name
+     *     "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
+     */
+    if (strlen(name) < (16 + strlen(fpga->name)))
+	goto failure;
+    /* Check FPGA name */
+    if (strcmp(&name[16], fpga->name) != 0)
+	goto failure;
+    /* Get version number */
+    memcpy(vname, name, 8);
+    vname[8] = '\0';
+    return simple_strtoul(vname, NULL, 16);
+
+ failure:
+    printf("Image name %s is invalid\n", name);
+    return -1;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static fpga_t* fpga_get(char* fpga_name)
+{
+    char name[FPGA_NAME_LEN];
+    int i;
+
+    if (strlen(fpga_name) >= FPGA_NAME_LEN)
+	goto failure;
+    for (i = 0; i < strlen(fpga_name); i++)
+	name[i] = toupper(fpga_name[i]);
+    name[i] = '\0';
+    for (i = 0; i < fpga_count; i++) {
+	if (strcmp(name, fpga_list[i].name) == 0)
+	    return &fpga_list[i];
+    }
+ failure:
+    printf("FPGA: name %s is invalid\n", fpga_name);
+    return NULL;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void fpga_status (fpga_t* fpga)
+{
+    /* Check state */
+    if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
+	printf ("%s is loaded (%08lx)\n",
+		fpga->name, fpga_control(fpga, FPGA_GET_ID));
+    else
+	printf ("%s is NOT loaded\n", fpga->name);
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
+
+static int fpga_reset (fpga_t* fpga)
+{
+    int i;
+
+    /* Set PROG to low and wait til INIT goes low */
+    fpga_control(fpga, FPGA_PROG_SET_LOW);
+    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
+	udelay (100);
+	if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_RESET_TIMEOUT)
+	goto failure;
+
+    /* Set PROG to high and wait til INIT goes high */
+    fpga_control(fpga, FPGA_PROG_SET_HIGH);
+    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
+	udelay (100);
+	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_RESET_TIMEOUT)
+	goto failure;
+
+    return 0;
+ failure:
+    return 1;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
+
+static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
+{
+    volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
+    image_header_t *hdr = (image_header_t *)addr;
+    ulong len;
+    uchar *data;
+    char msg[32];
+    int verify, i;
+
+#if defined(CONFIG_FIT)
+    if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+	puts ("Non legacy image format not supported\n");
+	return -1;
+    }
+#endif
+
+    /*
+     * Check the image header and data of the net-list
+     */
+    if (!image_check_magic (hdr)) {
+	strcpy (msg, "Bad Image Magic Number");
+	goto failure;
+    }
+
+    if (!image_check_hcrc (hdr)) {
+	strcpy (msg, "Bad Image Header CRC");
+	goto failure;
+    }
+
+    data = (uchar*)image_get_data (hdr);
+    len  = image_get_data_size (hdr);
+
+    verify = getenv_yesno ("verify");
+    if (verify) {
+	if (!image_check_dcrc (hdr)) {
+	    strcpy (msg, "Bad Image Data CRC");
+	    goto failure;
+	}
+    }
+
+    if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
+	return 1;
+
+    /* align length */
+    if (len & 1)
+	++len;
+
+    /*
+     * Reset FPGA and wait for completion
+     */
+    if (fpga_reset(fpga)) {
+	strcpy (msg, "Reset Timeout");
+	goto failure;
+    }
+
+    printf ("(%s)... ", image_get_name (hdr));
+    /*
+     * Copy data to FPGA
+     */
+    fpga_control (fpga, FPGA_LOAD_MODE);
+    while (len--) {
+	*fpga_addr = *data++;
+    }
+    fpga_control (fpga, FPGA_READ_MODE);
+
+    /*
+     * Wait for completion and check error status if timeout
+     */
+    for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
+	udelay (100);
+	if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_LOAD_TIMEOUT) {
+	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    strcpy(msg, "Invalid Size");
+	else
+	    strcpy(msg, "CRC Error");
+	goto failure;
+    }
+
+    printf("done\n");
+    return 0;
+
+ failure:
+
+    printf("ERROR: %s\n", msg);
+    return 1;
+}
+
+#if defined(CONFIG_CMD_BSP)
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+    ulong addr = 0;
+    int i;
+    fpga_t* fpga;
+
+    if (argc < 2)
+	goto failure;
+
+    if (strncmp(argv[1], "stat", 4) == 0) {		/* status */
+	if (argc == 2) {
+	    for (i = 0; i < fpga_count; i++) {
+		fpga_status (&fpga_list[i]);
+	    }
+	}
+	else if (argc == 3) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	    fpga_status (fpga);
+	}
+	else
+	    goto failure;
+    }
+    else if (strcmp(argv[1],"load") == 0) {		/* load */
+	if (argc == 3 && fpga_count == 1) {
+	    fpga = &fpga_list[0];
+	}
+	else if (argc == 4) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	}
+	else
+	    goto failure;
+
+	addr = simple_strtoul(argv[argc-1], NULL, 16);
+
+	printf ("FPGA load %s: addr %08lx: ",
+		fpga->name, addr);
+	fpga_load (fpga, addr, 1);
+
+    }
+    else if (strncmp(argv[1], "rese", 4) == 0) {	/* reset */
+	if (argc == 2 && fpga_count == 1) {
+	    fpga = &fpga_list[0];
+	}
+	else if (argc == 3) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	}
+	else
+	    goto failure;
+
+	printf ("FPGA reset %s: ", fpga->name);
+	if (fpga_reset(fpga))
+	    printf ("ERROR: Timeout\n");
+	else
+	    printf ("done\n");
+    }
+    else
+	goto failure;
+
+    return 0;
+
+ failure:
+    return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	fpga,	4,	1,	do_fpga,
+	"access FPGA(s)",
+	"fpga status [name] - print FPGA status\n"
+	"fpga reset  [name] - reset FPGA\n"
+	"fpga load [name] addr - load FPGA configuration data"
+);
+
+#endif
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+int fpga_init (void)
+{
+    ulong addr;
+    ulong new_id, old_id = 0;
+    image_header_t *hdr;
+    fpga_t* fpga;
+    int do_load, i, j;
+    char name[16], *s;
+
+    /*
+     *  Port setup for FPGA control
+     */
+    for (i = 0; i < fpga_count; i++) {
+	fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
+    }
+
+    /*
+     * Load FPGA(s): a new net-list is loaded if the FPGA is
+     * empty, Power-on-Reset or the old one is not up-to-date
+     */
+    for (i = 0; i < fpga_count; i++) {
+	fpga = &fpga_list[i];
+	printf ("%s:  ", fpga->name);
+
+	for (j = 0; j < strlen(fpga->name); j++)
+	    name[j] = tolower(fpga->name[j]);
+	name[j] = '\0';
+	sprintf(name, "%s_addr", name);
+	addr = 0;
+	if ((s = getenv(name)) != NULL)
+	    addr = simple_strtoul(s, NULL, 16);
+
+	if (!addr) {
+	    printf ("env. variable %s undefined\n", name);
+	    return 1;
+	}
+
+	hdr = (image_header_t *)addr;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+	   puts ("Non legacy image format not supported\n");
+	   return -1;
+	}
+#endif
+
+	if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1)
+	    return 1;
+
+	do_load = 1;
+
+	if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
+	    old_id = fpga_control(fpga, FPGA_GET_ID);
+	    if (new_id == old_id)
+		do_load = 0;
+	}
+
+	if (do_load) {
+	    printf ("loading ");
+	    fpga_load (fpga, addr, 0);
+	} else {
+	    printf ("loaded (%08lx)\n", old_id);
+	}
+    }
+
+    return 0;
+}
diff --git a/u-boot/board/siemens/common/fpga.h b/u-boot/board/siemens/common/fpga.h
new file mode 100644
index 0000000..2de25b0
--- /dev/null
+++ b/u-boot/board/siemens/common/fpga.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#define FPGA_INIT_IS_HIGH   0
+#define FPGA_INIT_SET_HIGH  1
+#define FPGA_INIT_SET_LOW   2
+#define FPGA_PROG_SET_HIGH  3
+#define FPGA_PROG_SET_LOW   4
+#define FPGA_DONE_IS_HIGH   5
+#define	FPGA_READ_MODE      6
+#define FPGA_LOAD_MODE      7
+#define FPGA_GET_ID         8
+#define FPGA_INIT_PORTS     9
+
+#define FPGA_NAME_LEN       8
+typedef struct {
+    char  name[FPGA_NAME_LEN];
+    ulong conf_base;
+    uint  init_mask;
+    uint  prog_mask;
+    uint  done_mask;
+} fpga_t;
+
+extern fpga_t fpga_list[];
+extern int    fpga_count;
+
+ulong fpga_control (fpga_t* fpga, int cmd);
+
+#endif /* _FPGA_H_ */
diff --git a/u-boot/board/sixnet/Makefile b/u-boot/board/sixnet/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/sixnet/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sixnet/flash.c b/u-boot/board/sixnet/flash.c
new file mode 100644
index 0000000..2090802
--- /dev/null
+++ b/u-boot/board/sixnet/flash.c
@@ -0,0 +1,790 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+/* environment.h defines the various CONFIG_ENV_... values in terms
+ * of whichever ones are given in the configuration file.
+ */
+#include <environment.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b;
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b);
+	}
+
+	/* Remap FLASH according to real size, so only at proper address */
+	memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b);
+
+	/* Do this again (was done already in flast_get_size), just
+	 * in case we move it when remap the FLASH.
+	 */
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+	/* read the hardware protection status (if any) into the
+	 * protection array in flash_info.
+	 */
+	flash_sync_real_protect(&flash_info[0]);
+#endif
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_ADDR
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	return (size_b);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (top boot sector type) */
+		for (i = 0; i < info->sector_count - 3; i++)
+			info->start[i] = base + (i * sect_size);
+		i = info->sector_count - 1;
+		info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		fmt = "29LV800B%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+	case (FPW)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MiB	*/
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect(flash_info_t *info)
+{
+    FPWV *addr = (FPWV *)(info->start[0]);
+    FPWV *sect;
+    int i;
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case FLASH_28F800C3B:
+    case FLASH_28F800C3T:
+    case FLASH_28F160C3B:
+    case FLASH_28F160C3T:
+    case FLASH_28F320C3B:
+    case FLASH_28F320C3T:
+    case FLASH_28F640C3B:
+    case FLASH_28F640C3T:
+	/* check for protected sectors */
+	*addr = (FPW)0x00900090;
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02.
+	     * D0 = 1 for each device if protected.
+	     * If at least one device is protected the sector is marked
+	     * protected, but mixed protected and  unprotected devices
+	     * within a sector should never happen.
+	     */
+	    sect = (FPWV *)(info->start[i]);
+	    info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+	break;
+
+    case FLASH_AM640U:
+    case FLASH_AM800T:
+    default:
+	/* no hardware protect that we support */
+	break;
+    }
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer(0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			base[0x0555] = (FPW)0x00800080;	/* erase mode */
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	/* write one word to the flash */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		res = write_word_amd(info, (FPWV *)addr, data);
+		break;
+	case FLASH_MAN_INTEL:
+		res = write_word_intel(info, (FPWV *)addr, data);
+		break;
+	default:
+		/* unknown flash type, error! */
+		printf ("missing or unknown FLASH type\n");
+		res = 1;	/* not really a timeout, but gives error */
+		break;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+    FPWV *base;		/* first address in flash bank	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+
+    base = (FPWV *)(info->start[0]);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+    base[0x02AA] = (FPW)0x00550055;	/* unlock */
+    base[0x0555] = (FPW)0x00A000A0;	/* selects program mode */
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    /* data polling for D7 */
+    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00F000F0;	/* reset bank */
+	    res = 1;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+    *dest = (FPW)0x00400040;	/* program setup		*/
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
+	    res = 1;
+	}
+    }
+
+    if (res == 0 && (*dest & (FPW)0x00100010))
+	res = 1;	/* write failed, time out error is close enough	*/
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+    return (res);
+}
+
+#ifdef CONFIG_SYS_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset (info);		/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset (info);		/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect (info);
+		break;
+
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/u-boot/board/sixnet/fpgadata.c b/u-boot/board/sixnet/fpgadata.c
new file mode 100644
index 0000000..2d3a7b3
--- /dev/null
+++ b/u-boot/board/sixnet/fpgadata.c
@@ -0,0 +1,1719 @@
+	0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff,
+	0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9,
+	0xff, 0xef, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xcf,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+	0x7f, 0x7b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x77, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x86, 0xf6, 0xf0, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x7f,
+	0xc1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xf8, 0xff, 0xff, 0xf6, 0xf0, 0xff, 0xff,
+	0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x0f, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0xf8, 0xf7, 0x8f, 0xcf, 0xf0, 0xf6, 0xff,
+	0xff, 0xef, 0xff, 0xfb, 0x7f, 0x2f, 0x1f, 0x71,
+	0xf5, 0xff, 0xff, 0xef, 0x7f,
+	0xff, 0x7f, 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0x7f, 0x77, 0xf7, 0xff, 0xfb,
+	0x0f, 0xff, 0xf0, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xfe, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xff, 0xfa, 0xce, 0xff, 0xfd, 0xff, 0xff,
+	0x9f, 0xff, 0x8e, 0xff, 0xf0, 0xbf, 0x7f, 0xf5,
+	0xff, 0xef, 0x9f, 0xfd, 0x81,
+	0xff, 0xf9, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff,
+	0xff, 0xef, 0x9f, 0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x7f,
+	0xff, 0x77, 0xfa, 0xb6, 0xff, 0x78, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xbf, 0xfd, 0x0f, 0x7f, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xf6, 0xf7, 0xf6, 0x7f, 0xbf, 0xff, 0xff,
+	0xff, 0xff, 0xef, 0xbf, 0xf2, 0x7f, 0xef, 0xff,
+	0xfe, 0xfb, 0xff, 0xef, 0xff,
+	0xff, 0xf7, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xf7, 0xff, 0xf7, 0xcf, 0x8f, 0xff, 0xf0,
+	0xef, 0xf9, 0xfb, 0xff, 0xff, 0xff, 0x9f, 0x0f,
+	0x65, 0xe1, 0xfb, 0x7b, 0xf3,
+	0xff, 0xf7, 0xf6, 0xfe, 0xff, 0x8f, 0xf6, 0xe8,
+	0xf6, 0xf1, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff,
+	0x6f, 0x61, 0xf1, 0xfb, 0xff,
+	0xff, 0xde, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xf7, 0xbf, 0xff, 0xd4, 0x8f, 0x0f, 0x71, 0xc1,
+	0x6f, 0xd1, 0xeb, 0x5f, 0xfd,
+	0xff, 0x9f, 0xff, 0xfb, 0xff, 0x8f, 0x9f, 0xf7,
+	0x9f, 0xff, 0xf4, 0xb7, 0xfd, 0xff, 0xfe, 0x8f,
+	0xbf, 0x71, 0x1f, 0xff, 0x7f,
+	0xff, 0xfd, 0x87, 0x87, 0xf0, 0x70, 0x1f, 0xf7,
+	0xbf, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0x81,
+	0xbf, 0x3e, 0x7f, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0xff, 0x07, 0xff, 0xf0, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0xf7, 0x8d, 0x7f, 0xf1, 0xff,
+	0xff, 0x9f, 0x6f, 0xf1, 0xff,
+	0xbf, 0x71, 0x87, 0xfe, 0xf0, 0x8f, 0x8f, 0xf0,
+	0xfb, 0xcb, 0xff, 0xf0, 0x8f, 0x7f, 0xf1, 0x8f,
+	0x1e, 0xe1, 0x7e, 0x91, 0x7f,
+	0xbf, 0x1a, 0xff, 0x71, 0xff, 0x9f, 0x8f, 0xf6,
+	0xf8, 0xdf, 0xf7, 0xf4, 0xff, 0xff, 0xff, 0x8f,
+	0x1f, 0xf0, 0x7f, 0x97, 0xff,
+	0xbf, 0x97, 0xff, 0xfb, 0xbf, 0xdf, 0xff, 0xf7,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xdf,
+	0xf9, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xdf, 0xff, 0xf1, 0xff,
+	0xff, 0x9f, 0xfc, 0xfb, 0xff, 0xf0, 0xfe, 0xff,
+	0xff, 0xff, 0x9d, 0xff, 0xf4, 0xcf, 0xff, 0x7f,
+	0xf7, 0xff, 0xff, 0xff, 0xcf,
+	0xff, 0x97, 0xff, 0xfa, 0xff, 0x8f, 0xf8, 0xf0,
+	0xff, 0xff, 0xff, 0xdf, 0xff, 0xfd, 0xff, 0x0f,
+	0x7f, 0xe1, 0xff, 0xf1, 0xff,
+	0xff, 0x83, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x6f, 0x7f, 0x77, 0x7d, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x6f, 0xf1,
+	0xff, 0xd7, 0xff, 0xfe, 0xff, 0xff, 0x9f, 0xfd,
+	0x78, 0xef, 0xff, 0xbf, 0xff, 0xf5, 0xff, 0xff,
+	0xbf, 0x0f, 0x79, 0xd1, 0xff,
+	0xff, 0xd2, 0xff, 0x72, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xfe, 0x70, 0x9d, 0xff, 0xf4, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xbf, 0x7f,
+	0xff, 0x07, 0xff, 0x78, 0xff, 0x9f, 0xff, 0xfe,
+	0xff, 0x77, 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x8f,
+	0x7f, 0xe1, 0x0f, 0x71, 0xf1,
+	0xff, 0xfe, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xfd, 0xff, 0xba, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0x7f, 0xa1, 0x7f,
+	0xff, 0xbd, 0x7f, 0xf7, 0xf9, 0xfd, 0xfb, 0xff,
+	0xff, 0x8f, 0xbf, 0xb7, 0x8f, 0xaf, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0x5f, 0xeb,
+	0xbf, 0xfd, 0xf8, 0xff, 0xff, 0xfb, 0xff, 0xfb,
+	0xff, 0xf7, 0xcf, 0xfb, 0xf0, 0xff, 0xff, 0xdf,
+	0xff, 0xff, 0xef, 0x7f, 0xab,
+	0xff, 0xfd, 0xfa, 0xbf, 0x8f, 0xbf, 0xca, 0xfe,
+	0xff, 0xff, 0xdf, 0x6f, 0xd4, 0xf6, 0x0f, 0x3f,
+	0x11, 0xf9, 0xff, 0x7f, 0x8b,
+	0xbf, 0xff, 0x8f, 0xff, 0xc0, 0xfb, 0xf5, 0xef,
+	0xf7, 0x7f, 0xff, 0xff, 0xfb, 0x7f, 0xff, 0x7f,
+	0xff, 0x6f, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xbb, 0xf8, 0xfb, 0xcf, 0xfe, 0xfe,
+	0xff, 0xef, 0xff, 0xfb, 0x7f, 0xff, 0xff, 0x8f,
+	0xff, 0xe1, 0x7f, 0x7b, 0xff,
+	0xbf, 0x80, 0x89, 0x88, 0xb0, 0xf5, 0xf0, 0xff,
+	0xf7, 0xdf, 0xfe, 0x7c, 0x8f, 0x0f, 0x71, 0xe1,
+	0xff, 0xf1, 0xe5, 0x0e, 0x2b,
+	0xff, 0xff, 0xff, 0xbf, 0xff, 0xcf, 0xf5, 0x9f,
+	0xff, 0xff, 0xfe, 0xff, 0x8f, 0x7f, 0x71, 0x8f,
+	0xff, 0x91, 0x7f, 0xfb, 0xff,
+	0xff, 0x7f, 0x7f, 0xcf, 0x8a, 0xff, 0xf0, 0xff,
+	0x57, 0xfe, 0xfb, 0x8f, 0xff, 0xf0, 0xff, 0x7e,
+	0xff, 0xff, 0x9a, 0xff, 0xf1,
+	0xff, 0xff, 0xcf, 0xb7, 0xce, 0xff, 0xf4, 0xff,
+	0xff, 0x7f, 0xf7, 0xfb, 0xff, 0xfe, 0xff, 0x7f,
+	0xff, 0xfd, 0xfe, 0x75, 0xfd,
+	0xff, 0xef, 0xcf, 0xff, 0xf5, 0xff, 0xf5, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
+	0xcf, 0x7f, 0x31, 0x7f, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xdf, 0xff, 0xff,
+	0xff, 0x9f, 0xff, 0x84, 0x0e,
+	0xff, 0xf8, 0x7f, 0xf7, 0x7f, 0xff, 0xff, 0x8f,
+	0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0x9f, 0x8e, 0x05, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x9f, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0xff, 0x8f,
+	0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
+	0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e,
+	0xf1, 0xdf, 0xff, 0xfb, 0x8e,
+	0xff, 0x80, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xaf, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xfe,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xdf, 0xdf, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xfd, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80,
+	0xff, 0xf0, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0x8e,
+	0x0f, 0x01, 0x71, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xdf, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd,
+	0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe,
+	0xff, 0xdf, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfd,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xaf, 0xfe, 0xf5, 0xff, 0xff,
+	0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x80, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0x1f, 0xaf, 0x71, 0xa7,
+	0x6f, 0xf5, 0xfe, 0xff, 0xff,
+	0xff, 0x77, 0x79, 0x8f, 0xff, 0xf0, 0x8f, 0xff,
+	0x00, 0xff, 0xd0, 0x4f, 0x3d, 0xf0, 0xf7, 0xfd,
+	0x8f, 0x7f, 0x81, 0x7f, 0xd1,
+	0xff, 0xcd, 0xff, 0xff, 0x8f, 0x0f, 0x70, 0xf0,
+	0xff, 0x7f, 0x7f, 0xff, 0xff, 0xdb, 0x8d, 0x4b,
+	0x73, 0xf9, 0xff, 0xdf, 0xff,
+	0x3f, 0xfc, 0xff, 0x8f, 0xff, 0xf2, 0x8f, 0x8f,
+	0x70, 0x7a, 0x3f, 0xbc, 0xf7, 0xdb, 0xff, 0xf9,
+	0xff, 0xff, 0xff, 0xff, 0xee,
+	0xff, 0xe8, 0xf7, 0x8f, 0xfd, 0x80, 0xff, 0xf0,
+	0x9f, 0xa5, 0x7a, 0xf4, 0x6f, 0x3f, 0xcf, 0x07,
+	0x6a, 0xe1, 0xff, 0x8f, 0x7f,
+	0xff, 0xff, 0x77, 0xf1, 0x8f, 0x8f, 0xf0, 0xf0,
+	0xbf, 0xff, 0xe7, 0x7f, 0x8f, 0x24, 0x03, 0x77,
+	0xf3, 0xff, 0xfe, 0xff, 0xff,
+	0xbf, 0x9f, 0x77, 0x8b, 0xff, 0xf0, 0xff, 0xef,
+	0x7d, 0x7f, 0xff, 0x9f, 0xeb, 0x3d, 0xff, 0xf7,
+	0xff, 0xfb, 0xfe, 0xff, 0xdf,
+	0xff, 0xff, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbb, 0x5d,
+	0xf5, 0xbb, 0xef, 0xff, 0xff,
+	0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf8, 0xff, 0xff,
+	0xf7, 0x7f, 0xff, 0xff, 0xaf, 0xbf, 0x75, 0xb7,
+	0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0x87, 0x7f, 0xf8, 0xff, 0xf7, 0xf7,
+	0x8f, 0xff, 0xf0, 0x7f, 0xf7, 0xff, 0xad, 0xff,
+	0xf7, 0xee, 0x9f, 0xff, 0xf5,
+	0xff, 0xf8, 0x07, 0xff, 0x80, 0x8f, 0x80, 0x80,
+	0xf0, 0x8f, 0x7f, 0x70, 0x4f, 0x0f, 0x79, 0xf1,
+	0xfd, 0xff, 0xef, 0x8f, 0x7f,
+	0xbf, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xd0, 0xbf, 0xdb, 0xe5,
+	0x3b, 0xfe, 0xf7, 0xff, 0x8f,
+	0xff, 0xff, 0x8f, 0x77, 0x80, 0xff, 0xf0, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xbd, 0xef, 0x07, 0x7f,
+	0xf1, 0xfe, 0xff, 0xfe, 0xff,
+	0x7f, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xf7, 0x8f,
+	0xbf, 0x70, 0xf5, 0x7f, 0xff, 0xef, 0x3f, 0x7d,
+	0xf7, 0xff, 0xff, 0xfe, 0xfe,
+	0xff, 0x97, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+	0x7e, 0xff, 0xff, 0x9f, 0xdf, 0xf7, 0x3b, 0xff,
+	0xf7, 0xff, 0x7f, 0xfe, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x1f, 0x1f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x80, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+	0x9f, 0x80, 0xe1, 0xf1, 0xff, 0xff, 0xef, 0xff,
+	0xfe, 0x9f, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xef,
+	0xfe, 0xef, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xef, 0xff, 0xff, 0xef, 0xfe, 0xef,
+	0xef, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xe0, 0xff, 0xff,
+	0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xef, 0xff, 0xff,
+	0xff, 0xff, 0xee, 0xef, 0x9f,
+	0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xe0, 0xff, 0xff,
+	0xff, 0xef, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xef, 0xff, 0xfe, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf,
+	0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e,
+	0xe1, 0xdf, 0xff, 0xf7, 0x8e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xef, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0x1f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x7e, 0xf1,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x8f, 0x80,
+	0xf7, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9e,
+	0x6f, 0x91, 0x71, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xef, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xdf, 0x8f,
+	0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+	0xff, 0xef, 0xff, 0xd7, 0xff,
+	0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0x8f, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xfe, 0xf9, 0xdf, 0xff,
+	0xff, 0xff, 0x8f, 0xbf, 0xf7, 0x9f, 0xf8, 0xf0,
+	0xff, 0xff, 0x77, 0xff, 0x0e, 0x1f, 0x61, 0x81,
+	0x7f, 0xf1, 0xfe, 0xff, 0xff,
+	0xff, 0x7f, 0xb9, 0xcf, 0xff, 0xff, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x7f, 0x75, 0x8b, 0x7f, 0xf1,
+	0x8f, 0x7f, 0x80, 0x7e, 0x91,
+	0xff, 0xbf, 0xdf, 0xff, 0xa7, 0x47, 0x70, 0xf7,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+	0x61, 0xf1, 0xef, 0xff, 0xff,
+	0x7f, 0xfe, 0xef, 0x5f, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xe7, 0xb7, 0xfc, 0xeb, 0x9f, 0x7f, 0xf1,
+	0x9f, 0x0f, 0x71, 0xf1, 0xee,
+	0xff, 0xf0, 0xf7, 0x3f, 0xef, 0x97, 0xf8, 0xe8,
+	0xff, 0x9f, 0x7f, 0xf0, 0x7f, 0x9f, 0x6f, 0x91,
+	0x7e, 0xf1, 0x9f, 0x8f, 0x57,
+	0xff, 0xff, 0x26, 0xb9, 0xb8, 0xff, 0xf0, 0xff,
+	0xff, 0xff, 0xf7, 0x7f, 0x6f, 0xf4, 0x9f, 0x1f,
+	0x71, 0xe1, 0xfe, 0x7f, 0xff,
+	0xbf, 0xff, 0x71, 0xbb, 0xe8, 0xff, 0xff, 0xf8,
+	0xbf, 0xff, 0xaf, 0xff, 0xf8, 0x9d, 0x6f, 0xf1,
+	0xbf, 0xff, 0xb7, 0xff, 0xbd,
+	0xbf, 0xff, 0xff, 0xdf, 0x97, 0xc7, 0xf7, 0xf0,
+	0xff, 0xff, 0x93, 0xff, 0xff, 0xef, 0xcf, 0x5f,
+	0xf1, 0xf7, 0xdf, 0xf5, 0x9f,
+	0xff, 0xff, 0x87, 0xbf, 0xe0, 0xbf, 0xf7, 0xff,
+	0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x5f, 0x21, 0xb1,
+	0xff, 0x6d, 0xff, 0xef, 0xff,
+	0xff, 0xff, 0xd7, 0xff, 0xb8, 0xff, 0xff, 0xff,
+	0x3f, 0xef, 0xf0, 0x7f, 0xd7, 0x7f, 0xf1, 0xff,
+	0xef, 0xee, 0xbf, 0x7f, 0xf1,
+	0xff, 0xf8, 0x47, 0x0f, 0xc7, 0xf0, 0x7f, 0xf0,
+	0xf0, 0x90, 0x7f, 0x70, 0x8f, 0x2f, 0xc1, 0x0f,
+	0x11, 0x1f, 0xef, 0xaf, 0x7f,
+	0xbf, 0x7f, 0xf0, 0x9f, 0xe7, 0xf7, 0x38, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf0, 0xaf, 0xff, 0xff,
+	0xbf, 0xfe, 0xfd, 0xdf, 0x8f,
+	0xff, 0xff, 0xbf, 0xf7, 0x8f, 0xff, 0xf7, 0xff,
+	0xeb, 0xff, 0xff, 0xff, 0x8d, 0x3f, 0x81, 0x7f,
+	0xd1, 0xfe, 0xdf, 0xfe, 0xff,
+	0x7f, 0xff, 0xff, 0xdf, 0xa8, 0xff, 0xf0, 0xff,
+	0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xef, 0xef,
+	0xef, 0x9f, 0x7f, 0x7e, 0xfe,
+	0xff, 0xff, 0xef, 0xff, 0xa7, 0x77, 0xff, 0xff,
+	0xef, 0xff, 0xff, 0xdf, 0xff, 0xe7, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xfe, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0x0f, 0x0f, 0xf1, 0xe1, 0xff, 0xff, 0xef,
+	0xef, 0xff, 0xff, 0x8e, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+	0x8f, 0x80, 0xf1, 0xf1, 0xef, 0xaf, 0xaf, 0xff,
+	0xee, 0xdf, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xef, 0x8f, 0x9f, 0xf1, 0xe1, 0xff, 0xaf, 0xef,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0x9f, 0xf1, 0xf1, 0xef, 0xff, 0xaf, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xef, 0xbf, 0xef, 0xff,
+	0xef, 0xbf, 0xff, 0xef, 0xff,
+	0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xfe,
+	0xcf, 0x3f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xef, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x6e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xe0, 0xff, 0xef, 0xff,
+	0xff, 0xff, 0xee, 0xef, 0x9f,
+	0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xa0, 0xff, 0xfe,
+	0xff, 0xbf, 0x8e, 0x6f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x6f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
+	0xff, 0xb0, 0x0f, 0xaf, 0x70, 0xff, 0x8f, 0x7e,
+	0xf1, 0xff, 0xff, 0xf1, 0x9e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xef, 0x8f, 0x7f, 0x90, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xaf, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x3f, 0xdf, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xbf, 0x7e, 0xf1,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0x0f, 0xaf, 0x80,
+	0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xde,
+	0x0f, 0x91, 0x7f, 0xf1, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xfe,
+	0xff, 0xff, 0xbf, 0xff, 0xfb,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xdf, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xdf, 0xbf, 0xff, 0xef, 0xff,
+	0xff, 0xaf, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xaf, 0xff,
+	0xf0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff,
+	0xdf, 0xfe, 0xfe, 0xff, 0xff,
+	0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x8f, 0xff, 0xf0,
+	0xf9, 0xff, 0xf7, 0xff, 0x0f, 0x5f, 0x29, 0x89,
+	0x77, 0xf1, 0xfa, 0xff, 0xde,
+	0xff, 0xc3, 0x3f, 0x4b, 0x7f, 0xe9, 0x0f, 0xff,
+	0x00, 0xff, 0x90, 0x0f, 0xd7, 0xff, 0x7f, 0xf9,
+	0x8f, 0x7f, 0x81, 0x7f, 0x81,
+	0xff, 0xff, 0xfb, 0x7d, 0x80, 0x46, 0x76, 0xf0,
+	0xff, 0xff, 0x6f, 0xff, 0xff, 0xad, 0xcf, 0x3f,
+	0x71, 0xf9, 0xff, 0xff, 0xff,
+	0x3f, 0xba, 0xff, 0xc7, 0xf7, 0xb9, 0xcf, 0xde,
+	0x77, 0xb7, 0x77, 0xfe, 0xff, 0xbf, 0x6f, 0xf9,
+	0xff, 0x7e, 0x79, 0xb9, 0xfe,
+	0xff, 0xe4, 0xf7, 0x8f, 0xfe, 0x07, 0xfe, 0xf8,
+	0xff, 0x89, 0x7f, 0xe8, 0x7f, 0xd7, 0x7f, 0x99,
+	0x76, 0xf1, 0xff, 0x0f, 0x7b,
+	0xbf, 0xff, 0xb6, 0xb9, 0x8f, 0xdf, 0xf6, 0xff,
+	0xff, 0xf7, 0xff, 0xff, 0x8f, 0xdd, 0x87, 0x7f,
+	0x71, 0xf1, 0xfe, 0xff, 0xff,
+	0xff, 0x7f, 0xf1, 0x8a, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0xff, 0xcf, 0xfb, 0xe8, 0x9d, 0x77, 0xa9,
+	0xff, 0x77, 0xda, 0x7f, 0xff,
+	0xbf, 0xff, 0xf7, 0xf7, 0x86, 0xe5, 0xf0, 0xe0,
+	0xff, 0xff, 0xbf, 0xff, 0xff, 0xef, 0x8f, 0x7f,
+	0xbd, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xef, 0x86, 0x8f, 0xf0, 0xff, 0xf6, 0x9f,
+	0xff, 0x7f, 0xff, 0xff, 0xcf, 0x1f, 0x71, 0xdd,
+	0x7f, 0xe1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xc7, 0xf7, 0xb9, 0xff, 0xff, 0xfa,
+	0x3f, 0xef, 0xf0, 0xff, 0xef, 0x7f, 0xd5, 0xff,
+	0xfb, 0xff, 0xf7, 0x6e, 0xf1,
+	0xff, 0xfc, 0xc7, 0xbf, 0xc8, 0xc0, 0x59, 0xff,
+	0xdf, 0xff, 0x7b, 0xf0, 0xa7, 0x1f, 0xa9, 0x77,
+	0x79, 0x71, 0x11, 0xff, 0x79,
+	0xbf, 0xfb, 0x70, 0xbf, 0xff, 0xf9, 0x37, 0xbe,
+	0xff, 0xff, 0x8f, 0x7f, 0xf4, 0x9f, 0xff, 0xff,
+	0xd7, 0x7f, 0xff, 0xff, 0xaf,
+	0xff, 0xff, 0x9e, 0xf7, 0x9f, 0xfe, 0xe4, 0xff,
+	0xcf, 0xcf, 0xff, 0xff, 0xdf, 0x7f, 0x8d, 0x7f,
+	0xf9, 0xfa, 0xdf, 0x9f, 0xef,
+	0x7f, 0xef, 0xff, 0xff, 0xbe, 0xfd, 0xd2, 0xdf,
+	0xff, 0x7e, 0xf7, 0xff, 0xff, 0xab, 0x97, 0xef,
+	0xf3, 0xfe, 0x7f, 0x71, 0xfe,
+	0xff, 0x9f, 0xff, 0xff, 0xb6, 0xfb, 0xf7, 0xff,
+	0xff, 0xf7, 0xff, 0xbf, 0xff, 0xb7, 0xdb, 0xff,
+	0xbb, 0xef, 0xff, 0xff, 0xff,
+	0x3f, 0x68, 0xfe, 0xfd, 0xfb, 0xff, 0xff, 0xef,
+	0xf1, 0x1e, 0x1b, 0xf1, 0xf5, 0xff, 0xff, 0xff,
+	0xff, 0x9f, 0xfb, 0x9a, 0x36,
+	0xff, 0xfc, 0x7d, 0xff, 0x73, 0xf7, 0xff, 0xaf,
+	0x9f, 0x94, 0xfd, 0xf5, 0xff, 0xf7, 0xff, 0xfb,
+	0xfe, 0xef, 0x3e, 0x07, 0x4d,
+	0xbf, 0xe8, 0xf8, 0xff, 0x7f, 0xff, 0xf7, 0xf7,
+	0xf1, 0x8f, 0xaf, 0xd1, 0xf7, 0xf9, 0xfd, 0xff,
+	0xf8, 0xdf, 0xfb, 0x8f, 0x2f,
+	0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xff,
+	0xa7, 0xaf, 0xf7, 0xf3, 0xdf, 0xff, 0xfd, 0xff,
+	0xfd, 0xff, 0xae, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, 0xf3, 0xf3,
+	0xff, 0xf3, 0xff, 0xf7, 0xfb, 0xf3, 0xff, 0xff,
+	0xff, 0xeb, 0xff, 0xf3, 0xdb,
+	0xff, 0xeb, 0x7b, 0xfb, 0xf7, 0xff, 0x8b, 0xf7,
+	0xfc, 0xf7, 0xfb, 0xff, 0xfb, 0xf3, 0xff, 0xff,
+	0x8b, 0x7f, 0xd4, 0xfb, 0xff,
+	0x7f, 0xec, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7,
+	0xff, 0x8e, 0xff, 0xf8, 0xf7, 0xfb, 0xfd, 0xff,
+	0xfd, 0x9f, 0xf7, 0x9f, 0x7e,
+	0xbf, 0xfb, 0x7c, 0xff, 0xf7, 0xff, 0xff, 0xfb,
+	0xfb, 0xf1, 0x8f, 0xf3, 0xdc, 0xf7, 0xfd, 0xff,
+	0xe9, 0xeb, 0xef, 0xc3, 0xb7,
+	0xff, 0x07, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xf7,
+	0x8f, 0xff, 0xf4, 0x8f, 0xfb, 0xfc, 0xff, 0xef,
+	0xff, 0xf7, 0x8f, 0x7f, 0xd1,
+	0xff, 0xfa, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xf3, 0x89, 0xef, 0xf8, 0xff, 0xf7, 0xff, 0xef,
+	0xef, 0xf7, 0xf3, 0xab, 0x7f,
+	0x3f, 0xf9, 0x7e, 0xf9, 0x8f, 0x7f, 0xf0, 0xef,
+	0xff, 0xfc, 0x1b, 0xff, 0x7c, 0xff, 0x8f, 0x6e,
+	0xf1, 0xf7, 0x73, 0xff, 0xa6,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf9, 0x8f, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfa, 0x8f, 0x7f,
+	0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
+	0x57, 0xaf, 0xfb, 0x85, 0x7f, 0xf4, 0xff, 0xfe,
+	0xef, 0xff, 0xef, 0xbf, 0x53,
+	0xff, 0x7d, 0xff, 0xff, 0xe3, 0xff, 0xff, 0xff,
+	0x97, 0x71, 0xf8, 0xff, 0xff, 0xff, 0xdb, 0xef,
+	0xef, 0xe7, 0x97, 0x72, 0xfd,
+	0xff, 0xff, 0xff, 0xff, 0xf3, 0x0f, 0xe3, 0x86,
+	0xf0, 0xf4, 0xfb, 0xff, 0xdf, 0xff, 0xfb, 0x8e,
+	0x0b, 0xa5, 0x72, 0xf9, 0xff,
+	0xff, 0xfb, 0xff, 0xff, 0xf7, 0xff, 0xf3, 0xff,
+	0xf7, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xfb, 0xee,
+	0xfb, 0xff, 0xef, 0xff, 0xff,
+	0xbf, 0x82, 0xf8, 0xf8, 0xf7, 0x7f, 0xf7, 0xff,
+	0xff, 0xef, 0x87, 0x87, 0xf0, 0xf0, 0xfb, 0xff,
+	0xfb, 0xf7, 0xef, 0xef, 0x87,
+	0xff, 0xf6, 0xff, 0xfa, 0xf1, 0xef, 0xf3, 0xf7,
+	0x7f, 0xff, 0xff, 0xef, 0xff, 0xf7, 0xff, 0xff,
+	0xfb, 0xf7, 0xff, 0xfe, 0xff,
+	0xff, 0xf7, 0xfb, 0xf2, 0xf3, 0xff, 0xf1, 0xf7,
+	0xff, 0xef, 0xf7, 0xef, 0xf7, 0xf7, 0xff, 0xfe,
+	0xff, 0xff, 0xef, 0xff, 0xe7,
+	0xff, 0xfb, 0xfb, 0xff, 0xf5, 0xef, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0x77, 0xff, 0xff, 0xfe,
+	0xff, 0xf7, 0xff, 0xef, 0xef,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0xef, 0xe5, 0xff,
+	0xfe, 0x61, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0xef, 0xef, 0xf3, 0xf7,
+	0xff, 0xff, 0x0f, 0x9f, 0xfa, 0x87, 0xff, 0xf6,
+	0xeb, 0xff, 0xff, 0xef, 0x0f, 0x6f, 0xfd, 0x0d,
+	0x53, 0xf1, 0xf3, 0xff, 0xff,
+	0xbf, 0x1b, 0x7f, 0x96, 0xfe, 0xff, 0x8f, 0xfb,
+	0x00, 0xff, 0xb0, 0x17, 0x7c, 0x8f, 0xff, 0xfd,
+	0x8f, 0x7f, 0x81, 0x7e, 0xf1,
+	0xff, 0xfd, 0xed, 0xee, 0x9e, 0x0b, 0x79, 0xff,
+	0xfb, 0x77, 0x5b, 0xff, 0x9f, 0xff, 0x4f, 0x0f,
+	0x71, 0xf0, 0xdb, 0xff, 0xf7,
+	0x7f, 0xe7, 0xef, 0x18, 0xff, 0xff, 0x9d, 0x8e,
+	0x67, 0xbf, 0x4f, 0xff, 0xff, 0xae, 0xff, 0xf1,
+	0xeb, 0xef, 0xfd, 0xad, 0xf6,
+	0xff, 0xfc, 0xf7, 0x1f, 0xff, 0x9f, 0xfb, 0xfc,
+	0xff, 0x8f, 0x77, 0xec, 0x5f, 0x6f, 0xdf, 0x25,
+	0x7e, 0xd9, 0xe6, 0x97, 0x3f,
+	0xff, 0xf7, 0x67, 0xec, 0x92, 0xbe, 0xf1, 0xfb,
+	0xff, 0x7f, 0xdf, 0x7b, 0x5e, 0x7d, 0xe7, 0x5f,
+	0xf1, 0xf1, 0xfb, 0xff, 0xf7,
+	0xbf, 0xf7, 0x71, 0x9a, 0xfd, 0xff, 0xf7, 0xfb,
+	0x5f, 0x7f, 0xaf, 0xdf, 0xf9, 0xe7, 0x77, 0xdd,
+	0x6f, 0xf7, 0xbb, 0xff, 0x8b,
+	0xbf, 0xff, 0x77, 0xff, 0x93, 0xfe, 0xf8, 0xfe,
+	0xbf, 0xfe, 0xbf, 0xff, 0xff, 0xbf, 0xab, 0x7f,
+	0xfd, 0xff, 0xcf, 0x67, 0xff,
+	0xff, 0x7f, 0x07, 0x9f, 0xe4, 0xdb, 0xff, 0xf1,
+	0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x6f, 0xd1, 0x6d,
+	0x73, 0xff, 0xff, 0xfb, 0xff,
+	0xff, 0x6f, 0x9f, 0x7b, 0xfd, 0xff, 0xf6, 0xfd,
+	0x27, 0xff, 0xfc, 0xff, 0xaf, 0xff, 0xfd, 0xfe,
+	0x7f, 0xdf, 0xff, 0x7f, 0xef,
+	0xff, 0xfe, 0x81, 0xe7, 0x93, 0x91, 0x83, 0x85,
+	0xef, 0x8f, 0x7f, 0x74, 0x8d, 0x1b, 0x2d, 0xe2,
+	0xcd, 0xe5, 0xb5, 0x9f, 0x77,
+	0xbf, 0x7f, 0xe4, 0xef, 0xff, 0xf7, 0xdb, 0xfd,
+	0x7f, 0xfe, 0xab, 0x7f, 0xfc, 0xbf, 0xff, 0xde,
+	0x77, 0xfb, 0xdf, 0xef, 0xbf,
+	0xff, 0xff, 0x1e, 0x7f, 0x8f, 0xff, 0x92, 0xf3,
+	0xdf, 0x7b, 0xff, 0x7b, 0xff, 0xdb, 0x3d, 0x5f,
+	0xf9, 0xf6, 0xff, 0xf2, 0xf7,
+	0x7f, 0x7f, 0xff, 0xff, 0xef, 0xd2, 0xf0, 0xb7,
+	0xfb, 0x7f, 0xfc, 0x77, 0xd7, 0x3f, 0xc7, 0x7f,
+	0xf3, 0xe7, 0xff, 0xfd, 0xfe,
+	0xff, 0xff, 0xef, 0x7b, 0xef, 0xf5, 0xda, 0xff,
+	0x7c, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xeb, 0xfb,
+	0xef, 0xff, 0xef, 0xff, 0xff,
+	0x3f, 0x60, 0xfc, 0xfb, 0xf7, 0xff, 0xff, 0xff,
+	0xfb, 0x00, 0x0f, 0xf1, 0xf5, 0xfb, 0xff, 0xff,
+	0xff, 0xff, 0xf3, 0x86, 0x3e,
+	0xff, 0xf8, 0x7f, 0xfb, 0x73, 0xff, 0xff, 0x9f,
+	0xab, 0x8c, 0xf5, 0xd1, 0xff, 0xfb, 0xff, 0xff,
+	0xfe, 0xeb, 0x36, 0x0d, 0x49,
+	0xbf, 0xf0, 0xfc, 0xfb, 0x73, 0xff, 0xf3, 0xff,
+	0xff, 0xab, 0xa7, 0xf1, 0xf9, 0xff, 0xf7, 0xdf,
+	0xfa, 0xfb, 0xff, 0xa7, 0x3f,
+	0xff, 0xf8, 0x7f, 0xff, 0xfb, 0xfb, 0xfb, 0xff,
+	0xaf, 0x8f, 0xf9, 0xf9, 0xdf, 0xdf, 0xf7, 0xdb,
+	0xff, 0xff, 0xba, 0x2f, 0x69,
+	0xff, 0xe7, 0xfb, 0xfb, 0xff, 0xff, 0xff, 0xfb,
+	0xff, 0xfb, 0xd7, 0xff, 0xdf, 0xf7, 0xd7, 0xdf,
+	0xf3, 0xdb, 0xff, 0xdb, 0xff,
+	0xff, 0xe3, 0x7b, 0xf9, 0xfb, 0xff, 0x8f, 0xfb,
+	0xf8, 0xff, 0xff, 0xef, 0xdf, 0xf3, 0xd7, 0xdf,
+	0xa3, 0x5b, 0xc4, 0xfb, 0xef,
+	0x7f, 0xe0, 0xfd, 0xfb, 0xfb, 0xff, 0xfb, 0xeb,
+	0xff, 0x8c, 0xeb, 0xf0, 0xd3, 0xff, 0xd7, 0xff,
+	0xf7, 0xbb, 0x7f, 0x8f, 0x7e,
+	0xbf, 0xfb, 0x6c, 0xfb, 0xfb, 0xff, 0xfb, 0xff,
+	0xfb, 0xf3, 0x8b, 0xf3, 0xf4, 0xf7, 0xd7, 0xff,
+	0xf3, 0xff, 0xfe, 0xc2, 0xbf,
+	0xff, 0x87, 0x7f, 0xfa, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf4, 0xff, 0xdf,
+	0xff, 0xfb, 0x8f, 0x7f, 0xc5,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb,
+	0xf3, 0x87, 0xef, 0xfc, 0xfd, 0xfb, 0xff, 0xff,
+	0xdf, 0xff, 0xfb, 0xab, 0x7f,
+	0x3f, 0xf3, 0xfa, 0xf9, 0x8f, 0x7f, 0xf0, 0xeb,
+	0xfb, 0xec, 0x1f, 0xcf, 0x7e, 0xff, 0x8f, 0x5e,
+	0xd1, 0xbf, 0xff, 0xfe, 0xaa,
+	0xff, 0x80, 0x7d, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x5f, 0x8c, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfa, 0x9f, 0x6f,
+	0xff, 0x9a, 0xfd, 0xfc, 0xff, 0xff, 0xff, 0xff,
+	0x6f, 0xbf, 0xd7, 0x89, 0x7f, 0xf4, 0xff, 0xfe,
+	0xff, 0xff, 0xdf, 0xbf, 0x6f,
+	0xff, 0xfd, 0xff, 0xff, 0xef, 0xff, 0xfb, 0xff,
+	0x2b, 0x73, 0xf0, 0xf3, 0xff, 0xff, 0xc3, 0xff,
+	0xff, 0xff, 0x8b, 0x62, 0xfd,
+	0xff, 0xef, 0xff, 0xff, 0xfb, 0x0f, 0x8b, 0x8e,
+	0xf0, 0xdc, 0xf7, 0xff, 0xff, 0xff, 0xfb, 0xae,
+	0x43, 0xa9, 0x73, 0xf9, 0xfb,
+	0x7f, 0xf9, 0xff, 0xff, 0xfd, 0xff, 0xf9, 0xff,
+	0xfb, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xf3, 0xfe,
+	0xf3, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xf9, 0x7f, 0xf9, 0xff,
+	0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xf3, 0xff,
+	0xf3, 0xfb, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff,
+	0xfb, 0xef, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xf7, 0xf9, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xfe,
+	0xf3, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xf1, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xfe,
+	0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xf1, 0xff, 0x85, 0xff,
+	0xfe, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff,
+	0xf3, 0xde, 0xff, 0xf3, 0xff,
+	0xbf, 0xff, 0x0f, 0x9f, 0xfa, 0x9f, 0xeb, 0xf2,
+	0xe7, 0xff, 0x7b, 0xff, 0x4f, 0x73, 0x31, 0x81,
+	0x5f, 0xf1, 0xfe, 0xff, 0xbf,
+	0xff, 0xaf, 0x7f, 0x94, 0xfb, 0xfe, 0x8f, 0xff,
+	0x00, 0xff, 0xf0, 0xef, 0xef, 0x5f, 0xfb, 0xf5,
+	0x8f, 0x7f, 0x81, 0x5e, 0xf1,
+	0xff, 0xf9, 0xff, 0xef, 0x86, 0x0f, 0x71, 0xf6,
+	0xff, 0x7f, 0x7f, 0x97, 0xcf, 0xfd, 0xbf, 0x5f,
+	0xf9, 0xf1, 0xf3, 0xff, 0xff,
+	0x3f, 0xdb, 0xed, 0x1e, 0xff, 0xf6, 0x95, 0x9a,
+	0x6f, 0x3d, 0xff, 0xf8, 0xfb, 0xdf, 0xf7, 0xfd,
+	0xfb, 0xf7, 0xfd, 0xed, 0xde,
+	0x7f, 0xf0, 0xf7, 0x87, 0x7f, 0x9b, 0xff, 0xec,
+	0x9f, 0xbf, 0x7f, 0xcd, 0x7f, 0xf7, 0x3b, 0xad,
+	0x7e, 0xf8, 0xff, 0xbb, 0x79,
+	0xff, 0xff, 0xe3, 0x7c, 0x01, 0x8d, 0xf5, 0xfb,
+	0xe7, 0xf7, 0xff, 0xff, 0x9e, 0x7d, 0x0f, 0x7f,
+	0xf1, 0xcd, 0xfe, 0xf7, 0xff,
+	0x3f, 0xd7, 0xf4, 0x9a, 0xf7, 0xed, 0xff, 0xf3,
+	0xb7, 0xff, 0xef, 0xff, 0xbd, 0xe7, 0x5f, 0xbd,
+	0xff, 0xef, 0xfe, 0x7f, 0xf1,
+	0x3f, 0xff, 0xe7, 0xff, 0xcf, 0xfa, 0xf8, 0xff,
+	0xff, 0xdf, 0xbf, 0xfe, 0xdf, 0xff, 0xd3, 0x1f,
+	0xfd, 0xef, 0x7f, 0xff, 0xcf,
+	0x7f, 0xff, 0x93, 0xdf, 0xf0, 0xef, 0xf3, 0xd4,
+	0x77, 0x6f, 0xff, 0xff, 0xbf, 0x7f, 0x7d, 0xfd,
+	0x7f, 0x7d, 0xff, 0xff, 0xf7,
+	0xff, 0xf7, 0xdf, 0xfb, 0xbc, 0xef, 0xff, 0xfd,
+	0xff, 0xff, 0xfc, 0x7f, 0xb7, 0xff, 0xfd, 0x5f,
+	0xcf, 0xff, 0xef, 0x7f, 0xfd,
+	0xff, 0xee, 0x87, 0xef, 0x92, 0xf0, 0x7e, 0xe5,
+	0xbf, 0x8f, 0x7f, 0x60, 0xd9, 0xdb, 0x71, 0xb3,
+	0x2d, 0x49, 0x6c, 0x29, 0x7f,
+	0xbf, 0xff, 0xe4, 0x6f, 0xf3, 0xfa, 0x57, 0xfd,
+	0xff, 0xfe, 0xb7, 0x7f, 0xfc, 0xff, 0x73, 0xdf,
+	0xf3, 0x7f, 0xfd, 0xff, 0xbf,
+	0xff, 0xef, 0x8b, 0x7f, 0x8f, 0xff, 0xf2, 0xff,
+	0xff, 0xf7, 0xfb, 0xff, 0xff, 0xdf, 0xed, 0xef,
+	0xf1, 0xf7, 0xfd, 0xdf, 0xf7,
+	0xff, 0xff, 0xff, 0xf7, 0xe7, 0xe6, 0xf1, 0xff,
+	0xdf, 0xfb, 0xe9, 0xfe, 0xbf, 0xff, 0xbf, 0x5f,
+	0xff, 0xbf, 0x0e, 0x75, 0xfa,
+	0xff, 0xff, 0xff, 0x6f, 0xfb, 0xf9, 0xff, 0xff,
+	0xf3, 0xff, 0xfb, 0xbf, 0xef, 0xff, 0xf3, 0x7f,
+	0xff, 0xff, 0xff, 0xfb, 0xff,
+	0xff, 0x38, 0xf8, 0xf7, 0xff, 0xff, 0xdf, 0x9f,
+	0xf7, 0x0b, 0x0f, 0xf5, 0xf5, 0xff, 0xff, 0xff,
+	0xbf, 0xf7, 0xf3, 0x8e, 0x0e,
+	0xbf, 0xe8, 0x6f, 0xef, 0x7f, 0xff, 0xdf, 0xdf,
+	0xef, 0x88, 0xf5, 0x91, 0xfb, 0xff, 0xff, 0xbf,
+	0xfe, 0xbf, 0xa6, 0x81, 0x71,
+	0xff, 0xf0, 0xf8, 0xff, 0x67, 0xef, 0xff, 0xb7,
+	0xf7, 0x8f, 0x2f, 0xd1, 0x41, 0xff, 0xcf, 0x5f,
+	0xfe, 0xff, 0x7b, 0x8f, 0x9f,
+	0xff, 0xf8, 0x6f, 0xef, 0xf7, 0xe7, 0xff, 0xff,
+	0xbf, 0x8f, 0xd1, 0xf1, 0xcf, 0xdf, 0xcf, 0xdf,
+	0xff, 0xff, 0x9f, 0x8f, 0xe1,
+	0xff, 0xe7, 0xff, 0xf7, 0xe7, 0x6f, 0xf7, 0xe7,
+	0xe7, 0x77, 0xef, 0xef, 0x6f, 0xff, 0xff, 0xdf,
+	0xff, 0xdf, 0xdf, 0xff, 0xff,
+	0xff, 0xa7, 0x6f, 0xff, 0xf7, 0xef, 0x97, 0xe7,
+	0xf0, 0xef, 0x7f, 0xaf, 0x4f, 0xff, 0xff, 0xdf,
+	0xbf, 0x5f, 0xe0, 0x7f, 0xef,
+	0x7f, 0xa0, 0xef, 0xff, 0xe7, 0xff, 0xf7, 0xf7,
+	0xff, 0x8b, 0xbf, 0xf8, 0xdf, 0xff, 0xcf, 0x7e,
+	0xff, 0xdf, 0x7f, 0x8e, 0x5f,
+	0xff, 0xff, 0x38, 0xff, 0xf7, 0xff, 0xf7, 0xf7,
+	0xf7, 0xf7, 0x8f, 0xf7, 0xf8, 0xf7, 0xcf, 0xff,
+	0xff, 0xff, 0xfe, 0xcb, 0x3f,
+	0x3f, 0x9f, 0x7f, 0xf8, 0xff, 0xef, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0xaf, 0xff, 0xf0, 0xff, 0xdf,
+	0xff, 0xff, 0xae, 0x7f, 0xc1,
+	0x7f, 0xf0, 0x7f, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xf7, 0xbf, 0xbf, 0xd0, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xff, 0x9b, 0xff,
+	0x7f, 0xcf, 0xf8, 0xff, 0x8f, 0x6f, 0xe0, 0xd7,
+	0xf7, 0xf7, 0xff, 0xfe, 0xf0, 0xfe, 0x8f, 0x5e,
+	0xd1, 0xff, 0xdf, 0xdf, 0xbe,
+	0xff, 0x84, 0x7f, 0xf8, 0xff, 0x7f, 0xdf, 0xff,
+	0xff, 0xaf, 0x7f, 0x81, 0x7f, 0xf5, 0xff, 0xff,
+	0xff, 0xff, 0xfa, 0x9f, 0x3f,
+	0xff, 0xd8, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x0f, 0xff, 0x85, 0x7f, 0xf0, 0xff, 0xfe,
+	0xbf, 0xff, 0xdf, 0x6f, 0xbf,
+	0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf7, 0xdf,
+	0xf7, 0x47, 0xf4, 0xff, 0xef, 0xff, 0xdf, 0x7f,
+	0xff, 0xbf, 0xcf, 0x5a, 0xf1,
+	0xff, 0xbf, 0xbf, 0xff, 0xff, 0x3f, 0x8f, 0xc0,
+	0xf3, 0xd1, 0xff, 0xfb, 0xef, 0xff, 0xdf, 0xbe,
+	0x0f, 0x25, 0xe9, 0xd1, 0xff,
+	0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xf7, 0xf7,
+	0x2f, 0xaf, 0xf3, 0xfb, 0xef, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xcf, 0xbf, 0xfb,
+	0xbf, 0x87, 0xf8, 0xf8, 0xdf, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xeb, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+	0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xdf, 0xf7, 0xff, 0xff, 0xcf, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xfe,
+	0xcf, 0xff, 0x7b, 0xfd, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xdf, 0xff, 0xbf, 0xff,
+	0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xef, 0xff,
+	0xfb, 0xbe, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xd4, 0xbf, 0xf0,
+	0xbf, 0xff, 0xff, 0xff, 0x93, 0x2f, 0xfd, 0xad,
+	0xf7, 0x75, 0xff, 0xff, 0xfe,
+	0xbf, 0x7f, 0xff, 0x9a, 0xff, 0xf4, 0x0f, 0xff,
+	0x00, 0xde, 0xf0, 0xf3, 0xf9, 0xbf, 0x7d, 0xff,
+	0x8f, 0x7f, 0x81, 0x0f, 0xd1,
+	0xff, 0xfb, 0xdf, 0xee, 0x8b, 0x0b, 0x78, 0xf0,
+	0xff, 0xfa, 0x7f, 0xbf, 0xff, 0xd5, 0x8f, 0x8f,
+	0xe1, 0xf7, 0xfb, 0xfb, 0xff,
+	0x7f, 0xb7, 0x99, 0xef, 0xdf, 0xf4, 0xff, 0xff,
+	0xe4, 0xf4, 0x5d, 0xf6, 0xef, 0x9f, 0xef, 0xf7,
+	0x3b, 0x3f, 0xdf, 0xbf, 0xec,
+	0xff, 0xec, 0xf7, 0xb9, 0x6b, 0xbc, 0xfb, 0xf7,
+	0xef, 0xff, 0x7e, 0xfd, 0x7e, 0xbb, 0xdf, 0x85,
+	0xfe, 0xf7, 0xff, 0x7b, 0x7f,
+	0xff, 0xff, 0xa7, 0xee, 0xe7, 0x5f, 0xe0, 0xf0,
+	0xff, 0xff, 0xff, 0x5f, 0xe6, 0x6f, 0x81, 0x8d,
+	0xd5, 0xf7, 0xbf, 0xef, 0xb6,
+	0xff, 0xd7, 0xf4, 0xee, 0xb7, 0x7c, 0xff, 0xd7,
+	0xaf, 0x7f, 0xed, 0x9f, 0xe5, 0xbf, 0xf7, 0x7d,
+	0xfb, 0xb7, 0xad, 0xd7, 0xfd,
+	0xbf, 0xff, 0xff, 0xc7, 0x8b, 0xff, 0xf0, 0xf6,
+	0xff, 0xfd, 0xfb, 0xff, 0xdf, 0xbe, 0x0f, 0x7f,
+	0xd5, 0xf7, 0xff, 0xf2, 0xfe,
+	0xff, 0xff, 0xc5, 0xff, 0xf0, 0x7c, 0xff, 0xad,
+	0x7f, 0x7f, 0xef, 0xff, 0xcf, 0x4f, 0xf1, 0xf5,
+	0x7b, 0xdd, 0xff, 0xdf, 0xff,
+	0xff, 0x77, 0xef, 0xff, 0xd8, 0xbf, 0xf7, 0xf3,
+	0x5f, 0xfb, 0xf9, 0x7f, 0xe7, 0xff, 0xd7, 0x7f,
+	0xad, 0xff, 0xfb, 0xfb, 0xf3,
+	0xff, 0xcc, 0x95, 0x8f, 0xd8, 0xf3, 0xfc, 0xbc,
+	0xdc, 0xdf, 0xbb, 0x44, 0x8b, 0xcb, 0x87, 0xb1,
+	0xb7, 0xa7, 0x97, 0xee, 0xf3,
+	0xff, 0x7f, 0xb4, 0xbf, 0xff, 0xc7, 0x7f, 0xcb,
+	0xfd, 0xbf, 0x7f, 0x7f, 0x74, 0xe7, 0xdf, 0xf5,
+	0xbb, 0xcf, 0xed, 0xfe, 0xfd,
+	0xff, 0x3f, 0xfb, 0x77, 0xcc, 0xbb, 0xf0, 0xfb,
+	0xff, 0xef, 0xbe, 0xff, 0xcf, 0xff, 0x85, 0x3f,
+	0xb5, 0xff, 0xf7, 0x37, 0x7f,
+	0x3f, 0xf7, 0xbf, 0xcf, 0x9f, 0xd7, 0xf7, 0xef,
+	0xff, 0x78, 0xe7, 0xff, 0xff, 0xff, 0x1f, 0x7f,
+	0x65, 0xbf, 0xbf, 0xff, 0xe7,
+	0xff, 0xff, 0xff, 0xff, 0xdb, 0xf7, 0xdf, 0xff,
+	0x77, 0x7f, 0xff, 0xff, 0xbf, 0xbf, 0xde, 0x77,
+	0xdd, 0xff, 0xff, 0xfe, 0xff,
+	0xbf, 0x68, 0xf8, 0xff, 0xf7, 0xff, 0xcf, 0xcf,
+	0xf3, 0x17, 0x3f, 0xd5, 0xdd, 0xf7, 0xff, 0xff,
+	0xcf, 0xdf, 0x73, 0x95, 0x3f,
+	0xff, 0xac, 0x6f, 0xef, 0x77, 0xdf, 0xff, 0xf7,
+	0xbb, 0x85, 0xdd, 0xe1, 0xf7, 0xfb, 0x7b, 0xdf,
+	0xfe, 0xff, 0xb7, 0x9f, 0x79,
+	0xff, 0xd8, 0xac, 0xfb, 0x47, 0xaf, 0xeb, 0xf7,
+	0xff, 0xaf, 0x2e, 0x70, 0xd9, 0xf7, 0xfb, 0xdf,
+	0xea, 0xfb, 0xfb, 0x1b, 0x5f,
+	0xff, 0xf8, 0x6f, 0xaf, 0xd7, 0xb7, 0xeb, 0xff,
+	0xe7, 0xaf, 0x7c, 0x70, 0xfb, 0xdf, 0xff, 0x7b,
+	0xfb, 0xff, 0xda, 0x9f, 0xf9,
+	0xff, 0x95, 0xbb, 0xfd, 0xc7, 0xcf, 0xfb, 0x83,
+	0xef, 0xf3, 0xbf, 0xcf, 0x47, 0xf7, 0xe7, 0x1f,
+	0xd7, 0x8b, 0x6f, 0x33, 0xbe,
+	0xff, 0xc7, 0x6f, 0xfd, 0x97, 0x2f, 0xeb, 0xb7,
+	0xdc, 0x77, 0xd7, 0x1f, 0x67, 0xf7, 0xe7, 0x9e,
+	0xe7, 0xdb, 0x34, 0xdb, 0xfb,
+	0x7f, 0xa8, 0xef, 0xff, 0xe7, 0xef, 0xff, 0xf7,
+	0xff, 0x8b, 0xbf, 0xd8, 0xef, 0xff, 0xe7, 0xdf,
+	0xf7, 0xfb, 0xf7, 0x9f, 0x66,
+	0xff, 0xfb, 0x6c, 0xff, 0xb7, 0x9f, 0xcf, 0xcb,
+	0xbb, 0x93, 0xaf, 0xff, 0xa8, 0xff, 0xc7, 0x3f,
+	0xa7, 0xcf, 0xfe, 0xe3, 0x3f,
+	0x3f, 0xdf, 0x7b, 0xfa, 0xff, 0xff, 0xff, 0xf7,
+	0x8f, 0x3f, 0xd0, 0xd3, 0x7f, 0xfc, 0xff, 0x8e,
+	0xff, 0xf3, 0x8f, 0x4e, 0xe4,
+	0x7f, 0xb8, 0xff, 0xff, 0xff, 0xef, 0x8f, 0xdf,
+	0xf3, 0xbb, 0x3f, 0xe0, 0xf3, 0xff, 0xff, 0xef,
+	0x8f, 0xd7, 0xf3, 0xab, 0xef,
+	0x7f, 0x8f, 0xf8, 0xfb, 0x8f, 0x6f, 0xa0, 0xff,
+	0xff, 0xdc, 0xff, 0x5f, 0xfc, 0xf3, 0x8f, 0x6e,
+	0xb1, 0xf7, 0xf7, 0xf7, 0x3e,
+	0xff, 0x90, 0x7b, 0xf8, 0xff, 0x7f, 0xdf, 0xff,
+	0xfb, 0x9f, 0x7f, 0xa0, 0xf3, 0xf1, 0xff, 0xff,
+	0xdf, 0xff, 0xdb, 0xbf, 0x3f,
+	0xff, 0xdc, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x77, 0xaf, 0xff, 0xad, 0xf3, 0xf8, 0xff, 0xfe,
+	0xef, 0xff, 0xff, 0x6f, 0xbf,
+	0xff, 0xff, 0xcf, 0xff, 0xa3, 0xff, 0xaf, 0xcf,
+	0x93, 0xc3, 0x74, 0xef, 0xdf, 0xff, 0xab, 0x2f,
+	0xe7, 0xc7, 0xf3, 0x73, 0x79,
+	0xff, 0xff, 0xcf, 0xff, 0xc3, 0x7f, 0x83, 0xe4,
+	0xd3, 0xbc, 0x7b, 0xdb, 0xdf, 0x7f, 0x8b, 0x8e,
+	0x83, 0x01, 0x51, 0xd5, 0x7b,
+	0xff, 0xfb, 0xdf, 0xff, 0xc3, 0xef, 0xb3, 0xff,
+	0xb7, 0xff, 0xfe, 0xbf, 0xdf, 0xff, 0x8b, 0x6e,
+	0xf3, 0xfb, 0xb7, 0x1f, 0xfe,
+	0xbf, 0x82, 0xc8, 0xf8, 0xd3, 0x7f, 0xf3, 0xfb,
+	0xff, 0xef, 0x87, 0x87, 0xd0, 0x70, 0x8b, 0xff,
+	0xf3, 0xff, 0xef, 0xef, 0x87,
+	0xff, 0xff, 0xff, 0xff, 0x47, 0xff, 0xf3, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xdf, 0x7f, 0xcb, 0xef,
+	0xf2, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xf7, 0xef, 0xf2, 0xf7, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xf7, 0xef, 0xdf, 0xf7, 0xca, 0x7f,
+	0xf3, 0xf7, 0xef, 0xff, 0xf6,
+	0xff, 0xfa, 0xfb, 0xff, 0xe7, 0xff, 0xf7, 0xff,
+	0xff, 0xef, 0xff, 0xf7, 0x57, 0x7f, 0xca, 0xef,
+	0xf3, 0xff, 0xff, 0xef, 0xef,
+	0xff, 0xf6, 0xeb, 0xfa, 0xf7, 0xff, 0xf7, 0x8f,
+	0xff, 0xe3, 0xf7, 0xef, 0xd7, 0xf7, 0xcb, 0x7f,
+	0xf3, 0x8f, 0x6c, 0xf2, 0xe7,
+	0xff, 0xff, 0x2f, 0xff, 0xf1, 0x9d, 0x9e, 0xf4,
+	0xff, 0xff, 0xff, 0xef, 0x0f, 0xff, 0xf1, 0x09,
+	0x3f, 0xf9, 0xbf, 0xf7, 0xfb,
+	0xff, 0xef, 0x7f, 0xf6, 0xfb, 0xf5, 0x0f, 0xdf,
+	0x00, 0xff, 0xd0, 0xbf, 0xc0, 0xbf, 0xf9, 0xff,
+	0x8f, 0x7f, 0x81, 0x6f, 0xe1,
+	0xff, 0xff, 0x9e, 0xaf, 0xf7, 0x0f, 0x18, 0xd9,
+	0xbf, 0x6f, 0x37, 0xef, 0x8f, 0xff, 0x9e, 0x06,
+	0x75, 0xf7, 0xf6, 0xff, 0xef,
+	0x7f, 0xf7, 0xcf, 0xbb, 0xfb, 0x6d, 0xfb, 0xef,
+	0x7d, 0xe9, 0xff, 0xff, 0xbf, 0xc2, 0xf7, 0x6f,
+	0xff, 0xdc, 0xff, 0xf3, 0xfa,
+	0x7f, 0x6f, 0xf7, 0xf9, 0xff, 0x6d, 0xfe, 0x9c,
+	0xbf, 0xbf, 0x7d, 0xe2, 0x7f, 0x77, 0x9f, 0xcd,
+	0xb7, 0xb5, 0xff, 0xff, 0x7f,
+	0x7f, 0xff, 0x87, 0xae, 0x86, 0xdf, 0xc0, 0xfd,
+	0xfb, 0xfa, 0xff, 0xff, 0x8e, 0x6d, 0xd5, 0x3d,
+	0xf1, 0xff, 0xfe, 0xef, 0xff,
+	0xff, 0x3f, 0xd2, 0xa4, 0xfe, 0xd9, 0xf7, 0xfe,
+	0xdf, 0xff, 0xcb, 0xff, 0xdd, 0x7e, 0xbb, 0xdd,
+	0x5f, 0xf7, 0xbf, 0xff, 0xed,
+	0xff, 0xfe, 0xf5, 0xff, 0xb7, 0xf6, 0xb4, 0xae,
+	0xfe, 0xef, 0xf7, 0xff, 0xff, 0x8f, 0x07, 0x7b,
+	0xfb, 0xff, 0x7f, 0xff, 0xf7,
+	0xff, 0x7b, 0xa3, 0xbf, 0xe3, 0xff, 0xff, 0xf7,
+	0xf7, 0xfd, 0xdf, 0xff, 0x8f, 0x7f, 0x9b, 0xdf,
+	0xfb, 0xef, 0xfe, 0xff, 0x3f,
+	0xff, 0x6f, 0xff, 0x7f, 0xb3, 0x7f, 0xdf, 0xbd,
+	0x78, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xef, 0xff,
+	0xdf, 0xee, 0x9d, 0xfd, 0xef,
+	0xff, 0xf8, 0x05, 0x8e, 0xb0, 0x58, 0xf7, 0xfc,
+	0xa4, 0x85, 0xdd, 0xbc, 0x0b, 0x05, 0x61, 0xf8,
+	0xb7, 0xff, 0xeb, 0xef, 0x7f,
+	0xbf, 0xff, 0xc7, 0xbb, 0xd8, 0x6f, 0x79, 0xde,
+	0xff, 0xff, 0xcf, 0xff, 0xba, 0xaf, 0xd9, 0x7b,
+	0xfd, 0xff, 0xf5, 0xdf, 0xbf,
+	0xff, 0xff, 0xaf, 0x7f, 0x88, 0x7f, 0xf0, 0xea,
+	0xfe, 0x7f, 0xf2, 0xff, 0xdf, 0xd7, 0x4f, 0x7f,
+	0xe3, 0xde, 0xff, 0xff, 0xf7,
+	0xff, 0x7d, 0x6f, 0x5f, 0xab, 0xff, 0x7a, 0xb6,
+	0xbf, 0x78, 0xdd, 0x7f, 0xde, 0xef, 0x4b, 0x9b,
+	0xeb, 0x7f, 0x76, 0x9f, 0xac,
+	0xff, 0xcf, 0xff, 0xff, 0xb7, 0x7f, 0xae, 0xef,
+	0xdb, 0xef, 0xff, 0xf7, 0xff, 0xfb, 0xe7, 0xfe,
+	0xbf, 0x7e, 0xfb, 0xf7, 0xfb,
+	0xff, 0xff, 0xff, 0xff, 0xcf, 0xbf, 0xff, 0xff,
+	0xf3, 0xff, 0xff, 0xff, 0xff, 0xef, 0xd7, 0xff,
+	0xe9, 0xef, 0xf2, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0xef, 0xff, 0x8d, 0xaf, 0xf2,
+	0x71, 0xff, 0xfe, 0xff, 0xff, 0x7f, 0xff, 0xcf,
+	0x0f, 0x75, 0xf1, 0xff, 0xff,
+	0x3f, 0x78, 0xbc, 0xfb, 0xfe, 0xff, 0xff, 0xbf,
+	0xf3, 0x0f, 0x3f, 0xc9, 0xe9, 0x7f, 0xf7, 0xdf,
+	0xff, 0xff, 0x57, 0x82, 0x2e,
+	0xff, 0xf8, 0x7f, 0xfb, 0x7a, 0xfb, 0xff, 0xff,
+	0xeb, 0x87, 0x9b, 0xf1, 0xe5, 0x7f, 0x75, 0x7f,
+	0xfe, 0xff, 0xbe, 0x39, 0x79,
+	0xff, 0xcd, 0xbf, 0xfd, 0x7e, 0xff, 0xfb, 0xf4,
+	0xf7, 0xed, 0x6f, 0xf3, 0x6b, 0xf7, 0xd7, 0xbf,
+	0xfe, 0xfd, 0xf7, 0x8f, 0xef,
+	0xff, 0xf8, 0x7a, 0xff, 0xfa, 0xf0, 0xff, 0xff,
+	0xe6, 0x8f, 0x9b, 0xf1, 0xad, 0xbf, 0xf7, 0xfd,
+	0xbf, 0xfd, 0xef, 0x8f, 0x3f,
+	0xbf, 0xff, 0xad, 0xfb, 0xf4, 0xbf, 0xf3, 0x90,
+	0xdd, 0xf0, 0xfa, 0xcf, 0xe7, 0xf2, 0xf7, 0x7f,
+	0xff, 0xad, 0xff, 0xf5, 0xdf,
+	0xff, 0xcb, 0x7b, 0xfa, 0xd2, 0x7f, 0xc7, 0xf3,
+	0xa9, 0xf7, 0xe7, 0x8b, 0xe7, 0xf1, 0xf7, 0x3f,
+	0x8f, 0x7f, 0xb0, 0xdf, 0xfd,
+	0x7f, 0xf8, 0xff, 0xfb, 0xf2, 0xff, 0xd2, 0xe3,
+	0xdf, 0x87, 0xd3, 0xf0, 0xed, 0xff, 0xf7, 0x7f,
+	0xff, 0xef, 0x77, 0xaa, 0x7f,
+	0xbf, 0xea, 0xfc, 0xfb, 0xb3, 0xbf, 0xb3, 0xff,
+	0xd8, 0x93, 0xab, 0xf1, 0xac, 0xff, 0xf7, 0x3f,
+	0xaf, 0xef, 0xed, 0xc7, 0xad,
+	0xff, 0xd6, 0xff, 0xfd, 0xff, 0xdf, 0xff, 0xf4,
+	0x8f, 0xbf, 0xb1, 0xed, 0xf5, 0xfb, 0xff, 0xef,
+	0xff, 0xf5, 0x8f, 0xdf, 0xf1,
+	0xff, 0xf8, 0xfe, 0xfb, 0xff, 0xdf, 0x9f, 0xf8,
+	0xf0, 0xef, 0xff, 0xd0, 0xfd, 0xf7, 0xff, 0xef,
+	0xaf, 0xf5, 0xf7, 0xce, 0x7f,
+	0x7f, 0x83, 0x7d, 0xfa, 0x8f, 0x5f, 0xd0, 0xcb,
+	0xe9, 0xbb, 0x76, 0x9f, 0x7b, 0xf7, 0x8f, 0x6e,
+	0xb1, 0xd5, 0xf7, 0x5f, 0xc6,
+	0xff, 0xa3, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
+	0xdf, 0x9f, 0x7f, 0xa8, 0x77, 0xf5, 0xff, 0xfe,
+	0xff, 0xff, 0xfe, 0x7f, 0x2d,
+	0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
+	0x37, 0x6f, 0xfd, 0xaf, 0x77, 0xf8, 0xff, 0xff,
+	0xef, 0xff, 0xff, 0xff, 0x4b,
+	0xff, 0x72, 0xaf, 0xff, 0xe5, 0xdf, 0x99, 0xfc,
+	0x10, 0x63, 0xf0, 0xef, 0xef, 0x7f, 0x8b, 0xef,
+	0xaf, 0xe7, 0xf5, 0xf7, 0x7d,
+	0xff, 0xef, 0x8f, 0xff, 0xa1, 0x4f, 0x81, 0xe7,
+	0xb0, 0xfa, 0xfe, 0xd7, 0xcf, 0xff, 0xca, 0xcf,
+	0x0b, 0x85, 0x71, 0xfa, 0xff,
+	0xff, 0xdd, 0xef, 0xff, 0xa4, 0xdf, 0xb1, 0xdc,
+	0xd3, 0xff, 0xf8, 0xff, 0xcf, 0x7f, 0xcb, 0x7f,
+	0xff, 0xf5, 0xff, 0xbf, 0xfd,
+	0xbf, 0x82, 0xc8, 0xf8, 0xe1, 0x7f, 0xf0, 0xdf,
+	0xff, 0xef, 0x87, 0x87, 0xc0, 0xf0, 0xca, 0x2f,
+	0xfb, 0xff, 0xef, 0xee, 0x97,
+	0xff, 0xff, 0x8f, 0xfa, 0xa5, 0xdf, 0xd1, 0xf7,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0xdb, 0xef,
+	0xff, 0xf5, 0xfd, 0xff, 0xff,
+	0xff, 0xf6, 0x8b, 0xf2, 0x94, 0xff, 0xf1, 0xf7,
+	0xff, 0xff, 0xf7, 0xef, 0xd7, 0xf7, 0xdf, 0xee,
+	0xfb, 0xff, 0xef, 0xff, 0xf7,
+	0xff, 0xf3, 0xcb, 0xff, 0xe6, 0xff, 0xf1, 0xef,
+	0xff, 0xef, 0xff, 0xe7, 0xd7, 0x7f, 0xdb, 0x7e,
+	0xfd, 0xf7, 0xff, 0xef, 0xef,
+	0xff, 0xfe, 0xcf, 0xff, 0xc4, 0xff, 0xf2, 0x9f,
+	0xff, 0xe0, 0xf7, 0xff, 0xdf, 0xff, 0xdf, 0x7f,
+	0xdb, 0xac, 0xef, 0xf1, 0xf7,
+	0x7f, 0xef, 0x0f, 0x5f, 0xb4, 0x8f, 0xff, 0xf6,
+	0xfd, 0xff, 0x6f, 0xff, 0x8f, 0xff, 0xe9, 0x8d,
+	0x7f, 0xf1, 0xd1, 0xf7, 0xfe,
+	0xff, 0xe7, 0x7f, 0x87, 0xfd, 0xe7, 0x8f, 0x9b,
+	0x00, 0xff, 0xb0, 0x7d, 0xfd, 0xcf, 0xfb, 0xfd,
+	0x8f, 0x7f, 0x81, 0x6d, 0xd1,
+	0xff, 0xbc, 0xed, 0xff, 0x86, 0x6e, 0x10, 0xf1,
+	0xf4, 0x5f, 0x7f, 0xfe, 0x9f, 0x37, 0xc3, 0x8f,
+	0xf7, 0xe5, 0xfb, 0xff, 0xff,
+	0x7f, 0xfe, 0xff, 0xfd, 0x97, 0xff, 0xfb, 0xff,
+	0x3f, 0xff, 0xf9, 0xc3, 0x1f, 0xf8, 0xff, 0xb5,
+	0x5f, 0xef, 0xdc, 0xff, 0xbe,
+	0xff, 0xcb, 0xe7, 0xfd, 0x69, 0xe7, 0xfc, 0xb6,
+	0xef, 0x9a, 0x77, 0xb6, 0x67, 0xdf, 0xef, 0xf7,
+	0xfe, 0xdf, 0xff, 0xf5, 0x7f,
+	0xff, 0xf7, 0x97, 0xbe, 0xf4, 0xff, 0xf1, 0xba,
+	0xfe, 0xff, 0x97, 0x7f, 0xbf, 0x77, 0x55, 0xdf,
+	0xd9, 0xf1, 0xff, 0xdf, 0xff,
+	0xbf, 0xbf, 0x72, 0xf2, 0xdd, 0xff, 0xe4, 0xff,
+	0x7f, 0xef, 0xff, 0xf7, 0xfe, 0xfb, 0xb9, 0xff,
+	0xff, 0xf5, 0xff, 0xfb, 0x96,
+	0xff, 0x7f, 0xf7, 0xef, 0x83, 0xf7, 0xf7, 0xff,
+	0xdf, 0xff, 0xf7, 0xfd, 0xd5, 0x9f, 0x0f, 0x7f,
+	0xf0, 0xfb, 0xae, 0xff, 0xec,
+	0xff, 0x7b, 0x85, 0xf7, 0xf3, 0xef, 0xff, 0xf7,
+	0xff, 0xed, 0xff, 0xe7, 0x8f, 0x7f, 0xc7, 0x97,
+	0x3f, 0xfc, 0xff, 0xf7, 0xde,
+	0xff, 0xfd, 0x8b, 0xff, 0xf7, 0x1f, 0xfb, 0xff,
+	0x2f, 0xfb, 0xf7, 0xff, 0xbf, 0xff, 0xff, 0x6f,
+	0xf7, 0xf9, 0xe7, 0xff, 0x33,
+	0xff, 0x9e, 0xe7, 0x8b, 0xf0, 0x50, 0xf1, 0xde,
+	0xff, 0x9f, 0x1b, 0x28, 0x1b, 0x8d, 0xb4, 0xe1,
+	0xf5, 0xf3, 0xfe, 0xef, 0xfa,
+	0xff, 0x7f, 0xf6, 0xff, 0xfe, 0x07, 0xec, 0xfb,
+	0x7f, 0xff, 0xfd, 0xff, 0xd6, 0x8f, 0xff, 0xf9,
+	0xff, 0x37, 0x7f, 0xfb, 0xdd,
+	0xff, 0xff, 0xff, 0x63, 0xef, 0xdf, 0xfa, 0xf1,
+	0xff, 0xfc, 0xfe, 0xdf, 0xfb, 0xff, 0x8f, 0x7f,
+	0xf9, 0xeb, 0xef, 0xfd, 0xff,
+	0x7f, 0x7f, 0xfb, 0xe7, 0x9f, 0x9b, 0xe5, 0xcf,
+	0xfd, 0xf7, 0xcf, 0xff, 0xf3, 0xbf, 0x5f, 0x5d,
+	0x67, 0x9f, 0xdf, 0x7f, 0xf9,
+	0xff, 0xff, 0xff, 0x1f, 0xfe, 0xff, 0xf5, 0xdf,
+	0x5f, 0xfb, 0xfb, 0xbf, 0xcf, 0xdf, 0xfb, 0x7f,
+	0xb7, 0xff, 0xfb, 0xff, 0xf7,
+	0x3f, 0x78, 0xfc, 0xf3, 0xff, 0xff, 0xdf, 0xbf,
+	0xf3, 0x05, 0x3f, 0xc1, 0xf1, 0xff, 0xf7, 0xef,
+	0xef, 0xff, 0xfb, 0x97, 0x1f,
+	0xff, 0xd8, 0x7f, 0xfb, 0x7b, 0xfb, 0xf7, 0xbf,
+	0xbb, 0x8e, 0xd3, 0xe1, 0xff, 0xfd, 0xf7, 0xed,
+	0xfe, 0x8b, 0x5e, 0x0f, 0x69,
+	0xbf, 0xf8, 0xfc, 0xfb, 0x7b, 0xff, 0xdf, 0xed,
+	0xf7, 0x8f, 0xbf, 0xce, 0xfe, 0xff, 0xf3, 0xff,
+	0xf6, 0xff, 0xfe, 0x8f, 0x0f,
+	0xff, 0xfc, 0x7d, 0xff, 0xff, 0xfd, 0xf3, 0xff,
+	0xbf, 0x8f, 0xe3, 0xf0, 0xfe, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0xae, 0x0f, 0x5d,
+	0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xd1,
+	0xfd, 0xf1, 0xd3, 0xdd, 0xfd, 0xf1, 0xfb, 0xff,
+	0xfb, 0xfd, 0xff, 0xfd, 0xf6,
+	0xff, 0xff, 0x7f, 0xfe, 0xfd, 0xff, 0x87, 0xff,
+	0xcc, 0xf3, 0xdf, 0xcb, 0xff, 0xfb, 0xfb, 0xff,
+	0x8b, 0x7f, 0xfa, 0xff, 0xff,
+	0x7f, 0xf8, 0xfe, 0xff, 0xef, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xe8, 0xff, 0xff, 0xf9, 0xff,
+	0xfb, 0xaf, 0x7f, 0x8f, 0x7e,
+	0xbf, 0xfb, 0x78, 0xff, 0xff, 0xff, 0xd7, 0xd3,
+	0xfd, 0xc3, 0x95, 0xc5, 0xf8, 0xff, 0xfb, 0xff,
+	0xfb, 0xff, 0xfc, 0xf2, 0x8f,
+	0xff, 0x8b, 0x7b, 0xff, 0xff, 0xdf, 0xff, 0xfd,
+	0x8f, 0xef, 0xf4, 0xb7, 0xff, 0xfe, 0xff, 0xfe,
+	0xff, 0xff, 0x8f, 0x6f, 0xf4,
+	0xff, 0xfd, 0xff, 0xfe, 0xff, 0xdf, 0xdf, 0xfd,
+	0xf1, 0xb3, 0xff, 0xd8, 0xff, 0xfd, 0xff, 0xff,
+	0xff, 0xfd, 0xf5, 0x87, 0x7f,
+	0x3f, 0xef, 0xff, 0xff, 0x8f, 0x5f, 0xf0, 0xff,
+	0xf1, 0xef, 0x39, 0xc7, 0x7e, 0xf3, 0x8f, 0x7e,
+	0xf1, 0xbd, 0xed, 0xfa, 0x9a,
+	0xff, 0x98, 0x7f, 0xfa, 0xff, 0x7f, 0xff, 0xff,
+	0xf3, 0x8f, 0x5f, 0x8a, 0xfb, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0xaf, 0x5f,
+	0xff, 0x86, 0xff, 0xfc, 0xff, 0xff, 0xdf, 0xff,
+	0x7f, 0xbf, 0xcb, 0xbd, 0x77, 0xf2, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xbf, 0x77,
+	0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xff, 0xdd,
+	0x11, 0x73, 0xfc, 0xfc, 0xef, 0xff, 0xfb, 0xff,
+	0xfd, 0xfd, 0x9d, 0xf3, 0xff,
+	0xff, 0xf9, 0xef, 0xff, 0xf3, 0x0f, 0x83, 0x9e,
+	0xf0, 0xf0, 0xff, 0xed, 0xef, 0xff, 0xe9, 0x8e,
+	0x7b, 0x9d, 0x70, 0xe9, 0xf7,
+	0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xf3, 0xf9,
+	0xf7, 0xff, 0xfb, 0xf3, 0xef, 0xfd, 0xeb, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xf8,
+	0x3f, 0x87, 0xec, 0xf8, 0xe5, 0x7f, 0xfb, 0xff,
+	0xff, 0xff, 0x8f, 0x87, 0xe8, 0xf0, 0xeb, 0xff,
+	0xff, 0xfd, 0xff, 0xff, 0x97,
+	0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xd3, 0xbf,
+	0x7f, 0xfe, 0xff, 0xff, 0xef, 0xff, 0xe3, 0xef,
+	0xff, 0xff, 0xff, 0xfe, 0xff,
+	0xff, 0x77, 0xef, 0xfa, 0xe7, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0xef, 0xef, 0xef, 0xf7, 0xea, 0xfe,
+	0xf3, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xf7, 0xeb, 0xf3, 0xef, 0xff, 0xf3, 0xff,
+	0xf1, 0x7f, 0xff, 0xe7, 0xe7, 0xf7, 0xea, 0xee,
+	0xf7, 0xff, 0xf1, 0xff, 0xe7,
+	0xff, 0xfb, 0x6f, 0xf6, 0xe5, 0xff, 0xeb, 0xdf,
+	0xef, 0xff, 0xff, 0xf7, 0xef, 0xff, 0xe3, 0xef,
+	0xff, 0xfe, 0xff, 0xfe, 0xf7,
+	0x7f, 0xff, 0x4f, 0x5f, 0xe1, 0xc7, 0xef, 0xf1,
+	0xfe, 0x7f, 0x7b, 0xff, 0x6f, 0xff, 0x93, 0x0b,
+	0x7f, 0xf1, 0xfa, 0xdf, 0xff,
+	0xff, 0xfb, 0x7f, 0xdf, 0xf7, 0xef, 0x8f, 0xff,
+	0x00, 0xef, 0xf0, 0xdf, 0x7f, 0xef, 0xff, 0xfb,
+	0x8f, 0x7f, 0x81, 0x6f, 0xd1,
+	0xff, 0xde, 0xff, 0xef, 0xb9, 0x49, 0x74, 0xf3,
+	0xef, 0x7b, 0x7f, 0xff, 0xeb, 0xf7, 0x85, 0x67,
+	0xf1, 0xf0, 0xe1, 0xff, 0xf7,
+	0x3f, 0xab, 0xff, 0xc4, 0xbb, 0xff, 0x8c, 0x9d,
+	0x7e, 0x3a, 0xb5, 0xbb, 0xe3, 0xfb, 0xf3, 0xcd,
+	0xe3, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xdc, 0xf7, 0xf8, 0x77, 0x8f, 0xf7, 0xfe,
+	0x9f, 0x97, 0x7a, 0xf2, 0x7f, 0xfb, 0x8f, 0x1f,
+	0x7d, 0xfd, 0xef, 0xb1, 0x7d,
+	0xff, 0xef, 0xa6, 0xef, 0x98, 0x9d, 0xf0, 0xf4,
+	0xf4, 0xff, 0xff, 0x7f, 0x8f, 0x7f, 0x89, 0x7f,
+	0xe7, 0xff, 0xff, 0xf7, 0xfb,
+	0xbf, 0xa7, 0xb7, 0xdf, 0xba, 0xfd, 0xfe, 0xeb,
+	0xff, 0xff, 0xc4, 0xef, 0x8f, 0x7c, 0xf7, 0x8f,
+	0x7f, 0xf9, 0xfb, 0xff, 0xfb,
+	0xff, 0xff, 0xff, 0xeb, 0x87, 0xfd, 0xf4, 0xf7,
+	0x6f, 0xff, 0xbf, 0xff, 0xff, 0xef, 0xef, 0xdf,
+	0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xf7, 0x85, 0xdb, 0xf2, 0xbf, 0xd7, 0xff,
+	0xff, 0xfd, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xaf,
+	0x7d, 0xff, 0xf7, 0xeb, 0xff,
+	0xbf, 0xfd, 0x8f, 0xff, 0xfa, 0x3f, 0xff, 0xf6,
+	0xb7, 0xff, 0xfe, 0xfb, 0x8f, 0x7f, 0xff, 0xff,
+	0xf3, 0xee, 0xbf, 0x7f, 0xff,
+	0xff, 0x67, 0xc6, 0xaf, 0xc3, 0x74, 0xf7, 0xfe,
+	0xee, 0x8a, 0x37, 0x6e, 0xec, 0x87, 0x71, 0x91,
+	0x13, 0x7d, 0xec, 0x87, 0xff,
+	0xbf, 0x7b, 0xf0, 0xef, 0xfb, 0x3f, 0xb7, 0xfc,
+	0xff, 0xff, 0x97, 0x7d, 0xe8, 0xef, 0x9d, 0x77,
+	0xfd, 0xfb, 0xff, 0xfb, 0xbf,
+	0xff, 0xff, 0xde, 0x77, 0xcd, 0xff, 0xf1, 0xfb,
+	0xff, 0xff, 0xf9, 0xe3, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xfc, 0xcf, 0xff, 0xf3,
+	0x7f, 0xff, 0xfe, 0x77, 0xaf, 0xf7, 0xf8, 0xef,
+	0xff, 0x76, 0xfa, 0xff, 0x99, 0x6d, 0x9f, 0x6f,
+	0xf1, 0xbf, 0x7f, 0x7f, 0xfc,
+	0xff, 0xff, 0xef, 0xbf, 0xeb, 0xfa, 0xdd, 0xef,
+	0xbc, 0xfd, 0xfd, 0xdf, 0xff, 0xf7, 0xff, 0xff,
+	0xd1, 0xfe, 0xff, 0xfb, 0xff,
+	0x3f, 0x70, 0xf8, 0xff, 0xf5, 0xff, 0xff, 0x9f,
+	0xf3, 0x09, 0x1f, 0xe1, 0xf3, 0xfd, 0xfd, 0xff,
+	0xef, 0xff, 0xf7, 0x8e, 0x1e,
+	0xff, 0xf8, 0x7f, 0xff, 0x77, 0xff, 0xff, 0x9b,
+	0x8f, 0x8e, 0xfb, 0xf1, 0xef, 0xe5, 0xfd, 0xef,
+	0xfe, 0x9f, 0x16, 0x03, 0x61,
+	0xbf, 0xf8, 0xfa, 0xfd, 0x73, 0xff, 0xff, 0xf7,
+	0xf7, 0x8d, 0x9f, 0xe1, 0xf1, 0xff, 0xef, 0xff,
+	0xfc, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xfd, 0xff,
+	0x9f, 0x8f, 0xe1, 0xf1, 0xef, 0xff, 0xff, 0xff,
+	0xfd, 0xff, 0x8e, 0x0f, 0x7d,
+	0xff, 0xf7, 0xf9, 0xfe, 0xf3, 0x7f, 0xff, 0xf7,
+	0xf7, 0xf3, 0xfd, 0xef, 0xff, 0xf9, 0xed, 0xff,
+	0xff, 0xef, 0xff, 0xf7, 0xff,
+	0xff, 0xf7, 0x7e, 0xfe, 0xf7, 0xff, 0x8b, 0xf7,
+	0xfc, 0xeb, 0xeb, 0xed, 0xeb, 0xf9, 0xfd, 0xff,
+	0x8f, 0x7f, 0xf2, 0xfe, 0xed,
+	0x7f, 0xf8, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7,
+	0xf7, 0x8d, 0xff, 0xe8, 0xff, 0xfd, 0xef, 0xfe,
+	0xfd, 0xdf, 0xf6, 0x8f, 0x6f,
+	0xbf, 0xff, 0x78, 0xff, 0xf7, 0xff, 0xfb, 0xff,
+	0xff, 0xe3, 0x9f, 0xe5, 0xea, 0xf5, 0xfd, 0xff,
+	0xed, 0xef, 0xff, 0xf7, 0x8f,
+	0xff, 0x07, 0xff, 0xf9, 0xff, 0xff, 0xff, 0xf7,
+	0x8f, 0xff, 0xf3, 0x93, 0xff, 0xff, 0xff, 0xef,
+	0xff, 0xf7, 0x8f, 0x7f, 0xf3,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x8b, 0xff, 0xe8, 0xfb, 0xff, 0xff, 0xef,
+	0xef, 0xf7, 0xf5, 0x8e, 0x7f,
+	0x3f, 0xec, 0xf9, 0xfc, 0x8f, 0x7f, 0xf0, 0xef,
+	0xef, 0xff, 0x1d, 0xed, 0x7e, 0xfd, 0x8f, 0x6e,
+	0xf1, 0xd7, 0xf7, 0xde, 0x8c,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xfb, 0x8f, 0x6f, 0x90, 0xff, 0xf3, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x87, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x9f, 0xff, 0x93, 0x7f, 0xf2, 0xff, 0xfe,
+	0xef, 0xff, 0xff, 0x9f, 0x69,
+	0xff, 0xfb, 0xef, 0xff, 0xf6, 0xff, 0xff, 0xff,
+	0x1f, 0x73, 0xfe, 0xf6, 0xff, 0xff, 0xff, 0xef,
+	0xef, 0xe7, 0x97, 0x77, 0xf7,
+	0xff, 0xff, 0xff, 0xff, 0xe7, 0x1f, 0x86, 0x95,
+	0xf0, 0xf6, 0xf7, 0xff, 0xff, 0xff, 0xfe, 0x8f,
+	0x6d, 0x93, 0x71, 0xf8, 0xfd,
+	0xff, 0xfe, 0xef, 0xfd, 0xf2, 0xff, 0xf6, 0xff,
+	0x6f, 0xef, 0xf7, 0xfd, 0xff, 0xff, 0xfd, 0xff,
+	0xfd, 0xff, 0xef, 0xff, 0xf5,
+	0x3f, 0x82, 0xf8, 0xf8, 0xe6, 0x7f, 0xf2, 0xff,
+	0xff, 0xff, 0x87, 0x87, 0xf0, 0xf0, 0xfc, 0xef,
+	0xfd, 0xf7, 0xef, 0xee, 0x87,
+	0xff, 0xff, 0xef, 0xff, 0xe7, 0xff, 0xf6, 0xf7,
+	0x7f, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+	0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xf7, 0xff, 0xf2, 0xe6, 0xff, 0xf5, 0xf7,
+	0xff, 0xff, 0xff, 0xe7, 0xff, 0xf7, 0xff, 0xfe,
+	0xff, 0xf7, 0xef, 0xff, 0xf7,
+	0xff, 0xfa, 0xeb, 0xff, 0xe3, 0xff, 0xf5, 0xff,
+	0xff, 0xff, 0xf7, 0xef, 0xf7, 0xff, 0xfd, 0xee,
+	0xfd, 0xff, 0xff, 0xef, 0xef,
+	0xff, 0xf6, 0xfb, 0x7a, 0xe7, 0xff, 0x91, 0xef,
+	0xff, 0xe2, 0xff, 0xf7, 0xf7, 0xf7, 0xfd, 0xff,
+	0xfd, 0xef, 0xeb, 0xf5, 0xe7,
+	0xff, 0xff, 0x8f, 0xbe, 0xf1, 0x93, 0xfd, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0x2e, 0x2f, 0x59, 0x8f,
+	0x6f, 0xf9, 0xf7, 0xff, 0xfa,
+	0xff, 0x4f, 0xbf, 0xc4, 0xfb, 0xf5, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x7f, 0x70, 0xaf, 0x7f, 0xff,
+	0x8f, 0x7f, 0x81, 0x7f, 0xb1,
+	0xff, 0xff, 0xda, 0xff, 0x2f, 0x4f, 0x7e, 0xf9,
+	0xfb, 0xff, 0x5f, 0xef, 0xff, 0xff, 0x99, 0x29,
+	0x71, 0xf1, 0xed, 0xff, 0xff,
+	0x3f, 0xb7, 0xef, 0xdf, 0xff, 0xf9, 0xfe, 0xfd,
+	0xff, 0xff, 0xb7, 0x9f, 0xff, 0xab, 0x73, 0xfd,
+	0xad, 0x3c, 0x6b, 0xff, 0xfa,
+	0xff, 0xe8, 0xf7, 0xbf, 0x6f, 0x8f, 0xff, 0xfe,
+	0xff, 0x87, 0x7f, 0xe0, 0x7f, 0xbf, 0x5f, 0x93,
+	0x7e, 0xe4, 0xf6, 0x97, 0x7b,
+	0xff, 0xdf, 0x27, 0xaf, 0xa7, 0xff, 0xf4, 0xf6,
+	0xff, 0xff, 0xff, 0x5f, 0xdf, 0xfb, 0x87, 0x1f,
+	0x70, 0xf3, 0xfe, 0x7f, 0xfb,
+	0xbf, 0xb7, 0x61, 0xb5, 0xfc, 0xff, 0xf7, 0xff,
+	0xbf, 0xff, 0xa2, 0xff, 0xd8, 0xa1, 0x77, 0xdf,
+	0xe6, 0xff, 0xff, 0x7e, 0xc4,
+	0xff, 0xff, 0xf6, 0xd7, 0x97, 0xdb, 0xe8, 0xff,
+	0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xb9, 0x3b,
+	0xf8, 0xff, 0xef, 0xe7, 0xbe,
+	0xff, 0xff, 0x86, 0xbf, 0xe2, 0xad, 0xff, 0xff,
+	0xff, 0xff, 0x9f, 0xff, 0x8f, 0x3f, 0x63, 0xcf,
+	0x7b, 0xfe, 0xff, 0xfd, 0xfe,
+	0xff, 0xff, 0xdf, 0xff, 0xba, 0x7f, 0xf7, 0xee,
+	0x17, 0xf7, 0xee, 0xef, 0x97, 0x7f, 0xf7, 0xff,
+	0xff, 0xfd, 0x9e, 0x77, 0xf3,
+	0xff, 0xfb, 0xc3, 0x8f, 0xc1, 0x70, 0x71, 0xff,
+	0xf7, 0x9f, 0x77, 0x7e, 0xb6, 0x4f, 0xb9, 0x01,
+	0x1f, 0x1b, 0x7a, 0x9a, 0x7e,
+	0xbf, 0xff, 0xf0, 0x9f, 0xef, 0x79, 0x3f, 0xf6,
+	0xff, 0xfd, 0x9d, 0x7b, 0xf2, 0xff, 0xc9, 0xf3,
+	0xff, 0x7d, 0xfb, 0xfd, 0xbf,
+	0xff, 0xfd, 0xbf, 0x77, 0x8f, 0xff, 0xf1, 0xf7,
+	0xff, 0xff, 0xff, 0xfd, 0xbb, 0x7f, 0xbf, 0x6f,
+	0xf3, 0xfe, 0xff, 0xe7, 0xbf,
+	0x7f, 0xff, 0xff, 0x5f, 0xaf, 0xf1, 0xfc, 0xf7,
+	0xff, 0x77, 0xfe, 0xff, 0xdf, 0xff, 0xdf, 0xff,
+	0xe3, 0x9e, 0x7f, 0x7a, 0xe3,
+	0xff, 0xff, 0x6f, 0xff, 0xaf, 0xfc, 0xff, 0xff,
+	0xfe, 0xfe, 0xfe, 0xff, 0xff, 0xff, 0xf3, 0xfb,
+	0xf7, 0xff, 0xf9, 0xfe, 0xff,
+	0x3f, 0x70, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xff, 0xf7, 0xff,
+	0xef, 0xff, 0xf7, 0x8c, 0x1e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xf7, 0xff, 0x8f,
+	0x8f, 0x88, 0xf1, 0xf1, 0xef, 0xff, 0xf7, 0xff,
+	0xee, 0x97, 0x1e, 0x01, 0x61,
+	0xbf, 0xf0, 0xfa, 0xfd, 0x75, 0xff, 0xf5, 0xff,
+	0xff, 0x8f, 0x9f, 0xe1, 0xf1, 0xff, 0xf7, 0xef,
+	0xfe, 0xff, 0xff, 0x8f, 0x1f,
+	0xff, 0xfa, 0x7f, 0xff, 0xfd, 0xff, 0xfd, 0xff,
+	0x9f, 0x9f, 0xf9, 0xf9, 0xff, 0xef, 0xf7, 0xff,
+	0xff, 0xff, 0x9e, 0x0f, 0x75,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
+	0xff, 0xf7, 0xf7, 0xff, 0xef, 0xf7, 0xe7, 0xef,
+	0xef, 0xef, 0xff, 0xff, 0xef,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf8, 0xf7, 0xff, 0xf7, 0xff, 0xf7, 0xe7, 0xef,
+	0x9f, 0x6f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xff, 0xfd, 0xff, 0xfd, 0x8f,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf7, 0xef,
+	0xf7, 0xff, 0xff, 0x9d, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xfd, 0xff, 0xfd, 0xf7,
+	0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xf7, 0xf7, 0xff,
+	0xf7, 0xef, 0xfe, 0xe7, 0x9f,
+	0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf8, 0x8f, 0xff, 0xf8, 0xff, 0xef,
+	0xff, 0xff, 0x8e, 0x6f, 0xe1,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xef, 0xef, 0xff, 0x9f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x9f,
+	0xf7, 0xfb, 0x07, 0xe7, 0x78, 0xf7, 0x8f, 0x7e,
+	0xf1, 0x9f, 0x7f, 0xff, 0x9e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x6f, 0x80, 0xff, 0xf1, 0xff, 0xff,
+	0xef, 0xff, 0xfe, 0x9f, 0x7f,
+	0xff, 0x88, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x9f, 0xef, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xef, 0x9f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x97, 0x77, 0xf8, 0xff, 0xef, 0xff, 0xf7, 0xff,
+	0xef, 0xef, 0x8f, 0x76, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0x0f, 0xf7, 0x88,
+	0xf7, 0xf0, 0xff, 0xff, 0xef, 0xff, 0xef, 0x8e,
+	0x07, 0x99, 0x61, 0xe1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7,
+	0xff, 0xff, 0xf7, 0xf7, 0xef, 0xff, 0xe7, 0xee,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xf7, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xef, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xef, 0xff, 0xe7, 0xff,
+	0xf6, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xe7, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
+	0x97, 0xee, 0xf9, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x80, 0x88, 0xff, 0xf8,
+	0xff, 0xff, 0xf7, 0xff, 0x0f, 0x1f, 0x79, 0x9b,
+	0x7f, 0xf0, 0xfe, 0xff, 0xff,
+	0xff, 0x4f, 0x7b, 0xf7, 0xf7, 0xf8, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x4f, 0x75, 0x8c, 0x79, 0xff,
+	0x8f, 0x7f, 0x81, 0x7e, 0xb1,
+	0xff, 0xf7, 0xff, 0xfe, 0x8f, 0x7f, 0x70, 0xf0,
+	0xff, 0xf7, 0x7f, 0xff, 0xf7, 0xff, 0x84, 0x0e,
+	0x73, 0xff, 0xf7, 0xff, 0xff,
+	0x3f, 0xbd, 0xfd, 0xfb, 0xf7, 0xe8, 0xff, 0xff,
+	0x78, 0xf0, 0x3f, 0xbf, 0xe3, 0x9b, 0x6f, 0xff,
+	0x97, 0x1f, 0x7f, 0xcf, 0xfe,
+	0xff, 0xf8, 0xf7, 0xff, 0x8f, 0x80, 0xff, 0xf8,
+	0xff, 0x8f, 0x78, 0xf0, 0x7f, 0x9f, 0x7f, 0x9b,
+	0x7f, 0xf1, 0xff, 0x97, 0x7f,
+	0xff, 0xff, 0x07, 0xff, 0x87, 0x7f, 0xf0, 0xf8,
+	0xff, 0x7f, 0xfb, 0x7f, 0xee, 0xfb, 0x99, 0x19,
+	0x73, 0xef, 0xf7, 0xef, 0xff,
+	0xbf, 0x87, 0x04, 0xfc, 0xff, 0x08, 0xf7, 0xff,
+	0x7b, 0x7f, 0x8e, 0x8f, 0xf9, 0x98, 0x6f, 0xf3,
+	0xff, 0xef, 0xff, 0xff, 0xdf,
+	0xff, 0xff, 0x73, 0xff, 0xf7, 0x9f, 0xf8, 0xfb,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x3d,
+	0x61, 0xff, 0xef, 0xff, 0xff,
+	0xff, 0x7f, 0x07, 0xff, 0xf8, 0x78, 0xff, 0xee,
+	0xfb, 0xff, 0xff, 0xff, 0x87, 0x1f, 0x71, 0xe3,
+	0xff, 0xfb, 0xff, 0xff, 0xff,
+	0xff, 0x77, 0x8b, 0x7f, 0xf8, 0x7f, 0xff, 0xff,
+	0x07, 0xe7, 0xfa, 0x77, 0x8f, 0x7f, 0xff, 0xef,
+	0xf1, 0xef, 0x9f, 0x77, 0xf9,
+	0xff, 0xf8, 0x73, 0x8f, 0xf8, 0x0f, 0x88, 0x88,
+	0xf8, 0x98, 0x77, 0x78, 0x8f, 0x6f, 0x87, 0x7b,
+	0xf7, 0xff, 0xef, 0x87, 0x6f,
+	0xbf, 0x7f, 0xf0, 0xff, 0x8f, 0x7f, 0xff, 0xff,
+	0x7e, 0xff, 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xeb,
+	0xef, 0xff, 0xfb, 0xff, 0x9f,
+	0xff, 0xff, 0xff, 0x77, 0xf8, 0x7f, 0xf8, 0xf7,
+	0xff, 0x7f, 0xf7, 0xff, 0x9f, 0x7f, 0x9b, 0x6f,
+	0xf1, 0xfe, 0xff, 0xfe, 0xff,
+	0x7f, 0x7f, 0x8f, 0xff, 0x8f, 0xff, 0x7f, 0x8f,
+	0xff, 0x70, 0xfb, 0x6f, 0xff, 0xff, 0xff, 0xf5,
+	0xf9, 0xff, 0xff, 0xff, 0xf4,
+	0xff, 0x87, 0xff, 0x74, 0xff, 0x7f, 0xff, 0xff,
+	0x7e, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff,
+	0xe9, 0xff, 0xf7, 0xff, 0xff,
+	0xbf, 0x78, 0xf8, 0x7f, 0xf7, 0xff, 0xff, 0xff,
+	0xf7, 0x07, 0x1f, 0xe1, 0xf1, 0xff, 0xf7, 0xff,
+	0xef, 0xef, 0xff, 0x8e, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87,
+	0x9f, 0x88, 0xf1, 0xe1, 0xff, 0xef, 0xf7, 0xef,
+	0xfe, 0x9f, 0x0f, 0x09, 0x71,
+	0xbf, 0xf0, 0xf8, 0xff, 0x77, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xf7, 0xff,
+	0xfe, 0xf7, 0xff, 0x8e, 0x1f,
+	0x7f, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x8f, 0xf9, 0xf8, 0xfe, 0xff, 0xe7, 0xf7,
+	0xff, 0xff, 0x96, 0x0f, 0x61,
+	0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0xef, 0xff, 0xf7, 0xe7, 0xef,
+	0xff, 0xe7, 0xff, 0xf7, 0xfe,
+	0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf8, 0xef, 0xef, 0xef, 0xff, 0xf7, 0xf7, 0xff,
+	0x9f, 0x67, 0xf0, 0xff, 0xff,
+	0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x8f, 0xff, 0xe0, 0xf7, 0xff, 0xf7, 0xfe,
+	0xf7, 0xf7, 0xff, 0x8f, 0x6e,
+	0x3f, 0xfb, 0x7c, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xe7, 0x9f, 0xef, 0xf0, 0xff, 0xe7, 0xef,
+	0xf7, 0xef, 0xf6, 0xf6, 0x87,
+	0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf4, 0x9f, 0xff, 0xfc, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf0,
+	0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x87, 0xff, 0xe8, 0xff, 0xf7, 0xff, 0xff,
+	0xef, 0xe7, 0xf7, 0x8f, 0x6f,
+	0x3f, 0xff, 0xfc, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
+	0xef, 0xe8, 0x1b, 0xef, 0x7c, 0xff, 0x8f, 0x7e,
+	0xe1, 0x97, 0x77, 0xff, 0x9e,
+	0xff, 0x80, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xfe,
+	0xef, 0xff, 0xff, 0x9f, 0x7f,
+	0xff, 0x84, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x6f, 0x9f, 0xff, 0x91, 0x7f, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff,
+	0x1f, 0x77, 0xf8, 0xf7, 0xef, 0xff, 0xf7, 0xff,
+	0xf7, 0xef, 0x87, 0x67, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8b, 0x8c,
+	0xf0, 0xf8, 0xf7, 0xff, 0xef, 0xff, 0xe7, 0x9e,
+	0x67, 0x89, 0x77, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0xfb, 0xff, 0xef, 0xff, 0xe7, 0xff,
+	0xf7, 0xf7, 0xff, 0xff, 0xf7,
+	0xbf, 0x87, 0xf8, 0xf8, 0xf7, 0x7f, 0xfb, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xe7, 0xfe,
+	0xf7, 0xff, 0xff, 0xff, 0x8e,
+	0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xfb, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xfb, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x7f, 0xf7, 0xff, 0x8b, 0xff,
+	0xfc, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xee, 0xff, 0xf6, 0xff,
+	0xff, 0xf7, 0x8f, 0xbf, 0xf9, 0x8f, 0xff, 0xf0,
+	0xff, 0xff, 0x7f, 0xff, 0x1f, 0x1f, 0x71, 0x89,
+	0x7f, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0x4f, 0xb8, 0xc6, 0xfb, 0xfd, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x7f, 0x79, 0x90, 0x7f, 0xf9,
+	0x8f, 0x7f, 0x81, 0x7f, 0x81,
+	0xff, 0xff, 0xcf, 0xff, 0xb0, 0x4f, 0x77, 0xf4,
+	0xff, 0xff, 0x7f, 0xe7, 0xee, 0xff, 0x97, 0x07,
+	0x69, 0xf1, 0xf7, 0xff, 0xff,
+	0x3f, 0xba, 0xff, 0x4d, 0xfe, 0xe5, 0xff, 0xff,
+	0x7f, 0xef, 0xbf, 0x9f, 0xe7, 0x9f, 0x77, 0xe9,
+	0x9f, 0x1f, 0x79, 0xc1, 0xfe,
+	0xff, 0xf8, 0xf7, 0x3f, 0xff, 0x9f, 0xf7, 0xf8,
+	0xff, 0x87, 0x7f, 0xf0, 0x7f, 0x97, 0x7f, 0x89,
+	0x7e, 0xf1, 0xff, 0x9f, 0x7f,
+	0xff, 0xff, 0x37, 0xbf, 0xb3, 0x7f, 0xf2, 0xff,
+	0xff, 0xf7, 0xff, 0x7f, 0x7b, 0xfe, 0x87, 0x1f,
+	0x71, 0xf1, 0xff, 0x7f, 0xfb,
+	0xff, 0xff, 0x70, 0xb7, 0xfe, 0x7b, 0xff, 0xf3,
+	0xbf, 0xf7, 0xff, 0xff, 0xf9, 0x9f, 0x7f, 0xf1,
+	0xff, 0xf7, 0xff, 0xff, 0xfb,
+	0xbf, 0xff, 0xf4, 0xcf, 0x87, 0xd8, 0xf8, 0xf8,
+	0xff, 0xff, 0x8f, 0xff, 0xe9, 0xff, 0x8f, 0x1f,
+	0x71, 0xff, 0xef, 0xff, 0x8d,
+	0xff, 0xff, 0x87, 0xbf, 0xf9, 0x3f, 0xff, 0xf7,
+	0xff, 0xff, 0xff, 0xff, 0x9f, 0x1f, 0x71, 0xf9,
+	0xff, 0x7b, 0xff, 0xfe, 0xff,
+	0xff, 0xff, 0xcb, 0xff, 0xbd, 0x7f, 0xfb, 0xff,
+	0x8f, 0xff, 0xf8, 0x7f, 0x9f, 0x7f, 0xf1, 0xef,
+	0xff, 0xf7, 0x8f, 0x7f, 0xf9,
+	0xff, 0xf8, 0x43, 0x8f, 0xc4, 0x75, 0x7d, 0xff,
+	0xff, 0x97, 0x7f, 0x78, 0x8f, 0x6f, 0x99, 0x17,
+	0x19, 0x71, 0xf9, 0x8f, 0x6f,
+	0xbf, 0x7f, 0xf0, 0x8f, 0xf6, 0x7d, 0x37, 0xff,
+	0xff, 0xff, 0x9f, 0x7f, 0xe0, 0xff, 0xff, 0xef,
+	0xff, 0xf7, 0xfb, 0xff, 0x8f,
+	0xff, 0xff, 0xbf, 0x77, 0x8e, 0xff, 0xf0, 0xff,
+	0xff, 0xf7, 0xf7, 0x7f, 0x97, 0x7f, 0x99, 0x7f,
+	0xf9, 0xfe, 0xff, 0xfe, 0xff,
+	0x7f, 0xff, 0xff, 0xcf, 0xbf, 0xf9, 0xfa, 0xff,
+	0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x8f, 0x7f, 0x71, 0xf6,
+	0xff, 0xff, 0xff, 0x7f, 0xb7, 0xfe, 0xfb, 0xff,
+	0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
+	0xff, 0xff, 0xf7, 0xff, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x08, 0x0f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8e, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+	0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0x8f, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0xff, 0x8f,
+	0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf8, 0x8f, 0xf7, 0xf8, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf,
+	0xff, 0xf6, 0x07, 0xff, 0x78, 0xff, 0x8f, 0x7e,
+	0xf1, 0x9f, 0x7f, 0xfd, 0x8e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x77, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x6e, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8f, 0x88,
+	0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8e,
+	0x7f, 0x81, 0x7f, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0x87, 0xff,
+	0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0xfe, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x3f, 0x8f, 0xf0, 0x85, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0x7f, 0x0d, 0x0f, 0x71, 0x81,
+	0x7e, 0xf1, 0xfe, 0xff, 0xff,
+	0xff, 0x5f, 0x3d, 0xf0, 0xf5, 0xfa, 0x0f, 0xff,
+	0x00, 0xff, 0x80, 0x0f, 0xf1, 0x88, 0x7f, 0xf1,
+	0x8f, 0x7e, 0x81, 0x7e, 0xc1,
+	0xff, 0xff, 0xff, 0xff, 0xba, 0x4f, 0x75, 0xfa,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+	0x71, 0xf1, 0xff, 0xff, 0xff,
+	0x3f, 0xbf, 0xff, 0xcf, 0xff, 0xfa, 0xff, 0xfe,
+	0x7f, 0xdf, 0x7f, 0xf4, 0xff, 0x8f, 0x7f, 0xf1,
+	0x8f, 0x0f, 0x71, 0xf1, 0xbe,
+	0xff, 0xf8, 0xf7, 0xbb, 0x7f, 0x85, 0xff, 0xf0,
+	0xff, 0x8f, 0x7f, 0xf0, 0x7f, 0x87, 0x7f, 0x81,
+	0x7e, 0xf1, 0x8f, 0x0f, 0x71,
+	0xff, 0xff, 0x87, 0x8f, 0x8d, 0xfd, 0xf5, 0xff,
+	0xfb, 0xff, 0xff, 0xff, 0xf7, 0xfe, 0x8f, 0x0f,
+	0x71, 0xf1, 0xfe, 0x7f, 0xf7,
+	0xbf, 0x07, 0xc0, 0xbf, 0xf7, 0xfd, 0xff, 0xff,
+	0xbf, 0xff, 0x85, 0x8f, 0xf9, 0x8f, 0x7f, 0xf1,
+	0xff, 0x7f, 0xf6, 0xff, 0x83,
+	0xff, 0xff, 0xf4, 0xff, 0x8f, 0xda, 0xf0, 0xb6,
+	0xdf, 0xfd, 0xf6, 0xff, 0xf9, 0xff, 0x8f, 0x1f,
+	0x71, 0xfd, 0x8f, 0x7b, 0xfd,
+	0xff, 0xff, 0xb7, 0x8f, 0xf0, 0xbd, 0xff, 0xfd,
+	0xf7, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0xf1,
+	0xff, 0x7b, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xba, 0x7f, 0xf5, 0xf7,
+	0x0f, 0xf7, 0xf0, 0x7f, 0x87, 0x7f, 0xf1, 0xff,
+	0xff, 0xfe, 0x8f, 0x7f, 0xf1,
+	0xff, 0xf8, 0x47, 0x8f, 0xca, 0x70, 0x7a, 0xff,
+	0xff, 0x8f, 0x7f, 0x70, 0x8f, 0x7f, 0x81, 0x0e,
+	0x01, 0x01, 0x71, 0x81, 0x7f,
+	0xbf, 0x7f, 0xf0, 0x8f, 0xff, 0x70, 0x3f, 0xff,
+	0xfd, 0xfe, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xfe, 0xfb, 0xff, 0x8f,
+	0xff, 0xff, 0xbf, 0x7f, 0x85, 0x7f, 0xf0, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0x81, 0x7f,
+	0x81, 0xfe, 0xf1, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xcf, 0x87, 0xfa, 0x75, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x7f, 0x70, 0xfe,
+	0xff, 0x87, 0xff, 0x4b, 0xbf, 0x7f, 0xfd, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xfe, 0xff, 0xfe, 0xff,
+	0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0x8e, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0x7f, 0x8f,
+	0x8f, 0x00, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0x8f, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0x7f, 0xff,
+	0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0x7f, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0xff, 0x8f,
+	0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
+	0xff, 0xfc, 0x8f, 0xff, 0xf0, 0xff, 0x8f, 0x7e,
+	0xf1, 0x8f, 0x7f, 0xf3, 0x8e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x8f, 0x7f, 0x80, 0x7f, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x8f, 0x7f, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80,
+	0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8e,
+	0x0f, 0x01, 0x71, 0xf0, 0xff,
+	0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xef, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xf7,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0xfe, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e,
+	0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0x7f, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
+	0x8f, 0xfe, 0xf0, 0xff, 0xff,
+	0xbf, 0xff, 0x0e, 0x8f, 0x70, 0x80, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0x0f, 0x7f, 0xf1, 0x0f,
+	0x7f, 0xf1, 0xfe, 0xff, 0x9f,
+	0xbf, 0x1f, 0xfb, 0x0c, 0xff, 0xf0, 0x8f, 0xff,
+	0x00, 0xff, 0xb0, 0x3f, 0x71, 0x80, 0xff, 0xf1,
+	0x8f, 0x7f, 0x81, 0x7e, 0xc1,
+	0xff, 0xff, 0xff, 0x7f, 0x8f, 0x0f, 0x70, 0xf0,
+	0x8f, 0x7f, 0x70, 0xcf, 0x8f, 0xff, 0x71, 0x0f,
+	0x7e, 0xf1, 0x8f, 0x7f, 0xf1,
+	0x7f, 0xff, 0x7f, 0x0f, 0xff, 0x78, 0x8f, 0x8f,
+	0x70, 0x70, 0x7f, 0xfe, 0xff, 0x8f, 0xff, 0x70,
+	0xff, 0xfe, 0xff, 0xff, 0xbe,
+	0xff, 0xf8, 0xf7, 0x0b, 0xf7, 0x88, 0xf7, 0xf0,
+	0x8f, 0x8f, 0x70, 0xf0, 0x7e, 0x73, 0xff, 0x8f,
+	0x7e, 0xf0, 0xff, 0x8f, 0x7f,
+	0xff, 0x78, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
+	0xff, 0x8f, 0x77, 0x70, 0x77, 0x7f, 0xff, 0x7f,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0xff, 0x77, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+	0x77, 0x7f, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0x7f, 0xff, 0xbf,
+	0xbf, 0xff, 0x74, 0xff, 0xff, 0x8f, 0xff, 0xfc,
+	0x0f, 0xf3, 0x8c, 0xff, 0xfd, 0xff, 0xff, 0x8f,
+	0x7f, 0xf1, 0x8f, 0x7d, 0x83,
+	0xff, 0x7f, 0x77, 0xff, 0xff, 0xff, 0xff, 0xfb,
+	0xf7, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x78, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+	0x0f, 0x8f, 0x70, 0x70, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xf8, 0xf7, 0x7f, 0xff, 0x8f, 0x8f, 0x80,
+	0x80, 0x81, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x6f, 0x8f, 0x0f, 0x71,
+	0xbf, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7b, 0xff, 0x9f, 0xff, 0x70, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xfe, 0x8f,
+	0xff, 0x87, 0x7f, 0x78, 0xfe, 0xff, 0x9e, 0xff,
+	0xf2, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xff, 0xef,
+	0xff, 0x7f, 0xff, 0xff, 0xff,
+	0x7f, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xfe, 0x8f,
+	0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0x7f, 0xf7, 0xff, 0xfe, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xaf, 0x0f,
+	0x70, 0xd1, 0xff, 0xf8, 0xfe,
+	0xff, 0xff, 0xff, 0xf7, 0xaf, 0x8f, 0xfa, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0x8f, 0x0f,
+	0x79, 0xe1, 0xff, 0xfe, 0xff,
+	0xbf, 0xff, 0xff, 0x7a, 0x8f, 0xff, 0xf0, 0xef,
+	0xff, 0xfb, 0xff, 0xaf, 0xff, 0xfb, 0x8f, 0x7f,
+	0xf1, 0xdf, 0xff, 0xf9, 0xff,
+	0xbf, 0xff, 0xff, 0xf7, 0xff, 0xaf, 0xff, 0xba,
+	0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xef, 0xdf,
+	0xff, 0xfd, 0xbe, 0xf7, 0xf5,
+	0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff,
+	0xff, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0x8f, 0x3f,
+	0x11, 0xeb, 0xdb, 0xcf, 0x7f,
+	0xbf, 0xf0, 0x8f, 0x87, 0xf0, 0xf0, 0xff, 0xbf,
+	0xff, 0x8f, 0xff, 0xf1, 0x8f, 0x0f, 0x31, 0xf1,
+	0x9f, 0xdf, 0xf9, 0x85, 0x7f,
+	0xbf, 0xff, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff,
+	0xee, 0xff, 0xfb, 0xf7, 0x8f, 0x7f, 0xb1, 0xff,
+	0xff, 0xff, 0xff, 0xdf, 0xfd,
+	0xff, 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0x80, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x2f, 0x71,
+	0xc1, 0x7f, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xbf,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xd1,
+	0x9f, 0xff, 0x7b, 0xb7, 0xff,
+	0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xbf, 0xb7, 0xff,
+	0xff, 0xa4, 0xf7, 0x88, 0xff, 0xf0, 0xaf, 0xbf,
+	0xfb, 0xef, 0xff, 0xf7, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xdd, 0xf7, 0x97, 0x7f,
+	0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xf0, 0xff,
+	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xaf, 0x0f, 0xa0, 0xf0,
+	0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+	0x71, 0xb1, 0x37, 0xf7, 0xff,
+	0xff, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xfe, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xbf, 0xff, 0xf8, 0xf7, 0xff, 0xa7, 0xff, 0xf0,
+	0xff, 0xff, 0x8f, 0xfe, 0xf0, 0xff, 0xff, 0x8f,
+	0x7f, 0xf1, 0xff, 0xff, 0xcf,
+	0xff, 0xff, 0xf7, 0x9f, 0xf7, 0xf3, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xbf, 0x7f, 0xf9,
+	0xff, 0xfe, 0xff, 0xff, 0xdf,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
+	0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xbf, 0xbf,
+	0xff, 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xff,
+	0x9f, 0xfe, 0xf1, 0xff, 0xff, 0xcf, 0x7f, 0xf1,
+	0xff, 0xff, 0xdf, 0xff, 0xf1,
+	0xbf, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xbf, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x6f,
+	0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0xf8, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xcf, 0xff,
+	0xff, 0xd8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x3f,
+	0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff,
+	0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f,
+	0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0xbf, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff,
+	0xdf, 0xff, 0x7f, 0xff, 0xbf,
+	0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1,
+	0xff, 0xef, 0xff, 0x7f, 0xff,
diff --git a/u-boot/board/sixnet/sixnet.c b/u-boot/board/sixnet/sixnet.c
new file mode 100644
index 0000000..edb5d13
--- /dev/null
+++ b/u-boot/board/sixnet/sixnet.c
@@ -0,0 +1,592 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Dave Ellis, SIXNET, dge@sixnetio.com.
+ *  Based on code by:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * and other contributors to U-Boot. See file CREDITS for list
+ * of people who contributed to this  project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <jffs2/jffs2.h>
+#include <mpc8xx.h>
+#include <net.h>	/* for eth_init() */
+#include <rtc.h>
+#include "sixnet.h"
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+static long ram_size(ulong *, long);
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress (int status)
+{
+#if defined(CONFIG_STATUS_LED)
+# if defined(STATUS_LED_BOOT)
+	if (status == 15) {
+		/* ready to transfer to kernel, make sure LED is proper state */
+		status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
+	}
+# endif /* STATUS_LED_BOOT */
+#endif /* CONFIG_STATUS_LED */
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ * returns 0 if recognized, -1 if unknown
+ */
+
+int checkboard (void)
+{
+	puts ("Board: SIXNET SXNI855T\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_CMD_PCMCIA)
+#error "SXNI855T has no PCMCIA port"
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_ 0xffffffff
+
+/* UPMB table for dual UART. */
+
+/* this table is for 50MHz operation, it should work at all lower speeds */
+const uint duart_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
+	0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
+
+	/* burst read. (offset 8 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
+	0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
+
+	/* burst write. (offset 20 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+};
+
+/* Load FPGA very early in boot sequence, since it must be
+ * loaded before the 16C2550 serial channels can be used as
+ * console channels.
+ *
+ * Note: Much of the configuration is not complete. The
+ *       stack is in DPRAM since SDRAM has not been initialized,
+ *       so the stack must be kept small. Global variables
+ *       are still in FLASH, so they cannot be written.
+ *	 Only the FLASH, DPRAM, immap and FPGA can be addressed,
+ *       the other chip selects may not have been initialized.
+ *       The clocks have been initialized, so udelay() can be
+ *       used.
+ */
+#define FPGA_DONE	0x0080	/* PA8, input, high when FPGA load complete */
+#define FPGA_PROGRAM_L	0x0040	/* PA9, output, low to reset, high to start */
+#define FPGA_INIT_L	0x0020	/* PA10, input, low indicates not ready	*/
+#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG))	/* FPGA port */
+
+int board_postclk_init (void)
+{
+
+	/* the data to load to the XCSxxXL FPGA */
+	static const unsigned char fpgadata[] = {
+# include "fpgadata.c"
+	};
+
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+#define porta (immap->im_ioport.iop_padat)
+	const unsigned char* pdata;
+
+	/* /INITFPGA and DONEFPGA signals are inputs */
+	immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
+
+	/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
+	porta &= ~FPGA_PROGRAM_L;
+
+	/* Set FPGA as an output */
+	immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
+
+	/* delay a little to make sure FPGA sees it, really
+	 * only need less than a microsecond.
+	 */
+	udelay(10);
+
+	/* unassert /PROGRAM */
+	porta |= FPGA_PROGRAM_L;
+
+	/* delay while FPGA does last erase, indicated by
+	 * /INITFPGA going high. This should happen within a
+	 * few milliseconds.
+	 */
+	/* ### FIXME - a timeout check would be good, maybe flash
+	 * the status LED to indicate the error?
+	 */
+	while ((porta & FPGA_INIT_L) == 0)
+		; /* waiting */
+
+	/* write program data to FPGA at the programming address
+	 * so extra /CS1 strobes at end of configuration don't actually
+	 * write to any registers.
+	 */
+	fpga = 0xff;		/* first write is ignored	*/
+	fpga = 0xff;		/* fill byte			*/
+	fpga = 0xff;		/* fill byte			*/
+	fpga = 0x4f;		/* preamble code		*/
+	fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
+	fpga = 0x4b;		/* field check code */
+
+	pdata = fpgadata;
+	/* while no error write out each of the 28 byte frames */
+	while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
+	       && pdata < fpgadata + sizeof(fpgadata)) {
+
+		fpga = 0x4f;	/* preamble code */
+
+		/* 21 bytes of data in a frame */
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++);
+
+		fpga = 0x4b;	/* field check code		*/
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0x4b;	/* extended write cycle
+				 * (actually 0x4b from bitgen.exe)
+				 */
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0xff;	/* extended write cycle		*/
+	}
+
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+
+#if 0 /* ### FIXME */
+	/* If didn't load all the data or FPGA_DONE is low the load failed.
+	 * Maybe someday stop here and flash the status LED? The console
+	 * is not configured, so can't print an error message. Can't write
+	 * global variables to set a flag (except gd?).
+	 * For now it must work.
+	 */
+#endif
+
+	/* Now that the FPGA is loaded, set up the Dual UART chip
+	 * selects. Must be done here since it may be used as the console.
+	 */
+	upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
+
+	memctl->memc_mbmr = DUART_MBMR;
+	memctl->memc_or5 = DUART_OR_VALUE;
+	memctl->memc_br5 = DUART_BR5_VALUE;
+	memctl->memc_or6 = DUART_OR_VALUE;
+	memctl->memc_br6 = DUART_BR6_VALUE;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* base address for SRAM, assume 32-bit port,  valid */
+#define NVRAM_BR_VALUE   (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
+
+/*  up to 64MB - will be adjusted for actual size */
+#define NVRAM_OR_PRELIM  (ORMASK(CONFIG_SYS_SRAM_SIZE) \
+	| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
+/*
+ * Miscellaneous platform dependent initializations after running in RAM.
+ */
+
+int misc_init_r (void)
+{
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	bd_t *bd = gd->bd;
+	uchar enetaddr[6];
+
+	memctl->memc_or2 = NVRAM_OR_PRELIM;
+	memctl->memc_br2 = NVRAM_BR_VALUE;
+
+	/* Is there any SRAM? Is it 16 or 32 bits wide? */
+
+	/* First look for 32-bit SRAM */
+	bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
+
+	if (bd->bi_sramsize == 0) {
+	    /* no 32-bit SRAM, but there could be 16-bit SRAM since
+	     * it would report size 0 when configured for 32-bit bus.
+	     * Try again with a 16-bit bus.
+	     */
+	    memctl->memc_br2 |= BR_PS_16;
+	    bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
+	}
+
+	if (bd->bi_sramsize == 0) {
+	    memctl->memc_br2 = 0;	/* disable select since nothing there */
+	}
+	else {
+	    /* adjust or2 for actual size of SRAM */
+	    memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
+	    bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
+	    printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
+	}
+
+
+	/* set standard MPC8xx clock so kernel will see the time
+	 * even if it doesn't have a DS1306 clock driver.
+	 * This helps with experimenting with standard kernels.
+	 */
+	{
+	    ulong tim;
+	    struct rtc_time tmp;
+
+	    rtc_get(&tmp);	/* get time from DS1306 RTC */
+
+	    /* convert to seconds since 1970 */
+	    tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+			 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+	    immap->im_sitk.sitk_rtck = KAPWR_KEY;
+	    immap->im_sit.sit_rtc = tim;
+	}
+
+	/* set up ethernet address for SCC ethernet. If eth1addr
+	 * is present it gets a unique address, otherwise it
+	 * shares the FEC address.
+	 */
+	if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+		eth_getenv_enetaddr("ethaddr", enetaddr);
+		eth_setenv_enetaddr("eth1addr", enetaddr);
+	}
+
+	return (0);
+}
+
+#if defined(CONFIG_CMD_NAND)
+void nand_init(void)
+{
+	unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'.
+ *
+ * The memory size MUST be a power of 2 for this to work.
+ *
+ * The only memory modified is 8 bytes at offset 0. This is important
+ * since for the SRAM this location is reserved for autosizing, so if
+ * it is modified and the board is reset before ram_size() completes
+ * no damage is  done. Normally even the memory at 0 is preserved. The
+ * higher SRAM addresses may contain battery backed RAM disk data which
+ * must never be corrupted.
+ */
+
+static long ram_size(ulong *base, long maxsize)
+{
+    volatile long	*test_addr;
+    volatile ulong	*base_addr = base;
+    ulong		ofs;		/* byte offset from base_addr */
+    ulong		save;		/* to make test non-destructive */
+    ulong		save2;		/* to make test non-destructive */
+    long		ramsize = -1;	/* size not determined yet */
+
+    save = *base_addr;		/* save value at 0 so can restore */
+    save2 = *(base_addr+1);	/* save value at 4 so can restore */
+
+    /* is any SRAM present? */
+    *base_addr = 0x5555aaaa;
+
+    /* It is important to drive the data bus with different data so
+     * it doesn't remember the value and look like RAM that isn't there.
+     */
+    *(base_addr + 1) = 0xaaaa5555;	/* use write to modify data bus */
+
+    if (*base_addr != 0x5555aaaa)
+	ramsize = 0;		/* no RAM present, or defective */
+    else {
+	*base_addr = 0xaaaa5555;
+	*(base_addr + 1) = 0x5555aaaa;	/* use write to modify data bus */
+	if (*base_addr != 0xaaaa5555)
+	    ramsize = 0;	/* no RAM present, or defective */
+    }
+
+    /* now size it if any is present */
+    for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
+	test_addr = (long*)((long)base_addr + ofs);	/* location to test */
+
+	*base_addr = ~*test_addr;
+	if (*base_addr == *test_addr)
+	    ramsize = ofs;	/* wrapped back to 0, so this is the size */
+    }
+
+    *base_addr = save;		/* restore value at 0 */
+    *(base_addr+1) = save2;	/* restore value at 4 */
+    return (ramsize);
+}
+
+/* ------------------------------------------------------------------------- */
+/* sdram table based on the FADS manual                                      */
+/* for chip MB811171622A-100                                                 */
+
+/* this table is for 50MHz operation, it should work at all lower speeds */
+
+const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* precharge and Mode Register Set initialization (offset 5).
+	 * This is also entered at offset 6 to do Mode Register Set
+	 * without the precharge.
+	 */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	/* FADS had 0x1f27fc04, ...
+	 * but most other boards have 0x1f07fc04, which
+	 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
+	 * like the single read.
+	 * This seems better so I am going with the change.
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+
+#define	SDRAM_MAX_SIZE		0x10000000	/* max 256 MB SDRAM */
+
+/* precharge and set Mode Register */
+#define SDRAM_MCR_PRE    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(1) | MCR_MAD(5))	/* 1 time at 0x05 */
+
+/* set Mode Register, no precharge */
+#define SDRAM_MCR_MRS    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(1) | MCR_MAD(6))	/* 1 time at 0x06 */
+
+/* runs refresh loop twice so get 8 refresh cycles */
+#define SDRAM_MCR_REFR   (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(2) | MCR_MAD(0x30))	/* twice at 0x30  */
+
+/* MAMR values work in either mamr or mbmr */
+#define SDRAM_MAMR_BASE  /* refresh at 50MHz */				  \
+			 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE		  \
+			 | MAMR_DSA_1_CYCL	/* 1 cycle disable */	  \
+			 | MAMR_RLFA_1X		/* Read loop 1 time */	  \
+			 | MAMR_WLFA_1X		/* Write loop 1 time */	  \
+			 | MAMR_TLFA_4X)	/* Timer loop 4 times */
+/* 8 column SDRAM */
+#define SDRAM_MAMR_8COL	(SDRAM_MAMR_BASE				  \
+			 | MAMR_AMA_TYPE_0	/* Address MUX 0 */	  \
+			 | MAMR_G0CLA_A11)	/* GPL0 A11[MPC] */
+
+/* 9 column SDRAM */
+#define SDRAM_MAMR_9COL	(SDRAM_MAMR_BASE				  \
+			 | MAMR_AMA_TYPE_1	/* Address MUX 1 */	  \
+			 | MAMR_G0CLA_A10)	/* GPL0 A10[MPC] */
+
+/* base address 0, 32-bit port, SDRAM UPM, valid */
+#define SDRAM_BR_VALUE   (BR_PS_32 | BR_MS_UPMA | BR_V)
+
+/*  up to 256MB, SAM, G5LS - will be adjusted for actual size */
+#define SDRAM_OR_PRELIM  (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
+
+/* This is the Mode Select Register value for the SDRAM.
+ * Burst length: 4
+ * Burst Type: sequential
+ * CAS Latency: 2
+ * Write Burst Length: burst
+ */
+#define SDRAM_MODE   0x22	/* CAS latency 2, burst length 4 */
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	uint size_sdram = 0;
+	uint size_sdram9 = 0;
+	uint base = 0;		/* SDRAM must start at 0 */
+	int i;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Configure the refresh (mostly).  This needs to be
+	 * based upon processor clock speed and optimized to provide
+	 * the highest level of performance.
+	 *
+	 * Preliminary prescaler for refresh.
+	 * This value is selected for four cycles in 31.2 us,
+	 * which gives 8192 cycles in 64 milliseconds.
+	 * This may be too fast, but works for any memory.
+	 * It is adjusted to 4096 cycles in 64 milliseconds if
+	 * possible once we know what memory we have.
+	 *
+	 * We have to be careful changing UPM registers after we
+	 * ask it to run these commands.
+	 *
+	 * PTA - periodic timer period for our design is
+	 *       50 MHz x 31.2us
+	 *       ---------------  = 195
+	 *       1 x 8 x 1
+	 *
+	 *    50MHz clock
+	 *    31.2us refresh interval
+	 *    SCCR[DFBRG] 0
+	 *    PTP divide by 8
+	 *    1 chip select
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;	/* 0x0800 */
+	memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
+
+	/* The SDRAM Mode Register value is shifted left 2 bits since
+	 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
+	 */
+	memctl->memc_mar = SDRAM_MODE << 2;	/* MRS code */
+	udelay(200);		/* SDRAM needs 200uS before set it up */
+
+	/* Now run the precharge/nop/mrs commands. */
+	memctl->memc_mcr = SDRAM_MCR_PRE;
+	udelay(2);
+
+	/* Run 8 refresh cycles (2 sets of 4) */
+	memctl->memc_mcr = SDRAM_MCR_REFR;	/* run refresh twice */
+	udelay(2);
+
+	/* some brands want Mode Register set after the refresh
+	 * cycles. This shouldn't hurt anything for the brands
+	 * that were happy with the first time we set it.
+	 */
+	memctl->memc_mcr = SDRAM_MCR_MRS;
+	udelay(2);
+
+	memctl->memc_mamr = SDRAM_MAMR_8COL;	/* enable refresh */
+	memctl->memc_or3 = SDRAM_OR_PRELIM;
+	memctl->memc_br3 = SDRAM_BR_VALUE + base;
+
+	/* Some brands need at least 10 DRAM accesses to stabilize.
+	 * It wont hurt the brands that don't.
+	 */
+	for (i=0; i<10; ++i) {
+		volatile ulong *addr = (volatile ulong *)base;
+		ulong val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/* Check SDRAM memory Size in 8 column mode.
+	 * For a 9 column memory we will get half the actual size.
+	 */
+	size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
+
+	/* Check SDRAM memory Size in 9 column mode.
+	 * For an 8 column memory we will see at most 4 megabytes.
+	 */
+	memctl->memc_mamr = SDRAM_MAMR_9COL;
+	size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
+
+	if (size_sdram < size_sdram9)	/* leave configuration at 9 columns */
+		size_sdram = size_sdram9;
+	else				/* go back to 8 columns */
+		memctl->memc_mamr = SDRAM_MAMR_8COL;
+
+	/* adjust or3 for actual size of SDRAM
+	 */
+	memctl->memc_or3 |= ORMASK(size_sdram);
+
+	/* Adjust refresh rate depending on SDRAM type.
+	 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
+	 * it at the current (fast) rate.
+	 * For 16, 64 and 128 MBit half the rate will do.
+	 */
+	if (size_sdram <= 32 * 1024 * 1024)
+		memctl->memc_mptpr = MPTPR_PTP_DIV16;	/* 0x0400 */
+
+	return (size_sdram);
+}
diff --git a/u-boot/board/sixnet/sixnet.h b/u-boot/board/sixnet/sixnet.h
new file mode 100644
index 0000000..e631874
--- /dev/null
+++ b/u-boot/board/sixnet/sixnet.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Memory map:
+ *
+ *   ff100000 -> ff13ffff : FPGA        CS1
+ *   ff030000 -> ff03ffff : EXPANSION   CS7
+ *   ff020000 -> ff02ffff : DATA FLASH  CS4
+ *   ff018000 -> ff01ffff : UART B      CS6/UPMB
+ *   ff010000 -> ff017fff : UART A      CS5/UPMB
+ *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
+ *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
+ *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
+ *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
+ */
diff --git a/u-boot/board/sixnet/u-boot.lds b/u-boot/board/sixnet/u-boot.lds
new file mode 100644
index 0000000..b4c7a0e
--- /dev/null
+++ b/u-boot/board/sixnet/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/snmc/qs850/Makefile b/u-boot/board/snmc/qs850/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/snmc/qs850/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/snmc/qs850/flash.c b/u-boot/board/snmc/qs850/flash.c
new file mode 100644
index 0000000..b592285
--- /dev/null
+++ b/u-boot/board/snmc/qs850/flash.c
@@ -0,0 +1,616 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+#define FLASH_WORD_SIZE unsigned long
+#define FLASH_ID_MASK 0xFFFFFFFF
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+	volatile FLASH_WORD_SIZE* flash_base;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here */
+	/* Test for 8M Flash first */
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_8M_PRELIM);
+	flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_8M_PRELIM);
+	size_b0 = flash_get_size(flash_base, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		size_b0, size_b0<<20);
+		return 0;
+	}
+
+	if (size_b0 < 8*1024*1024) {
+		/* Not quite 8M, try 4M Flash base address */
+		debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_4M_PRELIM);
+		flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_4M_PRELIM);
+		size_b0 = flash_get_size(flash_base, &flash_info[0]);
+	}
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		size_b0, size_b0<<20);
+		return 0;
+	}
+
+	/* Only one bank */
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets ((ulong)flash_base, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]);
+		size_b1 = 0 ;
+		flash_info[0].size = size_b0;
+		return(size_b0);
+	}
+
+	/* We have 2 banks */
+	size_b1 = flash_get_size(flash_base, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+	if (size_b1) {
+		mtdcr(EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr(EBC0_CFGDATA);
+		mtdcr(EBC0_CFGADDR, PB0CR);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+		mtdcr(EBC0_CFGDATA, pbcr);
+	}
+
+	if (size_b0) {
+		mtdcr(EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr(EBC0_CFGDATA);
+		mtdcr(EBC0_CFGADDR, PB1CR);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+		mtdcr(EBC0_CFGDATA, pbcr);
+	}
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+		CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CONFIG_SYS_MONITOR_LEN,
+			base_b1+size_b1-1, &flash_info[1]);
+
+		/* monitor protection OFF by default (one is enough) */
+		(void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CONFIG_SYS_MONITOR_LEN,
+			base_b0+size_b0-1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823.
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	long large_sect_size;
+	long small_sect_size;
+
+	/* set up sector start adress table */
+	large_sect_size = info->size / (info->sector_count - 8 + 1);
+	small_sect_size = large_sect_size / 8;
+
+	if (info->flash_id & FLASH_BTYPE) {
+
+		/* set sector offsets for bottom boot block type */
+		for (i = 0; i < 7; i++) {
+			info->start[i] = base;
+			base += small_sect_size;
+		}
+
+		for (; i < info->sector_count; i++) {
+			info->start[i] = base;
+			base += large_sect_size;
+		}
+	}
+	else
+	{
+		/* set sector offsets for top boot block type */
+		for (i = 0; i < (info->sector_count - 8); i++) {
+			info->start[i] = base;
+			base += large_sect_size;
+		}
+
+		for (; i < info->sector_count; i++) {
+			info->start[i] = base;
+			base += small_sect_size;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[]=", bottom boot sect)\n";
+	uchar topboot[]=", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf ("AMD ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf ("FUJITSU ");
+			break;
+		case FLASH_MAN_SST:
+			printf ("SST ");
+			break;
+		case FLASH_MAN_STM:
+			printf ("STM ");
+			break;
+		case FLASH_MAN_INTEL:
+			printf ("INTEL ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+	}
+
+	if (info->flash_id & 0x0001 ) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM160B:
+			printf ("AM29LV160B (16 Mbit%s",boottype);
+			break;
+		case FLASH_AM160T:
+			printf ("AM29LV160T (16 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL163T:
+			printf ("AM29DL163T (16 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL163B:
+			printf ("AM29DL163B (16 Mbit%s",boottype);
+			break;
+		case FLASH_AM320B:
+			printf ("AM29LV320B (32 Mbit%s",boottype);
+			break;
+		case FLASH_AM320T:
+			printf ("AM29LV320T (32 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL323T:
+			printf ("AM29DL323T (32 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL323B:
+			printf ("AM29DL323B (32 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL322T:
+			printf ("AM29DL322T (32 Mbit%s",boottype);
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+	info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if(addr[0x0000] != 0x00890089){
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+	}
+	value = addr[0];
+
+	switch (value) {
+		case (AMD_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (FUJ_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		case (STM_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_STM;
+			break;
+		case (SST_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_SST;
+			break;
+		case (INTEL_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_INTEL;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0); /* no or unknown flash */
+	}
+
+	value = addr[1]; /* device ID */
+
+	switch (value) {
+		case (AMD_ID_LV160T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_LV160B & FLASH_ID_MASK):
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_DL163T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL163T;
+			info->sector_count = 39;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_DL163B & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL163B;
+			info->sector_count = 39;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_DL323T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x00800000;
+			break; /* => 8 MB */
+
+		case (AMD_ID_DL323B & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x00800000;
+			break; /* => 8 MB */
+
+		case (AMD_ID_DL322T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x00800000;
+			break; /* => 8 MB */
+
+		default:
+			/* FIXME*/
+			info->flash_id = FLASH_UNKNOWN;
+			return (0); /* => no or unknown flash */
+	}
+
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+		*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+		(info->flash_id > FLASH_AMD_COMP) ) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+			addr[0] = (0x00300030 & FLASH_ID_MASK);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
+	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
+			(0x00800080&FLASH_ID_MASK)  )
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) { /* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3); /* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* AMD stuff */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+	return (0);
+}
diff --git a/u-boot/board/snmc/qs850/qs850.c b/u-boot/board/snmc/qs850/qs850.c
new file mode 100644
index 0000000..43f7495
--- /dev/null
+++ b/u-boot/board/snmc/qs850/qs850.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation, dnevil@snmc.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long  int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0f07cc04,  0x00adcc04,  0x00a74c00,  0x00bfcc04,
+	0x1fffcc05,  0xffffcc05,  0xffffcc05,  0xffffcc05,
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0ff7fc04,  0x0ffffc04,  0x00bdfc04,  0x00fffc00,
+	0x00fffc00,  0x00fffc00,  0x0ff77c00,  0x1ffffc05,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0f07cc04,  0x0fafcc00,  0x01ad0c04,  0x1ff74c07,
+	0xffffcc05,  0xffffcc05,  0xffffcc05,  0xffffcc05,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0ff7fc04,  0x0ffffc00,  0x00bd7c00,  0x00fffc00,
+	0x00fffc00,  0x00fffc00,  0x0ffffc04,  0x0ff77c04,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0xffffcc04,  0x1ff5cc84,  0xffffcc04,  0xffffcc04,
+	0xffffcc84,  0xffffcc05,  0xffffcc04,  0xffffcc04,
+	0xffffcc04,  0xffffcc04,  0xffffcc04,  0xffffcc04,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x1ff74c04,  0xffffcc07,  0xffffaa34,  0x1fb54a37
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (QS850, QS823, ...)
+ *
+ * Always return 1
+ */
+#if defined(CONFIG_QS850)
+#define BOARD_IDENTITY	"QS850"
+#elif defined(CONFIG_QS823)
+#define BOARD_IDENTITY	"QS823"
+#else
+#define	BOARD_IDENTITY	"QS???"
+#endif
+
+int checkboard (void)
+{
+	char *s, *e;
+	char buf[64];
+	int i;
+
+	i = getenv_f("serial#", buf, sizeof(buf));
+	s = (i>0) ? buf : NULL;
+
+	if (!s || strncmp(s, BOARD_IDENTITY, 5)) {
+		puts ("### No HW ID - assuming " BOARD_IDENTITY);
+	} else {
+		for (e=s; *e; ++e) {
+		if (*e == ' ')
+		break;
+	}
+
+	for ( ; s<e; ++s) {
+		putc (*s);
+		}
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+/* SDRAM Mode Register Definitions */
+
+/* Set SDRAM Burst Length to 4 (010) */
+/* See Motorola MPC850 User Manual, Page 13-14 */
+#define SDRAM_BURST_LENGTH      (2)
+
+/* Set Wrap Type to Sequential (0) */
+/* See Motorola MPC850 User Manual, Page 13-14 */
+#define SDRAM_WRAP_TYPE         (0 << 3)
+
+/* Set /CAS Latentcy to 2 clocks */
+#define SDRAM_CAS_LATENTCY      (2 << 4)
+
+/* The Mode Register value must be shifted left by 2, since it is */
+/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
+#define SDRAM_MODE_REG  ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
+
+#define UPMA_RUN(loops,index)   (0x80002000 + (loops<<8) + index)
+
+/* Please note a value of zero = 16 loops */
+#define REFRESH_INIT_LOOPS (0)
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/*
+	* Prescaler for refresh
+	*/
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/*
+	* Map controller bank 1 to the SDRAM address
+	*/
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
+	udelay(1000);
+
+	/* perform SDRAM initialization sequence */
+	memctl->memc_mamr = CONFIG_SYS_16M_MAMR;
+	udelay(100);
+
+	/* Program the SDRAM's Mode Register */
+	memctl->memc_mar  = SDRAM_MODE_REG;
+
+	/* Run the Prechard Pattern at 0x3C */
+	memctl->memc_mcr  = UPMA_RUN(1,0x3c);
+	udelay(1);
+
+	/* Run the Refresh program residing at MAD index 0x30 */
+	/* This contains the CBR Refresh command with a loop */
+	/* The SDRAM must be refreshed at least 2 times */
+	/* Please note a value of zero = 16 loops */
+	memctl->memc_mcr  = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
+	udelay(1);
+
+	/* Run the Exception program residing at MAD index 0x3E */
+	/* This contains the Write Mode Register command */
+	/* The Write Mode Register command uses the value written to MAR */
+	memctl->memc_mcr  = UPMA_RUN(1,0x3e);
+
+	udelay (1000);
+
+	/*
+	* Check for 32M SDRAM Memory Size
+	*/
+	size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE,
+	(long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
+	udelay (1000);
+
+	/*
+	* Check for 16M SDRAM Memory Size
+	*/
+	if (size != SDRAM_32M_MAX_SIZE) {
+	size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE,
+	(long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+	udelay (1000);
+	}
+
+	udelay(10000);
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/u-boot/board/snmc/qs850/u-boot.lds b/u-boot/board/snmc/qs850/u-boot.lds
new file mode 100644
index 0000000..f8c50cb
--- /dev/null
+++ b/u-boot/board/snmc/qs850/u-boot.lds
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/snmc/qs860t/Makefile b/u-boot/board/snmc/qs860t/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/snmc/qs860t/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/snmc/qs860t/flash.c b/u-boot/board/snmc/qs860t/flash.c
new file mode 100644
index 0000000..e725115
--- /dev/null
+++ b/u-boot/board/snmc/qs860t/flash.c
@@ -0,0 +1,1115 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+#ifdef CONFIG_SYS_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Only one bank */
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+#if 0	/* sand: */
+		(void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0,
+			FLASH_BASE1_PRELIM-1+size_b0,
+			&flash_info[0]);
+#else
+		(void)flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
+			&flash_info[0]);
+#endif
+		size_b1 = 0 ;
+		flash_info[0].size = size_b0;
+	} else {	/* 2 banks */
+		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+		if (size_b1) {
+			mtdcr(EBC0_CFGADDR, PB0CR);
+			pbcr = mfdcr(EBC0_CFGDATA);
+			mtdcr(EBC0_CFGADDR, PB0CR);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+			mtdcr(EBC0_CFGDATA, pbcr);
+		}
+
+		if (size_b0) {
+			mtdcr(EBC0_CFGADDR, PB1CR);
+			pbcr = mfdcr(EBC0_CFGDATA);
+			mtdcr(EBC0_CFGADDR, PB1CR);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+			mtdcr(EBC0_CFGDATA, pbcr);
+		}
+
+		size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
+
+		flash_get_offsets (base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+#if 0	/* sand: */
+		(void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0,
+			FLASH_BASE1_PRELIM-1+size_b0,
+			&flash_info[0]);
+#else
+		(void)flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
+			&flash_info[0]);
+#endif
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
+
+			flash_get_offsets (base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void)flash_protect(FLAG_PROTECT_SET,
+				base_b1+size_b1-CONFIG_SYS_MONITOR_LEN,
+				base_b1+size_b1-1,
+				&flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+				base_b0+size_b0-CONFIG_SYS_MONITOR_LEN,
+				base_b0+size_b0-1,
+				&flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if ((info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A ||
+		(info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A ||
+		(info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * info->size/info->sector_count);
+		}
+	}
+	else if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		} else {
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[]=", bottom boot sect)\n";
+	uchar topboot[]=", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	if (info->flash_id & 0x0001 ) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800B:	printf ("INTEL28F800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800T:	printf ("INTEL28F800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160B:	printf ("INTEL28F160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160T:	printf ("INTEL28F160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320B:	printf ("INTEL28F320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320T:	printf ("INTEL28F320T (32 Mbit%s",boottype);
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 Mbit%s",boottype);
+				break;
+
+#if 0 /* enable when devices are available */
+
+	case FLASH_INTEL640B:	printf ("INTEL28F640B (64 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL640T:	printf ("INTEL28F640T (64 Mbit%s",boottype);
+				break;
+#endif
+	case INTEL_ID_28F320J3A:	printf ("INTEL28F320JA3 (32 Mbit%s",boottype);
+				break;
+	case INTEL_ID_28F640J3A:	printf ("INTEL28F640JA3 (64 Mbit%s",boottype);
+				break;
+	case INTEL_ID_28F128J3A:	printf ("INTEL28F128JA3 (128 Mbit%s",boottype);
+				break;
+
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if(addr[0x0000] != 0x00890089){
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if(addr[0x0000] != 0x0089){
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0); /* no or unknown flash */
+
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	case (AMD_ID_DL322T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+#if 0 /* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+#endif
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 32 MBit	*/
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 64 MBit	*/
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 128 MBit	*/
+
+	default:
+		/* FIXME*/
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+		if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
+#ifndef CONFIG_SYS_FLASH_16BIT
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+#else
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+#endif
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
+
+
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
+#ifndef CONFIG_SYS_FLASH_16BIT
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
+				}
+#else
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
+#endif
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n",
+						(unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
+		}
+
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+
+/*int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+		ulong b_end = info->start[0] + info->size;*/	/* bank end addr */
+/*		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+*/	/* finally write data to flash */
+/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#ifndef CONFIG_SYS_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i=0; i<2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_short(info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CONFIG_SYS_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	if(info->flash_id > FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if(info->flash_id > FLASH_AMD_COMP) {
+		while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	} else {
+		while(!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+
+		if( addr[0] & 0x003A003A) {	/* check for error */
+			barf = addr[0] & 0x003A0000;
+			if( barf ) {
+				barf >>=16;
+			} else {
+				barf = addr[0] & 0x0000003A;
+			}
+			printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+			if(barf & 0x0002) printf("Block locked, not erased.\n");
+			if(barf & 0x0010) printf("Programming error.\n");
+			if(barf & 0x0008) printf("Vpp Low error.\n");
+			return(2);
+		}
+	}
+
+	return (0);
+}
+
+#else
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	if(info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if(info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+		/* intel stuff */
+		while(!(addr[0] & 0x0080)){	/* wait for error or finish */
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1);
+		}
+
+		if( addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+			if(barf & 0x0002) printf("Block locked, not erased.\n");
+			if(barf & 0x0010) printf("Programming error.\n");
+			if(barf & 0x0008) printf("Vpp Low error.\n");
+			return(2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while(!(addr[0] & 0x0080)){	/* wait for error or finish */
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1);
+		}
+		*addr = 0x00FF;
+	}
+	return (0);
+}
+
+#endif
+
+/*-----------------------------------------------------------------------*/
diff --git a/u-boot/board/snmc/qs860t/qs860t.c b/u-boot/board/snmc/qs860t/qs860t.c
new file mode 100644
index 0000000..fa88707
--- /dev/null
+++ b/u-boot/board/snmc/qs860t/qs860t.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation, dnevil@snmc.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long  int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (QS860T...)
+ *
+ * Always return 1
+ */
+
+int checkboard (void)
+{
+	char *s, *e;
+	char buf[64];
+	int i;
+
+	i = getenv_f("serial#", buf, sizeof(buf));
+	s = (i>0) ? buf : NULL;
+
+	if (!s || strncmp(s, "QS860T", 6)) {
+		puts ("### No HW ID - assuming QS860T");
+	} else {
+		for (e=s; *e; ++e) {
+			if (*e == ' ')
+			break;
+		}
+
+		for ( ; s<e; ++s) {
+			putc (*s);
+		}
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/*
+	* Prescaler for refresh
+	*/
+	memctl->memc_mptpr = 0x0400;
+
+	/*
+	* Map controller bank 2 to the SDRAM address
+	*/
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
+	udelay(200);
+
+	/* perform SDRAM initialization sequence */
+	memctl->memc_mbmr = CONFIG_SYS_16M_MBMR;
+	udelay(100);
+
+	memctl->memc_mar  = 0x00000088;
+	memctl->memc_mcr  = 0x80804105;	/* run precharge pattern */
+	udelay(1);
+
+	/* Run two refresh cycles on SDRAM */
+	memctl->memc_mbmr = 0x18802118;
+	memctl->memc_mcr  = 0x80804130;
+	memctl->memc_mbmr = 0x18802114;
+	memctl->memc_mcr  = 0x80804106;
+
+	udelay (1000);
+
+#if 0
+	/*
+	* Check for 64M SDRAM Memory Size
+	*/
+	size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
+	udelay (1000);
+
+	/*
+	* Check for 16M SDRAM Memory Size
+	*/
+	if (size != SDRAM_64M_MAX_SIZE) {
+#endif
+	size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+	udelay (1000);
+#if 0
+	}
+
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+#endif
+
+
+	udelay(10000);
+
+
+#if 0
+
+	/*
+	* Also, map other memory to correct position
+	*/
+
+	/*
+	* Map the 8M Intel Flash device to chip select 1
+	*/
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
+
+
+	/*
+	* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
+	* to chip select 3
+	*/
+	memctl->memc_or3 = CONFIG_SYS_OR3;
+	memctl->memc_br3 = CONFIG_SYS_BR3;
+
+	/*
+	* Map chip selects 4, 5, 6, & 7 for external expansion connector
+	*/
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
+
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
+
+	memctl->memc_or6 = CONFIG_SYS_OR6;
+	memctl->memc_br6 = CONFIG_SYS_BR6;
+
+	memctl->memc_or7 = CONFIG_SYS_OR7;
+	memctl->memc_br7 = CONFIG_SYS_BR7;
+
+#endif
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mbmr = mbmr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/u-boot/board/snmc/qs860t/u-boot.lds b/u-boot/board/snmc/qs860t/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/snmc/qs860t/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/socrates/Makefile b/u-boot/board/socrates/Makefile
new file mode 100644
index 0000000..1ca6377
--- /dev/null
+++ b/u-boot/board/socrates/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2008
+# Sergei Poselenov,  Emcraft Systems, sposelenov@emcraft.com.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+#
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-y	+= nand.o
+COBJS-y	+= sdram.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/socrates/ddr.c b/u-boot/board/socrates/ddr.c
new file mode 100644
index 0000000..2b62b84
--- /dev/null
+++ b/u-boot/board/socrates/ddr.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/socrates/law.c b/u-boot/board/socrates/law.c
new file mode 100644
index 0000000..cb55fd4
--- /dev/null
+++ b/u-boot/board/socrates/law.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x2fff_ffff	   DDR			   512M
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xc000_0000	   0xc00f_ffff	   FPGA			   1M
+ * 0xc800_0000	   0xcbff_ffff	   LIME			   64M
+ * 0xe000_0000	   0xe00f_ffff	   CCSR			   1M (mapped by CCSRBAR)
+ * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xfc00_0000	   0xffff_ffff	   FLASH		   64M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+#if defined(CONFIG_SYS_FPGA_BASE)
+	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/socrates/nand.c b/u-boot/board/socrates/nand.c
new file mode 100644
index 0000000..7d76f42
--- /dev/null
+++ b/u-boot/board/socrates/nand.c
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_SYS_NAND_BASE)
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+static int state;
+static void nand_write_byte(struct mtd_info *mtd, u_char byte);
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static u_char nand_read_byte(struct mtd_info *mtd);
+static u16 nand_read_word(struct mtd_info *mtd);
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static int nand_device_ready(struct mtd_info *mtdinfo);
+
+#define FPGA_NAND_CMD_MASK		(0x7 << 28)
+#define FPGA_NAND_CMD_COMMAND		(0x0 << 28)
+#define FPGA_NAND_CMD_ADDR		(0x1 << 28)
+#define FPGA_NAND_CMD_READ		(0x2 << 28)
+#define FPGA_NAND_CMD_WRITE		(0x3 << 28)
+#define FPGA_NAND_BUSY			(0x1 << 15)
+#define FPGA_NAND_ENABLE		(0x1 << 31)
+#define FPGA_NAND_DATA_SHIFT		16
+
+/**
+ * nand_write_byte -  write one byte to the chip
+ * @mtd:	MTD device structure
+ * @byte:	pointer to data byte to write
+ */
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+	nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
+}
+
+/**
+ * nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+
+	for (i = 0; i < len; i++) {
+		out_be32(this->IO_ADDR_W,
+			 state | (buf[i] << FPGA_NAND_DATA_SHIFT));
+	}
+}
+
+
+/**
+ * nand_read_byte -  read one byte from the chip
+ * @mtd:	MTD device structure
+ */
+static u_char nand_read_byte(struct mtd_info *mtd)
+{
+	u8 byte;
+	nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+	return byte;
+}
+
+/**
+ * nand_read_word -  read one word from the chip
+ * @mtd:	MTD device structure
+ */
+static u16 nand_read_word(struct mtd_info *mtd)
+{
+	u16 word;
+	nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+	return word;
+}
+
+/**
+ * nand_read_buf -  read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store date
+ * @len:	number of bytes to read
+ */
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+	int val;
+
+	val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
+
+	out_be32(this->IO_ADDR_W, val);
+	for (i = 0; i < len; i++) {
+		buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
+	}
+}
+
+/**
+ * nand_verify_buf -  Verify chip data against buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer containing the data to compare
+ * @len:	number of bytes to compare
+ */
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (buf[i] != nand_read_byte(mtd));
+			return -EFAULT;
+	}
+	return 0;
+}
+
+/**
+ * nand_device_ready - Check the NAND device is ready for next command.
+ * @mtd:	MTD device structure
+ */
+static int nand_device_ready(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+
+	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
+		return 0; /* busy */
+	return 1;
+}
+
+/**
+ * nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:	MTD device structure
+ * @cmd:	Command
+ */
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	if (ctrl & NAND_CTRL_CHANGE) {
+		state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
+
+		switch (ctrl & (NAND_ALE | NAND_CLE)) {
+		case 0:
+			state |= FPGA_NAND_CMD_WRITE;
+			break;
+
+		case NAND_ALE:
+			state |= FPGA_NAND_CMD_ADDR;
+			break;
+
+		case NAND_CLE:
+			state |= FPGA_NAND_CMD_COMMAND;
+			break;
+
+		default:
+			printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
+		}
+
+		if (ctrl & NAND_NCE)
+			state |= FPGA_NAND_ENABLE;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		nand_write_byte(mtdinfo, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->cmd_ctrl = nand_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->dev_ready = nand_device_ready;
+	nand->read_byte = nand_read_byte;
+	nand->read_word = nand_read_word;
+	nand->write_buf = nand_write_buf;
+	nand->read_buf = nand_read_buf;
+	nand->verify_buf = nand_verify_buf;
+
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/socrates/sdram.c b/u-boot/board/socrates/sdram.c
new file mode 100644
index 0000000..c8235f4
--- /dev/null
+++ b/u-boot/board/socrates/sdram.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ *       so this should be extended for other future boards
+ *       using this routine!
+ */
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+	/*
+	 * Disable memory controller.
+	 */
+	ddr->cs0_config = 0;
+	ddr->sdram_cfg = 0;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
+
+	asm ("sync;isync;msync");
+	udelay(1000);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
+	asm ("sync; isync; msync");
+	udelay(1000);
+
+	if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
+		/*
+		 * OK, size detected -> all done
+		 */
+		return CONFIG_SYS_SDRAM_SIZE<<20;
+	}
+
+	return 0;				/* nothing found !		*/
+}
+#endif
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
diff --git a/u-boot/board/socrates/socrates.c b/u-boot/board/socrates/socrates.c
new file mode 100644
index 0000000..72e7401
--- /dev/null
+++ b/u-boot/board/socrates/socrates.c
@@ -0,0 +1,447 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include "upm_table.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+extern GraphicDevice mb862xx;
+
+void local_bus_init (void);
+ulong flash_get_size (ulong base, int banknum);
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	char *src;
+	int f;
+	char *s = getenv("serial#");
+
+	puts("Board: Socrates");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+#ifdef CONFIG_PCI
+	/* Check the PCI_clk sel bit */
+	if (in_be32(&gur->porpllsr) & (1<<15)) {
+		src = "SYSCLK";
+		f = CONFIG_SYS_CLK_FREQ;
+	} else {
+		src = "PCI_CLK";
+		f = CONFIG_PCI_CLK_FREQ;
+	}
+	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
+#else
+	printf ("PCI1:  disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if boot FLASH isn't max size
+	 */
+	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+		set_lbc_or(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+		set_lbc_br(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
+	}
+
+	/*
+	 * Check if only one FLASH bank is available
+	 */
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
+
+		/*
+		 * Re-do flash protection upon new addresses
+		 */
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       gd->bd->bi_flashstart, 0xffffffff,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR,
+			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Redundant environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_ENV_ADDR_REDUND,
+			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+	}
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init (void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	sys_info_t sysinfo;
+	uint clkdiv;
+	uint lbc_mhz;
+	uint lcrr = CONFIG_SYS_LBC_LCRR;
+
+	get_sys_info (&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
+	if (lbc_mhz >= 66)
+		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */
+	else
+		lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	out_be32 (&lbc->lcrr, lcrr);
+	asm ("sync;isync;msync");
+
+	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */
+	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */
+	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
+	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */
+
+	/* Init UPMA for FPGA access */
+	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
+	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
+
+	/* Init UPMB for Lime controller access */
+	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
+	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init (&hose);
+#endif /* CONFIG_PCI */
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
+	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
+	out_be32((unsigned int*)&gur->gpiocr, 0x200 );	/* enable GPOut */
+	udelay(200);
+	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
+
+	return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[12];
+	int rc, i = 0;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR FLASH mapping */
+	val[i++] = 0;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = gd->bd->bi_flashstart;
+	val[i++] = gd->bd->bi_flashsize;
+
+	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
+		/* Fixup LIME mapping */
+		val[i++] = 2;			/* chip select number */
+		val[i++] = 0;			/* always 0 */
+		val[i++] = CONFIG_SYS_LIME_BASE;
+		val[i++] = CONFIG_SYS_LIME_SIZE;
+	}
+
+	/* Fixup FPGA mapping */
+	val[i++] = 3;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = CONFIG_SYS_FPGA_BASE;
+	val[i++] = CONFIG_SYS_FPGA_SIZE;
+
+	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+				  val, i * sizeof(u32), 1);
+	if (rc)
+		printf("Unable to update localbus ranges, err=%s\n",
+		       fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#define DEFAULT_BRIGHTNESS	25
+#define BACKLIGHT_ENABLE	(1 << 31)
+
+static const gdc_regs init_regs [] =
+{
+	{0x0100, 0x00010f00},
+	{0x0020, 0x801901df},
+	{0x0024, 0x00000000},
+	{0x0028, 0x00000000},
+	{0x002c, 0x00000000},
+	{0x0110, 0x00000000},
+	{0x0114, 0x00000000},
+	{0x0118, 0x01df0320},
+	{0x0004, 0x041f0000},
+	{0x0008, 0x031f031f},
+	{0x000c, 0x017f0349},
+	{0x0010, 0x020c0000},
+	{0x0014, 0x01df01e9},
+	{0x0018, 0x00000000},
+	{0x001c, 0x01e00320},
+	{0x0100, 0x80010f00},
+	{0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int lime_probe(void)
+{
+	uint cfg_br2;
+	uint cfg_or2;
+	int type;
+
+	cfg_br2 = get_lbc_br(2);
+	cfg_or2 = get_lbc_or(2);
+
+	/* Configure GPCM for CS2 */
+	set_lbc_br(2, 0);
+	set_lbc_or(2, 0xfc000410);
+	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
+
+	/* Get controller type */
+	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
+
+	/* Restore previous CS2 configuration */
+	set_lbc_br(2, 0);
+	set_lbc_or(2, cfg_or2);
+	set_lbc_br(2, cfg_br2);
+
+	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+	if (!lime_probe())
+		return 0;
+
+	mb862xx.winSizeX = 800;
+	mb862xx.winSizeY = 480;
+	mb862xx.gdfIndex = GDF_15BIT_555RGB;
+	mb862xx.gdfBytesPP = 2;
+
+	return CONFIG_SYS_LIME_BASE;
+}
+
+#define W83782D_REG_CFG		0x40
+#define W83782D_REG_BANK_SEL	0x4e
+#define W83782D_REG_ADCCLK	0x4b
+#define W83782D_REG_BEEP_CTRL	0x4d
+#define W83782D_REG_BEEP_CTRL2	0x57
+#define W83782D_REG_PWMOUT1	0x5b
+#define W83782D_REG_VBAT	0x5d
+
+static int w83782d_hwmon_init(void)
+{
+	u8 buf;
+
+	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
+		return -1;
+
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
+
+	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
+		      buf | 0x80);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
+
+	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
+		      (buf & 0xf4) | 0x01);
+	return 0;
+}
+
+static void board_backlight_brightness(int br)
+{
+	u32 reg;
+	u8 buf;
+	u8 old_buf;
+
+	/* Select bank 0 */
+	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+		goto err;
+	else
+		buf = old_buf & 0xf8;
+
+	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
+		goto err;
+
+	if (br > 0) {
+		/* PWMOUT1 duty cycle ctrl */
+		buf = 255 / (100 / br);
+		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+			goto err;
+
+		/* LEDs on */
+		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
+		if (!(reg & BACKLIGHT_ENABLE));
+			out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
+				 reg | BACKLIGHT_ENABLE);
+	} else {
+		buf = 0;
+		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+			goto err;
+
+		/* LEDs off */
+		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
+		reg &= ~BACKLIGHT_ENABLE;
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
+	}
+	/* Restore previous bank setting */
+	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+		goto err;
+
+	return;
+err:
+	printf("W83782G I2C access failed\n");
+}
+
+void board_backlight_switch (int flag)
+{
+	char * param;
+	int rc;
+
+	if (w83782d_hwmon_init())
+		printf ("hwmon IC init failed\n");
+
+	if (flag) {
+		param = getenv("brightness");
+		rc = param ? simple_strtol(param, NULL, 10) : -1;
+		if (rc < 0)
+			rc = DEFAULT_BRIGHTNESS;
+	} else {
+		rc = 0;
+	}
+	board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+		strcpy (info, " Board: Socrates");
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif
diff --git a/u-boot/board/socrates/tlb.c b/u-boot/board/socrates/tlb.c
new file mode 100644
index 0000000..4591e46
--- /dev/null
+++ b/u-boot/board/socrates/tlb.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+
+	/*
+	 * TLB 1:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#if defined(CONFIG_SYS_FPGA_BASE)
+	/*
+	 * TLB 4:	1M	Non-cacheable, guarded
+	 * 0xc0000000	1M	FPGA and NAND
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_1M, 1),
+#endif
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xc8000000	16M	LIME GDC framebuffer
+	 * 0xc9fc0000	256K	LIME GDC MMIO
+	 * (0xcbfc0000	256K	LIME GDC MMIO)
+	 * MMIO is relocatable and could be at 0xcbfc0000
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
+	 * 0x00000000  512M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/socrates/upm_table.h b/u-boot/board/socrates/upm_table.h
new file mode 100644
index 0000000..2a89c96
--- /dev/null
+++ b/u-boot/board/socrates/upm_table.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __UPM_TABLE_H
+#define __UPM_TABLE_H
+
+/* UPM Table Configuration Code for FPGA access */
+static const unsigned int UPMTableA[] =
+{
+	0x00fcec00,  0x00fcec00,  0x00fcec00,  0x00fcec00, /* Words 0 to 3	*/
+	0x00fcec00,  0x00fcfc00,  0x00fcfc00,  0x00fcec05, /* Words 4 to 7	*/
+	0x00fcec00,  0x00fcec00,  0x00fcec04,  0x00fcec04, /* Words 8 to 11	*/
+	0x00fcec04,  0x00fcec04,  0x00fcec04,  0x00fcec04, /* Words 12 to 15	*/
+	0x00fcec04,  0x00fcec04,  0x0fffec00,  0xffffec00, /* Words 16 to 19	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 20 to 23	*/
+	0x00ffec00,  0x00ffec00,  0x00f3ec00,  0x0fffec00, /* Words 24 to 27	*/
+	0x0ffffc04,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 28 to 31	*/
+	0x00ffec00,  0x00ffec00,  0x00f3ec04,  0x00f3ec04, /* Words 32 to 35	*/
+	0x00f3ec04,  0x00f3ec04,  0x00f3ec04,  0x00f3ec04, /* Words 36 to 39	*/
+	0x00f3ec04,  0x00f3ec04,  0x0fffec00,  0xffffec00, /* Words 40 to 43	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 44 to 47	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 48 to 51	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 52 to 55	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 56 to 59	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01  /* Words 60 to 63	*/
+};
+
+/* LIME UPM B Table Configuration Code */
+static unsigned int UPMTableB[] =
+{
+	0x0ffefc00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 0 to 3	*/
+	0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc04,  0x0ffffc01, /* Words 4 to 7	*/
+	0x0ffefc00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 8 to 11	*/
+	0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc04,  0x0ffcfc04, /* Words 12 to 15	*/
+	0x0ffcfc04,  0x0ffcfc04,  0x0ffcfc04,  0x0ffcfc04, /* Words 16 to 19	*/
+	0x0ffcfc04,  0x0ffcfc04,  0x0ffffc00,  0xfffffc01, /* Words 20 to 23	*/
+	0x0cfffc00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 24 to 27	*/
+	0x00fffc00,  0x00fffc00,  0x00fffc04,  0x0ffffc01, /* Words 28 to 31	*/
+	0x0cfffc00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 32 to 35	*/
+	0x00fffc00,  0x00fffc00,  0x00fffc04,  0x00fffc04, /* Words 36 to 39	*/
+	0x00fffc04,  0x00fffc04,  0x00fffc04,  0x00fffc04, /* Words 40 to 43	*/
+	0x00fffc04,  0x00fffc04,  0x0ffffc00,  0xfffffc01, /* Words 44 to 47	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 48 to 51	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  /* Words 60 to 63	*/
+};
+#endif
diff --git a/u-boot/board/sorcery/Makefile b/u-boot/board/sorcery/Makefile
new file mode 100644
index 0000000..ec5cf53
--- /dev/null
+++ b/u-boot/board/sorcery/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sorcery/sorcery.c b/u-boot/board/sorcery/sorcery.c
new file mode 100644
index 0000000..90d4298
--- /dev/null
+++ b/u-boot/board/sorcery/sorcery.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <netdev.h>
+
+phys_size_t initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, size);
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sorcery-C MPC8220\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc8220_init (struct pci_controller *hose);
+	pci_mpc8220_init (&hose);
+#endif /* CONFIG_PCI */
+}
+
+int board_eth_init(bd_t *bis)
+{
+	/* Initialize built-in FEC first */
+	cpu_eth_init(bis);
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/spc1920/Makefile b/u-boot/board/spc1920/Makefile
new file mode 100644
index 0000000..d783179
--- /dev/null
+++ b/u-boot/board/spc1920/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o hpi.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spc1920/hpi.c b/u-boot/board/spc1920/hpi.c
new file mode 100644
index 0000000..26d0f9c
--- /dev/null
+++ b/u-boot/board/spc1920/hpi.c
@@ -0,0 +1,612 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Host Port Interface (HPI)
+ */
+
+/* debug levels:
+ *  0 : errors
+ *  1 : usefull info
+ *  2 : lots of info
+ *  3 : noisy
+ */
+
+#define DEBUG 0
+
+#include <config.h>
+#include <common.h>
+#include <mpc8xx.h>
+
+#include "pld.h"
+#include "hpi.h"
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* original table:
+ * - inserted loops to achieve long CS low and high Periods (~217ns)
+ * - move cs high 2/4 to the right
+ */
+const uint dsp_table_slow[] =
+{
+	/* single read   (offset  0x00 in upm ram) */
+	0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00,
+	0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05,
+
+	/* burst read    (offset 0x08 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write  (offset 0x18 in upm ram) */
+	0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000,
+	0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* dsp hpi upm ram table
+ * works fine for noninc access, failes on incremental.
+ * - removed first word
+ */
+const uint dsp_table_fast[] =
+{
+	/* single read   (offset  0x00 in upm ram) */
+	0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04,
+	0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst read    (offset 0x08 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write  (offset 0x18 in upm ram) */
+	0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+#undef HPI_TEST_OSZI
+
+#define HPI_TEST_CHUNKSIZE	0x1000
+#define HPI_TEST_PATTERN	0x00000000
+#define HPI_TEST_START		0x0
+#define HPI_TEST_END		0x30000
+
+#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */
+#define TINY_AUTOINC_BASE_ADDR 0x0
+
+static int hpi_activate(void);
+#if 0
+static void hpi_inactivate(void);
+#endif
+static void dsp_reset(void);
+
+static int hpi_write_inc(u32 addr, u32 *data, u32 count);
+static int hpi_read_inc(u32 addr, u32 *buf, u32 count);
+static int hpi_write_noinc(u32 addr, u32 data);
+static u32 hpi_read_noinc(u32 addr);
+
+int hpi_test(void);
+static int hpi_write_addr_test(u32 addr);
+static int hpi_read_write_test(u32 addr, u32 data);
+#ifdef DO_TINY_TEST
+static int hpi_tiny_autoinc_test(void);
+#endif /* DO_TINY_TEST */
+#endif /* CONFIG_SPC1920_HPI_TEST */
+
+
+/* init the host port interface on UPMA */
+int hpi_init(void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
+
+	upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint));
+	udelay(100);
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR;
+	memctl->memc_or3 = CONFIG_SYS_OR3;
+	memctl->memc_br3 = CONFIG_SYS_BR3;
+
+	/* reset dsp */
+	dsp_reset();
+
+	/* activate hpi switch*/
+	pld->dsp_hpi_on = 0x1;
+
+	udelay(100);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+/* activate the Host Port interface */
+static int hpi_activate(void)
+{
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
+
+	/* turn on hpi */
+	pld->dsp_hpi_on = 0x1;
+
+	udelay(5);
+
+	/* turn on the power EN_DSP_POWER high*/
+	/* currently always on TBD */
+
+	/* setup hpi control register */
+	HPI_HPIC_1 = (u16) 0x0008;
+	HPI_HPIC_2 = (u16) 0x0008;
+
+	udelay(100);
+
+	return 0;
+}
+
+#if 0
+/* turn off the host port interface */
+static void hpi_inactivate(void)
+{
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
+
+	/* deactivate hpi */
+	pld->dsp_hpi_on = 0x0;
+
+	/* reset the dsp */
+	/* pld->dsp_reset = 0x0; */
+
+	/* turn off the power EN_DSP_POWER# high*/
+	/* currently always on TBD */
+
+}
+#endif
+
+/* reset the DSP */
+static void dsp_reset(void)
+{
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
+	pld->dsp_reset = 0x1;
+	pld->dsp_hpi_on = 0x0;
+
+	udelay(300000);
+
+	pld->dsp_reset = 0x0;
+	pld->dsp_hpi_on = 0x1;
+}
+
+
+/* write using autoinc (count is number of 32bit words) */
+static int hpi_write_inc(u32 addr, u32 *data, u32 count)
+{
+	int i;
+	u16 addr1, addr2;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	/* write address */
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	debugX(4, "writing from data=0x%lx to 0x%lx\n",
+		(ulong)data, (ulong)(data+count));
+
+	for(i=0; i<count; i++) {
+		HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff);
+		HPI_HPID_INC_2 = (u16) (data[i] & 0xffff);
+		debugX(4, "hpi_write_inc: data1=0x%x, data2=0x%x\n",
+		       (u16) ((data[i] >> 16) & 0xffff),
+		       (u16) (data[i] & 0xffff));
+	}
+#if 0
+	while(data_ptr < (u16*) (data + count)) {
+		HPI_HPID_INC_1 = *(data_ptr++);
+		HPI_HPID_INC_2 = *(data_ptr++);
+	}
+#endif
+
+	/* return number of bytes written */
+	return count;
+}
+
+/*
+ * read using autoinc (count is number of 32bit words)
+ */
+static int hpi_read_inc(u32 addr, u32 *buf, u32 count)
+{
+	int i;
+	u16 addr1, addr2, data1, data2;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	/* write address */
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	for(i=0; i<count; i++) {
+		data1 = HPI_HPID_INC_1;
+		data2 = HPI_HPID_INC_2;
+		debugX(4, "hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2);
+		buf[i] = (((u32) data1) << 16) | (data2 & 0xffff);
+	}
+
+#if 0
+	while(buf_ptr < (u16*) (buf + count)) {
+		*(buf_ptr++) = HPI_HPID_INC_1;
+		*(buf_ptr++) = HPI_HPID_INC_2;
+	}
+#endif
+
+	/* return number of bytes read */
+	return count;
+}
+
+
+/* write to non- auto inc regs */
+static int hpi_write_noinc(u32 addr, u32 data)
+{
+
+	u16 addr1, addr2, data1, data2;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	/* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
+
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	data1 = (u16) ((data >> 16) & 0xffff);
+	data2 = (u16) (data & 0xffff);
+
+	/* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
+
+	HPI_HPID_NOINC_1 = data1;
+	HPI_HPID_NOINC_2 = data2;
+
+	return 0;
+}
+
+/* read from non- auto inc regs */
+static u32 hpi_read_noinc(u32 addr)
+{
+	u16 addr1, addr2, data1, data2;
+	u32 ret;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	/* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
+
+	data1 = HPI_HPID_NOINC_1;
+	data2 = HPI_HPID_NOINC_2;
+
+	/* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
+
+	ret = (((u32) data1) << 16) | (data2 & 0xffff);
+	return ret;
+
+}
+
+/*
+ * Host Port Interface Tests
+ */
+
+#ifndef HPI_TEST_OSZI
+/* main test function */
+int hpi_test(void)
+{
+	int err = 0;
+	u32 i, ii, pattern, tmp;
+
+	pattern = HPI_TEST_PATTERN;
+
+	u32 test_data[HPI_TEST_CHUNKSIZE];
+	u32 read_data[HPI_TEST_CHUNKSIZE];
+
+	debugX(2, "hpi_test: activating hpi...");
+	hpi_activate();
+	debugX(2, "OK.\n");
+
+#if 0
+	/* Dump the first 1024 bytes
+	 *
+	 */
+	for(i=0; i<1024; i+=4) {
+		if(i%16==0)
+			printf("\n0x%08x: ", i);
+		printf("0x%08x ", hpi_read_noinc(i));
+	}
+#endif
+
+	/* HPIA read-write test
+	 *
+	 */
+	debugX(1, "hpi_test: starting HPIA read-write tests...\n");
+	err |= hpi_write_addr_test(0xdeadc0de);
+	err |= hpi_write_addr_test(0xbeefd00d);
+	err |= hpi_write_addr_test(0xabcd1234);
+	err |= hpi_write_addr_test(0xaaaaaaaa);
+	if(err) {
+		debugX(1, "hpi_test: HPIA read-write tests: *** FAILED ***\n");
+		return -1;
+	}
+	debugX(1, "hpi_test: HPIA read-write tests: OK\n");
+
+
+	/* read write test using nonincremental data regs
+	 *
+	 */
+	debugX(1, "hpi_test: starting nonincremental tests...\n");
+	for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
+		err |= hpi_read_write_test(i, pattern);
+
+		/* stolen from cmd_mem.c */
+		if(pattern & 0x80000000) {
+			pattern = -pattern;	/* complement & increment */
+		} else {
+			pattern = ~pattern;
+		}
+		err |= hpi_read_write_test(i, pattern);
+
+		if(err) {
+			debugX(1, "hpi_test: nonincremental tests *** FAILED ***\n");
+			return -1;
+		}
+	}
+	debugX(1, "hpi_test: nonincremental test OK\n");
+
+	/* read write a chunk of data using nonincremental data regs
+	 *
+	 */
+	debugX(1, "hpi_test: starting nonincremental chunk tests...\n");
+	pattern = HPI_TEST_PATTERN;
+	for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
+		hpi_write_noinc(i, pattern);
+
+		/* stolen from cmd_mem.c */
+		if(pattern & 0x80000000) {
+			pattern = -pattern;	/* complement & increment */
+		} else {
+			pattern = ~pattern;
+		}
+	}
+	pattern = HPI_TEST_PATTERN;
+	for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
+		tmp = hpi_read_noinc(i);
+
+		if(tmp != pattern) {
+			debugX(1, "hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp);
+			err = -1;
+		}
+		/* stolen from cmd_mem.c */
+		if(pattern & 0x80000000) {
+			pattern = -pattern;	/* complement & increment */
+		} else {
+			pattern = ~pattern;
+		}
+	}
+	if(err)
+		return -1;
+	debugX(1, "hpi_test: nonincremental chunk test OK\n");
+
+
+#ifdef DO_TINY_TEST
+	/* small verbose test using autoinc and nonautoinc to compare
+	 *
+	 */
+	debugX(1, "hpi_test: tiny_autoinc_test...\n");
+	hpi_tiny_autoinc_test();
+	debugX(1, "hpi_test: tiny_autoinc_test done\n");
+#endif /* DO_TINY_TEST */
+
+
+	/* $%& write a chunk of data using the autoincremental regs
+	 *
+	 */
+	debugX(1, "hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n",
+	       ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE),
+	       HPI_TEST_CHUNKSIZE);
+
+	for(i=HPI_TEST_START;
+	    i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE);
+	    i++) {
+		/* generate the pattern data */
+		debugX(3, "generating pattern data: ");
+		for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
+			debugX(3, "0x%x ", pattern);
+
+			test_data[ii] = pattern;
+			read_data[ii] = 0x0; /* zero to be sure */
+
+			/* stolen from cmd_mem.c */
+			if(pattern & 0x80000000) {
+				pattern = -pattern;	/* complement & increment */
+			} else {
+				pattern = ~pattern;
+			}
+		}
+		debugX(3, "done\n");
+
+		debugX(2, "Writing autoinc data @ 0x%x\n", i);
+		hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE);
+
+		debugX(2, "Reading autoinc data @ 0x%x\n", i);
+		hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE);
+
+		/* compare */
+		for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
+			debugX(3, "hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]);
+			if(read_data[ii] != test_data[ii]) {
+				debugX(0, "hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]);
+				return -1;
+			}
+		}
+	}
+	debugX(1, "hpi_test: autoinc test OK\n");
+
+	return 0;
+}
+#else /* HPI_TEST_OSZI */
+int hpi_test(void)
+{
+	int i;
+	u32 read_data[TINY_AUTOINC_DATA_SIZE];
+
+	unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
+		0x11112222, 0x33334444, 0x55556666, 0x77778888,
+		0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
+		0x00010002, 0x00030004, 0x00050006, 0x00070008,
+		0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
+	};
+
+	debugX(0, "hpi_test: activating hpi...");
+	hpi_activate();
+	debugX(0, "OK.\n");
+
+	while(1) {
+		led9(1);
+		debugX(0, " writing to autoinc...\n");
+		hpi_write_inc(TINY_AUTOINC_BASE_ADDR,
+			      dummy_data, TINY_AUTOINC_DATA_SIZE);
+
+		debugX(0, " reading from autoinc...\n");
+		hpi_read_inc(TINY_AUTOINC_BASE_ADDR,
+			     read_data, TINY_AUTOINC_DATA_SIZE);
+
+		for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
+			debugX(0, " written=0x%x, read(inc)=0x%x\n",
+			       dummy_data[i], read_data[i]);
+		}
+		led9(0);
+		udelay(2000000);
+	}
+	return 0;
+}
+#endif
+
+/* test if Host Port Address Register can be written correctly */
+static int hpi_write_addr_test(u32 addr)
+{
+	u32 read_back;
+	/* write address */
+	HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */
+	HPI_HPIA_2 = ((u16) addr);
+
+	read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2);
+
+	if(read_back == addr) {
+		debugX(2, " hpi_write_addr_test OK: written=0x%x, read=0x%x\n",
+		       addr, read_back);
+		return 0;
+	} else {
+		debugX(0, " hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n",
+		      addr, read_back);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* test if a simple read/write sequence succeeds */
+static int hpi_read_write_test(u32 addr, u32 data)
+{
+	u32 read_back;
+
+	hpi_write_noinc(addr, data);
+	read_back = hpi_read_noinc(addr);
+
+	if(read_back == data) {
+		debugX(2, " hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
+		return 0;
+	} else {
+		debugX(0, " hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
+		return -1;
+	}
+
+	return 0;
+}
+
+#ifdef DO_TINY_TEST
+static int hpi_tiny_autoinc_test(void)
+{
+	int i;
+	u32 read_data[TINY_AUTOINC_DATA_SIZE];
+	u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE];
+
+	unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
+		0x11112222, 0x33334444, 0x55556666, 0x77778888,
+		0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
+		0x00010002, 0x00030004, 0x00050006, 0x00070008,
+		0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
+	};
+
+	printf(" writing to autoinc...\n");
+	hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE);
+
+	printf(" reading from autoinc...\n");
+	hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE);
+
+	printf(" reading from noinc for comparison...\n");
+	for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++)
+		read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4);
+
+	for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
+		printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n",
+		       dummy_data[i], read_data[i], read_data_noinc[i]);
+	}
+	return 0;
+}
+#endif /* DO_TINY_TEST */
+
+#endif /* CONFIG_SPC1920_HPI_TEST */
diff --git a/u-boot/board/spc1920/hpi.h b/u-boot/board/spc1920/hpi.h
new file mode 100644
index 0000000..4503873
--- /dev/null
+++ b/u-boot/board/spc1920/hpi.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+int hpi_init(void);
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+int hpi_test(void);
+#endif
diff --git a/u-boot/board/spc1920/pld.h b/u-boot/board/spc1920/pld.h
new file mode 100644
index 0000000..5beb71b
--- /dev/null
+++ b/u-boot/board/spc1920/pld.h
@@ -0,0 +1,14 @@
+#ifndef __PLD_H__
+#define __PLD_H__
+
+typedef struct spc1920_pld {
+	uchar com1_en;
+	uchar dsp_reset;
+	uchar dsp_hpi_on;
+	uchar superv_mode;
+	uchar codec_dsp_power_en;
+	uchar clk3_select;
+	uchar clk4_select;
+} spc1920_pld_t;
+
+#endif /* __PLD_H__ */
diff --git a/u-boot/board/spc1920/spc1920.c b/u-boot/board/spc1920/spc1920.c
new file mode 100644
index 0000000..ee939bf
--- /dev/null
+++ b/u-boot/board/spc1920/spc1920.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mpc8xx.h>
+#include "pld.h"
+#include "hpi.h"
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+static long int dram_size (long int, long int *, long int);
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMB RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMB RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMB RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMB RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMB RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMB RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMB RAM)
+	 */
+	0x7FFFFC07, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */
+
+	long int size_b0;
+	long int size8, size9;
+	int i;
+
+	/*
+	 * Configure UPMB for SDRAM
+	 */
+	upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	udelay(100);
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	/* burst length=4, burst type=sequential, CAS latency=2 */
+	memctl->memc_mar = CONFIG_SYS_MAR;
+
+	/*
+	 * Map controller bank 1 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+	/* initialize memory address register */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
+
+	/* mode initialization (offset 5) */
+	udelay (200);				/* 0x80006105 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+	udelay (1);				/* 0x80006130 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
+	udelay (1);				/* 0x80006130 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
+	udelay (1);				/* 0x80006106 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
+
+	udelay (200);
+
+	/* Need at least 10 DRAM accesses to stabilize */
+	for (i = 0; i < 10; ++i) {
+		volatile unsigned long *addr =
+			(volatile unsigned long *) CONFIG_SYS_SDRAM_BASE;
+		unsigned long val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+		memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE;
+		udelay (500);
+	} else {			/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
+		udelay (500);
+	}
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
+			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+	udelay (1000);
+
+	/* initalize the DSP Host Port Interface */
+	hpi_init();
+
+	/* FRAM Setup */
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
+	udelay(1000);
+
+	return (size_b0);
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mbmr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mbmr = mbmr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+
+/************* other stuff ******************/
+
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* Set Go/NoGo led (PA15) to color red */
+	immap->im_ioport.iop_papar &= ~0x1;
+	immap->im_ioport.iop_paodr &= ~0x1;
+	immap->im_ioport.iop_padir |= 0x1;
+	immap->im_ioport.iop_padat |= 0x1;
+
+#if 0
+	/* Turn on LED PD9 */
+	immap->im_ioport.iop_pdpar &= ~(0x0040);
+	immap->im_ioport.iop_pddir |= 0x0040;
+	immap->im_ioport.iop_pddat |= 0x0040;
+#endif
+
+	/*
+	 * Enable console on SMC1. This requires turning on
+	 * the com2_en signal and SMC1_DISABLE
+	 */
+
+	/* SMC1_DISABLE: PB17 */
+	immap->im_cpm.cp_pbodr &= ~0x4000;
+	immap->im_cpm.cp_pbpar &= ~0x4000;
+	immap->im_cpm.cp_pbdir |= 0x4000;
+	immap->im_cpm.cp_pbdat &= ~0x4000;
+
+	/* COM2_EN: PD10 */
+	immap->im_ioport.iop_pdpar &= ~0x0020;
+	immap->im_ioport.iop_pddir &= ~0x4000;
+	immap->im_ioport.iop_pddir |= 0x0020;
+	immap->im_ioport.iop_pddat |= 0x0020;
+
+
+#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
+	immap->im_cpm.cp_simode |= 0x7000;
+	immap->im_cpm.cp_simode &= ~(0x8000);
+#endif
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+#ifdef CONFIG_SPC1920_HPI_TEST
+	printf("CMB1920 Host Port Interface Test: %s\n",
+	       hpi_test() ? "Failed!" : "OK");
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts("Board: SPC1920\n");
+	return 0;
+}
diff --git a/u-boot/board/spc1920/u-boot.lds b/u-boot/board/spc1920/u-boot.lds
new file mode 100644
index 0000000..fbd901a
--- /dev/null
+++ b/u-boot/board/spc1920/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/spd8xx/Makefile b/u-boot/board/spd8xx/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/spd8xx/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spd8xx/flash.c b/u-boot/board/spd8xx/flash.c
new file mode 100644
index 0000000..fb2fb6a
--- /dev/null
+++ b/u-boot/board/spd8xx/flash.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	/* All Speech Design board memory (DRAM and EPROM) initialisation is
+	done in dram_init().
+	The caller of ths function here expects the total size and will hang,
+	if we give here back 0. So we return the EPROM size. */
+
+	return (1024 * 1024); /* 1 MB */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	printf("no FLASH memory in MPC823TS board\n");
+	return;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	return 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/spd8xx/spd8xx.c b/u-boot/board/spd8xx/spd8xx.c
new file mode 100644
index 0000000..9e9678d
--- /dev/null
+++ b/u-boot/board/spd8xx/spd8xx.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sharc_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+	puts ("Board: SPD823TS\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0;
+
+#if 0
+	/*
+	 * Map controller bank 2 to the SRAM bank at preliminary address.
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
+#endif
+
+	/*
+	 * Map controller bank 4 to the PER8 bank.
+	 */
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
+
+#if 0
+	/* Configure SHARC at UMA */
+	upmconfig (UPMA, (uint *) sharc_table,
+		   sizeof (sharc_table) / sizeof (uint));
+	/* Map controller bank 5 to the SHARC */
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
+#endif
+
+	memctl->memc_mamr = 0x00001000;
+
+	/* Configure SDRAM at UMB */
+	upmconfig (UPMB, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;	/* refresh not enabled yet */
+
+	udelay (200);
+	memctl->memc_mcr = 0x80806105;
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;
+	udelay (1);
+	memctl->memc_mcr = 0x80806106;
+
+	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+	size_b0 =
+		dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mbmr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy (void)
+{
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	ushort sreg;
+
+	/* Configure extra port pins for NS DP83843 PHY */
+	immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
+
+	sreg = immr->im_ioport.iop_padir;
+	sreg |= PA_ENET_MDC;	/* Mgmt. Data Clock is Output */
+	sreg &= ~(PA_ENET_MDIO);	/* Mgmt. Data I/O is bidirect. => Input */
+	immr->im_ioport.iop_padir = sreg;
+
+	immr->im_ioport.iop_padat &= ~(PA_ENET_MDC);	/* set MDC = 0 */
+
+	/*
+	 * RESET in implemented by a positive pulse of at least 1 us
+	 * at the reset pin.
+	 *
+	 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
+	 *
+	 * Note: The RESET pin is high active, but there is an
+	 *       inverter on the SPD823TS board...
+	 */
+	immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
+	immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
+	/* assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
+	udelay (10);
+	/* de-assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
+	udelay (10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void ide_set_reset (int on)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/*
+	 * Configure PC for IDE Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+	} else {		/* release RESET */
+		immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
+	}
+
+	/* program port pin as GPIO output */
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/spd8xx/u-boot.lds b/u-boot/board/spd8xx/u-boot.lds
new file mode 100644
index 0000000..b9dd8b7
--- /dev/null
+++ b/u-boot/board/spd8xx/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    net/libnet.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    board/spd8xx/libspd8xx.o		(.text*)
+    *(.text.v*printf)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/spd8xx/u-boot.lds.debug b/u-boot/board/spd8xx/u-boot.lds.debug
new file mode 100644
index 0000000..a7a67a9
--- /dev/null
+++ b/u-boot/board/spd8xx/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/spear/common/Makefile b/u-boot/board/spear/common/Makefile
new file mode 100644
index 0000000..e0df6c1
--- /dev/null
+++ b/u-boot/board/spear/common/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS	:= spr_misc.o
+SOBJS	:= spr_lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spear/common/spr_lowlevel_init.S b/u-boot/board/spear/common/spr_lowlevel_init.S
new file mode 100644
index 0000000..6fbe579
--- /dev/null
+++ b/u-boot/board/spear/common/spr_lowlevel_init.S
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2006
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+/*
+ * platform specific initializations are already done in Xloader
+ * Initializations already done include
+ * DDR, PLLs, IP's clock enable and reset release etc
+ */
+.globl lowlevel_init
+lowlevel_init:
+	/* By default, U-Boot switches CPU to low-vector */
+	/* Revert this as we work in high vector even in U-Boot */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0x00002000
+	mcr	p15, 0, r0, c1, c0, 0
+	mov	pc, lr
+
+/* void setfreq(unsigned int device, unsigned int frequency) */
+.global setfreq
+setfreq:
+	stmfd 	sp!,{r14}
+	stmfd 	sp!,{r0-r12}
+
+	mov  	r8,sp
+	ldr 	sp,SRAM_STACK_V
+
+	/* Saving the function arguements for later use */
+	mov  	r4,r0
+	mov  	r5,r1
+
+	/* Putting DDR into self refresh */
+	ldr 	r0,DDR_07_V
+	ldr	r1,[r0]
+	ldr	r2,DDR_ACTIVE_V
+	bic	r1, r1, r2
+	str	r1,[r0]
+	ldr 	r0,DDR_57_V
+	ldr	r1,[r0]
+	ldr	r2,CYCLES_MASK_V
+	bic	r1, r1, r2
+	ldr	r2,REFRESH_CYCLES_V
+	orr	r1, r1, r2, lsl #16
+	str	r1,[r0]
+	ldr 	r0,DDR_07_V
+	ldr	r1,[r0]
+	ldr	r2,SREFRESH_MASK_V
+	orr	r1, r1, r2
+	str	r1,[r0]
+
+	/* flush pipeline */
+	b	flush
+	.align 5
+flush:
+	/* Delay to ensure self refresh mode */
+	ldr	r0,SREFRESH_DELAY_V
+delay:
+	sub	r0,r0,#1
+	cmp	r0,#0
+	bne	delay
+
+	/* Putting system in slow mode */
+	ldr	r0,SCCTRL_V
+	mov	r1,#2
+	str	r1,[r0]
+
+	/* Changing PLL(1/2) frequency */
+	mov	r0,r4
+	mov	r1,r5
+
+	cmp	r4,#0
+	beq	pll1_freq
+
+	/* Change PLL2 (DDR frequency) */
+	ldr	r6,PLL2_FREQ_V
+	ldr	r7,PLL2_CNTL_V
+	b	pll2_freq
+
+pll1_freq:
+	/* Change PLL1 (CPU frequency) */
+	ldr	r6,PLL1_FREQ_V
+	ldr	r7,PLL1_CNTL_V
+
+pll2_freq:
+	mov	r0,r6
+	ldr	r1,[r0]
+	ldr	r2,PLLFREQ_MASK_V
+	bic	r1,r1,r2
+	mov	r2,r5,lsr#1
+	orr	r1,r1,r2,lsl#24
+	str	r1,[r0]
+
+	mov	r0,r7
+	ldr	r1,P1C0A_V
+	str	r1,[r0]
+	ldr	r1,P1C0E_V
+	str	r1,[r0]
+	ldr	r1,P1C06_V
+	str	r1,[r0]
+	ldr	r1,P1C0E_V
+	str	r1,[r0]
+
+lock:
+	ldr	r1,[r0]
+	and	r1,r1,#1
+	cmp	r1,#0
+	beq	lock
+
+	/* Putting system back to normal mode */
+	ldr	r0,SCCTRL_V
+	mov	r1,#4
+	str	r1,[r0]
+
+	/* Putting DDR back to normal */
+	ldr	r0,DDR_07_V
+	ldr	r1,[R0]
+	ldr	r2,SREFRESH_MASK_V
+	bic	r1, r1, r2
+	str	r1,[r0]
+	ldr	r2,DDR_ACTIVE_V
+	orr	r1, r1, r2
+	str	r1,[r0]
+
+	/* Delay to ensure self refresh mode */
+	ldr	r0,SREFRESH_DELAY_V
+1:
+	sub	r0,r0,#1
+	cmp	r0,#0
+	bne	1b
+
+	mov	sp,r8
+	/* Resuming back to code */
+	ldmia	sp!,{r0-r12}
+	ldmia	sp!,{pc}
+
+SCCTRL_V:
+	.word 0xfca00000
+PLL1_FREQ_V:
+	.word 0xfca8000C
+PLL1_CNTL_V:
+	.word 0xfca80008
+PLL2_FREQ_V:
+	.word 0xfca80018
+PLL2_CNTL_V:
+	.word 0xfca80014
+PLLFREQ_MASK_V:
+	.word 0xff000000
+P1C0A_V:
+	.word 0x1C0A
+P1C0E_V:
+	.word 0x1C0E
+P1C06_V:
+	.word 0x1C06
+
+SREFRESH_DELAY_V:
+	.word 0x9999
+SRAM_STACK_V:
+	.word 0xD2800600
+DDR_07_V:
+	.word 0xfc60001c
+DDR_ACTIVE_V:
+	.word 0x01000000
+DDR_57_V:
+	.word 0xfc6000e4
+CYCLES_MASK_V:
+	.word 0xffff0000
+REFRESH_CYCLES_V:
+	.word 0xf0f0
+SREFRESH_MASK_V:
+	.word 0x00010000
+
+.global setfreq_sz
+setfreq_sz:
+	.word setfreq_sz - setfreq
diff --git a/u-boot/board/spear/common/spr_misc.c b/u-boot/board/spear/common/spr_misc.c
new file mode 100644
index 0000000..0562222
--- /dev/null
+++ b/u-boot/board/spear/common/spr_misc.c
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_emi.h>
+#include <asm/arch/spr_xloader_table.h>
+#include <asm/arch/spr_defs.h>
+
+#define CPU		0
+#define DDR		1
+#define SRAM_REL	0xD2801000
+
+DECLARE_GLOBAL_DATA_PTR;
+static struct chip_data chip_data;
+
+int dram_init(void)
+{
+	struct xloader_table *xloader_tb =
+	    (struct xloader_table *)XLOADER_TABLE_ADDRESS;
+	struct xloader_table_1_1 *table_1_1;
+	struct xloader_table_1_2 *table_1_2;
+	struct chip_data *chip = &chip_data;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1,
+					       PHYS_SDRAM_1_MAXSIZE);
+
+	if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) {
+		table_1_1 = &xloader_tb->table.table_1_1;
+		chip->dramfreq = table_1_1->ddrfreq;
+		chip->dramtype = table_1_1->ddrtype;
+
+	} else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
+		table_1_2 = &xloader_tb->table.table_1_2;
+		chip->dramfreq = table_1_2->ddrfreq;
+		chip->dramtype = table_1_2->ddrtype;
+	} else {
+		chip->dramfreq = -1;
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_NET)
+	uchar mac_id[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+		eth_setenv_enetaddr("ethaddr", mac_id);
+#endif
+	setenv("verify", "n");
+
+#if defined(CONFIG_SPEAR_USBTTY)
+	setenv("stdin", "usbtty");
+	setenv("stdout", "usbtty");
+	setenv("stderr", "usbtty");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+	unsigned int tap;
+	unsigned int tsdp;
+	unsigned int tdpw;
+	unsigned int tdpr;
+	unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+	.tap = 0x10,
+	.tsdp = 0x05,
+	.tdpw = 0x0a,
+	.tdpr = 0x0a,
+	.tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+	.tap = 0xf,
+	.tsdp = 0x0,
+	.tdpw = 0xff,
+	.tdpr = 0x111,
+	.tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+	const struct cust_emi_para *p = &emi_timing_m28w640hc;
+	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+	unsigned int cs;
+	unsigned int val, tmp;
+
+	val = readl(CONFIG_SPEAR_RASBASE);
+
+	if (val & EMI_ACKMSK)
+		tmp = 0x3f;
+	else
+		tmp = 0x0;
+
+	writel(tmp, &emi_regs_p->ack);
+
+	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+		       &emi_regs_p->bank_regs[cs].control);
+	}
+}
+#endif
+
+int spear_board_init(ulong mach_type)
+{
+	struct xloader_table *xloader_tb =
+	    (struct xloader_table *)XLOADER_TABLE_ADDRESS;
+	struct xloader_table_1_2 *table_1_2;
+	struct chip_data *chip = &chip_data;
+
+	gd->bd->bi_arch_number = mach_type;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+	/* CPU is initialized to work at 333MHz in Xloader */
+	chip->cpufreq = 333;
+
+	if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
+		table_1_2 = &xloader_tb->table.table_1_2;
+		memcpy(chip->version, table_1_2->version,
+		       sizeof(chip->version));
+	}
+
+#ifdef CONFIG_SPEAR_EMI
+	spear_emi_init();
+#endif
+	return 0;
+}
+
+static int i2c_read_mac(uchar *buffer)
+{
+	u8 buf[2];
+
+	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+	/* Check if mac in i2c memory is valid */
+	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+		/* Valid mac address is saved in i2c eeprom */
+		i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int write_mac(uchar *mac)
+{
+	u8 buf[2];
+
+	buf[0] = (u8)MAGIC_BYTE0;
+	buf[1] = (u8)MAGIC_BYTE1;
+	i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+	buf[0] = (u8)~MAGIC_BYTE0;
+	buf[1] = (u8)~MAGIC_BYTE1;
+
+	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+	/* check if valid MAC address is saved in I2C EEPROM or not? */
+	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+		i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
+		puts("I2C EEPROM written with mac address \n");
+		return 0;
+	}
+
+	puts("I2C EEPROM writing failed \n");
+	return -1;
+}
+
+int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	void (*sram_setfreq) (unsigned int, unsigned int);
+	struct chip_data *chip = &chip_data;
+	unsigned char mac[6];
+	unsigned int reg, frequency;
+	char *s, *e;
+	char i2c_mac[20];
+
+	if ((argc > 3) || (argc < 2))
+		return cmd_usage(cmdtp);
+
+	if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
+
+		frequency = simple_strtoul(argv[2], NULL, 0);
+
+		if (frequency > 333) {
+			printf("Frequency is limited to 333MHz\n");
+			return 1;
+		}
+
+		sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
+
+		if (!strcmp(argv[1], "cpufreq")) {
+			sram_setfreq(CPU, frequency);
+			printf("CPU frequency changed to %u\n", frequency);
+
+			chip->cpufreq = frequency;
+		} else {
+			sram_setfreq(DDR, frequency);
+			printf("DDR frequency changed to %u\n", frequency);
+
+			chip->dramfreq = frequency;
+		}
+
+		return 0;
+	} else if (!strcmp(argv[1], "ethaddr")) {
+
+		s = argv[2];
+		for (reg = 0; reg < 6; ++reg) {
+			mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		write_mac(mac);
+
+		return 0;
+	} else if (!strcmp(argv[1], "print")) {
+
+		if (chip->cpufreq == -1)
+			printf("CPU Freq    = Not Known\n");
+		else
+			printf("CPU Freq    = %d MHz\n", chip->cpufreq);
+
+		if (chip->dramfreq == -1)
+			printf("DDR Freq    = Not Known\n");
+		else
+			printf("DDR Freq    = %d MHz\n", chip->dramfreq);
+
+		if (chip->dramtype == DDRMOBILE)
+			printf("DDR Type    = MOBILE\n");
+		else if (chip->dramtype == DDR2)
+			printf("DDR Type    = DDR2\n");
+		else
+			printf("DDR Type    = Not Known\n");
+
+		if (!i2c_read_mac(mac)) {
+			sprintf(i2c_mac, "%pM", mac);
+			printf("Ethaddr (from i2c mem) = %s\n", i2c_mac);
+		} else {
+			printf("Ethaddr (from i2c mem) = Not set\n");
+		}
+
+		printf("Xloader Rev = %s\n", chip->version);
+
+		return 0;
+	}
+
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
+	   "configure chip",
+	   "chip_config cpufreq/ddrfreq frequency\n"
+	   "chip_config print");
diff --git a/u-boot/board/spear/spear300/Makefile b/u-boot/board/spear/spear300/Makefile
new file mode 100644
index 0000000..b9b0fed
--- /dev/null
+++ b/u-boot/board/spear/spear300/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= spear300.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spear/spear300/config.mk b/u-boot/board/spear/spear300/config.mk
new file mode 100644
index 0000000..11da2c3
--- /dev/null
+++ b/u-boot/board/spear/spear300/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+CONFIG_SYS_TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/u-boot/board/spear/spear300/spear300.c b/u-boot/board/spear/spear300/spear300.c
new file mode 100644
index 0000000..60ee544
--- /dev/null
+++ b/u-boot/board/spear/spear300/spear300.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR300);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/u-boot/board/spear/spear310/Makefile b/u-boot/board/spear/spear310/Makefile
new file mode 100644
index 0000000..6dce093
--- /dev/null
+++ b/u-boot/board/spear/spear310/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= spear310.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spear/spear310/config.mk b/u-boot/board/spear/spear310/config.mk
new file mode 100644
index 0000000..2b59c39
--- /dev/null
+++ b/u-boot/board/spear/spear310/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+CONFIG_SYS_TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
+
+# Support parallel flash
+ifeq ($(FLASH),PNOR)
+PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
+endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/u-boot/board/spear/spear310/spear310.c b/u-boot/board/spear/spear310/spear310.c
new file mode 100644
index 0000000..03dfe16
--- /dev/null
+++ b/u-boot/board/spear/spear310/spear310.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR310);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/u-boot/board/spear/spear320/Makefile b/u-boot/board/spear/spear320/Makefile
new file mode 100644
index 0000000..f6bd7dd
--- /dev/null
+++ b/u-boot/board/spear/spear320/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= spear320.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spear/spear320/config.mk b/u-boot/board/spear/spear320/config.mk
new file mode 100644
index 0000000..2b59c39
--- /dev/null
+++ b/u-boot/board/spear/spear320/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+CONFIG_SYS_TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
+
+# Support parallel flash
+ifeq ($(FLASH),PNOR)
+PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
+endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/u-boot/board/spear/spear320/spear320.c b/u-boot/board/spear/spear320/spear320.c
new file mode 100644
index 0000000..2ba2dbb
--- /dev/null
+++ b/u-boot/board/spear/spear320/spear320.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR320);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/u-boot/board/spear/spear600/Makefile b/u-boot/board/spear/spear600/Makefile
new file mode 100644
index 0000000..6b643bf
--- /dev/null
+++ b/u-boot/board/spear/spear600/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= spear600.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/spear/spear600/config.mk b/u-boot/board/spear/spear600/config.mk
new file mode 100644
index 0000000..11da2c3
--- /dev/null
+++ b/u-boot/board/spear/spear600/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+CONFIG_SYS_TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/u-boot/board/spear/spear600/spear600.c b/u-boot/board/spear/spear600/spear600.c
new file mode 100644
index 0000000..eef9a37
--- /dev/null
+++ b/u-boot/board/spear/spear600/spear600.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+		return spear_nand_init(nand);
+
+	return -1;
+}
diff --git a/u-boot/board/st/nhk8815/Makefile b/u-boot/board/st/nhk8815/Makefile
new file mode 100644
index 0000000..3f360dc
--- /dev/null
+++ b/u-boot/board/st/nhk8815/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= nhk8815.o
+SOBJS	:= platform.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/st/nhk8815/config.mk b/u-boot/board/st/nhk8815/config.mk
new file mode 100644
index 0000000..1789717
--- /dev/null
+++ b/u-boot/board/st/nhk8815/config.mk
@@ -0,0 +1,26 @@
+# (C) Copyright 2007
+# STMicroelectronics, <www.st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# image should be loaded at 0x01000000
+#
+
+CONFIG_SYS_TEXT_BASE = 0x03F80000
diff --git a/u-boot/board/st/nhk8815/nhk8815.c b/u-boot/board/st/nhk8815/nhk8815.c
new file mode 100644
index 0000000..faef810
--- /dev/null
+++ b/u-boot/board/st/nhk8815/nhk8815.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2005
+ * STMicrolelctronics, <www.st.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+	printf("%i\n", progress);
+}
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
+	gd->bd->bi_boot_params = 0x00000100;
+	writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
+	writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
+	writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
+	writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
+
+	/* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
+	writel(0x0000305b, REG_FSMC_BCR1);
+	writel(0x00033f33, REG_FSMC_BTR1);
+
+	/* Set up SMCS0 for OneNand: sram-like once again */
+	writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
+	writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
+
+	icache_enable();
+	return 0;
+}
+
+int board_late_init(void)
+{
+	/* Set the two I2C gpio lines to be gpio high */
+	nmk_gpio_set(__SCL, 1);	nmk_gpio_set(__SDA, 1);
+	nmk_gpio_dir(__SCL, 1);	nmk_gpio_dir(__SDA, 1);
+	nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
+
+	/* Reset the I2C port expander, on GPIO77 */
+	nmk_gpio_af(77, GPIO_GPIO);
+	nmk_gpio_dir(77, 1);
+	nmk_gpio_set(77, 0);
+	udelay(10);
+	nmk_gpio_set(77, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* set dram bank start addr and size */
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/st/nhk8815/platform.S b/u-boot/board/st/nhk8815/platform.S
new file mode 100644
index 0000000..2a67110
--- /dev/null
+++ b/u-boot/board/st/nhk8815/platform.S
@@ -0,0 +1,340 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2005
+ * STMicrolelctronics, <www.st.com>
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Jump to the flash address */
+	ldr r0, =CFG_ONENAND_BASE
+
+	/*
+	 * Make it independent whether we boot from 0x0 or 0x30000000.
+	 * Non-portable: it relies on the knowledge that ip has to be updated
+	 */
+	orr ip, ip, r0	/* adjust return address of cpu_init_crit */
+	orr lr, lr, r0	/* adjust return address */
+	orr pc, pc, r0	/* jump to the normal address */
+	nop
+
+	/* Initialize PLL, Remap clear, FSMC, MPMC here! */
+	/* What about GPIO, CLCD and UART */
+
+	/* PLL Initialization */
+	/* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */
+	ldr r0, =NOMADIK_SRC_BASE
+
+	ldr r1, =0x2B013502
+
+	str r1, [r0, #0x14]
+
+	/* Used to set all the timers clock to 2.4MHZ */
+	ldr r1, =0x2AAAA004
+	str r1, [r0]
+
+	ldr r1, =0x10000000
+	str r1, [r0, #0x10]
+
+	/* FSMC setup ---- */
+	ldr r0, =NOMADIK_FSMC_BASE
+
+	ldr r1, =0x10DB		/* For 16-bit NOR flash */
+	str r1, [r0, #0x08]
+
+	ldr r1, =0x03333333	/* For 16-bit NOR flash */
+	str r1, [r0, #0xc]
+
+	/* oneNAND setting */
+	ldr r1, =0x0000105B	/* BCR0 Prog control register */
+	str r1, [r0]
+
+	ldr r1, =0x0A200551	/* BTR0 Prog timing register */
+	str r1, [r0, #0x04]
+
+	/* preload the instructions into icache */
+	add r0, pc, #0x1F
+	bic r0, r0, #0x1F
+	mcr p15, 0, r0, c7, c13, 1
+	add r0, r0, #0x20
+	mcr p15, 0, r0, c7, c13, 1
+
+	/* Now Clear Remap */
+	ldr r0, =NOMADIK_SRC_BASE
+
+	ldr r1, =0x2004
+	str r1, [r0]
+
+	ldr r1, =0x10000000
+	str r1, [r0, #0x10]
+
+	ldr r0, =0x101E9000
+	ldr r1, =0x2004
+	str r1, [r0]
+
+	ldr r0, =NOMADIK_SRC_BASE
+	ldr r1, =0x2104
+	str r1, [r0]
+
+	/* FSMC setup -- */
+	mov r0, #(NOMADIK_FSMC_BASE & 0x10000000)
+	orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF)
+
+	ldr r1, =0x10DB		/* For 16-bit NOR flash */
+	str r1, [r0, #0x8]
+
+	ldr r1, =0x03333333	/* For 16-bit NOR flash */
+	str r1, [r0, #0xc]
+
+	/* MPMC Setup */
+	ldr r0, =NOMADIK_MPMC_BASE
+
+	ldr r1, =0xF00003
+	str r1, [r0]		/* Enable the MPMC and the DLL */
+
+	ldr r1, =0x183
+	str r1, [r0, #0x20]
+
+	ldr r2, =NOMADIK_PMU_BASE
+
+	ldr r1, =0x1111
+	str r1, [r2]
+
+	ldr r1, =0x1111		/* Prog the, mand delay strategy */
+	str r1, [r0, #0x28]
+
+	ldr r1, =0x103		/* NOP ,mand */
+	str r1, [r0, #0x20]
+
+	/* FIXME -- Wait required here */
+
+	ldr r1, =0x103		/* PALL ,mand*/
+	str r1, [r0, #0x20]
+
+	ldr r1, =0x1
+	str r1, [r0, #0x24]	/* To do at least two auto-refresh */
+
+	/* FIXME -- Wait required here */
+
+	/* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */
+	ldr r1, =0x31
+	str r1, [r0, #0x24]
+
+	/* Prog Little Endian, Not defined in 8800 board */
+	ldr r1, =0x0
+	str r1,	[r0, #0x8]
+
+
+	ldr r1, =0x2
+	str r1, [r0, #0x30]		/* Prog tRP timing */
+
+	ldr r1, =0x4			/* Change for 8815 */
+	str r1, [r0, #0x34]		/* Prog tRAS timing */
+
+	ldr r1, =0xB
+	str r1, [r0, #0x38]		/* Prog tSREX timing */
+
+
+	ldr r1, =0x1
+	str r1, [r0, #0x44]		/* Prog tWR timing */
+
+	ldr r1, =0x8
+	str r1, [r0, #0x48]		/* Prog tRC timing */
+
+	ldr r1, =0xA
+	str r1, [r0, #0x4C]		/* Prog tRFC timing */
+
+	ldr r1, =0xB
+	str r1, [r0, #0x50]		/* Prog tXSR timing */
+
+	ldr r1, =0x1
+	str r1, [r0, #0x54]		/* Prog tRRD timing */
+
+	ldr r1, =0x1
+	str r1, [r0, #0x58]		/* Prog tMRD timing */
+
+	ldr r1, =0x1
+	str r1, [r0, #0x5C]		/* Prog tCDLR timing */
+
+	/* DDR-SDRAM MEMORY IS ON BANK0 8815 */
+	ldr r1, =0x304			/* Prog RAS and CAS for CS 0 */
+	str r1, [r0, #0x104]
+
+	/* SDR-SDRAM MEMORY IS ON BANK1 8815 */
+	ldr r1, =0x304			/* Prog RAS and CAS for CS 1 */
+	str r1, [r0, #0x124]
+	/* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */
+	/* DDR-SDRAM MEMORY IS ON BANK0*/
+
+	ldr r1, =0x884			/* 8815 : config reg in BRC for CS0 */
+	str r1, [r0, #0x100]
+
+	/*SDR-SDRAM MEMORY IS ON BANK1*/
+
+	ldr r1, =0x884			/* 8815 : config reg in BRC for CS1 */
+	str r1, [r0, #0x120]
+
+	ldr r1, =0x83			/*MODE Mand*/
+	str r1, [r0, #0x20]
+
+	/* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */
+
+	ldr r1, =0x62000			/*Data in*/
+	ldr r1, [r1]
+
+	/* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */
+
+	ldr r1, =0x8062000
+	ldr r1, [r1]
+
+	ldr r1, =0x003
+	str r1, [r0, #0x20]
+
+	/* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/
+
+	ldr r1, =0x01			/* Enable buffer 0 */
+	str r1, [r0, #0x400]
+
+	ldr r1, =0x01			/* Enable buffer 1 */
+	str r1, [r0, #0x420]
+
+	ldr r1, =0x01			/* Enable buffer 2 */
+	str r1, [r0, #0x440]
+
+	ldr r1, =0x01			/* Enable buffer 3 */
+	str r1, [r0, #0x460]
+
+	ldr r1, =0x01			/* Enable buffer 4 */
+	str r1, [r0, #0x480]
+
+	ldr r1, =0x01			/* Enable buffer 5 */
+	str r1, [r0, #0x4A0]
+
+	/* GPIO settings */
+
+	ldr r0, =NOMADIK_GPIO1_BASE
+
+	ldr r1, =0xC0600000
+	str r1, [r0, #0x20]
+
+	ldr r1, =0x3F9FFFFF		/* ABHI change this for uart1 */
+	str r1, [r0, #0x24]
+
+	ldr r1, =0x3F9FFFFF		/* ABHI change this for uart1 */
+	str r1, [r0, #0x28]
+
+	ldr r0, =NOMADIK_GPIO0_BASE
+
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x20]
+
+	ldr r1, =0x00
+	str r1, [r0, #0x24]
+
+	ldr r1, =0x00
+	str r1, [r0, #0x28]
+
+	/* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */
+
+	ldr r0, =NOMADIK_FSMC_BASE
+
+	ldr r1, =0x10DB			/* INIT FSMC bank 0 */
+	str r1, [r0, #0x00]
+
+	ldr r1, =0x0FFFFFFF
+	str r1, [r0, #0x04]
+
+	ldr r1, =0x010DB		/* INIT FSMC bank 1 */
+	str r1, [r0, #0x08]
+
+	ldr r1, =0x00FFFFFFF
+	str r1, [r0, #0x0C]
+
+	ldr r0, =NOMADIK_UART0_BASE
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x0000004e
+	str r1, [r0, #0x24]
+
+	ldr r1, =0x00000008
+	str r1, [r0, #0x28]
+
+	ldr r1, =0x00000060
+	str r1, [r0, #0x2C]
+
+	ldr r1, =0x00000301
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x00000066
+	str r1, [r0]
+
+	ldr r0, =NOMADIK_UART1_BASE
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x0000004e
+	str r1, [r0, #0x24]
+
+	ldr r1, =0x00000008
+	str r1, [r0, #0x28]
+
+	ldr r1, =0x00000060
+	str r1, [r0, #0x2C]
+
+	ldr r1, =0x00000301
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x00000066
+	str r1, [r0]
+
+	ldr r0, =NOMADIK_UART2_BASE
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x0000004e
+	str r1, [r0, #0x24]
+
+	ldr r1, =0x00000008
+	str r1, [r0, #0x28]
+
+	ldr r1, =0x00000060
+	str r1, [r0, #0x2C]
+
+	ldr r1, =0x00000301
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x00000066
+	str r1, [r0]
+
+	/* Configure CPLD to enable UART0 */
+
+	mov pc, lr
diff --git a/u-boot/board/stx/stxgp3/Makefile b/u-boot/board/stx/stxgp3/Makefile
new file mode 100644
index 0000000..5eccfab
--- /dev/null
+++ b/u-boot/board/stx/stxgp3/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/stx/stxgp3/ddr.c b/u-boot/board/stx/stxgp3/ddr.c
new file mode 100644
index 0000000..93d1100
--- /dev/null
+++ b/u-boot/board/stx/stxgp3/ddr.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/stx/stxgp3/flash.c b/u-boot/board/stx/stxgp3/flash.c
new file mode 100644
index 0000000..61c9602
--- /dev/null
+++ b/u-boot/board/stx/stxgp3/flash.c
@@ -0,0 +1,515 @@
+/*
+ * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC.  <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updated to support the Silicon Tx GP3 8560.  We should only find
+ * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash),
+ * but I left other code here in case people order custom boards.
+ *
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F640C3T:	printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+	value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];             /* device ID            */
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+
+	case (INTEL_ID_28F640C3T):
+		info->flash_id += FLASH_28F640C3T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		sector_offset = 0x20000;
+		break;				/* => 2x8 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table
+	 * The first 127 blocks are large, the last 8 are small.
+	 */
+	for (i = 0; i < 127; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* Sectors are locked upon reset */
+		info->protect[i] = 0;
+	}
+	for (i = 127; i < 135; i++) {
+		info->start[i] = base;
+		base += 0x4000;
+		/* Sectors are locked upon reset */
+		info->protect[i] = 0;
+	}
+
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			asm("sync");
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			asm("sync");
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			asm("sync");
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			asm("sync");
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			asm("sync");
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			    asm("sync");
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if(*addr & 0x00200020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+			asm("sync");
+		}
+	}
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+	asm("sync");
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	asm("sync");
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+	asm("sync");
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+	start = get_timer (0);
+	while((*addr & 0x00800080) != 0x00800080){
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CONFIG_SYS_NO_FLASH */
diff --git a/u-boot/board/stx/stxgp3/law.c b/u-boot/board/stx/stxgp3/law.c
new file mode 100644
index 0000000..af0ac09
--- /dev/null
+++ b/u-boot/board/stx/stxgp3/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xfc00_0000     0xfc00_ffff     Config Latch            64K
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	/* This is not so much the SDRAM map as it is the whole localbus map. */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/stx/stxgp3/stxgp3.c b/u-boot/board/stx/stxgp3/stxgp3.c
new file mode 100644
index 0000000..de22bf5
--- /dev/null
+++ b/u-boot/board/stx/stxgp3/stxgp3.c
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2003, Embedded Edge, LLC
+ * Dan Malek, <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560
+ *
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TxD */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   0,   0   }, /* I2C CLK */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+static	uint64_t	next_led_update;
+static	uint		led_bit;
+
+int
+board_early_init_f(void)
+{
+#if defined(CONFIG_PCI)
+    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void
+reset_phy(void)
+{
+	volatile uint *blatch;
+
+	blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
+
+	/* reset Giga bit Ethernet port if needed here */
+
+	*blatch &= ~0x000000c0;
+	udelay(100);
+	*blatch = 0x000000c1;	/* Light one led, too */
+	udelay(1000);
+
+#if 0	/* This is the port we really want to use for debugging. */
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+#endif
+}
+
+int
+checkboard(void)
+{
+	printf ("Board: Silicon Tx GPPP 8560 Board\n");
+	return (0);
+}
+
+/* Blinkin' LEDS for Robert.
+*/
+void
+show_activity(int flag)
+{
+	volatile uint *blatch;
+
+	if (next_led_update > get_ticks())
+		return;
+
+	blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
+
+	led_bit >>= 1;
+	if (led_bit == 0)
+		led_bit = 0x08;
+	*blatch = (0xc0 | led_bit);
+	eieio();
+	next_led_update += (get_tbclk() / 4);
+}
+
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_stxgp3_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_stxgp3_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/u-boot/board/stx/stxgp3/tlb.c b/u-boot/board/stx/stxgp3/tlb.c
new file mode 100644
index 0000000..aa11a5d
--- /dev/null
+++ b/u-boot/board/stx/stxgp3/tlb.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xfc000000	16K	Configuration Latch register
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16K, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_64M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/stx/stxssa/Makefile b/u-boot/board/stx/stxssa/Makefile
new file mode 100644
index 0000000..6b47ceb
--- /dev/null
+++ b/u-boot/board/stx/stxssa/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/stx/stxssa/ddr.c b/u-boot/board/stx/stxssa/ddr.c
new file mode 100644
index 0000000..93d1100
--- /dev/null
+++ b/u-boot/board/stx/stxssa/ddr.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/* 2T timing enable */
+	popts->twoT_en = 1;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/stx/stxssa/law.c b/u-boot/board/stx/stxssa/law.c
new file mode 100644
index 0000000..e3c34ed
--- /dev/null
+++ b/u-boot/board/stx/stxssa/law.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xfaff_ffff     Local bus               128M
+ * 0xfb00_0000     0xfb00_ffff     Config Latch            64K
+ * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       64M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	/* Map the whole localbus, including flash and reset latch. */
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/stx/stxssa/stxssa.c b/u-boot/board/stx/stxssa/stxssa.c
new file mode 100644
index 0000000..83ffcd2
--- /dev/null
+++ b/u-boot/board/stx/stxssa/stxssa.c
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2005, Embedded Alley Solutions, Inc.
+ * Dan Malek, <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA
+ *
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 TxClav	*/
+	/* PA29 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[0] */
+	/* PA9	*/ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 L1TXD */
+	/* PA8	*/ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 L1RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   1,	 1,   1,   0,	0   }, /* TDM A1 L1RSYNC */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   1,   0,	 0,   0,   0,	0   }, /* FREERUN */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB9	*/ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB8	*/ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
+	/* PB7	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB6	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB5	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB4	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,	 0,   0,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   1,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FETHMDC */
+	/* PC9	*/ {   0,   0,	 0,   0,   0,	0   }, /* FETHMDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC2 TxD */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
+	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
+	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
+	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
+	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
+	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
+	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD18 */
+	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,	 1,   0,   0,	0   }, /* I2C CLK */
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
+	/* PD8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+static	uint64_t	next_led_update;
+static	uint		led_bit;
+
+void
+reset_phy(void)
+{
+	volatile uint *blatch;
+#if 0
+	int	i;
+#endif
+	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
+
+	/* reset Giga bit Ethernet port if needed here */
+
+#if 1
+	*blatch &= ~0x000000c0;
+	udelay(100);
+#else
+	*blatch = 0;
+	asm("eieio");
+	for (i=0; i<1000; i++)
+		udelay(1000);
+#endif
+	*blatch = 0x000000c1;	/* Light one led, too */
+	udelay(1000);
+
+#if 0	/* This is the port we really want to use for debugging. */
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=	FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=	FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+#endif
+}
+
+int
+board_early_init_f(void)
+{
+#if defined(CONFIG_PCI)
+	volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
+
+	pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+
+	/* Why is the phy reset done _after_ the ethernet
+	 * initialization in arch/powerpc/lib/board.c?
+	 * Do it here so it's done before the TSECs are used.
+	 */
+	reset_phy();
+
+	return 0;
+}
+
+int
+checkboard(void)
+{
+	printf ("Board: Silicon Tx GPPP SSA Board\n");
+	return (0);
+}
+
+/* Blinkin' LEDS for Robert.
+*/
+void
+show_activity(int flag)
+{
+	volatile uint *blatch;
+
+	if (next_led_update > get_ticks())
+		return;
+
+	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
+
+	led_bit >>= 1;
+	if (led_bit == 0)
+		led_bit = 0x08;
+	*blatch = (0xc0 | led_bit);
+	eieio();
+	next_led_update += (get_tbclk() / 4);
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_stxgp3_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose[] = {
+#ifndef CONFIG_PCI_PNP
+	{ config_table: pci_stxgp3_config_table,},
+#else
+	{},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/stx/stxssa/tlb.c b/u-boot/board/stx/stxssa/tlb.c
new file mode 100644
index 0000000..0386432
--- /dev/null
+++ b/u-boot/board/stx/stxssa/tlb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	6M4	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xf0000000		Local bus expansion option.
+	 * 0xfb000000		Configuration Latch register (one word)
+	 * 0xfc000000		Up to 64M flash
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/stx/stxxtc/Makefile b/u-boot/board/stx/stxxtc/Makefile
new file mode 100644
index 0000000..ac860c1
--- /dev/null
+++ b/u-boot/board/stx/stxxtc/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/stx/stxxtc/stxxtc.c b/u-boot/board/stx/stxxtc/stxxtc.c
new file mode 100644
index 0000000..4afbbf5
--- /dev/null
+++ b/u-boot/board/stx/stxxtc/stxxtc.c
@@ -0,0 +1,608 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2005
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * U-Boot port on STx XTc board
+ * Mostly copied from Netta
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Silicon Turnkey eXpress XTc\n");
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 9 */
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+	u32 d1, d2;
+
+	upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+
+	d1 = 0xAA55AA55;
+	*(volatile u32 *)0 = d1;
+	d2 = *(volatile u32 *)0;
+	if (d1 != d2) {
+		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+		DO_LOOP;
+	}
+
+	d1 = 0x55AA55AA;
+	*(volatile u32 *)0 = d1;
+	d2 = *(volatile u32 *)0;
+	if (d1 != d2) {
+		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+		DO_LOOP;
+	}
+
+	d1 = 0x12345678;
+	*(volatile u32 *)0 = d1;
+	d2 = *(volatile u32 *)0;
+	if (d1 != d2) {
+		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+		DO_LOOP;
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		miiphy_read("FEC", phyno, MII_PHYSID1, &v);
+		if (v == 0xFFFF)
+			continue;
+		miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
+		udelay(10000);
+		miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	_BW(6)
+#define PA_GP_OUTMASK	(_BW(7))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(7))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	0
+#define PB_GP_OUTMASK	(_B(23))
+#define PB_SP_MASK	0
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(23))
+#define PB_SP_DIRVAL	0
+
+#define PC_GP_INMASK	0
+#define PC_GP_OUTMASK	(_BW(15))
+
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	0
+#define PC_SP_DIRVAL	0
+
+#define PE_GP_INMASK	0
+#define PE_GP_OUTMASK	0
+#define PE_GP_OUTVAL	0
+
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	(void)ioport;
+	(void)cpm;
+#if 1
+	/* NAND chip select */
+	upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
+	memctl->memc_mbmr = 0;	/* all clear */
+#endif
+
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+#if 1
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	reset_phys();
+
+	return 0;
+}
diff --git a/u-boot/board/stx/stxxtc/u-boot.lds b/u-boot/board/stx/stxxtc/u-boot.lds
new file mode 100644
index 0000000..684ab81
--- /dev/null
+++ b/u-boot/board/stx/stxxtc/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text	:
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/stx/stxxtc/u-boot.lds.debug b/u-boot/board/stx/stxxtc/u-boot.lds.debug
new file mode 100644
index 0000000..df7b6ad
--- /dev/null
+++ b/u-boot/board/stx/stxxtc/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/svm_sc8xx/Makefile b/u-boot/board/svm_sc8xx/Makefile
new file mode 100644
index 0000000..6dc495c
--- /dev/null
+++ b/u-boot/board/svm_sc8xx/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/svm_sc8xx/flash.c b/u-boot/board/svm_sc8xx/flash.c
new file mode 100644
index 0000000..db1f21a
--- /dev/null
+++ b/u-boot/board/svm_sc8xx/flash.c
@@ -0,0 +1,797 @@
+/*
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#if 0
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+#endif
+#ifdef  CONFIG_BOOT_8B
+static int my_in_8( unsigned char *addr);
+static  void my_out_8( unsigned char *addr, int val);
+#endif
+#ifdef  CONFIG_BOOT_16B
+static  int my_in_be16( unsigned short *addr);
+static  void my_out_be16( unsigned short *addr, int val);
+#endif
+#ifdef  CONFIG_BOOT_32B
+static  unsigned my_in_be32( unsigned *addr);
+static  void my_out_be32( unsigned *addr, int val);
+#endif
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	size_b0=0;
+	size_b1=0;
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+#ifdef CONFIG_SYS_DOC_BASE
+#ifndef CONFIG_FEL8xx_AT
+	memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */
+	memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401;
+#else
+	memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */
+	memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401;
+#endif
+#endif
+#if defined( CONFIG_BOOT_8B)
+/*        memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */
+/*        memctl->memc_br0 = 0x40000401; */
+	size_b0 = 0x80000;  /* 512 K */
+	flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040;
+	flash_info[0].sector_count = 8;
+	flash_info[0].size = 0x00080000;
+	/* set up sector start address table */
+	for (i = 0; i < flash_info[0].sector_count; i++)
+	flash_info[0].start[i] = 0x40000000 + (i * 0x10000);
+	/* protect all sectors */
+	for (i = 0; i < flash_info[0].sector_count; i++)
+	flash_info[0].protect[i] = 0x1;
+#elif defined (CONFIG_BOOT_16B)
+/*        memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */
+/*        memctl->memc_br0 = 0x40000401; */
+	size_b0 = 0x400000;  /* 4MB , assume AMD29LV320B */
+	flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B;
+	flash_info[0].sector_count = 67;
+	flash_info[0].size = 0x00400000;
+	/* set up sector start address table */
+	flash_info[0].start[0] = 0x40000000  ;
+	flash_info[0].start[1] = 0x40000000 + 0x4000;
+	flash_info[0].start[2] = 0x40000000 + 0x6000;
+	flash_info[0].start[3] = 0x40000000 + 0x8000;
+	for (i = 4; i < flash_info[0].sector_count; i++)
+	flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000);
+	/* protect all sectors */
+	for (i = 0; i < flash_info[0].sector_count; i++)
+	flash_info[0].protect[i] = 0x1;
+#endif
+
+
+#ifdef CONFIG_BOOT_32B
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+
+#endif  /* CONFIG_BOOT_32B */
+
+	return (size_b0 + size_b1);
+}
+#if 0
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+}
+#endif
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#if 0
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect,in_mid,in_did;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#if defined (CONFIG_BOOT_8B )
+	my_out_8( (unsigned char * )  ((ulong)addr+0x555) , 0xaa );
+	my_out_8( (unsigned char * )  ((ulong)addr+0x2aa) , 0x55 );
+	my_out_8( (unsigned char * )  ((ulong)addr+0x555) , 0x90 );
+	in_mid=my_in_8( (unsigned char * ) addr );
+	in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_8( (unsigned char *)addr, 0xf0);
+	udelay(1);
+	my_out_8(     (unsigned char *) ((ulong)addr+0x555),0xaa );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x2aa),0x55 );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x555),0x80 );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x555),0xaa );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x2aa),0x55 );
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			/*addr[0] = 0x00300030; */
+			my_out_8(     (unsigned char *) ((ulong)addr),0x30 );
+			l_sect = sect;
+		}
+	}
+#elif defined(CONFIG_BOOT_16B )
+	my_out_be16( (unsigned short * )  ((ulong)addr+ (0xaaa)) , 0xaa );
+	my_out_be16( (unsigned short * )  ((ulong)addr+ (0x554)) , 0x55 );
+	my_out_be16( (unsigned short * )  ((ulong)addr+ (0xaaa)) , 0x90 );
+	in_mid=my_in_be16( (unsigned short * ) addr );
+	in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_be16( (unsigned short *)addr, 0xf0);
+	udelay(1);
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0xaaa),0xaa );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0x554),0x55 );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0xaaa),0x80 );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0xaaa),0xaa );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0x554),0x55 );
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			my_out_be16(     (unsigned short *) ((ulong)addr),0x30 );
+			l_sect = sect;
+		}
+	}
+
+#elif defined(CONFIG_BOOT_32B)
+	my_out_be32( (unsigned * )  ((ulong)addr+0x1554) , 0xaa );
+	my_out_be32( (unsigned * )  ((ulong)addr+0xaa8) , 0x55 );
+	my_out_be32( (unsigned  *)  ((ulong)addr+0x1554) , 0x90 );
+	in_mid=my_in_be32( (unsigned  * ) addr );
+	in_did=my_in_be32( (unsigned  * ) ((ulong)addr+4) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_be32( (unsigned *)addr, 0xf0);
+	udelay(1);
+	my_out_be32(     (unsigned  *) ((ulong)addr+0x1554),0xaa );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0xaa8),0x55 );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0x1554),0x80 );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0x1554),0xaa );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0xaa8),0x55 );
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			my_out_be32(     (unsigned *) ((ulong)addr),0x00300030 );
+			l_sect = sect;
+		}
+	}
+
+#else
+# error CONFIG_BOOT_(size)B missing.
+#endif
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+#if defined (CONFIG_BOOT_8B)
+	while (  (my_in_8((unsigned char *)addr) & 0x80) != 0x80 )
+#elif defined(CONFIG_BOOT_16B )
+	while (  (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 )
+#elif defined(CONFIG_BOOT_32B)
+	while (  (my_in_be32((unsigned  *)addr) & 0x00800080) != 0x00800080 )
+#else
+# error CONFIG_BOOT_(size)B missing.
+#endif
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#if defined (CONFIG_BOOT_8B)
+	my_out_8( (unsigned char *)addr, 0xf0);
+#elif defined(CONFIG_BOOT_16B )
+	my_out_be16( (unsigned short * ) addr , 0x00f0 );
+#elif defined(CONFIG_BOOT_32B)
+	my_out_be32 ( (unsigned *)addr,  0x00F000F0 );	/* reset bank */
+#else
+# error CONFIG_BOOT_(size)B missing.
+#endif
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong addr = (ulong)(info->start[0]);
+	ulong start,last;
+	int flag;
+	ulong i;
+	int  data_short[2];
+
+	/* Check if Flash is (sufficiently) erased */
+	if ( ((ulong)  *(ulong *)dest & data) != data ) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#if defined(CONFIG_BOOT_8B)
+#ifdef DEBUG
+	{
+	int in_mid,in_did;
+	my_out_8( (unsigned char * )  (addr+0x555) , 0xaa );
+	my_out_8( (unsigned char * )  (addr+0x2aa) , 0x55 );
+	my_out_8( (unsigned char * )  (addr+0x555) , 0x90 );
+	in_mid=my_in_8( (unsigned char * ) addr );
+	in_did=my_in_8( (unsigned char * ) (addr+1) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_8( (unsigned char *)addr, 0xf0);
+	udelay(1);
+	}
+#endif
+      {
+	int  data_ch[4];
+	data_ch[0]=(int ) ((data>>24) & 0xff);
+	data_ch[1]=(int ) ((data>>16) &0xff );
+	data_ch[2]=(int ) ((data >>8) & 0xff);
+	data_ch[3]=(int ) (data & 0xff);
+	for (i=0;i<4;i++ ){
+	  my_out_8( (unsigned char *) (addr+0x555),0xaa);
+	  my_out_8((unsigned char *) (addr+0x2aa),0x55);
+	  my_out_8( (unsigned char *)  (addr+0x555),0xa0);
+	  my_out_8((unsigned char *)  (dest+i) ,data_ch[i]);
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	  start = get_timer (0);
+	last  = start;
+	  while(  ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i]  ) ) {
+		  if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) {
+			  return 1;
+		  }
+	  }
+	}/* for */
+     }
+#elif defined( CONFIG_BOOT_16B)
+	data_short[0]=(int) (data>>16) & 0xffff;
+	data_short[1]=(int ) data & 0xffff ;
+	for (i=0;i<2;i++ ){
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0xaaa),0xaa );
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0x554),0x55 );
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 );
+	my_out_be16(  (unsigned short *) (dest+(i*2)) ,data_short[i]);
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+	  start = get_timer (0);
+	last  = start;
+	  while(  ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i]  ) ) {
+		  if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) {
+			  return 1;
+		  }
+	  }
+	}
+#elif defined( CONFIG_BOOT_32B)
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+#endif
+
+
+	return (0);
+}
+#ifdef  CONFIG_BOOT_8B
+static int my_in_8  ( unsigned char *addr)
+{
+       int ret;
+       __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+       return ret;
+}
+
+static void my_out_8  ( unsigned char *addr, int val)
+{
+       __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#endif
+#ifdef  CONFIG_BOOT_16B
+static int my_in_be16( unsigned short *addr)
+{
+       int ret;
+	__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+				return ret;
+}
+static void my_out_be16( unsigned short *addr, int val)
+{
+       __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#endif
+#ifdef  CONFIG_BOOT_32B
+static  unsigned my_in_be32( unsigned *addr)
+{
+	unsigned ret;
+	__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+				return ret;
+}
+static  void my_out_be32( unsigned *addr, int val)
+{
+       __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#endif
diff --git a/u-boot/board/svm_sc8xx/svm_sc8xx.c b/u-boot/board/svm_sc8xx/svm_sc8xx.c
new file mode 100644
index 0000000..4390e49
--- /dev/null
+++ b/u-boot/board/svm_sc8xx/svm_sc8xx.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+const uint sdram_table[] =
+{
+/*-----------------
+ UPM A contents:
+----------------- */
+/*---------------------------------------------------
+ Read Single Beat Cycle. Offset 0 in the RAM array.
+---------------------------------------------------- */
+0x1f07fc04,  0xeeaefc04,  0x11adfc04,  0xefbbbc00 ,
+0x1ff77c47,  0x1ff77c35,  0xefeabc34,  0x1fb57c35 ,
+/*------------------------------------------------
+ Read Burst Cycle. Offset 0x8 in the RAM array.
+------------------------------------------------ */
+0x1f07fc04,  0xeeaefc04,  0x10adfc04,  0xf0affc00,
+0xf0affc00,  0xf1affc00,  0xefbbbc00,  0x1ff77c47,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff,
+/*-------------------------------------------------------
+ Write Single Beat Cycle. Offset 0x18 in the RAM array
+------------------------------------------------------- */
+0x1f27fc04,  0xeeaebc00,  0x01b93c04,  0x1ff77c47 ,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+/*-------------------------------------------------
+ Write Burst Cycle. Offset 0x20 in the RAM array
+------------------------------------------------- */
+0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+/*------------------------------------------------------------------------
+ Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
+------------------------------------------------------------------------ */
+0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+/*-----------
+*  Exception:
+*  ----------- */
+0x7ffefc07,  0xffffffff,  0xffffffff,  0xffffffff ,
+};
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (SVM8...)
+ *
+ * Return 1 for "SC8xx" type, 0 else.
+ */
+
+int checkboard (void)
+{
+    char *s = getenv("serial#");
+    int board_type;
+
+    if (!s || strncmp(s, "SVM8", 4)) {
+	printf ("### No HW ID - assuming SVM SC8xx\n");
+	return (0);
+    }
+
+    board_type = 1;
+
+    for (; *s; ++s) {
+	if (*s == ' ')
+	    break;
+	putc (*s);
+    }
+
+    putc ('\n');
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0 = 0;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+#if defined (CONFIG_SDRAM_16M)
+	memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx;
+	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
+	udelay(1);
+	memctl->memc_mcr  = 0x80002830;
+	udelay(1);
+	memctl->memc_mar  = 0x00000088;
+	udelay(1);
+	memctl->memc_mcr  = 0x80002106;
+	udelay(1);
+	memctl->memc_or1 =  0xff000a00;
+	size_b0 = 0x01000000;
+#elif defined (CONFIG_SDRAM_32M)
+	memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx;
+	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
+	udelay(1);
+	memctl->memc_mcr  = 0x80002830;
+	udelay(1);
+	memctl->memc_mar  = 0x00000088;
+	udelay(1);
+	memctl->memc_mcr  = 0x80002106;
+	udelay(1);
+	memctl->memc_or1 =  0xfe000a00;
+	size_b0 = 0x02000000;
+#elif defined (CONFIG_SDRAM_64M)
+	memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx;
+	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
+	udelay(1);
+	memctl->memc_mcr  = 0x80002830;
+	udelay(1);
+	memctl->memc_mar  = 0x00000088;
+	udelay(1);
+	memctl->memc_mcr  = 0x80002106;
+	udelay(1);
+	memctl->memc_or1 =  0xfc000a00;
+	size_b0 = 0x04000000;
+#else
+#error SDRAM size configuration missing.
+#endif
+	memctl->memc_br1 =  0x00000081;
+	udelay(200);
+	return (size_b0 );
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+	        doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
diff --git a/u-boot/board/svm_sc8xx/u-boot.lds b/u-boot/board/svm_sc8xx/u-boot.lds
new file mode 100644
index 0000000..6ff4d8c
--- /dev/null
+++ b/u-boot/board/svm_sc8xx/u-boot.lds
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    lib/libgeneric.o			(.text*)
+    net/libnet.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    arch/powerpc/lib/libpowerpc.o	(.text*)
+    board/svm_sc8xx/libsvm_sc8xx.o	(.text*)
+    *(.text.*printf)
+    *(.text.do_mem_*)
+    *(.text.flash*)
+    *(.text.run_command)
+    *(.text.main_loop)
+    *(.text.srec_decode)
+
+    . = env_offset;
+    common/env_embedded.o		(.ppcenv*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/svm_sc8xx/u-boot.lds.debug b/u-boot/board/svm_sc8xx/u-boot.lds.debug
new file mode 100644
index 0000000..f212fab
--- /dev/null
+++ b/u-boot/board/svm_sc8xx/u-boot.lds.debug
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/sx1/Makefile b/u-boot/board/sx1/Makefile
new file mode 100644
index 0000000..27d85b0
--- /dev/null
+++ b/u-boot/board/sx1/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sx1.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/sx1/config.mk b/u-boot/board/sx1/config.mk
new file mode 100644
index 0000000..441bea2
--- /dev/null
+++ b/u-boot/board/sx1/config.mk
@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# SX1 board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# SX1 has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/u-boot/board/sx1/lowlevel_init.S b/u-boot/board/sx1/lowlevel_init.S
new file mode 100644
index 0000000..c1a811a
--- /dev/null
+++ b/u-boot/board/sx1/lowlevel_init.S
@@ -0,0 +1,397 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	 /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr	r0, REG_PULL_DWN_CTRL_0
+	ldr	r1, VAL_PULL_DWN_CTRL_0
+	str	r1, [r0]
+	ldr	r0, REG_PULL_DWN_CTRL_1
+	ldr	r1, VAL_PULL_DWN_CTRL_1
+	str	r1, [r0]
+	ldr	r0, REG_PULL_DWN_CTRL_2
+	ldr	r1, VAL_PULL_DWN_CTRL_2
+	str	r1, [r0]
+	ldr	r0, REG_PULL_DWN_CTRL_3
+	ldr	r1, VAL_PULL_DWN_CTRL_3
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_4
+	ldr	r1, VAL_FUNC_MUX_CTRL_4
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_5
+	ldr	r1, VAL_FUNC_MUX_CTRL_5
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_6
+	ldr	r1, VAL_FUNC_MUX_CTRL_6
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_7
+	ldr	r1, VAL_FUNC_MUX_CTRL_7
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_8
+	ldr	r1, VAL_FUNC_MUX_CTRL_8
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_9
+	ldr	r1, VAL_FUNC_MUX_CTRL_9
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_A
+	ldr	r1, VAL_FUNC_MUX_CTRL_A
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_B
+	ldr	r1, VAL_FUNC_MUX_CTRL_B
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_C
+	ldr	r1, VAL_FUNC_MUX_CTRL_C
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_D
+	ldr	r1, VAL_FUNC_MUX_CTRL_D
+	str	r1, [r0]
+	ldr	r0, REG_VOLTAGE_CTRL_0
+	ldr	r1, VAL_VOLTAGE_CTRL_0
+	str	r1, [r0]
+	ldr	r0, REG_TEST_DBG_CTRL_0
+	ldr	r1, VAL_TEST_DBG_CTRL_0
+	str	r1, [r0]
+	ldr	r0, REG_MOD_CONF_CTRL_0
+	ldr	r1, VAL_MOD_CONF_CTRL_0
+	str	r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr	r0, REG_COMP_MODE_CTRL_0
+	ldr	r1, VAL_COMP_MODE_CTRL_0
+	str	r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]	    /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	ldr r0, _GPIO_PIN_CONTROL_REG
+	mov r1,#0
+	orr r1, r1, #0x0001 /* M_PCM_SYNC */
+	orr r1, r1, #0x4000 /* IPC_ACTIVE */
+	strh r1,[r0]
+
+	ldr r0, _GPIO_DIR_CONTROL_REG
+	mov r1,#0
+	bic r1, r1, #0x0001 /* M_PCM_SYNC */
+	bic r1, r1, #0x4000 /* IPC_ACTIVE */
+	strh r1,[r0]
+
+	ldr r0, _GPIO_DATA_OUTPUT_REG
+	mov r1,#0
+	bic r1, r1, #0x0001 /* M_PCM_SYNC */
+	orr r1, r1, #0x4000 /* IPC_ACTIVE */
+	strh r1,[r0]
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end	    /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b		    /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000		    /* Load physical SDRAM base. */
+	mov r1, pc			    /* Get current execution location. */
+	cmp r1, r0			    /* Compare. */
+	bge skip_sdram			    /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800			       /* value should be checked */
+3:
+	subs r3, r3, #0x1		      /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC		    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000		    /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000		    /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]			    /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS	    /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS	    /* Point to MRS register. */
+	str r1, [r2]			    /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]			    /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1			    /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* SX1 specific */
+_GPIO_PIN_CONTROL_REG:
+	.word GPIO_PIN_CONTROL_REG
+_GPIO_DIR_CONTROL_REG:
+	.word GPIO_DIR_CONTROL_REG
+_GPIO_DATA_OUTPUT_REG:
+	.word GPIO_DATA_OUTPUT_REG
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00001000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x00001240       /*[Knoller]  Value of Symbian Image Wing B2*/
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x00201008
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00001000
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09008001       /*[Knoller]  Value of Symbian Image Wing B2*/
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0xfffeffff
+VAL_PULL_DWN_CTRL_1:
+	.word 0xd1ffffec
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffa80c5b
+VAL_PULL_DWN_CTRL_3:
+	.word 0xffffc0fe
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
+	 * says to write a 7.  Don't know what the right thing is to do, so
+	 * I'm leaving it at 7 since that's what was already here.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0da20000       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_ARM_CKCTL:
+	.word 0x010D
+
+VAL_DPLL1_CTL:
+	.word 0x3A33   /*[Hertle] Value of Symbian Image*/
+
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00213090       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00215070       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x0105f0b4       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027       /*[Knoller]  Value of Symbian Image Wing B2*/
diff --git a/u-boot/board/sx1/sx1.c b/u-boot/board/sx1/sx1.c
new file mode 100644
index 0000000..aaef76e
--- /dev/null
+++ b/u-boot/board/sx1/sx1.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of SX1 Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SX1;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.	 However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	unsigned int regval;
+
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+	if (regval & 0x0002) {
+		regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+		/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+		/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+		/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+	}
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/u-boot/board/syteco/jadecpu/Makefile b/u-boot/board/syteco/jadecpu/Makefile
new file mode 100644
index 0000000..30818d2
--- /dev/null
+++ b/u-boot/board/syteco/jadecpu/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= jadecpu.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/syteco/jadecpu/config.mk b/u-boot/board/syteco/jadecpu/config.mk
new file mode 100644
index 0000000..617603d
--- /dev/null
+++ b/u-boot/board/syteco/jadecpu/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x10000000
diff --git a/u-boot/board/syteco/jadecpu/jadecpu.c b/u-boot/board/syteco/jadecpu/jadecpu.c
new file mode 100644
index 0000000..69476f8
--- /dev/null
+++ b/u-boot/board/syteco/jadecpu/jadecpu.c
@@ -0,0 +1,177 @@
+/*
+ * (c) 2010 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mb86r0x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
+					MB86R0x_CCNT_BASE;
+
+	/* We select mode 0 for group 2 and mode 1 for group 4 */
+	writel(0x00000010, &ccnt->cmux_md);
+
+	gd->flags = 0;
+	gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
+	gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
+
+	icache_enable();
+
+	return 0;
+}
+
+static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
+				unsigned long pwm_base)
+{
+	struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+					MB86R0x_GPIO_BASE;
+	struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
+	const char *e;
+
+	writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
+
+	e = getenv(pwm_opts);
+	if (e != NULL) {
+		const char *s;
+		uint32_t freq, init;
+
+		freq = 0;
+		init = 0;
+
+		s = strchr(e, 'f');
+		if (s != NULL)
+			freq = simple_strtol(s + 2, NULL, 0);
+
+		s = strchr(e, 'i');
+		if (s != NULL)
+			init = simple_strtol(s + 2, NULL, 0);
+
+		if (freq > 0) {
+			writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
+				&pwm->bcr);
+			writel(1002, &pwm->tpr);
+			writel(1, &pwm->pr);
+			writel(init * 10 + 1, &pwm->dr);
+			writel(1, &pwm->cr);
+			writel(1, &pwm->sr);
+		}
+	}
+}
+
+int board_late_init(void)
+{
+	struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+					MB86R0x_GPIO_BASE;
+	uint32_t in_word;
+
+#ifdef CONFIG_VIDEO_MB86R0xGDC
+	/* Check if we have valid display settings and turn on power if so */
+	/* Display 0 */
+	if (getenv("gs_dsp_0_param") || getenv("videomode"))
+		setup_display_power((1 << 3), "gs_dsp_0_pwm",
+					MB86R0x_PWM0_BASE);
+
+	/* The corresponding GPIO is always an output */
+	writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
+
+	/* Display 1 */
+	if (getenv("gs_dsp_1_param") || getenv("videomode1"))
+		setup_display_power((1 << 4), "gs_dsp_1_pwm",
+					MB86R0x_PWM1_BASE);
+
+	/* The corresponding GPIO is always an output */
+	writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
+#endif /* CONFIG_VIDEO_MB86R0xGDC */
+
+	/* 5V enable */
+	writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
+	writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
+
+	/* We have special boot options if told by GPIOs */
+	in_word = readl(&gpio->gpdr1);
+
+	if ((in_word & 0xC0) == 0xC0) {
+		setenv("stdin", "serial");
+		setenv("stdout", "serial");
+		setenv("stderr", "serial");
+		setenv("preboot", "run gs_slow_boot");
+	} else if ((in_word & 0xC0) != 0) {
+		setenv("stdout", "vga");
+		setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;"
+			"fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
+			"bootelf 0x40000000; bootelf 0x10080000");
+		setenv("preboot", "run gs_slow_boot");
+	} else {
+		setenv("stdin", "serial");
+		setenv("stdout", "serial");
+		setenv("stderr", "serial");
+		if (getenv("gs_devel")) {
+			setenv("preboot", "run gs_slow_boot");
+		} else {
+			setenv("gs_bootcmd", "bootelf 0x10080000");
+			setenv("preboot", "run gs_fast_boot");
+		}
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+					PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/syteco/jadecpu/lowlevel_init.S b/u-boot/board/syteco/jadecpu/lowlevel_init.S
new file mode 100644
index 0000000..5ad4dce
--- /dev/null
+++ b/u-boot/board/syteco/jadecpu/lowlevel_init.S
@@ -0,0 +1,265 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/mb86r0x.h>
+#include <asm/arch/asm-offsets.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+/*
+ * Initialize Clock Reset Generator (CRG)
+ */
+
+	ldr		r0, =MB86R0x_CRG_BASE
+
+	/* Not change the initial value that is set by external pin.*/
+WAIT_PLL:
+	ldr		r2, [r0, #CRG_CRPR]	/* Wait for PLLREADY */
+	tst		r2, #MB86R0x_CRG_CRPR_PLLRDY
+	beq		WAIT_PLL
+
+	/* Set clock gate control */
+	ldr		r1, =CONFIG_SYS_CRG_CRHA_INIT
+	str		r1, [r0, #CRG_CRHA]
+	ldr		r1, =CONFIG_SYS_CRG_CRPA_INIT
+	str		r1, [r0, #CRG_CRPA]
+	ldr		r1, =CONFIG_SYS_CRG_CRPB_INIT
+	str		r1, [r0, #CRG_CRPB]
+	ldr		r1, =CONFIG_SYS_CRG_CRHB_INIT
+	str		r1, [r0, #CRG_CRHB]
+	ldr		r1, =CONFIG_SYS_CRG_CRAM_INIT
+	str		r1, [r0, #CRG_CRAM]
+
+/*
+ * Initialize External Bus Interface
+ */
+	ldr		r0, =MB86R0x_MEMC_BASE
+
+	ldr		r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
+	str		r1, [r0, #MEMC_MCFMODE0]
+	ldr		r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
+	str		r1, [r0, #MEMC_MCFMODE2]
+	ldr		r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
+	str		r1, [r0, #MEMC_MCFMODE4]
+
+	ldr		r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
+	str		r1, [r0, #MEMC_MCFTIM0]
+	ldr		r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
+	str		r1, [r0, #MEMC_MCFTIM2]
+	ldr		r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
+	str		r1, [r0, #MEMC_MCFTIM4]
+
+	ldr		r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
+	str		r1, [r0, #MEMC_MCFAREA0]
+	ldr		r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
+	str		r1, [r0, #MEMC_MCFAREA2]
+	ldr		r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
+	str		r1, [r0, #MEMC_MCFAREA4]
+
+/*
+ * Initialize DDR2 Controller
+ */
+
+	/* Wait for PLL LOCK up time or more */
+	wait_timer	20
+
+	/*
+	 * (2) Initialize DDRIF
+	 */
+	ldr	r0, =MB86R0x_DDR2_BASE
+	ldr	r1, =CONFIG_SYS_DDR2_DRIMS_INIT
+	strh	r1, [r0, #DDR2_DRIMS]
+
+	/*
+	 * (3) Wait for 20MCKPs(120nsec) or more
+	 */
+	wait_timer	20
+
+	/*
+	 * (4) IRESET/IUSRRST release
+	 */
+	ldr	r0, =MB86R0x_CCNT_BASE
+	ldr	r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
+	str	r1, [r0, #CCNT_CDCRC]
+
+	/*
+	 * (5) Wait for 20MCKPs(120nsec) or more
+	 */
+	wait_timer	20
+
+	/*
+	 * (6) IDLLRST release
+	 */
+	ldr	r0, =MB86R0x_CCNT_BASE
+	ldr	r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
+	str	r1, [r0, #CCNT_CDCRC]
+
+	/*
+	 * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
+	 */
+	wait_timer	33536
+
+	/*
+	 * (9) MCKE ON
+	 */
+	ldr	r0, =MB86R0x_DDR2_BASE
+	ldr	r1, =CONFIG_SYS_DDR2_DRIC1_INIT
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_DRIC2_INIT
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =CONFIG_SYS_DDR2_DRCA_INIT
+	strh	r1, [r0, #DDR2_DRCA]
+	ldr	r1, =MB86R0x_DDR2_DRCI_INIT
+	strh	r1, [r0, #DDR2_DRIC]
+
+	/*
+	 * (10) Initialize SDRAM
+	 */
+
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	wait_timer	67			/* 400ns wait */
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	wait_timer 200
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	wait_timer	18			/* 105ns wait */
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	wait_timer	200			/* MRS to OCD: 200clock */
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
+	strh	r1, [r0, #DDR2_DRIC1]
+	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
+	strh	r1, [r0, #DDR2_DRIC2]
+	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
+	strh	r1, [r0, #DDR2_DRIC]
+
+	ldr	r1, =CONFIG_SYS_DDR2_DRCM_INIT
+	strh	r1, [r0, #DDR2_DRCM]
+
+	ldr	r1, =CONFIG_SYS_DDR2_DRCST1_INIT
+	strh	r1, [r0, #DDR2_DRCST1]
+
+	ldr	r1, =CONFIG_SYS_DDR2_DRCST2_INIT
+	strh	r1, [r0, #DDR2_DRCST2]
+
+	ldr	r1, =CONFIG_SYS_DDR2_DRCR_INIT
+	strh	r1, [r0, #DDR2_DRCR]
+
+	ldr	r1, =CONFIG_SYS_DDR2_DRCF_INIT
+	strh	r1, [r0, #DDR2_DRCF]
+
+	ldr	r1, =CONFIG_SYS_DDR2_DRASR_INIT
+	strh	r1, [r0, #DDR2_DRASR]
+
+	/*
+	 * (11) ODT setting
+	 */
+	ldr	r1, =CONFIG_SYS_DDR2_DROBS_INIT
+	strh	r1, [r0, #DDR2_DROBS]
+	ldr	r1, =CONFIG_SYS_DDR2_DROABA_INIT
+	strh	r1, [r0, #DDR2_DROABA]
+	ldr	r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
+	strh	r1, [r0, #DDR2_DRIBSODT1]
+
+	/*
+	 * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
+	 */
+	ldr	r1, =CONFIG_SYS_DDR2_DROS_INIT
+	strh	r1, [r0, #DDR2_DROS]
+	ldr	r1, =MB86R0x_DDR2_DRCI_NORMAL
+	strh	r1, [r0, #DDR2_DRIC]
+
+	mov pc, lr
diff --git a/u-boot/board/t3corp/Makefile b/u-boot/board/t3corp/Makefile
new file mode 100644
index 0000000..4211b7b
--- /dev/null
+++ b/u-boot/board/t3corp/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	:= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB) $(SOBJS)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/t3corp/chip_config.c b/u-boot/board/t3corp/chip_config.c
new file mode 100644
index 0000000..98ab49f
--- /dev/null
+++ b/u-boot/board/t3corp/chip_config.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"600-67", "CPU: 600 PLB: 200 OPB:  67 EBC:  67",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
+		{
+			0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
+			0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066", "CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/u-boot/board/t3corp/config.mk b/u-boot/board/t3corp/config.mk
new file mode 100644
index 0000000..e893fee
--- /dev/null
+++ b/u-boot/board/t3corp/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/t3corp/init.S b/u-boot/board/t3corp/init.S
new file mode 100644
index 0000000..a24d6f3
--- /dev/null
+++ b/u-boot/board/t3corp/init.S
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ */
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
+		 CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
+		 AC_RWX | SA_G)
+#endif
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
+		 AC_RW | SA_IG)
+
+	/* PCIe UTL register */
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
+
+	/* TLB-entry for FPGA(s) */
+	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+		 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
+		 AC_RW | SA_IG)
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+		 AC_RWX | SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
+		 CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
+
+	tlbtab_end
diff --git a/u-boot/board/t3corp/t3corp.c b/u-boot/board/t3corp/t3corp.c
new file mode 100644
index 0000000..f2853e4
--- /dev/null
+++ b/u-boot/board/t3corp/t3corp.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <mtd/cfi_flash.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+
+int board_early_init_f(void)
+{
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0x7fffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * enable GPIO 49-63
+	 * UART0: 4 pins
+	 */
+	mtsdr(SDR0_PFC0, 0x00007fff);
+	mtsdr(SDR0_PFC1, 0x00040000);
+
+	/* Enable PCI host functionality in SDR0_PCI0 */
+	mtsdr(SDR0_PCI0, 0xe0000000);
+
+	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: T3CORP");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
+	 * boot EBC mapping only supports a maximum of 16MBytes
+	 * (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the flash has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfn00.0000 -> 4.cn00.0000
+	 */
+
+	/* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
+	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
+	      EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+		    CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR flash at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+	u32 eth_cfg;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	/* disable SGMII mode */
+	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+		     SDR0_ETH_CFG_SGMII1_ENABLE |
+		     SDR0_ETH_CFG_SGMII0_ENABLE);
+	/* Set the for 2 RGMII mode */
+	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
+
+int board_pcie_last(void)
+{
+	/*
+	 * Only PCIe0 for now, PCIe1 hangs on this board
+	 */
+	return 0;
+}
+
+/*
+ * Board specific WRDTR and CLKTR values used by the auto-
+ * calibration code (4xx_ibm_ddr2_autocalib.c).
+ */
+static struct sdram_timing board_scan_options[] = {
+	{1, 2},
+	{-1, -1}
+};
+
+struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
+{
+	return board_scan_options;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ *
+ * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
+ * can only be read correctly in 16bit mode. We need to emulate
+ * 8bit and 32bit reads here in the board specific code.
+ */
+u8 flash_read8(void *addr)
+{
+	u16 val = __raw_readw((void *)((u32)addr & ~1));
+
+	if ((u32)addr & 1)
+		return val;
+
+	return val >> 8;
+}
+
+u32 flash_read32(void *addr)
+{
+	return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
+}
+
+void flash_cmd_reset(flash_info_t *info)
+{
+	/*
+	 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+	 * needs the Spansion type reset commands. The other flash chip
+	 * is located behind a FPGA (Xilinx DS617) and needs the Intel type
+	 * reset command.
+	 */
+	if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+		flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+	else
+		flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
diff --git a/u-boot/board/tb0229/Makefile b/u-boot/board/tb0229/Makefile
new file mode 100644
index 0000000..76f1664
--- /dev/null
+++ b/u-boot/board/tb0229/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o vr4131-pci.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tb0229/config.mk b/u-boot/board/tb0229/config.mk
new file mode 100644
index 0000000..017511d
--- /dev/null
+++ b/u-boot/board/tb0229/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# ROM version
+CONFIG_SYS_TEXT_BASE = 0xBFC00000
+
+# RAM version
+#CONFIG_SYS_TEXT_BASE = 0x80400000
diff --git a/u-boot/board/tb0229/flash.c b/u-boot/board/tb0229/flash.c
new file mode 100644
index 0000000..75d7769
--- /dev/null
+++ b/u-boot/board/tb0229/flash.c
@@ -0,0 +1,1198 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+
+#ifdef CONFIG_SYS_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define	FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t * info, ulong dest, ushort data);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE,
+				&flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+#if 0				/* sand: */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM - monitor_flash_len +
+				      size_b0,
+				      FLASH_BASE0_PRELIM - 1 + size_b0,
+				      &flash_info[0]);
+#else
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CONFIG_SYS_MONITOR_BASE,
+				      CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[0]);
+#endif
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	}
+#ifdef CONFIG_SYS_FLASH_BASE_2
+	/* 2 banks */
+	else {
+		size_b1 =
+			flash_get_size ((volatile FLASH_WORD_SIZE *)
+					CONFIG_SYS_FLASH_BASE_2, &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr (EBC0_CFGADDR, PB0CR);
+			pbcr = mfdcr (EBC0_CFGDATA);
+			mtdcr (EBC0_CFGADDR, PB0CR);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr (EBC0_CFGDATA, pbcr);
+			/*          printf("PB1CR = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr (EBC0_CFGADDR, PB1CR);
+			pbcr = mfdcr (EBC0_CFGDATA);
+			mtdcr (EBC0_CFGADDR, PB1CR);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr (EBC0_CFGDATA, pbcr);
+			/*            printf("PB0CR = %x\n", pbcr); */
+		}
+
+		size_b0 =
+			flash_get_size ((volatile FLASH_WORD_SIZE *) base_b0,
+					&flash_info[0]);
+
+		flash_get_offsets (base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+#if 0				/* sand: */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM - monitor_flash_len +
+				      size_b0,
+				      FLASH_BASE0_PRELIM - 1 + size_b0,
+				      &flash_info[0]);
+#else
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CONFIG_SYS_MONITOR_BASE,
+				      CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[0]);
+#endif
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+				flash_get_size ((volatile FLASH_WORD_SIZE *)
+						base_b1, &flash_info[1]);
+
+			flash_get_offsets (base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void) flash_protect (FLAG_PROTECT_SET,
+					      base_b1 + size_b1 -
+					      monitor_flash_len,
+					      base_b1 + size_b1 - 1,
+					      &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void) flash_protect (FLAG_PROTECT_CLEAR,
+					      base_b0 + size_b0 -
+					      monitor_flash_len,
+					      base_b0 + size_b0 - 1,
+					      &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+#endif
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] =
+				base + (i * info->size / info->sector_count);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[] = ", bottom boot sect)\n";
+	uchar topboot[] = ", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	if (info->flash_id & 0x0001) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800B:
+		printf ("INTEL28F800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800T:
+		printf ("INTEL28F800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160B:
+		printf ("INTEL28F160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160T:
+		printf ("INTEL28F160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320B:
+		printf ("INTEL28F320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320T:
+		printf ("INTEL28F320T (32 Mbit%s", boottype);
+		break;
+
+#if 0				/* enable when devices are available */
+
+	case FLASH_INTEL640B:
+		printf ("INTEL28F640B (64 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL640T:
+		printf ("INTEL28F640T (64 Mbit%s", boottype);
+		break;
+#endif
+	case FLASH_28F320J3A:
+		printf ("INTEL28F320J3A (32 Mbit%s", boottype);
+		break;
+	case FLASH_28F640J3A:
+		printf ("INTEL28F640J3A (64 Mbit%s", boottype);
+		break;
+	case FLASH_28F128J3A:
+		printf ("INTEL28F128J3A (128 Mbit%s", boottype);
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
+{
+	short i;
+	ulong base = (ulong) addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if (addr[0x0000] != 0x00890089) {
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if (addr[0x0000] != 0x0089) {
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+
+	}
+
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0				/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+#if 0				/* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+#endif
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;		/* => 32 MBit   */
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 64 MBit   */
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 128 MBit          */
+
+	default:
+		/* FIXME */
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	flash_get_offsets (base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
+#ifndef CONFIG_SYS_FLASH_16BIT
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+#else
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+#endif
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->
+								     start
+								     [sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
+
+
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
+#ifndef CONFIG_SYS_FLASH_16BIT
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00500050;
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
+				}
+#else
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0050;	/* clear status register */
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
+#endif
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+#ifndef CONFIG_SYS_FLASH_16BIT
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+#else
+			addr[0] = (0x00FF & FLASH_ID_MASK);	/* reset bank */
+#endif
+		}
+
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+
+/*int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+										ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
+/*		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+*/ /* finally write data to flash */
+/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+#ifndef CONFIG_SYS_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CONFIG_SYS_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i = 0; i < 2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_short (info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CONFIG_SYS_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+#if defined (__MIPSEL__)
+	data = cpu_to_be32 (data);
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+
+	*((vu_long *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+
+		while ((*((vu_long *) dest) & 0x00800080) !=
+		       (data & 0x00800080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				printf ("timeout\n");
+				return (1);
+			}
+		}
+
+	} else {
+
+		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				printf ("timeout\n");
+				return (1);
+			}
+		}
+
+		if (addr[0] & 0x003A003A) {	/* check for error */
+			barf = addr[0] & 0x003A0000;
+			if (barf) {
+				barf >>= 16;
+			} else {
+				barf = addr[0] & 0x0000003A;
+			}
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+
+
+	}
+
+	return (0);
+}
+
+#else
+
+static int write_short (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+#if defined (__MIPSEL__)
+	data = cpu_to_be16 (data);
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+		/* intel stuff */
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		if (addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		*addr = 0x00FF;
+
+	}
+
+	return (0);
+
+}
+#endif
diff --git a/u-boot/board/tb0229/lowlevel_init.S b/u-boot/board/tb0229/lowlevel_init.S
new file mode 100644
index 0000000..5fce856
--- /dev/null
+++ b/u-boot/board/tb0229/lowlevel_init.S
@@ -0,0 +1,70 @@
+/*
+ *  Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ *  Copyright (c) 2003  Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <asm/regdef.h>
+
+
+	.globl  lowlevel_init
+lowlevel_init:
+
+	/* BCUCNTREG1 = 0x0040 */
+	la	t0, 0xaf000000
+	li	t1, 0x0040
+	sh	t1, 0(t0)
+
+	/* ROMSIZEREG = 0x3333 */
+	la	t0, 0xaf000004
+	li	t1, 0x3333
+	sh	t1, 0(t0)
+
+	/* ROMSPEEDREG = 0x3003 */
+	la	t0, 0xaf000006
+	li	t1, 0x3003
+	sh	t1, 0(t0)
+
+	/* BCUCNTREG3 = 0 */
+	la	t0, 0xaf000016
+	li	t1, 0x0000
+	sh	t1, 0(t0)
+
+	/* CMUCLKMSK */
+	la	t0, 0xaf000060
+	li	t1, 0x39a2
+	sh	t1, 0(t0)
+
+	/* PMUCNTREG */
+	la	t0, 0xaf0000c2
+	li	t1, 0x0006
+	sh	t1, 0(t0)
+
+	/* SDRAMMODEREG = 0x8029 */
+	la	t0, 0xaf000400
+	li	t1, 0x8029
+	sh	t1, 0(t0)
+
+	/* SDRAMCNTREG = 0x2322 */
+	la	t0, 0xaf000402
+	li	t1, 0x2322
+	sh	t1, 0(t0)
+
+	/* BCURFCNTREG = 0x0106 */
+	la	t0, 0xaf000404
+	li	t1, 0x0106
+	sh	t1, 0(t0)
+
+	/* RAMSZEREG = 0x5555 (64MB Bank) */
+	la	t0, 0xaf000408
+	li	t1, 0x5555
+	sh	t1, 0(t0)
+
+	j       ra
+	nop
diff --git a/u-boot/board/tb0229/tb0229.c b/u-boot/board/tb0229/tb0229.c
new file mode 100644
index 0000000..d3f05b2
--- /dev/null
+++ b/u-boot/board/tb0229/tb0229.c
@@ -0,0 +1,53 @@
+/*
+ * Board initialize code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/reboot.h>
+#include <pci.h>
+
+void _machine_restart(void)
+{
+	void (*f)(void) = (void *) 0xbfc00000;
+
+	f();
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+
+void pci_init_board (void)
+{
+	init_vr4131_pci(&hose);
+}
+#endif
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size (CONFIG_SYS_SDRAM_BASE, 0x8000000);
+}
+
+int checkboard (void)
+{
+	printf("Board: TANBAC TB0229 ");
+	printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+
+	set_io_port_base(0);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/tb0229/u-boot.lds b/u-boot/board/tb0229/u-boot.lds
new file mode 100644
index 0000000..56d7c25
--- /dev/null
+++ b/u-boot/board/tb0229/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}
diff --git a/u-boot/board/tb0229/vr4131-pci.c b/u-boot/board/tb0229/vr4131-pci.c
new file mode 100644
index 0000000..6ff4293
--- /dev/null
+++ b/u-boot/board/tb0229/vr4131-pci.c
@@ -0,0 +1,254 @@
+/*
+ * VR4131 PCIU support code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/addrspace.h>
+
+#define VR4131_PCIMMAW1REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG		(volatile unsigned int *)(CKSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG	(volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d04)
+#define VR4131_REVREG		(volatile unsigned int *)(CKSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG		(volatile unsigned int *)(CKSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG	(volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG	(volatile unsigned int *)(CKSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG	(volatile unsigned int *)(CKSEG1 + 0x0f000d18)
+
+/*#define VR41XX_PCIIRQ_OFFSET    (VR41XX_IRQ_MAX + 1)	*/
+/*#define VR41XX_PCIIRQ_MAX       (VR41XX_IRQ_MAX + 12)	*/
+/*#define VR4122_PCI_HOST_BASE    0xa0000000		*/
+
+volatile unsigned int *pciconfigaddr;
+volatile unsigned int *pciconfigdata;
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+/*
+ *	Access PCI Configuration Register for VR4131
+ */
+
+static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
+				     u32 * data)
+{
+	u32 bus;
+	u32 device;
+
+	bus = ((dev & 0xff0000) >> 16);
+	device = ((dev & 0xf800) >> 11);
+
+	if (bus == 0) {
+		/* Type 0 Configuration */
+		*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
+	} else {
+		/* Type 1 Configuration */
+		*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
+	}
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		*VR4131_PCICONFDREG = *data;
+	} else {
+		*data = *VR4131_PCICONFDREG;
+	}
+
+	return (0);
+}
+
+static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+{
+	u32 data;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+{
+	u32 data;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xffff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
+					 u32 * val)
+{
+	u32 data = 0;
+
+	if (reg & 3)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = data;
+
+	return (0);
+}
+
+static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+{
+	u32 data = 0;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
+						       ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+
+static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+{
+	u32 data = 0;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
+							 ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+{
+	u32 data;
+
+	if (reg & 3) {
+		return -1;
+	}
+
+	data = val;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return (0);
+}
+
+
+/*
+ *	Initialize VR4131 PCIU
+ */
+
+vr4131_pciu_init ()
+{
+	/* PCI clock */
+	*VR4131_PCICLKSELREG = 0x00000002;
+
+	/* PCI memory and I/O space */
+	*VR4131_PCIMMAW1REG = 0x100F9010;
+	*VR4131_PCIMMAW2REG = 0x140FD014;
+	*VR4131_PCIMIOAWREG = 0x160FD000;
+
+	/* Target memory window */
+	*VR4131_PCITAW1REG = 0x00081000;	/* 64MB */
+	*VR4131_PCITAW2REG = 0x00000000;
+
+	*VR4131_MAILBAREG = 0UL;
+	*VR4131_PCIMBA1REG = 0UL;
+
+	*VR4131_PCITRDYREG = 0x00008004;
+
+	*VR4131_PCIENREG = 0x00000004;	/* PCI enable */
+	*VR4131_COMMANDREG = 0x02000007;
+}
+
+/*
+ *	Initialize Module
+ */
+
+void init_vr4131_pci (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	vr4131_pciu_init ();	/* Initialize VR4131 PCIU */
+
+	/* PCI memory space #1 */
+	pci_set_region (hose->regions + 0,
+			0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
+
+	/* PCI memory space #2 */
+	pci_set_region (hose->regions + 1,
+			0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
+
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 2,
+			0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region (hose->regions + 3,
+			0x00000000,
+			0x80000000,
+			0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 4;
+
+	hose->read_byte = vr4131_pci_read_config_byte;
+	hose->read_word = vr4131_pci_read_config_word;
+	hose->read_dword = vr4131_pci_read_config_dword;
+	hose->write_byte = vr4131_pci_write_config_byte;
+	hose->write_word = vr4131_pci_write_config_word;
+	hose->write_dword = vr4131_pci_write_config_dword;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+
+	return;
+}
diff --git a/u-boot/board/tcm-bf518/Makefile b/u-boot/board/tcm-bf518/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/u-boot/board/tcm-bf518/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tcm-bf518/config.mk b/u-boot/board/tcm-bf518/config.mk
new file mode 100644
index 0000000..9a54dbf
--- /dev/null
+++ b/u-boot/board/tcm-bf518/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf518-0.0
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/tcm-bf518/tcm-bf518.c b/u-boot/board/tcm-bf518/tcm-bf518.c
new file mode 100644
index 0000000..5964059
--- /dev/null
+++ b/u-boot/board/tcm-bf518/tcm-bf518.c
@@ -0,0 +1,78 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+#include <asm/sdh.h>
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix TCM-BF518 board\n");
+	printf("       Support: http://www.bluetechnix.com/\n");
+	printf("                http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	bool valid_mac = false;
+
+#if 0
+	/* the MAC is stored in OTP memory page 0xDF */
+	uint32_t ret;
+	uint64_t otp_mac;
+
+	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+	if (!(ret & OTP_MASTER_ERROR)) {
+		uchar *otp_mac_p = (uchar *)&otp_mac;
+
+		for (ret = 0; ret < 6; ++ret)
+			mac_addr[ret] = otp_mac_p[5 - ret];
+
+		if (is_valid_ether_addr(mac_addr))
+			valid_mac = true;
+	}
+#endif
+
+	if (!valid_mac) {
+		puts("Warning: Generating 'random' MAC address\n");
+		bfin_gen_rand_mac(mac_addr);
+	}
+
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+	return bfin_mmc_init(bis);
+}
+#endif
diff --git a/u-boot/board/tcm-bf537/Makefile b/u-boot/board/tcm-bf537/Makefile
new file mode 100644
index 0000000..4d7bf14
--- /dev/null
+++ b/u-boot/board/tcm-bf537/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tcm-bf537/config.mk b/u-boot/board/tcm-bf537/config.mk
new file mode 100644
index 0000000..c5d45c7
--- /dev/null
+++ b/u-boot/board/tcm-bf537/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/u-boot/board/tcm-bf537/gpio_cfi_flash.c b/u-boot/board/tcm-bf537/gpio_cfi_flash.c
new file mode 100644
index 0000000..c4fef9f
--- /dev/null
+++ b/u-boot/board/tcm-bf537/gpio_cfi_flash.c
@@ -0,0 +1,3 @@
+#define GPIO_PIN_1 GPIO_PF4
+#define GPIO_PIN_2 GPIO_PF5
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/u-boot/board/tcm-bf537/tcm-bf537.c b/u-boot/board/tcm-bf537/tcm-bf537.c
new file mode 100644
index 0000000..04d6bdb
--- /dev/null
+++ b/u-boot/board/tcm-bf537/tcm-bf537.c
@@ -0,0 +1,52 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include "../cm-bf537e/gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix TCM-BF537 board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+
+	return 0;
+}
diff --git a/u-boot/board/ti/beagle/Makefile b/u-boot/board/ti/beagle/Makefile
new file mode 100644
index 0000000..f5454b1
--- /dev/null
+++ b/u-boot/board/ti/beagle/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= beagle.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/u-boot/board/ti/beagle/beagle.c b/u-boot/board/ti/beagle/beagle.c
new file mode 100644
index 0000000..8dbf6a8
--- /dev/null
+++ b/u-boot/board/ti/beagle/beagle.c
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "beagle.h"
+
+#define TWL4030_I2C_BUS			0
+#define EXPANSION_EEPROM_I2C_BUS	1
+#define EXPANSION_EEPROM_I2C_ADDRESS	0x50
+
+#define TINCANTOOLS_ZIPPY		0x01000100
+#define TINCANTOOLS_ZIPPY2		0x02000100
+#define TINCANTOOLS_TRAINER		0x04000100
+#define TINCANTOOLS_SHOWDOG		0x03000100
+#define KBADC_BEAGLEFPGA		0x01000600
+
+#define BEAGLE_NO_EEPROM		0xffffffff
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct {
+	unsigned int device_vendor;
+	unsigned char revision;
+	unsigned char content;
+	char fab_revision[8];
+	char env_var[16];
+	char env_setting[64];
+} expansion_config;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+	
+	return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ *		C1/2/3, C4 or xM. This can be done by reading
+ *		the level of GPIO173, GPIO172 and GPIO171. This should
+ *		result in
+ *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ */
+int get_board_revision(void)
+{
+	int revision;
+	
+	if (!omap_request_gpio(171) &&
+	    !omap_request_gpio(172) &&
+	    !omap_request_gpio(173)) {
+		
+		omap_set_gpio_direction(171, 1);
+		omap_set_gpio_direction(172, 1);
+		omap_set_gpio_direction(173, 1);
+		
+		revision = omap_get_gpio_datain(173) << 2 |
+		omap_get_gpio_datain(172) << 1 |
+		omap_get_gpio_datain(171);
+		
+		omap_free_gpio(171);
+		omap_free_gpio(172);
+		omap_free_gpio(173);
+	} else {
+		printf("Error: unable to acquire board revision GPIOs\n");
+		revision = -1;
+	}
+	
+	return revision;
+}
+
+/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ *		bus 1 for the availability of an AT24C01B serial EEPROM.
+ *		returns the device_vendor field from the EEPROM
+ */
+unsigned int get_expansion_id(void)
+{
+	i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+	
+	/* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
+	if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+		i2c_set_bus_num(TWL4030_I2C_BUS);
+		return BEAGLE_NO_EEPROM;
+	}
+	
+	/* read configuration data */
+	i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+			 sizeof(expansion_config));
+	
+	i2c_set_bus_num(TWL4030_I2C_BUS);
+	
+	return expansion_config.device_vendor;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+	
+	switch (get_board_revision()) {
+		case REVISION_AXBX:
+			printf("Beagle Rev Ax/Bx\n");
+			setenv("beaglerev", "AxBx");
+			setenv("mpurate", "600");
+			break;
+		case REVISION_CX:
+			printf("Beagle Rev C1/C2/C3\n");
+			setenv("beaglerev", "Cx");
+			setenv("mpurate", "600");
+			MUX_BEAGLE_C();
+			break;
+		case REVISION_C4:
+			printf("Beagle Rev C4\n");
+			setenv("beaglerev", "C4");
+			setenv("mpurate", "720");
+			MUX_BEAGLE_C();
+			/* Set VAUX2 to 1.8V for EHCI PHY */
+			twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+									TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+									TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+									TWL4030_PM_RECEIVER_DEV_GRP_P1);
+			break;
+		case REVISION_XM:
+			printf("Beagle xM Rev A\n");
+			setenv("beaglerev", "xMA");
+			setenv("mpurate", "1000");
+			MUX_BEAGLE_XM();
+			/* Set VAUX2 to 1.8V for EHCI PHY */
+			twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+									TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+									TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+									TWL4030_PM_RECEIVER_DEV_GRP_P1);
+			break;
+		default:
+			printf("Beagle unknown 0x%02x\n", get_board_revision());
+	}
+	
+	switch (get_expansion_id()) {
+		case TINCANTOOLS_ZIPPY:
+			printf("Recognized Tincantools Zippy board (rev %d %s)\n",
+				   expansion_config.revision,
+				   expansion_config.fab_revision);
+			MUX_TINCANTOOLS_ZIPPY();
+			setenv("buddy", "zippy");
+			break;
+		case TINCANTOOLS_ZIPPY2:
+			printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
+				   expansion_config.revision,
+				   expansion_config.fab_revision);
+			MUX_TINCANTOOLS_ZIPPY();
+			setenv("buddy", "zippy2");
+			break;
+		case TINCANTOOLS_TRAINER:
+			printf("Recognized Tincantools Trainer board (rev %d %s)\n",
+				   expansion_config.revision,
+				   expansion_config.fab_revision);
+			MUX_TINCANTOOLS_ZIPPY();
+			MUX_TINCANTOOLS_TRAINER();
+			setenv("buddy", "trainer");
+			break;
+		case TINCANTOOLS_SHOWDOG:
+			printf("Recognized Tincantools Showdow board (rev %d %s)\n",
+				   expansion_config.revision,
+				   expansion_config.fab_revision);
+			/* Place holder for DSS2 definition for showdog lcd */
+			setenv("defaultdisplay", "showdoglcd");
+			setenv("buddy", "showdog");
+			break;
+		case KBADC_BEAGLEFPGA:
+			printf("Recognized KBADC Beagle FPGA board\n");
+			MUX_KBADC_BEAGLEFPGA();
+			setenv("buddy", "beaglefpga");
+			break;
+		case BEAGLE_NO_EEPROM:
+			printf("No EEPROM on expansion board\n");
+			setenv("buddy", "none");
+			break;
+		default:
+			printf("Unrecognized expansion board: %x\n",
+				   expansion_config.device_vendor);
+			setenv("buddy", "unknown");
+	}
+	
+	if (expansion_config.content == 1)
+		setenv(expansion_config.env_var, expansion_config.env_setting);
+	
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+	
+	/* Configure GPIOs to output */
+	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+			 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+	
+	/* Set GPIOs */
+	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
+		   &gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		   GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+	
+	dieid_num_r();
+	
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_BEAGLE();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/ti/beagle/beagle.h b/u-boot/board/ti/beagle/beagle.h
new file mode 100644
index 0000000..10853d8
--- /dev/null
+++ b/u-boot/board/ti/beagle/beagle.h
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BEAGLE_H_
+#define _BEAGLE_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Beagle board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/* BeagleBoard revisions */
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM	0x0
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_BEAGLE() \
+/*SDRC*/\
+MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+/*GPMC*/\
+MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
+MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+/*DSS*/\
+MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/*CAMERA*/\
+MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+/*Audio Interface */\
+MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/*Expansion card */\
+MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+/*Wireless LAN */\
+MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+/*Bluetooth*/\
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+/*Modem Interface */\
+MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+/*Serial Interface*/\
+MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
+MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
+MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
+MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+/* USB EHCI (port 2) */\
+MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
+MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
+MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
+MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
+MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
+MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
+MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
+MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+/*Control and debug */\
+MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_BEAGLE_C() \
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#define MUX_BEAGLE_XM() \
+MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | EN  | M4)) /*GPIO_56*/\
+MUX_VAL(CP(GPMC_WAIT0),		(IDIS | PTU | EN  | M4)) /*GPIO_63*/\
+MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTU | EN  | M4)) /*GPIO_129*/\
+MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
+#define MUX_TINCANTOOLS_ZIPPY() \
+MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | EN  | M1)) /*MCSPI4_CLK*/\
+MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | EN  | M1)) /*MCSPI4_SIMO*/\
+MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
+MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | EN  | M1)) /*MCSPI4_CS0*/\
+MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
+MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_DR),      (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_141*/
+
+#define MUX_TINCANTOOLS_TRAINER() \
+MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTU | EN  | M4)) /*GPIO_140*/\
+MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_141*/\
+MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_162*/
+
+#define MUX_KBADC_BEAGLEFPGA() \
+MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | DIS | M1)) /*MCSPI4_CLK*/\
+MUX_VAL(CP(MCBSP1_DX),      (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
+MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTU | EN  | M1)) /*MCSPI4_SOMI*/\
+MUX_VAL(CP(MCBSP1_FSX),     (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+
+#endif
diff --git a/u-boot/board/ti/beagle/config.mk b/u-boot/board/ti/beagle/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/u-boot/board/ti/beagle/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/ti/evm/Makefile b/u-boot/board/ti/evm/Makefile
new file mode 100644
index 0000000..2ff8356
--- /dev/null
+++ b/u-boot/board/ti/evm/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/u-boot/board/ti/evm/config.mk b/u-boot/board/ti/evm/config.mk
new file mode 100644
index 0000000..d173eef
--- /dev/null
+++ b/u-boot/board/ti/evm/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006 - 2008
+# Texas Instruments, <www.ti.com>
+#
+# EVM uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/ti/evm/evm.c b/u-boot/board/ti/evm/evm.c
new file mode 100644
index 0000000..aaf3033
--- /dev/null
+++ b/u-boot/board/ti/evm/evm.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include "evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 omap3_evm_version;
+
+u32 get_omap3_evm_rev(void)
+{
+	return omap3_evm_version;
+}
+
+static void omap3_evm_get_revision(void)
+{
+#if defined(CONFIG_CMD_NET)
+	/*
+	 * Board revision can be ascertained only by identifying
+	 * the Ethernet chipset.
+	 */
+	unsigned int smsc_id;
+
+	/* Ethernet PHY ID is stored at ID_REV register */
+	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
+	printf("Read back SMSC id 0x%x\n", smsc_id);
+
+	switch (smsc_id) {
+	/* SMSC9115 chipset */
+	case 0x01150000:
+		omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
+		break;
+	/* SMSC 9220 chipset */
+	case 0x92200000:
+	default:
+		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+       }
+#else
+#if defined(CONFIG_STATIC_BOARD_REV)
+	/*
+	 * Look for static defintion of the board revision
+	 */
+	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
+#else
+	/*
+	 * Fallback to the default above.
+	 */
+	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+#endif
+#endif	/* CONFIG_CMD_NET */
+}
+
+#ifdef CONFIG_USB_OMAP3
+/*
+ * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+	u8 retval = 0;
+
+	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+		retval = 1;
+
+	return retval;
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+	omap3_evm_get_revision();
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_EVM();
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 64 as output pin */
+	writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
+
+	/* Now send a pulse on the GPIO pin */
+	writel(GPIO0, &gpio3_base->setdataout);
+	udelay(1);
+	writel(GPIO0, &gpio3_base->cleardataout);
+	udelay(1);
+	writel(GPIO0, &gpio3_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/u-boot/board/ti/evm/evm.h b/u-boot/board/ti/evm/evm.h
new file mode 100644
index 0000000..b721ad6
--- /dev/null
+++ b/u-boot/board/ti/evm/evm.h
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2008
+ * Nishanth Menon <menon.nishanth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"OMAP3 EVM board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+	OMAP3EVM_BOARD_GEN_1 = 0,	/* EVM Rev between  A - D */
+	OMAP3EVM_BOARD_GEN_2,		/* EVM Rev >= Rev E */
+};
+
+u32 get_omap3_evm_rev(void);
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_EVM() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+								 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+								 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card  */\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | DIS | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX  */\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+								 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+								 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+								 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+								 /* - LCD_RESB */\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKR  */\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) /*MCBSP1_FSR*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP1_DR*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*MCBSP_CLKS  */\
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) /*MCBSP1_FSX*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKX  */\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_*/\
+								 /* RCTX*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*HDQ_SIO*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO  */\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI  */\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+								 /* TS_PEN_IRQ */\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+								 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS3*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+								 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+								 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) /*SYS_CLKOUT2*/\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) /*ETK_CLK*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
+	MUX_VAL(CP(ETK_D0_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D0*/\
+	MUX_VAL(CP(ETK_D1_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D1*/\
+	MUX_VAL(CP(ETK_D2_ES2 ),	(IEN  | PTD | EN  | M0)) /*ETK_D2*/\
+	MUX_VAL(CP(ETK_D3_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D3*/\
+	MUX_VAL(CP(ETK_D4_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D4*/\
+	MUX_VAL(CP(ETK_D5_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D5*/\
+	MUX_VAL(CP(ETK_D6_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D6*/\
+	MUX_VAL(CP(ETK_D7_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D7*/\
+	MUX_VAL(CP(ETK_D8_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D8*/\
+	MUX_VAL(CP(ETK_D9_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D9*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D10*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D11*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D12*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D13*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D14*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D15*/\
+ /*Die to Die */\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
+
+#endif
diff --git a/u-boot/board/ti/omap1510inn/Makefile b/u-boot/board/ti/omap1510inn/Makefile
new file mode 100644
index 0000000..9281fc2
--- /dev/null
+++ b/u-boot/board/ti/omap1510inn/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= omap1510innovator.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/omap1510inn/config.mk b/u-boot/board/ti/omap1510inn/config.mk
new file mode 100644
index 0000000..67fe0bd
--- /dev/null
+++ b/u-boot/board/ti/omap1510inn/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/u-boot/board/ti/omap1510inn/lowlevel_init.S b/u-boot/board/ti/omap1510inn/lowlevel_init.S
new file mode 100644
index 0000000..0e01841
--- /dev/null
+++ b/u-boot/board/ti/omap1510inn/lowlevel_init.S
@@ -0,0 +1,396 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr     r0, REG_PULL_DWN_CTRL_0
+	ldr     r1, VAL_PULL_DWN_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_1
+	ldr     r1, VAL_PULL_DWN_CTRL_1
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_2
+	ldr     r1, VAL_PULL_DWN_CTRL_2
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_3
+	ldr     r1, VAL_PULL_DWN_CTRL_3
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_4
+	ldr     r1, VAL_FUNC_MUX_CTRL_4
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_5
+	ldr     r1, VAL_FUNC_MUX_CTRL_5
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_6
+	ldr     r1, VAL_FUNC_MUX_CTRL_6
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_7
+	ldr     r1, VAL_FUNC_MUX_CTRL_7
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_8
+	ldr     r1, VAL_FUNC_MUX_CTRL_8
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_9
+	ldr     r1, VAL_FUNC_MUX_CTRL_9
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_A
+	ldr     r1, VAL_FUNC_MUX_CTRL_A
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_B
+	ldr     r1, VAL_FUNC_MUX_CTRL_B
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_C
+	ldr     r1, VAL_FUNC_MUX_CTRL_C
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_D
+	ldr     r1, VAL_FUNC_MUX_CTRL_D
+	str     r1, [r0]
+	ldr     r0, REG_VOLTAGE_CTRL_0
+	ldr     r1, VAL_VOLTAGE_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_TEST_DBG_CTRL_0
+	ldr     r1, VAL_TEST_DBG_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_MOD_CONF_CTRL_0
+	ldr     r1, VAL_MOD_CONF_CTRL_0
+	str     r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr     r0, REG_COMP_MODE_CTRL_0
+	ldr     r1, VAL_COMP_MODE_CTRL_0
+	str     r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000                 /* Load physical SDRAM base. */
+	mov r1, pc                          /* Get current execution location. */
+	/* Zero all but top 6 bits of PC, as they alone detect whether an
+	 * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
+	 * valid range for SDRAM on the OMAP 1510/5910.
+	 */
+	and r1, r1, #0xfc000000
+	cmp r1, r0			/* Compare. */
+	beq skip_sdram			/* Skip over EMIF-fast initialization
+					 * if running from SDRAM.
+					 */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800                        /* value should be checked */
+3:
+	subs r3, r3, #0x1                     /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+	str r1, [r2]                        /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]                        /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1                     /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+ /* Next, Enable the RS232 Line Drivers in the FPGA. */
+ /* Also, power on the audio CODEC's amplifier here, */
+ /* which will make a noise on the audio output. */
+ /* This is done here instead of in the kernel so there */
+ /* isn't a loud popping noise at the start of each */
+ /* song. */
+ /* Also, disable the CODEC's clocks. */
+ /* omap1510-HelenP1 [specific] */
+
+	ldr r0, REG_FPGA_POWER
+	mov r1, #0
+	ldr r2, REG_FPGA_DIP_SWITCH
+	ldrb r3, [r2]
+	cmp r3, #0x8
+	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
+	strb r1, [r0]
+	ldr r0, REG_FPGA_AUDIO
+	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
+	strb r1, [r0]
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* Innovator specific */
+REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
+	.word 0x08000003
+REG_FPGA_POWER:			/* 8 bits */
+	.word 0x08000005
+REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
+	.word 0x0800000c
+REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
+	.word 0x0800000e
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x10001200
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x01201012
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09000000
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0x11a10000
+VAL_PULL_DWN_CTRL_1:
+	.word 0x2e047fff
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffd603a6
+VAL_PULL_DWN_CTRL_3:
+	.word 0x00003e03
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
+	 *   This slows down internal SRAM accesses.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0b000008
+VAL_ARM_CKCTL:
+	.word 0x010f
+VAL_DPLL1_CTL:
+	.word 0x2710
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x0000f559
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00003331
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
diff --git a/u-boot/board/ti/omap1510inn/omap1510innovator.c b/u-boot/board/ti/omap1510inn/omap1510innovator.c
new file mode 100644
index 0000000..2cb6062
--- /dev/null
+++ b/u-boot/board/ti/omap1510inn/omap1510innovator.c
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of OMAP 1510-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	{
+		unsigned int regval;
+
+		regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+		regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+		if (regval & 0x0002) {
+			regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+			/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+			/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+			/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+		}
+		*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+	}
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ti/omap1610inn/Makefile b/u-boot/board/ti/omap1610inn/Makefile
new file mode 100644
index 0000000..4e21a37
--- /dev/null
+++ b/u-boot/board/ti/omap1610inn/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= omap1610innovator.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/omap1610inn/config.mk b/u-boot/board/ti/omap1610inn/config.mk
new file mode 100644
index 0000000..ee0aa0a
--- /dev/null
+++ b/u-boot/board/ti/omap1610inn/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1610 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/u-boot/board/ti/omap1610inn/flash.c b/u-boot/board/ti/omap1610inn/flash.c
new file mode 100644
index 0000000..36200ad
--- /dev/null
+++ b/u-boot/board/ti/omap1610inn/flash.c
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+void flash_unlock(flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_unlock(flash_info_t * info)
+{
+	int j;
+	for (j=2;j<CONFIG_SYS_MAX_FLASH_SECT;j++){
+	FPWV *addr = (FPWV *) (info->start[j]);
+	flash_unprotect_sectors (addr);
+	*addr = (FPW) 0x00500050;/* clear status register */
+	*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash	*/
+	}
+
+	mb ();
+	value = addr[1];	/* device ID	    */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.	*/
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/ti/omap1610inn/lowlevel_init.S b/u-boot/board/ti/omap1610inn/lowlevel_init.S
new file mode 100644
index 0000000..b376ba5
--- /dev/null
+++ b/u-boot/board/ti/omap1610inn/lowlevel_init.S
@@ -0,0 +1,452 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+#ifdef CONFIG_CS_AUTOBOOT		/* do the setup depending on boot mode */
+	ldr	r0, CONF_STATUS
+	ldr	r1, [r0]
+	tst	r1, #0x02
+	beq	disable_wd		/* booting from RAM, skip setup */
+#endif
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+	 *------------------------------------------------------*/
+disable_wd:
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov	r0,	#0x10000000
+	/* Get current execution location. */
+	mov	r1,	pc
+	/* Compare. */
+	cmp	r1,	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+#ifdef CONFIG_CS_AUTOBOOT
+CONF_STATUS:
+	.word 0xfffe1130	/* 32 bits */
+#endif
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec504
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_INNOVATOROMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
diff --git a/u-boot/board/ti/omap1610inn/omap1610innovator.c b/u-boot/board/ti/omap1610inn/omap1610innovator.c
new file mode 100644
index 0000000..44818bb
--- /dev/null
+++ b/u-boot/board/ti/omap1610inn/omap1610innovator.c
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CS_AUTOBOOT
+unsigned long omap_flash_base;
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	if (machine_is_omap_h2())
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
+	else if (machine_is_omap_innovator())
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
+	else
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+
+#ifdef CONFIG_CS_AUTOBOOT
+	 /* Check swapping of CS0 and CS3, set flash base accordingly */
+	omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
+					PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
+#endif
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0400030b
+
+#ifdef CONFIG_H2_OMAP1610
+	#define LAN_RESET_REGISTER 0x0400001c
+
+	/* The debug board on which the lan chip resides may not be powered
+	 * ON at the same time as the OMAP chip. So wait in a loop until the
+	 * lan reset register (on the debug board) is available (powered on)
+	 * and reset the lan chip.
+	 */
+
+	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+		udelay (3);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+		udelay (3);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+#endif
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!  */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ti/omap2420h4/Makefile b/u-boot/board/ti/omap2420h4/Makefile
new file mode 100644
index 0000000..5174d89
--- /dev/null
+++ b/u-boot/board/ti/omap2420h4/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= omap2420h4.o mem.o sys_info.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/omap2420h4/config.mk b/u-boot/board/ti/omap2420h4/config.mk
new file mode 100644
index 0000000..ca5ebdf
--- /dev/null
+++ b/u-boot/board/ti/omap2420h4/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+#
+# TI H4 board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
+# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+#CONFIG_SYS_TEXT_BASE = 0x40270000
+
+
+# Handy to get symbols to debug ROM version.
+#CONFIG_SYS_TEXT_BASE = 0x0
+#CONFIG_SYS_TEXT_BASE = 0x08000000
+#CONFIG_SYS_TEXT_BASE = 0x04000000
diff --git a/u-boot/board/ti/omap2420h4/lowlevel_init.S b/u-boot/board/ti/omap2420h4/lowlevel_init.S
new file mode 100644
index 0000000..731c552
--- /dev/null
+++ b/u-boot/board/ti/omap2420h4/lowlevel_init.S
@@ -0,0 +1,185 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
+
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* get addr of clock setting code */
+	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
+	mov	r1, r1			/* r1 <- dest address (passed in) */
+	add	r2, r2, r0		/* r2 <- source end address */
+next2:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next2
+	mov	pc, lr			/* back to caller */
+
+/* ****************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *		 -executed from SRAM.
+ *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ *  R2 = dpll value
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+	sub	sp, sp, #0x4 /* get some stack space */
+	str	r4, [sp]     /* save r4's value */
+
+	/* move into fast relock bypass */
+	ldr	r8, pll_ctl_add
+	mov	r4, #0x2
+	str	r4, [r8]
+	ldr	r4, pll_stat
+block:
+	ldr	r8, [r4]	/* wait for bypass to take effect */
+	and	r8, r8, #0x3
+	cmp	r8, #0x1
+	bne	block
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr	r4, pll_div_add
+	ldr	r8, pll_div_val
+	str	r8, [r4]
+
+	/* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+	ldr	r4, cfg3_0_addr
+	ldr	r8, cfg3_0_val
+	str	r8, [r4]
+	ldr	r4, cfg4_0_addr
+	ldr	r8, cfg4_0_val
+	str	r8, [r4]
+	ldr	r4, cfg1_0_addr
+	ldr	r8, [r4]
+	orr	r8, r8, #0x3	 /* up gpmc divider */
+	str	r8, [r4]
+
+	/* setup to 2x loop though code.  The first loop pre-loads the
+	 * icache, the 2nd commits the prcm config, and locks the dpll
+	 */
+	mov	r4, #0x1000	 /* spin spin spin */
+	mov	r8, #0x4	 /* first pass condition & set registers */
+	cmp	r8, #0x4
+2:
+	ldrne	r8, [r3]	 /* DPLL lock check */
+	and	r8, r8, #0x7
+	cmp	r8, #0x2
+	beq	4f
+3:
+	subeq	r8, r8, #0x1
+	streq	r8, [r0]	 /* commit dividers (2nd time) */
+	nop
+lloop1:
+	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop1
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	streq	r2, [r1]	/* lock dpll (2nd time) */
+	nop
+lloop2:
+	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop2
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	ldreq	r8, [r3]	 /* get lock condition for dpll */
+	cmp	r8, #0x4	 /* first time though? */
+	bne	2b
+	moveq	r8, #0x2	 /* set to dpll check condition. */
+	beq	3b		 /* if condition not true branch */
+4:
+	ldr	r4, [sp]
+	add	sp, sp, #0x4	 /* return stack space */
+	mov	pc, lr		 /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+cfg3_0_addr:
+    .word  GPMC_CONFIG3_0
+cfg3_0_val:
+    .word  H4_24XX_GPMC_CONFIG3_0
+cfg4_0_addr:
+    .word  GPMC_CONFIG4_0
+cfg4_0_val:
+    .word  H4_24XX_GPMC_CONFIG4_0
+cfg1_0_addr:
+    .word  GPMC_CONFIG1_0
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_stat:
+    .word CM_IDLEST_CKGEN
+pll_div_add:
+    .word CM_CLKSEL1_PLL
+pll_div_val:
+    .word DPLL_VAL	/* DPLL setting (300MHz default) */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* map interrupt controller */
+	ldr	r0,	VAL_INTH_SETUP
+	mcr	p15, 0, r0, c15, c2, 4
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+VAL_INTH_SETUP:
+	.word PERIFERAL_PORT_BASE
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
diff --git a/u-boot/board/ti/omap2420h4/mem.c b/u-boot/board/ti/omap2420h4/mem.c
new file mode 100644
index 0000000..c8b4186
--- /dev/null
+++ b/u-boot/board/ti/omap2420h4/mem.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+/************************************************************
+ * sdelay() - simple spin loop.  Will be constant time as
+ *  its generally used in 12MHz bypass conditions only.  This
+ *  is necessary until timers are accessible.
+ *
+ *  not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*********************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
+ *   -- called from SRAM, or Flash (using temp SRAM stack).
+ *********************************************************************************/
+void prcm_init(void)
+{
+	u32 div;
+	void (*f_lock_pll) (u32, u32, u32, u32);
+	extern void *_end_vect, *_start;
+
+	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
+
+	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */
+	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */
+	__raw_writel(0, CM_ICLKEN1_CORE);
+	__raw_writel(0, CM_ICLKEN2_CORE);
+
+	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
+	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
+	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
+	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */
+
+	div = BUS_DIV;
+	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
+	sdelay(1000);
+
+	if(running_in_sram()){
+		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.
+		* but then comes back.  If running from Flash this sequence kills you, thus you need
+		* to run it using CONFIG_PARTIAL_SRAM.
+		*/
+		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
+		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
+		sdelay(1000);
+		/* set clock selection and dpll dividers. */
+		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */
+		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
+		sdelay(10000);
+		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
+		sdelay(10000);
+		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */
+	}else if(running_in_flash()){
+		/* if running from flash, need to jump to small relocated code area in SRAM.
+		 * This is the only safe spot to do configurations from.
+		 */
+		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
+	}
+
+	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */
+	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */
+	sdelay(1000);
+}
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontigious support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(SDRC_CS0_OSET);
+	size /= SZ_32M;  /* find size to offset CS1 */
+	a_add_high = (size & 3) << 8;   /* set up low field */
+	a_add_low = (size & 0x3C) >> 2; /* set up high field */
+	__raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in gussing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+	u32 val1, val2;
+	u32 pattern = 0x12345678;
+
+	__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400);   /* clear pos A */
+	__raw_writel(pattern, OMAP2420_SDRC_CS0);    /* pattern to pos B */
+	__raw_writel(0x0,OMAP2420_SDRC_CS0+4);       /* remove pattern off the bus */
+	val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
+	val2 = __raw_readl(OMAP2420_SDRC_CS0);       /* get val2 */
+
+	if ((val1 != 0) || (val2 != pattern))        /* see if pos A value changed*/
+		return(0);
+	else
+		return(1);
+}
+
+
+/********************************************************
+ *  sdrc_init() - init the sdrc chip selects CS0 and CS1
+ *  - early init routines, called from flash or
+ *  SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+	#define EARLY_INIT 1
+	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);  /* only init up first bank here */
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *  -called from low level code with stack only.
+ *  -code sets up SDRAM timing and muxing for 2422 or 2420.
+ *  -optimal settings can be placed here, or redone after i2c
+ *      inspection of board info
+ *
+ *  This is a bit ugly, but should handle all memory moduels
+ *   used with the H4. The first time though this code from s_init()
+ *   we configure the first chip select.  Later on we come back and
+ *   will configure the 2nd chip select if it exists.
+ *
+ **************************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+	u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
+	sdrc_data_t *sdata;	 /* do not change type */
+	u32 a, b, r;
+
+	static const sdrc_data_t sdrc_2422 =
+	{
+		H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
+		H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
+		0, H4_2422_SDRC_DLLAB_CTRL
+	};
+	static const sdrc_data_t sdrc_2420 =
+	{
+		H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
+		H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
+		H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
+		H4_2420_SDRC_DLLAB_CTRL
+	};
+
+	if (offset == SDRC_CS0_OSET)
+		cs0 = common = 1;  /* int regs shared between both chip select */
+
+	cpu = get_cpu_type();
+	rev = get_cpu_rev();
+
+	/* warning generated, though code generation is correct. this may bite later,
+	 * but is ok for now. there is only so much C code you can do on stack only
+	 * operation.
+	 */
+	if (cpu == CPU_2422){
+		sdata = (sdrc_data_t *)&sdrc_2422;
+		pass_type = STACKED;
+	} else{
+		sdata = (sdrc_data_t *)&sdrc_2420;
+		pass_type = IP_DDR;
+	}
+
+	__asm__ __volatile__("": : :"memory");  /* limit compiler scope */
+
+	/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
+	 * If we are running in flash prior to relocation and we use data
+	 * here which is not pc relative we need to get the address correct.
+	 * We need to find the current flash mapping to dress up the initial
+	 * pointer load.  As long as this is const data we should be ok.
+	 */
+	if((early) && running_in_flash()){
+		sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
+		/* NOR internal boot offset is 0x4000 from xloader signature */
+		if(running_from_internal_boot())
+			sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
+	}
+
+	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
+		if(mtype == DDR_COMBO){
+			pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
+			pass_type = COMBO_DDR; /* CS1 config */
+			__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
+		}
+		if(rev != CPU_2420_2422_ES1)	/* for es2 and above smooth things out */
+			make_cs1_contiguous();
+	}
+
+next_mem_type:
+	if (common) {	/* do a SDRC reset between types to clear regs*/
+		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);	/* reset sdrc */
+		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
+		__raw_writel(0, SDRC_SYSCONFIG);		/* clear soft reset */
+		__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
+#ifdef POWER_SAVE
+		__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
+		__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
+		__raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
+#endif
+	}
+
+	if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
+		__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
+	else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
+		__raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
+	} else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
+		__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
+	}
+
+	a = sdata->sdrc_actim_ctrla_0;
+	b = sdata->sdrc_actim_ctrlb_0;
+	r = sdata->sdrc_dllab_ctrl;
+
+	/* work around ES1 DDR issues */
+	if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
+		a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
+		b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
+		r = H4_242x_SDRC_RFR_CTRL_ES1;
+	}
+
+	if (cs0) {
+		__raw_writel(a, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(b, SDRC_ACTIM_CTRLB_0);
+	} else {
+		__raw_writel(a, SDRC_ACTIM_CTRLA_1);
+		__raw_writel(b, SDRC_ACTIM_CTRLB_1);
+	}
+	__raw_writel(r, SDRC_RFR_CTRL+offset);
+
+	/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
+	__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
+	sdelay(5000);  /* susposed to be 100us per design spec for mddr/msdr */
+	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
+	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
+	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
+
+	/*
+	 * CSx SDRC Mode Register
+	 * Burst length = (4 - DDR) (2-SDR)
+	 * Serial mode
+	 * CAS latency = x
+	 */
+	if(pass_type == IP_SDR)
+		__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
+	else
+		__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
+
+	/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
+	if (rev == CPU_2420_2422_ES1){
+		dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
+		__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
+			,SMS_CLASS_ARB0);/* enable bust complete for lcd */
+	}
+	else
+		dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
+
+	/* enable & load up DLL with good value for 75MHz, and set phase to 90
+	 * ES1 recommends 90 phase, ES2 recommends 72 phase.
+	 */
+	if (common && (pass_type != IP_SDR)) {
+		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
+	}
+	sdelay(90000);
+
+	if(mem_ok())
+		return; /* STACKED, other configued type */
+	++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
+	goto next_mem_type;
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	u32 mux=0, mtype, mwidth, rev, tval;
+
+	rev  = get_cpu_rev();
+	if (rev == CPU_2420_2422_ES1)
+		tval = 1;
+	else
+		tval = 0;  /* disable bit switched meaning */
+
+	/* global settings */
+	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
+	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
+	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+#ifdef CONFIG_SYS_NAND_BOOT
+	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#else
+	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#endif
+
+	/* discover bus connection from sysboot */
+	if (is_gpmc_muxed() == GPMC_MUXED)
+		mux = BIT9;
+	mtype = get_gpmc0_type();
+	mwidth = get_gpmc0_width();
+
+	/* setup cs0 */
+	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
+	sdelay(1000);
+
+#ifdef CONFIG_SYS_NAND_BOOT
+	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
+#else
+	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
+#endif
+
+#ifdef PRCM_CONFIG_III
+	__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+#endif
+	__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+	__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+#ifdef PRCM_CONFIG_III
+	__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+	__raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+#endif
+	__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
+	sdelay(2000);
+
+	/* setup cs1 */
+	__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
+	sdelay(1000);
+	__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
+	sdelay(2000);
+}
diff --git a/u-boot/board/ti/omap2420h4/omap2420h4.c b/u-boot/board/ti/omap2420h4/omap2420h4.c
new file mode 100644
index 0000000..1c98e1b
--- /dev/null
+++ b/u-boot/board/ti/omap2420h4/omap2420h4.c
@@ -0,0 +1,856 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void wait_for_command_complete(unsigned int wd_base);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+	gpmc_init(); /* in SRAM or SDRM, finish GPMC */
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;		/* board id for linux */
+	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);	/* adress of boot parameters */
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ *  general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+	/* if GP device unlock device SRAM for general use */
+	if (get_device_type() == GP_DEVICE) {
+		__raw_writel(0xFF, A_REQINFOPERM0);
+		__raw_writel(0xCFDE, A_READPERM0);
+		__raw_writel(0xCFDE, A_WRITEPERM0);
+	}
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with sram stack.
+ **********************************************************/
+void s_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	watchdog_init();
+	set_muxconf_regs();
+	delay(100);
+	try_unlock_sram();
+
+	if(!in_sdram)
+		prcm_init();
+
+	peripheral_enable();
+	icache_enable();
+	if (!in_sdram)
+		sdrc_init();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+	ether_init(); /* better done here so timers are init'ed */
+	return(0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
+	* The ROM takes care of the secure one. Of the 3 GP ones,
+	* 1 can reset us directly, the other 2 only generate MPU interrupts.
+	*/
+	__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
+	wait_for_command_complete(WD2_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
+
+#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
+	__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
+	wait_for_command_complete(WD3_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
+
+	__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
+	wait_for_command_complete(WD4_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
+#endif
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+	int pending = 1;
+	do {
+		pending = __raw_readl(wd_base+WWPS);
+	} while (pending);
+}
+
+/*******************************************************************
+ * Routine:ether_init
+ * Description: take the Ethernet controller out of reset and wait
+ *		   for the EEPROM load to complete.
+ ******************************************************************/
+void ether_init (void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+	int cnt = 20;
+
+	__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
+
+	__raw_writew(0x0, LAN_RESET_REGISTER);
+	do {
+		__raw_writew(0x1, LAN_RESET_REGISTER);
+		udelay (100);
+		if (cnt == 0)
+			goto h4reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+	cnt = 20;
+
+	do {
+		__raw_writew(0x0, LAN_RESET_REGISTER);
+		udelay (100);
+		if (cnt == 0)
+			goto h4reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+	udelay (1000);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (1000);
+
+	h4reset_err_out:
+	return;
+#endif
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+	unsigned int size0=0,size1=0;
+	u32 mtype, btype, rev, cpu;
+	u8 chg_on = 0x5; /* enable charge of back up battery */
+	u8 vmode_on = 0x8C;
+	#define NOT_EARLY 0
+
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
+
+	btype = get_board_type();
+	mtype = get_mem_type();
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+
+	display_board_info(btype);
+	if (btype == BOARD_H4_MENELAUS){
+		update_mux(btype,mtype); /* combo part on menelaus */
+		i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
+		i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
+	}
+
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
+	}
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	else /* ES2 and above can remap at 32MB granularity */
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ *              specific to the hardware
+ *********************************************************/
+void set_muxconf_regs (void)
+{
+	muxSetupSDRC();
+	muxSetupGPMC();
+	muxSetupUsb0();
+	muxSetupUart3();
+	muxSetupI2C1();
+	muxSetupUART1();
+	muxSetupLCD();
+	muxSetupCamera();
+	muxSetupMMCSD();
+	muxSetupTouchScreen();
+	muxSetupHDQ();
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void peripheral_enable(void)
+{
+	unsigned int v, if_clks=0, func_clks=0;
+
+	/* Enable GP2 timer.*/
+	if_clks |= BIT4;
+	func_clks |= BIT4;
+	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* Sys_clk input OMAP2420_GPT2 */
+	__raw_writel(v, CM_CLKSEL2_CORE);
+	__raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CONFIG_SYS_NS16550
+	/* Enable UART1 clock */
+	func_clks |= BIT21;
+	if_clks |= BIT21;
+#endif
+	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
+	__raw_writel(v,CM_ICLKEN1_CORE );
+	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+	__raw_writel(v, CM_FCLKEN1_CORE);
+	delay(1000);
+
+#ifndef KERNEL_UPDATED
+	{
+#define V1 0xffffffff
+#define V2 0x00000007
+
+		__raw_writel(V1, CM_FCLKEN1_CORE);
+		__raw_writel(V2, CM_FCLKEN2_CORE);
+		__raw_writel(V1, CM_ICLKEN1_CORE);
+		__raw_writel(V1, CM_ICLKEN2_CORE);
+	}
+#endif
+}
+
+/****************************************
+ * Routine: muxSetupUsb0   (ostboot)
+ * Description: Setup usb muxing
+ *****************************************/
+void muxSetupUsb0(void)
+{
+	volatile uint8   *MuxConfigReg;
+	volatile uint32  *otgCtrlReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	/* setup for USB VBus detection */
+	otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
+	*otgCtrlReg |= 0x00040000; /* bit 18 */
+}
+
+/****************************************
+ * Routine: muxSetupUart3   (ostboot)
+ * Description: Setup uart3 muxing
+ *****************************************/
+void muxSetupUart3(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
+	*MuxConfigReg &= (uint8)(~0x1F);
+}
+
+/****************************************
+ * Routine: muxSetupI2C1   (ostboot)
+ * Description: Setup i2c muxing
+ *****************************************/
+void muxSetupI2C1(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* I2C1 Clock pin configuration, PIN = M19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* I2C1 Data pin configuration, PIN = L15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* Pull-up required on data line */
+	/* external pull-up already present. */
+	/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
+}
+
+/****************************************
+ * Routine: muxSetupUART1  (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+void muxSetupUART1(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* UART1_CTS pin configuration, PIN = D21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RTS pin configuration, PIN = H21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_TX pin configuration, PIN = L20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RX pin configuration, PIN = T21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupLCD   (ostboot)
+ * Description: Setup lcd muxing
+ *****************************************/
+void muxSetupLCD(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* LCD_D0 pin configuration, PIN = Y7  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D1 pin configuration, PIN = P10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D2 pin configuration, PIN = V8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D3 pin configuration, PIN = Y8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D4 pin configuration, PIN = W8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D5 pin configuration, PIN = R10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D6 pin configuration, PIN = Y9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D7 pin configuration, PIN = V9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D8 pin configuration, PIN = W9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D9 pin configuration, PIN = P11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D10 pin configuration, PIN = V10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D11 pin configuration, PIN = Y10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D12 pin configuration, PIN = W10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D13 pin configuration, PIN = R11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D14 pin configuration, PIN = V11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D15 pin configuration, PIN = W11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D16 pin configuration, PIN = P12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D17 pin configuration, PIN = R12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_PCLK pin configuration,   PIN = W6   */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_VSYNC pin configuration,  PIN = V7  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_HSYNC pin configuration,  PIN = Y6  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_ACBIAS pin configuration, PIN = W7 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupCamera  (ostboot)
+ * Description: Setup camera muxing
+ *****************************************/
+void muxSetupCamera(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* CAMERA_RSTZ  pin configuration, PIN = Y16 */
+	/* CAM_RST is connected through the I2C IO expander.*/
+	/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
+	/* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
+
+	/* CAMERA_XCLK  pin configuration, PIN = U3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_LCLK  pin configuration, PIN = V5 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_VSYNC pin configuration, PIN = U2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_HSYNC pin configuration, PIN = T3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT0 pin configuration, PIN = T4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT1 pin configuration, PIN = V2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT2 pin configuration, PIN = V3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT3 pin configuration, PIN = U4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT4 pin configuration, PIN = W2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT5 pin configuration, PIN = V4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT6 pin configuration, PIN = W3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT7 pin configuration, PIN = Y2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT8 pin configuration, PIN = Y4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT9 pin configuration, PIN = V6 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupMMCSD (ostboot)
+ * Description: set up MMC muxing
+ *****************************************/
+void muxSetupMMCSD(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* SDMMC_CLKI pin configuration,  PIN = H15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CLKO pin configuration,  PIN = G19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CMD pin configuration,   PIN = H18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT0 pin configuration,  PIN = F20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT1 pin configuration,  PIN = H14 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT2 pin configuration,  PIN = E19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT3 pin configuration,  PIN = D19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CDIR pin configuration,  PIN = G18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
+	/* MMC_CD for 2422IP=K1 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+
+	/* MMC_WP pin configuration,      PIN = B4  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+}
+
+/******************************************
+ * Routine: muxSetupTouchScreen (ostboot)
+ * Description:  Set up touch screen muxing
+ *******************************************/
+void muxSetupTouchScreen(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* SPI1_CLK pin configuration,  PIN = U18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MOSI pin configuration, PIN = V20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MISO pin configuration, PIN = T18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_nCS0 pin configuration, PIN = U19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* PEN_IRQ pin configuration,   PIN = P20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupHDQ (ostboot)
+ * Description: setup 1wire mux
+ *****************************************/
+void muxSetupHDQ(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* HDQ_SIO pin configuration,  PIN = N18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/***************************************************************
+ * Routine: muxSetupGPMC (ostboot)
+ * Description: Configures balls which cam up in protected mode
+ ***************************************************************/
+void muxSetupGPMC(void)
+{
+	volatile uint8 *MuxConfigReg;
+	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
+
+	/* gpmc_io_dir */
+	*MCR = 0x19000000;
+
+	/* NOR FLASH CS0 */
+	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
+				   *MuxConfigReg = 0x01 ;
+
+	/* MPDB(Multi Port Debug Port) CS1 */
+	/* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
+				   *MuxConfigReg = 0x00 ;
+}
+
+/****************************************************************
+ * Routine: muxSetupSDRC  (ostboot)
+ * Description: Configures balls which come up in protected mode
+ ****************************************************************/
+void muxSetupSDRC(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	/* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
+				   *MuxConfigReg = 0x00;
+
+	if (get_cpu_type() == CPU_2422) {
+		MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
+					   *MuxConfigReg = 0x1b;
+	}
+}
+
+/*****************************************************************************
+ * Routine: update_mux()
+ * Description: Update balls which are different beween boards.  All should be
+ *              updated to match functionaly.  However, I'm only updating ones
+ *              which I'll be using for now.  When power comes into play they
+ *              all need updating.
+ *****************************************************************************/
+void update_mux(u32 btype,u32 mtype)
+{
+	u32 cpu, base = OMAP2420_CTRL_BASE;
+	cpu = get_cpu_type();
+
+	if (btype == BOARD_H4_MENELAUS) {
+		if (cpu == CPU_2420) {
+			/* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
+			__raw_writeb(0x3, base+0x30);
+			/* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
+			__raw_writeb(0x3, base+0xa3);
+			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
+			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
+			/* PIN = M1 (HSUSBOTG) */
+			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
+			__raw_writeb(0x3, base+0x9d);
+			/* PIN = U32, (WLAN_CLKREQ) */
+			/* PIN = Y11, WLAN */
+			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
+			__raw_writeb(0x3, base+0xe7);
+			/* PIN = AA8, mDOC */
+			/* PIN = AA10, BT */
+			/* PIN = AA13, WLAN */
+			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 HHUSB */
+			/* PIN = H19 HSUSB */
+			/* PIN = W13, P13, R13, W16 ... */
+			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
+			__raw_writeb(0x3, base+0xde);
+			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
+			__raw_writeb(0x0, base+0x12c);
+			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
+			__raw_writeb(0x0, base+0x136);
+		} else if (cpu == CPU_2422) {
+			/* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
+			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
+			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
+			__raw_writeb(0x0, base+0x92);
+			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
+			/* PIN = M1 (HSUSBOTG) */
+			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
+			__raw_writeb(0x3, base+0x10c);
+			/* PIN = U32, (WLAN_CLKREQ) */
+			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
+			__raw_writeb(0x3, base+0x30);
+			/* PIN = AA8, mDOC */
+			/* PIN = AA10, BT */
+			/* PIN = AA12, WLAN */
+			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 HHUSB */
+			/* PIN = H19 HSUSB */
+			/* PIN = W13, P13, R13, W16 ... */
+			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
+			__raw_writeb(0x3, base+0xde);
+			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
+			__raw_writeb(0x0, base+0x12c);
+			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
+			__raw_writeb(0x0, base+0x136);
+		}
+
+	} else if (btype == BOARD_H4_SDP) {
+		if (cpu == CPU_2420) {
+			/* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
+			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
+			/* Pin = Y11 VLNQ */
+			/* Pin = AA4 VLNQ */
+			/* Pin = AA6 VLNQ */
+			/* Pin = AA8 VLNQ */
+			/* Pin = AA10 VLNQ */
+			/* Pin = AA12 VLNQ */
+			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 MDOC_nDMAREQ */
+			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
+			__raw_writeb(0x3, base+0x114);
+			/* PIN = W13, V12, P13, R13, W19, W16 ... */
+			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
+		} else if (cpu == CPU_2422) {
+			/* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
+			/* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
+			/* Pin = Y11 VLNQ */
+			/* Pin = AA4 VLNQ */
+			/* Pin = AA6 VLNQ */
+			/* Pin = AA8 VLNQ */
+			/* Pin = AA10 VLNQ */
+			/* Pin = AA12 VLNQ */
+			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 MDOC_nDMAREQ */
+			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
+			__raw_writeb(0x3, base+0x114);
+			/* PIN = W13, V12, P13, R13, W19, W16 ... */
+			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
+		}
+	}
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ti/omap2420h4/sys_info.c b/u-boot/board/ti/omap2420h4/sys_info.c
new file mode 100644
index 0000000..a9f7241
--- /dev/null
+++ b/u-boot/board/ti/omap2420h4/sys_info.c
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>  /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+	u32 p;
+	p = __raw_readl(PRODUCTION_ID); /* get production ID */
+	return((p & CPU_242X_PID_MASK) >> 16);
+}
+
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ *   (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+	u32 v;
+
+	switch(get_prod_id()){
+		case 1:;/* 2420 */
+		case 2: return(CPU_2420); break; /* 2420 pop */
+		case 4: return(CPU_2422); break;
+		case 8: return(CPU_2423); break;
+		default: break;  /* early 2420/2422's unmarked */
+	}
+
+	v = __raw_readl(TAP_IDCODE_REG);
+	v &= CPU_24XX_ID_MASK;
+	if (v == CPU_2420_CHIPID) {	  /* currently 2420 and 2422 have same id */
+		if (is_gpmc_muxed() == GPMC_MUXED)	  /* if mux'ed */
+			return(CPU_2420);
+		else
+			return(CPU_2422);
+	} else
+		return(CPU_2420); /* don't know, say 2420 */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 v;
+	v = __raw_readl(TAP_IDCODE_REG);
+	v = v >> 28;
+	return(v+1);  /* currently 2422 and 2420 match up */
+}
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
+	if(*burst == H4_2420_SDRC_MR_0_SDR)
+		return(1);
+	return(0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+	u32 cpu, sdr = is_mem_sdr();
+
+	cpu = get_cpu_type();
+	if (cpu == CPU_2422 || cpu == CPU_2423)
+		return(DDR_STACKED);
+
+	if(get_prod_id() == 0x2)
+		return(XDR_POP);
+
+	if (get_board_type() == BOARD_H4_MENELAUS)
+		if(sdr)
+			return(SDR_DISCRETE);
+		else
+			return(DDR_COMBO);
+	else
+		if(sdr) /* SDP + SDR kit */
+			return(SDR_DISCRETE);
+		else
+			return(DDR_DISCRETE); /* origional SDP */
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+	size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
+	size &= 0x2FF;   /* remove unwanted bits */
+	size *= SZ_2M;   /* find size in MB */
+	return(size);
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
+ *      when they are available we can get info from there.  This should
+ *      be correct of all known boards up until today.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+	if (i2c_probe(I2C_MENELAUS) == 0)
+		return(BOARD_H4_MENELAUS);
+	else
+		return(BOARD_H4_SDP);
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings (dip switch on h4)
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return(0x00000FFF & __raw_readl(CONTROL_STATUS));
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = __raw_readl(GPMC_CONFIG7_0);
+	b &= 0x1F;	 /* keep base [5:0] */
+	b = b << 24; /* ret 0x0b000000 */
+	return(b);
+}
+
+/*****************************************************************
+ *  is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+	u32 mux;
+	mux = get_sysboot_value();
+	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+		return(GPMC_MUXED); /* NAND Boot mode */
+	if (mux & BIT1)	   /* if mux'ed */
+		return(GPMC_MUXED);
+	else
+		return(GPMC_NONMUXED);
+}
+
+/************************************************************************
+ *  get_gpmc0_type() - read sysboot lines to see type of memory attached
+ ************************************************************************/
+u32 get_gpmc0_type(void)
+{
+	u32 type;
+	type = get_sysboot_value();
+	if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
+		return(TYPE_NAND);
+	else
+		return(TYPE_NOR);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	u32 width;
+	width = get_sysboot_value();
+	if ((width & 0xF) == (BIT3|BIT2))
+		return(WIDTH_8BIT);
+	else
+		return(WIDTH_16BIT);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ *   volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+	u32 i = 0, val;
+	do {
+		++i;
+		val = __raw_readl(read_addr) & read_bit_mask;
+		if (val == match_value)
+			return(1);
+		if (i==bound)
+			return(0);
+	} while (1);
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char cpu_2420[] = "2420";   /* cpu type */
+	char cpu_2422[] = "2422";
+	char cpu_2423[] = "2423";
+	char db_men[] = "Menelaus"; /* board type */
+	char db_ip[] = "IP";
+	char mem_sdr[] = "mSDR";    /* memory type */
+	char mem_ddr[] = "mDDR";
+	char t_tst[] = "TST";	    /* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+
+	char *cpu_s, *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if(is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	if(cpu == CPU_2423)
+		cpu_s = cpu_2423;
+	else if (cpu == CPU_2422)
+		cpu_s = cpu_2422;
+	else
+		cpu_s = cpu_2420;
+
+	if(btype ==  BOARD_H4_MENELAUS)
+		db_s = db_men;
+	else
+		db_s = db_ip;
+
+	switch(sec){
+		case TST_DEVICE: sec_s = t_tst; break;
+		case EMU_DEVICE: sec_s = t_emu; break;
+		case HS_DEVICE:  sec_s = t_hs; break;
+		case GP_DEVICE:  sec_s = t_gp; break;
+		default: sec_s = unk;
+	}
+
+	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
+	printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ *          0 = 242x IP platform (first 2xx boards)
+ *          1 = 242x Menelaus platfrom.
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	u32 btype = get_board_type();
+
+	if (btype == BOARD_H4_MENELAUS){
+		rev = 1;
+	}
+	return(rev);
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32  val;
+	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return(val);
+}
+
+/********************************************************
+ *  get_base2(); get 2upper addr of current execution
+ *******************************************************/
+u32 get_base2(void)
+{
+	u32  val;
+	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
+	val &= 0xFF000000;
+	val >>= 24;
+	return(val);
+}
+
+/********************************************************
+ *  running_in_flash() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+	if (get_base() < 4)
+		return(1);  /* in flash */
+	return(0); /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sram() - tell if currently running in
+ *   sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+	if (get_base() == 4)
+		return(1);  /* in SRAM */
+	return(0); /* running in FLASH or SDRAM */
+}
+/********************************************************
+ *  running_in_sdram() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return(1);  /* in sdram */
+	return(0); /* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ *  running_from_internal_boot() - am I a signed NOR image.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+	u32 v, base;
+
+	v = get_sysboot_value() & BIT3;
+	base = get_base2();
+	/* if running at mask rom flash address and
+	 * sysboot3 says this was an internal boot
+	 */
+	if ((base == 0x08) && v)
+		return(1);
+	else
+		return(0);
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
+	return(mode >>= 8);
+}
diff --git a/u-boot/board/ti/omap5912osk/Makefile b/u-boot/board/ti/omap5912osk/Makefile
new file mode 100644
index 0000000..e2de898
--- /dev/null
+++ b/u-boot/board/ti/omap5912osk/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= omap5912osk.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/omap5912osk/config.mk b/u-boot/board/ti/omap5912osk/config.mk
new file mode 100644
index 0000000..0ed7d8a
--- /dev/null
+++ b/u-boot/board/ti/omap5912osk/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002-2004
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+# Rishi Bhattacharya <rishi@ti.com>
+#
+# TI OSK board with OMAP5912 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# OSK has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/u-boot/board/ti/omap5912osk/lowlevel_init.S b/u-boot/board/ti/omap5912osk/lowlevel_init.S
new file mode 100644
index 0000000..e60161e
--- /dev/null
+++ b/u-boot/board/ti/omap5912osk/lowlevel_init.S
@@ -0,0 +1,477 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*------------------------------------------------------*
+	 * Ensure i-cache is enabled                            *
+	 * To configure TC regs without fetching instruction    *
+	 *------------------------------------------------------*/
+	mrc	p15, 0, r0, c1, c0
+	orr	r0, r0, #0x1000
+	mcr	p15, 0, r0, c1, c0
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+	mov	r1,	#0x01               /* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]            /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable */
+	mov	r1,	#0x1000
+	ldr	r0,	REG_ARM_SYSST
+
+	mov	r2,	#0
+1:	cmp	r2,	#1
+	streqh	r1,	[r0]
+	add	r2,	r2,	#1
+	cmp	r2,	#0x100              /* wait for any bubbles to finish */
+	bne	1b
+
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10       /* Check if PLL is enabled. */
+	beq	lock_end                /* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01       /* Check the LOCK bit.*/
+	beq 2b                      /* loop until bit goes hi. */
+lock_end:
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...                 *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+	/* Set memory timings corresponding to the new clock speed */
+	ldr	r3, VAL_SDRAM_CONFIG_SDF0
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov	r0,	#0x10000000         /* Load physical SDRAM base. */
+	mov	r1,	pc                  /* Get current execution location. */
+	cmp	r1,	r0                  /* Compare. */
+	bge	skip_sdram              /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+	/* identify the device revision, -- TMX or TMP(TMS) */
+	ldr	r0, REG_DEVICE_ID
+	ldr	r1, [r0]
+
+	ldr	r0, VAL_DEVICE_ID_TMP
+	mov	r1, r1, lsl #15
+	mov	r1, r1, lsr #16
+	cmp	r0, r1
+	bne	skip_TMP_Patch
+
+	/* Enable TMP/TMS device new features */
+	mov	r0, #1
+	ldr	r1, REG_TC_EMIFF_DOUBLER
+	str	r0, [r1]
+
+	/* Enable new ac parameters */
+	mov	r0, #0x0b
+	ldr	r1, REG_SDRAM_CONFIG2
+	str	r0, [r1]
+
+	ldr	r3, VAL_SDRAM_CONFIG_SDF1
+
+skip_TMP_Patch:
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r0,	#0x1800		/* value should be checked */
+3:
+	subs	r0,	r0,	#0x1	/* Decrement count */
+	bne	3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	str	r3,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r0,	#0x0100
+waitMDDR2:
+	subs	r0,	r0,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r0,	#0x1800
+4:
+	subs	r0,	r0,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+	ldr	r0,	REG_SDRAM_CONFIG
+	str	r3,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+	ldr	r1,	VAL_TC_EMIFS_DWS
+	ldr	r0,	REG_TC_EMIFS_DWS
+	str	r1,	[r0] /* Enable EMIFS.RDY for CS1 (ether) */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_DEVICE_ID:			/* 32 bits */
+	.word 0xfffe2004
+REG_TC_EMIFS_CONFIG:
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFS_DWS:		/* 32 bits */
+	.word 0xfffecc40
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+REG_SDRAM_CONFIG2:
+	.word 0xfffecc3c
+REG_TC_EMIFF_DOUBLER:		/* 32 bits */
+	.word 0xfffecc60
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002    /* Phase of 72deg, write offset +31  */
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002    /* Phase of 72deg, read offset +31  */
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002    /* read offset +31  */
+
+REG_WATCHDOG:
+	.word 0xfffec808
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec504
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* 96 MHz Samsung Mobile DDR */
+/* Original setting for TMX device */
+VAL_SDRAM_CONFIG_SDF0:
+    .word 0x0014e6fe
+
+/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
+VAL_SDRAM_CONFIG_SDF1:
+    .word 0x0114e6fe
+
+VAL_ARM_CKCTL:
+	.word 0x2000		/* was:	0x3000, now use CLK_REF for timer input */
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_OSK_OMAP5912
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001133
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88013141
+VAL_TC_EMIFS_DWS:	/* Enable EMIFS.RDY for CS1 access (ether) */
+	.word 0x000000c0
+VAL_DEVICE_ID_TMP:	/* TMP/TMS=0xb65f, TMX=0xb58c */
+	.word 0xb65f
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88013141
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+/* command values */
+.equ CMD_SDRAM_NOP,             0x00000000
+.equ CMD_SDRAM_PRECHARGE,       0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,     0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,    0x00000007
diff --git a/u-boot/board/ti/omap5912osk/omap5912osk.c b/u-boot/board/ti/omap5912osk/omap5912osk.c
new file mode 100644
index 0000000..cbf451b
--- /dev/null
+++ b/u-boot/board/ti/omap5912osk/omap5912osk.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Rishi Bhattacharya <rishi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0480000b
+	int i;
+
+	*((volatile unsigned short *) 0xfffece08) = 0x03FF;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8000;
+	*((volatile unsigned short *) 0xfffb3830) = 0x0000;
+	*((volatile unsigned short *) 0xfffb3834) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3838) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3818) = 0x0002;
+	*((volatile unsigned short *) 0xfffb382C) = 0x0048;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8603;
+	udelay (3);
+	for (i=0;i<2000;i++);
+	*((volatile unsigned short *) 0xfffb381C) = 0x6610;
+	udelay (30);
+	for (i=0;i<10000;i++);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+
+
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!	 */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
+	*MuxConfReg |= 0x00000020;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: OSK5912");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ti/omap730p2/Makefile b/u-boot/board/ti/omap730p2/Makefile
new file mode 100644
index 0000000..a04f7aa
--- /dev/null
+++ b/u-boot/board/ti/omap730p2/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= omap730p2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/omap730p2/config.mk b/u-boot/board/ti/omap730p2/config.mk
new file mode 100644
index 0000000..8618820
--- /dev/null
+++ b/u-boot/board/ti/omap730p2/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/u-boot/board/ti/omap730p2/flash.c b/u-boot/board/ti/omap730p2/flash.c
new file mode 100644
index 0000000..5b56b98
--- /dev/null
+++ b/u-boot/board/ti/omap730p2/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/ti/omap730p2/lowlevel_init.S b/u-boot/board/ti/omap730p2/lowlevel_init.S
new file mode 100644
index 0000000..6c574f1
--- /dev/null
+++ b/u-boot/board/ti/omap730p2/lowlevel_init.S
@@ -0,0 +1,395 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003-2004
+ *
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
+ * (http://www.mpc-data.co.uk)
+ *
+ * TODO : Tidy up and change to use system register defines
+ *        from omap730.h where possible.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Save callers address in r11 - r11 must never be modified */
+	mov r11, lr
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1,	#0xffffffff
+	ldr	r0,	=REG_IHL1_MIR
+	str	r1,	[r0]
+	ldr	r0,	=REG_IHL2_MIR
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x1000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Compare physical SDRAM base & current execution location. */
+	and     r0, pc, #0xF0000000
+	/* Compare. */
+	cmp     r0, #0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bne	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne	3b
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_SDRAM_MRS_LEGACY
+	ldr	r1,	SDRAM_MRS_VAL
+	str	r1,	[r0]
+
+skip_sdram:
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS2_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS2_CONFIG
+	str	r1,	[r0] /* Chip Select 2 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+	/* 48MHz clock request for UART1 */
+	ldr	r1,	PERSEUS2_CONFIG_BASE
+	ldrh	r0,	[r1, #CONFIG_PCC_CONF]
+	orr	r0,	r0, #CONF_MOD_UART1_CLK_MODE_R
+	strh	r0,	[r1, #CONFIG_PCC_CONF]
+
+	/* Initialize public and private rheas
+	 *  - set access factor 2 on both rhea / strobe
+	 *  - disable write buffer on strb0, enable write buffer on strb1
+	 */
+
+	ldr	R0,	REG_RHEA_PUB_CTL
+	ldr	R1,	REG_RHEA_PRIV_CTL
+	ldr	R2,	VAL_RHEA_CTL
+	strh	R2,	[R0]
+	strh	R2,	[R1]
+	mov	R3,	#2          /* disable write buffer on strb0, enable write buffer on strb1 */
+	strh	R3,	[R0, #0x08]	/* arm rhea control reg */
+	strh	R3,	[R1, #0x08]
+
+	/* enable IRQ and FIQ */
+
+	mrs	r4,	CPSR
+	bic	r4,	r4, #IRQ_MASK
+	bic	r4,	r4, #FIQ_MASK
+	msr	CPSR,	r4
+
+	/* set TAP CONF to TRI EMULATION */
+
+	ldr	r1,	[r0, #CONFIG_MODE2]
+	bic	r1,	r1, #0x18
+	orr	r1,	r1, #0x10
+	str	r1,	[r0, #CONFIG_MODE2]
+
+	/* set tdbgen to 1 */
+
+	ldr	r0,	PERSEUS2_CONFIG_BASE
+	ldr	r1,	[r0, #CONFIG_MODE1]
+	mov	r2,	#0x10000
+	orr	r1,	r1, r2
+	str	r1,	[r0, #CONFIG_MODE1]
+
+#ifdef CONFIG_P2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	r11
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_P2_OMAP730
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+REG_SDRAM_MRS_LEGACY:
+	.word 0xfffecc24
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec504
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* Public and private rhea bridge registers definition */
+
+REG_RHEA_PUB_CTL:
+	.word 0xFFFECA00
+
+REG_RHEA_PRIV_CTL:
+	.word 0xFFFED300
+
+/* EMIFF SDRAM Configuration register
+   - self refresh disable
+   - auto refresh enabled
+   - SDRAM type 64 Mb, 16 bits bus 4 banks
+   - power down enabled
+   - SDRAM clock disabled
+ */
+SDRAM_CONFIG_VAL:
+	.word 0x0C017DF4
+
+/* Burst full page length ; cas latency = 3 */
+SDRAM_MRS_VAL:
+	.word 0x00000037
+
+VAL_ARM_CKCTL:
+	.word 0x6505
+VAL_DPLL1_CTL:
+	.word 0x3412
+
+#ifdef CONFIG_P2_OMAP730
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x0000FFF3
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+VAL_RHEA_CTL:
+	.word			0xFF22
+
+/* Config Register vals */
+PERSEUS2_CONFIG_BASE:
+	.word			0xFFFE1000
+
+.equ	CONFIG_PCC_CONF,	0xB4
+.equ	CONFIG_MODE1,		0x10
+.equ	CONFIG_MODE2,		0x14
+.equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A
+
+/* misc values */
+.equ	IRQ_MASK,		0x80           /* IRQ mask value */
+.equ	FIQ_MASK,		0x40           /* FIQ mask value */
diff --git a/u-boot/board/ti/omap730p2/omap730p2.c b/u-boot/board/ti/omap730p2/omap730p2.c
new file mode 100644
index 0000000..954ced5
--- /dev/null
+++ b/u-boot/board/ti/omap730p2/omap730p2.c
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int test_boot_mode(void);
+void spin_up_leds(void);
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define FLASH_ON_CS0	1
+#define FLASH_ON_CS3	0
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+int test_boot_mode(void)
+{
+	/* Check for CS0 and CS3 address decode swapping */
+	if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
+		return(FLASH_ON_CS3);
+	else
+		return(FLASH_ON_CS0);
+}
+
+/* Toggle backup LED indication */
+void toggle_backup_led(void)
+{
+	static int  backupLEDState = 0;	 /* Init variable so that the LED will be ON the first time */
+	volatile unsigned int *IOConfReg;
+
+
+	IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
+
+	if (backupLEDState != 0) {
+		*IOConfReg &= (0xFFFFEFFF);
+		backupLEDState = 0;
+	} else {
+		*IOConfReg |= (0x00001000);
+		backupLEDState = 1;
+	}
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+
+	peripheral_power_enable ();
+
+	/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
+	toggle_backup_led();
+
+	/* Hold GSM in reset until needed */
+	*((volatile unsigned short *)M_CTL) &= ~1;
+
+	/*
+	 *  CSx timings, GPIO Mux ... setup
+	 */
+
+	/* Flash: CS0 timings setup */
+	*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
+	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
+
+	/* Ethernet support trough the debug board */
+	/* CS1 timings setup */
+	*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
+	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
+
+	/* this speeds up your boot a quite a bit.  However to make it
+	 *  work, you need make sure your kernel startup flush bug is fixed.
+	 *  ... rkw ...
+	 */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+	unsigned int regval;
+
+	regval = *((volatile unsigned int *) EMIFS_CONFIG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_CONFIG) = regval;
+}
+
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define LAN_RESET_REGISTER 0x0400001c
+
+	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+		udelay (100);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+		udelay (100);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+
+#define ETH_CONTROL_REG 0x0400030b
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (100);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+
+	/*
+	 *  Backup LED Indication
+	 */
+
+	/* Configure MUXed pin. Mode 6: GPIO_140 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
+	*MuxConfReg &= (0xFFFFFF1F);	     /* Clear D_MPU_LPG1 */
+	*MuxConfReg |= 0x000000C0;	     /* Set D_MPU_LPG1 to 0x6 */
+
+	/* Configure GPIO_140 as output */
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
+	*MuxConfReg &= (0xFFFFEFFF);	     /* Clear direction (output) for GPIO 140 */
+
+	/*
+	 * Configure GPIOs for battery charge & feedback
+	 */
+
+	/* Configure MUXed pin. Mode 6: GPIO_35 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+	*MuxConfReg &= 0xFFFFFFF1;	     /* Clear M_CLK_OUT */
+	*MuxConfReg |= 0x0000000C;	     /* Set M_CLK_OUT = 0x6 (GPIOs) */
+
+	/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
+	*MuxConfReg &= 0xFFFF1FFF;	     /* Clear D_DDR */
+	*MuxConfReg |= 0x0000C000;	     /* Set D_DDR = 0x6 (GPIOs) */
+
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
+	*MuxConfReg |= 0x00000100;	     /* Configure GPIO_72 as input */
+	*MuxConfReg &= 0xFFFFFDFF;	     /* Configure GPIO_73 as output	*/
+
+	/*
+	 * Allow battery charge
+	 */
+
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
+	*MuxConfReg &= (0xFFFFFDFF);	     /* Clear GPIO_73 pin */
+
+	/*
+	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+	 * It is used as the Ethernet controller interrupt
+	 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
+	*MuxConfReg &= 0x1FFFFFFF;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+	volatile unsigned int *MuxConfReg;
+
+
+	/* Set up pins used by UART */
+
+	/* Start UART clock (48MHz) */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
+	*MuxConfReg &= (0xFFFFFFF7);
+	*MuxConfReg |= (0x00000008);
+
+	/* Get the UART pin in mode0  */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+	*MuxConfReg &= (0xFF1FFFFF);
+	*MuxConfReg &= (0xF1FFFFFF);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/ti/panda/Makefile b/u-boot/board/ti/panda/Makefile
new file mode 100644
index 0000000..2186403
--- /dev/null
+++ b/u-boot/board/ti/panda/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= panda.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/panda/config.mk b/u-boot/board/ti/panda/config.mk
new file mode 100644
index 0000000..33901a7
--- /dev/null
+++ b/u-boot/board/ti/panda/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 4430 SDP
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/u-boot/board/ti/panda/panda.c b/u-boot/board/ti/panda/panda.c
new file mode 100644
index 0000000..78e1910
--- /dev/null
+++ b/u-boot/board/ti/panda/panda.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "panda.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4 Panda\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure Panda board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the board.
+ */
+void set_muxconf_regs(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
+		   sizeof(core_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
+		   sizeof(wkup_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/ti/panda/panda.h b/u-boot/board/ti/panda/panda.h
new file mode 100644
index 0000000..e3d090e
--- /dev/null
+++ b/u-boot/board/ti/panda/panda.h
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PANDA_H_
+#define _PANDA_H_
+
+#include <asm/io.h>
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array[] = {
+	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
+	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
+	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
+	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
+	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
+	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
+	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
+	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
+	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
+	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
+	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
+	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
+	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
+	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
+	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
+	{GPMC_A16, (M3)},						/* gpio_40 */
+	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
+	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
+	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
+	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
+	{GPMC_A21, (M3)},						/* gpio_45 */
+	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
+	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
+	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
+	{GPMC_NCS0, (M3)},						/* gpio_50 */
+	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
+	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
+	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
+	{GPMC_NWP, (M3)},						/* gpio_54 */
+	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
+	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
+	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
+	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
+	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
+	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
+	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
+	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
+	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
+	{C2C_DATA14, (M1)},						/* dsi2_te0 */
+	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
+	{HDMI_HPD, (M0)},						/* hdmi_hpd */
+	{HDMI_CEC, (M0)},						/* hdmi_cec */
+	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
+	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
+	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
+	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
+	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
+	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
+	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
+	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
+	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
+	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
+	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
+	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
+	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
+	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
+	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
+	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
+	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
+	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
+	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
+	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
+	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
+	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
+	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
+	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
+	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
+	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
+	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
+	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
+	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
+	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
+	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
+	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
+	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
+	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
+	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
+	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
+	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
+	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
+	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
+	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
+	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
+	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
+	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
+	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
+	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
+	{UART2_RTS, (M0)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
+	{UART2_TX, (M0)},						/* uart2_tx */
+	{HDQ_SIO, (M3)},						/* gpio_127 */
+	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
+	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
+	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
+	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
+	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
+	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
+	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
+	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
+	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
+	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
+	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
+	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
+	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
+	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
+	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
+	{UART4_RX, (IEN | M0)},						/* uart4_rx */
+	{UART4_TX, (M0)},						/* uart4_tx */
+	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
+	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
+	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
+	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
+	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
+	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
+	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
+	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
+	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
+	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
+	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
+	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
+	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
+	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
+	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
+	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
+	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
+	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
+	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
+	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
+	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
+	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
+	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
+	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
+	{SYS_BOOT1, (M3)},						/* gpio_185 */
+	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
+	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT4, (M3)},						/* gpio_188 */
+	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
+	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
+	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
+	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
+	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
+	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
+	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
+	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
+	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
+	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
+	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
+	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
+	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
+	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
+	{DPM_EMU16, (M3)},						/* gpio_27 */
+	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
+	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
+	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
+};
+
+const struct pad_conf_entry wkup_padconf_array[] = {
+	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
+	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
+	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
+	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
+	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
+	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
+	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
+	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
+	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+};
+
+#endif
diff --git a/u-boot/board/ti/sdp3430/Makefile b/u-boot/board/ti/sdp3430/Makefile
new file mode 100644
index 0000000..bce8534
--- /dev/null
+++ b/u-boot/board/ti/sdp3430/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sdp.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/sdp3430/config.mk b/u-boot/board/ti/sdp3430/config.mk
new file mode 100644
index 0000000..be46298
--- /dev/null
+++ b/u-boot/board/ti/sdp3430/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/u-boot/board/ti/sdp3430/sdp.c b/u-boot/board/ti/sdp3430/sdp.c
new file mode 100644
index 0000000..72f0984
--- /dev/null
+++ b/u-boot/board/ti/sdp3430/sdp.c
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "sdp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"OMAP3 SDP3430 board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+	"NAND",
+#else
+	"NOR",
+#endif
+};
+
+/* Timing definitions for GPMC controller for Sibley NOR */
+static const u32 gpmc_sdp_nor[] = {
+    SDP3430_NOR_GPMC_CONF1,
+    SDP3430_NOR_GPMC_CONF2,
+    SDP3430_NOR_GPMC_CONF3,
+    SDP3430_NOR_GPMC_CONF4,
+    SDP3430_NOR_GPMC_CONF5,
+    SDP3430_NOR_GPMC_CONF6,
+    /*CONF7- computed as params */
+};
+
+/*
+ * Timing definitions for GPMC controller for Debug Board
+ * Debug board contains access to ethernet and DIP Switch setting
+ * information etc.
+ */
+static const u32 gpmc_sdp_debug[] = {
+    SDP3430_DEBUG_GPMC_CONF1,
+    SDP3430_DEBUG_GPMC_CONF2,
+    SDP3430_DEBUG_GPMC_CONF3,
+    SDP3430_DEBUG_GPMC_CONF4,
+    SDP3430_DEBUG_GPMC_CONF5,
+    SDP3430_DEBUG_GPMC_CONF6,
+    /*CONF7- computed as params */
+};
+
+/* Timing defintions for GPMC OneNAND */
+static const u32 gpmc_sdp_onenand[] = {
+    SDP3430_ONENAND_GPMC_CONF1,
+    SDP3430_ONENAND_GPMC_CONF2,
+    SDP3430_ONENAND_GPMC_CONF3,
+    SDP3430_ONENAND_GPMC_CONF4,
+    SDP3430_ONENAND_GPMC_CONF5,
+    SDP3430_ONENAND_GPMC_CONF6,
+    /*CONF7- computed as params */
+};
+
+/* GPMC definitions for GPMC NAND */
+static const u32 gpmc_sdp_nand[] = {
+    SDP3430_NAND_GPMC_CONF1,
+    SDP3430_NAND_GPMC_CONF2,
+    SDP3430_NAND_GPMC_CONF3,
+    SDP3430_NAND_GPMC_CONF4,
+    SDP3430_NAND_GPMC_CONF5,
+    SDP3430_NAND_GPMC_CONF6,
+    /*CONF7- computed as params */
+};
+
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/**
+ * @brief board_init - gpmc and basic setup as phase1 of boot sequence
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* TODO: Dynamically pop out CS mapping and program accordingly */
+	/* Configure devices for default ON ON ON settings */
+	enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
+			CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
+	enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
+			GPMC_SIZE_16M);
+	enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
+			GPMC_SIZE_16M);
+	enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
+			GPMC_SIZE_16M);
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+#define LAN_RESET_REGISTER	(CONFIG_LAN91C96_BASE + 0x01c)
+#define ETH_CONTROL_REG		(CONFIG_LAN91C96_BASE + 0x30b)
+
+/**
+ * @brief board_eth_init Take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete.
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	int cnt = 20;
+
+	writew(0x0, LAN_RESET_REGISTER);
+	do {
+		writew(0x1, LAN_RESET_REGISTER);
+		udelay(100);
+		if (cnt == 0)
+			goto reset_err_out;
+		--cnt;
+	} while (readw(LAN_RESET_REGISTER) != 0x1);
+
+	cnt = 20;
+
+	do {
+		writew(0x0, LAN_RESET_REGISTER);
+		udelay(100);
+		if (cnt == 0)
+			goto reset_err_out;
+		--cnt;
+	} while (readw(LAN_RESET_REGISTER) != 0x0000);
+	udelay(1000);
+
+	writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
+	udelay(1000);
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+reset_err_out:
+
+#endif
+	return rc;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+	/* Partial setup:
+	 *   VAUX3 - 2.8V for DVI
+	 *   VPLL1 - 1.8V
+	 *   VDAC  - 1.8V
+	 * and turns on LEDA/LEDB (not needed ... NOP?)
+	 */
+	twl4030_power_init();
+
+	/* FIXME finish setup:
+	 *   VAUX1 - 2.8V for mainboard I/O
+	 *   VAUX2 - 2.8V for camera
+	 *   VAUX4 - 1.8V for OMAP3 CSI
+	 *   VMMC1 - 3.15V (init, variable) for MMC1
+	 *   VMMC2 - 1.85V for MMC2
+	 *   VSIM  - off (init, variable) for MMC1.DAT[3..7], SIM
+	 *   VPLL2 - 1.8V
+	 */
+
+	return 0;
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need to be moved from protect
+ * to primary mode.
+ */
+void set_muxconf_regs(void)
+{
+	/* platform specific muxes */
+	MUX_SDP3430();
+}
diff --git a/u-boot/board/ti/sdp3430/sdp.h b/u-boot/board/ti/sdp3430/sdp.h
new file mode 100644
index 0000000..3526e94
--- /dev/null
+++ b/u-boot/board/ti/sdp3430/sdp.h
@@ -0,0 +1,417 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BOARD_SDP_H_
+#define _BOARD_SDP_H_
+
+#define OFF_IN_PD	0
+#define OFF_OUT_PD	0
+
+/*
+ * IEN	- Input Enable
+ * IDIS	- Input Disable
+ * PTD	- Pull type Down
+ * PTU	- Pull type Up
+ * DIS	- Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_SDP3430()\
+	/*SDRC*/\
+	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
+	/*GPMC*/\
+	MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
+	MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
+	MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
+	MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
+	MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
+	MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
+	MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
+	/*DSS*/\
+	MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	/*CAMERA*/\
+	MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
+	MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
+	MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
+	MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	/*Audio InterfACe */\
+	MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	/*Expansion Card */\
+	MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	/*Wireless LAN */\
+	MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
+	MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
+	MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
+	MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
+	/*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	/*Modem Interface */\
+	MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
+	MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
+	MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
+	MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
+	MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
+	MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
+	MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
+	MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	/*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	/* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
+	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
+	MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
+	MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
+	MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	/*Control and debug */\
+	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
+	MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
+	MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
+	MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
+	MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
+	MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
+	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
+	MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
+	MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
+	MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
+	MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
+	MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	/*Die to Die */\
+	MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
+	MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
+	MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
+
+/*
+ * GPMC Timing definitions for SDP3430
+ * at L3 = 166Mhz
+ */
+
+/* Timing definitions for GPMC controller for Sibley NOR */
+#define SDP3430_NOR_GPMC_CONF1 0x00001200
+#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
+#define SDP3430_NOR_GPMC_CONF3 0x00080802
+#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
+#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
+#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
+
+/*
+ * Timing definitions for GPMC controller for Debug Board
+ * Debug board contains access to ethernet and DIP Switch setting
+ * information etc.
+ */
+#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
+#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
+#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
+#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
+#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
+#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
+
+/* Timing defintions for GPMC OneNAND */
+#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
+#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
+#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
+#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
+#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
+#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
+
+/* GPMC definitions for GPMC NAND */
+#define SDP3430_NAND_GPMC_CONF1 0x00000800
+#define SDP3430_NAND_GPMC_CONF2 0x00141400
+#define SDP3430_NAND_GPMC_CONF3 0x00141400
+#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
+#define SDP3430_NAND_GPMC_CONF5 0x010C1414
+#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
+
+#endif /* _BOARD_SDP_H_ */
diff --git a/u-boot/board/ti/sdp4430/Makefile b/u-boot/board/ti/sdp4430/Makefile
new file mode 100644
index 0000000..f1ee544
--- /dev/null
+++ b/u-boot/board/ti/sdp4430/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= sdp.o cmd_bat.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/sdp4430/cmd_bat.c b/u-boot/board/ti/sdp4430/cmd_bat.c
new file mode 100644
index 0000000..fe33538
--- /dev/null
+++ b/u-boot/board/ti/sdp4430/cmd_bat.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BAT
+#include <twl6030.h>
+
+int do_vbat(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc == 2) {
+		if (strncmp(argv[1], "startcharge", 12) == 0)
+			twl6030_start_usb_charging();
+		else if (strncmp(argv[1], "stopcharge", 11) == 0)
+			twl6030_stop_usb_charging();
+		else if (strncmp(argv[1], "status", 7) == 0) {
+			twl6030_get_battery_voltage();
+			twl6030_get_battery_current();
+		} else {
+			goto bat_cmd_usage;
+		}
+	} else {
+		goto bat_cmd_usage;
+	}
+	return 0;
+
+bat_cmd_usage:
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	bat, 2, 1, do_vbat,
+	"battery charging, voltage/current measurements",
+	"status - display battery voltage and current\n"
+	"bat startcharge - start charging via USB\n"
+	"bat stopcharge - stop charging\n"
+);
+#endif /* CONFIG_BAT_CMD */
diff --git a/u-boot/board/ti/sdp4430/config.mk b/u-boot/board/ti/sdp4430/config.mk
new file mode 100644
index 0000000..33901a7
--- /dev/null
+++ b/u-boot/board/ti/sdp4430/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 4430 SDP
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/u-boot/board/ti/sdp4430/sdp.c b/u-boot/board/ti/sdp4430/sdp.c
new file mode 100644
index 0000000..b13c4c5
--- /dev/null
+++ b/u-boot/board/ti/sdp4430/sdp.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl6030.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "sdp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4430 SDP\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6030_POWER
+	twl6030_init_battery_charging();
+#endif
+	return 0;
+}
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the board.
+ */
+void set_muxconf_regs(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
+		   sizeof(core_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
+		   sizeof(wkup_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
diff --git a/u-boot/board/ti/sdp4430/sdp.h b/u-boot/board/ti/sdp4430/sdp.h
new file mode 100644
index 0000000..bf41067
--- /dev/null
+++ b/u-boot/board/ti/sdp4430/sdp.h
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDP_H_
+#define _SDP_H_
+
+#include <asm/io.h>
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array[] = {
+	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
+	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
+	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
+	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
+	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
+	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
+	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
+	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
+	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
+	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
+	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
+	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
+	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
+	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
+	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
+	{GPMC_A16, (M3)},						/* gpio_40 */
+	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
+	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
+	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
+	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
+	{GPMC_A21, (M3)},						/* gpio_45 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
+	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
+	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
+	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
+	{GPMC_NCS0, (M3)},						/* gpio_50 */
+	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
+	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
+	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
+	{GPMC_NWP, (M3)},						/* gpio_54 */
+	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
+	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
+	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
+	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
+	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
+	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
+	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
+	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
+	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
+	{C2C_DATA14, (M1)},						/* dsi2_te0 */
+	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
+	{HDMI_HPD, (M0)},						/* hdmi_hpd */
+	{HDMI_CEC, (M0)},						/* hdmi_cec */
+	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
+	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
+	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
+	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
+	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
+	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
+	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
+	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
+	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
+	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
+	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
+	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
+	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
+	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
+	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
+	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
+	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
+	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
+	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
+	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
+	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
+	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
+	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
+	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
+	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
+	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
+	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
+	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
+	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
+	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
+	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
+	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
+	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
+	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
+	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
+	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
+	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
+	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
+	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
+	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
+	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
+	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
+	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
+	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
+	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
+	{UART2_RTS, (M0)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
+	{UART2_TX, (M0)},						/* uart2_tx */
+	{HDQ_SIO, (M3)},						/* gpio_127 */
+	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
+	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
+	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
+	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
+	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
+	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
+	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
+	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
+	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
+	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
+	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
+	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
+	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
+	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
+	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
+	{UART4_RX, (IEN | M0)},						/* uart4_rx */
+	{UART4_TX, (M0)},						/* uart4_tx */
+	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
+	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
+	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
+	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
+	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
+	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
+	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
+	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
+	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
+	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
+	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
+	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
+	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
+	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
+	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
+	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
+	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
+	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
+	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
+	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
+	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
+	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
+	{SYS_BOOT1, (M3)},						/* gpio_185 */
+	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
+	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT4, (M3)},						/* gpio_188 */
+	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
+	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
+	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
+	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
+	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
+	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
+	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
+	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
+	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
+	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
+	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
+	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
+	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
+	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
+	{DPM_EMU16, (M3)},						/* gpio_27 */
+	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
+	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
+	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
+};
+
+const struct pad_conf_entry wkup_padconf_array[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
+	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+};
+
+#endif
diff --git a/u-boot/board/ti/tnetv107xevm/Makefile b/u-boot/board/ti/tnetv107xevm/Makefile
new file mode 100644
index 0000000..03238f0
--- /dev/null
+++ b/u-boot/board/ti/tnetv107xevm/Makefile
@@ -0,0 +1,49 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS		+= sdb_board.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+.PHONY: all
+
+all: $(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ti/tnetv107xevm/config.mk b/u-boot/board/ti/tnetv107xevm/config.mk
new file mode 100644
index 0000000..79b8304
--- /dev/null
+++ b/u-boot/board/ti/tnetv107xevm/config.mk
@@ -0,0 +1,20 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+CONFIG_SYS_TEXT_BASE = 0x83FC0000
diff --git a/u-boot/board/ti/tnetv107xevm/sdb_board.c b/u-boot/board/ti/tnetv107xevm/sdb_board.c
new file mode 100644
index 0000000..3ed1cfd
--- /dev/null
+++ b/u-boot/board/ti/tnetv107xevm/sdb_board.c
@@ -0,0 +1,149 @@
+/*
+ * TNETV107X-EVM: Board initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <linux/mtd/nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
+	{			/* CS0 */
+		.mode		= ASYNC_EMIF_MODE_NAND,
+		.wr_setup	= 5,
+		.wr_strobe	= 5,
+		.wr_hold	= 2,
+		.rd_setup	= 5,
+		.rd_strobe	= 5,
+		.rd_hold	= 2,
+		.turn_around	= 5,
+		.width		= ASYNC_EMIF_8,
+	},
+	{			/* CS1 */
+		.mode		= ASYNC_EMIF_MODE_NOR,
+		.wr_setup	= 2,
+		.wr_strobe	= 27,
+		.wr_hold	= 4,
+		.rd_setup	= 2,
+		.rd_strobe	= 27,
+		.rd_hold	= 4,
+		.turn_around	= 2,
+		.width		= ASYNC_EMIF_PRESERVE,
+	},
+	{			/* CS2 */
+		.mode		= ASYNC_EMIF_MODE_NOR,
+		.wr_setup	= 2,
+		.wr_strobe	= 27,
+		.wr_hold	= 4,
+		.rd_setup	= 2,
+		.rd_strobe	= 27,
+		.rd_hold	= 4,
+		.turn_around	= 2,
+		.width		= ASYNC_EMIF_PRESERVE,
+	},
+	{			/* CS3 */
+		.mode		= ASYNC_EMIF_MODE_NOR,
+		.wr_setup	= 1,
+		.wr_strobe	= 90,
+		.wr_hold	= 3,
+		.rd_setup	= 1,
+		.rd_strobe	= 26,
+		.rd_hold	= 3,
+		.turn_around	= 1,
+		.width		= ASYNC_EMIF_8,
+	},
+};
+
+static struct pll_init_data pll_config[] = {
+	{
+		.pll			= ETH_PLL,
+		.internal_osc		= 1,
+		.pll_freq		= 500000000,
+		.div_freq = {
+			5000000, 50000000, 125000000, 250000000, 25000000,
+		},
+	},
+};
+
+static const short sdio1_pins[] = {
+	TNETV107X_PIN_SDIO1_CLK_1,	TNETV107X_PIN_SDIO1_CMD_1,
+	TNETV107X_PIN_SDIO1_DATA0_1,	TNETV107X_PIN_SDIO1_DATA1_1,
+	TNETV107X_PIN_SDIO1_DATA2_1,	TNETV107X_PIN_SDIO1_DATA3_1,
+	-1
+};
+
+static const short uart1_pins[] = {
+	TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
+};
+
+static const short ssp_pins[] = {
+	TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
+	TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
+	TNETV107X_PIN_SSP1_3, -1
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	__raw_writel(0, INTC_GLB_EN);		/* Global disable       */
+	__raw_writel(0, INTC_HINT_EN);		/* Disable host ints    */
+	__raw_writel(0, INTC_EN_CLR0 + 0);	/* Clear enable         */
+	__raw_writel(0, INTC_EN_CLR0 + 4);	/* Clear enable         */
+	__raw_writel(0, INTC_EN_CLR0 + 8);	/* Clear enable         */
+#endif
+
+	gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	init_plls(ARRAY_SIZE(pll_config), pll_config);
+
+	init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
+
+	mux_select_pin(TNETV107X_PIN_ASR_CS3);
+	mux_select_pins(sdio1_pins);
+	mux_select_pins(uart1_pins);
+	mux_select_pins(ssp_pins);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/timll/devkit8000/Makefile b/u-boot/board/timll/devkit8000/Makefile
new file mode 100644
index 0000000..3f160b2
--- /dev/null
+++ b/u-boot/board/timll/devkit8000/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= devkit8000.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/timll/devkit8000/devkit8000.c b/u-boot/board/timll/devkit8000/devkit8000.c
new file mode 100644
index 0000000..95afaaa
--- /dev/null
+++ b/u-boot/board/timll/devkit8000/devkit8000.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/mach-types.h>
+#include "devkit8000.h"
+#ifdef CONFIG_DRIVER_DM9000
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+#ifdef CONFIG_DRIVER_DM9000
+	uchar enetaddr[6];
+	u32 die_id_0;
+#endif
+
+	twl4030_power_init();
+#ifdef CONFIG_TWL4030_LED
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+	/* Configure GPMC registers for DM9000 */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
+
+	/* Use OMAP DIE_ID as MAC address */
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		printf("ethaddr not set, using Die ID\n");
+		die_id_0 = readl(&id_base->die_id_0);
+		enetaddr[0] = 0x02; /* locally administered */
+		enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
+		enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
+		enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
+		enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
+		enetaddr[5] = (die_id_0 & 0x000000ff);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEVKIT8000();
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+/*
+ * Routine: board_eth_init
+ * Description: Setting up the Ethernet hardware.
+ */
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/timll/devkit8000/devkit8000.h b/u-boot/board/timll/devkit8000/devkit8000.h
new file mode 100644
index 0000000..aa69e6c
--- /dev/null
+++ b/u-boot/board/timll/devkit8000/devkit8000.h
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DEVKIT8000_H_
+#define _DEVKIT8000_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 DevKit8000",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEVKIT8000() \
+ /* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0 NAND*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS6 DM9000*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ /* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /* Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /* MMC Slot */\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /* Expansion Header */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+	MUX_VAL(CP(UART2_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+	MUX_VAL(CP(UART2_RX),		(IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*GPIO_148*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*GPIO_151*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*GPIO_152*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*GPIO_153*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*GPIO_154*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*GPIO_155*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*GPIO_160*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /* Serial Interface */\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS | PTD | EN  | M4)) /*GPIO_163 - LED2*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)) /*GPIO_164 - LED3*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ /* Host USB0 */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IDIS | PTU | DIS | M4)) /*GPIO_168*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | DIS | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTD | DIS | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M4)) /*GPIO_171*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M4)) /*GPIO_172*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | DIS | M0)) /*MCSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | EN  | M0)) /*SYS_CLKOUT1*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | EN  | M4)) /*GPIO_186 - LED1*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | EN  | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_24*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_25*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_26*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_27*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_28*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_29*/\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*D2D_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*D2D_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*D2D_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*D2D_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*D2D_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*D2D_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*D2D_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*D2D_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*D2D_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*D2D_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*D2D_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*D2D_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*D2D_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*D2D_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
+#endif
diff --git a/u-boot/board/total5200/Makefile b/u-boot/board/total5200/Makefile
new file mode 100644
index 0000000..066d9ca
--- /dev/null
+++ b/u-boot/board/total5200/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/total5200/mt48lc16m16a2-75.h b/u-boot/board/total5200/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..ae237c6
--- /dev/null
+++ b/u-boot/board/total5200/mt48lc16m16a2-75.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/total5200/mt48lc32m16a2-75.h b/u-boot/board/total5200/mt48lc32m16a2-75.h
new file mode 100644
index 0000000..cb4b43d
--- /dev/null
+++ b/u-boot/board/total5200/mt48lc32m16a2-75.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Micron MT48LC32M16A2-75 is compatible to:
+ *  - Infineon HYB39S512160AT-75
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x514F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/u-boot/board/total5200/sdram.c b/u-boot/board/total5200/sdram.c
new file mode 100644
index 0000000..d883eb6
--- /dev/null
+++ b/u-boot/board/total5200/sdram.c
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+#include "sdram.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	if (sdram_conf->ddr) {
+		/* set mode register: extended mode */
+		*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
+		__asm__ volatile ("sync");
+
+		/* set mode register: reset DLL */
+		*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
+		__asm__ volatile ("sync");
+	}
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
+	__asm__ volatile ("sync");
+
+	if (sdram_conf->ddr) {
+		/* set tap delay */
+		*(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
+		__asm__ volatile ("sync");
+	}
+
+	/* find RAM size using SDRAM CS0 only */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
diff --git a/u-boot/board/total5200/sdram.h b/u-boot/board/total5200/sdram.h
new file mode 100644
index 0000000..396a190
--- /dev/null
+++ b/u-boot/board/total5200/sdram.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct {
+	ulong ddr;
+	ulong mode;
+	ulong emode;
+	ulong control;
+	ulong config1;
+	ulong config2;
+	ulong tapdelay;
+} sdram_conf_t;
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/u-boot/board/total5200/total5200.c b/u-boot/board/total5200/total5200.c
new file mode 100644
index 0000000..61b5b80
--- /dev/null
+++ b/u-boot/board/total5200/total5200.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#include "sdram.h"
+
+#if CONFIG_TOTAL5200_REV==2
+#include "mt48lc32m16a2-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+phys_size_t initdram (int board_type)
+{
+	sdram_conf_t sdram_conf;
+
+	sdram_conf.ddr = SDRAM_DDR;
+	sdram_conf.mode = SDRAM_MODE;
+	sdram_conf.emode = 0;
+	sdram_conf.control = SDRAM_CONTROL;
+	sdram_conf.config1 = SDRAM_CONFIG1;
+	sdram_conf.config2 = SDRAM_CONFIG2;
+	sdram_conf.tapdelay = 0;
+	return mpc5xxx_sdram_init (&sdram_conf);
+}
+
+int checkboard (void)
+{
+#if CONFIG_TOTAL5200_REV==2
+	puts ("Board: Total5200 Rev.2 ");
+#else
+	puts ("Board: Total5200 ");
+#endif
+
+	/*
+	 * Retrieve FPGA Revision.
+	 */
+	printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
+
+	/*
+	 * Take all peripherals in power-up mode.
+	 */
+#if CONFIG_TOTAL5200_REV==2
+	*(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
+#else
+	*(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
+#endif
+
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+/* IRDA_1 aka PSC6_3 (pin C13) */
+#define GPIO_IRDA_1	0x20000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
+	*(vu_long *) MPC5XXX_GPIO_DIR    |= GPIO_IRDA_1;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
+	} else {
+		*(vu_long *) MPC5XXX_GPIO_DATA_O |=  GPIO_IRDA_1;
+	}
+}
+#endif
+
+#ifdef CONFIG_VIDEO_SED13806
+#include <sed13806.h>
+
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SED13806_8BPP
+#error CONFIG_VIDEO_SED13806_8BPP not supported.
+#endif /* CONFIG_VIDEO_SED13806_8BPP */
+
+#ifdef CONFIG_VIDEO_SED13806_16BPP
+static const S1D_REGS init_regs [] =
+{
+    {0x0001,0x00},   /* Miscellaneous Register */
+    {0x01FC,0x00},   /* Display Mode Register */
+    {0x0004,0x00},   /* General IO Pins Configuration Register 0 */
+    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+    {0x0008,0x00},   /* General IO Pins Control Register 0 */
+    {0x0009,0x00},   /* General IO Pins Control Register 1 */
+    {0x0010,0x02},   /* Memory Clock Configuration Register */
+    {0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+    {0x0021,0x03},   /* DRAM Refresh Rate Register */
+    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
+    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
+    {0x0020,0x80},   /* Memory Configuration Register */
+    {0x0030,0x25},   /* Panel Type Register */
+    {0x0031,0x00},   /* MOD Rate Register */
+    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
+    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+    {0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+    {0x0040,0x05},   /* LCD Display Mode Register */
+    {0x0041,0x00},   /* LCD Miscellaneous Register */
+    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
+    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
+    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
+    {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+    {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+    {0x0048,0x00},   /* LCD Pixel Panning Register */
+    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+    {0x005B,0x10},   /* TV Output Control Register */
+    {0x0060,0x05},   /* CRT/TV Display Mode Register */
+    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+    {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+    {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+    {0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+    {0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+    {0x0100,0x00},   /* BitBlt Control Register 0 */
+    {0x0101,0x00},   /* BitBlt Control Register 1 */
+    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+    {0x0103,0x00},   /* BitBlt Operation Register */
+    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+    {0x0110,0x00},   /* BitBlt Width Register 0 */
+    {0x0111,0x00},   /* BitBlt Width Register 1 */
+    {0x0112,0x00},   /* BitBlt Height Register 0 */
+    {0x0113,0x00},   /* BitBlt Height Register 1 */
+    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
+    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
+    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+    {0x01E0,0x00},   /* Look-Up Table Mode Register */
+    {0x01E2,0x00},   /* Look-Up Table Address Register */
+    {0x01E4,0x00},   /* Look-Up Table Data Register */
+    {0x01F0,0x00},   /* Power Save Configuration Register */
+    {0x01F1,0x00},   /* Power Save Status Register */
+    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+    {0x01FC,0x01},   /* Display Mode Register */
+    {0, 0}
+};
+#endif /* CONFIG_VIDEO_SED13806_16BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/* Return text to be printed besides the logo. */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+#if CONFIG_TOTAL5200_REV==1
+		strcpy (info, " Total5200");
+#elif CONFIG_TOTAL5200_REV==2
+		strcpy (info, " Total5200 Rev.2");
+#else
+#error CONFIG_TOTAL5200_REV must be 1 or 2.
+#endif
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/* Returns  SED13806 base address. First thing called in the driver. */
+unsigned int board_video_init (void)
+{
+	return CONFIG_SYS_LCD_BASE;
+}
+
+/* Called after initializing the SED13806 and before clearing the screen. */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/* Return a pointer to the initialization sequence. */
+const S1D_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SED13806 */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/tqc/tqm5200/Makefile b/u-boot/board/tqc/tqm5200/Makefile
new file mode 100644
index 0000000..d0e68c3
--- /dev/null
+++ b/u-boot/board/tqc/tqm5200/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+cam5200_flash.o:	cam5200_flash.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tqc/tqm5200/cam5200_flash.c b/u-boot/board/tqc/tqm5200/cam5200_flash.c
new file mode 100644
index 0000000..4c8922f
--- /dev/null
+++ b/u-boot/board/tqc/tqm5200/cam5200_flash.c
@@ -0,0 +1,790 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
+
+#if 0
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif
+
+#define swap16(x) __swab16(x)
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*
+ * CAM5200 is a TQM5200B based board. Additionally it also features
+ * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
+ * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
+ * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
+ * access to flash chip slightly more complicated as additional byte
+ * swapping is necessary within each 16 bit wide flash 'word'.
+ *
+ * This driver's task is to handle both flash devices: 32 bit TQM5200B
+ * flash chip and 16 bit NIOS cpu flash chip. In the below
+ * flash_addr_table table we use least significant address bit to mark
+ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
+ * specifics of both flashes.
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_32(flash_info_t * info, ulong dest, ulong data);
+static int write_word_16(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i, k;
+	int size, erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf("AMD ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf("FUJITSU ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_S29GL128N:
+			printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_AM320B:
+			printf ("29LV320B (32 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM320T:
+			printf ("29LV320T (32 Mbit, top boot sect)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s%s", info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+
+	DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
+
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1)
+		return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
+	else
+		return flash_get_size_32(addr, info);
+}
+
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case AMD_ID_MIRROR:
+			DEBUGF("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+					addr[14], addr[15]);
+			switch(addr[14]) {
+				case AMD_ID_GL128N_2:
+					if (addr[15] != AMD_ID_GL128N_3) {
+						DEBUGF("Chip: S29GL128N -> unknown\n");
+						info->flash_id = FLASH_UNKNOWN;
+					} else {
+						DEBUGF("Chip: S29GL128N\n");
+						info->flash_id += FLASH_S29GL128N;
+						info->sector_count = 128;
+						info->size = 0x02000000;
+					}
+					break;
+				default:
+					info->flash_id = FLASH_UNKNOWN;
+					return(0);
+			}
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00040000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+		return flash_erase_16(info, s_first, s_last);
+	} else {
+		return flash_erase_32(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_32(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < 4; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i)
+			data = (data << 8) | *src++;
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *) cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+		return write_word_16(info, dest, data);
+	} else {
+		return write_word_32(info, dest, data);
+	}
+}
+
+static int write_word_32(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	ulong *datap = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
+	ulong start;
+	int i, flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
+	udelay(1000);
+
+	value = swap16(addr2[0]);
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = swap16(addr2[1]);	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00002000;
+		info->start[2] = base + 0x00004000;
+		info->start[3] = base + 0x00006000;
+		info->start[4] = base + 0x00008000;
+		info->start[5] = base + 0x0000a000;
+		info->start[6] = base + 0x0000c000;
+		info->start[7] = base + 0x0000e000;
+
+		for (i = 8; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+
+		for (; i >= 0; i--)
+			info->start[i] = base + i * 0x00010000;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_16(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!",	prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
+
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_16(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_16(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	ulong *datap = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
+			return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
+
+		dest2[i] = swap16(data2[i]);
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+				(swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0)
+			continue;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i+1, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/u-boot/board/tqc/tqm5200/cmd_stk52xx.c b/u-boot/board/tqc/tqm5200/cmd_stk52xx.c
new file mode 100644
index 0000000..0789c58
--- /dev/null
+++ b/u-boot/board/tqc/tqm5200/cmd_stk52xx.c
@@ -0,0 +1,1242 @@
+/*
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * STK52XX specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_CMD_BSP)
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#define DEFAULT_VOL	45
+#define DEFAULT_FREQ	500
+#define DEFAULT_DURATION	200
+#define LEFT		1
+#define RIGHT		2
+#define LEFT_RIGHT	3
+#define BL_OFF		0
+#define BL_ON		1
+
+#define SM501_GPIO_CTRL_LOW		0x00000008UL
+#define SM501_GPIO_CTRL_HIGH		0x0000000CUL
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_LOW		0x00010000UL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+			  unsigned int channel);
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+			unsigned int channel);
+static void spi_init(void);
+static int spi_transmit(unsigned char data);
+static void pcm1772_write_reg(unsigned char addr, unsigned char data);
+static void set_attenuation(unsigned char attenuation);
+
+static void spi_init(void)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	/* PSC3 as SPI and GPIOs */
+	gpio->port_config &= 0xFFFFF0FF;
+	gpio->port_config |= 0x00000800;
+	/*
+	 * Its important to use the correct order when initializing the
+	 * registers
+	 */
+	spi->ddr = 0x0F; /* set all SPI pins as output */
+	spi->pdr = 0x08; /* set SS high */
+	spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
+	spi->cr2 = 0x00; /* normal operation */
+	spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
+}
+
+static int spi_transmit(unsigned char data)
+{
+	int dummy;
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+	spi->dr = data;
+	/* wait for SPI transmission completed */
+	while(!(spi->sr & 0x80))
+	{
+		if (spi->sr & 0x40)	/* if write collision occured */
+		{
+			/* do dummy read to clear status register */
+			dummy = spi->dr;
+			printf ("SPI write collision\n");
+			return -1;
+		}
+	}
+	return (spi->dr);
+}
+
+static void pcm1772_write_reg(unsigned char addr, unsigned char data)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+	spi->pdr = 0x00; /* Set SS low */
+	spi_transmit(addr);
+	spi_transmit(data);
+	/* wait some time to meet MS# hold time of PCM1772 */
+	udelay (1);
+	spi->pdr = 0x08; /* set SS high */
+}
+
+static void set_attenuation(unsigned char attenuation)
+{
+	pcm1772_write_reg(0x01, attenuation); /* left channel */
+	debug ("PCM1772 attenuation left set to %d.\n", attenuation);
+	pcm1772_write_reg(0x02, attenuation); /* right channel */
+	debug ("PCM1772 attenuation right set to %d.\n", attenuation);
+}
+
+void amplifier_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	/* Do this only once, because of the long time delay */
+	if (!init_done) {
+		/* configure PCM1772 audio format as I2S */
+		pcm1772_write_reg(0x03, 0x01);
+		/* enable audio amplifier */
+		gpio->sint_gpioe |=  0x02;	/* PSC3_5 as GPIO */
+		gpio->sint_ode &= ~0x02;	/* PSC3_5 is not open Drain */
+		gpio->sint_dvo &= ~0x02;	/* PSC3_5 is LOW */
+		gpio->sint_ddr |=  0x02;	/* PSC3_5 as output */
+		/*
+		 * wait some time to allow amplifier to recover from shutdown
+		 * mode.
+		 */
+		for(i = 0; i < 350; i++)
+			udelay(1000);
+		/*
+		 * The used amplifier (LM4867) has a so called "pop and click"
+		 * elmination filter. The input signal of the amplifier must
+		 * exceed a certain level once after power up to activate the
+		 * generation of the output signal. This is achieved by
+		 * sending a low frequent (nearly inaudible) sawtooth with a
+		 * sufficient signal level.
+		 */
+		set_attenuation(50);
+		i2s_sawtooth (200, 5, LEFT_RIGHT);
+		init_done = 1;
+	}
+}
+
+static void i2s_init(void)
+{
+	unsigned long i;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
+
+	*(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
+						  * 5.617 MHz */
+	*(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
+						       * register */
+	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
+	psc->ctur = 0x0F;	/* 16 bit frame width */
+
+	for(i=0;i<128;i++)
+	{
+		psc->psc_buffer_32 = 0; /* clear tx fifo */
+	}
+}
+
+static int i2s_play_wave(unsigned long addr, unsigned long len)
+{
+	unsigned long i;
+	unsigned char *wave_file = (uchar *)addr + 44;	/* quick'n dirty: skip
+							 * wav header*/
+	unsigned char swapped[4];
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	/*
+	 * play wave file in memory; bytes/words are be swapped
+	 */
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	for(i = 0;i < (len / 4); i++) {
+		swapped[3] = *wave_file++;
+		swapped[2] = *wave_file++;
+		swapped[1] = *wave_file++;
+		swapped[0] = *wave_file++;
+		psc->psc_buffer_32 =  *((unsigned long*)swapped);
+		while (psc->tfnum > 400) {
+			if(ctrlc())
+				return 0;
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+	return 0;
+}
+
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+			unsigned int channel)
+{
+	long i,j;
+	unsigned long data;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	/*
+	 * Generate sawtooth. Start with middle level up to highest level. Then
+	 * go to lowest level and back to middle level.
+	 */
+	for(j = 0; j < ((duration * freq) / 1000); j++)	{
+		for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4))))	{
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+	return 0;
+}
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+			 unsigned int channel)
+{
+	long i,j;
+	unsigned long data;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	/*
+	 * Generate sqarewave. Start with high level, duty cycle 1:1.
+	 */
+	for(j = 0; j < ((duration * freq) / 1000); j++)	{
+		for(i = 0; i < (44100/(freq*2)); i ++) {
+			data = 0x7FFF;
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = 0; i < (44100/(freq*2)); i ++) {
+			data = 0x8000;
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+	return 0;
+}
+
+static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long reg, val, duration;
+	char *tmp;
+	unsigned int freq, channel;
+	unsigned char volume;
+	int rcode = 1;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	switch (argc) {
+	case 0:
+	case 1:
+		return cmd_usage(cmdtp);
+	case 2:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
+						LEFT_RIGHT);
+			return rcode;
+		}
+
+		return cmd_usage(cmdtp);
+	case 3:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, DEFAULT_FREQ,
+						LEFT_RIGHT);
+			return rcode;
+		}
+		return cmd_usage(cmdtp);
+	case 4:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (duration, freq,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, freq,
+						LEFT_RIGHT);
+			return rcode;
+		} else if (strcmp(argv[1],"pcm1772") == 0) {
+			reg = simple_strtoul(argv[2], NULL, 10);
+			val = simple_strtoul(argv[3], NULL, 10);
+			printf("Set PCM1772 %lu. %lu\n", reg, val);
+			pcm1772_write_reg((uchar)reg, (uchar)val);
+			return 0;
+		}
+		return cmd_usage(cmdtp);
+	case 5:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			if (strncmp(argv[4],"l",1) == 0)
+				channel = LEFT;
+			else if (strncmp(argv[4],"r",1) == 0)
+				channel = RIGHT;
+			else
+				channel = LEFT_RIGHT;
+			printf ("Play squarewave\n");
+			rcode = i2s_sawtooth (duration, freq,
+					      channel);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			if (strncmp(argv[4],"l",1) == 0)
+				channel = LEFT;
+			else if (strncmp(argv[4],"r",1) == 0)
+				channel = RIGHT;
+			else
+				channel = LEFT_RIGHT;
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, freq,
+						channel);
+			return rcode;
+		}
+		return cmd_usage(cmdtp);
+	}
+	printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
+	return 1;
+}
+
+static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long length, addr;
+	unsigned char volume;
+	int rcode = 1;
+	char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	switch (argc) {
+
+	case 3:
+		length = simple_strtoul(argv[2], NULL, 16);
+		addr = simple_strtoul(argv[1], NULL, 16);
+		break;
+
+	case 2:
+		if ((tmp = getenv ("filesize")) != NULL) {
+			length = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No filesize provided\n");
+			return 1;
+		}
+		addr = simple_strtoul(argv[1], NULL, 16);
+
+	case 1:
+		if ((tmp = getenv ("filesize")) != NULL) {
+			length = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No filesize provided\n");
+			return 1;
+		}
+		if ((tmp = getenv ("loadaddr")) != NULL) {
+			addr = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No loadaddr provided\n");
+			return 1;
+		}
+		break;
+
+	default:
+		printf("Usage:\nwav <addr> <length[s]\n");
+		return 1;
+		break;
+	}
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	printf("Play wave file at %lX with length %lX\n", addr, length);
+	rcode = i2s_play_wave(addr, length);
+
+	return rcode;
+}
+
+static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned char volume;
+	unsigned int channel;
+	int rcode;
+	char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	switch (argc) {
+	case 0:
+	case 1:
+		channel = LEFT_RIGHT;
+		break;
+	case 2:
+		if (strncmp(argv[1],"l",1) == 0)
+			channel = LEFT;
+		else if (strncmp(argv[1],"r",1) == 0)
+			channel = RIGHT;
+		else
+			channel = LEFT_RIGHT;
+		break;
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	printf("Beep on ");
+	if (channel == LEFT)
+		printf ("left ");
+	else if (channel == RIGHT)
+		printf ("right ");
+	else
+		printf ("left and right ");
+	printf ("channel\n");
+
+	rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
+
+	return rcode;
+}
+#endif
+
+#if defined(CONFIG_STK52XX)
+void led_init(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	/* configure PSC3 for SPI and GPIO */
+	gpio->port_config &= ~(0x00000F00);
+	gpio->port_config |=   0x00000800;
+
+	gpio->simple_gpioe &= ~(0x00000F00);
+	gpio->simple_gpioe |=   0x00000F00;
+
+	gpio->simple_ddr &= ~(0x00000F00);
+	gpio->simple_ddr |=   0x00000F00;
+
+	/* configure timer 4-7 for simple GPIO output */
+	gpt->gpt4.emsr |=  0x00000024;
+	gpt->gpt5.emsr |=  0x00000024;
+	gpt->gpt6.emsr |=  0x00000024;
+	gpt->gpt7.emsr |=  0x00000024;
+
+#ifndef CONFIG_TQM5200S
+	/* enable SM501 GPIO control (in both power modes) */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+
+	/* configure SM501 gpio pins 24-27 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
+
+	/* configure SM501 gpio pins 48-51 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
+#endif /* !CONFIG_TQM5200S */
+}
+
+/*
+ * return 1 if led number unknown
+ * return 0 else
+ */
+int do_led(char * const argv[])
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	switch	(simple_strtoul(argv[2], NULL, 10)) {
+
+	case 0:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 8);
+		} else {
+			gpio->simple_dvo &= ~(1 << 8);
+		}
+		break;
+
+	case 1:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 9);
+		} else {
+			gpio->simple_dvo &= ~(1 << 9);
+		}
+		break;
+
+	case 2:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 10);
+		} else {
+			gpio->simple_dvo &= ~(1 << 10);
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 11);
+		} else {
+			gpio->simple_dvo &= ~(1 << 11);
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt4.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt4.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 5:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt5.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt5.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 6:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt6.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt6.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 7:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt7.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt7.emsr &=  ~(1 << 4);
+		}
+		break;
+#ifndef CONFIG_TQM5200S
+	case 24:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 24);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 24);
+		}
+		break;
+
+	case 25:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 25);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 25);
+		}
+		break;
+
+	case 26:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 26);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 26);
+		}
+		break;
+
+	case 27:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 27);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 27);
+		}
+		break;
+
+	case 48:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 16);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 16);
+		}
+		break;
+
+	case 49:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 17);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 17);
+		}
+		break;
+
+	case 50:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 18);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 18);
+		}
+		break;
+
+	case 51:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 19);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 19);
+		}
+		break;
+#endif /* !CONFIG_TQM5200S */
+	default:
+		printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+/*
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
+
+	/* GPIO configuration of the CAN pins is done in TQM5200.h */
+
+	if (!init_done) {
+		/* init CAN 1 */
+		can1->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can1->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can1->canctl1 & 0x02)) {
+			udelay(10);
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 initialize error, "
+				"can not enter sleep mode!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		}
+		i = 0;
+		can1->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can1->canctl1 & 0x01)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can1->canctl1 = 0x80;
+		can1->canctl1 |= 0x40;
+		can1->canbtr0 = 0x0F;
+		can1->canbtr1 = 0x7F;
+		can1->canidac &= ~(0x30);
+		can1->canidar1 = 0x00;
+		can1->canidar3 = 0x00;
+		can1->canidar5 = 0x00;
+		can1->canidar7 = 0x00;
+		can1->canidmr0 = 0xFF;
+		can1->canidmr1 = 0xFF;
+		can1->canidmr2 = 0xFF;
+		can1->canidmr3 = 0xFF;
+		can1->canidmr4 = 0xFF;
+		can1->canidmr5 = 0xFF;
+		can1->canidmr6 = 0xFF;
+		can1->canidmr7 = 0xFF;
+
+		i = 0;
+		can1->canctl0 &= ~(0x01);	/* leave init mode */
+		can1->canctl0 &= ~(0x02);
+		/* wait until init and sleep mode left */
+		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+
+		/* init CAN 2 */
+		can2->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can2->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can2->canctl1 & 0x02))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		i = 0;
+		can2->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can2->canctl1 & 0x01))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can2->canctl1 = 0x80;
+		can2->canctl1 |= 0x40;
+		can2->canbtr0 = 0x0F;
+		can2->canbtr1 = 0x7F;
+		can2->canidac &= ~(0x30);
+		can2->canidar1 = 0x00;
+		can2->canidar3 = 0x00;
+		can2->canidar5 = 0x00;
+		can2->canidar7 = 0x00;
+		can2->canidmr0 = 0xFF;
+		can2->canidmr1 = 0xFF;
+		can2->canidmr2 = 0xFF;
+		can2->canidmr3 = 0xFF;
+		can2->canidmr4 = 0xFF;
+		can2->canidmr5 = 0xFF;
+		can2->canidmr6 = 0xFF;
+		can2->canidmr7 = 0xFF;
+		can2->canctl0 &= ~(0x01);	/* leave init mode */
+		can2->canctl0 &= ~(0x02);
+
+		i = 0;
+		/* wait until init mode left */
+		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		init_done = 1;
+	}
+	return 0;
+}
+
+/*
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char * const argv[])
+{
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
+
+	/* send a message on CAN1 */
+	can1->cantbsel = 0x01;
+	can1->cantxfg.idr[0] = 0x55;
+	can1->cantxfg.idr[1] = 0x00;
+	can1->cantxfg.idr[1] &= ~0x8;
+	can1->cantxfg.idr[1] &= ~0x10;
+	can1->cantxfg.dsr[0] = 0xCC;
+	can1->cantxfg.dlr = 1;
+	can1->cantxfg.tbpr = 0;
+	can1->cantflg = 0x01;
+
+	i = 0;
+	while ((can1->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 send timeout, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can2->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can2->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN2 receive error, "
+			 "data mismatch!\n",
+			__FUNCTION__);
+		return 1;
+	}
+
+	/* send a message on CAN2 */
+	can2->cantbsel = 0x01;
+	can2->cantxfg.idr[0] = 0x55;
+	can2->cantxfg.idr[1] = 0x00;
+	can2->cantxfg.idr[1] &= ~0x8;
+	can2->cantxfg.idr[1] &= ~0x10;
+	can2->cantxfg.dsr[0] = 0xCC;
+	can2->cantxfg.dlr = 1;
+	can2->cantxfg.tbpr = 0;
+	can2->cantflg = 0x01;
+
+	i = 0;
+	while ((can2->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 send error, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can1->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can1->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN1 receive error 0x%02x\n",
+			__FUNCTION__, (can1->canrxfg.dsr[0]));
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * return 1 if rs232 port unknown
+ * return 2 on txd/rxd failure (only rs232 2)
+ * return 3 on rts/cts failure
+ * return 0 if no failure
+ */
+int do_rs232(char * const argv[])
+{
+	int error_status = 0;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	switch	(simple_strtoul(argv[2], NULL, 10)) {
+
+	case 1:
+		/* check RTS <-> CTS loop */
+		/* set rts to 0 */
+		psc1->op1 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 0) {
+			error_status = 3;
+			printf ("%s: failure at rs232_1, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		/* set rts to 1 */
+		psc1->op0 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 1) {
+			error_status = 3;
+			printf ("%s: failure at rs232_1, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		break;
+
+	case 2:
+		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |=   0x00000500;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |=   (1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+			error_status = 2;
+			printf ("%s: failure at rs232_2, rxd status is %d "
+				"(should be 1)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+			error_status = 2;
+			printf ("%s: failure at rs232_2, rxd status is %d "
+				"(should be 0)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |=   (1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+			error_status = 3;
+			printf ("%s: failure at rs232_2, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+			error_status = 3;
+			printf ("%s: failure at rs232_2, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |=   0x00000F00;
+		break;
+
+	default:
+		printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+		error_status = 1;
+		break;
+	}
+
+	return error_status;
+}
+
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
+static void sm501_backlight (unsigned int state)
+{
+	if (state == BL_ON) {
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+			(1 << 26) | (1 << 27);
+	} else if (state == BL_OFF)
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+			~((1 << 26) | (1 << 27));
+}
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
+
+int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+#if defined(CONFIG_STK52XX)
+	led_init();
+#endif
+	can_init();
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strncmp (argv[1], "can", 3) == 0) {
+			rcode = do_can (argv);
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+			return rcode;
+		}
+		break;
+
+	case 3:
+		if (strncmp (argv[1], "rs232", 3) == 0) {
+			rcode = do_rs232 (argv);
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+			return rcode;
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
+		} else if (strncmp (argv[1], "backlight", 4) == 0) {
+			if (strncmp (argv[2], "on", 2) == 0) {
+				sm501_backlight (BL_ON);
+				return 0;
+			}
+			else if (strncmp (argv[2], "off", 3) == 0) {
+				sm501_backlight (BL_OFF);
+				return 0;
+			}
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
+		}
+		break;
+
+#if defined(CONFIG_STK52XX)
+	case 4:
+		if (strcmp (argv[1], "led") == 0) {
+			return (do_led (argv));
+		}
+		break;
+#endif
+
+	default:
+		break;
+	}
+
+	printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
+	return 1;
+}
+
+
+U_BOOT_CMD(
+	sound ,    5,    1,     cmd_sound,
+	"Sound sub-system",
+	"saw [duration] [freq] [channel]\n"
+	"    - generate sawtooth for 'duration' ms with frequency 'freq'\n"
+	"      on left \"l\" or right \"r\" channel\n"
+	"sound square [duration] [freq] [channel]\n"
+	"    - generate squarewave for 'duration' ms with frequency 'freq'\n"
+	"      on left \"l\" or right \"r\" channel\n"
+	"pcm1772 reg val"
+);
+
+U_BOOT_CMD(
+	wav ,    3,    1,     cmd_wav,
+	"play wav file",
+	"[addr] [bytes]\n"
+	"    - play wav file at address 'addr' with length 'bytes'"
+);
+
+U_BOOT_CMD(
+	beep ,    2,    1,     cmd_beep,
+	"play short beep",
+	"[channel]\n"
+	"    - play short beep on \"l\"eft or \"r\"ight channel"
+);
+#endif /* CONFIG_STK52XX  || CONFIG_FO300 */
+
+#if defined(CONFIG_STK52XX)
+U_BOOT_CMD(
+	fkt ,	4,	1,	cmd_fkt,
+	"Function test routines",
+	"led number on/off\n"
+	"     - 'number's like printed on STK52XX board\n"
+	"fkt can\n"
+	"     - loopback plug for X83 required\n"
+	"fkt rs232 number\n"
+	"     - loopback plug(s) for X2 required"
+#ifndef CONFIG_TQM5200S
+	"\n"
+	"fkt backlight on/off\n"
+	"     - switch backlight on or off"
+#endif /* !CONFIG_TQM5200S */
+);
+#elif defined(CONFIG_FO300)
+U_BOOT_CMD(
+	fkt ,	3,	1,	cmd_fkt,
+	"Function test routines",
+	"fkt can\n"
+	"     - loopback plug for X16/X29 required\n"
+	"fkt rs232 number\n"
+	"     - loopback plug(s) for X21/X22 required"
+);
+#endif
+#endif
diff --git a/u-boot/board/tqc/tqm5200/cmd_tb5200.c b/u-boot/board/tqc/tqm5200/cmd_tb5200.c
new file mode 100644
index 0000000..79c1b98
--- /dev/null
+++ b/u-boot/board/tqc/tqm5200/cmd_tb5200.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2005 - 2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TB5200 specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_CMD_BSP)
+#if defined (CONFIG_TB5200)
+
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+
+static void led_init(void)
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	/* configure timer 4 for simple GPIO output */
+	gpt->gpt4.emsr |=  0x00000024;
+}
+
+int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	led_init();
+
+	if (strcmp (argv[1], "on") == 0) {
+		debug ("switch status LED on\n");
+		gpt->gpt4.emsr |=  (1 << 4);
+	} else if (strcmp (argv[1], "off") == 0) {
+		debug ("switch status LED off\n");
+		gpt->gpt4.emsr &=  ~(1 << 4);
+	} else {
+		printf ("Usage:\nled on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+	if (state == 1) {
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+			(1 << 26) | (1 << 27);
+	} else if (state == 0)
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+			~((1 << 26) | (1 << 27));
+}
+
+int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (strcmp (argv[1], "on") == 0) {
+		debug ("switch backlight on\n");
+		sm501_backlight (1);
+	} else if (strcmp (argv[1], "off") == 0) {
+		debug ("switch backlight off\n");
+		sm501_backlight (0);
+	} else {
+		printf ("Usage:\nbacklight on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	led ,	2,	1,	cmd_led,
+	"switch status LED on or off",
+	"on/off"
+);
+
+U_BOOT_CMD(
+	backlight ,	2,	1,	cmd_backlight,
+	"switch backlight on or off",
+	"on/off"
+	);
+
+#endif /* CONFIG_STK52XX */
+#endif
diff --git a/u-boot/board/tqc/tqm5200/mt48lc16m16a2-75.h b/u-boot/board/tqc/tqm5200/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..48b4321
--- /dev/null
+++ b/u-boot/board/tqc/tqm5200/mt48lc16m16a2-75.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/u-boot/board/tqc/tqm5200/tqm5200.c b/u-boot/board/tqc/tqm5200/tqm5200.c
new file mode 100644
index 0000000..352226f
--- /dev/null
+++ b/u-boot/board/tqc/tqm5200/tqm5200.c
@@ -0,0 +1,905 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+#include <netdev.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
+    defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ *
+ * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ *     ------------------------------------------------
+ *     00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
+ *     10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
+ *     20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
+ *     30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
+ *     40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
+ *     50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
+ *     60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
+ *     70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+	0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
+};
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+#if defined(CONFIG_TQM5200_B)
+	return dramsize + dramsize2;
+#else
+	return dramsize;
+#endif /* CONFIG_TQM5200_B */
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_AEVFIFO)
+	puts ("Board: AEVFIFO\n");
+	return 0;
+#endif
+
+#if defined(CONFIG_TQM5200S)
+# define MODULE_NAME	"TQM5200S"
+#else
+# define MODULE_NAME	"TQM5200"
+#endif
+
+#if defined(CONFIG_STK52XX)
+# define CARRIER_NAME	"STK52xx"
+#elif defined(CONFIG_TB5200)
+# define CARRIER_NAME	"TB5200"
+#elif defined(CONFIG_CAM5200)
+# define CARRIER_NAME	"CAM5200"
+#elif defined(CONFIG_FO300)
+# define CARRIER_NAME	"FO300"
+#elif defined(CONFIG_CHARON)
+# define CARRIER_NAME	"CHARON"
+#else
+# error "UNKNOWN"
+#endif
+
+	puts (	"Board: " MODULE_NAME " (TQ-Components GmbH)\n"
+		"       on a " CARRIER_NAME " carrier board\n");
+
+	return 0;
+}
+
+#undef MODULE_NAME
+#undef CARRIER_NAME
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#if defined (CONFIG_MINIFAP)
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_51			0x00080000UL
+#endif /* CONFIG MINIFAP */
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+#if defined (CONFIG_MINIFAP)
+	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
+
+	/* enable GPIO control (in both power modes) */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	/* configure GPIO51 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
+		SM501_GPIO_51;
+#else
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+
+	/* by default the ATA reset is de-asserted */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+#endif
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+#if defined (CONFIG_MINIFAP)
+	if (idereset) {
+		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+			~SM501_GPIO_51;
+	} else {
+		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+			SM501_GPIO_51;
+	}
+#else
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+#endif
+}
+#endif
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+#ifdef CONFIG_STK52XX
+	struct mpc5xxx_gpio *gpio;
+
+	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+	/*
+	 * Configure PSC6_0 through PSC6_3 as GPIO.
+	 */
+	gpio->port_config &= ~(0x00700000);
+
+	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+	gpio->simple_gpioe |= 0x20000000;
+
+	/* Configure GPIO_IRDA_1 as input */
+	gpio->simple_ddr &= ~(0x20000000);
+
+	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+#else
+	return 0;
+#endif
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+
+	extern int usb_cpu_init(void);
+
+#ifdef CONFIG_PS2MULT
+	ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+	/* Low level USB init, required for proper kernel operation */
+	usb_cpu_init();
+#endif
+
+	return (0);
+}
+#endif
+
+#ifdef CONFIG_FO300
+int silent_boot (void)
+{
+	vu_long timer3_status;
+
+	/* Configure GPT3 as GPIO input */
+	*(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
+
+	/* Read in TIMER_3 pin status */
+	timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
+
+#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
+	/* Force silent console mode if S1 switch
+	 * is in closed position (TIMER_3 pin status is LOW). */
+	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
+		return 1;
+#else
+	/* Force silent console mode if S1 switch
+	 * is in open position (TIMER_3 pin status is HIGH). */
+	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
+		return 1;
+#endif
+
+	return 0;
+}
+
+int board_early_init_f (void)
+{
+	if (silent_boot())
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+#endif	/* CONFIG_FO300 */
+
+#if defined(CONFIG_CHARON)
+#include <i2c.h>
+#include <asm/io.h>
+
+/* The TFP410 registers */
+#define TFP410_REG_VEN_ID_L 0x00
+#define TFP410_REG_VEN_ID_H 0x01
+#define TFP410_REG_DEV_ID_L 0x02
+#define TFP410_REG_DEV_ID_H 0x03
+#define TFP410_REG_REV_ID 0x04
+
+#define TFP410_REG_CTL_1_MODE 0x08
+#define TFP410_REG_CTL_2_MODE 0x09
+#define TFP410_REG_CTL_3_MODE 0x0A
+
+#define TFP410_REG_CFG 0x0B
+
+#define TFP410_REG_DE_DLY 0x32
+#define TFP410_REG_DE_CTL 0x33
+#define TFP410_REG_DE_TOP 0x34
+#define TFP410_REG_DE_CNT_L 0x36
+#define TFP410_REG_DE_CNT_H 0x37
+#define TFP410_REG_DE_LIN_L 0x38
+#define TFP410_REG_DE_LIN_H 0x39
+
+#define TFP410_REG_H_RES_L 0x3A
+#define TFP410_REG_H_RES_H 0x3B
+#define TFP410_REG_V_RES_L 0x3C
+#define TFP410_REG_V_RES_H 0x3D
+
+static int tfp410_read_reg(int reg, uchar *buf)
+{
+	if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
+		puts ("Error reading the chip.\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int tfp410_write_reg(int reg, uchar buf)
+{
+	if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
+		puts ("Error writing the chip.\n");
+		return 1;
+	}
+	return 0;
+}
+
+typedef struct _tfp410_config {
+	int	reg;
+	uchar	val;
+}TFP410_CONFIG;
+
+static TFP410_CONFIG tfp410_configtbl[] = {
+	{TFP410_REG_CTL_1_MODE, 0x37},
+	{TFP410_REG_CTL_2_MODE, 0x20},
+	{TFP410_REG_CTL_3_MODE, 0x80},
+	{TFP410_REG_DE_DLY, 0x90},
+	{TFP410_REG_DE_CTL, 0x00},
+	{TFP410_REG_DE_TOP, 0x23},
+	{TFP410_REG_DE_CNT_H, 0x02},
+	{TFP410_REG_DE_CNT_L, 0x80},
+	{TFP410_REG_DE_LIN_H, 0x01},
+	{TFP410_REG_DE_LIN_L, 0xe0},
+	{-1, 0},
+};
+
+static int charon_last_stage_init(void)
+{
+	volatile struct mpc5xxx_lpb *lpb =
+		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
+	int	oldbus = i2c_get_bus_num();
+	uchar	buf;
+	int	i = 0;
+
+	i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
+
+	/* check version */
+	if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
+		return -1;
+	if (!(buf & 0x04))
+		return -1;
+	if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
+		return -1;
+	if (!(buf & 0x10))
+		return -1;
+	/* OK, now init the chip */
+	while (tfp410_configtbl[i].reg != -1) {
+		int ret;
+
+		ret = tfp410_write_reg(tfp410_configtbl[i].reg,
+				tfp410_configtbl[i].val);
+		if (ret != 0)
+			return -1;
+		i++;
+	}
+	printf("TFP410 initialized.\n");
+	i2c_set_bus_num(oldbus);
+
+	/* set deadcycle for cs3 to 0 */
+	setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
+	return 0;
+}
+#endif
+
+int last_stage_init (void)
+{
+	/*
+	 * auto scan for really existing devices and re-set chip select
+	 * configuration.
+	 */
+	u16 save, tmp;
+	int restore;
+
+	/*
+	 * Check for SRAM and SRAM size
+	 */
+
+	/* save original SRAM content  */
+	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
+	restore = 1;
+
+	/* write test pattern to SRAM */
+	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in SRAM detection\n");
+
+	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
+		/* no SRAM at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
+		/* make sure that we access a mirrored address */
+		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
+		__asm__ volatile ("sync");
+		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
+			/* SRAM size = 512 kByte */
+			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
+								0x80000);
+			__asm__ volatile ("sync");
+			puts ("SRAM:  512 kB\n");
+		}
+		else
+			puts ("!! possible error in SRAM detection\n");
+	} else {
+		puts ("SRAM:  1 MB\n");
+	}
+	/* restore origianl SRAM content  */
+	if (restore) {
+		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
+		__asm__ volatile ("sync");
+	}
+
+#ifndef CONFIG_TQM5200S	/* The TQM5200S has no SM501 grafic controller */
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+		/* no grafic controller at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else {
+		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
+	}
+	/* restore origianl FB content  */
+	if (restore) {
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+
+#ifdef CONFIG_FO300
+	if (silent_boot()) {
+		setenv("bootdelay", "0");
+		disable_ctrlc(1);
+	}
+#endif
+#endif /* !CONFIG_TQM5200S */
+
+#if defined(CONFIG_CHARON)
+	charon_last_stage_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_SM501
+
+#ifdef CONFIG_FO300
+#define DISPLAY_WIDTH   800
+#else
+#define DISPLAY_WIDTH   640
+#endif
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if 0 /* CRT only */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x10090a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x10090a01},
+	{0x00054, 0x0},
+	{0x80200, 0x00010000},
+	{0x80204, 0x0},
+	{0x80208, 0x0A000A00},
+	{0x8020C, 0x02fa027f},
+	{0x80210, 0x004a028b},
+	{0x80214, 0x020c01df},
+	{0x80218, 0x000201e9},
+	{0x80200, 0x00013306},
+#else  /* panel + CRT */
+#ifdef CONFIG_FO300
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x301a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x0f013106},
+	{0x80004, 0xc428bb17},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0C800C80},
+	{0x80014, 0x03200000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00320},
+	{0x80024, 0x042a031f},
+	{0x80028, 0x0086034a},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201ea},
+	{0x80200, 0x00010000},
+#else
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x0f013106},
+	{0x80004, 0xc428bb17},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a028b},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e9},
+	{0x80200, 0x00010000},
+#endif /* #ifdef CONFIG_FO300 */
+#endif
+	{0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
+	defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
+	} else if (line_number == 2) {
+#if defined (CONFIG_CHARON)
+		strcpy (info, "        on a CHARON carrier board");
+#endif
+#if defined (CONFIG_STK52XX)
+		strcpy (info, "        on a STK52xx carrier board");
+#endif
+#if defined (CONFIG_TB5200)
+		strcpy (info, "        on a TB5200 carrier board");
+#endif
+#if defined (CONFIG_FO300)
+		strcpy (info, "        on a FO300 carrier board");
+#endif
+#endif
+	}
+	else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+	u16 save, tmp;
+	int restore, ret;
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+		/* no grafic controller found */
+		restore = 0;
+		ret = 0;
+	} else {
+		ret = SM501_MMIO_BASE;
+	}
+
+	if (restore) {
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+	return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#if defined(CONFIG_VIDEO)
+	fdt_add_edid(blob, "smi,sm501", edid_buf);
+#endif
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+	/* init Micrel KSZ8993 PHY */
+	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/tqc/tqm8260/Makefile b/u-boot/board/tqc/tqm8260/Makefile
new file mode 100644
index 0000000..d5b6df6
--- /dev/null
+++ b/u-boot/board/tqc/tqm8260/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../tqm8xx/)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tqc/tqm8260/tqm8260.c b/u-boot/board/tqc/tqm8260/tqm8260.c
new file mode 100644
index 0000000..95073b8
--- /dev/null
+++ b/u-boot/board/tqc/tqm8260/tqm8260.c
@@ -0,0 +1,368 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "TQM82", 5)) {
+		puts ("### No HW ID - assuming TQM8260\n");
+		return (0);
+	}
+
+	puts (str);
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#if 0							/* Just for debugging */
+#define	prt_br_or(brX,orX) do {				\
+    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
+    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
+    printf ("\n"					\
+	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
+	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
+	start, start+sizem, (sizem+1)>>20);		\
+    } while (0)
+	prt_br_or (br0, or0);
+	prt_br_or (br1, or1);
+	prt_br_or (br2, or2);
+	prt_br_or (br3, or3);
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+	/* Local SDRAM setup:
+	 */
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
+	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+
+	if (size8 < size9) {
+		lsize = size9;
+		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
+	} else {
+		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
+						  (uchar *) SDRAM_BASE2_PRELIM);
+		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
+	}
+
+#if 0
+	/* Set up BR2 so that the local SDRAM goes
+	 * right after the 60x SDRAM
+	 */
+	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CONFIG_SYS_SDRAM_BASE + psize);
+#endif
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/u-boot/board/tqc/tqm8272/Makefile b/u-boot/board/tqc/tqm8272/Makefile
new file mode 100644
index 0000000..d2a90d5
--- /dev/null
+++ b/u-boot/board/tqc/tqm8272/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2001-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../tqm8xx/)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tqc/tqm8272/nand.c b/u-boot/board/tqc/tqm8272/nand.c
new file mode 100644
index 0000000..8c8341b
--- /dev/null
+++ b/u-boot/board/tqc/tqm8272/nand.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include "tqm8272.h"
+
+/* UPM pattern for bus clock = 66.7 MHz */
+static const uint upmTable67[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 100 MHz */
+static const uint upmTable100[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 133.3 MHz */
+static const uint upmTable133[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+static int	chipsel = 0;
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+static u8 hwctl = 0;
+
+static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
+
+	if (hwctl & 0x1) {
+		WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS);
+	} else if (hwctl & 0x2) {
+		WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS);
+	} else {
+		WRITE_NAND(byte, base);
+	}
+}
+
+static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
+	}
+	if (cmd != NAND_CMD_NONE)
+		upmnand_write_byte (mtd, cmd);
+}
+
+static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
+
+	return READ_NAND(base);
+}
+
+static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
+{
+	/* constant delay (see also tR in the datasheet) */
+	udelay(12); \
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		buf[i] = *base;
+}
+
+static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		*base = buf[i];
+}
+
+static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != *base)
+			return -1;
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	chipsel = chip;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	static	int	UpmInit = 0;
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	if (hwinf.nand == 0) return -1;
+
+	/* Setup the UPM */
+	if (UpmInit == 0) {
+		switch (hwinf.busclk_real) {
+		case 100000000:
+			upmconfig (UPMB, (uint *) upmTable100,
+			   sizeof (upmTable100) / sizeof (uint));
+			break;
+		case 133333333:
+			upmconfig (UPMB, (uint *) upmTable133,
+			   sizeof (upmTable133) / sizeof (uint));
+			break;
+		default:
+			upmconfig (UPMB, (uint *) upmTable67,
+			   sizeof (upmTable67) / sizeof (uint));
+			break;
+		}
+		UpmInit = 1;
+	}
+
+	/* Setup the memctrl */
+	memctl->memc_or3 = CONFIG_SYS_NAND_OR;
+	memctl->memc_br3 = CONFIG_SYS_NAND_BR;
+	memctl->memc_mbmr = (MxMR_OP_NORM);
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	nand->cmd_ctrl	 = upmnand_hwcontrol;
+	nand->read_byte	 = upmnand_read_byte;
+	nand->dev_ready	 = tqm8272_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf	 = tqm8272_write_buf;
+	nand->read_buf	 = tqm8272_read_buf;
+	nand->verify_buf = tqm8272_verify_buf;
+#endif
+
+	/*
+	 * Select required NAND chip
+	 */
+	board_nand_select_device(nand, 0);
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/tqc/tqm8272/tqm8272.c b/u-boot/board/tqc/tqm8272/tqm8272.c
new file mode 100644
index 0000000..96ec078
--- /dev/null
+++ b/u-boot/board/tqc/tqm8272/tqm8272.c
@@ -0,0 +1,957 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include <command.h>
+#include <netdev.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/m8260_pci.h>
+#endif
+#include "tqm8272.h"
+
+#if 0
+#define deb_printf(fmt,arg...) \
+	printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
+#else
+#define deb_printf(fmt,arg...) \
+	do { } while (0)
+#endif
+
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+unsigned long board_get_cpu_clk_f (void);
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTCA	*/
+	/* PA29 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTSOC	*/
+	/* PA28 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[0] */
+	/* PA9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   0,   0,	0   }, /* PC30 */
+	/* PC29 */ {   1,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   0,	 0,   1,   0,	0   }, /* PC17 MDC */
+	/* PC16 */ {   1,   0,	 0,   0,   0,	0   }, /* PC16 MDIO*/
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* PC10 */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC9 */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   1,   1,	 0,   1,   0,	0   }, /* PC5 SMC1 TXD */
+	/* PC4	*/ {   1,   1,	 0,   0,   0,	0   }, /* PC4 SMC1 RXD */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
+	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
+	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
+	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
+	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
+	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
+	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
+	/* PD8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/* UPM pattern for slow init */
+static const uint upmTableSlow[] =
+{
+    /* Offset	UPM Read Single RAM array entry */
+    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
+    /* 0x04 */	0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry */
+    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
+    /* 0x1C */	0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for fast init */
+static const uint upmTableFast[] =
+{
+    /* Offset	UPM Read Single RAM array entry */
+    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
+    /* 0x04 */	0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry */
+    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
+    /* 0x1C */	0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+
+	puts ("Board: ");
+	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
+		puts (p);
+	} else {
+		puts ("No HWIB assuming TQM8272");
+	}
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+static int get_cas_latency (void)
+{
+	/* get it from the option -ts in CIB */
+	/* default is 3 */
+	int	ret = 3;
+	int	pos = 0;
+	char	*p = (char *) CIB_INFO_START_ADDR;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return ret;
+		}
+		if (*p == '-') {
+			if ((p[1] == 't') && (p[2] == 's')) {
+				return (p[4] - '0');
+			}
+		}
+		p++;
+		pos++;
+	}
+	return ret;
+}
+#endif
+
+static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
+{
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	int	clk = board_get_cpu_clk_f ();
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	int	busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
+	int	cas;
+
+	sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
+			 PSDMR_BUFCMD);
+	if (busmode) {
+		switch (clk) {
+			case 66666666:
+				sdmr |= (PSDMR_RFRC_66MHZ_60X | \
+					PSDMR_PRETOACT_66MHZ_60X | \
+					PSDMR_WRC_66MHZ_60X | \
+					PSDMR_BUFCMD_66MHZ_60X);
+				break;
+			case 100000000:
+				sdmr |= (PSDMR_RFRC_100MHZ_60X | \
+					PSDMR_PRETOACT_100MHZ_60X | \
+					PSDMR_WRC_100MHZ_60X | \
+					PSDMR_BUFCMD_100MHZ_60X);
+				break;
+
+		}
+	} else {
+		switch (clk) {
+			case 66666666:
+				sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
+					PSDMR_PRETOACT_66MHZ_SINGLE | \
+					PSDMR_WRC_66MHZ_SINGLE | \
+					PSDMR_BUFCMD_66MHZ_SINGLE);
+				break;
+			case 100000000:
+				sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
+					PSDMR_PRETOACT_100MHZ_SINGLE | \
+					PSDMR_WRC_100MHZ_SINGLE | \
+					PSDMR_BUFCMD_100MHZ_SINGLE);
+				break;
+			case 133333333:
+				sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
+					PSDMR_PRETOACT_133MHZ_SINGLE | \
+					PSDMR_WRC_133MHZ_SINGLE | \
+					PSDMR_BUFCMD_133MHZ_SINGLE);
+				break;
+		}
+	}
+	cas = get_cas_latency();
+	sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
+	sdmr |= cas;
+	sdmr |= ((cas - 1) << 6);
+	return sdmr;
+#else
+	return sdmr;
+#endif
+}
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base, int col)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+	sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE, 9);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+
+static inline int scanChar (char *p, int len, unsigned long *number)
+{
+	int	akt = 0;
+
+	*number = 0;
+	while (akt < len) {
+		if ((*p >= '0') && (*p <= '9')) {
+			*number *= 10;
+			*number += *p - '0';
+			p += 1;
+		} else {
+			if (*p == '-')	return akt;
+			return -1;
+		}
+		akt ++;
+	}
+	return akt;
+}
+
+static int dump_hwib(void)
+{
+	HWIB_INFO	*hw = &hwinf;
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	char *s = getenv("serial#");
+
+	if (hw->OK) {
+		printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
+		printf ("serial : %s\n", s);
+		printf ("ethaddr: %s\n", hw->ethaddr);
+		printf ("FLASH	: %x nr:%d\n", hw->flash, hw->flash_nr);
+		printf ("RAM	: %x cs:%d\n", hw->ram, hw->ram_cs);
+		printf ("CPU	: %lu\n", hw->cpunr);
+		printf ("CAN	: %d\n", hw->can);
+		if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
+		else printf ("No EEprom\n");
+		if (hw->nand) {
+			printf ("NAND	: %x\n", hw->nand);
+			printf ("NAND CS: %d\n", hw->nand_cs);
+		} else { printf ("No NAND\n");}
+		printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
+		printf ("  real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
+				 "60x" : "Single PQII"));
+		printf ("Option : %lx\n", hw->option);
+		printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
+		printf ("CPM Clk: %d\n", hw->cpmcl);
+		printf ("CPU Clk: %d\n", hw->cpucl);
+		printf ("Bus Clk: %d\n", hw->buscl);
+		if (hw->busclk_real_ok) {
+			printf ("  real Clk: %d\n", hw->busclk_real);
+		}
+		printf ("CAS	: %d\n", get_cas_latency());
+	} else {
+		printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
+	}
+	return 0;
+}
+
+static inline int search_real_busclk (int *clk)
+{
+	int	part = 0, pos = 0;
+	char *p = (char *) CIB_INFO_START_ADDR;
+	int	ok = 0;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return 0;
+		}
+		switch (part) {
+		default:
+			if (*p == '-') {
+				++part;
+			}
+			break;
+		case 3:
+			if (*p == '-') {
+				++part;
+				break;
+			}
+			if (*p == 'b') {
+				ok = 1;
+				p++;
+				break;
+			}
+			if (ok) {
+				switch (*p) {
+				case '6':
+					*clk = 66666666;
+					return 1;
+					break;
+				case '1':
+					if (p[1] == '3') {
+						*clk = 133333333;
+					} else {
+						*clk = 100000000;
+					}
+					return 1;
+					break;
+				}
+			}
+			break;
+		}
+		p++;
+	}
+	return 0;
+}
+
+int analyse_hwib (void)
+{
+	char	*p = (char *) HWIB_INFO_START_ADDR;
+	int	anz;
+	int	part = 1, i = 0, pos = 0;
+	HWIB_INFO	*hw = &hwinf;
+
+	deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
+	/* Head = TQM */
+	if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
+		deb_printf("No HWIB\n");
+		return -1;
+	}
+	p += 3;
+	if (scanChar (p, 4, &hw->cpunr) < 0) {
+		deb_printf("No CPU\n");
+		return -2;
+	}
+	p +=4;
+
+	hw->flash = 0x200000 << (*p - 'A');
+	p++;
+	hw->flash_nr = *p - '0';
+	p++;
+
+	hw->ram = 0x2000000 << (*p - 'A');
+	p++;
+	if (*p == '2') {
+		hw->ram_cs = 2;
+		p++;
+	}
+
+	if (*p == 'A') hw->can = 1;
+	if (*p == 'B') hw->can = 2;
+	p +=1;
+	p +=1;	/* connector */
+	if (*p != '0') {
+		hw->eeprom = 0x1000 << (*p - 'A');
+	}
+	p++;
+
+	if ((*p < '0') || (*p > '9')) {
+		/* NAND before z-option */
+		hw->nand = 0x8000000 << (*p - 'A');
+		p++;
+		hw->nand_cs = *p - '0';
+		p += 2;
+	}
+	/* z-option */
+	anz = scanChar (p, 4, &hw->option);
+	if (anz < 0) {
+		deb_printf("No option\n");
+		return -3;
+	}
+	if (hw->option & 0x8) hw->Bus = 1;
+	p += anz;
+	if (*p != '-') {
+		deb_printf("No -\n");
+		return -4;
+	}
+	p++;
+	/* C option */
+	if (*p == 'E') {
+		hw->SecEng = 1;
+		p++;
+	}
+	switch (*p) {
+		case 'M': hw->cpucl = 266666666;
+			break;
+		case 'P': hw->cpucl = 300000000;
+			break;
+		case 'T': hw->cpucl = 400000000;
+			break;
+		default:
+			deb_printf("No CPU Clk: %c\n", *p);
+			return -5;
+			break;
+	}
+	p++;
+	switch (*p) {
+		case 'I': hw->cpmcl = 200000000;
+			break;
+		case 'M': hw->cpmcl = 300000000;
+			break;
+		default:
+			deb_printf("No CPM Clk\n");
+			return -6;
+			break;
+	}
+	p++;
+	switch (*p) {
+		case 'B': hw->buscl = 66666666;
+			break;
+		case 'E': hw->buscl = 100000000;
+			break;
+		case 'F': hw->buscl = 133333333;
+			break;
+		default:
+			deb_printf("No BUS Clk\n");
+			return -7;
+			break;
+	}
+	p++;
+
+	hw->OK = 1;
+	/* search MAC Address */
+	while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return 0;
+		}
+		switch (part) {
+		default:
+			if (*p == ' ') {
+				++part;
+				i = 0;
+			}
+			break;
+		case 3:			/* Copy MAC address */
+			if (*p == ' ') {
+				++part;
+				i = 0;
+				break;
+			}
+			hw->ethaddr[i++] = *p;
+			if ((i % 3) == 2)
+				hw->ethaddr[i++] = ':';
+			break;
+
+		}
+		p++;
+	}
+
+	hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
+	return 0;
+}
+
+#if defined(CONFIG_GET_CPU_STR_F)
+/* !! This routine runs from Flash */
+char get_cpu_str_f (char *buf)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+	int	i = 0;
+
+	buf[i++] = 'M';
+	buf[i++] = 'P';
+	buf[i++] = 'C';
+	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
+		buf[i++] = *&p[3];
+		buf[i++] = *&p[4];
+		buf[i++] = *&p[5];
+		buf[i++] = *&p[6];
+	} else {
+		buf[i++] = '8';
+		buf[i++] = '2';
+		buf[i++] = '7';
+		buf[i++] = 'x';
+	}
+	buf[i++] = 0;
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+/* !! This routine runs from Flash */
+unsigned long board_get_cpu_clk_f (void)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+	int i = 0;
+
+	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
+		if (search_real_busclk (&i))
+			return i;
+	}
+	return CONFIG_8260_CLKIN;
+}
+#endif
+
+#if CONFIG_BOARD_EARLY_INIT_R
+
+static int can_test (unsigned long off)
+{
+	volatile unsigned char	*base	= (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
+
+	*(base + 0x17) = 'T';
+	*(base + 0x18) = 'Q';
+	*(base + 0x19) = 'M';
+	if ((*(base + 0x17) != 'T') ||
+	    (*(base + 0x18) != 'Q') ||
+	    (*(base + 0x19) != 'M')) {
+		return 0;
+	}
+	return 1;
+}
+
+static int can_config_one (unsigned long off)
+{
+	volatile unsigned char	*ctrl	= (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
+	volatile unsigned char	*cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02);
+	volatile unsigned char	*clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f);
+	unsigned char temp;
+
+	*cpu_if = 0x45;
+	temp = *ctrl;
+	temp |= 0x40;
+	*ctrl	= temp;
+	*clkout = 0x20;
+	temp = *ctrl;
+	temp &= ~0x40;
+	*ctrl	= temp;
+	return 0;
+}
+
+static int can_config (void)
+{
+	int	ret = 0;
+	can_config_one (0);
+	if (hwinf.can == 2) {
+		can_config_one (0x100);
+	}
+	/* make Test if they really there */
+	ret += can_test (0);
+	ret += can_test (0x100);
+	return ret;
+}
+
+static int init_can (void)
+{
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	int	count = 0;
+
+	if ((hwinf.OK) && (hwinf.can)) {
+		memctl->memc_or4 = CONFIG_SYS_CAN_OR;
+		memctl->memc_br4 = CONFIG_SYS_CAN_BR;
+		/* upm Init */
+		upmconfig (UPMC, (uint *) upmTableFast,
+			   sizeof (upmTableFast) / sizeof (uint));
+		memctl->memc_mcmr =	(MxMR_DSx_3_CYCL |
+					MxMR_GPL_x4DIS |
+					MxMR_RLFx_2X |
+					MxMR_WLFx_2X |
+					MxMR_OP_NORM);
+		/* can configure */
+		count = can_config ();
+		printf ("CAN:	%d @ %x\n", count, CONFIG_SYS_CAN_BASE);
+		if (hwinf.can != count) printf("!!! difference to HWIB\n");
+	} else {
+		printf ("CAN:	No\n");
+	}
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	analyse_hwib ();
+	init_can ();
+	return 0;
+}
+#endif
+
+int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	dump_hwib ();
+	return 0;
+}
+
+U_BOOT_CMD(
+	  hwib, 1,	1,	do_hwib_dump,
+	  "dump HWIB'",
+	  ""
+);
+
+#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
+static int get_flash_timing (void)
+{
+	/* get it from the option -tf in CIB */
+	/* default is 0x00000c84 */
+	int	ret = 0x00000c84;
+	int	pos = 0;
+	int	nr = 0;
+	char	*p = (char *) CIB_INFO_START_ADDR;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return ret;
+		}
+		if (*p == '-') {
+			if ((p[1] == 't') && (p[2] == 'f')) {
+				p += 6;
+				ret = 0;
+				while (nr < 8) {
+				if ((*p >= '0') && (*p <= '9')) {
+					ret *= 0x10;
+					ret += *p - '0';
+					p += 1;
+					nr ++;
+				} else if ((*p >= 'A') && (*p <= 'F')) {
+					ret *= 10;
+					ret += *p - '7';
+					p += 1;
+					nr ++;
+				} else {
+					if (nr < 8) return 0x00000c84;
+					return ret;
+				}
+				}
+			}
+		}
+		p++;
+		pos++;
+	}
+	return ret;
+}
+
+/* Update the Flash_Size and the Flash Timing */
+int update_flash_size (int flash_size)
+{
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	unsigned long reg;
+	unsigned long tim;
+
+	/* I must use reg, otherwise the board hang */
+	reg = memctl->memc_or0;
+	reg &= ~ORxU_AM_MSK;
+	reg |= MEG_TO_AM(flash_size >> 20);
+	tim = get_flash_timing ();
+	reg &= ~0xfff;
+	reg |= (tim & 0xfff);
+	memctl->memc_or0 = reg;
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+	return 0;
+}
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/tqc/tqm8272/tqm8272.h b/u-boot/board/tqc/tqm8272/tqm8272.h
new file mode 100644
index 0000000..6d558ec
--- /dev/null
+++ b/u-boot/board/tqc/tqm8272/tqm8272.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	_TQM8272_HEADER_H
+#define	_TQM8272_HEADER_H
+
+#define _NOT_USED_	0xFFFFFFFF
+
+typedef struct{
+	int	Bus;
+	int	flash;
+	int	flash_nr;
+	int	ram;
+	int	ram_cs;
+	int	nand;
+	int	nand_cs;
+	int	eeprom;
+	int	can;
+	unsigned long	cpunr;
+	unsigned long	option;
+	int	SecEng;
+	int	cpucl;
+	int	cpmcl;
+	int	buscl;
+	int	busclk_real_ok;
+	int	busclk_real;
+	unsigned char	OK;
+	unsigned char  ethaddr[20];
+} HWIB_INFO;
+
+static HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
+			 0, 0, 0, 0, 0, 0};
+#endif
diff --git a/u-boot/board/tqc/tqm834x/Makefile b/u-boot/board/tqc/tqm834x/Makefile
new file mode 100644
index 0000000..bce53a4
--- /dev/null
+++ b/u-boot/board/tqc/tqm834x/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tqc/tqm834x/pci.c b/u-boot/board/tqc/tqm834x/pci.c
new file mode 100644
index 0000000..f35ea89
--- /dev/null
+++ b/u-boot/board/tqc/tqm834x/pci.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
+ * per TQM834x design physical connections to external devices (PCI sockets)
+ * are routed only to the PCI1 we do not account for the second one - this code
+ * supports PCI1 module only. Should support for the PCI2 be required in the
+ * future it needs a separate pci_controller structure (above) and handling -
+ * please refer to other boards' implementation for dual PCI host controllers,
+ * for example board/Marvell/db64360/pci.c, pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u32 reg32;
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT
+	 *
+	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
+	 * line actually used for clocking all external PCI devices in TQM83xx.
+	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
+	 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
+	 * are known to hang the board; this issue is under investigation
+	 * (13 oct 05)
+	 */
+	reg32 = OCCR_PCICOE1;
+#if 0
+	/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
+	reg32 = 0xff000000;
+#endif
+	if (clk->spmr & SPMR_CKID) {
+		/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+		 * fields accordingly */
+		reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
+
+		reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
+			  | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
+			  | OCCR_PCICD6 | OCCR_PCICD7);
+	}
+
+	clk->occr = reg32;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+	udelay(2000);
+
+	mpc83xx_pci_init(1, reg);
+}
diff --git a/u-boot/board/tqc/tqm834x/tqm834x.c b/u-boot/board/tqc/tqm834x/tqm834x.c
new file mode 100644
index 0000000..2aa97f2
--- /dev/null
+++ b/u-boot/board/tqc/tqm834x/tqm834x.c
@@ -0,0 +1,442 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IOSYNC			asm("eieio")
+#define ISYNC			asm("isync")
+#define SYNC			asm("sync")
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+#define DDR_MAX_SIZE_PER_CS	0x20000000
+
+#if defined(DDR_CASLAT_20)
+#define TIMING_CASLAT		TIMING_CFG1_CASLAT_20
+#define MODE_CASLAT		DDR_MODE_CASLAT_20
+#else
+#define TIMING_CASLAT		TIMING_CFG1_CASLAT_25
+#define MODE_CASLAT		DDR_MODE_CASLAT_25
+#endif
+
+#define INITIAL_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
+				CSCONFIG_COL_BIT_9)
+
+/* External definitions */
+ulong flash_get_size (ulong base, int banknum);
+
+/* Local functions */
+static int detect_num_flash_banks(void);
+static long int get_ddr_bank_size(short cs, volatile long *base);
+static void set_cs_bounds(short cs, long base, long size);
+static void set_cs_config(short cs, long config);
+static void set_ddr_config(void);
+
+/* Local variable */
+static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+/**************************************************************************
+ * Board initialzation after relocation to RAM. Used to detect the number
+ * of Flash banks on TQM834x.
+ */
+int board_early_init_r (void) {
+	/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return 0;
+
+	/* detect the number of Flash banks */
+	return detect_num_flash_banks();
+}
+
+/**************************************************************************
+ * DRAM initalization and size detection
+ */
+phys_size_t initdram (int board_type)
+{
+	long bank_size;
+	long size;
+	int cs;
+
+	/* during size detection, set up the max DDRLAW size */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
+	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
+
+	/* set CS bounds to maximum size */
+	for(cs = 0; cs < 4; ++cs) {
+		set_cs_bounds(cs,
+			CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+			DDR_MAX_SIZE_PER_CS);
+
+		set_cs_config(cs, INITIAL_CS_CONFIG);
+	}
+
+	/* configure ddr controller */
+	set_ddr_config();
+
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
+		SDRAM_CFG_SREN |
+		SDRAM_CFG_SDRAM_TYPE_DDR1);
+	SYNC;
+
+	/* size detection */
+	debug("\n");
+	size = 0;
+	for(cs = 0; cs < 4; ++cs) {
+		debug("\nDetecting Bank%d\n", cs);
+
+		bank_size = get_ddr_bank_size(cs,
+			(volatile long*)(CONFIG_SYS_DDR_BASE + size));
+		size += bank_size;
+
+		debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
+
+		/* exit if less than one bank */
+		if(size < DDR_MAX_SIZE_PER_CS) break;
+	}
+
+	return size;
+}
+
+/**************************************************************************
+ * checkboard()
+ */
+int checkboard (void)
+{
+	puts("Board: TQM834x\n");
+
+#ifdef CONFIG_PCI
+	volatile immap_t * immr;
+	u32 w, f;
+
+	immr = (immap_t *)CONFIG_SYS_IMMR;
+	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
+		printf("PCI:   NOT in host mode..?!\n");
+		return 0;
+	}
+
+	/* get bus width */
+	w = 32;
+	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
+		w = 64;
+
+	/* get clock */
+	f = gd->pci_clk;
+
+	printf("PCI1:  %d bit, %d MHz\n", w, f / 1000000);
+#else
+	printf("PCI:   disabled\n");
+#endif
+	return 0;
+}
+
+
+/**************************************************************************
+ *
+ * Local functions
+ *
+ *************************************************************************/
+
+/**************************************************************************
+ * Detect the number of flash banks (1 or 2). Store it in
+ * a global variable tqm834x_num_flash_banks.
+ * Bank detection code based on the Monitor code.
+ */
+static int detect_num_flash_banks(void)
+{
+	typedef unsigned long FLASH_PORT_WIDTH;
+	typedef volatile unsigned long FLASH_PORT_WIDTHV;
+	FPWV *bank1_base;
+	FPWV *bank2_base;
+	FPW bank1_read;
+	FPW bank2_read;
+	ulong bank1_size;
+	ulong bank2_size;
+	ulong total_size;
+
+	cfi_flash_num_flash_banks = 2;	/* assume two banks */
+
+	/* Get bank 1 and 2 information */
+	bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
+	debug("Bank1 size: %lu\n", bank1_size);
+	bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
+	debug("Bank2 size: %lu\n", bank2_size);
+	total_size = bank1_size + bank2_size;
+
+	if (bank2_size > 0) {
+		/* Seems like we've got bank 2, but maybe it's mirrored 1 */
+
+		/* Set the base addresses */
+		bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+		bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
+
+		/* Put bank 2 into CFI command mode and read */
+		bank2_base[0x55] = 0x00980098;
+		IOSYNC;
+		ISYNC;
+		bank2_read = bank2_base[0x10];
+
+		/* Read from bank 1 (it's in read mode) */
+		bank1_read = bank1_base[0x10];
+
+		/* Reset Flash */
+		bank1_base[0] = 0x00F000F0;
+		bank2_base[0] = 0x00F000F0;
+
+		if (bank2_read == bank1_read) {
+			/*
+			 * Looks like just one bank, but not sure yet. Let's
+			 * read from bank 2 in autosoelect mode.
+			 */
+			bank2_base[0x0555] = 0x00AA00AA;
+			bank2_base[0x02AA] = 0x00550055;
+			bank2_base[0x0555] = 0x00900090;
+			IOSYNC;
+			ISYNC;
+			bank2_read = bank2_base[0x10];
+
+			/* Read from bank 1 (it's in read mode) */
+			bank1_read = bank1_base[0x10];
+
+			/* Reset Flash */
+			bank1_base[0] = 0x00F000F0;
+			bank2_base[0] = 0x00F000F0;
+
+			if (bank2_read == bank1_read) {
+				/*
+				 * In both CFI command and autoselect modes,
+				 * we got the some data reading from Flash.
+				 * There is only one mirrored bank.
+				 */
+				cfi_flash_num_flash_banks = 1;
+				total_size = bank1_size;
+			}
+		}
+	}
+
+	debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
+
+	/* set OR0 and BR0 */
+	set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+		   (-(total_size) & OR_GPCM_AM));
+	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+		   (BR_MS_GPCM | BR_PS_32 | BR_V));
+
+	return (0);
+}
+
+/*************************************************************************
+ * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
+ */
+static long int get_ddr_bank_size(short cs, volatile long *base)
+{
+	/* This array lists all valid DDR SDRAM configurations, with
+	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
+	 * The last entry has to to have size equal 0 and is igonred during
+	 * autodection. Bank sizes must be in increasing order of size
+	 */
+	struct {
+		long row;
+		long col;
+		long size;
+	} conf[] = {
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_8,	32 << 20},
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_9,	64 << 20},
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_10,	128 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_9,	128 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_10,	256 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_11,	512 << 20},
+		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_10,	512 << 20},
+		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_11,	1024 << 20},
+		{0,			0,			0}
+	};
+
+	int i;
+	int detected;
+	long size;
+
+	detected = -1;
+	for(i = 0; conf[i].size != 0; ++i) {
+
+		/* set sdram bank configuration */
+		set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
+
+		debug("Getting RAM size...\n");
+		size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
+
+		if((size == conf[i].size) && (i == detected + 1))
+			detected = i;
+
+		debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
+			conf[i].row,
+			conf[i].col,
+			conf[i].size >> 20,
+			base,
+			size >> 20);
+	}
+
+	if(detected == -1){
+		/* disable empty cs */
+		debug("\nNo valid configurations for CS%d, disabling...\n", cs);
+		set_cs_config(cs, 0);
+		return 0;
+	}
+
+	debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
+			conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
+
+	/* configure cs ro detected params */
+	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
+			conf[detected].col);
+
+	set_cs_bounds(cs, (long)base, conf[detected].size);
+
+	return(conf[detected].size);
+}
+
+/**************************************************************************
+ * Sets DDR bank CS bounds.
+ */
+static void set_cs_bounds(short cs, long base, long size)
+{
+	debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
+	if(size == 0){
+		im->ddr.csbnds[cs].csbnds = 0x00000000;
+	} else {
+		im->ddr.csbnds[cs].csbnds =
+			((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+			(((base + size - 1) >> CSBNDS_EA_SHIFT) &
+				CSBNDS_EA);
+	}
+	SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR banks CS configuration.
+ * config == 0x00000000 disables the CS.
+ */
+static void set_cs_config(short cs, long config)
+{
+	debug("Setting config %08x for cs %d\n", config, cs);
+	im->ddr.cs_config[cs] = config;
+	SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR clocks, timings and configuration.
+ */
+static void set_ddr_config(void) {
+	/* clock control */
+	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
+		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+	SYNC;
+
+	/* timing configuration */
+	im->ddr.timing_cfg_1 =
+		(4 << TIMING_CFG1_PRETOACT_SHIFT) |
+		(7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
+		(4 << TIMING_CFG1_ACTTORW_SHIFT)  |
+		(5 << TIMING_CFG1_REFREC_SHIFT)   |
+		(3 << TIMING_CFG1_WRREC_SHIFT)    |
+		(3 << TIMING_CFG1_ACTTOACT_SHIFT) |
+		(1 << TIMING_CFG1_WRTORD_SHIFT)   |
+		(TIMING_CFG1_CASLAT & TIMING_CASLAT);
+
+	im->ddr.timing_cfg_2 =
+		TIMING_CFG2_CPO_DEF |
+		(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
+	SYNC;
+
+	/* don't enable DDR controller yet */
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN |
+		SDRAM_CFG_SDRAM_TYPE_DDR1;
+	SYNC;
+
+	/* Set SDRAM mode */
+	im->ddr.sdram_mode =
+		((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
+			SDRAM_MODE_ESD_SHIFT) |
+		((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
+			SDRAM_MODE_SD_SHIFT) |
+		((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
+			MODE_CASLAT);
+	SYNC;
+
+	/* Set fast SDRAM refresh rate */
+	im->ddr.sdram_interval =
+		(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
+		(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
+	SYNC;
+
+	/* Workaround for DDR6 Erratum
+	 * see MPC8349E Device Errata Rev.8, 2/2006
+	 * This workaround influences the MPC internal "input enables"
+	 * dependent on CAS latency and MPC revision. According to errata
+	 * sheet the internal reserved registers for this workaround are
+	 * not available from revision 2.0 and up.
+	 */
+
+	/* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
+	 * (0x200)
+	 */
+	if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
+
+		/* There is a internal reserved register at IMMRBAR+0x2F00
+		 * which has to be written with a certain value defined by
+		 * errata sheet.
+		 */
+		u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
+
+#if defined(DDR_CASLAT_20)
+		*reserved_p = 0x201c0000;
+#else
+		*reserved_p = 0x202c0000;
+#endif
+	}
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif	/* CONFIG_PCI */
+}
+#endif	/* CONFIG_OF_BOARD_SETUP */
diff --git a/u-boot/board/tqc/tqm85xx/Makefile b/u-boot/board/tqc/tqm85xx/Makefile
new file mode 100644
index 0000000..a40a895
--- /dev/null
+++ b/u-boot/board/tqc/tqm85xx/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= sdram.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+COBJS-$(CONFIG_NAND) += nand.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tqc/tqm85xx/law.c b/u-boot/board/tqc/tqm85xx/law.c
new file mode 100644
index 0000000..c596303
--- /dev/null
+++ b/u-boot/board/tqc/tqm85xx/law.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * Standard mapping:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
+ * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
+ * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
+ * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
+ * 0xfc00_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
+ *
+ * Big FLASH mapping:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xa000_0000	   0xa000_ffff	   CCSR			   1M
+ * 0xa200_0000	   0xa2ff_ffff	   PCI1 IO		   16M
+ * 0xa300_0000	   0xa3ff_ffff	   CAN and NAND Flash	   16M
+ * 0xaf00_0000	   0xafff_ffff     PCI express IO          16M
+ * 0xb000_0000	   0xbfff_ffff	   RapidIO or PCI express  256M
+ * 0xc000_0000	   0xffff_ffff	   FLASH (boot bank)	   1G
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#ifdef CONFIG_TQM_BIGFLASH
+#define LAW_3_SIZE LAW_SIZE_1G
+#define LAW_5_SIZE LAW_SIZE_256M
+#else
+#define LAW_3_SIZE LAW_SIZE_128M
+#define LAW_5_SIZE LAW_SIZE_512M
+#endif
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
+#ifndef CONFIG_PCIE1
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
+#endif /* CONFIG_PCIE1 */
+#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
+	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
+};
+
+int num_law_entries = ARRAY_SIZE (law_table);
diff --git a/u-boot/board/tqc/tqm85xx/nand.c b/u-boot/board/tqc/tqm85xx/nand.c
new file mode 100644
index 0000000..4b16c31
--- /dev/null
+++ b/u-boot/board/tqc/tqm85xx/nand.c
@@ -0,0 +1,472 @@
+/*
+ * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
+ *
+ * (C) Copyright 2006
+ * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/fsl_upm.h>
+#include <ioports.h>
+
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern uint get_lbc_clock (void);
+
+/* index of UPM RAM array run pattern for NAND command cycle */
+#define	CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS	0x08
+
+/* index of UPM RAM array run pattern for NAND address cycle */
+#define	CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x10
+
+/* Structure for table with supported UPM timings */
+struct upm_freq {
+	ulong freq;
+	const u32 *upm_patt;
+	uchar gpl4_disable;
+	uchar ehtr;
+	uchar ead;
+};
+
+/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */
+
+/* UPM pattern for bus clock = 25 MHz */
+static const u32 upm_patt_25[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
+	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 33.3 MHz */
+static const u32 upm_patt_33[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
+	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 41.7 MHz */
+static const u32 upm_patt_42[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
+	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 50 MHz */
+static const u32 upm_patt_50[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
+	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 66.7 MHz */
+static const u32 upm_patt_67[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
+	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 83.3 MHz */
+static const u32 upm_patt_83[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
+	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 100 MHz */
+static const u32 upm_patt_100[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
+	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 133.3 MHz */
+static const u32 upm_patt_133[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
+	/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 166.7 MHz */
+static const u32 upm_patt_167[] = {
+	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
+	/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
+	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write CMD */
+	/* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35,
+	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
+	/* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35,
+	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Single RAM array entry -> NAND Write Data */
+	/* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05,
+	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+	/* UPM Write Burst RAM array entry -> unused */
+	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Refresh Timer RAM array entry -> unused */
+	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+	/* UPM Exception RAM array entry -> unsused */
+	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* Supported UPM timings */
+struct upm_freq upm_freq_table[] = {
+	/* nominal freq. | ptr to table | GPL4 dis. | EHTR  | EAD */
+	{25000000, upm_patt_25, 1, 0, 0},
+	{33333333, upm_patt_33, 1, 0, 0},
+	{41666666, upm_patt_42, 1, 0, 0},
+	{50000000, upm_patt_50, 0, 0, 0},
+	{66666666, upm_patt_67, 0, 0, 0},
+	{83333333, upm_patt_83, 0, 0, 0},
+	{100000000, upm_patt_100, 0, 1, 1},
+	{133333333, upm_patt_133, 0, 1, 1},
+	{166666666, upm_patt_167, 0, 1, 1},
+};
+
+#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq))
+
+volatile const u32 *nand_upm_patt;
+
+/*
+ * write into UPMB ram
+ */
+static void upmb_write (u_char addr, ulong val)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32 (&lbc->mdr, val);
+
+	clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK,
+			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
+
+	/* dummy access to perform write */
+	out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
+
+	clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
+}
+
+/*
+ * Initialize UPM for NAND flash access.
+ */
+static void nand_upm_setup (volatile fsl_lbc_t *lbc)
+{
+	uint i, j;
+	uint or3 = CONFIG_SYS_OR3_PRELIM;
+	uint clock = get_lbc_clock ();
+
+	set_lbc_br(3, 0);	/* disable bank and reset all bits */
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+
+	/*
+	 * Search appropriate UPM table for bus clock.
+	 * If the bus clock exceeds a tolerated value, take the UPM timing for
+	 * the next higher supported frequency to ensure that access works
+	 * (even the access may be slower then).
+	 */
+	for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
+		;
+
+	if (i >= UPM_FREQS)
+	/* no valid entry found */
+		/* take last entry with configuration for max. bus clock */
+		i--;
+
+	if (upm_freq_table[i].ehtr) {
+		/* EHTR must be set due to TQM8548 timing specification */
+		or3 |= OR_UPM_EHTR;
+	}
+	if (upm_freq_table[i].ead)
+		/* EAD must be set due to TQM8548 timing specification */
+		or3 |= OR_UPM_EAD;
+
+	set_lbc_or(3, or3);
+
+	/* Assign address of table */
+	nand_upm_patt = upm_freq_table[i].upm_patt;
+
+	for (j = 0; j < 64; j++) {
+		upmb_write (j, *nand_upm_patt);
+		nand_upm_patt++;
+	}
+
+	/* Put UPM back to normal operation mode */
+	if (upm_freq_table[i].gpl4_disable)
+		/* GPL4 must be disabled according to timing specification */
+		out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
+
+	return;
+}
+
+static struct fsl_upm_nand fun = {
+	.width = 8,
+	.upm_cmd_offset = 0x08,
+	.upm_addr_offset = 0x10,
+	.upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
+	.chip_offset = CONFIG_SYS_NAND_CS_DIST,
+	.chip_delay = NAND_BIG_DELAY_US,
+	.wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
+};
+
+void board_nand_select_device (struct nand_chip *nand, int chip)
+{
+}
+
+int board_nand_init (struct nand_chip *nand)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	if (!nand_upm_patt)
+		nand_upm_setup (lbc);
+
+	fun.upm.io_addr = nand->IO_ADDR_R;
+	fun.upm.mxmr = (void __iomem *)&lbc->mbmr;
+	fun.upm.mdr = (void __iomem *)&lbc->mdr;
+	fun.upm.mar = (void __iomem *)&lbc->mar;
+
+	return fsl_upm_nand_init (nand, &fun);
+}
diff --git a/u-boot/board/tqc/tqm85xx/sdram.c b/u-boot/board/tqc/tqm85xx/sdram.c
new file mode 100644
index 0000000..39a9e21
--- /dev/null
+++ b/u-boot/board/tqc/tqm85xx/sdram.c
@@ -0,0 +1,429 @@
+
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+struct sdram_conf_s {
+	unsigned long size;
+	unsigned long reg;
+#ifdef CONFIG_TQM8548
+	unsigned long refresh;
+#endif /* CONFIG_TQM8548 */
+};
+
+typedef struct sdram_conf_s sdram_conf_t;
+
+#ifdef CONFIG_TQM8548
+#ifdef CONFIG_TQM8548_AG
+sdram_conf_t ddr_cs_conf[] = {
+	{(1024 << 20), 0x80044202, 0x0002D000},	/* 1024MB, 14x10(4)	*/
+	{ (512 << 20), 0x80044102, 0x0001A000},	/*  512MB, 13x10(4)	*/
+	{ (256 << 20), 0x80040102, 0x00014000},	/*  256MB, 13x10(4)	*/
+	{ (128 << 20), 0x80040101, 0x0000C000},	/*  128MB, 13x9(4)	*/
+};
+#else /* !CONFIG_TQM8548_AG */
+sdram_conf_t ddr_cs_conf[] = {
+	{(512 << 20), 0x80044102, 0x0001A000},	/* 512MB, 13x10(4)	*/
+	{(256 << 20), 0x80040102, 0x00014000},	/* 256MB, 13x10(4)	*/
+	{(128 << 20), 0x80040101, 0x0000C000},	/* 128MB, 13x9(4)	*/
+};
+#endif /* CONFIG_TQM8548_AG */
+#else /* !CONFIG_TQM8548 */
+sdram_conf_t ddr_cs_conf[] = {
+	{(512 << 20), 0x80000202},	/* 512MB, 14x10(4)	*/
+	{(256 << 20), 0x80000102},	/* 256MB, 13x10(4)	*/
+	{(128 << 20), 0x80000101},	/* 128MB, 13x9(4)	*/
+	{( 64 << 20), 0x80000001},	/*  64MB, 12x9(4)	*/
+};
+#endif /* CONFIG_TQM8548 */
+
+#define	N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
+
+int cas_latency (void);
+static phys_size_t sdram_setup(int);
+
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ *       so this should be extended for other future boards
+ *       using this routine!
+ */
+phys_size_t fixed_sdram(void)
+{
+	int casl = 0;
+	phys_size_t dram_size = 0;
+
+	casl = cas_latency();
+	dram_size = sdram_setup(casl);
+	if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
+		/*
+		 * Try again with default CAS latency
+		 */
+		printf("Problem with CAS lantency, using default CL %d/10!\n",
+		       CONFIG_DDR_DEFAULT_CL);
+		dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
+		puts("       ");
+	}
+	return dram_size;
+}
+
+static phys_size_t sdram_setup(int casl)
+{
+	int i;
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#ifdef CONFIG_TQM8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+#endif
+#else /* !CONFIG_TQM8548 */
+	unsigned long cfg_ddr_timing1;
+	unsigned long cfg_ddr_mode;
+#endif /* CONFIG_TQM8548 */
+
+	/*
+	 * Disable memory controller.
+	 */
+	ddr->cs0_config = 0;
+	ddr->sdram_cfg = 0;
+
+#ifdef CONFIG_TQM8548
+	/* Timing and refresh settings for DDR2-533 and below */
+
+	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
+	ddr->cs0_config = ddr_cs_conf[0].reg;
+	ddr->timing_cfg_3 = 0x00020000;
+
+	/* TIMING CFG 1, 533MHz
+	 * PRETOACT: 4 Clocks
+	 * ACTTOPRE: 12 Clocks
+	 * ACTTORW:  4 Clocks
+	 * CASLAT:   4 Clocks
+	 * REFREC:   EXT_REFREC:REFREC 53 Clocks
+	 * WRREC:    4 Clocks
+	 * ACTTOACT: 3 Clocks
+	 * WRTORD:   2 Clocks
+	 */
+	ddr->timing_cfg_1 = 0x4C47D432;
+
+	/* TIMING CFG 2, 533MHz
+	 * ADD_LAT:       3 Clocks
+	 * CPO:           READLAT + 1
+	 * WR_LAT:        3 Clocks
+	 * RD_TO_PRE:     2 Clocks
+	 * WR_DATA_DELAY: 1/2 Clock
+	 * CKE_PLS:       3 Clock
+	 * FOUR_ACT:      14 Clocks
+	 */
+	ddr->timing_cfg_2 = 0x331848CE;
+
+	/* DDR SDRAM Mode, 533MHz
+	 * MRS:          Extended Mode Register
+	 * OUT:          Outputs enabled
+	 * RDQS:         no
+	 * DQS:          enabled
+	 * OCD:          default state
+	 * RTT:          75 Ohms
+	 * Posted CAS:   3 Clocks
+	 * ODS:          reduced strength
+	 * DLL:          enabled
+	 * MR:           Mode Register
+	 * PD:           fast exit
+	 * WR:           4 Clocks
+	 * DLL:          no DLL reset
+	 * TM:           normal
+	 * CAS latency:  4 Clocks
+	 * BT:           sequential
+	 * Burst length: 4
+	 */
+	ddr->sdram_mode = 0x439E0642;
+
+	/* DDR SDRAM Interval, 533MHz
+	 * REFINT:  1040 Clocks
+	 * BSTOPRE: 256
+	 */
+	ddr->sdram_interval = (1040 << 16) | 0x100;
+
+	/*
+	 * Workaround for erratum DDR19 according to MPC8548 Device Errata
+	 * document, Rev. 1: DDR IO receiver must be set to an acceptable
+	 * bias point by modifying a hidden register.
+	 */
+	if (SVR_REV (get_svr ()) < 0x21)
+		gur->ddrioovcr = 0x90000000;	/* enable, VSEL 1.8V */
+
+	/* DDR SDRAM CFG 2
+	 * FRC_SR:      normal mode
+	 * SR_IE:       no self-refresh interrupt
+	 * DLL_RST_DIS: don't care, leave at reset value
+	 * DQS_CFG:     differential DQS signals
+	 * ODT_CFG:     assert ODT to internal IOs only during reads to DRAM
+	 * LVWx_CFG:    don't care, leave at reset value
+	 * NUM_PR:      1 refresh will be issued at a time
+	 * DM_CFG:      don't care, leave at reset value
+	 * D_INIT:      no data initialization
+	 */
+	ddr->sdram_cfg_2 = 0x04401000;
+
+	/* DDR SDRAM MODE 2
+	 * MRS: Extended Mode Register 2
+	 */
+	ddr->sdram_mode_2 = 0x8000C000;
+
+	/* DDR SDRAM CLK CNTL
+	 * CLK_ADJUST: 1/2 Clock 0x02000000
+	 * CLK_ADJUST: 5/8 Clock 0x02800000
+	 */
+	ddr->sdram_clk_cntl = 0x02800000;
+
+	/* wait for clock stabilization */
+	asm ("sync;isync;msync");
+	udelay (1000);
+
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+	/*
+	 * Workaround for erratum DDR20 according to MPC8548 Device Errata
+	 * document, Rev. 1: "CKE signal may not function correctly after
+	 * assertion of HRESET"
+	 */
+
+	/* 1. Configure DDR register as is done in normal DDR configuration.
+	 *    Do not set DDR_SDRAM_CFG[MEM_EN].
+	 *
+	 * 2. Set reserved bit EEBACR[3] at offset 0x1000
+	 */
+	ecm->eebacr |= 0x10000000;
+
+	/*
+	 * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
+	 *
+	 * DDR_SDRAM_CFG_2:
+	 * FRC_SR:      normal mode
+	 * SR_IE:       no self-refresh interrupt
+	 * DLL_RST_DIS: don't care, leave at reset value
+	 * DQS_CFG:     differential DQS signals
+	 * ODT_CFG:     assert ODT to internal IOs only during reads to DRAM
+	 * LVWx_CFG:    don't care, leave at reset value
+	 * NUM_PR:      1 refresh will be issued at a time
+	 * DM_CFG:      don't care, leave at reset value
+	 * D_INIT:      enable data initialization
+	 */
+	ddr->sdram_cfg_2 |= 0x00000010;
+
+	/*
+	 * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
+	 *    training
+	 */
+	ddr->debug[2] |= 0x00000400;
+
+	/*
+	 * 5. Wait 200 micro-seconds
+	 */
+	udelay (200);
+
+	/*
+	 * 6. Set DDR_SDRAM_CFG[MEM_EN]
+	 *
+	 * BTW, initialize DDR_SDRAM_CFG:
+	 * MEM_EN:       enabled
+	 * SREN:         don't care, leave at reset value
+	 * ECC_EN:       no error report
+	 * RD_EN:        no registered DIMMs
+	 * SDRAM_TYPE:   DDR2
+	 * DYN_PWR:      no power management
+	 * 32_BE:        don't care, leave at reset value
+	 * 8_BE:         4 beat burst
+	 * NCAP:         don't care, leave at reset value
+	 * 2T_EN:        1T Timing
+	 * BA_INTLV_CTL: no interleaving
+	 * x32_EN:       x16 organization
+	 * PCHB8:        MA[10] for auto-precharge
+	 * HSE:          half strength for single and 2-layer stacks
+	 *               (full strength for 3- and 4-layer stacks not
+	 *               yet considered)
+	 * MEM_HALT:     no halt
+	 * BI:           automatic initialization
+	 */
+	ddr->sdram_cfg = 0x83000008;
+
+	/*
+	 * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
+	 */
+	asm ("sync;isync;msync");
+	while (ddr->sdram_cfg_2 & 0x00000010)
+		asm ("eieio");
+
+	/*
+	 * 8. Clear D3[21] to re-enable data training
+	 */
+	ddr->debug[2] &= ~0x00000400;
+
+	/*
+	 * 9. Set D2(21) to force data training to run
+	 */
+	ddr->debug[1] |= 0x00000400;
+
+	/*
+	 * 10. Poll on D2[21] until it is cleared by hardware
+	 */
+	asm ("sync;isync;msync");
+	while (ddr->debug[1] & 0x00000400)
+		asm ("eieio");
+
+	/*
+	 * 11. Clear reserved bit EEBACR[3] at offset 0x1000
+	 */
+	ecm->eebacr &= ~0x10000000;
+
+#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
+
+	/* DDR SDRAM CLK CNTL
+	 * MEM_EN:       enabled
+	 * SREN:         don't care, leave at reset value
+	 * ECC_EN:       no error report
+	 * RD_EN:        no register DIMMs
+	 * SDRAM_TYPE:   DDR2
+	 * DYN_PWR:      no power management
+	 * 32_BE:        don't care, leave at reset value
+	 * 8_BE:         4 beat burst
+	 * NCAP:         don't care, leave at reset value
+	 * 2T_EN:        1T Timing
+	 * BA_INTLV_CTL: no interleaving
+	 * x32_EN:       x16 organization
+	 * PCHB8:        MA[10] for auto-precharge
+	 * HSE:          half strength for single and 2-layer stacks
+	 * (full strength for 3- and 4-layer stacks no yet considered)
+	 * MEM_HALT:     no halt
+	 * BI:           automatic initialization
+	 */
+	ddr->sdram_cfg = 0x83000008;
+
+#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
+
+	asm ("sync; isync; msync");
+	udelay (1000);
+#else /* !CONFIG_TQM8548 */
+	switch (casl) {
+	case 20:
+		cfg_ddr_timing1 = 0x47405331 | (3 << 16);
+		cfg_ddr_mode = 0x40020002 | (2 << 4);
+		break;
+
+	case 25:
+		cfg_ddr_timing1 = 0x47405331 | (4 << 16);
+		cfg_ddr_mode = 0x40020002 | (6 << 4);
+		break;
+
+	case 30:
+	default:
+		cfg_ddr_timing1 = 0x47405331 | (5 << 16);
+		cfg_ddr_mode = 0x40020002 | (3 << 4);
+		break;
+	}
+
+	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
+	ddr->cs0_config = ddr_cs_conf[0].reg;
+	ddr->timing_cfg_1 = cfg_ddr_timing1;
+	ddr->timing_cfg_2 = 0x00000800;		/* P9-45,may need tuning */
+	ddr->sdram_mode = cfg_ddr_mode;
+	ddr->sdram_interval = 0x05160100;	/* autocharge,no open page */
+	ddr->err_disable = 0x0000000D;
+
+	asm ("sync; isync; msync");
+	udelay (1000);
+
+	ddr->sdram_cfg = 0xc2000000;		/* unbuffered,no DYN_PWR */
+	asm ("sync; isync; msync");
+	udelay (1000);
+#endif /* CONFIG_TQM8548 */
+
+	for (i = 0; i < N_DDR_CS_CONF; i++) {
+		ddr->cs0_config = ddr_cs_conf[i].reg;
+
+		if (get_ram_size (0, ddr_cs_conf[i].size) ==
+		    ddr_cs_conf[i].size) {
+			/*
+			 * size detected -> set Chip Select Bounds Register
+			 */
+			ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
+
+			break;
+		}
+	}
+
+#ifdef CONFIG_TQM8548
+	if (i < N_DDR_CS_CONF) {
+		/* Adjust refresh rate for DDR2 */
+
+		ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
+
+		ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
+		    (ddr_cs_conf[i].refresh & 0x0000F000);
+
+		return ddr_cs_conf[i].size;
+	}
+#endif /* CONFIG_TQM8548 */
+
+	/* return size if detected, else return 0 */
+	return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
diff --git a/u-boot/board/tqc/tqm85xx/tlb.c b/u-boot/board/tqc/tqm85xx/tlb.c
new file mode 100644
index 0000000..f9f8cc9
--- /dev/null
+++ b/u-boot/board/tqc/tqm85xx/tlb.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		       0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		       0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		       0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		       0, 0, BOOKE_PAGESZ_4K, 0),
+
+#ifndef CONFIG_TQM_BIGFLASH
+	/*
+	 * TLB 0, 1:	128M	Non-cacheable, guarded
+	 * 0xf8000000	128M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 1, BOOKE_PAGESZ_64M, 1),
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+		       CONFIG_SYS_FLASH_BASE + 0x4000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 0, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 3, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	PCI express MEM First half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	PCI express MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
+		       CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 5, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		       CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 5, BOOKE_PAGESZ_256M, 1),
+#endif /* CONFIG_PCIE */
+
+	/*
+	 * TLB 6:	 64M	Non-cacheable, guarded
+	 * 0xe0000000	  1M	CCSRBAR
+	 * 0xe2000000	 16M	PCI1 IO
+	 * 0xe3000000	 16M	CAN and NAND Flash
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 6, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 9:	 16M	Non-cacheable, guarded
+	 * 0xef000000	 16M	PCI express IO
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 9, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
+#else /* CONFIG_TQM_BIGFLASH */
+
+	/*
+	 * TLB 0,1,2,3:	  1G	Non-cacheable, guarded
+	 * 0xc0000000	  1G	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 3, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
+		       CONFIG_SYS_FLASH_BASE + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 2, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
+		       CONFIG_SYS_FLASH_BASE + 0x20000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 1, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
+		       CONFIG_SYS_FLASH_BASE + 0x30000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 5, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	PCI express MEM First half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 6, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 6, BOOKE_PAGESZ_256M, 1),
+
+#endif /* CONFIG_PCIE */
+
+	/*
+	 * TLB 7:	 64M	Non-cacheable, guarded
+	 * 0xa0000000	  1M	CCSRBAR
+	 * 0xa2000000	 16M	PCI1 IO
+	 * 0xa3000000	 16M	CAN and NAND Flash
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 7, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 10:	 16M	Non-cacheable, guarded
+	 * 0xaf000000	 16M	PCI express IO
+	 */
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 10, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
+#endif /* CONFIG_TQM_BIGFLASH */
+};
+
+int num_tlb_entries = ARRAY_SIZE (tlb_table);
diff --git a/u-boot/board/tqc/tqm85xx/tqm85xx.c b/u-boot/board/tqc/tqm85xx/tqm85xx.c
new file mode 100644
index 0000000..99b1331
--- /dev/null
+++ b/u-boot/board/tqc/tqm85xx/tqm85xx.c
@@ -0,0 +1,623 @@
+/*
+ * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
+ *
+ * (C) Copyright 2006
+ * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <linux/compiler.h>
+#include <ioports.h>
+#include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
+void local_bus_init (void);
+ulong flash_get_size (ulong base, int banknum);
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init (void);
+#endif
+
+#ifdef CONFIG_CPM2
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A: conf, ppar, psor, pdir, podr, pdat */
+	{
+	 {1, 1, 1, 0, 0, 0},	/* PA31: FCC1 MII COL */
+	 {1, 1, 1, 0, 0, 0},	/* PA30: FCC1 MII CRS */
+	 {1, 1, 1, 1, 0, 0},	/* PA29: FCC1 MII TX_ER */
+	 {1, 1, 1, 1, 0, 0},	/* PA28: FCC1 MII TX_EN */
+	 {1, 1, 1, 0, 0, 0},	/* PA27: FCC1 MII RX_DV */
+	 {1, 1, 1, 0, 0, 0},	/* PA26: FCC1 MII RX_ER */
+	 {0, 1, 0, 1, 0, 0},	/* PA25: FCC1 ATMTXD[0] */
+	 {0, 1, 0, 1, 0, 0},	/* PA24: FCC1 ATMTXD[1] */
+	 {0, 1, 0, 1, 0, 0},	/* PA23: FCC1 ATMTXD[2] */
+	 {0, 1, 0, 1, 0, 0},	/* PA22: FCC1 ATMTXD[3] */
+	 {1, 1, 0, 1, 0, 0},	/* PA21: FCC1 MII TxD[3] */
+	 {1, 1, 0, 1, 0, 0},	/* PA20: FCC1 MII TxD[2] */
+	 {1, 1, 0, 1, 0, 0},	/* PA19: FCC1 MII TxD[1] */
+	 {1, 1, 0, 1, 0, 0},	/* PA18: FCC1 MII TxD[0] */
+	 {1, 1, 0, 0, 0, 0},	/* PA17: FCC1 MII RxD[0] */
+	 {1, 1, 0, 0, 0, 0},	/* PA16: FCC1 MII RxD[1] */
+	 {1, 1, 0, 0, 0, 0},	/* PA15: FCC1 MII RxD[2] */
+	 {1, 1, 0, 0, 0, 0},	/* PA14: FCC1 MII RxD[3] */
+	 {0, 1, 0, 0, 0, 0},	/* PA13: FCC1 ATMRXD[3] */
+	 {0, 1, 0, 0, 0, 0},	/* PA12: FCC1 ATMRXD[2] */
+	 {0, 1, 0, 0, 0, 0},	/* PA11: FCC1 ATMRXD[1] */
+	 {0, 1, 0, 0, 0, 0},	/* PA10: FCC1 ATMRXD[0] */
+	 {0, 1, 1, 1, 0, 0},	/* PA9 : FCC1 L1TXD */
+	 {0, 1, 1, 0, 0, 0},	/* PA8 : FCC1 L1RXD */
+	 {0, 0, 0, 1, 0, 0},	/* PA7 : PA7 */
+	 {0, 1, 1, 1, 0, 0},	/* PA6 : TDM A1 L1RSYNC */
+	 {0, 0, 0, 1, 0, 0},	/* PA5 : PA5 */
+	 {0, 0, 0, 1, 0, 0},	/* PA4 : PA4 */
+	 {0, 0, 0, 1, 0, 0},	/* PA3 : PA3 */
+	 {0, 0, 0, 1, 0, 0},	/* PA2 : PA2 */
+	 {0, 0, 0, 0, 0, 0},	/* PA1 : FREERUN */
+	 {0, 0, 0, 1, 0, 0}	/* PA0 : PA0 */
+	 },
+
+	/* Port B: conf, ppar, psor, pdir, podr, pdat */
+	{
+	 {1, 1, 0, 1, 0, 0},	/* PB31: FCC2 MII TX_ER */
+	 {1, 1, 0, 0, 0, 0},	/* PB30: FCC2 MII RX_DV */
+	 {1, 1, 1, 1, 0, 0},	/* PB29: FCC2 MII TX_EN */
+	 {1, 1, 0, 0, 0, 0},	/* PB28: FCC2 MII RX_ER */
+	 {1, 1, 0, 0, 0, 0},	/* PB27: FCC2 MII COL */
+	 {1, 1, 0, 0, 0, 0},	/* PB26: FCC2 MII CRS */
+	 {1, 1, 0, 1, 0, 0},	/* PB25: FCC2 MII TxD[3] */
+	 {1, 1, 0, 1, 0, 0},	/* PB24: FCC2 MII TxD[2] */
+	 {1, 1, 0, 1, 0, 0},	/* PB23: FCC2 MII TxD[1] */
+	 {1, 1, 0, 1, 0, 0},	/* PB22: FCC2 MII TxD[0] */
+	 {1, 1, 0, 0, 0, 0},	/* PB21: FCC2 MII RxD[0] */
+	 {1, 1, 0, 0, 0, 0},	/* PB20: FCC2 MII RxD[1] */
+	 {1, 1, 0, 0, 0, 0},	/* PB19: FCC2 MII RxD[2] */
+	 {1, 1, 0, 0, 0, 0},	/* PB18: FCC2 MII RxD[3] */
+	 {1, 1, 0, 0, 0, 0},	/* PB17: FCC3:RX_DIV */
+	 {1, 1, 0, 0, 0, 0},	/* PB16: FCC3:RX_ERR */
+	 {1, 1, 0, 1, 0, 0},	/* PB15: FCC3:TX_ERR */
+	 {1, 1, 0, 1, 0, 0},	/* PB14: FCC3:TX_EN */
+	 {1, 1, 0, 0, 0, 0},	/* PB13: FCC3:COL */
+	 {1, 1, 0, 0, 0, 0},	/* PB12: FCC3:CRS */
+	 {1, 1, 0, 0, 0, 0},	/* PB11: FCC3:RXD */
+	 {1, 1, 0, 0, 0, 0},	/* PB10: FCC3:RXD */
+	 {1, 1, 0, 0, 0, 0},	/* PB9 : FCC3:RXD */
+	 {1, 1, 0, 0, 0, 0},	/* PB8 : FCC3:RXD */
+	 {1, 1, 0, 1, 0, 0},	/* PB7 : FCC3:TXD */
+	 {1, 1, 0, 1, 0, 0},	/* PB6 : FCC3:TXD */
+	 {1, 1, 0, 1, 0, 0},	/* PB5 : FCC3:TXD */
+	 {1, 1, 0, 1, 0, 0},	/* PB4 : FCC3:TXD */
+	 {0, 0, 0, 0, 0, 0},	/* PB3 : pin doesn't exist */
+	 {0, 0, 0, 0, 0, 0},	/* PB2 : pin doesn't exist */
+	 {0, 0, 0, 0, 0, 0},	/* PB1 : pin doesn't exist */
+	 {0, 0, 0, 0, 0, 0}	/* PB0 : pin doesn't exist */
+	 },
+
+	/* Port C: conf, ppar, psor, pdir, podr, pdat */
+	{
+	 {0, 0, 0, 1, 0, 0},	/* PC31: PC31 */
+	 {0, 0, 0, 1, 0, 0},	/* PC30: PC30 */
+	 {0, 1, 1, 0, 0, 0},	/* PC29: SCC1 EN *CLSN */
+	 {0, 0, 0, 1, 0, 0},	/* PC28: PC28 */
+	 {0, 0, 0, 1, 0, 0},	/* PC27: UART Clock in */
+	 {0, 0, 0, 1, 0, 0},	/* PC26: PC26 */
+	 {0, 0, 0, 1, 0, 0},	/* PC25: PC25 */
+	 {0, 0, 0, 1, 0, 0},	/* PC24: PC24 */
+	 {0, 1, 0, 1, 0, 0},	/* PC23: ATMTFCLK */
+	 {0, 1, 0, 0, 0, 0},	/* PC22: ATMRFCLK */
+	 {1, 1, 0, 0, 0, 0},	/* PC21: SCC1 EN RXCLK */
+	 {1, 1, 0, 0, 0, 0},	/* PC20: SCC1 EN TXCLK */
+	 {1, 1, 0, 0, 0, 0},	/* PC19: FCC2 MII RX_CLK CLK13 */
+	 {1, 1, 0, 0, 0, 0},	/* PC18: FCC Tx Clock (CLK14) */
+	 {1, 1, 0, 0, 0, 0},	/* PC17: PC17 */
+	 {1, 1, 0, 0, 0, 0},	/* PC16: FCC Tx Clock (CLK16) */
+	 {0, 1, 0, 0, 0, 0},	/* PC15: PC15 */
+	 {0, 1, 0, 0, 0, 0},	/* PC14: SCC1 EN *CD */
+	 {0, 1, 0, 0, 0, 0},	/* PC13: PC13 */
+	 {0, 1, 0, 1, 0, 0},	/* PC12: PC12 */
+	 {0, 0, 0, 1, 0, 0},	/* PC11: LXT971 transmit control */
+	 {0, 0, 0, 1, 0, 0},	/* PC10: FETHMDC */
+	 {0, 0, 0, 0, 0, 0},	/* PC9 : FETHMDIO */
+	 {0, 0, 0, 1, 0, 0},	/* PC8 : PC8 */
+	 {0, 0, 0, 1, 0, 0},	/* PC7 : PC7 */
+	 {0, 0, 0, 1, 0, 0},	/* PC6 : PC6 */
+	 {0, 0, 0, 1, 0, 0},	/* PC5 : PC5 */
+	 {0, 0, 0, 1, 0, 0},	/* PC4 : PC4 */
+	 {0, 0, 0, 1, 0, 0},	/* PC3 : PC3 */
+	 {0, 0, 0, 1, 0, 1},	/* PC2 : ENET FDE */
+	 {0, 0, 0, 1, 0, 0},	/* PC1 : ENET DSQE */
+	 {0, 0, 0, 1, 0, 0},	/* PC0 : ENET LBK */
+	 },
+
+	/* Port D: conf, ppar, psor, pdir, podr, pdat */
+	{
+#ifdef CONFIG_TQM8560
+	 {1, 1, 0, 0, 0, 0},	/* PD31: SCC1 EN RxD */
+	 {1, 1, 1, 1, 0, 0},	/* PD30: SCC1 EN TxD */
+	 {1, 1, 0, 1, 0, 0},	/* PD29: SCC1 EN TENA */
+#else /* !CONFIG_TQM8560 */
+	 {0, 0, 0, 0, 0, 0},	/* PD31: PD31 */
+	 {0, 0, 0, 0, 0, 0},	/* PD30: PD30 */
+	 {0, 0, 0, 0, 0, 0},	/* PD29: PD29 */
+#endif /* CONFIG_TQM8560 */
+	 {1, 1, 0, 0, 0, 0},	/* PD28: PD28 */
+	 {1, 1, 0, 1, 0, 0},	/* PD27: PD27 */
+	 {1, 1, 0, 1, 0, 0},	/* PD26: PD26 */
+	 {0, 0, 0, 1, 0, 0},	/* PD25: PD25 */
+	 {0, 0, 0, 1, 0, 0},	/* PD24: PD24 */
+	 {0, 0, 0, 1, 0, 0},	/* PD23: PD23 */
+	 {0, 0, 0, 1, 0, 0},	/* PD22: PD22 */
+	 {0, 0, 0, 1, 0, 0},	/* PD21: PD21 */
+	 {0, 0, 0, 1, 0, 0},	/* PD20: PD20 */
+	 {0, 0, 0, 1, 0, 0},	/* PD19: PD19 */
+	 {0, 0, 0, 1, 0, 0},	/* PD18: PD18 */
+	 {0, 1, 0, 0, 0, 0},	/* PD17: FCC1 ATMRXPRTY */
+	 {0, 1, 0, 1, 0, 0},	/* PD16: FCC1 ATMTXPRTY */
+	 {0, 1, 1, 0, 1, 0},	/* PD15: I2C SDA */
+	 {0, 0, 0, 1, 0, 0},	/* PD14: LED */
+	 {0, 0, 0, 0, 0, 0},	/* PD13: PD13 */
+	 {0, 0, 0, 0, 0, 0},	/* PD12: PD12 */
+	 {0, 0, 0, 0, 0, 0},	/* PD11: PD11 */
+	 {0, 0, 0, 0, 0, 0},	/* PD10: PD10 */
+	 {0, 1, 0, 1, 0, 0},	/* PD9 : SMC1 TXD */
+	 {0, 1, 0, 0, 0, 0},	/* PD8 : SMC1 RXD */
+	 {0, 0, 0, 1, 0, 1},	/* PD7 : PD7 */
+	 {0, 0, 0, 1, 0, 1},	/* PD6 : PD6 */
+	 {0, 0, 0, 1, 0, 1},	/* PD5 : PD5 */
+	 {0, 0, 0, 1, 0, 1},	/* PD4 : PD4 */
+	 {0, 0, 0, 0, 0, 0},	/* PD3 : pin doesn't exist */
+	 {0, 0, 0, 0, 0, 0},	/* PD2 : pin doesn't exist */
+	 {0, 0, 0, 0, 0, 0},	/* PD1 : pin doesn't exist */
+	 {0, 0, 0, 0, 0, 0}	/* PD0 : pin doesn't exist */
+	 }
+};
+#endif /*  CONFIG_CPM2 */
+
+#define CASL_STRING1	"casl=xx"
+#define CASL_STRING2	"casl="
+
+static const int casl_table[] = { 20, 25, 30 };
+#define	N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
+
+int cas_latency (void)
+{
+	char *s = getenv ("serial#");
+	int casl;
+	int val;
+	int i;
+
+	casl = CONFIG_DDR_DEFAULT_CL;
+
+	if (s != NULL) {
+		if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
+			    CASL_STRING2, strlen (CASL_STRING2)) == 0) {
+			val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
+
+			for (i = 0; i < N_CASL; ++i) {
+				if (val == casl_table[i]) {
+					return val;
+				}
+			}
+		}
+	}
+
+	return casl;
+}
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: %s", CONFIG_BOARDNAME);
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Recalculate CS configuration if second FLASH bank is available
+	 */
+	if (flash_info[0].size > 0) {
+		set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+			   (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+		set_lbc_br(1, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
+		/*
+		 * Re-check to get correct base address for bank 1
+		 */
+		flash_get_size (gd->bd->bi_flashstart, 0);
+	} else {
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
+	}
+
+	/*
+	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
+	 */
+	set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+		   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+	set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
+		   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
+	/*
+	 * Re-check to get correct base address for bank 0
+	 */
+	flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
+
+	/*
+	 * Re-do flash protection upon new addresses
+	 */
+	flash_protect (FLAG_PROTECT_CLEAR,
+		       gd->bd->bi_flashstart, 0xffffffff,
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+	/* Monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE, 0xffffffff,
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+	/* Environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	/* Redundant environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR_REDUND,
+		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CAN_DRIVER
+/*
+ * Initialize UPMC RAM
+ */
+static void upmc_write (u_char addr, uint val)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32 (&lbc->mdr, val);
+
+	clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
+			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
+
+	/* dummy access to perform write */
+	out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
+
+	/* normal operation */
+	clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
+}
+#endif /* CONFIG_CAN_DRIVER */
+
+uint get_lbc_clock (void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	sys_info_t sys_info;
+	ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
+
+	get_sys_info (&sys_info);
+
+	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+#ifdef CONFIG_MPC8548
+		/*
+		 * Yes, the entire PQ38 family use the same
+		 * bit-representation for twice the clock divider value.
+		 */
+		clkdiv *= 2;
+#endif
+		return sys_info.freqSystemBus / clkdiv;
+	}
+
+	puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint lbc_mhz = get_lbc_clock ()  / 1000000;
+
+#ifdef CONFIG_MPC8548
+	uint svr = get_svr ();
+	uint lcrr;
+
+	/*
+	 * MPC revision < 2.0
+	 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
+	 * Modify engineering use only register at address 0xE_0F20.
+	 * "1. Read register at offset 0xE_0F20
+	 * 2. And value with 0x0000_FFFF
+	 * 3. OR result with 0x0000_0004
+	 * 4. Write result back to offset 0xE_0F20."
+	 *
+	 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
+	 * Modify engineering use only register at address 0xE_0F20.
+	 * "1. Read register at offset 0xE_0F20
+	 * 2. And value with 0xFFFF_FFDF
+	 * 3. Write result back to offset 0xE_0F20."
+	 *
+	 * Since it is the same register, we do the modification in one step.
+	 */
+	if (SVR_MAJ (svr) < 2) {
+		uint dummy = gur->lbiuiplldcr1;
+		dummy &= 0x0000FFDF;
+		dummy |= 0x00000004;
+		gur->lbiuiplldcr1 = dummy;
+	}
+
+	lcrr = CONFIG_SYS_LBC_LCRR;
+
+	/*
+	 * Local Bus Clock > 83.3 MHz. According to timing
+	 * specifications set LCRR[EADC] to 2 delay cycles.
+	 */
+	if (lbc_mhz > 83) {
+		lcrr &= ~LCRR_EADC;
+		lcrr |= LCRR_EADC_2;
+	}
+
+	/*
+	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+	 * disable PLL bypass for Local Bus Clock > 83 MHz.
+	 */
+	if (lbc_mhz >= 66)
+		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
+
+	else
+		lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	lbc->lcrr = lcrr;
+	asm ("sync;isync;msync");
+
+	/*
+	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
+	 * and terminate with isync
+	 */
+	lcrr = lbc->lcrr;
+	asm ("isync;");
+
+	/* let DLL stabilize */
+	udelay (500);
+
+#else /* !CONFIG_MPC8548 */
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	if (lbc_mhz < 66) {
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
+		lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
+			     LTEDR_RAWA | LTEDR_CSD;	/* Disable all error checking */
+
+	} else if (lbc_mhz >= 133) {
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr ();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
+		udelay (200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm ("sync;isync;msync");
+	}
+#endif /* !CONFIG_MPC8548 */
+
+#ifdef	CONFIG_CAN_DRIVER
+	/*
+	 * According to timing specifications EAD must be
+	 * set if Local Bus Clock is > 83 MHz.
+	 */
+	if (lbc_mhz > 83)
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+	else
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+	set_lbc_br(2, CONFIG_SYS_BR2_CAN);
+
+	/* LGPL4 is UPWAIT */
+	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
+
+	/* Initialize UPMC for CAN: single read */
+	upmc_write (0x00, 0xFFFFED00);
+	upmc_write (0x01, 0xCCFFCC00);
+	upmc_write (0x02, 0x00FFCF00);
+	upmc_write (0x03, 0x00FFCF00);
+	upmc_write (0x04, 0x00FFDC00);
+	upmc_write (0x05, 0x00FFCF00);
+	upmc_write (0x06, 0x00FFED00);
+	upmc_write (0x07, 0x3FFFCC07);
+
+	/* Initialize UPMC for CAN: single write */
+	upmc_write (0x18, 0xFFFFED00);
+	upmc_write (0x19, 0xCCFFEC00);
+	upmc_write (0x1A, 0x00FFED80);
+	upmc_write (0x1B, 0x00FFED80);
+	upmc_write (0x1C, 0x00FFFC00);
+	upmc_write (0x1D, 0x0FFFEC00);
+	upmc_write (0x1E, 0x0FFFEF00);
+	upmc_write (0x1F, 0x3FFFEC05);
+#endif /* CONFIG_CAN_DRIVER */
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI1 */
+
+void pci_init_board (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	int pcie_ep;
+
+	u32 devdisr = in_be32(&gur->devdisr);
+
+	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
+	uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* PCI PSPEED in [4:5] */
+	uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333333) ? "33" :
+			(pci_speed == 66666666) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pcie_ep ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter");
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+#ifdef CONFIG_PCIX_CHECK
+		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
+			ushort reg16 =
+				PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
+				PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+			uint dev = PCI_BDF(0, 0, 0);
+
+			/* PCI-X init */
+			if (CONFIG_SYS_CLK_FREQ < 66000000)
+				puts ("PCI-X will only work at 66 MHz\n");
+
+			pci_write_config_word(dev, PCIX_COMMAND, reg16);
+		}
+#endif
+	} else {
+		printf("PCI1: disabled\n");
+	}
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+
+	FT_FSL_PCI_SETUP;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_PS2MULT
+	ps2mult_early_init ();
+#endif /* CONFIG_PS2MULT */
+	return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Intialize TSECs first */
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/tqc/tqm8xx/Makefile b/u-boot/board/tqc/tqm8xx/Makefile
new file mode 100644
index 0000000..888cf24
--- /dev/null
+++ b/u-boot/board/tqc/tqm8xx/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o load_sernum_ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/tqc/tqm8xx/load_sernum_ethaddr.c b/u-boot/board/tqc/tqm8xx/load_sernum_ethaddr.c
new file mode 100644
index 0000000..d269902
--- /dev/null
+++ b/u-boot/board/tqc/tqm8xx/load_sernum_ethaddr.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The TQM8xxL / TQM82xx Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset 0x0003FFC0
+ * - size 0x00000040
+ *
+ * Internal structure:
+ * - sequence of ASCII character strings
+ * - fields separated by a single space character (0x20)
+ * - last field terminated by NUL character (0x00)
+ * - remaining space filled with NUL characters (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) Serial Number
+ * 3) First MAC Address
+ * 4) Number of additional MAC addresses
+ */
+
+void load_sernum_ethaddr (void)
+{
+	unsigned char *hwi;
+	unsigned char  serial [CONFIG_SYS_HWINFO_SIZE];
+	unsigned char  ethaddr[CONFIG_SYS_HWINFO_SIZE];
+	unsigned short ih, is, ie, part;
+
+	hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
+	ih = is = ie = 0;
+
+	if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
+		return;
+	}
+
+	part = 1;
+
+	/* copy serial # / MAC address */
+	while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) {
+		if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
+			return;
+		}
+		switch (part) {
+		default:		/* Copy serial # */
+			if (hwi[ih] == ' ') {
+				++part;
+			}
+			serial[is++] = hwi[ih];
+			break;
+		case 3:			/* Copy MAC address */
+			if (hwi[ih] == ' ') {
+				++part;
+				break;
+			}
+			ethaddr[ie++] = hwi[ih];
+			if ((ie % 3) == 2)
+				ethaddr[ie++] = ':';
+			break;
+		}
+		++ih;
+	}
+	serial[is]  = '\0';
+	if (ie && ethaddr[ie-1] == ':')
+		--ie;
+	ethaddr[ie] = '\0';
+
+	/* set serial# and ethaddr if not yet defined */
+	if (getenv("serial#") == NULL) {
+		setenv ((char *)"serial#", (char *)serial);
+	}
+
+	if (getenv("ethaddr") == NULL) {
+		setenv ((char *)"ethaddr", (char *)ethaddr);
+	}
+}
diff --git a/u-boot/board/tqc/tqm8xx/tqm8xx.c b/u-boot/board/tqc/tqm8xx/tqm8xx.c
new file mode 100644
index 0000000..6576e02
--- /dev/null
+++ b/u-boot/board/tqc/tqm8xx/tqm8xx.c
@@ -0,0 +1,742 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <mpc8xx.h>
+#ifdef CONFIG_PS2MULT
+#include <ps2mult.h>
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static long int dram_size (long int, long int *, long int);
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+	0x1FF5FC47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+	0x1FF5FC47, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0xFFFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board: ");
+
+	if (!s || strncmp (s, "TQM8", 4)) {
+		puts ("### No HW ID - assuming TQM8xxL\n");
+		return (0);
+	}
+
+	if ((*(s + 6) == 'L')) {	/* a TQM8xxL type */
+		gd->board_type = 'L';
+	}
+
+	if ((*(s + 6) == 'M')) {	/* a TQM8xxM type */
+		gd->board_type = 'M';
+	}
+
+	if ((*(s + 6) == 'D')) {	/* a TQM885D type */
+		gd->board_type = 'D';
+	}
+
+	for (; *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+#ifdef CONFIG_VIRTLAB2
+	puts (" (Virtlab2)");
+#endif
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9, size10;
+	long int size_b0 = 0;
+	long int size_b1 = 0;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+#ifndef	CONFIG_CAN_DRIVER
+	if ((board_type != 'L') &&
+	    (board_type != 'M') &&
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
+		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+	}
+#endif							/* CONFIG_CAN_DRIVER */
+
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+#ifndef	CONFIG_CAN_DRIVER
+	if ((board_type != 'L') &&
+	    (board_type != 'M') &&
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
+		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
+		udelay (1);
+		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
+		udelay (1);
+	}
+#endif							/* CONFIG_CAN_DRIVER */
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
+
+	udelay(1000);
+
+#if defined(CONFIG_SYS_MAMR_10COL)
+	/*
+	 * try 10 column mode
+	 */
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
+#else
+	size10 = 0;
+#endif /* CONFIG_SYS_MAMR_10COL */
+
+	if ((size8 < size10) && (size9 < size10)) {
+		size_b0 = size10;
+	} else if ((size8 < size9) && (size10 < size9)) {
+		size_b0 = size9;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
+		udelay (500);
+	} else {
+		size_b0 = size8;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+		udelay (500);
+	}
+	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
+
+#ifndef	CONFIG_CAN_DRIVER
+	if ((board_type != 'L') &&
+	    (board_type != 'M') &&
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
+		/*
+		 * Check Bank 1 Memory Size
+		 * use current column settings
+		 * [9 column SDRAM may also be used in 8 column mode,
+		 *  but then only half the real size will be used.]
+		 */
+		size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
+				     SDRAM_MAX_SIZE);
+		debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
+	} else {
+		size_b1 = 0;
+	}
+#endif	/* CONFIG_CAN_DRIVER */
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					   + size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {					/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or3 =
+					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br3 =
+					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					+ size_b0;
+		} else {
+			unsigned long reg;
+
+#ifndef	CONFIG_CAN_DRIVER
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br3 = 0;
+#endif							/* CONFIG_CAN_DRIVER */
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+#ifdef	CONFIG_CAN_DRIVER
+	/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
+
+	/* Initialize OR3 / BR3 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
+
+	/* Initialize MBMR */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+
+	/* Initialize UPMB for CAN: single read */
+	memctl->memc_mdr = 0xFFFFCC04;
+	memctl->memc_mcr = 0x0100 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFD004;
+	memctl->memc_mcr = 0x0101 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFC000;
+	memctl->memc_mcr = 0x0102 | UPMB;
+
+	memctl->memc_mdr = 0x3FFFC004;
+	memctl->memc_mcr = 0x0103 | UPMB;
+
+	memctl->memc_mdr = 0xFFFFDC07;
+	memctl->memc_mcr = 0x0104 | UPMB;
+
+	/* Initialize UPMB for CAN: single write */
+	memctl->memc_mdr = 0xFFFCCC04;
+	memctl->memc_mcr = 0x0118 | UPMB;
+
+	memctl->memc_mdr = 0xCFFCDC04;
+	memctl->memc_mcr = 0x0119 | UPMB;
+
+	memctl->memc_mdr = 0x3FFCC000;
+	memctl->memc_mcr = 0x011A | UPMB;
+
+	memctl->memc_mdr = 0xFFFCC004;
+	memctl->memc_mcr = 0x011B | UPMB;
+
+	memctl->memc_mdr = 0xFFFDC405;
+	memctl->memc_mcr = 0x011C | UPMB;
+#endif							/* CONFIG_CAN_DRIVER */
+
+#ifdef	CONFIG_ISP1362_USB
+	/* Initialize OR5 / BR5 */
+	memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
+	memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
+#endif							/* CONFIG_ISP1362_USB */
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_MISC_INIT_R
+extern void load_sernum_ethaddr(void);
+int misc_init_r (void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	load_sernum_ethaddr();
+
+#ifdef	CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else {
+		trlx = 0;
+	}
+
+	/*
+	 * We assume that each 10MHz of bus clock require 1-clk SCY
+	 * adjustment.
+	 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+	/*
+	 * We need proper rounding here. This is what the "+5" and "-5"
+	 * are here for.
+	 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+	/*
+	 * For bus frequencies above 50MHz, we want to use relaxed timing
+	 * (OR_TRLX).
+	 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+		(CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+
+	memctl->memc_or0 =
+		flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
+#else
+	memctl->memc_or0 =
+		CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
+#endif
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+	       memctl->memc_br0, memctl->memc_or0);
+
+	if (flash_info[1].size) {
+#ifdef	CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+		memctl->memc_or1 = flash_or_timing |
+			(-flash_info[1].size & 0xFFFF8000);
+#else
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
+			(-flash_info[1].size & 0xFFFF8000);
+#endif
+		memctl->memc_br1 =
+			((CONFIG_SYS_FLASH_BASE +
+			  flash_info[0].
+			  size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
+		       memctl->memc_br1, memctl->memc_or1);
+	} else {
+		memctl->memc_br1 = 0;	/* invalidate bank */
+
+		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+		       memctl->memc_br1, memctl->memc_or1);
+	}
+
+# ifdef CONFIG_IDE_LED
+	/* Configure PA15 as output port */
+	immap->im_ioport.iop_padir |= 0x0001;
+	immap->im_ioport.iop_paodr |= 0x0001;
+	immap->im_ioport.iop_papar &= ~0x0001;
+	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
+# endif
+
+#ifdef CONFIG_NSCU
+	/* wake up ethernet module */
+	immap->im_ioport.iop_pcpar &= ~0x0004;	/* GPIO pin      */
+	immap->im_ioport.iop_pcdir |= 0x0004;	/* output        */
+	immap->im_ioport.iop_pcso &= ~0x0004;	/* for clarity   */
+	immap->im_ioport.iop_pcdat |= 0x0004;	/* enable        */
+#endif /* CONFIG_NSCU */
+
+	return (0);
+}
+#endif	/* CONFIG_MISC_INIT_R */
+
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* We have one led for both pcmcia slots */
+	if (status) {				/* led on */
+		immap->im_ioport.iop_padat |= 0x0001;
+	} else {
+		immap->im_ioport.iop_padat &= ~0x0001;
+	}
+}
+# endif
+
+#ifdef CONFIG_LCD_INFO
+#include <lcd.h>
+#include <version.h>
+#include <timestamp.h>
+
+void lcd_show_board_info(void)
+{
+	char temp[32];
+
+	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
+	lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
+	lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
+#ifdef CONFIG_LCD_INFO_BELOW_LOGO
+	lcd_printf ("MPC823 CPU at %s MHz\n",
+		strmhz(temp, gd->cpu_clk));
+	lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
+		gd->ram_size >> 20,
+		gd->bd->bi_flashsize >> 20 );
+#else
+	/* leave one blank line */
+	lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
+		strmhz(temp, gd->cpu_clk),
+		gd->ram_size >> 20,
+		gd->bd->bi_flashsize >> 20 );
+#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
+}
+#endif /* CONFIG_LCD_INFO */
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int fdt_set_node_and_value (void *blob,
+				char *nodename,
+				char *regname,
+				void *var,
+				int size)
+{
+	int ret = 0;
+	int nodeoffset = 0;
+
+	nodeoffset = fdt_path_offset (blob, nodename);
+	if (nodeoffset >= 0) {
+		ret = fdt_setprop (blob, nodeoffset, regname, var,
+					size);
+		if (ret < 0) {
+			printf("ft_blob_update(): "
+				"cannot set %s/%s property; err: %s\n",
+				nodename, regname, fdt_strerror (ret));
+		}
+	} else {
+		printf("ft_blob_update(): "
+			"cannot find %s node err:%s\n",
+			nodename, fdt_strerror (nodeoffset));
+	}
+	return ret;
+}
+
+int fdt_del_node_name (void *blob, char *nodename)
+{
+	int ret = 0;
+	int nodeoffset = 0;
+
+	nodeoffset = fdt_path_offset (blob, nodename);
+	if (nodeoffset >= 0) {
+		ret = fdt_del_node (blob, nodeoffset);
+		if (ret < 0) {
+			printf("%s: cannot delete %s; err: %s\n",
+				__func__, nodename, fdt_strerror (ret));
+		}
+	} else {
+		printf("%s: cannot find %s node err:%s\n",
+			__func__, nodename, fdt_strerror (nodeoffset));
+	}
+	return ret;
+}
+
+int fdt_del_prop_name (void *blob, char *nodename, char *propname)
+{
+	int ret = 0;
+	int nodeoffset = 0;
+
+	nodeoffset = fdt_path_offset (blob, nodename);
+	if (nodeoffset >= 0) {
+		ret = fdt_delprop (blob, nodeoffset, propname);
+		if (ret < 0) {
+			printf("%s: cannot delete %s %s; err: %s\n",
+				__func__, nodename, propname,
+				fdt_strerror (ret));
+		}
+	} else {
+		printf("%s: cannot find %s node err:%s\n",
+			__func__, nodename, fdt_strerror (nodeoffset));
+	}
+	return ret;
+}
+
+/*
+ * update "brg" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+	uchar enetaddr[6];
+	ulong brg_data = 0;
+
+	/* BRG */
+	brg_data = cpu_to_be32(bd->bi_busfreq);
+	fdt_set_node_and_value(blob,
+				"/soc/cpm", "brg-frequency",
+				&brg_data, sizeof(brg_data));
+
+	/* MAC addr */
+	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		fdt_set_node_and_value(blob,
+					"ethernet0", "local-mac-address",
+					enetaddr, sizeof(u8) * 6);
+	}
+
+	if (hwconfig_arg_cmp("fec", "off")) {
+		/* no FEC on this plattform, delete DTS nodes */
+		fdt_del_node_name (blob, "ethernet1");
+		fdt_del_node_name (blob, "mdio1");
+		/* also the aliases entries */
+		fdt_del_prop_name (blob, "/aliases", "ethernet1");
+		fdt_del_prop_name (blob, "/aliases", "mdio1");
+	} else {
+		/* adjust local-mac-address for FEC ethernet */
+		if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
+			fdt_set_node_and_value(blob,
+					"ethernet1", "local-mac-address",
+					enetaddr, sizeof(u8) * 6);
+		}
+	}
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+/* ---------------------------------------------------------------------------- */
+/* TK885D specific initializaion						*/
+/* ---------------------------------------------------------------------------- */
+#ifdef CONFIG_TK885D
+#include <miiphy.h>
+int last_stage_init(void)
+{
+	const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
+	unsigned short reg;
+	int ret, i = 100;
+	char *s;
+
+	mii_init();
+	/* Without this delay 0xff is read from the UART buffer later in
+	 * abortboot() and autoboot is aborted */
+	udelay(10000);
+	while (tstc() && i--)
+		(void)getc();
+
+	/* Check if auto-negotiation is prohibited */
+	s = getenv("phy_auto_nego");
+
+	if (!s || !strcmp(s, "on"))
+		/* Nothing to do - autonegotiation by default */
+		return 0;
+
+	for (i = 0; i < 2; i++) {
+		ret = miiphy_read("FEC", phy[i], MII_BMCR, &reg);
+		if (ret) {
+			printf("Cannot read BMCR on PHY %d\n", phy[i]);
+			return 0;
+		}
+		/* Auto-negotiation off, hard set full duplex, 100Mbps */
+		ret = miiphy_write("FEC", phy[i],
+				   MII_BMCR, (reg | BMCR_SPEED100 |
+					      BMCR_FULLDPLX) & ~BMCR_ANENABLE);
+		if (ret) {
+			printf("Cannot write BMCR on PHY %d\n", phy[i]);
+			return 0;
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/u-boot/board/tqc/tqm8xx/u-boot.lds b/u-boot/board/tqc/tqm8xx/u-boot.lds
new file mode 100644
index 0000000..209d1e0
--- /dev/null
+++ b/u-boot/board/tqc/tqm8xx/u-boot.lds
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+    arch/powerpc/lib/libpowerpc.o	(.text*)
+    board/tqc/tqm8xx/libtqm8xx.o	(.text*)
+    disk/libdisk.o			(.text*)
+    drivers/net/libnet.o		(.text*)
+    drivers/pcmcia/libpcmcia.o		(.text*)
+    drivers/rtc/librtc.o		(.text*)
+    drivers/misc/libmisc.o		(.text*)
+    *(.text.print_buffer)
+    *(.text.print_size)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.ppcenv*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/tqc/tqm8xx/u-boot.lds.debug b/u-boot/board/tqc/tqm8xx/u-boot.lds.debug
new file mode 100644
index 0000000..c218905
--- /dev/null
+++ b/u-boot/board/tqc/tqm8xx/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/trab/Makefile b/u-boot/board/trab/Makefile
new file mode 100644
index 0000000..82da40c
--- /dev/null
+++ b/u-boot/board/trab/Makefile
@@ -0,0 +1,71 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
+SOBJS	:= lowlevel_init.o
+
+COBJS_FKT := trab_fkt.o rs485.o tsc2000.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS_FKT:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT))
+
+LOAD_ADDR = 0xc100000
+
+#########################################################################
+
+all:	$(LIB) $(obj)trab_fkt.srec $(obj)trab_fkt.bin
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+$(obj)trab_fkt.srec:	$(OBJS_FKT) $(LIB)
+	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
+		-L$(obj)../../examples/standalone -lstubs \
+		-L$(obj)../../lib -lgeneric \
+		$(PLATFORM_LIBS)
+	$(OBJCOPY) -O srec $(<:.o=) $@
+
+$(obj)trab_fkt.bin:	$(obj)trab_fkt.srec
+	$(OBJCOPY) -I srec -O binary $< $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS) $(OBJS_FKT)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/trab/Pt1000_temp_data.h b/u-boot/board/trab/Pt1000_temp_data.h
new file mode 100644
index 0000000..17e9ed7
--- /dev/null
+++ b/u-boot/board/trab/Pt1000_temp_data.h
@@ -0,0 +1,71 @@
+/*
+ * Data file for tsc2000 driver.
+ * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ */
+
+#ifndef _PT1000_TEMP_DATA_H
+#define _PT1000_TEMP_DATA_H
+
+long Pt1000_temp_table[][2] = {
+	/* For quick range checking the largest element
+	 * is placed at index 0.
+	 * U, nV    T, C*100
+	 */
+	{ 44000000 , 12165 },
+	{ -10000000 , -2644 },
+	{ -9000000 , -2381 },
+	{ -8000000 , -2118 },
+	{ -7000000 , -1855 },
+	{ -6000000 , -1591 },
+	{ -5000000 , -1327 },
+	{ -4000000 , -1063 },
+	{ -3000000 , -798 },
+	{ -2000000 , -532 },
+	{ -1000000 , -266 },
+	{ 0 , 000 },
+	{ 1000000 , 267 },
+	{ 2000000 , 534 },
+	{ 3000000 , 802 },
+	{ 4000000 , 1070 },
+	{ 5000000 , 1338 },
+	{ 6000000 , 1607 },
+	{ 7000000 , 1876 },
+	{ 8000000 , 2146 },
+	{ 9000000 , 2416 },
+	{ 10000000 , 2687 },
+	{ 11000000 , 2958 },
+	{ 12000000 , 3230 },
+	{ 13000000 , 3502 },
+	{ 14000000 , 3774 },
+	{ 15000000 , 4047 },
+	{ 16000000 , 4321 },
+	{ 17000000 , 4595 },
+	{ 18000000 , 4869 },
+	{ 19000000 , 5144 },
+	{ 20000000 , 5419 },
+	{ 21000000 , 5694 },
+	{ 22000000 , 5971 },
+	{ 23000000 , 6247 },
+	{ 24000000 , 6524 },
+	{ 25000000 , 6802 },
+	{ 26000000 , 7080 },
+	{ 27000000 , 7358 },
+	{ 28000000 , 7637 },
+	{ 29000000 , 7916 },
+	{ 30000000 , 8196 },
+	{ 31000000 , 8476 },
+	{ 32000000 , 8757 },
+	{ 33000000 , 9039 },
+	{ 34000000 , 9320 },
+	{ 35000000 , 9602 },
+	{ 36000000 , 9885 },
+	{ 37000000 , 10168 },
+	{ 38000000 , 10452 },
+	{ 39000000 , 10736 },
+	{ 40000000 , 11021 },
+	{ 41000000 , 11306 },
+	{ 42000000 , 11592 },
+	{ 43000000 , 11879 },
+	{ 44000000 , 12165 },
+};
+#endif /* _PT1000_TEMP_DATA_H */
diff --git a/u-boot/board/trab/README.kbd b/u-boot/board/trab/README.kbd
new file mode 100644
index 0000000..3db00bc
--- /dev/null
+++ b/u-boot/board/trab/README.kbd
@@ -0,0 +1,44 @@
+
+The TRAB keyboard implementation is similar to that for LWMON and
+R360MPI boards. The only difference concerns key naming. There are 4
+keys on TRAB: 1, 2, 3, 4.
+
+1) The "kbd" command provides information about the current state of
+   the keys. For example,
+
+	TRAB # kbd
+	Keys: 1 0 1 0
+
+   means that keys 1 and 3 are pressed. The keyboard status is also
+   stored in the "keybd" environment variable. In this example we get
+
+	keybd=1010
+
+2) The "preboot" variable is set according to current environment
+   settings and keys pressed. This is an example:
+
+	TRAB # setenv magic_keys XY
+	TRAB # setenv key_magicX 12
+	TRAB # setenv key_cmdX echo ## Keys 1 + 2 pressed ##\;echo
+	TRAB # setenv key_magicY 13
+	TRAB # setenv key_cmdY echo ## Keys 1 + 3 pressed ##\;echo
+
+   Here "magic_keys=XY" means that the "key_magicX" and "key_magicY"
+   variables will be checked for a match. Each variable "key_magic*"
+   defines a set of keys. In the our example, if keys 1 and 3 are
+   pressed during reset, then "key_magicY" matches, so the "preboot"
+   variable will be set to the contents of "key_cmdY":
+
+	preboot=echo ## Keys 1 + 3 pressed ##;echo
+
+3) The TRAB board has optional modem support. When a certain key
+   combination is pressed on the keyboard at power-on, the firmware
+   performs the necessary initialization of the modem and allows for
+   dial-in. The key combination is specified in the
+   "include/configs/trab.h" file. For example:
+
+	#define        CONFIG_MODEM_KEY_MAGIC  "23"
+
+   means that modem will be initialized if and only if both keys 2, 3
+   are pressed. Note that the format of this string is similar to the
+   format of "key_magic*" environment variables described above.
diff --git a/u-boot/board/trab/auto_update.c b/u-boot/board/trab/auto_update.c
new file mode 100644
index 0000000..bcb8505
--- /dev/null
+++ b/u-boot/board/trab/auto_update.c
@@ -0,0 +1,676 @@
+/*
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+#include <hush.h>
+#endif
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI_NEW
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CONFIG_SYS_HUSH_PARSER
+#error "must define CONFIG_SYS_HUSH_PARSER"
+#endif
+
+#if !defined(CONFIG_CMD_FAT)
+#error "must define CONFIG_CMD_FAT"
+#endif
+
+/*
+ * Check whether a USB memory stick is plugged in.
+ * If one is found:
+ *	1) if prepare.img ist found load it into memory. If it is
+ *		valid then run it.
+ *	2) if preinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ *	3) if firmw_01.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	4) if kernl_01.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	5) if app.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	6) if disk.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	7) if postinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ */
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_PREPARE	"prepare.img"
+#define AU_PREINST	"preinst.img"
+#define AU_FIRMWARE	"firmw_01.img"
+#define AU_KERNEL	"kernl_01.img"
+#define AU_APP		"app.img"
+#define AU_DISK		"disk.img"
+#define AU_POSTINST	"postinst.img"
+
+struct flash_layout
+{
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#ifndef CONFIG_FLASH_8MB			/* 16 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0009FFFF
+#define AU_FL_VFD_ST		0x000A0000
+#define AU_FL_VFD_ND		0x000BFFFF
+#define AU_FL_KERNEL_ST		0x000C0000
+#define AU_FL_KERNEL_ND		0x001BFFFF
+#define AU_FL_APP_ST		0x001C0000
+#define AU_FL_APP_ND		0x005BFFFF
+#define AU_FL_DISK_ST		0x005C0000
+#define AU_FL_DISK_ND		0x00FFFFFF
+#else						/*  8 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0005FFFF
+#define AU_FL_KERNEL_ST		0x00060000
+#define AU_FL_KERNEL_ND		0x0013FFFF
+#define AU_FL_APP_ST		0x00140000
+#define AU_FL_APP_ND		0x0067FFFF
+#define AU_FL_DISK_ST		0x00680000
+#define AU_FL_DISK_ND		0x007DFFFF
+#define AU_FL_VFD_ST		0x007E0000
+#define AU_FL_VFD_ND		0x007FFFFF
+#endif	/* CONFIG_FLASH_8MB */
+
+/* a structure with the offsets to values in the EEPROM */
+struct eeprom_layout
+{
+	int time;
+	int size;
+	int dcrc;
+};
+
+/* layout of the EEPROM - offset from the start. All entries are 32 bit. */
+#define AU_EEPROM_TIME_PREINST	64
+#define AU_EEPROM_SIZE_PREINST	68
+#define AU_EEPROM_DCRC_PREINST	72
+#define AU_EEPROM_TIME_FIRMWARE	76
+#define AU_EEPROM_SIZE_FIRMWARE	80
+#define AU_EEPROM_DCRC_FIRMWARE	84
+#define AU_EEPROM_TIME_KERNEL	88
+#define AU_EEPROM_SIZE_KERNEL	92
+#define AU_EEPROM_DCRC_KERNEL	96
+#define AU_EEPROM_TIME_APP	100
+#define AU_EEPROM_SIZE_APP	104
+#define AU_EEPROM_DCRC_APP	108
+#define AU_EEPROM_TIME_DISK	112
+#define AU_EEPROM_SIZE_DISK	116
+#define AU_EEPROM_DCRC_DISK	120
+#define AU_EEPROM_TIME_POSTINST 124
+#define AU_EEPROM_SIZE_POSTINST 128
+#define AU_EEPROM_DCRC_POSTINST 132
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_PREPARE	0
+#define IDX_PREINST	1
+#define IDX_FIRMWARE	2
+#define IDX_KERNEL	3
+#define IDX_APP		4
+#define IDX_DISK	5
+#define IDX_POSTINST	6
+/* max. number of files which could interest us */
+#define AU_MAXFILES 7
+/* pointers to file names */
+char *aufile[AU_MAXFILES];
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES];
+/* offsets into the EEEPROM */
+struct eeprom_layout auee_off[AU_MAXFILES] = { \
+	{0}, \
+	{AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \
+	{AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \
+	{AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \
+	{AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \
+	{AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \
+	{AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \
+	};
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \
+	{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
+	{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
+	{AU_FL_APP_ST, AU_FL_APP_ND,}, \
+	{AU_FL_DISK_ST, AU_FL_DISK_ND,}, \
+};
+/* convert the index into aufile[] to an index into aufl_layout[] */
+#define FIDX_TO_LIDX(idx) ((idx) - 2)
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x0C100000)
+/* the app is the largest image */
+#define MAX_LOADSZ ausize[IDX_APP]
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+#ifdef CONFIG_VFD
+extern int trab_vfd (ulong);
+extern int transfer_pic(unsigned char, unsigned char *, int, int);
+#endif
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+/* change char* to void* to shutup the compiler */
+extern int i2c_write_multiple (uchar, uint, int, void *, int);
+extern int i2c_read_multiple (uchar, uint, int, void *, int);
+extern int u_boot_hush_start(void);
+
+int
+au_check_cksum_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	if (nbytes != image_get_image_size (hdr)) {
+		printf ("Image %s bad total SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the data CRC */
+	if (!image_check_dcrc (hdr)) {
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int
+au_check_header_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+	unsigned char buf[4];
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC);
+	printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM);
+	printf("size %#x %#lx ", image_get_data_size (hdr), nbytes);
+	printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL);
+#endif
+	if (nbytes < image_get_header_size ()) {
+		printf ("Image %s bad header SIZE\n", aufile[idx]);
+		return -1;
+	}
+	if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_ARM)) {
+		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the hdr CRC */
+	if (!image_check_hcrc (hdr)) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		return -1;
+	}
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) &&
+		!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_DISK) && !image_check_type (hdr, IH_TYPE_FILESYSTEM)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_APP) && !image_check_type (hdr, IH_TYPE_RAMDISK)
+		&& !image_check_type (hdr, IH_TYPE_FILESYSTEM)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST)
+		&& !image_check_type (hdr, IH_TYPE_SCRIPT)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	/* special case for prepare.img */
+	if (idx == IDX_PREPARE)
+		return 0;
+	/* recycle checksum */
+	checksum = image_get_data_size (hdr);
+	/* for kernel and app the image header must also fit into flash */
+	if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE))
+		checksum += image_get_header_size ();
+	/* check the size does not exceed space in flash. HUSH scripts */
+	/* all have ausize[] set to 0 */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the time stamp from the EEPROM */
+	/* read it in */
+	i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf));
+#ifdef CHECK_VALID_DEBUG
+	printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x "
+		"as int %#x time %#x\n",
+		buf[0], buf[1], buf[2], buf[3],
+		*((unsigned int *)buf), image_get_time (hdr));
+#endif
+	/* check it */
+	if (*((unsigned int *)buf) >= image_get_time (hdr)) {
+		printf ("Image %s is too old\n", aufile[idx]);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* power control defines */
+#define CPLD_VFD_BK ((volatile char *)0x04038002)
+#define POWER_OFF (1 << 1)
+
+int
+au_do_update(int idx, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* disable the power switch */
+	*CPLD_VFD_BK |= POWER_OFF;
+
+	/* execute a script */
+	if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
+		addr = (char *)((char *)hdr + image_get_header_size ());
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[image_get_data_size (hdr)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		return 0;
+	}
+
+	start = aufl_layout[FIDX_TO_LIDX(idx)].start;
+	end = aufl_layout[FIDX_TO_LIDX(idx)].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		flash_sect_protect(0, start, end);
+	}
+
+	/*
+	 * erase the address range.
+	 */
+	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+	flash_sect_erase(start, end);
+	wait_ms(100);
+	/* strip the header - except for the kernel and ramdisk */
+	if (image_check_type (hdr, IH_TYPE_KERNEL) ||
+			image_check_type (hdr, IH_TYPE_RAMDISK)) {
+		addr = (char *)hdr;
+		off = image_get_header_size ();
+		nbytes = image_get_image_size (hdr);
+	} else {
+		addr = (char *)((char *)hdr + image_get_header_size ());
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = image_get_data_size (hdr);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+	rc = flash_write(addr, start, nbytes);
+	if (rc != 0) {
+		printf("Flashing failed due to error %d\n", rc);
+		return -1;
+	}
+
+	/* check the dcrc of the copy */
+	if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) !=
+	    image_get_dcrc (hdr)) {
+		printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE)
+		flash_sect_protect(1, start, end);
+	return 0;
+}
+
+int
+au_update_eeprom(int idx)
+{
+	image_header_t *hdr;
+	int off;
+	uint32_t val;
+
+	/* special case for prepare.img */
+	if (idx == IDX_PREPARE) {
+		/* enable the power switch */
+		*CPLD_VFD_BK &= ~POWER_OFF;
+		return 0;
+	}
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* write the time field into EEPROM */
+	off = auee_off[idx].time;
+	val = image_get_time (hdr);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the size field into EEPROM */
+	off = auee_off[idx].size;
+	val = image_get_data_size (hdr);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the dcrc field into EEPROM */
+	off = auee_off[idx].dcrc;
+	val = image_get_dcrc (hdr);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* enable the power switch */
+	*CPLD_VFD_BK &= ~POWER_OFF;
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int
+do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+
+#undef ERASE_EEPROM
+#ifdef ERASE_EEPROM
+	int arr[18];
+	memset(arr, 0, sizeof(arr));
+	i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr));
+#endif
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(0);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		res = -1;
+		goto xit;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		res = -1;
+		goto xit;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		res = -1;
+		goto xit;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/* initialize the array of file names */
+	memset(aufile, 0, sizeof(aufile));
+	aufile[IDX_PREPARE] = AU_PREPARE;
+	aufile[IDX_PREINST] = AU_PREINST;
+	aufile[IDX_FIRMWARE] = AU_FIRMWARE;
+	aufile[IDX_KERNEL] = AU_KERNEL;
+	aufile[IDX_APP] = AU_APP;
+	aufile[IDX_DISK] = AU_DISK;
+	aufile[IDX_POSTINST] = AU_POSTINST;
+	/* initialize the array of flash sizes */
+	memset(ausize, 0, sizeof(ausize));
+	ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
+	ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
+	ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST;
+	ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST;
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = -1;
+	end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+		aufl_layout[0].start = start;
+		aufl_layout[0].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_KERNEL] = (end + 1) - start;
+		aufl_layout[1].start = start;
+		aufl_layout[1].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("app_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("app_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_APP] = (end + 1) - start;
+		aufl_layout[2].start = start;
+		aufl_layout[2].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("disk_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("disk_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_DISK] = (end + 1) - start;
+		aufl_layout[3].start = start;
+		aufl_layout[3].end = end;
+	}
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		/* just read the header */
+		sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ());
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, image_get_header_size ());
+		if (sz <= 0 || sz < image_get_header_size ()) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_header_valid(i, sz) < 0) {
+			debug ("%s header not valid\n", aufile[i]);
+			continue;
+		}
+		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, image_get_header_size ());
+		if (sz <= 0 || sz <= image_get_header_size ()) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			debug ("%s checksum not valid\n", aufile[i]);
+			continue;
+		}
+#ifdef CONFIG_VFD
+		/* now that we have a valid file we can display the */
+		/* bitmap. */
+		if (bitmap_first == 0) {
+			env = getenv("bitmap2");
+			if (env == NULL) {
+				trab_vfd(0);
+			} else {
+				/* not so simple - bitmap2 is supposed to */
+				/* contain the address of the bitmap */
+				env = (char *)simple_strtoul(env, NULL, 16);
+/* NOTE: these are taken from vfd_logo.h. If that file changes then */
+/* these defines MUST also be updated! These may be wrong for bitmap2. */
+#define VFD_LOGO_WIDTH 112
+#define VFD_LOGO_HEIGHT 72
+				/* must call transfer_pic directly */
+				transfer_pic(3, (unsigned char *)env,
+					     VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
+			}
+			bitmap_first = 1;
+		}
+#endif
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < 3);
+		if (cnt < 3)
+#else
+		} while (res < 0);
+#endif
+		/*
+		 * it doesn't make sense to update the EEPROM if the
+		 * update was interrupted by the user due to errors.
+		 */
+		if (got_ctrlc == 0)
+			au_update_eeprom(i);
+		else
+			/* enable the power switch */
+			*CPLD_VFD_BK &= ~POWER_OFF;
+	}
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+xit:
+	usb_stop();
+	return res;
+}
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/u-boot/board/trab/cmd_trab.c b/u-boot/board/trab/cmd_trab.c
new file mode 100644
index 0000000..dec3c61
--- /dev/null
+++ b/u-boot/board/trab/cmd_trab.c
@@ -0,0 +1,879 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include <rtc.h>
+
+/*
+ * TRAB board specific commands. Especially commands for burn-in and function
+ * test.
+ */
+#if defined(CONFIG_CMD_BSP)
+
+/* limits for valid range of VCC5V in mV  */
+#define VCC5V_MIN       4500
+#define VCC5V_MAX       5500
+
+/*
+ * Test strings for EEPROM test. Length of string 2 must not exceed length of
+ * string 1. Otherwise a buffer overrun could occur!
+ */
+#define EEPROM_TEST_STRING_1    "0987654321 :tset a si siht"
+#define EEPROM_TEST_STRING_2    "this is a test: 1234567890"
+
+/*
+ * min/max limits for valid contact temperature during burn in test (in
+ * degree Centigrade * 100)
+ */
+#define MIN_CONTACT_TEMP        -1000
+#define MAX_CONTACT_TEMP        +9000
+
+/* blinking frequency of status LED */
+#define LED_BLINK_FREQ          5
+
+/* delay time between burn in cycles in seconds */
+#ifndef BURN_IN_CYCLE_DELAY     /* if not defined in include/configs/trab.h */
+#define BURN_IN_CYCLE_DELAY     5
+#endif
+
+/* physical SRAM parameters */
+#define SRAM_ADDR       0x02000000 /* GCS1 */
+#define SRAM_SIZE       0x40000 /* 256 kByte */
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
+#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
+#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+/* I2C EEPROM device address */
+#define I2C_EEPROM_DEV_ADDR     0x54
+
+/* EEPROM address map */
+#define EE_ADDR_TEST                    192
+#define EE_ADDR_MAX_CYCLES              256
+#define EE_ADDR_STATUS                  258
+#define EE_ADDR_PASS_CYCLES             259
+#define EE_ADDR_FIRST_ERROR_CYCLE       261
+#define EE_ADDR_FIRST_ERROR_NUM         263
+#define EE_ADDR_FIRST_ERROR_NAME        264
+#define EE_ADDR_ACT_CYCLE               280
+
+/* Bit definitions for ADCCON */
+#define ADC_ENABLE_START     0x1
+#define ADC_READ_START       0x2
+#define ADC_STDBM            0x4
+#define ADC_INP_AIN0         (0x0 << 3)
+#define ADC_INP_AIN1         (0x1 << 3)
+#define ADC_INP_AIN2         (0x2 << 3)
+#define ADC_INP_AIN3         (0x3 << 3)
+#define ADC_INP_AIN4         (0x4 << 3)
+#define ADC_INP_AIN5         (0x5 << 3)
+#define ADC_INP_AIN6         (0x6 << 3)
+#define ADC_INP_AIN7         (0x7 << 3)
+#define ADC_PRSCEN           0x4000
+#define ADC_ECFLG            0x800
+
+/* misc */
+
+/* externals */
+extern int memory_post_tests (unsigned long start, unsigned long size);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+extern int i2c_read (uchar, uint, int , uchar* , int);
+extern void tsc2000_reg_init (void);
+extern s32 tsc2000_contact_temp (void);
+extern void tsc2000_spi_init(void);
+
+/* function declarations */
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+int i2c_read_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/* helper functions */
+static void adc_init (void);
+static int adc_read (unsigned int channel);
+static int read_dip (void);
+static int read_vcc5v (void);
+static int test_dip (void);
+static int test_vcc5v (void);
+static int test_rotary_switch (void);
+static int test_sram (void);
+static int test_eeprom (void);
+static int test_contact_temp (void);
+static void led_set (unsigned int);
+static void led_blink (void);
+static void led_init (void);
+static void sdelay (unsigned long seconds); /* delay in seconds */
+static int dummy (void);
+static int read_max_cycles(void);
+static void test_function_table_init (void);
+static void global_vars_init (void);
+static int global_vars_write_to_eeprom (void);
+
+/* globals */
+u16 max_cycles;
+u8 status;
+u16 pass_cycles;
+u16 first_error_cycle;
+u8 first_error_num;
+char first_error_name[16];
+u16 act_cycle;
+
+typedef struct test_function_s {
+	char *name;
+	int (*pf)(void);
+} test_function_t;
+
+/* max number of Burn In Functions */
+#define BIF_MAX 6
+
+/* table with burn in functions */
+test_function_t test_function[BIF_MAX];
+
+
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	int cycle_status;
+
+	if (argc > 1)
+		return cmd_usage(cmdtp);
+
+	led_init ();
+	global_vars_init ();
+	test_function_table_init ();
+	tsc2000_spi_init ();
+
+	if (global_vars_write_to_eeprom () != 0) {
+		printf ("%s: error writing global_vars to eeprom\n",
+			__FUNCTION__);
+		return (1);
+	}
+
+	if (read_max_cycles () != 0) {
+		printf ("%s: error reading max_cycles from eeprom\n",
+			__FUNCTION__);
+		return (1);
+	}
+
+	if (max_cycles == 0) {
+		printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__);
+		return (1);
+	}
+
+	status = 0;
+	for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) {
+
+		cycle_status = 0;
+
+		/*
+		 * avoid timestamp overflow problem after about 68 minutes of
+		 * udelay() time.
+		 */
+		reset_timer_masked ();
+		for (i = 0; i < BIF_MAX; i++) {
+
+			/* call test function */
+			if ((*test_function[i].pf)() != 0) {
+				printf ("error in %s test\n",
+					test_function[i].name);
+
+				/* is it the first error? */
+				if (status == 0) {
+					status = 1;
+					first_error_cycle = act_cycle;
+
+					/* do not use error_num 0 */
+					first_error_num = i+1;
+					strncpy (first_error_name,
+						 test_function[i].name,
+						 sizeof (first_error_name));
+					led_set (0);
+				}
+				cycle_status = 1;
+			}
+		}
+		/* were all tests of actual cycle OK? */
+		if (cycle_status == 0)
+			pass_cycles++;
+
+		/* set status LED if no error is occoured since yet */
+		if (status == 0)
+			led_set (1);
+
+		printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle);
+
+		/* pause between cycles */
+		sdelay (BURN_IN_CYCLE_DELAY);
+	}
+
+	if (global_vars_write_to_eeprom () != 0) {
+		led_set (0);
+		printf ("%s: error writing global_vars to eeprom\n",
+			__FUNCTION__);
+		status = 1;
+	}
+
+	if (status == 0) {
+		led_blink ();   /* endless loop!! */
+		return (0);
+	} else {
+		led_set (0);
+		return (1);
+	}
+}
+
+U_BOOT_CMD(
+	burn_in,	1,	1,	do_burn_in,
+	"start burn-in test application on TRAB",
+	"\n"
+	"    -  start burn-in test application\n"
+	"       The burn-in test could took a while to finish!\n"
+	"       The content of the onboard EEPROM is modified!"
+);
+
+
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i, dip;
+
+	if (argc > 1)
+		return cmd_usage(cmdtp);
+
+	if ((dip = read_dip ()) == -1)
+		return 1;
+
+	for (i = 0; i < 4; i++) {
+		if ((dip & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	dip,	1,	1,	do_dip,
+	"read dip switch on TRAB",
+	"\n"
+	"    - read state of dip switch (S1) on TRAB board\n"
+	"      read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\""
+);
+
+
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int vcc5v;
+
+	if (argc > 1)
+		return cmd_usage(cmdtp);
+
+	if ((vcc5v = read_vcc5v ()) == -1)
+		return (1);
+
+	printf ("%d", (vcc5v / 1000));
+	printf (".%d", (vcc5v % 1000) / 100);
+	printf ("%d V\n", (vcc5v % 100) / 10) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	vcc5v,	1,	1,	do_vcc5v,
+	"read VCC5V on TRAB",
+	"\n"
+	"    - read actual value of voltage VCC5V"
+);
+
+
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int contact_temp;
+
+	if (argc > 1)
+		return cmd_usage(cmdtp);
+
+	tsc2000_spi_init ();
+
+	contact_temp = tsc2000_contact_temp();
+	printf ("%d degree C * 100\n", contact_temp) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	c_temp,	1,	1,	do_contact_temp,
+	"read contact temperature on TRAB",
+	""
+	"    -  reads the onboard temperature (=contact temperature)\n"
+);
+
+
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc > 1)
+		return cmd_usage(cmdtp);
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+				(unsigned char*) &status, 1))
+		return (1);
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+				(unsigned char*) &pass_cycles, 2))
+		return (1);
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+				1, (unsigned char*) &first_error_cycle, 2))
+		return (1);
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+				1, (unsigned char*) &first_error_num, 1))
+		return (1);
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+			       1, (unsigned char*)first_error_name,
+			       sizeof (first_error_name)))
+		return (1);
+
+	if (read_max_cycles () != 0)
+		return (1);
+
+	printf ("max_cycles = %d\n", max_cycles);
+	printf ("status = %d\n", status);
+	printf ("pass_cycles = %d\n", pass_cycles);
+	printf ("first_error_cycle = %d\n", first_error_cycle);
+	printf ("first_error_num = %d\n", first_error_num);
+	printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name),
+		first_error_name);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bis,	1,	1,	do_burn_in_status,
+	"print burn in status on TRAB",
+	"\n"
+	"    -  prints the status variables of the last burn in test\n"
+	"       stored in the onboard EEPROM on TRAB board"
+);
+
+static int read_dip (void)
+{
+	unsigned int result = 0;
+	int adc_val;
+	int i;
+
+	/***********************************************************
+	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
+	   SW1 - AIN4
+	   SW2 - AIN5
+	   SW3 - AIN6
+	   SW4 - AIN7
+
+	   "On" DIP switch position short-circuits the voltage from
+	   the input channel (i.e. '0' conversion result means "on").
+	*************************************************************/
+
+	for (i = 7; i > 3; i--) {
+
+		if ((adc_val = adc_read (i)) == -1) {
+			printf ("%s: Channel %d could not be read\n",
+				 __FUNCTION__, i);
+			return (-1);
+		}
+
+		/*
+		 * Input voltage (switch open) is 1.8 V.
+		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
+		 * Set trigger at halve that value.
+		 */
+		if (adc_val < 368)
+			result |= (1 << (i-4));
+	}
+	return (result);
+}
+
+
+static int read_vcc5v (void)
+{
+	s32 result;
+
+	/* VCC5V is connected to channel 2 */
+
+	if ((result = adc_read (2)) == -1) {
+		printf ("%s: VCC5V could not be read\n", __FUNCTION__);
+		return (-1);
+	}
+	/*
+	 * Calculate voltage value. Split in two parts because there is no
+	 * floating point support.  VCC5V is connected over an resistor divider:
+	 * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
+	 */
+	result = result * 10 * 1000 / 1023; /* result in mV */
+
+	return (result);
+}
+
+
+static int test_dip (void)
+{
+	static int first_run = 1;
+	static int first_dip;
+
+	if (first_run) {
+		if ((first_dip = read_dip ()) == -1) {
+			return (1);
+		}
+		first_run = 0;
+		debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip);
+	}
+	if (first_dip != read_dip ()) {
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+
+static int test_vcc5v (void)
+{
+	int vcc5v;
+
+	if ((vcc5v = read_vcc5v ()) == -1) {
+		return (1);
+	}
+
+	if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) {
+		printf ("%s: vcc5v[V/100]=%d\n", __FUNCTION__, vcc5v);
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+
+static int test_rotary_switch (void)
+{
+	static int first_run = 1;
+	static int first_rs;
+
+	if (first_run) {
+		/*
+		 * clear bits in CPLD, because they have random values after
+		 * power-up or reset.
+		 */
+		*CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17);
+
+		first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7);
+		first_run = 0;
+		debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs);
+	}
+
+	if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) {
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+
+static int test_sram (void)
+{
+	return (memory_post_tests (SRAM_ADDR, SRAM_SIZE));
+}
+
+
+static int test_eeprom (void)
+{
+	unsigned char temp[sizeof (EEPROM_TEST_STRING_1)];
+	int result = 0;
+
+	/* write test string 1, read back and verify */
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+				(unsigned char*)EEPROM_TEST_STRING_1,
+				sizeof (EEPROM_TEST_STRING_1))) {
+		return (1);
+	}
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+			       temp, sizeof (EEPROM_TEST_STRING_1))) {
+		return (1);
+	}
+
+	if (strcmp ((char *)temp, EEPROM_TEST_STRING_1) != 0) {
+		result = 1;
+		printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp);
+	}
+
+	/* write test string 2, read back and verify */
+	if (result == 0) {
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+					(unsigned char*)EEPROM_TEST_STRING_2,
+					sizeof (EEPROM_TEST_STRING_2))) {
+			return (1);
+		}
+
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+				       temp, sizeof (EEPROM_TEST_STRING_2))) {
+			return (1);
+		}
+
+		if (strcmp ((char *)temp, EEPROM_TEST_STRING_2) != 0) {
+			result = 1;
+			printf ("%s: error; read str = \"%s\"\n",
+				__FUNCTION__, temp);
+		}
+	}
+	return (result);
+}
+
+
+static int test_contact_temp (void)
+{
+	int contact_temp;
+
+	contact_temp = tsc2000_contact_temp ();
+
+	if ((contact_temp < MIN_CONTACT_TEMP)
+	    || (contact_temp > MAX_CONTACT_TEMP))
+		return (1);
+	else
+		return (0);
+}
+
+
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not write to i2c device %d"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+#if 0
+		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+			"%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
+			alen, buffer, i, buffer+i, buffer+i);
+#endif
+
+		udelay (30000);
+	}
+	return (0);
+}
+
+
+int i2c_read_multiple ( uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not read from i2c device %#x"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+	}
+	return (0);
+}
+
+
+static int adc_read (unsigned int channel)
+{
+	int j = 1000; /* timeout value for wait loop in us */
+	int result;
+	struct s3c2400_adc *padc;
+
+	padc = s3c2400_get_base_adc();
+	channel &= 0x7;
+
+	adc_init ();
+
+	padc->adccon &= ~ADC_STDBM; /* select normal mode */
+	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
+
+	while (j--) {
+		if ((padc->adccon & ADC_ENABLE_START) == 0)
+			break;
+		udelay (1);
+	}
+
+	if (j == 0) {
+		printf("%s: ADC timeout\n", __FUNCTION__);
+		padc->adccon |= ADC_STDBM; /* select standby mode */
+		return -1;
+	}
+
+	result = padc->adcdat & 0x3FF;
+
+	padc->adccon |= ADC_STDBM; /* select standby mode */
+
+	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
+	       (padc->adccon >> 3) & 0x7, result);
+
+	/*
+	 * Wait for ADC to be ready for next conversion. This delay value was
+	 * estimated, because the datasheet does not specify a value.
+	 */
+	udelay (1000);
+
+	return (result);
+}
+
+
+static void adc_init (void)
+{
+	struct s3c2400_adc *padc;
+
+	padc = s3c2400_get_base_adc();
+
+	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+
+	/*
+	 * Wait some time to avoid problem with very first call of
+	 * adc_read(). Without this delay, sometimes the first read
+	 * adc value is 0. Perhaps because the adjustment of prescaler
+	 * takes some clock cycles?
+	 */
+	udelay (1000);
+
+	return;
+}
+
+
+static void led_set (unsigned int state)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	led_init ();
+
+	switch (state) {
+	case 0: /* turn LED off */
+		gpio->padat |= (1 << 12);
+		break;
+	case 1: /* turn LED on */
+		gpio->padat &= ~(1 << 12);
+		break;
+	default:
+		break;
+	}
+}
+
+static void led_blink (void)
+{
+	led_init ();
+
+	/* blink LED. This function does not return! */
+	while (1) {
+		reset_timer_masked ();
+		led_set (1);
+		udelay (1000000 / LED_BLINK_FREQ / 2);
+		led_set (0);
+		udelay (1000000 / LED_BLINK_FREQ / 2);
+	}
+}
+
+
+static void led_init (void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* configure GPA12 as output and set to High -> LED off */
+	gpio->pacon &= ~(1 << 12);
+	gpio->padat |= (1 << 12);
+}
+
+
+static void sdelay (unsigned long seconds)
+{
+	unsigned long i;
+
+	for (i = 0; i < seconds; i++) {
+		udelay (1000000);
+	}
+}
+
+
+static int global_vars_write_to_eeprom (void)
+{
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+				(unsigned char*) &status, 1)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+				(unsigned char*) &pass_cycles, 2)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+				1, (unsigned char*) &first_error_cycle, 2)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+				1, (unsigned char*) &first_error_num, 1)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+				1, (unsigned char*) first_error_name,
+				sizeof(first_error_name))) {
+		return (1);
+	}
+	return (0);
+}
+
+static void global_vars_init (void)
+{
+	status                  = 1; /* error */
+	pass_cycles             = 0;
+	first_error_cycle       = 0;
+	first_error_num         = 0;
+	first_error_name[0]     = '\0';
+	act_cycle               = 0;
+	max_cycles              = 0;
+}
+
+
+static void test_function_table_init (void)
+{
+	int i;
+
+	for (i = 0; i < BIF_MAX; i++)
+		test_function[i].pf = dummy;
+
+	/*
+	 * the length of "name" must not exceed 16, including the '\0'
+	 * termination. See also the EEPROM address map.
+	 */
+	test_function[0].pf = test_dip;
+	test_function[0].name = "dip";
+
+	test_function[1].pf = test_vcc5v;
+	test_function[1].name = "vcc5v";
+
+	test_function[2].pf = test_rotary_switch;
+	test_function[2].name = "rotary_switch";
+
+	test_function[3].pf = test_sram;
+	test_function[3].name = "sram";
+
+	test_function[4].pf = test_eeprom;
+	test_function[4].name = "eeprom";
+
+	test_function[5].pf = test_contact_temp;
+	test_function[5].name = "contact_temp";
+}
+
+
+static int read_max_cycles (void)
+{
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1,
+			       (unsigned char *) &max_cycles, 2) != 0) {
+		return (1);
+	}
+
+	return (0);
+}
+
+static int dummy(void)
+{
+	return (0);
+}
+
+int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int contact_temp;
+	int delay = 0;
+#if defined(CONFIG_CMD_DATE)
+	struct rtc_time tm;
+#endif
+
+	if (argc > 2)
+		return cmd_usage(cmdtp);
+
+	if (argc > 1)
+		delay = simple_strtoul(argv[1], NULL, 10);
+
+	tsc2000_spi_init ();
+	while (1) {
+
+#if defined(CONFIG_CMD_DATE)
+		rtc_get (&tm);
+		printf ("%4d-%02d-%02d %2d:%02d:%02d - ",
+			tm.tm_year, tm.tm_mon, tm.tm_mday,
+			tm.tm_hour, tm.tm_min, tm.tm_sec);
+#endif
+
+		contact_temp = tsc2000_contact_temp();
+		printf ("%d\n", contact_temp) ;
+
+		if (delay != 0)
+			/*
+			 * reset timer to avoid timestamp overflow problem
+			 * after about 68 minutes of udelay() time.
+			 */
+			reset_timer_masked ();
+			sdelay (delay);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	tlog,	2,	1,	do_temp_log,
+	"log contact temperature [1/100 C] to console (endlessly)",
+	"delay\n"
+	"    - contact temperature [1/100 C] is printed endlessly to console\n"
+	"      <delay> specifies the seconds to wait between two measurements\n"
+	"      For each measurment a timestamp is printeted"
+);
+
+#endif
diff --git a/u-boot/board/trab/config.mk b/u-boot/board/trab/config.mk
new file mode 100644
index 0000000..a349b8c
--- /dev/null
+++ b/u-boot/board/trab/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# TRAB board with S3C2400X (arm920t) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# TRAB has 1 bank of 16 MB or 32 MB DRAM
+#
+# 0c00'0000 to 0e00'0000
+#
+# Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000
+#
+# we load ourself to 0CF0'0000	/ 0DF0'0000
+#
+# download areas is 0C80'0000
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0x0DF40000
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/u-boot/board/trab/flash.c b/u-boot/board/trab/flash.c
new file mode 100644
index 0000000..4e89c41
--- /dev/null
+++ b/u-boot/board/trab/flash.c
@@ -0,0 +1,569 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00F000F0
+#define CMD_UNLOCK1		0x00AA00AA
+#define CMD_UNLOCK2		0x00550055
+#define CMD_ERASE_SETUP		0x00800080
+#define CMD_ERASE_CONFIRM	0x00300030
+#define CMD_PROGRAM		0x00A000A0
+#define CMD_UNLOCK_BYPASS	0x00200020
+#define CMD_READ_MANF_ID	0x00900090
+#define CMD_UNLOCK_BYPASS_RES1	0x00900090
+#define CMD_UNLOCK_BYPASS_RES2	0x00000000
+
+#define MEM_FLASH_ADDR		(*(volatile u32 *)CONFIG_SYS_FLASH_BASE)
+#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2)))
+#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2)))
+
+#define BIT_ERASE_DONE		0x00800080
+#define BIT_RDY_MASK		0x00800080
+#define BIT_PROGRAM_ERROR	0x00200020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = 0;
+		flash_info_t *info = &flash_info[i];
+
+		/* Init: no FLASHes known */
+		info->flash_id = FLASH_UNKNOWN;
+
+		size += flash_get_size (CONFIG_SYS_FLASH_BASE, info);
+
+		if (i == 0)
+			flashbase = CONFIG_SYS_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < info->sector_count; j++) {
+
+			info->protect[j] = 0;
+			info->start[j] = flashbase;
+
+			switch (info->flash_id & FLASH_TYPEMASK) {
+			case (FLASH_AM320B & FLASH_TYPEMASK):
+			case (FLASH_MXLV320B & FLASH_TYPEMASK):
+				/* Boot sector type: 8 x 8 + N x 128 kB */
+				flashbase += (j < 8) ? 0x4000 : 0x20000;
+				break;
+			case (FLASH_AM640U & FLASH_TYPEMASK):
+				/* Uniform sector type: 128 kB */
+				flashbase += 0x20000;
+				break;
+			default:
+				printf ("## Bad flash chip type 0x%04lX\n",
+					info->flash_id & FLASH_TYPEMASK);
+			}
+		}
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FLASH_MAN_AMD & FLASH_VENDMASK):
+			printf ("AMD ");		break;
+	case (FLASH_MAN_FUJ & FLASH_VENDMASK):
+			printf ("FUJITSU ");		break;
+	case (FLASH_MAN_MX  & FLASH_VENDMASK):
+			printf ("MACRONIX ");		break;
+	default:	printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (FLASH_AM320B & FLASH_TYPEMASK):
+		printf ("2x Am29LV320DB (32Mbit)\n");
+		break;
+	case (FLASH_MXLV320B & FLASH_TYPEMASK):
+		printf ("2x MX29LV320DB (32Mbit)\n");
+		break;
+	case (FLASH_AM640U & FLASH_TYPEMASK):
+		printf ("2x Am29LV640D (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+
+#if 0
+	int cflag;
+#endif
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1, chip2;
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FLASH_MAN_AMD & FLASH_VENDMASK):	break;	/* OK */
+	case (FLASH_MAN_FUJ & FLASH_VENDMASK):	break;	/* OK */
+	case (FLASH_MAN_MX  & FLASH_VENDMASK):	break;	/* OK */
+	default:
+		debug ("## flash_erase: unknown manufacturer\n");
+		return (ERR_UNKNOWN_FLASH_VENDOR);
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#if 0
+	cflag = icache_status ();
+	icache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = chip2 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+				if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip1 = ERR;
+
+				if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
+					chip2 = READY;
+
+				if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
+					chip2 = ERR;
+
+			} while (!chip1 || !chip2);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR || chip2 == ERR) {
+				rc = ERR_PROG_ERROR;
+				printf ("Flash erase error\n");
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				printf ("Flash erase timeout error\n");
+				goto outahere;
+			}
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#if 0
+	if (cflag)
+		icache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+
+#if 0
+	int cflag;
+#endif
+	int iflag;
+	int chip1, chip2;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#if 0
+	cflag = icache_status ();
+	icache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip1 = chip2 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+		if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip1 = READY;
+			else
+				chip1 = ERR;
+		}
+
+		if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
+			chip2 = READY;
+
+		if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
+				chip2 = READY;
+			else
+				chip2 = ERR;
+		}
+
+	} while (!chip1 || !chip2);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || chip2 == ERR || *addr != data) {
+		rc = ERR_PROG_ERROR;
+		printf ("Flash program error\n");
+		debug ("chip1: %#x, chip2: %#x, addr: %#lx *addr: %#lx, "
+		       "data: %#lx\n",
+		       chip1, chip2, addr, *addr, data);
+	}
+
+	if (iflag)
+		enable_interrupts ();
+
+#if 0
+	if (cflag)
+		icache_enable ();
+#endif
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			goto Done;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		if (((ulong)src) & 0x3) {
+			for (i = 0; i < 4; i++) {
+				((char *)&data)[i] = ((vu_char *)src)[i];
+			}
+		}
+		else {
+			data = *((vu_long *) src);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			goto Done;
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		rc = ERR_OK;
+		goto Done;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	rc = write_word (info, wp, data);
+
+	Done:
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	ulong value;
+
+	/* Write auto select command sequence and read Manufacturer ID */
+	addr[0x0555] = CMD_UNLOCK1;
+	addr[0x02AA] = CMD_UNLOCK2;
+	addr[0x0555] = CMD_READ_MANF_ID;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
+		debug ("## flash_init: unknown manufacturer\n");
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+
+		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
+		break;				/* =>  8 MB		*/
+
+	case AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+
+		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
+		break;				/* => 16 MB		*/
+
+	case MX_ID_LV320B:
+		info->flash_id += FLASH_MXLV320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+
+		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
+		break;				/* =>  8 MB		*/
+
+	default:
+		debug ("## flash_init: unknown flash chip\n");
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	return (info->size);
+}
diff --git a/u-boot/board/trab/lowlevel_init.S b/u-boot/board/trab/lowlevel_init.S
new file mode 100644
index 0000000..3cef414
--- /dev/null
+++ b/u-boot/board/trab/lowlevel_init.S
@@ -0,0 +1,182 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the TRAB board by
+ * (C) Copyright 2002-2003
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * TRAB specific tweaks.
+ *
+ */
+
+/* memory controller */
+#define BWSCON 0x14000000
+
+/* Bank0 */
+#define B0_Tacs	0x1	/* 1 clk */
+#define B0_Tcos	0x1	/* 1 clk */
+#define B0_Tacc	0x5	/* 8 clk */
+#define B0_Tcoh	0x1	/* 1 clk */
+#define B0_Tah	0x1	/* 1 clk */
+#define B0_Tacp	0x0
+#define B0_PMC	0x0	/* normal */
+
+/* Bank1 - SRAM */
+#define B1_Tacs	0x1	/* 1 clk */
+#define B1_Tcos	0x1	/* 1 clk */
+#define B1_Tacc	0x5	/* 8 clk */
+#define B1_Tcoh	0x1	/* 1 clk */
+#define B1_Tah	0x1	/* 1 clk */
+#define B1_Tacp	0x0
+#define B1_PMC	0x0	/* normal */
+
+/* Bank2 - CPLD */
+#define B2_Tacs	0x1	/* 1 clk */
+#define B2_Tcos	0x1	/* 1 clk */
+#define B2_Tacc	0x5	/* 8 clk */
+#define B2_Tcoh	0x1	/* 1 clk */
+#define B2_Tah	0x1	/* 1 clk */
+#define B2_Tacp	0x0
+#define B2_PMC	0x0	/* normal */
+
+/* Bank3 - setup for the cs8900 */
+#define B3_Tacs	0x3	/* 4 clk */
+#define B3_Tcos	0x3	/* 4 clk */
+#define B3_Tacc	0x7	/* 14 clk */
+#define B3_Tcoh	0x1	/* 1 clk */
+#define B3_Tah	0x0	/* 0 clk */
+#define B3_Tacp	0x3	/* 6 clk */
+#define B3_PMC	0x0	/* normal */
+
+/* Bank4 */
+#define B4_Tacs	0x0	/* 0 clk */
+#define B4_Tcos	0x0	/* 0 clk */
+#define B4_Tacc	0x7	/* 14 clk */
+#define B4_Tcoh	0x0	/* 0 clk */
+#define B4_Tah	0x0	/* 0 clk */
+#define B4_Tacp	0x0
+#define B4_PMC	0x0	/* normal */
+
+/* Bank5 */
+#define B5_Tacs	0x0	/* 0 clk */
+#define B5_Tcos	0x0	/* 0 clk */
+#define B5_Tacc	0x7	/* 14 clk */
+#define B5_Tcoh	0x0	/* 0 clk */
+#define B5_Tah	0x0	/* 0 clk */
+#define B5_Tacp	0x0
+#define B5_PMC	0x0	/* normal */
+
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x0	/* 2clk */
+#define	B6_SCAN	0x1	/* 9 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x0	/* 2clk */
+#define	B7_SCAN	0x1	/* 9 bit */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x1	/* 2clk */
+#define	B6_SCAN	0x0	/* 8 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x1	/* 2clk */
+#define	B7_SCAN	0x0	/* 8 bit */
+#endif	/* CONFIG_RAM_16MB */
+
+/* refresh parameter */
+#define REFEN	0x1	/* enable refresh */
+#define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
+#define Trp	0x0	/* 2 clk */
+#define Trc	0x3	/* 7 clk */
+#define Tchr	0x2	/* 3 clk */
+
+#ifdef CONFIG_TRAB_50MHZ
+#define REFCNT	1269	/* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
+#else
+#define REFCNT	1011	/* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
+#endif
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #52
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+	.word	0x2211d644	/* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
+	.word	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
+	.word	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
+	.word	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
+	.word	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
+	.word	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
+	.word	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
+	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
+	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
+	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
+	.word	0x17	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
+#endif	/* CONFIG_RAM_16MB */
+	.word	0x20	/* MRSR6, CL=2clk */
+	.word	0x20	/* MRSR7 */
diff --git a/u-boot/board/trab/memory.c b/u-boot/board/trab/memory.c
new file mode 100644
index 0000000..895b68e
--- /dev/null
+++ b/u-boot/board/trab/memory.c
@@ -0,0 +1,486 @@
+/*
+ * (C) Copyright 2002-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Memory test
+ *
+ * General observations:
+ * o The recommended test sequence is to test the data lines: if they are
+ *   broken, nothing else will work properly.  Then test the address
+ *   lines.  Finally, test the cells in the memory now that the test
+ *   program knows that the address and data lines work properly.
+ *   This sequence also helps isolate and identify what is faulty.
+ *
+ * o For the address line test, it is a good idea to use the base
+ *   address of the lowest memory location, which causes a '1' bit to
+ *   walk through a field of zeros on the address lines and the highest
+ *   memory location, which causes a '0' bit to walk through a field of
+ *   '1's on the address line.
+ *
+ * o Floating buses can fool memory tests if the test routine writes
+ *   a value and then reads it back immediately.  The problem is, the
+ *   write will charge the residual capacitance on the data bus so the
+ *   bus retains its state briefely.  When the test program reads the
+ *   value back immediately, the capacitance of the bus can allow it
+ *   to read back what was written, even though the memory circuitry
+ *   is broken.  To avoid this, the test program should write a test
+ *   pattern to the target location, write a different pattern elsewhere
+ *   to charge the residual capacitance in a differnt manner, then read
+ *   the target location back.
+ *
+ * o Always read the target location EXACTLY ONCE and save it in a local
+ *   variable.  The problem with reading the target location more than
+ *   once is that the second and subsequent reads may work properly,
+ *   resulting in a failed test that tells the poor technician that
+ *   "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
+ *   doesn't help him one bit and causes puzzled phone calls.  Been there,
+ *   done that.
+ *
+ * Data line test:
+ * ---------------
+ * This tests data lines for shorts and opens by forcing adjacent data
+ * to opposite states. Because the data lines could be routed in an
+ * arbitrary manner the must ensure test patterns ensure that every case
+ * is tested. By using the following series of binary patterns every
+ * combination of adjacent bits is test regardless of routing.
+ *
+ *     ...101010101010101010101010
+ *     ...110011001100110011001100
+ *     ...111100001111000011110000
+ *     ...111111110000000011111111
+ *
+ * Carrying this out, gives us six hex patterns as follows:
+ *
+ *     0xaaaaaaaaaaaaaaaa
+ *     0xcccccccccccccccc
+ *     0xf0f0f0f0f0f0f0f0
+ *     0xff00ff00ff00ff00
+ *     0xffff0000ffff0000
+ *     0xffffffff00000000
+ *
+ * To test for short and opens to other signals on our boards, we
+ * simply test with the 1's complemnt of the paterns as well, resulting
+ * in twelve patterns total.
+ *
+ * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
+ * written to a different address in case the data lines are floating.
+ * Thus, if a byte lane fails, you will see part of the special
+ * pattern in that byte lane when the test runs.  For example, if the
+ * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
+ * (for the 'a' test pattern).
+ *
+ * Address line test:
+ * ------------------
+ *  This function performs a test to verify that all the address lines
+ *  hooked up to the RAM work properly.  If there is an address line
+ *  fault, it usually shows up as two different locations in the address
+ *  map (related by the faulty address line) mapping to one physical
+ *  memory storage location.  The artifact that shows up is writing to
+ *  the first location "changes" the second location.
+ *
+ * To test all address lines, we start with the given base address and
+ * xor the address with a '1' bit to flip one address line.  For each
+ * test, we shift the '1' bit left to test the next address line.
+ *
+ * In the actual code, we start with address sizeof(ulong) since our
+ * test pattern we use is a ulong and thus, if we tried to test lower
+ * order address bits, it wouldn't work because our pattern would
+ * overwrite itself.
+ *
+ * Example for a 4 bit address space with the base at 0000:
+ *   0000 <- base
+ *   0001 <- test 1
+ *   0010 <- test 2
+ *   0100 <- test 3
+ *   1000 <- test 4
+ * Example for a 4 bit address space with the base at 0010:
+ *   0010 <- base
+ *   0011 <- test 1
+ *   0000 <- (below the base address, skipped)
+ *   0110 <- test 2
+ *   1010 <- test 3
+ *
+ * The test locations are successively tested to make sure that they are
+ * not "mirrored" onto the base address due to a faulty address line.
+ * Note that the base and each test location are related by one address
+ * line flipped.  Note that the base address need not be all zeros.
+ *
+ * Memory tests 1-4:
+ * -----------------
+ * These tests verify RAM using sequential writes and reads
+ * to/from RAM. There are several test cases that use different patterns to
+ * verify RAM. Each test case fills a region of RAM with one pattern and
+ * then reads the region back and compares its contents with the pattern.
+ * The following patterns are used:
+ *
+ *  1a) zero pattern (0x00000000)
+ *  1b) negative pattern (0xffffffff)
+ *  1c) checkerboard pattern (0x55555555)
+ *  1d) checkerboard pattern (0xaaaaaaaa)
+ *  2)  bit-flip pattern ((1 << (offset % 32))
+ *  3)  address pattern (offset)
+ *  4)  address pattern (~offset)
+ *
+ * Being run in normal mode, the test verifies only small 4Kb
+ * regions of RAM around each 1Mb boundary. For example, for 64Mb
+ * RAM the following areas are verified: 0x00000000-0x00000800,
+ * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
+ * 0x04000000. If the test is run in slow-test mode, it verifies
+ * the whole RAM.
+ */
+
+/* #ifdef CONFIG_POST */
+
+#include <post.h>
+#include <watchdog.h>
+
+/* #if CONFIG_POST & CONFIG_SYS_POST_MEMORY */
+
+/*
+ * Define INJECT_*_ERRORS for testing error detection in the presence of
+ * _good_ hardware.
+ */
+#undef  INJECT_DATA_ERRORS
+#undef  INJECT_ADDRESS_ERRORS
+
+#ifdef INJECT_DATA_ERRORS
+#warning "Injecting data line errors for testing purposes"
+#endif
+
+#ifdef INJECT_ADDRESS_ERRORS
+#warning "Injecting address line errors for testing purposes"
+#endif
+
+
+/*
+ * This function performs a double word move from the data at
+ * the source pointer to the location at the destination pointer.
+ * This is helpful for testing memory on processors which have a 64 bit
+ * wide data bus.
+ *
+ * On those PowerPC with FPU, use assembly and a floating point move:
+ * this does a 64 bit move.
+ *
+ * For other processors, let the compiler generate the best code it can.
+ */
+static void move64(const unsigned long long *src, unsigned long long *dest)
+{
+#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
+	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
+	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
+	 : : : "fr0" );		/* Clobbers fr0		*/
+    return;
+#else
+	*dest = *src;
+#endif
+}
+
+/*
+ * This is 64 bit wide test patterns.  Note that they reside in ROM
+ * (which presumably works) and the tests write them to RAM which may
+ * not work.
+ *
+ * The "otherpattern" is written to drive the data bus to values other
+ * than the test pattern.  This is for detecting floating bus lines.
+ *
+ */
+const static unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+const unsigned long long otherpattern = 0x0123456789abcdefULL;
+
+
+static int memory_post_dataline(unsigned long long * pmem)
+{
+	unsigned long long temp64;
+	int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+	int i;
+	unsigned int hi, lo, pathi, patlo;
+	int ret = 0;
+
+	for ( i = 0; i < num_patterns; i++) {
+		move64(&(pattern[i]), pmem++);
+		/*
+		 * Put a different pattern on the data lines: otherwise they
+		 * may float long enough to read back what we wrote.
+		 */
+		move64(&otherpattern, pmem--);
+		move64(pmem, &temp64);
+
+#ifdef INJECT_DATA_ERRORS
+		temp64 ^= 0x00008000;
+#endif
+
+		if (temp64 != pattern[i]){
+			pathi = (pattern[i]>>32) & 0xffffffff;
+			patlo = pattern[i] & 0xffffffff;
+
+			hi = (temp64>>32) & 0xffffffff;
+			lo = temp64 & 0xffffffff;
+
+			printf ("Memory (date line) error at %08lx, "
+				  "wrote %08x%08x, read %08x%08x !\n",
+					  (ulong)pmem, pathi, patlo, hi, lo);
+			ret = -1;
+		}
+	}
+	return ret;
+}
+
+static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
+{
+	ulong *target;
+	ulong *end;
+	ulong readback;
+	ulong xor;
+	int   ret = 0;
+
+	end = (ulong *)((ulong)base + size);	/* pointer arith! */
+	xor = 0;
+	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
+		target = (ulong *)((ulong)testaddr ^ xor);
+		if((target >= base) && (target < end)) {
+			*testaddr = ~*target;
+			readback  = *target;
+
+#ifdef INJECT_ADDRESS_ERRORS
+			if(xor == 0x00008000) {
+				readback = *testaddr;
+			}
+#endif
+			if(readback == *testaddr) {
+				printf ("Memory (address line) error at %08lx<->%08lx, "
+					"XOR value %08lx !\n",
+					(ulong)testaddr, (ulong)target,
+					xor);
+				ret = -1;
+			}
+		}
+	}
+	return ret;
+}
+
+static int memory_post_test1 (unsigned long start,
+			      unsigned long size,
+			      unsigned long val)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = val;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != val) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), val, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test2 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = 1 << (i % 32);
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != (1 << (i % 32))) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08x, read %08lx !\n",
+					  (ulong)(mem + i), 1 << (i % 32), readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test3 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test4 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = ~i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != ~i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), ~i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+int memory_post_tests (unsigned long start, unsigned long size)
+{
+	int ret = 0;
+
+	if (ret == 0)
+		ret = memory_post_dataline ((unsigned long long *)start);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((ulong *)start, (ulong *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((ulong *)(start + size - 8),
+					    (ulong *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x00000000);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xffffffff);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x55555555);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xaaaaaaaa);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test2 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test3 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test4 (start, size);
+	WATCHDOG_RESET ();
+
+	return ret;
+}
+
+#if 0
+DECLARE_GLOBAL_DATA_PTR;
+
+int memory_post_test (int flags)
+{
+	int ret = 0;
+	bd_t *bd = gd->bd;
+	phys_size_t memsize = (bd->bi_memsize >= 256 << 20 ?
+				 256 << 20 : bd->bi_memsize) - (1 << 20);
+
+
+	if (flags & POST_SLOWTEST) {
+		ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
+	} else {			/* POST_NORMAL */
+
+		unsigned long i;
+
+		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+			if (ret == 0)
+				ret = memory_post_tests (i << 20, 0x800);
+			if (ret == 0)
+				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+		}
+	}
+
+	return ret;
+}
+#endif /* 0 */
+
+/* #endif */ /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
+/* #endif */ /* CONFIG_POST */
diff --git a/u-boot/board/trab/rs485.c b/u-boot/board/trab/rs485.c
new file mode 100644
index 0000000..30336f2
--- /dev/null
+++ b/u-boot/board/trab/rs485.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ *
+ * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
+ * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include "rs485.h"
+
+static void rs485_setbrg (void);
+static void rs485_cfgio (void);
+static void set_rs485re(unsigned char rs485re_state);
+static void set_rs485de(unsigned char rs485de_state);
+static void rs485_setbrg (void);
+#ifdef	NOT_USED
+static void trab_rs485_disable_tx(void);
+static void trab_rs485_disable_rx(void);
+#endif
+
+#define UART_NR	S3C24X0_UART1
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+static void rs485_setbrg (void)
+{
+	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
+	int i;
+	unsigned int reg = 0;
+
+	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
+	/* reg = (33000000 / (16 * gd->baudrate)) - 1; */
+	reg = (33000000 / (16 * 38400)) - 1;
+
+	/* FIFO enable, Tx/Rx FIFO clear */
+	uart->ufcon = 0x07;
+	uart->umcon = 0x0;
+	/* Normal,No parity,1 stop,8 bit */
+	uart->ulcon = 0x3;
+	/*
+	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+	 * normal,interrupt or polling
+	 */
+	uart->ucon = 0x245;
+	uart->ubrdiv = reg;
+
+	for (i = 0; i < 100; i++);
+}
+
+static void rs485_cfgio (void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	gpio->pfcon &= ~(0x3 << 2);
+	gpio->pfcon |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+
+	gpio->pfcon &= ~(0x3 << 6);
+	gpio->pfcon |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+
+	gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
+	gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
+
+	gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+}
+
+/*
+ * Initialise the rs485 port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int rs485_init (void)
+{
+	rs485_cfgio ();
+	rs485_setbrg ();
+
+	return (0);
+}
+
+/*
+ * Read a single byte from the rs485 port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int rs485_getc (void)
+{
+	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
+
+	/* wait for character to arrive */
+	while (!(uart->utrstat & 0x1))
+		;
+
+	return uart->urxh & 0xff;
+}
+
+/*
+ * Output a single byte to the rs485 port.
+ */
+void rs485_putc (const char c)
+{
+	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
+
+	/* wait for room in the tx FIFO */
+	while (!(uart->utrstat & 0x2))
+		;
+
+	uart->utxh = c;
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		rs485_putc ('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int rs485_tstc (void)
+{
+	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
+
+	return uart->utrstat & 0x1;
+}
+
+void rs485_puts (const char *s)
+{
+	while (*s) {
+		rs485_putc (*s++);
+	}
+}
+
+
+/*
+ * State table:
+ *	RE	DE	Result
+ *	1	1	XMIT
+ *	0	0	RCV
+ *	1	0	Shutdown
+ */
+
+/* function that controls the receiver enable for the rs485 */
+/* rs485re_state reflects the level (0/1) of the RE pin */
+
+static void set_rs485re(unsigned char rs485re_state)
+{
+	if(rs485re_state)
+		*CPLD_RS485_RE = 0x010000;
+	else
+		*CPLD_RS485_RE = 0x0;
+}
+
+/* function that controls the sender enable for the rs485 */
+/* rs485de_state reflects the level (0/1) of the DE pin */
+
+static void set_rs485de(unsigned char rs485de_state)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* This is on PORT A bit 11 */
+	if(rs485de_state)
+		gpio->padat |= (1 << 11);
+	else
+		gpio->padat &= ~(1 << 11);
+}
+
+
+void trab_rs485_enable_tx(void)
+{
+	set_rs485de(1);
+	set_rs485re(1);
+}
+
+void trab_rs485_enable_rx(void)
+{
+	set_rs485re(0);
+	set_rs485de(0);
+}
+
+#ifdef	NOT_USED
+static void trab_rs485_disable_tx(void)
+{
+	set_rs485de(0);
+}
+
+static void trab_rs485_disable_rx(void)
+{
+	set_rs485re(1);
+}
+#endif
diff --git a/u-boot/board/trab/rs485.h b/u-boot/board/trab/rs485.h
new file mode 100644
index 0000000..19e3244
--- /dev/null
+++ b/u-boot/board/trab/rs485.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ *
+ * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
+ * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _RS485_H_
+#define _RS485_H_
+
+#include <asm/arch/s3c24x0_cpu.h>
+
+int rs485_init (void);
+int rs485_getc (void);
+void rs485_putc (const char c);
+int rs485_tstc (void);
+void rs485_puts (const char *s);
+void trab_rs485_enable_tx(void);
+void trab_rs485_enable_rx(void);
+
+#endif	/* _RS485_H_ */
diff --git a/u-boot/board/trab/trab.c b/u-boot/board/trab/trab.c
new file mode 100644
index 0000000..0f74e8f
--- /dev/null
+++ b/u-boot/board/trab/trab.c
@@ -0,0 +1,436 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SYS_BRIGHTNESS
+static void spi_init(void);
+static void wait_transmit_done(void);
+static void tsc2000_write(unsigned int page, unsigned int reg,
+						  unsigned int data);
+static void tsc2000_set_brightness(void);
+#endif
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+extern void disable_putc(void);
+extern int do_mdm_init; /* defined in common/main.c */
+
+/*
+ * We need a delay of at least 500 us after turning on the VFD clock
+ * before we can read any useful information for the CPLD controlling
+ * the keyboard switches. Let's play safe and wait 5 ms. The problem
+ * is that timers are not available yet, so we use a manually timed
+ * loop.
+ */
+#define KBD_MDELAY	5000
+static void udelay_no_timer (int usec)
+{
+	int i;
+	int delay = usec * 3;
+
+	for (i = 0; i < delay; i ++) gd->bd->bi_arch_number = MACH_TYPE_TRAB;
+}
+#endif /* CONFIG_MODEM_SUPPORT */
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init ()
+{
+#if defined(CONFIG_VFD)
+	extern int vfd_init_clocks(void);
+#endif
+	struct s3c24x0_clock_power * const clk_power =
+					s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* memory and cpu-speed are setup before relocation */
+#ifdef CONFIG_TRAB_50MHZ
+	/* change the clock to be 50 MHz 1:1:1 */
+	/* MDIV:0x5c PDIV:4 SDIV:2 */
+	clk_power->mpllcon = 0x5c042;
+	clk_power->clkdivn = 0;
+#else
+	/* change the clock to be 133 MHz 1:2:4 */
+	/* MDIV:0x7d PDIV:4 SDIV:1 */
+	clk_power->mpllcon = 0x7d041;
+	clk_power->clkdivn = 3;
+#endif
+
+	/* set up the I/O ports */
+	gpio->pacon = 0x3ffff;
+	gpio->pbcon = 0xaaaaaaaa;
+	gpio->pbup  = 0xffff;
+	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
+	/*  00,    10,      10,      10,      10,      10,      10	*/
+	gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+#ifdef CONFIG_HWFLOW
+	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
+	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+#else
+	/* do not pull up RXD0, RXD1, TXD0, TXD1 */
+	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+#endif
+	gpio->pgcon = 0x0;
+	gpio->pgup  = 0x0;
+	gpio->opencr = 0x0;
+
+	/* suppress flicker of the VFDs */
+	gpio->misccr = 0x40;
+	gpio->pfcon |= (2<<12);
+
+	gd->bd->bi_arch_number = MACH_TYPE_TRAB;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x0c000100;
+
+	/* Make sure both buzzers are turned off */
+	gpio->pdcon |= 0x5400;
+	gpio->pddat &= ~0xE0;
+
+#ifdef CONFIG_VFD
+	vfd_init_clocks();
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_MODEM_SUPPORT
+	udelay_no_timer (KBD_MDELAY);
+
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		do_mdm_init = 1;
+	}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+	/* Configure I/O ports PG5 und PG6 for I2C */
+	gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Keyboard Controller
+ */
+
+/* Maximum key number */
+#define KEYBD_KEY_NUM		4
+
+#define KBD_DATA	(((*(volatile ulong *)0x04020000) >> 16) & 0xF)
+
+static char *key_match (ulong);
+
+int misc_init_r (void)
+{
+	ulong kbd_data = KBD_DATA;
+	char *str;
+	char keybd_env[KEYBD_KEY_NUM + 1];
+	int i;
+
+#ifdef CONFIG_VERSION_VARIABLE
+	{
+		/* Set version variable. Please note, that this variable is
+		 * also set in main_loop() later in the boot process. The
+		 * version variable has to be set this early, because so it
+		 * could be used in script files on an usb stick, which
+		 * might be called during do_auto_update() */
+		extern char version_string[];
+
+		setenv ("ver", version_string);
+	}
+#endif /* CONFIG_VERSION_VARIABLE */
+
+#ifdef CONFIG_AUTO_UPDATE
+	{
+		extern int do_auto_update(void);
+		/* this has priority over all else */
+		do_auto_update();
+	}
+#endif
+
+	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
+		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
+	}
+	keybd_env[i] = '\0';
+	debug ("** Setting keybd=\"%s\"\n", keybd_env);
+	setenv ("keybd", keybd_env);
+
+	str = strdup (key_match (kbd_data));	/* decode keys */
+
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	debug ("** Setting preboot=\"%s\"\n", str);
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+
+#ifdef CONFIG_SYS_BRIGHTNESS
+	tsc2000_set_brightness();
+#endif
+	return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (ulong kbd_data, char *str)
+{
+	uchar key_mask;
+
+	debug ("compare_magic: kbd: %04lx  str: \"%s\"\n",kbd_data,str);
+	for (; *str; str++)
+	{
+		uchar c = *str - '1';
+
+		if (c >= KEYBD_KEY_NUM)		/* bad key number */
+			return -1;
+
+		key_mask = 1 << c;
+
+		if (!(kbd_data & key_mask)) {	/* key not pressed */
+			debug ( "compare_magic: "
+				"kbd: %04lx mask: %04lx - key not pressed\n",
+				kbd_data, key_mask );
+			return -1;
+		}
+
+		kbd_data &= ~key_mask;
+	}
+
+	if (kbd_data) {				/* key(s) not released */
+		debug ( "compare_magic: "
+			"kbd: %04lx - key(s) not released\n", kbd_data);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Check if pressed key(s) match magic sequence,
+ * and return the command string associated with that key(s).
+ *
+ * If no key press was decoded, NULL is returned.
+ *
+ * Note: the first character of the argument will be overwritten with
+ * the "magic charcter code" of the decoded key(s), or '\0'.
+ *
+ *
+ * Note: the string points to static environment data and must be
+ * saved before you call any function that modifies the environment.
+ */
+static char *key_match (ulong kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char cmd_name[sizeof (kbd_command_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	debug ("key_match: magic_keys=\"%s\"\n", kbd_magic_keys);
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix)
+	{
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		debug ("key_match: magic=\"%s\"\n",
+			getenv(magic) ? getenv(magic) : "<UNDEFINED>");
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0)
+		{
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			debug ("key_match: cmdname %s=\"%s\"\n",
+				cmd_name,
+				getenv (cmd_name) ?
+					getenv (cmd_name) :
+					"<UNDEFINED>");
+			return (getenv (cmd_name));
+		}
+	}
+	debug ("key_match: no match\n");
+	return (NULL);
+}
+#endif							/* CONFIG_PREBOOT */
+
+/* Read Keyboard status */
+int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong kbd_data = KBD_DATA;
+	char keybd_env[KEYBD_KEY_NUM + 1];
+	int i;
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
+		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
+		printf (" %c", keybd_env[i]);
+	}
+	keybd_env[i] = '\0';
+	putc ('\n');
+	setenv ("keybd", keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
+	"read keyboard status",
+	""
+);
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0);
+}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_SYS_BRIGHTNESS
+
+static inline void SET_CS_TOUCH(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	gpio->pddat &= 0x5FF;
+}
+
+static inline void CLR_CS_TOUCH(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	gpio->pddat |= 0x200;
+}
+
+static void spi_init(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+	int i;
+
+	/* Configure I/O ports. */
+	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
+
+	CLR_CS_TOUCH();
+
+	spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
+	spi->ch[0].sppin = 0x01;  /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */
+
+	/* Dummy byte ensures clock to be low. */
+	for (i = 0; i < 10; i++) {
+		spi->ch[0].sptdat = 0xFF;
+	}
+	wait_transmit_done();
+}
+
+static void wait_transmit_done(void)
+{
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+
+	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+		;
+}
+
+static void tsc2000_write(unsigned int page, unsigned int reg,
+						  unsigned int data)
+{
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+	unsigned int command;
+
+	SET_CS_TOUCH();
+	command = 0x0000;
+	command |= (page << 11);
+	command |= (reg << 5);
+
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
+	wait_transmit_done();
+	spi->ch[0].sptdat = (command & 0x00FF);
+	wait_transmit_done();
+	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
+	wait_transmit_done();
+	spi->ch[0].sptdat = (data & 0x00FF);
+	wait_transmit_done();
+
+	CLR_CS_TOUCH();
+}
+
+static void tsc2000_set_brightness(void)
+{
+	char tmp[10];
+	int i, br;
+
+	spi_init();
+	tsc2000_write(1, 2, 0x0); /* Power up DAC */
+
+	i = getenv_f("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CONFIG_SYS_BRIGHTNESS;
+
+	tsc2000_write(0, 0xb, br & 0xff);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_CS8900
+	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/trab/trab_fkt.c b/u-boot/board/trab/trab_fkt.c
new file mode 100644
index 0000000..fe3dab3
--- /dev/null
+++ b/u-boot/board/trab/trab_fkt.c
@@ -0,0 +1,1418 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define	DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include <timestamp.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include "tsc2000.h"
+#include "rs485.h"
+
+/*
+ * define, to wait for the touch to be pressed, before reading coordinates in
+ * command do_touch. If not defined, an error message is printed, when the
+ * command do_touch is invoked and the touch is not pressed within an specific
+ * interval.
+ */
+#undef	CONFIG_TOUCH_WAIT_PRESSED
+
+/* max time to wait for touch is pressed */
+#ifndef CONFIG_TOUCH_WAIT_PRESSED
+#define TOUCH_TIMEOUT   5
+#endif /* !CONFIG_TOUCH_WAIT_PRESSED */
+
+/* assignment of CPU internal ADC channels with TRAB hardware */
+#define VCC5V   2
+#define VCC12V  3
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
+#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
+#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+/* timer configuration bits for buzzer and PWM */
+#define START2		(1 << 12)
+#define UPDATE2         (1 << 13)
+#define INVERT2         (1 << 14)
+#define RELOAD2         (1 << 15)
+#define START3		(1 << 16)
+#define UPDATE3         (1 << 17)
+#define INVERT3         (1 << 18)
+#define RELOAD3         (1 << 19)
+
+#define PCLK		66000000
+#define BUZZER_FREQ     1000    /* frequency in Hz */
+#define PWM_FREQ        500
+
+
+/* definitions of I2C EEPROM device address */
+#define I2C_EEPROM_DEV_ADDR     0x54
+
+/* definition for touch panel calibration points */
+#define CALIB_TL 0              /* calibration point in (T)op (L)eft corner */
+#define CALIB_DR 1              /* calibration point in (D)own (R)ight corner */
+
+/* EEPROM address map */
+#define SERIAL_NUMBER           8
+#define TOUCH_X0                52
+#define TOUCH_Y0                54
+#define TOUCH_X1                56
+#define TOUCH_Y1                58
+#define CRC16                   60
+
+/* EEPROM stuff */
+#define EEPROM_MAX_CRC_BUF      64
+
+/* RS485 stuff */
+#define RS485_MAX_RECEIVE_BUF_LEN  100
+
+/* Bit definitions for ADCCON */
+#define ADC_ENABLE_START     0x1
+#define ADC_READ_START       0x2
+#define ADC_STDBM            0x4
+#define ADC_INP_AIN0         (0x0 << 3)
+#define ADC_INP_AIN1         (0x1 << 3)
+#define ADC_INP_AIN2         (0x2 << 3)
+#define ADC_INP_AIN3         (0x3 << 3)
+#define ADC_INP_AIN4         (0x4 << 3)
+#define ADC_INP_AIN5         (0x5 << 3)
+#define ADC_INP_AIN6         (0x6 << 3)
+#define ADC_INP_AIN7         (0x7 << 3)
+#define ADC_PRSCEN           0x4000
+#define ADC_ECFLG            0x8000
+
+/* function test functions */
+int do_dip (void);
+int do_info (void);
+int do_vcc5v (void);
+int do_vcc12v (void);
+int do_buttons (void);
+int do_fill_level (void);
+int do_rotary_switch (void);
+int do_pressure (void);
+int do_v_bat (void);
+int do_vfd_id (void);
+int do_buzzer (char * const *);
+int do_led (char * const *);
+int do_full_bridge (char * const *);
+int do_dac (char * const *);
+int do_motor_contact (void);
+int do_motor (char * const *);
+int do_pwm (char * const *);
+int do_thermo (char * const *);
+int do_touch (char * const *);
+int do_rs485 (char * const *);
+int do_serial_number (char * const *);
+int do_crc16 (void);
+int do_power_switch (void);
+int do_gain (char * const *);
+int do_eeprom (char * const *);
+
+/* helper functions */
+static void adc_init (void);
+static int adc_read (unsigned int channel);
+static void print_identifier (void);
+
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+static void touch_wait_pressed (void);
+#else
+static int touch_check_pressed (void);
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+
+static void touch_read_x_y (int *x, int *y);
+static int touch_write_clibration_values (int calib_point, int x, int y);
+static int rs485_send_line (const char *data);
+static int rs485_receive_chars (char *data, int timeout);
+static unsigned short updcrc(unsigned short icrc, unsigned char *icp,
+			     unsigned int icnt);
+
+#if defined(CONFIG_CMD_I2C)
+static int trab_eeprom_read (char * const *argv);
+static int trab_eeprom_write (char * const *argv);
+int i2c_write_multiple (uchar chip, uint addr, int alen, uchar *buffer,
+			int len);
+int i2c_read_multiple ( uchar chip, uint addr, int alen, uchar *buffer,
+			int len);
+#endif
+
+/*
+ * TRAB board specific commands. Especially commands for burn-in and function
+ * test.
+ */
+
+int trab_fkt (int argc, char * const argv[])
+{
+	int i;
+
+	app_startup(argv);
+	if (get_version () != XF_VERSION) {
+		printf ("Wrong XF_VERSION. Please re-compile with actual "
+			"u-boot sources\n");
+		printf ("Example expects ABI version %d\n", XF_VERSION);
+		printf ("Actual U-Boot ABI version %d\n", (int)get_version());
+		return 1;
+	}
+
+	debug ("argc = %d\n", argc);
+
+	for (i=0; i<=argc; ++i) {
+		debug ("argv[%d] = \"%s\"\n", i, argv[i] ? argv[i] : "<NULL>");
+	}
+
+	adc_init ();
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strcmp (argv[1], "info") == 0) {
+			return (do_info ());
+		}
+		if (strcmp (argv[1], "dip") == 0) {
+			return (do_dip ());
+		}
+		if (strcmp (argv[1], "vcc5v") == 0) {
+			return (do_vcc5v ());
+		}
+		if (strcmp (argv[1], "vcc12v") == 0) {
+			return (do_vcc12v ());
+		}
+		if (strcmp (argv[1], "buttons") == 0) {
+			return (do_buttons ());
+		}
+		if (strcmp (argv[1], "fill_level") == 0) {
+			return (do_fill_level ());
+		}
+		if (strcmp (argv[1], "rotary_switch") == 0) {
+			return (do_rotary_switch ());
+		}
+		if (strcmp (argv[1], "pressure") == 0) {
+			return (do_pressure ());
+		}
+		if (strcmp (argv[1], "v_bat") == 0) {
+			return (do_v_bat ());
+		}
+		if (strcmp (argv[1], "vfd_id") == 0) {
+			return (do_vfd_id ());
+		}
+		if (strcmp (argv[1], "motor_contact") == 0) {
+			return (do_motor_contact ());
+		}
+		if (strcmp (argv[1], "crc16") == 0) {
+			return (do_crc16 ());
+		}
+		if (strcmp (argv[1], "power_switch") == 0) {
+			return (do_power_switch ());
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[1], "full_bridge") == 0) {
+			return (do_full_bridge (argv));
+		}
+		if (strcmp (argv[1], "dac") == 0) {
+			return (do_dac (argv));
+		}
+		if (strcmp (argv[1], "motor") == 0) {
+			return (do_motor (argv));
+		}
+		if (strcmp (argv[1], "pwm") == 0) {
+			return (do_pwm (argv));
+		}
+		if (strcmp (argv[1], "thermo") == 0) {
+			return (do_thermo (argv));
+		}
+		if (strcmp (argv[1], "touch") == 0) {
+			return (do_touch (argv));
+		}
+		if (strcmp (argv[1], "serial_number") == 0) {
+			return (do_serial_number (argv));
+		}
+		if (strcmp (argv[1], "buzzer") == 0) {
+			return (do_buzzer (argv));
+		}
+		if (strcmp (argv[1], "gain") == 0) {
+			return (do_gain (argv));
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[1], "led") == 0) {
+			return (do_led (argv));
+		}
+		if (strcmp (argv[1], "rs485") == 0) {
+			return (do_rs485 (argv));
+		}
+		if (strcmp (argv[1], "serial_number") == 0) {
+			return (do_serial_number (argv));
+		}
+		break;
+
+	case 5:
+		if (strcmp (argv[1], "eeprom") == 0) {
+			return (do_eeprom (argv));
+		}
+		break;
+
+	case 6:
+		if (strcmp (argv[1], "eeprom") == 0) {
+			return (do_eeprom (argv));
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	printf ("Usage:\n<command> <parameter1> <parameter2> ...\n");
+	return 1;
+}
+
+void hang (void)
+{
+	puts ("### ERROR ### Please RESET the board ###\n");
+	for (;;);
+}
+
+int do_info (void)
+{
+	printf ("Stand-alone application for TRAB board function test\n");
+	printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
+
+	return 0;
+}
+
+int do_dip (void)
+{
+	unsigned int result = 0;
+	int adc_val;
+	int i;
+
+	/***********************************************************
+	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
+	   SW1 - AIN4
+	   SW2 - AIN5
+	   SW3 - AIN6
+	   SW4 - AIN7
+
+	   "On" DIP switch position short-circuits the voltage from
+	   the input channel (i.e. '0' conversion result means "on").
+	*************************************************************/
+
+	for (i = 7; i > 3; i--) {
+
+		if ((adc_val = adc_read (i)) == -1) {
+			printf ("Channel %d could not be read\n", i);
+			return 1;
+		}
+
+		/*
+		 * Input voltage (switch open) is 1.8 V.
+		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
+		 * Set trigger at halve that value.
+		 */
+		if (adc_val < 368)
+			result |= (1 << (i-4));
+	}
+
+	/* print result to console */
+	print_identifier ();
+	for (i = 0; i < 4; i++) {
+		if ((result & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+
+	return 0;
+}
+
+
+int do_vcc5v (void)
+{
+	int result;
+
+	/* VCC5V is connected to channel 2 */
+
+	if ((result = adc_read (VCC5V)) == -1) {
+		printf ("VCC5V could not be read\n");
+		return 1;
+	}
+
+	/*
+	 * Calculate voltage value. Split in two parts because there is no
+	 * floating point support.  VCC5V is connected over an resistor divider:
+	 * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
+	 */
+	print_identifier ();
+	printf ("%d", (result & 0x3FF)* 10 / 1023);
+	printf (".%d", ((result & 0x3FF)* 10 % 1023)* 10 / 1023);
+	printf ("%d V\n", (((result & 0x3FF) * 10 % 1023 ) * 10 % 1023)
+		* 10 / 1024);
+
+	return 0;
+}
+
+
+int do_vcc12v (void)
+{
+	int result;
+
+	if ((result = adc_read (VCC12V)) == -1) {
+		printf ("VCC12V could not be read\n");
+		return 1;
+	}
+
+	/*
+	 * Calculate voltage value. Split in two parts because there is no
+	 * floating point support.  VCC5V is connected over an resistor divider:
+	 * VCC12V=ADCval*2,5V/1023*(30K+270K)/30K.
+	 */
+	print_identifier ();
+	printf ("%d", (result & 0x3FF)* 25 / 1023);
+	printf (".%d V\n", ((result & 0x3FF)* 25 % 1023) * 10 / 1023);
+
+	return 0;
+}
+
+static int adc_read (unsigned int channel)
+{
+	int j = 1000; /* timeout value for wait loop in us */
+	int result;
+	struct s3c2400_adc *padc;
+
+	padc = s3c2400_get_base_adc();
+	channel &= 0x7;
+
+	padc->adccon &= ~ADC_STDBM; /* select normal mode */
+	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
+
+	while (j--) {
+		if ((padc->adccon & ADC_ENABLE_START) == 0)
+			break;
+		udelay (1);
+	}
+
+	if (j == 0) {
+		printf("%s: ADC timeout\n", __FUNCTION__);
+		padc->adccon |= ADC_STDBM; /* select standby mode */
+		return -1;
+	}
+
+	result = padc->adcdat & 0x3FF;
+
+	padc->adccon |= ADC_STDBM; /* select standby mode */
+
+	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
+	       (padc->adccon >> 3) & 0x7, result);
+
+	/*
+	 * Wait for ADC to be ready for next conversion. This delay value was
+	 * estimated, because the datasheet does not specify a value.
+	 */
+	udelay (1000);
+
+	return (result);
+}
+
+
+static void adc_init (void)
+{
+	struct s3c2400_adc *padc;
+
+	padc = s3c2400_get_base_adc();
+
+	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+
+	/*
+	 * Wait some time to avoid problem with very first call of
+	 * adc_read(). Without * this delay, sometimes the first read adc
+	 * value is 0. Perhaps because the * adjustment of prescaler takes
+	 * some clock cycles?
+	 */
+	udelay (1000);
+
+	return;
+}
+
+
+int do_buttons (void)
+{
+	int result;
+	int i;
+
+	result = *CPLD_BUTTONS; /* read CPLD */
+	debug ("%s: cpld_taster (32 bit) %#x\n", __FUNCTION__, result);
+
+	/* print result to console */
+	print_identifier ();
+	for (i = 16; i <= 19; i++) {
+		if ((result & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+	return 0;
+}
+
+
+int do_power_switch (void)
+{
+	int result;
+
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* configure GPE7 as input */
+	gpio->pecon &= ~(0x3 << (2 * 7));
+
+	/* signal GPE7 from power switch is low active: 0=on , 1=off */
+	result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1;
+
+	print_identifier ();
+	printf("%d\n", result);
+	return 0;
+}
+
+
+int do_fill_level (void)
+{
+	int result;
+
+	result = *CPLD_FILL_LEVEL; /* read CPLD */
+	debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result);
+
+	/* print result to console */
+	print_identifier ();
+	if ((result & (1 << 16)) == 0)
+		printf("0\n");
+	else
+		printf("1\n");
+	return 0;
+}
+
+
+int do_rotary_switch (void)
+{
+	int result;
+	/*
+	 * Please note, that the default values of the direction bits are
+	 * undefined after reset. So it is a good idea, to make first a dummy
+	 * call to this function, to clear the direction bits and set so to
+	 * proper values.
+	 */
+
+	result = *CPLD_ROTARY_SWITCH; /* read CPLD */
+	debug ("%s: cpld_inc (32 bit) %#x\n", __FUNCTION__, result);
+
+	*CPLD_ROTARY_SWITCH |= (3 << 16); /* clear direction bits in CPLD */
+
+	/* print result to console */
+	print_identifier ();
+	if ((result & (1 << 16)) == (1 << 16))
+		printf("R");
+	if ((result & (1 << 17)) == (1 << 17))
+		printf("L");
+	if (((result & (1 << 16)) == 0) && ((result & (1 << 17)) == 0))
+		printf("0");
+	if ((result & (1 << 18)) == 0)
+		printf("0\n");
+	else
+		printf("1\n");
+	return 0;
+}
+
+
+int do_vfd_id (void)
+{
+	int i;
+	long int pcup_old, pccon_old;
+	int vfd_board_id;
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* try to red vfd board id from the value defined by pull-ups */
+
+	pcup_old = gpio->pcup;
+	pccon_old = gpio->pccon;
+
+	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pull-ups */
+	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as
+						   * inputs */
+	udelay (10);            /* allow signals to settle */
+	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
+
+	gpio->pccon = pccon_old;
+	gpio->pcup = pcup_old;
+
+	/* print vfd_board_id to console */
+	print_identifier ();
+	for (i = 0; i < 4; i++) {
+		if ((vfd_board_id & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+	return 0;
+}
+
+int do_buzzer (char * const *argv)
+{
+	int counter;
+
+	struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* set prescaler for timer 2, 3 and 4 */
+	timers->tcfg0 &= ~0xFF00;
+	timers->tcfg0 |=  0x0F00;
+
+	/* set divider for timer 2 */
+	timers->tcfg1 &= ~0xF00;
+	timers->tcfg1 |=  0x300;
+
+	/* set frequency */
+	counter = (PCLK / BUZZER_FREQ) >> 9;
+	timers->ch[2].tcntb = counter;
+	timers->ch[2].tcmpb = counter / 2;
+
+	if (strcmp (argv[2], "on") == 0) {
+		debug ("%s: frequency: %d\n", __FUNCTION__,
+		       BUZZER_FREQ);
+
+		/* configure pin GPD7 as TOUT2 */
+		gpio->pdcon &= ~0xC000;
+		gpio->pdcon |= 0x8000;
+
+		/* start */
+		timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) &
+				~INVERT2;
+		timers->tcon = (timers->tcon | START2) & ~UPDATE2;
+		return (0);
+	}
+	else if (strcmp (argv[2], "off") == 0) {
+		/* stop */
+		timers->tcon &= ~(START2 | RELOAD2);
+
+		/* configure GPD7 as output and set to low */
+		gpio->pdcon &= ~0xC000;
+		gpio->pdcon |= 0x4000;
+		gpio->pddat &= ~0x80;
+		return (0);
+	}
+
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+
+int do_led (char * const *argv)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* configure PC14 and PC15 as output */
+	gpio->pccon &= ~(0xF << 28);
+	gpio->pccon |= (0x5 << 28);
+
+	/* configure PD0 and PD4 as output */
+	gpio->pdcon &= ~((0x3 << 8) | 0x3);
+	gpio->pdcon |= ((0x1 << 8) | 0x1);
+
+	switch (simple_strtoul(argv[2], NULL, 10)) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->pcdat |= (1 << 14);
+		else
+			gpio->pcdat &= ~(1 << 14);
+		return 0;
+
+	case 3:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->pcdat |= (1 << 15);
+		else
+			gpio->pcdat &= ~(1 << 15);
+		return 0;
+
+	case 4:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->pddat |= (1 << 0);
+		else
+			gpio->pddat &= ~(1 << 0);
+		return 0;
+
+	case 5:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->pddat |= (1 << 4);
+		else
+			gpio->pddat &= ~(1 << 4);
+		return 0;
+
+	default:
+		break;
+
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+
+int do_full_bridge (char * const *argv)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* configure PD5 and PD6 as output */
+	gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2));
+	gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2));
+
+	if (strcmp (argv[2], "+") == 0) {
+		gpio->pddat |= (1 << 5);
+	      gpio->pddat |= (1 << 6);
+	      return 0;
+	}
+	else if (strcmp (argv[2], "-") == 0) {
+		gpio->pddat &= ~(1 << 5);
+		gpio->pddat |= (1 << 6);
+		return 0;
+	}
+	else if (strcmp (argv[2], "off") == 0) {
+		gpio->pddat &= ~(1 << 5);
+		gpio->pddat &= ~(1 << 6);
+		return 0;
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+/* val must be in [0, 4095] */
+static inline unsigned long tsc2000_to_uv (u16 val)
+{
+	return ((250000 * val) / 4096) * 10;
+}
+
+
+int do_dac (char * const *argv)
+{
+	int brightness;
+
+	/* initialize SPI */
+	tsc2000_spi_init ();
+
+	if  (((brightness = simple_strtoul (argv[2], NULL, 10)) < 0) ||
+	     (brightness > 255)) {
+		printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+	tsc2000_write(TSC2000_REG_DACCTL, 0x0); /* Power up DAC */
+	tsc2000_write(TSC2000_REG_DAC, brightness & 0xff);
+
+	return 0;
+}
+
+
+int do_v_bat (void)
+{
+	unsigned long ret, res;
+
+	/* initialize SPI */
+	spi_init ();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x1836);
+
+	/* now wait for data available */
+	adc_wait_conversion_done();
+
+	ret = tsc2000_read(TSC2000_REG_BAT1);
+	res = (tsc2000_to_uv(ret) + 1250) / 2500;
+	res += (ERROR_BATTERY * res) / 1000;
+
+	print_identifier ();
+	printf ("%ld", (res / 100));
+	printf (".%ld", ((res % 100) / 10));
+	printf ("%ld V\n", (res % 10));
+	return 0;
+}
+
+
+int do_pressure (void)
+{
+	/* initialize SPI */
+	spi_init ();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2436);
+
+	/* now wait for data available */
+	adc_wait_conversion_done();
+
+	print_identifier ();
+	printf ("%d\n", tsc2000_read(TSC2000_REG_AUX2));
+	return 0;
+}
+
+
+int do_motor_contact (void)
+{
+	int result;
+
+	result = *CPLD_FILL_LEVEL; /* read CPLD */
+	debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result);
+
+	/* print result to console */
+	print_identifier ();
+	if ((result & (1 << 17)) == 0)
+		printf("0\n");
+	else
+		printf("1\n");
+	return 0;
+}
+
+int do_motor (char * const *argv)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* Configure I/O port */
+	gpio->pgcon &= ~(0x3 << 0);
+	gpio->pgcon |= (0x1 << 0);
+
+	if (strcmp (argv[2], "on") == 0) {
+		gpio->pgdat &= ~(1 << 0);
+		return 0;
+	}
+	if (strcmp (argv[2], "off") == 0) {
+		gpio->pgdat |= (1 << 0);
+		return 0;
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+static void print_identifier (void)
+{
+	printf ("## FKT: ");
+}
+
+int do_pwm (char * const *argv)
+{
+	int counter;
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+	struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+
+	if (strcmp (argv[2], "on") == 0) {
+		/* configure pin GPD8 as TOUT3 */
+		gpio->pdcon &= ~(0x3 << 8*2);
+		gpio->pdcon |= (0x2 << 8*2);
+
+		/* set prescaler for timer 2, 3 and 4 */
+		timers->tcfg0 &= ~0xFF00;
+		timers->tcfg0 |= 0x0F00;
+
+		/* set divider for timer 3 */
+		timers->tcfg1 &= ~(0xf << 12);
+		timers->tcfg1 |= (0x3 << 12);
+
+		/* set frequency */
+		counter = (PCLK / PWM_FREQ) >> 9;
+		timers->ch[3].tcntb = counter;
+		timers->ch[3].tcmpb = counter / 2;
+
+		/* start timer */
+		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
+		return 0;
+	}
+	if (strcmp (argv[2], "off") == 0) {
+
+		/* stop timer */
+		timers->tcon &= ~(START2 | RELOAD2);
+
+		/* configure pin GPD8 as output and set to 0 */
+		gpio->pdcon &= ~(0x3 << 8*2);
+		gpio->pdcon |= (0x1 << 8*2);
+		gpio->pddat &= ~(1 << 8);
+		return 0;
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+
+int do_thermo (char * const *argv)
+{
+	int     channel, res;
+
+	tsc2000_reg_init ();
+
+	if (strcmp (argv[2], "all") == 0) {
+		int i;
+		for (i=0; i <= 15; i++) {
+			res = tsc2000_read_channel(i);
+			print_identifier ();
+			printf ("c%d: %d\n", i, res);
+		}
+		return 0;
+	}
+	channel = simple_strtoul (argv[2], NULL, 10);
+	res = tsc2000_read_channel(channel);
+	print_identifier ();
+	printf ("%d\n", res);
+	return 0;                 /* return OK */
+}
+
+
+int do_touch (char * const *argv)
+{
+	int     x, y;
+
+	if (strcmp (argv[2], "tl") == 0) {
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+		touch_wait_pressed();
+#else
+		{
+			int i;
+			for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) {
+				if (touch_check_pressed ()) {
+					break;
+				}
+				udelay (1000);  /* pause 1 ms */
+			}
+		}
+		if (!touch_check_pressed()) {
+			print_identifier ();
+			printf ("error: touch not pressed\n");
+			return 1;
+		}
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+		touch_read_x_y (&x, &y);
+
+		print_identifier ();
+		printf ("x=%d y=%d\n", x, y);
+		return touch_write_clibration_values (CALIB_TL, x, y);
+	}
+	else if (strcmp (argv[2], "dr") == 0) {
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+		touch_wait_pressed();
+#else
+		{
+			int i;
+			for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) {
+				if (touch_check_pressed ()) {
+					break;
+				}
+				udelay (1000);  /* pause 1 ms */
+			}
+		}
+		if (!touch_check_pressed()) {
+			print_identifier ();
+			printf ("error: touch not pressed\n");
+			return 1;
+		}
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+		touch_read_x_y (&x, &y);
+
+		print_identifier ();
+		printf ("x=%d y=%d\n", x, y);
+
+		return touch_write_clibration_values (CALIB_DR, x, y);
+	}
+	return 1;                 /* not "tl", nor "dr", so return error */
+}
+
+
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+static void touch_wait_pressed (void)
+{
+	while (!(tsc2000_read(TSC2000_REG_ADC) & TC_PSM));
+}
+
+#else
+static int touch_check_pressed (void)
+{
+	return (tsc2000_read(TSC2000_REG_ADC) & TC_PSM);
+}
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+
+static int touch_write_clibration_values (int calib_point, int x, int y)
+{
+#if defined(CONFIG_CMD_I2C)
+	int x_verify = 0;
+	int y_verify = 0;
+
+	tsc2000_reg_init ();
+
+	if (calib_point == CALIB_TL) {
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1,
+			       (unsigned char *)&x, 2)) {
+			return 1;
+		}
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1,
+			       (unsigned char *)&y, 2)) {
+			return 1;
+		}
+
+		/* verify written values */
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1,
+			      (unsigned char *)&x_verify, 2)) {
+			return 1;
+		}
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1,
+			       (unsigned char *)&y_verify, 2)) {
+			return 1;
+		}
+		if ((y != y_verify) || (x != x_verify)) {
+			print_identifier ();
+			printf ("error: verify error\n");
+			return 1;
+		}
+		return 0;       /* no error */
+	}
+	else if (calib_point == CALIB_DR) {
+		  if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1,
+			       (unsigned char *)&x, 2)) {
+			return 1;
+		  }
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1,
+			       (unsigned char *)&y, 2)) {
+			return 1;
+		}
+
+		/* verify written values */
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1,
+				       (unsigned char *)&x_verify, 2)) {
+			return 1;
+		}
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1,
+			       (unsigned char *)&y_verify, 2)) {
+			return 1;
+		}
+		if ((y != y_verify) || (x != x_verify)) {
+			print_identifier ();
+			printf ("error: verify error\n");
+			return 1;
+		}
+		return 0;
+	}
+	return 1;
+#else
+	printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif
+}
+
+
+static void touch_read_x_y (int *px, int *py)
+{
+	tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD0 | TC_AD1);
+	adc_wait_conversion_done();
+	*px = tsc2000_read(TSC2000_REG_X);
+
+	tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD2);
+	adc_wait_conversion_done();
+	*py = tsc2000_read(TSC2000_REG_Y);
+}
+
+
+int do_rs485 (char * const *argv)
+{
+	int timeout;
+	char data[RS485_MAX_RECEIVE_BUF_LEN];
+
+	if (strcmp (argv[2], "send") == 0) {
+		return (rs485_send_line (argv[3]));
+	}
+	else if (strcmp (argv[2], "receive") == 0) {
+		timeout = simple_strtoul(argv[3], NULL, 10);
+		if (rs485_receive_chars (data, timeout) != 0) {
+			print_identifier ();
+			printf ("## nothing received\n");
+			return (1);
+		}
+		else {
+			print_identifier ();
+			printf ("%s\n", data);
+			return (0);
+		}
+	}
+	printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]);
+	return (1);             /* unknown command, return error */
+}
+
+
+static int rs485_send_line (const char *data)
+{
+	rs485_init ();
+	trab_rs485_enable_tx ();
+	rs485_puts (data);
+	rs485_putc ('\n');
+
+	return (0);
+}
+
+
+static int rs485_receive_chars (char *data, int timeout)
+{
+	int i;
+	int receive_count = 0;
+
+	rs485_init ();
+	trab_rs485_enable_rx ();
+
+	/* test every 1 ms for received characters to avoid a receive FIFO
+	 * overrun (@ 38.400 Baud) */
+	for (i = 0; i < (timeout * 1000); i++) {
+		while (rs485_tstc ()) {
+			if (receive_count >= RS485_MAX_RECEIVE_BUF_LEN-1)
+				break;
+			*data++ = rs485_getc ();
+			receive_count++;
+		}
+		udelay (1000);  /* pause 1 ms */
+	}
+	*data = '\0';           /* terminate string */
+
+	if (receive_count == 0)
+		return (1);
+	else
+		return (0);
+}
+
+
+int do_serial_number (char * const *argv)
+{
+#if defined(CONFIG_CMD_I2C)
+	unsigned int serial_number;
+
+	if (strcmp (argv[2], "read") == 0) {
+		if (i2c_read (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1,
+			      (unsigned char *)&serial_number, 4)) {
+			printf ("could not read from eeprom\n");
+			return (1);
+		}
+		print_identifier ();
+		printf ("%08d\n", serial_number);
+		return (0);
+	}
+	else if (strcmp (argv[2], "write") == 0) {
+		serial_number = simple_strtoul(argv[3], NULL, 10);
+		if (i2c_write (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1,
+			      (unsigned char *)&serial_number, 4)) {
+			printf ("could not write to eeprom\n");
+			return (1);
+		}
+		return (0);
+	}
+	printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]);
+	return (1);             /* unknown command, return error */
+#else
+	printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif
+}
+
+
+int do_crc16 (void)
+{
+#if defined(CONFIG_CMD_I2C)
+	int crc;
+	unsigned char buf[EEPROM_MAX_CRC_BUF];
+
+	if (i2c_read (I2C_EEPROM_DEV_ADDR, 0, 1, buf, 60)) {
+		printf ("could not read from eeprom\n");
+		return (1);
+	}
+	crc = 0;                /* start value of crc calculation */
+	crc = updcrc (crc, buf, 60);
+
+	print_identifier ();
+	printf ("crc16=%#04x\n", crc);
+
+	if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (unsigned char *)&crc,
+		       sizeof (crc))) {
+		printf ("could not read from eeprom\n");
+		return (1);
+	}
+	return (0);
+#else
+	printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif
+}
+
+
+/*
+ * Calculate, intelligently, the CRC of a dataset incrementally given a
+ * buffer full at a time.
+ * Initialize crc to 0 for XMODEM, -1 for CCITT.
+ *
+ * Usage:
+ *   newcrc = updcrc( oldcrc, bufadr, buflen )
+ *        unsigned int oldcrc, buflen;
+ *        char *bufadr;
+ *
+ * Compile with -DTEST to generate program that prints CRC of stdin to stdout.
+ * Compile with -DMAKETAB to print values for crctab to stdout
+ */
+
+    /* the CRC polynomial. This is used by XMODEM (almost CCITT).
+     * If you change P, you must change crctab[]'s initial value to what is
+     * printed by initcrctab()
+     */
+#define   P    0x1021
+
+    /* number of bits in CRC: don't change it. */
+#define W 16
+
+    /* this the number of bits per char: don't change it. */
+#define B 8
+
+static unsigned short crctab[1<<B] = { /* as calculated by initcrctab() */
+    0x0000,  0x1021,  0x2042,  0x3063,  0x4084,  0x50a5,  0x60c6,  0x70e7,
+    0x8108,  0x9129,  0xa14a,  0xb16b,  0xc18c,  0xd1ad,  0xe1ce,  0xf1ef,
+    0x1231,  0x0210,  0x3273,  0x2252,  0x52b5,  0x4294,  0x72f7,  0x62d6,
+    0x9339,  0x8318,  0xb37b,  0xa35a,  0xd3bd,  0xc39c,  0xf3ff,  0xe3de,
+    0x2462,  0x3443,  0x0420,  0x1401,  0x64e6,  0x74c7,  0x44a4,  0x5485,
+    0xa56a,  0xb54b,  0x8528,  0x9509,  0xe5ee,  0xf5cf,  0xc5ac,  0xd58d,
+    0x3653,  0x2672,  0x1611,  0x0630,  0x76d7,  0x66f6,  0x5695,  0x46b4,
+    0xb75b,  0xa77a,  0x9719,  0x8738,  0xf7df,  0xe7fe,  0xd79d,  0xc7bc,
+    0x48c4,  0x58e5,  0x6886,  0x78a7,  0x0840,  0x1861,  0x2802,  0x3823,
+    0xc9cc,  0xd9ed,  0xe98e,  0xf9af,  0x8948,  0x9969,  0xa90a,  0xb92b,
+    0x5af5,  0x4ad4,  0x7ab7,  0x6a96,  0x1a71,  0x0a50,  0x3a33,  0x2a12,
+    0xdbfd,  0xcbdc,  0xfbbf,  0xeb9e,  0x9b79,  0x8b58,  0xbb3b,  0xab1a,
+    0x6ca6,  0x7c87,  0x4ce4,  0x5cc5,  0x2c22,  0x3c03,  0x0c60,  0x1c41,
+    0xedae,  0xfd8f,  0xcdec,  0xddcd,  0xad2a,  0xbd0b,  0x8d68,  0x9d49,
+    0x7e97,  0x6eb6,  0x5ed5,  0x4ef4,  0x3e13,  0x2e32,  0x1e51,  0x0e70,
+    0xff9f,  0xefbe,  0xdfdd,  0xcffc,  0xbf1b,  0xaf3a,  0x9f59,  0x8f78,
+    0x9188,  0x81a9,  0xb1ca,  0xa1eb,  0xd10c,  0xc12d,  0xf14e,  0xe16f,
+    0x1080,  0x00a1,  0x30c2,  0x20e3,  0x5004,  0x4025,  0x7046,  0x6067,
+    0x83b9,  0x9398,  0xa3fb,  0xb3da,  0xc33d,  0xd31c,  0xe37f,  0xf35e,
+    0x02b1,  0x1290,  0x22f3,  0x32d2,  0x4235,  0x5214,  0x6277,  0x7256,
+    0xb5ea,  0xa5cb,  0x95a8,  0x8589,  0xf56e,  0xe54f,  0xd52c,  0xc50d,
+    0x34e2,  0x24c3,  0x14a0,  0x0481,  0x7466,  0x6447,  0x5424,  0x4405,
+    0xa7db,  0xb7fa,  0x8799,  0x97b8,  0xe75f,  0xf77e,  0xc71d,  0xd73c,
+    0x26d3,  0x36f2,  0x0691,  0x16b0,  0x6657,  0x7676,  0x4615,  0x5634,
+    0xd94c,  0xc96d,  0xf90e,  0xe92f,  0x99c8,  0x89e9,  0xb98a,  0xa9ab,
+    0x5844,  0x4865,  0x7806,  0x6827,  0x18c0,  0x08e1,  0x3882,  0x28a3,
+    0xcb7d,  0xdb5c,  0xeb3f,  0xfb1e,  0x8bf9,  0x9bd8,  0xabbb,  0xbb9a,
+    0x4a75,  0x5a54,  0x6a37,  0x7a16,  0x0af1,  0x1ad0,  0x2ab3,  0x3a92,
+    0xfd2e,  0xed0f,  0xdd6c,  0xcd4d,  0xbdaa,  0xad8b,  0x9de8,  0x8dc9,
+    0x7c26,  0x6c07,  0x5c64,  0x4c45,  0x3ca2,  0x2c83,  0x1ce0,  0x0cc1,
+    0xef1f,  0xff3e,  0xcf5d,  0xdf7c,  0xaf9b,  0xbfba,  0x8fd9,  0x9ff8,
+    0x6e17,  0x7e36,  0x4e55,  0x5e74,  0x2e93,  0x3eb2,  0x0ed1,  0x1ef0
+    };
+
+static unsigned short updcrc(unsigned short icrc, unsigned char *icp,
+			     unsigned int icnt )
+{
+	register unsigned short crc = icrc;
+	register unsigned char *cp = icp;
+	register unsigned int cnt = icnt;
+
+	while (cnt--)
+		crc = (crc<<B) ^ crctab[(crc>>(W-B)) ^ *cp++];
+
+	return (crc);
+}
+
+
+int do_gain (char * const *argv)
+{
+	int range;
+
+	range = simple_strtoul (argv[2], NULL, 10);
+	if ((range < 1) || (range > 3))
+	{
+		printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+
+	tsc2000_set_range (range);
+	return (0);
+}
+
+
+int do_eeprom (char * const *argv)
+{
+#if defined(CONFIG_CMD_I2C)
+	if (strcmp (argv[2], "read") == 0) {
+		return (trab_eeprom_read (argv));
+	}
+
+	else if (strcmp (argv[2], "write") == 0) {
+		return (trab_eeprom_write (argv));
+	}
+
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return (1);
+#else
+	printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif
+}
+
+#if defined(CONFIG_CMD_I2C)
+static int trab_eeprom_read (char * const *argv)
+{
+	int i;
+	int len;
+	unsigned int addr;
+	long int value = 0;
+	uchar *buffer;
+
+	buffer = (uchar *) &value;
+	addr = simple_strtoul (argv[3], NULL, 10);
+	addr &= 0xfff;
+	len = simple_strtoul (argv[4], NULL, 10);
+	if ((len < 1) || (len > 4)) {
+		printf ("%s: invalid parameter %s\n", __FUNCTION__,
+			argv[4]);
+		return (1);
+	}
+	for (i = 0; i < len; i++) {
+		if (i2c_read (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) {
+			printf ("%s: could not read from i2c device %#x"
+				", addr %d\n", __FUNCTION__,
+				I2C_EEPROM_DEV_ADDR, addr);
+			return (1);
+		}
+	}
+	print_identifier ();
+	if (strcmp (argv[5], "-") == 0) {
+		if (len == 1)
+			printf ("%d\n", (signed char) value);
+		else if (len == 2)
+			printf ("%d\n", (signed short int) value);
+		else
+			printf ("%ld\n", value);
+	}
+	else {
+		if (len == 1)
+			printf ("%d\n", (unsigned char) value);
+		else if (len == 2)
+			printf ("%d\n", (unsigned short int) value);
+		else
+			printf ("%ld\n", (unsigned long int) value);
+	}
+	return (0);
+}
+
+static int trab_eeprom_write (char * const *argv)
+{
+	int i;
+	int len;
+	unsigned int addr;
+	long int value = 0;
+	uchar *buffer;
+
+	buffer = (uchar *) &value;
+	addr = simple_strtoul (argv[3], NULL, 10);
+	addr &= 0xfff;
+	len = simple_strtoul (argv[4], NULL, 10);
+	if ((len < 1) || (len > 4)) {
+		printf ("%s: invalid parameter %s\n", __FUNCTION__,
+			argv[4]);
+		return (1);
+	}
+	value = simple_strtol (argv[5], NULL, 10);
+	debug ("value=%ld\n", value);
+	for (i = 0; i < len; i++) {
+		if (i2c_write (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) {
+			printf ("%s: could not write to i2c device %d"
+				", addr %d\n", __FUNCTION__,
+				I2C_EEPROM_DEV_ADDR, addr);
+			return (1);
+		}
+#if 0
+		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+			"%#x+%d=%p=%#x \n",I2C_EEPROM_DEV_ADDR_DEV_ADDR , addr,
+			i, addr+i, 1, buffer, i, buffer+i, *(buffer+i));
+#endif
+		udelay (30000); /* wait for EEPROM ready */
+	}
+	return (0);
+}
+
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not write to i2c device %d"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+#if 0
+		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+			"%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
+			alen, buffer, i, buffer+i, buffer+i);
+#endif
+
+		udelay (30000);
+	}
+	return (0);
+}
+
+int i2c_read_multiple ( uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not read from i2c device %#x"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+	}
+	return (0);
+}
+#endif
diff --git a/u-boot/board/trab/tsc2000.c b/u-boot/board/trab/tsc2000.c
new file mode 100644
index 0000000..426ed9c
--- /dev/null
+++ b/u-boot/board/trab/tsc2000.c
@@ -0,0 +1,366 @@
+/*
+ * Functions to access the TSC2000 controller on TRAB board (used for scanning
+ * thermo sensors)
+ *
+ * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
+#include <div64.h>
+#include "tsc2000.h"
+
+#include "Pt1000_temp_data.h"
+
+/* helper function */
+#define abs(value) (((value) < 0) ? ((value)*-1) : (value))
+
+/*
+ * Maximal allowed deviation between two immediate meassurments of an analog
+ * thermo channel. 1 DIGIT = 0.0276 °C. This is used to filter sporadic
+ * "jumps" in measurment.
+ */
+#define MAX_DEVIATION	18	/* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */
+
+void tsc2000_spi_init(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+	int i;
+
+	/* Configure I/O ports. */
+	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
+
+	CLR_CS_TOUCH();
+
+	spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
+	spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+				    CPHA=1 */
+
+	/* Dummy byte ensures clock to be low. */
+	for (i = 0; i < 10; i++) {
+		spi->ch[0].sptdat = 0xFF;
+	}
+	spi_wait_transmit_done();
+}
+
+
+void spi_wait_transmit_done(void)
+{
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+
+	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+		;
+}
+
+
+void tsc2000_write(unsigned short reg, unsigned short data)
+{
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+	unsigned int command;
+
+	SET_CS_TOUCH();
+	command = reg;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].sptdat = (command & 0x00FF);
+	spi_wait_transmit_done();
+	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].sptdat = (data & 0x00FF);
+	spi_wait_transmit_done();
+
+	CLR_CS_TOUCH();
+}
+
+
+unsigned short tsc2000_read (unsigned short reg)
+{
+	unsigned short command, data;
+	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
+
+	SET_CS_TOUCH();
+	command = 0x8000 | reg;
+
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].sptdat = (command & 0x00FF);
+	spi_wait_transmit_done();
+
+	spi->ch[0].sptdat = 0xFF;
+	spi_wait_transmit_done();
+	data = spi->ch[0].sprdat;
+	spi->ch[0].sptdat = 0xFF;
+	spi_wait_transmit_done();
+
+	CLR_CS_TOUCH();
+	return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
+}
+
+
+void tsc2000_set_mux (unsigned int channel)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
+	CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
+	switch (channel) {
+	case 0:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 1:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 2:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 3:
+		SET_MUX0; SET_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 4:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 5:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 6:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 7:
+		SET_MUX0; SET_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 8:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 9:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 10:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 11:
+		SET_MUX0; SET_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 12:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 13:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 14:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 15:
+		SET_MUX0; SET_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	default:
+		CLR_MUX0; CLR_MUX1;
+	}
+}
+
+
+void tsc2000_set_range (unsigned int range)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	switch (range) {
+	case 1:
+		CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1;
+		CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
+		break;
+	case 2:
+		CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
+		CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3;
+		break;
+	case 3:
+		SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
+		SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
+		break;
+	}
+}
+
+
+u16 tsc2000_read_channel (unsigned int channel)
+{
+	u16 res;
+
+	tsc2000_set_mux(channel);
+	udelay(20 * TSC2000_DELAY_BASE);
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2036);
+	adc_wait_conversion_done ();
+	res = tsc2000_read(TSC2000_REG_AUX1);
+	return res;
+}
+
+
+s32 tsc2000_contact_temp (void)
+{
+	long adc_pt1000, offset;
+	long u_pt1000;
+	long contact_temp;
+	long temp1, temp2;
+
+	tsc2000_reg_init ();
+	tsc2000_set_range (3);
+
+	/*
+	 * Because of sporadic "jumps" in the measured adc values every
+	 * channel is read two times. If there is a significant difference
+	 * between the two measurements, then print an error and do a third
+	 * measurement, because it is very unlikely that a successive third
+	 * measurement goes also wrong.
+	 */
+	temp1 = tsc2000_read_channel (14);
+	temp2 = tsc2000_read_channel (14);
+	if (abs(temp2 - temp1) < MAX_DEVIATION)
+		adc_pt1000 = temp2;
+	else {
+		printf ("%s: read adc value (channel 14) exceeded max allowed "
+			"deviation: %d * 0.0276 °C\n",
+			__FUNCTION__, MAX_DEVIATION);
+		printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n",
+			temp1, temp2);
+		adc_pt1000 = tsc2000_read_channel (14);
+		printf ("use (third read) adc value: adc_pt1000 = "
+			"%ld DIGITs\n",	adc_pt1000);
+	}
+	debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+
+	temp1 = tsc2000_read_channel (15);
+	temp2 = tsc2000_read_channel (15);
+	if (abs(temp2 - temp1) < MAX_DEVIATION)
+		offset = temp2;
+	else {
+		printf ("%s: read adc value (channel 15) exceeded max allowed "
+			"deviation: %d * 0.0276 °C\n",
+			__FUNCTION__, MAX_DEVIATION);
+		printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n",
+			temp1, temp2);
+		offset = tsc2000_read_channel (15);
+		printf ("use (third read) adc value: offset = %ld DIGITs\n",
+			offset);
+	}
+	debug ("read channel 15 (offset): %ld\n", offset);
+
+	/*
+	 * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+	 * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+	 * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+	 * error correction Values err_vref and err_amp3 are assumed as 0 in
+	 * u-boot, because this could cause only a very small error (< 1%).
+	 */
+	u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+	debug ("u_pt1000: %ld\n", u_pt1000);
+
+	if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+				&contact_temp) == -1) {
+		printf ("%s: error interpolating PT1000 vlaue\n",
+			 __FUNCTION__);
+		return (-1000);
+	}
+	debug ("contact_temp: %ld\n", contact_temp);
+
+	return contact_temp;
+}
+
+
+void tsc2000_reg_init (void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2036);
+	tsc2000_write(TSC2000_REG_REF, 0x0011);
+	tsc2000_write(TSC2000_REG_DACCTL, 0x0000);
+
+	CON_MUX0;
+	CON_MUX1;
+
+	CON_MUX1_ENABLE;
+	CON_MUX2_ENABLE;
+	CON_MUX3_ENABLE;
+	CON_MUX4_ENABLE;
+
+	CON_SEL_TEMP_V_0;
+	CON_SEL_TEMP_V_1;
+	CON_SEL_TEMP_V_2;
+	CON_SEL_TEMP_V_3;
+
+	tsc2000_set_mux(0);
+	tsc2000_set_range(0);
+}
+
+
+int tsc2000_interpolate(long value, long data[][2], long *result)
+{
+	int i;
+	unsigned long long val;
+
+	/* the data is sorted and the first element is upper
+	 * limit so we can easily check for out-of-band values
+	 */
+	if (data[0][0] < value || data[1][0] > value)
+		return -1;
+
+	i = 1;
+	while (data[i][0] < value)
+		i++;
+
+	/* To prevent overflow we have to store the intermediate
+	   result in 'long long'.
+	*/
+
+	val = ((unsigned long long)(data[i][1] - data[i-1][1])
+		   * (unsigned long long)(value - data[i-1][0]));
+	do_div(val, (data[i][0] - data[i-1][0]));
+	*result = data[i-1][1] + val;
+
+	return 0;
+}
+
+
+void adc_wait_conversion_done(void)
+{
+	while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+}
diff --git a/u-boot/board/trab/tsc2000.h b/u-boot/board/trab/tsc2000.h
new file mode 100644
index 0000000..f3cecb9
--- /dev/null
+++ b/u-boot/board/trab/tsc2000.h
@@ -0,0 +1,148 @@
+/*
+ * Functions to access the TSC2000 controller on TRAB board (used for scanning
+ * thermo sensors)
+ *
+ * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TSC2000_H_
+#define _TSC2000_H_
+
+/* temperature channel multiplexer definitions */
+#define CON_MUX0	(gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0	(gpio->pcdat &= 0x0FFEF)
+#define SET_MUX0	(gpio->pcdat |= 0x00010)
+
+#define CON_MUX1	(gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1	(gpio->pcdat &= 0x0FFDF)
+#define SET_MUX1	(gpio->pcdat |= 0x00020)
+
+#define CON_MUX1_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE	(gpio->pcdat |= 0x00040)
+#define SET_MUX1_ENABLE	(gpio->pcdat &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE	(gpio->pcdat |= 0x00080)
+#define SET_MUX2_ENABLE	(gpio->pcdat &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE	(gpio->pcdat |= 0x00100)
+#define SET_MUX3_ENABLE	(gpio->pcdat &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE	(gpio->pcdat |= 0x00200)
+#define SET_MUX4_ENABLE	(gpio->pcdat &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0	(gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
+							0x00100000)
+#define CLR_SEL_TEMP_V_0	(gpio->pcdat &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0	(gpio->pcdat |= 0x00400)
+
+#define CON_SEL_TEMP_V_1	(gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
+		0x00400000)
+#define CLR_SEL_TEMP_V_1	(gpio->pcdat &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1	(gpio->pcdat |= 0x00800)
+
+#define CON_SEL_TEMP_V_2	(gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
+		0x01000000)
+#define CLR_SEL_TEMP_V_2	(gpio->pcdat &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2	(gpio->pcdat |= 0x01000)
+
+#define CON_SEL_TEMP_V_3	(gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
+		0x04000000)
+#define CLR_SEL_TEMP_V_3	(gpio->pcdat &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3	(gpio->pcdat |= 0x02000)
+
+/* TSC2000 register definition */
+#define TSC2000_REG_X		((0 << 11) | (0 << 5))
+#define TSC2000_REG_Y		((0 << 11) | (1 << 5))
+#define TSC2000_REG_Z1		((0 << 11) | (2 << 5))
+#define TSC2000_REG_Z2		((0 << 11) | (3 << 5))
+#define TSC2000_REG_BAT1	((0 << 11) | (5 << 5))
+#define TSC2000_REG_BAT2	((0 << 11) | (6 << 5))
+#define TSC2000_REG_AUX1	((0 << 11) | (7 << 5))
+#define TSC2000_REG_AUX2	((0 << 11) | (8 << 5))
+#define TSC2000_REG_TEMP1	((0 << 11) | (9 << 5))
+#define TSC2000_REG_TEMP2	((0 << 11) | (0xA << 5))
+#define TSC2000_REG_DAC		((0 << 11) | (0xB << 5))
+#define TSC2000_REG_ZERO	((0 << 11) | (0x10 << 5))
+#define TSC2000_REG_ADC		((1 << 11) | (0 << 5))
+#define TSC2000_REG_DACCTL	((1 << 11) | (2 << 5))
+#define TSC2000_REG_REF		((1 << 11) | (3 << 5))
+#define TSC2000_REG_RESET	((1 << 11) | (4 << 5))
+#define TSC2000_REG_CONFIG	((1 << 11) | (5 << 5))
+
+/* bit definition of TSC2000 ADC register */
+#define TC_PSM			(1 << 15)
+#define TC_STS			(1 << 14)
+#define TC_AD3			(1 << 13)
+#define TC_AD2			(1 << 12)
+#define TC_AD1			(1 << 11)
+#define TC_AD0			(1 << 10)
+#define TC_RS1			(1 << 9)
+#define TC_RS0			(1 << 8)
+#define TC_AV1			(1 << 7)
+#define TC_AV0			(1 << 6)
+#define TC_CL1			(1 << 5)
+#define TC_CL0			(1 << 4)
+#define TC_PV2			(1 << 3)
+#define TC_PV1			(1 << 2)
+#define TC_PV0			(1 << 1)
+
+/* default value for TSC2000 ADC register for use with touch functions */
+#define DEFAULT_ADC		(TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0)
+
+#define TSC2000_DELAY_BASE	500
+#define TSC2000_NO_SENSOR	-0x10000
+
+#define ERROR_BATTERY		220	/* must be adjusted, if R68 is changed on TRAB */
+
+void tsc2000_write(unsigned short, unsigned short);
+unsigned short tsc2000_read (unsigned short);
+u16 tsc2000_read_channel (unsigned int);
+void tsc2000_set_mux (unsigned int);
+void tsc2000_set_range (unsigned int);
+void tsc2000_reg_init (void);
+s32 tsc2000_contact_temp (void);
+void spi_wait_transmit_done (void);
+void tsc2000_spi_init(void);
+int tsc2000_interpolate(long value, long data[][2], long *result);
+void adc_wait_conversion_done(void);
+
+
+static inline void SET_CS_TOUCH(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	gpio->pddat &= 0x5FF;
+}
+
+
+static inline void CLR_CS_TOUCH(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	gpio->pddat |= 0x200;
+}
+
+#endif	/* _TSC2000_H_ */
diff --git a/u-boot/board/trab/u-boot.lds b/u-boot/board/trab/u-boot.lds
new file mode 100644
index 0000000..cd50e85
--- /dev/null
+++ b/u-boot/board/trab/u-boot.lds
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  arch/arm/cpu/arm920t/start.o	(.text)
+	  lib/zlib.o	(.text)
+	  lib/crc32.o	(.text)
+	  lib/string.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o	(.ppcenv)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/u-boot/board/trab/vfd.c b/u-boot/board/trab/vfd.c
new file mode 100644
index 0000000..9a2b1ba
--- /dev/null
+++ b/u-boot/board/trab/vfd.c
@@ -0,0 +1,574 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************/
+/* ** DEBUG SETTINGS							*/
+/************************************************************************/
+
+/* #define DEBUG	*/
+
+/************************************************************************/
+/* ** HEADER FILES							*/
+/************************************************************************/
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+#include <stdarg.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_VFD
+
+/************************************************************************/
+/* ** CONFIG STUFF -- should be moved to board config file		*/
+/************************************************************************/
+
+/************************************************************************/
+
+#ifndef PAGE_SIZE
+#define	PAGE_SIZE	4096
+#endif
+
+#define ROT	0x09
+#define BLAU	0x0C
+#define VIOLETT	0X0D
+
+/* MAGIC */
+#define	FRAME_BUF_SIZE	((256*4*56)/8)
+#define frame_buf_offs 4
+
+/* defines for starting Timer3 as CPLD-Clk */
+#define START3			(1 << 16)
+#define UPDATE3			(1 << 17)
+#define INVERT3			(1 << 18)
+#define RELOAD3			(1 << 19)
+
+/* CPLD-Register for controlling vfd-blank-signal */
+#define VFD_DISABLE	(*(volatile uchar *)0x04038000=0x0000)
+#define VFD_ENABLE	(*(volatile uchar *)0x04038000=0x0001)
+
+/* Supported VFD Types */
+#define	VFD_TYPE_T119C		1	/* Noritake T119C VFD */
+#define	VFD_TYPE_MN11236	2
+
+/*#define NEW_CPLD_CLK*/
+
+int vfd_board_id;
+
+/* taken from armboot/common/vfd.c */
+unsigned long adr_vfd_table[112][18][2][4][2];
+unsigned char bit_vfd_table[112][18][2][4][2];
+
+/*
+ * initialize the values for the VFD-grid-control in the framebuffer
+ */
+void init_grid_ctrl(void)
+{
+	ulong adr, grid_cycle;
+	unsigned int bit, display;
+	unsigned char temp, bit_nr;
+
+	/*
+	 * clear frame buffer (logical clear => set to "black")
+	 */
+	memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE);
+
+	switch (gd->vfd_type) {
+	case VFD_TYPE_T119C:
+	    for (display=0; display<4; display++) {
+		for(grid_cycle=0; grid_cycle<56; grid_cycle++) {
+			bit = grid_cycle * 256  * 4 +
+			     (grid_cycle + 200) * 4 +
+			     frame_buf_offs + display;
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit - (FRAME_BUF_SIZE * 8);
+			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
+			bit_nr = bit % 8;
+			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+
+			if(grid_cycle<55)
+				bit = grid_cycle*256*4+(grid_cycle+201)*4+frame_buf_offs+display;
+			else
+				bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4;	/* grid nr. 0 */
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit-(FRAME_BUF_SIZE*8);
+			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
+			bit_nr = bit%8;
+			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+		}
+	    }
+	    break;
+	case VFD_TYPE_MN11236:
+	    for (display=0; display<4; display++) {
+		for (grid_cycle=0; grid_cycle<38; grid_cycle++) {
+			bit = grid_cycle * 256  * 4 +
+			     (253 - grid_cycle) * 4 +
+			     frame_buf_offs + display;
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit - (FRAME_BUF_SIZE * 8);
+			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
+			bit_nr = bit % 8;
+			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+
+			if(grid_cycle<37)
+				bit = grid_cycle*256*4+(252-grid_cycle)*4+frame_buf_offs+display;
+
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit-(FRAME_BUF_SIZE*8);
+			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
+			bit_nr = bit%8;
+			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+		}
+	    }
+	    break;
+	default:
+	    printf ("Warning: unknown display type\n");
+	    break;
+	}
+}
+
+/*
+ *create translation table for getting easy the right position in the
+ *physical framebuffer for some x/y-coordinates of the VFDs
+ */
+void create_vfd_table(void)
+{
+	unsigned long vfd_table[112][18][2][4][2];
+	unsigned int x, y, color, display, entry, pixel;
+	unsigned int x_abcdef = 0;
+
+	switch (gd->vfd_type) {
+	case VFD_TYPE_T119C:
+	    for(y=0; y<=17; y++) {	/* Line */
+		for(x=0; x<=111; x++) {	/* Column */
+		    for(display=0; display <=3; display++) {
+
+			    /* Display 0 blue pixels */
+			    vfd_table[x][y][0][display][0] =
+				(x==0) ? y*16+display
+				       : (x%4)*4+y*16+((x-1)/2)*1024+display;
+			    /* Display 0 red pixels */
+			    vfd_table[x][y][1][display][0] =
+				(x==0) ? y*16+512+display
+				       : (x%4)*4+y*16+((x-1)/2)*1024+512+display;
+		    }
+		}
+	    }
+	    break;
+	case VFD_TYPE_MN11236:
+	    for(y=0; y<=17; y++) {	/* Line */
+		for(x=0; x<=111; x++) {	/* Column */
+		    for(display=0; display <=3; display++) {
+
+			    vfd_table[x][y][0][display][0]=0;
+			    vfd_table[x][y][0][display][1]=0;
+			    vfd_table[x][y][1][display][0]=0;
+			    vfd_table[x][y][1][display][1]=0;
+
+			    switch (x%6) {
+			    case 0: x_abcdef=0; break; /* a -> a */
+			    case 1: x_abcdef=2; break; /* b -> c */
+			    case 2: x_abcdef=4; break; /* c -> e */
+			    case 3: x_abcdef=5; break; /* d -> f */
+			    case 4: x_abcdef=3; break; /* e -> d */
+			    case 5: x_abcdef=1; break; /* f -> b */
+			    }
+
+			    /* blue pixels */
+			    vfd_table[x][y][0][display][0] =
+				(x>1) ? x_abcdef*4+((x-1)/3)*1024+y*48+display
+				      : x_abcdef*4+             0+y*48+display;
+			    /* blue pixels */
+			    if (x>1 && (x-1)%3)
+				    vfd_table[x][y][0][display][1] = x_abcdef*4+((x-1)/3+1)*1024+y*48+display;
+
+			    /* red pixels */
+			    vfd_table[x][y][1][display][0] =
+				(x>1) ? x_abcdef*4+24+((x-1)/3)*1024+y*48+display
+				      : x_abcdef*4+24+             0+y*48+display;
+			    /* red pixels */
+			    if (x>1 && (x-1)%3)
+				    vfd_table[x][y][1][display][1] = x_abcdef*4+24+((x-1)/3+1)*1024+y*48+display;
+		    }
+		}
+	    }
+	    break;
+	default:
+	    /* do nothing */
+	    return;
+	}
+
+	/*
+	 * Create table with entries for physical byte adresses and
+	 * bit-number within the byte
+	 * from table with bit-numbers within the total framebuffer
+	 */
+	for(y=0;y<18;y++) {
+	    for(x=0;x<112;x++) {
+		for(color=0;color<2;color++) {
+		    for(display=0;display<4;display++) {
+			for(entry=0;entry<2;entry++) {
+			    unsigned long adr  = gd->fb_base;
+			    unsigned int bit_nr = 0;
+
+			    pixel  = vfd_table[x][y][color][display][entry] + frame_buf_offs;
+			    /*
+			     * wrap arround if offset
+			     * (see manual S3C2400)
+			     */
+			    if (pixel>=FRAME_BUF_SIZE*8)
+				    pixel = pixel-(FRAME_BUF_SIZE*8);
+			    adr    = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
+			    bit_nr = pixel%8;
+			    bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
+
+			    adr_vfd_table[x][y][color][display][entry] = adr;
+			    bit_vfd_table[x][y][color][display][entry] = bit_nr;
+			}
+		    }
+		}
+	    }
+	}
+}
+
+/*
+ * Set/clear pixel of the VFDs
+ */
+void set_vfd_pixel(unsigned char x, unsigned char y,
+		   unsigned char color, unsigned char display,
+		   unsigned char value)
+{
+	ulong adr;
+	unsigned char bit_nr, temp;
+
+	if (! gd->vfd_type) {
+		/* Unknown type. */
+		return;
+	}
+
+	/* Pixel-Eintrag Nr. 1 */
+	adr = adr_vfd_table[x][y][color][display][0];
+	/* Pixel-Eintrag Nr. 1 */
+	bit_nr = bit_vfd_table[x][y][color][display][0];
+	temp=(*(volatile unsigned char*)(adr));
+
+	if (value)
+		temp |=  (1<<bit_nr);
+	else
+		temp &= ~(1<<bit_nr);
+
+	(*(volatile unsigned char*)(adr))=temp;
+}
+
+/*
+ * transfer image from BMP-File
+ */
+void transfer_pic(int display, unsigned char *adr, int height, int width)
+{
+	int x, y;
+	unsigned char temp;
+
+	for (; height > 0; height -= 18)
+	{
+		if (height > 18)
+			y = 18;
+		else
+			y = height;
+		for (; y > 0; y--)
+		{
+			for (x = 0; x < width; x += 2)
+			{
+				temp = *adr++;
+				set_vfd_pixel(x, y-1, 0, display, 0);
+				set_vfd_pixel(x, y-1, 1, display, 0);
+				if ((temp >> 4) == BLAU)
+					set_vfd_pixel(x, y-1, 0, display, 1);
+				else if ((temp >> 4) == ROT)
+					set_vfd_pixel(x, y-1, 1, display, 1);
+				else if ((temp >> 4) == VIOLETT)
+				{
+					set_vfd_pixel(x, y-1, 0, display, 1);
+					set_vfd_pixel(x, y-1, 1, display, 1);
+				}
+				set_vfd_pixel(x+1, y-1, 0, display, 0);
+				set_vfd_pixel(x+1, y-1, 1, display, 0);
+				if ((temp & 0x0F) == BLAU)
+					set_vfd_pixel(x+1, y-1, 0, display, 1);
+				else if ((temp & 0x0F) == ROT)
+					set_vfd_pixel(x+1, y-1, 1, display, 1);
+				else if ((temp & 0x0F) == VIOLETT)
+				{
+					set_vfd_pixel(x+1, y-1, 0, display, 1);
+					set_vfd_pixel(x+1, y-1, 1, display, 1);
+				}
+			}
+		}
+		if (display > 0)
+			display--;
+		else
+			display = 3;
+	}
+}
+
+/*
+ * This function initializes VFD clock that is needed for the CPLD that
+ * manages the keyboard.
+ */
+int vfd_init_clocks (void)
+{
+	int i;
+
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+	struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+	struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
+
+	/* try to determine display type from the value
+	 * defined by pull-ups
+	 */
+	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pullups */
+	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */
+	/* allow signals to settle */
+	for (i=0; i<10000; i++)	/* udelay isn't working yet at this point! */
+		__asm__("NOP");
+	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
+
+	VFD_DISABLE;				/* activate blank for the vfd */
+
+#define	NEW_CPLD_CLK
+
+#ifdef NEW_CPLD_CLK
+	if (vfd_board_id) {
+		/* If new board revision, then use PWM 3 as cpld-clock */
+		/* Enable 500 Hz timer for fill level sensor to operate properly */
+		/* Configure TOUT3 as functional pin, disable pull-up */
+		gpio->pdcon &= ~0x30000;
+		gpio->pdcon |= 0x20000;
+		gpio->pdup |= (1 << 8);
+
+		/* Configure the prescaler */
+		timers->tcfg0 &= ~0xff00;
+		timers->tcfg0 |= 0x0f00;
+
+		/* Select MUX input (divider) for timer3 (1/16) */
+		timers->tcfg1 &= ~0xf000;
+		timers->tcfg1 |= 0x3000;
+
+		/* Enable autoreload and set the counter and compare
+		 * registers to values for the 500 Hz clock
+		 * (for a given  prescaler (15) and divider (16)):
+		 * counter = (66000000 / 500) >> 9;
+		 */
+		timers->ch[3].tcntb = 0x101;
+		timers->ch[3].tcmpb = 0x101 / 2;
+
+		/* Start timer */
+		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
+	}
+#endif
+	/* If old board revision, then use vm-signal as cpld-clock */
+	lcd->lcdcon2 = 0x00FFC000;
+	lcd->lcdcon3 = 0x0007FF00;
+	lcd->lcdcon4 = 0x00000000;
+	lcd->lcdcon5 = 0x00000400;
+	lcd->lcdcon1 = 0x00000B75;
+	/* VM (GPD1) is used as clock for the CPLD */
+	gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
+
+	return 0;
+}
+
+/*
+ * initialize LCD-Controller of the S3C2400 for using VFDs
+ *
+ * VFD detection depends on the board revision:
+ * starting from Rev. 200 a type code can be read from the data pins,
+ * driven by some pull-up resistors; all earlier systems must be
+ * manually configured. The type is set in the "vfd_type" environment
+ * variable.
+ */
+int drv_vfd_init(void)
+{
+	struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+	char *tmp;
+	ulong palette;
+	static int vfd_init_done = 0;
+	int vfd_inv_data = 0;
+
+	if (vfd_init_done != 0)
+		return (0);
+	vfd_init_done = 1;
+
+	debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id);
+
+	switch (vfd_board_id) {
+	case 0:			/* board revision < Rev.200 */
+		if ((tmp = getenv ("vfd_type")) == NULL) {
+			break;
+		}
+		if (strcmp(tmp, "T119C") == 0) {
+			gd->vfd_type = VFD_TYPE_T119C;
+		} else if (strcmp(tmp, "MN11236") == 0) {
+			gd->vfd_type = VFD_TYPE_MN11236;
+		} else {
+			/* cannot use printf for a warning here */
+			gd->vfd_type = 0;	/* unknown */
+		}
+
+		break;
+	default:		/* default to MN11236, data inverted */
+		gd->vfd_type = VFD_TYPE_MN11236;
+		vfd_inv_data = 1;
+		setenv ("vfd_type", "MN11236");
+	}
+	debug ("VFD type: %s%s\n",
+		(gd->vfd_type == VFD_TYPE_T119C)   ? "T119C" :
+		(gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" :
+		"unknown",
+		vfd_inv_data ? ", inverted data" : "");
+
+	gd->fb_base = gd->fb_base;
+	create_vfd_table();
+	init_grid_ctrl();
+
+	for (palette=0; palette < 16; palette++)
+		(*(volatile unsigned int*)(PALETTE+(palette*4)))=palette;
+	for (palette=16; palette < 256; palette++)
+		(*(volatile unsigned int*)(PALETTE+(palette*4)))=0x00;
+
+	/*
+	 * Hinweis: Der Framebuffer ist um genau ein Nibble verschoben
+	 * Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt
+	 * das letzte angezeigte Pixel wird aus dem ersten Nibble geholt
+	 * (wrap around)
+	 * see manual S3C2400
+	 */
+	/* Stopp LCD-Controller */
+	lcd->lcdcon1 = 0x00000000;
+	/* frame buffer startadr */
+	lcd->lcdsaddr1 = gd->fb_base >> 1;
+	/* frame buffer endadr */
+	lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+	lcd->lcdsaddr3 = ((256/4));
+	lcd->lcdcon2 = 0x000DC000;
+	if(gd->vfd_type == VFD_TYPE_MN11236)
+		lcd->lcdcon2 = 37 << 14;	/* MN11236: 38 lines */
+	else
+		lcd->lcdcon2 = 55 << 14;	/* T119C:   56 lines */
+	lcd->lcdcon3 = 0x0051000A;
+	lcd->lcdcon4 = 0x00000001;
+	if (gd->vfd_type && vfd_inv_data)
+		lcd->lcdcon5 = 0x000004C0;
+	else
+		lcd->lcdcon5 = 0x00000440;
+
+	/* Port pins as LCD output */
+	gpio->pccon =   (gpio->pccon & 0xFFFFFF00) | 0x000000AA;
+	gpio->pdcon =   (gpio->pdcon & 0xFFFFFF03) | 0x000000A8;
+
+	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
+	lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller	*/
+	while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */
+		;
+	while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */
+		;
+	while ((lcd->lcdcon5 & 0x060000) == 0x040000)
+		;
+	while ((lcd->lcdcon5 & 0x060000) != 0x000000)
+		;
+	if(gd->vfd_type)
+		VFD_ENABLE;
+
+	debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
+	debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
+	debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
+
+	return 0;
+}
+
+/*
+ * Disable VFD: should be run before resetting the system:
+ * disable VM, enable pull-up
+ */
+void disable_vfd (void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	VFD_DISABLE;
+	gpio->pdcon &= ~0xC;
+	gpio->pdup  &= ~0x2;
+}
+
+/************************************************************************/
+/* ** ROM capable initialization part - needed to reserve FB memory	*/
+/************************************************************************/
+
+/*
+ * This is called early in the system initialization to grab memory
+ * for the VFD controller.
+ *
+ * Note that this is running from ROM, so no write access to global data.
+ */
+ulong vfd_setmem (ulong addr)
+{
+	ulong size;
+
+	/* Round up to nearest full page */
+	size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+
+	debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr);
+
+	return (size);
+}
+
+/*
+ * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
+ * descriptors and palette areas.
+ */
+ulong calc_fbsize (void)
+{
+	return FRAME_BUF_SIZE;
+}
+
+#endif /* CONFIG_VFD */
diff --git a/u-boot/board/trizepsiv/Makefile b/u-boot/board/trizepsiv/Makefile
new file mode 100644
index 0000000..eac00ae
--- /dev/null
+++ b/u-boot/board/trizepsiv/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= conxs.o eeprom.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/trizepsiv/conxs.c b/u-boot/board/trizepsiv/conxs.c
new file mode 100644
index 0000000..99f665b
--- /dev/null
+++ b/u-boot/board/trizepsiv/conxs.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+#if CONFIG_MK_POLARIS
+#define BOOT_CONSOLE	"serial_stuart"
+#else
+#define BOOT_CONSOLE	"serial_ffuart"
+#endif
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int usb_board_init(void)
+{
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+	writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	return 0;
+}
+
+void usb_board_init_fail(void)
+{
+	return;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of ConXS Board */
+	gd->bd->bi_arch_number = 776;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_SERIAL_MULTI)
+	char *console=getenv("boot_console");
+
+	if ((console == NULL) || (strcmp(console,"serial_btuart") &&
+		strcmp(console,"serial_stuart") &&
+		strcmp(console,"serial_ffuart"))) {
+			console = BOOT_CONSOLE;
+	}
+	setenv("stdout",console);
+	setenv("stdin", console);
+	setenv("stderr",console);
+#endif
+	return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+	return &serial_ffuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/trizepsiv/eeprom.c b/u-boot/board/trizepsiv/eeprom.c
new file mode 100644
index 0000000..fd623df
--- /dev/null
+++ b/u-boot/board/trizepsiv/eeprom.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm9000.h>
+
+static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+	unsigned int i;
+	u8 data[2];
+
+	for (i=0; i < 0x40; i++) {
+		if (!(i % 0x10))
+			printf("\n%08x:", i);
+		dm9000_read_srom_word(i, data);
+		printf(" %02x%02x", data[1], data[0]);
+	}
+	printf ("\n");
+	return (0);
+}
+
+static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+	int offset,value;
+
+	if (argc < 4)
+		return cmd_usage(cmdtp);
+
+	offset=simple_strtoul(argv[2],NULL,16);
+	value=simple_strtoul(argv[3],NULL,16);
+	if (offset > 0x40) {
+		printf("Wrong offset : 0x%x\n",offset);
+		return cmd_usage(cmdtp);
+	}
+	dm9000_write_srom_word(offset, value);
+	return (0);
+}
+
+int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	if (strcmp (argv[1],"read") == 0)
+		return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
+	else if (strcmp (argv[1],"write") == 0)
+		return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
+	else
+		return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	dm9000ee,4,1,do_dm9000_eeprom,
+	"Read/Write eeprom connected to Ethernet Controller",
+	"\ndm9000ee write <word offset> <value> \n"
+	"\tdm9000ee read \n"
+	"\tword:\t\t00-02 : MAC Address\n"
+	"\t\t\t03-07 : DM9000 Configuration\n"
+	"\t\t\t08-63 : User data"
+);
diff --git a/u-boot/board/ttcontrol/vision2/Makefile b/u-boot/board/ttcontrol/vision2/Makefile
new file mode 100644
index 0000000..9ed8246
--- /dev/null
+++ b/u-boot/board/ttcontrol/vision2/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= vision2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ttcontrol/vision2/config.mk b/u-boot/board/ttcontrol/vision2/config.mk
new file mode 100644
index 0000000..952037e
--- /dev/null
+++ b/u-boot/board/ttcontrol/vision2/config.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
+ALL += $(obj)u-boot.imx
diff --git a/u-boot/board/ttcontrol/vision2/imximage_hynix.cfg b/u-boot/board/ttcontrol/vision2/imximage_hynix.cfg
new file mode 100644
index 0000000..ed531db
--- /dev/null
+++ b/u-boot/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -0,0 +1,209 @@
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# (C) Copyright 2010
+# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, nand, onenand, sd
+
+BOOT_FROM	spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+#######################
+### Disable WDOG ###
+#######################
+DATA 2 0x73f98000 0x30
+
+#######################
+### SET DDR Clk     ###
+#######################
+
+# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+DATA 4 0x73FD4018 0x000024C0
+
+# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+DATA 4 0x73FD4038 0x2010241
+
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8600 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8604 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8608 0x00000187
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa860c 0x00000187
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8614 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+DATA 4 0x73fa86a8 0x00000187
+
+#######################
+### Settings IOMUXC ###
+#######################
+
+# DDR IOMUX configuration
+# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+DATA 4 0x73fa84b8 0x000000e7
+# PVTC MAX (at GPC, PGR reg)
+#DATA 4 0x73FD8004 0x1fc00000
+
+#DQM0 DS high slew rate slow
+DATA 4 0x73fa84d4 0x000000e4
+#DQM1 DS high slew rate slow
+DATA 4 0x73fa84d8 0x000000e4
+#DQM2 DS high slew rate slow
+DATA 4 0x73fa84dc 0x000000e4
+#DQM3 DS high slew rate slow
+DATA 4 0x73fa84e0 0x000000e4
+
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+DATA 4 0x73fa84bc 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+DATA 4 0x73fa84c0 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+DATA 4 0x73fa84c4 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+DATA 4 0x73fa84c8 0x000000c4
+
+#DRAM_DATA B0
+DATA 4 0x73fa88a4 0x00000004
+#DRAM_DATA B1
+DATA 4 0x73fa88ac 0x00000004
+#DRAM_DATA B2
+DATA 4 0x73fa88b8 0x00000004
+#DRAM_DATA B3
+DATA 4 0x73fa882c 0x00000004
+
+#DRAM_DATA B0 slew rate
+DATA 4 0x73fa8878 0x00000000
+#DRAM_DATA B1 slew rate
+DATA 4 0x73fa8880 0x00000000
+#DRAM_DATA B2 slew rate
+DATA 4 0x73fa888c 0x00000000
+#DRAM_DATA B3 slew rate
+DATA 4 0x73fa889c 0x00000000
+
+#######################
+### Configure SDRAM ###
+#######################
+
+# Configure CS0
+#######################
+
+# ESDCTL0: Enable controller
+DATA 4 0x83fd9000 0x83220000
+
+# Init DRAM on CS0
+# ESDSCR: Precharge command
+DATA 4 0x83fd9014 0x04008008
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008010
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008010
+# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DATA 4 0x83fd9014 0x00338018
+# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+DATA 4 0x83fd9014 0x0020801a
+# ESDSCR
+DATA 4 0x83fd9014 0x00008000
+
+# ESDSCR: EMR with full Drive strength
+#DATA 4 0x83fd9014 0x0000801a
+
+# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+DATA 4 0x83fd9000 0xC3220000
+
+# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+#          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+#DATA 4 0x83fd9004 0xC33574AA
+
+#micron mDDR
+# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+#DATA 4 0x83FD9004 0x101564a8
+
+#hynix mDDR
+# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+DATA 4 0x83FD9004 0x704564a8
+
+# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+DATA 4 0x83fd9010 0x000a1700
+
+# Configure CS1
+#######################
+
+# ESDCTL1: Enable controller
+DATA 4 0x83fd9008 0x83220000
+
+# Init DRAM on CS1
+# ESDSCR: Precharge command
+DATA 4 0x83fd9014 0x0400800c
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008014
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008014
+# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DATA 4 0x83fd9014 0x0033801c
+# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+DATA 4 0x83fd9014 0x0020801e
+# ESDSCR
+DATA 4 0x83fd9014 0x00008004
+
+# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+DATA 4 0x83fd9008 0xC3220000
+
+# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+#          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+#DATA 4 0x83fd900c 0xC33574AA
+
+#micron mDDR
+# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+#DATA 4 0x83FD900C 0x101564a8
+
+#hynix mDDR
+# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+DATA 4 0x83FD900C 0x704564a8
+
+# ESDSCR (mDRAM configuration finished)
+DATA 4 0x83FD9014 0x00000004
+
+# ESDSCR - clear "configuration request" bit
+DATA 4 0x83fd9014 0x00000000
diff --git a/u-boot/board/ttcontrol/vision2/vision2.c b/u-boot/board/ttcontrol/vision2/vision2.c
new file mode 100644
index 0000000..f8ef4fc
--- /dev/null
+++ b/u-boot/board/ttcontrol/vision2/vision2.c
@@ -0,0 +1,765 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <mxc_gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <linux/fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+extern int mx51_fb_init(struct fb_videomode *mode);
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+static struct fb_videomode nec_nl6448bc26_09c = {
+	"NEC_NL6448BC26-09C",
+	60,	/* Refresh */
+	640,	/* xres */
+	480,	/* yres */
+	37650,	/* pixclock = 26.56Mhz */
+	48,	/* left margin */
+	16,	/* right margin */
+	31,	/* upper margin */
+	12,	/* lower margin */
+	96,	/* hsync-len */
+	2,	/* vsync-len */
+	0,	/* sync */
+	FB_VMODE_NONINTERLACED,	/* vmode */
+	0,	/* flag */
+};
+
+void hw_watchdog_reset(void)
+{
+	int val;
+
+	/* toggle watchdog trigger pin */
+	val = mxc_gpio_get(66);
+	val = val ? 0 : 1;
+	mxc_gpio_set(66, val);
+}
+#endif
+
+static void init_drive_strength(void)
+{
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+
+	/* Setting pad options */
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+
+u32 get_board_rev(void)
+{
+	system_rev = get_cpu_rev();
+
+	return system_rev;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+static void setup_weim(void)
+{
+	struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
+
+	pweim->csgcr1 = 0x004100b9;
+	pweim->csgcr2 = 0x00000001;
+	pweim->csrcr1 = 0x0a018000;
+	pweim->csrcr2 = 0;
+	pweim->cswcr1 = 0x0704a240;
+}
+
+static void setup_uart(void)
+{
+	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+			 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+	/* console RX on Pin EIM_D25 */
+	mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
+	/* console TX on Pin EIM_D26 */
+	mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
+}
+
+#ifdef CONFIG_MXC_SPI
+void spi_io_init(void)
+{
+	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/*
+	 * SS1 will be used as GPIO because of uninterrupted
+	 * long SPI transmissions (GPIO4_25)
+	 */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
+	mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+}
+
+static void reset_peripherals(int reset)
+{
+	if (reset) {
+
+		/* reset_n is on NANDF_D15 */
+		mxc_gpio_set(89, 0);
+		mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
+
+#ifdef CONFIG_VISION2_HW_1_0
+		/*
+		 * set FEC Configuration lines
+		 * set levels of FEC config lines
+		 */
+		mxc_gpio_set(75, 0);
+		mxc_gpio_set(74, 1);
+		mxc_gpio_set(95, 1);
+		mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
+
+		/* set direction of FEC config lines */
+		mxc_gpio_set(59, 0);
+		mxc_gpio_set(60, 0);
+		mxc_gpio_set(61, 0);
+		mxc_gpio_set(55, 1);
+		mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
+
+		/* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
+		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
+		/* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
+		/* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
+		/* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
+		/* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
+		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
+		/* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
+		/* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
+		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
+#endif
+
+		/*
+		 * activate reset_n pin
+		 * Select mux mode: ALT3 mux port: NAND D15
+		 */
+		mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
+			PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
+	} else {
+		/* set FEC Control lines */
+		mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
+		udelay(500);
+
+#ifdef CONFIG_VISION2_HW_1_0
+		/* FEC RDATA[3] */
+		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+		/* FEC RDATA[2] */
+		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+		/* FEC RDATA[1] */
+		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+		/* FEC RDATA[0] */
+		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+		/* FEC RX_CLK */
+		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+		/* FEC RX_ER */
+		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+		/* FEC COL */
+		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+#endif
+	}
+}
+
+static void power_init_mx51(void)
+{
+	unsigned int val;
+
+	/* Write needed to Power Gate 2 register */
+	val = pmic_reg_read(REG_POWER_MISC);
+
+	/* enable VCAM with 2.775V to enable read from PMIC */
+	val = VCAMCONFIG | VCAMEN;
+	pmic_reg_write(REG_MODE_1, val);
+
+	/*
+	 * Set switchers in Auto in NORMAL mode & STANDBY mode
+	 * Setup the switcher mode for SW1 & SW2
+	 */
+	val = pmic_reg_read(REG_SW_4);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	pmic_reg_write(REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	val = pmic_reg_read(REG_SW_5);
+	val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+		(SWMODE_MASK << SWMODE3_SHIFT));
+	val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+	pmic_reg_write(REG_SW_5, val);
+
+
+	/* Set VGEN3 to 1.8V, VCAM to 3.0V */
+	val = pmic_reg_read(REG_SETTING_0);
+	val &= ~(VCAM_MASK | VGEN3_MASK);
+	val |= VCAM_3_0;
+	pmic_reg_write(REG_SETTING_0, val);
+
+	/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
+	val = pmic_reg_read(REG_SETTING_1);
+	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+	val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
+	pmic_reg_write(REG_SETTING_1, val);
+
+	/* Configure VGEN3 and VCAM regulators to use external PNP */
+	val = VGEN3CONFIG | VCAMCONFIG;
+	pmic_reg_write(REG_MODE_1, val);
+	udelay(200);
+
+	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+		VVIDEOEN | VAUDIOEN  | VSDEN;
+	pmic_reg_write(REG_MODE_1, val);
+
+	val = pmic_reg_read(REG_POWER_CTL2);
+	val |= WDIRESET;
+	pmic_reg_write(REG_POWER_CTL2, val);
+
+	udelay(2500);
+
+}
+#endif
+
+static void setup_gpios(void)
+{
+	unsigned int i;
+
+	/* CAM_SUP_DISn, GPIO1_7 */
+	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
+
+	/* DAB Display EN, GPIO3_1 */
+	mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
+
+	/* WDOG_TRIGGER, GPIO3_2 */
+	mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
+
+	/* Now we need to trigger the watchdog */
+	WATCHDOG_RESET();
+
+	/* Display2 TxEN, GPIO3_3 */
+	mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
+
+	/* DAB Light EN, GPIO3_4 */
+	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
+
+	/* AUDIO_MUTE, GPIO3_5 */
+	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
+
+	/* SPARE_OUT, GPIO3_6 */
+	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
+
+	/* BEEPER_EN, GPIO3_26 */
+	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
+
+	/* POWER_OFF, GPIO3_27 */
+	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
+
+	/* FRAM_WE, GPIO3_30 */
+	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
+
+	/* EXPANSION_EN, GPIO4_26 */
+	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
+
+	/* PWM Output GPIO1_2 */
+	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+
+	/*
+	 * Set GPIO1_4 to high and output; it is used to reset
+	 * the system on reboot
+	 */
+	mxc_gpio_set(4, 1);
+	mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(7, 0);
+	mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
+	for (i = 65; i < 71; i++) {
+		mxc_gpio_set(i, 0);
+		mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
+	}
+
+	mxc_gpio_set(94, 0);
+	mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
+
+	/* Set POWER_OFF high */
+	mxc_gpio_set(91, 1);
+	mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(90, 0);
+	mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(122, 0);
+	mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(121, 1);
+	mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
+
+	WATCHDOG_RESET();
+}
+
+static void setup_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
+
+	/* FEC RDATA[3] */
+	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+	/* FEC RDATA[2] */
+	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+	/* FEC RDATA[1] */
+	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+	/* FEC RDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+	/* FEC TDATA[3] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
+
+	/* FEC TDATA[2] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
+
+	/* FEC TDATA[1] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
+
+	/* FEC TDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
+
+	/* FEC TX_ER */
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
+
+	/* FEC TX_COL */
+	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+
+	/* FEC RX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+	/* FEC RX_CRS */
+	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+	/* FEC RX_DV */
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+}
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+};
+
+int get_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = mxc_gpio_get(0);
+	else
+		*cd = 0;
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bis)
+{
+	mxc_request_iomux(MX51_PIN_SD1_CMD,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_CLK,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA0,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA1,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA2,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA3,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_GPIO1_0,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+		PAD_CTL_HYS_ENABLE);
+	mxc_request_iomux(MX51_PIN_GPIO1_1,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+		PAD_CTL_HYS_ENABLE);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+
+
+	init_drive_strength();
+
+	/* Setup debug led */
+	mxc_gpio_set(6, 0);
+	mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
+	mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* wait a little while to give the pll time to settle */
+	sdelay(100000);
+
+	setup_weim();
+	setup_uart();
+	setup_fec();
+	setup_gpios();
+
+	spi_io_init();
+
+	return 0;
+}
+
+static void backlight(int on)
+{
+	if (on) {
+		mxc_gpio_set(65, 1);
+		udelay(10000);
+		mxc_gpio_set(68, 1);
+	} else {
+		mxc_gpio_set(65, 0);
+		mxc_gpio_set(68, 0);
+	}
+}
+
+void lcd_enable(void)
+{
+	int ret;
+
+	mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+
+	mxc_gpio_set(2, 1);
+	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+
+	ret = mx51_fb_init(&nec_nl6448bc26_09c);
+	if (ret)
+		puts("LCD cannot be configured\n");
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2;	/* board id for linux */
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	power_init_mx51();
+
+	reset_peripherals(1);
+	udelay(2000);
+	reset_peripherals(0);
+	udelay(2000);
+
+	/* Early revisions require a second reset */
+#ifdef CONFIG_VISION2_HW_1_0
+	reset_peripherals(1);
+	udelay(2000);
+	reset_peripherals(0);
+	udelay(2000);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 system_rev = get_cpu_rev();
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	puts("Board: TTControl Vision II CPU V");
+
+	switch (system_rev & 0xff) {
+	case CHIP_REV_3_0:
+		puts("3.0 [");
+		break;
+	case CHIP_REV_2_5:
+		puts("2.5 [");
+		break;
+	case CHIP_REV_2_0:
+		puts("2.0 [");
+		break;
+	case CHIP_REV_1_1:
+		puts("1.1 [");
+		break;
+	case CHIP_REV_1_0:
+	default:
+		puts("1.0 [");
+		break;
+	}
+
+	cause = src_regs->srsr;
+	switch (cause) {
+	case 0x0001:
+		puts("POR");
+		break;
+	case 0x0009:
+		puts("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		puts("WDOG");
+		break;
+	default:
+		printf("unknown 0x%x", cause);
+	}
+	puts("]\n");
+
+	return 0;
+}
+
+int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int on;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	on = (strcmp(argv[1], "on") == 0);
+	backlight(on);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
+	"Vision2 Backlight",
+	"lcdbl [on|off]\n"
+);
diff --git a/u-boot/board/utx8245/Makefile b/u-boot/board/utx8245/Makefile
new file mode 100644
index 0000000..33c1dcd
--- /dev/null
+++ b/u-boot/board/utx8245/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Gregory E. Allen, gallen@arlut.utexas.edu
+# Matthew E. Karger, karger@arlut.utexas.edu
+# Applied Research Laboratories, The University of Texas at Austin
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/utx8245/flash.c b/u-boot/board/utx8245/flash.c
new file mode 100644
index 0000000..aac8116
--- /dev/null
+++ b/u-boot/board/utx8245/flash.c
@@ -0,0 +1,560 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+#define	FLASH_BANK_SIZE	((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
+#define	MAIN_SECT_SIZE	0x10000
+#define	SECT_SIZE_32KB	0x8000
+#define	SECT_SIZE_8KB	0x2000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+#if 0
+static void write_via_fpu (vu_long * addr, ulong * data);
+#endif
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);
+
+/*flash command address offsets*/
+#define ADDR0		(0x555)
+#define ADDR1		(0xAAA)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*---------------------------------------------------------------------*/
+/*#define	DEBUG_FLASH	1 */
+
+/*---------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+	int i;		/* flash bank counter */
+	int j;		/* flash device sector counter */
+	int k;		/* flash size calculation loop counter */
+	int N;		/* pow(2,N) is flash size, but we don't have <math.h> */
+	ulong total_size = 0, device_size = 1;
+	unsigned char manuf_id, device_id;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		vu_char *addr = (vu_char *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0x555] = 0xAA;		/* get manuf/device info command */
+		addr[0x2AA] = 0x55;		/* 3-cycle command */
+		addr[0x555] = 0x90;
+
+		manuf_id = addr[0];		/* read back manuf/device info */
+		device_id = addr[1];
+
+		addr[0x55] = 0x98;		/* CFI command */
+		N = addr[0x27];			/* read back device_size = pow(2,N) */
+
+		for (k = 0; k < N; k++)	/* calculate device_size = pow(2,N) */
+			device_size *= 2;
+
+		flash_info[i].size = device_size;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+
+#if defined DEBUG_FLASH
+		printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id);
+#endif
+		/* find out what kind of flash we are using */
+		if ((manuf_id == (uchar) (AMD_MANUFACT))
+			&& (device_id == AMD_ID_LV033C)) {
+			flash_info[i].flash_id =
+					((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
+					(FLASH_AM033C & FLASH_TYPEMASK);
+
+			/* set individual sector start addresses */
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				flash_info[i].start[j] =
+						(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
+						 j * MAIN_SECT_SIZE);
+			}
+		}
+
+		else if ((manuf_id == (uchar) (AMD_MANUFACT)) &&
+				 (device_id == AMD_ID_LV116DT)) {
+			flash_info[i].flash_id =
+					((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
+					(FLASH_AM160T & FLASH_TYPEMASK);
+
+			/* set individual sector start addresses */
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				flash_info[i].start[j] =
+						(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
+						 j * MAIN_SECT_SIZE);
+
+				if (j < (CONFIG_SYS_MAX_FLASH_SECT - 3)) {
+					flash_info[i].start[j] =
+							(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
+							 j * MAIN_SECT_SIZE);
+				} else if (j == (CONFIG_SYS_MAX_FLASH_SECT - 3)) {
+					flash_info[i].start[j] =
+							(flash_info[i].start[j - 1] + SECT_SIZE_32KB);
+
+				} else {
+					flash_info[i].start[j] =
+							(flash_info[i].start[j - 1] + SECT_SIZE_8KB);
+				}
+			}
+		}
+
+		else {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFF;
+			goto Done;
+		}
+
+#if defined DEBUG_FLASH
+		printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+#endif
+
+		addr[0] = 0xFF;
+
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+
+		total_size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				   CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+				   &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+	flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+  Done:
+	return total_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM033C:
+			type = "AM29LV033C (32 Mbit, uniform sector size)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+			"  Size: %lu KB in %d Sectors\n",
+			mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+				(info->start[i + 1] - info->start[i]) >> 2 :
+				(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+			 (flash != (unsigned long *) info->start[i] + size) && erased;
+			 flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+				(i % 5) ? "" : "\n   ",
+				info->start[i],
+				erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+		(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+		&& (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
+														   start[sect] -
+														   info->
+														   start[0]) <<
+														  sh8b));
+
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else {
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+												   info->
+												   start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+		   (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+		&& (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+								 info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+			   (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void write_via_fpu (vu_long * addr, ulong * data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+}
diff --git a/u-boot/board/utx8245/utx8245.c b/u-boot/board/utx8245/utx8245.c
new file mode 100644
index 0000000..8402689
--- /dev/null
+++ b/u-boot/board/utx8245/utx8245.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <netdev.h>
+
+#define	SAVE_SZ	32
+
+
+int checkboard(void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+}
+
+
+phys_size_t initdram(int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long new_bank1_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+	new_bank0_end = size/2 - 1;
+	new_bank1_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+
+	mear1 = (mear1  & 0xFFFF0000) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+		((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8);
+	emear1 = (emear1 & 0xFFFF0000) |
+		((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+		((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
+
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+static struct pci_config_table pci_utx8245_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
+				       PCI_FIREWIRE_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
+	{ }
+};
+
+
+static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	if (PCI_DEV(dev) == 11)
+		/* assign serial interrupt line 9 (int25) to FireWire */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
+
+	else if (PCI_DEV(dev) == 12)
+		/* assign serial interrupt line 8 (int24) to Ethernet */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
+
+	else if (PCI_DEV(dev) == 14)
+		/* assign serial interrupt line 0 (int16) to PMC slot 0 */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
+
+	else if (PCI_DEV(dev) == 15)
+		/* assign serial interrupt line 1 (int17) to PMC slot 1 */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
+}
+
+static struct pci_controller utx8245_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_utx8245_config_table,
+	fixup_irq: pci_utx8245_fixup_irq,
+	write_byte: pci_hose_write_config_byte
+#endif /*CONFIG_PCI_PNP*/
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init(&utx8245_hose);
+
+	icache_enable();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/u-boot/board/v37/Makefile b/u-boot/board/v37/Makefile
new file mode 100644
index 0000000..9b00eb0
--- /dev/null
+++ b/u-boot/board/v37/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/v37/flash.c b/u-boot/board/v37/flash.c
new file mode 100644
index 0000000..9b817ec
--- /dev/null
+++ b/u-boot/board/v37/flash.c
@@ -0,0 +1,559 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ *	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips);
+static void flash_get_id_word( void *ptr,  short *ptr_manuf, short *ptr_dev_id);
+static void flash_get_id_long( void *ptr,  short *ptr_manuf, short *ptr_dev_id);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	short manu, dev_id;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Do sizing to get full correct info */
+
+	flash_get_id_word((void*)CONFIG_SYS_FLASH_BASE0,&manu,&dev_id);
+
+	size_b0 = flash_get_size(manu, dev_id, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE0, &flash_info[0],0);
+
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id);
+
+	size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]);
+
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1);
+
+	memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1);
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0+size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips)
+{
+	int i, addr_shift;
+	vu_short *addr = (vu_short*)base;
+
+	addr[0x555] = 0x00AA ;
+	addr[0xAAA] = 0x0055 ;
+	addr[0x555] = 0x0090 ;
+
+	addr_shift = (two_chips ? 2 : 1 );
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + (0x00000000<<addr_shift);
+		info->start[1] = base + (0x00002000<<addr_shift);
+		info->start[2] = base + (0x00003000<<addr_shift);
+		info->start[3] = base + (0x00004000<<addr_shift);
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * (0x00008000<<addr_shift)) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - (0x00002000<<addr_shift);
+		info->start[i--] = base + info->size - (0x00003000<<addr_shift);
+		info->start[i--] = base + info->size - (0x00004000<<addr_shift);
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * (0x00008000<<addr_shift);
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (vu_short *)(info->start[i]);
+		info->protect[i] = addr[1<<addr_shift] & 1 ;
+	}
+
+	addr = (vu_short *)info->start[0];
+	*addr = 0xF0F0;	/* reset bank */
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_TOSH:	printf ("TOSHIBA ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static void flash_get_id_word( void *ptr,  short *ptr_manuf, short *ptr_dev_id)
+{
+	vu_short *addr = (vu_short*)ptr;
+
+	addr[0x555] = 0x00AA ;
+	addr[0xAAA] = 0x0055 ;
+	addr[0x555] = 0x0090 ;
+
+	*ptr_manuf  = addr[0];
+	*ptr_dev_id = addr[1];
+
+	addr[0] = 0xf0f0;       /* return to normal */
+}
+
+static void flash_get_id_long( void *ptr,  short *ptr_manuf, short *ptr_dev_id)
+{
+	vu_short *addr = (vu_short*)ptr;
+	vu_short *addr1, *addr2, *addr3;
+
+	addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
+	addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) );
+	addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
+
+	*addr1 = 0xAAAA;
+	*addr2 = 0x5555;
+	*addr3 = 0x9090;
+
+	*ptr_manuf  = addr[0];
+	*ptr_dev_id = addr[2];
+
+	addr[0] = 0xf0f0;       /* return to normal */
+}
+
+static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info)
+{
+	switch (manu) {
+	case ((short)AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case ((short)FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case ((short)TOSH_MANUFACT):
+		info->flash_id = FLASH_MAN_TOSH;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+
+	switch (dev_id) {
+	case ((short)TOSH_ID_FVT160):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 1 MB		*/
+
+	case ((short)TOSH_ID_FVB160):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 1 MB		*/
+
+	case ((short)AMD_ID_LV400T):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case ((short)AMD_ID_LV400B):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case ((short)AMD_ID_LV800T):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case ((short)AMD_ID_LV800B):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/*%%% Size doubled by yooth */
+		break;				/* => 4 MB		*/
+
+	case ((short)AMD_ID_LV160T):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 4 MB		*/
+
+	case ((short)AMD_ID_LV160B):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 4 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x555] = (vu_short)0xAAAAAAAA;
+	addr[0xAAA] = (vu_short)0x55555555;
+	addr[0x555] = (vu_short)0x80808080;
+	addr[0x555] = (vu_short)0xAAAAAAAA;
+	addr[0xAAA] = (vu_short)0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short *)(info->start[sect]) ;
+			addr[0] = (vu_short)0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_short *)(info->start[l_sect]);
+	while ((addr[0] & 0x8080) != 0x8080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short *)info->start[0];
+	addr[0] = (vu_short)0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short *)(info->start[0]);
+	vu_short sdata;
+
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* First write upper 16 bits */
+	sdata = (short)(data>>16);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x555] = 0xAAAA;
+	addr[0xAAA] = 0x5555;
+	addr[0x555] = 0xA0A0;
+
+	*((vu_short *)dest) = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+	/* Now write lower 16 bits */
+	sdata = (short)(data&0xffff);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x555] = 0xAAAA;
+	addr[0xAAA] = 0x5555;
+	addr[0x555] = 0xA0A0;
+
+	*((vu_short *)dest + 1) = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/v37/u-boot.lds b/u-boot/board/v37/u-boot.lds
new file mode 100644
index 0000000..9f36f53
--- /dev/null
+++ b/u-boot/board/v37/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2003-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/v37/v37.c b/u-boot/board/v37/v37.c
new file mode 100644
index 0000000..9c7bad5
--- /dev/null
+++ b/u-boot/board/v37/v37.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * DRAM related UPMA register values are modified.
+ * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define MBYTE		(1024*1024)
+#define DRAM_DELAY	0x00000379  /* DRAM delay count */
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*  single read. (offset 0 in upm RAM) */
+	0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
+	0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
+
+	/* burst read. (Offset 8 in upm RAM)   */
+	0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
+	0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* single write. (Offset 0x18 in upm RAM) */
+	0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*  burst write. (Offset 0x20 in upm RAM) */
+	0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
+	0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh cycle, offset 0x30 */
+	0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception, 0ffset 0x3C */
+	0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 for now.
+ *
+ */
+
+int checkboard (void)
+{
+	printf("Marel V37\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    unsigned long temp;
+    volatile int delay_cnt;
+    long int ramsize;
+
+    ramsize = dram_size();
+
+	/* Refresh clock prescalar */
+    memctl->memc_mptpr = 0x400 ;
+
+    if( ramsize == 32*MBYTE )
+       temp = 0xd0904110;
+   else				/* 16MB */
+       temp = 0xd0802110;
+
+    memctl->memc_mbmr = temp;
+
+    upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Map controller banks 2 to the SDRAM bank */
+    memctl->memc_or2 = 0xA00 | (0 - ramsize);
+    memctl->memc_br2 = 0xC1;
+
+    memctl->memc_mbmr = temp | 0x08;
+    memctl->memc_mcr  = 0x80804130;
+
+    delay_cnt = 0;
+    while( delay_cnt++ < DRAM_DELAY )
+	;
+
+    /* Run MRS command in location 5-8 of UPMB */
+
+    memctl->memc_mbmr = temp | 0x04;
+    memctl->memc_mar  = 0x88;
+
+    memctl->memc_mcr  = 0x80804105;
+
+    delay_cnt = 0;
+    while( delay_cnt++ < DRAM_DELAY )
+	;
+
+#ifdef	CONFIG_CAN_DRIVER
+    /* Initialize OR3 / BR3 */
+    memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+    memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
+
+    /* Initialize MBMR */
+    memctl->memc_mamr = MAMR_GPL_A4DIS;	/* GPL_A4 ouput line Disable */
+
+    /* Initialize UPMB for CAN: single read */
+    memctl->memc_mdr = 0xFFFFC004;
+    memctl->memc_mcr = 0x0100 | UPMA;
+
+    memctl->memc_mdr = 0x0FFFD004;
+    memctl->memc_mcr = 0x0101 | UPMA;
+
+    memctl->memc_mdr = 0x0FFFC000;
+    memctl->memc_mcr = 0x0102 | UPMA;
+
+    memctl->memc_mdr = 0x3FFFC004;
+    memctl->memc_mcr = 0x0103 | UPMA;
+
+    memctl->memc_mdr = 0xFFFFDC05;
+    memctl->memc_mcr = 0x0104 | UPMA;
+
+    /* Initialize UPMB for CAN: single write */
+    memctl->memc_mdr = 0xFFFCC004;
+    memctl->memc_mcr = 0x0118 | UPMA;
+
+    memctl->memc_mdr = 0xCFFCD004;
+    memctl->memc_mcr = 0x0119 | UPMA;
+
+    memctl->memc_mdr = 0x0FFCC000;
+    memctl->memc_mcr = 0x011A | UPMA;
+
+    memctl->memc_mdr = 0x7FFCC004;
+    memctl->memc_mcr = 0x011B | UPMA;
+
+    memctl->memc_mdr = 0xFFFDCC05;
+    memctl->memc_mcr = 0x011C | UPMA;
+#endif	/* CONFIG_CAN_DRIVER */
+
+    return (dram_size());
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Find size of RAM from configuration pins.
+ * The input pins that contain the memory size are also the debug port
+ * pins.  Normally they are configured as debug port pins.  To be able
+ * to read the memory configuration, we must deactivate the debug port
+ * and enable the pcmcia input pins.  Then return the register to
+ * previous state.
+ */
+
+static long int dram_size ()
+{
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+    volatile sysconf8xx_t *siu = &immap->im_siu_conf;
+    volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
+    long int		  i, memory=1;
+    unsigned long siu_mcr;
+
+    siu_mcr = siu->sc_siumcr;
+    siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
+    for(i=0; i<10; i++) i = i;
+
+    memory = (pcm->pcmc_pipr>>12) & 0x3;
+
+    siu->sc_siumcr = siu_mcr;
+
+    switch( memory )
+    {
+	case 1:
+	    return( 32*MBYTE );
+	case 2:
+	    return( 64*MBYTE );
+	default:
+	    break;
+    }
+    return( 16*MBYTE );
+}
diff --git a/u-boot/board/v38b/Makefile b/u-boot/board/v38b/Makefile
new file mode 100644
index 0000000..d463db4
--- /dev/null
+++ b/u-boot/board/v38b/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/v38b/ethaddr.c b/u-boot/board/v38b/ethaddr.c
new file mode 100644
index 0000000..4e2494e
--- /dev/null
+++ b/u-boot/board/v38b/ethaddr.c
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+/* For the V38B board the pin is GPIO_PSC_6 */
+#define GPIO_PIN	GPIO_PSC6_0
+
+#define NO_ERROR	0
+#define ERR_NO_NUMBER	1
+#define ERR_BAD_NUMBER	2
+
+static int is_high(void);
+static int check_device(void);
+static void io_out(int value);
+static void io_input(void);
+static void io_output(void);
+static void init_gpio(void);
+static void read_byte(unsigned char *data);
+static void write_byte(unsigned char command);
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr);
+void board_get_enetaddr(uchar *enetaddr);
+
+
+static int is_high()
+{
+	return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
+}
+
+static void io_out(int value)
+{
+	if (value)
+		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
+	else
+		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
+}
+
+static void io_input()
+{
+	*((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
+	udelay(3);	/* allow input to settle */
+}
+
+static void io_output()
+{
+	*((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
+}
+
+static void init_gpio()
+{
+	*((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN;	/* Enable appropriate pin */
+}
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr)
+{
+#define NBYTES 28
+	unsigned char crcval, i;
+	unsigned char buf[NBYTES];
+
+	*perr = 0;
+	crcval = 0;
+
+	for (i = 0; i < NBYTES; i++)
+		buf[i] = 0;
+
+	if (!check_device())
+		*perr = ERR_NO_NUMBER;
+	else {
+		*perr = NO_ERROR;
+		write_byte(0xCC);		/* skip ROM (0xCC) */
+		write_byte(0xF0);		/* Read memory command 0xF0 */
+		write_byte(0x00);		/* Address TA1=0, TA2=0 */
+		write_byte(0x00);
+		read_byte(&crcval);		/* Read CRC of address and command */
+
+		for (i = 0; i < NBYTES; i++)
+			read_byte(&buf[i]);
+	}
+	if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
+		*perr = ERR_BAD_NUMBER;
+		psernum[0] = 0x00;
+		psernum[1] = 0xE0;
+		psernum[2] = 0xEE;
+		psernum[3] = 0xFF;
+		psernum[4] = 0xFF;
+		psernum[5] = 0xFF;
+	} else {
+		psernum[0] = 0x00;
+		psernum[1] = 0xE0;
+		psernum[2] = 0xEE;
+		psernum[3] = buf[7];
+		psernum[4] = buf[6];
+		psernum[5] = buf[5];
+	}
+}
+
+static int check_device()
+{
+	int found;
+
+	io_output();
+	io_out(0);
+	udelay(500);  /* must be at least 480 us low pulse */
+
+	io_input();
+	udelay(60);
+
+	found = (is_high() == 0) ? 1 : 0;
+	udelay(500);  /* must be at least 480 us low pulse */
+
+	return found;
+}
+
+static void write_byte(unsigned char command)
+{
+	char i;
+
+	for (i = 0; i < 8; i++) {
+		/* 1 us to 15 us low pulse starts bit slot */
+		/* Start with high pulse for 3 us */
+		io_input();
+		udelay(3);
+
+		io_out(0);
+		io_output();
+		udelay(3);
+
+		if (command & 0x01) {
+			/* 60 us high for 1-bit */
+			io_input();
+			udelay(60);
+		} else
+			/* 60 us low for 0-bit */
+			udelay(60);
+		/*  Leave pin as input */
+		io_input();
+
+		command = command >> 1;
+	}
+}
+
+static void read_byte(unsigned char *data)
+{
+	unsigned char i, rdat = 0;
+
+	for (i = 0; i < 8; i++) {
+		/* read one bit from one-wire device */
+
+		/* 1 - 15 us low starts bit slot */
+		io_out(0);
+		io_output();
+		udelay(0);
+
+		/* allow line to be pulled high */
+		io_input();
+
+		/* delay 10 us */
+		udelay(10);
+
+		/* now sample input status */
+		if (is_high())
+			rdat = (rdat >> 1) | 0x80;
+		else
+			rdat = rdat >> 1;
+
+		udelay(60);	/* at least 60 us */
+	}
+	/* copy the return value */
+	*data = rdat;
+}
+
+void board_get_enetaddr(uchar *enetaddr)
+{
+	unsigned char sn[6], err = NO_ERROR;
+
+	init_gpio();
+
+	read_2501_memory(sn, &err);
+
+	if (err == NO_ERROR) {
+		sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+				sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
+		printf("MAC address: %s\n", enetaddr);
+		setenv("ethaddr", (char *)enetaddr);
+	} else {
+		sprintf((char *)enetaddr, "00:01:02:03:04:05");
+		printf("Error reading MAC address.\n");
+		printf("Setting default to %s\n", enetaddr);
+		setenv("ethaddr", (char *)enetaddr);
+	}
+}
diff --git a/u-boot/board/v38b/v38b.c b/u-boot/board/v38b/v38b.c
new file mode 100644
index 0000000..978ff8d
--- /dev/null
+++ b/u-boot/board/v38b/v38b.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <net.h>
+#include <asm/processor.h>
+
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else
+		dramsize2 = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0)
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	else
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize + dramsize2;
+}
+
+
+int checkboard (void)
+{
+	puts("Board: MarelV38B\n");
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+	/*
+	 * Enable and configure the direction (output) of PSC3_9 - watchdog
+	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
+	 * Manual.
+	 */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
+#endif /* CONFIG_HW_WATCHDOG */
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write access for the
+	 * detection process.  Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+	/*
+	 * Enable GPIO_WKUP_7 to "read the status of the actual power
+	 * situation". Default direction is input, so no need to set it
+	 * explicitly.
+	 */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
+	return 0;
+}
+
+extern void board_get_enetaddr(uchar *enetaddr);
+int misc_init_r(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+}
+#endif
+
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+	/*
+	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
+	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
+	 */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
+}
+#endif /* CONFIG_HW_WATCHDOG */
diff --git a/u-boot/board/ve8313/Makefile b/u-boot/board/ve8313/Makefile
new file mode 100644
index 0000000..4a1b249
--- /dev/null
+++ b/u-boot/board/ve8313/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/ve8313/ve8313.c b/u-boot/board/ve8313/ve8313.c
new file mode 100644
index 0000000..166e459
--- /dev/null
+++ b/u-boot/board/ve8313/ve8313.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <ns16550.h>
+#include <nand.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
+
+int checkboard(void)
+{
+	puts("Board: ve8313\n");
+	return 0;
+}
+
+static long fixed_sdram(void)
+{
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+	/* now check the real size */
+	disable_addr_trans ();
+	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+	enable_addr_trans ();
+#endif
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	sync();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
+
+#define VE8313_WDT_EN	0x00020000
+#define VE8313_WDT_TRIG	0x00040000
+
+int board_early_init_f (void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+
+#if defined(CONFIG_HW_WATCHDOG)
+	/* enable WDT */
+	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#else
+	/* disable WDT */
+	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#endif
+	/* set WDT pins as output */
+	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
+
+	return 0;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+	unsigned long reg;
+
+	reg = in_be32(&gpio->dat);
+	if (reg & VE8313_WDT_TRIG)
+		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+	else
+		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+}
+#endif
+
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	setbits_be32(&clk->occr, 0xe0000000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
+
+	mpc83xx_pci_init(1, reg);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/u-boot/board/voiceblue/Makefile b/u-boot/board/voiceblue/Makefile
new file mode 100644
index 0000000..e16b195
--- /dev/null
+++ b/u-boot/board/voiceblue/Makefile
@@ -0,0 +1,74 @@
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= voiceblue.o
+SOBJS	:= setup.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+LOAD_ADDR = 0x10400000
+
+#########################################################################
+
+all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+$(obj)eeprom_start.o:
+	echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
+
+$(obj)eeprom:		$(obj)eeprom_start.o $(obj)eeprom.o
+	$(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
+		-L$(obj)../../examples/standalone -lstubs \
+		$(PLATFORM_LIBS)
+
+$(obj)eeprom.srec:	$(obj)eeprom
+	$(OBJCOPY) -S -O srec $(<:.o=) $@
+
+$(obj)eeprom.bin:	$(obj)eeprom
+	$(OBJCOPY) -S -O binary $< $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS) $(obj)eeprom \
+		$(obj)eeprom.srec $(obj)eeprom.bin \
+		$(obj)eeprom.o $(obj)eeprom_start.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/voiceblue/config.mk b/u-boot/board/voiceblue/config.mk
new file mode 100644
index 0000000..412b57d
--- /dev/null
+++ b/u-boot/board/voiceblue/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x13FD0000
diff --git a/u-boot/board/voiceblue/eeprom.c b/u-boot/board/voiceblue/eeprom.c
new file mode 100644
index 0000000..aa6baca
--- /dev/null
+++ b/u-boot/board/voiceblue/eeprom.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <timestamp.h>
+#include <net.h>
+#include "../drivers/net/smc91111.h"
+
+static struct eth_device dev = {
+	.iobase = CONFIG_SMC91111_BASE
+};
+
+static u16 read_eeprom_reg(u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_RELOAD, CTL_REG);
+
+	timeout = 100;
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout reading register %02x\n", reg);
+		return 0;
+	}
+
+	return SMC_inw(&dev, GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+
+	SMC_outw(&dev, value, GP_REG);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_STORE, CTL_REG);
+
+	timeout = 100;
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout writing register %02x\n", reg);
+		return 0;
+	}
+
+	return 1;
+}
+
+static int write_data(u16 *buf, int len)
+{
+	u16 reg = 0x23;
+
+	while (len--)
+		write_eeprom_reg(*buf++, reg++);
+
+	return 0;
+}
+
+static int verify_macaddr(char *s)
+{
+	u16 reg;
+	int i, err = 0;
+
+	puts("HWaddr: ");
+	for (i = 0; i < 3; i++) {
+		reg = read_eeprom_reg(0x20 + i);
+		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+		if (s)
+			err |= reg != ((u16 *)s)[i];
+	}
+
+	return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+	int i;
+	char *e, eaddr[6];
+
+	/* turn string into mac value */
+	for (i = 0; i < 6; i++) {
+		eaddr[i] = simple_strtoul(s, &e, 16);
+		s = (*e) ? e+1 : e;
+	}
+
+	for (i = 0; i < 3; i++)
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+	return 0;
+}
+
+static int parse_element(char *s, unsigned char *buf, int len)
+{
+	int cnt;
+	char *p, num[3];
+	unsigned char id;
+
+	id = simple_strtoul(s, &p, 16);
+	if (*p++ != ':')
+		return -1;
+	cnt = 2;
+	num[2] = 0;
+	for (; *p; p += 2) {
+		if (p[1] == 0)
+			return -2;
+		if (cnt + 3 > len)
+			return -3;
+		num[0] = p[0];
+		num[1] = p[1];
+		buf[cnt++] = simple_strtoul(num, NULL, 16);
+	}
+	buf[0] = id;
+	buf[1] = cnt - 2;
+
+	return cnt;
+}
+
+int eeprom(int argc, char * const argv[])
+{
+	int i, len, ret;
+	unsigned char buf[58], *p;
+
+	app_startup(argv);
+	i = get_version();
+	if (i != XF_VERSION) {
+		printf("Using ABI version %d, but U-Boot provides %d\n",
+			XF_VERSION, i);
+		return 1;
+	}
+
+	if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
+		puts("SMSC91111 not found\n");
+		return 2;
+	}
+
+	/* Called without parameters - print MAC address */
+	if (argc < 2) {
+		verify_macaddr(NULL);
+		return 0;
+	}
+
+	/* Print help message */
+	if (argv[1][1] == 'h') {
+		puts("VoiceBlue EEPROM writer\n"
+			"Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
+			"Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+		return 0;
+	}
+
+	/* Try to parse information elements */
+	len = sizeof(buf);
+	p = buf;
+	for (i = 2; i < argc; i++) {
+		ret = parse_element(argv[i], p, len);
+		switch (ret) {
+		case -1:
+			printf("Element %d: malformed\n", i - 1);
+			return 3;
+		case -2:
+			printf("Element %d: odd character count\n", i - 1);
+			return 3;
+		case -3:
+			puts("Out of EEPROM memory\n");
+			return 3;
+		default:
+			p += ret;
+			len -= ret;
+		}
+	}
+
+	/* First argument (MAC) is mandatory */
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		puts("*** HWaddr does not match! ***\n");
+		return 4;
+	}
+
+	while (len--)
+		*p++ = 0;
+
+	write_data((u16 *)buf, sizeof(buf) >> 1);
+
+	return 0;
+}
diff --git a/u-boot/board/voiceblue/setup.S b/u-boot/board/voiceblue/setup.S
new file mode 100644
index 0000000..6dddd6b
--- /dev/null
+++ b/u-boot/board/voiceblue/setup.S
@@ -0,0 +1,280 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	/* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE:		.word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE:	.word 0xfffbc800
+OMAP5910_MPU_TC_BASE:		.word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE:		.word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE:	.word 0xfffe0800
+OMAP5910_DPLL1_BASE:		.word 0xfffecf00
+OMAP5910_GPIO_BASE:		.word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE:	.word 0xfffec800
+OMAP5910_MPUI_BASE:		.word 0xfffec900
+
+_OMAP5910_ARM_CKCTL:		.word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK:		.word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL:		.word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG:		.word 0x00009090
+VAL_EMIFS_CS1_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS2_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS3_CONFIG:		.word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT:		.word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+				/*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
+VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
+VAL_EMIFF_MRS:			.word 0x00000037
+
+/*
+ * GPIO04 - D4 (Onboard LED)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+	.word 0x0000ff6f
+/*
+ * Disable everything, but D4 LED (connected through invertor)
+ */
+GPIO_OUTPUT:
+	.word 0x00000010
+
+MUX_CONFIG_BASE:
+	.word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+	.align 4
+	.word 0x00000000	@ FUNC_MUX_CTRL_0
+	.word 0x00000000	@ FUNC_MUX_CTRL_1
+	.word 0x00000000	@ FUNC_MUX_CTRL_2
+	.word 0x00000000	@ FUNC_MUX_CTRL_3
+	.word 0x00000000	@ FUNC_MUX_CTRL_4
+	.word 0x12082480	@ FUNC_MUX_CTRL_5
+	.word 0x0000001c	@ FUNC_MUX_CTRL_6
+	.word 0x00000003	@ FUNC_MUX_CTRL_7
+	.word 0x10001200	@ FUNC_MUX_CTRL_8
+	.word 0x01201012	@ FUNC_MUX_CTRL_9
+	.word 0x02081248	@ FUNC_MUX_CTRL_A
+	.word 0x00001248	@ FUNC_MUX_CTRL_B
+	.word 0x12240000	@ FUNC_MUX_CTRL_C
+	.word 0x00002000	@ FUNC_MUX_CTRL_D
+	.word 0x00000000	@ PULL_DWN_CTRL_0
+	.word 0x0000085f	@ PULL_DWN_CTRL_1
+	.word 0x01001000	@ PULL_DWN_CTRL_2
+	.word 0x00000000	@ PULL_DWN_CTRL_3
+	.word 0x00000000	@ GATE_INH_CTRL_0
+	.word 0x00000000	@ VOLTAGE_CTRL_0
+	.word 0x00000000	@ TEST_DBG_CTRL_0
+	.word 0x00000006	@ MOD_CONF_CTRL_0
+	.word 0x0000eaef	@ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+	.align 1
+	.byte 0x00		@ FUNC_MUX_CTRL_0
+	.byte 0x04		@ FUNC_MUX_CTRL_1
+	.byte 0x08		@ FUNC_MUX_CTRL_2
+	.byte 0x10		@ FUNC_MUX_CTRL_3
+	.byte 0x14		@ FUNC_MUX_CTRL_4
+	.byte 0x18		@ FUNC_MUX_CTRL_5
+	.byte 0x1c		@ FUNC_MUX_CTRL_6
+	.byte 0x20		@ FUNC_MUX_CTRL_7
+	.byte 0x24		@ FUNC_MUX_CTRL_8
+	.byte 0x28		@ FUNC_MUX_CTRL_9
+	.byte 0x2c		@ FUNC_MUX_CTRL_A
+	.byte 0x30		@ FUNC_MUX_CTRL_B
+	.byte 0x34		@ FUNC_MUX_CTRL_C
+	.byte 0x38		@ FUNC_MUX_CTRL_D
+	.byte 0x40		@ PULL_DWN_CTRL_0
+	.byte 0x44		@ PULL_DWN_CTRL_1
+	.byte 0x48		@ PULL_DWN_CTRL_2
+	.byte 0x4c		@ PULL_DWN_CTRL_3
+	.byte 0x50		@ GATE_INH_CTRL_0
+	.byte 0x60		@ VOLTAGE_CTRL_0
+	.byte 0x70		@ TEST_DBG_CTRL_0
+	.byte 0x80		@ MOD_CONF_CTRL_0
+	.byte 0x0c		@ COMP_MODE_CTRL_0
+	.byte 0xff
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Improve performance a bit... */
+	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
+	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
+	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
+	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
+	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
+	mov	r1, #0x00
+	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
+	nop
+	nop
+	nop
+	nop
+
+	/* Setup clocking mode */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ prepare base of CLOCK unit
+	ldrh	r1, [r0, #0x18]			@ get reset status
+	bic	r1, r1, #(7 << 11)		@ clear clock select
+	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
+	mov	r2, #0				@ set wait counter to 100 clock cycles
+
+icache_loop:
+	cmp	r2, #0x01
+	streqh	r1, [r0, #0x18]
+	add	r2, r2, #0x01
+	cmp	r2, #0x10
+	bne	icache_loop
+	nop
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	ldr	r1, _OMAP5910_ARM_CKCTL
+	orr	r1, r1, #0x2000			@ enable DSP clock
+	strh	r1, [r0, #0x00]			@ setup clock divisors
+
+	/* Setup DPLL to generate requested freq */
+	ldr	r0, OMAP5910_DPLL1_BASE		@ base of DPLL1 register
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+	strh	r1, [r0]			@ write
+
+locking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #0x01
+	beq	locking				@ while LOCK not set
+
+	/* Enable clock */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	mov	r1, #(1 << 10)			@ disable idle mode do not check
+						@ nWAKEUP pin, other remain active
+	strh	r1, [r0, #0x04]
+	ldr	r1, _OMAP5910_ARM_EN_CLK
+	strh	r1, [r0, #0x08]
+	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
+						@ max delayed ( 32 x CLKIN )
+	strh	r1, [r0, #0x0c]
+
+	/* Configure 5910 pins functions to match our board. */
+	ldr     r0, MUX_CONFIG_BASE
+	adr	r1, MUX_CONFIG_VALUES
+	adr	r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+	ldrb	r3, [r2], #1
+	ldr	r4, [r1], #4
+	cmp	r3, #0xff
+	strne	r4, [r0, r3]
+	bne	next_mux_cfg
+
+	/* Configure GPIO pins (also enables onboard LED) */
+	ldr	r0, OMAP5910_GPIO_BASE
+	ldr	r1, GPIO_OUTPUT
+	strh    r1, [r0, #0x04]
+	ldr	r1, GPIO_DIRECTION
+	strh	r1, [r0, #0x08]
+
+	/* EnablePeripherals */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ CLOCK unit
+	mov	r1, #0x0001			@ Peripheral enable
+	strh	r1, [r0, #0x14]
+
+	/* Program LED Pulse Generator */
+	ldr	r0, OMAP5910_LPG1_BASE		@ 1st LED Pulse Generator
+	mov	r1, #0x7F			@ Set obscure frequency in
+	strb	r1, [r0, #0x00]			@ LCR
+	mov	r1, #0x01			@ Enable clock (CLK_EN) in
+	strb    r1, [r0, #0x04]			@ PMR
+
+	/* TIPB Lock UART1 */
+	ldr	r0, OMAP5910_TIPB_SWITCHES_BASE	@ prepare base of TIPB switches
+	mov	r1, #1				@ ARM allocated
+	strh	r1, [r0,#0x04]			@ clear IRQ line and status bits
+	strh	r1, [r0,#0x00]
+	ldrh	r1, [r0,#0x04]
+
+	/* Disable watchdog */
+	ldr	r0, OMAP5910_MPU_WD_TIMER_BASE
+	mov	r1, #0xf5
+	strh	r1, [r0, #0x8]
+	mov	r1, #0xa0
+	strh	r1, [r0, #0x8]
+
+	/* Enable MCLK */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE
+	mov	r1, #0x6
+	strh	r1, [r0, #0x34]
+	strh	r1, [r0, #0x34]
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
+
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
+
+ulocking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #1
+	beq	ulocking			@ while LOCK not set
+
+	/* EMIF init */
+	ldr	r0, OMAP5910_MPU_TC_BASE
+	ldrh	r1, [r0, #0x0c]			@ EMIFS_CONFIG_REG
+	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x0c]
+
+	ldr	r1, VAL_EMIFS_CS0_CONFIG
+	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
+	ldr	r1, VAL_EMIFS_CS1_CONFIG
+	str	r1, [r0, #0x14]			@ EMIFS_CS1_CONFIG
+	ldr	r1, VAL_EMIFS_CS2_CONFIG
+	str	r1, [r0, #0x18]			@ EMIFS_CS2_CONFIG
+	ldr	r1, VAL_EMIFS_CS3_CONFIG
+	str	r1, [r0, #0x1c]			@ EMIFS_CS3_CONFIG
+	ldr	r1, VAL_EMIFS_DYN_WAIT
+	str	r1, [r0, #0x40]			@ EMIFS_CFG_DYN_WAIT
+
+	/* Setup SDRAM */
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG
+	str	r1, [r0, #0x20]			@ EMIFF_SDRAM_CONFIG
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG2
+	str	r1, [r0, #0x3c]			@ EMIFF_SDRAM_CONFIG2
+	ldr	r1, VAL_EMIFF_MRS
+	str	r1, [r0, #0x24]			@ EMIFF_MRS
+	/* SDRAM needs 100us to stabilize */
+	mov	r0, #0x4000
+sdelay:
+	subs	r0, r0, #0x1
+	bne	sdelay
+
+	/* back to arch calling code */
+	mov	pc, lr
+.end
diff --git a/u-boot/board/voiceblue/voiceblue.c b/u-boot/board/voiceblue/voiceblue.c
new file mode 100644
index 0000000..5f8af2b
--- /dev/null
+++ b/u-boot/board/voiceblue/voiceblue.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
+
+	/* arch number of VoiceBlue board */
+	gd->bd->bi_arch_number = MACH_TYPE_VOICEBLUE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
+
+	/* Take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete. */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+	udelay(10);	/* doesn't work before timer_init call */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+	udelay(500);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/vpac270/Makefile b/u-boot/board/vpac270/Makefile
new file mode 100644
index 0000000..f9acf63
--- /dev/null
+++ b/u-boot/board/vpac270/Makefile
@@ -0,0 +1,47 @@
+#
+# Voipac PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= vpac270.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/vpac270/vpac270.c b/u-boot/board/vpac270/vpac270.c
new file mode 100644
index 0000000..43bbdff
--- /dev/null
+++ b/u-boot/board/vpac270/vpac270.c
@@ -0,0 +1,132 @@
+/*
+ * Voipac PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* Arch number of vpac270 */
+	gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+	return &serial_ffuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef	CONFIG_RAM_256M
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+}
+
+#ifdef	CONFIG_CMD_USB
+int usb_board_init(void)
+{
+	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+void usb_board_init_fail(void)
+{
+	return;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/u-boot/board/w7o/Makefile b/u-boot/board/w7o/Makefile
new file mode 100644
index 0000000..5c94870
--- /dev/null
+++ b/u-boot/board/w7o/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
+	  watchdog.o
+SOBJS	= init.o post1.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/w7o/cmd_vpd.c b/u-boot/board/w7o/cmd_vpd.c
new file mode 100644
index 0000000..cab9881
--- /dev/null
+++ b/u-boot/board/w7o/cmd_vpd.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_CMD_BSP)
+
+#include "vpd.h"
+
+/* ======================================================================
+ * Interpreter command to retrieve board specific Vital Product Data, "VPD"
+ * ======================================================================
+ */
+int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	VPD vpd;			/* Board specific data struct */
+	uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+
+	/* Validate usage */
+	if (argc > 2)
+		return cmd_usage(cmdtp);
+
+	/* Passed in EEPROM address */
+	if (argc == 2)
+		dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16);
+
+	/* Read VPD and output it */
+	if (!vpd_get_data (dev_addr, &vpd)) {
+		vpd_print (&vpd);
+		return 0;
+	}
+
+	return 1;
+}
+
+U_BOOT_CMD(
+	  vpd,	2,	1,	do_vpd,
+	  "Read Vital Product Data",
+	  "[dev_addr]\n"
+	  "        - Read VPD Data from default address, or device address 'dev_addr'."
+);
+
+#endif
diff --git a/u-boot/board/w7o/errors.h b/u-boot/board/w7o/errors.h
new file mode 100644
index 0000000..05b4eae
--- /dev/null
+++ b/u-boot/board/w7o/errors.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ERRORS_H_
+#define _ERRORS_H_
+
+#define ERR_FF		-1	/* led test value(2) */
+#define ERR_00		0x0000	/* led test value(2) */
+#define ERR_LED		0x01	/* led test failed (1)(3)(4) */
+#define ERR_RAMG	0x04	/* start SDRAM data bus test (2) */
+#define ERR_RAML	0x05	/* SDRAM data bus fault in LSW chip (5) */
+#define ERR_RAMH	0x06	/* SDRAM data bus fault in MSW chip (6) */
+#define ERR_RAMB	0x07	/* SDRAM data bus fault both chips (5)(6)(7) */
+#define ERR_ADDG	0x08	/* start Address ghosting test (13) */
+#define ERR_ADDF	0x09	/* fault during Address ghosting test (13) */
+#define ERR_POST1	0x0a	/* post1 tests complete */
+#define ERR_TMP1	0x0b	/* */
+#define ERR_R55G	0x0c	/* start SDRAM fill 55 test (2) */
+#define ERR_R55L	0x0d	/* SDRAM fill test 55 failed in LSW chip (8) */
+#define ERR_R55H	0x0e	/* SDRAM fill test 55 failed in MSW chip (9) */
+#define ERR_R55B	0x0f	/* SDRAM fill test 55 fail in both chips (10) */
+#define ERR_RAAG	0x10	/* start SDRAM fill aa test (2) */
+#define ERR_RAAL	0x11	/* SDRAM fill test aa failed in LSW chip (8) */
+#define ERR_RAAH	0x12	/* SDRAM fill test aa failed in MSW chip (9) */
+#define ERR_RAAB	0x13	/* SDRAM fill test aa fail in both chips (10) */
+#define ERR_R00G	0x14	/* start SDRAM fill 00 test (2) */
+#define ERR_R00L	0x15	/* SDRAM fill test 00 failed in LSW chip (8) */
+#define ERR_R00H	0x16	/* SDRAM fill test 00 failed in MSW chip (9) */
+#define ERR_R00B	0x17	/* SDRAM fill test 00 fail in both chips (10) */
+#define ERR_RTCG	0x18	/* start RTC test */
+#define ERR_RTCBAT	0x19	/* RTC battery failure */
+#define ERR_RTCTIM	0x1A	/* RTC invalid time/date values */
+#define ERR_RTCVAL	0x1B	/* RTC NVRAM not accessable */
+#define ERR_FPGAG	0x20	/* fault during FPGA programming */
+#define ERR_XRW1	0x21	/* Xilinx - can't read/write regs on FPGA 1 */
+#define ERR_XRW2	0x22	/* Xilinx - can't read/write regs on FPGA 2 */
+#define ERR_XRW3	0x23	/* Xilinx - can't read/write regs on FPGA 3 */
+#define ERR_XRW4	0x24	/* Xilinx - can't read/write regs on FPGA 4 */
+#define ERR_XRW5	0x25	/* Xilinx - can't read/write regs on FPGA 5 */
+#define ERR_XRW6	0x26	/* Xilinx - can't read/write regs on FPGA 6 */
+#define ERR_XINIT0	0x27	/* Xilinx - INIT line failed to go low */
+#define ERR_XINIT1	0x28	/* Xilinx - INIT line failed to go high */
+#define ERR_XDONE1	0x29	/* Xilinx - DONE line failed to go high */
+#define ERR_XIMAGE	0x2A	/* Xilinx - Bad FPGA image in Flash */
+#define ERR_TempG	0x2b	/* start temp sensor tests */
+#define ERR_Tinit0	0x2C	/* temp sensor 0 failed to init */
+#define ERR_Tinit1	0x2D	/* temp sensor 1 failed to init */
+#define ERR_Ttest0	0x2E	/* temp sensor 0 failed test */
+#define ERR_Ttest1	0x2F	/* temp sensor 1 failed test */
+#define ERR_lm75r	0x30	/* temp sensor read failure */
+#define ERR_lm75w	0x31	/* temp sensor write failure */
+
+
+#define ERR_POSTOK	0x55	/* PANIC: psych... OK */
+
+#if !defined(__ASSEMBLY__)
+extern void log_stat(int errcode);
+extern void log_warn(int errcode);
+extern void log_err(int errcode);
+#endif
+
+/*
+Debugging suggestions:
+(1) periferal data bus shorted or crossed
+(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
+(3) check p_we, p_r/w, p_oe, p_rdy lines.
+(4) check LED buffers
+(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
+(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
+(7) check SDRAM control lines and clocks
+(8) check decoupling caps, replace LSW SDRAM
+(9) check decoupling caps, replace MSW SDRAM
+(10)
+(11)
+(12)
+(13) SDRAM address shorted or unconnected, check sdram caps
+*/
+#endif /* _ERRORS_H_ */
diff --git a/u-boot/board/w7o/flash.c b/u-boot/board/w7o/flash.c
new file mode 100644
index 0000000..184661b
--- /dev/null
+++ b/u-boot/board/w7o/flash.c
@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *  Based on code by:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#include <watchdog.h>
+
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word8(flash_info_t *info, ulong dest, ulong data);
+static int write_word32 (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    int i;
+    unsigned long size_b0, base_b0;
+    unsigned long size_b1, base_b1;
+
+    /* Init: no FLASHes known */
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* Get Size of Boot and Main Flashes */
+    size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+    if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size_b0, size_b0<<20);
+	return 0;
+    }
+    size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+    if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size_b1, size_b1<<20);
+	return 0;
+    }
+
+    /* Calculate base addresses */
+    base_b0 = -size_b0;
+    base_b1 = -size_b1;
+
+    /* Setup offsets for Boot Flash */
+    flash_get_offsets (base_b0, &flash_info[0]);
+
+    /* Protect board level data */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			base_b0,
+			flash_info[0].start[1] - 1,
+			&flash_info[0]);
+
+
+    /* Monitor protection ON by default */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1,
+			&flash_info[0]);
+
+    /* Protect the FPGA image */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM,
+			FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN - 1,
+			&flash_info[1]);
+
+    /* Protect the default boot image */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN,
+			FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN + 0x600000 - 1,
+			&flash_info[1]);
+
+    /* Setup offsets for Main Flash */
+    flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    return (size_b0 + size_b1);
+} /* end flash_init() */
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+    int i;
+
+    /* set up sector start address table - FOR BOOT ROM ONLY!!! */
+    if ((info->flash_id & FLASH_TYPEMASK)  == FLASH_AM040) {
+	for (i = 0; i < info->sector_count; i++)
+	    info->start[i] = base + (i * 0x00010000);
+    }
+} /* end flash_get_offsets() */
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:     printf ("1 x AMD ");    break;
+	case FLASH_MAN_STM:	printf ("1 x STM ");	break;
+	case FLASH_MAN_INTEL:   printf ("2 x Intel ");  break;
+	default:                printf ("Unknown Vendor ");
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+	    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		printf ("AM29LV040 (4096 Kbit, uniform sector size)\n");
+	    else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+		printf ("M29W040B (4096 Kbit, uniform block size)\n");
+	    else
+		printf ("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n");
+	    break;
+	case FLASH_28F320J3A:
+	    printf ("28F320J3A (32 Mbit = 128K x 32)\n");
+	    break;
+	case FLASH_28F640J3A:
+	    printf ("28F640J3A (64 Mbit = 128K x 64)\n");
+	    break;
+	case FLASH_28F128J3A:
+	    printf ("28F128J3A (128 Mbit = 128K x 128)\n");
+	    break;
+	default:
+	    printf ("Unknown Chip Type\n");
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+	printf ("  Size: %ld KB in %d Blocks\n",
+		info->size >> 10, info->sector_count);
+    } else {
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	 * Check if whole sector is erased
+	 */
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++)
+	{
+	    if (*flash++ != 0xffffffff)
+	    {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   "
+	);
+    }
+    printf ("\n");
+} /* end flash_print_info() */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong base = (ulong)addr;
+
+    /* Setup default type */
+    info->flash_id = FLASH_UNKNOWN;
+    info->sector_count =0;
+    info->size = 0;
+
+    /* Test for Boot Flash */
+    if (base == FLASH_BASE0_PRELIM) {
+	unsigned char value;
+	volatile unsigned char * addr2 = (unsigned char *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	*(addr2 + 0x555) = 0xaa;
+	*(addr2 + 0x2aa) = 0x55;
+	*(addr2 + 0x555) = 0x90;
+
+	/* Manufacture ID */
+	value = *addr2;
+	switch (value) {
+	    case (unsigned char)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	    case (unsigned char)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	    default:
+		*addr2 = 0xf0;              /* no or unknown flash  */
+		return 0;
+	}
+
+	/* Device ID */
+	value = *(addr2 + 1);
+	switch (value) {
+	    case (unsigned char)AMD_ID_LV040B:
+	    case (unsigned char)STM_ID_29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;                       /* => 512Kb */
+	    default:
+		*addr2 = 0xf0;               /* => no or unknown flash */
+		return 0;
+	}
+    }
+    else { /* MAIN Flash */
+	unsigned long value;
+	volatile unsigned long * addr2 = (unsigned long *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	*addr2 = 0x90909090;
+
+	/* Manufacture ID */
+	value = *addr2;
+	switch (value) {
+	    case (unsigned long)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	    default:
+		*addr2 = 0xff;              /* no or unknown flash  */
+		return 0;
+	}
+
+	/* Device ID - This shit is interleaved... */
+	value = *(addr2 + 1);
+	switch (value) {
+	    case (unsigned long)INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000 * 2;
+		break;                       /* => 2 X 4 MB */
+	    case (unsigned long)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000 * 2;
+		break;                       /* => 2 X 8 MB */
+	    case (unsigned long)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000 * 2;
+		break;                       /* => 2 X 16 MB */
+	    default:
+		*addr2 = 0xff;               /* => no or unknown flash */
+	}
+    }
+
+    /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */
+    if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+	printf ("** ERROR: sector count %d > max (%d) **\n",
+		info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+    }
+
+    /* set up sector start address table */
+    switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	    break;
+	case FLASH_28F320J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F128J3A:
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00020000 * 2); /* 2 Banks */
+	    break;
+    }
+
+    /* Test for Boot Flash */
+    if (base == FLASH_BASE0_PRELIM) {
+	volatile unsigned char *addr2;
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (AX .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr2 = (volatile unsigned char *)(info->start[i]);
+	    info->protect[i] = *(addr2 + 2) & 1;
+	}
+
+	/* Restore read mode */
+	*(unsigned char *)base = 0xF0;       /* Reset NORMAL Flash */
+    }
+    else { /* Main Flash */
+	volatile unsigned long *addr2;
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (AX .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr2 = (volatile unsigned long *)(info->start[i]);
+	    info->protect[i] = *(addr2 + 2) & 0x1;
+	}
+
+	/* Restore read mode */
+	*(unsigned long *)base = 0xFFFFFFFF; /* Reset  Flash */
+    }
+
+    return (info->size);
+} /* end flash_get_size() */
+
+/*-----------------------------------------------------------------------
+ */
+
+static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout)
+{
+    int i;
+
+    volatile uchar *vaddr =  (uchar *)addr;
+
+    /* Loop X times */
+    for (i = 1; i <= (100 * tout); i++) {    /* Wait up to tout ms */
+	udelay(10);
+	/* Pause 10 us */
+
+	/* Check for completion */
+	if ((vaddr[0] & 0x80) == (cmp_val & 0x80)) {
+	    return 0;
+	}
+
+	/* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */
+	if (!(i % 110000))
+	    putc('.');
+
+	/* Kick the dog if needed */
+	WATCHDOG_RESET();
+    }
+
+    return 1;
+} /* wait_for_DQ7() */
+
+/*-----------------------------------------------------------------------
+ */
+
+static int flash_erase8(flash_info_t *info, int s_first, int s_last)
+{
+    int tcode, rcode = 0;
+    volatile uchar *addr = (uchar *)(info->start[0]);
+    volatile uchar *sector_addr;
+    int flag, prot, sect;
+
+    /* Validate arguments */
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN)
+	    printf ("- missing\n");
+	else
+	    printf ("- no sectors to erase\n");
+	return 1;
+    }
+
+    /* Check for KNOWN flash type */
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    /* Check for protected sectors */
+    prot = 0;
+    for (sect = s_first; sect <= s_last; ++sect) {
+	if (info->protect[sect])
+	    prot++;
+    }
+    if (prot)
+	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    else
+	printf ("\n");
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect] == 0) {      /* not protected */
+	    sector_addr = (uchar *)(info->start[sect]);
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+		    printf("Erasing block %p\n", sector_addr);
+		else
+		    printf("Erasing sector %p\n", sector_addr);
+
+	    /* Disable interrupts which might cause Flash to timeout */
+	    flag = disable_interrupts();
+
+	    *(addr + 0x555) = (uchar)0xAA;
+	    *(addr + 0x2aa) = (uchar)0x55;
+	    *(addr + 0x555) = (uchar)0x80;
+	    *(addr + 0x555) = (uchar)0xAA;
+	    *(addr + 0x2aa) = (uchar)0x55;
+	    *sector_addr = (uchar)0x30;      /* sector erase */
+
+	    /*
+	     * Wait for each sector to complete, it's more
+	     * reliable.  According to AMD Spec, you must
+	     * issue all erase commands within a specified
+	     * timeout.  This has been seen to fail, especially
+	     * if printf()s are included (for debug)!!
+	     * Takes up to 6 seconds.
+	     */
+	    tcode  = wait_for_DQ7((ulong)sector_addr, 0x80, 6000);
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    /* Make sure we didn't timeout */
+	    if (tcode) {
+		printf ("Timeout\n");
+		rcode = 1;
+	    }
+	}
+    }
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /* reset to read mode */
+    addr = (uchar *)info->start[0];
+    *addr = (uchar)0xF0;                     /* reset bank */
+
+    printf (" done\n");
+    return rcode;
+} /* end flash_erase8() */
+
+static int flash_erase32(flash_info_t *info, int s_first, int s_last)
+{
+    int flag, sect;
+    ulong start, now, last;
+    int prot = 0;
+
+    /* Validate arguments */
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN)
+	    printf ("- missing\n");
+	else
+	    printf ("- no sectors to erase\n");
+	return 1;
+    }
+
+    /* Check for KNOWN flash type */
+    if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+	printf ("Can erase only Intel flash types - aborted\n");
+	return 1;
+    }
+
+    /* Check for protected sectors */
+    for (sect = s_first; sect <= s_last; ++sect) {
+	if (info->protect[sect])
+	    prot++;
+    }
+    if (prot)
+	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    else
+	printf ("\n");
+
+    start = get_timer (0);
+    last  = start;
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect <= s_last; sect++) {
+	WATCHDOG_RESET();
+	if (info->protect[sect] == 0) {      /* not protected */
+	    vu_long *addr = (vu_long *)(info->start[sect]);
+	    unsigned long status;
+
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    *addr = 0x00500050;              /* clear status register */
+	    *addr = 0x00200020;              /* erase setup */
+	    *addr = 0x00D000D0;              /* erase confirm */
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    /* Wait at least 80us - let's wait 1 ms */
+	    udelay (1000);
+
+	    while (((status = *addr) & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+		    printf ("Timeout\n");
+		    *addr = 0x00B000B0;      /* suspend erase      */
+		    *addr = 0x00FF00FF;      /* reset to read mode */
+		    return 1;
+		}
+
+		/* show that we're waiting */
+		if ((now - last) > 990) {   /* every second */
+		    putc ('.');
+		    last = now;
+		}
+	    }
+	    *addr = 0x00FF00FF;              /* reset to read mode */
+	}
+    }
+    printf (" done\n");
+    return 0;
+} /* end flash_erase32() */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+    if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+	return flash_erase8(info, s_first, s_last);
+    else
+	return flash_erase32(info, s_first, s_last);
+} /* end flash_erase() */
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    ulong start;
+    int i, l, rc;
+
+    start = get_timer (0);
+
+    wp = (addr & ~3);                        /* get lower word
+						aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word8(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word8(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+	if (get_timer(start) > 1000) {   /* every second */
+	   WATCHDOG_RESET();
+	   putc ('.');
+	   start = get_timer(0);
+	}
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word8(info, wp, data));
+} /* end write_buff8() */
+
+#define	FLASH_WIDTH	4	/* flash bus width in bytes */
+static int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	ulong start;
+
+	start = get_timer (0);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word32(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word32(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	  if (get_timer(start) > 990) {   /* every second */
+			putc ('.');
+			start = get_timer(0);
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word32(info, wp, data));
+} /* write_buff32() */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    int retval;
+
+    if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+	retval = write_buff8(info, src, addr, cnt);
+    else
+	retval = write_buff32(info, src, addr, cnt);
+
+    return retval;
+} /* end write_buff() */
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_word8(flash_info_t *info, ulong dest, ulong data)
+{
+    volatile uchar *addr2 = (uchar *)(info->start[0]);
+    volatile uchar *dest2 = (uchar *)dest;
+    volatile uchar *data2 = (uchar *)&data;
+    int flag;
+    int i, tcode, rcode = 0;
+
+    /* Check if Flash is (sufficently) erased */
+    if ((*((volatile uchar *)dest) &
+	(uchar)data) != (uchar)data) {
+	return (2);
+    }
+
+    for (i=0; i < (4 / sizeof(uchar)); i++) {
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*(addr2 + 0x555) = (uchar)0xAA;
+	*(addr2 + 0x2aa) = (uchar)0x55;
+	*(addr2 + 0x555) = (uchar)0xA0;
+
+	dest2[i] = data2[i];
+
+	/* Wait for write to complete, up to 1ms */
+	tcode = wait_for_DQ7((ulong)&dest2[i], data2[i], 1);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+	    enable_interrupts();
+
+	/* Make sure we didn't timeout */
+	if (tcode) {
+	    rcode = 1;
+	}
+    }
+
+    return rcode;
+} /* end write_word8() */
+
+static int write_word32(flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long *)dest;
+    ulong status;
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*addr & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *addr = 0x00400040;                      /* write setup */
+    *addr = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (((status = *addr) & 0x00800080) != 0x00800080) {
+	WATCHDOG_RESET();
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+	    *addr = 0x00FF00FF;              /* restore read mode */
+	    return (1);
+	}
+    }
+
+    *addr = 0x00FF00FF;                      /* restore read mode */
+
+    return (0);
+} /* end write_word32() */
+
+
+static int _flash_protect(flash_info_t *info, long sector)
+{
+    int i;
+    int flag;
+    ulong status;
+    int rcode = 0;
+    volatile long *addr = (long *)sector;
+
+    switch(info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F128J3A:
+	    /* Disable interrupts which might cause Flash to timeout */
+	    flag = disable_interrupts();
+
+	    /* Issue command */
+	    *addr = 0x00500050L;             /* Clear the status register */
+	    *addr = 0x00600060L;             /* Set lock bit setup */
+	    *addr = 0x00010001L;             /* Set lock bit confirm */
+
+	    /* Wait for command completion */
+	    for (i = 0; i < 10; i++) {       /* 75us timeout, wait 100us */
+		udelay(10);
+		if ((*addr & 0x00800080L) == 0x00800080L)
+		    break;
+	    }
+
+	    /* Not successful? */
+	    status = *addr;
+	    if (status != 0x00800080L) {
+		printf("Protect %x sector failed: %x\n",
+		       (uint)sector, (uint)status);
+		rcode = 1;
+	    }
+
+	    /* Restore read mode */
+	    *addr = 0x00ff00ffL;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    break;
+	case FLASH_AM040:                    /* No soft sector protection */
+	    break;
+    }
+
+    /* Turn protection on for this sector */
+    for (i = 0; i < info->sector_count; i++) {
+	if (info->start[i] == sector) {
+	    info->protect[i] = 1;
+	    break;
+	}
+    }
+
+    return rcode;
+} /* end _flash_protect() */
+
+static int _flash_unprotect(flash_info_t *info, long sector)
+{
+    int i;
+    int flag;
+    ulong status;
+    int rcode = 0;
+    volatile long *addr = (long *)sector;
+
+    switch(info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F128J3A:
+	    /* Disable interrupts which might cause Flash to timeout */
+	    flag = disable_interrupts();
+
+	    *addr = 0x00500050L;             /* Clear the status register */
+	    *addr = 0x00600060L;             /* Clear lock bit setup */
+	    *addr = 0x00D000D0L;             /* Clear lock bit confirm */
+
+	    /* Wait for command completion */
+	    for (i = 0; i < 80 ; i++) {      /* 700ms timeout, wait 800 */
+		udelay(10000);               /* Delay 10ms */
+		if ((*addr & 0x00800080L) == 0x00800080L)
+		    break;
+	    }
+
+	    /* Not successful? */
+	    status = *addr;
+	    if (status != 0x00800080L) {
+		printf("Un-protect %x sector failed: %x\n",
+		       (uint)sector, (uint)status);
+		*addr = 0x00ff00ffL;
+		rcode = 1;
+	    }
+
+	    /* restore read mode */
+	    *addr = 0x00ff00ffL;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    break;
+	case FLASH_AM040:                    /* No soft sector protection */
+	    break;
+    }
+
+    /*
+     * Fix Intel's little red wagon.  Reprotect
+     * sectors that were protected before we undid
+     * protection on a specific sector.
+     */
+    for (i = 0; i < info->sector_count; i++) {
+	if (info->start[i] != sector) {
+	    if (info->protect[i]) {
+		if (_flash_protect(info, info->start[i]))
+		    rcode = 1;
+	    }
+	}
+	else /* Turn protection off for this sector */
+	    info->protect[i] = 0;
+    }
+
+    return rcode;
+} /* end _flash_unprotect() */
+
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+    int rcode;
+
+    if (prot)
+	rcode = _flash_protect(info, info->start[sector]);
+    else
+	rcode = _flash_unprotect(info, info->start[sector]);
+
+    return rcode;
+} /* end flash_real_protect() */
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/w7o/fpga.c b/u-boot/board/w7o/fpga.c
new file mode 100644
index 0000000..100bce4
--- /dev/null
+++ b/u-boot/board/w7o/fpga.c
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *  and
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include "w7o.h"
+#include <asm/processor.h>
+#include "errors.h"
+
+static void
+fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
+{
+    unsigned long i;
+    volatile unsigned long val;
+    volatile unsigned short *dest = daddr;	/* volatile-bypass optimizer */
+
+    for (i = 0; i < len; i++, src++) {
+	val = *src;
+	*dest = (unsigned short)((val & 0xff000000L) >> 16);
+	*dest = (unsigned short)((val & 0x00ff0000L) >> 8);
+	*dest = (unsigned short)(val & 0x0000ff00L);
+	*dest = (unsigned short)((val & 0x000000ffL) << 8);
+    }
+
+    /* Terminate programming with 4 C clocks */
+    dest = daddr;
+    val = *(unsigned short *)dest;
+    val = *(unsigned short *)dest;
+    val = *(unsigned short *)dest;
+    val = *(unsigned short *)dest;
+
+}
+
+
+int
+fpgaDownload(unsigned char *saddr,
+	     unsigned long size,
+	     unsigned short *daddr)
+{
+    int i;					/* index, intr disable flag */
+    int start;					/* timer */
+    unsigned long greg, grego;			/* GPIO & output register */
+    unsigned long length;			/* image size in words */
+    unsigned long *source;			/* image source addr */
+    unsigned short *dest;			/* destination FPGA addr */
+    volatile unsigned short *ndest;		/* temp dest FPGA addr */
+    volatile unsigned short val;		/* temp val */
+    unsigned long cnfg = GPIO_XCV_CNFG;		/* FPGA CNFG */
+    unsigned long eirq = GPIO_XCV_IRQ;
+    int retval = -1;				/* Function return value */
+
+    /* Setup some basic values */
+    length = (size / 4) + 1;			/* size in words, rounding UP
+						    is OK */
+    source = (unsigned long *)saddr;
+    dest = (unsigned short *)daddr;
+
+    /* Get DCR output register */
+    grego = in32(PPC405GP_GPIO0_OR);
+
+    /* Reset FPGA */
+    grego &= ~GPIO_XCV_PROG;			/* PROG line low */
+    out32(PPC405GP_GPIO0_OR, grego);
+
+    /* Setup timeout timer */
+    start = get_timer(0);
+
+    /* Wait for FPGA init line */
+    while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
+	/* Check for timeout - 100us max, so use 3ms */
+	if (get_timer(start) > 3) {
+	    printf("     failed to start init.\n");
+	    log_warn(ERR_XINIT0);		/* Don't halt */
+
+	    /* Reset line stays low */
+	    goto done;				/* I like gotos... */
+	}
+    }
+
+    /* Unreset FPGA */
+    grego |= GPIO_XCV_PROG;			/* PROG line high */
+    out32(PPC405GP_GPIO0_OR, grego);
+
+    /* Wait for FPGA end of init period .  */
+    while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
+
+	/* Check for timeout */
+	if (get_timer(start) > 3) {
+	    printf("     failed to exit init.\n");
+	    log_warn(ERR_XINIT1);
+
+	    /* Reset FPGA */
+	    grego &= ~GPIO_XCV_PROG;		/* PROG line low */
+	    out32(PPC405GP_GPIO0_OR, grego);
+
+	    goto done;
+	}
+    }
+
+    /* Now program FPGA ... */
+    ndest = dest;
+    for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+	/* Toggle IRQ/GPIO */
+	greg = mfdcr(CPC0_CR0);			/* get chip ctrl register */
+	greg |= eirq;				/* toggle irq/gpio */
+	mtdcr(CPC0_CR0, greg);			/*  ... just do it */
+
+	/* turn on open drain for CNFG */
+	greg = in32(PPC405GP_GPIO0_ODR);	/* get open drain register */
+	greg |= cnfg;				/* CNFG open drain */
+	out32(PPC405GP_GPIO0_ODR, greg);	/*  .. just do it */
+
+	/* Turn output enable on for CNFG */
+	greg = in32(PPC405GP_GPIO0_TCR);	/* get tristate register */
+	greg |= cnfg;				/* CNFG tristate inactive */
+	out32(PPC405GP_GPIO0_TCR, greg);	/*  ... just do it */
+
+	/* Setup FPGA for programming */
+	grego &= ~cnfg;				/* CONFIG line low */
+	out32(PPC405GP_GPIO0_OR, grego);
+
+	/*
+	 * Program the FPGA
+	 */
+	printf("\n       destination: 0x%lx ", (unsigned long)ndest);
+
+	fpga_img_write(source,  length,  (unsigned short *)ndest);
+
+	/* Done programming */
+	grego |= cnfg;				/* CONFIG line high */
+	out32(PPC405GP_GPIO0_OR, grego);
+
+	/* Turn output enable OFF for CNFG */
+	greg = in32(PPC405GP_GPIO0_TCR);	/* get tristate register */
+	greg &= ~cnfg;				/* CNFG tristate inactive */
+	out32(PPC405GP_GPIO0_TCR, greg);	/*  ... just do it */
+
+	/* Toggle IRQ/GPIO */
+	greg = mfdcr(CPC0_CR0);			/* get chip ctrl register */
+	greg &= ~eirq;				/* toggle irq/gpio */
+	mtdcr(CPC0_CR0, greg);			/*  ... just do it */
+
+	ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */
+	cnfg >>= 1;				/* XXX - Next  */
+	eirq >>= 1;
+    }
+
+    /* Terminate programming with 4 C clocks */
+    ndest = dest;
+    for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+	val = *ndest;
+	val = *ndest;
+	val = *ndest;
+	val = *ndest;
+	ndest = (unsigned short *)((char *)ndest + 0x00100000L);
+    }
+
+    /* Setup timer */
+    start = get_timer(0);
+
+    /* Wait for FPGA end of programming period .  */
+    while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
+
+	/* Check for timeout */
+	if (get_timer(start) > 3) {
+	    printf("     done failed to come high.\n");
+	    log_warn(ERR_XDONE1);
+
+	    /* Reset FPGA */
+	    grego &= ~GPIO_XCV_PROG;		/* PROG line low */
+	    out32(PPC405GP_GPIO0_OR, grego);
+
+	    goto done;
+	}
+    }
+
+    printf("\n       FPGA load succeeded\n");
+    retval = 0;					/* Program OK */
+
+done:
+    return retval;
+}
+
+/* FPGA image is stored in flash */
+extern flash_info_t    flash_info[];
+
+int init_fpga(void)
+{
+    unsigned int i,j,ptr;			/* General purpose */
+    unsigned char bufchar;			/* General purpose character */
+    unsigned char *buf;				/* Start of image pointer */
+    unsigned long len;				/* Length of image */
+    unsigned char *fn_buf;			/* Start of filename string */
+    unsigned int fn_len;			/* Length of filename string */
+    unsigned char *xcv_buf;			/* Pointer to start of image */
+    unsigned long xcv_len;			/* Length of image */
+    unsigned long crc;				/* 30bit crc in image */
+    unsigned long calc_crc;			/* Calc'd 30bit crc */
+    int retval = -1;
+
+    /* Tell the world what we are doing */
+    printf("FPGA:  ");
+
+    /*
+     * Get address of first sector where the FPGA
+     * image is stored.
+     */
+    buf = (unsigned char *)flash_info[1].start[0];
+
+    /*
+     * Get the stored image's CRC & length.
+     */
+    crc = *(unsigned long *)(buf+4);		/* CRC is first long word */
+    len = *(unsigned long *)(buf+8);		/* Image len is next long */
+
+    /* Pedantic */
+    if ((len < 0x133A4) || (len > 0x80000))
+	goto bad_image;
+
+    /*
+     * Get the file name pointer and length.
+     */
+    fn_len = (*(unsigned short *)(buf+12) & 0xff); /* filename length
+						      is next short */
+    fn_buf = buf + 14;
+
+    /*
+     * Get the FPGA image pointer and length length.
+     */
+    xcv_buf = fn_buf + fn_len;			/* pointer to fpga image */
+    xcv_len = len - 14 - fn_len;		/* fpga image length */
+
+    /* Check for uninitialized FLASH */
+    if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
+	goto bad_image;
+
+    /*
+     * Calculate and Check the image's CRC.
+     */
+    calc_crc = crc32(0, xcv_buf, xcv_len);
+    if (crc != calc_crc) {
+	printf("\nfailed - bad CRC\n");
+	goto done;
+    }
+
+    /* Output the file name */
+    printf("file name  : ");
+    for (i=0;i<fn_len;i++) {
+	bufchar = fn_buf[+i];
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    /*
+     * find rest of display data
+     */
+    ptr = 15;					/* Offset to ncd filename
+						   length in fpga image */
+    j = xcv_buf[ptr];				/* Get len of ncd filename */
+    if (j > 32) goto bad_image;
+    ptr = ptr + j + 3;				/* skip ncd filename string +
+						   3 bytes more bytes */
+
+    /*
+     * output target device string
+     */
+    j = xcv_buf[ptr++] - 1;			/* len of targ str less term */
+    if (j > 32) goto bad_image;
+    printf("\n       target     : ");
+    for (i = 0; i < j; i++) {
+	bufchar = (xcv_buf[ptr++]);
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    /*
+     * output compilation date string and time string
+     */
+    ptr += 3;					/* skip 2 bytes */
+    printf("\n       synth time : ");
+    j = (xcv_buf[ptr++] - 1);			/* len of date str less term */
+    if (j > 32) goto bad_image;
+    for (i = 0; i < j; i++) {
+	bufchar = (xcv_buf[ptr++]);
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    ptr += 3;					/* Skip 2 bytes */
+    printf(" - ");
+    j = (xcv_buf[ptr++] - 1);			/* slen = targ dev str len */
+    if (j > 32) goto bad_image;
+    for (i = 0; i < j; i++) {
+	bufchar = (xcv_buf[ptr++]);
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    /*
+     * output crc and length strings
+     */
+    printf("\n       len & crc  : 0x%lx  0x%lx", len, crc);
+
+    /*
+     * Program the FPGA.
+     */
+    retval = fpgaDownload((unsigned char*)xcv_buf, xcv_len,
+			  (unsigned short *)0xfd000000L);
+    return retval;
+
+bad_image:
+    printf("\n       BAD FPGA image format @ %lx\n", flash_info[1].start[0]);
+    log_warn(ERR_XIMAGE);
+done:
+    return retval;
+}
+
+void test_fpga(unsigned short *daddr)
+{
+    int i;
+    volatile unsigned short *ndest = daddr;
+
+    for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+#if defined(CONFIG_W7OLMG)
+	ndest[0x7e] = 0x55aa;
+	if (ndest[0x7e] != 0x55aa)
+	    log_warn(ERR_XRW1 + i);
+	ndest[0x7e] = 0xaa55;
+	if (ndest[0x7e] != 0xaa55)
+	    log_warn(ERR_XRW1 + i);
+	ndest[0x7e] = 0xc318;
+	if (ndest[0x7e] != 0xc318)
+	    log_warn(ERR_XRW1 + i);
+
+#elif defined(CONFIG_W7OLMC)
+	ndest[0x800] = 0x55aa;
+	ndest[0x801] = 0xaa55;
+	ndest[0x802] = 0xc318;
+	ndest[0x4800] = 0x55aa;
+	ndest[0x4801] = 0xaa55;
+	ndest[0x4802] = 0xc318;
+	if ((ndest[0x800] != 0x55aa) ||
+	    (ndest[0x801] != 0xaa55) ||
+	    (ndest[0x802] != 0xc318))
+	    log_warn(ERR_XRW1 + (2 * i));       /* Auto gen error code */
+	if ((ndest[0x4800] != 0x55aa) ||
+	    (ndest[0x4801] != 0xaa55) ||
+	    (ndest[0x4802] != 0xc318))
+	    log_warn(ERR_XRW2 + (2 * i));       /* Auto gen error code */
+
+#else
+# error "Unknown W7O board configuration"
+#endif
+    }
+
+    printf("       FPGA ready\n");
+    return;
+}
diff --git a/u-boot/board/w7o/fsboot.c b/u-boot/board/w7o/fsboot.c
new file mode 100644
index 0000000..0ef9a61
--- /dev/null
+++ b/u-boot/board/w7o/fsboot.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2001
+ * Wave 7 Optics, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+
+/*
+ * FIXME: Add code to test image and it's header.
+ */
+extern int valid_elf_image (unsigned long addr);
+
+static int
+image_check(ulong addr)
+{
+    return valid_elf_image(addr);
+}
+
+void
+init_fsboot(void)
+{
+    char  *envp;
+    ulong loadaddr;
+    ulong testaddr;
+    ulong alt_loadaddr;
+    char buf[9];
+
+    /*
+     * Get test image address
+     */
+    if ((envp = getenv("testaddr")) != NULL)
+	testaddr = simple_strtoul(envp, NULL, 16);
+    else
+	testaddr = -1;
+
+    /*
+     * Are we going to test boot and image?
+     */
+    if ((testaddr != -1) && image_check(testaddr)) {
+
+	/* Set alt_loadaddr */
+	alt_loadaddr = testaddr;
+	sprintf(buf, "%lX", alt_loadaddr);
+	setenv("alt_loadaddr", buf);
+
+	/* Clear test_addr */
+	setenv("testaddr", NULL);
+
+	/*
+	 * Save current environment with alt_loadaddr,
+	 * and cleared testaddr.
+	 */
+	saveenv();
+
+	/*
+	 * Setup temporary loadaddr to alt_loadaddr
+	 * XXX - DO NOT SAVE ENVIRONMENT!
+	 */
+	loadaddr = alt_loadaddr;
+	sprintf(buf, "%lX", loadaddr);
+	setenv("loadaddr", buf);
+
+    } else { /* Normal boot */
+	setenv("alt_loadaddr", NULL);		/* Clear alt_loadaddr */
+	setenv("testaddr", NULL);		/* Clear testaddr */
+	saveenv();
+    }
+
+    return;
+}
diff --git a/u-boot/board/w7o/init.S b/u-boot/board/w7o/init.S
new file mode 100644
index 0000000..b3aadca
--- /dev/null
+++ b/u-boot/board/w7o/init.S
@@ -0,0 +1,266 @@
+/******************************************************************************
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	addi	r3, 0, EBC0_CFG
+	mtdcr	EBC0_CFGADDR, r3
+	addis	r4, 0, 0xb040		/* Device base timeout = 1024 cycles */
+	ori	r4, r4, 0x0		/* Drive CS with external master */
+	mtdcr	EBC0_CFGDATA, r4
+
+	/********************************************************************
+	 * Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, CPC0_CR1
+	ori	r4, r4, 0x4000
+	mtdcr	CPC0_CR1, r4
+
+	/********************************************************************
+	 * Memory Bank 0 (Flash Bank 0) initialization
+	 *******************************************************************/
+	addi	r3, 0, PB1AP
+	mtdcr	EBC0_CFGADDR, r3
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
+	mtdcr	EBC0_CFGDATA, r4
+
+	addi	r3, 0, PB0CR
+	mtdcr	EBC0_CFGADDR, r3
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
+	mtdcr	EBC0_CFGDATA, r4
+
+	/********************************************************************
+	 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
+	 *******************************************************************/
+	addi	r3, 0, PB7AP
+	mtdcr	EBC0_CFGADDR, r3
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
+	mtdcr	EBC0_CFGDATA, r4
+
+	addi	r3, 0, PB7CR
+	mtdcr	EBC0_CFGADDR, r3
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
+	mtdcr	EBC0_CFGDATA, r4
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ *		Serial Presence Detect, "SPD," reads the SDRAM EEPROM
+ *		via the IIC bus and then configures the SDRAM memory
+ *		banks appropriately. If Auto Memory Configuration is
+ *		is not used, it is assumed that a 4MB 11x8x2, non-ECC,
+ *		SDRAM is soldered down.
+ *
+ * Notes:	Expects that the stack is already setup.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -8(r1)		/* Save back chain and move SP */
+	stw	r0, +12(r1)		/* Save link register */
+
+	/*
+	 * First call spd_sdram to try to init SDRAM according to the
+	 * contents of the SPD EEPROM.  If the SPD EEPROM is blank or
+	 * erronious, spd_sdram returns 0 in R3.
+	 */
+	li	r3,0
+	bl	spd_sdram
+	addic.	r3, r3, 0		/* Check for error, save dram size */
+	bne	..sdri_done		/* If it worked, we're done... */
+
+	/********************************************************************
+	 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
+	 * is the SMALLEST SDRAM size the 405 supports.  We can do this
+	 * because W7O boards have soldered on RAM, and there will always
+	 * be some amount present.  If we were using DIMMs, we should hang
+	 * the board instead, since it doesn't have any RAM to continue
+	 * running with.
+	 *******************************************************************/
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	addi    r3, 0, SDRAM0_CFG
+	mtdcr   SDRAM0_CFGADDR, r3
+	addis   r4, 0, 0x0
+	ori     r4, r4, 0x0
+	mtdcr   SDRAM0_CFGDATA, r4
+
+	/*
+	 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
+	 * All other banks are disabled.
+	 */
+	addi	r3, 0, SDRAM0_B0CR
+	mtdcr	SDRAM0_CFGADDR, r3
+	addis	r4, 0, 0x0000		/* BA=0x0, SZ=4MB */
+	ori	r4, r4, 0x8001		/* Mode is 5, 11x8x2or4, BE=Enabled */
+	mtdcr	SDRAM0_CFGDATA, r4
+
+	/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
+	addi	r4, 0, 0		/* Zero the data reg */
+
+	addi	r3, r3, 4		/* Point to MB1CF reg */
+	mtdcr	SDRAM0_CFGADDR, r3		/* Set the address */
+	mtdcr	SDRAM0_CFGDATA, r4		/* Zero the reg */
+
+	addi	r3, r3, 4		/* Point to MB2CF reg */
+	mtdcr	SDRAM0_CFGADDR, r3		/* Set the address */
+	mtdcr	SDRAM0_CFGDATA, r4		/* Zero the reg */
+
+	addi	r3, r3, 4		/* Point to MB3CF reg */
+	mtdcr	SDRAM0_CFGADDR, r3		/* Set the address */
+	mtdcr	SDRAM0_CFGDATA, r4		/* Zero the reg */
+
+	/********************************************************************
+	 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+	 * To set the appropriate timings, we assume sdram is
+	 * 100MHz (pc100 compliant).
+	 *******************************************************************/
+
+	/*
+	 * Set up SDTR1
+	 */
+	addi    r3, 0, SDRAM0_TR
+	mtdcr   SDRAM0_CFGADDR, r3
+	addis   r4, 0, 0x0086		/* SDTR1 value for 100Mhz */
+	ori     r4, r4, 0x400D
+	mtdcr   SDRAM0_CFGDATA, r4
+
+	/*
+	 * Set RTR
+	 */
+	addi    r3, 0, SDRAM0_RTR
+	mtdcr   SDRAM0_CFGADDR, r3
+	addis   r4, 0, 0x05F0		/* RTR refresh val = 15.625ms@100Mhz */
+	mtdcr   SDRAM0_CFGDATA, r4
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait 200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	addi    r3, 0, SDRAM0_CFG
+	mtdcr   SDRAM0_CFGADDR, r3
+	addis   r4, 0, 0x80E0		/* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
+	ori     r4, r4, 0x0000		/* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
+	mtdcr   SDRAM0_CFGDATA, r4		/* EMDULR=1 */
+
+..sdri_done:
+	/* restore and return */
+	lwz	r0, +12(r1)		/* Get saved link register */
+	addi	r1, r1, +8		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/u-boot/board/w7o/post1.S b/u-boot/board/w7o/post1.S
new file mode 100644
index 0000000..0aaca02
--- /dev/null
+++ b/u-boot/board/w7o/post1.S
@@ -0,0 +1,742 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *  and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Description:
+ *	Routine to exercise memory for the bringing up of our boards.
+ */
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include <watchdog.h>
+
+#include "errors.h"
+
+#define _ASMLANGUAGE
+
+	.globl	test_sdram
+	.globl	test_led
+	.globl	log_stat
+	.globl	log_warn
+	.globl	log_err
+	.globl  temp_uart_init
+	.globl  post_puts
+	.globl  disp_hex
+
+/*****************************************************
+*******   Text Strings for low level printing   ******
+*******          In section got2               *******
+*****************************************************/
+
+/*
+ * Define the text strings for errors and warnings.
+ * Switch to .data section.
+ */
+	.section ".data"
+err_str:	.asciz "*** POST ERROR   = "
+warn_str:	.asciz "*** POST WARNING = "
+end_str:  .asciz "\r\n"
+
+/*
+ * Enter the labels in Global Entry Table (GOT).
+ * Switch to .got2 section.
+ */
+	START_GOT
+	GOT_ENTRY(err_str)
+	GOT_ENTRY(warn_str)
+	GOT_ENTRY(end_str)
+	END_GOT
+
+/*
+ * Switch  back to .text section.
+ */
+	.text
+
+/****************************************
+ ****************************************
+ ********    LED register test   ********
+ ****************************************
+ ***************************************/
+test_led:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	WATCHDOG_RESET			/* Reset the watchdog */
+
+	addi    r3, 0, ERR_FF		/* first test value is ffff */
+	addi	r4, r3, 0		/* save copy of pattern */
+	bl	set_led			/* store first test value */
+	bl	get_led			/* read it back */
+	xor.	r4, r4, r3		/* compare to original */
+#if defined(CONFIG_W7OLMC)
+	andi.   r4, r4, 0x00ff		/* lmc has 8 bits */
+#else
+	andi.   r4, r4, 0xffff		/* lmg has 16 bits */
+#endif
+	beq     LED2			/* next test */
+	addi    r3, 0, ERR_LED		/* error code = 1 */
+	bl	log_err			/* display error and halt */
+LED2:	addi    r3, 0, ERR_00		/* 2nd test value is 0000 */
+	addi	r4, r3, 0		/* save copy of pattern */
+	bl	set_led			/* store first test value */
+	bl	get_led			/* read it back */
+	xor.	r4, r4, r3		/* compare to original */
+#if defined(CONFIG_W7OLMC)
+	andi.   r4, r4, 0x00ff		/* lmc has 8 bits */
+#else
+	andi.   r4, r4, 0xffff		/* lmg has 16 bits */
+#endif
+	beq     LED3			/* next test */
+	addi    r3, 0, ERR_LED		/* error code = 1 */
+	bl	log_err			/* display error and halt */
+
+LED3:	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/****************************************
+ ****************************************
+ ********     SDRAM TESTS        ********
+ ****************************************
+ ***************************************/
+test_sdram:
+	/* called with mem size in r3 */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stmw	r30, +8(r1)		/* save R30,R31 */
+					/* r30 is log2(mem size) */
+					/* r31 is mem size */
+
+	/* take log2 of total mem size */
+	addi	r31, r3, 0		/* save total mem size */
+	addi	r30, 0, 0		/* clear r30 */
+l2_loop:
+	srwi.	r31, r31, 1		/* shift right 1 */
+	addi	r30, r30, 1		/* count shifts */
+	bne	l2_loop			/* loop till done */
+	addi	r30, r30, -1		/* correct for over count */
+	addi	r31, r3, 0		/* save original size */
+
+	/* now kick the dog and test the mem */
+	WATCHDOG_RESET			/* Reset the watchdog */
+	bl	Data_Buster		/* test crossed/shorted data lines */
+	addi	r3, r30, 0		/* get log2(memsize) */
+	addi	r4, r31, 0		/* get memsize */
+	bl	Ghost_Buster		/* test crossed/shorted addr lines */
+	addi	r3, r31, 0		/* get mem size */
+	bl	Bit_Buster		/* check for bad internal bits */
+
+	/* restore stack and return */
+	lmw	r30, +8(r1)		/* Restore r30, r31 */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+
+/****************************************
+ ********  sdram data bus test   ********
+ ***************************************/
+Data_Buster:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -24(r1)		/* Save back chain and move SP */
+	stw	r0, +28(r1)		/* Save link register */
+	stmw	r28, 8(r1)		/* save r28 - r31 on stack */
+					/* r31 i/o register */
+					/* r30 sdram base address */
+					/* r29 5555 syndrom */
+					/* r28 aaaa syndrom */
+
+	/* set up led register for this test */
+	addi    r3, 0, ERR_RAMG		/* set led code to 1 */
+	bl	log_stat		/* store test value */
+	/* now test the dram data bus */
+	xor	r30, r30, r30		/* load r30 with base addr of sdram */
+	addis	r31, 0, 0x5555		/* load r31 with test value */
+	ori	r31, r31, 0x5555
+	stw	r31,0(r30)		/* sto the value */
+	lwz	r29,0(r30)		/* read it back */
+	xor	r29,r31,r29		/* compare it to original */
+	addis	r31, 0, 0xaaaa		/* load r31 with test value */
+	ori	r31, r31, 0xaaaa
+	stw	r31,0(r30)		/* sto the value */
+	lwz	r28,0(r30)		/* read it back */
+	xor	r28,r31,r28		/* compare it to original */
+	or	r3,r28,r29		/* or together both error terms */
+	/*
+	 * Now that we have the error bits,
+	 * we have to decide which part they are in.
+	 */
+	bl	get_idx			/* r5 is now index to error */
+	addi	r3, r3, ERR_RAMG
+	cmpwi	r3, ERR_RAMG		/* check for errors */
+	beq	db_done			/* skip if no errors */
+	bl	log_err			/* log the error */
+
+db_done:
+	lmw	r28, 8(r1)		/* restore r28 - r31 from stack */
+	lwz	r0, +28(r1)		/* Get saved link register */
+	addi	r1, r1, +24		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/****************************************************
+ ********  test for address ghosting in dram ********
+ ***************************************************/
+
+Ghost_Buster:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -36(r1)		/* Save back chain and move SP */
+	stw	r0, +40(r1)		/* Save link register */
+	stmw	r25, 8(r1)		/* save r25 - r31 on stack */
+					/* r31 = scratch register */
+					/* r30 is main referance loop counter,
+					   0 to 23 */
+					/* r29 is ghost loop count, 0 to 22 */
+					/* r28 is referance address */
+					/* r27 is ghost address */
+					/* r26 is log2 (mem size) =
+					     number of byte addr bits */
+					/* r25 is mem size */
+
+	/* save the log2(mem size) and mem size */
+	addi	r26, r3, 0		/* r26 is number of byte addr bits */
+	addi	r25, r4, 0		/* r25 is mem size in bytes */
+
+	/* set the leds for address ghost test */
+	addi	r3, 0, ERR_ADDG
+	bl	set_led
+
+	/* first fill memory with zeros */
+	srwi	r31, r25, 2		/* convert bytes to longs */
+	mtctr	r31			/* setup byte counter */
+	addi	r28, 0, 0		/* start at address at 0 */
+	addi	r31, 0, 0		/* data value = 0 */
+clr_loop:
+	stw	r31, 0(r28)		/* Store zero value */
+	addi	r28, r28, 4		/* Increment to next word */
+	andi.	r27, r28, 0xffff	/* check for 2^16 loops */
+	bne	clr_skip		/* if not there, then skip */
+	WATCHDOG_RESET			/* kick the dog every now and then */
+clr_skip:
+	bdnz	clr_loop		/* Round and round... */
+
+	/* now do main test */
+	addi	r30, 0, 0		/* start referance counter at 0 */
+outside:
+	/*
+	 * Calculate the referance address
+	 *   the referance address is calculated by setting the (r30-1)
+	 *   bit of the base address
+	 * when r30=0, the referance address is the base address.
+	 * thus the sequence 0,1,2,4,8,..,2^(n-1)
+	 * setting the bit is done with the following shift functions.
+	 */
+	WATCHDOG_RESET			/* Reset the watchdog */
+
+	addi	r31, 0, 1		/* r31 = 1 */
+	slw	r28, r31, r30		/* set bit coresponding to loop cnt */
+	srwi	r28, r28, 1		/* then shift it right one so  */
+					/*   we start at location 0 */
+	/* fill referance address with Fs */
+	addi	r31, 0, 0x00ff		/* r31 = one byte of set bits */
+	stb     r31,0(r28)		/* save ff in referance address */
+
+	/* ghost (inner) loop, now check all posible ghosted addresses */
+	addi	r29, 0, 0		/* start ghosted loop counter at 0 */
+inside:
+	/*
+	 * Calculate the ghost address by flipping one
+	 *  bit of referance address.  This gives the
+	 *  sequence 1,2,4,8,...,2^(n-1)
+	 */
+	addi	r31, 0, 1		/* r31 = 1 */
+	slw     r27, r31, r29		/* set  bit coresponding to loop cnt */
+	xor	r27, r28, r27		/* ghost address = ref addr with
+					     bit flipped*/
+
+	/* now check for ghosting */
+	lbz     r31,0(r27)		/* get content of ghost addr */
+	cmpwi   r31, 0			/* compare read value to 0 */
+	bne	Casper			/*   we found a ghost! */
+
+	/* now close ghost ( inner ) loop */
+	addi	r29, r29, 1		/* increment inner loop counter */
+	cmpw	r29, r26		/* check for last inner loop */
+	blt		inside		/* do more inner loops */
+
+	/* now close referance ( outer ) loop */
+	addi	r31, 0, 0		/* r31 = zero */
+	stb	r31, 0(28)		/* zero out the altered address loc. */
+	/*
+	 * Increment and check for end, count is zero based.
+	 * With the ble, this gives us one more loops than
+	 * address bits for sequence 0,1,2,4,8,...2^(n-1)
+	*/
+	addi	r30, r30, 1		/* increment outer loop counter */
+	cmpw	r30, r26		/* check for last inner loop */
+	ble	outside			/* do more outer loops */
+
+	/* were done, lets go home */
+	b	gb_done
+Casper:					/* we found a ghost !! */
+	addi	r3, 0, ERR_ADDF		/* get indexed error message */
+	bl	log_err			/* log error led error code */
+gb_done: /*  pack your bags, and go home */
+	lmw     r25, 8(r1)              /* restore r25 - r31 from stack */
+	lwz     r0, +40(r1)             /* Get saved link register */
+	addi    r1, r1, +36             /* Remove frame from stack */
+	mtlr    r0                      /* Restore link register */
+	blr                             /* Return to calling function */
+
+/****************************************************
+ ********      SDRAM data fill tests       **********
+ ***************************************************/
+Bit_Buster:
+	/* called with mem size in r3 */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+	stw	r5, +12(r1)		/* save r5 */
+
+	addis	r5, r3, 0		/* save mem size */
+
+	/* Test 55555555 */
+	addi	r3, 0, ERR_R55G		/* set up error code in case we fail */
+	bl	log_stat		/* store test value */
+	addis	r4, 0, 0x5555
+	ori	r4, r4, 0x5555
+	bl	fill_test
+
+	/* Test aaaaaaaa  */
+	addi	r3, 0, ERR_RAAG		/* set up error code in case we fail */
+	bl	log_stat		/* store test value */
+	addis	r4, 0, 0xAAAA
+	ori	r4, r4, 0xAAAA
+	bl	fill_test
+
+	/* Test 00000000  */
+	addi	r3, 0, ERR_R00G		/* set up error code in case we fail */
+	bl	log_stat		/* store test value */
+	addis	r4, 0, 0
+	ori	r4, r4, 0
+	bl	fill_test
+
+	/* restore stack and return */
+	lwz	r5, +12(r1)		/* restore r4 */
+	lwz	r4, +8(r1)		/* restore r4 */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/****************************************************
+ ********             fill test              ********
+ ***************************************************/
+/*	tests memory by filling with value, and reading back */
+/*	r5 = Size of memory in bytes */
+/*	r4 = Value to write */
+/*	r3 = Error code */
+fill_test:
+	mflr    r0                      /* Get link register */
+	stwu    r1, -32(r1)             /* Save back chain and move SP */
+	stw     r0, +36(r1)             /* Save link register */
+	stmw    r27, 8(r1)              /* save r27 - r31 on stack */
+					/* r31 - scratch register */
+					/* r30 - memory address */
+	mr	r27, r3
+	mr	r28, r4
+	mr	r29, r5
+
+	WATCHDOG_RESET			/* Reset the watchdog */
+
+	/* first fill memory with Value */
+	srawi	r31, r29, 2		/* convert bytes to longs */
+	mtctr	r31			/* setup counter */
+	addi	r30, 0, 0		/* Make r30 = addr 0 */
+ft_0:	stw	r28, 0(r30)		/* Store value */
+	addi	r30, r30, 4		/* Increment to next word */
+	andi.	r31, r30, 0xffff	/* check for 2^16 loops */
+	bne	ft_0a			/* if not there, then skip */
+	WATCHDOG_RESET			/* kick the dog every now and then */
+ft_0a:	bdnz	ft_0			/* Round and round... */
+
+	WATCHDOG_RESET			/* Reset the watchdog */
+
+	/* Now confirm Value is in memory */
+	srawi	r31, r29, 2		/* convert bytes to longs */
+	mtctr	r31			/* setup counter */
+	addi	r30, 0, 0		/* Make r30 = addr 0 */
+ft_1:	lwz	r31, 0(r30)		/* get value from memory */
+	xor.	r31, r31, r28		/* Writen = Read ? */
+	bne	ft_err			/* If bad, than halt */
+	addi	r30, r30, 4		/* Increment to next word */
+	andi.	r31, r30, 0xffff	/* check for 2^16 loops*/
+	bne	ft_1a			/* if not there, then skip */
+	WATCHDOG_RESET			/* kick the dog every now and then */
+ft_1a:	bdnz	ft_1			/* Round and round... */
+
+	WATCHDOG_RESET			/* Reset the watchdog */
+
+	b	fill_done		/* restore and return */
+
+ft_err:	addi	r29, r27, 0		/* save current led code */
+	addi	r27, r31, 0		/* get pattern in r27 */
+	bl	get_idx			/* get index from r27 */
+	add	r27, r27, r29		/* add index to old led code */
+	bl	log_err			/* output led err code, halt CPU */
+
+fill_done:
+	lmw     r27, 8(r1)              /* restore r27 - r31 from stack */
+	lwz     r0, +36(r1)             /* Get saved link register */
+	addi    r1, r1, +32             /* Remove frame from stack */
+	mtlr    r0                      /* Restore link register */
+	blr                             /* Return to calling function */
+
+
+/****************************************************
+ *******  get error index from r3 pattern    ********
+ ***************************************************/
+get_idx:				/* r3 = (MSW(r3) !=0)*2 +
+					    (LSW(r3) !=0) */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	andi.	r4, r3, 0xffff		/* check for lower bits */
+	beq	gi2			/* skip if no bits set */
+	andis.	r4, r3, 0xffff		/* check for upper bits */
+	beq	gi3			/* skip if no bits set */
+	addi	r3, 0, 3		/* both upper and lower bits set */
+	b	gi_done
+gi2:	andis.	r4, r3, 0xffff		/* check for upper bits*/
+	beq	gi4			/* skip if no bits set */
+	addi	r3, 0, 2		/* only upper bits set */
+	b	gi_done
+gi3:	addi	r3, 0, 1		/* only lower bits set */
+	b	gi_done
+gi4:	addi	r3, 0, 0		/* no bits set */
+gi_done:
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/****************************************************
+ ********       set LED to R5 and hang       ********
+ ***************************************************/
+log_stat:				/* output a led code and continue */
+set_led:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	addis	r4, 0, 0xfe00		/* LED buffer is at 0xfe000000 */
+#if defined(CONFIG_W7OLMG)		/* only on gateway, invert outputs */
+	xori	r3,r3, 0xffff		/* complement led code, active low */
+	sth	r3, 0(r4)		/* store first test value */
+	xori	r3,r3, 0xffff		/* complement led code, active low */
+#else					/* if not gateway, then don't invert */
+	sth	r3, 0(r4)		/* store first test value */
+#endif
+
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+get_led:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	addis	r4, 0, 0xfe00		/* LED buffer is at 0xfe000000 */
+	lhz	r3, 0(r4)		/* store first test value */
+#if defined(CONFIG_W7OLMG)		/* only on gateway, invert inputs */
+	xori	r3,r3, 0xffff		/* complement led code, active low */
+#endif
+
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+log_err:	/* output the error and hang the board ( for now ) */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r3, +8(r1)		/* save a copy of error code */
+	bl	set_led			/* set the led pattern */
+	GET_GOT				/* get GOT address in r14 */
+	lwz	r3,GOT(err_str)		/* get address of string */
+	bl	post_puts		/* output the warning string */
+	lwz	r3, +8(r1)		/* get error code */
+	addi	r4, 0, 2		/* set disp length to 2 nibbles */
+	bl	disp_hex		/* output the error code */
+	lwz	r3,GOT(end_str)		/* get address of string */
+	bl	post_puts		/* output the warning string */
+halt:
+	b	halt			/* hang */
+
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+log_warn:	/* output a warning, then continue with operations */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stw	r3, +8(r1)		/* save a copy of error code */
+	stw	r14, +12(r1)		/* save a copy of r14 (used by GOT) */
+
+	bl	set_led			/* set the led pattern */
+	GET_GOT				/* get GOT address in r14 */
+	lwz	r3,GOT(warn_str)	/* get address of string */
+	bl	post_puts		/* output the warning string */
+	lwz	r3, +8(r1)		/* get error code */
+	addi	r4, 0, 2		/* set disp length to 2 nibbles */
+	bl	disp_hex		/* output the error code */
+	lwz	r3,GOT(end_str)		/* get address of string */
+	bl	post_puts		/* output the warning string */
+
+	addis	r3, 0, 64		/* has a long delay */
+	mtctr	r3
+log_2:
+	WATCHDOG_RESET			/* this keeps dog from barking, */
+					/*   and takes time */
+	bdnz	log_2			/* loop till time expires */
+
+	/* restore stack and return */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	lwz	r14, +12(r1)		/* restore r14 */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/*******************************************************************
+ *	temp_uart_init
+ *	Temporary UART initialization routine
+ *	Sets up UART0 to run at 9600N81 off of the internal clock.
+ *	R3-R4 are used.
+ ******************************************************************/
+temp_uart_init:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -8(r1)		/* Save back chain and move SP */
+	stw	r0, +12(r1)		/* Save link register */
+
+	addis   r3, 0, 0xef60
+	ori     r3, r3, 0x0303          /* r3 = UART0_LCR */
+	addi    r4, 0, 0x83             /* n81 format, divisor regs enabled */
+	stb     r4, 0(r3)
+
+	/* set baud rate to use internal clock,
+	   baud = (200e6/16)/31/42 = 9600 */
+
+	addis   r3, 0, 0xef60		/* Address of baud divisor reg */
+	ori     r3, r3, 0x0300		/*   UART0_DLM */
+	addi    r4, 0, +42		/* uart baud divisor LSB = 93 */
+	stb     r4, 0(r3)               /* baud = (200 /16)/14/93 */
+
+	addi    r3, r3, 0x0001		/* uart baud divisor addr */
+	addi    r4, 0, 0
+	stb     r4, 0(r3)               /* Divisor Latch MSB = 0 */
+
+	addis   r3, 0, 0xef60
+	ori     r3, r3, 0x0303          /* r3 = UART0_LCR */
+	addi    r4, 0, 0x03             /* n81 format, tx/rx regs enabled */
+	stb     r4, 0(r3)
+
+	/* output a few line feeds */
+	addi	r3, 0, '\n'		/* load line feed */
+	bl	post_putc		/* output the char */
+	addi	r3, 0, '\n'		/* load line feed */
+	bl	post_putc		/* output the char */
+
+	/* restore stack and return */
+	lwz	r0, +12(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +8		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/**********************************************************************
+ **	post_putc
+ **	outputs charactor in R3
+ **	r3 returns the error code ( -1 if there is an error )
+ *********************************************************************/
+
+post_putc:
+
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -20(r1)		/* Save back chain and move SP */
+	stw	r0, +24(r1)		/* Save link register */
+	stmw	r29, 8(r1)		/* save	r29 - r31 on stack
+					   r31 - uart base address
+					   r30 - delay counter
+					   r29 - scratch reg */
+
+     addis   r31, 0, 0xef60		/* Point to uart base */
+     ori     r31, r31, 0x0300
+     addis   r30, 0, 152		/* Load about 10,000,000 ticks. */
+pputc_lp:
+	lbz     r29, 5(r31)		/* Read Line Status Register */
+	andi.   r29, r29, 0x20		/* Check THRE status */
+	bne     thre_set		/* Branch if FIFO empty */
+	addic.  r30, r30, -1		/* Decrement and check if empty. */
+	bne     pputc_lp		/* Try, try again */
+	addi    r3, 0, -1		/* Load error code for timeout */
+	b       pputc_done		/* Bail out with error code set */
+thre_set:
+	stb     r3, 0(r31)		/* Store character to UART */
+	addi	r3, 0, 0		/* clear error code */
+pputc_done:
+	lmw	r29, 8(r1)		/*restore r29 - r31 from stack */
+	lwz	r0, +24(r1)		/* Get saved link register */
+	addi	r1, r1, +20		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/****************************************************************
+    post_puts
+    Accepts a null-terminated string pointed to by R3
+    Outputs to the serial port until 0x00 is found.
+    r3 returns the error code ( -1 if there is an error )
+*****************************************************************/
+post_puts:
+
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r31, 8(r1)		/* save r31 - char pointer */
+
+	addi	r31, r3, 0              /* move pointer to R31 */
+pputs_nxt:
+	lbz	r3, 0(r31)		/* Get next character */
+	addic.  r3, r3, 0		/* Check for zero */
+	beq	pputs_term		/* bail out if zero */
+	bl	post_putc		/* output the char */
+	addic.	r3, r3, 0		/* check for error */
+	bne	pputs_err
+	addi	r31, r31, 1		/* point to next char */
+	b	pputs_nxt		/* loop till term */
+pputs_err:
+	addi	r3, 0, -1		/* set error code */
+	b	pputs_end		/* were outa here */
+pputs_term:
+	addi	r3, 0, 1		/* set success code */
+	/* restore stack and return */
+pputs_end:
+	lwz	r31, 8(r1)		/* restore r27 - r31 from stack */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/********************************************************************
+ *****	disp_hex
+ *****	Routine to display a hex value from a register.
+ *****	R3 is value to display
+ *****	R4 is number of nibbles to display ie 2 for byte 8 for (long)word
+ *****	Returns -1 in R3 if there is an error ( ie serial port hangs )
+ *****	Returns 0 in R3 if no error
+ *******************************************************************/
+disp_hex:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stmw	r30, 8(r1)		/* save r30 - r31 on stack */
+					/* r31 output char */
+					/* r30 uart base address */
+	addi	r30, 0, 8               /* Go through 8 nibbles. */
+	addi	r31, r3, 0
+pputh_nxt:
+	rlwinm	r31, r31, 4, 0, 31	/* Rotate next nibble into position */
+	andi.	r3, r31, 0x0f		/* Get nibble. */
+	addi	r3, r3, 0x30		/* Add zero's ASCII code. */
+	cmpwi	r3, 0x03a
+	blt	pputh_out
+	addi	r3, r3, 0x07            /* 0x27 for lower case. */
+pputh_out:
+	cmpw	r30, r4
+	bgt	pputh_skip
+	bl	post_putc
+	addic.	r3, r3, 0		/* check for error */
+	bne	pputh_err
+pputh_skip:
+	addic.	r30, r30, -1
+	bne	pputh_nxt
+	xor	r3, r3, r3		/* Clear error code */
+	b	pputh_done
+pputh_err:
+	addi	r3, 0, -1		/* set error code */
+pputh_done:
+	/* restore stack and return */
+	lmw	r30, 8(r1)		/*  restore r30 - r31 from stack */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
diff --git a/u-boot/board/w7o/post2.c b/u-boot/board/w7o/post2.c
new file mode 100644
index 0000000..1dfaa2f
--- /dev/null
+++ b/u-boot/board/w7o/post2.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
+ *   and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <rtc.h>
+#include "errors.h"
+#include "dtt.h"
+
+/* for LM75 DTT POST test */
+#define DTT_READ_TEMP		0x0
+#define DTT_CONFIG		0x1
+#define DTT_TEMP_HYST		0x2
+#define DTT_TEMP_SET		0x3
+
+#if defined(CONFIG_RTC_M48T35A)
+void rtctest(void)
+{
+    volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9);
+    struct rtc_time tmp;
+
+    /* set up led code for RTC tests */
+    log_stat(ERR_RTCG);
+
+    /*
+     * Do RTC battery test. The first write after power up
+     * fails if battery is low.
+     */
+    *tchar = 0xaa;
+    if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT);
+    *tchar = 0x55;				/* Reset test address */
+
+    /*
+     * Now lets check the validity of the values in the RTC.
+     */
+    rtc_get(&tmp);
+    if ((tmp.tm_sec < 0)	| (tmp.tm_sec  > 59)   |
+	(tmp.tm_min < 0)	| (tmp.tm_min  > 59)   |
+	(tmp.tm_hour < 0)	| (tmp.tm_hour > 23)   |
+	(tmp.tm_mday < 1 )	| (tmp.tm_mday > 31)   |
+	(tmp.tm_mon < 1 )	| (tmp.tm_mon  > 12)   |
+	(tmp.tm_year < 2000)	| (tmp.tm_year > 2500) |
+	(tmp.tm_wday < 1 )	| (tmp.tm_wday > 7)) {
+	log_warn(ERR_RTCTIM);
+	rtc_reset();
+    }
+
+    /*
+     * Now lets do a check to see if the NV RAM is there.
+     */
+    *tchar = 0xaa;
+    if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL);
+    *tchar = 0x55;				/* Reset test address */
+
+} /* rtctest() */
+#endif	/* CONFIG_RTC_M48T35A */
+
+
+#ifdef CONFIG_DTT_LM75
+int dtt_test(int sensor)
+{
+    short temp, trip, hyst;
+
+    /* get values */
+    temp = dtt_read(sensor, DTT_READ_TEMP) / 256;
+    trip = dtt_read(sensor, DTT_TEMP_SET) / 256;
+    hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
+
+    /* check values */
+    if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) ||
+	(trip != CONFIG_SYS_DTT_MAX_TEMP) ||
+	(temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP))
+	return 1;
+
+    return 0;
+} /* dtt_test() */
+#endif /* CONFIG_DTT_LM75 */
+
+/*****************************************/
+
+void post2(void)
+{
+#if defined(CONFIG_RTC_M48T35A)
+    rtctest();
+#endif	/* CONFIG_RTC_M48T35A */
+
+#ifdef CONFIG_DTT_LM75
+    log_stat(ERR_TempG);
+    if(dtt_test(2) != 0) log_warn(ERR_Ttest0);
+    if(dtt_test(4) != 0) log_warn(ERR_Ttest1);
+#endif /* CONFIG_DTT_LM75 */
+} /* post2() */
diff --git a/u-boot/board/w7o/u-boot.lds.debug b/u-boot/board/w7o/u-boot.lds.debug
new file mode 100644
index 0000000..5ff67d1
--- /dev/null
+++ b/u-boot/board/w7o/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/w7o/vpd.c b/u-boot/board/w7o/vpd.c
new file mode 100644
index 0000000..57558e8
--- /dev/null
+++ b/u-boot/board/w7o/vpd.c
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(VXWORKS)
+# include <stdio.h>
+# include <string.h>
+# define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0
+extern char iicReadByte( char, char );
+extern ulong_t crc32( unsigned char *, unsigned long );
+#else
+#include <common.h>
+#endif
+
+#include "vpd.h"
+
+/*
+ * vpd_reader() - reads VPD data from I2C EEPROMS.
+ *                returns pointer to buffer or NULL.
+ */
+static unsigned char *
+vpd_reader(unsigned char *buf, unsigned dev_addr, unsigned off, unsigned count)
+{
+    unsigned offset = off;			/* Calculated offset */
+
+    /*
+     * The main board EEPROM contains
+     * SDRAM SPD in the first 128 bytes,
+     * so skew the offset.
+     */
+    if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
+	offset += SDRAM_SPD_DATA_SIZE;
+
+    /* Try to read the I2C EEPROM */
+#if defined(VXWORKS)
+    {
+	int i;
+	for( i = 0; i < count; ++i ) {
+	    buf[ i ] = iicReadByte( dev_addr, offset+i );
+	}
+    }
+#else
+    if (eeprom_read(dev_addr, offset, buf, count)) {
+	printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n",
+	       count, dev_addr, offset);
+	return NULL;
+    }
+#endif
+
+    return buf;
+} /* vpd_reader() */
+
+
+/*
+ * vpd_get_packet() - returns next VPD packet or NULL.
+ */
+static vpd_packet_t *vpd_get_packet(vpd_packet_t *vpd_packet)
+{
+    vpd_packet_t *packet = vpd_packet;
+
+    if (packet != NULL) {
+	if (packet->identifier == VPD_PID_TERM)
+	    return NULL;
+	else
+	    packet = (vpd_packet_t *)((char *)packet + packet->size + 2);
+    }
+
+    return packet;
+} /* vpd_get_packet() */
+
+
+/*
+ * vpd_find_packet() - Locates and returns the specified
+ *		       VPD packet or NULL on error.
+ */
+static vpd_packet_t *vpd_find_packet(vpd_t *vpd, unsigned char ident)
+{
+    vpd_packet_t *packet = (vpd_packet_t *)&vpd->packets;
+
+    /* Guaranteed illegal */
+    if (ident == VPD_PID_GI)
+	return NULL;
+
+    /* Scan tuples looking for a match */
+    while ((packet->identifier != ident) &&
+	   (packet->identifier != VPD_PID_TERM))
+	packet = vpd_get_packet(packet);
+
+    /* Did we find it? */
+    if ((packet->identifier) && (packet->identifier != ident))
+	return NULL;
+    return packet;
+}
+
+
+/*
+ * vpd_is_valid() - Validates contents of VPD data
+ *		    in I2C EEPROM.  Returns 1 for
+ *		    success or 0 for failure.
+ */
+static int vpd_is_valid(unsigned dev_addr, unsigned char *buf)
+{
+    unsigned	    num_bytes;
+    vpd_packet_t    *packet;
+    vpd_t	    *vpd = (vpd_t *)buf;
+    unsigned short  stored_crc16, calc_crc16 = 0xffff;
+
+    /* Check Eyecatcher */
+    if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
+	unsigned offset = 0;
+	if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
+	    offset += SDRAM_SPD_DATA_SIZE;
+	printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, offset);
+
+	return 0;
+    }
+
+    /* Check Length */
+    if (vpd->header.size> VPD_MAX_EEPROM_SIZE) {
+	printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n",
+	       dev_addr, vpd->header.size);
+	return 0;
+    }
+
+    /* Now find the termination packet */
+    if ((packet = vpd_find_packet(vpd, VPD_PID_TERM)) == NULL) {
+	printf("Error: VPD EEPROM 0x%x missing termination packet\n",
+	       dev_addr);
+	return 0;
+    }
+
+    /* Calculate data size */
+    num_bytes = (unsigned long)((unsigned char *)packet -
+				(unsigned char *)vpd + sizeof(vpd_packet_t));
+
+    /* Find stored CRC and clear it */
+    if ((packet = vpd_find_packet(vpd, VPD_PID_CRC)) == NULL) {
+	printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr);
+	return 0;
+    }
+    stored_crc16 = *((ushort *)packet->data);
+    *(ushort *)packet->data = 0;
+
+    /* OK, lets calculate the CRC and check it */
+#if defined(VXWORKS)
+    calc_crc16 = (0xffff & crc32(buf, num_bytes));
+#else
+    calc_crc16 = (0xffff & crc32(0, buf, num_bytes));
+#endif
+    *(ushort *)packet->data = stored_crc16;     /* Now restore the CRC */
+    if (stored_crc16 != calc_crc16) {
+	printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n",
+	       dev_addr, stored_crc16);
+	return 0;
+    }
+
+    return 1;
+} /* vpd_is_valid() */
+
+
+/*
+ * size_ok() - Check to see if packet size matches
+ *	       size of data we want. Returns 1 for
+ *	       good match or 0 for failure.
+ */
+static int size_ok(vpd_packet_t *packet, unsigned long size)
+{
+    if (packet->size != size) {
+	printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
+	return 0;
+    }
+    return 1;
+} /* size_ok() */
+
+
+/*
+ * strlen_ok() - Check to see if packet size matches
+ *		 strlen of the string we want to populate.
+ *		 Returns 1 for valid length or 0 for failure.
+ */
+static int strlen_ok(vpd_packet_t *packet, unsigned long length)
+{
+    if (packet->size >= length) {
+	printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
+	return 0;
+    }
+    return 1;
+} /* strlen_ok() */
+
+
+/*
+ * get_vpd_data() - populates the passed VPD structure 'vpdInfo'
+ *		    with data obtained from the specified
+ *		    I2C EEPROM 'dev_addr'.  Returns 0 for
+ *		    success or 1 for failure.
+ */
+int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo)
+{
+    unsigned char buf[VPD_EEPROM_SIZE];
+    vpd_t *vpd = (vpd_t *)buf;
+    vpd_packet_t *packet;
+
+    if (vpdInfo == NULL)
+	return 1;
+
+     /*
+      * Fill vpdInfo with 0s to blank out
+      * unused fields, fill vpdInfo->ethAddrs
+      * with all 0xffs so that other's code can
+      * determine how many real Ethernet addresses
+      * there are.  OUIs starting with 0xff are
+      * broadcast addresses, and would never be
+      * permantely stored.
+      */
+    memset((void *)vpdInfo, 0, sizeof(VPD));
+    memset((void *)&vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs));
+    vpdInfo->_devAddr = dev_addr;
+
+    /* Read the minimum size first */
+    if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL) {
+	return 1;
+    }
+
+    /* Check validity of VPD data */
+    if (!vpd_is_valid(dev_addr, buf)) {
+	printf("VPD Data is INVALID!\n");
+	return 1;
+    }
+
+    /*
+      * Walk all the packets and populate
+      * the VPD info structure.
+      */
+    packet = (vpd_packet_t *)&vpd->packets;
+    do {
+	switch (packet->identifier) {
+	    case VPD_PID_GI:
+		printf("Error: Illegal VPD value\n");
+		break;
+	    case VPD_PID_PID:
+		if (strlen_ok(packet, MAX_PROD_ID)) {
+		    strncpy(vpdInfo->productId,
+			    (char *)(packet->data), packet->size);
+		}
+		break;
+	    case VPD_PID_REV:
+		if (size_ok(packet, sizeof(char)))
+		    vpdInfo->revisionId = *packet->data;
+		break;
+	    case VPD_PID_SN:
+		if (size_ok(packet, sizeof(unsigned long))) {
+		    vpdInfo->serialNum =
+			*(unsigned long *)packet->data;
+		}
+		break;
+	    case VPD_PID_MANID:
+		if (size_ok(packet, sizeof(unsigned char)))
+		    vpdInfo->manuID = *packet->data;
+		break;
+	    case VPD_PID_PCO:
+		if (size_ok(packet, sizeof(unsigned long))) {
+		    vpdInfo->configOpt =
+			*(unsigned long *)packet->data;
+		}
+		break;
+	    case VPD_PID_SYSCLK:
+		if (size_ok(packet, sizeof(unsigned long)))
+		    vpdInfo->sysClk = *(unsigned long *)packet->data;
+		break;
+	    case VPD_PID_SERCLK:
+		if (size_ok(packet, sizeof(unsigned long)))
+		    vpdInfo->serClk = *(unsigned long *)packet->data;
+		break;
+	    case VPD_PID_FLASH:
+		if (size_ok(packet, 9)) {	/* XXX - hardcoded,
+						   padding in struct */
+		    memcpy(&vpdInfo->flashCfg, packet->data, 9);
+		}
+		break;
+	    case VPD_PID_ETHADDR:
+		memcpy(vpdInfo->ethAddrs, packet->data, packet->size);
+		break;
+	    case VPD_PID_POTS:
+		if (size_ok(packet, sizeof(char)))
+		    vpdInfo->numPOTS = (unsigned)*packet->data;
+		break;
+	    case VPD_PID_DS1:
+		if (size_ok(packet, sizeof(char)))
+		    vpdInfo->numDS1 = (unsigned)*packet->data;
+	    case VPD_PID_GAL:
+	    case VPD_PID_CRC:
+	    case VPD_PID_TERM:
+		break;
+	    default:
+		printf("Warning: Found unknown VPD packet ID 0x%x\n",
+		       packet->identifier);
+		break;
+	}
+    } while ((packet = vpd_get_packet(packet)));
+
+    return 0;
+} /* end get_vpd_data() */
+
+
+/*
+ * vpd_init() - Initialize default VPD environment
+ */
+int vpd_init(unsigned char dev_addr)
+{
+    return (0);
+} /* vpd_init() */
+
+
+/*
+ * vpd_print() - Pretty print the VPD data.
+ */
+void vpd_print(VPD *vpdInfo)
+{
+    const char *const sp    = "";
+    const char *const sfmt  = "%4s%-20s: \"%s\"\n";
+    const char *const cfmt  = "%4s%-20s: '%c'\n";
+    const char *const dfmt  = "%4s%-20s: %ld\n";
+    const char *const hfmt  = "%4s%-20s: %08lX\n";
+    const char *const dsfmt = "%4s%-20s: %d\n";
+    const char *const hsfmt = "%4s%-20s: %04X\n";
+    const char *const dhfmt = "%4s%-20s: %ld (%lX)\n";
+
+    printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr);
+
+    if (vpdInfo->productId[0])
+	printf(sfmt, sp, "Product ID", vpdInfo->productId);
+    else
+	printf(sfmt, sp, "Product ID", "UNKNOWN");
+
+    if (vpdInfo->revisionId)
+	printf(cfmt, sp, "Revision ID", vpdInfo->revisionId);
+
+    if (vpdInfo->serialNum)
+	printf(dfmt, sp, "Serial Number", vpdInfo->serialNum);
+
+    if (vpdInfo->manuID)
+	printf(dfmt, sp, "Manufacture ID", (long)vpdInfo->manuID);
+
+    if (vpdInfo->configOpt)
+	printf(hfmt, sp, "Configuration", vpdInfo->configOpt);
+
+    if (vpdInfo->sysClk)
+	printf(dhfmt, sp, "System Clock", vpdInfo->sysClk, vpdInfo->sysClk);
+
+    if (vpdInfo->serClk)
+	printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk, vpdInfo->serClk);
+
+    if (vpdInfo->numPOTS)
+	printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS);
+
+    if (vpdInfo->numDS1)
+	printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1);
+
+    /* Print Ethernet Addresses */
+    if (vpdInfo->ethAddrs[0][0] != 0xff) {
+	int i, j;
+	printf("%4sEtherNet Address(es): ", sp);
+	for (i = 0; i < MAX_ETH_ADDRS; i++) {
+	    if (vpdInfo->ethAddrs[i][0] != 0xff) {
+		for (j = 0; j < 6; j++) {
+		    printf("%02X", vpdInfo->ethAddrs[i][j]);
+		    if (((j + 1) % 6) != 0)
+			printf(":");
+		    else
+			printf(" ");
+		}
+		if (((i + 1) % 3) == 0) printf("\n%24s: ", sp);
+	    }
+	}
+	printf("\n");
+    }
+
+    if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) {
+	printf("Main Flash Configuration:\n");
+	printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg);
+	printf(hsfmt, sp, "Device ID",      vpdInfo->flashCfg.dev);
+	printf(dsfmt, sp, "Device Width",   vpdInfo->flashCfg.devWidth);
+	printf(dsfmt, sp, "Num. Devices",   vpdInfo->flashCfg.numDevs);
+	printf(dsfmt, sp, "Num. Columns",   vpdInfo->flashCfg.numCols);
+	printf(dsfmt, sp, "Column Width",   vpdInfo->flashCfg.colWidth);
+	printf(dsfmt, sp, "WE Data Width",  vpdInfo->flashCfg.weDataWidth);
+    }
+} /* vpd_print() */
diff --git a/u-boot/board/w7o/vpd.h b/u-boot/board/w7o/vpd.h
new file mode 100644
index 0000000..1b71c8d
--- /dev/null
+++ b/u-boot/board/w7o/vpd.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VPD_H_
+#define _VPD_H_
+
+/*
+ * Main Flash Configuration.
+ */
+typedef struct flashCfg_s {
+    unsigned short mfg;				/* Manufacture ID */
+    unsigned short dev;				/* Device ID */
+    unsigned char devWidth;			/* Device Width */
+    unsigned char numDevs;			/* Number of devices */
+    unsigned char numCols;			/* Number of columns */
+    unsigned char colWidth;			/* Width of a column */
+    unsigned char weDataWidth;			/* Write/Erase Data Width */
+} flashCfg_t;
+
+/*
+ * Vital Product Data - VPD
+ */
+#define MAX_PROD_ID		15
+#define MAX_ETH_ADDRS		10
+typedef unsigned char EthAddr[6];
+typedef struct vpd {
+    unsigned char _devAddr;			/* Device address during read */
+    char productId[MAX_PROD_ID];		/* Product ID */
+    char revisionId;				/* Revision ID as a char */
+    unsigned long serialNum;			/* Serial number */
+    unsigned char  manuID;			/* Manufact ID - byte int */
+    unsigned long configOpt;			/* Config Option - bit field */
+    unsigned long sysClk;			/* System clock in Hertz */
+    unsigned long serClk;			/* Ext. clock in Hertz */
+    flashCfg_t flashCfg;			/* Flash configuration */
+    unsigned long numPOTS;			/* Number of POTS lines */
+    unsigned long numDS1;			/* Number of DS1 circuits */
+    EthAddr ethAddrs[MAX_ETH_ADDRS];		/* Ethernet MAC, 1st = craft */
+} VPD;
+
+
+#define VPD_MAX_EEPROM_SIZE	512		/* Max size VPD EEPROM */
+#define SDRAM_SPD_DATA_SIZE	128		/* Size SPD in VPD EEPROM */
+
+/*
+ * PIDs - Packet Identifiers
+ */
+#define VPD_PID_GI		0x0		/* Guaranted Illegal */
+#define VPD_PID_PID		0x1		/* Product Identifier */
+#define VPD_PID_REV		0x2		/* Product Revision */
+#define VPD_PID_SN		0x3		/* Serial Number */
+#define VPD_PID_MANID		0x4		/* Manufacture ID */
+#define VPD_PID_PCO		0x5		/* Product configuration */
+#define VPD_PID_SYSCLK		0x6		/* System Clock */
+#define VPD_PID_SERCLK		0x7		/* Ser. Clk. Speed in Hertz */
+#define VPD_PID_CRC		0x8		/* VPD CRC */
+#define VPD_PID_FLASH		0x9		/* Flash Configuration */
+#define VPD_PID_ETHADDR		0xA		/* Ethernet Address(es) */
+#define VPD_PID_GAL		0xB		/* Galileo Switch Config */
+#define VPD_PID_POTS		0xC		/* Number of POTS Lines */
+#define VPD_PID_DS1		0xD		/* Number of DS1s */
+#define VPD_PID_TERM		0xFF		/* Termination packet */
+
+/*
+ * VPD - Eyecatcher/Magic
+ */
+#define VPD_EYECATCHER		"W7O"
+#define VPD_EYE_SIZE		3
+typedef struct vpd_header {
+    unsigned char eyecatcher[VPD_EYE_SIZE];	/* eyecatcher - "W7O" */
+    unsigned short size __attribute__((packed)); /* size of EEPROM */
+} vpd_header_t;
+
+
+#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \
+			sizeof(vpd_header_t))
+typedef struct vpd_s {
+    vpd_header_t header;
+    unsigned char packets[VPD_DATA_SIZE];
+} vpd_t;
+
+typedef struct vpd_packet {
+    unsigned char identifier;
+    unsigned char size;
+    unsigned char data[1];
+} vpd_packet_t;
+
+/*
+ * VPD configOpt bit mask
+ */
+#define VPD_HAS_BBRAM		0x1		/* Battery backed SRAM */
+#define VPD_HAS_RTC		0x2		/* Battery backed RTC */
+#define VPD_HAS_EXT_SER_CLK	0x4		/* External serial clock */
+#define VPD_HAS_SER_TRANS_1	0x8		/* COM1 transceiver */
+#define VPD_HAS_SER_TRANS_2	0x10		/* COM2 transceiver */
+#define VPD_HAS_CRAFT_PHY	0x20		/* CRAFT Ethernet */
+#define VPD_HAS_DTT_1		0x40		/* I2C Digital therm. #1 */
+#define VPD_HAS_DTT_2		0x80		/* I2C Digital therm. #2 */
+#define VPD_HAS_1000_UP_LASER	0x100		/* GMM - 1000Mbit Uplink */
+#define VPD_HAS_70KM_UP_LASER	0x200		/* CMM - 70KM Uplink laser */
+#define VPD_HAS_2_UPLINKS	0x400		/* CMM - 2 uplink lasers */
+#define VPD_HAS_FPGA		0x800		/* Has 1 or more FPGAs */
+#define VPD_HAS_DFA		0x1000		/* CLM - Has 2 Fiber Inter. */
+#define VPD_HAS_GAL_SWITCH	0x2000		/* GMM - Has a Gal switch */
+#define VPD_HAS_POTS_LINES	0x4000		/* GMM - Has POTS lines */
+#define VPD_HAS_DS1_CHANNELS	0x8000		/* GMM - Has DS1 channels */
+#define VPD_HAS_CABLE_RETURN	0x10000		/* GBM/GBR - Cable ret. path */
+
+#define VPD_EEPROM_SIZE         (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */
+
+extern int vpd_get_data(unsigned char dev_addr, VPD *vpd);
+extern void vpd_print(VPD *vpdInfo);
+
+#endif /* _VPD_H_ */
diff --git a/u-boot/board/w7o/w7o.c b/u-boot/board/w7o/w7o.c
new file mode 100644
index 0000000..5c84e65
--- /dev/null
+++ b/u-boot/board/w7o/w7o.c
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include "w7o.h"
+#include <asm/processor.h>
+
+#include "vpd.h"
+#include "errors.h"
+#include <watchdog.h>
+
+unsigned long get_dram_size (void);
+void sdram_init(void);
+
+/*
+ * Macros to transform values
+ * into environment strings.
+ */
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_W7OLMG)
+	/*
+	 * Setup GPIO pins - reset devices.
+	 */
+	out32 (PPC405GP_GPIO0_ODR, 0x10000000);	/* one open drain pin */
+	out32 (PPC405GP_GPIO0_OR, 0x3E000000);	/* set output pins to default */
+	out32 (PPC405GP_GPIO0_TCR, 0x7f800000);	/* setup for output */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,
+					   INT0 highest priority */
+
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+#elif defined(CONFIG_W7OLMC)
+	/*
+	 * Setup GPIO pins
+	 */
+	out32 (PPC405GP_GPIO0_ODR, 0x01800000);	/* XCV Done Open Drain */
+	out32 (PPC405GP_GPIO0_OR, 0x03800000);	/* set out pins to default */
+	out32 (PPC405GP_GPIO0_TCR, 0x66C00000);	/* setup for output */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,
+					   INT0 highest priority */
+
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+#else  /* Unknown */
+#    error "Unknown W7O board configuration"
+#endif
+
+	WATCHDOG_RESET ();	/* Reset the watchdog */
+	temp_uart_init ();	/* init the uart for debug */
+	WATCHDOG_RESET ();	/* Reset the watchdog */
+	test_led ();		/* test the LEDs */
+	test_sdram (get_dram_size ());	/* test the dram */
+	log_stat (ERR_POST1);	/* log status,post1 complete */
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	VPD vpd;
+
+	puts ("Board: ");
+
+	/* VPD data present in I2C EEPROM */
+	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
+		/*
+		 * Known board type.
+		 */
+		if (vpd.productId[0] &&
+		    ((strncmp (vpd.productId, "GMM", 3) == 0) ||
+		     (strncmp (vpd.productId, "CMM", 3) == 0))) {
+
+			/* Output board information on startup */
+			printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
+			return (0);
+		}
+	}
+
+	puts ("### Unknown HW ID - assuming NOTHING\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in arch/powerpc/cpu/ppc4xx
+	 */
+	sdram_init();
+
+	return get_dram_size ();
+}
+
+unsigned long get_dram_size (void)
+{
+	int tmp, i, regs[4];
+	int size = 0;
+
+	/* Get bank Size registers */
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);	/* get bank 0 config reg */
+	regs[0] = mfdcr (SDRAM0_CFGDATA);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);	/* get bank 1 config reg */
+	regs[1] = mfdcr (SDRAM0_CFGDATA);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);	/* get bank 2 config reg */
+	regs[2] = mfdcr (SDRAM0_CFGDATA);
+
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);	/* get bank 3 config reg */
+	regs[3] = mfdcr (SDRAM0_CFGDATA);
+
+	/* compute the size, add each bank if enabled */
+	for (i = 0; i < 4; i++) {
+		if (regs[i] & 0x0001) {	/* if enabled, */
+			tmp = ((regs[i] >> (31 - 14)) & 0x7);	/* get size bits */
+			tmp = 0x400000 << tmp;	/* Size bits X 4MB = size */
+			size += tmp;
+		}
+	}
+
+	return size;
+}
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+static void w7o_env_init (VPD * vpd)
+{
+	/*
+	 * Read VPD
+	 */
+	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
+		return;
+
+	/*
+	 * Known board type.
+	 */
+	if (vpd->productId[0] &&
+	    ((strncmp (vpd->productId, "GMM", 3) == 0) ||
+	     (strncmp (vpd->productId, "CMM", 3) == 0))) {
+		char buf[30];
+		char *eth;
+		char *serial = getenv ("serial#");
+		char *ethaddr = getenv ("ethaddr");
+
+		/* Set 'serial#' envvar if serial# isn't set */
+		if (!serial) {
+			sprintf (buf, "%s-%ld", vpd->productId,
+				 vpd->serialNum);
+			setenv ("serial#", buf);
+		}
+
+		/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
+		eth = (char *)(vpd->ethAddrs[0]);
+		if (ethaddr
+		    && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
+			/* Now setup ethaddr */
+			sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+				 eth[0], eth[1], eth[2], eth[3], eth[4],
+				 eth[5]);
+			setenv ("ethaddr", buf);
+		}
+	}
+}				/* w7o_env_init() */
+
+
+int misc_init_r (void)
+{
+	VPD vpd;		/* VPD information */
+
+#if defined(CONFIG_W7OLMG)
+	unsigned long greg;	/* GPIO Register */
+
+	greg = in32 (PPC405GP_GPIO0_OR);
+
+	/*
+	 * XXX - Unreset devices - this should be moved into VxWorks driver code
+	 */
+	greg |= 0x41800000L;	/* SAM, PHY, Galileo */
+
+	out32 (PPC405GP_GPIO0_OR, greg);	/* set output pins to default */
+#endif /* CONFIG_W7OLMG */
+
+	/*
+	 * Initialize W7O environment variables
+	 */
+	w7o_env_init (&vpd);
+
+	/*
+	 * Initialize the FPGA(s).
+	 */
+	if (init_fpga () == 0)
+		test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
+
+	/* More POST testing. */
+	post2 ();
+
+	/* Done with hardware initialization and POST. */
+	log_stat (ERR_POSTOK);
+
+	/* Call silly, fail safe boot init routine */
+	init_fsboot ();
+
+	return (0);
+}
diff --git a/u-boot/board/w7o/w7o.h b/u-boot/board/w7o/w7o.h
new file mode 100644
index 0000000..d1fed02
--- /dev/null
+++ b/u-boot/board/w7o/w7o.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _W7O_H_
+#define _W7O_H_
+#include <config.h>
+
+/* AMCC 405GP PowerPC GPIO registers */
+#define PPC405GP_GPIO0_OR	0xef600700L	/* GPIO Output */
+#define PPC405GP_GPIO0_TCR	0xef600704L	/* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR	0xef600718L	/* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR	0xef60071cL	/* GPIO Input */
+
+/* LMG FPGA <=> CPU GPIO signals */
+#define LMG_XCV_INIT		0x10000000L
+#define LMG_XCV_PROG		0x04000000L
+#define LMG_XCV_DONE		0x00400000L
+#define LMG_XCV_CNFG_0		0x08000000L
+#define LMG_XCV_IRQ_0		0x0L
+
+/* LMC FPGA <=> CPU GPIO signals */
+#define LMC_XCV_INIT		0x00800000L
+#define LMC_XCV_PROG		0x40000000L
+#define LMC_XCV_DONE		0x01000000L
+#define LMC_XCV_CNFG_0		0x00004000L	/* Shared with IRQ 0 */
+#define LMC_XCV_CNFG_1		0x00002000L	/* Shared with IRQ 1 */
+#define LMC_XCV_CNFG_2		0x00001000L	/* Shared with IRQ 2 */
+#define LMC_XCV_IRQ_0		0x00080000L	/* Shared with GPIO 17 */
+#define LMC_XCV_IRQ_1		0x00040000L	/* Shared with GPIO 18 */
+#define LMC_XCV_IRQ_3		0x00020000L	/* Shared tiwht GPIO 19 */
+
+
+/*
+ * Setup FPGA <=> GPIO mappings
+ */
+#if defined(CONFIG_W7OLMG)
+# define GPIO_XCV_INIT		LMG_XCV_INIT
+# define GPIO_XCV_PROG		LMG_XCV_PROG
+# define GPIO_XCV_DONE		LMG_XCV_DONE
+# define GPIO_XCV_CNFG		LMG_XCV_CNFG_0
+# define GPIO_XCV_IRQ		LMG_XCV_IRQ_0
+# define GPIO_GPIO_1		0x40000000L
+# define GPIO_GPIO_6		0x02000000L
+# define GPIO_GPIO_7		0x01000000L
+# define GPIO_GPIO_8		0x00800000L
+#elif defined(CONFIG_W7OLMC)
+# define GPIO_XCV_INIT		LMC_XCV_INIT
+# define GPIO_XCV_PROG		LMC_XCV_PROG
+# define GPIO_XCV_DONE		LMC_XCV_DONE
+# define GPIO_XCV_CNFG		LMC_XCV_CNFG_0
+# define GPIO_XCV_IRQ		LMC_XCV_IRQ_0
+#else
+# error "Unknown W7O board configuration"
+#endif
+
+/* Power On Self Tests */
+extern void post2(void);
+extern int test_led(void);
+extern int test_sdram(unsigned long size);
+extern void test_fpga(unsigned short *daddr);
+
+/* FGPA */
+extern int init_fpga(void);
+
+/* Misc */
+extern int temp_uart_init(void);
+extern void init_fsboot(void);
+
+#endif /* _W7O_H_ */
diff --git a/u-boot/board/w7o/watchdog.c b/u-boot/board/w7o/watchdog.c
new file mode 100644
index 0000000..131399c
--- /dev/null
+++ b/u-boot/board/w7o/watchdog.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * W7O board level hardware watchdog.
+ */
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+void hw_watchdog_reset(void)
+{
+    volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000);
+
+    /*
+     * Read the LMG's hwd register and toggle the
+     * watchdog bit to reset it.   On the LMC, just
+     * reading it is enough, but toggling the bit
+     * doen't hurt either.
+     */
+    *hwd = *hwd ^ 0x8000;
+
+} /* hw_watchdog_reset() */
+
+#endif /* CONFIG_HW_WATCHDOG */
diff --git a/u-boot/board/westel/amx860/Makefile b/u-boot/board/westel/amx860/Makefile
new file mode 100644
index 0000000..12e4aa6
--- /dev/null
+++ b/u-boot/board/westel/amx860/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/westel/amx860/amx860.c b/u-boot/board/westel/amx860/amx860.c
new file mode 100644
index 0000000..91dcc0d
--- /dev/null
+++ b/u-boot/board/westel/amx860/amx860.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint edo_60ns[] =
+{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
+  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
+  0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08,
+  0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48,
+  0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: AMX860\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
+
+	upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
+
+#ifndef CONFIG_AMX_RAM_EXT
+	memctl->memc_mptpr = 0x0400; /* divide by 16 */
+#else
+	memctl->memc_mptpr = 0x0200;
+#endif
+
+	memctl->memc_mamr = 0x30a21114;
+	memctl->memc_or2 = 0xffc00800;
+#ifndef CONFIG_AMX_RAM_EXT
+	memctl->memc_br2 = 0x81;
+
+	return (4 << 20);
+#else
+	memctl->memc_or1 = 0xff000800;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_br2 = 0x01000081;
+
+	return (20 << 20);
+#endif
+}
diff --git a/u-boot/board/westel/amx860/flash.c b/u-boot/board/westel/amx860/flash.c
new file mode 100644
index 0000000..fe8bce4
--- /dev/null
+++ b/u-boot/board/westel/amx860/flash.c
@@ -0,0 +1,637 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+#if defined(FLASH_BASE1_PRELIM) && (FLASH_BASE1_PRELIM != 0)
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+#else
+	size_b1 = 0;
+#endif	/* FLASH_BASE1_PRELIM */
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	DEBUGF ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				   BR_MS_GPCM | BR_V;
+
+		DEBUGF("## BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+
+# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+# endif
+
+# ifdef CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+#ifndef CONFIG_AMX_RAM_EXT
+		memctl->memc_br1 = 0;		/* invalidate bank */
+		memctl->memc_or1 = 0;		/* invalidate bank */
+#endif
+
+		DEBUGF("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for uniform sector type	*/
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00040000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/u-boot/board/westel/amx860/u-boot.lds b/u-boot/board/westel/amx860/u-boot.lds
new file mode 100644
index 0000000..206ec70
--- /dev/null
+++ b/u-boot/board/westel/amx860/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+    net/libnet.o			(.text*)
+    board/westel/amx860/libamx860.o	(.text*)
+    *(.text.*printf)
+
+    . = env_offset;
+    common/env_embedded.o		(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/westel/amx860/u-boot.lds.debug b/u-boot/board/westel/amx860/u-boot.lds.debug
new file mode 100644
index 0000000..9c1e3ec
--- /dev/null
+++ b/u-boot/board/westel/amx860/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/xaeniax/Makefile b/u-boot/board/xaeniax/Makefile
new file mode 100644
index 0000000..0a2fe96
--- /dev/null
+++ b/u-boot/board/xaeniax/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= xaeniax.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xaeniax/flash.c b/u-boot/board/xaeniax/flash.c
new file mode 100644
index 0000000..b051c89
--- /dev/null
+++ b/u-boot/board/xaeniax/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW    FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/xaeniax/xaeniax.c b/u-boot/board/xaeniax/xaeniax.c
new file mode 100644
index 0000000..40b0f3b
--- /dev/null
+++ b/u-boot/board/xaeniax/xaeniax.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of xaeniax */
+	gd->bd->bi_arch_number = 585;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/xes/common/Makefile b/u-boot/board/xes/common/Makefile
new file mode 100644
index 0000000..39d105f
--- /dev/null
+++ b/u-boot/board/xes/common/Makefile
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
+COBJS-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
+COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
+COBJS-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
+COBJS-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
+COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xes/common/actl_nand.c b/u-boot/board/xes/common/actl_nand.c
new file mode 100644
index 0000000..465aeb0
--- /dev/null
+++ b/u-boot/board/xes/common/actl_nand.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+				CONFIG_SYS_NAND_ACTL_ALE |
+				CONFIG_SYS_NAND_ACTL_NCE);
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+		if (ctrl & NAND_NCE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_addr_hwcontrol;
+	nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+	return 0;
+}
diff --git a/u-boot/board/xes/common/board.c b/u-boot/board/xes/common/board.c
new file mode 100644
index 0000000..738f0a6
--- /dev/null
+++ b/u-boot/board/xes/common/board.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+	char name[] = CONFIG_SYS_BOARD_NAME;
+	char *s;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+	s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+	s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+	s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+	s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+	s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+	s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+	s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+	s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+	s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+	s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+	s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+	s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+	s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+	s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+	name[strlen(name) - 1] += get_board_derivative();
+	printf("Board: X-ES %s %s SBC\n", name, s);
+
+	/* Display board specific information */
+	puts("       ");
+	if ((s = getenv("board_rev")))
+		printf("Rev %s, ", s);
+	if ((s = getenv("serial#")))
+		printf("Serial# %s, ", s);
+	if ((s = getenv("board_cfg")))
+		printf("Cfg %s", s);
+	puts("\n");
+
+	return 0;
+}
diff --git a/u-boot/board/xes/common/fsl_8xxx_clk.c b/u-boot/board/xes/common/fsl_8xxx_clk.c
new file mode 100644
index 0000000..20d0a30
--- /dev/null
+++ b/u-boot/board/xes/common/fsl_8xxx_clk.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/*
+ * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
+ */
+unsigned long get_board_sys_clk(ulong dummy)
+{
+#if defined(CONFIG_MPC85xx)
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#elif defined(CONFIG_MPC86xx)
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+	if (in_be32(&gur->gpporcr) & 0x10000)
+		return 66666666;
+	else
+#ifdef CONFIG_P2020
+		return 100000000;
+#else
+		return 50000000;
+#endif
+}
+
+#ifdef CONFIG_MPC85xx
+/*
+ * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ * Note: 86xx doesn't support asynchronous DDR clk
+ */
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
+
+	if (ddr_ratio == 0x7)
+		return get_board_sys_clk(dummy);
+
+#ifdef CONFIG_P2020
+	if (in_be32(&gur->gpporcr) & 0x20000)
+		return 66666666;
+	else
+		return 100000000;
+#else
+	return 66666666;
+#endif
+}
+#endif
diff --git a/u-boot/board/xes/common/fsl_8xxx_misc.c b/u-boot/board/xes/common/fsl_8xxx_misc.c
new file mode 100644
index 0000000..36e9146
--- /dev/null
+++ b/u-boot/board/xes/common/fsl_8xxx_misc.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+	if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_NVM_WP)
+		return 1;
+
+	return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number.  For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+       volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+       volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+       /*
+	* The top 4 lines of the local bus address are pulled low/high and
+	* can be read to determine the least significant digit of a board's
+	* model number.
+	*/
+       return gur->gpporcr >> 28;
+}
diff --git a/u-boot/board/xes/common/fsl_8xxx_misc.h b/u-boot/board/xes/common/fsl_8xxx_misc.h
new file mode 100644
index 0000000..ecc70da
--- /dev/null
+++ b/u-boot/board/xes/common/fsl_8xxx_misc.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
+
+uint get_board_derivative(void);
+
+#endif /* __FSL_8XXX_MISC_H__ */
diff --git a/u-boot/board/xes/common/fsl_8xxx_pci.c b/u-boot/board/xes/common/fsl_8xxx_pci.c
new file mode 100644
index 0000000..28c83c7
--- /dev/null
+++ b/u-boot/board/xes/common/fsl_8xxx_pci.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+void pci_init_board(void)
+{
+	int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr = in_be32(&gur->devdisr);
+	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
+	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
+	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
+	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+			pci_32 ? 32 : 64,
+			pcix ? "PCIX" : "PCI",
+			pci_spd_norm ? ">=" : "<=",
+			pcix ? freq * 2 : freq,
+			pcie_ep ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI1: disabled\n");
+	}
+#elif defined CONFIG_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	/* PCI1 not present on MPC8572 */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_pci_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/u-boot/board/xes/xpedite1000/Makefile b/u-boot/board/xes/xpedite1000/Makefile
new file mode 100644
index 0000000..5b0ffc2
--- /dev/null
+++ b/u-boot/board/xes/xpedite1000/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xes/xpedite1000/config.mk b/u-boot/board/xes/xpedite1000/config.mk
new file mode 100644
index 0000000..b648bc6
--- /dev/null
+++ b/u-boot/board/xes/xpedite1000/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# XES XPedite1000 PPC440GX
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/u-boot/board/xes/xpedite1000/init.S b/u-boot/board/xes/xpedite1000/init.S
new file mode 100644
index 0000000..27769cc
--- /dev/null
+++ b/u-boot/board/xes/xpedite1000/init.S
@@ -0,0 +1,50 @@
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+	tlbtab_end
diff --git a/u-boot/board/xes/xpedite1000/u-boot.lds.debug b/u-boot/board/xes/xpedite1000/u-boot.lds.debug
new file mode 100644
index 0000000..a747578
--- /dev/null
+++ b/u-boot/board/xes/xpedite1000/u-boot.lds.debug
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/xes/xpedite1000/init.o (.text)
+    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
+    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
+    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
+    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
+    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
+    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+    lib/zlib.o		(.text)
+
+/*    common/env_embedded.o(.text) */
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/u-boot/board/xes/xpedite1000/xpedite1000.c b/u-boot/board/xes/xpedite1000/xpedite1000.c
new file mode 100644
index 0000000..a3534d2
--- /dev/null
+++ b/u-boot/board/xes/xpedite1000/xpedite1000.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	unsigned long sdrreg;
+
+	/*
+	 * Enable GPIO for pins 18 - 24
+	 * 18 = SEEPROM_WP
+	 * 19 = #M_RST
+	 * 20 = #MONARCH
+	 * 21 = #LED_ALARM
+	 * 22 = #LED_ACT
+	 * 23 = #LED_STATUS1
+	 * 24 = #LED_STATUS2
+	 */
+	mfsdr(SDR0_PFC0, sdrreg);
+	mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
+	out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	LED0_OFF();
+	LED1_OFF();
+	LED2_OFF();
+	LED3_OFF();
+
+	/* Setup the external bus controller/chip selects */
+	mtebc(PB0AP, 0x04055200);	/* 16MB Strata FLASH */
+	mtebc(PB0CR, 0xff098000);	/* BAS=0xff0 16MB R/W 8-bit */
+	mtebc(PB1AP, 0x04055200);	/* 512KB Socketed AMD FLASH */
+	mtebc(PB1CR, 0xfe018000);	/* BAS=0xfe0 1MB R/W 8-bit */
+	mtebc(PB6AP, 0x05006400);	/* 32-64MB AMD MirrorBit FLASH */
+	mtebc(PB6CR, 0xf00da000);	/* BAS=0xf00 64MB R/W i6-bit */
+	mtebc(PB7AP, 0x05006400);	/* 32-64MB AMD MirrorBit FLASH */
+	mtebc(PB7CR, 0xf40da000);	/* BAS=0xf40 64MB R/W 16-bit */
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr(UIC1PR, 0xfffffe00);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x01c00000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00ff8000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC0PR, 0xfc000000);	/* */
+	mtdcr(UIC0TR, 0x00000000);	/* */
+	mtdcr(UIC0VR, 0x00000001);	/* */
+
+	LED0_ON();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s;
+
+	printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
+	printf("       ");
+	s = getenv("board_rev");
+	if (s)
+		printf("Rev %s, ", s);
+	s = getenv("serial#");
+	if (s)
+		printf("Serial# %s, ", s);
+	s = getenv("board_cfg");
+	if (s)
+		printf("Cfg %s", s);
+	printf("\n");
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return spd_sdram();
+}
+
+/*
+ * Override weak pci_pre_init()
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller * hose)
+{
+	unsigned long strap;
+
+	/* See if we're supposed to setup the pci */
+	mfsdr(SDR0_SDSTP1, strap);
+	if ((strap & 0x00010000) == 0)
+		return 0;
+
+#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
+	/* Setup System Device Register PCIL0_XCR */
+	mfsdr(SDR0_XCR, strap);
+	strap &= 0x0f000000;
+	mtsdr(SDR0_XCR, strap);
+#endif
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+	return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return ctrlc();
+}
+#endif
diff --git a/u-boot/board/xes/xpedite517x/Makefile b/u-boot/board/xes/xpedite517x/Makefile
new file mode 100644
index 0000000..cac32e9
--- /dev/null
+++ b/u-boot/board/xes/xpedite517x/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xes/xpedite517x/ddr.c b/u-boot/board/xes/xpedite517x/ddr.c
new file mode 100644
index 0000000..1d57d09
--- /dev/null
+++ b/u-boot/board/xes/xpedite517x/ddr.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+#ifdef SPD_EEPROM_ADDRESS2
+		} else if (ctrl_num == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS2;
+#endif
+		} else {
+			/* An inalid ctrl number was give, use default SPD */
+			printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num);
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork.  These are:
+ *   1.) CPO (Read Capture Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths and
+ *                   chip-specific internal delays.
+ *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths.
+ *                   Unless clock and DQ lanes are very different
+ *                   lengths (>2"), this should be set to the nominal value
+ *                   of 1/2 clock delay.
+ *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *           - DDR_SDRAM_CLK_CNTL register
+ *           Source: Signal Integrity Simulations
+ *   4.) 2T Timing on Addr/Ctl
+ *           - TIMING_CFG_2 register
+ *           Source: Signal Integrity Simulations
+ *           Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     PCB routing on the XPedite5170 is nearly identical to the XPedite5370
+ *     so we use the XPedite5370 settings as a basis for the XPedite5170.
+ */
+
+typedef struct board_memctl_options {
+	uint16_t datarate_mhz_low;
+	uint16_t datarate_mhz_high;
+	uint8_t clk_adjust;
+	uint8_t cpo_override;
+	uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 9,
+			.write_data_delay	= 2,
+		},
+	},
+	{
+		/* Controller 1 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 7,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			dimm_params_t *pdimm,
+			unsigned int ctrl_num)
+{
+	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+	sys_info_t sysinfo;
+	int i;
+	unsigned int datarate;
+
+	get_sys_info(&sysinfo);
+	datarate = fsl_ddr_get_mem_data_rate() / 1000000;
+
+	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+		if ((bopts[i].datarate_mhz_low <= datarate) &&
+		    (bopts[i].datarate_mhz_high >= datarate)) {
+			debug("controller %d:\n", ctrl_num);
+			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+			debug(" cpo = %d\n", bopts[i].cpo_override);
+			debug(" write_data_delay = %d\n",
+				bopts[i].write_data_delay);
+			popts->clk_adjust = bopts[i].clk_adjust;
+			popts->cpo_override = bopts[i].cpo_override;
+			popts->write_data_delay = bopts[i].write_data_delay;
+		}
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/xes/xpedite517x/law.c b/u-boot/board/xes/xpedite517x/law.c
new file mode 100644
index 0000000..df23df1
--- /dev/null
+++ b/u-boot/board/xes/xpedite517x/law.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE
+	/* NAND LAW covers 2 NAND flashes */
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/xes/xpedite517x/xpedite517x.c b/u-boot/board/xes/xpedite517x/xpedite517x.c
new file mode 100644
index 0000000..61443aa
--- /dev/null
+++ b/u-boot/board/xes/xpedite517x/xpedite517x.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+#endif
+
+/*
+ * Print out which flash was booted from and if booting from the 2nd flash,
+ * swap flash chip selects to maintain consistent flash numbering/addresses.
+ */
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = fsl_ddr_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize and enable DDR ECC */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	return dram_size;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/xes/xpedite520x/Makefile b/u-boot/board/xes/xpedite520x/Makefile
new file mode 100644
index 0000000..a774816
--- /dev/null
+++ b/u-boot/board/xes/xpedite520x/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xes/xpedite520x/ddr.c b/u-boot/board/xes/xpedite520x/ddr.c
new file mode 100644
index 0000000..c5616d5
--- /dev/null
+++ b/u-boot/board/xes/xpedite520x/ddr.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+	/* We use soldered memory, but use an SPD EEPROM to describe it.
+	 * The SPD has an unspecified dimm type, but the DDR2 initialization
+	 * code requires a specific type to be specified. This sets the type
+	 * as a standard unregistered SO-DIMM. */
+	if (spd->dimm_type == 0) {
+		spd->dimm_type = 0x4;
+		((uchar *)spd)[63] += 0x4;
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 9;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/xes/xpedite520x/law.c b/u-boot/board/xes/xpedite520x/law.c
new file mode 100644
index 0000000..5c1fcd2
--- /dev/null
+++ b/u-boot/board/xes/xpedite520x/law.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/xes/xpedite520x/tlb.c b/u-boot/board/xes/xpedite520x/tlb.c
new file mode 100644
index 0000000..bd7bff8
--- /dev/null
+++ b/u-boot/board/xes/xpedite520x/tlb.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+	/* *I*G* - PCI IO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/xes/xpedite520x/xpedite520x.c b/u-boot/board/xes/xpedite520x/xpedite520x.c
new file mode 100644
index 0000000..c79171d
--- /dev/null
+++ b/u-boot/board/xes/xpedite520x/xpedite520x.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/u-boot/board/xes/xpedite537x/Makefile b/u-boot/board/xes/xpedite537x/Makefile
new file mode 100644
index 0000000..86138f9
--- /dev/null
+++ b/u-boot/board/xes/xpedite537x/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xes/xpedite537x/ddr.c b/u-boot/board/xes/xpedite537x/ddr.c
new file mode 100644
index 0000000..4d3f255
--- /dev/null
+++ b/u-boot/board/xes/xpedite537x/ddr.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		if (ctrl_num == 1)
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork.  These are:
+ *   1.) CPO (Read Capture Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths and
+ *                   chip-specific internal delays.
+ *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths.
+ *                   Unless clock and DQ lanes are very different
+ *                   lengths (>2"), this should be set to the nominal value
+ *                   of 1/2 clock delay.
+ *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *           - DDR_SDRAM_CLK_CNTL register
+ *           Source: Signal Integrity Simulations
+ *   4.) 2T Timing on Addr/Ctl
+ *           - TIMING_CFG_2 register
+ *           Source: Signal Integrity Simulations
+ *           Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite5370 DDR2-600 read delay calculations ======
+ *
+ *     See Freescale's App Note AN2583 as refrence.  This document also
+ *     contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ *     For MPC8572E
+ *     Minimum chip delay (Ch 0): 1.372ns
+ *     Maximum chip delay (Ch 0): 2.914ns
+ *     Minimum chip delay (Ch 1): 1.220ns
+ *     Maximum chip delay (Ch 1): 2.595ns
+ *
+ *     CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
+ *
+ *     Minimum delay calc (Ch 0):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     2.3" * 180 - 400ps     + 1.9" * 180         + 2080ps     + 1372ps
+ *                                                 = 3808ps
+ *                                                 = 3.808ns
+ *
+ *     Maximum delay calc (Ch 0):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ *     2.3" * 180 + 400ps     + 2.4" * 180         + 2080ps     + 2914ps
+ *                                                 = 6240ps
+ *                                                 = 6.240ns
+ *
+ *     Minimum delay calc (Ch 1):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180- 400ps     + 0.7" * 180         + 2080ps     + 1220ps
+ *                                                 = 3288ps
+ *                                                 = 3.288ns
+ *
+ *     Maximum delay calc (Ch 1):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180+ 400ps     + 1.1" * 180         + 2080ps     + 2595ps
+ *                                                 = 5536ps
+ *                                                 = 5.536ns
+ *
+ *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
+ *              This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
+ *              This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
+ *
+ *
+ *     ====== XPedite5370 DDR2-800 read delay calculations ======
+ *
+ *     See Freescale's App Note AN2583 as refrence.  This document also
+ *     contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ *     For MPC8572E
+ *     Minimum chip delay (Ch 0): 1.372ns
+ *     Maximum chip delay (Ch 0): 2.914ns
+ *     Minimum chip delay (Ch 1): 1.220ns
+ *     Maximum chip delay (Ch 1): 2.595ns
+ *
+ *     CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
+ *
+ *     Minimum delay calc (Ch 0):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     2.3" * 180 - 350ps     + 1.9" * 180         + 1563ps     + 1372ps
+ *                                                 = 3341ps
+ *                                                 = 3.341ns
+ *
+ *     Maximum delay calc (Ch 0):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ *     2.3" * 180 + 350ps     + 2.4" * 180         + 1563ps     + 2914ps
+ *                                                 = 5673ps
+ *                                                 = 5.673ns
+ *
+ *     Minimum delay calc (Ch 1):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180- 350ps     + 0.7" * 180         + 1563ps     + 1220ps
+ *                                                 = 2822ps
+ *                                                 = 2.822ns
+ *
+ *     Maximum delay calc (Ch 1):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180+ 350ps     + 1.1" * 180         + 1563ps     + 2595ps
+ *                                                 = 4968ps
+ *                                                 = 4.968ns
+ *
+ *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
+ *              This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
+ *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
+ *              This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *
+ * Write latency (WR_DATA_DELAY) is calculated by doing the following:
+ *
+ *      The DDR SDRAM specification requires DQS be received no sooner than
+ *      75% of an SDRAM clock period—and no later than 125% of a clock
+ *      period—from the capturing clock edge of the command/address at the
+ *      SDRAM.
+ *
+ * Based on the above tracelengths, the following are calculated:
+ *      Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 =  0.342ns
+ *      Ch. 0 8572 to DRAM propagation (CLKs) :     2.3" * 180 =  0.414ns
+ *      Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 =  0.126ns
+ *      Ch. 1 8572 to DRAM propagation (CLKs   ) : 1.47" * 180 =  0.264ns
+ *
+ * Difference in arrival time CLK vs. DQS:
+ *      Ch. 0 0.072ns
+ *      Ch. 1 0.138ns
+ *
+ *      Both of these values are much less than 25% of the clock
+ *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
+ *      the 1/2 cycle which normally aligns the first DQS transition
+ *      exactly WL (CAS latency minus one cycle) after the CAS strobe.
+ *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
+ *      terminology corresponds to exactly one clock period delay after
+ *      the CAS strobe. (due to the fact that the "delay" is referenced
+ *      from the *falling* edge of the CLK, just after the rising edge
+ *      which the CAS strobe is latched on.
+ */
+
+typedef struct board_memctl_options {
+	uint16_t datarate_mhz_low;
+	uint16_t datarate_mhz_high;
+	uint8_t clk_adjust;
+	uint8_t cpo_override;
+	uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 9,
+			.write_data_delay	= 2,
+		},
+	},
+	{
+		/* Controller 1 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 7,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+	sys_info_t sysinfo;
+	int i;
+	unsigned int datarate;
+
+	get_sys_info(&sysinfo);
+	datarate = sysinfo.freqDDRBus / 1000 / 1000;
+
+	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+		if ((bopts[i].datarate_mhz_low <= datarate) &&
+		    (bopts[i].datarate_mhz_high >= datarate)) {
+			debug("controller %d:\n", ctrl_num);
+			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+			debug(" cpo = %d\n", bopts[i].cpo_override);
+			debug(" write_data_delay = %d\n",
+			      bopts[i].write_data_delay);
+			popts->clk_adjust = bopts[i].clk_adjust;
+			popts->cpo_override = bopts[i].cpo_override;
+			popts->write_data_delay = bopts[i].write_data_delay;
+		}
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/u-boot/board/xes/xpedite537x/law.c b/u-boot/board/xes/xpedite537x/law.c
new file mode 100644
index 0000000..54c28da
--- /dev/null
+++ b/u-boot/board/xes/xpedite537x/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/xes/xpedite537x/tlb.c b/u-boot/board/xes/xpedite537x/tlb.c
new file mode 100644
index 0000000..a465ce3
--- /dev/null
+++ b/u-boot/board/xes/xpedite537x/tlb.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/xes/xpedite537x/xpedite537x.c b/u-boot/board/xes/xpedite537x/xpedite537x.c
new file mode 100644
index 0000000..d074495
--- /dev/null
+++ b/u-boot/board/xes/xpedite537x/xpedite537x.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/xes/xpedite550x/Makefile b/u-boot/board/xes/xpedite550x/Makefile
new file mode 100644
index 0000000..7bc224c
--- /dev/null
+++ b/u-boot/board/xes/xpedite550x/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xes/xpedite550x/ddr.c b/u-boot/board/xes/xpedite550x/ddr.c
new file mode 100644
index 0000000..38a4597
--- /dev/null
+++ b/u-boot/board/xes/xpedite550x/ddr.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr3_spd_eeprom_t));
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+/*
+ *     There are traditionally three board-specific SDRAM timing parameters
+ *     which must be calculated based on the particular PCB artwork.  These are:
+ *     1.) CPO (Read Capture Delay)
+ *	       - TIMING_CFG_2 register
+ *	       Source: Calculation based on board trace lengths and
+ *		       chip-specific internal delays.
+ *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *	       - DDR_SDRAM_CLK_CNTL register
+ *	       Source: Signal Integrity Simulations
+ *     3.) 2T Timing on Addr/Ctl
+ *	       - TIMING_CFG_2 register
+ *	       Source: Signal Integrity Simulations
+ *	       Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ *     The P2020 processor provides an autoleveling option. Setting CPO to
+ *     0x1f enables this auto configuration.
+ */
+
+typedef struct {
+	unsigned short datarate_mhz_low;
+	unsigned short datarate_mhz_high;
+	unsigned char clk_adjust;
+	unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR3-600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+		{
+			/* DDR3-800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/*
+	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->twoT_en = 0;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * Enable on-die termination.
+	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
+	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = 3;
+}
diff --git a/u-boot/board/xes/xpedite550x/law.c b/u-boot/board/xes/xpedite550x/law.c
new file mode 100644
index 0000000..66f1cf9
--- /dev/null
+++ b/u-boot/board/xes/xpedite550x/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/u-boot/board/xes/xpedite550x/tlb.c b/u-boot/board/xes/xpedite550x/tlb.c
new file mode 100644
index 0000000..cf3ff4d
--- /dev/null
+++ b/u-boot/board/xes/xpedite550x/tlb.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/u-boot/board/xes/xpedite550x/xpedite550x.c b/u-boot/board/xes/xpedite550x/xpedite550x.c
new file mode 100644
index 0000000..6f91c83
--- /dev/null
+++ b/u-boot/board/xes/xpedite550x/xpedite550x.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/u-boot/board/xilinx/common/xbasic_types.c b/u-boot/board/xilinx/common/xbasic_types.c
new file mode 100644
index 0000000..c3a171a
--- /dev/null
+++ b/u-boot/board/xilinx/common/xbasic_types.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+     *
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.c
+*
+* This file contains basic functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+unsigned int XAssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+u32 XWaitInAssert = TRUE;
+
+/* The callback function to be invoked when an assert is taken */
+static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implements assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the XWaitInAssert variable.
+*
+* @param    File is the name of the filename of the source
+* @param    Line is the linenumber within File
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XAssert(char *File, int Line)
+{
+	/* if the callback has been set then invoke it */
+	if (XAssertCallbackRoutine != NULL) {
+		(*XAssertCallbackRoutine) (File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (XWaitInAssert) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    Routine is the callback to be invoked when an assert is taken
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void
+XAssertSetCallback(XAssertCallback Routine)
+{
+	XAssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XNullHandler(void *NullParameter)
+{
+}
diff --git a/u-boot/board/xilinx/common/xbasic_types.h b/u-boot/board/xilinx/common/xbasic_types.h
new file mode 100644
index 0000000..ef0b7c2
--- /dev/null
+++ b/u-boot/board/xilinx/common/xbasic_types.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+* This file contains basic types for Xilinx software IP.  These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*		      compiler warnings
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H		/* prevent circular inclusions */
+#define XBASIC_TYPES_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+/** Null */
+
+#define XCOMPONENT_IS_READY	0x11111111	/* component has been initialized */
+#define XCOMPONENT_IS_STARTED	0x22222222	/* component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED	0
+#define XTEST_FAILED	1
+
+#define XASSERT_NONE	 0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+/** @name Primitive types
+ * These primitive types are created for transportability.
+ * They are dependent upon the target architecture.
+ * @{
+ */
+#include <linux/types.h>
+
+typedef struct {
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return
+*
+* The upper 32 bits of the 64 bit word.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return
+*
+* The lower 32 bits of the 64 bit word.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+*	 the assert occurs.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression)			\
+{							\
+	if (expression) {				\
+		XAssertStatus = XASSERT_NONE;		\
+	} else {					\
+		XAssert(__FILE__, __LINE__);		\
+		XAssertStatus = XASSERT_OCCURRED;	\
+		return;					\
+	}						\
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+*	 the assert occurs.
+*
+* @return
+*
+* Returns 0 unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression)		   \
+{						   \
+	if (expression) {			   \
+		XAssertStatus = XASSERT_NONE;	   \
+	} else {				   \
+		XAssert(__FILE__, __LINE__);	   \
+		XAssertStatus = XASSERT_OCCURRED;  \
+		return 0;			   \
+	}					   \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS()			   \
+{						   \
+	XAssert(__FILE__, __LINE__);		   \
+	XAssertStatus = XASSERT_OCCURRED;	   \
+	return;					   \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS()		   \
+{						   \
+	XAssert(__FILE__, __LINE__);		   \
+	XAssertStatus = XASSERT_OCCURRED;	   \
+	return 0;				   \
+}
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+void XNullHandler(void *NullParameter);
+
+#endif	/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xbuf_descriptor.h b/u-boot/board/xilinx/common/xbuf_descriptor.h
new file mode 100644
index 0000000..fdd51d5
--- /dev/null
+++ b/u-boot/board/xilinx/common/xbuf_descriptor.h
@@ -0,0 +1,252 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xbuf_descriptor.h
+*
+* DESCRIPTION:
+*
+* This file contains the interface for the XBufDescriptor component.
+* The XBufDescriptor component is a passive component that only maps over
+* a buffer descriptor data structure shared by the scatter gather DMA hardware
+* and software. The component's primary purpose is to provide encapsulation of
+* the buffer descriptor processing.  See the source file xbuf_descriptor.c for
+* details.
+*
+* NOTES:
+*
+* Most of the functions of this component are implemented as macros in order
+* to optimize the processing.  The names are not all uppercase such that they
+* can be switched between macros and functions easily.
+*
+******************************************************************************/
+
+#ifndef XBUF_DESCRIPTOR_H	/* prevent circular inclusions */
+#define XBUF_DESCRIPTOR_H	/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xdma_channel_i.h"
+
+/************************** Constant Definitions *****************************/
+
+/* The following constants allow access to all fields of a buffer descriptor
+ * and are necessary at this level of visibility to allow macros to access
+ * and modify the fields of a buffer descriptor.  It is not expected that the
+ * user of a buffer descriptor would need to use these constants.
+ */
+
+#define XBD_DEVICE_STATUS_OFFSET    0
+#define XBD_CONTROL_OFFSET	    1
+#define XBD_SOURCE_OFFSET	    2
+#define XBD_DESTINATION_OFFSET	    3
+#define XBD_LENGTH_OFFSET	    4
+#define XBD_STATUS_OFFSET	    5
+#define XBD_NEXT_PTR_OFFSET	    6
+#define XBD_ID_OFFSET		    7
+#define XBD_FLAGS_OFFSET	    8
+#define XBD_RQSTED_LENGTH_OFFSET    9
+
+#define XBD_SIZE_IN_WORDS	    10
+
+/*
+ * The following constants define the bits of the flags field of a buffer
+ * descriptor
+ */
+
+#define XBD_FLAGS_LOCKED_MASK	    1UL
+
+/**************************** Type Definitions *******************************/
+
+typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/* each of the following macros are named the same as functions rather than all
+ * upper case in order to allow either the macros or the functions to be
+ * used, see the source file xbuf_descriptor.c for documentation
+ */
+
+#define XBufDescriptor_Initialize(InstancePtr)			\
+{								\
+    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0);   \
+    (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \
+    (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \
+}
+
+#define XBufDescriptor_GetControl(InstancePtr)	 \
+    (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET))
+
+#define XBufDescriptor_SetControl(InstancePtr, Control)	 \
+    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control)
+
+#define XBufDescriptor_IsLastControl(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \
+	       XDC_CONTROL_LAST_BD_MASK)
+
+#define XBufDescriptor_SetLast(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK)
+
+#define XBufDescriptor_GetSrcAddress(InstancePtr) \
+    ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET)))
+
+#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \
+    (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source)
+
+#define XBufDescriptor_GetDestAddress(InstancePtr) \
+    ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET)))
+
+#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \
+    (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination)
+
+#define XBufDescriptor_GetLength(InstancePtr)				\
+    (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) -	\
+	      *((u32 *)InstancePtr + XBD_LENGTH_OFFSET))
+
+#define XBufDescriptor_SetLength(InstancePtr, Length)			    \
+{									    \
+    (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length));    \
+    (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
+}
+
+#define XBufDescriptor_GetStatus(InstancePtr)	 \
+    (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET))
+
+#define XBufDescriptor_SetStatus(InstancePtr, Status)	 \
+    (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status)
+
+#define XBufDescriptor_IsLastStatus(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \
+	       XDC_STATUS_LAST_BD_MASK)
+
+#define XBufDescriptor_GetDeviceStatus(InstancePtr) \
+    ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET)))
+
+#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \
+    (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status)
+
+#define XBufDescriptor_GetNextPtr(InstancePtr) \
+    (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET))
+
+#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \
+    (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr)
+
+#define XBufDescriptor_GetId(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET))
+
+#define XBufDescriptor_SetId(InstancePtr, Id) \
+    (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id)
+
+#define XBufDescriptor_GetFlags(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET))
+
+#define XBufDescriptor_SetFlags(InstancePtr, Flags) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags)
+
+#define XBufDescriptor_Lock(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK)
+
+#define XBufDescriptor_Unlock(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK)
+
+#define XBufDescriptor_IsLocked(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/* The following prototypes are provided to allow each of the functions to
+ * be implemented as a function rather than a macro, and to provide the
+ * syntax to allow users to understand how to call the macros, they are
+ * commented out to prevent linker errors
+ *
+
+u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr);
+
+u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control);
+
+u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr);
+
+u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length);
+
+u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status);
+u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr);
+
+u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr,
+				    u32 Status);
+
+u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr,
+				  u32 SourceAddress);
+
+u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr,
+				   u32 DestinationAddress);
+
+XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr,
+			       XBufDescriptor* NextPtr);
+
+u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id);
+
+u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags);
+
+void XBufDescriptor_Lock(XBufDescriptor* InstancePtr);
+void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr);
+u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr);
+
+void XBufDescriptor_Copy(XBufDescriptor* InstancePtr,
+			 XBufDescriptor* DestinationPtr);
+
+*/
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xdma_channel.c b/u-boot/board/xilinx/common/xdma_channel.c
new file mode 100644
index 0000000..f816138
--- /dev/null
+++ b/u-boot/board/xilinx/common/xdma_channel.c
@@ -0,0 +1,738 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel.c
+*
+* DESCRIPTION:
+*
+* This file contains the DMA channel component. This component supports
+* a distributed DMA design in which each device can have it's own dedicated
+* DMA channel, as opposed to a centralized DMA design. This component
+* performs processing for DMA on all devices.
+*
+* See xdma_channel.h for more information about this component.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdma_channel.h"
+#include "xbasic_types.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_Initialize
+*
+* DESCRIPTION:
+*
+* This function initializes a DMA channel.  This function must be called
+* prior to using a DMA channel.  Initialization of a channel includes setting
+* up the registers base address, and resetting the channel such that it's in a
+* known state.  Interrupts for the channel are disabled when the channel is
+* reset.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* BaseAddress contains the base address of the registers for the DMA channel.
+*
+* RETURN VALUE:
+*
+* XST_SUCCESS indicating initialization was successful.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
+{
+	/* assert to verify input arguments, don't assert base address */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	/* setup the base address of the registers for the DMA channel such
+	 * that register accesses can be done
+	 */
+	InstancePtr->RegBaseAddress = BaseAddress;
+
+	/* initialize the scatter gather list such that it indicates it has not
+	 * been created yet and the DMA channel is ready to use (initialized)
+	 */
+	InstancePtr->GetPtr = NULL;
+	InstancePtr->PutPtr = NULL;
+	InstancePtr->CommitPtr = NULL;
+	InstancePtr->LastPtr = NULL;
+
+	InstancePtr->TotalDescriptorCount = 0;
+	InstancePtr->ActiveDescriptorCount = 0;
+	InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+	/* initialize the version of the component
+	 */
+	XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
+
+	/* reset the DMA channel such that it's in a known state and ready
+	 * and indicate the initialization occured with no errors, note that
+	 * the is ready variable must be set before this call or reset will assert
+	 */
+	XDmaChannel_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_IsReady
+*
+* DESCRIPTION:
+*
+* This function determines if a DMA channel component has been successfully
+* initialized such that it's ready to use.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* TRUE if the DMA channel component is ready, FALSE otherwise.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_IsReady(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments used by the base component */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	return InstancePtr->IsReady == XCOMPONENT_IS_READY;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetVersion
+*
+* DESCRIPTION:
+*
+* This function gets the software version for the specified DMA channel
+* component.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* A pointer to the software version of the specified DMA channel.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XVersion *
+XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return a pointer to the version of the DMA channel */
+
+	return &InstancePtr->Version;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SelfTest
+*
+* DESCRIPTION:
+*
+* This function performs a self test on the specified DMA channel.  This self
+* test is destructive as the DMA channel is reset and a register default is
+* verified.
+*
+* ARGUMENTS:
+*
+* InstancePtr is a pointer to the DMA channel to be operated on.
+*
+* RETURN VALUE:
+*
+* XST_SUCCESS is returned if the self test is successful, or one of the
+* following errors.
+*
+*	XST_DMA_RESET_REGISTER_ERROR		Indicates the control register value
+*										after a reset was not correct
+*
+* NOTES:
+*
+* This test does not performs a DMA transfer to test the channel because the
+* DMA hardware will not currently allow a non-local memory transfer to non-local
+* memory (memory copy), but only allows a non-local memory to or from the device
+* memory (typically a FIFO).
+*
+******************************************************************************/
+
+#define XDC_CONTROL_REG_RESET_MASK  0x98000000UL	/* control reg reset value */
+
+XStatus
+XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
+{
+	u32 ControlReg;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* reset the DMA channel such that it's in a known state before the test
+	 * it resets to no interrupts enabled, the desired state for the test
+	 */
+	XDmaChannel_Reset(InstancePtr);
+
+	/* this should be the first test to help prevent a lock up with the polling
+	 * loop that occurs later in the test, check the reset value of the DMA
+	 * control register to make sure it's correct, return with an error if not
+	 */
+	ControlReg = XDmaChannel_GetControl(InstancePtr);
+	if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
+		return XST_DMA_RESET_REGISTER_ERROR;
+	}
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_Reset
+*
+* DESCRIPTION:
+*
+* This function resets the DMA channel. This is a destructive operation such
+* that it should not be done while a channel is being used.  If the DMA channel
+* is transferring data into other blocks, such as a FIFO, it may be necessary
+* to reset other blocks.  This function does not modify the contents of a
+* scatter gather list for a DMA channel such that the user is responsible for
+* getting buffer descriptors from the list if necessary.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_Reset(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* reset the DMA channel such that it's in a known state, the reset
+	 * register is self clearing such that it only has to be set
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
+		  XDC_RESET_MASK);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetControl
+*
+* DESCRIPTION:
+*
+* This function gets the control register contents of the DMA channel.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The control register contents of the DMA channel. One or more of the
+* following values may be contained the register.  Each of the values are
+* unique bit masks.
+*
+*	XDC_DMACR_SOURCE_INCR_MASK	Increment the source address
+*	XDC_DMACR_DEST_INCR_MASK	Increment the destination address
+*	XDC_DMACR_SOURCE_LOCAL_MASK Local source address
+*	XDC_DMACR_DEST_LOCAL_MASK	Local destination address
+*	XDC_DMACR_SG_ENABLE_MASK	Scatter gather enable
+*	XDC_DMACR_GEN_BD_INTR_MASK	Individual buffer descriptor interrupt
+*	XDC_DMACR_LAST_BD_MASK		Last buffer descriptor in a packet
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetControl(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the DMA control register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetControl
+*
+* DESCRIPTION:
+*
+* This function sets the control register of the specified DMA channel.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* Control contains the value to be written to the control register of the DMA
+* channel. One or more of the following values may be contained the register.
+* Each of the values are unique bit masks such that they may be ORed together
+* to enable multiple bits or inverted and ANDed to disable multiple bits.
+*
+*	XDC_DMACR_SOURCE_INCR_MASK	Increment the source address
+*	XDC_DMACR_DEST_INCR_MASK	Increment the destination address
+*	XDC_DMACR_SOURCE_LOCAL_MASK Local source address
+*	XDC_DMACR_DEST_LOCAL_MASK	Local destination address
+*	XDC_DMACR_SG_ENABLE_MASK	Scatter gather enable
+*	XDC_DMACR_GEN_BD_INTR_MASK	Individual buffer descriptor interrupt
+*	XDC_DMACR_LAST_BD_MASK		Last buffer descriptor in a packet
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
+{
+	/* assert to verify input arguments except the control which can't be
+	 * asserted since all values are valid
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the DMA control register to the specified value */
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetStatus
+*
+* DESCRIPTION:
+*
+* This function gets the status register contents of the DMA channel.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The status register contents of the DMA channel. One or more of the
+* following values may be contained the register. Each of the values are
+* unique bit masks.
+*
+*	XDC_DMASR_BUSY_MASK			The DMA channel is busy
+*	XDC_DMASR_BUS_ERROR_MASK	A bus error occurred
+*	XDC_DMASR_BUS_TIMEOUT_MASK	A bus timeout occurred
+*	XDC_DMASR_LAST_BD_MASK		The last buffer descriptor of a packet
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the DMA status register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetIntrStatus
+*
+* DESCRIPTION:
+*
+* This function sets the interrupt status register of the specified DMA channel.
+* Setting any bit of the interrupt status register will clear the bit to
+* indicate the interrupt processing has been completed. The definitions of each
+* bit in the register match the definition of the bits in the interrupt enable
+* register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* Status contains the value to be written to the status register of the DMA
+* channel.  One or more of the following values may be contained the register.
+* Each of the values are unique bit masks such that they may be ORed together
+* to enable multiple bits or inverted and ANDed to disable multiple bits.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
+{
+	/* assert to verify input arguments except the status which can't be
+	 * asserted since all values are valid
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the interrupt status register with the specified value such that
+	 * all bits which are set in the register are cleared effectively clearing
+	 * any active interrupts
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetIntrStatus
+*
+* DESCRIPTION:
+*
+* This function gets the interrupt status register of the specified DMA channel.
+* The interrupt status register indicates which interrupts are active
+* for the DMA channel.  If an interrupt is active, the status register must be
+* set (written) with the bit set for each interrupt which has been processed
+* in order to clear the interrupts.  The definitions of each bit in the register
+* match the definition of the bits in the interrupt enable register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The interrupt status register contents of the specified DMA channel.
+* One or more of the following values may be contained the register.
+* Each of the values are unique bit masks.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the interrupt status register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetIntrEnable
+*
+* DESCRIPTION:
+*
+* This function sets the interrupt enable register of the specified DMA
+* channel.  The interrupt enable register contains bits which enable
+* individual interrupts for the DMA channel.  The definitions of each bit
+* in the register match the definition of the bits in the interrupt status
+* register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* Enable contains the interrupt enable register contents to be written
+* in the DMA channel. One or more of the following values may be contained
+* the register. Each of the values are unique bit masks such that they may be
+* ORed together to enable multiple bits or inverted and ANDed to disable
+* multiple bits.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
+{
+	/* assert to verify input arguments except the enable which can't be
+	 * asserted since all values are valid
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the interrupt enable register to the specified value */
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetIntrEnable
+*
+* DESCRIPTION:
+*
+* This function gets the interrupt enable of the DMA channel.  The
+* interrupt enable contains flags which enable individual interrupts for the
+* DMA channel. The definitions of each bit in the register match the definition
+* of the bits in the interrupt status register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The interrupt enable of the DMA channel.  One or more of the following values
+* may be contained the register. Each of the values are unique bit masks.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the interrupt enable register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_Transfer
+*
+* DESCRIPTION:
+*
+* This function starts the DMA channel transferring data from a memory source
+* to a memory destination. This function only starts the operation and returns
+* before the operation may be complete.  If the interrupt is enabled, an
+* interrupt will be generated when the operation is complete, otherwise it is
+* necessary to poll the channel status to determine when it's complete.  It is
+* the responsibility of the caller to determine when the operation is complete
+* by handling the generated interrupt or polling the status.  It is also the
+* responsibility of the caller to ensure that the DMA channel is not busy with
+* another transfer before calling this function.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* SourcePtr contains a pointer to the source memory where the data is to
+* be tranferred from and must be 32 bit aligned.
+*
+* DestinationPtr contains a pointer to the destination memory where the data
+* is to be transferred and must be 32 bit aligned.
+*
+* ByteCount contains the number of bytes to transfer during the DMA operation.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* The DMA h/w will not currently allow a non-local memory transfer to non-local
+* memory (memory copy), but only allows a non-local memory to or from the device
+* memory (typically a FIFO).
+*
+* It is the responsibility of the caller to ensure that the cache is
+* flushed and invalidated both before and after the DMA operation completes
+* if the memory pointed to is cached. The caller must also ensure that the
+* pointers contain a physical address rather than a virtual address
+* if address translation is being used.
+*
+******************************************************************************/
+void
+XDmaChannel_Transfer(XDmaChannel * InstancePtr,
+		     u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
+{
+	/* assert to verify input arguments and the alignment of any arguments
+	 * which have expected alignments
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(SourcePtr != NULL);
+	XASSERT_VOID(((u32) SourcePtr & 3) == 0);
+	XASSERT_VOID(DestinationPtr != NULL);
+	XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
+	XASSERT_VOID(ByteCount != 0);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* setup the source and destination address registers for the transfer */
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
+		  (u32) SourcePtr);
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
+		  (u32) DestinationPtr);
+
+	/* start the DMA transfer to copy from the source buffer to the
+	 * destination buffer by writing the length to the length register
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
+}
diff --git a/u-boot/board/xilinx/common/xdma_channel.h b/u-boot/board/xilinx/common/xdma_channel.h
new file mode 100644
index 0000000..4685982
--- /dev/null
+++ b/u-boot/board/xilinx/common/xdma_channel.h
@@ -0,0 +1,291 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel.h
+*
+* DESCRIPTION:
+*
+* This file contains the DMA channel component implementation. This component
+* supports a distributed DMA design in which each device can have it's own
+* dedicated DMA channel, as opposed to a centralized DMA design.
+* A device which uses DMA typically contains two DMA channels, one for
+* sending data and the other for receiving data.
+*
+* This component is designed to be used as a basic building block for
+* designing a device driver. It provides registers accesses such that all
+* DMA processing can be maintained easier, but the device driver designer
+* must still understand all the details of the DMA channel.
+*
+* The DMA channel allows a CPU to minimize the CPU interaction required to move
+* data between a memory and a device.  The CPU requests the DMA channel to
+* perform a DMA operation and typically continues performing other processing
+* until the DMA operation completes.  DMA could be considered a primitive form
+* of multiprocessing such that caching and address translation can be an issue.
+*
+* Scatter Gather Operations
+*
+* The DMA channel may support scatter gather operations. A scatter gather
+* operation automates the DMA channel such that multiple buffers can be
+* sent or received with minimal software interaction with the hardware.  Buffer
+* descriptors, contained in the XBufDescriptor component, are used by the
+* scatter gather operations of the DMA channel to describe the buffers to be
+* processed.
+*
+* Scatter Gather List Operations
+*
+* A scatter gather list may be supported by each DMA channel.  The scatter
+* gather list allows buffer descriptors to be put into the list by a device
+* driver which requires scatter gather.  The hardware processes the buffer
+* descriptors which are contained in the list and modifies the buffer
+* descriptors to reflect the status of the DMA operations.  The device driver
+* is notified by interrupt that specific DMA events occur including scatter
+* gather events.  The device driver removes the completed buffer descriptors
+* from the scatter gather list to evaluate the status of each DMA operation.
+*
+* The scatter gather list is created and buffer descriptors are inserted into
+* the list.  Buffer descriptors are never removed from the list after it's
+* creation such that a put operation copies from a temporary buffer descriptor
+* to a buffer descriptor in the list.  Get operations don't copy from the list
+* to a temporary, but return a pointer to the buffer descriptor in the list.
+* A buffer descriptor in the list may be locked to prevent it from being
+* overwritten by a put operation.  This allows the device driver to get a
+* descriptor from a scatter gather list and prevent it from being overwritten
+* until the buffer associated with the buffer descriptor has been processed.
+*
+* Typical Scatter Gather Processing
+*
+* The following steps illustrate the typical processing to use the
+* scatter gather features of a DMA channel.
+*
+* 1. Create a scatter gather list for the DMA channel which puts empty buffer
+*    descriptors into the list.
+* 2. Create buffer descriptors which describe the buffers to be filled with
+*	 receive data or the buffers which contain data to be sent.
+* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
+*    gather operations are requested.
+* 4. Commit the buffer descriptors in the list such that they are ready to be
+*    used by the DMA channel hardware.
+* 5. Start the scatter gather operations of the DMA channel.
+* 6. Process any interrupts which occur as a result of the scatter gather
+*    operations or poll the DMA channel to determine the status.
+*
+* Interrupts
+*
+* Each DMA channel has the ability to generate an interrupt.  This component
+* does not perform processing for the interrupt as this processing is typically
+* tightly coupled with the device which is using the DMA channel.  It is the
+* responsibility of the caller of DMA functions to manage the interrupt
+* including connecting to the interrupt and enabling/disabling the interrupt.
+*
+* Critical Sections
+*
+* It is the responsibility of the device driver designer to use critical
+* sections as necessary when calling functions of the DMA channel.  This
+* component does not use critical sections and it does access registers using
+* read-modify-write operations.  Calls to DMA functions from a main thread
+* and from an interrupt context could produce unpredictable behavior such that
+* the caller must provide the appropriate critical sections.
+*
+* Address Translation
+*
+* All addresses of data structures which are passed to DMA functions must
+* be physical (real) addresses as opposed to logical (virtual) addresses.
+*
+* Caching
+*
+* The memory which is passed to the function which creates the scatter gather
+* list must not be cached such that buffer descriptors are non-cached.  This
+* is necessary because the buffer descriptors are kept in a ring buffer and
+* not directly accessible to the caller of DMA functions.
+*
+* The caller of DMA functions is responsible for ensuring that any data
+* buffers which are passed to the DMA channel are cache-line aligned if
+* necessary.
+*
+* The caller of DMA functions is responsible for ensuring that any data
+* buffers which are passed to the DMA channel have been flushed from the cache.
+*
+* The caller of DMA functions is responsible for ensuring that the cache is
+* invalidated prior to using any data buffers which are the result of a DMA
+* operation.
+*
+* Memory Alignment
+*
+* The addresses of data buffers which are passed to DMA functions must be
+* 32 bit word aligned since the DMA hardware performs 32 bit word transfers.
+*
+* Mutual Exclusion
+*
+* The functions of the DMA channel are not thread safe such that the caller
+* of all DMA functions is responsible for ensuring mutual exclusion for a
+* DMA channel.  Mutual exclusion across multiple DMA channels is not
+* necessary.
+*
+* NOTES:
+*
+* Many of the provided functions which are register accessors don't provide
+* a lot of error detection. The caller is expected to understand the impact
+* of a function call based upon the current state of the DMA channel.  This
+* is done to minimize the overhead in this component.
+*
+******************************************************************************/
+
+#ifndef XDMA_CHANNEL_H		/* prevent circular inclusions */
+#define XDMA_CHANNEL_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdma_channel_i.h"	/* constants shared with buffer descriptor */
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xversion.h"
+#include "xbuf_descriptor.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants provide access to the bit fields of the DMA control
+ * register (DMACR)
+ */
+#define XDC_DMACR_SOURCE_INCR_MASK	0x80000000UL	/* increment source address */
+#define XDC_DMACR_DEST_INCR_MASK	0x40000000UL	/* increment dest address */
+#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL	/* local source address */
+#define XDC_DMACR_DEST_LOCAL_MASK	0x10000000UL	/* local dest address */
+#define XDC_DMACR_SG_DISABLE_MASK	0x08000000UL	/* scatter gather disable */
+#define XDC_DMACR_GEN_BD_INTR_MASK	0x04000000UL	/* descriptor interrupt */
+#define XDC_DMACR_LAST_BD_MASK		XDC_CONTROL_LAST_BD_MASK	/* last buffer */
+															 /*     descriptor  */
+
+/* the following constants provide access to the bit fields of the DMA status
+ * register (DMASR)
+ */
+#define XDC_DMASR_BUSY_MASK			0x80000000UL	/* channel is busy */
+#define XDC_DMASR_BUS_ERROR_MASK	0x40000000UL	/* bus error occurred */
+#define XDC_DMASR_BUS_TIMEOUT_MASK	0x20000000UL	/* bus timeout occurred */
+#define XDC_DMASR_LAST_BD_MASK		XDC_STATUS_LAST_BD_MASK	/* last buffer */
+														    /* descriptor  */
+#define XDC_DMASR_SG_BUSY_MASK		0x08000000UL	/* scatter gather is busy */
+
+/* the following constants provide access to the bit fields of the interrupt
+ * status register (ISR) and the interrupt enable register (IER), bit masks
+ * match for both registers such that they are named IXR
+ */
+#define XDC_IXR_DMA_DONE_MASK		0x1UL	/* dma operation done */
+#define XDC_IXR_DMA_ERROR_MASK	    0x2UL	/* dma operation error */
+#define XDC_IXR_PKT_DONE_MASK	    0x4UL	/* packet done */
+#define XDC_IXR_PKT_THRESHOLD_MASK	0x8UL	/* packet count threshold */
+#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL	/* packet wait bound reached */
+#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL	/* scatter gather disable
+						   acknowledge occurred */
+#define XDC_IXR_SG_END_MASK			0x40UL	/* last buffer descriptor
+							   disabled scatter gather */
+#define XDC_IXR_BD_MASK				0x80UL	/* buffer descriptor done */
+
+/**************************** Type Definitions *******************************/
+
+/*
+ * the following structure contains data which is on a per instance basis
+ * for the XDmaChannel component
+ */
+typedef struct XDmaChannelTag {
+	XVersion Version;	/* version of the driver */
+	u32 RegBaseAddress;	/* base address of registers */
+	u32 IsReady;		/* device is initialized and ready */
+
+	XBufDescriptor *PutPtr;	/* keep track of where to put into list */
+	XBufDescriptor *GetPtr;	/* keep track of where to get from list */
+	XBufDescriptor *CommitPtr;	/* keep track of where to commit in list */
+	XBufDescriptor *LastPtr;	/* keep track of the last put in the list */
+	u32 TotalDescriptorCount;	/* total # of descriptors in the list */
+	u32 ActiveDescriptorCount;	/* # of descriptors pointing to buffers
+					   * in the buffer descriptor list */
+} XDmaChannel;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress);
+u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr);
+XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr);
+void XDmaChannel_Reset(XDmaChannel * InstancePtr);
+
+/* Control functions */
+
+u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr);
+void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control);
+
+/* Status functions */
+
+u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr);
+void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status);
+u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr);
+void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable);
+u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr);
+
+/* DMA without scatter gather functions */
+
+void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
+			  u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount);
+
+/* Scatter gather functions */
+
+XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr,
+			   XBufDescriptor ** BufDescriptorPtr);
+XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
+				 u32 * MemoryPtr, u32 ByteCount);
+u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr);
+
+XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
+				  XBufDescriptor * BufDescriptorPtr);
+XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
+				  XBufDescriptor ** BufDescriptorPtr);
+
+/* Packet functions for interrupt collescing */
+
+u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr);
+void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold);
+u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr);
+void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound);
+u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xdma_channel_i.h b/u-boot/board/xilinx/common/xdma_channel_i.h
new file mode 100644
index 0000000..e9f343b
--- /dev/null
+++ b/u-boot/board/xilinx/common/xdma_channel_i.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel_i.h
+*
+* DESCRIPTION:
+*
+* This file contains data which is shared internal data for the DMA channel
+* component. It is also shared with the buffer descriptor component which is
+* very tightly coupled with the DMA channel component.
+*
+* NOTES:
+*
+* The last buffer descriptor constants must be located here to prevent a
+* circular dependency between the DMA channel component and the buffer
+* descriptor component.
+*
+******************************************************************************/
+
+#ifndef XDMA_CHANNEL_I_H	/* prevent circular inclusions */
+#define XDMA_CHANNEL_I_H	/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XDC_DMA_CHANNEL_V1_00_A		"1.00a"
+
+/* the following constant provides access to the bit fields of the DMA control
+ * register (DMACR) which must be shared between the DMA channel component
+ * and the buffer descriptor component
+ */
+#define XDC_CONTROL_LAST_BD_MASK	0x02000000UL	/* last buffer descriptor */
+
+/* the following constant provides access to the bit fields of the DMA status
+ * register (DMASR) which must be shared between the DMA channel component
+ * and the buffer descriptor component
+ */
+#define XDC_STATUS_LAST_BD_MASK		0x10000000UL	/* last buffer descriptor */
+
+/* the following constants provide access to each of the registers of a DMA
+ * channel
+ */
+#define XDC_RST_REG_OFFSET	0	/* reset register */
+#define XDC_MI_REG_OFFSET	0	/* module information register */
+#define XDC_DMAC_REG_OFFSET	4	/* DMA control register */
+#define XDC_SA_REG_OFFSET	8	/* source address register */
+#define XDC_DA_REG_OFFSET	12	/* destination address register */
+#define XDC_LEN_REG_OFFSET	16	/* length register */
+#define XDC_DMAS_REG_OFFSET	20	/* DMA status register */
+#define XDC_BDA_REG_OFFSET	24	/* buffer descriptor address register */
+#define XDC_SWCR_REG_OFFSET 28	/* software control register */
+#define XDC_UPC_REG_OFFSET	32	/* unserviced packet count register */
+#define	XDC_PCT_REG_OFFSET	36	/* packet count threshold register */
+#define XDC_PWB_REG_OFFSET	40	/* packet wait bound register */
+#define XDC_IS_REG_OFFSET	44	/* interrupt status register */
+#define XDC_IE_REG_OFFSET	48	/* interrupt enable register */
+
+/* the following constant is written to the reset register to reset the
+ * DMA channel
+ */
+#define XDC_RESET_MASK				0x0000000AUL
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xdma_channel_sg.c b/u-boot/board/xilinx/common/xdma_channel_sg.c
new file mode 100644
index 0000000..a8e9462
--- /dev/null
+++ b/u-boot/board/xilinx/common/xdma_channel_sg.c
@@ -0,0 +1,1317 @@
+/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel_sg.c
+*
+* DESCRIPTION:
+*
+* This file contains the implementation of the XDmaChannel component which is
+* related to scatter gather operations.
+*
+* Scatter Gather Operations
+*
+* The DMA channel may support scatter gather operations. A scatter gather
+* operation automates the DMA channel such that multiple buffers can be
+* sent or received with minimal software interaction with the hardware.	 Buffer
+* descriptors, contained in the XBufDescriptor component, are used by the
+* scatter gather operations of the DMA channel to describe the buffers to be
+* processed.
+*
+* Scatter Gather List Operations
+*
+* A scatter gather list may be supported by each DMA channel.  The scatter
+* gather list allows buffer descriptors to be put into the list by a device
+* driver which requires scatter gather.	 The hardware processes the buffer
+* descriptors which are contained in the list and modifies the buffer
+* descriptors to reflect the status of the DMA operations.  The device driver
+* is notified by interrupt that specific DMA events occur including scatter
+* gather events.  The device driver removes the completed buffer descriptors
+* from the scatter gather list to evaluate the status of each DMA operation.
+*
+* The scatter gather list is created and buffer descriptors are inserted into
+* the list.  Buffer descriptors are never removed from the list after it's
+* creation such that a put operation copies from a temporary buffer descriptor
+* to a buffer descriptor in the list.  Get operations don't copy from the list
+* to a temporary, but return a pointer to the buffer descriptor in the list.
+* A buffer descriptor in the list may be locked to prevent it from being
+* overwritten by a put operation.  This allows the device driver to get a
+* descriptor from a scatter gather list and prevent it from being overwritten
+* until the buffer associated with the buffer descriptor has been processed.
+*
+* The get and put functions only operate on the list and are asynchronous from
+* the hardware which may be using the list of descriptors.  This is important
+* because there are no checks in the get and put functions to ensure that the
+* hardware has processed the descriptors.  This must be handled by the driver
+* using the DMA scatter gather channel through the use of the other functions.
+* When a scatter gather operation is started, the start function does ensure
+* that the descriptor to start has not already been processed by the hardware
+* and is not the first of a series of descriptors that have not been committed
+* yet.
+*
+* Descriptors are put into the list but not marked as ready to use by the
+* hardware until a commit operation is done.  This allows multiple descriptors
+* which may contain a single packet of information for a protocol to be
+* guaranteed not to cause any underflow conditions during transmission. The
+* hardware design only allows descriptors to cause it to stop after a descriptor
+* has been processed rather than before it is processed.  A series of
+* descriptors are put into the list followed by a commit operation, or each
+* descriptor may be commited.  A commit operation is performed by changing a
+* single descriptor, the first of the series of puts, to indicate that the
+* hardware may now use all descriptors after it.  The last descriptor in the
+* list is always set to cause the hardware to stop after it is processed.
+*
+* Typical Scatter Gather Processing
+*
+* The following steps illustrate the typical processing to use the
+* scatter gather features of a DMA channel.
+*
+* 1. Create a scatter gather list for the DMA channel which puts empty buffer
+*    descriptors into the list.
+* 2. Create buffer descriptors which describe the buffers to be filled with
+*    receive data or the buffers which contain data to be sent.
+* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
+*    gather operations are requested.
+* 4. Commit the buffer descriptors in the list such that they are ready to be
+*    used by the DMA channel hardware.
+* 5. Start the scatter gather operations of the DMA channel.
+* 6. Process any interrupts which occur as a result of the scatter gather
+*    operations or poll the DMA channel to determine the status.  This may
+*    be accomplished by getting the packet count for the channel and then
+*    getting the appropriate number of descriptors from the list for that
+*    number of packets.
+*
+* Minimizing Interrupts
+*
+* The Scatter Gather operating mode is designed to reduce the amount of CPU
+* throughput necessary to manage the hardware for devices. A key to the CPU
+* throughput is the number and rate of interrupts that the CPU must service.
+* Devices with higher data rates can cause larger numbers of interrupts and
+* higher frequency interrupts. Ideally the number of interrupts can be reduced
+* by only generating an interrupt when a specific amount of data has been
+* received from the interface. This design suffers from a lack of interrupts
+* when the amount of data received is less than the specified amount of data
+* to generate an interrupt. In order to help minimize the number of interrupts
+* which the CPU must service, an algorithm referred to as "interrupt coalescing"
+* is utilized.
+*
+* Interrupt Coalescing
+*
+* The principle of interrupt coalescing is to wait before generating an
+* interrupt until a certain number of packets have been received or sent. An
+* interrupt is also generated if a smaller number of packets have been received
+* followed by a certain period of time with no packet reception. This is a
+* trade-off of latency for bandwidth and is accomplished using several
+* mechanisms of the hardware including a counter for packets received or
+* transmitted and a packet timer. These two hardware mechanisms work in
+* combination to allow a reduction in the number of interrupts processed by the
+* CPU for packet reception.
+*
+* Unserviced Packet Count
+*
+* The purpose of the packet counter is to count the number of packets received
+* or transmitted and provide an interrupt when a specific number of packets
+* have been processed by the hardware. An interrupt is generated whenever the
+* counter is greater than or equal to the Packet Count Threshold. This counter
+* contains an accurate count of the number of packets that the hardware has
+* processed, either received or transmitted, and the software has not serviced.
+*
+* The packet counter allows the number of interrupts to be reduced by waiting
+* to generate an interrupt until enough packets are received. For packet
+* reception, packet counts of less than the number to generate an interrupt
+* would not be serviced without the addition of a packet timer. This counter is
+* continuously updated by the hardware, not latched to the value at the time
+* the interrupt occurred.
+*
+* The packet counter can be used within the interrupt service routine for the
+* device to reduce the number of interrupts. The interrupt service routine
+* loops while performing processing for each packet which has been received or
+* transmitted and decrements the counter by a specified value. At the same time,
+* the hardware is possibly continuing to receive or transmit more packets such
+* that the software may choose, based upon the value in the packet counter, to
+* remain in the interrupt service routine rather than exiting and immediately
+* returning. This feature should be used with caution as reducing the number of
+* interrupts is beneficial, but unbounded interrupt processing is not desirable.
+*
+* Since the hardware may be incrementing the packet counter simultaneously
+* with the software decrementing the counter, there is a need for atomic
+* operations. The hardware ensures that the operation is atomic such that
+* simultaneous accesses are properly handled.
+*
+* Packet Wait Bound
+*
+* The purpose of the packet wait bound is to augment the unserviced packet
+* count. Whenever there is no pending interrupt for the channel and the
+* unserviced packet count is non-zero, a timer starts counting timeout at the
+* value contained the the packet wait bound register.  If the timeout is
+* reached, an interrupt is generated such that the software may service the
+* data which was buffered.
+*
+* NOTES:
+*
+* Special Test Conditions:
+*
+* The scatter gather list processing must be thoroughly tested if changes are
+* made.	 Testing should include putting and committing single descriptors and
+* putting multiple descriptors followed by a single commit.  There are some
+* conditions in the code which handle the exception conditions.
+*
+* The Put Pointer points to the next location in the descriptor list to copy
+* in a new descriptor. The Get Pointer points to the next location in the
+* list to get a descriptor from.  The Get Pointer only allows software to
+* have a traverse the list after the hardware has finished processing some
+* number of descriptors.  The Commit Pointer points to the descriptor in the
+* list which is to be committed.  It is also used to determine that no
+* descriptor is waiting to be commited (NULL).	The Last Pointer points to
+* the last descriptor that was put into the list.  It typically points
+* to the previous descriptor to the one pointed to by the Put Pointer.
+* Comparisons are done between these pointers to determine when the following
+* special conditions exist.
+
+* Single Put And Commit
+*
+* The buffer descriptor is ready to be used by the hardware so it is important
+* for the descriptor to not appear to be waiting to be committed.  The commit
+* pointer is reset when a commit is done indicating there are no descriptors
+* waiting to be committed.  In all cases but this one, the descriptor is
+* changed to cause the hardware to go to the next descriptor after processing
+* this one.  But in this case, this is the last descriptor in the list such
+* that it must not be changed.
+*
+* 3 Or More Puts And Commit
+*
+* A series of 3 or more puts followed by a single commit is different in that
+* only the 1st descriptor put into the list is changed when the commit is done.
+* This requires each put starting on the 3rd to change the previous descriptor
+* so that it allows the hardware to continue to the next descriptor in the list.
+*
+* The 1st Put Following A Commit
+*
+* The commit caused the commit pointer to be NULL indicating that there are no
+* descriptors waiting to be committed.	It is necessary for the next put to set
+* the commit pointer so that a commit must follow the put for the hardware to
+* use the descriptor.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- ------------------------------------------------------
+* 1.00a rpm  02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
+*		      from SetPktThreshold.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdma_channel.h"
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xbuf_descriptor.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL	/* scatter gather enable */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/* the following macro copies selected fields of a buffer descriptor to another
+ * buffer descriptor, this was provided by the buffer descriptor component but
+ * was moved here since it is only used internally to this component and since
+ * it does not copy all fields
+ */
+#define CopyBufferDescriptor(InstancePtr, DestinationPtr)	   \
+{								   \
+    *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_CONTROL_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_SOURCE_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_LENGTH_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_STATUS_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) =      \
+	*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET);      \
+    *((u32 *)DestinationPtr + XBD_ID_OFFSET) =		       \
+	*((u32 *)InstancePtr + XBD_ID_OFFSET);		       \
+    *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_FLAGS_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) =      \
+	*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET);      \
+}
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SgStart
+*
+* DESCRIPTION:
+*
+* This function starts a scatter gather operation for a scatter gather
+* DMA channel.	The first buffer descriptor in the buffer descriptor list
+* will be started with the scatter gather operation.  A scatter gather list
+* should have previously been created for the DMA channel and buffer
+* descriptors put into the scatter gather list such that there are scatter
+* operations ready to be performed.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* A status containing XST_SUCCESS if scatter gather was started successfully
+* for the DMA channel.
+*
+* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
+* been created.
+*
+* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started
+* because the scatter gather list of the DMA channel does not contain any
+* buffer descriptors that are ready to be processed by the hardware.
+*
+* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started
+* because the scatter gather was not stopped, but was already started.
+*
+* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of
+* scatter gather list which was to be started is not committed to the list.
+* This status is more likely if this function is being called from an ISR
+* and non-ISR processing is putting descriptors into the list.
+*
+* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the
+* scatter gather list which was to be started had already been used by the
+* hardware for a DMA transfer that has been completed.
+*
+* NOTES:
+*
+* It is the responsibility of the caller to get all the buffer descriptors
+* after performing a stop operation and before performing a start operation.
+* If buffer descriptors are not retrieved between stop and start operations,
+* buffer descriptors may be processed by the hardware more than once.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_SgStart(XDmaChannel * InstancePtr)
+{
+	u32 Register;
+	XBufDescriptor *LastDescriptorPtr;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if a scatter gather list has not been created yet, return a status */
+
+	if (InstancePtr->TotalDescriptorCount == 0) {
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* if the scatter gather list exists but is empty then return a status */
+
+	if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
+		return XST_DMA_SG_LIST_EMPTY;
+	}
+
+	/* if scatter gather is busy for the DMA channel, return a status because
+	 * restarting it could lose data
+	 */
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
+	if (Register & XDC_DMASR_SG_BUSY_MASK) {
+		return XST_DMA_SG_IS_STARTED;
+	}
+
+	/* get the address of the last buffer descriptor which the DMA hardware
+	 * finished processing
+	 */
+	LastDescriptorPtr =
+	    (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
+					XDC_BDA_REG_OFFSET);
+
+	/* setup the first buffer descriptor that will be sent when the scatter
+	 * gather channel is enabled, this is only necessary one time since
+	 * the BDA register of the channel maintains the last buffer descriptor
+	 * processed
+	 */
+	if (LastDescriptorPtr == NULL) {
+		XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET,
+			  (u32) InstancePtr->GetPtr);
+	} else {
+		XBufDescriptor *NextDescriptorPtr;
+
+		/* get the next descriptor to be started, if the status indicates it
+		 * hasn't already been used by the h/w, then it's OK to start it,
+		 * s/w sets the status of each descriptor to busy and then h/w clears
+		 * the busy when it is complete
+		 */
+		NextDescriptorPtr =
+		    XBufDescriptor_GetNextPtr(LastDescriptorPtr);
+
+		if ((XBufDescriptor_GetStatus(NextDescriptorPtr) &
+		     XDC_DMASR_BUSY_MASK) == 0) {
+			return XST_DMA_SG_NO_DATA;
+		}
+		/* don't start the DMA SG channel if the descriptor to be processed
+		 * by h/w is to be committed by the s/w, this function can be called
+		 * such that it interrupts a thread that was putting into the list
+		 */
+		if (NextDescriptorPtr == InstancePtr->CommitPtr) {
+			return XST_DMA_SG_BD_NOT_COMMITTED;
+		}
+	}
+
+	/* start the scatter gather operation by clearing the stop bit in the
+	 * control register and setting the enable bit in the s/w control register,
+	 * both of these are necessary to cause it to start, right now the order of
+	 * these statements is important, the software control register should be
+	 * set 1st.  The other order can cause the CPU to have a loss of sync
+	 * because it cannot read/write the register while the DMA operation is
+	 * running
+	 */
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
+		  Register | XDC_SWCR_SG_ENABLE_MASK);
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET,
+		  Register & ~XDC_DMACR_SG_DISABLE_MASK);
+
+	/* indicate the DMA channel scatter gather operation was started
+	 * successfully
+	 */
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SgStop
+*
+* DESCRIPTION:
+*
+* This function stops a scatter gather operation for a scatter gather
+* DMA channel. This function starts the process of stopping a scatter
+* gather operation that is in progress and waits for the stop to be completed.
+* Since it waits for the operation to stopped before returning, this function
+* could take an amount of time relative to the size of the DMA scatter gather
+* operation which is in progress.  The scatter gather list of the DMA channel
+* is not modified by this function such that starting the scatter gather
+* channel after stopping it will cause it to resume.  This operation is
+* considered to be a graceful stop in that the scatter gather operation
+* completes the current buffer descriptor before stopping.
+*
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is stopped and the caller is responsible for handling the
+* interrupt.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* BufDescriptorPtr is also a return value which contains a pointer to the
+* buffer descriptor which the scatter gather operation completed when it
+* was stopped.
+*
+* RETURN VALUE:
+*
+* A status containing XST_SUCCESS if scatter gather was stopped successfully
+* for the DMA channel.
+*
+* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped
+* because the scatter gather is not started, but was already stopped.
+*
+* BufDescriptorPtr contains a pointer to the buffer descriptor which was
+* completed when the operation was stopped.
+*
+* NOTES:
+*
+* This function implements a loop which polls the hardware for an infinite
+* amount of time. If the hardware is not operating correctly, this function
+* may never return.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_SgStop(XDmaChannel * InstancePtr,
+		   XBufDescriptor ** BufDescriptorPtr)
+{
+	u32 Register;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufDescriptorPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the contents of the software control register, if scatter gather is not
+	 * enabled (started), then return a status because the disable acknowledge
+	 * would not be generated
+	 */
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
+
+	if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) {
+		return XST_DMA_SG_IS_STOPPED;
+	}
+
+	/* Ensure the interrupt status for the scatter gather is cleared such
+	 * that this function will wait til the disable has occurred, writing
+	 * a 1 to only that bit in the register will clear only it
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
+		  XDC_IXR_SG_DISABLE_ACK_MASK);
+
+	/* disable scatter gather by writing to the software control register
+	 * without modifying any other bits of the register
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
+		  Register & ~XDC_SWCR_SG_ENABLE_MASK);
+
+	/* scatter gather does not disable immediately, but after the current
+	 * buffer descriptor is complete, so wait for the DMA channel to indicate
+	 * the disable is complete
+	 */
+	do {
+		Register =
+		    XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
+	} while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0);
+
+	/* Ensure the interrupt status for the scatter gather disable is cleared,
+	 * writing a 1 to only that bit in the register will clear only it
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
+		  XDC_IXR_SG_DISABLE_ACK_MASK);
+
+	/* set the specified buffer descriptor pointer to point to the buffer
+	 * descriptor that the scatter gather DMA channel was processing
+	 */
+	*BufDescriptorPtr =
+	    (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
+					XDC_BDA_REG_OFFSET);
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_CreateSgList
+*
+* DESCRIPTION:
+*
+* This function creates a scatter gather list in the DMA channel.  A scatter
+* gather list consists of a list of buffer descriptors that are available to
+* be used for scatter gather operations.  Buffer descriptors are put into the
+* list to request a scatter gather operation to be performed.
+*
+* A number of buffer descriptors are created from the specified memory and put
+* into a buffer descriptor list as empty buffer descriptors. This function must
+* be called before non-empty buffer descriptors may be put into the DMA channel
+* to request scatter gather operations.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* MemoryPtr contains a pointer to the memory which is to be used for buffer
+* descriptors and must not be cached.
+*
+* ByteCount contains the number of bytes for the specified memory to be used
+* for buffer descriptors.
+*
+* RETURN VALUE:
+*
+* A status contains XST_SUCCESS if the scatter gather list was successfully
+* created.
+*
+* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list
+* was not created because the list has already been created.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
+			 u32 * MemoryPtr, u32 ByteCount)
+{
+	XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr;
+	XBufDescriptor *PreviousDescriptorPtr = NULL;
+	XBufDescriptor *StartOfListPtr = BufferDescriptorPtr;
+	u32 UsedByteCount;
+
+	/* assert to verify valid input arguments, alignment for those
+	 * arguments that have alignment restrictions, and at least enough
+	 * memory for one buffer descriptor
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(MemoryPtr != NULL);
+	XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor));
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the scatter gather list has already been created, then return
+	 * with a status
+	 */
+	if (InstancePtr->TotalDescriptorCount != 0) {
+		return XST_DMA_SG_LIST_EXISTS;
+	}
+
+	/* loop thru the specified memory block and create as many buffer
+	 * descriptors as possible putting each into the list which is
+	 * implemented as a ring buffer, make sure not to use any memory which
+	 * is not large enough for a complete buffer descriptor
+	 */
+	UsedByteCount = 0;
+	while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) {
+		/* setup a pointer to the next buffer descriptor in the memory and
+		 * update # of used bytes to know when all of memory is used
+		 */
+		BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr +
+							  UsedByteCount);
+
+		/* initialize the new buffer descriptor such that it doesn't contain
+		 * garbage which could be used by the DMA hardware
+		 */
+		XBufDescriptor_Initialize(BufferDescriptorPtr);
+
+		/* if this is not the first buffer descriptor to be created,
+		 * then link it to the last created buffer descriptor
+		 */
+		if (PreviousDescriptorPtr != NULL) {
+			XBufDescriptor_SetNextPtr(PreviousDescriptorPtr,
+						  BufferDescriptorPtr);
+		}
+
+		/* always keep a pointer to the last created buffer descriptor such
+		 * that they can be linked together in the ring buffer
+		 */
+		PreviousDescriptorPtr = BufferDescriptorPtr;
+
+		/* keep a count of the number of descriptors in the list to allow
+		 * error processing to be performed
+		 */
+		InstancePtr->TotalDescriptorCount++;
+
+		UsedByteCount += sizeof (XBufDescriptor);
+	}
+
+	/* connect the last buffer descriptor created and inserted in the list
+	 * to the first such that a ring buffer is created
+	 */
+	XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr);
+
+	/* initialize the ring buffer to indicate that there are no
+	 * buffer descriptors in the list which point to valid data buffers
+	 */
+	InstancePtr->PutPtr = BufferDescriptorPtr;
+	InstancePtr->GetPtr = BufferDescriptorPtr;
+	InstancePtr->CommitPtr = NULL;
+	InstancePtr->LastPtr = BufferDescriptorPtr;
+	InstancePtr->ActiveDescriptorCount = 0;
+
+	/* indicate the scatter gather list was successfully created */
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_IsSgListEmpty
+*
+* DESCRIPTION:
+*
+* This function determines if the scatter gather list of a DMA channel is
+* empty with regard to buffer descriptors which are pointing to buffers to be
+* used for scatter gather operations.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* A value of TRUE if the scatter gather list is empty, otherwise a value of
+* FALSE.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr)
+{
+	/* assert to verify valid input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the number of descriptors which are being used in the list is zero
+	 * then the list is empty
+	 */
+	return (InstancePtr->ActiveDescriptorCount == 0);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_PutDescriptor
+*
+* DESCRIPTION:
+*
+* This function puts a buffer descriptor into the DMA channel scatter
+* gather list. A DMA channel maintains a list of buffer descriptors which are
+* to be processed.  This function puts the specified buffer descriptor
+* at the next location in the list.  Note that since the list is already intact,
+* the information in the parameter is copied into the list (rather than modify
+* list pointers on the fly).
+*
+* After buffer descriptors are put into the list, they must also be committed
+* by calling another function.	This allows multiple buffer descriptors which
+* span a single packet to be put into the list while preventing the hardware
+* from starting the first buffer descriptor of the packet.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into
+* the next available location of the scatter gather list.
+*
+* RETURN VALUE:
+*
+* A status which indicates XST_SUCCESS if the buffer descriptor was
+* successfully put into the scatter gather list.
+*
+* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
+* been created.
+*
+* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not
+* put into the list because the list was full.
+*
+* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not
+* put into the list because the buffer descriptor in the list which is to
+* be overwritten was locked.  A locked buffer descriptor indicates the higher
+* layered software is still using the buffer descriptor.
+*
+* NOTES:
+*
+* It is necessary to create a scatter gather list for a DMA channel before
+* putting buffer descriptors into it.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
+			  XBufDescriptor * BufferDescriptorPtr)
+{
+	u32 Control;
+
+	/* assert to verify valid input arguments and alignment for those
+	 * arguments that have alignment restrictions
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufferDescriptorPtr != NULL);
+	XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if a scatter gather list has not been created yet, return a status */
+
+	if (InstancePtr->TotalDescriptorCount == 0) {
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* if the list is full because all descriptors are pointing to valid
+	 * buffers, then indicate an error, this code assumes no list or an
+	 * empty list is detected above
+	 */
+	if (InstancePtr->ActiveDescriptorCount ==
+	    InstancePtr->TotalDescriptorCount) {
+		return XST_DMA_SG_LIST_FULL;
+	}
+
+	/* if the buffer descriptor in the list which is to be overwritten is
+	 * locked, then don't overwrite it and return a status
+	 */
+	if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) {
+		return XST_DMA_SG_BD_LOCKED;
+	}
+
+	/* set the scatter gather stop bit in the control word of the descriptor
+	 * to cause the h/w to stop after it processes this descriptor since it
+	 * will be the last in the list
+	 */
+	Control = XBufDescriptor_GetControl(BufferDescriptorPtr);
+	XBufDescriptor_SetControl(BufferDescriptorPtr,
+				  Control | XDC_DMACR_SG_DISABLE_MASK);
+
+	/* set both statuses in the descriptor so we tell if they are updated with
+	 * the status of the transfer, the hardware should change the busy in the
+	 * DMA status to be false when it completes
+	 */
+	XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK);
+	XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0);
+
+	/* copy the descriptor into the next position in the list so it's ready to
+	 * be used by the h/w, this assumes the descriptor in the list prior to this
+	 * one still has the stop bit in the control word set such that the h/w
+	 * use this one yet
+	 */
+	CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr);
+
+	/* only the last in the list and the one to be committed have scatter gather
+	 * disabled in the control word, a commit requires only one descriptor
+	 * to be changed, when # of descriptors to commit > 2 all others except the
+	 * 1st and last have scatter gather enabled
+	 */
+	if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) &&
+	    (InstancePtr->CommitPtr != NULL)) {
+		Control = XBufDescriptor_GetControl(InstancePtr->LastPtr);
+		XBufDescriptor_SetControl(InstancePtr->LastPtr,
+					  Control & ~XDC_DMACR_SG_DISABLE_MASK);
+	}
+
+	/* update the list data based upon putting a descriptor into the list,
+	 * these operations must be last
+	 */
+	InstancePtr->ActiveDescriptorCount++;
+
+	/* only update the commit pointer if it is not already active, this allows
+	 * it to be deactivated after every commit such that a single descriptor
+	 * which is committed does not appear to be waiting to be committed
+	 */
+	if (InstancePtr->CommitPtr == NULL) {
+		InstancePtr->CommitPtr = InstancePtr->LastPtr;
+	}
+
+	/* these updates MUST BE LAST after the commit pointer update in order for
+	 * the commit pointer to track the correct descriptor to be committed
+	 */
+	InstancePtr->LastPtr = InstancePtr->PutPtr;
+	InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr);
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_CommitPuts
+*
+* DESCRIPTION:
+*
+* This function commits the buffer descriptors which have been put into the
+* scatter list for the DMA channel since the last commit operation was
+* performed.  This enables the calling functions to put several buffer
+* descriptors into the list (e.g.,a packet's worth) before allowing the scatter
+* gather operations to start.  This prevents the DMA channel hardware from
+* starting to use the buffer descriptors in the list before they are ready
+* to be used (multiple buffer descriptors for a single packet).
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* A status indicating XST_SUCCESS if the buffer descriptors of the list were
+* successfully committed.
+*
+* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors
+* were not committed because there was nothing to commit in the list.  All the
+* buffer descriptors which are in the list are commited.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_CommitPuts(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the buffer descriptor to be committed is already committed or
+	 * the list is empty (none have been put in), then indicate an error
+	 */
+	if ((InstancePtr->CommitPtr == NULL) ||
+	    XDmaChannel_IsSgListEmpty(InstancePtr)) {
+		return XST_DMA_SG_NOTHING_TO_COMMIT;
+	}
+
+	/* last descriptor in the list must have scatter gather disabled so the end
+	 * of the list is hit by h/w, if descriptor to commit is not last in list,
+	 * commit descriptors by enabling scatter gather in the descriptor
+	 */
+	if (InstancePtr->CommitPtr != InstancePtr->LastPtr) {
+		u32 Control;
+
+		Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr);
+		XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control &
+					  ~XDC_DMACR_SG_DISABLE_MASK);
+	}
+	/* Update the commit pointer to indicate that there is nothing to be
+	 * committed, this state is used by start processing to know that the
+	 * buffer descriptor to start is not waiting to be committed
+	 */
+	InstancePtr->CommitPtr = NULL;
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetDescriptor
+*
+* DESCRIPTION:
+*
+* This function gets a buffer descriptor from the scatter gather list of the
+* DMA channel. The buffer descriptor is retrieved from the scatter gather list
+* and the scatter gather list is updated to not include the retrieved buffer
+* descriptor.  This is typically done after a scatter gather operation
+* completes indicating that a data buffer has been successfully sent or data
+* has been received into the data buffer. The purpose of this function is to
+* allow the device using the scatter gather operation to get the results of the
+* operation.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which
+* was retrieved from the list.	The buffer descriptor is not really removed
+* from the list, but it is changed to a state such that the hardware will not
+* use it again until it is put into the scatter gather list of the DMA channel.
+*
+* RETURN VALUE:
+*
+* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from
+* the scatter gather list of the DMA channel.
+*
+* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
+* been created.
+*
+* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was
+* retrieved from the list because there are no buffer descriptors to be
+* processed in the list.
+*
+* BufDescriptorPtr is updated to point to the buffer descriptor which was
+* retrieved from the list if the status indicates success.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
+			  XBufDescriptor ** BufDescriptorPtr)
+{
+	u32 Control;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufDescriptorPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if a scatter gather list has not been created yet, return a status */
+
+	if (InstancePtr->TotalDescriptorCount == 0) {
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* if the buffer descriptor list is empty, then indicate an error */
+
+	if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
+		return XST_DMA_SG_LIST_EMPTY;
+	}
+
+	/* retrieve the next buffer descriptor which is ready to be processed from
+	 * the buffer descriptor list for the DMA channel, set the control word
+	 * such that hardware will stop after the descriptor has been processed
+	 */
+	Control = XBufDescriptor_GetControl(InstancePtr->GetPtr);
+	XBufDescriptor_SetControl(InstancePtr->GetPtr,
+				  Control | XDC_DMACR_SG_DISABLE_MASK);
+
+	/* set the input argument, which is also an output, to point to the
+	 * buffer descriptor which is to be retrieved from the list
+	 */
+	*BufDescriptorPtr = InstancePtr->GetPtr;
+
+	/* update the pointer of the DMA channel to reflect the buffer descriptor
+	 * was retrieved from the list by setting it to the next buffer descriptor
+	 * in the list and indicate one less descriptor in the list now
+	 */
+	InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr);
+	InstancePtr->ActiveDescriptorCount--;
+
+	return XST_SUCCESS;
+}
+
+/*********************** Interrupt Collescing Functions **********************/
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetPktCount
+*
+* DESCRIPTION:
+*
+* This function returns the value of the unserviced packet count register of
+* the DMA channel.  This count represents the number of packets that have been
+* sent or received by the hardware, but not processed by software.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* The unserviced packet counter register contents for the DMA channel.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetPktCount(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the unserviced packet count from the register and return it */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_DecrementPktCount
+*
+* DESCRIPTION:
+*
+* This function decrements the value of the unserviced packet count register.
+* This informs the hardware that the software has processed a packet.  The
+* unserviced packet count register may only be decremented by one in the
+* hardware.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr)
+{
+	u32 Register;
+
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the unserviced packet count register can be decremented (rather
+	 * than rolling over) decrement it by writing a 1 to the register,
+	 * this is the only valid write to the register as it serves as an
+	 * acknowledge that a packet was handled by the software
+	 */
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
+	if (Register > 0) {
+		XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET,
+			  1UL);
+	}
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetPktThreshold
+*
+* DESCRIPTION:
+*
+* This function sets the value of the packet count threshold register of the
+* DMA channel.	It reflects the number of packets that must be sent or
+* received before generating an interrupt.  This value helps implement
+* a concept called "interrupt coalescing", which is used to reduce the number
+* of interrupts from devices with high data rates.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* Threshold is the value that is written to the threshold register of the
+* DMA channel.
+*
+* RETURN VALUE:
+*
+* A status containing XST_SUCCESS if the packet count threshold was
+* successfully set.
+*
+* NOTES:
+*
+* The packet threshold could be set to larger than the number of descriptors
+* allocated to the DMA channel. In this case, the wait bound will take over
+* and always indicate data arrival. There was a check in this function that
+* returned an error if the treshold was larger than the number of descriptors,
+* but that was removed because users would then have to set the threshold
+* only after they set descriptor space, which is an order dependency that
+* caused confustion.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold)
+{
+	/* assert to verify input arguments, don't assert the threshold since
+	 * it's range is unknown
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the packet count threshold in the register such that an interrupt
+	 * may be generated, if enabled, when the packet count threshold is
+	 * reached or exceeded
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET,
+		  (u32) Threshold);
+
+	/* indicate the packet count threshold was successfully set */
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetPktThreshold
+*
+* DESCRIPTION:
+*
+* This function gets the value of the packet count threshold register of the
+* DMA channel.	This value reflects the number of packets that must be sent or
+* received before generating an interrupt.  This value helps implement a concept
+* called "interrupt coalescing", which is used to reduce the number of
+* interrupts from devices with high data rates.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* The packet threshold register contents for the DMA channel and is a value in
+* the range 0 - 1023.  A value of 0 indicates the packet wait bound timer is
+* disabled.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u8
+XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the packet count threshold from the register and return it,
+	 * since only 8 bits are used, cast it to return only those bits */
+
+	return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetPktWaitBound
+*
+* DESCRIPTION:
+*
+* This function sets the value of the packet wait bound register of the
+* DMA channel.	This value reflects the timer value used to trigger an
+* interrupt when not enough packets have been received to reach the packet
+* count threshold.
+*
+* The timer is in millisecond units with +/- 33% accuracy.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* WaitBound is the value, in milliseconds, to be stored in the wait bound
+* register of the DMA channel and is a value in the range 0  - 1023.  A value
+* of 0 disables the packet wait bound timer.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(WaitBound < 1024);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the packet wait bound in the register such that interrupt may be
+	 * generated, if enabled, when packets have not been handled for a specific
+	 * amount of time
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetPktWaitBound
+*
+* DESCRIPTION:
+*
+* This function gets the value of the packet wait bound register of the
+* DMA channel.	This value contains the timer value used to trigger an
+* interrupt when not enough packets have been received to reach the packet
+* count threshold.
+*
+* The timer is in millisecond units with +/- 33% accuracy.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* The packet wait bound register contents for the DMA channel.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the packet wait bound from the register and return it */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET);
+}
diff --git a/u-boot/board/xilinx/common/xio.h b/u-boot/board/xilinx/common/xio.h
new file mode 100644
index 0000000..5bb09c8
--- /dev/null
+++ b/u-boot/board/xilinx/common/xio.h
@@ -0,0 +1,81 @@
+/*
+ * xio.h
+ *
+ * Defines XIo functions for Xilinx OCP in terms of Linux primitives
+ *
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef XIO_H
+#define XIO_H
+
+#include "xbasic_types.h"
+#include <asm/io.h>
+
+typedef u32 XIo_Address;
+
+extern inline u8
+XIo_In8(XIo_Address InAddress)
+{
+	return (u8) in_8((volatile unsigned char *) InAddress);
+}
+extern inline u16
+XIo_In16(XIo_Address InAddress)
+{
+	return (u16) in_be16((volatile unsigned short *) InAddress);
+}
+extern inline u32
+XIo_In32(XIo_Address InAddress)
+{
+	return (u32) in_be32((volatile unsigned *) InAddress);
+}
+extern inline void
+XIo_Out8(XIo_Address OutAddress, u8 Value)
+{
+	out_8((volatile unsigned char *) OutAddress, Value);
+}
+extern inline void
+XIo_Out16(XIo_Address OutAddress, u16 Value)
+{
+	out_be16((volatile unsigned short *) OutAddress, Value);
+}
+extern inline void
+XIo_Out32(XIo_Address OutAddress, u32 Value)
+{
+	out_be32((volatile unsigned *) OutAddress, Value);
+}
+
+#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
+#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
+#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
+#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
+
+#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
+#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
+#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
+#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
+
+#endif				/* XIO_H */
diff --git a/u-boot/board/xilinx/common/xipif_v1_23_b.c b/u-boot/board/xilinx/common/xipif_v1_23_b.c
new file mode 100644
index 0000000..c7311ab
--- /dev/null
+++ b/u-boot/board/xilinx/common/xipif_v1_23_b.c
@@ -0,0 +1,331 @@
+/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
+/******************************************************************************
+*
+*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*       FOR A PARTICULAR PURPOSE.
+*
+*       (c) Copyright 2002 Xilinx Inc.
+*       All rights reserved.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* FILENAME:
+*
+* xipif.c
+*
+* DESCRIPTION:
+*
+* This file contains the implementation of the XIpIf component. The
+* XIpIf component encapsulates the IPIF, which is the standard interface
+* that IP must adhere to when connecting to a bus.  The purpose of this
+* component is to encapsulate the IPIF processing such that maintainability
+* is increased.  This component does not provide a lot of abstraction from
+* from the details of the IPIF as it is considered a building block for
+* device drivers.  A device driver designer must be familiar with the
+* details of the IPIF hardware to use this component.
+*
+* The IPIF hardware provides a building block for all hardware devices such
+* that each device does not need to reimplement these building blocks. The
+* IPIF contains other building blocks, such as FIFOs and DMA channels, which
+* are also common to many devices.  These blocks are implemented as separate
+* hardware blocks and instantiated within the IPIF.  The primary hardware of
+* the IPIF which is implemented by this software component is the interrupt
+* architecture.  Since there are many blocks of a device which may generate
+* interrupts, all the interrupt processing is contained in the common part
+* of the device, the IPIF.  This interrupt processing is for the device level
+* only and does not include any processing for the interrupt controller.
+*
+* A device is a mechanism such as an Ethernet MAC.  The device is made
+* up of several parts which include an IPIF and the IP.  The IPIF contains most
+* of the device infrastructure which is common to all devices, such as
+* interrupt processing, DMA channels, and FIFOs.  The infrastructure may also
+* be referred to as IPIF internal blocks since they are part of the IPIF and
+* are separate blocks that can be selected based upon the needs of the device.
+* The IP of the device is the logic that is unique to the device and interfaces
+* to the IPIF of the device.
+*
+* In general, there are two levels of registers within the IPIF.  The first
+* level, referred to as the device level, contains registers which are for the
+* entire device.  The second level, referred to as the IP level, contains
+* registers which are specific to the IP of the device.  The two levels of
+* registers are designed to be hierarchical such that the device level is
+* is a more general register set above the more specific registers of the IP.
+* The IP level of registers provides functionality which is typically common
+* across all devices and allows IP designers to focus on the unique aspects
+* of the IP.
+*
+* The interrupt registers of the IPIF are parameterizable such that the only
+* the number of bits necessary for the device are implemented. The functions
+* of this component do not attempt to validate that the passed in arguments are
+* valid based upon the number of implemented bits.  This is necessary to
+* maintain the level of performance required for the common components.  Bits
+* of the registers are assigned starting at the least significant bit of the
+* registers.
+*
+* Critical Sections
+*
+* It is the responsibility of the device driver designer to use critical
+* sections as necessary when calling functions of the IPIF.  This component
+* does not use critical sections and it does access registers using
+* read-modify-write operations.  Calls to IPIF functions from a main thread
+* and from an interrupt context could produce unpredictable behavior such that
+* the caller must provide the appropriate critical sections.
+*
+* Mutual Exclusion
+*
+* The functions of the IPIF are not thread safe such that the caller of all
+* functions is responsible for ensuring mutual exclusion for an IPIF.  Mutual
+* exclusion across multiple IPIF components is not necessary.
+*
+* NOTES:
+*
+* None.
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.23b jhl  02/27/01 Repartioned to reduce size
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xipif_v1_23_b.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constant is used to generate bit masks for register testing
+ * in the self test functions, it defines the starting bit mask that is to be
+ * shifted from the LSB to MSB in creating a register test mask
+ */
+#define XIIF_V123B_FIRST_BIT_MASK     1UL
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XIpIf_SelfTest
+*
+* DESCRIPTION:
+*
+* This function performs a self test on the specified IPIF component.  Many
+* of the registers in the IPIF are tested to ensure proper operation.  This
+* function is destructive because the IPIF is reset at the start of the test
+* and at the end of the test to ensure predictable results.  The IPIF reset
+* also resets the entire device that uses the IPIF.  This function exits with
+* all interrupts for the device disabled.
+*
+* ARGUMENTS:
+*
+* InstancePtr points to the XIpIf to operate on.
+*
+* DeviceRegistersWidth contains the number of bits in the device interrupt
+* registers. The hardware is parameterizable such that only the number of bits
+* necessary to support a device are implemented.  This value must be between 0
+* and 32 with 0 indicating there are no device interrupt registers used.
+*
+* IpRegistersWidth contains the number of bits in the IP interrupt registers
+* of the device.  The hardware is parameterizable such that only the number of
+* bits necessary to support a device are implemented.  This value must be
+* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
+*
+* RETURN VALUE:
+*
+* A value of XST_SUCCESS indicates the test was successful with no errors.
+* Any one of the following error values may also be returned.
+*
+*   XST_IPIF_RESET_REGISTER_ERROR       The value of a register at reset was
+*                                       not valid
+*   XST_IPIF_IP_STATUS_ERROR            A write to the IP interrupt status
+*                                       register did not read back correctly
+*   XST_IPIF_IP_ACK_ERROR               One or more bits in the IP interrupt
+*                                       status register did not reset when acked
+*   XST_IPIF_IP_ENABLE_ERROR            The IP interrupt enable register
+*                                       did not read back correctly based upon
+*                                       what was written to it
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+
+/* the following constant defines the maximum number of bits which may be
+ * used in the registers at the device and IP levels, this is based upon the
+ * number of bits available in the registers
+ */
+#define XIIF_V123B_MAX_REG_BIT_COUNT 32
+
+XStatus
+XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
+{
+	XStatus Status;
+
+	/* assert to verify arguments are valid */
+
+	XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
+
+	/* reset the IPIF such that it's in a known state before the test
+	 * and interrupts are globally disabled
+	 */
+	XIIF_V123B_RESET(RegBaseAddress);
+
+	/* perform the self test on the IP interrupt registers, if
+	 * it is not successful exit with the status
+	 */
+	Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/* reset the IPIF such that it's in a known state before exiting test */
+
+	XIIF_V123B_RESET(RegBaseAddress);
+
+	/* reaching this point means there were no errors, return success */
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* IpIntrSelfTest
+*
+* DESCRIPTION:
+*
+* Perform a self test on the IP interrupt registers of the IPIF. This
+* function modifies registers of the IPIF such that they are not guaranteed
+* to be in the same state when it returns.  Any bits in the IP interrupt
+* status register which are set are assumed to be set by default after a reset
+* and are not tested in the test.
+*
+* ARGUMENTS:
+*
+* InstancePtr points to the XIpIf to operate on.
+*
+* IpRegistersWidth contains the number of bits in the IP interrupt registers
+* of the device.  The hardware is parameterizable such that only the number of
+* bits necessary to support a device are implemented.  This value must be
+* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
+*
+* RETURN VALUE:
+*
+* A status indicating XST_SUCCESS if the test was successful.  Otherwise, one
+* of the following values is returned.
+*
+*   XST_IPIF_RESET_REGISTER_ERROR       The value of a register at reset was
+*                                       not valid
+*   XST_IPIF_IP_STATUS_ERROR            A write to the IP interrupt status
+*                                       register did not read back correctly
+*   XST_IPIF_IP_ACK_ERROR               One or more bits in the IP status
+*                                       register did not reset when acked
+*   XST_IPIF_IP_ENABLE_ERROR            The IP interrupt enable register
+*                                       did not read back correctly based upon
+*                                       what was written to it
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+static XStatus
+IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
+{
+	/* ensure that the IP interrupt interrupt enable register is  zero
+	 * as it should be at reset, the interrupt status is dependent upon the
+	 * IP such that it's reset value is not known
+	 */
+	if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
+		return XST_IPIF_RESET_REGISTER_ERROR;
+	}
+
+	/* if there are any used IP interrupts, then test all of the interrupt
+	 * bits in all testable registers
+	 */
+	if (IpRegistersWidth > 0) {
+		u32 BitCount;
+		u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
+		u32 Mask = XIIF_V123B_FIRST_BIT_MASK;	/* bits assigned MSB to LSB */
+		u32 InterruptStatus;
+
+		/* generate the register masks to be used for IP register tests, the
+		 * number of bits supported by the hardware is parameterizable such
+		 * that only that number of bits are implemented in the registers, the
+		 * bits are allocated starting at the MSB of the registers
+		 */
+		for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
+			Mask = Mask << 1;
+			IpInterruptMask |= Mask;
+		}
+
+		/* get the current IP interrupt status register contents, any bits
+		 * already set must default to 1 at reset in the device and these
+		 * bits can't be tested in the following test, remove these bits from
+		 * the mask that was generated for the test
+		 */
+		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
+		IpInterruptMask &= ~InterruptStatus;
+
+		/* set the bits in the device status register and verify them by reading
+		 * the register again, all bits of the register are latched
+		 */
+		XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
+		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
+		if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
+		{
+			return XST_IPIF_IP_STATUS_ERROR;
+		}
+
+		/* test to ensure that the bits set in the IP interrupt status register
+		 * can be cleared by acknowledging them in the IP interrupt status
+		 * register then read it again and verify it was cleared
+		 */
+		XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
+		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
+		if ((InterruptStatus & IpInterruptMask) != 0) {
+			return XST_IPIF_IP_ACK_ERROR;
+		}
+
+		/* set the IP interrupt enable set register and then read the IP
+		 * interrupt enable register and verify the interrupts were enabled
+		 */
+		XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
+		if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
+			return XST_IPIF_IP_ENABLE_ERROR;
+		}
+
+		/* clear the IP interrupt enable register and then read the
+		 * IP interrupt enable register and verify the interrupts were disabled
+		 */
+		XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
+		if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
+			return XST_IPIF_IP_ENABLE_ERROR;
+		}
+	}
+	return XST_SUCCESS;
+}
diff --git a/u-boot/board/xilinx/common/xipif_v1_23_b.h b/u-boot/board/xilinx/common/xipif_v1_23_b.h
new file mode 100644
index 0000000..3ce1fff
--- /dev/null
+++ b/u-boot/board/xilinx/common/xipif_v1_23_b.h
@@ -0,0 +1,746 @@
+/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
+/******************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* FILENAME:
+*
+* xipif.h
+*
+* DESCRIPTION:
+*
+* The XIpIf component encapsulates the IPIF, which is the standard interface
+* that IP must adhere to when connecting to a bus.  The purpose of this
+* component is to encapsulate the IPIF processing such that maintainability
+* is increased.	 This component does not provide a lot of abstraction from
+* from the details of the IPIF as it is considered a building block for
+* device drivers.  A device driver designer must be familiar with the
+* details of the IPIF hardware to use this component.
+*
+* The IPIF hardware provides a building block for all hardware devices such
+* that each device does not need to reimplement these building blocks. The
+* IPIF contains other building blocks, such as FIFOs and DMA channels, which
+* are also common to many devices.  These blocks are implemented as separate
+* hardware blocks and instantiated within the IPIF.  The primary hardware of
+* the IPIF which is implemented by this software component is the interrupt
+* architecture.	 Since there are many blocks of a device which may generate
+* interrupts, all the interrupt processing is contained in the common part
+* of the device, the IPIF.  This interrupt processing is for the device level
+* only and does not include any processing for the interrupt controller.
+*
+* A device is a mechanism such as an Ethernet MAC.  The device is made
+* up of several parts which include an IPIF and the IP.	 The IPIF contains most
+* of the device infrastructure which is common to all devices, such as
+* interrupt processing, DMA channels, and FIFOs.  The infrastructure may also
+* be referred to as IPIF internal blocks since they are part of the IPIF and
+* are separate blocks that can be selected based upon the needs of the device.
+* The IP of the device is the logic that is unique to the device and interfaces
+* to the IPIF of the device.
+*
+* In general, there are two levels of registers within the IPIF.  The first
+* level, referred to as the device level, contains registers which are for the
+* entire device.  The second level, referred to as the IP level, contains
+* registers which are specific to the IP of the device.	 The two levels of
+* registers are designed to be hierarchical such that the device level is
+* is a more general register set above the more specific registers of the IP.
+* The IP level of registers provides functionality which is typically common
+* across all devices and allows IP designers to focus on the unique aspects
+* of the IP.
+*
+* Critical Sections
+*
+* It is the responsibility of the device driver designer to use critical
+* sections as necessary when calling functions of the IPIF.  This component
+* does not use critical sections and it does access registers using
+* read-modify-write operations.	 Calls to IPIF functions from a main thread
+* and from an interrupt context could produce unpredictable behavior such that
+* the caller must provide the appropriate critical sections.
+*
+* Mutual Exclusion
+*
+* The functions of the IPIF are not thread safe such that the caller of all
+* functions is responsible for ensuring mutual exclusion for an IPIF.  Mutual
+* exclusion across multiple IPIF components is not necessary.
+*
+* NOTES:
+*
+* None.
+*
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.23b jhl  02/27/01 Repartioned to minimize size
+*
+******************************************************************************/
+
+#ifndef XIPIF_H			/* prevent circular inclusions */
+#define XIPIF_H			/* by using protection macros */
+
+/***************************** Include Files *********************************/
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants define the register offsets for the registers of the
+ * IPIF, there are some holes in the memory map for reserved addresses to allow
+ * other registers to be added and still match the memory map of the interrupt
+ * controller registers
+ */
+#define XIIF_V123B_DISR_OFFSET	   0UL	/* device interrupt status register */
+#define XIIF_V123B_DIPR_OFFSET	   4UL	/* device interrupt pending register */
+#define XIIF_V123B_DIER_OFFSET	   8UL	/* device interrupt enable register */
+#define XIIF_V123B_DIIR_OFFSET	   24UL /* device interrupt ID register */
+#define XIIF_V123B_DGIER_OFFSET	   28UL /* device global interrupt enable reg */
+#define XIIF_V123B_IISR_OFFSET	   32UL /* IP interrupt status register */
+#define XIIF_V123B_IIER_OFFSET	   40UL /* IP interrupt enable register */
+#define XIIF_V123B_RESETR_OFFSET   64UL /* reset register */
+
+#define XIIF_V123B_RESET_MASK		  0xAUL
+
+/* the following constant is used for the device global interrupt enable
+ * register, to enable all interrupts for the device, this is the only bit
+ * in the register
+ */
+#define XIIF_V123B_GINTR_ENABLE_MASK	  0x80000000UL
+
+/* the following constants contain the masks to identify each internal IPIF
+ * condition in the device registers of the IPIF, interrupts are assigned
+ * in the register from LSB to the MSB
+ */
+#define XIIF_V123B_ERROR_MASK		  1UL	/* LSB of the register */
+
+/* The following constants contain interrupt IDs which identify each internal
+ * IPIF condition, this value must correlate with the mask constant for the
+ * error
+ */
+#define XIIF_V123B_ERROR_INTERRUPT_ID	  0	/* interrupt bit #, (LSB = 0) */
+#define XIIF_V123B_NO_INTERRUPT_ID	  128	/* no interrupts are pending */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_RESET
+*
+* DESCRIPTION:
+*
+* Reset the IPIF component and hardware.  This is a destructive operation that
+* could cause the loss of data since resetting the IPIF of a device also
+* resets the device using the IPIF and any blocks, such as FIFOs or DMA
+* channels, within the IPIF.  All registers of the IPIF will contain their
+* reset value when this function returns.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+
+/* the following constant is used in the reset register to cause the IPIF to
+ * reset
+ */
+#define XIIF_V123B_RESET(RegBaseAddress) \
+    XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_DISR
+*
+* DESCRIPTION:
+*
+* This function sets the device interrupt status register to the value.
+* This register indicates the status of interrupt sources for a device
+* which contains the IPIF.  The status is independent of whether interrupts
+* are enabled and could be used for polling a device at a higher level rather
+* than a more detailed level.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  With the exception of some internal IPIF
+* conditions, the contents of this register are not latched but indicate
+* the live status of the interrupt sources within the device.  Writing any of
+* the non-latched bits of the register will have no effect on the register.
+*
+* For the latched bits of this register only, setting a bit which is zero
+* within this register causes an interrupt to generated.  The device global
+* interrupt enable register and the device interrupt enable register must be set
+* appropriately to allow an interrupt to be passed out of the device. The
+* interrupt is cleared by writing to this register with the bits to be
+* cleared set to a one and all others to zero.	This register implements a
+* toggle on write functionality meaning any bits which are set in the value
+* written cause the bits in the register to change to the opposite state.
+*
+* This function writes the specified value to the register such that
+* some bits may be set and others cleared.  It is the caller's responsibility
+* to get the value of the register prior to setting the value to prevent a
+* destructive behavior.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Status contains the value to be written to the interrupt status register of
+* the device.  The only bits which can be written are the latched bits which
+* contain the internal IPIF conditions.	 The following values may be used to
+* set the status register or clear an interrupt condition.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DISR
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt status register contents.
+* This register indicates the status of interrupt sources for a device
+* which contains the IPIF.  The status is independent of whether interrupts
+* are enabled and could be used for polling a device at a higher level.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  With the exception of some internal IPIF
+* conditions, the contents of this register are not latched but indicate
+* the live status of the interrupt sources within the device.
+*
+* For only the latched bits of this register, the interrupt may be cleared by
+* writing to these bits in the status register.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* A status which contains the value read from the interrupt status register of
+* the device. The bit definitions are specific to the device with
+* the exception of the latched internal IPIF condition bits. The following
+* values may be used to detect internal IPIF conditions in the status.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DISR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_DIER
+*
+* DESCRIPTION:
+*
+* This function sets the device interrupt enable register contents.
+* This register controls which interrupt sources of the device are allowed to
+* generate an interrupt.  The device global interrupt enable register must also
+* be set appropriately for an interrupt to be passed out of the device.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  Setting a bit in this register enables that
+* interrupt source to generate an interrupt.  Clearing a bit in this register
+* disables interrupt generation for that interrupt source.
+*
+* This function writes only the specified value to the register such that
+* some interrupts source may be enabled and others disabled.  It is the
+* caller's responsibility to get the value of the interrupt enable register
+* prior to setting the value to prevent an destructive behavior.
+*
+* An interrupt source may not be enabled to generate an interrupt, but can
+* still be polled in the interrupt status register.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Enable contains the value to be written to the interrupt enable register
+* of the device.  The bit definitions are specific to the device with
+* the exception of the internal IPIF conditions. The following
+* values may be used to enable the internal IPIF conditions interrupts.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
+*					  u32 Enable)
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DIER
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt enable register contents.
+* This register controls which interrupt sources of the device
+* are allowed to generate an interrupt.	 The device global interrupt enable
+* register and the device interrupt enable register must also be set
+* appropriately for an interrupt to be passed out of the device.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  Setting a bit in this register enables that
+* interrupt source to generate an interrupt if the global enable is set
+* appropriately.  Clearing a bit in this register disables interrupt generation
+* for that interrupt source regardless of the global interrupt enable.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* The value read from the interrupt enable register of the device.  The bit
+* definitions are specific to the device with the exception of the internal
+* IPIF conditions. The following values may be used to determine from the
+* value if the internal IPIF conditions interrupts are enabled.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DIER(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DIPR
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt pending register contents.
+* This register indicates the pending interrupt sources, those that are waiting
+* to be serviced by the software, for a device which contains the IPIF.
+* An interrupt must be enabled in the interrupt enable register of the IPIF to
+* be pending.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* the device which contains the IPIF.  With the exception of some internal IPIF
+* conditions, the contents of this register are not latched since the condition
+* is latched in the IP interrupt status register, by an internal block of the
+* IPIF such as a FIFO or DMA channel, or by the IP of the device.  This register
+* is read only and is not latched, but it is necessary to acknowledge (clear)
+* the interrupt condition by performing the appropriate processing for the IP
+* or block within the IPIF.
+*
+* This register can be thought of as the contents of the interrupt status
+* register ANDed with the contents of the interrupt enable register.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* The value read from the interrupt pending register of the device.  The bit
+* definitions are specific to the device with the exception of the latched
+* internal IPIF condition bits. The following values may be used to detect
+* internal IPIF conditions in the value.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DIIR
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt ID for the highest priority interrupt
+* which is pending from the interrupt ID register. This function provides
+* priority resolution such that faster interrupt processing is possible.
+* Without priority resolution, it is necessary for the software to read the
+* interrupt pending register and then check each interrupt source to determine
+* if an interrupt is pending.  Priority resolution becomes more important as the
+* number of interrupt sources becomes larger.
+*
+* Interrupt priorities are based upon the bit position of the interrupt in the
+* interrupt pending register with bit 0 being the highest priority. The
+* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
+* highest priority. The interrupt ID register is live rather than latched such
+* that multiple calls to this function may not yield the same results.	A
+* special value, outside of the interrupt priority range of 0 - 31, is
+* contained in the register which indicates that no interrupt is pending.  This
+* may be useful for allowing software to continue processing interrupts in a
+* loop until there are no longer any interrupts pending.
+*
+* The interrupt ID is designed to allow a function pointer table to be used
+* in the software such that the interrupt ID is used as an index into that
+* table.  The function pointer table could contain an instance pointer, such
+* as to DMA channel, and a function pointer to the function which handles
+* that interrupt.  This design requires the interrupt processing of the device
+* driver to be partitioned into smaller more granular pieces based upon
+* hardware used by the device, such as DMA channels and FIFOs.
+*
+* It is not mandatory that this function be used by the device driver software.
+* It may choose to read the pending register and resolve the pending interrupt
+* priorities on it's own.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
+* which is pending.  A value of XIIF_NO_INTERRUPT_ID indicates that there is
+* no interrupt pending. The following values may be used to identify the
+* interrupt ID for the internal IPIF interrupts.
+*
+*   XIIF_V123B_ERROR_INTERRUPT_ID     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_GLOBAL_INTR_DISABLE
+*
+* DESCRIPTION:
+*
+* This function disables all interrupts for the device by writing to the global
+* interrupt enable register.  This register provides the ability to disable
+* interrupts without any modifications to the interrupt enable register such
+* that it is minimal effort to restore the interrupts to the previous enabled
+* state.  The corresponding function, XIpIf_GlobalIntrEnable, is provided to
+* restore the interrupts to the previous enabled state.	 This function is
+* designed to be used in critical sections of device drivers such that it is
+* not necessary to disable other device interrupts.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_GINTR_ENABLE
+*
+* DESCRIPTION:
+*
+* This function writes to the global interrupt enable register to enable
+* interrupts from the device.  This register provides the ability to enable
+* interrupts without any modifications to the interrupt enable register such
+* that it is minimal effort to restore the interrupts to the previous enabled
+* state.  This function does not enable individual interrupts as the interrupt
+* enable register must be set appropriately.  This function is designed to be
+* used in critical sections of device drivers such that it is not necessary to
+* disable other device interrupts.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress)		  \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
+	       XIIF_V123B_GINTR_ENABLE_MASK)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_IS_GINTR_ENABLED
+*
+* DESCRIPTION:
+*
+* This function determines if interrupts are enabled at the global level by
+* reading the gloabl interrupt register. This register provides the ability to
+* disable interrupts without any modifications to the interrupt enable register
+* such that it is minimal effort to restore the interrupts to the previous
+* enabled state.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress)		\
+    (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) ==	\
+	      XIIF_V123B_GINTR_ENABLE_MASK)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_IISR
+*
+* DESCRIPTION:
+*
+* This function sets the IP interrupt status register to the specified value.
+* This register indicates the status of interrupt sources for the IP of the
+* device.  The IP is defined as the part of the device that connects to the
+* IPIF.	 The status is independent of whether interrupts are enabled such that
+* the status register may also be polled when interrupts are not enabled.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* IP.  All bits of this register are latched. Setting a bit which is zero
+* within this register causes an interrupt to be generated.  The device global
+* interrupt enable register and the device interrupt enable register must be set
+* appropriately to allow an interrupt to be passed out of the device. The
+* interrupt is cleared by writing to this register with the bits to be
+* cleared set to a one and all others to zero.	This register implements a
+* toggle on write functionality meaning any bits which are set in the value
+* written cause the bits in the register to change to the opposite state.
+*
+* This function writes only the specified value to the register such that
+* some status bits may be set and others cleared.  It is the caller's
+* responsibility to get the value of the register prior to setting the value
+* to prevent an destructive behavior.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Status contains the value to be written to the IP interrupt status
+* register.  The bit definitions are specific to the device IP.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_IISR
+*
+* DESCRIPTION:
+*
+* This function gets the contents of the IP interrupt status register.
+* This register indicates the status of interrupt sources for the IP of the
+* device.  The IP is defined as the part of the device that connects to the
+* IPIF. The status is independent of whether interrupts are enabled such
+* that the status register may also be polled when interrupts are not enabled.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device.  All bits of this register are latched.  Writing a 1 to a bit within
+* this register causes an interrupt to be generated if enabled in the interrupt
+* enable register and the global interrupt enable is set.  Since the status is
+* latched, each status bit must be acknowledged in order for the bit in the
+* status register to be updated.  Each bit can be acknowledged by writing a
+* 0 to the bit in the status register.
+
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* A status which contains the value read from the IP interrupt status register.
+* The bit definitions are specific to the device IP.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_IISR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_IIER
+*
+* DESCRIPTION:
+*
+* This function sets the IP interrupt enable register contents.	 This register
+* controls which interrupt sources of the IP are allowed to generate an
+* interrupt.  The global interrupt enable register and the device interrupt
+* enable register must also be set appropriately for an interrupt to be
+* passed out of the device containing the IPIF and the IP.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* IP.  Setting a bit in this register enables the interrupt source to generate
+* an interrupt.	 Clearing a bit in this register disables interrupt generation
+* for that interrupt source.
+*
+* This function writes only the specified value to the register such that
+* some interrupt sources may be enabled and others disabled.  It is the
+* caller's responsibility to get the value of the interrupt enable register
+* prior to setting the value to prevent an destructive behavior.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Enable contains the value to be written to the IP interrupt enable register.
+* The bit definitions are specific to the device IP.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_IIER
+*
+* DESCRIPTION:
+*
+*
+* This function gets the IP interrupt enable register contents.	 This register
+* controls which interrupt sources of the IP are allowed to generate an
+* interrupt.  The global interrupt enable register and the device interrupt
+* enable register must also be set appropriately for an interrupt to be
+* passed out of the device containing the IPIF and the IP.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* IP.  Setting a bit in this register enables the interrupt source to generate
+* an interrupt.	 Clearing a bit in this register disables interrupt generation
+* for that interrupt source.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* The contents read from the IP interrupt enable register.  The bit definitions
+* are specific to the device IP.
+*
+* NOTES:
+*
+* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
+*
+******************************************************************************/
+#define XIIF_V123B_READ_IIER(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization Functions
+ */
+XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xpacket_fifo_v1_00_b.c b/u-boot/board/xilinx/common/xpacket_fifo_v1_00_b.c
new file mode 100644
index 0000000..ae2d6d4
--- /dev/null
+++ b/u-boot/board/xilinx/common/xpacket_fifo_v1_00_b.c
@@ -0,0 +1,448 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/*
+*
+* @file xpacket_fifo_v1_00_b.c
+*
+* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h
+* for more information about the component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 03/26/02  First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xstatus.h"
+#include "xpacket_fifo_v1_00_b.h"
+
+/************************** Constant Definitions *****************************/
+
+/* width of a FIFO word */
+
+#define XPF_FIFO_WIDTH_BYTE_COUNT       4UL
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************* Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a packet FIFO.  Initialization resets the
+* FIFO such that it's empty and ready to use.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+* @param RegBaseAddress contains the base address of the registers for
+*        the packet FIFO.
+* @param DataBaseAddress contains the base address of the data for
+*        the packet FIFO.
+*
+* @return
+*
+* Always returns XST_SUCCESS.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
+			    u32 RegBaseAddress, u32 DataBaseAddress)
+{
+	/* assert to verify input argument are valid */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	/* initialize the component variables to the specified state */
+
+	InstancePtr->RegBaseAddress = RegBaseAddress;
+	InstancePtr->DataBaseAddress = DataBaseAddress;
+	InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+	/* reset the FIFO such that it's empty and ready to use and indicate the
+	 * initialization was successful, note that the is ready variable must be
+	 * set prior to calling the reset function to prevent an assert
+	 */
+	XPF_V100B_RESET(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function performs a self-test on the specified packet FIFO.  The self
+* test resets the FIFO and reads a register to determine if it is the correct
+* reset value.  This test is destructive in that any data in the FIFO will
+* be lost.
+*
+* @param InstancePtr is a pointer to the packet FIFO to be operated on.
+*
+* @param FifoType specifies the type of FIFO, read or write, for the self test.
+*        The FIFO type is specified by the values XPF_READ_FIFO_TYPE or
+*        XPF_WRITE_FIFO_TYPE.
+*
+* @return
+*
+* XST_SUCCESS is returned if the selftest is successful, or
+* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the
+* occupancy/vacancy count register after a reset does not match the
+* specified reset value.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType)
+{
+	u32 Register;
+
+	/* assert to verify valid input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) ||
+			(FifoType == XPF_WRITE_FIFO_TYPE));
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* reset the fifo and then check to make sure the occupancy/vacancy
+	 * register contents are correct for a reset condition
+	 */
+	XPF_V100B_RESET(InstancePtr);
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress +
+			    XPF_COUNT_STATUS_REG_OFFSET);
+
+	/* check the value of the register to ensure that it's correct for the
+	 * specified FIFO type since both FIFO types reset to empty, but a bit
+	 * in the register changes definition based upon FIFO type
+	 */
+
+	if (FifoType == XPF_READ_FIFO_TYPE) {
+		/* check the regiser value for a read FIFO which should be empty */
+
+		if (Register != XPF_EMPTY_FULL_MASK) {
+			return XST_PFIFO_BAD_REG_VALUE;
+		}
+	} else {
+		/* check the register value for a write FIFO which should not be full
+		 * on reset
+		 */
+		if ((Register & XPF_EMPTY_FULL_MASK) != 0) {
+			return XST_PFIFO_BAD_REG_VALUE;
+		}
+	}
+
+	/* the test was successful */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is
+* currently 32 bits wide such that an input buffer which is a series of bytes
+* is filled from the FIFO a word at a time. If the requested byte count is not
+* a multiple of 32 bit words, it is necessary for this function to format the
+* remaining 32 bit word from the FIFO into a series of bytes in the buffer.
+* There may be up to 3 extra bytes which must be extracted from the last word
+* of the FIFO and put into the buffer.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+* @param BufferPtr points to the memory buffer to write the data into. This
+*        buffer must be 32 bit aligned or an alignment exception could be
+*        generated. Since this buffer is a byte buffer, the data is assumed to
+*        be endian independent.
+* @param ByteCount contains the number of bytes to read from the FIFO. This
+*        number of bytes must be present in the FIFO or an error will be
+*        returned.
+*
+* @return
+*
+* XST_SUCCESS indicates the operation was successful.  If the number of
+* bytes specified by the byte count is not present in the FIFO
+* XST_PFIFO_LACK_OF_DATA is returned.
+*
+* If the function was successful, the specified buffer is modified to contain
+* the bytes which were removed from the FIFO.
+*
+* @note
+*
+* Note that the exact number of bytes which are present in the FIFO is
+* not known by this function.  It can only check for a number of 32 bit
+* words such that if the byte count specified is incorrect, but is still
+* possible based on the number of words in the FIFO, up to 3 garbage bytes
+* may be present at the end of the buffer.
+* <br><br>
+* This function assumes that if the device consuming data from the FIFO is
+* a byte device, the order of the bytes to be consumed is from the most
+* significant byte to the least significant byte of a 32 bit word removed
+* from the FIFO.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
+		      u8 * BufferPtr, u32 ByteCount)
+{
+	u32 FifoCount;
+	u32 WordCount;
+	u32 ExtraByteCount;
+	u32 *WordBuffer = (u32 *) BufferPtr;
+
+	/* assert to verify valid input arguments including 32 bit alignment of
+	 * the buffer pointer
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufferPtr != NULL);
+	XASSERT_NONVOID(((u32) BufferPtr &
+			 (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the count of how many 32 bit words are in the FIFO, if there aren't
+	 * enought words to satisfy the request, return an error
+	 */
+
+	FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
+			     XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+	if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) {
+		return XST_PFIFO_LACK_OF_DATA;
+	}
+
+	/* calculate the number of words to read from the FIFO before the word
+	 * containing the extra bytes, and calculate the number of extra bytes
+	 * the extra bytes are defined as those at the end of the buffer when
+	 * the buffer does not end on a 32 bit boundary
+	 */
+	WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
+	ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
+
+	/* Read the 32 bit words from the FIFO for all the buffer except the
+	 * last word which contains the extra bytes, the following code assumes
+	 * that the buffer is 32 bit aligned, otherwise an alignment exception could
+	 * be generated
+	 */
+	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
+		WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress);
+	}
+
+	/* if there are extra bytes to handle, read the last word from the FIFO
+	 * and insert the extra bytes into the buffer
+	 */
+	if (ExtraByteCount > 0) {
+		u32 LastWord;
+		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
+
+		/* get the last word from the FIFO for the extra bytes */
+
+		LastWord = XIo_In32(InstancePtr->DataBaseAddress);
+
+		/* one extra byte in the last word, put the byte into the next location
+		 * of the buffer, bytes in a word of the FIFO are ordered from most
+		 * significant byte to least
+		 */
+		if (ExtraByteCount == 1) {
+			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+		}
+
+		/* two extra bytes in the last word, put each byte into the next two
+		 * locations of the buffer
+		 */
+		else if (ExtraByteCount == 2) {
+			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
+		}
+		/* three extra bytes in the last word, put each byte into the next three
+		 * locations of the buffer
+		 */
+		else if (ExtraByteCount == 3) {
+			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
+			ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
+		}
+	}
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide
+* such that an input buffer which is a series of bytes must be written into the
+* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is
+* necessary for this function to format the remaining bytes into a single 32
+* bit word to be inserted into the FIFO. This is necessary to avoid any
+* accesses past the end of the buffer.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+* @param BufferPtr points to the memory buffer that data is to be read from
+*        and written into the FIFO. Since this buffer is a byte buffer, the data
+*        is assumed to be endian independent. This buffer must be 32 bit aligned
+*        or an alignment exception could be generated.
+* @param ByteCount contains the number of bytes to read from the buffer and to
+*        write to the FIFO.
+*
+* @return
+*
+* XST_SUCCESS is returned if the operation succeeded.  If there is not enough
+* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is
+* returned.
+*
+* @note
+*
+* This function assumes that if the device inserting data into the FIFO is
+* a byte device, the order of the bytes in each 32 bit word is from the most
+* significant byte to the least significant byte.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
+		       u8 * BufferPtr, u32 ByteCount)
+{
+	u32 FifoCount;
+	u32 WordCount;
+	u32 ExtraByteCount;
+	u32 *WordBuffer = (u32 *) BufferPtr;
+
+	/* assert to verify valid input arguments including 32 bit alignment of
+	 * the buffer pointer
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufferPtr != NULL);
+	XASSERT_NONVOID(((u32) BufferPtr &
+			 (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the count of how many words may be inserted into the FIFO */
+
+	FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
+			     XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+	/* Calculate the number of 32 bit words required to insert the specified
+	 * number of bytes in the FIFO and determine the number of extra bytes
+	 * if the buffer length is not a multiple of 32 bit words
+	 */
+
+	WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
+	ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
+
+	/* take into account the extra bytes in the total word count */
+
+	if (ExtraByteCount > 0) {
+		WordCount++;
+	}
+
+	/* if there's not enough room in the FIFO to hold the specified
+	 * number of bytes, then indicate an error,
+	 */
+	if (FifoCount < WordCount) {
+		return XST_PFIFO_NO_ROOM;
+	}
+
+	/* readjust the word count to not take into account the extra bytes */
+
+	if (ExtraByteCount > 0) {
+		WordCount--;
+	}
+
+	/* Write all the bytes of the buffer which can be written as 32 bit
+	 * words into the FIFO, waiting to handle the extra bytes seperately
+	 */
+	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
+		XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]);
+	}
+
+	/* if there are extra bytes to handle, extract them from the buffer
+	 * and create a 32 bit word and write it to the FIFO
+	 */
+	if (ExtraByteCount > 0) {
+		u32 LastWord = 0;
+		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
+
+		/* one extra byte in the buffer, put the byte into the last word
+		 * to be inserted into the FIFO, perform this processing inline rather
+		 * than in a loop to help performance
+		 */
+		if (ExtraByteCount == 1) {
+			LastWord = ExtraBytesBuffer[0] << 24;
+		}
+
+		/* two extra bytes in the buffer, put each byte into the last word
+		 * to be inserted into the FIFO
+		 */
+		else if (ExtraByteCount == 2) {
+			LastWord = ExtraBytesBuffer[0] << 24 |
+			    ExtraBytesBuffer[1] << 16;
+		}
+
+		/* three extra bytes in the buffer, put each byte into the last word
+		 * to be inserted into the FIFO
+		 */
+		else if (ExtraByteCount == 3) {
+			LastWord = ExtraBytesBuffer[0] << 24 |
+			    ExtraBytesBuffer[1] << 16 |
+			    ExtraBytesBuffer[2] << 8;
+		}
+
+		/* write the last 32 bit word to the FIFO and return with no errors */
+
+		XIo_Out32(InstancePtr->DataBaseAddress, LastWord);
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/u-boot/board/xilinx/common/xpacket_fifo_v1_00_b.h b/u-boot/board/xilinx/common/xpacket_fifo_v1_00_b.h
new file mode 100644
index 0000000..1cda0e8
--- /dev/null
+++ b/u-boot/board/xilinx/common/xpacket_fifo_v1_00_b.h
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/*
+*
+* @file xpacket_fifo_v1_00_b.h
+*
+* This component is a common component because it's primary purpose is to
+* prevent code duplication in drivers. A driver which must handle a packet
+* FIFO uses this component rather than directly manipulating a packet FIFO.
+*
+* A FIFO is a device which has dual port memory such that one user may be
+* inserting data into the FIFO while another is consuming data from the FIFO.
+* A packet FIFO is designed for use with packet protocols such as Ethernet and
+* ATM.  It is typically only used with devices when DMA and/or Scatter Gather
+* is used.  It differs from a nonpacket FIFO in that it does not provide any
+* interrupts for thresholds of the FIFO such that it is less useful without
+* DMA.
+*
+* @note
+*
+* This component has the capability to generate an interrupt when an error
+* condition occurs.  It is the user's responsibility to provide the interrupt
+* processing to handle the interrupt. This component provides the ability to
+* determine if that interrupt is active, a deadlock condition, and the ability
+* to reset the FIFO to clear the condition. In this condition, the device which
+* is using the FIFO should also be reset to prevent other problems. This error
+* condition could occur as a normal part of operation if the size of the FIFO
+* is not setup correctly.  See the hardware IP specification for more details.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 03/26/02  First release
+* </pre>
+*
+*****************************************************************************/
+#ifndef XPACKET_FIFO_H		/* prevent circular inclusions */
+#define XPACKET_FIFO_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * These constants specify the FIFO type and are mutually exclusive
+ */
+#define XPF_READ_FIFO_TYPE      0	/* a read FIFO */
+#define XPF_WRITE_FIFO_TYPE     1	/* a write FIFO */
+
+/*
+ * These constants define the offsets to each of the registers from the
+ * register base address, each of the constants are a number of bytes
+ */
+#define XPF_RESET_REG_OFFSET            0UL
+#define XPF_MODULE_INFO_REG_OFFSET      0UL
+#define XPF_COUNT_STATUS_REG_OFFSET     4UL
+
+/*
+ * This constant is used with the Reset Register
+ */
+#define XPF_RESET_FIFO_MASK             0x0000000A
+
+/*
+ * These constants are used with the Occupancy/Vacancy Count Register. This
+ * register also contains FIFO status
+ */
+#define XPF_COUNT_MASK                  0x0000FFFF
+#define XPF_DEADLOCK_MASK               0x20000000
+#define XPF_ALMOST_EMPTY_FULL_MASK      0x40000000
+#define XPF_EMPTY_FULL_MASK             0x80000000
+
+/**************************** Type Definitions *******************************/
+
+/*
+ * The XPacketFifo driver instance data. The driver is required to allocate a
+ * variable of this type for every packet FIFO in the device.
+ */
+typedef struct {
+	u32 RegBaseAddress;	/* Base address of registers */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 DataBaseAddress;	/* Base address of data for FIFOs */
+} XPacketFifoV100b;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/*
+*
+* Reset the specified packet FIFO.  Resetting a FIFO will cause any data
+* contained in the FIFO to be lost.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_RESET(InstancePtr) \
+    XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK);
+
+/*****************************************************************************/
+/*
+*
+* Get the occupancy count for a read packet FIFO and the vacancy count for a
+* write packet FIFO. These counts indicate the number of 32-bit words
+* contained (occupancy) in the FIFO or the number of 32-bit words available
+* to write (vacancy) in the FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* The occupancy or vacancy count for the specified packet FIFO.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_GET_COUNT(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_COUNT_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is almost empty. Almost empty is
+* defined for a read FIFO when there is only one data word in the FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is almost empty, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_ALMOST_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is almost full. Almost full is
+* defined for a write FIFO when there is only one available data word in the
+* FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is almost full, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_ALMOST_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is empty. This applies only to a
+* read FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is empty, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_EMPTY(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is full. This applies only to a
+* write FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is full, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_FULL(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is deadlocked.  This condition occurs
+* when the FIFO is full and empty at the same time and is caused by a packet
+* being written to the FIFO which exceeds the total data capacity of the FIFO.
+* It occurs because of the mark/restore features of the packet FIFO which allow
+* retransmission of a packet. The software should reset the FIFO and any devices
+* using the FIFO when this condition occurs.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is deadlocked, FALSE otherwise.
+*
+* @note
+*
+* This component has the capability to generate an interrupt when an error
+* condition occurs.  It is the user's responsibility to provide the interrupt
+* processing to handle the interrupt. This function provides the ability to
+* determine if a deadlock condition, and the ability to reset the FIFO to
+* clear the condition.
+*
+* In this condition, the device which is using the FIFO should also be reset
+* to prevent other problems. This error condition could occur as a normal part
+* of operation if the size of the FIFO is not setup correctly.
+*
+* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_DEADLOCK_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/* Standard functions */
+
+XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
+				    u32 RegBaseAddress, u32 DataBaseAddress);
+XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType);
+
+/* Data functions */
+
+XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
+			      u8 * ReadBufferPtr, u32 ByteCount);
+XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
+			       u8 * WriteBufferPtr, u32 ByteCount);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xstatus.h b/u-boot/board/xilinx/common/xstatus.h
new file mode 100644
index 0000000..ffda4d7
--- /dev/null
+++ b/u-boot/board/xilinx/common/xstatus.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called XStatus.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						 * registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						 * the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						 * interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						 * have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						 * already started i.e.
+						 * sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						 * already stopped i.e.
+						 * sub channel */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Adapter is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid adapter init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The status typedef.
+ */
+typedef u32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/common/xversion.c b/u-boot/board/xilinx/common/xversion.c
new file mode 100644
index 0000000..c8a6915
--- /dev/null
+++ b/u-boot/board/xilinx/common/xversion.c
@@ -0,0 +1,350 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* This file contains the implementation of the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+</pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants define the masks and shift values to allow the
+ * revisions to be packed and unpacked, a packed version is packed into a 16
+ * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
+ * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
+ * revision
+ */
+#define XVE_MAJOR_SHIFT_VALUE       12
+#define XVE_MINOR_ONLY_MASK         0x0FE0
+#define XVE_MINOR_SHIFT_VALUE       5
+#define XVE_COMP_ONLY_MASK          0x001F
+
+/* the following constants define the specific characters of a version string
+ * for each character of the revision, a version string is in the following
+ * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
+ * revision (00 - 99), and Z is the compatability revision (a - z)
+ */
+#define XVE_MAJOR_CHAR      0	/* major revision 0 - 9 */
+#define XVE_MINOR_TENS_CHAR 2	/* minor revision tens 0 - 9 */
+#define XVE_MINOR_ONES_CHAR 3	/* minor revision ones 0 - 9 */
+#define XVE_COMP_CHAR       4	/* compatability revision a - z */
+#define XVE_END_STRING_CHAR 5
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static u32 IsVersionStringValid(s8 * StringPtr);
+
+/*****************************************************************************
+*
+* Unpacks a packed version into the specified version. Versions are packed
+* into the configuration ROM to reduce the amount storage. A packed version
+* is a binary format as oppossed to a non-packed version which is implemented
+* as a string.
+*
+* @param    InstancePtr points to the version to unpack the packed version into.
+* @param    PackedVersion contains the packed version to unpack.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion)
+{
+	/* not implemented yet since CROM related */
+}
+
+/*****************************************************************************
+*
+* Packs a version into the specified packed version. Versions are packed into
+* the configuration ROM to reduce the amount storage.
+*
+* @param    InstancePtr points to the version to pack.
+* @param    PackedVersionPtr points to the packed version which will receive
+*           the new packed version.
+*
+* @return
+*
+* A status, XST_SUCCESS, indicating the packing was accomplished
+* successfully, or an error, XST_INVALID_VERSION, indicating the specified
+* input version was not valid such that the pack did not occur
+* <br><br>
+* The packed version pointed to by PackedVersionPtr is modified with the new
+* packed version if the status indicates success.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr)
+{
+	/* not implemented yet since CROM related */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************
+*
+* Determines if two versions are equal.
+*
+* @param    InstancePtr points to the first version to be compared.
+* @param    VersionPtr points to a second version to be compared.
+*
+* @return
+*
+* TRUE if the versions are equal, FALSE otherwise.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+u32
+XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr)
+{
+	u8 *Version1 = (u8 *) InstancePtr;
+	u8 *Version2 = (u8 *) VersionPtr;
+	int Index;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(VersionPtr != NULL);
+
+	/* check each byte of the versions to see if they are the same,
+	 * return at any point a byte differs between them
+	 */
+	for (Index = 0; Index < sizeof (XVersion); Index++) {
+		if (Version1[Index] != Version2[Index]) {
+			return FALSE;
+		}
+	}
+
+	/* No byte was found to be different between the versions, so indicate
+	 * the versions are equal
+	 */
+	return TRUE;
+}
+
+/*****************************************************************************
+*
+* Converts a version to a null terminated string.
+*
+* @param    InstancePtr points to the version to convert.
+* @param    StringPtr points to the string which will be the result of the
+*           conversion. This does not need to point to a null terminated
+*           string as an input, but must point to storage which is an adequate
+*           amount to hold the result string.
+*
+* @return
+*
+* The null terminated string is inserted at the location pointed to by
+* StringPtr if the status indicates success.
+*
+* @note
+*
+* It is necessary for the caller to have already allocated the storage to
+* contain the string.  The amount of memory necessary for the string is
+* specified in the version header file.
+*
+******************************************************************************/
+void
+XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(StringPtr != NULL);
+
+	/* since version is implemented as a string, just copy the specified
+	 * input into the specified output
+	 */
+	XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
+}
+
+/*****************************************************************************
+*
+* Initializes a version from a null terminated string. Since the string may not
+* be a format which is compatible with the version, an error could occur.
+*
+* @param    InstancePtr points to the version which is to be initialized.
+* @param    StringPtr points to a null terminated string which will be
+*           converted to a version.  The format of the string must match the
+*           version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
+*           Z = a - z.
+*
+* @return
+*
+* A status, XST_SUCCESS, indicating the conversion was accomplished
+* successfully, or XST_INVALID_VERSION indicating the version string format
+* was not valid.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(StringPtr != NULL);
+
+	/* if the version string specified is not valid, return an error */
+
+	if (!IsVersionStringValid(StringPtr)) {
+		return XST_INVALID_VERSION;
+	}
+
+	/* copy the specified string into the specified version and indicate the
+	 * conversion was successful
+	 */
+	XVersion_Copy((XVersion *) StringPtr, InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************
+*
+* Copies the contents of a version to another version.
+*
+* @param    InstancePtr points to the version which is the source of data for
+*           the copy operation.
+* @param    VersionPtr points to another version which is the destination of
+*           the copy operation.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr)
+{
+	u8 *Source = (u8 *) InstancePtr;
+	u8 *Destination = (u8 *) VersionPtr;
+	int Index;
+
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(VersionPtr != NULL);
+
+	/* copy each byte of the source version to the destination version */
+
+	for (Index = 0; Index < sizeof (XVersion); Index++) {
+		Destination[Index] = Source[Index];
+	}
+}
+
+/*****************************************************************************
+*
+* Determines if the specified version is valid.
+*
+* @param    StringPtr points to the string to be validated.
+*
+* @return
+*
+* TRUE if the version string is a valid format, FALSE otherwise.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static u32
+IsVersionStringValid(s8 * StringPtr)
+{
+	/* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
+	 * YY = 00 - 99, and Z = a - z, then indicate it's not valid
+	 */
+	if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
+	    (StringPtr[XVE_MAJOR_CHAR] > '9') ||
+	    (StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
+	    (StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
+	    (StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
+	    (StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
+	    (StringPtr[XVE_COMP_CHAR] < 'a') ||
+	    (StringPtr[XVE_COMP_CHAR] > 'z')) {
+		return FALSE;
+	}
+
+	return TRUE;
+}
diff --git a/u-boot/board/xilinx/common/xversion.h b/u-boot/board/xilinx/common/xversion.h
new file mode 100644
index 0000000..17f9da7
--- /dev/null
+++ b/u-boot/board/xilinx/common/xversion.h
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* This file contains the interface for the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XVERSION_H		/* prevent circular inclusions */
+#define XVERSION_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+typedef s8 XVersion[6];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion);
+
+XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion);
+
+u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr);
+
+void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr);
+
+XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr);
+
+void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/microblaze-generic/Makefile b/u-boot/board/xilinx/microblaze-generic/Makefile
new file mode 100644
index 0000000..efe64d8
--- /dev/null
+++ b/u-boot/board/xilinx/microblaze-generic/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $^)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xilinx/microblaze-generic/config.mk b/u-boot/board/xilinx/microblaze-generic/config.mk
new file mode 100644
index 0000000..f8d7e26
--- /dev/null
+++ b/u-boot/board/xilinx/microblaze-generic/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2007 Michal Simek
+#
+# Michal  SIMEK <monstr@monstr.eu>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# CAUTION: This file is automatically generated by libgen.
+# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
+#
+
+CONFIG_SYS_TEXT_BASE = 0x29000000
+
+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mxl-barrel-shift
diff --git a/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c b/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c
new file mode 100644
index 0000000..183e4dc
--- /dev/null
+++ b/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+
+#include <common.h>
+#include <config.h>
+#include <netdev.h>
+#include <asm/microblaze_intc.h>
+#include <asm/asm.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_SYS_GPIO_0
+	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
+	    ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
+#endif
+#ifdef CONFIG_SYS_RESET_ADDRESS
+	puts ("Reseting board\n");
+	asm ("bra r0");
+#endif
+	return 0;
+}
+
+int gpio_init (void)
+{
+#ifdef CONFIG_SYS_GPIO_0
+	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF;
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_SYS_FSL_2
+void fsl_isr2 (void *arg) {
+	volatile int num;
+	*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) =
+	    ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)));
+	GET (num, 2);
+	NGET (num, 2);
+	puts("*");
+}
+
+int fsl_init2 (void) {
+	puts("fsl_init2\n");
+	install_interrupt_handler (FSL_INTR_2, fsl_isr2, NULL);
+	return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	/*
+	 * This board either has PCI NICs or uses the CPU's TSECs
+	 * pci_eth_init() will return 0 if no NICs found, so in that case
+	 * returning -1 will force cpu_eth_init() to be called.
+	 */
+#ifdef CONFIG_XILINX_EMACLITE
+	return xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR);
+#endif
+}
diff --git a/u-boot/board/xilinx/microblaze-generic/u-boot.lds b/u-boot/board/xilinx/microblaze-generic/u-boot.lds
new file mode 100644
index 0000000..ee41145
--- /dev/null
+++ b/u-boot/board/xilinx/microblaze-generic/u-boot.lds
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		arch/microblaze/cpu/start.o (.text)
+		*(.text)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		__data_end = .;
+	}
+
+	.u_boot_cmd ALIGN(0x4):
+	{
+		. = .;
+		__u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		__u_boot_cmd_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.sbss)
+		*(.scommon)
+		*(.bss)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+	__end = . ;
+}
diff --git a/u-boot/board/xilinx/microblaze-generic/xparameters.h b/u-boot/board/xilinx/microblaze-generic/xparameters.h
new file mode 100644
index 0000000..fae03bf
--- /dev/null
+++ b/u-boot/board/xilinx/microblaze-generic/xparameters.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * CAUTION: This file is automatically generated by libgen.
+ * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
+ */
+
+#define XILINX_BOARD_NAME	microblaze-generic
+
+/* System Clock Frequency */
+#define XILINX_CLOCK_FREQ	100000000
+
+/* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR	1
+#define XILINX_FSL_NUMBER	3
+
+/* Interrupt controller is opb_intc_0 */
+#define XILINX_INTC_BASEADDR	0x41200000
+#define XILINX_INTC_NUM_INTR_INPUTS	6
+
+/* Timer pheriphery is opb_timer_1 */
+#define XILINX_TIMER_BASEADDR	0x41c00000
+#define XILINX_TIMER_IRQ	0
+
+/* Uart pheriphery is RS232_Uart */
+#define XILINX_UARTLITE_BASEADDR	0x40600000
+#define XILINX_UARTLITE_BAUDRATE	115200
+
+/* IIC pheriphery is IIC_EEPROM */
+#define XILINX_IIC_0_BASEADDR	0x40800000
+#define XILINX_IIC_0_FREQ	100000
+#define XILINX_IIC_0_BIT	0
+
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR	0x40000000
+
+/* Flash Memory is FLASH_2Mx32 */
+#define XILINX_FLASH_START	0x2c000000
+#define XILINX_FLASH_SIZE	0x00800000
+
+/* Main Memory is DDR_SDRAM_64Mx32 */
+#define XILINX_RAM_START	0x28000000
+#define XILINX_RAM_SIZE	0x04000000
+
+/* Sysace Controller is SysACE_CompactFlash */
+#define XILINX_SYSACE_BASEADDR	0x41800000
+#define XILINX_SYSACE_HIGHADDR	0x4180ffff
+#define XILINX_SYSACE_MEM_WIDTH	16
+
+/* Ethernet controller is Ethernet_MAC */
+#define XILINX_EMACLITE_BASEADDR       0x40C00000
diff --git a/u-boot/board/xilinx/ml507/.gitignore b/u-boot/board/xilinx/ml507/.gitignore
new file mode 100644
index 0000000..f6418a0
--- /dev/null
+++ b/u-boot/board/xilinx/ml507/.gitignore
@@ -0,0 +1 @@
+/config.tmp
diff --git a/u-boot/board/xilinx/ml507/Makefile b/u-boot/board/xilinx/ml507/Makefile
new file mode 100644
index 0000000..de23f29
--- /dev/null
+++ b/u-boot/board/xilinx/ml507/Makefile
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+COBJS	+= $(BOARD).o
+
+include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile
diff --git a/u-boot/board/xilinx/ml507/config.mk b/u-boot/board/xilinx/ml507/config.mk
new file mode 100644
index 0000000..4df1d9c
--- /dev/null
+++ b/u-boot/board/xilinx/ml507/config.mk
@@ -0,0 +1,4 @@
+# need to strip off double quotes
+ifneq ($(CONFIG_SYS_LDSCRIPT),)
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
diff --git a/u-boot/board/xilinx/ml507/ml507.c b/u-boot/board/xilinx/ml507/ml507.c
new file mode 100644
index 0000000..f9789cf
--- /dev/null
+++ b/u-boot/board/xilinx/ml507/ml507.c
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+
+int checkboard(void)
+{
+	puts("Xilinx ML507 Board\n");
+	return 0;
+}
diff --git a/u-boot/board/xilinx/ml507/xparameters.h b/u-boot/board/xilinx/ml507/xparameters.h
new file mode 100644
index 0000000..1992fff
--- /dev/null
+++ b/u-boot/board/xilinx/ml507/xparameters.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
+#define XPAR_INTC_0_BASEADDR		0x81800000
+#define XPAR_UARTLITE_0_BASEADDR	0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
+#define XPAR_UARTLITE_0_BAUDRATE	9600
+
+#endif
diff --git a/u-boot/board/xilinx/ppc405-generic/.gitignore b/u-boot/board/xilinx/ppc405-generic/.gitignore
new file mode 100644
index 0000000..b644f59
--- /dev/null
+++ b/u-boot/board/xilinx/ppc405-generic/.gitignore
@@ -0,0 +1 @@
+config.tmp
diff --git a/u-boot/board/xilinx/ppc405-generic/Makefile b/u-boot/board/xilinx/ppc405-generic/Makefile
new file mode 100644
index 0000000..501fd46
--- /dev/null
+++ b/u-boot/board/xilinx/ppc405-generic/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../xilinx/ppc405-generic)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xilinx/ppc405-generic/config.mk b/u-boot/board/xilinx/ppc405-generic/config.mk
new file mode 100644
index 0000000..4df1d9c
--- /dev/null
+++ b/u-boot/board/xilinx/ppc405-generic/config.mk
@@ -0,0 +1,4 @@
+# need to strip off double quotes
+ifneq ($(CONFIG_SYS_LDSCRIPT),)
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
diff --git a/u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
new file mode 100644
index 0000000..9bd1770
--- /dev/null
+++ b/u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+ulong __get_PCI_freq(void)
+{
+	return 0;
+}
+
+ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
+
+int __board_pre_init(void)
+{
+	return 0;
+}
+int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
+
+int __checkboard(void)
+{
+	puts("Xilinx PPC405 Generic Board\n");
+	return 0;
+}
+int checkboard(void) __attribute__((weak, alias("__checkboard")));
+
+phys_size_t __initdram(int board_type)
+{
+	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
+
+void __get_sys_info(sys_info_t *sysInfo)
+{
+	sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sysInfo->freqPCI = 0;
+
+	return;
+}
+void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
diff --git a/u-boot/board/xilinx/ppc405-generic/xparameters.h b/u-boot/board/xilinx/ppc405-generic/xparameters.h
new file mode 100644
index 0000000..e8e8ced
--- /dev/null
+++ b/u-boot/board/xilinx/ppc405-generic/xparameters.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
+#define XPAR_INTC_0_BASEADDR		0x81800000
+#define XPAR_SPI_0_BASEADDR             0x83400000
+#define XPAR_UARTLITE_0_BASEADDR	0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
+#define XPAR_UARTLITE_0_BAUDRATE	9600
+#define XPAR_SPI_0_NUM_TRANSFER_BITS	8
+
+#endif
diff --git a/u-boot/board/xilinx/ppc440-generic/.gitignore b/u-boot/board/xilinx/ppc440-generic/.gitignore
new file mode 100644
index 0000000..f6418a0
--- /dev/null
+++ b/u-boot/board/xilinx/ppc440-generic/.gitignore
@@ -0,0 +1 @@
+/config.tmp
diff --git a/u-boot/board/xilinx/ppc440-generic/Makefile b/u-boot/board/xilinx/ppc440-generic/Makefile
new file mode 100644
index 0000000..ed2cf9f
--- /dev/null
+++ b/u-boot/board/xilinx/ppc440-generic/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../xilinx/ppc440-generic)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
+SOBJS 	+= ../../xilinx/ppc440-generic/init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xilinx/ppc440-generic/config.mk b/u-boot/board/xilinx/ppc440-generic/config.mk
new file mode 100644
index 0000000..4df1d9c
--- /dev/null
+++ b/u-boot/board/xilinx/ppc440-generic/config.mk
@@ -0,0 +1,4 @@
+# need to strip off double quotes
+ifneq ($(CONFIG_SYS_LDSCRIPT),)
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
diff --git a/u-boot/board/xilinx/ppc440-generic/init.S b/u-boot/board/xilinx/ppc440-generic/init.S
new file mode 100644
index 0000000..54f2d7f
--- /dev/null
+++ b/u-boot/board/xilinx/ppc440-generic/init.S
@@ -0,0 +1,45 @@
+/*
+ *  (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+.section .bootpg,"ax"
+.globl tlbtab
+
+tlbtab:
+tlbtab_start
+tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbtab_end
diff --git a/u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
new file mode 100644
index 0000000..0c3d667
--- /dev/null
+++ b/u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int __board_pre_init(void)
+{
+	return 0;
+}
+int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
+
+int __checkboard(void)
+{
+	puts("Xilinx PPC440 Generic Board\n");
+	return 0;
+}
+int checkboard(void) __attribute__((weak, alias("__checkboard")));
+
+phys_size_t __initdram(int board_type)
+{
+	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
+
+void __get_sys_info(sys_info_t *sysInfo)
+{
+	sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sysInfo->freqPCI = 0;
+
+	return;
+}
+void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
diff --git a/u-boot/board/xilinx/ppc440-generic/xparameters.h b/u-boot/board/xilinx/ppc440-generic/xparameters.h
new file mode 100644
index 0000000..1992fff
--- /dev/null
+++ b/u-boot/board/xilinx/ppc440-generic/xparameters.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
+#define XPAR_INTC_0_BASEADDR		0x81800000
+#define XPAR_UARTLITE_0_BASEADDR	0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
+#define XPAR_UARTLITE_0_BAUDRATE	9600
+
+#endif
diff --git a/u-boot/board/xilinx/xilinx_enet/emac_adapter.c b/u-boot/board/xilinx/xilinx_enet/emac_adapter.c
new file mode 100644
index 0000000..35bcc4d
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/emac_adapter.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include "xemac.h"
+
+#if defined(XPAR_EMAC_0_DEVICE_ID)
+/*
+ * ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
+ * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
+ */
+
+#define ENET_MAX_MTU           PKTSIZE
+#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
+#define ENET_ADDR_LENGTH       6
+
+static XEmac Emac;
+static char etherrxbuff[PKTSIZE_ALIGN];	/* Receive buffer */
+
+/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
+#ifdef CONFIG_ENV_IS_NOWHERE
+static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+#endif
+
+static int initialized = 0;
+
+void
+eth_halt(void)
+{
+	if (initialized)
+		(void) XEmac_Stop(&Emac);
+}
+
+int
+eth_init(bd_t * bis)
+{
+	u32 Options;
+	XStatus Result;
+	uchar enetaddr[6];
+
+#ifdef DEBUG
+	printf("EMAC Initialization Started\n\r");
+#endif
+
+	Result = XEmac_Initialize(&Emac, XPAR_EMAC_0_DEVICE_ID);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+
+	/* make sure the Emac is stopped before it is started */
+	(void) XEmac_Stop(&Emac);
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+#ifdef CONFIG_ENV_IS_NOWHERE
+		memcpy(enetaddr, EMACAddr, 6);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+#endif
+	}
+
+	Result = XEmac_SetMacAddress(&Emac, enetaddr);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+
+	Options =
+	    (XEM_POLLED_OPTION | XEM_UNICAST_OPTION | XEM_BROADCAST_OPTION |
+	     XEM_FDUPLEX_OPTION | XEM_INSERT_FCS_OPTION |
+	     XEM_INSERT_PAD_OPTION);
+	Result = XEmac_SetOptions(&Emac, Options);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+
+	Result = XEmac_Start(&Emac);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+#ifdef DEBUG
+	printf("EMAC Initialization complete\n\r");
+#endif
+
+	initialized = 1;
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------------+
++-----------------------------------------------------------------------------*/
+int
+eth_send(volatile void *ptr, int len)
+{
+	XStatus Result;
+
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	Result = XEmac_PollSend(&Emac, (u8 *) ptr, len);
+	if (Result == XST_SUCCESS) {
+		return (1);
+	} else {
+		printf("Error while sending frame\n\r");
+		return (0);
+	}
+
+}
+
+int
+eth_rx(void)
+{
+	u32 RecvFrameLength;
+	XStatus Result;
+
+	RecvFrameLength = PKTSIZE;
+	Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
+	if (Result == XST_SUCCESS) {
+#ifndef CONFIG_EMACLITE
+		NetReceive((uchar *)etherrxbuff, RecvFrameLength);
+#else
+		NetReceive(etherrxbuff, RecvFrameLength);
+#endif
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+#endif
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac.c b/u-boot/board/xilinx/xilinx_enet/xemac.c
new file mode 100644
index 0000000..48b4ede
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac.c
@@ -0,0 +1,844 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac.c
+*
+* The XEmac driver. Functions in this file are the minimum required functions
+* for this driver. See xemac.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  07/23/02 Removed the PHY reset from Initialize()
+* 1.00b rmm  09/23/02 Removed commented code in Initialize(). Recycled as
+*                     XEmac_mPhyReset macro in xemac_l.h.
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* 1.00c rpm  12/12/02 Changed location of IsStarted assignment in XEmac_Start
+*                     to be sure the flag is set before the device and
+*                     interrupts are enabled.
+* 1.00c rpm  02/03/03 SelfTest was not clearing polled mode. Take driver out
+*                     of polled mode in XEmac_Reset() to fix this problem.
+* 1.00c rmm  05/13/03 Fixed diab compiler warnings relating to asserts.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static XStatus ConfigureDma(XEmac * InstancePtr);
+static XStatus ConfigureFifo(XEmac * InstancePtr);
+static void StubFifoHandler(void *CallBackRef);
+static void StubErrorHandler(void *CallBackRef, XStatus ErrorCode);
+static void StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr,
+			  u32 NumBds);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Initialize a specific XEmac instance/driver.  The initialization entails:
+* - Initialize fields of the XEmac structure
+* - Clear the Ethernet statistics for this device
+* - Initialize the IPIF component with its register base address
+* - Configure the FIFO components with their register base addresses.
+* - If the device is configured with DMA, configure the DMA channel components
+*   with their register base addresses. At some later time, memory pools for
+*   the scatter-gather descriptor lists may be passed to the driver.
+* - Reset the Ethernet MAC
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param DeviceId is the unique id of the device controlled by this XEmac
+*        instance.  Passing in a device id associates the generic XEmac
+*        instance to a specific device, as chosen by the caller or application
+*        developer.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+* - XST_DEVICE_IS_STARTED if the device has already been started
+* - XST_DEVICE_NOT_FOUND if device configuration information was not found for
+*   a device with the supplied device ID.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId)
+{
+	XStatus Result;
+	XEmac_Config *ConfigPtr;	/* configuration information */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a status
+	 * indicating it is started.  This allows the user to stop the device
+	 * and reinitialize, but prevents a user from inadvertently initializing
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Lookup the device configuration in the temporary CROM table. Use this
+	 * configuration info down below when initializing this component.
+	 */
+	ConfigPtr = XEmac_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		return XST_DEVICE_NOT_FOUND;
+	}
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->IsReady = 0;
+	InstancePtr->IsStarted = 0;
+	InstancePtr->IpIfDmaConfig = ConfigPtr->IpIfDmaConfig;
+	InstancePtr->HasMii = ConfigPtr->HasMii;
+	InstancePtr->HasMulticastHash = FALSE;
+
+	/* Always default polled to false, let user configure this mode */
+	InstancePtr->IsPolled = FALSE;
+	InstancePtr->FifoRecvHandler = StubFifoHandler;
+	InstancePtr->FifoSendHandler = StubFifoHandler;
+	InstancePtr->ErrorHandler = StubErrorHandler;
+	InstancePtr->SgRecvHandler = StubSgHandler;
+	InstancePtr->SgSendHandler = StubSgHandler;
+
+	/*
+	 * Clear the statistics for this driver
+	 */
+	XEmac_mClearStruct((u8 *) & InstancePtr->Stats, sizeof (XEmac_Stats));
+
+	/*
+	 * Initialize the device register base addresses
+	 */
+	InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
+
+	/*
+	 * Configure the send and receive FIFOs in the MAC
+	 */
+	Result = ConfigureFifo(InstancePtr);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	/*
+	 * If the device is configured for DMA, configure the send and receive DMA
+	 * channels in the MAC.
+	 */
+	if (XEmac_mIsDma(InstancePtr)) {
+		Result = ConfigureDma(InstancePtr);
+		if (Result != XST_SUCCESS) {
+			return Result;
+		}
+	}
+
+	/*
+	 * Indicate the component is now ready to use. Note that this is done before
+	 * we reset the device and the PHY below, which may seem a bit odd. The
+	 * choice was made to move it here rather than remove the asserts in various
+	 * functions (e.g., Reset() and all functions that it calls).  Applications
+	 * that use multiple threads, one to initialize the XEmac driver and one
+	 * waiting on the IsReady condition could have a problem with this sequence.
+	 */
+	InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+	/*
+	 * Reset the MAC to get it into its initial state. It is expected that
+	 * device configuration by the user will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XEmac_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Start the Ethernet controller as follows:
+*   - If not in polled mode
+*       - Set the internal interrupt enable registers appropriately
+*       - Enable interrupts within the device itself. Note that connection of
+*         the driver's interrupt handler to the interrupt source (typically
+*         done using the interrupt controller component) is done by the higher
+*         layer software.
+*       - If the device is configured with scatter-gather DMA, start the DMA
+*         channels if the descriptor lists are not empty
+*   - Enable the transmitter
+*   - Enable the receiver
+*
+* The PHY is enabled after driver initialization. We assume the upper layer
+* software has configured it and the EMAC appropriately before this function
+* is called.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS if the device was started successfully
+* - XST_NO_CALLBACK if a callback function has not yet been registered using
+*   the SetxxxHandler function. This is required if in interrupt mode.
+* - XST_DEVICE_IS_STARTED if the device is already started
+* - XST_DMA_SG_NO_LIST if configured for scatter-gather DMA and a descriptor
+*   list has not yet been created for the send or receive channel.
+*
+* @note
+*
+* The driver tries to match the hardware configuration. So if the hardware
+* is configured with scatter-gather DMA, the driver expects to start the
+* scatter-gather channels and expects that the user has set up the buffer
+* descriptor lists already. If the user expects to use the driver in a mode
+* different than how the hardware is configured, the user should modify the
+* configuration table to reflect the mode to be used. Modifying the config
+* table is a workaround for now until we get some experience with how users
+* are intending to use the hardware in its different configurations. For
+* example, if the hardware is built with scatter-gather DMA but the user is
+* intending to use only simple DMA, the user either needs to modify the config
+* table as a workaround or rebuild the hardware with only simple DMA.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and SetOptions functions. So if one task might be setting device
+* options while another is trying to start the device, the user is required to
+* provide protection of this shared data (typically using a semaphore).
+*
+******************************************************************************/
+XStatus
+XEmac_Start(XEmac * InstancePtr)
+{
+	u32 ControlReg;
+	XStatus Result;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * If it is already started, return a status indicating so
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * If not polled, enable interrupts
+	 */
+	if (!InstancePtr->IsPolled) {
+		/*
+		 * Verify that the callbacks have been registered, then enable
+		 * interrupts
+		 */
+		if (XEmac_mIsSgDma(InstancePtr)) {
+			if ((InstancePtr->SgRecvHandler == StubSgHandler) ||
+			    (InstancePtr->SgSendHandler == StubSgHandler)) {
+				return XST_NO_CALLBACK;
+			}
+
+			/* Enable IPIF interrupts */
+			XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+					      XEM_IPIF_DMA_DFT_MASK |
+					      XIIF_V123B_ERROR_MASK);
+			XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress,
+					      XEM_EIR_DFT_SG_MASK);
+
+			/* Enable scatter-gather DMA interrupts */
+			XDmaChannel_SetIntrEnable(&InstancePtr->RecvChannel,
+						  XEM_DMA_SG_INTR_MASK);
+			XDmaChannel_SetIntrEnable(&InstancePtr->SendChannel,
+						  XEM_DMA_SG_INTR_MASK);
+		} else {
+			if ((InstancePtr->FifoRecvHandler == StubFifoHandler) ||
+			    (InstancePtr->FifoSendHandler == StubFifoHandler)) {
+				return XST_NO_CALLBACK;
+			}
+
+			/* Enable IPIF interrupts (used by simple DMA also) */
+			XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+					      XEM_IPIF_FIFO_DFT_MASK |
+					      XIIF_V123B_ERROR_MASK);
+			XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress,
+					      XEM_EIR_DFT_FIFO_MASK);
+		}
+
+		/* Enable the global IPIF interrupt output */
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+	}
+
+	/*
+	 * Indicate that the device is started before we enable the transmitter
+	 * or receiver. This needs to be done before because as soon as the
+	 * receiver is enabled we may get an interrupt, and there are functions
+	 * in the interrupt handling path that rely on the IsStarted flag.
+	 */
+	InstancePtr->IsStarted = XCOMPONENT_IS_STARTED;
+
+	/*
+	 * Enable the transmitter, and receiver (do a read/modify/write to preserve
+	 * current settings). There is no critical section here since this register
+	 * is not modified during interrupt context.
+	 */
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+	ControlReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
+	ControlReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+
+	XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
+
+	/*
+	 * If configured with scatter-gather DMA and not polled, restart the
+	 * DMA channels in case there are buffers ready to be sent or received into.
+	 * The DMA SgStart function uses data that can be modified during interrupt
+	 * context, so a critical section is required here.
+	 */
+	if ((XEmac_mIsSgDma(InstancePtr)) && (!InstancePtr->IsPolled)) {
+		XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+		/*
+		 * The only error we care about is if the list has not yet been
+		 * created, or on receive, if no buffer descriptors have been
+		 * added yet (the list is empty). Other errors are benign at this point.
+		 */
+		Result = XDmaChannel_SgStart(&InstancePtr->RecvChannel);
+		if ((Result == XST_DMA_SG_NO_LIST)
+		    || (Result == XST_DMA_SG_LIST_EMPTY)) {
+			XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+			return Result;
+		}
+
+		Result = XDmaChannel_SgStart(&InstancePtr->SendChannel);
+		if (Result == XST_DMA_SG_NO_LIST) {
+			XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+			return Result;
+		}
+
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Stop the Ethernet MAC as follows:
+*   - If the device is configured with scatter-gather DMA, stop the DMA
+*     channels (wait for acknowledgment of stop)
+*   - Disable the transmitter and receiver
+*   - Disable interrupts if not in polled mode (the higher layer software is
+*     responsible for disabling interrupts at the interrupt controller)
+*
+* The PHY is left enabled after a Stop is called.
+*
+* If the device is configured for scatter-gather DMA, the DMA engine stops at
+* the next buffer descriptor in its list. The remaining descriptors in the list
+* are not removed, so anything in the list will be transmitted or received when
+* the device is restarted. The side effect of doing this is that the last
+* buffer descriptor processed by the DMA engine before stopping may not be the
+* last descriptor in the Ethernet frame. So when the device is restarted, a
+* partial frame (i.e., a bad frame) may be transmitted/received. This is only a
+* concern if a frame can span multiple buffer descriptors, which is dependent
+* on the size of the network buffers.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS if the device was stopped successfully
+* - XST_DEVICE_IS_STOPPED if the device is already stopped
+*
+* @note
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and SetOptions functions. So if one task might be setting device
+* options while another is trying to start the device, the user is required to
+* provide protection of this shared data (typically using a semaphore).
+*
+******************************************************************************/
+XStatus
+XEmac_Stop(XEmac * InstancePtr)
+{
+	u32 ControlReg;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * If the device is already stopped, do nothing but return a status
+	 * indicating so
+	 */
+	if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STOPPED;
+	}
+
+	/*
+	 * If configured for scatter-gather DMA, stop the DMA channels. Ignore
+	 * the XST_DMA_SG_IS_STOPPED return code. There is a critical section
+	 * here between SgStart and SgStop, and SgStart can be called in interrupt
+	 * context, so disable interrupts while calling SgStop.
+	 */
+	if (XEmac_mIsSgDma(InstancePtr)) {
+		XBufDescriptor *BdTemp;	/* temporary descriptor pointer */
+
+		XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+		(void) XDmaChannel_SgStop(&InstancePtr->SendChannel, &BdTemp);
+		(void) XDmaChannel_SgStop(&InstancePtr->RecvChannel, &BdTemp);
+
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+	}
+
+	/*
+	 * Disable the transmitter and receiver. There is no critical section
+	 * here since this register is not modified during interrupt context.
+	 */
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+	ControlReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+	XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
+
+	/*
+	 * If not in polled mode, disable interrupts for IPIF (includes MAC and
+	 * DMAs)
+	 */
+	if (!InstancePtr->IsPolled) {
+		XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+	}
+
+	InstancePtr->IsStarted = 0;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Reset the Ethernet MAC. This is a graceful reset in that the device is stopped
+* first. Resets the DMA channels, the FIFOs, the transmitter, and the receiver.
+* The PHY is not reset. Any frames in the scatter-gather descriptor lists will
+* remain in the lists. The side effect of doing this is that after a reset and
+* following a restart of the device, frames that were in the list before the
+* reset may be transmitted or received. Reset must only be called after the
+* driver has been initialized.
+*
+* The driver is also taken out of polled mode if polled mode was set. The user
+* is responsbile for re-configuring the driver into polled mode after the
+* reset if desired.
+*
+* The configuration after this reset is as follows:
+*   - Half duplex
+*   - Disabled transmitter and receiver
+*   - Enabled PHY (the PHY is not reset)
+*   - MAC transmitter does pad insertion, FCS insertion, and source address
+*     overwrite.
+*   - MAC receiver does not strip padding or FCS
+*   - Interframe Gap as recommended by IEEE Std. 802.3 (96 bit times)
+*   - Unicast addressing enabled
+*   - Broadcast addressing enabled
+*   - Multicast addressing disabled (addresses are preserved)
+*   - Promiscuous addressing disabled
+*   - Default packet threshold and packet wait bound register values for
+*     scatter-gather DMA operation
+*   - MAC address of all zeros
+*   - Non-polled mode
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note that the PHY is not reset. PHY
+* control is left to the upper layer software. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required due to an internal error, the driver notifies the
+* upper layer software of this need through the ErrorHandler callback and
+* specific status codes.  The upper layer software is responsible for calling
+* this Reset function and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+* @internal
+*
+* The reset is accomplished by setting the IPIF reset register.  This takes
+* care of resetting all hardware blocks, including the MAC.
+*
+******************************************************************************/
+void
+XEmac_Reset(XEmac * InstancePtr)
+{
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Stop the device first
+	 */
+	(void) XEmac_Stop(InstancePtr);
+
+	/*
+	 * Take the driver out of polled mode
+	 */
+	InstancePtr->IsPolled = FALSE;
+
+	/*
+	 * Reset the entire IPIF at once.  If we choose someday to reset each
+	 * hardware block separately, the reset should occur in the direction of
+	 * data flow. For example, for the send direction the reset order is DMA
+	 * first, then FIFO, then the MAC transmitter.
+	 */
+	XIIF_V123B_RESET(InstancePtr->BaseAddress);
+
+	if (XEmac_mIsSgDma(InstancePtr)) {
+		/*
+		 * After reset, configure the scatter-gather DMA packet threshold and
+		 * packet wait bound registers to default values. Ignore the return
+		 * values of these functions since they only return error if the device
+		 * is not stopped.
+		 */
+		(void) XEmac_SetPktThreshold(InstancePtr, XEM_SEND,
+					     XEM_SGDMA_DFT_THRESHOLD);
+		(void) XEmac_SetPktThreshold(InstancePtr, XEM_RECV,
+					     XEM_SGDMA_DFT_THRESHOLD);
+		(void) XEmac_SetPktWaitBound(InstancePtr, XEM_SEND,
+					     XEM_SGDMA_DFT_WAITBOUND);
+		(void) XEmac_SetPktWaitBound(InstancePtr, XEM_RECV,
+					     XEM_SGDMA_DFT_WAITBOUND);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the MAC address for this driver/device.  The address is a 48-bit value.
+* The device must be stopped before calling this function.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param AddressPtr is a pointer to a 6-byte MAC address.
+*
+* @return
+*
+* - XST_SUCCESS if the MAC address was set successfully
+* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr)
+{
+	u32 MacAddr = 0;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(AddressPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * The device must be stopped before setting the MAC address
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Set the device station address high and low registers
+	 */
+	MacAddr = (AddressPtr[0] << 8) | AddressPtr[1];
+	XIo_Out32(InstancePtr->BaseAddress + XEM_SAH_OFFSET, MacAddr);
+
+	MacAddr = (AddressPtr[2] << 24) | (AddressPtr[3] << 16) |
+	    (AddressPtr[4] << 8) | AddressPtr[5];
+
+	XIo_Out32(InstancePtr->BaseAddress + XEM_SAL_OFFSET, MacAddr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the MAC address for this driver/device.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BufferPtr is an output parameter, and is a pointer to a buffer into
+*        which the current MAC address will be copied. The buffer must be at
+*        least 6 bytes.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr)
+{
+	u32 MacAddrHi;
+	u32 MacAddrLo;
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(BufferPtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	MacAddrHi = XIo_In32(InstancePtr->BaseAddress + XEM_SAH_OFFSET);
+	MacAddrLo = XIo_In32(InstancePtr->BaseAddress + XEM_SAL_OFFSET);
+
+	BufferPtr[0] = (u8) (MacAddrHi >> 8);
+	BufferPtr[1] = (u8) MacAddrHi;
+	BufferPtr[2] = (u8) (MacAddrLo >> 24);
+	BufferPtr[3] = (u8) (MacAddrLo >> 16);
+	BufferPtr[4] = (u8) (MacAddrLo >> 8);
+	BufferPtr[5] = (u8) MacAddrLo;
+}
+
+/******************************************************************************/
+/**
+*
+* Configure DMA capabilities.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS  if successful initialization of DMA
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static XStatus
+ConfigureDma(XEmac * InstancePtr)
+{
+	XStatus Result;
+
+	/*
+	 * Initialize the DMA channels with their base addresses. We assume
+	 * scatter-gather DMA is the only possible configuration. Descriptor space
+	 * will need to be set later by the upper layer.
+	 */
+	Result = XDmaChannel_Initialize(&InstancePtr->RecvChannel,
+					InstancePtr->BaseAddress +
+					XEM_DMA_RECV_OFFSET);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	Result = XDmaChannel_Initialize(&InstancePtr->SendChannel,
+					InstancePtr->BaseAddress +
+					XEM_DMA_SEND_OFFSET);
+
+	return Result;
+}
+
+/******************************************************************************/
+/**
+*
+* Configure the send and receive FIFO components with their base addresses
+* and interrupt masks.  Currently the base addresses are defined constants.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* XST_SUCCESS if successful initialization of the packet FIFOs
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static XStatus
+ConfigureFifo(XEmac * InstancePtr)
+{
+	XStatus Result;
+
+	/*
+	 * Return status from the packet FIFOs initialization is ignored since
+	 * they always return success.
+	 */
+	Result = XPacketFifoV100b_Initialize(&InstancePtr->RecvFifo,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_RXREG_OFFSET,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_RXDATA_OFFSET);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	Result = XPacketFifoV100b_Initialize(&InstancePtr->SendFifo,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_TXREG_OFFSET,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_TXDATA_OFFSET);
+	return Result;
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the scatter-gather send and recv callbacks. The stub
+* is here in case the upper layers forget to set the handlers.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param BdPtr is a pointer to the first buffer descriptor in a list
+* @param NumBds is the number of descriptors in the list.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, u32 NumBds)
+{
+	XASSERT_VOID_ALWAYS();
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the non-DMA send and recv callbacks.  The stub is here in
+* case the upper layers forget to set the handlers.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+StubFifoHandler(void *CallBackRef)
+{
+	XASSERT_VOID_ALWAYS();
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the asynchronous error callback.  The stub is here in
+* case the upper layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param ErrorCode is the Xilinx error code, indicating the cause of the error
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+StubErrorHandler(void *CallBackRef, XStatus ErrorCode)
+{
+	XASSERT_VOID_ALWAYS();
+}
+
+/*****************************************************************************/
+/**
+*
+* Lookup the device configuration based on the unique device ID.  The table
+* EmacConfigTable contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+*
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XEmac_Config *
+XEmac_LookupConfig(u16 DeviceId)
+{
+	XEmac_Config *CfgPtr = NULL;
+	int i;
+
+	for (i = 0; i < XPAR_XEMAC_NUM_INSTANCES; i++) {
+		if (XEmac_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmac_ConfigTable[i];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac.h b/u-boot/board/xilinx/xilinx_enet/xemac.h
new file mode 100644
index 0000000..584cb7a
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac.h
@@ -0,0 +1,673 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac.h
+*
+* The Xilinx Ethernet driver component.	 This component supports the Xilinx
+* Ethernet 10/100 MAC (EMAC).
+*
+* The Xilinx Ethernet 10/100 MAC supports the following features:
+*   - Simple and scatter-gather DMA operations, as well as simple memory
+*     mapped direct I/O interface (FIFOs).
+*   - Media Independent Interface (MII) for connection to external
+*     10/100 Mbps PHY transceivers.
+*   - MII management control reads and writes with MII PHYs
+*   - Independent internal transmit and receive FIFOs
+*   - CSMA/CD compliant operations for half-duplex modes
+*   - Programmable PHY reset signal
+*   - Unicast, broadcast, and promiscuous address filtering (no multicast yet)
+*   - Internal loopback
+*   - Automatic source address insertion or overwrite (programmable)
+*   - Automatic FCS insertion and stripping (programmable)
+*   - Automatic pad insertion and stripping (programmable)
+*   - Pause frame (flow control) detection in full-duplex mode
+*   - Programmable interframe gap
+*   - VLAN frame support.
+*   - Pause frame support
+*
+* The device driver supports all the features listed above.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the EMAC. The driver handles transmission and reception of
+* Ethernet frames, as well as configuration of the controller. It does not
+* handle protocol stack functionality such as Link Layer Control (LLC) or the
+* Address Resolution Protocol (ARP). The protocol stack that makes use of the
+* driver handles this functionality. This implies that the driver is simply a
+* pass-through mechanism between a protocol stack and the EMAC. A single device
+* driver can support multiple EMACs.
+*
+* The driver is designed for a zero-copy buffer scheme. That is, the driver will
+* not copy buffers. This avoids potential throughput bottlenecks within the
+* driver.
+*
+* Since the driver is a simple pass-through mechanism between a protocol stack
+* and the EMAC, no assembly or disassembly of Ethernet frames is done at the
+* driver-level. This assumes that the protocol stack passes a correctly
+* formatted Ethernet frame to the driver for transmission, and that the driver
+* does not validate the contents of an incoming frame
+*
+* <b>PHY Communication</b>
+*
+* The driver provides rudimentary read and write functions to allow the higher
+* layer software to access the PHY. The EMAC provides MII registers for the
+* driver to access. This management interface can be parameterized away in the
+* FPGA implementation process. If this is the case, the PHY read and write
+* functions of the driver return XST_NO_FEATURE.
+*
+* External loopback is usually supported at the PHY. It is up to the user to
+* turn external loopback on or off at the PHY. The driver simply provides pass-
+* through functions for configuring the PHY. The driver does not read, write,
+* or reset the PHY on its own. All control of the PHY must be done by the user.
+*
+* <b>Asynchronous Callbacks</b>
+*
+* The driver services interrupts and passes Ethernet frames to the higher layer
+* software through asynchronous callback functions. When using the driver
+* directly (i.e., not with the RTOS protocol stack), the higher layer
+* software must register its callback functions during initialization. The
+* driver requires callback functions for received frames, for confirmation of
+* transmitted frames, and for asynchronous errors.
+*
+* <b>Interrupts</b>
+*
+* The driver has no dependencies on the interrupt controller. The driver
+* provides two interrupt handlers.  XEmac_IntrHandlerDma() handles interrupts
+* when the EMAC is configured with scatter-gather DMA.	XEmac_IntrHandlerFifo()
+* handles interrupts when the EMAC is configured for direct FIFO I/O or simple
+* DMA.	Either of these routines can be connected to the system interrupt
+* controller by the user.
+*
+* <b>Interrupt Frequency</b>
+*
+* When the EMAC is configured with scatter-gather DMA, the frequency of
+* interrupts can be controlled with the interrupt coalescing features of the
+* scatter-gather DMA engine. The frequency of interrupts can be adjusted using
+* the driver API functions for setting the packet count threshold and the packet
+* wait bound values.
+*
+* The scatter-gather DMA engine only interrupts when the packet count threshold
+* is reached, instead of interrupting for each packet. A packet is a generic
+* term used by the scatter-gather DMA engine, and is equivalent to an Ethernet
+* frame in our case.
+*
+* The packet wait bound is a timer value used during interrupt coalescing to
+* trigger an interrupt when not enough packets have been received to reach the
+* packet count threshold.
+*
+* These values can be tuned by the user to meet their needs. If there appear to
+* be interrupt latency problems or delays in packet arrival that are longer than
+* might be expected, the user should verify that the packet count threshold is
+* set low enough to receive interrupts before the wait bound timer goes off.
+*
+* <b>Device Reset</b>
+*
+* Some errors that can occur in the device require a device reset. These errors
+* are listed in the XEmac_SetErrorHandler() function header. The user's error
+* handler is responsible for resetting the device and re-configuring it based on
+* its needs (the driver does not save the current configuration). When
+* integrating into an RTOS, these reset and re-configure obligations are
+* taken care of by the Xilinx adapter software if it exists for that RTOS.
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process.  Configuration parameters are stored in the xemac_g.c files.
+* A table is defined where each entry contains configuration information
+* for an EMAC device.  This information includes such things as the base address
+* of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules
+* within the device, and whether the device has DMA, counter registers,
+* multicast support, MII support, and flow control.
+*
+* The driver tries to use the features built into the device. So if, for
+* example, the hardware is configured with scatter-gather DMA, the driver
+* expects to start the scatter-gather channels and expects that the user has set
+* up the buffer descriptor lists already. If the user expects to use the driver
+* in a mode different than how the hardware is configured, the user should
+* modify the configuration table to reflect the mode to be used. Modifying the
+* configuration table is a workaround for now until we get some experience with
+* how users are intending to use the hardware in its different configurations.
+* For example, if the hardware is built with scatter-gather DMA but the user is
+* intending to use only simple DMA, the user either needs to modify the config
+* table as a workaround or rebuild the hardware with only simple DMA. The
+* recommendation at this point is to build the hardware with the features you
+* intend to use. If you're inclined to modify the table, do so before the call
+* to XEmac_Initialize().  Here is a snippet of code that changes a device to
+* simple DMA (the hardware needs to have DMA for this to work of course):
+* <pre>
+*	 XEmac_Config *ConfigPtr;
+*
+*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
+*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
+* </pre>
+*
+* <b>Simple DMA</b>
+*
+* Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of
+* the driver (i.e., there is no separate interface for it). The driver makes use
+* of the DMA engine for a simple DMA transfer if the device is configured with
+* DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is
+* therefore transparent to the user, the caching of network buffers is not.
+* If the device is configured with DMA and the FIFO interface is used, the user
+* must ensure that the network buffers are not cached or are cache coherent,
+* since DMA will be used to transfer to and from the Emac device. If the device
+* is configured with DMA and the user really wants to use the FIFOs directly,
+* the user should rebuild the hardware without DMA. If unable to do this, there
+* is a workaround (described above in Device Configuration) to modify the
+* configuration table of the driver to fake the driver into thinking the device
+* has no DMA. A code snippet follows:
+* <pre>
+*	 XEmac_Config *ConfigPtr;
+*
+*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
+*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
+* </pre>
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XEmac driver is composed of several source files. Why so many?  This
+* allows the user to build and link only those parts of the driver that are
+* necessary. Since the EMAC hardware can be configured in various ways (e.g.,
+* with or without DMA), the driver too can be built with varying features.
+* For the most part, this means that besides always linking in xemac.c, you
+* link in only the driver functionality you want. Some of the choices you have
+* are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA,
+* self-test diagnostics, and driver statistics. Note that currently the DMA code
+* must be linked in, even if you don't have DMA in the device.
+*
+* @note
+*
+* Xilinx drivers are typically composed of two components, one is the driver
+* and the other is the adapter.	 The driver is independent of OS and processor
+* and is intended to be highly portable.  The adapter is OS-specific and
+* facilitates communication between the driver and an OS.
+* <br><br>
+* This driver is intended to be RTOS and processor independent.	 It works
+* with physical addresses only.	 Any needs for dynamic memory management,
+* threads or thread mutual exclusion, virtual memory, or cache control must
+* be satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
+*		      configuration parameter
+* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
+*		      argument to SgSend
+* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
+*		      from SetPktThreshold in the internal DMA driver. Also
+*		      avoided compiler warnings by initializing Result in the
+*		      DMA interrupt service routines.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_H			/* prevent circular inclusions */
+#define XEMAC_H			/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include <config.h>
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xpacket_fifo_v1_00_b.h"	/* Uses v1.00b of Packet Fifo */
+#include "xdma_channel.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Device information
+ */
+#define XEM_DEVICE_NAME	    "xemac"
+#define XEM_DEVICE_DESC	    "Xilinx Ethernet 10/100 MAC"
+
+/** @name Configuration options
+ *
+ * Device configuration options (see the XEmac_SetOptions() and
+ * XEmac_GetOptions() for information on how to use these options)
+ * @{
+ */
+/**
+ * <pre>
+ *   XEM_BROADCAST_OPTION	 Broadcast addressing on or off (default is on)
+ *   XEM_UNICAST_OPTION		 Unicast addressing on or off (default is on)
+ *   XEM_PROMISC_OPTION		 Promiscuous addressing on or off (default is off)
+ *   XEM_FDUPLEX_OPTION		 Full duplex on or off (default is off)
+ *   XEM_POLLED_OPTION		 Polled mode on or off (default is off)
+ *   XEM_LOOPBACK_OPTION	 Internal loopback on or off (default is off)
+ *   XEM_FLOW_CONTROL_OPTION	 Interpret pause frames in full duplex mode
+ *				 (default is off)
+ *   XEM_INSERT_PAD_OPTION	 Pad short frames on transmit (default is on)
+ *   XEM_INSERT_FCS_OPTION	 Insert FCS (CRC) on transmit (default is on)
+ *   XEM_INSERT_ADDR_OPTION	 Insert source address on transmit (default is on)
+ *   XEM_OVWRT_ADDR_OPTION	 Overwrite source address on transmit. This is
+ *				 only used if source address insertion is on.
+ *				 (default is on)
+ *   XEM_STRIP_PAD_FCS_OPTION	 Strip FCS and padding from received frames
+ *				 (default is off)
+  * </pre>
+ */
+#define XEM_UNICAST_OPTION	  0x00000001UL
+#define XEM_BROADCAST_OPTION	  0x00000002UL
+#define XEM_PROMISC_OPTION	  0x00000004UL
+#define XEM_FDUPLEX_OPTION	  0x00000008UL
+#define XEM_POLLED_OPTION	  0x00000010UL
+#define XEM_LOOPBACK_OPTION	  0x00000020UL
+#define XEM_FLOW_CONTROL_OPTION	  0x00000080UL
+#define XEM_INSERT_PAD_OPTION	  0x00000100UL
+#define XEM_INSERT_FCS_OPTION	  0x00000200UL
+#define XEM_INSERT_ADDR_OPTION	  0x00000400UL
+#define XEM_OVWRT_ADDR_OPTION	  0x00000800UL
+#define XEM_STRIP_PAD_FCS_OPTION  0x00002000UL
+/*@}*/
+/*
+ * Not supported yet:
+ *   XEM_MULTICAST_OPTION	 Multicast addressing on or off (default is off)
+ */
+/* NOT SUPPORTED YET... */
+#define XEM_MULTICAST_OPTION	  0x00000040UL
+
+/*
+ * Some default values for interrupt coalescing within the scatter-gather
+ * DMA engine.
+ */
+#define XEM_SGDMA_DFT_THRESHOLD	    1	/* Default pkt threshold */
+#define XEM_SGDMA_MAX_THRESHOLD	    255 /* Maximum pkt theshold */
+#define XEM_SGDMA_DFT_WAITBOUND	    5	/* Default pkt wait bound (msec) */
+#define XEM_SGDMA_MAX_WAITBOUND	    1023	/* Maximum pkt wait bound (msec) */
+
+/*
+ * Direction identifiers. These are used for setting values like packet
+ * thresholds and wait bound for specific channels
+ */
+#define XEM_SEND    1
+#define XEM_RECV    2
+
+/*
+ * Arguments to SgSend function to indicate whether to hold off starting
+ * the scatter-gather engine.
+ */
+#define XEM_SGDMA_NODELAY     0 /* start SG DMA immediately */
+#define XEM_SGDMA_DELAY	      1 /* do not start SG DMA */
+
+/*
+ * Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEM_CFG_NO_IPIF		    0	/* Not supported by the driver */
+#define XEM_CFG_NO_DMA		    1	/* No DMA */
+#define XEM_CFG_SIMPLE_DMA	    2	/* Simple DMA */
+#define XEM_CFG_DMA_SG		    3	/* DMA scatter gather */
+
+/*
+ * The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEM_MAC_ADDR_SIZE   6	/* six-byte MAC address */
+#define XEM_MTU		    1500	/* max size of Ethernet frame */
+#define XEM_HDR_SIZE	    14	/* size of Ethernet header */
+#define XEM_HDR_VLAN_SIZE   18	/* size of Ethernet header with VLAN */
+#define XEM_TRL_SIZE	    4	/* size of Ethernet trailer (FCS) */
+#define XEM_MAX_FRAME_SIZE  (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE)
+#define XEM_MAX_VLAN_FRAME_SIZE	 (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE)
+
+/*
+ * Define a default number of send and receive buffers
+ */
+#define XEM_MIN_RECV_BUFS   32	/* minimum # of recv buffers */
+#define XEM_DFT_RECV_BUFS   64	/* default # of recv buffers */
+
+#define XEM_MIN_SEND_BUFS   16	/* minimum # of send buffers */
+#define XEM_DFT_SEND_BUFS   32	/* default # of send buffers */
+
+#define XEM_MIN_BUFFERS	    (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS)
+#define XEM_DFT_BUFFERS	    (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS)
+
+/*
+ * Define the number of send and receive buffer descriptors, used for
+ * scatter-gather DMA
+ */
+#define XEM_MIN_RECV_DESC   16	/* minimum # of recv descriptors */
+#define XEM_DFT_RECV_DESC   32	/* default # of recv descriptors */
+
+#define XEM_MIN_SEND_DESC   8	/* minimum # of send descriptors */
+#define XEM_DFT_SEND_DESC   16	/* default # of send descriptors */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats())
+ */
+typedef struct {
+	u32 XmitFrames;		 /**< Number of frames transmitted */
+	u32 XmitBytes;		 /**< Number of bytes transmitted */
+	u32 XmitLateCollisionErrors;
+				 /**< Number of transmission failures
+					  due to late collisions */
+	u32 XmitExcessDeferral;	 /**< Number of transmission failures
+					  due o excess collision deferrals */
+	u32 XmitOverrunErrors;	 /**< Number of transmit overrun errors */
+	u32 XmitUnderrunErrors;	 /**< Number of transmit underrun errors */
+	u32 RecvFrames;		 /**< Number of frames received */
+	u32 RecvBytes;		 /**< Number of bytes received */
+	u32 RecvFcsErrors;	 /**< Number of frames discarded due
+					  to FCS errors */
+	u32 RecvAlignmentErrors; /**< Number of frames received with
+					  alignment errors */
+	u32 RecvOverrunErrors;	 /**< Number of frames discarded due
+					  to overrun errors */
+	u32 RecvUnderrunErrors;	 /**< Number of recv underrun errors */
+	u32 RecvMissedFrameErrors;
+				 /**< Number of frames missed by MAC */
+	u32 RecvCollisionErrors; /**< Number of frames discarded due
+					  to collisions */
+	u32 RecvLengthFieldErrors;
+				 /**< Number of frames discarded with
+					  invalid length field */
+	u32 RecvShortErrors;	 /**< Number of short frames discarded */
+	u32 RecvLongErrors;	 /**< Number of long frames discarded */
+	u32 DmaErrors;		 /**< Number of DMA errors since init */
+	u32 FifoErrors;		 /**< Number of FIFO errors since init */
+	u32 RecvInterrupts;	 /**< Number of receive interrupts */
+	u32 XmitInterrupts;	 /**< Number of transmit interrupts */
+	u32 EmacInterrupts;	 /**< Number of MAC (device) interrupts */
+	u32 TotalIntrs;		 /**< Total interrupts */
+} XEmac_Stats;
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;	    /**< Unique ID  of device */
+	u32 BaseAddress;    /**< Register base address */
+	u32 HasCounters;   /**< Does device have counters? */
+	u8 IpIfDmaConfig;   /**< IPIF/DMA hardware configuration */
+	u32 HasMii;	   /**< Does device support MII? */
+
+} XEmac_Config;
+
+/** @name Typedefs for callbacks
+ * Callback functions.
+ * @{
+ */
+/**
+ * Callback when data is sent or received with scatter-gather DMA.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ *	  when setting the callback functions, and passed back to the upper
+ *	  layer when the callback is invoked.
+ * @param BdPtr is a pointer to the first buffer descriptor in a list of
+ *	  buffer descriptors.
+ * @param NumBds is the number of buffer descriptors in the list pointed
+ *	  to by BdPtr.
+ */
+typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr,
+				 u32 NumBds);
+
+/**
+ * Callback when data is sent or received with direct FIFO communication or
+ * simple DMA. The user typically defines two callacks, one for send and one
+ * for receive.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ *	  when setting the callback functions, and passed back to the upper
+ *	  layer when the callback is invoked.
+ */
+typedef void (*XEmac_FifoHandler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ *	  when setting the callback functions, and passed back to the upper
+ *	  layer when the callback is invoked.
+ * @param ErrorCode is a Xilinx error code defined in xstatus.h.  Also see
+ *	  XEmac_SetErrorHandler() for a description of possible errors.
+ */
+typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode);
+/*@}*/
+
+/**
+ * The XEmac driver instance data. The user is required to allocate a
+ * variable of this type for every EMAC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	u32 BaseAddress;	/* Base address (of IPIF) */
+	u32 IsStarted;		/* Device is currently started */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 IsPolled;		/* Device is in polled mode */
+	u8 IpIfDmaConfig;	/* IPIF/DMA hardware configuration */
+	u32 HasMii;		/* Does device support MII? */
+	u32 HasMulticastHash;	/* Does device support multicast hash table? */
+
+	XEmac_Stats Stats;
+	XPacketFifoV100b RecvFifo;	/* FIFO used to receive frames */
+	XPacketFifoV100b SendFifo;	/* FIFO used to send frames */
+
+	/*
+	 * Callbacks
+	 */
+	XEmac_FifoHandler FifoRecvHandler;	/* for non-DMA/simple DMA interrupts */
+	void *FifoRecvRef;
+	XEmac_FifoHandler FifoSendHandler;	/* for non-DMA/simple DMA interrupts */
+	void *FifoSendRef;
+	XEmac_ErrorHandler ErrorHandler;	/* for asynchronous errors */
+	void *ErrorRef;
+
+	XDmaChannel RecvChannel;	/* DMA receive channel driver */
+	XDmaChannel SendChannel;	/* DMA send channel driver */
+
+	XEmac_SgHandler SgRecvHandler;	/* callback for scatter-gather DMA */
+	void *SgRecvRef;
+	XEmac_SgHandler SgSendHandler;	/* callback for scatter-gather DMA */
+	void *SgSendRef;
+} XEmac;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured for
+* scatter-gather DMA.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE
+* if it is not.
+*
+* @note
+*
+* Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr)
+*
+******************************************************************************/
+#define XEmac_mIsSgDma(InstancePtr) \
+	    ((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG)
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured for simple DMA.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise
+*
+* @note
+*
+* Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr)
+*
+******************************************************************************/
+#define XEmac_mIsSimpleDma(InstancePtr) \
+	    ((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA)
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured with DMA (either
+* simple DMA or scatter-gather DMA)
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with DMA, or FALSE otherwise
+*
+* @note
+*
+* Signature: u32 XEmac_mIsDma(XEmac *InstancePtr)
+*
+******************************************************************************/
+#define XEmac_mIsDma(InstancePtr) \
+	    (XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xemac.c
+ */
+XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId);
+XStatus XEmac_Start(XEmac * InstancePtr);
+XStatus XEmac_Stop(XEmac * InstancePtr);
+void XEmac_Reset(XEmac * InstancePtr);
+XEmac_Config *XEmac_LookupConfig(u16 DeviceId);
+
+/*
+ * Diagnostic functions in xemac_selftest.c
+ */
+XStatus XEmac_SelfTest(XEmac * InstancePtr);
+
+/*
+ * Polled functions in xemac_polled.c
+ */
+XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
+XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
+
+/*
+ * Interrupts with scatter-gather DMA functions in xemac_intr_dma.c
+ */
+XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay);
+XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr);
+XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold);
+XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction,
+			      u8 * ThreshPtr);
+XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction,
+			      u32 TimerValue);
+XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction,
+			      u32 * WaitPtr);
+XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr,
+			     u32 ByteCount);
+XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr,
+			     u32 ByteCount);
+void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
+			    XEmac_SgHandler FuncPtr);
+void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
+			    XEmac_SgHandler FuncPtr);
+
+void XEmac_IntrHandlerDma(void *InstancePtr);	/* interrupt handler */
+
+/*
+ * Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used
+ * for simple DMA.
+ */
+XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
+XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
+void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef,
+			      XEmac_FifoHandler FuncPtr);
+void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef,
+			      XEmac_FifoHandler FuncPtr);
+
+void XEmac_IntrHandlerFifo(void *InstancePtr);	/* interrupt handler */
+
+/*
+ * General interrupt-related functions in xemac_intr.c
+ */
+void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
+			   XEmac_ErrorHandler FuncPtr);
+
+/*
+ * MAC configuration in xemac_options.c
+ */
+XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag);
+u32 XEmac_GetOptions(XEmac * InstancePtr);
+XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr);
+void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr);
+XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2);
+void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr);
+
+/*
+ * Multicast functions in xemac_multicast.c (not supported by EMAC yet)
+ */
+XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr);
+XStatus XEmac_MulticastClear(XEmac * InstancePtr);
+
+/*
+ * PHY configuration in xemac_phy.c
+ */
+XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 * PhyDataPtr);
+XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress,
+		       u32 RegisterNum, u16 PhyData);
+
+/*
+ * Statistics in xemac_stats.c
+ */
+void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr);
+void XEmac_ClearStats(XEmac * InstancePtr);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_g.c b/u-boot/board/xilinx/xilinx_enet/xemac_g.c
new file mode 100644
index 0000000..d985157
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_g.c
@@ -0,0 +1,60 @@
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 6.1.2 EDK_G.14
+* DO NOT EDIT.
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include <config.h>
+#include "xemac.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmac_Config XEmac_ConfigTable[] = {
+	{
+	 XPAR_OPB_ETHERNET_0_DEVICE_ID,
+	 XPAR_OPB_ETHERNET_0_BASEADDR,
+	 XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST,
+	 XPAR_OPB_ETHERNET_0_DMA_PRESENT,
+	 XPAR_OPB_ETHERNET_0_MII_EXIST}
+};
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_i.h b/u-boot/board/xilinx/xilinx_enet/xemac_i.h
new file mode 100644
index 0000000..9c160f3
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_i.h
@@ -0,0 +1,207 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_i.h
+*
+* This header file contains internal identifiers, which are those shared
+* between XEmac components.  The identifiers in this file are not intended for
+* use external to the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  04/29/02 Moved register definitions to xemac_l.h
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_I_H		/* prevent circular inclusions */
+#define XEMAC_I_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xemac.h"
+#include "xemac_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Default buffer descriptor control word masks. The default send BD control
+ * is set for incrementing the source address by one for each byte transferred,
+ * and specify that the destination address (FIFO) is local to the device. The
+ * default receive BD control is set for incrementing the destination address
+ * by one for each byte transferred, and specify that the source address is
+ * local to the device.
+ */
+#define XEM_DFT_SEND_BD_MASK	(XDC_DMACR_SOURCE_INCR_MASK | \
+				 XDC_DMACR_DEST_LOCAL_MASK)
+#define XEM_DFT_RECV_BD_MASK	(XDC_DMACR_DEST_INCR_MASK |  \
+				 XDC_DMACR_SOURCE_LOCAL_MASK)
+
+/*
+ * Masks for the IPIF Device Interrupt enable and status registers.
+ */
+#define XEM_IPIF_EMAC_MASK	0x00000004UL	/* MAC interrupt */
+#define XEM_IPIF_SEND_DMA_MASK	0x00000008UL	/* Send DMA interrupt */
+#define XEM_IPIF_RECV_DMA_MASK	0x00000010UL	/* Receive DMA interrupt */
+#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL	/* Receive FIFO interrupt */
+#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL	/* Send FIFO interrupt */
+
+/*
+ * Default IPIF Device Interrupt mask when configured for DMA
+ */
+#define XEM_IPIF_DMA_DFT_MASK	(XEM_IPIF_SEND_DMA_MASK |   \
+				 XEM_IPIF_RECV_DMA_MASK |   \
+				 XEM_IPIF_EMAC_MASK |	    \
+				 XEM_IPIF_SEND_FIFO_MASK |  \
+				 XEM_IPIF_RECV_FIFO_MASK)
+
+/*
+ * Default IPIF Device Interrupt mask when configured without DMA
+ */
+#define XEM_IPIF_FIFO_DFT_MASK	(XEM_IPIF_EMAC_MASK |	    \
+				 XEM_IPIF_SEND_FIFO_MASK |  \
+				 XEM_IPIF_RECV_FIFO_MASK)
+
+#define XEM_IPIF_DMA_DEV_INTR_COUNT   7 /* Number of interrupt sources */
+#define XEM_IPIF_FIFO_DEV_INTR_COUNT  5 /* Number of interrupt sources */
+#define XEM_IPIF_DEVICE_INTR_COUNT  7	/* Number of interrupt sources */
+#define XEM_IPIF_IP_INTR_COUNT	    22	/* Number of MAC interrupts */
+
+/* a mask for all transmit interrupts, used in polled mode */
+#define XEM_EIR_XMIT_ALL_MASK	(XEM_EIR_XMIT_DONE_MASK |	    \
+				 XEM_EIR_XMIT_ERROR_MASK |	    \
+				 XEM_EIR_XMIT_SFIFO_EMPTY_MASK |    \
+				 XEM_EIR_XMIT_LFIFO_FULL_MASK)
+
+/* a mask for all receive interrupts, used in polled mode */
+#define XEM_EIR_RECV_ALL_MASK	(XEM_EIR_RECV_DONE_MASK |	    \
+				 XEM_EIR_RECV_ERROR_MASK |	    \
+				 XEM_EIR_RECV_LFIFO_EMPTY_MASK |    \
+				 XEM_EIR_RECV_LFIFO_OVER_MASK |	    \
+				 XEM_EIR_RECV_LFIFO_UNDER_MASK |    \
+				 XEM_EIR_RECV_DFIFO_OVER_MASK |	    \
+				 XEM_EIR_RECV_MISSED_FRAME_MASK |   \
+				 XEM_EIR_RECV_COLLISION_MASK |	    \
+				 XEM_EIR_RECV_FCS_ERROR_MASK |	    \
+				 XEM_EIR_RECV_LEN_ERROR_MASK |	    \
+				 XEM_EIR_RECV_SHORT_ERROR_MASK |    \
+				 XEM_EIR_RECV_LONG_ERROR_MASK |	    \
+				 XEM_EIR_RECV_ALIGN_ERROR_MASK)
+
+/* a default interrupt mask for scatter-gather DMA operation */
+#define XEM_EIR_DFT_SG_MASK    (XEM_EIR_RECV_ERROR_MASK |	    \
+				XEM_EIR_RECV_LFIFO_OVER_MASK |	    \
+				XEM_EIR_RECV_LFIFO_UNDER_MASK |	    \
+				XEM_EIR_XMIT_SFIFO_OVER_MASK |	    \
+				XEM_EIR_XMIT_SFIFO_UNDER_MASK |	    \
+				XEM_EIR_XMIT_LFIFO_OVER_MASK |	    \
+				XEM_EIR_XMIT_LFIFO_UNDER_MASK |	    \
+				XEM_EIR_RECV_DFIFO_OVER_MASK |	    \
+				XEM_EIR_RECV_MISSED_FRAME_MASK |    \
+				XEM_EIR_RECV_COLLISION_MASK |	    \
+				XEM_EIR_RECV_FCS_ERROR_MASK |	    \
+				XEM_EIR_RECV_LEN_ERROR_MASK |	    \
+				XEM_EIR_RECV_SHORT_ERROR_MASK |	    \
+				XEM_EIR_RECV_LONG_ERROR_MASK |	    \
+				XEM_EIR_RECV_ALIGN_ERROR_MASK)
+
+/* a default interrupt mask for non-DMA operation (direct FIFOs) */
+#define XEM_EIR_DFT_FIFO_MASK  (XEM_EIR_XMIT_DONE_MASK |	    \
+				XEM_EIR_RECV_DONE_MASK |	    \
+				XEM_EIR_DFT_SG_MASK)
+
+/*
+ * Mask for the DMA interrupt enable and status registers when configured
+ * for scatter-gather DMA.
+ */
+#define XEM_DMA_SG_INTR_MASK	(XDC_IXR_DMA_ERROR_MASK	 |	\
+				 XDC_IXR_PKT_THRESHOLD_MASK |	\
+				 XDC_IXR_PKT_WAIT_BOUND_MASK |	\
+				 XDC_IXR_SG_END_MASK)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/*
+*
+* Clears a structure of given size, in bytes, by setting each byte to 0.
+*
+* @param StructPtr is a pointer to the structure to be cleared.
+* @param NumBytes is the number of bytes in the structure.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes)
+*
+******************************************************************************/
+#define XEmac_mClearStruct(StructPtr, NumBytes)	    \
+{						    \
+    int i;					    \
+    u8 *BytePtr = (u8 *)(StructPtr);	    \
+    for (i=0; i < (unsigned int)(NumBytes); i++)    \
+    {						    \
+	*BytePtr++ = 0;				    \
+    }						    \
+}
+
+/************************** Variable Definitions *****************************/
+
+extern XEmac_Config XEmac_ConfigTable[];
+
+/************************** Function Prototypes ******************************/
+
+void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus);
+void XEmac_CheckFifoRecvError(XEmac * InstancePtr);
+void XEmac_CheckFifoSendError(XEmac * InstancePtr);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_intr.c b/u-boot/board/xilinx/xilinx_enet/xemac_intr.c
new file mode 100644
index 0000000..b9a2621
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_intr.c
@@ -0,0 +1,402 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_intr.c
+*
+* This file contains general interrupt-related functions of the XEmac driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* 1.00c rpm  03/31/03 Added comment to indicate that no Receive Length FIFO
+*                     overrun interrupts occur in v1.00l and later of the EMAC
+*                     device. This avoids the need to reset the device on
+*                     receive overruns.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Set the callback function for handling asynchronous errors.  The upper layer
+* software should call this function during initialization.
+*
+* The error callback is invoked by the driver within interrupt context, so it
+* needs to do its job quickly. If there are potentially slow operations within
+* the callback, these should be done at task-level.
+*
+* The Xilinx errors that must be handled by the callback are:
+* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is
+*   typically a bus error or bus timeout. The handler must reset and
+*   re-configure the device.
+* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a
+*   deadlock condition in the packet FIFO. The handler must reset and
+*   re-configure the device.
+* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an
+*   overrun or underrun. The handler must reset and re-configure the device.
+* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather
+*   DMA list that has not yet been created.
+* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from
+*   the receive descriptor list, but the list was empty.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param CallBackRef is a reference pointer to be passed back to the adapter in
+*        the callback. This helps the adapter correlate the callback to a
+*        particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
+		      XEmac_ErrorHandler FuncPtr)
+{
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(FuncPtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	InstancePtr->ErrorHandler = FuncPtr;
+	InstancePtr->ErrorRef = CallBackRef;
+}
+
+/****************************************************************************/
+/*
+*
+* Check the interrupt status bits of the Ethernet MAC for errors. Errors
+* currently handled are:
+* - Receive length FIFO overrun. Indicates data was lost due to the receive
+*   length FIFO becoming full during the reception of a packet. Only a device
+*   reset clears this condition.
+* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
+*   device reset clears this condition.
+* - Transmit status FIFO overrun. Indicates data was lost due to the transmit
+*   status FIFO becoming full following the transmission of a packet. Only a
+*   device reset clears this condition.
+* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
+*   device reset clears this condition.
+* - Transmit length FIFO overrun. Indicates data was lost due to the transmit
+*   length FIFO becoming full following the transmission of a packet. Only a
+*   device reset clears this condition.
+* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
+*   device reset clears this condition.
+* - Receive data FIFO overrun. Indicates data was lost due to the receive data
+*   FIFO becoming full during the reception of a packet.
+* - Receive data errors:
+*   - Receive missed frame error. Valid data was lost by the MAC.
+*   - Receive collision error. Data was lost by the MAC due to a collision.
+*   - Receive FCS error.  Data was dicarded by the MAC due to FCS error.
+*   - Receive length field error. Data was dicarded by the MAC due to an invalid
+*     length field in the packet.
+*   - Receive short error. Data was dicarded by the MAC because a packet was
+*     shorter than allowed.
+*   - Receive long error. Data was dicarded by the MAC because a packet was
+*     longer than allowed.
+*   - Receive alignment error. Data was truncated by the MAC because its length
+*     was not byte-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param IntrStatus is the contents of the interrupt status register to be checked
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* This function is intended for internal use only.
+*
+******************************************************************************/
+void
+XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
+{
+	u32 ResetError = FALSE;
+
+	/*
+	 * First check for receive fifo overrun/underrun errors. Most require a
+	 * reset by the user to clear, but the data FIFO overrun error does not.
+	 */
+	if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
+		InstancePtr->Stats.RecvOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+	}
+
+	if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
+		/*
+		 * Receive Length FIFO overrun interrupts no longer occur in v1.00l
+		 * and later of the EMAC device. Frames are just dropped by the EMAC
+		 * if the length FIFO is full. The user would notice the Receive Missed
+		 * Frame count incrementing without any other errors being reported.
+		 * This code is left here for backward compatibility with v1.00k and
+		 * older EMAC devices.
+		 */
+		InstancePtr->Stats.RecvOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;	/* requires a reset */
+	}
+
+	if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
+		InstancePtr->Stats.RecvUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;	/* requires a reset */
+	}
+
+	/*
+	 * Now check for general receive errors. Get the latest count where
+	 * available, otherwise just bump the statistic so we know the interrupt
+	 * occurred.
+	 */
+	if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
+		if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
+			/*
+			 * Caused by length FIFO or data FIFO overruns on receive side
+			 */
+			InstancePtr->Stats.RecvMissedFrameErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RMFC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
+			InstancePtr->Stats.RecvCollisionErrors =
+			    XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
+			InstancePtr->Stats.RecvFcsErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RFCSEC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
+			InstancePtr->Stats.RecvLengthFieldErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
+			InstancePtr->Stats.RecvShortErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
+			InstancePtr->Stats.RecvLongErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
+			InstancePtr->Stats.RecvAlignmentErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RAEC_OFFSET);
+		}
+
+		/*
+		 * Bump recv interrupts stats only if not scatter-gather DMA (this
+		 * stat gets bumped elsewhere in that case)
+		 */
+		if (!XEmac_mIsSgDma(InstancePtr)) {
+			InstancePtr->Stats.RecvInterrupts++;	/* TODO: double bump? */
+		}
+
+	}
+
+	/*
+	 * Check for transmit errors. These apply to both DMA and non-DMA modes
+	 * of operation. The entire device should be reset after overruns or
+	 * underruns.
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			  XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		InstancePtr->Stats.XmitOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;
+	}
+
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			  XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		InstancePtr->Stats.XmitUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;
+	}
+
+	if (ResetError) {
+		/*
+		 * If a reset error occurred, disable the EMAC interrupts since the
+		 * reset-causing interrupt(s) is latched in the EMAC - meaning it will
+		 * keep occurring until the device is reset. In order to give the higher
+		 * layer software time to reset the device, we have to disable the
+		 * overrun/underrun interrupts until that happens. We trust that the
+		 * higher layer resets the device. We are able to get away with disabling
+		 * all EMAC interrupts since the only interrupts it generates are for
+		 * error conditions, and we don't care about any more errors right now.
+		 */
+		XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
+
+		/*
+		 * Invoke the error handler callback, which should result in a reset
+		 * of the device by the upper layer software.
+		 */
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					  XST_RESET_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Check the receive packet FIFO for errors. FIFO error interrupts are:
+* - Deadlock.  See the XPacketFifo component for a description of deadlock on a
+*   FIFO.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, it can return an asynchronous error to the
+* application through the error handler.  It can return XST_FIFO_ERROR if a FIFO
+* error occurred.
+*
+* @note
+*
+* This function is intended for internal use only.
+*
+******************************************************************************/
+void
+XEmac_CheckFifoRecvError(XEmac * InstancePtr)
+{
+	/*
+	 * Although the deadlock is currently the only interrupt from a packet
+	 * FIFO, make sure it is deadlocked before taking action. There is no
+	 * need to clear this interrupt since it requires a reset of the device.
+	 */
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
+		u32 IntrEnable;
+
+		InstancePtr->Stats.FifoErrors++;
+
+		/*
+		 * Invoke the error callback function, which should result in a reset
+		 * of the device by the upper layer software. We first need to disable
+		 * the FIFO interrupt, since otherwise the upper layer thread that
+		 * handles the reset may never run because this interrupt condition
+		 * doesn't go away until a reset occurs (there is no way to ack it).
+		 */
+		IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
+		XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+				      IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK);
+
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					  XST_FIFO_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Check the send packet FIFO for errors. FIFO error interrupts are:
+* - Deadlock. See the XPacketFifo component for a description of deadlock on a
+*   FIFO.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, it can return an asynchronous error to the
+* application through the error handler.  It can return XST_FIFO_ERROR if a FIFO
+* error occurred.
+*
+* @note
+*
+* This function is intended for internal use only.
+*
+******************************************************************************/
+void
+XEmac_CheckFifoSendError(XEmac * InstancePtr)
+{
+	/*
+	 * Although the deadlock is currently the only interrupt from a packet
+	 * FIFO, make sure it is deadlocked before taking action. There is no
+	 * need to clear this interrupt since it requires a reset of the device.
+	 */
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
+		u32 IntrEnable;
+
+		InstancePtr->Stats.FifoErrors++;
+
+		/*
+		 * Invoke the error callback function, which should result in a reset
+		 * of the device by the upper layer software. We first need to disable
+		 * the FIFO interrupt, since otherwise the upper layer thread that
+		 * handles the reset may never run because this interrupt condition
+		 * doesn't go away until a reset occurs (there is no way to ack it).
+		 */
+		IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
+		XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+				      IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK);
+
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					  XST_FIFO_ERROR);
+	}
+}
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_intr_dma.c b/u-boot/board/xilinx/xilinx_enet/xemac_intr_dma.c
new file mode 100644
index 0000000..567abb4
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_intr_dma.c
@@ -0,0 +1,1344 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_intr_dma.c
+*
+* Contains functions used in interrupt mode when configured with scatter-gather
+* DMA.
+*
+* The interrupt handler, XEmac_IntrHandlerDma(), must be connected by the user
+* to the interrupt controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
+*                     argument to SgSend
+* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
+*                     from SetPktThreshold in the internal DMA driver. Also
+*                     avoided compiler warnings by initializing Result in the
+*                     interrupt service routines.
+* 1.00c rpm  03/26/03 Fixed a problem in the interrupt service routines where
+*                     the interrupt status was toggled clear after a call to
+*                     ErrorHandler, but if ErrorHandler reset the device the
+*                     toggle actually asserted the interrupt because the
+*                     reset had cleared it.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xbuf_descriptor.h"
+#include "xdma_channel.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void HandleDmaRecvIntr(XEmac * InstancePtr);
+static void HandleDmaSendIntr(XEmac * InstancePtr);
+static void HandleEmacDmaIntr(XEmac * InstancePtr);
+
+/*****************************************************************************/
+/**
+*
+* Send an Ethernet frame using scatter-gather DMA. The caller attaches the
+* frame to one or more buffer descriptors, then calls this function once for
+* each descriptor. The caller is responsible for allocating and setting up the
+* descriptor. An entire Ethernet frame may or may not be contained within one
+* descriptor.  This function simply inserts the descriptor into the scatter-
+* gather engine's transmit list. The caller is responsible for providing mutual
+* exclusion to guarantee that a frame is contiguous in the transmit list. The
+* buffer attached to the descriptor must be word-aligned.
+*
+* The driver updates the descriptor with the device control register before
+* being inserted into the transmit list.  If this is the last descriptor in
+* the frame, the inserts are committed, which means the descriptors for this
+* frame are now available for transmission.
+*
+* It is assumed that the upper layer software supplies a correctly formatted
+* Ethernet frame, including the destination and source addresses, the
+* type/length field, and the data field.  It is also assumed that upper layer
+* software does not append FCS at the end of the frame.
+*
+* The buffer attached to the descriptor must be word-aligned on the front end.
+*
+* This call is non-blocking.  Notification of error or successful transmission
+* is done asynchronously through the send or error callback function.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BdPtr is the address of a descriptor to be inserted into the transmit
+*        ring.
+* @param Delay indicates whether to start the scatter-gather DMA channel
+*        immediately, or whether to wait. This allows the user to build up a
+*        list of more than one descriptor before starting the transmission of
+*        the packets, which allows the application to keep up with DMA and have
+*        a constant stream of frames being transmitted. Use XEM_SGDMA_NODELAY or
+*        XEM_SGDMA_DELAY, defined in xemac.h, as the value of this argument. If
+*        the user chooses to delay and build a list, the user must call this
+*        function with the XEM_SGDMA_NODELAY option or call XEmac_Start() to
+*        kick off the tranmissions.
+*
+* @return
+*
+* - XST_SUCCESS if the buffer was successfull sent
+* - XST_DEVICE_IS_STOPPED if the Ethernet MAC has not been started yet
+* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode
+* - XST_DMA_SG_LIST_FULL if the descriptor list for the DMA channel is full
+* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into
+*   the list because a locked descriptor exists at the insert point
+* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the
+*   list, the DMA channel believes there are no new descriptors to commit. If
+*   this is ever encountered, there is likely a thread mutual exclusion problem
+*   on transmit.
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* @internal
+*
+* A status that should never be returned from this function, although
+* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device
+* requires a list to be created, and this function requires the device to be
+* started.
+*
+******************************************************************************/
+XStatus
+XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay)
+{
+	XStatus Result;
+	u32 BdControl;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BdPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for scatter-gather DMA, then be sure
+	 * it is started.
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Set some descriptor control word defaults (source address increment
+	 * and local destination address) and the destination address
+	 * (the FIFO).  These are the same for every transmit descriptor.
+	 */
+	BdControl = XBufDescriptor_GetControl(BdPtr);
+	XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_SEND_BD_MASK);
+
+	XBufDescriptor_SetDestAddress(BdPtr,
+				      InstancePtr->BaseAddress +
+				      XEM_PFIFO_TXDATA_OFFSET);
+
+	/*
+	 * Put the descriptor in the send list. The DMA component accesses data
+	 * here that can also be modified in interrupt context, so a critical
+	 * section is required.
+	 */
+	XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+	Result = XDmaChannel_PutDescriptor(&InstancePtr->SendChannel, BdPtr);
+	if (Result != XST_SUCCESS) {
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+		return Result;
+	}
+
+	/*
+	 * If this is the last buffer in the frame, commit the inserts and start
+	 * the DMA engine if necessary
+	 */
+	if (XBufDescriptor_IsLastControl(BdPtr)) {
+		Result = XDmaChannel_CommitPuts(&InstancePtr->SendChannel);
+		if (Result != XST_SUCCESS) {
+			XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+			return Result;
+		}
+
+		if (Delay == XEM_SGDMA_NODELAY) {
+			/*
+			 * Start the DMA channel. Ignore the return status since we know the
+			 * list exists and has at least one entry and we don't care if the
+			 * channel is already started.  The DMA component accesses data here
+			 * that can be modified at interrupt or task levels, so a critical
+			 * section is required.
+			 */
+			(void) XDmaChannel_SgStart(&InstancePtr->SendChannel);
+		}
+	}
+
+	XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Add a descriptor, with an attached empty buffer, into the receive descriptor
+* list. The buffer attached to the descriptor must be word-aligned. This is
+* used by the upper layer software during initialization when first setting up
+* the receive descriptors, and also during reception of frames to replace
+* filled buffers with empty buffers. This function can be called when the
+* device is started or stopped. Note that it does start the scatter-gather DMA
+* engine.  Although this is not necessary during initialization, it is not a
+* problem during initialization because the MAC receiver is not yet started.
+*
+* The buffer attached to the descriptor must be word-aligned on both the front
+* end and the back end.
+*
+* Notification of received frames are done asynchronously through the receive
+* callback function.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BdPtr is a pointer to the buffer descriptor that will be added to the
+*        descriptor list.
+*
+* @return
+*
+* - XST_SUCCESS if a descriptor was successfully returned to the driver
+* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode
+* - XST_DMA_SG_LIST_FULL if the receive descriptor list is full
+* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into
+*   the list because a locked descriptor exists at the insert point.
+* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the
+*   list, the DMA channel believes there are no new descriptors to commit.
+*
+* @internal
+*
+* A status that should never be returned from this function, although
+* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device
+* requires a list to be created, and this function requires the device to be
+* started.
+*
+******************************************************************************/
+XStatus
+XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr)
+{
+	XStatus Result;
+	u32 BdControl;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BdPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for scatter-gather DMA
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Set some descriptor control word defaults (destination address increment
+	 * and local source address) and the source address (the FIFO). These are
+	 * the same for every receive descriptor.
+	 */
+	BdControl = XBufDescriptor_GetControl(BdPtr);
+	XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_RECV_BD_MASK);
+	XBufDescriptor_SetSrcAddress(BdPtr,
+				     InstancePtr->BaseAddress +
+				     XEM_PFIFO_RXDATA_OFFSET);
+
+	/*
+	 * Put the descriptor into the channel's descriptor list and commit.
+	 * Although this function is likely called within interrupt context, there
+	 * is the possibility that the upper layer software queues it to a task.
+	 * In this case, a critical section is needed here to protect shared data
+	 * in the DMA component.
+	 */
+	XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+	Result = XDmaChannel_PutDescriptor(&InstancePtr->RecvChannel, BdPtr);
+	if (Result != XST_SUCCESS) {
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+		return Result;
+	}
+
+	Result = XDmaChannel_CommitPuts(&InstancePtr->RecvChannel);
+	if (Result != XST_SUCCESS) {
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+		return Result;
+	}
+
+	/*
+	 * Start the DMA channel. Ignore the return status since we know the list
+	 * exists and has at least one entry and we don't care if the channel is
+	 * already started. The DMA component accesses data here that can be
+	 * modified at interrupt or task levels, so a critical section is required.
+	 */
+	(void) XDmaChannel_SgStart(&InstancePtr->RecvChannel);
+
+	XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for the Ethernet driver when configured with scatter-
+* gather DMA.
+*
+* Get the interrupt status from the IpIf to determine the source of the
+* interrupt.  The source can be: MAC, Recv Packet FIFO, Send Packet FIFO, Recv
+* DMA channel, or Send DMA channel. The packet FIFOs only interrupt during
+* "deadlock" conditions.
+*
+* @param InstancePtr is a pointer to the XEmac instance that just interrupted.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_IntrHandlerDma(void *InstancePtr)
+{
+	u32 IntrStatus;
+	XEmac *EmacPtr = (XEmac *) InstancePtr;
+
+	EmacPtr->Stats.TotalIntrs++;
+
+	/*
+	 * Get the interrupt status from the IPIF. There is no clearing of
+	 * interrupts in the IPIF. Interrupts must be cleared at the source.
+	 */
+	IntrStatus = XIIF_V123B_READ_DIPR(EmacPtr->BaseAddress);
+
+	/*
+	 * See which type of interrupt is being requested, and service it
+	 */
+	if (IntrStatus & XEM_IPIF_RECV_DMA_MASK) {	/* Receive DMA interrupt */
+		EmacPtr->Stats.RecvInterrupts++;
+		HandleDmaRecvIntr(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_SEND_DMA_MASK) {	/* Send DMA interrupt */
+		EmacPtr->Stats.XmitInterrupts++;
+		HandleDmaSendIntr(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_EMAC_MASK) {	/* MAC interrupt */
+		EmacPtr->Stats.EmacInterrupts++;
+		HandleEmacDmaIntr(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_RECV_FIFO_MASK) {	/* Receive FIFO interrupt */
+		EmacPtr->Stats.RecvInterrupts++;
+		XEmac_CheckFifoRecvError(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_SEND_FIFO_MASK) {	/* Send FIFO interrupt */
+		EmacPtr->Stats.XmitInterrupts++;
+		XEmac_CheckFifoSendError(EmacPtr);
+	}
+
+	if (IntrStatus & XIIF_V123B_ERROR_MASK) {
+		/*
+		 * An error occurred internal to the IPIF. This is more of a debug and
+		 * integration issue rather than a production error. Don't do anything
+		 * other than clear it, which provides a spot for software to trap
+		 * on the interrupt and begin debugging.
+		 */
+		XIIF_V123B_WRITE_DISR(EmacPtr->BaseAddress,
+				      XIIF_V123B_ERROR_MASK);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the packet count threshold for this device. The device must be stopped
+* before setting the threshold. The packet count threshold is used for interrupt
+* coalescing, which reduces the frequency of interrupts from the device to the
+* processor. In this case, the scatter-gather DMA engine only interrupts when
+* the packet count threshold is reached, instead of interrupting for each packet.
+* A packet is a generic term used by the scatter-gather DMA engine, and is
+* equivalent to an Ethernet frame in our case.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param Threshold is the value of the packet threshold count used during
+*        interrupt coalescing. A value of 0 disables the use of packet threshold
+*        by the hardware.
+*
+* @return
+*
+* - XST_SUCCESS if the threshold was successfully set
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DEVICE_IS_STARTED if the device has not been stopped
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* The packet threshold could be set to larger than the number of descriptors
+* allocated to the DMA channel. In this case, the wait bound will take over
+* and always indicate data arrival. There was a check in this function that
+* returned an error if the treshold was larger than the number of descriptors,
+* but that was removed because users would then have to set the threshold
+* only after they set descriptor space, which is an order dependency that
+* caused confustion.
+*
+******************************************************************************/
+XStatus
+XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure device is configured for scatter-gather DMA and has been stopped
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Based on the direction, set the packet threshold in the
+	 * corresponding DMA channel component.  Default to the receive
+	 * channel threshold register (if an invalid Direction is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		return XDmaChannel_SetPktThreshold(&InstancePtr->SendChannel,
+						   Threshold);
+
+	case XEM_RECV:
+		return XDmaChannel_SetPktThreshold(&InstancePtr->RecvChannel,
+						   Threshold);
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the value of the packet count threshold for this driver/device. The packet
+* count threshold is used for interrupt coalescing, which reduces the frequency
+* of interrupts from the device to the processor. In this case, the
+* scatter-gather DMA engine only interrupts when the packet count threshold is
+* reached, instead of interrupting for each packet. A packet is a generic term
+* used by the scatter-gather DMA engine, and is equivalent to an Ethernet frame
+* in our case.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param ThreshPtr is a pointer to the byte into which the current value of the
+*        packet threshold register will be copied. An output parameter. A value
+*        of 0 indicates the use of packet threshold by the hardware is disabled.
+*
+* @return
+*
+* - XST_SUCCESS if the packet threshold was retrieved successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 * ThreshPtr)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(ThreshPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Based on the direction, return the packet threshold set in the
+	 * corresponding DMA channel component.  Default to the value in
+	 * the receive channel threshold register (if an invalid Direction
+	 * is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		*ThreshPtr =
+		    XDmaChannel_GetPktThreshold(&InstancePtr->SendChannel);
+		break;
+
+	case XEM_RECV:
+		*ThreshPtr =
+		    XDmaChannel_GetPktThreshold(&InstancePtr->RecvChannel);
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the packet wait bound timer for this driver/device. The device must be
+* stopped before setting the timer value. The packet wait bound is used during
+* interrupt coalescing to trigger an interrupt when not enough packets have been
+* received to reach the packet count threshold. A packet is a generic term used
+* by the scatter-gather DMA engine, and is equivalent to an Ethernet frame in
+* our case. The timer is in milliseconds.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param TimerValue is the value of the packet wait bound used during interrupt
+*        coalescing. It is in milliseconds in the range 0  - 1023. A value of 0
+*        disables the packet wait bound timer.
+*
+* @return
+*
+* - XST_SUCCESS if the packet wait bound was set successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DEVICE_IS_STARTED if the device has not been stopped
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 TimerValue)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(TimerValue <= XEM_SGDMA_MAX_WAITBOUND);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure device is configured for scatter-gather DMA and has been stopped
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Based on the direction, set the packet wait bound in the
+	 * corresponding DMA channel component.  Default to the receive
+	 * channel wait bound register (if an invalid Direction is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		XDmaChannel_SetPktWaitBound(&InstancePtr->SendChannel,
+					    TimerValue);
+		break;
+
+	case XEM_RECV:
+		XDmaChannel_SetPktWaitBound(&InstancePtr->RecvChannel,
+					    TimerValue);
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the packet wait bound timer for this driver/device. The packet wait bound
+* is used during interrupt coalescing to trigger an interrupt when not enough
+* packets have been received to reach the packet count threshold. A packet is a
+* generic term used by the scatter-gather DMA engine, and is equivalent to an
+* Ethernet frame in our case. The timer is in milliseconds.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param WaitPtr is a pointer to the byte into which the current value of the
+*        packet wait bound register will be copied. An output parameter. Units
+*        are in milliseconds in the range 0  - 1023. A value of 0 indicates the
+*        packet wait bound timer is disabled.
+*
+* @return
+*
+* - XST_SUCCESS if the packet wait bound was retrieved successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 * WaitPtr)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(WaitPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Based on the direction, return the packet wait bound set in the
+	 * corresponding DMA channel component.  Default to the value in
+	 * the receive channel wait bound register (if an invalid Direction
+	 * is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		*WaitPtr =
+		    XDmaChannel_GetPktWaitBound(&InstancePtr->SendChannel);
+		break;
+
+	case XEM_RECV:
+		*WaitPtr =
+		    XDmaChannel_GetPktWaitBound(&InstancePtr->RecvChannel);
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Give the driver the memory space to be used for the scatter-gather DMA
+* receive descriptor list. This function should only be called once, during
+* initialization of the Ethernet driver. The memory space must be big enough
+* to hold some number of descriptors, depending on the needs of the system.
+* The xemac.h file defines minimum and default numbers of descriptors
+* which can be used to allocate this memory space.
+*
+* The memory space must be word-aligned. An assert will occur if asserts are
+* turned on and the memory is not word-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param MemoryPtr is a pointer to the word-aligned memory.
+* @param ByteCount is the length, in bytes, of the memory space.
+*
+* @return
+*
+* - XST_SUCCESS if the space was initialized successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DMA_SG_LIST_EXISTS if this list space has already been created
+*
+* @note
+*
+* If the device is configured for scatter-gather DMA, this function must be
+* called AFTER the XEmac_Initialize() function because the DMA channel
+* components must be initialized before the memory space is set.
+*
+******************************************************************************/
+XStatus
+XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(MemoryPtr != NULL);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	return XDmaChannel_CreateSgList(&InstancePtr->RecvChannel, MemoryPtr,
+					ByteCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* Give the driver the memory space to be used for the scatter-gather DMA
+* transmit descriptor list. This function should only be called once, during
+* initialization of the Ethernet driver. The memory space must be big enough
+* to hold some number of descriptors, depending on the needs of the system.
+* The xemac.h file defines minimum and default numbers of descriptors
+* which can be used to allocate this memory space.
+*
+* The memory space must be word-aligned. An assert will occur if asserts are
+* turned on and the memory is not word-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param MemoryPtr is a pointer to the word-aligned memory.
+* @param ByteCount is the length, in bytes, of the memory space.
+*
+* @return
+*
+* - XST_SUCCESS if the space was initialized successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DMA_SG_LIST_EXISTS if this list space has already been created
+*
+* @note
+*
+* If the device is configured for scatter-gather DMA, this function must be
+* called AFTER the XEmac_Initialize() function because the DMA channel
+* components must be initialized before the memory space is set.
+*
+******************************************************************************/
+XStatus
+XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(MemoryPtr != NULL);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	return XDmaChannel_CreateSgList(&InstancePtr->SendChannel, MemoryPtr,
+					ByteCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the callback function for handling received frames in scatter-gather DMA
+* mode.  The upper layer software should call this function during
+* initialization.  The callback is called once per frame received. The head of
+* a descriptor list is passed in along with the number of descriptors in the
+* list. Before leaving the callback, the upper layer software should attach a
+* new buffer to each descriptor in the list.
+*
+* The callback is invoked by the driver within interrupt context, so it needs
+* to do its job quickly. Sending the received frame up the protocol stack
+* should be done at task-level. If there are other potentially slow operations
+* within the callback, these too should be done at task-level.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param CallBackRef is a reference pointer to be passed back to the adapter in
+*        the callback. This helps the adapter correlate the callback to a
+*        particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
+		       XEmac_SgHandler FuncPtr)
+{
+	/*
+	 * Asserted IsDmaSg here instead of run-time check because there is really
+	 * no ill-effects of setting these when not configured for scatter-gather.
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(FuncPtr != NULL);
+	XASSERT_VOID(XEmac_mIsSgDma(InstancePtr));
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	InstancePtr->SgRecvHandler = FuncPtr;
+	InstancePtr->SgRecvRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the callback function for handling confirmation of transmitted frames in
+* scatter-gather DMA mode.  The upper layer software should call this function
+* during initialization.  The callback is called once per frame sent. The head
+* of a descriptor list is passed in along with the number of descriptors in
+* the list. The callback is responsible for freeing buffers attached to these
+* descriptors.
+*
+* The callback is invoked by the driver within interrupt context, so it needs
+* to do its job quickly. If there are potentially slow operations within the
+* callback, these should be done at task-level.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param CallBackRef is a reference pointer to be passed back to the adapter in
+*        the callback. This helps the adapter correlate the callback to a
+*        particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
+		       XEmac_SgHandler FuncPtr)
+{
+	/*
+	 * Asserted IsDmaSg here instead of run-time check because there is really
+	 * no ill-effects of setting these when not configured for scatter-gather.
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(FuncPtr != NULL);
+	XASSERT_VOID(XEmac_mIsSgDma(InstancePtr));
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	InstancePtr->SgSendHandler = FuncPtr;
+	InstancePtr->SgSendRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/*
+*
+* Handle an interrupt from the DMA receive channel. DMA interrupts are:
+*
+* - DMA error. DMA encountered a bus error or timeout. This is a fatal error
+*   that requires reset of the channel.  The driver calls the error handler
+*   of the upper layer software with an error code indicating the device should
+*   be reset.
+* - Packet count threshold reached.  For scatter-gather operations, indicates
+*   the threshold for the number of packets not serviced by software has been
+*   reached. The driver behaves as follows:
+*       - Get the value of the packet counter, which tells us how many packets
+*         are ready to be serviced
+*       - For each packet
+*           - For each descriptor, remove it from the scatter-gather list
+*           - Check for the last descriptor in the frame, and if set
+*               - Bump frame statistics
+*               - Call the scatter-gather receive callback function
+*               - Decrement the packet counter by one
+*       Note that there are no receive errors reported in the status word of
+*       the buffer descriptor.  If receive errors occur, the MAC drops the
+*       packet, and we only find out about the errors through various error
+*       count registers.
+* - Packet wait bound reached.  For scatter-gather, indicates the time to wait
+*   for the next packet has expired.  The driver follows the same logic as when
+*   the packet count threshold interrupt is received.
+* - Scatter-gather end acknowledge.  Hardware has reached the end of the
+*   descriptor list.  The driver follows the same logic as when the packet count
+*   threshold interrupt is received. In addition, the driver restarts the DMA
+*   scatter-gather channel in case there are newly inserted descriptors.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, there are asynchronous errors that can
+* be generated (by calling the ErrorHandler) from this function.  These are:
+* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from the
+*   DMA channel, but there was not one ready for software.
+* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a fatal
+*   error that requires reset.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+HandleDmaRecvIntr(XEmac * InstancePtr)
+{
+	u32 IntrStatus;
+
+	/*
+	 * Read the interrupt status
+	 */
+	IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->RecvChannel);
+
+	/*
+	 * For packet threshold or wait bound interrupts, process desciptors. Also
+	 * process descriptors on a SG end acknowledgement, which means the end of
+	 * the descriptor list has been reached by the hardware. For receive, this
+	 * is potentially trouble since it means the descriptor list is full,
+	 * unless software can process enough packets quickly enough so the
+	 * hardware has room to put new packets.
+	 */
+	if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK |
+			  XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) {
+		XStatus Result = XST_SUCCESS;
+		u32 NumFrames;
+		u32 NumProcessed;
+		u32 NumBuffers;
+		u32 NumBytes;
+		u32 IsLast;
+		XBufDescriptor *FirstBdPtr;
+		XBufDescriptor *BdPtr;
+
+		/*
+		 * Get the number of unserviced packets
+		 */
+		NumFrames = XDmaChannel_GetPktCount(&InstancePtr->RecvChannel);
+
+		for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) {
+			IsLast = FALSE;
+			FirstBdPtr = NULL;
+			NumBuffers = 0;
+			NumBytes = 0;
+
+			/*
+			 * For each packet, get the descriptor from the list. On the
+			 * last one in the frame, make the callback to the upper layer.
+			 */
+			while (!IsLast) {
+				Result =
+				    XDmaChannel_GetDescriptor(&InstancePtr->
+							      RecvChannel,
+							      &BdPtr);
+				if (Result != XST_SUCCESS) {
+					/*
+					 * An error getting a buffer descriptor from the list.
+					 * This should not happen, but if it does, report it to
+					 * the error callback and break out of the loops to service
+					 * other interrupts.
+					 */
+					InstancePtr->ErrorHandler(InstancePtr->
+								  ErrorRef,
+								  Result);
+					break;
+				}
+
+				/*
+				 * Keep a pointer to the first descriptor in the list, as it
+				 * will be passed to the upper layers in a bit. By the fact
+				 * that we received this packet means no errors occurred, so
+				 * no need to check the device status word for errors.
+				 */
+				if (FirstBdPtr == NULL) {
+					FirstBdPtr = BdPtr;
+				}
+
+				NumBytes += XBufDescriptor_GetLength(BdPtr);
+
+				/*
+				 * Check to see if this is the last descriptor in the frame,
+				 * and if so, set the IsLast flag to get out of the loop.
+				 */
+				if (XBufDescriptor_IsLastStatus(BdPtr)) {
+					IsLast = TRUE;
+				}
+
+				/*
+				 * Bump the number of buffers in this packet
+				 */
+				NumBuffers++;
+
+			}	/* end while loop */
+
+			/*
+			 * Check for error that occurred inside the while loop, and break
+			 * out of the for loop if there was one so other interrupts can
+			 * be serviced.
+			 */
+			if (Result != XST_SUCCESS) {
+				break;
+			}
+
+			InstancePtr->Stats.RecvFrames++;
+			InstancePtr->Stats.RecvBytes += NumBytes;
+
+			/*
+			 * Make the callback to the upper layers, passing it the first
+			 * descriptor in the packet and the number of descriptors in the
+			 * packet.
+			 */
+			InstancePtr->SgRecvHandler(InstancePtr->SgRecvRef,
+						   FirstBdPtr, NumBuffers);
+
+			/*
+			 * Decrement the packet count register to reflect the fact we
+			 * just processed a packet
+			 */
+			XDmaChannel_DecrementPktCount(&InstancePtr->
+						      RecvChannel);
+
+		}		/* end for loop */
+
+		/*
+		 * If the interrupt was an end-ack, check the descriptor list again to
+		 * see if it is empty. If not, go ahead and restart the scatter-gather
+		 * channel. This is to fix a possible race condition where, on receive,
+		 * the driver attempted to start a scatter-gather channel that was
+		 * already started, which resulted in no action from the XDmaChannel
+		 * component. But, just after the XDmaChannel component saw that the
+		 * hardware was already started, the hardware stopped because it
+		 * reached the end of the list.  In that case, this interrupt is
+		 * generated and we can restart the hardware here.
+		 */
+		if (IntrStatus & XDC_IXR_SG_END_MASK) {
+			/*
+			 * Ignore the return status since we know the list exists and we
+			 * don't care if the list is empty or the channel is already started.
+			 */
+			(void) XDmaChannel_SgStart(&InstancePtr->RecvChannel);
+		}
+	}
+
+	/*
+	 * All interrupts are handled (except the error below) so acknowledge
+	 * (clear) the interrupts by writing the value read above back to the status
+	 * register. The packet count interrupt must be acknowledged after the
+	 * decrement, otherwise it will come right back. We clear the interrupts
+	 * before we handle the error interrupt because the ErrorHandler should
+	 * result in a reset, which clears the interrupt status register. So we
+	 * don't want to toggle the interrupt back on by writing the interrupt
+	 * status register with an old value after a reset.
+	 */
+	XDmaChannel_SetIntrStatus(&InstancePtr->RecvChannel, IntrStatus);
+
+	/*
+	 * Check for DMA errors and call the error callback function if an error
+	 * occurred (DMA bus or timeout error), which should result in a reset of
+	 * the device by the upper layer software.
+	 */
+	if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) {
+		InstancePtr->Stats.DmaErrors++;
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Handle an interrupt from the DMA send channel. DMA interrupts are:
+*
+* - DMA error. DMA encountered a bus error or timeout. This is a fatal error
+*   that requires reset of the channel.  The driver calls the error handler
+*   of the upper layer software with an error code indicating the device should
+*   be reset.
+* - Packet count threshold reached.  For scatter-gather operations, indicates
+*   the threshold for the number of packets not serviced by software has been
+*   reached. The driver behaves as follows:
+*       - Get the value of the packet counter, which tells us how many packets
+*         are ready to be serviced
+*       - For each packet
+*           - For each descriptor, remove it from the scatter-gather list
+*           - Check for the last descriptor in the frame, and if set
+*               - Bump frame statistics
+*               - Call the scatter-gather receive callback function
+*               - Decrement the packet counter by one
+*       Note that there are no receive errors reported in the status word of
+*       the buffer descriptor.  If receive errors occur, the MAC drops the
+*       packet, and we only find out about the errors through various error
+*       count registers.
+* - Packet wait bound reached.  For scatter-gather, indicates the time to wait
+*   for the next packet has expired.  The driver follows the same logic as when
+*   the packet count threshold interrupt is received.
+* - Scatter-gather end acknowledge.  Hardware has reached the end of the
+*   descriptor list.  The driver follows the same logic as when the packet count
+*   threshold interrupt is received. In addition, the driver restarts the DMA
+*   scatter-gather channel in case there are newly inserted descriptors.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, there are asynchronous errors
+* that can be generated from this function.  These are:
+* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from
+*   the DMA channel, but there was not one ready for software.
+* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a
+*   fatal error that requires reset.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+HandleDmaSendIntr(XEmac * InstancePtr)
+{
+	u32 IntrStatus;
+
+	/*
+	 * Read the interrupt status
+	 */
+	IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->SendChannel);
+
+	/*
+	 * For packet threshold or wait bound interrupt, process descriptors. Also
+	 * process descriptors on a SG end acknowledgement, which means the end of
+	 * the descriptor list has been reached by the hardware. For transmit,
+	 * this is a normal condition during times of light traffic.  In fact, the
+	 * wait bound interrupt may be masked for transmit since the end-ack would
+	 * always occur before the wait bound expires.
+	 */
+	if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK |
+			  XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) {
+		XStatus Result = XST_SUCCESS;
+		u32 NumFrames;
+		u32 NumProcessed;
+		u32 NumBuffers;
+		u32 NumBytes;
+		u32 IsLast;
+		XBufDescriptor *FirstBdPtr;
+		XBufDescriptor *BdPtr;
+
+		/*
+		 * Get the number of unserviced packets
+		 */
+		NumFrames = XDmaChannel_GetPktCount(&InstancePtr->SendChannel);
+
+		for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) {
+			IsLast = FALSE;
+			FirstBdPtr = NULL;
+			NumBuffers = 0;
+			NumBytes = 0;
+
+			/*
+			 * For each frame, traverse the descriptor list and look for
+			 * errors. On the last one in the frame, make the callback.
+			 */
+			while (!IsLast) {
+				Result =
+				    XDmaChannel_GetDescriptor(&InstancePtr->
+							      SendChannel,
+							      &BdPtr);
+				if (Result != XST_SUCCESS) {
+					/*
+					 * An error getting a buffer descriptor from the list.
+					 * This should not happen, but if it does, report it to
+					 * the error callback and break out of the loops to service
+					 * other interrupts
+					 */
+					InstancePtr->ErrorHandler(InstancePtr->
+								  ErrorRef,
+								  Result);
+					break;
+				}
+
+				/*
+				 * Keep a pointer to the first descriptor in the list and
+				 * check the device status for errors. The device status is
+				 * only available in the first descriptor of a packet.
+				 */
+				if (FirstBdPtr == NULL) {
+					u32 XmitStatus;
+
+					FirstBdPtr = BdPtr;
+
+					XmitStatus =
+					    XBufDescriptor_GetDeviceStatus
+					    (BdPtr);
+					if (XmitStatus &
+					    XEM_TSR_EXCESS_DEFERRAL_MASK) {
+						InstancePtr->Stats.
+						    XmitExcessDeferral++;
+					}
+
+					if (XmitStatus &
+					    XEM_TSR_LATE_COLLISION_MASK) {
+						InstancePtr->Stats.
+						    XmitLateCollisionErrors++;
+					}
+				}
+
+				NumBytes += XBufDescriptor_GetLength(BdPtr);
+
+				/*
+				 * Check to see if this is the last descriptor in the frame,
+				 * and if so, set the IsLast flag to get out of the loop. The
+				 * transmit channel must check the last bit in the control
+				 * word, not the status word (the DMA engine does not update
+				 * the last bit in the status word for the transmit direction).
+				 */
+				if (XBufDescriptor_IsLastControl(BdPtr)) {
+					IsLast = TRUE;
+				}
+
+				/*
+				 * Bump the number of buffers in this packet
+				 */
+				NumBuffers++;
+
+			}	/* end while loop */
+
+			/*
+			 * Check for error that occurred inside the while loop, and break
+			 * out of the for loop if there was one so other interrupts can
+			 * be serviced.
+			 */
+			if (Result != XST_SUCCESS) {
+				break;
+			}
+
+			InstancePtr->Stats.XmitFrames++;
+			InstancePtr->Stats.XmitBytes += NumBytes;
+
+			/*
+			 * Make the callback to the upper layers, passing it the first
+			 * descriptor in the packet and the number of descriptors in the
+			 * packet.
+			 */
+			InstancePtr->SgSendHandler(InstancePtr->SgSendRef,
+						   FirstBdPtr, NumBuffers);
+
+			/*
+			 * Decrement the packet count register to reflect the fact we
+			 * just processed a packet
+			 */
+			XDmaChannel_DecrementPktCount(&InstancePtr->
+						      SendChannel);
+
+		}		/* end for loop */
+
+		/*
+		 * If the interrupt was an end-ack, check the descriptor list again to
+		 * see if it is empty. If not, go ahead and restart the scatter-gather
+		 * channel. This is to fix a possible race condition where, on transmit,
+		 * the driver attempted to start a scatter-gather channel that was
+		 * already started, which resulted in no action from the XDmaChannel
+		 * component. But, just after the XDmaChannel component saw that the
+		 * hardware was already started, the hardware stopped because it
+		 * reached the end of the list.  In that case, this interrupt is
+		 * generated and we can restart the hardware here.
+		 */
+		if (IntrStatus & XDC_IXR_SG_END_MASK) {
+			/*
+			 * Ignore the return status since we know the list exists and we
+			 * don't care if the list is empty or the channel is already started.
+			 */
+			(void) XDmaChannel_SgStart(&InstancePtr->SendChannel);
+		}
+	}
+
+	/*
+	 * All interrupts are handled (except the error below) so acknowledge
+	 * (clear) the interrupts by writing the value read above back to the status
+	 * register. The packet count interrupt must be acknowledged after the
+	 * decrement, otherwise it will come right back. We clear the interrupts
+	 * before we handle the error interrupt because the ErrorHandler should
+	 * result in a reset, which clears the interrupt status register. So we
+	 * don't want to toggle the interrupt back on by writing the interrupt
+	 * status register with an old value after a reset.
+	 */
+	XDmaChannel_SetIntrStatus(&InstancePtr->SendChannel, IntrStatus);
+
+	/*
+	 * Check for DMA errors and call the error callback function if an error
+	 * occurred (DMA bus or timeout error), which should result in a reset of
+	 * the device by the upper layer software.
+	 */
+	if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) {
+		InstancePtr->Stats.DmaErrors++;
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Handle an interrupt from the Ethernet MAC when configured with scatter-gather
+* DMA. The only interrupts handled in this case are errors.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+HandleEmacDmaIntr(XEmac * InstancePtr)
+{
+	u32 IntrStatus;
+
+	/*
+	 * When configured with DMA, the EMAC generates interrupts only when errors
+	 * occur. We clear the interrupts immediately so that any latched status
+	 * interrupt bits will reflect the true status of the device, and so any
+	 * pulsed interrupts (non-status) generated during the Isr will not be lost.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus);
+
+	/*
+	 * Check the MAC for errors
+	 */
+	XEmac_CheckEmacError(InstancePtr, IntrStatus);
+}
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_l.h b/u-boot/board/xilinx/xilinx_enet/xemac_l.h
new file mode 100644
index 0000000..a463937
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_l.h
@@ -0,0 +1,462 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_l.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  High-level driver functions
+* are defined in xemac.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/26/02 First release
+* 1.00b rmm  09/23/02 Added XEmac_mPhyReset macro
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_L_H		/* prevent circular inclusions */
+#define XEMAC_L_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Offset of the MAC registers from the IPIF base address */
+#define XEM_REG_OFFSET	   0x1100UL
+
+/*
+ * Register offsets for the Ethernet MAC. Each register is 32 bits.
+ */
+#define XEM_EMIR_OFFSET	  (XEM_REG_OFFSET + 0x0)	/* EMAC Module ID */
+#define XEM_ECR_OFFSET	  (XEM_REG_OFFSET + 0x4)	/* MAC Control */
+#define XEM_IFGP_OFFSET	  (XEM_REG_OFFSET + 0x8)	/* Interframe Gap */
+#define XEM_SAH_OFFSET	  (XEM_REG_OFFSET + 0xC)	/* Station addr, high */
+#define XEM_SAL_OFFSET	  (XEM_REG_OFFSET + 0x10)	/* Station addr, low */
+#define XEM_MGTCR_OFFSET  (XEM_REG_OFFSET + 0x14)	/* MII mgmt control */
+#define XEM_MGTDR_OFFSET  (XEM_REG_OFFSET + 0x18)	/* MII mgmt data */
+#define XEM_RPLR_OFFSET	  (XEM_REG_OFFSET + 0x1C)	/* Rx packet length */
+#define XEM_TPLR_OFFSET	  (XEM_REG_OFFSET + 0x20)	/* Tx packet length */
+#define XEM_TSR_OFFSET	  (XEM_REG_OFFSET + 0x24)	/* Tx status */
+#define XEM_RMFC_OFFSET	  (XEM_REG_OFFSET + 0x28)	/* Rx missed frames */
+#define XEM_RCC_OFFSET	  (XEM_REG_OFFSET + 0x2C)	/* Rx collisions */
+#define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30)	/* Rx FCS errors */
+#define XEM_RAEC_OFFSET	  (XEM_REG_OFFSET + 0x34)	/* Rx alignment errors */
+#define XEM_TEDC_OFFSET	  (XEM_REG_OFFSET + 0x38)	/* Transmit excess
+							 * deferral cnt */
+
+/*
+ * Register offsets for the IPIF components
+ */
+#define XEM_ISR_OFFSET		 0x20UL /* Interrupt status */
+
+#define XEM_DMA_OFFSET		 0x2300UL
+#define XEM_DMA_SEND_OFFSET	 (XEM_DMA_OFFSET + 0x0) /* DMA send channel */
+#define XEM_DMA_RECV_OFFSET	 (XEM_DMA_OFFSET + 0x40)	/* DMA recv channel */
+
+#define XEM_PFIFO_OFFSET	 0x2000UL
+#define XEM_PFIFO_TXREG_OFFSET	 (XEM_PFIFO_OFFSET + 0x0)	/* Tx registers */
+#define XEM_PFIFO_RXREG_OFFSET	 (XEM_PFIFO_OFFSET + 0x10)	/* Rx registers */
+#define XEM_PFIFO_TXDATA_OFFSET	 (XEM_PFIFO_OFFSET + 0x100)	/* Tx keyhole */
+#define XEM_PFIFO_RXDATA_OFFSET	 (XEM_PFIFO_OFFSET + 0x200)	/* Rx keyhole */
+
+/*
+ * EMAC Module Identification Register (EMIR)
+ */
+#define XEM_EMIR_VERSION_MASK	 0xFFFF0000UL	/* Device version */
+#define XEM_EMIR_TYPE_MASK	 0x0000FF00UL	/* Device type */
+
+/*
+ * EMAC Control Register (ECR)
+ */
+#define XEM_ECR_FULL_DUPLEX_MASK	 0x80000000UL	/* Full duplex mode */
+#define XEM_ECR_XMIT_RESET_MASK		 0x40000000UL	/* Reset transmitter */
+#define XEM_ECR_XMIT_ENABLE_MASK	 0x20000000UL	/* Enable transmitter */
+#define XEM_ECR_RECV_RESET_MASK		 0x10000000UL	/* Reset receiver */
+#define XEM_ECR_RECV_ENABLE_MASK	 0x08000000UL	/* Enable receiver */
+#define XEM_ECR_PHY_ENABLE_MASK		 0x04000000UL	/* Enable PHY */
+#define XEM_ECR_XMIT_PAD_ENABLE_MASK	 0x02000000UL	/* Enable xmit pad insert */
+#define XEM_ECR_XMIT_FCS_ENABLE_MASK	 0x01000000UL	/* Enable xmit FCS insert */
+#define XEM_ECR_XMIT_ADDR_INSERT_MASK	 0x00800000UL	/* Enable xmit source addr
+							 * insertion */
+#define XEM_ECR_XMIT_ERROR_INSERT_MASK	 0x00400000UL	/* Insert xmit error */
+#define XEM_ECR_XMIT_ADDR_OVWRT_MASK	 0x00200000UL	/* Enable xmit source addr
+							 * overwrite */
+#define XEM_ECR_LOOPBACK_MASK		 0x00100000UL	/* Enable internal
+							 * loopback */
+#define XEM_ECR_RECV_STRIP_ENABLE_MASK	 0x00080000UL	/* Enable recv pad/fcs strip */
+#define XEM_ECR_UNICAST_ENABLE_MASK	 0x00020000UL	/* Enable unicast addr */
+#define XEM_ECR_MULTI_ENABLE_MASK	 0x00010000UL	/* Enable multicast addr */
+#define XEM_ECR_BROAD_ENABLE_MASK	 0x00008000UL	/* Enable broadcast addr */
+#define XEM_ECR_PROMISC_ENABLE_MASK	 0x00004000UL	/* Enable promiscuous mode */
+#define XEM_ECR_RECV_ALL_MASK		 0x00002000UL	/* Receive all frames */
+#define XEM_ECR_RESERVED2_MASK		 0x00001000UL	/* Reserved */
+#define XEM_ECR_MULTI_HASH_ENABLE_MASK	 0x00000800UL	/* Enable multicast hash */
+#define XEM_ECR_PAUSE_FRAME_MASK	 0x00000400UL	/* Interpret pause frames */
+#define XEM_ECR_CLEAR_HASH_MASK		 0x00000200UL	/* Clear hash table */
+#define XEM_ECR_ADD_HASH_ADDR_MASK	 0x00000100UL	/* Add hash table address */
+
+/*
+ * Interframe Gap Register (IFGR)
+ */
+#define XEM_IFGP_PART1_MASK	    0xF8000000UL	/* Interframe Gap Part1 */
+#define XEM_IFGP_PART1_SHIFT	    27
+#define XEM_IFGP_PART2_MASK	    0x07C00000UL	/* Interframe Gap Part2 */
+#define XEM_IFGP_PART2_SHIFT	    22
+
+/*
+ * Station Address High Register (SAH)
+ */
+#define XEM_SAH_ADDR_MASK	    0x0000FFFFUL	/* Station address high bytes */
+
+/*
+ * Station Address Low Register (SAL)
+ */
+#define XEM_SAL_ADDR_MASK	    0xFFFFFFFFUL	/* Station address low bytes */
+
+/*
+ * MII Management Control Register (MGTCR)
+ */
+#define XEM_MGTCR_START_MASK	    0x80000000UL	/* Start/Busy */
+#define XEM_MGTCR_RW_NOT_MASK	    0x40000000UL	/* Read/Write Not (direction) */
+#define XEM_MGTCR_PHY_ADDR_MASK	    0x3E000000UL	/* PHY address */
+#define XEM_MGTCR_PHY_ADDR_SHIFT    25	/* PHY address shift */
+#define XEM_MGTCR_REG_ADDR_MASK	    0x01F00000UL	/* Register address */
+#define XEM_MGTCR_REG_ADDR_SHIFT    20	/* Register addr shift */
+#define XEM_MGTCR_MII_ENABLE_MASK   0x00080000UL	/* Enable MII from EMAC */
+#define XEM_MGTCR_RD_ERROR_MASK	    0x00040000UL	/* MII mgmt read error */
+
+/*
+ * MII Management Data Register (MGTDR)
+ */
+#define XEM_MGTDR_DATA_MASK	    0x0000FFFFUL	/* MII data */
+
+/*
+ * Receive Packet Length Register (RPLR)
+ */
+#define XEM_RPLR_LENGTH_MASK	    0x0000FFFFUL	/* Receive packet length */
+
+/*
+ * Transmit Packet Length Register (TPLR)
+ */
+#define XEM_TPLR_LENGTH_MASK	    0x0000FFFFUL	/* Transmit packet length */
+
+/*
+ * Transmit Status Register (TSR)
+ */
+#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL	/* Transmit excess deferral */
+#define XEM_TSR_FIFO_UNDERRUN_MASK   0x40000000UL	/* Packet FIFO underrun */
+#define XEM_TSR_ATTEMPTS_MASK	     0x3E000000UL	/* Transmission attempts */
+#define XEM_TSR_LATE_COLLISION_MASK  0x01000000UL	/* Transmit late collision */
+
+/*
+ * Receive Missed Frame Count (RMFC)
+ */
+#define XEM_RMFC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Receive Collision Count (RCC)
+ */
+#define XEM_RCC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Receive FCS Error Count (RFCSEC)
+ */
+#define XEM_RFCSEC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Receive Alignment Error Count (RALN)
+ */
+#define XEM_RAEC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Transmit Excess Deferral Count (TEDC)
+ */
+#define XEM_TEDC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
+ * part of the IPIF IP Interrupt registers
+ */
+#define XEM_EIR_XMIT_DONE_MASK	       0x00000001UL	/* Xmit complete */
+#define XEM_EIR_RECV_DONE_MASK	       0x00000002UL	/* Recv complete */
+#define XEM_EIR_XMIT_ERROR_MASK	       0x00000004UL	/* Xmit error */
+#define XEM_EIR_RECV_ERROR_MASK	       0x00000008UL	/* Recv error */
+#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK  0x00000010UL	/* Xmit status fifo empty */
+#define XEM_EIR_RECV_LFIFO_EMPTY_MASK  0x00000020UL	/* Recv length fifo empty */
+#define XEM_EIR_XMIT_LFIFO_FULL_MASK   0x00000040UL	/* Xmit length fifo full */
+#define XEM_EIR_RECV_LFIFO_OVER_MASK   0x00000080UL	/* Recv length fifo
+							 * overrun */
+#define XEM_EIR_RECV_LFIFO_UNDER_MASK  0x00000100UL	/* Recv length fifo
+							 * underrun */
+#define XEM_EIR_XMIT_SFIFO_OVER_MASK   0x00000200UL	/* Xmit status fifo
+							 * overrun */
+#define XEM_EIR_XMIT_SFIFO_UNDER_MASK  0x00000400UL	/* Transmit status fifo
+							 * underrun */
+#define XEM_EIR_XMIT_LFIFO_OVER_MASK   0x00000800UL	/* Transmit length fifo
+							 * overrun */
+#define XEM_EIR_XMIT_LFIFO_UNDER_MASK  0x00001000UL	/* Transmit length fifo
+							 * underrun */
+#define XEM_EIR_XMIT_PAUSE_MASK	       0x00002000UL	/* Transmit pause pkt
+							 * received */
+#define XEM_EIR_RECV_DFIFO_OVER_MASK   0x00004000UL	/* Receive data fifo
+							 * overrun */
+#define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL	/* Receive missed frame
+							 * error */
+#define XEM_EIR_RECV_COLLISION_MASK    0x00010000UL	/* Receive collision
+							 * error */
+#define XEM_EIR_RECV_FCS_ERROR_MASK    0x00020000UL	/* Receive FCS error */
+#define XEM_EIR_RECV_LEN_ERROR_MASK    0x00040000UL	/* Receive length field
+							 * error */
+#define XEM_EIR_RECV_SHORT_ERROR_MASK  0x00080000UL	/* Receive short frame
+							 * error */
+#define XEM_EIR_RECV_LONG_ERROR_MASK   0x00100000UL	/* Receive long frame
+							 * error */
+#define XEM_EIR_RECV_ALIGN_ERROR_MASK  0x00200000UL	/* Receive alignment
+							 * error */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************
+*
+* Low-level driver macros and functions. The list below provides signatures
+* to help the user use the macros.
+*
+* u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset)
+* void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask)
+*
+* void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask)
+* void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr)
+*
+* void XEmac_mEnable(u32 BaseAddress)
+* void XEmac_mDisable(u32 BaseAddress)
+*
+* u32 XEmac_mIsTxDone(u32 BaseAddress)
+* u32 XEmac_mIsRxEmpty(u32 BaseAddress)
+*
+* void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size)
+* int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr)
+*
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mReadReg(BaseAddress, RegOffset) \
+		    XIo_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \
+		    XIo_Out32((BaseAddress) + (RegOffset), (Data))
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the control register. Use the XEM_ECR_* constants
+* defined above to create the bit-mask to be written to the register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    Mask is the 16-bit value to write to the control register
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mSetControlReg(BaseAddress, Mask) \
+		    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask))
+
+/****************************************************************************/
+/**
+*
+* Set the station address of the EMAC device.
+*
+* @param    BaseAddress is the base address of the device
+* @param    AddressPtr is a pointer to a 6-byte MAC address
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mSetMacAddress(BaseAddress, AddressPtr)		    \
+{								    \
+    u32 MacAddr;						\
+								    \
+    MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1];		    \
+    XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr);		    \
+								    \
+    MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) |   \
+	      ((AddressPtr)[4] << 8) | (AddressPtr)[5];		    \
+								    \
+    XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr);		    \
+}
+
+/****************************************************************************/
+/**
+*
+* Enable the transmitter and receiver. Preserve the contents of the control
+* register.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mEnable(BaseAddress) \
+{ \
+    u32 Control; \
+    Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
+    Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \
+    Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \
+    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
+}
+
+/****************************************************************************/
+/**
+*
+* Disable the transmitter and receiver. Preserve the contents of the control
+* register.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mDisable(BaseAddress) \
+		XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \
+		    XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \
+		    ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Check to see if the transmission is complete.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   TRUE if it is done, or FALSE if it is not.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mIsTxDone(BaseAddress) \
+	     (XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Check to see if the receive FIFO is empty.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   TRUE if it is empty, or FALSE if it is not.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mIsRxEmpty(BaseAddress) \
+	  (!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Reset MII compliant PHY
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mPhyReset(BaseAddress) \
+{ \
+    u32 Control;				    \
+    Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
+    Control &= ~XEM_ECR_PHY_ENABLE_MASK;		\
+    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
+    Control |= XEM_ECR_PHY_ENABLE_MASK;			\
+    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
+}
+
+/************************** Function Prototypes ******************************/
+
+void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size);
+int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr);
+
+#endif				/* end of protection macro */
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_options.c b/u-boot/board/xilinx/xilinx_enet/xemac_options.c
new file mode 100644
index 0000000..1f225f8
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_options.c
@@ -0,0 +1,318 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_options.c
+*
+* Functions in this file handle configuration of the XEmac driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XEM_MAX_IFG         32	/* Maximum Interframe gap value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * A table of options and masks. This table maps the user-visible options with
+ * the control register masks. It is used in Set/GetOptions as an alternative
+ * to a series of if/else pairs. Note that the polled options does not have a
+ * corresponding entry in the control register, so it does not exist in the
+ * table.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionMap;
+
+static OptionMap OptionsTable[] = {
+	{XEM_UNICAST_OPTION, XEM_ECR_UNICAST_ENABLE_MASK},
+	{XEM_BROADCAST_OPTION, XEM_ECR_BROAD_ENABLE_MASK},
+	{XEM_PROMISC_OPTION, XEM_ECR_PROMISC_ENABLE_MASK},
+	{XEM_FDUPLEX_OPTION, XEM_ECR_FULL_DUPLEX_MASK},
+	{XEM_LOOPBACK_OPTION, XEM_ECR_LOOPBACK_MASK},
+	{XEM_MULTICAST_OPTION, XEM_ECR_MULTI_ENABLE_MASK},
+	{XEM_FLOW_CONTROL_OPTION, XEM_ECR_PAUSE_FRAME_MASK},
+	{XEM_INSERT_PAD_OPTION, XEM_ECR_XMIT_PAD_ENABLE_MASK},
+	{XEM_INSERT_FCS_OPTION, XEM_ECR_XMIT_FCS_ENABLE_MASK},
+	{XEM_INSERT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_INSERT_MASK},
+	{XEM_OVWRT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_OVWRT_MASK},
+	{XEM_STRIP_PAD_FCS_OPTION, XEM_ECR_RECV_STRIP_ENABLE_MASK}
+};
+
+#define XEM_NUM_OPTIONS     (sizeof(OptionsTable) / sizeof(OptionMap))
+
+/*****************************************************************************/
+/**
+*
+* Set Ethernet driver/device options.  The device must be stopped before
+* calling this function.  The options are contained within a bit-mask with each
+* bit representing an option (i.e., you can OR the options together). A one (1)
+* in the bit-mask turns an option on, and a zero (0) turns the option off.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param OptionsFlag is a bit-mask representing the Ethernet options to turn on
+*        or off. See xemac.h for a description of the available options.
+*
+* @return
+*
+* - XST_SUCCESS if the options were set successfully
+* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+*
+* @note
+*
+* This function is not thread-safe and makes use of internal resources that are
+* shared between the Start, Stop, and SetOptions functions, so if one task
+* might be setting device options while another is trying to start the device,
+* protection of this shared data (typically using a semaphore) is required.
+*
+******************************************************************************/
+XStatus
+XEmac_SetOptions(XEmac * InstancePtr, u32 OptionsFlag)
+{
+	u32 ControlReg;
+	int Index;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) {
+		if (OptionsFlag & OptionsTable[Index].Option) {
+			ControlReg |= OptionsTable[Index].Mask;	/* turn it on */
+		} else {
+			ControlReg &= ~OptionsTable[Index].Mask;	/* turn it off */
+		}
+	}
+
+	/*
+	 * TODO: need to validate addr-overwrite only if addr-insert?
+	 */
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
+
+	/*
+	 * Check the polled option
+	 */
+	if (OptionsFlag & XEM_POLLED_OPTION) {
+		InstancePtr->IsPolled = TRUE;
+	} else {
+		InstancePtr->IsPolled = FALSE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Ethernet driver/device options. The 32-bit value returned is a bit-mask
+* representing the options.  A one (1) in the bit-mask means the option is on,
+* and a zero (0) means the option is off.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* The 32-bit value of the Ethernet options. The value is a bit-mask
+* representing all options that are currently enabled. See xemac.h for a
+* description of the available options.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+u32
+XEmac_GetOptions(XEmac * InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ControlReg;
+	int Index;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Get the control register to determine which options are currently set.
+	 */
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) {
+		if (ControlReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	if (InstancePtr->IsPolled) {
+		OptionsFlag |= XEM_POLLED_OPTION;
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the Interframe Gap (IFG), which is the time the MAC delays between
+* transmitting frames.  There are two parts required.  The total interframe gap
+* is the total of the two parts.  The values provided for the Part1 and Part2
+* parameters are multiplied by 4 to obtain the bit-time interval. The first
+* part should be the first 2/3 of the total interframe gap. The MAC will reset
+* the interframe gap timer if carrier sense becomes true during the period
+* defined by interframe gap Part1. Part1 may be shorter than 2/3 the total and
+* can be as small as zero. The second part should be the last 1/3 of the total
+* interframe gap, but can be as large as the total interframe gap. The MAC
+* will not reset the interframe gap timer if carrier sense becomes true during
+* the period defined by interframe gap Part2.
+*
+* The device must be stopped before setting the interframe gap.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Part1 is the interframe gap part 1 (which will be multiplied by 4 to
+*        get the bit-time interval).
+* @param Part2 is the interframe gap part 2 (which will be multiplied by 4 to
+*        get the bit-time interval).
+*
+* @return
+*
+* - XST_SUCCESS if the interframe gap was set successfully
+* - XST_DEVICE_IS_STARTED if the device has not been stopped
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2)
+{
+	u32 Ifg;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Part1 < XEM_MAX_IFG);
+	XASSERT_NONVOID(Part2 < XEM_MAX_IFG);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure device has been stopped
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	Ifg = Part1 << XEM_IFGP_PART1_SHIFT;
+	Ifg |= (Part2 << XEM_IFGP_PART2_SHIFT);
+	XIo_Out32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET, Ifg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the interframe gap, parts 1 and 2. See the description of interframe gap
+* above in XEmac_SetInterframeGap().
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Part1Ptr is a pointer to an 8-bit buffer into which the interframe gap
+*        part 1 value will be copied.
+* @param Part2Ptr is a pointer to an 8-bit buffer into which the interframe gap
+*        part 2 value will be copied.
+*
+* @return
+*
+* None. The values of the interframe gap parts are copied into the
+* output parameters.
+*
+******************************************************************************/
+void
+XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr)
+{
+	u32 Ifg;
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(Part1Ptr != NULL);
+	XASSERT_VOID(Part2Ptr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	Ifg = XIo_In32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET);
+	*Part1Ptr = (Ifg & XEM_IFGP_PART1_MASK) >> XEM_IFGP_PART1_SHIFT;
+	*Part2Ptr = (Ifg & XEM_IFGP_PART2_MASK) >> XEM_IFGP_PART2_SHIFT;
+}
diff --git a/u-boot/board/xilinx/xilinx_enet/xemac_polled.c b/u-boot/board/xilinx/xilinx_enet/xemac_polled.c
new file mode 100644
index 0000000..23768bc
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_enet/xemac_polled.c
@@ -0,0 +1,482 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_polled.c
+*
+* Contains functions used when the driver is in polled mode. Use the
+* XEmac_SetOptions() function to put the driver into polled mode.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Send an Ethernet frame in polled mode.  The device/driver must be in polled
+* mode before calling this function. The driver writes the frame directly to
+* the MAC's packet FIFO, then enters a loop checking the device status for
+* completion or error. Statistics are updated if an error occurs. The buffer
+* to be sent must be word-aligned.
+*
+* It is assumed that the upper layer software supplies a correctly formatted
+* Ethernet frame, including the destination and source addresses, the
+* type/length field, and the data field.  It is also assumed that upper layer
+* software does not append FCS at the end of the frame.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BufPtr is a pointer to a word-aligned buffer containing the Ethernet
+*        frame to be sent.
+* @param ByteCount is the size of the Ethernet frame.
+*
+* @return
+*
+* - XST_SUCCESS if the frame was sent successfully
+* - XST_DEVICE_IS_STOPPED if the device has not yet been started
+* - XST_NOT_POLLED if the device is not in polled mode
+* - XST_FIFO_NO_ROOM if there is no room in the EMAC's length FIFO for this frame
+* - XST_FIFO_ERROR if the FIFO was overrun or underrun. This error is critical
+*   and requires the caller to reset the device.
+* - XST_EMAC_COLLISION if the send failed due to excess deferral or late
+*   collision
+*
+* @note
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that transmission is
+* done). If this is of concern to the user, the user should provide protection
+* from this problem - perhaps by using a different timer thread to monitor the
+* PollSend thread. On a 10Mbps MAC, it takes about 1.21 msecs to transmit a
+* maximum size Ethernet frame (1518 bytes). On a 100Mbps MAC, it takes about
+* 121 usecs to transmit a maximum size Ethernet frame.
+*
+* @internal
+*
+* The EMAC uses FIFOs behind its length and status registers. For this reason,
+* it is important to keep the length, status, and data FIFOs in sync when
+* reading or writing to them.
+*
+******************************************************************************/
+XStatus
+XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount)
+{
+	u32 IntrStatus;
+	u32 XmitStatus;
+	XStatus Result;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufPtr != NULL);
+	XASSERT_NONVOID(ByteCount > XEM_HDR_SIZE);	/* send at least 1 byte */
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for polled mode and it is started
+	 */
+	if (!InstancePtr->IsPolled) {
+		return XST_NOT_POLLED;
+	}
+
+	if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STOPPED;
+	}
+
+	/*
+	 * Check for overruns and underruns for the transmit status and length
+	 * FIFOs and make sure the send packet FIFO is not deadlocked. Any of these
+	 * conditions is bad enough that we do not want to continue. The upper layer
+	 * software should reset the device to resolve the error.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+
+	/*
+	 * Overrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			  XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		InstancePtr->Stats.XmitOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Underrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			  XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		InstancePtr->Stats.XmitUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Before writing to the data FIFO, make sure the length FIFO is not
+	 * full.  The data FIFO might not be full yet even though the length FIFO
+	 * is. This avoids an overrun condition on the length FIFO and keeps the
+	 * FIFOs in sync.
+	 */
+	if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
+		/*
+		 * Clear the latched LFIFO_FULL bit so next time around the most
+		 * current status is represented
+		 */
+		XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+				      XEM_EIR_XMIT_LFIFO_FULL_MASK);
+		return XST_FIFO_NO_ROOM;
+	}
+
+	/*
+	 * This is a non-blocking write. The packet FIFO returns an error if there
+	 * is not enough room in the FIFO for this frame.
+	 */
+	Result =
+	    XPacketFifoV100b_Write(&InstancePtr->SendFifo, BufPtr, ByteCount);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	/*
+	 * Loop on the MAC's status to wait for any pause to complete.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+
+	while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
+		IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+		/*
+		   * Clear the pause status from the transmit status register
+		 */
+		XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+				      IntrStatus & XEM_EIR_XMIT_PAUSE_MASK);
+	}
+
+	/*
+	 * Set the MAC's transmit packet length register to tell it to transmit
+	 */
+	XIo_Out32(InstancePtr->BaseAddress + XEM_TPLR_OFFSET, ByteCount);
+
+	/*
+	 * Loop on the MAC's status to wait for the transmit to complete. The
+	 * transmit status is in the FIFO when the XMIT_DONE bit is set.
+	 */
+	do {
+		IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+	}
+	while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0);
+
+	XmitStatus = XIo_In32(InstancePtr->BaseAddress + XEM_TSR_OFFSET);
+
+	InstancePtr->Stats.XmitFrames++;
+	InstancePtr->Stats.XmitBytes += ByteCount;
+
+	/*
+	 * Check for various errors, bump statistics, and return an error status.
+	 */
+
+	/*
+	 * Overrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			  XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		InstancePtr->Stats.XmitOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Underrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			  XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		InstancePtr->Stats.XmitUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Clear the interrupt status register of transmit statuses
+	 */
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+			      IntrStatus & XEM_EIR_XMIT_ALL_MASK);
+
+	/*
+	 * Collision errors are stored in the transmit status register
+	 * instead of the interrupt status register
+	 */
+	if (XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) {
+		InstancePtr->Stats.XmitExcessDeferral++;
+		return XST_EMAC_COLLISION_ERROR;
+	}
+
+	if (XmitStatus & XEM_TSR_LATE_COLLISION_MASK) {
+		InstancePtr->Stats.XmitLateCollisionErrors++;
+		return XST_EMAC_COLLISION_ERROR;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Receive an Ethernet frame in polled mode. The device/driver must be in polled
+* mode before calling this function. The driver receives the frame directly
+* from the MAC's packet FIFO. This is a non-blocking receive, in that if there
+* is no frame ready to be received at the device, the function returns with an
+* error. The MAC's error status is not checked, so statistics are not updated
+* for polled receive. The buffer into which the frame will be received must be
+* word-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BufPtr is a pointer to a word-aligned buffer into which the received
+*        Ethernet frame will be copied.
+* @param ByteCountPtr is both an input and an output parameter. It is a pointer
+*        to a 32-bit word that contains the size of the buffer on entry into the
+*        function and the size the received frame on return from the function.
+*
+* @return
+*
+* - XST_SUCCESS if the frame was sent successfully
+* - XST_DEVICE_IS_STOPPED if the device has not yet been started
+* - XST_NOT_POLLED if the device is not in polled mode
+* - XST_NO_DATA if there is no frame to be received from the FIFO
+* - XST_BUFFER_TOO_SMALL if the buffer to receive the frame is too small for
+*   the frame waiting in the FIFO.
+*
+* @note
+*
+* Input buffer must be big enough to hold the largest Ethernet frame. Buffer
+* must also be 32-bit aligned.
+*
+* @internal
+*
+* The EMAC uses FIFOs behind its length and status registers. For this reason,
+* it is important to keep the length, status, and data FIFOs in sync when
+* reading or writing to them.
+*
+******************************************************************************/
+XStatus
+XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr)
+{
+	XStatus Result;
+	u32 PktLength;
+	u32 IntrStatus;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufPtr != NULL);
+	XASSERT_NONVOID(ByteCountPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for polled mode and it is started
+	 */
+	if (!InstancePtr->IsPolled) {
+		return XST_NOT_POLLED;
+	}
+
+	if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STOPPED;
+	}
+
+	/*
+	 * Make sure the buffer is big enough to hold the maximum frame size.
+	 * We need to do this because as soon as we read the MAC's packet length
+	 * register, which is actually a FIFO, we remove that length from the
+	 * FIFO.  We do not want to read the length FIFO without also reading the
+	 * data FIFO since this would get the FIFOs out of sync.  So we have to
+	 * make this restriction.
+	 */
+	if (*ByteCountPtr < XEM_MAX_FRAME_SIZE) {
+		return XST_BUFFER_TOO_SMALL;
+	}
+
+	/*
+	 * First check for packet FIFO deadlock and return an error if it has
+	 * occurred. A reset by the caller is necessary to correct this problem.
+	 */
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Get the interrupt status to know what happened (whether an error occurred
+	 * and/or whether frames have been received successfully). When clearing the
+	 * intr status register, clear only statuses that pertain to receive.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+			      IntrStatus & XEM_EIR_RECV_ALL_MASK);
+
+	/*
+	 * Check receive errors and bump statistics so the caller will have a clue
+	 * as to why data may not have been received. We continue on if an error
+	 * occurred since there still may be frames that were received successfully.
+	 */
+	if (IntrStatus & (XEM_EIR_RECV_LFIFO_OVER_MASK |
+			  XEM_EIR_RECV_DFIFO_OVER_MASK)) {
+		InstancePtr->Stats.RecvOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+	}
+
+	if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
+		InstancePtr->Stats.RecvUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+	}
+
+	/*
+	 * General receive errors
+	 */
+	if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
+		if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
+			InstancePtr->Stats.RecvMissedFrameErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RMFC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
+			InstancePtr->Stats.RecvCollisionErrors =
+			    XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
+			InstancePtr->Stats.RecvFcsErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RFCSEC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
+			InstancePtr->Stats.RecvLengthFieldErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
+			InstancePtr->Stats.RecvShortErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
+			InstancePtr->Stats.RecvLongErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
+			InstancePtr->Stats.RecvAlignmentErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RAEC_OFFSET);
+		}
+	}
+
+	/*
+	 * Before reading from the length FIFO, make sure the length FIFO is not
+	 * empty. We could cause an underrun error if we try to read from an
+	 * empty FIFO.
+	 */
+	if ((IntrStatus & XEM_EIR_RECV_DONE_MASK) == 0) {
+		return XST_NO_DATA;
+	}
+
+	/*
+	 * Determine, from the MAC, the length of the next packet available
+	 * in the data FIFO (there should be a non-zero length here)
+	 */
+	PktLength = XIo_In32(InstancePtr->BaseAddress + XEM_RPLR_OFFSET);
+	if (PktLength == 0) {
+		return XST_NO_DATA;
+	}
+
+	/*
+	 * Write the RECV_DONE bit in the status register to clear it. This bit
+	 * indicates the RPLR is non-empty, and we know it's set at this point.
+	 * We clear it so that subsequent entry into this routine will reflect the
+	 * current status. This is done because the non-empty bit is latched in the
+	 * IPIF, which means it may indicate a non-empty condition even though
+	 * there is something in the FIFO.
+	 */
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, XEM_EIR_RECV_DONE_MASK);
+
+	/*
+	 * We assume that the MAC never has a length bigger than the largest
+	 * Ethernet frame, so no need to make another check here.
+	 */
+
+	/*
+	 * This is a non-blocking read. The FIFO returns an error if there is
+	 * not at least the requested amount of data in the FIFO.
+	 */
+	Result =
+	    XPacketFifoV100b_Read(&InstancePtr->RecvFifo, BufPtr, PktLength);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	InstancePtr->Stats.RecvFrames++;
+	InstancePtr->Stats.RecvBytes += PktLength;
+
+	*ByteCountPtr = PktLength;
+
+	return XST_SUCCESS;
+}
diff --git a/u-boot/board/xilinx/xilinx_iic/xiic_l.c b/u-boot/board/xilinx/xilinx_iic/xiic_l.c
new file mode 100644
index 0000000..6b78163
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_iic/xiic_l.c
@@ -0,0 +1,484 @@
+/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
+/******************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiic_l.c
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- --- -------  -----------------------------------------------
+* 1.01b jhl 5/13/02  First release
+* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
+*		     interrupt status mask was not being done in the loop such
+*		     that a read would sometimes fail on the last byte because
+*		     the transmit error which should have been ignored was
+*		     being used.  This would leave an extra byte in the FIFO
+*		     and the bus throttled such that the next operation would
+*		     also fail.	 Also updated the receive function to not
+*		     disable the device after the last byte until after the
+*		     bus transitions to not busy which is more consistent
+*		     with the expected behavior.
+* 1.01c ecm 12/05/02 new rev
+* </pre>
+*
+****************************************************************************/
+
+/***************************** Include Files *******************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"
+#include "xiic_l.h"
+
+/************************** Constant Definitions ***************************/
+
+/**************************** Type Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *******************/
+
+
+/******************************************************************************
+*
+* This macro clears the specified interrupt in the IPIF interrupt status
+* register.  It is non-destructive in that the register is read and only the
+* interrupt specified is cleared.  Clearing an interrupt acknowledges it.
+*
+* @param    BaseAddress contains the IPIF registers base address.
+*
+* @param    InterruptMask contains the interrupts to be disabled
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XIic_mClearIisr(u32 BaseAddress,
+*				  u32 InterruptMask);
+*
+******************************************************************************/
+#define XIic_mClearIisr(BaseAddress, InterruptMask)		    \
+    XIIF_V123B_WRITE_IISR((BaseAddress),			    \
+	XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
+
+/******************************************************************************
+*
+* This macro sends the address for a 7 bit address during both read and write
+* operations. It takes care of the details to format the address correctly.
+* This macro is designed to be called internally to the drivers.
+*
+* @param    SlaveAddress contains the address of the slave to send to.
+*
+* @param    Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
+*
+******************************************************************************/
+#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation)	    \
+{									    \
+    u8 LocalAddr = (u8)(SlaveAddress << 1);			    \
+    LocalAddr = (LocalAddr & 0xFE) | (Operation);			    \
+    XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr);		    \
+}
+
+/************************** Function Prototypes ****************************/
+
+static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr,
+			  unsigned ByteCount);
+static unsigned SendData (u32 BaseAddress, u8 * BufferPtr,
+			  unsigned ByteCount);
+
+/************************** Variable Definitions **************************/
+
+
+/****************************************************************************/
+/**
+* Receive data as a master on the IIC bus.  This function receives the data
+* using polled I/O and blocks until the data has been received.	 It only
+* supports 7 bit addressing and non-repeated start modes of operation.	The
+* user is responsible for ensuring the bus is not busy if multiple masters
+* are present on the bus.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    Address contains the 7 bit IIC address of the device to send the
+*	    specified data to.
+* @param    BufferPtr points to the data to be sent.
+* @param    ByteCount is the number of bytes to be sent.
+*
+* @return
+*
+* The number of bytes received.
+*
+* @note
+*
+* None
+*
+******************************************************************************/
+unsigned XIic_Recv (u32 BaseAddress, u8 Address,
+		    u8 * BufferPtr, unsigned ByteCount)
+{
+	u8 CntlReg;
+	unsigned RemainingByteCount;
+
+	/* Tx error is enabled incase the address (7 or 10) has no device to answer
+	 * with Ack. When only one byte of data, must set NO ACK before address goes
+	 * out therefore Tx error must not be enabled as it will go off immediately
+	 * and the Rx full interrupt will be checked.  If full, then the one byte
+	 * was received and the Tx error will be disabled without sending an error
+	 * callback msg.
+	 */
+	XIic_mClearIisr (BaseAddress,
+			 XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
+			 XIIC_INTR_ARB_LOST_MASK);
+
+	/* Set receive FIFO occupancy depth for 1 byte (zero based)
+	 */
+	XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0);
+
+	/* 7 bit slave address, send the address for a read operation
+	 * and set the state to indicate the address has been sent
+	 */
+	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION);
+
+	/* MSMS gets set after putting data in FIFO. Start the master receive
+	 * operation by setting CR Bits MSMS to Master, if the buffer is only one
+	 * byte, then it should not be acknowledged to indicate the end of data
+	 */
+	CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
+	if (ByteCount == 1) {
+		CntlReg |= XIIC_CR_NO_ACK_MASK;
+	}
+
+	/* Write out the control register to start receiving data and call the
+	 * function to receive each byte into the buffer
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
+
+	/* Clear the latched interrupt status for the bus not busy bit which must
+	 * be done while the bus is busy
+	 */
+	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
+
+	/* Try to receive the data from the IIC bus */
+
+	RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount);
+	/*
+	 * The receive is complete, disable the IIC device and return the number of
+	 * bytes that was received
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
+
+	/* Return the number of bytes that was received */
+
+	return ByteCount - RemainingByteCount;
+}
+
+/******************************************************************************
+*
+* Receive the specified data from the device that has been previously addressed
+* on the IIC bus.  This function assumes that the 7 bit address has been sent
+* and it should wait for the transmit of the address to complete.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    BufferPtr points to the buffer to hold the data that is received.
+* @param    ByteCount is the number of bytes to be received.
+*
+* @return
+*
+* The number of bytes remaining to be received.
+*
+* @note
+*
+* This function does not take advantage of the receive FIFO because it is
+* designed for minimal code space and complexity.  It contains loops that
+* that could cause the function not to return if the hardware is not working.
+*
+* This function assumes that the calling function will disable the IIC device
+* after this function returns.
+*
+******************************************************************************/
+static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
+{
+	u8 CntlReg;
+	u32 IntrStatusMask;
+	u32 IntrStatus;
+
+	/* Attempt to receive the specified number of bytes on the IIC bus */
+
+	while (ByteCount > 0) {
+		/* Setup the mask to use for checking errors because when receiving one
+		 * byte OR the last byte of a multibyte message an error naturally
+		 * occurs when the no ack is done to tell the slave the last byte
+		 */
+		if (ByteCount == 1) {
+			IntrStatusMask =
+				XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
+		} else {
+			IntrStatusMask =
+				XIIC_INTR_ARB_LOST_MASK |
+				XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
+		}
+
+		/* Wait for the previous transmit and the 1st receive to complete
+		 * by checking the interrupt status register of the IPIF
+		 */
+		while (1) {
+			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
+			if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
+				break;
+			}
+			/* Check the transmit error after the receive full because when
+			 * sending only one byte transmit error will occur because of the
+			 * no ack to indicate the end of the data
+			 */
+			if (IntrStatus & IntrStatusMask) {
+				return ByteCount;
+			}
+		}
+
+		CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);
+
+		/* Special conditions exist for the last two bytes so check for them
+		 * Note that the control register must be setup for these conditions
+		 * before the data byte which was already received is read from the
+		 * receive FIFO (while the bus is throttled
+		 */
+		if (ByteCount == 1) {
+			/* For the last data byte, it has already been read and no ack
+			 * has been done, so clear MSMS while leaving the device enabled
+			 * so it can get off the IIC bus appropriately with a stop.
+			 */
+			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+				  XIIC_CR_ENABLE_DEVICE_MASK);
+		}
+
+		/* Before the last byte is received, set NOACK to tell the slave IIC
+		 * device that it is the end, this must be done before reading the byte
+		 * from the FIFO
+		 */
+		if (ByteCount == 2) {
+			/* Write control reg with NO ACK allowing last byte to
+			 * have the No ack set to indicate to slave last byte read.
+			 */
+			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+				  CntlReg | XIIC_CR_NO_ACK_MASK);
+		}
+
+		/* Read in data from the FIFO and unthrottle the bus such that the
+		 * next byte is read from the IIC bus
+		 */
+		*BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);
+
+		/* Clear the latched interrupt status so that it will be updated with
+		 * the new state when it changes, this must be done after the receive
+		 * register is read
+		 */
+		XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |
+				 XIIC_INTR_TX_ERROR_MASK |
+				 XIIC_INTR_ARB_LOST_MASK);
+		ByteCount--;
+	}
+
+	/* Wait for the bus to transition to not busy before returning, the IIC
+	 * device cannot be disabled until this occurs.	 It should transition as
+	 * the MSMS bit of the control register was cleared before the last byte
+	 * was read from the FIFO.
+	 */
+	while (1) {
+		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
+			break;
+		}
+	}
+
+	return ByteCount;
+}
+
+/****************************************************************************/
+/**
+* Send data as a master on the IIC bus.	 This function sends the data
+* using polled I/O and blocks until the data has been sent.  It only supports
+* 7 bit addressing and non-repeated start modes of operation.  The user is
+* responsible for ensuring the bus is not busy if multiple masters are present
+* on the bus.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    Address contains the 7 bit IIC address of the device to send the
+*	    specified data to.
+* @param    BufferPtr points to the data to be sent.
+* @param    ByteCount is the number of bytes to be sent.
+*
+* @return
+*
+* The number of bytes sent.
+*
+* @note
+*
+* None
+*
+******************************************************************************/
+unsigned XIic_Send (u32 BaseAddress, u8 Address,
+		    u8 * BufferPtr, unsigned ByteCount)
+{
+	unsigned RemainingByteCount;
+
+	/* Put the address into the FIFO to be sent and indicate that the operation
+	 * to be performed on the bus is a write operation
+	 */
+	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);
+
+	/* Clear the latched interrupt status so that it will be updated with the
+	 * new state when it changes, this must be done after the address is put
+	 * in the FIFO
+	 */
+	XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
+			 XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
+
+	/* MSMS must be set after putting data into transmit FIFO, indicate the
+	 * direction is transmit, this device is master and enable the IIC device
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+		  XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
+		  XIIC_CR_ENABLE_DEVICE_MASK);
+
+	/* Clear the latched interrupt
+	 * status for the bus not busy bit which must be done while the bus is busy
+	 */
+	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
+
+	/* Send the specified data to the device on the IIC bus specified by the
+	 * the address
+	 */
+	RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);
+
+	/*
+	 * The send is complete, disable the IIC device and return the number of
+	 * bytes that was sent
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
+
+	return ByteCount - RemainingByteCount;
+}
+
+/******************************************************************************
+*
+* Send the specified buffer to the device that has been previously addressed
+* on the IIC bus.  This function assumes that the 7 bit address has been sent
+* and it should wait for the transmit of the address to complete.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    BufferPtr points to the data to be sent.
+* @param    ByteCount is the number of bytes to be sent.
+*
+* @return
+*
+* The number of bytes remaining to be sent.
+*
+* @note
+*
+* This function does not take advantage of the transmit FIFO because it is
+* designed for minimal code space and complexity.  It contains loops that
+* that could cause the function not to return if the hardware is not working.
+*
+******************************************************************************/
+static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
+{
+	u32 IntrStatus;
+
+	/* Send the specified number of bytes in the specified buffer by polling
+	 * the device registers and blocking until complete
+	 */
+	while (ByteCount > 0) {
+		/* Wait for the transmit to be empty before sending any more data
+		 * by polling the interrupt status register
+		 */
+		while (1) {
+			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
+
+			if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
+					  XIIC_INTR_ARB_LOST_MASK |
+					  XIIC_INTR_BNB_MASK)) {
+				return ByteCount;
+			}
+
+			if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
+				break;
+			}
+		}
+		/* If there is more than one byte to send then put the next byte to send
+		 * into the transmit FIFO
+		 */
+		if (ByteCount > 1) {
+			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
+				  *BufferPtr++);
+		} else {
+			/* Set the stop condition before sending the last byte of data so that
+			 * the stop condition will be generated immediately following the data
+			 * This is done by clearing the MSMS bit in the control register.
+			 */
+			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+				  XIIC_CR_ENABLE_DEVICE_MASK |
+				  XIIC_CR_DIR_IS_TX_MASK);
+
+			/* Put the last byte to send in the transmit FIFO */
+
+			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
+				  *BufferPtr++);
+		}
+
+		/* Clear the latched interrupt status register and this must be done after
+		 * the transmit FIFO has been written to or it won't clear
+		 */
+		XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
+
+		/* Update the byte count to reflect the byte sent and clear the latched
+		 * interrupt status so it will be updated for the new state
+		 */
+		ByteCount--;
+	}
+
+	/* Wait for the bus to transition to not busy before returning, the IIC
+	 * device cannot be disabled until this occurs.
+	 * Note that this is different from a receive operation because the stop
+	 * condition causes the bus to go not busy.
+	 */
+	while (1) {
+		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
+			break;
+		}
+	}
+
+	return ByteCount;
+}
diff --git a/u-boot/board/xilinx/xilinx_iic/xiic_l.h b/u-boot/board/xilinx/xilinx_iic/xiic_l.h
new file mode 100644
index 0000000..a2c4c49
--- /dev/null
+++ b/u-boot/board/xilinx/xilinx_iic/xiic_l.h
@@ -0,0 +1,150 @@
+/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
+/*****************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xiic_l.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  High-level driver functions
+* are defined in xiic.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  05/07/02 First release
+* 1.01c ecm  12/05/02 new rev
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XIIC_L_H /* prevent circular inclusions */
+#define XIIC_L_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions ****************************/
+
+#define XIIC_MSB_OFFSET		       3
+
+#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
+
+/*
+ * Register offsets in bytes from RegisterBase. Three is added to the
+ * base offset to access LSB (IBM style) of the word
+ */
+#define XIIC_CR_REG_OFFSET   0x00+XIIC_REG_OFFSET   /* Control Register	  */
+#define XIIC_SR_REG_OFFSET   0x04+XIIC_REG_OFFSET   /* Status Register	  */
+#define XIIC_DTR_REG_OFFSET  0x08+XIIC_REG_OFFSET   /* Data Tx Register	  */
+#define XIIC_DRR_REG_OFFSET  0x0C+XIIC_REG_OFFSET   /* Data Rx Register	  */
+#define XIIC_ADR_REG_OFFSET  0x10+XIIC_REG_OFFSET   /* Address Register	  */
+#define XIIC_TFO_REG_OFFSET  0x14+XIIC_REG_OFFSET   /* Tx FIFO Occupancy  */
+#define XIIC_RFO_REG_OFFSET  0x18+XIIC_REG_OFFSET   /* Rx FIFO Occupancy  */
+#define XIIC_TBA_REG_OFFSET  0x1C+XIIC_REG_OFFSET   /* 10 Bit Address reg */
+#define XIIC_RFD_REG_OFFSET  0x20+XIIC_REG_OFFSET   /* Rx FIFO Depth reg  */
+
+/* Control Register masks */
+
+#define XIIC_CR_ENABLE_DEVICE_MASK	  0x01	/* Device enable = 1	  */
+#define XIIC_CR_TX_FIFO_RESET_MASK	  0x02	/* Transmit FIFO reset=1  */
+#define XIIC_CR_MSMS_MASK		  0x04	/* Master starts Txing=1  */
+#define XIIC_CR_DIR_IS_TX_MASK		  0x08	/* Dir of tx. Txing=1	  */
+#define XIIC_CR_NO_ACK_MASK		  0x10	/* Tx Ack. NO ack = 1	  */
+#define XIIC_CR_REPEATED_START_MASK	  0x20	/* Repeated start = 1	  */
+#define XIIC_CR_GENERAL_CALL_MASK	  0x40	/* Gen Call enabled = 1	  */
+
+/* Status Register masks */
+
+#define XIIC_SR_GEN_CALL_MASK		  0x01	/* 1=a mstr issued a GC	  */
+#define XIIC_SR_ADDR_AS_SLAVE_MASK	  0x02	/* 1=when addr as slave	  */
+#define XIIC_SR_BUS_BUSY_MASK		  0x04	/* 1 = bus is busy	  */
+#define XIIC_SR_MSTR_RDING_SLAVE_MASK	  0x08	/* 1=Dir: mstr <-- slave  */
+#define XIIC_SR_TX_FIFO_FULL_MASK	  0x10	/* 1 = Tx FIFO full	  */
+#define XIIC_SR_RX_FIFO_FULL_MASK	  0x20	/* 1 = Rx FIFO full	  */
+#define XIIC_SR_RX_FIFO_EMPTY_MASK	  0x40	/* 1 = Rx FIFO empty	  */
+
+/* IPIF Interrupt Status Register masks	   Interrupt occurs when...	  */
+
+#define XIIC_INTR_ARB_LOST_MASK		  0x01	/* 1 = arbitration lost	  */
+#define XIIC_INTR_TX_ERROR_MASK		  0x02	/* 1=Tx error/msg complete*/
+#define XIIC_INTR_TX_EMPTY_MASK		  0x04	/* 1 = Tx FIFO/reg empty  */
+#define XIIC_INTR_RX_FULL_MASK		  0x08	/* 1=Rx FIFO/reg=OCY level*/
+#define XIIC_INTR_BNB_MASK		  0x10	/* 1 = Bus not busy	  */
+#define XIIC_INTR_AAS_MASK		  0x20	/* 1 = when addr as slave */
+#define XIIC_INTR_NAAS_MASK		  0x40	/* 1 = not addr as slave  */
+#define XIIC_INTR_TX_HALF_MASK		  0x80	/* 1 = TX FIFO half empty */
+
+/* IPIF Device Interrupt Register masks */
+
+#define XIIC_IPIF_IIC_MASK	    0x00000004UL    /* 1=inter enabled */
+#define XIIC_IPIF_ERROR_MASK	    0x00000001UL    /* 1=inter enabled */
+#define XIIC_IPIF_INTER_ENABLE_MASK  (XIIC_IPIF_IIC_MASK |  \
+				      XIIC_IPIF_ERROR_MASK)
+
+#define XIIC_TX_ADDR_SENT	      0x00
+#define XIIC_TX_ADDR_MSTR_RECV_MASK   0x02
+
+/* The following constants specify the depth of the FIFOs */
+
+#define IIC_RX_FIFO_DEPTH	  16   /* Rx fifo capacity		 */
+#define IIC_TX_FIFO_DEPTH	  16   /* Tx fifo capacity		 */
+
+/* The following constants specify groups of interrupts that are typically
+ * enabled or disables at the same time
+ */
+#define XIIC_TX_INTERRUPTS					    \
+	    (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK |    \
+	     XIIC_INTR_TX_HALF_MASK)
+
+#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
+
+/* The following constants are used with the following macros to specify the
+ * operation, a read or write operation.
+ */
+#define XIIC_READ_OPERATION  1
+#define XIIC_WRITE_OPERATION 0
+
+/* The following constants are used with the transmit FIFO fill function to
+ * specify the role which the IIC device is acting as, a master or a slave.
+ */
+#define XIIC_MASTER_ROLE     1
+#define XIIC_SLAVE_ROLE	     0
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+unsigned XIic_Recv(u32 BaseAddress, u8 Address,
+		   u8 *BufferPtr, unsigned ByteCount);
+
+unsigned XIic_Send(u32 BaseAddress, u8 Address,
+		   u8 *BufferPtr, unsigned ByteCount);
+
+#endif		  /* end of protection macro */
diff --git a/u-boot/board/xm250/Makefile b/u-boot/board/xm250/Makefile
new file mode 100644
index 0000000..4e86cc2
--- /dev/null
+++ b/u-boot/board/xm250/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= xm250.o flash.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/xm250/flash.c b/u-boot/board/xm250/flash.c
new file mode 100644
index 0000000..b02149c
--- /dev/null
+++ b/u-boot/board/xm250/flash.c
@@ -0,0 +1,536 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x00890089
+#define INTEL_ALT     0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE   0x00200020
+#define INTEL_CLEAR   0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS  0x00700070
+#define INTEL_READID  0x00900090
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK       0x00800080
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	reset_timer_masked ();
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				reset_timer_masked ();
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+				{
+					if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/u-boot/board/xm250/xm250.c b/u-boot/board/xm250/xm250.c
new file mode 100644
index 0000000..3188cf2
--- /dev/null
+++ b/u-boot/board/xm250/xm250.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/* local prototypes */
+
+inline void sleep (int i);
+
+inline void
+/**********************************************************/
+sleep (int i)
+/**********************************************************/
+{
+	while (i--) {
+		udelay (1000000);
+	}
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of MicroSys XM250 */
+	gd->bd->bi_arch_number = MACH_TYPE_XM250;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/u-boot/board/zeus/Makefile b/u-boot/board/zeus/Makefile
new file mode 100644
index 0000000..1ed0265
--- /dev/null
+++ b/u-boot/board/zeus/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o update.o
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/zeus/update.c b/u-boot/board/zeus/update.c
new file mode 100644
index 0000000..141f14b
--- /dev/null
+++ b/u-boot/board/zeus/update.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <i2c.h>
+
+#if defined(CONFIG_ZEUS)
+
+u8 buf_zeus_ce[] = {
+/*00    01    02    03    04    05    06    07 */
+  0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08    09    0a    0b    0c    0d    0e    0f */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10    11    12    13    14    15    16    17 */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18    19    1a    1b    1c    1d    1e    1f */
+  0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
+
+u8 buf_zeus_pe[] = {
+
+/* CPU_CLOCK_DIV 1    = 00
+   CPU_PLB_FREQ_DIV 3 = 10
+   OPB_PLB_FREQ_DIV 2 = 01
+   EBC_PLB_FREQ_DIV 2 = 00
+   MAL_PLB_FREQ_DIV 1 = 00
+   PCI_PLB_FRQ_DIV 3  = 10
+   PLL_PLLOUTA        = IS SET
+   PLL_OPERATING      = IS NOT SET
+   PLL_FDB_MUL 10     = 1010
+   PLL_FWD_DIV_A 3    = 101
+   PLL_FWD_DIV_B 3    = 101
+   TUNE               = 0x2be */
+/*00    01    02    03    04    05    06    07 */
+  0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08    09    0a    0b    0c    0d    0e    0f */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10    11    12    13    14    15    16    17 */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18    19    1a    1b    1c    1d    1e    1f */
+  0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
+
+static int update_boot_eeprom(void)
+{
+	u32 len = 0x20;
+	u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR;
+	u8 *pbuf;
+	u8 base;
+	int i;
+
+	if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) {
+		pbuf = buf_zeus_pe;
+		base = 0x40;
+	} else {
+		pbuf = buf_zeus_ce;
+		base = 0x00;
+	}
+
+	for (i = 0; i < len; i++, base++) {
+		if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
+			printf("i2c_write fail\n");
+			return 1;
+		}
+		udelay(11000);
+	}
+
+	return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
+{
+	return update_boot_eeprom();
+}
+
+U_BOOT_CMD (
+	update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+	"update boot eeprom content",
+	""
+);
+
+#endif
diff --git a/u-boot/board/zeus/zeus.c b/u-boot/board/zeus/zeus.c
new file mode 100644
index 0000000..7e33d3f
--- /dev/null
+++ b/u-boot/board/zeus/zeus.c
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REBOOT_MAGIC	0x07081967
+#define REBOOT_NOP	0x00000000
+#define REBOOT_DO_POST	0x00000001
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern env_t *env_ptr;
+extern uchar default_environment[];
+
+ulong flash_get_size(ulong base, int banknum);
+void env_crc_update(void);
+
+static u32 start_time;
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 */
+	mtdcr(CPC0_PCI, CPC0_PCI_SPE);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 pbcr;
+	int size_val = 0;
+	u32 post_magic;
+	u32 post_val;
+
+	post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
+	post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
+	if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
+		/*
+		 * Set special bootline bootparameter to pass this POST boot
+		 * mode to Linux to reset the username/password
+		 */
+		setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
+
+		/*
+		 * Normally don't run POST tests, only when enabled
+		 * via the sw-reset button. So disable further tests
+		 * upon next bootup here.
+		 */
+		out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
+	} else {
+		/*
+		 * Only run POST when initiated via the sw-reset button mechanism
+		 */
+		post_word_store(0);
+	}
+
+	/*
+	 * Get current time
+	 */
+	start_time = get_timer(0);
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	mfebc(PB0CR, pbcr);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtebc(PB0CR, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Zeus-");
+
+	if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE))
+		puts("PE");
+	else
+		puts("CE");
+
+	puts(" of BulletEndPoint");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	/* both LED's off */
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
+	udelay(10000);
+	/* and on again */
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1);
+
+	return (0);
+}
+
+static int default_env_var(char *buf, char *var)
+{
+	char *ptr;
+	char *val;
+
+	/*
+	 * Find env variable
+	 */
+	ptr = strstr(buf + 4, var);
+	if (ptr == NULL) {
+		printf("ERROR: %s not found!\n", var);
+		return -1;
+	}
+	ptr += strlen(var) + 1;
+
+	/*
+	 * Now the ethaddr needs to be updated in the "normal"
+	 * environment storage -> redundant flash.
+	 */
+	val = ptr;
+	setenv(var, val);
+	printf("Updated %s from eeprom to %s!\n", var, val);
+
+	return 0;
+}
+
+static int restore_default(void)
+{
+	char *buf;
+	char *buf_save;
+	u32 crc;
+
+	set_default_env("");
+
+	gd->env_valid = 1;
+
+	/*
+	 * Read board specific values from I2C EEPROM
+	 * and set env variables accordingly
+	 * -> ethaddr, eth1addr, serial#
+	 */
+	buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+	if (buf == NULL) {
+		printf("ERROR: malloc() failed\n");
+		return -1;
+	}
+	if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+			(u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
+		puts("\nError reading EEPROM!\n");
+	} else {
+		crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
+		if (crc != *(u32 *)buf) {
+			printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf);
+			return -1;
+		}
+
+		default_env_var(buf, "ethaddr");
+		buf += 8 + 18;
+		default_env_var(buf, "eth1addr");
+		buf += 9 + 18;
+		default_env_var(buf, "serial#");
+	}
+
+	/*
+	 * Finally save updated env variables back to flash
+	 */
+	saveenv();
+
+	free(buf_save);
+
+	return 0;
+}
+
+int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *buf;
+	char *buf_save;
+	char str[32];
+	u32 crc;
+	char var[32];
+
+	if (argc < 4) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+	memset(buf, 0, FACTORY_RESET_ENV_SIZE);
+
+	strcpy(var, "ethaddr");
+	printf("Setting %s to %s\n", var, argv[1]);
+	sprintf(str, "%s=%s", var, argv[1]);
+	strcpy(buf + 4, str);
+	buf += strlen(str) + 1;
+
+	strcpy(var, "eth1addr");
+	printf("Setting %s to %s\n", var, argv[2]);
+	sprintf(str, "%s=%s", var, argv[2]);
+	strcpy(buf + 4, str);
+	buf += strlen(str) + 1;
+
+	strcpy(var, "serial#");
+	printf("Setting %s to %s\n", var, argv[3]);
+	sprintf(str, "%s=%s", var, argv[3]);
+	strcpy(buf + 4, str);
+
+	crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
+	*(u32 *)buf_save = crc;
+
+	if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+			 (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
+		puts("\nError writing EEPROM!\n");
+		return -1;
+	}
+
+	free(buf_save);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	setdef,	4,	1,	do_set_default,
+	"write board-specific values to EEPROM (ethaddr...)",
+	"ethaddr eth1addr serial#\n    - write board-specific values to EEPROM"
+	);
+
+static inline int sw_reset_pressed(void)
+{
+	return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET));
+}
+
+int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
+{
+	int delta;
+	int count = 0;
+	int post = 0;
+	int factory_reset = 0;
+
+	if (!sw_reset_pressed()) {
+		printf("SW-Reset already high (Button released)\n");
+		printf("-> No action taken!\n");
+		return 0;
+	}
+
+	printf("Waiting for SW-Reset button to be released.");
+
+	while (1) {
+		delta = get_timer(start_time);
+		if (!sw_reset_pressed())
+			break;
+
+		if ((delta > CONFIG_SYS_TIME_POST) && !post) {
+			printf("\nWhen released now, POST tests will be started.");
+			gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
+			post = 1;
+		}
+
+		if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) {
+			printf("\nWhen released now, factory default values"
+			       " will be restored.");
+			gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
+			factory_reset = 1;
+		}
+
+		udelay(1000);
+		if (!(count++ % 1000))
+			printf(".");
+	}
+
+
+	printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
+
+	if (delta > CONFIG_SYS_TIME_FACTORY_RESET) {
+		printf("Starting factory reset value restoration...\n");
+
+		/*
+		 * Restore default setting
+		 */
+		restore_default();
+
+		/*
+		 * Reset the board for default to become valid
+		 */
+		do_reset(NULL, 0, 0, NULL);
+
+		return 0;
+	}
+
+	if (delta > CONFIG_SYS_TIME_POST) {
+		printf("Starting POST configuration...\n");
+
+		/*
+		 * Enable POST upon next bootup
+		 */
+		out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC);
+		out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST);
+		post_bootmode_init();
+
+		/*
+		 * Reset the logbuffer for a clean start
+		 */
+		logbuff_reset();
+
+		do_reset(NULL, 0, 0, NULL);
+
+		return 0;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	chkreset, 1, 1, do_chkreset,
+	"Check for status of SW-reset button and act accordingly",
+	""
+);
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	u32 post_magic;
+	u32 post_val;
+
+	post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
+	post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
+
+	if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
+		return 1;
+	else
+		return 0;
+}
+#endif /* CONFIG_POST */
diff --git a/u-boot/board/zipitz2/Makefile b/u-boot/board/zipitz2/Makefile
new file mode 100644
index 0000000..16eea07
--- /dev/null
+++ b/u-boot/board/zipitz2/Makefile
@@ -0,0 +1,52 @@
+
+#
+# Copyright (C) 2009
+# Marek Vasut <marek.vasut@gmail.com>
+#
+# Heavily based on pxa255_idp platform
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= zipitz2.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/zipitz2/u-boot.lds b/u-boot/board/zipitz2/u-boot.lds
new file mode 100644
index 0000000..fb4358b
--- /dev/null
+++ b/u-boot/board/zipitz2/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/u-boot/board/zipitz2/zipitz2.c b/u-boot/board/zipitz2/zipitz2.c
new file mode 100644
index 0000000..9e6a0d5
--- /dev/null
+++ b/u-boot/board/zipitz2/zipitz2.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2009
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Heavily based on pxa255_idp platform
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/hardware.h>
+#include <spi.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef	CONFIG_CMD_SPI
+void lcd_start(void);
+#else
+inline void lcd_start(void) {};
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of Z2 */
+	gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* Enable LCD */
+	lcd_start();
+
+	return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+	return &serial_stuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef	CONFIG_CMD_SPI
+
+struct {
+	unsigned char	reg;
+	unsigned short	data;
+	unsigned char	mdelay;
+} lcd_data[] = {
+	{ 0x07,	0x0000,	0 },
+	{ 0x13,	0x0000,	10 },
+	{ 0x11,	0x3004,	0 },
+	{ 0x14,	0x200F,	0 },
+	{ 0x10,	0x1a20,	0 },
+	{ 0x13,	0x0040,	50 },
+	{ 0x13,	0x0060,	0 },
+	{ 0x13,	0x0070,	200 },
+	{ 0x01,	0x0127,	0 },
+	{ 0x02,	0x0700,	0 },
+	{ 0x03,	0x1030,	0 },
+	{ 0x08,	0x0208,	0 },
+	{ 0x0B,	0x0620,	0 },
+	{ 0x0C,	0x0110,	0 },
+	{ 0x30,	0x0120,	0 },
+	{ 0x31,	0x0127,	0 },
+	{ 0x32,	0x0000,	0 },
+	{ 0x33,	0x0503,	0 },
+	{ 0x34,	0x0727,	0 },
+	{ 0x35,	0x0124,	0 },
+	{ 0x36,	0x0706,	0 },
+	{ 0x37,	0x0701,	0 },
+	{ 0x38,	0x0F00,	0 },
+	{ 0x39,	0x0F00,	0 },
+	{ 0x40,	0x0000,	0 },
+	{ 0x41,	0x0000,	0 },
+	{ 0x42,	0x013f,	0 },
+	{ 0x43,	0x0000,	0 },
+	{ 0x44,	0x013f,	0 },
+	{ 0x45,	0x0000,	0 },
+	{ 0x46,	0xef00,	0 },
+	{ 0x47,	0x013f,	0 },
+	{ 0x48,	0x0000,	0 },
+	{ 0x07,	0x0015,	30 },
+	{ 0x07,	0x0017,	0 },
+	{ 0x20,	0x0000,	0 },
+	{ 0x21,	0x0000,	0 },
+	{ 0x22,	0x0000,	0 },
+};
+
+void zipitz2_spi_sda(int set)
+{
+	/* GPIO 13 */
+	if (set)
+		writel((1 << 13), GPSR0);
+	else
+		writel((1 << 13), GPCR0);
+}
+
+void zipitz2_spi_scl(int set)
+{
+	/* GPIO 22 */
+	if (set)
+		writel((1 << 22), GPCR0);
+	else
+		writel((1 << 22), GPSR0);
+}
+
+unsigned char zipitz2_spi_read(void)
+{
+	/* GPIO 40 */
+	return !!(readl(GPLR1) & (1 << 8));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* Always valid */
+	return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* GPIO 88 low */
+	writel((1 << 24), GPCR2);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	/* GPIO 88 high */
+	writel((1 << 24), GPSR2);
+
+}
+
+void lcd_start(void)
+{
+	int i;
+	unsigned char reg[3] = { 0x74, 0x00, 0 };
+	unsigned char data[3] = { 0x76, 0, 0 };
+	unsigned char dummy[3] = { 0, 0, 0 };
+
+	/* PWM2 AF */
+	writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
+	/* Enable clock to all PWM */
+	writel(readl(CKEN) | 0x3, CKEN);
+	/* Configure PWM2 */
+	writel(0x4f, PWM_CTRL2);
+	writel(0x2ff, PWM_PWDUTY2);
+	writel(792, PWM_PERVAL2);
+
+	/* Toggle the reset pin to reset the LCD */
+	writel((1 << 19), GPSR0);
+	udelay(100000);
+	writel((1 << 19), GPCR0);
+	udelay(20000);
+	writel((1 << 19), GPSR0);
+	udelay(20000);
+
+	/* Program the LCD init sequence */
+	for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
+		reg[0] = 0x74;
+		reg[1] = 0x0;
+		reg[2] = lcd_data[i].reg;
+		spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+		data[0] = 0x76;
+		data[1] = lcd_data[i].data >> 8;
+		data[2] = lcd_data[i].data & 0xff;
+		spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+		if (lcd_data[i].mdelay)
+			udelay(lcd_data[i].mdelay * 1000);
+	}
+
+	writel((1 << 11), GPSR0);
+}
+#endif
diff --git a/u-boot/board/zpc1900/Makefile b/u-boot/board/zpc1900/Makefile
new file mode 100644
index 0000000..9079aad
--- /dev/null
+++ b/u-boot/board/zpc1900/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/zpc1900/zpc1900.c b/u-boot/board/zpc1900/zpc1900.c
new file mode 100644
index 0000000..027d566
--- /dev/null
+++ b/u-boot/board/zpc1900/zpc1900.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003-2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB  */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB  */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC  */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   0,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER  */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN  */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER  */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL    */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS    */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN  */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN CLSN */
+	/* PC28 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC21 */
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC20 */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RENA */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT972 MDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT972 MDIO */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD  */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD  */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   0,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
+void *nvram_read(void *dest, long src, size_t count)
+{
+	return memcpy(dest, (const void *)src, count);
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	vu_char     *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555);
+	vu_char     *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA);
+	vu_char     *d = (vu_char *)dest;
+	const uchar *s = (const uchar *)src;
+
+	/* Unprotect the EEPROM */
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0x80;
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0x20;
+	udelay(10000);
+
+	/* Write the data to the EEPROM */
+	while (count--) {
+		*d++ = *s++;
+		while (*(d - 1) != *(s - 1))
+			/* wait */;
+	}
+
+	/* Protect the EEPROM */
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0xA0;
+	udelay(10000);
+}
+#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */
+
+phys_size_t initdram(int board_type)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr;
+	uchar c = 0xFF;
+	long int msize = CONFIG_SYS_SDRAM_SIZE;
+	int i;
+
+	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
+		immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
+		immap->im_siu_conf.sc_siumcr =
+			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+			| SIUMCR_LBPC01;
+	}
+
+#ifndef CONFIG_SYS_RAMBOOT
+	immap->im_siu_conf.sc_ppc_acr  = 0x03;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifdef CONFIG_SYS_LSDRAM_BASE
+	/*
+	  Initialise local bus SDRAM only if the pins
+	  are configured as local bus pins and not as PCI.
+	*/
+	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
+		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
+		memctl->memc_or4   = CONFIG_SYS_LSDRAM_OR;
+		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BR;
+		ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN;
+	}
+#endif /* CONFIG_SYS_LSDRAM_BASE */
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or2  = CONFIG_SYS_PSDRAM_OR;
+	memctl->memc_br2  = CONFIG_SYS_PSDRAM_BR;
+	/*
+	 * The mode data for Mode Register Write command must appear on
+	 * the address lines during a mode-set cycle. It is driven by
+	 * the memory controller, in single PowerQUICC II mode,
+	 * according to PSDMR[CL] and PSDMR[BL] fields. In
+	 * 60x-compatible mode, software must drive the correct value on
+	 * the address lines. BL=0 because for 64-bit port size burst
+	 * length must be 4.
+	 */
+	ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE |
+			      ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+
+	printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
+	return 0;
+}
diff --git a/u-boot/board/zylonite/Makefile b/u-boot/board/zylonite/Makefile
new file mode 100644
index 0000000..3e57e49
--- /dev/null
+++ b/u-boot/board/zylonite/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= zylonite.o nand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/zylonite/config.mk b/u-boot/board/zylonite/config.mk
new file mode 100644
index 0000000..954f46e
--- /dev/null
+++ b/u-boot/board/zylonite/config.mk
@@ -0,0 +1,4 @@
+#CONFIG_SYS_TEXT_BASE = 0x0
+#CONFIG_SYS_TEXT_BASE = 0xa1700000
+#CONFIG_SYS_TEXT_BASE = 0xa3080000
+CONFIG_SYS_TEXT_BASE = 0xa3008000
diff --git a/u-boot/board/zylonite/flash.c b/u-boot/board/zylonite/flash.c
new file mode 100644
index 0000000..5ba84c6
--- /dev/null
+++ b/u-boot/board/zylonite/flash.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#if 0
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+#endif
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/u-boot/board/zylonite/lowlevel_init.S b/u-boot/board/zylonite/lowlevel_init.S
new file mode 100644
index 0000000..6f2ad23
--- /dev/null
+++ b/u-boot/board/zylonite/lowlevel_init.S
@@ -0,0 +1,373 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+	mrc	p15,0,\reg,c2,c0,0
+	mov	\reg,\reg
+	sub	pc,pc,#4
+.endm
+
+
+.macro wait time
+	ldr		r2, =OSCR
+	mov		r3, #0
+	str		r3, [r2]
+0:
+	ldr		r3, [r2]
+	cmp		r3, \time
+	bls		0b
+.endm
+
+/*
+ *	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Set up GPIO pins first ----------------------------------------- */
+	mov	 r10, lr
+
+	/*  Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
+	ldr		r0, =0x40E10438 @ GPIO41 FFRXD
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E1043C @ GPIO42 FFTXD
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E10440 @ GPIO43 FFCTS
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E10444 @ GPIO 44 FFDCD
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E10448 @ GPIO 45 FFDSR
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E1044C @ GPIO 46 FFRI
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E10450 @ GPIO 47 FFDTR
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	ldr		r0, =0x40E10454 @ GPIO 48
+	ldr		r1, =0x802
+	str		r1, [r0]
+
+	/* tebrandt - ASCR, clear the RDH bit */
+	ldr		r0, =ASCR
+	ldr		r1, [r0]
+	bic		r1, r1, #0x80000000
+	str		r1, [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	/* mk:	 replaced with wait macro */
+/*	ldr r3, =OSCR			/\* reset the OS Timer Count to zero *\/ */
+/*	mov r2, #0 */
+/*	str r2, [r3] */
+/*	ldr r4, =0x300			/\* really 0x2E1 is about 200usec,   *\/ */
+/*					/\* so 0x300 should be plenty	     *\/ */
+/* 1: */
+/*	ldr r2, [r3] */
+/*	cmp r4, r2 */
+/*	bgt 1b */
+	wait #0x300
+
+mem_init:
+
+	/* configure the MEMCLKCFG register */
+	ldr		r1, =MEMCLKCFG
+	ldr		r2, =0x00010001
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+	/* set CSADRCFG[0] to data flash SRAM mode */
+	ldr		r1, =CSADRCFG0
+	ldr		r2, =0x00320809
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+	/* set CSADRCFG[1] to data flash SRAM mode */
+	ldr		r1, =CSADRCFG1
+	ldr		r2, =0x00320809
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+	/* set MSC 0 register for SRAM memory */
+	ldr		r1, =MSC0
+	ldr		r2, =0x11191119
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+	/* set CSADRCFG[2] to data flash SRAM mode */
+	ldr		r1, =CSADRCFG2
+	ldr		r2, =0x00320809
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+	/* set CSADRCFG[3] to VLIO mode */
+	ldr		r1, =CSADRCFG3
+	ldr		r2, =0x0032080B
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+	/* set MSC 1 register for VLIO memory */
+	ldr		r1, =MSC1
+	ldr		r2, =0x123C1119
+	str		r2, [r1]	     @ WRITE
+	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
+
+#if 0
+	/* This does not work in Zylonite. -SC */
+	ldr		r0, =0x15fffff0
+	ldr		r1, =0xb10b
+	str		r1, [r0]
+	str		r1, [r0, #4]
+#endif
+
+	/* Configure ACCR Register */
+	ldr		r0, =ACCR		@ ACCR
+	ldr		r1, =0x0180b108
+	str		r1, [r0]
+	ldr		r1, [r0]
+
+	/* Configure MDCNFG Register */
+	ldr		r0, =MDCNFG		@ MDCNFG
+	ldr		r1, =0x403
+	str		r1, [r0]
+	ldr		r1, [r0]
+
+	/* Perform Resistive Compensation by configuring RCOMP register */
+	ldr		r1, =RCOMP		@ RCOMP
+	ldr		r2, =0x000000ff
+	str		r2, [r1]
+	ldr		r2, [r1]
+
+	/* Configure MDMRS Register for SDCS0 */
+	ldr		r1, =MDMRS		@ MDMRS
+	ldr		r2, =0x60000023
+	ldr		r3, [r1]
+	orr		r2, r2, r3
+	str		r2, [r1]
+	ldr		r2, [r1]
+
+	/* Configure MDMRS Register for SDCS1 */
+	ldr		r1, =MDMRS		@ MDMRS
+	ldr		r2, =0xa0000023
+	ldr		r3, [r1]
+	orr		r2, r2, r3
+	str		r2, [r1]
+	ldr		r2, [r1]
+
+	/* Configure MDREFR */
+	ldr		r1, =MDREFR		@ MDREFR
+	ldr		r2, =0x00000006
+	str		r2, [r1]
+	ldr		r2, [r1]
+
+	/* Configure EMPI */
+	ldr		r1, =EMPI		@ EMPI
+	ldr		r2, =0x80000000
+	str		r2, [r1]
+	ldr		r2, [r1]
+
+	/* Hardware DDR Read-Strobe Delay Calibration */
+	ldr		r0, =DDR_HCAL		@ DDR_HCAL
+	ldr		r1, =0x803ffc07	    @ the offset is correct? -SC
+	str		r1, [r0]
+	wait		#5
+	ldr		r1, [r0]
+
+	/* Here we assume the hardware calibration alwasy be successful. -SC */
+	/* Set DMCEN bit in MDCNFG Register */
+	ldr		r0, =MDCNFG		@ MDCNFG
+	ldr		r1, [r0]
+	orr		r1, r1, #0x40000000	@ enable SDRAM for Normal Access
+	str		r1, [r0]
+
+#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
+	/* scrub/init SDRAM if enabled/present */
+/*	ldr	r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */
+/*	ldr	r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */
+/*	mov	r8,r12		 /\* save DRAM size (mk: why???) *\/ */
+	ldr	r8, =0xa0000000	 /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
+	ldr	r9, =0x04000000	 /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
+	mov	r0, #0		 /* scrub with 0x0000:0000 */
+	mov	r1, #0
+	mov	r2, #0
+	mov	r3, #0
+	mov	r4, #0
+	mov	r5, #0
+	mov	r6, #0
+	mov	r7, #0
+10:	/* fastScrubLoop */
+	subs	r9, r9, #32	/* 32 bytes/line */
+	stmia	r8!, {r0-r7}
+	beq	15f
+	b	10b
+#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
+
+15:
+	/* Mask all interrupts */
+	mov	r1, #0
+	mcr	p6, 0, r1, c1, c0, 0	@ ICMR
+
+	/* Disable software and data breakpoints */
+	mov	r0, #0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/* Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init							 */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov	pc, lr
+
+/*
+@********************************************************************************
+@ DDR calibration
+@
+@  This function is used to calibrate DQS delay lines.
+@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+	@ Case 1:	Write the correct delay value once
+	@ Configure DDR_SCAL Register
+	ldr	r0, =DDR_SCAL		@ DDR_SCAL
+q	ldr	r1, =0xaf2f2f2f
+	str	r1, [r0]
+	ldr	r1, [r0]
+*/
+/*	@ Case 2:	Software Calibration
+	@ Write test pattern to memory
+	ldr	r5, =0x0faf0faf		@ Data Pattern
+	ldr	r4, =0xa0000000		@ DDR ram
+	str	r5, [r4]
+
+	mov	r1, =0x0		@ delay count
+	mov	r6, =0x0
+	mov	r7, =0x0
+ddr_loop1:
+	add	r1, r1, =0x1
+	cmp	r1, =0xf
+	ble	end_loop
+	mov	r3, r1
+	mov	r0, r1, lsl #30
+	orr	r3, r3, r0
+	mov	r0, r1, lsl #22
+	orr	r3, r3, r0
+	mov	r0, r1, lsl #14
+	orr	r3, r3, r0
+	orr	r3, r3, =0x80000000
+	ldr	r2, =DDR_SCAL
+	str	r3, [r2]
+
+	ldr	r2, [r4]
+	cmp	r2, r5
+	bne	ddr_loop1
+	mov	r6, r1
+ddr_loop2:
+	add	r1, r1, =0x1
+	cmp	r1, =0xf
+	ble	end_loop
+	mov	r3, r1
+	mov	r0, r1, lsl #30
+	orr	r3, r3, r0
+	mov	r0, r1, lsl #22
+	orr	r3, r3, r0
+	mov	r0, r1, lsl #14
+	orr	r3, r3, r0
+	orr	r3, r3, =0x80000000
+	ldr	r2, =DDR_SCAL
+	str	r3, [r2]
+
+	ldr	r2, [r4]
+	cmp	r2, r5
+	be	ddr_loop2
+	mov	r7, r2
+
+	add	r3, r6, r7
+	lsr	r3, r3, =0x1
+	mov	r0, r1, lsl #30
+	orr	r3, r3, r0
+	mov	r0, r1, lsl #22
+	orr	r3, r3, r0
+	mov	r0, r1, lsl #14
+	orr	r3, r3, r0
+	orr	r3, r3, =0x80000000
+	ldr	r2, =DDR_SCAL
+
+end_loop:
+
+	@ Case 3:	Hardware Calibratoin
+	ldr	r0, =DDR_HCAL		@ DDR_HCAL
+	ldr	r1, =0x803ffc07	    @ the offset is correct? -SC
+	str	r1, [r0]
+	wait	#5
+	ldr	r1, [r0]
+	mov	pc, lr
+*/
diff --git a/u-boot/board/zylonite/nand.c b/u-boot/board/zylonite/nand.c
new file mode 100644
index 0000000..71d18a6
--- /dev/null
+++ b/u-boot/board/zylonite/nand.c
@@ -0,0 +1,562 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CONFIG_SYS_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CONFIG_SYS_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CONFIG_SYS_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr delta_bbt_descr = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern
+};
+
+static struct nand_ecclayout delta_oob = {
+	.eccbytes = 6,
+	.eccpos = {2, 3, 4, 5, 6, 7},
+	.oobfree = { {8, 2}, {12, 4} }
+};
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	return;
+}
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+	if(NDSR & NDSR_RDY)
+		return 1;
+	else
+		return 0;
+	return 0;
+}
+#endif
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	unsigned long bytes_multi = len & 0xfffffffc;
+	unsigned long rest = len & 0x3;
+	unsigned long *long_buf;
+	int i;
+
+	DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
+	if(bytes_multi) {
+		for(i=0; i<bytes_multi; i+=4) {
+			long_buf = (unsigned long*) &buf[i];
+			writel(*long_buf, NDDB);
+		}
+	}
+	if(rest) {
+		printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+	}
+	return;
+}
+
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+	int i=0, j;
+
+	/* we have to be carefull not to overflow the buffer if len is
+	 * not a multiple of 4 */
+	unsigned long bytes_multi = len & 0xfffffffc;
+	unsigned long rest = len & 0x3;
+	unsigned long *long_buf;
+
+	DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+	/* if there are any, first copy multiple of 4 bytes */
+	if(bytes_multi) {
+		for(i=0; i<bytes_multi; i+=4) {
+			long_buf = (unsigned long*) &buf[i];
+			*long_buf = readl(NDDB);
+		}
+	}
+
+	/* ...then the rest */
+	if(rest) {
+		unsigned long rest_data = NDDB;
+		for(j=0;j<rest; j++)
+			buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+	}
+
+	return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+	printf("dfc_read_word: UNIMPLEMENTED.\n");
+	return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
+/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+	unsigned char byte;
+	unsigned long dummy;
+
+	if(bytes_read < 0) {
+		read_buf = readl(NDDB);
+		dummy = readl(NDDB);
+		bytes_read = 0;
+	}
+	byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+	if(bytes_read >= 4)
+		bytes_read = -1;
+
+	DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+	return byte;
+}
+
+/* calculate delta between OSCR values start and now  */
+static unsigned long get_delta(unsigned long start)
+{
+	unsigned long cur = readl(OSCR);
+
+	if(cur < start) /* OSCR overflowed */
+		return (cur + (start^0xffffffff));
+	else
+		return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+	unsigned long start = readl(OSCR);
+	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
+
+	while (get_delta(start) < us) {
+		/* do nothing */
+	}
+}
+
+static void dfc_clear_nddb(void)
+{
+	writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
+	wait_us(CONFIG_SYS_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+	unsigned long ndsr, timeout, start = readl(OSCR);
+
+	if(!event)
+		return 0xff000000;
+	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
+					* OSCR_CLK_FREQ, 1000);
+	else
+		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
+					* OSCR_CLK_FREQ, 1000);
+
+	while(1) {
+		ndsr = readl(NDSR);
+		if(ndsr & event) {
+			writel(readl(NDSR) | event, NDSR);
+			break;
+		}
+		if(get_delta(start) > timeout) {
+			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
+			return 0xff000000;
+		}
+
+	}
+	return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd(void)
+{
+	int retry = 0;
+	unsigned long status;
+
+	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
+		/* Clear NDSR */
+		writel(0xFFF, NDSR);
+
+		/* set NDCR[NDRUN] */
+		if (!(readl(NDCR) & NDCR_ND_RUN))
+			writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
+
+		status = dfc_wait_event(NDSR_WRCMDREQ);
+
+		if(status & NDSR_WRCMDREQ)
+			return;
+
+		DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+		dfc_clear_nddb();
+	}
+	DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
+{
+	unsigned long ndsr=0, event=0;
+	int state = this->state;
+
+	if(state == FL_WRITING) {
+		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+	} else if(state == FL_ERASING) {
+		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+	}
+
+	ndsr = dfc_wait_event(event);
+
+	if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+		return(0x1); /* Status Read error */
+	return 0;
+}
+
+/* cmdfunc send commands to the DFC */
+static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+			int column, int page_addr)
+{
+	/* register struct nand_chip *this = mtd->priv; */
+	unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+	/* clear the ugly byte read buffer */
+	bytes_read = -1;
+	read_buf = 0;
+
+	switch (command) {
+	case NAND_CMD_READ0:
+		DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+		dfc_new_cmd();
+		ndcb0 = (NAND_CMD_READ0 | (4<<16));
+		column >>= 1; /* adjust for 16 bit bus */
+		ndcb1 = (((column>>1) & 0xff) |
+			 ((page_addr<<8) & 0xff00) |
+			 ((page_addr<<8) & 0xff0000) |
+			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+		event = NDSR_RDDREQ;
+		goto write_cmd;
+	case NAND_CMD_READ1:
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+		goto end;
+	case NAND_CMD_READOOB:
+		DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+		goto end;
+	case NAND_CMD_READID:
+		dfc_new_cmd();
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+		ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+		event = NDSR_RDDREQ;
+		goto write_cmd;
+	case NAND_CMD_PAGEPROG:
+		/* sent as a multicommand in NAND_CMD_SEQIN */
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+		goto end;
+	case NAND_CMD_ERASE1:
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+		dfc_new_cmd();
+		ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
+		ndcb1 = (page_addr & 0x00ffffff);
+		goto write_cmd;
+	case NAND_CMD_ERASE2:
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+		goto end;
+	case NAND_CMD_SEQIN:
+		/* send PAGE_PROG command(0x1080) */
+		dfc_new_cmd();
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+		ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+		column >>= 1; /* adjust for 16 bit bus */
+		ndcb1 = (((column>>1) & 0xff) |
+			 ((page_addr<<8) & 0xff00) |
+			 ((page_addr<<8) & 0xff0000) |
+			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+		event = NDSR_WRDREQ;
+		goto write_cmd;
+	case NAND_CMD_STATUS:
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+		dfc_new_cmd();
+		ndcb0 = NAND_CMD_STATUS | (4<<21);
+		event = NDSR_RDDREQ;
+		goto write_cmd;
+	case NAND_CMD_RESET:
+		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+		ndcb0 = NAND_CMD_RESET | (5<<21);
+		event = NDSR_CS0_CMDD;
+		goto write_cmd;
+	default:
+		printk("dfc_cmdfunc: error, unsupported command.\n");
+		goto end;
+	}
+
+ write_cmd:
+	writel(ndcb0, NDCB0);
+	writel(ndcb1, NDCB0);
+	writel(ndcb2, NDCB0);
+
+	/*  wait_event: */
+	dfc_wait_event(event);
+ end:
+	return;
+}
+
+static void dfc_gpio_init(void)
+{
+	DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+	/* no idea what is done here, see zylonite.c */
+	writel(0x1, GPIO4);
+
+	writel(0x00000001, DF_ALE_nWE1);
+	writel(0x00000001, DF_ALE_nWE2);
+	writel(0x00000001, DF_nCS0);
+	writel(0x00000001, DF_nCS1);
+	writel(0x00000001, DF_nWE);
+	writel(0x00000001, DF_nRE);
+	writel(0x00000001, DF_IO0);
+	writel(0x00000001, DF_IO8);
+	writel(0x00000001, DF_IO1);
+	writel(0x00000001, DF_IO9);
+	writel(0x00000001, DF_IO2);
+	writel(0x00000001, DF_IO10);
+	writel(0x00000001, DF_IO3);
+	writel(0x00000001, DF_IO11);
+	writel(0x00000001, DF_IO4);
+	writel(0x00000001, DF_IO12);
+	writel(0x00000001, DF_IO5);
+	writel(0x00000001, DF_IO13);
+	writel(0x00000001, DF_IO6);
+	writel(0x00000001, DF_IO14);
+	writel(0x00000001, DF_IO7);
+	writel(0x00000001, DF_IO15);
+
+	writel(0x1901, DF_nWE);
+	writel(0x1901, DF_nRE);
+	writel(0x1900, DF_CLE_nOE);
+	writel(0x1901, DF_ALE_nWE1);
+	writel(0x1900, DF_INT_RnB);
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+	/* set up GPIO Control Registers */
+	dfc_gpio_init();
+
+	/* turn on the NAND Controller Clock (104 MHz @ D0) */
+	writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
+
+#undef CONFIG_SYS_TIMING_TIGHT
+#ifndef CONFIG_SYS_TIMING_TIGHT
+	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tCH);
+	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tCS);
+	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tWH);
+	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tWP);
+	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tRH);
+	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tRP);
+	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+		 DFC_MAX_tR);
+	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+		   DFC_MAX_tWHR);
+	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+		  DFC_MAX_tAR);
+#else /* this is the tight timing */
+
+	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+		  DFC_MAX_tCH);
+	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+		  DFC_MAX_tCS);
+	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+		  DFC_MAX_tWH);
+	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+		  DFC_MAX_tWP);
+	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+		  DFC_MAX_tRH);
+	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+		  DFC_MAX_tRP);
+	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+		 DFC_MAX_tR);
+	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+		   DFC_MAX_tWHR);
+	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+		  DFC_MAX_tAR);
+#endif /* CONFIG_SYS_TIMING_TIGHT */
+
+
+	DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+	/* tRP value is split in the register */
+	if(tRP & (1 << 4)) {
+		tRP_high = 1;
+		tRP &= ~(1 << 4);
+	} else {
+		tRP_high = 0;
+	}
+
+	writel((tCH << 19) |
+		(tCS << 16) |
+		(tWH << 11) |
+		(tWP << 8) |
+		(tRP_high << 6) |
+		(tRH << 3) |
+		(tRP << 0),
+		NDTR0CS0);
+
+	writel((tR << 16) |
+		(tWHR << 4) |
+		(tAR << 0),
+		NDTR1CS0);
+
+	/* If it doesn't work (unlikely) think about:
+	 *  - ecc enable
+	 *  - chip select don't care
+	 *  - read id byte count
+	 *
+	 * Intentionally enabled by not setting bits:
+	 *  - dma (DMA_EN)
+	 *  - page size = 512
+	 *  - cs don't care, see if we can enable later!
+	 *  - row address start position (after second cycle)
+	 *  - pages per block = 32
+	 *  - ND_RDY : clears command buffer
+	 */
+	/* NDCR_NCSX |		/\* Chip select busy don't care *\/ */
+
+	writel(NDCR_SPARE_EN |		/* use the spare area */
+		NDCR_DWIDTH_C |		/* 16bit DFC data bus width  */
+		NDCR_DWIDTH_M |		/* 16 bit Flash device data bus width */
+		(2 << 16) |		/* read id count = 7 ???? mk@tbd */
+		NDCR_ND_ARB_EN |	/* enable bus arbiter */
+		NDCR_RDYM |		/* flash device ready ir masked */
+		NDCR_CS0_PAGEDM |	/* ND_nCSx page done ir masked */
+		NDCR_CS1_PAGEDM |
+		NDCR_CS0_CMDDM |	/* ND_CSx command done ir masked */
+		NDCR_CS1_CMDDM |
+		NDCR_CS0_BBDM |		/* ND_CSx bad block detect ir masked */
+		NDCR_CS1_BBDM |
+		NDCR_DBERRM |		/* double bit error ir masked */
+		NDCR_SBERRM |		/* single bit error ir masked */
+		NDCR_WRDREQM |		/* write data request ir masked */
+		NDCR_RDDREQM |		/* read data request ir masked */
+		NDCR_WRCMDREQM,		/* write command request ir masked */
+		NDCR);
+
+
+	/* wait 10 us due to cmd buffer clear reset */
+	/*	wait(10); */
+
+	nand->cmd_ctrl = dfc_hwcontrol;
+/*	nand->dev_ready = dfc_device_ready; */
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->ecc.layout = &delta_oob;
+	nand->options = NAND_BUSWIDTH_16;
+	nand->waitfunc = dfc_wait;
+	nand->read_byte = dfc_read_byte;
+	nand->read_word = dfc_read_word;
+	nand->read_buf = dfc_read_buf;
+	nand->write_buf = dfc_write_buf;
+
+	nand->cmdfunc = dfc_cmdfunc;
+	nand->badblock_pattern = &delta_bbt_descr;
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/zylonite/zylonite.c b/u-boot/board/zylonite/zylonite.c
new file mode 100644
index 0000000..749a40f
--- /dev/null
+++ b/u-boot/board/zylonite/zylonite.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif